SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME

According to one embodiment, a method for manufacturing a semiconductor memory device is disclosed. A trench is formed in a structure on a body. The structure includes first and second films alternately stacked in a first direction. A part of the first films is removed through the trench. One of the first films has a first side surface. Other one of the first films having a second side surface is positioned between the one of the first films and the body. The removing makes a distance between the trench and the second side surface shorter than a distance between the trench and the first side surface. A first space formed by the removing is filled with an insulating material. The first films are removed via a hole formed in the structure. A second space formed by the removing the first films is filled with a conductive material.

FIELD

Embodiments described later relate to a semiconductor memory device and a method for manufacturing the same.

BACKGROUND

In the semiconductor memory device, there is desired an increase in memory capacity.

DETAILED DESCRIPTION

According to one embodiment, a method for manufacturing a semiconductor memory device is disclosed. The method can include forming a trench in a structure provided on a lower body. The structure includes a plurality of first films and a plurality of second films alternately stacked in a first direction crossing a surface of the lower body. The method further includes removing a part of the plurality of first films being exposed inside of the trench. One of the plurality of first films has a first side surface crossing a second direction perpendicular to the first direction. Other one of the plurality of first films is positioned between the one of the plurality of first films and the lower body. The other one of the plurality of first films has a second side surface crossing the second direction. The removing the part of the plurality of first films makes a second distance shorter than a first distance. The first distance is between the trench and the first side surface in the second direction. The second distance is between the trench and the second side surface in the second direction. The method further includes filling a first space formed by the removing the part of each of the plurality of first films with an insulating material. The method further includes forming a hole in the structure after the filling with the insulating material, and removing the plurality of first films via the hole. The method further includes filling a second space formed by the removing the first films with a conductive material to form a plurality of conductive films arranged in the first direction.

The drawings are schematic and conceptual, and the relationships between the thickness and width of portions, the size ratio among portions, etc., are not necessarily the same as the actual values thereof. Further, the dimensions and proportions may be illustrated differently among drawings, even for identical portions.

In the present specification and drawings, the same elements as those described previously with reference to earlier figures are labeled with like reference numerals, and the detailed description thereof is omitted as appropriate.

First Embodiment

FIG. 1is a schematic cross-sectional view illustrating a semiconductor memory device according to a first embodiment.

As shown inFIG. 1, the semiconductor memory device111according to the embodiment includes a stacked body ML, semiconductor pillars50, and memory films54.

The stacked body ML includes a plurality of conductive layers21and a plurality of insulating layers22which are alternately stacked.

The stacking direction (a first direction) of the conductive layers21and the insulating layers22is defined as a Z-axis direction. One of directions perpendicular to the Z-axis direction is defined as an X-axis direction. The direction perpendicular to the Z-axis direction and the X-axis direction is defined as a Y-axis direction.

The stacked body ML is provided on a surface10u(e.g., an upper surface) of a lower body10. The lower body10can also be a substrate. The lower body10can also be a layer (e.g., an insulating layer) provided on a substrate. The lower body10may be a conductive layer. The lower body10may include a conductive layer. The surface10uof the lower body10extends along, for example, an X-Y plane. The first direction crosses the surface10u. The first direction is substantially perpendicular to the surface10u.

For example, the plurality of conductive layers21include a first conductive layer21a, a second conductive layer21b, a third conductive layer21c, a fourth conductive layer21d, and so on.

These conductive layers are arranged along the Z-axis direction in this order. These conductive layers are separated from each other in the Z-axis direction.

For example, the plurality of insulating layers22include a first insulating layer22a, a second insulating layer22b, a third insulating layer22c, a fourth insulating layer22d, a fifth insulating layer22e, and so on. These insulating layers are arranged along the Z-axis direction in this order. These insulating layers are separated from each other in the Z-axis direction.

The semiconductor pillars50each extends in the first direction through the stacked body ML.

The memory film54is provided between the semiconductor pillar50and the stacked body ML. The memory film54includes, for example, a charge storage film, and the like. An example of the memory film54will be described later.

Memory cells MC are formed between the plurality of conductive layers21and the semiconductor pillar50.

On the lower body10, an area provided with the memory cells MC corresponds to a memory region MR. On the lower body10, there is further provided a connection region CR. The plurality of conductive layers21extend from the memory region MR to the connection region CR. In the connection region CR, a plurality of connection sections CP (e.g., first through fourth connection sections CP1through CP4) are provided. The plurality of connection sections CP extend along the first direction. One of the plurality of connection sections CP is electrically connected to one of the plurality of conductive layers21.

In the embodiment, the state in which a first conductor is electrically connected to a second conductor includes the state in which the first conductor and the second conductor have physical contact with each other. The state in which the first conductor is electrically connected to the second conductor includes the state in which a third conductor (including a semiconductor) is inserted between the first conductor and the second conductor and a current flows between the first conductor and the second conductor via the third conductor. It is also possible to provide a plurality of third conductors in a current path between the first conductor and the second conductor.

The plurality of conductive layers21form, for example, word lines. At least a part of the semiconductor pillar50forms, for example, a channel. In addition, a bit line, a source line, and on the like are provided. An example of these interconnections will be described later.

In this example, two connection regions CR are provided between two memory regions MR.

In the connection regions CR, the positions of end portions of the plurality of conductive layers21vary to form a stepped shape. In other words, the distances between the end portions of the plurality of conductive layers21and the memory films54descend as the distance from the lower body10increases. By causing the shape of the plurality of conductive layers21to have the stepped shape, connection with the connection sections CP becomes easy. On the part having the stepped shape, there is provided an insulating section66L.

In this example, a central portion in the thickness direction (the first direction) of the end surface of each of the plurality of conductive layers21in the connection region CR recedes from ends in the thickness direction thereof as shown inFIG. 1. In other words, in one end surface of the conductive layer21, the ends in the thickness direction project from the central portion in the thickness direction.

Hereinafter, the configuration will be described.

As described above, the stacked body ML includes the first insulating layer22a, the second insulating layer22b, and the first conductive layer21a. The second insulating layer22bis separated from the first insulating layer22ain the first direction. The first conductive layer21ais provided between the first insulating layer22aand the second insulating layer22b.

The first conductive layer21aincludes an end surface21as. The end surface21asis separated from the memory film54in a second direction (the X-axis direction in this example) crossing the first direction. The end surface21ascrosses the second direction. The end surface21asincludes first through third regions r1through r3. The first region r1is located on the first insulating layer22aside. The second region r2is located on the second insulating layer22bside.

In other words, the position in the first direction (the Z-axis direction) of the first region r1is located between the position in the first direction of the third region r3and the position in the first direction of the first insulating layer22a. The position in the first direction of the second region r2is located between the position in the first direction of the third region r3and the position in the first direction of the second insulating layer22b.

A third distance d3along a second direction (the X-axis direction) between the third region r3and the memory film54is shorter than a first distance d1along the second direction between the first region r1and the memory film54. In other words, the third region r3(the central portion of the first conductive layer21a) recedes from the first region r1.

In the example, in addition, the third distance d3is shorter than a second distance d2along the second direction between the second region r2and the memory film54.

Due to such a configuration, the contact area between the first conductive layer21aand the first insulating layer22aincreases, for example. There exists a reference example in which, for example, the third distance d3is equal to the first distance d1, and at the same time, is equal to the second distance d2. In the case in which the third distance d3is equal between the configuration illustrated inFIG. 1and the reference example, the contact area between the first conductive layer21aand the first insulating layer22abecomes larger in the configuration illustrated inFIG. 1compared to the reference example. Thus, for example, the adhesiveness between the conductive layers and the insulating layers, for example, is improved. Stable connection can be obtained. For example, the area of the connection regions CR can be reduced. Therefore, for example, the area of the memory region MR can be enlarged. Thus, the memory capacity can be increased.

Hereinafter, an example of a method for manufacturing a semiconductor memory device111will be described.

FIG. 2AthroughFIG. 2DandFIG. 3AthroughFIG. 3Care schematic cross-sectional views illustrating a method for manufacturing the semiconductor memory device according to the first embodiment.

As shown inFIG. 2A, a structure SB is formed on the lower body10. The structure SB is provided on the surface10uof the lower body10. The structure SB includes a plurality of first films61and a plurality of second films62alternately stacked in the first direction. The first direction crosses the surface10uof the lower body10. The first direction is substantially perpendicular to the surface10u. The first films61each includes, for example, silicon nitride. The second films62each includes, for example, silicon oxide.

As shown inFIG. 2B, a trench65his formed in the structure SB. On the inner side of the trench65hof the structure SB, the plurality of first films61and the plurality of second films62are exposed.

As shown inFIG. 2C, a part of each of the plurality of first films61exposed on the inner side of the trench65his removed. The process of removing a part of each of the plurality of first films61includes removing a part of each of the first films61using wet etching. In the case in which the first films61each includes silicon nitride, a phosphoric acid solution, for example, is used as an etchant. Etching is performed using the etchant supplied from an opening section of the trench65h.

On this occasion, as shown inFIG. 2C, the degree of removing the first film61in a part near to an upper side (the opening section) of the trench65his higher than the degree of removing the first film61in a lower side part of the trench65h. The receding amount of the first film61in the part near to the upper side of the trench65his greater than the receding amount of the first film61in the lower side part of the trench65h. For example, in the part near to the opening section, the concentration of the component causing a contribution to etching in the etchant is higher than that in the part far from the opening section. Thus, such a difference in etching amount can be obtained.

For example, one (the first film61p) of the plurality of first films61has a first side surface61pacrossing the second direction (the X-axis direction) perpendicular to the first direction. Another (the first film61q) of the plurality of first films61is located between the one (the first film61p) thereof and the lower body10. Another (the first film61q) thereof has a second side surface61qscrossing the second direction. A second distance L2along the second direction between the trench65hand the second side surface61qsis shorter than a first distance L1along the second direction between the trench65hand the first side surface61pa.

As described above, in the method, removing a part of each of the plurality of first films61is performed. The positions of the end portions of the plurality of first films61vary to form a stepped shape.

As shown inFIG. 2D, etching is further continued. Thus, the positions of the end portions of the plurality of first films61form a predetermined stepped shape. Thus, a space (a first space65a) is formed in an area from which a part of each of the plurality of first films61is removed.

As shown inFIG. 3A, the first space65a(the space formed by the removing a part of each of the plurality of first films61) is filled with an insulating material66. The insulating material66is, for example, silicon oxide. The trench65his also filled with the insulating material66. The insulating film66forms an insulating section66L.

As shown inFIG. 3B, the semiconductor pillars50penetrating the structure SB are formed. In this process, for example, memory holes each piercing the structure SB in the first direction are formed, and then the memory film54is formed on an inner wall surface of each of the memory holes. Then, after forming the memory films54, the semiconductor pillar50extending in the first direction is formed in the remaining space of the memory hole. In such a manner as described above, the semiconductor pillars50are formed.

After forming the semiconductor pillars50(i.e., after the process of filling the space with the insulating material66), a hole SLT is formed in the structure SB. The hole SLT can also be a trench. The hole SLT can also be a slit. The plurality of first films61are removed via the hole SLT.

Further, a second space65bformed by the removing the first films61is filled with a conductive material21M. Thus, the plurality of conductive layers21arranged in the first direction are formed from the conductive material21M. The second films62respectively form the insulating layers22. As the conductive material21M, there is used, for example, tungsten. In the embodiment, the conductive material21M is arbitrary.

As shown inFIG. 3C, the second films62(the insulating layers22) and the insulating material66are partially removed to form contact holes. The contact holes reach the plurality of conductive layers21, and each extends in the first direction. The contact holes are filled with a conductive material. Thus, the connection sections CP are formed.

In the first manufacturing method described above, when the plurality of first films61are etched via the trench65h, there is used the fact that the etching rate differs along the height direction (the first direction). The difference in the etching rate is caused by a difference in concentration of the component causing a contribution to etching in the etchant between, for example, an area near to the opening section of the trench65hand a deep area of the trench65h.

For example, the etchant is used in the process of removing a part of each of the plurality of first films61. The etching rate of the one (the first film61p) of the plurality of first films61with respect to the etchant is higher (faster) than the etching rate of the other one (the first film61q) of the plurality of first films61. The plurality of plurality of first films61are processed to have the stepped shape using such a difference in etching rate.

Thus, for example, the process becomes simple. For example, a variation in processing is suppressed. For example, the accuracy of the positions of the end portions of the first films61can be improved. Thus, the connection regions CR can be narrowed. Thus, the semiconductor memory device with a high memory capacity can be manufactured.

In contrast, there exists a reference example of forming a mask on the structure SB including the plurality of first films61and the plurality of second films62stacked alternately, and then alternately repeating processing of the structure SB via the mask and slimming of the mask. In this reference example, the number of processes is large. Further, in some cases, the accuracy of the positions of the end portions of the plurality of first films61is not sufficient due to the variation in processing.

In the first manufacturing method according to the embodiment, the number of processes can be reduced. Further, the variation in processing is suppressed, and thus, high positional accuracy can be obtained.

The semiconductor memory device111described above can also be manufactured using a second manufacturing method described below.

FIG. 4AthroughFIG. 4Dare schematic cross-sectional views illustrating another method of manufacturing the semiconductor memory device according to the first embodiment.

Also in this example, there is provided the structure SB on the lower body10. In the second manufacturing method, the following process is performed between the process (seeFIG. 2B) of forming the trench65hand the process (seeFIG. 2C) of removing a part of each of the plurality of first films61.

As shown inFIG. 4A, a third film63is formed on a sidewall65hsof the trench65hof the structure SB. The third film63can also be formed on an upper surface of the structure SB. The third film63includes, for example, substantially the same material as that of the first films61. The third film63includes, for example, silicon nitride. The third film63is formed using, for example, an atomic layer deposition (ALD) method.

As shown inFIG. 4B, the third film63is processed. This processing is performed between the process (FIG. 3A) of forming the third film and the process (FIG. 2C) of removing a part of each of the plurality of first films61. In the processing of the third film63, a length t1(the thickness) along the second direction (the X-axis direction) of the third film63at a first position p1distant from the lower body10is made shorter than a length t2(the thickness) along the second direction of the third film63at a second position p2located between the first position p1and the lower body10.

For example, the etching rate of the third film63in the part near to the opening section of the trench65his higher (faster) than the etching rate of the third film63deep in the trench65h. Thus, the slimming described above (a variation in length, a variation in thickness) is achieved.

As shown inFIG. 4C, in the case of continuing the removal (etching) of the third film63, a part of each of the plurality of first films61(in a part corresponding to an upper layer area) is exposed in the part from which the third film63has been removed. The part of each of the first films61is removed at the same time as the removing the third film63.

Specifically, the process of removing a part of each of the plurality of first films61includes a process of removing the part corresponding to the first position p1of the third film63, and then removing at least a part of one of the plurality of first films61, which has been exposed by the removing the part corresponding to the first position p1. Further, the process of removing a part of each of the plurality of first films61includes a process of removing the part corresponding to the second position p2of the third film63after the removing the part corresponding to the first position p1, and then removing at least a part of another of the plurality of first films61, which has been exposed by the removing the part corresponding to the second position p2. As described above, the third film63is gradually removed along the first direction, and a part of each of the first films61having been exposed by the removal is removed in sequence.

In this example, the thickness along the second direction of the third film63is varied, and the third film63is gradually removed along the first direction. Thus, the timing of starting the removal (etching) of a part of each of the plurality of first films61is controlled. The time of starting the removal (etching) of a part of each of the plurality of first films61varies along the first direction.

Thus, as shown inFIG. 4D, the end portions of the plurality of first films61are processed to form the stepped shape. Subsequently, by performing, for example, the process described with reference toFIG. 3AthroughFIG. 3C, the semiconductor memory device111can be formed.

Also in the second manufacturing method, the number of processes can be reduced. Further, the variation in processing is suppressed, and thus, high positional accuracy can be obtained. In the second manufacturing method, slimming of the third film63is performed. By using the third film63, the variation in processing of the plurality of plurality of first films61can be suppressed. Thus, higher accuracy can be obtained.

The semiconductor memory device111described above can also be manufactured using a third manufacturing method described below.

FIG. 5AthroughFIG. 5Dare schematic cross-sectional views illustrating another method of manufacturing the semiconductor memory device according to the first embodiment.

Also in this example, there is provided the structure SB on the lower body10. In the third manufacturing method, the following process is performed between the process (seeFIG. 2B) of forming the trench65hand the process (seeFIG. 2C) of removing a part of each of the plurality of first films61.

As shown inFIG. 5A, the third film63is formed in the trench65h. The third film63can also be formed on the upper surface of the structure SB. The third film63includes, for example, substantially the same material as that of the first films61. The third film63includes, for example, silicon nitride.

As shown inFIG. 5B, a part of the third film63is removed by etching, and then a part of each of the first films61, which have been exposed by the removing a part of the third film63, is removed by etching.

Further, as shown inFIG. 5C, the third film63is further removed by etching. Thus, another part of the plurality of first films61is exposed. By the etching of the third film63, the removing the first films61having been newly exposed is started.

Specifically, in the process of removing a part of each of the plurality of first films61, a part of the third film63is removed to cause the third film63to recede along the first direction. A process of removing at least a part of one of the plurality of first films61having been exposed by the recession of the third film63is included. Further, the process of removing a part of each of the plurality of first films61further includes a process of causing the third film63to further recede after the recession of the third film63described above, and then removing at least a part of another of the plurality of first films61, which has been exposed by the further recession of the third film63.

In this example, the third film63is gradually removed along the first direction. Thus, the timing of starting the removal (etching) of a part of each of the plurality of first films61is controlled. The time of starting the removal (etching) of a part of each of the plurality of first films61varies along the first direction.

Thus, as shown inFIG. 5D, the end portions of the plurality of first films61are processed to form the stepped shape. Subsequently, by performing, for example, the process described with reference toFIG. 3AthroughFIG. 3C, the semiconductor memory device111can be formed.

Also in the third manufacturing method, the number of processes can be reduced. Further, the variation in processing is suppressed, and thus, high positional accuracy can be obtained. In the third manufacturing method, the third film63is provided, and the third film63is made to recede in sequence to expose the plurality of first films61in sequence. Thus, the variation in processing of the plurality of first films61can be suppressed. Thus, higher accuracy can be achieved.

The speed of the recession along the first direction of the third film63has an influence on the speed of the sequential exposure of the plurality of first films61. In the case in which the length in the second direction of the third film63is excessively short, the space existing after the third film63is removed becomes excessively narrow, and the etching time for the first films61becomes excessively long, for example. If the length in the second direction of the third film63is excessively long, the variation in recession amount between the plurality of first films61becomes large, for example.

(Another Semiconductor Memory Device According to First Embodiment)

FIG. 6is a schematic cross-sectional view illustrating another semiconductor memory device according to the first embodiment.

As shown inFIG. 6, a semiconductor memory device112according to the embodiment also includes the stacked body ML, the semiconductor pillars50, and the memory films54. In the semiconductor memory device112, in the connection regions CR, the positions (the positions in the X-axis direction) of the plurality of end portions of the insulating layers22follow the positions (the positions in the X-axis direction) of the end portions of the conductive layers21provided on the lower side (the lower body10side) of the plurality of insulating layers22. The rest of the configuration is substantially the same as the configuration of the semiconductor memory device111, and therefore, the description thereof will be omitted. The configuration of the semiconductor memory device112is formed using, for example, a fourth manufacturing method described below.

FIG. 7AthroughFIG. 7Care schematic cross-sectional views illustrating another method of manufacturing the semiconductor memory device according to the first embodiment.

As shown inFIG. 7A, the end portions of the plurality of first films61are processed to form the stepped shape. This configuration is the configuration described with reference toFIG. 2D. This configuration can be formed using, for example, either of the first through third manufacturing methods.

In the fourth manufacturing method, the following process is performed between the process (seeFIG. 2BorFIG. 7A) of removing a part of each of the plurality of first films61and the process (seeFIG. 3A) of filling the space with the insulating material66.

As shown inFIG. 7B, a part of each of the plurality of second films62is removed. The part of each of the plurality of second films62is a part, which is not sandwiched by the plurality of first films61in the first direction (the Z-axis direction). On this part (the part not sandwiched by the plurality of first films61in the first direction) of the second film62, the plurality of first films61are not provided. This part of the second film62is not covered with either of the plurality of first films61. Such a part of each of the second films62is removed. In this removal, reactive ion etching (RIE), for example, is used. For example, anisotropic etching is performed.

Thus, the positions (the positions in the X-axis direction) of the respective end portions of the plurality of second films62substantially coincide with the positions (the positions in the X-axis direction) of the end portions of the first films61provided on the lower side (the lower body10side) of the plurality of second films62.

As shown inFIG. 7C, the space thus formed is filled with the insulating material66. Therefore, the process (seeFIG. 3AorFIG. 7C) of filling the space with the insulating material66includes further filling the space, which has been formed by the removing the part (the part not sandwiched by the plurality of first films61in the first direction) described above of the second film62, with the insulating material66.

As described above, in the fourth manufacturing method, a part (a midair part) of each of the second films62is removed after the process of removing a part of each of the plurality of first films61. The midair parts are parts of the second films62, which have become in the state of being separated from each other in the midair by the removing a part of each of the first films61. By removing the midair part of each of the second films62, the second films62can be inhibited from being broken at unwanted parts. Thus, more stable processing can be achieved.

Also in the fourth manufacturing method, the number of processes can be reduced. Further, the variation in processing is suppressed, and thus, high positional accuracy can be obtained. In the fourth manufacturing method, the midair part of each of the second films62is removed. Thus, for example, the accuracy of the second films62and the first films61is improved. The second films62can be inhibited from being broken at unwanted positions. For example, foreign matters can be inhibited from being generated. For example, the yield ratio can be improved.

(Another Semiconductor Memory Device According to First Embodiment)

FIG. 8is a schematic cross-sectional view illustrating another semiconductor memory device according to the first embodiment.

As shown inFIG. 8, a semiconductor memory device113according to the embodiment also includes the stacked body ML, the semiconductor pillars50, and the memory films54. In the semiconductor memory device113, the shape of the end portion of the first conductive layer21ais different from that of the semiconductor memory device111. The rest of the configuration is substantially the same as the configuration of the semiconductor memory device111, and therefore, the description thereof will be omitted.

In the semiconductor memory device113, an end surface21as(a surface crossing the second direction) of the first conductive layer21aincludes the first through third regions r1through r3. The position in the first direction (the Z-axis direction) of the first region r1is located between the position in the first direction of the third region r3and the position in the first direction of the first insulating layer22a. The position in the first direction of the second region r2is located between the position in the first direction of the third region r3and the position in the first direction of the second insulating layer22b.

Also in this example, the third distance d3along a second direction (the X-axis direction) between the third region r3and the memory film54is shorter than the first distance d1along the second direction between the first region r1and the memory film54. In other words, the third region r3(the central portion of the first conductive layer21a) recedes from the first region r1.

Further, in the semiconductor memory device113, the third distance d3is longer than the second distance d2along the second direction between the second region r2and the memory film54. On this occasion, between the second insulating layer22band the lower body10, there is disposed the first insulating layer22a. In other words, the first region r1in the end surface21asof the first conductive layer21ais located on the lower body10side (the lower side), and the second region r2is located on the upper side. In such a configuration, the distance between the end surface21asand the memory film54decreases along a direction from the bottom toward the top. In other words, the third distance d3is shorter than the first distance d1, and the second distance d2is shorter than the third distance d3. In other words, the end surface21asis tilted. The end surface21ashas a positive tapered shape.

Such a configuration is formed using, for example, the fourth manufacturing method described above.

In other words, in the process (removing a part of each of the plurality of second films62) described with reference toFIG. 7Bdescribed above, for example, a part of the first film61adjacent to the second film62is removed together with the second film62. Thus, in the end portion of the first film61, the position of the upper part recedes from the position of the lower part in some cases. In these cases, the configuration described above with respect to the semiconductor memory device113can be obtained.

In the semiconductor memory device113, since the end surface21asof the first conductive layer21ahas the positive tapered shape, breakage in the end portion of the first conductive layer21ais suppressed. Thus, high positional accuracy can be obtained. Foreign matters are inhibited from being generated, and the yield ratio is improved.

(Another Semiconductor Memory Device According to First Embodiment)

FIG. 9is a schematic cross-sectional view illustrating another semiconductor memory device according to the first embodiment.

As shown inFIG. 9, a semiconductor memory device114according to the embodiment also includes the stacked body ML, the semiconductor pillars50, and the memory films54. In the semiconductor memory device114, pillar sections67each extending in the first direction are further provided in the connection regions CR. In this example, the pillar sections67each supports the plurality of insulating layers22(the plurality of second films62) during the process. The rest of the configuration is substantially the same as the configuration of the semiconductor memory device111, and therefore, the description thereof will be omitted. The semiconductor memory device114is formed using, for example, a fifth manufacturing method described below.

FIG. 10AthroughFIG. 10Care schematic cross-sectional views illustrating another method of manufacturing the semiconductor memory device according to the first embodiment.

As shown inFIG. 10A, the fifth manufacturing method further includes a process of forming the pillar sections67each piercing the structure SB in the first direction. This process is performed before, for example, the process (see, e.g.,FIG. 2B) of forming the trench65hin the structure SB. The trench65his formed so as to be separated from the pillar sections67.

The pillar sections67are each formed by forming a hole extending in the first direction in the structure SB, and then forming a stacked film of, for example, a silicon oxide film and a silicon nitride film in the hole. As described later, it is also possible to perform at least a part of the formation of the pillar sections67at the same time as at least a part of the formation of the memory films54.

As shown inFIG. 10B, a part of each of the plurality of first films61is removed. A part having a stepped shape is formed in the end portions of the plurality of first films61. In this process, the process described with respect to the first through third manufacturing methods, for example, is performed.

As shown inFIG. 10B, by the removing a part of each of the plurality of first films61, parts of the plurality of second films62become in the state of being separated from each other in the midair. In other words, the midair part of each of the second films62is formed. The midair part is held by the pillar sections67. Thus, the midair part can be inhibited from being broken.

As shown inFIG. 10C, the first space65a, which has been formed by removing a part of each of the plurality of first films61, is filled with the insulating material66. Subsequently, the processes described with respect toFIG. 3BandFIG. 3Care performed to form the semiconductor memory device114.

FIG. 11AthroughFIG. 11Care schematic cross-sectional views illustrating another method of manufacturing the semiconductor memory device according to the first embodiment.

As shown inFIG. 11A, the semiconductor pillars50and the memory films54extending in the first direction are provided to the structure SB. The memory film54is provided between the semiconductor pillar50and the structure SB. Meanwhile, the pillar sections67each piercing the structure SB in the first direction is provided. The pillar sections67each includes, for example, a core section67aextending in the first direction, and an intermediate section67bprovided between the core section67aand the structure SB. The core section67aincludes, for example, the same material as the material included in the semiconductor pillar50. The intermediate section67bincludes, for example, at least a part of the material included in the memory film54. The forming the pillar sections67can also be performed at the same time as, for example, the formation of the memory films54and the semiconductor pillars50. For example, the intermediate section67bcan also include a stacked film of a film including silicon nitride and a film including silicon oxide.

As shown inFIG. 11B, a part of each of the plurality of first films61is removed. A part having a stepped shape is formed in the end portions of the plurality of first films61. In this process, the process described with respect to the first through third manufacturing methods, for example, is performed.

Also in this case, by the removing a part of each of the plurality of first films61, parts of the plurality of second films62become in the state of being separated from each other in the midair. The midair part of each of the second films62is formed. The midair part is held by the pillar sections67. Thus, the midair part can be inhibited from being broken.

As shown inFIG. 11C, the first space65a, which has been formed by removing a part of each of the plurality of first films61, is filled with the insulating material66.

Subsequently, the process described with respect toFIG. 3Cis performed to form the semiconductor memory device114.

(Another Semiconductor Memory Device According to First Embodiment)

FIG. 12is a schematic cross-sectional view illustrating another semiconductor memory device according to the first embodiment.

As shown inFIG. 12, in a semiconductor memory device115according to the embodiment, there are also provided the pillar sections67. The rest of the configuration is substantially the same as the configuration of the semiconductor memory device113, and therefore, the description thereof will be omitted. The semiconductor memory device115is formed using, for example, a seventh manufacturing method described below.

FIG. 13AthroughFIG. 13Dare schematic cross-sectional views illustrating another method of manufacturing the semiconductor memory device according to the first embodiment.

As shown inFIG. 13A, the semiconductor pillars50and the memory films54extending in the first direction are formed in the structure SB. Further, the pillar sections67each piercing the structure SB in the first direction is formed. The pillar sections67each includes the core section67aextending in the first direction, and the intermediate section67bprovided between the core section67aand the structure SB.

As shown inFIG. 13B, a part of each of the plurality of first films61is removed. A part having a stepped shape is formed in the end portions of the plurality of first films61. In this process, the process described with respect to the first through third manufacturing methods, for example, is performed. The midair parts of the plurality of second films62are held by the pillar sections67.

As shown inFIG. 13C, the midair part of each of the plurality of second films62is removed. The anisotropic etching using RIE described with reference toFIG. 7B, for example, is performed. On this occasion, a part of the intermediate section67bincluded in the pillar section67can also be removed. In the case in which, for example, the intermediate section67bincludes the stacked film of the film including silicon nitride and the film including silicon oxide, a part of each of these films can also be removed.

As shown inFIG. 13D, the space thus formed is filled with the insulating material66.

As described above, the manufacturing method further includes a process (FIG. 13C) of removing at least a part of the portion (the midair part), which is not sandwiched by the plurality of first films61in the first direction, of each of the plurality of second films62between the process (FIG. 13B) of removing a part of each of the plurality of first films61and the process (FIG. 13D) of filling the space with the insulating material66.

The process of filling the space with the insulating material66includes further filling the space formed by the removing at least a part of the midair part (the part not sandwiched by the first films61) of the second films62with the insulating material66in addition to the first space65a(the area from which a part of each of the plurality of first films61is removed).

In this manufacturing method, the plurality of second films62are held by the pillar sections67in the process of removing a part of each of plurality of the first films61. Thus, the second films62are inhibited from being broken. Further, the midair part of each of the plurality of second films62is removed after removing a part of each of the plurality of first films61. Thus, the influence of the breakage of the second films62is further suppressed.

Second Embodiment

FIG. 14is a schematic cross-sectional view illustrating a semiconductor memory device according to a second embodiment.

As shown inFIG. 14, a semiconductor memory device121according to the embodiment also includes the stacked body ML, the semiconductor pillars50, and the memory films54. The stacked body ML includes the plurality of conductive layers21(e.g., the first through fourth conductive layers21athrough21d) and the plurality of insulating layers22(e.g., the first through fourth insulating layers22athrough22d). In this example, a central portion in the thickness direction of one end portion of each of the insulating layers22is receding. The rest of the configuration is substantially the same as, for example, the configuration of the semiconductor memory device111.

An example of the recession of the central portion of the end portion of each of the insulating layers22will be described. The stacked body ML includes the first conductive layer21a, the second conductive layer21b, and the first insulating layer22a.

The second conductive layer21bis separated from the first conductive layer21ain the first direction (the Z-axis direction). The first insulating layer22ais provided between the first conductive layer21aand the second conductive layer21b. The semiconductor pillars50each extends in the first direction through the stacked body ML. The memory film54is provided between the semiconductor pillar50and the stacked body ML. The memory cells MC are formed between the plurality of conductive layers21and the semiconductor pillar50.

The first insulating layer22aincludes an end surface22as.The end surface22asis separated from the memory film54in the second direction (the X-axis direction in this example) crossing the first direction. The end surface22ascrosses the second direction.

The end surface22asincludes fourth through sixth regions r4through r6. The position in the first direction of the fourth region r4is located between the position in the first direction of the sixth region r6and the position in the first direction of the first conductive layer21a. The position in the first direction of the fifth region r5is located between the position in the first direction of the sixth region r6and the position in the first direction of the second conductive layer21b.

As shown inFIG. 14, a sixth distance d6along the second direction between the sixth region r6and the memory film54is shorter than a fourth distance d4along the second direction between the fourth region r4and the memory film54.

In the example, the sixth distance d6is longer than a fifth distance d5along the second direction between the fifth region r5and the memory film54. In this configuration, between the second conductive layer21band the lower body10, there is disposed the first conductive layer21a. Therefore, the distance between the end surface22asand the memory film54is long on the lower body10side of the first insulating layer22a, and the distance decreases as the distance from the lower body10increases.

In other words, the distance between the end surface22asand the memory film54decreases along a direction from the bottom toward the top. In other words, the fourth distance d4is shorter than the sixth distance d6, and the fifth distance d5is shorter than the sixth distance d6. In other words, the end surface22asis tilted. The end surface22ashas a positive tapered shape.

In the semiconductor memory device121, since the end surface22asof the first insulating layer22ahas the positive tapered shape, breakage in the end portion of the first insulating layer22ais suppressed. Thus, high positional accuracy can be obtained. Foreign matters are inhibited from being generated, and the yield ratio is improved.

Also in this example, in the connection regions CR, the positions of end portions of the plurality of conductive layers21vary to form a stepped shape. In other words, the distances between the end portions of the plurality of conductive layers21and the memory film54decrease as the distance from the lower body10increases. By causing the shape of the plurality of conductive layers21to have the stepped shape, connection with the connection sections CP becomes easy. On the part having the stepped shape, there is provided the insulating section66L.

In the case in which the insulating layers22include silicon oxide, and the insulating section66L includes silicon oxide, the boundary between the insulating layers22and the insulating section66L is unclear in some cases.

In the semiconductor memory device121, the adhesion of the first insulating layer22acan be enhanced in, for example, a part including the end surface22asof the first insulating layer22a. For example, the connection regions CR can be made smaller. The memory capacity can be increased.

The semiconductor memory device121can be manufactured using, for example, an eighth manufacturing method described below.

FIG. 15AthroughFIG. 15DandFIG. 16AthroughFIG. 16Care schematic cross-sectional views illustrating a method of manufacturing the semiconductor memory device according to the second embodiment.

As shown inFIG. 15A, the structure SB is formed on the lower body10. The structure SB is provided on the surface10uof the lower body10. The structure SB includes the plurality of first films61and the plurality of second films62alternately stacked in the first direction. The first direction crosses the surface10uof the lower body10. The first direction is substantially perpendicular to the surface10u. The first films61each includes, for example, silicon nitride. The second films62each includes, for example, silicon oxide.

As shown inFIG. 15B, the trench65his formed in the structure SB. On the inner side of the trench65hof the structure SB, the plurality of first films61and the plurality of second films62are exposed.

As shown inFIG. 15C, a part of each of the plurality of second films62exposed on the inner side of the trench65his removed. This process can be performed by, for example, wet etching. In the case in which the second films62each includes silicon oxide, a hydrofluoric acid solution, for example, is used as an etchant of this process.

In this manufacturing method, the rate of the removing the second films62varies along the first direction.

For example, one (the second film62p) of the plurality of second films62includes a third side surface62ps. The third side surface62pscrosses the second direction (the X-axis direction) perpendicular to the first direction. Another (the second film62q) of the plurality of second films is located between the one (the second film62p) of the plurality of second films62and the lower body10. The second film62qhas a fourth side surface62qs. The fourth side surface62qscrosses the second direction (the X-axis direction). A fourth distance L4along the second direction between the trench65hand the fourth side surface62qsis shorter than a third distance L3along the second direction between the trench65hand the third side surface62ps.

In the process of removing a part of each of the plurality of second films62, the etching rate of the second films62at the position far from, the lower body10is higher (faster) than the etching rate of the second films62at the position near to the lower body10. Such a variation in the etching rate can be obtained from the fact that, for example, the etching rate of the etchant supplied to the trench65his high at the position far from the lower body10, and is low at the position near to the lower body10. For example, the concentration of the component causing a contribution to etching in the etchant is higher at the position far from the lower body10(i.e., the position near to the opening section of the trench65h) than at the position near to the lower body10. Thus, such a difference in etching rate as described above can be formed.

Thus, as shown inFIG. 15D, the stepped shape can be formed in the end portions of the plurality of second films62.

As shown inFIG. 16A, a part of each of the plurality of first films61is removed after the process of removing a part of each of the plurality of second films62. For example, an RIE process is performed. For example, an anisotropic etching is performed using RIE. After the process of removing a part of each of the plurality of second films62, the second film62is not provided on the part of each of the plurality of first films61. In other words, after the process of removing a part of each of the plurality of second films62, the part of each of the plurality of first films61is not covered with the second film62. By the removing the part of each of the plurality of first films61, each of the end portions of the plurality of first films61becomes to follow the end portion of the second film62adjacent to the upper side of the first film61. Thus, the stepped shape is provided to the plurality of first films61.

Subsequently, a part of each of the second films62is removed to expose the part of each of the first films61having been covered with the second film62.

As shown inFIG. 16B, a space (the first space65a) formed by the removing the part of each of the plurality of first films61and the removing the part of each of the plurality of second films62is filled with the insulating material66. The insulating material66forms an insulating section66L.

After the process of filling the space with the insulating material66described above, the holes SLT are formed in the structure SB, and then the plurality of first films61are removed via the holes SLT.

A space (a second space65b) formed by the removing the first films61is filled with a conductive material21M. Thus, the plurality of conductive layers21arranged in the first direction are formed. The second films62respectively form the insulating layers22.

In this example, in the process shown inFIG. 16C, the semiconductor pillars50and the memory films54are formed in the structure SB.

Subsequently, as shown inFIG. 16C, a part of the insulating material66is removed to form the contact holes. The contact holes reach each of the plurality of conductive layers21, and each extends in the first direction. The contact holes are filled with a conductive material. Thus, the connection sections CP are formed.

In the eighth manufacturing method described above, when the plurality of second films62are etched via the trench65h, there is used the fact that the etching rate differs along the height direction (the first direction). The difference in the etching rate is caused by a difference in concentration of the component causing a contribution to etching in the etchant between, for example, an area near to the opening section of the trench65hand a deep area of the trench65h.

For example, the etchant is used in the process of removing a part of each of the plurality of second films62. The etching rate of the one (the second film62p) of the plurality of second films62with respect to the etchant is higher (faster) than the etching rate of the other one (the second film62q) of the plurality of second films62.

The plurality of second films62are processed to have the stepped shape using such a difference in etching rate.

Thus, for example, the process becomes simple. For example, a variation in processing is suppressed. For example, the accuracy of the positions of the end portions of the plurality of second films62can be improved. Thus, the accuracy of the positions of the end portions of the plurality of first films61can be improved. Thus, the connection regions CR can be narrowed. Thus, the semiconductor memory device with a high memory capacity can be manufactured.

The semiconductor memory device121described above can also be manufactured using a ninth manufacturing method described below.

FIG. 17AthroughFIG. 17Dare schematic cross-sectional views illustrating another method of manufacturing the semiconductor memory device according to the second embodiment.

As shown inFIG. 17A, also in this example, there is provided the structure SB on the lower body10.

As shown inFIG. 17B, the third film63is formed on the sidewall65hsof the trench65hbetween the process (e.g.,FIG. 15B) of forming the trench65hand the process (see, e.g.,FIG. 15C) of removing a part of each of the second films62. The third film63includes, for example, the material included in the second films62. The second films62include, for example, silicon oxide, and the third film63includes silicon oxide.

Further, the third film63is processed between the process of forming the third film63and the process (FIG. 15C) of removing a part of each of the plurality of second films62. In the processing, the length t1along the second direction (the X-axis direction) of the third film63at the first position p1distant from the lower body10is made shorter than the length t2along the second direction of the third film63at the second position p2located between the first position p1and the lower body10.

In the processing of the third film63, there is used the fact that, for example, the etching rate of the third film63is high in the part near to the opening section of the trench65h.

As shown inFIG. 17C, a part of each of the plurality of second films62is gradually removed while gradually removing the third film63.

Specifically, the process of removing a part of each of the plurality of second films62includes a process of removing the part corresponding to the first position p1of the third film63, and then removing at least a part of one of the plurality of second films62, which has been exposed by the removing the part corresponding to the first position p1. Further, the process of removing a part of each of the plurality of second films62includes a process of removing the part corresponding to the second position p2of the third film63after the removing the part corresponding to the first position p1described above, and then removing at least a part of another of the second films62, which has been exposed by the removing the part corresponding to the second position p2.

Subsequently, the processes described with reference toFIG. 16AthroughFIG. 16C, for example, are performed. Thus, the semiconductor memory device121can be formed.

As described above, by the processing of the third film63, the time of start of the removing a part of each of the plurality of second films62is controlled. In other words, after starting the removing the second films62at the position distant from the lower body10, the removing the second films62at the position near to the lower body10is started.

Thus, the accuracy of the positions of the end portions of the plurality of second films62can be improved. The accuracy of the positions of the end portions of the plurality of first films61can be improved. Thus, the connection regions CR can be narrowed. Thus, the semiconductor memory device with a high memory capacity can be manufactured.

The semiconductor memory device121can also be manufactured using a tenth manufacturing method described below.

FIG. 18AthroughFIG. 18Dare schematic cross-sectional views illustrating another method of manufacturing the semiconductor memory device according to the second embodiment.

As shown inFIG. 18A, also in this example, there is provided the structure SB on the lower body10.

As shown inFIG. 18B, the third film63is formed in the trench15hbetween the process (FIG. 15B) of forming the trench65hand the process (FIG. 15C) of removing a part of each of the plurality of second films62.

As shown inFIG. 18C, a part of each of the plurality of second films62is removed while removing the third film63. Specifically, the process of removing a part of each of the plurality of second films62includes a process of removing a part of the third film63to cause the third film63to recede along the first direction, and then removing at least a part of one of the plurality of second films62, which has been exposed by the recession of the third film63. Further, the process of removing a part of each of the plurality of second films62further includes a process of causing the third film63to further recede after the recession of the third film63described above, and then removing at least a part of another of the plurality of second films62, which has been exposed by the further recession of the third film63.

Subsequently, the processes described with reference toFIG. 16AthroughFIG. 16C, for example, are performed. Thus, the semiconductor memory device121can be formed.

Also in this case, by the processing of the third film63, the time of start of the removing a part of each of the plurality of second films62is controlled. In other words, after starting the removing the second films62at the position distant from the lower body10, the removing the second films62at the position near to the lower body10is started.

Thus, the accuracy of the positions of the end portions of the plurality of second films62can be improved. The accuracy of the positions of the end portions of the plurality of first films61can be improved. Thus, the connection regions CR can be narrowed. Thus, the semiconductor memory device with a high memory capacity can be manufactured.

In the eighth through tenth manufacturing methods described above, it is also possible to form the pillar sections67piercing the structure SB in the first direction prior to the process of forming the trench65has described with reference toFIG. 10AthroughFIG. 10C, andFIG. 11AthroughFIG. 11C. In this case, the trench65his separated from the pillar sections67.

Furthermore, it is also possible for the eighth though tenth manufacturing method described above to further include a process of forming the memory cells MC. Specifically, a process of forming the memory holes piercing the structure SB in the first direction is performed prior to the process (e.g.,FIG. 15C) of removing the plurality of plurality of second films62. Further, the memory film54is formed on the inner wall surface of each of the memory holes. Further, after forming the memory films54, it is also possible to form the semiconductor pillar50extending in the first direction in the remaining space of each of the memory holes.

(Another Semiconductor Memory Device According to Second Embodiment)

FIG. 19is a schematic cross-sectional view illustrating another semiconductor memory device according to the second embodiment.

As shown inFIG. 19, a semiconductor memory device122according to the embodiment also includes the stacked body ML, the semiconductor pillars50, and the memory films54. In the semiconductor memory device122, the sixth distance d6along the second direction (the X-axis direction) between the sixth region r6and the memory film54is shorter than the fourth distance d4along the second direction between the fourth region r4and the memory film54in the end surface22asof the first insulating layer22a. Further, the sixth distance d6is shorter than a fifth distance d5along the second direction between the fifth region r5and the memory film54. The rest of the configuration is substantially the same as, for example, the configuration of the semiconductor memory device121.

As described above, in the embodiment, the end surface22asof the first insulating layer22acan be receding in the central portion.

FIG. 20AthroughFIG. 20Dare schematic cross-sectional views illustrating another method of manufacturing the semiconductor memory device according to the embodiment.

As shown inFIG. 20A, the structure SB is formed on the lower body10. The structure SB includes the plurality of first films61and the plurality of second films62alternately stacked along the Z-axis direction (the first direction). The first direction (the Z-axis direction) crosses the surface10uof the lower body10.

In this example, the characteristics of the plurality of first films61differ along the stacking direction (the first direction). For example, the plurality of first films61include film61athrough film61h.

As described later, a part of each of the plurality of first films61is removed. In the removal, etching using an etchant is performed. The etching rate of the film61anear to the lower body10is lower than the etching rate of the film61hfar from the lower body10.

For example, in the formation of the first films61, by varying the shape condition, the etching rate can be controlled. In the formation of the first films61, by varying the shape condition, the density of the first film61can be controlled. In the formation of the first films61, by varying the shape condition, an amount (the concentration) of a specific chemical bond included in the first film61can be controlled. For example, by varying the density, the etching rate varies. For example, by varying the amount of the specific chemical bond, the etching rate varies.

As described above, in this example, the etching rate of one (e.g., the film61hon the upper side) of the plurality of first films61with respect to an etchant used in the process of removing a part of each of the plurality of first films61is higher than the etching rate of another (e.g., the film61aon the lower side) of the plurality of first films61with respect to this etchant. The film61hon the upper side corresponds to, for example, the first film61p(seeFIG. 20C). The film61aon the lower side corresponds to, for example, the first film61q(seeFIG. 20C).

In other words, the characteristics of the film are changed between the first film61pand the first film61qso that a difference occurs in the removing a part of each of the plurality of first films61. For example, the density of one (the first film61p) of the plurality of first films61is lower than the density of another (the first film61q) of the plurality of first films61.

Thus, the etching rate of the first film61on the upper side becomes higher than the etching rate of the first film61on the lower side.

After forming such a structure SB, the trench65his formed as shown inFIG. 20B.

As shown inFIG. 20C, a part of each of the plurality of first films61exposed inside the trench65his removed. In the removing a part of each of the plurality of first films61, an amount of removing the first film61becomes large on the upper side compared to the lower side.

Thus, as shown inFIG. 20D, the stepped shape is formed in the plurality of first films61.

Subsequently, the processes described with reference toFIG. 3AthroughFIG. 3Care performed, and thus the semiconductor memory device111, for example, is formed.

In the eleventh manufacturing method, it is also possible to remove a part of each of the second films62in accordance with the stepped shape of the first films61. Further, it is also possible to process the first films61using the third film63. Further, it is also possible to provide the pillar sections67. Further, it is also possible to form the memory holes piercing the structure SB in the first direction, form the memory film54on the inner wall surface of each of the memory holes, and form the semiconductor pillar50extending in the first direction in the remaining space of each of the memory holes.

In the case in which the plurality of first films61each includes silicon nitride, the etching rate of the silicon nitride with respect to the wet etching varies in accordance with the density (concentration) of a specific chemical bond included in silicon nitride. For example, a silicon nitride film includes an N—H bond and an Si—N bond. For example, at peaks of an infrared spectroscopic analysis, the peaks corresponding respectively to these bonds are detected. The wave number corresponding to the N—H bond is, for example, 900 cm−1. The wave number corresponding to the Si—N bond is 3200 cm−1. The ratio of the intensity of the peak of the N—H bond to the intensity of the peak of the Si—N bond is defined as an NH/SiN ratio.

For example, a phosphoric acid solution is used as the etchant. The phosphoric acid concentration is, for example, 90%. In this case, the etching rate with the NH/SiN ratio of 2% is assumed as 1. In this case, the etching rate with the NH/SiN ratio of 3.5% is about 2. The etching rate with the NH/SiN ratio of 7% becomes about 3.

In such a manner, the etching rate varies in accordance with the NH/SiN ratio. This characteristic can be used.

For example, in the infrared spectroscopic analysis, one (the first film61p) of the plurality of first films61has a first peak corresponding to the bond (N—H bond) between hydrogen and nitrogen, and a second peak corresponding to the bond (Si—N bond) between silicon and nitrogen. In the infrared spectroscopic analysis, another (the first film61q) of the plurality of first films61has a third peak corresponding to the bond between hydrogen and nitrogen, and a fourth peak corresponding to the bond between silicon and nitrogen.

The ratio (NH/SiN ratio) of the intensity of the third peak to the intensity of the fourth peak in the first film61qon the lower side is lower than the ratio (NH/SiN ratio) of the intensity of the first peak to the intensity of the second peak in the first film61pon the upper side. Thus, the etching rate in the first film61qon the lower side becomes lower than the etching rate of the first film61pon the upper side.

FIG. 21AthroughFIG. 21Dare schematic cross-sectional views illustrating another method of manufacturing the semiconductor memory device according to the embodiment.

As shown inFIG. 21A, the structure SB is formed on the lower body10. The structure SB includes the plurality of first films61and the plurality of second films62alternately stacked along the Z-axis direction (the first direction).

In this example, the characteristics of the plurality of second films62differ along the stacking direction (the first direction). For example, the plurality of second films62includes film62athrough film62i.

As described later, a part of each of the plurality of second films62is removed. In the removal, etching using an etchant is performed. The etching rate of the film62anear to the lower body10is lower than the etching rate of the film62ifar from the lower body10.

For example, the density of one (the second film62p, seeFIG. 21C) of the plurality of second films62is lower than the density of another (the second film62q, seeFIG. 21C) of the plurality of second films62.

After forming such a structure SB, the trench65his formed as shown inFIG. 21B.

As shown inFIG. 21C, a part of each of the plurality of second films62exposed inside the trench65his removed. In the removing a part of each of the plurality of second films62, an amount of removing the second film62becomes large on the upper side compared to the lower side.

Thus, as shown inFIG. 21D, the stepped shape is formed in the plurality of second films62.

Subsequently, the processes described with reference toFIG. 16AthroughFIG. 16Care performed, and thus the semiconductor memory device121, for example, is formed.

In this twelfth manufacturing method, it is also possible to remove a part of each of the first films61in accordance with the stepped shape of the plurality of second films62. Further, it is also possible to process the second films62using the third film63. Further, it is also possible to provide the pillar sections67. Further, it is also possible to form the memory holes piercing the structure SB in the first direction, form the memory film54on the inner wall surface of each of the memory holes, and form the semiconductor pillar50extending in the first direction in the remaining space of each of the memory holes.

In the case in which the plurality of second films62each includes silicon oxide, the etching rate of the silicon oxide with respect to the wet etching varies in accordance with the concentration of carbon included in silicon oxide. For example, DHF is used as the etchant of etching of silicon oxide. The concentration of DHF is, for example, 0.5%. On this occasion, the etching rate with the carbon concentration in silicon oxide of 10×1022atm/cm3is assumed as 1. The etching rate with the carbon concentration in silicon oxide of 8.5×1022atm/cm3is about 2. The etching rate with the carbon concentration in silicon oxide of 7×1022atm/cm3is about 3.

In such a manner, the etching rate varies in accordance with the carbon concentration in silicon oxide. This characteristic can be used.

Specifically, in the twelfth manufacturing method, the plurality of second films62include silicon oxide. The carbon concentration of one (the second film62pon the upper side) of the plurality of second films62is lower than the carbon concentration of another (the second film62qon the lower side) of the plurality of second films62. Thus, the etching rate in the second film62qon the lower side becomes lower than the etching rate of the second film62pon the upper side.

In the manufacturing method, the configuration of the plurality of first films61different in characteristic from each other described with respect to the eleventh manufacturing method and slimming of the mask are combined with each other.

FIG. 22AthroughFIG. 22C,FIG. 23A, andFIG. 23Bare schematic cross-sectional views illustrating another method of manufacturing the semiconductor memory device according to the embodiment.

As shown inFIG. 22A, the structure SB is formed on the lower body10. The structure SB includes the plurality of first films61and the plurality of second films62alternately stacked along the Z-axis direction (the first direction).

In this example, the plurality of first films61are divided into a plurality of blocks BK. In one of the blocks BK, the characteristics of the plurality of first films61differ along the stacking direction (the first direction). For example, in one of the blocks BK, the plurality of first films61include film61athrough film61d. Such blocks BK are stacked on one another.

In one of the blocks BK, the etching rate of the film61anear to the lower body10is lower than the etching rate of the film61dfar from the lower body10.

For example, in the formation of the first films61, by varying the shape condition, the etching rate can be controlled. In the formation of the first films61, by varying the shape condition, the density of the first film61can be controlled. In the formation of the first films61, by varying the shape condition, an amount (the concentration) of a specific chemical bond included in the first film61can be controlled. For example, by varying the density, the etching rate varies. For example, by varying the concentration of a chemical bond, the etching rate varies.

As shown inFIG. 22B, a mask68is formed on the structure SB. Further, the mask68is processed, and then the trench65his formed in a part of the structure SB using the mask68.

As shown inFIG. 22C, the mask68is slimmed. The structure SB is processed using the mask68thus slimmed. Thus, a step is provided to the trench65h.

As shown inFIG. 23A, a part of each of the plurality of first films61exposed in the trench65his removed. On this occasion, in each of the plurality of blocks BK, the etching rate is made different between the plurality of first films61(the film61athrough the film61d). Thus, in each of the plurality of blocks BK, the recession of the first film61is made different between the first films61. Thus, the stepped shape can be provided to the plurality of first films61.

As shown inFIG. 23B, the space thus formed is filled with the insulating material66. Subsequently, the processes described with reference toFIG. 3AthroughFIG. 3C, for example, are performed. Thus, the semiconductor memory device is formed.

In the manufacturing method, it is also possible to remove a part of each of the second films62in accordance with the stepped shape of the first films61. Further, it is also possible to process the first films61using the third film63. Further, it is also possible to provide the pillar sections67. Further, it is also possible to form the memory holes piercing the structure SB in the first direction, form the memory film54on the inner wall surface of each of the memory holes, and form the semiconductor pillar50extending in the first direction in the remaining space of each of the memory holes.

(Another Semiconductor Memory Device According to Embodiment)

FIG. 24is a schematic cross-sectional view illustrating another semiconductor memory device according to the embodiment.

As shown inFIG. 24, in another semiconductor memory device131according to the embodiment, the positions (the positions along the second direction) of some end portions of the plurality of insulating layers22are made different in the first direction from each other. In this example, the insulating layers22include first through fifth insulating layers22athrough22e. The positions in the second direction (the X-axis direction) of the respective end portions (the end portions on the opposite side to the memory film54) of the first through third insulating layers22athrough22care different from the positions in the second direction (the X-axis direction) of the end portions (the end portions on the opposite side to the memory film54) of the fourth and fifth insulating layers22dand22e. The rest of the configuration is substantially the same as the configuration of the semiconductor memory device111, and therefore, the description thereof will be omitted.

Such a semiconductor memory device131is formed using, for example, the thirteenth manufacturing method described above. Also in the semiconductor memory device131, the memory capacity can be increased.

In the manufacturing method, the configuration of the plurality of second films62different in characteristic from each other described with respect to the twelfth manufacturing method and slimming of the mask are combined with each other.

FIG. 25AthroughFIG. 25C,FIG. 26A, andFIG. 26Bare schematic cross-sectional views illustrating another method of manufacturing the semiconductor memory device according to the embodiment.

As shown inFIG. 25A, the structure SB is formed on the lower body10. The structure SB includes the plurality of first films61and the plurality of second films62alternately stacked along the Z-axis direction (the first direction).

In this example, the plurality of second films62are divided into a plurality of blocks BK. In one of the blocks BK, the characteristics of the plurality of second films62differ along the stacking direction (the first direction). For example, in one of the blocks BK, the plurality of second films62include film62athrough film62d. Such blocks BK are stacked on one another.

In one of the blocks BK, the etching rate of the film62anear to the lower body10is lower than the etching rate of the film62dfar from the lower body10.

For example, in the formation of the second films62, by varying the shape condition, the etching rate can be controlled. In the formation of the second films62, by varying the shape condition, the density of the second film62can be controlled. In the formation of the second films62, by varying the shape condition, the concentration of carbon included in the second film62can be controlled. For example, by varying the carbon concentration, the etching rate varies.

As shown inFIG. 25B, the mask68is formed on the structure SB. Further, the mask68is processed, and then the trench65his formed in a part of the structure SB using the mask68.

As shown inFIG. 25C, the mask68is slimmed. The structure SB is processed using the mask68thus slimmed. Thus, a step is provided to the trench65h.

As shown inFIG. 26A, a part of each of the plurality of second films62exposed in the trench65his removed. On this occasion, in each of the plurality of blocks BK, the etching rate is made different between the plurality of second films62(the film62athrough the film62d). Thus, in each of the plurality of blocks BK, the recession of the second film62is made different between the second films62. Thus, the stepped shape can be provided to the plurality of second films62.

Subsequently, the plurality of first films61are processed in accordance with the stepped shape of the second films62as needed.

As shown inFIG. 26B, the space thus formed is filled with the insulating material66. Subsequently, the processes described with reference toFIG. 16AandFIG. 16C, for example, are performed. Thus, the semiconductor memory device is formed.

In the manufacturing method, it is also possible to process the second films62using the third film63. Further, it is also possible to provide the pillar sections67. Further, it is also possible to form the memory holes piercing the structure SB in the first direction, form the memory film54on the inner wall surface of each of the memory holes, and form the semiconductor pillar50extending in the first direction in the remaining space of each of the memory holes.

Hereinafter, one specific example of the semiconductor device according to the embodiment will be described.

FIG. 27is a schematic cross-sectional view illustrating a semiconductor memory device according to the embodiment.

FIG. 28AandFIG. 28Bare schematic cross-sectional views illustrating a part of the semiconductor memory device according to the embodiment.

As shown inFIG. 27, in a semiconductor memory device100according to the embodiment, there is provided a substrate10s(may be a conductive layer, for example). The substrate10sis, for example, a silicon substrate. In this example, an insulating layer11is provided on the substrate10s. On the insulating layer11, there are provided the semiconductor pillars50, the memory films54, the stacked bodies ML, and source members SM. In this example, the insulating layer11corresponds to the lower body10.

The semiconductor pillars50are electrically connected to the substrate10s. The source member SM is disposed in the stacked body ML. The semiconductor pillar50and the source member SM are electrically connected to each other via the substrate10s. The stacked body ML includes the plurality of conductive layers21and the plurality of insulating layers22.

Between the stacked body ML and the semiconductor pillar50, there is provided the memory film54.

As shown inFIG. 28AandFIG. 28B, in this example, the semiconductor pillar50has a cylindrical shape. In the semiconductor pillar50, there is provided a core section55extending in the first direction. The core section55has, for example, an insulation property.

The memory film54includes, for example, an outside film54a, an inside film54b, and an intermediate film54c. The outside film54ais provided between the semiconductor pillar50and the conductive layers21. The inside film54bis provided between the semiconductor pillar50and the outside film54a. The intermediate film54cis provided between the outside film54aand the inside film54b. The outside film54ais, for example, a block insulating film. The intermediate film54cis, for example, a charge storage film. The inside film54bis, for example, a tunnel insulating film.

The intermediate film54cincludes, for example, a silicon nitride.

Between the source member SM and the stacked body ML, there is provided an insulating film SMi.

On the insulating section66L and the stacked body ML, there is provided an insulating film71. On the insulating film71, there is provided an insulating film72. On the insulating film72, there is provided an insulating film73. On the insulating film73, there is provided an insulating film74. On the insulating film74, there is provided an insulating film75.

In the connection regions CR, on the plurality of conductive layers21, there are respectively provided contact plugs81. The contact plugs81each has, for example, a roughly columnar shape extending in the Z-axis direction. Each of the contact plugs81is electrically connected to corresponding one of the plurality of conductive layers21. The contact plugs81each includes a conductive material such as tungsten. On the periphery of each of the contact plugs81, there is disposed the insulating section66L.

Between the contact plug81and the insulating section66L and between the contact plug81and the conductive layer21, which is electrically connected to that contact plug81, there is provided a barrier metal film81a. The barrier metal films81ais a film including metal, and includes, for example, titanium. The barrier metal film81acan also be a film including titanium nitride.

On each of the semiconductor pillars50, there is provided a plug82. On the plug82, there is disposed a plug83. On the plugs83, there is disposed a plurality of bit lines91extending in, for example, the X-axis direction. The semiconductor pillar50and one of the plurality of bit lines91are electrically connected to each other via the plugs82and83.

On the source member SM, there is provided a plug84. On the plug84, there is disposed a source interconnection92. The source member SM and the source interconnection92are connected to each other via the plug84.

On the contact plug81, there is provided a plug85. On the plug85, there is provided, for example, an interconnection93extending in the X-axis direction. The contact plug81and the interconnection93are connected to each other via the plug85.

In the embodiment, the stacked body ML can also be separated from the substrate10s. It is also possible to provide an interconnection connected to the memory cell MC between the memory cell MC to be connected to the conductive layer included in the stacked body ML and the substrate10s.

FIG. 29is a schematic cross-sectional view illustrating a semiconductor memory device according to the embodiment.

As shown inFIG. 29, in another semiconductor memory device100aaccording to the embodiment, other layers including transistors10G are provides instead of the substrate10spresented inFIG. 27. In the semiconductor memory device100a, the transistors10G are provided on a substrate10H, which is made of silicon, for example. An insulating layer10F is provided around transistors10G. Interconnection layer10D is provided on the insulating layer10F. Another insulating layer10E is provided around the interconnection layer10D. The interconnection layer10D may functions as a source line, for example. In this example, the interconnection layer10D is electrically connected with a terminal (source or drain) of the transistor10G.

A connecting member10C is provided on the interconnection layer10D to be electrically connected therewith. Another insulating layer10B is provided around the connecting member10C. A conductive layer10A is provided on the connecting member10C, on the insulating layer10B and on the insulating layer10F. The conductive layer10A is electrically connected with the interconnection layer10D via the connecting member10C.

According to the embodiment, there can be provided a semiconductor memory device capable of increasing the memory capacity, and a method for manufacturing the semiconductor memory device.

Hereinabove, exemplary embodiments of the invention are described with reference to specific examples. However, the embodiments of the invention are not limited to these specific examples. For example, one skilled in the art may similarly practice the invention by appropriately selecting specific configurations of components included in semiconductor memory devices such as conductive layers, insulating layers, memory cells, semiconductor pillars, memory films, connection sections, etc., from known art. Such practice is included in the scope of the invention to the extent that similar effects thereto are obtained.

Moreover, all semiconductor memory devices, and methods for manufacturing the same practicable by an appropriate design modification by one skilled in the art based on the semiconductor memory devices and methods for manufacturing the same described above as embodiments of the invention also are within the scope of the invention to the extent that the spirit of the invention is included.