Method for fabricating conductive substrates for electronic and optoelectronic devices

A method for fabricating a conductive substrate for an electronic device includes the steps of providing a semiconductor substrate; forming a plurality of grooves part way through the semiconductor substrate; filling the grooves with a polymer insulating material to form a plurality of polymer filled grooves; thinning the substrate from the back side to expose the polymer filled grooves; and singulating the semiconductor substrate into a plurality of conductive substrates. An optoelectronic device includes a conductive substrate; a polymer filled groove configured to separate the conductive substrate into a first semiconductor substrate and a second semiconductor substrate; a first front side electrode on the first semiconductor substrate and a second front side electrode on the second semiconductor substrate; and a light emitting diode (LED) chip on the first semiconductor substrate in electrical communication with the first front side electrode and with the second front side electrode.

BACKGROUND

This disclosure relates generally to the fabrication of conductive substrates for electronic devices, particularly optoelectronic devices, such as light emitting diodes (LEDs).

Many electronic devices include a conductive substrate on which different electrical elements are mounted. For example, an optoelectronic device can include a conductive substrate make of a semiconductor material, such as silicon, and a light emitting diode (LED) chip mounted to the conductive substrate. In addition to providing a support structure for the LED chip, the conductive substrate can also include other electrical elements, such as terminals and conductors for making electrical connections to the LED chip. In addition, the conductive substrate can include heat transfer paths from the LED chip for dissipating heat generated during operation of the optoelectronic device.

Due to the operation of the various electrical elements on the conductive substrate, it is sometimes necessary to electrically isolate these electrical elements. Electrical isolation has typically been accomplished by depositing or growing insulating materials, such as polymers or oxides, on various surfaces of the substrate. In general, these techniques require specialized equipment, such as deposition or oxidation apparatus, and are therefore relatively expensive to perform. In addition, the deposited or grown insulating layers can adversely affect heat transfer paths from elements on the conductive substrate.

It would be advantageous to have a low cost method for fabricating conductive substrates for electronic devices. It would also be advantageous to have a method, which produces conductive substrates for optoelectronic devices with lower thermal resistance, higher brightness, improved efficiency and better reliability. The present disclosure is directed to a low cost method for fabricating conductive substrates, which produces improved electronic devices, particularly optoelectronic devices. However, the foregoing examples of the related art and limitations related therewith, are intended to be illustrative and not exclusive. Other limitations of the related art will become apparent to those of skill in the art upon a reading of the specification and a study of the drawings.

SUMMARY

A method for fabricating a conductive substrate for an electronic device includes the steps of providing a semiconductor substrate having a front side and a back side; forming a plurality of grooves on the front side part way through the semiconductor substrate; filling the grooves with a polymer insulating material to form polymer filled grooves; optionally forming front side electrodes on the front side; thinning the semiconductor substrate from the back side to expose the polymer filled grooves; optionally forming backside electrodes on the back side; and then singulating the semiconductor substrate into a plurality of conductive substrates. Each conductive substrate includes at least one polymer filled groove extending edge to edge and orthogonally from the front side to the back side configured to separate the conductive substrate into a first semiconductor substrate and a second semiconductor substrate.

Prior to the singulating step, additional processes can be performed for fabricating a desired electronic device. For an optoelectronic device these processes can include LED chip mounting, wire bonding, depositing a phosphor layer and forming an encapsulating lens. An optoelectronic device fabricated using the method includes a conductive substrate having a first semiconductor substrate and a second semiconductor substrate separated by a polymer filled groove. The optoelectronic device also includes an encapsulated light emitting diode (LED) chip, a first electrode on the first semiconductor substrate, and a second electrode on the second semiconductor substrate.

Another optoelectronic device fabricated using the method includes a pair of parallel spaced polymer filled grooves, which electrically and thermally isolate three separate semiconductor substrates to provide separate heat transfer and electrical paths. Yet another optoelectronic device fabricated using the method includes a polymer filled groove which electrically and thermally isolates two separate semiconductor substrates one of which contains an integrated semiconductor device, such as a protective device (e.g., zener diode).

DETAILED DESCRIPTION

Referring toFIGS. 1A-1Dand2A-2C, steps in a method for fabricating a conductive substrate for an electronic device are illustrated. Although for illustrative purposes the steps of the method are shown in a particular order, the method can be practiced with a different order. Initially, as shown inFIG. 1A, a semiconductor wafer10can be provided. Although in the illustrative embodiment, the method is performed on an entire semiconductor wafer10, it is to be understood that the method can be performed on a portion of a semiconductor wafer10or other suitable semiconductor substrate. Also in the illustrative embodiment, the semiconductor wafer10comprises a blank wafer. However, as will be further explained, the wafer10can include integrated circuits such as protective circuitry.

The semiconductor wafer10can comprise a conventional semiconductor wafer having a standard diameter and a full thickness (T1). By way of example, a 150 mm diameter wafer has a full thickness (T1) of about 675 μm, a 200 mm diameter wafer has a full thickness (T1) of about 725 μm, and a 300 mm diameter wafer has a full thickness (T1) of about 775 μm. In the illustrative embodiment, the semiconductor wafer10comprises silicon (Si). However, the semiconductor wafer10can comprise another material such GaAs, SiC, GaP, GaN or AlN. In addition, the semiconductor wafer10includes a semiconductor substrate12having a front side14(first side), and a back side16(second side), which are the major planar surfaces of the semiconductor wafer10. The semiconductor wafer10also includes a major flat18, which indicates the crystal orientation of the silicon.

Next, as shown inFIGS. 1B and 2A, a plurality of grooves20A,20B are formed on the front side14part way through the wafer10in a criss cross pattern. As shown inFIG. 2A, the grooves20A,20B extend to the edges22of the wafer10and have a depth D1which is less than the thickness T1(FIG. 1A) of the wafer10. For example, D1can equal from about 10% to 90% of T1. As also shown inFIG. 2A, the grooves20A,20B have a width W1which can equal from about 1 μm to 2000 μm. The grooves20A are generally parallel and spaced relative to one another, are generally perpendicular to the grooves20B, and are generally parallel to the major flat18. Similarly, the grooves20B are generally parallel and spaced relative to one another, are generally perpendicular to the grooves20A, and are generally perpendicular to the major flat18. Although the grooves20A,20B are illustrated in a criss cross pattern, it is to be understood that the method can be performed with grooves in a parallel spaced pattern (e.g., just grooves20A or just grooves20B). Each groove20A,20B can be generally rectangular in cross section with two parallel sidewalls and an orthogonal bottom surface.

The grooves20A,20B (FIG. 1B) can be formed using a suitable process such as sawing or cutting the front side14of the wafer10using a dicing saw. The grooves20A,20B (FIG. 1B) can also be formed by etching the front side14of the wafer10using a wet etching process, a dry etching process, a breaking process or a plasma etching process. The grooves20A,20B (FIG. 1B) can also be formed by laser machining the front side14of the wafer10using a laser machining system. The grooves20A,20B (FIG. 1B) can also be formed by stamping the front side14of the wafer10using a press or similar apparatus. Because the grooves20A,20B (FIG. 1B) do not extend completely through the wafer10, it can be handled using conventional equipment, such as a wafer handler, without breaking apart. Additionally, the wafer10can be supported during formation of the grooves20A,20B (FIG. 1B) using suitable equipment, such as a film frame or dicing tape (not shown).

Next, as shown inFIGS. 1C and 2B, the grooves20A,20B are at least partially filled with a polymer to form polymer filled grooves24A,24B. The polymer filled grooves24A,24B can be formed using a suitable process such as by deposition of the polymer through a nozzle into the grooves20A,20B, or by spatuling, screen printing or stenciling the polymer into the grooves20A,20B. The polymer filled grooves24A,24B can also be formed using any suitable process such as an injection molding process, a transfer molding process, a stenciling process, a screen printing process, a spin resist process, a dry film process, a stereographic lithographic process, or a CVD process. The polymer can comprise an electrically insulating, curable polymer such as a silicone, a polyimide, an epoxy, a ceramic paste, a glass paste or parylene. In addition, the polymer can include fillers, such as silicates, configured to reduce the coefficient of thermal expansion (CTE) and adjust the viscosity of the polymer material. Following deposition, the polymer can be cured or reacted to harden such as by placement in an oven at an elevated temperature for a suitable period of time. Following curing, the polymer filled grooves24A,24B can be planarized to the front surface14of the wafer10using a suitable process such as grinding or chemical mechanical planarization (CMP).

Next, as shown inFIGS. 1D and 2C, a front side metal forming step is performed to form a plurality of front side electrodes26A,26B (FIG. 2C) separated by a plurality of spaces28(FIG. 2C). The front side electrodes26A,26B (FIG. 2C) can be formed using a suitable metallization process. As will be further explained, the spaces28(FIG. 2C) between the front side electrodes26A,26B form streets where the wafer10will be singulated as indicated by future singulation lines30(FIG. 3C).

The front side electrodes26A,26B can comprise a single layer of a highly conductive metal such as Ti, Ta, Cu, W, TiW, Hf, Ag, Au, or Ni deposited using sputtering, PVD, CVD, evaporation or electroless chemical deposition. However, rather than a single layer of material, the front side electrodes26A,26B can comprise a multi-metal stack, such as a bi-metal stack comprised of a conductive layer and a bonding layer (e.g., Ti/Ni/Au), or multi layers such a Ta/TaN/Cu/Ni/Au and alloys of these metals. The front side electrodes26A,26B can be formed using a suitable deposition process (i.e., additive process) such as PVD, electroless deposition, electroplating or PVD through a mask (not shown). As another example, the front side electrodes26A,26B can be formed by blanket deposition of a metal layer followed by etching through a mask (i.e., subtractive process).

Referring toFIGS. 3A-3C, further steps in the method are illustrated.FIG. 3Ais a cross section throughFIG. 1Dshowing the polymer filled grooves24B formed part way through the wafer.FIG. 3Aalso shows the front side electrodes26A,26B separated by the spaces28which correspond to the future singulation lines30B (FIG. 3C).

Next, as shown inFIG. 3B, following formation of the front side electrodes26A,26B, a thinning and polishing step can be performed from the back side16of the wafer10. The thinning and polishing step thins the wafer10, polishes the back side16, and exposes the polymer filled grooves24A,24B on the back side16. The thinning and polishing step can be performed using a mechanical planarization process performed with a mechanical planarization apparatus, such as a grinder. This type of mechanical planarization process is sometimes referred to as dry polishing. One suitable mechanical planarization apparatus is manufactured by Okamoto, and is designated a model no. VG502. The thinning step can also be performed using a chemical mechanical planarization (CMP) apparatus. Suitable chemical mechanical planarization (CMP) apparatus are commercially available from manufacturers such as Westech, SEZ, Plasma Polishing Systems, and TRUSI. The thinning and polishing step can also be performed using an etch back process, such as a wet etch process, a dry etch process or a plasma etching process either performed alone or in combination with mechanical planarization. The thinning and polishing step can also be performed using a multi step process such as back grinding, followed by a soft polish step, then CMP and a cleaning step. The thickness T2of the thinned wafer10T can be selected as desired, with from 35 μm to 600 μm being representative. The thinned back side16has a smooth, polished surface, and is devoid of features.

Next, as shown inFIG. 3C, a back side metal forming step is performed to form a plurality of back side electrodes32A,32B separated by a plurality of spaces34. The back side metal forming step can be performed as previously described for the front side metal forming step. In addition, the spaces34align with the spaces28(FIG. 3A) on the front side which correspond to the future singulation lines30B (FIG. 3C). As also shown inFIG. 3C, a plurality of conductive substrates38are formed on the thinned wafer10T. During a subsequent singulation step, the conductive substrates38will be separated along singulation lines30A (FIG. 4A) and 30B(FIG. 3C).

FIG. 4Ais a plan view showing each conductive substrate38with a pair of front side electrodes26A and26B, a polymer filled groove24B, and an outline defined by singulation lines30A and30B.FIG. 4Bis a bottom view showing each conductive substrate38with a pair of back side electrodes32A and32B, a polymer filled groove24B, and an outline defined by singulation lines30A and30B. As will be further explained, polymer filled grooves24A will be trimmed away from the conductive substrate38along singulation lines30A during the subsequent singulation step.

Referring toFIGS. 5A-5E, further steps in the method are illustrated. The steps shown inFIGS. 5A-5Eare for forming optoelectronic devices36(FIG. 6C) with the conductive substrates38(FIG. 6C). As is apparent, for forming other electronic devices different steps would be utilized. As shown inFIG. 5A, a light emitting diode mounting step can be performed to mount LED chips40on the front side14in electrical contact with the front side electrodes26B. A bonding layer (not shown) can be formed using a solder reflow process, a bumping process or a silver epoxy curing process to bond the LED chips40to the front side electrodes26B with each conductive substrate38having one LED chip40. The LED chips40can comprise conventional LED chips fabricated using known processes. Suitable LED chips are commercially available from SEMILEDS, INC. located in Boise Id., and Miao-Li County, Taiwan, R.O.C.

Next, as shown inFIG. 5B, a wire bonding step is performed in which wires42A,42B (FIG. 6A) are wire bonded to contacts on the LED chips40. In addition, the wires42A,42B (FIG. 6A) cross over the polymer filled grooves24B, and are wire bonded to the front side electrodes26A. The wire bonding step can be performed using conventional wire bonding equipment.

Next, as shown inFIG. 5C, a fluorescent layer deposition step is performed in which fluorescent material containing layers44are formed on the LED chips40. As shown inFIG. 6C, the fluorescent material containing layers44can be formed to encapsulate the LED chips40. The fluorescent material containing layers44can comprise a suitable material, such as a phosphor based material, which can be deposited using a suitable process such as spin on, dispensing or spray on and then patterned to cover the LED chips40.

Next, as shown inFIG. 5D, a lens forming step is performed to form transparent domes46on the LED chips40. The transparent domes46can comprise a transparent material, such as silicone, which function as encapsulating lenses for the optoelectronic devices36(FIG. 6C). The transparent domes46can be formed using a suitable process such as a molding process.

Next, as shown inFIG. 5E, a singulation step is performed to singulate the thinned semiconductor wafer10T into a plurality of optoelectronic devices36, each of which includes a conductive substrate38. The singulation process is also referred to in the art as dicing. The singulation step can be performed using a process such as lasering, sawing, water jetting or etching, in which the individual optoelectronic devices36are separated along the singulation lines30A and30B (FIG. 4A). The singulation step also trims away the polymer filled grooves24A (FIG. 2C). However, as previously explained, the method can be practiced by forming only the polymer filled grooves24B in a parallel spaced pattern, rather than polymer filled grooves24A,24B in a criss cross pattern.

Referring toFIGS. 6A-6C, the optoelectronic device36is illustrated. The optoelectronic device36includes the conductive substrate38and the LED chip40mounted to the conductive substrate38. As shown inFIGS. 6A and 6B, the polymer filled groove24B extends completely across the conductive substrate38from edge to edge. As shown inFIG. 6C, the polymer filled groove24B extends completely through the conductive substrate38from the front side14to the back side16. In addition, the polymer filled groove24B separates the conductive substrate38into a first semiconductor substrate12A and a second semiconductor substrate12B. The first semiconductor substrate12A is in electrical contact with the front side electrode26B, and in electrical contact with the back side electrode32B. The first semiconductor substrate12A thus provides an electrical path from the LED chip40to the back side electrode32B. The second semiconductor substrate12B is in electrical contact with the front side electrode26A and in electrical contact with the back side electrode32A. The second semiconductor substrate12B thus provides an electrical path from the wires42A,42B to the back side electrode32B. In addition, as shown inFIG. 6C, in the optoelectronic device36, a heat transfer path48is provided from the LED chip40through the first semiconductor substrate12A.

Referring toFIGS. 7A-7B, a second optoelectronic device36A is illustrated. Elements of the optoelectronic device36A are denoted by the suffix A or −A on the same reference numerals previously used to describe optoelectronic device36. The optoelectronic device36A includes a conductive substrate38A characterized by separate electrical and heat transfer paths, and a surface mounted protective device50A, such as a zener diode. The optoelectronic device36A also includes an LED chip40A mounted to the conductive substrate38A, a transparent dome46A, and a fluorescent material containing layer as previously described, which for simplicity is not shown. The conductive substrate38A is similar to the previously described conductive substrate38(FIG. 6C) but with three separate semiconductor substrates12A-A,12B-A and12C-A. In addition, the optoelectronic device36A includes a pair of parallel spaced polymer filled grooves24B-A similar to the previously described polymer filled groove24B (FIG. 6C), which separate and electrically insulate the semiconductor substrates12A-A,12B-A and12C-A.

Further, the optoelectronic device36A (FIGS. 7A-7B) includes a pair of front side electrodes26A-A and26B-A similar to the previously described front side electrodes26A,26B (FIG. 6C). However, the front side electrode26B-A is in electrical contact with the first semiconductor substrate12A-A, and also with the third semiconductor substrate12C-A as well. Still further, the optoelectronic device36A includes three back side electrodes32A-A,32B-A and32C-A similar to the previously described back side electrodes32A,32B (FIG. 6C). However, the second back side electrode32B-A is electrically insulated by a back side insulating layer52A on the first semiconductor substrate12A-A. The insulating layer52A can comprise an electrically insulating, curable polymer such as a silicone, a polyimide, an epoxy, a ceramic paste, a glass paste, a silicon dioxide, a silicon nitride, AlN, Al2O3or parylene. The first semiconductor substrate12A-A and the second back side electrode32B-A provide a separate heat transfer path from the LED chip40A. In addition, the LED chip40A is in electrical contact with the front side electrode26B-A, which provides an electrical path through the third semiconductor substrate12C-A to the third back side electrode32C-A. Further, the LED chip40A and the protective device50A are wire bonded to the first front side electrode26A-A which provides an electrical path through the second semiconductor substrate12B-A to the first back side electrode32A-A.

The optoelectronic device36A (FIGS. 7A-7B) can be fabricated using the previously described method of fabrication for optoelectronic device36(FIG. 6C). However, the method is performed such that a pair of parallel, spaced, polymer filled grooves24B-A per conductive substrate38A are formed, rather than a single polymer filled groove24B (FIG. 6C) as in conductive substrate38(FIG. 6C). In addition, the method is performed such that front side electrode26B-A is in electrical contact with first semiconductor substrate12A-A, and with the third semiconductor substrate12C-A as well. Further, the method is performed such that three back side electrodes32A-A,32B-A and32C-A are formed, and a back side insulating layer52A is formed between the first semiconductor substrate12A-A and the second back side electrode32B-A. The optoelectronic device36A can also be fabricated with a front side insulating layer (not shown) rather than a back side insulating layer52A. The first semiconductor substrate12A-A and the second back side electrode32B-A thus function only to provide a heat transfer path from the LED chip40A.

Referring toFIGS. 8A-8E, a third optoelectronic device36B is illustrated. Elements of the optoelectronic device36B are denoted by the suffix B or −B on the same reference numerals previously used to describe the optoelectronic device36(FIG. 6C). The optoelectronic device36B includes a conductive substrate38B characterized by an integrated protective device50B, such as a zener diode. The optoelectronic device36B also includes an LED chip40B mounted to the conductive substrate38B, a transparent dome46B, and a fluorescent material containing layer as previously described, which for simplicity is not shown. The conductive substrate38B is similar to the previously described conductive substrate38(FIG. 6C) and includes a first semiconductor substrate12A-B and a second semiconductor substrate12B-B separated by a polymer filled groove24B-B. However, in this embodiment the second semiconductor substrate12B-B includes an integrated protective semiconductor device50B formed by separate N− and P+ layers on a Si N− substrate. As shown inFIG. 8E, the integrated protective semiconductor device50B can comprise a zener diode ZD for protecting the LED chip40B. The optoelectronic device36B can be fabricated using the previously described method of fabrication for optoelectronic device36(FIG. 6C). However, the integrated protective semiconductor device50B can be formed prior to the grooves20A,20B (FIG. 2A) using semiconductor fabrication techniques such as ion implantation and doping.

Referring toFIGS. 9A-9E, a fourth optoelectronic device36C is illustrated. Elements of the optoelectronic device36C are denoted by the suffix C or −C on the same reference numerals previously used to describe the optoelectronic device36A (FIGS. 7A-7B). The optoelectronic device36C includes a conductive substrate38C characterized by separate electrical and heat transfer paths, and an integrated protective device50C, such as a zener diode. The optoelectronic device36C also includes an LED chip40C mounted to the conductive substrate38C, a transparent dome46C, and a fluorescent material containing layer44C. The conductive substrate38C is similar to the previously described conductive substrate38A (FIGS. 7A-7B) and includes a first semiconductor substrate12A-C, a second semiconductor substrate12B-C, and a third semiconductor substrate12C-C separated by a pair of parallel, spaced polymer filled groove24B-C. However, in this embodiment the second semiconductor substrate12B-C includes an integrated protective semiconductor device50C formed by separate N− and P+ layers on a Si N− substrate. As shown inFIG. 9E, the integrated protective semiconductor device50C can comprise a zener diode ZD for protecting the LED chip40C. The optoelectronic device36C can be fabricated using the previously described method of fabrication for optoelectronic device36(FIG. 6C). However, the integrated protective semiconductor device50C can be formed prior to the grooves20A,20B (FIG. 2A) using semiconductor fabrication techniques such as ion implantation and doping. In addition, a back side insulating layer52A-C (FIG. 9C) can be formed to electrically insulate the first semiconductor substrate12A-C which functions to provide only a heat transfer path. The optoelectronic device36C can also be fabricated with a front side insulating layer (not shown) rather than a back side insulating layer52A-C.

Referring toFIG. 10, a process flow chart for fabricating the optoelectronic device36(FIGS. 6A-6C) or the optoelectronic device36A (FIGS. 7A-7B) is illustrated. Approach A is for fabricating the optoelectronic device36(FIGS. 6A-6C). Approach B is for fabricating the optoelectronic device36(FIGS. 6A-6C). Approach C is for fabricating the optoelectronic device36A (FIGS. 7A-7B) but with a front side insulating layer (not shown) rather than a back side insulating layer52A (FIG. 7B).

Referring toFIG. 11, a process flow chart for fabricating the optoelectronic device36B (FIGS. 8A-8E) or the optoelectronic device36C (FIGS. 9A-9E) is illustrated. Approach A is for fabricating the optoelectronic device36B (FIGS. 8A-8E). Approach B is for fabricating the optoelectronic device36C (FIGS. 9A-9E). Approach C is for fabricating the optoelectronic device36C (FIGS. 9A-9C) but with a front side insulating layer (not shown) rather than a back side insulating layer52A-C (FIG. 9C).

Thus the disclosure describes a method for making conductive substrate for electronic and optoelectronic devices such as light emitting diode (LEDs) as well as improved conductive substrates and optoelectronic devices. While a number of exemplary aspects and embodiments have been discussed above, those of skill in the art will recognize certain modifications, permutations, additions and subcombinations thereof. It is therefore intended that the following appended claims and claims hereafter introduced are interpreted to include all such modifications, permutations, additions and sub-combinations as are within their true spirit and scope.