Semiconductor device and method of forming the same

A semiconductor device includes an insulating substrate, a semiconductor chip, an insulating layer, and a sealing layer. The insulating substrate has an opening. A semiconductor chip is disposed in the opening. An insulating layer is disposed on a first surface of the insulating substrate. The insulating layer covers the opening. The sealing layer is disposed on a second surface of the insulating substrate. The sealing layer seals the semiconductor chip and the opening.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to a semiconductor device and a method of forming the same.

Priority is claimed on Japanese Patent Application No. 2009-124141, filed May 22, 2009, the content of which is incorporated herein by reference.

2. Description of the Related Art

A semiconductor device having a BGA (Ball Grid Array) structure has been known. A semiconductor chip is mounted on a semiconductor substrate such as a wiring substrate having wiring patterns that are formed on one surface thereof Japanese Unexamined Patent Application, First Publication, No. JP-A-2001-044229 discloses such a semiconductor device. The semiconductor device has a BGA structure. The semiconductor device includes predetermined circuits on one surface of the wiring substrate. The semiconductor device includes a semiconductor chip having plural electrode pads mounted on the surface of the wiring substrate. A matrix array of solder balls is disposed on the other surface of the wiring substrate. Solder balls serve as external electrodes that correspond to the electrode pads on the semiconductor chip. The electrode pads on the semiconductor chip and the corresponding external electrodes are electrically connected to each other via wires of the wiring substrate. A sealing member is disposed on one surface of the wiring substrate. The sealing member covers at least connection portions between the semiconductor chip and the wiring substrate.

The semiconductor device having the past BGA structure can be manufactured by an MAP (Mold Array Process) for manufacturing plural products at a time.

Japanese Unexamined Patent Application, First Publication, No. JP-A-2003-133521 discloses that to decrease the thickness of the semiconductor device, there was suggested a semiconductor device having the BGA structure using a wiring substrate having an opening. Japanese Unexamined Patent Application, First Publication, No. JP-A-2003-133521 discloses the semiconductor device configured to dispose a semiconductor chip in the opening of the wiring substrate by the use of a support tape. This configuration provides a clearance between the semiconductor devices. This configuration allows stacking the semiconductor devices having the BGA structure with reduced stress applied to the connecting portions between the semiconductor devices.

The semiconductor device disclosed in Japanese Unexamined Patent Application, First Publication, No. JP-A-2001-044229 has the following issues. The semiconductor chip is bonded and fixed to the wiring substrate through a DAF (Die Attach Film) or an adhesive. When a material having a different coefficient of thermal expansion is bonded and fixed to the wiring substrate, stress is generated in the semiconductor device in manufacture, and this stress is applied to the external electrodes. The external electrodes may be broken due to this stress.

The semiconductor device disclosed in Japanese Unexamined Patent Application, First Publication, No. JP-A-2003-133521 discloses the following problems. The balance of thermal expansion is poor between the support tape disposed on one surface of the wiring substrate and the sealing member disposed on the other surface thereof, and stress or bending may be caused in the semiconductor device. When stress or bending is caused, disconnection may be caused at the time of mounting the semiconductor device on a main substrate or the like. The external electrodes are not partially connected. Particularly, in the semiconductor device having plural semiconductor devices stacked, bending or stress of each of the stacked semiconductor devices has a great influence. In the related art, the reliability of secondary mounting is lowered due to the generation of stress or bending of each of the stacked semiconductor devices.

SUMMARY

In one embodiment, a semiconductor device may include, but is not limited to, an insulating substrate, a semiconductor chip, an insulating layer, and a sealing layer. The insulating substrate has an opening. A semiconductor chip is disposed in the opening. An insulating layer is disposed on a first surface of the insulating substrate. The insulating layer covers the opening. The sealing layer is disposed on a second surface of the insulating substrate. The sealing layer seals the semiconductor chip and the opening.

In another embodiment, a semiconductor device may include, but is not limited to, an insulating substrate, a semiconductor chip, external electrodes and conductors. The insulating substrate has an opening. The semiconductor chip is disposed inside the space of the opening. External electrodes are disposed on a first surface of the insulating substrate. Conductors electrically connect the external electrodes to the semiconductor chip.

In still another embodiment, a semiconductor device may include, but is not limited to, a wiring substrate, a semiconductor chip, a sealing resin layer, and external electrodes. The wiring substrate may include, but is not limited to, an insulating substrate, a first wiring layer, a second wiring layer, a through-wire, ands an insulating layer. The insulating substrate has an opening. The first wiring layer is disposed on the first surface of the insulating substrate. The second wiring layer is disposed on the second surface of the insulating substrate. The through-wire penetrates the insulating substrate. The through-wire connects the first wiring layer and the second wiring layer. The insulating layer is disposed on a first surface of the insulating substrate. The insulating layer covers the opening. The semiconductor chip is disposed in the opening. The semiconductor chip is electrically connected to the second wiring layer. The sealing resin layer is disposed on a second surface of the insulating substrate. The sealing resin layer seals the semiconductor chip and the opening. The external electrodes are disposed on the first surface of the insulating substrate. The external electrodes are partially exposed from the insulating layer.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

In one embodiment, a semiconductor device may include, but is not limited to, an insulating substrate, a semiconductor chip, an insulating layer, and a sealing layer.

The insulating substrate has an opening. A semiconductor chip is disposed in the opening. An insulating layer is disposed on a first surface of the insulating substrate. The insulating layer covers the opening. The sealing layer is disposed on a second surface of the insulating substrate. The sealing layer seals the semiconductor chip and the opening.

In some cases, the semiconductor device may further include, but is not limited to, external electrodes disposed on the first surface of the insulating substrate. The external electrodes are partially exposed from the insulating layer.

In these cases, the semiconductor device may further include, but is not limited to, conductors electrically connecting the external electrodes to the semiconductor chip.

In some cases, each of the conductors may include, but is not limited to, a first wiring layer, a second wiring layer, and a through-wire. The first wiring layer is disposed on the first surface of the insulating substrate. The first wiring layer is connected to the external electrode. The second wiring layer is disposed on the second surface of the insulating substrate. The through-wire penetrates the insulating substrate. The through-wire connects the first wiring layer and the second wiring layer.

In these cases, the second wiring layer may be bonded via a bonding-wire to the semiconductor chip. The bonding-wire may be buried in the sealing layer.

In some cases, a first thickness of the insulating layer may be substantially the same as a second thickness of the sealing layer. The second thickness is defined between the second substrate and a surface of the sealing layer.

In some cases, the insulating layer may be substantially the same in coefficient of thermal expansion as the sealing layer.

In some cases, a first thickness of the insulating layer may be thinner than a second thickness of the sealing layer. The second thickness is defined between the second substrate and a surface of the sealing layer. The insulating layer is greater in coefficient of thermal expansion than the sealing layer.

In some cases, a first thickness of the insulating layer may be thicker than a second thickness of the sealing layer. The second thickness is defined between the second substrate and a surface of the sealing layer. The insulating layer may be smaller in coefficient of thermal expansion than the sealing layer.

In some cases, the insulating layer may cover entirely the first surface of the insulating substrate.

In some cases, the sealing layer may cover entirely the second surface of the insulating substrate.

In some cases, the semiconductor chip may be mounted on the insulating layer.

In another embodiment, a semiconductor device may include, but is not limited to, an insulating substrate, a semiconductor chip, external electrodes and conductors. The insulating substrate has an opening. The semiconductor chip is disposed inside the space of the opening. External electrodes are disposed on a first surface of the insulating substrate. Conductors electrically connect the external electrodes to the semiconductor chip.

In some cases, the semiconductor device may include, but is not limited to, an insulating layer on the first surface of the insulating substrate. The insulating layer covers the opening. The sealing layer is disposed on the second surface of the insulating substrate. The sealing layer seals the semiconductor chip and the opening.

In still another embodiment, a semiconductor device may include, but is not limited to, a wiring substrate, a semiconductor chip, a sealing resin layer, and external electrodes. The wiring substrate may include, but is not limited to, an insulating substrate, a first wiring layer, a second wiring layer, a through-wire, ands an insulating layer. The insulating substrate has an opening. The first wiring layer is disposed on the first surface of the insulating substrate. The second wiring layer is disposed on the second surface of the insulating substrate. The through-wire penetrates the insulating substrate. The through-wire connects the first wiring layer and the second wiring layer. The insulating layer is disposed on a first surface of the insulating substrate. The insulating layer covers the opening. The semiconductor chip is disposed in the opening. The semiconductor chip is electrically connected to the second wiring layer. The sealing resin layer is disposed on a second surface of the insulating substrate. The sealing resin layer seals the semiconductor chip and the opening. The external electrodes are disposed on the first surface of the insulating substrate. The external electrodes are partially exposed from the insulating layer.

In some cases, a first thickness of the insulating layer may be substantially the same as a second thickness of the sealing layer. The second thickness is defined between the second substrate and a surface of the sealing layer.

In some cases, the insulating layer may be substantially the same in coefficient of thermal expansion as the sealing layer.

In some cases, a first thickness of the insulating layer may be thinner than a second thickness of the sealing layer. The second thickness is defined between the second substrate and a surface of the sealing layer. The insulating layer may be greater in coefficient of thermal expansion than the sealing layer.

In some cases, a first thickness of the insulating layer may be thicker than a second thickness of the sealing layer. The second thickness is defined between the second substrate and a surface of the sealing layer. The insulating layer may be smaller in coefficient of thermal expansion than the sealing layer.

In yet another embodiment, a method of forming a semiconductor device may include, but is not limited to, the following processes. A wiring substrate is prepared. The wiring substrate may include, but is not limited to, an insulating substrate, a first wiring layer, a second wiring layer, a through-wire, ands an insulating layer. The insulating substrate has an opening. The first wiring layer is disposed on the first surface of the insulating substrate. The second wiring layer is disposed on the second surface of the insulating substrate. The through-wire penetrates the insulating substrate. The through-wire connects the first wiring layer and the second wiring layer. The insulating layer is disposed on a first surface of the insulating substrate. The insulating layer covers the opening. A semiconductor chip is formed in the opening. A sealing resin layer is formed on a second surface of the insulating substrate. The sealing resin layer seals the semiconductor chip and the opening. External electrodes are formed on the first surface of the insulating substrate. The external electrodes are partially exposed from the insulating layer.

In some cases, the wiring substrate can be prepared by forming the opening in the insulating substrate, forming the conductors in the insulating substrate, and forming the insulating layer on the first surface of the insulating substrate.

A semiconductor device according to an embodiment of the invention will be described with reference toFIGS. 1 and 2.FIG. 1is a plan view of a semiconductor device1according to an embodiment of the invention.FIG. 2is a sectional view taken along line II-II′ ofFIG. 1.

As shown inFIGS. 1 and 2, the semiconductor device1is a BGA-type semiconductor device. The semiconductor device1includes a substantially rectangular shaped wiring substrate10having a substantially rectangular-shaped opening14. The semiconductor device1also includes a semiconductor chip30disposed in the substantially rectangular-shaped opening14of the wiring substrate10.

The wiring substrate10includes a substantially rectangular-shaped insulating member12having the opening14. The wiring substrate10includes plural conductors20that surround the periphery of the opening14. The wiring substrate10includes an insulating layer16that is stacked on one surface12aof the insulating member12. The insulating layer16covers the opening14. Each conductor20includes a first wiring layer22disposed on a surface12aof the insulating member12. Each conductor20includes a second wiring layer26disposed on a surface12bof the insulating member12. Each conductor20includes a through-wire24passing through the insulating member12. The through-wire24electrically connects the first wiring layer22and the second wiring layer26. The insulating layer16is stacked to form a land portion62by exposing at least a part of the first wiring layer22. A metallic ball (external electrode)60made of solder is formed on the land portion62. The land portions62are arranged, for example, in a grid array or a lattice array.

In the opening14, the semiconductor chip30is fixed to the insulating layer16with an adhesive layer34interposed therebetween. The semiconductor chip30is disposed so that the sides thereof are separated from the inner wall of the opening14by about 10 μm.

A predetermined circuit (not shown) is disposed on a surface30aof the semiconductor chip30. Plural electrode pads32are disposed on the periphery of the surface30aof the semiconductor chip30. The electrode pads32are connected to the corresponding second wiring layers26by bonding wires50(hereinafter, simply referred to as “wires”) formed of a conductive material such as Au. In this way, the semiconductor chip30is electrically connected to the metallic balls60via the conductors20and the wires50. An insulating passivation film not shown is disposed on the surface30aof the semiconductor chip30except for the electrode pads32, whereby the circuit disposed on the surface30ais protected.

A sealing resin layer40is stacked on the other surface12bof the insulating member12. The sealing resin layer40covers the opening14, the semiconductor chip30, and the wires50.

The insulating member12may be, for example, a glass epoxy material. The thickness of the insulating member12is preferably, for example, in the range of 50 μm to 200 μm and is more preferably the same as the thickness of the mounted semiconductor chip30. When the thickness is in the above-mentioned range, the thickness of the semiconductor device1can be reduced and proper strength can be maintained. The coefficient of thermal expansion (CTE) of the insulating member12can be determined in consideration of the CTE of the semiconductor chip30, and the CTE is preferably, for example, in the range of 5×10−6/° C. to 15×10−6/° C. For example, the CTE is preferably 5×10−6/° C. which is equal to the CTE of Si as a base material of the semiconductor chip30.

The CTE is a linear expansion coefficient. The CTE is the value of the ratio at which the length varies with a rise in temperature (which is the same hereinafter).

The insulating layer16is formed of, for example, solder resist. The thickness t1(seeFIG. 2) of the insulating layer16can be determined in consideration of the thickness of the sealing resin layer40or the like. The thickness t1can be determined, for example, in the range of 20 μm to 300 μm. The thickness t1is preferably in the range of 20 μm to 40 μm.

The CTE of the insulating layer16can be determined in consideration of the thickness t1of the insulating layer16. For example, when the thickness t1of the insulating layer16is in the range of 20 μm to 40 μm, the CTE is preferably set in the range of 20×10−6/° C. to 30×10−6/° C. For example, when the thickness t1is 40 μm, the CTE is preferably set to 30×10−6/° C. By setting the thickness and the CTE as described above, the insulating layer16and the sealing resin layer40can be balanced in thermal expansion, thereby reducing the generation of stress or bending in the semiconductor device1due to the thermal expansion.

The sealing resin layer40is a sealing resin formed of thermosetting resin such as an epoxy resin. The thickness t2(seeFIG. 2) of the sealing resin layer40can be determined in consideration that the wires50are not exposed from the sealing resin layer40. The thickness t2is preferably in the range of 100 μm to 300 μm. The thickness t2of the sealing resin layer40is a thickness above the surface12bof the insulating member12. The sealing resin layer40having the thickness t2does not include the part filled in the clearance between the opening14and the semiconductor chip30.

The CTE of the sealing resin layer40can be determined in consideration of the thickness t2of the sealing resin layer40. For example, when the thickness t2of the sealing resin layer40is in the range of 100 μm to 300 μm, the CTE can be set preferably in the range of 5×10−6/° C. to 20×10−6/° C. For example, when the thickness t2is 200 μm, the CTE can be set preferably at 6×10−6/° C. By setting the thickness and the CTE as described above, the insulating layer16and the sealing resin layer40can be balanced in thermal expansion, thereby reducing the generation of stress or bending in the semiconductor device1due to the thermal expansion.

By adjusting the thicknesses and the CTEs of the insulating layer16and the sealing resin layer40, it is possible to further reduce bending of the semiconductor device1.

For example, it is preferable that the thickness t1of the insulating layer16and the thickness t2of the sealing resin layer40are substantially equal to each other and more preferably completely equal to each other. By setting t1and t2to substantially equal values, it is possible to improve the anti-bending effect of the semiconductor device1. Here, “substantially equal” means that the thickness ratio expressed by t1/t2is in the range of 0.95 to 1.05.

For example, the CTE, hereinafter referred to as CTE1, of the insulating layer16and the CTE, hereinafter, referred to as CTE2, of the sealing resin layer40are preferably substantially equal to each other and more preferably completely equal to each other. By setting CTE1and CTE2to the substantially equal value, it is possible to improve the anti-bending effect of the semiconductor device1. Here, “substantially equal” means that the thickness ratio expressed by CTE1/CTE2is in the range of 0.95 to 1.05.

When t1<t2is set, it is preferable that the materials of the insulating layer16and the sealing resin layer40are selected to satisfy CTE1>CTE2. By setting the CTE in this way, it is possible to improve the anti-bending effect of the semiconductor device1. The magnitude of the ratio of CTE1to CTE2can be determined in consideration of the thickness ratio expressed by t1/t2.

When t1>t2is set, it is preferable that the materials of the insulating layer16and the sealing resin layer40are selected to satisfy CTE1<CTE2. By setting the CTE in this way, it is possible to improve the anti-bending effect of the semiconductor device1. The magnitude of the ratio of CTE2to CTE1can be determined in consideration of the thickness ratio expressed by t1/t2.

In the semiconductor chip30, for example, semiconductor elements such as MOS transistors are formed on a silicon substrate. The thickness of the semiconductor chip30is preferably in the range of 50 μm to 200 μm. The CTE of the semiconductor chip30is preferably set at 5×10−6/° C.

For example, a DAF or an insulating adhesive can be used for the adhesive layer34.

The first wiring layer22can be patterned, for example, with a conductive material such as Cu. The second wiring layer26is the same as the first wiring layer22.

The through-wire24can be formed by filling the through-hole formed in the insulating member12with a conductive material such as Cu.

(Method of Manufacturing Semiconductor Device)

A method of manufacturing a semiconductor device according to an embodiment of the invention includes the following processes. A process (preparation process) is to prepare a wiring substrate. A process (die bonding process) is to dispose a semiconductor chip in an opening of the wiring substrate. A process (wire bonding process) is to electrically connect the conductor of the wiring substrate to the semiconductor chip. A process (resin sealing process) is to stack a sealing resin layer on the other surface of the insulating material so as to cover the opening and the semiconductor chip. A process (ball mounting process) is to dispose external electrodes connected to the conductor.

An example of the method of manufacturing a semiconductor device according to an embodiment of the invention will be described with reference toFIGS. 3A through 4K.FIG. 3Ais a plan view illustrating a wiring base substrate100used to manufacture the semiconductor device1according to an embodiment of the invention.FIG. 3Bis a sectional view taken along line B-B′ ofFIG. 3A.FIGS. 4A through 4Fare sectional views illustrating a process of manufacturing the wiring base substrate100used to manufacture the semiconductor device1according to an embodiment of the invention.FIGS. 4G through 4Kare sectional views illustrating a process of manufacturing the semiconductor device1according to an embodiment of the invention.

The preparation process is a process of preparing the wiring base substrate100having an opening14formed in each product forming section110as shown inFIGS. 3A and 3B. The wiring base substrate100may be prepared by purchase and may be manufactured by the following manufacturing method.

The base wiring substrate used to manufacture the semiconductor device1will be described. As shown inFIGS. 3A and 3B, the wiring base substrate100is processed in the MAP method. The wiring base substrate100has a configuration such that plural product forming sections110are arranged in a matrix shape in an insulating base substrate101which is a source of the insulating member12. Dicing lines106for individually separating the product forming sections110to form the wiring substrates10are formed between the product forming sections110. The product forming sections110have the same configuration as the wiring substrate10in the step in which they are cut and separated from each other by the dicing lines106to form the respective wiring substrates10.

A frame102is disposed around the plural product forming sections110arranged in a matrix array. Positioning holes104are disposed in the frame102at a predetermined interval to transport or position the frame.

As shown inFIG. 3B, holes are formed in the insulating layer16to form the land portions62by exposing a part of the first wiring layer22.

An example of the method of manufacturing the wiring base substrate100will be described with reference toFIGS. 4A through 4F. The method of manufacturing the wiring base substrate100includes the following processes. A process (opening process) is to form openings in the insulating base material. A process (conductor forming process) is to form conductors in the insulating base material. A process (insulating layer stacking process) is to stack an insulating layer on one surface of the insulating base material.

As shown inFIG. 4A, plural openings14are formed at positions corresponding to the product forming sections110of the insulating base substrate101by punching using a cutting punch or etching (opening process). The insulating base substrate101is formed of, for example, a substantially rectangular-shaped glass epoxy base material.

With reference toFIG. 4A, plural via holes120are formed at positions corresponding to the through-wires24of the insulating base substrate101by punching using a cutting punch or etching.

With reference toFIG. 4B, the via holes120are filled with a conductive material such as Cu to form the through-wires24.

With reference toFIG. 4C, subsequently, by disposing a conductor layer such as a Cu film on the overall surface of the surface101bof the insulating base substrate101and etching the conductor layer in a pattern, the second wiring layer26is formed.

With reference toFIG. 4D, similarly to the surface101bside, the first wiring layer22of the pattern is formed on the surface101aof the insulating base substrate101. In this way, the conductor20including the first wiring layer22, the through-wire24, and the second wiring layer26is formed (conductor forming process).

With reference toFIG. 4E, a solder resist film with a thickness of 40 μm or more is disposed on the overall surface of the surface101ato form the insulating layer16covering the opening14and the first wiring layer22.

With reference toFIG. 4F, subsequently, the insulating layer16corresponding to the land portions on which the external electrodes in the first wiring layers22are mounted are etched to form a hole, whereby the land portions62are formed by partially exposing the first wiring layers22(insulating layer stacking process). In this way, the wiring base substrate100can be manufactured.

An example of the method of assembling the semiconductor device1using the wiring base substrate100will be described with reference toFIGS. 4G through 4K. The method of assembling the semiconductor device1includes a die bonding process, a wire bonding process, a resin sealing process, and a ball mounting process.

With reference toFIG. 4Gthe semiconductor chips30are disposed in the openings14formed in the wiring base substrate100, respectively. Each semiconductor chip30has a surface which is opposite to the surface on which the electrode pad32is formed. The opposite surface of each semiconductor chip30is adhered and fixed to the insulating layer16in the opening14with an adhesive layer (not shown) such as a DAF or an insulating adhesive interposed therebetween. At this time, the respective sides of the semiconductor chip30are separated from the inner wall of the opening14by about 10 μm (die bonding process).

With reference toFIG. 4H, the electrode pad32of the semiconductor chip30disposed in each opening14and the second wiring layer26are connected to each other by a conductive material such as a wire50formed of Au (wire bonding process). Accordingly, the electrode pad32of the semiconductor chip30and the first wiring layer22corresponding thereto are electrically connected to each other via the wire50, the second wiring layer26, and the through-wire24.

In the wiring bonding process, the wire50of which the tip has a ball formed by melting is bonded to the electrode pad32by ultrasonic thermo-compression, for example, using a wire bonding apparatus. A loop shape is then formed. The other tip of the wire50is bonded to the corresponding second wiring layer26by ultrasonic thermo-compression. By disposing the semiconductor chip30in the opening14, it is possible to reduce the length of the wire50, thereby reducing short-circuits or flow of the wires.

With reference toFIG. 4I, the product forming sections110arranged in a matrix array are sealed by a thermoplastic resin (sealing resin) such as epoxy resin. In this way, the sealing resin layer40is stacked on the surface101bof the insulating base substrate101. The sealing resin layer40covers at least the openings14, the semiconductor chips30, and the wires50(resin sealing process). At this time, the clearances between the openings14and the semiconductor chips30are filled with the sealing resin.

In the resin sealing process, for example, the wiring base substrate100is clamped with a shaping mold including an upper mold and a lower mold of a transfer mold apparatus, the epoxy resin is pressed into the cavity formed by the upper mold and the lower mold from a gate, and the sealing resin is thermally cured, whereby the sealing resin layer40can be formed.

With reference toFIG. 4J, conductive metallic balls (external terminals)60are mounted on the land portions62arranged in a matrix array on the surface101aof the insulating base substrate101. In the ball mounting process, the metallic balls60formed of, for example, solder are kept in absorbing holes using an absorbing mechanism. The absorbing mechanism has plural absorbing holes. The plural absorbing holes are positioned corresponding to the arrangement of the land portions62. Flux is transferred to the kept metallic balls60. As a result, the land portions62are mounted. The metallic balls are reflowed after mounting the metallic balls60. Reflow process can cause the metallic balls60as the external terminals to be exposed and fixed from the insulating layer16. In this way, a terminal-attached base substrate200can be obtained. InFIGS. 4J and 4K, the surface101aand the surface101bof the insulating base substrate101are inverted with respect toFIGS. 4G to 4I.

With reference toFIG. 4K, the terminal-attached base substrate200is cut along the dicing lines106to form the individual semiconductor devices1(substrate dicing process). In the substrate dicing process, a dicing tape130is bonded to the side surface of the sealing resin layer40of the terminal-attached base substrate200to support the terminal-attached base substrate200by the use of the dicing tape130. The terminal-attached base substrate200is horizontally and vertically cut along the dicing lines106by the use of a dicing blade to form the individual pieces. InFIG. 4K, the substrate is cut by full-cut dicing, but the individual semiconductor devices1are supported by the dicing tape130. By picking up the semiconductor devices1from the dicing tape130after finishing the dicing process, it is possible to obtain the semiconductor device1shown inFIGS. 1 and 2.

As described above, in the semiconductor device1according to an embodiment of the invention, it is possible to reduce the thickness in comparison with the semiconductor device in which the semiconductor chip30is mounted on the insulating member12, by forming the opening14in the insulating member12and disposing the semiconductor chip30in the opening14. In addition, by stacking the insulating layer16on one surface of the insulating member12and stacking the sealing resin layer40on the other surface, the sealing resin layer40also expands or contracts when the insulating layer16expands or contracts. The insulating member12can be interposed between the insulating layer16and the sealing resin layer40, to improve the thermal expansion balance of the constituent elements of the semiconductor device1, thereby reducing the generation of stress or bending of the semiconductor device1. Accordingly, it is possible to prevent the connection failure of the external electrodes60, thereby improving reliability in the secondary mounting of the semiconductor device1.

In addition, the thicknesses and the CTEs of the insulating layer16and the sealing resin layer40can be adjusted to further reduce bending of the semiconductor device1.

In the semiconductor device1manufactured in the above-mentioned MAP method, the wiring base substrate100sealed is cut and separated by dicing. Thus, the side surfaces of the wiring substrate10and the sealing resin layer40are aligned to form a plan surface, thereby obtaining a good hexagonal structure.

In the method of manufacturing the semiconductor device according to an embodiment of the invention, the sealing resin layer40is stacked on one surface of the insulating member12. The sealing resin layer40covers the opening14and the semiconductor chip30. Accordingly, the semiconductor device1having a configuration, such that the semiconductor chip30is disposed in the opening14and the insulating member12is interposed between the insulating layer16and the sealing resin layer40, can easily be formed without using a semiconductor chip mounting member such as the past support tape.

The invention is not limited to the above-mentioned embodiments.

The plural electrode pads32are disposed in the vicinity of the periphery of the semiconductor chip30according to the embodiment, but a semiconductor chip having other electrode pad arrangements such as a center pad arrangement may be used.

Although it has been described in the above-mentioned embodiment that the invention is applied to the BGA-type semiconductor device, the invention may be applied to other-types of semiconductor devices such as an LGA (Land Grid Array) type.

Although the method of manufacturing a semiconductor device using a MAP method has been described in the above-mentioned embodiment, the invention is not limited to the method. For example, the individual semiconductor devices may be manufactured using insulating materials cut individually in advance instead of the insulating base material.

As used herein, the following directional terms “forward, rearward, above, downward, vertical, horizontal, below, and transverse” as well as any other similar directional terms refer to those directions of an apparatus equipped with the present invention. Accordingly, these terms, as utilized to describe the present invention should be interpreted relative to an apparatus equipped with the present invention.