Interconnects forming method and interconnects forming apparatus

The present invention provides an interconnects-forming method and an interconnects-forming apparatus which can minimize the lowering of processing accuracy in etching, minimize light exposure processing for the formation of interconnect recesses in the production of multi-level interconnects, improve the electromigration resistance of interconnects without impairing the electrical properties of the interconnects, and enhance the reliability of the device. The interconnects-forming method, includes providing interconnect recesses in an insulating film formed in a surface of a substrate; embedding an interconnect material in the interconnect recesses while forming a metal film of the interconnect material on a surface of the insulating film; removing an extra metal material other than the metal material in the interconnect recesses and flattening the substrate surface, thereby forming interconnects; forming a first protective film of a conductive material selectively on exposed surfaces of the interconnects; forming a second protective film on the surface of the substrate having the thus-formed first protective film; forming an interlevel insulating film on the surface of the substrate having the thus-formed second protective film; and flattening a surface of the interlevel insulating film.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an interconnects-forming method and an interconnects-forming apparatus, and more particularly to an interconnects-forming method and an interconnects-forming apparatus for forming interconnects by filling an interconnect material (metal) into fine recesses for interconnects formed in a surface of a substrate, such as a semiconductor wafer.

2. Description of the Related Art

In recent years, instead of using aluminum or aluminum alloys as a material for forming interconnect circuits on a substrate such as a semiconductor wafer, there is an eminent movement towards using copper (Cu) which has a low electric resistivity and high electromigration resistance. Copper interconnects are generally formed by filling copper into fine interconnect recesses formed in a surface of a substrate. Various techniques for forming such copper interconnects are known, including CVD, sputtering, and plating. According to any such technique, a copper film is formed in a substantially entire surface of a substrate, followed by removal of unnecessary copper by chemical-mechanical polishing (CMP).

In the case of interconnects formed by such a process, embedded interconnects have exposed surfaces after performing a flattening processing. When an additional embedded interconnect structure is formed on such interconnects-exposed surface of a substrate, the following problems maybe encountered. For example, during formation of a new SiO2or a low-k material in a sequence process for forming an interlevel insulating film, exposed surfaces of pre-formed interconnects are likely to be oxidized. Further, upon etching of the SiO2or the low-k material for formation of via holes, the pre-formed interconnects exposed on the bottoms of the via holes can be contaminated with an etchant, a peeled resist, and the like.

In order to avoid such problems, it has been conventional to form a protective film of SiN or the like not only on a circuit-formed region of a substrate where surfaces of interconnects are exposed, but also on an entire surface of the substrate, thereby preventing contamination of these interconnects with an etchant, and the like.

However, when a protective film of SiN or the like, which generally has a low bonding power or adhesion to an interconnect material such as copper, is formed on an entire surface of a substrate, electrons are likely to move between interconnects and the protective film caused by electromigration. Furthermore, in a semiconductor device having an embedded interconnect structure, as a protective film generally has high dielectric constant k than a dielectric constant k of the conventional interlevel insulating film, the dielectric constant of the interlevel insulating film increases, thus inducing delayed interconnections even when a low-resistivity material such as copper or silver is employed for interconnects, whereby the performance of the semiconductor device may be impaired.

In view of this, it has been proposed to selectively cover surfaces of exposed interconnects with a protective film of Co (Cobalt), a Co alloy, Ni (Nickel) or a Ni alloy, exhibiting a good adhesion to an interconnect material such as copper or silver and having a low resistivity (ρ), for example, an alloy film which is obtained by electroless plating.

FIGS. 1A through 1Dillustrate, in sequence of process steps, an example of forming such a semiconductor device having copper interconnects. As shown inFIG. 1A, an insulating film2, such as an oxide film of SiO2or a film of low-k material, is deposited on a conductive layer1aon a semiconductor base1having formed semiconductor devices. Contact holes3and interconnect trenches4for interconnect recesses are formed in the insulating film2by the lithography/etching technique. Thereafter, a barrier layer5of TaN or the like is formed on the insulating film2, and a seed layer6as an electric supply layer for electroplating is formed on the barrier layer5by sputtering or the like.

Then, as shown inFIG. 1B, copper plating is performed onto the surface of the substrate W to fill the contact holes3and the interconnect trenches4of the substrate W with copper and, at the same time, deposit a copper film7on the insulating film2. Thereafter, the barrier layer5, the seed layer6and the copper film7on the insulating film2are removed by chemical-mechanical polishing (CMP) so as to make the surface of the copper film7filled in the contact holes3and the interconnect trenches4, and the surface of the insulating film2lie substantially on the same plane. Interconnects (copper interconnects)8composed of the seed layer6and the copper film7, as shown inFIG. 1C, is thus formed in the insulating film2.

Then, as shown inFIG. 1D, electroless plating is performed onto the surface of the substrate W to form a protective film9of a Co alloy, a Ni alloy or the like on the surfaces of interconnects8selectively, thereby covering and protecting the surfaces of interconnects8with the protective film9.

However, according to the conventional process for selectively covering and protecting the exposed surfaces of interconnects with a protective film, the protective film protrudes from the surface of an insulating film whereby the surface loses its flatness. When second-level interconnects are formed on first-level interconnects in the production of a multi-level interconnect structure, irregularities reflecting the shape of a protective film are produced on the surface of an interlevel insulating film deposited on the surface of the first-level interconnects, and the irregularities of the surface of the interlevel insulating film affect the processing accuracy in later etching, light exposure or the like processing for the formation of interconnect recesses. Further, unless the film thickness of the selectively formed protective film is controlled optimally, there may occur a case where adjacent protective films are too close to each other, and trouble, such as dissolution of the protective film or a barrier layer, can occur. This may result in generation of a leakage current that can lower the electrical properties of interconnects.

SUMMARY OF THE INVENTION

The present invention has been made in view of the above situation in the related art. It is therefore an object of the present invention to provide an interconnects-forming method and an interconnects-forming apparatus which can minimize the lowering of processing accuracy in etching, light exposure or the like processing for the formation of interconnect recesses in the production of multi-level interconnects, can improve the electromigration resistance of interconnects without impairing the electrical properties of the interconnects, and can enhance the reliability of the device.

In order to achieve the above object, the present invention provides an interconnects-forming method, comprising: providing interconnect recesses in an insulating film formed in a surface of a substrate; embedding an interconnect material in the interconnect recesses while forming a metal film of the interconnect material on a surface of the insulating film; removing an extra metal material other than the metal material in the interconnect recesses and flattening the substrate surface, thereby forming interconnects; forming a first protective film of a conductive material selectively on exposed surfaces of the interconnects; forming a second protective film on the surface of the substrate having the thus-formed first protective film; forming an interlevel insulating film on the surface of the substrate having the thus-formed second protective film; and flattening a surface of the interlevel insulating film.

Flattening the surface of the interlevel insulating film can minimize the lowering of processing accuracy in later etching, light exposure or the like processing for the formation of interconnect recesses in the interlevel insulating film.

In a preferred embodiment of the present invention, interconnect recesses are provided in the interlevel insulating film, and an interconnect material is embedded in the interconnect recesses to make a multi-level interconnect structure. A highly-integrated VLSI can be produced according to this embodiment.

The flattening of the surface of the interlevel insulating film is carried out, for example, by chemical-mechanical polishing, wet etching with a chemical, or heat reflowing.

The first protective film is composed of, for example, Co, a Co alloy, Ni, a Ni alloy, Mo, a Mo alloy, Ta, a Ta alloy, Ta nitride, WN, ZrN, Ti, a Ti alloy or Ti nitride.

The second protective film is composed of, for example, SixNy, SiC, SiCN, SiCO or a borazine-silicon polymer.

Preferably, after the formation of interconnects by removing the extra metal material other than the metal material in the interconnect recesses and flattening the substrate surface, recesses for protective film are formed at the top portions of interconnects.

By forming the recesses for protective film at the top portions of interconnects and forming the first protective film selectively in the recesses for protective film to completely fill the recesses with the first protective film, it becomes possible to ensure a sufficient film thickness for the first protective film.

The recesses for protective film are formed, for example, by chemical-mechanical polishing, electrolytic polishing, dry etching with a plasma or wet etching with a chemical.

The depth of the recesses for protective film is preferably from 5 to 50 nm. This can minimize a rise in the resistance of interconnects.

The film thickness of the first protective film is preferably from 5 to 65 nm. This can optimize the height of the interconnects, whose surface is covered with the first protective film, protruding from the insulating film (interlevel insulating film).

The first protective film is preferably formed by electroless plating. This makes it possible to form a high-quality alloy film with good selectivity on the exposed interconnects.

Preferably, in advance of the electroless plating, a metal ion-containing catalyst is applied to the exposed surfaces of the interconnects. The application of a metal ion-containing catalyst to the surfaces of the interconnects enables the formation of a continuous uniform alloy film.

The film-forming rate in the electroless plating is preferably from 3 to 18 nm/min. If the film-forming rate is too high, the quality of the plated film is poor and, in addition, control of the film thickness is difficult. If the plating rate is too low, on the other hand, the consequent drop in the production throughput adversely affects the production cost. It is therefore preferred to control the processing conditions so as to attain the optimum film-forming rate of 3 to 18 nm/min.

The first protective film may have a protruding portion which protrudes from the surface of the insulating film.

Preferably, the height of the protruding portion of the first protective film from the surface plane of the insulating film is approximately equal to the film thickness of a barrier layer which has been formed on the surface of the interconnect recesses prior to the formation of the metal film.

A barrier layer, in general, is formed of Ta or TaN. Accordingly, when forming the first protective film by electroless plating, for example, the electroless plated film does not deposit on such a barrier layer. The electroless plated film, however, deposits (grows) isotropically. Thus, the first protective film grows not only in the height direction but also in the lateral direction. Accordingly, if the film thickness of the first protective film (plated film) is made too thick, it is highly likely that because of the lateral growth, adjacent first protective films (electroless plated films), formed on adjacent interconnects, come close to each other, leading to generation of a leakage current. If the film thickness of the electroless plated film is smaller than the film thickness of the barrier layer, on the other hand, the exposed end surface of the barrier layer cannot be fully covered with the first protective film; (i.e. the end surface remains partly exposed). There is, therefore, a likelihood that when the substrate is immersed in, for example, a liquid chemical or pure water, a large electrode potential difference is produced between the exposed barrier layer and the first protective film whereby due to the local cell effect, the metal can be dissolved in the liquid. When the metal is dissolved in the liquid, upon a post-treatment after the formation of the first protective film, for example, dissolved metal ions can remain on the insulating film between the interconnects, which could cause a leakage current between the interconnects.

In view of the above, the height of the protruding portion of the first protective film from the surface plane of the insulating film is set to be approximately equal to the film thickness of the barrier layer which has been formed on the surface of the interconnect recesses prior to the formation of the metal film. This makes it possible to fully cover the exposed surface of the barrier layer with the first protective film without the lateral extension of the protective film, thus obviating the above drawbacks and providing the first protective film with the optimum electrical properties.

The present invention also provides another interconnects-forming method, comprising: providing interconnect recesses in an insulating film formed in a surface of a substrate; embedding an interconnect material in the interconnect recesses while forming a metal film of the interconnect material on a surface of the insulating film; removing an extra metal material other than the metal material in the interconnect recesses and flattening the substrate surface, thereby forming interconnects; forming a first protective film of a conductive material selectively on exposed surfaces of the interconnects; forming a second protective film on the surface of the substrate having the thus-formed first protective film; flattening a surface of the second protective film; and forming an interlevel insulating film on the flattened surface of the second protective film.

Also by flattening the surface of the second protective film, the surface of the interlevel insulating film deposited thereon can be flattened, minimizing the lowering of processing accuracy in later etching, light exposure or the like processing for the formation of interconnect recesses in the interlevel insulating film.

The flattening of the surface of the second protective film is carried out, for example, by chemical-mechanical polishing or heat reflowing.

The present invention also provides still another interconnects-forming method, comprising: providing interconnect recesses in an insulating film formed in a surface of a substrate; embedding an interconnect material in the interconnect recesses while forming a metal film of the interconnect material on a surface of the insulating film; removing an extra metal material other than the metal material in the interconnect recesses and flattening the substrate surface, thereby forming interconnects; forming a first protective film of a conductive material selectively on exposed surfaces of the interconnects; forming an interlevel insulating film on the surface of the substrate having the thus-formed first protective film; and flattening a surface of the inter level insulating film.

There is a case where the interlevel insulating film is deposited directly on the surface of the substrate having the first protective film, without forming the second protective film. Also in such a case, flattening of the surface of the interlevel insulating film can minimize the lowering of processing accuracy in later etching, light exposure or the like processing for the formation of interconnect recesses in the interlevel insulating film.

The present invention also provides an interconnects-forming apparatus, comprising: an interconnects-forming unit for embedding an interconnect material in interconnect recesses provided in an insulating film formed in a surface of a substrate while forming a metal film of the interconnect material on a surface of the insulating film; a first flattening unit for removing an extra metal material other than the metal material in the interconnect recesses and flattening the substrate surface, thereby forming interconnects; a first protective film-forming unit for forming a first protective film of a conductive material selectively on exposed surfaces of the interconnects; a second protective film-forming unit for forming a second protective film on the surface of the substrate having the thus-formed first protective film; an inter level insulating film-forming unit for forming an interlevel insulating film on the surface of the substrate having the thus-formed second protective film; and a second flattening unit for flattening a surface of the interlevel insulating film.

The first protective film-forming unit is preferably comprised of an electroless plating unit comprising a plating tank, a substrate holding mechanism, an automatic substrate transport mechanism, a plating solution circulation mechanism, a plating solution temperature control mechanism, and a liquid control mechanism having a plating solution analysis/replenishment function.

Preferably, the electroless plating unit has at least one of a catalyst application treatment function, a pre-and/or post-catalyst application chemical cleaning function, a plating function, a post-plating chemical cleaning function, a post-chemical cleaning rinsing function and a substrate drying function.

The interconnects-forming apparatus may further comprise a recess processing unit which, after the formation of interconnects by removing the extra metal material other than the metal material in the interconnect recesses and flattening the substrate surface, forms recesses for protective film at the top portions of the interconnects.

The present invention also provides another interconnects-forming apparatus, comprising: an interconnects-forming unit for embedding an interconnect material in interconnect recesses provided in an insulating film formed in a surface of a substrate while forming a metal film of the interconnect material on a surface of the insulating film; a first flattening unit for removing an extra metal material other than the metal material in the interconnect recesses and flattening the substrate surface, thereby forming interconnects; a first protective film-forming unit for forming a first protective film of a conductive material selectively on exposed surfaces of the interconnects; a second protective film-forming unit for forming a second protective film on the surface of the substrate having the thus-formed first protective film; a second flattening unit for flattening a surface of the second protective film; and an interlevel insulating film-forming unit for forming an interlevel insulating film on the flattened surface of the second protective film.

The present invention also provides still another interconnects-forming apparatus, comprising: an interconnects-forming unit for embedding an interconnect material in interconnect recesses provided in an insulating film formed in a surface of a substrate while forming a metal film of the interconnect material on a surface of the insulating film; a first flattening unit for removing an extra metal material other than the metal material in the interconnect recesses and flattening the substrate surface, thereby forming interconnects; a first protective film-forming unit for forming a first protective film of a conductive material selectively on exposed surfaces of the interconnects; an interlevel insulating film-forming unit for forming an interlevel insulating film on the surface of the substrate having the thus-formed first protective film; and a second flattening unit for flattening a surface of the interlevel insulating film.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Preferred embodiments of the present invention will now be described with reference to the drawings. The embodiments illustrate the case of forming interconnect recesses, such as interconnect trenches, in a surface of a substrate, such as a semiconductor wafer, and embedding copper as an interconnect material in the interconnect recesses to form interconnects of copper.

FIG. 2shows a plan view of an interconnects-forming apparatus according to an embodiment of the present invention. As shown inFIG. 2, the interconnects-forming apparatus includes a rectangular housing12and a transport box10, such as a SMIF box or a FOUP, detachably mounted to the housing12and housing a number of substrates such as semiconductor wafers. A loading/unloading station16, which is provided with a first transport robot14as a first transport device therein, is provided in the housing12. Further, in that area within the housing12which is partitioned off from the loading/unloading station16by a partition18, there are provided an interconnects-forming unit20, a first protective film-forming unit22, a second protective film-forming unit24, an interlevel insulating film-forming unit26, a first flattening unit28and a second flattening unit30, which units are disposed on either side of a second transport robot32as a second transport device.

The housing12is made light-shielding so that the below-described processing steps can be carried out under light-shielded conditions in the housing12; (i.e., without irradiation of light, such as illuminating light, onto interconnects). This can prevent corrosion of interconnects of e.g. copper due to a photopotential difference that would be produced by light irradiation onto the interconnects.

The interconnects-forming unit20is to embed copper as an interconnect material in interconnect recesses, such as interconnect trenches, provided in an insulating film formed in a surface of a substrate while forming a metal film of copper (copper film) on a surface of the insulating film, and is comprised of, for example, an electroplating unit, an electroless plating unit, a CVD unit or a PVD unit.

The first flattening unit28is to remove an extra metal material other than the metal material in the interconnect recesses and flatten the substrate surface, thereby forming interconnects, and is comprised of, for example, a chemical-mechanical polishing (CMP) unit or an electrolytic polishing unit.

The first protective film-forming unit22is provided to form a first protective film of a conductive material selectively on exposed surfaces of interconnects, and is comprised of, for example, an electroless plating unit.

The electroless plating unit for forming the first protective film comprises at least a plating tank, a substrate holding mechanism, an automatic substrate transport mechanism, a plating solution circulation mechanism, a plating solution temperature control mechanism, and a liquid control mechanism having a plating solution analysis/replenishment function. This makes it possible to realize a stable electroless plating process automatically. Further, the electroless plating unit has at least one of a catalyst application treatment function, a pre-and/or post-catalyst application chemical cleaning function, a plating function, a post-plating chemical cleaning function, a post-chemical cleaning rinsing function and a substrate drying function. Such a unit can form a high-quality first protective film on the interconnects.

The second protective film-forming unit24is provided to form a second protective film on the surface of the substrate after the formation of the first protective film, and is comprised of, for example, a CVD unit, a PVD unit or a coating unit.

The interlevel insulating film-forming unit26is provided to form an interlevel insulating film on the surface of the substrate after the formation of the second protective film, and is comprised of, for example, a CVD unit or a coating unit.

The second flattening unit30is provided to flatten the surface of the interlevel insulating film, and is comprised of, for example, a chemical-mechanical polishing unit, a chemical wet etching unit or a heat reflowing unit.

Though in this embodiment the first flattening unit28and the second flattening unit30are provided separately, it is also possible to use, for example, one chemical-mechanical polishing unit or electrolytic polishing unit both as the first flattening unit28and as the second flattening unit30.

An interconnects (copper interconnects)-forming method according to a first embodiment of the present invention will now be described by referring toFIGS. 3A through 6.

First, as shown inFIG. 3A, interconnect recesses such as interconnect trenches42are formed by, for example, the lithography/etching technique in an insulating film40, such as an oxide film of SiO2or a film of low-k material, formed in a surface of a substrate (step1). A barrier layer44of TaN or the like is formed on a surface of the insulating film40, as shown inFIG. 3B(step2), and a (copper) seed layer46as an electric supply layer is formed by, for example, sputtering on a surface of the barrier layer44, as shown inFIG. 3C(step3). The substrate having the thus-formed seed layer46is housed in the transport box10, and the transport box10housing such substrates is transported to the housing12of the interconnects-forming apparatus and is mounted to the housing12.

Next, the substrates are taken one by one by the first transport robot14out of the transport box10and are each carried in the loading/unloading station16. Thereafter, the substrate is transported by the second transport robot32to the interconnects-forming unit20.

In the interconnects-forming unit20, as shown inFIG. 4A, the interconnect material (copper) is embedded in the interconnect trenches (interconnect recesses)42by, for example, electroplating or electroless plating while forming a metal film (copper film)48of copper on a surface of the seed layer46(step4).

The substrate having the copper film48formed in the surface is transported by the second transport robot32to the first flattening unit28. In the first flattening unit28, as shown inFIG. 4B, the extra metal material other than the metal material in the interconnect trenches42(i.e., the copper film48, the seed layer46, and the barrier layer44on the insulating film40) is removed and the substrate surface is flattened by, for example, chemical-mechanical polishing (CMP) or electrolytic polishing, thereby forming interconnects50composed of the copper film48(step5).

Next, the substrate after the formation of interconnects50by the surface flattening is transported by the second transport robot32to the first protective film-forming unit22. In the first protective film-forming unit22, as shown inFIG. 4C, a first protective film52of a conductive material, such as Co, a Co alloy, Ni, a Ni alloy, Mo, a Mo alloy, Ta, a Ta alloy, Ta nitride, WN, ZrN, Ti, a Ti alloy or Ti nitride, is formed selectively on exposed surfaces of the interconnects50by, for example, electroless plating (step6).

The use of electroless plating makes it possible to form a high-quality first protective film52of e.g. an alloy with good selectivity on the exposed surfaces of the interconnects50. It is preferred that in advance of the electroless plating, a metal ion-containing catalyst be applied to the exposed surfaces of the interconnects. The application of a metal ion-containing catalyst to the surfaces of the interconnects enables the formation of a continuous uniform first protective film52of e.g. an alloy.

The film-forming rate in the electroless plating is preferably from 3 to 18 nm/min. If the film-forming rate is too high, the quality of the plated film is poor and, in addition, control of the film thickness is difficult. If the plating rate is too low, on the other hand, the consequent drop in the production throughput adversely affects the production cost. It is therefore preferred to control the processing conditions so as to attain the optimum film-forming rate of 3 to 18nm/min. It is preferred that the film thickness T1of the first protective film52formed on the surfaces of the interconnects50be approximately equal to the film thickness T2of the barrier layer44formed on the surfaces of the interconnect trenches42(T1?T2). This can produce the first protective film52having optimum electrical properties. It is to be noted in this regard that the barrier layer44, in general, is formed of Ta or TaN. Accordingly, when forming the first protective film52by electroless plating, for example, the electroless plated film does not deposit on such a barrier layer44. The electroless plated film, however, deposits (grows) isotropically. Thus, the first protective film52grows not only in the height direction but also in the lateral direction. Accordingly, if the film thickness of the first protective film52(plated film) is made too thick, it is highly likely that because of the lateral growth, adjacent first protective films52, formed on adjacent interconnects50, come close to each other, leading to generation of a leakage current. If the film thickness of the first protective film52is smaller than the thickness of the barrier layer44, on the other hand, the exposed end surface of the barrier layer44cannot be fully covered with the first protective film52(i.e., the end surface remains partly exposed). There is, therefore, a likelihood that when the substrate is immersed in, for example, a liquid chemical or pure water, a large electrode potential difference is produced between the exposed barrier layer44and the first protective film52whereby due to the local cell effect, the metal can be dissolved in the liquid. When the metal is dissolved in the liquid, upon a post-treatment after the formation of the first protective film52, for example, dissolved metal ions can remain on the insulating film40between the interconnects50, which could cause a leakage current between the interconnects50.

In view of the above, the film thickness T1of the first protective film52(i.e., the height of the first protective film52protruding from the surface plane of the insulating film40) is set to be approximately equal to the film thickness T2of the barrier layer44formed on the surfaces of the interconnect trenches42. This makes it possible to fully cover the exposed surface of the barrier layer44with the first protective film52without the lateral extension of the protective film52, thus obviating the above drawbacks and providing the first protective film52with the optimum electrical properties.

Next, the substrate having the thus-formed first protective film52is transported by the second transport robot32to the second protective film-forming unit24. In the second protective film-forming unit24, as shown inFIG. 5A, a second protective film54as a hard mask or an etch step layer composed of, for example, SixNy, SiC, SiCN or a borazine-silicon polymer is formed on the surface of the substrate by, for example, CVD, PVD or coating (step7).

The substrate having the thus-formed second protective film54is transported by the second transport robot32to the interlevel insulating film-forming unit26. In the interlevel insulating film-forming unit26, as shown inFIG. 5B, an interlevel insulating film56is formed on the surface of the substrate by, for example, CVD or coating (step8). When the interlevel insulating film56is thus formed, irregularities reflecting the shape of the first protective film52are produced on a surface of the interlevel insulating film56, and the irregularities of the surface of the interlevel insulating film56affect the processing accuracy in later etching, light exposure or the like processing for the formation of interconnect recesses.

Accordingly, the substrate having the thus-formed interlevel insulating film56is transported by the second transport robot32to the second flattening unit30, where a surface of the interlevel insulating film56is flattened by, for example, chemical-mechanical polishing, wet etching with a chemical or heat reflowing, as shown inFIG. 5C(step9).

The interlevel insulating film56is then subjected to the same process as described above (steps1–9) to form a multi-level interconnect structure. This enables the production of a highly-integrated VLSI. The flattening of the surface of the interlevel insulating film56can minimize the lowering of processing accuracy in later etching, light exposure or the like processing for the formation of interconnect recesses in the interlevel insulating film56.

FIGS. 7A through 8illustrate an interconnects-forming method according to a second embodiment of the present invention. This embodiment differs from the above-described first embodiment in the respects described below. This embodiment employs as the second flattening unit30shown inFIG. 2a unit, comprised of, for example, a chemical-mechanical polishing unit, an electrolytic polishing unit or a heat reflowing unit, for flattening the surface of the second protective film54.

First, as with the first embodiment, interconnect trenches (interconnect recesses)42are formed in an insulating film40formed in a surface of a substrate, and a barrier layer44and a seed layer46are formed in this order on a surface of the insulating film40. Further, a metal film (copper film)48of copper is formed on a surface of the seed layer46. Thereafter, an extra metal material other than the metal material in the interconnect trenches42is removed and the substrate surface is flattened to thereby form interconnects50composed of the copper film48, and then a first protective film52is formed selectively on exposed surfaces of the interconnects50(steps1to6).

The substrate after the formation of the first protective film52is transported by the second transport robot32to the second protective film-forming unit24, where a second protective film54is formed on the surface of the substrate, as shown inFIG. 7A(step7). The substrate after the formation of the second protective film54is transported by the second transport robot32to the second flattening unit30.

In the second flattening unit30, as shown inFIG. 7B, a surface of the second protective film54is flattened by, for example, chemical-mechanical polishing, electrolytic polishing or heat reflowing (step8).

The substrate after the flattening of the surface of the second protective film54is transported by the second transport robot32to the interlevel insulating film-forming unit26, where an interlevel insulating film56is formed on the surface of the substrate, as shown inFIG. 7C(step9). Since the surface of the second protective film54has been flattened in the preceding step, the interlevel insulating film56can have a flat surface.

FIGS. 9A through 10illustrate an interconnects-forming method according to a third embodiment of the present invention. This embodiment differs from the above-described first embodiment in the respects described below. According to this embodiment, the second protective film-forming unit24shown inFIG. 2is omitted.

First, as with the first embodiment, interconnect trenches (interconnect recesses)42are formed in an insulating film40formed in a surface of a substrate, and a barrier layer44and a seed layer46are formed in this order on a surface of the insulating film40. Further, a metal film (copper film)48of copper is formed on a surface of the seed layer46. Thereafter, an extra metal material other than the metal material in the interconnect trenches42is removed and the substrate surface is flattened to thereby form interconnects50composed of the copper film48, and then a first protective film52is formed selectively on exposed surfaces of the interconnects50(steps1to6).

The substrate after the formation of the first protective film52is transported by the second transport robot32to the interlevel insulating film-forming unit26, where an interlevel insulating film56is formed on the surface of the substrate, as shown inFIG. 9A(step7). Next, the substrate after the formation of the interlevel insulating film56is transported by the second transport robot32to the second flattening unit30, where a surface of the interlevel insulating film56is flattened, as shown inFIG. 9B(step8).

There is a case where the interlevel insulating film56is deposited directly on the surface of the substrate having the first protective film52, without forming the second protective film54. Also in such a case, flattening the surface of the interlevel insulating film56can minimize the lowering of processing accuracy in later etching, light exposure or the like processing for the formatting of interconnect recesses in the interlevel insulating film56.

FIGS. 11A through 13illustrate an interconnects-forming method according to a fourth embodiment of the present invention. This embodiment differs from the above-described first embodiment in the respects described below. This embodiment employs as the first flattening unit28shown inFIG. 2, for example, a chemical-mechanical polishing unit or an electrolytic processing unit, and utilizes the chemical-mechanical polishing unit or the electrolytic polishing unit also as a recess processing unit. Instead of the chemical-mechanical polishing unit or the electrolytic polishing unit, it is also possible to employ a dry etching unit using a plasma or a wet etching unit using a liquid chemical as a recess processing unit. Such a unit may be provided exclusively for recess processing. This holds also for the embodiments described later.

First, as with the first embodiment, interconnect trenches (interconnect recesses)42are formed in an insulating film40formed in a surface of a substrate, and a barrier layer44and a seed layer46are formed in this order on the surface of the insulating film40. A metal film (copper film)48of copper is then formed on a surface of the seed layer46(steps1to5).

The substrate having the metal film48formed in the surface is transported by the second transport robot32to the first flattening unit28. In the first flattening unit28, as shown inFIG. 11A, an extra metal material other than the metal material in the interconnect trenches42(i.e., the copper film48, the seed layer46, and the barrier layer44on the insulating film40) is removed, and the substrate surface is flattened by, for example, chemical-mechanical polishing (CMP) or electrolytic polishing, thereby forming interconnects50composed of the copper film48(step5). Subsequently, interconnect recess processing is carried out in the first flattening unit28. In particular, as shown inFIG. 11B, the top portions of the interconnects50are removed, thereby forming recesses58for protective film having a depth D of e.g. 5 to 50 nm (step6).

Next, the substrate having the thus-formed recesses58for protective film is transported by the second transport robot32to the first protective film-forming unit22. In the first protective film-forming unit22, as shown inFIG. 11C, a first protective film52of a conductive material is formed selectively on exposed surfaces of the interconnects50by, for example, electroless plating, thereby filling the recesses58for protective film with the first protective film52(step7). By thus setting the depth D of the recesses58to form a protective film with a thickness of 5 to 20 nm and filling the recesses58with the first protective film52, the first protective film52having a sufficient film thickness can be formed while suppressing a rise in the resistance of the interconnects50.

As with the preceding embodiments, the first protective film52is made to protrude from the surface plane of the insulating film40such that the height H of the protruding portion of the first protective film52is approximately equal to the film thickness T2of the barrier layer44formed on the surfaces of the interconnect recesses42(H≈T2). This can produce the first protective film52having an optimum film thickness with respect to electrical properties.

The film thickness of the first protective film52is preferably made e.g. 5 to 65 nm, depending upon the depth of the recesses58for protective film. This can optimize the height of the interconnects50, whose surface is covered with the first protective film52, protruding from the insulating film (interlevel insulating film)40.

Next, the substrate having the thus-formed first protective film52is transported by the second transport robot32to the second protective film-forming unit24. In the second protective film-forming unit24, as shown inFIG. 12A, a second protective film54as a hard mask or an etch step layer is formed on the surface of the substrate by, for example, CVD, PVD or coating (step8).

The substrate having the thus-formed second protective film54is transported by the second transport robot32to the interlevel insulating film-forming unit26. In the interlevel insulating film-forming unit26, as shown inFIG. 12B, an interlevel insulating film56is formed on the surface of the substrate by, for example, CVD or coating (step9).

Next, the substrate having the thus-formed interlevel insulating film56is transported by the second transport robot32to the second flattening unit30, where a surface of the interlevel insulating film56is flattened by, for example, chemical-mechanical polishing, wet etching with a chemical or heat reflowing, as shown inFIG. 12C(step10).

FIGS. 14A through 15illustrate an interconnects-forming method according to a fifth embodiment of the present invention. This embodiment differs from the above-described fourth embodiment in the respects described below. As with the above-described second embodiment, this embodiment employs as the second flattening unit30shown inFIG. 2a unit, comprised of, for example, a chemical-mechanical polishing unit, an electrolytic polishing unit or a heat reflowing unit, for flattening the surface of the second protective film54.

First, as with the fourth embodiment, interconnect trenches (interconnect recesses)42are formed in an insulating film40formed in a surface of a substrate, and a barrier layer44and a seed layer46are formed in this order on a surface of the insulating film40. Further, a metal film (copper film)48of copper is formed on a surface of the seed layer46. Thereafter, an extra metal material other than the metal material in the interconnect trenches42is removed and the substrate surface is flattened to thereby form interconnects50composed of the copper film48. After subsequently forming recesses58for protective film at top portions of the interconnects50, a first protective film52is formed selectively on exposed surfaces of the interconnects50(steps1to7).

The substrate after the formation of the first protective film52is transported by the second transport robot32to the second protective film-forming unit24, where a second protective film54is formed on the surface of the substrate, as shown inFIG. 14A, (step8). The substrate after the formation of the second protective film54is transported by the second transport robot32to the second flattening unit30.

In the second flattening unit30, as shown inFIG. 14B, a surface of the second protective film54is flattened by, for example, chemical-mechanical polishing, electrolytic polishing or heat reflowing (step9).

The substrate after the flattening of the surface of the second protective film54is transported by the second transport robot32to the interlevel insulating film-forming unit26, where an interlevel insulating film56is formed on the surface of the substrate, as shown inFIG. 14C(step10). Since the surface of the second protective film54has been flattened in the preceding step, the interlevel insulating film56can have a flat surface.

FIGS. 16A through 17illustrate an interconnects-forming method according to a sixth embodiment of the present invention. This embodiment differs from the above-described fourth embodiment in the respects described below. According to this embodiment, as in the above-described third embodiment, the second protective film-forming unit24shown inFIG. 2is omitted.

First, as with the fourth embodiment, interconnect trenches (interconnect recesses)42are formed in an insulating film40formed in a surface of a substrate, and a barrier layer44and a seed layer46are formed in this order on a surface of the insulating film40. Further, a metal film (copper film)48of copper is formed on a surface of the seed layer46. Thereafter, the extra metal material other than the metal material in the interconnect trenches42is removed and the substrate surface is flattened to thereby form interconnects50composed of the copper film48. After subsequently forming recesses58for protective film at top portions of the interconnects50, a first protective film52is formed selectively on exposed surfaces of the interconnects50(steps1to7).

The substrate after the formation of the first protective film52is transported by the second transport robot32to the interlevel insulating film-forming unit26, where an interlevel insulating film56is formed on the surface of the substrate, as shown inFIG. 16A(step8). Next, the substrate after the formation of the interlevel insulating film56is transported by the second transport robot32to the second flattening unit30, where a surface of the interlevel insulating film56is flattened, as shown inFIG. 16B(step9).

Though the above embodiments illustrate the case of using copper as an interconnect material, it is possible to use a copper alloy, silver, a silver alloy, etc. instead of copper.

As described in detail here in above, according to the present invention, flattening the surface of an interlevel insulating film can minimize the lowering of processing accuracy in later etching, light exposure or the like processing for the formation of interconnect recesses in the interlevel insulating film in the production of multi-level interconnects. Furthermore, by optimally controlling the film thickness of a first protective film when it is formed selectively on the surfaces of inter connects, it becomes possible to improve the electro migration resistance of interconnects, without impairing the electrical properties of interconnects, and enhance the reliability of the device.