SEMICONDUCTOR DEVICE AND METHOD AND SYSTEM OF ARRANGING PATTERNS OF THE SAME

A semiconductor device, method, and system of arranging patterns of the same are provided. The method includes generating a plurality of gate patterns and conductive patterns, wherein each of the plurality of gate patterns and conductive patterns is located at a first horizontal level and extends along a first direction. The method also includes selecting one of the gate patterns as an input pin or one of the conductive patterns as an output pin. The method further includes generating, based on a selected gate pattern or a selected conductive pattern, a plurality of metallization patterns. Each of the plurality of metallization patterns is located at a second horizontal level overlying the first horizontal level and extends along a second direction substantially perpendicular to the first direction.

BACKGROUND

Industry requirements for decreased size in integrated circuits (ICs) have resulted in smaller devices which consume less power yet provide more functionality at higher speeds. The miniaturization process has also resulted in stricter design and manufacturing specifications as well as reliability challenges. Various electronic design automation (EDA) tools generate, optimize, and verify standard cell layout designs for integrated circuits while ensuring that the standard cell layout design and manufacturing specifications are met.

DETAILED DESCRIPTION

As used herein, although terms such as “first,” “second” and “third” describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms may only be used to distinguish one element, component, region, layer or section from another. Terms such as “first,” “second” and “third” when used herein do not imply a sequence or order unless clearly indicated by the context.

FIG.1illustrates a method100of manufacturing a semiconductor device, in accordance with some embodiments.FIGS.2,3,4, and5illustrate methods of manufacturing a layout of a semiconductor device, in accordance with some embodiments.

In some embodiments, method100includes operations102and104. The method begins with operation102in which a layout diagram is generated. The layout diagram is discussed in more detail as follows with respect toFIGS.2-5.

The method100continues with operation104: based on the layout diagram, in which at least one of (A) one or more photolithographic exposures are made or (B) one or more semiconductor masks are fabricated or (C) one or more components in a layer of a semiconductor device are fabricated.

As shown inFIG.2, the operation102can include operations110,120, and130. In some embodiments, operation110can include generating active patterns, gate patterns, and conductive patterns. In some embodiments, the active patterns can correspond to active regions of a semiconductor device. In some embodiments, the gate patterns can correspond to gate structures of a semiconductor device. In some embodiments, the conductive pattern can correspond to metal diffusion (MD) conductive features of a semiconductor device.

In some embodiments, the active region can include one or more fin structures for forming, for example, Fin Field-Effect Transistor (FinFET). In other embodiments, the active region can include one or more nanosheet structures. In some embodiments, the term “active region” discussed in the present disclosure may be also referred to as “OD” (oxide diffusion area).

In some embodiments, the gate structure can include a gate dielectric layer and a gate electrode layer. The gate dielectric layer may be a single layer or multiple layers. The gate dielectric layer may include silicon oxide (SiOx), silicon nitride (SixNy), silicon oxynitride (SiON), or a combination thereof The gate electrode layer can be disposed on the gate dielectric layer. The gate electrode layer can be made of conductive material, such as polysilicon, aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), or other applicable materials. In some embodiments, the gate electrode layer includes a work function layer. The work function layer is made of metal material, and the metal material may include N-work-function metal or P-work-function metal.

In some embodiments, the patterns of the MD conductive features are arranged as source/drain (S/D) contacts that are electrically connected to source regions and/or drain regions of a semiconductor device. The MD conductive feature can include a barrier layer and a conductive layer on the barrier layer. The barrier layer may include titanium, tantalum, titanium nitride, tantalum nitride, manganese nitride or a combination thereof. The conductive layer may include metal, such as tungsten (W), copper (Cu), Ru, Ir, Ni, Os, Rh, Al, Mo, Co, alloys thereof, or combinations thereof.

The operation120can include selecting at least one of the gate patterns as an input pin and/or at least one of the conductive patterns as an output pin. In some embodiments, the gate structure can be utilized to serve as a gate of a transistor, a gate of a memory, or a dummy gate. In some embodiments, the gate of a transistor (or a gate of a memory) can be imposed on a supply voltage, and electrically connected to a power source through conductive vias and metallization layers (e.g., M0, M1... etc). The gate pattern, corresponding to the aforesaid gate, can be referred to as an input pin. Similarly, the conductive pattern, corresponding to the MD conductive feature serving as, for example, a drain of a transistor or a drain of a memory, can be referred to as an output pin.

The operation130can include generating, based on a selected gate pattern or a selected conductive pattern, metallization patterns. The metallization patterns can correspond to metallization layers of a semiconductor device, such as the zero metal layer (M0). The M0of the metallization layers can be electrically connected to the gate structure or MD conductive feature through a conductive via. In this disclosure, the term “M0” or “M0 of the metallization layers” can refer to the lowest metallization layer of a semiconductor device configured to electrically connect the gate structure (or MD conductive feature) to upper metallization layers, such as M1, M2, and so on.

FIG.2A,FIG.2B, andFIG.2Cillustrate various stages of manufacturing a layout200aof a semiconductor device corresponding to operation102ofFIG.2, in accordance with some embodiments of the present disclosure.

Referring toFIG.2A, operation102can begin with forming active patterns210-1, and210-2, gate patterns220-1,220-2,220-3, and220-4, conductive patterns230-1,230-2,230-3,230-4,230-5,230-6,230-7,230-8, and230-9as well as wiring patterns241and242. Each of the active patterns210-1and210-2can extend along an X-axis and be arranged along a Y-axis. Each of the gate patterns220-1to220-4can extend along the Y-axis and be arranged along the X-axis. Each of the conductive patterns230-1to230-9can extend along the Y-axis and at least partially be arranged along the X-axis. Each of the wiring patterns241and242can extend along the X-axis and be arranged along the Y-axis. The wiring patterns241and242can be power grid (PG) patterns which represent portions of longer corresponding power grid lines of a semiconductor device which has been fabricated based on layout200a. In some embodiments, the wiring pattern241is designated for a first reference voltage and the wiring pattern242is designated for a second reference voltage. In some embodiments, the first reference voltage is VDD and the second reference voltage is VSS.

In a top-down sequence, the active patterns can be located at a first horizontal level. The gate patterns220-1to220-4as well as conductive patterns230-1to230-9can be located at a second horizontal level overlying the first horizontal level. The wiring patterns241and242can be located at a third horizontal level overlying the second horizontal level. It should be noted that the layout of the active patterns210-1,210-2, gate patterns220-1to220-4and conductive patterns230-1to230-9are merely an example, and can be modified based on requirements for fabricating a semiconductor device. As used herein, the term “first horizontal level,” “second horizontal level,” and “third horizontal level” refer to vertical positional relations of the patterns of the layout200a. Although in this disclosure, the gate patterns220-1to220-4and the conductive patterns230-1to230-9are located at the second horizontal level, the gate structure and the MD conductive feature may be located at different horizontal levels or at least partially at the same horizontal level in an actual semiconductor device.

Further, the layout200acan include routing tracks RT1, RT2, RT3, RT4, and RT5. Each of the routing tracks RT1to RT5can extend along the X-axis. The routing tracks RT1to RT5can be configured to define the location of the metallization patterns of M0, M1, M2, and so on.

It should be noted thatFIG.2Aonly illustrates a portion of a layout of a semiconductor device, or a portion of a layout within a cell. The layout200acan further include other active patterns, gate patterns, conductive patterns, or other patterns.

Referring toFIG.2B, at least one gate pattern can be selected as an input pin, and/or at least one conductive pattern can be selected as an output pin. In this embodiment, one gate and one conductive pattern are selected as input and output pins, respectively. The denotation “I” shown inFIG.2Bcan refer to an input pin. The denotation “ZN” shown inFIG.2Bcan refer to an output pin. In this embodiment, the gate pattern220-3is selected as an input pin, and the conductive pattern230-5is selected as an output pin as shown inFIG.2B. In other embodiments, two or more gate patterns220-1to220-4can be selected as input pins. In other embodiments, two or more conductive patterns230-1to230-9can be selected as output pins. The number of the input and/or output pins is not intended to be limiting.

Referring toFIG.2C, based on the selected gate pattern and/or the selected conductive pattern, metallization patterns of M0can be generated accordingly. As described, the M0of the metallization layer can be the lowest metallization layer to electrically connect the gate structure (or MD conductive feature) to upper metallization layers, such as M1, M2, and so on. The metallization patterns of M0can extend along the X-axis . The metallization patterns of M0can be located at the third horizontal level overlying the second horizontal level.

In some embodiments, when input and/or output pins of a semiconductor device are selected, metallization patterns of M0can be generated to connect aforesaid input and/or output pins. As shown inFIG.2C, the routing track RT2can be selected, thereby forming a metallization pattern240-2extending along the routing track RT2. The metallization pattern240-2can serve as an output pin electrically connected to the selected conductive pattern230-5. Further, the routing track RT4can be selected, thereby forming a metallization pattern240-4along the routing track RT4. The metallization pattern240-4can serve as an input pin electrically connected to the selected gate pattern220-3. In this embodiments, routing tracks RT1-RT5can be selected based on the selected gate patterns and/or conductive patterns of a semiconductor device. For example, the routing track RT2is selected to form the metallization pattern240-2, thereby connecting the conductive pattern230-5and a selected gate pattern in another cell (not shown). In other embodiments, other routing tracks, such as RT1and RT3, can be selected to serve as input and output pins electrically connected to the selected gate pattern220-3and conductive pattern230-5, respectively. In some embodiments, the metallization patterns240-2and240-4can have different lengths along the X-axis.

In some embodiments, after the metallization patterns240-2and240-4are formed, interconnection patterns254-1and252-1can be generated accordingly, thereby connecting the metallization pattern240-2and conductive pattern230-5as well as the metallization pattern240-4and gate pattern220-3, respectively. The interconnection pattern can correspond to a conductive via, and be located at a horizontal level between those of the gate pattern220-1to220-5and the metallization pattern of M0(e.g.,240-2). As shown inFIG.2C, the gate pattern220-3, interconnection pattern252-1, and metallization pattern240-4overlap along the Z direction. The conductive pattern230-5, interconnection pattern254-1, and metallization pattern240-2overlap along a Z-axis. In some embodiments, the interconnection pattern (e.g.,252-1), connecting the gate pattern and metallization pattern of M0, can be referred to as “VG.” In some embodiments, the interconnection pattern (eg.,254-1), connecting the conductive pattern and metallization pattern of M0, can be referred to as “VD.”

In a comparative method of generating a layout of a semiconductor device, the metallization patterns of M0are predetermined, and have fixed shapes. For example, all of the metallization patterns of M0along the routing tracks RT1to RT5have the same lengths. In a comparative method, the metallization patterns of M0are the lowest patterns to be selected as input and output pins. Thus, in order to connect the selected input and output pins of the metallization patterns of M0, the layout of the upper metallization patterns, such as M1, are designed to connect input and output pins. In the comparative example, only the layouts of the metallization patterns of M1and/or higher metallization patterns (e.g., M2) are flexible to design a routing path to electrically connect different components. Further, in the comparative example, the layout of the metallization patterns of M0is predetermined or fixed, and cannot be allowed to cross from one cell to another cell in order to meet design rules of the process technology. In this embodiment, the gate pattern and/or the conductive pattern can be the lowest pattern to be defined as the input and/or output pin. Thus, the layout of the metallization patterns of M0is not predetermined in comparison with the comparative examples, contributing to freedom in the layout of the metallization patterns of M0.

FIG.3is a flowchart of a method for manufacturing a layout of a semiconductor device according to various aspects of the present disclosure. More particularly, the method ofFIG.3shows operations120and130ofFIG.2in more detail, in accordance with one or more embodiments.

In some embodiments, operation120can include operation121, and operation130can include operations131,132, and138. In some embodiments, the operation121can include selecting at least one of the gate patterns as an input pin. From operation121, the flow proceeds to operation131. In some embodiments, operation131can include selecting at least one routing track to generate a metallization pattern of M0as the input pin. In some embodiments, operation132can include generating an interconnection pattern to connect the selected gate pattern and the metallization pattern of M0. In some embodiments, operation138can include generating metallization patterns of M0of unoccupied routing tracks based on the semiconductor fabrication requirement.

FIG.3A,FIG.3B, andFIG.3Cillustrate various stages of manufacturing a layout200bof a semiconductor device corresponding to the method ofFIG.3, in accordance with some embodiments of the present disclosure.

Referring toFIG.3A, in some embodiments, the output pins of conductive patterns and some of the metallization patterns of M0can be predetermined, resulting in input pin(s) of the gate patterns and some of the metallization patterns of M0to be unrestricted. For example, the conductive patterns230-2and230-7may be selected as output pins. The routing tracks RT1and RT5are selected to form metallization patterns240-1and240-5as output pins. The interconnection patterns254-1and254-2are generated to connect the selected metallization patterns of M0and conductive patterns. Further, an upper metallization pattern260is generated to connect the conductive patterns230-2and230-7. The metallization pattern260can correspond to the first metal layer (M1) of a semiconductor device, and located at a fourth horizontal level overlying the third horizontal level. In this embodiment, the input pin of the gate pattern is not predetermined. In this embodiment, at least one of the gate patterns220-1to220-4can be selected as an input pin. For example, the gate pattern220-3can be selected as an input pin.

Referring toFIG.3B, one of routing tracks RT1to RT5can be selected to generate a metallization pattern as the input pin in accordance with some embodiments. As shown inFIG.3B, since all of the space of routing tracks RT1and RT5is utilized to form the metallization patterns240-1and240-5, one of the routing tracks RT2, RT3, and RT4can be selected as the input pin. For example, the routing track RT2can be selected to form the metallization pattern240-2. Further, the interconnection pattern252-1can be generated accordingly to connect the selected gate pattern220-3and metallization pattern240-2.

Referring toFIG.3C, metallization patterns of remaining unoccupied routing tracks can be generated based on semiconductor fabrication requirements in accordance with some embodiments. After the formation of input and output pins of the metallization patterns of M0, the remaining space of the routing tracks RT1to RT5, which is not occupied by the input and output pins of the metallization patterns, can be utilized to form metallization patterns of M0. These metallization patterns of M0can correspond to dummy metallization layers or intra-cell wiring patterns, which can be an intra-cell conductor in a corresponding cell region in a semiconductor device having been fabricated based on a larger layout diagram which includes layout200b. An intra-cell conductor is different than an input or an output pin. In the embodiment shown inFIG.3C, the routing tracks RT2, RT3, and RT4can be selected to generate the metallization patterns of M0serving as dummy patterns, intra-cell wiring patterns, or other wiring patterns. For example, the routing tracks RT3and RT4can be selected to form metallization patterns240-3and240-4. In other embodiments, one or more routing tracks can be selected to be free from formation of metallization patterns of M0.

FIG.4is a flowchart of a method for manufacturing a layout of a semiconductor device according to various aspects of the present disclosure. More particularly, the method ofFIG.4shows operations120and130ofFIG.2in more detail, in accordance with one or more embodiments.

In some embodiments, operation120can include operation122, and operation130can include operations133,134, and138. In some embodiments, the operation122can include selecting at least one of the conductive patterns as an output pin. From operation122, the flow proceeds to operation133. In some embodiments, operation133can include selecting at least one of routing tracks to generate a metallization pattern of M0as the output pin. In some embodiments, operation134can include generating an interconnection pattern to connect the selected conductive pattern and the metallization pattern of M0. From operation134, the flow can proceed to operation138.

FIG.4A,FIG.4B, andFIG.4Cillustrate various stages of manufacturing a layout200cof a semiconductor device corresponding to the method ofFIG.4, in accordance with some embodiments of the present disclosure.

Referring toFIG.4A, in some embodiments, the input pins of gate patterns and some of the metallization patterns of M0can be predetermined, contributing to output of the conductive patterns and some of the metallization patterns of M0to be unrestricted. For example, the gate patterns220-2,220-3, and220-4may be selected as input pins. The routing tracks RT2and RT3are selected to form metallization patterns240-2(a),240-2(b) and240-3as input pins. The interconnection patterns252-1,252-2and252-3are generated to connect the selected metallization patterns of M0and gate patterns. Further, a cut pattern270-1can be generated to identify locations of metallization patterns240-2(a) and240-2(b), or identify locations of corresponding metallization layers of M0. In this embodiment, the output pin of the conductive pattern is not predetermined. In this embodiment, at least one of the conductive patterns230-1to230-9can be selected as an output pin. For example, the conductive pattern230-5can be selected as an output pin.

Referring toFIG.4B, one of routing tracks RT1to RT5can be selected to generate a metallization pattern as the output pin in accordance with some embodiments. As shown inFIG.4B, since all of the space of routing tracks RT2and RT3is utilized to form the metallization patterns240-2(s),240-2(b), and240-3, one of the routing tracks RT1, RT4, and RT5can be selected as the output pin. For example, the routing track RT1can be selected to form the metallization pattern240-1. Further, the interconnection pattern254-1can be generated accordingly to connect the selected conductive pattern230-5and metallization pattern240-1.

Referring toFIG.4C, metallization patterns of unoccupied routing tracks can be generated based on semiconductor fabrication requirements in accordance with some embodiments. After the formation of input and output pins of the metallization patterns of M0, the remaining space, which is not occupied by the input and output pins of the metallization patterns of M0, can be utilized to form metallization patterns of M0. In the embodiment shown inFIG.4C, the routing tracks RT4and RT5can be selected to generate the metallization patterns of M0serving as dummy patterns, intra-cell wiring patterns, or other wiring patterns. For example, the routing tracks RT4and RT5can be selected to form metallization patterns240-4and240-5.

FIG.5is a flowchart of a method for manufacturing a layout of a semiconductor device according to various aspects of the present disclosure. More particularly, the method ofFIG.5shows operations120and130ofFIG.2in more detail, in accordance with one or more embodiments.

In some embodiments, operation120can include operation123, and operation130can include operations135,136,137and138. In some embodiments, the operation123can include selecting at least one of the gate patterns as an input pin and at least one of the conductive patterns as an output pin. From operation123, the flow proceeds to operation135. In some embodiments, operation135can include selecting routing tracks to generate metallization patterns as the output pin and input pin. In some embodiments, operation136can include generating interconnection patterns to connect the selected gate pattern to the metallization pattern, and connect the selected conductive pattern to the metallization pattern. In some embodiments, operation137can include generating cut pattern(s). In some embodiments, operation137can further include operation1371in which the locations of the cut pattern are determined. From operation1371, the flow can proceed to operation138.

FIG.5AandFIG.5Billustrate various stages of manufacturing a layout200dof a semiconductor device corresponding to the method ofFIG.5, in accordance with some embodiments of the present disclosure.

Referring toFIG.5A, in some embodiments, the input pin(s) of gate patterns, the output pin(s) of the conductive pattern, and metallization patterns of M0serving as the input and output pins, the interconnection patterns of the VG and VD can be predetermined, resulting in cutting pattern(s) being unrestricted. For example, the gate patterns220-2,220-3, and220-4may be selected as input pins. The routing tracks RT2and RT3are selected to form metallization patterns240-2(a),240-2(b) and240-3as input pins. The interconnection patterns252-1,252-2and252-3are generated to connect the selected metallization patterns of M0and gate patterns. A cut pattern270-1can be generated to identify locations of metallization patterns240-2(a) and240-2(b). Further, the conductive patterns230-5can be selected as an output pin. The routing track RT4is selected to form metallization pattern240-4as an output pin. The interconnection pattern254-1is generated to connect the selected metallization patterns of M0and conductive pattern.

Referring toFIG.5B, a cut pattern270-2can be generated to form metallization patterns240-4(a) and240-4(b). In some embodiments, the location of the cut pattern270-2can be selected based on the selected gate and conductive patterns or on semiconductor fabrication requirements. As shown inFIG.5B, the cut pattern270-2, the gate pattern220-3, and the metallization pattern240-4overlap so that the metallization pattern240-4(a) can have the rightmost end at the gate pattern220-3, and the metallization pattern240-4(b) can have the leftmost end at the gate pattern220-3. In other embodiments, the location of the cut pattern270-2can be selected to overlap other gate patterns or conductive patterns so that the locations and lengths of the metallization patterns240-4(a) and240-4(b) can be controlled. In this embodiment, the shape of the metallization patterns of M0can be determined by the location of the cut pattern270-2. In this embodiment, the length of the metallization patterns of M0can be determined by the location of the cut pattern270-2. In this embodiment, the interconnection patterns of the VG and VD are predetermined, resulting in the cut pattern being unrestricted.

FIG.6is a flowchart of a method for manufacturing a semiconductor device according to various aspects of the present disclosure.

In some embodiments, operation102can include operations122,152,154,156, and158. From operation122, the flow can proceed to operation152. In some embodiments, operation152can include determining whether two active patterns are connected by upper metallization patterns of M1or higher metallization patterns rather than by metallization patterns of M0. Next, based on the determination of operation152, operation154or158is performed. In some embodiments, when it is determined that two active patterns are connected by upper metallization patterns of M1or higher metallization patterns, operations154and156are performed in order. In some embodiments, operation154can include forming a cut pattern on the conductive pattern. In some embodiments, operation156can include generating metallization patterns of M0and M1and interconnection patterns to connect the active patterns. In some embodiments, when it is determined that two active patterns are connected by metallization patterns of M0, operation158is performed. In some embodiments, operation158can include generating a conductive pattern and interconnection patterns to connect the active patterns.

FIG.6AandFIG.6Billustrate various stages of manufacturing a layout200eor200fof a semiconductor device corresponding to the method ofFIG.6, in accordance with some embodiments of the present disclosure.

Referring toFIG.6A, when it is determined that the active patterns210-1and210-2are connected by the metallization patterns of M1, a cut pattern280can be generated to define the locations of conductive patterns230-5and230-10. The cut pattern280can be utilized to identify a length and location of the conductive patterns. The cut pattern280can also be referred to as “cut-MD.” Interconnection patterns254-1and254-2can be generated accordingly. The routing tracks RT1and RT5can be selected to determine the shape of the metallization patterns240-1and240-2. Further, an upper metallization pattern260, such as the first metal layer (M1), is generated to connect the conductive patterns230-5and230-10. Other interconnection patterns (not shown), connecting the conductive patterns230-5and230-10to the upper metallization pattern260, can be generated. As a result, the active patterns210-1and210-2can be connected using the upper metallization pattern260, thereby forming the layout200e. In this embodiment, the upper metallization pattern260in M1can be selected as an output pin.

Referring toFIG.6B, when it is determined that two active patterns are connected using metallization patterns of MD, the cut pattern280shown inFIG.6Acan be omitted. The conductive patterns230-5and230-10can be connected through the conductive pattern230-11. Interconnection pattern254-1can then be used to access the newly formed connection of conductive patterns230-5,230-10, and230-11from M0layer by means of the metallization pattern240-1. The routing track RT1can be selected to determine the shape of the metallization pattern240-1, thereby forming the layout200f. In this embodiment, the conductive patterns230-5,230-10, and230-11can be selected as an output pin. In this embodiment, the metallization patterns240-1is flexible and can be located on different available routing tracks RT1-RT5. In this embodiment, the active patterns can also be selected as an output pin, allowing layout design of a semiconductor device to be more flexible.

FIG.7is a top view of a layout300a semiconductor device, in accordance with some embodiments.

In some embodiments, the layout300can include cells310and320. It should be noted that a portion of the cells310and320and some patterns therein have been omitted for brevity. In some embodiments, a gate pattern311within the cell310is selected as an input pin, and a conductive pattern322within the cell320is selected as an output pin. In some embodiments, the routing track RT3can be selected to form a metallization pattern330, which corresponds to the M0of a semiconductor device, connecting the gate pattern311and the conductive pattern322. In some embodiments, the metallization pattern330can extend continuously from the cell310to the cell320. In some embodiments, the metallization pattern330can extend between the cells310and320In some embodiments, the metallization pattern330can extend across a space between the cells310and320.

FIG.8is a block diagram of a system400of designing a semiconductor device, in accordance with some embodiments. The system400can include, for example, an electronic design automation (EDA) system.

In some embodiments, system400includes an automatic placement and routing (APR) system. Methods described herein of generating PG layout diagrams, in accordance with one or more embodiments, are implementable, for example, using the system400, in accordance with some embodiments.

In some embodiments, system400is a general purpose computing device including a hardware processor402and a non-transitory, computer-readable storage medium404. Storage medium404, amongst other things, is encoded with, i.e., stores, computer program code406, i.e., a set of executable instructions. Execution of instructions406by hardware processor402represents (at least in part) an EDA tool which implements a portion or all of a method according to an embodiment, e.g., the methods described herein in accordance with one or more embodiments. (hereinafter, the noted processes and/or methods).

Processor402is electrically coupled to computer-readable storage medium404via a bus408. Processor402is also electrically coupled to an I/O interface410by bus408. A network interface412is also electrically connected to processor402via bus408. Network interface412is connected to a network414, so that processor402and computer-readable storage medium404are capable of connecting to external elements via network414. Processor402is configured to execute computer program code406encoded in computer-readable storage medium404in order to cause system400to be usable for performing a portion or all of the noted processes and/or methods. In one or more embodiments, processor402is a central processing unit (CPU), a multi-processor, a distributed processing system, an application specific integrated circuit (ASIC), and/or a suitable processing unit.

In one or more embodiments, storage medium404stores computer program code (instructions)406configured to cause system400(where such execution represents (at least in part) the EDA tool) to be usable for performing a portion or all of the noted processes and/or methods In one or more embodiments, storage medium404also stores information which facilitates performing a portion or all of the noted processes and/or methods. In one or more embodiments, storage medium404stores library407of standard cells including such standard cells as disclosed herein and one or more layout diagrams408such as are disclosed herein.

System400also includes network interface412coupled to processor402. Network interface412allows system400to communicate with network414, to which one or more other computer systems are connected. Network interface412includes wireless network interfaces such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or wired network interfaces such as ETHERNET, USB, or IEEE-1364. In one or more embodiments, a portion or all of noted processes and/or methods, is implemented in two or more systems400.

System400is configured to receive information through I/O interface410. The information received through I/O interface410includes one or more of instructions, data, design rules, libraries of standard cells, and/or other parameters for processing by processor402. The information is transferred to processor402via bus408. System400is configured to receive information related to a UI through I/O interface410. The information is stored in computer-readable medium404as user interface (UI)442.

FIG.9is a block diagram of a semiconductor device manufacturing system500, and a semiconductor device flow associated therewith, in accordance with some embodiments. In some embodiments, based on a layout diagram, at least one of (A) one or more semiconductor masks or (B) at least one component in a layer of a semiconductor integrated circuit is fabricated using manufacturing system500.

InFIG.9, ICmanufacturing system500includes entities, such as a design house520, a mask house530, and an IC manufacturer/fabricator (“fab”)550, that interact with one another in the design, development, and manufacturing cycles and/or services related to manufacturing an IC device560. The entities in system500are connected by a communications network. In some embodiments, the communications network is a single network. In some embodiments, the communications network is a variety of different networks, such as an intranet and the Internet. The communications network includes wired and/or wireless communication channels. Each entity interacts with one or more of the other entities and provides services to and/or receives services from one or more of the other entities. In some embodiments, two or more of design house520, mask house530, and IC fab550is owned by a single larger company. In some embodiments, two or more of design house520, mask house530, and IC fab550coexist in a common facility and use common resources.

Design house (or design team)520generates an IC design layout diagram522. IC design layout diagram522includes various geometrical patterns designed for an IC device560. The geometrical patterns correspond to patterns of metal, oxide, or semiconductor layers that make up the various components of IC device560to be fabricated. The various layers combine to form various IC features. For example, a portion of IC design layout diagram522includes various IC features, such as an active region, gate electrode, source and drain, metal lines or vias of an interlayer interconnection, and openings for bonding pads, to be formed in a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate. Design house520implements a proper design procedure to form IC design layout diagram522. The design procedure includes one or more of logic design, physical design or place and route. IC design layout diagram522is presented in one or more data files having information of the geometrical patterns. For example, IC design layout diagram522can be expressed in a GDSII file format or DFII file format.

Mask house530includes data preparation532and mask fabrication544. Mask house530uses IC design layout diagram522to manufacture one or more masks545to be used for fabricating the various layers of IC device560according to IC design layout diagram522. Mask house530performs mask data preparation532, where IC design layout diagram522is translated into a representative data file (“RDF”). Mask data preparation532provides the RDF to mask fabrication544. Mask fabrication544includes a mask writer. A mask writer converts the RDF to an image on a substrate, such as a mask (reticle)545or a semiconductor wafer553. The design layout diagram522is manipulated by mask data preparation532to comply with particular characteristics of the mask writer and/or requirements of IC fab550. InFIG.9, mask data preparation532and mask fabrication544are illustrated as separate elements. In some embodiments, mask data preparation532and mask fabrication544can be collectively referred to as mask data preparation.

In some embodiments, mask data preparation532includes a mask rule checker (MRC) that checks the IC design layout diagram522that has undergone processes in OPC with a set of mask creation rules which contain certain geometric and/or connectivity restrictions to ensure sufficient margins, to account for variability in semiconductor manufacturing processes, and the like. In some embodiments, the MRC modifies the IC design layout diagram522to compensate for limitations during mask fabrication544, which may undo part of the modifications performed by OPC in order to meet mask creation rules.

It should be understood that the foregoing description of mask data preparation532has been simplified for the purposes of clarity. In some embodiments, data preparation532includes additional features such as a logic operation (LOP) to modify the IC design layout diagram522according to manufacturing rules. Additionally, the processes applied to IC design layout diagram522during data preparation532may be executed in a variety of different orders.

After mask data preparation532and during mask fabrication544, a mask545or a group of masks545are fabricated based on the modified IC design layout diagram522. In some embodiments, mask fabrication544includes performing one or more lithographic exposures based on IC design layout diagram522. In some embodiments, an electron-beam (e-beam) or a mechanism of multiple e-beams is used to form a pattern on a mask (photomask or reticle)545based on the modified IC design layout diagram522. Mask545can be formed in various technologies. In some embodiments, mask545is formed using binary technology. In some embodiments, a mask pattern includes opaque regions and transparent regions. A radiation beam, such as an ultraviolet (UV) beam, used to expose the image sensitive material layer (eg., photoresist) which has been coated on a wafer, is blocked by the opaque region and transmits through the transparent regions. In one example, a binary mask version of mask545includes a transparent substrate (eg., fused quartz) and an opaque material (e.g., chromium) coated in the opaque regions of the binary mask. In another example, mask545is formed using a phase shift technology. In a phase shift mask (PSM) version of mask545, various features in the pattern formed on the phase shift mask are configured to have proper phase difference to enhance the resolution and imaging quality. In various examples, the phase shift mask can be attenuated PSM or alternating PSM. The masks generated by mask fabrication544are used in a variety of processes. For example, such a mask(s) can be used in an ion implantation process to form various doped regions in semiconductor wafer553, in an etching process to form various etching regions in semiconductor wafer553, and/or in other suitable processes.

IC fab550includes wafer fabrication552. IC fab550is an IC fabricator that includes one or more manufacturing facilities for the fabrication of a variety of different IC products. In some embodiments, IC Fab550can be a semiconductor foundry. For example, there may be a manufacturing facility for the front end fabrication of a plurality of IC products (front-end-of-line (FEOL) fabrication), while a second manufacturing facility may provide the back end fabrication for the interconnection and packaging of the IC products (back-end-of-line (BEOL) fabrication), and a third manufacturing facility may provide other services for the foundry business.

Some embodiments of the present disclosure provide a method of arranging patterns of a semiconductor device. The method includes generating a plurality of gate patterns corresponding to a set of gate structures of the semiconductor device and a plurality of conductive patterns corresponding to a set of metal diffusion (MD) conductive features of the semiconductor device. Each of the plurality of gate patterns and conductive patterns is located at a first horizontal level and extends along a first direction. The method also includes selecting one of the gate patterns as an input pin or one of the conductive patterns as an output pin. The method further includes generating, based on a selected gate pattern or a selected conductive pattern, a plurality of metallization patterns corresponding to a set of first metallization layers of the semiconductor device. Each of the plurality of metallization patterns is located at a second horizontal level overlying the first horizontal level and extends along a second direction substantially perpendicular to the first direction.

Some embodiments of the present disclosure provide a system for arranging patterns of a semiconductor device. The system includes at least one processing unit and at least one memory including computer program code for one or more programs. The at least one memory, the computer program code and the at least one processing unit are configured to cause the system to perform: generating a plurality of gate patterns corresponding to a set of gate structures of the semiconductor device and a plurality of conductive patterns corresponding to a set of metal diffusion (MD) conductive features of the semiconductor device, wherein each of the plurality of gate patterns and conductive patterns is located at a first horizontal level and extends along a first direction; selecting one of the gate patterns as an input pin or one of the conductive patterns as an output pin; and generating, based on a selected gate pattern or a selected conductive pattern, a plurality of metallization patterns corresponding to a set of first metallization layers of the semiconductor device, wherein each of the plurality of metallization patterns is located at a second horizontal level overlying the first horizontal level and extends along a second direction substantially perpendicular to the first direction.

Some embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes a first cell. The first cell includes a plurality of gate structures, metal diffusion (MD) conductive features, and first metallization layers. The gate structures are located at a first horizontal level and extend along a first direction. The MD conductive features are located at the first horizontal level and extend along the first direction. The first metallization layers are located at a second horizontal level overlying the first horizontal level and extend along a second direction substantially orthogonal to the first direction. At least one of the first metallization layers is electrically connected to one of the plurality of gate structures or one of the MD conductive features through a conductive via. The plurality of first metallization layers includes a first metallization layer with a first length along the second direction and a second metallization layer with a second length, along the second direction, different from the first length.