Semiconductor image sensor module and method of manufacturing the same

The present invention provides a CMOS type semiconductor image sensor module in which the aperture ratio of the pixel is improved and at the same time chip use efficiency is attempted to be improved and furthermore, simultaneous shuttering of all the pixels is made possible, and a method of manufacturing the same. The semiconductor image sensor module of the present invention is constituted by laminating a first semiconductor chip including an image sensor in which a plurality of pixels, each constituted by a photoelectric conversion element and transistors, are arranged, and a second semiconductor chip including an A/D converter array. Preferably, a third semiconductor chip including a memory element array is further laminated. Also, a semiconductor image sensor module of the present invention is constituted by laminating a first semiconductor chip provided with the aforesaid image sensor and a fourth semiconductor chip provided with an analog type nonvolatile memory array.

TECHNICAL FIELD

The present invention relates to a semiconductor image sensor module and a method of manufacturing the same. In more detail, it relates to a semiconductor image sensor module which realizes simultaneous shuttering meeting speeding up of the shutter speed of, for example, a digital still camera, a video camera, a mobile phone with a camera or the like.

BACKGROUND ART

Since a CMOS image sensor operates with a single power supply in low power consumption as compared with a CCD image sensor and can be manufactured by a standard CMOS process, there is an advantage that a system on chip is easy. In recent years, a CMOS image sensor has started to be used based on this advantage even in a high-grade single lens reflex type digital still camera and a mobile phone.

InFIG. 54andFIG. 55, simplified constitutions of a CCD image sensor and a CMOS image sensor are shown respectively.

A CCD image sensor1shown inFIG. 54is formed in a constitution that a plurality of light receiving sensors (photoelectric conversion elements)3which become pixels are arranged regularly in an imaging region2, for example, in a two dimensional matrix form and at the same time, vertical transfer registers4of a CCD structure which transfer signal charges in the vertical direction are arranged corresponding to respective light receiving sensor columns, further, a horizontal transfer register5of a CCD structure which is connected with respective vertical transfer registers4and which transfers signal charges in the horizontal direction is arranged, and an output unit6converting charge voltages to voltage signals and outputting the voltage signals is connected at the final stage of this horizontal transfer register5. In this CCD image sensor1, light received by the imaging region2is converted to signal charges in respective light receiving sensors3and is accumulated, and the signal charges of these respective light receiving sensors3are read out to the vertical transfer registers4through a readout gate portion7and are transferred in the vertical direction. Also, signal charges read out from the vertical transfer registers4to the horizontal transfer register5on a line-to-line basis are transferred in the horizontal direction, converted to voltage signals by the output unit6, and outputted as image signals.

On the other hand, a CMOS image sensor11shown inFIG. 55is constituted by being provided with an imaging region13in which a plurality of pixels12are arranged, a control circuit14, a vertical drive circuit15, a column unit16, a horizontal drive circuit17, and an output circuit18. In the imaging region13, a plurality of pixels12are regularly arranged two dimensionally, for example, in a two dimensional matrix form. Each pixel12is formed by a photoelectric conversion element (for example, photodiode) and a plurality of MOS transistors. The control circuit14receives an input clock, and data for instructing an operation mode or the like, and also outputs data including information of the image sensor.

In this CMOS image sensor11, a line of pixels12is selected by a drive pulse from the vertical drive circuit15, and outputs of the pixels12of the selected line are transmitted to the column unit16through vertical selection lines21. In the column unit16, column signal processing circuits19are arranged corresponding to the columns of pixels and receive signals of the pixels12for one line, and processes such as CDS (Correlated Double Sampling: process for eliminating fixed pattern noise), signal amplification, analog/digital (AD) conversion or the like are applied to the signals. Then, the column signal processing circuits19are sequentially selected by the horizontal drive circuit17, and signals thereof are introduced to a horizontal signal line20and are outputted from the output circuit18as image signals.

There are shown, inFIGS. 56A and 56B, accumulation timing charts of pixel lines corresponding to respective scanning lines of the CCD image sensor1and the CMOS image sensor11. In the case of the CCD image sensor1, signal charges are accumulated in respective light receiving sensors3during the same period, and the signal charges are read out from the light receiving sensors3to the vertical transfer register4for all the pixels simultaneously. More specifically, as shown inFIG. 56A, signal charges of the pixels of all the lines are accumulated at the same time instant during an accumulation period of a certain frame. Thereby, simultaneity of accumulation is obtained, and simultaneous electronic shuttering is made possible.

On the other hand, in the case of the CMOS image sensor11, due to its fundamental operation method, the pixel12which has outputted a signal starts accumulation of a photoelectrically converted signal again from that time point, so that as shown inFIG. 56B, accumulation periods are shifted in accordance with scanning timings in a certain frame period. Owing to this fact, simultaneity of accumulation is not obtained, and simultaneous electronic shuttering cannot be obtained. More specifically, in the CMOS image sensor11, because a vertical transfer register which delays the transfer timing as in the case of the CCD image sensor is not provided, timing for transmitting data to the column signal processing circuit is adjusted by adjusting the pixel accumulation period in accordance with the reset timing. For this reason, it is necessary to shift accumulation periods of signal charges, and a simultaneous shutter configuration to perform charge accumulation of all the pixels at the same timing cannot be realized (see page 179 of Non-patent Document 1).

In particular, this difference comes out when imaging a moving picture at a high speed.FIGS. 57A and 57Bshow recorded pictures when a fan rotating at a high speed is recorded with a CCD image sensor and a CMOS image sensor. As can be appreciated from the same drawings, a fan25recorded by the CCD image sensor is recorded normally, but the fan25recorded by the CMOS image sensor is recorded distorted in its shape (see page 180 of Non-patent Document 1).

[Non-patent Document 1] ┌Basic and Application of CCD/CMOS Image Sensor┘ by Kazuya Yonemoto, published from CQ Publishing Kabushiki-kaisha on Aug. 10, 2003, pages 179 to 180

As a countermeasure for imaging a picture moving at a high speed in the above-mentioned CMOS image sensor, there has been proposed a constitution shown inFIG. 52andFIG. 53. This CMOS image sensor31is a one applied to a front-illuminated type CMOS image sensor, and as shown in a plane block layout of FIG.52, it is constituted by forming in a necessary region of one semiconductor chip, an imaging region, a so-called photodiode PD/sensor circuit region32, in which pixels, each of which is composed of a photodiode as a photoelectric conversion element and a plurality of MOS transistors, are arranged, and an ADC/memory region33in which a plurality of analog/digital (AD) conversion circuits connected with respective pixels and memory means are arranged, adjacent to this photodiode PD-sensor circuit region32.

There is shown inFIG. 53a cross section structure of a unit pixel of the CMOS image sensor31. In this example, it is constituted as a front-illuminated type by forming a p-type semiconductor well region36in an n-type semiconductor substrate35; a unit pixel38composed of a photodiode PD and a plurality of MOS transistors Tr in a p-type semiconductor well region36of each region which is partitioned by a pixel separation region37; a multilayer wiring layer39in which multilayers, for example, a first layer wiring441, a second layer wiring442, and a third layer wiring443are formed, on the substrate front face side, through an interlayer insulation film43; and further a color filter41and an on-chip microlens42on the multiplayer wiring layer39. The photodiode PD is constituted by a buried type photodiode having an n-type semiconductor region46, and a p+ semiconductor region47that becomes an accumulation layer on the front face. Although not shown, it is possible to make the MOS transistors Tr constituting a pixel, for example, as a 3 transistor structure including a readout transistor, a reset transistor, and an amplifier transistor, or a 4 transistor structure in which a vertical selection transistor is further added.

In this CMOS image sensor31, it is constituted such that after photoelectric conversion is carried out by the photodiode, analog/digital conversion is carried out at once and simultaneously, and the signal is held in the memory means as data, and thereafter, the data is read out from the memory means sequentially. In this constitution, because the signal which has been analog-to-digital converted is once held in the memory means and thereafter signal processing is carried out, simultaneous shuttering is made possible.

However, in the CMOS image sensor having the constitution ofFIG. 52, the photodiode PD-sensor circuit region32and the ADC-memory region33are included in a single semiconductor chip, so that when the number of pixels is increased to achieve high resolution, the opening area of a unit pixel, that is, a minute pixel, becomes small, and high sensitivity cannot not be obtained. Then, chip use efficiency is inferior and the area of a chip is increased, so that cost increase cannot be avoided.

DISCLOSURE OF THE INVENTION

The present invention is to provide a CMOS type semiconductor image sensor module in which the aperture ratio of a pixel is improved and at the same time, improvement of chip use efficiency is attempted and furthermore, simultaneous shuttering of all the pixels is made possible, and a method of manufacturing the same.

A semiconductor image sensor module according to the present invention is characterized by being formed by laminating a first semiconductor chip including an image sensor in which a plurality of pixels are arranged regularly and each of the pixels is constituted by a photoelectric conversion element and transistors and a second semiconductor chip including an analog/digital converter array composed of a plurality of analog/digital converters.

A preferable mode of the present invention has a constitution in the aforesaid semiconductor image sensor module that a third semiconductor chip including a memory element array provided with at least a decoder and a sense amplifier is further laminated.

A preferable mode of the present invention has a constitution that the first and second semiconductor chips are arranged close to the third semiconductor chip such that a plurality of photoelectric conversion elements and a plurality of memory elements share one analog/digital converter.

It is possible to constitute the memory element by a volatile memory, a floating gate type nonvolatile memory, an MONOS type nonvolatile memory, a multivalued nonvolatile memory or the like.

It is possible to configure the memory element array to have a memory bit for parity check. It is possible to configure the memory element array to have a constitution that a spare bit for relieving a defect is included.

A semiconductor image sensor module according to the present invention is characterized by being formed by laminating a first semiconductor chip including an image sensor in which a plurality of pixels are arranged regularly and each of the pixels is constituted by a photoelectric conversion element and transistors, and a fourth semiconductor chip including an analog type nonvolatile memory array composed of a plurality of analog type nonvolatile memories, and in that an amount of information corresponding to an amount of accumulated electric charge is stored by the analog type nonvolatile memory.

A manufacturing method of a semiconductor image sensor module according to the present invention is characterized by including the steps of: forming a first semiconductor chip provided with an image sensor in which a plurality of pixels, each of which is constituted by a photoelectric conversion element and transistors, are regularly arranged two-dimensionally; forming a second semiconductor chip provided with an analog/digital converter array which is composed of a plurality of analog/digital converters; and laminating the first semiconductor chip and the second semiconductor chip and connecting the pixels of aforesaid image sensor and the analog/digital converters. In this connection process, the pixels of the image sensor of the first semiconductor chip and the analog/digital converters of the second semiconductor chip are bonded by means of bumps with the analogue/digital converters faced downward or connected by means of through-holes which pass through a wafer vertically with respect to an LSI chip surface.

A preferable mode of a manufacturing method of a semiconductor image sensor module according to the present invention includes in the aforementioned manufacturing method of a semiconductor image sensor module, a process for forming a third semiconductor chip provided with a memory element array which includes at least a decoder and a sense amplifier; and a process for laminating the first semiconductor chip, the second semiconductor chip, and the third semiconductor chip and connecting the pixels of the image sensor with the memory through the analog/digital converters. In this connection process, the pixels of the image sensor of the first semiconductor chip are connected with the memory of the third semiconductor chip through the analog/digital converters of the second semiconductor chip by means of through-holes passing through the wafer vertically with respect to the wafer face.

A manufacturing method of a semiconductor image sensor module according to the present invention is characterized by including: a process for forming a first semiconductor chip provided with an image sensor in which a plurality of pixels, each of which is constituted by a photoelectric conversion element and transistors, are regularly arranged two-dimensionally; a process for forming a fourth semiconductor chip provided with an analog nonvolatile memory array composed of a plurality of analog type nonvolatile memories; and a process for laminating the first semiconductor chip and the fourth semiconductor chip and connecting the pixels of the image sensor and the analog type nonvolatile memories.

According to a semiconductor image sensor module of the present invention, a first semiconductor chip provided with an image sensor in which a pixel is constituted by a photoelectric conversion element and transistors and a second semiconductor chip provided with an analog/digital converter array which is composed of a plurality of analog/digital converters are laminated to constitute the semiconductor image sensor module, so that in the first semiconductor chip, a large portion thereof can be formed as a pixel region and therefore, the aperture ratio of the photoelectric conversion element is improved and also, it is possible to improve chip utilization. Also, by providing a semiconductor chip which includes a memory element array composed of a plurality of memory elements, the pixel signals from the first semiconductor chip can be signal-processed after carrying out analog/digital conversion in the second semiconductor chip in a short period and once storing the signals in the memory element array, so that it is possible to realize simultaneous shuttering of the pixels.

By configuring a first semiconductor chip provided with an image sensor in which the pixel is constituted by a photoelectric conversion element and transistors, a second semiconductor chip provided with an analog/digital converter array which is composed of a plurality of analog/digital converters, and further a third semiconductor chip provided with a memory element array which includes at least a decoder and a sense amplifier, in a laminated structure, one unified device is obtained, and it is possible to realize improvement of the aperture ratio of the photoelectric conversion element, improvement of chip utilization, and further simultaneous shuttering of all the pixels.

By employing a constitution that the first and third semiconductor chips are arranged close to the second semiconductor chip such that a plurality of photoelectric conversion elements and a plurality of memory elements share one analog/digital converter, the signals from the plurality of photoelectric conversion elements can be analog-to-digital converted serially in the analog/digital converter and can be held in the memory elements in a short period, and it is possible to execute simultaneous shuttering of all the pixels.

According to a semiconductor image sensor module of the present invention, by employing a constitution that a first semiconductor chip provided with an image sensor in which a pixel is constituted by a photoelectric conversion element and transistors and a fourth semiconductor chip provided with an analog type nonvolatile memory array are laminated, in the first semiconductor chip, a large portion thereof can be formed as a pixel region, so that the aperture ratio of the photoelectric conversion element is improved and also, it is possible to improve chip utilization. In addition, because the pixel signals from the first semiconductor chip are signal-processed after having been held once in the analog type nonvolatile memory cell, it is possible to realize simultaneous shuttering of the pixels.

According to a manufacturing method of a semiconductor image sensor module of the present invention, it is possible to manufacture a semiconductor image sensor module provided with a CMOS image sensor in which it is possible to realize improvement of the aperture ratio of the photoelectric conversion element, improvement of chip utilization, and further simultaneous shuttering of all the pixels.

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, exemplified embodiments of the present invention will be explained with reference to the drawings

FIG. 1shows a general constitution of a first exemplified embodiment of a semiconductor image sensor module according to the present invention. A semiconductor image sensor module51according to the exemplified embodiment of the present invention is constituted by laminating a first semiconductor chip52provided with an image sensor in which a plurality of pixels are arranged regularly and each of the pixels is constituted by a photodiode as a photoelectric conversion element and a transistor, a second semiconductor chip53provided with an analog/digital converter array composed of a plurality of analog/digital converters (a so-called analog/digital conversion circuit), and a third semiconductor chip54provided with a memory element array including at least a decoder and a sense amplifier.

The image sensor of the first semiconductor chip52in this example is constituted by a so-called back-illuminated type CMOS image sensor in which a transistor forming region56, in which transistors constituting a unit pixel are formed, is formed on the chip front face side, and a photodiode forming region57having an incidence plane where light L enters and in which a plurality of photodiodes which become a plurality of photoelectric conversion elements are regularly arranged two dimensionally, for example, in a two dimensional matrix form, is formed on the chip rear face side.

There is shown inFIG. 2an example of a unit pixel of a back-illuminated type CMOS image sensor. In the back-illuminated type CMOS image sensor60of this example, pixel separation regions62are formed in an imaging region59of a thinned semiconductor substrate, for example, an n-type silicon substrate61, and a plurality of MOS transistors Tr, each of which is composed of an n-type source-drain region64, a gate insulation film65, and a gate electrode66, are formed in a p-type semiconductor well region63of each pixel region partitioned by the pixel separation regions62. These MOS transistors Tr are so-called sensor transistors by means of an amplifier transistor, a transistor for XY selection switching and the like, and are formed on the substrate front face side. The plurality of transistors Tr may be constituted by, for example, 3 transistors, i.e., a readout transistor having a source-drain region, which becomes a floating diffusion region FD, a reset transistor, and an amplifier transistor, or 4 transistors, i.e., the aforementioned 3 transistors and a vertical selection transistor. On the substrate front face side, there is formed a multilayer wiring layer78in which multilayer wirings77are formed through interlayer insulation films76. Further, a support substrate79for reinforcement, for example, by means of a silicon substrate or the like, is joined on the multilayer wiring layer78.

The photodiode PD is formed by an n+ charge accumulation region68a, an n-type semiconductor region68b, and p+ semiconductor regions69which become accumulation layers formed on both the front and rear faces of the substrate for suppressing dark current. Then, a color filter72is formed on the substrate rear face side through a passivation film71, and further, an on chip microlens73corresponding to each pixel is formed on the color filter72. This imaging region59becomes a so-called photodiode PD-sensor circuit region.

On the other hand, with respect to the second semiconductor chip53, a plurality of analog/digital converter arrays each of which is composed of a plurality of analog/digital converters are arranged two dimensionally.

In the third semiconductor chip54, there is formed thereon a memory array in which memory element sub-arrays composed of a plurality of memory elements are arranged two dimensionally. The memory element sub-array is constituted including a decoder and a sense amplifier. Each memory element sub-array is formed as a memory array block composed of a plurality of memory elements and including a decoder and sense amplifier, so as to correspond to each pixel array block in which, as described later, a plurality of pixels are assembled as a group.

For the memory element, it is possible to use, for example, a volatile memory, which is represented by a DRAM or a SRAM, a floating gate type nonvolatile memory, an MONOS type nonvolatile memory or the like.

There is shown inFIG. 18andFIG. 19a general constitution of a floating gate type nonvolatile memory. As shown inFIG. 18, a floating type nonvolatile memory101is constituted such that a source region103and a drain region104are formed in a semiconductor substrate102and a floating gate105and a control gate106are formed through a gate insulation film. There are shown inFIG. 19cell array connection wiring diagrams, writing operations, and erasing operations of representative NAND type, NOR type and AND type flash memories. Since contact of a bit line and a single cell can be omitted in the NAND type one, ideally the minimum cell size of 4F2(F is ½ of a minimum pitch determined by designing rule) can be realized. Writing is based on the channel FN tunneling (Fowler-Nordheim Tunneling) method and erasing is based on the substrate FN tunneling emission method. High-speed random access is possible in the NOR type in which writing is based on the CHE (Channel Hot Electron) method and erasing is based on the FN tunneling emission method to the source terminal. Writing of the AND type is based on the FN tunneling of the drain terminal and reading out thereof is based on the channel FN tunneling method. Writing speed of the NAND type flash memory is 25-50 μS which is slow, but, by increasing the parallel degree in processing as shown inFIG. 4andFIG. 5, high-speed data transfer of GBPS (gigabyte/sec) becomes possible.

There is shown inFIG. 20andFIG. 21a general constitution of an MONOS type nonvolatile memory. As shown inFIG. 20, an MONOS type nonvolatile memory111is constituted such that a source region113and a drain region114is formed in a semiconductor substrate112, and a tunnel oxide film115, an Si3N4 charge trap layer116, a top oxide film117and a gate polyelectrode118are formed sequentially. There are shown inFIG. 21a cell array connection wiring diagram, a writing operation and erasing operations of the MONOS type memory. Programming is carried out by injecting a hot electron to the Si3N4 charge trap layer116based on the CHE method and by changing the threshold. Erasing is carried out by injecting a hot hole or by pulling-out based on the FN tunneling method.

The first semiconductor chip52provided with the CMOS image sensor60and the second semiconductor chip53provided with the analog/digital converter array are laminated such that the front face side opposite to the light incident side of the first semiconductor chip52faces the second semiconductor chip53, and respective pads81and82for connection are electrically connected through electroconductive connection bodies, for example, through bumps83. Also, the second semiconductor chip53provided with the analog/digital converter array and the third semiconductor chip54laminated thereon and provided with the memory element array are joined such that the analog/digital converter and the memory elements are electrically connected through penetration contact portions84passing through the second semiconductor chip53.

Usually, the analog/digital converter requires 50 to 100 times of layout area to the area of 1 pixel. Consequently, it is constituted in this exemplified embodiment such that a single analog/digital converter collectively processes the number of pixels of around the layout area of one analog/digital converter. Further, it is constituted such that data of a plurality of pixels are saved in the memory elements of the third semiconductor chip54laminated thereon. Usually, there is a data volume of 10 to 14 bits per 1 pixel, so that there is arranged a memory element array having the number of bits corresponding to the product obtained by multiplying the number of pixels corresponding to those directly on one analog/digital converter and the number of memory elements each of which can store the amount of information per 1 pixel.

FIG. 3shows in a form of a schematic perspective view, a relation among one pixel array block composed of the above-mentioned plurality of pixels, one analog/digital converter, and one memory element sub-array (that is, memory array block) composed of a plurality of memory elements which store data corresponding to the number of pixels in the pixel array block. The first semiconductor chip52as the image sensor, the second semiconductor chip53as the analog/digital converter array, and the third semiconductor chip54as the memory element array are laminated, and they are mutually connected such that one analog/digital converter87corresponds to one pixel array block86composed of a plurality of pixels and one memory element sub-array (memory array block)88composed of a plurality of memory elements which can store information of the pixel array block86corresponds to this one analog/digital converter87.

FIG. 4shows an example of data transfer of one pixel array block86. In this example, the pixel array block86composed of 64 (=8×8) pieces of pixels86acorresponds to one analog/digital converter (ADC)87. Picture data are transferred from the pixel array block86to the analog/digital converter87serially. Data is written from the analog/digital converter87to the memory array block88serially with a bus width corresponding to the resolution. In this example, 1 pixel data are converted to 12 bits and are written in the memory array block88. The memory array block88is provided with a sense amplifier93and a decoder94[X decoder94X, Y decoder94Y] which selects the pixels86a. Since the analog/digital converter87is arranged on the sensor, it is desirable for the chip area efficiency that the number of pixels to be processed by one analog/digital converter87is selected such that the area of the analog/digital converter87and the area of the pixel array block86become comparable and that the memory array block88also has a comparable size since it is arranged on the analog/digital converter87. Also, the memory array block88is arranged on the analog/digital converter87. It is not always necessary that the pixel array block86, the analog/digital converter87, and the memory array block88are in such a positional relation that one is located immediately above another, and it is enough if respective taking out portions of the signal wirings overlap each other.

FIG. 5is a whole block diagram. There are provided with a pixel array121in which a plurality of pieces of 64 pixels array blocks86are arranged, an analog/digital converter array122in which a plurality of pieces of analog/digital converter arrays each composed of a plurality of analog/digital converters87are arranged two-dimensionally such that one analog/digital converter87corresponds to each pixel array block86, a memory array123in which a plurality of memory array blocks88are arranged two-dimensionally, and a digital signal processing device124. Each of the pixel array121, the analog/digital converter array122, the memory array123, and the digital signal processing device124is controlled by a control circuit125. In this block diagram, data of each pixel in the 64 (=8×8) pixel array block86in the pixel array121are transferred to one analog/digital converter87serially, and also, pixel data of each pixel array block86are transferred to the corresponding analog/digital converter87in the analog/digital converter array122in parallel. The data transferred to the analog/digital converter array122are written in the memory array123after converting one pixel data to 12 bits in this example, by means of parallel processing of the number of analog/digital converters×12 bits. The data of this memory array123is processed by the digital signal processing device124. In this manner, data of the whole pixels or the pixels in one block are transferred in parallel, so that a very high transfer speed can be realized as a system.

In this exemplified embodiment, the memory element array (memory array block)88described above has the number of bits of around 500 to 1 k bits, and is provided with a readout circuit (sense amplifier), a writing circuit, and a decoder. For example, if the pixel size is 2 μm2and the analog/digital conversion apparatus87is 100 μm2, it is enough if the number of pixels processed by one analog/digital converter87is 50 pieces, and the size of the memory element array provided on the analogue/digital converter87is one including a decoder of 50×(10 to 14) bits. Supposing that the amount of information is maximum 14 bits and the cell occupancy in the memory array block is 60%, the memory cell area becomes 0.01 μm2, and it can be realized by a cell size of a 90 nm generation DRAM.

The rear face side of the first semiconductor chip52is formed mainly as a photodiode PD array for a large portion thereof, so that an adequate aperture characteristic, that is, an aperture ratio can be obtained as a photodiode PD. Also, since an adequate aperture ratio can be obtained, conversely a minute pixel can be manufactured.

The analog-to-digital converted signal is once held in the memory element cell. With respect to the writing period to the memory element, it can be transferred by μS order if sequential accessing is performed using, for example, a DRAM, so that the transfer time is adequately short as compared with an accumulation period of the photodiode PD, and as a result, simultaneous shuttering of all the pixels can be realized.

As shown inFIG. 3, there may be included parity check bits89and defect relieving redundant bits90in the memory element sub-array88.

According to the semiconductor image sensor module51of the first exemplified embodiment, by laminating and integrating the first semiconductor chip52provided with the back-illuminated type CMOS image sensor60; the second semiconductor chip53provided with the analog/digital converter array composed of the plurality of analog/digital converters87; and the third semiconductor chip54provided with the memory array (memory element array) in which the memory element arrays are included, that is, a plurality of memory element sub-arrays (memory array blocks)88are arranged two dimensionally, it is possible to make the photodiode PD area on the rear face side, that is, the pixel aperture ratio adequately large. Thereby, pixel miniaturization corresponding to shrinkage of the optical system becomes possible, and also, low noise equivalent to a CCD image sensor can be realized. In particular, because production of a minute pixel having a large aperture ratio also becomes possible, a high resolution semiconductor image sensor module can be obtained. Also, because it is constituted such that the pixel array86composed of a plurality of pixels and the memory element array88composed of a plurality of memory elements share one analog/digital converter87and the signal from the pixel array86, which has been analog-to-digital converted in a short period, is held in the memory element array88and thereafter signal-processed, it is possible to carry out simultaneous shuttering of all the pixels. Consequently, it is possible to provide a CMOS image sensor-module that has a high sensitivity and that is capable of simultaneous electronic shuttering. The CMOS image sensor-module of this exemplified embodiment is preferably applied, for example, to a digital still camera of a high-grade single lens reflex, a mobile phone or the like.

In the first exemplified embodiment, the first, second and third semiconductor chips52,53and54have been laminated, however, it is also possible, for example, to laminate the first semiconductor chip52of the CMOS image sensor and the second semiconductor chip53of the analog/digital converter array except the third semiconductor chip54including the memory element array, arrange the third semiconductor chip in a necessary substrate or package together with the laminated body of the first and second semiconductor chips52and53, and connect the second semiconductor chip53and the third semiconductor chip54through an external wiring.

There is shown inFIG. 6a general constitution of a second exemplified embodiment of a semiconductor image sensor module according to the present invention. A semiconductor image sensor module99according to this exemplified embodiment is constituted similarly as mentioned above by laminating the first semiconductor chip52provided with the CMOS image sensor60in which a plurality of pixels are arranged regularly and each of the pixels is constituted by the photodiode forming region57and the transistor forming region56, the second semiconductor chip53provided with an analog/digital converter array composed of a plurality of analog/digital converters, and the third semiconductor chip54provided with a memory element array including at least a decoder and a sense amplifier.

Then, in this exemplified embodiment, a multivalued nonvolatile memory (hereinafter, referred to as a multivalued memory) is formed as the memory element of the third semiconductor chip54. For this multivalued memory, it is possible to use, for example, a nonvolatile resistance random-access-memory (RRAM) by means of a thin film having huge magnetic resistance, which was published in 193-196 pages of IEDM Technical Digest (2002).

There is shown inFIG. 8a characteristic evaluation circuit of a simple element. There are shown inFIG. 9a pulse application diagram and inFIG. 10a voltage-current diagram.

In this RRAM, that is, a resistance-changing type multivalued memory element, as shown inFIG. 7, element separation regions173are formed in a silicon substrate172, and a first, a second and a third source/drain regions174,175and176are formed in the substrate172partitioned by the element separation regions173. A first MOS transistor Tr1is formed by the first and second source/drain regions174and175and a gate electrode (so-called word line)177which is formed through an insulation film. Also, a second MOS transistor Tr2is formed by the second and third source/drain regions175and176and a gate electrode (so-called word line)178which is formed through an insulation film. The second source/drain region175is connected with a sense line181through a conductive plug179, which passes through an interlayer insulation film. On the other hand, the first and third source/drain regions174and176are connected with resistance-changing type multivalued memory elements182and183through the conductive plugs179respectively. The other terminals of the resistance-changing type multivalued memory elements182and183are connected with a bit line180. For the memory elements182and183, it is possible to use, for example, a material of SrZrO3: Cr system. There exists in addition for the memory material, PCMO (Pr0.7Ca0.3MnO3), a material in which Cu or Ag has been added to chalcogenide, or the like. Pt electrodes185and186are formed above and below this memory material184and thereby the memory elements182and183are formed. 1 bit is constituted by one memory element and one MOS transistor. InFIG. 7, there are constituted memory elements for 2 bits, which share the sense line. There is shown inFIG. 8a circuit of a single memory element.

First, it will be reviewed about a case of a binary resistance-changing type memory.

A pulse voltage is applied to the memory element as shown inFIG. 9. The switching voltage threshold changes according to the material and the film thickness. InFIG. 9, the threshold voltage is made to be +−0.7 V. Although it is actually not a target in many cases, it will be explained here assuming that absolute values of the threshold voltages of “0” writing and “1” writing are equal. When the pulse voltage is increased to the threshold or more, the resistance value changes (4→5, 10→11: (seeFIG. 10)). In an actual readout operation, a voltage lower than the threshold is applied and “0” or “1” is judged from the flowing current. In many cases, a middle resistance having a resistance value between “0” resistance value and “1” resistance value is created, and “0” or “1” is judged by comparing this resistance and the memory resistance. There is shown inFIG. 11a connection wiring diagram of a memory array.FIG. 12shows an explanatory diagram of the “0” writing operation. When writing “0” (high resistance) in a “1” (low resistance) bit, the word line of a selection cell is made ON and “0” writing is carried out by adding a pulse voltage to the bit line such that a voltage of the threshold voltage or more is added to the memory element.

“1” writing (Reset) will be explained usingFIG. 13. The word line of the “1” writing operation selecting cell is made ON and “1” writing is carried out by adding a pulse voltage between the sense line and the bit line such that a voltage of the threshold voltage or more is added to the memory element.FIG. 14is a diagram for explaining a readout operation. A voltage adequately lower than the threshold voltage is applied to the memory element between the sense line and the bit line, this current is converted to a voltage, and “1” or “0” is judged by comparing it with the current flowing in the middle resistance (reference).

FIG. 15illustrates a current-voltage characteristic example of a multivalued memory having four thresholds. In the case of a multivalued memory, in the example of the current-voltage characteristic inFIG. 15in which the thresholds become plural, the readout for V0, V1′, V2′ and V3′ are carried out by a voltage (Vread in the drawing) lower than V1. In the case of a writing operation to a higher level than the previous level, writing of level2is carried out by a voltage between V1and V2, writing of level3is carried out by a voltage between V2and V3, and writing of level4is carried out by a voltage of V3or more. Also, in the case of writing-in to a level lower than the previous state, writing of level3is carried out by a voltage between V3′ and V2′, writing of level2is carried out by a voltage between V2′ and V1′, and writing of level1is carried out by a voltage between V1′ and V0. Readout is carried out by performing comparison of sizes with the middle resistance at respective levels that have been generated. The multivalue control can be performed with the bias voltage control from the outside of the memory array, so that the cell array circuit itself is the same as in the binary value (seeFIG. 11). The multivalued memory can be realized even by changing the writing pulse.

FIG. 16is a diagram showing an observation result of the aforesaid IEDM (International Electron Device Meeting) Technical Digest. It will be explained with respect to this ideal case referring toFIG. 17. As shown in the drawing, the element resistance changes step-wise depending on the number of program pulses. The reset is carried out with applying a pulse of the opposite direction. For the readout, the resistance value is detected by applying a voltage that is adequately low as compared with the program voltage. Also in this case, the cell array circuit is the same as that inFIG. 11.

In this manner, a RAM can record if the number of writing pulses of the memory is adjusted in response to the amount of the accumulated electric charge of the photodiode PD. Also, readout can be carried out with applying a current to the memory and detecting the difference of resistance values (voltages). Supposing that the data volume per one pixel is x and an n value memory is used, the number of memory bits y constituting the memory cell per one pixel becomes n-th root of x, and it is possible to decrease the number of memory bits in the memory array block.

InFIG. 6, other constitutions are similar to those of the first exemplified embodiment described above, so that the same reference numerals are put on the corresponding portions and the repetitive explanation thereof will be omitted.

According to the CMOS image sensor-module99in the second exemplified embodiment, by using a nonvolatile multivalued memory for the memory element constituting the memory element array of the third semiconductor chip, the number of memory elements which records information corresponding to one pixel is decreased drastically. Then, similarly as the first exemplified embodiment, the rear face side is formed mainly as a photodiode PD array for a large portion thereof, so that an adequate aperture ratio of a photodiode PD can be obtained, and also it is possible to produce a minute pixel. The analog-to-digital converted signal is once held in the memory element cell once. With respect to the writing period to the memory element, data can be transferred by μS order if sequential access is performed, which is adequately short to an accumulation period of the photodiode PD, and simultaneous shuttering of all the pixels can be realized. Consequently, it is possible to provide a CMOS image sensor-module that has a high sensitivity and is capable of simultaneous electronic shuttering.

There is shown inFIG. 22a general constitution of a third exemplified embodiment of a semiconductor image sensor module according to the present invention. A semiconductor image sensor module100according to this exemplified embodiment is constituted by laminating the first semiconductor chip52provided with the CMOS image sensor60similar to the previously described one in which a plurality of pixels are arranged regularly and each of the pixels is constituted by the photodiode forming region57and the transistor forming region56, and the fourth semiconductor chip55in which a memory element array is formed.

Then, in this exemplified embodiment, the memory element constituting the memory element array of the fourth semiconductor chip55is formed by means of an analog type nonvolatile memory represented, for example, by a switched capacitor. In this analog type nonvolatile memory, for example, in a switched capacitor, a potential corresponding to a charge amount accumulated by the pixel photoresist PD is generated by an amplifier, and according to this potential, the amount of accumulated electric charge of the capacitor is controlled. The charge accumulated in the capacitor is proportional to the signal charge amplified by the amplifier. In this case, it is enough if memory elements corresponding to the number of pixels are provided.

There is shown inFIG. 23a memory cell circuit diagram using a switched capacitor. This memory cell circuit130is constituted by including a memory capacitor131, a switch for writing132, a writing dummy switch133, a D-type flip-flop134for writing, a switch for readout135and a D-type flip-flop for readout136. Each of the switches132,133and135is constituted of an NMOS transistor Trn and a PMOS transistor Trp. In other words, each of the switches is constituted of CMOS transistors. In this switched capacitor type analog memory, with respect to writing, the switch for writing132is made ON when a Q output of the D-type flip flop for writing134becomes a high level (High) and the memory capacitor131is charged so as to be of a voltage between Vin and Vc. With respect to readout, the switch for readout135(so-called CMOS pass transistor) is made ON when an output Q of the D-type flip-flop for readout136becomes a high level (High) and an output is derived therefrom. It is allowed to insert an amplifier in the succeeding stage thereof. Data of the switched capacitor type analog memory are transferred to an analog/digital converter (ADC).

FIG. 24shows one example of a cross section structure of a switched capacitor. The drawing shows the portion of a memory capacitor and a switch for readout. An NMOS transistor Trn is formed by forming element separation regions142in a p-type semiconductor substrate141, and a n-type source region143, a drain region144, and a gate electrode145by means of 1 layer polysilicon through a gate insulation film in the substrate141partitioned by the element separation regions142. A p-type region146is a potential supply region provided for fixing the substrate potential. A PMOS transistor Trp is formed by forming a n-type semiconductor well region147in the p-type semiconductor substrate141, and a p-type source region148, a drain region149, and a gate electrode150by means of 1 layer polysilicon through a gate insulation film in this n-type semiconductor well region147. An n-type region151is a potential supply region provided for fixing the well region potential. CMOS transistors constituting the switch for readout135are formed by these NMOS transistor Trn and PMOS transistor Trp. On the other hand, there is formed on the element separation region142, the memory capacitor131which is constituted by laminating a first electrode153by means of 1 layer polysilicon, a dielectric film (interlayer insulation film)154, and a second electrode155by means of 2 layer polysilicon. A wiring158connected with each region through each conductive plug157, which passes through an interlayer insulation film156, is formed. Only 1 layer metal is shown for the wiring158, but it does not matter even if there is provided a wiring pattern of a plurality of layers. For the memory capacitor131, it is possible to use a capacitor using a 2 layer metal or a MOS capacitor other than the above-described one.

There is shown inFIG. 25a block diagram using an analog memory array by means of switched capacitor type analog memories. A plurality of switched capacitor type analog memories130are arranged in a line-column form to form an analog memory array161. It is constituted such that the analog memories130in each column are connected with a writing control signal input line162and a readout control signal input line163. Corresponding to the analog memories130in respective lines of the analog memory cell161, pixel array blocks164are connected on the input side of the analog memory array161and analog/digital converters165are connected on the output side thereof, respectively. The analog signal inputted from each pixel cell of the pixel array blocks164to the analog memory array161is accumulated sequentially in each of the analog memories (memory cells)130serially. With respect to readout, signals are inputted sequentially to the analog/digital converter165corresponding to the pixel array block164starting from the head memory cell according to readout control signals, and digital signals are outputted.

Other constitutions are similar to those of the first exemplified embodiment described above, so that repetitive explanation thereof will be omitted by putting the same reference numerals on the corresponding portions.

Writing to this analog type nonvolatile memory is carried out by relating each plurality of pixels to the memory element sub-array in which information of the plurality of pixels is stored and by serially accessing the information of the plurality of pixels for writing in the corresponding memory array. With respect to the writing period, transferring can be attained in μS order or less if this analog memory is used and sequential access is employed.

According to the semiconductor image sensor module100in the third exemplified embodiment, by laminating and integrating the first semiconductor chip52provided with the back-illuminated type CMOS image sensor and the fourth semiconductor chip55provided with the analog type nonvolatile memory array, similarly as in the first exemplified embodiment described above, the rear face side of the first semiconductor chip52is formed mainly as a photodiode PD array for a large portion thereof, so that an adequate aperture ratio of a photodiode PD can be obtained, and also it is possible to produce a minute pixel. Further, with respect to the writing period to the analogue type nonvolatile memory, because data can be transferred in μS order or less, which is adequately short relative to an accumulation period of the photodiode PD, simultaneous shuttering of all the pixels can be realized.

Next, an exemplified embodiment of a manufacturing method of a semiconductor image sensor module according to the present invention will be explained usingFIG. 26. This example is a case that the method is applied to the manufacture of the semiconductor image sensor module51according to the first exemplified embodiment inFIG. 1.

First, as shown inFIG. 26A, a transistor forming region is formed on a first front face side of a semiconductor substrate, and the first semiconductor chip52is formed in which a forming region for a photodiode which becomes a photoelectric conversion element is formed on a second front face which is the rear face of the substrate. Specifically, as shown inFIG. 2, a pixel transistor is formed on the front face side of a thinned semiconductor substrate, and a photodiode is formed so as to make the rear face side a light incidence plane. A multilayer wiring layer is formed on the front face side of the semiconductor substrate, and a support substrate for reinforcement, for example, a silicon substrate, is joined thereon. A color filter is formed on the rear face side of the semiconductor substrate through a passivation film, and further, an on chip microlens is formed. Thinning of the semiconductor substrate is carried out using grinding and CMP (Chemical Mechanical Polishing) or the like after joining the support substrate. Then, the pads81connected with the multilayer wiring are formed on the support substrate, for example through penetration contacts.

Next, as shown inFIG. 26B, at least an analog/digital converter array is formed in the semiconductor substrate, the pads82for connection of respective analog/digital converters are formed on the front face of the semiconductor substrate, and further, the second semiconductor chip53, in which the penetration contact portions84which pass through the semiconductor substrate so as to be exposed to the rear face side of the semiconductor substrate have been formed, is formed. This semiconductor substrate is also thinned.

The conductive micro bumps83are provided on the pads82of this second semiconductor chip53and the pads82of the second semiconductor chip53and the pads81on the front face side of the first semiconductor chip52are connected electrically through this micro bumps83with the second semiconductor chip53faced downward.

Next, as shown inFIG. 26C, the third semiconductor chip54, in which a memory array has been formed with arranging memory element arrays two dimensionally, is formed. This third semiconductor chip54is laminated on the second semiconductor chip53, and the second analog/digital converter array and the memory element array of the third semiconductor chip54are connected electrically through the penetration contact portions84. Thereby, the semiconductor image sensor module51provided with the aimed CMOS image sensor is obtained.

According to the manufacturing method of the semiconductor image sensor module in this exemplified embodiment, mainly a back-illuminated type CMOS image sensor is formed on the first semiconductor chip52, so that the aperture ratio of the photodiode becomes large and it is possible to attempt a high sensitivity even in the case of a minute pixel. Then, the first, the second and the third semiconductor chips52,53and54are laminated and mutual electric connections thereof are carried out by means of the micro bumps83and the penetration contact portions84, so that it is possible to make wirings of the mutual connections the shortest and to accumulate data of the photodiode in the memory element array at a high speed, and simultaneous shuttering of all the pixels becomes possible. Accordingly, it is possible to manufacture a semiconductor image sensor module provided with a CMOS image sensor, that has a high sensitivity and that is capable of simultaneous electronic shuttering.

In the exemplified embodiment ofFIG. 26, the second semiconductor chip53in which the analog/digital converter array has been formed is laminated so as to be connected on the front face side of the first semiconductor chip52in which the CMOS image sensor has been formed, with the second semiconductor chip53faced downward, but instead of this configuration, it is allowed to employ a configuration that connection between the first semiconductor chip52and the second semiconductor chip53is performed by a penetration contact portion which passes through the second semiconductor chip53.

It is possible to manufacture also the semiconductor image sensor module99according to the second exemplified embodiment shown inFIG. 6fundamentally by a manufacturing method similar to the one shown inFIG. 25.

In addition, it is possible to manufacture the semiconductor image sensor module100according to the third exemplified embodiment inFIG. 22by providing micro bumps to the pads of the fourth semiconductor chip55in which the analog type nonvolatile memory array has been formed according to the process ofFIG. 25Band by connecting the fourth semiconductor image sensor module55with the first semiconductor chip52with the fourth semiconductor image sensor module55faced downward.

There are shown inFIGS. 27A and 27Bgeneral constitutions of a fourth exemplified embodiment of a semiconductor image sensor module according to the present invention. Semiconductor image sensor modules166and167according to this exemplified embodiment are constituted similarly as described above by laminating the first semiconductor chip52provided with the CMOS image sensor60in which a plurality of pixels are arranged regularly and each pixel is constituted by the photodiode forming region57and the transistor forming region56, the second semiconductor chip53provided with an analog/digital converter array composed of a plurality of analog/digital converters, and the third semiconductor chip54provided with a memory element array including at least a decoder and a sense amplifier. The first semiconductor chip52and the second semiconductor chip53are electrically connected between the pads81and82for connection, which have been formed respectively, through, for example, the bumps (micro bumps)83. Also, the second semiconductor chip53and the third semiconductor chip54are joined each other such that the analog/digital converters and the memory elements are connected electrically through penetration contact portions84passing through the second semiconductor chip53. Then, in this exemplified embodiment, the analog/digital converters87are formed on the undersurface side of the second semiconductor chip53.

The semiconductor image sensor module166inFIG. 27Ais an example in which the penetration contact portion84is not connected with the pad82directly and is formed deviated from the position immediately above the pad82. In other words, this semiconductor image sensor module166is suitably applied to a case in which it is not desired to directly connect the penetration contact portion84with the pad82.

The semiconductor image sensor module167ofFIG. 27Bis an example in which the penetration contact portion84is formed just above the pad82.FIG. 27Bis a schematic diagram, and it appears as if the analog/digital converter87intervenes between the penetration contact portion84and the pad82, but actually, it is formed such that the penetration contact portion84is connected with the pad82directly and the analog/digital converter is formed around the penetration contact portion84. In other words, this semiconductor image sensor module167is suitably applied to a case in which it is desired to directly connect the penetration contact portion84with the pad82.

According to the semiconductor image sensor modules166and167in the fourth exemplified embodiment inFIGS. 27A and 27B, it is possible to transmit signals to the analog/digital converter87without picking up a noise in the penetration contact portion84.

There are shown inFIGS. 28A and 28Bgeneral constitutions of a fifth exemplified embodiment of a semiconductor image sensor module according to the present invention. Semiconductor image sensor modules168and169according to this exemplified embodiment is constituted similarly as mentioned above by laminating the first semiconductor chip52provided with the CMOS image sensor60in which a plurality of pixels are arranged regularly, the second semiconductor chip53provided with an analog/digital converter array composed of a plurality of analog/digital converters, and the third semiconductor chip54provided with a memory element array including at least a decoder and a sense amplifier. The first semiconductor chip52and the second semiconductor chip53are electrically connected between the pads81and82for connection which have been formed respectively, through, for example, the bumps (micro bumps)83. Also, the second semiconductor chip53and the third semiconductor chip54are joined each other such that the analog/digital converter and the memory elements are connected electrically through penetration contact portions84passing through the second semiconductor chip53. Then, in this exemplified embodiment, the analog/digital converters87are formed on the upper surface side of the second semiconductor chip53. The signal of each pixel from the first semiconductor chip52passes through the penetration contact portion84and is analog/digital converted by the analog/digital converter87.

The semiconductor image sensor module168inFIG. 28Ais an example in which the penetration contact portion84is not connected with the pad82directly and is formed deviated from the position immediately above the pad82. In this case, a wiring layer170connected with the pad82is formed on the undersurface side of the second semiconductor chip53, and the pad82and the penetration contact portion84are connected electrically through this wiring layer170. In other words, this semiconductor image sensor module168is suitably applied to a case that it is not desired to connect the penetration contact portion84with the pad82directly.

The semiconductor image sensor module169ofFIG. 28Bis an example in which the penetration contact portion84is formed just above the pad82. Also,FIG. 28Bis a schematic diagram, and similarly as mentioned above, the penetration contact portion84is connected with the analog/digital converter87so as to be positioned at the center portion of the analog/digital converter87on the upper surface side. In other words, this semiconductor image sensor module169is suitably applied to a case that it is desired to connect the penetration contact portion84with the pad82directly.

The semiconductor image sensor modules168and169according to the fifth exemplified embodiment ofFIGS. 28A and 28Bare preferably applied to a case that distortion is large on the undersurface side of the second semiconductor chip53and it is difficult to form the analog/digital converter87on the undersurface side.

There are shown inFIGS. 29A and 29Bgeneral constitutions of a sixth exemplified embodiment of a semiconductor image sensor module according to the present invention. Semiconductor image sensor modules187and188according to this exemplified embodiment are constituted similarly as mentioned above by laminating the first semiconductor chip52provided with the CMOS image sensor60in which a plurality of pixels are arranged regularly and each pixel is constituted by the photodiode forming region57and the transistor forming region56, the second semiconductor chip53provided with an analog/digital converter array composed of a plurality of analog/digital converters, and the third semiconductor chip54provided with a memory element array including at least a decoder and a sense amplifier. The first semiconductor chip52and the second semiconductor chip53are electrically connected between the pads81and82for connection which have been formed respectively, through, for example, the bumps (micro bumps)83. Also, the second semiconductor chip53and the third semiconductor chip54are joined each other such that the analog/digital converter and the memory elements are connected electrically through penetration contact portions84passing through the second semiconductor chip53. Then, in this exemplified embodiment, the memory array blocks88are formed on the undersurface side of the third semiconductor chip54. The signal analog/digital converted by the analog/digital converter array of the second semiconductor chip53is stored in the memory array block88.

The semiconductor image sensor module187inFIG. 29Ais an example in which the penetration contact portion84in the second semiconductor chip53is not connected with the pad82directly and is formed deviated from the position immediately above the pad82. In this case, a wiring layer170connected with the pad82is formed on the undersurface side of the second semiconductor chip53, and the pad82and the penetration contact portion84are connected electrically through this wiring layer170. In other words, this semiconductor image sensor module187is suitably applied to a case in which it is not desired to connect the penetration contact portion84in the second semiconductor chip53and the pad82directly.

The semiconductor image sensor module188ofFIG. 29Bis an example in which the penetration contact portion84in the second semiconductor chip53is formed just above the pad82. In other words, this semiconductor image sensor module188is suitably applied to a case in which the penetration contact portion84in the second semiconductor chip53and the pad82are connected directly.

The semiconductor image sensor modules187and188according to the fifth exemplified embodiment ofFIGS. 29A and 29Bare preferably applied to a case in which distortion is large on the upper surface side of the third semiconductor chip54and it is difficult to form the memory array block88on the upper surface side.

There are shown inFIGS. 30A and 30Boutlines of a seventh exemplified embodiment of a semiconductor image sensor module according to the present invention. Semiconductor image sensor modules189and190according to this exemplified embodiment is constituted similarly as mentioned above by laminating the first semiconductor chip52provided with the CMOS image sensor60in which a plurality of pixels are arranged regularly and each pixel is constituted by the photodiode forming region57and the transistor forming region56, the second semiconductor chip53provided with an analog/digital converter array composed of a plurality of analog/digital converters, and the third semiconductor chip54provided with a memory element array including at least a decoder and a sense amplifier. The first semiconductor chip52and the second semiconductor chip53are electrically connected between the pads81and82for connection which have been formed respectively, through, for example, the bumps (micro bumps)83. Also, the second semiconductor chip53and the third semiconductor chip54are joined each other such that the analog/digital converter and the memory elements are connected electrically through penetration contact portions84passing through the second semiconductor chip53and penetration contact portions84′ passing through the third semiconductor chip53. Then, in this exemplified embodiment, the memory array blocks88are formed on the upper surface side of the third semiconductor chip54, and the penetration contact portions84and84′ are connected so as to face each other. The signal analog/digital converted by the analog/digital converter array of the second semiconductor chip53is stored in the memory array block88by way of the penetration contact portions84and84′.

The semiconductor image sensor module189inFIG. 30Ais an example in which the penetration contact portion84in the second semiconductor chip53, which is connected with the penetration contact portion84′ in the third semiconductor chip54, is not connected with the pad82directly and is formed deviated from the position immediately above the pad82. In this case, a wiring layer170connected with the pad82is formed on the undersurface side of the second semiconductor chip53, and the pad82and the penetration contact portion84are connected electrically through this wiring layer170. In other words, this semiconductor image sensor module187is suitably applied to a case in which it is not desired to connect the penetration contact portion84in the second semiconductor chip53and the pad82directly.

The semiconductor image sensor module190ofFIG. 30Bis an example in which the penetration contact portion84in the second semiconductor chip53, which is connected with the penetration contact portion84′ in the third semiconductor chip54, is formed just above the pad82. In other words, this semiconductor image sensor module190is suitably applied to a case in which the penetration contact portion84in the second semiconductor chip53and the pad82are connected directly.

The semiconductor image sensor modules189and190according toFIGS. 30A and 30Bare preferably applied to a case in which distortion is large on the undersurface side of the third semiconductor chip54and it is difficult to form the memory array block88on the undersurface side.

There are shown inFIGS. 31A and 31Boutlines of an eighth exemplified embodiment of a semiconductor image sensor module according to the present invention. Semiconductor image sensor modules189and190according to this exemplified embodiment are constituted by laminating the first semiconductor chip52and a second semiconductor chip193. The first semiconductor chip52is provided with the CMOS image sensor60in which a plurality of pixels are arranged regularly and each pixel is constituted by the photodiode forming region57and the transistor forming region56the CMOS image sensor60. The second semiconductor chip193is provided with an analog/digital converter array composed of a plurality of analog/digital converters on the lower portion side and at the same time provided with a memory element array including at least a decoder and a sense amplifier on the upper portion side. Also, in the second semiconductor chip193, the analog/digital converters and the memory elements are connected electrically through the penetration contact portions84which pass through the region in which the analog/digital converter array is formed.

The semiconductor image sensor module191ofFIG. 31Ais constituted such that the pads82are formed on the undersurface of the second semiconductor chip193, the pads81are formed on the upper surface of the first semiconductor chip52, and the first semiconductor chip52and the second semiconductor chip193are pressed to contact each other while applying heat so as to connect the pad82and81. By bonding the region other than the pads81and82by means of adhesive material, the bonding strength between the first and the second semiconductor chips52and193is further intensified.

In the semiconductor image sensor module192ofFIG. 31B, pads are not formed, the penetration contact portions84are formed in the region in which the analog/digital converter array is formed on the lower portion side of the second semiconductor chip193, and contact portion84″ are formed in the transistor forming region56of the first semiconductor chip52. Then, the semiconductor image sensor module192is constituted by connecting the first semiconductor chip52and the second semiconductor chip193by causing the contact portions84and84″ to face each other and to contact each other by applying heat and pressure.

There are shown inFIG. 32outlines of a ninth exemplified embodiment of a semiconductor image sensor module according to the present invention together with a method of manufacturing the same. In the semiconductor image sensor module194according to this exemplified embodiment, first, as shown inFIG. 32A, the first semiconductor chip52and the second semiconductor chip193are formed. The first semiconductor chip52is provided with the CMOS image sensor60in which a plurality of pixels are arranged regularly and each pixel is constituted by the photodiode forming region57and the transistor forming region56, and the pads81are formed on the upper surface of the transistor forming region56. The second semiconductor chip193is provided with an analog/digital converter array composed of a plurality of analog/digital converters on the lower portion side and at the same time is provided with a memory element array including at least a decoder and a sense amplifier on the upper portion side. In this second semiconductor chip193, the pads82are formed on the undersurface of the lower side portion in which the analog/digital converter array has been formed, the penetration contact portions84which pass through the lower side portion are formed, and at the same time, the pads82and the penetration contact portions84are connected through the wiring layers170.

Next, as shown inFIG. 32B, the pads81of the first semiconductor chip52and the pads82of the second semiconductor chip193are joined through the bumps (micro bumps)83by applying heat and pressure. Parallel connection in units of several pixels becomes possible by means of these bumps83. In this manner, the semiconductor image sensor module194according to the ninth exemplified embodiment is manufactured.

There is shown inFIG. 33a manufacturing method of the semiconductor image sensor module191ofFIG. 31A. First, as shown inFIG. 33A, the first semiconductor chip52and the second semiconductor chip193are formed. The first semiconductor chip52is provided with the CMOS image sensor60in which a plurality of pixels are arranged regularly and each pixel is constituted by the photodiode forming region57and the transistor forming region56, and the pads81are formed on the upper surface of the transistor forming region56. The second semiconductor chip193is provided with an analog/digital converter array composed of a plurality of analog/digital converters on the lower portion side and at the same time is provided with a memory element array including at least a decoder and a sense amplifier on the upper portion side. In this second semiconductor chip193, the pads82are formed on the undersurface of the lower side portion in which the analog/digital converter array is formed, the penetration contact portions84which pass through the lower side portion are formed, and at the same time, the pads82and the penetration contact portions84are connected through the wiring layers170.

Next, as shown inFIG. 33B, the first semiconductor chip52and the second semiconductor chip193are joined by applying heat and pressure such that the pads81and82are connected facing each other. By forming the pads81and82small, parallel connection in units of several pixels becomes possible. By bonding the region other than the connection region of the pads81and82by means of adhesive material, the bonding strength is further intensified. In this manner, the semiconductor image sensor module191ofFIG. 31Ais manufactured.

There is shown inFIG. 34a manufacturing method of the semiconductor image sensor module192ofFIG. 31B. First, as shown inFIG. 34A, the first semiconductor chip52and the second semiconductor chip193are formed. The first semiconductor chip52is provided with the CMOS image sensor60in which a plurality of pixels are arranged regularly and each pixel is constituted by the photodiode forming region57and the transistor forming region56, and the contact portions84″ are formed in the transistor forming region56. The second semiconductor chip193is provided with an analog/digital converter array composed of a plurality of analog/digital converters on the lower portion side and at the same time is provided with a memory element array including at least a decoder and a sense amplifier on the upper portion side. In this second semiconductor chip193, the penetration contact portions are formed on the lower side portion in which the analog/digital converter array has been formed, so as to pass therethrough. No pads are formed on the first and the second semiconductor chips52and193.

Next, as shown inFIG. 34B, the first semiconductor chip52and the second semiconductor chip193are joined by applying heat and pressure such that the contact portion84″ and the penetration contact portion84are connected facing each other. In this manner, the semiconductor image sensor module192of FIG.31B is manufactured. In this manufacturing method, alignment is difficult, but it is possible to increase the number of pixels per unit area to the utmost. Also, in the exemplified embodiments inFIG. 32toFIG. 34, it is possible in the semiconductor image sensor module192ofFIG. 34to make the height from the undersurface of the first semiconductor chip to the upper surface of the second semiconductor chip the smallest.

There are shown inFIGS. 35 to 37outlines of tenth to twelfth exemplified embodiments of a semiconductor image sensor module according to the present invention together with a method of manufacturing the same. The semiconductor image sensor modules according to the tenth to twelfth exemplified embodiments are constituted by joining a first semiconductor chip196including the photodiode forming region57, the transistor forming region56, and the analog/digital converter array195, and a second semiconductor chip197in which a memory array has been formed. In the first semiconductor chip196, the analog/digital converter array195is connected on the side of the transistor forming region56. By employing such a constitution, the analog signal generated in the photodiode forming region57can be converted to a digital signal by the analog/digital converter without picking up a noise in, for example, the bumps (micro bumps)83inFIG. 32B. For this reason, the final picture output signal contains less noise.

There is shown inFIG. 35a semiconductor image sensor module of the tenth exemplified embodiment. In a semiconductor image sensor module198according to this exemplified embodiment, the first semiconductor chip196and the second semiconductor chip197are formed. The first semiconductor chip196is constituted to include the CMOS image sensor constituted by the photodiode forming region57formed on the lower portion side and the transistor forming region56formed in the intermediate portion and the analog/digital converter array195formed on the upper portion side. In the region in which the analog/digital converter array195has been formed, there are formed the penetration contact portions84, and the pads81connected with the penetration contact portions84are formed on the upper surface. The second semiconductor chip197is constituted by forming a memory array and by forming the pad82on the undersurface.

Next, as shown inFIG. 35B, the first semiconductor chip196and the second semiconductor chip197are joined by forming the bumps (micro bumps)83between the pads81and the pads82and by applying heat and pressure In this manner, the semiconductor image sensor-block198of the tenth exemplified embodiment is manufactured. In this semiconductor image sensor-block198, parallel connection in units of several pixels becomes possible by means of the bumps83.

There is shown inFIG. 36a semiconductor image sensor module of an eleventh exemplified embodiment. With respect to the semiconductor image sensor module199according to this exemplified embodiment, first, as shown inFIG. 36A, the first semiconductor chip196and the second semiconductor chip197are formed similarly as mentioned above. The constitutions of the first semiconductor chip196and the second semiconductor chip197are similar to those ofFIG. 35, so that detailed explanations thereof will be omitted by putting the same reference numerals on the corresponding portions thereof.

Next, as shown inFIG. 36B, the first semiconductor chip196and the second semiconductor chip197are joined by applying heat and pressure such that the pads81and82are connected facing each other. In this manner, the semiconductor image sensor-block199of the eleventh exemplified embodiment is manufactured. In this semiconductor image sensor module199, by forming the pads81and82small, parallel connection in units of several pixels becomes possible. It should be noted that by bonding the region other than the connection region of the pads81and82by means of adhesive material, the bonding strength between the first and the second semiconductor chips196and197is further intensified.

There is shown inFIG. 37a semiconductor image sensor module of a twelfth exemplified embodiment. With respect to the semiconductor image sensor module200according to this exemplified embodiment, first, as shown inFIG. 37A, the first semiconductor chip196and the chip197are formed similarly as mentioned above. The constitution of the first semiconductor chip196is similar to the one ofFIG. 35other than that no pads are formed, so that detailed explanations thereof will be omitted by putting the same reference numerals on the corresponding portions thereof. Also, the second semiconductor chip197is constituted by forming a memory array and at the same time by forming contact portions201so as to be exposed to the undersurface. Various forms of the contact portion201can be conceived and, for example, it is also possible to form it so as to pass therethrough. No pads are formed in this second semiconductor chip197.

Next, as shown inFIG. 37B, the first semiconductor chip196and the second semiconductor chip197are joined by applying heat and pressure such that the penetration contact portions84and the contact portions201are connected facing each other. In this manner, the semiconductor image sensor module200of the twelfth exemplified embodiment is manufactured. In the manufacturing method of the semiconductor image sensor module200according to this twelfth exemplified embodiment, alignment is difficult, but it is possible to increase the number of pixels per unit area to the utmost. Also, in the exemplified embodiments from the tenth exemplified embodiment to the twelfth exemplified embodiment, it is possible in the semiconductor image sensor module200of the second exemplified embodiment to make the height from the undersurface of the first semiconductor chip196to the upper surface of the second semiconductor chip197the smallest.

Next, it will be explained with respect to a thirteenth exemplified embodiment of a semiconductor image sensor module according to the present invention. The semiconductor image sensor module according to this exemplified embodiment has a constitution in respective exemplified embodiments described above such that the floating diffusion is shared by a plurality of pixels in the transistor forming region thereof. Thereby, it is possible to increase the photodiode area per unit pixel area.

In addition, it is possible to employ a constitution that under a condition that the floating diffusion is shared by a plurality of pixels in the transistor forming region, further, the amplifier transistor is also shared by a plurality of pixels. With this constitution also, it is possible to further increase the photodiode area per unit pixel area.

There is shown inFIG. 38an equivalent circuit in a pixel in a case that a portion of the pixel transistor circuit is shared by four pixels in the transistor forming region.

This equivalent circuit is constituted such that there are provided separate transfer transistors212corresponding to four light receiving portions (photodiodes PD)210of four pixels, these transfer transistors212are connected with a common floating diffusion (FD) portion to share one amplifier transistor214and one reset transistor220or the like in the subsequent stage. The signal charge is connected to a signal output line through the amplifier transistor214. It is also possible to switch the output to the signal output line by providing a transfer transistor between the amplifier transistor214and the signal output line.

It is possible to apply the pixel structure sharing this floating diffusion portion with a plurality of pixels to the back-illuminated type CMOS image sensor according to the present invention. For example, when the micro bump requires an area corresponding to 4 pixels, the floating diffusion FD, the amplifier transistor214, and the reset transistor220are shared by 4 pixels. In this manner, even in a case that the necessary area of the micro bump is large, it needs not design one pixel with a large area corresponding to the necessary area of the micro bump thereof, so that it is possible to increase the number of pixels per unit area.

Also, the description has been made with respect to a case that a portion of the pixel transistor circuit is shared by four pixels in the transistor forming region, but a case is also conceivable that a portion of the pixel transistor circuit is shared by three pixels in the transistor forming region or a case that a portion of the pixel transistor circuit is shared by six pixels in the transistor forming region.

Next, it will be explained with respect to a fourteenth exemplified embodiment of a semiconductor image sensor module according to the present invention. The semiconductor image sensor module according to this exemplified embodiment is constituted by being equipped with color coating technology that arranges pixels in a zigzag (in so-called oblique arrangement). With the constitution of this pixel arrangement, the imaginary number of pixels per unit pixel area is increased as compared with a square pixel arrangement. It is possible to apply this pixel arrangement to the back-illuminated type CMOS image sensor according to the present invention. For example, in a case that the micro bump requires an area for a plurality of pixels, if the floating diffusion FD is shared by a plurality of pixels as in the thirteenth exemplified embodiment described above, it needs not design one pixel with a large area corresponding to the necessary area of the micro bump. Consequently, is possible to increase the number of pixels per unit area, and further, the imaginary number of pixels per unit pixel area is increased as compared with a square pixel arrangement.

There is shown inFIG. 39a general constitution of a semiconductor image sensor module according to a fourteenth exemplified embodiment of the present invention, that is, a back-illuminated type CMOS image sensor. The semiconductor image sensor of this exemplified embodiment is an example that color-separation is carried out without using an on chip color filter. A semiconductor image sensor261according to this exemplified embodiment is formed by being provided with an imaging region264formed on the front face of the same semiconductor chip262(corresponding to first semiconductor chip52), which becomes a light receiving region in which a plurality of pixels263are arranged two-dimensionally, and with peripheral circuits265and266arranged on the outside of this imaging region264for selection of the pixels263and for signal output. It is allowed that the peripheral circuits265and266are not within the photodiode forming region57mentioned above, and they may be located within the transistor forming region56. The peripheral circuit265is constituted by a vertical scanning circuit (so-called vertical register circuit) which is positioned on the side of the imaging region264. The peripheral circuit266is constituted by a horizontal scanning circuit (so-called horizontal register circuit) positioned on the lower side of the imaging region264and an output circuit or the like (including a signal amplification circuit, an A/D converter circuit, a synchronous signal generating circuit or the like).

In the imaging region264, a plurality of pixels are arranged in a so-called oblique arrangement. More specifically, it is constituted by a first pixel group in which a plurality of pixels263A are arranged two-dimensionally with predetermined pitches W1in the horizontal and vertical directions approximately in a lattice shape, and a second pixel group in which a plurality of pixels263B are arranged two-dimensionally deviated by approximately ½ pitch of the aforesaid pitch W1both in the horizontal direction and in the vertical direction with respect to the first pixel group, and the pixels263A and263B are arranged and formed just in a square lattice shape deviated obliquely. In this example, the pixels263B are arranged in odd lines, and the pixel263A are arranged in even lines deviated by ½ pitch. For the on chip color filters, primary color filters of red (R), green (G) and blue (B) are used in this example. InFIG. 39, the designation of R/B shows that it is either one of red (R) and blue (B). More specifically, the red (R) and the blue (B) are arranged alternatively along the vertical direction inFIG. 39so as to be red (R)-blue (B)-red (R)-blue (B) . . . .

Next, it will be explained with respect to a fifteenth exemplified embodiment of a semiconductor image sensor module according to the present invention. The semiconductor image sensor module of this exemplified embodiment is an example in which an ADC shared by pixels is installed. Here, there is shown a flow of charge signals in the case of any one exemplified embodiment of the first to fourteenth exemplified embodiments mentioned above. Due to sharing of FD by pixels (thirteenth exemplified embodiment) and zigzag coating (fourteenth exemplified embodiment), charge signals outputted from the transistor forming region are transmitted to the inside of the AD conversion array.

FIG. 40is a block diagram showing a constitution of a solid-state imaging device applied to a semiconductor image sensor module according to the fifteenth exemplified embodiment, for example, a CMOS image sensor equipped with a pixel parallel ADC.

As shown inFIG. 40, a CMOS image sensor310according to this exemplified embodiment is configured to include a line or unit pixel scanning circuit313, a column processing unit314, a reference voltage supply unit315, a column or unit pixel scanning circuit316, a horizontal output line317, and a timing control circuit318, in addition to a pixel array unit312in which a large number of unit pixels311each including a photoelectric conversion element are arranged in a line-column form (in a matrix form) two dimensionally.

In this system constitution, the timing control circuit318generates, based on the master clock MCK, clock signals which become the basis of the operations of the line or unit pixel scanning circuit313, the column or unit pixel processing unit314, the reference voltage supply unit315, the column or unit pixel scanning circuit316and the like, and control signals and the like, and supplies them to the line or unit pixel scanning circuit313, the column processing unit314, the reference voltage supply unit315, the column or unit pixel scanning circuit316and the like.

Also, a peripheral drive system and a signal processing system which drive or control each unit pixel311of the pixel array unit312, that is, the line or unit pixel scanning circuit313, the reference voltage supply unit315, the column or unit pixel scanning circuit316, the timing control circuit318and the like, are integrated in a transistor forming region356on a same chip319(corresponding to the first semiconductor chip52) as the pixel array unit312.

For the unit pixel311, although graphic indication is omitted here, it is possible to use a pixel of 3 transistor constitution, which includes, in addition to a photoelectric conversion element (for example, photodiode), for example, a transfer transistor transferring charges obtained by performing photoelectric conversion in aforesaid photoelectric conversion element to the FD (floating diffusion) portion, a reset transistor controlling the potential of this FD portion, and an amplifier transistor outputting signals corresponding to the potential of the FD portion, and further, it is possible to use a pixel of 4 transistor constitution which further includes a selection transistor separately for carrying out pixel selection or the like.

In the pixel array unit312, unit pixels311are arranged two dimensionally in m columns and n lines, and at the same time, to the pixel arrangement of these m lines and n columns, line or unit pixel control lines321(321-1to321-n) are wired for respective lines or unit pixels, and column or unit pixel signal lines322(322-1to322-m) are wired for respective columns or unit pixels. Alternatively, to the pixel arrangement of these m lines and n columns, it is allowed to wire pixel control lines for respective pixels so as to control each pixel. Respective terminals of the line control lines321-1to321-nare connected with corresponding output terminals of the line scanning circuit313. The line or unit pixel scanning circuit313is constituted by a shift register or the like and carries out controls of line or unit pixel addresses of the pixel array unit312and line or unit pixel scanning, through the line or unit pixel control lines321-1to321-n. The column or unit pixel processing unit314includes ADCs (analog-to-digital conversion circuits)323-1to323-mprovided, for example, for respective pixel columns or unit pixels of the pixel array unit312, that is, for respective columns or unit pixel signal lines322-1to322-m, and outputs analog signals outputted from the unit pixels311of the pixel array unit312for respective columns or unit pixels by converting them to digital signals.

This exemplified embodiment is characterized by the constitution of these ADCs323-1to323-m, and it will be described later with respect to the details thereof.

The reference voltage supply unit315includes, for example, a DAC (digital-to-analog conversion circuit)351as a means for generating a reference voltage Vref of a so-called ramp (RAMP) waveform whose level changes in an inclined state as time elapses. It should be noted that the means for generating the reference voltage Vref of a ramp waveform is not limited to the DAC351. The DAC351generates the reference voltage Vref of a ramp waveform based on the clock CK given from this timing control circuit318under a control by a control signal CS1given from the timing control circuit318and supplies it to the ADCs323-1to323-mof the column or unit pixel processing unit314.

Here, it will be explained specifically with respect to details of the constitution of the ADCs323-1to323-mby which this exemplified embodiment is characterized. It should be noted that each of the ADCs323-1to323-mhas a constitution that the AD conversion operation can be carried out selectively between the operation mode corresponding to a usual frame rate mode by means of a progressive scanning system in which information of all of the unit pixels311is read out and the operation mode corresponding to a high-speed frame rate mode which increases the frame rate as much as N times, for example, 2 times as compared with the occasion of the usual frame rate mode by setting the exposure period of the unit pixel311to 1/N. The changeover of these operation modes is executed according to the control by control signals CS2, CS3given from the timing control circuit318. Also, to the timing control circuit318, instruction information is given from an external system controller (not shown) for changing the operation mode between the usual frame rate mode and the high-speed frame rate mode.

The ADC323-1to323-mhave the same constitution and are arranged in the AD conversion array in the first semiconductor chip52or the second semiconductor chip described above. Also, it is allowed to arrange the column or unit pixel processing unit314, a comparator331, for example, an up/down counter (in the drawing, marked as U/D CNT)332which is a counting means, a transfer switch333and a memory device334, a DAC351, the reference voltage supply unit315, and the timing control circuit318in the AD conversion array of the first semiconductor chip52or the second semiconductor chip. Also, different from the constitution that the reference voltage supply unit315, the column or unit pixel scanning circuit316, and the timing control circuit318are provided in the transistor forming region56of aforesaid first semiconductor chip52, it is allowed to arrange the reference voltage supply unit, the column or unit pixel scanning circuit, and the timing control circuit in the AD conversion array within the first semiconductor chip52or the second semiconductor chip.

Here, it will be explained by taking the ADC323-mfor each column or unit pixel. The ADC323-mhas a constitution including the comparator331, for example the up/down counter (in the drawing, marked as U/D CNT)332which is a counting means, the transfer switch333, and the memory device334.

The comparator331compares signal voltage Vx of the column or unit pixel signal line322-mcorresponding to the signal outputted from each unit pixel311of the n-th column of the pixel array unit312with the reference voltage Vref of a ramp waveform supplied from the reference voltage supply unit315and for example when the reference voltage Vref is larger than the signal voltage Vx, the output Vco becomes a “H” level, and when the reference voltage Vref is equal to or less than the signal voltage Vx, the output Vco becomes a “L” level.

The up/down counter332is an asynchronous counter, and is provided with the clock CK from the timing control circuit318simultaneously with the DAC351under the control by the control signal CS2given from the timing control circuit318, and by carrying out a down (DOWN) count or up (UP) count in synchronism with this clock CK, a comparison period from the start to the end of the comparison operation is measured. Specifically, in the usual frame rate mode, in a signal reading-out operation from one unit pixel311, the comparison period on the first readout is measured by carrying out a down-count on the occasion of the first readout operation and the comparison period on the second readout is measured by carrying out an up-count on the occasion of the second readout operation. On the other hand, in the high-speed frame rate mode, a count result with respect to a unit pixel311of a certain line is maintained as it is, and subsequently, with respect to a unit pixel311of a next line, the comparison period on the occasion of the first readout is measured by carrying out a down-count from the previous count result on the occasion of the first readout operation and the comparison period on the occasion of the second readout is measured therefrom by carrying out an up-count on the occasion of the second readout operation.

In the usual frame rate mode, the transfer switch333becomes an ON (closed) state at the time point when the count operation of the up/down counter332with respect to a unit pixel311of a certain line is completed under the control by means of the control signal CS3given from the timing control circuit318, and transfers the count result of the up/down counter332to the memory device334. On the other hand, in the high-speed frame rate mode of, for example, N=2, it remains in an OFF (open) state at the time point when the count operation of the up/down counter332with respect to a unit pixel311of a certain line is completed, and subsequently, it becomes an ON state at the time point when the count operation of the up/down counter332with respect to a unit pixel311of a next line is completed, and the count result for vertical 2 pixels of this up/down counter332is transferred to the memory device334. In this manner, the analog signals which are supplied for respective columns or unit pixels by way of column or unit pixel signal lines322-1to322-mfrom respective unit pixels311of the pixel array unit312are converted to digital signals of N bits according to respective operations of the comparator331and the up/down counter332in the ADC323(323-1to323-m) and stored in the memory device334(334-1to334-m).

The column or unit pixel scanning circuit316is constituted by a shift register or the like and carries out control of line or unit pixel addresses and scanning of column or unit pixels of the ADCs323-1to323-min the column or unit pixel processing unit314. Under the control by means of this line or unit pixel scanning circuit316, the digital signals of N bits AD-converted in respective ADCs323-1to323-mare read out sequentially to the horizontal output line317and outputted as image data by way of this horizontal output line317.

Although not shown particularly because it is not related directly to this exemplified embodiment, it should be noted that it is also possible to provide a circuit applying various kinds of signal processes to the image data outputted by way of the horizontal output line317or the like, other than the aforesaid components. In the CMOS image sensor310equipped with an ADC with parallel column or unit pixels according to this exemplified embodiment having the aforesaid constitution, because it is possible to transfer the count result of the up/down counter332selectively to the memory device334through the transfer switch333, it is possible to control the count operation of the up/down counter332and the readout operation of the count result of this up/down counter332to the horizontal output line317independently.

Next, it will be explained with respect to the operation of the CMOS image sensor310according to the fifteenth exemplified embodiment of the aforesaid constitution by using a timing chart ofFIG. 41.

Here, explanation with respect to the specific operation of the unit pixel311will be omitted, however, as well known, the reset operation and the transfer operation are carried out in each unit pixel311, and in the reset operation, the potential of the FD portion when the unit pixel is reset to a predetermined potential is outputted as a reset component from the unit pixel311to the column or unit pixel signal lines322-1to322-m, and in the transfer operation, the potential of the FD portion when the charge by means of photoelectric conversion is transferred from the photoelectric conversion element is outputted as a signal component from the unit pixel311to the column or unit pixel signal lines322-1to322-m.

A certain line or unit pixel i is selected by means of line or unit pixel scanning by the line or unit pixel scanning circuit313, and after a first readout operation from the unit pixel311of the selected line or unit pixel i to the column or unit pixel signal lines322-1to322-mhas been stabilized, a reference voltage Vref having a ramp waveform is applied from the DAC351to each comparator331of the ADCs323-1to323-m, thereby the comparison operation with respect to each of the signal voltages Vx of the column or unit pixel signal lines322-1to322-mand the reference voltage Vref is carried out in the comparator331. At the same time when the reference voltage Vref is applied to the comparator331, the clock CK is applied from the timing control circuit318to the up/down counter332, thereby in this up/down counter332, the comparison period in the comparator331on the occasion of the first readout operation is measured by the down count operation.

Then, when the reference voltage Vref and the signal voltage Vx of the column or unit pixel signal lines322-1to322-mbecome equal to each other, the output Vco of the comparator331is inverted from the “H” level to the “L” level. Receiving this polarity inversion of the output Vco of the comparator321, the up/down counter332stops the down count operation and holds the counted value corresponding to the first comparison period in the comparator331. In this first readout operation, as previously noted, the reset component ΔV of the unit pixel311is read out. In this reset component ΔV, a fixed pattern noise which fluctuates with respect to each unit pixel311is included as an offset.

However, because fluctuation of this reset component ΔV is small generally, and also, the reset level is common for all the pixels, the signal voltage Vx of each of the column or unit pixel signal lines322-1to322-mis almost well-known. Consequently, on the occasion of the readout of the first reset component ΔV, it is possible to shorten the comparison period by adjusting the reference voltage Vref.

In this exemplified embodiment, comparison of the reset component ΔV is carried out during the count period for 7 bits (128 clock). In the second readout operation, in addition to the reset component ΔV, the signal component Vsig corresponding to the amount of incident light of each unit pixel311is read out by an operation similar to the readout operation of the first reset component ΔV. More specifically, after the second readout from the unit pixel311of the selection line or unit pixel i to the column or unit pixel signal lines322-1to322-mhas been stabilized, the reference voltage Vref is applied from the DAC351to each comparator331of the ADCs323-1to323-m, thereby the comparison operation with respect to each of the signal voltages Vx of the column or unit pixel signal lines322-1to322-mand the reference voltage Vref is carried out in the comparator331. At the same time, the second comparison period in this comparator331is measured in the up/down counter332by an up count operation conversely to the first one.

In this manner, by making the count operation of the up/down counter332a down count operation at the first time and an up count operation at the second time, a subtraction process of (second comparison period)-(first comparison period) is carried out in this up/down counter332automatically. Then, when the reference voltage Vref and the signal voltage Vx of the column signal lines322-1to322-mbecome equal to each other, the output Vco of the comparator331is inverted in polarity, and receiving this polarity inversion, the count operation of the up/down counter332stops. As a result, the counted value corresponding to the result of the subtraction process of (second comparison period)−(first comparison period) is held in the up/down counter332. It is calculated as (second comparison period)−(first comparison period)=(signal component Vsig+reset component ΔV+offset component of ADC323)−(reset component ΔV+offset component of ADC323)=(signal component Vsig), and owing to the above two readout operations and the subtraction process in the up/down counter332, the offset component of each of the ADCs323(323-1to323-m) is also removed in addition to the reset component ΔV including the fluctuation of each unit pixel311, so that it is possible to extract only the signal component Vsig corresponding to the amount of incident light of each unit pixel311.

Here, the process for removing the reset component ΔV including fluctuation of each unit pixel311is a so-called CDS (correlated double sampling) process. On the occasion of the second readout, because the signal component Vsig corresponding to the amount of incident light is read out, it is necessary to greatly change the reference voltage Vref in order to judge the magnitude of the amount of light in a wide range. Consequently, it is constituted in the CMOS image sensor310according to this exemplified embodiment such that comparison after readout of the signal component Vsig is carried out during the count period for 10 bits (1024 clocks). In this case, the compared number of bits is different between the first time and the second time, but by making inclination of the ramp waveform of the reference voltage Vref identical for both of the first and second times, the accuracy of AD conversion can be made equal to each other, so that a correct subtraction result can be obtained as a result of the subtraction process of (second comparison period)−(first comparison period) by means of the up/down counter332.

After the termination of a series of AD conversion operations mentioned above, a digital value of N bits is held in the up/down counter332. Then, the digital values of N bits (digital signals) which have been AD-converted in respective ADCs323-1to323-mof the column processing unit314are outputted sequentially to the outside by way of the horizontal output line317having an N-bit width by means of column or unit pixel scanning by the column or unit pixel scanning circuit316. Thereafter, similar operations are repeated sequentially for respective lines or unit pixels, and thereby a two dimensional picture is generated. Also, in the CMOS image sensor310equipped with the column or unit pixel parallel ADC according to this exemplified embodiment, each of the ADCs323-1to323-mhas a memory device334, so that it is possible to execute the readout operation and the up/down count operation in parallel with respect to the unit pixels311of (i+1)thline while transferring the digital value after AD conversion to the memory device34and outputting it externally from the horizontal output line317with respect to the unit pixels311of ithline.

According to this exemplified embodiment, in a solid-state imager device having a constitution that analog signals outputted from the unit pixel through the column signal line are converted to digital values and are read out, even if the exposure period of the unit pixel is shortened by adding respective digital values among a plurality of unit pixels to be read out, it never occurs as a result that the amount of information of one pixel decreases, so that it is possible to attempt achieving a high frame rate mode, without incurring sensitivity lowering.

It is possible to form the penetration contact portions (inside of the first, second and third semiconductor chips) and the contact portions84″ and201in all the exemplified embodiments described above by Cu, Al, W, WSi, Ti, TiN, silicide or a combination thereof.

There is shown, inFIG. 42, a sixteenth exemplified embodiment of a semiconductor image sensor module according to the present invention.FIG. 42is a schematic cross-section diagram showing a constitution of a semiconductor image sensor module mounting a back-illuminated type CMOS solid-state imaging device. A semiconductor image sensor module400according to this exemplified embodiment is formed, for example, by mounting a sensor chip401awhich is a back-illuminated type CMOS solid-state imaging device provided with an imaging pixel unit on an interposer (intermediate substrate)403and a signal processing chip402which is provided with a peripheral circuit unit of a signal process or the like.

In the sensor chip401a, an interlayer insulation layer420is formed on a support substrate430, and buried wiring layers421are buried inside of the layer420. A semiconductor layer412is formed in the upper layer of the layer420and a surface insulation film411is formed on the front face thereof. There are formed, in the semiconductor layer412, a photodiode414which becomes a photoelectric conversion element, electrodes413for testing, and the like. Also, a portion of the buried wiring layers421becomes a gate electrode formed through a gate insulation film with respect to the semiconductor layer412, and thus a MOS transistor415is constituted. Further, there are formed support substrate penetrating wirings431which pass through the support substrate430to be connected with the buried wiring layers421, and there are formed, on the front faces of the support substrate penetrating wirings431, protrusion electrodes (bumps)432which project from the front face of the support substrate430. The bumps (micro bumps)432are protrusion like metal electrodes formed by electrolytic plating or the like on pads which are smaller than a usual pad electrode used for wire bonding.

The sensor chip401ahaving the constitution mentioned above is a so-called back-illuminated type CMOS solid-state imaging device in which when light is illuminated from the surface insulation film411side to the photodiode414formed in the semiconductor layer412, signal charge is generated and accumulated in the photodiode. The MOS transistor415has the functions of transfer of signal charge accumulated in the photodiode414to the FD portion and signal amplification or resetting and the like. In the constitution mentioned above, the semiconductor layer is obtained by thinning the rear face of the semiconductor substrate, and has a structure of being pasted with the support substrate430in order to stabilize the substrate shape.

As described above, the CMOS solid-state imaging device according to this exemplified embodiment is a back-illuminated type solid-state imaging device in which there are formed buried wirings connected with a plurality of pixels on one surface of the semiconductor layer in which a plurality of pixels including photoelectric conversion elements and field effect transistors have been formed, and the other surface of the semiconductor layer becomes a light receiving surface of the photoelectric conversion element.

The sensor chip401amentioned above is mounted by flip chip on the interposer403, in which the wirings440and the insulation layer441for insulating them have been formed, from the support substrate430side which is the opposite side of the light illumination side such that the land, which is formed by causing a portion of the front face of the wiring to be exposed from the opening portion of the insulation layer, and the bump are joined.

On the other hand, the signal processing chip402in which peripheral circuit units have been formed is mounted on the interposer403by flip chip, for example, through bumps.

The semiconductor image sensor module400having such a constitution is mounted on another mounting substrate together with the interposer403, and is connected electrically to be used, for example, by means of the wire bonding442or the like. For example, there is formed, on the interposer403, an electrode PAD for evaluating the function of 1 chip made by connecting the aforesaid sensor chip (CMOS solid-state imaging device)401aand the signal processing chip402.

FIG. 43is a block diagram showing a constitution of an image sensor (corresponding to semiconductor image sensor module) installing a CMOS solid-state imaging device according to this exemplified embodiment.FIG. 44is an equivalent circuit diagram showing a pixel constitution of a CMOS solid-state imaging device according to this exemplified embodiment. The image sensor according to this exemplified embodiment is constituted by an imaging pixel unit512, a V selection means (vertical transfer register)514, an H selection means (horizontal transfer register)516, a timing generator (TG)518, a S/H-CDS (sampling hold-correlated double sampling) circuit unit520, an AGC unit522, an A/D conversion unit524, a digital amplifier unit526and the like. It is possible, for example, to take a configuration that the imaging pixel unit512, the V selection means514, the H selection means516, and the S/H & CDS circuit unit520are assembled on 1 chip collectively to be the sensor chip401ainFIG. 42and the remaining circuit units are assembled collectively on the signal processing chip402. Alternatively, it is also possible to configure such that only the imaging pixel unit512is formed in the sensor chip401a.

In the imaging pixel unit512, a large number of pixels are arranged two dimensionally in a matrix form, and in each pixel, as shown inFIG. 44, a photodiode (PD)600which is a photoelectric conversion element for generating and accumulating the signal charge corresponding to the amount of received light is provided, and further, there are provided four MOS transistors, i.e., a transfer transistor620for transferring the signal charge converted and accumulated by this photodiode600to a floating diffusion portion (FD portion)610, a reset transistor630for resetting the voltage of the FD portion610, an amplifier transistor640for outputting an output signal corresponding to the voltage of the FD portion610, and a selection (address) transistor650for outputting the output signal of the this amplifier transistor640to a vertical signal line660.

In the pixel having such a constitution, the signal charge converted photoelectrically in the photodiode600is transferred to the FD portion610by the transfer transistor220. The FD portion610is connected with the gate of the amplifier transistor640, and the amplifier transistor640constitutes a source follower with a constant current source670provided outside of the imaging pixel unit512, so that when the address transistor650is turned ON, a voltage corresponding to the voltage of the FD portion610is outputted to the vertical signal line660. Also, the reset transistor630resets the voltage of the FD portion610to a constant voltage not depending on the signal charge (to a drive voltage Vdd inFIG. 44). Also, in the imaging pixel unit512, various kinds of driving wirings for driving and controlling respective MOS transistors are wired in the horizontal direction, respective pixels of the imaging pixel unit512are selected in horizontal line (pixel line) units sequentially in the vertical direction by means of the V selection means514, and the MOS transistors of respective pixels are controlled by various kinds of pulse signals from the timing generator518, thereby signals of respective pixels are read out to the S/H-CDS unit520for each pixel column by way of the vertical signal line660.

The S/H-CDS unit520provides a S/H-CDS circuit for each pixel column of the imaging pixel unit512and carries out signal processing such as a CDS (correlated double sampling) or the like with respect to the pixel signal read out from each of the pixel columns of the imaging pixel unit512. The H selection means516outputs the pixel signal from the S/H-CDS unit520to the AGC unit522. The AGC unit522carries out a predetermined gain control with respect to the pixel signal from the S/H-CDS unit520selected by the H selection means516and outputs the pixel signal to the A/D conversion unit524. The A/D conversion unit524converts the pixel signal from the AGC unit522from an analog signal to a digital signal and outputs it to the digital amplifier unit526. The digital amplifier unit526carries out necessary amplification and/or buffering to the digital signal output from the A/D conversion unit524and outputs it from an external terminal which is not shown. The timing generator518supplies various kinds of timing signals also to respective portions other than the pixels of the imaging pixel unit512mentioned above.

It becomes possible for the semiconductor image sensor module (that is, CMOS image sensor)400according to the sixteenth exemplified embodiment mentioned above to input the signals outputted from the pixels of the CMOS image sensor to the signal process device directly through the micro bumps with respect to each pixel unit or each unit of a plurality of pixels, without inputting the output signals from the pad electrode in the chip periphery to the signal process device after outputting signals outputted from the pixels to the pixel peripheral circuit, as in the past. Thereby, it becomes possible to provide a highly functional device that is fast in the signal process speed between the devices and is highly advanced and in which the image sensor and the signal process device are made by 1 chip. Also, the aperture ratio of the photodiode is improved, chip utilization is improved, and simultaneous shuttering of all the pixels can be realized.

It will be explained with respect to a manufacturing method of the back-illuminated type CMOS solid-state imaging device according to the sixteenth exemplified embodiment. First, as shown inFIG. 45A, for example, an insulation film411which is composed of oxide silicon or the like and which becomes a surface insulation film by post-process is formed on the front face of a semiconductor substrate410composed of silicon or the like by means of a thermal oxidation method, a CVD (chemical vapor deposition) method or the like. Further, for example, a semiconductor layer412of silicon or the like is formed for an upper layer of the insulation film411, for example, by means of a bonding method, an epitaxial growth method or the like, and thereby a SOI (semiconductor on insulator) substrate is formed. Here, an electrode413for testing is formed in the semiconductor layer412beforehand.

Next, as shown inFIG. 45B, for example, a pn junction is formed by ion-injecting p-type conductive impurity in the n-type semiconductor layer412, thereby the photodiode414is formed in the semiconductor layer412as a photoelectric conversion element, further, a gate electrode is formed on the front face of the semiconductor layer412through a gate insulation film, the MOS transistor415is formed by connecting the gate electrode with the photodiode414and the like, and thereby a plurality of pixels having the constitution mentioned above are formed. Further, for example, the interlayer insulation layer420which covers the MOS transistor is formed. At that time, the buried wiring layers421are formed while being buried in the interlayer insulation layer420so as to be connected with the transistor, the semiconductor layer412and the like.

Next, as shown inFIG. 45C, the support substrate430composed of a silicon substrate, an insulating resin substrate or the like is bonded to the upper layer of the interlayer insulation layer420for example by thermal compression using heat-hardening resin as the adhesive agent or the like.

Next, as shown inFIG. 46A, the support substrate430is thinned from the opposite side of the bonded surface for example by mechanical grinding or the like.

Next, as shown inFIG. 46B, the support substrate penetrating wirings431passing through the support substrate430are formed so as to be connected with the buried wiring layers421.

It is possible to form this, for example, by pattern-forming a resist film by a photolithographic process and carrying out etching such as dry etching or the like to form an opening portion reaching the buried wiring layer421in the support substrate430, and by burying a low resistance metal of copper or the like.

Next, as shown inFIG. 47A, for example, the bumps432projecting from the front face of the support substrate430are formed on the front faces of the support substrate penetrating wirings431by means of a metal plating process or the like.

Next, as shown inFIG. 47B, for example, the semiconductor substrate410is thinned from the semiconductor substrate410side of the SOI substrate until it becomes possible for the photodiode414to receive light. For example, the insulation film411is made a stopper and it is carried out from the rear face side of the semiconductor substrate410by mechanical grinding, wet etching process or the like until the insulation film411is exposed. Thereby, it becomes a constitution that the semiconductor layer412of the SOI substrate is left. Here, the insulation film412exposed on the front face is referred to as a surface insulation film. It is shown for the drawing such that the up and down relation is opposite with respect toFIG. 47A.

As described above, the back-illuminated type CMOS solid-state imaging device (sensor chip)401aaccording to this exemplified embodiment is formed. Further, it is preferable to form an insulation film, for example, by a CVD method on the rear face of the semiconductor substrate (semiconductor layer412) which has been obtained by being thinned. It is possible that this insulation film realizes the object of protecting the silicon surface of the rear face and at the same time functions as an anti-reflection film with respect to the incident light.

The back-illuminated type CMOS solid-state imaging device (sensor chip)401aformed as mentioned above is mounted on the interposer403by flip chip through the bumps432with the light receiving surface side directed upward. For example, the lands and the bumps on the wiring of the interposer403and the bumps on the support substrate of the sensor chip are pressure-bonded at a temperature lower than the melting point of the wiring used in the sensor chip401aor the signal processing chip402and also at a temperature that the bumps are connected electrically stably. In addition, it is also possible, for example, to mount the sensor chip401adirectly on the signal processing chip402so as to be constituted as a module, and also in this case, the above-described method can be employed similarly.

On the other hand, the signal processing chip402in which the peripheral circuit unit has been formed is also similarly mounted on the interposer403by flip chip through the bumps. Thereby, the back-illuminated type CMOS solid-state imaging device (sensor chip)401aand the signal processing chip402are connected through the wirings formed on the interposer403.

It is possible to manufacture an image sensor installing a back-illuminated type CMOS solid-state imaging device according to this exemplified embodiment, in the manner described above. In addition, it is also possible to test the circuits of the sensor chip using the electrode413for testing after carrying out the mounting by flip chip

As described above, according to the manufacturing method of the back-illuminated type CMOS solid-state imaging device of this exemplified embodiment, the semiconductor substrate is thinned after the support substrate is bonded to secure the strength, and also, the penetrating wiring is formed after the support substrate is thinned, so that it is possible to take out the electrode from the support substrate without taking out the electrode from the rear face of the semiconductor substrate and it is possible to manufacture a back-illuminated type CMOS solid-state imaging device having a constitution that the electrode is taken out from the surface on the opposite side of the illumination surface conveniently and easily. Also, based on that the electrode can be formed on the support substrate side which is the opposite side of the surface to which light enters, the degree of freedom of electrode arrangement rises, and it becomes possible to form a large number of micro bumps immediately below a pixel or immediately below the periphery of a pixel without spoiling the aperture ratio of the CMOS image sensor. In this manner, by thinning the rear face of the semiconductor substrate and by connecting a mounting substrate such as an interposer or the like and another semiconductor chip such as a signal processing chip or the like in which bumps are formed by means of respective bumps, it is possible to manufacture a device of high performance and a high function.

As the semiconductor substrate, for example, a substrate such as an SOI substrate in which an oxide film is formed in the substrate beforehand is preferable, because it is possible to use the oxide film in the SOI substrate as a stopper of wet etching for thinning the semiconductor substrate and it is possible to obtain a uniform and flat semiconductor substrate after the thinning process.

There is shown, inFIG. 48, a seventeenth exemplified embodiment of a semiconductor image sensor module according to the present invention.FIG. 48is a schematic cross-section diagram showing a constitution of a semiconductor image sensor module mounting a back-illuminated type CMOS solid-state imaging device. The semiconductor image sensor module401according to this exemplified embodiment is formed similarly as the sixteenth exemplified embodiment, for example, by mounting a sensor chip401bwhich is a back-illuminated type CMOS solid-state imaging device provided with an imaging pixel unit and the signal processing chip402provided with the peripheral circuit unit for signal processing or the like on the interposer (intermediate substrate403).

In the sensor chip401b, the interlayer insulation layer420is formed on the support substrate430, and the buried wiring layers421are buried therein. The semiconductor layer412is formed for the upper layer thereof and surface insulation films (411,419) are formed on the front face thereof. There are formed in the semiconductor layer412the photodiode414and the electrode413for testing or the like. Also, a portion of the buried wiring layers421becomes a gate electrode formed with respect to the semiconductor layer412through a gate insulation film, and thereby the MOS transistor415is constituted. Also, there is formed the semiconductor layer penetrating wiring416connected with the buried wiring layer421through the semiconductor layer412.

Further, the support substrate penetrating wiring431passing through the support substrate430is formed, and the protrusion electrode (bump)432projecting from the front face of the support substrate430is formed on the front face of the support substrate penetrating wiring431. On the other hand, for example, a semiconductor layer and insulation layer penetrating wiring417connected with the support substrate penetrating wiring431through the semiconductor layer412and the interlayer insulation layer420is formed, and the semiconductor layer penetrating wiring416and the semiconductor layer and insulation layer penetrating wiring417are connected by means of a connection wiring418formed on the surface insulation film411.

The support substrate penetrating wiring431has a constitution in this exemplified embodiment to be connected with the buried wiring layers421through the semiconductor layer and insulation layer penetrating wiring417, the connection wiring418and the semiconductor layer penetrating wiring416as mentioned above, but it is not limited toy this, and it may be such a constitution that the support substrate penetrating wiring431is connected with the buried wiring layers421through a portion thereof or directly without any of them.

The sensor chip401bhaving the constitution mentioned above is configured such that when light is illuminated from the surface insulation film (411,419) side to the photodiode414formed in the semiconductor layer412, signal charges are generated, which are then accumulated in the photodiode. Then, this sensor chip401bis a back-illuminated type solid-state imaging device, in which there is formed a buried wiring which is connected with a plurality of pixels on one surface of the semiconductor layer in which a plurality of pixels including photoelectric conversion elements and field effect transistors have been formed, and the other surface of the semiconductor layer becomes a light receiving surface of the photoelectric conversion element.

The sensor chip401bmentioned above is mounted by flip chip on the interposer403in which the wirings440and the insulation layer441insulating them have been formed on the front face thereof from the support substrate430side which is the opposite side of the light illumination side, such that the land formed by a portion of the front face of the wiring exposed from the opening portion of the insulation layer or the like and the bump are joined.

On the other hand, the signal processing chip402in which the peripheral circuit unit has been formed is mounted on the interposer by flip chip for example through bumps. The semiconductor image sensor module401having such a constitution is mounted on another mounting substrate together with the interposer403, and is connected electrically, for example, by the wire bonding442or the like to be used. The constitution of the image sensor (corresponding to semiconductor image sensor module) installing a CMOS solid-state imaging device according to this exemplified embodiment and the constitution of the pixel are similar to those of the sixteenth exemplified embodiment.

The semiconductor image sensor module (that is, CMOS image sensor)401according to the above-mentioned seventeenth exemplified embodiment achieves similar effects as the sixteenth exemplified embodiment.

It will be explained with respect to a manufacturing method of a back-illuminated type CMOS solid-state imaging device according to the seventeenth exemplified embodiment. First, as shown inFIG. 49A, for example, the insulation film411which is formed by oxide silicon or the like and which becomes a surface insulation film in the post-process is formed by a thermal oxidation method, a CVD (chemical vapor deposition) method or the like on the front face of the semiconductor substrate410composed of silicon or the like. Further, for example, the semiconductor layer412of silicon or the like is formed, for example, by a bonding method, an epitaxial growth method or the like in the upper layer of the insulation film411to make a SOI substrate. Here, an electrode413for testing is formed and prepared in the semiconductor layer412.

Next, as shown inFIG. 49B, the photodiode414is formed as a photoelectric conversion element in the semiconductor layer412, for example, by ion-injecting conductive impurity, and further, gate electrodes are formed through a gate insulation film on the front face of the semiconductor layer412to be connected with the photodiode414or the like, thereby the MOS transistor415is formed, and thus a plurality of pixels each having the constitution mentioned above are formed. Further, for example, the interlayer insulation layer420covering the MOS transistor is formed. At that time, it is formed while burying the buried wiring layers421into the interlayer insulation layer420so as to be connected with the transistor, the semiconductor layer412and the like.

On the other hand, the support substrate wirings431becoming support substrate penetrating wirings which reach at least a predetermined depth from the front face of one main surface of the support substrate430composed of a silicon substrate, an insulating resin substrate or the like are formed. Next, as shown inFIG. 49C, the support substrate430is bonded to the upper layer of the interlayer insulation layer420from the side of the support substrate wiring431forming surface.

Next, as shown inFIG. 50A, the semiconductor substrate410is thinned, for example, from the semiconductor substrate410side of the SOI substrate until it becomes possible for the photodiode414to receive light. For example, the insulation film411is made a stopper and it is carried out by mechanical grinding, wet etching or the like from the rear face side of the semiconductor substrate410until the insulation film411is exposed. Thereby, it becomes a constitution that the semiconductor layer412of the SOI substrate is left. It is shown for the drawing such that the up and down relation is made opposite with respect toFIG. 49C.

Next, as shown inFIG. 50B, a connection wiring for connecting the support substrate wiring431and the buried wiring layer421is formed. Specifically, for example, the semiconductor layer penetrating wiring416connected with the buried wiring layer421through the semiconductor layer412is formed. The semiconductor layer and insulation layer penetrating wiring417which is connected with the support substrate penetrating wiring431through the semiconductor layer412and the interlayer insulation layer420is formed. The connection wiring418for connecting the semiconductor layer penetrating wiring416and the semiconductor layer and insulation layer penetrating wiring417is formed. Thereafter, the surface insulation film419which becomes a protection film is formed.

Next, as shown inFIG. 51A, the support substrate430is thinned from the opposite side of the bonded surface, for example, by mechanical grinding or the like until the support substrate wiring431is exposed, and the support substrate wiring431is made a support substrate penetrating wiring which passes through the support substrate430.

Next, as shown inFIG. 51B, the bumps432projecting from the front face of the support substrate430are formed on the front face of the support substrate penetrating wiring431, for example, by a metal plating process or the like. In the manner described above, a back-illuminated type CMOS solid-state imaging device (sensor chip)401baccording to this exemplified embodiment is formed.

The back-illuminated type CMOS solid-state imaging device (sensor chip)401bformed as mentioned above is mounted by flip chip on the interposer403through bumps432by facing the light receiving surface side upward. The signal processing chip402is similarly mounted by flip chip. Then, the back-illuminated type CMOS solid-state imaging device (sensor chip)401band the signal processing chip402are connected through the wiring formed in the interposer403. In the manner described above, it is possible to manufacture an image sensor installing a back-illuminated type CMOS solid-state imaging device according to this exemplified embodiment.

In this exemplified embodiment, the buried wiring formed on the semiconductor substrate and the penetration electrode in the support substrate are not directly connected, but the penetration electrode and the buried wiring are connected by wiring after thinning the rear face of the semiconductor substrate. In this method, it is connected with the signal process device by micro bumps formed on the rear face of the support substrate, so that it is not necessary to carry out wire bonding, and it is possible to make the size small when it is made in one chip.

As described above, according to a manufacturing method of a back-illuminated type CMOS solid-state imaging device according to this exemplified embodiment, the semiconductor substrate is thinned after securing the strength by bonding the support substrate, and also, the penetrating wiring is formed after thinning the support substrate, so that it is possible to conveniently and easily manufacture a back-illuminated type CMOS solid-state imaging device having a constitution that the electrode is taken out from the surface on the opposite side of the illumination surface.

As described above, in the semiconductor image sensor module (that is, CMOS image sensor incorporating the CMOS solid-state imaging device)401according to the seventeenth exemplified embodiment, it is possible to input the signal outputted from the pixel to the signal process device directly through micro bumps for each pixel unit or unit of a plurality of pixels. Thereby, it is possible to provide a high functional device that is fast in the signal process speed between the devices and that shows high performance and in which the image sensor and the signal process device are made in one chip. Also, the aperture ratio of the photodiode is improved, the chip utilization is improved, and simultaneous shuttering of all the pixels can be realized. Also, because it is not necessary to be connected with the chip or the wafer by wire bonding, it is possible to reduce the chip size, the yield of the wafer rises, and it is possible to lower the chip cost.

It is possible to form the penetrating wiring in the sixteenth and seventeenth exemplified embodiments described above by Cu, Al, W, WSi, Ti, TiN, silicide or a combination thereof.

The present invention explained usingFIG. 42andFIG. 48is not limited by the explanation of the aforesaid sixteenth and seventeenth exemplified embodiments. For example, in the aforesaid exemplified embodiments, an SOI substrate is used as a semiconductor substrate, but it is not limited to this, and it is also possible to carry out thinning from the surface of the opposite side of the photodiode or transistor forming surface using an ordinary semiconductor substrate. Also, the bumps formed to be projected from the support substrate can be formed on the whole chip area, and it is allowed to employ a constitution that, for example, independent bumps are formed for each pixel of the CMOS image sensor and are connected with the interposer or the like such that reading out becomes possible for each pixel. In addition, various changes are possible without departing from the scope of the present invention.

The semiconductor image sensor module according to each of the first to seventeenth exemplified embodiments mentioned above is applied to a camera module used, for example, in a digital still camera, a video camera, a mobile phone with a camera or the like. Further, it is applied to an electronic instrument module used in an electronic device or the like.

The above-mentioned semiconductor image sensor has been configured to include a back-illuminated type CMOS image sensor, however, it is also possible otherwise to employ a constitution including a front-illuminated type CMOS image sensor ofFIG. 27.

DESCRIPTION OF REFERENCE NUMERALS