Memory device, laminated semiconductor substrate and method of manufacturing the same

A memory device has a laminated chip package and a controller chip. In the laminated chip package, a plurality of memory chips are laminated. An interposed chip is laminated between the laminated chip package and the controller chip. The memory chips have a plurality of first wiring electrodes. The interposed chip has a plurality of second wiring electrodes. The second wiring electrodes are formed with a common arrangement pattern common with an arrangement pattern of a plurality of wiring electrodes for controller which are formed in the controller chip. The controller chip is laid on the interposed chip.

BACKGROUND

1. Field of the Invention

The present invention relates to a memory device using a laminated chip package, a laminated semiconductor substrate for manufacturing the memory device and a method of manufacturing the same.

2. Related Background Art

In recent years, electronic devices such as cellular phones and notebook personal computers need to be reduced in weight and improved in performance. With such needs, higher integration of electronic components used for the electronic devices has been required. Further, the higher integration of electronic components has been required also for increase in capacity of a semiconductor memory device.

Recently, System in Package (hereinafter referred to as a “SIP”) has attracted attention as a highly integrated electronic component. The SIP is a device created by stacking a plurality of LSIs and mounting them in one package, and a SIP using the three-dimensional mounting technique of laminating a plurality of semiconductor chips has received attention recently. Known as such a SIP is a package having a plurality of laminated semiconductor chips, that is, a laminated chip package. The laminated chip package has an advantage that speed up of operation of circuits and reduction in stray capacitance of wiring become possible because the length of the wiring can be reduced as well as an advantage of capability of high integration.

Known as the three-dimensional mounting techniques for manufacturing the laminated chip package include a wire bonding system and a through electrode system. The wire bonding system is a system of laminating a plurality of semiconductor chips on a substrate and connecting a plurality of electrodes formed on each of the semiconductor chips and external connecting terminals formed on the substrate by wire bonding. The through electrode system is a system of forming a plurality of through electrodes in each of the laminated semiconductor chips and realizing wiring between the respective semiconductor chips by the through electrodes.

The wire bonding system has a problem of a difficulty in reducing the spaces between the electrodes in a manner that the wires are not in contact with each other, a problem of a difficulty in speeding up the operation of circuits because of a high resistance value of wires, and a problem of a difficulty in reducing the thickness.

Though the above-described problems in the wire bonding system are solved in the through electrode system, the through electrode system has a problem of increased cost of the laminated chip package because many processes are required for forming the through electrodes in each of the semiconductor chips.

Conventionally known methods of manufacturing the laminated chip package are those disclosed, for example, in U.S. Pat. Nos. 5,953,588 (referred also to as patent document 1) and 7,127,807 B2 (referred also to as patent document 2), for example. In the patent document 1, the following manufacturing method is described. In this manufacturing method, first, a plurality of semiconductor chips cut out of a wafer are embedded in an embedding resin. Then, a plurality of leads to be connected to the semiconductor chips are formed to create a structure called Neo-Wafer. Subsequently, the Neo-Wafer is cut to create a plurality of structures called Neo-chips each including the semiconductor chip, the resin surrounding the semiconductor chip, and the plurality of leads. In this event, end faces of the plurality of leads connected to the semiconductor chips are exposed on side surfaces of the Neo-chips. Then, a plurality of kinds of Neo-chips are laminated to create a laminated body. In this laminated body, the end faces of the plurality of leads connected to the semiconductor chips at the respective layers are exposed on the same side surface of the laminated body.

Keith D. Gann, “Neo-Stacking Technology”, HDI Magazine, December, 1999 (referred also to as non-patent document 1) describes that a laminated body is formed by the same method as the manufacturing method described in Patent document 1 and wiring is formed on two side surfaces of the laminated body.

On the other hand, Patent document 2 discloses a multilayer module which is configured by laminating a plurality of active layers made by forming one or more electronic elements and a plurality of conductive traces on a flexible polymer substrate.

SUMMARY OF THE INVENTION

Conventionally, a memory device such as flash memory, DRAM, SRAM including a semiconductor storage element has been known as an electronic component using a laminated chip package. For example, in U.S. Pat. No. 7,557,439 B1 (referred also to as Patent Document 3), a memory device400that is an example of the conventional memory device is disclosed.FIG. 36is a perspective view illustrating the conventional memory device400. The memory device400has a laminated chip package401and a controller chip402. The laminated chip package401is bonded to the upper surface of the controller chip402, whereby the laminated chip package401and the controller chip402are integrated.

Further, not-illustrated electrode pads are formed on the uppermost surface of the laminated chip package401, and the electrode pads are connected to not-illustrated electrode pads of the controller chip402. InFIG. 36, the laminated chip package401is illustrated turned upside down.

In the laminated chip package401, a plurality of semiconductor chips399are laminated. The semiconductor chip399has many memory cells. A control IC controlling read/write data from/to the many memory cells is formed in the controller chip402.

On the other hand, in this kind of memory device, the storage capacity of a single memory device can be increased by using a laminated chip package403having an increased lamination number of semiconductor chips399as illustrated inFIG. 37. The laminated chip package403is disclosed, for example, in U.S. Pat. No. 7,745,259 B2 (referred also to as Patent Document 4).

The conventional memory device is manufactured using the laminated chip package and the controller chip, and the plurality of semiconductor chips399are laminated in the laminated chip package.

However, the semiconductor chip399and the controller chip402are manufactured in completely different processes and have different outside dimensions of the chips and different wiring structures necessary for connection of the electrode pads and so on. Therefore, for example, when the memory device400is manufactured, the laminated chip package401needs to be manufactured so that the controller chip402can be connected thereto.

Since the laminated chip package401is manufactured by being cut out of a laminated semiconductor substrate in which a plurality of semiconductor wafers are laminated, every semiconductor wafer being the material thereof needs to be manufactured so that the controller chip402can be connected thereto. For example, the arrangement of the electrode pads of the semiconductor wafer needs to be adapted to that of the electrode pads of the controller chip402.

Therefore, for example, when semiconductor wafers are manufactured so that the controller chip402can be connected thereto and a laminated chip package is manufactured using the semiconductor wafers, the laminated chip package can be connected as it is to the controller chip402. However, the laminated chip package could not be sometimes connected as it is to another controller chip having different wirings.

Accordingly, to enable to connect another controller chip, the manufacturing process of the laminated chip package needs to be changed. Therefore, it is difficult to simplify the manufacturing process.

In short, the prior art matches only with the case of manufacturing a specific memory device but can't match with efficient manufacture of various kinds of memory devices.

The present invention is made to solve the above problem, and it is an object to provide a memory device having a highly-versatile structure capable of manufacturing various kinds of memory devices more in a unit time, a laminated semiconductor substrate for manufacturing the memory device, and manufacturing methods of the same.

To solve the above problem, the present invention is a memory device including a laminated chip package laminated a plurality of memory chips each having a plurality of memory cells and a controller chip having a control circuit controlling read/write from/to the plurality of memory cells, the laminated chip package and the controller chip being laminated, each of the memory chips including: a device region in which the plurality of memory cells are formed; a resin insulating layer made of an insulating resin formed outside the device region; and a plurality of first wiring electrodes connected to the plurality of memory cells and extending from the device region to the top of the resin insulating layer; an interposed chip equal in outside dimension to the memory chip and having no semiconductor element is laminated between the laminated chip package and the controller chip, the interposed chip has a plurality of second wiring electrodes connected to the control circuit and formed in a common arrangement pattern in common with an arrangement pattern of a plurality of wiring electrodes for controller formed on the controller chip, wherein side surfaces of the plurality of memory chips and a side surface of the interposed chip form a common wiring side surface in which the surfaces are joined together without forming a step, and the first wiring electrodes are connected to the second wiring electrodes within the common wiring side surface, and the controller chip is laid on the interposed chip, and the plurality of wiring electrodes for controller are connected to the plurality of second wiring electrodes.

In this memory device, an interposed chip for connecting a controller chip is laminated. The interposed chip is formed as an interposer having no semiconductor element. Further, the interposed chip has a plurality of second wiring electrodes. The second wiring electrodes are formed in a common arrangement pattern in common with that of the wiring electrodes for controller, and therefore when the controller chip is laid on the interposed chip, all of the wiring electrodes for controller are vertically overlaid on the second wiring electrodes. Further, the end faces of the first wiring electrodes together with the end faces of the second wiring electrodes are formed in the common wiring side surface, so that even if the arrangement pattern of the first wiring electrodes is different from that of the wiring electrodes for controller, the first wiring electrodes are connected to the second wiring electrodes on the common wiring side surface and connected also to the wiring electrodes for controller.

Further, the present invention provides a memory device including a laminated chip package laminated a plurality of memory chips each having a plurality of memory cells and a controller chip having a control circuit controlling read/write from/to the plurality of memory cells, the laminated chip package and the controller chip being laminated, each of the memory chips including: a device region in which the plurality of memory cells are formed; a resin insulating layer made of an insulating resin formed outside the device region; and a plurality of wiring electrodes connected to the plurality of memory cells and extending from the device region to the top of the resin insulating layer; side surfaces of the plurality of memory chips form a common wiring side surface in which the surfaces are joined together without forming a step, and the wiring electrodes are connected within the common wiring side surface, where the memory chip laminated on a side closest to the controller chip among the plurality of memory chips is an interposed memory chip, only the plurality of wiring electrodes of the interposed memory chip are connected to the control circuit and formed in a common arrangement pattern in common with an arrangement pattern of a plurality of wiring electrodes for controller formed on the controller chip, and the controller chip is laid on the interposed memory chip, and the plurality of wiring electrodes for controller are connected to the wiring electrodes of the interposed memory chip.

In the case of this memory device, since one of the plurality of memory chips is the interposed memory chip, the interposed chip as the interposer having no semiconductor element becomes unnecessary.

It is preferable that the above-described memory device further including a plurality of connection electrodes formed on the common wiring side surface along a laminated direction in which the memory chips are laminated, a plurality of first wiring end faces being respective end faces of the first wiring electrodes and a plurality of second wiring end faces being respective end faces of the seconds wiring electrodes are formed on the common wiring side surface, and the first wiring end faces and the second wiring end faces are connected by the respective connection electrodes.

In this memory device, the first wiring electrodes and the second wiring electrodes are connected via the connection electrodes, and the connection electrodes are formed on the common wiring side surface and thus can be formed in a flat shape without forming a step.

Further, in the above-described memory device, it is possible that the interposed chip includes a semiconductor region equal in size to the device region, and a resin insulating layer made of an insulating resin formed outside the semiconductor region, and the second wiring electrodes extend from the semiconductor region to the top of the resin insulating layer.

Further, in case of the above-described memory device, it is preferable that the plurality of first wiring electrodes and the plurality of second wiring electrodes are formed such that the number and the arrangement interval of the plurality of first wiring electrodes are equal to the number and the arrangement interval of the plurality of second wiring electrodes.

Further, in case of the above-described memory device, it is possible that a plurality of rear wiring electrodes connected to the respective connection electrodes are formed on a rear surface side of the laminated chip package.

Further, in case of the above-described memory device, it is preferable that the interposed chip has an outside dimension larger than the outside dimension of the controller chip, and the plurality of second wiring electrodes have corresponding electrode pads corresponding to electrode pads of the plurality of wiring electrodes for controller.

Further, in case of the above-described memory device, it is preferable that the resin insulating layer has a double-layer structure in which an upper insulating layer is laid on a lower insulating layer, and the lower insulating layer is formed using a low-viscosity resin lower in viscosity than an upper resin forming the upper insulating layer.

Further, it is preferable that the memory chip further includes a surface insulating layer formed to cover the plurality of memory cell and constituting a surface layer of the memory chip, and the first wiring electrode is formed in a protruding shape rising above a surface of the surface insulating layer.

Further, the present invention provides a laminated semiconductor substrate in which a second semiconductor substrate is laminated on a laminated substrate laminated a plurality of first semiconductor substrates, the first semiconductor substrate having a plurality of first scribe groove parts formed along scribe lines and a plurality of memory cells formed in a device region in contact with the first scribed groove part, the first semiconductor substrate including: a first in-groove insulating layer formed inside the first scribe groove part; and a plurality of first wiring electrodes connected to the memory cells and extending from the device region to the top of the first in-groove insulating layer, the second semiconductor substrate having a plurality of second scribe groove parts arranged at positions corresponding to the first scribe groove parts, the second semiconductor substrate including: a semiconductor region in contact with the second scribed groove part and equal in size to the device region; and a second in-groove insulating layer formed inside the second scribe groove part; and a plurality of second wiring electrodes extending from the semiconductor region to the top of the second in-groove insulating layer and formed in a common arrangement pattern in common with an arrangement pattern of a plurality of wiring electrodes for controller formed on the controller chip having a control circuit controlling read/write from/to the plurality of memory cells.

Further, in case of the above-described laminated semiconductor substrate, it is possible that the second semiconductor substrate is formed as an interposed substrate having no semiconductor element formed in the semiconductor region.

Further, in case of the above-described laminated semiconductor substrate, it is also possible that the second semiconductor substrate is formed as a memory substrate having a plurality of memory cells formed in the semiconductor region.

Further, in case of the above-described laminated semiconductor substrate, it is preferable that the plurality of first wiring electrodes and the plurality of second wiring electrodes are formed such that the number and the arrangement interval of the plurality of first wiring electrodes are equal to the number and the arrangement interval of the plurality of second wiring electrodes.

Further, in case of the above-described laminated semiconductor substrate, it is preferable that the plurality of second wiring electrodes have corresponding electrode pads corresponding to electrode pads of the plurality of wiring electrodes for controller.

In case of the above-described laminated semiconductor substrate, it is preferable that the first scribe-groove parts and the second scribe-groove parts have a wide-port structure in which a wide width part wider in width than a groove lower part including a bottom part is formed at an inlet port thereof.

In case of the above-described laminated semiconductor substrate, it is preferable that the laminated substrate is composed by laminating one or two or more unit laminated substrates in each of which four the first semiconductor substrates are laminated.

Further, the present invention provides a method of manufacturing a laminated semiconductor substrate, including the following steps (1) to (4):

(1) a groove part forming step of forming, in each of a plurality of first unprocessed substrates having a plurality of memory cells formed therein, a plurality of first scribe groove parts along scribe lines in a device surface where the plurality of memory cells are formed, and forming, in a single surface of a second unprocessed substrate, a plurality of second scribe groove parts arranged at positions corresponding to the first scribe groove parts;

(2) an insulating layer forming step of forming, in each of the plurality of first unprocessed substrates, a first in-groove insulating layer inside the first scribe groove part by applying an insulating resin to the device surface, and forming, in the second unprocessed substrate, a second in-groove insulating layer inside the second scribe groove part by applying an insulating resin to a groove forming surface where the second scribe groove parts are formed;

(3) a wiring electrode forming step of forming, in the device surface in each of the plurality of first unprocessed substrates, a plurality of first wiring electrodes connected to the plurality of memory cells and extending from a device region in contact with at least one of the plurality of first scribe groove parts to the inside of the first scribe groove part, and forming, in the groove forming surface in the second unprocessed substrate, a plurality of second wiring electrodes extending from a semiconductor region in contact with at least one of the plurality of second scribe groove parts to the inside of the second scribe groove part in a common arrangement pattern in common with an arrangement pattern of a plurality of wiring electrodes for controller formed on a controller chip having a control circuit controlling read/write from/to the plurality of memory cells

(4) a laminating step of laminating the plurality of first unprocessed substrates and the second unprocessed substrate such that the positions of the first scribe groove parts and the second scribe groove parts are aligned and the groove forming surface of the second unprocessed substrate is arranged on the outermost side.

In case of the above-described method of manufacturing, it is preferable that in the laminating step, a polishing step of polishing a rear surface side of the groove forming surface of the second unprocessed substrate to reduce the thickness of the second unprocessed substrate is performed before the plurality of first unprocessed substrates and the second unprocessed substrate are laminated, and the plurality of first unprocessed substrates are laminated on the rear surface side of the groove forming surface after the polishing step is performed.

Further, in the above-described method of manufacturing, it is preferable that in the wiring electrode forming step, when the plurality of second wiring electrodes are formed, corresponding electrode pads corresponding to electrode pads of the plurality of wiring electrodes for controller are formed.

Further, the present invention provides a method of manufacturing a memory device, the laminated semiconductor substrate manufactured by the above-described manufacturing method is cut along the second scribe groove parts to manufacture a laminated chip package, then the controller chip is laid on the groove forming surface side of the laminated chip package, and the wiring electrodes for controller of the controller chip are connected to the second wiring electrodes.

Further, it is preferable that the above-described manufacturing method further includes the following step (5).

(5) a connection electrode forming step of, when manufacturing the laminated chip package, making a resin insulating layer made of an insulating resin and end faces of the first wiring electrodes and the second wiring electrodes appear at a cut surface when the laminated semiconductor substrate is cut along the second scribe groove part, and forming connection electrodes connecting the end faces of the first wiring electrodes and the second wiring electrodes on the cut surface.

Further, it is preferable that the above-described manufacturing method further includes the following step (6).

(6) a rear surface wiring electrode forming step of forming a plurality of rear surface wiring electrodes respectively connected to the connection electrodes on a flat surface on a rear surface side of the laminated chip package.

The present invention will be more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus are not to be considered as limiting the present invention.

DETAILED DESCRIPTION OF THE EMBODIMENTS

In the following, embodiments of the present invention will be described with reference to the drawings. Note that the same components will be referred to with the same numerals or letters, while omitting their overlapping descriptions.

First Embodiment

(Structures of Memory Device100)

To begin with, the structure of a memory device100will be described with reference toFIG. 1toFIG. 7.FIG. 1is a perspective view illustrating the entire memory device100according to a first embodiment of the present invention.FIG. 2is a perspective view illustrating a laminated chip package90and an interposer51constituting the memory device100.FIG. 3is a sectional view taken along the line3-3inFIG. 1and a sectional view illustrating an electrode substrate130.FIG. 4is a bottom view of the memory device100.FIG. 5is a perspective view illustrating a memory chip50constituting the memory device100.FIG. 6is a perspective view illustrating the interposer51.FIG. 7is a perspective view of a controller chip95, seen from bottom surface side.

The memory device100has the laminated chip package90, the interposer51and the controller chip95. The memory device100is constituted by laying the interposer51between the laminated chip package90and the controller chip95. Besides, the laminated chip package90is constituted by laying eight memory chips50. As illustrated inFIG. 2, in the laminated chip package90, the interposer51is laid on a controller side (uppermost surface, inFIG. 2), which is closest to the controller chip95, of eight memory chips50. In the memory device100, nine semiconductor chips are laid in all except the controller chip95.

As illustrated inFIG. 4, a plurality of rear wiring electrodes65are formed at a bottom surface of the laminated chip package90(the memory device100). Each of the rear wiring electrodes65is formed at a position adapted to a wiring131of the electrode substrate130. On the electrode substrate130, wirings131are formed. As illustrated inFIG. 3, the rear wiring electrodes65are connected to the wirings131by solders122. As will be described later, the memory device100is incorporated in an SSD (Solid State Drive), in which case the memory device100is held on the electrode substrate130keeping the connection state by the rear wiring electrodes65and the wirings131.

The memory chip50is formed as a whole in a thin rectangular plate shape as illustrated inFIG. 5, and its four side surfaces are covered by a resin insulating layer24. This resin insulating layer24has a double-layer structure in which an upper insulating layer22ais laminated on a lower insulating layer23. Further, the upper insulating layer22ahas a larger depth than that of the lower insulating layer23at four side surfaces of the memory chip50.

The memory chip50has device regions10formed inside the resin insulating layer24. Many later-described memory cells41are formed in the device regions10.

Further, in the memory chip50, the flat surface on one side is the surface22cof a surface insulating layer22, and the plural three-dimensional wiring electrodes15rising above the surface22care formed. The wiring electrodes15correspond to first wiring electrode according to an embodiment of the present invention. Besides, end faces15cof the wiring electrodes15appear as projecting end faces at wiring side surfaces50A,50A. The end faces15ccorrespond to first wiring end faces. The end faces15care connected to later-described connection electrodes60.

Six wiring electrodes15are arranged along each of two long sides50aof the memory chip50at regular intervals. Twelve wiring electrodes15in total are formed. Each of the wiring electrodes15has an extended terminal part15aand an electrode pad15bwhich will be described later. In addition, to widen the device region10as much as possible, the length of the extended terminal part15a(the depth from the long side50a) is made short so that the electrode pad15bis close to the long side50a. The extended terminal part15aextends from the device region10to the top of resin insulating layer24.

Next, the interposer51will be described. The interposer51corresponds to an interposed chip according to an embodiment of the present invention. The interposer51is formed in a rectangular plate shape having the same size as the memory chip50. The interposer51is the same as memory chip50in that four side surfaces are covered with the resin insulating layer24and a flat surface of one side is the surface22cof the surface insulating layer22. But, the interposer51is different in that the semiconductor regions11are formed in place of the device regions10and a plurality of wiring electrodes35are formed in place of a plurality of wiring electrodes15.

The semiconductor regions11have the same size as the device regions10. However, in the semiconductor regions11, semiconductor elements such as a memory cell41, integrated circuit are not formed. Therefore, the interposer51does not have semiconductor elements.

Wiring electrodes35correspond to second wiring electrodes according to the embodiment of the present invention. Six wiring electrodes35are arranged along each long side51aat regular intervals as in the memory chip50. Further, the wiring electrode35has an extended terminal part35aand an electrode pad35bwhich will be described later. However, the length of the extended terminal part35ais longer than the length of the extended terminal part15aso that the electrode pad35bis far from the long side51a.

Assuming that the interval between the electrode pads in a direction crossing the long side is a cross interval and the interval between the electrode pads in a direction along the long side is a long side interval, the cross interval between the electrode pads35bis set to W35aand the long side interval is set to W35bon the interposer51as illustrated inFIG. 6. The cross interval W35ais different from the cross interval between the electrode pads15bon the memory chip50, but coincides with a cross interval W95abetween later-described wiring electrodes97on the controller chip95. Thus, the wiring electrodes35are formed in a common arrangement pattern in common with the arrangement pattern of the wiring electrodes97. Further, the electrode pad35bis formed at a position corresponding to an electrode pad97bof the wiring electrode97and thus has a constitution as a corresponding electrode pad. Note that the arrangement pattern will be described later in detail.

The end faces35cof the extended terminal parts35aappear as projecting end faces in the wiring side surface51A,51A. The end faces35ccorrespond to second wiring end faces. The end faces35care connected to the connection electrodes60.

The wiring side surfaces51A are joined to the above-described wiring side surfaces50A of the eight memory chips50without forming a step. The wiring side surfaces51A and the wiring side surfaces50A of the eight memory chips50form two common wiring side surfaces52. The common wiring side surfaces52are flat surfaces.

Next, the controller chip95will be described. The controller chip95is formed in a rectangular plate shape smaller in outside dimension than the memory chip50as illustrated inFIG. 1,FIG. 3, andFIG. 7.

In the controller chip95, a control IC is formed. The control IC is a control circuit according to the embodiment of the present invention which is an integrated circuit controlling read/write of data from/to many memory cells41formed in each memory chip50. In this embodiment, the memory device100is incorporated in an SSD (Solid State Drive). The control IC is disposed between a not-illustrated connection terminal of the SSD and the memory chips50and controls read/write of data in each of the memory chips50.

As illustrated inFIG. 1, the controller chip95has a plurality of external electrode pads96formed on a front surface95A (a surface opposite to the laminated chip package90). Further, as illustrated inFIG. 7, a plurality of wiring electrodes97are formed as wiring electrodes for controller on a bottom surface95B. The wiring electrodes97are connected to the control IC. The illustrated wiring electrode97does not have an extended terminal part like the extended terminal part15aon the bottom surface95B of the controller chip95but has only an electrode pad97b. Six wiring electrodes97(electrode pads97b) are arranged along each of long sides95aat regular intervals. Twelve wiring electrodes97in total are formed.

These twelve electrode pads97bhave an original arrangement pattern on the controller chip95, and this arrangement pattern coincides with the arrangement pattern of the wiring electrodes35. In other words, the cross interval W95aof the controller chip95coincides with the cross interval W35a, and the long side interval W95bcoincides with the long side interval W35b. Since the controller chip95and the above-described interposer51are equal in the number of electrode pads and the arrangement interval, the arrangement pattern of the electrode pads97bin the controller chip95coincide with the arrangement pattern of the electrode pads35bin the interposer51. Therefore, in the memory device100, all of the electrode pads97bare connected to the electrode pads35bby solders121.

Meanwhile, the memory device100has a plurality of connection electrodes60as illustrated inFIG. 1. The connection electrodes60are formed on the common wiring side surfaces52,52. Each of the connection electrodes60is connected to a plurality of end faces arranged on a straight line along the laminated direction (the direction in which the interposer51and the eight memory chips50are laminated) of the end faces15cand the end faces35c. Therefore, the end face35cof the interposer51is connected to the end faces15cof the eight memory chips50by each of the connection electrodes60. Further, the connection electrode60is connected also to the rear wiring electrode65. The memory device100is configured such that the memory chips50, the interposer51and the controller chip95are connected to the wiring electrodes131by the rear wiring electrodes65.

In the memory device100, connection between the interposer51and the eight memory chips50is established by the connection electrodes60. Further, the controller chip95is connected to the interposer51by the solders121.

The memory device100can realize devices with various storage capacities such as 64 GB (gigabyte), 128 GB, and 256 GB by varying the memory parts in the later-described semiconductor wafer1. Note that eight memory chips50are laminated in the memory device100. However, the number of the memory chips50which are laminated within the memory device100is not limited to eight.

In the memory device100having the above-described constitution, the laminated chip package90and interposer51are manufactured by using the later-described semiconductor wafer1and a semiconductor wafer5. A structure of the semiconductor wafer1and a structure of the semiconductor wafer5are as the following.

To begin with, the structure of a semiconductor wafer1and the structure of a semiconductor wafer5will be described with reference toFIG. 8toFIG. 11,FIG. 13toFIG. 14. Here,FIG. 8is a perspective view illustrating the entire the semiconductor wafer1and the semiconductor wafer5according to the embodiment of the present invention.FIG. 9is a plan view illustrating a device region10and a region surrounding it formed in the semiconductor wafer1.FIG. 10is a plan view illustrating the device region11and a region surrounding it formed in the semiconductor wafer5.FIG. 11is a sectional view taken along the line11-11inFIG. 9.FIG. 13is a perspective view illustrating a principal part of the semiconductor wafer1with a part thereof omitted.FIG. 14is a sectional view taken along the line14-14inFIG. 13. Note that inFIG. 8, device regions10, semiconductor regions11, groove parts20,21and so on are enlarged for convenience of illustration.

The semiconductor wafer1, the semiconductor wafer5are composed using a silicon wafer2. The semiconductor wafer1has, as illustrated inFIG. 8, scribe lines3A and3B formed on a device surface1aof the silicon wafer2(the rear surface side of the device surface1ais a rear surface1b). A plurality of each of the scribe lines3A and3B are formed on the device surface1aand formed on straight lines at predetermined intervals along certain directions, respectively. The scribe lines3A are orthogonal to the scribe lines3B. The semiconductor wafer5has also scribe lines3A and3B the same as the silicon wafer1.

The semiconductor wafer1corresponds to a first semiconductor substrate according to the embodiment of the present invention. The semiconductor wafer5corresponds to a second semiconductor substrate. The above-described memory chips50are formed by the semiconductor wafer1, the above-described interposer51is formed by the semiconductor wafer5.

The semiconductor wafer1further has groove parts20and21formed in the device surface1a. The groove parts20,21are formed along the scribe lines3A and3B. Since the groove parts20,21are formed along the scribe lines3A and3B, the groove parts20,21have a constitution as a scribe-groove part of the present invention. The groove parts20,21of the semiconductor wafer1have a first scribe-groove part according to the embodiment of the present invention. Besides, the groove parts20,21of the semiconductor wafer5have a second scribe-groove part according to the embodiment of the present invention. Note that a surface of the semiconductor wafer5corresponding to the device surface1ais also referred to as a groove forming surface.

In the semiconductor wafer1, the device region10is formed within a rectangular region surrounded by the adjacent groove parts20,20and groove parts21,21. The semiconductor wafer5is different in that the semiconductor regions11are formed in place of the device regions10, as compared with the semiconductor wafer1.

The groove part20has a groove lower part20aand a wide width part20band is formed in a direction almost orthogonal to the device surface1aas illustrated inFIG. 14in detail.

The groove lower part20ais a part including a bottom part20cof the groove part20and having a certain height from the bottom part20c(seeFIG. 20,FIG. 21about the bottom part20c). The groove lower part20ais a lower part of the groove part20which a resin relatively hardly enters, and has a width w1(about 60 μm to about 80 μm) and a depth d1(about 10 μm to about 40 μm) as illustrated inFIG. 20(A), (B). Inside of the groove lower part20a, a lower insulating layer23is formed as illustrated inFIG. 11,FIG. 14and so on.

The wide width part20bis a part arranged on the upper side of the groove lower part20ain the groove part20, which is a part including an inlet port20dof the groove part20and having a certain depth from the inlet port20d. The wide width part20bis formed wider than the groove lower part20aand is formed over the entire length direction of the inlet port20dof the groove part20. In other words, as illustrate inFIG. 20(A), (B), a width w2of the wide width part20bis larger than the width w1of the groove lower part20a(w2>w1). The width w2of the wide width part20bis about 80 μm to about 120 μm, and a depth d2of the wide width part20bis about 10 μm to about 40 μm. Further, an upper insulating layer22ais formed inside the wide width part20b.

The groove part21has a groove lower part21aand a wide width part21band is formed in a direction almost orthogonal to the device surface1a. The groove lower part21ais a part having a certain height from a bottom part similarly to the groove lower part20a, and has the same width and depth as those of the groove lower part20a. Inside the groove lower part21a, the lower insulating layer23is formed as in the groove lower part20a. The wide width part21bis a part arranged on the upper side of the groove lower part21a. The wide width part21bis formed wider than the groove lower part21aand has the width and the depth similar to those of the wide width part20b. The upper insulating layer22ais formed inside the wide width part21bas in the wide width part20b.

As described above, the groove parts20and21have a wide-port structure in which the wide width part20band the wide width part21bwider than the groove lower parts20aand21aare formed at the respective inlet ports. In addition, a resin insulating layer24having a double-layer structure in which the upper insulating layer22ais laminated on the lower insulating layer23is formed inside the groove parts20and21.

The semiconductor wafer1has a surface insulating layer22as illustrated in detail inFIG. 11. The semiconductor wafer5has the surface insulating layer22as the same with the semiconductor wafer1.

The surface insulting layer22is formed to cover the device region10, the semiconductor region11and thus the surface insulting layer22covers almost the whole device surface1aof the semiconductor wafer1, the whole groove forming surface of the semiconductor wafer5to constitute a surface layer of the semiconductor wafer1, the semiconductor wafer5. The surface insulating layer22has a larger thickness than that of a later-described protecting insulating layer31and has a surface22cformed flat. The surface insulating layer22is disposed at the outermost position of the semiconductor wafer1, the semiconductor wafer5except for parts where wiring electrodes15, wiring electrodes35are formed.

Further, the surface insulating layer22is structured integrally with an upper insulating layer22aformed inside the groove parts20and21, and is thus formed in one body without joints between the upper insulating layer22aand other parts. The surface insulating layer22is formed with a plurality of contact holes22b, and one wiring electrode15or one wiring electrode35is formed in each of the contact holes22b.

The surface insulating layer22can be formed using a resin such as an epoxy resin or a polyimide resin, or an insulating material made of silicon silicate glass (SOG) or the like. In this embodiment, a case using a resin for the surface insulating layer22is discussed. It is especially preferable to form the surface insulating layer22using a resin having a low thermal expansion coefficient. This ensures that when the semiconductor wafer1, the semiconductor wafer5are cut along the groove parts20and21by a dicing saw, the cutting can be easily performed.

The lower insulating layer23is formed also using a resin similarly to the surface insulating layer22. The lower insulating layer23, however, is formed using a low-viscosity resin having a lower viscosity than that of the resin forming the surface insulating layer22.

The semiconductor wafer1, the semiconductor wafer5have a silicon substrate30composed of the silicon wafer2, and upper parts thereof are the device regions10, the semiconductor region11. A plurality of connecting pads32are formed on the surface of the device region10, and a part other than the connecting pads32is covered with the protecting insulating layer31. The semiconductor region11is covered with the protecting insulating layer31. Connecting pads32are not formed in the semiconductor region11.

The protecting insulating layer31is disposed under the surface insulating layer22and formed to cover the device region10, the semiconductor region11. The protecting insulating layer31is made of silicon dioxide (SiO2) or the like, and has connecting holes31aformed at positions where the connecting pads32are to be formed. The connecting holes31aare formed to expose the connecting pads32so as to connect the later-described wiring electrodes15to the connecting pads32. The connecting pads32are connected to a memory cell41in the device region10(seeFIG. 12for details).

The device region10, the semiconductor region11are a rectangular region surrounded by the adjacent groove parts20,20and the groove parts21,21as illustrated in detail inFIG. 9,FIG. 10. A plurality of the device regions10, the semiconductor regions11are formed on the first surface1a, groove forming surface and each of them is a unit region divided from adjacent regions by the groove parts20and21.

Each of the device regions10has the memory part formed on the first surface1aby performing wafer process, and a plurality of wiring electrodes15are formed. Since a plurality of the memory cells41are formed in the memory part, the semiconductor wafer1has a constitution as a memory substrate. Note that the wafer process means a manufacturing process of forming a semiconductor element and an integrated circuit on the wafer such as the silicon wafer2or the like.

A semiconductor element such as a memory cell or the like is not formed on the groove forming surface side of the semiconductor regions11. The semiconductor wafer5is a semiconductor substrate for forming the interposer51. The semiconductor wafer5has a constitution as an interposed substrate. A plurality of the wiring electrodes35are formed in the semiconductor regions11.

Next, the wiring electrode15, the wiring electrode35will be described. The wiring electrode15is made of a conductive material such as Cu or the like. The wiring electrode15has an extended terminal part15aand a rectangular electrode pad15bhaving wider width than the extended terminal part15a, and the extended terminal part15aand the rectangular electrode pad15bhave, as a whole, a protruding structure rising above the surface22cof the surface insulating layer22into a three-dimensional shape. A width of the electrode pad15balong the surface22cis formed wider than a width of the extended terminal part15aalong the surface22c.

The wiring electrode15is illustrated in detail inFIG. 13and so on in addition toFIG. 11. An end face15gof the extended terminal part15aof the wiring electrode15is a projecting end face projecting outward from the surface22cof the surface insulating layer22. Further, the wiring electrode15has a cross side surface15d, a top end face15e, and an embedded part15f.

The cross side surface15dis a side surface part projecting outward from the surface22cof the surface insulating layer22and crossing with the surface22cto rise up from (almost intersecting to) the surface22c. The top end face15eis connected to the cross side surface15dand projects outward from the surface22c, and further has a rectangular part disposed in a direction along the surface22cand a band-shaped part extending from the rectangular part in a direction along the surface22ctoward the groove part20. The embedded part15fis a part embedded inward from the surface22cto connect to the connecting pad32.

The electrode pad15bis composed of the cross side surface15d, the top end face15e, and the embedded part15f, and the extended terminal part15ais composed of the cross side surface15dand the top end face15e.

The electrode pad15bis connected to the connecting pad32via the contact hole22band the connecting hole31awhich are arranged to be stacked one on the other, and has a depth reaching the connecting pad32. More specifically, the electrode pad15bhas a height (an expanded height) h15expanded from the top end face15eouter than the surface22cto the connecting pad32via the contact hole22band the connecting hole31a. The expanded height h15is larger than a height h32of the connecting pad32(h15>h32). For example, h15is about 2 to 6 μm, and h32is about 0.5 to 1 μm.

The wiring electrodes15are formed along adjacent groove parts20,20of the device region10. The six wiring electrodes15are positioned at identical interval along groove parts20,20. Besides, in the adjacent device region10, the wiring electrodes15are arranged so as to face each other.

Further, in the wiring electrodes15, one parts of the extended terminal parts15aextend from the device region10into the groove part20. More specifically, the extended terminal parts15aare formed such that their respective parts on their tip sides apart from the electrode pads15bbulge out from an edge part (the above-described inlet port20d) of the groove part20and stay inside the groove part20in the width direction. Further, the extended terminal parts15aare formed such that their respective parts extending out from the device region10are in a protruding shape rising above the surface22cof the surface insulating layer22.

Further, as illustrated inFIG. 13,FIG. 14, the extended terminal parts15abulge out from both sides in the width direction of the groove part20such that the end faces15gare opposed to each other with slight separation therebetween near the middle in the width direction of the groove part20.

Meanwhile, the wiring electrode35is also made of a conductive material such as Cu or the like. As illustrated inFIG. 10, the wiring electrode35has an extended terminal part35aand a rectangular electrode pad35b, and the extended terminal part35aand the electrode pad35bhave, as a whole, a protruding structure like the wiring electrode15. An end face of the extended terminal part35aof the wiring electrode35is a projecting end face projecting outward from the surface22c.

However, since a length of the extended terminal part35ais longer than a length of the extended terminal part15a, the electrode pad35bare arranged inside the semiconductor region11away from the groove part20. The electrode pads35bare arranged at a position which is near a center of the semiconductor region11. In the semiconductor wafer5, the electrode pads35bare arranged at a position which is near a center of the semiconductor region11, the twelve electrode pads35bare formed with a common arrangement pattern common with an electrode pads97bof the controller chip95.

The semiconductor wafer1, the semiconductor wafer5have the extended terminal parts15aand the extended terminal parts35a. Therefore, in the cut surfaces when the semiconductor wafer1, the semiconductor wafer5are cut along the groove parts20, the end faces15cand35cappear projecting outward from the surface22c.

In addition, the number of the wiring electrodes15formed on the semiconductor wafer1is equal to the number of the wiring electrodes35formed on the semiconductor wafer5. For example, as illustrated inFIG. 9andFIG. 10, twelve wiring electrodes15are formed in each device region10, whereas twelve wiring electrodes35are formed in each semiconductor region11. Further, the planer shapes (the shapes drawn on a plane) of the wiring electrodes15formed in the device region10are the same, and the planer shapes (the shapes drawn on a plane) of the wiring electrodes35formed in the device region11are the same. Furthermore, the long side interval between the electrode pads15bcoincides with the long side interval between the electrode pads35b.

However, the lengths of the extended terminal part15aand the extended terminal part35aare different, and the cross interval between the electrode pads15band the cross interval between the electrode pads35bare different. Accordingly, the arrangement pattern of the electrode pads15bon the semiconductor wafer1is different from the arrangement pattern of the electrode pads35bon the semiconductor wafer5. The arrangement pattern here is a pattern decided depending on the number and the arrangement interval of the electrode pads constituting the wiring electrodes and means the arrangement form of the electrode pads indicating how the electrode pads are arranged in the device region10or the semiconductor region11.

Meanwhile, in the memory part of the device region10, a number of memory cells41as the semiconductor devices are formed. The memory cell41has a structure as illustrated inFIG. 12.FIG. 12is a sectional view mainly illustrating memory cells41of two semiconductor wafers1.

To the memory cell41, the wiring electrodes15are connected via the connecting pads32. The memory cell41is formed on the surface of an N-type substrate71constituting the semiconductor wafer1. InFIG. 12, two memory cells41are laminated one on the other via an adhesive layer33A. The adhesive layer33A is formed by an adhesive used when the semiconductor wafers1are bonded together.

Each of the memory cells41constitutes a flash memory and is formed on a P-type well72which is formed on the surface of the N-type substrate71. The memory cell41has a source73A and a drain73B, insulating layers77, an insulating film81, a floating gate82, an insulating film83and a control gate84. The memory cell41further has a source electrode74, a drain electrode76and a gate electrode75.

Both of the source73A and the drain73B are N-type regions and connected with the source electrode74and the drain electrode76, respectively. The insulating layers77are formed with contact holes for connecting the connecting pads32to the source electrode74and the drain electrode76, respectively. The source electrode74, the gate electrode75, and the drain electrode76are connected to the source73A, the control gate84and the drain73B via the corresponding contact holes, respectively.

(Method of Manufacturing Semiconductor Wafer).

Subsequently, the method of manufacturing the semiconductor wafer1, the semiconductor wafer5having the above-described structure will be described with reference toFIG. 15toFIG. 26. Here,FIG. 15is a plan view illustrating the partially manufactured semiconductor wafer,FIG. 16is a plan view illustrating the semiconductor wafer subsequent to that inFIG. 15.FIG. 17toFIG. 19is a plan view illustrating the semiconductor wafer subsequent to that in the order.FIG. 20is a sectional view of the semiconductor wafer mainly illustrating the groove part, in which (A) shows a state in which a first groove part forming step has been executed, and (B) shows a state in which a second groove part forming step has been executed.FIG. 21is a sectional view of the semiconductor wafer subsequent to that inFIG. 20, in which (A) shows a state in which the lower insulating layer has been formed and (B) shows a state in which the upper insulating layer and the surface insulating layer have been formed.FIG. 22toFIG. 26is a sectional view taken along the line22-22, the line23-23, the line24-24, the line25-25, the line26-26inFIG. 15toFIG. 19, respectively. Note that hatching is given to the surface insulating layer22inFIG. 18andFIG. 19for convenience of illustration. Besides, since forming steps of semiconductor wafer1are about the same as forming steps of semiconductor wafer5, an illustration of the semiconductor wafer5is omitted inFIG. 15toFIG. 26.

For manufacturing the semiconductor wafer1, to begin with, eight wafers (first unprocessed wafers) are prepared which has memory parts and a plurality of connecting pads32formed in the device regions10by performing wafer process. For manufacturing the semiconductor wafer5, one wafer (second unprocessed wafer) are prepared which semiconductor regions11are formed.

Then, as illustrated inFIG. 22, the protecting insulating layer31is formed on the device surface1afor the first unprocessed wafer, and then the connecting holes31aare formed at the locations in the protecting insulating layer31where the connecting pads32are to be formed. Besides, regarding the second unprocessed wafer, the protecting insulating layer31is formed on the groove forming surface.

Next, regarding the first unprocessed wafers and the second unprocessed wafer, the groove parts20and21are formed along the scribe lines3A and3B by performing a groove part forming step. The groove parts20and21are formed by the dicing saw. The groove parts20and21may be formed by etching such as the reactive ion etching or the like.

When the groove part forming step is performed, the following first groove part forming step and second groove part forming step are sequentially executed.

In the first groove part forming step, as illustrated inFIG. 15,FIG. 20(A), andFIG. 22, groove parts (first groove parts120) having a first width and a first depth are formed in the device surface1aalong the scribe lines3A and3B using a not-shown first blade (cutting blade). In the first groove part120, a part having a certain height from its bottom part will form the groove lower part20aor the groove lower part21aafterward. Here, the first width, which is the above-described width w1, is about 60 μm to about 80 μm, and the first depth, which is the depth d0illustrated inFIG. 20(A), is about 40 μm to about 80 μm.

Subsequently, the second groove part forming step is executed. In the second groove part forming step, as illustrated inFIG. 16,FIG. 20(B), andFIG. 23, second groove parts123are formed at the inlet ports of the first groove parts120along the entire length direction of the first groove parts120using a not-shown second blade. The second groove part123has a second width and a second depth. The second width, which is the above-described width w2, is about 80 μm to about 120 μm, and the second depth, which is the above-described depth d2, is about 10 μm to about 40 μm. The second width is larger than the first width, and the second depth d2is shallower than the first depth d0(d0>d2). By forming the second groove parts123, parts having a certain height from the bottom parts of the first groove parts120form the groove lower parts20aand the groove lower parts21a, and parts on the upper side of the groove lower parts20aand the groove lower parts21aform the wide width parts20band the wide width parts21b, respectively.

Then, an insulating layer forming step is executed. In the insulating layer forming step, prior to application of a resin for forming the surface insulating layer22(referred also to as a resin for surface layer), a low-viscosity resin having a viscosity lower than that of the resin for surface layer is applied to the device surface1a, the groove forming surface, regarding the eight first unprocessed wafers and the second unprocessed wafer. Then, the low-viscosity resin is uniformly spread over the device surface1a, the groove forming surface using a not-shown spin coater. The low-viscosity resin has a high flowability because it is purling due to its low viscosity. Therefore, the low-viscosity resin surely enters the inside of the groove lower parts20aand the groove lower parts21awhich a resin relatively hardly enters. In addition, due to the formation of the wide width parts20band21bon the upper side of the groove lower parts20aand the groove lower parts21arespectively, the low-viscosity resin more easily enter the inside of the groove lower parts20aand the groove lower parts21a.

Thus, as illustrated inFIG. 17,FIG. 21(A), andFIG. 24, the low-viscosity resin remaining inside the groove lower parts20aand the groove lower parts21aforms the lower insulating layer23. Note that the low-viscosity resin not only enters the inside of the groove parts20and21but also sometimes remains outside the groove parts20and21(for example, on the upper side of the protecting insulating layer31) though illustration of the low-viscosity resin remaining outside the groove parts20and21is omitted.

Next, regarding the eight first unprocessed wafers and the one second unprocessed wafer, a resin for surface layer is applied to the entire device surface1a, groove forming surface as illustrated inFIG. 18,FIG. 21(B), andFIG. 25. Then, the applied resin for surface layer is uniformly spread over the device surface1a, the groove forming surface using the not-shown spin coater. The resin for surface layer is, for example, epoxy resin, polyimide resin or the like and is higher in viscosity and lower in flowability than the low-viscosity resin. Therefore, the resin for surface layer hardly enters the inside of a groove part having a narrower width and a deeper depth. However, the wide width parts20band21bare formed at the inlet ports of the groove parts20and21. Thus, the resin for surface layer easily enters the inside of the groove parts20and21.

By the application of the low-viscosity resin prior to the application of the resin for surface layer, the lower insulating layer23has been formed in the groove lower parts20aand the groove lower parts21a. Therefore, when the resin for surface layer enters the inside of the groove parts20and21, by the resin for surface layer, an insulating layer different from the lower insulating layer23is formed inside the groove parts20and21. This insulating layer forms the upper insulating layer22a. Thus, the resin insulating layer24having the double-layer structure is formed inside the groove parts20and21. The resin insulating layer24of the semiconductor wafer1corresponds to a first in-groove insulating layer according to the embodiment of the present invention. The resin insulating layer24of the semiconductor wafer5corresponds to a second in-groove insulating layer according to the embodiment of the present invention,

Subsequently, regarding the eight first unprocessed wafers and the one second unprocessed wafer, each surface is polished to be planarized. Thus, the surface insulating layer22is formed. The parts of the applied resin for surface layer entered into the groove parts20and21form the upper insulating layer22a, so that the surface insulating layer22is formed integrally with the upper insulating layer22a.

Subsequently, as illustrated inFIG. 19,FIG. 26, regarding the eight first unprocessed wafers, the contact holes22bare formed in the surface insulating layer22to expose the connecting pads32. Thereafter, a wiring electrode forming step is performed to form the wiring electrodes15regarding the eight first unprocessed wafers. Regarding the second unprocessed wafer, the wiring electrodes35are formed. The wiring electrodes15are formed in a shape having the above-described protruding structure and including the extended terminal parts15a. The wiring electrodes35are formed in a shape having the above-described protruding structure and including the extended terminal parts35a. Besides, the electrode pads35bare formed with the above-described common arrangement pattern regarding the second unprocessed wafer. The wiring electrodes15,35can be formed, for example, in the procedure as follows.

First, a not-shown seed layer for plating is formed on the surface insulating layer22. Next, a frame (not shown) including groove portions is formed on the seed layer. The frame is formed, for example, by patterning a photoresist by the photolithography. Further, plating layers which will be parts of the wiring electrodes15and35are formed within the groove parts of the formed frame and on the seed layer. Subsequently, the frame is removed, and a part of the seed layer other than the part which exists under the plating layer is removed by etching. By the above processing, the wiring electrodes15and35can be formed of the plating layer and the seed layer under the plating layer.

Because, the wiring electrodes15and35are formed after the formation of the surface insulating layer22, the extended terminal parts15aand35aare formed in a manner that they are wholly disposed on the surface22cof the surface insulating layer22. The electrode pads15bare formed such that their peripheral parts are disposed upper side of the surface22cand their center parts are embedded inward from the surface22cto connect with the connecting pads32. The electrode pads35bare disposed upper side of the surface22c.

Through the above process, the semiconductor wafer1, the semiconductor wafer5having the above-described structure can be manufactured. In the semiconductor wafer1, the semiconductor wafer5, the groove parts20and21have the wide-port structure so that a liquid resin easily enters the inside of the groove parts20and21. Therefore, when forming an insulating layer inside the groove parts20and21using a liquid resin, the resin surely enters the inside of the groove parts20and21. This eliminates a situation that an unfilled part (air gap) that is not filled with the resin is formed inside the groove parts20and21. In short, the whole inside of the groove parts20and21is filled with the resin.

In the semiconductor wafer1, the semiconductor wafer5, the lower insulating layer23and the upper insulating layer22aare formed of the resin filled without forming such an air gap. More specifically, the semiconductor wafer1, the semiconductor wafer5have the groove parts20and21having a structure in which the inside of the groove parts20and21is filled with the insulating layer composed of a plurality of resins such as the low-viscosity resin and the resin for surface layer with no space (this structure is referred to as a “filled structure”).

Incidentally, when manufacturing the memory device100using the semiconductor wafer1, the semiconductor wafer5, it is necessary to laminate a plurality of semiconductor wafers1and the semiconductor wafer5(described later for detail). For this reason, the load caused by the semiconductor wafers1laminated at the upper part acts on the semiconductor wafer1laminated at the lower part, and the load also acts on the extended terminal parts15a,35a. Parts on the tip end side of the extended terminal parts15a,35aare extended from the device region10, semiconductor region11and located on the upper side of the groove part20. Therefore, when the load from above acts on the extended terminal parts15a,35a, the tip end side of the extended terminal parts15a,35aextending from the inlet port20dof the groove part20are likely to bow downward.

In the semiconductor wafer1, the semiconductor wafer5, however, the groove parts20and21have the filled structure, so that the lower insulating layer23and the upper insulating layer22anever move inside the groove parts20and21, and therefore the position of the surface22cof the surface insulating layer22never shifts. The surface insulating layer22, the upper insulating layer22a, and the lower insulating layer23are supporting members supporting the extended terminal parts15a,35a, and their positions never shift so that the extended terminal parts15a,35aare surely supported by the surface insulating layer22, the upper insulating layer22a, and the lower insulating layer23(seeFIG. 14). Accordingly, the extended terminal parts15a,35aare never deformed and can surely keep their original shapes even when the load from above acts thereon. Thus, by using the semiconductor wafer1, the semiconductor wafer5, the electrical connection of the memory device100can be surely established (described later for detail).

Further, in the groove parts20and21, the wide width parts20band21bare formed over the entire length direction of their inlet ports20d. Therefore, the resin easily enters the inside of the whole groove parts20and21. Thus, the extended terminal parts15a,35awhich are not deformed can be formed at any part of the groove parts20and21.

Since the groove lower parts20aand21aof the groove parts20and21are located closer to the bottom parts, a resin relatively hardly enters them as compared to other parts. Hence, in the semiconductor wafer1, the semiconductor wafer5, the lower insulating layer23is formed inside the groove lower parts20aand21ausing the low-viscosity resin. The low-viscosity resin has a high flowability and therefore surely enters even a part hard to enter. Accordingly, the low-viscosity resin is very suitable for making the groove parts20and21in the filled structure. As described above, by using the low-viscosity resin in the semiconductor wafer1, the semiconductor wafer5, the filled structure of the groove parts20and21is more surely formed.

On the other hand, the resin for surface layer is higher in viscosity and lower in flowability than the low-viscosity resin. Therefore, if the groove parts20and21are composed only of the groove lower parts20aand21aand not in the wide-port structure, the resin for surface layer stays near the inlet port of the groove part20(21) and hardly enters the inside thereof. Then, an air gap in which no resin exists appears inside the groove parts20and21to cause the surface insulating layer22on the upper side of the groove parts20and21to bend. Further, since the resin for surface layer has a low flowability, it is difficult to make the groove part20(21) in the filled structure even if the groove part20(21) is widened about the width. Accordingly, it is difficult to avoid the situation that the air gap appears inside the groove part20(21) as well as to avoid the deformation of the extended terminal parts15a,35aby using only the resin for surface layer.

Hence, when manufacturing the semiconductor wafer1, the semiconductor wafer5, the low-viscosity resin is applied to the device surface1a, groove forming surface prior to the application of the rein for surface layer. This makes it possible to fill the inside of the groove lower parts20aand21awhich a resin relatively hardly enters and the resin for surface layer is difficult to enter, with the low-viscosity resin before the inlet ports20dof the groove parts20and21are closed with the resin for surface layer. Thus, occurrence of the air gap is completely eliminated, so that the filled structure of the groove parts20and21can be more surely obtained.

Furthermore, the upper insulating layer22aand the surface insulating layer22can be formed using the same resin in the same one step, and therefore the semiconductor wafer1, the semiconductor wafer5can be easily manufactured.

(Method of Manufacturing Laminated Semiconductor Wafer and Memory Device)

By using the semiconductor wafers1and the semiconductor wafer5having the above-described structure, a laminated semiconductor wafer98and the memory device100can be manufactured. The laminated semiconductor wafer98corresponds to a laminated semiconductor substrate according to the embodiment of the present invention. In the laminated semiconductor wafer98, a laminated memory substrate97is laminated to the one semiconductor wafer5. The laminated memory substrate97corresponds to a laminated substrate according to the embodiment of the present invention. In the laminated memory substrate97, the eight semiconductor wafers1are laminated. By using the laminated semiconductor wafer98, the memory device100can be manufactured. The method of manufacturing the laminated semiconductor wafer98and the memory device100will be described usingFIG. 27toFIG. 30as follows.

Here,FIG. 27is a sectional view similar toFIG. 11, illustrating the partially manufactured laminated semiconductor wafer98and a base34.FIG. 28toFIG. 30is a plan view similar toFIG. 11, illustrating the process subsequent to that in the order.

By performing a laminating step after manufacturing the eight semiconductor wafers1and the semiconductor wafer5as mentioned above, the laminated semiconductor wafer98can be manufactured. The laminated semiconductor wafer98has a structure which the laminated memory substrate97is laminated to the one semiconductor wafer5.

The laminating step is performed by laying the eight semiconductor wafers1in order on the one semiconductor wafer5. First, as illustrated inFIG. 27, an insulating adhesive is applied on the groove forming surface of the semiconductor wafer5to fix it to the base34. InFIG. 27, the adhesive layer33made of the adhesive applied at this time is shown. The base34is a member for supporting the semiconductor wafer1, and a glass plate is used for the base34inFIG. 27.

Subsequently, the rear surface1bof the semiconductor wafer5is polished until the groove parts20and21appear so that the thickness of the semiconductor wafer5is decreased as illustrated inFIG. 27.

Next, the semiconductor wafer1is bonded to the rear surface1bside of the semiconductor wafer5as illustrated inFIG. 28using an adhesive. In this event, position adjustment of the semiconductor wafer5and the semiconductor wafer1is performed such that the positions of the groove parts20and21of both of them coincide with each other. Then, the rear surface1bof the semiconductor wafer1is polished until the groove parts20and21appear.

Subsequently, as illustrated inFIG. 29, regarding other semiconductor wafer1, a process of bonding it to the rear surface1bside of the semiconductor wafer1which already laminated and polishing it (a bonding and polishing process) is performed.

When such a bonding and polishing process is performed regarding the eight semiconductor wafers1in total, the laminated semiconductor wafer98can be manufactured, as illustrated inFIG. 30. In the laminated semiconductor wafer98, a part which the eight semiconductor wafers1are laminated is the laminated memory substrate.

Since the laminated semiconductor wafer98is manufactured by using the semiconductor wafers1and semiconductor wafer5, the laminated semiconductor wafer98has the same structure as the above-described semiconductor wafer1and the semiconductor wafer5.

In the above description, the laminated semiconductor wafer98is manufactured by sequentially laminating the eight semiconductor wafers1one by one on the semiconductor wafer5. However, the laminated semiconductor wafer98may be manufactured by manufacturing the semiconductor wafer5reduced in thickness by polishing the rear surface1b, and then laminating the laminated memory substrate97on the semiconductor wafer5. In this case, the laminated memory substrate97can be manufactured in advance by laminating the eight semiconductor wafers1in the above-described manner. As a matter of course, the laminated memory substrate97may be manufactured by laminating four semiconductor wafers1, or may be manufactured by laminating two semiconductor wafers1.

Namely, the number of semiconductor wafers1which will be laminated in the laminated semiconductor wafer98according to this embodiment can be relatively easily changed. Since many memory cells41are formed in the semiconductor wafer1, the storage capacity of the memory device which will be manufactured is also changed according to the change of the number of the semiconductor wafers1.

Furthermore, it is also adoptable to use the laminated memory substrate97in which the eight semiconductor wafers1are laminated as a unit laminated substrate, and laminate a plurality of the unit laminated substrates to form a laminated semiconductor wafer. For example, in the laminated semiconductor wafer in which two unit laminated substrates are laminated, 16 semiconductor wafers1are laminated. In three unit laminated substrates, 24 semiconductor wafers1are laminated. Accordingly, the number of the semiconductor wafers1which are laminated within the laminated semiconductor wafer is a multiple of 8.

Furthermore, it is also adoptable to use the laminated memory substrate in which the four semiconductor wafers1are laminated as a unit laminated substrate, and laminate a plurality of the unit laminated substrates to form a laminated semiconductor wafer. In this case, the number of the semiconductor wafers1which are laminated within the laminated semiconductor wafer is a multiple of 4.

When the laminated semiconductor wafer98is constituted using the above-described unit laminated substrate, the number of units according to the capacity of a memory required in the memory device can be easily found. Further, the capacity of the memory in the memory device can be easily varied only by varying the lamination number of unit laminated substrates. For example, when one unit is formed to provide 64 GB, memories of 128 GB and 256 GB can be realized only by varying the lamination number of units. Note that since all multiples of 8 are multiples of 4, it is preferable to laminate the four semiconductor wafers1to form the unit laminated substrate.

Then, when the memory device100is manufactured, the following process is performed continuously about the laminated semiconductor wafer98.

To begin with, the laminated semiconductor wafer98is cut along the groove parts20and21. Thus, the semiconductor wafer5and the eight semiconductor wafers1are divided into every the device region10, device region11laminated in the laminated direction. By this, device blocks in a block-like shape are manufactured.

In this device block, the one interposer51and the eight memory chips50are laminated. When the laminated semiconductor wafer98is manufactured, position adjustment of the semiconductor wafer5and the semiconductor wafers1is performed such that the positions of the groove parts20and21of both of them coincide with each other. Therefore, by cutting of the laminated semiconductor wafer98along the groove parts20and21, the laminated semiconductor wafer98is divided into every block surrounded by the adjacent groove parts20and21. The each block is the device block.

Then, as has been described, the semiconductor wafer5and the eight semiconductor wafers1are polished until the respective groove parts20,21appear. Inside each of the groove parts20,21, the lower insulating layer23and the upper insulating layer22aare formed. Therefore, in the device block, four side surfaces are covered by the lower insulating layer23and the upper insulating layer22a, namely, the resin insulating layer24in each of the interposer51and the eight memory chips50.

Further, when the laminated semiconductor wafer98is cut along the groove parts20,21, the semiconductor wafer5and the eight semiconductor wafers1are cut together, and therefore four flat cut surfaces appear. In addition, since the wiring electrodes15and the wiring electrodes35are extended to the top of the resin insulating layer24, the end faces15c,35cof the wiring electrodes15and the wiring electrodes35appear at the cut surfaces. A pair of opposite cut surfaces of the four cut surfaces are the above-described common wiring side surfaces52,52. The end faces15c,35care arranged on straight lines along the laminated direction on the common wiring side surfaces52.

Accordingly, the wiring electrodes15on each of the semiconductor wafers1can be electrically connected to the wiring electrodes35on the semiconductor wafer5by forming the band-shape connection electrodes60along the laminated direction on the common wiring side surfaces52as illustrated inFIG. 2.

Thereafter, when the rear surface wiring electrodes65are formed on the bottom surface of the device block, namely, the rear surface side of the memory chip50laminated on the lowermost side, the laminated chip package90on which the interposer51is laminated can be manufactured.

Further, the controller chip95is laid on the interposer51. In this case, the electrode pads97bare formed on the bottom surface95B of the controller chip95. Therefore, the bottom surface95B is directed toward the interposer51side, and the electrode pads97bare then connected to the electrode pads35bof the interposer51by the solders121. Thus, the memory device100can be manufactured.

(Operation and Effect of Laminated Semiconductor Wafer98and Memory Device100)

As described above, the memory device100can be manufactured by laying the controller chip95on the interposer51and connecting the electrode pads97bof the controller chip95to the electrode pads35bof the interposer51. The eight memory chips50are laminated in the laminated chip package90, and each of the memory chips50and the controller chip95are manufactured by completely different processes. Therefore, the memory chip50and the controller chip95are different in outside dimension and also different in the arrangement pattern of electrode pads necessary for connection with the external part.

Therefore, when the interposer51is not laminated on the laminated chip package90, wiring electrodes need to be additionally formed on either the memory chip50or the controller chip95so that the arrangement pattern of the memory chip50coincides with the arrangement pattern of the controller chip95.

When the electrode pad15bof the memory chip50is connected to the electrode pad97bof the controller chip95by solder, it is necessary that the positions of both the electrode pads coincide and both the electrode pads are overlaid one on the other. However, if the arrangement patterns of the electrode pads are different, the positions of both the electrode pads are out of alignment. Therefore, only one of the plurality of electrode pads97b(for example, only one of twelve electrode pads97b) can be overlaid on the electrode pad15b, but all of the electrode pads97bcannot be overlaid on the electrode pads15b. Accordingly, electrode pads which cannot be connected to the electrode pads (referred also to as unconnectable electrode pads) emerge in the plurality of electrode pads97b, failing to complete the memory device.

Hence, in the memory device100, the interposer51is laminated between the controller chip95and the laminated chip package90outside the eight memory chips50. This interposer51, in which semiconductor elements such as memory cell or the like are not formed, has a plurality of wiring electrodes35, and the wiring electrodes35are formed in the arrangement pattern (the common arrangement pattern) in common with the arrangement pattern of the controller chip95. Therefore, when the controller chip95is laid on the interposer51, all of the electrode pads97bof the controller chip95can be arranged on the electrode pads35bof the interposer51, thereby eliminating emergence of the unconnectable electrode pads.

Accordingly, the solders121can be used to connect all of the electrode pads97bof the controller chip95to the electrode pads35bof the interposer51. Further, since the interposer51is larger in outside dimension than the controller chip95, the length of the extended terminal part35acan be adjusted within a wider range in the interposer51. If the controller chip95is larger in outside dimension than the interposer51, the cross interval between the electrodes pads97bmay exceed the cross interval between the electrode pads35bso that all of the electrode pads97bare not likely to be able to be connected to the electrode pads35b. However, in the memory device100, all of the electrode pads97bfall within the outer periphery of the interposer51to eliminate the possibility of the above-described situation.

As described above, since the interposer51for connecting the controller chip95is laminated in the memory device100, it is unnecessary to change the structure and the manufacturing process of the memory chip50so that the arrangement of the electrode pads15bis adapted to the electrode pads97b. Therefore, the memory device100has a highly-versatile structure capable of simplifying the manufacturing process. Further, for example, in the case where a controller chip having an arrangement pattern of the electrode pads different from that of the electrode pads97bis used, when the positions of the electrode pads are laterally changed along the long side direction, it is only necessary to manufacture the interposer in the arrangement pattern in common with the arrangement pattern of the electrode pads. In this case, only the structure and the manufacturing process of the interposer need to be changed, and the structure and the manufacturing process of the memory chip50do not need to be changed. The memory chip50can be manufactured in the same structure and the same manufacturing process as those before the change. Accordingly, a memory device has the structure like the memory device100and thereby enables simplification of the manufacturing processes of various kinds of memory devices. Therefore, the memory device100matches with efficient manufacture of various kinds of memory devices and is thus excellent in mass production.

On the other hand, the respective end faces35c,15cof the wiring electrodes35of the interposer51and the wiring electrodes15of the memory chips50appear at the common wiring side surfaces52and are connected via the connection electrodes60. Therefore, the electrode pads97bof the controller chip95are connected to the electrode pads35bof the interposer51, whereby the controller chip95is connected to each of the memory chips50via the connection electrodes60. The interposer51functions as an interface for connecting the controller chip95to each of the memory chips50. Accordingly, in the memory device100, read/write of data from/to the memory cells41of the memory chips50can be surely performed by control of the control IC of the controller chip95.

As described above, the memory device100can be manufactured by laying the various kinds of memory chips having different arrangement patterns of the wiring electrodes owing to lamination of the interposer51for connecting to the controller chip95, and is increased in versatility to be able to manufacture various kinds of memory devices. Further, by laying the controller chip95on the interposer51, the solders121can be used to connect the controller chip95, thus eliminating excessive load on the process for connecting the controller chip95. Accordingly, the memory device100can be simplified in manufacturing process and also reduced in manufacturing time.

Further, if the lamination number of the memory chips50is increased from eight so as to increase the storage capacity of the memory device100, the controller chip95can be connected to all of the memory chips50only by laminating the interposer51. Accordingly, the increase in storage capacity of the laminated chip package90never increases the load on the process for connecting the controller chip95.

Meanwhile, the memory device100is manufactured using the semiconductor wafer1and the semiconductor wafer5. The plurality of wiring electrodes15of the semiconductor wafer1and the plurality of wiring electrodes35of the semiconductor wafer5have the respective extended terminal parts15a,35a, and therefore the respective end faces15c,35cappear at the common wiring side surfaces52. In addition, since the wiring electrodes15and the wiring electrodes35are formed such that the number and the arrangement interval of the wiring electrodes15and the number and the arrangement interval of the wiring electrodes35are equal, the end faces15c,35cappear arranged in straight lines along the laminated direction. Accordingly, the interposer51can be connected to the eight memory chips50by forming the connection electrodes60in a band-shape along the laminated direction on the common wiring side surfaces52, thereby simplifying the process required for connection of the interposer51.

Further, the rear wiring electrodes65are formed in the rear surface side of the laminated chip package90, the rear wiring electrodes65are connected to the connection electrodes60. Therefore, the eight memory chips50and the controller chip95are able to connect to the electrode substrate130by the rear wiring electrodes65.

The laminated semiconductor wafer98for manufacturing the memory device100can be manufactured by laminating the semiconductor wafers1on the semiconductor wafer5. By manufacturing the laminated memory substrate97in advance by laminating only the semiconductor wafers1, the laminated semiconductor wafer98can be obtained by laminating the laminated memory substrate97on the semiconductor wafer5. Accordingly, if a large variety of laminated memory substrates97different in the lamination number of the semiconductor wafers1are manufactured in advance for manufacturing a laminated semiconductor wafer98, a large variety of laminated semiconductor wafers98can be efficiently manufactured. Since the laminated semiconductor wafer98can be changed in the number of the memory cells41included therein by changing the lamination number of the semiconductor wafers1, the laminated semiconductor wafer98is very preferable in manufacturing a large variety of memory devices100different in storage capacity.

Meanwhile, when cutting the laminated semiconductor wafer98along the groove parts20,21, the groove parts20,21are cut along cut lines CL illustrated inFIG. 14. Then, the extended terminal parts15a(also the extended terminal parts35a) are cut along the cut lines CL. Further, as described above, the resin insulating layer24has been formed inside the groove parts20and21in each semiconductor wafer1, semiconductor wafer5. Therefore, the section of the insulating layer of the double-layer structure (the section of the insulating layer is referred also to as an “insulating section”) appears in a cut surface when the laminated semiconductor wafer98is cut along the groove parts20and21. The insulating section is in the double-layer structure in which an insulating section22dthat is the section of the upper insulating layer22ais laminated on an insulating section23cthat is the section of the lower insulating layer23.

Further, the wide width parts20band21bare formed wider than the groove lower parts20aand21ain each semiconductor wafer1, semiconductor wafer5. Therefore, the upper insulating layer22ahas a depth larger than that of the lower insulating layer23at four side surfaces of the device block. This depth means a distance d11between the insulating section22dand the inner side surface of the wide width part20b(21b) and a distance d12between the insulating section23cand the inner side surface of the groove lower part20a(21a) in the device block (also in the memory device100, the memory chip50and the interposer51) as illustrated inFIG. 14. The distance d11is larger than the distance d12and therefore d11>d12.

By the way, the memory device100is manufactured by forming the connection electrodes60on the common wiring side surface52. The end faces15cand35cconnected by the connection electrodes60are formed in a manner to project upward from the surface22c.

At the time of forming the connection electrodes60, the mask pattern for forming the connection electrodes60needs to be accurately placed, but the memory device100is able to be manufactured even if the position adjustment of the mask pattern is roughly performed. Even with the rough position adjustment, the connection electrodes60connecting the vertically arranged plural end faces15care able to be formed.

More specifically, in the memory device100, the alignment does not need to be performed with high accuracy when forming the connection electrodes60. Therefore, the process after the device block in the rectangular parallelepiped shape is obtained are able to be simplified, thereby simplifying the whole manufacturing process of the memory device100. Accordingly, the manufacturing time of the memory device100is able to be reduced. This can increase the number of memory device100manufacturable in a unit time, resulting in a reduced manufacturing cost of the memory device100.

The reason why the alignment does not need to be performed with high accuracy in case of forming the connection electrodes60is given as follows.

First of all, the device block has four side surfaces composed of cut surfaces when the laminated semiconductor wafer98is cut. In one of the cut surfaces, the end faces15cand35cappear as end faces projecting similarly to the end faces15g(seeFIG. 13for details). This is because of the following reason. Note that the end face projecting is also referred to as a projecting end face in this embodiment.

The wiring electrodes15,35of each of the semiconductor wafers1, the semiconductor wafer5have the extended terminal parts15a, the extended terminal part35arespectively. The extended terminal parts15aand the extended terminal parts35aare extended inside the groove parts20. For this reason, when the laminated semiconductor wafer98is cut along the groove parts20,21, the extended terminal parts15aand the extended terminal parts35aare also cut. Further, the end faces15c,35cformed when the extended terminal parts15a, the extended terminal parts35aare cut appear at one of the cut surfaces.

On the other hand, the extended terminal parts15a,35aare formed in the protruding shape similarly to the electrode pads15b,35bhaving the expanded height h15. Therefore, the end faces15c,35cappear as projecting end faces projecting upward from the surface22c.

For the connecting pads32, a case where terminal parts extending to the inside of the groove part20are formed is discussed here (the terminal parts are referred to as virtual terminal parts). In this case, end faces of the virtual terminal parts will appear at the side surface of the device block.

However, the extended terminal parts15a,35ahave top end faces common with the electrode pads15band35bhaving the expanded height h15and are formed to be larger in thickness than the connecting pads32. For this reason, the end faces15c,35cwill appear having a larger size than the end faces of the above-described virtual terminal parts. In the device block, the end faces15c,35chaving such a large size appear arranged in the vertical direction, so that the end faces15care easily connected to each other and the end faces35care also easily connected to each other. It is only necessary for the connection electrodes60to connect the end faces15cor the end faces35c. Therefore, the position adjustment of the mask pattern may be roughly performed at the time when the connection electrodes60are formed. For this reason, in the device block, the alignment does not need to be performed with high accuracy in case of forming the connection electrodes60.

On the other hand, the large size of the end faces15c,35cmeans that the sectional areas of the wiring electrodes15,35have been expanded. Accordingly, the resistance values of the wiring electrodes15,35are able to be decreased. This causes the current flowing through the wiring electrodes15,35to easily flow, so that the power consumption of the memory device100is also able to be reduced.

Thus, the semiconductor wafer1, the semiconductor wafer5have the wiring electrodes15,35as described above, whereby the manufacturing process of the memory device100are able to be simplified to reduce the manufacturing time.

Further, because the semiconductor wafer1, the semiconductor wafer5have the extended terminal parts15a,35aextending inside of the groove parts20, the end faces15c,35care able to appear at the cut surfaces when the laminated semiconductor wafer98is cut along the groove parts20. In other words, by cutting the laminated semiconductor wafer98, in which the semiconductor wafers1and the semiconductor wafer5are laminated, along the groove parts20, the end faces15c,35care able to be obtained.

Therefore, in case of using the semiconductor wafer1and the semiconductor wafer5, it is unnecessary to separately provide another process in order to make the wirings connecting to the device regions10, semiconductor region11appear at the cut surfaces. If the wiring electrodes15,35do not have the extended terminal parts15a,35a, the wiring electrodes15,35are not able to be cut even by cutting the laminated semiconductor wafer along the groove parts20. Therefore, only by cutting the laminated semiconductor wafer along the groove parts, the wirings connecting to the device regions10are not able to be made to appear at the cut surfaces. Thus, in order to make such wirings appear at the cut surfaces, another process needs to be performed.

However, in the case of using the semiconductor wafer1and the semiconductor wafer5, the end faces of the wiring electrodes15,35are able to be made to appear at the cut surfaces when the laminated semiconductor wafer98is cut along the groove parts, and therefore it is unnecessary to separately perform a process for making the wirings appear at the cut surfaces. Consequently, the manufacturing process of the memory device100is able to be further simplified by using the semiconductor wafer1and the semiconductor wafer5.

Further, the wiring electrodes15,35are formed to rise above the surface insulating layer22. Therefore, when the end faces15c,35cappear at the cut surface, the end faces15clocated one above the other are arranged via the surface insulating layer22and the end faces35clocated one above the other are arranged via the surface insulating layer22. Accordingly, a situation that the memory chips located one on the other short-circuit is able to be prevented.

In addition, because the extended terminal parts15a,35ahave a narrow-width structure having narrower widths than those of the electrode pads15b,35b, many wiring electrodes15,35are able to be arranged in the device region10, the semiconductor region11. Accordingly, the wiring density of the wiring electrodes15,35are able to be increased in the semiconductor wafer1, the semiconductor wafer5. Furthermore, the memory parts of each device region10are formed on the same plane in the semiconductor wafer1, so that the alignment error is 0 (zero).

The above memory device100is manufactured by laminating the semiconductor wafers1and the semiconductor wafer5. Therefore, the wiring electrodes15,35of the each memory chip50, the interposer51are surely supported by the surface insulating layers22, the upper insulating layers22aand the lower insulating layers23, and are never deformed due to bending downward.

Because there is no deformation of the wiring electrodes15,35in the memory device100, the end faces15c,35cof the wiring electrodes15,35surely appear at determined positions having determined sizes in the each memory chip50, the interposer51. If the extended terminal parts15a,35aare deformed due to bending downward, their angles with respect to the wiring side surface50A,51A may change to cause an insufficient contact between the end faces15c,35cand the connection electrodes60. However, there is no such possibility in the memory device100, the memory chip50and the interposer51.

Accordingly, the end faces15cof the memory chip50and the end faces35cof the interposer51are able to be surely connected with each other by the connection electrodes60in the memory device100. Therefore, the memory device100has a very high reliability of electrical connection. By manufacturing the memory device100using the semiconductor wafer1and the semiconductor wafer5as describe above, the reliability of electrical connection of the memory device100is able to be enhanced.

Second Embodiment

FIG. 31is a sectional view, similar withFIG. 3, illustrating a memory device300and the electrode substrate130according to a second embodiment of the present invention. The memory device300is different in that it has a laminated chip package290in place of the laminated chip package90and that the interposer51is not laminated, as compared with the memory device100. The laminated chip package290is different in that a memory chip53is laminated in place of the one memory chip50among the eight memory chip50, as compared with the laminated chip package90. That is, in the laminated chip package290, the one memory chip53and the seven memory chips50are laminated.

The memory chip53is laminated on the uppermost surface closest to the interposer51of the seven memory chips50and corresponds to the interposed memory chip according to the embodiment of the present invention. The memory chip53is different in that twelve wiring electrodes25are formed in place of the twelve wiring electrodes15as compared with the memory chip50as illustrated inFIG. 34. In the case of the memory chip53, the device region10is formed as an interposed device region. Each of the twelve wiring electrodes25has an extended terminal part25aand an electrode pad25b. Further, an end face25cof the extended terminal part25aappears as a projecting end face at a wiring side surface53A similar to the wiring side surface50A. However, the arrangement pattern of the wiring electrodes25is different from the arrangement pattern of the wiring electrodes15. The arrangement pattern of the wiring electrodes25is the common arrangement pattern in common with the arrangement pattern of the wiring electrodes97in the controller chip95. The extended terminal part25ais longer than the extended terminal part15a, and the electrode pad25bis arranged inner than the electrode pad15b.

In addition, the memory chip53is manufactured by using a semiconductor wafer6insulated inFIG. 32. This semiconductor wafer6is different in that it has wiring electrodes25as compared with the semiconductor wafer1. The wiring electrodes25are formed with the common arrangement pattern in common with the arrangement pattern of the wiring electrodes97.

On the other hand, the interposer51for connecting to the controller chip95is laminated in the memory device100, but the interposer51is not laminated in the memory device300. However, in place of the interposer51, the memory chip53is laminated. In the memory chip53, the wiring electrodes25are formed in the common arrangement pattern. Only the memory chip53is formed in the common arrangement pattern. Therefore, when the controller chip95is laid on the laminated chip package290, the wiring electrode25and the wiring electrode97are arranged to be overlaid one on the other. Accordingly, all of the electrode pads97bof the controller chip95can be arranged on the electrode pads25bof the memory chip53, thus eliminating emergence of the unconnectable electrode pads.

Accordingly, all of the electrode pads97bof the controller chip95can be connected to the electrode pads25bof the memory chip53through use of the solders121. Since only the memory chip53is formed in the common arrangement pattern in the memory device300, it is only necessary to change the structure and the manufacturing process of only the memory chip53, and it is unnecessary to change the structure and the manufacturing process of the other seven memory chips. Therefore, the memory device300also has a highly-versatile structure capable of simplifying the manufacturing process.

Moreover in the memory device300, the interposer51is not laminated. Therefore, an outside dimension of the memory device300can be made small. Further, the number of semiconductor chips which are laminated within the memory device300is small, so that a time required for lamination of the semiconductor wafer is able to be reduced, many memory devices100is able to manufacture in a unit time. Further, since a material for plating or the like is able to be reduced, cost for manufacturing of the memory device300is able to be reduced.

In addition, the memory device300is able to be manufactured by using a laminated semiconductor wafer198illustrated inFIG. 33. This laminated semiconductor wafer198is different in that the semiconductor wafer6is laminated in place of the semiconductor wafer5and the number of semiconductor wafer1which are laminated is seven, as compared with the laminated semiconductor wafer98.

(Method of Manufacturing Laminated Semiconductor Wafer198and Memory Device300)

When the laminated semiconductor wafer198is manufactured, the semiconductor wafer6is used in place of the semiconductor wafer5. The rear surface1bof the semiconductor wafer6is polished so that the thickness of the semiconductor wafer6is decreased by a procedure similar to the procedure for manufacturing the laminated semiconductor wafer98. Next, the seven semiconductor wafers1are laid on the rear surface1bof the semiconductor wafer6by the procedure similar to the procedure for manufacturing the laminated semiconductor wafer98. Thus, the laminated semiconductor wafer198is able to be manufactured.

After that, the laminated semiconductor wafer198is cut along the groove parts20and21. Subsequently, forming of the connection electrodes60and a connection of the controller chip95are performed by the same procedure as the memory device100. By this, the memory device300is able to be manufactured.

Other Embodiments

A semiconductor wafer111will be described with reference toFIG. 35. In the above-described semiconductor wafer1, the semiconductor wafer5and the semiconductor wafer6, the groove parts20and21are formed. The semiconductor wafer111is different from the semiconductor wafer1, the semiconductor wafer5and the semiconductor wafer6in that groove parts21are not formed but only groove parts20are formed. Accordingly, the semiconductor wafer111is formed such that a plurality of groove parts20are arranged at regular intervals and the groove parts are formed in the shape of stripes not intersecting with each other. Further, the groove parts20may be formed along every other scribe line3A, they are not illustrated.

In the semiconductor wafer1, the semiconductor wafer5and the semiconductor wafer6, the device region10, the semiconductor region11are in contact with the four groove parts20and21, so that the device region10, the semiconductor region11are in contact with the groove parts20and21in the four directions, that is, upper, lower, right and left directions. Accordingly, as illustrated inFIG. 5,6,34, the memory chip50,53, the interposer51are covered by the resin insulating layer24at the four side surfaces.

In contrast, in the semiconductor wafer111, the device region10, the semiconductor region11are in contact with the groove parts20only in the two, that is, right and left directions. Accordingly, following memory chip or interposer are obtained by using a semiconductor wafer in which the groove parts are formed in the shape of stripes as in the semiconductor wafer111. This memory chip or the interposer has two sets of opposite side surfaces. But, only one set of side surfaces are covered by the insulating layer.

Though the wiring electrodes15, the wiring electrodes35have the protruding structure in the above embodiments, the present invention is also applicable to a laminated semiconductor substrate and memory device including wiring electrodes that do not have the protruding structure. Further, terminal parts in a structure across the groove part may be formed in adjacent two device regions10, semiconductor region11in place of the extended terminal parts15a. Furthermore, the scribe-groove part may not have the wide-port structure, unlike the groove part20,21.

This invention is not limited to the foregoing embodiments but various changes and modifications of its components may be made without departing from the scope of the present invention. Besides, it is clear that various embodiments and modified examples of the present invention can be carried out on the basis of the foregoing explanation. Therefore, the present invention can be carried out in modes other than the above-mentioned best modes within the scope equivalent to the following claims.