SOI transistors with improved source/drain structures with enhanced strain

A transistor structure with improved device performance, and a method for forming the same is provided. The transistor structure is an SOI (silicon-on-insulator) transistor. In one embodiment, a silicon layer over the oxide layer is a relatively uniform film and in another embodiment, the silicon layer over the oxide layer is a silicon fin. The transistor devices include source/drain structures formed of a strain material that extends through the silicon layer, through the oxide layer and into the underlying substrate which may be silicon. The source/drain structures also include portions that extend above the upper surface of the silicon layer thereby providing an increased volume of the strain layer to provide added carrier mobility and higher performance.

TECHNICAL FIELD

The disclosure relates to semiconductor devices and methods for manufacturing the same. More particularly, the disclosure relates to transistors such as SOI-MOSFET devices with improved device performance due to improved source/drain structures having enhanced strain.

BACKGROUND

Metal oxide semiconductor field effect transistor (MOSFET) devices fabricated on SOI (silicon on insulator) substrates offer advantages of low-voltage and high speed operation. SOI-MOSFETs have a comparatively simple construction and a smaller layout as compared with bulk silicon transistor devices. SOI transistors have therefore become increasingly popular in today's semiconductor manufacturing industry where there is a constant push to reduce the layout size of devices and increase device speed and performance.

SOI-MOSFET and other SOI transistor devices are formed on substructures that include an upper silicon layer formed over an oxide layer formed over a bulk substrate. To achieve better short channel effects, the silicon layer atop the oxide layer is formed to be very thin.

SOI-MOSFET devices, other MOSFET devices and other semiconductor device transistors benefit from strain enhancement in the source/drain regions. This is true for PMOS and NMOS technologies. The increased strain is known to improve device performance and device speed. Source/drain regions of transistors are generally formed in the substrate over which the transistor gate is formed and for SOI-MOSFET devices, the source/drain regions are formed in the upper silicon layer.

With the source/drain regions formed in the necessarily thin upper silicon layer, one shortcoming of SOI transistor devices is the inability to improve device performance by introducing strain materials in the source/drain regions.

DETAILED DESCRIPTION

The disclosure provides for forming transistor devices such as MOSFET's, on SOI substructures. The disclosure provides for forming strain regions of increased volume as part of the source/drain structures. An overview of the method used to form various transistors according to the disclosure, is provided inFIG. 1. Further details of the method and structures formed according to the methods are provided in conjunction with the subsequent figures.

FIG. 1is a flowchart describing a broad method for carrying out the formation of transistors on SOI substrates. At step100, an SOI substructure is provided. The SOI substructure is a substructure with silicon, or another suitable semiconductor material, formed over an oxide formed over a semiconductor or other bulk substrate. The semiconductor material may be silicon or other materials and may be in the form of a layer formed over the substrate or a fin formed and defined over the substrate. Step102provides for the formation of a gate structure. Step104provides for the formation of source/drain spacers along sidewalls of the gate structure and is an optional step. Step106provides for etching through the semiconductor material, the oxide and into the underlying substrate to form openings. Step108provides for a grading implant involving the introduction of dopant species into the substrate beneath the opening formed at step106. Ion implantation or other methods to introduce dopant impurities are used but step108is not used in all embodiments. The grading implant is technology specific with N-type dopants used for NMOS transistors and P-type dopants used for PMOS transistors. Step110provides for in-situ doped strained material growth to form a plug of strained material that fills the opening and extends above the upper surface of the semiconductor material. Step110is also technology specific with dedicated materials used for NMOS transistors and other materials used for PMOS transistors. Step112is a source/drain annealing process.

FIG. 2Ais a cross-sectional view showing substrate2. Substrate2is silicon in one embodiment and substrate2is formed of other suitable materials in other embodiments. Oxide layer4is formed over substrate2and semiconductor material6is formed over oxide layer4. Oxide layer4may be silicon dioxide or other suitable oxide materials. Various formation methods are used to form oxide layer4. Oxide layer4is often referred to as a buried oxide, BOX, because it is situated beneath semiconductor material6. In one embodiment, semiconductor material6is silicon. Semiconductor material6includes top surface8. In one embodiment, semiconductor material6is crystalline silicon and in other embodiments, semiconductor material6is polycrystalline or amorphous silicon. In other embodiments, semiconductor material6is other suitable semiconductor materials.

Gate structures10are formed over semiconductor material6and a gate oxide is present between gate structures10and semiconductor material6but not visible in the illustration ofFIGS. 2A-2C. Gate structures10include gate electrode12and spacers14. In one embodiment, gate structure10is a gate structure for an NMOS transistor and in another embodiment, gate structure10is a gate structure for a PMOS transistor. Gate electrode12is formed of doped or undoped polysilicon in some embodiments. In other embodiments, gate electrode12is formed of a material having a work function suitable and compatible with the type of transistor—NMOS or PMOS—being formed. Spacers14are formed alongside the sidewalls of gate electrode12and are formed of nitride, oxynitride, or other suitable spacer materials. Spacers14are formed by depositing a thick layer of the spacer material over a structure including over the gate electrodes, then carrying out an isotropic etch to produce spacers14, in some embodiments. In some embodiments, spacers14are not used.

Oxide layer4includes thickness16. In one embodiment, thickness16lies within the range of 10-30 nm but thickness16takes on other values in other embodiments. In one embodiment, semiconductor material6is a film or layer of substantially uniform thickness substantially covering oxide layer4. Semiconductor material6includes thickness18which is 5-20 nm according to one embodiment in which semiconductor material6is the film or layer of substantially uniform thickness. In other embodiments, thickness18of semiconductor material6takes on other values. According to other embodiments, semiconductor material6is a fin with a considerably greater thickness. A fin embodiment will be shown inFIGS. 4A and 4B. Conventional and other methods are available and various suitable processes are available to form the structure shown inFIG. 2A.

FIG. 2Bshows the structure ofFIG. 2Aafter openings26have been formed. Openings26extend through semiconductor material6, through oxide layer4and into substrate2. Openings26are formed to various depths. The overall depth of openings26depend upon the thickness of semiconductor material6and oxide layer4and the extent that openings26extend into substrate2. Depth34represents the depth of the recess formed extending into substrate2. In one embodiment, depth34is about 10-30 nanometers but depth34has other values in other embodiments. Various etching operations are used to form openings26in between and adjacent gate structures10. More particularly, various sequences of etching operations are used to etch through semiconductor material6, oxide layer4and into substrate2. In one embodiment, an etching operation that undercuts spacers14is used and openings26extend laterally to gate electrodes12and include portions beneath spacers14. Openings26include bottom surfaces28.

FIG. 2Balso shows grading dopant areas22. Arrows30indicate the introduction of dopant impurities into bottom surface28of substrate2to form grading dopant areas22and in one embodiment, arrows30indicate the introduction of dopant impurities into bottom surface28of substrate2via ion implantation. Grading dopant areas22include N-type dopant impurities when used in conjunction with NMOS transistors and P-type dopant impurities when used in conjunction with PMOS transistors. Various suitable N-type and P-type dopant impurities are used in various embodiments. One suitable P-type dopant impurity is boron and suitable N-type impurities include phosphorous and arsenic. Other dopant impurities are used in other embodiments. The introduction of grading dopant impurities is advantageously used to prevent junction leakage but is not used in some embodiments. In one embodiment, an ion implantation operation is used. In other embodiments, other methods for introducing dopant impurities into bottom surface28of substrate2, are used to form grading dopant areas22. In one embodiment, the dopant impurities are formed to a concentration of about 1e19 cm−3, but the concentration of grading dopant areas22varies from 1e18 to 5e19 cm−3in other embodiments. The grading implant operation, i.e. grading dopant areas22, are not used in some embodiments.

Openings26ofFIG. 2Bare each filled with a suitable strain material to produce the structure shown inFIG. 2C. Strained layers or materials are used in semiconductor devices because the biaxial tensile or compressive strain produced by the strain material alters the carrier mobilities in the layers, enabling the fabrication of high-speed devices, low-power devices, or both.

FIG. 2Cshows strain materials38formed within previous openings26and extending above top surface8of semiconductor material6. In one embodiment, top surfaces40of strain materials38are disposed above top surface8by about 20-30 nm but other dimensions are used in other embodiments. Strain materials38serve as source/drain regions in their associated transistors, i.e. in conjunction with the transistor gate10that is adjacent to strain material38. Strain materials38extend laterally to gate electrode12and under spacers14in various embodiments. Strain materials38are used with PMOS transistors and NMOS transistors and the materials used to form strain materials38are chosen in conjunction with the associated transistor type. When used in conjunction with PMOS transistors, strain material38is SiGe or other materials with similar lattices that are similar to that of SiGe. When used in conjunction with NMOS transistors, strain material38is SiC in one embodiment but other materials with lattice structures similar to SiC are used in other NMOS transistor embodiments.

In one embodiment, strain materials38are formed using selective epitaxial growth. Other formation methods are used in other embodiments. According to various embodiments for forming both NMOS and PMOS transistors, an in-situ doping operation is carried out in conjunction with the epitaxial formation process. When used in conjunction with NMOS transistors, strain materials38are doped with phosphorus or other suitable dopants used for NMOS transistors, and when used in conjunction with PMOS transistors, strain materials38are doped with boron or other suitable dopants used for PMOS transistors. Other dopant species are used in other embodiments. A source/drain annealing operation is then carried out to anneal the structures. Various types of annealing operations with various conditions, are used in various embodiments. Grading dopant areas22are disposed under respective bottom surfaces28of former openings26and also below strain materials38which serve as source/drain regions and fill former openings26. Graded dopant areas22do not overlap the strain materials38serving as source/drain regions. Interface29is the interface between the respective grading dopant areas22and the strain materials38serving as the source/drain regions and the common boundary at which the grading dopant areas22directly contact the strain materials38serving as the source/drain regions. As such, since grading dopant areas22are disclosed to be disposed below strain materials38which serve as source/drain regions.

The transistor embodiments illustrated inFIG. 2Cundergo various additional processing operations and are coupled to various other semiconductor devices and structures using suitable circuitry to form any of various integrated circuits and other types of semiconductor devices.

FIGS. 3A and 3Bare a top and cross-sectional view, respectively, of planar SOI-MOSFET transistor devices.FIG. 3Ais a top view showing three transistor gate structures10, each including gate electrode12and spacers14. Strain materials38are formed between the transistor structures as described above.

FIG. 3Bis substantially similar toFIG. 2Cand represents a planar SOI-MOSFET device but does not include grading dopant area22.

FIGS. 4A and 4Bshow an SOI FinFET structure according to the disclosure. The structure shown inFIG. 4Ais formed using the same sequence of processing operations described in conjunction withFIG. 2Aand covered in the flowchart ofFIG. 1. In the FinFET embodiment illustrated inFIGS. 4A and 4B, the semiconductor material formed over oxide layer4is formed as a fin device. Semiconductor fin48includes top surface50and side surfaces52. Semiconductor fin48is formed of silicon in one embodiment. Semiconductor fin48is formed of other suitable materials in other embodiments. Various patterning and etching operations are used to form semiconductor fin48.

Fin gate structure54is formed over semiconductor fin48including over top surface50and side surfaces52. In the embodiment ofFIG. 4B, fin gate structure54extends orthogonally with respect to semiconductor fin48and includes gate electrode56and spacers58, although spacers58are not used in some embodiments. The gate oxide present between gate electrode56and semiconductor fin48is not visible inFIGS. 4A and 4B. Various patterning and etching operations are used to form fin gate structure54that extends over semiconductor fin48.

In one embodiment,FIG. 4Bis a cross-section taken along the line bisecting semiconductor fin48ofFIG. 4A, and after spacers and strain materials are formed.

FIG. 4Bshows substrate2, oxide layer4, and semiconductor fin48with fin gate structure54formed over top surface50of semiconductor fin48. In the embodiment ofFIG. 4B, fin gate structure54includes gate electrode56and spacers58. Gate electrode56and spacers58are formed of the materials described in conjunction withFIGS. 2A-2C, in various embodiments. Strain materials60are formed as described in conjunction withFIGS. 2A-2Cand using materials described in conjunction withFIGS. 2A-2C. In particular, openings are formed adjacent fin gate structure54and extending through semiconductor fin48and oxide layer4and into substrate2. Although not illustrated inFIG. 4B, various SOI FinFET embodiments also include grading dopant areas beneath strain materials60. Strain materials60are formed as described above and extend into substrate2and encroach beneath spacers58, extending laterally to gate electrode56. Strain materials60include upper surfaces62disposed above top surface50of semiconductor fin48in the illustrated embodiment. Top surface62may be at other heights in other embodiments. Various source/drain annealing operations are used to anneal the structure ofFIG. 4B, including strain materials60which are doped with suitable dopant impurities as described in conjunction with strain materials38ofFIG. 2C.

According to one aspect, a semiconductor device is provided. The semiconductor device includes an SOI (silicon on insulator) transistor device comprising: a substructure including a silicon substrate, a buried oxide layer formed over the silicon substrate and a crystalline silicon material formed over the buried oxide layer; a gate structure formed over the crystalline silicon material; and source/drain structures disposed adjacent the gate structure, the source/drain structures formed of a strain material and disposed in an opening that extends through the crystalline silicon material and the buried oxide layer, and into the silicon substrate. The source/drain structures each have an upper portion extending above the crystalline silicon material

According to another aspect, a semiconductor device is provided. The semiconductor device includes an SOI (silicon on insulator) transistor device comprising: a substructure including a silicon substrate, a buried oxide layer disposed on the silicon substrate and a crystalline silicon material disposed on the buried oxide layer; a gate structure formed over the crystalline silicon material, the gate structure including a gate electrode and source/drain spacers along sidewalls of the gate electrode; source/drain structures disposed adjacent opposite sides of the gate electrode, the source/drain structures formed of a strain material filling an opening that extends through the crystalline silicon material and the buried oxide layer and into the silicon substrate, including beneath the source/drain spacers, the source/drain structures each having an upper portion disposed above an upper surface of the crystalline silicon material. Dopant impurity regions are disposed in the semiconductor substrate beneath each the source/drain structure.

According to another aspect, a method for forming a transistor on a silicon-on-insulator (SOI) substructure, is provided. The method comprises: providing a semiconductor substrate; forming an oxide layer over the semiconductor substrate; forming a crystalline silicon material over the oxide layer; forming a gate structure over the crystalline silicon material; creating openings extending through the oxide layer and the crystalline silicon material and extending into the semiconductor substrate, adjacent the gate structure; and filling the openings with a strain material, the strain material including a top surface above an upper surface of the crystalline silicon material.