Redundant clock transition tolerant latch circuit

Embodiments of a latch circuit and a method of operating a latch circuit are described. In one embodiment, a latch circuit includes an input terminal configured to receive an input data signal, a switching unit configured to control application of the input data signal, a first inverter circuit connected to the switching unit, where the first inverter circuit includes a first cross-coupled pair of inverters, and a second inverter circuit connected to the first inverter circuit through the switching unit. The second inverter circuit includes a second cross-coupled pair of inverters and two transistor devices. Each inverter of the second cross-coupled pair of inverters is connected to a voltage rail through a corresponding transistor device. Each of the two transistor devices is connected to a node that is between the switching unit and the first inverter circuit or the second inverter circuit. Other embodiments are also described.

This application claims priority from European Patent Application No. EP13191288, filed Nov. 1, 2013, which is incorporated herein by reference in its entirety.

Embodiments of the invention relate generally to electronic hardware and methods for operating electronic hardware, and, more particularly, to latch circuits and methods for operating latch circuits.

The power consumption of an electronic circuit is an important performance metric. For example, for low power embedded devices such as microcontrollers and smartcards, reducing the power consumption is important to the performance of the device. Dynamic power consumption caused by redundant clock transitions of digital devices can account for a significant portion of the overall power consumption of digital devices. Specifically, charging and discharging of internal nodes of a latch circuit in which the input data of the latch circuit is in the same state for consecutive clock cycles result in unnecessary power consumption. For example, dynamic power consumption caused by redundant clock transitions can account for around 50% of the power consumption of a latch circuit. The reduction in power consumption by redundant clock transitions can reduce the overall power consumption of a latch circuit and improve the power efficiency of the latch circuit. Therefore, it is desirable to reduce power consumption caused by redundant clock transition in a latch circuit.

Embodiments of a latch circuit and a method of operating a latch circuit are described. In one embodiment, a latch circuit includes an input terminal configured to receive an input data signal, a switching unit configured to control application of the input data signal, a first inverter circuit connected to the switching unit, where the first inverter circuit includes a first cross-coupled pair of inverters, and a second inverter circuit connected to the first inverter circuit through the switching unit. The second inverter circuit includes a second cross-coupled pair of inverters and two transistor devices. Each inverter of the second cross-coupled pair of inverters is connected to a voltage rail through a corresponding transistor device. Each of the two transistor devices is connected to a node that is between the switching unit and the first inverter circuit or the second inverter circuit. The latch circuit implements data aware power gating to reduce or eliminate dynamic power consumption caused by redundant clock transitions within the latch circuit. Other embodiments are also described.

In an embodiment, a latch circuit includes an input terminal configured to receive an input data signal, a switching unit configured to control application of the input data signal, a first inverter circuit connected to the switching unit, where the first inverter circuit includes a first cross-coupled pair of inverters, and a second inverter circuit connected to the first inverter circuit through the switching unit. The second inverter circuit includes a second cross-coupled pair of inverters and two transistor devices. Each inverter of the second cross-coupled pair of inverters is connected to a voltage rail through a corresponding transistor device. Each of the two transistor devices is connected to a node that is between the switching unit and the first inverter circuit or the second inverter circuit.

In an embodiment, a latch circuit includes an input terminal configured to receive an input data signal, a switching unit, a first inverter circuit, and a second inverter circuit. The switching unit includes a first inverter configured to generate an inverted version of the input data signal from the input data signal, a second inverter connected to the first inverter and configured to generate a non-inverted version of the input data signal, a first set of switching transistors of a first polarity type, where the first set of switching transistors are connected to the first and second inverters and a second set of switching transistors of a second, opposite, polarity type. The first inverter circuit is connected to the first and second sets of switching transistors and includes a first cross-coupled pair of inverters. The second inverter circuit is connected to the first inverter circuit through the second set of switching transistors. The second inverter circuit includes a second cross-coupled pair of inverters and two transistor devices. Each inverter of the second cross-coupled pair of inverters is connected to a low voltage rail and to a high voltage rail through a corresponding transistor device. Gate terminals of the two transistor devices are cross-connected to drain terminals or source terminals of the second set of switching transistors.

In an embodiment, a method for operating a latch circuit involves receiving input data at the latch circuit and discharging or charging input nodes of a cross-coupled pair of inverters of the latch circuit if the input data is different for consecutive clock cycles of the latch circuit.

FIG. 1is a schematic block diagram of a latch circuit100in accordance with an embodiment of the invention. In the embodiment depicted inFIG. 1, the latch circuit includes an input terminal102, a switching unit104, a first inverter circuit106, a second inverter circuit108, and an output terminal110. The latch circuit can be used in various applications, such as automotive applications, communications applications, industrial applications, medical applications, computer applications, and/or consumer or appliance applications. The latch circuit can be implemented in a substrate, such as a semiconductor wafer or a printed circuit board (PCB). In an embodiment, the latch circuit is included in a low power system-on-chip (SoC). For example, the latch circuit may be included in a low power cryptographic SoC. Although the latch circuit is shown inFIG. 1as including certain components, in some embodiments, the latch circuit includes less or more components to implement less or more functionalities. For example, the latch circuit may include a clock source or a voltage source.

The input terminal102of the latch circuit100is configured to receive an input data signal. The output terminal110of the latch circuit is configured to output an output data signal in response to the input data signal.

The switching unit104of the latch circuit100is configured to control application of the input data signal. In some embodiments, the switching unit controls application of the input data signal to the first inverter circuit and to the second inverter circuit. The switching unit may include a first set of switches that includes transistors of a first polarity type and a second set of switches that includes transistors of a second, opposite, polarity type.

The first inverter circuit106of the latch circuit100is connected to the switching unit104and includes a first cross-coupled pair112of inverters114,116. A cross-coupled pair of inverters is also referred to as a cross-coupled inverter pair (CCIP). The second inverter circuit108of the latch circuit is connected to the first inverter circuit through the switching unit. The second inverter circuit includes a second cross-coupled pair122of inverters124,126, and at least two transistor devices128,130. In some embodiments, each inverter of the second cross-coupled pair of inverters is connected to a voltage rail132through a corresponding transistor device128or130. The voltage rail may have a positive voltage. Alternatively, the voltage rail may be connected to the ground. In these embodiments, each of the two transistor devices is connected to a node that is between the switching unit and the first inverter circuit or the second inverter circuit. In some embodiments, the first inverter circuit106is a master inverter circuit and the second inverter circuit108is a slave inverter circuit. In these embodiments, a change in state of the first inverter circuit causes a change in state of the second inverter circuit.

Latch circuits, such as a Master-Slave D-type flip-flop, a “clock on demand” flip-flop, and a master slave flip-flop, as described in European Patent Application No. EP13191288, use clock gating to turn off the clocking of the portion of the latch circuit that is not in use. However, clock gating can be ineffective for situations in which the data sampled by the clocked element is identical for two consecutive clock cycles. The redundant switching of the internal nodes of a latch circuit caused by the clock signal, when the input data at the input terminal102is in the same state for consecutive clock cycles, may cause an unnecessary increase in the power consumption (e.g., un necessary charging and discharging of internal node parasitic capacitances). In the embodiment depicted inFIG. 1, input data aware power gating can be implemented by connecting each of the two transistor devices128,130to a node that is between the switching unit104and the first inverter circuit112or the second inverter circuit122. Compared to other retention latch circuits, the latch circuit100depicted inFIG. 1exhibits reduced power consumption, eliminates extra control signals, and reduces area overhead due to redundant switching by input data aware power gating. In addition, compared to other latch circuits, the latch circuit depicted inFIG. 1does not require an internal clock-buffer. Further, compared to other latch circuits, the latch circuit depicted inFIG. 1can use single phase clocking, and therefore does not need internal clock signal inversion. The latch circuit depicted inFIG. 1can be implemented with low power, with no dynamic power consumption for redundant transitions when the input data signal and the output data signal are the same.

In some embodiments, gate terminals of the two transistor devices128,130of the second inverter circuit108are cross-connected to nodes between the switching unit104and the second cross-coupled pair of inverters122.FIG. 2depicts an embodiment of the latch circuit100depicted inFIG. 1in which gate terminals, “G,” of two transistor devices260,262of a slave inverter circuit208are cross-connected to nodes282,272between a switching unit204and a cross-coupled inverter pair (CCIP)222(referred to as the slave CCIP) of the slave inverter circuit. In the embodiment depicted inFIG. 2, a latch circuit200includes an input terminal, “DIN,” the switching unit204, a master inverter circuit206having a cross-coupled inverter pair (CCIP)222(referred to as the master CCIP), the slave inverter circuit208having the slave CCIP222, an inverter227, and an output terminal, “DOUT.” A change in state of the master inverter circuit causes a change in state of the slave inverter circuit. In the embodiment depicted inFIG. 2, input data aware power gating is implemented for the slave inverter circuit208. The latch circuit200depicted inFIG. 2is one possible embodiment of the latch circuit100depicted inFIG. 1. However, the latch circuit100depicted inFIG. 1is not limited to the embodiment shown inFIG. 2.

In an embodiment, the input terminal, “DIN,” is configured to receive an input data signal. The output terminal, “DOUT,” is configured to output an output data signal in response to the input data signal.

The switching unit204, which includes an inverter circuit240and a switching module242, is configured to control the application of the input data signal received from the input terminal, “DIN,” to inverters214,216of the master CCIP212and to inverters224,226of the slave CCIP222. The inverter circuit240is configured to generate an inverted version, “DBN,” of the input data signal and a non-inverted version, “DB,” of the input data signal. In the embodiment depicted inFIG. 2, the inverter circuit240includes inverters244,246. The inverter244is connected to the input terminal, “DIN,” and is configured to generate the inverted version, “DBN,” of the input data signal. The inverter246is configured to generate the non-inverted version, “DB,” of the input data signal. The switching module242is configured to switch either the inverted version, “DBN,” or the non-inverted version, “DB,” of the input data signal to an input terminal of the master CCIP212or the slave CCIP222and to switch the other one of the inverted and non-inverted versions of the input data signal to an output terminal of the master CCIP212or the slave CCIP222. In the embodiment depicted inFIG. 2, the switching module includes a first set of switches that are implemented as PMOS transistors250,252, and a second set of switches that are implemented as NMOS transistors256,258. The transistor250is configured to switch the inverted version, “DBN,” of the input data signal to an input terminal290of the master CCIP212. The transistor252is configured to switch the non-inverted version, “DB,” of the input data signal to an output terminal292of the master CCIP212. The transistor256is configured to switch the inverted version, “DBN,” of the input data signal to an input terminal282of the slave CCIP222. The transistor258is configured to switch the non-inverted version, “DB,” of the input data signal to an output terminal272of the slave CCIP222.

The master inverter circuit206includes the master CCIP212, which includes inverters214,216. The inverters214,216are connected back-to-back. As shown inFIG. 2, the output terminal of the inverter214is connected to the input terminal of the inverter216, while the output terminal of the inverter216is connected to the input terminal of the inverter214.

The slave inverter circuit208is connected to the master inverter circuit206through the switching unit204. In the embodiment depicted inFIG. 2, the slave inverter circuit includes the slave CCIP222with the inverters224,226and two transistor devices260,262that are implemented as PMOS transistors. The inverter224includes an NMOS transistor266and a PMOS transistor268connected in series with each other. Gate terminals, “G,” of the NMOS transistor266and the PMOS transistor268are connected to a source terminal or drain terminal of the NMOS transistor258. The PMOS transistor260is connected to a high voltage rail270with a positive voltage, “VDD,” and to the inverter224. The inverter226includes an NMOS transistor276and a PMOS transistor278connected in series with each other. Gate terminals, “G,” of the NMOS transistor276and the PMOS transistor278are connected to a source terminal or drain terminal of the NMOS transistor256. The PMOS transistor262is connected to the high voltage rail270with the positive voltage, “VDD,” and to the inverter226. The transistors266,276are connected to a low voltage rail280that is connected to ground. In the embodiment depicted inFIG. 2, PMOS transistors260,268are stacked together while PMOS transistors262,278are stacked together. Stacked PMOS transistors in the slave inverter circuit helps to mitigate leakage current. In the embodiment depicted inFIG. 2, input data aware power gating is implemented using floating power gating for the slave inverter circuit. Specifically, the gate terminal, “G,” of the PMOS transistor262is connected to the node282that is connected to the NMOS transistor256and the gate terminal, “G,” of the PMOS transistor260is connected to a node272that is connected to the NMOS transistor258. The latch circuit200enables relaxed transistor sizes because the floating connection of the slave CCIP to the voltage rail270that is dependent on the input data of the latch circuit can facilitate and accelerate the overpowering of the state of the slave CCIP222. Compared to other latch circuits, the latch circuit depicted inFIG. 2does not require internal clock signal inversion. Absence of an internal clock inverter pair reduces unnecessary power consumption caused by the redundant clock transitions in which the input data remains the same for consecutive clock cycles of the clock signal, “CK,” because all the internal charging and discharging of the capacitances of the latch circuit200occur when the input data of the latch circuit200changes.

Turning back toFIG. 1, in some embodiments, input data aware power gating is implemented for the slave inverter circuit108in which gate terminals of the two transistor devices128,130are cross-connected to nodes between two switches of the switching unit104and the first cross-coupled pair of inverters112.FIG. 3depicts an embodiment of the latch circuit100depicted inFIG. 1in which gate terminals of the two transistor devices260,262of a slave inverter circuit308are cross-connected to nodes between a switching unit204and a cross-coupled inverter pair (CCIP)222(referred to as the slave CCIP) of the slave inverter circuit308. In the embodiment depicted inFIG. 3, a latch circuit300includes the input terminal, “DIN,” the switching unit204, a master inverter circuit206having a master CCIP212, the slave inverter circuit308having the slave CCIP222, the inverter227, and the output terminal, “DOUT.” The difference between the latch circuit300depicted inFIG. 3and the latch circuit200depicted inFIG. 2is the connections of the floating gate terminals, “G,” of the PMOS transistors260,262. In the embodiment depicted inFIG. 3, input data aware power gating is implemented using floating power gating for the slave CCIP222. Specifically, the gate terminal, “G,” of the PMOS transistor260is connected to a node372that is connected to the NMOS transistor258and the inverters214,216of the master inverter circuit while the gate terminal, “G,” of the PMOS transistor262is connected to a node382that is connected to the NMOS transistor256and the inverters214,216of the master inverter circuit. The latch circuit300enables relaxed transistor sizes because of the floating connection of the slave CCIP to the voltage rail270dependent on the input data of the latch circuit can facilitate and accelerate the overpowering of the state of the slave CCIP222. Compared to other latch circuits, the latch circuit depicted inFIG. 3does not require an internal clock signal inversion, which reduces unnecessary power consumption caused by the redundant clock transitions.

Turning back toFIG. 1, in some embodiments, input data aware power gating is implemented for both the slave inverter circuit108and the master inverter circuit106.FIG. 4depicts an embodiment of the latch circuit100depicted inFIG. 1in which input data aware power gating is implemented for a slave inverter circuit308and the master inverter circuit406. In the embodiment depicted inFIG. 4, the latch circuit400includes the input terminal, “DIN,” the switching unit204, the master inverter circuit406having a master CCIP412, the slave inverter circuit308having a slave CCIP222, the inverter227, and the output terminal, “DOUT.” In the embodiment depicted inFIG. 4, the master inverter circuit406includes the cross-coupled pair412of inverters414,416and two transistor devices460,462that are implemented as PMOS transistors. The inverter414includes an NMOS transistor466and a PMOS transistor468connected in series with each other. Gate terminals, “G,” of the NMOS transistor466and the PMOS transistor468are connected to a source terminal or drain terminal of the PMOS transistor252. The PMOS transistor460is connected to the high voltage rail270with the positive voltage, “VDD,” and to the inverter414. The inverter416includes an NMOS transistor476and a PMOS transistor478connected in series with each other. Gate terminals, “G,” of the NMOS transistor476and the PMOS transistor478are connected to a source terminal or drain terminal of the PMOS transistor250. The PMOS transistor462is connected to the high voltage rail270with the positive voltage, “VDD,” and to the inverter416. The transistors466,476are connected to a low voltage rail280that is connected to the ground. In the embodiment depicted inFIG. 4, PMOS transistors460,468are stacked together while PMOS transistors462,478are stacked together. Stacked PMOS transistors in the slave inverter circuit and the master inverter circuit helps to mitigate the leakage current. In the embodiment depicted inFIG. 4, input data aware power gating is implemented using floating power gating for slave cross-coupled inverters and master cross-coupled inverters. Specifically, the gate terminal, “G,” of the PMOS transistor460is connected to a node472at the output of the inverter246that is connected to the PMOS transistor252, while the gate terminal of the PMOS transistor462is connected to a node482at the output of the inverter244that is connected to the PMOS transistor250. In the latch circuit depicted inFIG. 4, the internal nodes (e.g., DBN, DB) of the latch circuit are discharged or charged only when the input data received at the input terminal, “DIN,” is different for consecutive clock cycles of the clock signal, “CK.” Compared to other latch circuits, the latch circuit depicted inFIG. 4does not require internal clock signal inversion. The absence of an internal clock inverter pair reduces unnecessary power consumption caused by redundant clock transitions in which the input data remains the same for consecutive clock cycles of the clock signal, “CK.”

Some examples of operation of the latch circuit400depicted inFIG. 4are described with respect to signal value transitions labeled inFIGS. 5-7. Specifically,FIG. 5shows the latch circuit ofFIG. 4with a low phase of the clock signal, “CK.” In the embodiment depicted inFIG. 5, the input data at the input terminal, “DIN,” transitions from “1” to “0.” Because of the inverters244,246, signals at the PMOS transistors250,252are “1” and “0,” respectively. The transition of the input data turns off the PMOS transistor462, which is stacked to the inverter416holding the logic value “1,” and facilitates overpowering of the master CCIP data.

FIG. 6shows the latch circuit400ofFIG. 4with a rising edge of the clock signal, “CK.” In the embodiment depicted inFIG. 6, the transition of the input data turns off the PMOS transistor262, which is stacked to the inverter226holding “1,” and facilitates overpowering of the slave CCIP data.

FIG. 7shows the latch circuit400ofFIG. 4in an active hold state. In the embodiment depicted inFIG. 7, the output data at the output terminal, “DOUT,” is at “0.” The stacked PMOS transistors in the master CCIP and the slave CCIP limit the leakage current.

FIG. 8shows the latch circuit300ofFIG. 3in a retention state. In the embodiment depicted inFIG. 8, the states of the slave CCIP222and the master CCIP212are retained. In the retention state, the output data at the output terminal, “DOUT,” is at “0.” The clock signal, “CK,” is at logical high such that internal latch information from the input terminal, “DIN,” is isolated as PMOS transistors250,252are turned OFF. The redundancy (duplication) of stored states in the master CCIP and the slave CCIP provides an extra resilience against data flips risk during retention. The stacked OFF transistors (e.g., transistors262,278the slave inverter circuit308) helps to mitigate the leakage current. The latch circuit does not need extra control signals as used in balloon latch type retention flip flop circuits.

FIG. 9illustrates an example of signals of the latch circuits300,400depicted inFIG. 3andFIG. 4. In the embodiment depicted inFIG. 9, the clock input, “CLK,” the data input at the terminal, “DIN,” the data output at the terminal, “DOUT”, the input at node, “Q,” and the inverted input at node, “QB,” to the slave CCIP, and the input at node, “GP,” and inverted input at node, “GN,” to the master CCIP are shown. The internal nodes of the latch circuits, (e.g., GP, GN, QB, Q) are discharged or charged only when the input data received at the input terminal, “DIN,” is different for consecutive clock cycles of the clock signal, “CK.”

FIG. 10is a process flow diagram that illustrates a method for operating a latch circuit in accordance with another embodiment of the invention. The latch circuit may be, for example, the same as or similar to the latch circuit100depicted inFIG. 1, the latch circuit200depicted inFIG. 2, the latch circuit300depicted inFIG. 3, and/or the latch circuit400depicted inFIG. 4. At block1002, input data is received at the latch circuit. At block1004, input nodes of a cross-coupled pair of inverters of the latch circuit are discharged or charged if the input data is different for consecutive clock cycles of the latch circuit.

In addition, although specific embodiments of the invention that have been described or depicted include several components described or depicted herein, other embodiments of the invention may include fewer or more components to implement less or more features.

Furthermore, although specific embodiments of the invention have been described and depicted, the invention is not to be limited to the specific forms or arrangements of parts so described and depicted. The scope of the invention is to be defined by the claims appended hereto and their equivalents.