Semiconductor device package with groove

A semiconductor device package includes a semiconductor chip having bonding pads; a printed circuit board (PCB) including an insulation pattern with a groove and bonding electrodes corresponding to the bonding pads, the groove corresponding to the edge of the semiconductor chip and being formed to partially expose a lower portion of the edge of the semiconductor chip; an adhesive material provided for adhering the bottom of the semiconductor chip to the insulation pattern to mount the semiconductor chip on the PCB; bonding wires provided for electrically connecting the bonding electrodes to the corresponding bonding pads; and a molding material provided for sealing the PCB, the semiconductor chip, the adhesive material, and the bonding wires.

CROSS-REFERENCE TO RELATED APPLICATIONS

This U.S. non-provisional patent application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2006-91386, filed on Sep. 20, 2006, the entirety of which is hereby incorporated by reference.

BACKGROUND

1. Technical Field

The present invention relates to semiconductor device packages and, more specifically, to a semiconductor device package having a groove to prevent void formation between a semiconductor chip and a printed circuit board.

2. Description of the Related Art

With the recent trend toward higher integration of semiconductor devices as well as miniaturization and multi-functionalization of electronic appliances, there is a requirement for a variety of semiconductor device packaging technologies. For instance, mounting of bare chips is often conducted as a high-density mounting method for specific applications that require high performance. However, a bare chip package suffers from problems such as difficulty in quality assurance of the bare chips, establishment and standardization of package technologies by users, and reliability guarantee issues after packaging the bare chips. Therefore, the bare chip package is not widely utilized.

In view of the foregoing requirements, a variety of semiconductor device packages have been developed. One of the semiconductor device packages is a ball grid array package (BGA package), which is a high-density surface mount technology (SMT) package where a printed circuit board (PCB) is used instead of a lead frame and an external lead is not needed. As input/output terminals of a semiconductor device are increasing in number, recent attention has been focused on the BGA package where ball-type protrusive terminals are formed on an entire bottom surface of the semiconductor device package.

Typical configurations of a BGA package are characterized in that, instead of leads, solder balls are used as connection terminals to electrically connect a semiconductor chip and a main board to each other. BGA packages are classified into ceramic BGA (CBGA) packages, plastic BGA (PBGA) packages, tape BGA (TBGA) packages, metal BGA (MBGA) packages, and fine pitch BGA (FPBGA) packages.

Semiconductor device packages are becoming lighter, thinner, shorter, and smaller. For this reason, most adhesive materials used to adhere a semiconductor chip (or die) to a PCB are changing to film-type materials that advantageously provide a lower profile of the semiconductor device package and are suitable for a thin semiconductor wafer. However, defects may occur in the case where a film-type adhesive material is used. One of the typical defects is a swelling phenomenon, which is due to the delamination resulting from a void formed at the boundary between the semiconductor chip and the PCB. The swelling phenomenon has an adverse effect on the reliability of the package. The swelling phenomenon occurring between the lowermost semiconductor chip of a stacked chip semiconductor device package and the PCB is the most common defect occurring in the semiconductor device package. The present invention addresses these and other disadvantages of the conventional art.

SUMMARY

Exemplary embodiments of the present invention are directed to a semiconductor device chip package. In an exemplary embodiment, the semiconductor device chip package may include: a semiconductor chip including bonding pads; a printed circuit board (PCB) including an insulation pattern with a groove and bonding electrodes corresponding to the bonding pads, the groove corresponding to the edge of the semiconductor chip and being formed to partially expose a lower portion of the edge of the semiconductor chip; an adhesive material provided for adhering the bottom of the semiconductor chip to the insulation pattern to mount the semiconductor chip on the PCB; bonding wires provided for electrically connecting the bonding electrodes to the corresponding bonding pads; and a molding material provided for sealing the PCB, the semiconductor chip, the adhesive material, and the bonding wires.

DETAILED DESCRIPTION

FIG. 1Ais a top plan view illustrating a semiconductor chip package according to an embodiment of the present invention, andFIG. 1Bis a cross-sectional view taken along the line I-I′ ofFIG. 1A.

Referring toFIGS. 1A and 1B, the semiconductor chip package includes a semiconductor chip110, a printed circuit board (PCB)120, an adhesive material114, bonding wires140, and a molding material150. The semiconductor chip110includes bonding pads112, which are disposed on the upper surface of the semiconductor chip110. The PCB120includes an insulation pattern122and bonding electrodes124, which are disposed on the upper surface of the PCB120. The insulation pattern122includes a groove126, which corresponds to the edge of the semiconductor chip110and is formed to expose a lower portion of the edge of the semiconductor chip110. The bonding electrodes124correspond to the bonding pads112. The adhesive material114is used to adhere the bottom of the semiconductor chip110to the insulation pattern122, mounting the semiconductor chip110on the PCB120. The bonding wires140are provided to electrically connect the bonding electrodes124to the corresponding bonding pads112. The molding material150is used to seal the PCB120, the semiconductor chip110, the adhesive material114, and the bonding wires140. Reference numerals128,130, and132represent joint electrodes128, an insulation material130, and solder balls132, respectively, for a connection terminal provided to electrically connect the ball grid array package type PCB120, on which the semiconductor chip110is mounted, to an underlying main board.

The semiconductor chip110may be mounted on the PCB120, including the upper surface on which the insulation pattern122is provided, by the adhesive material114. The insulation pattern122may be a photo solder resist (PSR). The adhesive material114may be a film-type material, which advantageously provides a lower profile of a semiconductor device package and is suitable for a thin semiconductor wafer.

The groove126may be formed to partially expose a lower portion of the edge of the semiconductor chip110and to expose the PCB120at the same time. During a process of mounting the semiconductor chip110on the PCB120, the groove126serves to offer a path along which a void formed at the boundary between the semiconductor chip110and the PCB120may be discharged. Therefore, the formation of a void may be suppressed at the boundary between the semiconductor chip110and the PCB120during the process of mounting the semiconductor chip110on the PCB120.

In the case where the semiconductor chip110is rectangular, the groove126may be a closed rectangular groove formed to partially expose a lower portion of the edge of the semiconductor chip110and to expose the PCB120at the same time. As illustrated inFIG. 1A, the groove126is formed to partially expose lower portions of all side edges of the semiconductor chip110and to expose the PCB120at the same time.

In order to electrically connect the semiconductor chip110to the PCB120, the bonding pads112provided on the semiconductor chip110may be wire bonded to the bonding electrodes124spaced apart from the semiconductor chip110by means of the bonding wires140made of conductive metal lines. The bonding electrodes124are arranged around the semiconductor chip110to be used as terminals for electrical connection to the exterior.

The molding material150may seal the PCB120, the semiconductor chip110, the adhesive material114, and the boding wires140to fully cover the PCB120on which the semiconductor chip110is mounted. The molding material150may be epoxy molding compound (EMC).

The groove126may be formed at a position so as to change the flow of the molding material150during a process of sealing the molding material150. Thus, during the process of sealing the molding material150, the groove126serves to prevent incomplete molding caused by a difference between a flow rate at an area where the semiconductor chip110of the PCB120is mounted and a flow rate at an area where the semiconductor chip110of the PCB120is not mounted. Moreover, the molding material150fills the groove126to prevent the swelling phenomenon where a void formed at the boundary between the semiconductor chip110and the PCB120absorbs external water (H2O) and gas so as to be swollen. In addition, since the molding material150has a higher adhesion force to the PCB120than the insulation pattern122, a locking effect of the molding material150may be enhanced.

The table [TABLE 1] shows the conditions and the result of a pre-confirm test for estimating reliability of semiconductor chip packages. The pre-confirm test is conducted from level “0” to level “2”. The levels “0”, “1”, and “2” may include extreme environmental conditions each having temperature, humidity, and time. A reflow process is carried out for semiconductor chip packages subjected to the extreme environmental conditions. In this case, the highest temperature of the reflow process is 260 degrees centigrade. The extreme environmental conditions and the reflow process are designed to expedite the swelling phenomenon so that defects can be identified.

As shown through the pre-confirm test of the level “2”, no defect occurs at a number of semiconductor chip packages (180 semiconductor chip packages) according to the present invention. Thus, it may be concluded that the semiconductor chip packages according to the present invention prevent the swelling phenomenon occurring between the semiconductor chip110and the PCB120.

FIG. 2Ais a top plan view illustrating a semiconductor chip package according to another embodiment of the present invention.FIGS. 2B and 2Care cross-sectional views taken along the lines II-II′ and III-III′ ofFIG. 2A, respectively.

Referring toFIGS. 2A through 2C, the semiconductor chip package includes a semiconductor chip210, a printed circuit board (PCB)220, an adhesive material214, bonding wires240, and a molding material250. The semiconductor chip210includes bonding pads212, which are disposed on the upper surface of the semiconductor chip210. The PCB220includes an insulation pattern222and bonding electrodes224, which are disposed on the upper surface of the PCB220. The insulation pattern222includes a groove226, which corresponds to the edge of the semiconductor chip210and is formed to expose a lower portion of the edge of the semiconductor chip210. The bonding electrodes224correspond to the bonding pads212. The adhesive material214is used to adhere the bottom of the semiconductor chip210to the insulation pattern222, mounting the semiconductor chip210on the PCB220. The bonding wires240are provided to electrically connect the bonding electrodes224to the corresponding bonding pads212. The molding material250is used to seal the PCB220, the semiconductor chip210, the adhesive material214, and the bonding wires240. Reference numerals228,230, and232represent joint electrodes228, an insulation material230, and solder balls232, respectively, for a connection terminal provided to electrically connect the ball grid array package type PCB220, on which the semiconductor chip210is mounted, to an underlying main board.

The semiconductor chip210may be mounted on the PCB220, including the upper surface on which the insulation pattern222is provided, by the adhesive material214. The insulation pattern222may be a photo solder resist (PSR). The adhesive material214may be a film-type material, which advantageously provides a lower profile of a semiconductor device package and is suitable for a thin semiconductor wafer.

The groove226may be formed to partially expose a lower portion of the edge of the semiconductor chip210and to expose the PCB220at the same time. During a process of mounting the semiconductor chip210on the PCB220, the groove226serves to offer a path along which a void formed at the boundary between the semiconductor chip210and the PCB220may be discharged. Therefore, the formation of a void may be suppressed at the boundary between the semiconductor chip210and the PCB220during the process of mounting the semiconductor chip210on the PCB220.

In the case where the semiconductor chip210is rectangular, the groove226may be a closed rectangular groove formed to partially expose a lower portion of at least one edge of the semiconductor chip210and to expose the PCB220at the same time. The groove226may be formed to partially expose a lower portion of at least one pair of opposite edges of the semiconductor chip210and the PCB220at the same time. As illustrated inFIG. 2A, the groove226may be formed to partially expose a lower portion of a pair of edges of the semiconductor chip210perpendicular to the line III-III′ and to expose the PCB220at the same time.

The molding material250may seal the PCB220, the semiconductor chip210, the adhesive material214, and the boding wires240to fully cover the PCB220on which the semiconductor chip210is mounted. The molding material250may be epoxy molding compound (EMC).

FIG. 3Ais a top plan view illustrating a semiconductor chip package according to still another embodiment of the present invention.FIGS. 3B and 3Care cross-sectional views taken along the lines IV-IV′ and V-V′ ofFIG. 3A, respectively.

Referring toFIGS. 3A through 3C, the semiconductor chip package includes a semiconductor chip310, a printed circuit board (PCB)320, an adhesive material314, bonding wires340, and a molding material350. The semiconductor chip310includes bonding pads312, which are disposed on the upper surface of the semiconductor chip310. The PCB320includes an insulation pattern322and bonding electrodes324, which are disposed on the upper surface of the PCB320. The insulation pattern322includes a groove326, which corresponds to the edge of the semiconductor chip310and is formed to expose a lower portion of the edge of the semiconductor chip310. The bonding electrodes324correspond to the bonding pads312. The adhesive material314is used to adhere the bottom of the semiconductor chip310to the insulation pattern322mounting the semiconductor chip310on the PCB320. The bonding wires340are provided to electrically connect the bonding electrodes324to the corresponding bonding pads312. The molding material350is used to seal the PCB320, the semiconductor chip310, the adhesive material314, and the bonding wires340. Reference numerals328,330, and332represent joint electrodes328, an insulation material330, and solder balls332, respectively, for a connection terminal provided to electrically connect the ball grid array package type PCB320, on which the semiconductor chip310is mounted, to an underlying main board.

The semiconductor chip310may be mounted on the PCB320, including the upper surface on which the insulation pattern322is provided, by the adhesive material314. The insulation pattern322may be a photo solder resist (PSR). The adhesive material314may be a film-type material, which advantageously provides a lower profile of a semiconductor device package and is suitable for a thin semiconductor wafer.

The groove326may be formed to partially expose a lower portion of the edge of the semiconductor chip310and to expose the PCB320at the same time. During a process of mounting the semiconductor chip310on the PCB320, the groove326serves to offer a path along which a void formed at the boundary between the semiconductor chip310and the PCB320may be discharged. Therefore, the formation of a void may be suppressed at the boundary between the semiconductor chip310and the PCB320during the process of mounting the semiconductor chip310on the PCB320.

In the case where the semiconductor chip310is rectangular, the groove326may be a closed rectangular groove formed to partially expose a lower portion of at least one edge of the semiconductor chip310and to expose the PCB320at the same time. The groove326may be formed to partially expose a lower portion of at least one pair of opposite edges of the semiconductor chip310and the PCB320at the same time. As illustrated inFIG. 3A, the groove326may be formed to partially expose a lower portion of a pair of edges of the semiconductor chip310perpendicular to the line IV-IV′ and to expose the PCB320at the same time.

The molding material350may seal the PCB320, the semiconductor chip310, the adhesive material314, and the boding wires340to fully cover the PCB320on which the semiconductor chip310is mounted. The molding material350may be epoxy molding compound (EMC).

FIG. 4Ais a top plan view illustrating a semiconductor chip package according to yet another embodiment of the present invention.FIGS. 4B and 4Care cross-sectional views taken along the lines VI-VI′ and VII-VII′ ofFIG. 4A, respectively.

Referring toFIGS. 4A through 4C, the semiconductor chip package includes a semiconductor chip410, a printed circuit board (PCB)420, an adhesive material414, bonding wires440, and a molding material450. The semiconductor chip410includes bonding pads412, which are disposed on the upper surface of the semiconductor chip410. The PCB420includes an insulation pattern422and bonding electrodes424, which are disposed on the upper surface of the PCB420. The insulation pattern422includes a groove426, which corresponds to the edge of the semiconductor chip410and is formed to expose a lower portion of the edge of the semiconductor chip410. The bonding electrodes424correspond to the bonding pads412. The adhesive material414is used to adhere the bottom of the semiconductor chip410to the insulation pattern422, mounting the semiconductor chip410on the PCB420. The bonding wires440are provided to electrically connect the bonding electrodes424to the corresponding bonding pads412. The molding material450is used to seal the PCB420, the semiconductor chip410, the adhesive material414, and the bonding wires440. Reference numerals428,430, and432represent joint electrodes428, an insulation material430, and solder balls432, respectively, for a connection terminal provided to electrically connect the ball grid array package type PCB420, on which the semiconductor chip410is mounted, to an underlying main board.

The semiconductor chip410may be mounted on the PCB420, including the upper surface on which the insulation pattern422is provided, by the adhesive material414. The insulation pattern422may be a photo solder resist (PSR). The adhesive material414may be a film-type material, which advantageously provides a lower profile of a semiconductor device package and is suitable for a thin semiconductor wafer.

The groove426may be formed to partially expose a lower portion of the edge of the semiconductor chip410and to expose the PCB420at the same time. During a process of mounting the semiconductor chip410on the PCB420, the groove426serves to offer a path along which a void formed at the boundary between the semiconductor chip410and the PCB420may be discharged. Therefore, the formation of a void may be suppressed at the boundary between the semiconductor chip410and the PCB420during the process of mounting the semiconductor chip410on the PCB420.

In the case where the semiconductor chip410is rectangular, the groove426may be a closed rectangular groove formed to partially expose a lower portion of at least one edge of the semiconductor chip410and to expose the PCB420at the same time. The closed rectangular groove includes at least one extension portion extending in an edge direction of the PCB420. The groove426may be formed to partially expose a lower portion of at least one pair of opposite edges of the semiconductor chip410and the PCB420at the same time. As illustrated inFIG. 4A, the groove426may be formed to partially expose a lower portion of a pair of edges of the semiconductor chip410perpendicular to the line VII-VII′ and to expose the PCB420at the same time. Also the groove426may extend at the edge of the semiconductor chip410in a length direction to further expose a PCB420adjacent to a region where the bonding electrodes424are formed.

The molding material450may seal the PCB420, the semiconductor chip410, the adhesive material414, and the boding wires440to fully cover the PCB420on which the semiconductor chip410is mounted. The molding material450may be epoxy molding compound (EMC).

FIG. 5Ais a top plan view illustrating a stacked chip semiconductor device package according to some embodiments of the present invention, andFIG. 5Bis a cross-sectional view taken along the line VIII-VIII′ ofFIG. 5A.

Referring toFIGS. 5A and 5B, the stacked chip semiconductor device package includes stacked semiconductor chips510a,510b,510c, etc., a printed circuit board (PCB)520, an adhesive material514, bonding wires540a,540b, and540c, and a molding material550. The stacked semiconductor chips510a,510b,510c, etc., include bonding pads512a,512b,512c, etc., which are disposed on the upper surface of the stacked semiconductor chips510a,510b,510c, etc., respectively. The PCB520includes an insulation pattern522and bonding electrodes524. The insulation pattern522includes a groove526, which corresponds to the edge of an overlying lowermost semiconductor chip510aand is formed to partially expose a lower portion of the edge of the lowermost semiconductor chip510a. The bonding electrodes524correspond to bonding pads512a,512b,512c, etc., respectively. The adhesive material514is used to adhere the bottom of the lowermost semiconductor chip510ato the insulation pattern522, mounting the stacked semiconductor chips510a,510b,510c, etc. on the PCB520. The bonding wires540a,540b, and540care provided to electrically connect the bonding electrodes324to the corresponding bonding pads512a,512b, and512c, respectively. The molding material550is used to seal the PCB520, the stacked semiconductor chips510a,510b,510c, etc., the adhesive material514, and the bonding wires540a,540b, and540c. Reference numerals516aand516brepresent inter-chip adhesive materials516aand516bused to adhere the stacked semiconductor chips510a,510b, and510c, to each other, respectively. Reference numerals528,530, and532represent joint electrodes528, an insulation material530, and solder balls532, respectively, for a connection terminal provided to electrically connect the ball grid array package type PCB520, on which the stacked semiconductor chips510a,510b,510c, etc. are mounted, to an underlying main board.

The stacked semiconductor chips510a,510b,510c, etc. may be mounted on the PCB520, including the upper surface on which the insulation pattern522is provided, by the adhesive material514. The insulation pattern522may be a photo solder resist (PSR). The adhesive material514may be a film-type material, which advantageously provides a lower profile of a semiconductor device package and is suitable for a thin semiconductor wafer. The inter-chip adhesive materials516aand516b, which are used to adhere the stacked semiconductor chips510a,510b, and510c, to each other, may each include a film-type adhesive material or an epoxy-group material having an adhesive property.

The groove526may be formed to partially expose a lower portion of the edge of a lowermost semiconductor chip510aand to expose the PCB520at the same time. During a process of mounting the stacked semiconductor chips510a,510b,510c, etc. on the PCB520, the groove526serves to offer a path along which a void formed at the boundary between the lowermost semiconductor chip510aand the PCB520may be discharged. Therefore, the formation of a void may be suppressed at the boundary between the lowermost semiconductor chip510aand the PCB520during the process of mounting the stacked semiconductor chips510a,510b,510c, etc. on the PCB520.

In the case where the lowermost semiconductor chip510ais rectangular, the groove526may be a closed rectangular groove formed to partially expose a lower portion of at least one edge of the lowermost semiconductor chip510aand to expose the PCB520at the same time or a groove including at least one extension portion extending in an edge direction of the PCB520. As illustrated inFIG. 5A, the groove526may be formed to partially expose a lower portion of edges of all sides of the lowermost semiconductor chip510aand to expose the PCB520at the same time.

Bonding pads512band512cof additional semiconductor chips510band510cstacked on the lowermost semiconductor chip510amay be connected to a selected one of the bonding pads512aand512bor the corresponding bonding electrodes524underlying the lowermost semiconductor chips510a. As illustrated inFIG. 5A, the bonding pads512a,512b, and512c, of the stacked semiconductor chips510a,510b, and510c, may be connected to corresponding bonding electrodes524.

The molding material550may seal the PCB520, the stacked semiconductor chips510a,510b,510c, etc., the adhesive material514, and the boding wires540a,540b, and540cto fully cover the PCB520on which the stacked semiconductor chips510a,510b,510c, etc. are mounted. The molding material550may be epoxy molding compound (EMC).

According to the foregoing embodiments of the present invention, a semiconductor device package is provided to offer a space along which a void is discharged during a process of adhering a semiconductor chip on a printed circuit board (PCB). Thus, a swelling phenomenon occurring between the semiconductor chip and the PCB is suppressed to achieve a reliable semiconductor device package.

Although the present invention has been described in connection with the embodiment of the present invention illustrated in the accompanying drawings, it is not limited thereto. It will be apparent to those skilled in the art that various substitutions, modifications and changes may be made without departing from the scope and spirit of the invention.