Semiconductor device and method of manufacturing

A semiconductor device includes a semiconductor substrate, and first and second transistors over the semiconductor substrate. Both the first and second transistors are p-type transistors or both the first and second transistors are n-type transistors. The first and second transistors have the same nominal operating voltage. The first transistor has a higher threshold voltage than the second transistor. The second transistor has at least one of a source region or a drain region with higher charge carrier mobility than at least one of a source region or a drain region of the first transistor.

BACKGROUND

The recent trend in miniaturizing integrated circuits (ICs) has resulted in smaller devices which consume less power, yet provide more functionally at higher speeds than before. For these advantages to be realized, various developments in IC manufacturing are developed. For example, as semiconductor devices, such as metal-oxide-semiconductor field-effect transistors (MOSFETs), are scaled down, source and drain regions of MOSFETs are formed with stressors to enhance carrier mobility and improve device performance.

DETAILED DESCRIPTION

In some embodiments, stressors are formed in devices or transistors with lower threshold voltages, but are not formed in devices or transistors with higher threshold voltages. As a result, enhanced carrier mobility and device performance are obtainable for the devices or transistors with lower threshold voltages. In the devices or transistors with higher threshold voltages, leakage current, which is associated with carrier mobility, is reduced due to the absence of stressors. The reduced leakage current in devices or transistors with higher threshold voltages is preferred over enhanced carrier mobility in at least one embodiment.

FIGS. 1A-1Fare schematic cross-sectional views of a semiconductor device in various manufacturing operations in accordance with some embodiments.

In one or more embodiments, the semiconductor device comprises active components such as field effect transistors (FET), complementary metal-oxide-semiconductor (CMOS) transistors, metal-oxide-semiconductor field effect transistors (MOSFETs), high voltage transistors, high frequency transistors, and combinations thereof. In one or more embodiments, the semiconductor device comprises passive components, such as resistors, capacitors, inductors, and fuses. In the description below, p-channel metal-oxide semiconductor (PMOS) and/or n-channel metal-oxide semiconductor (NMOS) devices are described. However, further embodiments are applicable to other types of semiconductor devices or components.

In the operation inFIG. 1A, a substrate110is formed with a plurality of isolation features111,112. In some embodiments, the substrate110comprises an elementary semiconductor, a compound semiconductor, an alloy semiconductor, or combinations thereof. Examples of the elementary semiconductor include, but are not limited to, silicon and germanium. Examples of a compound semiconductor include, but are not limited to, silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide. Examples of the alloy semiconductor include, but are not limited to, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP. Other semiconductor materials including group III, group IV, and group V elements are used in some embodiments. In one or more embodiments, the substrate110comprises a semiconductor on insulator (SOI), a doped epitaxial layer, a gradient semiconductor layer, and/or a stacked semiconductor structure with one semiconductor layer (e.g., Si) overlying another semiconductor layer (e.g., Ge) of a different type.

The isolation features111,112are formed at least partially in the substrate110. In some embodiments, the isolation features111,112include raised structures partially located outside the substrate110. The isolation features111,112utilize isolation technology, such as local oxidation of silicon (LOCOS) and/or shallow trench isolation (STI), to define and electrically isolate various regions of the substrate110from each other. In some embodiments, the isolation features111,112comprise silicon oxide, silicon nitride, silicon oxynitride, other suitable materials, or combinations thereof. The isolation features111,112are formed by a suitable process. In one example, the formation of an STI comprises a photolithography process, etching a trench in the substrate110, and filling the trench, for example, by using a chemical vapor deposition (CVD) process with one or more dielectric materials. In one or more embodiments, the filled trench has a multi-layer structure, such as a thermal oxide liner layer filled with silicon nitride or silicon oxide.

The isolation features111,112isolate various regions of the substrate110from each other. For example, one or more isolation features111(one of which is indicated inFIG. 1Afor simplicity) isolate an input/output (I/O) device region113of the substrate110from a core device region114of the substrate110. The core device region114includes circuitry formed of core devices which are the devices having the thinnest gate dielectric layer, fastest speed and lowest nominal operating voltage in the semiconductor device. The I/O device region113includes I/O devices which are configured to input and output data to and from the circuitry in the core device region114, and to exchange data with a peripheral device either in the semiconductor device or external to the semiconductor device. In at least one embodiment, the peripheral device includes at least one embedded flash cell formed over the substrate110. The I/O devices have a higher nominal operating voltage than the core devices.

One or more isolation features112(one of which is indicated inFIG. 1Afor simplicity) are formed inside the core device region114, and isolate a region115for at least one core device with a higher threshold voltage (hereinafter “HVt device”) from a region116for at least one core device with a lower threshold voltage (hereinafter “LVt device”). The HVt and LVt devices are both core devices and have the same nominal operating voltage. However, the HVt and LVt devices are configured to have different threshold voltages depending on the circuit design and/or application. In at least one embodiment, the HVt devices comprise devices with different levels of threshold voltages which are referred to as high threshold voltage devices and ultra-high threshold voltage devices in some situations. In at least one embodiment, the LVt devices comprise devices with different levels of threshold voltages which are referred to as standard threshold voltage devices, low threshold voltage devices and ultra-low threshold voltage devices in some situations.

One or more isolation features (not indicated inFIG. 1A) further isolate regions for p-type devices from regions for n-type devices. A p-type device is a device configured to have holes as charge carriers. An example of a p-type device is a PMOS transistor. An n-type device is a device configured to have electrons as charge carriers. An example of an n-type device is an NMOS transistor. In the following description, all regions113,115, and116indicated inFIG. 1Aare for the same type of devices. In one example, all devices in the regions113,115, and116are PMOS devices. In another example, all devices in the regions113,115, and116are NMOS devices.

The isolation features111,112define active regions117,118in the corresponding I/O device region113and core device region114. In some embodiments, one or more of the active regions117,118include doped regions. A p-type doped region comprises one or more p-type dopants, such as boron or BF2. An n-type doped region comprises one or more n-type dopants, such as phosphorus or arsenic. In one or more embodiments, doped regions are formed directly on the substrate110, in a P-well structure, an N-well structure, a dual-well structure, or a raised structure. When a p-type doped region is being formed, n-type doped regions or regions to be doped with n-type dopants are protected, for example, by one or more protective layers, such as photoresist layers, and vice versa. In at least one embodiment, the active region117of an I/O device is configured to be different from the active regions118of the HVt and LVt devices, for example, by performing different doping operations in the active region117and in the active regions118. In at least one embodiment, the active regions118of the HVt and LVt devices are configured to be the same.

A gate structure120of an I/O device is formed over the substrate110in the I/O device region113. The gate structure120comprises a gate dielectric layer121, a gate electrode122, and a hard mask layer123. Other layers are included in some embodiments. In some embodiments, the gate structure120is formed by CVD, physical vapor deposition (PVD), atomic layer deposition (ALD), high density plasma CVD (HDPCVD), plating, other suitable methods, or combinations thereof.

The gate dielectric layer121is formed over the substrate110and comprises a dielectric material, a high-k dielectric material, other suitable dielectric material, or combinations thereof. Examples of a dielectric material include, but are not limited to, silicon oxide, silicon oxynitride, silicon nitride, or combinations thereof. Examples of high-k dielectric materials include, but are not limited to, HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or combinations thereof. In some embodiments, the gate dielectric layer121comprises a multilayer structure. For example, the gate dielectric layer121comprises an interfacial layer, and a high-k dielectric material layer formed on the interfacial layer. An exemplary interfacial layer is a grown silicon oxide layer formed by a thermal process or ALD process.

The gate electrode122is formed over the gate dielectric layer121. In one or more embodiments, the gate electrode122is a polycrystalline silicon (polysilicon) layer. In one or more embodiments, the polysilicon layer is doped for proper conductivity, e.g., in a gate-first process. In one or more embodiments, the polysilicon is not doped where it is a dummy gate to be replaced in a subsequent gate replacement (gate last) process. In one or more embodiments, the gate electrode122comprises a conductive layer having a proper work function. For example, a p-type work function metal (p-metal) comprises TiN, TaN and/or a carbon-doped metal nitride such as TaCN, whereas an n-type work function metal (n-metal) comprises Ta, TiAl, and/or TiAlN—. In one or more embodiments, the work function layer comprises doped conducting oxide materials. In one or more embodiments, the gate electrode122comprises other conductive materials, such as aluminum, copper, tungsten, metal alloys, metal silicide, other suitable materials, or combinations thereof. For example, where the gate electrode122comprises a work function layer, another conductive layer is formed over the work function layer.

The hard mask layer123is formed over the gate electrode122to function as an etch mask, and/or to protect the underlying layers from damage during subsequent processing. In one or more embodiments, the hard mask layer123comprises silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or combinations thereof. The described structure of the gate structure120is an example. Other gate structure configurations are within the scope of various embodiments.

The regions of the I/O device region113outside the gate structure120are doped with dopants124to form lightly doped source/drain (LDD) regions125. The dopants are selected depending on the type of the devices to be formed in the LDD regions125. For example, LDD regions for forming NMOS devices are doped with an n-type dopant, such as phosphorous or arsenic, and LDD regions for forming PMOS devices are doped with a p-type dopant, such as boron or BF2. A resulting structure100A is obtained upon formation of the LDD regions125.

In the operation inFIG. 1B, dummy spacers126are formed over sidewalls of the gate structure120. In at least one embodiment, the dummy spacers126comprise a nitride material, such as silicon nitride, silicon oxide, silicon oxynitride, or combinations thereof. In some embodiments, a liner is formed over the sidewalls of the gate structure120before the spacers126are formed. In at least one embodiment, such a liner comprises an oxide material, such as silicon oxide and/or another suitable dielectric material. In at least one embodiment, the liner and the dummy spacers126are formed by blanket depositing a first dielectric layer for defining the liner over the structure100A, and a second dielectric layer for defining the dummy spacers126over the first dielectric layer. The dielectric layers are then anisotropically etched to form the liner and the dummy spacers126.

A selective ion implantation is performed to adjust the threshold voltage of the HVt device in the HVt device region115to be higher than the threshold voltage of the LVt device in the LVt device region116. For example, when the HVt device to be formed is a PMOS transistor, n-type dopants128, such as phosphorous, are implanted into the active region118of the HVt device in the HVt device region115, to form the n-doped region129. The presence of n-type dopants128in the active region118of a PMOS transistor decreases the number of holes (which are charge carriers of the PMOS transistor) available in a channel region of the PMOS transistor. Since fewer holes are available, a higher gate voltage is to be applied for switching the PMOS transistor, i.e., the threshold voltage of the PMOS transistor is increased. When the HVt device to be formed is an NMOS transistor, p-type dopants, such as boron, are implanted into the active region118of the HVt device. The higher the concentration of the dopants128, the higher the threshold voltage of the HVt device. In some embodiments, the dopants128are implanted in the active region118of the HVt device, and are not implanted in the active region118of the LVt device. In some embodiments, the dopants128are implanted in the active regions118of both the HVt and LVt devices, and with a higher concentration of the dopants128in the active region118of the HVt device than in the active region118of the LVt device. The described threshold voltage adjustment through ion implantation is an example. Other threshold voltage adjustment arrangements are within the scope of various embodiments. A resulting structure100B is obtained upon completion of the threshold voltage adjustment.

In the operation inFIG. 1C, gate structures130H and130L are formed over the structure100B, in the active regions118of the HVt and LVt devices. In at least one embodiment, the gate structure130H has a narrower width (or gate length) than the gate structure120, resulting in a HVt device (which is a core device) having a smaller size than the I/O device corresponding to the gate structure120. Similarly, the gate structure130L has a narrower width (or gate length) than the gate structure120, resulting in a LVt device (which is a core device) having a smaller size than the I/O device corresponding to the gate structure120.

In at least one embodiment, the gate structures130H and130L are configured to have the same configuration comprising a gate dielectric layer131, a gate electrode132and a hard mask layer133. In some embodiments, one or more of the described materials of and/or processes for forming the gate dielectric layer121, gate electrode122and hard mask layer123are applicable to the corresponding gate dielectric layer131, gate electrode132and hard mask layer133. In at least one embodiment, the gate dielectric layers131of the gate structures130H and130L have the same dielectric material of the same thickness which is thinner than the gate dielectric layer121of the I/O device, resulting in the corresponding core devices having a faster speed and/or a lower nominal operating voltage than the I/O device.

In some embodiments, the regions of the core device region114outside the gate structures130H and130L are doped to form LDD regions (not indicated in the figures). One or more of the described materials of and/or processes for forming the LDD regions125in the I/O device region113are applicable to the LDD regions in the core device region114.

Dummy spacers136are formed over sidewalls of the gate structures130H and130L. In some embodiments, the spacers136are formed after the formation of the LDD regions in the core device region114. In at least one embodiment, one or more of the described materials of and/or processes for forming the spacers126are applicable to the spacers136. A resulting structure100C is obtained upon formation of the gate structures130H and130L and the spacers126.

In the operation inFIG. 1D, a sacrificial layer140is formed over the structure100C, and covers the I/O device region113and the core device region114including the gate structures120,130H,130L formed thereover. In some embodiments, the sacrificial layer140includes SiN. Other materials are within the scope of various embodiments. A photoresist layer142is formed over the sacrificial layer140. The photoresist layer142covers the I/O device region113and the HVt device region115, without covering the LVt device region116. In at least one embodiment, at least one embedded flash cell is formed over the substrate110, and the sacrificial layer140and photoresist layer142cover the embedded flash cell. A resulting structure100D is obtained upon formation of the sacrificial layer140and the photoresist layer142.

In the operation inFIG. 1E, a stressor is formed in at least one of a source region or a drain region of the LVt device in the LVt device region116which is not covered by the photoresist layer142. The stressor is configured to enhance charge carrier mobility in the at least one source or drain region. For example, for a PMOS device, the stressor is configured to apply a compressive stress to enhance hole mobility in the at least one source or drain region of the PMOS device. For an NMOS device, the stressor is configured to apply a tensile stress to enhance electron mobility in the at least one source or drain region of the PMOS device. Examples of the stressor material include, but are not limited to, SiGe, SiC, GeSn, SiGeSn, and other suitable materials. In at least one embodiment, the stressor for a PMOS device comprises SiGe. In at least one embodiment, the stressor for an NMOS device comprises SiC.

In at least one embodiment, the stressor formation comprises an etching process and a deposition process. The etching process is performed to remove portions of the sacrificial layer140and the substrate110outside the gate structure130L and the isolation feature112to form recesses in the substrate110, corresponding source and drain regions of the LVt device. In some embodiments, the recesses are formed in the LDD regions125previously formed in the LVt device region116. The etching process comprises a dry etching process, a wet etching process, or combinations thereof.

In the deposition process, a semiconductor material is deposited in the recesses to form stressors144in the source and drain regions of the LVt device. In one or more embodiments, an epitaxial process (epitaxy) is performed to deposit the semiconductor material in the recesses. Examples of the epitaxial process include, but are not limited to, a selective epitaxy growth (SEG) process, CVD deposition techniques (e.g., vapor-phase epitaxy (VPE) and/or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, other suitable epitaxial processes, or combinations thereof. In one or more embodiments, the epitaxial process uses gaseous and/or liquid precursors, which interact with the composition of the substrate110.

The grown stressors144are raised above an upper surface of the substrate110and are higher than corresponding source and drain regions of the HVt device in the HVt device region115. In some embodiments, the stressors144are grown to have an upper surface flush with or lower than the upper surface of the substrate110. A resulting structure100E is obtained upon removal of the sacrificial layer140and the photoresist layer142.

In the operation inFIG. 1F, main spacers146are formed over the dummy spacers126,136. For example, the spacers146are formed by blanket depositing a dielectric layer over the structure100E, and then anisotropically etching to remove the dielectric layer to form the spacers146. The spacers146comprise a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, other suitable materials, or combinations thereof. In at least one embodiment, the dummy spacers126and/or136are removed before the formation of the main spacers146. For example, the dummy spacers126and/or136are removed by a wet etching using phosphoric acid or hydrofluoric acid, or by a dry etching using a suitable etchant.

The source and drain regions154,164H and164L are formed in the corresponding I/O device region113, HVt device region115and LVt device region116. For example, the source and drain regions154and164H are formed by doping the substrate110outside the corresponding gate structure120and gate structure130H, and the source and drain regions164L are formed by doping the stressors144outside the corresponding gate structure130L with dopants in an ion implantation process, a plasma immersion ion implantation (PIII) process, a gas and/or solid source diffusion process, other suitable process, or combinations thereof. A resulting semiconductor device100F comprises an I/O device159, a HVt device169H and a LVt device169L. The I/O device159comprises the gate structure120, the corresponding main spacers146over the sidewalls of the gate structure120, and the source and drain regions154all formed over the active region117in the I/O device region113. The HVt device169H comprises the gate structure130H, the corresponding main spacers146over the sidewalls of the gate structure130H, and the source and drain regions164H all formed over the active region118in the HVt device region115of the core device region114. The LVt device169L comprises the gate structure130L, the corresponding main spacers146over the sidewalls of the gate structure130L, and the source and drain regions164L with stressors144, all formed over the active region118in the LVt device region116of the core device region114.

In some embodiments, the semiconductor device100F further includes silicide features formed on the source and drain regions154,164H and/or164L to reduce electrical resistance with the contact. The silicide features are formed, for example, by depositing a metal layer, annealing the metal layer such that the metal layer reacts with silicon to form silicide, and then removing the non-reacted metal layer. In some embodiments, the semiconductor device100F further includes an inter-level dielectric (ILD) layer formed over the substrate110, and a chemical mechanical polishing (CMP) process is further applied to planarize the ILD layer. In some embodiments, the gate electrodes122and/or132remain polysilicon in a gate first process. In some embodiments, the polysilicon is removed and replaced with a metal in a gate last or gate replacement process. In a gate last process, the CMP process on the ILD layer is continued to expose the polysilicon of the gate structures120and/or130H and/or130L, and an etching process is performed to remove the polysilicon, thereby forming trenches. The trenches are filled with a proper work function metal (e.g., p-type work function metal and n-type work function metal) for corresponding p-type devices and n-type devices, respectively. In some embodiments, a multilayer interconnection (MLI) including metal layers and inter-metal dielectric (IMD) is formed over the semiconductor device100F to electrically connect various features or structures of the semiconductor device100F. The multilayer interconnection includes vertical interconnects, such as vias or contacts, and horizontal interconnects, such as metal lines. The various interconnection features may implement various conductive materials including copper, tungsten, silicide, and/or some metal alloys. In at least one example, a damascene process is used to form a copper multilayer interconnection structure and one or more metal alloys are deposited as a barrier for such a multilayer structure in the damascene process.

In the description herein, some embodiments include I/O devices and core devices. Such an arrangement is an example. Other arrangements are within the scope of various embodiments. For example, at least one embodiment, I/O devices and the corresponding I/O region are omitted. For another example, in at least one embodiment, the HVt device169H and the LVt device169L are not core devices.

In the semiconductor device100F in accordance with some embodiments, the HVt device169H has a higher threshold voltage than the LVt device169L, and the LVt device169L includes stressors144which are not formed in the HVt device169H. As a result, carrier mobility is higher in the LVt device169L than in the HVt device169H due to the presence of the stressors144, whereas leakage current, which is associated with carrier mobility, is lower in the HVt device169H due to the absence of stressors. Such an arrangement in at least one embodiment permits flexibility in circuit design with enhanced performance obtained at some devices, e.g., the LVt devices, and current leakage reduction provided at other devices, e.g., the HVt devices. Examples of applications where such an arrangement is advantageous include, but are not limited to, automotive and mobile applications where leakage current is a consideration. In another approach, implantation tuning is employed, but is insufficient to meet low leakage requirements in some applications. In a further approach, the gate length is increased to lower current leakage at the expense of increased die area. Compared to the other approaches, semiconductor devices in accordance with one or more embodiments have leakage current reduced to a level sufficient to meet low leakage requirements in some applications, without increasing the device size and/or chip area.

FIG. 2is a flow chart of a method200of manufacturing a semiconductor device in accordance with some embodiments.

At an operation210, isolation features, active regions, and a gate structure for an I/O device are formed over a semiconductor substrate. For example, isolation features111,112, active regions117,118, and a gate structure120for an I/O device are formed over a semiconductor substrate110, as described with respect toFIG. 1A.

At an operation220, a first threshold voltage of a first core device is adjusted to be higher than a second threshold voltage of a second core device. For example, the threshold voltage of a first core device to be formed over the active region118in the HVt device region115is adjusted to be higher than the threshold voltage of a second core device to be formed over the active region118in LVt device region116. An example threshold voltage adjustment includes ion implantation, as described with respect toFIG. 1B.

At an operation230, first and second gate structures for the first and second core devices are formed over the semiconductor substrate. For example, gate structures130H and130L for the corresponding HVt device and LVt device are formed over the substrate110in the corresponding active regions118, as described with respect toFIG. 1C.

At an operation240, stressors are formed in source and drain regions of the second core device, without forming stressors in source and drain regions of the first core device. For example, stressors144are formed in source and drain regions of the LVt device, without forming stressors in source and drain regions of the HVt device, as described with respect toFIGS. 1D-1E.

At an operation250, spacers and source and drain regions of the I/O device and the core devices are formed. For example, spacers146and source and drain regions154,164H and164L of the corresponding I/O device159, HVt device169H and LVt device169L are formed, as described with respect toFIG. 1F.

The method described herein in accordance with some embodiments is useful for manufacturing semiconductor devices using technology nodes at 40 nm and below. The method described herein in accordance with some embodiments is also useful for manufacturing semiconductor devices using technology nodes above 40 nm.

The described method shows example operations, but they are not necessarily required to be performed in the order shown. Operations may be added, replaced, changed order, and/or eliminated as appropriate, in accordance with the spirit and scope of embodiments of the disclosure. Embodiments that combine different features and/or different embodiments are within the scope of the disclosure and will be apparent to those of ordinary skill in the art after reviewing various embodiments.

FIG. 3is a diagram showing a mask generation operation300in a method of manufacturing a semiconductor device in accordance with some embodiments. The mask generation operation300is arranged to generate a mask for selectively forming stressors in some devices, e.g., LVt devices in the LVt device region116, but not in other devices, e.g., the HVt devices in the HVt device region115.

As shown inFIG. 3, a layout of the semiconductor device to be manufactured includes a HVt device region315for HVt devices, and a LVt device region316for LVt devices. In at least one embodiment, the HVt device region315and LVt device region316correspond to the HVt device region115and LVt device region116as described herein.

A mask372is used for an ion implantation to adjust a threshold voltage of the HVt devices to be higher than a threshold voltage of the LVt devices. For example, the mask372covers the HVt device region315and permits a patterned photoresist layer to be formed over the LVt device region316in a photolithography process using the mask372. As a result, the patterned photoresist layer covers the LVt device region316, without covering the HVt device region315, and permits an ion implantation to be performed in the HVt device region315, but not in the LVt device region316, for example, as described herein with respect toFIG. 1B.

A mask374is to be used in accordance with another approach to form stressors in both the HVt devices and the LVt devices. For example, the mask374covers the HVt device region315and the LVt device region316. The mask374permits a patterned photoresist layer formed in a photolithography process using the mask374to expose both the HVt device region315and the LVt device region316. As a result, the patterned photoresist layer permits stressors to be formed for both HVt devices and LVt devices in accordance with the another approach.

A mask376is obtained by performing at least one logic operation (LOP) on the mask372and the mask374. For example, an XOR operation is performed on the mask372and the mask374to obtain the mask376. Other LOPs, such as, AND, OR, NOT, NOR, NAND and bias (sizing) are within the scope of various embodiments. In at least one embodiment, more than one LOPs are performed to generate the mask376. The mask376covers the LVt device region316and permits a patterned photoresist layer, such as the photoresist layer142described with respect toFIG. 1D, to be formed over the HVt device region315in a photolithography process using the mask376. As a result, the patterned photoresist layer covers the HVt device region315, without covering the LVt device region316, and permits a stressor formation, such as an epitaxial growth described herein with respect toFIG. 1E, to be performed in the LVt device region316but not in the HVt device region315.

In at least one embodiment, the mask generation operation300is a simple modification to change a manufacturing process in accordance with another approach which forms stressors in all core devices to a manufacturing process in accordance with some embodiments which selectively form stressors in LVt devices, but not in HVt devices. As a result, one or more of the various advantages described herein with respect to some embodiments are obtainable with minimal changes to the manufacturing process of another approach. In some embodiments, the mask generation operation300is performed by one or more processors and/or application specific integrated circuits (ASICs).

As described herein, some embodiments form stressors in devices with lower threshold voltages, but not in devices with higher threshold voltages. As a result, enhanced carrier mobility and device performance are obtainable for the devices with lower threshold voltages. In the devices with higher threshold voltages, leakage current is reduced which is preferred in some applications, such as automotive and mobile applications. In at least one embodiment, reduced leakage current is obtainable in accordance with some embodiments by adding a simple LOP to a manufacturing process in accordance with another approach.

In some embodiments, a semiconductor device comprises a semiconductor substrate, and a first transistor and a second transistor over the semiconductor substrate. Both the first and second transistors are p-type transistors or both the first and second transistors are n-type transistors. The first and second transistors have the same nominal operating voltage. The first transistor has a higher threshold voltage than the second transistor. The second transistor has at least one of a source region or a drain region with higher charge carrier mobility than at least one of a source region or a drain region of the first transistor.

In some embodiments, a semiconductor device comprises a semiconductor substrate, and a first transistor and a second transistor over the semiconductor substrate. Both the first and second transistors are p-type transistors or both the first and second transistors are n-type transistors. The first and second transistors have corresponding first and second gate dielectric layers, the first and second gate dielectric layers comprising the same dielectric material and having the same thickness. A channel region of the first transistor and a channel region of the second transistor comprise different concentrations of a dopant. A source region and a drain region of the second transistor comprise a stressor, the stressor configured to apply a tensile stress or a compressive stress to the source region and the drain region of the second transistor. A source region and a drain region of the first transistor are free of the stressor.

In a method in accordance with some embodiments, first and second gate structures of corresponding first and second core devices are formed over a semiconductor substrate, and a stressor is formed in source and drain regions of the second core device, but not in source and drain regions of the first core device. Both the first and second core devices are p-type devices or both the first and second core devices are n-type devices.