Structures with thinned dielectric material

The disclosure relates to semiconductor structures and, more particularly, to structures with thinned dielectric material and methods of manufacture. The method includes depositing a high-k dielectric on a substrate. The method further includes depositing a titanium nitride film directly on the high-k while simultaneously etching the high-k dielectric.

FIELD OF THE INVENTION

The present disclosure relates to semiconductor structures and, more particularly, to structures with thinned dielectric material and methods of manufacture.

BACKGROUND

A trend in modern integrated circuit manufacture is to produce semiconductor devices, such as field effect transistors (FETs), which are as small as possible. In a typical FET, a source and a drain are formed in an active region of a semiconductor substrate by implanting or p-type impurities in the semiconductor material. Disposed between the source and the drain is a channel (or body) region. Disposed above the body region is a gate electrode. The gate electrode and the body are spaced apart by a gate dielectric layer.

Although the fabrication of smaller transistors allows more transistors to be placed on a single substrate for the formation relatively large circuit systems in a relatively small die area, this downscaling can result in the performance improvement but the degraded reliability. For example, the downscaling of n-channel field effect transistors (nFETs) and p-channel field effect transistors (pFETs) may result in a scaled inversion layer thickness (Tinv) being located between the gate metals and the semiconductor substrate to enhance the performance

In scaling of the devices, there remains a conflict to improve the reliability between nFET devices and pFET devices by adjusting dielectric thickness. For example, thinner dielectric material can improve the positive bias temperature instability (pBTI) reliability for nFET devices, whereas, thicker dielectric material can help the negative bias temperature instability (nBTI) reliability for pFET devices. However, it has been found to be difficult to make such adjustments using current technologies.

SUMMARY

In an aspect of the disclosure, a method includes depositing a high-k dielectric on a substrate. The method further includes depositing a titanium nitride film directly on the high-k while simultaneously etching the high-k dielectric.

In an aspect of the disclosure, a method includes depositing a high-k dielectric material on a pFET side and an nFET side of a substrate. The method further includes depositing titanium nitride (TiN) with a precursor of TiCl4directly on the high-k dielectric material on at least one of the pFET side and the nFET side of the substrate to thin the high-k dielectric material which contacts the TiCl4TiN

In an aspect of the disclosure, structure includes: an nFET device having a high-k dielectric material on a substrate; and a pFET device having the high-k dielectric material on the substrate. The high-k dielectric material of at least one of the nFET device and the pFET device includes Cl and is devoid of C.

DETAILED DESCRIPTION

The present disclosure relates to semiconductor structures and, more particularly, to structures with thinned dielectric material and methods of manufacture. More specifically, the present disclosure is directed to atomic (selective) etching of high-k dielectric material, e.g., HfO2, using high temperature TiCl4TiN for gate dielectric scaling of nFET and pFET devices. Advantageously, in embodiments, the methods described herein provide reliability improvements in scaled devices by, in one implementation, having thicker HfO2for improved pFET negative bias temperature instability (nBTI) and thinner HfO2for improved nFET positive bias temperature instability (pBTI).

In embodiments, atomic layer deposition (ALD) TiN is prepared using a TiCl4precursor at high temperature. By way of an example, HCl is a by-product of high temperature reaction between precursor TiCl4and precursor NH3during TiN deposition. High-k materials such as HfO2cannot be etched by wet HCl processes commonly used; however, the inventors have found that the HCl by-product of the TiCl4TiN deposition under certain conditions allows etching of a high-k film at atomic level control. Accordingly, TiCl4TiN can be used to thin the dielectric material, e.g., HfO2, in a controllable manner which allows further scaling of the devices and improved reliability. The approaches described herein can be performed either by selective or non-selective etching.

FIG. 1shows a structure and respective fabrication processing of nFET and pFET devices in accordance with aspects of the present disclosure. In embodiments, the structure5comprises a substrate10with a plurality of trenches12formed on an nFET side of the substrate10and a pFET side of the substrate10. In embodiments, the substrate10can be an oxide material or one or more dielectric materials. The structure5can be a planar structure or a finFET structure, as should be understood by those of ordinary skill in the art such that no further explanation is required.

In embodiments, trenches12are formed in the substrate10on both the nFET side and the pFET side. The trenches12can be formed by conventional lithography and etching (e.g., reactive ion etching (RIE) or wets) processes. More specifically, a resist is formed on the substrate10, and exposed to energy (light) to form a pattern (openings). A reactive ion etching (RIE) or wets is performed through the openings to form the trenches12. The resist can then be removed by oxygen ashing or other conventional stripants.

Still referring toFIG. 1, an interfacial material14is deposited on the substrate10and on surfaces within the trenches12. The interfacial material14can be an oxide material, e.g., SiO2. The interfacial material14can be formed by any conventional deposition process such as, e.g., chemical vapor deposition (CVD). A dielectric material16is formed on the interfacial material14. The dielectric material16is preferably a high-k dielectric material, e.g., hafnium based material (HfO2). The dielectric material16can be deposited by an atomic layer deposition (ALD) process; although other deposition processes are also contemplated by the present invention, e.g., CVD or plasma enhanced CVD (PECVD) processes. The dielectric material16can be deposited to a thickness of about 1.5 nm to about 3 nm; although other dimensions are also contemplated by the present invention. In embodiments, the dielectric material16can undergo a post deposition annealing process.

FIG. 1further shows a TiN layer18formed on the dielectric material16. In embodiments, the TiN layer18can include a metal organic (MO) precursor as should be understood by those of ordinary skill in the art. In embodiments, the TiN layer18is deposited to a thickness of about 20 Å to about 50 Å; although other dimensions are also contemplated by the present invention. A resist or mask20is formed over the TiN layer18, on the pFET side. More specifically, the resist or mask20is formed on the TiN layer18, over both the nFET and pFET. The resist20is exposed to energy (light) to form a pattern. As shown inFIG. 1, this pattern is an opening exposing the nFET side of the substrate, i.e., exposes the TiN layer18on the nFET side.

InFIG. 2, the TiN layer18on the nFET side is removed using a RIE or wets process. In embodiments, the removal of the TiN layer18will expose the underlying dielectric layer16on the nFET side of the substrate. It should be understood that the RIE or wets process is selective to the TiN layer18, and hence does not attack the dielectric layer16on the nFET side of the substrate. Following removal of the TiN layer18and the resist layer, a layer of TiN material22with a precursor is deposited at high temperature on the TiN layer18(on the pFET side) and the dielectric layer16(on the nFET side). In embodiments, the precursors are TiCl4and NH3, and the TiCl4TiN layer22(a.k.a. TiCl4TiN) can be deposited using an ALD or CVD process at a temperature of at or above about 300° C., and more preferably at higher temperature such as 450-500° C. In additional or alternative embodiments, the precursor can be a mixture precursor source of TiCl4and NH3. In embodiments a range of 0.1 g/min to 1.2 g/min for TiCl4and 1 slm to 10 slm for NH3can be used to etch HfO2in the given temperature range.

It has been found by the inventors that the deposition of the TiN layer22(a.k.a. TiCl4 TiN) will thin the underlying dielectric layer16on the nFET side of the substrate (i.e., atomic (selective) etching of high-k dielectric material). For example, the inventors have found that the TiN layer22(a.k.a. TiCl4 TiN) can etch approximately 3 Å from the underlying dielectric layer16on the nFET side of the substrate; whereas, the dielectric layer16on the pFET side will remain at its original deposited thickness as shown at the junction represented at reference numeral16a. More specifically, the dielectric layer16on the pFET side of the substrate remains protected by the TiN layer18and, hence, will not undergo a thinning process.

As shown inFIG. 3, the TiN layer22(a.k.a. TiCl4 TiN) and TiN layer18can be removed to expose the dielectric layer16on the pFET side and the nFET side. The structure can then undergo a conventional metal gate process, e.g., deposition of metal fill materials and patterning processes to form gate structures. In this way, a thicker dielectric material, e.g., HfO2, can be used for pFET nBTI, with a thinner dielectric material, e.g., HfO2, used for nFET pBTI.

FIG. 4shows an alternative structure and respective fabrication processes in accordance with additional aspects of the disclosure. In the structure5′ ofFIG. 4, the TiN layer22(a.k.a. TiCl4 TiN) will remain on the dielectric material16on both the nFET side and pFET side. Similar to that described with respect toFIGS. 1-3, though, the TiN layer22(a.k.a. TiCl4 TiN) (with precursor TiCl4and precursor NH3or a mixture of TiCl4and NH3precursor) can etch up to approximately 3 Å from the underlying dielectric layer16on the nFET side of the substrate; whereas, the dielectric layer16on the pFET side will remain at its original deposited thickness as shown at the junction represented at reference numeral16a(due to the protection afforded by layer18). An nFET metal stack30is then deposited on the TiN layer22(a.k.a. TiCl4 TiN). In embodiments, the nFET metal stack30can include one of TiAlC, TaAlC, TiAl, Ti and Al, followed by metal fill, e.g., TiN, tungsten, aluminum or other metal fills.

FIGS. 5a-5cshow alternative structures and respective fabrication processes in accordance with additional aspects of the disclosure. Similar to that described with respect toFIG. 1, in the structure5″ ofFIG. 5a, the interfacial material14, e.g., SiO2, is deposited on the substrate10, and within the trenches12. The dielectric material16is formed on the interfacial material14. The dielectric material16is preferably a high-k dielectric material, e.g., HFO2, deposited by an atomic layer deposition (ALD) process to a thickness of about 1.5 nm to about 3 nm (as represented by “y”). In embodiments, the dielectric material16can undergo a post deposition annealing process.

As shown inFIG. 5b, TiN layer22(a.k.a. TiCl4 TiN) (with precursor TiCl4and precursor NH3or a mixtured TiCl4and NH3precursor) is deposited at high temperature on the dielectric material16on both the nFET side and pFET side. Similar to that described with respect toFIGS. 1-3, the TiN layer22(a.k.a. TiCl4 TiN) (with precursor TiCl4and precursor NH3or a mixture of TiCl4and NH3precursor) can selectively atomic etch up to approximately 3 Å from the underlying dielectric layer16to a thinned dimension as represented by “x” (where x<y). In embodiments, the etching can be greater than 3 Å, depending on the nucleation time of TiN. Once the uniform TiN is formed on the dielectric layer16, e.g., HfO2, the etch will be stopped. As the TiN layer22(a.k.a. TiCl4 TiN) is deposited on both the nFET side and the pFET side, the dielectric layer16will now be thinned on both sides of the device as representatively shown inFIGS. 5band 5cby reference “x”. InFIG. 5c, the TiN layer is removed using a conventional etching process. A metal fill process can then follow for the formation of nFET and pFET gate stacks.

FIG. 6shows a structure with a different polarity as compared to the structure shown inFIGS. 1-3. In particular, the structure5″′ ofFIG. 6shows a thinning of the dielectric material16on the pFET side of the substrate (i.e., atomic (selective) etching of high-k dielectric material16). To this end, it should be understood that pFET leakage is much lower than nFET leakage due to band gap offset of the HfO2. Accordingly, if pFET reliability is not an issue, the thickness of the dielectric material (e.g., HfO2) on the pFET side of the substrate can be thinned to provide improved scaling in accordance with aspects of the present disclosure.

More specifically and similar to that shown and described inFIG. 1, interfacial material14, e.g., SiO2, is deposited on the substrate10and within the trenches12. The dielectric material16is formed on the interfacial material14. The dielectric material16is preferably a high-k dielectric material, e.g., HfO2, deposited by ALD processes; although other deposition processes are also contemplated by the present invention, e.g., CVD or PECVD processes. The dielectric material16can be deposited to a thickness of about 1.5 nm to about 3 nm; although other dimensions are also contemplated by the present invention. In embodiments, the dielectric material16can undergo a post deposition annealing process.

Still referring toFIG. 6, a barrier layer18, e.g., MO TiN or PVD TiN, is formed on the dielectric material16, followed by nFET metals, e.g., a layer30(e.g., TiAlC, TaAlC, TiAl, Ti and Al), and a capping layer32, e.g., TiN layer. The layers18,30and32can be deposited by conventional deposition processes, e.g., ALD. In embodiments, the layer18can be deposited to a thickness of about 10 Å or less, the layer30can be deposited to a thickness of about 20 Å to 100 Å and the layer32can be deposited to a thickness of about 1.5 nm to 3 nm; although other dimensions are contemplated herein. After deposition, the layers18,30and32can be patterned, e.g., removed from the pFET side of the substrate, by conventional lithography and etching (RIE) processes. The patterning process will expose the dielectric material16on the pFET side of the substrate.

Following removal of the layers18,30,32on the pFET side, a layer of TiN layer22(a.k.a. TiCl4 TiN) with precursors (e.g., precursor TiCl4and precursor NH3or a mixture of TiCl4and NH3precursor) is deposited at high temperature on the capping layer32on the nFET side and the dielectric layer16on the pFET side of the substrate. As previously described, the precursor for the TiN layer22(a.k.a. TiCl4 TiN) is a high temperature TiCl4, and the TiCl4TiN layer22(a.k.a. TiCl4 TiN) can be deposited using an ALD or CVD process at a temperature of at or above about 350° C., and more preferably at or about 390° C., and more preferably about 450° C. In additional or alternative embodiments, the precursor can be a mixtured precursor of TiCl4and NH3.

As already described herein, it has been found by the inventors that the TiN layer22(a.k.a. TiCl4 TiN) will thin (i.e., atomically etch) the underlying dielectric layer16, which in this embodiment will be on the pFET side of the substrate. For example, the inventors have found that the TiN layer22(a.k.a. TiCl4 TiN) can etch approximately 3 Å from the underlying dielectric layer16on the pFET side of the substrate; whereas, the dielectric layer16on the nFET side will remain at its original deposited thickness as shown at the junction represented by reference numeral16a. The processes can continue with a metal fill process after the removal of the TiN layer22(a.k.a. TiCl4 TiN).

As discovered by the inventors, in each of the embodiments using the processes described herein, e.g., TiN layer22(a.k.a. TiCl4 TiN), Cl can be found contained in the deposited TiN film and dielectric material16but with no C. In comparison, in conventional processes using MO TiN with a precursor of NH3, C can be found contained in the deposited TiN and the dielectric material16. In a further comparison with a conventional PVD TiN with a Ti target and N2gas precursor, Cl, C, or O cannot be found in the deposited TiN and C cannot be found in the underlying dielectric material. Accordingly, the structures described herein can be distinguished from a compositional standpoint by noting whether Cl and C can be found in the TiN or C can be found in the underlying dielectric material. In embodiments, the high-k material may act as a gate material for a transistor of a semiconductor device.

More specifically,FIG. 7shows Cl concentration in the deposited TiCl4 TiN, when implementing the processes as described in the present disclosure. As shown inFIG. 7, concentration of Cl is shown to be reduced at deposition temperatures of between 300° C. to 450° C.

FIG. 8shows a graph comparing dielectric thickness, post deposition of MO TiN and TiCl4TiN deposited at high temperature in accordance with aspects of the disclosure. As shown from this graph, dielectric thickness loss (i.e., thickness) after deposition of the high temperature TiCl4TiN was about 2.5 Å, compared to no thickness loss of dielectric material for MO TiN.

FIG. 9shows a graph comparing dielectric loss (thickness loss) versus deposition temperature of TiCl4TiN. In this graph, the y-axis represents loss of dielectric material, e.g., HfO2, and the x-axis represents deposition temperature of TiCl4TiN. As shown in this graph, dielectric loss increases with deposition temperature. For example, dielectric loss of about 1 Å occurs at a deposition temperature of about 390° C.; whereas, dielectric loss of about 3.0 Å occurs at a deposition temperature of about 450° C.