Display panel and display device

A display panel and a display device are disclosed. The display panel comprises an array substrate and spacers; the array substrate comprises a first substrate, gate lines, data lines, and multiple sub-pixel units; the first substrate is provided with multiple sub-pixel regions, first wiring regions each located between two adjacent rows of sub-pixel regions, and second wiring regions each located between two adjacent columns of sub-pixel regions and intersecting the first wiring regions; at least part of each sub-pixel unit is located on a sub-pixel region; the gate lines and the data lines are respectively located on the first wiring regions and the second wiring regions and are electrically connected to the sub-pixel units; the data lines and the gate lines are insulated from each other and intersect each other; each data line is provided with an alignment part.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present disclosure is a national phase application under 35 U.S.C. § 371 of International Application No. PCT/CN2021/079911 filed on Mar. 10, 2021, which claims the benefit of and priority to Chinese Patent Application No. 202010291154.6, entitled “Display Panel and Display Device” filed on Apr. 14, 2020, where the contents of both which are hereby incorporated by reference in their entireties herein.

TECHNICAL FIELD

The present disclosure relates to the field of display technology and, in particular, to a display panel and a display device.

BACKGROUND

With the continuous development of liquid-crystal display (LCD) panels, high-resolution products are constantly being developed. However, with the increase of pixels, it is prone to generating a series of problems. For example, when certain pressure tests are performed on the LCD panels, the color film substrate will slide relative to the array substrate, which causes the spacer on the color filter substrate to scratch the alignment (PI) film of the array substrate, causing abnormal liquid crystal alignment and uncontrollable light leakage, which affects the display effect.

It should be noted that the information disclosed in the above BACKGROUND is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to those of ordinary skill in the art.

SUMMARY

The purpose of the present disclosure is to provide a display panel and a display device.

According to an aspect of the present disclosure, there is provided a display panel, including:an array substrate; wherein the array substrate includes a first substrate, gate lines, data lines, and a plurality of sub-pixel units, the first substrate has a plurality of sub-pixel regions arranged in an array, first wiring regions each located between two adjacent rows of sub-pixel regions, and second wiring regions each located between two adjacent columns of sub-pixel regions, the first wiring regions intersect with the second wiring regions; at least part of each of the sub-pixel units is located on one of the sub-pixel regions; the gate lines are located on the first wiring regions and are electrically connected with the sub-pixel units; the data lines are located on the second wiring regions and are electrically connected with the sub-pixel units; the data lines and the gate lines are insulated from each other and orthographic projections of the data line and the gate line on the first substrate intersect with each other; the data line has an alignment part, and an orthographic projection of the alignment part on the first substrate is located in a region where the first wiring region and the second wiring region intersect; anda spacer, disposed on a side of the alignment part away from the array substrate, an orthographic projection of the spacer on the first substrate is located within an orthographic projection of the alignment part on the first substrate.

In an exemplary embodiment of the present disclosure, the data line further has main line parts located on opposite sides of the alignment part in a column direction, an orthographic projection of the main line part on the first substrate and an orthographic projections of the first wiring area on the first substrate do not overlap, and a size of the main line part in a row direction is smaller than that of the alignment part in the row direction.

In an exemplary embodiment of the present disclosure, in a direction from a side of the alignment part close to the main line part to a center of the alignment part, the size of the alignment part in the row direction gradually increases.

In an exemplary embodiment of the present disclosure, a distance between an edge of the orthographic projection of the spacer on the first substrate and an edge of the orthographic projection of the alignment part on the first substrate is a first distance,wherein, a ratio between the first distance and the size of the main line part of the data line in the row direction is 50% to 100%.

In an exemplary embodiment of the present disclosure, two gate lines are provided on the first wiring area, and each of the gate lines is electrically connected to at least part of the sub-pixel units in an adjacent row of the sub-pixel units;the orthographic projection of the alignment part on the first substrate is located between orthographic projections of the two gate lines on the first substrate.

In an exemplary embodiment of the present disclosure, barrier walls located on opposite sides of the spacer in the column direction are further provided on the first substrate;a distance between the barrier wall and the spacer is a second distance;wherein, a ratio between the second distance and the size of the main line part of the data line in the row direction is 2.5 to 8.

In an exemplary embodiment of the present disclosure, the data line further has a transition part located between the main line part and the alignment part; orthographic projections of the transition part and the gate line on the first substrate overlap, and an overlapping position is defined as a blocking position;the barrier wall includes a portion of the transition part located at the blocking position and a portion of the gate line located at the blocking position.

In an exemplary embodiment of the present disclosure, the alignment part is electrically connected with two adjacent columns of sub-pixel units.

In an exemplary embodiment of the present disclosure, the display panel further includes a color filter substrate, wherein the color filter substrate includes a second substrate located on a side of the spacer away from the array substrate and a shielding layer located on a side of the second substrate close to the array substrate, and the shielding layer has an intersecting shielding part, first shielding parts located on opposite sides of the intersecting shielding part in the row direction, and second shielding parts located on opposite sides of the intersecting shielding part in the column direction; wherein,an orthographic projection of the intersecting shielding part on the first substrate at least covers an intersection area of the first wiring area and the second wiring area, and an orthographic projection of the first shielding part on the first substrate at least covers the first wiring area and does not overlap with the second wiring area, and an orthographic projection of the second shielding part on the first substrate at least covers the second wiring area and does not overlap with the first wiring area;a size of the intersecting shielding part in the column direction is larger than that of the first shielding part in the column direction, and a size of the intersecting shielding part in the row direction is larger than that of the second shielding part in the row direction.

In an exemplary embodiment of the present disclosure, an orthographic projection of the spacer on the second substrate is located in a central area of an orthographic projection of the intersecting shielding part on the second substrate,a distance between an edge of the orthographic projection of the spacer on the first substrate and an edge of the orthographic projection of the intersecting shielding part on the first substrate is a third distance;wherein, a ratio between the third distance and the size of the main line part of the data line in the row direction is 6.5 to 12.

In an exemplary embodiment of the present disclosure, the shielding layer further has a transition shielding part located between the intersecting shielding part and the first shielding part; opposite end faces between the transition shielding part and the first shielding part completely overlap, and opposite end faces between the transition shielding part and the intersecting shielding part completely overlap.

According to an aspect of the present disclosure, there is provided a display device, including the display panel according to any one of the above.

DETAILED DESCRIPTION

In the following, the technical solutions of the present disclosure will be further described in detail through the embodiments and in conjunction with the accompanying drawings. In the specification, the same or similar reference numerals indicate the same or similar parts. The following description of the embodiments of the present disclosure with reference to the accompanying drawings is intended to explain the general inventive concept of the present disclosure, and should not be construed as a limitation to the present disclosure.

In addition, in the following detailed description, for the convenience of explanation, many specific details are set forth to provide a comprehensive understanding of the embodiments of the present disclosure. However, it is apparent that one or more embodiments can also be implemented without these specific details.

It should be noted that the “on . . . ”, “formed on . . . ”, and “disposed on . . . ” in this disclosure can mean that one layer is directly formed or disposed on another layer, or it can also mean that a layer is indirectly formed or disposed on another layer, that is, there are other layers between the two layers.

The terms “a”, “an”, “the”, “said”, and “at least one” are used to indicate the presence of one or more elements/components/etc.; the terms “including” and “having” are used to indicate open-ended inclusive meaning and means that there may be additional elements/components/etc. in addition to the listed elements/components/etc.

It should be noted that although the terms “first”, “second”, etc. may be used herein to describe various parts, components, elements, regions, layers and/or sections, these parts, components, elements, regions, and layers and/or sections should not be limited by these terms. Rather, these terms are used to distinguish one part, member, element, region, layer, and/or section from another part, member, element, region, layer, and/or section.

In the present disclosure, unless otherwise specified, the adopted term “arranged in the same layer” means that two layers, parts, components, elements, or sections can be formed by the same patterning process, and the two layers, parts, components, elements, or sections are generally formed of the same material.

In the present disclosure, unless otherwise specified, the expression “patterning process” generally includes steps of photoresist coating, exposure, development, etching, and photoresist stripping. The expression “one-time patterning process” means a process of forming patterned layers, parts, components, etc., using one mask.

An embodiment of the present disclosure provides a display panel, which may be a liquid crystal display panel. As shown inFIG.1, the display panel may include an array substrate1and a spacer3. In addition, the display panel may also include a color filter substrate2, where the color filter substrate2is located on a side of the spacer3away from the array substrate1. In other words, the spacer3can be located between the color filter substrate2and the array substrate1to support the color filter substrate2and the array substrate1, and the liquid crystals4can be located in the space supported by the spacer3.

As shown inFIGS.2and4to6, the array substrate1may include a first substrate10, data lines11, gate lines12, and a plurality of sub-pixel units13formed on the first substrate10. Specifically, the first substrate10has a plurality of sub-pixel regions10aarranged in an array, first wiring regions10beach located between two adjacent rows of sub-pixel regions10a, and second wiring regions10ceach located between two adjacent columns of sub-pixel regions10a. The first wiring regions10bintersect with the second wiring regions10c; at least part of each of the sub-pixel units13is located on one of the sub-pixel regions10a; the gate lines12are located on the first wiring regions10band are electrically connected with the sub-pixel units13; the data lines11are located on the second wiring regions10cand are electrically connected with the sub-pixel units13; and the data lines11and the gate lines12are insulated from each other and orthographic projections of the data line11and the gate line12on the first substrate10intersect with each other. Specifically, the orthographic projections of the data line11and the gate line12on the first substrate10intersect in the area where the first wiring area10band the second wiring area10cintersect. It should be understood that the extension directions of the data line11and the gate line12are different. Specifically, the data line11extends in the column direction Y, and the gate line12extends in the row direction X. The data line11has an alignment part110, and an orthographic projection of the alignment part110on the first substrate10is located in a region where the first wiring region10band the second wiring region10cintersect.

It should be understood that the first substrate10is mainly used to form structures such as sub-pixel units13, gate lines12, and data lines11, or the like, thereon. In order to facilitate processing these structures to a specific area on the first substrate10, regions corresponding to these structures may be divided on the first substrate10first. For example, the sub-pixel region10a, the first wiring region10b, and the second wiring region10ccan be divided on the first substrate10first, and then the sub-pixel unit13is formed on the sub-pixel region10aof the first substrate10, at least the gate lines12are formed on the first wiring region10b, and at least the data lines11are formed on the second wiring region10c. There may be also a plurality of first wiring areas10band second wiring areas10c; in addition, the first substrate10may also be provided with other wiring areas besides the first wiring area10band the second wiring area10c, it depends on the specific situation.

As shown inFIGS.2and4to6, the spacer3is disposed on a side of the alignment part110of the data line11away from the array substrate1, and an orthographic projection of the spacer3on the first substrate10is located within an orthographic projection of the alignment part110on the first substrate10. That is, an outer contour of the orthographic projection of the spacer3on the first substrate10is located inside an outer contour of the orthographic projection of the alignment part110on the first substrate10, to ensure that the spacer3is stably supported on the array substrate1.

As shown inFIGS.2,4to6, the color filter substrate2may include a second substrate20and a shielding layer22. The second substrate20is located on the side of the spacer3away from the array substrate1, and the shielding layer22is located on a side of the second substrate200close to array substrate.

As shown inFIGS.5aand7, the shielding layer22has an intersecting shielding part222, first shielding parts220located on opposite sides of the intersecting shielding part222in the row direction X, and second shielding parts221located on opposite sides of the intersecting shielding part222in the column direction Y. As shown inFIGS.4and5a, an orthographic projection of the intersecting shielding part222on the first substrate10at least covers an intersection area of the first wiring area10band the second wiring area10c, and an orthographic projection of the first shielding part220on the first substrate10at least covers the first wiring area10band does not overlap with the second wiring area10c, and an orthographic projection of the second shielding part221on the first substrate10at least covers the second wiring area10cand does not overlap with the first wiring area10b.

The first shielding part220, the second shielding part221, and the intersecting shielding part222in the shielding layer22may be arranged in an array. As shown inFIGS.4,5aand7, the first shielding part220, the second shielding part221and the intersecting shielding part222arranged in an array may enclose a light-transmitting hole224, an orthographic projection of the light-transmitting hole224on the first substrate is located in the sub-pixel region10a, and the light-transmitting hole224is used to allow light to pass through. When the entire area of the display panel is constant, the larger the total area of the light-transmitting holes224is, that is, the smaller the total area of the shielding part is, the higher the light transmittance of the display panel is, and the better the display effect will be.

It should be noted that in order to ensure that the shielding layer22can completely cover the wiring area on the array substrate1, the orthographic projections of the first shielding part220, the second shielding part221and the intersecting shielding part222in the shielding layer22on the first substrate can also be made to cover a part of the sub-pixel regions10a, as shown inFIG.4.

In the embodiment of the present disclosure, by disposing the spacer3on the alignment part110in the intersection area of the first wiring area10band the second wiring area10cin the data line11, when the spacer3moves in the row direction X and the column direction Y, the scratches formed on the alignment film layer17will also be shielded by the first shielding part220, the second shielding part221and the intersecting shielding part222which shield the first wiring area10band the second wiring area10c. This design can alleviate the situation that the spacer3slips out of the original light-shielding range during the pressure test, thereby alleviating the light leakage that easily occurs, and then improving the display effect.

It should be understood that even if the spacer3slides in other directions (that is, directions other than the row direction X and the column direction Y) during the pressure test, since the spacer3in the embodiment of the present disclosure is located on the alignment part110in the intersection area of the first wiring area10band the second wiring area10cin the data line11, compared with the scheme of the related art shown inFIG.8that the spacer3is arranged on the gate line12between two adjacent sub-pixel units13in the same column which also aims to ensure that the scratches generated during the movement of the spacer3can be completely covered, the increased area of the shielding part in the embodiment of the present disclosure is much smaller than the increased area of the shielding part in the related art.

Specifically, as shown inFIGS.5a,7,9a, and9b, the area enclosed by the S frame inFIGS.7and9bis the moving area of the spacer3, and the distance that the spacer3moves to the surroundings in this related technical solution is the same as the distance that the spacer3moves to the surroundings in the solution described in the embodiment of the present disclosure. In order to ensure that the scratches generated during the movement of the spacer3can be completely shielded by the shielding layer22, both the areas of the shielding part of the shielding layer22in the technical solutions in the related art and in the embodiments of the present disclosure are increased. In the embodiment, the sum of the areas of Q1, Q2, Q3, and Q4inFIG.7is the increased area of the shielding part in the embodiment of the present disclosure. The area of Q inFIG.9bis the increased area of the shielding part in the related art. The area of Q is greater than the sum of areas of Q1, Q2, Q3and Q4. Therefore, the loss of aperture ratio caused in the embodiment of the present disclosure is significantly less than the loss in the related technical solution.

That is to say, compared with the scheme of the related art shown inFIG.8that the spacer3is arranged on the gate line12between two adjacent sub-pixel units13in the same column, the solution of the embodiment of the present disclosure may also increase the pixel aperture ratio, while ensuring that the scratches generated during the movement of the spacer3can be completely shielded by the shielding layer22. The pixel aperture ratio refers to the ratio between the total area of the light-transmitting holes224in the shielding layer22and the entire area of the display panel.

For example, as for a 55-inch UHD (Ultra High Definition) display product, when the distance that the spacer3moves to the surroundings during the stress test is 40 μm to 60 μm, and when the width of the sub-pixel unit13is 105 um and the length thereof is 315 um, when the scheme of the related technology is adopted, the aperture ratio is 56.9%; when the scheme described in the embodiment of the present disclosure is adopted, the aperture ratio is 60.9%. Compared with the scheme of the related technology, the absolute value of the aperture ratio is increased by 4% and the relative value thereof is increased by approximately 10.7% in the scheme described in the embodiment of the present disclosure.

It should be noted that the bold dashed line, single-dotted line, double-dotted line inFIG.7and the bold dashed line and double-dotted line inFIG.9bdo not have practical meanings. It is only for facilitating those skilled in the art to understand the positions corresponding to each part of the shielding layer22and the moving range of the spacer3.

In addition, as shown inFIG.6, since the data line11is usually closer to the spacer3than the gate line12, for example, the data line11is usually arranged in the same layer as the source and drain electrodes of the thin film transistor in the array substrate1, and the gate line12is usually arranged in the same layer as the gate electrode of the thin film transistor in the array substrate1, in the embodiment of the present disclosure, the spacer3is adopted to align with the data line11, that is, the spacer3is arranged above the data line11. Compared with the solution in the related art in which the spacer3is arranged above the gate line12, the alignment accuracy can be improved, thereby ensuring the assembly yield of the display panel.

The display panel described in the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

In some embodiments, as shown inFIG.6, the first substrate10in the array substrate1may have a single-layer structure, and the material of the first substrate10may be glass. But it is not limited to this, the first substrate10may also have a multilayer structure; and the material of the first substrate10is not limited to glass, and may also be other materials, such as polyimide and other materials, depending on the specific situation.

As shown inFIGS.2to6, the sub-pixel unit13may include a common electrode130, a pixel electrode131, and a thin film transistor132. The thin film transistor132may include a gate electrode1320, an active layer1321, a source electrode1322, and a drain electrode1323. As shown inFIGS.2,3, and5b, the gate electrode1320may belong to a part of the gate line12, but it is not limited to this. The gate electrode1320may also be arranged independently of the gate line12, and the gate electrode1320of the thin film transistor132may be arranged in the same layer as the gate line12. It should be noted that there may be a plurality of thin film transistors132in the sub-pixel unit13, and the sub-pixel unit13may also include a capacitor structure, which is not shown in the figure.

In addition, it should be understood that, as shown inFIG.6, a first insulating layer15may be further provided between the gate electrode1320and the active layer1321, to insulate the gate electrode1320and the active layer1321from each other. The first insulating layer15may be made of inorganic materials, for example, silicon oxide, silicon nitride and other inorganic materials.

The thin film transistor132may be a top gate type or a bottom gate type. In the embodiments of the present disclosure, the thin film transistor132of a bottom-gate type is taken as an example for description. As shown inFIGS.5band6, when the thin film transistor132is of a bottom gate type, the gate electrode1320is formed on the first substrate10. The gate electrode1320may include metal materials or alloy materials, such as molybdenum, aluminum, and titanium, etc., in order to ensure its good electrical conductivity; the first insulating layer15is formed on the first substrate10and covers the gate electrode1320, the first insulating layer15can be made of inorganic materials, such as silicon oxide, silicon nitride and other inorganic materials; the active layer1321is formed on the side of the first insulating layer15away from the first substrate10, the source electrode1322and the drain electrode1323are respectively connected to two doped regions of the active layer1321, the source electrode1322and the drain electrode1323may include a metal material or an alloy material, such as a metal single-layer or multi-layer structure formed of molybdenum, aluminum, titanium, etc., for example, the multi-layer structure is a multi-metal laminated layer, such as a three-layer metal laminated layer (Al/Ti/Al) of titanium, aluminum, and titanium, etc.

In order to ensure the light transmittance of the array substrate1, the common electrode130can be made of transparent materials such as ITO (Indium Tin Oxide), Indium Zinc Oxide (IZO), and Zinc Oxide (ZnO); that is, since the materials adopted by the common electrode130are different from those of the gate electrode1320, source electrode1322, drain electrode1323of the thin film transistor132, the common electrode130and the gate electrode1320, source electrode1322, drain electrode1323of the thin film transistor132can be manufactured by adopting different patterning processes.

For example, the common electrode130of this embodiment can be formed on the first substrate10before the gate electrode1320of the thin film transistor132is formed. That is to say, when the array substrate1is manufactured, the common electrode130is formed on a first substrate10by adopting a patterning process first, and then a gate electrode1320of the thin film transistor132is formed on the first substrate10by adopting another patterning process. It should be noted that although the common electrode130and the gate electrode1320are both formed on the first substrate10, the common electrode130and the gate electrode1320are disconnected from each other, that is, there is no electrical connection between the common electrode130and the gate electrode1320.

However, it should be understood that when the material of the gate electrode1320and the material of the common electrode130are the same, the gate electrode1320and the common electrode130can also be formed on the first substrate10at the same time by using one-time patterning process. In addition, the common electrode130may not only be formed on the first substrate10before the gate electrode1320of the thin film transistor132is formed, but also may be formed after the gate electrode1320of the thin film transistor132is formed, which depends on the specific situation.

Similarly, in order to ensure the light transmittance of the array substrate1, the pixel electrode131can also be made of transparent materials such as ITO (Indium Tin Oxide), Indium Zinc Oxide (IZO), and Zinc Oxide (ZnO), etc.; the pixel electrode131can be formed on the side of the source electrode1322, the drain electrode1323away from the first substrate10; as shown inFIGS.5band6, the pixel electrode131can be connected to the drain electrode1323. It should be understood that after the drain electrode1323and the drain electrode1323are formed, and before the pixel electrode131is formed, a second insulating layer16can further be formed. In order to realize the connection between the pixel electrode131and the drain electrode1323, a hole can be made on the second insulating layer16and the hole can expose the surface of the drain electrode1323, and the pixel electrode131can be electrically connected to the drain electrode1323through the hole.

For example, the pixel electrode131and the common electrode130may be oppositely designed in a direction perpendicular to the first substrate10. As shown inFIGS.2and4, the pixel electrode131may be a slit electrode, that is, a slit1310is provided on the electrode, while the common electrode130can be a plate electrode (that is, the electrode is a whole piece without slits). The electric field generated by the pixel electrode131and the electric field generated between the common electrodes130in the same plane form a multi-dimensional electric field, so that all the liquid crystal molecules between the electrodes and directly above the electrodes are deflected, which can improve the operating efficiency of the liquid crystal and increase the light transmission efficiency. But it is not limited to this, the pixel electrode131and the common electrode130can also be set as other structures, depending on the specific situation.

In addition, it should be noted that the positional relationship between the common electrode130and the pixel electrode131is not limited to being located on the same substrate as mentioned above, and they also may not be on the same substrate. For example, the pixel electrode131may be located on the array substrate1, while the common electrode130may be located on the color filter substrate2, depending on the specific situation.

As shown inFIGS.5band6, the data line11can be arranged in the same layer as the source electrode1322and the drain electrode1323of the thin film transistor132, and electrically connected to the source electrode1322, but it is not limited to this. The data line11can also be arranged in the same layer as other electrodes, depending on the specific situation. For example, the data line11may include metal materials or alloy materials, such as molybdenum, aluminum, titanium, etc., to ensure good electrical conductivity.

As shown inFIG.5b, in addition to the alignment part110, the data line11may also have main line parts111located on opposite sides of the alignment part110in the column direction Y, and the main line parts111are located between two adjacent columns of sub-pixel units13. As shown inFIGS.4and5b, the orthographic projection of the main line111on the first substrate10is located outside the intersection area of the first wiring area10band the second wiring area10c, that is, the orthographic projections of the main line part111and the first wiring area10bon the first substrate10do not overlap; wherein a size of the main line part111in a row direction X is smaller than that of the alignment part110in the row direction X.

In the embodiment of the present disclosure, the size of the alignment part110in the data line11in the row direction X is designed to be larger, such that the spacer3and the data line11can be aligned; the size of the main line part111in the data line11in the row direction X is designed to be smaller, such that the area covered by the shielding part can be reduced, thereby increasing the pixel aperture ratio.

In the embodiment, in a direction from the side of the alignment part110close to the main line part111to the center of the alignment part110, the size of the alignment part110in the row direction X gradually increases. This design ensures that the alignment part110has a sufficient area for alignment with the spacer3, and also avoids the area of the alignment part110too large, thereby affecting the arrangement of other structures. For example, the shape of the orthographic projection of the alignment part110on the first substrate10may be similar to a rhombus, an ellipse, or other polygons, etc., depending on the specific situation.

It should be noted that, in the column direction Y, the size of the main line part111of the data line11in the row direction X is basically unchanged.

Optionally, a distance between an edge of the orthographic projection of the spacer3on the first substrate10and an edge of the orthographic projection of the alignment part110on the first substrate10is a first distance, a ratio between the first distance and the size of the main line part111of the data line11in the row direction X is 50% to 100%; for example, the size of the main line part111of the data line11in the row direction X is 5 μm to 6 μm, and the distance (i.e., the first distance) between an edge of the orthographic projection of the spacer3on the first substrate10and an edge of the orthographic projection of the alignment part110on the first substrate10may be 3 μm to 5 μm, such as 3 μm, 4 μm, 5 μm, etc., to meet the requirements of alignment deviation. It should be noted that the distance between an edge of the orthographic projection of the spacer3on the first substrate10and an edge of the orthographic projection of the alignment part110on the first substrate10is not limited to 3 μm to 5 μm, and it may be more than 5 μm, etc., depending on the alignment deviation of the color filter substrate2and the array substrate1in the production line.

In addition, as shown inFIGS.4and5b, the data line11further has a transition part112located between the main line part111and the alignment part110, the orthographic projection of the transition part112on the first substrate10can be located on the intersection area of the first wiring area10band the second wiring area10c, but not limited to this, the orthographic projection of the portion of the transition part112on the first substrate10may also be located on the second wiring area10cand do not overlap with the first wiring area10b.

As shown inFIG.5b, the size of the transition part112in the row direction X may be slightly larger than the size of the main line part111in the row direction X, and smaller than the size of the alignment part110in the row direction X, but it is not limited to this. The size of the transition part112in the row direction X may also be equal to the size of the main line part111in the row direction X.

It should be noted that, as shown inFIGS.4and5b, the orthographic projection of the alignment part110of the data line11on the first substrate10and the orthographic projection of the gate line12located on the first wiring area10bon the first substrate10do not overlap, and the orthographic projection of the transition part112on the first substrate10overlaps with the orthographic projection of the gate line12located on the first wiring area10bon the first substrate10. Since the size of the transition part112in the row direction X is smaller than the size of the alignment part110in the row direction X, this design can reduce the overlapping area between the data line11and the gate line12, thereby reducing the capacitance between the gate line12and the data line11and then ensuring the performance of the array substrate1.

Since the area of the alignment part110is relatively large, as shown inFIG.5b, the alignment part110is electrically connected with the drain electrodes1323of the sub-pixel units13of two adjacent columns, so as to realize the electrical connection of the data line11and the sub-pixel units13of two adjacent columns. This design can reduce the difficulty of the process while ensuring the reliable electrical connection between the data line11and the sub-pixel units13of two adjacent columns.

In some embodiments, as shown inFIGS.2,4, and5b, two gate lines12may be provided on the first wiring area10bon the first substrate10; each gate line and at least part of the sub-pixel units13of its adjacent row are electrically connected.

In addition, as shown inFIGS.2,4, and5b, the first wiring area10bcan also be provided with a common line14. This common line14can be provided in the same layer as the gate line12, and is connected to the common electrode130of each sub-pixel unit13in a row of the sub-pixel units13, to realize the electrical connection between the common line14and the common electrode130.

It should be understood that, in order to facilitate the connection of the sub-pixel unit13with the data line11, the gate line12and the common line14, part of the sub-pixel units13may be located in the first wiring area10b, as shown inFIGS.2and4.

As shown inFIGS.2,4, and5b, when two gate lines12are provided in the first wiring area10b, the orthographic projection of the alignment part110of the data line11on the first substrate10is located between the orthographic projections of the two gate lines on the first substrate10, this design not only reduces the overlapping area between the data line11and the two gate lines12, but also makes the alignment part110of the data line11as close as possible to the center position of the intersection area of the first wiring area10band the second wiring area10c, that is, it ensures that the spacer3is as close as possible to the center position of the intersection area of the first wiring area10band the second wiring area10c, so as to prevent the spacer3from sliding out of the shielding range of the intersecting shielding part222during the pressure test.

In some embodiments, as shown inFIGS.5band6, when the spacer3is formed on the color filter substrate2, barrier walls18located on opposite sides of the spacer3in the column direction Y are further provided on the first substrate10, the surface of the barrier wall18that is far away from the first substrate10is farther from the first substrate10than the surface of the spacer3that is close to the first substrate10, and is closer to the first substrate10than the surface of the spacer3that is far away from the first substrate10. In the embodiment of the present disclosure, the sliding displacement of the spacer3in the column direction Y can be limited by setting the barrier wall18, so as to prevent the spacer3from sliding out of the shielded area during the pressure test.

It should be understood that the embodiments of the present disclosure are not limited to providing barrier walls18on opposite sides of the spacer3in the column direction Y, and barrier walls18may also be provided in the row direction X or other directions.

Optionally, a distance between the barrier wall18and the spacer3is a second distance, a ratio between the second distance and the size of the main line part111of the data line11in the row direction X is 2.5 to 8; for example, the size of the main line part111of the data line11in the row direction X is 5 μm to 6 μm; the distance (i.e., the second distance) between the barrier wall18and the spacer3can be 15 μm to 40 μm, for example, 15 μm, 20 μm, 25 μm, 30 μm, 35 μm, 40 μm. By designing the distance between the barrier wall18and the spacer3to be greater than or equal to 15 μm, it can avoid the situation that the barrier wall18cannot prevent the spacer3from sliding due to the excessively small distance; by designing the distance between the barrier wall18and the spacer3to be less than or equal to 40 μm, it can avoid that the setting of the barrier wall18becomes meaningless due to the excessively large distance.

In some embodiments, as shown inFIGS.5band6, orthographic projections of the transition part112of the data line11and the gate line12on the first substrate10overlap, and an overlapping position may be defined as a blocking position; wherein the barrier wall18may include a portion of the transition part112located at the blocking position and a portion of the gate line12located at the blocking position. That is, the barrier wall18of the embodiment of the present disclosure may be formed by a part where the data line11and the gate line12overlap, such design does not need to set the barrier wall18through other processes, which can reduce the processing cost.

As shown inFIGS.5band6, the orthographic projections of the transition part112of the data line11and the common line14on the first substrate10overlap, and the overlapping portion may also form the barrier wall18.

It should be understood that the data line11and the source electrode1322, the drain electrode1323of the thin film transistor132are arranged in the same layer, the gate line12, the common line14and the gate electrode1320of the thin film transistor132are arranged in the same layer, therefore, a first insulating layer15is also provided between the overlapping parts between the data line11, and the gate line12, the common line14, that is to say, in addition to the portion of the transition part112located at the blocking position and the portion of the gate line12(common line14) located at the blocking position, the retaining wall18may also include a portion of the first insulating layer15located at the blocking position; in addition, it may also include the portion of the second insulating layer16located at the blocking position.

In some embodiments, as shown inFIG.7, a size of the intersecting shielding part222of the shielding layer22in the color filter substrate2in the column direction Y is larger than that of the first shielding part220in the column direction Y, and a size of the intersecting shielding part222in the row direction X is larger than that of the second shielding part221in the row direction X; this design can prevent the spacer3from slipping out of the shielded area during the pressure test.

Optionally, as shown inFIG.7, an orthographic projection of the spacer3on the second substrate20is located in a central area of an orthographic projection of the intersecting shielding part222on the second substrate20, and a distance between an edge of the orthographic projection of the spacer3on the first substrate10and an edge of the orthographic projection of the intersecting shielding part222on the first substrate10is a third distance, a ratio between the third distance and the size of the main line part111of the data line11in the row direction X is 6.5 to 12; for example, the size of the main line part111of the data line11in the row direction X is 5 μm to 6 μm; the distance (i.e., the third distance) between an edge of the orthographic projection of the spacer3on the first substrate10and an edge of the orthographic projection of the intersecting shielding part222on the first substrate10may be 40 μm to 60 μm, such as 40 μm, 45 μm, 50 μm, 55 μm, 60 μm, etc., in order to prevent the spacer3from slipping out of the shielded area during the pressure test.

In the embodiment, the shielding layer22further has a transition shielding part223located between the intersecting shielding part222and the first shielding part220; in a direction from the first shielding part220to the intersecting shielding part222, the size of the transition shielding part223in the column direction Y gradually increases; wherein opposite end faces between the transition shielding part223and the first shielding part220completely overlap, and opposite end faces between the transition shielding part223and the intersecting shielding part222completely overlap; by providing the transition shielding part, while preventing the spacer3from sliding out of the shielded area during the stress test, the shielding area of the shielding layer22can also be reduced, thereby increasing the pixel aperture ratio.

The color filter substrate2can also be provided with a color filter layer21, the color filter layer21can be formed on the side of the shielding layer22away from the second substrate20, and the color filter layer21can include filter structures of red, green, blue, and other colors arranged in an array.

In some embodiments, the spacer3can be formed on the color filter substrate2first, and then the color filter substrate2and the array substrate1are aligned. However, it is not limited to this. The spacer3can also be formed on the array substrate1first, and then the color filter substrate2and the array substrate1are aligned.

There may be a plurality of spacers3, and the arrangement of the plurality of spacers3can improve the uniformity of the overall thickness of the display panel, increase the tolerance of the display panel to fluctuations of the liquid crystals4, and thereby improve the yield of the display panel. The plurality of spacers can include a main spacer and an auxiliary spacer. The main spacer can be a spacer3as shown inFIG.6. When the display panel does not receive external pressure, two ends of the main spacer can be in contact with the array substrate1and the color filter substrate2respectively, and mainly play a supporting role; while as for the auxiliary spacer (not shown in the figure), when the display panel does not receive external pressure, if the auxiliary spacer is formed on the color filter substrate2, there is a certain distance between the auxiliary spacer and the array substrate1, that is, there is a step difference (height difference) between the main spacer and the auxiliary spacer. By adjusting the step difference between the main spacer and the auxiliary spacer, the thickness of the display panel can be fine-tuned. For example, the height of the main spacer is greater than the height of the auxiliary spacer. When the display panel is subjected to external pressure, the main spacer bears all the pressure first and is compressed. When the main spacer is compressed to the situation when the step difference between the main spacer and the auxiliary spacer drops to 0, the main spacer and the auxiliary spacer can bear the external pressure together.

In addition, it should be noted that the position of the spacer3is selectively arranged, and it is not necessary for the spacer3to be arranged in each intersection area of the first wiring area10band the second wiring area10cin the array substrate1, in this way, the alignment part110is not provided at the each of the intersection area of the first wiring region10band the second wiring region10cin the data line, and the specific number and position of the spacer3can be determined according to actual requirements.

An embodiment of the present disclosure also provides a display device, which includes the display panel described in any of the foregoing embodiments. The display device may be a liquid crystal display device.

According to the embodiments of the present disclosure, the specific type of the display device is not particularly limited. The types of display devices commonly used in the field can be used, such as liquid crystal display screens, mobile devices such as mobile phones, laptop computers, wearable devices such as watches, and VR devices, etc., which can be selected by those skilled in the art according to the specific purpose of the display device, which will not be repeated herein.

It should be noted that in addition to the display panel, the display device also includes other necessary parts and components. Taking the display as an example, it may also include a backlight module, a housing, a main circuit board, power cords, etc., those skilled in the art can make corresponding supplements according to the specific use requirements of the display device, which will not be repeated herein.

Those skilled in the art will easily think of other embodiments of the present disclosure after considering the specification and practicing the disclosure disclosed herein. This disclosure is intended to cover any variations, uses, or adaptive changes of the present disclosure. These variations, uses, or adaptive changes follow the general principles of the present disclosure and include common knowledge or conventional technical means in the technical field that are not disclosed in the present disclosure. The description and the embodiments are only regarded as exemplary, and the true scope and spirit of the present disclosure are indicated by the appended claims.