CMOS image sensor

A CMOS image sensor includes a semiconductor substrate; a pinned photodiode formed in a light-sensing region of the semiconductor substrate, the pinned photodiode comprising a charge-accumulating diffusion region and a surface pinning diffusion region overlying the charge-accumulating diffusion region; a transfer transistor, wherein the transfer transistor has a transfer gate comprising a protruding first gate segment with a first gate dimension and a second gate segment with a second gate dimension that is smaller than the first gate dimension. A first overlapping portion between the protruding first gate segment and the charge-accumulating diffusion region is greater than a second overlapping portion between the second gate segment and the charge-accumulating diffusion region.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an image sensor and, more particularly, to a CMOS image sensor integrated with a pinned photodiode, which is capable of reducing clock feedthrough and improving dynamic range.

2. Description of the Prior Art

CMOS (complementary metal-oxide-semiconductor) image sensor or CMOS sensor is known in the art. Generally, a CMOS sensor includes a plurality of unit pixels having a light-sensing region and a peripheral circuit region. Each of the unit pixels also includes a light-sensing element such as a photodiode formed in the light-sensing region and a plurality of transistors formed on the peripheral circuit region. The photodiode senses incident light and accumulates image charges that are generated due to the incident light.

FIG. 1illustrates a layout of four-transistor (4T) pixel cell10of a conventional CMOS sensor.FIG. 2is a schematic, cross-sectional view of the CMOS sensor ofFIG. 1taken along line I-I′. The CMOS sensor pixel cell10includes a charge-accumulating region20in an underlying portion of the substrate. A pinned photodiode22is formed in the charge-accumulating region20. A transfer gate30is provided for transferring photoelectric charges generated in the charge-accumulating region20to a floating diffusion region (sensing node)25. The pinned photodiode is termed “pinned” because the potential in the photodiode is pinned to a constant value when the photodiode is fully depleted.

Typically, the floating diffusion region25is coupled to a gate34of a source follower transistor. The source follower transistor provides an output signal to a row select access transistor having a gate36. A reset transistor having a gate32resets the floating diffusion region25to a specified charge level before each charge transfer from the charge-accumulating region20. As best seen inFIG. 1, N-type doped source/drain regions27are provided on either side of the transistor gates32,34,36. The floating diffusion region25adjacent the transfer gate30is also N-type.

As best seen inFIG. 2, the charge-accumulating region20is formed as a pinned photodiode22, which has a PNP junction region consisting of a surface P+pinning layer24, an N-type photodiode region26and a P-type substrate12. The pinned photodiode22includes two P-type regions12,24so that the N-type photodiode region26is fully depleted at a pinning voltage. Trench isolation regions15are formed in the P-type substrate12adjacent the charge-accumulating region20. The trench isolation regions15are typically formed using a conventional shallow trench isolation (STI) process or by using a local oxidation of silicon (LOCOS) process.

CMOS sensors typically suffer from narrow dynamic range and poor charge transfer efficiency. As shown inFIG. 2, the overlapping portion between the gate30and the underlying N-type photodiode region26is designated as “A”. It has been known that in order to increase the charge transfer efficiency of the CMOS sensor, “A” should be made as large as possible. The distance between the surface P+pinning layer24and the P type substrate12underneath the gate30is designated as “B”. If the distance “B” is too small, pinch-off occurs resulting in narrow dynamic range and undesirable image lags.

A conventional non-self alignment method for forming the pixel sensor can provide larger overlapping portion “A” and distance “B”. According to the conventional non-self-alignment method, the N type photodiode region26is implanted into the pre-selected areas of the P-type substrate12using a photomask prior to the definition of the transfer gate30. However, the prior art non-self-aligned method suffers from so-called fixed pattern noise due to misalignment of the lithography and non-uniformity of the overlapping portion “A” among pixels.

Referring toFIG. 3, a schematic potential diagram of a CMOS sensor during operation is demonstrated. On the other hand, the above-described prior art CMOS sensor has another drawback in that a potential “pocket” indicated by numeral number 50 forms due to an excessively large overlapping portion “A”. The potential “pocket”50is caused by a large number of trapped electrons accumulated underneath the gate30, which leads to deteriorated clock feed-through of the gate30of the transfer transistor, image lag, and also poor dynamic range.

SUMMARY OF THE INVENTION

It is one object of the present invention to provide an improved CMOS image sensor integrated with a pinned photodiode, which is capable of reducing clock feedthrough, image lag, and improving dynamic range.

According to the claimed invention, a CMOS image sensor is disclosed. The CMOS image sensor includes a semiconductor substrate of a first conductivity type; a pinned photodiode formed in a light-sensing region of the semiconductor substrate, the pinned photodiode comprising a charge-accumulating diffusion region of a second conductivity type and a surface pinning diffusion region of the first conductivity type overlying the charge-accumulating diffusion region; and a transfer transistor formed on the semiconductor substrate, the transfer transistor being adjacent to the pinned photodiode, wherein the transfer transistor has a transfer gate comprising a protruding first gate segment with a first gate dimension and a second gate segment with a second gate dimension that is smaller than the first gate dimension; wherein a first overlapping portion between the protruding first gate segment and the charge-accumulating diffusion region being greater than a second overlapping portion between the second gate segment and the charge-accumulating diffusion region.

DETAILED DESCRIPTION

Please refer toFIGS. 4-6.FIG. 4is a top view of an exemplary four-transistor (4T) pixel cell of a CMOS sensor100according to one preferred embodiment of this invention; andFIGS. 5 and 6are schematic, cross-sectional diagrams taken along line II-II′ and line III-III′ ofFIG. 4, respectively, where like numeral numbers designate like elements, regions or layers.

As shown inFIG. 4, the CMOS sensor100comprises a charge-accumulating region20in an underlying portion of a substrate11. A pinned photodiode220is formed in the charge-accumulating region20. A transfer gate60is provided for transferring photoelectric charges generated in the charge-accumulating region20to a floating diffusion region (sensing node)25.

The floating diffusion region25is coupled to a gate34of a source follower transistor. The source follower transistor provides an output signal to a row select access transistor having a gate36. A reset transistor having a gate32resets the floating diffusion region25to a specified charge level before each charge transfer from the charge-accumulating region20.

According to the preferred embodiment, N-type doped source/drain regions27are provided on either side of the transistor gates32,34,36. The floating diffusion region25adjacent the transfer gate30is also preferably N-type.

As specifically indicated inFIG. 4, in accordance with the preferred embodiment of this invention, the transfer gate60includes a protruding first gate segment60awith a first gate dimension L1and a second gate segment60bwith a second gate dimension L2. According to the preferred embodiment, the first gate dimension L1is greater than the second gate dimension L2by an offset S (L1=L2+S). Preferably, the offset S is smaller than the second gate dimension L2. By way of example, the second gate dimension L2may range between 0.1 micrometer and 0.8 micrometer, and the offset S may range between 0.05 micrometer and 0.6 micrometer, but not limited thereto.

The protruding first gate segment60a, which juts out toward the light-sensing area20, has a width designated as W, which preferably ranges between 0.1 micrometer and 1.0 micrometer. Preferably, the protruding first gate segment60ais disposed approximately at the midpoint of the gate60.

As shown inFIGS. 5 and 6, the pinned photodiode220is formed in light-sensing region20of the semiconductor substrate11. The pinned photodiode220comprises an N-type charge-accumulating diffusion region226and a surface P+pinning layer224overlying the charge-accumulating diffusion region226, and a P−substrate14. The P−substrate14may be an P type epitaxial layer grown on a P+silicon substrate13.

Trench isolation regions15are formed in the P−substrate14adjacent the charge-accumulating region20. The trench isolation regions15are typically formed using a conventional shallow trench isolation (STI) process or by using a local oxidation of silicon (LOCOS) process.

Further, P wells28and29are formed in the P−substrate14. The P well28,which encompasses the floating diffusion25and the STI15, is situated under the gate60and is in contiguous with the N-type charge-accumulating diffusion region226. It is to be understood that the P well28is optional. The surface P+0pinning layer224is contiguous or merged with the P well29that encompasses the STI15.

It is one salient feature of the present invention that a first overlapping portion A1between the first gate segment60aand the charge-accumulating diffusion region226(shown inFIG. 5) is greater than a second overlapping portion A2between the second gate segment60band the charge-accumulating diffusion region226(shown inFIG. 6).

The advantages of the present invention are demonstrated inFIGS. 7-8.FIG. 7is a schematic potential diagram with respect to the photodiode structure set forth inFIG. 5.FIG. 8is a schematic potential diagram with respect to the photodiode structure set forth inFIG. 6. In operation, as seen inFIG. 8, a small overlapping portion A2between the second gate segment60band the charge-accumulating diffusion region226and short distance B2between the surface P+pinning layer224and the P well28lead to early pinch-off and a potential barrier formation.

The amount of the trapped electrons is reduced, thus preventing a potential “pocket” from occurring underneath the second gate segment60b. This helps to reduce clock feedthrough of the transfer gate60and also widen dynamic range. As seen inFIG. 7, a shrunk potential “pocket” merely occurs directly under the protruding first gate segment60a. When the charge-accumulating diffusion region226is depleted, electrons tend to transfer through underneath the protruding first gate segment60a. Since the overlapping portion A1between the first gate segment60aand the charge-accumulating diffusion region226and the distance B1between the pinning layer224and the P well28are both greater, no pinch-off occurs and thus no obvious barrier is formed.