LUT based synapse weight update scheme in STDP neuromorphic systems

A method and system are provided for updating synapse weight values in neuromorphic system with Spike Time Dependent Plasticity model. The method includes selectively performing, by a hardware-based synapse weight incrementer or decrementer, one of a synapse weight increment function or decrement function, each using a respective lookup table, to generate updated synapse weight values responsive to spike timing data. The method further includes storing the updated synapse weight values in a memory. The method additionally includes performing, by a hardware-based processor, a learning process to integrate the updated synapse weight values stored in the memory into the Spike Time Dependent Plasticity model neuromorphic system for improved neuromorphic simulation.

BACKGROUND

Technical Field

The present invention relates to neuromorphic systems and more particularly to updating synapse weight values in Spike Time Dependent Plasticity neuromorphic systems.

Description of Related Art

Neuromorphic systems with a Spike Time Dependent Plasticity (STDP) model are often simulated with software in which the system can be described in a simple mathematical model. This process, however, often takes a large amount of time to compute and, even with a simple model, is time-consuming.

Operations can be achieved much faster (approximately 103times or more) with the implementation of hardware. This implementation enables larger numbers of learning cycles to be computable within a practical operation timeframe and on a real-time on-system (i.e., an on-chip for a neuromorphic chip) learning.

One of the key steps needed to implement a chip with an on-chip self-learning function is the ability to implement a Synapse Weight (SW) update function. This SW update function requires a special scheme to implement the corresponding simple models in hardware because a biological synapse has a complicated function and its electrical model needs a large number of parameters to be able to emulate it.

In a conventional system, SW values of target synapses are calculated with a complicated software program functioning in the background and loaded into a system. For the STDP model, the difference of the spike arrival time from the pre-neuron and from the post-neuron is converted into an update amount of the SW values. However, such conventional schemes have drawbacks. Real-time on-system (on-chip) learning cannot be implemented using the conventional scheme because the time it takes to calculate and load the SW values is relatively long. Additionally, using the conventional scheme, the SW update resolution cannot be increased very much since the shape of the spike is a simple digital pulse, such as a square wave. Furthermore, using the conventional scheme, the software program for calculating the next SW values is so complicated that an end user cannot exploit it without learning special skills or know-how.

SUMMARY

According to an aspect of the present principles, a method for updating synapse weight values of a Spike Time Dependent Plasticity model in a neuromorphic system is provided. The method includes selectively performing, by a hardware-based synapse weight incrementer or decrementer, one of a synapse weight increment function or decrement function, each using a respective lookup table, to generate updated synapse weight values responsive to spike timing data. The method further includes storing the updated synapse weight values in a memory. The method additionally includes performing, by a hardware-based processor, a learning process to integrate the updated synapse weight values stored in the memory into the Spike Time Dependent Plasticity model neuromorphic system for improved neuromorphic simulation.

According to an aspect of the present principles, a system is provided for updating synapse weight values in a Spike Time Dependent Plasticity model. The system includes at least one of a hardware-based synapse weight incrementer and a hardware-based synapse weight decrementer, each respectively configured to perform either a synapse weight increment function or a synapse weight decrement function, using a respective lookup table, to generate updated synapse weight values in response to spike timing data. The system further includes a memory configured to store the updated synapse weight values. The system additionally includes a hardware-based processor configured to perform a learning process to integrate the updated synapse weight values stored in the memory into the Spike Time Dependent Plasticity model neuromorphic system for improved neuromorphic simulation.

DETAILED DESCRIPTION

Embodiments of the present invention implement a scheme to update Synapse Weight (SW) values in a Spike Time Dependent Plasticity (STDP) system using a precise and effective SW update function for a digital STDP neuromorphic system in hardware. The scheme implements an SW increment and decrement function with two independent blocks: a Synapse Weight Decrement (SWD) block; and a Synapse Weight Increment (SWI) block. The SWD and SWI blocks receive spike timing data and control signals in a special timing sequence to generate updated SW values from current SW values.

In an embodiment of the present principles, the scheme includes a Lookup Table (LUT) in both blocks. By introducing the LUT in both the SWI and SWD blocks, the next SW values can be calculated without a complicated calculation. The operation with the LUT increases the speed at the system in which complicated system behavior is implemented.

The scheme is based on a fully digital circuit, and can be implemented with a Field-Programmable Gate Array (FPGA) or a programmable logic device. Furthermore, LUTs can be updated flexibly for system parameter fitting.

According to the present principles, an SW update scheme based on the STDP model can be implemented with high accuracy. The SW update scheme can be implemented easily by loading data obtained from a hardware measurement into two (increment and decrement) LUTs. Furthermore, with this scheme, a developer does not have to analyze or understand a complicated synapse update algorithm.

In an embodiment of the present principles, a chip with an on-chip self-learning function is implemented. One of the key steps needed to implement a chip with an on-chip self-learning function is the ability to implement an SW update function. In an embodiment of the present principles, the system is able to implement such an SW update function.

Using the present scheme, performance can be free from Process, Voltage, and Temperature (PVT) variation and can achieve a good model hardware configuration, unlike when using an analog implementation. This enables a user to implement an accurate system quickly with reconfigurable logic, such as an FPGA.

Referring to the drawings in which like numerals represent the same or similar elements and initially toFIG. 1, a diagram of synapses130having a crossbar structure is shown.

In a typical neuromorphic system, a synapse130is connected between an axon110of a neuron (a pre-neuron) and a dendrite120of another neuron (a post-neuron). Thus, herein, axons110are shown horizontally and dendrites120are shown vertically in the crossbar structure. Each synapse130has its own SW value, which shows the strength of the connection. In the STDP model, the SW values are updated with the timing between (1) an axon110spike from the pre-neuron, and (2) a dendrite120spike from the post-neuron. In the present scheme, synapses130are assumed to have a crossbar structure. However, other types of synapse structures may be used in connection with the present principles. In a crossbar structure, the axons110and dendrites120are perpendicular to each other and the two110,120cross at the synapses130.

Referring now toFIG. 2, a block diagram of an exemplary neuromorphic system200is shown.

In this system200, synapse devices with a crossbar structure are implemented with SW Random Access Memory (RAM)210. In one example, there is a configuration with 256 neurons and 2562(65536) synapses. The number of neurons, however, can be any number and can be modified according to the target application. The SW data for these synapses is stored in the SW RAM210in, for example, 8 bit each. The raw and column of the SW RAM210correspond to the axon and neuron body (or dendrite), respectively. That is, in one example, the SW RAM (i, j)210(or SWi, j) (for i, j=0 to 255) shows the SW value of the synapse between axon i and dendrite j (or neuron body j).

Spike timing at the axon and at the dendrite (or neuron body) has to be monitored. This is due to the fact that the timing difference between the axon and the dendrite is one of the most important parameters in the STDP model. Thus, this scheme expects timing information for the axon spike and the dendrite spike to be obtained and monitored. One way to supply this information is to use an Axon Timer (AT)220and a Dendrite Timer (DT)230. These timers220,230provide elapsed times since a spike is given to the axon nodes and the dendrite nodes of the synapses, respectively. AT access signals, at_acs, and DT access signals, dt_acs, are activated when the ATs and DTs, respectively, are accessed for read. The lengths of the AT220and the DT230are, for example, in 4 bits. However, these lengths can be determined according to the target application. For example, the at_sel<0:7> are 8 bit AT selection signals which select one AT value which is used for the SWI out of the 256 ATs. Additionally, the dt_sel<0:7> are 8 bit DT selection signals which select one DT value which is used for the SWD out of the 256 DTs. The AT220and DT230work like a decrement counter and are preset at the spike-in timing.

The STDP model uses the spike timing information for the SW update operation. The SWI block240increments the SW values and the SWD block250decrements the SW values, respectively. LUTs are used in SWI240and SWD250blocks. In an embodiment of the present principles, the contents of these LUTs are prepared based on the simulation or hardware measurement results. In another embodiment, the contents are pre-loaded into each LUT with the load_address<0:11> and load_data<0:7> signals shown inFIGS. 4 and 7. There is a large amount of data in the LUTs, and, if all of the data for the LUT is acquired, the data can be loaded in these LUTs. However, if there is any missing data in the measurement or simulation for the LUTs, the missing data can be calculated with interpolation or extrapolation using existing data. In addition to the measurement and the simulation, the contents of the LUTs can be supplied with equations or a mixture of them.

The increment and decrement amounts of the SW values can be determined with current AT220, DT230, and SW values. A Row Address Decoder (RAD)260and a Column Address Recorder (CAD)270decode row and column addresses for the SW RAM210. The RAD260and CAD270are used for read and write access to the SW RAM210. For the read access, the current SW value, sw(t)<0:7> is taken at read data output ports sw_read<0:7>, and for the write access, the next SW value, sw(t+1)<0:7> is given at write data input ports sw_write<0:7>. This value replaces current SW value sw(t)<0:7> in the write access. In an embodiment of the present principles, there is a configuration that has 256 ATs220and256DTs230. However, the number of ATs220and DTs230can be modified to the target application. In this configuration, an AT220and a DT230are assigned to each axon and dendrite, one by one. For the time-sharing serial operation at the SWI240and SWD250blocks, a 256 to 1 Multiplexor (MUX)280is used to select one of the AT220data out of the 256 AT220data. This is also true of the 256 to 1 MUX285for the DT230data. The AT220data value is ax_tmr(t)<0:3> and the DT230data value is dr_tmr(t)<0:3>. A 2 to 1 MUX235selects one of the results from either the SWD block250or the SWI block240which is to be written to the SW RAM210as updated SW data. A Sequencer for block control signals & Address Generator for SW RAM (SAG)290implements the timing sequence generating trigger or the control (select) signals to the other blocks. This block290has clock (clk) and reset inputs and generates row and column address signals (sw_ram_row_adr<0:7> and sw_ram_col_adr<0:7>, respectively) for the SW RAM210.

Additionally, the SAG290sends a neuron membrane potential register trigger signal, np_reg_trg to a Neuron membrane Potential Register (NPR)205, which stores data on the Neuron membrane Potential (NP) in, for example, 8 bit each. The SAG290further sends an LUT trigger signal, npu_lut_trg<1:2>, for NP update to a Neuron membrane Potential Update block (NPU)215. In the NPU215, an NP value is updated with spike input (Axon Input) timing (ax_tmr(t)<0:3>), SW values for corresponding synapses (sw(t)<0:7>), and the current NP value (np(t)<0:7>). The updated NP value, np(t+1)<0:7>, is then sent to the NPR205. The NPU215further checks whether the NP reaches a certain threshold level to generate a fire signal (fire_th<0:7>). The NPU implements this operation with the leaky decay of the NP. These operations are called Leaky Integrate and Fire (LIF) operations. In order to implement the LIF function, the NPU receives input signals for the current AT220, SW and NP values. The NPU then applies the leaky decay effect and generates the output signal for the next NP value.

The dr_out_pulse signal is used to generate signals, dr_out0-dr_out255, from original signals, dor0-dor255. Furthermore, in a Dendrite Output Register (DOR)225, a serial to parallel conversion of Dendrite Output (or Neuron Fire) signals is achieved. This may be needed because internal signals are processed in a serial manner, while the external interface is processed in a parallel manner. The DOR225converts a serial signal, dr_out (neuron fire), to parallel signals (dor0to dor255) to give parallel input to the synapse or the axon of the next synapse.

In an embodiment of the present principles, the SW update is achieved together with the NP update. In this embodiment, the SW values and the NP values can be updated simultaneously.

In an embodiment of the present principles, the system is able to switch from a learning mode to a non-learning mode via an internal switch. This switching capability can be used to enable the accumulation of information and/or data before a functional operation is performed.

Referring now toFIG. 3, a sequence for the operation of the system is shown. In this figure, evaluation time cycles Teval k−1, Teval kand Teval k+1are shown. The timing sequence for Teval k, which is described in detail, is repeated, so the other evaluation time cycles, such as Teval k−1and Teval k+1, have completely the same sequences. At Teval k, the sequence progresses from top to bottom. The sequence begins at step310.

At step310, a spike is input from the pre-neuron or from an external input.

At step320, once the axon spike is inputted, the AT is updated, during which all AT times are decremented by 1 or a certain amount and the AT is preset for axons with input spikes only.

At step330, the SWD block decrements the SW values. In an embodiment of the present principles, the decrement amount is determined using the current DT and SW values.

At step340, the NP is updated while incorporating the leak effect. During this step, the NPU receives input signals for the current AT, SW, and NP values. The NPU then applies the leaky decay effect and generates the output signal for the next NP value.

At step350, all of the neurons are checked in order to determine whether or not each of the neurons fires or not. In an embodiment of the present principles, the NPU checks whether the NP reaches a certain threshold level to generate a fire signal (fire_th<0:7>).

At step360, the DT is updated, during which all DT times are decremented by 1 or a certain amount and the DT is preset for dendrites with fired neurons only.

At step370, the SWI block increments the SW values. In an embodiment of the present principles, the increment amount is determined using the current AT and SW values.

In one embodiment, there is only one 8-bit write port for SW RAM. The sw_inc_dec_sel signal selects an updated (incremented) SW value, sw_inc(t+1)<0:7>, or an updated (decremented) SW value, sw_dec(t+1)<0:7>, to be written into the SW RAM. If the system is on step330, the sw_inc_dec_sel signal is Low. If the system is on step370, the sw_inc_dec_sel signal is High.

At step380, a spike is output from the post-neuron or from an external output.

Referring now toFIG. 4, a block diagram of an exemplary SWI block400is shown. This block400consists of an LUT410for an SWI and an LUT Access Timing Generator (LATG)420. The LATG420generates an LUT access (or trigger) signal (sw_inc_lut_trg) from sw_inc_trg input signal and dr_outj(j=0 to 255) (neuron fire) signals. The LUT410has address input ports430for the AT value (ax_tmr(t)<0:3>) and address import ports440for the current SW value (sw(t)<0:7>). It also has data output ports450for the updated (incremented) SW value (sw_inc(t+1)<0:7>). The LUT data can be loaded (written) with load_address<0:11> and load_data<0:7> before operation. In this example, the length of the address input data (ax_tmr(t)<0:3> & sw(t)<0:7>) is 12 (=4+8) bits and the length of the output data (sw_inc(t+1)<0:7>) is 8 bits.

Referring now toFIG. 5, a timing diagram for the operation of an SWI block over Tevalcycles0to4,500,510,520,530and540, respectively, is shown. When there is a spike560at the dr_out, input and the sw_inc_trg signal is activated, the LATG generates time pulses on the sw_inc_lut_trg signal at pulse timing slot j. In an embodiment of the present principles, the LATG generates 256 pulses on the sw_inc_lut_trg signal at pulse timing slot j (j=0 to 255)550. This pulse timing slot corresponds to the column of SW values to be updated (incremented). In this example, dr_out0has a spike560in Tevalcycle0500. Thus, in this configuration, there are 256 pulses on the sw_inc_lut_trg signal at pulse timing slot0. At the same time, ax_tmr(t)<0:3> for ATi(i=0 to 255) and sw(t)<0:7> for SWi0(i=0 to 255) are supplied from external blocks (AT,SW RAM, RAD,CAD and SAG inFIG. 2). There is no dr_out spike560in Tevalcycle1510. Thus there is no pulse on the sw_inc_lut_trg signal during this cycle. In Tevalcycle2520, there is a spike560at the dr_outjsignal. Thus, in this configuration, 256 pulses are generated on the sw_inc_lut_trg signal at pulse timing slot j. In Tevalcycles3530and4540, there are spikes560at multiple dr_outj(j=0 to 255) signals. In the Tevalcycle3530, there are spikes560at the dr_out1and dr_out2signals. In Tevalcycle4540, there are spikes560at the dr_out2and dr_out255signals. That is, for the Tevalcycles3530and4540, a multiple (2) of the 256 pulses are generated on the sw_inc_lut_trg signal at multiple pulse timing slots of “1 and 2” and “2 and 255,” respectively.

Referring now toFIG. 6, a magnified timing diagram of Tevalcycle4540inFIG. 5is shown. This figure shows transferred data for ax_tmr(t)<0:3>, sw(t)<0:7>, and sw_inc(t+1)<0:7> in detail.

Referring now toFIG. 7, a block diagram of an exemplary SWD block700is shown. This block700consists of an LUT710for an SWD and an LATG720. The LATG720generates an LUT access (or trigger) signal (sw_dec_lut_trg) from sw_dec_trg input signal and the ax_ini(i=0 to 255) signals. The LUT710has address input ports730for the DT value (dr_tmr(t)<0:3>) and address input ports740for the current SW value (sw(t)<0:7>). It also has data output ports750for the updated (decremented) SW value (sw_dec(t+1)<0:7>). The LUT data can be loaded (written) with the load_address<0:11> and the load_data<0:7> before operation. In this example, the length of the address input data (dr_tmr(t)<0:3> & sw(t)<0:7>) is 12 (=4+8) bits and the length of the output data (sw_dec(t+1)<0:7>) is 8 bits.

Referring now toFIG. 8, a timing diagram for the operation of an SWD block over Tevalcycles0to4,800,810,820,830and840, respectively, is shown. When there is a spike860at the ax_in, input and the sw_dec_trg signal is activated, the LATG generates times pulses on the sw_dec_lut_trg signal at pulse timing slot i. In an embodiment of the present principles, the LATG generates 256 times pulses on the sw_dec_lut_trg signal at pulse timing slot i (i=0 to 255). This pulse timing slot corresponds to the row of SW values to be updated (decremented). In this example, ax_in0has a spike860in Teal cycle0800. Thus, in this configuration, there are 256 pulses on the sw_dec_lut_trg signal at pulse timing slot0. At the same time, dr_tmr(t)<0:3> for DTj(j=0 to 255) and sw(t)<0:7> for SW0j(j=0 to 255) are supplied from external blocks (DT,SW RAM, RAD,CAD and SAG inFIG. 2). There is no ax_in spike860in Tevalcycle1810. Thus there is no pulse on the sw_dec_lut_trg signal during this cycle. In Tevalcycle2820, there is a spike860at the ax_inisignal. Thus, in this configuration, 256 pulses are generated on the sw_dec_lut_trg signal at pulse timing slot i. In Tevalcycles3830and4840, there are spikes860at multiple ax_in signals. In Tevalcycle3830, there are spikes860at the ax_in1and ax_in2signals. In Tevalcycle4840, there are spikes860at the ax_in2and ax_in255signals. That is, for Tevalcycles3830and4840, a multiple (2) of the 256 pulses are generated on the sw_dec_lut_trg signal at multiple pulse timing slots of “1 and 2” and “2 and 255,” respectively.

Referring now toFIG. 9, a magnified timing diagram around Tevalcycle4540inFIG. 8is shown. This figure shows transferred data for dr_tmr(t)<0:3>, sw(t)<0:7>, and sw_dec

Referring now to the LUTs for the SWI block and the SWD block, in one of the embodiments of the present principles, all of the data of an LUT for an SWI block is calculated with equations based on the STDP theory (neither with measurement nor with simulation). The LUT's data is determined with equation 1 (eq. 1), while the delta value (+α(t)) is determined with equation 2 (eq. 2). Eq. 1 is defined as:
sw(t+1)=sw(t)+ax_tmr(t)2/p*((sw(t)−q)/q)2)q)2
Eq. 2 is defined as:
a(t)=ax_tmr(t)2/p*((sw(t)−q)/q)2q)2
Wherein p and q are optimization parameters for fitting eq. 1 and eq. 2 to actual synapse weight performance. This calculation, with the given equations, can be used for interpolation or extrapolation, too.

In one of the embodiments of the present principles, all of the data of an LUT for an SWD block is calculated with equations based on the STDP theory. The LUT's data is determined with equation 3 (eq. 3), while the delta value (−β(t)) is determined with equation 4 (eq. 4). Eq. 3 is defined as:
sw(t+1)=sw(t)−dr_tmr(t)2/p*(sw(t)/q)2
Eq. 4 is defined as:
β(t)=dr_tmr(t)2/p*(sw(t)/q)2
Wherein p and q are optimization parameters for fitting the eq. 1 and eq. 2 to actual synapse weight performance. This calculation, with the given equations, can be used for interpolation or extrapolation, too. In this system, the SW is expressed with 8-bit length digital (256 steps) data while the AT and DT values are expressed with 4-bit length data.

The contents of the LUTs can be supplied with delta values between sw(t) and sw(t+1), too. The delta values of the LUT's data for the SWI block shown inFIG. 11and for the SWD block shown inFIG. 12are +α(t) and −β(t), respectively.

Referring now toFIGS. 10 and 11, graphs are shown for the delta values for the SWI block and SWD block, respectively. InFIG. 10, the x-axis represents the AT value for time t, ax_tmr(t), and the y-axis represents the SW delta for time t, +α(t). InFIG. 11, the x-axis represents the DT value for time t, dr_tmr(t), and the y-axis represents the SW delta for time t, (−β(t)). In bothFIGS. 10 and 11, the SW deltas are represented for SWs of 0, 1, 16, 32, 48, 64, 80, 96, 112, 128, 144, 160, 176, 192, 208, 224, 240, and 255. If the contents of the LUTs are these delta values, both the SWI block and the SWD block need an adder at the output of each LUT. The SWI block and SWD block, with the adder, are shown inFIG. 12andFIG. 13, respectively.

Referring now toFIG. 12, a block diagram of the SWI block1200using an adder1260at the output of the LUT1210is shown. This block1200consists of an LUT1210for an SWI and an LATG1220. The LATG1220generates an LUT access (or trigger) signal (sw_inc_lut_trg) from an sw_inc_trg input signal and dr_outj(j=0 to 255) (neuron fire) signals. The LUT1210has an address input port1230for the AT value (ax_tmr(t)<0:3>) and an address import port1240for the current SW value (sw(t)<0:7>). It also has data output ports1250for the SW delta (+α(t)<0:7>). The adder1260adds the current SW value (sw(t)<0:7>) and the SW delta (+α(t)<0:7>). The LUT data can be loaded (written) with load_address<0:11> and load_data<0:7> before neuromorphic system operation. In this example, the length of the address input data (ax_tmr(t)<0:3> & sw(t)<0:7>) is 12 (=4+8) bits and the length of the output data (+α(t)<0:7>) is 8 bits.

Referring now toFIG. 13, a block diagram of the SWD block1300using an adder1360at the output of the LUT1310is shown. This block1300consists of an LUT1310for an SWD and an LATG1320. The LATG1320generates the LUT access (or trigger) signal (sw_dec_lut_trg) from the sw_dec_trg input signal and the ax_ini(i=0 to 255) signals. The LUT1310has an address input port1330for the DT value (dr_tmr(t)<0:3>) and an address input port1340for the current SW value (sw(t)<0:7>). It also has data output ports1350for the SW delta (−β(t)<0:7>). The adder1360adds the current SW value (sw(t)<0:7>) and the SW delta (−β(t)<0:7>). The LUT data can be loaded (written) with the load_address<0:11> and the load_data<0:7> before operation. In this example, the length of the address input data (dr_tmr(t)<0:3> & sw(t)<0:7>) is 12 (=4+8) bits and the length of the output data (43(t)<0:7>) is 8 bits.

With this example of LUTs that are made by the equations, the behavior of the STDP model is verified below.

Referring now toFIG. 14, delta values (+α(t) and −β(t)) are shown in one graph. The SW deltas are represented for SWs of 0, 16, 32, 48, 64, 80, 96, 112, 128, 144, 160, 176, 192, 208, 224, 240, and 255. The X-axis represents the timing difference between pre-neuron activation and post-neuron activation. The positive area of the X coordinate corresponds to an (16−ATi(i-th ax_tmr(t))) (i=0 to 255) value when dr_outj(j=0 to 255) has a spike out. In this graph, X=16 corresponds to AT (i-th ax_tmr(t))=0 and X=1 corresponds to ATi(i-th ax_tmr(t))=15. Conversely, the negative area of X coordinate corresponds to a (DTj(j-th dr_tmr(t))−16) (j=0 to 255) value when ax_in, (i=0 to 255) has a spike in. In this graph, X=(−16) corresponds to DTj(j-th dr_tmr(t))=0 and X=(−1) corresponds to DTj(j-th dr_tmr(t))=15. This graph shows the following behaviors of the proposed scheme. (1) If there is any spike output at dr_out, (j=0 to 255) within 15 Tevalcycles since ATiis reset with spike input at ax_ini(i=0 to 255), SWijis incremented. The increment amount is maximum at X=1 or AT (i-th ax_tmr(t))=15 and it decreases little by little when X is larger or ATi(i-th ax_tmr(t)) is smaller.

The increment amount is 0 when X=16 or AT (i-th ax_tmr(t))=0. In other words, the increment amount increases if the timing difference from ax_inispike to dr_outjspike decreases. The increment amount decreases if this timing difference increases. Conversely, (2) if there is any spike input at ax_ini(i=0 to 255) just after there is any spike output at dr_outj(j=0 to 255), SWijis decremented. The decrement amount is maximum at X=−1 or DT, (j-th dr_tmr(t))=15 and it decreases little by little when X is smaller or DT, (j-th dr_tmr(t)) is smaller. The decrement amount is 0 when X=(−16) or DT, (j-th dr_tmr(t))=0. In other words, the decrement amount increases if the timing difference from dr_outjspike to ax_inispike decreases. It decreases if this timing difference increases. These operations correspond to the behavior of the STDP model in which the timing difference between the axon pulse and the dendrite pulse determines the value of the next SW.