Semiconductor device and manufacturing method of the semiconductor device

A semiconductor device includes a semiconductor substrate, a device region including first and second parts, first and second gate electrodes formed in the first and the second parts, first and second source regions, first and second drain regions, first, second, third, and fourth embedded isolation film regions formed under the first source, the first drain, the second source, and the second drain regions, respectively. Further, the first drain region and the second source region form a single diffusion region, the second and the third embedded isolation film regions form a single embedded isolation film region, an opening is formed in a part of the single diffusion region so as to extend to the second and the third embedded isolation film regions, and the opening is filled with an isolation film.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority of Japanese Patent Application No. 2011-092285, filed Apr. 18, 2011. The entire contents of which are incorporated herein by reference.

FIELD

The embodiment discussed herein is related to a semiconductor device and a manufacturing method of the semiconductor device.

BACKGROUND

Generally, in a MOS transistor, the source region or the drain region is formed in an opposite-conductivity-type well included in a device region. In this case, the source region or the drain region is isolated from the well by the PN junction formed between the source region and the well or between the drain region and the well.

However, in the MOS transistor having such a general structure, the operation speed may be reduced due the parasitic capacity of the PN junction, and a leakage current may occur.

To resolve the problem, there has been proposed a MOS transistor structure in which in the device region, the well is isolated from the source region or the drain region by an isolation structure using an oxide film, a nitride film, and a void (space) locally formed under the source region or the drain region. Such MOS transistor structure may be importance because it may be effective to reduce the junction capacitance and the leakage current.

As a forming process of forming the MOS transistor structure, for example, Japanese Laid-open Patent Publication No. 2007-27231 (hereinafter “Patent Document 1”) discloses a method in which a laminated structure is formed in which a Si layer is formed on a Si—Ge mixed crystal layer, and then, only the Si—Ge mixed crystal layer is removed by using the etching-rate difference between the Si layer and the Si—Ge mixed crystal layer.

By filling the void (air hole) with a silicon oxide film the void being generated by removing the Si—Ge mixed crystal layer, it may become possible to locally form an embedded region where a silicon oxide film is locally embedded into under the source region or the drain region, so that so-called an SOI (Silicon-on-insulator) structure may locally be formed.

SUMMARY

According to an aspect, a semiconductor device includes a semiconductor substrate; a device region formed on the semiconductor substrate, defined by a device isolation region, and including a first device region part (first part) and a second device region part (second part); a first gate electrode formed in the first device region part; a first source region formed on a first side of the first gate electrode in the first device region part; a first drain region formed on a second side of the first gate electrode in the first device region part; a second gate electrode formed in the second device region part; a second source region formed on a first side of the second gate electrode in the second device region part; a second drain region formed on a second side of the second gate electrode in the second device region part; a first embedded isolation film region formed under the first source region; a second embedded isolation film region formed under the first drain region; a third embedded isolation film region formed under the second source region; and a fourth embedded isolation film region formed under the second drain region. Further, the first drain region and the second source region constitute (form) a single (the same) diffusion region between the first gate electrode and the second gate electrode. Further, in the second embedded isolation film region and the third embedded isolation film region constitute (form) a single (the same) embedded isolation film region between the first gate electrode and the second gate electrode. Further, between the first gate electrode and the second gate electrode, an opening is formed in a part of the diffusion region including (forming) the first drain region and the second source region, so that the opening extends to (reaches) the second embedded isolation film region and the third embedded isolation film region. Further, the opening is filled with an isolation film.

The objects and advantages of the embodiments disclosed herein will be realized and attained by means of the elements and combinations particularly pointed out in the claims.

DESCRIPTION OF EMBODIMENTS

In the method of Patent Document 1, the active region of the transistor including the source region and the drain region is formed in a shape of a mesa structure, so that the Si—Ge mixed crystal layer is disposed on the side wall surface of the mesa structure under the source region and the drain region.

In this structure, the Si—Ge mixed crystal layer may be easily removed by etching from the side wall surface of the mesa structure, and a desirable air hole (void) may be formed under the source region and the drain region and the air hole may be filled with an embedded isolation film.

To use the technique (method) of Patent Document 1, it may be necessary to form the mesa structure in the active region. However, it may not be always possible to form the mesa structure for each of the transistors.

For example, in a semiconductor device including first and second transistors where the drain region of the first transistor and the source region of the second transistor are commonly used, it may be difficult to form the mesa structure for each of the first and the second transistors. For example, even in such a case where a silicon epitaxial layer is formed on the Si—Ge mixed crystal layer, and first and second transistors are formed on the silicon epitaxial layer, it may still be difficult to selectively etch the Si—Ge mixed crystal layer under the diffusion region commonly used as the drain region of the first transistor and the source region of the second transistor to form a void (air hole) and form an embedded isolation film under the diffusion region by filling the void with an isolation film.

First Embodiment

FIGS. 1A through 1Dillustrate an example configuration of a semiconductor device20according to a first embodiment. Specifically,FIG. 1Ais a top view.FIG. 1Bis a cross-sectional view cut along the line E-E′ inFIG. 1A.FIG. 1Cis a cross-sectional view cut along the line B-B′ inFIG. 1A.FIG. 1Dis a cross-sectional view cut along the line C-C′ inFIG. 1A.

As illustrated inFIGS. 1A through 1D, for example, the semiconductor device20is formed on a device region (a.k.a active region)21defined by a device isolation region (“isolation region”)21I on a p-type silicon substrate11. The device region21includes a first device region part (first part)21A and a second device region part (second part)21B which are adjacent (contiguous) to each other.

In the first device region part21A, a first MOS transistor20A is formed. In the second device region part21B, a second MOS transistor20B is formed. The device isolation region21I is an STI-type device isolation region including a device isolation groove21tsurrounding the device region21and an isolation film such as a silicon oxide film filling the device isolation groove21t.

Basically, the first device region part21A is contiguous to (in contact with) the second device region part21B. However, as illustrated inFIGS. 1A through 1D, in the connecting part between the first device region part21A and the second device region part21B, there is an isolation film region21J formed by filling an insulation film such as an silicon oxide film into a trench, a concave part, or a hole (an opening)21ubesides the device isolation region21I.

The isolation film region21J is isolated from the device isolation region21I. Namely, as illustrated inFIG. 1A, the isolation film region21J is surrounded by the first device region part21A and the second device region part21B which (collectively) constitute (form) the device region21.

As described in detail below, in this embodiment, for example, the isolation film region21J is simultaneously formed with the device isolation region21I. The depth of the trench21uis the same as that of the device isolation groove21t. Further, the same isolation film is used as the isolation film filled into the device isolation groove21tand the isolation film filled into the trench21u. In the example of the figures, the isolation films are made of a silicon oxide film formed by the CVD (Chemical Vapor Deposition) method.

Further, under the device region21, as illustrated inFIGS. 1B through 1D, there is formed a channel stopper region21cshaving n-type conductivity opposite to that of the silicon substrate11and extended (reached) from the first device region part21A to the second device region part21B.

Further, in the first device region part21A, there is a first gate electrode23A formed on the silicon substrate11via a first gate isolation film22A, the first gate electrode23A being the gate of the first MOS transistor20A and made of polysilicon or the like.

Similarly, in the second device region part21B, there is a second gate electrode23B formed on the silicon substrate11via a second gate isolation film22B, the second gate electrode23B being the gate of the second MOS transistor20B and being made of polysilicon or the like. In this example of the figures, the first gate electrode23A and the second gate electrode23B extend in parallel to each other.

Further, the first gate electrode23A has (two) side walls facing each other, and includes first side wall isolation films23aformed on the respective side walls. The first side wall isolation films23aare made of SiN, SiON, a silicon oxide film or the like. Under the first gate electrode23A, there is formed a first channel region21Cha.

Further, in the p-type silicon substrate11and under the first side wall isolation films23a, there are formed n-type source extension regions21aand21bon the left-hand side and the right-hand side, respectively, of the first channel region21Cha. Similarly, the second gate electrode23B has side walls facing each other, and includes second side wall isolation films23bformed on the respective side walls. The second side wall isolation films23bare made of SiN, SiON, a silicon oxide film or the like. Under the second gate electrode23B, there is formed a second channel region21Chb.

Further, in the p-type silicon substrate11and under the second side wall isolation films23b, there are formed n-type source extension regions21cand21don the left-hand side and the right-hand side, respectively, of the second channel region21Chb. In this embodiment, it should be noted that each of the first channel region21Cha and the second channel region21Chb is formed in a part of the p-type silicon substrate11.

Further, in the configuration (structure) ofFIGS. 1A through 1D, in a part where the first channel region21Cha and the n-type source extension regions21aand21bare formed in the silicon substrate11, there is formed a mesa structure M1rising upward from the lower side of the silicon substrate11where the channel stopper region21csare formed in the first device region part21A.

Similarly, in a part where the second channel region21Chb and the n-type source extension regions21cand21dare formed in the silicon substrate11, there is formed a mesa structure M2rising upward from the lower side of the silicon substrate11where the channel stopper region21csare formed in the second device region part21B.

Further, in the upper side of the mesa structure M1, there is a silicon epitaxial layer21ep1epitaxially formed relative to the p-type silicon substrate11so that the silicon epitaxial layer21ep1is in contact with the left-hand side of the side wall surface of the mesa structure M1. Similarly, there is a silicon epitaxial layer21ep2epitaxially formed relative to the p-type silicon substrate11so that the silicon epitaxial layer21ep2is in contact with the right-hand side of the side wall surface of the mesa structure M1and the left-hand side of the side wall surface of the mesa structure M2as well.

Also, there is a silicon epitaxial layer21ep3epitaxially formed relative to the p-type silicon substrate11so that the silicon epitaxial layer21ep3is in contact with the right-hand side of the side wall surface of the mesa structure M2. Further, as the source region of the first MOS transistor20A, there is an n+ type diffusion region21eformed in the silicon epitaxial layer21ep1outside the left-hand first side wall isolation films23aof the first gate electrode23A.

Further, as the drain region of the first MOS transistor20A, there is an n+ type diffusion region21fformed in the silicon epitaxial layer21ep2outside the right-hand first side wall isolation films23aof the first gate electrode23A. Further, as the source region of the second MOS transistor20B, there is an n+ type diffusion region21gformed in the silicon epitaxial layer21ep2outside the left-hand second side wall isolation films23bof the second gate electrode23B.

As illustrated inFIG. 1D, the n+ type diffusion region21fis contiguous to the n+ type diffusion region21gin the connecting part between the first device region part21A and the second device region part21B. Therefore, the diffusion regions are commonly used by the first MOS transistor20A and the second MOS transistor20B.

Further, as the drain region of the second MOS transistor20B, there is an n+ type diffusion region21hformed in the silicon epitaxial layer21ep3outside the right-hand second side wall isolation films23bof the second gate electrode23B.

As illustrated in the cross-sectional views ofFIGS. 1B through 1D, under the silicon epitaxial layer21ep1, there is a first embedded isolation film261formed so as to be contiguous to a part of the device isolation region21I and a part of the isolation film region21J.

Similarly, under the silicon epitaxial layer21ep2, there is a second embedded isolation film262formed so as to be contiguous to a part of the isolation film region21J and a part of the device isolation region21I. Further, under the silicon epitaxial layer21ep3, there is a third embedded isolation film263formed so as to be contiguous to a part of the device isolation region21I and a part of the isolation film region21J.

As illustrated inFIGS. 1A through 1D, there are silicide layers25A through25C formed on the exposure (upper) surfaces of the embedded isolation films261though263, respectively. Further, there are also silicide layers24A and24B formed on the exposure surfaces of the first gate electrode23A and the second gate electrode23B, respectively.

Further, an isolation film27is formed on the silicon substrate11so as to coat the first gate electrode23A and the second gate electrode23B. Further, as illustrated in top view ofFIG. 1A, in the isolation film27, as the source contact of the first MOS transistor20A, there are formed via plugs27A and27B on the silicide layer25A.

Further, as the drain contact of the first MOS transistor20A and the source contact of the second MOS transistor20B, there are formed via plugs27C and27D on the silicide layer25B. Further, as the drain contact of the second MOS transistor20B, there are formed via plugs27E and27F on the silicide layer25C.

Further, as illustrated in top view ofFIG. 1A, in parts of the device isolation region21I, there are formed contact pads23P and23Q on the first gate electrode23A and the second gate electrode23B, respectively. Further, there are formed via plugs27G and27H which are in contact with the contact pads23P and23Q, respectively.

As illustrated inFIG. 1B, the via plugs27C and27D have a configuration including metal plugs27cand27dmade of copper (Cu), tungsten (W) or the like and a barrier metal film27bcoating the surface of the metal plugs27cand27d, respectively, the barrier metal film27bhaving a Ta/TaN or Ti/TiN laminated structure. The same applies to the other via plugs27A,27B, and27E through27F.

In this embodiment, the isolation film region21J is isolated from the device isolation region21I, and is surrounded by silicon epitaxial layer21ep2. However, to prevent the increase of the device surface, it is preferable that the isolation film region21J has the same size and the same shape (figure) as those of the via plugs27A through27F.

However, it is not always necessary that the he isolation film region21J is isolated from the device isolation region21I. For example, when permitted by circuit design, as illustrated in a modified example ofFIG. 19, the isolation film region21J may be contiguous to a part of the device isolation region21I. However, in the modified example ofFIG. 19, the isolation film region21J is extended; therefore, there is no via plug (via contact)27C unlike the semiconductor device in the embodiment ofFIGS. 1A through 1D.

In the following, an example method of manufacturing the semiconductor device according to the first embodiment is described with reference toFIGS. 2A through 18D.

FIGS. 2A through 2Dillustrate a step of a manufacturing process of the semiconductor device20according to the first embodiment. Specifically,FIG. 2Ais a top view.FIG. 2Bis a cross-sectional view cut along the line E-E′ inFIG. 2A.FIG. 2Cis a cross-sectional view cut along the line B-B′ inFIG. 2A.FIG. 2Dis a cross-sectional view cut along the line C-C′ inFIG. 2A.

As illustrated inFIG. 2A through 2D, an n-type impurity element such as P, As or the like is introduced by ion implantation into the p-type silicon substrate11to form the channel stopper region21csin the p-type silicon substrate11. Further, in this case, the upper end of the channel stopper region21csis formed at the depth of approximately 90 nm from the upper surface of the p-type silicon substrate11and a PN junction is formed.

FIGS. 3A through 3Dillustrate a step of the manufacturing process of the semiconductor device20according to the first embodiment following the step ofFIGS. 2A through 2D. Specifically,FIG. 3Ais a top view corresponding toFIG. 2A.FIG. 3Bis a cross-sectional view cut along the line E-E′ inFIG. 3A.FIG. 3Cis a cross-sectional view cut along the line B-B′ inFIG. 3A.FIG. 3Dis a cross-sectional view cut along the line C-C′ inFIG. 3A.

As illustrated inFIG. 3A through 3D, in the p-type silicon substrate11, a first device isolation groove (“first trench”)21tis formed so as to be deeper than the PN junction to define the device region21. At the same time, being isolated from the first trench21t, a second trench, a concave portion, or a hole (an opening)21uis also formed so as to have the same depth as that of the first trench21t.

However, it is not always necessary that the second trench21uhas the same depth as that of the first trench21t. For example, the second trench21umay be formed so as to have a shallower than the first trench21t. Further, the first trench21tand the second trench21umay be separately formed (i.e., may not be simultaneously formed).

Further, in the step ofFIGS. 3Athrough3D, the first trench21tand the second trench21uare filled with the silicon oxide film. Specifically, the first trench21tand the second trench21uare filled with the silicon oxide film using the CVD method, and a chemical mechanical polishing is performed so that the surface of the silicon substrate11is exposed.

FIGS. 4A through 4Dillustrate a step of the manufacturing process of the semiconductor device20according to the first embodiment following the step ofFIGS. 3A through 3D. Specifically,FIG. 4Ais a top view corresponding toFIG. 3A.FIG. 4Bis a cross-sectional view cut along the line E-E′ inFIG. 4A.FIG. 4Cis a cross-sectional view cut along the line B-B′ inFIG. 4A.FIG. 4Dis a cross-sectional view cut along the line C-C′ inFIG. 4A.

As illustrated inFIG. 4A through 4D, in this step, the silicon substrate11is thermally oxidized in an oxidizing atmosphere to form a thermally-oxidized film22having a film thickness in a range from 0.3 nm to 1 nm in the device region21. Herein, the oxidizing atmosphere refers to an atmosphere including oxygen such as an ozone atmosphere, an oxygen atmosphere, an oxidation nitride gas atmosphere or the like.

In the step ofFIG. 4A through 4D, a heating process or a plasma process may further be performed on the thermally-oxidized film22in a nitrogen atmosphere to transform the thermally-oxidized film into a silicon oxynitride film. For example, the thermally-oxidized film22having a film thickness of 0.7 nm is formed, and the formed thermally-oxidized film22is further heated in an NO gas atmosphere to transform the thermally-oxidized film into an isolation film made of the silicon oxynitride film.

In the following, it is assumed that the thermally-oxidized film (isolation film)22is the silicon oxynitride film formed as described above.

FIGS. 5A through 5Dillustrate a step of the manufacturing process of the semiconductor device20according to the first embodiment following the step ofFIGS. 4A through 4D. Specifically,FIG. 5Ais a top view corresponding toFIG. 4A.FIG. 5Bis a cross-sectional view cut along the line E-E′ inFIG. 5A.FIG. 5Cis a cross-sectional view cut along the line B-B′ inFIG. 5A.FIG. 5Dis a cross-sectional view cut along the line C-C′ inFIG. 5A.

As illustrated inFIG. 5A through 5D, in this step, a polysilicon film23is deposited on the silicon substrate11via the isolation film22so that the polysilicon film23has the thickness approximately in a range from 10 nm to 100 nm using, for example, a heating CVD method. By doing this, the device isolation region21I, the first device region part21A, and the second device region part21B, including the isolation film region21J are continuously coated. The polysilicon film23may be deposited as a form of amorphous silicon film and then crystallized.

FIGS. 6A through 6Dillustrate a step of the manufacturing process of the semiconductor device20according to the first embodiment following the step ofFIGS. 5A through 5D. Specifically,FIG. 6Ais a top view corresponding toFIG. 5A.FIG. 6Bis a cross-sectional view cut along the line E-E′ inFIG. 6A.FIG. 6Cis a cross-sectional view cut along the line B-B′ inFIG. 6A.FIG. 6Dis a cross-sectional view cut along the line C-C′ inFIG. 6A.

As illustrated inFIG. 6A through 6D, in this step, the polysilicon film23is patterned. Further, the first gate electrode23A is formed on a first side (i.e., on the left-hand side) inFIGS. 6C and 6D, and the second gate electrode23B is formed on a second side (i.e., on the right-hand side) inFIGS. 6C and 6D.

When the polysilicon film23is patterned, the isolation film22is also patterned so that the first gate isolation film22A is formed between the first gate electrode23A and the silicon substrate11and under the first gate electrode23A, and the second gate isolation film22B is formed between the second gate electrode23B and the silicon substrate11and under the second gate electrode23B.

Further, the first gate electrode23A extends on the device isolation region21I to form the contact pad23P. Similarly, the second gate electrode23B extends on the device isolation region21I to form the contact pad23Q.

FIGS. 7A through 7Dillustrate a step of the manufacturing process of the semiconductor device20according to the first embodiment following the step ofFIGS. 6A through 6D. Specifically,FIG. 7Ais a top view corresponding toFIG. 6A.FIG. 7Bis a cross-sectional view cut along the line E-E′ inFIG. 7A.FIG. 7Cis a cross-sectional view cut along the line B-B′ inFIG. 7A.FIG. 7Dis a cross-sectional view cut along the line C-C′ inFIG. 7A.

As illustrated inFIG. 7A through 7D, in this step, a pair of side wall isolation films23dais formed on the respective side walls of the first gate electrode23A, the side walls being disposed opposite to each other. Also, a pair of side wall isolation films23dbis formed on the respective side walls of the second gate electrode23B, the side walls being disposed opposite to each other. The side wall isolation films23daand23dbare made of a material (e.g., SiN) having an etching selectivity with respect to silicon of the silicon substrate11and silicon oxide film of the device isolation region21I and the isolation film region21J. Further, the side wall isolation films23daand23dbwill be removed; therefore, the side wall isolation films23daand23dbmay also be called dummy side wall isolation films23daand23db.

The dummy side wall isolation films23daand23dbextent on the device isolation region21I and are formed on the side wall surfaces of the contact pad23P and23Q.

FIGS. 8A through 8Dillustrate a step of the manufacturing process of the semiconductor device20according to the first embodiment following the step ofFIGS. 7A through 7D. Specifically,FIG. 8Ais a top view corresponding toFIG. 7A.FIG. 8Bis a cross-sectional view cut along the line E-E′ inFIG. 8A.FIG. 8Cis a cross-sectional view cut along the line B-B′ inFIG. 8A.FIG. 8Dis a cross-sectional view cut along the line C-C′ inFIG. 8A.

As illustrated inFIG. 8A through 8D, in this step, dry etching is performed on the silicon substrate11by using the first gate electrode23A, the second gate electrode23B, and the dummy side wall isolation films23daand23dbas a mask and by applying, for example, chlorine gas (Cl2) or hydrochloric gas (HCl) as etching gas. By the dry etching, the part outside the dummy side wall isolation films23dawhen viewed from the first gate electrode23A and the part outside dummy side wall isolation films23dbwhen viewed from the second gate electrode23B in the silicon substrate11are etched in a manner such that the depth of the etched parts does not exceed the depth of the device isolation region21I and the isolation film region21J.

In this case, the silicon substrate11is etched to a depth of, for example, 80 nm. As a result, a first trench21TA, a second trench21TB, and a third trench21TC are formed. Specifically, the first trench21TA is formed on the first side (i.e., on the left-hand side) of the first gate electrode23A. The third trench21TC are formed on the second side (i.e., on the right-hand side) of the second gate electrode23B. Further, the second trench21TB is formed between the first gate electrode23A and the second gate electrode23B. Though it is not illustrated, on the upper parts of the first gate electrode23A and the second gate electrode23B, in the step ofFIGS. 5A through 5D, silicon oxide films are formed to be used as an etching mask.

As a result of forming the trenches21TA,21TB, and21TC, as a part of the p-type silicon substrate11, the mesa structure M1rising upward from the bottom of the trenches21TA and21TB is formed under the first gate electrode23A and the (first) dummy side wall isolation films23da. Also, as a part of the p-type silicon substrate11, the mesa structure M2rising upward from the bottom of the trenches21TB and21TC is formed under the second gate electrode23B and the (second) dummy side wall isolation films23db.

FIGS. 9A through 9Dillustrate a step of the manufacturing process of the semiconductor device20according to the first embodiment following the step ofFIGS. 8A through 8D. Specifically,FIG. 9Ais a top view corresponding toFIG. 8A.FIG. 9Bis a cross-sectional view cut along the line E-E′ inFIG. 9A.FIG. 9Cis a cross-sectional view cut along the line B-B′ inFIG. 9A.FIG. 9Dis a cross-sectional view cut along the line C-C′ inFIG. 9A.

As illustrated inFIG. 9A through 9D, in this step, a Si—Ge mixed layer is selectively and epitaxially grown to have a thickness of in a range, for example, from 20 nm to 80 nm by the CVD method using a mixed gas of, for example, silane (SiH4) or dichlosilane (SiH2Cl2), monogermane (GeH4), hydrogen chloride (HCl), and hydrogen (H2) as a material. Herein, the term Si—Ge mixed layer may be a mixed layer including any other element in addition to Si and Ge.

For example, the Si—Ge mixed layer may be epitaxially grown at a growth speed of, for example, 45 nm/min under a pressure in a range from 1330 Pa to 13300 Pa (i.e., 10 Torr to 100 Torr), preferably at 5320 Pa (40 Torr), a substrate temperature in a range from 650° C. to 750° C., preferably at 700° C., a hydrogen gas partial pressure in a range from 4000 Pa to 6000 Pa, preferably at 5300 Pa, a dichlorosilane gas partial pressure in a range from 20 Pa to 30 Pa, preferably at 26 Pa, a monogermane gas partial pressure in a range from 10 Pa to 15 Pa, preferably at 12 Pa, and a hydrogen chloride gas partial pressure in a range from 10 Pa to 15 Pa, preferably at 12 Pa.

As a result of the growth of the Si—Ge mixed layer, a first Si—Ge mixed layer region SG1, a second Si—Ge mixed layer region SG2, and a third Si—Ge mixed layer region SG3are epitaxially formed relative to the p-type silicon substrate11corresponding to the first trench21TA, the second trench21TB, and the third trench21TC, respectively, so as to have a thickness in a range from 20 nm to 80 nm.

Here, for example, the Si—Ge mixed layer regions SG1through SG3having approximately 20% of Ge atomic fraction are used. However, Ge composition in the Si—Ge mixed layer regions SG1through SG3may be increased as long as the Si—Ge mixed layer regions SG1through SG3may epitaxially grow relative to the silicon substrate11. For example, it may be possible to use the Si—Ge mixed layer having approximately 40% of the Ge atomic fraction may be used as the Si—Ge mixed layer regions SG1through SG3. Further, as the Si—Ge mixed layer regions SG1through SG3, it may also be possible to use the Si—Ge mixed layer further includes C (Carbon).

Further, in the step ofFIGS. 9A through 9D, on the Si—Ge mixed layer regions SG1, SG2, and SG3in the trenches21TA,21TB, and21TC, the silicon epitaxial layers21ep1,21ep2, and21ep3, respectively, are epitaxially grown relative to the silicon substrate11using mixed gas including, for example, disilane gas, hydrogen chloride gas, and hydrogen gas.

For example, the silicon epitaxial layers21ep1,21ep1, and21ep1may be grown at a growth speed of, for example, 0.7 nm/min under a pressure in a range from 1330 Pa to 13300 Pa (i.e., 10 Torr to 100 Torr), preferably at 5320 Pa (40 Torr), a substrate temperature in a range from 650° C. to 750° C., preferably at 700° C., a hydrogen gas partial pressure in a range from 4000 Pa to 6000 Pa, preferably at 5300 Pa, a dichlorosilane gas partial pressure in a range from 15 Pa to 25 Pa, preferably at 21 Pa, and a hydrogen chloride gas partial pressure in a range from 3 Pa to 10 Pa, preferably at 5 Pa.

As a result of the growth of the Si—Ge mixed layer, it may become possible to fill the trenches21TA,21TB, and21TC up to the upper surface of the silicon substrate11with the silicon epitaxial layers21ep1,21ep2, and21ep3on the Si—Ge mixed layer regions SG2, SG2, and SG2, respectively. However, in this embodiment, the silicon epitaxial layers21ep1,21ep2, and21ep3may be grown so as to exceed the upper surface of the silicon substrate11.

FIGS. 10A through 10Dillustrate a step of the manufacturing process of the semiconductor device20according to the first embodiment following the step ofFIGS. 9A through 9D. Specifically,FIG. 10Ais a top view corresponding toFIG. 9A.FIG. 10Bis a cross-sectional view cut along the line E-E′ inFIG. 10A.FIG. 10Cis a cross-sectional view cut along the line B-B′ inFIG. 10A.FIG. 10Dis a cross-sectional view cut along the line C-C′ inFIG. 10A.

As illustrated inFIG. 10A through 10D, in this step, dry etching or wet etching using HF is performed on the structure illustrated inFIGS. 9A through 9Dto remove the silicon oxide films filling the device isolation groove (first trench)21tand the second trench21uin the device isolation region21I and the isolation film region21J, respectively and expose the side wall surfaces of the Si—Ge mixed layer regions SG2, SG2, and SG2filling the trenches21TA,21TB, and21TC, respectively.

In the example ofFIGS. 10A through 10D, in the device isolation groove (first trench)21tand the second trench21u, the silicon oxide films corresponding to the device isolation region21I and the isolation film region21J remain at the same depth as the lower end of the silicon epitaxial layers21ep1,21ep2, and21ep3. However, this is not always necessary. Namely, for example, the silicon oxide films may be completely removed from the device isolation groove (first trench)21tand the second trench21u.

Further, in the device isolation groove (first trench)21tand the second trench21u, the silicon oxide films may remain at the depth higher than the level illustrated in the figures, as long as sufficient areas of the side walls of the silicon epitaxial layers21ep1,21ep2, and21ep3are exposed.

FIGS. 11A through 11Dillustrate a step of the manufacturing process of the semiconductor device20according to the first embodiment following the step ofFIGS. 10A through 10D. Specifically,FIG. 11Ais a top view corresponding toFIG. 10A.FIG. 11Bis a cross-sectional view cut along the line E-E′ inFIG. 11A.FIG. 11Cis a cross-sectional view cut along the line B-B′ inFIG. 11A.FIG. 11Dis a cross-sectional view cut along the line C-C′ inFIG. 11A.

As illustrated inFIG. 11A through 11D, in this step, through the device isolation groove (first trench)21tand the second trench21u, etching is performed on the silicon epitaxial layers21ep1,21ep2, and21ep3and the silicon substrate11from the side wall surfaces of the silicon epitaxial layers21ep1,21ep2, and21ep3so as to selectively remove the silicon epitaxial layers21ep1,21ep2, and21ep3and the silicon substrate11along gas flowing paths as illustrated in arrows in the figures. As a result, voids (air holes)21V1,21V2, and21V3corresponding to the Si—Ge mixed layer regions SG1, SG2, and SG3are formed.

For example, the selective etching of the silicon epitaxial layers21ep1,21ep2, and21ep3may be performed by dry etching using hydrogen gas and chlorine-based gas such as hydrogen gas, chlorine gas or the like at a temperature of, for example, 700° C. or dry etching using CF4 radical. Further, the selective etching may be performed by wet etching using a mixture of acetic acid and hydrofluoric acid.

The voids21V1and21V3formed as described above are in communication with the device isolation groove (first trench)21t. Further, the void21V2formed as described above is in communication with the second trench21u.

As described above, in this embodiment, when the Si—Ge mixed layer regions SG1, SG2, and SG3are selectively etched, by forming the isolation film region21J (in advance), it may become possible to perform etching by way of the second trench21u. As a result, it may become possible to effectively perform etching.

On the other hand, in an comparative example where no isolation film region21J is formed, as illustrated inFIGS. 20A through 20C, the etching is performed only bay way of the device isolation groove (first trench)21t. As a result, the Si—Ge mixed layer regions SG1and SG3may be effectively removed in the multiple directions of the device isolation groove (first trench)21talong the gas flow directions as illustrated in the figures from the device isolation groove (first trench)21t.

However, in the Si—Ge mixed layer region SG2formed between the mesa structures M1and M2, there are only two portions along the extending directions of the gate electrodes23A and23B where the Si—Ge mixed layer region SG2is exposed to the device isolation groove (first trench)21t. Therefore, it may be difficult to (effectively) remove the Si—Ge mixed layer region SG2by etching. Herein,FIGS. 20A through 20Cillustrate a semiconductor device according to a comparative example of this embodiment.FIG. 20Bis a cross-sectional view cut along the line E-E′ inFIG. 20A.FIG. 20Cis a cross-sectional view cut along the line B-B′ inFIG. 20A.

FIGS. 12A through 12Dillustrate a step of the manufacturing process of the semiconductor device20according to the first embodiment following the step ofFIGS. 11A through 11D. Specifically,FIG. 12Ais a top view corresponding toFIG. 11A.FIG. 12Bis a cross-sectional view cut along the line E-E′ inFIG. 12A.FIG. 12Cis a cross-sectional view cut along the line B-B′ inFIG. 12A.FIG. 12Dis a cross-sectional view cut along the line C-C′ inFIG. 12A.

As illustrated inFIG. 12A through 12D, in this step, the embedded isolation film26is accumulated on the structure ofFIGS. 11A through 11D, so that not only the device isolation groove (first trench)21tand the second trench21ubut also the voids21V1,21V2, and21V3are filled with the embedded isolation film26. To accumulate the embedded isolation film26, it is preferable to use a film forming method having an excellent step coverage such as an ALD (Atomic Layered Deposition) method, the CVD method, an SOD (Spin-On-Dielectric) method, or the like.

For example, the embedded isolation film26may be formed by using tetradimethylaminosilane (TDMAS) and ozone (O3) as material gas at a temperature in a range from 300° C. to 600° C. Alternatively, as the material gas, BTBBAS (bis(tertiary-butylamino)silane) and oxygen. Further, in the step ofFIG. 12A through 12D, it may not be necessary to completely fill the voids21V1,21V2, and21V3with the embedded isolation film26. Namely, for example, a void may remain partially.

InFIG. 12A, no embedded isolation film26accumulated on the surface of the silicon substrate11is illustrated.

FIGS. 13A through 13Dillustrate a step of the manufacturing process of the semiconductor device20according to the first embodiment following the step ofFIGS. 12A through 12D. Specifically,FIG. 13Ais a top view corresponding toFIG. 12A.FIG. 13Bis a cross-sectional view cut along the line E-E′ inFIG. 13A.FIG. 13Cis a cross-sectional view cut along the line B-B′ inFIG. 13A.FIG. 13Dis a cross-sectional view cut along the line C-C′ inFIG. 13A.

As illustrated inFIG. 13A through 13D, in this step, an excessive embedded isolation film26on the silicon substrate11is etched back (removed) by dry etching, so that the surfaces of the silicon epitaxial layers21ep1,21ep2, and21ep3are exposed. As a result of the etch back, in the device isolation region21I and the isolation film region21J and under the silicon epitaxial layers21ep1,21ep2, and21ep3, not only the device isolation groove (first trench)21tand the second trench21ubut also the voids21V1,21V2, and21V3are filled with the embedded isolation film26, so that the embedded isolation films261,262, and263are formed under the silicon epitaxial layers21ep1,21ep2, and21ep3, respectively. The embedded isolation films261,262, and263correspond to the embedded isolation films261,262, and263inFIGS. 1A through 1D.

Further, the device isolation groove (first trench)21tand the second trench21uare also filled with the embedded isolation film26. As a result, in the device isolation region21I and the isolation film region21J, the lower parts of the device isolation groove (first trench)21tand the second trench21uare filled with the isolation film filled in step ofFIGS. 3A through 3D, and the upper parts of the device isolation groove (first trench)21tand the second trench21uare filled with the embedded isolation film26.

FIGS. 14A through 14Dillustrate a step of the manufacturing process of the semiconductor device20according to the first embodiment following the step ofFIGS. 13A through 13D. Specifically,FIG. 14Ais a top view corresponding toFIG. 13A.FIG. 14Bis a cross-sectional view cut along the line E-E′ inFIG. 14A.FIG. 14Cis a cross-sectional view cut along the line B-B′ inFIG. 14A.FIG. 14Dis a cross-sectional view cut along the line C-C′ inFIG. 14A.

As illustrated inFIG. 14A through 14D, in this step, the (first) dummy side wall isolation films23daformed on the side wall surfaces of the first gate electrode23A and the (second) dummy side wall isolation films23dbformed on the side wall surfaces of the second gate electrode23A are removed.

As a result, on both left-hand and right-hand sides of the of the first gate electrode23A, a surface of the mesa structure M1constituting a part of the p-type silicon substrate11and the surfaces of the silicon epitaxial layers21ep1and21ep2are continuously exposed. Similarly, on both left-hand and right-hand sides of the of the second gate electrode23B, a surface of the mesa structure M2constituting a part of the p-type silicon substrate11and the surfaces of the silicon epitaxial layers21ep2and21ep3are continuously exposed.

FIGS. 15A through 15Dillustrate a step of the manufacturing process of the semiconductor device20according to the first embodiment following the step ofFIGS. 14A through 14D. Specifically,FIG. 15Ais a top view corresponding toFIG. 14A.FIG. 15Bis a cross-sectional view cut along the line E-E′ inFIG. 15A.FIG. 15Cis a cross-sectional view cut along the line B-B′ inFIG. 15A.FIG. 15Dis a cross-sectional view cut along the line C-C′ inFIG. 15A.

As illustrated inFIG. 15A through 15D, in this step, by using the first gate electrode23A and the second gate electrode23B as a mask, n-type impurity elements such as arsenic (As) and phosphorus (P) are introduced into the surfaces of the mesa structures by the ion implantation method. By doing this, in the surface part of the first mesa structure M1, an n-type source extension region21aof the first MOS transistor20A is formed on the left-hand side (i.e., the first side) of the first gate electrode23A. Also, an n-type drain extension region21bis formed on the right-hand side (i.e., the second side) of the first gate electrode23A.

At the same time, in the surface part of the second mesa structure M2, an n-type source extension region21cof the second MOS transistor20B is formed on the left-hand side (i.e., the first side) of the second gate electrode23B. Also, an n-type drain extension region21d ais formed on the right-hand side (i.e., the second side) of the second gate electrode23B. Here, the n-type drain extension region21band the n-type source extension region21cconstitute (form) a single contiguous n-type diffusion region.

When the first MOS transistor20A and the second MOS transistor20B are n-channel MOS transistors, the source extension regions21aand21cand the source extension region21band21dmay be formed by the ion implantation method in which, for example, arsenic (As) is introduced at acceleration energy of 5 keV or less and with a doze amount in a range from 2×1013cm−2to 2×1015cm−2.

Further, when the first MOS transistor20A and the second MOS transistor20B are p-channel MOS transistors, the p-type source extension regions21aand21cand the p-type drain extension region21band21dmay be formed by the ion implantation method in which, for example, Boron (B) is introduced at acceleration energy of 2 keV or less and with a doze amount in a range from 2×1013cm−2to 2×1015cm−2.

Further, in step ofFIGS. 15A through 15D, though it is not illustrated, when the ion implantation method is performed by obliquely introducing p-type impurity element such as boron (B) to the first device region part21A and the second device region part21B by using the first gate electrode23A and the second gate electrode23B as a mask, pocket regions may be formed.

When the first MOS transistor20A and the second MOS transistor20B are p-channel MOS transistors, such ion implantation may be performed by, for example, Boron (B) is introduced at acceleration energy of 20 keV or less and with a doze amount of 5×1013cm−2or less.

Further, when the first MOS transistor20A and the second MOS transistor20B are n-channel MOS transistors, such ion implantation may be performed by, for example, arsenic (As) is introduced at acceleration energy of 100 keV or less and with a doze amount of 5×1013cm−2or less.

FIGS. 16A through 16Dillustrate a step of the manufacturing process of the semiconductor device20according to the first embodiment following the step ofFIGS. 15A through 15D. Specifically,FIG. 16Ais a top view corresponding toFIG. 15A.FIG. 16Bis a cross-sectional view cut along the line E-E′ inFIG. 16A.FIG. 16Cis a cross-sectional view cut along the line B-B′ inFIG. 16A.FIG. 16Dis a cross-sectional view cut along the line C-C′ inFIG. 16A.

As illustrated inFIG. 16A through 16D, in this step, similar to the side wall isolation films23daand the side wall isolation films23db, a pair of side wall isolation films23aand a pair of side wall isolation films23bformed of, for example, a silicone nitride film (SiN), a silicon oxynitride film (SiON), or a silicon oxide film (SiO2) are formed on both the first side and the second side walls of the first gate electrode23A and the second gate electrode23B, respectively, the first side being the sides opposite to the second side.

As described above, similar to the side wall isolation films23daand23db, by forming the side wall isolation films23aand the side wall isolation films23bagain, it may become possible to update (replace) the dummy side wall isolation films23daand23dbwhich may have been exhausted because of being used as a mask in the etching of the trenches21TA through21TC and further being used as a mask to protect side wall surfaces of the first gate electrode23A and the second gate electrode23B in step ofFIGS. 13A through 13D.

FIGS. 17A through 17Dillustrate a step of the manufacturing process of the semiconductor device20according to the first embodiment following the step ofFIGS. 16A through 16D. Specifically,FIG. 17Ais a top view corresponding toFIG. 16A.FIG. 17Bis a cross-sectional view cut along the line E-E′ inFIG. 17A.FIG. 17Cis a cross-sectional view cut along the line B-B′ inFIG. 17A.FIG. 17Dis a cross-sectional view cut along the line C-C′ inFIG. 17A.

As illustrated inFIG. 17A through 17D, in this step, by using the first gate electrode23A and the second gate electrode23B and the side wall isolation films23aand the side wall isolation films23bas masks, an n-type impurity element is introduced again by the ion implantation, so that in the silicon epitaxial layers21ep1and21ep2, on the outside of the side wall isolation films23awhen viewed from the first gate electrode23A, an n+ type source regions21eand an n+ type drain region21fare formed so as to be deeper than the n-type source extension regions21aand the n-type drain extension region21b, respectively, and having higher impurity concentration (than the n-type source extension regions21aand the n-type drain extension region21b).

Further, at the same time, in the silicon epitaxial layers21ep2and21ep3, on the outside of the side wall isolation films23bwhen viewed from the second gate electrode23B, an n+ type source regions21gand an n+ type drain region21hare formed so as to be deeper than the n-type source extension regions21cand the n-type drain extension region21d, respectively, and having higher impurity concentration (than the n-type source extension regions21cand the n-type drain extension region21d). Further, in this step, the first gate electrode23A and the second gate electrode23B formed of poly silicon are n+ type doped.

When the first MOS transistor20A and the second MOS transistor20B are n-channel MOS transistors, the n+ type source regions21eand21gand the n+ type drain regions21fand21hmay be formed by the ion implantation method in which, for example, arsenic (As) is introduced at acceleration energy of 5 keV or less and with a doze amount in a range from 2×1014cm−2to 2×1016cm−2.

Further, when the first MOS transistor20A and the second MOS transistor20B are p-channel MOS transistors, the p+ type source regions21eand21gand the p+ type drain regions21fand21hmay be formed by the ion implantation method in which, for example, Boron (B) is introduced at acceleration energy of 7 keV or less and with a doze amount in a range from 2×1014cm−2to 2×1016cm−2.

As illustrated inFIG. 17D, the n+ type drain region21fand the n+ type source region21gconstitute (form) a single contiguous (the same) diffusion region.

FIGS. 18A through 18Dillustrate a step of the manufacturing process of the semiconductor device20according to the first embodiment following the step ofFIGS. 17A through 17D. Specifically,FIG. 18Ais a top view corresponding toFIG. 17A.FIG. 18Bis a cross-sectional view cut along the line E-E′ inFIG. 18A.FIG. 18Cis a cross-sectional view cut along the line B-B′ inFIG. 18A.FIG. 18Dis a cross-sectional view cut along the line C-C′ inFIG. 18A.

As illustrated inFIG. 18A through 18D, in this step, a silicide layer is formed on the exposed silicon surface of the structure ofFIGS. 17A through 17Dusing a salicide (silicide) method. As a result, silicide layers25A,25B, and15C are formed on the surfaces of the silicon epitaxial layers21ep1,21ep2, and21ep3, respectively. Also, silicide layers24A and24B are formed on the surfaces of the first polysilicon gate electrode23A and the second polysilicon gate electrode23B, respectively.

After the step ofFIGS. 18A through 18D, the isolation film27is formed on the silicon substrate11, and the via plugs27A through27H are formed in the isolation film27, so as to form the semiconductor device20described with reference toFIGS. 1A through 1D.

As described above, according to this embodiment, in a case where the Si—Ge mixed layer regions SG1through SG3are selectively etched, by forming the isolation film region21J (in advance), it may become possible to etch the Si—Ge mixed layer regions SG2by using the second trench21u. As a result, it may become possible to effectively etch the Si—Ge mixed layer regions SG1through SG3. Further, in step ofFIGS. 12A through 12D, it may become possible to improve the efficiency in filling the voids21V1through21V3with the embedded isolation films261,262, and263.

In the semiconductor device20having been formed as described above, in each of the first MOS transistor20A and the second MOS transistor20B, the first channel region21Cha and the second channel region21Chb are formed in the mesa structures M1and M2, respectively, which are originally a part of the silicon substrate11having higher quality, and which are not formed based on any of the silicon epitaxial layers21ep1,21ep2, and21ep3which are grown later. Therefore, it may become possible to form the semiconductor (channel) regions having higher crystal quality and prevent carriers from being scattered or extinguished due to a defect or an impurity element.

Second Embodiment

Next, an example method of forming (manufacturing) a semiconductor device according to a second embodiment of the present invention is described with reference toFIGS. 21A through 27D.FIG. 21Ais a top view.FIG. 21Bis a cross-sectional view cut along the line E-E′ inFIG. 21A.FIG. 21Cis a cross-sectional view cut along the line B-B′ inFIG. 21A.FIG. 21Dis a cross-sectional view cut along the line C-C′ inFIG. 21A.

As illustrated inFIGS. 21A through 21D, none of the device isolation region21I, the device region21, the first device region part21A, the second device region part21B and the like are formed on the silicon substrate11. However, after the ion implantation is performed to form the channel stopper region21cs, stripe-shaped mask patterns31MA and31MB which are parallel to the boundary between the first device region part21A and the second device region part21B are formed in a region to be the first device region part21A and the second device region part21B of the silicon substrate11afterwards by using a silicon oxide film (SiO2), a silicone nitride film (SiN) or the like.

FIGS. 22A through 22Dillustrate a step of a manufacturing process of the semiconductor device20according to the second embodiment following the step ofFIGS. 21A through 21D. Specifically,FIG. 22Ais a top view corresponding toFIG. 21A.FIG. 22Bis a cross-sectional view cut along the line E-E′ inFIG. 22A.FIG. 22Cis a cross-sectional view cut along the line B-B′ inFIG. 22A.FIG. 22Dis a cross-sectional view cut along the line C-C′ inFIG. 22A.

As illustrated inFIG. 22A through 22D, in this step, the silicon substrate11is etched by dry etching using the mask patterns31MA and31MB as masks and using chlorine gas (Cl2) or hydrochloric gas (HCl) as etching gas. As a result of the etching, a first trench21TA is formed on the first side (i.e., on the left-hand side) of the mask pattern31MA. A second trench21TB is formed on the second side (i.e., on the right-hand side) of the mask pattern31MA and on the first side (i.e., on the left-hand side) of the mask pattern31MB. Further, a third trench21TC are formed on the second side (i.e., on the right-hand side) of the mask pattern31MB.

Preferably, those trenches21TA,21TB, and21TC are formed so as to extend to (reach) the channel stopper region21cs. In the example ofFIGS. 22A through 22D, it may appear that the trenches21TA,21TB, and21TC do not extend to (reach) the channel stopper region21cs. However, it is not always necessary that the trenches21TA,21TB, and21TC do not exceed the channel stopper region21cs. Namely, for example, the trenches21TA,21TB, and21TC may be formed so as to extend deeper than (i.e., exceed) the channel stopper region21cs.

After a result of forming the trenches21TA,21TB, and21TC, on the silicon substrate11, a mesa structure MA corresponding to the first device region part21A is formed between the trench21TA and the trench21TB, and a mesa structure MB corresponding to the second device region part21B is formed between the trench21TB and the trench21TC.

FIGS. 23A through 23Dillustrate a step of the manufacturing process of the semiconductor device20according to the second embodiment following the step ofFIGS. 22A through 22D. Specifically,FIG. 23Ais a top view corresponding toFIG. 22A.FIG. 23Bis a cross-sectional view cut along the line E-E′ inFIG. 23A.FIG. 23Cis a cross-sectional view cut along the line B-B′ inFIG. 23A.FIG. 23Dis a cross-sectional view cut along the line C-C′ inFIG. 23A.

As illustrated inFIG. 23A through 23D, in this step, the CVD process is performed by using the mask patterns31MA and31MB as masks, so that, similar to the step ofFIGS. 9A through 9D, the trenches21TA,21TB, and21TC are filled with the epitaxially grown Si—Ge mixed layers and silicon layers in the lower in the lower part and the upper part, respectively, of the trenches21TA,21TB, and21TC.

As a result, the trench21TA is filled with the Si—Ge mixed layer SG1and the silicon epitaxial layers21ep1in the lower part and the upper part, respectively. Similarly, the trench21TB is filled with the Si—Ge mixed layer SG2and the silicon epitaxial layers21ep2in the lower part and the upper part, respectively, and the trench21TC is filled with the Si—Ge mixed layer SG3and the silicon epitaxial layers21ep3in the lower part and the upper part, respectively.

FIGS. 24A through 24Dillustrate a step of the manufacturing process of the semiconductor device20according to the second embodiment following the step ofFIGS. 23A through 23D. Specifically,FIG. 24Ais a top view corresponding toFIG. 23A.FIG. 24Bis a cross-sectional view cut along the line E-E′ inFIG. 24A.FIG. 24Cis a cross-sectional view cut along the line B-B′ inFIG. 24A.FIG. 24Dis a cross-sectional view cut along the line C-C′ inFIG. 24A.

As illustrated inFIG. 24A through 24D, in this step, in the silicon substrate11, the device isolation groove (first trench)21tcorresponding to the device isolation region21I is formed so as to define the device region21. Also, the second trench21uis formed at the boundary part between the first device region part21A and the second device region part21B. Preferably, the device isolation groove (first trench)21tand the second trench21uare simultaneously formed and formed so as to be deeper than the lower ends of the Si—Ge mixed layer regions SG1through SG3. In the example ofFIGS. 24A through 24D, it may appear that the lower ends of the device isolation groove (first trench)21tand the second trench21uextended correspond to the lower end of the channel stopper region21cs.

However, it is not always necessary that the lower ends of the device isolation groove (first trench)21tand the second trench21uextended correspond to the lower end of the channel stopper region21cs. Namely, for example, the lower ends of the device isolation groove (first trench)21tand the second trench21umay be deeper (lower) or may be shallower (higher) than the lower end of the channel stopper region21cs.

FIGS. 25A through 25Dillustrate a step of the manufacturing process of the semiconductor device20according to the second embodiment following the step ofFIGS. 24A through 24D. Specifically,FIG. 25Ais a top view corresponding toFIG. 24A.FIG. 25Bis a cross-sectional view cut along the line E-E′ inFIG. 25A.FIG. 25Cis a cross-sectional view cut along the line B-B′ inFIG. 25A.FIG. 25Dis a cross-sectional view cut along the line C-C′ inFIG. 25A.

As illustrated inFIG. 25A through 25D, in this step, similar to the step ofFIGS. 11A through 11D, the Si—Ge mixed layer regions SG1through SG3are selectively etched and removed, so that voids21V1through21V3corresponding to the Si—Ge mixed layer regions SG1through SG3are formed.

In this embodiment, similar to the first embodiment, by not only forming the device isolation groove (first trench)21tbut also forming the second trench21uin the epitaxial layers21ep2, it may become possible to promote gas flow of etching gas along the arrow directions illustrated inFIGS. 25A through 25D.

As a result, the gas flow to etch the Si—Ge mixed layer SG2under the epitaxial layers21ep2may be promoted. The etching of the Si—Ge mixed layer SG2under the epitaxial layers21ep2may be much difficult without the formed second trench21u. Namely, it may become possible to more effectively (promote to) etch not only the Si—Ge mixed layers SG1and SG2but also the Si—Ge mixed layers SG3.

FIGS. 26A through 26Dillustrate a step of the manufacturing process of the semiconductor device20according to the second embodiment following the step ofFIGS. 25A through 25D. Specifically,FIG. 26Ais a top view corresponding toFIG. 25A.FIG. 26Bis a cross-sectional view cut along the line E-E′ inFIG. 26A.FIG. 26Cis a cross-sectional view cut along the line B-B′ inFIG. 26A.FIG. 26Dis a cross-sectional view cut along the line C-C′ inFIG. 26A.

As illustrated inFIG. 26A through 26D, this step corresponds to the steps ofFIG. 12AthroughFIG. 12DandFIG. 13AthroughFIG. 13D. Namely, the voids21V1,21V2, and21V3are filled with the embedded isolation films261,262, and263, respectively.

FIGS. 27A through 27Dillustrate a step of the manufacturing process of the semiconductor device20according to the second embodiment following the step ofFIGS. 26A through 26D. Specifically,FIG. 27Ais a top view corresponding toFIG. 26A.FIG. 27Bis a cross-sectional view cut along the line E-E′ inFIG. 27A.FIG. 27Cis a cross-sectional view cut along the line B-B′ inFIG. 27A.FIG. 27Dis a cross-sectional view cut along the line C-C′ inFIG. 27A.

As illustrated inFIG. 27A through 27D, in this step of this embodiment, polysilocon gate electrodes23A and23B similar to those ofFIGS. 6A through 6Dare formed on the mesa structures MA and MB of the silicon substrate11via the gate isolation films22A and22B, respectively.

Further, similar to the step ofFIGS. 15A through 15D, the ion implantation is performed by using the polysilocon gate electrodes23A and23B as masks to form the source extension regions21aand the drain extension region21bof the first MOS transistor20A and the source extension regions21cand the drain extension region21dof the second MOS transistor20B. In this embodiment, the drain extension region21band the source extension regions21cconstitute (form) a single contiguous (the same) diffusion region.

After that, by executing the steps ofFIGS. 16A through 16D,FIGS. 17A through 17D, andFIGS. 18A through 18D, the semiconductor device having the structure ofFIGS. 1A and 1Dmay be acquired (formed).

In this embodiment as well, by forming the hole (opening) (i.e., the second trench)21uin the epitaxial layers21ep2, it may become possible to effectively remove Si—Ge mixed layer regions SG1through SG3from under the silicon epitaxial layers21ep1through21ep3, respectively, in the step ofFIGS. 25A through 25D.

Namely, the semiconductor device may be more effectively formed (manufactured). Further, in the step ofFIGS. 26A through 26D, it may become possible to improve the efficiency of filling the voids21V1,21V2, and21V3with the embedded isolation films261,262, and263, respectively.

Further, in the semiconductor device20as formed as described above, in each of the first MOS transistor20A and the second MOS transistor20B, the first channel region21Cha and the second channel region21Chb are formed in the mesa structures MA and MB, respectively, which are originally a part of the silicon substrate11having higher quality, and which are not formed based on any of the silicon epitaxial layers21ep1,21ep2, and21ep3which are grown later. Therefore, it may become possible to form the semiconductor (channel) regions having higher crystal quality and prevent carriers from being scattered or extinguished due to a defect or an impurity element.

In the above embodiments, it is basically assumed that the silicon substrate11is p-type substrate. However, obviously, the above embodiments may also be applied to a case where the silicon substrate11is n-type simply by reversing the conductivity type in each of the layers.

According to an embodiment, a semiconductor device include a semiconductor substrate; a device region formed on the semiconductor substrate, defined by a device isolation region, and including a first device region part and a second device region part; a first gate electrode formed in the first device region part; a first source region formed on a first side of the first gate electrode in the first device region part; a first drain region formed on a second side of the first gate electrode in the first device region part; a second gate electrode formed in the second device region part; a second source region formed on a first side of the second gate electrode in the second device region part; a second drain region formed on a second side of the second gate electrode in the second device region part; a first embedded isolation film region formed under the first source region; a second embedded isolation film region formed under the first drain region; a third embedded isolation film region formed under the second source region; and a fourth embedded isolation film region formed under the second drain region. Further, the first drain region and the second source region constitute (form) a single (the same) diffusion region between the first gate electrode and the second gate electrode. Further, the second embedded isolation film region and the third embedded isolation film region constitute (form) a single (the same) embedded isolation film region between the first gate electrode and the second gate electrode. Further, between the first gate electrode and the second gate electrode, an opening is formed in a part of the diffusion region including (forming) the first drain region and the second source region, so that the opening extends to (reaches) the second embedded isolation film region and the third embedded isolation film region. Further, the opening is filled with an isolation film.

According to an embodiment, a depth of the opening may be substantially the same as a depth of the device isolation region.

According to an embodiment, the opening may extend to (reach) the semiconductor substrate under the embedded isolation film region.

According to an embodiment, between the first gate electrode and the second gate electrode, the opening may be formed in a manner that the opening is arranged in a line with via plugs formed to be in contact with the first drain region and the second drain region.

According to an embodiment, the size of the opening on the surface of the semiconductor substrate is substantially the same as that of the via plugs on the surface of the semiconductor substrate.

According to an embodiment, the first embedded isolation film region may be contiguous to the device isolation region in a part of the outer circumference of the first device region part, and the second embedded isolation film region may be contiguous to the device isolation region in a part of the outer circumference of the second device region part

According to an embodiment, a method of manufacturing a semiconductor device include forming a device isolation groove on a semiconductor substrate to define a device region including a first device region part and a second device region part which are adjacent to each other by the device isolation groove; forming a hole at a contacting part between the first device region part and a second device region part of the device region; filling the device isolation groove and the hole with a first isolation film, to form a first isolation film region in the device isolation groove and a second isolation film region in the hole; forming a first gate electrode and a second gate electrode in a manner that the first gate electrode is formed in the first device region part and the second gate electrode is formed in the second device region part and the first gate electrode is formed on a first side of the second gate electrode and the second gate electrode is formed on a second side of the first gate electrode; forming a first side wall isolation film and a second side wall isolation film in a manner that the first side wall isolation film is formed on each of first and second sides of the first gate electrode, the second side being opposite to the first side, and a second side wall isolation film is formed on each of the first side and the second side of the second gate electrode; etching the semiconductor substrate by using the first gate electrode and the first side wall isolation film in the first device region part and the second gate electrode and the second side wall isolation film in the second device region part as masks, to form first, second, third, and fourth trenches in a manner that in the first device region part, the first trench is formed on the first side of the first gate electrode so that the first trench is contiguous to a part of the device isolation groove in the first side of the first gate electrode and a part of the first isolation film region is exposed, the second trench is formed on the second side of the first gate electrode so that the second trench is contiguous to a part of the hole in the second side of the first gate electrode and a part of the second isolation film region is exposed, and in the second device region part, the third trench is formed on the first side of the second gate electrode so that the third trench is disposed on the first side of the second gate electrode and is contiguous to a part of the hole so that a part of the second isolation film region is exposed, the fourth trench is formed on the second side of the second gate electrode so that the fourth trench is contiguous to a part of the device isolation groove in the second side of the second gate electrode and a part of the first isolation film region is exposed, and the second trench is contiguous to the third trench in a connecting part between the first device region part and the second device region part; filling lower parts of the first, the second, the third, and the fourth trenches with a first semiconductor layer having etching selectivity relative to the semiconductor substrate; forming a second semiconductor layer on the first semiconductor layer in the first, the second, the third, and the fourth trenches, the second semiconductor layer having etching selectivity relative to the first semiconductor layer, to fill the first, the second, the third, and the fourth trenches up to at least a surface of the semiconductor substrate; removing the first isolation film region through the device isolation groove and the second isolation film region through the hole, to expose the first semiconductor layer and the second semiconductor layer in the device isolation groove and the hole; selectively etching and removing the first semiconductor layer relative to the semiconductor substrate and the second semiconductor layer through the device isolation groove and the hole to form a void in a part where the first semiconductor layer had been formed in the first, the second, the third, and the fourth trenches; filling with the void with a third semiconductor layer in the first, the second, the third, and the fourth trenches, so that first, second, third, and fourth embedded isolation film regions are formed under the second semiconductor layers in the first, the second, the third, and the fourth trenches, respectively, a device isolation region is formed in the device isolation groove, and an isolation film region is formed in the hole; removing the first side wall isolation film and the second side wall isolation film; performing ion implantation by introducing an impurity element by using the first gate electrode in the first device region part an the second gate electrode in the second device region part as masks after the first side wall isolation film and the second side wall isolation film are removed, to form a source extension region and a drain extension region of a first transistor to be formed in the first device region part, the source extension region and the drain extension region being formed on the first side and the second side, respectively, of the first gate electrode, and a source extension region and a drain extension region of a second transistor to be formed in the second device region part, the source extension region and the drain extension region being formed on the first side and the second side, respectively, of the second gate electrode; forming a third side wall isolation film on each of the first and the second sides of the first gate electrode and a fourth side wall isolation film on each of the first and the second sides of the second gate electrode; and introducing an impurity element by using the first electrode, the second electrode, the third side wall isolation film, and the fourth side wall isolation film as masks to form a source region of the first transistor in the second semiconductor layer formed in the first trench, a drain region of the first transistor in the second semiconductor layer formed in the second trench, a source region of the second transistor in the second semiconductor layer formed in the third trench, and a drain region of the second transistor in the second semiconductor layer formed in the fourth trench.

According to an embodiment, a method of manufacturing a semiconductor device includes forming a region to be a first active region of a first transistor and a region to be a second active region of a second transistor in a manner that the first active region is formed by using a first mask pattern, the first active region being included in a first device region part where the first transistor including a first gate electrode is to be formed, the first device region being included in a semiconductor substrate surface, and the second active region is formed by using a second mask pattern, the second active region being included in a second device region part where the second transistor including a second gate electrode is to be formed, the second device region being included in a semiconductor substrate surface, the first mask pattern being disposed on a first side of the second mask pattern, the second mask pattern being disposed on a second side of the first mask pattern; etching the semiconductor substrate using the first mask pattern and the second mask pattern as masks to form first, second, third, and fourth trenches in a manner that the first trench is formed on the first side of the first mask pattern, the second trench is formed on the second side of the first mask pattern, the second side being opposite to the first side of the first mask pattern, the third trench is formed on the first side of the second mask pattern, the fourth trench is formed on the second side of the second mask pattern, and the second trench is contiguous to the third trench; filling lower parts of the first, the second, the third, and the fourth trenches with a first semiconductor layer having etching selectivity relative to the semiconductor substrate; forming a second semiconductor layer on the first semiconductor layer in the first, the second, the third, and the fourth trenches, the second semiconductor layer having etching selectivity relative to the first semiconductor layer, to fill the first, the second, the third, and the fourth trenches at least up to a surface of the semiconductor substrate; forming a device isolation groove and a hole in the semiconductor substrate in a manner that the device isolation groove defines a device region including the first, the second, the third, and the fourth trenches, the hole is formed at a boundary between the first device region part where the first transistor is to be formed in the device region and the second device region part where the second transistor is to be formed in the device region, the second semiconductor layer formed in the first trench is exposed through the device isolation groove, the second semiconductor layer formed in the fourth trench is exposed through the device isolation groove, and the second semiconductor layer formed on the second trench and the second semiconductor layer formed in the third trench are disposed through the hole; selectively etching and removing the first semiconductor layer from the first and the fourth trenches through the device isolation groove and the first semiconductor layer from the second and the third trenches through the hole relative to the semiconductor substrate and the second semiconductor layer, to form a void in parts where the first semiconductor layer had been formed in the first, the second, the third, and the fourth trenches; filling the void in the first, the second the third, and the fourth trenches with a third isolation film through the device isolation groove and the hole, to form first, second, third, and fourth embedded isolation film region in a manner that the first, the second, the third, and the fourth embedded isolation film regions are formed under the second semiconductor layer in the first, the second, the third, and the fourth trenches, respectively; forming first and second gate electrodes in the first and the second active regions, respectively, via respective gate isolation films in a manner that the first gate electrode is formed on the first side of the second gate electrode and the second gate electrode is formed on the second side of the first gate electrode; performing ion implantation by introducing an impurity element by using the first gate electrode in the first active region and the second gate electrode in the second active region as masks, to form a source extension region and a drain extension region of the first transistor on the first side and the second side, respectively, of the first gate electrode in the first active region, and a source extension region and a drain extension region of the second transistor on the first side and the second side, respectively, of the second gate electrode in the second active region, forming first and second side wall isolation films in a manner that the first side wall isolation film is formed on each of the first and the second sides of the first gate electrode and the second side wall isolation film is formed on each of the first and the second sides of the second gate electrode; and introducing impurity element by using the first and the second gate electrodes and the first and the second side wall isolation films as masks, to form a source region of the first transistor in the second semiconductor layer in the first trench, a drain region of the first transistor in the second transistor layer in the second trench, a source region of the second transistor in the second semiconductor layer in the third trench, and a drain region of the second transistor in the second semiconductor layer in the fourth trench.

According to an embodiment, the hole may be simultaneously formed with the device isolation groove.

According to an embodiment, the hole may be separately formed from the device isolation groove.

According to an embodiment, the size and the figure of the hole may be substantially the same as those of a via plug to be formed between the first and the second gate electrodes.

According to an embodiment, as the first through the fourth side wall isolation films, a silicon oxide film may be used.

According to an embodiment, the first through the fourth side wall isolation films may be formed by a vapor-phase deposition method.

According to an embodiment, the semiconductor substrates may be a silicon substrate, the first semiconductor layer may be a Si—Ge mixed layer, the second semiconductor layer may be a silicon layer, and the first and the second semiconductor layers may be epitaxially grown on the silicon substrate.

According to an embodiment, in a semiconductor device in which the source region of the first transistor and the drain region of the second transistor constitute (form) a single (the same) diffusion region, it may become possible to easily and selectively remove the first semiconductor layer under the second semiconductor layer through the second trench, the first semiconductor layer having etching selectivity relative to the second semiconductor layer, the source and the detain regions of the first and the second transistors being formed in the second semiconductor layer. Further, it may become possible to easily form a void under each of the source and the detain regions of the first and the second transistors. Further, the void may be easily filled with an embedded isolation film through the second trench.