Semiconductor device including heat dissipating structure

A semiconductor device includes a substrate serving as a base and having a surface on which electrodes are provided, a semiconductor chip mounted to the surface of the substrate, a sealing portion sealing the semiconductor chip and the surface of the substrate, first vias each penetrating the sealing portion in a thickness direction of the sealing portion to reach the electrodes on the surface of the substrate, external terminals connected to the first vias, and second vias provided near the semiconductor chip, extending to such a depth that the second vias do not penetrate the sealing portion, and insulated from the substrate and the semiconductor chip.

BACKGROUND

The present disclosure relates to semiconductor devices including heat dissipating structures, in particular to a semiconductor device including a semiconductor chip packaged on a base with resin sealing.

In recent years, with a higher integration density of integrated circuits on a semiconductor chip and a higher processing speed, the amount of heat generation from the semiconductor chip has been increased. In order to prevent malfunction or abnormal operation due to such heat from a semiconductor chip, the importance of a heat dissipating structure in the semiconductor device increases.

Japanese Unexamined Patent Publication No. 2003-7910 describes a semiconductor device as illustrated inFIG. 15Ain which a back surface of a semiconductor chip107mounted to a substrate1is polished together with a ball108aand a sealing portion3, so that the back surface is exposed to dissipate heat generated from the substrate1and the semiconductor chip107. Alternatively, as illustrated inFIG. 15B, substrate via holes134are formed in the semiconductor chip107mounted to the substrate1, and balls124exposed from the sealing portion3are in contact with the back surface of the semiconductor chip107, so that heat from the semiconductor chip107is efficiently dissipated.

SUMMARY

However, in the semiconductor device of Japanese Unexamined Patent Publication No. 2003-7910 illustrated inFIG. 15A, the sealing portion is polished together with the substrate and the ball. Therefore, due to stress during polishing, cracks may be formed in the substrate, the balls, and the sealing portion, or the substrate, the ball, and the sealing portion may be detached from each other at the interface therebetween. Thus, manufacturing and reliability problems may arise. Exposing the semiconductor chip by polishing the sealing portion protecting the semiconductor chip results in a reliability problem where resistance to stress during secondary packaging and water resistance are reduced.

In assembling the semiconductor device of Japanese Unexamined Patent Publication No. 2003-7910 illustrated inFIG. 15B, a terminal made of a hard material such as metal is externally brought into contact with a pad on the back surface of the semiconductor chip. Therefore, stress is applied to the semiconductor chip and a peripheral structure of the semiconductor chip. This may lead to the reliability problem. The semiconductor chip is structured such that a pad connected to the ball exposed from the sealing portion is provided on the back surface of the semiconductor chip, and the pad is further connected to a through via extending from an element surface to the back surface of the semiconductor chip. With this structure, the through via restricts a region of the element surface of the semiconductor chip on which elements are arranged, so that the area of the semiconductor chip is increased. Additionally, the through via also restricts the layout design of the interior of the semiconductor chip, which may also produce undesirable results including an increase in interconnection delay.

Therefore, the present disclosure is generally directed to a structure capable of improving heat dissipation of a semiconductor device without deteriorating the reliability and the performance of the semiconductor device. The present disclosure is also directed to a heat dissipating structure which does not restrict the design of the semiconductor chip and has a high degree of freedom so that an arrangement pattern is freely changed depending on heat generation.

A first semiconductor device of the present disclosure includes: a base having a first surface, a second surface opposite to the first surface, and electrodes on the first surface; a first semiconductor chip mounted to the first surface of the base; a sealing portion sealing the first semiconductor chip and the first surface of the base; a plurality of first vias penetrating the sealing portion from a surface of the sealing portion in a thickness direction of the sealing portion and each electrically connected to a corresponding one of the electrodes on the first surface of the base; a plurality of first external terminals provided on the surface of the sealing portion and each connected to a corresponding one of the first vias; a plurality of second vias located inwardly from the first vias and extending from the surface of the sealing portion in the thickness direction of the sealing portion to such a depth that the second vias do not penetrate the sealing portion; and a plurality of second external terminals provided on the surface of the sealing portion and each connected to a corresponding one of the second vias; wherein the second vias are not in contact with the first semiconductor chip.

According to the semiconductor device of the present disclosure, the second vias are arranged in the periphery of the semiconductor chip which is a heat source, in particular, near the side surface of the semiconductor chip. Thus, heat from the heat source (the semiconductor chip) is efficiently transferred in the sealing portion to thermal conductors (the vias). Therefore, the heat dissipation can be improved. The heat conducting path extending from the second vias to the external terminals is perpendicular to the principal surface of the base and is thus the shortest path to the outside of the semiconductor device. Therefore, heat can be efficiently dissipated also in the case of the semiconductor device in which a semiconductor chip is packaged by resin sealing.

The semiconductor chip is protected by the sealing portion, and the heat conducting path for heat dissipation is in contact with neither the substrate nor the semiconductor chip. Thus, the heat dissipation can be improved without deteriorating the reliability or the performance of the semiconductor device.

The second vias do not penetrate the sealing portion and are thus insulated from the first substrate. Thus, it is no longer necessary to provide an electrode on the surface of the first substrate to connect the via, so that the heat dissipation can be improved without limiting the design of the semiconductor chip. The depth of each second via can be adjusted such that the second via reaches neither the semiconductor chip nor the substrate. Thus, the second vias can be arranged almost anywhere in the sealing portion, so that the heat dissipating structure having a high degree of freedom depending on heat generated from the semiconductor chip is possible.

A semiconductor device assembly of the present disclosure includes: a mounting substrate having a surface on which a wiring pattern is formed, wherein the first external terminals and the second external terminals of the first semiconductor device are electrically connected to electrodes of the mounting substrate, the electrodes being fixed at a constant electric potential.

According to the semiconductor device assembly of the present disclosure, release of electric noise generated from the semiconductor chip to lateral sides of the semiconductor device can be reduced, and noise from the mounting substrate and the outside of the semiconductor device is reduced, so that the semiconductor chip can be stably operated.

According to the present disclosure, a resin sealed semiconductor device whose reliability and performance are not deteriorated can be provided with the heat dissipation being improved.

DETAILED DESCRIPTION

The semiconductor device and the electronic component of the present disclosure will be described with reference to the drawings.

First Embodiment

FIGS. 1A and 1Bare respectively a cross-sectional view and a plan view schematically illustrating a semiconductor device according to the present embodiment.

A semiconductor device100illustrated inFIG. 1Aincludes a substrate1, a semiconductor chip2mounted to an upper surface of the substrate1, a sealing portion3sealing the upper surface of the substrate1and the semiconductor chip2, first vias4penetrating the sealing portion3in a thickness direction of the sealing portion3, second vias5extending in the thickness direction of the sealing portion3, external terminals6aconnected to the first vias4, and external terminals6bconnected to the second vias5.

On the upper surface of the substrate1, a wiring pattern (not shown) is formed. The wiring pattern includes electrodes (not shown) electrically connected to the semiconductor chip and the first vias4. It is sufficient that the substrate1serves as a base to which a semiconductor chip will be mounted. The substrate1is not limited to a circuit board and may be a lead frame.

The semiconductor chip2is flip-chip mounted to the upper surface of the substrate1via a plurality of bumps7. A principal surface of the semiconductor chip2, that is, a surface on which the bumps7are bonded, has an active region in which an integrated circuit including a transistor, a capacitor, etc. is formed.

The sealing portion3covers the semiconductor chip2and is provided on the upper surface of the substrate1. The sealing portion3is an insulator such as a resin.

Through holes extending in the thickness direction of the sealing portion3from the electrode on the upper surface of the substrate1to an upper surface of the sealing portion3are formed in the sealing portion3. The through holes are filled with a conductive substance, thereby forming the first vias4. On the surface of the sealing portion3opposite to the substrate1, the external terminals6aare arranged to be in contact with the first vias4. That is, one end of each first via4is connected to the electrode on the upper surface of the substrate1, and the other end is connected to a corresponding one of the external terminals6aexposed from the sealing portion3. Through this electric pathway, the function of the semiconductor chip2is utilized from outside of the semiconductor device100.

Recessed portions are formed in the sealing portion3at positions located outwardly from (outside) the semiconductor chip2, in particular, near a side surface of the semiconductor chip2. The recessed portions extend in the thickness direction of the sealing portion3to such a depth that the recessed portions do not reach the wiring pattern on the substrate1. The recessed portions having such a depth that the recessed portion do not reach the wiring pattern on the substrate1are filled with a conductive substance, thereby forming the second vias5. The second vias5are in contact with neither the substrate1nor the semiconductor chip2. The second vias5are insulated from the substrate1and the semiconductor chip2. On the surface of the sealing portion3, the external terminals6bare arranged to be in contact with the second vias5. Heat generated from the semiconductor chip2is dissipated through a heat conducting paths formed by the second vias5formed near the side surface of the semiconductor chip2and the external terminals6bto the outside of the semiconductor device100.

At least either of the first vias4or the second vias5may be structured such that a metal thin film is formed on an inner surface of the through holes or the recessed portions.

The semiconductor device100is mounted to a mounting substrate (not shown) via the external terminals6a,6bto obtain an assembly. Heat generated from the semiconductor chip2is transferred to the mounting substrate of the assembly mainly via the second vias5and the external terminals6b, so that the heat is dissipated to the outside of the semiconductor device100.

On an upper surface of the semiconductor device100illustrated inFIG. 1B, the external terminals6a,6bare arranged on the surface of the sealing portion3. The external terminals6bare arranged at positions located outwardly from the semiconductor chip2, preferably, near the semiconductor chip2to surround the semiconductor chip2. The external terminals6aare arranged outside the external terminals6b. The external terminals6amay be arranged in an outer edge region of the semiconductor device100. Each of the external terminals6ais connected to a corresponding one of the first vias4in the sealing portion3, and each of the external terminals6bis connected to a corresponding one of the second vias5in the sealing portion3.

With this configuration, the second vias5are arranged in the periphery of the semiconductor chip2serving as a heat source, in particular, near the side surface of the semiconductor chip2. Thus, heat from the heat source (the semiconductor chip) is efficiently transferred to thermal conductors (the vias) in the sealing portion3, so that the heat dissipation can be improved. Moreover, the heat conducting path from the second vias5to the external terminals6bis perpendicular to the principal surface of the substrate1and is thus the shortest path to the outside of the semiconductor device100. Thus, efficient heat dissipation is possible also in the case of the resin sealed semiconductor device100in which the semiconductor chip2is not exposed.

The semiconductor chip2is protected by the sealing portion3, and the heat conducting path for heat dissipation is in contact with neither the substrate1nor the semiconductor chip2. Thus, the heat dissipation can be improved without deteriorating the reliability and the performance of the semiconductor device100.

The second vias5do not penetrate the sealing portion3and are thus insulated from the substrate1. Therefore, it is no longer necessary to provide electrodes to be connected to the vias on the surface of the substrate1. Thus, without limiting the design of the semiconductor chip, the heat dissipation can be improved. Furthermore, the depth of each second via5can be adjusted so that the second via5reaches neither the semiconductor chip2nor the substrate1. Thus, the second vias5can be arranged almost anywhere in the sealing portion3. Thus, it is possible to obtain a heat dissipating structure having a very high degree of freedom depending on heat generation from the semiconductor chip2.

Here, all the external terminals6aarranged at an outer circumference section of the semiconductor chip2are not necessarily connected to the electrodes on the substrate1via the first vias4. For example, a dummy external terminal which is not electrically continuous with the electrode on the substrate1may be included. The dummy external terminal may be connected to, for example, a via which does not penetrate the sealing portion3.

The external terminals6barranged near the semiconductor chip2may include an external terminal connected to a via penetrating the sealing portion3. In this case, on the upper surface of the substrate1, an electrode connected to the via is provided near a mounting region of the semiconductor chip2. Usually, interconnects drawn out from the semiconductor chip2are concentrated near the mounting region of the semiconductor chip2, and thus a region for an electrode connected to a via and an interconnect connected to the electrode has to be ensured. This complicates the interconnection of the substrate1. Moreover, a limitation on the arrangement of the vias, for example, excess of an underfill material or a dice bonding material used for mounting the semiconductor chip2, is also found near the mounting region of the semiconductor chip2. Therefore, arranging only through vias connected to the electrodes on the substrate1near the semiconductor chip2is not practical because of the limitations on interconnect design and via arrangement. That is, in order to obtain the effect of improving the heat dissipation, many of the vias connected to the external terminals6ahave to be the second vias5which do not penetrate the sealing portion3.

(First Variation of First Embodiment)

FIGS. 2A and 2Bare respectively a cross-sectional view and a plan view schematically illustrating a semiconductor device according to a first variation.

In the first embodiment, the heat conducting path from the semiconductor chip2to the outside of the semiconductor device100is formed by the second vias5in the sealing portion3and the external terminals6beach connected to a corresponding one of the second vias5and arranged on the surface of the sealing portion3. As illustrated inFIG. 2A, a semiconductor device110of the present variation includes a heat dissipating body8on the surface of the sealing portion3.

The heat dissipating body8is provided to cover a back surface of the semiconductor chip2(a surface opposite to a surface of the semiconductor chip2via which the semiconductor chip2is mounted to the substrate1). The width of the heat dissipating body8is greater than the width of the semiconductor chip2when viewed in section. The heat dissipating body8is connected to the second vias5and the external terminals6b. The heat dissipating body8is in contact with neither the substrate1nor the semiconductor chip2and is thus insulated from the substrate1and the semiconductor chip2. A heat conducting path formed by the second vias5formed near the side surface of the semiconductor chip2, the heat dissipating body8formed to face the back surface of the semiconductor chip2, and the external terminals6bdissipates heat generated from the semiconductor chip2to the outside of the semiconductor device110.

The heat dissipating body8may be a metal film or a sheet having conductivity. In order to improve the heat dissipation, the heat dissipating body8may be a substance having high thermal conductivity.

On an upper surface of the semiconductor device110illustrated inFIG. 2B, the external terminals6a,6band the heat dissipating body8are arranged on the sealing portion3. The heat dissipating body8may be closely contacted with the surface of the sealing portion3.

With this configuration, a heat conducting path for transferring heat generated from the semiconductor chip2from the sealing portion3via the heat dissipating body8on the surface of the sealing portion3to the second vias5and the external terminals6bis formed in addition to the heat conducting path from the sealing portion3via the second vias5and the electrodes6bto the outside of the semiconductor device110, for example, to the mounting substrate, or the like. That is, a plurality of heat conducting paths in a side surface direction and in a back surface direction of the semiconductor chip2are provided to the semiconductor chip2. Therefore, the heat dissipation can be further improved in addition to the effect of the first embodiment.

(Second Variation of First Embodiment)

FIGS. 3A and 3Bare respectively a cross-sectional view and a plan view schematically illustrating a semiconductor device according to a second variation.

In the first embodiment, the semiconductor chip2is flip chip connected to the upper surface of the substrate1via the bumps7. As illustrated inFIG. 3A, a semiconductor device120of the present variation includes a semiconductor chip9electrically connected to the electrode on the substrate1via a plurality of wires10. The wires10can be wires containing, for example, gold, copper, or the like as a main component.

On an upper surface of the semiconductor device120illustrated inFIG. 3B, the external terminals6a,6bare arranged on the sealing portion3. The second vias5connected to the external terminals6bdo not penetrate the sealing portion3, and the depth of the second vias5can be adjusted, so that each second via5can be disposed between the wires10in a region in which the wires10are arranged.

With this configuration, short heat conducting paths can also be provided for the wire bonding-type semiconductor device120. Therefore, in a manner similar to the first embodiment, the heat dissipation can be improved.

(Third Variation of First Embodiment)

A semiconductor device130illustrated inFIG. 4Aincludes a semiconductor chip9electrically connected to a substrate1via wires10in a manner similar to the second variation and further includes a heat dissipating body8arranged on the surface of the sealing portion3. Also in this case, as illustrated inFIG. 4B, each of the external terminals6bcan be disposed between the wires10. With this configuration, a plurality of heat conducting paths in a side surface direction and in a back surface direction of the semiconductor chip9can be provided to the semiconductor chip9. Therefore, also in the wire bonding-type semiconductor device130, the heat dissipation can be improved.

Second Embodiment

FIG. 5is a cross-sectional view schematically illustrating an assembly of a semiconductor device according to a second embodiment.

In the first embodiment, the semiconductor device100is mounted to the mounting substrate via the external terminals6a,6b. As illustrated inFIG. 5, an assembly200of the present embodiment includes a constant electric potential supply12provided in a mounting substrate11.

The constant electric potential supply12in the mounting substrate11may have a form of an interconnect or a form of a plane. The constant electric potential supply12may be a metal film or an interconnect made of copper or aluminum. The electric potential of the constant electric potential supply12in the mounting substrate11is a power supply voltage or a ground voltage and is fixed at a predetermined electric potential (constant electric potential).

The constant electric potential supply12formed in the mounting substrate11is bonded to external terminals6bformed on a sealing portion3by solder, or the like, thereby fixing second vias5formed in the sealing portion3and the external terminals6bat the constant electric potential.

Rendering the second vias5and the external terminals6belectrically continuous with the constant electric potential supply12allows the second vias5and the external terminals6bto serve as an electric shield as well as the heat conducting path.

The second vias5are arranged along all sides of the semiconductor chip2, so that the effect of the shield can be increased.

This configuration provides the effect of the first embodiment and can also reduce release of electric noise generated from the semiconductor chip2to lateral sides of the semiconductor device200. Additionally, this configuration reduces noise from the mounting substrate11and the outside of the semiconductor device200, so that the semiconductor chip2can be stably operated.

Similar to the variations of the first embodiment, a heat dissipating body8(not shown) may be further provided to cover a back surface of the semiconductor chip2. With this configuration, the heat dissipating body8is electrically continuous with the second vias5and the external terminals6b. Thus, the heat dissipating body8is also fixed at the constant electric potential. That is, rendering the second vias5, the external terminals6b, and the heat dissipating body8electrically continuous with the constant electric potential supply12in the mounting substrate11allows the second vias5, the external terminals6b, and the heat dissipating body8to serve as an electric shield covering a side surface and the back surface of the semiconductor chip2as well as the heat conducting path. Thus, the effect of the shield can be further increased.

(Variation of Second Embodiment)

FIG. 6is a cross-sectional view schematically illustrating an assembly of a semiconductor device according to a variation.

In the second embodiment, the electric shield formed by the second vias5and the external terminals6band the electric shield further including the heat dissipating body8in addition to the second vias5and the external terminals6bare described. As illustrated inFIG. 6, an assembly210of the present variation includes a conductor13provided between the mounting substrate11and the heat dissipating body8. The conductor13may be a paste made of a conductive substance or a metal plate, or may be a metal thin film or a metal sheet.

With this configuration in which the conductor13is provided, the thickness of the electric shield formed by the second vias5, the external terminals6b, and the heat dissipating body8is increased. Thus, release of electric noise generated from a semiconductor chip2to the outside of the semiconductor device can be more effectively reduced. With this configuration, noise from the outside of the mounting substrate11and the semiconductor device is reduced, so that the semiconductor chip2can be stably operated.

Moreover, the conductor13is provided, so that the area at which the external terminals6band the heat dissipating body8are in contact with the mounting substrate11is increased. Thus, the volume of the heat conducting path from the semiconductor device to the mounting substrate11is increased, which further improves the heat dissipation.

Third Embodiment

FIGS. 7A and 7Bare respectively a cross-sectional view and a plan view schematically illustrating a configuration of a semiconductor device according to a third embodiment.

The first embodiment includes the second vias5provided at positions located outwardly from the semiconductor chip2, in particular, near the semiconductor chip2and the external terminals6bconnected to the second vias5as a heat conducting path through which heat generated from the semiconductor chip2is dissipated. As illustrated inFIG. 7A, a semiconductor device300of the present embodiment includes a plurality of recessed portions formed in a region facing a back surface of a semiconductor chip2in a sealing portion3. The recessed portions extend in a thickness direction of the sealing portion3to such a depth that the recessed portions do not reach the back surface of the semiconductor chip2. The recessed portions are filled with a conductive substance, thereby forming a plurality of third vias14. The third vias are in contact with neither the semiconductor chip2nor a substrate1and are thus insulated from the semiconductor chip2and the substrate1. On a surface of the sealing portion3, external terminals6cconnected to the third vias14are provided.

Heat generated from the semiconductor chip2is transferred to a mounting substrate (not shown) mainly via the second vias5and the external terminals6band via the third vias14and the external terminals6c, so that the heat is dissipated to the outside of the semiconductor device300.

On an upper surface of the semiconductor device300illustrated inFIG. 7B, external terminals6a,6band the external terminals6care arranged on the sealing portion3.

The external terminals6bare arranged at positions located outwardly from the semiconductor chip2or near the semiconductor chip2to surround the semiconductor chip2. The external terminals6aare arranged outside the external terminals6b. The external terminals6amay be arranged in an outer edge region of the semiconductor device300. Each of the external terminals6ais connected to a corresponding one of the first vias4in the sealing portion3, and each of the external terminals6bis connected to a corresponding one of the second vias5in the sealing portion3.

The external terminals6care arranged in a region located inwardly from the external terminals6band overlapping the semiconductor chip2when viewed in plan. Each of the external terminals6cis connected to a corresponding one of the third vias14in the sealing portion3.

With this configuration, the second vias5are arranged in the periphery of the semiconductor chip2which is a heat source, in particular, near a side surface of the semiconductor chip2. The third vias14are further arranged near the back surface of the semiconductor chip2. That is, in the sealing portion3, heat from the heat source (semiconductor chip2) is efficiently transferred from the side surface and the back surface of the semiconductor chip2to thermal conductors (the vias), so that the heat dissipation can be improved. The heat conducting path from the second vias5to the external terminals6band the heat conducting path from the third vias14to the external terminals6care both perpendicular to a principal surface of the substrate1and are thus the shortest paths to the outside of the semiconductor device300. Therefore, efficient heat dissipation is possible even in the case of a resin sealed semiconductor device in which the semiconductor chip2is not exposed.

(Variation of Third Embodiment)

FIGS. 8A and 8Bare respectively a cross-sectional view and a plan view schematically illustrating a semiconductor device according to a variation.

In the third embodiment, the heat conducting paths from the semiconductor chip2to the outside of the semiconductor device300are formed by the second vias5and the third vias14in the sealing portion3, and the external terminals6b,6cconnected to the second vias5and the third vias14, respectively and arranged on the surface of the sealing portion3. As illustrated inFIG. 8A, a semiconductor device310of the present variation further includes a heat dissipating body15provided on the surface of the sealing portion3. The heat dissipating body15has a larger plane area than a semiconductor chip2and is connected to the second vias5, the third vias14, and the external terminals6b,6c.

The heat dissipating body15is provided to cover the back surface of the semiconductor chip2and has a larger width than the semiconductor chip2when viewed in cross section. The heat dissipating body15is connected to the second vias5, the third vias14, and the external terminals6b,6c. The heat dissipating body15is in contact with neither a substrate1nor the semiconductor chip2and is thus isolated from the substrate1and the semiconductor chip2. These heat conducting paths formed by the second vias5formed near the side surface of the semiconductor chip2, the third vias14formed near the back surface of the semiconductor chip2, the heat dissipating body15, and the external terminals6b,6cdissipate heat generated from the semiconductor chip2to the outside of the semiconductor device310.

The heat dissipating body15may be a metal film or a sheet having conductivity. In order to improve the heat dissipation, the heat dissipation body15may be a substance having high thermal conductivity.

On the upper surface of the semiconductor device310illustrated inFIG. 8B, the external terminals6a,6b,6c, and the heat dissipating body15are arranged on the sealing portion3. The heat dissipating body15may be in close contact with the surface of the sealing portion3.

With this configuration, a heat conducting path through which heat generated from the semiconductor chip2is transferred from the sealing portion3to the second vias5, the third vias14, and the external terminals6b,6cvia the heat dissipating body15on the surface of the sealing portion3is formed in addition to the heat conducting paths for dissipating the heat from the sealing portion3to the mounting substrate (not shown), or the like outside the semiconductor device310via the second vias5and the external terminals6b, and via the third vias14and the external terminals6c. Thus, the heat dissipation can be further improved.

Fourth Embodiment

FIG. 9is a cross-sectional view schematically illustrating a configuration of a semiconductor device according to a fourth embodiment.

In the semiconductor device100of the first embodiment, the back surface of the semiconductor chip2is covered with the sealing portion3whose surface is flat. As illustrated inFIG. 9, a semiconductor device400of the present embodiment includes a sealing portion16in which an opening17is formed and a semiconductor chip2whose back surface is partially exposed through the opening17.

The opening17may have any shape such as a square, rectangular, or round shape as long as the area of the opening17is smaller than that of the back surface of the semiconductor chip2, and the opening17does not extends beyond edges of the semiconductor chip2. From the point of view of improving the heat dissipation, the opening preferably has a largest possible aperture with a center positioned in a portion at which the amount of heat generation from the chip is large.

The opening17can be formed by chemically or physically polishing a surface of the sealing portion16to expose the back surface of the semiconductor chip2. The chemical or physical polishing can be any method such as polishing by using micro particles or a grinder (grindstone), etching, laser processing, or the like.

With this configuration, heat generated from the semiconductor chip2is dissipated to a mounting substrate, or the like outside the semiconductor device400via the heat conducting path formed by the sealing portion16, second vias5, and external terminals6b. The back surface of the semiconductor chip2is exposed from the sealing portion16, so that a heat transfer path through which heat generated from the semiconductor chip2is directly dissipated to the air outside the semiconductor device400is formed. This heat transfer path can further improve the heat dissipation together with the heat transfer path formed by the second vias5and the external terminals6b.

(Variation of Fourth Embodiment)

FIG. 10is a cross-sectional view schematically illustrating a configuration of a semiconductor device of a variation.

In the fourth embodiment, the back surface of the semiconductor chip2of the semiconductor device400is partially exposed through the opening17formed in the sealing portion3. As illustrated inFIG. 10, a semiconductor device410of the present variation includes a heat dissipating body18provided to cover the opening17in the sealing portion16foil led at the back surface of the semiconductor chip2.

The heat dissipating body18is provided to be in contact with the back surface of the semiconductor chip2and the surface of the sealing portion16. The heat dissipating body18is larger than the back surface of the semiconductor chip2and is connected to the second vias5and the external terminals6b.

The heat dissipating body18may be a metal film or a sheet having conductivity. In order to improve the heat dissipation, the heat dissipating body18may be a substance having high thermal conductivity.

With this configuration, heat generated from the semiconductor chip2is dissipated to the outside of the semiconductor device410, for example, to a mounting substrate, or the like through the heat conducting path formed by the sealing portion16, the second vias5, and the external terminals6b. Further, the heat dissipating body18is provided on the back surface of the semiconductor chip2which is exposed through the opening17in the sealing portion16and on the surface of the sealing portion16, so that a heat conducting path for dissipating heat via the heat dissipating body18to the second vias5and the external terminals6bis formed. Thus, a plurality of heat conducting paths through which heat released from a side surface and the back surface of the semiconductor chip2can be efficiently dissipated are formed. Thus, the heat dissipation of the semiconductor device410can be further improved.

Fifth Embodiment

FIG. 11is a cross-sectional view schematically illustrating a configuration of a semiconductor device according to a fifth embodiment.

In the first variation of the first embodiment, the heat dissipating body8is provided on the surface of the sealing portion3of the semiconductor device110. As illustrated inFIG. 11, a semiconductor device500of the present embodiment includes a heat dissipating body19formed in a sealing portion3.

The heat dissipating body19is provided to be in contact with a back surface of a semiconductor chip2and has a greater width than the semiconductor chip2when viewed in cross section. The heat dissipating body19is connected to a plurality of second vias5. The heat dissipating body19is not in contact with a substrate1and is thus insulated from the substrate1. The heat dissipating body19is in contact with the back surface of the semiconductor chip2but is not electrically connected to circuits of the semiconductor chip2.

The heat dissipating body19may be a metal film or a sheet having conductivity. In order to improve the heat dissipation, the heat dissipating body19may be a substance having high thermal conductivity.

With this configuration, heat generated from the semiconductor chip2is dissipated through a heat conducting path formed by the sealing portion3, the second vias5, and external terminals6bto the outside of the semiconductor device500, for example, to a mounting substrate, or the like. This configuration further includes a heat conducting path from the heat dissipating body19which is in contact with the back surface of the semiconductor chip2to the second vias5connected to the heat dissipating body19and the external terminals6b. Thus, the heat dissipation of the semiconductor device500can be further improved. In particular, according to the present variation, heat released from the back surface of the semiconductor chip2can be directly transferred to the heat dissipating body19without being transferred through the sealing portion3. Thus, more efficient heat dissipation is possible compared to the configuration in which only the heat conducting path including the sealing portion3is formed.

Sixth Embodiment

FIGS. 12A and 12Bare respectively a cross-sectional view and a plan view schematically illustrating a configuration of a semiconductor device according to a sixth embodiment.

In the first to fifth embodiments and the variations thereof, one or more heat conducting paths for heat released from one semiconductor chip2mounted to the upper surface of the substrate1of the semiconductor device to the outside of the semiconductor device are formed. As illustrated inFIG. 12A, a semiconductor device600of the present embodiment includes heat conducting paths to the outside of the semiconductor device600. The heat conducting paths are each provided to a corresponding one of a plurality of semiconductor chips2a,2bmounted to an upper surface of a substrate1.

Depending on functions required for the semiconductor device600, electronic components20a,20bin addition to the semiconductor chips may be mounted. In the present embodiment, the electronic components20aare provided on the upper surface of the substrate1, and the electronic component20bis provided on a back surface of the substrate1(a surface opposite to the surface of the substrate1on which the semiconductor chips2a,2bare mounted).

On the upper surface of the substrate1, a wiring pattern is formed, and the wiring pattern includes an electrode (not shown) electrically connected to the semiconductor chips and first vias4. A pattern electrically connected to the electronic component20bis also formed on the back surface of the substrate1.

The semiconductor chips2a,2bare flip-chip mounted to the upper surface of the substrate1via bumps7. Principal surfaces of the semiconductor chips2a,2b, that is, surfaces on which the bumps7are bonded, include active regions in which integrated circuits including transistors and capacitors are formed.

A sealing portion3covers the semiconductor chips2a,2band is formed on the upper surface of the substrate1. The sealing portion3is, for example, an insulator such as a resin.

Through holes extending in a thickness direction of the sealing portion3from the electrode on the upper surface of the substrate1to an upper surface of the sealing portion3are formed in the sealing portion3. The through holes are filled with a conductive substance, thereby forming the first vias4. On a surface of the sealing portion3opposite to the substrate1, external terminals6aare arranged to be connected to the first vias4. That is, one end of each first via4is connected to the electrode on the upper surface of the substrate1, and the other end is connected to a corresponding one of the external terminals6aexposed from the sealing portion3. Through this electric pathway, the function of the semiconductor chips2a,2bis utilized from outside of the semiconductor device600.

Moreover, recessed portions are formed in the sealing portion3at positions located outwardly from each of the semiconductor chips2a,2b, in particular, near a side surface of each of the semiconductor chips2a,2b. The recessed portions extend in a thickness direction of the sealing portion3to such a depth that the recessed portions do not reach the wiring pattern of the substrate1. The recessed portions extending to such a depth that the recessed portions do not reach the wiring pattern of the substrate1are filled with a conductive substance, thereby forming second vias5. The second vias5are in contact with none of the semiconductor chips2a,2band the substrate1and are thus insulated from the semiconductor chips2a,2band the substrate1. On the surface of the sealing portion3, external terminals6bare arranged to be connected to the second vias5. A heat conducting path formed by the second vias5formed near the side surfaces of the semiconductor chips2a,2band the external terminals6bdissipates heat generated from the semiconductor chips2a,2bto the outside of the semiconductor device600.

A plurality of heat dissipating bodies21a,21bare further formed on the surface of the sealing portion3to cover back surfaces of the semiconductor chip2a,2b, respectively. The heat dissipating body21ahas a greater width than the semiconductor chip2awhen viewed in cross section, and the heat dissipating body21bhas a greater width than the semiconductor chip2bwhen viewed in cross section. The heat dissipating body21ais connected to the second vias5formed near the semiconductor chip2aand the external terminals6b. The heat dissipating body21ais in contact with neither the substrate1nor the semiconductor chip2aand is thus insulated from the substrate1and the semiconductor chip2a. The heat dissipating body21bis connected to the second vias5formed near the semiconductor chip2band the external terminals6b. The heat dissipating body21bis in contact with neither the substrate1nor the semiconductor chip2band is thus insulated from the substrate1and the semiconductor chip2b.

Heat conducting paths formed by the heat dissipating bodies21a,21brespectively formed on the back surfaces of the semiconductor chips2a,2band the second vias5and the external terminals6bconnected to the heat dissipating bodies21a,21bdissipate heat generated from the semiconductor chips2a,2bto the outside of the semiconductor device600.

The heat dissipating bodies21a,21bmay be metal films or sheets having conductivity. In order to improve the heat dissipation, the heat dissipating bodies21a,21bmay be substances having high thermal conductivity.

The electronic components20amounted to the upper surface of the substrate1are elements such as capacitors, resistors, inductors, or filters, and the electronic component20bmounted to the back surface of the substrate1is an antenna element.

On an upper surface of the semiconductor device600illustrated inFIG. 12B, the external terminals6a,6band the heat dissipating bodies21a,21bare arranged on the surface of the sealing portion3. The external terminals6bare arranged at positions located outwardly from each of the semiconductor chips2a,2b, preferably near each of the semiconductor chips2a,2bto surround each of the semiconductor chips2a,2b. The external terminals6aare arranged outside the external terminals6b. The external terminals6amay be arranged in an outer edge region of the semiconductor device600. Each of the external terminals6ais connected to a corresponding one of the first vias4in the sealing portion3.

The heat dissipating body21ais connected to the external terminals6bformed near the semiconductor chip2a, and the heat dissipating body21bis connected to the external terminal6bformed near the semiconductor chip2b. The heat dissipating body21ais larger than the back surface of the semiconductor chip2aand is connected to the second vias5and the external terminals6b. The heat dissipating body21bis larger than the back surface of the semiconductor chip2band is connected to the second vias5and the external terminals6b.

With this configuration, heat generated from the semiconductor chips2a,2bis transferred to the second vias5formed near the semiconductor chips2a,2bvia the sealing portion3and is dissipated to the outside of the semiconductor device600, for example, to a mounting substrate, or the like through the heat conducting path formed by the second vias5and the external terminals6b. Heat is transferred from the back surfaces of the semiconductor chips2a,2brespectively to the heat dissipating bodies21a,21bvia the sealing portion3and is dissipated through the heat conducting path formed by the second vias5and the external terminals6bconnected to the heat dissipating bodies21a,21b. Thus, even in the case of the semiconductor device600to which the semiconductor chips2a,2bare mounted, an efficient heat dissipating structure is provided to each of the semiconductor chips, so that efficient heat dissipation is possible.

The semiconductor device600is mounted to a mounting substrate (not shown) via the external terminals6a,6bto obtain an assembly. Heat generated from the semiconductor chips2a,2bof the assembly is transferred to the mounting substrate mainly via the heat dissipating bodies21a,21b, the second vias5, and the external terminals6band is dissipated to the outside of the semiconductor device600.

Here, rendering the second vias5, the external terminals6b, and the heat dissipating bodies21a,21belectrically continuous with a constant electric potential supply of the mounting substrate allows the structure including the second vias5, the external terminals6b, and the heat dissipating bodies21a,21bto serve as an electric shield as well as the heat conducting path. The second vias5are arranged to surround all of four sides of each of the semiconductor chips2a,2b, and the heat dissipating bodies21a,21bare arranged to cover the entire back surface of the semiconductor chips2a,2b, respectively. Thus, the shield effect can be further increased.

With this configuration, propagation of electric noise generated from the semiconductor chip2a(2b) to the electronic components20a,20badjacent to the semiconductor chip2a(2b) and to the other semiconductor chip2b(2a) can be reduced. Moreover, release of the electric noise generated from the semiconductor chip2a(2b) to the outside of the semiconductor device600can be reduced.

This configuration further reduces noise from the mounting substrate and the outside of the semiconductor device600or from the electronic components20a,20badjacent to the semiconductor chip2a(2b) and the other semiconductor chip2b(2a), so that the semiconductor device600can be stably operated.

The second vias5are not in contact with the substrate1. Thus, the positions and the number of the second vias5to be arranged can be optimally determined according to the size of the semiconductor chip and the amount of heat generation from the semiconductor chip. Therefore, even when a plurality of semiconductor chips are mounted, a heat dissipation effect corresponding to the amount of heat generation from each of the semiconductor chips can be obtained, so that the heat dissipation can be improved.

TheFIGS. 13A and 13Bare respectively a cross-sectional view and a plan view illustrating a configuration of a semiconductor device according to a variation.

In the sixth embodiment, in the semiconductor device600, the heat conducting paths are independently provided to each of the semiconductor chips2a,2bmounted to the upper surface of the substrate1. Specifically, the second vias5arranged near the semiconductor chip2a, the heat dissipating body21a, and the external terminals6bconnected to the second vias5and the heat dissipating body21aform the heat conducting path and serve as the electric shield for the semiconductor chip2a. The second vias5arranged near the semiconductor chip2b, the heat dissipating body21b, and the external terminals6bconnected to the second vias5and the heat dissipating body21bform the heat conducting path and serves as the electric shield for the semiconductor chip2b.

As illustrated inFIG. 13A, a semiconductor device610of the present variation includes heat dissipating bodies22provided on the surface of the sealing portion3and connected to each other, and the heat dissipating bodies22are arranged to face the back surfaces of the semiconductor chips2a,2band the electronic components20a.

On an upper surface of the semiconductor device610illustrated inFIG. 13B, the external terminals6a,6band the heat dissipating bodies22are arranged on the surface of the sealing portion3. The external terminals6bare arranged at positions located outwardly from the semiconductor chips2a,2band the electronic components20a, preferably near the semiconductor chips2a,2band the electronic components20ato surround each of the semiconductor chips2a,2band the electronic components20a. The heat dissipating body22is obtained by connecting the heat dissipating bodies each provided to a corresponding one of the semiconductor chips2a,2band the electronic components20a. The heat dissipating bodies22are each larger than a corresponding one of the semiconductor chips2a,2band the electronic components20aand are arranged to cover the back surfaces of the semiconductor chips2a,2band the electronic components20a.

Here, the second vias5and the external terminals6bare shared between the semiconductor chips2a,2badjacent to each other or between each of the semiconductor chips2a,2band corresponding one of the electronic components20a. More specifically, the second vias5and the external terminals6barranged near a side of the semiconductor chip2afacing the semiconductor chip2bserve also as the second vias5and the external terminals6barranged near a side of the semiconductor chip2bfacing the semiconductor chip2a. Moreover, the heat dissipating body22corresponding to the semiconductor chip2aand the heat dissipating body22corresponding to the semiconductor chip2bare connected to the shared second vias5and external terminals6bat a connecting portion between the heat dissipating bodies22.

With this configuration, even when it is not possible to sufficiently ensure a space in which the second vias5and the external terminals6bare arranged for each of the semiconductor chips2a,2band the electronic components20adue to the dimensional relationship among a substrate1, the semiconductor chips2a,2b, and the electronic components20a, the second vias5and the external terminals6bcan be shared by arranging the second vias5and the external terminals6bin a single row between mounted components adjacent to each other.

Also in this case, the sealing portion3, the second vias5, the heat dissipating bodies22, and the external terminals6bform heat conducting paths for heat generated from the semiconductor chips2a,2band the electronic components20a. Thus, the heat can be effectively dissipated to the outside of the semiconductor device610.

Rendering the second vias5, the external terminals6b, and the heat dissipating bodies22electrically continuous with a constant electric potential supply of the mounting substrate allows the second vias5, the external terminals6b, and the heat dissipating bodies22to serve as electric shields as well as the heat conducting paths. The second vias5are arranged to completely surround each of the semiconductor chips2a,2band the electronic components20a, and the heat dissipating bodies22are provided to cover the upper surfaces of the semiconductor chips2a,2band the electronic components20a, so that the shield effect can be further increased.

With this configuration, release of electric noise generated from the semiconductor chips2a,2band the electronic components20ato the outside of the semiconductor device610can be reduced. Additionally, noise from the mounting substrate and the outside of the semiconductor device610can be reduced, so that the semiconductor chips2a,2band the electronic components20a,20bcan be stably operated.

Seventh Embodiment

FIG. 14is a cross-sectional view schematically illustrating a configuration of a semiconductor device700according to a seventh embodiment.

The first to sixth embodiments and the variations thereof each include a heat dissipating structure which is a heat conducting path including the second vias5and the external terminals6bconnected to the second vias5. As illustrated inFIG. 14, in the semiconductor device700of the present embodiment, a heat dissipating body23but not external terminals is connected to second vias5. The heat dissipating body23is connected to first vias4and external terminals6dvia a re-distribution interconnect24formed on a surface of a sealing portion3.

Through holes extending in a thickness direction of the sealing portion3from an electrode on an upper surface of a substrate1to an upper surface of the sealing portion3are formed in the sealing portion3. The through holes are filled with a conductive substance, thereby forming the first vias4. That is, one end of each first via4is connected to the electrode on the upper surface of the substrate1, and the other end is connected to a corresponding one of the external terminals6dexposed from the sealing portion3. Through this electric pathway, the function of the semiconductor chip2is utilized from outside of the semiconductor device700.

Recessed portions are formed at positions located outwardly from the semiconductor chip2, in particular, near a side surface of the semiconductor chip2in the sealing portion3in the thickness direction of the sealing portion3to have such a depth that the recessed portions do not reach a wiring pattern of the substrate1. The recessed portions having such a depth that the recessed portions do not reach the wiring pattern of the substrate1are filled with a conductive substance, thereby forming the second vias5.

The second vias5are in contact with neither the substrate1nor the semiconductor chip2and are thus insulated from the substrate1and the semiconductor chip2.

The heat dissipating body23is formed on the surface of the sealing portion3to cover the semiconductor chip2. The heat dissipating body23has a larger width than the semiconductor chip2when viewed in cross section and is connected to the second vias5. The heat dissipating body23may be a metal film or a sheet having conductivity. In order to improve the heat dissipation, the heat dissipating body23may be a substance having high thermal conductivity.

On the surface of the sealing portion3, the re-distribution interconnect24is formed outside the second vias5. The first vias4and the second vias5are connected to and are electrically continuous with each other by the re-distribution interconnect24. The re-distribution interconnect24is an interconnect. The re-distribution interconnect24may be a metal film or an interconnect made of copper or aluminum.

With this configuration, the heat dissipation can be further improved by a heat conducting path in which heat generated from the semiconductor chip2propagates via the sealing portion3to the second vias5arranged near the semiconductor chip2and the heat dissipating body23and a heat conducting path in which the heat propagates via the re-distribution interconnect24to the first vias4and the external terminals6a.

As described above, even when no external terminals6bis connected to the second vias5, the heat dissipation can be improved by forming a heat conducting path by connecting the second vias5to the first vias4.

Common configurations in the embodiments and the variation thereof will be additionally described in this paragraph. In the first to seventh embodiments, and the like, the mounting substrate may be a resin substrate or a ceramic substrate or may be a both-sided substrate or a multilayer substrate. Components or elements in addition to the semiconductor device may be mounted to the mounting substrate. In the first and third variations of the first embodiment, the variations of the second to fourth embodiments, the sixth embodiment and the variations of the sixth embodiment, it is not essential to connect the heat dissipating body to both of the second vias and the external terminals connected to the second vias. Even when the heat dissipating body is connected, for example, only to the second vias, a certain degree of effect can be obtained as long as the heat dissipating body is part of the heat conducting path to the external terminal. In the first and third variations of the first embodiment, the variations of the second to fourth embodiments, the sixth embodiment and the variations of the sixth embodiment, and the seventh embodiment, the heat dissipating body may be arranged on the surface of the sealing portion or may be partially embedded in the sealing portion.

The conductive substance, which is filled in the through holes to form the first vias may be the same as the conductive substance, which is filled in the recessed portions having such a depth that the recessed portions do not reach the back surface of the chip and forms the second vias and the third vias. In this case, the fabrication process is simplified. On the other hand, an optimal material for each of the substances may be selected. For example, the first vias may be filled with a conductive substance, whereas the second and third vias may be filled with an insulative material having high thermal conductivity. For example, any of alumina (aluminum oxide), aluminum nitride, and silicon carbide, or a mixture thereof can be used as the insulative material to be filled in the second and third vias. These insulative materials having high thermal conductivity may be used as a filler. Specifically, an insulative material having high thermal conductivity is powdered and mixed with a resin to obtain a mixture, and the mixture may be filled in each recessed portion. Carbon or diamond having very high thermal conductivity can be used as the filler. In this case, the second vias and the third vias filled with the filler at a high density have higher thermal conductivity than the sealing portion made of the insulative material.

In the above description, the present disclosure has been described in detail based on the embodiments and the variations thereof, wherein elements denoted by the same reference numerals have features similar to those of the preceding embodiments or variations, unless otherwise indicated. Elements denoted by the same reference numerals and structures obtained by associating the elements ensure the effect obtained in the preceding embodiments or variations, unless otherwise indicated. Moreover, the effect of the first embodiment is also ensured in the other embodiments and variations, unless otherwise indicated.

The present disclosure is not limited to the embodiments, and the like. Changes and modifications can be made as long as doing so does not depart from the spirit of the present disclosure. For example, a configuration obtained by combining the configurations of embodiments, and the like different from each other and a configuration obtained by substituting a part of an element with a similar part which is not described in the embodiments, or the like are also in the scope of the present disclosure.

The semiconductor device of the present disclosure has high heat dissipation and high noise resistance and is excellent in high frequency operation. Thus, the semiconductor device of the present disclosure is useful as RF modules, semiconductor packages, or the like of communication devices.