Digitally controlled voltage generator

A digitally controlled voltage generator is disclosed for use in applications requiring fine resolution voltage control, such as generating a common voltage for a liquid crystal display. A constant resistance digital to analog converter (DAC) is configured to provide appropriate voltage steps by tuning bias resistors to generate desirable reference voltages for the DAC. The bias resistors are configured to be tuned after placement and routing steps in an integrated circuit design.

BACKGROUND OF THE INVENTION

1. Field of the Invention

Embodiments of the present invention relate generally to voltage generator circuits and, more specifically, to a common voltage generator circuit for liquid crystal displays.

2. Description of the Related Art

A modern liquid crystal display (LCD) screen is formed as an array of pixels that are backlit using a uniform polarized light source (backlight). Each pixel comprises at least one region of liquid crystal material sandwiched between two electrodes. A color LCD screen may use three regions of liquid crystal material to form one color pixel comprising red, green, and blue color components. The electrodes are fabricated from an electrically conductive material that is thin enough to be relatively transparent to light, allowing light to pass through both electrodes and each region of sandwiched liquid crystal material. One of the two electrodes is connected to a common voltage (VCOM), and the second electrode is connected to a column wire via a field effect transistor that is configured to connect the column wire to the second electrode in response to a row select signal on a corresponding row wire. The column wire is driven with a voltage value corresponding to a desired intensity for the associated liquid crystal region. A color LCD panel may need three column wires, corresponding to red, green, and blue color components, to determine a color value for one pixel. When a given row is selected, a voltage potential is established between the two electrodes, causing liquid crystal material in a corresponding region to modulate the polarization of light transmitted through the region. The transmitted light originates as polarized light from the backlight, passes through the liquid crystal material, and passes through a polarizing filter before exiting a viewing surface of an LCD panel. By modulating the polarization of the light transmitted through the liquid crystal region, the pixel brightness is correspondingly modulated when viewed from the viewing surface of the LCD panel.

Persons skilled in the art understand that the optimal VCOM voltage for a given LCD panel may vary on a panel-to-panel basis, based on manufacturing variation for the LCD panel. In other words, VCOM for each panel should be individually adjusted, preferably as part of a manufacturing process. One challenge in adjusting VCOM to an optimal value is that relatively small differences in VCOM can cause visible degradation in image quality of a particular LCD panel. For example, a difference of one millivolt can oftentimes have a perceptible effect on image quality. One common type of visible degradation appears as flicker in images displayed by the LCD panel. An analog variable resistor is sometimes used to adjust VCOM with millivolt resolution. However, the analog variable resistor introduces additional manufacturing costs and is therefore not a preferred solution in high-volume LCD manufacturing. A more efficient solution involves digitally adjusting VCOM, as described below inFIG. 1.

FIG. 1illustrates a prior art digitally controlled common voltage generator circuit100. The common voltage (VCOM) generator circuit100includes a voltage generator130, and an output driver132, which generates VCOM190. VCOM190corresponds to a common voltage (VCOM) reference conventionally used in LCD panels. The voltage generator130receives an analog voltage on node VDDA104, and a digital voltage on node VDDB106. Each voltage is measured with respect to a ground (GND) node102. The GND node102is defined as having a potential of zero volts. A reference voltage associated with VREFA112, also measured with respect to GND102, is generated from a resistor divider formed by resistors R124and R122. VREFA112is generated according to a target specification for an associated LCD panel. Amplifier120is configured to form a voltage follower with a high-impedance input, which is connected to VREFA112, and a low impedance output, which is connected to VREFB114. The voltage follower drives VREFB114with a low impedance at a voltage corresponding closely to VREFA112, thereby isolating VREFA112from variable sink currents drawn through an “R-2R” digital to analog converter (DAC)140. Persons skilled in the art will understand that an R-2R DAC140presents a variable current load to node VREFB114, and that the variable current load is a function of a digital DAC value156. The DAC value156conventionally represents a fixed-length integer. Each integer represented by the DAC value156has a corresponding voltage value generated at VDAC150. Each increment in the DAC value156has a corresponding voltage step at VDAC150.

The DAC value156comprises a parallel vector transmitted from a serial digital controller144to a DAC decoder142. The serial digital controller144receives a serial clock signal SCL152and a serial data signal SDA154. A digital data vector is transmitted from an external device (not shown) via SCL152and SDA154for representation within the voltage generator130as DAC value156. In one embodiment, the serial data controller144adheres to conventional “I2C” signaling.

In response to a given DAC value156, the DAC decoder142generates control signals to activate one or more analog pass gates within the R-2R DAC140in order to produce a corresponding output voltage at VDAC150. VDAC150is transmitted to the output driver132, where amplifier160, Q162, and R164are configured to convert VDAC150to a current, which is sourced from node188and sinked through R164to GND102. Resistor R184forms the top of a voltage divider, while R182, Q162and R164form the bottom of the voltage divider, which is configured to generate a voltage on node188that is between VDDA104and GND102. Amplifier180is configured as a voltage driver (follower), which drives VCOM190with a voltage corresponding closely to the voltage on node188. Amplifier180should be configured to drive enough current to maintain a relatively stable voltage value on node VCOM190.

One problem with prior art designs for the common voltage generator circuit100is that amplifier120is costly in terms of die area and power consumption. Additionally, amplifier120introduces an offset voltage between VREFA112and VREFB114, that may commonly correspond to dozens of voltage steps at VDAC150, thereby degrading accuracy and control in the prior art common voltage generator circuit100. Additional die area or additional power consumption, or both, may be utilized as part of a design trade-off to attempt to reduce the offset voltage associated with amplifier120. However, such trade-offs further reduce the efficiency of the overall common voltage generator circuit100.

As the foregoing illustrates, what is needed in the art is a technique for precisely generating a digitally controlled voltage that is more efficient than in existing art.

SUMMARY OF THE INVENTION

One or more embodiments of the invention provide a digitally controlled voltage generator for use in applications requiring fine resolution voltage control, such as generating a common voltage for a liquid crystal display. A constant resistance digital to analog converter (DAC) is configured to provide appropriate voltage steps by tuning bias resistors to generate desirable reference voltages for the DAC. The bias resistors are configured to be tuned after placement and routing steps in an integrated circuit design.

A voltage generator according to an embodiment of the invention includes a constant resistance digital-to-analog converter for generating an output voltage, wherein the constant resistance digital-to-analog converter includes a resistor network and is connected to a reference voltage through a first resistor and to ground through a second resistor. The resistor network may be a linear string of serially connected resistors or a plurality of resistor segments, each having a string of serially connected resistors.

A voltage generator according to another embodiment of the invention includes a constant resistance digital-to-analog converter for generating an output voltage, a resistor divider including a first resistor and a second resistor connected in series between a digital reference voltage and ground, a third resistor connected at a first end to a node between the first resistor and the second resistor and at a second end to the constant resistance digital-to-analog converter, and a fourth resistor connected in series between the constant resistance digital-to-analog converter and ground. According to a further embodiment, the constant resistance digital-to-analog converter includes a plurality of gates that are controlled to generate the output voltage at a desired level.

An LCD display device according to an embodiment of the invention includes a plurality of LCD elements to which is supplied a common voltage reference, and a common voltage reference generator including a constant resistance digital-to-analog converter having a resistor network for generating an output voltage from which the common voltage reference is generated. According to a further embodiment, the common voltage reference generator further includes an output driver for receiving the output voltage from the constant resistance digital-to-analog converter and generating the common voltage reference.

A method of tuning a voltage generator for a digital-to-analog converter that includes a constant resistance digital-to-analog converter, according to an embodiment of the invention includes the steps of adjusting a resistor value of the first resistor, and adjusting a resistor value of the second resistor, wherein the resistor values are adjusted based on parasitic resistance values determined prior to the steps of adjusting.

DETAILED DESCRIPTION

FIG. 2illustrates an improved digitally controlled common voltage generator circuit200, according to one embodiment of the present invention. The common voltage generator circuit200of the present invention includes a voltage generator230, and an output driver232, which generates a digitally controlled common voltage on VCOM290. VCOM290corresponds to a common voltage (VCOM) reference conventionally used in LCD panels. The voltage generator230receives an analog voltage on node VDDA204, and a digital voltage on node VDDB206. Each voltage is measured with respect to a ground (GND) node202. The GND node202is defined as having a potential of zero volts. A reference voltage on node VTOP212, measured with respect to GND202, is a function of voltage VDDA204, R1, R2, R3, a constant resistance (RDAC) associated with constant R DAC240, and R4.

The DAC value256conventionally represents a fixed-length integer. Each integer represented by the DAC value256has a corresponding voltage value generated at VDAC250. Each increment in the DAC value256has a corresponding voltage step at VDAC250. The DAC value256comprises a parallel vector transmitted from a serial digital controller244to a DAC decoder242. The serial digital controller244receives a serial clock signal SCL252and a serial data signal SDA254. A digital data vector is transmitted from an external device (not shown) via SCL252and SDA254for representation within the voltage generator230as DAC value256. In one embodiment, the serial data controller244adheres to conventional “I2C” signaling.

In response to a given DAC value256, the DAC decoder242generates control signals to activate one or more analog pass gates within the constant R DAC240in order to produce a corresponding output voltage at VDAC250. VDAC250is transmitted to the output driver232, where amplifier260, Q262, and R7are configured to convert VDAC250to a current, which is sourced from node288and sinked through R7to GND102. Resistor R5forms the top of a voltage divider, while R7, Q262and R6form the bottom of the voltage divider, which is configured to generate a voltage on node288that is between VDDA204and GND202. Amplifier280is configured as a voltage driver (follower), which drives VCOM290with a voltage corresponding closely to the voltage on node288. Amplifier280should be configured to drive enough current to maintain a relatively stable voltage value on node VCOM290.

A design methodology for selecting values of R1, R2, R3, R4is described below. RDAC is taken as a given here, although persons skilled in the art will recognize that design trade-off also exist when designing constant R DAC240, and those trade-offs lead to a final value of RDAC. In general, RDAC should be a relatively large resistance value (KΩ's through MΩ's) for low power operation.

Equation 1 is used to compute values for R3and R4. RBIAS is computed and assigned to R3(as a nominal value for R3) for the upper voltage range of VDAC250, and RBIAS is computed again and assigned to R4(as a nominal value for R4) for the lower voltage range of VDAC250. RBIAS is computed based on RDAC, N (number of bits in DAC value256), and α, an offset value measured in integral (LSB) steps of DAC value256. When R3is computed, α represents a number of steps below VREF212a maximum VDAC250voltage should be. When R4is computed, α represents a number of steps above 0 a minimum VDAC250value should be.

Equation 2 is used to compute RDAC for the special case of a constant R DAC240comprising a linear resistor string. Persons skilled in the art will recognize that other techniques, including segmented resistor string DAC architectures, may also be used to build the constant R DAC240. Computing RDAC for DAC structures other than a series resistor string should be computed according to the particular topology of the given DAC structure. For example, a segmented resistor string DAC is characterized by a sum of resistance values associated with a primary rank of resistors.
RDAC=ΣRS(Equation 2)

An equivalent resistance of the resistive path from VTOP212through the constant R DAC240to ground is given in Equation 3.
REQUIV=R3+R4+ΣRS(Equation 3)

Equation 4 should be used to compute a resistance value for R1. Equation 4 uses REQUIV computed in Equation 3, analog voltage VDDA204, a target value for VREF (VTOP212), and value for R2. In one embodiment R2is set to REQUIV. The target value for VREF dictates the upper voltage limit for VDAC250, independent of offsets implemented using bias resistors R3and R4.

Using Equations 1 through 4, values for R1, R2, R3, and R4may be computed and used as nominal design values in a physical design (integrated circuit mask layout) implementation of the common voltage generator circuit200. The physical design implementation may be generated and advantageously used in multiple different integrated circuit designs, each potentially with different routing constraints. As such, parasitic resistance between GND202and true ground for the integrated circuit hosting the common voltage generator circuit200may cause VDAC250to be offset with respect to a desired design target. Similarly, parasitic resistance between VDDA204and the true analog supply voltage for the integrated circuit may cause VDAC250to be offset with respect to a desired design target.

In a typical physical design setting, the common voltage generator circuit200may be subject to different parasitic resistance values between VDDA204, GND202, and their respective reference nodes on different designs. Furthermore, the parasitic resistance values are not conventionally known until after circuitry outside the common voltage generator circuit200is placed and routed within the integrated circuit.

To compensate for parasitic resistance values outside of the common voltage generator circuit200, bias resistors R3and R4may be adjusted in a step performed after conventional place and route has been performed and relevant parasitic resistance values may be determined. Each of the bias resistors R3and R4is configured to be independently tunable using a small number of layer modifications. For example, R3and R4may be configured to be tunable by placing a via cut (one layer modification) in one or more pre-defined locations. Alternatively, R3and R4may be independently configured by placing a poly-silicon contact (one layer modification) in a specified location. Alternatively, R3and R4may be independently configured by placing a poly-silicon bridge (one layer modification) in a specified location between two strips of poly-silicon. Persons skilled in the art will recognize that various other techniques for tuning R3and R4may be implemented without departing the scope of the present invention. Furthermore, persons skilled in the art will recognize that bias resistors R3and R4should be designed to accommodate a range of values to compensate for a range of parasitic resistance values coupled to VDDA204and GND202.

FIG. 3Aillustrates an exemplary constant resistance (R) digital to analog converter (DAC)240employing a linear architecture, according to one embodiment of the present invention. The constant R DAC240comprises a series string of resistors RS352, each connected to a corresponding pass gate354. Each pass gate354is also coupled to VDAC250, which serves as the output node of the constant R DAC240. Each pass gate354is controlled by a corresponding control signal350, which is generated by a DAC decoder244.

In one embodiment, the DAC decoder244activates one control signal350at a time to turn on one pass gate354at a time. The DAC decoder244activates one control signal350in response to receiving a corresponding DAC value256. For example, a DAC value256of “1” may be decoded by the DAC decoder244to activate control signal350(1), which closes pass gate354(1) to couple node356to VDAC250, thereby transmitting the voltage on node356to VDAC250. Each sequential node along the series string of resistors RS352establishes a discrete voltage that is linearly distributed between VBOT (the voltage on node VBOT214) and VTOP (the voltage on node VTOP212). A substantially identical voltage step is established along sequential nodes. By activating a given pass gate354, a corresponding discrete voltage is transmitted to VDAC250. In one embodiment, N is an integral power of two, such as 2^6 (64), 2^7 (128), 2^8 (256), and so forth. When N is and integral power of two, VDAC250ranges from VBOT to VTOP*(2^N−1)/(2^N).

The values of R1, R2, R3, and R4are selected as described previously inFIG. 2. Persons skilled in the art will recognize that any constant R DAC, regardless of architecture, may be employed as constant R DAC240without departing the scope of the present invention.

FIG. 3Billustrates an exemplary constant resistance (R) digital to analog converter (DAC)240employing a segmented architecture, according to one embodiment of the present invention. The constant R DAC240comprises a plurality of resistor string segments coupled to pass gates that are used to couple one resistor in each one of the resistor string segments to either another resistor string segment or to an output node. For example, resistors RS362comprise a first resistor string segment, and resistors RS372comprise a second resistor string segment. Pass gates364connect resistors362the second resistor string segment via intermediate nodes368. Resistors372are connected to intermediate nodes368and output node VDAC250. Each pass gate364,374is controlled by a corresponding control signal360,370, generated by a DAC decoder244and transmitted to the constant R DAC240as control signals350.

In one embodiment, the DAC decoder244activates two control signals360at a time to turn on two pass gates364at a time, coupling one resistor RS362in parallel with intermediate nodes368. The DAC decoder244activates one control signal370at a time to couple a selected voltage from a final resistor string segment to output node VDAC250. In this example, the second resistor string segment is the final resistor string segment. Each resistor string segment corresponds to bits of decreasing significance in the magnitude of DAC value256. The first resistor strong segment corresponds to the most significant bits of DAC value256, while the final resistor string segment corresponds to the least significant bits of DAC value256. Persons skilled in the art will readily understand that an arbitrary number of resistor string segments may be coupled together in this way to form a constant R DAC of arbitrary resolution, where each resistor string segment has one resistor coupled in parallel with a successively lower significance segment, with the exception of the final resistor string segment, which is coupled to the output node VDAC250.

The control signals350are generated in response to receiving a corresponding DAC value256. For each resistor string segment, a set of control bits, corresponding to bits within the DAC value256, is generated within control signals350. For example, control signals350comprise most significant bit control signals360generated from two most significant bits of DAC value256. Control signals350further comprise least significant bit control signals370, generated from two least significant bits of DAV value256. For example, a DAC value256of “0001” (one linear voltage increment going from VBOT214towards VTOP212) should be decoded by the DAC decoder244to activate control signals360(0),360(1), and370(2), which closes pass gate364(0),364(1),374(2) to couple node376to VDAC250, thereby transmitting the voltage on node376to VDAC250. The voltage on node376appropriately corresponds to one linear voltage increment, going from VBOT214towards VTOP212.

The values of R1, R2, R3, and R4are selected as described previously inFIG. 2. Persons skilled in the art will recognize that any constant R DAC, regardless of architecture, may be employed as constant R DAC240without departing the scope of the present invention.

FIG. 4Adepicts a liquid crystal display (LCD) subsystem400, configured to implement one or more aspects of the present invention. The LCD subsystem400includes the common voltage generator circuit200ofFIG. 2, an LCD panel430, a column driver420and a row driver410. The LCD panel430includes an LCD element440(0,0), which includes a transistor, Q434, and an LCD cell432. The LCD cell432includes a liquid crystal region sandwiched between two electrodes. A first electrode of the two electrodes is connected to VCOM290. A second electrode of the two electrodes is connected to Q434, which is coupled to column drive signal424. When Q434is turned on, the column drive signal424is coupled to the second of the two electrodes. A voltage potential between the two electrodes modulates polarization rotation within the LCD cell432, which, in turn, controls how much light is transmitted through the LCD cell432.

The row driver410receives a row input signal412, and generates a row drive signal414. The row input signal412should be a digital signal having two defined states, corresponding to an active state and an inactive state. In the active state, the row driver410drives a row drive signal414that turns on Q434, coupling the column drive signal424to the LCD cell432. The column driver420receives an analog column input signal422and drives the column input signal422as a voltage on column drive signal424. In one embodiment, the column input signal422is an analog voltage signal that represents an amount of light to be transmitted by LCD element440(0,0) when the row drive signal414is in the active state. The amount of light is determined by the voltage potential between the column drive signal424and VCOM290. In one embodiment, a software control signal405is used to drive signals SCL252and SDA254, ofFIG. 2, to configure an output voltage value for VCOM290.

FIG. 4Billustrates an LCD display device490, configured to implement one or more aspects of the present invention. The LCD display device490includes the common voltage generator circuit200ofFIG. 2, the LCD panel430, row drivers450, column drivers452, a timing engine456, and a video data engine454. The video data engine454receives video information via input video data460. The video information includes rows of intensity data that form sequential video frames of two-dimensional intensity data. The video information also includes timing information delineating lines of intensity data within delineated sequential video frames. The intensity data is transmitted to the video data engine454and the timing information is transmitted to the timing engine456. Timing information may also be transmitted to the video data engine454.

The timing engine456extracts line and frame timing information to generate control signals for activating individual drivers within row drivers450. For example, at the start of a new frame, and after a first row of intensity data is received by the video data engine454, row driver410may be activated. After a second row of intensity data is received by the video data engine454, row driver411may be activated, and so forth. Column drivers452receive analog input signals from the video data engine454to drive analog voltages on column wires within the LCD panel430. When one row is activated, the column wires configure a row of LCD elements440to transmit an a corresponding set of intensity values. Each one of the LCD elements440should be a substantially identical instance of LCD element440(0,0), described inFIG. 4A.

As an example of the operation of the LCD display device290, when row driver410is active, column driver420drives LCD cell432within LCD element440(0,0) via column wire424with a voltage corresponding to a desired intensity for the LCD element440(0,0). The voltage, in conjunction VCOM290, determines an intensity value the LCD element440(0,0). In a color LCD panel430, three LCD elements440(red, green, blue) are used to form one color pixel. In one embodiment, a software (SW) control signal405is used to drive signals SCL252and SDA254, ofFIG. 2, to configure an output voltage value for VCOM290. The SW control signal405may be used during manufacturing to establish a value for VCOM290. The value for VCOM290may be stored in non-volatile memory (not shown) within the LCD display device290.

In sum, a technique for generating a digitally controlled voltage is disclosed. The digitally controlled voltage is suitable for use as a common voltage in LCD display panels. The technique is based on a circuit architecture comprising four resistors and a constant R DAC, such as a resistor string DAC. The four resistors are used to provide appropriate reference voltages to the constant R DAC. At least two of the four resistors are configured to be tunable in a layout modification step performed after conventional place and route physical design of a related integrated circuit.

One advantage of the disclosed invention is that the circuit architecture is simplified with respect to conventional common voltage generators through the elimination of an operational amplifier. Furthermore, lower power and greater accuracy may also be achieved by eliminating the operational amplifier, which introduces an offset voltage. This offset voltage represents an error in the digitally controlled voltage output. Another advantage of the disclosed invention is that the bias resistors may be configured to compensate for post-layout routing resistance that deviates from nominal routing resistance values. Yet another advantage of the disclosed invention is that dynamic power consumption within the constant R DAC may be reduced on average versus a conventional “R2R” resistor DAC because current flow through the constant R DAC remains essentially constant.

In view of the foregoing, the scope of the present invention is determined by the claims that follow.