Read-data stage circuitry for DDR-SDRAM memory controller

A circuit for sampling data from a memory device comprises a circuit for providing a clock signal to the memory device, a data bus carrying data at twice the rate of the clock signal, a circuit for providing a control signal to indicate the period of time where data are valid, and a set of registers whose content is triggered by both edges of a signal resulting from the delay of the control signal. The set of registers is divided into several sub-parts, each sub-part loading the value of the data bus carrying data provided by the memory device at a period being an integer multiple of the clock signal where the sampling point is different for each sub-part.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to DDR memory devices. More particularly, the present invention relates to read data stage circuitry architecture for Mobile DDR memory device controllers.

2. The Prior Art

DDR-SDRAM devices can transfer data twice as fast as regular SDRAM chips (SDR-SDRAM). This is because DDR-SDRAM devices can send and receive signals twice per clock cycle. Mobile DDR-SRAM devices are a kind of DDR memory device designed for low-power consumption. Their intrinsic timings for read accesses slightly differs from that of standard DDR memory devices.

FIG. 1is a block diagram that shows a typical microcontroller system architecture10employing a microprocessor12connected to a DDR-SDRAM device14. Conventional Crystal oscillators can generate frequencies up to 30 MHz. To obtain clock frequencies of 100 Mhz and higher for use by the microprocessor12and the system bus, there is a need to employ phase-locked loop (PLL) circuitry. The system clock may be generated from the main oscillator and PLL16that can be found in a microprocessor circuit. The main oscillator and PLL circuitry16is used to multiply the frequency produced by the crystal oscillator. If the microprocessor circuit12drives a DDR memory device14, a DDR-SDRAM memory controller18must be used and this module requires DQS-delay circuitry20to delay DQS signals22and24from DDR-SDRAM memory for read operations.

If the system bus (26,28, and30) and microprocessor12(also known as CPU) are clocked at 100 MHz, then any write access to DDR memory controller18will require the PLL16to be configured at 200 MHz for the DDR-SDRAM controller18to align the data with the waveforms shown inFIG. 3. This may be performed by logic within the DDR-SDRAM controller18that is clocked at 2× frequency of the main clock frequency of the DDR-SDRAM controller18.

In order to drive the microprocessor12and system bus (26,28, and30) and main logic of the DDR-SDRAM controller module at 100 MHz, a divide-by-2 circuit32is used to derive the 100 MHz system clock34from the 200 MHz PLL output. This clock is gated and supplied to the DDR-SDRAM memory device14on clock line36.

The DDR-SDRAM controller18drives the DDR-SDRAM memory device14through buffers38. The propagation delay for each buffer is assumed to be the same for simplicity purposes. In real-life the delay for each buffer may be slightly different but without significant difference because buffers are high-drive buffers designed to drive DDR devices and share roughly the same capacitive load. The command signals40(RAS/CAS/WE/CKE) passed to the DDR-SDRAM device14must be aligned in such a way that a setup time and hold time is guaranteed with respect to the rising edge of the clock signal provided to the memory device on clock line36.

For each type of memory the read data bus42must be properly sampled and the data must be passed to the system bus (shown as rdata30inFIG. 1). For proper operation, the edge of the DQS signal is delayed so that sampling occurs in the middle of the data window. Read logic44drives read registers46to accomplish this task.

Referring now toFIG. 2, a block diagram illustrates the details of an arrangement of read registers46that may be used to properly sample the output data from the DDR-SDRAM device14. As is shown inFIG. 2several internal registers are required to pass data onto the system bus. The first set of registers48(DataReg1) captures data D0, the second set of registers50(DataReg2) captures data D1. When the rising edge of the system bus clock on line52occurs somewhere in the window period of captured data D1, the data capture register50holding D1is ready but the data capture register48holding D0may no longer be holding D0depending on the propagation delay (T1). If T1is very low, then this capture register48may have already switched to the D2value and therefore cannot provide the system bus with D0and D1. Therefore another capture register54(DataReg3) samples the data captured by register48for each falling edge of the delayed DQS signal, using inverter56to invert the delayed DQS signal on line58.

At the rising edge of the CPU clock the 32-bit data is formed by sampling both 16-bit data capture registers50and54. If the propagation delay in the I/O pad providing data and clock to the DDR-SDRAM device14varies from 0 to half the period of the DDR clock/CPU clock, the data sampled will be correct. The data sampling circuitry is safe and robust. When read accesses are performed, data from the DDR-SDRAM device14must be sampled but when no access is being performed it may be useful to prevent data switching by holding the data provided to the system bus to achieve lower power consumption. This is done by providing sample-and-hold functions which consist of DFFs60and62and multiplexers64and66. One input of each multiplexer recirculates the data output of the DFF to its D input. When a multi-bit signal has to be stored, this architecture is repeated for each bit of the multibit signal.

FIG. 3illustrates the best and worst case timings (shown as T1=min and T1=max, respectively) for read accesses for a standard DDR-SDRAM memory device at a frequency of 100 MHz for a given manufacturing process, operating voltage and temperature (PVT). Both values of T1are shorter than one-half the clock period of the DDR clock. The circuit ofFIG. 2accommodates the worst-case timing shown inFIG. 3.

FIG. 4illustrates the best and worst-case timings for read accesses for a mobile DDR-SDRAM device at a frequency of 100 MHz for a given PVT. Compared to the timing of the standard DDR-SDRAM shown inFIG. 3, the best and worst case timings (Tacc_min and Tacc_max) for the mobile DDR-SDRAM have a larger dispersion as may be seen inFIG. 4and are shown separately. It is seen that, at some higher frequencies, the value Tacc_max may be larger than one-half of the clock period of the DDR clock depending on the clock frequency used to clock the DDR memory device. When standard and mobile DDR-SDRAM devices may be used with a microcontroller, the user may not want to reduce the frequency of the system clock to accommodate the different memory device types. In order to obtain proper operation, the intrinsic timing differences must be accommodated at higher clock frequencies to avoid data-read errors.

Because mobile DDR-SDRAM memory devices have a large variation in propagation delay (access time), the difference in best case and worst case access time is greater than half the CPU clock period/clock sent to the DDR memory device for some range of frequencies. If it is desired to drive mobile DDR memory devices at the same CPU clock frequency used to drive standard DDR memory devices using the read data stage ofFIG. 2, unpredictable behavior of read data stage circuitry may result in which it will work properly with worst-case timing but will not operate properly with best-case timing. In between best-case and worst-case timing, it is not possible to predict the point at which the circuit46will switch from working to non-working.

FIG. 5is a set of timing diagrams that illustrate the operation of the circuit ofFIG. 2for a standard DDR-SDRAM memory device under best-case and worst-case timing conditions. As shown inFIG. 5, the sampling point occurs when the data in registers50(DataReg2), and54(DataReg3) is valid. The delay T1represents the buffer delay between the internal RAS/CAS/WE/Cke signals and those signals at the external pads as well as the buffer delay between the edge of the gated clock signal at line36ofFIG. 1and the external clock signal input CLK to the DDR memory inFIG. 1. Delay T2represents the delay between the edge of the DDR CLK signal to the DDR-SDRAM memory device ofFIG. 1and the delayed DQS signal from DQS delay circuit20ofFIG. 1. T3is the register50hold time. Under both the best-case and worst-case conditions, the D0and D1data is stable in the capture DFFs DataReg2and DataReg3and thus is correctly transferred to the system bus by the sampling DFFs.

FIG. 6is a set of timing diagrams that illustrate the operation of the circuit ofFIG. 2for a mobile DDR-SDRAM memory device under worst-case conditions.FIG. 6shows the relevant waveforms when the access time of the mobile DDR memory device is very high (7 ns), which is more than half the clock period of 5 ns. This is the worst-case access time and is essentially equivalent to the worst-case access time of a standard DDR memory device. The delay T1represents the buffer delay between the internal RAS/CAS/WE/Cke signals and those signals at the external pads as well as the buffer delay between the edge of the gated clock signal at line36ofFIG. 1and the external clock signal input CLK to the DDR memory inFIG. 1. Delay T2represents the delay between the edge of the external DDR CLK signal to the DDR-SDRAM memory device ofFIG. 1and the delayed DQS signal from DQS delay circuit20ofFIG. 1that occurs after the access time of the DDR-SDRAM memory device. T3is the captured data setup time compared to the rising edge of system bus clock.

It may be seen that the basic read stage circuitry46ofFIG. 2behaves correctly under the timing conditions ofFIG. 6. The delay T3is greater than the setup time for a DFF or other sequential element used to capture data that will be sampled onto the system bus. As shown inFIG. 6, at the end of delay T3, the D0and D1data respectively stored in DataReg3and DataReg2is stable in the capture DFFs and thus is correctly transferred to the system bus by the sampling DFFs.

There is range of operating conditions where the circuit behavior will be unpredictable. This is shown with reference toFIG. 7, a set of timing diagrams that illustrate the operation of the circuit ofFIG. 2for a mobile DDR-SDRAM memory device under best-case conditions.FIG. 7shows the relevant waveforms when the access time of the mobile DDR memory device is very low (2 ns), which is less than half the clock period (5 ns). Again, the delay T1represents the buffer delay between the internal RAS/CAS/WE/Cke signals and those signals at the external pads as well as the buffer delay between the edge of the gated clock signal at line36ofFIG. 1and the external clock signal input CLK to the DDR memory inFIG. 1. Delay T2represents the delay between the edge of the external DDR CLK signal to the DDR-SDRAM memory device ofFIG. 1and the delayed DQS signal from DQS delay circuit20ofFIG. 1that occurs after the access time of the DDR-SDRAM memory device. It will appear obvious to those skilled in the art that if T1and the access time are very low, then data D0and D1will be respectively stored in DataReg3and DataReg2one clock cycle before the sampling point of the system bus.

Consider the DDR memory device access time constant. If the system frequency is increased, the conditions shown inFIG. 7will exist. If the system frequency is reduced, the conditions shown inFIG. 6will exist. While T3is positive (i.e., greater than the DFF setup time plus the propagation delay of combinational logic that would be placed prior to drive the D input of the DFF) there is no problem. If, however, T3is less than this value or negative as shown inFIG. 7, there is a problem. As a consequence, if the access time varies due to operating condition changes (temperature, voltage, etc.) then either a range of temperature and/or range of voltage will be forbidden or, for a given operating conditions, a clock frequency range will be forbidden. T3is a consequence of T2and the system clock period. Therefore such read data stage circuitry cannot be used for mobile DDR-SDRAM memory devices at some frequencies.

Consider the system clock frequency to be constant. If the DDR memory device access time plus the time T1is increased, the conditions shown inFIG. 7will exist. If the DDR memory device access time is reduced, the conditions shown inFIG. 6will exist. While the DDR memory device access time plus the propagation delay of combinational logic that would be placed prior to drive the D input of the DFF plus the DFF setup time is greater than the system clock period there is no problem. On the contrary as shown inFIG. 6, there is a problem. As a consequence, if the access time varies due to operating condition changes (temperature, voltage, etc.), then either a range of temperature and/or range of voltage will be forbidden or, for given operating conditions, a range of access time will be forbidden. Therefore such read data stage circuitry cannot be used for mobile DDR-SDRAM memory devices under different operating conditions.

BRIEF DESCRIPTION OF THE INVENTION

According to the present invention, a circuit for sampling data from a memory device comprises a circuit for providing a clock signal to the memory device, a data bus carrying data at twice the rate of the clock signal, a circuit for providing a control signal to indicate the period of time where data are valid, and a set of registers whose content is triggered by both edges of a signal resulting from the delay of the control signal. The set of registers is divided into several sub-parts, each sub-part loading the value of the data bus carrying data provided by the memory device every other clock cycle (e.g., at a period being an integer multiple of the clock signal where the sampling point is different for each sub-part).

DETAILED DESCRIPTION OF THE INVENTION

The architecture of the present invention is designed to extend the clock range of mobile DDR-SDRAM memory devices at frequencies where the access time value is significant compared to the system clock period. The present invention allows the controller circuitry to handle the timings provided by mobile-DDR memory devices which slightly differs from standard DDR-SDRAM memory devices.

The read data stage of the invention is capable of managing both the mobile DDR-SDRAM access time and standard DDR-SDRAM access time and provides a single controller circuitry being able to perform safe data capture for both types of memory devices. The present invention allows driving mobile DDR-SDRAM memory devices at frequencies where the access time value is close to the clock period or comprises a significant portion of the clock period. The circuitry architecture allows a safe sampling of read data bus whatever the derating factors are (PVT=Process, Voltage, Temperature) and is tolerant compared to the placement and routing of the circuitry on silicon (layout). The read data stage architecture can also be used for standard DDR-SDRAM memory device therefore the memory controller can drive both types of DDR-SDRAM memory devices.

Referring now toFIG. 8, a block diagram shows a read data stage logic configuration according to the present invention for use in a DDR memory controller such as that shown inFIG. 1. Sixteen-bit DDR-SDRAM data is presented on lines72. Capture DFF74captures the data on the rising edge of the delayed DQS signal on delayed DQS line76. The output of capture DFF74is presented to capture DFF78through multiplexer80and to capture DFF82through multiplexer84. The Q output of capture DFF78provides the D0output and the Q output of capture DFF82provides the D2output.

Capture DFFs86and88accept data from lines72through multiplexers90and92, respectively. The Q output of capture DFF86provides the D1output and the Q output of capture DFF88provides the D3output. Multiplexers80,84,90, and92allow data to be recirculated in DFFs78,82,86, and88. DFF74is clocked by the delayed DQS signal on line76, and DFFs78,82,86, and88are clocked by the delayed DQS signal on line76inverted in inverter94.

Reset_sel on line96is a signal which is high when no read access is performed and which is cleared when a read access is started. When Reset_sel is set to logical “one,” DFF98, clocked by the delayed DQS on line76, inverter102, and AND gate104act as a divide-by-2 circuit providing waveform “dqs_en” at the output of DFF98that drives the select inputs of multiplexers80and90and the waveform “dqs_en!” at the output of inverter102that drives the select inputs of multiplexers84and92. Similarly, DFF106clocked by the system clock on line100, and AND gate108having an inverted input act as a divide-by-2 circuit that provides a “sel_D0D1” output at the Q output of DFF106.

The D0and D2outputs from capture DFFs78and82drive the data inputs of multiplexer110and the D1and D3outputs from capture DFFs86and88drive the data inputs of multiplexer112. The select inputs of multiplexers110and112are driven by the “sel_D0D1” output of DFF106.

The inputs to capture-data-register DFFs114and116are selected by means of multiplexers118and120, respectively. The clock inputs of DFFs114and116are both driven by system clock bus100. Multiplexers118and120are required to hold the data value on the system bus at the combined outputs of capture data DFFs114and116by recirculating the outputs of DFFs114and116when the input “sampling_enabled” on line122is not active.

By employing multiplexers80,84,90and92to re-circulate data into respective DFFs78,82,86, and88, under the control of the two divide-by-two circuits, the data bus coming from DDR-SDRAM memory device is sampled every two DQS cycles. This provides a longer data stability period and therefore allows accommodation of a greater operating frequency range.

Referring now toFIG. 9, a series of timing diagrams illustrate the operation of the circuit ofFIG. 8for a mobile DDR-SDRAM memory device under a best-case operating condition. From an examination ofFIG. 9, the difference between the location of the first sampling point achieved by employing the prior-art circuit ofFIG. 2and the location of the first sampling point achieved by employing the circuit ofFIG. 8can be seen in the bottom trace.

Referring now toFIG. 10, a series of timing diagrams illustrate the operation of the circuit ofFIG. 8for a mobile DDR-SDRAM memory device under a worst-case operating condition. From an examination ofFIG. 10, the difference between the location of the first sampling point achieved by employing the prior-art circuit ofFIG. 2and the location of the first sampling point achieved by employing the circuit ofFIG. 8can be seen in the bottom trace. Unlike the case with the circuit ofFIG. 8, the increased access time for the mobile DDR-SDRAM memory device does not adversely affect the data capture due to the increased data stability over two clock cycles instead of one as provided in the system ofFIG. 2.

Referring now toFIG. 11, a series of timing diagrams illustrate the operation of the circuit ofFIG. 8for a standard DDR-SDRAM memory device under best-case and worst-case operating conditions. The first data sampling point shown in the bottom trace occurs later in time than it would using the circuit ofFIG. 2.

Propagation delay is due to the data PAD propagation delay or propagation delay of feedback data logic in the circuit embedding the memory controller. To avoid any capture errors in best-case operating conditions if the propagation delay is significant (equal or greater than half the clock period) a modification may be made in the circuitry ofFIG. 8.

Referring now toFIG. 12, a block diagram shows an alternative read data stage logic configuration according to the present invention for use in a DDR memory controller such as that shown inFIG. 1. The circuit is substantially similar to the circuit shown inFIG. 8. In the description of the embodiment ofFIG. 12, elements corresponding to elements present inFIG. 8will be referred to using the same reference numerals used inFIG. 8.

In the circuit shown inFIG. 12, sixteen-bit DDR-SDRAM data is presented on lines72. The operation of the circuit ofFIG. 12is generally similar to that of the circuit ofFIG. 8.

InFIG. 12, the D0and D2outputs from capture DFFs78and82drive the data inputs of multiplexer136and the D1and D3outputs from capture DFFs86and88drive the data inputs of multiplexer138. The select inputs of multiplexers136and138are driven by the sel_D0D1output of DFF106.

InFIG. 12, the inputs to capture-data-register data latches132and134are selected by means of multiplexers136and138, respectively. The clock inputs of capture-data-register data latches132and134are both driven by the output of AND gate140, having one input driven by system clock bus100and the other input driven by sampling_enabled line122.

By employing multiplexers80,84,90, and92to re-circulate data into respective DFFs78,82,86, and88, under the control of the two divide-by-two circuits, the data bus coming from DDR-SDRAM memory device is sampled every two DQS cycles.

The signal traces associated with the circuit ofFIG. 12are shown inFIG. 13. As shown in the last trace ofFIG. 13, the sampling point is the same that shown inFIG. 11. This is done by the logic driving the signal “sampling Enabled” on line122and “reset_sel” on line96.

In the traces shown inFIG. 13, it can be seen that delay T3is reduced as the propagation delay increases in the clock PAD buffer. T3may be reduced by other propagation delays, such as DDR data arriving late compared to the DQS signal, the data feedback logic delay including the PAD propagation delay due to input mode buffer38ofFIG. 1, or the propagation delay of the DFFs ofFIG. 2if this net is buffered for design rules. Therefore there is a risk that T3will violate the setup time of a DFF if the circuit ofFIG. 8is used, but in the circuit ofFIG. 13the latch remains opened for the high-level period of the clock, and there is no problem with the setup margin.

The present invention solves the problem of driving both mobile and standard DDR-SDRAM memory devices without any need to employ a data FIFO. The number of data capture registers is increased and each of them samples every two clock cycles compared with sampling each clock cycle in prior-art architectures. The first sampling point is delayed by one clock cycle compared to the prior-art architecture. Even if delayed by one clock cycle in prior-art architectures, the problem would not have been solved because the worst-case timing would operate correctly but the best-case timing would not operate correctly since the first data would be lost and the data sequence would start with D2D3instead of D0D1as shown inFIG. 6.

The capture registers are sampling read data once every two clock cycles, therefore they are holding data for two clock cycles. Therefore, whatever the access time of the DDR-SDRAM memory device (assuming it is not greater than one clock cycle) the data held by the capture registers can be sampled in a safe way because two clock cycles of stability is greater than one clock cycle of access time variance. To have the correct data sequence on the system bus, the selection of the capture registers have to be switched every clock cycle. The number of sample registers is double and each set of registers samples DDR data during a different clock cycle from the other set. The selection between each set of registers is switched every clock cycle as can be seen inFIG. 11.