Forming embedded dielectric layers adjacent to sidewalls of shallow trench isolation regions

A semiconductor structure is provided. The semiconductor structure includes a semiconductor substrate; an insulating region extending from substantially a top surface of the semiconductor substrate into the semiconductor substrate; an embedded dielectric spacer adjacent the insulating region, wherein a bottom of the embedded dielectric spacer adjoins the semiconductor substrate; and a semiconductor material adjoining a top edge and extending on a sidewall of the embedded dielectric spacer.

TECHNICAL FIELD

This invention relates generally to integrated circuits, and more particularly to metal-oxide-semiconductor (MOS) devices having stressed channel regions and fabrication methods for forming the same, and even more particularly, to a method of reducing compressive stresses applied by shallow trench isolation regions.

BACKGROUND

With integrated circuits becoming smaller and faster, the improvement in device driving currents of metal-oxide-semiconductor (MOS) devices becomes increasingly more important. Device current is closely related to gate length, gate capacitance, and carrier mobility. Shortening poly-gate length, increasing gate capacitance, and increasing carrier mobility can improve the device current performance. Gate length reduction is an on-going effort coming with the effort to shrink circuit size. Increasing gate capacitance has also been achieved by efforts such as reducing the gate dielectric thickness, increasing the gate dielectric constant, and the like. In order to further improve device current, enhancing carrier mobility has also been explored.

Among efforts made to enhance the carrier mobility, forming stressed channels is a known practice. Stress can enhance bulk mobility of electrons and holes, and hence the performance of MOS devices can be enhanced through stressed-surface channels. This technique allows the performance of MOS devices to be improved at a constant gate length, without adding complexity to circuit fabrication or design.

When silicon is placed under stress, the in-plane, room temperature electron mobility is dramatically increased. One way to develop stress is by using a graded SiGe epitaxy layer as a substrate on which a layer of relaxed SiGe is formed. A layer of silicon is formed on the relaxed SiGe layer. MOS devices are then formed on the silicon layer, which has an inherent stress. Since the lattice constant of SiGe is greater than that of Si, the Si film is under biaxial tension and thus the carriers exhibit stress-enhanced mobility.

Stress in a device may have components in three directions: parallel to the MOS device channel length, parallel to the device channel width, and perpendicular to the channel plane. The stresses parallel to the device channel length and width are called in-plane stresses. Research has revealed that a bi-axial, in-plane tensile stress field can improve the performance of n-type MOS (NMOS), and a compressive stress parallel to the channel length direction can improve the performance of p-type MOS (PMOS device).

Typically, STI regions apply compressive stresses to the channel regions of nearby MOS devices. This is beneficial to the PMOS devices while detrimental to the NMOS devices. In further explorations, local mechanical stress-control technologies have been reported to improve device performance of NMOS devices by using sub-atmospheric chemical vapor deposition (SACVD) to form shallow trench isolation regions. Since the high-shrinkage material in the STI regions reduce the adverse compressive stress applied to the channel regions of NMOS device, the degradation in the performance of NMOS devices is less severe. Other methods to increase desirable stresses or to reduce undesirable stresses in the channel regions are also needed.

SUMMARY OF THE INVENTION

In accordance with one aspect of the present invention, a semiconductor structure includes a semiconductor substrate; an insulating region extending from substantially a top surface of the semiconductor substrate into the semiconductor substrate; an embedded dielectric spacer adjacent the insulating region, wherein a bottom of the embedded dielectric spacer adjoins the semiconductor substrate; and a semiconductor material adjoining a top edge and extending on a sidewall of the embedded dielectric spacer.

In accordance with another aspect of the present invention, a semiconductor structure includes a semiconductor substrate; a shallow trench isolation (STI) region in the semiconductor substrate; a gate stack on a top surface of the semiconductor substrate; and a recess extending from the top surface of the semiconductor substrate into the semiconductor substrate. The recess is between the STI region and the gate stack, and has a first sidewall facing the STI region and a second sidewall facing the gate stack. The semiconductor structure further includes an embedded spacer in the recess and on the first sidewall of the recess; and a semiconductor material filling a remaining portion of the recess.

In accordance with yet another aspect of the present invention, a semiconductor structure includes a semiconductor substrate; a shallow trench isolation (STI) region in the semiconductor substrate; a gate stack on a top surface of the semiconductor substrate; and an epitaxial semiconductor material in a recess of the semiconductor substrate. The semiconductor material is between the STI region and the gate stack. The epitaxial semiconductor material includes a bottom portion having a first sidewall facing the STI region and a second sidewall facing the gate stack. The semiconductor structure further includes an embedded dielectric spacer adjoining the first sidewall of the epitaxial semiconductor material, wherein a top portion of the epitaxial semiconductor material extends on a top edge of the embedded dielectric spacer.

In accordance with yet another aspect of the present invention, a method for forming a semiconductor structure includes providing a semiconductor substrate; forming an insulating region in the semiconductor substrate; etching the semiconductor substrate to form a recess using the insulating region as a mask; forming an embedded dielectric spacer in the recess and on a sidewall of the recess, wherein the sidewall of the recess faces the insulating region; and filling the recess with a semiconductor material.

In accordance with yet another aspect of the present invention, a method for forming a semiconductor structure includes providing a semiconductor substrate; forming a shallow trench isolation (STI) region in the semiconductor substrate; forming a gate stack on the semiconductor substrate and adjacent the STI region; forming a gate spacer on a sidewall of the gate stack, wherein the gate spacer is between the gate stack and the STI region; using the gate stack, the gate spacer and the STI region as a mask to recess an exposed portion of the semiconductor substrate between the gate spacer and the STI region to form a recess; blanket forming a spacer layer, wherein the spacer layer extends into the recess; etching the spacer layer to form an embedded dielectric spacer in the recess; and epitaxially growing a semiconductor material in the recess to form an epitaxial region.

The embedded dielectric spacers formed in the recesses have the advantageous features of blocking undesirable stresses applied to channel regions of MOS devices by the nearby shallow trench isolation regions. The performance of MOS devices is thus improved.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

A novel method for reducing undesirable stresses in metal-oxide-semiconductor (MOS) devices and the resulting structures are provided. The intermediate stages of manufacturing embodiments of the present invention are illustrated. Throughout the various views and illustrative embodiments of the present invention, like reference numbers are used to designate like elements.

Referring toFIG. 1, substrate20is provided. In an embodiment, substrate20is a bulk silicon substrate. In other embodiments, substrate20comprises silicon germanium, silicon carbon, and the like. In yet other embodiments, substrate20has a silicon-on-insulator structure.

Optional pad layer22and hard mask layer24are formed over substrate20. Pad layer22is preferably a thin oxide film formed through a thermal process, and is preferably used for reducing the stress between substrate20and the subsequently formed hard mask layer24. In the preferred embodiment, hard mask layer24is formed of silicon nitride using low-pressure chemical vapor deposition (LPCVD). In other embodiments, hard mask layer24is formed of high-density plasma (HDP) nitride or plasma enhanced silicon nitride. In yet other embodiments, hard mask layer24is formed by thermal nitridation or plasma anodic nitridation of silicon using nitrogen. Photo resist26is formed and patterned over hard mask layer24.

Referring toFIG. 3, a dielectric material is filled into openings28, followed by a chemical mechanical polish (CMP) to remove excess dielectric material, leaving shallow trench isolation (STI) regions34in openings28. Hard mask layer24is used as a CMP stop layer. Preferably, the dielectric material is filled using a high-shrinkage gap-filling process, so that the resulting dielectric material has a high shrinkage rate when annealed. The methods for filling dielectric material is preferably selected from sub-atmospheric chemical vapor deposition (SACVD), high-density plasma deposition processes such as high-density plasma CVD, spin-on, and the like. However, other commonly used methods for forming high-shrinkage dielectric materials can also be used. The process precursors may include tetra ethyl ortho silicate (TEOS), O3, silane, NH3, N2, H2, O2, and combinations thereof.

Mask layer24and pad layer22are then removed, as shown inFIG. 4. Mask layer24, if formed of silicon nitride, may be removed using a H3PO4, while pad layer22may be removed using diluted HF if it is formed of silicon oxide.

Again referring toFIG. 4, gate dielectric38and gate electrode40are formed, followed by the formation of lightly doped source/drain (LDD) regions42. As is known in the art, gate dielectric38may include silicon oxide or high-k dielectric materials, and gate electrode40may include doped polysilicon or metal-containing conductive materials. The details for forming gate dielectric38, gate electrode40, and LDD regions42are well known in the art, and thus are not repeated herein. In the preferred embodiment, the resulting MOS device is an NMOS device. Accordingly, LDD regions42are preferably doped with n-type impurities, such as phosphorus, arsenic, and combinations thereof. If, however, a PMOS device is to be formed, LDD regions42will be doped with p-type impurities.

FIG. 4also illustrates the formation of dummy spacers44. As is known in the art, the formation of dummy spacers44preferably includes forming a spacer layer, and removing horizontal portions of the spacer layer using dry etching. The side edges46of dummy spacers44are preferably tilted, with a tilt angle α of less than 90 degrees, and more preferably less than about 75 degrees. Tilt angle α may be reduced by adjusting the structure and/or materials of the spacer layer. Alternatively, tilt angle α is reduced by adjusting the process conditions in the dry etching. Dummy spacers44may include materials such as silicon nitride, silicon oxide, and the like, and can be formed using commonly used methods such as plasma enhanced chemical vapor deposition (PECVD).

InFIG. 5, the exposed portions of substrate20are recessed, forming recesses48. In an exemplary embodiment, recesses48have depth D1of between about 40 nm and about 100 nm. In the preferred embodiment, the recessing is anisotropic. Since the sidewalls of STI regions34are typically slightly tilted, thin substrate regions49may remain on sidewalls of STI regions34. If, however, the sidewalls of STI regions34are substantially vertical, substrate regions49will be removed during the recessing of substrate20. In other embodiments, the recessing is isotropic, and hence substrate regions49are removed even if the sidewalls of STI regions34are tilted. Please note that in the formation of recesses48, STI regions34, gate electrode40, and dummy spacers44are used as a mask, hence the formation of recesses48is self-aligned. Therefore, the embodiments of the present invention are highly scalable.

Embedded dielectric layer50is then blanket formed. Embedded dielectric layer50may be formed of commonly used dielectric materials, which preferably have the ability of blocking the compressive stress applied by STI regions34. Exemplary materials include silicon oxide, silicon oxynitride, tetraethoxysilane (TEOS) oxide, and combinations thereof. Embedded dielectric layer50may also be a composite layer including more than one layer, for example, a silicon nitride layer on a TEOS oxide layer. The thickness T of embedded dielectric layer50is preferably between about 25 nm and about 85 nm. In an embodiment, embedded dielectric layer50is formed of a different dielectric material from dummy spacers44, so that in the subsequent patterning (and possibly removal) of embedded dielectric layer50, dummy spacers44are substantially intact.

FIGS. 6A through 6Cillustrate the formation of embedded spacers54and56. Referring toFIG. 6A, a dry etching is performed to remove horizontal portions of embedded dielectric layer50, forming embedded spacers54and56. Preferably, the top edges60of embedded spacers56are lower than the bottom surface of gate dielectric38to ensure that the channel region of the resulting MOS device is not electrically insulated from the subsequently formed source/drain regions. More preferably, distance D2between the top edges60of embedded spacers56and the bottom surface of gate dielectric38is substantially equal to, or greater than the thickness of channel region61of the resulting MOS device. In an exemplary embodiment, distance D2is greater than about 50 Å, and more preferably between about 100 Å and about 350 Å. Advantageously, with dummy spacers44having tilted edges46, the portions of embedded dielectric spacer layer50higher than the bottom surface of gate dielectric38can be fully removed.

FIG. 6Billustrates a top view of the structure shown inFIG. 6A. Embedded spacers54and56form a spacer ring encircling a source region of the resulting MOS device, and a spacer ring encircling a drain region of the resulting MOS device.

FIG. 6Cillustrates another embodiment. After the formation of embedded spacers54and56, photo resist58is formed to mask embedded spacers54, leaving embedded spacers56exposed. An etching, which is preferably a wet etching, is then performed to remove embedded spacers56. In this embodiment, top edges62of embedded spacers54may be slightly lower than the bottom surface of gate dielectric38. More preferably, top edges62are either substantially level with, or higher than, the bottom surface of gate dielectric38to achieve better stress blocking ability.

In the embodiment substrate regions49are removed (refer toFIG. 5), embedded spacers54physically contact the sidewall of STI regions34. Otherwise, embedded spacers54directly contact sidewalls of substrate regions49.

FIG. 7illustrates the growth of epitaxial regions66in recesses48, preferably using selective epitaxial growth (SEG). In an embodiment, substantially pure silicon may be grown in recesses48. Desirable impurities, preferably n-type impurities, may be doped when the epitaxial growth proceeds. Elements that can change the lattice constant of epitaxial regions66are preferably added in order to apply a desirable stress to the channel region64of the resulting MOS device. In the preferred embodiment, silicon carbon is epitaxially grown in recesses48, wherein the atomic percentage of carbon is preferably between about 1 percent and about 2 percent. Alternatively, SiGe is grown in recesses48, wherein the germanium atomic percentage is preferably between about 10 percent and about 25 percent.

The epitaxial growth of epitaxial regions66may be performed in a single step. Alternatively, a two-step growth is performed. Epitaxial regions661(bottom portions of epitaxial regions66), which have top surfaces substantially level with the top edges of the embedded spacers56and/or54, are first formed. Process conditions are then changed to form epitaxial regions662(top portions of epitaxial regions66). In a first embodiment, the formation of epitaxial regions661is specifically tuned to reduce the dislocations. In a second embodiment, epitaxial regions661have a lower carbon atomic percentage than epitaxial regions662, so that a greater tensile stress is applied to channel region64by epitaxial regions66. Preferably, epitaxial regions66have top surfaces higher than the bottom surface of gate dielectric38.

InFIG. 8, dummy spacers44are removed, followed by the formation of gate spacers74. Preferably, gate spacers74have a greater thickness than the dummy spacers44. Alternatively, spacers44are left in the final structure. Source and drain regions68and source/drain silicide regions70are then formed. As is known in the art, to form an NMOS device, the source/drain regions68are implanted with n-type impurities, while the formation of a PMOS device requires the implantation of p-type impurities. The formation of source/drain silicide regions70includes blanket forming a metal layer, performing an annealing to react the metal layer with the underlying silicon, and removing the un-reacted metal layer. MOS device72is thus formed. The details for forming source/drain regions68and source/drain silicide regions70are well known in the art, and hence are not repeated herein.

STI regions34typically apply a compressive stress to the channel region61of MOS device72. Advantageously, for NMOS devices, by forming STI regions34with high shrinkage materials using SACVD and the like, the adverse compressive stress applied by STI regions34is reduced. The embedded spacers54and56have the advantageous features of blocking the adverse compressive stress, which were proven by simulation results. Further, simulation results performed on the NMOS devices revealed that the embodiments of the present invention have improved drive currents and leakages currents due to the blockage of the adverse compressive stress.FIG. 9illustrates an I-V curve of a first sample MOS device (solid circles) including embedded spacers54, and a second sample MOS device (solid squares) having similar structure as the first sample MOS device except that the second sample device has no embedded spacers54. It can be found fromFIG. 9that the drive current of the first sample device is significantly higher than that of the second sample device. In further simulations, it was found that at the same operating conditions, the first sample MOS device has a drain-source leakage current of about 132 nA/μm, while the drain-source leakage current of the second sample MOS device is about 1267 nA/μm, which is one order greater than the first sample device. This may partially due to the reason the formation of the embedded spacer reduces the junction leakage currents along the sidewalls of the STI regions.