Three-dimensional memory device and manufacturing method thereof

A three-dimensional memory device including first and second stacking structures and first and second conductive pillars is provided. The first stacking structure includes first stacking layers stacked along a vertical direction. Each first stacking layer includes a first gate layer, a first channel layer, and a first ferroelectric layer between the first gate and channel layers. The second stacking structure is laterally spaced from the first stacking structure and includes second stacking layers stacked along the vertical direction. Each second stacking layer includes a second gate layer, a second channel layer, and a second ferroelectric layer is between the second gate and channel layers. The first and second gate layers are disposed between the first and second ferroelectric layers, and the first and second conductive pillars extend along the vertical direction in contact respectively with the first and second channel layers.

BACKGROUND

Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. For example, a three-dimensional (3D) memory device has been introduced to replace a planar memory device. However, the 3D memory device has not been satisfactory in all respects. Additional problems arise that should be addressed.

DETAILED DESCRIPTION

Among various non-volatile memories, the ferroelectric field effect transistor (FeFET) is a promising candidate for high-density, low-power application. Due to its field-driven operation, the FeFET has advantages such as non-destructive readout, high program/erase speed, and low power consumption. In addition, the FeFET has attracted more attention because of its high scalability and high CMOS compatibility. Toward even higher density, a three-dimensional (3D) vertical structure is proposed. Generally, poly-silicon is used as a channel material. However, there are several challenges with the poly-silicon channel, such as low carrier mobility at the very thin poly-silicon channel and an interfacial layer with a low dielectric constant between the ferroelectric material and the poly-silicon. Because of the capacitance mismatch between the interfacial layer with a low dielectric constant and the ferroelectric material, a large voltage is applied on the interfacial layer during operation. This eventually results in the breakdown of the interfacial layer, thereby causing an endurance failure. In addition, the interfacial layer with low dielectric constant increases charge trapping, which results in a threshold voltage shift issue that degrades reliability.

To overcome the foregoing challenges, a FeFET with an oxide semiconductor channel is proposed. The oxide semiconductor channel is suitable for fast access speeds due to its high carrier mobility with a very thin body.

FIG.1AtoFIG.11Aare schematic top views of structures produced at various stages of a manufacturing method of a three-dimensional memory device10in accordance with some embodiments of the disclosure.FIG.1BtoFIG.11Bare schematic cross-sectional views along the lines A-A′ shown inFIG.1AtoFIG.11A, respectively.FIG.4CtoFIG.11Care schematic plan views along the lines B-B′ shown inFIG.4BtoFIG.11B, respectively.

Referring toFIG.1AandFIG.1B, a multilayer stack110is formed on the substrate100. The multilayer stack110includes insulating layers112and sacrificial layers114. As shown inFIG.1B, the insulating layers112and the sacrificial layers114are alternately stacked on the substrate100along a direction Z. In detail, the insulating layers112are space apart from one another by the sacrificial layers114along the direction Z. That is to say, the insulating layers112are vertically space apart from one another by the sacrificial layers114. From another point of view, each sacrificial layer114is sandwiched between an underlying insulating layer112and an overlying insulating layer112. Further, the sacrificial layers114will be replaced by gate layers118in the subsequent steps to be described with reference toFIGS.9A-9CandFIGS.10A-10C. Although three insulating layers112and two sacrificial layers114are presented inFIG.1Bfor illustrative purposes, those skilled in the art can understand that the number of the insulating layers112and the number of the sacrificial layers114may be more than what are depicted inFIG.1B, and may be designated based on demand and/or design layout.

In some embodiments, the material of the insulating layers112has a sufficient etching selectivity with respect to the material of the sacrificial layers114, such that the insulating layers112could remain substantially intact during removal of the sacrificial layers114in the subsequent step as to be described with reference toFIGS.9A-9C. In some embodiments, the insulating layers112are made of silicon oxide, while the sacrificial layers114are made of silicon nitride. However, those skilled in the art may select other suitable materials for the insulating layers112and the sacrificial layers114according to process requirements. In some alternative embodiments, the material of the insulating layers112may be selected from silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borosilicate glass (BSG), or boron-doped phosphosilicate glass (BPSG), and the material of the sacrificial layers114may be selected from silicon oxide, silicon oxynitride, PSG, BSG, or BPSG. In some embodiments, the insulating layers112have the same dielectric material, such as silicon oxide. However, the embodiments of the present disclosure are not limited thereto. In some alternative embodiments, the insulating layers112may have different dielectric materials. Similarly, in some embodiments, the sacrificial layers114have the same dielectric material, such as silicon nitride. However, the embodiments of the present disclosure are not limited thereto. In some alternative embodiments, the sacrificial layers114may have different dielectric materials. In some embodiments, the method for forming each of the insulating layers112and each of the sacrificial layers114includes a deposition process, such as a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process.

In some embodiments, the substrate100is an etching stop layer formed over a complementary metal-oxide-semiconductor (CMOS) integrated circuit. In these embodiments, the material of the substrate100has a sufficient etching selectivity with respect to the materials in the multilayer stack110. In these embodiments, the material of the substrate100includes silicon carbide, silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon oxide, or silicon nitride. In those embodiments where the insulating layers112and the sacrificial layers114are made of silicon oxide and silicon nitride, the material of the substrate100is formed of silicon carbide. However, the disclosure is not limited thereto. In some alternative embodiments, the substrate100is a semiconductor wafer or a semiconductor-on-insulator (SOI) wafer.

In some embodiments, along the direction Z, the insulating layers112have a thickness t1in the range of about 15 nm to about 90 nm, and the sacrificial layers114have a thickness t2in the range of about 15 nm to about 90 nm. In some embodiments, the insulating layers112are formed to a different thickness than the sacrificial layers114. In some alternative embodiments, the insulating layers112are formed to the same thickness as the sacrificial layers114. For example, the thickness t2of the sacrificial layers114is from about 10% to about 50% greater than or less than the thickness t1of the insulating layers112. In some embodiments, the multilayer stack110has an overall height h1in the range of about 1000 nm to about 10000 nm along the direction Z.

Referring toFIG.2AandFIG.2B, trenches TR1are formed in the multilayer stack110. As shown inFIG.2B, the trenches TR1penetrate through the multilayer stack110along the direction Z. That is to say, the trenches TR1vertically extend in the multilayer stack110. In the illustrated embodiment, the trenches TR1vertically extend through all layers (e.g., all of the insulating layers112and all of the sacrificial layers114) of the multilayer stack110and expose the substrate100. That is to say, the bottom surfaces of the trenches TR1are defined by the substrate100. In other words, the substrate100is exposed at the bottoms of the trenches TR1. However, the disclosure is not limited thereto. In some alternative embodiments, the trenches TR1vertically extend through some but not all layers of the multilayer stack110. For example, the trenches TR1may vertically extend through all of the sacrificial layers114and expose the bottommost insulating layer112. Although three trenches TR1are presented inFIG.2AandFIG.2Bfor illustrative purposes, those skilled in the art can understand that the number of the trenches TR1may be more than what is depicted inFIG.2AandFIG.2B, and may be designated based on demand and/or design layout.

As shown in the top view ofFIG.2A, the trenches TR1vertically penetrating through the multilayer stack110laterally extend along a direction Y perpendicular to the direction Z and are arranged along a direction X perpendicular to the direction Y and the direction Z. Accordingly, the multilayer stack110is cut into multiple strip portions by the trenches TR. In such case, the multiple strip portions are referred to as the remaining portions of the multilayer stack110hereinafter. Further, after forming the trenches TR1, each remaining portion of the multilayer stack110is disposed between two adjacent trenches TR1along the direction X. That is to say, two adjacent remaining portions of the multilayer stack110are spaced apart from each other by the corresponding trench TR1. In some embodiments, the remaining portions of the multilayer stack110have a width w1in the range of about 50 nm to about 200 nm along the direction X and further have the height h1discussed with respect toFIG.1AandFIG.1B. In some embodiments, the trenches TR1have a width w2in the range of about 50 nm to about 200 nm along the direction X. The aspect ratio (AR) of each remaining portion of the multilayer stack110is the ratio of the height h1to the width of the narrowest feature of the remaining portion of the multilayer stack110, which is the width w1at this step of processing. In addition, as shown inFIG.2B, the trenches TR1expose the side surfaces of the remaining portions of the multilayer stack110. That is to say, the sidewalls of the trenches TR1are defined by the remaining portions of the multilayer stack110. In the illustrated embodiment, the trenches TR1completely expose the side surfaces of the remaining portions of the multilayer stack110. That is to say, the trenches TR1expose the side surfaces of all layers (e.g., all of the insulating layers112and all of the sacrificial layers114) in the remaining portions of the multilayer stack110. However, the disclosure is not limited thereto. In some alternative embodiments, the trenches TR1partially expose the side surfaces of the remaining portions of the multilayer stack110. In some embodiments, the side surfaces of the insulating layers112are substantially coplanar or flush with the side surfaces of the sacrificial layers114in the current step.

In some embodiments, the method for forming the trenches TR1includes a lithography process and an etching process (e.g., an anisotropic etching process). Since the substrate100has sufficient etching selectivity with respect to the materials in the multilayer stack110, the substrate100may remain substantially intact during the etching process. In some embodiments where the substrate100is formed of silicon carbide, the insulating layers112are formed of silicon oxide, and the sacrificial layers114are formed of silicon nitride, the trenches TR1are formed by a dry etch using a fluorine-based gas (e.g., C4F6) mixed with hydrogen (e.g., H2) or oxygen (e.g., O2) gas.

Referring toFIG.3AandFIG.3B, the sacrificial layers114in the remaining portions of the multilayer stack110are laterally recessed with respect to the insulating layers112in the remaining portions of the multilayer stack110. As shown inFIG.3B, portions of the sacrificial layers114exposed by the trenches TR1are removed to form recesses R. Each of the recesses R is formed between two adjacent insulating layers112. Each of the recesses R is connected to (e.g., in spatial communication with) the corresponding trench TR1. From another point of view, as shown inFIG.3B, the side surfaces of the sacrificial layers114are exposed by the recesses R and the trenches TR1, and the exposed side surfaces of the sacrificial layers114are no longer coplanar with the exposed side surfaces of the insulating layers112, but are laterally recessed from the exposed side surfaces of the insulating layers112. Although the exposed side surfaces of the sacrificial layers114are illustrated inFIG.3Bas being straight, the side surfaces may be concave or convex.

In some embodiments, a method for laterally recessing the sacrificial layers114includes an etching process, such as an isotropic etching process. During such etching process, the insulating layers112may be barely etched as having sufficient etching selectivity with respect to the sacrificial layers114. That is to say, the etching process used to form the recesses R is one that is selective to the material of the sacrificial layers114(e.g., selectively etches the material of the sacrificial layers114at a faster rate than the material of the insulating layers112). From another point of view, since the substrate100has sufficient etching selectivity with respect to the materials in the multilayer stack110, the substrate100may remain substantially intact during such etching process. In some embodiments where the substrate100is formed of silicon carbide, the insulating layers112are formed of silicon oxide, and the second sacrificial layers114are formed of silicon nitride, the trenches TR1are expanded to form the recesses R by a wet etch using phosphoric acid (e.g., H3PO4). However, the embodiments of the disclosure are not limited thereto. In some alternative embodiments, a dry etch selective to the material of the sacrificial layers114may be used.

After formation, each of the recesses R has a depth dl extending past the sidewalls of the insulating layers112along the direction X. Timed etching processes may be used to stop the etching of the recesses R after the recesses R reach a desired depth dl. In some embodiments, the depth dl of the recesses R is in the range of about 5 nm to about 20 nm. From another point of view, forming the recesses R reduces the width of the sacrificial layers114. In some embodiments, each of the sacrificial layers114has a width w3in the range of about 20 nm to about 100 nm along the direction X after forming the recesses R. As noted above, the aspect ratio (AR) of each remaining portion of the multilayer stack110is the ratio of the height h1to the width of the narrowest feature of the remaining portion of the multilayer stack110, which is the width w3at this step of processing. Forming the recesses R thus increases the aspect ratio of each remaining portion of the multilayer stack110.

Referring toFIG.4A,FIG.4B, andFIG.4C, ferroelectric layers120are formed in the recesses R. In detail, as shown inFIG.4BandFIG.4C, each of the ferroelectric layers120is formed within one of the recesses R in a one-to-one relationship. The ferroelectric layer120is formed to cover or contact the side surface of the corresponding sacrificial layer114exposed by the corresponding recess R. As such, in each remaining portion of the multilayer stack110, the adjacent ferroelectric layers120along the direction X are laterally spaced apart from each other by the corresponding sacrificial layer114. Further, as shown inFIG.4B, one of the sacrificial layers114and the corresponding ferroelectric layers120are at substantially the same level in each remaining portion of the multilayer stack110. Herein, when elements are described as “at substantially the same level”, the elements are formed at substantially the same height. From another point of view, as shown inFIG.4B, the ferroelectric layers120are each embedded between two adjacent insulating layers112. In other words, the ferroelectric layers120along the direction Z are vertically spaced apart from each other by the corresponding insulating layer112.

In some embodiments, the ferroelectric layers120are formed by the following steps. First, a ferroelectric material is formed over the substrate100to fill in the recesses R between the insulating layers112. In some embodiments, the ferroelectric material not only fills the recesses R, but also further covers the side surfaces of the insulating layers112exposed by the trenches TR1, the top surface of the topmost insulating layer112, and the top surface of the substrate100exposed by the trenches TR1. In some embodiments, the method for forming the ferroelectric material includes a deposition process, such as a CVD process or an ALD process. Thereafter, the portions of the ferroelectric material covering the side surfaces of the insulating layers112exposed by the trenches TR1, the top surface of the topmost insulating layer112, and the top surface of the substrate100exposed by the trenches TR1are removed, so as to form the separate and disconnected ferroelectric layers120. In some embodiments, the method for removing some portions of the ferroelectric material includes performing an isotropic etching process. However, the disclosure is not limited thereto. In some alternative embodiments, an anisotropic etching process is performed followed by performing an isotropic etching process to remove some portions of the ferroelectric material.

In some embodiments, the ferroelectric layers120include a ferroelectric material that is capable of switching between two different polarization directions by applying appropriate voltage differentials across the ferroelectric layers120. For example, the polarization of a ferroelectric layer120changes due to an electric field resulting from applying the voltage differential. In some embodiments, the ferroelectric material of the ferroelectric layers120includes hafnium zirconium oxide (e.g., HZO), silicon-doped hafnium oxide (e.g., HSO), hafnium silicon oxide (e.g., HfSiO), hafnium lanthanum oxide (e.g., HfLaO), hafnium oxide (e.g., HfO2), hafnium zirconium oxide (e.g., HfZrO2), zirconium oxide (e.g., ZrO2), or HfO2doped by lanthanum (e.g., La), yttrium (e.g., Y), silicon (e.g., Si), or germanium (e.g., Ge). However, the disclosure is not limited thereto. In some alternative embodiments, the ferroelectric material of the ferroelectric layers120may be a high-k dielectric material, such as a hafnium (Hf) based dielectric material, or the like. For example, the ferroelectric material may be a hafnium-containing compound, such as hafnium zirconium oxide (e.g., HfZnO), hafnium aluminum oxide (e.g., HfAlO), hafnium lanthanum oxide (e.g., HfLaO), hafnium cerium oxide (e.g., HfCeO), hafnium oxide (e.g., HfO), hafnium gadolinium oxide (e.g., HfGdO), hafnium silicon oxide (e.g., HfSiO), hafnium zirconium lanthanum oxide (e.g., HfZrLaO), hafnium zirconium gadolinium oxide (e.g., HfZrGdO), hafnium zirconium yttrium oxide (e.g., HfZrYO), hafnium zirconium cerium oxide (e.g., HfZrCeO), hafnium zirconium strontium oxide (e.g., HfZrSrO), or the like. In addition, the hafnium-containing compound may further be doped by some dopants, such as lanthanum (e.g., La), yttrium (e.g., Y), silicon (e.g., Si), germanium (e.g., Ge), cerium (e.g., Ce), gadolinium (e.g., Gd), strontium (e.g., Sr), or the like, or a combination thereof. By doping these dopants in the hafnium-containing compound, an orthorhombic lattice structure can be achieved in the ferroelectric layers120. In some embodiments, the hafnium-containing compound with the orthorhombic lattice structure has a desired ferroelectric property to achieve the switchable performance of the ferroelectric layers120in the memory device. In addition, by including the dopants, an orthorhombic lattice structure in the ferroelectric layers120may be achieved relatively easily (e.g., at a lower temperature), and the ferroelectric layers120may be formed within the relatively low thermal budget of back-end-of-line (BEOL) processes (e.g., at a temperature that does not damage front end of line (FEOL) features).

As shown in the plan view ofFIG.4C, the ferroelectric layers120laterally extend along the direction Y. In some embodiments, the ferroelectric layers120have a thickness t3(see, e.g.,FIG.4B) substantially the same as the thickness t2of the sacrificial layers114(see, e.g.,FIG.4B) along the direction Z. In some embodiments, the thickness t3of the ferroelectric layers120is in the range of about 3 nm to about 15 nm. In some embodiments, along the direction X, the ferroelectric layers120have a width w4(see, e.g.,FIG.4C) less than the depth dl of the recess R (see, e.g.,FIG.4B). That is to say, the recesses R are partially occupied by the corresponding ferroelectric layers120. Timed etching processes may be used to stop the etching of the ferroelectric layers120after the ferroelectric layers120reach a desired width w4. In some embodiments, the width w4of the ferroelectric layers120is in the range of about 3 nm to about 15 nm along the direction X.

With continued reference toFIG.4BandFIG.4C, channel layers122are formed in the recesses R. In detail, as shown inFIG.4BandFIG.4C, each of the channel layers122is formed within one of the recesses R in a one-to-one relationship. The channel layer122is formed to cover or contact the side surface of the corresponding ferroelectric layer120exposed by the corresponding recess R. As such, in each remaining portion of the multilayer stack110, the corresponding channel layers122along the direction X are laterally spaced apart from each other by the corresponding ferroelectric layers120and the corresponding sacrificial layer114. Further, as shown inFIG.4B, one of the sacrificial layers114, the corresponding ferroelectric layers120, and the corresponding channel layers122are at substantially the same level in each remaining portion of the multilayer stack110. From another point of view, as shown inFIG.4B, the channel layers122are each embedded between two adjacent insulating layers112. In other words, the channel layers122along the direction Z are vertically spaced apart from each other by the corresponding insulating layers112.

In some embodiments, the channel layers122are formed by the following steps. First, a channel material is formed over the substrate100to fill in the recesses R between the insulating layers112. In some embodiments, the channel material not only fills up the recesses R, but also further covers the side surfaces of the insulating layers112exposed by the trenches TR1, the top surface of the topmost insulating layer112, and the top surface of the substrate100exposed by the trenches TR1. In some embodiments, the method for forming the channel material includes a deposition process, such as a CVD process or an ALD process. Thereafter, the portions of the channel material covering the side surfaces of the insulating layers112exposed by the trenches TR1, the top surface of the topmost insulating layer112, and the top surface of the substrate100exposed by the trenches TR1are removed, so as to form the separate and disconnected channel layers122. In some embodiments, the method for removing some portions of the channel material includes performing an anisotropic etching process.

In some embodiments, the channel material of the channel layers122includes a metal oxide (or oxide semiconductor), such as an indium-based oxide material (e.g., indium gallium zinc oxide (e.g., IGZO)). Other suitable materials for the channel layers122include zinc oxide (e.g., ZnO), indium tungsten oxide (e.g., InWO), tungsten oxide (e.g., WO), tantalum oxide (e.g., TaO), and molybdenum oxide (e.g., MoO).

As shown in the plan view ofFIG.4C, the channel layers122laterally extend along the direction Y, and the ferroelectric layers120are disposed between the corresponding channel layer122and the corresponding sacrificial layer114. In some embodiments, the channel layers122have a thickness t4(see, e.g.,FIG.4B) substantially the same as the thickness t2of the sacrificial layers114(see, e.g.,FIG.4B) along the direction Z. In some embodiments, the thickness t4of the channel layers122is in the range of about 5 nm to about 15 nm. In some embodiments, along the direction X, the channel layers122have a width w5(see, e.g.,FIG.4C) less than the depth dl of the recess R (see, e.g.,FIG.4B). In some embodiments, the width w5of the channel layers122is in the range of about 5 nm to about 15 nm along the direction X.

In some embodiments, as shown inFIG.4B, the side surface of each channel layer122exposed by the corresponding trench TR1is substantially coplanar or level with the side surfaces of the adjacent insulating layers112exposed by the corresponding trench TR1. In such a case, a sum of the width w4of the ferroelectric layers120(see, e.g.,FIG.4C) and the width w5of the channel layers122(see, e.g.,FIG.4C) is substantially the same as the depth dl of the recess R. However, the disclosure is not limited thereto. In some alternative embodiments, the side surface of each channel layer122exposed by the corresponding trench TR1is slightly recessed from the side surfaces of the adjacent insulating layers112exposed by the corresponding trench TR1by a non-zero distance. The non-zero distance ranges from about 1 nm to about 5 nm, for example.

Referring toFIG.5A,FIG.5B, andFIG.5C, after forming the channel layers122, dielectric walls124are formed to fill up the trenches TR1. As shown inFIG.5A,FIG.5B, andFIG.5C, the dielectric walls124are in contact with the side surfaces of the insulating layers112exposed by the trenches TR1and the side surfaces of the channel layers122exposed by the trenches TR1. In embodiments where the side surface of each channel layer122exposed by the corresponding trench TR1is substantially coplanar or level with the side surfaces of the adjacent insulating layers112exposed by the corresponding trench TR1, the side surface of the dielectric wall124in contact with the side surfaces of the insulating layers112and the side surface of the channel layer122exposed by the corresponding trench TR1has a substantially smooth profile. In some embodiments, as shown inFIG.5A,FIG.5B, andFIG.5C, each side surface of the dielectric wall124in contact with the side surfaces of the insulating layers112and the side surface of the channel layers122exposed by the corresponding trench TR1is substantially straight. However, the disclosure is not limited thereto. In embodiments where the side surface of each channel layer122exposed by the corresponding trench TR1is slightly recessed from the side surfaces of the adjacent insulating layers112exposed by the corresponding trench TR1, the side surface of the dielectric wall124in contact with the side surfaces of the insulating layers112and the side surface of the channel layers122exposed by the corresponding trench TR1has an uneven profile. In such a case, the dielectric walls124may have laterally protruding portions in contact with the side surfaces of the corresponding channel layers122.

In some embodiments, as shown inFIG.5B, the bottom surfaces of the dielectric walls124are in contact with the top surface of the substrate100exposed by the trenches TR1. However, the disclosure is not limited thereto. In embodiments where the trenches TR1vertically extend through some but not all layers of the multilayer stack110, the bottom surfaces of the dielectric walls124are in contact with the remaining portions of the multilayer stack110.

In some embodiments, the dielectric walls124are formed by the following steps. After forming the channel layers122, a dielectric material is formed to fill the trenches TR1. The dielectric material may include silicon nitride, silicon oxide, silicon oxynitride, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or the like, or a combination thereof, and may be formed by a suitable deposition process, such as a CVD process or an ALD process. After the dielectric material is formed, a planarization process, such as a chemical mechanical planarization (CMP) process, an etching process, or a combination thereof, may be performed to remove portions of the dielectric material outside the trenches TR1. In some embodiments, the portions of the dielectric material removed by the planarization process are over the top surface of the topmost insulating layer112. That is to say, the planarization process exposes the multilayer stack110such that the top surface of the multilayer stack110(e.g., the top surface of the topmost insulating layer112) and the top surfaces of the remaining portions of the dielectric material are substantially coplanar or level with one another after the planarization process is complete. The remaining portions of the dielectric material in the trenches TR1form the dielectric walls124.

As shown in the plan view ofFIG.5C, the dielectric walls124laterally extend along the direction Y, and each of the channel layers122is disposed between the corresponding dielectric wall124and the corresponding ferroelectric layer120. In some embodiments, the dielectric walls124(see, e.g.,FIG.5C) have a height h2substantially the same as the overall height h1of the multilayer stack110(see, e.g.,FIG.5C) along the direction Z. In some embodiments, the height h2of the dielectric walls124is in the range of about 1000 nm to about 10000 nm. In some embodiments, the dielectric walls124(see, e.g.,FIG.5B) have a width w6substantially the same as the width w2of the trenches TR1(see, e.g.,FIG.5B) along the direction X. In some embodiments, the width w6of the dielectric walls124is in the range of about 50 nm to about 200.

Referring toFIG.6A,FIG.6B, andFIG.6C, through holes TH are formed in the dielectric walls124, the insulating layers112, and the channel layers122. In detail, as shown inFIG.6A,FIG.6B, andFIG.6C, each through hole TH penetrates through the corresponding dielectric wall124, the corresponding insulating layers112, and the corresponding channel layers122along the direction Z to expose the substrate100. That is to say, each through hole TH vertically extends through the corresponding dielectric wall124, the corresponding insulating layers112, and the corresponding channel layers122. Further, as shown inFIG.6C, the through holes TH penetrate through the channel layers122to cut off the channel layers122, such that each of the channel layers122is rendered as a discontinuous channel layer. However, the disclosure is not limited thereto. In some alternative embodiments, the through holes TH may penetrate through the channel layers122without cutting off the channel layers122. In such case, each of the channel layers122still is a continuous channel layer. In addition, as shown inFIG.6B, after forming the through holes TH, the side surfaces of the ferroelectric layers120in contact with the channel layers122are exposed by the through holes TH. However, the disclosure is not limited thereto. In embodiments where the through holes TH penetrate through the channel layers122without cutting off the channel layers122, the ferroelectric layers120are not exposed by the through holes TH.

In some embodiments, the through holes TH are laterally separated from one another. As shown inFIG.6A,FIG.6B, andFIG.6C, the through holes TH arranged in the same dielectric wall124are laterally separated from one another by the dielectric wall124, the corresponding insulating layers112, and the corresponding channel layers122. From another point of view, as shown inFIG.6AandFIG.6C, the through holes TH are separately arranged as having multiple columns extending along the direction Y, and two adjacent columns of the through holes TH are spaced apart from each other along the direction X. The through holes TH in the same column are laterally separated from one another by the corresponding dielectric wall124, the corresponding insulating layers112, and the corresponding channel layers122. The through holes TH in one of the adjacent columns of the through holes TH arranged in the same dielectric wall124are laterally separated from the through holes TH in another one of the adjacent columns by the dielectric wall124.

In some embodiments, the through holes TH are formed by using a lithography process and an etching process. A mask pattern, such as patterned photoresist, may be formed over the multilayer stack110. The etching process may then be performed by using the mask pattern as an etching mask to remove portions of the dielectric walls124, the insulating layers112, and the channel layers122so as to form the through holes TH. After the etching process is finished, the mask pattern (e.g., patterned photoresist) may be removed by a suitable removal process, such as ashing or stripping. In some embodiments, the etching process is an anisotropic etching process.

Referring toFIG.7A,FIG.7B, andFIG.7C, conductive pillars126are formed to fill up the through holes TH. In detail, as shown inFIG.7A,FIG.7B, andFIG.7C, each conductive pillar126penetrates through the corresponding dielectric wall124, the corresponding insulating layers112, and the corresponding channel layers122along the direction Z and reaches to the top surface of the substrate100exposed by the corresponding through hole TH. That is to say, each conductive pillar126vertically extends through the corresponding dielectric wall124, the corresponding insulating layers112, and the corresponding channel layers122. In some embodiments, each conductive pillar126is formed to be in lateral contact with one of the corresponding channel layers122through more than one side surfaces. In the illustrated embodiment, as shown inFIG.6C, since the through holes TH cut off the channel layers122to expose the side surfaces of the ferroelectric layers120, two side surfaces of each conductive pillar126filling up the corresponding through hole TH are in lateral contact with one of the corresponding channel layers122. From another point of view, the conductive pillars126filling up the through holes TH are in contact with the side surfaces of the ferroelectric layers120exposed by the corresponding through holes TH. However, the disclosure is not limited thereto. In embodiments where the through holes TH penetrate through the channel layers122without cutting off the channel layers122, portions of each conductive pillar126are embedded in the corresponding channel layers122. In such case, three side surfaces of each conductive pillar126filling up the corresponding through hole TH are in lateral contact with one of the corresponding channel layers122. Although sixteen conductive pillars126are presented inFIG.7Afor illustrative purposes, those skilled in the art can understand that the number of the conductive pillars126may be more than what is depicted inFIG.7A, and may be designated based on demand and/or design layout.

In some embodiments, the conductive pillars126are laterally separated from one another. As shown inFIG.7A,FIG.7B, andFIG.7C, the conductive pillars126arranged in the same dielectric wall124are laterally separated from one another by the dielectric wall124, the corresponding insulating layers112, and the corresponding channel layers122. From another point of view, as shown inFIG.7AandFIG.7C, the conductive pillars126are separately arranged in an array of rows and columns. In detail, the conductive pillars126are separately arranged as having multiple columns extending along the direction Y, and adjacent columns of the conductive pillars126are spaced apart from each other along the direction X. The conductive pillars126in the same column are laterally separated from one another by the corresponding dielectric wall124, the corresponding insulating layers112, and the corresponding channel layers122. The conductive pillars126in one of the adjacent columns of the conductive pillars126arranged in the same dielectric wall124are laterally separated from the conductive pillars126in another one of the adjacent columns by the dielectric wall124.

In some embodiments, the conductive pillars126are formed by the following steps. After forming the through holes TH, a conductive material is formed to fill the through holes TH. The conductive material may include copper, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, ruthenium, aluminum, combinations thereof, or the like, and may be formed by a deposition process (e.g., a CVD process or a physical vapor deposition (PVD) process), a plating process, or a combination thereof. After the conductive material is formed, a planarization process, such as a CMP process, an etching process, or a combination thereof, may be performed to remove portions of the conductive material outside the through holes TH. In some embodiments, the portions of the conductive material removed by the planarization process are over the top surface of the topmost insulating layer112and the top surfaces of the dielectric walls124. That is to say, the planarization process exposes the multilayer stack110and the dielectric walls124, such that the top surface of the multilayer stack110(e.g., the top surface of the topmost insulating layer112), the top surfaces of the dielectric walls124, and the top surfaces of the remaining portions of the conductive material are substantially coplanar or level with one another after the planarization process is complete. The remaining portions of the conductive material in the through holes TH form the conductive pillars126.

After forming the conductive pillars126in contact with the channel layers122, the sacrificial layers114are subsequently replaced with gate layers118by a replacement process, which will be described in details inFIG.8AtoFIG.10A,FIG.8BtoFIG.10B, andFIG.8CtoFIG.10C.

Referring toFIG.8A,FIG.8B, andFIG.8C, trenches TR2are formed in the multilayer stack110. In the illustrated embodiment, the trenches TR2penetrate through the remaining portions of the multilayer stack110rendered after forming the recesses R (as described with reference toFIG.3AandFIG.3B) along the direction Z. To avoid clutter and for ease of discussion, the remaining portions of the multilayer stack110rendered after forming the recesses R are referred to as the remaining portions of the multilayer stack110in the discussion hereinafter. In detail, each of the trenches TR2is formed in one of the remaining portions of the multilayer stack110in a one-to-one relationship. From another point of view, in the illustrated embodiment, each of the trenches TR2vertically extends through all layers (e.g., all of the insulating layers112and all of the sacrificial layers114) of the corresponding remaining portion of the multilayer stack110to expose the substrate100. That is to say, each remaining portion of the multilayer stack110can be regarded as being cut into two half portions by the corresponding trench TR2. However, the disclosure is not limited thereto. In some alternative embodiments, the trenches TR2vertically extend through some but not all layers of the remaining portions of the multilayer stack110. For example, the trenches TR2may extend through all of the sacrificial layers114and expose the bottommost insulating layer112.

As shown in the top view ofFIG.8Aand the plan view ofFIG.8C, the trenches TR2laterally extend along the direction Y and are arranged along the direction X. Further, after forming the trenches TR2, the two half portions of each remaining portion of the multilayer stack110are laterally spaced apart from each other by one of the trenches TR2. In some embodiments, the trenches TR2have a width w7(see, e.g.,FIG.8B) in the range of about 5 nm to about 20 nm along the direction X. That is to say, the two half portions of each remaining portion of the multilayer stack110are laterally spaced apart from each other by the separation distance equal to the width w7of the corresponding trench TR2. In addition, as shown inFIG.8B, the trenches TR2expose the remainder of the sacrificial layers114in each half of the remaining portions of the multilayer stack110.

In some embodiments, the method for forming the trenches TR2includes a lithography process and an etching process (e.g., an anisotropic etching process). Since the substrate100has sufficient etching selectivity with respect to the materials in the multilayer stack110, the substrate100may remain substantially intact during the etching process. In some embodiments where the substrate100is formed of silicon carbide, the insulating layers112are formed of silicon oxide, and the sacrificial layers114are formed of silicon nitride, the trenches TR2are formed by a dry etch using a fluorine-based gas (e.g., C4F6) mixed with hydrogen (e.g., H2) or oxygen (e.g., O2) gas. In some embodiments, the etching process for forming the trenches TR2may be similar to the etching process used to form the trenches TR1described with respect toFIG.2AandFIG.2B.

Referring toFIG.9A,FIG.9B, andFIG.9C, the remainder of the sacrificial layers114are selectively removed to form gaps G between the insulating layers112. By removing the remainder of the sacrificial layers114via the trenches TR2, the surfaces of the insulating layers112and the ferroelectric layers120previously in contact with the sacrificial layers114are currently exposed by the gaps G. In addition, since the ferroelectric layers120, the dielectric walls124, and the conductive pillars126are connected to the insulating layers112, the ferroelectric layers120, the dielectric walls124, and the conductive pillars126can provide support for the insulating layers112and prevent the insulating layers112from collapse after removal of the remainder of the sacrificial layers114. In some embodiments, the method for removing the remainder of the sacrificial layers114includes an isotropic etching process. Since the substrate100, the insulating layers112, and the ferroelectric layers120may have sufficient etching selectivity with respect to the sacrificial layers114, the sacrificial layers114can be selectively removed during such isotropic etching process.

Referring toFIG.10A,FIG.10B, andFIG.10C, gate layers118are formed into the gaps G previously occupied by the sacrificial layers114. In other words, the previously existing sacrificial layers114in each half of the remaining portions of the multilayer stack110are replaced by the gate layers118. After forming the gate layers118, stacking structures ST each including the insulating layers112and the gate layers118alternately stacked on the substrate100are formed. That is to say, after performing the replacement process on the remaining portions of the multilayer stack110as described with respect toFIG.8AtoFIG.10A,FIG.8BtoFIG.10B, andFIG.8CtoFIG.10C, the remaining portions of the multilayer stack110turn into the stacking structures ST. In detail, as shown inFIG.8BandFIG.10B, after performing the replacement process, each remaining portion of the multilayer stack110turns into two stacking structures ST. Since the sacrificial layer114, the corresponding ferroelectric layers120, and the corresponding channel layers122are at substantially the same level in each remaining portion of the multilayer stack110as described with reference toFIG.4A,FIG.4B, andFIG.4C, the gate layer118taking the place of the sacrificial layer114in the stacking structure ST is at substantially the same level with the corresponding ferroelectric layers120and the corresponding channel layers122.

In some embodiments, the stacking structures ST are laterally spaced apart from one another. In detail, as shown inFIG.10A,FIG.10B, andFIG.10C, two adjacent stacking structures ST at opposite sides of one of the trenches TR2are laterally spaced apart from each other by the one of the trenches TR2. In some embodiments, the two adjacent stacking structures ST at opposite sides of one of the trenches TR2are laterally spaced apart from each other by the separation distance equal to the width w7of the trench TR2described with respect toFIG.8A,FIG.8B, andFIG.8C. Further, as shown inFIG.10A,FIG.10B, andFIG.10C, two adjacent stacking structures ST at opposite sides of one of the dielectric walls124are laterally spaced apart from each other by the one of the dielectric walls124, the corresponding ferroelectric layers120, the corresponding channel layers122, and the corresponding conductive pillars126. As shown in the top view ofFIG.10Aand the plan view ofFIG.10C, the stacking structures ST laterally extend along the direction Y and are arranged along the direction X. In some embodiments, the gate layers118have a thickness t5(see, e.g.,FIG.10B) substantially the same as the thickness t3of the ferroelectric layers120along the direction Z. In some embodiments, the thickness t5of the gate layers118is in the range of about 15 nm to about 90 nm. In some embodiments, along the direction X, the gate layers118have a width w8(see, e.g.,FIG.10C) in the range of about 10 nm to about 50 nm.

In some embodiments, each of the gate layers118is formed within one of the gaps G in a one-to-one relationship. As shown inFIG.10BandFIG.10C, the gate layer118is formed to cover or contact the side surface of the ferroelectric layer120exposed by the corresponding gap G. In some embodiments, the side surfaces of the gate layers118exposed by the trenches TR2are substantially coplanar or level with the side surfaces of the adjacent insulating layers112exposed by the trenches TR2, as shown inFIG.10B. However, the disclosure is not limited thereto. In some alternative embodiments, the side surface of each gate layer118exposed by the corresponding trench TR2is slightly recessed from the side surfaces of the adjacent insulating layers112exposed by the corresponding trench TR2by a non-zero distance. The non-zero distance ranges from about 1 nm to about 5 nm, for example.

In some embodiments, the gate layers118are formed by the following steps. First, a gate material is formed over the substrate100to fill up the trenches TR2and the gaps G between the insulating layers112. In some embodiments, the gate material not only fills the gaps G and the trenches TR2, but also further covers the top surfaces of the topmost insulating layers112in the stacking structures ST, the top surfaces of the conductive pillars126, and the top surfaces of the dielectric walls124. In some embodiments, the method for forming the gate material includes a deposition process, such as a CVD process or an ALD process. The gate material may include copper, tungsten, cobalt, aluminum, tungsten nitride, rhuthenium, silver, gold, rhodium, molybdenum, nickel, cadmium, zinc, alloys thereof, combinations thereof, or the like. Thereafter, the portions of the gate material not covered by the insulating layers112in the stacking structures ST are removed by an etching process, such as an anisotropic etching process. The remaining portions of the conductive material form the gate layers118. In other words, the insulating layers112in the stacking structures ST may function as shadow masks during the etching process and the patterning of the conductive material can be considered as a self-aligned process. In some alternative embodiments, barrier layers may be formed between the gate layers118and the adjacent insulating layers112, so as to prevent the metal elements of the gate layers118from diffusing to the adjacent insulating layers112. The barrier layers may also provide the function of increasing the adhesion between the gate layers118and the adjacent insulating layers112and may be referred to as glue layers in some examples. The barrier layers may include a metal nitride, such as titanium nitride, tantalum nitride, molybdenum nitride, zirconium nitride, or hafnium nitride. In some other embodiments, the barrier layers and the gate layers118have different conductive materials. For example, the gate layers118are made of tungsten, and the barrier layers are made of titanium nitride.

Referring toFIG.11A,FIG.11B, andFIG.11C, dielectric walls128are formed to fill up the trenches TR2. As shown inFIG.11A,FIG.11B, andFIG.11C, the dielectric walls128are in contact with the side surfaces of the insulating layers112exposed by the trenches TR2and the side surfaces of the gate layers118exposed by the trenches TR2. In embodiments where the side surface of each gate layer118exposed by the corresponding trench TR2is substantially coplanar or level with the side surfaces of the adjacent insulating layers112exposed by the corresponding trench TR2, the side surface of the dielectric wall128in contact with the side surfaces of the insulating layers112and the side surface of the gate layer118exposed by the corresponding trench TR1has a substantially smooth profile. In some embodiments, as shown inFIG.11A,FIG.11B, andFIG.11C, the side surface of the dielectric wall128in contact with the side surfaces of the insulating layers112and the side surface of the gate layer118exposed by the corresponding trench TR2is substantially straight. However, the disclosure is not limited thereto. In embodiments where the side surface of each gate layer118exposed by the corresponding trench TR2is slightly recessed from the side surfaces of the adjacent insulating layers112exposed by the corresponding trench TR2, the side surface of the dielectric wall128in contact with the side surfaces of the insulating layers112and the side surface of the gate layers118exposed by the corresponding trench TR2has an uneven profile. In such case, the dielectric walls128may have laterally protruding portions in contact with the side surfaces of the corresponding gate layers118. In some embodiments, as shown inFIG.11B, the bottom surfaces of the dielectric walls128are in contact with the top surface portion of the substrate100exposed by the trenches TR2. However, the disclosure is not limited thereto. In some alternative embodiments, the bottom surfaces of the dielectric walls128are not in contact with the top surface portion of the substrate100exposed by the trenches TR2. For example, the bottom surfaces of the dielectric walls128may in contact with the bottommost insulating layer112.

In some embodiments, the dielectric walls128are formed by the following steps. A dielectric material is formed to fill the trenches TR2. The dielectric material may include silicon nitride, silicon oxide, silicon oxynitride, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or the like, or a combination thereof, and may be formed by a suitable deposition process, such as a CVD process or an ALD process. After the dielectric material is formed, a planarization process, such as a chemical mechanical planarization (CMP) process, an etching process, or a combination thereof, may be performed to remove portions of the dielectric material outside the trenches TR2. In some embodiments, the portions of the dielectric material removed by the planarization process are over the top surfaces of the topmost insulating layers112in the stacking structures ST. That is to say, the planarization process exposes the stacking structures ST, such that the top surfaces of the stacking structures ST (e.g., the top surfaces of the topmost insulating layers112) and the top surfaces of the remaining portions of the dielectric material are substantially coplanar or level with one another after the planarization process is complete. The remaining portions of the dielectric material in the trenches TR2form the dielectric walls128.

As shown in the plan view ofFIG.11C, the dielectric walls128laterally extend along the direction Y. In addition, as shown in the plan view ofFIG.11C, each of the dielectric walls128is disposed between two adjacent stacking structures ST. That is to say, two adjacent stacking structures ST at opposite sides of one of the dielectric walls128are laterally separated from each other by the one of the dielectric walls128. In some embodiments, along the direction X, the dielectric walls128have a width w9(see, e.g.,FIG.11B) substantially the same as the width w7of the trench TR2(see, e.g.,FIG.8B) described with respect toFIG.8AtoFIG.8C. In some embodiments, the width w9of the dielectric walls128is in the range of about 5 nm to about 20 nm.

Up to here, the three-dimensional memory device10according to some embodiments of the present disclosure has been formed. Referring toFIG.11A,FIG.11B, andFIG.11C, the three-dimensional memory device10includes the stacking structures ST laterally spaced apart from one another, wherein each of the stacking structures ST includes the insulating layers112and the gate layers118alternately stacked on the substrate100. In detail, the stacking structures ST are laterally spaced apart from one another by dielectric walls (e.g., the dielectric walls124and the dielectric walls128). Further, the three-dimensional memory device10also includes the ferroelectric layers120between two adjacent insulating layers112in each of the stacking structures ST, the channel layers122between two adjacent insulating layers112in each of the stacking structures ST, and the conductive pillars126vertically penetrate through the dielectric walls124, laterally separated from one another and in contact with the channel layers122in each of the stacking structures ST. As shown inFIG.11BandFIG.11C, one of the gate layers118in each stacking structure ST is at substantially the same level with one of the ferroelectric layers120and one of the channel layers122. That is to say, in each stacking structure ST, one gate layer118, one ferroelectric layer120, and one channel layer122are together sandwiched between the same underlying insulating layer112and the same overlying insulating layer112. As such, the gate layer118, the ferroelectric layer120, and the channel layer122at substantially the same level can be collectively referred to as a stacking layer of the stacking structure ST. In view of this, the stacking structure ST can be regarded as including stacking layers (each including one gate layer118, one ferroelectric layer120and one channel layer122) and insulating layers112alternately stacked on the substrate100.

As shown inFIG.11C, in each of the stacking structures ST, a portion of the gate layer118, portions of the ferroelectric layer120and the channel layer122that are in the same stacking layer as the gate layer118and that are laterally adjacent to the portion of the gate layer118, and portions of the two adjacent conductive pillars126laterally adjacent to the portion of the gate layer118constitute a field effect transistor (FET), which is functioned as a memory cell MC. That is to say, the memory cell MC can be regarded as including a pair of the conductive pillars126, one channel layer122, one ferroelectric layer120, and one gate layer118. In one memory cell MC, one of the pair of the conductive pillars126is functioned as a source terminal of the memory cell MC and another one of the pair of the conductive pillars126is functioned as a drain terminal of the memory cell MC. Dipole moments in opposite directions can be stored in the ferroelectric layer120. Accordingly, the FET has different threshold voltages corresponding to the dipole moments. Thus, the FET can be identified as having different logic states. In these embodiments, the memory cell MC is a ferroelectric FET.

Further, as shown inFIG.11BandFIG.11C, the stacking layers (each including one gate layer118, one ferroelectric layer120, and one channel layer122) stacked along the direction Z (e.g., the vertical direction) in each stacking structure ST, as well as portions of pairs of conductive pillars126aside the stacking layers, form a stack of memory cells MC. In addition, as shown inFIG.11A,FIG.11B, andFIG.11C, multiple stacks of the memory cells MC are arranged along the direction X (e.g., the horizontal direction) and the direction Y (e.g., the horizontal direction). That is to say, the multiple stacks of the memory cells MC are separately arranged in an array of rows and columns. In detail, the multiple stacks of the memory cells MC are separately arranged as having multiple columns extending along the direction Y and multiple rows extending along the direction X.

As shown inFIG.11BandFIG.11C, each of the channel layers122is shared by the corresponding column of memory cells MC along the direction Y, and thus conductive channels of these memory cells MC are formed in different sections of the channel layer122. In addition, as shown inFIG.11BandFIG.11C, laterally adjacent memory cells MC at opposite sides of one of the dielectric walls128are separated from each other by the one of the dielectric walls128. That is to say, the gate layers118of the laterally adjacent memory cells MC at opposite sides of one of the dielectric walls128are physically and electrically separate from each other. In other words, the laterally adjacent memory cells MC at opposite sides of one of the dielectric walls128include two separate, independent gate layers118. Consequently, in the three-dimensional memory device10, the disturbance between the laterally adjacent memory cells at opposite sides of one of the dielectric walls128can be effectively prevented. Further, as shown inFIG.11BandFIG.11C, laterally adjacent memory cells MC at opposite sides of one of the dielectric walls124are separated from each other by the one of the dielectric walls124. That is to say, the pairs of conductive pillars126in the laterally adjacent memory cells MC at opposite sides of one of the dielectric walls124are physically and electrically separate from each other. In other words, the laterally adjacent memory cells MC at opposite sides of one of the dielectric walls124respectively have their own pairs of source and drain terminals. Consequently, in the three-dimensional memory device10, the disturbance between the laterally adjacent memory cells at opposite sides of one of the dielectric walls124can be effectively prevented.

In addition, although not shown, the three-dimensional memory device10further includes bit lines and source lines electrically connected to the conductive pillars126. The pair of conductive pillars126in each stack of memory cells MC are connected to one of the bit lines and one of the source lines, respectively. In some embodiments, the bit lines and the source lines extend along the direction X. In some embodiments, the conductive pillars126in adjacent stacks of memory cells MC may be connected to different bit lines and different source lines. Accordingly, the memory cells MC in adjacent stacks of memory cells MC can be controlled by different bit lines and different source lines, whereby disturbance between the memory cells MC in adjacent stacks of memory cells MC can be reduced. In embodiments where the conductive pillars126in adjacent stacks of memory cells MC are connected to different bit lines and different source lines, the bit lines and the source lines are disposed at opposite sides of the substrate100. For example, the source lines extend below the substrate100, while the bit lines extend above the stacking structures ST. As another example, the source lines extend above the stacking structures ST, while the bit lines extend below the substrate100. However, the disclosure is not limited thereto. In some alternative embodiments, the bit lines and the source lines may be disposed at the same side of the substrate100. In such a case, the bit lines and the source lines are alternately arranged along the direction Y, wherein each of the bit lines is electrically connected to the conductive pillars126in the same row, and each of the source lines is electrically connected to the conductive pillars126in the same row, and each of the bit lines and each of the source lines are perpendicular to the stacking structures ST.

Although the steps of the method are illustrated and described as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events are not to be interpreted in a limiting sense. In addition, not all illustrated process or steps are required to implement one or more embodiments of the present disclosure.

FIG.12is an equivalent circuit diagram of the three-dimensional memory device shown inFIG.11A,FIG.11BandFIG.11C.

Referring toFIG.11B,FIG.11C, andFIG.12, the gate layers118in each stacking structure ST shown inFIG.11BandFIG.11Cfunction as word lines WL as shown inFIG.12. Each word line WL connects gate terminals G of the corresponding column of memory cells MC along the direction Y. In addition, each pair of conductive pillars126in one of the memory cells MC shown inFIG.11BandFIG.11Cseparately connect to source and drain terminals S, D of the memory cells MC stacked along the direction Z as shown inFIG.12. As shown inFIG.12, the gate terminals G of each stack of the memory cells MC are respectively connected to one of the word lines WL. Further, as shown inFIG.12, the gate terminals G of the adjacent stacks of the memory cells MC are respectively connected to different word lines WL. In addition, the source terminals S of each stack of the memory cells MC are connected together by one of the corresponding pair of the conductive pillars126, and the drain terminals D of each stack of the memory cells MC are connected together by another one of the corresponding pair of the conductive pillars126. In other words, channels CH between the source and drain terminals S, D of each stack of the memory cells MC are connected in parallel. Accordingly, each stack of the memory cells MC may be regarded as being connected by a NOR-flash configuration, and the three-dimensional memory device10may be referred as a three-dimensional NOR memory device.

FIG.13is a schematic cross-sectional view illustrating a semiconductor structure20in accordance with some embodiments of the disclosure.

Referring toFIGS.11A-11CandFIG.13, the semiconductor structure20shown inFIG.13includes the three-dimensional memory device10as described with reference toFIGS.11A-11C. In those embodiments where the substrate100of the three-dimensional memory device10is an etching stop layer, a CMOS integrated circuit LC may lie under the substrate100, and the CMOS integrated circuit LC may also be referred as a CMOS-under-array (CUA). Although not shown, the gate layers118and the conductive pillars126may be routed to the CMOS integrated circuit LC, and the three-dimensional memory device10may be controlled by the CMOS integrated circuit LC.

In some embodiments, the CMOS integrated circuit LC is built on a semiconductor substrate200. The semiconductor substrate200may be a semiconductor wafer or a semiconductor-on-insulator (SOI) wafer. The CMOS integrated circuit LC may include active devices formed on a surface region of the semiconductor substrate200. In some embodiments, the active devices include metal-oxide-semiconductor (MOS) transistors202. The MOS transistors202may respectively include a gate structure204formed over the semiconductor substrate200. In some embodiments, the gate structure204includes a gate electrode206, a gate dielectric layer208, and a gate spacer210. The gate dielectric layer208may spread between the gate electrode206and the semiconductor substrate200, and may or may not further cover a sidewall of the gate electrode206. The gate spacer210may laterally surround the gate electrode206and the gate dielectric layer208. Further, the MOS transistor202may further include source/drain regions212. The source/drain regions212may be formed in the semiconductor substrate200, and are located at opposite sides of the gate structure204. In some embodiments, the source/drain regions212may be epitaxial structures, and may protrude from a surface of the semiconductor substrate200. It should be noted that, although the MOS transistors202are depicted as planar-type MOS transistors that forms conductive channels (not shown) along the surface of the semiconductor substrate200, the MOS transistors202may alternatively be fin-type MOS transistors (or referred as finFET), gate-all-around (GAA) FETs, or the like.

In some embodiments, the CMOS integrated circuit LC further includes dielectric layers214stacked on the semiconductor substrate200and includes contact plugs216and interconnections218formed in the stack of dielectric layers214. A bottommost dielectric layer214may laterally surround the gate structures204and cover the source/drain regions212. Some of the contact plugs216may penetrate through the bottommost one of the dielectric layers214, in order to establish electrical connection with the source/drain regions212, while others of the contact plugs216may stand on the gate structures204and electrically connect to the gate electrodes206of the gate structures204. The interconnections218may spread on the contact plugs216and are electrically connected to the contact plugs216. The interconnections218may include conductive traces and conductive vias. The conductive traces respectively lie on one of the dielectric layers214, whereas the conductive vias respectively penetrate through one or more of the dielectric layers214and electrically connect to one or more of the conductive traces.

In some embodiments, the three-dimensional memory device10is disposed on the stack of dielectric layers214. In these embodiments, the gate layers118and the conductive pillars126of the three-dimensional memory device10may be routed to the interconnections218in the stack of dielectric layers214by conductive paths (not shown) extending through the substrate100and the topmost one of the dielectric layers214. For instance, the gate layers118(or referred to as word lines) may be routed to word line drivers formed by some of the active devices interconnected by a portion of the interconnections218, and the conductive pillars126may be routed to sense amplifiers formed by others of the active devices interconnected by another portion of the interconnections218.

FIG.14is a schematic plan view of a three-dimensional memory device30in accordance with some alternative embodiments of the present disclosure. The three-dimensional memory device30illustrated inFIG.14is similar to the three-dimensional memory device10illustrated inFIG.11C. Hence, the same reference numerals are used to refer to the same or like parts, and its detailed description will be omitted herein. The differences between the three-dimensional memory device30illustrated inFIG.14and the three-dimensional memory device10illustrated inFIG.11Cwill be described below.

Referring toFIG.14, the three-dimensional memory device30further includes insulators300penetrating through the dielectric walls124, the insulating layers112and the channel layers122along the direction Z. In detail, each insulator300vertically extends through the corresponding dielectric wall124, the corresponding insulating layers112, and the corresponding channel layers122. As shown inFIG.14, each insulator300laterally extends to cut off two adjacent channel layers122at opposite sides of the corresponding dielectric wall124along the direction X. That is to say, the insulator300laterally extends between two adjacent stacking structures ST at opposite sides of the corresponding dielectric wall124along the direction X. Further, as shown inFIG.14, the insulator300is formed between the laterally adjacent memory cells MC in the column of memory cells MC along the direction Y. In view of this, the channel layers122of the laterally adjacent memory cells MC in each column of memory cells MC along the direction Y are separated from each other by the one of the insulators300. That is to say, the channel layers122of the laterally adjacent memory cells MC in each column of memory cells MC along the direction Y are physically and electrically separate from each other. In other words, the laterally adjacent memory cells MC in each column of memory cells MC along the direction Y include two separate, independent channel layers122. Consequently, in the three-dimensional memory device30, the disturbance between the laterally adjacent memory cells in each column of memory cells MC along the direction Y can be effectively prevented. From another point of view, as shown inFIG.14, the pair of the conductive pillars126in each memory cell MC is disposed between two adjacent insulators300along the direction Y. Further, since the insulator300laterally extends between two adjacent columns of the memory cells MC at opposite sides of the corresponding dielectric wall124along the direction X, two pairs of the conductive pillars126in two adjacent memory cells MC at opposite sides of one of the dielectric walls124are disposed between the same two adjacent insulators300along the direction Y. Although nine insulators300are presented inFIG.14for illustrative purposes, those skilled in the art can understand that the number of the insulators300may be more than what is depicted inFIG.14and may be designated based on demand and/or design layout.

In the illustrated embodiment, the insulators300do not laterally extend through the ferroelectric layers120along the direction X. Different sections of the ferroelectric layer120may be independently polarized, and thus the ferroelectric layer120can function to store values even when adjacent sections of the ferroelectric layer120corresponding to the laterally adjacent memory cells MC in each column of memory cells MC along the direction Y are not physically and electrically separated. However, the disclosure is not limited thereto. In some alternative embodiments, each insulator300further laterally extends to cut off the ferroelectric layers120at opposite sides of the corresponding dielectric wall124along the direction X.

In some embodiments, the insulators300are laterally separated from one another. As shown inFIG.14, the insulators300are separately arranged as having multiple columns extending along the direction Y, and adjacent columns of the insulators300are spaced apart from each other along the direction X. In the illustrated embodiment, the insulators300are laterally separated from the conductive pillars126. However, the disclosure is not limited thereto. In some alternative embodiments, the insulators300may contact the conductive pillars126.

In some embodiments, the method for forming the insulators300includes the following steps. First, after the conductive pillars126are formed as described with reference toFIG.7A,FIG.7B, andFIG.7C, trenches penetrating through the dielectric walls124, the insulating layers112, and the channel layers122along the direction Z are formed by using a lithography process and an etching process. A mask pattern, such as patterned photoresist, may be formed over the multilayer stack110. The etching process may then be performed by using the mask pattern as an etching mask to remove portions of the dielectric walls124, the insulating layers112, and the channel layers122so as to form the trenches. After the etching process is finished, the mask pattern (e.g., patterned photoresist) may be removed by a suitable removal process, such as ashing or stripping. In some embodiments, the etching process is an anisotropic etching process. Next, a dielectric material is formed to fill the trenches. The dielectric material may include silicon oxide, silicon nitride, silicon oxynitride, tetraethylorthosilicate (TEOS) oxide, un-doped silicate glass, borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), low-k dielectric material, other suitable dielectric material, or combinations thereof. Exemplary low-k dielectric materials include FSG, carbon doped silicon oxide, Black Diamond® (Applied Materials of Santa Clara, Calif.), Xerogel, Aerogel, amorphous fluorinated carbon, Parylene, benzocyclobutene (BCB), SiLK™ (Dow Chemical, Midland, Mich.), polyimide, other low-k dielectric material, or combinations thereof. Herein, the low-k dielectric material used in the insulators300between adjacent memory cells MC is able to decrease the crosstalk or the coupling interference between the adjacent memory cells MC, thereby increasing the performance and the reliability of the three-dimensional memory device30. The dielectric material may be formed by a suitable deposition process, such as a CVD process or an ALD process. After the dielectric material is formed, a planarization process, such as a CMP process, an etching process, or a combination thereof, may be performed to remove portions of the dielectric material outside the trenches. In some embodiments, the portions of the dielectric material removed by the planarization process are over the top surface of the topmost insulating layer112, the top surfaces of the dielectric walls124, and the top surfaces of the conductive pillars126. That is to say, the planarization process exposes the multilayer stack110, the dielectric walls124, and the conductive pillars126, such that the top surface of the multilayer stack110(e.g., the top surface of the topmost insulating layer112), the top surfaces of the dielectric walls124, the top surfaces of the conductive pillars126, and the top surfaces of the remaining portions of the dielectric material are substantially coplanar or level with one another after the planarization process is complete. The remaining portions of the dielectric material in the trenches form the insulators300. However, the disclosure is not limited thereto. In some alternative embodiments, the step for forming the insulators300may precede the step for forming the conductive pillars126.

FIG.15is a schematic plan view of a three-dimensional memory device in accordance with some alternative embodiments of the present disclosure. The three-dimensional memory device40illustrated inFIG.15is similar to the three-dimensional memory device10illustrated inFIG.11C. Hence, the same reference numerals are used to refer to the same or liked parts and its detailed description will be omitted herein. The differences between the three-dimensional memory device40illustrated inFIG.15and the three-dimensional memory device10illustrated inFIG.11Cwill be described below.

Referring toFIG.15, in the three-dimensional memory device40, the conductive pillars126penetrate through the dielectric walls124along the direction Z without penetrating through the channel layers122. That is to say, in each memory cell MC, the conductive pillars126are laterally separated from the corresponding ferroelectric layer120by the corresponding channel layers122. From another point of view, as shown inFIG.15, each conductive pillar126is formed to be in lateral contact with one of the corresponding channel layers122through one side surface. In addition, as shown inFIG.15, the conductive pillars126arranged in the same dielectric wall124are laterally separated from one another by the dielectric wall124. Further, although not shown, the three-dimensional memory device40may further include insulators between the laterally adjacent memory cells MC along the direction Y as described with reference toFIG.14.

In the aforesaid embodiments with respect toFIGS.1-15, the conductive pillars126in the same row of the array are all aligned with one another. However, the disclosure is not limited thereto. In some alternative embodiments, the conductive pillars126may be arranged in a staggered configuration. Hereinafter, other configurations of the three-dimensional memory device will be discussed in conjunction withFIG.16.

FIG.16is a schematic plan view of a three-dimensional memory device in accordance with some alternative embodiments of the present disclosure. The three-dimensional memory device50illustrated inFIG.16is similar to the three-dimensional memory device10illustrated inFIG.11C. Hence, the same reference numerals are used to refer to the same or liked parts and its detailed description will be omitted herein. The differences between the three-dimensional memory device50illustrated inFIG.16and the three-dimensional memory device10illustrated inFIG.11Cwill be described below.

Referring toFIG.16, in three-dimensional memory device50, the conductive pillars126are formed in a staggered configuration. In detail, the columns of the conductive pillars126are alternately offset from others along the same direction (e.g., the direction Y). For instance, even columns of the conductive pillars126are offset from odd columns of the conductive pillars126along the direction Y. In some embodiments, as shown inFIG.16, the columns of the conductive pillars126are alternately offset from others along the direction Y by substantially identical offset amount. In addition, although not shown, the three-dimensional memory device50further includes bit lines and source lines electrically connected to the conductive pillars126. In embodiments where columns of the conductive pillars126are alternately offset from others, the conductive pillars126in adjacent stacks of memory cells MC may be connected to different bit lines and different source lines. In some embodiments, the source lines and the bit lines all extend above the stacking structures ST. However, the disclosure is not limited thereto. In some alternative embodiments, the bit lines and the source lines are disposed at opposite sides of the substrate100. Further, although not shown, the three-dimensional memory device50may further include insulators between the laterally adjacent memory cells MC along the direction Y as described with reference toFIG.14.

In accordance with an embodiment, a three-dimensional memory device includes: a first stacking structure including first stacking layers stacked along a vertical direction, wherein each of the first stacking layers includes a first gate layer, a first ferroelectric layer, and a first channel layer, wherein the first gate layer, the first ferroelectric layer, and the first channel layer respectively extend along a horizontal direction perpendicular to the vertical direction, and wherein the first ferroelectric layer is disposed between the first gate layer and the first channel layer; a second stacking structure laterally spaced apart from the first stacking structure and including second stacking layers stacked along the vertical direction, wherein each of the second stacking layers includes a second gate layer, a second ferroelectric layer, and a second channel layer, wherein the second gate layer, the second ferroelectric layer, and the second channel layer respectively extend along the horizontal direction, the second ferroelectric layer is disposed between the second gate layer and the second channel layer, and the first gate layer and the second gate layer are disposed between the first ferroelectric layer and the second ferroelectric layer; first conductive pillars extending along the vertical direction, laterally separated from one another, and in contact with the first channel layer of each of the first stacking layers; and second conductive pillars extending along the vertical direction, laterally separated from one another, and in contact with the second channel layer of each of the second stacking layers. In some embodiments, the first conductive pillars penetrate through the first channel layer of each of the first stacking layers along the vertical direction, wherein the second conductive pillars penetrate through the second channel layer of each of the second stacking layers along the vertical direction. In some embodiments, the first conductive pillars are in contact with the first ferroelectric layer of each of the first stacking layers, wherein the second conductive pillars are in contact with the second ferroelectric layer of each of the second stacking layers. In some embodiments, the first conductive pillars are laterally separated from one another by the first channel layer of each of the first stacking layers, wherein the second conductive pillars are laterally separated from one another by the second channel layer of each of the second stacking layers. In some embodiments, the first conductive pillars are laterally separated from the first ferroelectric layer of each of the first stacking layers by the first channel layer of each of the first stacking layers, wherein the second conductive pillars are laterally separated from the second ferroelectric layer of each of the second stacking layers by the second channel layer of each of the second stacking layers. In some embodiments, the three-dimensional memory device further includes: first insulators penetrating through the first channel layer of each of the first stacking layers along the vertical direction and laterally separated from one another; and second insulators penetrating through the second channel layer of each of the second stacking layers along the vertical direction and laterally separated from one another. In some embodiments, two of the first conductive pillars are disposed between two adjacent first insulators, wherein two of the second conductive pillars are disposed between two adjacent second insulators. In some embodiments, the three-dimensional memory device further includes a dielectric wall disposed between the first stacking structure and the second stacking structure, wherein the dielectric wall is disposed between the first gate layer of each of the first stacking layers and the second gate layer of each of the second stacking layers.

In accordance with an embodiment, a three-dimensional memory device includes: a first stacking structure and a second stacking structure disposed on a substrate and laterally spaced apart from each other, wherein the first stacking structure includes first insulating layers and first gate layers alternately stacked on the substrate, and wherein the second stacking structure includes second insulating layers and second gate layers alternately stacked on the substrate; a dielectric wall disposed on the substrate and between the first stacking structure and the second stacking structure; first ferroelectric layers disposed between the dielectric wall and the first gate layers, wherein each of the first ferroelectric layers is disposed between two adjacent first insulating layers; first channel layers disposed between the dielectric wall and the first ferroelectric layers, wherein each of the first channel layers is disposed between two adjacent first insulating layers; second ferroelectric layers disposed between the dielectric wall and the second gate layers, wherein each of the second ferroelectric layers is disposed between two adjacent second insulating layers; second channel layers disposed between the dielectric wall and the second ferroelectric layers, wherein each of the second channel layers is disposed between two adjacent second insulating layers; first conductive pillars penetrating through the dielectric wall, laterally separated from one another, and in contact with the first channel layers; and second conductive pillars penetrating through the dielectric wall, laterally separated from one another, and in contact with the second channel layers. In some embodiments, the dielectric wall is in contact with side surfaces of the first insulating layers, side surfaces of the second insulating layers, side surfaces of the first channel layers, and side surfaces of the second channel layers. In some embodiments, side surfaces of the first gate layers are laterally recessed from the side surfaces of the first insulating layers, and the first ferroelectric layers are respectively in contact with the side surfaces of the first gate layers; and side surfaces of the second gate layers are laterally recessed from the side surfaces of the second insulating layers, and the second ferroelectric layers are respectively in contact with the side surfaces of the second gate layers. In some embodiments, each of the first gate layers, each of the second gate layers, each of the first ferroelectric layers, each of the first channel layers, each of the second ferroelectric layers, and each of the second channel layers laterally extend over the substrate along a first direction, and wherein the dielectric wall, each of the first conductive pillars, and each of the second conductive pillars vertically extend along a second direction perpendicular to the first direction. In some embodiments, the first conductive pillars penetrate through the dielectric wall and the first channel layers along the second direction, wherein the second conductive pillars penetrate through the dielectric wall and the second channel layers along the second direction. In some embodiments, the first conductive pillars penetrate through the dielectric wall along the second direction without penetrating through the first channel layers, wherein the second conductive pillars penetrate through the dielectric wall along the second direction without penetrating through the second channel layers. In some embodiments, the three-dimensional memory device further includes insulators disposed on the substrate, penetrating through the dielectric wall, the first channel layers, and the second channel layers along the second direction, and laterally extending between the first stacking structure and the second stacking structure along a third direction perpendicular to the first direction and the second direction. In some embodiments, two of the first conductive pillars and two of the second conductive pillars are disposed between two adjacent insulators along the first direction.

In accordance with an embodiment, a method includes: forming a multilayer stack on a substrate, wherein the multilayer stack includes insulating layers and sacrificial layers alternately stacked on the substrate; forming a trench vertically penetrating through the multilayer stack; removing portions of the sacrificial layers exposed by the trench to form recesses, wherein each of the recesses is formed between two adjacent insulating layers; forming ferroelectric layers in the recesses to cover side surfaces of remaining portions of the sacrificial layers exposed by the recesses; forming channel layers in the recesses to be in contact with the ferroelectric layers; filling up the trench with a dielectric material to form a dielectric wall; forming conductive pillars vertically penetrating through the dielectric wall; and replacing remaining portions of the sacrificial layers by gate layers. In some embodiments, the insulating layers and the sacrificial layers include materials with different etching selectivities. In some embodiments, the method further includes forming insulators vertically penetrating through the dielectric wall and the channel layers. In some embodiments, the replacing of the remaining portions of the sacrificial layers by the gate layers includes: forming trenches vertically penetrating through the multilayer stack; removing the remaining portions of the sacrificial layers via the trenches to form gaps, wherein each of the gaps is formed between two adjacent insulating layers; and forming the gate layers in the gaps.