SYNCHRONIZATION OF INPUT SURFACE DATA AND DISPLAY SCREEN REFRESH

An aspect provides a method, including: providing an indication of display screen refresh timing derived from a display system; associating, using the indication of the display screen refresh timing, a set of input data derived from an input surface with a display screen refresh interval; and synchronizing, using one or more processors, the set of input data derived from the input surface with a refresh of a display screen. Other aspects are described and claimed.

BACKGROUND

Information handling devices (“devices”), for example cell phones, smart phones, tablet devices, laptop and desktop computers, televisions, alarm clocks, navigation systems, e-readers, etc., employ one or more input devices. Among these input devices are input surfaces such as a touch sensitive input surface, for example touch screens, digitizers and touch pads.

Input surfaces such as digitizers and touch screens continually record the location of a stylus pointer or finger (relative to the input surface). This location information may be reported to the system, e.g., typically the operating system (OS) uses this location information to render some visual effect based on the location information. Any lags or inconsistency of motion (between the input provided by the user and the interpretation and rendering thereof by the OS) breaks the illusion of responsiveness. Such inconsistencies may cause the user to try to compensate (e.g., by modifying the input provided) or simply frustrate the user.

Sensing, interpreting and rendering within one display screen refresh period creates a beneficial user experience. Achieving all these actions in one screen refresh period is challenging, however, e.g., because screen refresh periods are short (on the order of 17 ms for a liquid crystal display (LCD)). In conventional systems it is not uncommon to have on-screen response to inputs lag by several frames (refresh periods).

BRIEF SUMMARY

In summary, one aspect provides a method, comprising: providing an indication of display screen refresh timing derived from a display system; associating, using the indication of the display screen refresh timing, a set of input data derived from an input surface with a display screen refresh interval; and synchronizing, using one or more processors, the set of input data derived from the input surface with a refresh of a display screen.

Another aspect provides an information handling device, comprising: an input surface; a display system; one or more processors; a memory device assessable to the one or more processors and storing code executable by the one or more processors to: provide an indication of display screen refresh timing derived from a display system; associate, using the indication of the display screen refresh timing, a set of input data derived from an input surface with a display screen refresh interval; and synchronize, using one or more processors, the set of input data derived from the input surface with a refresh of a display screen.

A further aspect provides a program product, comprising: a storage device having computer readable program code stored therewith, the computer readable program code comprising: computer readable program code configured to provide an indication of display screen refresh timing derived from a display system; computer readable program code configured to associate, using the indication of the display screen refresh timing, a set of input data derived from an input surface with a display screen refresh interval; and computer readable program code configured to synchronize, using one or more processors, the set of input data derived from the input surface with a refresh of a display screen.

DETAILED DESCRIPTION

Many input surfaces (e.g., digitizer, touch screen, etc.) function as a sensor that delivers data at one point in time, i.e., as input data is sensed it is streamed or reported to another component or system, e.g., an operating system (OS). This minimizes delay latency in the input data delivery but also incurs a high expense of having the input surface provide many interrupts, each transferring only a small amount of data. One possible result is greater end-to-end latency as the system processor/CPU receives each data point and adds it to a buffer to be processed when the OS is ready for the data.

I/O architecture (e.g., USB, I2C, etc.) is evolving to adopt a batch-processing methodology. Thus, input surfaces fill an internal buffer and release data on-demand as a batch or group of data points that have been collected during an interval. This is generally more efficient in terms of interrupt handling but introduces a new problem, i.e., the data in the buffer(s) is likely to straddle two display frames (refresh periods), part from one frame and part from another. The system (OS) simply requests/receives a batch of data points collected since the last request and no attempt is made to take into account the relationship between the location data points and the display screen functioning (e.g., frame or refresh rate). This leads to difficulties in certain contexts. For example, if the user is providing input rapidly (e.g., moving a stylus around quickly, such as when providing handwriting input), the resultant visual display may be a “jumpy” drawing characteristic rendered by the display screen. For example, a line drawn on screen by a user may be rendered such that it falls behind the stylus tip and then catches up abruptly.

Accordingly, an embodiment provides a solution wherein input surface data (e.g., derived from an input to a digitizer or touch screen) is synchronized with a screen refresh timing. An embodiment utilizes an indication of the display screen refresh timing, e.g., the vsync signal signal available from a graphics sub-system. This provides data from the input surface to the system (e.g., OS) and applications thereof in a timely fashion such that on screen renderings are improved by virtue of including in the overall synchronization the data of the input sub-system.

Referring toFIG. 1andFIG. 2, while various other circuits, circuitry or components may be utilized in information handling devices, with regard to smart phone and/or tablet circuitry200, an example illustrated inFIG. 2includes a system on a chip design found for example in tablet or other mobile computing platforms. Software and processor(s) are combined in a single chip210. Internal busses and the like depend on different vendors, but essentially all the peripheral devices (220) may attach to a single chip210. In contrast to the circuitry illustrated inFIG. 1, the circuitry200combines the processor, memory control, and I/O controller hub all into a single chip210. Also, system200of this type do not typically use SATA or PCI or LPC. Common interfaces for example include SDIO and I2C.

There are power management chip(s)230, e.g., a battery management unit, BMU, which manage power as supplied for example via a rechargeable battery240, which may be recharged by a connection to a power source (not shown). In at least one design, a single chip, such as210, is used to supply BIOS like functionality and DRAM memory.

System200typically includes one or more of a WWAN transceiver250and a WLAN transceiver260for connecting to various networks, such as telecommunications networks and wireless base stations. Commonly, system200will include a touch screen270for data input and display. System200also typically includes various memory devices, for example flash memory280and SDRAM290.

FIG. 1, for its part, depicts a block diagram of another example of information handling device circuits, circuitry or components. The example depicted inFIG. 1may correspond to computing systems such as the THINKPAD series of personal computers sold by Lenovo (US) Inc. of Morrisville, N.C., or other devices. As is apparent from the description herein, embodiments may include other features or only some of the features of the example illustrated inFIG. 1.

The example ofFIG. 1includes a so-called chipset110(a group of integrated circuits, or chips, that work together, chipsets) with an architecture that may vary depending on manufacturer (for example, INTEL, AMD, ARM, etc.). The architecture of the chipset110includes a core and memory control group120and an I/O controller hub150that exchanges information (for example, data, signals, commands, et cetera) via a direct management interface (DMI)142or a link controller144. InFIG. 1, the DMI142is a chip-to-chip interface (sometimes referred to as being a link between a “northbridge” and a “southbridge”). The core and memory control group120include one or more processors122(for example, single or multi-core) and a memory controller hub126that exchange information via a front side bus (FSB)124; noting that components of the group120may be integrated in a chip that supplants the conventional “northbridge” style architecture.

InFIG. 1, the memory controller hub126interfaces with memory140(for example, to provide support for a type of RAM that may be referred to as “system memory” or “memory”). The memory controller hub126further includes a LVDS interface132for a display device192(for example, a CRT, a flat panel, touch screen, et cetera). A block138includes some technologies that may be supported via the LVDS interface132(for example, serial digital video, HDMI/DVI, display port). The memory controller hub126also includes a PCI-express interface (PCI-E)134that may support discrete graphics136.

InFIG. 1, the I/O hub controller150includes a SATA interface151(for example, for HDDs, SDDs,180et cetera), a PCI-E interface152(for example, for wireless connections182), a USB interface153(for example, for devices184such as a digitizer, keyboard, mice, cameras, phones, microphones, storage, other connected devices, et cetera), a network interface154(for example, LAN), a GPIO interface155, a LPC interface170(for ASICs171, a TPM172, a super I/O173, a firmware hub174, BIOS support175as well as various types of memory176such as ROM177, Flash178, and NVRAM179), a power management interface161, a clock generator interface162, an audio interface163(for example, for speakers194), a TCO interface164, a system management bus interface165, and SPI Flash166, which can include BIOS168and boot code190. The I/O hub controller150may include gigabit Ethernet support.

Information handling devices, as for example outlined inFIG. 1andFIG. 2, may provide input surfaces (e.g., digitizer, touch screen or the like) that allow a user to provide input (e.g., touch input via a finger tip or stylus, etc.) and have renderings on screen in response to such inputs. A common example of such rendering and response is providing handwriting input to a touch screen or digitizer with a stylus that is in turn rendered on the display screen as handwritten input.

Referring toFIG. 3, an input surface, e.g., digitizer, may buffer input data (i.e., input data corresponding to x, y coordinate data of inputs from a stylus) at the top or beginning of a first display frame refresh at301. The digitizer continues to buffer the input data, e.g., until the top of a next or second display frame, i.e., corresponding to the beginning of a screen refresh on the display is detected at302.

Thus, at a predetermined point in time, a determination is made302, e.g., a determination that a top of a next display frame (such as 2ndframe) is detected. This causes the digitizer to buffer the remaining input data for the current display frame303and to sequester the current buffer304until the system (e.g., OS) requests the data from the digitizer sub-system. Also, the digitizer will make available another buffer304continue to buffer the input data (storing the input data into another buffer), e.g., selected from a pool of available buffers. An embodiment proceeds in this manner such that when the top of an nthframe is detected305, an nthbuffer is created306and sequestration/availing a new buffer continue307in like fashion. This permits sequestering input data into buffers, and subsequent release thereof to an OS, utilizing timing information of the display screen's refresh. The buffer pool or storage space needs to contain enough space to buffer input data to cover a worst-case scenario, i.e., input data corresponding to a number of frames the OS may (temporarily) fall behind such that this data is available when the OS is capable of handling it.

Other mechanisms for leveraging the indication of display screen refresh rate or timing are possible. For example, in addition to such buffering, or as an alternative thereto, an embodiment may provide timing information along with the input data derived form the input sub-system. Thus, another component, e.g., an OS of the overall system, may be able to sort through the input data and utilize appropriately synchronized input data based on knowledge of the display screen refresh rate. Thus, an input sub-system need not be explicitly notified or made aware of the display screen refresh timing. Moreover, an OS may be modified to appropriately time requests such that input data buffered by an input sub-system is appropriately synchronized with the display screen refresh timing.

Referring toFIG. 4, in the example case of buffering the input data, an input sub-system such as a digitizer incorporated in an information handling device400(e.g., a laptop computer) may include a plurality of buffers401. It should be noted that although separate buffers are illustrated in the group or plurality of buffers401, these may be logical or physical distinctions.

A controller of the input sub-system, including e.g., including a processor402, may provide input data to a processor403of system400, e.g., for use in an OS404operating a display405(noting that display405may include its own sub-system, e.g., graphics sub-system). Likewise, as further described herein, OS404may avail input sub-system processor402with information or indication regarding the timing of display screen405refresh/frame rate. For example, processor403may communicate this information to processor402, which in turn manages the input data buffering in buffers401such that it is appropriately synchronized with the display device405timing.

A digitizer sub-system (as a non-limiting example of an input sub-system) may detect or be apprised of the beginning of a new display frame of a display device405through several mechanisms. For example, a graphics sub-system generally makes available or provides a “vsync” (vertical synchronization) interrupt to the OS404at the bottom or end of a display frame. In reaction to this, the OS404may explicitly notify the processor402of the digitizer or input sub-system in question of the end of or impending beginning of a display frame.

As another example, an additional vsync signal line (not illustrated) may be routed directly to a new start of frame input on the input sub-system to inform, e.g., a processor403of a digitizer, of the start or top of a new display frame. Therefore, the vsync signal may be utilized to indicate the synchronization timing between the display screen405frame refresh and collected input data stored in buffers401.

In an example case where the input sub-system is closely integrated with the display screen405(e.g., a touch screen sub-system), the existing vsync signal utilized by the touch screen control may be borrowed from the display screen405and routed to the digitizer or touch screen sub-system. This is akin to having the OS404notify the digitizer or touch screen sub-system, but takes advantage of the locality of the components of the touch screen sub-system. For example, as all components of the touch screen/digitizer may be located in the same functional block, such an approach may be particularly appropriate for in-cell touch input device designs.

Other possible mechanisms of obtaining synchronization information are possible. For example, current digitizer and touch screen implementations attempt to cancel out interference between display scanning and digitizer scanning In order to do this (e.g., off-set the display scan and the digitizer scan), the sub-system is aware of the display refresh or frame beginning point or timing (e.g., vsync signal interval). In an embodiment, the detected vsync signal interval or timing may be used, in addition to preventing scan interference, to indicate when the display begins a new frame in order to appropriately buffer and provide input data to the display for refresh.

A benefit of determining the precise timing of the display scan position allows an input sub-system to more efficiently cancel out interference that display scanning creates. For example, an input sub-system may scan its own array slightly ahead of or behind the display scan, etc., because the display scan position is known. This would permit off-set between the two scans (display and input) and consequently avoidance of interference there-between.

Processing of the input data may be appropriately scaled or tailored using such timing information regarding display screen refresh or scanning During the time that the input sub-system controller (including processor402) is accumulating input samples in buffers401and, e.g., in between vsync boundaries, the input sub-system controller may apply additional processing or filtering of the input data. In contrast to conventional filtering processes that may not be completed prior to the next request, and thus delay delivery of data, e.g., to OS404, an embodiment, having timing information regarding display refresh rate available (e.g., by virtue of knowing the vsync signal interval), may appropriately scale processing so as to not delay delivery of buffered input data. For example, the input sub-system controller sub-system may use the collection of samples to filter out errant data points or to apply signal processing to improve the accuracy or quality of the collection of samples during the buffering interval. Such processing may include but not necessarily be limited to improved line drawing routines such as smoothing and straightening, improved character formation, assisted handwriting recognition pre-processing and shape or region drawing assistance.

The input sub-system controller may alter its sampling frequency from one vsync period to the next. In this fashion, the amount of activity within the current vsync period can be used to predict the appropriate sampling frequency of the next period. The per-vsync period frequency adjustment would allow the input sub-system controller to trade off sampling resolution for power consumption based on the content of the previous interval or period.

By combining increased sample frequency and additional signal processing within the input sub-system controller, the accuracy of the input device can be improved. This may be accomplished using samples for the same data input position and then averaging them together to register an (x, y) point with greater accuracy. This concept may be extended to a line segment, where each (x, y) point may use the previous series of points to more accurately register the current position.

Accordingly, an embodiment provides synchronization between input data provisioning, e.g., via appropriate buffering/delivery of input data within a data input sub-system, and display screen refresh/frame rate. Such appropriate synchronization will help a system avoid unfortunate visual artifacts (e.g., delayed rendering, tearing, etc.) from occurring due to out-of-synch input data and display screen data.

Any combination of one or more non-signal device readable medium(s) may be utilized. The non-signal medium may be a storage medium. A storage medium may be, for example, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a storage medium would include the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

Aspects are described herein with reference to the figures, which illustrate example methods, devices and program products according to various example embodiments. It will be understood that the actions and functionality may be implemented at least in part by program instructions. These program instructions may be provided to a processor of a general purpose information handling device, a special purpose information handling device, or other programmable data processing device or information handling device to produce a machine, such that the instructions, which execute via a processor of the device implement the functions/acts specified.