Filter chip

A filter chip includes a substrate, a plurality of external terminals formed on the substrate for external connection, and a plurality of passive element forming regions provided in the regions between the plurality of external terminals in plan view when viewed along a direction normal to the surface of the substrate, the plurality of passive element forming regions including at least a resistor forming region where a resistor is formed. The resistor forming region includes a resistive conductive film formed on the substrate with one end and the other end thereof electrically connected to different ones of the external terminals, and a fuse portion integrally formed with the resistive conductive film. The fuse portion is cuttably provided to electrically connect a part of the resistive conductive film to the external terminals, or to electrically separate a part of the resistive conductive film from the external terminals.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application corresponds to Patent Application No. 2015-143327 submitted to Japanese Patent Office on Jul. 17, 2015, and Patent Application No. 2016-131743 submitted to Japanese Patent Office on Jul. 1, 2016, and the entire contents of these applications are hereby incorporated by reference.

TECHNICAL FIELD

The present invention relates to a filter chip including a plurality of passive element forming regions.

BACKGROUND ART

A patent literature 1 (Japanese Unexamined Patent Application Publication 10-322157) discloses a noise filter equipped with a coil conductor, a resistive element, and a capacitor conductor.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a filter chip capable of minimizing an error relative to a required element value of a passive element thereby achieving favorable frequency characteristics.

DESCRIPTION OF EMBODIMENTS

A filter chip according to an aspect of the present invention for achieving the above-described object includes a substrate, a plurality of external terminals formed on the substrate for external connection, and a plurality of passive element forming regions provided in the regions between the plurality of external terminals in plan view when viewed along a direction normal to the surface of the substrate, the plurality of passive element forming regions including at least a resistor forming region where a resistor is formed. The resistor forming region includes a resistive conductive film formed on the substrate with one end and the other end thereof electrically connected to different ones of the external terminals, and a fuse portion integrally formed with the resistive conductive film. The fuse portion is cuttably provided to electrically connect a part of the resistive conductive film to the external terminals, or to electrically separate a part of the resistive conductive film from the external terminals.

With this configuration, a part of the resistive conductive film is electrically connected to the external terminals or electrically separated from the external terminals, and thus the resistance value of a resistor can be adjusted. Thereby, the resistance value of a resistor can be adjusted to a desired resistance value, and thus an error relative to a required resistance value of a resistor can be minimized. As a result, a filter chip capable of achieving favorable frequency characteristics can be provided. More specifically, such a resistor, when adopted for a low-pass filter or a high-pass filter, can contribute to the suppression of insertion loss variation and so forth in the passband.

In the filter chip, the resistive conductive film may include a portion formed in a zig-zag pattern.

In the filter chip, the resistive conductive film may include a resistor film formed on the substrate, and a plurality of conductor films formed spaced apart from each other on the resistor film. In this case, a portion of the resistor film exposed between mutually adjacent conductor films constitutes a single resistive element, and the fuse portion may be provided to electrically connect at least one of a plurality of the resistive elements to the external terminals or to electrically separate at least one of the plurality of the resistive elements from the external terminals.

With this configuration, the resistance value of a resistor can be adjusted by the connection or separation of a resistive element, and thus the adjustment precision for a resistance value can be further improved. Further, by changing the shape and/or the area of the resistor film exposed between mutually adjacent conductor films, the resistance value of a resistive element can be modified or adjusted. A plurality of the resistive elements with each having the same resistance value is favorably arrayed in a matrix on the substrate. With this configuration, a resistance value can be easily adjusted to a desired resistance value by the cutting or non-cutting of a fuse portion without altering the basic design of a filter chip.

In the filter chip, the plurality of passive element forming regions may include a capacitor forming region where a capacitor is formed. The capacitor forming region may include a dielectric film, and a lower electrode and an upper electrode provided to sandwich the dielectric film and electrically connected to different external terminals. With this configuration, the upper electrode may include a plurality of electrode film portions separately formed to face the lower electrode with mutually different facing areas, and a capacitor-side fuse portion cuttably provided to electrically separate the electrode film portions from the external terminals.

With this configuration, an electrode film portion is selectively and electrically separated from the external terminal, and thus the capacitance value of a capacitor can be adjusted. Thereby, the capacitance value of a capacitor can be adjusted to a desired capacitance value, and thus an error relative to a required capacitance value of a capacitor can be minimized. For example, when the facing areas of a plurality of electrode film portions facing to a lower electrode are set to form a geometric progression, a capacitance value can be adjusted to a target capacitance value with high precision corresponding to a minimum capacitance value (a value of the first term in a geometric progression). According to a filter chip including such a capacitor, a various types of filter circuits having further favorable frequency characteristics can be achieved by combining with the above-described resistors. The above-described filter chip may constitute a low-pass filter including the above described resistor and the above described capacitor, or may constitute a high-pass filter including the above described resistor and the above described capacitor.

In the filter chip, the plurality of passive element forming regions may include a coil forming region where a coil is formed. The coil forming region may include a coil conductor formed with one end and the other end thereof electrically connected to different ones of the external terminals in a spiral shape in plan view when viewed along a direction normal to the surface of the substrate. The coil conductor may be embedded in a trench formed in the substrate in a spiral shape in plan view.

The coil forming region may include a first electrode and a second electrode electrically connected to different ones of the external terminals and formed spaced apart from each other to be electrically connected to one end and the other end of the coil conductor. The first electrode may include a plurality of extraction electrodes extracted toward a plurality of different portions of the coil conductor and connected to the plurality of different portions of the coil conductor, and a fuse portion integrally formed with the extraction electrode and cuttably provided to electrically separate the plurality of different portions of the coil conductor from each of the external terminals.

With this configuration, the number of windings of a coil can be adjusted by selectively cutting a coil side fuse portion. Thereby, the value of inductance of a coil can be adjusted to a desired value, and thus an error relative to a required value of inductance of a coil can be minimized. According to a filter chip including such a coil, a various types of filter circuits having further favorable frequency characteristics can be achieved by combining with the previously described resistors. The filter chip may constitute a low-pass filter including the resistor and the coil, or may constitute a high-pass filter including the resistor and the coil.

In the filter chip, the plurality of passive element forming regions may include a capacitor forming region where a capacitor is formed, and a coil forming region where a coil is formed. A low-pass filter including the resistor, the capacitor and the coil may be formed, or a high-pass filter including the resistor, the capacitor and the coil may be formed.

A filter chip according to another aspect of the present invention includes a substrate, a plurality of external terminals formed on the substrate for external connection, and a plurality of passive element forming regions provided in the regions between the plurality of external terminals in plan view when viewed along a direction normal to the surface of the substrate, the plurality of passive element forming regions including at least a capacitor forming region where a capacitor is formed. The capacitor forming region includes a lower electrode electrically connected to an external terminal, an upper electrode electrically connected to another external terminal different from the external terminal to which the lower electrode is connected, and a dielectric film interposed between the lower electrode and the upper electrode. The upper electrode includes a plurality of electrode film portions separately formed to face the lower electrode with mutually different facing areas, and a fuse portion cuttably provided to electrically separate the electrode film portions from the external terminals.

With this configuration, the capacitance value of a capacitor can be adjusted by selectively and electrically separating an electrode film portion from the external terminal. Thereby, the capacitance value of a capacitor can be adjusted to a desired capacitance value, and thus an error relative to a required capacitance value of a capacitor can be minimized. As a result, a filter chip capable of achieving favorable frequency characteristics can be provided. For example, such a capacitor, when adopted for a low-pass filter or a high-pass filter, can contribute to the suppression of insertion loss variation and so forth in the passband. Further, when the facing areas of a plurality of electrode film portions facing to a lower electrode are set to form a geometric progression, a capacitance value can be adjusted to a target capacitance value with high precision corresponding to a minimum capacitance value (a value of the first term in a geometric progression).

A filter chip according to still another aspect of the present invention includes a substrate, a plurality of external terminals formed on the substrate for external connection, and a plurality of passive element forming regions provided in the regions between the plurality of external terminals in plan view when viewed along a direction normal to the surface of the substrate, the plurality of passive element forming regions including at least a coil forming region where a coil is formed. The coil forming region includes a first electrode and a second electrode formed spaced apart from each other to be electrically connected to different external terminals, and a coil conductor formed in a spiral shape in plan view with one end electrically connected to the first electrode and the other end electrically connected to the second electrode. The first electrode includes a plurality of extraction electrodes extracted toward a plurality of different portions of the coil conductor and connected to the plurality of different portions of the coil conductor, and a fuse portion integrally formed with the extraction electrode and cuttably provided to electrically separate the plurality of different portions of the coil conductor from each of the external terminals.

With this configuration, the number of windings of a coil can be adjusted by selectively cutting a fuse portion. Thereby, the value of inductance of a coil can be adjusted to a desired value, and thus an error relative to a required value of inductance of a coil can be minimized. As a result, a filter chip capable of achieving favorable frequency characteristics can be provided. For example, such a coil, when adopted for a low-pass filter or a high-pass filter, can contribute to the suppression of insertion loss variation and so forth in the passband.

Hereinafter, embodiments according to the present invention will be specifically discussed with reference to the attached drawings.

First Embodiment

FIG. 1is a partially notched perspective view of a filter chip1according to a first embodiment of the present invention.FIG. 2is a schematic plan view of the filter chip1shown inFIG. 1.

Referring toFIG. 1, a filter chip1is formed in a substantially rectangular parallelepiped shape, and has a planar rectangular shape. A length L in the longitudinal direction of the filter chip1may be, for example, between 0.5 mm and 1.5 mm, inclusive (approximately 1.0 mm in this embodiment). A length W in the transversal direction of the filter chip1may be, for example, between 0.4 mm and 1.2 mm, inclusive (approximately 0.8 mm in this embodiment). A thickness T of the filter chip1may be, for example, between 0.1 mm and 0.5 mm, inclusive (approximately 0.2 mm in this embodiment).

The filter chip1includes a substantially rectangular parallelepiped substrate2. The substrate2includes a pair of principal surfaces2a,2b, a pair of side surfaces2calong the longitudinal direction, and a pair of side surfaces2dalong the transversal direction. One of the principal surfaces2a,2b(principal surface2aon the upper side inFIG. 1) is defined as an element forming surface2a. Hereinafter, the principal surface2ais referred to as the “element forming surface2a,” and the principal surface2bon the opposite side of the element forming surface2ais referred to as the “rear surface2b.”

A plurality of external terminals3(five external terminals in this embodiment) is formed spaced apart from each other on the element forming surface2aof the substrate2. The plurality of external terminals3includes a pair of input terminals3a, a pair of output terminals3b, and a ground terminal3c. The pair of input terminals3ais formed spaced apart from each other on the side of one end of the substrate2(left side end inFIG. 1) in plan view when viewed along a direction normal to the element forming surface2aof the substrate2(hereinafter simply referred to as “in plan view”).

The pair of output terminals3bis formed spaced apart from each other on the side of the other end of the substrate2(right side end inFIG. 1) in plan view. The ground terminal3cis formed in the center of the substrate2in plan view. Each external terminal is formed in substantially a hemispherical shape. The diameter ϕ of each external terminal3is, for example, between 0.1 mm and 0.3 mm, inclusive (approximately 0.25 mm in this embodiment). Each external terminal3may be, for example, a solder ball.

Referring toFIG. 2, a pad electrode film forming region5on which a pad electrode film4is provided at a position corresponding to each external terminal3on the element forming surface2aof the substrate2. More specifically, the pad electrode film forming region5includes a pair of input-side pad electrode film forming regions5a, a pair of output-side pad electrode film forming regions5band a ground-side pad electrode film forming region5c. Input-side pad electrode films4ato which the input terminals3aare connected are formed in the pair of input-side pad electrode film forming regions5a. Output-side pad electrode films4bto which the output terminals3bare connected are formed in the pair of output-side pad electrode film forming regions5b. Ground-side pad electrode film4cto which the ground terminal3cis connected is formed in the ground-side pad electrode film forming region5c.

Further, a first filter circuit forming region12on which a first filter circuit FC1is formed and a second filter circuit forming region13on which a second filter circuit FC2is formed are provided on the element forming surface2aof the substrate2. The first filter circuit forming region12and the second filter circuit forming region13are partitioned in a rectangular shape by a pair of side surfaces2dalong the transversal direction, a transversal line TL traversing the intermediate portion of the pair of side surfaces2d, and a pair of side surfaces2calong the longitudinal direction.

The transversal line TL traverses the ground-side pad-electrode film forming region5cto provide the first filter circuit FC1and the second filter circuit FC2with a common ground-side pad electrode film4c. That is, the ground terminal3cprovides the first filter circuit FC1and the second filter circuit FC2with a common ground potential. A filter unit FU1is composed of these first filter circuit FC1and second filter circuit FC2.

In the first filter circuit forming region12, regions between a plurality of the pad electrode film forming regions5(that is, regions between the plurality of external terminals3), a first capacitor forming region14, a first diode forming region15, a second capacitor forming region16, a second diode forming region17, and a resistor forming region18are provided. The first capacitor forming region14, the second capacitor forming region16, and the resistor forming region18are formed as an example of the passive element forming region according to the present invention. The configuration of the second filter circuit forming region13is the same as the configuration of the first filter circuit forming region12, and therefore the description is omitted by applying the same reference numerals to corresponding elements.

A first electrode film20and a second electrode film21are formed spaced apart from each other in the first capacitor forming region14, the first diode forming region15, the second capacitor forming region16, the second diode forming region17, and the resistor forming region18. A first connection electrode film22is electrically connected to the first electrode film20, and a second connection electrode film23is electrically connected to the second electrode film21.

Hereinafter, the first electrode film20formed in each region is referred to as “a first electrode film20C1,20C2,20D1,20D2,20R,” and the second electrode film21is referred to as “a second electrode film21C1,21C2,21D1,21D2,21R.” Further, the first connection electrode film22formed in each region is referred to as “a first connection electrode film22C1,22C2,22D1,22D2,22R,” and the second connection electrode film23is referred to as “a second connection electrode film23C1,23C2,23D1,23D2,23R.”

The first capacitor forming region14is provided in a region between the input-side pad electrode film forming regions5aand the transversal line TL. A first capacitor C1is formed between the first electrode film20C1and the second electrode film21C1. The first capacitor C1is electrically connected to the input-side pad electrode film4avia the first electrode film20C1and the first connection electrode film22C1, and is electrically connected to the ground-side pad electrode film4cvia the second electrode film21C1and the second connection electrode film23C1.

The first diode forming region15is provided in a region between the input-side pad electrode film forming regions5aand the ground-side pad electrode film forming region5c. A first diode D1is formed between the first electrode film20D1and the second electrode film21D1. The first diode D1is electrically connected to the input-side pad electrode film4avia the first electrode film20D1and the first connection electrode film22D1, and is electrically connected to the ground-side pad electrode film4cvia the second electrode film21D1and the second connection electrode film23D1.

The second capacitor forming region16is provided in a region between the output-side pad electrode film forming regions5band the transversal line TL. A second capacitor C2is formed between the first electrode film20C2and the second electrode film21C2. The second capacitor C2is electrically connected to the output-side pad electrode film4bvia the first electrode film20C2and the first connection electrode film22C2, and is electrically connected to the ground-side pad electrode film4cvia the second electrode film21C2and the second connection electrode film23C2.

The second diode forming region17is provided in a region between the output-side pad electrode film forming regions5band the ground-side pad electrode film forming region5c. A second diode D2is formed between the first electrode film20D2and the second electrode film21D2. The second diode D2is electrically connected to the output-side pad electrode film4bvia the first electrode film20D2and the first connection electrode film22D2, and is electrically connected to the ground-side pad electrode film4cvia the second electrode film21D2and the second connection electrode film23D2.

The resistor forming region18is provided in a region segmented by the first diode forming region15, the second diode forming region17, and the ground-side pad electrode film forming region5c. A resistor R is formed between the first electrode film20Rand the second electrode film21R. The resistor R is electrically connected to the input-side pad electrode film4avia the first electrode film20Rand the first connection electrode film22R, and is electrically connected to output-side pad electrode film4bvia the second electrode film21Rand the second connection electrode film23R.FIG. 2shows an example wherein the first connection electrode film22Ris integrally formed with the first connection electrode film22D1, and the second connection electrode film23Ris integrally formed with the first connection electrode film22D2.

FIG. 3is a circuit diagram of the filter chip1shown inFIG. 1. As shown inFIG. 3, the first filter circuit FC1and the second filter circuit FC2include a π type low-pass filter24. The π type low-pass filter24includes a resistor R, and a first capacitor C1and a second capacitor C2connected in parallel with each other at both ends of the resistor R. Further, the first filter circuit FC1and the second filter circuit FC2include the first diode D1and the second diode D2connected in parallel with the π type low-pass filter24between the π type low-pass filter24and the input terminal3aand between π type low-pass filter24and the output terminal3b. The first diode D1and the second diode D2are bidirectional Zener diodes in this embodiment. Thus, in the filter chip1, the single filter unit FU1is composed of the first filter circuit FC1and the second filter circuit FC2.

Hereinafter, the specific configuration of the filter chip1is described with reference toFIG. 4.FIG. 4is a schematic cross-sectional view of the filter chip1shown inFIG. 1. Since the first capacitor forming region14and the second capacitor forming region16have substantially the same configuration, hereinafter the configuration of the first capacitor forming region14will be described as an example. Further, since the first diode forming region15and the second diode forming region17have substantially the same configuration, the configuration of the first diode forming region15will be described as an example.

Referring toFIG. 4, the first capacitor C1, the first diode D1, and the resistor R are formed in respectively different layers. More specifically, a laminated film with a plurality of insulating films25-28laminated therein and an encapsulation resin30that covers the laminated film. The plurality of insulating films25-28includes a first insulating film25, a second insulating film26, a third insulating film27and a fourth insulating film28formed in this order from the element forming surface2aof the substrate2(see alsoFIG. 1). Further, although the filter chip1includes a fifth insulating film29that covers at least the side surfaces2c,2das shown inFIG. 1, which is not shown inFIG. 4.

The first insulating film25includes a silicon oxide film, and has a thickness for example between 8000 Å and 12000 Å, inclusive (approximately 10000 Å in this embodiment). The second insulating film26includes a silicon oxide film with a flat surface (surface opposite the substrate2), more specifically a flat film composed of Undoped Silica Glass (USG) or a flat film composed of Spin On Glass (SOG). The thickness of the second insulating film is, for example, between 15000 Å and 25000 Å, inclusive (approximately 20000 Å in this embodiment).

The third insulating film27includes a silicon nitride film, and has a thickness, for example, between 1000 Å and 5000 Å, inclusive (approximately 3000 Å in this embodiment). The fourth insulating film28includes a silicon nitride film, and has a thickness, for example, between 10000 Å and 15000 Å, inclusive (approximately 12000 Å in this embodiment). The fifth insulating film29includes a silicon nitride film. The third insulating film27, the fourth insulating film28and the fifth insulating film29are formed as passivation films.

The first capacitor C1and the first diode D1are formed on the substrate2and the first insulating film25. The resistor R is formed on the second insulating film26. The pad electrode film4, the first connection electrode film22and the second connection electrode film23are formed on the third insulating film27. The pad electrode film4, the first connection electrode film22and the second connection electrode film23may be composed of an electrode film integrally formed with each other.

The pad electrode film4, the first connection electrode film22and the second connection electrode film23include a metal film containing at least either aluminum (Al) or copper (Cu). The pad electrode film4, the first connection electrode film22and the second connection electrode film23may be an alloy film composed of, for example, AuCu, AlSiCu and so forth. The pad electrode film4, the first connection electrode film22and the second connection electrode film23may have a thickness, for example, between 5000 Å and 12000 Å, inclusive (approximately 12000 Å in this embodiment). Further, the pad electrode film4, the first connection electrode film22and the second connection electrode film23may be configured so that portions having the same potential are selectively formed as an integrated electrode film. Hereinafter, the specific configurations of the first capacitor forming region14, the first diode forming region15, and the resistor forming region18will be described in this order.

FIG. 5is a plan view of a capacitor forming region14shown inFIG. 2.

Referring toFIG. 4andFIG. 5, the first electrode film20C1and the second electrode film21C1are formed spaced apart from each other on the first insulating film25in the first capacitor forming region14. The first capacitor C1is formed in the region between these first electrode film20C1and the second electrode film21C1. The first capacitor C1includes a dielectric film35formed on the substrate2, and a lower electrode36and an upper electrode37formed to sandwich the dielectric film35.

More specifically, the substrate2has, for example, p-type impurities introduced therein. An impurity region38as the lower electrode36having n-type impurities introduced therein is formed in the surface portion of the substrate2. The impurity region38is formed, for example, in a substantially rectangular shape in plan view. A thin film portion25ais selectively formed in the first insulating film25to thinly cover the impurity region38. The thickness of the thin film portion25ais, for example, between 100 Å and 500 Å, inclusive (approximately 200 Å in this embodiment). A first opening39and a second opening40are formed spaced apart from each other to selectively expose the impurity region38in the thin film portion25aof the first insulating film25.

The first opening39is formed in a substantially rectangular shape in plan view to extend along the first capacitor forming region14(see dashed line inFIG. 5). Whereas, the second opening40is formed in a substantially rectangular shape in plan view to expose the impurity region38with an opening area smaller than the opening area of the first opening39(see dashed line inFIG. 5). The dielectric film35kept in contact with the impurity region38, and the upper electrode37facing the impurity region38across the dielectric film35, are formed on the substrate2exposed through the first opening39. Whereas, a contact electrode41is formed spaced apart from the upper electrode37on the substrate2exposed through the second opening40.

One surface and the other surface of the dielectric film35are formed along the element forming surface2aof the substrate2exposed through the first opening39and the first insulating film25, and are selectively extracted toward a region outside the first capacitor forming region14. The dielectric film35includes at least either a silicon nitride film or a silicon oxide film. The dielectric film35may be an ONO film wherein a silicon oxide film, a silicon nitride film, and a silicon oxide film are laminated in this order. The thickness of the dielectric film35may be between 100 Å and 1000 Å, inclusive (approximately 500 Å in this embodiment).

The upper electrode37is integrally formed with the first electrode film20C1as an extracted portion extracted from the first electrode film20C1, and is formed to face the impurity region38across the dielectric film35at least in the opening39. One surface and the other surface of the upper electrode37are formed in a substantially rectangular shape in plan view along the element forming surface2aof the substrate2exposed through the first opening39and the first insulating film25.

The contact electrode41is integrally formed with the second electrode film21C1as an extracted portion extracted from the second electrode film21C1, and is formed to be electrically connected with the impurity region38in the second opening40. The contact electrode41is formed above the first insulating film25across the dielectric film35. The contact electrode41is electrically separated from the upper electrode37by a slit S provided along each perimeter of the upper electrode37and the contact electrode41.

The first electrode film20C1is electrically connected to the input-side pad electrode film4avia a corresponding contact42and the first connection electrode film22C1, and the second electrode film21C1is electrically connected to the ground-side pad electrode film4cvia a corresponding contact42and the second connection electrode film23C1. The contact42may include a conductive material embedded in a contact hole formed to pass through the second insulating film26and the third insulating film27. The contact42may be integrally formed using the same material as each pad electrode4and each connection electrode film22,23.

When a prescribe voltage is applied between the input terminal3aand the output terminal3b, charges are stored in the dielectric film35interposed between the lower electrode36(impurity region38) and the upper electrode37. As such, the first capacitor C1is formed in the first capacitor forming region14.

FIG. 6is a plan view of the first diode forming region15shown inFIG. 2.

Referring toFIG. 4andFIG. 6, the first electrode film20D1and the second electrode film21D1are formed spaced apart from each other on the first insulating film25in the first diode forming region15. The first diode D1is formed in the region between these first electrode film20D1and the second electrode film21D1. More specifically the first diode D1includes a plurality of first diffusion regions45and a plurality of second diffusion regions46, which are formed by introducing n-type impurities into the surface portion of the substrate2.

The first diffusion region45and the second diffusion region46have the same depth and the same n-type impurity concentration, and form a p-n junction with the substrate2. The first diffusion region45and the second diffusion region46are arranged at the center along a direction between the first electrode film20D1and the second electrode film21D1facing each other, and are aligned along a direction orthogonal to the facing direction. The first diffusion region45and the second diffusion region46are alternately arranged spaced apart from each other.

The first insulating film25has the thin film portion25aselectively formed on the first diffusion region45and the second diffusion region46. The thin film portion25aof the first insulating film25has a first contact hole47and a second contact hole48that selectively expose the first diffusion region45and the second diffusion region46. The first contact hole47and the second contact hole48expose the first diffusion region45and the second diffusion region46at a position with a distance from the peripheral edges of the first diffusion region45and the second diffusion region46in plan view.

The first electrode film20D1is formed above the first insulating film25across the dielectric film35, and includes a plurality of first extraction electrodes49extracted toward each first diffusion region45. Each first extraction electrode49is extracted to cover the first diffusion region45with a width boarder than the width of each first diffusion region45. That is, the first extraction electrodes49are formed in a comb shape in plan view.

The tip portion of each first extraction electrode49is formed in a substantially rectangular shape with a notched corner. The first extraction electrode49enters the first contact hole47from above the first insulating film25, and forms an ohmic contact with the first diffusion region45. In this embodiment, the first electrode film20D1formed in the first diode forming region15is integrally formed with the first electrode film20C1(upper electrode37) formed in the first capacitor forming region14.

The second electrode film21D1is formed above the first insulating film25across the dielectric film35, and includes a plurality of second extraction electrodes50extracted toward each second diffusion region46. Each second extraction electrode50is extracted to cover the second diffusion region46with a width boarder than the width of each second diffusion region46. That is, the second extraction electrodes50are formed in a comb shape to engage with the first extraction electrodes49in plan view. The tip portion of each second extraction electrode50is formed in a substantially rectangular shape with a notched corner. The second extraction electrode50enters the second contact hole48from above the first insulating film25, and forms an ohmic contact with the second diffusion region46.

The first electrode film20D1is electrically connected to the input-side pad electrode film4avia a corresponding contact42and the first connection electrode film22D1. The second electrode film21D1is electrically connected to the ground-side pad electrode film4cvia a corresponding contact42and the second connection electrode film23D1. The plurality of first diffusion regions45and the plurality of second diffusion regions46constitute a single bidirectional Zener diode. In this embodiment, the first diode D1and the second diode D2may provide the first filter circuit FC1and the second filter circuit FC2with electrostatic discharge (ESD) tolerance of, for example, 10 kV or more.

FIG. 7is a plan view of a resistor forming region18shown inFIG. 2.FIG. 8is a plan view enlarging a portion of the resistor forming region18shown inFIG. 7.FIG. 9is cross-sectional view taken along line IX-IX shown inFIG. 8. As shown inFIG. 4andFIGS. 7-9, the first electrode film20Rand the second electrode film21Rare formed spaced apart from each other on the second insulating film26in the resistor forming region18. The resistor R is formed in the region between the first electrode film20Rand the second electrode film21R. The resistor R is formed between the first electrode film20Rand the second electrode film21R, and includes a resistive conductive film51with one end and the other end connected to the first electrode film20Rand the second electrode film21R. The resistive conductive film51includes a portion formed in a zig-zag pattern which is formed by folding the portion over a plurality of cycles.

More specifically, the resistive conductive film51includes a plurality of first linear patterns51alinearly extending spaced apart from each other along a direction between the first electrode film20Rand the second electrode film21Rfacing each other. The resistive conductive film51also includes a plurality of second linear patterns51bconnected to the first linear patterns51a, linearly extending along a direction intersecting with the facing direction (orthogonal direction). The resistive conductive film51is formed including the plurality of first linear patterns51aand the plurality of second linear patterns51bwith a prescribed number of foldbacks. More specifically, the resistive conductive film51is formed on the second insulting film26, including a resistor film line52formed in a zig-zag pattern, and a plurality of conductor films53laminated on the resistor film line52.

The resistor film line52may include one or more metallic species selected from a group including TiN, TiON and TiSiON. The thickness of the resistor film line52may be, for example, between 500 Å and 3000 Å, inclusive (approximately 1000 Å in this embodiment). As shown inFIG. 9, the plurality of conductor films53is arranged on the resistor film line52with a prescribed distance therebetween.

The conductor films53have an electric conductivity ρFhigher than an electric conductivity ρLof the resister film line52(ρL<ρF). The conductor film53contains at least either aluminum (Al) or copper (Cu). The conductor film53may be an alloy film such as AuCu, AlSiCu. In this embodiment, the conductor film53is composed of AuCu. The thickness of the conductor film53may be, for example, between 5000 Å and 12000 Å, inclusive (approximately 8000 Å in this embodiment).

Hereinafter, the configuration of the resistive conductive film51will be specifically described with reference toFIG. 10andFIG. 11.FIG. 10is a circuit diagram corresponding to a portion shown inFIG. 9.FIG. 11is a circuit diagram simplifyingFIG. 10.

Referring toFIG. 10, an exposed portion of the resistor film line52exposed between mutually adjacent conductor films53constitutes a single resistive element54. Each of a plurality of resistive elements54has the same shape and area. That is, each resistive element54is formed as a unit resistor having the same resistance value r. Whereas, a portion where the conductor film53is arranged causes a short-circuit through the conductor film53, and thus does not function as the resistive element54.

A plurality of such resistive elements is formed in the resistor film line52. The plurality of the resistive elements is arrayed spaced apart from each other in a matrix along the direction between the first electrode film20Rand the second electrode film21Rfacing each other and along the direction orthogonal to the facing direction. In this embodiment, eight resistive elements54are arrayed along the facing direction, and forty-four resistive elements54are arrayed along a direction orthogonal to the facing direction as shown inFIG. 8. That is, a total of 352 resistive elements54are formed.

A group of series resistors wherein 1-64 resistive elements54are connected in series is formed on each resistor film line52. The resistance value of each resistor film line52is determined by a synthesized resistor of a plurality of resistive elements formed on the resistor film line52. As such, each resistor film line52is formed as a unit resistor having a plurality of types of resistance values, and thus the resistance value of the resistor R is determined by a synthesized resistor of a plurality of resistor film lines52.

The resistive conductive film51also includes a connection conductor film55integrally formed with the plurality of conductor films53, and a fuse portion56formed on the second insulating film26to be integrally connected to the connection conductor film55. That is, the plurality of conductor films53is electrically connected to the first electrode film20Rvia the connection conductor film55and the fuse portion56.

The connection conductor film55includes a plurality of first linear patterns55alinearly extending along a direction between the first electrode film20Rand the second electrode film21Rfacing each other, and a plurality of second linear patterns55bconnected to the first linear patterns55a, linearly extending along a direction intersecting with the facing direction (orthogonal direction). The connection conductor film55is composed of the same material as that of the conductor film53.

The fuse portion56is formed to be integrally connected to the connection conductor film55between the first electrode film20and the connection conductor film55. The fuse portion56is cuttably (fusibly) provided to electrically connect at least one of the plurality of resistive elements54to the first electrode film20Rand the second electrode film21R, or to electrically separate at least one of the plurality of resistive elements54from the first electrode film20Rand the second electrode film21R. The fuse portion56is cut (melted) using, for example, laser light.

The fuse portion56is formed to linearly extend along a line between the first electrode film20Rand the second electrode film21Rfacing each other. The fuse portion56is formed to be thinner than the connection conductor film55. The fuse portion56is formed on the same layer with the same material. The fuse portion56may be composed of a portion of the resistive element (resistor film line52) and a portion of the conductor film53on the resistor film line52.

The input-side pad electrode film4ais electrically connected to the first electrode film20Rvia the contact42and the first connection electrode film22R. The previously-described second connection electrode film23Ris electrically connected to the second electrode film21Rvia the contact42and the second connection electrode film23R.

FIG. 12is a view applying the circuit diagram shown inFIG. 11toFIG. 8. Referring toFIG. 12, when the fuse portion56is connected the resistive element54(resister film line52) is short-circuited by the conductor film53and the connection conductor film55. For example, when a voltage is applied between the first electrode film20and the second electrode film21, a current flowing in the connection conductor film55by-passes the resistor film line52and the resistive element54, and flows in the conductor film53and the connection conductor film55. That is, when the fuse portion56is connected to the connection conductor film55, the resistive element54is electrically separated from the first electrode film20and the second electrode film21, and thus the resistance value does not increase.

Whereas, the fuse portion56is cut (melted), the resistive element54(resistor film line52) is electrically connected between the first electrode film20Rand the second electrode film21R. Therefore, a voltage is applied between the first electrode film20Rand the second electrode film21R, a current path in which a current flows through the resistive element54(resister film line52) is formed. That is, when the fuse portion56is cut (melted), the resistance value of the resistor R increases. By using such a resistive conductive film51, various types of resistor circuits can be achieved as shown inFIGS. 13-15.

FIG. 13is a circuit diagram illustrating an example of a resistive conductive film51. The resistor R includes a reference resistor circuit R8, and a series circuit of resistor R for serially connecting a resistor circuit R64, two resistor circuits R32, a resistor circuit R16, a resistor circuit R8, a resistor circuit R4, a resistor circuit R2, a resistor circuit R1, a resistor circuit R/2, a resistor circuit R/4, a resistor circuit R/8, a resistor circuit R/16, and a resistor circuit R/32.

Each of the reference resistor circuit R8and the resistor circuits R64-R2includes serially connected resistive elements54of the same number as the number each noted at the end (R64includes 64 resistive elements54). Each of the resistor circuits R/2-R/32 includes parallely connected resistive elements54of the same number as the number thereof noted at the end (R/32 includes 32 resistive elements54). The fuse portion56is parallely connected for each of the resistor circuits64—R/32 except for the reference resistor circuit R8.

when the fuse portion56is not melted, the resistor circuits64-R/32 except for the reference resistor circuit R8are short-circuited by the fuse portion56. Thus, a current flows in the fuse portion56so as to by-pass the resistor circuits64-R/32 after flowing through the reference resistor circuit R8. Eight resistive elements54are serially connected in the reference resistor circuit R8. Provided that the resistance value r of a single resistive element54is, for example, 8Ω, the resistance value of the resistor R is 64Ω. As such, by selectively fusing the fuse portions56, the resistance value of the resistor R can be adjusted as a whole digitally and precisely to obtain any resistance value.

FIG. 14is a circuit diagram illustrating another example of the resistive conductive film51. The resistor R includes a reference resistor circuit R/16, and a parallel circuit including 12 types of resistor circuits serially connected to the reference resistor circuit R/16 that are a resistor circuits R/16, R/8, R/4, R/2, R1, R2, R4, R8, R16, R32, R64, and R128. The fuse portions56are serially connected to each of the 12 types of resistor circuits R/16-R128except for the reference resistor circuit R/16. Even in this configuration, by selectively fusing the fuse portions56, the resistance value of the resistor R can be adjusted digitally and precisely to obtain any resistance value.

FIG. 15is a circuit diagram illustrating still another example of the resistive conductive film51. The resistor R includes a plurality of serially connected serial resistor circuits R12n(n=0, 1, 2 . . . ) and a plurality of parallely connected parallel resistor circuits R22n(n=0, 1, 2 . . . ). The serial resistor circuits R12nand the parallel resistor circuits R22nare connected in series. The fuse portions56are parallely connected to the serial resistor circuits R12nfor each resistor circuit similarly to the circuit shown inFIG. 13.

The fuse portions56are serially connected to the parallel resistor circuits R22nfor each resistor circuit similarly to the circuit shown inFIG. 14. According to this circuit, a high resistor circuit (for example, a resistor circuit of 1 kΩ or more) can be formed on the side of the serial resistor circuits R12nand a low resistor circuit (for example, a resistor circuit of 1 kΩ or less) can be formed on the side of the parallel resistor circuits R22n. As such, the resistor R including a resistor circuit with a wide range of a few ohms to a few thousand ohms can be easily obtained.

Thus, the filter chip1includes a single filter unit FU1composed of the first filter circuit FC1and the second filter circuit FC2(also seeFIG. 3). The filter unit FU1includes the resistor R with an adjustable resistance value. The measuring results of the resistance value of the filter chip1are shown in a table 1 below:

As shown in a table 1, the resistance value of the resistor R in the filter chip1, when actually measured, represented values between 9.9Ω and 10.1Ω, inclusive, and thus the resistance value of the resistor R could be adjusted with an error of ±1% or less with reference to the target resistance value of 10Ω. That is, it was found that the resistance value for the resistor R could be achieved with a tolerance of ±1% or less according to the filter chip1.

As a reference example, we, inventors measure the resistance value of a filter chip including a resistor R with so-called a solid shape wherein a linear resistive conductive film51connects between the first electrode film20Rand the second electrode film21R. The resistance value of the filter chip according to the reference example, when actually measured, represented values between 9.7Ω and 10.3Ω, inclusive, and thus the error of the resistance value was ±10%-±30%. As such, it was found that the adjustment precision for the resistance value of the resistor R had significantly improved in the filter chip1according to this embodiment.

The measuring results of the frequency characteristics of the filter chip1measured in an experiment are shown inFIG. 16.FIG. 16is a graph illustrating the frequency characteristics of the filter chip1shown inFIG. 1. The horizontal axis shown inFIG. 16represents frequencies (Hz), and the vertical axis represents insertion losses (dB). In this experiment, two filter chips1were prepared to measure each frequency characteristic as shown in a below-described table 2. One filter chip1has a first capacitor C1and a second capacitor C2with each having a capacitance value of 100 pF. The other filter chip1has a first capacitor C1and a second capacitor C2with each having a capacitance value of 10 pF.

Hereinafter, the filter chip1with a high capacitance value is referred to as a filter chip1A, and the filter chip1with a low capacitance value is referred to as a filter chip1B. InFIG. 16, a graph A shows the frequency characteristics of the filter chip1A, and a graph B shows the frequency characteristics of the filter chip1B.

Referring to the table 2 and the graph A shown inFIG. 16, in filter chip1A, a theoretical insertion loss at a passband is −0.83 dB while the actual insertion loss at the passband was −0.82 dB. Thus, it was confirmed that the insertion loss variation at the passband decreased in the filter chip1A. Further, it was found that the filter chip1A has favorable attenuation characteristics since an increase in insertion loss is limited at high frequencies in the graph A.

Referring to the table 2 and the graph B shown inFIG. 16, in filter chip1B, a theoretical insertion loss at a passband is −0.83 dB while the actual insertion loss at the passband was −0.82 dB. Thus, it was confirmed that the insertion loss variation at the passband decreased also in the filter chip1B. Further, it was found that the filter chip1B has favorable attenuation characteristics since an increase in insertion loss is almost nothing at high frequencies in the graph B.

Thus, in this embodiment, the resistance value of the resistor R can be adjusted by electrically connecting or separating at least one of the resistive elements54to and from the input terminal3aand the output terminal3b. As such, the resistance value of the resistor R can be adjusted to a desired resistance value, to thereby minimize an error relative to a required resistance value of the resistor R. In particular, the resistance value of the resistor R can be adjusted via a plurality of resistive elements54with mutually same resistance values in this embodiment, and thus the adjustment precision of the resistance value can be further improved. Thereby, in this embodiment, a target resistance value of the resistor R can be adjusted within the error range of ±1%. As a result, a filter chip1capable of achieving favorable frequency characteristics as shown inFIG. 16can be provided.

Further, in this embodiment, the resistive conductive film51includes a portion formed in a zig-zag pattern. As such, by adjusting the number of foldbacks in the portion formed in a zig-zag pattern, the value of parasite inductance in the resistive conductive film51can be adjusted. Thereby, by cutting the fuse portion56, the value of parasite inductance can also be adjusted to a desired value.

FIGS. 17-23are cross-sectional views illustrating an example of a method for manufacturing the filter chip1shown inFIG. 1.FIGS. 17-23are cross-sectional views illustrating regions corresponding to the previously described region shown inFIG. 4.

When forming the filter chip1, first provided is, for example, a disc-shaped base substrate60as shown inFIG. 17. The base substrate60is provided with chip forming regions61made into the filter chips1, arranged, for example, in a matrix, and formed in a substantially rectangular shape in plan view. The first capacitor forming region14, the first diode forming region15, the second capacitor forming region16, the second diode forming region17and the resistor forming region18are provided in the chip forming region61(also seeFIG. 2). After any required processes are carried out for the base substrate60, the base substrate60is cut along the chip forming regions61and diced into the filter chips1.

More specifically, the first insulating film25is formed on the surface of the base substrate60. The first insulating film25may be a silicon nitride film formed, for example, by thermal oxidation. Next, openings62are formed in the first insulating film25in the first capacitor forming region15and the first diode forming region16to selectively expose the surface of the base substrate60by wet etching with resist masks (not shown).

A thin insulating film is formed on the surface of the base substrate60exposed through the openings62as the thin film portion25aof the first insulating film25. This thin insulating film may be formed, for example, by thermal oxidation. Next, n-type impurities pass through the thin film portion25a, and are introduced into the surface portion of the base substrate60. The n-type impurities are diffused in the surface portion of the base substrate60by drive-in. Thereby, an impurity region38, a first diffusion region45and a second diffusion region46(seeFIG. 6) are formed in the surface portion of the base substrate60.

Next, as shown inFIG. 18, a first opening39is formed in the thin film portion25aby wet etching with resist masks (not shown). Then, the dielectric film35composed of a silicon nitride film is formed along the surface of the base substrate60exposed through the first opening39and the surface of the first insulating film25using, for example, chemical vapor deposition (CVD).

Next, as shown inFIG. 19, unnecessary portions of the dielectric film35are removed by dry etching with resist masks (not shown). Next, by dry etching with resist masks (not shown), the thin film portion25ais selectively removed, and a second opening40, the first contact hole47and the second contact hole48(seeFIG. 6) are formed. The dry etching may be, for example, Reactive Ion Etching (RIE).

A first metal film63including AlSiCu alloy is formed on the first insulating film25. The first metal film63is patterned into a prescribed shape by dry etching with resist masks (not shown). The dry etching may be RIE. Thereby, the first electrode films20C1,20C2, C20D1,20D2, and the second electrode films21C121C2,21D1,21D2are formed, while the first capacitor C1, the second capacitor C2, the first diode D1, and the second diode D2are formed.

Next, as shown inFIG. 20, a thick USG film64is formed on the first insulating film25, for example by CVD method. Next, the surface of the USG film64is planarized, for example by Chemical Mechanical Polishing (CMP). The thickness of the USG film64may be, for example, 20000 Å after planarization. Thus, the second insulating film26with a planarized surface is formed on the first insulating film25. The second insulating film26may be formed by repeating several times the formation of the USG film64and the planarization process using CMP method until the second insulation film26has a prescribed thickness. Also, the second insulating film26having a planarized surface may be formed by forming an SOG film in place of the USG film64or adding the SOG film to the USG film64.

In the forming process of the SOG film, an inorganic solvent including SiO2, or an organic solvent including SiO2is applied onto the base substrate60with the base substrate60rotating at a prescribed rotation speed. The solvent applied to the base substrate60is effected by a centrifugal force due to the rotation of the base substrate60, and is spread over the whole surface of the substrate60. Thereby, a solvent film with a substantially even thickness is formed on the surface of the base substrate60. Thereafter, a heat treatment is applied to the solvent film, the solvent film is cured (vitrification). In this way, the second insulating film26having a flat surface is formed.

Next, the resistor R is formed on the second insulating film26. In the formation process of the resistor R, first, a resistor film66composed of TION as a portion of a second metal film65is formed on the second insulating film26, for example by sputtering. Then, a conductor film67composed of AlCu as a portion of the second metal film65is formed on the resistor film66, for example by sputtering. Then, the resistor film66and the conductor film67are patterned by dry etching with resist masks (not shown). The dry etching may be RIE.

Next, the conductor film67covering the resistor film line52is selectively patterned by wet etching with resist masks (not shown). Thereby, the plurality of conductor films53is formed on the resistor film line52with a prescribed distance. Thus, the first electrode film20R, the second electrode film21R, and the resistive conductive film51are formed. The resistive conductive film51includes the resistor film line52, the conductor film53, the connection conductor film55and the fuse portion56(seeFIG. 7andFIG. 8).

Next, as shown inFIG. 21, the third insulating film27composed of a silicon nitride film is formed on the second insulating film26, for example by CVD method. Then, unnecessary portions of the second insulating film26and the third insulating film27are removed by dry etching with resist masks (not shown). Thereby, formed are a contact hole68that passes through the second insulating film26and the third insulating film27for selectively exposing the first metal film63, and a contact hole69that passes through the third insulating film27for selectively exposing the second metal film65.

A third metal film70composed of ALCu electrode film is formed on the third insulating film27to cover the third insulating film27by filling the contact holes68,69, for example, by sputtering. The third metal film70is patterned in a prescribed shape by wet etching with resist masks (not shown). Thereby, each pad electrode film4and each connection electrode film22,23are formed.

Next, as shown inFIG. 22, a cover film71is formed to cover the entire region of the third insulating film27, for example, by CVD method. The cover film71may be composed of a silicon nitride film. Then, the cover film71is selectively etched so as to expose a portion of the first electrode film20Rand a portion of the second electrode film21Rin the resistor forming region18. Then, the probe of a resistor measuring device is brought into contact with the first electrode film20Rand the second electrode film21Rto measure the resistance of the resistor R.

Next, laser light is radiated through the cover film71to fuse an arbitrary fuse portion56(seeFIG. 7andFIG. 8). Meanwhile, other regions except for the portions exposing the first electrode film20and the second electrode film21are covered with the cover film71, and thus connection failures such as short-circuit and so forth caused by fragments generated and adhered to other regions during fusing can be suppressed. Then, a silicon nitride film is repeatedly formed on the third insulating film27, for example, by CVD method, thereby increasing the thickness of the cover film71. Thus, the fourth insulating film28is formed on the third insulating film27.

Next, as shown inFIG. 23, a photosensitive polyimide is applied onto the fourth insulating film28to form a sealing resin30. The sealing resin30is exposed in a pattern corresponding to each pad electrode film4(also seeFIG. 2), and then developed. Thereby openings corresponding to each pad electrode film4are formed in the sealing resin30. Thereafter, heat treatment is applied to cure the sealing resin30as necessary. Next, unnecessary portions of the third insulating film27are removed by dry etching with the sealing resin30as a mask. Thereby, openings for exposing each pad electrode film4are formed in the third insulating film27. Next, the external terminals3(seeFIG. 1) are connected to each pad electrode film4.

Next, the base substrate60is selectively half etched to a prescribed depth from the front side toward the rear side, for example, by plasma etching. By this plasma etching, a groove partitioning a shape for forming the filter chip1in plan view is formed in the base substrate60. Then, the fifth insulating film29(seeFIG. 1) is formed on the inner surface of the groove, for example, by CVD method. Thereafter, the rear surface of the base substrate60is ground to communicate with the groove, for example, by CMP method. Thereby, each filter chip1is diced out from the base substrate60.

Second Embodiment

FIG. 24is a schematic plan view of a filter chip81according to a second embodiment of the present invention.FIG. 25is a circuit diagram of the filter chip81shown inFIG. 24.FIGS. 24, 25correspond to previously describedFIGS. 2, 3. The same reference numerals are applied to parts inFIGS. 24, 25corresponding to the parts illustrated in the previously describedFIGS. 2, 3, and the descriptions are omitted.

The filter chip81includes a first filter circuit forming region82including a first filter circuit FC11and a second filter circuit forming region83including a second filter circuit FC12. A single filter unit FU2is composed of the first filter circuit FC11and the second filter circuit FC12. The first filter circuit forming region82and the second filter circuit forming region83may include a coil forming region84where a coil L is formed in place of the above-described resistor forming region18. In this embodiment, the first capacitor forming region14, the second capacitor forming region16and the coil forming region84are formed as examples of the passive element forming regions according to the present invention.

A first electrode film20Land a second electrode film21Lare formed spaced apart from each other in place of the previously-described first electrode film20Rand the second electrode film21Rin the coil forming region84. The coil L is electrically connected to the input-side pad electrode film4avia the first electrode film20Land the first connection electrode film22L, and is electrically connected to the output-side pad electrode film4bvia the second electrode film21Land the second connection electrode film23L.FIG. 24shows an example where the first connection electrode film22Lis an electrode film integrally formed with the first connection electrode film22D1, and the second connection electrode film23Lis an electrode film integrally formed with the first connection electrode film22D2.

Referring toFIG. 25, the first filter circuit FC11and the second filter circuit FC12include a π type low pas filter85. The π type low pas filter85includes the coil L and the first capacitor C1and the second capacitor C2connected in parallel at both ends of the coil L. Thus, in the filter chip81, the single filter unit FU2is composed of the first filter circuit FC11and the second filter circuit FC12. Hereinafter, the specific configuration of the coil forming region84is described with reference toFIG. 26andFIG. 27.

FIG. 26is a cross-sectional view of the filter chip81shown inFIG. 24.FIG. 27is a plan view of the coil forming region84shown inFIG. 24.FIG. 26corresponds to the previously-describedFIG. 4. InFIG. 26, the same reference numerals are applied to parts corresponding to the parts shown in the previously-describedFIG. 4and so forth, and descriptions are omitted.

Referring toFIG. 26andFIG. 27, the first electrode film20Land the second electrode film21Lare formed spaced apart from each other on the first insulating film25in the coil forming region84. The coil L is formed in the region between the first electrode film20Land the second electrode film21L. More specifically, the coil L includes a coil conductor86formed in a spiral shape in plan view. The coil conductor86is formed in a rectangular spiral shape in plan view, and has a plurality of linear portions respectively parallel to each side surface2c,2dof the substrate2. The coil conductor86may be formed in a circular spiral shape in plan view or in a polygonal spiral shape in plan view other than a rectangular shape, such as an octagonal spiral shape in plan view.

The coil conductor86, more specifically, is embedded in a trench87formed in a spiral shape in plan view, etched to a prescribed depth from the element forming surface2aof the substrate2. The cross-section of the trench87is formed in an elongated rectangular shape in the thickness direction of the substrate2in relation to a cross-section in a direction orthogonal to the spiral direction of the trench87. A width X1of the trench87may be, for example, between 3 μm and 10 μm, inclusive. Further, a depth X2of the trench87may be, for example, between 10 μm and 100 μm, inclusive. An inner-surface insulating film88is formed on the inner surface of the trench87in the substrate2. The inner-surface insulating film88contains, for example, silicon oxide. In this embodiment, an entire wall sandwiched between the trenches87is formed as the inner-surface insulating film88, thereby forming an insulator portion89.

The coil conductor86may include a tungsten (W) film. Further, the coil conductor86may be a laminated film including a titanium nitride (Tin) film and a tungsten film. In this case, the titanium nitride (Tin) film is formed along the inner wall surface of the trench87. The thickness of the titanium nitride (Tin) film may be, for example, between 300 Å and 500 Å, inclusive. Meanwhile, the tungsten film is formed to fill a concave space partitioned by the titanium nitride film in the trench87.

The thin film portion25ais selectively formed on the first insulating film25in the coil forming region84. A plurality of input-side contact holes is formed in the thin film portion25aof the first insulating film25, for selectively exposing different portions of the coil conductor86spirally shaped in plan view as end parts near the first electrode film20L. Further, an output-side contact hole91is formed in the thin film portion25aof the first insulating film25for exposing an end part of the coil L near the second electrode film21L.

The first electrode film20Lintegrally includes a plurality of first extraction electrodes92extracted toward each input-side contact holes90, and fuse portions93integrally formed with the first extraction electrodes92, cuttably (fusibly) provided to electrically separate the coil conductor86from the first electrode film20L. Each first extraction electrode92enters each input-side contact hole90from above the first insulating film25, and is electrically connected to the coil conductor86in the input-side contact hole90.

Meanwhile the second electrode film21Lintegrally includes a second extraction electrode94extracted toward the output-side contact hole91. The second extraction electrode94enters the output-side contact hole91from above the first insulating film25, and is electrically connected to the coil conductor86in the output-side contact hole91.

The first electrode film20Land the second electrode film21Lare formed of the same material as the first electrode film20C1, D1and the second electrode film21C2, D2in the first capacitor forming region14and the first diode forming region15. The input-side pad electrode film4ais electrically connected to the first electrode film20Lvia the first connection electrode film22Land the contact42, and the output-side pad electrode film4bis electrically connected to the second electrode film21Lvia the second connection electrode film23Land the contact42.

FIG. 28is a circuit diagram illustrating the configuration of the coil L shown inFIG. 27. Referring toFIG. 28, by cutting other fuse portions93except for one fuse portion93selected, the number of windings of the coil L may be adjusted. Thereby, the inductance value of the coil L can be adjusted to a desired inductance value.

As described above, in this embodiment, the number of windings of the coil L can be adjusted by selectively cutting the fuse portions93. As such, the inductance value of the coil L can be adjusted to a desired inductance value, an error relative to a required inductance value of the coil L can be minimized.

Further, as a parameter representing the performance (quality) of the coil L, Q value (quality factor) of the coil L is used. The higher is Q value, the smaller loss becomes to provide excellent characteristics as a high frequency inductance. The Q value of the coil L is represented by the following expression:
Q=2πfL/RL(1)

In the above expression (1), f represents the frequency of a current flowing in the coil L; L represents the inductance of the coil L; and RLrepresents the internal resistance of the coil L. The coil L is configured so that the coil conductor86is embedded in the trench87formed in the substrate2to have a spiral shape in plan view. As such, the coil L can have a large cross-sectional area compared to a case where the coil L is formed of the coil conductor86on the element forming surface2aof the substrate2, and thus the internal resistance RLof the coil L can be reduced. Thereby, the Q value of the coil L can be improved. As a result, a filter chip81achieving favorable frequency characteristics can be provided.

In order to form a filter chip as described above, a trench87spirally shaped in plan view is formed in the base substrate60, for example, by etching with a resist mask prior to a step (the step shown inFIG. 17) of forming the first insulating film25on the base substrate60. Next, an inner-surface insulating film88(insulator portion89) is formed on the inner surface of the trench87, for example, by thermal oxidation. Next, a coil conductor86covering the element forming surface2aof the substrate2is formed by filling the trench87, for example, by sputtering.

Next, the unnecessary portions of the coil conductor86are etched back. Thereby, the coil conductor86is embedded in the trench87. Then, the first insulating film25, the first metal film63, and so forth are formed sequentially. Next, the first metal film63is patterned to form the first electrode film20Land the second electrode film21L. Next, after going through the same steps as the previously described cutting steps (FIG. 22) of the fuse portions56, the inductance value is adjusted by selectively cutting the fuse portions93. In this way, the coil L is formed. Thereafter, the filter chip81is formed by going through the same steps as the steps for the filter chip1.

Third Embodiment

FIG. 29is a plan view illustrating a first capacitor forming region14of a filter chip101according to a third embodiment of the present invention.FIG. 29corresponds to the previously mentionedFIG. 5. InFIG. 29, the same reference numerals are applied to the parts corresponding to the parts shown in the previously mentionedFIG. 5and so forth, and descriptions are omitted. The configuration of the second capacitor forming region16in the filter chip101is substantially the same as the configuration of the first capacitor forming region14, and thus, hereinafter, only the configuration of the first capacitor forming region14is described.

As shown inFIG. 29, a first capacitor C11is formed in the first capacitor forming region14in the filter chip101. The first capacitor C11includes an upper electrode37divided into two or more (six in this embodiment) electrode film portions102-107, and fuse portions108integrally formed with each electrode film portion102-107. Each electrode film portion102-107is formed in a rectangular shape in plan view, elongated in a belt-like shape from a first electrode film20C1to a second electrode film21C1.

Respective electrode film portions102-107face the impurity region38across the dielectric film35with mutually different facing areas. The facing areas of the respective electrode film portions102-107may form a geometric progression with geometric ratio of 1 or more. This embodiment shows an example where the facing areas of the respective electrode film portion102-107are 1:2:4:8:16:32 (geometric progression with geometric ration of 2). These electrode film portions102-107constitute a plurality of capacitor elements CE1-CE2.

The fuse portions108are provided between the respective electrode film portions102-107and the first electrode film20C1, electrically connecting the respective electrode film portions102-107with the first electrode film20C1. The fuse portions108integrally include a first wide-width portions109connected to the first electrode film20C1, a second wide-width portions110connected to the electrode film portions102-107, and a narrow-width portions111connected to the first wide-width portions109and the second wide-width portions110. The narrow-width portions111is formed to be narrower than the first wide-width portions109and the second wide-width portions110. By selectively cutting (fusing) the narrow-width portions111, the electrode film portions102-107can be electrically separated from the first electrode film20C1and the second electrode film21C1.

FIG. 30is a circuit diagram illustrating the configuration of the first capacitor C11shown inFIG. 29. As shown inFIG. 30, a plurality of capacitor elements CE1-CE6is connected in parallel between the first electrode film20C1and the second electrode film21C1. The fuse portions108are serially connected with respective capacitor elements

CE1-CE6. In a state where all of the fuse portions are not cut, the capacitance value of the first capacitor C11is equal to the value of the synthesized capacitance of the entire capacitor elements CE1-CE6. Whereas, in a state where the fuse portions108are selectively cut (melted), the capacitance value of the first capacitor C11decreases by the capacitance value of the capacitor elements CE1-CE6cut off.

As described above, by selectively and electrically separating the electrode film portions102-107from the external terminal3, the capacitance value of the first capacitor C11can be adjusted. Particularly, in this embodiment, the facing areas of the plurality of the electrode film portions102-107facing the lower electrode36are provided to form a geometric progression, and thus a capacitance value can be adjusted to a target capacitance value with the accuracy corresponding to the minimum capacitance value (the value of the first term of geometric progression).

Thereby, the capacitance value of the first capacitor C11can be adjusted to a desired capacitance value, and thus an error relative to a required capacitance value of the first capacitor C11can be minimized. As a result, the filter chip101having favorable frequency characteristics can be provided. Such a filter chip101can be formed, for example, only by changing the layout of masks used in patterning the first metal film63inFIG. 19and adding the same steps as the cutting steps of the above-described fuse portions56.

As above, a plurality of embodiments according to the present invention is described, however, the present invention can also be put into practice in still other embodiments.

For example, each of the previously described embodiments describes an example where the filter chip1,81,101includes a single filter unit, FU1, FU2. However, the filter chip1,81,101may include two or more filter units. In this case, as shown inFIG. 31, a filter chip121including two filter units FU1, FU2may be adopted, which is composed of two filter chips1,81,101with the longitudinal side surfaces2cjointly formed. Of course, a filter chip including the two filter units FU1, FU2may be adopted, composed of two filter chips1with the transversal side surfaces2djointly formed.

Further, as shown inFIG. 32, a filter chip122may be adopted, which includes four filter units FU1, FU2, composed of the two filter chips121with the transversal side surfaces thereof jointly formed. Further, as shownFIG. 33, a filter chip123may be adopted, which includes four filter units FU1, FU2, composed of the two filter chips121with the longitudinal side surfaces thereof jointly formed.

Each filter chip1,81,101,121,122,123with different sizes shown inFIG. 1andFIGS. 31-33can be concurrently manufactured in the same steps as the steps shown in the previously describedFIGS. 17-23. That is, it is enough to adjust the number of the chip manufacturing regions61partitioned by the groove when half etching the base substrate60by plasma etching. Thereby, each filter chip1,81,101,121,122,123with different sizes shown inFIG. 1andFIGS. 31-33can be concurrently manufactured after undergoing the rear-surface grinding of the base substrate60.

Further, in the previously described first embodiment, an example where the resistor R is formed on the second insulating film26is described. However, the resistor R may be formed on the substrate2, having contact with the substrate2, or may be formed on the first insulating film25, having contact with the first insulating film25.

Further, in the previously described second embodiment, an example where the coil L includes the coil conductor86embedded in the trench87is described. However, the coil conductor86may be formed on the substrate2, having contact with the substrate2, or may be formed on the first insulating film25, having contact with the first insulating film25. The coil conductor86may be formed on the second insulating film26, having contact with the second insulating film26.

Further, in each previously described embodiment, an example where the first capacitors C1, C11and the second capacitor C2include the impurity region38as the lower electrode36is described. However, the first capacitors C1, and the second capacitor C2may include the lower electrode36composed of a metal film in place of the impurity region38. The lower electrode36may be formed, for example, of the same material as the upper electrode37.

In this case, the first capacitors C1, C11and the second capacitor C2may be formed on the first insulating film25, having contact with the first insulating film25, or may be formed on the second insulating film26, having contact with the second insulating film26without having contact with the substrate2. Further, in this case, in the first capacitors C1, C11and the second capacitor C2, the lower electrode36including a plurality of electrode film portions similarly to the upper electrode37shown inFIG. 29may be formed.

Further, in the previously described first embodiment, an example is described, where the first filter circuit FC1and the second filter circuit FC2include the π type low-pass filter24formed by parallely connecting the first capacitor C1and the second capacitor C2at both ends of the resistor R. However, the π type high-pass filter may be formed by parallely connecting each resistor R at both ends of a single capacitor C1(C2).

Further, in the previously described second embodiment, an example is described, where the first filter circuit FC11and the second filter circuit FC12include the π type low-pass filter85formed by parallely connecting the first capacitor C1and the second capacitor C2at both ends of the resistor R. However, the π type high-pass filter may be formed by parallely connecting each coil L at both ends of a single capacitor C1(C2).

Further, the filter circuits applied to each filter chip1,81,101,121,122,123are not limited to the first filter circuits FC1, FC11and the second filter circuits FC2, FC12including the π type low-pass filters24,85or the π type high-pass filters. A various types of filter circuits as shown inFIGS. 34-37may be applied to each filter chip1,81,101,121,122,123.FIGS. 34-37are circuit diagrams illustrating an example of a filter circuit applied to each filter chip1,81,101,121,122,123.

Each filter circuit131-134shown inFIGS. 34-37includes a filter having a first passive element135, a second passive element136, and a third passive element137. Here, “passive elements” represent the above-described resistor R, the capacitors C1, C2, C11, and the coil L. At least two types or more passive elements selected from a group including the resistor R, the capacitors C1, C2, C11, and the coil L are applied to the first passive element135, the second passive element136, and the third passive element137.

In a filter circuit131shown inFIG. 34, a π type low-pass filter or a π type high-pass filter may be formed where the second passive element136and the third passive element137are parallely connected at both ends of the first passive element135.

In a filter circuit132shown inFIG. 35, a T type low-pass filter or a T type high-pass filter may be formed where the second passive element136is parallely connected to the connecting part between the first passive element135and the third passive element137.

In a filter circuit133shown inFIG. 36, an L type low-pass filter or an L type high-pass filter may be formed where the third passive element137is parallely connected to a series circuit including the first passive element135and the second passive element136. Of course, in the filter circuit133, the L type low-pass filter or the L type high-pass filter may be formed by parallely connecting the third passive element137only to the first passive element135in place of the series circuit composed of the first passive element135and the second passive element136.

In a filter circuit134shown inFIG. 37, the L type low-pass filter or the L type high-pass filter may be achieved where a series circuit including the second passive element136and the third passive element137is parallely connected to the first passive element135.

Of course, inFIGS. 34-37, a series circuit formed by a plurality of passive elements, a parallel circuit formed by a plurality of passive elements, or a circuit network combined by these series circuits and parallel circuits may be applied to the first passive element135, the second passive element136and the third passive element137. That is, a filter chip including a band-pass filter that passes only frequencies in a prescribed frequency range, or a band-stop filter that attenuates those in a prescribed range to very low levels may be created by including a series circuit and a parallel circuit composed of a plurality of passive elements.

Further in each previously described embodiment, the substrate2may be a silicon substrate (semiconductor substrate). A silicon substrate facilitates machining (trench formation, cutting of a base substrate60) compared to a ceramic substrate. For example, a silicon substrate facilitates the dicing of filter chips from the base substrate60by plasma etching. Particularly, plasma etching facilitates the dicing of filter chips of various sizes as shown inFIGS. 31-33from a single base substrate60while miniaturizing the chip size.

The previously described filter chip1,81,101121,122,123may be incorporated into an electronic device and a mobile terminal such as mobile electronic devices, for example, as a filter for a power circuit, a high-frequency circuit, a digital circuit and so forth. In this case, the electronic device may include a housing storing a circuit assembly having filter chip1,81,101121,122,123mounted thereon.

FIG. 38is a schematic plan view illustrating the configuration on a first insulating film25of a filter chip200according to a fourth variation.FIG. 39is an enlarged view of a region surrounded by dashed-dotted lines XXXIX inFIG. 38. InFIGS. 38, 39, the same reference numerals are applied to the configuration corresponding to the configuration described in the first embodiment, and the description is omitted.

Referring toFIG. 38, a filter chip200according to this variation is a chip part including the filter unit FU1that has the first filter circuit FC1and the second filter circuit FC2similarly to the previously described first embodiment.

In the filter chip200according to this variation, a pair of first input electrode films201(first electrode film) electrically connected to the pair of input terminals3a, a pair of first output electrode films202(second electrode film) electrically connected to the pair of output terminals3b, and a first ground electrode film203(reference potential electrode film) electrically connected to the ground terminals3care formed on the first insulating film25that is formed on the substrate2. The pair of first input electrode films201is respectively disposed right below the pair of input terminals3a; the pair of first output electrode films202is respectively disposed right below the pair of output terminals3b; and the first ground electrode film203is disposed right below the ground terminal3c.

The pair of first input electrode films201in this variation is formed in a rectangular shape in plan view having four sides parallel to the longitudinal side surfaces2cand the transversal side surfaces2dof the substrate2, and is formed spaced apart along the transversal side surface2dat one end of the substrate2(left side end inFIG. 38). The first output electrode films202is formed in a rectangular shape in plan view having four sides parallel to the longitudinal side surfaces2cand the transversal side surfaces2dof the substrate2, and is formed spaced apart along the transversal side surface2dat the other end of the substrate2(right side end inFIG. 38).

The first input electrode films201and the first output electrode films202are formed spaced apart from each other along the longitudinal side surface2cof the substrate2, facing each other along the element forming surface2a.

Hereinafter, a direction along which the first input electrode films201and the first output electrode films202face each other is simply referred to as “facing direction,” and a direction orthogonal to the facing direction is simply referred to as “orthogonal direction.” The facing direction is also a direction along the longitudinal side surface2cof the substrate2, and the orthogonal is also a direction along the transversal side surface2dof the substrate2.

The first ground electrode film203, in this variation, includes a first portion203aarranged in a region between the first input electrode films201and the first output electrode films202so as to cover the region between the first input electrode films201and the first output electrode films202. The first ground electrode film203also includes a second portion203barranged displaced from the first portion203ain a direction orthogonal to the facing direction so as to cover a region outside the region between the first input electrode film201and the first output electrode film202. In this embodiment, the first portion203aof the first ground electrode film203is formed as an extraction portion extracted from the second portion203bof the first ground electrode film203between the first input electrode films201and the first output electrode films202.

More specifically, the second portion203bof the first ground electrode film203is positioned in the region right below the ground terminal3c, that is, in the center region of the substrate2, and is formed in a rectangular shape in plan view having four sides parallel to the longitudinal side surface2cand the transversal side surface2d. The second portion203bof the first ground electrode film203has a portion facing a portion of the first input electrode films201and a portion of the first output electrode films202along the facing direction. The first portion203aof the first ground electrode film203is extracted from the second portion203btoward the region between the first input electrode film201and the first output electrode film202along the orthogonal direction, and is formed in a rectangular shape in plan view. In this embodiment, the first portion203ais a single electrode film extracted from the second portion203b.

The first portion203aof the first ground electrode film203is formed spaced apart from the

A removal region205rectangularly shaped in plan view, from which a portion of the electrode material of the first portion203ais removed, is selectively formed in the first portion203aof the first ground electrode film203. In this variation, the removal region205includes an opening extending along the orthogonal direction at the center in the width direction of the first portion203a. A ratio of the area that the removal region205occupies in the first portion203aof the first ground electrode film203is smaller than a ratio of the area that the region outside the removal region205occupies in the first portion203aof the first ground electrode film203. The specific function of this removal region205will be described later.

In the filter chip200according to this variation, similarly to the first embodiment, the first filter circuit forming region12and the second filter circuit forming region13are provided having the transversal line TL interposed therebetween, the transversal line TL traversing each intermediate portion of a pair of side surfaces2dalong the transversal direction. The configurations of the first filter circuit forming region12and the configurations of the second filter circuit forming region13are substantially same. Hereinafter, the configurations of the first filter circuit forming region12are described as an example, and the description of the configurations of the second filter circuit forming region13is omitted by putting the same reference numeral as that of the configuration of the first filter circuit forming region12to each configuration of the second filter circuit forming region13.

Referring toFIG. 39, the previously described first diode D1is formed in the surface part of the substrate2between the first input electrode film201and the first ground electrode film203and is electrically connected to the first input electrode film201and the first ground electrode film203. Further, the previously described second diode D2is formed in the surface part of the substrate2between the first output electrode film202and the first ground electrode film203and is electrically connected to the first output electrode film202and the first ground electrode film203. Similarly to the previously described first embodiment, both the first diode D1and the second diode D2form an overvoltage protection circuit for protecting the π type low-pass filter24from an overvoltage in the first filter circuit FC1(also seeFIG. 3and so forth).

In this variation, the first diode D1is formed in the region where a part of the second portion203bof the first ground electrode film203and a part of the first input electrode film201face each other and in the region where a part of the first portion203aof the first ground electrode film203and a part of the first input electrode film201face each other between the first input electrode film201and the first ground electrode film203.

The first diode D1includes the substrate2as a diffusion region including p-type impurities (first impurity region), and a plurality of n-type diffusion regions206A,206B (second impurity region) including n-type impurities formed in the surface part in the substrate2. The plurality of n-type diffusion regions206A,206B is formed spaced apart from each other in the orthogonal direction. The plurality of n-type diffusion regions206A,206B includes a plurality of first diffusion regions206A electrically connected to the first input electrode film201(input terminal3a), and a plurality of second diffusion regions206B electrically connected to the first ground electrode film203(ground terminal3c). The plurality of first diffusion regions206A and the plurality of second diffusion regions206B are alternately arranged along the orthogonal direction.

Both the plurality of n-type diffusion regions206A,206B are formed in a belt-like shape in plan view, extending along the facing direction between the first input electrode film201and the first output electrode film202, between the first input electrode film201and the first ground electrode film203. The plurality of n-type diffusion regions206A,206B is respectively formed to have substantially the same depth and substantially the same impurity concentration. Further, the plurality of n-type diffusion regions206A,206B is respectively formed in substantially the same shape in plan view.

That is, the widths of the plurality of n-type diffusion regions206A,206B are set equal to each other along the facing direction, and set equal to each other also along the orthogonal direction. The plurality of n-type diffusion regions206A,206B is the configuration element corresponding to the first plurality of diffusion regions45and the second plurality of diffusion regions46.

The first input electrode film201includes a plurality of first belt-like portions207extracted toward the first ground electrode film203to cover the plurality of first diffusion regions206A one by one. Further the first ground electrode film203includes a plurality of second belt-like portions208extracted toward the first input electrode film201to cover the plurality of second diffusion regions206B one by one. The first belt-like portions207of the first input electrode film201and the second belt-like portions208of the first ground electrode film203are formed in comb-like shapes to engage with each other.

Each first belt-like portion207of the first input electrode film201is formed in a rectangular shape in plan view, having a corner-notched tip, and is electrically connected to the first diffusion region206A via the first contact hole209formed in the first insulating film25. Further, each second belt-like portion208of the first ground electrode film203is formed in a rectangular shape in plan view, having a corner-notched tip, and is electrically connected to the first diffusion region206A via the second contact hole210formed in the first insulating film25.

Thus, the first diode D1includes a single bidirectional Zener diode integrally including a plurality of bidirectional Zener diode elements De1formed along the orthogonal direction. More specifically, the bidirectional Zener diode elements De1includes a first Zener diode Dz1and a second Zener diode Dz2formed adjacent to each other in the orthogonal direction. The first Zener diode Dz1is formed by a p-n junction between the substrate2and the first diffusion region206A. The second Zener diode Dz2is formed by a p-n junction between the substrate2and the second diffusion region2068. The first Zener diode Dz1and the second Zener diode Dz2are electrically connected to each other via the substrate2.

Meanwhile, in this variation, the second diode D2is formed in the region where a part of the second portion203bof the first ground electrode film203and a part of the first output electrode film202face each other and in the region where a part of the first portion203aof the first ground electrode film203and a part of the first output electrode film202face each other between the first output electrode film202and the first ground electrode film203.

The first diode D2includes the substrate2as a p-type diffusion region, and a plurality of n-type diffusion regions211A,211B including n-type impurities formed in the surface part in the substrate2. The plurality of n-type diffusion regions211A,211B is formed spaced apart from each other in the orthogonal direction. The plurality of n-type diffusion regions211A,211B includes a plurality of first diffusion regions211A electrically connected to the first output electrode film202(output terminal3a), and a plurality of second diffusion regions211B electrically connected to the first ground electrode film203(ground terminal3c). The plurality of first diffusion regions211A and the plurality of second diffusion regions211B are alternately arranged along the orthogonal direction. The plurality of n-type diffusion regions211A,211B is respectively formed to have substantially the same configuration with the plurality of n-type diffusion regions206A,206B in relation to the previously described first diode D1.

The first output electrode film202includes a plurality of first belt-like portions212extracted toward the first ground electrode film203to cover the plurality of first diffusion regions211A one by one. Further the first ground electrode film203includes a plurality of second belt-like portions213extracted toward the first output electrode film202to cover the plurality of second diffusion regions211B one by one. The first belt-like portions212of the first output electrode film202and the second belt-like portions213of the first ground electrode film203are formed in comb-like shapes to engage with each other.

Each first belt-like portion212of the first output electrode film202is formed in a rectangular shape in plan view, having a corner-notched tip, and is electrically connected to the first diffusion region211A via the first contact hole214formed in the first insulating film25. Further, each second belt-like portion213of the first ground electrode film203is formed in a rectangular shape in plan view, having a corner-notched tip, and is electrically connected to the first diffusion region211A via the second contact hole215formed in the first insulating film25.

Thus, similarly to the previously described first diode D1, the second diode D2includes a single bidirectional Zener diode integrally including a plurality of bidirectional Zener diode elements De1formed along the orthogonal direction. More specifically, the bidirectional Zener diode elements De1includes a first Zener diode Dz1and a second Zener diode Dz2formed adjacent to each other in the orthogonal direction. The first Zener diode Dz1is formed by a p-n junction between the substrate2and the first diffusion region211A. The second Zener diode Dz2is formed by a p-n junction between the substrate2and the second diffusion region211B. The first Zener diode Dz1and the second Zener diode Dz2are electrically connected to each other via the substrate2.

The first belt-like portion207of the first input electrode film201, the first belt-like portion212of the first output electrode film202, and the second belt-like portions208,213of the first ground electrode film203are also configuration elements corresponding to the first extraction electrode49and the second extraction electrode50in relation to the previously described first embodiment. Further, the first contact holes209,214and the second contact hole210,215are also configuration elements corresponding to the first contact hole47and the second contact hole48in relation to the previously described first embodiment. Although not shown here, similarly to the previously described first embodiment, the first insulating film25has the thin film portion25a(seeFIG. 4) in the portion where the first contact holes209and the second contact hole210are formed.

In the filter chip200according to this variation, the relatively wide first portion203aof the first ground electrode film203is arranged in the region between the first input electrode film201and the first output electrode film202. In the filter chip200according to this variation, the concentration of electric field in the first ground electrode film203is suppressed by such a configuration, and thus each electrostatic discharge tolerance of the first diode D1and the second diode D2can be improved. A filter chip220having a first ground electrode film203different in shape from the first ground electrode film203of the filter chip200according to this variation, is prepared as shown inFIG. 40to compare each electrostatic discharge tolerance of the first diode D1and the second diode D2of the filter chip200according to this variation with the electrostatic discharge tolerance of the diode in the filter chip220.

FIG. 40is an enlarged view of a region corresponding toFIG. 39, and a plan view illustrating the first ground electrode film203in the filter chip220according to a reference example. In the filter chip220according to the reference example, the first ground electrode film203includes a first extraction portion221and a second extraction portion222extracted from the second portion203binstead of the first portion203ain the region between the first input electrode film201and the first output electrode film202.

The first extraction portion221is extracted from the end of the second portion203bnear the first input electrode film201in a belt-like shape along the orthogonal direction. The width of the first extraction portion221along the facing direction is set to a value smaller than the width of one of second belt-like portions208in the first ground electrode film203along the orthogonal direction. Whereas, the second extraction portion222is extracted from the end of the second portion203bnear the first output electrode film202in a belt-like shape along the orthogonal direction. The width of the second extraction portion222along the facing direction is set to a value smaller than the width of one of second belt-like portions213in the first ground electrode film203along the orthogonal direction.

In the filter chip220according to the reference example, the first diode D1is formed in the surface part of the substrate2between the first input electrode film201and the first extraction portion221to electrically connecting the first input electrode film201and the first extraction portion221. Further, the second diode D2is formed in the surface part of the substrate2between the first output electrode film202and the second extraction portion222to electrically connecting the first output electrode film202and the second extraction portion222.

A relatively wide free space223formed in a rectangular shape in plan view is partitioned by the second portion203bof the first ground electrode film203, the first extraction portion221and the second extraction portion222in the region between the first input electrode film201and the first output electrode film202. A ratio of the area occupied by the free space223in plan view in the region between the first input electrode film201and the first output electrode film202is larger than a ratio of the area occupied by the first ground electrode film203in plan view in the region between the first input electrode film201and the first output electrode film202. Other configurations in the filter chip220according to the reference example is the same as those in the filter chip200according to this variation, and thus the description is omitted.

FIG. 41is a graph illustrating simulation results of the electrostatic discharge tolerance of the first diode D1when changing the number of bidirectional Zener diode elements De1in the filter chip200according to this variation and the filter chip220according to the reference example. AlthoughFIG. 41shows the simulation results of the electrostatic discharge tolerance of the first diode D1, it should be added that the results can also be applied to the second diode D2.

InFIG. 41, the vertical axis represents electrostatic discharge tolerances, and the horizontal axis represents the number of the bidirectional Zener diode elements De1.FIG. 41shows two lines L1, L2. The line L1represents the relationship between the number of the bidirectional Zener diode elements De1and electrostatic discharge tolerances of the filter chip220according to the reference example. The line L2represents the relationship between the number of the bidirectional Zener diode elements De1and electrostatic discharge tolerances of the filter chip200according to this variation.

With reference to the Lines L1, L2, it can be seen that the electrostatic discharge tolerance can be improved by increasing the number of the bidirectional Zener diode elements De1. It can also be seen that the filter chip200according to this variation can achieve an electrostatic discharge tolerance higher than the electrostatic discharge tolerance of the filter chip220according to the reference example.

This can be explained for the following reasons. That is, with reference toFIG. 40, in the case of the filter chip220according to the reference example, the width of the first extraction portion221along the facing direction and the width of the second extraction portion222along the facing direction are set to values smaller than the width of the second portion203bof the first ground electrode film203along the facing direction, and smaller than the width of the second belt-like portions208,213of the first ground electrode film203along the orthogonal direction. As such, when currents separately flowing in the plurality of second belt-like portions208are joined together at the first extraction portion221, current density sharply increases at the first extraction portion221. Further, when currents separately flowing in the plurality of second belt-like portions213are joined together at the second extraction portion222, current density sharply increases at the second extraction portion222.

As a result, electric field concentration takes place at the first extraction portion221and/or the second extraction portion222and the electrostatic discharge tolerance decreases. Such electric field concentration most likely takes place particularly at the joint between the second portion203bof the first ground electrode film203and the first extraction portion221, and at the joint between the second portion203bof the first ground electrode film203and the second extraction portion222.

As such, as shown in the filter chip200according to this variation, by securing a relatively wide current path with the first portion203ahaving a relatively wide width, currents can be prevented from concentrating locally at the ground electrode film203. Thereby, electric field concentration can be prevented from taking place at the joints of the first portion203aand the second portion203bof the first ground electrode film203, thus, the electrostatic discharge tolerance can be improved.

With reference toFIG. 39, the dimensions of the first ground electrode film203of the filter chip200according to this variation is specifically described. In the first ground electrode film203according to this variation, a width X of the first portion203aalong the facing direction is preferably set to a value greater than at least a width Y of the second belt-like portions208,213along the orthogonal direction.

More specifically, the width X of the first portion203aalong the facing direction is preferably set to a value at least greater than a total value of the width Y in the orthogonal direction of the plurality of second belt-like portions208disposed between the first portion203aand the first input electrode film201, or to a value greater than a total value of the width Y in the orthogonal direction of the plurality of second belt-like portions213disposed between the first portion203aand the first output electrode film202.

Furthermore specifically, the width X of the first portion203aalong the facing direction is preferably set to a value greater than a total value of the width Y in the orthogonal direction of the plurality of second belt-like portions208disposed between the first portion203aand the first input electrode film201, and the width Y in the orthogonal direction of the plurality of second belt-like portions213disposed between the first portion203aand the first output electrode film202.

In this way, by forming the first portion203awherein the width X in the facing direction is set to a value at least greater than the width Y of respective second belt-like portions208,213in the orthogonal direction, current density can be effectively prevented from sharply increasing at the first portion203awhen currents following in the plurality of second belt-like portions208,213are joined together at the first portion203a. Thereby, electric field concentration can be effectively prevented from taking place at the junctions of the first portion203aand the second portion203bof the first ground electrode film203, and thus the electrostatic discharge tolerance can be effectively improved.

Although this variation shows an example where the first portion203aof the first ground electrode film203is composed of a single electrode film, the first portion203aof the first ground electrode film203may be divided into a plurality of electrode film portions by the previously described removal region205and so forth. In this case, provided that the width of each electrode film portion along the facing direction is set to X, the width X of each electrode film portion is preferably set to a value greater than the width Y of the second belt-like portions208,213along the orthogonal direction, or to a value greater than the total value of width Y of the plurality of the second belt-like portions208,213along the orthogonal direction, as in the case of the previously described width X of the first portion203a.

In this variation,FIG. 42shows a change in electrostatic discharge tolerance of the first diode D1when the total perimeter of the plurality of n-type diffusion regions206A,206B is made to vary in the first diode D1.FIG. 42is a graph illustrating simulation results of the electrostatic discharge tolerance of the first diode D1when changing the total perimeter of the plurality of n-type diffusion regions206A,206B in the filter chip200according to the fourth variation shown inFIG. 4. AlthoughFIG. 42shows simulation results of the electrostatic discharge tolerance of the first diode D1, it should be added that the results can also be applied to the second diode D2.

InFIG. 42, the vertical axis represents electrostatic discharge tolerances and the horizontal axis represents the total perimeter of the plurality of n-type diffusion regions206A,206B. Here, by changing the number of the bidirectional Zener diode elements De1, the total perimeter of the plurality of n-type diffusion regions206A,206B is made to vary. Here, the total perimeter of the plurality of n-type diffusion regions206A,206B is defined as the total value of perimeters of each

n-type diffusion regions206A,206B with respect to the element forming surface2aof the substrate2.

Referring toFIG. 42, provided that the total perimeter of the plurality of n-type diffusion regions206A,206B is between 500 μm and 2000 μm, inclusive, it can be seen that the electrostatic discharge tolerance between 8 kV and 30 kV, inclusive, can be achieved. More specifically, provided that the total perimeter of the plurality of n-type diffusion regions206A,206B is 500 μm or greater, the electrostatic discharge tolerance no less than 8 kV can be achieved; provided that the total perimeter is 1000 μm or greater, the electrostatic discharge tolerance no less than 15 kV can be achieved; provided that the total perimeter is 1500 μm or greater, the electrostatic discharge tolerance no less than 25 kV can be achieved.

FIG. 43is a graph illustrating simulation results of the electrostatic discharge tolerance of the first diode when changing the total perimeter of the plurality of n-type diffusion regions206A,206B while the number of Zener diode elements De1is fixed in the filter chip200according to the fourth variation shown inFIG. 38. AlthoughFIG. 43shows simulation results of the electrostatic discharge tolerance of the first diode D1, it should be added that the results can also be applied to the second diode D2.

InFIG. 43, the vertical axis represents electrostatic discharge tolerances and the horizontal axis represents the total perimeter of the plurality of n-type diffusion regions206A,206B.FIG. 43shows electrostatic discharge tolerances, when the total perimeter of the plurality of n-type diffusion regions206A,206B is made to vary with the number of the bidirectional Zener diode elements De1set to 8. Further,FIG. 43shows electrostatic discharge tolerances, when the total perimeter of the plurality of n-type diffusion regions206A,206B is made to vary with the number of the bidirectional Zener diode elements De1set to 12.

Referring toFIG. 43, when the number of the bidirectional Zener diode elements De1is set to 8, and the total perimeter of the plurality of n-type diffusion regions206A,206B is approximately 550 μm, the electrostatic discharge tolerance is 11 KV. When the total perimeter of the plurality of n-type diffusion regions206A,206B is increased from approximately 550 μm to approximately 1100 μm, the electrostatic discharge tolerance is increased from 11 KV to 19 kV.

Further, when the number of the bidirectional Zener diode elements De1is set to 12, and the total perimeter of the plurality of n-type diffusion regions206A,206B is approximately 600 μm, the electrostatic discharge tolerance is 12 KV. When the total perimeter of the plurality of n-type diffusion regions206A,206B is increased from approximately 600 μm to approximately 1800 μm, the electrostatic discharge tolerance is increased from 12 KV to 27 kV.

When comparing the case where the number of the bidirectional Zener diode elements De1is 8, and the total perimeter of the plurality of n-type diffusion regions206A,206B is approximately 550 μm with the case where the number of the bidirectional Zener diode elements De1is 12, and the total perimeter of the plurality of n-type diffusion regions206A,206B is approximately 600 μm, there is not so much difference between these electrostatic discharge tolerances.

In contrast, when the total perimeter of the plurality of n-type diffusion regions206A,206B is increased, the electrostatic discharge tolerance is increased whether the number of the bidirectional Zener diode elements De1is 8 or 12. From this, it can be seen that the electrostatic discharge tolerance of the diode D1changes depending on the total perimeter of the plurality of n-type diffusion regions206A,206B rather than the number of the bidirectional Zener diode elements De1.

From the simulation results shown inFIGS. 41-43, it can be seen that the first diode D1is preferably designed so that the total perimeter of the plurality of n-type diffusion regions206A,206B is 500 μm or greater, 1000 μm or greater, or 1500 μm or greater, and the number of the bidirectional Zener diode elements De1is no less than 8 or no less than 12. According to this design, a favorable electrostatic discharge tolerance can be achieved.

Thus, the filter chip200according to this variation, the first ground electrode film203is formed in the region between the first input electrode film201and the first output electrode film202to cover the region therebetween. As such, the first ground electrode film203allows the region between the first input electrode film201and the first output electrode film202to provide a relatively wide current path, and thus even if a current flows into the first ground electrode film203from either one or both of the first diode D1and the second diode D2, currents can be prevented from concentrating locally at the ground electrode film203. Therefore, the occurrence of electric field concentration at the first ground electrode film203can be favorably suppressed, and thus the filter chip200capable of improving voltage resistance can be provided.

Next, with reference toFIGS. 44, 45, the configuration of the second insulating film26covering the first insulating film25is described.FIG. 44is a schematic plan view illustrating the configuration on the second insulating film26in the filter chip200shown inFIG. 38.FIG. 45is an enlarged view of a region surrounded by dashed-dotted lines XLV inFIG. 44.

Referring toFIGS. 44, 45, the second insulating film26according to this variation is formed on the first insulating film25to cover the entire region of the first input electrode film201, the first output electrode film202and the first ground electrode film203. A pair of second input electrode films231(third electrode film) electrically connected to the previously described pair of input terminals3a, a pair of second output electrode films232(fourth electrode film) electrically connected to the previously described pair of output terminals3b, and a second ground electrode film233electrically connected to the previously described ground terminal3care formed on the second insulating film26. The pair of second input electrode films231is disposed right below the pair of input terminals3a; the pair of second output electrode films232is disposed right below the pair of output terminals3b; and the second ground electrode film233is disposed right below the ground terminal3c.

The pair of second input electrode films231in this variation is formed in a rectangular shape in plan view having four sides parallel to the longitudinal side surfaces2cand the transversal side surfaces2dof the substrate2, and is formed spaced apart along the transversal side surface2dat one end of the substrate2(left side end inFIG. 38). Each second input electrode film231is disposed right above the previously described first input electrode film201. The pair of second output electrode films232in this variation is formed in a rectangular shape in plan view having four sides parallel to the longitudinal side surfaces2cand the transversal side surfaces2dof the substrate2, and is formed spaced apart along the transversal side surface2dat the other end of the substrate2(right side end inFIG. 38). Each second output electrode film232is disposed right above the previously described first output electrode film202.

The second ground electrode films233in this variation is formed in a rectangular shape in plan view having four sides parallel to the longitudinal side surfaces2cand the transversal side surfaces2dof the substrate2. The second ground electrode films233in this variation is disposed in the center region of the substrate2in plan view, that is, right above the second portion203bof the previously described first ground electrode film203. The second ground electrode films233faces the second input electrode film231and the second output electrode film232along the direction of the element forming surface2aof the substrate2.

Each second input electrode film231is electrically connected to the first input electrode film201right therebelow via a first contact hole234formed in the second insulating film26. Also, each second output electrode film232is electrically connected to the first output electrode film202right therebelow via a second contact hole235formed in the second insulating film26. Further, the second ground electrode films233is electrically connected to the first ground electrode film203right therebelow via a third contact hole236formed in the second insulating film26.

The configurations of the first filter circuit forming region12and the configurations of the second filter circuit forming region13are substantially same even on the second insulating film26. Hereinafter, the configurations of the first filter circuit forming region12are described as an example, and the description of the configurations of the second filter circuit forming region13is omitted by putting the same reference numeral as that of the configuration of the first filter circuit forming region12to each configuration of the second filter circuit forming region13.

In the first filter circuit forming region12, the second input electrode film231and the second output electrode film232are formed spaced apart from each other along the longitudinal side surfaces2cof the substrate2and along the element forming surface2aof the substrate2.

Referring toFIG. 45, the resistor R is formed on the second insulating film26positioned between the second input electrode film231and the second output electrode film232, including a resistive conductive film240electrically connected to the second input electrode film231and the second output electrode film232. The resistive conductive film240in this variation is formed in the region partitioned by the second input electrode film231, the second output electrode film232and the second ground electrode film233, in the region between the second input electrode film231and the second output electrode film232.

The resistive conductive film240is formed at a position overlapping the first ground electrode film203in plan view. The resistive conductive film240includes a first pattern243having a plurality of first resistor film lines241formed on the second insulating film26and a plurality of first conductor films242formed spaced apart from each other on the plurality of first resistor film lines241. Further, the resistive conductive film240includes a second pattern246having a plurality of second resistor film lines244formed on the second insulating film26and a plurality of second conductor films245formed spaced apart from each other on the plurality of second resistor film lines244.

Further, the resistive conductive film240according to this variation includes a fuse portion247cuttably provided to electrically connect a portion of the resistive conductive film240to the second input electrode film231and the second output electrode film232or to electrically separate a portion of the resistive conductive film240from the second input electrode film231and the second output electrode film232. More specifically, the fuse portion247is positioned between the first pattern243and the second pattern246to separatably connect the first pattern243and the second pattern246. The first pattern243and the second pattern246are connected in series with the fuse portion247interposed therebetween.

The configuration of the first resistor film line241and the first conductor film242in relation to the first pattern243and the configuration of the second resistor film line244and the second conductor film245in relation to the second pattern246are configuration elements corresponding to the resistor film line52and the conductor film53in the previously described first embodiment. Each configuration of the first resistor film line241and the first conductor film242in relation to the first pattern243and each configuration of the second resistor film line244and the second conductor film245in relation to the second pattern246are substantially the same as each configuration of

the resistor film line52and the conductor film53in the previously described first embodiment except that aspects of formation and connection are different, and therefore the specific descriptions are omitted.

In the resistive conductive film240, by selectively cutting the fuse portion247, a portion of the first pattern243can be electrically connected to the second input electrode film231and the second output electrode film232, or a portion of the first pattern243can be electrically separated from the second input electrode film231and the second output electrode film232. Further, in

the resistive conductive film240, by selectively cutting the fuse portion247, a portion of the second pattern246can be electrically connected to the second input electrode film231and the second output electrode film232, or a portion of the second pattern246can be electrically separated from the second input electrode film231and the second output electrode film232. In this way, the resistive conductive film240is configured to easily provide a wide range of resistance values from several ohms to several thousands of ohms.

Next, referring toFIGS. 46, 47together, the arrangement of the fuse portion247of the resistive conductive film240is further specifically described.FIG. 46is a vertical cross-sectional view along line XLVI-XLVI inFIG. 45, illustrating a state where the fuse portion247is not cut.FIG. 47is a vertical cross-sectional view of a portion corresponding toFIG. 46, illustrating a state where the fuse portion247is cut.

Referring toFIG. 46, the second insulating film26is formed to fill the removal region205which is formed in the first portion203aof the first ground electrode film203to thus cover the first portion203aof the first ground electrode film203. The fuse portion247of the resistive conductive film240is disposed at a position overlapping the previously described removal region205in plan view which is formed in the first portion203aof the first ground electrode film203.

Referring toFIG. 47, when the fuse portion247is melted by laser irradiation, since the first portion203aof the first ground electrode film203does not exist in the region right below the fuse portion247, the first portion203acan be effectively prevented from being melted by the laser irradiation. Thereby, the area in plan view of the first portion203aof the first ground electrode film203can be effectively prevented from being reduced by the melting of the first portion203a, and thus the unwanted increase in the density of current that flows in the first portion203acan be favorably avoided. Further, the previously described third insulating film27is formed on the second insulating film26so as to fill the melted portion248of the fuse portion247after the fuse portion247is melted, and thus a favorable insulating state between the first pattern243and the second pattern246can be maintained.

The first input electrode film201according to this variation is a configuration element corresponding to the first electrode film20D1according to the previously described first embodiment; the first output electrode film202according to this variation is a configuration element corresponding to the first electrode film20D2according to the previously described first embodiment; and the first ground electrode film203according to this variation is a configuration element corresponding to the second electrode films21D2,21D2according to the previously described first embodiment. Further, the second input electrode film231according to this variation is a configuration element corresponding to the first electrode film20Raccording to the previously described first embodiment; and the second output electrode film232according to this variation is a configuration element corresponding to the second electrode film21Raccording to the previously described first embodiment.

Further, in this variation, the previously described first capacitor C1is formed on the element forming surface2aof the substrate2between the first input electrode film201and the first ground electrode film203so as to be electrically connected to the first input electrode film201and the first ground electrode film203via the first electrode film20C1and the second electrode film20C2. Further, the previously described second capacitor C2is formed on the element forming surface2aof the substrate2between the first output electrode film202and the first ground electrode film203so as to be electrically connected to the first output electrode film202and the first ground electrode film203via the first electrode film20C1and the second electrode film20C2.

It is to be understood that variations and modifications will be apparent to those skilled in the art without departing from the scope and spirit of the present invention. The following Features can be extracted from the specification and the drawings (FIGS. 38-47):

Item 1: A chip part including a substrate; a first electrode film and a second electrode film formed on the substrate spaced apart from each other so as to face each other in a direction along the surface of the substrate; a reference electrode film that covers a region between the first electrode film and the second electrode film, and is formed on the substrate so as to face the first electrode film and the second electrode film with a distance therebetween in a direction along the surface of the substrate; and a diode formed in the surface part of the substrate, interposed between at least either the first electrode film or the second electrode film and the reference electrode film, and electrically connected to the at least one electrode film and the reference electrode film.

In this chip part, the reference electrode film is formed in a region between the first electrode film and the second electrode film so as to cover the region between the first electrode film and the second electrode film. Therefore, the reference electrode film allows a relatively wide current path to be formed in the region between the first electrode film and the second electrode film, and thus even if electrical currents flow into the reference electrode film, such electrical currents can be prevented from concentrating locally at the reference electrode film. Thus, the occurrence of electric field concentration at the reference electrode film can be favorably suppressed, and thus a chip part capable of improving voltage resistance can be provided.

Item 2: A chip part described in item 1 wherein the reference electrode film covers a region outside the region between the first electrode film and the second electrode film in addition to the region between the first electrode film and the second electrode film.

Item 3: A chip part described in item 1 or 2, wherein the reference electrode film includes a first portion disposed in a region between the first electrode film and the second electrode film so as to cover the region between the first electrode film and the second electrode film, and a second portion disposed in a region outside the region

between the first electrode film and the second electrode film, and the diode is formed in the surface part of the substrate between the at least one electrode film and the first portion of the reference electrode film.

Item 4: A chip part described in any one of items 1-3, wherein the diode includes a first impurity region of a first conductivity type formed in the surface part of the substrate, and a plurality of second impurity regions of a second conductivity type formed in the surface part of the first impurity region, arranged spaced apart from each other along a direction orthogonal to the facing direction between the first electrode film and the second electrode film.

Item 5: A chip part described in item 4, wherein the at least one electrode film includes a first belt-like portion extracted in a belt-like shape in plan view toward the reference electrode film so as to cover at least one of the plurality of second impurity regions, and the reference electrode film includes a second belt-like portion extracted toward the at least one electrode film so as to cover at least one second impurity region not covered by the first belt-like portion.

Item 6: A chip part described in item 5, wherein the at least one electrode film includes a plurality of the first belt-like portions extracted to cover a part of the plurality of second impurity regions, and the reference electrode film includes a plurality of the second belt-like portions extracted to cover a part of the plurality of second impurity regions, wherein the first belt-like portions of the at least one electrode film and the second belt-like portions of the reference electrode film are formed in a comb-like shape to engage with each other.

Item 7: A chip part described in any one of items 4-6, wherein the diode includes a first Zener diode formed by a p-n junction between the first impurity region and the second impurity region electrically connected to the at least one electrode film, and a second Zener diode formed by a p-n junction between the first impurity region and the second impurity region electrically connected to the reference electrode film and electrically connected to the first Zener diode via the first impurity region.

Item 8: A chip part described in item 7, wherein the diode includes a bidirectional Zener diode element formed along the orthogonal direction, and the bidirectional Zener diode element includes a pair of the first Zener diode and the second Zener diode formed adjacent to each other along the orthogonal direction.

Item 9: A chip part described in item 8, wherein eight or more of the bidirectional Zener diode elements are formed along the orthogonal direction.

Item 10: A chip part described in any one of items 4-9, wherein in the diode, the total perimeter of the plurality of second impurity regions defined by the total value of the perimeter of each second impurity region with respect to the surface of the substrate is 500 μm or greater.

Item 11: A chip part described in any one of items 1-10, wherein the electrostatic discharge tolerance of the diode is 8 kV or greater.

Item 12: A chip part described in any one of items 1-11, wherein a low-pass filter circuit is formed between the first electrode film and the second electrode film, the diode forms an overvoltage protection circuit for protecting the low-pass filter from an overvoltage.

Item 13: A chip part described in any one of items 1-12, further including an insulating film formed on the substrate so as to cover at least the reference electrode film, a third electrode film and a fourth electrode film formed on the insulating film spaced apart from each other, facing each other in a direction along the surface of the substrate, and a resistive conductive film formed on the insulating film to be electrically connected to the third electrode film and the fourth electrode film.

Item 14: A chip part described in item 13, wherein the resistive conductive film is formed to overlap the reference electrode film in plan view.

Item 15: A chip part described in 13 or 14, the resistive conductive film has a fuse portion cuttably provided to electrically connect a part of the resistive conductive film to the third electrode film and the fourth electrode film, or to electrically separate a part of the resistive conductive film from the third electrode film and the fourth electrode film.

Item 16: A chip part described in item 15, wherein a removal region from which a part of the electrode material of the reference electrode film is removed is selectively formed in the reference electrode film; the insulating film fills the removal region and covers the reference electrode film; and the fuse portion of the resistive conductive film is disposed at a position overlapping the removal region of the reference electrode film in plan view.

Item 17: A chip part described in item 16, wherein a ratio of the area that the removal region occupies in the reference electrode film in plan view is smaller than a ratio of the area that a region outside the removal region occupies in the reference electrode film in plan view.

Item 18: A chip part described in any one of items 15-17, wherein the resistive conductive film includes a first pattern including a first resistor film formed on the insulating film and a plurality of first conductor films formed spaced apart from each other on the first resistor film, and a second pattern including a second resistor film formed on the insulating film and a plurality of second conductor films formed spaced apart from each other on the second resistor film, wherein the first pattern and the second pattern are electrically connected to each other via the fuse portion.

Item 19: A chip part described in any one of items 13-18, wherein the third electrode film is electrically connected to the first electrode film via a first contact hole formed in the insulating film; the fourth electrode film is electrically connected to the second electrode film via a second contact hole formed in the insulating film; and the diode and the resistive conductive film are electrically connected to each other.