Semiconductor device and method for fabricating the same

The invention provides a semiconductor device, including: a substrate of a first conductivity type having an active region and a termination region; an epitaxial layer of the first conductivity type over the substrate; a plurality of first trenches and second trenches in the epitaxial layer; an implant blocker layer formed at bottoms of the first and second trenches; a liner of a second conductivity type different from the first conductivity type conformally formed along sidewalls of the first and second trenches; a dielectric material filled in the first and second trenches defining a plurality of first columns and a plurality second column, respectively; a gate dielectric layer over the epitaxial layer; two floating gates formed on the gate dielectric layer; a source region; an inter-layer dielectric layer; and a contact plug formed on the source region.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device, and in particular, relates to a super junction semiconductor device

2. Description of the Related Art

There is a large demand for energy saving electronic devices since eco-friendly products and green technology have been advocated in recent years. To meet the growing need for such devices, semiconductor industries are moving towards a more energy-conscious perspective. Super junction metal-oxide-semiconductor field effect transistors (MOSFETs) that provide improved energy efficiency has accordingly been developed. Compared to the conventional planar MOSFET structures, super junction MOSFETs are capable of reducing the on-resistance to a very low degree without affecting the voltage tolerance of the devices. As the result, a MOSFET with a lower on-resistance per unit area can be produced.

A typical super junction MOSFET device includes two regions, an active region (also referred to as cell region) and a termination region. The termination region of a super junction MOSFET device is designed to sustain the transverse electric potential voltage in the device. When the potential voltage sustained by the termination region is small, there is a large electric field generated in vertical and horizontal directions in the device. Accordingly, the termination region of the device easily breaks down.

Therefore, an improved super junction device is needed.

BRIEF SUMMARY OF THE INVENTION

An exemplary embodiment provides a semiconductor device, including: a substrate of a first conductivity type having an active region and a termination region an epitaxial layer of the first conductivity type over the substrate; a plurality of first trenches in the epitaxial layer of the active region; a plurality of second trenches in the epitaxial layer of the termination region; an implant blocker layer formed at bottoms of the first and second trenches; a liner of a second conductivity type different from the first conductivity type conformally formed along sidewalls of the first and second trenches; a dielectric material filled in the first and second trenches defining a plurality of first columns and a plurality second column, respectively; a gate dielectric layer over the epitaxial layer; two floating gates formed on the gate dielectric layer over opposite sides of a first column which is farthest away from the termination region; a source region formed between the floating gates; an inter-layer dielectric layer covering the gate dielectric layer and the floating gates; and a contact plug formed on the source region through the inter-layer dielectric layer.

Another exemplary embodiment provides a method for fabricating a semiconductor device, comprising; providing a substrate of a first conductivity type, wherein the substrate has an active region and a termination region; forming an epitaxial layer of the first conductivity type over the substrate; forming a plurality of first trenches in the epitaxial layer of the active region; forming a plurality of second trenches in the epitaxial layer of the termination region; forming an implant blocker layer at bottoms of the first and second trenches; forming a liner conformally on sidewalls of the first and second trenches; implanting a dopant of a second conductivity type into the liner, wherein the first and second conductivity types are different, and wherein the implant blocker layer blocks the dopant from entering into the bottoms of the first and second trenches; filling a dielectric material into the first and second trenches to form a plurality of first columns and a plurality second column, respectively; forming a gate dielectric layer over the epitaxial layer; forming two floating gates on the gate dielectric layer over opposite sides of a first column which is farthest away from the termination region; forming a source region between the floating gates; forming an inter-layer dielectric layer covering the gate dielectric layer and the floating gates; and forming a contact plug on the source through the inter-layer dielectric.

DETAILED DESCRIPTION OF THE INVENTION

The present invention will be described with respect to particular embodiments and with reference to certain drawings, but the invention is not limited thereto and is only limited by the claims The drawings described are only schematic and are non-limiting. In the drawings, the size of some of the elements may be exaggerated and not drawn to scale for illustrative purposes. The dimensions and the relative dimensions do not correspond to actual dimensions to practice the invention.

FIGS. 1-13are cross-sectional views illustrating the flowchart of a method for forming a super junction semiconductor device in accordance with embodiments of the present disclosure.

Referring toFIG. 1, a substrate100of a first conductivity is provided. The substrate100has an active region100aand a termination region100badjacent to the active region100a. The substrate100may be a bulk silicon substrate, silicon-on-insulator (SOI) substrate, or the like. In addition, other suitable substrates may also be used, such as a multi-layered substrate, gradient substrate, hybrid orientation substrate, or the like. In some embodiments, the substrate100may have a first conductivity type of p-type, such as a boron doped substrate. In other embodiments, the substrate100may have a first conductivity type of n-type, such as a phosphor or arsenic substrate. Any other suitable substrates may also be used. In one embodiment, the substrate100is a heavily doped n-type (N+) substrate.

Referring toFIG. 2, an epitaxial layer102of the first conductivity type is formed on the substrate100. The substrate100has a doping concentration larger than that of the epitaxial layer102. For example, when the first conductivity type is n-type, the substrate100may be a heavily doped n-type (N+) substrate100, while the epitaxial layer102may be a lightly doped n-type (N−) epitaxial layer. The epitaxial layer102may be formed by epitaxial growth to a thickness ranging from 1 to 100 μm depend on the device range.

After the epitaxial layer102is formed, a process for forming a plurality of trenches in the epitaxial layer102is performed. Referring toFIG. 3, a plurality of first trenches104are formed in the epitaxial layer102of the active region100a, and a plurality of second trenches106are formed in the epitaxial layer102of the termination region100b. The first and the second trenches104and106may be formed by lithography and etching processes. In some embodiments, the distance between the first and the second trenches104and106may vary from active region100ato termination region100b. For example, the distance between the first and the second trenches104and106may increase from active region100ato termination region100b. In particular, the distance a is smaller than the distance b, the distance b is smaller than the distance c, the distance c is smaller than the distance d, and the distance d is smaller than the distance e. However, in other embodiments, the distance between the first and the second trenches104and106are the same.

After the formation of the first and the second trenches, an implant blocker is formed in the first and the second trenches104and106.FIGS. 4A-4Dillustrates the steps for forming an implant blocker layer108in accordance to an embodiment. Referring toFIG. 4A, a first oxide layer108A, a nitride layer108B, and a second oxide layer108C are sequentially formed conformally over the epitaxial layer102. The thickness ratio between the first oxide layer108A, the nitride layer108B, and the second oxide layer108C is about 1-10:1-10:1-50. The first and second oxide layer108A and108C may include silicon oxide, tetraethyl orthosilicate (TEOS) oxide, or combinations thereof, and the nitride layer108B may include silicon nitride, or silicon oxynitride or combinations thereof. In one embodiment, the first oxide layer108A is a silicon oxide layer, the nitride layer108B a silicon nitride layer, and the second oxide layer is a TEOS oxide layer. The layers108A,108B, and108C may be formed by a deposition process, such as chemical vapor deposition (CVD) or be thermally grown by oxidation or nitridation processes. After the layers108A,108B, and108C are formed, a mask layer210is formed to completely fill the first and the second trenches104and106that expose the surface of the second oxide layer108C, as shown inFIG. 4B. Referring toFIG. 4C, portions of the first oxide layer108A, the nitride layer108B, and the second oxide layer108C that are not covered by the mask layer210are removed. The removal method may be a wet etching process. After the step inFIG. 4C, the mask layer210is removed, the remaining portions of the first oxide layer108A, the nitride layer108B, and the second oxide layer108C form the implant blocker layer108, as shown inFIG. 4D. In this embodiment, the implant blocker layer108does not directly contact the sidewalls of the trenches104and106. The bottom sidewalls of the trenches104and106are exposed. The overall thickness of the implant blocker layer108varies in between 1000 A to 5000 A. In one embodiment, the overall thickness of the implant blocker layer108is about 2000 A.

FIG. 4D′ illustrates a cross-sectional view of the implant blocker layer108in accordance to another embodiment. In the embodiment ofFIG. 4D′, a first oxide layer108A′, a nitride layer108B′, and a second oxide layer108C′ are formed directly at the bottom of the first and second trenches104and106by, for example, a high density plasma chemical vapor deposition (HDPCVD) process. In the embodiment, the removal process as shown inFIGS. 4A-4Cis not required since the layers108A′,108B′ and108C′ are directly formed only in the trenches104and106, and an implant blocker layer108′, which is formed by the layers108A′,108B′ and108C′, covers the sidewalls at the bottoms of the first and second trenches104and106. The thickness ratio between the first oxide layer108A′, the nitride layer108B′, and the second oxide layer108C′ is about 1-10:1-10:1-50. The overall thickness of the implant blocker layer108′ varies in between 1000 A to 5000 A. In one embodiment, the overall thickness of the implant blocker layer108′ is about 2000 A.

Although the implant blocker layer108illustrated inFIG. 4DandFIG. 4D′ is an oxide-nitride-oxide composite layer, it should be noted that the implant blocker layer may include other configurations, such as a nitride-oxide-nitride composite layer, a nitride-oxide composite layer, or an oxide-oxynitride-oxide composite layer. In the following, the implant blocker layer108′ shown inFIG. 4D′ will be used as an illustrative example for further description.

After the formation of the implant blocker layer108′, a liner110is formed conformally over the epitaxial layer102, as shown inFIG. 5. The liner110may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride or other suitable materials. It should be noted that although the steps illustrated inFIG. 5is performed on the implant blocker layer108′ shown inFIG. 4D′, however, the steps inFIG. 5may also be performed on the implant blocker layer108shown inFIG. 4D. In the embodiments of forming the liner110on the implant blocker layer108as shown inFIG. 4D, the liner110is also formed on the sidewalls and the bottoms of the trenches104and106that are not covered by the implant blocker layer108. The liner110may have a thickness of about 100-500 A.

Referring toFIG. 6, following the steps ofFIG. 5, an implant process300is performed to implant a dopant of a second conductivity type at an angle into the liner110on the sidewalls of the trenches104and106. The first and the second conductivity types are different. For example, when the first conductivity is n-type, the second conductivity type is p-type. In the step of performing the implant process300, the implant blocker layer108′ blocks the dopant from entering into the bottoms of the first and second trenches104and106.

Referring toFIG. 7, after the liner110is implanted with the dopant of the second conductivity type, a dielectric material is filled into the first and second trenches104and106, thereby forming a plurality of first columns112and a plurality of second columns114, respectively. The dielectric material may be silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, other suitable dielectric materials, or combinations thereof. The method for filling the dielectric material may include a deposition process and a CMP process. The deposition process may include CVD. The CMP process may also removes the portion of the liner110beyond the epitaxial layer102.

After the formation of the gate dielectric layer116, two floating gates118are formed on the gate dielectric layer over opposite sides of a first column112in the active region100athat is farthest away from the termination region100b, as shown inFIG. 9. The floating gates118may be formed of a material comprising metal, polysilicon, tungsten silicide (WSi2), or combinations thereof. The floating gates118may be formed using a process such as low-pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), other suitable processes, or combinations thereof. In addition, a plurality of floating gates120may also be simultaneously formed over the gate dielectric layer116of the termination region100b, wherein the floating gates120covers a portion of the second columns114and a portion of the epitaxial layer102in the termination region100b, as shown inFIG. 9. The material and the formation method of the floating gates120are similar to the floating gates118, and hence is not discussed herein to avoid repetition.

Following the steps inFIG. 9, a source region122is formed in the epitaxial layer102between the floating gates118, as shown inFIG. 10. The source region122may be formed by a doping process commonly used in the art, such as an ion implantation process.

Referring toFIG. 11, an inter-layer dielectric (ILD) layer124is formed after the formation of the source region122. The ILD124may be formed covering the gate dielectric layer116and the float gates118and120with a contact hole124aexposing the source region122.

After the step inFIG. 11, a process for forming a contact plug is performed to complete the formation of the super junction device. Referring toFIG. 12, a contact plug126extending through the contact hole124aof the ILD layer124is formed on the source region122, to complete the formation of the super junction device1000. It should be noted that although the super junction device inFIG. 12is manufactured from the structure shown inFIG. 4D′, the super junction device may also be manufactured from the structure shown inFIG. 4Das shown inFIG. 13. In the embodiments of manufacturing the super junction device from the structure shown inFIG. 4D, the liner110is formed on the sidewalls and the bottoms of the trenches104and106that are not covered by the implant blocker layer108′, as shown inFIG. 13.

The invention utilizes an implant blocker layer108or108′ to prevent the termination region of the super junction device from losing potential voltage caused by the diffusion of the implanted dopant in the liner110into the bottoms of the second trenches106, thereby mitigating the generation of the electric field at the bottom of trench in the termination region of the super junction device that normally occurs in a conventional super junction device. Without high electric field at the bottom of trench in the termination region, the breakdown problem in the termination region of a super junction device can be effectively eliminated.