Bandgap reference circuitry

Bandgap reference circuitry comprises a first current mirror connected to a power supply line and configured to supply a first current to a first node and a second current to a second node virtually-shorted to the first node, a first pn junction element between the first node and a ground line; a first variable resistor element between the second node and the ground line, and a second pn junction element connected in series to the first variable resistor element. The first variable resistor element has a resistance dependent on a power supply voltage supplied to the power supply line.

CROSS REFERENCE

This application claims priority to Japanese Patent Application No. 2017-211132, filed on Oct. 31, 2017, the disclosure of which is incorporated herein by reference in its entirety.

TECHNICAL FIELD

The present disclosure relates to bandgap reference circuitry.

BACKGROUND

Bandgap reference circuitry, which makes use of the temperature dependence of the current-voltage property of a pn junction to generate an output voltage stable against the temperature, is widely used for semiconductor integrated circuits.

In general, the output voltage of bandgap reference circuitry is considerably stable against disturbance; however, the output voltage may be slightly dependent on the power supply voltage, depending on the configuration of the bandgap reference circuitry.

SUMMARY

In one or more embodiments, bandgap reference circuitry comprises a current mirror connected to a power supply line and configured to supply a first current to a first node and supply a second current to a second node virtually-shorted to the first node, a first pn junction element between the first node and a ground line, a variable resistor element between the second node and the ground line, and a second pn junction element connected in series to the variable resistor element. The variable resistor element has a resistance dependent on a power supply voltage supplied to the power supply line.

In one or more embodiments, bandgap reference circuitry comprises a variable resistor element having a resistance dependent on a power supply voltage supplied to a power supply line, a current mirror connected to the power supply line, a first pn junction element between the first node and a ground line, a second pn junction element between the second node and the ground line, and a first resistor element connected in series to the second pn junction. The current mirror is configured to supply a first current to a first node and supply a second current to a second node virtually-shorted to the first node via the variable resistor element.

In one or more embodiments, bandgap reference circuitry comprises a current mirror connected to a power supply line, and supply a third current to an output node, a first pn junction element between the first node and a ground line, a second pn junction element between the second node and the ground line, a first resistor element connected in series to the second pn junction element, and a variable resistor element between the output node and the ground line. The variable resistor element having a resistance dependent on a power supply voltage supplied to the power supply line. The current mirror is configured to supply a first current to a first node, supply a second current to a second node virtually-shorted to the first node.

DETAILED DESCRIPTION

In the following, a description is given of various embodiments of the present disclosure with reference to the attached drawings. Note that same or similar components may be denoted by same or corresponding reference numerals in the following description.

In one or more embodiments, as illustrated inFIG. 1, bandgap reference circuitry100comprises a power supply line11, a ground line12, a current mirror13, an operational amplifier14, resistor elements R1, R2, R3, a variable resistor element R4, and bipolar transistors Q1and Q2. In one embodiment, the power supply line11is supplied with a power supply voltage Vcc, and the ground line12is grounded.

In one or more embodiments, the current mirror is connected to the power supply line11and configured to output first and second currents I1and I2. The first and second currents I1and I2may have the same current level. In one or more embodiments, the current mirror13comprises a pair of PMOS transistors MP1and MP2. The PMOS transistors MP1and MP2may have commonly connected gates, and the sources thereof may be commonly connected to the power supply line11. Further, the drain of the PMOS transistor MP1may be connected to a first node N1via a resistor element R1, and the drain of the PMOS transistor MP2may be connected to a second node N2via a resistor element R2. The drain of the PMOS transistor MP1may be used as a first output configured to output the first current I1, and the drain of the PMOS transistor MP2may be used as a second output configured to output the second current I2. In one or more embodiments, the resistor elements R1and R2are designed to have the same resistance.

In one or more embodiments, the operational amplifier14comprises a first input connected to the first node N1, a second input connected to the second node N2, and an output connected to the gates of the PMOS transistors MP1and MP2. The first input may be a non-inverting input, and the second input may be an inverting input. In one or more embodiments, the operational amplifier14is configured to output a control voltage to the current mirror13to control the first and second currents I1and I2. The operational amplifier14may be configured to supply the control voltage to the gates of the PMOS transistors MP1and MP2. In one or more embodiments, the operational amplifier14is configured to control the potential on the gates of the PMOS transistors MP1and MP2so that the nodes N1and N2have the same potential. In one or more embodiments, the first and second nodes N1and N2are virtually-shorted through the above operation of the operational amplifier14. In one or more embodiments, the current mirror13and the operational amplifier14operate together as current supply circuitry configured to control the nodes N1and N2to the same potential and supply currents of the same current level to the nodes N1and N2.

In one or more embodiments, the bipolar transistor Q1is diode-connected to operate as a first pn junction element incorporating a pn junction. In one or more embodiments, an NPN transistor is used as the bipolar transistor Q1. The bipolar transistor Q1may have an emitter connected to the ground line12, and a collector and base may be commonly connected to the first node N1. The first current I1may flow through the pn junction formed between the base and the emitter of the bipolar transistor Q1in the forward direction.

In one or more embodiments, the bipolar transistor Q2, the resistor element R3, and the variable resistor element R4are connected in series between the second node N2and the ground line12. InFIG. 1, the variable resistor element R4is denoted by the legend “R4(Vcc)” to indicate that the resistance of the variable resistor element R4is dependent on the power supply voltage Vcc. In one or more embodiments, the order in which the bipolar transistor Q2, the resistor element R3, and the variable resistor element R4are connected is interchangeable.

In one or more embodiments, bipolar transistor Q2is diode-connected to operate as a second pn junction element, similarly to the bipolar transistor Q1. In one or more embodiments, an NPN transistor is used as the bipolar transistor Q2. The area of the base-emitter junction of the bipolar transistor element Q2may be N times as large as that of the base-emitter junction of the bipolar transistor element Q1, where N is a number larger than 1. In one or more embodiments, the bipolar transistor Q2has an emitter connected to the ground line12, and a collector and a base are commonly connected to the second node N2via the resistor element R3and the variable resistor element R4. The second current I2may flow through the pn junction between the base and emitter of the bipolar transistor Q2.

In various embodiments, the diode-connected PNP transistors may be used as the bipolar transistors Q1and Q2.

In one or more embodiments, parasitic bipolar transistors formed together with MOS transistors may be used as the bipolar transistors Q1and Q2. This configuration facilitates integration of the bandgap reference circuitry100into a MOS transistor-based integrated circuit.

Other elements including a pn junction may be used in place of the diode-connected bipolar transistors Q1and Q2. For example, in one or more embodiments, diodes including a well formed in a semiconductor substrate and a diffusion layer formed in the well may be used in place of the bipolar transistors Q1and Q2. Alternatively, diode-connected MOS transistors may be used in place of the diode-connected bipolar transistors Q1and Q2.

In one or more embodiments, the variable resistor element R4has a resistance dependent on the power supply voltage Vcc supplied to the power supply line11. In one or more embodiments, as illustrated inFIG. 2, an NMOS transistor MN1having a gate to which the power supply voltage Vcc is supplied may be used as the variable resistor element R4. The on-resistance of the NMOS transistor MN1, which has the gate configured to receive the power supply voltage Vcc, may depend on the power supply voltage Vcc, and this property allows the NMOS transistor MN1to be used as the variable resistor element R4. In this case, the resistance of the variable resistor element R4decreases as the power supply voltage Vcc is increased. A bias voltage generated from the power supply voltage Vcc for example through voltage dividing may be supplied to the gate of the NMOS transistor MN1used as the variable resistor element R4, in place of the power supply voltage Vcc. In alternative embodiments, a PMOS transistor may be used as the variable resistor element R4.

In one or more embodiments, the output voltage Vout of the bandgap reference circuitry100is outputted from an output node Nout configured to connect the drain of the PMOS transistor MP2and the resistor element R2. In this configuration, the output voltage Vout is generated as the sum of the base-emitter voltage VBE2of the bipolar transistor Q2and the voltage drops across the resistor elements R2, R3and the variable resistor element R4. As discussed later in detail, the second current I2, which flows through the resistor elements R2, R3and the variable resistor element R4, may have a positive temperature dependence against the absolute temperature T, while the base-emitter voltage VBE2of the bipolar transistor Q2may have a negative temperature dependence against the absolute temperature T. This effectively reduces the temperature dependence of the output voltage Vout of the bandgap reference circuitry100against the absolute temperature T. Further, in various embodiments, the bandgap reference circuitry100operates to generate the output voltage Vout as described in the following.

In one or more embodiments, the first and second currents I1and I2, which are supplied to the first and second nodes N1and N2, respectively, have current levels proportional to the absolute temperature due to the effect of the bipolar transistors Q1, Q2, the resistor element R3and the variable resistor element R4. In this case, the bipolar transistors Q1, Q2, the resistor element R3, and the variable resistor element R4may be collectively referred to as PTAT (proportional to absolute temperature) current generator circuitry15.

More specifically, when the first and second currents I1and I2are controlled to have the same current level I by the current mirror13, for example, the following expressions (1a) and (1b) may hold for the base-emitter voltage VBE1of the bipolar transistor Q1and the base-emitter voltage VBE2of the bipolar transistor Q2, on the basis that the area of the base-emitter junction of the bipolar transistor Q2may be N times as large as that of the base-emitter junction of the bipolar transistor Q1:

VBE⁢⁢1=k⁢⁢Tq⁢ln⁡(IIS)(1⁢a)VBE⁢⁢2=k⁢⁢Tq⁢ln⁡(IIS·1N)(1⁢b)
where Isis the backward saturation current, k is the Boltzmann constant, T is the absolute temperature, and q is the elementary charge.

Since the first and second nodes N1and N2may be virtually-shorted and the voltage on the node N2may be equal to the base-emitter voltage VBE1of the bipolar transistor Q1, the following expression (2) may hold:

I=VBE⁢⁢1-VBE⁢⁢2R⁢⁢3+R⁢⁢4⁢(Vcc)(2)
where R4(Vcc) is the resistance of the variable resistor element R4and dependent on the power supply voltage Vcc.

The current level I of the currents I1and I2may be represented by the following expression (3), which is obtained by substituting expressions (1a) and (1b) into expression (2):

I=Vt·ln⁡(N)R⁢⁢3+R⁢⁢4⁢(Vcc)(3)
where Vt is the thermal voltage given by the following expression (4):

The current level I of the currents I1and I2may be proportional to the absolute temperature T. Since the current I2increases proportionally to the absolute temperature T, the voltage drops across the resistor elements R2, R3and the variable resistor elements R4also increase proportionally to the absolute temperature T.

The output voltage Vout, which is the sum of the voltage drops across the resistor elements R2, R3and the variable resistor element R4and the base-emitter voltage VBE2of the bipolar transistor Q2, may be represented, for example, by the following expression (5):

Additionally, as is understood from expression (5), the dependence of the output voltage Vout on the power supply voltage Vcc can be reduced by selecting the property of the variable resistor element R4in accordance with the dependence of the output voltage Vout on the power supply voltage Vcc for the case where the variable resistor element R4is not provided. In one or more embodiments, when the variable resistor element R4is not provided, the output voltage Vout increases as the power supply voltage Vcc is increased. In such cases, the dependence of the output voltage Vout on the power supply voltage Vcc can be reduced by using a variable resistor element R4configured to have a resistance that increases as the power supply voltage Vcc is increased. When the output voltage Vout decreases as the power supply voltage Vcc is increased for the case where the variable resistor element R4is not provided, in contrast, the dependence of the output voltage Vout on the power supply voltage Vcc can be reduced by using a variable resistor element R4configured to have a resistance that decreases as the power supply voltage Vcc is increased.

In one or more embodiments, as illustrated inFIG. 3, bandgap reference circuitry100is configured similarly to the one illustrated inFIG. 1, except that PTAT current generator circuitry16does not incorporate the variable resistor element R4and that the bandgap reference circuitry100comprises a variable resistor element R5connected in series to the resistor element R2between the output node Nout and the second node N2.

An NMOS transistor having a gate to which the power supply voltage Vcc is supplied may be used as the variable resistor element R5, as is the case with the variable resistor element R4(also seeFIG. 2). In this case, the resistance of the variable resistor element R5decreases as the power supply voltage Vcc is increased. A bias voltage generated from the power supply voltage Vcc, for example through voltage dividing, may be supplied to the gate of the NMOS transistor used as the variable resistor element R5, in place of the power supply voltage Vcc. In alternative embodiments, a PMOS transistor may be used as the variable resistor element R5. In one or more embodiments, the positions of the resistor elements R2and the variable resistor element R5are interchangeable.

In the configuration illustrated inFIG. 3, the voltage on the second node N2may be equal to the base-emitter voltage VBE1of the bipolar transistor Q1, and accordingly the following expression (6) may hold:

I=VBE⁢⁢1-VBE⁢⁢2R⁢⁢3(6)
Therefore, the current level I of the currents I1and I2may be obtained by the following expression (7):

The output voltage Vout may be the sum of the voltage drops across the resistor element R2, the variable resistor element R5and the resistor element R3and the base-emitter voltage VBE2of the bipolar transistor Q2as is represented for example by the following expression (8):

In one or more embodiments, the property of the variable resistor element R5may be selected so that the dependence of the output voltage Vout on the power supply voltage Vcc is reduced in accordance with the dependence of the output voltage Vout on the power supply voltage Vcc for the case where the variable resistor element R5is not provided. In various embodiments, when the variable resistor element R5is not provided, the output voltage Vout increases as the power supply voltage Vcc is increased. For example, the dependence of the output voltage Vout on the power supply voltage Vcc can be reduced by using the variable resistor element R5configured to have a resistance that decreases as the power supply voltage Vcc is increased. When the output voltage Vout decreases as the power supply voltage Vcc is increased for the case where the variable resistor element R5is not provided, in contrast, the dependence of the output voltage Vout on the power supply voltage Vcc can be reduced by using a variable resistor element R5configured to have a resistance that increases as the power supply voltage Vcc is increased.

In one or more embodiments, as illustrated inFIG. 4, bandgap reference circuitry100is configured similarly to the one illustrated inFIG. 3, except that the bandgap reference circuitry100comprises another variable resistor element R5connected in series to the resistor element R1between the first node N1and the drain of the PMOS transistor MP1, in addition to the variable resistor element R5connected in series to the resistor element R2between the second node N2and the drain of MP2. This circuit configuration is more symmetric and effectively reduces the difference between the current levels of the first and second currents I1and I2potentially caused by the Early effect of the PMOS transistors MP1and MP2. In one or more embodiments, the positions of the resistor element R1and the variable resistor element R5are interchangeable.

In one or more embodiments, as illustrated inFIG. 5, bandgap reference circuitry100is configured as a combination of the configuration illustrated inFIG. 1and that illustrated inFIG. 4. The bandgap reference circuitry100illustrated inFIG. 5comprises the PTAT current generator circuitry15that incorporates the variable resistor element R4. Additionally, the resistor element R1and the variable resistor element R5are connected in series between the first node N1and the drain of the PMOS transistor MP1, and the resistor element R2and another variable resistor element R5are connected in series between the second node N2and the drain of the PMOS transistor MP2.

In the configuration illustrated inFIG. 5, the output voltage Vout, which is the sum of the voltage drops across the resistor element R2, the variable resistor element R5, the variable resistor element R4and the resistor element R3and the base-emitter voltage VBE2of the bipolar transistor Q2, may be represented, for example, by the following expression (9):

In one or more embodiments, N, R2, R3, R4(Vcc) and R5(Vcc) are adjusted so as to make the generated output voltage Vout less dependent on the temperature or free from the temperature dependence, on the basis of expression (9).

The properties of the variable resistor elements R4and R5may be selected so as to reduce the dependence of the output voltage Vout on the power supply voltage Vcc, in accordance with the dependence of the output voltage Vout on the power supply voltage Vcc in the embodiment where the variable resistor elements R4and R5are not provided.

In one or more embodiments, as illustrated inFIG. 6, bandgap reference circuitry200comprises a power supply line21, a ground line22, a current mirror23, an operational amplifier24, resistor elements R3, R6, R7and R8, a variable resistor element R4and bipolar transistors Q1and Q2. Further, in one embodiment, the power supply line21is supplied with the power supply voltage Vcc, and the ground line22is grounded.

In one embodiment, the current mirror23is configured to output first and second currents I1and I2. The first and second currents I1and I2may have the same current level. Additionally, the current mirror23may be configured to output a third current I0having a current level proportional to that of the first and second currents I1and I2. In one or more embodiments, the current mirror23may be configured to output the third current I0so that the third current I0has the same current level as that of the first and second currents I1and I2. In one or more embodiments, the current mirror23may comprise PMOS transistors MP0, MP1and MP2. The PMOS transistors MP0, MP1and MP2may have commonly-connected gates, and the sources thereof may be commonly connected to the power supply line21. The drain of the PMOS transistor MP1may be connected to a first node N1, and the drain of the PMOS transistor MP2may be connected to a second node N2. The drain of the PMOS transistor MP0is connected to an output node Nout.

In various embodiments, the operational amplifier24has a first input connected to the first node N1, a second input connected to the second node N2, and an output connected to the gates of the PMOS transistors MP1and MP2. The first input may be a non-inverting input, and the second input may be an inverting input. In one or more embodiments, the operational amplifier24is configured to output a control voltage to the gates of the PMOS transistors MP1, MP2and MP0of the current mirror23to control the first, second and third currents I1, I2and I0. Further, the operational amplifier24may control the potential of the gates of the PMOS transistors MP1and MP2so that the first and second nodes N1and N2have the same potential. In one or more embodiments, the nodes N1and N2are virtually-shorted through the above operation of the operational amplifier24. In one or more embodiments, the current mirror23and the operational amplifier24operate together as current supply circuitry configured to control the nodes N1and N2to the same potential and supply currents of the same current level to the nodes N1and N2.

In one or more embodiments, the bipolar transistors Q1, Q2, the resistor element R3and the variable resistor element R4operates as PTAT current generator circuitry25, similarly to the case of the bandgap reference circuitry100illustrated inFIG. 1. The bipolar transistor Q1is connected between the node N1and the ground line22. The resistor element R3, the bipolar transistor Q2and the variable resistor element R4are connected in series between the node N1and the ground line22. The area of the base-emitter junction of the bipolar transistor Q2may be N times as large as that of the base-emitter junction of the bipolar transistor Q1. In one or more embodiments, the order in which the resistor element R3, the bipolar transistor Q2and the variable resistor element R4are connected is interchangeable.

As is illustrated, in one embodiment, the resistor element R6is connected in parallel to the bipolar transistor Q1between the node N1and the ground line22, and the resistor element R7is connected in parallel to the resistor element R3. Further, the bipolar transistor Q2and the variable resistor element R4are connected between the node N2and the ground line22. In one or more embodiments, the resistor elements R6and R7are designed to have the same resistance.

In one or more embodiments, the resistor element R8is connected between the output node Nout and the ground line22. The resistor element R8may configured to generate an output voltage Vout from the current I0supplied to the output node Nout.

The bandgap reference circuitry200may be configured to generate the output voltage Vout so that the temperature dependence of the output voltage Vout is reduced. The current I1Aflowing through the bipolar transistor Q1and the current I2Aflowing through the resistor element R3, the bipolar transistor Q2and the variable resistor element R4may both be a PTAT current having a positive temperature dependence. Further, the current I1Bflowing through the resistor element R6and the current I2Bflowing through the resistor element R7may both be a CTAT (complementary to absolute temperature) current having a negative temperature dependence. Since the current I1is the sum current of the currents I1Aand I1Band the current I2is the sum current of the currents I2Aand I2B, the temperature dependences of the currents I1and I2is reduced.

Accordingly, in one or more embodiments, the temperature dependence of the current I0, which is generated through mirroring of the currents I1and I2, is also reduced. Further, as the output voltage Vout may be generated through a voltage drop across the resistor element R8caused by the current I0, the temperature dependence of the output voltage Vout is also reduced.

In one or more embodiments, the current I2supplied to the node N2is the sum current of the currents I2Aand I2Band the following expression (10) holds:
I2=I2A+I2B(10)

Since the nodes N1and N2are virtually-shorted, the potential on the node N2may be equal to the base-emitter voltage VBE1of the bipolar transistor Q1, and accordingly the currents I2Aand I2Bmay be represented by the following expressions (11a) and (11b):

From expressions (1a) and (1b), which represent the base-emitter voltages VBE1and VBE2, and expressions (10), (11a) and (11b), the current I2may be represented by the following expression (12):

When the current mirror23is configured to output the current I0so that the current I0has the same current level as that of the current I2, the output voltage Vout may be represented, for example, by the following expression (13):

Since the thermal temperature Vt has a positive temperature dependence and increases proportionally to the temperature while the base-emitter voltage VBE1has a negative temperature dependence, the temperature dependence of the output voltage Vout may be effectively reduced by appropriately adjusting N, R2, R3, R4(Vcc) and R7, as is understood from expression (13).

Additionally, in one or more embodiments, the dependence of the output voltage Vout on the power supply voltage Vcc may also be reduced by selecting the property of the variable resistor element R4, in accordance with the dependence of the output voltage Vout on the power supply voltage Vcc in an embodiment where the variable resistor element R4is not provided.

In one or more embodiments, as illustrated inFIG. 7, bandgap reference circuitry200is configured similarly to the one illustrated inFIG. 6, except that PTAT current generator circuitry26does not incorporate the variable resistor element R4, while current-voltage converter circuitry27is connected between the output node Nout and the ground line22. The current-voltage converter circuitry27comprises the resistor element R8and the variable resistor element R5which are serially connected.

In the bandgap reference circuitry200illustrated inFIG. 7, the current I2may be represented, for example, by the following expression (14):

Accordingly, the output voltage Vout may be represented, for example, by the following expression (15):

As may be understood from expression (15), the temperature dependence of the output voltage Vout may be reduced by appropriately adjusting N, R2, R3and R7.

Additionally, in one or more embodiments, the dependence of the output voltage Vout on the power supply voltage Vcc may be also reduced by appropriately selecting the property of the variable resistor element R5in accordance with the dependence of the output voltage Vout on the power supply voltage Vcc in an embodiment where the variable resistor element R5is not provided.

In one or more embodiments, as illustrated inFIG. 8, bandgap reference circuitry200is configured as a combination of the configuration illustrated inFIG. 6and that illustrated inFIG. 7. In the configuration illustrated inFIG. 8, PTAT current generator circuitry25incorporates the variable resistor element R4. Additionally, current-voltage converter circuitry27is connected between the output node Nout and the ground line22. The current-voltage converter circuitry27includes the resistor element R8and the variable resistor element R5which are connected in series.

In the configuration illustrated inFIG. 8, the output voltage Vout may be represented, for example, by the following expression (16):

In one or more embodiments, N, R3, R4(Vcc) and R7are adjusted so as to make the generated output voltage Vout less dependent on the temperature or free from the temperature dependence, on the basis of expression (16).

The properties of the variable resistor elements R4and R5are adjusted so as to reduce the dependence of the output voltage Vout on the power supply voltage Vcc, in accordance with the dependence of the output voltage Vout on the power supply voltage Vcc when the variable resistor elements R4and R5are not provided.

In one or more embodiments, as illustrated inFIG. 9, bandgap reference circuitry300comprises a power supply line31, a ground line32, a current mirror33, first and second operational amplifiers34-1and34-2, a resistor element R3, a variable resistor element R4, bipolar transistors Q1, Q2, Q3and one embodiment, the power supply line31is supplied with the power supply voltage Vcc, and the ground line32is grounded.

In one or more embodiments, the current mirror is configured to output first and second currents I1and I2, third current I0, and fourth current I3. The currents I0, I1, I2and I3may have the same current level. In various embodiments, the current mirror33comprises PMOS transistors MP0, MP1, MP2and MP3. The PMOS transistors MP0, MP1, MP2and MP3may have commonly-connected gates, and the sources thereof may be commonly connected to the power supply line31. Further the drains of the PMOS transistors MP1, MP2and MP3may be connected to the first, second and third nodes N1, N2and N3, respectively, and the drain of the PMOS transistor MP0may be connected to the output node Nout.

In one or more embodiments, the bipolar transistors Q1, Q2and Q3operate as first, second and third pn junction elements, respectively, each incorporating a pn junction. In one or more embodiments, NPN transistors are used as the bipolar transistors Q1, Q2and Q3. The bases of the bipolar transistors Q1, Q2and Q3may be commonly connected to the collector of the bipolar transistor Q3. The collectors of the bipolar transistors Q1, Q2and Q3may be connected to the first, second and third nodes N1, N2and N3, respectively. In one or more embodiments, the emitters of the bipolar transistors Q1and Q3are connected to the ground line32, and the emitter of the bipolar transistor Q2is connected to the ground line32via the resistor element R3and the variable resistor element R4. The above connections allow the first, second, and fourth currents I1, I2and I3to flow through the base-emitter pn junctions of the bipolar transistors Q1, Q2and Q3, respectively, in the forward directions.

In one or more embodiments, the base-emitter junctions of the bipolar transistors Q1and Q3have the same area. Further, the area of the base-emitter junction of the bipolar transistor Q2may be N times as large as that of the base-emitter junctions of the bipolar transistors Q1and Q3, where N is a number larger than 1.

In various embodiments, the first operational amplifier34-1has a first input connected to the first node N1, a second input connected to the second node N2, and an output connected to the gates of the PMOS transistors MP0, MP1, MP2and MP3. The first input may be an inverting input, and the second input may be a non-inverting input. The first operational amplifier34-1may output a control voltage to the gates of the PMOS transistors MP1and MP2of the current mirror33to control the first and second currents I1and I2.

In one or more embodiments, the second operational amplifier34-2has a first input connected to the first node N1, a second input connected to the third node N3, and an output connected to the bases of the bipolar transistors Q1, Q2and Q3. The first input may be a non-inverting input, and the second input may be an inverting input. The second operational amplifier34-2may output a control voltage to the bases of the bipolar transistors Q1, Q2and Q3to control the first and third currents I1and I3.

In various embodiments, the first and second operational amplifiers34-1and34-2are configured to control the potential on the gates of the PMOS transistors MP1, MP2and MP3and the potential on the bases of the bipolar transistors Q1, Q2and Q3so that the first, second and third nodes N1, N2and N3have the same potential. In one or more embodiments, the first, second and third nodes N1, N2and N3are virtually-shorted through the above operation of the first and second operational amplifiers34-1and34-2. In one or more embodiments, the current mirror33and the operational amplifiers34-1and34-2collectively operate as current supply circuitry configured to control the nodes N1, N2and N3to the same potential and supply currents of the same current level to the nodes N1, N2and N3.

The current-voltage converter circuitry36may generate the output voltage Vout from the third current I0received from the current mirror33. In one or more embodiments, the current-voltage converter circuitry36comprises a diode-connected bipolar transistor Q0and resistor elements R9and R10. Further, the base-emitter junction of the bipolar transistor Q0may have the same area as that of the base-emitter junctions of the bipolar transistors Q1and Q3. The bipolar transistor Q0and the resistor element R9may be connected in series between the output node Nout and the ground line32. In various embodiments, the positions of the bipolar transistor Q0and the resistor element R9are interchangeable. In one embodiment, the resistor element R10is connected between the output node Nout and the ground line32in parallel to the bipolar transistor Q0and the resistor element R9.

In one or more embodiments, the bandgap reference circuitry300illustrated inFIG. 10is configured to generate an output voltage Vout with reduced temperature dependence in accordance with the principle described in the following. The first current I1, which flows through the bipolar transistor Q1, and the second current I2, which flows through the bipolar transistor Q2, the resistor element R3and the variable resistor element R4, are both PTAT currents having positive temperature dependence. In such an embodiment, the bipolar transistors Q1, Q2, the resistor element R3and the variable resistor element R4may be collectively referred to as PTAT current generator circuitry35.

The third current I0supplied to the current-voltage converter circuitry36may also be a PTAT current, since the current I0has the same current level I as the currents I1and I2. The current-voltage converter circuitry36may be configured to divide the third current I0into a current I0Ahaving a positive temperature dependence and a current I0Bhaving a reduced temperature dependence, and output a voltage generated across the resistor element R10by the current I0Bas the output voltage Vout. Accordingly, the bandgap reference circuitry300may reduce the temperature dependence of the output voltage Vout. In various embodiments, the bandgap reference circuitry300generates the output voltage Vout as described in the following.

In the configuration illustrated inFIG. 9, and in one or more embodiments, the first, second and third currents I1, I2and I0have the same current level I, which may be represented by the following expression (17):

I=Vt·ln⁡(N)R⁢⁢3+R⁢⁢4⁢(Vcc)(17)
Since the third current I0has the same current level I as the first and second currents I1and I2and is generated as the sum current of the current I0Aflowing through the bipolar transistor Q0and the resistor element R9and the current I0Bflowing through the resistor element R10, the following expression (18) holds:
I0=I=I0A+I0B(18)

With respect to the base-emitter voltage VBE0of the bipolar transistor Q0and the voltage drops across the resistor elements R9and R10, the following expression (19) holds:
VBE0+I0A·R9=I0B·R10   (19)

From expressions (17) to (19), the current I0Bmay be represented by the following expression (20):

The output voltage Vout may be represented, for example, by the following expression (21):

Since the thermal voltage Vt has a positive temperature dependence and increases proportionally to the temperature while the base-emitter voltage VBE0has a negative temperature dependence, the temperature dependence of the output voltage Vout can be effectively reduced by appropriately adjusting N, R3, R4(Vcc) and R9.

Additionally, as is understood from expression (21), the dependence of the output voltage Vout on the power supply voltage Vcc can be also reduced by appropriately selecting the property of the variable resistor element R4in accordance with the dependence of the output voltage Vout on the power supply voltage Vcc in an embodiment where the variable resistor element R4is not provided.

In one or more embodiments, as illustrated inFIG. 10, bandgap reference circuitry300is configured similarly to the one illustrated inFIG. 9, except that PTAT current generator circuitry37does not incorporate the variable resistor element R4and that current-voltage converter circuitry38is used in which a variable resistor element R5is connected in series to the bipolar transistor Q0and the resistor element R9. In one or more embodiments, the order in which the bipolar transistor Q0, the resistor element R9and the variable resistor element R5are connected is interchangeable.

In one or more embodiments, the first, second and third currents I1, I2and I0have the same current level I, which may be represented by the following expression (22):

With respect to the base-emitter voltage VBE0and the voltage drops across the resistor elements R9and R10, the following expression (23) holds:
VBE0+I0A·(R9+R5(Vcc))=I0B·R10   (23)

From expressions (18), (22) and (23), the current I0Bmay be represented by the following expression (24):

The output voltage Vout may be represented, for example, by the following expression (25):

Since the thermal voltage Vt has a positive temperature dependence and increases proportionally to the temperature while the base-emitter voltage VBE1has a negative temperature dependence, as is understood from expression (25), the temperature dependence of the output voltage can be reduced by appropriately adjusting N, R3, R9and R5(Vcc).

Additionally, the dependence of the output voltage Vout on the power supply voltage Vcc can be effectively reduced by appropriately selecting the property of the variable resistor element R5in accordance with the dependence of the output voltage Vout on the power supply voltage Vcc in an embodiment where the variable resistor element R5is not provided.

In one or more embodiments, as illustrated inFIG. 11, bandgap reference circuitry300is configured as a combination of the configuration illustrated inFIG. 9and that illustrated inFIG. 10. In the configuration illustrated inFIG. 11, PTAT current generator circuitry35incorporates a variable resistor element R4. Additionally, current-voltage converter circuitry38is used, in which the resistor element R5is connected in series to the bipolar transistor Q0and the resistor element R9.

In the configuration illustrated inFIG. 11, the output voltage Vout may be represented, for example, by the following expression (26):

In one or more embodiments, N, R3, R4(Vcc), R5(Vcc) and R9are adjusted so as to make the generated output voltage Vout less dependent on the temperature or free from the temperature dependence, on the basis of expression (26).

The properties of the variable resistor elements R4and R5are adjusted so as to reduce the dependence of the output voltage Vout on the power supply voltage Vcc, in accordance with the dependence of the output voltage Vout on the power supply voltage Vcc for an embodiment where the variable resistor elements R4and R5are not provided.

In one or more embodiments, as illustrated inFIG. 12, bandgap reference circuitry400comprises a power supply line41, a ground line42, a first current mirror43, a first operational amplifier44, a resistor element R3, a variable resistor element R4, bipolar transistors Q1, Q2, Q3, current-voltage converter circuitry46, a second current mirror47, and a second operational amplifier48. In one embodiment, thee power supply line41is supplied with the power supply voltage Vcc, and the ground line42is grounded.

In one or more embodiments, the first current mirror43is configured to output first and second currents I1and I2, third current I0, and the fourth current I3. The currents I0, I2and I3may have the same current level. In one or more embodiments, the first current mirror43comprises PMOS transistors MP0, MP1, MP2and MP3. The PMOS transistors MP0, MP1, MP2and MP3may have commonly-connected gates, and the sources thereof may be commonly connected to the power supply line41. Further, the drains of the PMOS transistors MP1, MP2and MP3may be connected to the nodes N1, N2and N3, respectively, and the drain of the PMOS transistor MP0may be connected to the output node Nout.

In one or more embodiments, the bipolar transistors Q1, Q2and Q3operates as first, second and third pn junction elements, respectively, each incorporating a pn junction. In one or more embodiments, NPN transistors are used as the bipolar transistors Q1, Q2and Q3. The bases of the bipolar transistors Q1, Q2and Q3may be commonly connected to the collector of the bipolar transistor Q3. The collectors of the bipolar transistors Q1, Q2and Q3may be connected to the first, second and third nodes N1, N2and N3, respectively. The emitters of the bipolar transistors Q1and Q3may be connected to the ground line42, and the emitter of the bipolar transistor Q2may be connected to the ground line42via the resistor element R3and the variable resistor element R4. The second and fourth currents I1, I2and I3may flow through the base-emitter pn junctions of the bipolar transistors Q1, Q2and Q3, respectively, in the forward directions.

In one or more embodiments, the base-emitter junctions of the bipolar transistors Q1and Q3have the same area, and the area of the base-emitter junction of the bipolar transistor Q2is N times as large as that of the base-emitter junctions of the bipolar transistors Q1and Q3, where N is an number larger than 1.

In various embodiments, the first operational amplifier44has a first input connected to the first node N1, a second input connected to the second node N2, and an output connected to the gates of the PMOS transistors MP0, MP1, MP2and MP3. Further, the first operational amplifier44may be configured to output a control voltage to the gates of the PMOS transistors MP0, MP1, MP2and MP3of the first current mirror43to control the currents I0, I1, I2and I3. In various embodiments, the operational amplifier44controls the potential of the gates of the PMOS transistors MP0, MP1, MP2and MP3so that the first and second nodes N1and N2have the same potential. The first and second nodes N1and N2may be virtually-shorted through the above operation of the first operational amplifier44. In one or more embodiments, the first current mirror and the operational amplifier44operate together as current supplier circuitry configured to control the nodes N1and N2to the same potential and supply currents of the same current level to the nodes N1and N2.

The current-voltage converter circuitry46may generate an output voltage Vout in response to the third current I0received from the first current mirror43. In one or more embodiments, the current-voltage converter circuitry46comprises a diode-connected bipolar transistor Q0and resistor elements R9and R10. The base-emitter junction of the bipolar transistor Q0may have the same area as that of the base-emitter junctions of the bipolar transistors Q1and Q3. The bipolar transistor Q0and the resistor element R9may be connected in series between the output node Nout and the ground line42. In one or more embodiments, the positions of the bipolar transistor Q0and the resistor element R9are interchangeable. Further, the resistor element R10may be connected between the output node Nout and the ground line42in parallel to the bipolar transistor Q0and the resistor element R9.

In one or more embodiments, the second current mirror47is configured to output a fifth current I4to the third node N3and output a sixth current I5to the current-voltage converter circuitry46. The current-voltage converter circuitry46may receive the sum current of the third current I0from the first current mirror43and the sixth current I5from the second current mirror47. The mirror ratio of the second current mirror47may be A:1, and accordingly the current level of the sixth current I5may be 1/A as large as that of the fifth current I4. In one or more embodiments, the second current mirror47comprises PMOS transistors MP4and MP5. The PMOS transistors MP4and MP5may have commonly-connected gates, and the sources thereof may be commonly connected to the power supply line41. The drain of the PMOS transistor MP4may be connected to the node N3, and the drain of the PMOS transistor MP5may be connected to the current-voltage converter circuitry46. In one or more embodiments, the PMOS transistors MP4and MP5are designed so that the PMOS transistors MP4and MP5has the same gate length L while the gate width WMP4of the PMOS transistor MP4is A times as large as the gate width WMP5of the PMOS transistor MP5.

In one or more embodiments, the second operational amplifier48outputs a control voltage to the gates of the PMOS transistors MP4and MP5of the second current mirror47to control the fifth and sixth currents I4and I5. The second operational amplifier48may be configured to control the potential of the PMOS transistors MP4and MP5so that the second and third nodes N2and N3have the same potential. The second and third nodes N2and N3may be virtually-shorted by the second operational amplifier48.

In one or more embodiments, the bandgap reference circuitry400illustrated inFIG. 12is configured to output the output voltage Vout through the operation described in the following.

In various embodiments, as the first, second and fourth currents I1, I2and I3are supplied to the bipolar transistors Q1, Q2and Q3as the collector currents while the first, second and fourth currents I1, I2and I3are controlled to have the same current level, the fifth current I4, which is supplied from the second current mirror47to the third node N3, is the sum current of the base currents of the bipolar transistors Q1, Q2and Q3. Accordingly, the sixth current I5, which is supplied to the current-voltage converter circuitry46from the second current mirror47, is dependent on the base currents of the bipolar transistors Q1, Q2and Q3.

In one embodiment, the base current of an emitter-grounded bipolar transistor is much smaller than the collector current, and therefore the current I4, which is the sum current of the base currents of the bipolar transistors Q1, Q2and Q3, can be considered as being much smaller than the currents I1, I2and I3, which are the collector currents of the bipolar transistors Q1, Q2and Q3. Further, the current I5can be considered as being much smaller than the current I0, because the current level of the current I0is equal to that of the currents I1, I2and I3and the current I5is 1/A times as large as the current I4.

In such an embodiment, to a first approximation, the output voltage Vout of the bandgap reference circuitry400may be represented for example by the above-described expression (21) as is the case with the bandgap reference circuitry300illustrated inFIG. 9. Accordingly, the temperature dependence of the output voltage Vout can be effectively reduced by appropriately adjusting N, R3, R4(Vcc) and R9. Additionally, in one or more embodiments, the dependence of the output voltage Vout on the power supply voltage Vcc can be also reduced by appropriately selecting the property of the variable resistor element R4in accordance with the dependence of the output voltage Vout on the power supply voltage Vcc in an embodiment where the variable resistor element R4is not provided.

The current I5, which is supplied to the current-voltage converter circuitry46from the current mirror47, may be used to compensate the non-linear temperature dependence of the output voltage Vout. As is understood from expression (21), the output voltage Vout is dependent on the base-emitter voltage VBE0. It is generally known that the base-emitter voltage of a bipolar transistor has non-linear negative temperature dependence. Meanwhile, the thermal voltage Vt is proportional to the absolute temperature T, having a linear temperature dependence. Accordingly, In one or more embodiments, the non-linear temperature dependence of the output voltage Vout is not fully cancelled when only the current I0is supplied to the current-voltage converter circuitry46. The current I5has a current level proportional to the current level of the base currents of the bipolar transistors Q1, Q2and Q3, and therefore exhibits a non-linear temperature dependence. The bandgap reference circuitry illustrated inFIG. 12may further reduce the temperature dependence of the output voltage Vout by supplying the current I5to the current-voltage converter circuitry46in addition to the current I0for compensation of the non-linear temperature dependence of the base-emitter voltage VBE0.

In one or more embodiments, as illustrated inFIG. 13, bandgap reference circuitry400is configured similarly to that illustrated inFIG. 12, except that the PTAT current generator circuitry49does not incorporate the variable resistor element R4and that current-voltage converter circuitry50is used, in which a variable resistor element R5is connected in series to the bipolar transistor Q0and the resistor element R9. In one or more embodiments, the order in which the bipolar transistor Q0, the resistor element R9and the variable resistor element R5are connected is interchangeable.

The discussion with respect to the bandgap reference circuitry400illustrated inFIG. 12may also be applicable to the bandgap reference circuitry400illustrated inFIG. 13. To a first approximation, the output voltage Vout of the bandgap reference circuitry400illustrated inFIG. 13may be represented, for example, by the above-described expression (25), as is the case with the bandgap reference circuitry300illustrated inFIG. 10. Accordingly, in one or more embodiments, the temperature dependence of the output voltage Vout can be effectively reduced by appropriately adjusting N, R3, R9and R5(Vcc). Additionally, the dependence of the output voltage Vout on the power supply voltage Vcc can be also reduced by appropriately selecting the property of the variable resistor element R5in accordance with the dependence of the output voltage Vout on the power supply voltage Vcc in an embodiment where the variable resistor element R5is not provided.

In one or more embodiments, as illustrated inFIG. 14, bandgap reference circuitry400is configured as a combination of the configuration illustrated inFIG. 12and that illustrated inFIG. 13. In the configuration illustrated inFIG. 14, the PTAT current generator circuitry45incorporates a resistor element R4. Additionally, the current-voltage converter circuitry50is used, in which the variable resistor element R5is connected in series to the bipolar transistor Q0and the resistor element R9.

The discussions with respect to the bandgap reference circuitry400illustrated inFIGS. 12 and 13may also be applicable to that illustrated inFIG. 14. To a first approximation, the output voltage Vout of the bandgap reference circuitry400illustrated in Fig. may be represented, for example, by the above-described expression (26), as is the case with the bandgap reference circuitry300illustrated inFIG. 11. In one or more embodiments, N, R3, R4(Vcc), R5(Vcc) and R9are adjusted to make the generated output voltage Vout less dependent on the temperature or free from the temperature dependence, on the basis of expression (26). Additionally, the properties of the variable resistor elements R4and R5are selected so as to reduce the dependence of the output voltage Vout on the power supply voltage Vcc, in accordance with the dependence of the output voltage Vout on the power supply voltage Vcc for the case where the variable resistor elements R4and R5are not provided.

In one embodiment, a method for operating bandgap reference circuitry comprises supplying a first current to a first node via a current mirror connected to a power supply line. Further, a second current is supplied to a second node virtually-shorted to the first node by the current mirror. The method further comprises letting the first current flow from the first node to a ground line through a first pn junction element.

Additionally, the method comprises letting the second current flow from the second node to the ground line through a second pn junction element and a variable resistor element. The variable resistor element is configured to have a resistance dependent on a power supply voltage supplied to the power supply line.

Although various embodiments of the present disclosure have been specifically described in the above, a person skilled in the art would appreciate that the techniques disclosed in this disclosure may be implemented with various modifications.