Scintillation camera having simplified electronic control

A scintillation camera, comprises the structure of a scintillation crystal (10), a collimator (20), a light guide (30), an array (50) of p photodetectors, p acquisition channels (60), and a processor (100) for supplying the coordinates x.sub.j and y.sub.j of a scintillation j and its associated energy E.sub.j, and further comprises structure characterized in that: PA0 (A) the p acquisition channels apply p digital signals to the input of the processor; PA0 (B) the processor (100) itself comprises: PA1 (a) a bus for transferring the p digital signals; PA1 (b) a digital summing stage (200); PA1 (c) a scintillation processing stage; and PA0 (C) a detection, sequencing and storage stage (400) which receives a signal which corresponds to the sum of the p output signals of the photodetectors, is provided in order to supply the various clock signals and the correction coefficients for the scintillation processing stage.

BACKGROUND 
The invention relates to a scintillation camera, comprising a scintillation 
crystal which may comprise a collimator and which serves to convert each 
photon received into a scintillation, a light guide for coupling the 
crystal to the entrance window of an array of p photodetectors which serve 
to convert each scintillation into a current, p acquisition channels which 
receive the output signals of the photodetectors and which supply p 
characteristic electric signals which relate notably to the intensity of 
the scintillations and to the distance between the respective 
scintillation and each of the photodetectors, and a processor which serves 
to supply the coordinates x.sub.j and y.sub.j of a scintillation j and its 
associated energy E.sub.j. 
For the determination of the image of the radio-active distribution inside 
an organ, medical diagnostics utilizes inter alia the scintigraphy 
principle. This method is based on the introduction of a radioactive 
element into the organism of a patient which attaches itself more or less 
to given organs, depending on whether these organs are healthy or not. The 
measurement of the intensity of the gamma radiation emitted provides an 
indication of the distribution of the radioactive element in the organism 
and hence forms a diagnostic aid. A measurement of this kind is performed 
by means of a scintillation camera. 
In conventional scintillation cameras, for example, Anger type cameras (the 
physician Anger was the first one to propose a scintillation camera whose 
principles are described in U.S. Pat. No. 3,011,057), the gamma rays which 
are representative of the radioactive distribution in the enviroment 
examined penetrate a scintillation crystal after having passed through a 
collimator. The scintillations thus produced in the crystal are 
subsequently detected by a series of photomultiplier tubes (for example, 
37) after having passed through a light guide which provides optical 
coupling between the crystal and the tubes. These tubes are distributed in 
front of the optical block (crystal+light guide) so as to cover 
substantially the entire surface thereof and to convert the light energy 
of each scintillation occurring into a measurable electric signal. 
Thus, with each photomultiplier tube there is associated an analog 
acquisition channel which successively provides amplification, integration 
and shaping of the signals supplied by the tube. The output signals 
S.sub.ij of the set of acquisition channels are applied to a processor 
which supplies, by estimation, the coordinates x.sub.j and y.sub.j of a 
scintillation j and its energy E.sub.j (the index i designates the 
relevant acquisition channel). The processor may comprise several types of 
calculation devices, but essentially two thereof are used, in practice, 
i.e. an arithmetical calculation device for determining the bary center. 
In such an arithmetical calculation device, the quantities x.sub.j, 
y.sub.j, E.sub.j are given by the expressions: 
##EQU1## 
In these expressions: 
##EQU2## 
where the coefficients G.sub.i, K.sub.i, H.sub.i, J.sub.i are weighting 
factors related to the position of the axis of each of the p 
photomultiplier tubes. 
In such a logarithmic calculation device, the quantities x.sub.j, y.sub.j, 
E.sub.j are given by the expressions: 
##EQU3## 
The weighting factors are again related to the position of the axis of 
each of the p photomultiplier tubes. 
Regardless of the arithmetic used, contemporary scintillation cameras 
generally comprise devices for calculating weighted sums which utilize 
resistance networks with associated summing amplifiers. In the cameras of 
this type it is not possible to execute calculations relating to a 
scintillation before the signals corresponding to the preceding 
scintillation have been set to zero, so that the maximum calculation speed 
is limited. In order to increase this speed, various solutions have 
already been proposed, for example, the reduction of the duration of the 
electric signals or the integration time by means of analog circuits. 
However, such a reduction could be achieved only at the expense of given 
intrinsic characteristics of the cameras, notably the spatial and the 
spectral resolution. 
In a previous French Patent Application FR-A 2 552 233 Applicant has 
proposed a digital radiation measuring device in which it is no longer 
necessary for the electric signals to return to zero before each new 
measurement, which means that a partial pile-up of the detected 
scintillations (and hence of the electric signals or pulses corresponding 
thereto) is accepted. 
It is the object of the invention to propose a novel scintillation camera 
which incorporates given elements of the above device which, however, are 
arranged partly within the p acquisition channels and partly within the 
processor and which has a simplified electronic design which allows for 
the A/D conversion and the subsequent digital integration of the signals 
to be performed by means of less accurate, and hence less expensive 
converters. This design also enables the execution of unpiling 
calculations by means of a limited number of processing circuits. 
To achieve this, the scintillation camera in accordance with the invention 
is characterized in that: 
(A) the p acquisition channels sample the output signals of the 
photodetectors, followed by the A/D conversion of the samples obtained and 
their summing, and apply p digital signals to the input of the processor; 
(B) the processor itself comprises: 
(a) a bus for transferring the digital signals; 
(b) a digital summing stage, comprising four digital weighted sum forming 
devices which supply four digital signals X.sub.m, Y.sub.m, Z.sub.m, 
E.sub.m on the basis of the output signals of the p acquisition channels; 
(c) a scintillation processing stage which includes unpiling calculation 
circuits and two dividers and which supplies the three coordinate and 
energy signals x, y, E on the basis of the signals X.sub.m, Y.sub.m, 
Z.sub.m, E.sub.m ; 
(C) a detection, sequencing and storage stage which receives a signal which 
corresponds to the sum of the p output signals of the photodetectors is 
provided in order to supply on the one hand the various clock signals for 
synchronizing the elements of the p acquisition channels and the elements 
of the processor, and on the other hand the correction coefficients for 
the scintillation processing stage. 
For example, European patent application No. 0166169 describes a 
scintillation camera which realizes the A/D conversion only in the 
processor; this notably leads to the use of high-precision and components 
which are far more costly, i.e. with a ratio of at least 1:100.

The conventional scintillation camera shown in FIG. 1 comprises a 
scintillation crystal 10 which is provided with a collimator 20 and which 
is intended for converting each photon received into a scintillation. By a 
light guide 30, the crystal is coupled to the entrance window of an array 
of p photodetectors which are in this case formed by photomultiplier tubes 
50. The tubes 50 convert each scintillation into a current which is then 
processed by p fully analog acquisition channels 60. The acquisition 
channels 60 realize notably the amplification, filtering, integration and 
shaping of the output signals of the photomultiplier tubes 50 and are 
followed by a processor 100 which supplies the coordinates x.sub.j, 
y.sub.i and the energy E.sub.j. 
In the embodiment which will be described in detail hereinafter with 
reference to FIG. 2 which shows the modifications to the circuit diagram 
of FIG. 1 for a camera in accordance with the invention, the p acquisition 
channels 60 are no longer fully analog like in conventional cameras, but 
apply p digital signals M.sub.i,j (i=index varying from 1 to p) to the 
input of the processor 100. The p channel now successively provide the 
amplification, filtering and sampling of the output signals of the 
photomultiplier tubes 50 after the A/D conversion of the samples obtained 
and the summing of the digital samples. The value of the p digital signals 
is related to that of the output current of the tubes 50 and hence to a 
fraction of the intensity of the initial scintillation, but different in 
accordance with the pile-up rate of the scintillations (this fraction 
itself is related to the realization of the optical block and notably to 
the distance between the scintillation point and the axis of the tubes). 
If there were no pile-up, the value of each of these signals would be 
denoted as S.sub.i,j ; the estimation of these values in the presence of 
pile-up will be denoted in S.sub.i,j. 
For realizing the above functions each of the p channels thus comprises a 
series connection of an amplification and filtering circuit 61 which 
receives the output signal of the corresponding tube 50, a time 
realignment circuit 62 which is followed by a conversion and integration 
device 63 which provides the successive sampling of the output signals of 
the corresponding circuit 62, the A/D conversion of the signals thus 
obtained, and the summing thereof. There is also provided an analog 
summing amplifier 64 whose p inputs receive the p output signals of the 
amplification and filtering circuits 61 and whose output signal is applied 
to a pulse-start detector which is situated in the detection, sequencing 
the storage stage 400 to be described hereinafter. The output signal of 
each of the p conversion and integration devices is applied to the 
processor 100, possibly via p FIFO memories which enable later operation 
at much lower frequencies thus by controlling the output of 
scintillations. This array of FIFO memories actually enables a reduction 
of the speed of later calculations and the slower rhythm thus obtained may 
be practically equal to the means arrival rhythm of the scintillations 
(for example, 2 microseconds for a mean rhythm of 500,000 scintillations 
per second) and no longer equal to the arbitrary arrival rhythm of the 
scintillations (approximately 0.2 microseconds in the former case). Each 
of the the conversion and integration devices 63 used herein is equivalent 
to that disclosed in French patent application FR-A 2 552 233 and 
comprises, in the embodiment shown in FIG. 3, a sampling and D/A 
conversion circuit 310 which is followed by an adder 311. To the output of 
the adder 311 there are connected to a first register 312 for storing the 
output signal of the adder, the output signal of the register being 
applied to a second input of the adder, and a second register 313 for 
storing the output signal of the adder, the output signal of the second 
register being that of the conversion and integration device which thus 
realizes a cumulative addition and the corresponding storage as the 
samples arrive. These operations are performed under the control of the 
detection, sequencing and storage stage 400 to be described hereinafter. 
The processor 100 receives the p output signals of the acquisition channels 
and comprises various calculation devices for distinctly determining the 
coordinates x.sub.j, y.sub.j and the energy E.sub.j of each scintillation 
j, either by means of the relations (1) to (6) in the case of an 
arithmetical calculation device or by means of the relations (7) to (13) 
in the case of a logarithmic calculation device. 
More precisely, the processor 100 as shown in FIG. 4 is constructed as 
follows in the case of an arthmetical calculation device. It comprises 
first of all a bus 150 for transferring the digital signals M.sub.i,j 
present at the output of the p acquisition channels. If for one of these 
channels, for example the channel i, the individual analog signals 
associated with several scintillations wich are grouped in time (FIG. 5a) 
and the resultant pile-up signal of these individual signals are 
represented (FIG. 5b), it appears that the scintillation j is disturbed 
upstream by several scintillations j-1, j-2, etc. If .alpha..sub.j and 
.gamma..sub.k,j are coefficients for correction by extrapolation and 
interpolation, respectively, which can be determined from the known mean 
shape, as a function of time, of the pulses corresponding to a detected 
scintillation and from the measurement of the period .theta..sub.j,j+1 
between t.sub.o,j and t.sub.o,j+1, if k is successively equal to j-1, J-2, 
. . . j-q, and if the signals S.sub.ik represent for these respective 
values of k the values corrected for pile-up effects which would be 
supplied by the digital acquisition channel in reaction to the 
scintillations j-1, j-2, . . . , j-Q, the digital signals obtained at the 
output of the acquisition channels will be shaped as: 
##EQU4## 
where M.sub.i,j represents the value measured at the instant t.sub.o,j+1, 
resulting from the summing of the samples during the time interval 
.theta..sub.j,j+1 for the channel i. The shape of the signal M.sub.i,j is 
shown in FIG. 5c. 
The processor finally comprises, connected to the output of the transfer 
bus 150, a digital summing stage 200 which itself is composed for four 
digital weighted sum forming devices 201 and 204 as shown in FIG. 4. The 
four devices 201 to 204 form the following weighted sums: 
EQU X.sub.m,j =.SIGMA..sub.i K.sub.i M.sub.ij (15) 
EQU Y.sub.m,j =.SIGMA..sub.i H.sub.i M.sub.ij (16) 
EQU Z.sub.m,j =.SIGMA..sub.i J.sub.i M.sub.ij (17) 
EQU E.sub.m,j =.SIGMA..sub.i G.sub.i M.sub.ij (18) 
respectively, where the coefficients K.sub.i, H.sub.i, J.sub.i, G.sub.i are 
the digital expressions of the weighting factors defined in accordance 
with the expressions (3) to (6) (for an arithmetical calculation device). 
Each of the digital weighted sum forming devices is, for example of the 
type multiplier-accumulator TDC 1009 (marketed by TRW, La Jolla, CA 92038, 
USA), one of the inputs of which receives the corresponding output signal 
of the bus 150, its other input receiving the weighting coefficients (in 
digital form), which are stored in an auxiliary memory. When this type of 
multiplier-accumulator is effectively used, the auxiliary memory must be 
synchronized with the operation of the complete processor and may be 
incorporated, for example in the detection, sequencing and storage stage 
400 to be described hereinafter. 
The output signals X.sub.m, Y.sub.m, Z.sub.m, E.sub.m of the digital 
summing stage 200 are thus applied to a scintillation processing stage 
500. As appears from FIG. 4, the stage 500 comprises four unpiling 
calculation circuits 501 to 504, two dividers 505 and 506, and one time 
realignment circuit 507. Because the four circuits 501 to 504 are 
identical, only one thereof will be described, for example the circuit 
501. This circuit is shown in FIG. 6 and comprises a subtractor 510 whose 
first, positive input receives the output signal of the corresponding 
digital weighted sum forming device 201 (the circuits 501 to 504 
correspond to the devices 201 to 204, respectively). The subtractor 510 is 
followed by a first multiplier 511 and a storage register 512, the output 
of which is that of the circuit 501. The subtractor 510 is also followed, 
connected parallel to the elements 511 and 512, by a second multiplier 513 
and a second storage register 514. These multipliers may be replaced by a 
single multiplier circuit in association with a time 
multiplexer/demultiplexer. The negative input of the subtractor 510 is 
connected to the output of the storage register 514. The The second input 
of the multiplier 511 is connected to the output of a memory 470 which 
stores the coefficients .alpha..sub.j and that of the multiplier 513 is 
connected to the output of a memory 480 which stores the coefficient 
.gamma..sub.j,k. For the scintillation j the outputs X, Y, Z, E of the 
four unpiling calculation circuits 501 to 504 are given by the 
expressions: 
##EQU5## 
The elements of each circuit 501 to 504, for example the elements 510 to 
514 of the circuit 501, form an upiling calculation circuit which is 
equivalent to that described in French patent application FR-A 2 552 233 
and denoted by the reference numerals 120 to 160. The other three circuits 
502 to 504 comprise the same elements as the circuit 501. 
The output signal X of the unpiling calculation circuit 501 is applied to 
the first input of the divider 505 and the output signal Y of the circuit 
502 is applied to the first input of the divider 506. The second input of 
each of these dividers is formed by the output Z of the unpiling 
calculation circuit 503. The three output signals of the processing stage, 
also being those of the processor, are formed by the output signal x.sub.j 
=X.sub.j /Z.sub.j of the divider 505, the output signals x.sub.j =Y.sub.j 
/Z.sub.j of the divider 506, and the output signal E.sub.j of the time 
realignment circuit 507 connected to the output of the unpiling 
calculation circuit 504. In the processor the detection, sequencing and 
storage stage 400 is also associated with these elements. The stage 400 is 
shown in FIG. 7 and comprises first of all a pulse start detector 410 
which receives the output signal of the analog summing amplifier 64 (see 
FIGS. 2 and 4). The detector 410 is followed by a clock circuit 420 and a 
clock signal counter 430. The number thus counted is applied to a test 
circiuit 440 whose output signal is applied to the sequencing circuit 450. 
The latter circuit synchronizes the operations performed in the 
acquisition channels, the stage 200 and the stage 500, and validates the 
contents of a register 460 for storing the output signal of the counter 
430, the register 460 being connected parallel to the test circuit 440. To 
the output of the register 460 there are connected the two memories 470 
and 480 mentioned above with reference to FIG. 6 and storing the 
coefficients .alpha..sub.i and .gamma..sub.j,k, respectively. The above 
elements 410 to 480 form a detection, sequencing, and storage stage which 
is similar to that disclosed in the Application FR-A 2 552 233. 
In a second embodiment, the calculation of the scintillation coordinates 
can be realized, without introducing extrapolation, in accordance with the 
following expressions: 
##EQU6## 
where always x.sub.j =X'.sub.j /Z'.sub.j and y.sub.j =Y'.sub.j /Z'.sub.j. 
The correction coefficient C.sub.k,j is a function of .theta..sub.j,j+1 
and .theta..sub.k,j. In this embodiment, the scintillation processing 
stage is denoted by the reference numeral 600 and the three unpiling 
calculation circuits which receive the signals X.sub.m, Y.sub.m, Z.sub.m 
are modified by the omission of the multiplier 511. These circuits 
actually have the construction shown in FIG. 8 for an arbitary one of 
these circuits, for example the first one of the circuits 601 to 603. The 
circuit 601 comprises a substractor 610 which receives on its first input 
the output signal of the corresponding digital weighted sum forming device 
201. The subtractor 610 is followed on the one hand directly by a storage 
register 612 whose output is that of the unpiling calculation circuit as 
before, and on the other hand, in parallel, by a multiplier 613, followed 
by a storage register 614. The output signal of the register 614 is 
applied to the second input of the substractor 610, the other input of the 
multiplier 613 being connected to the output of the memory 480 included in 
the stage 400 for the storage of the coefficient .gamma.. The other two 
circuits 602 and 603 comprise similar elements. The unpiling calculation 
circuit 504 remaining the same, the construction of the processor 100 is 
now as shown in FIG. 9. As before, the energy E is available on the output 
of the time realignment circuit 507. 
In a third embodiment as shown in FIG. 10, the processor 100 comprises a 
third type of scintillation processing stage which is denoted by the 
reference numeral 700. In this embodiment the unpiling operation is no 
longer performed on the output signals X.sub.m, Y.sub.m, Z.sub.m of the 
digital summing state 200 but on the coordinates x.sub.m and y.sub.m, that 
to have been measured because for each scintillation j they are derived 
directly from the non-corrected quantities X.sub.m, Y.sub.m, Z.sub.m in 
accordance with the relations x.sub.m,j =X.sub.m,j /Z.sub.m,j and 
y.sub.m,j =Y.sub.m,j /Z.sub.m,j. These signals x.sub.m and y.sub.m are 
obtained on the output of the two dividers 705 and 706, the divider 705 
receiving the output signals of the digital summing devices 201 and 203, 
while the divider 706 receives those of the devices 202 and 203. The 
coordinates x.sub.j, y.sub.j corresponding to the scintillation j are thus 
obtained on the outputs of the unpiling calculation circuits 701 and 702 
on the basis of, on the one hand, the measured data and, on the other 
hand, on the basis of the already known coordinates x.sub. y, y.sub.k of 
the preceding scintillations which disturb the scintillation j, in 
accordance with the following expressions: 
##EQU7## 
The coefficients .GAMMA..sub.k,j, being a function of the measured time 
intervals O.sub.j,j+1, O.sub.k,j and the ratios E.sub.k /E.sub.j, are 
calculated in an additional calculation circuit 707 which receives, on the 
one hand, the output signal E of the unpiling calculation circuit 504, 
which is always included in the processing stage, and, on the other hand, 
the coefficients .alpha. and .gamma. supplied by the detection, sequencing 
and storage stage 400. In the present embodiment the circuit 707 
calculates, on the one hand, based on the values of E successively 
received, the successive ratios E.sub.k /E.sub.j and, on the other hand, 
the products .alpha..sub.j .gamma..sub.k,j on the basis of which the 
coefficients .GAMMA..sub.k,j are evaluated in accordance with the relation 
.GAMMA..sub.k,j =.alpha..sub.j .gamma..sub.k,j E.sub.k /E.sub.j. The 
unpiling calculation circuits 701 and 702 have a configuration which is 
similar to that of the circuits 601 and 602. As before, the energy E is 
available on the output of the time realignment circuit 507. 
It is to be understood that the invention is not restricted to the 
embodiments described and shown, for which many alternatives are feasible 
without departing from the scope of the invention. For example, there may 
be provided an amplitude rejection circuit for reducing the number of 
scintillations to be processed, so that calculations are performed only on 
selected scintillations (by means of a threshold, an energy window, etc.). 
On the other hand, there may be provided a time multiplex circuit so that 
only one divider need be used instead of two in each of the embodiments 
shown in the FIGS. 4, 9 and 10. A time multiplex circuit may also be 
provided in order to reduce the number of unpiling calculation circuits, 
so that only one unpiling calculation circuit need be used instead of the 
four circuits 501 to 504 in the embodiment shown in FIG. 4, the four 
circuits 601 to 603 and 504 in the embodiment shown in FIG. 9, or the 
three circuits 701, 702 and 504 in the embodiment shown in FIG. 10. The 
series of alternatives proposed in this section is also applicable to 
other embodiments according to the FIGS. 11 to 16. 
Taking into account the means for the correction of linearity errors and 
energy errors utilized by state of the art gamma cameras on the basis of 
the signals x, y and E on the output of the processor, Z or E can be used 
arbitrarily for the calculation of the coordinates. In that case only one 
of these quantities can be calculated and, depending on the choice made, 
the other quanitity can be deduced from calculations in which specific 
corrections for this choice are made and which are executed by these 
means. The digital summing stage 200 thus comprises only three digital 
weighted sum forming devices which supply the signals X.sub.m, Y.sub.m, 
Z.sub.m or X.sub.m, Y.sub.m, E.sub.m, respectively. Moreover the 
scintillation processing stage 500 comprises only three unpiling 
calculation circuits. Similar to the FIGS. 4, 9 and 10, the FIGS. 11 to 13 
show the modifications in the processor when only three channels X, Y, Z 
are used, while the FIGS. 14 to 16 show, again similar to the FIGS. 4, 9 
and 10, the modifications of the processor when only three channels X, Y, 
E are used. 
On the hand, it is also to be noted that, in order to enable operation at 
lower frequencies by controlling the scintillation rate, read/write FIFO 
memories which are controlled by the detection, sequencing and storage 
stage 400 can be arranged upstream from the digital summing stage. 
Finally, it is to be noted that the bus 150 is either incorporated in the 
processor in which it forms the input or access element, or is connected 
thereto without being included therein. 
The weighted sum forming device in accordance with the invention which is 
shown in FIG. 17 comprises a digital multiplier 220 which sequentially 
receives, via a first shaping circuit 209, the signals for which the 
weighted sum is to be formed, an adder/accumulator 230, and a second 
shaping circuit 240. The first shaping circuit 209 essentially serves to 
restore the shape of the signals which, upon arrival, may have been 
disturbed by the circuits previously traversed, while the second shaping 
circuit 240 realizes, in addition to shaping a current gain and/or 
impedance matching. 
A digital memory 250 supplies the digital multiplier 220 with weighting 
coefficients to be applied to the signals. Commercially available 
integrated circuit digital multipliers (some of which also incorporate the 
adder/accumulator) can operate on signed as well as non-signed data. Thus, 
either positive or negative weighting coefficients can be stored in the 
digital memory 250. 
A processing circuit 210 is connected in series between the first shaping 
circuit 209 and the digital multiplier 220. The circuit 210 is controlled 
by a clock signal which will be described hereinafter. In the present 
embodiment a digital register 211 which contains a (possibly variable) 
threshold value (including the range to the value 0) is connected to the 
processing circuit 210. The processing circuit 210 may be formed simply by 
a circuit for eliminating signals which are below said threshold, or by a 
circuit having a more complex construction. 
In a first embodiment, the digital memory 250 is a ROM. The coefficients 
stored therein are thus permanently fixed during manufacture. In a more 
elaborate embodiment, the memory 250 may be a RAM. The weighting 
coefficients can then be modified by means of an additional wire or 
microprogrammed circuit (microprocessor, microcomputer, . . . ). 
The operation of the weighted sum calculation device in accordance with the 
invention will be described hereinafter with reference to FIG. 18 which 
shows the shape of the signals present at various points in the device. 
The digital signals present on the input of the shaping circuit 209 are 
denoted by the references S.sub.1, S.sub.2, . . . , S.sub.i, . . . , 
S.sub.p, . . . etc. and are shown in FIG. 18a. After shaping, these 
signals are received by the processing circuit 210 in the rhythm of the 
clock signal which is shown in FIG. 18b and with which the arrival of the 
digital signals S.sub.1, S.sub.2, . . . , S.sub.p, . . . , is 
synchronized. This clock signal is received on the connection 212. In the 
described embodiment, the circuit 211 defines the threshold value and the 
output signals of the circuit 209 are applied, or not, to the digital 
multiplier 220, depending on whether there are larger than/equal to or 
smaller than said threshold value, respectively. 
The signals present on the output of the processing circuit 210 are thus 
multiplied by respective weighting coefficients in the rhythm of a signal 
supplied on the connection 222. This signal is shown in FIG. 18c and is 
identical to that shown in FIG. 18b, but has been delayed with respect 
thereto by a period of time necessary for the transfer of the signals. The 
weighting coefficients are supplied by the memory 250 which is addressed 
in the rhythm of the signal which is shown in FIG. 18d, which is present 
on the connection 252 and which is in phase with the signal shown in FIG. 
18a. 
The adder/accumulator 230 thus performs a progressive summing operation on 
the weighted digital signals applied to its input, i.e. in the rhythm of 
the signal shown in FIG. 18e which is identical to that shown in FIG. 18b 
but which has also been delayed (in a manner other than in the preceding 
case) with respect thereto in order to compensate for the signal 
propagation time. The signal shown in FIG. 18e is received on the 
connection 232, a connection 234 being provided for the supply of a signal 
for resetting the adder/accumulator to zero (see FIG. 18f). Finally, FIG. 
18g shows a validation signal which is applied to the connection 242 of 
the shaping circuit 240 and which makes the desired weighted sum signal 
available on the output of the circuit 240. This sum signal is shown in 
FIG. 18h (the state preceding its arrival is referred to as a high 
impedance state). 
In the described embodiments or in the alternatives which can be realized 
within the scope of the invention, the weighted sum calculation device in 
accordance with the invention can find an important application in the 
field of scintillation cameras.