Method for producing semiconductor package

A technical concept of the present disclosure provides a method of producing a semiconductor package, the method including operations of: arranging a plurality of wafers on a tray, forming an interconnect structure on the tray and the plurality of wafers, and separating the plurality of wafers from the tray.

TECHNICAL FIELD

A technical concept of the present disclosure relates to a method of producing a semiconductor package, and more particularly, to a method of producing a semiconductor package using wafer level package technology.

BACKGROUND ART

In general, semiconductor packages are produced by performing a semiconductor package process on semiconductor chips manufactured by performing various semiconductor processes on a wafer. Recently, to reduce the production cost of semiconductor packages, wafer level package technology of performing a semiconductor package process in a wafer level and separating a wafer level semiconductor package subject to the semiconductor package process into semiconductor chips has been proposed.

Because the wafer level package does not require a printed circuit board, the total thickness of semiconductor packages can be reduced, and semiconductor packages with an excellent heat-dissipating effect can be manufactured due to their small thickness. However, there is a demand for methods of further reducing the cost of the semiconductor package process and improving productivity of the semiconductor package process in using the wafer level package technology.

DESCRIPTION OF TECHNICAL PROBLEM

The present disclosure is directed to provide a method of producing a semiconductor package, which is capable of improving productivity of a semiconductor package process.

SOLUTION TO TECHNICAL PROBLEM

According to a technical concept of the present disclosure for solving the above-described problem, there is provided a method of producing a semiconductor package, the method including arranging a plurality of wafers on a tray, forming an interconnect structure on the tray and the plurality of wafers, and separating the plurality of wafers from the tray.

Also, according to a technical concept of the present disclosure for solving the above-described problem, there is provided a method of producing a semiconductor package, including operations of: preparing a plurality of wafers having pads arranged on first surfaces, arranging the plurality of wafers in a plurality of cavities such that the first surfaces are exposed, forming an interconnect structure on a tray and the plurality of wafers, and separating the plurality of wafers from the tray, wherein the operation of forming the interconnect structure includes forming a first insulating layer having an opening exposing the pads of the plurality of wafers, a distribution layer electrically connected to the pads of the plurality of wafers, and a second insulating layer covering the distribution layer, sequentially, on the tray and the plurality of wafers accommodated in the cavities, and when the interconnect structure is formed, a space between side walls of the cavities and the wafers accommodated in the cavities is covered by the first insulating layer.

ADVANTAGEOUS EFFECTS OF DISCLOSURE

By a method of producing a semiconductor package according to embodiments of the present disclosure, a compact semiconductor package with excellent heat dissipation efficiency can be produced by using wafer level package technology.

Further, by a method of producing a semiconductor package according to embodiments of the present disclosure, the cost of a semiconductor package process can be reduced and the productivity of the semiconductor package process can be improved by arranging a plurality of wafers on a tray to perform the semiconductor package process in a panel level.

DETAILED DESCRIPTION

A method of producing a semiconductor package, according to the present disclosure, includes arranging a plurality of wafers on a tray, forming an interconnect structure on the tray and the plurality of wafers, and separating the plurality of wafers from the tray.

Hereinafter, preferred embodiments of a concept of the present disclosure will be described in detail with reference to the accompanying drawings. However, the embodiments of the concept of the present disclosure can be modified in many different forms, and it should be not interpreted that the scope of the concept of the present disclosure is limited to embodiments which will be described below. The embodiments of the concept of the present disclosure should be preferably interpreted to be provided to more completely describe the concept of the present disclosure to those having ordinary skill in the art. Like reference numerals refer to like elements throughout the specification. Further, various elements and areas in the drawings are schematically shown. Accordingly, the concept of the present disclosure is not limited by relative sizes and intervals shown in the drawings.

It will be understood that, although the terms “first”, “second”, etc. may be used herein to describe various components, these components should not be limited by these terms. These terms are only used to distinguish one component from another. For example, a first component could be termed a second component, and, similarly, a second component could be termed a first component, without departing from the scope of the present disclosure.

The terms used in the present specification are used to describe the embodiments of the present disclosure, not for the purpose of limiting the present disclosure. It is to be understood that the singular forms “a,” “an,” and “the” include plural referents unless the context clearly dictates otherwise. It will be understood that when the terms “includes,” “comprises,” “including,” and/or “comprising,” when used in this specification, specify the presence of stated features, figures, steps, components, or combination thereof, but do not preclude the presence or addition of one or more other features, figures, steps, components, members, or combinations thereof.

Unless otherwise defined, all terms, including technical terms and scientific terms, used herein have the same meaning as how they are generally understood by those of ordinary skill in the art to which the concept of the present disclosure pertains. Any term that is defined in a general dictionary should be construed to have the same meaning in the context of the relevant art, and, unless otherwise defined explicitly, should not be interpreted to have an idealistic or excessively formalistic meaning.

FIG. 1is a flowchart showing a method of producing a semiconductor package, according to some embodiments of a technical concept of the present disclosure.

Referring toFIG. 1, a method of producing a semiconductor package, according to embodiments of the present disclosure, may sequentially perform operation S100of preparing a plurality of wafers, operation S200of arranging the plurality of wafers on a tray, operation S300of forming an interconnect structure on the plurality of wafers, operation S400of separating the plurality of wafers from the tray, and operation S500of cutting each of the plurality of wafers in units of packages.

More specifically, in operation S100of preparing the plurality of wafers, a plurality of wafers each including a semiconductor substrate and a semiconductor device formed on the semiconductor substrate may be prepared.

The semiconductor substrate may include, for example, silicon (Si). Alternatively, the semiconductor substrate may include a semiconductor element such as germanium (Ge), or a compound semiconductor, such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). Alternatively, the semiconductor substrate may have a silicon on insulator (SOI) structure. For example, the semiconductor substrate may include a buried oxide layer (BOX). The semiconductor substrate may include a conductive area, for example, an impurity-doped well. Also, the semiconductor substrate may have various isolation structures such as a shallow trench isolation (STI) structure.

The semiconductor device may include various kinds of individual devices. For example, the plurality of individual devices may include various microelectronic devices, for example, a metal-oxide-semiconductor field effect transistor (MOSFET) (e.g., a complementary metal-insulator-semiconductor (CMOS) transistor), an image sensor (e.g., system large scale integration (LSI) and a CMOS imaging sensor (CIS)), a micro-electro-mechanical system (MEMS), an active device, a passive device, etc. The plurality of individual devices may be electrically connected to the conductive area of the semiconductor substrate. The semiconductor device may further include a conductive wire or a conductive plug electrically connecting at least two of the plurality of individual devices to each other or electrically connecting the plurality of individual devices to the conductive area of the semiconductor substrate. Also, each of the plurality of individual devices may be electrically insulated from the neighboring individual devices by insulating films.

Successively, in operation S200of arranging the plurality of wafers on the tray, a tray (for example, see100ofFIG. 2a) having an appropriate structure to arrange the plurality of wafers thereon may be prepared, and the plurality of wafers may be arranged at predetermined positions on the tray. According to some embodiments, a plurality of cavities may be formed to accommodate the plurality of wafers to easily arrange the plurality of wafers on the tray. When the wafers are arranged in the cavities of the tray, upper surfaces of the wafers on which pads are formed may face upward, and lower surfaces of the wafers, which are opposite to the upper surfaces thereof, may contact a surface of the tray.

Then, in operation S300of forming the interconnect structure on the plurality of wafers, an interconnect structure may be formed simultaneously on the plurality of wafers arranged on the tray. Herein, the interconnect structure (see200ofFIG. 6i) may mean a structure formed on the wafers to electrically connect pads of semiconductor devices formed on the wafers with an external device. Operation S300of forming the interconnect structure on the wafers will be described in more detail with reference toFIGS. 6bto 6h, later.

Thereafter, in operation S400of separating the plurality of wafers from the tray, a portion of a structure formed through operation S300of forming the interconnect structure on the plurality of wafers may be removed, and then the plurality of wafers may be separated from the tray. Each of the plurality of wafers separated from the tray may be a semiconductor package that is in the form of a wafer level package including an interconnect structure formed thereon. Operation S400of separating the plurality of wafers from the tray will be described in more detail with reference toFIG. 6i, later.

Then, in operation S500of cutting each of the plurality of wafers in units of packages, a process of sawing each wafer level semiconductor package separated from the tray may be performed to singulate the wafer level semiconductor package into a plurality of package unit semiconductor packages.

By the method of producing the semiconductor package, according to embodiments of the present disclosure, a compact semiconductor package with excellent heat-dissipating efficiency may be manufactured by using wafer level package technology.

Further, by the method of producing the semiconductor package, according to embodiments of the present disclosure, a plurality of wafers may be arranged on a tray so that at least a part of unit processes of a semiconductor package process may be performed in a panel level. Accordingly, a semiconductor package process may be performed simultaneously on the plurality of wafers, thereby simplifying the semiconductor package process and improving the productivity.

FIG. 2ais a perspective view of a tray100according to some embodiments of the present disclosure.FIG. 2bis a cross-sectional view of the tray100taken along line IIB-IIB′ ofFIG. 2a, showing a state in which a plurality of wafers10are arranged on the tray100.

Referring toFIGS. 2aand 2b, the tray100may be in the shape of a plate and include a body110and a plurality of cavities120.

The tray100may have a sufficient horizontal area to arrange all of the plurality of wafers10thereon. The tray100may support the plurality of wafers10while a semiconductor package process is performed on the plurality of wafers10. An outer circumference of the tray100may be in the shape of a rectangle, as shown inFIG. 2a, although not limited thereto.

The body110may form an entire outer appearance of the tray100and have a sufficient horizontal area to arrange all of the plurality of wafers10thereon, like the tray100.

The plurality of cavities120may provide spaces to accommodate the plurality of wafers10, respectively. That is, each cavity120may be a recess provided in the body110and include a bottom surface facing a lower surface of the corresponding wafer10and a side wall facing a side surface of the wafer10.

The plurality of cavities120may have shapes corresponding to the wafers10. For example, when the tray100is seen from above, each cavity120may be in the shape of a circle. InFIGS. 2aand 2b, the plurality of cavities120are shown to have substantially the same dimension. However, the dimensions of the plurality of cavities120, for example, horizontal areas and/or depths120hof the plurality of cavities120may be different from each other. Further, inFIG. 2a, four cavities120are shown to be formed in the tray100. However, the number of cavities120formed in a single tray100may be two or more.

In some embodiments, the tray100may include a notch portion130. The notch portion130may be positioned at each of the plurality of cavities120. For example, the notch portion120may be positioned at the side wall of each cavity120. The notch portion130may be provided to locate the wafer100at a predetermined position on the tray100. Through the notch portion130, the wafer10may be aligned in a predetermined direction in the cavity120. In some embodiments, the notch portion130may contact a notch of the wafer10to fix the wafer10in the cavity120.

In some embodiments, the tray100may include an align mark140. The align mark140may be located around each of the plurality of cavities120on a upper surface111of the body110. The align mark140may locate the wafers10at predetermined positions on the tray100. Also, semiconductor manufacturing equipment for performing a plurality of unit processes during a semiconductor package process may recognize positions of the cavities120and/or the wafers10positioned in the cavities120through the align mark140.

As shown inFIG. 2b, the wafer10may be positioned in the cavity120such that an upper surface11of the wafer10, on which a pad13is formed, faces upward and a lower surface of the wafer10, which is opposite to the upper surface11thereof, faces the bottom surface of the cavity120. In other words, when the wafer10is disposed in the cavity120, an active surface of the wafer10may be exposed to the outside and an inactive surface of the wafer10may face the bottom surface of the cavity120. A horizontal width of the cavity120, for example, a horizontal width traversing a diameter of the cavity120, may be greater than a horizontal width of the wafer10, and accordingly, the side wall of the cavity120may be spaced a predetermined distance190from an edge of the wafer10. The distance190between the side wall of the cavity120and the edge of the wafer10may be adjusted appropriately such that, when an insulating layer (for example, see211ofFIG. 6b) is formed on the plurality of wafers10and the surface of the tray100, for example, by a laminating method, a space120S between the side wall of the cavity120and the edge of the wafer10is not filled by the insulating layer.

In some embodiments, the depth120hof the cavity120may be substantially equal to a thickness10hof the wafer10. In other words, when the wafer10is located in the cavity120, the upper surface111of the body110may be in the same level as the upper surface11of the wafer10. That is, the upper surface111of the body110may be co-planar with the upper surface11of the wafer10. When the upper surface111of the body110is in the same level as the upper surface11of the wafer10, an insulating layer formed to cover the upper surface111of the body110and the upper surface11of the wafer10may have little stepped portion.

In the embodiments of the present disclosure, because at least a part of a semiconductor package manufacturing process is performed in the state in which the plurality of wafers10are arranged on the tray100, the tray100may be made of a material having chemical resistance and thermal resistance.

In some embodiments, the tray100may be made of a metal material, for example, iron, nickel, cobalt, titanium, or an alloy thereof.

In some embodiments, the tray100may be made of a ceramic material, for example, alumina or silicon carbide.

In some embodiments, the tray100may be made of carbon fiber. Alternatively, the tray100may be made of prepreg, which is an insulator. For example, the tray100may be made of a material resulting from absorbing a thermosetting resin into reinforced fiber or the like before molding to harden to B-stage (a semi-hardened state of a resin).

FIG. 3is a perspective view of a tray100aaccording to some embodiments of a technical concept of the present disclosure. The tray100ashown inFIG. 3may have substantially the same configuration as the tray100shown inFIGS. 2aand 2bexcept that a plurality of cavities120aand120bhave different horizontal widths. InFIG. 3, the same reference numerals as those used inFIGS. 2aand 2bindicate the same components, and therefore, detailed descriptions about the components will be omitted or briefly given.

Referring toFIG. 3, the tray100amay include a first cavity120aand a second cavity120bhaving different horizontal widths. For example, a diameter of the first cavity120amay be greater than that of the second cavity120b.Because the tray100aincludes the first cavity120aand the second cavity120bhaving different horizontal widths, wafers having different diameters may be mounted on the tray100a,simultaneously. Accordingly, the tray100amay be used to simultaneously perform a semiconductor package process on wafers having different diameters.

In the drawings, the tray100ais shown to include cavities having two different horizontal widths. However, the tray100amay include cavities having three different horizontal widths or more.

FIG. 4is a cross-sectional view showing a state in which the plurality of wafers10are arranged on a tray100baccording to some embodiments of a technical concept of the present disclosure. The tray100bshown inFIG. 4may have substantially the same configuration as the tray100shown inFIGS. 2aand 2bexcept for a depth120haof cavities120a.InFIG. 4, the same reference numerals as those used inFIGS. 2aand 2bindicate the same components, and therefore, detailed descriptions about the components will be omitted or briefly given.

Referring toFIG. 4, the depth120haof the cavities120aprovided in the tray100bmay be less than a thickness10hof the wafers10. Accordingly, when the wafers10are arranged in the cavities120a,at least a portion of each wafer10may protrude from an upper surface111aof a body110a.That is, when the wafers10are arranged in the cavities120a,the upper surface11aof the body110amay be in a level that is lower than the upper surfaces11of the wafers10. In other words, a vertical distance between bottom surfaces of the cavities120aand the upper surface111aof the body110may be less than a vertical distance between the bottom surfaces of the cavities120aand the upper surfaces11of the wafers10accommodated in the cavities120a.

Although not shown in the drawing, the tray100bmay include a notch portion (see130ofFIG. 2a) positioned on a side wall of each cavity120aand/or an align mark (see140ofFIG. 2a) provided on the upper surface111aof the body110a.

When the upper surface111aof the body110ais in a level that is lower than the upper surfaces11of the wafers10, an insulating layer (for example, see211ofFIG. 6b) formed to cover the upper surface111aof the body110aand the upper surfaces11of the wafers10may have stepped portions around the edges of the wafers10. Also, the insulating layer may be formed to cover a portion of the side surfaces of the wafers10.

FIG. 5is a cross-sectional view showing a state in which the plurality of wafers10are arranged on a tray100caccording to some embodiments of a technical concept of the present disclosure. The tray100cshown inFIG. 5may have substantially the same configuration as the tray100shown inFIGS. 2aand 2bexcept that the tray100chas no cavity. InFIG. 5, the same reference numerals as those used inFIGS. 2aand 2bindicate the same components, and therefore, detailed descriptions about the components will be omitted or briefly given.

Referring toFIG. 5, the tray100cmay provide a flat upper surface111bon which the plurality of wafers10may be arranged. The plurality of wafers10may be arranged at predetermined positions on an upper surface111bof a body110b.

Although not shown in the drawing, the tray100cmay include an align mark (see140ofFIG. 2a) provided on the upper surface111bof the body110.

When the tray100chas the flat upper surface111b,an insulating layer (for example, see211ofFIG. 6b) formed along the surface of the tray100cand the surfaces of the wafers10may cover the upper surface111bof the tray100c,and cover the upper surfaces11of the wafers10and at least a portion of the side surfaces of the wafers10. By the insulation layer, the wafers10arranged on the tray100cmay be fixed during a semiconductor package process.

FIGS. 6ato 6jare cross-sectional views showing a method of producing a semiconductor package, according to some embodiments of a technical concept of the present disclosure, in the order of processes. InFIGS. 6ato 6j, a method of producing a semiconductor package by using the tray100shown inFIGS. 2aand 2bwill be described.

Referring toFIG. 6a, a plurality of wafers10may be arranged on a tray100. The respective wafers10may be accommodated in different cavities120provided in the tray100. Each wafer10may be positioned in the cavity120such that an upper surface11of the wafer10, on which a pad13is formed, is exposed. In other words, the wafer10may be positioned in the cavity120such that a lower surface of the wafer10, which is opposite to the upper surface11, faces a bottom surface of the cavity120. In other words, an active surface of the wafer10may be exposed, and an inactive surface of the wafer10may contact a surface of the tray100.

The wafer10may be positioned in the cavity120in such a way to be spaced from a side wall of the cavity120. Because the side surface of the wafer10is spaced from the side wall of the cavity120, a space120S that opens in an up direction may be formed between the side surface of the wafer10and the side wall of the cavity120.

As shown inFIG. 6a, a depth of the cavity120may be substantially equal to a thickness of the wafer10, and accordingly, the upper surface11of the wafer10positioned in the cavity120and the upper surface111of the body110may have the same height level.

However, when the wafer10is positioned in the cavity120, the upper surface of the body110may have a height level that is different from the upper surface11of the wafer10. For example, the upper surface of the body110may have a level that is lower than the upper surface11of the wafer10.

Referring toFIG. 6b, a first insulating layer211may be formed on the tray100and the plurality of wafers10. The first insulating layer211may have an opening211H to expose at least a portion of the pad13. The first insulating layer211may cover the upper surface111of the body110and the upper surfaces11of the plurality of wafers10.

The first insulating layer211may fix the wafers10positioned in the cavities120during a subsequent process. Also, the first insulating layer211may cover the space120S between the wafers10and the side walls of the cavities120. For example, the space120S between the wafers10and the side walls of the cavities120may be sealed by the first insulating layer211. When an interconnect structure is formed, the first insulating layer211may cover the space120S between the wafers10and the side walls of the cavities120to prevent foreign materials from entering the space120S.

In some embodiments, the first insulating layer211may cover a top area of the space120S between the side surfaces of the wafers10and the side walls of the cavities120such that a material forming the first insulating layer211is not filled in the space120S between the side surfaces of the wafers10and the side walls of the cavities120. Because the material forming the first insulating layer211is not filled in the space120S between the side surfaces of the wafers10and the side walls of the cavities120, the wafers10may be easily separated from the tray100, later.

In some embodiments, the first insulating layer211may be formed through a film process using an insulating film. More specifically, to form the first insulating layer211, a photosensitive film may be attached on the upper surface111of the body110and the upper surfaces11of the plurality of wafers10by a laminating method, and then, a portion of the photosensitive film may be removed through exposure and development processes to expose the pads13of the wafers10.

Also, in some embodiments, the first insulating layer211may include a non-photosensitive material. For example, to form the first insulating layer211, a non-photosensitive film may be attached on the upper surface111of the body110and the upper surfaces11of the plurality of wafers10, and then, a portion of the non-photosensitive film may be removed by a laser cutting apparatus to expose the pads13of the wafers10.

The first insulating layer211may be formed with a polymer material such as, for example, polyimide.

Meanwhile, in other embodiments, the first insulating layer211may be formed by a spin-coating method.

Referring toFIG. 6c, a seed metal layer221amay be formed to cover a surface of the first insulating layer211and surfaces of the pads13exposed through openings211H of the first insulating layer211. The seed metal layer221amay be deposited by, for example, a sputtering method. However, a method of forming the seed metal layer221ais not limited to the sputtering method. The seed metal layer221amay include any one of, for example, Ti, Cu, Ni, Al, Pt, Au, Ag, W, Ta, Co, or a combination thereof.

Referring toFIG. 6d, a first mask pattern290having a first mask opening290H may be formed on the seed metal layer221a.A portion of the seed metal layer221amay be exposed by the first mask opening290H.

The first mask pattern290may be formed by forming a photosensitive material film on the seed metal layer221aand then performing a patterning process using photolithography technology on the photosensitive material film. For the photolithography process, an exposure mask on which a predetermined pattern is formed may be used, or a laser light source such as KrF or ArF may be used.

In some embodiments, the first mask pattern290may be formed by a film process. For example, a photosensitive film may be attached on the seed metal layer221ato cover the seed metal layer221a,and then, a portion of the seed metal layer221amay be exposed through exposure and development processes to form the first mask opening290H.

Referring toFIG. 6e, a first metal layer223may be formed to fill at least a portion of the first mask opening290H. The first metal layer223may cover a surface of the seed metal layer221aexposed through the first mask opening290H.

The first metal layer223may be formed through, for example, a plating method. For example, the first metal layer223may be formed with copper. In some embodiments, the first metal layer223may be formed by a plating method using the seed metal layer221aas a seed. For example, the first metal layer223may be formed by immersion plating, electroless plating, electroplating, or a combination thereof.

In some embodiments, the seed metal layer221amay be formed with a substantially uniform thickness on the upper surface111of the tray100and the plurality of wafers10. Particularly, when the depth of the cavities120is substantially equal to the thickness of the wafers10accommodated in the cavities120, the seed metal layer221amay be formed without any stepped portion even around the space (see120S ofFIG. 6b) between the side walls of the cavities120and the wafers10accommodated in the cavities120. In this case, around the space between the side walls of the cavities120and the wafers10accommodated in the cavities120, the seed metal layer221amay be parallel to the upper surface111of the tray100. Also, a thickness of the seed metal layer221aon the space between the side walls of the cavities120and the wafers10accommodated in the cavities120may be substantially equal to a thickness of portions of the seed metal layer221aon the plurality of wafers10. Accordingly, in a plating process of applying power to the seed metal layer221aby a plating jig (not shown), the power may be more uniformly transferred to the entirety of the seed metal layer221a.For example, even when the plating jig contacts a portion of the seed metal layer221aaround an edge of the upper surface111of the tray100, power applied through the plating jig may be uniformly transferred to the entirety of the seed metal layer221ahaving a uniform thickness.

Referring toFIG. 6f, after the first metal layer223is formed, the first mask pattern290and the seed metal layer (221aofFIG. 6e) located below the first mask pattern290may be removed from the resultant structure ofFIG. 6e.

To remove the first mask pattern290, an ashing or strip process may be used. Also, after the first mask pattern290is removed, a chemical etching method may be used to remove the seed metal layer (221aofFIG. 6e) located below the first mask pattern290.

In some embodiments, the first metal layer223and the seed metal layer221amay be combined into one body to construct a distribution layer220.

Referring toFIG. 6g, a second insulating layer213may be formed to cover the first metal layer223, and successively, a second metal layer225may be formed to penetrate the second metal layer213to be connected to the first metal layer223. In some embodiments, the first insulating layer211, the distribution layer220, the second insulating layer213, and the second metal layer225may construct an interconnect structure200a.

In some embodiments, the second insulating layer213may be formed by a film process, like the first insulating layer211described above with reference toFIG. 6b. The second insulating layer213may include a photosensitive material or a non-photosensitive material.

In some embodiments, the second metal layer225may be a under bump metal (UBM). In other embodiments, the second metal layer225may be omitted.

Referring toFIG. 6h, an external connection terminal400may be formed on the second metal layer225. The external connection terminal400may be, for example, a solder ball or a solder bump. The external connection terminal400may electrically connect the semiconductor package with an external device. The external connection terminal400may be electrically connected to the pads13of the wafers10via the seed metal layer221, the first metal layer223, and the second metal layer225. Meanwhile, when the second metal layer225is omitted, the external connection terminal400may be attached on the first metal layer223exposed by the second insulating layer213.

Referring toFIG. 6i, to separate the plurality of wafers10from the tray100, a portion of a structure stacked on the tray100and/or the plurality of wafers10may be removed. At this time, a material remaining between the side walls of the cavities120and the wafers120accommodated in the cavities120may be also removed.

For example, by removing the portion of the structure stacked on the tray100and/or the plurality of wafers10, a separation lane250may be formed in the interconnection structure200. The separation lane250may penetrate the first insulating layer211and the second insulating layer213perpendicularly, and be formed along the edge of each of the plurality of wafers10. The separation lane250may be in the shape of a ring, as seen from above. By the separation lane250, the space120S between the side walls of the cavities120and the edges of the wafers10may be exposed. Further, a portion of the edges of the wafers10and/or a portion of the surface of the tray100may also be exposed. By the separation lane250, wafer level semiconductor packages including the wafers10and the interconnect structure200formed on the wafers10may be separated from each other.

The separation lane250may be formed by, for example, a laser drilling method.

Referring toFIG. 6j, a wafer level semiconductor package1may be separated from the tray (100ofFIG. 6i), and the wafer level semiconductor package1may be singulated into a plurality of package unit semiconductor packages through a sawing process. In other words, a sawing blade BL may cut the wafer level semiconductor package1along a scribe lane SL to separate the wafer level semiconductor package1. As a result, the wafer level semiconductor package1may be singulated into a plurality of package unit semiconductor packages.

FIGS. 7ato 7dare cross-sectional views showing a method of producing a semiconductor package, according to some embodiments of a technical concept of the present disclosure, in the order of processes. InFIGS. 7ato 7d, a method of producing a semiconductor package by using the tray100cshown inFIG. 5will be described, and descriptions overlapping with those given above with reference toFIGS. 6ato 6jwill be omitted or briefly given.

Referring toFIG. 7a, a plurality of wafers10may be arranged on the tray100c.An upper surface11of each of the plurality of wafers10, on which a pad13is formed, may be exposed upward, and a lower surface of the wafer10, which is opposite to the upper surface11, may face a surface of the tray100c.To arrange the plurality of wafers10at predetermined positions on the tray100c,an align mark (see140ofFIG. 2a) provided on the tray100cmay be used.

Referring toFIG. 7b, a first insulating layer311covering the surface of the tray100cand the surface of the wafer10and having an opening311H exposing the pad13of the wafer10may be formed. Because the upper surface11of the wafer10has a level that is higher than the surface of the tray100c,the first insulating layer311may have a stepped shape. The first insulating layer311may fix the plurality of wafers10at predetermined positions on the tray100cduring a subsequent process.

Referring toFIG. 7c, an interconnect structure300amay be formed on the plurality of wafers10and the tray100cthrough the substantially same process as that described above with reference toFIGS. 6cto 6g, and an external connection terminal400connected to a second metal layer325may be formed.

Referring toFIG. 7d, to separate the plurality of wafers10from the tray100c,a portion of the first insulating layer311and a portion of a second insulating layer313may be removed along the edges of the plurality of wafers10.

Because a portion of the first insulating layer311and a portion of the second insulating layer313are removed along the edges of the plurality of wafers10, a separation lane350may be formed in the interconnect structure300. By the separation lane350, wafer level semiconductor packages including the wafers10and the interconnect structure300formed on the wafers10may be separated from each other.

After the separation lane350is formed, the wafer level semiconductor packages may be separated from the tray100c.Each of the separated wafer level semiconductor packages may be singulated into a plurality of package unit semiconductor packages through a sawing process.

By the method of producing the semiconductor package, according to the embodiments of the present disclosure, a plurality of unit processes of a semiconductor package process may be performed by using a tray capable of supporting a plurality of wafers. That is, because the semiconductor package process is performed by arranging a plurality of wafers on a tray, a plurality of wafer level semiconductor packages may be manufactured in a panel level. Accordingly, by the technical concept of the present disclosure, semiconductor package processes for a plurality of wafers can be performed at the same time, which leads to improving productivity.

FIG. 8is a flowchart showing a method of producing a semiconductor package, according to some embodiments of a technical concept of the present disclosure.

Referring toFIG. 8, the method of producing the semiconductor package, according to the embodiments of the present disclosure, may sequentially perform operation S1100of preparing a plurality of wafers, operation S1300of forming an interconnect structure on the plurality of wafers, and operation S1500of cutting each of the plurality of wafers in units of packages.

More specifically, in operation S1100of preparing the plurality of wafers, a plurality of wafers including a semiconductor substrate and a semiconductor device formed on the semiconductor substrate may be prepared.

The semiconductor substrate may include, for example, silicon (Si). Alternatively, the semiconductor substrate may include a semiconductor element such as germanium (Ge), or a compound semiconductor, such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). Alternatively, the semiconductor substrate may have a silicon on insulator (SOI) structure. For example, the semiconductor substrate may include a buried oxide layer (BOX). The semiconductor substrate may include a conductive area, for example, an impurity-doped well. Also, the semiconductor substrate may have various isolation structures such as a shallow trench isolation (STI) structure.

The semiconductor device may include various kinds of individual devices. For example, the plurality of individual devices may include various microelectronic devices, for example, a metal-oxide-semiconductor field effect transistor (MOSFET) (e.g., a complementary metal-insulator-semiconductor (CMOS) transistor), an image sensor (e.g., system large scale integration (LSI) and a CMOS imaging sensor (CIS)), a micro-electro-mechanical system (MEMS), an active device, a passive device, etc. The plurality of individual devices may be electrically connected to the conductive area of the semiconductor substrate. The semiconductor device may further include a conductive wire or a conductive plug electrically connecting at least two of the plurality of individual devices to each other, or electrically connecting the plurality of individual devices to the conductive area of the semiconductor device. Also, each of the plurality of individual devices may be electrically insulated from the neighboring individual devices by insulating films.

Then, in operation S1300of forming the interconnect structure on the plurality of wafers, an interconnect structure may be formed simultaneously on the plurality of wafers arranged on the tray. Herein, the interconnect structure (see200ofFIG. 10j) may mean a structure formed on a wafer to electrically connect a pad of a semiconductor device formed on the wafer with an external device.

In operation S1300of forming the interconnect structure on the plurality of wafers, some processes may be performed in the state in which the plurality of wafers are arranged on the tray, and the other processes may be performed in the state in which the plurality of wafers are separated from the tray. That is, operation S1300of forming the interconnect structure on the plurality of wafers may include an operation of arranging the plurality of wafers on the tray and/or an operation of separating the plurality of wafers from the tray between unit processes for a semiconductor package.

In the operation of arranging the plurality of wafers on the tray, a tray (for example, see100ofFIG. 2a) having an appropriate structure to arrange the plurality of wafers thereon may be prepared, and the plurality of wafers may be arranged at predetermined positions on the tray. In some embodiments, a plurality of cavities for accommodating the plurality of wafers may be formed to facilitate an arrangement of the plurality of wafers. When the wafers are arranged in the cavities of the tray, the upper surfaces of the wafers, on which pads are formed, may face upward, and the lower surfaces of the wafers, which are opposite to the upper surfaces thereof, may contact the surface of the tray.

Also, in the operation of separating the plurality of wafers from the tray, a portion of a structure formed through the operation of forming the interconnect structure on the plurality of wafers may be removed, and then, the plurality of wafers may be separated from the tray.

Operation S1300of forming an interconnect structure on the plurality of wafers will be described in more detail, below.

Thereafter, in operation S1500of cutting the plurality of wafers in units of packages, a sawing process may be performed on a wafer level semiconductor package including the interconnect structure to singulate the wafer level semiconductor package into a plurality of package unit semiconductor packages.

By the method of producing the semiconductor package, according to the embodiments of the present disclosure, a compact semiconductor package with excellent heat-dissipating efficiency may be manufactured by using wafer level package technology.

Further, by the method of producing the semiconductor package, according to embodiments of the present disclosure, a plurality of wafers may be arranged on a tray so that at least a part of unit processes of a semiconductor package process may be performed in a panel level. Accordingly, a semiconductor package process may be performed simultaneously on the plurality of wafers, thereby simplifying the semiconductor package process and improving productivity.

FIG. 9is a flowchart showing a method of producing a semiconductor package, according to some embodiments of the present disclosure.FIGS. 10ato 10kare cross-sectional views showing a method of producing a semiconductor package, according to some embodiments of a technical concept of the present disclosure, in the order of processes. Hereinafter, a method of producing a semiconductor package using the tray100shown inFIGS. 2aand 2bwill be described with reference toFIGS. 9 and 10ato10k.

Referring toFIGS. 9 and 10a, a plurality of wafers10may be arranged on the tray100(S1301). The respective wafers10may be accommodated in different cavities120provided in the tray100. Each wafer10may be positioned in the cavity120such that an upper surface11of the wafer10, on which a pad13is formed, is exposed upward, and a lower surface of the wafer10, which is opposite to the upper surface11, faces a bottom surface of the cavity120. In other words, an active surface of the wafer10may be exposed, and an inactive surface of the wafer10may contact a surface of the tray100.

The wafer10may be positioned in the cavity120in such a way to be spaced from a side wall of the cavity120. Because a side surface of the wafer10is spaced from the side wall of the cavity120, a space120S that opens in an up direction may be formed between the side surface of the wafer10and the side wall of the cavity120.

As shown inFIG. 10a, a depth of the cavity120may be substantially equal to a thickness of the wafer10, and accordingly, the upper surface11of the wafer10positioned in the cavity120and an upper surface111of the body110may have the same height level.

However, when the wafer10is positioned in the cavity120, the upper surface of the body110may have a height level that is different from the upper surface11of the wafer10. For example, the upper surface of the body110may have a level that is lower than the upper surface11of the wafer10.

In some embodiments, to arrange the wafers10at predetermined positions in the cavities120, a notch portion (see130ofFIG. 2a) and/or an align mark (see140ofFIG. 2a) provided on the tray100may be used.

Referring toFIGS. 9 and 10b, a first insulating layer211may be formed on the tray100and the plurality of wafers10(S1310). The first insulating layer211may have an opening211H to expose at least a portion of the pad13. The first insulating layer211may cover the upper surface111of the body110and the upper surfaces11of the plurality of wafers10.

The first insulating layer211may fix the wafers10positioned in the cavities120during a subsequent process. Also, the first insulating layer211may cover the space120S between the wafers10and the side walls of the cavities120. For example, the space120S between the wafers10and the side walls of the cavities120may be sealed by the first insulating layer211. When an interconnect structure is formed, the first insulating layer211may cover the space120S between the wafers10and the side walls of the cavities120to prevent foreign materials from entering the space120S.

In some embodiments, the first insulting layer211may cover a top area of the space120S between the side surfaces of the wafers10and the side walls of the cavities120such that a material forming the first insulating layer211is not filled in the space120S between the side surfaces of the wafers10and the side walls of the cavities120. Because the material forming the first insulating layer211is not filled in the space120S between the side surfaces of the wafers10and the side walls of the cavities120, the wafers10may be easily separated from the tray100, later.

In some embodiments, the first insulating layer211may be formed through a film process. More specifically, to form the first insulating layer211, an insulating film may be attached on the upper surface111of the body110and the upper surfaces11of the plurality of wafers10by a laminating method, and then, a portion of the insulating film may be removed to expose the pads13of the wafers10. The insulating film may be a photosensitive film, and exposure and development processes may be performed to remove a portion of the photosensitive film.

Also, in some embodiments, the first insulating layer211may include a non-photosensitive material. For example, to form the first insulating layer211, a non-photosensitive film may be attached on the upper surface111of the body110and the upper surfaces11of the plurality of wafers10, and then, a portion of the non-photosensitive film may be removed by a laser cutting apparatus to expose the pads13of the wafers10.

The first insulating layer211may be formed with a polymer material such as, for example, polyimide.

Meanwhile, in other embodiments, the first insulating layer211may be formed by a spin-coating method.

Referring toFIGS. 9 and 10c, a seed metal layer221amay be formed to cover a surface of the first insulating layer211and a surface of the pad13exposed through the opening211H of the first insulating layer211(S1320). The seed metal layer221amay be deposited by, for example, a sputtering method. However, a method of forming the seed metal layer221ais not limited to the sputtering method. The seed metal layer221amay include any one of, for example, Ti, Cu, Ni, Al, Pt, Au, Ag, W, Ta, Co, or a combination thereof.

Referring toFIGS. 9 and 10d, a first mask pattern290having a first mask opening290H may be formed on the seed metal layer221a(S1330). A portion of the seed metal layer221amay be exposed by the first mask opening290H.

The first mask pattern290may be formed, for example, by forming an insulating film on the seed metal layer221aand then performing a patterning process on the insulating film.

In some embodiments, the first mask pattern290may be formed by a film process. For example, to form the first mask pattern290, a photosensitive film may be attached on the seed metal layer221ato cover the seed metal layer221a,and then, a portion of the seed metal layer221amay be exposed through exposure and development processes to form the first mask opening290H.

Referring toFIGS. 9 and 10e, to separate the plurality of wafers10from the tray100, a portion of a structure stacked on the tray100and/or the plurality of wafers10may be removed, and the plurality of wafers10may be separated from the tray100(S1340). At this time, a material remaining between the side walls of the cavities120and the wafers120accommodated in the cavities120may be also removed.

For example, by removing the portion of the structure stacked on the tray100and/or the plurality of wafers10, a separation lane250may be formed. For example, the separation lane250may penetrate the first insulating layer211, the seed metal layer221a,and the first mask pattern290perpendicularly, and extend along the edge of each of the plurality of wafers10. The separation lane250may be in the shape of a ring, as seen from above. By the separation lane250, the space120S between the side walls of the cavities120and the edges of the wafers10may be exposed upward. Further, by the separation lane250, a portion of the edges of the wafers10and/or a portion of the surface of the tray100may also be exposed. The separation lane250may be formed by, for example, a laser drilling method.

Referring toFIGS. 9 and 10f, a first metal layer223may be formed on each of the separated wafers10to fill at least a portion of the first mask opening290H (S1350). The first metal layer223may cover a surface of a portion of the seed metal layer221aexposed through the first mask opening290H.

The first metal layer223may be formed by, for example, a plating method. For example, the first metal layer223may be formed with copper. In some embodiments, the first metal layer223may be formed by a plating method using the seed metal layer221aas a seed. For example, the first metal layer223may be formed by immersion plating, electroless plating, electroplating, or a combination thereof.

In some embodiments, a plating process for forming the first metal layer223may be performed simultaneously on a large number of wafers10than a number (hereinafter, referred to as a ‘tray unit’) of wafers10that can be accommodated in a single tray. For example, the plating process may be performed by immersing a larger number of wafers10than the tray unit in a plating bath500in which an electrolyte is stored. Therefore, a plating process may be performed more efficiently than a case in which a plating process is performed in a tray unit.

Referring toFIGS. 9 and 10g, after the first metal layer223is formed, the first mask pattern290and the seed metal layer (221aofFIG. 10f) located below the first mask pattern290may be removed from the resultant structure ofFIG. 10f(S1360).

To remove the first mask pattern290, an ashing or strip process may be used. Also, after the first mask pattern290is removed, a chemical etching method may be used to remove the seed metal layer (221aofFIG. 10f) located below the first mask pattern290.

In some embodiments, the first metal layer223and the seed metal layer221may be combined into one body to construct a distribution layer220.

Referring toFIGS. 9 and 10h, a plurality of wafers10each being a resultant structure shown inFIG. 10gmay be arranged on the tray100(S1370). The plurality of wafers10may be arranged on the tray100such that the first metal layer223is exposed upward, and the respective wafers10may be accommodated in different cavities120formed in the tray100. In some embodiments, to arrange the wafers10at predetermined positions in the cavities120, a notch portion (see130ofFIG. 2a) and/or an align mark (see140ofFIG. 2a) provided on the tray100may be used.

Meanwhile, inFIG. 10h, the first insulating layer211is shown to remain on the upper surface111of the tray100. However, unlike this, a first mask pattern (see290ofFIG. 10e) may remain on the first insulating layer211. Alternatively, the tray100from which the first insulating layer211has been removed may be used.

After the plurality of wafers10are arranged on the tray100, a second insulating layer213may be formed to cover the upper surface111of the tray100and the plurality of wafers10. The second insulating layer213may cover the first insulating layer211on the tray100, the first insulating layer211on the plurality of wafers10, and the first metal layer223. The second insulating layer213may include an opening to expose a portion of the first metal layer223.

The second insulating layer213may fix the wafers10on the tray100during a subsequent process. Also, the second insulating layer213may cover the space120S between the edges of the wafers10and the side walls of the cavities120. For example, the second insulating layer213may seal up the space120S between the side walls of the cavities120and the edges of the wafers10.

In some embodiments, the second insulating layer213may be formed by a film process, similarly to the first insulating layer211described above with reference toFIG. 10b. The second insulating layer213may include a photosensitive material or a non-photosensitive material.

Referring toFIGS. 9 and 10i, the second metal layer225may be formed to be connected to a portion of the first metal layer223exposed through the second insulating layer213(S1380). In some embodiments, the first insulating layer211, the distribution layer220, the second insulating layer213, and the second metal layer225may construct an interconnect structure200a.

In some embodiments, the second metal layer225may be a under bump metal (UBM). In other embodiments, the second metal layer225may be omitted.

After the second metal layer225is formed, an external connection terminal400may be formed on the second metal layer225. The external connection terminal400may be, for example, a solder ball or a solder bump. The external connection terminal400may electrically connect the semiconductor package with an external device. The external connection terminal400may be electrically connected to the pads13of the wafers10via the seed metal layer221, the first metal layer223, and the second metal layer225. Meanwhile, when the second metal layer225is omitted, the external connection terminal400may be attached on the first metal layer223exposed by the second insulating layer213.

Referring toFIGS. 9 and 10j, the plurality of wafers10may be separated from the tray100(S1390). To separate the plurality of wafers10from the tray100, a portion of a structure stacked on the tray100and/or the plurality of wafers10may be removed to form a separation lane260.

For example, the separation lane260may penetrate the second insulation layer213perpendicularly, and be formed along the edges of each of the plurality of wafers10. By the separation lane260, the space120S between the side walls of the cavities120and the edges of the wafers10may be exposed upward. By the separation lane260, wafer level semiconductor packages including the wafers10and the interconnect structure200formed on the wafers10may be separated from each other. The separation lane260may be formed by, for example, a laser drilling method.

Referring toFIG. 10k, a wafer level semiconductor package1may be separated from the tray (100ofFIG. 10j), and then singulated into a plurality of package unit semiconductor packages through a sawing process. In other words, a sawing blade BL may cut the wafer level semiconductor package1along a scribe lane SL to separate the wafer level semiconductor package1, so that the wafer level semiconductor package1may be singulated into a plurality of package unit semiconductor packages.

Meanwhile, a method of producing the semiconductor package, according to some embodiments of the present disclosure, may perform the substantially same processes as those described above with reference toFIGS. 10ato 10g, and then, the subsequent processes may be performed on each of the plurality of wafers. That is, the subsequent processes may be performed in the state in which the plurality of wafers are not arranged on the tray. For example, by sequentially forming the second insulating layer covering the distribution layer, the second metal layer connected to the distribution layer through the second insulating layer, and the external connection terminal on the second metal layer on the resultant structure shown inFIG. 10g, a semiconductor package process for each of the plurality of wafers may be performed.

FIG. 11is a flowchart showing a method of producing a semiconductor package, according to some embodiments of a technical concept of the present disclosure.

Referring toFIGS. 9 and 11, a part of semiconductor package processes may be performed on wafers in a tray unit, and the other part of the semiconductor package processes may be performed on a larger number of wafers than the tray unit. As described above, semiconductor package processes for a first group of wafers10A in a tray unit and a second group of wafers10B in a tray unit may be performed through operations S100to S500.

In the semiconductor package processes for the first group of wafers10A and the second group of wafers10B, processes that are performed in the state that wafers are arranged on a tray may be performed on each of the first group of wafers10A and the second group of wafers10B, and processes that are performed in the state that the wafers are separated from the tray may be performed on both of the first group of wafers10A and the second group of wafers10B. For example, operation S1350of forming the first metal layer on the seed metal layer exposed through the first mask pattern, and/or operation S1360of removing the first mask pattern and the seed metal layer below the first mask pattern may be performed on both of the first group of wafers10A and the second group of wafers10B.

Meanwhile, in the drawings, operation S350and/or operation S360are shown to process two tray units of wafers at the same time. However, the present disclosure is not limited to this, and operation S350and/or operation S360may be performed on a larger number of waters than two tray units.

FIGS. 12ato 12fare cross-sectional views showing a method of producing a semiconductor package according to some embodiments of a technical concept of the present disclosure, in the order of processes. InFIGS. 12ato 12f, a method of producing a semiconductor package by using the tray100cshown inFIG. 5will be described, and descriptions overlapping with those given above with reference toFIGS. 10ato 10kwill be omitted or briefly given.

Referring toFIG. 12a, a plurality of wafers10may be arranged on the tray100c.An upper surface11of each of the plurality of wafers10, on which a pad13is formed, may be exposed upward, and a lower surface of the wafer10, which is opposite to the upper surface11, may face a surface of the tray100c.To arrange the plurality of wafers10at predetermined positions on the tray100c,an align mark (see140ofFIG. 2a) provided on the tray100cmay be used.

Referring toFIG. 12b, a first insulating layer311covering the surface of the tray100cand the surface of the wafer10and having an opening311H exposing the pad13of the wafer10may be formed. Because the upper surface11of the wafer10has a level that is higher than the surface of the tray100c,the first insulating layer311may have a stepped portion. The first insulating layer311may fix the plurality of wafers10at predetermined positions on the tray100cduring a subsequent process.

After the first insulating layer311is formed, a seed metal layer321amay be formed on the first insulating layer311and the pads13of the wafers10exposed through the opening311H of the first insulating layer311, and a second mask pattern390having a second mask opening3900H may be formed on the seed metal layer321a.

Referring toFIG. 12c, to separate the plurality of wafers10from the tray100c,a portion of a structure stacked on the tray100cand/or the plurality of wafers10may be removed to form a separation lane350. For example, the separation lane350may extend along edges of the plurality of wafers10, and penetrate the first insulating layer311and the seed metal layer321aperpendicularly.

After the portion of the structure stacked on the tray100cand/or the plurality of wafers10is removed by the separation lane350, the plurality of wafers10may be separated from the tray100c.

Referring toFIG. 12d, the substantially same method as the method of forming the first metal layer (223ofFIG. 10f) described above with reference toFIG. 10fmay be performed to form a first metal layer323filling at least one portion of the first mask opening390H for each of the separated wafers10.

Then, the second mask pattern390and the seed metal layer321alocated below the second mask pattern390may be removed by the substantially same method as that described above with reference toFIG. 10g. In some embodiments, the seed metal layer321aand the first metal layer323may construct a distribution layer320.

Referring toFIG. 12e, the plurality of wafers10including a predetermined structure may be arranged on the tray100c,and a second insulating layer313covering the tray100c,the first insulating layer311on the plurality of wafers10, and the distribution layer320may be formed. By the second insulating layer313, the plurality of wafers10may be fixed on the tray100.

Successively, at least a portion of the first metal layer323may be exposed through the second insulating layer313, a second metal layer325connected to the exposed first metal layer323may be formed, and an external connection terminal400may be formed on the second metal layer325.

Referring toFIG. 12f, a portion of a structure stacked on the tray100cand/or the plurality of wafers10may be removed along the edges of the plurality of wafers10to form a separation lane360. For example, the separation lane360may penetrate the second insulating layer213perpendicularly.

After the separation lane360is formed, the wafer level semiconductor package may be separated from the tray100c,and then singulated into a plurality of package unit semiconductor packages through a sawing process.

FIG. 13is a flowchart of a method of producing a semiconductor package according to some embodiments of a technical concept of the present disclosure.FIGS. 14ato 14fare cross-sectional views showing a method of producing a semiconductor package according to some embodiments of a technical concept of the present disclosure, in the order of processes. Hereinafter, a method of producing a semiconductor package by using the tray100shown inFIGS. 2aand 2bwill be described with reference toFIGS. 13 and 14ato14f, and descriptions overlapping with those given above with reference toFIGS. 10ato 10kwill be omitted or briefly given.

Referring toFIGS. 13 and 14a, a first insulating layer212may be formed on each of a plurality of wafers10(S1310a), and the plurality of wafers10may be arranged on the tray100(S1320a). More specifically, the first insulating layer212may be formed on upper surfaces11of the plurality of wafers10on which pads13are formed, and the plurality of wafers10may be accommodated in cavities120such that lower surfaces of the wafers10face bottom surfaces of the cavities120.

Referring toFIGS. 13 and 14b, a seed metal layer221amay be formed to be electrically connected with the pads13of the plurality of wafers10(S1330a). For example, the seed metal layer221amay cover a surface of the tray100and a surface of the first insulating layer212, and be connected to the pads13exposed through an opening211H of the first insulating layer212.

Referring toFIGS. 13 and 14c, a first mask pattern290having a first mask opening290H may be formed on the seed metal layer221a(S1340a). In some embodiments, to form the first mask pattern290, a photosensitive film may be attached on the seed metal layer221ato cover the seed metal layer221a,and then, a portion of the seed metal layer221amay be exposed through exposure and development processes to form the first mask opening290H. In this case, the first mask pattern290may fix the plurality of wafers10on the tray100.

Referring toFIGS. 13 and 14d, a first metal layer223may be formed on the portion of the seed metal layer221aexposed through the first mask pattern290(S1350a). In some embodiments, the first metal layer223may be formed by a plating method using the seed metal layer221aas a seed. For example, to perform a plating process of making a plating jig contact the seed metal layer221ato apply a voltage to the seed metal layer221a,the plating jig may contact the seed metal layer221aprovided on the plurality of wafers10.

Referring toFIGS. 13 and 14e, the first mask pattern290and the seed metal layer (221aofFIG. 14d) located below the first mask pattern290may be removed from the resultant structure ofFIG. 14d(S1360a). In some embodiments, the seed metal layer221and the first metal layer223may construct a distribution layer220.

Referring toFIGS. 13 and 14f, a second insulating layer213may be formed on the tray100and the plurality of wafers10(S1370a). The second insulating layer213may cover the seed metal layer221formed on the upper surface111of the tray100, and also cover the first insulating layer212and the distribution layer220formed on the plurality of wafers10. In some embodiments, the second insulating layer213may fix the plurality of wafers10on the tray100during a subsequent process.

Successively, a second metal layer225may be formed to be connected to a portion of the first metal layer223exposed through the second insulating layer213(S1380a). In some embodiments, the first insulating layer212, the distribution layer220, the second insulating layer213, and the second metal layer225may construct an interconnect structure200a.Thereafter, an external connection terminal may be formed on the second metal layer225.

Thereafter, the plurality of wafers10may be separated from the tray100(S1390a). For example, to separate the plurality of wafers10, a portion of the second insulating layer213may be removed to expose the edges of the plurality of wafers10. The plurality of wafers10separated from the tray100may be singulated into a plurality of package unit semiconductor packages through a sawing process.

Meanwhile, a method of producing the semiconductor package, according to some embodiments of the present disclosure, may perform the substantially same processes as those described above with reference toFIGS. 14ato 14e, and then, the subsequent processes may be performed on each of the plurality of wafers. That is, the subsequent processes may be performed in the state in which the plurality of wafers are not arranged on the tray. That is, by separating the plurality of wafers from the tray in the resultant structure ofFIG. 14e, and sequentially forming the second insulating layer covering the distribution layer, the second metal layer connected to the distribution layer through the second insulating layer, and the external connection terminal on the second metal layer for each of the plurality of wafers, a semiconductor package process for each of the plurality of wafers may be performed.

Meanwhile, inFIGS. 13 to 14f, a method of producing a semiconductor package by using the tray100shown inFIGS. 2aand 2bhas been described, however, methods of producing semiconductor packages by using the trays100a,100b,and100cdescribed above with reference toFIGS. 3 to 5may be performed in the substantially same way as those described above with reference toFIGS. 13 to 14f.

Meanwhile, at least a part of semiconductor package manufacturing processes may be performed in the state in which a plurality of wafers are arranged on a tray. Hereinafter, a method of producing a semiconductor package according to some embodiments of the present disclosure will be described with reference toFIG. 15.

As described above, a method of producing a semiconductor package may include operation S1410of forming a first insulating layer on a wafer, operation S1420of forming a distribution layer connected to a pad of the wafer exposed through the first insulating layer on the first insulating layer, operation S1470of forming a second insulating layer on the distribution layer and the first insulating layer, and operation S1480of forming a second metal layer connected to the distribution layer exposed through the second insulating layer. Operation S1420of forming the distribution layer may include operation S1430of forming a seed metal layer on the first insulating layer and the pad of the wafer exposed through the first insulating layer, operation S1440of forming a first mask pattern on the seed metal layer, operation S1450of forming a first metal layer on a portion of the seed metal layer exposed through the first mask pattern, and operation S1460of removing the first mask pattern and the seed metal layer located below the first mask pattern.

In some embodiments of the present disclosure, a part of operations S410and S480may be performed in the state in which a plurality of wafers are arranged on a tray, and the other part may be performed on each of the plurality of wafers in the state in which the plurality of wafers are separated from the tray. Accordingly, before and/or after each of operations S410to S480, an operation of arranging the plurality of wafers on the tray or operation of separating the plurality of wafers from the tray may be performed.

By the method of producing the semiconductor package, according to embodiments of the present disclosure, a plurality of unit processes of a semiconductor package process may be performed by using a tray capable of supporting a plurality of wafers. That is, because the semiconductor package process is performed by arranging a plurality of wafers on a tray, a plurality of wafer level semiconductor packages may be manufactured in a panel level. Accordingly, by a technical concept of the present disclosure, semiconductor package processes for a plurality of wafers can be performed at the same time, and therefore, productivity may be improved.

Further, by the method of producing the semiconductor package, according to embodiments of the present disclosure, a part of the plurality of unit processes of the semiconductor package process may process the wafers using a tray, and the other part may be performed in the state in which the wafers are separated from the tray. Therefore, the productivity of the semiconductor package process may be further improved.

FIGS. 16ato 16iare cross-sectional views showing a method of producing a semiconductor package according to some embodiments of a technical concept of the present disclosure. InFIGS. 16ato 16i, a method of producing a semiconductor package by using the tray100shown inFIGS. 2aand 2bwill be described.

Referring toFIG. 16a, a plurality of wafers10may be arranged on the tray100. The plurality of wafers10may be respectively accommodated in different cavities120provided in the tray100. Each wafer10may be positioned in the cavity120such that an upper surface11of the wafer10on which a pad13is formed is exposed upward. In other words, the wafer10may be positioned in the cavity120such that a lower surface of the wafer10, which is opposite to the upper surface11, faces a bottom surface of the cavity120. In other words, an active surface of the wafer10may be exposed, and an inactive surface of the wafer10may contact a surface of the tray100.

The wafer10may be positioned in the cavity120in such a way to be spaced from a side wall of the cavity120. Because the side surface of the wafer10is spaced from the side wall of the cavity120, a space120S that opens in an up direction may be formed between the side surface of the wafer10and the side wall of the cavity120.

As shown inFIG. 16a, a depth of the cavity120may be substantially equal to a thickness of the wafer10, and accordingly, the upper surface11of the wafer10positioned in the cavity120and the upper surface111of the body110may have the same height level.

However, when the wafer10is positioned in the cavity120, an upper surface of the body110may have a height level that is different from the upper surface11of the wafer10. For example, the upper surface of the body110may have a level that is lower than the upper surface11of the wafer10.

Referring toFIG. 16b, a first insulating layer211may be formed on the tray100and the plurality of wafers10. The first insulating layer211may have an opening211H to expose at least a portion of the pad13. The first insulating layer211may cover the upper surface111of the body110and the upper surfaces11of the plurality of wafers10.

The first insulating layer211may fix the wafers10positioned in the cavities120during a subsequent process. Also, the first insulating layer211may cover the space120S between the wafers10and the side walls of the cavities120. For example, the space120S between the wafers10and the side walls of the cavities120may be sealed by the first insulating layer211. When an interconnect structure is formed, the first insulating layer211may cover the space120S between the wafers10and the side walls of the cavities120to prevent foreign materials from entering the space120S.

In some embodiments, the first insulating layer211may cover a top area of the space120S between the side surfaces of the wafers10and the side walls of the cavities120such that a material forming the first insulating layer211is not filled in the space120S between the side surfaces of the wafers10and the side walls of the cavities120. Because the material forming the first insulating layer211is not filled in the space120S between the side surfaces of the wafers10and the side walls of the cavities120, the wafers10may be easily separated from the tray100, later.

In some embodiments, the first insulating layer211may be formed by a laminating method. For example, the first insulating layer211may include a photosensitive material. More specifically, to form the first insulating layer211, a photosensitive film may be attached on the upper surface111of the body110and the upper surfaces11of the plurality of wafers10by a laminating method, and then, a portion of the photosensitive film may be removed through exposure and development processes to expose the pads13of the wafers10.

Also, in some embodiments, the first insulating layer211may include a non-photosensitive material. For example, to form the first insulating layer211, a non-photosensitive film may be attached on the upper surface111of the body110and the upper surfaces11of the plurality of wafers10, and then, a portion of the non-photosensitive film may be removed by a laser cutting apparatus to expose the pads13of the wafers10.

The first insulating layer211may be formed with a polymer material such as, for example, polyimide.

Meanwhile, in other embodiments, the first insulating layer211may be formed by a spin-coating method.

Referring toFIG. 16c, a seed metal layer221amay be formed to cover a surface of the first insulating layer211and a surface of the pad13exposed through the opening211H of the first insulating layer211. The seed metal layer221amay be deposited by, for example, a sputtering method, however a method of forming the seed metal layer221ais not limited to the sputtering method. The seed metal layer221amay include any one of, for example, Ti, Cu, Ni, Al, Pt, Au, Ag, W, Ta, Co, or a combination thereof.

Referring toFIG. 16d, a first mask pattern290having a first mask opening290H may be formed on the seed metal layer221a.A part of the seed metal layer221amay be exposed by the first mask opening290H.

The first mask pattern290may be formed, for example, by forming a photosensitive material film on the seed metal layer221aand then performing a patterning process using photolithography technology on the photosensitive material film. For the photolithography process, an exposure mask on which a predetermined pattern is formed may be used, and a laser light source such as KrF or ArF may be used.

In some embodiments, the first mask pattern290may be formed by a laminating method. For example, a photosensitive film may be attached on the seed metal layer221ato cover the seed metal layer221a,and then, a portion of the seed metal layer221amay be exposed through exposure and development processes to form a first mask opening290H.

Referring toFIGS. 16eand 16f, a first metal layer223may be formed to fill at least a portion of the first mask opening290H. The first metal layer223may cover a surface of the portion of the seed metal layer221aexposed through the first mask opening290H.

The first metal layer223may be formed through, for example, a plating method. For example, the first metal layer223may be formed with copper. In some embodiments, the first metal layer223may be formed by a plating method using the seed metal layer221aas a seed. For example, the first metal layer223may be formed by immersion plating, electroless plating, electroplating, or a combination thereof.

More specifically, as shown inFIG. 16e, the tray100on which the plurality of wafers10are arranged may be immersed in a plating bath500, and a plating jig may contact at least one location280on the seed metal layer221a.Successively, as shown inFIG. 16f, when a power supply510applies a voltage to the plating jig520, the first metal layer223may be formed on the surface of the portion of the seed metal layer221aexposed through the first mask opening290H. That is, when power is supplied to an electrolyte stored in the plating bath500and the plating jig520by the power supply510, metal ions contained in the electrolyte may be reduced to a metal to be plated on the portion of the seed metal layer221aexposed through the first mask opening290H. Because a portion of the seed metal layer221aof an area perpendicularly overlapping the plurality of wafers10is electrically connected to the location280that the plating jig520contacts, the first metal layer223may be plated on the seed metal layer221aof the area perpendicularly overlapping the plurality of wafers10.

In some embodiments, the location280on the seed metal layer22awhich the plating jig520contacts may be spaced in a peripheral direction from a portion of the seed metal layer221aon the plurality of wafers10. In other words, the location280on the seed metal layer22awhich the plating jig520contacts may be spaced in a peripheral direction from a predetermined area of the seed metal layer221aperpendicularly overlapping the plurality of wafers10. For example, the location280on the seed metal layer22awhich the plating jig520contacts may be spaced in a peripheral direction from the cavity120. In this case, a plating process may be more simplified than a case of making the plating jig520contact the portion of the seed metal layer221on the plurality of wafers10to perform a plating process.

Also, in some embodiments, the seed metal layer221aformed on the upper surface111of the tray100and the plurality of wafers10and the seed metal layer221aformed on the first insulating layer211may have a substantially uniform thickness. Particularly, when a depth of the cavities120is substantially equal to a thickness of the wafers10accommodated in the cavities120, the seed metal layer221amay be parallel to the upper surface111of the tray100around the space between the side walls of the cavities120and the wafers10accommodated in the cavities120. Also, a thickness of a portion of the seed metal layer221aabove the space between the side walls of the cavities120and the wafers10accommodated in the cavities120may be substantially equal to that of the portion of the seed metal layer221aon the plurality of wafers10. Because the seed metal layer221ahas a substantially uniform thickness, power applied to the at least one location280on the seed metal layer221afrom the plating jig520may be more uniformly transferred to the entirety of the seed metal layer221a.

Meanwhile, referring toFIG. 16g, in some embodiments, a location280aon the seed metal layer221which the plating jig520contacts may be in the portion of the seed metal layer221aon the plurality of wafers10. In other words, the location280aon the seed metal layer221which the plating jig520contacts may be in a predetermined area of the seed metal layer221aperpendicularly overlapping the plurality of wafers10. When the plating jig520contacts the location280ain portions of the seed metal layer221aon the plurality of wafers10and power is applied to the plating jig520, the portions of the seed metal layers221aon the plurality of wafers10may be electrically connected to each other so that the first metal layer223may be formed on the portions of the seed metal layer221aon the plurality of wafers10.

Referring toFIG. 16h, after the first metal layer223is formed, the first mask pattern290and the seed metal layer (221aofFIG. 16g) located below the first mask pattern290may be removed from the resultant structure ofFIG. 16e.

To remove the first mask pattern290, an ashing or strip process may be used. Also, to remove the seed metal layer (221aofFIG. 16g) located below the first mask pattern290after the first mask pattern290is removed, a chemical etching method may be used.

In some embodiments, the first metal layer223and the seed metal layer221may be combined into one body to construct a distribution layer220.

Referring toFIG. 16i, a second insulating layer213covering the first metal layer223may be formed, and successively, a second metal layer225penetrating the second insulating layer213to be connected to the first metal layer223may be formed. In some embodiments, the first insulating layer211, the distribution layer220, the second insulating layer213, and the second metal layer225may construct an interconnect structure200a.

In some embodiments, the second insulating layer213may be formed by a laminating method, like the first insulating layer211described above with reference toFIG. 16b. The second insulating layer213may include a photosensitive material or a non-photosensitive material.

In some embodiments, the second metal layer225may be a UBM. In other embodiments, the second metal layer225may be omitted.

Referring toFIG. 16j, an external connection terminal400may be formed on the second metal layer225. The external connection terminal400may be, for example, a solder ball or a solder bump. The external connection terminal400may electrically connect the semiconductor package with an external device. The external connection terminal400may be electrically connected to the pad13of the wafer10via the seed metal layer221, the first metal layer223, and the second metal layer225. Meanwhile, when the second metal layer225is omitted, the external connection terminal400may be attached on the first metal layer223exposed by the second insulating layer213.

Referring toFIG. 16k, to separate the plurality of wafers10from the tray100, a portion of a structure stacked on the tray100and/or the plurality of wafers10may be removed. At this time, a material remaining between the side walls of the cavities120and the wafers120accommodated in the cavities120may be also removed.

For example, by removing a portion of the structure stacked on the tray100and/or the plurality of wafers10, a separation lane250may be formed in the interconnection structure200. The separation lane250may penetrate the first insulating layer211and the second insulating layer213perpendicularly, and be formed along the edges of each of the plurality of wafers10. The separation lane250may be in the shape of a ring, as seen from above. By the separation lane250, the space120S between the side walls of the cavities120and the edges of the wafers10may be exposed upward. Further, a portion of the edges of the wafer10and/or a portion of the surface of the tray100may be exposed. By the separation lane250, wafer level semiconductor packages including the wafers10and the interconnect structure200formed on the wafers10may be separated from each other.

The separation lane250may be formed by, for example, a laser drilling method.

Referring toFIG. 16I, a wafer level semiconductor package1may be separated from the tray100, and then singulated into a plurality of package-unit semiconductor packages through a sawing process. In other words, a sawing blade BL may cut the wafer level semiconductor package1along a scribe lane SL to separate the wafer level semiconductor package1. As a result, the wafer level semiconductor package1may be singulated into a plurality of package unit semiconductor packages.

FIGS. 17ato 17gare cross-sectional views showing a method of manufacturing a semiconductor package according to some embodiments of a technical concept of the present disclosure. InFIGS. 17ato 17g, a method of manufacturing a semiconductor package by using the tray100cshown inFIG. 5will be described, and descriptions overlapping with those given above with reference toFIGS. 16ato16I will be omitted or briefly given.

Referring toFIG. 17a, a plurality of wafers10may be arranged on the tray100c.An upper surface11of each wafer10on which a pad13is formed may be exposed, and a lower surface of the wafer10, which is opposite to the upper surface11, may face a surface of the tray100c.To arrange the plurality of wafers10at predetermined locations on the tray100c,an align mark (140ofFIG. 2a) provided on the tray100cmay be used.

Referring toFIG. 17b, a first insulating layer311covering the surface of the tray100cand the surface of the wafer10and having an opening311H exposing the pad13of the wafer10may be formed. Because the upper surface11of the wafer10has a level that is higher than the surface of the tray100c,the first insulating layer311may have a stepped portion. The first insulating layer311may fix the plurality of wafers10at predetermined positions on the tray100cduring a subsequent process.

After the first insulating layer311is formed, a seed metal layer321amay be formed on the first insulating layer311and the pads13of the wafers10exposed through the opening311H of the first insulating layer311, and a second mask pattern390having a second mask opening3900H may be formed on the seed metal layer321a.

Referring toFIGS. 17cand 17d, more specifically, the tray100con which the plurality of wafers10are arranged may be immersed in a plating bath500, and a plating jig520may contact at least one location380on the seed metal layer321a.Successively, when a power supply510applies a voltage to the plating jig520, a first metal layer323may be formed on a surface of a portion of the seed metal layer321aexposed through the first mask opening390H.

In some embodiments, as shown in the drawings, the at least one location380on the seed metal layer321awhich the plating jig520contacts may be spaced in a peripheral direction from the portion of the seed metal layer321aon the plurality of wafers10. That is, the plating jig520may be located in another area except for an area where the plurality of wafers10are arranged, on an upper surface111bof the tray100c.

Or, in other embodiments, as shown inFIG. 17e, at least one location380aon the seed metal layer321which the plating jig520contacts may be in the portion of the seed metal layer321aon the plurality of wafers10.

Referring toFIG. 17f, the first mask pattern390and the portion of the seed metal layer321alocated below the first mask pattern390may be removed from the resultant structure ofFIG. 17d. Thereafter, a second insulating layer313, a second metal layer323, and an external connection terminal400may be formed sequentially through the substantially same process as that described above with reference toFIGS. 16iand16j.

Referring toFIG. 17g, a portion of an interconnect structure (300aofFIG. 17e) may be removed along the edges of the plurality of wafers10to form a separation lane350. For example, a portion of the second insulating layer313, a portion of the first metal layer323, a portion of the seed metal layer321, and a portion of the first insulating layer311may be removed along the edges of the plurality of wafers10to expose the edges of the plurality of wafers10. By the separation lane350, wafer level semiconductor packages including the wafers10and the interconnect structure200formed on the wafers10may be separated from each other.

After the separation lane350is formed, the wafer level semiconductor packages may be separated from the tray100c.Each of the separated wafer level semiconductor packages may be singulated into a plurality of package unit semiconductor packages through a sawing process.

By the method of producing the semiconductor package, according to the embodiments of the present disclosure, a plurality of unit processes of a semiconductor package process may be performed by using a tray capable of supporting a plurality of wafers. That is, because the semiconductor package process is performed by arranging a plurality of wafers on a tray, a plurality of wafer level semiconductor packages may be manufactured in a panel level. Accordingly, by the technical concept of the present disclosure, semiconductor package processes for a plurality of wafers can be performed at the same time, and therefore, productivity may be improved.

FIGS. 18ato 18care views conceptually showing a plating process in a method of producing a semiconductor package according to some embodiments of a technical concept of the present disclosure. InFIGS. 18ato 18c, for convenience of description, wafers arranged on the tray and structures formed on the tray and the wafers are not shown. Also, hereinafter, a part of a method of producing a semiconductor package by using the tray100shown inFIGS. 2aand 2bwill be described.

Referring toFIGS. 18aand 18b, the number of locations280bat which the plating jig520contacts the seed metal layer (see221aofFIG. 16e) may be less than the number of wafers arranged on the tray100.

In some embodiments, as shown inFIG. 18a, for the tray100on which four wafers can be arranged, a plating jig520may contact two locations280bon an upper surface111of the tray100to apply power for a plating process to the seed metal layer.

The two locations280bat which the plating jig520contacts the seed metal layer may be spaced in a peripheral direction from areas where the wafers are arranged on the upper surface111of the tray100. That is, the two locations280bmay be spaced in a peripheral direction from the cavities120on the upper surface111of the tray100. Also, the two locations280bmay be adjacent to two different corners of the upper surface111of the tray100.

In some embodiments, as shown inFIG. 18b, two locations280cwhich the plating jig520contacts the seed metal layer may be spaced in a peripheral direction from areas where the wafers are arranged, on the upper surface111of the tray100, and the two locations280cmay be adjacent to centers of edges of the upper surface111of the tray100.

Referring toFIG. 18c, the number of locations280dat which the plating jig520contacts the seed metal layer (see221aofFIG. 16e) may be equal to the number of wafers arranged on the tray100. For example, for the tray100on which four wafers can be arranged, the plating jig520may contact four locations280don the upper surface111of the tray100to apply power for a plating process to the seed metal layer. For example, when the plating jig520contacts four locations280don the upper surface111of the tray100, each of the four locations280dmay apply power for a plating process to the seed metal layer formed on the respective wafers accommodated in four cavities120.

Meanwhile, inFIGS. 18ato 18c, a plating process of a case of using the tray100shown inFIGS. 2aand 2bhas been described, however, plating processes using the trays100a,100b,and100cas described above with reference toFIGS. 3 to 5may also be performed in the substantially same way as that described above with reference toFIGS. 18ato18c.

FIG. 19ais a perspective view of a tray100daccording to some embodiments of the present disclosure.FIG. 19bis a cross-sectional view of the tray100dofFIG. 19a, taken along line VIB-VIB′, showing a state in which a plurality of wafers10are arranged on the tray100d.The tray100dshown inFIGS. 19aand 19bmay have substantially the same configuration as that of the tray100cshown inFIG. 5except that the tray100dfurher includes a pattern150. InFIGS. 19aand19B, the same reference numerals as those used inFIG. 5indicate the same components, and therefore, detailed descriptions about the components will be omitted or briefly given.

Referring toFIGS. 19aand 19b, the tray100dmay include the pattern150provided on the upper surface111bof the body110b.The pattern150may define a wafer arrangement area113on which the plurality of wafers10may be arranged. In some embodiments, the pattern150and/or an align mark140may be used to arrange the plurality of wafers10on a plurality of wafer arrangement areas113. By the pattern150, an error by which the wafers10arranged on the tray100ddeviate from predetermined locations may be reduced.

The pattern150may be exposed upward, and may be in the shape of a ring, as seen from above. In this case, an inside area of the pattern150in the shape of a ring may be defined as the wafer arrangement area113. In the drawings, the pattern150is shown to be in the shape of a continuously extending ring, however, the shape of the pattern150is not limited thereto. For example, the pattern150may be discontinuous, and may be in the shape of a ring whose a portion is cut off. The pattern150may be formed with, for example, copper, although not limited thereto.

FIG. 20ais an exploded perspective view of a tray100eaccording to some embodiments of the present disclosure.FIG. 20bis a cross-sectional view showing a state in which a plurality of wafers10are arranged on the tray100eofFIG. 20a. The tray100eshown inFIGS. 20aand 20bmay have substantially the same configuration as that of the tray100shown inFIGS. 2aand 2bexcept that the tray100eincludes a first body110_1and a second body110_2. InFIGS. 20aand 20b, the same reference numerals as those used inFIGS. 2aand 2bindicate the same components, and therefore, detailed descriptions about the components will be omitted or briefly given.

Referring toFIGS. 20aand 20b, the tray100emay include a body100chaving the first body110_1and the second body110_2that may be separated from or coupled with each other. The first body110_1may be in the shape of a flat plate. The second body110_2may be positioned on the first body110_1, and include a plurality of holes121penetrating the second body110_2. When the first body110_1is coupled with the second body110_2, the first body110_1may be positioned below the second body110_2to block one sides of the plurality of holes121.

As shown inFIG. 20b, when the first body110_1is coupled with the second body110_2, the first body110_1may block one sides of the plurality of holes121, and therefore, recess areas for accommodating the plurality of wafers10may be formed in the tray100e.While at least a part of a semiconductor package process is performed, the plurality of wafers1may be respectively accommodated in the plurality of holes121. When the plurality of wafers10are accommodated in the plurality of holes, lower surfaces of the plurality of wafers10may face the first body110_1, and side portions of the plurality of wafers10may face side walls provided by the plurality of holes121.

Meanwhile, because the first body110_1is couled with or separated from the second body110_2, the wafers10may be more easily separated from the tray100eafter an interconnect structure (for example, see200ofFIG. 6i) is formed. That is, by separating the second body110_2from the first body110_1, the side portions of the plurality of wafers10may be exposed so that the wafers10may be prevented from being damaged when being separated.

FIG. 21is a cross-sectional view showing a state in which a plurality of wafers10are arranged on a tray100f according to some embodiments of a technical concept of the present disclosure. The tray100f shown inFIG. 21may have substantially the same configuration as the tray100shown inFIGS. 2aand 2bexcept for the shape of cavities120a.InFIG. 21, the same reference numerals as those used inFIGS. 2aand 2bindicate the same components, and therefore, detailed descriptions about the components will be omitted or briefly given.

Referring toFIG. 21, side walls of the cavities120amay be inclined. For example, the cavities120aformed in an upper portion of the body110dmay be narrowed from top to bottom. In other words, a horizontal width of the cavities120amay be smaller as being closer to bottom surfaces of the cavities120a.

Because the side walls of the cavities120aare inclined, the wafers10may be more easily arranged in the cavities120aof the tray100f.Furthermore, because the cavities120aare widened upward, the wafers10may be prevented from being damaged due to collision with the side walls of the cavities120awhen being separated.

As described above, exemplary embodiments are disclosed in the specification and drawings. Specific terms used in the present specification should be considered for purposes for describing the technical concept of the present disclosure, not for purposes for limiting the meanings or the scope of the present disclosure written in the claims. Therefore, it will be understood by those of ordinary skill in the art that various modifications or other equivalent embodiments may be made from the embodiments. Accordingly, the true technical protecting range of the present disclosure should be determined according to the technical concept of the attached claims.