Extended drain metal oxide semiconductor transistor and manufacturing method thereof

A MOS transistor having an extended drain structure and including a semiconductor substrate formed in a well of a first conductivity type. A gate insulating layer is formed on the substrate, a gate electrode is formed on the gate insulating layer, and a source region is formed in a first portion of the substrate, which is near to one side of the gate insulating layer and the gate electrode. A drain region is formed in a second portion of the substrate, which is near to another side of the gate insulating layer and the gate electrode. The second portion is recessed from the surface of the substrate by a predetermined depth.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to and the benefit of Korean Patent Application No. 10-2005-0066432 filed in the Korean Intellectual Property Office on Jul. 21, 2005, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to semiconductor technologies, and more specifically, to metal-oxide-semiconductor (MOS) transistors having an extended drain structure and fabrication method thereof.

2. Description of the Related Art

In semiconductor devices, MOS transistors having an extended drain structure have been developed to improve a breakdown voltage of the conventional transistors. The extended drain MOS transistors are widely used for high power devices.

Referring toFIG. 1, the conventional extended drain MOS transistor is explained in terms of its structure and fabrication method. InFIG. 1, an N-channel MOS transistor is shown.

Dopants of a first conductivity type (e.g., boron) are injected into a silicon semiconductor substrate10to form a P well12. Then, a shallow trench isolation is formed to define field and active regions. In the active regions where electronic circuitries including MOS transistors are to be formed, a gate oxide and polysilicon are sequentially deposited on the substrate10. Through a photolithographic process, the gate oxide and polysilicon are patterned to form a gate stack consisted of a gate insulating layer14and a gate electrode16.

With the gate electrode16as a mask, the dopants having lower density and opposite charge to the P-channel well12(e.g., phosphorous or arsenic) are injected into the substrate to form lightly doped source region22aand light doped drain region (LDD region)24a.

After forming the regions22aand24a, insulating material is formed on the entire surface of the substrate10by low pressure chemical vapor deposition (LPCVD) and the deposited insulating material is selectively etched to leave material at the sidewalls of the gate electrode16. The remaining insulating material forms a sidewall spacer18that enables the self-aligned process of the heavily doped drain region and electrically separates the gate electrode from the source/drain regions in subsequent salicide process.

With the gate electrode16and the sidewall spacer18as a mask, dopants having higher density and opposite charge to the P-channel well12(e.g., phosphorous or arsenic) are injected into the substrate10to form source/drain regions22and24. In this process, a photoresist pattern (PR1) is used as shown inFIG. 1to form an extended drain structure. The photoresist pattern (PR1) covers parts of the gate electrode16and drain region, and extends, in a horizontal direction on the substrate, to a predetermined distance, g, from the edge of the sidewall spacer18near to the drain region. As a result, the highly doped drain region24is formed to be distant by distance, g, from the gate electrode16.

As explained above, the conventional extended drain MOS transistor has the highly doped drain region24remote from the gate polysilicon16for obtaining a breakdown voltage required by a design rule. However, the integration of the MOS transistor in a horizontal direction is degraded as the distance between the highly doped drain region and the gate electrode increases.

SUMMARY OF THE INVENTION

It is an object of the present invention to assure a breakdown voltage required by a design rule, while improving integration in a horizontal direction.

In a first aspect, embodiments of the present invention are directed to a MOS transistor having an extended drain structure and comprising: a semiconductor substrate formed in a well of a first conductivity type; a gate insulating layer formed on the substrate; a gate electrode formed on the gate insulating layer; a source region formed in a first portion of the substrate, which is near to one side of the gate insulating layer and the gate electrode; and a drain region formed in a second portion of the substrate, which is near to other side of the gate insulating layer and the gate electrode, where the second portion is recessed from the surface of the substrate by a predetermined depth.

In a second aspect, embodiments of the present invention are directed to a method for fabricating a MOS transistor, comprising the steps of: forming a well of a first conductivity type in a semiconductor substrate; sequentially depositing a gate insulating layer and a gate conducting layer on the substrate; forming a gate stack by patterning the gate insulating layer and the gate conducting layer; forming a photoresist pattern, which covers the surface of the substrate and opens a portion of the substrate at one side of the gate stack; etching the portion of the substrate, which is opened by the photoresist pattern, to a predetermined depth to form a recessed region in the substrate; and injecting dopants of second conductivity type into the substrate to form a drain region in the recessed region of the substrate at the one side of the gate stack and to form a source region in surface region of the substrate at another side of the gate stack.

Preferably, the semiconductor substrate is a silicon substrate, the gate conducting layer is made of polysilicon, and the protective layer includes a first silicon oxide layer and a first silicon nitride layer. The first silicon oxide layer is formed on the gate conducting layer and the first silicon nitride layer is formed on the first silicon oxide layer.

These and other aspects of embodiments of the invention will become evident by reference to the following description of embodiments, often referring to the accompanying drawings.

DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION

Referring toFIG. 2, an extended drain MOS transistor of the present invention is explained. The embodiment ofFIG. 2is N-channel MOS transistor. However, a person of ordinary skill in the art would easily understand that the present invention could be applied to P-channel MOS transistor.

A P-well120of a first conductivity type (e.g, boron) is formed in a silicon semiconductor substrate100. On the substrate100, a gate electrode160of polysilicon and an insulating layer140are formed to have a predetermined width. At one side of the insulating layer140and the gate electrode160, a source region220of a second conductivity type, which is opposite in charge to the first conductivity type (e.g., phosphorous or arsenic), is formed. At the other side of the insulating layer140and the gate electrode160, a drain region240of the second conductivity type is formed. At both sides of the gate electrode160and the insulating layer140, a pair of sidewall spacers180and180aare formed. Under the sidewall spacers180and180a, lightly doped source/drain regions220aand240aare formed in the substrate.

According to an embodiment of the present invention, the drain region240is formed in a recessed region “R,” which is formed by, e.g., etching the substrate100to a predetermined depth. Therefore, the drain region240is placed lower than the source region220by depth “D” from the surface of the substrate100. With this structure of a recessed drain, the drain is distant, in a vertical direction of the substrate, from the gate electrode160and thus the breakdown voltage required by a design rule can be met. Furthermore, in a horizon direction, the drain region240has a minimum distance from the gate electrode160, which leads to highly improved integration in the horizon direction of the substrate when compared to the conventional extended drain MOS transistor.

On the gate electrode160, a protective layer can be formed. When the gate material is polysilicon, it is preferable to make the protective layer with a silicon oxide layer162and a silicon nitride layer164. The features of the protective layer will be explained below.

FIGS. 3A to 3Dare cross-sectional views for illustrating the method for fabricating the extended drain MOS transistor according to the present invention.

Referring toFIG. 3A, gate oxide140aand polysilicon160aare deposited on the silicon substrate100in which a well120of a first conductivity type is formed. In an embodiment, on the polysilicon160a, silicon oxide162aand silicon nitride164acan be deposited for protecting the polysilicon160a. The silicon nitride164ais to protect the polysilicon160afrom being etched during the formation of the recessed region “R” as shown inFIG. 3C. The silicon oxide162aprevents stress from the silicon nitride164ato the polysilicon160a.

Referring toFIG. 3B, the gate oxide140aand polysilicon160aare patterned by a photolithographic process to form a gate stack including the gate oxide layer140and gate electrode160. When the protective materials162aand164aare deposited on the polysilicon160a, they are etched to form protective layers162and164during the formation of the gate stack.

Referring toFIG. 3C, a photoresist is deposited on the substrate100and patterned to open a region of the substrate where the drain is to be formed. Thus, photoresist pattern (PR2) covers the entire surface of the substrate except for the region for a drain. For alignment margin, the photoresist pattern (PR2) can partly cover the top surface of the electrode160. Since the photoresist pattern (PR2) partly covers the gate electrode160, the gate electrode can be etched or damaged during the subsequent process for forming the recessed region in the substrate. The silicon nitride layer164of the protective layer can prevent the damage of the gate electrode160.

With the photoresist pattern (PR2) as a mask, the exposed region of the substrate for drain is etched by a predetermined depth “D” to form a recessed region “R”. When a wet etching method is employed for the formation of the recessed region, an undercut can occur in the lower portion of the gate electrode160. Therefore, it is preferable to form the recessed region by a dry etching method.

Referring toFIG. 3D, after forming the recessed region, the photoresist pattern (PR2) is removed. Then an oxide layer166and oxide layers122and124are formed on sidewalls of the gate electrode160and the surface of substrate, respectively, by, e.g., a thermal oxidation. The sidewall oxide166mitigates the concentration of electric fields to lower edges of the gate electrode160, while the oxide layers122and124prevent the substrate surface from being damaged by a subsequent ion implantation process.

Subsequently, a first ion implantation process for forming lightly doped source/drain regions, a process for forming sidewall spacers, and a second ion implantation process for forming heavily doped source/drain regions are carried out to form the extended drain MOS transistor structure ofFIG. 2.

More specifically, with the gate electrode160as a mask, the dopants having lower density and opposite charge to the P-channel well120(e.g., phosphorous or arsenic) are injected into the substrate to form a lightly doped source region220aand a lightly doped drain region240a.

After forming the regions220aand240a, insulating material is deposited on the entire surface of the substrate100by LPCVD and the deposited insulating material is selectively etched with leaving at the sidewalls of the gate electrode160to form sidewall spacers180.

With the gate polysilicon160and the sidewall spacer180as a mask, dopants having higher density and opposite conductivity type to the P-channel well120(e.g., phosphorous or arsenic) are injected into the substrate100to form heavily doped source/drain regions220and240. In this process, the heavily doped drain region240is formed in the recessed region “R.” Therefore, the heavily doped drain region240has boundary distance from the gate electrode160, which leads to a MOS transistor having a breakdown voltage required by a design rule. By controlling the depth “D” of the recessed region “R,” the distance in a vertical direction from the heavily doped drain region240and the gate electrode160can be adjusted.