Synchronization circuit

A synchronization circuit includes a state detection circuit for outputting a control signal according to the temporal relationship between a transition point of an input signal and an edge of a synchronization clock, a delay selection circuit for adding a delay to the input signal based on the control signal, and a latch circuit for synchronizing the signal outputted from the delay selection circuit with the synchronization clock. Therefore, synchronization of the input signal can be carried out without adding latency to the input signal.

FILED OF THE INVENTION

The present invention relates to a synchronization circuit for synchronizing an asynchronously inputted signal with a clock, in a digital signal transmission apparatus.

BACKGROUND OF THE INVENTION

A conventional synchronization circuit synchronizes an asynchronously inputted signal with a synchronization clock, and outputs the synchronized signal (refer to Japanese Published Patent Application No. 5-327676 and USP4965814). Hereinafter, the conventional synchronization circuit will be described with reference to FIG.17.

FIG. 17is a block diagram illustrating the construction of the conventional synchronization circuit.

With reference toFIG. 17, a flip-flop1receives an input signal SIN that is asynchronous to a synchronization clock SCK and an inverse clock nSCK that is output from an inverter5, and the flip-flop1latches the input signal SIN at a timing of a rising edge of the inverse clock nSCK. A flip-flop2receives the input signal SIN and the synchronization clock SCK, and latches the input signal SIN at a timing of a rising edge of the synchronization clock SCK. A flip-flop3receives a signal that is selected by a selection circuit4and the synchronization clock SCK, and outputs a synchronizing signal SOUT at a timing of the rising edge of the synchronization clock SCK. The selection circuit4selects either the output of the flip-flop1or the output of the flip-flop2based on a control signal CTL that is output from a switching control circuit6. The inverter5receives the synchronization clock SCK, and outputs the an inverse clock nSCK that is obtained by inverting the synchronization clock SCK. The switching control circuit6outputs a control signal CTL according to the temporal relationship between a transition point of the input signal SIN and an edge of the synchronization clock SCK.

Hereinafter, the operation of the conventional synchronization circuit as constructed in the manner as described above with reference toFIG. 17will be described.

The asynchronous input signal SIN is applied to respective data terminals D of the flip-flops1and2.

When the inverse clock nSCK that is outputted from the inverter5is input to the flip-flop1through a clock input terminal CK, the flip-flop1latches the input signal SIN at a timing of the rising edge of the inverse clock nSCK, and outputs the signal to the selection circuit4through a data output terminal Q.

Further, when the synchronization clock SCK is input to the flip-flop2through a clock input terminal CK, the flip-flop2latches the input signal SIN at a timing of the rising edge of the synchronization clock SCK, and outputs the signal to the selection circuit4through a data output terminal Q.

On the other hand, the switching control circuit6monitors the temporal relationship between the transition point of the asynchronous input signal SIN and the edge of the synchronization clock SCK, and outputs the control signal CTL when detecting that the temporal relationship approaches a predetermined period of time, to thereby control the selection circuit4.

The flip-flop3latches the signal that is selected by the selection circuit4at a timing of the rising edge of the synchronization clock SCK, and outputs a synchronizing signal SOUT through a data output terminal Q.

In this way, the asynchronous input signal SIN is synchronized with the synchronization clock SCK.

However, the signal which is latched at the inverse clock nSCK has already been output from the selection circuit4when the switching control circuit6detects that the transition point of the asynchronous input signal SIN approaches the edge of the synchronous clock SCK, and this signal is again latched at the synchronization clock SCK by the third flip-flop3, and as a result, a latency is undesirably added to the signal.

Furthermore, there are many cases where plural pieces of asynchronous signals are input in recent multi-channel digital transmission, and skews between the plural input signals adversely affect data transmission as the input signals become faster. Since, in the conventional technique, there is a possibility that a latency is added to each inputted signal, such skews cause a serious problem in data transmission in which error-free signal synchronization should be carried out.

SUMMARY OF THE INVENTION

The present invention is made to solve the above-described problems, and the object of the present invention to provide a synchronization circuit which can prevent the addition of latency to an input signal, and which is reduced in circuit scale.

Other objects and advantages of the present invention will become more apparent from the detailed description that follows. The detailed description and specific embodiments described herein are provided only for illustration since various additions and modifications within the scope of the present invention will be apparent to those of skill in the art from the detailed description.

According to a first aspect of the present invention, there is provided a synchronization circuit for receiving an input signal and a clock having a frequency which is equal to a transfer rate of the input signal, and synchronizing the input signal with the clock. The synchronization circuit of the first aspect comprises: a state detection circuit for outputting a control signal according to the temporal relationship between a transition point of the input signal and an edge of the clock; a delay selection circuit for adding a delay to the input signal based on the control signal outputted from the state detection circuit; and a latch circuit for synchronizing the signal that outputted from the delay selection circuit with the clock, and outputting the synchronized signal. Therefore, the input signal can be synchronized with the inputted clock without needing to invent the input signal as in the conventional circuit. As a result, a synchronization circuit that can perform the above-described synchronization without adding latency to the input signal can be implemented with a relatively simple construction.

According to a second aspect of the present invention, there is provided a synchronization circuit for receiving an input signal and a clock having a frequency which is equal to a transfer rate of the input signal, and for synchronizing the input signal with the clock. The synchronization circuit of the second aspect comprises: a state detection circuit for outputting a control signal according to the temporal relationship between a transition point of the input signal and an edge of the clock; a delay selection circuit for adding a delay to the clock based on the control signal outputted from the state detection circuit; and a latch circuit for synchronizing the input signal with the clock that is outputted from the delay selection circuit, and outputting the synchronized signal. Therefore, the input signal can be synchronized with the inputted clock without needing to invert the input signal as in the conventional circuit. As a result, a synchronization circuit that can perform the above-described synchronization without adding latency to the input signal can be implemented with a relatively simple construction.

According to a third aspect of the present invention, there is provided a synchronization circuit for receiving plural input signals having phases which are irrelevant to each other and a clock having a frequency which is equal to a transfer rate of the plural input signals, and for synchronizing the plural input signals with the clock. The synchronization circuit of the third aspect comprises: a state detection circuit for outputting control signals relating to the respective input signals according to the temporal relationship between transition points of the plural input signals; a delay selection circuit for adding delays to the respective input signals based on the control signals relating to the respective input signals; and a latch circuit for synchronizing the respective signals outputted from the delay selection circuit with the clock, and outputting the synchronized signals. Therefore, each input signal can be synchronized with the inputted clock without needing to invert the input signal as in the conventional circuit. As a result, a synchronization circuit that can perform the above-described synchronization without adding latency to the input signal can be implemented with a relatively simple construction.

According to a fourth aspect of the present invention, there is provided a synchronization circuit for receiving plural signal bundles each comprising a set of plural input signals which are synchronized with each other and a single clock having a frequency which is equal to a transfer rate of the plural input signals, in which the phases of the input signals which are included in one signal bundle are irrelevant to the phases of the input signals which are included in the other signal bundles, and for synchronizing the input signals which are included in one signal bundle with the input signals which are included in the other signal bundles by using a single synchronization clock that is selected from among the clocks which are included in the respective signal bundles. The synchronization circuit of the fourth aspect comprises: a state detection circuit for detecting the state between the plural input signals which are included in the respective signal bundles; a clock selection circuit for receiving the clocks which are included in the respective signal bundles, and selecting one of the inputted clocks, as a synchronization clock, based on the result of the state detection performed between the respective signal bundles by the state detection circuit; a delay selection circuit for adding delays to the plural input signals which are included in each signal bundle based on the result of the state detection performed between the respective signal bundles; and a latch circuit for synchronizing the output signal from the delay selection circuit for each signal bundler with the synchronization clock, and outputting the synchronized signal. Therefore, the plural signal bundles which are inputted asynchronously with each other can be synchronized with each other without inverting the plural input signals which are included in the respective signal bundles. As a result, a synchronization circuit that can perform synchronization without adding latency to the input signals can be implemented with relatively simple construction.

According to a fifth aspect of the present invention, in accordance with the synchronization circuit of the fourth aspect, the state detection circuit comprises: an early/late detection circuit for detecting which signal bundle is earlier in input timing between the respective signal bundles, and outputting an early/late detection signal; and an overlap detection circuit for detecting an overlap period between the respective signal bundles, and outputting an overlap detection signal. Further, according to the fifth aspect, the clock selection circuit selects, as a synchronization clock, a clock that is included in a signal bundle which is determined as being inputted earlier between the respective signal bundles based on the early/late detection signal, Moreover, the delay selection circuit adds delays based on the early/late detection signal and the overlap detection signal, to the plural input signals which are included in the respective signal bundles. Therefore, a synchronization circuit that can synchronize plural signal bundles regardless of the presence or absence of an overlap period between data to be synchronized, which data are included in the respective signal bundles, can be implemented with a relatively simple construction.

According to a sixth aspect of the present invention, in accordance with the synchronization circuit of the first aspect, the delay selection circuit comprises: a delay circuit for adding a delay to the input signal; and a selection circuit for selecting either the input signal or the output signal of the delay circuit based on the control signal outputted from the state detection circuit. Since a delay is added to the input signal based on the control signal, it becomes unnecessary to invert the input signal as in the conventional circuit, thereby resulting in a synchronization circuit that can avoid the addition of latency to the input signal.

According to a seventh aspect of the present invention, in accordance with the synchronization circuit of the second aspect, the delay selection circuit comprises: a delay circuit for adding a delay to the inputted clock; and a selection circuit for selecting either the inputted clock or the clock that is outputted from the delay circuit based on the control signal outputted from the state detection circuit. Therefore, a synchronization clock, which is obtained by adding a delay to the clock based on the control signal, can be used for synchronizing the input signal. As a result, it becomes unnecessary to invert the input signal as in the conventional circuit, thereby resulting in a synchronization circuit that can avoid the addition of latency to the input signal.

According to an eighth aspect of the present invention, in accordance with the synchronization circuit of the third aspect, the delay selection circuit comprises: a delay circuit for adding delays to the respective input signals; and a selection circuit for selecting one from among the plural input signals and the signals which are outputted from the delay circuit, for each of the plural input signals, based the control signals relating to the respective input signals, and for outputting the selected signal. Since a delay is added to each input signal based on each control signal, it becomes unnecessary to invert the input signal as in the conventional circuit, thereby resulting in a synchronization circuit that can avoid the addition of latency to the input signal.

According to a ninth aspect of the present invention, in accordance with the synchronization circuit of any one of the first through fifth aspects, the state detection circuit detects the state of the input signal based on an externally supplied preamble detection signal which indicates the positional relationship of the data to be synchronized. Therefore, the positional relationship of the data to be synchronized can be easily determined.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Hereinafter, embodiments of the present invention will be described with reference to the drawings. The embodiments described herein are merely examples, and the present invention is not restricted thereto.

First Embodiment

Hereinafter, a synchronization circuit according to a first embodiment of the present invention will be described with reference toFIGS. 1 and 2.

FIG. 1is a waveform diagram illustrating an asynchronous input signal SIN that is input to a synchronization circuit according to the present invention, wherein a period Ts is a signal definite period in which a set-up hold time of the signal SIN is ensured, and a period Td is a signal indefinite period in the vicinity of a transition point of the asynchronous input signal SIN.

FIG. 2is a block diagram illustrating the construction of the synchronization circuit according to the first embodiment.

The synchronization circuit shown inFIG. 2is provided with a state detection circuit102for outputting a control signal CTL according to the temporal relationship between a transition point of the input signal SIN and an edge of a synchronization clock SCK, a delay selection circuit101for adding a delay to the input signal SIN based on the control signal CTL outputted from the state detection circuit102, and a latch circuit (flip-flop)103for synchronizing an output signal SD of the delay selection circuit101with the synchronization clock SCK.

The state detection circuit102sets the control signal CTL at “High” and outputs the control signal CTL, when the edge of the synchronization clock SCK exists in a period where a sufficient set-up hold time is not ensured for the input signal SIN, i.e., in the signal indefinite period Td shown in FIG.1. On the other hand, the state detection circuit102sets the control signal CTL at “Low” and does not output the control signal CTL when the edge of the synchronization clock SCK exists in the signal definite period Ts. As shown inFIG. 5, the state detection circuit102can be implemented as a circuit comprising a delay circuit104which adds a delay to the input signal SIN, an XOR circuit105which receives the input signal SIN and an output signal DSi of the delay circuit104and which outputs a signal Sxor, and a flip-flop106which receives the output signal Sxor of the XOR circuit105and the synchronization clock SCK and which outputs the control signal CTL.

The delay selection circuit101comprises a delay circuit111for adding a delay to the input signal SIN, and a selection circuit (2:1 selector)112for selecting either the input signal SIN or an output signal DSIN of the delay circuit111based on the control signal CTL outputted from the state detection circuit102. The selection circuit112selects the output signal DSIN of the delay circuit111when the control signal CTL is input thereto.

Hereinafter, the operation of the synchronization circuit of the first embodiment as constructed in the manner as described above will be described with reference toFIGS. 3 and 4.

The input signal SIN is input to the delay selection circuit101and the state detection circuit102, and the synchronization clock SCK is input to the state detection circuit102and the flip-flop103. While the transfer rate of the input signal SIN is equal to the frequency of the synchronization clock SCK, the phase of the input signal SIN is irrelevant to the phase of the synchronization clock SCK.

Initially, in the delay selection circuit101, the delay circuit111adds a delay to the input signal SIN, and outputs the delay-added signal DSIN to the selection circuit112.

On the other hand, the state detection circuit102performs a comparison of phases between the input clock CK and the input signal SIN.

As a result of the phase comparison that is performed by the state detection circuit102, when it is detected that an edge e11of the synchronization clock SCK exists in the signal definite period Ts of data d11of the input signal SIN as shown inFIG. 3, the control signal CTL remains at “Low” and is not output to the delay selection circuit101. Accordingly, in the selection circuit112in the delay selection circuit101, the input signal SIN is selected and outputted as a signal SD to the flip-flop103. In the flip-flop103, the data d11of the signal SD which is outputted from the delay selection circuit101is synchronized with the synchronization clock SCK to be output as a synchronizing signal SOUT.

Further, as a result of the phase comparison that is performed by the state detection circuit102, when it is detected that an edge e12of the synchronization clock SCK exists in the signal indefinite period Td of data d12of the input signal SIN as shown inFIG. 4, the control signal CTL is changed from “Low” to “High”, and the control signal CTL is to be output to the delay selection circuit101. Accordingly, in the selection circuit112in the delay selection circuit101, the output signal of the delay circuit111, i.e., the signal DSIN which is obtained by adding a delay time Tdel to the input signal SIN, is selected and outputted as a signal SD to the flip-flop103. In the flip-flop103, the data d12of the signal SD which is outputted from the delay selection circuit101is latched at an edge e13of the synchronization clock SCK so as to be output as a synchronizing signal SOUT.

While in the above description the operation of the selection circuit112is switched when the output from the state detection circuit102is “High”, the present invention is not restricted thereto.

The synchronization circuit according to the first embodiment is provided with the state detection circuit102for outputting the control signal CTL according to the temporal relationship between the transition point of the input signal SIN and the edge of the synchronization clock SCK, the delay selection circuit101for adding a delay to the input signal SIN based on the control signal CTL outputted from the state detection circuit102, and the latch circuit103for synchronizing the signal SD which is outputted from the delay selection circuit101with the synchronization clock SCK. Since it is not necessary to invert the input signal SIN as in the conventional circuit, the input signal SIN can be synchronized with the synchronization clock SCK without considering the temporal relationship between the signal indefinite period of the input signal SIN and the edge of the synchronization clock SCK. As a result, a synchronization circuit that can perform the above-described synchronization without adding latency to the input signal can be implemented with a relatively simple construction.

Second Embodiment

Hereinafter, a synchronization circuit according to a second embodiment of the present invention will be described with reference to FIG.6.

FIG. 6is a block diagram illustrating the construction of the synchronization circuit according to the second embodiment.

The synchronization circuit shown inFIG. 6is provided with a state detection circuit202for outputting a control signal CTL according to the temporal relationship between a transition point of an input signal SIN and an edge of an input clock CK, a delay selection circuit201for adding a delay to the input clock CK based on the control signal CTL outputted from the state detection circuit202, and a flip-flop203for synchronizing the input signal SIN with a clock SCK that is selected by the delay selection circuit201.

The state detection circuit202sets the control signal CTL at “High” and outputs the control signal CTL when the edge of the synchronization clock SCK exists within a period in which a sufficient set-up hold time is not ensured for the input signal SIN, i.e., the signal indefinite period Td shown in FIG.1. On the other hand, the state detection circuit202sets the control signal CTL at “Low” and does not output the control signal CTL when the edge of the synchronization clock SCK exists within the signal definite period Ts shown in FIG.1. The state detection circuit202can be implemented by the circuit shown in FIG.5.

The delay selection circuit201is provided with a delay circuit211for adding a delay to the input clock CK, and a selection circuit (2:1 selector)212for selecting either the input clock CK or an output clock DCK of the delay circuit211based on the control signal CTL outputted from the state detection circuit202. The selection circuit212selects the output clock DCK of the delay circuit211when the control signal CTL is input thereto.

The operation of the synchronization circuit of the second embodiment as constructed in the manner as described above will now be described with reference toFIGS. 7 and 8.

The input signal SIN is input to the state detection circuit202and the flip-flop203, and the input clock CK is input to the state detection circuit202and the delay selection circuit201. Although the transfer rate of the input signal SIN is equal to the frequency of the input clock SCK, the phase of the input signal SIN is irrelevant to the phase of the input clock SCK.

First of all, in the delay selection circuit201, the delay circuit211adds a delay to the input clock CK, and outputs the delay-added clock DCK to the selection circuit212.

On the other hand, the state detection circuit202performs a comparison of phases between the input clock CK and the input signal SIN.

As a result of the phase comparison that is performed by the state detection circuit202, when it is detected that an edge e21of the input clock exists in the signal definite period Ts of data d21of the input signal SIN as shown inFIG. 7, the control signal CTL remains at “Low” and is not output to the delay selection circuit201. Accordingly, in the selection circuit212in the delay selection circuit201, the input clock CK is selected and outputted as a synchronization clock SCK to the flip-flop203. In the flip-flop203, the data d21of the input signal SIN is synchronized with the synchronization clock SCK to be output as a synchronizing signal SOUT.

Further, as a result of the phase comparison that is performed by the state detection circuit202, when it is detected that an edge e22of the input clock exists in the signal indefinite period Td of data d22of the input signal SIN as shown inFIG. 8, the control signal CTL is changed from “Low” to “High”, and the control signal CTL is output to the delay selection circuit201. Accordingly, in the selection circuit212in the delay selection circuit201, the output signal of the delay circuit211, i.e., a clock DCK which is obtained by adding a delay time Tdel to the input clock CK, is selected and outputted as a synchronization clock CK to the flip-flop203. In the flip-flop203, the data d22of the input signal SIN is latched at an edge e23of the clock SCK which is outputted from the delay selection circuit201to be output as a synchronizing signal SOUT.

While, in the above descriptions the operation of the selection circuit212is switched when the output from the state detection circuit202is “High”, the present invention is not necessarily restricted thereto.

The synchronization circuit according to the second embodiment is provided with the state detection circuit202for outputting the control signal CTL according to the temporal relationship between the transition point of the input signal SIN and the edge of the clock CK, the delay selection circuit201for adding a delay to the clock CK based on the control signal CTL outputted from the state detection circuit202, and the latch circuit203for synchronizing the input signal SIN with the clock SCK which is outputted from the delay selection circuit201. Since it is not necessary to invert the input signal SIN as in the conventional circuit, the input signal SIN can be synchronized with the synchronization clock SCK without considering the temporal relationship between the signal indefinite period of the input signal SIN and the edge of the synchronization clock SCK. As a result, a synchronization circuit that can perform the above-mentioned synchronization without adding latency to the input signal can be implemented with a relatively simple construction.

Third Embodiment

Hereinafter, a synchronization circuit according to a third embodiment of the present invention will be described with reference to FIG.9.

FIG. 9is a block diagram illustrating the construction of the synchronization circuit according to the third embodiment.

The synchronization circuit shown inFIG. 9is provided with: a state detection circuit303for outputting a first control signal CTL1and a second control signal CTL2according to the temporal relationships between transition points of a first input signal SIN1and a second input signal SIN2, and an edge of a synchronization clock SCK, respectively; a first delay selection circuit301for adding a delay to the first input signal SIN1based the first control signal CTL1outputted from the stated detection circuit303; a second delay selection circuit302for adding a delay to the second input signal SIN2based on the second control signal CTL2outputted from the state detection circuit303; a first flip-flop304for synchronizing the output signal of the first delay selection circuit301with the synchronization clock SCK so as to output a first synchronizing signal SOUT; and a second flip-flop305for synchronizing the output signal of the second delay selection circuit302with the synchronization clock SCK so as to output a second synchronizing signal SOUT2.

The state detection circuit303outputs the control signal CTL when the edge of the synchronization clock SCK exists within a period in which a sufficient set-up hold time is not secured for the input signal, i.e., the signal indefinite period Td shown inFIG. 1, and the state detection circuit303does not output the control signal CTL when the edge of the synchronization clock SCK exists within the signal definite period Ts shown in FIG.1. The state detection circuit303can be implemented by the circuit shown in FIG.5.

Further, the first delay selection circuit301is provided with the first delay circuit311for adding a delay to the first input signal SIN1, and a first selection circuit (2:1 selector)312for selecting either the first input signal SIN1or the output signal DSIN of the first delay circuit311based on the first control signal CTL1outputted from the stated detection circuit303. The first selection circuit312selects the output signal SDIN of the first delay circuit311when the first control signal CTL1is input thereto.

Further, the second delay selection circuit302is provided with a second delay circuit321for adding a delay to the second input signal SIN2, and a second selection circuit (2:1 selector)322for selecting either the second input signal SIN2or the output signal DSIN2of the second delay circuit321based on the second control signal CTL2outputted from the state detection circuit303. The second selection circuit322selects the output signal DSIN2of the second delay circuit321when the second control signal CTL2is input thereto.

Hereinafter, the operation of the synchronization circuit of the third embodiment as constructed in the manner as described above will now be described.

The first input signal SIN1is input to the first delay selection circuit301and the state detection circuit303, the second input signal SIN2is input to the second delay selection circuit302and the state detection circuit303, and the synchronization clock SCK is input to the state detection circuit303, the flip-flop304, and the flip-flop305. While the transfer rates of the respective input signals SIN1and SIN2are equal to the frequency of the synchronization clock SCK, the phases of the first and second input signals SIN1and SIN2are irrelevant to the phase of the synchronization clock SCK.

Initially, in the first delay selection circuit301, the first delay circuit311adds a delay to the first input signal SIN1, and outputs the delay-added signal DSIN to the first selection circuit312. Further, in the second delay selection circuit302, the second delay circuit321adds a delay to the second input signal SIN2, and outputs the delay-added signal DSIN to the second selection circuit322.

On the other hand, the state detection circuit303performs a comparison of phases between the synchronization clock SCK and the first and second input signals SIN1and SIN2.

As a result of the phase comparison that is performed by the state detection circuit303, when it is detected that the edge of the synchronization clock SCK exists in the signal indefinite period Td of the first input signal SIN1, the first control signal CTL1is output to the first delay selection circuit301. Accordingly, in the first selection circuit312in the first delay selection circuit301, the output signal DSIN1of the first delay circuit311is selected and outputted to the first flip-flop304as a signal SD1.

On the other hand, when it is detected that the edge of the synchronization clock SCK exists in the signal definite period Ts of the first input signal SIN1, the first control signal CTL1is not output to the first delay selection circuit301and, therefore, the first input signal SIN1is selected by the first selection circuit312and outputted to the first flip-flop304as a signal SD1.

Further, when it is detected that the edge of the synchronization clock SCK exists in the signal indefinite period Td of the second input signal SIN2, the second control signal CTL2is output to the second delay selection circuit302. Accordingly, in the second selection circuit322in the second delay selection circuit302, the output signal DSIN2of the second delay circuit321is selected and outputted to the second flip-flop305as a signal SD2.

On the other hand, when it is detected that the edge of the synchronization clock SCK exists in the signal definite period Ts of the second input signal SIN2, the second control signal CTL2is not output to the second delay selection circuit302and, therefore, the second input signal SIN2is selected by the second selection circuit322and outputted to the second flip-flop305as a signal SD2.

In the first flip-flop304, the output signal SD1from the first delay selection circuit301is latched at the edge of the synchronization clock SCK to be output as a first synchronizing signal SOUT1. Further, in the second flip-flop305, the output signal SD2from the second delay selection circuit302is latched at the edge of the synchronization clock SCK to be output as a second synchronizing signal SOUT2.

While, in the above description, two input signals SIN1and SIN2are adopted, an arbitrary number of input signals (not less than two) may be adopted. At this time, the number of times of state detection in the state detection circuit303changes according to the number of input signals.

The synchronization circuit according to the third embodiment is provided with: the state detection circuit303for outputting the first and second control signals CTL1and CTL2relating to the respective input signals SIN1and SIN2according to the temporal relationship between the transition points of the first and second input signals SIN1and SIN2, and an edge of the synchronization clock SCK, respectively; the delay selection circuit302for adding delays to the respective input signals SIN1and SIN2based on the first and second control signals CTL1and CTL2, respectively; and the first and second latch circuits304and305for synchronizing the first and second signals SD1and SD2which are respectively outputted from the first and second delay selection circuits301and circuit302with the synchronization clock SCK. Since it is not necessary to invert each input signal as in the conventional circuit, the first input signal SIN1and the second input signal SIN2can be synchronized with each other by using the synchronization clock SCK without considering the temporal relationship between the signal indefinite period of each input signal and the edge of the synchronization clock SCK. As a result, a synchronization circuit that can perform the above-described synchronization without adding latency to the input signals can be implemented with a relatively simple construction.

Fourth Embodiment

Hereinafter, a synchronization circuit according to a fourth embodiment of the present invention will be described with reference to FIG.10.

The synchronization circuit according to the fourth embodiment receives plural signal bundles each comprising a set of plural input signals which are synchronized with each other and a single clock having a frequency which is equal to a transfer rate of the plural input signals, in which the phases of the input signals that are included in one signal bundle are irrelevant to the phases of the input signals that are included in the other signal bundles, and the synchronization circuit synchronizes the input signals that are included in one signal bundle with the input signals that are included in the other signal bundles by using a single synchronization clock that is selected from among the clocks which are included in the respective signal bundles.

FIG. 10is a block diagram illustrating the construction of the synchronization circuit according to the fourth embodiment of the present invention. While plural signal bundles should be input to the synchronization circuit,FIG. 10shows two signal bundles each comprising a set of a single input signal and a single clock for the sake of convenience. To be specific, inFIG. 10, SIN-1denotes one of the signals that is included in the first signal bundle, SIN-2denotes one of the signals that is included in the second signal bundle, CK1is a clock that is included in the first signal bundle, and CK2is a clock that is included in the second signal bundle.

The synchronization circuit shown inFIG. 10is provided with: a state detection circuit401for detecting the state between the first input signal SIN-1and the second input signal SIN-2which are included in the respective signal bundles; a clock selection circuit402for selecting either the first input clock CK1or the second input clock CK2based on a result of the state detection that is performed between the respective signal bundles by the state detection circuit401, and outputting the selected clock as a synchronization clock SCK; a delay selection circuit403for adding a first delay to the first input signal SIN-1based on the result of the state detection that is performed between the respective signal bundles, and outputting the delayed signal as a first signal SD11; a second delay selection circuit404for adding a delay to the second input signal SIN-2based on the result of the state detection that is performed between the respective signal bundles, and outputting the delayed signal as a second signal SD21; a first flip-flop405for synchronizing the first signal SD11with the synchronization clock SCK; and a second flip-flop406for synchronizing the second signal SD21with the synchronization clock SCK.

As shown inFIG. 12, the state detection circuit401is provided with an early/late detection circuit407for detecting as to which signal bundle is earlier in input timing between the respective signal bundles (SIN-1and SIN-2), and an overlap detection circuit408for detecting an overlap period between the respective signal bundles (SIN-1and SIN-2).

As shown inFIG. 13, the early/late detection circuit407is provided with a first flip-flop444for receiving the first input signal SIN-1, and a second flip-flop445for receiving the second input signal SIN-2. One of the first and second flip-flops444and445which receives the input signal earlier than the other flip-flop outputs a signal Ki1or Ki2to the other flip-flop444or445indicating that inputting should be stopped. When the first input signal SIN-1is inputted earlier than the second input signal SIN-2, the first flip-flop444outputs an early/late detection signal Fa1. When the second input signal SIN-2is inputted earlier than the first input signal SIN-1, the second flip-flop445outputs an early/late detection signal Fa2.

As shown inFIG. 14, the overlap detection circuit408is provided with: a first delay circuit421for adding a delay to the first input signal SIN-1, a second delay circuit422for adding a delay to the second input signal SIN-2, a first AND circuit426for receiving the first input signal SIN-1and the output signal of the second delay circuit422, a second AND circuit427for receiving the second input signal SIN-2and the output signal of the first delay circuit421, a third AND circuit428for receiving the output signal of the first AND circuit426and the output signal of the second AND circuit427, an XOR circuit429for receiving the output signal of a first flip-flop423and the output signal of a second flip-flop424, the first flip-flop423for receiving the output signal of the first AND circuit426, the second flip-flop424for receiving the output signal of the second AND circuit427, and a third flip-flop425for receiving the output signal of the third AND circuit428.

As shown inFIG. 15, the first delay selection circuit403is provided with: a first flip-flop431for receiving the first input signal SIN-1and the first clock signal CK1, and outputting a signal AD; a second flip-flop432for receiving the output signal AD of the first flip-flop431and the first clock signal CK1, and outputting a signal BD; a first selection circuit433for selecting the output signal BD of the second flip-flop432when either the early/late detection signal Fa1or the overlap detection circuit Ov1is input, while selecting the output signal AD of the first flip-flop431when no signal is inputted; a delay circuit435for adding a delay time Tdelay to the output signal SIN-S1of the selection circuit433, and outputting a delay-added signal SIN-D1; and a second selection circuit434for selecting the output signal SIN-S1of the first selection circuit433when the overlap detection signal So1is not inputted, while selecting the output signal SIN-D1of the delay circuit435when the overlap detection signal So1is inputted. The first selection circuit433and the second selection circuit434are 2:1 selectors.

The operation of the synchronization circuit of the fourth embodiment as constructed in the manner as described above will now be described.

The first input signal SIN-1is input to the first delay selection circuit403and the state detection circuit401, the second input signal SIN-2is input to the second delay selection circuit404and the state detection circuit401, the first input clock CK1is input to the first delay selection circuit403and the clock selection circuit402, and the second input clock CK2is input to the second delay selection circuit404and the clock selection circuit402. While the first input signal SIN-1and the first input clock CK1(the second input signal SIN-2and the second input clock) are inputted in synchronization with each other as shown inFIG. 11, the first input signal SIN-1and the second input signal SIN-2are asynchronous to each other. Further, data d41and data d42are signals to be synchronized.

Initially, in the state detection circuit401, the early/late detection circuit407detects as to which signal is earlier in input timing between the first input signal SIN-1and the second input signal SIN-2, and outputs a first detection signal Fa1to the clock selection circuit402when the first input signal SIN-1is earlier, or outputs a second detection signal Fa2to the clock selection circuit402when the second input signal SIN-2is earlier. When the first detection signal Fa1is input to the clock selection circuit402, the clock selection circuit402outputs the first input clock CK1as a synchronization clock SCK to the first flip-flop405and the second flip-flop406. On the other hand, when the second detection signal Fa2is input to the clock selection circuit402, the clock selection circuit402outputs the second input clock CK2as a synchronization clock SCK to the first flip-flop405and the second flip-flop406.

On the other hand, in the state detection circuit401, the overlap detection circuit408detects an overlap period between the first input signal SIN-1and the second input signal SIN-2. When the overlap period is longer than a delay time Tso, the overlap detection circuit408outputs a first detection signal Ov1and a second detection signal Ov2to the first delay selection circuit403and the second delay selection circuit404, respectively. When the overlap period is shorter than the delay time Tso, the overlap detection circuit408outputs a first detection signal So1and a second detection signal So2to the first delay selection circuit403and the second delay selection circuit404, respectively.

In the first delay selection circuit403, when either the first detection signal Ov1or the first detection signal Fa1from the state detection circuit401is input to the first selection circuit433, the output signal BD from the second flip-flop432is selected. Otherwise, the output signal AD from the first flip-flop431is selected. Further, when the overlap detection signal So1is input to the second selection circuit434, the output signal SIN-D1of the delay circuit435is selected and outputted as a first signal SD11to the first flip-flop406. Otherwise, the output signal SIN-S1of the first selection circuit433is outputted as a first signal SD11. Then, in the first flip-flop405, the first output signal SD11of the first delay selection circuit403is synchronized with the synchronization clock SCK which is outputted from the clock selection circuit402so to be output as a first synchronizing signal SOUT11.

Further, the second delay selection circuit404is controlled by the output signals Ov2, So2, and Fa2of the state detection circuit401in a similar like manner as described above for the first delay selection circuit403, and a second signal SD21is output to the second flip-flop406. Then, in the second flip-flop406, the second output signal SD21of the second delay selection circuit404is synchronized with the synchronization clock SCK which is outputted from the clock selection circuit402so as to be output as a second synchronizing signal SOUT21.

In this way, the first signal bundle SIN-1and the second signal bundle SIN-2, which have been inputted asynchronously to each other, are synchronized. Since these signals are synchronized even when the data d43and d44to be synchronized have no overlap period as shown inFIG. 16, displacements of pictures or the like can be avoided.

While two input signals are adopted in the fourth embodiment, an arbitrary number of input signals not less than two may be adopted. Further, as for clocks to be input in synchronization with the respective input signals, an arbitrary number of clocks not less than two may be adopted. Thus, the number of input signals and the number of clocks may be arbitrarily selected as long as the above-mentioned functions are satisfied, and the present invention is not restricted to the above-described construction.

The synchronization circuit according to the fourth embodiment is provided with the state detection circuit401for receiving two signal bundles each comprising a set of plural synchronous input signals and a single clock having a frequency which is equivalent to a transfer rate of the plural input signals, in which the input signals that are included in one signal bundle is irrelevant to the input signals that are included in the other signal bundles, and for detecting the state between the input signals included in the respective signal bundles. The synchronization circuit according to the fourth embodiment is also provided with: the clock selection circuit402for receiving the clock CK1and the clock CK2which are included in the respective signal bundles, and selecting one of the input clocks CK1and CK2as a synchronization clock SCK based on the result of the state detection that performed by the state detection circuit401; the first and second delay selection circuits403and404for respectively adding delays to the plural input signals SIN-1and SIN-2which are included in the respective signal bundles based on the result of the state detection that is performed between the respective signal bundles; and the first and second latch circuits405and406for synchronizing the first and second output signals SD11and DS21from the first and second delay selection circuits403and404with the synchronization clock SCK, respectively. Since it is not necessary to invert the input signal SIN-1and the input signal SIN2as in the conventional circuit, the input signals SIN-1and SIN-2can be synchronized with each other by using the synchronization clock SCK without considering the temporal relationship between the signal indefinite period of each input signal and the edge of the synchronization clock. As a result, a synchronization circuit that can perform the above-mentioned synchronization of the respective input signals SIN-1and SIN-2without adding latency to the input signals, even when there is no overlap period of data to be synchronized, can be implemented with a relatively simple construction.

In the respective embodiments of the present invention, a preamble signal indicating the positional relationship between the data to be synchronized may be input to the state detection circuit so as to detect a preamble pattern of the input signal, and as a result, whereby the positional relationship between the data to be synchronized can easily be detected.

The synchronization circuit according to the present invention is useful as a circuit which is capable of increasing the data transmission efficiency in a data transmission system such as a digital transmission apparatus.