Embodiments related to transistors and integrated circuits having aluminum indium phosphide subfins and germanium channels, systems incorporating such transistors, and methods for forming them are discussed.

CLAIM OF PRIORITY

This Application is a National Stage Entry of, and claims priority to, PCT Application No. PCT/US2015/049634, filed on 11 Sep. 2015 and titled “ALUMINUM INDIUM PHOSPHIDE SUBFIN GERMANIUM CHANNEL TRANSISTORS”, which is incorporated by reference in its entirety for all purposes.

TECHNICAL FIELD

Embodiments of the invention generally relate to semiconductor transistors with enhanced channel mobility and reduced leakage, and more particularly relate to germanium channel transistors with aluminum indium phosphide subfins and related devices and manufacturing techniques.

BACKGROUND

In some implementations, transistors, such as metal-oxide-semiconductor field-effect transistors (MOSFETs) may by multi-gate devices (e.g., tri-gate transistors, FinFETs or the like). Such structures may offer the advantages of more current flow when the device is on and less current flow when the device is off as compared to similar planar transistor structures, and may thereby provide greater performance and less power usage. For example, multi-gate devices may include a fin or the like such as a silicon fin that is coupled to a source, a drain, and a gate between the source and the drain. The fin may include a channel region adjacent to the gate.

Furthermore, as device improvements are sought, different materials may be implemented for the various components of the multi-gate devices. In particular, the fin or pillar may be made up of materials other than silicon in order to improve device performance. Such materials may provide increased electron and/or hole mobilities or the like to increase drive current, for example. As new materials are provided within the fin structure, the optimization of channel mobility and subfin leakage may be a continuing problem.

As such, existing techniques do not provide for transistor structures with enhanced channel mobility and minimal or reduced leakage such as subfin leakage. Such problems may become critical as devices having increased speed, enhanced drive current, and low power consumption are needed in various applications.

DETAILED DESCRIPTION

Reference is made in the following detailed description to the accompanying drawings, which form a part hereof, wherein like numerals may designate like parts throughout to indicate corresponding or analogous elements. It will be appreciated that for simplicity and/or clarity of illustration, elements illustrated in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Further, it is to be understood that other embodiments may be utilized and structural and/or logical changes may be made without departing from the scope of claimed subject matter. It should also be noted that directions and references, for example, up, down, top, bottom, over, under, and so on, may be used to facilitate the discussion of the drawings and embodiments and are not intended to restrict the application of claimed subject matter. Therefore, the following detailed description is not to be taken in a limiting sense and the scope of claimed subject matter defined by the appended claims and their equivalents.

Transistors, integrated circuits, devices, apparatuses, computing platforms, and methods are described below related to transistors having enhanced channel mobility and reduced leakage.

As described above, it may be advantageous to provide transistors having enhanced channel mobility and minimal or reduced leakage. Such transistors may provide increased drive current and power savings. In an embodiment, a transistor may include a germanium fin channel and a subfin having an aluminum indium phosphide layer adjacent to the germanium fin channel and a second layer adjacent to the aluminum indium phosphide layer. The germanium fin channel may provide a high channel mobility material for the transistor. Furthermore, the aluminum indium phosphide layer of the subfin layer may provide reduced leakage (e.g., subfin leakage) by providing a conduction band offset and/or a valence band offset with respect to the germanium fin channel. Such offsets may provide an energy state barrier for containment of leakage such as subfin (e.g., via the bottom of the fin channel) leakage. For example, the valence band offset (VBO) may provide containment for a PMOS (P-type metal-oxide semiconductor) transistor and the conduction band offset (CBO) may provide containment for an NMOS (N-type metal-oxide semiconductor) transistor.

In an embodiment, the transistor may be an NMOS transistor and the aluminum indium phosphide layer of the subfin may provide a tensile strain to the fin channel. In another embodiment, the transistor may be a PMOS transistor and the aluminum indium phosphide layer of the subfin may provide a compressive strain to the fin channel. For example, a higher aluminum concentration in the aluminum indium phosphide layer may provide a smaller lattice constant in the aluminum indium phosphide layer, which may provide an advantageous compressive strain for a PMOS transistor and a lower aluminum concentration may provide a larger lattice constant and an advantageous tensile strain for an NMOS transistor.

In an embodiment, a CMOS (complimentary metal-oxide semiconductor) circuit may include a PMOS transistor with a fin channel under a compressive strain and an NMOS transistor with a fin channel under a tensile strain by selectively providing aluminum indium phosphide subfin layers of differing aluminum concentrations. In some embodiments, a CMOS circuit may include an NMOS transistor having a germanium fin channel and a subfin having an aluminum indium phosphide layer adjacent to the germanium fin channel and a PMOS transistor having different fin channel and/or subfin materials. For example, the PMOS transistor fin channel may be germanium, silicon, or a III-V material and the subfin layer adjacent to the fin channel may be any suitable material. In other embodiments, a CMOS circuit may include a PMOS transistor having a germanium fin channel and a subfin having an aluminum indium phosphide layer adjacent to the germanium fin channel and an NMOS transistor having different fin channel and/or subfin materials. For example, the NMOS transistor fin channel may be germanium, silicon, or a III-V material and the subfin layer adjacent to the fin channel may be any suitable material. In an embodiment, the NMOS transistor fin channel may be indium gallium arsenide and the subfin layer adjacent to the fin channel may be gallium arsenide.

In an embodiment, an integrated circuit may comprise a transistor including a fin channel that comprises germanium and a subfin with an aluminum indium phosphide layer adjacent to the fin channel and a second layer adjacent to the aluminum indium phosphide layer. Such a transistor may provide high performance and low power with high channel mobility and minimal or reduced subfin leakage. These and additional embodiments are discussed further herein with respect to the figures.

FIG. 1Ais a side view of an example integrated circuit100including example transistors120,130andFIG. 1Bis a plan view of example transistors120,130, arranged in accordance with at least some implementations of the present disclosure.FIG. 1Aprovides a side view taken along plane A as shown in the plan view ofFIG. 1B. In some examples, transistor120may be an NMOS transistor and transistor130may be a PMOS transistor. Transistors120,130may be characterized as tri-gate transistors, multi-gate transistors, FinFETs, or the like. Transistors120,130may provide for a fin architecture for CMOS circuits that provide high channel mobility and low subfin leakage.

As shown, integrated circuit100may include a substrate101and a dielectric layer102. In an embodiment, substrate101is silicon (e.g., (100) crystalline silicon). Dielectric layer102may include a pattern providing openings or trenches for fins as shown. In an embodiment, dielectric layer102is an oxide (e.g., silicon oxide). For example, transistor120may include a fin having a fin channel121and a subfin122including a base layer103and a subfin layer104. Transistor130may include a fin having a fin channel131and a subfin132including a base layer105and a subfin layer106. As used herein, the term fin may include both a fin channel and a subfin. In some embodiments, the subfin may include multiple layers such as a layer adjacent to the fin channel (e.g., a subfin layer) and a second layer adjacent to the subfin layer (e.g., a base layer). In other embodiments, the subfin may include only a subfin layer. Furthermore, as used herein, the term fin channel may include a portion of the fin that at least partially extends above a dielectric layer or the like. Such a fin channel may include a portion that provides a channel in operation and other portions such as portions that provide contact to a source and a drain. As will be appreciated, only a portion of such a fin channel provides a channel in operation and such a channel may be described as a channel region either when the transistor is in operation or not. In some embodiments, such a region of a fin may be characterized as a fin portion, an active fin portion, an exposed fin portion, or the like.

In an embodiment, base layer103and/or base layer105include or are composed of gallium arsenide such as an epitaxially grown, crystalline, or substantially singular crystalline gallium arsenide. In an embodiment, subfin layer104and/or subfin layer106include or are composed of an epitaxially grown, crystalline, or substantially singular crystalline aluminum indium phosphide layer. Subfin layers104,106may include any composition of aluminum indium phosphide such as aluminum concentrations in the range of 1% to 99%, indium concentrations in the range of about 1% to 99%, or the like. In an embodiment, fin channel121and/or fin channel131include or are composed of an epitaxially grown, crystalline, or substantially singular crystalline germanium layer. As is discussed further herein, base layers103,105, subfin layers104,106, and fin channels121,131may be epitaxially grown within a trench (e.g., a narrow or high aspect ratio trench).

Also as shown inFIG. 1B, transistor120may include a gate107and transistor130may include a gate108. Gates107,108may provide a charge (e.g., via a gate contact, not shown) to portions of fin channels121,131to induce a channel within fin channels121,131during the operation of transistors120,130. For example, gates107,108may be disposed over portions of fin channels121,131. Gates107,108are not shown inFIG. 1Aand are shown in hatched lines inFIG. 1Bfor the sake of clarity of presentation.

As shown inFIG. 1Btransistor120may include a source109and a drain110coupled to fin channel121and transistor130may include a source111and a drain112coupled to fin channel131. Sources109,111and drains110,112may provide electrical contact to transistors120,130and may include any suitable material or materials. In some embodiments, sources109,111and drains110,112may be formed via a raised source and drain epitaxial growth or regrowth process or via material deposition and patterning processes or the like. Sources109,111and drains110,112are not shown inFIG. 1Aand are shown in hatched lines inFIG. 1Bfor the sake of clarity of presentation.

As discussed, fin channels121,131may include or be composed of germanium such as an epitaxial germanium. In an embodiment, fin channels121,131may provide enhanced or increased electron and hole mobility for fin channels121,131as compared to other channel materials. For example, germanium may provide a low effective mass for both NMOS and PMOS transistors allowing for high mobility and drive currents.

Also as discussed, subfin layers104,106may include or be composed of aluminum indium phosphide such as an epitaxial aluminum indium phosphide. In an embodiment, subfin layers104,106may include or be composed of aluminum indium phosphide having the same compositions. Aluminum indium phosphide subfin layers104,106may provide large band offsets with respect to germanium fin channels121,131, which may reduce or eliminate subfin leakage during the operation of transistors120,130.

FIG. 2is an example band diagram200of an example hetero junction203between germanium and aluminum indium phosphide, arranged in accordance with at least some implementations of the present disclosure. As shown inFIG. 2, band diagram200may include a germanium band gap250having a conduction band edge251indicative of a conduction band and a valence band edge252indicative of a valence band. For example, germanium band gap250may include a narrow band gap associated with a germanium region201. Also as shown, band diagram200may include an aluminum indium phosphide band gap260having a conduction band edge261indicative of a conduction band and a valence band edge262indicative of a valence band. For example, aluminum indium phosphide band gap260may include a wide band gap associated with aluminum indium phosphide region202. As shown, germanium region201and aluminum indium phosphide region202may meet at hetero junction203.

As shown, germanium201may provide a narrow band gap material having a gap width (Eg) of about 0.67 eV and aluminum indium phosphide may provide a wide band gap material having a gap width (Eg) of about 2.34 eV. Such a band gap structure across the physical dimension of transistors120,130extending from fin channels121,131downwardly to subfin layers104,106(please refer toFIG. 1A) may provide a high conduction band offset (CBO) and a high valence band offset (VBO) across hetero junction203. For example, the CBO may be about 0.51 and the VBO may be about 1.16 as shown inFIG. 2. The provided gap widths, CBO, and VBO are example values and transistors120,130may include any suitable materials as discussed herein.

In the germanium and aluminum indium phosphide system illustrated inFIG. 2, the illustrated conduction band offset may provide minimal, reduced, or negligible transportation for electrons in NMOS transistors. Furthermore, the illustrated valence band offset may provide minimal, reduced, or negligible transportation for holes in PMOS transistors. Therefore, for both NMOS and PMOS transistors, a germanium and aluminum indium phosphide system may provide for high channel mobility (e.g., via germanium fin channels) and minimal, reduced, or negligible subfin leakage (e.g., via the germanium fin channel and aluminum indium phosphide hetero-junction).

Furthermore, the illustrated germanium and aluminum indium phosphide system may provide improved dopant barrier properties at hetero junction203(e.g., between fin channels121,131and subfin layers104,106, please refer toFIG. 1A). For example, aluminum content in aluminum indium phosphide region202(e.g., in aluminum indium phosphide subfin layers104,106) may improve dopant barrier properties by suppressing or reducing intermixing of the germanium of germanium region201(e.g., germanium fin channels121,131) and aluminum indium phosphide, which, for example, may be dopant species for the opposite layers.

Returning toFIGS. 1A and 1B, in some embodiments, transistor120may be an NMOS transistor and transistor130may be a PMOS transistor. In some implementations, for example, it may be more difficult to achieve low subfin leakage with respect to an NMOS transistor in germanium and aluminum indium phosphide systems and other material systems such as germanium fin channel systems. In some embodiments, NMOS transistor120may include a germanium fin channel121and an aluminum indium phosphide subfin layer104while PMOS transistor130may include a subfin layer106and fin channel131including other materials. In other embodiments, PMOS transistor130may include a germanium fin channel131and an aluminum indium phosphide subfin layer106while NMOS transistor120may include a subfin layer104and fin channel121including other materials. In an embodiment, NMOS transistor120may include a gallium arsenide subfin layer104and an indium gallium arsenide fin channel121.

Furthermore, it may be advantageous to provide stress engineering to fin channels121,131such that fin channel121of NMOS transistor120is under tensile strain while PMOS transistor130is under compressive strain as shown via arrows141,142inFIG. 1B. In some embodiments, NMOS transistor120may include an aluminum indium phosphide subfin layer104having a composition that may provide a tensile strain to germanium fin channel121. In some embodiments, PMOS transistor130may include subfin layer104(e.g., comprising aluminum indium phosphide or another material) having a composition that may provide a compressive strain to germanium fin channel121.

In an embodiment, NMOS transistor120may include a germanium fin channel121and an aluminum indium phosphide subfin layer104. For example, germanium fin channel121may be a doped germanium having a lattice constant in the range of about 5.6 to 5.7 Å. The composition of aluminum indium phosphide subfin layer104may be selected such that subfin layer104has a larger lattice constant with respect to the lattice constant of germanium fin channel121and such that a tensile strain may be exerted on germanium fin channel121. For example, a larger lattice constant aluminum indium phosphide subfin layer104may be provided by increasing the concentration of indium and reducing the concentration of aluminum in aluminum indium phosphide subfin layer104. In some embodiments, the aluminum concentration in an aluminum indium phosphide subfin layer104may be in the range of about 35% to 50% such that a tensile strain may be exerted on germanium fin channel121. As discussed, subfin layer104may provide a tensile strain on fin channel121of NMOS transistor120. In some embodiments, the tensile strain may be up to about 1%, although any tensile strain may be provided. In some embodiments, no tensile strain may be provided.

In an embodiment, PMOS transistor130may include a germanium fin channel131and an aluminum indium phosphide subfin layer106. For example, germanium fin channel131may be a doped germanium having a lattice constant in the range of about 5.6 to 5.7 Å as discussed with respect to fin channel121. The composition of aluminum indium phosphide subfin layer106may be selected such that subfin layer106has a smaller lattice constant with respect to the lattice constant of germanium fin channel121and such that a compressive strain may be exerted on germanium fin channel131. For example, a smaller lattice constant aluminum indium phosphide subfin layer106may be provided by decreasing the concentration of indium and increasing the concentration of aluminum in aluminum indium phosphide subfin layer106. In some examples, the aluminum concentration in an aluminum indium phosphide subfin layer104may be in the range of about 100% to 50% such that a compressive strain may be exerted on germanium fin channel131. As discussed, subfin layer106may provide a compressive strain on fin channel131of PMOS transistor130. In some embodiments, the compressive strain may be in the range of about 1% to 2% although any compressive strain may be provided. In some embodiments, no compressive strain may be provided.

As discussed, in some embodiments, fin channel121of NMOS transistor120may be under tensile strain and fin channel131of PMOS transistor130may be under compressive strain based on the compositions of subfin layers104,106. In an embodiment, the aluminum to indium ratio of an aluminum indium phosphide subfin layer104may be less than the aluminum to indium ratio of an aluminum indium phosphide subfin layer106such that the discussed stress engineering may be attained.

In some embodiments, NMOS transistor120may include a gallium arsenide base layer103, an aluminum indium phosphide subfin layer104, and a germanium fin channel121. Furthermore, in some embodiments, PMOS transistor130may include a gallium arsenide base layer103, an aluminum indium phosphide subfin layer104, and a germanium fin channel121. In some embodiments, the composition of subfin layers104,106may be different and selected to provide stress engineering and/or fin channels121,131may be doped or the like to provide advantageous properties for transistors120,130. In some embodiments, NMOS transistor120or PMOS transistor130may include different material systems or selections. For example, NMOS transistor120or PMOS transistor130may include base layers having materials other than gallium arsenide, subfin layers having materials other than aluminum indium phosphide, or fin channels having materials other than germanium. In some embodiments, NMOS transistor120may include a gallium arsenide, aluminum indium phosphide, germanium system and PMOS transistor130may include a different material system such as a base layer including gallium arsenide, a subfin layer having any material that may decrease sub-fin leakage, and a fin channel including germanium, silicon, a III-V material, or the like. In some embodiments, PMOS transistor130may include a gallium arsenide, aluminum indium phosphide, germanium system and NMOS transistor120may include a different material system such as a base layer including gallium arsenide, a subfin layer having any material that may decrease sub-fin leakage, and a fin channel including germanium, silicon, a III-V material, or the like. In an embodiment, NMOS transistor120may include a base layer including gallium arsenide, a subfin layer including gallium arsenide, and a fin channel including indium gallium arsenide.

In an embodiment, subfin layers104,106may comprise the same compositions. As discussed with respect toFIG. 2, such a material system may provide high barrier offsets for both NMOS and PMOS devices. Furthermore, such a material system may provide for simpler manufacturing process flows. However, such a material system may not allow for independent stress engineering of NMOS and PMOS devices.

As shown inFIG. 1A, in some examples, fin channels121,131may extend above dielectric layer102by a portion123and a portion133, respectively. For example, dielectric layer102may be adjacent to base layers103,105and adjacent to a portion of subfin layer104and a portion of subfin layer106. Furthermore, base layers103,105and dielectric layer102may be on substrate101as shown. Subfin layers104,106may have portions123,133that extend beyond a top surface140of dielectric layer102such that bottom surfaces of fin channels121,131are above dielectric layer102. Such an arrangement may provide for enhanced control of fin channels121,131via gates107,108. For example, if the bottoms of fin channels121,131were below top surface140of dielectric layer102, gates107,108may disadvantageously lose contact area with fin channels121,131, which may cause loss of gate control or the like.

Furthermore, sources109,111and drains110,112may include any suitable materials. In some examples, sources109,111and drains110,112may include an epitaxial growth material. In some examples, source109and drain110and/or source111and drain112may include or be composed of a different material than fin channels121,131. In some examples, source109and drain110may include or be composed of the same material or materials as source111and drain112. In other examples, source109and drain110may include or be composed of different materials as source111and drain112. In some embodiments, sources109,111and drains110,112may include material(s) selected to provide strain engineering to fin channels121,131for improved performance. Furthermore, source111and drain112may be heavily doped with a p-type dopant and source109and drain110may be heavily doped with an n-type dopant.

As discussed, gates107,108may be disposed over fin channels121,131. Gates107,108may include any suitable material, materials or stack of materials for providing electrical control over channel regions of fin channels121,131. In an embodiment, gates107,108include an epitaxial layer of silicon or other suitable material adjacent to channel regions of fin channels121,131, a high-k gate dielectric over the epitaxial layer of silicon and a metal gate portion over the high-k gate dielectric. In an embodiment, gates107,108include a high-k gate dielectric adjacent to channel regions of fin channels121,131and a metal gate portion over the high-k gate dielectric.

Additional details associated with the described features of integrated circuit100and/or transistors120,130are provided herein with respect toFIGS. 4A-4Gand the associated discussion, which provides additional details related to the formation of integrated circuit100and transistors120,130. Furthermore, integrated circuit100may be implemented in an electronic device structure such as a logic device, an SRAM, or the like, as is discussed further herein.

FIG. 3is a flow diagram illustrating an example process300for forming transistors having enhanced channel mobility and reduced leakage, arranged in accordance with at least some implementations of the present disclosure. For example, process300may be implemented to fabricate transistor120and/or transistor130as discussed herein. In the illustrated implementation, process300may include one or more operations as illustrated by operations301-304. However, embodiments herein may include additional operations, certain operations being omitted, or operations being performed out of the order provided.

Process300may begin at operation301, “Form a Subfin having a Base Layer and an Aluminum Indium Phosphide Layer over a Substrate”, where a subfin having a base layer and an aluminum indium phosphide layer over the base layer may be formed over or on a substrate. For example, the base layer may be a first layer and the aluminum indium phosphide layer may be a second layer or subfin layer as discussed herein. In an embodiment, subfin122and/or subfin132may be formed over substrate101as discussed further herein with respect toFIGS. 4A-4Fand elsewhere herein. In an embodiment, subfins122,132may include the same or substantially the same materials and subfins122,132may be formed together. In another embodiment, subfins122,132may include different materials (e.g., different concentrations of aluminum in their aluminum indium phosphide layer) and subfins122,132may be formed separately as is discussed further herein. In an embodiment, the subfins may be formed in a trench via epitaxial growth techniques.

Process300may continue at operation302, “Dispose a Germanium Fin Channel over the Aluminum Indium Phosphide Layer”, where a fin channel comprising germanium may be disposed over the aluminum indium phosphide layer of the subfin. In an embodiment, fin channel121and/or fin channel131may be disposed over subfin122and/or subfin132, respectively, as discussed further herein with respect toFIGS. 4E-4Gand elsewhere herein. In an embodiment, fin channel121and/or fin channel131may be deposited over subfin122and/or subfin132. In an embodiment, fin channels121,131, may include the same or substantially the same materials and fin channels121,131may be formed together. In another embodiment, fin channels121,131may include different materials and fin channels121,131may be formed separately as is discussed further herein. In an embodiment, the fin channels may be formed in a trench via epitaxial growth techniques.

Process300may continue at operation303, “Dispose a Gate over the Fin Channel”, where a gate may be disposed over the fin channel. In an embodiment, gate107and/or gate108may be formed over a channel region of fin channel121and/or a channel region of fin channel131, respectively. For example, gate107and/or gate108may include an epitaxial layer of silicon or other suitable material adjacent to channel regions of fin channels121,131a high-k gate dielectric over the epitaxial layer of silicon and a metal gate portion over the high-k gate dielectric. For example, the gates may be formed via epitaxial growth techniques and/or blanket deposition techniques and patterning techniques or the like.

Process300may continue at operation304, “Couple a Source and a Drain to the Fin”, where a source and a drain may be coupled to the fin channel. In an embodiment, source109and drain110may be coupled to fin channel121and/or source111and drain112may be coupled to fin channel131. As discussed, fin channels121,131may include channel regions that provide channels in operation. Furthermore, fin channels121,131may include source/drain contact regions for contacting a source and drain. For example, the sources and drains may be formed via masking and epitaxial growth techniques or via blanket deposition and patterning techniques or the like.

As discussed, process300may be implemented to fabricate transistor120and/or transistor130. Further details associated with such fabrication techniques are discussed herein an in particular, with respect toFIGS. 4A-4G. Any one or more of the operations of process300(or the operations discussed herein with respect toFIGS. 4A-4G) may be undertaken in response to instructions provided by one or more computer program products. Such program products may include signal bearing media providing instructions that, when executed by, for example, a processor, may provide the functionality described herein. The computer program products may be provided in any form of computer readable medium. Thus, for example, a processor including one or more processor core(s) may undertake one or more of the described operations in response to instructions conveyed to the processor by a computer readable medium.

FIGS. 4A-4Gare side views of example transistor structures as particular fabrication operations are performed, arranged in accordance with at least some implementations of the present disclosure.FIG. 4Aillustrates a side view of transistor structure401taken along plane A as shown in the plan view ofFIG. 1B. As shown inFIG. 4A, transistor structure401includes substrate101, sacrificial fins403,404, and dielectric layer402. For example, substrate101may be a substrate substantially aligned along a predetermined crystal orientation (e.g., (100), (111), (110), or the like). In some examples, substrate101may include a semiconductor material such as monocrystalline silicon (Si), germanium (Ge), silicon germanium (SiGe), a III-V materials based material (e.g., gallium arsenide (GaAs)), a silicon carbide (SiC), a sapphire (Al2O3), or any combination thereof. In an embodiment, substrate101may include silicon having a (100) crystal orientation. In various examples, substrate101may include metallization interconnect layers for integrated circuits or electronic devices such as transistors, memories, capacitors, resistors, optoelectronic devices, switches, or any other active or passive electronic devices separated by an electrically insulating layer, for example, an interlayer dielectric, a trench insulation layer, or the like.

Also as shown inFIG. 4A, sacrificial fins403,404and a dielectric layer402may be formed over substrate101such that sacrificial fins403,404are adjacent to dielectric layer402. For example, sacrificial fins403,404may be formed via a patterning and etch of substrate101as illustrated (e.g., sacrificial fins403,404may comprise crystalline silicon) or via a material deposition and patterning of the material (e.g., polysilicon or the like). The size and shape of sacrificial fins403,404may define subsequent openings that may, in turn, define the size and shape of subfins122,132and fin channels121,131, which may be formed in trenches formed when sacrificial fins403,404are removed. In an embodiment, sacrificial fins403,404may have substantially vertical sidewalls as shown. In an embodiment, sacrificial fins403,404may have angled sidewalls such that the bottoms of sacrificial fins403,404may be wider than the tops of sacrificial fins403,404. In another embodiment, the sidewalls of sacrificial fins403,404may each have a curved shape such that the bottoms of sacrificial fins403,404may wider than the tops of sacrificial fins403,404and such that the sidewalls have a concave curved shape. Additional details associated with sacrificial fins403,404are discussed further herein with respect to the trenches they form.

Dielectric layer402may include any material that may be selectively etched with respect to sacrificial fins403,404and that may allow selective epitaxial growth from substrate101(e.g., without epitaxial growth from dielectric layer402). Dielectric layer402may be formed in any suitable manner such as bulk deposition or thermal growth and planarization techniques or the like. In an embodiment, dielectric layer402is a silicon oxide. In some embodiments, dielectric layer402may include silicon nitride, silicon oxynitride, aluminum oxide, or the like. For example, dielectric layer402may deposited using a blanket deposition techniques such as chemical vapor deposition (CVD), plasma Enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), molecular beam epitaxy (MBE), metalorganic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), or the like, and a planar technique such as chemical mechanical polishing techniques may be used to expose sacrificial fins403,404.

FIG. 4Billustrates a transistor structure405similar to transistor structure401, after the removal of sacrificial fins403,404to form trenches406,407. Sacrificial fins403,404may be removed using any suitable technique such as an etch operation. As discussed, the size and shape of sacrificial fin403,404may define the size and shape of trenches406,407. In various embodiments, trenches406,407may have substantially vertical sidewalls, sloped sidewalls, or sloped and concave sidewalls, or the like. Trenches406,407may include width and heights. In some embodiments, the widths may be in the range of 8 to 20 nm. In some embodiments, the heights may be in the range of 200 to 350 nm.

Furthermore, facets408,409may be formed in substrate101as part of forming trenches406,407. For example, facets408,409may support or aid the subsequent epitaxial growth of materials within trenches406,407. In an embodiment, facets408,409may be (111) facets in a silicon substrate101. In some embodiments, facets408,409may not be formed in substrate101.

FIG. 4Cillustrates a transistor structure410similar to transistor structure405, after the formation of base layers103,105. Base layers103,105may be formed, for example, via any suitable epitaxial growth technique such as, for example, an epitaxial growth via chemical vapor deposition, metal organic chemical vapor deposition, atomic layer deposition, or any other epitaxial growth technique. Base layers103,105may include any suitable epitaxial layer materials. For example, base layers103,105may bridge any lattice mismatch between substrate101and subsequent subfin layers. In an embodiment, base layers103,105comprises gallium arsenide. Base layers103,105may have any suitable height such as a height in the range of about 50 to 120 nm.

FIG. 4Dillustrates a transistor structure411similar to transistor structure410, after the formation of mask412. Mask412may be formed using any suitable technique or techniques such as photolithography techniques. In some embodiments, mask412may include a hardmask material (e.g., silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or the like). Mask412may be any material that provides epitaxial growth selectivity with respect to base layer105.

As discussed herein, in some embodiments, subfin layers104,105may have different material compositions or different materials and/or fin channels121,131may have different material compositions or different materials. To form such devices, mask412may be provided such that one subfin layer and fin channel may be formed in one trench (e.g., for an NMOS or a PMOS transistor) while another is masked. Subsequently, the mask may be removed and the other subfin layer and the other fin channel may be formed in the now exposed trench (e.g., for the other type of transistor). The process flow illustrated viaFIGS. 4A-4Gmay provide for NMOS and PMOS transistors having the same base layers and may provide for different subfin layer and fin channel materials. However, in an embodiment, the NMOS and PMOS transistors may have the same subfin layers and such subfin layers may be formed without masking (e.g., simultaneously). In another embodiment, the NMOS and PMOS transistors may have different base layers and masking may be performed prior to the formation of such base layers. Furthermore, the process flow illustrated viaFIGS. 4A-4Gillustrates portions of a PMOS transistor being formed prior to the formation portions of an NMOS transistor. In some embodiments, portions of an NMOS transistor may be formed prior to the formation of portions of a PMOS transistor.

FIG. 4Eillustrates a transistor structure413similar to transistor structure411, after the formation of subfin layer106and fin channel414. Subfin layer106may be formed via any suitable epitaxial growth technique such as, for example, an epitaxial growth via chemical vapor deposition, metal organic chemical vapor deposition, atomic layer deposition, or any other epitaxial growth technique. In an embodiment, subfin layer106comprises aluminum indium phosphide. In an embodiment, subfin layer106comprises aluminum indium phosphide having a concentration of aluminum selected as described herein to provide a compressive strain on fin channel414(and subsequently formed fin channel131). Subfin layer106may have any suitable height such as a height in the range of about 50 to 120 nm.

Fin channel414may be formed, for example, via any suitable epitaxial growth technique such as, for example, an epitaxial growth via chemical vapor deposition, metal organic chemical vapor deposition, atomic layer deposition, or any other epitaxial growth technique. In an embodiment, fin channel414comprises germanium as discussed herein. As shown, fin channel414may have an overgrowth portion that extends above dielectric layer402. Such an overgrowth portion may be subsequently removed. Fin channel414(after removal of such an overgrowth portion) may have any suitable height such as a height in the range of about 50 to 120 nm. Also, as discussed, base layer105, subfin layer106, and fin channel414may have any suitable widths such as widths in the range of 8 to 20 nm.

FIG. 4Fillustrates a transistor structure415similar to transistor structure413, after the removal of mask412and the formation of fin channel131, subfin layer104, and fin channel121. For example, mask layer412may be removed using any suitable technique or techniques such as an etch (e.g., a dry or wet etch) or the like. Subfin layer104may be formed via any suitable epitaxial growth technique such as, for example, an epitaxial growth via chemical vapor deposition, metal organic chemical vapor deposition, atomic layer deposition, or any other epitaxial growth technique. In an embodiment, subfin layer104comprises aluminum indium phosphide. In an embodiment, subfin layer104comprises aluminum indium phosphide having a concentration of aluminum selected as described herein to provide a tensile strain on fin channel121. Subfin layer106may have any suitable height such as a height in the range of about 50 to 120 nm. In some embodiments, subfin layers106,104may have the same or substantially the same heights and, in other embodiments, their heights may be different.

Fin channel121may be formed, for example, via any suitable epitaxial growth technique such as, for example, an epitaxial growth via chemical vapor deposition, metal organic chemical vapor deposition, atomic layer deposition, or any other epitaxial growth technique. In an embodiment, fin channel121comprises germanium as discussed herein. In an embodiment, the formation of fin channel121may provide an overgrowth portion analogous to the overgrowth portion of fin channel414(please refer toFIG. 4E). Furthermore, the formation subfin layer104and fin channel121may include masking fin channel414(and subsequent mask removal) or not. In embodiments that do not include such masking, additional overgrowths of the materials of subfin layer104and fin channel121may grow from fin channel414and over dielectric layer402. In any event, such overgrowth portions may be removed by a planarization operation or the like to form fin channels121,131as illustrated inFIG. 4F. Fin channel121may have any suitable height such as a height in the range of about 50 to 120 nm. In some embodiments, fin channels121,131may have the same or substantially the same heights and, in other embodiments, their heights may be different. Also, as discussed, base layer103, subfin layer104, and fin channel121may have any suitable widths such as widths in the range of 8 to 20 nm.

FIG. 4Gillustrates a transistor structure416similar to transistor structure415, after recessing dielectric layer402to form dielectric layer102. As shown inFIG. 4G, in an embodiment, dielectric layer402may be recessed such that a top surface of dielectric layer102is below the bottom surfaces of fin channels121,131and above the top surfaces of subfin layers104,105. Dielectric layer402may be recessed using any suitable technique or techniques such as etch operations, timed etch operations, or the like.

As discussed with respect to process300andFIGS. 1A and 1B, gates, sources, and drains may be formed. Such gates, sources, and drains may be formed using any suitable technique or techniques. For example, gates may be formed using deposition techniques (e.g., conformal or bulk depositions) and patterning techniques (e.g., photolithography and etch techniques). Furthermore, sources and drains may be formed by selective growth of epitaxial sources and drains, by bulk deposition and patterning techniques, or the like.

FIGS. 4A-4Gillustrate an example process flow for fabricating transistor120and transistor130as discussed herein. In various examples, additional operations may be included or certain operations may be omitted. In particular, the illustrated process may provide for transistors with subfin layers and fin channels having different material compositions. As discussed, some operations may be omitted and/or modified to fabricate transistors having subfin layers and/or fin channels with the same material compositions or transistors with base layers having different material compositions, or the like.

FIG. 5is a view of an example SRAM cell500implementing one or more transistors having enhanced channel mobility and reduced leakage, arranged in accordance with at least some implementations of the present disclosure.FIG. 5illustrates an example 6 transistor (6T) SRAM cell500including access transistors520, pull-down transistors515, and pull-up transistors525. In various examples, access transistors520, pull-down transistors515, and pull-up transistors525may be implemented as transistor120and/or130. A complete SRAM memory circuit may be formed by interconnecting many SRAM cells such as SRAM cell500.

In an embodiment, one or more of access transistors520and pull-down transistors515are NMOS transistors and may include features discussed with respect to NMOS transistors herein and pull-up transistors525are PMOS transistors and may include features discussed with respect to NMOS transistors discussed herein. In an embodiment, access transistors520may include fin channel121comprising germanium, subfin layer104comprising aluminum indium phosphide adjacent to fin channel121, and base layer103adjacent to subfin layer104. In an embodiment, subfin layer104comprises gallium arsenide. Furthermore, in some embodiments, pull-down transistors515may include fin channel131, subfin layer106adjacent to fin channel131, and base layer105adjacent to subfin layer106. In an embodiment, pull-down transistors515include fin channel131comprising germanium, subfin layer106comprising aluminum indium phosphide adjacent to fin channel131, and base layer105comprising gallium arsenide adjacent to subfin layer106. In an embodiment, subfin layer106may comprise an aluminum to indium ratio greater than the aluminum to indium ratio of subfin layer104. As discussed, such material suggestions may provide stress engineering to optimize the performance of pull-down transistors515and pull-up transistors525.

FIG. 6is an illustrative diagram of a mobile computing platform600employing an IC with transistor(s) having germanium fin channels and aluminum indium phosphide subfin layers, arranged in accordance with at least some implementations of the present disclosure. A transistor or transistors having germanium fin channels and aluminum indium phosphide subfin layers may be any transistors as discussed herein such as transistor120or transistor130or the like. In some examples, NMOS and PMOS transistors as discussed herein may be implemented together as a CMOS circuit. Mobile computing platform600may be any portable device configured for each of electronic data display, electronic data processing, wireless electronic data transmission, or the like. For example, mobile computing platform600may be any of a tablet, a smart phone, a netbook, a laptop computer, etc. and may include a display screen605, which in the exemplary embodiment is a touchscreen (e.g., capacitive, inductive, resistive, etc. touchscreen), a chip-level (SoC) or package-level integrated system610, and a battery615.

Integrated system610is further illustrated in the expanded view620. In the exemplary embodiment, packaged device650(labeled “Memory/Processor” inFIG. 6) includes at least one memory chip (e.g., RAM), and/or at least one processor chip (e.g., a microprocessor, a multi-core microprocessor, or graphics processor, or the like). In an embodiment, package device650is a microprocessor including an SRAM cache memory. In an embodiment, package device650includes one or more of transistor120or transistor130or both. For example, an employed transistor may include a germanium fin channel and an aluminum indium phosphide subfin layer adjacent to the germanium fin channel. Packaged device650may be further coupled to (e.g., communicatively coupled to) a board, a substrate, or an interposer660along with, one or more of a power management integrated circuit (PMIC)630, RF (wireless) integrated circuit (RFIC)625including a wideband RF (wireless) transmitter and/or receiver (TX/RX) (e.g., including a digital baseband and an analog front end module further comprises a power amplifier on a transmit path and a low noise amplifier on a receive path), and a controller thereof635. In general, packaged device650may be also be coupled to (e.g., communicatively coupled to) display screen605.

Functionally, PMIC630may perform battery power regulation, DC-to-DC conversion, etc., and so has an input coupled to battery615and with an output providing a current supply to other functional modules. In an embodiment, PMIC630may perform high voltage operations. As further illustrated, in the exemplary embodiment, RFIC625has an output coupled to an antenna (not shown) to implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. In alternative implementations, each of these board-level modules may be integrated onto separate ICs coupled to the package substrate of packaged device650or within a single IC (SoC) coupled to the package substrate of the packaged device650.

FIG. 7is a functional block diagram of a computing device700, arranged in accordance with at least some implementations of the present disclosure. Computing device700may be found inside platform600, for example, and further includes a motherboard702hosting a number of components, such as but not limited to a processor701(e.g., an applications processor) and one or more communications chips704,705. Processor701may be physically and/or electrically coupled to motherboard702. In some examples, processor701includes an integrated circuit die packaged within the processor701. In general, the term “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

In various examples, one or more communication chips704,705may also be physically and/or electrically coupled to the motherboard702. In further implementations, communication chips704may be part of processor701. Depending on its applications, computing device700may include other components that may or may not be physically and electrically coupled to motherboard702. These other components may include, but are not limited to, volatile memory (e.g., DRAM)707,708, non-volatile memory (e.g., ROM)710, a graphics processor712, flash memory, global positioning system (GPS) device713, compass714, a chipset706, an antenna716, a power amplifier709, a touchscreen controller711, a touchscreen display717, a speaker715, a camera703, and a battery718, as illustrated, and other components such as a digital signal processor, a crypto processor, an audio codec, a video codec, an accelerometer, a gyroscope, and a mass storage device (such as hard disk drive, solid state drive (SSD), compact disk (CD), digital versatile disk (DVD), and so forth), or the like.

Communication chips704,705may enables wireless communications for the transfer of data to and from the computing device700. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. Communication chips704,705may implement any of a number of wireless standards or protocols, including but not limited to those described elsewhere herein. As discussed, computing device700may include a plurality of communication chips704,705. For example, a first communication chip may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

The following examples pertain to further embodiments.

In one or more first embodiments, an integrated circuit comprises a transistor including a fin channel comprising germanium and a subfin having a first layer adjacent to the fin channel and a second layer adjacent to the first layer, wherein the first layer comprises aluminum indium phosphide.

Further to the first embodiments, the integrated circuit further comprises a second transistor including a second fin channel and a second subfin having a third layer adjacent to the fin channel and a fourth layer adjacent to the first layer, wherein the transistor is a PMOS transistor and the second transistor is an NMOS transistor.

Further to the first embodiments, the integrated circuit further comprises a second transistor including a second fin channel and a second subfin having a third layer adjacent to the fin channel and a fourth layer adjacent to the first layer, wherein the transistor is a PMOS transistor and the second transistor is an NMOS transistor and the third layer comprises aluminum indium phosphide having the same composition as the first layer.

Further to the first embodiments, the integrated circuit further comprises a second transistor including a second fin channel and a second subfin having a third layer adjacent to the fin channel and a fourth layer adjacent to the first layer, wherein the transistor is a PMOS transistor and the second transistor is an NMOS transistor, the second fin channel comprises germanium, the first layer comprises a first aluminum to indium ratio, and the third layer comprises aluminum indium phosphide having a second aluminum to indium ratio less than the first aluminum to indium ratio.

Further to the first embodiments, the integrated circuit further comprises a second transistor including a second fin channel and a second subfin having a third layer adjacent to the fin channel and a fourth layer adjacent to the first layer, wherein the transistor is a PMOS transistor and the second transistor is an NMOS transistor and the second fin channel comprises indium gallium arsenide and the third layer comprises gallium arsenide.

Further to the first embodiments, the second layer comprises gallium arsenide.

Further to the first embodiments, the integrated circuit further comprises a dielectric layer adjacent to the second layer and a first portion of the first layer, wherein a second portion of the first layer extends beyond a top surface of the dielectric layer, and a substrate, wherein the first layer and the dielectric layer are on the substrate.

Further to the first embodiments, the second layer comprises gallium arsenide and/or the integrated circuit further comprises a dielectric layer adjacent to the second layer and a first portion of the first layer, wherein a second portion of the first layer extends beyond a top surface of the dielectric layer, and a substrate, wherein the first layer and the dielectric layer are on the substrate.

Further to the first embodiments, the transistor is a PMOS transistor and the first layer comprises aluminum indium phosphide having an aluminum concentration in the range of 100% to 50%.

Further to the first embodiments, the transistor is an NMOS transistor and the first layer comprises aluminum indium phosphide having an aluminum concentration in the range of 35% to 50%.

In one or more second embodiments, an SRAM cell comprises an NMOS transistor including a fin channel comprising germanium and a subfin having a first layer adjacent to the fin channel and a second layer adjacent to the first layer, wherein the first layer comprises aluminum indium phosphide, and a PMOS transistor including a second fin channel and a second subfin having a third layer adjacent to the fin channel and a fourth layer adjacent to the first layer.

Further to the second embodiments, the second fin channel comprises germanium, the first layer comprises a first aluminum to indium ratio, and the third layer comprises aluminum indium phosphide having a second aluminum to indium ratio greater than the first aluminum to indium ratio.

Further to the second embodiments, the second fin channel comprises at least one of germanium, silicon, or a III-V material.

Further to the second embodiments, the second layer comprises gallium arsenide.

Further to the second embodiments, the SRAM cell further comprises an insulator layer adjacent to the second layer and a first portion of the first layer, wherein a second portion of the first layer extends beyond the insulator layer, and a substrate, wherein the first layer and the insulator are on the substrate.

Further to the second embodiments, the second fin channel comprises at least one of germanium, silicon, or a III-V material and/or the second layer comprises gallium arsenide and/or the SRAM cell further comprises an insulator layer adjacent to the second layer and a first portion of the first layer, wherein a second portion of the first layer extends beyond the insulator layer, and a substrate, wherein the first layer and the insulator are on the substrate.

In one or more third embodiments, a method for fabricating an integrated circuit comprises forming a subfin having a first layer over a substrate and a second layer over the first layer, wherein the second layer comprises aluminum indium phosphide and disposing a fin channel comprising germanium over the second layer of the subfin.

Further to the third embodiments, forming the subfin and disposing the fin channel comprises forming a trench in a dielectric layer, epitaxially growing the first layer, epitaxially growing the second layer, epitaxially growing the fin channel, and recessing the dielectric layer such that a top surface of the dielectric layer is below a top surface of the second layer.

Further to the third embodiments, the method further comprises forming a second subfin having a third layer over the substrate and a fourth layer over the third layer and disposing a second fin channel comprising germanium over the fourth layer, wherein the fourth layer comprises aluminum indium phosphide having a different aluminum concentration than the second layer.

Further to the third embodiments, the method further comprises forming a second subfin and disposing a second fin channel comprising at least one of germanium, silicon, or a III-V material over the second subfin.

Further to the third embodiments, the first layer comprises gallium arsenide.

Further to the third embodiments, the method further comprises forming a second subfin having a third layer over the substrate and a fourth layer over the third layer and disposing a second fin comprising germanium over the fourth layer, wherein the fourth layer comprises aluminum indium phosphide having a different aluminum concentration than the second layer, and wherein forming the second subfin and disposing the second fin channel comprises forming a first sacrificial fin and a second sacrificial fin each adjacent to a dielectric layer, removing the first and second sacrificial fins to form a first trench and a second trench, epitaxially growing the first layer within the first trench and the third layer within the second trench, masking the first layer and the first trench, epitaxially growing the fourth layer within the second trench, and epitaxially growing the second fin within the second trench.

In one or more fourth embodiments, a mobile computing platform comprises any of the example structures discussed with respect to the first or second embodiments.