Light emitting display and data driver there of

An organic light emitting diode display being driven according to a current programming method. A digital/analog converter of a data driver sequentially converts data signals representing gray scales to data currents and sequentially transmits the data currents to an output stage. The output stage sequentially samples the data currents and concurrently transmits the data currents to data lines. A precharge voltage is applied to a wire between the digital/analog converter and the output stage before a respective one of the data currents is transmitted to the output stage. As such, the data currents may be properly transmitted to the output stage.

CROSS-REFERENCES TO RELATED APPLICATIONS

This application claims priority to and the benefit of Korean Patent Application Nos. 10-2004-0080371, 10-2004-0080373, and 10-2004-0080374 filed in the Korean Intellectual Property Office on Oct. 8, 2004, the entire contents of which are incorporated herein by reference.

FIELD OF THE INVENTION

The present invention relates to a light emitting display, and more particularly, to a data driver for outputting data currents in the light emitting display.

BACKGROUND OF THE INVENTION

A light emitting display is a display device which uses a plurality of light emitting elements to display an image. Each of the light emitting elements emits light according to an applied current. Particularly, an organic light emitting diode display uses an organic light emitting cell as the light emitting element, and the organic light emitting cell has characteristics of a diode and can be referred to as an organic light emitting diode (OLED). The organic light emitting cell includes an anode, an organic thin film, and a cathode.

According to an addressing method, methods for driving the organic light emitting cells may be classified into a passive matrix method or an active matrix method. In the passive matrix method, the organic light emitting cells are formed between anode lines and cathode lines perpendicularly crossing the anode line, and driven by selecting the respective lines. In the active matrix method, a thin film transistor is coupled to each pixel electrode (e.g., an anode line), and the organic light emitting cells are driven according to a voltage maintained by a capacitor coupled to a gate of a thin film transistor. Further, depending on formats of signals applied to the capacitor for maintaining the voltage, the active matrix method may be categorized as either a voltage programming method or a current programming method.

A pixel circuit according to the voltage programming method has difficulties in obtaining high gray scales because of deviations in threshold voltages and/or in electron mobilities of thin film transistors, the deviations being caused by non-uniformity of a manufacturing process. On the other hand, according to the current programming method, uniform display characteristics are achieved even though driving transistors in each pixel have non-uniform voltage-current characteristics, provided that a current source for supplying the current to the pixel is uniform throughout the whole panel (i.e., all the data lines).

However, in the light emitting display using the current programming method, it is necessary to provide a data driver which converts a data signal representing a gray scale to an analog current (hereinafter, “data current”) to be applied to a data line coupled to the pixel circuit.

The data driver needs a digital/analog converter for converting the digital data signal to the analog data current and an output stage for buffering and outputting the converted data current. Generally, before the data currents are transmitted to the data lines during one horizontal period, the output stage has to buffer the data currents corresponding to the pixel circuits on one row during the horizontal period. However, as the resolution of a light emitting display becomes higher, a horizontal period becomes shorter. Because of this, the output stage may not be able to buffer the data currents during the horizontal period when a magnitude of a data current is small. As a result, the data currents can be improperly transmitted to the data lines.

SUMMARY OF THE INVENTION

An embodiment of the present invention provides a data driver for converting data signals representing gray scales to data currents and for outputting the data currents to data lines. The embodiment of the present invention also provides a data driver for properly transmitting the data current to an output stage.

According to an embodiment of the present invention, a wire coupled to an output stage is precharged before a data current is transmitted to the output stage.

One embodiment of the invention provides a data driver for sequentially receiving a plurality of data signals representing gray scales and applying a plurality of data currents to a plurality of data lines formed on a display area of a light emitting display. The data driver includes at least one converter, at least one output stage, at least one wire, and a precharge unit. The converter converts the data signals to the data currents, and the output stage sequentially receives the data currents transmitted from the converter and transmits the received data currents to the data lines. The wire is coupled between the converter and the output stage, and the precharge unit applies a precharge voltage to the wire before a respective one of the data currents is transmitted to the output stage.

According to an exemplary embodiment of the present invention, the converter includes a first transistor having a drain to which the respective one of the data currents flows. The precharge unit includes a second transistor coupled to the first transistor as a current mirror, and outputs a voltage corresponding to a drain voltage of the second transistor determined by the respective one of the data currents as the precharge voltage. Herein, the precharge unit may further include a unit gain amplifier coupled between the drain of the second transistor and a first terminal of the wire.

According to another exemplary embodiment of the present invention, the precharge voltage is predetermined and is independent of the data currents.

According to still another exemplary embodiment of the present invention, the converter includes a first transistor having a drain coupled to a first terminal of the wire and a source coupled to a first power source for supplying a first voltage. The output stage includes a second transistor having a drain coupled to a second terminal of the wire and a source coupled to a second power source for supplying a second voltage. The precharge unit outputs a third voltage between the second voltage and the first voltage as the precharge voltage.

According to another exemplary embodiment of the present invention, the precharge unit determines a voltage corresponding to a respective one of the data signals to be the precharge voltage.

According to yet another exemplary embodiment of the present invention, the precharge unit includes a voltage converter for generating the precharge voltage from at least one data bit among a plurality of data bits of the respective one of the data signals.

One embodiment of the invention provides a light emitting display including a display area, a scan driver, and a data driver. The display area includes a plurality of data lines, a plurality of first scan lines, a plurality of second scan lines, and a plurality of pixel areas. The first and second scan lines are extending perpendicular to the data lines, and each of the pixel areas is defined by a respective one of the data lines and a respective one of the first scan lines and has at least one light emitting element. The scan driver selectively transmits a plurality of select signals to the plurality of first scan lines, and selectively transmits a plurality of emission control signals to the plurality of second scan lines. The data driver includes a converter for sequentially receiving a plurality of data signals and for sequentially converting the plurality of data signals to a plurality of data currents, and an output stage for sequentially receiving the data currents from the converter and for transmitting the data currents to the plurality of data lines. A precharge voltage is applied to a wire coupled between the converter and the output stage before a respective one of the data currents is transmitted from the converter to the output stage.

DETAILED DESCRIPTION

FIG. 1shows a plan view of a light emitting display according to an exemplary embodiment of the present invention.

As shown inFIG. 1, the light emitting display includes a display area100seen as a screen to a user, a scan driver200, and a data driver300.

The display area100includes a plurality of data lines D1to Dm, a plurality of select scan lines S1to Sn, a plurality of emit scan lines E1to En, and a plurality of sub-pixels110. The data lines D1to Dmare extended in a column direction and transmit data currents representing images to the corresponding sub-pixels110. The select scan lines S1to Snare extended in a row direction and transmit select signals for selecting corresponding data lines D1to Dmcrossing to the select scan lines S1to Snto apply the data currents to the sub-pixels110of the corresponding data and scan lines D1to Dmand S1to Sn. The emit scan lines E1to Emare extended in a row direction and transmit emission control signals for controlling light emission of the sub-pixels110.

A pixel area is defined by one of the data lines D1to Dmand one of the select scan lines S1to Sn, and a sub-pixel110is formed on the pixel area. For example, the sub-pixel110coupled to the ithselect scan line and the jthdata line programs the data current from the data line Djin response to the select signal from the select scan line Si, and represents a gray scale corresponding to the programmed data current in response to the emission control signal from the emit scan line Ei. Also, it is assumed that a pixel is formed by the sub-pixel for emitting light of the red (R) color, the sub-pixel for emitting light of the green (G) color, and the sub-pixel for emitting light of the blue (B) color.

The data driver300sequentially receives the data signals representing gray scales from a timing controller (not shown), converts the received data signals to the data currents, and applies the converted data currents to the data lines D1to Dmcorresponding to the sub-pixels110of the data and scan lines D1to Dmand S1to Snto which select signals are applied. The scan driver200sequentially applies the select signals to the select scan lines S1to Sn, and sequentially applies the emission control signals to the emit scan lines E1to Em.

In one embodiment, the scan driver200and/or the data driver300are fabricated as integrated circuits (ICs) and the ICs are mounted on a substrate on which the display area100is formed. Alternatively, in one embodiment, the ICs are mounted on flexible connecting members, such as tape carrier packages (TCPs), flexible printed circuits (FPCs), and the flexible connecting members that are attached to the substrate to be coupled thereto. On the other hand, the scan driver200and/or the data driver300may be substituted with driving circuits formed in the substrate, which are made of the same layers as the scan lines, the data lines, and the transistors for driving the sub-pixels. In addition, the scan driver200and/or the data driver300may be mounted on printed circuit boards which are electrically coupled to the substrate on which the display area100is formed.

The data driver300ofFIG. 1will be described in more detail with reference toFIG. 2andFIG. 3.

FIG. 2shows a diagram of a configuration of the data driver300according to a first exemplary embodiment of the present invention, andFIG. 3shows a diagram of a configuration of a multiplexing processor330of the data driver300shown inFIG. 2. For exemplary purposes,300data lines D1to D300corresponding to 100 pixels, i.e., 100 data lines corresponding to R sub-pixels, 100 data lines corresponding to G sub-pixels, and 100 data lines corresponding to B sub-pixels, are shown inFIG. 2andFIG. 3. That is, the data driver300with 300 channels is exemplarily described, but the present invention is not thereby limited. Also, it is assumed that the data signals corresponding to the 100 pixels of one row are sequentially input to the data driver300, and the R, G, and B data signals corresponding to the 3 sub-pixels of the pixel are input to the data driver300in parallel.

As shown inFIG. 2, the data driver300includes a shift register310, a latch320, a multiplexing processor330, a digital to analog (hereinafter, D/A) converting unit340, a control signal generator350, and an output stage360. InFIG. 2, the latch320, the multiplexing processor330, the D/A converting unit340, and the output stage360process the R, G, and B data signals or the R, G, and B data currents corresponding to one pixel in parallel.

The shift register310sequentially shifts a sampling signal to transmit a plurality of sampling signals SRH0to SRH99to the latch320. The latch320sequentially samples and holds the R, G, and B data signals DR0to DR99, DG0to DG99, and DB0to DB99according to the sampling signals SRH0to SRH99, and includes a sampling latch321and a hold latch322.

In more detail, the shift register310generates the sampling signal SRH0in response to an enable signal IE, and sequentially shifts the sampling signals SRH0in synchronization with a clock CLKH to sequentially output the plurality of sampling signals SRH0to SRH99. As such, the 100 sampling signals SRH0to SRH99corresponding to the 100 pixels on the one row are generated.

The sampling latch321sequentially samples the R, G, and B data signals DR0to DR99, DG0to DG99, and DB0to DB99in response to the sampling signals SRH0to SRH99, respectively. That is, the sampling latch321samples the R, G, and B data signals DRi, DGi, and DBi corresponding to the (i+1)thpixel in response to the sampling signal SRHi (where, ‘i’ is an integer between 0 and 99). In one embodiment, if the R, G, and B data signals DRi, DGi, and DBi are respectively 10 bits data, the sampling latch321samples 30 bits data for each pixel. The hold latch322holds the data signals which are sequentially sampled by the sampling latch321until the data signals corresponding to the one row are sampled, and outputs the sampled data signals DR0to DR99, DG0to DG99, and DB0to DB99in response to a holding enable signal DH.

As shown inFIG. 3, the multiplexing processor330includes a shift register331and a multiplexer332. The shift register331sequentially outputs multiplexing signals MSW0to MSW99and shift signals SRL0to SRL99by receiving a clock CLKL and an enable signal DAS. At this time, a frequency of the clock CLKL applied to the shift register331may be less than the same of the clock CLKH applied to the shift register310, and the enable signal DAS has a same timing as the enable signal DH applied to the holding latch322. The multiplexing signals MSW0to MSW99and the shift signals SRL0to SRL99are output from the timing controller (not shown) in synchronization with the clock CLKL. In addition, the multiplexing signals MSW0to MSW99are transmitted to the multiplexer332of the multiplexing processor330, and the shift signals SRL0to SRL99are transmitted to the control signal generator350.

The multiplexer332of the multiplexing processor330multiplexes each of the R, G, and B data signals DR0to DR99, DG0to DG99, and DB0to DB99output from the holding latch322in response to each of the multiplexing signals MSW0to MSW99, and sequentially transmits the R, G, and B data signals DR0to DR99, DG0to DG99, and DB0to DB99to the D/A converting unit340. That is, the multiplexer332transmits the R, G, and B data signals DRi, DGi, and DBi to the D/A converting unit340in response to the multiplexing signal MSWi.

The D/A converting unit340sequentially converts the R, G, and B data signals DR0to DR99, DG0to DG99, and DB0to DB99to the data currents R0to R99, G0to G99, and B0to B99, and sequentially outputs the converted data currents R0to R99, G0to G99, and B0to B99to the output stage360. Herein, the D/A converting unit340includes R, G, and B D/A converters341,342, and343, and the R, G, and B D/A converters341,342, and343respectively convert the R, G, and B data signals to the R, G, and B data currents.

The control signal generator350sequentially receives the shift signals SRL0to SRL99from the multiplexing processor330, and generates sampling signals CHS0to CHS99to sequentially output them to the output stage360. The sampling signal CHSi is generated by the shift signal SRLi to be synchronized with a time when the R, G, and B data currents Ri, Gi, and Bi converted by the D/A converting unit340in response to the multiplexing signal MSWi are transmitted to the output stage360.

The output stage360sequentially samples the R, G, and B data currents R0to R99, G0to G99, and B0to B99in response to each of the sampling signals CHS0to CHS99. That is, the output stage360samples the R, G, and B data currents Ri, Gi, and Bi, which are input from the D/A converting unit340in response to the sampling signal CSH1. The output stage360samples the R, G, and B data currents R0to R99, G0to G99, and B0to B99corresponding to the pixels of one row and concurrently outputs the sampled R, G, and B data currents R0to R99, G0to G99, and B0to B99to the corresponding data lines D1to D300.

In the above, a process has been described in which the R, G, and B data signals corresponding to the pixels of one row are input to the data driver300to be converted to the data currents, and the data currents are output to the data lines of the display area100. The data driver300repeatedly performs this process to the R, G, and B data signals corresponding to the pixels of all rows, thereby converting the data signals corresponding to one frame to the data currents and outputting the converted data currents to the data lines of the display area100. In addition, according to the first exemplary embodiment, the D/A converters are not formed according to the data lines D1to Dmbut formed according to the colors of the R, G, and B data Therefore, the number of the D/A converters can be reduced.

Next, an example of the D/A converting unit340used in the data driver300will be described with reference toFIG. 4.FIG. 4shows a diagram of a configuration of an example of the D/A converter341. InFIG. 4, the R D/A converter341of the D/A converting unit340is shown, and the G and B D/A converters342and343having substantially the same structure as the R D/A converter341will not be shown and/or described in more detail.

Referring toFIG. 4, the D/A converter341includes a transistor TB coupled to a current source IB, 10 mirror transistors T0to T9, switches SW0to SW9, and an output terminal341a(shown inFIG. 5). The transistors T0to T9are respectively coupled to the transistor TB as current mirrors, and sizes of the mirror transistors T0to T9are respectively 20to 29times a size of the transistor TB. Herein, the size of the transistor is a ratio W/L of a channel width W and a channel length L of the transistor. In more detail, the transistor TB is diode-connected, and has a source coupled to a power voltage VDD1and a drain coupled to the current source IB. The transistor Tj has a source coupled to the power voltage VDD1and a gate coupled to a gate of the transistor TB (where ‘j’ is an integer from 0 to 9). A switch SWj is coupled between a drain of the transistor Tj and the output terminal341a(FIG. 5) of the D/A converter341.

Then, currents 20IBto 29IB, which are respectively 20to 29times the current IBflowing through the drain of the transistor TB, respectively output through the drains of the mirror transistors T0to T9. Each of the switches SW0to SW9is turned on in response to a one bit data of the 10 bits R data signal DRi which are sequentially transmitted from the multiplexer332of the multiplexing processor330. For example, when the R data signal DRi is “0101000101”, the switches SW0, SW2, SW6, and SW8corresponding to bit data of ‘1’ are turned on so that a data current Iintransmitted to the output terminal341a(FIG. 5) of the D/A converter341is (20+22+26+28)IB.

As described above, the D/A converters respectively convert the R, G, and B data signals to the R, G, and B data currents and respectively transmit the R, G, and B data currents to the output stage360through wires370(shown inFIG. 5).

FIG. 5shows the output terminal341aof the D/A converter341and an input terminal361of the output stage360in the data driver300according to the first exemplary embodiment of the present invention. InFIG. 5, only the output terminal341aof the R D/A converter341and the input terminal361of the output stage360coupled to the R D/A converter341are shown, and the output terminals of the G and B D/A converters342and343have substantially the same structure as that341aof the R D/A converter341. In addition, the output stage360has input terminals which are coupled to the G and B D/A converters342and343and have substantially the same structure as that361coupled to R D/A converter341.

As shown inFIG. 5, the output terminal341aof the D/A converter341includes a current mirror M1and M2, and the input terminal361of the output stage360also includes a current mirror M3and M4. InFIG. 5, transistors M1and M2forming the current mirror of the D/A converter341are depicted as NMOS transistors, and transistors M3and M4forming the current mirror of the output stage360are depicted as PMOS transistors

In the output terminal341a, the data current Iinfrom the D/A converter341is transmitted to a drain of the diode-connected transistor M1, and a source of the transistor M1is coupled to a ground voltage. The transistor M2has a source coupled to the ground voltage and a gate coupled to a gate of the transistor M1, and a drain of the transistor M2is coupled to the input terminal361of the output stage360through the wire370.

In the input terminal361, a drain of the diode-connected transistor M3is coupled to the output terminal341aof the D/A converter341through the wire370, and a source of the transistor M3is coupled to a power voltage VDD2. The transistor M4has a source coupled to the power voltage VDD2and a gate coupled to a gate of the transistor M3. A current flowing to a drain of the transistor M4is an input current of the output stage360.

The two transistors M1and M2have the-same size, and the two transistors M3and M4have the same size. Because of this, a current having the same magnitude as the data current Iinflowing to the drain of the transistor M1flows from the drain of the transistor M3to the drain of the transistor M2through the wire370. Therefore, a current having the same magnitude as the data current Iinof the D/A converter341flows to the drain of the transistor M4of the output stage360.

In a like manner, when the R, G, and B data currents corresponding to the pixels on one row are sequentially output from the D/A converting unit340, the output stage sequentially samples these R, G, and B data currents. Herein, a period during which the R, G, and B data currents corresponding to the pixels on one row are transmitted to the output stage360is substantially equal to one horizontal period. That is, a period during which the R, G, and B data currents corresponding to the one pixel transmitted to the output stage360(hereinafter, “a data transmitting period”) is a period corresponding to 1/100 of the one horizontal period. However, when the magnitude of the data current is small and parasitic components on the wire370are great, the data currents may not be properly transmitted to the output stage360during the data transmitting period so that the output stage360does not sample the required currents.

FIG. 6shows the output terminal341aof the D/A converter341, a precharge unit380a, and the input terminal361of the output stage360in the data driver according to a second exemplary embodiment of the present invention.

As shown inFIG. 6, the data driver according to the second exemplary embodiment further includes the precharge units380awhich are respectively coupled between the output terminals of the R, G, and B D/A converters341,342, and343and the input terminals (e.g. the input terminal361) of the output stage360in contrast with the first exemplary embodiment. Only the precharge unit380acoupled to the output terminal341aof the R D/A converter341and the input terminal361of the output stage360are shown inFIG. 6, and the precharge units having substantially the same structure as the precharge unit380arespectively are coupled to the G and B D/A converters342and343.

The precharge unit380aincludes transistors M5and M6, switches SW11and SW12, and a unit gain amplifier381. InFIG. 6, the transistor M5is depicted as an NMOS transistor, and the transistor M6is depicted as a PMOS transistor.

The transistor M5has a gate coupled to the gate of the transistor M1and a source coupled to the ground voltage, and forms a current mirror together with the transistor M1. The transistor M6is diode-connected, and has a drain coupled to the drain of the transistor M5and a source coupled to the power voltage VDD2. The transistors M5and M6respectively have the same sizes and characteristics as the transistors M2and M3. The drains of the transistors M5and M6are coupled to an input terminal of the unit gain amplifier381, and the switch SW11is coupled between an output terminal of the unit gain amplifier381and a first terminal of the wire370. The switch SW12is coupled between the input terminal361of the output stage361and a second terminal of the wire370. Herein, an output voltage of the unit gain amplifier381is applied to the wire370as a precharge voltage.

Next, an operation of the precharge unit380awill be described also with reference toFIG. 7.FIG. 7shows a switching timing diagram of the precharge unit380aofFIG. 6. InFIG. 7, the data transmitting period corresponding to the one pixel is shown, and a high level and a low level respectively represent a turn-on state and a turn-off state of each of the switches SW11and SW12.

ReferringFIG. 7, the data transmitting period includes a precharge period Tp and a mirroring period Tm.

In the precharge period Tp, the switch SW11is turned on, and the switch SW12is turned off. Then, a current having the same magnitude as the data current Iintransmitted to the drain of the transistor M1flows to the drain of the transistor M5, and a voltage at the drain of the transistor M5is determined by the drain current of the transistor M5. That is, the power voltage VDD2is divided by on-resistances of the transistors M5and M6to be the voltage at the drain of the transistor M5. Then, the unit gain amplifier381applies the precharge voltage having substantially the same level as the voltage at the drain of the transistor M5to the first terminal of wire370and the drain of the transistor M2. Accordingly, a voltage at the wire370and the drain voltage of the transistor M2are substantially equal to the voltage at the drain of the transistor since the switch SW12is turned off.

In the mirroring period Tm, the switch SW11is turned off, and the switch SW12is turned on. Since the voltage at the wire370has been set to be substantially equal to the drain voltage of the transistor M2in the precharge period Tp, the drain voltage of the transistor M3is substantially equal to the drain voltage of the transistor M2when the switch SW12is turned on. In this embodiment, since the sizes and characteristics of the transistors M2and M3are respectively the same as those of the transistors M5and M6, and the voltage at the drains of the transistors M2and M3are equal to the voltage at the drains of the transistors M5and M6. Accordingly, a current flowing to the drains of the transistors M2and M3is substantially equal to the data current Iinflowing to the drains of the transistors M5and M6in the beginning of the mirroring period Tm. That is, the data current Iincan be transmitted from the drain of the transistor M1to the drain of the transistor M3in the beginning of the mirroring period Tm.

As described above, according to the second exemplary embodiment, the data current Iincan be transmitted from the output terminal341aof the D/A converter341to the input terminal361of the output stage360even if the data transmitting period is short.

FIG. 8shows the output terminal341aof the D/A converter341, a precharge unit380b, and the input terminal361of the output stage360in the data driver according to a third exemplary embodiment of the present invention, andFIG. 9shows a switching timing diagram of the precharge unit380bofFIG. 8. InFIG. 9, a high level and a low level respectively represent a turn-on state and a turn-off state of each of the switches SW13, SW14, and SW15.

As shown inFIG. 8, the data driver according to the third exemplary embodiment has substantially the same structure as the second exemplary embodiment except for the precharge unit380b.

In more detail, the precharge unit380bincludes resistors R11and R12, and switches SW13, SW14, and SW15. The resistors R11and R12are coupled in series between the power voltage VDD2and the ground voltage, and the resistors R11and R12have substantially the same resistance magnitudes. The switch SW13is coupled between the gate of the transistor M1and the gate of the transistor M2, and the switch SW14is coupled between the second terminal of the wire370and the drain of the transistor M3. The switch SW15is coupled between a point where the resistors R11and R12meet and the first terminal of the wire370.

Referring toFIG. 9, in a precharge period Tp′, the switches SW13and SW14are turned off, and the switch SW15is turned on. Then, the power voltage VDD2and the ground voltage are divided by the resistors R11and R12so that a voltage VDD2/2 corresponding to a half of the power voltage VDD2is applied to the first terminal of the wire370as the precharge voltage.

Next, in a mirroring period Tm′, the switch SW15is turned off and the switches SW13and SW14are turned on. Then, the drain voltages of the transistors M2and M3are determined by the data current Iinbetween the power voltage VDD2and the ground voltage. In the meantime, since the drains of the transistors M2and M3coupled to the wire370have been precharged to the VDD2/2 voltage in the precharge period Tp′, the drain voltages of the transistors M2and M3can be quickly changed to voltages corresponding to the data current Iin. Therefore, in one embodiment of the present invention, a period during which the data current Iinis transmitted to the drain of the transistor M3is shortened.

While the wire370has been described to be precharged to VDD2/2 voltage by the resistors R11and R12having the same resistance magnitudes in the third exemplary embodiment, the resistors R11and R12may have different resistance magnitudes so that the wire370is precharged to another voltage.

FIG. 10shows the output terminal341aof the D/A converter341, a precharge unit380c, and the input terminal361of the output stage360in the data driver according to a fourth exemplary embodiment of the present invention, andFIG. 11shows a switching timing diagram of the precharge unit380cofFIG. 10. InFIG. 11, a high level and a low level respectively represent a turn-on state and a turn-off state of each of the switches SW16and SW17.

As shown inFIG. 10, the data driver according to the fourth exemplary embodiment has substantially the same structure as that of the second exemplary embodiment, except for the precharge unit380c.

In more detail, the precharge unit380cincludes a voltage D/A converter382, and switches SW16and SW17. The voltage D/A converter382receives the R data signal DRi transmitted to the D/A converter341and converts the received R data signal DRi to a voltage. The switch SW16is coupled between an output terminal of the voltage D/A converter382and the first terminal of the wire370, and the switch SW17is coupled to the second terminal of the wire370and the input terminal361of the output stage360. A voltage of the wire370can be calculated when the data current Iinflows to the input terminal361. That is, the drain voltage of the transistor M3when the data current flows to the drains of the transistors M2and M3corresponds to the voltage of the wire370. Accordingly, the precharge unit380creceives the data signal DRi transmitted to the D/A converter341, and converts the data signal DRi to a voltage equivalent to when the data current corresponding to the data signal DRi flows to the input terminal361of the output stage360. In addition, the precharge unit380capplies the converted voltage to the first terminal of the wire370as the precharge voltage.

ReferringFIG. 11, in a precharge period Tp″, the switch SW16is turned on, and the switch SW17is turned off. Then, the D/A converter382generates the precharge voltage according to the data signal DRi transmitted to the D/A converter382and applies the precharge voltage to the wire370through the switch SW16. That is, the wire370is charged to the precharge voltage.

Next, in a mirroring period Tm″, the switch SW16is turned off, and the switch SW17is turned on. Since the wire370has been charged to the precharge voltage corresponding to the data signal DRi, the current flowing to the drain of the transistor M1can be transmitted to the drain of the transistor M3in the beginning of the mirroring period Tm″.

As described above, the drain voltage of the transistor M3when the data current Iincorresponding to the data signal DRi flows to drains of the transistors M2and M3is used as the precharge voltage in the fourth exemplary embodiment.

Generally, the voltage D/A converter382uses a plurality of resistors coupled in series and a plurality of switches respectively coupled to the plurality of resistors to convert the data signal to the precharge voltage. When the data signal DRi is 10 bits data, the voltage D/A converter382needs a large number of the resistors and the switches for processing the 210data signals so that a dimension of the voltage D/A converter382increases. In order to reduce the dimension of the voltage D/A converter382, the precharge voltage may be determined by high order bits of the 10 bits data.

FIG. 12shows an example of the voltage D/A converter382shown inFIG. 10. InFIG. 12, the voltage D/A converter382is shown to determine the precharge voltage by using 3 high order bits D0, D1, and D2of 10 bits data signal.

As shown inFIG. 12, the voltage D/A converter382includes a plurality of resistors R1to R7, and a plurality of switches S10to S17, S20to S23, S30, and S31. The resistors R1to R7are coupled in series between a power voltage VDD3and the ground voltage. The 8 switches S10to S17are respectively coupled to a point where the ground voltage and the resistor R1meet, 6 points adjacent to where two of the resistors R1to R7meet, and a point where the power voltage VDD3and the resistor R7meet. The switch S20is coupled to a point where the switches S10and S11meet, and the switch S21is coupled to a point where the switches S12and S13meet. The switch S22is coupled to a point where the switches S14and S15meet, and the switch S23is coupled to a point where the switches S16and S17meet. In addition, the switch S30is coupled to a point where the switches S20and S21meet, and the switch S31is coupled to a point where the switches S22and S23meet. A voltage output from a point where the switches S30and S31meet is the precharge voltage Vpre.

Herein, the switch S30is turned on when the most significant bit (MSB) D0is ‘1’, and the switch S31is turned on when the MSB D0is ‘0’. The switches S20and S22are turned on when the second higher order bit D1is ‘1’, and the switches S21and S23are turned on when the second higher order bit D1is ‘0’. The switches S10, S12, S14, and S16are turned on when the third higher order bit D2is ‘1’, and the switches S11, S13, S15, and S17are turned on when the third higher order bit D0is ‘0’. Then, the switches which will be turned on among the plurality of switches S10to S17, S20to S23, S30, and S31are determined by the 3 high order bits D0, D1, and D2so that the precharge voltage Vpre is determined. For example, when the 3 high order bits D0, D1, and D2are ‘110’, the switches S30, S20, and S11are turned on so that the power voltage VDD3is divided by the resistors R2to R7and the resistor R1to output as the precharge voltage Vpre.

As described above, while the R, G, and B D/A converters are formed on D/A converting units340in the first to fourth exemplary embodiments, one D/A converter may be used to convert the R, G, and B gray scale data to the current. In this case, the multiplexing processor330sequentially transmits the R, G, and B data signals corresponding to the one pixel to the D/A converting unit340.

In addition, while one D/A converting unit340is formed on the data driver300in the first to fourth exemplary embodiments, a plurality of D/A converting units may be formed in the data driver300. That is, the plurality of data lines D1to Dmmay be divided into a plurality of groups, and the plurality of D/A converting units respectively corresponding to the plurality of groups may be formed.

FIG. 13shows a diagram of a configuration of a data driver according to a fifth exemplary embodiment of the present invention. InFIG. 13, a case in which 2 D/A converting units are formed on the data driver is shown.

As shown inFIG. 13, the data driver300′ according to the fifth exemplary embodiment has substantially the same structure as the first exemplary embodiment. However, the data driver300′ includes 2 D/A converting units340aand340b,2 multiplexing processors330aand330b, and 2 output stages360aand360bin contrast with the data driver300shown inFIG. 2.

In more detail, a shift-register (not shown) of the multiplexing processor330asequentially outputs 50 multiplexing signals MSW0to MSW49, and shifting signals SRL0to SRL49. A multiplexer (not shown) of the multiplexing processor330amultiplexes each of the 1stto 50thR, G, and B data signals DR0to DR49, DG0to DG49, and DB0to DB49output from the holding latch322in response to each of the multiplexing signals MSW0to MSW49, and sequentially transmits the R, G, and B data signals DR0to DR49, DG0to DG49, and DB0to DB49to the D/A converting unit340a. In like manner, a shift register (not shown) of the multiplexing processor330bsequentially outputs 50 multiplexing signals MSW50to MSW99, and shifting signals SRL50to SRL99. A multiplexer (not shown) of the multiplexing processor330bmultiplexes each of the 51stto 100thR, G, and B data signals DR50to DR99, DG50to DG99, and DB50to DB99output from the holding latch322in response to each of the multiplexing signals MSW50to MSW99, and sequentially transmits the R, G, and B data signals DR50to DR99, DG50to DG99, and DB50to DB99to the D/A converting unit340b.

The control signal generator350sequentially receives the shift signals SRL0to SRL49and SRL50to SRL99from the multiplexing processors330aand330b, generates sampling signals CHS0to CHS49to sequentially output them to the output stage360a, and generates sampling signals CHS50to CHS99to sequentially output them to the output stage360b. The output stage360asequentially samples the R, G, and B data currents R0to R49, G0to G49, and B0to B49in response to each of the sampling signals CHS0to CHS49, and the output stage360bsequentially samples the R, G, and B data currents R50to R99, G50to G99, and B50to B99in response to each of the sampling signals CHS50to CHS99.

According to the fifth exemplary embodiment, since the data signals corresponding to the two pixels are processed in parallel, the data transmitting period can be increased. As a result, the data current can be properly transmitted from the D/A converting units (e.g., the D/A converting units340aand340b) to the output stages (e.g., the output stages360aand360b). In addition, the precharge unit380a,380b, or380cdescribed in the second to fourth exemplary embodiments may be applicable to the fifth exemplary embodiment.

In the first to fifth exemplary embodiments, while the data driver for outputting the data current corresponding to the 300 data lines D1to D300is described, the data driver does not have to be limited to this number of data lines. In addition, the data driver may be manufactured as an integrated circuit (IC), and the plurality of ICs can be formed on the light emitting display. Furthermore, while one pixel is described to be formed by the R, G, and B sub-pixels, the one pixel may be formed by at least two sub-pixels, or the one pixel may be formed by one sub-pixel.

According to the exemplary embodiments of the present invention, the data signals may be converted to the data currents to be transmitted to the plurality of data lines, and the plurality of data lines may share one D/A converting unit so that a dimension of the D/A converting unit is minimized. In addition, the data currents output from the D/A converting unit may be properly transmitted to the output stage.

While the invention has been described in connection with certain exemplary embodiments, it is to be understood by those skilled in the art that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications included within the spirit and scope of the appended claims and equivalents thereof.