Semiconductor device and method for fabricating the same

A method for fabricating a semiconductor device is provided. The method includes forming a first memory cell and a second memory cell over a substrate, wherein each of the first and second memory cells comprises a bottom electrode, a resistance switching element over the bottom electrode, and a top electrode over the resistance switching element; depositing a first dielectric layer over the first and second memory cells, such that the first dielectric layer has a void between the first and second memory cells; depositing a second dielectric layer over the first dielectric layer; and forming a first conductive feature and a second conductive feature in the first and second dielectric layers and respectively connected with the top electrode of the first memory cell and the top electrode of the second memory cell.

BACKGROUND

Semiconductor memories are used in integrated circuits for electronic applications, including radios, televisions, cell phones, and personal computing devices, as examples. One type of semiconductor memory device involves spin electronics, which combines semiconductor technology and magnetic materials and devices. The spins of electrons, through their magnetic moments, rather than the charge of the electrons, are used to indicate a bit.

One such spin electronic device is magnetoresistive random access memory (MRAM) array, which includes conductive lines (word lines and bit lines) positioned in different directions, e.g., perpendicular to each other in different metal layers. The conductive lines sandwich a magnetic tunnel junction (MTJ), which functions as a magnetic memory cell.

DETAILED DESCRIPTION

According to some embodiments of this disclosure, a magnetoresistive random access memory (MRAM) device is formed. The MRAM device includes a magnetic tunnel junction (MTJ) stack. The resistance switching element includes a tunnel barrier layer formed between a ferromagnetic pinned layer and a ferromagnetic free layer. The tunnel barrier layer is thin enough (such as a few nanometers) to permit electrons to tunnel from one ferromagnetic layer to the other. A resistance of the resistance switching element is adjusted by changing a direction of a magnetic moment of the ferromagnetic free layer with respect to that of the ferromagnetic pinned layer. When the magnetic moment of the ferromagnetic free layer is parallel to that of the ferromagnetic pinned layer, the resistance of the resistance switching element is in a lower resistive state, corresponding to a digital signal “0”. When the magnetic moment of the ferromagnetic free layer is anti-parallel to that of the ferromagnetic pinned layer, the resistance of the resistance switching element is in a higher resistive state, corresponding to a digital signal “1”. The resistance switching element is coupled between top and bottom electrodes and an electric current flowing through the resistance switching element (tunneling through the tunnel barrier layer) from one electrode to the other is detected to determine the resistance and the digital signal state of the resistance switching element.

According to some embodiments of this disclosure, memory cells are formed within a chip region of a substrate. A plurality of semiconductor chip regions is marked on the substrate by scribe lines between the chip regions. The substrate will go through a variety of cleaning, layering, patterning, etching and doping steps to form the MRAM devices. The term “substrate” herein generally refers to a bulk substrate on which various layers and device elements are formed. In some embodiments, the bulk substrate includes silicon or a compound semiconductor, such as GaAs, InP, SiGe, or SiC. Examples of the layers include dielectric layers, doped layers, polysilicon layers or conductive layers. Examples of the device elements include transistors, resistors, and/or capacitors, which may be interconnected through an interconnect layer to additional integrated circuits.

FIG.1illustrates a wafer having a substrate110thereon. The substrate110has a logic region LR where logic circuits are to be formed and a memory region MR where memory cells are to be formed. The substrate110includes an interlayer dielectric (ILD) layer or inter-metal dielectric (IMD) layer114with a metallization pattern112over the logic region LR and the memory region MR. The ILD layer114may be silicon oxide, fluorinated silica glass (FSG), carbon doped silicon oxide, tetra-ethyl-ortho-silicate (TEOS) oxide, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), Black Diamond® (Applied Materials of Santa Clara, Calif.), amorphous fluorinated carbon, low-k dielectric material, the like or combinations thereof. The metallization pattern112may be aluminum, aluminum alloy, copper, copper alloy, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, cobalt, the like, and/or combinations thereof. Formation of the metallization pattern112and the ILD layer114may be a dual-damascene process and/or a single-damascene process. The substrate110may also include active and passive devices, for example, underlying the ILD layer114. These further components are omitted from the figures for clarity.

An etch stop layer120and a dielectric layer130are formed over the logic region LR and the memory region MR of the substrate110in a sequence. The etch stop layer120may have a high etch resistance to one or more subsequent etching processes. The etch stop layer120may be formed of dielectric material different from the underlying ILD layer114. For example, the ILD layer114may be a silicon oxide layer, and the etch stop layer120may be a silicon nitride layer.

The dielectric layer130in some embodiments is silicon carbide (SiC), silicon oxynitride (SiON), silicon nitride (SiN), silicon dioxide, TEOS, low-k dielectrics, black diamond, FSG, PSG, BPSG, the like, and/or combinations thereof. The dielectric layer130may be a single-layered structure or a multi-layered structure. The dielectric layer130may be formed by acceptable deposition techniques, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), the like, and/or a combination thereof.

Openings O1are formed in the etch stop layer120and the dielectric layer130in the memory region MR1, and exposes portions of the metallization pattern112. An exemplary formation method of the openings O1includes forming a patterned mask over the dielectric layer130, and then etching the dielectric layer130and the etch stop layer120through the patterned mask by one or more etching processes, such as dry etching, wet etching, or combinations thereof. After the formation of the openings O1, the patterned mask is removed from the dielectric layer130by suitable ashing process.

Bottom electrode vias (BEVA)140are then formed within the openings O1. In some embodiments, at least one of the BEVAs140is a multi-layered structure and includes, for example, a diffusion barrier layer and a filling metal filling a recess in the diffusion barrier layer. An exemplary formation method of the BEVAs140includes forming in sequence the diffusion barrier layer and the filling metal into the openings O1, and performing a planarization process, such as a chemical-mechanical polish (CMP) process, to remove excess materials of the filling metal and of the diffusion barrier layer outside the openings O1. The remaining diffusion barrier layer and the remaining filling metal in the openings O1can serve as the BEVAs140. In some embodiments, the BEVAs140are electrically connected to an underlying electrical component, such as a transistor, through the metallization pattern112.

In some embodiments, the diffusion barrier layer is a titanium nitride (TiN) layer or a tantalum nitride (TaN) layer, which can act as a suitable barrier to prevent metal diffusion. Formation of the diffusion barrier layer may be exemplarily performed using CVD, PVD, ALD, the like, and/or a combination thereof. In some embodiments, the filling metal is titanium (Ti), tantalum (Ta), platinum (Pt), ruthenium (Ru), tungsten (W), aluminum (Al), copper (Cu), the like, and/or combinations thereof. Formation of the filling metal may be exemplarily performed using CVD, PVD, ALD, the like, and/or a combination thereof.

Reference is made toFIG.2. A bottom electrode layer150is then blanketly formed over the BEVAs140and over the dielectric layer130, so that the bottom electrode layer150extends along top surfaces of the BEVAs140and of the dielectric layer130. The bottom electrode layer150can be a single-layered structure or a multi-layered structure. In some embodiments, the bottom electrode layer150is titanium (Ti), tantalum (Ta), platinum (Pt), ruthenium (Ru), tungsten (W), aluminum (Al), copper (Cu), TiN, TaN, the like, and/or a combination thereof. Formation of the bottom electrode layer150may be exemplarily performed using CVD, PVD, ALD, the like, and/or a combination thereof.

A resistance switching layer160is formed over the bottom electrode layer150. In some embodiments, the resistance switching layer160may be a magnetic tunnel junction (MTJ) structure. To be specific, the resistance switching layer160includes at least a first magnetic layer, a tunnel barrier layer and a second magnetic layer formed in sequence over the bottom electrode layer150. The magnetic moment of the second magnetic layer may be programmed causing the resistance of the resulting MTJ cell to be changed between a high resistance and a low resistance.

In some embodiments, the first magnetic layer includes an anti-ferromagnetic material (AFM) layer over the bottom electrode layer150and a ferromagnetic pinned layer over the AFM layer. In the anti-ferromagnetic material (AFM) layer, magnetic moments of atoms (or molecules) align in a regular pattern with magnetic moments of neighboring atoms (or molecules) in opposite directions. A net magnetic moment of the AFM layer is zero. In certain embodiments, the AFM layer includes platinum manganese (PtMn). In some embodiments, the AFM layer includes iridium manganese (IrMn), rhodium manganese (RhMn), iron manganese (FeMn), or OsMn. An exemplary formation method of the AFM layer includes sputtering, PVD, ALD or the like.

The ferromagnetic pinned layer in the first magnetic layer forms a permanent magnet and exhibits strong interactions with magnets. A direction of a magnetic moment of the ferromagnetic pinned layer can be pinned by an anti-ferromagnetic material (AFM) layer and is not changed during operation of a resulting resistance switching element fabricated from the resistance switching layer160. In certain embodiments, the ferromagnetic pinned layer includes cobalt-iron-boron (CoFeB). In some embodiments, the ferromagnetic pinned layer includes CoFeTa, NiFe, Co, CoFe, CoPt, or the alloy of Ni, Co and Fe. An exemplary formation method of the ferromagnetic pinned layer includes sputtering, PVD, ALD, thermal or e-beam evaporated deposition. In some embodiments, the ferromagnetic pinned layer includes a multilayer structure.

The tunnel barrier layer is formed over the first magnetic layer. The tunnel barrier layer can also be referred to as a tunneling layer, which is thin enough that electrons are able to tunnel through the tunnel barrier layer when a biasing voltage is applied to a resulting resistance switching element fabricated from the resistance switching layer160. In certain embodiments, the tunnel barrier layer includes magnesium oxide (MgO), aluminum oxide (Al2O3), aluminum nitride (AlN), aluminum oxynitride (AlON), hafnium oxide (HfO2) or zirconium oxide (ZrO2). An exemplary formation method of the tunnel barrier layer includes sputtering, PVD, ALD, e-beam or thermal evaporated deposition, or the like.

The second magnetic layer is formed over the tunnel barrier layer. The second magnetic layer is a ferromagnetic free layer in some embodiments. A direction of a magnetic moment of the second magnetic layer is not pinned because there is no anti-ferromagnetic material in the second magnetic layer. Therefore, the magnetic orientation of this layer is adjustable, thus the layer is referred to as a free layer. In some embodiments, the direction of the magnetic moment of the second magnetic layer is free to rotate parallel or anti-parallel to the pinned direction of the magnetic moment of the ferromagnetic pinned layer in the first magnetic layer. The second magnetic layer may include a ferromagnetic material similar to the material in the ferromagnetic pinned layer in the first magnetic layer. Since the second magnetic layer has no anti-ferromagnetic material while the first magnetic layer has an anti-ferromagnetic material therein, the first and second magnetic layers and have different materials. In certain embodiments, the second magnetic layer includes cobalt, nickel, iron or boron, compound or alloy thereof. An exemplary formation method of the second magnetic layer includes sputtering, PVD, ALD, e-beam or thermal evaporated deposition, or the like.

A top electrode layer170is formed over the resistance switching layer160. The top electrode layer170includes a conductive material. In some embodiments, the top electrode layer170is similar to the bottom electrode layer150in terms of composition. In some embodiments, the top electrode layer170comprises titanium (Ti), tantalum (Ta), platinum (Pt), ruthenium (Ru), tungsten (W), aluminum (Al), copper (Cu), the like or combinations thereof. An exemplary formation method of the top electrode layer170includes sputtering, PVD, ALD or the like.

Reference is made toFIG.3. The top electrode layer170, the resistance switching layer160, and the bottom electrode layer150(referring toFIG.2) are patterned into top electrodes172, resistance switching elements162, and bottom electrodes152in the memory region MR. The top electrodes172, the resistance switching elements162, and the bottom electrodes152in combination may be referred to as memory stacks MS. In the present embodiments, the patterning may include a directional physical dry etching process, such as IBE process. The IBE process may use an etchant gas such as an Ar series Kr, Ne, Ar, O, N, the like, or a combination thereof. The IBE process may be performed in a chamber with a rotatable stage or substrate table with more than one axis of rotation. This rotation allows a more uniform etch profile and allows control of the angle of incidence of the ion beam. The IBE process may have an end point detection system to allow the etching process to stop before etching through the underlying dielectric layer130.

In some embodiments, the physical dry etching process may etch the underlying dielectric layer130, thereby forming recesses130R in the dielectric layer130. In some embodiments, the recesses130R in the dielectric layer130are designed to be deep enough to reduce the amount of redeposition films on sidewalls of MTJ structure during the IBE process. For example, in some embodiments, a thickness of the dielectric layer130is in a range from about 40 nanometers to about 70 nanometers, and a depth of the recess130R may be in a range from about 20 nanometers to about 50 nanometers. If the thickness of the dielectric layer130is less than 40 nanometers, the IBE process performed to form the resistance switching elements162without the redeposition films may etch through the dielectric layer130, such that the recess130R may expose underlying etch stop layer120. If the thickness of the dielectric layer130is greater than 70 nanometers, due to the limited thickness of the ILD layer subsequently formed (e.g., the ILD layer210inFIG.10), a portion of the ILD layer subsequently formed above the top electrode172may be too thin, which may result in difficulty in the formation of the top electrode via (referring toFIG.13). The BEVA140may have a height in a range from about 40 nanometers to about 70 nanometers according to the thickness of the dielectric layer130. Through the IBE process, the memory stacks MS are formed with high aspect ratio, which in turn may induce gap fill issue in subsequent process. The IBE process may also lower a top surface130T of the dielectric layer130in the region LR.

Reference is then made toFIG.4. Spacers182are respectively formed around and enclosing the memory stacks MS. The spacer182in some embodiments may include SiN, but in other embodiments may include SiC, SiON, silicon oxycarbide (SiOC), the like, and/or combinations thereof. The formation of the spacers182may include depositing a spacer layer over the memory stacks MS and the dielectric layer130, and then patterning the spacer layer into the spacers182by suitable etching process. Deposition of the spacer layer may include CVD, PVD, ALD, the like, and/or combinations thereof. The etching process may be anisotropic dry etching process (e.g., plasma etching process), using gas etchants such as CH2F2, CF4, CHxFy, CHF3, CH4, N2, O2, Ar, He, or the like. The etching process removes horizontal portions of the spacer layer, and leaving vertical portions of the spacer layer on sidewalls of the memory stacks MS and the dielectric layer130. The remaining vertical portions of the spacer layer may be referred to as the spacer182hereinafter. The spacer182may include multiple layers in some embodiments. In some embodiments, the dielectric layer130and the top electrodes172may have a higher etch resistance to the etching process than that of the spacer182, such that the etching process to the spacer layer may stop at the top surfaces of the dielectric layer130and the top electrodes172. After the etching process, portions of the top electrodes172are exposed by the spacers182. In some embodiments, the etching process may further lower the top surface130T of the dielectric layer130and deepen the recess130R.

Reference is then made toFIG.5. A protective layer190is conformally deposited over the spacer182, the memory stacks MS, the dielectric layer130. The protective layer190may be formed of dielectric material different from the etch stop layer120, the dielectric layer130, and the spacers182. In some embodiments, the protective layer190may be a metal-containing compound layer. For example, the protective layer190is made from AlOx, AlN, AlNyOx, other suitable material, or the combination thereof. In some other embodiments, the protective layer190may be a metal oxide layer containing other metals. In some other embodiments, the protective layer190may be dielectric layer, such as silicon nitride layer. In some embodiments, the protective layer190can be a single layer or a multi-layered structure.

Reference is made toFIGS.6and7. A dielectric material200is deposited over the structure ofFIG.5. In the present embodiments, the dielectric material200is deposited with poor step coverage compared with the deposition process of an ILD layer subsequently formed above the top electrode172(e.g., the ILD layer210inFIG.10). For example, the deposition process of the dielectric material200may include PVD or CVD process, such as atmosphere pressure CVD (APCVD). In some embodiments where the dielectric material200is deposited by the CVD process, a deposition rate of the dielectric material200is greater than a deposition rate of the ILD layer subsequently formed above the top electrode172(e.g., the ILD layer210inFIG.10). The dielectric material200may include suitable dielectric materials, such as oxides. In some embodiments, the dielectric material200may include a material different from that of the ILD layer subsequently formed above the top electrode172(e.g., the ILD layer210inFIG.10). For example, the dielectric material200may include SiOx, SiNx, SiOXNyor the like. Alternatively, in some other embodiments, the dielectric material200may include a same material with that of the ILD layer210inFIG.10.

In the present embodiments, due to the fast depositing process, the dielectric material200is initially formed around the memory stacks MS, and then merged to have void200V between the memory stacks MS. For example, inFIG.6, at an initial stage, the depositing process may form a dielectric portion202around one of the memory stacks MS, a dielectric portion204around another of the memory stacks MS, and there is a space between the dielectric portions202and204. Due to the fast depositing process, the dielectric portions202and204may have a first sub-portion P1and a second sub-portion P2below the first sub-portion at sidewalls of the memory stacks MS, and the first sub-portion P1is thicker than the second sub-portion P2. The depositing process may also form a dielectric portion206over the protective layer190between the memory stacks MS and a dielectric portion208in logic region LR. Due to the poor coverage of the fast deposition process, a thickness of a portion of the dielectric material200between the dielectric portions202and206may be negligible, and a thickness of a portion of the dielectric material200between the dielectric portions204and206may be negligible. In other words, the dielectric portions202-206may be spaced apart from each other at the initial stage of the deposition process.

By continuing the depositing process, the dielectric portions202-208get thicker, and then merge with each other, as shown inFIG.7. For example, inFIG.7, the first sub-portion P1of the dielectric portion202is merged and connected with the first sub-portions P1of the dielectric portion204. The second sub-portions P2of the dielectric portions202and204may merge with the dielectric portion206. In some embodiments, the merging result in voids200V among the dielectric portions202-206in the memory region MR and next to the memory stacks MS. For example, the second sub-portions P2of the dielectric portions202and204are not connected with each other, and have the void200V therebetween. In other words, the dielectric portions202-206surrounds the void200V. In some embodiments of the present disclosure, by suitable controlling the fast deposition process, a top end of the void200V is formed at a position lower than a top surface of the top electrodes172, thereby avoiding being exposed in subsequent processes. In some embodiments a top end of the void200V is lower than a bottom surface of the top electrodes172. In some embodiments a bottom end of the void200V is higher than a bottom surface of the bottom electrodes152.

In some embodiments, through the merging, the dielectric material200has a continues top surface200T over the memory stacks MS in the memory region MR, in which the top surface200T has a higher planarity than that of the protective layer190. For example, a bottommost portion of the top surface200T between the memory stacks MS in the memory region MR may be at a position higher than that of a top surface of the top electrodes172. Through the configuration, the deposition of the dielectric material200may relax the high aspect ratio of the memory stack MS.

Reference is made toFIG.8. The dielectric material200is etched back, thereby lowering a top surface200T of the dielectric material200above the top electrode172. The etch back process may use gas etchant, such as CH2F2, CF4, CHxFy, CHF3, CH4, N2, O2, Ar, He, or the like. The etch back process may make the bottommost portion of the top surface200T of the dielectric material200between the memory stacks MS in the memory region MR be at a position lower than that of the top surface of the top electrodes172. After the etch back process, a top end of the void200V remains at a position lower than the top surface200T of the dielectric material200. The etch back process may also lower the top surface200T of the dielectric material200in the logic region LR. For example, after the etch back process, the top surface200T of the dielectric material200in the logic region LR is lower than a bottom surface of the bottom electrode152. Through the etch back process, a portion of the dielectric material200above the top electrode172is thinned, such that a portion of the ILD layer subsequently formed above the top electrode172may have suitable thickness, thereby benefiting the formation of the top electrode via (referring toFIG.13).

Reference is made toFIG.9. The portion208of the dielectric material200and a portion of the protective layer190out of the memory region MR (referring toFIG.8) may be removed by suitable etching process. The removal may include one or more etching processes. For example, a etch mask may be formed over the memory region MR and exposing the logic region LR, and a first etching process is performed to etch the portion208of the dielectric material200(referring toFIG.8) over the logic region LR through the etch mask. The first etching process may use an etchant gas such as CH2F2, CF4, CHxFy, CHF3, CH4, N2, O2, Ar, He, a combination thereof, or the like. The protective layer190may have a higher etch resistance to the first etching process than that of the dielectric material200, thereby protecting underlying layers from being etched. Subsequently, a second etching process is performed to remove the portion of the protective layer190in the logic region LR (referring toFIG.8) through the etch mask after the first etching process. The second etching process may use an etchant gas such as Cl2, BCl3, or the like, or a combination thereof. The dielectric layer130may have a higher etch resistance to the second etching process than that of the protective layer190, thereby protecting underlying layers from being etched. The second etching process may further remove a portion of the dielectric layer130in the logic region LR, thereby lowering the top surface130T of the dielectric layer130in the logic region LR. In some other embodiments, the second etching process may remove a portion of the dielectric layer130in the logic region LR, such that a top surface of the etch stop layer120in the logic region LR is exposed after the etching process.

Reference is made toFIG.10. An ILD layer210is formed with good step coverage over the structure ofFIG.9. In some embodiments, the ILD layer210includes silicon oxide, fluorinated silica glass (FSG), carbon doped silicon oxide, tetra-ethyl-ortho-silicate (TEOS) oxide, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), Black Diamond® (Applied Materials of Santa Clara, Calif.), amorphous fluorinated carbon, low-k dielectric material, the like or combinations thereof. As aforementioned, the ILD layer210may include a material the same as or different from that of the dielectric material200. In some embodiments, the ILD layer210may have an interface with the dielectric material200. In some embodiments, the ILD layer210may have a material the same as or different from that of the ILD layer114. In some embodiments, the ILD layer210may be formed using suitable CVD process, such as low-pressure CVD (LPCVD), plasma-enhanced CDV (PECVD), or high density plasma CVD (HDPCVD). The CVD process of the ILD layer210may have a lower deposition rate than that of the CVD process of the dielectric material200. In some other embodiments, the ILD layer210may be formed using, for example, spin-on-glass (SOG) or other suitable techniques. Through the process, the ILD layer210may have a top surface210T conformal to the top surface200T of the dielectric material200. In some embodiments, the ILD layer210may not be deposited into the voids200V in the dielectric material200, such that the voids200V remain being air voids.

Reference is made toFIG.11. After the formation of the ILD layer210, a planarization process may be performed to the top surface210T of the ILD layer210, such that the top surface210T of the ILD layer210becomes substantially flat. The planarization process may include a CMP process.

In absence of the dielectric material200, the ILD layer210deposited with fine coverage may have voids between adjacent memory stacks MS having high aspect ratio. The voids of the ILD layer210may have their top ends higher than a top surface of the top electrodes172. The planarization process performed to the ILD layer210may remove a portion of the ILD layer210and expose the voids. The exposed voids may be expanded in subsequent via and trench etching process, and induce undesired metal residues during subsequent formation process of metallization pattern, which may result in undesired contact short.

In some embodiments of the present disclosure, through the configuration of the dielectric material200with poor coverage, the voids200V between the memory stacks MS are formed to have their top ends lower than that of the top electrodes172of the memory stacks MS. Through the configuration, the voids200V would not be exposed during planarizing the ILD layer210, which in turn will eliminate or reduce metal residues formed during the formation of the metallization pattern.

Reference is made toFIG.12. Via openings210MV and210LV and trenches210MT and210LT are formed in the ILD layer210. Formation of the via openings210MV and210LV and trenches210MT and210LT may include a via etching process, a trench etching process, a liner removal process. The via etching process may be performed to etch vias openings210MV in the ILD layer210in the memory region MR and etch via openings210LV in the ILD layer210and dielectric layer130in the logic region LR. The trench etching process may be performed to etch trenches210MT in the ILD layer210in the memory region MR, etch trenches210LT in the ILD layer210in the logic region LR, and deepen the vias openings210MV and210LV after the via etching process. The via etching process and the trench etching process may include suitable anisotropic etching processes. In some embodiments where the ILD layer210is silicon oxide, the etchant used in the via etching process and the trench etching process can be dilute hydrofluoric acid (HF), HF vapor, CF4, C4F8, CHxFy, CxFy, SF6, or NF3, Ar, N2, O2, Ne, gas. In some embodiments, the liner removal process may be performed to slope the sidewalls of the via openings210MV and210LV and remove a portion of the etch stop layer120exposed by the via opening210LV. The liner removal process may include one or more isotropic etching processes, such as dry etching processes using CH2F2and Ar as etching gases.

In some embodiments, in the region MR, the protective layer190may have a higher etch resistance to the via and trench etching processes than that of the ILD layer210, such that the via and trench etching processes may stop at the protective layer190. After the via and trench etching processes, a cleaning process may be performed to remove residue polymers. The cleaning process may use suitable wet liquid, such as acid liquid. The cleaning process may consume and remove a portion of the protective layer190exposed by the via openings210MV or the trench210MT, thereby exposing the top electrodes172. In some embodiments, the top electrodes172may have a higher resistance to the cleaning process than that of the protective layer190, such that the cleaning process may stop at the top electrodes172and not damage the underlying layers.

In some embodiments, in the logic region LR, the etch stop layer120may have a higher etch resistance to the via and trench etching processes than that of the ILD layer210and the dielectric layer130, such that the via and trench etching processes may stop at the etch stop layer120. The liner removal process may remove a portion of the etch stop layer120exposed by the via opening210LV and expose the underlying metallization pattern112. In some embodiments, the metallization pattern112may have a higher etch resistance to the liner removal process than that of the etch stop layer120, such that the liner removal process may stop at the metallization pattern112and not damage the underlying layers.

In some other embodiments, the vias openings210MV may be omitted, and the via etching process may etch via openings210LV and not etch vias openings210MV in the ILD layer210, and the trench etching process may be performed to etch the trenches210MT until reaching the protective layer190. Through the cleaning process, portions of the protective layers190exposed by the trenches210MT may be removed, and the trenches210MT may expose the top electrodes172.

Reference is made toFIG.13. The via openings210MV and210LV and trenches210MT and210LT are filled with one or more conductive materials. The conductive materials may include metals, such as titanium (Ti), tantalum (Ta), platinum (Pt), ruthenium (Ru), tungsten (W), aluminum (Al), copper (Cu), the like, and/or combinations thereof. Formation of the conductive materials may be exemplarily performed using CVD, PVD, ALD, the like, and/or a combination thereof. After the via openings210MV and210LV and trenches210MT and210LT are filled with the conductive materials, a planarization is performed to remove an excess portion of the conductive materials outside the openings, thereby forming a metallization pattern in the ILD layer210. For example, in the memory region MR, the metallization pattern may include top electrode vias220MV formed in the via openings210MV and metal lines220ML in the trenches210MT. In some embodiments, a top electrode via220MV and a metal line220ML may be referred to as a memory conductive feature in some embodiments. In some embodiments, the top electrode via220MV may be omitted, and the top electrode172may be directly connected with the metal lines220ML. In the logic region LR, the metallization pattern may include the conductive via220LV in the via openings210LV and the metal lines220LL in the trenches210LT. In some embodiments, a conductive via220LV and a metal lines220LL may be referred to as a logic conductive feature in some embodiments.

Through the configuration, plural memory cells MC are formed. In some embodiments, each of the memory cells MC includes a resistance switching element162, a top electrode172over the resistance switching element162, and a bottom electrode152under the resistance switching element162. In the present embodiments, a BEVA140is formed under the bottom electrode152, and a top electrode via220MV is formed over the top electrode172.

FIG.14illustrates an integrated circuit including memory cells and logic devices. The integrated circuit includes a logic region LR and a memory region MR. Logic region LR may include circuitry, such as the exemplary transistor902, for processing information received from memory cells MC in the memory regions MR and for controlling reading and writing functions of memory cells MC.

As depicted, the integrated circuit is fabricated using five metallization layers, labeled as M1through M5, with five layers of metallization vias or interconnects, labeled as V1through V5. Other embodiments may contain more or fewer metallization layers and a corresponding more or fewer number of vias. Logic region LR includes a full metallization stack, including a portion of each of metallization layers M1-M5connected by interconnects V2-V5, with V1connecting the stack to a source/drain contact of logic transistor902. The memory region MR includes a full metallization stack connecting memory cells MC to transistors912in the memory region MR1, and a partial metallization stack connecting a source line SL to transistors912in the memory region MR1. Memory cells MC are depicted as being fabricated in between the top of the M3layer and the bottom the M4layer. Six ILD layers, identified as ILD0through ILD5are depicted inFIG.14as spanning the logic region LR and the memory region MR. The ILD layers may provide electrical insulation as well as structural support for the various features of the integrated circuit during many fabrication process steps.

Based on the above discussions, it can be seen that the present disclosure offers advantages. It is understood, however, that other embodiments may offer additional advantages, and not all advantages are necessarily disclosed herein, and that no particular advantage is required for all embodiments. One advantage is that a dielectric layer with poor coverage is formed prior to the formation of ILD layer, thereby relaxing the high aspect ratio of the memory stacks, which in turn may improve the subsequent formation of the ILD layer and metallization pattern. Another advantage is that voids between adjacent memory stacks are formed to have their top ends lower than that of the top electrodes of the memory stacks, such that the voids would not be exposed during planarizing the ILD layer, which in turn will eliminate or reduce metal residues formed during the formation of the metallization pattern, thereby preventing the undesired contact short. Still another advantage is that the deposition process for forming the dielectric material with low coverage (e.g., PVD or fast CVD) is low-cost and beneficial for high throughput.

In some embodiments, a method for fabricating a semiconductor device is provided. The method includes forming a first memory cell and a second memory cell over a substrate, wherein each of the first and second memory cells comprises a bottom electrode, a resistance switching element over the bottom electrode, and a top electrode over the resistance switching element; depositing a first dielectric layer over the first and second memory cells, such that the first dielectric layer has a void between the first and second memory cells; depositing a second dielectric layer over the first dielectric layer; and forming a first conductive feature and a second conductive feature in the first and second dielectric layers and respectively connected with the top electrode of the first memory cell and the top electrode of the second memory cell.

In some embodiments, a method for fabricating a semiconductor device is provided. The method includes forming a memory cell over a memory region of a substrate, wherein the memory cell comprises a bottom electrode, a resistance switching element over the bottom electrode, and a top electrode over the resistance switching element; depositing a protective layer over the memory region and a logic region of the substrate after forming the memory cell; depositing a first dielectric layer over the protective layer over the memory region and the logic region; etching back the first dielectric layer; and depositing a second dielectric layer over the first dielectric layer over the memory region and the logic region after etching back the first dielectric layer; and forming a first conductive feature in the first and second dielectric layers and connected with the top electrode of the memory cell and a second conductive feature in the second dielectric layer over the logic region.

In some embodiments, a semiconductor device includes a substrate, first and second memory cells, a first dielectric layer, a second dielectric layer, and first and second conductive features. The first and second memory cells are over the substrate. Each of the first and second memory cells comprises a bottom electrode, a resistance switching element over the bottom electrode, and a top electrode over the resistance switching element. The first dielectric layer surrounds the first and second memory cells, in which the first dielectric layer has a void between the first and second memory cells. The second dielectric layer is over the first dielectric layer. The first and second conductive features are in the first and second dielectric layers and respectively connected to the top electrode of the first memory cell and the top electrode of the second memory cell.