Memory controller, memory system, and control method of memory system

A memory controller includes a host interface circuit connectable to a host device by a bus conforming to a memory card system specification, a data buffer circuit including a buffer memory, a tag information generation circuit configured to generate tag information associated with a command received by the host interface circuit, and a first register in which the tag information generated by the tag information generation circuit is stored, and a second register into which the tag information stored in the first register is copied after the command is fetched from the host interface circuit for processing. When a read request is made from the host interface circuit to the data buffer circuit, the data buffer circuit returns read data stored in the buffer memory upon confirming that the tag information stored in the first register and the tag information stored in the second register match each other.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2020-087856, filed May 20, 2020, the entire contents of which are incorporated herein by reference.

FIELD

An embodiment described herein relates generally to a memory controller, a memory system, and a control method of a memory system.

BACKGROUND

A memory card in which a NAND flash memory is embedded, is known.

DETAILED DESCRIPTION

Embodiments provide a memory controller, a memory system, and a control method of a memory system that can improve reliability of an operation.

In general, according to one embodiment, a memory controller includes a host interface circuit configured to be connected to a host device by a bus conforming to a memory card system specification, a data buffer circuit including a buffer memory, a tag information generation circuit configured to generate tag information associated with a command received by the host interface circuit from the host device, and a first register in which the tag information generated by the tag information generation circuit is stored, and a second register into which the tag information stored in the first register is copied after the command is fetched from the host interface circuit for processing. When a read request is made from the host interface circuit to the data buffer circuit, the data buffer circuit returns read data stored in the buffer memory upon confirming that the first register and the tag information stored in the second register match each other.

Hereinafter, an embodiment of the present disclosure will be described with reference to the drawings. In the description of the drawings described below, the same or similar portions are denoted by the same or similar reference numerals. However, the drawings are schematic, and a size of each component in a block diagram may be different from an actual size.

A memory system according to the embodiment will be described with reference toFIG.1.FIG.1is a block diagram illustrating an example of a configuration of the memory system according to the embodiment.

As shown inFIG.1, a memory system1according to the embodiment includes a memory controller10and a nonvolatile memory3. The memory system1can be connected to a host4, andFIG.1shows a state where the memory system1is connected to the host4. The host4is an electronic device such as a personal computer or a portable terminal. The memory system1that can be connected to the host4is a storage device including a memory and a memory controller, for example, a memory card such as an SD® card.

The nonvolatile memory3according to the present embodiment is, for example, a NAND memory. However, the nonvolatile memory3is not limited to the NAND memory, and can be other types of nonvolatile memory, such as flash memory, FeRAM, and MRAM. In a case of a NAND memory, data is written and read in a unit called a page. For example, one page is about 2K bytes. Erasing of data is performed in a block unit with a plurality of pages, for example, 64 pages as one unit.

The memory controller10controls writing to the nonvolatile memory3in accordance with a write request from the host4. In addition, the memory controller10controls reading of data from the nonvolatile memory3in accordance with a read request from the host4. The memory controller10includes a host interface (I/F) circuit11, a processor12, a data buffer circuit13, and a memory interface (I/F) circuit14. The host I/F circuit11, the processor12, the data buffer circuit13, and the memory I/F circuit14are connected to each other via wiring. The host4and the host I/F circuit11are connected via an external bus. The external bus communicates according to a standard conforming to a memory card system specification. Examples of the memory card system specification include a serial peripheral interface (SPI) bus and an SD bus.

The host I/F circuit11outputs the write request, the read request, user data, and the like which are received from the host4to the bus. The host I/F circuit11transmits user data read from the nonvolatile memory3, a response from the processor12, and the like to the host4.

Examples of the processor12include a central processing unit (CPU) and a micro-processing unit (MPU).

The memory I/F circuit14is connected to the nonvolatile memory3via a memory control unit (not shown). The memory control unit performs an operation of writing data or the like to the non-volatile memory3and an operation of reading data or the like from the non-volatile memory3. The write operation and the read operation are performed based on an instruction from the processor12. Alternatively, the memory I/F circuit14may be connected to the nonvolatile memory directly.

The processor12controls each circuit in the memory controller10. When a command is input from the host4via the host I/F circuit11, the processor12performs control in accordance with the command. The processor12manages a storage area on the nonvolatile memory3(corresponding to physical address on the nonvolatile memory3) of the user data to be written to and read from the host4by using, for example, an address conversion table.

The data buffer circuit13includes a memory area for temporarily storing user data, write data, read data, and the like. For example, a semiconductor memory such as a DRAM is provided in the data buffer circuit13.

Next, a more detailed configuration of the memory controller10will be described.

As shown inFIG.1, the host I/F circuit11includes a host I/F111, a command and response processing circuit112, a read control circuit113, a read data processing circuit114, an interrupt signal generation circuit115, a processor I/F116, and a tag information generation circuit117. The tag information generation circuit117includes a first register118.

The host I/F circuit11communicates with the host4through the host I/F111. When a command is received via the host I/F111, the command and response processing circuit112returns a response corresponding to a control state in the memory controller10to the host via the host I/F111. The command and response processing circuit112is connected to the read control circuit113, the interrupt signal generation circuit115, the processor I/F116, and the tag information generation circuit117, and transmits a control signal necessary for an operation of each circuit.

When the host I/F circuit11receives a read command, the read control circuit113makes a read request to the data buffer circuit13.

The read data processing circuit114operates when the read data is to be output from the data buffer circuit13to the host4. When the read data is to be output from the data buffer circuit13to the host4, the read data is output via the read data processing circuit114and the host I/F111.

When the command and response processing circuit112receives a command via the host I/F111, the interrupt signal generation circuit115generates an interrupt signal and notifies the processor12of a command reception interrupt.

The processor I/F116is used as an I/F when the processor12fetches a detail of the command.

When the host I/F circuit11receives a command from the host4, the tag information generation circuit117generates tag information associated with the command and stores the tag information in the first register118. The command used to generate the tag information according to the embodiment may be limited to the read command, or may not be limited in particular to the read command.

The first register118stores the tag information generated by the tag information generation circuit117. Every time the command is received from the host4, the tag information generation circuit117generates the tag information and stores the tag information in the first register118. That is, the tag information associated with the latest command is updated and stored in the first register118.

The data buffer circuit13includes a processor I/F131, a buffer memory132, a buffer management circuit133, and a tag information comparison circuit135. The processor I/F131includes a second register134.

The processor I/F131is used as an interface when the data buffer circuit13communicates with the processor12. In the present embodiment, the second register134is provided inside the processor I/F131, but, in other embodiments, may be provided outside the processor I/F131.

The read data requested by the read command is read from the nonvolatile memory3and stored in the buffer memory132.

When an amount of the read data read into the buffer memory132from the nonvolatile memory3exceeds a predetermined amount, the buffer management circuit133notifies the read control circuit113that the read data stored in the buffer memory132is readable. For example, 512 bytes is selected as the predetermined amount. A read request from the read control circuit113and a response that read data stored in the buffer memory132is readable (e.g., buffer ready response) from the buffer management circuit133are carried out each time the predetermined amount of data has completed accumulating in the buffer memory132. Although 512 bytes is given as an example of the predetermined amount, the data amount of the predetermined amount is not limited to 512 bytes, and may be any data amount other than 512 bytes. On the contrary, until the amount of read data read into the buffer memory132exceeds the predetermined amount, the read control circuit113is notified that the read data stored in the buffer memory132is not readable.

The tag information stored in the first register118is copied and stored in the second register134. Copying of the tag information is performed by the processor12.

When preparation of the read data in the buffer memory132is complete, the tag information comparison circuit135checks whether the tag information stored in the first register118and the tag information stored in the second register134match each other. A comparison of the tag information is performed every time the read request is made from the read control circuit113.

In the embodiment, the tag information are pieces of information that can be stored in the first register118and the second register134, respectively, and that the tag information comparison circuit135can check if they match each other. For example, the tag information generation circuit117may be a counter, and the tag information may be a count value that is updated each time the counter receives a command. The tag information may be a read address of the read command received from the host4or time information generated by the tag information generation circuit117.

Next, an operation of the memory system1according to the embodiment will be described with reference toFIG.2.FIG.2is a diagram illustrating an operation sequence of the memory system according to the embodiment.

First, when the external host4transmits the read command to the memory system1, the host I/F circuit11receives the read command. Here, the read command is a command of the host4to the memory system1to read data at a particular address in the memory system1. In the following description, a case of reading data at an address “A0” and an address “A1” will be described as an example. The read commands for reading the data at the address “A0” and the address “A1” are referred to as a read command (A0) and a read command (A1), respectively. When receiving the read command (A0) via the host I/F111, the command and response processing circuit112returns a response corresponding to a control state in the memory controller10to the host4via the host I/F111. When the host I/F circuit11receives the read command (A0), the tag information generation circuit117generates new tag information (T1) and stores the tag information (T1) in the first register118. For example, when the count value (N) is used for the tag information (T1), the tag information generation circuit117generates a value of “N=1” and stores the value in the first register118. Similarly, when the read address is used for the tag information (T1), the tag information generation circuit117extracts a value of “A0” from the read command (A0) and stores the value in the first register118. When the time information is used for the tag information (T1), the tag information generation circuit117generates information of “t1” and stores the information in the first register118. In the following description, a case where the count value (N) is used for the tag information (T1) will be described.

Next, the read control circuit113starts a data read request to the buffer management circuit133. Based on a comparison result of the tag information comparison circuit135, the buffer management circuit133transfers the read data from the nonvolatile memory3stored in the buffer memory132to the read data processing circuit114, and sends a response signal (for the data read request) as to whether the read data stored in the buffer memory132is readable (buffer ready response) to the read control circuit113to perform data read control. Therefore, the read control circuit113is in a waiting state until an amount of the read data that is read corresponding to the read command (A0) exceeds the predetermined amount or a read stop or end command is received from the host4. Therefore, at this point, data transfer is not performed from the buffer memory132to the read data processing circuit114. In the following description, the read data corresponding to the read command (A0) is referred to as read data (A0). Similarly, the read data corresponding to the read command (A1) is referred to as read data (A1). A sequence example shown inFIG.2shows a case where the host I/F circuit11receives the read stop or end command or receives the next read command (A1) before the read data (A0) corresponding to the read command (A0) is taken into the buffer memory132.

The interrupt signal generation circuit115notifies the processor12of a read command (A0) reception interrupt. The processor12confirms the notification of the read command (A0) reception interrupt.

Next, the processor12fetches a detail of the read command (A0) from the processor I/F116of the host I/F circuit11. At this time, the tag information (T1) stored in the first register118is also read together. The tag information (T1) is fetched together as attribute information of the read command (A0).

Next, the processor12copies the tag information (T1) to the second register134in the processor I/F131of the data buffer circuit13. As a result, the count value “N=1” is stored in the second register134as the tag information (T1).

Next, the processor12instructs the memory I/F circuit14to read the read data (A0). The read data that is read is stored in the buffer memory132.

The tag information comparison circuit135compares the tag information stored in the first register118of the tag information generation circuit117with the tag information stored in the second register134in the data buffer circuit13in accordance with the read request from the read control circuit113. When the two pieces of tag information match each other and the amount of read data read into the buffer memory132exceeds the predetermined amount, the buffer management circuit133responds to the read control circuit113that the read data stored in the buffer memory132is readable (buffer ready response), and releases the waiting state of the read control circuit113. Here, in the sequence example inFIG.2, if the count value “N=1” is stored in both the first register and the second register, the pieces of tag information can be regarded as matching each other. However, since reading of the read data corresponding to the read command (A0) is not complete at this point, the read data is not output to the host4.

Next, in this state, for example, it is assumed that the host I/F circuit11receives the read stop or end command from the external host4. Such a situation occurs when processing of the memory system1is delayed with respect to the host4. Specifically, such a situation may occur when there is a large amount of read data to be read and the waiting state of the read control circuit113continues for a long time. Alternatively, such a situation may occur when it takes time to return to command processing in a low power consumption state for the purpose of reducing power consumption of the memory system1, or when the memory system1cannot keep up with a processing speed expected by the host4because the host4is relatively fast and the processor12is relatively slow.

When the host I/F circuit11receives the read stop or end command, the command and response processing circuit112returns a response to the host4via the host I/F111. Then, the interrupt signal generation circuit115notifies the processor12of the reception interrupt of the read stop or end command.

Next, the host I/F circuit11receives the next read command (A1) from the external host4. The read command (A1) is a command different from the previous read command (A0). When the read command (A1) is received via the host I/F111, the command and response processing circuit112returns a response to the host4via the host I/F111. The interrupt signal generation circuit115notifies the processor12of the reception interrupt of the read command (A1).

When the host I/F circuit11receives the read command (A1), the tag information generation circuit117operates to generate new tag information (T2) and stores the new tag information in the first register118. For example, when the count value (N) is used for the tag information, a value of “N=2” is generated and stored.

Next, the read control circuit113starts the read request to the buffer management circuit133. As described above, this sequence example is a case where the processing of the memory system1is delayed with respect to the host4.

The tag information comparison circuit135compares the tag information stored in the first register118with the tag information stored in the second register134in accordance with the read request from the read control circuit113. At this time, “N=2” updated as the count value of the new tag information corresponding to input of the new read command (A1) is stored in the first register118. On the other hand, since the count value “N=1” of the tag information corresponding to the previous read command (A0) is stored in the second register134in the data buffer circuit13, the tag information stored in the first register118and the tag information stored in the second register134do not match each other.

Therefore, the buffer management circuit133can control the read control circuit113so as not to transfer from the buffer memory132. As described above, by comparing the tag information stored in the first register118with the tag information stored in the second register134, it is possible to prevent old read data corresponding to the read command (A0) from being erroneously output to the host4, instead of the new read data corresponding to the read command (A1).

Next, the processor12confirms the notification of a read stop or end command reception interrupt. Then, the processor12instructs the memory I/F circuit14to stop reading the read data (A0). Further, the processor12instructs to discard the read data (A0) read and stored in the data buffer circuit13. Even when the notification of a read command (A1) reception interrupt is performed while such end process is being performed, the processor12continues the end process in priority.

After the end process is complete, the processor12confirms the notification of the read command (A1) reception interrupt. Then, the processor12fetches a detail of the read command (A1) from the processor I/F116of the host I/F circuit11. At this time, the tag information (T2) stored in the first register118is also read together.

Next, the processor12copies the tag information (T2) to the second register134in the processor I/F131of the data buffer circuit13. As a result, the count value “N=2” is stored in the second register134.

Next, the processor12instructs the memory I/F circuit14to read the read data (A1). The read data that is read is stored in the buffer memory132. Then, the buffer management circuit133compares the tag information stored in the first register118with the tag information stored in the second register134in accordance with the read request from the read control circuit113. At this time, the count value “N=2” is stored in both the first register118in the tag information generation circuit117and the second register134in the data buffer circuit13, and the tag information stored in the first register118and the tag information stored in the second register134match each other. Since the amount of read data corresponding to the read command (A1) read into the buffer memory132exceeds the predetermined amount, the read control circuit113is notified that the read data stored in the buffer memory132is readable.

When the read control circuit113is notified that the read data stored in the buffer memory132is readable, the read control circuit113outputs the read data (A1) from the buffer memory132to the external host4via the read data processing circuit114and the host I/F111. As described above, according to the present embodiment, it is possible to prevent the read data (A0) corresponding to the previous read command (A0) from being erroneously output in response to the input of the read command (A1), and to output the correct read data (A1) corresponding to the read command (A1).

Next, a memory system2according to a comparative example will be described with reference toFIG.3.FIG.3is a block diagram illustrating an example of a configuration of the memory system according to the comparative example.

In the memory system2, a part of the configuration of a memory controller20is different from that of the memory controller10of the memory system1. The memory controller20differs from the memory controller10in that the host I/F circuit21does not have a tag information generation circuit and a first register, or the data buffer23does not have a second register and a tag information comparison circuit. Other configurations are the same as those of the memory controller10.

Next, an operation of the memory system2according to the comparative example will be described with reference toFIG.4.FIG.4is a diagram illustrating an operation sequence of the memory system according to the comparative example. A description of the same operation as that of the memory system1according to the embodiment will be omitted.

The memory system2according to the comparative example does not have a circuit associated with tag information. Therefore, when an amount of the read data (A0) read into a buffer memory232exceeds a predetermined amount, a buffer management circuit233notifies a read control circuit213that the read data stored in the buffer memory132is readable.

The operation of the memory system2inFIG.4illustrates a case where a read stop or end command is received from the external host4after a start of reading the read data (A0) in the same situation and for the same reason as that of the memory system1inFIG.2.

The operation of the memory system2according to the comparative example is similar until the amount of read data (A0) read into the buffer memory232exceeds the predetermined amount, except that the operation related to the tag information is not performed. Therefore, a description will be made from a time point when the amount of read data (A0) read into the buffer memory232exceeds the predetermined amount.

As described above, when the amount of read data (A0) read into the buffer memory232exceeds the predetermined amount, the buffer management circuit233notifies the read control circuit213that the read data stored in the buffer memory132is readable. When the read control circuit213is notified that the read data stored in the buffer memory132is readable, the read control circuit213outputs the read data (A0) from the buffer memory232to the external host4via a read data processing circuit214and a host I/F211. However, a read command at this time is the read command (A1). Therefore, according to the comparative example, the erroneous read data (A0) is output in response to the read command (A1).

As described above, in the memory system2according to the comparative example, when processing of the memory system2is delayed with respect to the host4, erroneous read data may be output in response to the read command. On the other hand, in the memory system1according to the present embodiment, the tag information stored in the first register118and the tag information stored in the second register134are compared before the amount of read data (A1) read into the buffer memory132exceeds the predetermined amount and the read control circuit113is notified that the read data stored in the buffer memory132is readable. By comparing the tag information, it is possible to check whether the read data read into the buffer memory132and the data requested by the read command match each other. Therefore, as shown inFIG.2, even when the processing of the memory system1is delayed with respect to the host4, it is possible to prevent a malfunction that a previous read data is erroneously output in response to a new read command, and then to output correct read data in response to the new read command. As a result, reliability of the operation of the memory system can be improved.