SEMICONDUCTOR DEVICE

A semiconductor device includes first and second cell arrays. The first cell array includes a first gate electrode that extends in a vertical direction, a first channel pattern on a side surface of the first gate electrode, and a first bit line electrically connected to the first channel pattern. The second cell array includes a second gate electrode that extends in the vertical direction, a second channel pattern on a side surface of the second gate electrode, and a second bit line electrically connected to the second channel pattern. A first bit line pad is electrically connected to the first bit line and a second bit line pad is electrically connected to the second bit line. The first bit line pad is spaced apart from the second bit line pad with the first and second cell arrays therebetween.

CROSS-REFERENCE TO RELATED APPLICATIONS

This U.S. non-provisional patent application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2022-0104011, filed on Aug. 19, 2022, in the Korean Intellectual Property Office, the entire contents of which are hereby incorporated by reference.

BACKGROUND OF THE INVENTION

The inventive concept relates to a semiconductor device and a method for manufacturing the same, and more particularly, relates to a semiconductor memory device including a ferroelectric field effect transistor and a method for manufacturing the same.

Semiconductor memory devices may be classified into volatile memory devices and nonvolatile memory devices. The volatile memory devices may lose their stored data when their power supplies are interrupted. For example, the volatile memory devices may include at least one of dynamic random access memory (DRAM) devices and static random access memory (SRAM) devices. The nonvolatile memory devices may retain their stored data even when their power supplies are interrupted. For example, the non-volatile memory devices may include at least one of programmable ROM (PROM), erasable PROM (EPROM), electrically EPROM (EEPROM), and/or a flash memory device. Next-generation semiconductor memory devices such as magnetic random access memory (MRAM) devices and/or phase-change random access memory (PRAM) devices have been developed to provide high-performance and/or low power consumption semiconductor memory devices. In addition, with high integration of the semiconductor devices, various studies are conducted to overcome the limitations of a manufacturing process of the semiconductor device.

SUMMARY

An object of the inventive concept is to provide a semiconductor device that is easily highly integrated and a method of manufacturing the same.

An object of the inventive concept is to provide a semiconductor device having excellent reliability and a method of manufacturing the same.

A semiconductor device according to some embodiments of the inventive concept may include a first cell array and a second cell array on a substrate and adjacent to each other in a first direction parallel to an upper surface of the substrate. The first cell array may include a first gate electrode that extends in a second direction perpendicular to the upper surface of the substrate, first channel patterns on a side surface of the first gate electrode and spaced apart from each other in the second direction, and a first bit line electrically connected to a corresponding first channel pattern among the first channel patterns. The second cell array may include a second gate electrode that extends in the second direction, second channel patterns on a side surface of the second gate electrode and spaced apart from each other in the second direction, and a second bit line electrically connected to a corresponding second channel pattern among the second channel patterns. The semiconductor device may further include a first bit line pad electrically connected to the first bit line and a second bit line pad electrically connected to the second bit line. The first bit line pad may be spaced apart from the second bit line pad in a third direction which is parallel to the upper surface of the substrate and intersects the first direction, with the first and second cell arrays therebetween.

A semiconductor device according to some embodiments of the inventive concept may include a first cell array on a substrate. The first cell array may include a first bit line and a first source line spaced apart from each other in a first direction parallel to an upper surface of the substrate, a first gate electrode disposed between the first bit line and the first source line and that extends in a second direction perpendicular to the upper surface of the substrate, and first channel patterns on a side surface of the first gate electrode and spaced apart from each other in the second direction. The semiconductor device may further include a first bit line pad electrically connected to the first bit line and a first source line pad electrically connected to the first source line. The first bit line and the first source line may extend in a third direction parallel to the upper surface of the substrate and intersecting the first direction. The first bit line pad may be spaced apart from the first source line pad in the third direction with the first cell array therebetween.

A semiconductor device according to some embodiments of the inventive concept may include a first cell array and a second cell array on a substrate and adjacent to each other in a first direction parallel to an upper surface of the substrate. The first cell array may include a first gate electrode that extends in a second direction perpendicular to the upper surface of the substrate, first channel patterns on a side surface of the first gate electrode and spaced apart from each other in the second direction, and first conductive lines respectively electrically connected to the first channel patterns and spaced apart from each other in the second direction. The second cell array may include a second gate electrode that extends in the second direction, second channel patterns on a side surface of the second gate electrode and spaced apart from each other in the second direction, and second conductive lines respectively electrically connected to the second channel patterns and spaced apart from each other in the second direction. The semiconductor device may further include first conductive line pads respectively electrically connected to the first conductive lines and second conductive line pads respectively electrically connected to the second conductive lines. The first conductive line pads may be spaced apart from the second conductive line pads in a third direction which is parallel to the upper surface of the substrate and intersects the first direction, with the first and second cell arrays therebetween.

DETAILED DESCRIPTION

Hereinafter, the inventive concept will be described in detail by describing embodiments of the inventive concept with reference to the accompanying drawings.

FIG.1is a schematic perspective view of a semiconductor device according to some embodiments of the inventive concept.FIG.2is a plan view of a semiconductor device according to some embodiments of the inventive concept.FIG.3Ais a cross-sectional view taken along line A-A′ ofFIG.2, andFIG.3Bis a cross-sectional view taken along line B-B′ ofFIG.2.

Referring toFIGS.1,2,3A, and3B, a lower insulating layer102and an etch stop layer104may be sequentially disposed on a substrate100. The lower insulating layer102may be disposed between the substrate100and the etch stop layer104. The substrate100may include a semiconductor substrate (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, or a silicon-germanium (Si—Ge) substrate). The lower insulating layer102may include, for example, silicon oxide, silicon nitride, and/or silicon oxynitride, and the etch stop layer104may include a metal oxide (e.g., aluminum oxide).

A first cell array CAR1and a second cell array CAR2may be disposed on the etch stop layer104and may neighbor or be adjacent to each other in a first direction D1parallel to an upper surface100U of the substrate100.

The first cell array CAR1may include first conductive lines BL1and SL1and first gate electrodes GE1. The first conductive lines BL1and SL1may include first bit lines BL1spaced apart from each other in a second direction D2perpendicular to the upper surface100U of the substrate100, and first source lines SL1spaced apart from the first bit lines BL1in the first direction D1and spaced apart from each other in the second direction D2. The first gate electrodes GE1may be disposed between the first bit lines BL1and the first source lines SL1, and may extend in the second direction D2. The first bit lines BL1and the first source lines SL1may extend in a third direction D3parallel to the upper surface100U of the substrate100, and the third direction D3may intersect the first direction D1. The first bit lines BL1and the first source lines SL1may extend parallel to each other in the third direction D3. The first gate electrodes GE1may cross the first bit lines BL1and the first source lines SL1. The first gate electrodes GE1may be spaced apart from each other in the third direction D3between the first bit lines BL1and the first source lines SL1, and may extend in the second direction D2.

The first cell array CAR1may further include a plurality of first channel patterns CH1surrounding a side surface GE1_S of each of the first gate electrodes GE1. The plurality of first channel patterns CH1may surround the side surface GE1_S of each of the first gate electrodes GE1and may be spaced apart from each other in the second direction D2. The plurality of first channel patterns CH1may be disposed between the first bit lines BL1and the first source lines SL1. The first bit lines BL1may be connected to the plurality of first channel patterns CH1, respectively, and the first source lines SL1may be connected to the plurality of first channel patterns CH1, respectively. Each of the plurality of first channel patterns CH1may be connected to a corresponding first bit line BL1among the first bit lines BL1, and a corresponding first source line SL1among the first source lines SL1. Each of the plurality of first channel patterns CH1may be disposed between the corresponding first bit line BL1and the corresponding first source line SL1. In a cross-sectional view, the corresponding first bit line BL1, each of the plurality of first channel patterns CH1, and the corresponding first source line SL1may be horizontally (e.g., in the first direction D1) overlap each other. Each of the first bit lines BL1may extend in the third direction D3, and may be connected to first channel patterns CH1spaced apart from each other in the third direction D3. Each of the first source lines SL1may extend in the third direction D3and may be connected to the first channel patterns CH1spaced apart from each other in the third direction D3.

The first cell array CAR1may further include a first ferroelectric pattern FP1between each of the plurality of first channel patterns CH1and the corresponding first gate electrode GE1, a first metal pattern MP1between each of the plurality of first channel patterns CH1and the first ferroelectric pattern FP1, and a first insulating pattern IN1between each of the plurality of first channel patterns CH1and the first metal pattern MP1. The first ferroelectric pattern FP1may surround the side surface GE1_S of the corresponding first gate electrode GE1. The first metal pattern MP1may surround the side surface GE1_S of the corresponding first gate electrode GE1and may be spaced apart from the side surface GE1_S of the corresponding first gate electrode GE1with the first ferroelectric pattern FP1interposed therebetween. The first insulating pattern IN1may surround the side surface GE1_S of the corresponding first gate electrode GE1and may be spaced apart from the side surface GE1_S of the corresponding first gate electrode GE1with the first ferroelectric pattern FP1and the first metal pattern MP1interposed therebetween.

The first cell array CAR1may further include first impurity patterns OP1between the first bit lines BL1and the plurality of first channel patterns CH1, and second impurity patterns OP2between the first source lines SL1and the plurality of first channel patterns CH1. The first impurity patterns OP1may be spaced apart from each other in the second direction D2and may be interposed between the first bit lines BL1and the plurality of first channel patterns CH1, respectively. The second impurity patterns OP2may be spaced apart from each other in the second direction D2and may be interposed between the first source lines SL1and the plurality of first channel patterns CH1, respectively. The second impurity patterns OP2may be spaced apart from the first impurity patterns OP1in the first direction D1with the plurality of first channel patterns CH1, the first insulating pattern IN1, the first metal pattern MP1, the first ferroelectric pattern FP1, and the corresponding first gate electrode GE1interposed therebetween. The first bit lines BL1may be electrically connected to the plurality of first channel patterns CH1through the first impurity patterns OP1, respectively, and the first source lines SL1may be electrically connected to the plurality of first channel patterns CH1through the second impurity patterns OP2, respectively. The corresponding first gate electrode GE1, each of the plurality of first channel patterns CH1surrounding the corresponding side surface GE1_S of the first gate electrode GE1, the first ferroelectric pattern FP1interposed between each of the plurality of first channel patterns CH1and the corresponding first gate electrode GE1, the first metal pattern MP1, the first insulating pattern IN1, and a corresponding first impurity pattern OP1and a corresponding second impurity pattern OP2disposed on both sides of each of the plurality of first channel patterns CH1may be a ferroelectric field effect transistor.

First conductive line pads BLP1and SLP1may be disposed on one side of the first cell array CAR1. The first conductive line pads BLP1and SLP1may include first bit line pads BLP1and first source line pads SLP1.

The first bit line pads BLP1may be disposed on the one side of the first cell array CAR1and may be respectively connected to the first bit lines BL1. The first bit lines BL1may extend longer in the third direction D3as the first bit lines BL1are closer to the substrate100, and the first bit line pads BLP1may be connected to ends of the first bit line BL1, respectively. Each of the first bit line pads BLP1and each of the first bit lines BL1may be connected to each other to form an integral body. The first bit line pads BLP1may be stacked in the second direction D2on the one side of the first cell array CAR1to form a stepped structure. A width BLP1_W of each of the first bit line pads BLP1in the first direction D1may be greater than a width BL1_W of each of the first bit lines BL1in the first direction D1.

The first source line pads SLP1may be disposed on the one side of the first cell array CAR1and may be respectively connected to the first source lines SL1. The first source lines SL1may extend longer in the third direction D3as the source lines SL1are closer to the substrate100, and the first source line pads SLP1may be connected to ends of the first source lines SL1, respectively. Each of the first source line pads SLP1and each of the first source lines SL1may be connected to each other to form an integral body. The first source line pads SLP1may be stacked in the second direction D2on the one side of the first cell array CAR1to form a stepped structure. A width SLP1_W of each of the first source line pads SLP1in the first direction D1may be greater than a width SL1_W of each of the first source lines SL1in the first direction D1.

The first bit line pads BLP1and the first source line pads SLP1may be disposed on the same side of the first cell array CAR1and be spaced apart from each other in the first direction D1. The first source line pads SLP1may neighbor or be adjacent to the first bit line pads BLP1in the first direction D1. First conductive contacts MC1may be respectively disposed on the first bit line pads BLP1and the first source line pads SLP1, and may be electrically connected to the first bit line pads BLP1and the first source line pads SLP1, respectively.

The second cell array CAR2may include second conductive lines BL2and SL2and second gate electrodes GE2. The second conductive lines BL2and SL2may include second bit lines BL2spaced apart from each other in the second direction D2, and second source lines SL2spaced apart from the second bit lines BL2in the first direction D1and spaced apart from each other in the second direction D2. The second gate electrodes GE2may be disposed between the second bit lines BL2and the second source lines SL2and may extend in the second direction D2. The second bit lines BL2may be spaced apart from the first bit lines BL1and the first source lines SL1in the first direction D1. The second bit lines BL2and the second source lines SL2may extend parallel to each other in the third direction D3. The second gate electrodes GE2may cross the second bit lines BL2and the second source lines SL2. The second gate electrodes GE2may be spaced apart from each other in the third direction D3between the second bit lines BL2and the second source lines SL2and may extend in the second direction D2.

The second cell array CAR2may further include a plurality of second channel patterns CH2surrounding a side surface GE2_S of each of the second gate electrodes GE2. The plurality of second channel patterns CH2may surround the side surface GE2_S of each of the second gate electrodes GE2and may be spaced apart from each other in the second direction D2. The plurality of second channel patterns CH2may be disposed between the second bit lines BL2and the second source lines SL2. The second bit lines BL2may be connected to the plurality of second channel patterns CH2, respectively, and the second source lines SL2may be respectively connected to the plurality of second channel patterns CH2. Each of the plurality of second channel patterns CH2may be connected to a corresponding second bit line BL2among the second bit lines BL2and a corresponding second source line SL2among the second source lines SL2. Each of the plurality of second channel patterns CH2may be disposed between the corresponding second bit line BL2and the corresponding second source line SL2. In a cross-sectional view, the corresponding second bit line BL2, each of the plurality of second channel patterns CH2, and the corresponding second source line SL2may horizontally (e.g., in the first direction D1) overlap each other. Each of the second bit lines BL2may extend in the third direction D3, and may be connected to second channel patterns CH2spaced apart from each other in the third direction D3. Each of the second source lines SL2may extend in the third direction D3and may be connected to the second channel patterns CH2spaced apart from each other in the third direction D3.

The second cell array CAR2may further include a second ferroelectric pattern FP2between each of the plurality of second channel patterns CH2and the corresponding second gate electrode GE2, a second metal pattern MP2between each of the plurality of second channel patterns CH2and the second ferroelectric pattern FP2, and a second insulating pattern IN2between each of the plurality of second channel patterns CH2and the second metal pattern MP2. The second ferroelectric pattern FP2may surround the side surface GE2_S of the corresponding second gate electrode GE2. The second metal pattern MP2may surround the side surface GE2_S of the corresponding second gate electrode GE2and the corresponding second gate electrode and may be spaced apart from the side surface GE2_S of the corresponding second gate electrode GE2with the second ferroelectric pattern FP2interposed therebetween. The second insulating pattern IN2may surround the side surface GE2_S of the corresponding second gate electrode GE2, and may be spaced apart from the side surface GE2_S of the corresponding second gate electrode GE2with the second ferroelectric pattern FP2and the second metal pattern MP2interposed therebetween.

The second cell array CAR2may further include third impurity patterns OP3between the second bit lines BL2and the plurality of second channel patterns CH2, and fourth impurity patterns OP4between the second source lines SL2and the plurality of second channel patterns CH2. The third impurity patterns OP3may be spaced apart from each other in the second direction D2, and may be interposed between the second bit lines BL2and the plurality of second channel patterns CH2, respectively. The fourth impurity patterns OP4may be spaced apart from each other in the second direction D2, and may be interposed between the second source lines SL2and the plurality of second channel patterns CH2, respectively. The fourth impurity patterns OP4may be spaced apart from the third impurity patterns OP3with the plurality of second channel patterns CH2, the second insulating pattern IN2, the second metal pattern MP2, the second ferroelectric pattern FP2, and the corresponding second gate electrode GE2in the first direction D1therebetween. The second bit lines BL2may be electrically connected to the plurality of second channel patterns CH2through the third impurity patterns OP3, respectively, and the second source lines SL2may be electrically connected to the plurality of second channel patterns CH2through the fourth impurity patterns OP4, respectively. The corresponding second gate electrode GE2, each of the plurality of second channel patterns CH2surrounding the side surface GE2_S of the corresponding second gate electrode GE2, the second ferroelectric pattern FP2interposed between each of the plurality of second channel patterns CH2and the corresponding second gate electrode GE2, the second metal pattern MP2and the second insulating pattern IN2, and a corresponding third impurity pattern OP3and a corresponding fourth impurity pattern OP4disposed on both sides of each of the plurality of second channel patterns CH2may be a ferroelectric field effect transistor.

Second conductive line pads BLP2and SLP2may be disposed on one side of the second cell array CAR2. The second conductive line pads BLP2and SLP2may include second bit line pads BLP2and second source line pads SLP2.

The second bit line pads BLP2may be disposed on the one side of the second cell array CAR2and may be respectively connected to the second bit lines BL2. The second bit lines BL2may extend longer in a direction opposite to the third direction D3as the second bit lines BL2are closer to the substrate100, and the second bit line pads BLP2may be connected to ends of the second bit lines BL2, respectively. Each of the second bit line pads BLP2and each of the second bit lines BL2may be connected to each other to form an integral body. The second bit line pads BLP2may be stacked in the second direction D2on the one side of the second cell array CAR2to form a stepped structure. A width BLP2_W of each of the second bit line pads BLP2in the first direction D1may be greater than a width BL2_W of each of the second bit lines BL2in the first direction D1.

The second source line pads SLP2may be disposed on the one side of the second cell array CAR2and may be respectively connected to the second source lines SL2. The second source lines SL2may extend longer in a direction opposite to the third direction D3as the second source lines SL2closer to the substrate100, and the second source line pads SLP2may be connected to ends of the second source lines SL2, respectively. Each of the second source line pads SLP2and each of the second source lines SL2may be connected to each other to form an integral body. The second source line pads SLP2may be stacked in the second direction D2on the one side of the second cell array CAR2to form a stepped structure. A width SLP2_W of each of the second source line pads SLP2in the first direction D1may be greater than a width SLP2_W of each of the second source lines SL2in the first direction D1.

The second bit line pads BLP2and the second source line pads SLP2may be disposed on the same side of the second cell array CAR2and be spaced apart from each other in the first direction D1. The second source line pads SLP2may neighbor or be adjacent to the second bit line pads BLP2in the first direction D1. The first bit line pads BLP1and the first source line pads SLP1may be spaced apart from the second bit line pads BLP2and the second source line pads SLP2in the third direction D3with the first cell array CAR1and the second cell array CAR2interposed therebetween. Second conductive contacts MC2may be disposed on the second bit line pads BLP2and the second source line pads SLP2, respectively, and each of the second bit line pads BLP2and the second source line pads SLP2may be electrically connected to each other.

The first bit lines BL1, the first bit line pads BLP1, the first source lines SL1, the first source line pads SLP1, and the second bit lines BL2, the second bit line pads BLP2, the second source lines SL2, and the second source line pads SLP2may include a conductive material, and for example, may include doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or a combination thereof. The first bit lines BL1, the first bit line pads BLP1, the first source lines SL1, the first source line pads SLP1, and the second bit lines BL2, the second bit line pads BLP2, the second source lines SL2, and the second source line pads SLP2may be formed of, for example, doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, or a combination thereof. However, the inventive concept is not limited thereto. The first bit lines BL1, the first bit line pads BLP1, the first source lines SL1, the first source line pads SLP1, and the second bit lines BL2, the second bit line pads BLP2, the second source lines SL2, and the second source line pads SLP2may include a two-dimensional semiconductor material, and for example, the two-dimensional semiconductor material may include graphene, carbon nanotubes, or a combination thereof.

The first and second ferroelectric patterns FP1and FP2may include hafnium (Hf) oxide having ferroelectric properties. The first and second ferroelectric patterns FP1and FP2may further include a dopant, and the dopant may be at least one of Zr, Si, Al, Y, Gd, La, Sc, and/or Sr. The first and second ferroelectric patterns FP1and FP2may include, for example, HfO2, HfZnO, HfSiO, HfSiON, HfTaO, HfSiO, HfZrO, or a combination thereof. The first and second ferroelectric patterns FP1and FP2may have an orthorhombic phase. The first and second metal patterns MP1and MP2may include a metal (e.g., Pt, etc.) and/or a metal oxide (e.g., RuO2, IrO2, LaSrCoO3, etc.). The first and second metal patterns MP1and MP2may be used to easily maintain the polarization of the first and second ferroelectric patterns FP1and FP2. In some embodiments, the first and second metal patterns MP1and MP2may be omitted. The first and second insulating patterns IN1and IN2may include a silicon oxide layer, a silicon oxynitride layer, a high-k layer having a higher dielectric constant than a dielectric constant of the silicon oxide layer, or a combination thereof. The high-k layer may include a metal oxide or a metal oxynitride.

The first impurity patterns OP1and the second impurity patterns OP2may include impurities having the same conductivity type. The first impurity patterns OP1and the second impurity patterns OP2may include, for example, an N-type impurity or a P-type impurity. The third impurity patterns OP3and the fourth impurity patterns OP4may include impurities having the same conductivity type. The third impurity patterns OP3and the fourth impurity patterns OP4may include, for example, an N-type impurity or a P-type impurity.

The first and second conductive contacts MC1and MC2may include a conductive material, and for example, may include doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or a combination thereof.

Interlayer insulating layers106may be interposed between the plurality of first channel patterns CH1of the first cell array CAR1. The interlayer insulating layers106and the plurality of first channel patterns CH1may be alternately stacked in the second direction D2. The plurality of first channel patterns CH1may be electrically separated (or insulated) from each other by the interlayer insulating layers106. The interlayer insulating layers106may surround the side surface GE1_S of the corresponding first gate electrode GE1. The interlayer insulating layers106may extend between the first impurity patterns OP1and between the first bit lines BL1, and may extend between the second impurity patterns OP2and between the first source lines SL1. The interlayer insulating layers106may extend between first insulating patterns IN1adjacent to each other in the second direction D2and between first metal patterns MP1adjacent to each other in the second direction D2. That is, the first insulating pattern IN1and the first metal pattern MP1may be interposed between interlayer insulating layers106adjacent to each other in the second direction D2among the interlayer insulating layers106. The first ferroelectric pattern FP1may extend between each of the interlayer insulating layers106and the corresponding first gate electrode GE1. The interlayer insulating layers106may be in contact with side surfaces of the first ferroelectric pattern FP1.

The interlayer insulating layers106may be interposed between the plurality of second channel patterns CH2of the second cell array CAR2. The interlayer insulating layers106and the plurality of second channel patterns CH2may be alternately stacked in the second direction D2. The plurality of second channel patterns CH2may be electrically separated (or insulated) from each other by the interlayer insulating layers106. The interlayer insulating layers106may surround the side surface GE2_S of the corresponding second gate electrode GE2. The interlayer insulating layers106may extend between the third impurity patterns OP3and between the second bit lines BL2, and may extend between the fourth impurity patterns OP4and between the second source lines SL2. The interlayer insulating layers106may extend between second insulating patterns IN2adjacent to each other in the second direction D2, and second metal patterns MP2adjacent to each other in the second direction D2. That is, the second insulating pattern IN2and the second metal pattern MP2may be interposed between interlayer insulating layers106adjacent to each other in the second direction D2among the interlayer insulating layers106. The second ferroelectric pattern FP2may extend between each of the interlayer insulating layers106and the corresponding second gate electrode GE2. The interlayer insulating layers106may be in contact with side surfaces of the second ferroelectric pattern FP2.

The interlayer insulating layers106may extend in the third direction D3and may be interposed between the first bit line pads BLP1and between the first source line pads SLP1. The interlayer insulating layers106may cover or overlap the first bit line pads BLP1and the first source line pads SLP1. Each of the first conductive contacts MC1may pass through a corresponding interlayer insulating layer106of the interlayer insulating layer106, and may be connected to a corresponding one of the first bit line pads BLP1and the first source line pads SLP1. The interlayer insulating layers106may extend in a direction opposite to the third direction D3and may be interposed between the second bit line pads BLP2and the second source line pads SLP2. The interlayer insulating layers106may cover or overlap the second bit line pads BLP2and the second source line pads SLP2. Each of the second conductive contacts MC2may pass through a corresponding interlayer insulating layer106of the interlayer insulating layer106and may be connected to a corresponding one of the second bit line pads BLP2and the second source line pads SLP2. The interlayer insulating layers106may include, for example, silicon oxide.

Sidewall insulating patterns130may be disposed on the etch stop layer104and on both sides of each of the first cell array CAR1and the second cell array CAR2. The sidewall insulating patterns130may be spaced apart from each other in the first direction D1with each of the first cell array CAR1and the second cell array CAR2interposed therebetween. The sidewall insulating patterns130may extend in the second direction D2and the third direction D3. One of the sidewall insulating patterns130may extend in the second direction D2to cover or be on side surfaces of the first bit lines BL1and the interlayer insulating layers106, and may extend in the third direction D3along the side surfaces of the first bit lines BL1. Another one of the sidewall insulating patterns130may extend in the second direction D2to cover or be on side surfaces of the first source lines SL1, the interlayer insulating layers106, and the second bit lines BL2, and may extend in the third direction D3along the side surfaces of the first source lines SL1and the second bit lines BL2. Another one of the sidewall insulating patterns130may extend in the second direction D2to cover or be on side surfaces of the second source lines SL2and the interlayer insulating layers106, and may extend along the side surfaces of the second source lines SL2in the third direction D3. The sidewall insulating patterns130may include, for example, silicon oxide, silicon nitride, and/or silicon oxynitride.

According to the present embodiments, the first bit line pads BLP1and the first source line pads SLP1may be spaced apart from the second bit line pads BLP2and the second source line pads SLP2in the third direction D3with the first cell array CAR1and the second cell array CAR2interposed therebetween. That is, the first bit line pads BLP1and the first source line pads SLP1connected to the first cell array CAR1may be disposed in an opposite direction to the second bit line pads BLP2and the second source line pads SLP2connected to the second cell array CAR2. Accordingly, it may be easy to increase the widths BLP1_W, BLP2_W, SLP1_W, and SLP2_W of the first and second bit line pads BLP1and BLP2and the first and second source line pads SLP1and SLP2, and as a result, the first conductive contacts MC1may be easily formed on the first bit line pads BLP1and the first source line pads SLP1, and the second conductive contacts MC2may be easily formed on the second bit line pads BLP2and the second source line pads SLP2. Therefore, a semiconductor device that is easily highly integrated and has excellent reliability may be provided.

FIGS.4,6,8,10,12, and14are plan views illustrating a method of manufacturing a semiconductor device according to some embodiments of the inventive concept.FIGS.5A,7A,9A,11A,13A, and15Aare cross-sectional views corresponding to A-A′ ofFIGS.4,6,8,10,12, and14, respectively, andFIGS.5B,7B,9B,11B,13B, and15Bare cross-sectional views corresponding to B-B′ ofFIGS.4,6,8,10,12, and14, respectively. For simplification of description, descriptions overlapping those of the semiconductor device described with reference toFIGS.1,2,3A, and3Bwill be omitted.

Referring toFIGS.4,5A, and5B, a lower insulating layer102and an etch stop layer104may be sequentially formed on a substrate100. Interlayer insulating layers106and sacrificial layers108may be stacked on the etch stop layer104. The interlayer insulating layers106and the sacrificial layers108may be alternately stacked in the second direction D2perpendicular to an upper surface100U of the substrate100. The lowermost interlayer insulating layer106of the interlayer insulating layers106may be interposed between the lowest sacrificial layer108of the sacrificial layers108and the etch stop layer104, and the uppermost interlayer insulating layer106of the interlayer insulating layers106may be disposed on the uppermost sacrificial layer108of the sacrificial layers108. The sacrificial layers108may include sacrificial pads108P extending in a third direction D3parallel to the upper surface100U of the substrate100or in a direction opposite to the third direction D3, respectively. The interlayer insulating layers106may include, for example, silicon oxide. The sacrificial layers108may include a material having etch selectivity with respect to the interlayer insulating layers106, and may include, for example, silicon nitride.

First trenches T1may be formed in the interlayer insulating layers106and the sacrificial layers108. Each of the first trenches T1may pass through the interlayer insulating layers106and the sacrificial layers108in the second direction D2, and may expose an upper surface of the etch stop layer104. The first trenches T1may be spaced apart from each other in the first direction D1parallel to the upper surface100U of the substrate100, and may extend in the third direction D3parallel to the upper surface100U of the substrate100. The third direction D3may cross the first direction D1. Forming the first trenches T1may include, for example, anisotropically etching the interlayer insulating layers106and the sacrificial layers108.

A first mold structure MS1and a second mold structure MS2may be defined by the first trenches T1. Each of the first and second mold structures MS1and MS2may include the interlayer insulating layers106and the sacrificial layers108between a pair of the first trenches T1. The first trenches T1may be spaced apart from each other in the first direction D1with the first and second mold structures MS1and MS2interposed therebetween, may extend in the third direction D3. The first and second mold structures MS1and MS2may be spaced apart from each other in the first direction D1, and may extend in the third direction D3between the first trenches T1.

The sacrificial layers108of the first mold structure MS1may extend in the third direction D3, and may include the sacrificial pads108P disposed on one side of the first mold structure MS1. The sacrificial pads108P connected to the first mold structure MS1may form a stepped structure at the one side of the first mold structure MS1. The sacrificial layers108of the second mold structure MS2may extend in a direction opposite to the third direction D3, and may include the sacrificial pads108P disposed on one side of the second mold structure MS2. The sacrificial pads108P connected to the second mold structure MS2may form a stepped structure at the one side of the second mold structure MS2. The sacrificial pads108connected to the first mold structure MS1may be spaced apart from the sacrificial pads108connected to the second mold structure MS2in the third direction D3with the first mold structure MS1and the second mold structure MS2interposed therebetween. That is, the sacrificial pads108connected to the first mold structure MS1may be disposed in an opposite direction to the sacrificial pads108connected to the second mold structure MS2. The interlayer insulating layers106of the first and second mold structures MS1and MS2may extend in the third direction D3and in a direction opposite to the third direction D3, and may cover or overlap the sacrificial pads108P.

First holes H1may be formed in each of the first and second mold structures MS1and MS2. Each of the first holes H1may extend in the second direction D2to pass through a corresponding one of the first and second mold structures MS1and MS2, and may expose an upper surface of the etch stop layer104. The first holes H1may be spaced apart from each other in the third direction D3between the first trenches T1. Forming the first holes H1may include, for example, anisotropically etching the interlayer insulating layers106and the sacrificial layers108.

Referring toFIGS.6,7A, and7B, first sacrificial patterns110may be respectively formed in the first trenches T1. The first sacrificial patterns110may be formed to respectively fill the first trenches T1. The first sacrificial patterns110may be spaced apart from each other in the first direction D1with the first and second mold structures MS1and MS2interposed therebetween, and extend in the third direction D3. The first sacrificial patterns110may cover or be on both sides of each of the first and second mold structures MS1and MS2. The first sacrificial patterns110may include a material having etch selectivity with respect to the sacrificial layers108. For example, each of the first sacrificial patterns110may include silicon oxide conformally covering or overlapping inner surfaces of each of the first trenches T1and filling upper regions of each of the first trenches T1and silicon nitride filling the remainder of each of the first trenches T1.

Each of the first holes H1may expose side surfaces of the interlayer insulating layers106and the sacrificial layers108of each of the first and second mold structures MS1and MS2. The exposed side surfaces of the sacrificial layers108may be selectively recessed, and accordingly, first recess regions R1may be formed in the first and second mold structures MS1and MS2. Forming the first recess regions R1may include, for example, performing an etching process having etch selectivity on the sacrificial layers108to etch the exposed side surfaces of the sacrificial layers108, laterally. The first recess regions R1may be spaced apart from each other in the second direction D2within each of the first and second mold structures MS1and MS2, and may be interposed between the interlayer insulating layers106, respectively. Each of the first recess regions R1may be formed to surround each of the first holes H1on a plane view.

Referring toFIGS.8,9A and9B, a plurality of first channel patterns CH1may be respectively formed in the first recess regions R1in the first mold structure MS1, respectively, and a plurality of second channel patterns CH2may be formed in the first recess regions R1of the second mold structure MS2, respectively. Each of the plurality of first and second channel patterns CH1and CH2may fill a portion of each of the first recess regions R1. Forming the plurality of first and second channel patterns CH1and CH2may include, for example, forming a channel layer filling the first recess regions R1and at least partially filling each of the first holes H1, removing the channel layer from the first holes H1, and laterally etching the channel layer in each of the first recess regions R1until the channel layer remains at a desired thickness.

First insulating patterns IN1may be formed in the first recess regions R1of the first mold structure MS1, respectively, and may cover or be on side surfaces of the plurality of first channel patterns CH1, respectively. Second insulating patterns IN2may be formed in the first recess regions R1of the second mold structure MS2, respectively, and may cover or be on side surfaces of the plurality of second channel patterns CH2, respectively. Each of the first and second insulating patterns IN1and IN2may fill a portion of each of the first recess regions R1. First metal patterns MP1may be formed in the first recess regions R1of the first mold structure MS1, respectively, and may cover or be on side surfaces of the first insulating patterns IN1, respectively. Second metal patterns MP2may be formed in the first recess regions R1of the second mold structure MS2, respectively, and may cover or be on side surfaces of the second insulating patterns IN2, respectively. Each of the first and second metal patterns MP1and MP2may fill the remainder of each of the first recess regions R1. The first and second insulating patterns IN1and IN2and the first and second metal patterns MP1and MP2may be formed by substantially the same manner as the plurality of first and second channel patterns CH1and CH2.

Referring toFIGS.10,11A and11B, second sacrificial patterns120may be respectively formed in the first holes H1. The second sacrificial patterns120may be formed to fill the first holes H1, respectively. The second sacrificial patterns120may be spaced apart from each other in the third direction D3in each of the first and second mold structures MS1and MS2. The second sacrificial patterns120may include a material having etch selectivity with respect to the sacrificial layers108. For example, each of the second sacrificial patterns120may include silicon oxide conformally covering or overlapping the inner surface of each of the first holes H1and filling the upper region of each of the first holes H1, and silicon nitride filling the remainder of each of the first holes H1.

The first sacrificial patterns110may be removed from the first trenches T1. Each of the first trenches T1may expose side surfaces of the interlayer insulating layers106and the sacrificial layers108of each of the first and second mold structures MS1and MS2. The exposed side surfaces of the sacrificial layers108may be selectively recessed, and thus second recess regions R2may be formed in the first and second mold structures MS1and MS2. Forming the second recess regions R2may include, for example, performing an etching process having etch selectivity on the sacrificial layers108to laterally etch the exposed side surfaces of the sacrificial layers108. The second recess regions R2may expose side surfaces of the plurality of first and second channel patterns CH1and CH2. The second recess regions R2may be spaced apart from each other in the second direction D2within each of the first and second mold structures MS1and MS2, and may be interposed between the interlayer insulating layers106, respectively. Each of the second recess regions R2may have a line shape extending in the third direction D3.

The sacrificial pads108P may be removed while the sacrificial layers108in the first and second mold structures MS1and MS2are recessed, and accordingly, extended recess regions R2P may be formed. The second recessed regions R2may be respectively connected to the extended recessed regions R2P. The second recessed regions R2may include the extended recessed regions R2P, respectively.

Referring toFIGS.12,13A, and13B, first impurity patterns OP1and second impurity patterns OP2may be formed in the second recess regions R2in the first mold structure MS1, respectively. Each of the first impurity patterns OP1and the second impurity patterns OP2may fill a portion of each of the second recess regions R2in the first mold structure MS1, and may be in contact with one side of each of the plurality of first channel patterns CH1. The first impurity patterns OP1may be spaced apart from each other in the second direction D2. The second impurity patterns OP2may be spaced apart from the first impurity patterns OP1in the first direction D1and may be spaced apart from each other in the second direction D2.

Third impurity patterns OP3and fourth impurity patterns OP4may be respectively formed in the second recess regions R2in the second mold structure MS2. Each of the third impurity patterns OP3and the fourth impurity patterns OP4may fill a portion of each of the second recess regions R2in the second mold structure MS2, and may be in contact with one side of each of the plurality of second channel patterns CH2. The third impurity patterns OP3may be spaced apart from each other in the second direction D2. The fourth impurity patterns OP4may be spaced apart from the third impurity patterns OP3in the first direction D1and may be spaced apart from each other in the second direction D2.

Forming the first to fourth impurity patterns OP1, OP2, OP3, and OP4may include, for example, doping impurities on side surfaces of the plurality of first and second channel patterns CH1and CH2exposed by the second recess regions R2. The first impurity patterns OP1and the second impurity patterns OP2may have the same conductivity type, and the third impurity patterns OP3and the fourth impurity patterns OP4may have the same conductivity type. The impurity may be an N-type impurity or a P-type impurity.

First bit lines BL1and first source lines SL1may be formed to fill the remaining portions of the second recess regions R2in the first mold structure MS1. The first bit lines BL1may be spaced apart from each other in the second direction D2, and may be respectively connected to the first impurity patterns OP1. The first source lines SL1may be spaced apart from the first bit lines BL1in the first direction D1and may be spaced apart from each other in the second direction D2. The first source lines SL1may be respectively connected to the second impurity patterns OP2. Each of the first bit lines BL1and the first source lines SL1may have a line shape extending in the third direction D3. First bit line pads BLP1and first source line pads SLP1may be respectively formed in corresponding extended recess regions R2P among the extended recess regions R2P. The first bit line pads BLP1may be respectively connected to the first bit lines BL1, and the first source line pads SLP1may be respectively connected to the first source lines SL1. The first bit line pads BLP1may form a stepped structure at one side of the first mold structure MS1, and the first source line pads SLP1may form a stepped structure at the one side of the first mold structure MS1.

Second bit lines BL2and second source lines SL2may be formed to fill the remaining portions of the second recess regions R2in the second mold structure MS2. The second bit lines BL2may be spaced apart from the first source lines SL1in the first direction D1and may be spaced apart from each other in the second direction D2. The second bit lines BL2may be respectively connected to the third impurity patterns OP3. The second source lines SL2may be spaced apart from the second bit lines BL2in the first direction D1and may be spaced apart from each other in the second direction D2. The second source lines SL2may be respectively connected to the fourth impurity patterns OP4. Each of the second bit lines BL2and the second source lines SL2may have a line shape extending in the third direction D3. Second bit line pads BLP2and second source line pads SLP2may be respectively formed in corresponding extended recess regions R2P among the extended recess regions R2P. The second bit line pads BLP2may be respectively connected to the second bit lines BL2, and the second source line pads SLP2may be respectively connected to the second source lines SL2. The second bit line pads BLP2may form a stepped structure at one side of the second mold structure MS2, and the second source line pads SLP2may form a stepped structure at the one side of the second mold structure MS2.

The first bit line pads BLP1and the first source line pads SLP1may be spaced apart from the second bit line pads BLP2and the second source line pads SLP2in the third direction D3with the first and second mold structures MS1and MS2interposed therebetween.

Forming the first and second bit lines BL1and BL2, the first and second source lines SL1and SL2, the first and second bit line pads BLP1and BLP2, and the first and second bit line pads BLP1and BLP2, and second source line pads SLP1and SLP2may include, for example, forming a conductive layer filling the remaining portions of the second recess regions R2and the extended recess regions R2P and partially filling each of the first trenches T1, and removing the conductive layer from the first trenches T1.

Sidewall insulating patterns130may be respectively formed in the first trenches T1. The sidewall insulating patterns130may be formed to fill each of the first trenches T1. The sidewall insulating patterns130may be spaced apart from each other in the first direction D1with the first and second mold structures MS1and MS2interposed therebetween. One of the sidewall insulating patterns130may extend in the second direction D2to cover or be on side surfaces of the first bit lines BL1, and another one of the sidewall insulating patterns130may extend in the second direction D2to cover or be on side surfaces of the first source lines SL1and the second bit lines BL2. Another one of the sidewall insulating patterns130may extend in the second direction D2to cover or be on side surfaces of the second source lines SL2. Each of the sidewall insulating patterns130may have a line shape extending in the third direction D3.

Referring toFIGS.14,15A and15B, the second sacrificial patterns120may be removed from the first holes H1. A first ferroelectric pattern FP1may be formed in each of the first holes H1in the first mold structure MS1, and a second ferroelectric pattern FP2may be formed in each of the first hoes H1in the second mold structure MS2. The first ferroelectric pattern FP1may conformally cover, overlap, or be on inner surfaces of each of the first holes H1in the first mold structure MS1. The first ferroelectric pattern FP1may conformally cover or be on side surfaces of the first metal patterns MP1, side surfaces of the interlayer insulating layers106, and an upper surface of the etch stop layer104. The second ferroelectric pattern FP2may conformally cover, overlap, or be on inner surfaces of each of the first holes H1in the second mold structure MS2. The second ferroelectric pattern FP2may conformally cover or be on side surfaces of the second metal patterns MP2, side surfaces of the interlayer insulating layers106, and an upper surface of the etch stop layer104.

Referring back toFIGS.2,3A and3B, a first gate electrode GE1may be formed in each of the first holes H1in the first mold structure MS1, and a second gate electrode GE2may be formed in each of the first holes H1in the second mold structure MS2. The first gate electrode GE1, the first ferroelectric pattern FP1, the plurality of first channel patterns CH1, the first insulating patterns IN1, the first metal patterns MP1, the first and second impurity patterns OP1and OP2, the first bit lines BL1, and the first source lines SL1may be a first cell array CAR1. The second gate electrode GE2, the second ferroelectric pattern FP2, the plurality of second channel patterns CH2, the second insulating patterns IN2, the second metal patterns MP2, the third and fourth impurity patterns OP3and OP4, the second bit lines BL2, and the second source lines SL2may be a second cell array CAR2.

The first bit line pads BLP1may be disposed on one side of the first cell array CAR1and may be respectively connected to the first bit lines BL1. The first bit line pads BLP1may be stacked in the second direction D2on the one side of the first cell array CAR1to form a stepped structure. The first source line pads SLP1may be disposed on the one side of the first cell array CAR1and may be respectively connected to the first source lines SL1. The first source line pads SLP1may be stacked in the second direction D2on the one side of the first cell array CAR1to form a stepped structure. The first bit line pads BLP1and the first source line pads SLP1may be disposed on the same side of the first cell array CAR1, and may neighbor or be adjacent to each other in the first direction D1.

The second bit line pads BLP2may be disposed on one side of the second cell array CAR2and may be respectively connected to the second bit lines BL2. The second bit line pads BLP2may be stacked in the second direction D2on the one side of the second cell array CAR2to form a stepped structure. The second source line pads SLP2may be disposed on the one side of the second cell array CAR2and may be respectively connected to the second source lines SL2. The second source line pads SLP2may be stacked in the second direction D2on the one side of the second cell array CAR2to form a stepped structure. The second bit line pads BLP2and the second source line pads SLP2may be disposed on the same side of the second cell array CAR2and may neighbor or be adjacent to each other in the first direction D1.

The first bit line pads BLP1and the first source line pads SLP1may be spaced apart from the second bit line pads BLP2and the second source line pads SLP2in the third direction D3with the first cell array CAR1and the second cell array CAR2interposed therebetween.

FIG.16is a plan view of a semiconductor device according to some embodiments of the inventive concept, andFIG.17is a cross-sectional view taken along line B-B′ ofFIG.16. The cross-sectional view taken along line A-A′ ofFIG.16is substantially the same as the cross-sectional view ofFIG.3A. For simplicity of description, differences from the semiconductor device described with reference toFIGS.1,2,3A, and3Bwill be mainly described.

Referring toFIGS.16,3A, and17, first bit line pads BLP1may be disposed on one side of the first cell array CAR1and may be connected to the first bit lines BL1, respectively. The first bit lines BL1may extend longer in the third direction D3as the first bit lines BL1are closer to the substrate100, and the first bit line pads BLP1may be connected to ends of the first bit lines BL1, respectively. The first bit line pads BLP1may be stacked in the second direction D2on the one side of the first cell array CAR1to form a stepped structure. A width BLP1_W of each of the first bit line pads BLP1in the first direction D1may be greater than a width BL1_W of each of the first bit lines BL1in the first direction D1.

First source line pads SLP1may be disposed on the other side of the first cell array CAR1and may be respectively connected to the first source lines SL1. The first source lines SL1may extend longer in a direction opposite to the third direction D3as the first source lines SL1are closer to the substrate100, and the first source line pads SLP1may be connected to ends of the first source lines SL1, respectively. The first source line pads SLP1may be stacked on the other side of the first cell array CAR1in the second direction D2to form a stepped structure. A width SLP1_W of each of the first source line pads SLP1in the first direction D1may be greater than a width SL1_W of each of the first source lines SL1in the first direction D1.

According to the present example embodiments, the first bit line pads BLP1may be spaced apart from the first source line pads SLP1in the third direction D3with the first cell array CAR1interposed therebetween. The first bit line pads BLP1and the first source line pads SLP1may be respectively disposed on opposite sides of the first cell array CAR1. The first bit lines BL1and the first source lines SL1may be referred to as first conductive lines, and the first bit line pads BLP1and the first source line pads SLP1may be referred to as first conductive line pads.

Second bit line pads BLP2may be disposed on one side of the second cell array CAR2and may be respectively connected to the second bit lines BL2. The second bit lines BL2may extend longer in the third direction D3as the second bit lines BL2are closer to the substrate100, and the second bit line pads BLP2may be connected to ends of the second bit lines BL2, respectively. The second bit line pads BLP2may be stacked in the second direction D2on the one side of the second cell array CAR2to form a stepped structure. A width BLP2_W of each of the second bit line pads BLP2in the first direction D1may be greater than a width BL2_W of each of the second bit lines BL2in the first direction D1.

Second source line pads SLP2may be disposed on the other side of the second cell array CAR2and may be respectively connected to the second source lines SL2. The second source lines SL2may extend longer in a direction opposite to the third direction D3as the second source lines SL2are closer to the substrate100, and the second source line pads SLP2may be connected to ends of the second source lines SL2, respectively. The second source line pads SLP2may be stacked in the second direction D2on the other side of the second cell array CAR2to form a stepped structure. The width SLP2_W of each of the second source line pads SLP2in the first direction D1may be greater than a width SL2_W in the first direction D1.

According to the present example embodiments, the second bit line pads BLP2may be spaced apart from the second source line pads SLP2in the third direction D3with the second cell array CAR2interposed therebetween. The second bit line pads BLP2and the second source line pads SLP2may be respectively disposed on opposite sides of the second cell array CAR2. The second bit line pads BLP2may neighbor or be adjacent to the first bit line pads BLP1in the first direction D1, and the second source line pads SLP2may neighbor or be adjacent to the first source line pads SLP1in the first direction D1. The second bit lines BL2and the second source lines SL2may be referred to as second conductive lines, and the second bit line pads BLP2and the second source line pads SLP2may be referred to as second conductive line pads.

According to the present example embodiments, the first bit line pads BLP1and the second bit line pads BLP2may be spaced apart from the first source line pads SLP1and the second source line pads SLP2in the third direction D3with the first cell array CAR1and the second cell array CAR2interposed therebetween. That is, the first bit line pads BLP1and the second bit line pads BLP2may be disposed in an opposite direction to the first source line pads SLP1and the second source line pads SLP2. Accordingly, it may be easy to increase the widths BLP1_W, BLP2_W, SLP1_W, and SLP2_W of the first and second bit line pads BLP1and BLP2and the first and second source line pads SLP1and SLP2, and as a result, the first conductive contacts MC1may be easily formed on the first bit line pads BLP1and the first source line pads SLP1, and the second conductive contacts MC2may be easily formed on the second bit line pads BLP2and the second source line pads SLP2. Accordingly, a semiconductor device that is easily highly integrated and has excellent reliability may be provided.

According to the concept of the inventive concept, the first bit line pads and the first source line pads connected to the first cell array may be disposed in opposite direction to the second bit line pads and the second source line pads connected to the second cell array. In some embodiments, the first bit line pads and the first source line pads connected to the first cell array may be disposed in opposite direction to each other. Accordingly, it may be easy to increase the widths of the first and second bit line pads and the first and second source line pads, and as a result, the conductive contacts may be easily formed on the first and second bit line pads and the first and second source line pads. Therefore, it is possible to provide the semiconductor device with the high integration and excellent reliability.

While embodiments are described above, a person skilled in the art may understand that many modifications and variations are made without departing from the spirit and scope of the inventive concept defined in the following claims. Accordingly, the example embodiments of the inventive concept should be considered in all respects as illustrative and not restrictive, with the spirit and scope of the inventive concept being indicated by the appended claims.