Method for fabrication of NIR CMOS image sensor

A method of fabricating CMOS image sensors is disclosed. In contrast to traditional fabrication processes, the present sequence implants dopants into the epitaxial layer from both the first surface and the second surface. Because dopant is introduced through both sides, the maximum implant energy to perform the implant may be reduced by as much as 50%. In certain embodiments, the second implant is performed prior to the application of the electrical contacts. In another embodiments, the second implant is performed after the application of the electrical contacts. This method may allow deeper photodiodes to be fabricated using currently available semiconductor processing equipment than would otherwise be possible.

FIELD

Embodiments of this disclosure are directed to methods for fabricating a CMOS image sensor, and more particularly a back-illuminated near infrared image sensor having vertical photodiodes.

BACKGROUND

CMOS image sensors are used for many applications, including cameras, webcams, infrared sensor, proximity sensors and others. Over time, the demand for higher resolution of these image sensors has increased. More specifically, the demand for near infrared (NIR) sensors for thermal imaging in autonomous vehicles is expected to accelerate in the coming years.

One way to achieve higher resolution is to rearrange the image sensor so that the photodiodes are vertically oriented. In this way, the total volume that is used for each photodiode remains unchanged, but the surface area used by each photodiode is reduced. In this way, more photodiodes may be disposed in the same surface area.

As technology advances, these vertical photodiodes are becoming deeper and deeper. This increased depth creates issues regarding the introduction of dopant into these vertical photodiodes. More specifically, the energy used to implant dopant throughout the photodiode has become very high, such as in excess of 10 MeV or more. Further, future image sensors are likely to have even deeper photodiodes, exacerbating this issue.

Therefore, it would be beneficial if there was a method of fabricating an image sensor that utilized the implant energies that are currently employed. In this way, existing semiconductor processing equipment could continue to be used. Further, it would be advantageous if this method could be easily integrated into current fabrication processes.

SUMMARY

A method of fabricating CMOS image sensors is disclosed. In contrast to traditional fabrication processes, the present sequence implants dopants into the epitaxial layer from both the first surface and the second surface. Because dopant is introduced through both sides, the maximum implant energy to perform the implant may be reduced by as much as 50%. In certain embodiments, the second implant is performed prior to the application of the electrical contacts. In another embodiments, the second implant is performed after the application of the electrical contacts. This method may allow deeper photodiodes to be fabricated using currently available semiconductor processing equipment than would otherwise be possible.

According to one embodiment, a method of fabricating an image sensor is disclosed. The method comprises forming an epitaxial layer on a surface of a wafer, wherein a first surface of the epitaxial layer comprises an exposed surface and a second surface of the epitaxial layer is disposed on the surface of the wafer; performing a first implant by implanting dopant through the first surface and into the epitaxial layer; forming circuitry and electrical contacts on the first surface; bonding a handle wafer to the electrical contacts; thinning the wafer; performing a second implant by implanting dopant through the second surface and into the epitaxial layer; performing a thermal treatment to anneal the dopant; and forming optical components on the second surface. In certain embodiments, the first implant and the second implant are each performed using a plurality of implant energies. In some further embodiments, the maximum implant energy is selected such that dopant is implanted at a depth that is at least 50% of a thickness of the epitaxial layer. In some embodiments, the method further comprises creating deep trench isolation in the epitaxial layer. In some embodiments, the deep trench isolation is created by implanting a second dopant having an opposite conductivity as the dopant into the epitaxial layer through the first surface. In some embodiments, the deep trench isolation is created by implanting a second dopant having an opposite conductivity as the dopant into the epitaxial layer through the second surface. In certain embodiments, the dopant comprises a N-type dopant and the deep trench isolation is formed by implanting a P-type dopant. In some embodiments, the thermal treatment comprises a laser anneal. In certain embodiments, the thermal treatment is performed following the second implant and before forming the optical components.

According to another embodiment, a method of fabricating an image sensor is disclosed. The method comprises forming an epitaxial layer on a surface of a wafer, wherein a first surface of the epitaxial layer comprises an exposed surface and a second surface of the epitaxial layer is disposed on the surface of the wafer; performing a first implant by implanting dopant through the first surface and into the epitaxial layer; bonding a handle wafer to the first surface; thinning the wafer; performing a second implant by implanting dopant through the second surface and into the epitaxial layer; forming circuitry and electrical contacts on the second surface; performing a thermal treatment to anneal the dopant; bonding a second handle wafer to the electrical contacts; removing the handle wafer to expose the first surface; and forming optical components on the first surface. In certain embodiments, the first implant and the second implant are each performed using a plurality of implant energies. In some further embodiments, the maximum implant energy is selected such that dopant is implanted at a depth that is at least 50% of a thickness of the epitaxial layer. In some embodiments, the method further comprises creating deep trench isolation in the epitaxial layer. In some embodiments, the deep trench isolation is created by implanting a second dopant having an opposite conductivity as the dopant into the epitaxial layer through the first surface. In some embodiments, the deep trench isolation is created by implanting a second dopant having an opposite conductivity as the dopant into the epitaxial layer through the second surface. In certain embodiments, the dopant comprises a N-type dopant and the deep trench isolation is formed by implanting a P-type dopant. In some embodiments, the thermal treatment comprises a laser anneal. In certain embodiments, the thermal treatment is performed following the second implant and before forming the optical components.

DETAILED DESCRIPTION

The present disclosure utilizes ion implants that are performed into both sides of a workpiece. By implanting ion through both sides of a workpiece, the implant energy that is used to reach the deepest depths is reduced.

FIGS.1A-1Kshow the various processes that a workpiece undergoes during a fabrication sequence to create a CMOS image sensor according to one embodiment. This image sensor may be a near infrared (NIR) sensor.

FIG.2shows a flowchart that reflects the fabrication sequence used to create the CMOS image sensor according to this embodiment.

As shown inFIG.1A, a wafer100, such as a silicon wafer, is used. The wafer100may be about 750 μm thick.

Next, as shown inFIG.1Band in Box200ofFIG.2, epitaxial layer110is grown on the top surface of the wafer100. An epitaxial process may introduce a silicon-containing gas in a chamber containing the wafer100. The epitaxial layer110may be partially or completely comprised of silicon. In some embodiments, the height of the epitaxial layer110may be greater than 5 μm. In certain embodiments, the height of the epitaxial layer110may be in excess of 10 μm. The epitaxial layer110has a first surface111a, which is the top surface after growth, and a second surface111b, opposite the first surface111a, which contacts the wafer100.

As shown inFIG.1Cand in Box210ofFIG.2, a first implant of dopant115is performed. Dopant115is implanted into the epitaxial layer110through the first surface111a. In certain embodiments, the dopant115may be a n-type dopant, such as a Group 5 element, which may be phosphorus or arsenic. Multiple implants may be performed using different implant energies. These multiple implants may be used to create a concentration profile that resembles a box profile. The concentration of dopant in the epitaxial layer110may be 1E17 in certain embodiments. The depth of the implant having the greatest implant energy may be 50% or more of the total thickness of the epitaxial layer110.

FIG.1Dshows the workpiece following the implant of dopant115. Note that the epitaxial layer110is now bifurcated, where there is an implanted epitaxial layer110aand an unimplanted epitaxial layer110b. The implanted epitaxial layer110ais disposed proximate the first surface111a, while the unimplanted epitaxial layer110bis proximate the second surface111b. The dopant115is used to create photodiodes112in the epitaxial layer110. As described above, these photodiodes112are vertically arranged, and have a depth that may be greater than the length or width. These photodiodes112may extend through much of the epitaxial layer110. For example, if the epitaxial layer110is 10 μm thick, the photodiode112may have a thickness of 8 μm or more.

In certain embodiments, part or all of the deep trench isolation116may be created at this time as well. Deep trench isolation116is used to separate adjacent photodiodes112from one another to minimize crosstalk and interferences. In certain embodiments, the deep trench isolation is achieved by passivating with an implant the boundaries between adjacent photodiodes112with a second dopant having the opposite conductivity as the dopant115used to form the photodiodes112. Thus, if the photodiode112is N-doped, the deep trench isolation116may be P-doped. The deep trench isolation may be created by implanting P-type dopants through the first surface111aof the epitaxial layer110.

In certain embodiments, as shown in Box220inFIG.2, the first surface111aof the epitaxial layer110is masked and then implanted with a p-type dopant, such as boron. Multiple implants at different implant energies may be used to create the deep trench isolation116. Since, the deep trench isolation116is used to separate the photodiodes112, it may extend as deep as the photodiodes112. In other embodiments, the implants are performed at an implant energy such that the deep trench isolation116extends at least 50% of the thickness of the epitaxial layer110.

Next, as shown inFIG.1Eand in Box230inFIG.2, circuitry may be fabricated on the first surface111aof the epitaxial layer110. This circuitry may include poly-silicon gates. Additionally, bonding pads may be disposed on the first surface111aof the epitaxial layer110. In addition to the circuitry, there may be electrical contacts120on the first surface111aof the epitaxial layer110. Note that the circuitry and electrical contacts120are adjacent to the implanted epitaxial layer110a. In certain embodiments, the electrical contacts120may be created through the application of one or more metallization layers.

As shown inFIG.1Fand in Box240ofFIG.2, a second wafer, which may be referred to as a handle wafer130, is bonded to the electrical contacts120. In one embodiment, the handle wafer130is secured to the top surface of the electrical contacts120through direct bonding. In this embodiment, a thin silicon oxide layer may be deposited, grown or otherwise formed on the top surface of the electrical contacts120. A thin silicon oxide layer may also be deposited, grown, or otherwise formed on one surface of the handle wafer130. These two thin silicon oxide layers may both be planarized, such as through the use of chemical mechanical polishing (CMP). These two thin silicon oxide layers are then pressed together, and bond together via direct silicon bonding. In another embodiment, the handle wafer130may be secure to the top surface of the electrical contacts using an adhesive.

The combined workpiece is then flipped, as shown inFIG.1G.

The wafer100is then thinned, as shown inFIG.1Hand in Box250ofFIG.2, such as through use of a CMP process. The wafer100may be thinned such that the second surface111bof the epitaxial layer110is exposed. In other embodiments, a thin layer of the wafer100may remain after the CMP process.

As shown inFIG.1Iand in Box260ofFIG.2, a second implant of dopant115is performed. Dopant115is implanted through the second surface111band into the unimplanted epitaxial layer110b. In certain embodiments, the dopant115may be a n-type dopant, such as a Group 5 element, which may be phosphorus or arsenic. Multiple implants may be performed using different implant energies. These multiple implants may be used to create a concentration profile that resembles a box profile. The concentration of dopant in the epitaxial layer110may be 1E17 in certain embodiments. The depth of the implant having the greatest implant energy may be 50% or more of the total thickness of the epitaxial layer110such that, the dopant115from the second implant extends to the implanted epitaxial layer110a. In other words, there is no undoped region in the middle of the epitaxial layer110. In certain embodiments, the entirety of the epitaxial layer110is doped. However, in other embodiments, there may be less doped or undoped regions that are disposed near the first surface111aor the second surface111b.

In certain embodiments, as shown in Box270ofFIG.2, part or all of the deep trench isolation116may be created at this time as well. As described above, in certain embodiments, the deep trench isolation is achieved by doping the boundaries between adjacent photodiodes112by implanting a second dopant having the opposite conductivity as the dopant115used to form the photodiodes112. Thus, if the photodiode112is N-doped, the deep trench isolation116may be P-doped.

In certain embodiments, the second surface111bof the epitaxial layer110is masked and then implanted with a p-type dopant, such as boron. Multiple implants at different implant energies may be used to create the deep trench isolation116. Specifically, the deep trench isolation116is used to separate the photodiodes112. Thus, the deep trench isolation may extend as far as the photodiodes112. In other embodiments, the implants are performed at an implant energy such that the deep trench isolation116extends at least 50% of the thickness of the epitaxial layer110.

In certain embodiments, Box220may be omitted. In other embodiments, Box270may be omitted.

FIG.1Jshows the workpiece after the second implant is performed. At this point, the epitaxial layer110has been implanted with dopant115to form the photodiode112. Furthermore, the deep trench isolation116has been fully formed.

In some embodiments, as shown in Box280ofFIG.2, a thermal treatment is performed at this time. The thermal treatment is performed such that the electrical contacts120are not damaged by this treatment. In certain embodiments, the thermal treatment may be a laser anneal.

In another embodiment, the thermal treatment may be performed at two different points in time. For example, a first thermal treatment may be performed following the first implant shown inFIG.1D(i.e. Box210or Box220), and the second thermal treatment may be performed following the second implant shown inFIG.1I.

After the thermal treatment is performed, the optical components140, which may comprise the antireflective coating, color filters, spacers, and microlenses, are formed on top of the second surface111bof the epitaxial layer110, as shown inFIG.1Kand in Box290.

The image sensor can be integrated with a digital signal processor or other circuitry via the electrical contacts120. For example, the handle wafer130may be removed to expose the electrical contacts120.

This final workpiece is similar in structure to a traditional CMOS image sensor. However, unlike conventional CMOS image sensors, the implanting of the dopant115was performed from both sides of the epitaxial layer110. This reduces the implant energy needed to create the desired concentration box profile in the photodiodes112.

FIGS.3A-3Nshow the various processes that a workpiece undergoes during a fabrication sequence to create a CMOS image sensor according to a second embodiment.

FIG.4shows a flowchart that reflects the fabrication sequence used to create the CMOS image sensor according to this embodiment.

Note thatFIGS.3A-3Dare the same as those described above with respect to the first embodiment and shown inFIGS.1A-1D. Therefore, these processes will not be described again. Similarly, Boxes400-420ofFIG.4are the same as Boxes200-220ofFIG.2.

InFIG.3Eand Box430ofFIG.4, a handle wafer130is bonded to the first surface111aof the epitaxial layer110, which is the top surface of the implanted epitaxial layer110a. This bonding may be direct bonding and may be achieved using the technique described above with respect toFIG.1F. In another embodiment, an adhesive may be used to bond the handle wafer130to the epitaxial layer110.

The combined workpiece is then flipped, as shown inFIG.3F.

The wafer100is then thinned, as shown inFIG.3Gand in Box440ofFIG.4, such as through use of a CMP process. The wafer100may be thinned such that the second surface111bof the epitaxial layer110is exposed. In other embodiments, a thin layer of the wafer100may remain on the second surface111bof the epitaxial layer110.

As shown inFIG.3Hand in Box450ofFIG.4, a second implant of dopant115is performed. Dopant115is implanted through the second surface111band into the unimplanted epitaxial layer110b. As described above, in certain embodiments, the dopant115may be a n-type dopant, such as a Group 5 element, which may be phosphorus or arsenic. Multiple implants may be performed using different implant energies. These multiple implants may be used to create a concentration profile that resembles a box profile. The concentration of dopant in the epitaxial layer110may be 1E17 in certain embodiments. The depth of the implant having the greatest implant energy may be 50% or more of the total thickness of the epitaxial layer110such that, the dopant115from the second implant extends to the implanted epitaxial layer110a. In other words, there is no undoped region in the middle of the epitaxial layer110. In certain embodiments, the entirety of the epitaxial layer110is doped. However, in other embodiments, there may be less doped or undoped regions that are disposed near the first surface111aor the second surface111b.

In certain embodiments, as shown in Box460ofFIG.4, part or all of the deep trench isolation116may be created at this time as well. As described above, in certain embodiments, the deep trench isolation is achieved by passivating with an implant the boundaries between adjacent photodiodes112with a second dopant having the opposite conductivity as the dopant115used to create the photodiode112. Thus, if the photodiode112is N-doped, the deep trench isolation116may be P-doped.

In certain embodiments, the second surface111bof the epitaxial layer110is masked and then implanted with a p-type dopant, such as boron. Multiple implants at different implant energies may be used to create the deep trench isolation116. Specifically, the deep trench isolation116is used to separate the photodiodes112. Thus, the deep trench isolation may extend as far as the photodiodes112. In other embodiments, the implants are performed at an implant energy such that the deep trench isolation116extends at least 50% of the thickness of the epitaxial layer110.

In certain embodiments, Box420may be omitted. In other embodiments, Box460may be omitted.

FIG.3Ishows the workpiece after the second implant is performed. At this point, the epitaxial layer110has been implanted with dopant115. Furthermore, the deep trench isolation116has been fully formed.

In certain embodiments, as shown in Box470ofFIG.4, a thermal treatment may be performed after the second implant. This thermal treatment may be performed using a laser anneal or another process.

Next, as shown inFIG.3Jand in Box480inFIG.4, circuitry may be fabricated on the second surface111bof the epitaxial layer110. This circuitry may include poly-silicon gates. Additionally, bonding pads may be disposed on the top surface of the epitaxial layer110. In addition to the circuitry, there may be one or more electrical contacts120on the second surface111bof the epitaxial layer110.

As shown inFIG.3Kand in Box490ofFIG.4, a third wafer, which may be referred to as a second handle wafer150, is bonded to the electrical contacts120. In one embodiment, the second handle wafer150is secured to the top surface of the workpiece through direct bonding. In this embodiment, a thin silicon oxide layer may be deposited, grown or otherwise formed on the top surface of the electrical contacts120. A thin silicon oxide layer may also be deposited, grown, or otherwise formed on one surface of the second handle wafer150. These two thin silicon oxide layers may both be planarized, such as through the use of chemical mechanical polishing (CMP). These two thin silicon oxide layers are then pressed together, and bond together via direct silicon bonding. In another embodiment, the second handle wafer150is bonded using an adhesive.

The combined workpiece is then flipped, as shown inFIG.3L.

The handle wafer130is then removed, as shown inFIG.3Mand in Box493ofFIG.4. This may be done through use of a CMP process. In another embodiment, the handle wafer130may be removed by applying heat or mechanical force. When the handle wafer130is removed, the first surface111aof the epitaxial layer110is exposed.

In certain embodiments, a thermal treatment may be performed after the thinning. This thermal treatment may be performed so as not to damage the electrical contacts120. This may be achieved using a laser anneal.

Finally, the optical components140, which may comprise the antireflective coating, color filters, spacers, and microlenses, are formed on top of the first surface111aof the epitaxial layer110, as shown inFIG.3Nand in Box496ofFIG.4.

The image sensor can be integrated with a digital signal processor or other circuitry via the electrical contacts120. For example, the second handle wafer150may be removed to expose the electrical contacts120.

Again, this final workpiece is similar in structure to a traditional CMOS image sensor. However, unlike conventional CMOS image sensors, the implanting of the dopant115was performed from both sides of the epitaxial layer110. This reduces the implant energy needed to create the desired concentration box profile in the photodiodes112.

In fact, in certain embodiments, the fabrication process from Box450to Box496may be the same as is currently performed.

The methods described herein have many advantages. First, as CMOS image sensors become more dense, the depths of the photodiodes has increased. In fact, in certain embodiments, dopant is implanted into the device to create photodiodes. These photodiodes may be more than 5 μm thick. Thus, implant energies in excess of 10 MeV may be used to create the desired concentration profile. As photodiodes continue to become thicker, implant energies used to perform these implants will also continue to increase. The ability to perform implants at these implant energies is challenging and will become more so over time. For example, to achieve these higher implant energies, current implanters may need to be re-designed and built with a much larger footprint to withstand these extremely high voltages. The capital expenditure and time to implement implanters capable of greater than 10 MeV is prohibitive, thus exacerbating this issue.

By implanting the dopant through both surfaces of the epitaxial layer, the maximum implant energy is effectively reduced by 50%. This will enable the current capabilities of semiconductor processing equipment to be used to create deeper photodiodes than would otherwise be possible. Further, it allows next generation semiconductor processing equipment to create the next generation photodiodes that are twice as deep as would otherwise be possible.