Discrete three-dimensional vertical memory

The present invention discloses a discrete three-dimensional vertical memory (3D-MV). It comprises at least a 3D-array die and at least a voltage-generator die. The 3D-array die comprises a plurality of vertical memory strings. At least a voltage-generator component for the 3D-array die is located on the voltage-generator die instead of the 3D-array die. The 3D-array die and the voltage-generator die have substantially different back-end-of-line (BEOL) structures.

BACKGROUND

1. Technical Field of the Invention

The present invention relates to the field of integrated circuit, and more particularly to three-dimensional memory (3D-M).

2. Prior Arts

U.S. Pat. No. 5,835,396 issued to Zhang on Nov. 3, 1998 discloses a 3D-M, more particularly a 3D-ROM. As illustrated inFIG. 1A, a 3D-M die20comprises a substrate-circuit level0K and a plurality of vertically stacked memory levels16A,16B. The substrate-circuit level0K comprises substrate transistors0tand substrate interconnects0i. The substrate transistors0tare formed in a semiconductor substrate0. The substrate interconnects0iare the interconnects for the substrate transistor0t. In this example, the substrate interconnects0iincludes metal layers0M1,0M2. Hereinafter, the metal layers0M1,0M2in the substrate interconnects0iare referred to as substrate interconnect layers; the materials used in the substrate interconnects0iare referred to as substrate interconnect materials.

The memory levels16A,16B are stacked above the substrate-circuit level0K. They are coupled to the substrate0through contact vias (e.g.,1av). Each of the memory levels (e.g.,16A) comprises a plurality of upper address lines (e.g.,2a), lower address lines (e.g.,1a) and memory cells (e.g.,5aa). The memory cells could comprise diodes, transistors or other devices. Among all types of memory cells, the diode-based memory cells are of particular interest because they have the smallest size of ˜4F2, where F is the minimum feature size. Since they are generally located at the cross points between the upper and lower address lines, the diode-based memory cells form a cross-point array. Hereinafter, diode is broadly interpreted as any two-terminal device whose resistance at the read voltage is substantially lower than when the applied voltage has a magnitude smaller than or polarity opposite to that of the read voltage. In one exemplary embodiment, diode is a semiconductor diode, e.g., p-i-n silicon diode. In another exemplary embodiment, diode is a metal-oxide diode, e.g., titanium-oxide diode, nickel-oxide diode.

The memory levels16A,16B form at least a 3D-M array16, while the substrate-circuit level0K comprises the peripheral circuit for the 3D-M array16. A first portion of the peripheral circuit is located underneath the 3D-M array16and it is referred to as under-array peripheral circuit. A second portion of the peripheral circuit is located outside the 3D-M array16and it is referred to as outside-array peripheral circuits18. Because the outside-array peripheral circuit18comprises significantly fewer back-end-of-line (BEOL) layers than the 3D-M array16, the space17above the outside-array peripheral circuits18is empty and completely wasted. Hereinafter, a BEOL layer refers to the layer(s) defined by a single photolithography step during BEOL processing. InFIG. 1A, the 3D-M array16comprises fourteen BEOL layers, including two for each interconnect layer (e.g.,0M1,0M2) and five for each memory level (e.g.,16A,16B). On the other hand, the outside-array peripheral circuit18comprises only four BEOL layers, including two for each substrate interconnect layer (e.g.,0M1,0M2).

U.S. Pat. No. 7,383,476 issued to Crowley et al. on Jun. 3, 2008 discloses an integrated 3D-M die, whose 3D-arrays and peripheral circuit are integrated on a same die. As is illustrated inFIG. 1B, an integrated 3D-M die20comprises a 3D-array region22and a peripheral-circuit region28. The 3D-array region22comprises a plurality of 3D-M arrays (e.g.,22aa,22ay) and their decoders (e.g.,24,24G). These decoders include local decoders24and global decoders24G. The local decoder24decodes address/data for a single 3D-M array, while the global decoder24G decodes global address/data25to each 3D-M array.

The peripheral-circuit region28comprises all necessary peripheral-circuit components for a standalone integrated 3D-M die20to perform basic memory functions, i.e., it can directly use the voltage supply23provided by a user (e.g., a host device), directly read data27from the user and directly write data27to the user. It includes a read/write-voltage generator (VR/VW-generator)21and an address/data translator (A/D-translator)29. The VR/VW-generator21provides read voltage VRand/or write (programming) voltage VWto the 3D-M array(s). The A/D-translator29converts address and/or data from a logical space to a physical space and/or vice versa. Hereinafter, the logical space is the space viewed from the perspective of a user of the 3D-M, while the physical space is the space viewed from the perspective of the 3D-M.

The VR/VW-generator21includes a band-gap reference generator21B, a VRgenerator21R and a charge-pump circuit21W. Among them, the band-gap reference generator21B is a precision reference generator; the VRgenerator21R generates the read voltage VR; and, the charge-pump circuit21W generates the write voltage VW(referring to U.S. Pat. No. 6,486,728, “Multi-Stage Charge-pump circuit”, issued to Kleveland on Nov. 26, 2002). The integrated 3D-M die20generates both read voltage and write voltage internally.

The A/D-translator29includes address translator and data translator. It includes an oscillator290, an error checking & correction (ECC) circuit29E, a page register/fault memory/trim-bit circuit29P and a smart write controller29W. The oscillator290provides an internal clock signal. The ECC circuit29E detects and corrects errors while performing ECC-decoding after data are read out from the 3D-M arrays. It also performs ECC-encoding before data are written to the 3D-M arrays (referring to U.S. Pat. No. 6,591,394, “Three-Dimensional Memory Array and Method for Storing Data Bits and ECC Bits Therein” issued to Lee et al. on Jul. 8, 2003). The page register29P serves as an intermediate storage device between the user and the 3D-M array(s), while the fault memory/trim-bit circuit29P performs address mapping (referring to U.S. Pat. No. 8,223,525, “Page Register Outside Array and Sense Amplifier Interface”, issued to Balakrishnan et al. on Jul. 17, 2012). The smart write controller29W collects detected errors during programming and activates the self-repair mechanism which will reprogram the data in a redundant row (referring to U.S. Pat. No. 7,219,271, “Memory Device and Method for Redundancy/Self-Repair”, issued to Kleveland et al. on May 15, 2007). The integrated 3D-M die20performs both address translation and data translation internally.

The VR/VW-generator21and A/D-translator29are outside-array peripheral-circuit components18. Because they occupy a large area on the 3D-M die20, the integrated 3D-M die20has a low array efficiency. The array efficiency is defined as the ratio between the total memory area (i.e., the chip area used for memory) and the total chip area. In 3D-M, the total memory area (AM) is the chip area directly underneath user-addressable bits (not counting bits a user cannot access) and can be expressed as AM=Ac*CL=(4F2)*C3D-M/N, where CLis the storage capacity per memory level, Acis the area of a single memory cell, C3D-Mis the total storage capacity of the 3D-M, F is the address-line pitch, and N is the total number of memory levels in the 3D-M. In the following paragraphs, two 3D-M dice are examined for their array efficiencies.

As a first example, a 3-D one-time-programmable memory (3D-OTP) is disclosed in Crowley et al. “512 Mb PROM with 8 Layers of Antifuse/Diode Cells” (referring to 2003 International Solid-State Circuits Conference, FIG. 16.4.5). This 3D-OTP die has a storage capacity of 512 Mb and comprises eight memory levels manufactured at 0.25 um node. The total memory area is 4*(0.25 um)2*512 Mb/8=16 mm2. With a total chip area of 48.3 mm2, the array efficiency of the 3D-OTP die is ˜33%.

As a second example, a 3-D resistive random-access memory (3D-ReRAM) is disclosed in Liu et al. “A 130.7 mm22-Layer 32 Gb ReRAM Memory Device in 24 nm Technology” (referring to 2013 International Solid-State Circuits Conference, FIG. 12.1.7). This 3D-ReRAM die has a storage capacity of 32 Gb and comprises two memory levels manufactured at 24 nm node. The total memory area is 4*(24 nm)2*32 Gb/2=36.8 mm2. With a total chip area of 130.7 mm2, the array efficiency of the 3D-ReRAM die is 28%.

The example inFIGS. 1A-1Bis a three-dimensional horizontal memory (3D-MH), whose basic storage units are horizontal memory levels. This cost-analysis can also be applied to a three-dimensional vertical memory (3D-MV), whose basic storage units are vertical memory strings.

U.S. Pat. No. 8,638,611 issued to Sim et al. on Jan. 28, 2014 discloses a 3D-MV. It is a vertical-NAND. Besides vertical-NAND, the 3D-ROM, 3D-RAM, 3D-memristor, 3D-ReRAM or 3D-RRAM, 3D-PCM, 3D-PMC, 3D-CBRAM disclosed above can also be arranged into 3D-MV. As illustrated inFIG. 2, a 3D-MVdie20V comprises at least a 3D-MVarray16V and a peripheral circuit18. The 3D-MVarray16V comprises a plurality of vertical memory strings16X,16Y. Each memory string (e.g.,16X) comprises a plurality of vertically stacked memory cells (e.g.,8a-8h). These memory cells are coupled by at least a vertical address line. Each memory cell (e.g.,8f) comprises at least a vertical transistor, with a gate6, an information storage layer7and a vertical channel9. As an integrated 3D-MV, the 3D-MVarray16V and its peripheral circuit18are integrated into a single die20V.

A notable difference between 3D-MH(FIG. 1A) and 3D-MV(FIG. 2) is that the horizontal memory levels16A,16B in 3D-MHdo not include any portion of the substrate0, whereas the vertical memory strings16X,16Y in 3D-MVinclude a portion of the substrate0. In other words, the 3D-MHdie20could comprise an under-array peripheral circuit, whereas the 3D-MVdie20V cannot comprise any under-array peripheral circuit. The peripheral circuit18for the 3D-MV20V is completely located outside the 3D-MVarray16V. It comprises substrate transistors0tand substrate interconnects0i. The substrate transistors0tare conventional (horizontal) transistors, which are formed in a semiconductor substrate0. The substrate interconnects0iare the interconnects for the substrate transistor0t. In this example, the substrate interconnects0iincludes metal layers0M1,0M2.

It is a prevailing belief in the field of integrated circuit that more integration is always desired. However, this belief is no longer true for any 3D-M (including both 3D-MHand 3D-MV). For 3D-MH, because the peripheral circuit18comprises significantly fewer BEOL layers than the 3D-MHarrays16, integration would force the peripheral circuit18to use the expensive BEOL manufacturing process of the 3D-MHarrays16and therefore, increases the overall 3D-MHcost. Similarly, for 3D-MV, because the vertical memory strings16X,16Y use a complex BEOL process whereas the peripheral circuit18uses a relatively simple BEOL process, integrating the vertical memory strings16X,16Y with their peripheral circuit18will force the peripheral circuit18to use the expensive BEOL manufacturing process for the vertical memory strings16X,16Y. As a result, integration does not lower the overall cost, but actually increases the overall cost of the 3D-MV.

OBJECTS AND ADVANTAGES

It is a principle object of the present invention to provide a three-dimensional vertical memory (3D-MV) with a lower overall cost.

It is another object of the present invention to improve the array efficiency of the 3D-MV.

In accordance with these and other objects of the present invention, a discrete 3D-MVis disclosed.

SUMMARY OF THE INVENTION

To lower the overall cost of the 3D-MV, the present invention follows this design guideline: separate the 3-D circuit and 2-D circuit into different dice in such a way that they could be optimized separately. To improve the array efficiency of the 3D-array die, its peripheral circuit should be minimized. For example, the voltage-generator could be separated into another die. Accordingly, the present invention discloses a discrete 3D-MV. It comprises at least a 3D-array die and at least a voltage-generator die. The 3D-array die (3-D circuit) is formed in a 3-D space and comprises a plurality of functional levels. The voltage-generator die is formed on a 2-D plane and comprises just a single functional level. Because it is an essential circuit for the 3D-MVto perform basic memory functions, absence of any voltage-generator component makes the 3D-array die per se not a functional memory. Discrete 3D-MVbrings one key benefit: the 3D-array die has a higher array efficiency.

Designed and manufactured separately, the 3D-array die and the voltage-generator die in a discrete 3D-MVcan have substantially different back-end-of-line (BEOL) structures: the voltage-generator die can have much fewer BEOL layers. Although the 3D-array die has a similar wafer cost to the integrated 3D-MVdie, the voltage-generator die has a much lower wafer cost because it can be manufactured using an independent but much less complex BEOL process. Overall, the discrete 3D-MVhas a lower cost than the integrated 3D-MVfor a given storage capacity.

It should be noted that all the drawings are schematic and not drawn to scale. Relative dimensions and proportions of parts of the device structures in the figures have been shown exaggerated or reduced in size for the sake of clarity and convenience in the drawings. The same reference symbols are generally used to refer to corresponding or similar features in the different embodiments.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Those of ordinary skills in the art will realize that the following description of the present invention is illustrative only and is not intended to be in any way limiting. Other embodiments of the invention will readily suggest themselves to such skilled persons from an examination of the within disclosure.

In the present invention, the symbol “/” means a relationship of “and” or “or”. For example, the read/write voltage could be either only the read voltage, or only the write voltage, or both the read voltage and the write voltage. In another example, the address/data could be either only address, or only data, or both address and data.

Referring now toFIGS. 3A-3B, a preferred discrete three-dimensional vertical memory (3D-MV)50is disclosed. It comprises a 3D-array die30(a 3-D circuit) and a voltage-generator die40(a 2-D circuit). The 3D-array die30is formed in a 3-D space and comprises a plurality of functional levels (i.e., memory levels). The voltage-generator die40is formed in a 2-D space and comprises a single functional level. Separating the 3-D circuit and 2-D circuit into discrete dice can help to optimize them separately.

The discrete 3D-MV50ofFIG. 3Ais a memory card. It includes a physical interface54according to a standard for connecting to a variety of hosts. Physical interface54includes individual contacts52a,52b,54a-54dthat connect with corresponding contacts in a host receptacle. The power-supply contact52ais provided to connect to a power-supply contact in the host receptacle. The voltage supplied by the host to power-supply contact52ais referred to as voltage supply VDD. The ground contact52bprovides a ground connection at a voltage VSS. The contacts54a-54dprovide signal connections between the host and the discrete 3D-MV50. The signals represented on the contacts54a-54dinclude address and data, among others. Because they are directly to/from the host, the address and data represented on the contacts54a-54dare logical address and logical data.

The voltage-generator die40receives a voltage supply VDDfrom the power-supply contact52aand provides the 3D-array die30with at least a read/write voltage through a power bus56. The read/write voltage includes at least a read voltage and/or a write voltage other than the voltage supply VDD. In other words, it could be either at least a read voltage VR, or at least a write voltage VW, or both read voltage VRand write voltage VW, with the values of VRand VWdifferent from VDD. In this preferred embodiment, the read/write voltage includes one read voltage VRand two write voltages VW1, VW2. Alternatively, it could include more than one read voltage or more than two write voltages.

FIG. 3Bis a block diagram of the preferred discrete 3D-MV50. The 3D-array die30comprises the 3D-M arrays22aa. . .22ay. . . and their decoders24,24G. The voltage-generator die40is located between the global decoder24G of the 3D-array die30and the physical interface54. It comprises at least a voltage-generator component of the 3D-MV. Different from the integrated 3D-MV, this voltage-generator component is formed on the voltage-generator die40instead of the 3D-array die30. Because it is an essential circuit for the 3D-MVto perform basic memory functions, absence of this voltage-generator component makes the 3D-array die30per se not a functional memory.

The voltage generator of the 3D-MVcould comprise many voltage-generator components. Examples include a band-gap reference generator (precision reference generator)40B, a VRgenerator40R and a charge-pump circuit40W. The VRgenerator40R generates the read voltage VR, while the charge-pump circuit40W generates the write voltage VW(referring to U.S. Pat. No. 6,486,728, “Multi-Stage Charge-pump circuit”, issued to Kleveland on Nov. 26, 2002). More examples of the voltage-generator components are disclosed inFIGS. 7A-7C.

Referring now toFIG. 4, another preferred discrete 3D-MV50is disclosed. This preferred embodiment is used for a high-capacity memory card or a solid-state drive. It comprises a plurality of 3D-array dice30a,30b. . .30w. The voltage-generator40uses the power bus56to provide read/write voltage(s) to all 3D-array dice. The translator die60translates logical address/data from the contacts54a-54dinto physical address/data. The 3D-array dice form two channels: Channel A and Channel B. The internal bus58A on Channel A provides these physical address/data to the 3D-array dice30a,30b. . .30i, while the internal bus58B on Channel B provides these physical address/data to the 3D-array dice30r,30s. . .30w. Although two channels are used in this example, it should be apparent to those skilled in the art that more than two channels may be used.

Referring now toFIG. 5, a cross-sectional view of a preferred 3D-array die30is disclosed. The preferred 3D-array die30is formed in a 3-D space and comprises a plurality of vertical memory strings16X,16Y. Each memory string (e.g.,16Y) comprises a plurality of vertically stacked memory cells (e.g.,8a-8h). These memory cells are coupled by at least a vertical address line. Each memory cell (e.g.,8f) comprises at least a vertical transistor, with a gate6, an information storage layer7and a vertical channel9. An exemplary memory cell is a vertical-NAND cell. Because a vertical-NAND string comprises a large number (from 24 to 256) of vertically stacked memory cells, a 3D-array die30comprises a large number (from 24 to 256) of BEOL layers.

Referring now toFIG. 6, a cross-sectional view of a preferred voltage-generator die40is disclosed. The voltage-generator die40is formed on a 2-D plane and includes a single functional level, i.e., the substrate-circuit level0K′. The substrate-circuit level0K′ comprises substrate transistors0tand substrate interconnects0iB. The substrate transistors are formed in a voltage-generator substrate0B. The substrate interconnects0iB comprise two interconnect layers, i.e., metal layers0M1′-0M2′. Because each substrate interconnect layer (e.g.,0M1′) comprises two BEOL layers, the voltage-generator die40comprises a total of only four BEOL layers.

Designed and manufactured separately, the 3D-array die30and the voltage-generator die40in a discrete 3D-MV50can have substantially different BEOL structures: the voltage-generator die40can have much fewer BEOL layers. Although the 3D-array die30has a similar wafer cost to the integrated 3D-MVdie20V, the voltage-generator die40has a much lower wafer cost because it can be manufactured using an independent but much less complex BEOL process. Overall, the discrete 3D-MV50has a lower cost than the integrated 3D-MV20V for a given storage capacity.

For a conventional two-dimensional memory (2D-M, whose memory cells are arranged on a 2-D plane, e.g., flash memory), although it is possible to form at least a voltage-generator component on a voltage-generator die instead of a 2D-array die, doing so will increase the overall 2D-M cost. This is because the 2D-array die and the voltage-generator die have similar BEOL structures and similar wafer costs. Adding the extra bonding cost, a discrete 2D-M is more expensive than an integrated 2D-M. This is in sharp contrast to the 3D-MV. The 3D-array die30and voltage-generator die40of a discrete 3D-MV50have substantially different BEOL structures. As a result, a discrete 3D-MVis less expensive than an integrated 3D-M.

Referring now toFIGS. 7A-7C, three preferred voltage-generator components are disclosed. The voltage-generator component preferably uses a DC-to-DC converter. It could be a step-up, whose output voltage is higher than the input voltage, or a step-down, whose output voltage is lower than the input voltage. Examples of step-up include charge pump (FIG. 7A) and boost converter (FIG. 7B), and examples of step-down include low dropout (FIG. 7C) and buck converter.

InFIG. 7A, the voltage-generator component includes a charge pump72to provide an output voltage Voutthat is higher than the input voltage Vin. The voltage-generator component may include one or more integrated circuits and also include one or more discrete devices. Charge pump72may generally be formed having a low profile that fits within the physical constraints of low-profile memory cards.

InFIG. 7B, the voltage-generator component is a high frequency boost converter74. It may also be used to generate an output voltage Voutthat is higher than an input voltage Vin. A boost converter may be formed with a low profile inductor so that the profile of the VR/VW-generator is within the limits for a memory card or a solid-state drive.

InFIG. 7C, the voltage-generator component includes a low dropout (LDO)76to provide an output voltage Voutthat is lower than the input voltage Vin. Generally, an LDO uses one or more (in this case, two) capacitors. Thus, the voltage-generator component may be comprised of at least one die and may also include one or more discrete devices.

Referring now toFIG. 8A-8C, several preferred discrete 3D-MVpackages (or, module)60are disclosed. The 3D-MVpackages inFIGS. 8A-8Bare multi-chip package (MCP), while the 3D-MVmodule inFIG. 8Cis a multi-chip module (MCM). These MCP and MCM can be used as a memory card and/or a solid-state drive.

The preferred discrete 3D-MVpackage60ofFIG. 8Acomprises two separate dice: a 3D-array die30and a voltage-generator die40. These dice30,40are vertically stacked on a package substrate63and located inside a package housing61. Bond wires65provide electrical connection between the dice30and40. Here, bond wire65provides a coupling means between the 3D-array die30and the voltage-generator die40. Other exemplary coupling means include solder bump. To ensure data security, the dice30,40are preferably encapsulated into a molding compound67. In this preferred embodiment, the 3D-array die30is vertically stacked above the voltage-generator die40. Alternatively, the voltage-generator die40can be vertically stacked above the 3D-array die30; or, the 3D-array die30can be stacked face-to-face towards the voltage-generator die40; or, the 3D-array die30can be mounted side-by-side with the voltage-generator die40.

The preferred discrete 3D-MVpackage60ofFIG. 8Bcomprises two 3D-array dice30a,30band a voltage-generator die40. These dice30a,30b,40are three separate dice. They are located inside a package housing61. The 3D-array die30ais vertically stacked on the 3D-array die30b, and the 3D-array die30bis vertically stacked on the voltage-generator die40. Bond wires65provide electrical connections between the dice30A,30B, and40.

The preferred discrete 3D-MVmodule60ofFIG. 8Ccomprises a module frame76, which houses two discrete packages, i.e., a 3D-array package72and a voltage-generator package74. The 3D-array package72comprises two 3D-array dice30a,30b, while the voltage-generator package74comprises a voltage-generator die40. The module frame76provides electrical connections between the 3D-array package72and the voltage-generator package74(not drawn in this figure).

While illustrative embodiments have been shown and described, it would be apparent to those skilled in the art that may more modifications than that have been mentioned above are possible without departing from the inventive concepts set forth therein. The invention, therefore, is not to be limited except in the spirit of the appended claims.