Forming sacrificial endpoint layer for deep STI recess

A method is presented for forming a semiconductor structure. The method includes forming a plurality of fins over a substrate, forming one or more shallow isolation trench (STI) structures defining a first region and a second region, forming a liner dielectric and forming spacers adjacent sidewalls of the plurality of fins and adjacent the one or more STI structures. The method further includes filling the one or more STI structures with an oxide layer, and incrementally recessing the oxide layer and the spacers adjacent the plurality of fins in an alternate manner until a proximal end of the second region is detected.

BACKGROUND

Technical Field

The present invention relates generally to semiconductor devices, and more specifically, to forming a sacrificial endpoint layer for deep shallow trench isolation (STI) recess.

Description of the Related Art

A typical semiconductor device in a complementary metal-oxide-semiconductor (CMOS) circuit is formed in a p-well or an n-well in a semiconductor substrate. Since other semiconductor devices are also present in the semiconductor substrate, a given semiconductor device requires electrical isolation from adjacent semiconductor devices. Electrical isolation is provided by isolation structures that employ trenches filled with an insulator material (e.g., shallow trench isolation or “STI” regions). The electrical isolation of a semiconductor device from other devices located in the same well is referred to as “intra-well” isolation. In contrast, the electrical isolation of a semiconductor device from other devices in an adjacent well (typically of the opposite polarity type, but could also be a same polarity type well of a different well bias) is referred to as “inter-well” isolation. In either case, the unintended functionality of parasitic devices needs to be suppressed. This is typically done by placing a dielectric material, such as an STI structure, in the current paths of the elements of the parasitic devices.

SUMMARY

In accordance with an embodiment, a method is provided for forming a semiconductor structure. The method includes forming a plurality of fins over a substrate, forming one or more shallow isolation trench (STI) structures defining a first region and a second region, forming a liner dielectric, and forming spacers adjacent sidewalls of the plurality of fins and adjacent the one or more STI structures. The method further includes filling the one or more STI structures with an oxide layer, and incrementally recessing the oxide layer and the spacers adjacent the plurality of fins in an alternate manner until a proximal end of the second region is detected.

In accordance with an embodiment, a method is provided for forming a semiconductor structure. The method includes forming a plurality of fins over a substrate, forming at least one shallow isolation trench (STI) structure, and forming polysilicon spacers adjacent sidewalls of the plurality of fins and adjacent the at least one STI structure. The method further includes filling the at least one STI structure with an STI oxide and alternately recessing the STI oxide and the polysilicon spacers adjacent the plurality of fins in a stepwise manner until the polysilicon spacers adjacent the plurality of fins are entirely removed.

In accordance with another embodiment, a semiconductor device is provided. The semiconductor device includes a plurality of fins formed over a substrate, one or more shallow isolation trench (STI) structures defining a first region and a second region, a liner dielectric, spacers adjacent sidewalls of the plurality of fins and adjacent the one or more STI structures, and an oxide layer for filling the one or more STI structures. The oxide layer and the spacers adjacent the plurality of fins are incrementally recessed in an alternate manner until a proximal end of the second region is detected.

DETAILED DESCRIPTION

In one or more embodiments, a method includes forming a plurality of fins over a substrate, forming one or more shallow isolation trench (STI) structures defining a first region and a second region, forming a liner dielectric, and forming spacers adjacent sidewalls of the plurality of fins and adjacent the one or more STI structures. The method further includes filling the one or more STI structures with an oxide layer, and incrementally recessing the oxide layer and the spacers adjacent the plurality of fins in an alternate manner until a proximal end of the second region is detected.

In one or more embodiments, a method includes forming a plurality of fins over a substrate, forming at least one shallow isolation trench (STI) structure, and forming polysilicon spacers adjacent sidewalls of the plurality of fins and adjacent the at least one STI structure. The method further includes filling the at least one STI structure with an STI oxide, and alternately recessing the STI oxide and the polysilicon spacers adjacent the plurality of fins in a stepwise manner until the polysilicon spacers adjacent the plurality of fins are entirely removed.

In one or more embodiments, a semiconductor structure includes a plurality of fins formed over a substrate, one or more shallow isolation trench (STI) structures defining a first region and a second region, a liner dielectric, spacers adjacent sidewalls of the plurality of fins and adjacent the one or more STI structures, and an oxide layer for filling the one or more STI structures. The oxide layer and the spacers adjacent the plurality of fins are incrementally recessed in an alternate manner until a proximal end of the second region is detected.

In one or more embodiments, when the STI is recessed to only a deep STI region, polysilicon (sidewall spacers) only exist on sidewalls of the deep trench. Thus, the Si signal changes to a very low level and this signal change can be captured to indicate an end-point of the STI recess process.

In one or more embodiments, the present invention is directed to various methods of forming fins and isolation regions on a FinFET semiconductor device. As will be readily apparent to those skilled in the art upon a complete reading of the present application, the methods described herein may be employed in manufacturing a variety of different devices, including, but not limited to, logic devices, memory devices, etc., and they may be employed with respect to a variety of different technologies, e.g., N-type FinFET devices, P-type FinFET devices, CMOS applications, etc.

In forming integrated circuits, it is necessary to electrically isolate certain device or circuits from one another. This is typically accomplished by forming one or more isolation structures, comprised of an insulating material. In modern-day devices, the isolation regions are typically so-called shallow trench isolation (STI) structures wherein one or more insulating materials are formed in a trench that has been formed in a semiconductor substrate. In the case of FinFET devices, the formation of isolation regions is a bit more complex as there needs to be a relatively deep device isolation region that separates the device, e.g., an N-type FinFET device, from other devices, such as a P-type FinFET device. Additionally, in the case of a multiple fin FinFET device, a shallow isolation region is formed between the adjacent fins of the device. The exemplary embodiments of the present invention describe a method for forming isolation regions by forming sacrificial endpoint spacers to recess the STI to have better process control.

Disclosed herein, in part, are methods of fabricating a semiconductor device having an isolation feature within a fin structure which, for instance, facilitates isolating circuit elements associated with the fin structure. As discussed above, in fabricating integrated circuit (ICs), the desire for reduced component size features and circuit dimensions has led to significant challenges using existing fabricating techniques, including isolation of circuit features being formed on a wafer.

As used herein, “semiconductor device” refers to an intrinsic semiconductor material that has been doped, that is, into which a doping agent has been introduced, giving it different electrical properties than the intrinsic semiconductor. Doping involves adding dopant atoms to an intrinsic semiconductor, which changes the electron and hole carrier concentrations of the intrinsic semiconductor at thermal equilibrium. Dominant carrier concentration in an extrinsic semiconductor determines the conductivity type of the semiconductor.

As used herein, the term “drain” means a doped region in the semiconductor device located at the end of the channel, in which carriers are flowing out of the transistor through the drain.

As used herein, the term “source” is a doped region in the semiconductor device, in which majority carriers are flowing into the channel.

The term “direct contact” or “directly on” means that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediary conducting, insulating or semiconductor layers at the interface of the two elements.

The terms “overlying”, “atop”, “positioned on” or “positioned atop” means that a first element, such as a first structure, is present on a second element, such as a second structure, wherein intervening elements, such as an interface structure can be present between the first element and the second element.

The term “electrically connected” means either directly electrically connected, or indirectly electrically connected, such that intervening elements are present; in an indirect electrical connection, the intervening elements can include inductors and/or transformers.

The term “crystalline material” means any material that is single-crystalline, multi-crystalline, or polycrystalline.

The term “non-crystalline material” means any material that is not crystalline; including any material that is amorphous, nano-crystalline, or micro-crystalline.

The term “intrinsic material” means a semiconductor material which is substantially free of doping atoms, or in which the concentration of dopant atoms is less than 1015atoms/cm3.

As used herein, “p-type” refers to the addition of impurities to an intrinsic semiconductor that creates deficiencies of valence electrons. In a silicon-containing substrate, examples of n-type dopants, i.e., impurities, include but are not limited to: boron, aluminum, gallium and indium.

As used herein, “n-type” refers to the addition of impurities that contributes free electrons to an intrinsic semiconductor. In a silicon containing substrate examples of n-type dopants, i.e., impurities, include but are not limited to antimony, arsenic and phosphorous.

As used herein, an “anisotropic etch process” denotes a material removal process in which the etch rate in the direction normal to the surface to be etched is greater than in the direction parallel to the surface to be etched. The anisotropic etch can include reactive-ion etching (RIE). Other examples of anisotropic etching that can be used include ion beam etching, plasma etching or laser ablation.

As used herein, the term “fin structure” refers to a semiconductor material, which can be employed as the body of a semiconductor device, in which a gate structure is positioned around the fin structure such that charge flows down the channel on the two sidewalls of the fin structure and optionally along the top surface of the fin structure. The fin structures are processed to provide FinFETs. A field effect transistor (FET) is a semiconductor device in which output current, i.e., source-drain current, is controlled by the voltage applied to the gate structure to the channel of a semiconductor device. A finFET is a semiconductor device that positions the channel region of the semiconductor device in a fin structure.

The term “processing” as used herein includes deposition of material or photoresist, patterning, exposure, development, etching, cleaning, stripping, implanting, doping, stressing, layering, and/or removal of the material or photoresist as required in forming a described structure.

Exemplary types of semiconductor devices include planar field effect transistors (FETs), fin-type field effect transistors (FinFETs), nanowire/nanosheet devices, vertical field effect transistors (VFETs), or other devices.

FIG. 1is a cross-sectional view of a semiconductor structure including a silicon nitride (SiN) fin hard mask formed over silicon (Si), in accordance with an embodiment of the present invention.

A semiconductor structure5includes a semiconductor substrate10with a doped bottom source/drain (S/D) layer12deposited over the substrate10. An undoped channel region14is deposited over the bottom S/D layer12. The undoped channel region14is used to form a plurality of fins, as described below. The undoped channel region14can be, e.g., silicon (Si). The bottom source/drain (S/D) layer12can be, e.g., an n-type doped material. A hard mask16is deposited over the undoped channel region14. The hard mask16can be, e.g., a silicon nitride (SiN) hard mask. The hard mask16can be e.g., a fin hard mask for forming fin structures.

In one or more embodiments, the substrate10can be a semiconductor or an insulator with an active surface semiconductor layer. The substrate10can be crystalline, semi-crystalline, microcrystalline, or amorphous. The substrate10can be essentially (i.e., except for contaminants) a single element (e.g., silicon), primarily (i.e., with doping) of a single element, for example, silicon (Si) or germanium (Ge), or the substrate10can include a compound, for example, Al2O3, SiO2, GaAs, SiC, or SiGe. The substrate10can also have multiple material layers, for example, a semiconductor-on-insulator substrate (SeOI), a silicon-on-insulator substrate (SOI), germanium-on-insulator substrate (GeOI), or silicon-germanium-on-insulator substrate (SGOI). The substrate10can also have other layers forming the substrate10, including high-k oxides and/or nitrides. In one or more embodiments, the substrate10can be a silicon wafer. In an embodiment, the substrate10is a single crystal silicon wafer.

FIG. 2is a cross-sectional view of the semiconductor structure ofFIG. 1where a plurality of vertical fins are formed by etching the silicon (Si), in accordance with an embodiment of the present invention.

In various embodiments, the undoped channel region14is etched to form fins18. The hard mask16remains over the fins18after etching the undoped channel region14. The hard mask16can be, e.g., a silicon nitride (SiN) hard mask16. A distal portion of the fins18extends up to the doped S/D layer12. The fins18extend vertically from the substrate10. Stated differently, the fins18are normal to or perpendicular to the substrate10. The fins18can define a distal end15and a proximal end17.

As used herein, a “semiconductor fin” refers to a semiconductor structure including a portion having a shape of a rectangular parallelepiped. The direction along which a semiconductor fin18laterally extends the most is herein referred to as a “lengthwise direction” of the semiconductor fin18. The height of each semiconductor fin18can be in a range from 5 nm to 300 nm, although lesser and greater heights can also be employed. The width of each semiconductor fin18can be in a range from 5 nm to 100 nm, although lesser and greater widths can also be employed. In various embodiments, the fins18can have a width in the range of about 6 nm to about 20 nm, or can have a width in the range of about 8 nm to about 15 nm, or in the range of about 10 nm to about 12 nm. In various embodiments, the fin18can have a height in the range of about 25 nm to about 75 nm, or in the range of about 40 nm to about 50 nm.

Multiple semiconductor fins18can be arranged such that the multiple semiconductor fins18have the same lengthwise direction, and are laterally spaced from each other along a horizontal direction that is perpendicular to the lengthwise direction. In this case, the horizontal direction that is perpendicular to the common lengthwise direction is referred to as a “widthwise direction.” Each semiconductor fin18includes a pair of parallel sidewalls along the lengthwise direction.

In one embodiment, each semiconductor fin18can be formed by lithography and etching. The lithographic step can include forming a photoresist (not shown) atop a substrate including a topmost semiconductor material, exposing the photoresist to a desired pattern of radiation and then developing the exposed photoresist utilizing a conventional resist developer. The pattern within the photoresist is then transferred into the topmost semiconductor material. The etch can include a dry etch process, a chemical wet etch process, or any combination thereof. When a dry etch is used, the dry etch can be a reactive ion etch process, a plasma etch process, ion beam etching or laser ablation. The patterned photoresist material can be removed after transferring the pattern utilizing a conventional stripping process.

In another embodiment of the present application, each semiconductor fin18can be formed utilizing a SIT (sidewall image transfer) process. In a typical SIT process, spacers are formed on sidewall surfaces of a sacrificial mandrel that is formed on a topmost semiconductor material of a substrate. The sacrificial mandrel is removed and the remaining spacers are used as a hard mask to etch the topmost semiconductor material of the substrate. The spacers are then removed after each semiconductor fin18has been formed. In another embodiment, sequential SIT processes can be utilized to form fins with highly scaled fin width and pitches.

In some embodiments, the fins18in the plurality of semiconductor fins can have a fin width between 5 nm and 10 nm. The combination of the fin width and the width of the trough equals, in embodiments, the fin pitch. The fin width and the fin pitch can vary in different areas of a fin array, and can vary from one fin array to another on a semiconductor wafer, according to the design parameters of the integrated circuit that is being made. For example, fins of negatively doped FinFETs can have a different fin size than positively doped FinFETs because of the electrical properties of the materials they are made of.

FIG. 3is a cross-sectional view of the semiconductor structure ofFIG. 2where a deep shallow trench isolation (STI) mask is applied over portions of the plurality of fins and a deep STI recess is formed, in accordance with an embodiment of the present invention.

In various embodiments, a mask20is applied over the plurality of fins18. After the mask20is applied, a recess or trench22is formed between the plurality of fins18. The recess22extends a length “X” from a top surface of the mask20into the substrate10. After formation of the recess22, etching of the mask20takes place. The etching can be, e.g., an RIE etch. The etching removes the entire mask20. Removal of the mask20results in the formation of an STI structure having a first region23and a second region24. The first region extends a distance “A” and the second region extends a distance “B.” The width of the second region24is designated as “W.” The width of the second region24is less than the width of the first region23. The first region23is defined as a region formed between the plurality of fins18, the fins18having a proximal end17and a distal end15. The second region24is defined as a region formed within the substrate10, as well as within the bottom source/drain (S/D) layer12deposited over the substrate10. The second region24can also be referred to as a deep STI region. The second region24is offset from the plurality of fins18. The proximal endpoint25of the second region24is located near or at the distal end15of the fins18.

The block masks can comprise soft and/or hard mask materials and can be formed using deposition, photolithography and etching. In one embodiment, the block mask comprises a photoresist. A photoresist block mask can be produced by applying a photoresist layer, exposing the photoresist layer to a pattern of radiation, and then developing the pattern into the photoresist layer utilizing conventional resist developer. Typically, the block masks have a thickness ranging from 100 nm to 300 nm.

The block mask can comprise soft and/or hard mask materials and can be formed using deposition, photolithography and etching. In one embodiment, the block mask is a hard mask composed of a nitride-containing material, such as silicon nitride. It is noted that it is not intended that the block mask be limited to only silicon nitride, as the composition of the hard mask can include any dielectric material that can be deposited by chemical vapor deposition (CVD) and related methods. Other hard mask compositions for the block mask can include silicon oxides, silicon oxynitrides, silicon carbides, silicon carbonitrides, etc. Spin-on dielectrics can also be utilized as a hard mask material including, but not limited to: silsequioxanes, siloxanes, and boron phosphate silicate glass (BPSG).

In one embodiment, a block mask comprising a hard mask material can be formed by blanket depositing a layer of hard mask material, providing a patterned photoresist atop the layer of hard mask material, and then etching the layer of hard mask material to provide a block mask protecting the plurality of fins. A patterned photoresist can be produced by applying a blanket photoresist layer to the surface of the plurality of fins, exposing the photoresist layer to a pattern of radiation, and then developing the pattern into the photoresist layer utilizing resist developer. Etching of the exposed portion of the block mask can include an etch chemistry for removing the exposed portion of the hard mask material and having a high selectivity to at least the block mask. In one embodiment, the etch process can be an anisotropic etch process, such as reactive ion etch (RIE). In another embodiment, the replacement gate can be formed by utilizing the SIT patterning and etching process described above.

The etching can include a dry etching process such as, for example, reactive ion etching, plasma etching, ion etching or laser ablation. The etching can further include a wet chemical etching process in which one or more chemical etchants are used to remove portions of the blanket layers that are not protected by the patterned photoresist. The patterned photoresist can be removed utilizing an ashing process.

RIE is a form of plasma etching in which during etching the surface to be etched is placed on the RF powered electrode. Moreover, during RIE the surface to be etched takes on a potential that accelerates the etching species extracted from plasma toward the surface, in which the chemical etching reaction is taking place in the direction normal to the surface. Other examples of anisotropic etching that can be used at this point of the present invention include ion beam etching, plasma etching or laser ablation.

As used herein, the term “selective” in reference to a material removal process denotes that the rate of material removal for a first material is greater than the rate of removal for at least another material of the structure to which the material removal process is being applied. For example, in one embodiment, a selective etch can include an etch chemistry that removes a first material selectively to a second material by a ratio of 10:1 or greater, e.g., 100:1 or greater, or 1000:1 or greater.

In various embodiments, the materials and layers can be deposited by physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), or any of the various modifications thereof, for example plasma-enhanced chemical vapor deposition (PECVD), metal-organic chemical vapor deposition (MOCVD), low pressure chemical vapor deposition (LPCVD), electron-beam physical vapor deposition (EB-PVD), and plasma-enhanced atomic layer deposition (PE-ALD). The depositions can be epitaxial processes, and the deposited material can be crystalline. In various embodiments, formation of a layer can be by one or more deposition processes, where, for example, a conformal layer can be formed by a first process (e.g., ALD, PE-ALD, etc.) and a fill can be formed by a second process (e.g., CVD, electrodeposition, PVD, etc.).

FIG. 4is a cross-sectional view of the semiconductor structure ofFIG. 3where a dielectric liner is applied and spacers are formed on sidewalls of the plurality of fins, in accordance with an embodiment of the present invention.

In various embodiments, a dielectric liner26is deposited over the structure. The dielectric liner36can be, e.g., a silicon nitride (SiN) liner. The SiN liner26covers sidewalls of the exposed fins18, as well as sidewalls/top surface of the hard mask16. The SiN liner26is also formed within the deep trench24′. The SiN liner26is a conformal liner that prevents the Si channel and the bottom source/drain (S/D) layer12from oxidation during STI annealing.

In various embodiments, spacers28are formed by, e.g., an RIE etch. The spacers28can be, e.g., a nitride film (i.e., nitride layer26). In an embodiment, the spacers28can be an oxide, for example, silicon oxide (SiO), a nitride, for example, a silicon nitride (SiN), or an oxynitride, for example, silicon oxynitride (SiON). In an embodiment, the spacers28can be, e.g., SiOCN, SiBCN, or similar film types. The spacers28can also be referred to as a non-conducting dielectric layer.

In some exemplary embodiments, the spacers28can include a material that is resistant to some etching processes such as, for example, HF chemical etching or chemical oxide removal etching.

In one or more embodiments, the spacers28can have a thickness in the range of about 3 nm to about 10 nm, or in the range of about 3 nm to about 5 nm.

The spacers28extend to a top portion of the hard mask16formed over the fins18. In other words, the top surface of the spacers28are flush with the hard mask16. The spacers28can have a thickness that is less than a thickness of the fins18and less than a thickness of the hard mask16. The spacers28can have a thickness that is greater than the thickness of the SiN liner26. The spacers28can be polysilicon (or poly-Si) spacers.

There are two types of spacers28that are being formed. Spacers28are formed adjacent the fins18and spacers28are also formed within the trench24′. The spacers28extend along an entire length of the deep trench24′. The spacers28contact the SiN liner26along the entire length of the deep trench24′. After deposition of the SiN liner26and the spacers28, the deep trench24′ now has a with W′.

FIG. 5is a cross-sectional view of the semiconductor device ofFIG. 4where an oxide fill takes place, in accordance with an embodiment of the present invention.

In various embodiments, an oxide gap fill takes place. The ILD oxide30is planarized. The ILD oxide30fills the remaining gap or recess between the fins18. The ILD oxide30extends to a top surface of the hard mask16. In other words, the ILD oxide30can be flush with the nitride layer16. The ILD oxide30also fills the gap or deep recess of the second region24′. Thus, the ILD oxide fill30contacts the spacers28adjacent the fins18, as well as the spacers28within the trench24′.

In various embodiments, the height of the ILD oxide fill30can be reduced by chemical-mechanical polishing (CMP) and/or etching. Therefore, the planarization process can be provided by CMP. Other planarization process can include grinding and polishing.

In one or more embodiments, the ILD oxide30can have a thickness in the range of about 3 nm to about 10 nm, or in the range of about 3 nm to about 5 nm.

The ILD30can be selected from the group consisting of silicon containing materials such as SiO2, Si3N4, SiOxNy, SiC, SiCO, SiCOH, and SiCH compounds, the above-mentioned silicon containing materials with some or all of the Si replaced by Ge, carbon doped oxides, inorganic oxides, inorganic polymers, hybrid polymers, organic polymers such as polyamides or SiLK™, other carbon containing materials, organo-inorganic materials such as spin-on glasses and silsesquioxane-based materials, and diamond-like carbon (DLC), also known as amorphous hydrogenated carbon, α-C:H). Additional choices for the ILD30include any of the aforementioned materials in porous form, or in a form that changes during processing to or from being porous and/or permeable to being non-porous and/or non-permeable.

FIG. 6is a cross-sectional view of the semiconductor device ofFIG. 5where the oxide is selectively etched to expose upper portions of the sidewall spacers of the plurality of fins, in accordance with an embodiment of the present invention.

In various embodiments, the oxide30is selectively etched in an incremental manner (or by an iterative process). This results in the exposure of a top portion29of spacers28adjacent sidewalls of the hard mask16. The oxide30is etched by an amount or distance “B” that results in remaining oxide30′. This is the first step in the etching process. The second step is described below with reference toFIG. 7.

FIG. 7is a cross-sectional view of the semiconductor device ofFIG. 6where the exposed sidewall spacers are etched away to expose the top side surface of the plurality of fins, in accordance with an embodiment of the present invention.

In various embodiments, the top portion29of spacers28adjacent sidewalls of the hard mask16are etched, thus exposing the top sidewalls32of the hard mask16. This is the second step of the process. The first and second steps are repeated continuously until an endpoint is reached. The endpoint is reached when all the oxide30′ and the all the spacers28adjacent the hard mask16and the fins18are completely removed. Thus, when the STI is recessed to only a deep STI region, polysilicon (sidewall spacers) only exist on sidewalls of the deep trench. As a result, the Si signal changes to a very low level and this signal change can be captured to indicate an end-point of the STI recess process. Stated differently, the Si signal from the polysilicon spacers is detected during silicon dry etch. Therefore, the process involves incrementally recessing the oxide layer30′ and the spacers28adjacent the plurality of fins18in an alternate manner until a proximal end of the second region24′ is detected. The endpoint of the second region24′ is designated by proximal endpoint25located near or at the distal end15of the fins18.

FIG. 8is a graph illustrating the continuous incremental recessing of the oxide layer and the sidewall spacers adjacent the plurality of fins in an alternate manner until a proximal end of a region of the deep STI is detected, in accordance with an embodiment of the present invention.

In various embodiments, the STI recess is accomplished by repeatedly executing two steps until an endpoint is detected. In the first step45, the oxide30′ is incrementally etched to expose the sidewall spacers28. In the second step47, the exposed sidewall spacer29is etched away to expose the SiN layer26. This process continuous several times by incrementally and methodically etching or reducing or removing the oxide and the spacers in an alternate manner (or in an iterative manner) until an endpoint is detected that signals the completion of such two-step process. Stated differently, the exemplary embodiments of the present invention alternately recess the STI oxide30′ and the polysilicon spacers28adjacent the plurality of fins18in a stepwise or iterative manner until the polysilicon spacers18adjacent the plurality of fins18are entirely removed.

For example, point40indicates a decline in the Si signal during the second step47. This is shown as a declining slope. Point42indicates the completion of the removal of the exposed polysilicon spacer29for that iteration. When that iteration ends, the process switches back to the first step45to reduce the oxide level by another incremental amount. Once that's accomplished, the process moves back to the second step47to now etch the newly exposed sidewall spacer29, and so forth until the entire oxide30′ is removed and the entire exposed sidewall spacer29adjacent the hard mask16and the fins18is completely removed.

Point44indicates a very low level of the Si signal. This is indicated as a flat line (as opposed to a declining slope). Thus, after the STI is recessed below the fin18, the value at point44is less than or lower than the value at point40. The STI recess rate decreased due to a small size trench when in the deep STI region. At this point of the process, only a few polysilicon liners are exposed in the STI sidewall compared to a large amount of polysilicon liners on the sidewalls of the fins. This is the indication of the endpoint of the two-step process. In other words, the process is notified to end at this point. The process being the etching of the oxide and the sidewall spacers adjacent the fins18. Therefore, the process is triggered to end at endpoint25. This leaves the oxide and sidewall spacers formed within the deep trench (region2) intact, as shown below with reference toFIG. 9.

FIG. 9is a cross-sectional view of the semiconductor device ofFIG. 7where sidewall spacers remain within the deep trench to isolate the plurality of fins, in accordance with an embodiment of the present invention.

In various embodiments, an isolation region50is formed between the plurality of fins18. The isolation region50includes the deep trench (second region) being filled with a SiN liner52, polysilicon spacers54, and oxide56. The oxide56is sandwiched between the spacers54. The spacers54are in contact with or engage the SiN liners52. The width of the isolation region50can be, e.g., less than the width of the fins18. The isolation region50can also be referred to as an isolation pillar. The isolation pillars can be used to isolate sets of fins18. The isolation region50can also be referred to as an isolation trench positioned between first and second sets of fins18. It is noted that the isolation region50or isolation pillar or isolation trench is not in contact with the fins18. The isolation region50can be considered an insulating region.

In some embodiments, the width of the deep isolation region (region2) may also be greater that the width of the shallow isolation region (region1). The absolute value of the final depth and final width of the first and second isolation regions can vary depending upon the particular application. For example, the upper surface width can fall within a range of about 20-100 nm, the final depth can fall within a range of about 30-50 nm or the upper surface width can fall within a range of about 100-1000 nm, and the final depth can fall within a range of about 50-100 nm.

FIG. 10is a block/flow diagram of an exemplary method for forming a sacrificial endpoint spacer to recess STI, in accordance with an embodiment of the present invention.

At block102, a plurality of fins are formed over a substrate.

At block104, one or more shallow isolation trench (STI) structures defining a first region and a second region are formed.

At block106, a liner dielectric is formed.

At block108, spacers are formed adjacent sidewalls of the plurality of fins and adjacent the one or more STI structures.

At block110, the one or more STI structures are filled with an oxide layer.

At block112, the oxide layer and the spacers adjacent the plurality of fins are incrementally recessed in an alternate manner until a proximal end of the second region is detected.

By forming the devices as described herein, a device designer has greater flexibility to tune one or more of the devices so that it is adapted for use with the circuit design under consideration. In short, using the novel methods described herein, the fins can be formed with variations in cross-sectional shape (which is as related to the position of the fin relative to adjacent trenches formed for device isolation regions and the different depth/width of such trenches), all while forming device isolations that have an enhanced capability to electrically isolate adjacent devices. All of this may be accomplished while at the same time the variations in electrical characteristics (i.e., threshold voltage) due to the differences in the cross-sectional configurations of the fins is minimized.

It is to be understood that the present invention will be described in terms of a given illustrative architecture; however, other architectures, structures, substrate materials and process features and steps/blocks can be varied within the scope of the present invention.

Having described preferred embodiments of a method of device fabrication and a semiconductor device thereby fabricated to form a replacement metal gate scheme with a self-alignment gate for a VFET (which are intended to be illustrative and not limiting), it is noted that modifications and variations can be made by persons skilled in the art in light of the above teachings. It is therefore to be understood that changes may be made in the particular embodiments described which are within the scope of the invention as outlined by the appended claims.