Forced pulldown of array read bitlines for generating MUX select signals

An apparatus, a method, and a computer program product are provided for time reduction in an array read access control consisting of a bitcell and a pulldown device outside of the bitcell. To reduce gate delay, this design implements a pulldown device that controls the bitcell readout. A pulldown signal is generated to activate the pulldown device. Therefore, the pulldown signal can control the pulling down of the bitcell readout without a complete read of the data array inside the bitcell. This design reduces gate delay because the dependency upon the gating logic is overridden and the number of stages is reduced.

FIELD OF THE INVENTION

The present invention relates generally to array read access controls, and more particularly, to array read access controls involving the forced pulldown of array readouts from a bitcell.

DESCRIPTION OF THE RELATED ART

Standard bitcells and array read access controls are used in data processing systems to perform the function of accepting written data, storing this data in arrays, reading this data and then transforming the data into decoded select signals. There is a constant search to reduce the time delay involved with producing these decoded select signals. Conventional array read access designs consist of a conventional bitcell with a read port followed by specific gating logic to generate the desired multiplexer (MUX) select signals. After a write is performed the bitcell will store the information as data in an array. Then the bitcell produces a readout of this data and that readout will be gated to produce the desired MUX signals. Any operation that is based upon the read result from the bitcell will require additional clock cycles, which increases the time delay of the circuit. If the gate delay stages are reduced, then the array read timing operation becomes less critical and the devices may be sized to achieve greater reliability and/or lower power.

Referring toFIG. 1of the drawings, reference numeral100generally indicates a conventional bitcell with a read port. The write wordline105is connected to the gates of two n-channel field effect transistors (NFETs)120and125. The write bitline110is connected to the source of NFET120. The drain of NFET120is connected through junction130as an input of inverter135. The output of inverter135is connected to junction140, which is connected to the source of NFET125. The complement of the write bitline115exists at the drain of NFET125. Another inverter145is connected with its input attached to junction140and its output attached to junction130. The two NFETs120and125, and the two inverters in series135and145, create a static memory cell150, which maintains a constant value in the bitcell. When the write wordline105is on, the values on the write bitlines110and115will be passed to the memory cell150, and the memory cell150will hold new values at junctions130and140. Junction140is also connected to the gate of NFET155.

The drain of NFET155is connected to the source of NFET170. The read wordline160is connected to the gate of NFET170. The drain of NFET170is the read bitline165. The NFET170and the NFET155make up the pulldown device175, and both transistors must be activated before the read bitline165will pull down. If NFET155is not activated, then the read bitline165will maintain its precharged state. The source of NFET155is connected to ground180. The pulldown device175allows the signal that has been read to be pulled down as a readout of the read bitline165. At this point the readout of the bitcell can be gated to produce the MUX select signals.

Referring toFIG. 2of the drawings, reference numeral200generally indicates a block diagram depicting the conventional array readout of a standard bitcell followed by signal gating. The bitcell208corresponds toFIG. 1, reference numeral100. The Array Bit Slice205depicts an array of bitcells208as they would appear in a processor. The readout210corresponds to the read bitline165inFIG. 1. This readout signal210is produced by the bitcell with a read port. The readout210is then connected to the specific gating logic220as an input. Gating signals215are also connected to the gating logic220as an input. The desired MUX select signals225are the output of the gating logic220.

These separate steps lead to a time delay that was previously described. Any operation that requires a readout signal from the bitcell will require additional clock cycles. This result forces array read devices to be designed with timing constraints as the primary issue. If timing issues are less significant, then array read devices can be designed to be smaller in area, more reliable and/or more power efficient. Therefore, there is a need for a method and/or apparatus to modify conventional array read access controls to perform faster.

SUMMARY OF THE INVENTION

The present invention provides a method, an apparatus, and a computer program for the reduction of time delay for array read access controls consisting of a bitcell and a pulldown device outside of the bitcell. The pulldown device consists of an nFET transistor that is implemented to pull down a readout from the bitcell. A pulldown signal is generated outside of the array core, and is brought into the array core to activate the pulldown device. Overall, a pulldown of the data array from the bitcell can be accomplished without a complete read of the data array. This reduces the number of stages and the time delay of a data array read. As a result of this time delay reduction, the array read timing operation becomes less critical and the devices may be sized to achieve greater reliability and/or lower power consumption.

DETAILED DESCRIPTION

Referring toFIG. 3of the drawings, the reference numeral300generally depicts a block diagram illustrating the forced pulldown of the global bitline from a conventional bitcell. The bitcell308corresponds to the reference numeral100inFIG. 1. The Array Bit Slice305denotes an array of these bitcells as they would exist in a processor. The readout310of the bitcell is pulled down as the global bitline325by the pulldown device335. The readout310and the global bitline325exist at the same node340. The readout310corresponds to the read bitline165inFIG. 1. The global bitline325denotes the desired MUX select signals. The pulldown device335contains an nFET transistor315. The pulldown signal320, which will be controlled by outside gating logic, is connected to the gate of N-channel field effect transistor (NFET)315. This pulldown signal320will activate NFET315, which pulls down the global bitline325. The drain of NFET315is connected to ground330. The global bitline325is connected to the source of NFET315at node340.

A pulsed clock is used as the bitline pulldown signal320and the read wordline signal160. These two signals should be mutually exclusive but they are not required to be. The best embodiment of this device involves separate pulsed clock signals for the bitline pulldown signal320and the read wordline signal160. An extra clock signal must be shaped and staged along with the read wordline signal160and the precharge signals to resolve timing issues, such as contention, float, and pulsewidth. In an embodiment, there is only one instance of gating logic outside of the array core that controls the pulldown device335. This outside gating logic will be used to produce the pulldown signal320. The physical area of the array core is reduced because the logic gating is outside of the core. The activation of the write wordlines105and the read wordlines160must be mutually exclusive.

The use of certain logic outside of the array core to control the global read bitlines allows the removal of the dependency on a read of the data array. A 5:1 multiplexer has four of the five select signals stored in the array as 1-hot and the remaining, master select signal existing outside of the array. The values of all five selects must be 1-hot when controlling the multiplexer. Previous methods require reading the data from the array and gating them with the master select signal to ensure the 1-hot condition among all five signals. This modified design controls these bitlines with the pulldown device335and the timing dependency on the gating logic can be overridden. Basically, the pulldown device335overrides the bitcell100, and can pull down the bitline regardless of a standard read of the bitcell value. The pulldown device335is controlled by a pulldown signal320that is produced outside of the array core.

As shown inFIG. 3the readout310is no longer followed by the additional logic. The outside gating now controls the global bitline325and there is no additional delay. The end result is a faster circuit with a significant reduction in gate delay. A major advantage of reducing the gate delay is that the read timing operation becomes less critical and the devices may be sized to achieve greater reliability and/or lower power.

Referring toFIG. 4of the drawings, the reference numeral400generally indicates a flow chart illustrating the process of pulling down the global bitline from a conventional bitcell. As shown in step405the pulldown signal320is produced by gating logic outside of the array core. This pulldown signal320controls the pulldown device335. In step410the pulldown signal320is brought into the array core. In step415it is determined whether the pulldown device335is activated. If the pulldown signal320does not activate the pulldown device335, then in step430the global bitline325remains precharged and is not pulled down. If the pulldown signal320does activate the pulldown device335, then the global bitline325is pulled down in step435. Alternatively, the read bitline165can be pulled down by a standard read from the value of the bitcell100also. The pulldown device335overrides the bitcell100, but if the pulldown device335is not activated, then the read bitline165can be pulled down by a standard read of the value of the bitcell.

It is understood that the present invention can take many forms and embodiments. Accordingly, several variations of the present design may be made without departing from the scope of the invention. The capabilities outlined herein allow for the possibility of a variety of programming models. This disclosure should not be read as preferring any particular programming model, but is instead directed to the underlying concepts on which these programming models can be built.