Via configuration for wafer-to-wafer interconnection

A modification to the standard layout of vias used for vertically-stacked wafer bonding is proposed which has been found to improve the interconnect overlay while avoiding the dishing problems associated with the planarization processes used in the creation of conductive posts within the vias. In particular, the pitch, i.e. the spacing between adjacent posts, is intentionally chosen to be different for each wafer. By using different pitches, there is an increase in the probability of overlap of posts on each wafer, even when one wafer is slightly offset with respect to the other (which is possible when aligning one wafer with another in a standard bonding tool). Advantageously, the use of different pitches allows for the use of relatively small diameter (one micron or less) posts while still creating sufficient overlap for the necessary connections.

BACKGROUND

As packaging density in semiconductor devices continues to increase, three-dimensional (3D) wafer-to-wafer stacking has become a viable solution for accommodating an increased number of devices within a specific “footprint” (surface area) of a given package. 3D wafer stacking technology offers a number of potential benefits, including, for example, improved form factors, lower costs, enhanced performance, as well as greater integration through system-on-chip (SoC) solutions. In addition, the 3D technology may provide other functionality to the chip.

One factor in achieving manufacturable and cost-effective 3D wafer configurations relates to providing reliable and repeatable electrical bonding between wafers within the stack. An exemplary approach for providing wafer-to-wafer bonding is defined as “direct bonding”, which can be thought of as using conventional wafer fabrication techniques (including wafer thinning, photolithography masking, via etching and interconnect metallization) to create bond pad areas (“posts”) on each wafer. The wafers are then disposed one on top of another such that the posts face each other. Presuming the posts are properly aligned, the wafers are bonded together, forming both physical attachment and electrical signal path connection between the wafers.

One critical parameter in the direct bond interface (DBI) process is the flatness that can be obtained on an exposed top surface of the wafer within which the metal posts are formed. After the metal is deposited in the vias formed in the wafer, a planarization process is used to even out the upper surface of the wafer and expose a planar array of post surfaces. In most cases, a chemical mechanical polishing (CMP) operation is used to perform this planarization. It is well known, however, that “dishing” (removal of metal below the final surface of the structure) occurs during CMP and is directly proportional to the diameter of the post. That is, the larger the diameter of the post, the wider and deeper the dishing that may result. Obviously, if the dishing is too severe, electrical connection between mating posts is compromised.

While decreasing the diameter of the posts is a reasonable solution to overcome the dishing problem, the use of small diameter posts impacts the ability of conventional wafer bonding tools to align one wafer with another when forming the vertical wafer stack. In other words, the overlay accuracy of the bonding tool ultimately determines the reliability and repeatability of the DBI process.

SUMMARY

One aspect of the present invention relates to a modification to the standard layout of vias used in the mutual bonding of vertically stacked wafers (or integrated circuit die), in order to improve the interconnect overlay while avoiding the dishing problems associated with CMP. The vias formed on each wafer (or die) are separated by a pitch defined for that wafer (die), where the pitches are preferably related by a pitch factor N so that overlap between vias of joining wafers will occur with a given periodicity. The use of different (but related) pitches thus de-couples the overlay problem associated with using small diameter (i.e., sub-micron) vias from the tolerances of conventional bonding tools.

In one embodiment, relatively small diameter posts may be used as bonding sites on each wafer (e.g., diameter on the order of one micron, perhaps less). The use of relatively small posts is less likely to be affected by dishing during a CMP process. In accordance with the present invention, the spacing between adjacent posts (defined as the “pitch”) is intentionally chosen to be different for each wafer. This is in contrast to the prior art, which uses the same pitch spacing on each wafer being bonded. By using different pitches, there is an increase in the probability of overlap of posts on each wafer, even when one wafer is slightly offset with respect to the other (which is possible when aligning one wafer with another in a standard bonding tool).

In one exemplary configuration, the pitches can be related through a function of some integer N, that is, the pitches are inversely proportional to a specific value based on N. In one case, the pitch of posts on a first wafer may be scaled by a value of (N+1) and the pitch of the posts on a second, joining wafer may be scaled by an incrementally different value of (N−1). By relating the two pitches through this common pitch factor N, there will inevitably be one or more locations where overlap between the two sets of posts will occur, provided the minimum diameter D of the posts is at least 2P0/(N2−1), where P0is a nominal pitch value. More generally, Pbotand Ptopcan be related by (N+x), (N−x), where the step value x is greater than zero but less than N. Often, a unit step value of x=1 may be preferred for ease of fabrication.

One particular embodiment of the present invention can be defined as a vertically stacked integrated circuit assembly comprising a first integrated circuit substrate including a first plurality of bond posts, with adjacent bond posts separated by a predetermined first pitch Pbot, and a second integrated circuit substrate including a second plurality of bond posts, with adjacent bond posts of the second plurality of bond posts separated by a predetermined second pitch Ptop, where Ptop≠Pbot. Thus, when the first and second integrated circuit substrates are vertically arranged, the second plurality of bond posts overlaps at least a portion of the first plurality of bond posts. A bond is then utilized to electrically and physically connect the overlapped portions of the first plurality of bond posts and the second plurality of bond posts.

Another particular embodiment of the present invention may take the form of a method of forming an integrated circuit assembly, comprising disposing a first substrate having a first plurality of posts having a first pitch Ptopover a second substrate having a second plurality of posts having a second pitch Pbot, aligning the first and second substrates such that the second plurality of bond posts overlaps at least a portion of the first plurality of bond posts, and attaching the first substrate to the second substrate by bonding the overlapped portions of the first plurality of bond posts with the second plurality of bond posts.

DETAILED DESCRIPTION, WITH EXAMPLES

As will be discussed in detail below, the techniques of the present invention relate to using small-diameter posts for attaching vertically-stacked wafers in a direct bond interconnect (DBI) structure. The posts may be formed to have a diameter on the order of one micron (or less), minimizing dishing problems that arise when polishing or otherwise planarizing a wafer surface after filling the vias with a conductive material (for example, copper). Conventional, larger-sized posts (typically on the order of 10 microns or so), may exhibit areas where too much surface material is removed during planarization, thus impacting the quality of the electrical connection thereafter formed with posts on an overlying wafer.

Inasmuch as typical wafer bonding tools are not equipped to provide micron-level alignment, the use of small-diameter posts has heretofore not been an option. However, it is now determined in accordance with the teachings of the present invention that by using different inter-post spacings (pitch) on each wafer, the ability to guarantee a certain degree of overlap between posts on each wafer is increased. The amount of overlap is provided by using different (but related) pitches for each wafer, thus ensuring that a sufficient electrical connection and physical bond is formed between via arrays on each wafer. Although the following discussion is related to one or more embodiments where a first wafer is bonded to a second wafer, it is to be understood that the principles of the present invention relate generally to electrical interconnections between any two integrated circuit “substrates”. The term “substrate” in this regard includes die, wafers and substrates associated with integrated circuit formation, including “interposer” substrates that are used as an interconnection elements between pairs of circuit-populated substrates or wafers.

FIG. 1illustrates an exemplary wafer10formed to include a plurality of etched vias12, where vias12are utilized to provide an electrical conduction path to metal contacts11formed within wafer10. Well-known fabrication techniques are used to pattern the surface of wafer10and create vias12, where in accordance with the present invention the patterning is used to define both the diameter D1of the vias and a predetermined pitch Pbotbetween the centers of adjacent vias. A following step in the process of creating a direct bond interface (DBI) structure is to fill vias12with a conductive material.FIG. 2illustrates wafer10after this step, where vias12have been filled with a conductive material (e.g., copper) to form a plurality of conductive posts14. Posts14are shown as also being spaced by the predetermined pitch Pbot.

In accordance with various exemplary embodiments of the present invention, each post14is formed to have a relatively small diameter D1, typically on the order of one micron (or even less). Thus, during a post-fill step of planarizing surface S of wafer10, the integrity of the surface of each post is maintained. This is in contrast to prior art DBI configurations that use posts having a diameter on the order of 10 microns, where these larger exposed copper surfaces have been known to be subjected to over-processing (i.e., “dishing”) during planarization processes. It is to be understood, however, that the inventive use of multiple pitches in arranging via arrays is not limited to implementations with small diameter vias and, in fact, may be used in configurations with vias of any given diameter.

FIG. 3illustrates a next step in providing DBI between a pair of wafers. Here, a second wafer20(referred to at times hereafter as a “top” wafer) is disposed over and attached to bottom wafer10. It is to be understood that the terms “top”, “bottom”, “over”, “under” are used only for the sake of convenience in explaining an embodiment of the present invention and are not intended to limit any specific orientation or placement of the various elements.

Continuing with the description of the elements inFIG. 3, second wafer20is shown as processed in a manner similar to wafer10, where a plurality of vias22has been etched in wafer20. A conductive material (e.g., copper) is later deposited to fill vias22and form bond posts24. In accordance with the present invention, and discussed in detail below, vias22(and, therefore, posts24) are formed to exhibit a different pitch than that associated with wafer10. In particular,FIG. 3shows a pitch Ptopbetween adjacent posts24. Both vias22and posts24are preferably formed to exhibit a diameter D2that is essentially equal to the diameter D1exhibited by vias12and bond posts14(where “essentially equal” is used in this case to mean “equal to within 10% to allow for manufacturing tolerances”).

In providing post-to-post attachment, second wafer20is positioned so that the plurality of posts24are disposed over (for example), and attached to, posts14formed within the top surface of first wafer10. As will be discussed in detail below, by virtue of using different (but related) pitches Pbotand Ptopin combination with posts of essentially equal diameters D1and D2, the likelihood for alignment between posts14and posts24is increased, even with the inaccuracies in alignment that are encountered when using conventional bonding tools to attach wafer20to wafer10. The use of these different pitches allows for small diameter vias to be utilized, thus de-coupling the problem of overlaying “small” vias from the given alignment tolerance limitations of conventional bonding tools.

More particularly, an exemplary embodiment of the present invention is based upon defining a pitch factor N that is used to define the relationship between Pbotand Ptop, where the pitch factor N can be thought of as a “shrinkage” factor to be applied against a conventional pitch factor. That is, for a given pitch factor N and a nominal (conventional and predefined) pitch P0, a difference in pitch useful in achieving sufficient overlay can be defined as follows:

Ptop=P0(N+1),andPbot=P0(N-1),
where in this example the pitch for each via array is stepped “one” unit from the pitch factor (i.e., either “up” or “down” from the pitch factor N). With respect to prior art configurations, a “nominal” pitch P0of 20 μm can be considered as typical, used with bond posts having a diameter on the order of 10 μm.

Continuing, the above relation can be rewritten as follows:

Ptop=(N-1N+1)⁢Pbot,
where it is to be understood that the increment of “one up, one down” is exemplary only, and the relation between Ptopand Pbotcan be generally expressed as follows:

Ptop=(N-xN+x)⁢Pbot,
where x is defined as the “pitch step” and may be any positive non-zero value less than N. Indeed, x may be a non-integer value (say, 0.5), where in this case the relationship between Ptopand Pbotwould be “half up, half down”. In another case, x may be somewhat larger than unity, say a value of 5 or 10, as limited, e.g., by the capabilities of the fabrication equipment used to pattern the vias and form the bond posts.

FIG. 4is a diagram of an exemplary layout of vias (or posts) in a linear array form, showing posts14(from first wafer10) and posts24(from second wafer20). In the figure, posts24are seen to “overlay” posts14when second wafer20is positioned over first wafer10. In this particular illustration, posts14and24are of relatively small diameter (with the diameter of posts14being essentially equal to the diameter of posts24) and for the sake of comparison a pair of prior art large-sized posts P1, P2are shown as well. (Posts P1, P2are conventionally formed to extend about 10 microns in both the x and y directions.) The pitch (i.e., separation) between adjacent posts14, Pbot, is shown in this view, as well as pitch Ptopassociated with posts24. As shown inFIG. 4, posts14and24extend along the entire extent of the bonding surface in the x-direction. Inasmuch as a planarization process is utilized to prepare the final surface of the wafer (including the plurality of posts), it is desirable to utilize a layout of posts across the entire extent of the wafer to prevent “local” non-uniformities from interrupting the planarization process.

In this diagram, it is presumed that the center posts14cand24ccompletely overlap each other. As the posts are each spaced by their respective pitches, the overlap between neighboring posts is also shown. In the diagram ofFIG. 4, vias14′ and24′ (to the left of14c,24c), are shown to include overlapped portions. A similar overlapped portion is shown for posts14″,24″.

If it is presumed that center post14con wafer10is aligned with center post24con wafer20, the nearest neighbors from the center posts are thus offset by:

Δ=2⁢P0(N2-1),
where P0is defined as a nominal pitch value used in determining Pbotand Ptop(thus in the present example, Pbot=P0/(N−1), Ptop=P0/(N+1)). In accordance with the present invention, as long as the diameters D1and D2of posts14, and24, respectively, are greater than or equal to Δ, any shift of top wafer20with respect to bottom wafer10will result in at least one electrical connection between posts being maintained.

In one exemplary configuration formed in accordance with an embodiment of the present invention, the post diameters D1and D2(for the posts on wafer10and wafer20, respectively) are both selected to be 1.0 μm, with Pbot=1.8 μm and Ptop=2.2 μm. In this case, simple geometrical arguments show that for any overlay offset between bottom wafer10and top wafer20, the overlap for at least one pair posts cannot be less than (D1(or D2)−Δ/2), which in this case provides a minimum overlap of 0.8 μm, yielding excellent contact regardless of bond overlay.

In one exemplary configuration formed in accordance with an embodiment of the present invention, the post diameter D (for the posts on each wafer) is selected to be 1.0 μm, with Pbot=1.8 μm and Ptop=2.2 μm. In this case, simple geometrical arguments show that for any overlay offset between bottom wafer10and top wafer20, the overlap for at least one pair posts cannot be less than (D−Δ/2), which in this case provides a minimum overlap of 0.8 μm, yielding excellent contact regardless of bond overlay.

It is to be understood that the use of different pitches may extend to a two-dimensional array, as shown inFIG. 5. In this configuration, additional electrical connections may be created between a pair of vertically-stacked wafers by using additional posts fabricated in two dimensions within the “footprint” of a conventional ten-micron-diameter post. As with the configuration ofFIG. 4, the pitch along both the x- and y-directions is different for each wafer, providing the arrangement as shown. Again, in the two-dimensional embodiment the posts are disposed in a layout that covers the surface of the wafer in a manner that allows for a CMP process to maintain planarity of the surface.

Summarizing, the use of via arrays configured to exhibit different pitches represents a significant enhancement to the manufacturability of 3D wafer stacks. By implementing a different pitch on each wafer, relatively small diameter posts may be used (addressing the dishing problems associated with larger-sized posts) without requiring complex, expensive bonding tools to provide sub-micron alignment in joining the wafers. That is, as mentioned above, the use of different pitches de-couples the post overlay criteria from the tolerances of a given bonding tool.

Moreover, while the above embodiments have described the use of multiple pitches in the context of a DBI process, it is to be understood that the inventive approach of using multiple pitches is applicable to any arrangement used to provide wafer-to-wafer attachment in a vertical stack. Some of these other arrangements include, but are not limited to, indium bump-to-bond, metal-to-metal diffusion bonding, adhesive bonding, and the like. Also, as mentioned above, although examples have been described in the context of attaching one “wafer” to another, the same techniques may also be used to create a vertical connection between one integrated circuit die (a smaller portion of a wafer) and another die (i.e., die-to-die vertical stack). The same techniques can even be used for wafer-to-die stacking configuration, including configurations where an interposer element is used to provide connections between other wafers or dies in a stack. In general, any type of vertical stacking and interconnection of integrated circuit “substrates” may utilize the multiple pitch topology as described above.

In a typical IC assembly, certain of the small-diameter posts on a given wafer will be designated to make an electrical connection. Those posts will connect to an underlying patterned metal line within the wafer. For example, the footprint of a prior art post (such as posts P1and P2shown inFIGS. 4 and 5) may be shifted, in implementations of the new approach described here, to an underlying metal layer.

Other posts in the typical IC assembly will be dummy posts that lie outside of any electrical connection. Those posts are included as fill for the CMP planarization process. That is, a full array of posts is useful for maintaining planarity of the entire planarized region.