Integrated circuit memory with built-in self-test (BIST)

An integrated circuit includes a memory core and a built-in self-test (BIST) controller. The memory core has an array of memory cells located at intersections of a plurality of word lines and a plurality of bit line pairs. The BIST controller is coupled to the memory core and has a mission mode and a built-in self-test mode. When in the mission mode, the BIST controller performs read and write accesses using precharge on demand. When in the built-in self-test mode, the BIST controller performs a floating bit line test by draining a voltage on true and complement bit lines of a selected bit line pair and subsequently precharging the true and complement bit lines of the selected bit line pair, before reading or writing data using the true and complement bit lines of the selected bit line pair.

BACKGROUND

Static random-access memory (SRAM) is a type of semiconductor memory that uses bi-stable latching circuitry to store binary bits of data. SRAM cells have the advantage of holding data without requiring a refresh. SRAM is volatile because data is lost when the memory is not powered. In an SRAM array or sub-array, an addressed memory cell is at the intersection of a selected row (identified by a word line) and a selected column (typically identified by a bit line pair having a true bit line and a complement bit line). Bit lines are typically metallic conductors disposed perpendicularly to the word lines and are physically connected to the source/drains of memory cell access transistors and are the conductors through which information is written to and read from the memory cells.

One common use for large SRAM arrays in modern integrated circuit design is as data and tag storage for data processing caches. Cache SRAM arrays are relatively large, such as 32 megabytes, and therefore can take a long time to test. In order to test large SRAM arrays efficiently, circuit designers often add special-purpose testing circuits, known as built-in self-test (BIST) circuits, that can be activated to automatically test the memory cells and access circuitry in the SRAM array and reduce overall test time. A BIST controller typically performs patterns of write and subsequent read cycles to detect failures under a variety of conditions. However, it is difficult even for BIST controllers to test all memory cells under all operating conditions that may result in a failure during normal operation in the field, such as testing of accesses after startup or other transient conditions.

In the following description, the use of the same reference numerals in different drawings indicates similar or identical items. Unless otherwise noted, the word “coupled” and its associated verb forms include both direct connection and indirect electrical connection by means known in the art, and unless otherwise noted any description of direct connection implies alternate embodiments using suitable forms of indirect electrical connection as well. Additionally, the terms remap and migrate, and variations thereof, are utilized interchangeably as a descriptive term for relocating.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

As will be described in detail below, an integrated circuit includes a memory core and a controller. The memory core has an array of memory cells located at intersections of a plurality of word lines and a plurality of bit line pairs. The controller is coupled to the memory core and has a mission mode and a built-in self-test mode. When in the mission mode, the controller performs read and write accesses using precharge on demand. When in the built-in self-test mode, the controller performs a floating bit line test by draining a voltage on true and complement bit lines of a selected bit line pair and subsequently precharging the true and complement bit lines of the selected bit line pair, before reading or writing data using the true and complement bit lines of the selected bit line pair.

An integrated circuit includes a memory core and a controller. The memory core has an array of memory cells located at intersections of a plurality of word lines and a plurality of bit line pairs, wherein the memory core performs precharge-on-demand. The controller is coupled to the memory core, and performs a floating bit line test of the array of memory cells by executing a sequence of draining a voltage on true and complement bit lines of the corresponding bit line pair, precharging the true and complement bit lines, writing a predetermined data bit to a predetermined memory cell using the true and complement bit lines, draining the voltage on the true and complement bit lines, precharging the true and complement bit lines, and reading a result data bit from the predetermined memory cell using the true and complement bit lines. The floating bit line test checks whether the result data bit matches the predetermined data bit.

A method of operating a memory having an array of memory cells located at intersections of a plurality of word lines and a plurality of bit line pairs includes, in a mission mode, performing read and write accesses using precharge on demand. In a built-in self-test mode, floating bit line testing is performed on the array of memory cells by draining a voltage on true and complement bit lines of a selected bit line pair and subsequently precharging the true and complement bit lines of the selected bit line pair, before reading or writing data using the true and complement bit lines of the selected bit line pair.

FIG. 1illustrates in block diagram form a data processor100having various caches using SRAM known in the prior art. Data processor100is a single-chip multi-core processor that includes generally a CPU core complex110, a shared L2 cache120, an L3 cache122, and a main memory controller128. CPU core complex110includes a central processing unit (CPU) core112labeled “CPU0” a level-one (L1) cache114, a CPU core116labeled “CPU1” having an L1 cache118, a shared level-two (L2) cache120, a level-three (L3) cache122, and a main memory controller128.

Shared L2 cache120is a shared cache that has a first processor-side bidirectional port connected to CPU core112over a bidirectional bus, a second processor-side bidirectional port connected to CPU core116over a second bidirectional bus, and a memory-side port. L3 cache122has a processor-side bidirectional port coupled to the memory-side bidirectional port of shared L2 cache120, and a memory-side bidirectional port. Main memory controller128has a processor-side bidirectional port connected to the memory-side bidirectional port of L3 cache130, and a memory side bidirectional port adapted to be connected to a main memory. In the illustrated example, shared L2 cache120is shared between CPU cores112and116, but they could independently utilize separate L2 caches. Furthermore, data processor100could use other L2 cache and L3 cache configurations, and could include multiple cores with shared L2 caches.

In the example ofFIG. 1, L1 caches114and118, shared L2 cache120, and L3 cache122all implement tag and data storage arrays with SRAMs so that in the aggregate, data processor100uses a lot of SRAM memory. Moreover, data processor100is capable of implementing various low-power modes with various power-saving features. For example, data processor100can operate at various power-performance states (P-states), each of which correspond to a separate combination of operational voltage and clock frequency. In addition, the SRAM arrays can implement a feature known as “precharge on demand”. Precharge on demand allows the SRAM array to save power by saving the leakage current that would occur if both bit lines of a complementary but line pair were to be continuously precharged when the SRAM is idle. Instead, the bit lines are only precharged right before read and/or write cycles occur, but not precharged during periods of no activity. The inventors have discovered that known BIST techniques are inadequate to test marginal bit cells that may fail as a memory array that supports precharge on demand is awakened and precharge is re-applied. A further description of this problem will now be described.

FIG. 2illustrates a timing diagram200showing various signals associated with an access to a memory cell in a precharge on demand SRAM array. InFIG. 2the horizontal axis represents time in nanoseconds (ns), and the vertical axis represents the amplitude of various signals in volts. Timing diagram200shows waveforms of various signals of interest, including a waveform210of a clock signal labeled “ACCESS CLOCK”, a waveform220of a control signal labeled “WAKE”, a waveform230of an active-low bit-line precharge signal labeled “BLPCX”, a waveform240of a word line signal labeled “WL”, waveforms250including a waveform250of a bit-line true signal labeled “BLT” and a waveform251of a bit-line complement signal labeled “BLC”, and a waveform of a sense amplifier enable signal labeled “SAEN”. Timing diagram200also shows three time points of interest, labeled “t1”, “t2”, and “t3” corresponding to rising edges of the ACCESS CLOCK signal.

Before t1, the memory array is in a floating bit line mode, labeled “Hi-Z”, and the WAKE signal is low. BLPCX is inactive at a logic high voltage, and WL is inactive at a logic low. During long periods between accesses, in which the bit lines are floating, the voltages on BLT and BLC can float to low voltages due to leakage. These periods can be on the order of tens to hundreds of nanoseconds, but is data dependent and can be even longer depending on the pattern of ones and zeros stored in the memory cells of the column. In particular, the inventors have discovered that the low voltages can be approximately 200 millivolts (mV). The bit line signals, BLT and BLC, are at a low voltage since the lapse of time between the last precharge cycle has caused both voltages to slowly discharge to a level slightly above the ground power supply voltage, for example about 200 millivolts (mV).

Between t1and t2, the memory array is in a Wake mode. The WAKE signal transitions to an active state at a logic high voltage. The rising edge of the WAKE signal causes precharge signal BLPCX to become active at a logic low. The falling edge of the BLPCX signal in turn causes the bit line precharge circuit to become active and to pull the BLT and BLC signals slowly toward a logic high voltage. In the example shown inFIG. 2, the memory array has a defect such that one bit line signal rises more slowly than the other bit line signal such that the other bit line signal fails to fully precharge to a power supply voltage labeled “VDD”, resulting in a difference in voltage between the two bit lines at time t2.

Between t2and t3, the memory array is in a Read/Write mode. In particular,FIG. 2shows a read cycle. The BLPCX signal is about to transition to an inactive state coincident with the rising edge of the ACCESS CLOCK around time t2. The WL signal is also activated according to the decoded row address signal to start the read access, and the WAKE signal is deactivated at a logic low voltage. In response to the rising edge of the WL signal, the accessed memory cell starts to provide a differential voltage on the bit lines according to the state of the memory cell. In this example, the state of the memory cell is a “1”, which would be indicated by a positive voltage differential between the BLT and BLC signals.

However, because the memory cell has a defect, it provides an insufficient differential voltage between BLT and BLC. During the second half of the Read/Write mode, the SAEN signal is activated, causing the bit line sense amplifier to attempt to resolve the differential voltage between BLT and BLC. Because of the insufficient differential voltage, the bit line sense amplifier is incapable of correctly discriminating the state of the memory cell, causing the SRAM array to return incorrect data.

This failure mode is difficult to detect through normal built-in self-test (BIST) routines because the precharge operation is never stressed during normal BIST operation, but only during the first access of the SRAM memory after powerup because the BLT and BLC pairs are fully discharged to the level slightly above ground. The deep discharge of the BLT and BLC signals that may be encountered during precharge on demand may take many ACCESS CLOCK cycles. To test the entire memory array containing, for example 32 MB of data, the discharge period would have to be alternated with read and write cycles for at least every word line of the array and for both data states. The result would be in inordinate amount of test time that would make this failure mechanism virtually impossible to test.

The inventors have discovered that this problem can be overcome using a new technique implemented by a BIST controller. An integrated circuit subject to this problem has a memory core having an array of memory cells located at intersections of a plurality of word lines and a plurality of bit line pairs, and a controller connected to the memory core. The controller has a mission mode, i.e. a normal read and write operation mode, and a built-in self-test mode. In the mission mode, the controller performs read and write accesses using the precharge on demand feature. In the built-in self-test mode, the controller performs a floating bit line test by draining a voltage on true and complement bit lines of a selected bit line pair and subsequently precharging the true and complement bit lines of the selected bit line pair, before reading or writing data using the true and complement bit lines of the selected bit line pair. The memory core uses a new Drain cycle, which is a special cycle in which the voltages on the bit lines (e.g. BLT and BLC) are discharged as they would be after a long period after precharge is removed. Next, the memory cells are precharged in a Wake cycle. Then the memory cells are written to or read from. Thus instead of waiting long periods of time before the memory cell precharge would naturally decay, the special Drain cycle allows the controller to simulate the same conditions of a long delay and test the memory cells under this condition by configuring the write drive to pull both bit lines low.

An SRAM array capable of executing this floating bit line test using a BIST controller will now be described.

FIG. 3illustrates in partial block diagram and partial schematic form a portion of an SRAM300with a BIST mode according to some embodiments. SRAM300includes generally a memory core305and a mission mode and BIST controller380.

Memory core305includes an array310of memory cells, a row decoder and word line driver320, a write driver330, a write column select circuit340, a bit line precharge circuit350, a read column select circuit360, and a read sense amplifier370.

Array310is an array of M columns and N rows of memory cells including a representative ithcolumn with a true bit line311conducting signal BLT, a complement bit line312conducting signal BLC, and exemplary memory cells313,314, and315. Each of exemplary memory cells313,314, and315has a first input/output terminals connected to true bit line311, a second input/output terminal connected to complement bit line312, and a select terminal connected to a corresponding word line.

Row decoder and word line driver320has an input for receiving a row address, and outputs for providing word line signals to array310on corresponding word lines. As shown inFIG. 3, row decoder and word line driver320provides word line signals to N word lines, including representative word lines321,322, and323that conduct corresponding word line signals labeled “WL[0]”, “WL[1]”, and “WL[N−1]”.

Write driver330has a first input for receiving a write data signal labeled “WD[j]”, a second input for receiving a signal labeled “DRAIN”, and outputs providing signals labeled “WDT[j]” and “WDC[j]”, respectively.

Write column select circuit340is associated with the ithcolumn and is a circuit that selectively multiplexes the outputs of write driver330onto the associated column, and as shown inFIG. 3, includes transistors341and342to selectively connect the output of write driver330to the column of memory cells shown inFIG. 3. Transistor341is an N-channel MOS transistor having a first source/drain terminal connected to a corresponding output of write driver330for receiving the WDT[j] signal, a gate for receiving one of a set of write column select signals labeled “WRCS[k−1:0]” that multiplexes the output of write driver330onto a selected one of k columns, and a second source/drain terminal connected to bit line311in array310. Transistor342is an N-channel MOS transistor having a first source/drain terminal connected to a corresponding output of write driver330, a gate for receiving the ithone of the WRCS[k−1:0] signals, and a second source/drain terminal connected to complement bit line312in array310. Memory300includes other circuitry, not shown inFIG. 3, to selectively connect the WDT[j] and WDC[j] signals to one of k columns.

Bit line precharge circuit350is associated with the ithcolumn and includes transistors351,352, and353. Transistor351is a P-channel MOS transistor having a source connected to the positive power supply voltage terminal, a gate for receiving bit line precharge signal BLPCX, and a drain connected to true bit line311. Transistor352is a P-channel MOS transistor having a source connected to the positive power supply voltage terminal, a gate for receiving bit line precharge signal BLPCX, and a drain connected to complement bit line312. Transistor353is a P-channel MOS transistor having a first source/drain terminal connected to true bit line311, a gate for receiving bit line precharge signal BLPCX, and a drain/source connected to complement bit line312.

Read column select circuit360is associated with the ithcolumn and is a circuit that selectively de-multiplexes that de-multiplexes the selected one of k columns onto read column lines labeled “RDT[j]” and RDC[j]”, respectively, and as shown inFIG. 3, includes transistors361and362. Transistor361is a P-channel MOS transistor having a first source/drain terminal connected to true bit line311, a gate for receiving an ithone of a set of read column select signals labeled “RDCS[k−1:0]”, and a second drain/source terminal for providing the RDT[j] signal. Transistor362is a P-channel MOS transistor having a first source/drain terminal connected to complement bit line312, a gate for receiving the ithone of the RDCS[k−1:0] signals, and a second drain/source terminal for providing the RDC[j] signal.

Read sense amplifier and latch370has a first input connected to the second source/drain terminal of transistor361for receiving the RDT[j] signal, a second input connected to the second source/drain terminal of transistor362for receiving the RDC[j] signal, a control input for receiving a signal labeled “SAEN”, and an output for providing a signal labeled “READ DATA[j]”.

Mission mode and BIST controller380has inputs for receiving signals labeled “ADDRESS”, “DATA” and “R/W” from, e.g., a cache controller, a clock input for receiving the ACCESS CLOCK, a control input for receiving a signal labeled “BIST_EN”, outputs for providing corresponding write data signals to each write driver such as exemplary write data signal WD[j] to write driver330, the DRAIN signal to each write driver such as write driver330, a corresponding write column select signal of a group of column select signals labeled “WRCS[k−1:0]” to each write column select circuit such as exemplary write column select circuit340, the ROW ADDRESS to row decoder and word line driver320, the BLPCX signal to each bit line precharge circuit such as bit line precharge circuit350, a corresponding read column select signal to each read column select circuit such as exemplary read column select circuit360, a corresponding sense amplifier enable signal to each sense amplifier such as the SAEN signal to sense amplifier370, and an input for receiving a read data signal from each read sense amplifier such as read data signal READ DATA[j] from read sense amplifier and output latch370.

In operation, SRAM300performs read and write cycles during a mission mode (i.e., normal operation), and BIST operations during a BIST mode using a combined mission mode and BIST controller380.

In the mission mode, signal BIST_EN is inactive and BIST mode is disabled. Mission mode and BIST controller380receives read and write accesses from, e.g., a cache controller. The cache controller provides the ADDRESS signal to indicate the address of the access and the R/W signal in a logic state that corresponds to the type of access. Mission mode and BIST controller380may receive other control signals that are not important to understanding the relevant operation of SRAM300and that are not shown inFIG. 3.

SRAM300implements precharge on demand. Thus, when SRAM300is not being accessed, the BLPCX signal remains high. In response to an access, mission mode and BIST controller380activates the WAKE signal, which causes it to drive the BLPCX signal low, precharging all bit lines in array310.

In the BIST mode, signal BIST_EN is active and BIST mode is enabled. Mission mode and BIST controller380autonomously generates test sequences to detect the presence of any failures in array310or in the related access circuitry, including write driver330, write column select circuit340, bit line precharge circuit350, read column select circuit360, and read sense amplifier and latch370. It performs the BIST operations using at least two kinds of tests.

Mission mode and BIST controller380performs background testing of array310by ensuring that all memory cells can be written to both a “1” and a “0” state and then read in the correct logic state. Since SRAM300is a precharge-on-demand memory, it precharges array310before performing a series of write and subsequent read operations.

Mission mode and BIST controller380performs floating bit line testing of array310by determining whether all memory cells can operate properly starting from a fully-discharged state. As noted above, in the fully-discharged state, true and complement bit lines will discharge to around 200 mV. However to execute the floating bit line testing, mission mode and BIST controller380further discharges both the true and complement bit lines to ground using a drain cycle. In this way, it provides a robust testing that detects potential failures before they occur during mission mode and cause an actual loss of data or program failure.

Pseudo-code segment [1] indicates an operation including a write of an initial data value such as a binary “0” to a selected memory location, followed by a read of the same data value from the selected location. This sequence ensures that the memory cell is basically functional and sets the background data.

Pseudo-code segment [2] indicates an operation including a DRAIN cycle, followed by a programmable number of no-operation (“noop”) cycles during which the array will wake up, that is precharge the bit lines, followed by a write of a subsequent data value different from the initial data value (such as a binary “1”), followed by an immediate read of the data value (to determine whether the write cycle failed). This sequence is followed by another DRAIN cycle, followed by the programmable number of no-operation cycles during which the array will wake up, followed by a read of the data value. If the first read operation passes but the second read operation fails, then mission mode and BIST controller380detects a floating bit line test failure.

Pseudo-code segment [3] does the opposite of pseudo-code segment [2] and indicates an operation including a DRAIN cycle, followed by the programmable number of no-operation cycles, followed by a write of the initial data value such as a binary “0”, followed by an immediate read of the data value (to determine whether the write cycle failed). This sequence is followed by another DRAIN cycle, followed by the programmable number of no-operation cycles, followed by a read of the data value. If the first read operation passes but the second read operation fails, then mission mode and BIST controller380detects a floating bit line test failure.

In this way, mission mode and BIST controller380tests both basic write and read functionality, as well as memory cell and circuit weaknesses that could cause failures during operation because of the precharge on demand feature. Thus, memory300has improved test coverage compared to other known memories that use precharge on demand.

SRAM300could perform a variety of remedial actions upon detection of a failure. For example, it could cause a redundant row to be substituted for a row in which a failure is detected. It could also cause an entry to be made in a replacement cache, in which the replacement cache dynamically substitutes a redundant row for the row in which the failure occurred when an access to the row is detected. It could also just report the failure to system management firmware, which would them perform a remedial action as appropriate. If the BIST operation occurred at manufacturing test, it could also cause the integrated circuit to be rejected.

FIG. 4illustrates in schematic form write driver330ofFIG. 3according to some embodiments. Write driver330includes generally a predriver410, an inverting driver420, a predriver430, and an inverting driver440. Predriver410includes a NOR gate411and an inverter412. NOR gate411has a first input for receiving a write data signal labeled “WD[j]”, a second input for receiving the DRAIN signal, and an output. Inverter412has an input connected to the output of NOR gate411, and an output. Inverting driver420includes transistors421and422. Transistor421is a P-channel MOS transistor having a source connected to a positive power supply voltage terminal, a gate connected to the output of inverter412, and a drain for providing the WDC[j] signal. Transistor422is an N-channel MOS transistor having a drain connected to the drain of transistor421, a gate connected to the output of inverter412, and a source connected to ground. Predriver430includes an inverter431a NOR gate432, and an inverter433. Inverter431has an input terminal for receiving signal WD[j], and an output. NOR gate432has a first input connected to the output of inverter431, a second input for receiving the DRAIN signal, and an output. Inverter433has an input connected to the output of NOR gate432, and an output. Inverting driver440includes transistors441and442. Transistor441is a P-channel MOS transistor having a source connected to the positive power supply voltage terminal, a gate connected to the output of inverter433, and a drain for providing the WDT[j] signal. Transistor442is an N-channel MOS transistor having a drain connected to the drain of transistor441, a gate connected to the output of inverter433, and a source connected to ground.

In operation, when the Drain signal is inactive (DRAIN=0), the logic low of the DRAIN signal causes NOR gates411and432to invert the voltages on their inputs. NOR gate411provides the complement of the WD[j] signal on its output, which is then twice inverted by inverter412and driver420to provide the complement of the WD[j] signal on the output of inverting driver420. NOR gate432provides the WD[j] signal on its output due to the presence of inverter431, which is then twice inverted by inverter433and driver440to provide the WD[j] signal on the output of inverting driver440. Thus, if WD[j]=0, then BLT=1 and BLC=0, and if WD[j]=1, then BLT=0 and BLC=1.

During a Drain cycle (DRAIN=1), the logic high of the DRAIN signal forces the outputs of NOR gates411and432to be a logic low. Inverters412and433provide a logic high on their outputs in response to the logic lows on their inputs. Drivers420and440are inverting drivers that provide both the WDT[j] and WDC[j] signals at logic low voltages in response to the logic high voltages on their inputs. In this way, write driver330discharges the voltages on both WDT[j] and WDC[j] to ground during the Drain cycle.

Thus, mission mode and BIST controller380ofFIG. 3leverages the existing word line drivers to quickly discharge both the true and complement bit lines of each bit line pair during Drain cycle with just a small increase in circuit area, i.e. by changing pre-existing inverters into NOR gates. The inventors believe that this can be accomplished for more contemporary CMOS write drivers within the pitch of the associated columns of memory cells, thus not growing the size of the array.

In some embodiments, transistors422and442can be connected, selectively or always, to a voltage below ground to support boosted word lines. This operation does not impact the new Drain cycle.

FIG. 5illustrates a timing diagram500of a floating bit line test performed by SRAM300ofFIG. 3according to some embodiments. InFIG. 5the horizontal axis represents time in ns, and the vertical axis represents the amplitude of various signals in volts. Timing diagram500shows waveforms of various signals of interest, including a waveform510of the ACCESS CLOCK signal, a waveform520of the DRAIN signal, a waveform530of the WAKE signal, a waveform540of the WRCS signal, a waveform550of the BLPCX signal, a waveform560of the WL signal, and waveforms570including a waveform571of the BLT signal and a waveform572of the BLC signal. Timing diagram500also shows six time points of interest, labeled “t1”, “t2”, “t3”, “t4”, “t5”, and “t6” corresponding to rising edges of the ACCESS CLOCK signal and defining different cycles of the test.

Before t1, SRAM300is not being accessed, and the bit lines are not being precharged and are floating in the Hi-Z state. Timing diagram500shows that both bit lines have discharged because of the lapse of time since the last precharge cycle, and the voltages on both the BLT signal and the BLC signal have discharged to approximately 200 mV. Each of the WAKE and WL signals is inactive at a logic low, and the BLPCX signal is inactive at a logic high.

Prior to t1, mission mode and BIST controller380activates the DRAIN signal in preparation for a Drain cycle, which occurs between t1and t2. During the Drain cycle, mission mode and BIST controller380activates the WRCS signal, causing write driver330to drive both BLT and BLC to a low voltage, substantially all the way to ground. The low voltage ensures that it is testing the worst-case starting condition by lowering the voltage on the BLT and BLC signals by approximately 200 mV for extra margin. Mission mode and BIST controller380subsequently de-activates the DRAIN signal.

Between t2and t3, SRAM300provides one Wake cycle, optionally followed by one or more no-operation (Noop) cycles that would ensure that the WAKE signal setup time to the access clock is sufficient. Mission mode and BIST controller380activates the WAKE signal internally, which causes it to activate the BLPCX signal at a logic low to enable the bit line precharge circuits of all columns in SRAM300. The falling edge of the BLPCX signal in turn causes the bit line precharge circuits of all columns in SRAM300to become active and to pull the BLT and BLC signals to a logic high voltage. In the example shown inFIG. 5, the memory cell does not have a defect such that both the BLT and BLC signals rise rapidly and reach a voltage of approximately the power supply voltage VDD.

Between t3and t4, mission mode and BIST controller380performs a Write cycle. It deactivates the BLPCX signal at a logic high shortly after the rising edge of the ACCESS CLOCK transitions high at time t3. It also activates the WL signal according to the decoded row address signal and the WRCS signal according to the decoded column address to start a write access. Coincident with the rising edge of the WL signal, write driver330drives the voltages on the bit lines according to the state of the data bit to be written to the accessed memory cell. In this example, the data bit is a “0”, which is indicated by a positive voltage differential between the BLT and BLC signals.

Prior to t4, mission mode and BIST controller380activates the DRAIN signal in preparation for a Drain cycle, which occurs between t4and t5. During the Drain cycle, mission mode and BIST controller380activates the WRCS signal, causing write driver330to drive both BLT and BLC to a low voltage, substantially all the way to ground. The low voltage ensures that it is testing the worst-case starting condition by lowering the voltage on the BLT and BLC signals by approximately 200 mV for extra margin. Mission mode and BIST controller380subsequently de-activates the WRCS and DRAIN signals.

Between t5and t6, SRAM300again provides one Wake cycle, optionally followed by Noop cycles that would ensure that the WAKE signal setup time to the access clock is sufficient. Mission mode and BIST controller380activates the WAKE signal internally, which causes it to activate the BLPCX signal at a logic low to enable the bit line precharge circuits of all columns in SRAM300. The falling edge of the BLPCX signal in turn causes the bit line precharge circuits of all columns in SRAM300to become active and to pull the BLT and BLC signals to a logic high voltage. In the example shown inFIG. 5, the memory cell does not have a defect such that both the BLT and BLC signals rise rapidly and reach a voltage of approximately the power supply voltage VDD.

After t6, mission mode and BIST controller380performs a Read cycle. It deactivates the BLPCX signal at a logic high shortly after the rising edge of the ACCESS CLOCK transitions high at time t6. It also activates the WL signal according to a decoded row address signal and the RDCS signal according to the decoded column address to start a read access. Coincident with the rising edge of the WL signal, mission mode and BIST controller380activates the RDCS[k−1] and SAEN signals for the selected column or columns (not shown inFIG. 5), and the accessed memory cell drives a differential voltage on the BLT and BLC signals according to their logic states. As shown inFIG. 5, the accessed memory cell now provides a sufficient differential voltage between the BLT and BLC signals for read sense amplifier and latch370to sense the correct voltage. However, mission mode and BIST controller380has detected this condition without waiting a large number of cycles, making floating bit line testing of the entire array feasible.

SRAM300or any portions thereof may be described or represented by a computer accessible data structure in the form of a database or other data structure which can be read by a program and used, directly or indirectly, to fabricate integrated circuits. For example, this data structure may be a behavioral-level description or register-transfer level (RTL) description of the hardware functionality in a high level design language (HDL) such as Verilog or VHDL. The description may be read by a synthesis tool which may synthesize the description to produce a netlist including a list of gates from a synthesis library. The netlist includes a set of gates that also represent the functionality of the hardware including integrated circuits. The netlist may then be placed and routed to produce a data set describing geometric shapes to be applied to masks. The masks may then be used in various semiconductor fabrication steps to produce the integrated circuits. Alternatively, the database on the computer accessible storage medium may be the netlist (with or without the synthesis library) or the data set, as desired, or Graphic Data System (GDS) II data.

While particular embodiments have been described, various modifications to these embodiments will be apparent to those skilled in the art. For example, floating bit line testing was described above with reference to testing a single memory cell in a single column; various embodiments of the mission mode and BIST controller will test many memory cells from respective columns in parallel. In the exemplary embodiments, the mission mode controller and BIST controller were combined into a single controller, but in other embodiments, they can be separated in different circuits. The BIST controller can performs floating bit line testing along with other types of testing, such as data-dependent testing by writing certain patterns of data to the memory array, in which reads or writes of certain data patterns in columns may induce failures in adjacent columns. These additional forms of memory testing are well known in the art and therefore have not been described in detail. An SRAM with floating bit line testing as described herein can be used in a variety of types of integrated circuits, including microprocessors, microcontrollers, digital signal processors (DSPs), application-specific integrated circuits (ASICs), single-chip SRAMs, and the like. The BIST operations can be performed at a variety of times during the useful life of the integrated circuit, including probe testing, final testing, during operation in the field, in the laboratory during failure analysis, and the like.

Accordingly, it is intended by the appended claims to cover all modifications of the disclosed embodiments that fall within the scope of the disclosed embodiments.