Method and apparatus for pulse frequency modulation with discontinuous voltage sensing

Exemplary embodiments may include a method of applying a charging pulse to an output capacitor, detecting satisfaction of a charging threshold, ending the charging pulse in response to the detecting the satisfaction of the charging threshold, and discharging the sampling capacitor in response to the detecting the satisfaction of the charging threshold. In some embodiments, once a sampling capacitor voltage drops below a discharging threshold, a charging pulse is applied. Exemplary embodiments may also include an apparatus with a controller coupled to an input node, a timer coupled to the controller, an inductive charger coupled to the controller, to an input node, and to an output node, and a sensor coupled to the controller and the output node. Exemplary embodiments may further include an apparatus where a sensor with a sampling capacitor has a first terminal coupled to the output node and a second terminal coupled to the controller and the inductive charger.

TECHNICAL FIELD

The present embodiments relate generally to electrical power supplies, and more particularly to a method and apparatus for pulse frequency modulation with discontinuous voltage sensing.

BACKGROUND

DC-DC converters sometimes use discontinuous output voltage sensing. Examples include “high side” buck and “primary sensing” flyback topologies. These topologies can be used with universal AC input voltage (e.g., 85V AC to 265V AC) where low “standby” and “no load” input power consumption (PIN,min) may be regulated and mandated by national and international standards. Pulse frequency modulation (“PFM”) in systems using continuous output voltage sensing can demonstrate desirable efficiency under light electrical load. A light-load efficiency may enable low minimum input power (“PIN,min”) for more efficient low power or “standby” modes for electrical or electronic devices. However, discontinuous VOUT sensing impacts usage of PFM operation, because PFM systems compatible with continuous VOUT sensing are not compatible with discontinuous VOUT sensing. Two types of parts and configurations are conventionally available. First, parts that can achieve low PIN must operate with large COUT (optimized for low PIN only). Second, parts that cannot achieve low PIN while in operation use small COUT (optimized for low total BOM cost only). Thus, there exists a need for achieving, in discontinuous output voltage sensing DC-DC converters, light load efficiency associated with continuous output voltage systems with PFM.

SUMMARY

The present embodiments relate to methods and apparatuses for controlling DC-DC converters, for example a PFM control method for DC-DC regulators using discontinuous VOUT sensing. Present embodiments relate to pulse frequency modulation control for DC-DC regulators using discontinuous output voltage sensing, where input power in “standby” and “no load” modes can be adjusted or adjustably set by varying characteristics of various electrical components. Various electrical components include, but are not limited to, capacitors, resistors, inductors, AND gates, OR gates, NOT gates, amplifiers, operational amplifiers, comparators, transistors, and the like.

Exemplary embodiments may include a method of applying a charging pulse to an output capacitor, detecting satisfaction of a charging threshold, ending the charging pulse in response to the detecting the satisfaction of the charging threshold, and discharging the sampling capacitor in response to the detecting the satisfaction of the charging threshold. Exemplary embodiments may also include an apparatus with a controller coupled to an input node, a timer coupled to the controller, an inductive charger coupled to the controller, to an input node, and to an output node, and a sensor coupled to the controller and the output node. Exemplary embodiments may further include an apparatus where a sensor with a sampling capacitor has a first terminal coupled to the output node and a second terminal coupled to the controller and the inductive charger.

DETAILED DESCRIPTION

The present embodiments will now be described in detail with reference to the drawings, which are provided as illustrative examples of the embodiments so as to enable those skilled in the art to practice the embodiments and alternatives apparent to those skilled in the art. Notably, the figures and examples below are not meant to limit the scope of the present embodiments to a single embodiment, but other embodiments are possible by way of interchange of some or all of the described or illustrated elements. Moreover, where certain elements of the present embodiments can be partially or fully implemented using known components, only those portions of such known components that are necessary for an understanding of the present embodiments will be described, and detailed descriptions of other portions of such known components will be omitted so as not to obscure the present embodiments. Embodiments described as being implemented in software should not be limited thereto, but can include embodiments implemented in hardware, or combinations of software and hardware, and vice-versa, as will be apparent to those skilled in the art, unless otherwise specified herein. In the present specification, an embodiment showing a singular component should not be considered limiting; rather, the present disclosure is intended to encompass other embodiments including a plurality of the same component, and vice-versa, unless explicitly stated otherwise herein. Moreover, applicants do not intend for any term in the specification or claims to be ascribed an uncommon or special meaning unless explicitly set forth as such. Further, the present embodiments encompass present and future known equivalents to the known components referred to herein by way of illustration.

FIG. 1illustrates an exemplary system in accordance with present embodiments. As illustrated inFIG. 1, an exemplary system100includes an input102, a load104, a controller110, a timer112, a sensor114, and a charger116.

The input102may comprise a source of electrical power, voltage, current, or the like for supplying power to the system100. In some embodiments, the input102includes, but is not limited to rectified 120 V AC power, rectified 220V-240V AC power, regulated power, unregulated power, or the like. In some embodiments, the input102may comprise a wired power connection, a wireless direct contact power connection, a wireless and contactless power connection, the like, or any power connection as is known or may become known.

The load104may comprise one or more electrical, electronic, electromechanical, electrochemical, or like devices or systems for receiving power, voltage, current, or the like from the charger116to perform one or more actions. In some embodiments, the load includes at least one battery, electronic display, electronic computer, electronic input device, electromechanical input device, electronic output device, electromechanical output device or the like. Examples of these devices include notebook computers, desktop computers, tablets, smartphones, printers, scanners, telephony endpoints, videoconferencing endpoints, keyboards, mice, trackpads, gaming peripherals, monitors, televisions, and the like. In some embodiments, the load104comprises one or more devices that are partially or fully separable from system100. In some embodiments, the load104comprises one or more devices that are partially or fully integrated into system100.

The controller110may comprise one or more logic devices for controlling operation of the charger. In some embodiments, the controller comprises one or more electrical components, general purpose electronic components, programmable electronic components, reprogrammable electronic components, or the like.

The timer112may comprise one or more electrical, electronic, electromechanical, electrochemical, or like devices or systems for measuring or indicating progress or expiration of a particular time period, time range, time point, time stamp, or the like. In some embodiments, the timer112may comprise a hardware counter or other digital logic.

The sensor114may comprise one or more electrical, electronic, electromechanical, electrochemical, or like devices or systems for detecting one or more electromagnetic characteristics of the input102, the load104, and the charger116. Exemplary electromagnetic characteristics include but are not limited to voltage, current, power, capacitance, inductance, flux, or the like.

The charger116may comprise one or more electrical, electronic, electromechanical, electrochemical, or like devices or systems for charging the load104. In some embodiments, the charger may comprise an inductive charger. An inductive charger may be, but is not limited to, a buck charger, a buck-boost charger, a flyback charger, a combination thereof, or the like.

FIG. 2illustrates an exemplary circuit apparatus in accordance with present embodiments. As illustrated inFIG. 2, an exemplary system200includes an input portion, an output portion, a charger portion, a controller portion, a timer portion, and a sensor portion. In some embodiments, the exemplary system200may comprise one or more discrete electrical, electronic, or like elements assembled on a printed circuit board, a solderless circuit board (e.g., a “breadboard”) or the like. In some embodiments, one or more elements of the exemplary system200may be fabricated in an integrated circuit or multiple integrated circuits assembled on a printed circuit board, a solderless circuit board, or the like. In some embodiments, one or more portions or components of the exemplary system200may be implemented in one or more programmable or reprogrammable devices or systems.

The input portion may comprise an input node248for receiving a supply voltage. In some embodiments, the input node248comprises a wired or wireless connection interface for receiving an input in accordance with the input102. The output portion may comprise an output node246for supplying an output voltage. In some embodiments, the output node246comprises a wired connection interface for supplying an output in accordance with the load104. In some embodiments, at least one of the input node248and the output node246includes one or more USB terminals or ports (e.g., USB-C ports).

The charger portion may comprise an inductor240, an output diode242, and an output capacitor244. In some embodiments, the charger portion comprises a circuit, a device, a system, or the like, in accordance with the charger116. The inductor240may have a first terminal operatively coupled to the output node246and a second node operatively coupled to a charger input node. The output diode242may have a cathode terminal operatively coupled to the charger input node and an anode terminal operatively coupled to a ground node. The output capacitor may have a first terminal operatively coupled to the output node246and a second terminal operatively coupled to the ground node. It is to be understood that the charger portion may include additional components to effect operation as a buck converter, a boost converter, a buck-boost converter, or the like. In some embodiments, the inductor240may comprise a transformer in a flyback converter. In some embodiments, the charger portion may include one or more switching transistors arranged with terminals operatively coupled to the inductor240in order to implement a buck converter, a boost converter, a buck-boost converter, or the like.

The controller portion may comprise a logic gate220, a logic device222a switching transistor224, for controlling pulse frequency, a precision voltage reference210, a first comparator212, a second comparator214, and a current sensing amplifier216for sensing at least a charging threshold. In some embodiments, the controller portion comprises a circuit, a programmable device, a programmable system, or the like, in accordance with the controller110. The logic gate220may be an AND gate or a functional equivalent thereof, may be a distinct circuit component or integrated with other circuits components. The logic gate220may include a first input terminal operatively coupled to an output terminal of the timer230, a second input terminal operatively coupled to a component associated with the sensor portion, and an output terminal operatively coupled to the logic device222. In some embodiments, the logic device222may be an SR flip flop, a functional equivalent thereof, or the like. The exemplary logic device222embodied as an SR flip flop may include a set input terminal (“S”) operatively coupled to the output terminal of the logic gate220, a reset input terminal (“R”) operatively coupled to another component associated with the charge detection threshold portion, and a noninverted output terminal (“Q”) operatively coupled to a control output node. In some embodiments, the switching transistor may be a FET, a MOSFET, power MOSFET, a BJT, a functional equivalent thereof, or the like. The exemplary switching transistor224embodied as a power MOSFET may include a gate terminal operatively coupled to the control output node, a drain terminal operatively coupled to the input node248, and a source terminal operatively coupled to the charger input node. It is to be understood that the controller may be implemented in accordance with the present embodiments with any circuit, programmable device, programmable system, or plurality or combination thereof as are known or may become known.

The timer portion may comprise a timer230for generating a delay corresponding to a particular time period. In some embodiments, the timer portion comprises a circuit, a programmable device, a programmable system, or the like, in accordance with the timer112. The timer230may include a timer output terminal (“T”) operatively coupled to the first input node of the logic gate220, and a reset terminal (“R”) operably coupled to the control output node.

The precision voltage reference210may comprise a positive terminal operatively coupled to a second sensor node, and the precision voltage reference210may further comprise a negative terminal operatively coupled to the charger input node. In some embodiments, the precision voltage reference210is configured to set discharging and charging thresholds by coupling its positive terminal to the noninverting input of the first comparator212and the inverting input of the comparator214. The first comparator212may comprise an inverting input terminal operatively coupled to the first sensor node, a noninverting input terminal operatively coupled to the second sensor node, and an output terminal operatively coupled to the second input of the logic gate220. The second comparator214may comprise an inverting input terminal operatively coupled to the second sensor node, a noninverting input terminal operatively coupled to the current sensing amplifier216, and an output terminal operatively coupled to the reset terminal of the logic device222. The current sensing amplifier216may comprise an output terminal operatively coupled to the noninverting input terminal of the second comparator214, and an input terminal operatively coupled to the charger input node. In some embodiments, the current sensing amplifier216operatively senses current through the switching transistor224. In some embodiments, the current sensing amplifier216may comprise or be substituted with a constant-on timer (COT). In some embodiments, the COT is adaptive to one or more of input and output voltages.

The charge detection threshold portion may comprise a sampling capacitor202, a voltage divider circuit including resistors204and206, and a feedback diode208. In some embodiments, the charge detection threshold portion comprises a circuit, a programmable device, a programmable system, or the like, in accordance with the sensor114. The sampling capacitor202may have a first terminal operatively coupled to a feedback node, and a second node operatively coupled to the charger input node. In some embodiments, the sampling capacitor202may be an adjustable- or variable-capacitance capacitor. The resistors204and206of an exemplary voltage divider circuit may be arranged in series with each other and in parallel with the sampling capacitor202. The resistor204may comprise a first terminal operatively coupled to the feedback node, and a second terminal operatively coupled to a first sensor node. The resistor206may comprise a first terminal operatively coupled to the first sensor node and a second terminal operatively coupled to the charger input node. The feedback diode208may comprise a cathode terminal operatively coupled to the feedback node, and an anode terminal operatively coupled to the output node246. It is to be understood that the nodes described herein may include therein various electronic components, and are not limited to direct electrical connections between the exemplary components described herein.

FIG. 3illustrates an exemplary integrated circuit apparatus in accordance with present embodiments. As illustrated inFIG. 3, an exemplary system300includes an input portion, an integrated circuit portion, a circuit portion, and an output portion. In some embodiments, the exemplary system300includes a regulator using a floating topology, where ground of an integrated circuit portion is operatively coupled to a non-ground charger input node. In some embodiments, the exemplary system300may comprise one or more discrete electrical, electronic, or like elements assembled on a printed circuit board, a solderless circuit board (e.g., a “breadboard”) or the like. In some embodiments, one or more elements of the exemplary system300may be fabricated in an integrated circuit or multiple integrated circuits assembled on a printed circuit board, a solderless circuit board, or the like. In some embodiments, one or more portions or components of the exemplary system300may be implemented in one or more programmable or reprogrammable devices or systems.

The input portion may comprise an input node340for receiving a supply voltage. In some embodiments, the input node340comprises a wired or wireless connection interface for receiving an input in accordance with the input102or the input node248. The output portion may comprise an output node342for supplying an output voltage. In some embodiments, the output node342comprises a wired connection interface for supplying an output in accordance with the load104or the output node246. In some embodiments, at least one of the input node340and the output node342includes one or more USB terminals or ports (e.g., USB-C ports).

The integrated circuit portion may comprise at least one integrated circuit310including an input voltage pin312, an IC supply input pin314, a feedback pin316, and an IC ground pin318. In some embodiments, the integrated circuit310may be a Renesas Electronics™ RAA223011 low power offline regulator operable to receive rectified universal AC input (e.g., 85V AC to 265V AC), and output 12V DC output, among others. In some embodiments, the integrated circuit310may be one or more of a Monolithic Power Systems™ MP174, a Power Integrations™ LinkSwitch-TN2, a Power Integrations™ LinkZero-AX, and an NXP Semiconductors™ TEA172x class integrated circuit. The integrated circuit310may comprise at least one integrated circuit for implementing at least a portion of the system100or the system200. The input voltage pin312may be operatively coupled to the input node340. In some embodiments, the IC supply input pin314may be operatively coupled to a circuit supply node. In some embodiments, the IC supply input pin314The IC supply input pin314may be operatively coupled to a circuit that supplies the IC from the output node342. The feedback pin316may be operatively coupled to a feedback node. The IC ground pin318may be operatively coupled to a charger input node.

The circuit portion may comprise an IC supply decoupling capacitor320, a voltage divider circuit including resistors322and324, a sampling capacitor326, an output diode328, an inductor330, an output capacitor332, an output resistor334, a supply diode336, and a feedback diode338. The IC supply decoupling capacitor320may have a first terminal operatively coupled to the circuit supply node, and a second terminal operatively coupled to the charger input node. The sampling capacitor326may comprise a first terminal operatively coupled to a sampling node and a second terminal operatively coupled to the charger input node. In some embodiments, the sampling capacitor326may be an adjustable- or variable-capacitance capacitor. The resistors322and324of an exemplary voltage divider circuit may be arranged in series with each other and in parallel with the sampling capacitor326. The resistor322may comprise a first terminal operatively coupled to the sampling node, and a second terminal operatively coupled to the feedback node. The resistor324may comprise a first terminal operatively coupled to the feedback node and a second terminal operatively coupled to the charger input node.

The output diode328may comprise a cathode terminal operatively coupled to the charger input node, and an anode terminal operatively coupled to a ground node. The output capacitor332may comprise a first terminal operatively coupled to the output node342, and a second terminal operatively coupled to the ground node. The supply diode336may comprise a cathode terminal operatively coupled to the circuit supply node, and an anode terminal operatively coupled to the output node342. The feedback diode338may comprise a cathode terminal operatively coupled to the sampling node, and an anode terminal operatively coupled to the output node342. The output resistor334may comprise a first terminal operatively coupled to the output node342, and a second terminal operatively coupled to the ground node.

The inductor330may have a first terminal operatively coupled to the output node342and a second node operatively coupled to the charger input node. It is to be understood that the circuit portion may include additional components to effect operation as a buck converter, a boost converter, a buck-boost converter, or the like. In some embodiments, the inductor330may comprise a transformer in a flyback converter. In some embodiments, the circuit portion may include one or more switching transistors arranged with terminals operatively coupled to the inductor330in order to implement a buck converter, a boost converter, a buck-boost converter, or the like.

FIG. 4illustrates exemplary timing diagrams including sampling capacitor voltage magnitude and charging pulse current magnitude in accordance with present embodiments. As illustrated by way of example inFIG. 4, an exemplary system may operate according to voltage and current timing in exemplary timing diagrams400. An exemplary voltage across a sampling capacitor (VSC) varies from time t0402through time t5412. Concurrently, an output voltage at a load or output node (VOUT) varies from time t0402through time t5412. Concurrently, an exemplary charger current (IL) can be measured from time t0402to time t5412. Concurrently an exemplary output current at the load or the output node (IOUT) is substantially constant and present from time t0402through time t5412. The exemplary system may undergo multiple sequential cycles in accordance with present embodiments.

At time t0402, a first voltage regulation period420begins, a first sampling capacitor charge-discharge cycle422begins, a first burst period430begins, and a first charging pulse432begins. At time t0, VOUTis decreasing from a sensed output voltage level corresponding to a peak output voltage level440, and the exemplary system detects that VSCis less than or equal to a voltage threshold442, and the exemplary system begins the charging pulse432having a magnitude equal to a peak current threshold444. In response to the first charging pulse432, VSCincreases toward the peak output voltage level440. VOUTstops decreasing and begins increasing to the peak output voltage level440when VSCessentially equals, equals or exceeds VOUT. In some embodiments, VOUTand VSCremain equal after VSCincreases to equal VOUTand continues increasing to the peak voltage level440, until time t1404. At time t1404, the first burst period430ends, the first charging pulse432ends, and a first sampling capacitor discharge period450begins. The first charging pulse432ends when VSCincreases to equal the peak voltage output level440. In response, VOUTstops increasing and begins decreasing. At time t2406, the first voltage regulation period420ends, the first sampling capacitor charge-discharge cycle422ends, and the first sampling capacitor discharge period450ends. VOUTcontinues decreasing. In addition, a second voltage regulation period420begins, a second sampling capacitor charge-discharge cycle424begins, a second burst period430begins, and a second charging pulse434begins.

The exemplary system may thus repeat operation according to the first sampling capacitor charge-discharge cycle422in subsequent cycles. Operation of the exemplary system at time t2406and time t4410may correspond to operation at time t0402. Further, operation of the exemplary system at time t3408and time t5412may correspond to operation at time t1404. Thus, second and third sampling capacitor charge-discharge cycles424and426may operate correspondingly to the first sampling capacitor charge-discharge cycle422. In addition, second and third charging pulses may operate correspondingly to the first charging pulse432. Alternatively, charging pulse comprises a charging timer during which a charging pulse exists.

In exemplary embodiments, VSCdecays faster that than VOUT, to prevent voltage across the sampling capacitor202from exceeding the peak voltage output level440. If the voltage across the sampling capacitor202exceeds the peak output voltage level440in various embodiments, the feedback diode208will not activate to begin a charging cycle of any of the charge-discharge cycle422,424or426, and sampling may not occur. Therefore, it can be understood that:

An exemplary ripple voltage across an exemplary sampling capacitor corresponds to a difference between the peak output voltage level440and a voltage threshold442. The threshold voltage may be a function of a precision reference voltage and a voltage divider circuit. Thus:

An exemplary output current IOUT, can be understood with respect to an inductor peak current IPEAK, a switching period T, an “on-off” period TPcomprising an “on” time TONand an “off” time TOFF, and an inductance L, by:

An exemplary minimum input power PIN,minis based on a minimum output current IOUT,min. As an exemplary sampling capacitor discharges to a minimum current level, time increases. To discharge an exemplary sampling capacitor sufficiently to IOUT,min, a maximum time period TMAXmay elapse. Thus, an exemplary output current IOUT,min, IPEAK, and TMAXmay all be understood as:

Based on the above exemplary Eqs. (5), (6) and (7), and an exemplary power supply efficiency it may be understood that:

Thus, as PIN,mindecreases, COUTincreases. Exemplary embodiments, in accordance with Eq. (10), may set or select a desired PIN,minby varying the value of COUTin an exemplary output capacitor. A value of COUTsatisfying a desired PIN,minmay then be applied to Eq. (1) to set or select values for the voltage divider resistors R1and R2and the sampling capacitor Cs in exemplary embodiments. The exemplary systems100,200and300may be embodied in accordance with at least one of Eqs. (1)-(10). This way, PIN,mincan be adjusted externally, without additional pins and without additional external components.

FIG. 5illustrates an exemplary method of applying a charging pulse to an output capacitor in accordance with the exemplary timing diagrams ofFIG. 4. In some embodiments, one of the exemplary systems100,200or300performs method500according to present embodiments. In some embodiments, regulation of charging pulse timing and charging-discharge cycles is based on ripple voltage of the exemplary sampling capacitor202ofFIG. 2.

At step510, an exemplary system applies a charging pulse. In the exemplary system200, the switching transistor224is activated, and inductor current ramps up. The method then continues to step520.

At step520, the exemplary system detects whether inductor current satisfies a current threshold. In some embodiments, the current threshold corresponds to IPEAK. In some embodiments, a charge pulse is defined by a timer circuit, timer logic, or the like. The method500continues to step522. Alternatively, if the exemplary system does not detect that the inductor current satisfies IPEAKthreshold, or detects that the voltage across the sampling capacitor does not satisfy the maximum voltage threshold, the method500continues to step510.

At step522, the exemplary system ends the charging pulse. The method500then continues to step530.

At step530, the exemplary system begins a discharge cycle. During this time, the sampling capacitor202slowly discharges through the resistors204and206. Concurrently, the output capacitor244slowly discharges as well. The method then continues to step532.

At step532, the exemplary system detects whether voltage across the sampling capacitor202drops below a voltage threshold. In some embodiments, the voltage threshold corresponds to the discharge threshold, and further corresponds to VTHof Eq. (3). The method then continues to step534. Alternatively, if the exemplary system does not detect that the voltage across the sampling capacitor does not satisfy the satisfy the charging threshold, the method500continues to step530.

At step534, the exemplary system detects whether delay timer has satisfied a delay time period. In some embodiments, the delay timer defines a minimum capacitor discharge period. In some embodiments, the minimum capacitor discharge period corresponds to the capacitor discharge period450, and defines a maximum switching frequency comprising the first burst period430and the capacitor discharge period450. If the exemplary system detects that the delay timer satisfies the delay time period, then the method continues to step510. Alternatively, if the exemplary system does not detect that the delay timer satisfies the delay time period, or detects that the delay timer does not satisfy the delay time period, the method500continues to step530.

Further, unless otherwise noted, the use of the words “approximate,” “about,” “around,” “substantially,” etc., mean plus or minus ten percent.