IMAGE SENSOR

Disclosed is an image sensor including first to fourth, fifth to eighth, ninth to 12th and 13th to 16th unit pixel circuits, a first readout line connected to the first and ninth unit pixel circuits, a second readout line connected to the fifth and 13th unit pixel circuits, a third readout line connected to the second and 10th unit pixel circuits, a fourth readout line connected to the sixth and 14th unit pixel circuits, a fifth readout line connected to the third and 11th unit pixel circuits, a sixth readout line connected to the seventh and 15th unit pixel circuits, a seventh readout line connected to the fourth and 12th unit pixel circuits, an eighth readout line connected to the eighth and 16th unit pixel circuits, first to fourth readout circuits, and a path selector connecting the unit pixel circuits to the readout circuits via the readout lines.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2022-0112953, filed on Sep. 6, 2022, the disclosure of which is incorporated herein by reference in its entirety.

BACKGROUND

Various embodiments of the present disclosure relate to a semiconductor design technique, and more particularly, to an image sensor that supports a binning mode.

2. Description of the Related Art

Image sensors are electronic devices for capturing images using the property of a semiconductor, which reacts to light. Image sensors may be classified into charge-coupled device (CCD) image sensors and complementary metal-oxide semiconductor (CMOS) image sensors. Recently, CMOS image sensors are widely used because the CMOS image sensors can allow both analog and digital control circuits to be directly implemented on a single integrated circuit (IC).

SUMMARY

Various embodiments of the present disclosure are directed to an image sensor capable of performing an analog binning operation in a horizontal direction.

In accordance with an embodiment of the present disclosure, an image sensor may include: a first pixel group including first to fourth unit pixel circuits arranged in at least one row; a second pixel group including fifth to eighth unit pixel circuits arranged in at least one other row; a third pixel group including ninth to 12thunit pixel circuits arranged in at least one other row; a fourth pixel group including 13th to 16thunit pixel circuits arranged in at least one other row; a first readout line disposed in a first column and connected to the first unit pixel circuit and the ninth unit pixel circuit; a second readout line disposed in a second column and connected to the fifth unit pixel circuit and the 13thunit pixel circuit; a third readout line disposed in a third column and connected to the second unit pixel circuit and the 10thunit pixel circuit; a fourth readout line disposed in a fourth column and connected to the sixth unit pixel circuit and the 14thunit pixel circuit; a fifth readout line disposed in a fifth column and connected to the third unit pixel circuit and the 11thunit pixel circuit; a sixth readout line disposed in a sixth column and connected to the seventh unit pixel circuit and the 15thunit pixel circuit; a seventh readout line disposed in a seventh column and connected to the fourth unit pixel circuit and the 12thunit pixel circuit; an eighth readout line disposed in an eighth column and connected to the eighth unit pixel circuit and the 16thunit pixel circuit; first to fourth readout circuits; and a path selector suitable for connecting the first to 16th unit pixel circuits to the first to fourth readout circuits via the first to eighth readout lines during a single row time in a binning mode.

In accordance with an embodiment of the present disclosure, an image sensor may include: a pixel array including N*M unit pixel circuits, where N≥2 and M≥N; K*N readout lines connected to the N*M unit pixel circuits, where K≥2; a signal converter including N readout circuits; and a path selector suitable for connecting the N*M unit pixel circuits to the N readout circuits via the K*N readout lines during a single row time in a binning mode.

In accordance with an embodiment of the present disclosure, an image sensor may include: a pixel array including a plurality of unit pixel circuits; a plurality of readout lines connected to the plurality of unit pixel circuits; a plurality of readout circuits; a first path selection circuit coupled between the plurality of readout lines and the plurality of bias circuits, and suitable for selectively connecting the plurality of readout lines to the plurality of bias circuits on the basis of a plurality of first control signals; a plurality of readout circuits; and a second path selection circuit coupled between the plurality of readout lines and the plurality of readout circuits, and suitable for selectively connecting the plurality of readout lines to the plurality of readout circuits on the basis of a plurality of second control signals.

In accordance with an embodiment of the present disclosure, an image sensor may include: a 4×4 array of unit pixel circuits; and a peripheral circuit configured to average during a single row time: pixel signals output through odd readout lines of respective odd columns of the array to generate a first selection pixel signal, pixel signals output through odd readout lines of respective even columns of the array to generate a second selection pixel signal, pixel signals output through even readout lines of the respective odd columns to generate a third selection pixel signal, and pixel signals output through even readout lines of the respective even columns to generate a fourth selection pixel signal, wherein the unit pixel circuits arranged in odd rows of the array are coupled to the respective even readout lines of the respective columns of the array, and wherein the unit pixel circuit arranged in even rows of the array are coupled to the respective odd readout lines of the respective columns of the array.

DETAILED DESCRIPTION

Various embodiments of the present disclosure are described below with reference to the accompanying drawings, in order to describe in detail the present disclosure so that those with ordinary skill in art to which the present disclosure pertains may easily carry out the technical spirit of the present disclosure.

It will be understood that when an element is referred to as being “connected to” or “coupled to” another element, the element may be directly connected to or coupled to the another element, or electrically connected to or coupled to the another element with one or more elements interposed therebetween. In addition, it will also be understood that the terms “comprises,” “comprising,” “includes,” and “including” when used in this specification do not preclude the presence of one or more other elements, but may further include or have the one or more other elements, unless otherwise mentioned. In the description throughout the specification, some components are described in singular forms, but the present disclosure is not limited thereto, and it will be understood that the components may be formed in plural.

FIG.1is a block diagram illustrating an image sensor100in accordance with a first embodiment of the present disclosure.

Referring toFIG.1, the image sensor100may include a row controller110, a pixel array120, a timing controller130, a path selector140, a bias generator150and a signal converter160.

The row controller110may generate row control signals RCTRLs for controlling the pixel array120.

The row controller110may generate the row control signals RCTRLs for controlling the pixel array120for each single row group in a normal mode. For example, the row controller110may generate first row control signals for controlling a first unit pixel circuit group arranged in a first row group, for example, first and second rows, of the pixel array120during a first single row time, and generate ythrow control signals for controlling a ythunit pixel circuit group arranged in a ythrow group, for example, 2*y−1 to 2*y rows, of the pixel array120during a ythsingle row time, where “y” is a natural number equal to or greater than 2. The row control signals RCTRLs may include the first to ythrow control signals.

The row controller110may generate the row control signals RCTRLs for controlling the pixel array120by a plurality of row groups in a binning mode. For example, the row controller110may generate first to fourth row control signals for controlling first to fourth unit pixel circuit groups arranged in first to fourth row groups, for example, first to eighth rows, of the pixel array120during a first single row time, and generate (y−3)thto ythrow control signals for controlling (y−3)thto ythunit pixel circuit groups arranged in (y−3)thto ythrow groups, for example, 2*y−7 to 2*y rows, of the pixel array120during a (y/4)thsingle row time.

The pixel array120may include a plurality of pixels arranged at intersections of a plurality of rows and a plurality of columns. The plurality of pixels may output pixel signals Ps, which correspond to at least one row, through column lines on the basis of the row control signals RCTRLs. The pixel array120may include unit pixel circuits, arranged in a grid structure (refer toFIG.2or3).

The timing controller130may generate first control signals BSELs and second control signals PSELs. For example, the timing controller130may repeatedly generate the first control signals BSELs and the second control signals PSELs during the first to ythsingle row times in the normal mode, and repeatedly generate the first control signals BSELs and the second control signals PSELs during the first to (y/4)thsingle row times in the binning mode.

The path selector140may provide a path of the pixel signals Ps and a path of biases on the basis of the first control signals BSELs and the second control signals PSELs. The path selector140may generate the pixel signals Ps as selection pixel signals Ss in the normal mode, and generate the selection pixel signals Ss by performing an analog binning operation on the pixel signals Ps in the binning mode. For example, the analog binning operation refers to an operation of averaging pixel signals corresponding to the same color filter among the pixel signals Ps. The path selector140is described in detail below.

The bias generator150may be connected to the pixel array120through the path selector140. For example, the bias generator150may generate a bias current so that the pixel signals Ps may be read out through the column lines. The bias generator150is described in detail below.

The signal converter160may convert the selection pixel signals Ss transmitted from the path selector140into digital signals DOUTs. For example, the signal converter160may include an analog to digital converter.

FIG.2is a block diagram illustrating an example of the pixel array120, the path selector140, the bias generator150and the signal converter160illustrated inFIG.1in accordance with an embodiment of the present disclosure. For convenience in description,FIG.2illustrates only a portion of each of the pixel array120, the path selector140, the bias generator150and the signal converter160.

Referring toFIG.2, the pixel array120may include first to 16thunit pixel circuits.

The first to fourth unit pixel circuits may be included in the first unit pixel circuit group. That is, the first to fourth unit pixel circuits may be arranged in the first row group, for example, the first and second rows. Each of the first to fourth unit pixel circuits may include four pixels arranged in a 2*2 structure. Each of the first to fourth unit pixel circuits may have a structure in which a plurality of photodiodes share one floating diffusion node. For example, each of the first to fourth unit pixel circuits may have a structure in which four photodiodes corresponding to the 2*2 structure share one floating diffusion node. The first unit pixel circuit may be connected to a first column line OL1, and output a first pixel signal P<1> through the first column line OL1. For example, the first unit pixel circuit may sequentially output four pixel signals, which correspond to first to fourth pixels, as the first pixel signal P<1>. The second unit pixel circuit may be connected to a third column line OL2, and output a third pixel signal P<3> through the third column line OL2. For example, the second unit pixel circuit may sequentially output four pixel signals, which correspond to fifth to eighth pixels, as the third pixel signal P<3>. The third unit pixel circuit may be connected to a fifth column line OL3, and output a fifth pixel signal P<5> through the fifth column line OL3. For example, the third unit pixel circuit may sequentially output four pixel signals, which correspond to ninth to 12thpixels, as the fifth pixel signal P<5>. The fourth unit pixel circuit may be connected to a seventh column line OL4, and output a seventh pixel signal P<7> through the seventh column line OL4. For example, the fourth unit pixel circuit may sequentially output four pixel signals, which correspond to 13thto 16thpixels, as the seventh pixel signal P<7>.

The fifth to eighth unit pixel circuits may be included in the second unit pixel circuit group. That is, the fifth to eighth unit pixel circuits may be arranged in the second row group, for example, the third and fourth rows. Each of the fifth to eighth unit pixel circuits may include four pixels arranged in the 2*2 structure. The fifth unit pixel circuit may be connected to a second column line EL1, and output a second pixel signal P<2> through the second column line EL1. For example, the fifth unit pixel circuit may sequentially output four pixel signals, which correspond to 17thto 20thpixels, as the second pixel signal P<2>. The sixth unit pixel circuit may be connected to a fourth column line EL2, and output a fourth pixel signal P<4> through the fourth column line EL2. For example, the sixth unit pixel circuit may sequentially output four pixel signals, which correspond to 21stto 24thpixels, as the fourth pixel signal P<4>. The seventh unit pixel circuit may be connected to a sixth column line EL3, and output a sixth pixel signal P<6> through the sixth column line EL3. For example, the seventh unit pixel circuit may sequentially output four pixel signals, which correspond to 25thto 28thpixels, as the sixth pixel signal P<6>. The eighth unit pixel circuit may be connected to an eighth column line EL4, and output an eighth pixel signal P<8> through the eighth column line EL4. For example, the eighth unit pixel circuit may sequentially output four pixel signals, which correspond to 29thto 32ndpixels, as the eighth pixel signal P<8>.

The ninth to 12thunit pixel circuits may be included in the third unit pixel circuit group. That is, the ninth to 12thunit pixel circuits may be arranged in the third row group, for example, the fifth and sixth rows. Each of the ninth to 12thunit pixel circuits may include four pixels arranged in the 2*2 structure. The ninth unit pixel circuit may be connected to the first column line OL1, and output the first pixel signal P<1> through the first column line OL1. For example, the ninth unit pixel circuit may sequentially output four pixel signals, which correspond to 33rdto 36thpixels, as the first pixel signal P<1>. The 10thunit pixel circuit may be connected to the third column line OL2, and output the third pixel signal P<3> through the third column line OL2. For example, the 10thunit pixel circuit may sequentially output four pixel signals, which correspond to 37thto 40thpixels, as the third pixel signal P<3>. The 11thunit pixel circuit may be connected to the fifth column line OL3, and output the fifth pixel signal P<5> through the fifth column line OL3. For example, the 11thunit pixel circuit may sequentially output four pixel signals, which correspond to 41stto 44thpixels, as the fifth pixel signal P<5>. The 12thunit pixel circuit may be connected to the seventh column line OL4, and output the seventh pixel signal P<7> through the seventh column line OL4. For example, the 12thunit pixel circuit may sequentially output four pixel signals, which correspond to 45thto 48thpixels, as the seventh pixel signal P<7>.

The 13thto 16thunit pixel circuits may be included in the fourth unit pixel circuit group. That is, the 13thto 16thunit pixel circuits may be arranged in the fourth row group, for example, the seventh and eighth rows. Each of the 13thto 16thunit pixel circuits may include four pixels arranged in the 2*2 structure. The 13thunit pixel circuit may be connected to the second column line EL1, and output the second pixel signal P<2> through the second column line EL1. For example, the 13thunit pixel circuit may sequentially output four pixel signals, which correspond to 49thto 52ndpixels, as the second pixel signal P<2>. The 14thunit pixel circuit may be connected to the fourth column line EL2, and output the fourth pixel signal P<4> through the fourth column line EL2. For example, the 14thunit pixel circuit may sequentially output four pixel signals, which correspond to 53rdto 56thpixels, as the fourth pixel signal P<4>. The 15thunit pixel circuit may be connected to the sixth column line EL3, and output the sixth pixel signal P<6> through the sixth column line EL3. For example, the 15thunit pixel circuit may sequentially output four pixel signals, which correspond to 57thto 60thpixels, as the sixth pixel signal P<6>. The 16thunit pixel circuit may be connected to the eighth column line EL4, and output the eighth pixel signal P<8> through the eighth column line EL4. For example, the 16thunit pixel circuit may sequentially output four pixel signals, which correspond to 61stto 64thpixels, as the eighth pixel signal P<8>.

Although the present embodiment describes as an example that each unit pixel circuit includes pixels arranged in the 2*2 structure, the present disclosure is not necessarily limited thereto, and the present embodiment may also be applied to a unit pixel circuit including pixels arranged in another structure, for example, 2*4, 3*3, etc.

The bias generator150may include first to fourth bias circuits PXBIAS1to PXBIAS4. The first to fourth bias circuits PXBIAS1to PXBIAS4may be configured to have the same number as the number of unit pixel circuits, for example, the first to fourth unit pixel circuits, arranged for each row group, for example, the first row group. The first to fourth bias circuits PXBIAS1to PXBIAS4may be selectively connected to first to eighth readout lines OL1to OL4and EL1to EL4via the path selector140. For example, each of the first to fourth bias circuits PXBIAS1to PXBIAS4may include a current source.

The signal converter160may include first to fourth readout circuits ADC1to ADC4. The first to fourth readout circuits ADC1to ADC4may be configured to have the same number as the number of unit pixel circuits, for example, the first to fourth unit pixel circuits, arranged for each row group, for example, the first row group. The first to fourth bias circuits PXBIAS1to PXBIAS4may be selectively connected to the first to eighth readout lines OL1to OL4and EL1to EL4via the path selector140.

The path selector140may include first and second path selection circuits141and143.

The first path selection circuit141may be coupled between the first to eighth readout lines OL1to OL4and EL1to EL4and the first to fourth bias circuits PXBIAS1to PXBIAS4. The first path selection circuit141may selectively connect the first to eighth readout lines OL1to OL4and EL1to EL4to the first to fourth bias circuits PXBIAS1to PXBIAS4on the basis of a plurality of first control signals BSEL<1:12>. The plurality of first control signals BSEL<1:12> may correspond to the plurality of first control signals BSELs illustrated inFIG.1. The first path selection circuit141may selectively connect one of the readout lines to one of the bias circuits for each single row time in the normal mode. For example, in the normal mode, the first path selection circuit141may alternately connect the odd-numbered readout lines OL1to OL4and the even-numbered readout lines EL0to EL4to the first to fourth bias circuits PXBIAS1to PXBIAS4. The first path selection circuit141may selectively connect two or more of the readout lines to one of the bias circuits for each single row time in the binning mode. For example, in the binning mode, the first path selection circuit141may connect the first and fifth readout lines OL1and OL3to the first bias circuit PXBIAS1, connect the second and sixth readout lines EL1and EL3to the third bias circuit PXBIAS3, connect the third and seventh readout lines OL2and OL4to the second bias circuit PXBIAS2, and connect the fourth and eighth readout lines EL2and EL4to the fourth bias circuit PXBIAS4. For example, the first path selection circuit141may include first to 12thbias switches.

The first bias switch may be coupled between the first readout line OL1and the first bias circuit PXBIAS1. The first bias switch may selectively connect the first readout line OL1to the first bias circuit PXBIAS1on the basis of the first control signal BSEL<1> among the plurality of first control signals BSEL<1:12>.

The second bias switch may be coupled between the second readout line EL1and the first bias circuit PXBIAS1. The second bias switch may selectively connect the second readout line EL1to the first bias circuit PXBIAS1on the basis of the second control signal BSEL<2> among the plurality of first control signals BSEL<1:12>.

The third bias switch may be coupled between the second readout line EL1and the third bias circuit PXBIAS3. The third bias switch may selectively connect the second readout line EL1to the third bias circuit PXBIAS3on the basis of the third control signal BSEL<3> among the plurality of first control signals BSEL<1:12>.

The fourth bias switch may be coupled between the third readout line OL2and the second bias circuit PXBIAS2. The fourth bias switch may selectively connect the third readout line OL2to the second bias circuit PXBIAS2on the basis of the fourth control signal BSEL<4> among the plurality of first control signals BSEL<1:12>.

The fifth bias switch may be coupled between the fourth readout line EL2and the second bias circuit PXBIAS2. The fifth bias switch may selectively connect the fourth readout line EL2to the second bias circuit PXBIAS2on the basis of the fifth control signal BSEL<5> among the plurality of first control signals BSEL<1:12>.

The sixth bias switch may be coupled between the fourth readout line EL2and the fourth bias circuit PXBIAS4. The sixth bias switch may selectively connect the fourth readout line EL2to the fourth bias circuit PXBIAS4on the basis of the sixth control signal BSEL<6> among the plurality of first control signals BSEL<1:12>.

The seventh bias switch may be coupled between the fifth readout line OL3and the first bias circuit PXBIAS1. The seventh bias switch may selectively connect the fifth readout line OL3to the first bias circuit PXBIAS1on the basis of the seventh control signal BSEL<7> among the plurality of first control signals BSEL<1:12>.

The eighth bias switch may be coupled between the fifth readout line OL3and the third bias circuit PXBIAS3. The eighth bias switch may selectively connect the fifth readout line OL3to the third bias circuit PXBIAS3on the basis of the eighth control signal BSEL<8> among the plurality of first control signals BSEL<1:12>.

The ninth bias switch may be coupled between the sixth readout line EL3and the third bias circuit PXBIAS3. The ninth bias switch may selectively connect the sixth readout line EL3to the third bias circuit PXBIAS3on the basis of the ninth control signal BSEL<9> among the plurality of first control signals BSEL<1:12>.

The 10thbias switch may be coupled between the seventh readout line OL4and the fourth bias circuit PXBIAS4. The 10thbias switch may selectively connect the seventh readout line OL4to the fourth bias circuit PXBIAS4on the basis of the 10thcontrol signal BSEL<10> among the plurality of first control signals BSEL<1:12>.

The 11thbias switch may be coupled between the seventh readout line OL4and the fourth bias circuit PXBIAS4. The 11thbias switch may selectively connect the seventh readout line OL4to the fourth bias circuit PXBIAS4on the basis of the 11thcontrol signal BSEL<11> among the plurality of first control signals BSEL<1:12>.

The 12thbias switch may be coupled between the eighth readout line EL4and the fourth bias circuit PXBIAS4. The 12thbias switch may selectively connect the eighth readout line EL4to the fourth bias circuit PXBIAS4on the basis of the 12thcontrol signal BSEL<12> among the plurality of first control signals BSEL<1:12>.

The second path selection circuit143may be coupled between the first to eighth readout lines OL1to OL4and EL1to EL4and the first to fourth readout circuits ADC1to ADC4. The second path selection circuit143may selectively connect the first to eighth readout lines OL1to OL4and EL1to EL4to the first to fourth readout circuits ADC1to ADC4on the basis of a plurality of second control signals PSEL<1:12>. The plurality of second control signals PSEL<1:12> may correspond to the plurality of second control signals PSELs illustrated inFIG.1. The second path selection circuit143may selectively connect one of the readout lines to one of the readout circuits for each single row time in the normal mode. For example, in the normal mode, the second path selection circuit143may alternately connect odd-numbered readout lines OL1to OL4and even-numbered readout lines EL0to EL4to the first to fourth readout circuits ADC1to ADC4. The second path selection circuit143may selectively connect two or more of the readout lines to one of the readout circuits for each single row time in the binning mode. For example, in the binning mode, the second path selection circuit143may connect the first and fifth readout lines OL1and OL3to the first readout circuit ADC1, connect the second and sixth readout lines EL1and EL3to the third readout circuit ADC3, connect the third and seventh readout lines OL2and OL4to the second readout circuit ADC2, and connect the fourth and eighth readout lines EL2and EL4to the fourth readout circuit ADC4. For example, the second path selection circuit143may include first to 12thtransfer switches.

The first transfer switch may be coupled between the first readout line OL1and the first readout circuit ADC1. The first transfer switch may selectively connect the first readout line OL1to the first readout circuit ADC1on the basis of the first control signal PSEL<1> among the plurality of second control signals PSEL<1:12>.

The second transfer switch may be coupled between the second readout line EL1and the first readout circuit ADC1. The second transfer switch may selectively connect the second readout line EL1to the first readout circuit ADC1on the basis of the second control signal PSEL<2> among the plurality of second control signals PSEL<1:12>.

The third transfer switch may be coupled between the second readout line EL1and the third readout circuit ADC3. The third transfer switch may selectively connect the second readout line EL1to the third readout circuit ADC3on the basis of the third control signal PSEL<3> among the plurality of second control signals PSEL<1:12>.

The fourth transfer switch may be coupled between the third readout line OL2and the second readout circuit ADC2. The fourth transfer switch may selectively connect the third readout line OL2to the second readout circuit ADC2on the basis of the fourth control signal PSEL<4> among the plurality of second control signals PSEL<1:12>.

The fifth transfer switch may be coupled between the fourth readout line EL2and the second readout circuit ADC2. The fifth transfer switch may selectively connect the fourth readout line EL2to the second readout circuit ADC2on the basis of the fifth control signal PSEL<5> among the plurality of second control signals PSEL<1:12>.

The sixth transfer switch may be coupled between the fourth readout line EL2and the fourth readout circuit ADC4. The sixth transfer switch may selectively connect the fourth readout line EL2to the fourth readout circuit ADC4on the basis of the sixth control signal PSEL<6> among the plurality of second control signals PSEL<1:12>.

The seventh transfer switch may be coupled between the fifth readout line OL3and the first readout circuit ADC1. The seventh transfer switch may selectively connect the fifth readout line OL3to the first readout circuit ADC1on the basis of the seventh control signal PSEL<7> among the plurality of second control signals PSEL<1:12>.

The eighth transfer switch may be coupled between the fifth readout line OL3and the third readout circuit ADC3. The eighth transfer switch may selectively connect the fifth readout line OL3to the third readout circuit ADC3on the basis of the eighth control signal PSEL<8> among the plurality of second control signals PSEL<1:12>.

The ninth transfer switch may be coupled between the sixth readout line EL3and the third readout circuit ADC3. The ninth transfer switch may selectively connect the sixth readout line EL3to the third readout circuit ADC3on the basis of the ninth control signal PSEL<9> among the plurality of second control signals PSEL<1:12>.

The 10thtransfer switch may be coupled between the seventh readout line OL4and the fourth readout circuit ADC4. The 10thtransfer switch may selectively connect the seventh readout line OL4to the fourth readout circuit ADC4on the basis of the 10thcontrol signal PSEL<10> among the plurality of second control signals PSEL<1:12>.

The 11thtransfer switch may be coupled between the seventh readout line OL4and the fourth readout circuit ADC4. The 11thtransfer switch may selectively connect the seventh readout line OL4to the fourth readout circuit ADC4on the basis of the 11thcontrol signal PSEL<11> among the plurality of second control signals PSEL<1:12>.

The 12thtransfer switch may be coupled between the eighth readout line EL4and the fourth readout circuit ADC4. The 12thtransfer switch may selectively connect the eighth readout line EL4to the fourth readout circuit ADC4on the basis of the 12thcontrol signal PSEL<12> among the plurality of second control signals PSEL<1:12>.FIG.3is a block diagram illustrating another example of the pixel array120, the path selector140, the bias generator150and the signal converter160illustrated inFIG.1in accordance with an embodiment of the present disclosure. For convenience in description,FIG.3illustrates only a portion of each of the pixel array120, the path selector140, the bias generator150and the signal converter160. Since the pixel array120and the signal converter160illustrated inFIG.3are the same as the pixel array120and the signal converter160illustrated inFIG.2, only the path selector140and the bias generator150are described below.

Referring toFIG.3, the bias generator150may include first to eighth bias circuits PXBIAS1to PXBIAS8. In particular, the first to eighth bias circuits PXBIAS1to PXBIAS8may be one-to-one connected to the first to eighth readout lines OL1to OL4and EL1to EL4in the binning mode. Accordingly, settling time of first to eighth pixel signals P<1:8> is reduced so that readout speeds of the first to eighth pixel signals P<1:8> may be improved. For example, each of the first to eighth bias circuits PXBIAS1to PXBIAS8may include a current source.

The path selector140may include a first path selection circuit141and a second path selection circuit143. Since the second path selection circuit143is the same as the second path selection circuit143illustrated inFIG.2, only the first path selection circuit141is described below.

The first path selection circuit141may be coupled between the first to eighth readout lines OL1to OL4and EL1to EL4and the first to eighth bias circuits PXBIAS1to PXBIAS8. The first path selection circuit141may selectively connect the first to eighth readout lines OL1to OL4and EL1to EL4to the first to eighth bias circuits PXBIAS1to PXBIAS8on the basis of a plurality of first control signals BSEL<1:16>. The plurality of first control signals BSEL<1:16> may correspond to the plurality of first control signals BSELs illustrated inFIG.1. The first path selection circuit141may connect one of the readout lines to one of the bias circuits for each single row time in the normal mode. For example, in the normal mode, the first path selection circuit141may connect odd-numbered readout lines OL1to OL4to odd-numbered bias circuits PXBIAS1, PXBIAS3, PXBIAS5and PXBIAS7, and connect even-numbered readout lines EL0to EL4to even-numbered bias circuits PXBIAS2, PXBIAS4, PXBIAS6and PXBIAS8. The first path selection circuit141may selectively connect one of the readout lines to one of the bias circuits for each single row time in the binning mode. That is, first to 16thbias switches may one-to-one connect the first to eighth readout lines OL1to OL4and EL1to EL4to the first to eighth bias circuits PXBIAS1to PXBIAS8in the binning mode. For example, in the binning mode, the first path selection circuit141may cross-connect the first and fifth readout lines OL1and OL3to the first and fifth bias circuits PXBIAS1and PXBIAS5, cross-connect the second and six readout lines EL1and EL3to the second and sixth bias circuits PXBIAS2and PXBIAS6, cross-connect the third and seventh readout lines OL2and OL4to the third and seventh bias circuits PXBIAS3and PXBIAS7, and cross-connect the fourth and eighth readout lines EL2and EL4to the fourth and eighth bias circuits PXBIAS4and PXBIAS8. For example, the first path selection circuit141may include the first to 16thbias switches.

The first bias switch may be coupled between the first readout line OL1and the first bias circuit PXBIAS1. The first bias switch may selectively connect the first readout line OL1to the first bias circuit PXBIAS1on the basis of the first control signal BSEL<1> among the plurality of first control signals BSEL<1:16>.

The second bias switch may be coupled between the first readout line OL1and the fifth bias circuit PXBIAS5. The second bias switch may selectively connect the first readout line OL1to the fifth bias circuit PXBIAS5on the basis of the second control signal BSEL<2> among the plurality of first control signals BSEL<1:16>.

The third bias switch may be coupled between the second readout line EL1and the second bias circuit PXBIAS2. The third bias switch may selectively connect the second readout line EL1to the second bias circuit PXBIAS2on the basis of the third control signal BSEL<3> among the plurality of first control signals BSEL<1:16>.

The fourth bias switch may be coupled between the second readout line EL1and the sixth bias circuit PXBIAS6. The fourth bias switch may selectively connect the second readout line EL1to the sixth bias circuit PXBIAS6on the basis of the fourth control signal BSEL<4> among the plurality of first control signals BSEL<1:16>.

The fifth bias switch may be coupled between the third readout line OL2and the third bias circuit PXBIAS3. The fifth bias switch may selectively connect the third readout line OL2to the third bias circuit PXBIAS3on the basis of the fifth control signal BSEL<5> among the plurality of first control signals BSEL<1:16>.

The sixth bias switch may be coupled between the third readout line OL2and the seventh bias circuit PXBIAS7. The sixth bias switch may selectively connect the third readout line OL2to the seventh bias circuit PXBIAS7on the basis of the sixth control signal BSEL<6> among the plurality of first control signals BSEL<1:16>.

The seventh bias switch may be coupled between the fourth readout line EL2and the fourth bias circuit PXBIAS4. The seventh bias switch may selectively connect the fourth readout line EL2to the fourth bias circuit PXBIAS4on the basis of the seventh control signal BSEL<7> among the plurality of first control signals BSEL<1:16>.

The eighth bias switch may be coupled between the fourth readout line EL2and the eighth bias circuit PXBIAS8. The eighth bias switch may selectively connect the fourth readout line EL2to the eighth bias circuit PXBIAS8on the basis of the eighth control signal BSEL<8> among the plurality of first control signals BSEL<1:16>.

The ninth bias switch may be coupled between the fifth readout line OL3and the first bias circuit PXBIAS1. The ninth bias switch may selectively connect the fifth readout line OL3to the first bias circuit PXBIAS1on the basis of the ninth control signal BSEL<9> among the plurality of first control signals BSEL<1:16>.

The 10thbias switch may be coupled between the fifth readout line OL3and the fifth bias circuit PXBIAS5. The 10thbias switch may selectively connect the fifth readout line OL3to the fifth bias circuit PXBIAS5on the basis of the 10thcontrol signal BSEL<10> among the plurality of first control signals BSEL<1:16>.

The 11thbias switch may be coupled between the sixth readout line EL3and the second bias circuit PXBIAS2. The 11thbias switch may selectively connect the sixth readout line EL3to the second bias circuit PXBIAS2on the basis of the 11thcontrol signal BSEL<11> among the plurality of first control signals BSEL<1:16>.

The 12thbias switch may be coupled between the sixth readout line EL3and the sixth bias circuit PXBIAS6. The 12thbias switch may selectively connect the sixth readout line EL3to the sixth bias circuit PXBIAS6on the basis of the 12thcontrol signal BSEL<12> among the plurality of first control signals BSEL<1:16>.

The 13thbias switch may be coupled between the seventh readout line OL4and the third bias circuit PXBIAS3. The 13thbias switch may selectively connect the seventh readout line OL4to the third bias circuit PXBIAS3on the basis of the 13thcontrol signal BSEL<13> among the plurality of first control signals BSEL<1:16>.

The 14thbias switch may be coupled between the seventh readout line OL4and the seventh bias circuit PXBIAS7. The 14thbias switch may selectively connect the seventh readout line OL4to the seventh bias circuit PXBIAS7on the basis of the 14thcontrol signal BSEL<14> among the plurality of first control signals BSEL<1:16>.

The 15thbias switch may be coupled between the eighth readout line EL4and the fourth bias circuit PXBIAS4. The 15thbias switch may selectively connect the eighth readout line EL4to the fourth bias circuit PXBIAS4on the basis of the 15thcontrol signal BSEL<15> among the plurality of first control signals BSEL<1:16>.

The 16thbias switch may be coupled between the eighth readout line EL4and the eighth bias circuit PXBIAS8. The 16thbias switch may selectively connect the eighth readout line EL4to the eighth bias circuit PXBIAS8on the basis of the 16thcontrol signal BSEL<16> among the plurality of first control signals BSEL<1:16>.

Hereinafter, an operation of the image sensor100in accordance with an embodiment of the present disclosure, which has the above-described configuration, is described with reference toFIGS.4to6.

FIGS.4and5are diagrams for describing the operation of the image sensor100according to the normal mode in accordance with an embodiment of the present disclosure.

Referring toFIG.4, the image sensor100may output the first pixel signal P<1>, the third pixel signal P<3>, the fifth pixel signal P<5> and the seventh pixel signal P<7>, which are generated from the first to fourth unit pixel circuits, as first to fourth selection pixel signals S<1:4> through the odd-numbered readout lines OL1to OL4during a first single row time. For example, the image sensor100may generate the first pixel signal P<1>, the third pixel signal P<3>, the fifth pixel signal P<5> and the seventh pixel signal P<7> from pixels each having a green filter G among the pixels included in the first to fourth unit pixel circuits, and then sequentially generate the first pixel signal P<1>, the third pixel signal P<3>, the fifth pixel signal P<5> and the seventh pixel signal P<7> from pixels having other color filters R, G and B during the first single row time.

Referring toFIG.5, the image sensor100may output the second pixel signal P<2>, the fourth pixel signal P<4>, the sixth pixel signal P<6> and the eighth pixel signal P<8>, which are generated from the fifth to eighth unit pixel circuits, as first to fourth selection pixel signals S<1:4> through the even-numbered readout lines EL1to EL4during a second single row time. For example, the image sensor100may generate the second pixel signal P<2>, the fourth pixel signal P<4>, the sixth pixel signal P<6> and the eighth pixel signal P<8> from pixels each having a green filters G among the pixels included in the fifth to eighth unit pixel circuits, and then sequentially generate the second pixel signal P<2>, the fourth pixel signal P<4>, the sixth pixel signal P<6> and the eighth pixel signal P<8> from pixels having other color filters R, G and B during the second single row time.

FIG.6is a diagram for describing the operation of the image sensor100according to the binning mode in accordance with an embodiment of the present disclosure.

Referring toFIG.6, the image sensor100may simultaneously output pixel signals, which correspond to pixels having the same color filter, from first to sixteenth unit pixel circuits. For example, the image sensor100may perform an analog binning operation, i.e., an averaging operation, on pixel signals generated from the first unit pixel circuit, the third unit pixel circuit, the ninth unit pixel circuit and the 11thunit pixel circuit to output the pixel signals as a first selection pixel signal S<1>, perform the analog binning operation, i.e., the averaging operation, on pixel signals generated from the second unit pixel circuit, the fourth unit pixel circuit, the 10thunit pixel circuit and the 12thunit pixel circuit to output the pixel signals as a second selection pixel signal S<2>, perform the analog binning operation, i.e., the averaging operation, on pixel signals generated from the fifth unit pixel circuit, the seventh unit pixel circuit, the 13thunit pixel circuit and the 15thunit pixel circuit to output the pixel signals as a third selection pixel signal S<3>, and perform the analog binning operation, i.e., the averaging operation, on pixel signals generated from the sixth unit pixel circuit, the eighth unit pixel circuit, the 14thunit pixel circuit and the 16thunit pixel circuit to output the pixel signals as a fourth selection pixel signal S<4>.

According to an embodiment of the present disclosure as described above, an analog binning operation in a horizontal direction as well as an analog binning operation in a vertical direction may be performed, and the number of bias circuits and the number of bias switches may be optimized according to design intent.

According to an embodiment of the present disclosure, an analog binning operation in a horizontal direction is performed in a binning mode, which makes it possible to improve a frame rate.

Furthermore, according to an embodiment of the present disclosure, a bias generator and a path selector necessary for reading out pixel signals are optimized, which makes it possible to achieve a low area design and ease of design or to improve a readout speed.

While the present disclosure has been illustrated and described with respect to specific embodiments, the disclosed embodiments are provided for the description, and not intended to be restrictive. Further, it is noted that the present disclosure may be achieved in various ways through substitution, change, and modification that fall within the scope of the following claims, as those skilled in the art will recognize in light of the present disclosure and the following claims. Furthermore, the embodiments may be combined to from additional embodiments.