Area efficient charge pump

A first charge pump includes a collection of voltage adder stages. The first voltage adder stage receives an input voltage VCC and in response to a clock signal provides a first voltage signal alternating between 2*VCC and VCC. The Nth voltage adder stage receives an input voltage VCC and a first voltage signal from the preceding stage, and provides a second voltage signal alternating between N*VCC and VCC. The capacitors included within each adder stage are required to sustain a maximum voltage of VCC. In an alternate embodiment the first charge pump may be combined with one or more voltage doubler stages to produce even higher output voltages.

FIELD OF THE INVENTION

This invention pertains generally to voltage generation circuits and more particularly to a charge pump circuit that is area efficient when implemented in applications such as an integrated circuit.

BACKGROUND OF THE INVENTION

Charge pumps use a switching process to provide a DC output voltage larger than its DC input voltage. In general, a charge pump will have a capacitor coupled to switches between an input and an output. During one clock phase, the charging half cycle, the capacitor couples in parallel to the input so as to charge up to the input voltage. During a second clock phase, the transfer half cycle, the charged capacitor couples in series with the input voltage so as to provide an output voltage twice the level of the input voltage. This process is illustrated inFIGS. 1aand1b. InFIG. 1a, the capacitor5is arranged in parallel with the input voltage VINto illustrate the charging half cycle. InFIG. 1b, the charged capacitor5is arranged in series with the input voltage to illustrate the transfer half cycle. As seen inFIG. 1b, the positive terminal of the charged capacitor5will thus be 2*VINwith respect to ground.

The generic charge pump described above will transfer power only during the transfer half cycle. U.S. Pat. No. 5,436,587, the contents of which are hereby incorporated by reference, discloses a charge pump having a voltage adder stage followed by a plurality of voltage doubler stages, wherein each stage transfers power on every clock phase. Each stage includes two capacitors that cycle according to a charging half cycle and a transfer half cycle as described above. However, the two capacitors are driven in a complementary fashion such that when one is charging the other is transferring power and vice versa. In this manner, each stage may transfer power during each clock phase. The voltage adder stage may be denoted an adder because, in response to receiving a DC supply voltage (VCC) and a CLK signal of amplitude VCC, the adder stage provides a DC output voltage equal to VCC+VCC. The voltage doubler stages are arranged in series such that the Nth voltage doubler stage receives as its input voltages the output voltages produced by the (N−1)th voltage doubler stage. The voltage doubler stages may be denoted as doublers because each voltage doubler stage receives an input voltage and provides an output voltage equaling twice its input voltage. Although the voltage doubler stages provide higher output voltages than that produced by the voltage adder stage, greater voltage stress occurs across the capacitors in the voltage doubler stages as compared to those in the voltage adder stage. Specifically, the capacitors in the Nth voltage doubler stage will have to withstand a voltage stress of VCC*2(N−1), whereas the capacitors in the voltage adder stage need withstand only a voltage stress of VCC. Because the capacitors in the voltage doubler stages must withstand greater voltage stresses, these capacitors require a thicker oxide insulation layer to prevent dielectric breakdown and shorting. In general, if the maximum voltage to be sustained between the plates of a capacitor is increased by a factor of m, the separation must also be increased by this same factor.

The thicker oxide required for the capacitors used in voltage doubler stages affects the chip area required for these stages as follows. Although this discussion assumes a parallel plate topology for the capacitors used, it is equally applicable to other capacitor topologies. A parallel plate capacitor's capacitance C is proportional to the area A of the capacitor's plates divided by their separation D. In an integrated circuit process a specific oxide thickness is generally provided that is optimized to reliably sustain the power supply voltage, VCC, and is typically called the gate oxide thickness. There is often one other oxide thickness provided that can reliably sustain the output voltage of the main charge pump, and this oxide may be referred to as the high voltage gate oxide. Typically this oxide thickness is 3 to 8 times thicker than that of the gate oxide and often only one type of transistor is provided with this oxide thickness (usually nMOS). Unfortunately it is very difficult and/or costly to provide additional oxides whose thickness can be optimized for any specific multiple of VCC. To achieve the same capacitance C as D is increased, the area A of each capacitor required to sustain more than VCC must also increase by a factor of 3 to 8, and this significantly decreases the amount of chip real estate available for other uses. This factor is so significant that the capacitor area may totally eclipse the area associated with all of the control transistors.

Another type of charge pump is disclosed in U.S. application Ser. No. 10/260,115 entitled “Charge Pump with Fibonacci Number Multiplication,” filed Sep. 27, 2002, the contents of which are hereby incorporated by reference. In this type of charge pump the voltage output of a given stage is the sum of the outputs of the preceding two stages. The disclosed implementation includes one capacitor per stage, but like that shown in U.S. Pat. No. 5,436,587 referenced earlier, the capacitor must be capable of sustaining a progressively higher voltage at each stage, and thus suffers the same disadvantage of large capacitor area.

Accordingly, there is a need in the art for area-efficient charge pumps.

SUMMARY

An area efficient charge pump is comprised of stages that successively boost voltage. Stages are configured so that individual capacitors in a stage do not have high voltages applied across their dielectric. Thus, even where a stage has a voltage output that is several times the input voltage of the charge pump, the capacitor dielectric is only subject to a voltage that is approximately the input voltage of the charge pump. This allows thinner capacitor dielectric to be used. Capacitors may thus be made smaller in area than they would be if they were to sustain high voltages.

In accordance with one aspect of the invention, a charge pump includes N voltage adder stages arranged in cascade. The first voltage adder stage receives a DC supply voltage VCC and is operable to provide, in response to a clock signal, a first voltage signal and its complement, the first voltage signal being substantially equal to 2*VCC during a first phase of the clock signal and VCC during a second phase of the clock signal, complement voltage signal being substantially equal to VCC during a first phase of the clock signal and 2*VCC during a second phase of the clock signal. The Nth voltage adder stage receives the (N−1)th voltage signal and its complement and is operable to provide, in response to the clock signal, a Nth voltage signal and its complement, the Nth voltage signal being substantially equal to (N+1)*VCC during the first phase of the clock signal and VCC during the second phase of the clock signal, the complement voltage signal being substantially equal to VCC during a first phase of the clock signal and (N+1)*VCC during a second phase of the clock signal.

In accordance with another aspect of the invention, the charge pump further includes a plurality of voltage doubler stages. A first voltage doubler stage in the plurality receives the Nth voltage signal and its complement, and provides a (N+1)th voltage signal and its complement to a second voltage doubler stage in the plurality, and so on. In general, a Kth voltage doubler stage in the plurality will receive the (K+N−1)th voltage signal and its complement, the kth voltage doubler stage operable to provide, in response to the clock signal, the (K+N)th voltage signal and its complement, the (K+N)th voltage signal being substantially equal to 2K*((N+1)*VCC) during the first phase of the clock signal and 2(K−1)*((N+1)*VCC) during the second phase of the clock signal. The complement of the (K+N)th voltage signal being substantially equal to 2(K−1)*((N+1)*VCC) during the first phase of the clock signal and 2K*((N+1)*VCC) during the second phase of the clock signal.

In accordance with yet another aspect of the invention, a method of generating a voltage output signal comprises receiving a supply voltage VCC and a clock signal. The supply voltage is added using two adder stages so as to produce a first voltage signal substantially equal to 3*VCC. The first voltage signal may then be doubled at least once to produce the voltage output signal. In general, if the first voltage signal is doubled N times, the voltage output signal will be substantially equal to 3*VCC*2N.

The following description and figures disclose other aspects and advantages of the present invention.

DETAILED DESCRIPTION

InFIG. 2, a circuit diagram for a first voltage adder stage12is illustrated. Two signals, CLK and its complement, CLKBAR, are inputs to this stage. These signals alternate between voltage levels VCC and ground at approximately a 50% duty cycle, such that when CLK is low, CLKBAR is high and when CLK is high, CLKBAR is low. In the description that follows, the voltage level of CLK will be defined as low (ground) during odd numbered half cycles, and high (VCC) during even numbered half cycles. For ease of explanation we will assume that the desired charge pump output voltage is positive with respect to a ground reference and that VCC is a more positive voltage than ground, but the techniques described are equally applicable to producing negative voltage charge pumps by suitable change of the reference level. As will be explained shortly, the name used to identify each voltage variable node, Vij with i and j as integers, is chosen to not only identify a unique node name but also indicate its approximate voltage levels in units of VCC during each of the two half cycles of CLK. For example, the voltage level on node V21will be substantially equal to 2*VCC during the odd half cycles of CLK and 1*VCC during even half cycles of CLK. Similarly the voltage level on node V12will be substantially equal to 1*VCC during the odd half cycles of CLK and 2*VCC during the even half cycles of CLK.

Referring toFIG. 2, the source of pMOS21is connected to an input voltage signal (shown in this figure as VCC) and its drain is connected to the drain of nMOS23as well as one side of capacitor25forming node V10. Similarly the source of pMOS22is connected to an input voltage signal (also shown as VCC) and its drain is connected to the drain of nMOS24as well as one side of capacitor26forming node V01. The source of both nMOS23and nMOS24are connected to ground. The other side of capacitors25and26are connected to output nodes V21and V12respectively. Also connected to V21is the source of nMOS27and the gate of nMOS28, and connected to V12is the source of nMOS28and the gate of nMOS27. The drain of both nMOS27and nMOS28are connected to VCC.

Capacitors25and26are typically formed from MOS transistors by connecting the source and drain together as one terminal and using the gate as the other terminal. Because the capacitance of an MOS transistor can vary with applied gate voltage, these transistors are preferably operated in the accumulation region as opposed to the inversion region commonly used in transistor operation, although operation in the inversion region is also possible. For example, if capacitor25is formed from a pMOS transistor, the source, drain, and local substrate (typically n-well) are connected together (indicated as the curved terminal) and attached to node V10, and the gate terminal (indicated as a flat plate) is attached to node V21. As will be demonstrated shortly, V21is more positive than node V10during each half cycle of CLK and thus attracts or accumulates electrons from the n-well to the surface. Under these conditions the capacitance is as large as possible and does not vary as the gate voltage changes.

The gates of nMOS23and a pMOS21both receive the CLK signal, and the gates of an nMOS24and a pMOS22receive the CLKBAR signal. During the odd half cycles of the CLK signal when CLK is low, pMOS21will be ON and nMOS23will be OFF. Because the source of pMOS21couples to the input voltage signal (VCC), node V10at the drain of pMOS21will be substantially equal to VCC during these odd half cycles. As will be explained further, during the even half cycles of the CLK signal, capacitor25will be charged such that node V21has a potential of VCC with respect to node V10. Thus, during the odd half cycles of the CLK signal, when node V10is charged to VCC, the output voltage on node V21will have a voltage substantially equal to 2*VCC. Note that the charge stored on capacitor25may have been depleted slightly due to charge sharing, capacitive coupling, and/or leakage effects. Thus, the voltage across capacitor25may be slightly less than VCC during this time. As used herein, a voltage signal “substantially equal” to a desired level is understood to include any such losses.

During the odd half cycle of the CLK signal, the CLKBAR signal will be high, turning nMOS24ON, pulling node V01towards ground. Because node V21has a voltage of 2*VCC at this time, nMOS28will be ON, bringing the output voltage on node V12substantially equal to VCC, such that capacitor26will be charged to VCC with respect to node V01. At the same time, the gate of nMOS27will be charged to VCC since it couples to node V12. Because the source of nMOS27connected to node V21is charged to 2*VCC at this time, nMOS27will be OFF, preventing voltage on node V21from discharging back through this transistor. In summary, during the odd half cycle the ON transistors are pMOS21, nMOS24, and nMOS28, and the OFF transistors are nMOS23, pMOS22, and nMOS27.

During the even half cycles of the CLK signal, nMOS23is ON, bringing node V10towards ground. Similarly pMOS22is ON, thereby charging node V01to VCC. Because capacitor26was charged to VCC during the odd half cycle of the CLK signal with output node V12being more positive than node V01as described above, charging node V01to VCC will cause the output voltage on node V12to be substantially equal to 2*VCC at this time. This voltage signal couples to the gate of nMOS27, turning it ON such that the output voltage at node V21will be substantially equal to VCC. In this fashion, capacitor25will be charged to VCC with respect to the grounded node V10, validating the earlier assumption. In turn, because the gate of nMOS28is charged to VCC whereas its source is charged to 2*VCC, nMOS28will be OFF preventing output voltage on node V12from discharging back through this transistor. In summary, during the even half cycle the ON transistors are pMOS22, nMOS23, and nMOS27, and the OFF transistors are nMOS24, pMOS21, and nMOS28.

Turning now toFIG. 3, the operation of second voltage adder stage14is analogous, having the same structure as first voltage adder stage12with corresponding elements referenced with identical numbers followed by prime (′). However, rather than receiving VCC as the input voltage signal to the sources of pMOS21′ and22′, second voltage adder stage14receives input voltage signals V21and V12from first adder stage12. Note that supply voltage VCC is still applied to nMOS27′ and28′. During the odd half cycles of the CLK signal, pMOS transistor21′ will be ON, bringing node V20to a voltage of 2*VCC. Assuming that capacitor25′ had been previously charged to VCC with respect to node V20, output voltage at node V31will be substantially equal to 3*VCC during the odd half cycles of the CLK signal. This output voltage couples to the gate of nMOS28′, switching it ON such that node V13will be charged to substantially VCC. This voltage signal couples to the gate of nMOS27′, switching it OFF and preventing output voltage on node V31from discharging back through this transistor. At the same time, nMOS24′ will be ON, pulling node V02towards ground such that capacitor26′ is charged to VCC with respect to node V02.

During the even half cycles of the CLK signal, nMOS23′ will be ON, pulling node V20towards ground. At the same time, pMOS22will be ON, charging node V02to a voltage of 2*VCC. Because capacitor26′ has already been charged to VCC with respect to node V02, the output voltage on node V13will be substantially equal to 3*VCC. In turn, this output voltage level for V13switches nMOS27′ ON, bringing output voltage on node V31to be substantially equal to VCC. Thus capacitor25′ will be charged to VCC with respect to grounded node V20. Because node V31is substantially equal to VCC at this time, nMOS28′ will be OFF, preventing the output voltage on node V13from discharging back through this transistor.

FIG. 4shows the Nth adder stage of a charge pump containing more than two adder stages and simply generalizes the principles discussed above in regards toFIGS. 2and3when multiple adder stages are cascaded. As in those previous figures, corresponding elements are indicated by the same number followed by a double prime (″). The complementary input voltage signals are VN1and V1N; if N is chosen to be 3, these would be identical with the outputs V31and V13of FIG.3. Referring to the voltage across capacitor25″, note that it is between nodes V(N+1)1and VN0, and that the net voltage across capacitor is always VCC, and similarly for capacitor26″. This is an important feature of cascaded adder charge pumps in that the large area capacitors can be fabricated with the same gate oxide as that used by the low voltage transistors, and are significantly smaller than capacitors used in doublers which are required to reliably sustain an applied voltage of N*VCC.

The operation of this stage is essentially identical to that ofFIGS. 2 & 3. During the odd half cycles when CLK is low, pMOS21″ is turned on and charges node VN0to N*VCC (the value of the input voltage VN1). Since capacitor25″ was previously charged to VCC with respect to node VN0, output node V(N+1)1rises to (N+1)*VCC. During the even half cycles when CLK is high, nMOS23″ discharges node VN0to ground, moving it by N*VCC. This change moves node V(N+1)1to VCC and nMOS27″ insures it remains no lower than VCC since the gate signal of nMOS27″ is more positive at (N+1)*VCC than either its drain or source. Now the general principle of this voltage adder can be seen in that VCC (from nMOS27″) is applied to the output side of the capacitor while its other side is grounded, and subsequently the ground is released and N*VCC (from the preceding stage) is applied causing the output node to rise to (N+1)*VCC, effectively adding VCC to the output of the preceding stage.

FIG. 5shows a block diagram of a charge pump5composed entirely of adder stages and an output stage. First stage12corresponds toFIG. 2; second stage14corresponds toFIG. 3; and Nth stage15corresponds to FIG.4. In practice the output signals V(N+1)1and V1(N+1) would be combined in such a way as to produce a constant output voltage VPP of value (N+1)*VCC. One method of accomplishing is shown in simplified form as stage19. In this circuit two diodes D1and D2are used to form the output voltage VPP. The anode of diode D1is connected to V(N+1)1and the anode of diode D2is connected to V1(N+1). The cathodes of both diodes are connected together to form the output voltage VPP. One way of implementing these diodes is to use a transistor and connect the gate and drain together as shown here. Preferably this transistor is a depletion nMOS device (shown in the diagram with a double line in the channel region) having a threshold voltage near 0 volts. In this case there will be negligible voltage drop across the diode connected transistor, and the output voltage will be close to (N+1)*VCC. If enhancement mode transistors are used, VPP would be reduced by the value of their threshold voltage.

The magnitude of the output current that this charge pump can supply to a load is principally determined by the absolute value of the capacitors and the clock frequency. Depending on the application, the output current may be relatively continuous (such as when driving a resistive load) or a transient current (such as when charging large amounts of circuit capacitance as, for example, a word line). During the odd half cycles of CLK when node V(N+1)1is supplying the output voltage (N+1)*VCC, charge is transported from capacitor25″ to the load (through diode D1). Since the current supplied by a capacitor is C*ΔV/ΔT where ΔV is the change in voltage across the capacitor and ΔT is the time period over which this current is supplied, for a given clock half cycle time (ΔT) and allowable change in output voltage (ΔV), the magnitude of the current is directly proportional to the value of C. Generally the value of the capacitance and the clock frequency should be chosen such that ΔV remains less than 1 volt. If the clock frequency is set too high, the internal power losses in the charge pump may become undesirable. These losses include charging and discharging the stray and parasitic capacitances (CV2f) and resistive losses in the MOS switches used to charge the main capacitors. One other feature to note about this charge pump is that the source of the output current is primarily from the VCC supply through nMOS27″ and nMOS28″, as these transistors directly charge the output capacitances, and thus supply the charge that is delivered to the load.

A charge pump comprising cascaded adder stages without multiplier stages can be advantageous when relatively lower output voltages and high currents are required because the smaller area of the capacitors required to sustain a maximum voltage of VCC more than offsets the additional number of stages required when compared to the conventional voltage doublers referenced earlier. However, typical flash EEPROM memory chips may require multiple charge pumps at differing power levels. Thus there may be situations where a number of cascaded adder stages may be desirably combined with one or more voltage multiplier stages. For example, if the output current required of the charge pump is relatively small, the size of the output capacitors may be such that the increased size of the internal capacitors needed in a doubler stage may be acceptable.

An example of a charge pump using both adder and doubler stages is illustrated inFIG. 6. Acharge pump6includes a first voltage adder stage12(such as that shown in FIG.2), a second voltage adder stage14, a first voltage doubler stage16, a second voltage doubler stage18, and an output stage20. Each stage receives a clock signal CLK and its complement clock signal CLKBAR. A detailed circuit diagram for doubler stage16is shown in FIG.7. Like the adder stages previously described, it includes four nMOS transistors, two pMOS transistors, and two capacitors, although they are connected differently. Unlike the adder, this stage does not use VCC as an input source of power, but extracts power from the complementary input signals V31and V13that in this example are obtained from the second adder stage14, which was previously described usingFIG. 3as an example. Input signal V31connects to the source of pMOS41whose drain is connected to the drain of nMOS43, one side of capacitor45, and the gate of pMOS42forming node V30. The gate of nMOS43is connected to CLK and its source is connected to ground. Similarly input signal V13connects to the source of pMOS42whose drain is connected to the drain of nMOS44, one side of capacitor46, and the gate of pMOS41forming node V03. The gate of nMOS44is connected to CLKBAR and its source is connected to ground. Input signal V31also goes to the drain of nMOS48whose gate is connected to HCLKBAR and in a similar fashion input signal V13goes to the drain of nMOS47whose gate is connected to HCLK. HCLK is a high voltage form of CLK. In this example it is generated in stage20(FIG. 9) and could also be labeled V12;0. When CLK is low, HCLK is low; when CLK is high (VCC level), HCLK is high (M*VCC), where M*VCC is at least as large as the maximum input voltage to this stage. HCLKBAR has the same voltage levels as HCLK but is complementary to it in the same way that CLKBAR is complementary to CLK, and in this example could be labeled V0;12. Finally the source of nMOS47and the other side of capacitor45are connected to form output node V63, and the source of nMOS48and the other side of capacitor46are connected together to form output node V36.

Operation of this circuit will now be described. During odd half cycles of the CLK signal, mMOS44will be ON, pulling node V03towards ground. In turn, the low voltage of node V03switches pMOS41ON, such that input voltage signal V31couples through this transistor and charges node V30to a voltage of 3*VCC. Assuming that capacitor45has been previously charged to 3*VCC with respect to node V30, output node V63at will be substantially equal to 6*VCC at this time. Because the high voltage clock HCLK is low during odd half cycles of the CLK signal, nMOS47is OFF, preventing voltage signal V63from discharging back through nMOS47into node V13, which is at VCC during these odd half cycles. At the same time, complementary high voltage clock HCLKBAR is high, switching nMOS48ON such that voltage signal V31will charge capacitor46to a voltage of 3*VCC with respect to node V03. Because of the high voltage 3*VCC at node V30, pMOS42is OFF, preventing the low voltage at node V03from pulling down voltage signal V13.

During even half cycles of the CLK signal, CLK is high, switching nMOS43ON to pull node V30low. The HCLK signal will also be high, switching nMOS47ON so that voltage signal V13will be coupled to node V63bringing it substantially equal to 3*VCC. In turn, this voltage at node V63will charge capacitor45to 3*VCC with respect to grounded node V30, as assumed in the previous discussion of the CLK odd half cycles. Because node V30is grounded, pMOS42will be ON, and input V13will bring node V03to a voltage of 3*VCC. At the same time, the CLKBAR signal will be low, switching nMOS44OFF, preventing node V03from being pulled to ground. In turn, because capacitor46was already charged to a voltage of 3*VCC with respect to node V03, node V36will be substantially equal 6*VCC. Signal HCLKBAR is low, thereby switching nMOS48OFF and preventing voltage signal V36from discharging back to V31through this transistor.

Turning now toFIG. 8, the construction and operation of second voltage doubler stage18is analogous, having the same structure as first voltage doubler stage16with corresponding elements referenced with identical numbers followed by prime (′). However, rather than receiving voltage signals V31and V13and produce voltage signals V63and V36, second voltage doubler stage18receives voltage signals V63and V36and produces voltage signals V12;6and V6;12. Similarly internal nodes V60and V06correspond to nodes V30and V03of FIG.7.

During odd half cycles of the CLK signal, CLKBAR is high, thereby switching nMOS44′ ON, pulling node V06towards ground. In turn, the low voltage at node V06switches pMOS41′ ON, pulling the voltage at node V60towards 6*VCC. Assuming that capacitor45′ has been charged to 6*VCC with respect to node V60in a previous half cycle, the voltage at node V12;6will be substantially equal to 12*VCC. Because HCLK′ is also low at this time, nMOS47′ is OFF, thereby preventing the voltage at node V12;6from discharging back through this transistor. Signal HCLKBAR′ will be high, thereby switching nMOS48′ ON such that node V6;12will have a voltage substantially equal to 6*VCC at this time. In addition, capacitor46′ will be charged substantially to a voltage of 6*VCC with respect to node V06.

During even half cycles of CLK, nMOS44′ and48′ will be OFF and nMOS43′ and47′ will be ON. Thus, the voltage at node V60will be pulled towards ground, thereby switching pMOS42′ ON. Accordingly, the voltage at node V06will rise to be substantially equal to 6*VCC. Because of the pre-charging of capacitor46′, voltage at node V6;12will thus be substantially equal to 12*VCC. At the same time, the voltage at node V12;6will be substantially equal to 6*VCC, thereby also charging capacitor45′ to substantially equal to 6*VCC with respect to node V60.

Note that voltage levels equaling 12*VCC may thus be produced using only 2 voltage doubler stages16and18, thereby minimizing the chip area required for charge pumps. Given voltage signals V12;6and V6;12, it will be appreciated that many types of circuits could be used to “rectify” the two signals to produce a 12*VCC volt DC signal VPP (FIG.9). Turning now toFIG. 9, a circuit diagram for an embodiment of an output stage20for producing signal VPP is illustrated. During odd half cycles of the CLK signal, CLKBAR will be high, thereby switching nMOS84ON and pulling node88towards ground. In turn, this brings the HCLK signal low. Because the gate of pMOS82will have a greater potential (12*VCC) than its source (6*VCC) and drain (node88or HCLK at ground), pMOS82will be OFF, preventing voltage signal V6;12from discharging into ground. At the same time, the gate of pMOS81will be charged to 6*VCC while its source is at 12*VCC, switching pMOS81ON and charging node87(HCLKBAR) to 12*VCC. Accordingly, the HCLKBAR signal will be substantially equal to 12*VCC at this time. Assuming that transistor capacitor85has been charged to 6*VCC with respect to node87, node89will be a voltage of 18*VCC. In turn, this high voltage at node89switches nMOS91ON, permitting signal VPP to be substantially equal to 12*VCC. The high voltage at node89will also switch nMOS94ON, permitting transistor capacitor86to be re-charged to a voltage of 6*VCC with respect to grounded node88. Because the gate and drain (V6;12) of nMOS92will be at the same potential, this transistor will be switched OFF, preventing signal VPP from discharging back through this transistor. In this case the terminal V6;12of nMOS92indicated as the drain is actually acting as a source since it is at a lower potential (6*VCC) than the indicated source (VPP=12*VCC). The 6*VCC voltage at node90will be transferred through ON pMOS86to the gate of nMOS93. Since its gate voltage (6*VCC) is less than its source (12*VCC) or drain (node89at 12*VCC) nMOS93will be OFF so that the high voltage at node89will not discharge back through this transistor.

During even half cycles of the CLK signal, nMOS83will be switched ON, pulling node87(HCLKBAR) towards ground. The gate of pMOS82will be 6*VCC, lower than its source (V6;12at 12*VCC) so that this transistor will be switched ON, permitting the HCLK signal at node88to rise to be substantially equal to 12*VCC volts. Signal CLKBAR will be low, thereby switching nMOS84OFF and preventing the HCLK signal from discharging into ground. Following the nomenclature used earlier, HCLK could also be named V12;0and HCLKBAR could be named V0;12. At the same time, the gate of pMOS81will be at 12*VCC, higher than that of its source (V12;6which is at 6*VCC), switching this transistor OFF. Because transistor capacitor86was previously charged to 6*VCC with respect to node88, node90will have a potential of 18*VCC, switching nMOS92ON to keep output signal VPP at substantially 12*VCC volts. The high voltage at node90will also switch nMOS93ON, permitting transistor capacitor85to re-charge to 6*VCC volts with respect to node87and node89will be at 6*VCC. Because the gate and drain of nMOS91are at the same potential, this transistor will be switched OFF, preventing signal VPP from discharging back through this transistor. With its gate at a potential of 6*VCC, and its source at 12*VCC, and its drain at 18*VCC, nMOS94will also be switched OFF, preventing node90from discharging back to V6;12through this transistor.

It will be appreciated that charge pump10ofFIG. 9may be modified to include additional voltage double stages having the same structure as first and second voltage doubler stages16and18. Thus, there would be a plurality of N voltage doubler stages, starting with the first voltage doubler stage16, followed by the second voltage doubler stage18and so on up to the Nth voltage doubler stage in the plurality. Referring back toFIG. 2, it can be seen that the first voltage adder stage12provides the first and second voltage signals in the form of V21and V12, respectively. The second voltage adder stage14receives these signals and provides the third and fourth voltage signals in the form of V31and V13, respectively. The first voltage doubler stage16receives V31and V13and provides the fifth and sixth voltage signals in the form of V63and V36, respectively. The second voltage doubler stage18receives V63and V36and provides the seventh and eighth voltage signals, V12;6and V6;12, respectively. Should there be a third voltage doubler stage, it would receive V12;6and V6;12and provide the ninth and tenth voltage signals V24;12and V12;24, respectively. In this fashion, the Nth voltage doubler stage in the plurality would receive the voltage signals from the (N−1)th voltage doubler stage and provide the (2*N+3)th and the (2*N+4)th voltage signals, where the (2*N+3)th voltage signal would be substantially equal to 2N*3*VCC volts during odd half cycles of the CLK signal and would be substantially equal to 2(N−1)*3*VCC volts during even half cycles of the CLK signal. The (2*N+4)th voltage signal would be complementary to the (2*N+3)th voltage signal. In turn, output stage20would receive the voltage signals from the Nth and final voltage doubler stage in the plurality and produce a VPP signal having an amplitude substantially equal to 2N*3*VCC volts.

In the charge pump ofFIG. 6the HCLK and HCLKBAR signals required by each doubler stage are derived from a common output stage. Thus the signals labeled HCLK and HCLKBAR inFIG. 7corresponding to stage16of FIG.6and HCLK′ and HCLKBAR′ inFIG. 8corresponding to stage18ofFIG. 6are shown connected to the HCLK and HCLKBAR outputs respectively from output stage20.FIG. 10shows an alternate embodiment in which the input signals HCLK and HCLKBAR of doubler stage N are derived from additional output signals from stage N+1, and only the last doubler stage receives these signals from the output stage. In this figure, all stages are numbered identically to their corresponding stages inFIG. 6with the addition of a prime (′). In the earlier discussion ofFIG. 9, it was noted that HCLK could alternately be labeled as V12;0and HCLKBAR as V0;12. Referring toFIG. 7(first doubler stage) it is observed that an HCLK and HCLKBAR signal of amplitude 6*VCC is sufficient to pass the input voltage of 3*VCC to the output nodes, and similarly an amplitude of 0 volt is sufficient to block the discharge of the 6*VCC signal back to the input. Thus a V60 signal can be substituted for a V12;0 signal (HCLK), and it is sufficient that the HCLK and HCLKBAR signals come from the succeeding stage rather than from the output stage. The advantage of this embodiment is that a lower voltage signal is used on the gate and in some device technologies this may reduce the size or complexity of the associated transistors, as well as potentially increase the reliability.

The capacitors in the first voltage adder stage12and output stage20may be precharged so that charge pump10may begin cycling. For example,FIGS. 11aand11billustrate circuits for precharging capacitors25and26, respectively, of first voltage adder stage12at power on. By applying a voltage VON through diode transistors95and96to the nodes29and30, respectively, a precharge of VON (which may equal VCC) less the threshold voltage of nMOS transistors31and32is placed across each of the capacitors25and26to initialize first voltage adder stage12. If both CLK and CLKBAR are initially held constant at VCC before charge pump operation is started, both nodes V10and V01ofFIG. 2will be forced to ground such that the full VON voltage will be placed across these capacitors. As the pump begins and reaches steady state, the diode connection prevents nodes V21and V12from discharging back to VON. Similarly,FIGS. 10cand10dillustrate circuits for precharging the transistor capacitors85and86, respectively of FIG.9. By applying VON through diode transistors97and98to nodes89and90, respectively, a precharge of VON is placed across each of transistor capacitors85and86. Similar circuits could be used to precharge the capacitors in the remaining stages of charge pump10. In practice, however, the four precharge circuits ofFIGS. 11a-11dhave been found to provide satisfactory results.

Although the invention has been described with reference to particular embodiments, the description is only an example of the invention's application and should not be taken as a limitation. Consequently, various adaptations and combinations of features of the embodiments disclosed are within the scope of the invention as encompassed by the following claims.