Control circuit for step-up DC/DC converter

A switching transistor is configured such that its on resistance RON is switchable between at least two values RON1 and RON2. When the switching transistor is switched from off to on, a control circuit sets the on resistance of the switching transistor to the first value RON1 for a first period immediately after the switching of the switching transistor. Subsequently, for a second period until the switching transistor is turned off, the control circuit sets the on resistance of the switching transistor to the second value RON2 that is smaller than the first value RON1.

CROSS-REFERENCE TO FOREIGN PRIORITY

The present invention claims priority under 35 U.S.C. §119 to Japanese Application No. 2013-073355 filed Mar. 29, 2013, the entire content of which is incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a step-up DC/DC converter.

2. Description of the Related Art

In order to generate a voltage that is higher than the input voltage, a step-up DC/DC converter (switching regulator) is employed.FIG. 1is a circuit diagram showing a typical configuration of a step-up DC/DC converter100r. The step-up DC/DC converter100rincludes an inductor L1, an output capacitor C1, a switching transistor M1, a rectifier diode D1, and a control circuit2r.

The control circuit2ris configured in the form of a package, which is mounted on a common printed circuit board (PCB) on which the inductor L1, the rectifier diode D1, and the output capacitor C1are also mounted. The switching transistor M1is integrated on a semiconductor chip4included in the control circuit2r.

The voltage (output voltage) VOUTat the output terminal POUTis divided by resistors R1and R2, and the voltage thus divided is fed back to a voltage detection terminal VS of the control circuit2r. The control circuit2rcontrols the switching of the switching transistor M1such that the feedback voltage VSapproaches a predetermined target voltage VREF.

The semiconductor chip4included in the control circuit (package)2rincludes a pulse modulator10, a driver12, and a transmission path14, in addition to the switching transistor M1.

The pulse modulator10adjusts the duty ratio of the pulse signal SPWM, i.e., its output signal, such that the feedback voltage VSapproaches the predetermined target voltage VREF. The driver12drives the switching transistor M1according to the pulse signal S. Related techniques have been disclosed in Japanese Patent Application Laid Open No. 2009-55708, for example.

The present inventors have investigated the DC/DC converter100rshown inFIG. 1, and have come to recognize the following problem.

In the DC/DC converter100rshown inFIG. 1, there are parasitic inductances LPKG1and LPKG2within the control circuit2rconfigured as a semiconductor package, and there is a parasitic inductance LSUBand a parasitic resistance RSUBon the printed circuit board mounting the control circuit2r.

In the off period of the switching transistor M1, the rectifier diode D1is biased in the forward direction by means of the electromotive force generated by the coil. In this state, charge is accumulated in the rectifier diode D1. Subsequently, after the switching transistor M1transits to on, the charge stored in the rectifier diode D1flows toward the switching transistor M1due to the reverse recovery property of the rectifier diode D1. The charge flows to the ground of the printed circuit board via the switching transistor M1. That is to say, during the reverse recovery time TRRof the rectifier diode, the rectifier diode D1can be regarded as a capacitance COJ.

Thus, during the reverse recovery time TRR, a loop including the output capacitor C1, the rectifier diode D1, the switching transistor M1, and the ground line forms a series RLC resonance circuit. It should be noted that the capacitance value of the output capacitor C1is sufficiently large as compared with the capacitance COJof the rectifier diode D1. Thus, with such a series connection with the rectifier diode D1, the effect of the capacitance value of the output capacitor C1is negligible.

In the on state of the switching transistor M1, ideally, the voltage (which is also referred to as the “switching voltage) VSWat the switching (SW) terminal is 0 V. However, in some cases, immediately after the transition to the on state, the switching voltage VSWand the output voltage VOUToscillate at a resonance frequency ωo=1√(LC) [rad] of the RLC resonance circuit.
L≈LPKG1+LPKG2+LSUB
C≈COJ

The oscillation of the switching voltage VSWand/or the output voltage VOUTis emitted to the outside in the form of electromagnetic noise. Thus, in a case in which the resonance frequency ωois within a frequency band to be controlled as specified by an EMI standard, an EMI countermeasure must be applied. Typical examples of conceivable EMI countermeasures include: a method in which the circuit is covered by an electromagnetic shielding material; a method in which the value of the inductor L1is adjusted; and the like. However, such methods lead to an increased cost, and require such adjustments to be repeatedly performed by means of a trial and error approach.

SUMMARY OF THE INVENTION

The present invention has been made in order to solve such a problem. Accordingly, it is an exemplary purpose of an embodiment of the present invention to provide a technique for suppressing oscillation and ringing in the switching voltage VSWand the output voltage VOUTfor the reverse recovery time TRRof a rectifier diode D1.

An embodiment of the present invention relates to a control circuit for a step-up DC/DC converter. The step-up DC/DC converter comprises an inductor, a rectifier diode, an output capacitor, and a switching transistor. The switching transistor is configured such that its on resistance is switchable between at least two values. The control circuit is configured such that, when the switching transistor is switched from off to on, the control circuit sets the on resistance of the switching transistor to a first value for a first period immediately after the switching of the switching transistor, following which the control circuit sets the on resistance of the switching transistor to a second value that is smaller than the first value for a second period until the switching transistor is turned off.

During the reverse recovery time immediately after the switching transistor is turned on, an RLC resonance circuit comprising the capacitance component of the rectifier diode is formed. In this state, a current discharged from the capacitance component COJof the rectifier diode flows through the RLC resonance circuit, whereby resonance can occur. Here, the attenuation coefficient ξ of the series RLC circuit is represented by the following Expression.
ξ=R/(2√(L/C))

In the first period, which overlaps the reverse recovery time, the on resistance of the switching transistor is set to a first value which is relatively high, thereby raising the attenuation coefficient ξ. Thus, such an arrangement is capable of suppressing resonance. Alternatively, even if resonance occurs, such an arrangement is capable of settling the resonance in a short period of time by means of strong damping.

Also, the first period may be configured to have a length which is equal to or otherwise greater than the reverse recovery time of the rectifier diode.

In a case in which the first period is shorter than the reverse recovery time, the reverse recovery time continues even after the first period ends. With such an arrangement, when the on resistance of the switching transistor is switched to the second value, which is relatively low, after the first period has ended, in some cases, the relation ξ<1 holds true, which satisfies the condition for resonance. In this state, if the resonance energy in the resonance circuit is not sufficiently damped in the first period, there is a risk of oscillation in the switching voltage or the output voltage.

With the embodiment, the first period is set to a length which is equal to or greater than the reverse recovery time, thereby preventing oscillation in the switching voltage and the output voltage in a sure manner.

Also, with the series resistance component of a loop comprising the output capacitor, the rectifier diode, the switching transistor, and a ground line as R, with the capacitance component of this loop as C, and with the series inductance component of this loop as L, the first value may be determined such that the relation R/(2×√(L/C))>1 is satisfied.

In this case, the condition for resonance is not satisfied, thereby suppressing oscillation and ringing in the switching voltage and the output voltage.

In order to avoid resonance at a predetermined frequency fc, with the series resistance component of a loop comprising the output capacitor, the rectifier diode, the switching transistor, and a ground line as R, and with the capacitance component of this loop as C, the first value may be determined such that the relation R=1/(π×fc×C)) is satisfied.

Even in a case in which it is difficult to estimate the inductance value, such an arrangement is capable of suppressing oscillation and ringing in the switching voltage and the output voltage at a predetermined frequency fc.

Also, the control circuit may be configured to be capable of adjusting the length of the first period according to the reverse recovery time of the rectifier diode.

Also, the control circuit may be configured to be capable of adjusting the first value according to the capacitance value of the rectifier diode.

Also, the switching transistor may comprise multiple transistor elements connected in parallel such that their control terminals are arranged independently. Also, the control circuit may be configured to switch the on-state transistor element according to switching between the first period and the second period, thereby switching the on resistance of the switching transistor corresponding to a combined resistance of the multiple switching elements.

Also, the control circuit may comprise: a pulse modulator configured to generate a pulse signal having a duty ratio adjusted such that a feedback voltage that corresponds to an output voltage of the step-up DC/DC converter approaches a predetermined target voltage; a first driver configured to drive a first transistor element configured as a transistor element which is to be turned on for at least the first period, on the basis of the pulse signal; and a second driver configured to drive a second transistor element configured as a transistor element which is to be turned on only for the second period, on the basis of the pulse signal.

Such an arrangement allows the first value and the second value of the on resistance to be designed based on the size and the gate-source voltage of each of the first transistor element and the second transistor element.

Also, the control circuit may further comprise a variable delay circuit configured to apply, to a gate pulse signal to be supplied to the second transistor element, a delay that is adjustable according to the reverse recovery time of the rectifier diode that is actually employed.

This allows the length of the first period to be optimized according to the reverse recovery time.

Also, the control circuit may further comprise a driving adjustment circuit configured to adjust the on resistance of the first transistor element according to the capacitance of the rectifier diode that is actually employed.

This allows the first value of the on resistance to be optimized according to the capacitance of the rectifier diode.

Also, the driving adjustment circuit may be configured to change the amplitude (high level voltage) of a gate pulse signal to be supplied to a control terminal of the first transistor element.

Also, the control circuit may further comprise a register configured to store data which represents at least one from among the reverse recovery time and the capacitance of the rectifier diode that is actually employed, or otherwise an external setting terminal configured to allow settings to be made for at least one from among the reverse recovery time and the capacitance of the rectifier diode that is actually employed.

Also, the control circuit may further comprise a capacitance detection circuit configured to detect the capacitance COJof the rectifier diode by integrating a current that flows when the switching transistor is turned on after the rectifier diode is charged using a predetermined voltage.

After the switching transistor is turned off, the capacitance component COJis charged according to the voltage difference ΔV between the current input voltage and the current output voltage. In this case, the charge amount Q stored in the capacitance COJis represented by the following Expression.
Q=COJ·ΔV

Subsequently, when the switching transistor M1is turned on, the discharge current flows through the switching transistor M1. By integrating the discharge current, such an arrangement is capable of calculating the charge amount Q. When the voltage difference ΔV is a known value, such an arrangement is capable of calculating the capacitance COJof the rectifier diode.

Also, the control circuit may further comprise a time measurement circuit configured to detect the reverse recovery time of the rectifier diode based on the waveform of a current that flows when the switching transistor is turned on after the rectifier diode is charged using a predetermined voltage.

Also, the control circuit may monolithically be integrated on a single semiconductor chip. Also, the switching transistor may monolithically be integrated on the control circuit.

Examples of such a “monolithically integrated” arrangement include: an arrangement in which all the circuit components are formed on a semiconductor chip; and an arrangement in which principal circuit components are monolithically integrated. Also, a part of the circuit components such as resistors and capacitors may be arranged in the form of components external to such a semiconductor chip in order to adjust the circuit constants. By integrating the circuit in the form of a single IC, such an arrangement provides an advantage of a reduced circuit area, and an advantage of maintaining uniform circuit element characteristics.

Another embodiment of the present invention relates to a step-up DC/DC converter. The step-up DC/DC converter comprises: an inductor having one end via which an input voltage is to be applied; a switching transistor arranged between a second end of the inductor and a ground line; a rectifier diode having an anode connected to the second end of the inductor; an output capacitor arranged between a cathode of the rectifier diode and the ground line; and the aforementioned control circuit configured to perform switching of the switching transistor.

Yet another embodiment of the present invention relates to an electronic device. The electronic device comprises the aforementioned switching power supply.

Yet another embodiment of the present invention relates to a vehicle. The vehicle comprises: a battery; and the aforementioned switching power supply configured to step up the voltage supplied by the battery.

DETAILED DESCRIPTION OF THE INVENTION

In the present specification, a state represented by the phrase “the member A is connected to the member B” includes a state in which the member A is indirectly connected to the member B via another member that does not affect the electric connection therebetween, in addition to a state in which the member A is physically and directly connected to the member B.

Similarly, a state represented by the phrase “the member C is provided between the member A and the member B” includes a state in which the member A is indirectly connected to the member C, or the member B is indirectly connected to the member C via another member that does not affect the electric connection therebetween, in addition to a state in which the member A is directly connected to the member C, or the member B is directly connected to the member C.

FIG. 2is a circuit diagram showing a schematic configuration of a step-up DC/DC converter (which will also be referred to simply as the “DC/DC converter” hereafter)100. The DC/DC converter100steps up the input voltage VINinput via an input line102, and supplies, to a load (not shown) connected to an output line104, an output voltage VOUTstabilized to the target level.

The DC/DC converter100includes an inductor L1, a switching transistor M1, a rectifier diode D1, an output capacitor C1, a feedback circuit108, and a control circuit2. A first end of the inductor L1is connected to the input line102. The switching transistor M1is arranged between a second end of the inductor L1and a ground line106. The output capacitor C1is arranged between the output line104and the ground line106. The rectifier diode D1is connected such that its anode is connected to the second end of the inductor L1and its cathode is connected to the output line104. The feedback circuit108includes resistors R1and R2, and is configured to divide the output voltage VOUT, and to supplies the output voltage VOUTthus divided to a voltage feedback (VS) terminal of the control circuit2.

The control circuit2controls the switching of the switching transistor M1such that the feedback voltage VSat the VS terminal approaches a predetermined target voltage VREF. With the present embodiment, the control circuit2is configured as a function IC (Integrated Circuit) in the form of a package. That is to say, the circuit elements and wiring that form the control circuit2are integrated on a single semiconductor chip4.

The switching transistor M1is built into the control circuit2. It should be noted that, as the switching transistor M1, a bipolar transistor or otherwise an IGBT may be employed instead of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor).

With the control circuit2, the switching transistor M1is configured such that its on resistance RONis switchable between at least two values. With the present embodiment, the on resistance RONis switchable between two values, i.e., between a first value RON1and a second value RON2that is sufficiently lower than the first value RON1.

The second value RON2is determined so as to satisfy requirements such as the efficiency required for the DC/DC converter. Typically, the second on resistance RON2is preferably set to as low a value as possible. Specifically, the second on resistance RON2is set to a value ranging between several mΩ and several tens of mΩ. The setting of the first value RON1will be described later.

The control circuit2includes a pulse modulator10, a driver12, and an on resistance controller16, in addition to the switching transistor M1. The pulse modulator10generates a pulse signal SPWMhaving a duty ratio adjusted such that the output voltage VOUTof the DC/DC converter100approaches a predetermined target voltage. Typically, the pulse modulator10instructs an error amplifier (not shown) to amplify the difference between the feedback voltage VSand a predetermined reference voltage VREFso as to generate an error signal VFB. Subsequently, the pulse modulator10converts the error signal VFBthus generated into a pulse signal SPWMhaving a duty ratio that corresponds to the voltage level of the error signal VFB. The modulation method of the pulse modulator10is not restricted in particular. Examples of pulse modulators which can be employed as the pulse modulator10include voltage mode pulse modulators, current mode pulse modulators, hysteresis control modulators, and the like. The configuration of the pulse modulator10is not restricted in particular.

The driver12performs switching of the control terminal (gate) of the switching transistor M1according to the pulse signal SPWM.

When the switching transistor M1is switched from off to on, in a first period T1immediately after the switching, the on resistance controller16sets the on resistance RONof the switching transistor M1to the first value RON1. After the first period T1elapses, in a second period T2until the switching transistor M1is turned off, the on resistance controller16sets the on resistance RONof the switching transistor M1to the second value RON2that is lower than the first value RON1.

The on resistance controller16may switch the transistor size of the switching transistor M1so as to change the on resistance RON, for example. Also, the on resistance controller16may switch the amplitude of the gate voltage (high level voltage) of the switching transistor M1so as to change the on resistance RON.

It should be noted that the on resistance controller16is not necessarily required to be configured as a specified component built into the control circuit2. Rather, the control circuit2may preferably be configured such that the switching between the first period T1and the second period T2is controlled in the overall control operation of the control circuit2.

The above is the configuration of the control circuit2and the DC/DC converter100employing the control circuit2.

FIGS. 3A and 3Bare equivalent circuit diagrams each showing the DC/DC converter100in the on period of the switching transistor M1.FIG. 3Ashows an equivalent circuit for the reverse recovery time TRRof the rectifier diode D1immediately after the switching transistor M1is turned on.FIG. 3Bshows an equivalent circuit after the reverse recovery time TRRelapses.

In the reverse recovery time TRR, the rectifier diode D1can be regarded as the capacitance COJ. In addition to the current that flows in the forward direction (direction from the anode to the cathode), in the reverse recovery time TRR, discharge current flows through the rectifier diode D1in the reverse direction (direction from the cathode to anode) from the capacitance COJ.

As shown inFIG. 3A, a loop comprising the output capacitor C1, the rectifier diode D1, the switching transistor M1, and the ground line106forms a series RLC resonance circuit. With the series resistance component of the loop as R, with the capacitance component of the loop as C, and with the series inductance component of the loop as L, the attenuation coefficient ξ is represented by the following Expression (1).
ξ=R/(2√(L/C))  (1)

Here, ΣRp represents the summation of the parasitic resistance components formed in the loop, and ΣLp represents the summation of the parasitic inductance components formed in the loop.

With such an RLC resonance circuit, in a case in which the relation ξ<1 holds true, this leads to damped oscillation of the system. Here, the damping time constant τ is represented by the following Expression (2).
τ=2L/R(2)

Thus, as the value of R becomes greater, the oscillation damping becomes faster.

If the value of R is further raised such that the relation ξ>1 holds true, the system is exponentially damped without oscillation.

As shown inFIG. 3B, after the reverse recovery time TRRhas elapsed, the RLC resonance circuit is shut off by means of the rectification function of the rectifier diode D1. Thus, in this stage, there is no oscillation in the switching voltage VSW.

FIG. 4is a simulation waveform diagram showing a state of the RLC resonance circuit shown inFIG. 3A.FIG. 4shows a current waveform with L=30 nH, and with C=85 PF when the resistance value R is changed.

With the control circuit2shown inFIG. 2, in the first period T1that overlaps the reverse recovery time TRRwhen damped oscillation can occur in the RLC resonance circuit, by setting the on resistance RONof the switching transistor M1to RON1such that the relation ξ>1 holds true, i.e., such that Expression (3) holds true, such an arrangement is capable of suppressing oscillation in the switching voltage VSWand the output voltage VOUT.
R>(2√(L/C))  (3)

For example, in a case in which the sum total of the parasitic inductance components L is 30 nH, and the capacitance COJof the rectifier diode D1is 85 pF, RON1may preferably be determined such that the relation R>(2√(30 nH/85 pF))≈38Ω holds true. For example, in a case in which the sum total of parasitic resistance components ΣRp is 8Ω, RON1is preferably set to be higher than 30Ω, thereby suppressing oscillation in the switching voltage VSWand the output voltage VOUT.

There are multiple kinds of printed circuit boards, and in some cases the parasitic inductance cannot be estimated. Even in this case, if the resonance frequency to be avoided is known, with the resonance frequency to be avoided as fc, the resistance value which allows resonance to be avoided only at the resonance frequency fc can be calculated based on the following Expressions, so as to avoid resonance at that frequency.
fc=1/(2π√(L×C))
√L=1/(2πfc√C))
R=2√R/√C=2/(2π×fc×√C×√C)=1/(π×fc×C)>1

Thus, R which satisfies the relation ξ>1 is represented by the following Expression.
R=1/(π×fc×C).

For example, in a case in which fc=80 MHz, R is determined to be 46Ω based on the relation expression R=1/(π×80 MHz×85 pF).

In a case in which the first period T1is shorter than the reserve recovery time TRR, the reverse recovery time TRRcontinues after the first period T1ends. If the on resistance of the switching transistor M1is switched to the second value RON2having a relatively low value after the first period T1ends, in some cases, the condition for resonance, i.e., the relation ξ<1, is satisfied. In this case, if the resonance energy that occurs in the resonance circuit is not sufficiently damped in the first period T1, in some cases, there is a risk of oscillation in the switching voltage VSWor the output voltage VOUT.

In order to solve such a problem, by setting the relation T1≧TRR, such an arrangement ensures that there is no oscillation in the reverse recovery time TRR. Otherwise, even if resonance occurs, such an arrangement ensures that the resonance settles in a short period of time.

It should be noted that, if the on resistance of the switching transistor M1is maintained at the first value RON1after the reverse recovery time TRRelapses, this leads to a problem of increased switching loss although there is no risk of resonance. Thus, the first period T1is preferably set to be as short as possible while satisfying the relation T1≧TRR.

FIG. 5Ais a waveform diagram showing the operation of the control circuit2.FIG. 5Bis a waveform diagram showing the operation of the control circuit2rshown inFIG. 1.

In order to clarify the advantage of the control circuit2shown inFIG. 2, first, description will be made with reference toFIG. 5Bregarding the operation of the control circuit2raccording to a conventional technique. In the drawing, the second and subsequent waveforms are shown with an expanded time scale.

During the period from the time point t0to the time point t1, the switching transistor M1is turned off. In this period, the switching voltage VSWis set to (Vout+VF). Here, VFrepresents the forward voltage of the rectifier diode D1.

At the time point t1, the pulse signal SPWMis switched to high level, which turns on the switching transistor M1. With the control circuit2rshown inFIG. 1, at the time point t1, the on resistance RONof the switching transistor M1is reduced to a value that corresponds to the second value RON2.

The on resistance RON2is very low. This reduces the value of the resistance R in Expression (1), leading to a situation in which ξ<<1. As a result, damped oscillation occurs in the RLC resonance circuit. The damping time constant τ is represented by Expression (2). Thus, as the resistance value R becomes lower, the time constant τ becomes greater. As a result, with the control circuit2rshown inFIG. 1, great oscillation occurs in the output voltage VOUTand the switching voltage VSW, leading to the occurrence of electromagnetic noise.

Next, description will be made with reference toFIG. 5Aregarding the operation of the control circuit2shown inFIG. 2. Description will be made below assuming that the relation T1>TRRholds true, and the relation ξ>1 holds true.

At the time point t1, the pulse signal SPWMis switched to high level, which turns on the switching transistor M1.

In the first period T1after the pulse signal SPWMis switched to high level, the on resistance controller16sets the on resistance of the switching transistor M1to the first value RON1. In this state, the relation ξ>1 holds true, and resonance is suppressed.

After the first period T1ends, the period becomes the second period T2. In this period, the on resistance controller16sets the on resistance of the switching transistor M1to the second value RON2. This allows the switching loss of the switching transistor M1to be reduced.

A control circuit, a DC/DC converter, and a control method for a DC/DC converter based on the concept described above are encompassed within the technical scope of the present invention.

Description will be made below regarding a specific configuration of the control circuit2with reference to embodiments.

First Embodiment

FIG. 6is a circuit diagram showing a configuration of a control circuit2aaccording to a first embodiment.

With the first embodiment, the switching transistor M1includes at least two transistor elements, e.g., transistor elements M11and M12, (description will be made in the present embodiment regarding a switching transistor M1comprising two transistor elements) configured such that their drains are connected in common, their sources are connected in common, and their control terminals (gates) are each configured independently, i.e., such that the transistor elements are connected in parallel.

The control circuit2instructs the on resistance controller16shown inFIG. 2to switch the on-state transistor element between the transistor elements M11and M12according to the first period T1and the second period T2. Thus, such an arrangement is capable of switching the on resistance RONof the switching transistor M1between two values that correspond to the combined resistance of the multiple transistor elements.

The first transistor element M11is turned on at least for the first period T1. For the second period T2, the first transistor M11may be turned on. Otherwise, the first transistor M11may be turned off. Description will be made below in the present embodiment regarding an arrangement in which the switching transistor element M11is turned on for both the first period T1and the second period T2.

The second transistor element M12is turned on only for the second period T2.

The driver12includes a first driver DR1and a second driver DR2. The first driver DR1sets the gate pulse signal SG1to high level so as to turn on the first transistor element M11for the first period T1and the second period T2, i.e., the whole on period TONwhen the switching transistor M1is to be turned on. During the second period T2, the second driver DR2sets to the gate pulse signal SG2to high level so as to turn on the second transistor element M12.

The propagation delay T1that occurs due to the path between the first driver DR1and the gate of the first transistor element M11and the propagation delay t2that occurs due to the path between the second driver DR2and the gate of the second transistor element M12may be configured such that there is a difference of Δτ between them. In this case, after the propagation delay τ1elapses after the pulse signal SPWMtransits to high level, the first transistor M11is turned on, and after the propagation delay τ2elapses after the pulse signal SPWMtransits to high level, the second transistor element M12is turned on. Thus, the time difference Δτ=(τ2−τ1) corresponds to the first period T1.

In the control circuit2ashown inFIG. 6, it can be said that a component comprising the switching transistor M1having the first transistor element M11and the second transistor element M12each configured as a separate transistor element, the driver12having the first driver DR1and the second driver DR2each configured as a separate driver, and propagation paths14_1and14_2which respectively provide the propagation delays τ1and τ2corresponds to the on resistance controller16shown inFIG. 2.

It should be noted that the propagation paths14_1and14_2having a delay difference may be arranged as upstream components of the first driver DR1and the second driver DR2. With such an arrangement, there is a difference between the delay T1that occurs in the pulse signal SPWMsupplied to the first driver DR1and the delay T2that occurs in the pulse signal SPWMsupplied to the second driver DR2.

The above is the configuration of the control circuit2a.

FIG. 7is an operation waveform diagram of the control circuit2ashown inFIG. 6. At the time point t1, the pulse signal SPWMis switched from the off time TOFFto the on time TON. When the first driver DR1receives the signal transition, the first driver DR1turns on the first transistor element M11. In this stage, the whole on resistance RON1of the switching transistor M1becomes RON11. It should be noted that RON11represents the on resistance of the first transistor element M11.

Subsequently, the period progresses to the second period T2after the first period T1from the time point t1, and the second transistor M12is turned on by the second driver DR2. For the second period T2, the whole on resistance RON2of the switching transistor M1is represented by (RON11//RON12). Here, RON12represents the on resistance of the second transistor M12, and the symbol “//” is an operator which represents the combined resistance of two resistance components connected in parallel.

With the configuration shown inFIG. 7, such an arrangement allows the on resistance RONof the switching transistor M1to be switched between multiple values.

FIG. 8is a diagram showing a spectrum (i) of the current that flows through the DC/DC converter100ashown inFIG. 6. Also,FIG. 8shows a spectrum (ii) of the current that flows through the DC/DC converter100rshown inFIG. 1. As can be clearly understood fromFIG. 8, with the DC/DC converter100ashown inFIG. 6, such an arrangement is capable of providing a great reduction in the current magnitude, in the vicinity of 100 MHz.

Second Embodiment

As described above, in order to suppress resonance for the reverse recovery time TRR, it is desirable for the relation ξ>1 to be satisfied in the first period T1which is determined such that the relation T1≧TRRholds true.

It can be assumed that there is a difference in the reverse recovery time TRRof the rectifier diode D1between the value of the step-up DC/DC converter100that is manufactured by assembling the components such as the control circuit2, the rectifier diode D1, etc., and the design value estimated in the original design stage, due to modification of the specifications of the rectifier diode D1. Thus, if the length of the first period T1is fixed in the control circuit2, if there is a difference between the actual value TRR_REALand the originally deigned value TRR_TYPof the reverse recovery time TRR, there is a risk that (i) the relation T1<<TRRwill hold true, resonance will occur, and EMI noise will be emitted, or that (ii) the relation T1>>TRRwill hold true, leading to a problem of unnecessarily increased switching loss.

FIGS. 9A and 9Bare circuit diagrams respectively showing the configurations of the control circuits2band2caccording to the second embodiment. In the following embodiments, the package terminal XXPKGand the chip terminal XXCHIPwill not be differentiated, and will collectively represented by “XX”.

The control circuits2band2cshown inFIGS. 9A and 9Bare each configured to be capable of changing the length of the first period T1. For example, a variable delay circuit20is provided on a path of the gate pulse signal SG2, instead of or otherwise in addition to the propagation path14_2. By changing the delay amount of the variable delay circuit20, the control circuit2bis capable of adjusting the length of the first period T1.

At least one external setting terminal TSET is provided to the control circuit2b, so as to allow the reverse recovery time TRRof the actual rectifier diode D to be set from the outside. For example, two external setting terminals TSET are provided to the control circuit2b, which allows their states (pull-up state, pull-down state, etc.) to be set from the outside. That is to say, by making a combination of the states of the two external setting terminals TSET, such an arrangement allows the settings for the reverse recovery time TRRto be switched between four values.

The variable delay circuit20is configured such that its delay amount is adjustable according to the state of the external setting terminals TSET. The variable delay circuit20may be configured as a digital counter or otherwise as an analog or digital delay circuit.

The control circuit2cshown inFIG. 9Bis configured to be capable of changing the length of the first period T1. The control circuit2cincludes: an interface (IF) terminal connected to an external host processor (not shown) via a bus (not shown); an interface circuit22; and a register24. The interface circuit22receives, from the host processor, data which represents the reverse recovery time TRRof the actual rectifier diode D1, and stores the data thus received in the register24. The delay amount is set for the variable delay circuit20according to the data stored in the register24.

With the control circuits2band2cshown inFIGS. 9A and 9B, such an arrangement allows the first period T1to have a suitable length based on the reverse recovery time TRRof the rectifier diode D1that is actually employed.

Third Embodiment

It can be assumed that there are cases in which there is a difference in the value of the capacitance COJof the rectifier diode D1and the design value estimated in the original design stage for the control circuit, due to modification of the specifications of the rectifier diode D1. If the capacitance COJbecomes smaller than the originally designed value, the attenuation coefficient ξ becomes smaller, and this has the property of potential oscillation in the voltage.

FIGS. 10A and 10Bare circuit diagrams respectively showing the configurations of control circuits2dand2eaccording to the third embodiment. The control circuits2dand2eaccording to the third embodiment are each configured to be capable of changing the on resistance of the switching transistor M1to be set for the first period T1, i.e., the on resistance RON1of the first transistor element M11. The on resistance of a MOSFET changes according to the gate-source voltage VGS. Accordingly, the control circuits2dand2eeach include a driving adjustment circuit26which adjusts the amplitude of the gate pulse signal SG1to be supplied to the control terminal (gate) of the first transistor element M11. It should be noted that the control circuit may be configured to adjust the size of the first transistor M11instead of adjusting the amplitude of the gate pulse signal SG1.

For example, the driving adjustment circuit26may adjust the gate resistance of the first transistor element M11. Alternatively, the driving adjustment circuit26may adjust the voltage VH supplied to the higher-side power supply terminal of the first driver DR1.

The amplitude of the gate pulse signal SG1can be adjusted according to the capacitance COJof the actual rectifier diode D1.

The control circuit2dshown inFIG. 10Aincludes at least one external setting terminal COJfor setting the capacitance COJ. The driving adjustment circuit26adjusts the amplitude of the gate pulse signal SG1according to the external setting terminal COJ.

With the control circuit2eshown inFIG. 10B, the interface circuit22receives, from the external host processor, data which indicates the capacitance COJ, and stores the data thus received in the register24. The driving adjustment circuit26adjusts the amplitude of the gate pulse signal SG1according to the data stored in the register24.

With the control circuits2dand2eshown inFIGS. 10A and 10B, such an arrangement is capable of adjusting the first value RON1of the on resistance of the switching transistor M1to a suitable value based on the capacitance COJof the rectifier diode D1that is actually employed.

Fourth Embodiment

Description has been made in the second and third embodiments regarding an arrangement in which the settings for the reverse recovery time TRRof the rectifier diode D1are made from the outside and an arrangement in which the settings for the capacitance value COJof the rectifier diode D1are made from the outside. Description will be made in the fourth embodiment regarding an arrangement in which the control circuit2ditself executes a calibration sequence so as to measure at least one of the reverse recovery time TRRor the capacitance COJof the rectifier diode D1that is employed Description will be made below regarding an arrangement configured to measure them both.

FIG. 11is a circuit diagram showing a configuration of a control circuit2faccording to the fourth embodiment.FIG. 12is a waveform diagram showing the operation of the control circuit2fshown inFIG. 11. The control circuit2fincludes a capacitance measurement circuit30, a time measurement circuit40, and a parameter setting unit50.

In the calibration sequence, the capacitance measurement circuit30detects the capacitance COJof the rectifier diode by integrating the current that flows when the switching transistor M1has been turned on after the rectifier diode D1has been charged using a predetermined voltage.

Specifically, the capacitance measurement circuit includes a current sensor32, an integrator34, and a capacitance calculation unit36.

When the switching transistor M1is turned off, the capacitance COJof the rectifier diode is charged according to the voltage difference ΔV between the current input voltage VINand the current output voltage VOUT. The voltage difference ΔV is known. In this case, the charge amount Q stored in the capacitance COJis represented by the following Expression.
Q=COJ·ΔV

Subsequently, when the switching transistor M1is turned on, the discharge current flows through the switching transistor M1. With the present embodiment, only the first transistor element M11is turned on, and the second transistor element M12is turned off. The current sensor32detects the discharge current I11that flows through the first transistor element M11. The configuration of the current sensor32is not restricted in particular. For example, (i) an arrangement may be made including a current mirror circuit which copies the current that flows through the first transistor element M11. Also, (ii) an arrangement may be made including a detection resistor arranged on a path of the discharge current I11, and configured to detect the voltage drop across the detection resistor as the current value. Alternatively, (iii) an arrangement may be made in which the known on resistance of the first transistor element M11itself is used instead of the detection resistor. That is to say, the configuration of the detection resistor is not restricted in particular.

The integrator34integrates the discharge current I11so as to calculate the charge amount Q. The integrator34may be configured as a low-pass filter. The integrator34may have (i) a configuration so as to charge a capacitance using the current detected by the current sensor32. Also, the integrator34may have (ii) a configuration in which the current value detected by the current sensor32is converted into a digital value, and the digital value thus converted is integrated. That is to say, the configuration of the integrator34is not restricted in particular.

The capacitance calculation unit36is capable of calculating the capacitance COJof the rectifier diode based on the relation COJ=Q/ΔV.

Furthermore, in the calibration sequence, the time measurement circuit40detects the reverse recovery time of the rectifier diode D1based on the waveform of the current that flows when the switching transistor M1is turned on after the rectifier diode D1is charged using a predetermined voltage difference ΔV.

Specifically, the time measurement circuit40includes a current sensor32, an integrator34, and a time acquisition unit46.

As described above, when the switching transistor M1is turned off, the capacitance COJof the rectifier diode is charged according to the voltage difference ΔV between the current input voltage VINand the current output voltage VOUT. Subsequently, when the switching transistor M1is turned on, discharge current flows through the switching transistor M1during the reverse recovery time TRRof the rectifier diode D1. With the present embodiment, only the first transistor element M11is turned on, and the second transistor element M12is turned off. The current sensor32detects the discharge current I11that flows through the first transistor element M11. The integrator34integrates the discharge current I11.

As shown inFIG. 12, after the progress of the reverse recovery time TRR, the integrated waveform of the discharge current I11has a substantially constant level. Accordingly, the time acquisition unit46measures the time up to the time point at which the integrated waveform of the discharge current Inis stabilized at a constant level, so as to acquire the reverse recovery time TRR. It should be noted that the capacitance calculation unit36may acquire the reverse recovery time TRRbased on the output of the current sensor32, instead of the output of the integrator34.

The measurement of the capacitance COJby means of the capacitance measurement circuit30and the measurement of the reverse recovery time TRRby means of the time measurement circuit40may be performed at the same time, or otherwise may be performed separately.

The parameter setting unit50adjusts the driving adjustment circuit26based on the capacitance COJacquired by the capacitance measurement circuit30. Furthermore, the parameter setting unit50adjusts the driving adjustment circuit26based on the reverse recovery time TRRacquired by the time measurement circuit40.

With the control circuit2f, such an arrangement is capable of suppressing oscillation in a sure manner even if a substitute rectifier diode D1is employed due to modification of the design, or otherwise even if the parasitic resistance, the parasitic inductance, or the like, changes due to modification of the design of the printed circuit board or the like.

As a modification of the fourth embodiment, only one of the reverse recovery time TRRor the capacitance COJof the rectifier diode D1employed in actuality may be measured.

Description has been made regarding the present invention with reference to the embodiment. The above-described embodiment has been described for exemplary purposes only, and is by no means intended to be interpreted restrictively. Rather, it can be readily conceived by those skilled in this art that various modifications may be made by making various combinations of the aforementioned components or processes, which are also encompassed in the technical scope of the present invention. Description will be made below regarding such modifications.

First Modification

Description has been made in the embodiments regarding an arrangement in which the circuit constants are determined so as to satisfy the relation ξ>1. However, the present invention is not restricted to such an arrangement. Also, the resistance component R, i.e., the value RON1of the on resistance RONof the switching transistor M1, may be determined such that the time constant τ is sufficiently short. Such an arrangement is capable of reducing the spectrum component of the switching voltage VSWin the vicinity of the resonance frequency even if the relation ξ>1 holds true in the first period T1.

Second Modification

In a case in which the first period T1is shorter than the reverse recovery time TRR, resonance can occur even after the first period T1has ended. However, in a case in which the energy stored in the resonance circuit is sufficiently damped in the first period T1, even if oscillation occurs in the switching voltage VSWor the output voltage VOUTafter the first period T1elapses, the emission of electromagnetic energy is small. In some cases, the electromagnetic energy thus emitted satisfies the EMI standards. In this case, an arrangement may be made in which T1<TRR.

Third Modification

With the present embodiment, the switching transistor M1is configured as a MOSFET. Also, the switching transistor M1may be configured as a bipolar transistor or an IGBT (Insulated Gate Bipolar Transistor).

Fourth Modification

The settings of the signals, such as the high-level state and the low-level state of the signals, and the magnitude relations of the voltage signals, have been described in the present embodiments for exemplary purposes only. The settings can be freely modified by inverting the signals using inverters or the like.

Lastly, description will be made regarding the usage of the DC/DC converter100.FIG. 13Ais a diagram showing a vehicle including the DC/DC converter100. A vehicle500includes an in-vehicle battery502, the DC/DC converter100, and a load504. The in-vehicle battery502generates a DC voltage VBATof 12 V or otherwise 24 V. The DC/DC converter100steps up and stabilizes the battery voltage VBATto a predetermined level, and supplies the voltage thus stepped up and stabilized to the load504.

The vehicle system employs an FM-VICS (Vehicle Information and Communication System, trademark) which uses the FM band. Thus, if FB band noise is emitted from the DC/DC converter100, this leads to instability of the vehicle system. By employing the DC/DC converter100according to the embodiment, such an arrangement is capable of reducing the FM band electromagnetic noise, thereby providing a stabilized system.

FIG. 13Bis a diagram showing an electronic device600including the DC/DC converter100. Examples of such an electronic device600include cellular phone terminals, tablet PCs, digital still cameras, digital video cameras, etc. The electronic device600includes a battery602, the DC/DC converter100, and a load604. The DC/DC converter100steps up the battery voltage VBAT, and supplies the voltage thus stepped up to the load604. Examples of such a load604include liquid crystal drivers, liquid crystal backlight LEDs, and camera flash LEDs, etc.

By employing the DC/DC converter100according to the embodiment, such an arrangement is capable of reducing FM band electromagnetic noise, thereby reducing the effect on other electronic devices in the vicinity of the electronic device.

The electronic device may be configured as a consumer electronics device such as a TV, a PC, a refrigerator, etc.