Semiconductor device

A semiconductor device includes a semiconductor substrate, a fin-shaped structure, a gate structure, a first doped region, a second doped region, and an intermediate region. The fin-shaped structure is disposed on and extends upwards from a top surface of the semiconductor substrate in a vertical direction. The gate structure is disposed straddling a part of the fin-shaped structure. At least a part of the first doped region is disposed in the fin-shaped structure. The second doped region is disposed in the fin-shaped structure and disposed above the first doped region in the vertical direction. The intermediate region is disposed in the fin-shaped structure. The second doped region is separated from the first doped region by the intermediate region, and a bottom surface of the gate structure is lower than or coplanar with a top surface of the first doped region in the vertical direction.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device, and more particularly, to a semiconductor device including a fin-shaped structure.

2. Description of the Prior Art

As the size of the field effect transistors (FETs) becomes smaller continuously, the conventional planar field effect transistor has difficulty in development because of the manufacturing limitations. Therefore, for overcoming the manufacturing limitations, the non-planar transistor technology such as fin field effect transistor (FinFET) technology is developed to replace the planar FET and becomes a development trend in the related industries. Since the three-dimensional structure of a FinFET increases the overlapping area between the gate and the fin-shaped structure, the channel region can therefore be more effectively controlled by the gate. This way, the drain-induced barrier lowering (DIBL) effect and the short channel effect (SCE) of the device with smaller dimensions may be reduced. However, there are still some issues have to be solved in the FinFETs for further improving the electrical characteristics thereof.

SUMMARY OF THE INVENTION

A semiconductor device and a manufacturing method thereof are provided in the present invention. Leakage current and/or capacitance between different doped regions within a fin-shaped structure may be reduced by separating the doped regions, modifying an area of fin-shaped structure covered by a gate structure straddling the fin-shaped structure, and/or enlarging a bottom portion of the gate structure for improving electrical characteristics of the semiconductor device.

According to an embodiment of the present invention, a semiconductor device is provided. The semiconductor device includes a semiconductor substrate, a fin-shaped structure, a gate structure, a first doped region, a second doped region, and an intermediate region. The fin-shaped structure is disposed on and extends upwards from a top surface of the semiconductor substrate in a vertical direction. The gate structure is disposed straddling a part of the fin-shaped structure. At least a part of the first doped region is disposed in the fin-shaped structure. The second doped region is disposed in the fin-shaped structure and disposed above the first doped region in the vertical direction. The intermediate region is disposed in the fin-shaped structure. The second doped region is separated from the first doped region by the intermediate region, and a bottom surface of the gate structure is lower than or coplanar with a top surface of the first doped region in the vertical direction.

According to an embodiment of the present invention, a manufacturing method of a semiconductor device is provided. The manufacturing method includes the following steps. A fin-shaped structure is formed on a semiconductor substrate, and the fin-shaped structure extends upwards from a top surface of the semiconductor substrate in a vertical direction. At least a part of a first doped region is located in the fin-shaped structure. A second doped region is formed in the fin-shaped structure. The second doped region is located above the first doped region in the vertical direction, and the second doped region is separated from the first doped region by an intermediate region located in the fin-shaped structure. A gate structure is formed straddling a part of the fin-shaped structure. A bottom surface of the gate structure is lower than or coplanar with a top surface of the first doped region in the vertical direction.

According to an embodiment of the present invention, a semiconductor device is provided. The semiconductor device includes a semiconductor substrate, a fin-shaped structure, and a gate structure. The fin-shaped structure is disposed on and extends upwards from a top surface of the semiconductor substrate in a vertical direction. The gate structure is disposed straddling a part of the fin-shaped structure, and the gate structure includes a first portion and a second portion disposed on the first portion. A width of the first portion of the gate structure is greater than a width of the second portion of the gate structure.

According to an embodiment of the present invention, a manufacturing method of a semiconductor device is provided. The manufacturing method includes the following steps. A fin-shaped structure is formed on a semiconductor substrate, and the fin-shaped structure extends upwards from a top surface of the semiconductor substrate in a vertical direction. A gate structure is formed straddling a part of the fin-shaped structure, and the gate structure includes a first portion and a second portion disposed on the first portion. A width of the first portion is greater than a width of the second portion.

DETAILED DESCRIPTION

Although specific configurations and arrangements are discussed, it could be understood that this is done for illustrative purposes only. A person skilled in the pertinent art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to a person skilled in the related art that the present invention can also be employed in a variety of other applications.

The term “etch” is used herein to describe the process of patterning a material layer so that at least a portion of the material layer after etching is retained. When “etching” a material layer, at least a portion of the material layer is retained after the end of the treatment. In contrast, when the material layer is “removed”, substantially all the material layer is removed in the process. However, in some embodiments, “removal” is considered to be a broad term and may include etching.

The term “forming” or the term “disposing” are used hereinafter to describe the behavior of applying a layer of material to the substrate. Such terms are intended to describe any possible layer forming techniques including, but not limited to, thermal growth, sputtering, evaporation, chemical vapor deposition, epitaxial growth, electroplating, and the like.

FIG.1is a stereoscopic schematic drawing illustrating a semiconductor device101according to a first embodiment of the present invention,FIG.2is a cross-sectional schematic drawing illustrating the semiconductor device101in this embodiment,FIG.3is a cross-sectional schematic drawing illustrating a source/drain structure30in the semiconductor device101according to this embodiment, andFIG.4is a cross-sectional schematic drawing illustrating a gate structure GS in the semiconductor device101according to this embodiment.FIG.2may be regarded as a cross-sectional diagram taken alone an elongation direction of a fin-shaped structure FS in the semiconductor device101(such as a first direction D1represented inFIGS.1-4), andFIG.3andFIG.4may be regarded as cross-sectional diagrams taken alone a direction perpendicular to the elongation direction of the fin-shaped structure FS (such as a second direction D2represented inFIGS.1-4). As illustrated inFIGS.1-4, the semiconductor device101includes a semiconductor substrate10, a fin-shaped structure FS, a gate structure GS, a first doped region14, a second doped region24, and an intermediate region16. The fin-shaped structure FS is disposed on the semiconductor substrate10and extends upwards from a top surface10TS of the semiconductor substrate10in a vertical direction (such as a third direction D3represented inFIGS.1-4). The gate structure GS is disposed straddling a part of the fin-shaped structure FS. At least a part of the first doped region14is disposed in the fin-shaped structure FS. The second doped region24is disposed in the fin-shaped structure FS and disposed above the first doped region14in the third direction D3. The intermediate region16is disposed in the fin-shaped structure FS. The second doped region24is separated from the first doped region14by the intermediate region16, and a bottom surface BS of the gate structure GS is lower than or coplanar with a top surface14TS of the first doped region14in the third direction D3.

In some embodiments, the fin-shaped structure FS may be formed by etching a part of the semiconductor substrate10, and a material composition of the fin-shaped structure FS and/or a material composition of the bottom of the fin-shaped structure FS may be the same as a material composition of the semiconductor substrate10and/or a material composition of the top of the semiconductor substrate10directly connected with the bottom of the fin-shaped structure FS. For example, the fin-shaped structure FS may be a silicon semiconductor fin-shaped structure FS when the semiconductor substrate10is a silicon semiconductor substrate, but not limited thereto. In other words, the fin-shaped structure FS in the present invention is not a fin-shaped structure directly formed on an insulator layer of a semiconductor-on-insulator (SOI) substrate. In some embodiments, the semiconductor substrate10may include a silicon semiconductor substrate, a silicon germanium semiconductor substrate, a silicon carbide semiconductor substrate, or a substrate made of other suitable semiconductor materials. In a top view of the semiconductor device101, the fin-shaped structure FS may be elongated in the first direction D1, the gate structure GS may be elongated in the second direction D2for straddling a part of the fin-shaped structure FS, and the second direction D2may be substantially orthogonal to the first direction D1, but not limited thereto. Therefore, the gate structure GS may be partially disposed at two opposite sides of the fin-shaped structure FS in the second direction D2, and the fin-shaped structure FS may be partially disposed at two opposite sides of the gate structure GS in the first direction D1. It is worth noting that some of the components illustrated in the figures of the present invention may further extend in the first direction D1and/or the second direction D2and are not limited to the shape illustrated in the figures. For example, the gate structure GS disposed at two opposite sides of the fin-shaped structure FS in the second direction D2may further extend in the second direction D2for straddling another fin-shaped structure, but not limited thereto.

In some embodiments, the third direction D3may be regarded as a thickness direction of the semiconductor substrate10, and the semiconductor substrate10may have the top surface10TS and a bottom surface opposite to the top surface10TS in the third direction D3. In some embodiments, the first direction D1and the second direction D2may be regarded as horizontal directions located in a horizontal plane orthogonal to a vertical direction (e.g. the third direction D3) and parallel with the top surface10TS and/or the bottom surface of the semiconductor substrate10, but not limited thereto. Additionally, in this description, a distance between the bottom surface of the semiconductor substrate10and a relatively higher location and/or a relatively higher part in the third direction D3is greater than a distance between the bottom surface of the semiconductor substrate10and a relatively lower location and/or a relatively lower part in the third direction D3. The bottom or a lower portion of each component may be closer to the bottom surface of the semiconductor substrate10in the third direction D3than the top or upper portion of this component. Another component disposed above a specific component may be regarded as being relatively far from the bottom surface of the semiconductor substrate10in the third direction D3, and another component disposed under a specific component may be regarded as being relatively closer to the bottom surface of the semiconductor substrate10in the third direction D3. Additionally, in this description, a top surface of a specific component may include a topmost surface of this component in the third direction D3, and a bottom surface of a specific component may include a bottommost surface of this component in the third direction D3.

In some embodiments, a conductivity type of the second doped region24may be different from and complementary to a conductivity type of the first doped region14. For example, the first doped region14may contain first conductive impurities, the second doped region24may contain second conductive impurities, and the first conductive impurities may be different from the second conductive impurities in conductivity type. In some embodiments, when the semiconductor device101is an n-type transistor, the first doped region14may be a p-type doped region containing p-type impurities, and the second doped region24may be an n-type doped region containing n-type impurities. When the semiconductor device101is a p-type transistor, the first doped region14may be an n-type doped region containing n-type impurities, and the second doped region24may be a p-type doped region containing p-type impurities. The p-type impurities described above may include boron (B) or other suitable p-type conductive impurities, and the n-type impurities described above may include phosphorus (P), arsenic (As), or other suitable n-type conductive impurities, but not limited thereto. In addition, a conductivity type of the intermediate region16may be identical to the conductivity type of the first doped region14, and an impurity concentration in the first doped region14may be higher than an impurity concentration in the intermediate region16. For example, the intermediate region16may include third conductive impurities, the conductivity type of the third conductive impurities may be the same as that of the first conductive impurities, but the concentration of the third conductive impurities in the intermediate region16is lower than the concentration of the first conductive impurities in the first doped region14. In some embodiments, the third conductive impurities may be identical to or different from the first conductive impurities, but both the first conductive impurities and the third conductive impurities are n-type conductive impurities or p-type conductive impurities.

In some embodiments, the semiconductor device101may further include a well region12, an isolation structure15, a channel region18, a spacer structure26, a source/drain region28, a source/drain structure30, and a dielectric layer32. The well region12may be partly disposed in the semiconductor substrate10and partly disposed in the fin-shaped structure FS, and the first doped region14may be disposed above the well region12. Therefore, a bottom surface14BS of the first doped region14may be higher than the top surface10TS of the semiconductor substrate10in the third direction D3, but not limited thereto. In some embodiments, a conductivity type of the well region12may be identical to the conductivity type of the first doped region14, and the impurity concentration in the first doped region14may be higher than an impurity concentration in the well region12. For example, the well region12may include fourth conductive impurities, the conductivity type of the fourth conductive impurities may be the same as that of the first conductive impurities, but the concentration of the fourth conductive impurities in the well region12is lower than the concentration of the first conductive impurities in the first doped region14. In some embodiments, the fourth conductive impurities may be identical to or different from the first conductive impurities, but both the first conductive impurities and the fourth conductive impurities are n-type conductive impurities or p-type conductive impurities.

The channel region18may be disposed in the fin-shaped structure FS and located above the intermediate region16in the third direction D3. In some embodiments, a conductivity type of the channel region18may be identical to the conductivity type of the intermediate region16, the channel region18may contain conductive impurities identical to the third conductive impurities in the intermediate region16, and an impurity concentration in the channel region18may be substantially equal to the impurity concentration in the intermediate region16, but not limited thereto. In some embodiments, the channel region18may be directly connected with the intermediate region16, and the gate structure GS may cover the channel region18in the second direction D2and the third direction D3and cover a part of the intermediate region16in the second direction D2.

In some embodiments, the gate structure GS may include a gate dielectric layer and a gate material layer disposed on the gate dielectric layer (not illustrated in the figures). The gate dielectric layer may include a high dielectric constant (high-k) dielectric material or other suitable dielectric materials. The high-k dielectric material described above may include hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), tantalum oxide (Ta2O5), zirconium oxide (ZrO2), or other suitable high-k materials. The gate material layer may include a non-metallic electrically conductive material (such as doped polysilicon) or a metallic electrically conductive material, such as a metal gate structure formed with a work function layer and a low electrical resistivity layer stacked with each other, but not limited thereto. The work function layer described above may include titanium nitride (TiN), titanium carbide (TiC), tantalum nitride (TaN), tantalum carbide (TaC), tungsten carbide (WC), titanium tri-aluminide (TiAl3), aluminum titanium nitride (TiAlN), or other suitable electrically conductive work function materials. The low electrical resistivity layer described above may include tungsten, aluminum, copper, titanium aluminide, titanium, or other suitable low electrical resistivity materials.

The isolation structure15may be disposed on the semiconductor substrate10and surrounding a part of the fin-shaped structure FS, such as a lower part of the fin-shaped structure FS. The isolation structure15may include a single layer or multiple layers of insulation materials, such as oxide insulation materials (silicon oxide, for example), or other suitable insulation materials. In some embodiments, a part of the gate structure GS may be disposed on the isolation structure15in the third direction D3, and a top surface15TS of the isolation structure15may be lower than or coplanar with the top surface14TS of the first doped region14in the third direction D3. In some embodiments, the bottom surface BS of the gate structure GS may directly contact the top surface15TS of the isolation structure15, and the gate structure GS may cover a part of a side surface16SS of the intermediate region16in the second direction D2. The bottom surface BS of the gate structure GS is lower than or coplanar with the top surface14TS of the first doped region14in the third direction D3for ensuring that the intermediate region16located between the channel region18and the first doped region14is covered by the gate structure GS in the second direction D2.

The spacer structure26may include a single layer or multiple layers of dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials. The spacer structure26may be partly disposed on sidewalls of the gate structure GS and partly disposed on sidewalls of the fin-shaped structure FS. For example, the spacer structure26may include a first portion26A disposed on the sidewalls of the gate structure GS and a second portion26B disposed on the sidewalls of a lower portion of the fin-shaped structure FS, but not limited thereto. A part of the first portion26A may be directly connected with a part of the second portion26B, and a top surface of the second portion26B may be lower than a top surface of the first portion26A in the third direction D3. The source/drain region28is disposed in the fin-shaped structure FS and disposed above the second doped region24in the third direction D3. A conductivity type of the source/drain region28may be identical to the conductivity type of the second doped region24, and an impurity concentration in the source/drain region28may be higher than an impurity concentration in the second doped region24. For example, the source/drain region28may include fifth conductive impurities, the conductivity type of the fifth conductive impurities may be the same as that of the second conductive impurities in the second doped region24, but the concentration of the fifth conductive impurities in the source/drain region28is higher than the concentration of the second conductive impurities in the second doped region24. Therefore, the source/drain region28may be regarded as a heavily doped region, and the second doped region24may be regarded as a highly doped region or a relatively lightly doped region (such as a lightly doped drain, LDD), but not limited thereto. In some embodiments, the fifth conductive impurities may be identical to or different from the second conductive impurities, but both the second conductive impurities and the fifth conductive impurities are n-type conductive impurities or p-type conductive impurities. For example, the second conductive impurities in the second doped region24may be arsenic and the fifth conductive impurities in the source/drain region28may be phosphorus for an n-type transistor because arsenic is less likely to diffuse than phosphorus, but not limited thereto.

In some embodiments, the source/drain structure30may be disposed on the fin-shaped structure FS and encompass the source/drain region28, but not limited thereto. The source/drain structure30may include an epitaxial material, such as epitaxial silicon, epitaxial silicon germanium (SiGe), epitaxial silicon phosphide (SiP), or other suitable epitaxial materials. In some embodiments, the source/drain structure30may contain conductive impurities identical to or similar to the fifth conductive impurities in the source/drain region28. The source/drain structure30may include two separated portions disposed at two opposite sides of the gate structure GS in the first direction D1, respectively, and the two portions of the source/drain structure30may be regarded as a source electrode and a drain electrode of the semiconductor device, respectively. The source/drain region28may include two separated portions disposed at the two opposite sides of the gate structure GS in the first direction D1, respectively, and the two portions of the source/drain region28may be regarded as a source doped region and a drain doped region of the semiconductor device, respectively. The second doped region24may include two separated portions disposed at the two opposite sides of the gate structure GS in the first direction D1, respectively, and the two portions of the second doped region24may be regarded as a LDD region for the source electrode and a LDD region for the drain electrode in the semiconductor device, respectively, but not limited thereto. The dielectric layer32may include a single layer or multiple layers of dielectric materials, such as silicon oxide, silicon oxynitride, silicon nitride, or other suitable dielectric materials. The dielectric layer32may cover the source/drain structure30and the spacer structure26, and a top surface32TS of the dielectric layer32may be substantially coplanar with a top surface of the gate structure GS, but not limited thereto.

The first doped region14with relatively higher impurity concentration may be used to reduce leakage current between the source electrode and the drain electrode (such as the different portions of the source/drain structure30disposed at two opposite sides of the gate structure GS in the first direction D1, respectively) at the bottom of the fin-shaped structure FS, and the first doped region14may be regarded as a channel cut region, but not limited thereto. The intermediate region16with relatively lower impurity concentration disposed between the first doped region14and the second doped region24may be used to reduce leakage current between the first doped region14and the second doped region24and/or capacitance between the first doped region14and the second doped region24. Additionally, the gate structure GS having the bottom surface BS lower than or coplanar with the top surface14TS of the first doped region14in the third direction D3may be used to reduce leakage current between different lightly doped regions (such as the different portions of the second doped region24disposed at two opposite sides of the gate structure GS in the first direction D1, respectively) by covering the intermediate region16located between the channel region18and the first doped region14. Therefore, the electrical characteristics of the semiconductor device may be improved by the intermediate region16disposed between the first doped region14and the second doped region24and the gate structure GS having the bottom surface BS lower than or coplanar with the top surface14TS of the first doped region14in the third direction D3.

FIGS.5-9are stereoscopic schematic drawings illustrating a manufacturing method of the semiconductor device101according to the first embodiment of the present invention, whereinFIG.6is a stereoscopic schematic drawing in a step subsequent toFIG.5,FIG.7is a stereoscopic schematic drawing in a step subsequent toFIG.6,FIG.8is a stereoscopic schematic drawing in a step subsequent toFIG.7,FIG.9is a stereoscopic schematic drawing in a step subsequent toFIG.8, andFIG.1may be regarded as a stereoscopic schematic drawing in a step subsequent toFIG.9. As illustrated inFIGS.1-4, a manufacturing method of the semiconductor device101may include the following steps. The fin-shaped structure FS is formed on the semiconductor substrate10, and the fin-shaped structure FS extends upwards from the top surface10TS of the semiconductor substrate10in the vertical direction (such as the third direction D3). At least a part of the first doped region14is located in the fin-shaped structure FS. The second doped region24is formed in the fin-shaped structure FS. The second doped region24is located above the first doped region14in the third direction D3, and the second doped region24is separated from the first doped region14by the intermediate region16located in the fin-shaped structure FS. The gate structure GS is formed straddling a part of the fin-shaped structure FS. The bottom surface BS of the gate structure GS is lower than or coplanar with the top surface14TS of the first doped region14in the third direction D3.

Specifically, the manufacturing method of the semiconductor device101in this embodiment may include but is not limited to the following steps. Firstly, as illustrated inFIG.5, the semiconductor substrate10is provided, and the first doped region14may be formed in the semiconductor substrate10by a doping process91. The doping process described in this description may include an ion implantation process or other suitable impurity doping approaches. The range, the depth, and the impurity concentration of the first doped region14in the semiconductor substrate10may be controlled by modifying the process parameters of the doping process91. Subsequently, as illustrated inFIG.5andFIG.6, the fin-shaped structure FS may be formed by performing a patterning process to the semiconductor substrate10, and the isolation structure15may be formed surrounding the lower portion of the fin-shaped structure FS. In some embodiments, a part of an original surface10S of the semiconductor substrate10may be recessed by the patterning process to be the top surface10TS of the semiconductor substrate10represented inFIG.3andFIG.4, and another part of the original surface10S of the semiconductor substrate10may become a top surface of the fin-shaped structure FS, but not limited thereto. In some embodiments, the top surface15TS of the isolation structure15may be controlled by an etching back process performed to the isolation structure15for recessing the isolation structure15and exposing the upper portion of the fin-shaped structure FS and a portion of a sidewall SW1of the fin-shaped structure FS. The exposed portion of the fin-shaped structure FS may be doped with the third conductive impurities described above after the step of forming the isolation structure15, and the top surface15TS of the isolation structure15may be controlled to be substantially coplanar with the top surface of the first doped region14and/or be aligned with the top surface of the first doped region14in the third direction D3. Therefore, the first doped region14may be formed before the step of forming the fin-shaped structure FS, but not limited thereto. In some embodiments, the first doped region14may be formed after the step of forming the fin-shaped structure FS according to other design and/or process considerations.

As illustrated inFIG.8, a dummy gate DG is formed straddling the fin-shaped structure FS. In some embodiments, a method of forming the dummy gate DG may include but is not limited to the following steps. As illustrated inFIG.6andFIG.7, a material layer may be formed on the isolation structure and covering the fin-shaped structure FS, and a patterning process may be performed to the material layer with a mask layer22formed on the material layer as a mask for forming a patterned material layer20P on the semiconductor substrate after the step of forming the fin-shaped structure FS. A planarization process of the material layer (e.g. a chemical mechanical polishing (CMP)) may be performed after forming the material layer and before forming the mask layer22. The mask layer22may include oxide insulation materials (silicon oxide, for example), or other suitable insulation materials. In some embodiments, the patterned material layer20P may include a first portion20A and a second portion20B connected with the first portion20A. The first portion20A may be disposed straddling a part of the fin-shaped structure FS, and the second portion20B may be elongated in the first direction D1and cover a part of the sidewall SW1of the fin-shaped structure FS. For example, the second portion20B of the patterned material layer20P may cover the sidewall SW1of the lower part of the exposed fin-shaped structure FS. After the step of forming the patterned material layer20P, the second doped region24may be formed in the fin-shaped structure FS by performing another doping process92. In some embodiments, the patterned material layer20P may be used as a mask in the doping process92, the second doped region24may be formed in the exposed portion of the fin-shaped structure FS, and a portion of the fin-shaped structure FS covered by the patterned material layer20P may be the intermediate region16and the channel region described above. As illustrated inFIG.7andFIG.8, after the step of forming the second doped region24, an etching process may be performed to the patterned material layer20P, and the patterned material layer20P may be etched to be the dummy gate DG by the etching process. In some embodiments, the second portion20B of the patterned material layer20P may be removed by the etching process, and the first portion20A of the patterned material layer20P may be regarded as the dummy gate DG, but not limited thereto. In some embodiments, the second doped region24may be formed after the step of forming the patterned material layer20P and before the second portion20B of the patterned material layer20P is removed by the etching process, but not limited thereto. In addition, the dummy gate DG may cover a part of the side surface of the intermediate region16in second direction D2, and the dummy gate DG may be replaced with the gate structure described above in subsequent processes. In some embodiments, the dummy gate DG may be formed from the patterned material layer20P, and the dummy gate DG and the patterned material layer20P may include a silicon-containing material, such as polysilicon, amorphous silicon, or other suitable materials.

As illustrated inFIG.9, the spacer structure26may be formed after the step of forming the second doped region24, the first portion26A of the spacer structure26may be formed on sidewalls of the dummy gate DG, and the second portion26B of the spacer structure26may be formed on the sidewalls of the fin-shaped structure FS. In some embodiments, a part of the second portion26B of the spacer structure26may be etched back for exposing an upper portion of the fin-shaped structure FS, and the source/drain structure30may be formed on the exposed fin-shaped structure FS by an epitaxial growth process or other suitable approaches. In some embodiments, a dielectric layer (such as a dielectric layer19represented inFIG.3) may be formed on the fin-shaped structure FS before the step of forming the material layer described above and the step of forming the spacer structure26, a part of the dielectric layer has to be removed before the step of forming the source/drain structure30, and a part of the dielectric layer may remain and be located between the spacer structure26and the fin-shaped structure FS, but not limited thereto. In some embodiments, the source/drain structure30may be doped in-situ during the process of forming the source/drain structure30, and the source/drain region28may be formed concurrently by the process, but not limited thereto. Instead of in-situ doping process described above, the source/drain structure30and the source/drain region28may be doped by ion implantation process after forming the source/drain structure30. Subsequently, as illustrated inFIG.9andFIG.1, the dielectric layer32may be formed and the dummy gate DG may be replaced with the gate structure GS by a replacement metal gate (RMG) process, but not limited thereto. In some embodiments, the dummy gate DG and the mask layer22may be replaced with the gate structure GS. In some embodiments, the mask layer22may be removed by a planarization process performed to the dielectric layer32, the spacer structure26, and the mask layer22, and the dummy gate DG may be replaced with the gate structure GS after the planarization process. The planarization process may include the CMP process, an etching back process, or other suitable planarization approaches.

It is worth noting that the manufacturing method of the semiconductor device is not limited to the approach described above and other suitable approaches may also be applied in the manufacturing method of the semiconductor device according to the present invention. Additionally, at least some steps of the manufacturing method described above may also be applied in other embodiments of the present invention.

The following description will detail the different embodiments of the present invention. To simplify the description, identical components in each of the following embodiments are marked with identical symbols. For making it easier to understand the differences between the embodiments, the following description will detail the dissimilarities among different embodiments and the identical features will not be redundantly described.

FIG.10is a cross-sectional schematic drawing illustrating the source/drain structure30in a semiconductor device102according to a second embodiment of the present invention, andFIG.11is a cross-sectional schematic drawing illustrating the gate structure GS in the semiconductor device102according to this embodiment.FIG.10andFIG.11may be regarded as cross-sectional diagrams at different portions of the semiconductor device102. As illustrated inFIG.10andFIG.11, in the semiconductor device102, the fin-shaped structure FS may include a first portion P1, a second portion P2, and a third portion P3. The second portion P2is disposed on the first portion P1in the third direction D3, and the third portion P3is disposed between the first portion P1and the second portion P2in the third direction D3. A width W1of the first portion P1may be greater than a width W2of the second portion P2, and a sidewall SW2of the third portion P3may be tapered for increasing the area of the fin-shaped structure FS covered by the gate structure GS. In some embodiments, the width W1of the first portion P1may be regarded as a length of the first portion P1in the second direction D2, and the width W2of the second portion P2may be regarded as a length of the second portion P2in the second direction D2. Additionally, at least a part of the intermediate region16may be disposed in the third portion P3, at least a part of the first doped region14may be disposed in the first portion P1, and the second doped region24and the source/drain region28may be disposed in the second portion P2, but not limited thereto. In some embodiments, the interface between the first portion P1and the third portion P3in the third direction D3may be substantially coplanar with the top surface15TS of the isolation structure15and/or the bottom surface BS of the gate structure GS, but not limited thereto. In addition, a length of the second portion P2in the third direction D3may be greater than a length of the third portion P3in the third direction D3, a slope of the sidewall of the second portion P2may be greater than a slope of the sidewall SW2of the third portion P3, and the third portion P3may be regarded as an enlarged portion for increasing the surface area of the fin-shaped structure FS covered by the gate structure GS, but not limited thereto.

FIGS.12-14are stereoscopic schematic drawings illustrating a manufacturing method of the semiconductor device102according to the second embodiment of the present invention, whereinFIG.13is a stereoscopic schematic drawing in a step subsequent toFIG.12,FIG.14is a stereoscopic schematic drawing in a step subsequent toFIG.13, andFIG.10andFIG.11may be regarded as cross-sectional schematic drawings in a step subsequent toFIG.14. As illustrated inFIGS.10-12, the fin-shaped structure FS including the first portion P1, the second portion P2, and the third portion P3described above may be formed by modifying the patterning process to the semiconductor substrate10described above. As illustrated inFIGS.10,11, and13, in some embodiments, the second portion20B of the patterned material layer20P may cover the third portion P3and a part of the second portion P2of the fin-shaped structure FS in the second direction D2during the doping process92for forming the second doped region24. As illustrated inFIGS.10,11,13, and14, the second portion20B of the patterned material layer20P may be removed for forming the dummy gate DG, the dummy gate DG may cover a part of the sidewall SW2of the third portion P3, and the intermediate region16may be partly formed in the third portion P3and partly formed in the second portion P2, but not limited thereto. Subsequently, the dummy gate DG may be replaced with the gate structure GS for forming the semiconductor device102.

It is worth noting that the manufacturing method of the semiconductor device102is not limited to the approach described above and other suitable approaches may also be applied in the manufacturing method of the semiconductor device102. Additionally, the fin-shaped structure FS including the first portion P1, the second portion P2, and the third portion P3in this embodiment may also be applied to other embodiments of the present invention.

FIG.15is a cross-sectional schematic drawing illustrating the source/drain structure30in a semiconductor device103according to a third embodiment of the present invention, andFIG.16is a cross-sectional schematic drawing illustrating the gate structure GS in the semiconductor device103according to this embodiment.FIG.15andFIG.16may be regarded as cross-sectional diagrams at different portions of the semiconductor device103. As illustrated inFIG.15andFIG.16, in the semiconductor device103, the top surface15TS of the isolation structure15and the bottom surface BS of the gate structure GS may be lower than the top surface14TS of the first doped region14in the third direction D3and higher than the bottom surface14BS of the first doped region14in the third direction D3. Therefore, the gate structure GS may further cover a part of a side surface14SS of the first doped region14in the second direction D2for ensuring that the intermediate region16located between the channel region18and the first doped region14is covered by the gate structure GS in the second direction D2.

FIGS.17-19are stereoscopic schematic drawings illustrating a manufacturing method of the semiconductor device103according to the third embodiment of the present invention, whereinFIG.18is a stereoscopic schematic drawing in a step subsequent toFIG.17,FIG.19is a stereoscopic schematic drawing in a step subsequent toFIG.18, andFIG.15andFIG.16may be regarded as cross-sectional schematic drawings in a step subsequent toFIG.19. As illustrated inFIG.17, after the step of forming the isolation structure15, the top surface15TS of the isolation structure15may be lower than the top surface14TS of the first doped region14in the fin-shaped structure FS. In some embodiments, the top surface15TS of the isolation structure15may be controlled by an etching back process performed to the isolation structure15for recessing the isolation structure15and exposing the upper portion of the fin-shaped structure FS and a portion of the first doped region14. As illustrated inFIG.18, in some embodiments, the second portion20B of the patterned material layer20P may cover the side surface of the intermediate region16and a part of the side surface of the first doped region14in the second direction D2during the doping process92for forming the second doped region24. As illustrated inFIG.18andFIG.19, the second portion20B of the patterned material layer20P may be removed for forming the dummy gate DG, the dummy gate DG may cover a part of the side surface16SS of the intermediate region16and a part of the side surface14SS of the first doped region14in the second direction D2, and a bottom surface of the dummy gate DG may be lower than the top surface14TS of the first doped region14in the third direction D3. Subsequently, as illustrated inFIGS.19,15, and16, the dummy gate DG may be replaced with the gate structure GS for forming the semiconductor device103.

It is worth noting that the manufacturing method of the semiconductor device103is not limited to the approach described above and other suitable approaches may also be applied in the manufacturing method of the semiconductor device103. Additionally, the gate structure GS covering a part of the side surface16SS of the intermediate region16and a part of the side surface14SS of the first doped region14in this embodiment may also be applied to other embodiments of the present invention.

FIG.20is a stereoscopic schematic drawing illustrating a semiconductor device104according to a fourth embodiment of the present invention,FIG.21is a cross-sectional schematic drawing illustrating the semiconductor device104in this embodiment, andFIG.22is a cross-sectional schematic drawing illustrating the gate structure GS in the semiconductor device104according to this embodiment.FIG.21may be regarded as a cross-sectional diagram taken alone the elongation direction of the fin-shaped structure FS in the semiconductor device104andFIG.22may be regarded as cross-sectional diagrams taken alone the direction perpendicular to the elongation direction of the fin-shaped structure FS. As illustrated inFIGS.20-22, the semiconductor device104includes the semiconductor substrate10, the fin-shaped structure FS, and the gate structure GS. The fin-shaped structure FS is disposed on and extends upwards from the top surface10TS of the semiconductor substrate10in a vertical direction (such as the third direction D3). The gate structure GS is disposed straddling a part of the fin-shaped structure FS, and the gate structure GS includes a first portion GS1and a second portion GS2disposed on and directly connected with the first portion GS1in the third direction D3. A width W3of the first portion GS1of the gate structure GS is greater than a width W4of the second portion GS2of the gate structure GS. The width W4of the second portion GS2may be regarded as a length of the second portion GS2in the first direction D1, and the width W3of the first portion GS1may be regarded as a length of the first portion GS1in the first direction D1, such as the maximum length of the first portion GS1in the first direction D1, but not limited thereto.

In some embodiments, the first portion GS1of the gate structure GS may include a lower part GS11and an upper part GS12directly connected with the lower part GS11, a slope of a sidewall SW3of the lower part GS11may be different from a slope of a sidewall SW4of the upper part GS12, and the width of the first portion GS1of the gate structure GS may be gradually changed in the first direction D3, but not limited thereto. For example, the slope of the sidewall SW3of the lower part GS11may be greater than the slope of the sidewall SW4of the upper part GS12, and the width of the first portion GS1of the gate structure GS may be gradually reduced from the bottom surface BS of the gate structure GS to the interface between the first portion GS1and the second portion GS2. In some embodiments, an included angle between the sidewall SW3of the lower part GS11and the bottom surface BS of the gate structure GS may be greater than an included angle AG between the sidewall SW4of the upper part GS12and a horizontal plane HP parallel to the top surface10TS of the semiconductor substrate10for increasing the area of the fin-shaped structure FS covered by the first portion GS1of the gate structure GS. For example, the included angle AG between the sidewall SW4of the upper part GS12and the horizontal plane HP may be less than 45 degrees, and the included angle between the sidewall SW3of the lower part GS11and the bottom surface BS of the gate structure GS may be greater than 45 degrees and less than 90 degrees, but not limited thereto. In some embodiments, the sidewall of the first portion GS1may be a curved surface and have a width gradually reduced from the bottom surface BS of the gate structure GS to the interface between the first portion GS1and the second portion GS2. In addition, a length of the second portion GS2in the third direction D3may be greater than a length of the first portion GS1in the third direction D3, and a slope of the sidewall of the second portion GS2may be greater than the slope of the sidewall SW3of the lower part GS11. Therefore, the change rate of the width of the second portion GS2may be less than that of the first portion GS1in the third direction D3. In addition, the first portion GS1of the gate structure GS may include two separated portions disposed at two opposite sides of the fin-shaped structure FS in the second direction D2, respectively, and each of the two separated portions includes the lower part GS11and the upper part GS12described above.

Similarly, the semiconductor device104may further include the well region12, the first doped region14, the isolation structure15, the channel region18, the spacer structure26, the source/drain region28, the source/drain structure30, and the dielectric layer32described above. At least a part of the first doped region14may be disposed in the fin-shaped structure FS. The second doped region24may be disposed in the fin-shaped structure FS and disposed above the first doped region14in the third direction D3, and the conductivity type of the second doped region24may be different from and complementary to the conductivity type of the first doped region14. The bottom surface BS of the gate structure GS may be lower than or coplanar with the top surface14TS of the first doped region14in the third direction D3. In some embodiments, the second doped region24may be directly connected with the first doped region14, and the first portion GS1of the gate structure GS may be regarded as an enlarged bottom portion of the gate structure GS for reducing the leakage current between the first doped region14and the second doped region24and the capacitance between the first doped region14and the second doped region24because the area of the interface between the second doped region24and the first doped region14is relatively reduced, a part of the second doped region24is separated from the first doped region14in the third direction D3by a part of the channel region18covered by the first portion GS1of the gate structure GS, and/or the impurity concentration in the first doped region14may be lowered relatively. In other words, the electrical characteristics of the semiconductor device104may be improved by the gate structure GS including the first portion GS1described above without forming the intermediate region separating the first doped region14and the second doped region24.

FIGS.23-26are stereoscopic schematic drawings illustrating a manufacturing method of the semiconductor device104according to the fourth embodiment of the present invention, whereinFIG.24is a stereoscopic schematic drawing in a step subsequent toFIG.23,FIG.25is a stereoscopic schematic drawing in a step subsequent toFIG.24,FIG.26is a stereoscopic schematic drawing in a step subsequent toFIG.25, andFIG.20may be regarded as a stereoscopic schematic drawing in a step subsequent toFIG.26. As illustrated inFIGS.20-22, a manufacturing method of the semiconductor device104may include the following steps. The fin-shaped structure FS is formed on the semiconductor substrate10, and the fin-shaped structure FS extends upwards from the top surface10TS of the semiconductor substrate10in a vertical direction (such as the third direction D3). The gate structure GS is formed straddling a part of the fin-shaped structure FS, and the gate structure GS includes the first portion GS1and the second portion GS2disposed on the first portion GS1. The width W3of the first portion GS1is greater than the width W4of the second portion GS2.

Specifically, the manufacturing method of the semiconductor device104in this embodiment may include but is not limited to the following steps. As illustrated inFIG.25the dummy gate DG is formed straddling a part of the fin-shaped structure FS. The dummy gate DG in this embodiment may include a first portion DG1and a second portion DG2disposed on the first portion DG1, and a width of the first portion DG1of the dummy gate DG may be greater than a width of the second portion DG2of the dummy gate DG Additionally, the first portion DG1of the dummy gate DG may include a lower part DG11and an upper part DG12, and a slope of a sidewall SW5of the lower part DG11may be different from a slope of a sidewall SW6of the upper part DG12. In some embodiments, the shape of the dummy gate DG may be substantially identical to that of the gate structure described above (such as the shape of the gate structure GS represented inFIGS.20-22). In other words, as illustrated inFIG.25andFIGS.20-22, the shape and the dimension of the first portion DG1of the dummy gate DG may be identical to or similar to those of the first portion GS1of the gate structure GS, and the shape and the dimension of the second portion DG2of the dummy gate DG may be identical to or similar to those of the second portion GS2of the gate structure GS. As illustrated inFIG.25, at least a part of the first doped region14may be located in the fin-shaped structure FS, and the second doped region24may be formed in the fin-shaped structure FS by the doping process92after the step of forming the dummy gate DG The second doped region24may be located above the first doped region14in the third direction D3, and the conductivity type of the second doped region24may be different from and complementary to the conductivity type of the first doped region14.

In some embodiments, a method of forming the dummy gate DG including the first portion DG1and the second portion DG2described above may include but is not limited to the following steps. As illustrated inFIG.23, the patterned material layer20P may be formed on the semiconductor substrate after the step of forming the fin-shaped structure FS. In some embodiments, the patterned material layer20P may include the first portion20A disposed straddling the fin-shaped structure FS and a third portion20C disposed on the first portion20A, and the mask layer22may be disposed on the third portion20C of the patterned material layer20P. In addition, a dummy spacer DS may be formed on sidewalls of the third portion20C and sidewalls of the mask layer22, and a patterned mask layer23may be formed covering a part of the first portion20A, a part of the dummy spacer DS, and a part of the mask layer22. In some embodiments, the dummy spacer DS may include an insulation material, such as silicon nitride, or other suitable insulation materials, and the patterned mask layer23may include photoresist or other suitable mask materials. In some embodiments, the material composition of the dummy spacer DS may be identical to or similar to the material composition of the patterned material layer20P for being etched in subsequent etching processes, but not limited thereto. Subsequently, as illustrated inFIG.23andFIG.24, an etching process may be performed to the patterned material layer20P, the dummy spacer DS, and the mask layer22with the patterned mask layer23as an etching mask for removing the exposed portion of the dummy spacer DS, the exposed portion of the mask layer22, the third portion20C of the patterned material layer20P, and a part of the exposed portion of the first portion20A of the patterned material layer20P and forming a fourth portion20D in the patterned material layer20P. The patterned mask layer23may be removed after the etching process described above. The shape of the fourth portion20D may be similar to the shape of the exposed portion of the dummy spacer DS and the exposed portion of the mask layer22before the etching process, and the etching process may be regarded as a process for transferring the shape of the exposed portion of the dummy spacer DS and the exposed portion of the mask layer22into the patterned material layer20P, but not limited thereto.

Subsequently, as illustrated inFIG.24andFIG.25, another etching process may be performed to the patterned material layer20P including the first portion20A, the third portion20C, and the fourth portion20D with the mask layer22as an etching mask, and the patterned material layer20P may be etched to be the dummy gate DG including the first portion DG1and the second portion DG2described above by the etching process. After the step of forming the dummy gate DG, the second doped region24may be formed in the fin-shaped structure FS, and a portion of the fin-shaped structure FS covered by the dummy gate DG may be the channel region described above. As illustrated inFIG.25andFIG.26, the spacer structure26may be formed after the step of forming the second doped region24, a part of the second portion26B of the spacer structure26may be etched back for exposing an upper portion of the fin-shaped structure FS, and the source/drain structure30may be formed on the exposed fin-shaped structure FS by an epitaxial growth process or other suitable approaches. In some embodiments, the source/drain structure30may be doped in-situ during the process of forming the source/drain structure30, and the source/drain region28may be formed concurrently by the process, but not limited thereto. Instead of in-situ doping process described above, the source/drain structure30and the source/drain region28may be doped by ion implantation process after forming the source/drain structure30. Subsequently, as illustrated inFIG.26andFIG.20, the dielectric layer32may be formed and the dummy gate DG may be replaced with the gate structure GS by a RMG process, but not limited thereto.

It is worth noting that the manufacturing method of the semiconductor device104is not limited to the approach described above and other suitable approaches may also be applied in the manufacturing method of the semiconductor device104according to the present invention. Additionally, the gate structure GS including the first portion GS1and the second portion GS2in this embodiment may also be applied to other embodiments of the present invention.

FIG.27is a stereoscopic schematic drawing illustrating a semiconductor device105according to a fifth embodiment of the present invention. As illustrated inFIG.27, in the semiconductor device105, the gate structure GS includes the first portion GS1and the second portion GS2disposed on and directly connected with the first portion GS1in the third direction D3. The width W3of the first portion GS1of the gate structure GS is greater than the width W4of the second portion GS2of the gate structure GS. In some embodiments, the included angle between the sidewall of the first portion GS1and the bottom surface BS of the gate structure GS may be about 90 degrees, and the gate width may be sharply increased from the interface between the second portion GS2and the first portion GS1to the first portion GS1. In other words, the change rate of the gate width from first portion GS1to the interface between the second portion GS2and the first portion GS1may be greater than that of the second portion GS2in the third direction D3. The first portion GS1of the gate structure GS may be regarded as an enlarged bottom portion of the gate structure GS for reducing the leakage current between the first doped region14and the second doped region24and the capacitance between the first doped region14and the second doped region24because the area of the interface between the second doped region24and the first doped region14is relatively reduced and/or the impurity concentration in the first doped region14may be lowered relatively.

FIGS.28-32are stereoscopic schematic drawings illustrating a manufacturing method of the semiconductor device105according to the fifth embodiment of the present invention, whereinFIG.29is a stereoscopic schematic drawing in a step subsequent toFIG.28,FIG.30is a stereoscopic schematic drawing in a step subsequent toFIG.29,FIG.31is a stereoscopic schematic drawing in a step subsequent toFIG.30,FIG.32is a stereoscopic schematic drawing in a step subsequent toFIG.31, andFIG.27may be regarded as a cross-sectional schematic drawing in a step subsequent toFIG.32. As illustrated inFIG.32, the dummy gate DG is formed straddling a part of the fin-shaped structure FS. The dummy gate DG in this embodiment may include the first portion DG1and the second portion DG2disposed on the first portion DG1, and a width of the first portion DG1of the dummy gate DG may be greater than a width of the second portion DG2of the dummy gate DG In some embodiments, the shape of the dummy gate DG may be substantially identical to that of the gate structure described above (such as the shape of the gate structure GS represented inFIG.27). In other words, as illustrated inFIG.32andFIG.27, the shape and the dimension of the first portion DG1of the dummy gate DG may be identical to or similar to those of the first portion GS1of the gate structure GS, and the shape and the dimension of the second portion DG2of the dummy gate DG may be identical to or similar to those of the second portion GS2of the gate structure GS. As illustrated inFIG.32, at least a part of the first doped region14may be located in the fin-shaped structure FS, the second doped region24may be formed in the fin-shaped structure FS by the doping process92after the step of forming the dummy gate DG, and a portion of the fin-shaped structure FS covered by the dummy gate DG may be the channel region described above.

In some embodiments, a method of forming the dummy gate DG including the first portion DG1and the second portion DG2described above may include but is not limited to the following steps. As illustrated inFIG.28, a material layer20may be formed on the semiconductor substrate and cover the fin-shaped structure FS after the step of forming the fin-shaped structure FS. The material layer20may include a silicon-containing material, such as polysilicon, amorphous silicon, or other suitable materials. Subsequently, the mask layer22may be formed on the material layer20, and the dummy spacer DS may be formed on the material layer20and sidewalls of the mask layer22. In some embodiments, the material composition of the dummy spacer DS may be different from the material composition of the mask layer22and the material composition of the material layer20for the etching selectivity concerned in subsequent etching steps. For example, in some embodiments, the material of the dummy spacer DS may be silicon nitride, the material of the mask layer22may be silicon oxide, and the material layer20may be a polysilicon layer, but not limited thereto. In some embodiments, as illustrated inFIG.28andFIG.29, an etching process may be performed to the dummy spacer DS and the mask layer22for removing a part of the dummy spacer DS and a part of the mask layer22and adjusting the length of the dummy spacer DS and the mask layer22in the second direction D2and/or the area of a portion of the material layer20overlapped by the dummy spacer DS and the mask layer22in the third direction D3.

Subsequently, as illustrated inFIG.29andFIG.30, another etching process may be performed to the material layer20with the mask layer22and the dummy spacer DS as an etching mask for forming the patterned material layer20P including the first portion20A and the third portion20C. In other words, the material layer20may be patterned to be the patterned material layer20P by the etching process using the mask layer22and the dummy spacer DS as the etching mask. As illustrated inFIGS.30-32, the dummy spacer DS may be removed after the step of forming the patterned material layer20P, and an etching process may be performed to the patterned material layer20P including the first portion20A and the third portion20C with the mask layer22as an etching mask for forming the dummy gate DG including the first portion DG1and the second portion DG2represented inFIG.32. In some embodiments, the etching process may be regarded as a process for transferring the shape of the third portion20C to the first portion DG1of the dummy gate DG, but not limited thereto. After the step of forming the dummy gate DG, the second doped region24may be formed in the fin-shaped structure FS by performing the doping process92. As illustrated inFIG.32andFIG.27, the spacer structure26, the source/drain structure30, the source/drain region28, and the dielectric layer32may be formed after the step of forming the second doped region24, and the dummy gate DG may be replaced with the gate structure GS by a RMG process for forming the semiconductor device105represented inFIG.27.

It is worth noting that the manufacturing method of the semiconductor device105is not limited to the approach described above and other suitable approaches may also be applied in the manufacturing method of the semiconductor device105according to the present invention. Additionally, the gate structure GS including the first portion GS1and the second portion GS2in this embodiment may also be applied to other embodiments of the present invention.

FIG.33is a cross-sectional schematic drawing illustrating a semiconductor device106according to a sixth embodiment of the present invention. As illustrated inFIG.33, in the semiconductor device106, the gate structure GS may include the first portion GS1and the second portion GS2, and the first portion GS1may include the lower part GS11and the upper part GS12described above. In other words, the gate structure GS in this embodiment may be identical or at least similar to the gate structure GS represented inFIGS.20-22described above. In addition, the semiconductor device106may further include the intermediate region16disposed in the fin-shaped structure FS, and the second doped region24may be separated from the first doped region14by the intermediate region16. The conductivity type of the intermediate region16may be identical to the conductivity type of the first doped region14, and the impurity concentration in the first doped region14may be higher than the impurity concentration in the intermediate region16. The bottom surface BS of the gate structure GS is lower than or coplanar with the top surface14TS of the first doped region14in the third direction D3, and a part of the intermediate region16located between the channel region18and the first doped region14and a part of the intermediate region16located between the second doped region24and the first doped region14may be covered by the gate structure GS in the second direction D2. In some embodiments, the shape of the intermediate region16is influenced by the process of forming the gate structure GS, and the intermediate region16may include an upper portion having a shape similar to the shape of the first portion GS1of the gate structure GS, but not limited thereto. Accordingly, the top surface16TS of the intermediate region16(such as the topmost surface of the intermediate region16) may be higher than the bottom surface24BS of the second doped region24(such as the bottommost surface of the second doped region24) in the third direction D3.

In this embodiment, the intermediate region16with relatively lower impurity concentration disposed between the first doped region14and the second doped region24may be used to reduce leakage current between the first doped region14and the second doped region24and/or capacitance between the first doped region14and the second doped region24. Additionally, the first portion GS1of the gate structure GS may be regarded as an enlarged bottom portion of the gate structure GS for reducing the leakage current between the first doped region14and the second doped region24and the capacitance between the first doped region14and the second doped region24because the distance between a part of the second doped region24and the first doped region14in the third direction D3is increased by the upper portion of the intermediate region16, a part of the intermediate region16located between the channel region18and the first doped region14and a part of the intermediate region16located between the second doped region24and the first doped region14are covered by the gate structure GS in the second direction D2, and/or the impurity concentration in the first doped region14may be lowered relatively. In other words, the electrical characteristics of the semiconductor device106may be improved by the gate structure GS including the first portion GS1and the second portion GS2described above and the intermediate region16separating the first doped region14and the second doped region24.

FIG.34andFIG.35are stereoscopic schematic drawings illustrating a manufacturing method of the semiconductor device106according to the sixth embodiment of the present invention, whereinFIG.35is a stereoscopic schematic drawing in a step subsequent toFIG.34, andFIG.33may be regarded as a cross-sectional schematic drawing in a step subsequent toFIG.35. As illustrated inFIG.34, the patterned material layer20P may include the first portion20A, the second portion20B, and a fifth portion20E located between the first portion20A and the second portion20B in the third direction D3. The first portion20A may be disposed straddling the fin-shaped structure FS, and the second portion20B may cover a part of the sidewall SW1of the fin-shaped structure FS. In some embodiments, the shape of the fifth portion20E may be similar to the shape of the first portion DG1represented inFIG.25described above, and the method of forming the patterned material layer20P including the first portion20A, the second portion20B, and the fifth portion20E may be similar to the method represented inFIGS.23-25described above, but not limited thereto. Subsequently, the second doped region24may be formed in the fin-shaped structure FS, and the intermediate region16in the fin-shaped structure FS may be covered by the patterned material layer20P in the second direction D2. As illustrated inFIG.34andFIG.35, after the step of forming the second doped region24, an etching process may be performed to the patterned material layer20P, the patterned material layer20P may be etched to be the dummy gate DG including the first portion DG1and the second portion DG2by the etching process, and at least a part of the second portion20B of the patterned material layer20P may be removed by the etching process. The dummy gate DG may cover a part of the side surface of the first doped region14in the second direction D2, the dummy gate DG may include the first portion DG1and the second portion DG2disposed on the first portion DG1, and the width of the first portion DG1of the dummy gate DG may be greater than the width of the second portion DG2of the dummy gate DG Additionally, the first portion DG1of the dummy gate DG may include the lower part DG11and the upper part DG12, and the slope of a sidewall SW5of the lower part DG11may be different from the slope of a sidewall SW6of the upper part DG12. In some embodiments, the second doped region24in this embodiment may be formed after the step of forming the patterned material layer20P and before the step of forming the dummy gate DG and the step of removing at least a part of the second portion20B of the patterned material layer20P. As illustrated inFIG.35andFIG.33, the spacer structure26, the source/drain structure30, the source/drain region28, and the dielectric layer32may be formed after the step of forming the dummy gate DG, and the dummy gate DG may then be replaced with the gate structure GS by a RMG process for forming the semiconductor device106.

It is worth noting that the manufacturing method of the semiconductor device106is not limited to the approach described above and other suitable approaches may also be applied in the manufacturing method of the semiconductor device106according to the present invention.

FIG.36is a cross-sectional schematic drawing illustrating a semiconductor device107according to a seventh embodiment of the present invention. As illustrated inFIG.36, in the semiconductor device107, the gate structure GS may include the first portion GS1and the second portion GS2, and the gate structure GS in this embodiment may be identical or at least similar to the gate structure GS represented inFIG.27described above. In addition, the semiconductor device107may further include the intermediate region16disposed in the fin-shaped structure FS, and the second doped region24may be separated from the first doped region14by the intermediate region16. The conductivity type of the intermediate region16may be identical to the conductivity type of the first doped region14, and the impurity concentration in the first doped region14may be higher than the impurity concentration in the intermediate region16. The bottom surface BS of the gate structure GS is lower than or coplanar with the top surface14TS of the first doped region14in the third direction D3, and a part of the intermediate region16located between the channel region18and the first doped region14and a part of the intermediate region16located between the second doped region24and the first doped region14may be covered by the gate structure GS in the second direction D2. In some embodiments, the shape of the intermediate region16is influenced by the process of forming the gate structure GS, and the intermediate region16may include an upper portion having a shape similar to the shape of the first portion GS1of the gate structure GS, but not limited thereto. Accordingly, the top surface16TS of the intermediate region16(such as the topmost surface of the intermediate region16) may be higher than the bottom surface24B S of the second doped region24(such as the bottommost surface of the second doped region24) in the third direction D3. The width W3of the first portion GS1of the gate structure GS is greater than the width W4of the second portion GS2of the gate structure GS, and the gate width may be sharply increased from the interface between the second portion GS2and the first portion GS1to the first portion GS1. The electrical characteristics of the semiconductor device107may be improved by the gate structure GS including the first portion GS1and the second portion GS2described above and the intermediate region16separating the first doped region14and the second doped region24.

FIG.37andFIG.38are stereoscopic schematic drawings illustrating a manufacturing method of the semiconductor device107according to the seventh embodiment of the present invention, whereinFIG.38is a stereoscopic schematic drawing in a step subsequent toFIG.37, andFIG.36may be regarded as a cross-sectional schematic drawing in a step subsequent to FIG.38. As illustrated inFIG.37, the patterned material layer20P may include the first portion20A, the second portion20B, and the fifth portion20E located between the first portion20A and the second portion20B in the third direction D3. In some embodiments, the shape of the fifth portion20E may be similar to the shape of the first portion DG1of the dummy gate DG represented inFIG.27described above, and the method of forming the patterned material layer20P including the first portion20A, the second portion20B, and the fifth portion20E may be similar to the method represented inFIGS.28-32described above, but not limited thereto. Subsequently, the second doped region24may be formed in the fin-shaped structure FS, and the intermediate region16in the fin-shaped structure FS may be covered by the patterned material layer20P in the second direction D2. As illustrated inFIG.37andFIG.38, after the step of forming the second doped region24, an etching process may be performed to the patterned material layer20P, and the patterned material layer20P may be etched to be the dummy gate DG including the first portion DG1and the second portion DG2by the etching process. Therefore, the second doped region24in this embodiment may be formed after the step of forming the patterned material layer20P and before the step of forming the dummy gate DG As illustrated inFIG.38andFIG.36, the spacer structure26, the source/drain structure30, the source/drain region28, and the dielectric layer32may be formed after the step of forming the dummy gate DG and the dummy gate DG may then be replaced with the gate structure GS by a RMG process for forming the semiconductor device107.

It is worth noting that the manufacturing method of the semiconductor device107is not limited to the approach described above and other suitable approaches may also be applied in the manufacturing method of the semiconductor device107according to the present invention.

In addition,FIG.33may be regarded as a cross-sectional schematic drawing illustrating a semiconductor device according to another embodiment of the present invention,FIG.10may be regarded as a cross-sectional schematic drawing illustrating the source/drain structure30in this embodiment, andFIG.11may be regarded as a cross-sectional schematic drawing illustrating the gate structure GS in this semiconductor device. As illustrated inFIG.33,FIG.10, andFIG.11, the fin-shaped structure FS may include the first portion P1, the second portion P2, and the third portion P3described above. The width W1of the first portion P1may be greater than the width W2of the second portion P2, and the sidewall SW2of the third portion P3may be tapered for increasing the area of the fin-shaped structure FS covered by the gate structure GS including the first portion GS1and the second portion GS2represented inFIG.33described above.

In addition,FIG.36may be regarded as a cross-sectional schematic drawing illustrating a semiconductor device according to another embodiment of the present invention,FIG.10may be regarded as a cross-sectional schematic drawing illustrating the source/drain structure30in this embodiment, andFIG.11may be regarded as a cross-sectional schematic drawing illustrating the gate structure GS in this semiconductor device. As illustrated inFIG.36,FIG.10, andFIG.11, the fin-shaped structure FS may include the first portion P1, the second portion P2, and the third portion P3described above. The width W1of the first portion P1may be greater than the width W2of the second portion P2, and the sidewall SW2of the third portion P3may be tapered for increasing the area of the fin-shaped structure FS covered by the gate structure GS including the first portion GS1and the second portion GS2represented inFIG.36described above.

FIG.39is a cross-sectional schematic drawing illustrating a semiconductor device108according to an eighth embodiment of the present invention. As illustrated inFIG.39, in the semiconductor device108, the bottom surface BS of the gate structure GS may be lower than the top surface14TS of the first doped region14in the third direction D3, and the gate structure GS may cover a part of the side surface of the intermediate region16and a part of the side surface of the first doped region14in the second direction D2for ensuring that the intermediate region16located between the channel region18and the first doped region14in the third direction D3is covered by the gate structure GS in the second direction D2. In some embodiments, a part of the side surface of the first doped region14may be covered by the first portion GS1of the gate structure GS in the second direction D2, and a part of the side surface of the intermediate region16may be covered by the second portion GS2of the gate structure GS in the second direction D2, but not limited thereto. The electrical characteristics of the semiconductor device108may be improved by the gate structure GS including the first portion GS1and the second portion GS2described above and the intermediate region16separating the first doped region14and the second doped region24.

FIG.40andFIG.41are stereoscopic schematic drawings illustrating a manufacturing method of the semiconductor device108according to the eighth embodiment of the present invention, whereinFIG.41is a stereoscopic schematic drawing in a step subsequent toFIG.40, andFIG.39may be regarded as a cross-sectional schematic drawing in a step subsequent toFIG.41. As illustrated inFIG.40, after the step of forming the isolation structure15, the top surface15TS of the isolation structure15may be lower than the top surface of the first doped region14in the fin-shaped structure FS. The shape of the patterned material layer20P including the first portion20A, the second portion20B, and the fifth portion20E in this embodiment may be similar to that of the patterned material layer20P represented inFIG.34described above, but the second portion20B in this embodiment may be relatively thicker for covering the side surface of the intermediate region16and a part of the side surface of the first doped region14in the second direction D2during the doping process92for forming the second doped region24. As illustrated inFIG.40andFIG.41, after the step of forming the second doped region24, an etching process may be performed to the patterned material layer20P, and the patterned material layer20P may be etched to be the dummy gate DG including the first portion DG1and the second portion DG2by the etching process. As illustrated inFIG.41andFIG.39, the spacer structure26, the source/drain structure30, the source/drain region28, and the dielectric layer32may be formed after the step of forming the dummy gate DG, and the dummy gate DG may then be replaced with the gate structure GS by a RMG process for forming the semiconductor device108.

It is worth noting that the manufacturing method of the semiconductor device108is not limited to the approach described above and other suitable approaches may also be applied in the manufacturing method of the semiconductor device108according to the present invention.

FIG.42is a cross-sectional schematic drawing illustrating a semiconductor device109according to a ninth embodiment of the present invention. As illustrated inFIG.42, in the semiconductor device109, the bottom surface BS of the gate structure GS may be lower than the top surface14TS of the first doped region14in the third direction D3, and the gate structure GS may cover a part of the side surface of the intermediate region16and a part of the side surface of the first doped region14in the second direction D2for ensuring that the intermediate region16located between the channel region18and the first doped region14in the third direction D3is covered by the gate structure GS in the second direction D2. In some embodiments, a part of the side surface of the first doped region14may be covered by the first portion GS1of the gate structure GS in the second direction D2, and a part of the side surface of the intermediate region16may be covered by the second portion GS2of the gate structure GS in the second direction D2, but not limited thereto. The width W3of the first portion GS1of the gate structure GS is greater than the width W4of the second portion GS2of the gate structure GS, and the gate width may be sharply increased from the interface between the second portion GS2and the first portion GS1to the first portion GS1. The electrical characteristics of the semiconductor device109may be improved by the gate structure GS including the first portion GS1and the second portion GS2described above and the intermediate region16separating the first doped region14and the second doped region24.

FIG.43andFIG.44are stereoscopic schematic drawings illustrating a manufacturing method of the semiconductor device109according to the ninth embodiment of the present invention, whereinFIG.44is a stereoscopic schematic drawing in a step subsequent toFIG.43, andFIG.42may be regarded as a cross-sectional schematic drawing in a step subsequent toFIG.44. As illustrated inFIG.43, after the step of forming the isolation structure15, the top surface15TS of the isolation structure15may be lower than the top surface of the first doped region14in the fin-shaped structure FS. The shape of the patterned material layer20P including the first portion20A, the second portion20B, and the fifth portion20E in this embodiment may be similar to that of the patterned material layer20P represented inFIG.37described above, but the second portion20B in this embodiment may be relatively thicker for covering the side surface of the intermediate region16and a part of the side surface of the first doped region14in the second direction D2during the doping process92for forming the second doped region24. As illustrated inFIG.43andFIG.44, after the step of forming the second doped region24, an etching process may be performed to the patterned material layer20P, and the patterned material layer20P may be etched to be the dummy gate DG including the first portion DG1and the second portion DG2by the etching process. As illustrated inFIG.44andFIG.42, the spacer structure26, the source/drain structure30, the source/drain region28, and the dielectric layer32may be formed after the step of forming the dummy gate DG, and the dummy gate DG may then be replaced with the gate structure GS by a RMG process for forming the semiconductor device109.

It is worth noting that the manufacturing method of the semiconductor device109is not limited to the approach described above and other suitable approaches may also be applied in the manufacturing method of the semiconductor device109according to the present invention.

FIG.45andFIG.46are stereoscopic schematic drawings illustrating a manufacturing method of a semiconductor device according to a tenth embodiment of the present invention, whereinFIG.46is a stereoscopic schematic drawing in a step subsequent toFIG.45, andFIG.45may be regarded as a stereoscopic schematic drawing in a step subsequent toFIG.8. As illustrated inFIG.8andFIG.45, in some embodiments, after the step of etching back the second portion26B of the spacer structure26and exposing an upper portion of the fin-shaped structure FS, the exposed portion of fin-shaped structure FS (such as an upper portion of the second doped region24) may be removed by an etching process93. Subsequently, as illustrated inFIGS.45and46, the source/drain structure30may be formed on the fin-shaped structure FS by an epitaxial growth process or other suitable approaches. It is worth noting that the method of removing a part of the fin-shaped structure FS before the step of forming the source/drain structure30may also be applied in other embodiments of the present invention (such as the embodiments described above). The etching process93may include a dry etching process or a wet etching process. In the structure illustrated inFIG.46, the source/drain structure30can push or pull the channel region18laterally. So, removing a part of the fin-shaped structure FS before the step of forming the source/drain structure30may increase source/drain current of fin-FET, because lateral stress in the channel region18may increase. Moreover, in the structure illustrated inFIG.46, the source/drain structure30with heavy impurity concentration is disposed closer to the bottom surface of the second doped region24than other embodiments. So, the impurities of the source/drain structure30may diffuse downward beyond the bottom surface of the second doped region24in the third direction D3. Even in this case, the merits of other embodiments of the present invention are still effective if a portion of the second doped region24covered by the first portion26A of the spacer structure26is separated from the first doped region14.

FIG.47is a stereoscopic schematic drawing illustrating a manufacturing method of a semiconductor device according to an eleventh embodiment of the present invention. As illustrated inFIG.47, in some embodiments, the fin-shaped structure FS may include a plurality of first layers11A and a plurality of second layers11B alternately stacked in the third direction D3. The material composition of each of the first layers11A may be different from the material composition of each of the second layers11B. For example, the first layer11A may be a silicon layer, and the second layer11B may be a silicon germanium layer, but not limited thereto. In some embodiments, the dummy gate DG may be formed straddling the fin-shaped structure FS including the first layers11A and the second layers11B alternately stacked, and the second doped region and/or the source/drain region described above may be formed in the first layer11A and/or the second layer11B of the fin-shaped structure FS, but not limited thereto. In some embodiments, a portion of the second layers11B covered by the dummy gate DG may be removed after the step of removing the dummy gate DG and before the step of forming the gate structure described above, and the gate structure may surround a part of each of the first layers11A for forming a gate-all-around (GAA) transistor, but not limited thereto. It is worth noting that the fin-shaped structure FS including the first layers11A and the second layers11B alternately stacked may also be applied in other embodiments of the present invention (such as the embodiments described above). In the gate-all-around transistor (GAA), the short channel effect (SCE) can be suppressed because channels made of the first layers11A are surrounded by the gate structure. In the structure illustrated inFIG.47, the top surface14TS of the first doped region14is disposed higher than or coplanar with a top surface15TS of the isolation structure15. So, the second doped region24may be formed in a top portion of the first doped region14and may increase the leakage current and/or the capacitance, if structures explained in embodiments of the present invention are not applied. So, even in the case of the gate-all-around transistor (GAA), the merits of other embodiments of the present invention are still effective.

To summarize the above descriptions, according to the semiconductor device and the manufacturing method thereof in the present invention, the leakage current and/or the capacitance between the first doped region and the second doped region within the fin-shaped structure may be reduced by separating the first doped region from the second doped region, modifying the area of fin-shaped structure covered by the gate structure straddling the fin-shaped structure, and/or enlarging the bottom portion of the gate structure for improving the electrical characteristics of the semiconductor device.