Apparatus and method for data transmission

The present invention discloses a data transmission apparatus and method to lower a data transmission voltage for eliminating EMI. In the data driving apparatus, a timing controller aligns input pixel data, lowers input data voltages of the input pixel data, and outputs to a plurality of data transmission lines. A data driver raises the lowered input data voltages for driving the liquid crystal display panel and then converts into analog pixel voltage signals to supply the analog pixel voltage signals to the data lines.

This application claims the benefit of the Korean Application No. P2002-02089 filed on Jan. 14, 2002, which is hereby incorporated by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a data transmission method, and more particularly, to an apparatus and method for data transmission for minimizing electromagnetic interference (EMI) occurring upon parallel data transmission. Although the present invention is suitable for a wide scope of applications, it is particularly suitable for a data driving apparatus of a liquid crystal display.

2. Discussion of the Related Art

Nowadays, the amount of video data transmitted through a transmission medium has been increased to satisfy a user's demand on a high quality image. As a result, the video data has been transferred at a high speed. In an effort to achieve this end, a transmission frequency of the video data has been increased and the number of transmission lines for transmitting the video data has also been increased. As the video data having a high frequency is transferred synchronously over the increased data transmission lines, electromagnetic interference (EMI) occurs among the data transmission lines.

In order to reduce the EMI, the number of the data transition has been reduced in the liquid crystal display (LCD) by using a data modulation system. Alternatively, the transmission frequency has been reduced by using a six-bus system.

FIG. 1shows a data driving apparatus of a conventional LCD that transmits video data by using a six-bus system.

Referring toFIG. 1, the data driving apparatus includes data driving IC's8for driving data lines of a liquid crystal display panel10, and a timing controller2for controlling a driving of the data driving IC's8. Each data driving IC8is mounted on a tape carrier package (TCP)6to be connected to the liquid crystal display panel10. Further, each data driving IC8is connected to a timing controller2through the TCP6and a printed circuit board (PCB)4.

More specifically, in the liquid crystal display panel10, gate lines and data lines are arranged in such a manner to cross each other. Liquid crystal cells are positioned at every area where each gate line cross each data line. The liquid crystal display panel10is provided with pixel electrodes and a common electrode for supplying an electric field to each of the liquid crystal cells. Each pixel electrode is connected to one of data lines through source and drain electrodes of a thin film transistor as a switching device. The gate electrode of the thin film transistor is connected to one of the gate lines allowing a pixel voltage signal to be applied to the pixel electrodes for each line. Accordingly, the liquid crystal display panel10controls light transmittance by the electric field applied between the pixel electrode and the common electrode in accordance with the pixel voltage signal for each liquid crystal cell, thereby displaying a picture thereon.

The data driving IC's8apply a pixel voltage signal to each data line whenever a gate signal is applied to one of the gate lines by gate driving IC's (not shown). Particularly, the data driving IC's8convert digital video data (pixel data) inputted from the timing controller2into analog pixel voltage signals.

The timing controller2controls driving of the data driving IC's8and the gate driving IC's and applies the pixel data to the data driving IC's8at the same time. To this end, as shown inFIG. 2, the timing controller2includes a control signal generator3for generating control signals, and a data aligner5for aligning the pixel data in conformity to the six-bus system.

The control signal generator3generates data control signals (i.e., SSC, SSP, SOE and POL, etc.) for controlling the data driving IC8using a main clock signal MCLK and horizontal and vertical synchronizing signals H and V inputted from the exterior thereof. The data control signals are applied to the data driving IC8through each transmission line included in a data control signal bus16. Further, the control signal generator3generates and supplies gate control signals (i.e., GSC, GSP and GOE, etc.) for controlling the gate driving IC (not shown) to the gate driving IC through a control signal bus (not shown).

The data aligner5aligns pixel data R, G, and B inputted from the exterior thereof in conformity to the six-bus system to supply to the data driving IC8. In other words, the data aligner5divides the pixel data R, G, and B into even-numbered pixel data RO, GO, and BO and even-numbered pixel data RE, GE, and BE to simultaneously supply to the data driving IC8through each three odd-numbered data buses12and each three even-numbered data buses14. Herein, when each pixel data RD, GD, and BD consists of a 6-bit signal, each of the odd-numbered data buses12and the even-numbered data buses14consists of6data transmission lines. Thus, the data buses include36data transmission lines in total.

The data driving IC of the conventional LCD transmit the pixel data by the six-bus system to reduce the transmission frequency, thereby reducing the EMI. However, the conventional data driving apparatus fails to reduce the EMI because the number of data transmission lines is increased.

SUMMARY OF THE INVENTION

Accordingly, the present invention is directed to an apparatus and method for data transmission that substantially obviates one or more of problems due to limitations and disadvantages of the related art.

Another object of the present invention is to provide an apparatus and method for data transmission that reduces a data transmission voltage to eliminate the EMI.

To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a data transmission apparatus includes data interfacing means for receiving input data having an input data voltage, lowering the input data voltage, and outputting the lowered input data voltage to a plurality of data transmission lines, and data input means for raising the lowered data voltage back to the input data voltage for driving a liquid crystal display panel.

In the data transmission apparatus, the voltage-divider includes a first resistor arranged in series at each data transmission line, and a second resistor arranged in parallel at each data transmission line and having a resistance value lower than the first resistor.

Herein, the first resistor is arranged at an output terminal of the data interfacing means, and the second resistor is arranged at an input terminal of the data input means.

Alternatively, the first and second resistors are arranged at an output terminal of the data interfacing means.

In another aspect of the present invention, a data transmission method includes lowering an input data voltage of an input data and outputting the lowered input data voltage to a plurality of data transmission lines, and raising the lowered input voltage of the input data back to the input data voltage for driving a liquid crystal display panel.

In another aspect of the present invention, a data driving apparatus of a liquid crystal display for driving a plurality of data lines of a liquid crystal display panel includes a timing controller for aligning input pixel data, for lowering input data voltage of the input pixel data, and for outputting to a plurality of data transmission lines, and a data driver for raising the lowered input data voltages of the pixel data back to the input data voltages for driving the liquid crystal display panel and converting into analog pixel voltage signals to apply the analog pixel voltage signals to the data lines.

In the data driving apparatus, the voltage-divider includes a first resistor arranged in series at each data transmission line, and a second resistor arranged in parallel at each data transmission line and having a resistance value lower than the first resistor.

Herein, the first resistor is arranged at an output terminal of the timing controller, and the second resistor is arranged at an input terminal of the data driver.

Alternatively, the first and second resistors are arranged at an output terminal of the timing controller.

The timing controller generates a plurality of control signals for controlling a driving of the data driver, and lowers voltages of the control signals with the aid of another voltage-divider to output to a plurality of control signal transmission lines.

The voltage-divider includes a first resistor arranged in series at each of the data transmission lines and the control signal transmission lines, and a second resistor arranged in parallel at each of the data transmission lines and the control signal transmission lines and having a resistance value lower than the first resistor.

Herein, the first resistor is arranged at an output terminal of the timing controller, while the second resistor is arranged at an input terminal of the data driver.

Herein, the first resistor is incorporated into the timing controller, and the second resistor is incorporated into the data driver.

Alternatively, the first and second resistors are arranged at an output terminal of the timing controller.

Herein, the first and second resistors are incorporated into the timing controller.

The data driver includes a level shifter array for raising the lowered input data voltages of the input pixel data back to the input data voltages for driving the liquid crystal display panel, and a data driving unit for converting the raised the input data voltages into analog pixel voltage signals to apply the analog pixel voltage signals to the data lines.

DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS

Reference will now be made in detail to the illustrated embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.

FIG. 3is a block diagram showing a configuration of a data driving apparatus of a liquid crystal display according to the present invention.

Referring toFIG. 3, the data driving apparatus includes data driving IC's30for driving data lines of a liquid crystal display panel (not shown) and a timing controller20for controlling the driving of the data driving IC's30.

More specifically, the timing controller20controls the driving of the data driving IC's30and gate driving IC's (not shown) and applies pixel data (i.e., RO, GO, BO, RE, GE, and BE) to the data driving IC's30at the same time. To this end, the timing controller20includes a control signal generator22for generating control signals, and a data aligner24for aligning the pixel data RO, GO, BO, RE, GE, and BE in conformity to the six-bus system.

The control signal generator22generates data control signals (i.e., SSC, SSP, SOE, and POL, etc.) for controlling the data driving IC30using a main clock signal MCLK and horizontal and vertical synchronizing signals H and V inputted from the exterior thereof. The data control signals are applied to the data driving IC30through each transmission line included in a data control signal bus46. Further, the control signal generator22generates and supplies gate control signals (i.e., GSC, GSP, and GOE, etc.) for controlling the gate driving IC (not shown) to the gate driving IC through a control signal bus (not shown).

The data aligner24aligns pixel data R, G, and B inputted from the exterior thereof in conformity to the six-bus system and supplies to the data driving IC30. In other words, the data aligner24divides the pixel data R, G, and B into even numbered odd-numbered pixel data RO, GO, and BO and even-numbered pixel data RE, GE, and BE and simultaneously supplies to the data driving IC30through each three odd-numbered data buses42and each three even-numbered data buses44. Herein, when each pixel data RD, GD, and BD consists of a 6-bit signal, each of the odd-numbered data buses42and the even-numbered data buses44consists of 6 data transmission lines. Thus, the data buses include 36 data transmission lines in total.

Each data transmission line included in the odd-numbered data buses42and the even-numbered data buses44is provided with voltage-dividing resistors R1and R2to reduce voltages of the pixel data RO, GO, BO, RE, GE, and BE outputted from the timing controller20. Further, each control signal transmission line included in the data control signal bus46is provided with voltage-dividing resistors R1and R2to reduce voltages of data control signals outputted from the timing controller20.

More specifically, a first resistor R1having a relatively large resistance value is arranged in series at each of the data transmission lines and the control signal transmission lines connected to the output terminal of the timing controller20. Further, a second resistor R2having a resistance value lower than the first resistor R1is arranged in parallel at each of the data transmission lines and the control signal transmission lines connected to the input terminal of the data driving IC30. Thus, pixel data LRO, LGO, LBO, LRE, LGE, and LBE voltage-dropped in proportion to the resistance value of the first resistor R1are supplied to the data driving IC30through the odd-numbered data buses42and the even-numbered data buses44. Further, data control signals LSSO, LSSC, LSOE and LPOL, etc. voltage-dropped in proportion to the resistance value of the first resistor R1are supplied to the data driving IC30through the data control signal bus46.

For instance, the control signals SSC, SSP, SOE, and POL, etc. outputted from the control signal generator22of the timing controller20and the pixel data RO, GO, BO, RE, GE, and BE outputted from the data aligner24has a swing voltage of about 3.3V as shown inFIG. 4. The source shift clock signal SSC and the pixel data RO, GO, BO, RE, GE, and BE shown inFIG. 4have a swing voltage of about 300 mV with the aid of the voltage-dividing resistors R1and R2arranged at the output terminal of the timing controller20and the input terminal of the data driving IC30, and are transferred through the control signal bus46and the data buses42and44. Voltages of the data control signals LSSC, LSSP, LSOE, and LPOL, etc. and the pixel data LRO, LGO, LBO, LRE, LGE, and LBE transferred through the control signal bus46and the data buses42and44are considerably low in comparison to the previously known values, so that the EMI at the buses42,44, and46is minimized. Herein, the first resistors R1arranged at the output terminal of the timing controller20are integrated along with the timing controller20. Further, the second resistors R2arranged at the input terminal of the data driving IC30are integrated along with the data driving IC30. Alternatively, all the voltage-dividing resistors R1and R2may be arranged at the output terminal of the timing controller20to be integrated along with the timing controller20.

The data driving IC30includes a level shifter array32for converting voltages of the voltage-dropped data control signals LSSC, LSSP, LSOE, and LPOL, etc. and the voltage-dropped pixel data LRO, LGO, LBO, LRE, LGE, and LBE, etc. inputted from the timing controller20into the normal driving voltage, and a data driver34for converting the pixel-data RO, GO, BO, RE, GE, and BE into analog pixel voltage signals and supplying them to the data lines.

The level shifter array32raises a low voltage level of data control signals LSSC, LSSP, LSOE, and LPOL, etc. inputted through the control signal bus46and a low voltage level of pixel data LRO, LGO, LBO, LRE, LGE, and LBE inputted through the data buses42and44into the normal driving voltages of about 3.3V. The level shifter array32then outputs the normal driving voltage level. To this end, the level shifter array32includes voltage amplifiers36arranged at the data control signal input lines and the pixel data input lines as shown inFIG. 5. The voltage amplifier36must have a Schmitt-trigger characteristic capable of generating a sharp rectangular wave signal regardless of the input waveform.

The data driver34drives the data lines using the data control signals SSP, SSC, SOE, and POL, etc. and the pixel data RO, GO, BO, RE, GE, and BE raised into the normal driving voltage by means of the level shifter array32. More specifically, the data driver34sequentially latches the pixel data RO, GO, BO, RE, GE, and BE in response to the source start pulse SSP and the source shift clock signal SSC and then simultaneously outputs the latched pixel data in response to the source output enable signal SOE. Subsequently, the data driver34converts the simultaneously outputted pixel data RO, GO, BO, RE, GE, and BE into the pixel voltage signals by using gamma voltages to supply the pixel voltage signals to the data lines. In this case, the data driver34converts the pixel data into the pixel voltage signals in such a manner to be suitable for a dot inversion driving system or a column inversion driving system in response to the polarity control signal POL.

As described above, the data driving apparatus of the LCD according to the present invention considerably lowers voltage levels of the control signals and the pixel data from the timing controller20with the aid of the voltage-dividing resistors to transfer the signals and the data to the data driving IC and then raises them into the normal driving voltage. Thus, the EMI at the data transmission path is minimized and power consumption is much reduced in the present invention.

Moreover, such a technique of lowering the data voltage transferred through the buses with the aid of the voltage-dividing resistors to transfer the lowered data voltage and to raise them back to the normal driving voltage may be easily applicable to a data transmission apparatus providing a parallel data transmission using a multiple bus so as to minimize EMI.

As described above, according to the present invention, the data voltage is considerably lowered with the aid of the voltage-dividing resistors to be transmitted through the buses and then raised back to the normal driving voltage, so that the EMI between the data signals transferred simultaneously through a multiple bus may be minimized. Accordingly, a distortion of the data signals caused by the EMI may be prevented in the present invention.

Furthermore, according to the present invention, voltages of the control signals and the pixel data from the timing controller is considerably lowered with the aid of the voltage-dividing resistors to be transmitted to the data driving IC and then raised back to the normal driving voltage. Thus, it minimizes the EMI at the data transmission path and reduces power consumption.