Method for inhibiting a converter with distributed energy stores

A method for inhibiting a converter having at least two phase modules is disclosed. Each phase module has an upper and a lower valve branch, with each upper and lower valve branch having a plurality of two-pole submodules which are electrically connected in series and each have a unipolar energy storage capacitor, with a series connection of two turn-off semiconductor switches each being connected in parallel with an antiparallel connected diode. With the method, the submodules in an upper and a lower valve branch in each phase module in the converter are controlled to a switching state III, staggered in time. This considerably reduces the voltage load for the converter and a connected polyphase motor, or a connected power supply system.

CROSS-REFERENCES TO RELATED APPLICATIONS

This application claims the priority of German Patent Application, Serial No. 10 2010 030 078.0, filed Jun. 15, 2010, pursuant to 35 U.S.C. 119(a)-(d), the content of which is incorporated herein by reference in its entirety as if fully set forth herein.

BACKGROUND OF THE INVENTION

The present invention relates to a relates to a method for inhibiting a converter with distributed energy stores having at least two phase modules, which each have an upper and a lower valve branch, which each have a multiplicity of two-pole submodules, which are electrically connected in series and each have a unipolar energy storage capacitor, with which a series circuit of two semiconductor switches which can be turned off, each with a diode connected back-to-back in parallel, is connected electrically in parallel.

A conventional converter with distributed energy stores is illustrated schematically inFIG. 1. According toFIG. 1, this converter2has three phase modules41,42and43, which each have an upper and a lower respective valve branch P1and N1, P2and N2as well as P3and N3. These two valve branches P1, N1; P2, N2and P3, N3in each phase module41,42and43, respectively, are connected to form one bridge arm. A junction point between an upper and a lower valve branch P1and N1, P2and N2as well as P3and N3is passed out as a respective connection L1, L2or L3, respectively, on the AC voltage side of the respective phase module41,42or43. A polyphase motor6or a power supply system is connected to these connections L1, L2or L3on the AC side. The phase modules41,42and43are electrically connected in parallel with one another and are connected to form a DC voltage feed device, which is not illustrated in any more detail but is connected to the DC voltage connections P0and N0of the converter2with distributed energy stores CSM. A generated DC voltage Udcis present between these DC voltage connections P0and N0.

This illustration of the converter2with distributed energy stores CSMlikewise shows that each valve branch P1, N1, P2, N2, P3and N3has a multiplicity of two-pole submodules SM1, SM2, . . . , SMn, which are electrically connected in series. Each two-pole submodule SM1, SM2, . . . , SMn, based on the illustration of the submodule SM1, has a unipolar energy storage capacitor CSM, two semiconductor switches S1and S2which can be turned off, and two diodes D1and D2. The two semiconductor switches S1and S2which can be turned off are electrically connected in series, and this series circuit is electrically connected in parallel with the unipolar energy storage capacitor CSM. A respective diode D1or D2is connected back-to-back in parallel with the semiconductor switches S1and S2which can be turned off. These diodes D1and D2therefore each form a freewheeling diode. A junction point between the two semiconductor switches S1and S2which can be turned off is passed out as the module connection X2. The negative connection of the unipolar energy storage capacitor CSMforms a second module connection X1. When the unipolar energy storage capacitor CSMhas been charged, a capacitor voltage USMis dropped across it.

These capacitor voltages USM1, USM2, USMnof the two-pole submodules SM1, SM2, . . . , SMn in each valve branch P1, N1, P2, N2, P3and N3are respectively added to form a valve voltage UZP1, UZN1, UZP2, UZN2, UZP3and UZN3. The addition of in each case two valve voltages UZP1, UZN1as well as UZP2and UZN2as well as UZP3and UZN3of a respective phase module41,42or43results in the DC voltage Udcwhich is present between the DC voltage connections P0and N0.

The configuration of each two-pole submodule SM in the converter2with distributed energy stores CSMallows each submodule SM each to be controlled to three switching states, specifically the switching states I, II and III. In the switching state I, the semiconductor switch S1which can be turned off is in the ON-state, and the semiconductor switch S2which can be turned off is in the OFF-state. The capacitor voltage USMis therefore present as the terminal voltage UX2X1at the module connections X2and X1of the submodule SM, independently of the direction of a branch current iZflowing. In the switching state II, the semiconductor switch S1which can be turned off is in the OFF-state, and the semiconductor switch S2which can be turned off is in the ON-state, thus resulting in a terminal voltage UX2X1with the amplitude zero being present at the module connections X2and X1of the submodule SM, likewise independently of the direction of a branch current iZflowing. In the switching state III both semiconductor switches S1and S2which can be turned off are in the OFF-state. The amplitude of the terminal voltage UX2X1of each submodule SM when in the switching state III is dependent on the direction of a branch current iZflowing. If the branch current is greater than zero, then the amplitude of the terminal voltage UX2X1of the submodule SM corresponds to the amplitude of the capacitor voltage USMin this submodule SM. In contrast, if the branch current is less than zero, the amplitude of the terminal voltage is equal to zero. If no branch current iZis flowing and if the voltage split between the semiconductor switches S1and S2which can be turned off in the submodule SM is symmetrical, the amplitude of the terminal voltage UX2X1corresponds to half the amplitude of the capacitor voltage USMin the submodule SM.

In the conventional converter2with distributed energy stores CSM, only the switching states I and II of the submodules SM are used during normal operation of this converter2. The switching state III is used only in the event of defects, for example a short at its DC voltage connections P0and N0, for a deliberate open circuit (interruption of converter operation) and for negligibly short switching delay times for the semiconductor switches S1and S2which can be turned off in a submodule SM, when a switching state change occurs.

It is known that a so-called pulse inhibitor can be activated, in order to turn the converter off in critical operating states, for example overcurrent, overvoltage, failure of a drive, failure of a control system, failure of communications between the converter valve and the modulator, . . . , such that this converter is in a safe state after operation of the pulse inhibitor. This pulse inhibitor can be implemented by inhibiting all the converter valves in the self-commutated converter (inverter). This is preferably done by interruption of the supply voltage, which is derived from an external voltage, for the optocouplers in the associated drive circuits.

When a pulse inhibitor in a converter2with distributed energy stores CSMis triggered, then all the drive signals for the semiconductor switches S1and S2which can be turned off in all the submodules SM1, SM2, . . . , SMn in all the valve branches P1, N1, P2, N2, P3and N3in the phase modules41,42and43in the converter2with distributed energy stores CSMmust be inhibited at the same time, as shown inFIG. 1.

FIG. 2ashows for sake of clarity in more detail only the phase module41of the converter2with distributed energy stores CSMdepicted inFIG. 1. The submodules SM1, . . . , SM4in the upper and lower valve branches P1and N1in this phase module41illustrate a switching state distribution during normal operation of this converter2. Of the four submodules SM1, . . . , SM4in the upper valve branch P1, the submodules SM2to SM4are in the switching state I, and the submodule SM1is in the switching state II. Of the submodules SM1, . . . , SM4in the lower valve branch N1, the submodules SM1to SM3are in the switching state II, and the submodule SM4is in the switching state I. The amplitude of the DC voltage Udcwhich is present at the DC voltage connections P0and N0of the converter2is therefore Udc=4·USM. The voltage uZPin the upper valve branch P1with respect to a virtual neutral point is given by uZP=3·USM, while, in contrast, the voltage uZNin the lower valve branch N1is given by uZN=1·USM.

Once a pulse inhibitor is triggered, all the submodules SM1to SM4in the upper and lower valve branches P1and N1are switched to the switching state III. The phase module41with the submodules SM1to SM4in the switching state III is illustrated inFIG. 2b. The pulse inhibitor can be set on the one hand by a fault occurring (for example an overcurrent) by an open-loop and closed-loop control device, which is not illustrated in any more detail, in the converter2, whereas on the other hand autonomously by the submodules SM1to SM4(disturbance with or breakdown of communication, overvoltage). Since the time at which a pulse inhibitor is set cannot be predicted, the voltages uZPand uZNand/or their rates of change duZP/dt and duZN/dt over the valve branches P1and N1in a phase module41are governed solely by the direction of the corresponding branch current iZP1and iZN1when the pulse inhibitor is set.

On the assumption that the sum of the two branch voltages uZPand uZNin a respective phase41,42or43corresponds on average to the DC voltage Udcduring normal operation, this results in the voltages and voltage changes as shown in the following table after a pulse inhibitor has been set.

Direction of thebranch currentsiZP/iZNpos/pospos/negneg/posneg/neguZPUdcUdc00uZNUdc0Udc0uZP+ uZN2 UdcUdcUdc0Δ(uZP+ uZN) *+Udc00−Udc* Assumption: mean sum of the branch voltages before the pulse inhibitor (uZP+ uZN) = Udc

It is also assumed that the capacitor voltages USMin each submodule SM on average have a value of USM=Udc/nsub, where nsubrepresents the number of series-connected submodules SM1, . . . , SMn in each valve branch P1, N1, P2, N2, P3and N3in the converter2with distributed energy stores CSM.

As can be seen from this table, two worst-case scenarios occur with respect to the voltage change in the branches in one phase when a pulse inhibitor is set. The maximum voltage change in the sum of the branch voltages uZPand uZNin a phase module41,42and43is ±Udcand occurs when both branch currents iZPand iZNin a phase module4have the same mathematical sign. This state is maintained until one of the branch currents has been commutated down to zero.

Switching on the switching state III results in commutation processes from the semiconductor switch S1which can be turned off to a diode D2in said submodules SM2, SM3, SM4in the upper valve branch P1and the submodule SM4in the lower valve branch N1in the phase module41, if, before setting of the pulse inhibitor, the sum of the branch voltages uZPand uZNin a phase module41is on average equal to the DC voltage Udcbetween the DC voltage connections P0and N0, and the branch currents iZPand iZNhave a negative mathematical sign. When the switching state III is switched on, no commutation processes occur in the submodule SM1in the upper valve branch P1and the submodules SM1, SM2, SM3in the lower valve branch N1in the phase module41if, before the setting of the pulse inhibitor, the sum of the branch voltages uZPand uZNin a phase module41is on average equal to the DC voltage Udcand the branch currents iZPand iZNhave a negative mathematical sign since the diode D2carried the corresponding branch current before switching on the switching state III.

In contrast, commutation processes take place from the semiconductor switch S2which can be turned off to the diode D1in said submodules as a result of switching on the switching state III in the submodule SM1in the upper valve branch P1and the submodules SM1, SM2, SM3in the lower valve branch N1in the phase module41if, before setting of the pulse inhibitor, the sum of the branch voltages uZPand uZNof a phase module41is on average equal to the DC voltage Udcbetween the DC voltage connections Poand No, and the branch currents iZPand iZNhave a positive mathematical sign. No commutation processes take place when the switching state III is switched on in the submodules SM2, SM3, SM4in the upper valve branch P1and the submodule SM4in the lower valve branch N1in the phase module41if, before setting of a pulse inhibitor, the sum of the branch voltages uZPand UZNof a phase module41is on average equal to the DC voltage Udcand the branch currents iZPand iZNhave a negative mathematical sign, since the diode D1carried the corresponding branch current before switching on the switching state III.

A voltage rate of change which, for example, may be 4 kV/μs can be assumed for a semiconductor switch S1or S2which can be turned off in each submodule SM, for every voltage change which occurs during a commutation process. This then results in a voltage rate of change across the two valve branches P1and N1in the phase module41with a value of 16 kV/μs, because there are four submodules SM in the phase module41in the switching state I before the setting of a pulse inhibitor. The greater the number of submodules SM which are used in each valve branch P1, N1, P2, N2, P3and N3in the converter3with distributed energy stores CSM, the higher is the value of the voltage change per phase module41,42and43.

In order to obtain a respective output voltage uL10, UL20, UL30with as sinusoidal a waveform as possible at the respective output L1, L2or L3of a respective phase module41,42or43in the converter2with distributed energy stores CSM, twelve or more submodules SM, for example, are used for each valve branch P1, N1, P2, N2, P3and N3. When there are twelve submodules SM for each valve branch P1, N1, P2, N2, P3and N3, the voltage rate of change is already 48 kV/μs.

If the DC voltage Udcwhich is present at the DC voltage connections P0and N0of the converter2with distributed energy stores CSMis assumed to be constant, then said voltage rate of change acts not only on a branch inductor LZbut also on a parasitic inductor Ldcin the DC voltage circuit. This voltage load on the branch inductor LZleads to a large physical size, because of the use of reinforced insulation.

With respect to the output voltages uL10, uL20and uL30of the converter2with distributed energy stores CSM, different worst-case conditions occur in comparison to the converter-internal voltages uZPand uZN. A worst-case situation will be explained below with reference toFIGS. 3aand3b, with respect to the voltage changes in the phase voltages uL10in the phase module41in the converter2as shown inFIG. 1.

Because of the switching state distribution of the submodules SM1to SM4in the valve branches P1and N1in the phase module41in the converter2with distributed energy stores CSMas shown inFIG. 1, the submodules SM1to SM4in the upper valve branch P1are all in switching state II. In contrast, the submodules SM1to SM4in the lower valve branch N1are all in the switching state I. The phase voltage uL10, which is equal to half the difference between the valve voltages uZNand uZP, is Udc/2. If a pulse inhibitor is now set, then this results in a voltage change in the phase voltage UL10which is dependent on the instantaneous current direction of the branch currents iZPand iZN. The following table provides an overview of the voltages and voltage changes over the valve branches P and N in a phase module4after a pulse inhibitor has been set.

The worst-case situation with respect to the voltage change in the phase voltage UL10, uL20or UL30after setting a pulse inhibitor occurs when the following conditions occur before setting of the pulse inhibitor:all the submodules in a valve branch, for example in the valve branch N1, in a phase module are in the switching state Iall the submodules in a corresponding valve branch, for example the valve branch P1, in a phase module are in switching state IIthe branch current, for example the branch current iZN, in the valve branch with the submodules which are in switching state I has a negative mathematical sign, andthe branch current, for example the branch current iZP, in the valve branch with the submodules which are in switching state II has a positive mathematical sign.

In these conditions, the phase voltage uL10jumps from Udc/2 to −Udc/2, or from −Udc/2 to U/dc/2. In these conditions, the change in the phase voltage uL10is therefore ±Udc. If it is now assumed that a voltage rate of change of, for example, 4 kV/μs occurs across each submodule SM in the phase module41in each submodule SM1to SM4in each valve branch P1and N1in a phase module41, because of the commutation from a semiconductor switch S1or S2which can be turned off to a respective diode D2or D1then this results in a value of 16 kV/μs for the voltage rate of change of the phase voltage uL10/dt, uL20/dt and uL30/dt when there are four submodules SM in each valve branch P and N, and in a value of 48 kV/μs when there are twelve submodules SM in each valve branch P and N in a phase module41.

This means in the worst-case situation, in which two phase voltages change suddenly through ±Udcin opposite senses, for a line voltage uL1L2, that a voltage change of ΔuL1L2=±2Udcand a voltage rate of change of 32 kV/μs occurs across an output impedance (stator winding of a connected polyphase motor6) when four submodules SM are used in each valve branch P and N in a phase module41, or of 96 kV/μs when twelve submodules SM are used in each valve branch P and N in a phase module41. In order to prevent a DC voltage feeder on the power supply system side and a polyphase motor6connected on the load side from being excessively damaged when worst-case situations occur, these components must be designed for a very much greater voltage rate of change, thus resulting in additional costs to a not inconsiderable level.

It would therefore be desirable and advantageous to obviate prior art shortcomings and to provide an improved method for inhibiting a converter with distributed energy stores, in which the voltage load in worst-case situations is significantly reduced.

SUMMARY OF THE INVENTION

According to one aspect of the present invention, a method for inhibiting a converter having at least two phase modules, which each phase module having an upper and a lower valve branch, with each upper and lower valve branch having a plurality of two-pole submodules, which are electrically connected in series and each have a unipolar energy storage capacitor, with a series connection of two turn-off semiconductor switches each being connected in parallel with an antiparallel connected diode, includes the steps of a) triggering a pulse inhibitor in response to a fault occurring during operation of the converter, b) controlling a switching state of one two-pole submodule in each valve branch to a switching state III after a pulse inhibitor has been set, c) controlling an additional submodule in each valve branch to a switching state III after a predetermined time interval has elapsed, and d) repeating step c) until all two-pole submodules in each valve branch are controlled to the switching state III.

According to an advantageous feature of the present invention, controlling the switching state of an additional submodule includes controlling either an outer additional submodule or an inner additional submodule in an upper and a lower valve branch in each phase module.

According to another advantageous feature of the present invention, the predetermined time interval is equal to a turn-off delay time of a turn-off semiconductor switch in a two-pole submodule.

According to another advantageous feature of the present invention, the two turn-off semiconductor switches of a two-pole submodule are switched of when the two-pole submodule is in the switching state III.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

The method according to the invention for inhibiting a converter2with distributed energy stores CSMas shown inFIG. 1will now be explained in more detail with reference toFIGS. 4ato4e. According to the method according to the invention, after a pulse inhibitor has been set, the submodules SM1to SM4in an upper and lower valve branch P1and N1in each phase module41,42and43in the converter2are no longer controlled at the same time to the switching state III, but staggered in time. This time staggering of the processing of a pulse inhibitor which has been set is illustrated by four switching state distributions of the submodules SM1to SM4in the valve branches P1and N1in the phase module41, with the arrows between two respective switching state distributions in the phase module41as shown inFIGS. 4bto4eeach symbolizing a predetermined time interval Δt for the time-staggered or stepped implementation of the processing of a pulse inhibitor which has been set.

FIG. 4aillustrates the phase module41in the converter2as shown inFIG. 1with a random switching state distribution of the submodules SM1to SM4in its upper and lower valve branches P1and N1. Of the submodules SM1to SM4in the valve branches P1and N1in the phase module41, the submodules SM1and SM2are each in the switching state II while, in contrast, the submodules SM3and SM4are each in the switching state I. If a pulse inhibitor is now set, then, in a first step at the time t1(FIG. 4b), one submodule SM1in the upper and lower valve branches P1and N1is in each case controlled to the switching state III. After a predetermined time interval Δt has elapsed, that is to say at the time t2(FIG. 4c), a further submodule SM2in the upper and lower valve branches P1and N1in the phase module41is in each case controlled to the switching state III. After a predetermined time interval Δt has elapsed, specifically at the time t3(FIG. 4d), a further submodule SM3in the upper and lower valve branches P1and N1in this phase module41is in each case controlled to the switching state III. After a further time interval Δt has elapsed, at the time t4(FIG. 4e), a further submodule SM4in the upper and lower valve branches P1and N1in this phase module41is controlled to the switching state III. At the time t4, all the submodules SM1to SM4in each valve branch P1, N1, P2, N2, P3and N3in the converter2with distributed energy stores CSMare therefore in the switching state III, with a pulse inhibitor which has been set being implemented in a staggered form, according to the invention.

There is a predetermined time interval Δt in each case as the time stagger between the individual method steps (FIGS. 4bto4e), and this preferably corresponds to a so-called “delay time” of a semiconductor switch S1or S2which can be turned off in a submodule SM. This delay time of a semiconductor switch S1or S2which can be turned off in a submodule SM is the minimum time interval Δt which can be implemented. After a minimum time interval Δt has in each case elapsed, a switching state change of a submodule SM is complete. This ensures that the voltage load in each time step of the stepped processing of a pulse inhibitor which has been set corresponds at most only to the voltage rate of change of two submodules SM.

For example, if the voltage rate of change in each submodule SM is 4 kV/μs, the maximum du/dt load during each switching state change is only 8 kV/μs in comparison to 16 kV/μs when a pulse inhibitor is processed in the conventional manner. This means that the method according to the invention at least halves the voltage load for converter-internal voltages and phase output voltages.

When a pulse inhibitor which has been set is processed staggered in time according to the invention, there is no need to control in each case one submodule SM in an upper and a lower valve branch to the switching state III at the same time, while, instead it is also possible to control only one submodule SM in each phase module41,42and43to the switching state III. It is irrelevant which of the submodules SM in a phase module41,42and43is started with. The sequence on the basis of which the submodules SM in an upper and a lower valve branch P1, N1, P2, N2, P3and N3and a phase module41,42and43are controlled to the switching state III is also irrelevant for the reduction in the du/dt load.

It is important to provide a time offset between the switching state changes of in each case one submodule SM in an upper and a lower valve branch P1, N1, P2, N2, P3and N3and a phase module41,42and43.

If only one submodule SM in a phase module41,42and43in the converter2with distributed energy stores CSMas shown inFIG. 1is in each case controlled to the switching state III when a pulse inhibitor which has been set is processed staggered in time, twice as many time steps are required instead of the four time steps shown inFIG. 4, that is to say eight time steps are required, before a pulse inhibitor which has been set has been implemented. Considerably more time is accordingly required to implement a pulse inhibitor which has been set. If there are twelve or more submodules in each valve branch P1, N1, P2, N2, P3and N3in the converter2as shown inFIG. 1, it is necessary to check, depending on the application of the converter, whether the protection functions which are initialized with the pulse inhibitor can be satisfied.

The pulse inhibitor is set in order to turn off the converter2with distributed energy stores CSMin critical operating states, for example overcurrent, overvoltage or failure of the drive, such that the converter2is in a safe state after the pulse inhibitor has been applied. The time available for turning off the converter2is not unlimited, because of these fault situations.

The method according to the invention is therefore used, wherein two submodules, specifically one submodule in the upper valve branch P1, P2, P3and one submodule SM in the lower valve branch N1, N2, N3, are controlled to the switching state III at the same time in each time stagger.