LOW FLICKER NOISE DIFFERENTIAL VOLTAGE REFERENCE GENERATOR CIRCUIT

A bandgap voltage generator circuit is formed using only bipolar transistors. The bandgap voltage generator circuit includes output nodes generating first and second bandgap reference currents. A transconductance amplifier circuit in a current control feedback loop of the bandgap voltage generator circuit has differential inputs which receive base currents. A differential amplifier circuit has inputs configured to receive the first and second bandgap reference currents and includes a compensation current sink circuit configured to sink compensation currents from the first and second bandgap reference currents which correspond to the base current received at the differential inputs of the transconductance amplifier circuit.

TECHNICAL FIELD

The present disclosure generally relates to differential voltage reference generator circuits and, in particular, to a differential voltage reference generator with low flicker noise.

BACKGROUND

Reference is made toFIGS.1A and1Bwhich show a circuit diagram for a conventional current-mode bandgap reference voltage generator circuit10. The circuit10includes a current mirroring circuit12and bandgap core circuit14.

The current mirroring circuit12is formed by p-channel metal oxide semiconductor field effect transistor (MOSFET) devices M1, M2and M3. The source terminals of transistors M1, M2and M3are coupled, preferably connected, to the supply node Vdd. The gate terminals of transistors M1, M2and M3are coupled, preferably connected, to each other and biased by a voltage Vout to generate mirrored currents. The drain terminal of transistor M1outputs a first mirrored current, the drain terminal of transistor M2outputs a second mirrored current, and the drain terminal of transistor M3outputs a third mirrored current. The third mirrored current output from the drain terminal of transistor M3is applied across resistor R3to generate the bandgap reference voltage Vbg at an output node of the circuit10. Resistor R3has a first terminal coupled, preferably connected, to the drain of transistor M3at the output node and a second terminal coupled, preferably connected, to the ground node Gnd.

The bandgap core circuit14includes a differential amplifier circuit16, for example comprising an operational amplifier (OP-AMP), configured in a current control feedback loop that generates the bias voltage Vout which controls generation of the mirrored currents by the transistors M1, M2and M3. The non-inverting (+) input of the differential amplifier circuit16receives a voltage V+ at the drain of the transistor M1and the inverting (−) input of the differential amplifier circuit16receives a voltage V− at the drain of the transistor M2. The bandgap core circuit14further includes PNP bipolar transistors Q1and Q2. The collector terminals of transistors Q1and Q2are coupled, preferably connected, to the ground node Gnd. The base terminals of transistors Q1and Q2are coupled, preferably connected, to each other and to the ground node Gnd. The transistors Q1and Q2of the bandgap core circuit14are thus each connected in diode-configuration. The emitter terminal of transistor Q1is coupled, preferably connected, to an intermediate node18. The emitter terminal of transistor Q2is coupled, preferably connected, to the drain of transistor M2at the inverting (−) input of the differential amplifier circuit16. A resistor R1has a first terminal coupled, preferably connected, to the intermediate node18and a second terminal coupled, preferably connected, to the drain of transistor M1at the non-inverting (+) input of the differential amplifier circuit16. A first resistor R2has a first terminal coupled, preferably connected, to the drain of transistor M1at the non-inverting (+) input of the differential amplifier circuit16and a second terminal coupled, preferably connected, to the ground node Gnd. A second resistor R2has a first terminal coupled, preferably connected, to the emitter of transistor Q2at the inverting (−) input of the differential amplifier circuit16and a second terminal coupled, preferably connected, to the ground node Gnd.

As an example, the differential amplifier circuit16includes a differential pair20of input transistors M5, M6coupled to a current mirror load circuit22formed by transistors M7, M8. The input transistors M5, M6are n-channel MOSFETs. The load transistors M7, M8are p-channel MOSFETs. The common source terminals of the transistors M5and M6are coupled, preferably connected, to a tail current source20connected to the ground node Gnd. The gate terminal of input transistor M5(at the non-inverting (+) input) receives the voltage V+ at the drain of the transistor M1and the gate terminal of the input transistor M6(at the inverting (−) input) receives the voltage V− at the drain of the transistor M2. The drain terminal of input transistor M5is coupled, preferably connected, to the drain and gate terminals of the load transistor M7. The drain terminal of input transistor M6is coupled, preferably connected, to the drain terminal of the load transistor M8at the output of the amplifier. The gate terminals of the transistors M7, M8are coupled, preferably connected, to each other. The transistor M7is connected in diode-configuration. The output voltage Vout of the differential amplifier circuit16is generated at the common drain terminals of transistors M6, M8and is a function of the difference between the voltages V+ and V−, and the magnitudes of the first, second and third mirrored currents at the drains of transistors M1, M2and M3is a function of the voltage Vout.

The principle of operation of the circuit10is to generate a complementary to absolute temperature (CTAT) voltage and a proportional to absolute temperature (PTAT) voltage, and then add those voltages in a scaled proportion to achieve a cancelation of the positive and negative temperature coefficients.

The generating of the PTAT component uses the difference in base to emitter voltages (VBE) between two forward bias voltages having different current densities (m) using transistors Q1and Q2. The voltage across resistor R1is then PTAT in nature:

The current flowing through the resistor R2is CTAT:

The output bandgap voltage Vbg can be expressed as follows:

The operating point of the circuit10can accordingly be scaled by setting of the resistances for resistors R2and R3, and the temperature coefficient can be adjusted by setting of the resistances for resistors R1and R2.

There is a recognized problem with the circuit10. The MOSFETs M5, M6, M7and M8introduce flicker (1/f) noise which can perturb the output voltage Vbg. This is a concern when the output voltage Vbg provides a reference voltage for a noise sensitive circuit (like an analog-to-digital converter (ADC)).

To address the issue of flicker noise, there is a teaching in the art to use a chopper technique. See, for example, U.S. Patent Application Publication No. 2010/0295529 and U.S. Pat. No. 10,983,547 (both incorporated herein by reference). However, there are a number of drawbacks associated with the use of the chopper technique including the need for more complicated circuitry and a stable (for example, external) clock source to control the switching operations.

SUMMARY

In an embodiment, a circuit comprises: a bandgap voltage generator circuit formed using only bipolar transistors and including a transconductance amplifier circuit in a current control feedback loop having a differential input which receives a bipolar transistor base current, wherein the bandgap voltage generator circuit includes a first output node generating a first current comprising a bandgap reference current plus the bipolar transistor base current and a second output node generating a second current comprising the bandgap reference current minus the bipolar transistor base current; and a transresistance amplifier circuit comprising: a differential amplification circuit having a non-inverting input configured to receive the first current, an inverting input configured to receive the second current, a non-inverting output and an inverting output; a first feedback resistor coupled between the non-inverting input and the inverting output; a second feedback resistor coupled between the inverting input and the non-inverting output; and a compensation current sink circuit configured to sink a first compensation current from the non-inverting input corresponding to the base current and configured to sink a second compensation current from the inverting input corresponding to the base current.

In an embodiment, a circuit comprises: a first current mirroring circuit including a first bipolar transistor, a second bipolar transistor, a third bipolar transistor and a fourth bipolar transistor, wherein a first current is output by the third bipolar transistor and a second current is output by the fourth bipolar transistor; a second current mirroring circuit configured to mirror the second current and generate a third current; a bandgap core circuit including: a fifth bipolar transistor and sixth bipolar transistor coupled, respectively, to the first and second bipolar transistors and configured to use a difference in base to emitter voltages of the fifth and sixth bipolar transistors to generate a complementary to absolute temperature (CTAT) voltage and a proportional to absolute temperature (PTAT) voltage from currents output by the first and second bipolar transistors; and a transconductance amplification circuit having a differential input comprising seventh and eighth bipolar transistors coupled, respectively, to the first and second bipolar transistors, the seventh bipolar transistor having a base configured to receive a first base current and the eighth bipolar transistor having a base configured to receive a second base current, and an output coupled to apply a bias current to base terminals of the first, second, third and fourth bipolar transistors; and a differential amplification circuit having a non-inverting input configured to receive the first current, an inverting input configured to receive the third current, a ninth bipolar transistor having a base coupled to the non-inverting input and configured to sink a first compensation current corresponding to the first base current and a tenth bipolar transistor having a base coupled to the inverting input and configured to sink a second compensation current corresponding to the second base current.

DETAILED DESCRIPTION

Reference is now made toFIGS.2A and2Bwhich show a circuit diagram for a flicker noise free current-mode bandgap reference voltage generator circuit110. The circuit110includes a current mirror circuit112, a bandgap core circuit114and a compensation current sink circuit115.

The current mirror circuit112is formed by PNP bipolar transistors QA, QB and QC. The emitter terminals of transistors QA, QB and QC are coupled, preferably connected, to the supply node Vdd. The base terminals of transistors QA, QB and QC are coupled, preferably connected, to each other and biased by a bias current Ibias to generate mirrored currents. The collector terminal of transistor QA outputs a first mirrored current, the collector terminal of transistor QB outputs a second mirrored current, and the collector terminal of transistor QC outputs a third mirrored current. The third mirrored current output from the collector terminal of transistor QC is applied across resistor R3to generate the bandgap reference voltage Vbg at an output node134of the circuit110. Resistor R3has a first terminal coupled, preferably connected, to the collector of transistor QC at the output node134and a second terminal coupled, preferably connected, to the ground node Gnd.

The bandgap core circuit114includes a differential operational transconductance amplifier (OTA) circuit116configured in a current control feedback loop that generates an output current Iout which controls generation of the mirrored currents by the transistors QA, QB and QC. The non-inverting (+) input of the differential OTA circuit116receives a voltage V+ at the collector of the transistor QA and the inverting (−) input of the differential OTA circuit116receives a voltage V− at the collector of the transistor QB. The bandgap core circuit114further includes PNP bipolar transistors Q1and Q2. The collector terminals of transistors Q1and Q2are coupled, preferably connected, to a virtual ground node150. The base terminals of transistors Q1and Q2are coupled, preferably connected, to each other and to the virtual ground node150. The transistors Q1and Q2of the bandgap core circuit114are thus each connected in diode-configuration. The emitter terminal of transistor Q1is coupled, preferably connected, to an intermediate node118. The emitter terminal of transistor Q2is coupled, preferably connected, to the collector of transistor QB at the inverting (−) input of the differential OTA circuit116. A resistor R1has a first terminal coupled, preferably connected, to the intermediate node18and a second terminal coupled, preferably connected, to the collector of transistor QA at the non-inverting (+) input of the differential OTA circuit116. A first resistor R2has a first terminal coupled, preferably connected, to the collector of transistor QA at the non-inverting (+) input of the differential OTA circuit116and a second terminal coupled, preferably connected, to the virtual ground node150. A second resistor R2has a first terminal coupled, preferably connected, to the emitter of transistor Q2at the inverting (−) input of the differential OTA circuit116and a second terminal coupled, preferably connected, to the virtual ground node150.

A resistor Rshift has a first terminal coupled, preferably connected, to the virtual ground node150and a second terminal coupled, preferably connected, to a circuit ground node Gnd. It will be noted that in an alternative implementation, the resistor Rshift may be omitted and the virtual ground node150and ground node Gnd would then be the same node. This alternative implementation is indicated inFIG.2Aby the dotted double-arrow connection152.

The differential OTA circuit116includes a differential pair120of input transistors Q5, Q6coupled to a current mirror load circuit122formed by transistors Q7, Q8. The input transistors Q5, Q6are NPN bipolar transistors. The load transistors Q7, Q8are PNP bipolar transistors. The common emitter terminals of the transistors Q5and Q6are coupled, preferably connected, to a tail current source124connected to the ground node Gnd. The base terminal of input transistor Q5(at the non-inverting (+) input) receives the voltage V+ at collector of the transistor QA (as well as a base current Ib) and the base terminal of the input transistor Q6(at the inverting (−) input) receives the voltage V− at collector of the transistor QB (as well as a base current Ib). The collector terminal of input transistor Q5is coupled, preferably connected, to the collector and base terminals of the load transistor Q7. The collector terminal of input transistor Q6is coupled, preferably connected, to the collector terminal of the load transistor Q8at the output of the amplifier. The base terminals of the transistors Q7, Q8are coupled, preferably connected, to each other. The transistor Q7is connected in diode-configuration. The output current Iout of the differential OTA circuit116generated at the common collector terminals of transistors Q6and Q8is a function of the difference between the voltages V+ and V−. A stabilization capacitor Cs has a first terminal coupled, preferably connected, to the common collector terminals of transistors Q6and Q8and a second terminal coupled, preferably connected, to the ground node Gnd.

The use of an OTA amplifier116formed by bipolar transistor devices, as opposed to the differential amplifier16formed by MOSFET devices inFIG.1B, assists in with addressing the flicker (1/f) noise concern. Flicker noise is also addressed by using bipolar transistors QA, QB and QC in the current mirroring circuit112, as opposed to MOSFET devices M1, M2and M3inFIG.1A. The main drawback of using bipolar transistors for the differential pair120of input transistors Q5, Q6is their base current Ib. It will be noted that the mirrored current flowing through each of the transistors QA, QB and QC has three components: the PTAT current Iptat across R1, the CTAT current Ictat across R2, and the base current Ib flowing into the bases of the pair of transistors120. The base current Ib is unwanted and must be addressed by compensation. The effect of this base current Ib is compensated at the output node134where the reference voltage Vbg is generated. The compensation current sink circuit115operates to sink a compensation current Ib′ from the third current flowing through transistor QC, wherein the compensation current Ib′ corresponds to (i.e., is equal or substantially equal within the limits of circuit tolerances to) the base current Ib.

The current sink circuit115replicates one-half of the differential OTA circuit116with a bipolar PNP transistor QD (matching the transistor Q7), an NPN transistor QE (matching the transistor Q5), and a current source140(corresponding to the tail current source124but with a different current magnitude). The emitter terminal of transistor QD is coupled, preferably connected, to the supply node Vdd. The collector and base terminals of transistor QD are coupled, preferably connected, to each other at intermediate node142. The transistor QD is connected in diode-configuration. The collector terminal of transistor QE is coupled, preferably connected, to intermediate node142. The base terminal of transistor QE is coupled, preferably connected, to the output node134and is biased by the compensation current Ib′ corresponding to the base current Ib at the pair of transistors120in amplifier116. The emitter terminal of transistor QE is coupled, preferably connected, to current source140connected to the ground node Gnd. Because the current sink circuit115replicates only one-half of the differential OTA circuit116, the current source140sinks a current Is with a magnitude that is one-half the magnitude of the current2Is sunk by the current source124.

Since the amplifier116is of the OTA-type, it cannot effectively drive a resistive load (i.e., it cannot sink with current Iout a current with a magnitude of31bfrom the connected bases of the transistors QA, QB and QC) without introducing a significant offset to the amplifier input. To address this issue, the bandgap core circuit114further includes a current buffer circuit130. The output current Iout is buffered by the current buffer circuit130to generate the bias current Ibias. The magnitude of the first, second and third mirrored currents at the collectors of transistors QA, QB and QC is a function of the bias current Ibias.

The current buffer circuit130comprises a first follower circuit formed by a first transistor T1having a control terminal coupled, preferably connected, to receive the amplifier output current Iout, a reference terminal coupled, preferably connected, to the ground node Gnd and a follower terminal coupled, preferably connected, to receive a first source current Isrc generated by a first current source150coupled to the supply node Vdd. The current buffer circuit130further comprises a second follower circuit formed by a second transistor T2having a control terminal coupled, preferably connected, to the follower terminal of the transistor T1, a reference terminal coupled, preferably connected, to the supply node Vdd and a follower terminal coupled, preferably connected, to receive a sink current Isnk generated by a second current source152coupled to the ground node Gnd. The bias current Ibias is generated at the follower terminal of the transistor T2.

In a preferred implementation as shown inFIG.2B, the current buffer circuit130is implemented as a source-follower circuit where the first transistor T1is a p-channel MOSFET device and the second transistor T2is an n-channel MOSFET device. The drain of transistor T1is connected to ground and the source of transistor T1is connected to the first current source150and to the gate of transistor T2. The drain of transistor T2is connected to the supply node Vdd and the source of transistor T2is connected to the second current source152and provides the current Ibias. The implementation illustrated using MOSFET devices for transistors T1, T2is preferred because there is no current consumption at the gate terminals. It will be noted that any flicker noise introduced by the use of MOSFET devices for transistors T1, T2is considered to insignificantly contribute to overall noise in the output voltage Vbg and can be ignored.

The use of first and second follower circuits in the current buffer circuit130makes it possible to maintain approximately the same voltage at the collector terminals of transistors Q7, Q8in order to guarantee the linear operation of transistor Q8in generating the current Iout and thus avoid any early differential effect.

In the implementation which uses the resistor Rshift, the resistance of the resistor Rshift is selected as a function of the mirrored first and second currents (in transistors QA and QB) and the base current Ib so that the voltage drop across the resistor is equal or substantially equal (within design tolerances) to the voltage drop across the current source124in the amplifier116.

Reference is now made toFIGS.3A,3B and3Cwhich show a circuit diagram for a flicker noise free differential voltage reference generator circuit210. The circuit210includes a current mirror circuit212,219, a bandgap core circuit214and a transresistance amplifier circuit215with a compensation current sinking functionality.

The current mirror circuit212is formed by PNP bipolar transistors QA, QB, QC and QD as well as NPN bipolar transistors QE and QF. The emitter terminals of transistors QA, QB, QC and QD are coupled, preferably connected, to the supply node Vdd. The base terminals of transistors QA, QB, QC and QD are coupled, preferably connected, to each other and biased by a bias current Ibias to generate mirrored currents. The collector terminal of transistor QA outputs a first mirrored current, the collector terminal of transistor QB outputs a second mirrored current, the collector terminal of transistor QC outputs a third mirrored current and the collector terminal of transistor QD outputs a fourth mirrored current. The third mirrored current output from the collector terminal of transistor QC is applied (perhaps through a series-connected input resistor—not explicitly shown) to the non-inverting (+) input of a fully differential amplifier217of the transresistance amplifier circuit215. The fourth mirrored current output from the collector terminal of transistor QD is mirrored by transistors QE and QF of circuit219and applied (perhaps through a series-connected input resistor—not explicitly shown) to the inverting (−) input of the fully differential amplifier217.

The transresistance amplifier circuit215further includes a first feedback resistor R3having a first terminal coupled, preferably connected, to the non-inverting input of the fully differential amplifier217and a second terminal coupled, preferably connected, to the inverting output of the fully differential amplifier217. A second feedback resistor R3has a first terminal coupled, preferably connected, to the inverting input of the fully differential amplifier217and a second terminal coupled, preferably connected, to the non-inverting output of the fully differential amplifier217.

The emitter terminals of transistors QE and QF of mirror circuit219are coupled, preferably connected, to a reference voltage (for example, ground) node250, and the collector terminal of transistor QE is coupled, preferably connected, to the collector terminal of transistor QD, the collector terminal of transistor QF is coupled, preferably connected, to the inverting input of fully differential amplifier217, and the base terminals of transistors QE and QF are coupled, preferably connected, to each other and to the collector of transistor QE.

The bandgap core circuit214includes a differential operational transconductance amplifier (OTA) circuit216configured in a current control feedback loop that generates an output current Iout which controls generation of the mirrored currents by the transistors QA, QB, QC and QD. The non-inverting (+) input of the differential OTA circuit216receives a voltage V+ at the collector of the transistor QA and the inverting (−) input of the differential OTA circuit216receives a voltage V− at the collector of the transistor QB. The bandgap core circuit214further includes PNP bipolar transistors Q1and Q2. The collector terminals of transistors Q1and Q2are coupled, preferably connected, to the reference voltage (ground) node250. The base terminals of transistors Q1and Q2are coupled, preferably connected, to each other and to the ground node250. The transistors Q1and Q2of the bandgap core circuit214are thus each connected in diode-configuration. The emitter terminal of transistor Q1is coupled, preferably connected, to an intermediate node218. The emitter terminal of transistor Q2is coupled, preferably connected, to the collector of transistor QB at the inverting (−) input of the differential OTA circuit216. A resistor R1has a first terminal coupled, preferably connected, to the intermediate node218and a second terminal coupled, preferably connected, to the collector of transistor QA at the non-inverting (+) input of the differential OTA circuit216. A first resistor R2has a first terminal coupled, preferably connected, to the collector of transistor QA at the non-inverting (+) input of the differential OTA circuit216and a second terminal coupled, preferably connected, to the ground node250. A second resistor R2has a first terminal coupled, preferably connected, to the emitter of transistor Q2at the inverting (−) input of the differential OTA circuit216and a second terminal coupled, preferably connected, to the ground node250.

The differential OTA circuit216includes a differential pair220of input transistors Q5, Q6coupled to a current mirror load circuit222formed by transistors Q7, Q8. The input transistors Q5, Q6are NPN bipolar transistors. The load transistors Q7, Q8are PNP bipolar transistors. The common emitter terminals of the transistors Q5and Q6are coupled, preferably connected, to a tail current source224connected to the ground node Gnd. The base terminal of input transistor Q5(at the non-inverting (+) input) receives the voltage V+ at collector of the transistor QA (as well as a base current Ib) and the base terminal of the input transistor Q6(at the inverting (−) input) receives the voltage V− at collector of the transistor QB (as well as a base current Ib). The collector terminal of input transistor Q5is coupled, preferably connected, to the collector and base terminals of the load transistor Q7. The collector terminal of input transistor Q6is coupled, preferably connected, to the collector terminal of the load transistor Q8at the output of the amplifier. The base terminals of the transistors Q7, Q8are coupled, preferably connected, to each other. The transistor Q7is connected in diode-configuration. The output current Iout of the differential OTA circuit216generated at the common collector terminals of transistors Q6and Q8is a function of the difference between the voltages V+ and V−. A stabilization capacitor Cs has a first terminal coupled, preferably connected, to the common collector terminals of transistors Q6and Q8and a second terminal coupled, preferably connected, to the ground node Gnd.

The bandgap core circuit214further includes a current buffer circuit230. The output current Iout is buffered by the current buffer circuit230to generate the bias current Ibias. The magnitude of the first, second, third and fourth mirrored currents at the collectors of transistors QA, QB, QC and QD is a function of the bias current Ibias.

The current buffer circuit230comprises a first follower circuit formed by a first transistor T1having a control terminal coupled, preferably connected, to receive the amplifier output current Iout, a reference terminal coupled, preferably connected, to the ground node Gnd and a follower terminal coupled, preferably connected, to receive a first source current Isrc generated by a first current source250coupled to the supply node Vdd. The current buffer circuit230further comprises a second follower circuit formed by a second transistor T2having a control terminal coupled, preferably connected, to the follower terminal of the transistor T1, a reference terminal coupled, preferably connected, to the supply node Vdd and a follower terminal coupled, preferably connected, to receive a sink current Isnk generated by a second current source252coupled to the ground node Gnd. The bias current Ibias is generated at the follower terminal of the transistor T2.

In a preferred implementation as shown inFIG.3B, the current buffer circuit230is implemented as a source-follower circuit where the first transistor T1is a p-channel MOSFET device and the second transistor T2is an n-channel MOSFET device. The drain of transistor T1is connected to ground and the source of transistor T1is connected to the first current source250and to the gate of transistor T2. The drain of transistor T2is connected to the supply node Vdd and the source of transistor T2is connected to the second current source252and provides the current Ibias. The implementation illustrated using MOSFET devices for transistors T1, T2is preferred because there is no current consumption at the gate terminals. It will be noted that any flicker noise introduced by the use of MOSFET devices for transistors T1, T2is considered to insignificantly contribute to overall noise in the output voltage Vbg and can be ignored.

The use of first and second follower circuits in the current buffer circuit230makes it possible to maintain approximately the same voltage at the collector terminals of transistors Q7, Q8in order to guarantee the linear operation of transistor Q8in generating the current Iout and thus avoid any early differential effect.

The fully differential amplifier circuit217includes an input stage formed by a differential pair260of input transistors Q9, Q10coupled to a current mirror load circuit262formed by transistors Q11, Q12. The input transistors Q9, Q10are NPN bipolar transistors. The load transistors Q11, Q12are PNP bipolar transistors. The common emitter terminals of the transistors Q9and Q10are coupled, preferably connected, to a tail current source264connected to the ground node Gnd. The transistors Q9, Q10and tail current source264are configured to respectively match the transistors Q5, Q6and tail current source224(i.e., replica transistor devices and same current magnitudes for the current sources).

The base terminal of input transistor Q9(at the non-inverting (+) input) receives the voltage Vin+ at the collector of the transistor QC (as well as a base current Ib′) and the base terminal of the input transistor Q9(at the inverting (−) input) receives the voltage Vin− at the collector of the transistor QE (as well as a base current Ib′). The collector terminal of input transistor Q9is coupled, preferably connected, to the collector and base terminals of the load transistor Q11. The collector terminal of input transistor Q10is coupled, preferably connected, to the collector terminal of the load transistor Q12at the output of the amplifier. The base terminals of the transistors Q11, Q12are coupled, preferably connected, to each other and receive a bias control voltage VC.

The positive output voltage Vout+ generated at the common collector terminals of transistors Q10and Q12is a function of the difference between the voltages V+ and V− and is applied to an input of an output stage including a first flip voltage follower circuit270. The first flip voltage follower circuit270includes a transistor T3coupled, preferably connected, in series with a transistor T4. Transistors T3and T4are both p-channel MOSFET devices. The positive output voltage Vout+, stabilized by a capacitor Cs, is applied to the gate terminal of transistor T3. The source of transistor T4is coupled, preferably connected, to the supply node Vdd. The drain of transistor T4is coupled, preferably connected, to the source of transistor T3at the non-inverting output of amplifier217where the positive differential output reference voltage REFP is generated. The gate of transistor T4is coupled, preferably connected, to the drain of transistor T3. The drain of transistor T3is further connected to a current source252configured to generate a bias current sunk from transistor T3to the ground node.

The negative output voltage Vout-generated at the common collector terminals of transistors Q9and Q11is a function of the difference between the voltages V+ and V− and is applied to an input of the output stage including a second flip voltage follower circuit272. The second flip voltage follower circuit272includes a transistor T5coupled, preferably connected, in series with a transistor T6. Transistors T5and T6are both n-channel MOSFET devices. The negative output voltage Vout-, stabilized by a capacitor Cs, is applied to the gate terminal of transistor T5. The source of transistor T6is coupled, preferably connected, to the ground node. The drain of transistor T6is coupled, preferably connected, to the source of transistor T5at the inverting output of amplifier217where the negative differential output reference voltage REFN is generated. The gate of transistor T6is coupled, preferably connected, to the drain of transistor T5. The drain of transistor T5is further connected to a current source254configured to generate a bias current sourced to transistor T5from the supply node Vdd.

The transistors T3and T5of the circuits270and272are operating in source follower configuration.

Discharged capacitors are applied at each clock cycle on the REFP node (often close to the supply voltage). When REFP drops, the gate to source voltage (Vgs) of transistor T3is reduced accordingly. The current flowing in the source-drain path of transistor T3is then less than the current Iref (sunk by current source252). Therefore, the gate voltage of transistor T4rapidly decreases, resulting in a high current through this transistor, recharging the capacitors connected to the REFP node.

Charged capacitors are applied at each clock cycle to the REFN node (often close to ground). When the REFN suddenly increases, the Vgs voltage of transistor T5is reduced accordingly. The current flowing in the source-drain path of transistor T5is then less than the current Iref (sourced by current source254). Therefore, the gate voltage of transistor T6increases rapidly, resulting in a high current through this transistor, discharging the capacitors connected to the REFN node.

An advantage of using the circuits270and272in the output stage of the amplifier217is to lower the output impedance of the amplifier circuit217. The use of flip voltage follower circuits270and272in the output stage is also superior to the use of a conventional MS transistor-based voltage follower circuit because the sourcing and sinking current at the output nodes is not limited by the current sources.

The bias control voltage VC applied at the connected base terminals of transistors Q11and Q12is output from a differential amplifier280, for example comprising an operational amplifier (OP-AMP). A first input of the differential amplifier280receives a common mode reference voltage VCM. This voltage VCM may be generated by a suitable generator circuit at a voltage level half-way between Vdd and ground. A second input of the differential amplifier280receives a feedback voltage VFB generated by a resistive divider circuit282formed by a first feedback resistor RFBN and second feedback resistor RFBP connected in series with each other at a tap node. The first feedback resistor RFBN is coupled, preferably connected, between the inverting output of amplifier217(where the negative differential output reference voltage REFN is generated) and the tap node. The second feedback resistor RFBP is coupled, preferably connected, between the non-inverting output of amplifier217(where the positive differential output reference voltage REFP is generated) and the tap node. The bias control voltage VC is generated at a level which causes the output voltages Vout+ and Vout− as applied to the output stage flip voltage follower circuits270,272to generate the differential output voltages REFP and REFN at levels where their median voltage equals the common mode voltage level.

The main drawback of using bipolar transistors for the differential pair220of input transistors Q5, Q6in circuit220is their base current Ib. It will be noted that the mirrored current flowing through each of the transistors QA, QB, QC and QD has three components: the PTAT current Iptat across R1, the CTAT current Ictat across R2(wherein IREF=Iptat+Ictat), and the base current Ib flowing into the bases of the pair of transistors220. The base current Ib is unwanted and must be addressed by compensation. The effect of this base current Ib is compensated at the differential input of the amplifier217by sinking, at each input, a compensation current Ib′ from the applied input currents IREF+Ib and IREF-Ib, wherein the compensation current Ib′ corresponds to (i.e., is equal or substantially equal within the limits of circuit tolerances to) the base current Ib.

The third mirrored current output from the collector terminal of transistor QC is composed of the constant (across process, voltage and temperature (PVT)) current IREF and an undesired current Ib corresponding to the base current Ib of the differential input transistors Q5and Q6. The current IREF+Ib is applied to (i.e., sourced to) the non-inverting (+) input of the fully differential amplifier217where the input transistor Q9(matching transistor Q5) sinks a base current Ib′ for compensation. The current flowing through the first feedback resistor R3(coupled, preferably connected, between the non-inverting input of the fully differential amplifier217and the inverting output of the fully differential amplifier217) is the current IREF=(IREF+Ib)−Ib′, where Ib′ is equal or substantially equal to Ib.

Likewise, the fourth mirrored current output from the collector terminal of transistor QD is composed of the constant (across process, voltage and temperature (PVT)) current IREF and an undesired current Ib corresponding to the base current Ib of the differential input transistors Q5and Q6. The current IREF+Ib is mirrored by the mirror216to generate the current IREF-Ib which is applied to (i.e., sunk from) the inverting (−) input of the fully differential amplifier217where the input transistor Q10(matching transistor Q6) sinks a base current Ib′ for compensation. The current flowing through the second feedback resistor R3(coupled, preferably connected, between the inverting input of the fully differential amplifier217and the non-inverting output of the fully differential amplifier217) is the current IREF=(IREF−Ib)+Ib′, where Ib′ is equal or substantially equal to Ib. Note here that because mirror circuit219uses bipolar transistors QE and QF, a base current Ib is sunk by each transistor QE and QF so that the output current of the mirror is (IREF+Ib)−(2*Ib)=IREF-Ib. In this configuration, the bipolar transistors QE and QF of the mirror circuit219are designed to match differential input transistors Q5and Q6and differential input transistors Q9and Q10.

AlthoughFIG.3Adoes not show the use of a virtual ground and the resistor Rshift, it will be understood that the bandgap circuit ofFIG.3Acould be implemented in a manner like the bandgap circuit ofFIG.2Ato include a virtual ground.

While the invention has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are considered illustrative or exemplary and not restrictive; the invention is not limited to the disclosed embodiments. Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims.