Pixel circuit and display panel

A pixel circuit including a drive transistor connected between a first power supply line and a second power supply line; a first compensation transistor having a first electrode electrically connected to a gate of the drive transistor, and a gate electrically connected to a scan line; a second compensation transistor having a first electrode electrically connected to a second electrode of the first compensation transistor, a second electrode electrically connected to a first electrode or a second electrode of the drive transistor, and a gate electrically connected to a first control line, and a third compensation transistor having a first electrode electrically connected to the second electrode of the first compensation transistor and the first electrode of the second compensation transistor, a gate electrically connected to a second control line, and a second electrode electrically connected to a first potential line.

FIELD AND BACKGROUND OF THE INVENTION

The present disclosure relates to the field of display technologies, and more particularly, to a pixel circuit and a display panel.

In the case of low-frequency driving, the duration of a frame is long, and therefore, the luminance of the pixel circuit in the duration of the frame is changed greatly, which causes a large flicker to be perceived by human eyes, and affects the display quality.

SUMMARY OF THE INVENTION

The present disclosure provides a pixel circuit and a display panel.

According to an aspect of the present disclosure, a pixel circuit is provided. The pixel circuit includes a drive transistor, a first compensation transistor, a second compensation transistor, and a third compensation transistor. The drive transistor is connected between a first power supply line and a second power supply line. A first electrode of the first compensation transistor is electrically connected to a gate of the drive transistor. A gate of the first compensation transistor is electrically connected to a scan line. A first electrode of the second compensation transistor is electrically connected to a second electrode of the first compensation transistor. A second electrode of the second compensation transistor is electrically connected to a first electrode of the drive transistor or to a second electrode of the drive transistor. A gate of the second compensation transistor is electrically connected to a first control line. A first electrode of the third compensation transistor is electrically connected to the second electrode of the first compensation transistor and the first electrode of the second compensation transistor. A gate of the third compensation transistor is electrically connected to a second control line. A second electrode of the third compensation transistor is electrically connected to a first potential line.

According to another aspect of the present disclosure, a display panel is provided. The display panel includes a pixel circuit. The pixel circuit includes a drive transistor, a first compensation transistor, a second compensation transistor, and a third compensation transistor. The drive transistor is connected between a first power supply line and a second power supply line. A first electrode of the first compensation transistor is electrically connected to a gate of the drive transistor. A gate of the first compensation transistor is electrically connected to a scan line. A first electrode of the second compensation transistor is electrically connected to a second electrode of the first compensation transistor. A second electrode of the second compensation transistor is electrically connected to a first electrode of the drive transistor or to a second electrode of the drive transistor. A gate of the second compensation transistor is electrically connected to a first control line. A first electrode of the third compensation transistor is electrically connected to the second electrode of the first compensation transistor and the first electrode of the second compensation transistor. A gate of the third compensation transistor is electrically connected to a second control line. A second electrode of the third compensation transistor is electrically connected to a first potential line. A plurality of the pixel circuits is arranged in an array. Each of the scan lines is electrically connected to two adjacent rows of the pixel circuits. Each of the first control lines is electrically connected to two adjacent rows of the pixel circuits. Each of the second control lines is electrically connected to two adjacent rows of the pixel circuits. Each of the third control lines is electrically connected to two adjacent rows of the pixel circuits. And, each of the fourth control lines is electrically connected to two adjacent rows of the pixel circuits.

DESCRIPTION OF SPECIFIC EMBODIMENTS OF THE INVENTION

In order to make the purpose, technical solutions and effects of the present disclosure clearer and more explicit, the present disclosure will be further described in detail below with reference to the accompanying drawings and by way of embodiments. It should be understood that the specific embodiments described herein are merely used to explain the present disclosure and are not intended to limit the present disclosure.

FIG.1is a schematic diagram of a structure of a pixel circuit in the related art. The pixel circuit includes a drive transistor T1, a compensation transistor T3, a first light-emitting control transistor T6, a second light-emitting control transistor T5, a first initialization transistor T7, a second initialization transistor T4, a write transistor T2, a storage capacitor Cst, and at least one of light-emitting devices D1.

One end of the storage capacitor Cst is electrically connected to a first power supply line, and another end of the storage capacitor Cst is electrically connected to a gate of the drive transistor T1.

One of a source or a drain of the second light-emitting control transistor T5is electrically connected to the first power supply line, another one of the source or the drain of the second light-emitting control transistor T5is electrically connected to one of a source or a drain of the drive transistor T1, and a gate of the second light-emitting control transistor T5is electrically connected to a light-emitting control line.

One of a source or a drain of the write transistor T2is electrically connected to another one of the source or the drain of the second light-emitting control transistor T5, another one of the source or the drain of the write transistor T2is connected to a data line, and a gate of the write transistor T2is electrically connected to a first scan line.

One of a source or a drain of the compensation transistor T3is electrically connected to another one of the source or the drain of the drive transistor T1, another one of the source or the drain of the compensation transistor T3is electrically connected to the gate of the drive transistor T1, and a gate of the compensation transistor T3is electrically connected to the first scan line.

One of a source or a drain of the first light-emitting control transistor T6is electrically connected to another one of the source or the drain of the drive transistor T1, a gate of the first light-emitting control transistor T6is electrically connected to the light-emitting control line, and another one of the source or the drain of the first light-emitting control transistor T6is electrically connected to an anode of the light-emitting device D1.

A cathode of the light-emitting device D1is electrically connected to a second power supply line.

One of a source or a drain of the first initialization transistor T7is electrically connected to the anode of the light-emitting device D1, another one of the source or the drain of the first initialization transistor T7is connected to an initialization line, and a gate of the first initialization transistor T7is electrically connected to the first scan line.

One of a source or a drain of the second initialization transistor T4is electrically connected to the gate of the drive transistor T1, another one of the source or the drain of the second initialization transistor T4is connected to the initialization line, and a gate of the second initialization transistor T4is electrically connected to a second scan line.

The data line is configured to transmit a data signal Data. The first power supply line is configured to transmit a first power supply signal VDD, and the second power supply line is configured to transmit a second power supply signal VSS. A potential of the first power supply signal VDD is greater than a potential of the second power supply signal VSS. The light-emitting control line is configured to transmit a light-emitting control signal EM (n). The initialization line is configured to transmit an initialization signal Vi. The first scan line is configured to transmit a scan signal Scan (n). The second scan line is configured to transmit a scan signal Scan (n−1).

The drive transistor T1, the compensation transistor T3, the first light-emitting control transistor T6, the second light-emitting control transistor T5, the first initialization transistor T7, the second initialization transistor T4, and the write transistor T2are all P-channel thin-film transistors and are low-temperature polysilicon thin-film transistors.

The operation of the 7TIC pixel circuit described with reference toFIG.1during a frame can be divided into the following three main operation phases as shown inFIG.2.

Reset phase M1: The scan signal Scan (n−1) is set to a low level, the second initialization transistor T4is turned on, and the gate of the drive transistor T1is reset to a potential of the initialization signal Vi.

Charging phase M2: The scan signal Scan (n) is set to a low level, the write transistor T2, the drive transistor T1, and the compensation transistor T3are all turned on, and a potential of the gate of the drive transistor T1is charged to Vdata-Vth; Meanwhile, the first initialization transistor T7is turned on, and the anode of the light-emitting device is reset to a potential of the initialization signal Vi. Here, Vdata is a potential of the data signal Data, and Vth is a threshold voltage of the drive transistor T1.

Light-emitting phase M3: The light-emitting control signal EM (n) is set to a low level, and the light-emitting device emits light.

It should be noted that in the charging phase M2, the second initialization transistor T4, the first light-emitting control transistor T5, and the second light-emitting control transistor T6are all turned off. At this time, the data signal Data charges the gate of the drive transistor T1through the path of the writing transistor T2, the drive transistor T1, and the compensation transistor T3. When the potential of the gate of the drive transistor T1is raised to Vdata-Vth, the drive transistor is turned off, and the potential of the gate thereof is no longer raised.

In the light-emitting phase M3, the light-emitting luminance of the light-emitting device is directly determined by the potential of the gate of the drive transistor T1, and the most important factor affecting the potential of the gate of the drive transistor T1is the leakage current. Since the gate of the drive transistor T1is connected to both the compensation transistor T3and the second initialization transistor T4, the current leakage characteristics of these two transistors directly affect the luminance stability during the light-emitting phase. Since the leakage current of the low-temperature polysilicon thin-film transistor (LTPS TFT) is large, the potential of the gate (i.e., the point Q) of the drive transistor T1is unstable within a duration of one frame (the two dotted lines inFIG.1indicate the corresponding leakage current path), which causes the Ids, i.e., the light-emitting current, flowing through the drive transistor T1to change, thereby causing the brightness of the screen to change within a duration of one frame.

In view of this, in order to reduce the gate leakage current of the drive transistor T1, the related art improves the compensation transistor T3and the second initialization transistor T4in the pixel circuit to the structure of double gate thin-film transistors as shown inFIG.3, mainly considering that leakage current of the double gate thin-film transistors is theoretically smaller than that of the single-gate thin-film transistor. However, in the actual manufacturing processes of display panels, it is difficult to avoid generating some parasitic capacitances. For example, a potential of the point D in the middle of the double gate thin-film transistors T3-1and T3-2and a potential of the point E in the middle of the double gate thin-film transistors T4-1and T4-2, due to the coupling effect of parasitic capacitance, will be coupled into a higher potential than the potential at the point Q when the potential of the scan signal Scan (n−1) or the scan signal Scan (n) changes from low to high (that is, during the turn-off process of the corresponding transistor). In the subsequent light-emitting process, due to the leakage current of the transistor T3-1and the transistor T4-1, the potential of the point Q is continuously increased, and the gate-source voltage difference (Vgs) corresponding to the drive transistor T1is reduced, thereby causing the light-emitting luminance of the light-emitting device D1to gradually decrease within a duration of one frame, as shown inFIG.4, where the luminance of the light-emitting device D1decreases by ΔL within a duration of one frame.

In addition, the related art employs a new LTPO (LTPS TFT+IGZO TFT) technique, in which the compensation transistor T3and the second initialization transistor T4inFIG.1are replaced with an indium gallium zinc oxide thin-film transistor (IGZO TFT) having a low leakage current, so as to solve the serious problem of flicker under low-frequency driving, such that a low-frequency driving scheme can be employed when a still frame is displayed, thereby finally achieving the purpose of reducing power consumption. However, the structures and processes of the back plate, which combines LTPS TFT and IGZO TFT together, are more complex and costlier.

In view of the above-mentioned deficiencies, the present embodiment provides a pixel circuit100. Refer toFIGS.5and6. As shown inFIG.5, the pixel circuit100includes a drive transistor T1, a first compensation transistor T3, a second compensation transistor T8, and a third compensation transistor T9. The drive transistor T1is connected between a first power supply line and a second power supply line. A first electrode of the first compensation transistor T3is electrically connected to a gate of the drive transistor T1, and a gate of the first compensation transistor T3is electrically connected to a scan line. A first electrode of the second compensation transistor T8is electrically connected to a second electrode of the first compensation transistor T3, a second electrode of the second compensation transistor T8is electrically connected to a first electrode of the drive transistor T1or to a second electrode of the drive transistor T1, and a gate of the second compensation transistor T8is electrically connected to a first control line. A first electrode of the third compensation transistor T9is electrically connected to the second electrode of the first compensation transistor T3and the first electrode of the second compensation transistor T8, a gate of the third compensation transistor T9is electrically connected to a second control line, and a second electrode of the third compensation transistor T9is electrically connected to a first potential line.

It will be appreciated that in the pixel circuit100provided in the present embodiment, the potential of the second electrode of the first compensation transistor T3and the potential of the first electrode of the second compensation transistor T8can be duly changed by the first potential line through the third compensation transistor T9such that the voltage differences between the gate of the drive transistor T1versus the second electrode of the first compensation transistor T3and the first electrode of the second compensation transistor T8are reduced, the gate leakage current of the drive transistor T1is reduced, enabling the light-emitting current flowing through the drive transistor T1to be more constant, thereby improving the uniformity of the intra-frame luminance.

Further, when the first compensation transistor T3is in the off state and the second compensation transistor T8and the third compensation transistor T9are in the on state, the first potential line can change the potentials of the first electrode and the second electrode of the drive transistor T1through the second compensation transistor T8and the third compensation transistor T9, such that the unidirectional drift range of a threshold voltage of the drive transistor T1in a single operating state is reduced, facilitating further maintaining of the stability of the light-emitting current flowing through the drive transistor T1.

It should be noted that in the present disclosure, the first electrode may be one of a source or a drain, and the second electrode may be another one of the source or the drain. For example, when the first electrode is a source, the second electrode is a drain. Alternatively, when the first electrode is a drain, the second electrode is a source.

In one embodiment thereof, the first potential line is configured to transmit the first potential signal VI3. In a duration of one frame the operation of the pixel circuit100includes writing the frame and holding the frame. A potential of the first potential signal VI3during writing the frame is lower than that during holding the frame.

It should be noted that the potential of the first potential signal VI3during writing the frame is lower than that during holding the frame, which not only facilitates lowering the gate leakage current of the drive transistor T1, but also facilitates changing a potential of point B and a potential of point A so as to reduce the unidirectional drift range of a threshold voltage of the drive transistor T1in a single operating state. The potential of point B may be linked to the potential of point A by the drive transistor T1. That is, when the potential of one of point A or point B changes, the potential of another one of point A or point B changes accordingly.

In one embodiment, the pixel circuit100further includes a first light-emitting control transistor T6, a light-emitting device D1, and a reset transistor T7. A first electrode of the first light-emitting control transistor T6is electrically connected to the second electrode of the drive transistor T1, and a gate of the first light-emitting control transistor T6is electrically connected to a third control line. An anode of the light-emitting device D1is electrically connected to a second electrode of the first light-emitting control transistor T6, and a cathode of the light-emitting device D1is electrically connected to the second power supply line. A first electrode of the reset transistor T7is electrically connected to the anode of the light-emitting device D1, a second electrode of the reset transistor T7is electrically connected to a second potential line or the first potential line, and a gate of the reset transistor T7is electrically connected to the gate of the second compensation transistor T8.

It should be noted that the gate of the reset transistor T7is electrically connected to the gate of the second compensation transistor T8, such that the gate of the reset transistor T7and the gate of the second compensation transistor T8share the same first control line, thereby reducing the number of signal lines required by the pixel circuit100, improving the density and aperture ratio of the pixel circuit100.

Further, under the control of the first control line, the reset transistor T7may be turned on multiple times at different phases of a frame to adjust or reset a potential of the anode of the light-emitting device D1multiple times, which can improve the light-emitting luminance of the light-emitting device D1and further improve the differences of intra-frame luminance.

The light-emitting device D1may be one of an organic light-emitting diode, a quantum dot light-emitting diode, a micro light-emitting diode, or a mini light-emitting diode.

In one embodiment thereof, the second potential line transmits a second potential signal VI2. A potential of the second potential signal VI2during writing a frame is lower than that during holding the frame.

It should be noted that the potential of the second potential signal VI2during writing a frame is lower than that during holding the frame, which facilitates adjusting or resetting the potential of the anode of the light-emitting device D1to further improve the differences of intra-frame luminance.

In one embodiment thereof, a channel type of the reset transistor T7is same as a channel type of the second compensation transistor T8.

It should be noted that since the gate of the reset transistor T7and the gate of the second compensation transistor T8share the same first control line, the channel type of the reset transistor T7being same as the channel type of the second compensation transistor T8allows the reset transistor T7and the second compensation transistor T8to be in a synchronous state so as to enable the reset transistor T7and the second compensation transistor T8to be synchronously turned on multiple times in different phases within a frame.

In one embodiment, the pixel circuit100further includes a second light-emitting control transistor T5, a write transistor T2, and a first initialization transistor T41. A first electrode of the second light-emitting control transistor T5is electrically connected to the first power supply line, a second electrode of the second light-emitting control transistor T5is electrically connected to the first electrode of the drive transistor T1, and a gate of the second light-emitting control transistor T5is electrically connected to the gate of the first light-emitting control transistor T6. A first electrode of the write transistor T2is electrically connected to a data line, a gate of the write transistor T2is electrically connected to the scan line, and a second electrode of the write transistor T2is electrically connected to the first electrode of the drive transistor T1or the second electrode of the drive transistor T1. A first electrode of the first initialization transistor T41is electrically connected to the gate of the drive transistor T1, a gate of the first initialization transistor T41is electrically connected to a fourth control line, and a second electrode of the first initialization transistor T41is electrically connected to one of a third potential line, the first potential line, or the second potential line.

It should be noted that the gate of the second light-emitting control transistor T5is electrically connected to the gate of the first light-emitting control transistor T6, such that it can be achieved that the gate of the second light-emitting control transistor T5and the gate of the first light-emitting control transistor T6can share the same third control line, thereby reducing the number of signal lines required by the pixel circuit100, improving of the density and aperture ratio of the pixel circuit100.

Further, the gate of the write transistor T2is electrically connected to the scan line, such that it can be achieved that the gate of the write transistor T2and the gate of the first compensation transistor T3can share the same scan line, thereby reducing the number of signal lines required by the pixel circuit100, improving the density and the aperture ratio of the pixel circuit100.

Further, when the second electrode of the first initialization transistor T41is electrically connected to the first potential line or the second potential line, the first initialization transistor T41may share the same potential line with the third compensation transistor T9or the reset transistor T7, thereby reducing the number of signal lines required by the pixel circuit100, improving the density and the aperture ratio of the pixel circuit100.

In one embodiment, the pixel circuit100further includes a second initialization transistor T42. A first electrode of the second initialization transistor T42is electrically connected to the gate of the drive transistor T1, a gate of the second initialization transistor T42is electrically connected to the gate of the first initialization transistor T41, and a second electrode of the second initialization transistor T42is electrically connected to the first electrode of the first initialization transistor T41and the first electrode of the third compensation transistor T9.

It should be noted that the second electrode of the second initialization transistor T42is electrically connected to the first electrode of the first initialization transistor T41and the first electrode of the third compensation transistor T9, the stability of a potential of a connection node between the second electrode of the second initialization transistor T42and the first electrode of the first initialization transistor T41can also be improved, and the potential difference between the connection node and the gate of the drive transistor T1can be reduced such that the gate leakage current of the drive transistor T1is decreased, thereby improving the differences of intra-frame luminance.

In one embodiment, at least two of a channel type of the drive transistor T1, a channel type of the first compensation transistor T3, a channel type of the second compensation transistor T8, a channel type of the third compensation transistor T9, a channel type of the first light-emitting control transistor T6, a channel type of the reset transistor T7, a channel type of the second light-emitting control transistor T5, a channel type of the write transistor T2, a channel type of the first initialization transistor T41, and a channel type of the second initialization transistor T42are the same.

It should be noted that the same channel type of these transistors facilitates simplified fabrication processes, structures, and costs. Here, the channel type may be a P-channel or an N-channel.

In one embodiment, at least two of the drive transistor T1, the first compensation transistor T3, the second compensation transistor T8, the third compensation transistor T9, the first light-emitting control transistor T6, the reset transistor T7, the second light-emitting control transistor T5, the write transistor T2, the first initialization transistor T41, and the second initialization transistor T42are low-temperature polysilicon thin-film transistors.

It should be noted that the channel materials of these transistors are all low-temperature polysilicon, which is advantageous not only for improving the dynamic performance of the pixel circuit100, but also for further simplifying the fabrication processes, structures and costs. Each of the above-mentioned transistors being a low-temperature polysilicon thin-film transistor may serve as a preferable solution, but is not limited thereto. At least one of the above-mentioned transistors may also be an indium gallium zinc oxide thin-film transistor.

In one embodiment thereof, the pixel circuit100further includes a storage capacitor C1. One end of the storage capacitor C1is electrically connected to the first power supply line, and another end of the storage capacitor C1is electrically connected to the gate of the drive transistor T1.

It should be noted that the first power supply line is configured to transmit a first power supply signal VDD, and the second power supply line is configured to transmit a second power supply signal VSS. A potential of the first power supply signal VDD is higher than that of the second power supply signal VSS. The data line is configured to transmit a data signal Data. The first potential line is configured to transmit a first potential signal VI3. The second potential line is configured to transmit a second potential signal VI2. The third potential line is configured to transmit a third potential signal VI1. The scan line is configured to transmit a scan signal Scan. The first control line is configured to transmit a first control signal EM2-2. The second control line is configured to transmit a second control signal EM1-2. The third control line is configured to transmit a third control signal EM1-1. The fourth control line is configured to transmit a fourth control signal EM2-1.

It should be noted that, as shown inFIG.6, when the above pixel circuit100operates at the highest refresh frequency, in a duration of one frame the operation of the pixel circuit100includes only writing the frame and does not include holding the frame; when the above pixel circuit100operates at a lower refresh frequency (lower than the highest refresh frequency), in a duration of one frame of the operation of the pixel circuit100includes writing the frame and holding the frame. The operation process in a duration of one frame of the pixel circuit100will be described below with reference to a state in which the pixel circuit100operates at the lower refresh frequency as an example.

The writing of the frame includes the following phases.

Phase P1: The third control signal EM1-1is high, and the first light-emitting control transistor T6and the second light-emitting control transistor T5are turned off. The scan signal Scan is high, and the write transistor T2and the first compensation transistor T3are turned off. The first control signal EM2-2is high, and the second compensation transistor T8and the reset transistor T7are turned off. The second control signal EM1-2is high, and the third compensation transistor T9is turned off. The fourth control signal EM2-1is low, and the first initialization transistor T41and the second initialization transistor T42are turned on. The third potential signal VI1resets the gate of the drive transistor T1or the other end of the storage capacitor C1.

Writing phase P2: the third control signal EM1-1is high, and the first light-emitting control transistor T6and the second light-emitting control transistor T5are turned off. The second control signal EM1-2is high, and the third compensation transistor T9is turned off. The fourth control signal EM2-1is high, and the first initialization transistor T41and the second initialization transistor T42are turned off. The scan signal Scan is high, and the write transistor T2and the first compensation transistor T3are turned on. The first control signal EM2-2is low, and the second compensation transistor T8and the reset transistor T7are turned on. The data signal Data is written to the gate of the drive transistor T1through the write transistor T2, the drive transistor T1, the second compensation transistor T8and the first compensation transistor T3in sequence. Meanwhile, the second potential signal VI2resets the anode of the light-emitting device D1via the reset transistor T7.

First compensation phase P3: The third control signal EM1-1is high, and the first light-emitting control transistor T6and the second light-emitting control transistor T5are turned off. The scan signal Scan is high, and the write transistor T2and the first compensation transistor T3are turned on. The fourth control signal EM2-1is high, and the first initialization transistor T41and the second initialization transistor T42are turned off. The second control signal EM1-2is low, and the third compensation transistor T9is turned on. The first control signal EM2-2is low, and the second compensation transistor T8and the reset transistor T7are turned on, such that the potential of the second electrode of the first compensation transistor T3is stabilized, a voltage difference between a potential of the gate of the drive transistor T1and the potential of the second electrode of the first compensation transistor T3is reduced to reduce the leakage current of the first compensation transistor T3, and a potential of the first electrode of the drive transistor T1and a potential of the second electrode of the drive transistor T1are reset to improve the operation state of the drive transistor T1, thereby avoiding that a threshold voltage thereof is shifted towards a positive or negative direction due to being under a same stress state for a long time.

First light-emitting phase P4: The third control signal EM1-1is low, and the first light-emitting control transistor T6and the second light-emitting control transistor T5are turned on. The drive transistor T1is turned on, and the other transistors are turned off. The light-emitting device D1emits light.

The holding of the frame includes the following phases:

Second compensation phase P5: The second compensation phase P5repeats the operations of the above first compensation phase P3such that the potential of the second electrode of the first compensation transistor T3is stabilized, the voltage difference between the potential of the gate of the drive transistor T1and the potential of the second electrode of the first compensation transistor T3is reduced, and the potential of the first electrode of the drive transistor T1and the potential of the second electrode of the drive transistor T1are reset. Meanwhile, the potential of the anode of the light-emitting device D1is reset multiple times.

Second light-emitting phase: The second light-emitting phase is between two adjacent second compensation phases P5to implement the light emission by the light-emitting device D1.

It should be noted that the potential of the first potential signal VI3may also be kept consistent during writing the frame and holding the frame, and the range thereof may be 0˜7.6V. The potential of the second potential signal VI2may also be kept consistent during writing the frame and holding the frame, and the range thereof may be 0˜−6V. A potential of the third potential signal VI1may be kept consistent during writing the frame and holding the frame, or the potential of the third potential signal VI1during writing the frame may be higher than that during holding the frame, and the range thereof may be 0˜−6V.

In one embodiment, the present embodiment provides a display panel including the pixel circuit100in at least one embodiment described above. A plurality of the pixel circuits100are arranged in an array. Each of the scan lines is electrically connected to two adjacent rows of the pixel circuits100. Each of the first control lines is electrically connected to two adjacent rows of the pixel circuits100. Each of the second control lines is electrically connected to two adjacent rows of the pixel circuits100. Each of the third control lines is electrically connected to two adjacent rows of the pixel circuits100. Each of the fourth control lines is electrically connected to two adjacent rows of the pixel circuits100.

It will be appreciated that according to the display panel provided in the present embodiment, the potential of the second electrode of the first compensating transistor T3and the potential of the first electrode of the second compensating transistor T8can be duly changed by the first potential line through the third compensating transistor T9, such that the voltage differences between the gate of the drive transistor T1versus the second electrode of the first compensating transistor T3and the first electrode of the second compensating transistor T8are reduced, the gate leakage current of the drive transistor T1is reduced, enabling the light-emitting current flowing through the drive transistor T1to be more constant, thereby improving the uniformity of the intra-frame luminance.

Further, when the first compensation transistor T3is in the off state and the second compensation transistor T8and the third compensation transistor T9are in the on state, the first potential line may change the potentials of the first electrode and the second electrode of the drive transistor T1through the second compensation transistor T8and the third compensation transistor T9, such that the unidirectional drift range of a threshold voltage of the drive transistor T1in a single operating state is reduced, facilitating further maintaining of the stability of the light-emitting current flowing through the drive transistor T1.

Further, since adjacent two rows of the pixel circuits100can share a same scan line, and the adjacent two rows of the pixel circuits100can share the same first control line, second control line, third control line, and fourth control line, the display panel can further reduce the number of signal lines required, thereby improving the pixel density and aperture ratio of the display panel.

In one embodiment, as shown inFIG.7, the display panel further includes two gate drive circuits, a first drive circuit200, a second drive circuit300, a third drive circuit400, and a fourth drive circuit500, where one of the gate drive circuits is electrically connected to an end of the scan line and another one of the gate drive circuits is electrically connected to another end of the scan line; the first drive circuit200is electrically connected to the third control line; the second drive circuit300is electrically connected to the first control line; the third drive circuit400is electrically connected to the fourth control line; the fourth drive circuit500is electrically connected to the second control line; where the two gate drive circuits are located on both sides of the plurality of the pixel circuits100, respectively, two of the first drive circuit200, the second drive circuit300, the third drive circuit400, and the fourth drive circuit500are located on an outer side of one of the gate drive circuits, and the other two of the first drive circuit200, the second drive circuit300, the third drive circuit400, and the fourth drive circuit500are located on an outer side of the other of the gate drive circuits.

It should be noted that the layout of the present embodiment not only enables the normal driving of the pixel circuit100, but also facilitates the layout design of each circuit and the narrow edge.

Each gate drive circuit includes a plurality of cascaded gate drive units, for example, a first gate drive unit and a second gate drive unit, and so on. Each scan line is electrically connected to two corresponding gate drive units to improve the drive capability of the scan signal Scan.

It will be appreciated by those of ordinary skill in the art that equivalents may be substituted or altered in accordance with the technical solution of the present disclosure and its inventive concept, and all such variations or substitutions are intended to fall within the scope of the claims appended hereto.