Method of manufacturing a magnetoresistive random access memory device and method of manufacturing a semiconductor chip including the same

In a method of manufacturing an MRAM device, first and second lower electrodes may be formed on first and second regions, respectively, of a substrate. First and second MTJ structures having different switching current densities from each other may be formed on the first and second lower electrodes, respectively. First and second upper electrodes may be formed on the first and second MTJ structures, respectively.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 USC § 119 to Korean Patent Application No. 10-2017-0065113, filed on May 26, 2017 in the Korean Intellectual Property Office (KIPO), the contents of which are herein incorporated by reference in their entirety.

BACKGROUND

1. Technical Field

Example embodiments relate to methods of manufacturing a semiconductor device and methods of manufacturing a semiconductor chip including the same. More particularly, example embodiments relate to methods of manufacturing a magnetoresistive random access memory (MRAM) device and methods of manufacturing a semiconductor chip including the same.

2. Description of Related Art

If a switching current density for changing the magnetization direction of a free layer of an MTJ is low, an MRAM device including the MTJ may have a low consumption power and a high operation speed. However, if the switching current density is high, the MRAM device may have a high data retention characteristic. It is difficult to develop an MRAM device including the low consumption power and the high operation speed, and the high data retention characteristic as well.

SUMMARY

According to example embodiments, there is provided a method of manufacturing an MRAM device. In the method, first and second lower electrodes may be formed on first and second regions, respectively, of a substrate. First and second MTJ structures having different switching current densities from each other may be formed on the first and second lower electrodes, respectively. First and second upper electrodes may be formed on the first and second MTJ structures, respectively.

According to example embodiments, there is provided a method of manufacturing an MRAM device. In the method, first and second lower electrode layers may be formed on first and second memory cell regions, respectively, of a substrate. First and second MTJ structure layers may be formed on the first and second lower electrode layers, respectively. First and second upper electrodes may be formed on the first and second MTJ structure layers, respectively. The first and second MTJ structure layers and the first and second lower electrode layers may be patterned using the first and second upper electrodes as an etching mask to form a first lower electrode, a first MTJ structure, and the first upper electrode sequentially stacked on the first memory cell region of the substrate, and a second lower electrode, a second MTJ structure, and the second upper electrode sequentially stacked on the second memory cell region of the substrate. The first and second MTJ structures may have different data retentions from each other.

According to example embodiments, there is provided a method of manufacturing a semiconductor chip. In the method, first and second lower electrodes may be formed on first and second memory cell regions, respectively, of a substrate including first and second memory block regions, a logic region, and an input/output (I/O) region. The first memory block region may include the first memory cell region and a first peripheral circuit region, and the second memory block region may include the second memory cell region and a second peripheral circuit region. First and second MTJ structures having different switching current densities from each other may be formed on the first and second lower electrodes, respectively. First and second upper electrodes may be formed on the first and second MTJ structures, respectively.

The MRAM device in accordance with example embodiments may be fabricated to have different characteristics in different regions, for example, a high data retention in one region, and a lower consumption power and a high operation speed in another region.

DESCRIPTION OF EMBODIMENTS

FIGS. 1 to 4are cross-sectional views illustrating a method of manufacturing an MRAM device in accordance with example embodiments.

Referring toFIG. 1, an insulating interlayer110may be formed on a substrate100, and first and second contact plugs122and124may be formed through the insulating interlayer110.

The substrate100may include first and second regions I and II. In example embodiments, each of the first and second regions I and II may serve as a memory cell region in which memory cells may be formed, and the first and second regions I and II may be distinguished from each other. For example, the first and second regions I and II may be spaced apart from each other.

Various types of elements, e.g., word lines, transistors, diodes, source/drain layers, contacts plugs, vias, wirings, etc., and an insulating interlayer covering the elements may be formed on the substrate100. For example, the first and second contact plugs122and124may contact wirings or source/drain layers overlying or underlying the first and second contact plugs122and124.

The insulating interlayer110may include an oxide, e.g., silicon dioxide (SiO2), or a low-k dielectric material having a dielectric constant lower than that of silicon dioxide, e.g., equal to or less than about 3.9. Thus, the insulating interlayer110may include, for example, silicon oxide, silicon oxide doped with fluorine or carbon, porous silicon oxide, spin-on-organic polymer, or inorganic polymer, e.g., hydrogen silsesquioxane (HSSQ), methyl silsesquioxane (MSSQ), etc.

In example embodiments, the first and second contact plugs122and124may be formed by a damascene process.

In an embodiment, portions of the insulating interlayer110on the first and second regions I and II may be etched to form first and second contact holes, respectively, each of which may expose an upper surface of the substrate100. A contact plug layer may be formed on the exposed upper surfaces of the substrate100, sidewalls of the first and second contact holes, and the insulating interlayer110to fill the first and second contact holes, and an upper portion of the contact plug layer may be planarized until an upper surface of the insulating interlayer110may be exposed to form the first and second contact plugs122and124. In example embodiments, each of the first and second contact plugs122and124may include a first conductive pattern and a first barrier pattern covering a bottom and a sidewall of the first conductive pattern. The first conductive pattern may include a metal, e.g., tungsten, copper, aluminum, etc., and the first barrier pattern may include a metal nitride, e.g., tantalum nitride, titanium nitride, etc.

In example embodiments, the planarization process may be performed by a chemical mechanical polishing (CMP) process and/or an etch back process.

A first lower electrode layer132may be formed on the upper surface of the insulating interlayer110and an upper surface of the first contact plug122on the first region I of the substrate100.

In an example embodiment, the first lower electrode layer132may be formed by forming a first preliminary lower electrode layer on the upper surfaces of the insulating interlayer110on the first and second regions I and II of the substrate100and upper surfaces of the first and second contact plugs122and124, and etching the first preliminary lower electrode layer using a first etching mask covering the first region I of the substrate100to remove a portion of the first preliminary lower electrode layer on the second region II of the substrate100.

For example, the first preliminary lower electrode layer may include a metal nitride, e.g., tantalum nitride, titanium nitride, tungsten nitride, etc.

Referring toFIG. 2, a second lower electrode layer134may be formed on the upper surface of the insulating interlayer110on the second region II of the substrate100and the upper surface of the second contact plug124.

In an example embodiment, the second lower electrode layer134may be formed by forming a second preliminary lower electrode layer on the upper surface of the insulating interlayer110in the second region II of the substrate100, the upper surface of the second contact plug124, and an upper surface and a sidewall of the first lower electrode layer132, and planarizing an upper portion of the second preliminary lower electrode layer until the upper surface of the first lower electrode layer132is exposed.

Alternatively, the second lower electrode layer134may be formed by forming the second preliminary lower electrode layer on the upper surface of the insulating interlayer110in the second region II of the substrate100, the upper surface of the second contact plug124, and the upper surface and the sidewall of the first lower electrode layer132, and etching the second preliminary lower electrode layer using a second etching mask covering the second region II of the substrate100to remove a portion of the second preliminary lower electrode layer in the first region I of the substrate100.

For example, the second lower electrode layer134may include a metal nitride, e.g., tantalum nitride, titanium nitride, tungsten nitride, etc. In example embodiments, the second lower electrode layer134may include a material different from that of the first lower electrode layer132. For example, the first lower electrode layer132may include titanium nitride, and the second lower electrode layer134may include tantalum nitride or tungsten nitride.

Referring toFIG. 3, a magnetic tunnel junction (MTJ) structure layer170may be formed on the first and second lower electrode layers132and134, and first and second upper electrodes182and184may be formed on the first MTJ structure layer170.

In example embodiments, the first MTJ structure layer170may include a first fixed layer structure140, a first tunnel barrier layer150, and a first free layer160stacked.

In an example embodiment, the first fixed layer structure140may include a pinning layer, a lower ferromagnetic layer, an anti-ferromagnetic coupling spacer layer, and an upper ferromagnetic layer.

In example embodiments, locations of the first fixed layer structure140and the first free layer160may be switched with each other in the first MTJ structure layer170, or at least one of the first fixed layer structure140, the first tunnel barrier layer150, and the first free layer160may be formed in plural numbers.

Each of the first fixed layer structure140and the first free layer160in the first MTJ structure layer170may have a vertical or horizontal magnetization direction, and the magnetization direction of the first fixed layer structure140may be fixed while the magnetization direction of the first free layer160may be switched by 180 degrees.

A current density required for switching the magnetization direction of a free layer of an MTJ structure may be referred to as a switching current density. A data retention of the MTJ structure may increase as a switching current density of the free layer increases, while a consumption power of the MTJ structure may decrease and an operation speed of the MTJ structure may increase as the switching current density of the free layer decreases.

In example embodiments, when the first MTJ structure layer170is deposited on the first and second lower electrode layers132and134, a switching current density or data retention of the first MTJ structure layer170may be influenced by material, crystallinity, surface roughness, stress, etc., of the underlying first and second lower electrode layers132and134. When the first and second lower electrode layers132and134having different materials are formed in the first and second regions I and II of the substrate100, portions of the first MTJ structure layer170in the respective first and second regions I and II of the substrate100may have different switching current densities or data retentions.

For example, the portion of the first MTJ structure layer170on the first lower electrode layer132including titanium nitride in the first region I of the substrate100may have a switching current density or data retention higher than that of the portion of the first MTJ structure layer170on the second lower electrode layer134including tantalum nitride or tungsten nitride in the second region II of the substrate100, and thus may have a high consumption power and a low operation speed.

Even though the first and second lower electrode layers132and134include substantially the same material, for example, when the first lower electrode layer132has an amorphous material or crystallinity matching crystallinity of the first MTJ structure layer170and the second lower electrode layer134has crystallinity different from the crystallinity of the first MTJ structure layer170, the portions of the first MTJ structure layer170on the respective first and second lower electrode layers132and134may have different characteristics. That is, the switching current densities, data retentions, consumption powers, and operation speeds of the portions of the first MTJ structure layer170in the respective first and second regions I and II may be different from each other.

The first and second upper electrodes182and184may be formed in the first and second regions I and II, respectively, of the substrate100, and may include a metal, e.g., titanium, tantalum, tungsten, etc., and/or a metal nitride, e.g., titanium nitride, tantalum nitride, etc.

Referring toFIG. 4, an etching process may be performed using the first and second upper electrodes182and184as an etching mask to pattern the first MTJ structure layer170, and the first and second lower electrode layers132and134, so that a first lower electrode136, a first MTJ structure172and the first upper electrode182may be sequentially stacked on the first contact plug122, and a second lower electrode138, a second MTJ structure174and the second upper electrode184may be sequentially stacked on the second contact plug124.

The first MTJ structure172may include a first fixed structure142, a first tunnel barrier pattern152, and a first free layer pattern162sequentially stacked, and the second MTJ structure174may include a second fixed structure144, a second tunnel barrier pattern174, and a second free layer pattern164sequentially stacked.

In example embodiments, the etching process may be performed by a physical etching process, e.g., an ion beam etching (IBE) process using, e.g., argon ions, krypton ions, etc.

In an embodiment, the first and second MTJ structures172and174in the respective first and second regions I and II of the substrate100may be influenced by the characteristics, e.g., material, crystallinity, surface roughness, stress, etc., of the underlying first and second lower electrodes136and138, and may have different characteristics, e.g., different switching current densities, data retentions, etc. In an example embodiment, the switching current density of the first MTJ structure172may be different from that of the second MTJ structure174by about 10% of the switching current density of the first MTJ structure172, and the data retention of the first MTJ structure172may be different from that of the second MTJ structure174by about 1000 times.

Accordingly, the MRAM device including the first and second MTJ structures172and174may be fabricated to have different characteristics in different regions, for example, a high data retention in one region, and a lower consumption power and a high operation speed in another region.

FIGS. 5 to 7are cross-sectional views illustrating a method of manufacturing an MRAM device.

This method may include processes substantially the same as or similar to those illustrated with reference toFIGS. 1 to 4.

Referring toFIG. 5, processes substantially the same as or similar to those illustrated with reference toFIG. 1may be performed. However, unlike the first lower electrode layer132having a single layer inFIG. 1, a third lower electrode layer232including a plurality of layers sequentially stacked may be formed in the first region I of the substrate100.

In example embodiments, the third lower electrode layer232may include a plurality of layers each including a metal, e.g., ruthenium, tantalum, etc., or a metal nitride, e.g., titanium nitride, tantalum nitride, etc. In an example embodiment, the third lower electrode layer232may include first, second, and third layers202,212, and222sequentially stacked, which may include ruthenium, tantalum, and ruthenium, respectively. Alternatively, the first, second, and third layers202,212, and222may include titanium nitride, tantalum, and titanium nitride, respectively. In some embodiments, the third lower electrode layer232may include more than 3 layers.

Referring toFIG. 6, processes substantially the same as or similar to those illustrated with reference toFIG. 2may be performed. However, instead of forming the second lower electrode layer134having a single layer, a fourth lower electrode layer234including a plurality of layers sequentially stacked may be formed in the second region II of the substrate100.

In example embodiments, the fourth lower electrode layer234may include a plurality of layers each including a metal, e.g., ruthenium, tantalum, etc., or a metal nitride, e.g., titanium nitride, tantalum nitride, etc. In an example embodiment, the fourth lower electrode layer234may include fourth, fifth, and sixth layers204,214, and224sequentially stacked. The fourth to sixth layers204,214, and224may have thicknesses equal to those of the respective first to third layers202,212, and222corresponding thereto, however, at least one of the fourth to sixth layers204,214, and224may include a material different from that of the corresponding one of the first to third layers202,212, and222. In some embodiments, the fourth lower electrode layer234may include more than 3 layers as the third lower electrode layer232.

Referring toFIG. 7, processes substantially the same as or similar to those illustrated with reference toFIGS. 3 and 4may be performed to complete the manufacture of the MRAM device.

In an embodiment, a third lower electrode236, the first MTJ structure172, and the first upper electrode182may be sequentially stacked on the first contact plug122, and a fourth lower electrode238, the second MTJ structure174, and the second upper electrode184may be sequentially stacked on the second contact plug124.

The third lower electrode236may include first, second, and third patterns206,216, and226sequentially stacked, and the fourth lower electrode238may include fourth, fifth, and sixth patterns208,218, and228sequentially stacked.

In an embodiment, the first and second MTJ structures172and174in the respective first and second regions I and II of the substrate100may be influenced by the characteristics, e.g., material, crystallinity, surface roughness, stress, etc., of the underlying respective third and fourth electrodes236and238, and may have different characteristics, e.g., different switching current densities, data retentions. Accordingly, the MRAM device including the first and second MTJ structures172and174may be fabricated to have different characteristics in different regions, for example, a high data retention in one region, and a lower consumption power and a high operation speed in another region.

FIGS. 8 and 9are cross-sectional views illustrating a method of manufacturing an MRAM device.

This method may include processes substantially the same as or similar to those illustrated with reference toFIGS. 1 to 4orFIGS. 5 to 7.

Referring toFIG. 8, the third and fourth lower electrodes236and238may be formed on the first and second contact plugs122and124, respectively.

In example embodiments, the fourth to sixth patterns208,218, and228of the fourth lower electrode238may include materials substantially the same as those of the first to third patterns206,216, and226of the third lower electrode236. However, at least one of the fourth to sixth patterns208,218, and228may have a thickness different from that of corresponding one of the first to third patterns206,216, and226.

Accordingly, even though the third and fourth lower electrodes236and238under the respective first and second MTJ structures172and174may include substantially the same material, at least one of the patterns of the third lower electrode236may have a different thickness from that of the corresponding one of the patterns of the fourth lower electrode238. Thus, the first and second MTJ structures172and174may have different characteristics, e.g., different switching current densities, data retentions, consumption powers, operation speeds, etc.

In an example embodiment, the third and fourth lower electrodes236and238may have substantially the same thickness as each other.

Referring toFIG. 9, the third and second lower electrodes236and138may be formed on the first and second contact plugs122and124, respectively.

That is, the third lower electrode236including the first to third patterns206,216, and226may be formed on the first contact plug122, and the second lower electrode138having a single layer may be formed on the second contact plug124.

The third and second lower electrodes236and138may have different materials from each other, and thus the first and second MTJ structures172and174may have different characteristics, e.g., different switching current densities, data retentions, consumption powers, operation speeds, etc.

FIGS. 10 and 11are cross-sectional views illustrating a method of manufacturing an MRAM device.

This method may include processes substantially the same as or similar to those illustrated with reference toFIGS. 1 to 4.

Referring toFIG. 10, like the processes substantially the same as or similar to those illustrated with reference toFIG. 1, the insulating interlayer110may be formed on the substrate100, and the first and second contact plugs122and124may be formed through the insulating interlayer110.

However, a fifth lower electrode layer130may be formed on the insulating interlayer110, and the first and second contact plugs122and124. That is, the fifth lower electrode layer130may be commonly formed on the first and second regions I and II of the substrate100.

Like the processes substantially the same as or similar to those illustrated with reference toFIG. 3, the first MTJ structure layer170may be formed on the fifth lower electrode layer130.

In an embodiment, a first mask300covering the first region I of the substrate100may be formed on the first MTJ structure layer170, and chemical or physical treatment may be performed on a portion of the first MTJ structure layer170in the second region II of the substrate100, so that a second MTJ structure layer175may be formed in the second region II of the substrate100, and the first MTJ structure layer170may remain in the first region I of the substrate100. The second MTJ structure layer175may include a second fixed layer structure145, a second tunnel barrier layer155, and a second free layer165sequentially stacked.

In example embodiments, the chemical treatment may include an annealing process under hydrogen atmosphere. Thus, the first and second MTJ structure layers170and175on the respective first and second regions I and II of the substrate100may have different characteristics, e.g., different switching current densities, data retentions, etc. In an example embodiment, the first MTJ structure layer170remaining in the first region I of the substrate100may have a relatively high switching current density and a relatively high data retention, while the chemically treated second MTJ structure layer175may have a relatively low consumption power and a relatively high operation speed.

In example embodiments, the physical treatment may include an ion bombardment process using argon ions, krypton ions, etc. Thus, first and second MTJ structure layers170and175in the respective first and second regions I and II of the substrate100may have different characteristics, e.g., different switching current densities, data retentions, etc. In an example embodiment, the first MTJ structure layer170remaining in the first region I of the substrate100may have a relatively high switching current density and a relatively high data retention, while the chemically treated second MTJ structure layer175may have a relatively low consumption power and a relatively high operation speed. The energy, amount of dose used in the ion bombardment process may be adjusted so that the characteristics of the second MTJ structure layer175may be controlled.

Referring toFIG. 11, after removing the first mask300, the first and second upper electrodes182and184may be formed on the first and second MTJ structure layers170and175, respectively.

Processes substantially the same as or similar to those illustrated with reference toFIG. 4may be performed to complete the manufacture of the MRAM device.

Thus, a fifth lower electrode139, the first MTJ structure172, and the first upper electrode182may be sequentially stacked on the first contact plug122, and the fifth lower electrode139, a third MTJ structure176, and the second upper electrode184may be sequentially stacked on the second contact plug124. The third MTJ structure176may include a third fixed structure146, a third tunnel barrier pattern156, and a third free layer pattern166sequentially stacked.

As illustrated above, the first and third MTJ structures172and176in the respective first and second regions I and II of the substrate100may have different characteristics, e.g., different switching current densities, data retentions, etc., by the chemical or physical treatment. Accordingly, the MRAM device including the first and third MTJ structures172and176may be fabricated to have different characteristics in different regions, for example, a high switching current density and a high data retention in one region, and a lower consumption power and a high operation speed in another region.

FIGS. 12 to 14are cross-sectional views illustrating a method of manufacturing an MRAM device.

This method may include processes substantially the same as or similar to those illustrated with reference toFIGS. 1 to 4orFIGS. 10 to 11.

Referring toFIG. 12, processes substantially the same as or similar to those illustrated with reference toFIGS. 10 and 11may be performed.

However, unlike those illustrated with reference toFIG. 10, the portion of the first MTJ structure layer170on the second region II of the substrate100may not be chemically or physically treated.

Thus, the fifth lower electrode139, the first MTJ structure172, and the first upper electrode182may be sequentially stacked on the first contact plug122, and the fifth lower electrode139, the second MTJ structure174, and the second upper electrode184may be sequentially stacked on the second contact plug124.

Referring toFIG. 13, chemical or physical treatment may be performed as the processes substantially the same as or similar to thoseFIG. 10.

In an embodiment, the chemical or physical treatment may be performed on the first MTJ structure172that may be formed by patterning the first MTJ structure layer170. A second mask310covering the second MTJ structure174in the second region II of the substrate100may be formed on the insulating interlayer110, and chemical or physical treatment may be performed on the first MTJ structure172in the first region I of the substrate100to form a fourth MTJ structure178. The fourth MTJ structure178may include a fourth fixed structure148, a fourth tunnel barrier pattern158, and a fourth free layer pattern168sequentially stacked.

As illustrated above, the fourth and second MTJ structures178and174in the respective first and second regions I and II of the substrate100may have different characteristics, e.g., different switching current densities, data retentions, etc., by the chemical or physical treatment. Accordingly, the MRAM device including the fourth and second MTJ structures178and174may be easily fabricated to have different characteristics in different regions, for example, a high switching current density and a high data retention in one region, and a lower consumption power and a high operation speed in another region.

FIGS. 15 to 35are plan views and cross-sectional views illustrating a method of manufacturing an MRAM device in accordance with example embodiments.

This method of manufacturing the MRAM device may include processes substantially the same as or similar to those illustrated with reference toFIGS. 1 to 4.

Referring toFIGS. 15 and 16, an upper portion of a substrate400may be partially etched to form a first recess407.

The substrate400may include first, second, and third regions I, II, and III. Each of the first and second regions I and II may serve as a memory cell region, and the third region III may serve as a peripheral circuit region in which peripheral circuits may be formed.

In example embodiments, the third region III may include fourth, fifth, and sixth regions IV, V, and VI. In an example embodiment, the fourth region IV may serve as a row decoder region, the fifth region V may serve as a column decoder region, and the sixth region IV may serve as a sense amplifier region.

In an example embodiment, a plurality of first regions I may be formed in a first direction substantially parallel to an upper surface of the substrate100, which may be spaced apart from each other by the fourth region IV. In an embodiment, a plurality of second regions II may be formed in the first direction, which may be spaced apart from each other by the fourth region IV.

In example embodiments, the first and second regions I and II may be spaced apart from each other by the fifth and sixth regions V and VI in a second direction substantially parallel to the upper surface of the substrate100and substantially perpendicular to the first direction.

As the first recess407is formed on the substrate400, an active region405and a field region may be defined on the substrate400. The active region405may be also referred to as an active fin.

In example embodiments, the active fin405may extend in the first direction, and a plurality of active fins405may be formed in the second direction.

Referring toFIG. 17, a third etching mask410may be formed on a portion of the substrate400, and a portion of the substrate400may be removed using the third etching mask410.

In example embodiments, a portion of the active fin405and a portion of the substrate400thereunder may be removed, and thus a second recess415may be formed on the substrate400.

Referring toFIG. 18, after removing the third etching mask410, an isolation pattern420may be formed on the substrate100to fill the second recess415and a portion of the first recess407.

The isolation pattern420may be formed by forming an isolation layer on the substrate400to fill the first and second recesses407and415, planarizing the isolation layer until an upper surface of the active fin405may be exposed, and an upper portion of the isolation layer may be removed to expose an upper sidewall of the first recess407.

As the isolation pattern420is formed on the substrate400, the active fin405may be divided into a lower active pattern405bof which a sidewall is covered by the isolation pattern420, and an upper active pattern405aprotruding from an upper surface of the isolation pattern420.

Referring toFIGS. 19 and 20, a dummy gate structure460may be formed on the substrate400.

In an embodiment, the dummy gate structure460may be formed by sequentially forming a dummy gate insulation layer, a dummy gate electrode layer, and a dummy gate mask layer on the active fin405of the substrate400and the isolation pattern420, patterning the dummy gate mask layer to form a dummy gate mask450, and sequentially etching the dummy gate electrode layer and the dummy gate insulation layer using the dummy gate mask450as an etching mask.

Thus, the dummy gate structure460may include a dummy gate insulation pattern430, a dummy gate electrode440and the dummy gate mask450sequentially stacked on the substrate100.

In example embodiments, the dummy gate structure460may extend in the second direction, and a plurality of dummy gate structures460may be formed in the first direction.

Referring toFIGS. 21 and 22, a gate spacer470may be formed on a sidewall of the dummy gate structure460.

The gate spacer470may be formed by forming a spacer layer on the active fin405of the substrate400and the isolation pattern420to cover the dummy gate structure460, and anisotropically etching the spacer layer. The gate spacer470may be formed on the sidewall of the dummy gate structure460, and a fin spacer480may be formed on a sidewall of the upper active pattern405a.

Referring toFIGS. 23 and 24, an upper portion of the active fin405adjacent the gate spacer470may be etched to form a third recess490.

In an embodiment, the upper portion of the active fin405may be removed by a dry etching process using the dummy gate structure460and the gate spacer470on the sidewall thereof as an etching mask to form the third recess490. When the third recess490is formed, the fin spacer480adjacent the active fin405may be mostly removed, however, a lower portion of the fin spacer480may remain.

A source/drain layer500may be formed in the third recess490.

In example embodiments, the source/drain layer500may be formed by a selective epitaxial growth (SEG) process using an upper surface of the active fin405exposed by the third recess490as a seed.

In example embodiments, by the SEG process, a single crystalline silicon-germanium layer may be formed to serve as the source/drain layer500. A p-type impurity source gas may be also used in the SEC process to form a single crystalline silicon-germanium layer doped with p-type impurities serving as the source/drain layer500. Thus, the source/drain layer500may serve as a source/drain region of a positive-channel metal oxide semiconductor (PMOS) transistor.

The source/drain layer500may grow not only in a vertical direction but also in a horizontal direction to fill the third recess490, and may contact a sidewall of the gate spacer470.

In example embodiments, when the active fins405disposed in the second direction are close to each other, the source/drain layers500growing on the respective active fins405may be merged with each other.

In an embodiment, the source/drain layer500serves as the source/drain region of the PMOS transistor. In an embodiment, the source/drain layer500serves as a source/drain region of a negative-channel metal oxide semiconductor (NMOS) transistor.

Thus, a single crystalline silicon carbide layer or a single crystalline silicon layer may be formed as the source/drain layer500. In the SEG process, an n-type impurity source gas may be also used to form a single crystalline silicon carbide layer doped with n-type impurities.

Referring toFIGS. 25 to 27, an insulation layer510may be formed on the substrate400to cover the dummy gate structure460, the gate spacer470, the source/drain layer500, and the fin spacer480, and may be planarized until an upper surface of the dummy gate electrode440of the dummy gate structure460may be exposed.

During the planarization process, the dummy gate mask450may be also removed, and an upper portion of the gate spacer470may be removed. A space between the merged source/drain layer500and the isolation pattern420may not be fully filled, and thus an air gap515may be formed.

The exposed dummy gate electrode440and the dummy gate insulation pattern430thereunder may be removed to form a first opening exposing an inner sidewall of the gate spacer470and an upper surface of the active fin405, and a gate structure560may be formed to fill the first opening.

The gate structure560may be formed by following processes.

A thermal oxidation process may be performed on the exposed upper surface of the active fin405by the first opening to form an interface pattern520, a gate insulation layer and a work function control layer may be sequentially formed on the interface pattern520, the isolation pattern420, the gate spacer470, and the insulation layer510, and a gate electrode layer may be formed on the work function control layer to sufficiently fill a remaining portion of the first opening.

The interface pattern520may be formed by a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process instead of the thermal oxidation process, and in this case, the interface pattern520may be formed not only on the upper surface of the active fin405but also on the upper surface of the isolation420and the inner wall of the gate spacer470.

The gate electrode layer, the work function control layer, and the gate insulation layer may be planarized until the upper surface of the insulation layer510may be exposed to form a gate insulation pattern530and a work function control pattern540sequentially stacked on the upper surface of the interface pattern520, the upper surface of the isolation pattern420, and the inner wall of the gate spacer470, and to form a gate electrode550filling the remaining portion of the first opening on the work function control pattern540. Thus, a bottom and a sidewall of the gate electrode550may be covered by the work function control pattern540.

The interface pattern520, the gate insulation pattern530, the work function control pattern540, and the gate electrode550sequentially stacked may form the gate structure560, and the gate structure560together with the source/drain layer500may form a PMOS transistor or an NMOS transistor according to the conductivity type of the source/drain layer500.

Referring toFIGS. 28 and 29, a capping layer570and a first insulating interlayer580may be sequentially formed on the insulation layer510, the gate structure560, and the gate spacer470, and a source line600may be formed through the insulation layer510, the capping layer570, and the first insulating interlayer580to contact an upper surface of the source/drain layer500in the first and second regions I and II of the substrate400.

The source line600may be formed by following processes.

A second opening may be formed through the insulation layer510, the capping layer570, and the first insulating interlayer580to expose the upper surface of the source/drain layer500in the first and second regions I and II of the substrate400, a first metal layer may be formed on the exposed upper surface of the source/drain layer500, a sidewall of the second opening, and an upper surface of the first insulating interlayer580, and thermal treatment may be performed on the first metal layer to form a first metal silicide pattern590on the source/drain layer500.

A second barrier layer may be formed on an upper surface of the first metal silicide pattern590, the sidewall of the second opening, and the upper surface of the first insulating interlayer580, a second conductive layer may be formed on the second barrier layer to fill the second opening, and the second conductive layer and the second barrier layer may be planarized until the upper surface of the first insulating interlayer580may be exposed.

Thus, the source line600including the second barrier pattern and the second conductive pattern sequentially stacked on the first metal silicide pattern590may be formed to fill the second opening.

In example embodiments, the source line600may extend in the second direction to a given length, and a plurality of source lines600may be formed in the first direction.

A second insulating interlayer610may be formed on the first insulating interlayer580and the source line600, a third opening may be formed through the insulation layer510, the capping layer570, the first insulating interlayer580, and the second insulating interlayer610to expose an upper surface of the source/drain layer500in the first to third regions I, II, and III of the substrate400, a second metal layer may be formed on the exposed upper surface of the source/drain layer500, a sidewall of the third opening, and an upper surface of the second insulating interlayer610, and thermal treatment may be performed on the second metal layer to form a second metal silicide pattern620on the source/drain layer500.

A third barrier layer may be formed on an upper surface of the second metal silicide pattern620, the sidewall of the third opening, and the upper surface of the second insulating interlayer610, a third conductive layer may be formed on the third barrier layer to fill the third opening, and the third conductive layer and the third barrier layer may be planarized until the upper surface of the second insulating interlayer610may be exposed.

Thus, a lower contact plug630including the second barrier pattern and the second conductive pattern sequentially stacked on the first metal silicide pattern620may be formed to fill the third opening.

In example embodiments, a plurality of lower contact plugs630may be formed on each of the first to third regions I, II, and III of the substrate400.

Referring toFIGS. 30 and 31, a third insulating interlayer640may be formed on the second insulating interlayer610and the lower contact plug630, and a first conductive line660extending through an upper portion of the third insulating interlayer640and a first via650extending through a lower portion of the third insulating interlayer640may be formed.

In example embodiments, the first conductive line660and the first via650may be simultaneously formed by a dual damascene process. Thus, each of the first conductive line660and the first via650may be formed to include a fourth conductive pattern and a fourth barrier pattern covering a bottom and a sidewall of the fourth conductive pattern.

Alternatively, the first conductive line660and the first via650may be independently formed by a single damascene process.

In example embodiments, the first conductive line660may extend in a direction, and a plurality of first conductive lines660may be formed to be spaced apart from each other. In example embodiments, the first via650may be formed beneath the first conductive line660to contact an upper surface of the lower contact plug630.

Referring toFIGS. 32 and 33, processes substantially the same as or similar to those illustrated with reference toFIGS. 1 to 4may be performed.

Thus, a fourth insulating interlayer710may be formed on the third insulating interlayer640and the first conductive line660, and first and second contact plugs722and724may be formed through the fourth insulating interlayer710to contact the first conductive lines660on the first and second regions I and II of the substrate400.

A first lower electrode736, a first MTJ structure772, and a first upper electrode782may be sequentially stacked on the first contact plug722, and a second lower electrode738, a second MTJ structure774, and a second upper electrode784may be sequentially stacked on the second contact plug724.

The first MTJ structure772may include a first fixed structure742, a first tunnel barrier pattern752, and a first free layer pattern762sequentially stacked, and the second MTJ structure774may include a second fixed structure744, a second tunnel barrier pattern754, and a second free layer pattern764sequentially stacked.

In an embodiment, the first and second MTJ structures772and774on the respective first and second regions I and II of the substrate400may have different characteristics, e.g., different switching current densities, data retentions, etc., due to the respective underlying first and second lower electrodes736and738. Thus, the MRAM device including the first and second MTJ structures772and774may be easily fabricated to have different characteristics in different regions, for example, a high data retention in one region, and a lower consumption power and a high operation speed in another region.

Referring toFIGS. 34 and 35, a protection layer790may be formed on the fourth insulating interlayer710to cover the first and second lower electrodes736and738, the first and second MTJ structures772and774, and the first and second upper electrodes782and784, and a fifth insulating interlayer800may be formed on the protection layer790.

A second via812and a second conductive line822extending through an upper portion of the fifth insulating interlayer800and contacting an upper surface of the first upper electrode782may be formed, and a third via814and a third conductive line824extending through an upper portion of the fifth insulating interlayer800and contacting an upper surface of the second upper electrode784may be formed.

In example embodiments, each of the second and third conductive lines822and824may extend in the second direction, and may serve as a bit line of the MRAM device.

Even though, in the drawings, the first MTJ structure772is formed between the first conductive line660and the second conductive line822, and the second MTJ structure774is formed between the first conductive line660and the third conductive line824, embodiments are not limited thereto. That is, the MRAM device may include a plurality of conductive lines disposed in a vertical direction, and the first and second MTJ structures772and774may be formed between any neighboring ones of the plurality conductive lines in the vertical direction.

FIG. 36illustrates a method of manufacturing a semiconductor chip in accordance with example embodiments.

Referring toFIG. 36, a semiconductor chip1000may include first and second memory blocks910and920, a logic device930, and an input/output (I/O) device940.

Each of the first and second memory blocks910and920may include memory cells in a memory cell region, and peripheral circuits in a peripheral circuit region. In example embodiments, each of the first and second memory blocks910and920may include an MRAM device. The first and second memory blocks910and920may be distinguished or spaced apart from each other, and may include first and second MTJ structures, respectively.

In example embodiments, the first and second MTJ structures may have different characteristics, e.g., different switching current densities, data retentions, consumption powers, operation speeds, etc., and thus the MRAM device including the first and second MTJ structures may have different characteristics in different regions. For example, the MRAM device of the first memory block910may have a relatively high switching current density and/or a relatively high data retention, and the MRAM device of the second memory block920may have a relatively low consumption power and/or a relatively high operation speed.