Repair circuit, semiconductor apparatus and semiconductor system using the same

A repair circuit may be provided. The repair circuit may include a latch array including a plurality of latch sets. The repair circuit may include a fuse array including a plurality of fuse sets, and configured to be written, in each fuse set, with repair address data and latch address data which defines a position of a latch set where the repair address data is to be stored, among the plurality of latch sets. The repair circuit may include a first decoder configured to cause data written in any one fuse set among the plurality of fuse sets to be outputted, and a second decoder configured to cause the repair address data to be stored in the latch set corresponding to the latch address data among the plurality of latch sets.

CROSS-REFERENCES TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. § 119(a) to Korean application number 10-2015-0132597, filed on Sep. 18, 2015, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety.

BACKGROUND

1. Technical Field

Various embodiments generally relate to a semiconductor circuit, and, more particularly, to a repair circuit, a semiconductor apparatus and a semiconductor system using the same.

2. Related Art

A semiconductor apparatus may use a fuse to store information of a memory cell in which a fail has occurred, among memory cells.

Recently, a repair operation may be performed even after packaging. The repair operation is performed by using an e-fuse. The e-fuse is capable of updating fuse information through a rupture operation.

Referring toFIG. 1, a repair circuit according to the conventional art has a structure in which a fuse array and a latch array are matched one to one.

When viewed in the row direction, fuses of the fuse array are referred to as fuse sets, and latches of the latch array are referred to as latch sets.

A fuse set of the fuse array and a latch set of the latch array on the same line when viewed in the row direction are matched one to one.

In the fuse array, entire fuse sets may be allocated, by the unit of a predetermined number, to respective redundancy sections including redundancy memory cells for replacing memory cells which are determined as fails.

Therefore, after a wafer test or a package test, a large number of unused fuses exist in the entire fuse array, as illustrated inFIG. 1.

As a result, in the conventional repair circuit, problems may be caused in that efficiency of the fuse array is degraded and a circuit area increases due to the fuse array.

SUMMARY

Various embodiments are directed to a repair circuit capable of reducing a circuit area and ensuring a stable repair operation, a semiconductor apparatus and a semiconductor system using the same.

In an embodiment, a repair circuit may include: a latch array including a plurality of latch sets; a fuse array including a plurality of fuse sets, and configured to be written, in each fuse set, with repair address data and latch address data which defines a position of a latch set where the repair address data is to be stored, among the plurality of latch sets; a first decoder configured to cause data written in any one fuse set among the plurality of fuse sets to be outputted, according to a counting signal; and a second decoder configured to cause the repair address data to be stored in the latch set corresponding to the latch address data among the plurality of latch sets.

In an embodiment, a semiconductor apparatus may include: a memory cell array; a latch array including a plurality of latch sets; a fuse array including a plurality of fuse sets, and configured to be written, in each fuse set, with repair address data or weak cell data and latch address data which defines a position of a latch set where the repair address data or the weak cell data is to be stored, among the plurality of latch sets; a first decoder configured to cause data written in any one fuse set among the plurality of fuse sets to be outputted, according to a counting signal; a second decoder configured to cause the repair address data or the weak cell data to be stored in the latch set corresponding to the latch address data among the plurality of latch sets; and a refresh control circuit configured to control a refresh operation for a memory cell corresponding to the weak cell data in the memory cell array.

In an embodiment, a semiconductor system may include: a plurality of stacked semiconductor chips; and a processor configured to access the plurality of stacked semiconductor chips, wherein at least one of the plurality of stacked semiconductor chips comprises a plurality of fuse sets and a plurality of latch sets, and wherein repair address data and latch address data are stored in each of the plurality of fuse sets, and the repair address data is stored in a latch set corresponding to the latch address data among the plurality of latch sets.

According to the embodiments, it is possible to reduce a circuit area and perform a stable repair operation, and unused fuses may be used in controlling a refresh operation.

DETAILED DESCRIPTION

Various embodiments may be directed to a repair circuit capable of reducing a circuit area and ensuring a stable repair operation, a semiconductor apparatus and a semiconductor system using the same.

According to the embodiments, it may be possible to reduce a circuit area and perform a stable repair operation, and unused fuses may be used in controlling a refresh operation.

Hereinafter, a repair circuit, a semiconductor apparatus and a semiconductor system using the same will be described below with reference to the accompanying drawings through various examples of embodiments.

Referring toFIG. 2, a repair circuit100in accordance with an embodiment may include a fuse array200, a latch array300, a counter400, a first decoder500, a second decoder600, and a counting controller900.

The latch array300may include a plurality of latches. The plurality of latches may be divided by the unit of latches in a row direction, that is, a latch set.

Repair address data FDATA may be stored in each latch set of the latch array300.

The fuse array200may be configured to store repair address data FDATA and latch address data KDATA which define positions where the repair address data FDATA are to be stored, among the latch sets of the latch array300.

Repair address data FDATA may be addresses of memory cells which are determined as fails in a memory cell array.

The fuse array200may include a first fuse array region210for storing repair address data FDATA and a second fuse array region220for storing latch address data KDATA.

The fuses of the fuse array200may be divided by the unit of fuses in the row direction, that is, a fuse set.

After a test process, for example, a wafer test or a package test, a row address and a column address corresponding to a memory cell determined as a fail may be detected.

The detected row address and column address may be written in fuse sets of the first fuse array region210of the fuse array200as repair address data FDATA, through a rupture process, and latch address data KDATA corresponding to the repair address data FDATA may be written in the second fuse array region220.

The counter400may be configured to increase (or decrease) the value of a counting signal OUT<0:n> according to a clock signal CLK_CTRL.

The first decoder500may be configured to select any one of the fuse sets of the fuse array200according to the counting signal OUT<0:n>.

The first decoder500may sequentially select the fuse sets of the fuse array200, starting from a most significant fuse set or a least significant fuse set, according to the counting signal OUT<0:n>.

Repair address data FDATA and latch address data KDATA may be outputted from a fuse set of the fuse array200which is selected by the first decoder500.

The second decoder600may be configured to select a latch set corresponding to a result of decoding latch address data KDATA, among the latch sets of the latch array300.

The repair address data FDATA outputted from the fuse set of the fuse array200may be stored in the latch set which is selected by the second decoder600.

The counting controller900may be configured to generate the clock signal CLK_CTRL which controls an enable period of a source clock signal CLK, according to repair address data FDATA.

As may be readily seen from the configurations described above with reference toFIG. 2, the repair circuit100in accordance with an embodiment may select a latch set where repair address data FDATA is to be stored, among all the latch sets of the latch array300, by using latch address data KDATA.

Accordingly, referring toFIG. 3, each of the fuse sets of the fuse array200may be matched with any latch set among all the latch sets of the latch array300.

Referring toFIG. 4, according to an embodiment, repair address data FDATA and latch address data KDATA may be written in a desired fuse set among the fuse sets of the fuse array200.

For example, repair address data FDATA and latch address data KDATA may be sequentially written, starting from a fuse set of a most significant turn in the row direction.

Therefore, a different kind of data other than repair address data FDATA and latch address data KDATA may be used by being written in surplus fuse sets which are not used.

For example, as a different kind of data, data related with a refresh operation may be written.

Referring toFIG. 5, the counting controller900may include first to third logic gates910to930and an edge detector940.

The first logic gate910may output a result of performing an OR logic function on repair address data FDATA.

The edge detector940may generate a boot-up end signal BOOTUPEND by detecting a falling edge of the output signal of the first logic gate910.

The second logic gate920may invert the boot-up end signal BOOTUPEND, and output a resultant signal.

The third logic gate930may output the clock signal CLK_CTRL by performing an AND logic function on the source clock signal CLK and the output signal of the second logic gate920.

Referring to the operation waveforms ofFIG. 5, at least one of signal bits of repair address data FDATA outputted from a fuse set which has been used among the fuse sets of the fuse array200has a high level.

Thus, while reading repair address data FDATA for used fuse sets, the edge detector940retains the boot-up end signal BOOTUPEND at a low level, and accordingly, the clock signal CLK_CTRL cyclically generates clock pluses.

Meanwhile, since the read operation is continuously performed and repair address data FDATA of an unused fuse set has a low level, the edge detector940generates a pulse of the boot-up end signal BOOTUPEND, and accordingly, the clock signal CLK_CTRL is retained at a low level.

Because the clock signal CLK_CTRL is retained at the low level, the counter400retains the value of the counting signal OUT<0:n> at a current state, and accordingly, the read operation for the fuse array200may be interrupted.

Referring toFIG. 6, the read operation may be performed to only a fuse set which is used among the fuse sets of the fuse array200, for corresponding repair address data FDATA and latch address data KDATA, and may be interrupted for unused fuse sets.

Hereinbelow, examples of semiconductor apparatuses in accordance with embodiments will be described with reference toFIGS. 7 and 8.

Referring toFIG. 7, a semiconductor apparatus102in accordance with an embodiment may include a memory region800, a fuse array200, a counter400, a first decoder500, and a counting controller900.

The counting controller900may be configured to generate a clock signal CLK_CTRL which controls an enable period of a source clock signal CLK, according to repair address data FDATA. The counting controller900may be configured as illustrated inFIG. 5and as discussed with relation toFIG. 5.

The memory region800may include a memory cell array700, a latch array300, and a second decoder600.

The memory cell array700may correspond to a mat as a small unit memory block or a bank or a plurality of banks as a large unit memory block.

The memory cell array700may include a plurality of normal sections NRM and a plurality of redundancy sections RED.

Each of the plurality of normal sections NRM may include normal memory cells.

Each of the plurality of redundancy sections RED may include redundancy memory cells for replacing normal memory cells in which fails have occurred.

As described above with reference toFIG. 2, the latch array300may include a plurality of latches. The plurality of latches may be divided by the unit of latches in a row direction, that is, a latch set.

The latch array300may be coupled with the plurality of redundancy sections RED.

Repair address data FDATA may be stored in each latch set of the latch array300.

The second decoder600may be configured to select a latch set corresponding to a result of decoding latch address data KDATA, among the latch sets of the latch array300.

Repair address data FDATA outputted from a fuse set of the fuse array200may be stored in the latch set which is selected by the second decoder600.

The fuse array200may basically have a structure in which fuses are arranged as illustrated inFIG. 2, and may be configured to store repair address data FDATA and latch address data KDATA which define positions where the repair address data FDATA are to be stored, among the latch sets of the latch array300.

The fuse array200may be positioned in a peripheral circuit region of the semiconductor apparatus102.

The fuse array200may include a first fuse array region210for storing repair address data FDATA and a second fuse array region220for storing latch address data KDATA.

The fuses of the fuse array200may be divided by the unit of fuses in the row direction, that is, a fuse set.

After a test process, for example, a wafer test or a package test, a row address and a column address corresponding to a memory cell determined as a fail may be detected.

The detected row address and column address may be written in fuse sets of the fuse array200as repair address data FDATA, through a rupture process.

The counter400may be configured to generate a counting signal OUT<0:n> according to the clock signal CLK_CTRL.

The clock signal CLK_CTRL may be enabled during a period in which a boot-up mode of the semiconductor apparatus102is performed.

The first decoder500may be configured to select any one of the fuse sets of the fuse array200according to the counting signal OUT<0:n>.

The first decoder500may sequentially select the fuse sets of the fuse array200, starting from a most significant fuse set or a least significant fuse set, according to the counting signal OUT<0:n>.

Repair address data FDATA and latch address data KDATA may be outputted from a fuse set of the fuse array200which is selected by the first decoder500.

Repair address data FDATA written in the fuse array200may be stored in the latch array300during the period of the boot-up mode.

In the semiconductor apparatus102, after the period of the boot-up mode expires, if an inputted external address has the same value as the repair address data FDATA, a repair operation may be performed by selecting not a memory cell of the normal sections NRM but a redundancy memory cell of the redundancy sections RED matched to a corresponding latch set of the latch array300.

A semiconductor apparatus103in accordance with an embodiment relates to the utilization of surplus fuse sets, described above with reference toFIG. 4.

Memory cells may be divided into normal cells which are determined as passes through a test (for example, a read/write test), failed cells which are determined as fails, and weak cells which are not determined as failed cells but are likely to be determined through a refresh test as failed cells according to a refresh cycle since their data retention times are relatively shorter than normal cells.

Therefore, in the semiconductor apparatus103in accordance with an embodiment, addresses of weak cells are written as weak cell data in the surplus fuse sets separately from repair address data FDATA and latch address data KDATA, in such a manner that a refresh operation may be controlled according to the weak cell data.

Referring toFIG. 8, the semiconductor apparatus103may include a memory region801, a fuse array201, a counter400, a first decoder500, a counting controller900, and a refresh control circuit1000.

The counting controller900may be configured to generate a clock signal CLK_CTRL which controls an enable period of a source clock signal CLK, according to repair address data FDATA. The counting controller900may be configured as illustrated inFIG. 5and discussed with relation toFIG. 5.

The memory region801may include a memory cell array700, a latch array301, and a second decoder601.

The memory cell array700may correspond to a mat as a small unit memory block or a bank or a plurality of banks as a large unit memory block.

The memory cell array700may include a plurality of normal sections NRM and a plurality of redundancy sections RED.

Each of the plurality of normal sections NRM may include normal memory cells.

Each of the plurality of redundancy sections RED may include redundancy memory cells for replacing normal memory cells in which fails have occurred, that is, failed cells.

The latch array301may include a repair latch array310and a refresh latch array320.

The latch array301may be coupled with the plurality of redundancy sections RED.

The repair latch array310may include a plurality of latches. The plurality of latches may be divided by the unit of latches in a row direction, that is, a latch set.

Repair address data FDATA may be stored in each latch set of the repair latch array310.

The refresh latch array320may include a plurality of latches. The plurality of latches may be divided by the unit of latches in the row direction, that is, a latch set.

Weak cell data may be stored in each latch set of the refresh latch array320.

The second decoder601may be configured to select a latch set corresponding to a result of decoding latch address data KDATA, among the latch sets of the repair latch array310and refresh latch array320.

Repair address data FDATA or weak cell data may be stored in a latch set which is selected by the second decoder601.

The fuse array201may basically have a structure in which fuses are arranged as illustrated inFIG. 2, and may be configured to store repair address data FDATA, weak cell data, and latch address data KDATA which define positions where the repair address data FDATA or the weak cell data are to be stored, among the latch sets of the latch array301.

The fuse array201may be positioned in a peripheral circuit region of the semiconductor apparatus103.

The fuse array201may include a first fuse array region211for storing repair address data FDATA and weak cell address data and a second fuse array region221for storing latch address data KDATA.

The fuses of the fuse array201may be divided by the unit of fuses in the row direction, that is, a fuse set.

After a test process, for example, a wafer test or a package test, a row address and a column address corresponding to a memory cell determined as a fail may be detected.

The detected row address and column address may be written in fuse sets of the fuse array201as repair address data FDATA, through a rupture process.

Also, addresses of weak cells detected through a refresh test may be written in partial fuse sets among surplus fuse sets excluding fuse sets used to write the repair address data FDATA, among the fuse sets of the fuse array201.

The counter400may be configured to generate a counting signal OUT<0:n> according to the clock signal CLK_CTRL.

The clock signal CLK_CTRL may be enabled during a period in which a boot-up mode of the semiconductor apparatus103is performed.

The first decoder500may be configured to select any one of the fuse sets of the fuse array201according to the counting signal OUT<0:n>.

The first decoder500may sequentially select the fuse sets of the fuse array201, starting from a most significant fuse set or a least significant fuse set, according to the counting signal OUT<0:n>.

Repair address data FDATA and latch address data KDATA or weak cell data and latch address data KDATA may be outputted from a fuse set of the fuse array201which is selected by the first decoder500.

For example, in a normal operation of the semiconductor apparatus103, repair address data FDATA and latch address data KDATA may be outputted from a fuse set of the fuse array201which is selected by the first decoder500.

Meanwhile, in the refresh operation of the semiconductor apparatus103, weak cell data and latch address data KDATA may be outputted from a fuse set of the fuse array201which is selected by the first decoder500.

The refresh control circuit1000may control the refresh operation according to the weak cell data stored in the refresh latch array320in the refresh operation.

For example, the refresh control circuit1000may perform a control task in the refresh operation in such a manner that refresh is performed a larger number of times for memory cells corresponding to the weak cell data stored in the refresh latch array320, than normal cells.

For another example, the refresh control circuit1000may perform a control task in the refresh operation in such a manner that refresh is performed with a shorter cycle for a unit memory block including memory cells corresponding to the weak cell data stored in the refresh latch array320, than other unit memory blocks.

Repair address data FDATA written in the fuse array201may be stored in the latch array301during the period of the boot-up mode.

In the semiconductor apparatus103, after the period of the boot-up mode expires, if an inputted external address has the same value as the repair address data FDATA, a repair operation may be performed by selecting not a memory cell of the normal sections NRM but a redundancy memory cell of the redundancy sections RED matched to a corresponding latch set of the latch array301.

Referring toFIG. 9, a semiconductor system104in accordance with an embodiment may include a substrate50, a stacked semiconductor memory20, and a processor10.

The semiconductor system104may be realized in the type of a system-in-package, a multi-chip package or a system-on-chip, and may be realized in the type of a package-on-package which includes a plurality of packages.

The substrate50may provide signal paths for smooth data communication between the processor10and the stacked semiconductor memory20, and may include an additional logic circuit for providing the signal paths and a logic circuit for a test.

The substrate50may be realized in various types such as of an interposer and a PCB (printed circuit board). The signal paths provided by the substrate50may include electrical coupling paths such as metal layers or through-silicon vias.

The substrate50may be electrically coupled with an external device through package balls60such as a ball grid array, bump balls and C4bumps. The external device may be a host2which operates by being coupled with the semiconductor system104.

The substrate50may be electrically coupled with the processor10and the stacked semiconductor memory20through micro bumps70.

The processor10may communicate with the host2through a system bus (not illustrated) and the substrate50, and may perform various calculation operations required by the host2.

The processor10may include at least one among a central processing unit (CPU), a graphic processing unit (GPU), a multimedia processor (MMP) and a digital signal processor (DSP).

The processor10may be realized in the types of a system-on-chip, a system-in-package and a package-on-package in which processor chips having various functions, such as application processors (AP), are combined.

The processor10may access the stacked semiconductor memory20through a memory controller11.

A physical layer (PHY)12of the memory controller11and a physical layer (PHY)31of the stacked semiconductor memory20may convert signals to be exchanged between them, in conformity with the interface between them.

While the present embodiments illustrate an example in which the memory controller11is disposed in the processor10, it is to be noted that, as the case may be, the memory controller11may be separately disposed outside the processor10.

The memory controller11may be stacked as any one chip (a base chip or a logic chip) of the stacked semiconductor memory20.

The memory controller11may be separately stacked on the substrate50by being separated from the stacked semiconductor memory20and the processor10.

The memory controller11may provide a command, an address, a clock and data to the stacked semiconductor memory20to control the stacked semiconductor memory20, and may receive data outputted from the stacked semiconductor memory20.

The physical layers12and31may be interface circuits which convert a signal transmitted from the processor10or the memory controller11into a signal appropriate to be used in the stacked semiconductor memory20and output the converted signal or which convert a signal transmitted from the stacked semiconductor memory20into a signal appropriate to be used in the processor10or the memory controller11.

The stacked semiconductor memory20may be a stacked memory device which includes a plurality of stacked chips.

The stacked semiconductor memory20may include a logic chip30and a plurality of memory chips40to42which are sequentially stacked on the logic chip30.

The logic chip30and the plurality of memory chips40to42may be electrically coupled through vias or bonding wires.

The logic chip30may relay signal and data transmission between the memory controller11and the plurality of memory chips40to42.

The logic chip30may include the physical layer31, a test circuit32, and so forth.

The physical layer31may receive a signal and data transmitted through the processor10or the memory controller11and the physical layer12, and may amplify signals and data outputted from the plurality of memory chips40to42and transmit the amplified signals and data to the physical layer12.

The test circuit32may perform tests for the plurality of memory chips40to42by being coupled with the processor10or the memory controller11, or may perform tests for the plurality of memory chips40to42by being coupled with the host2, for example, test equipment. Also, the test circuit32may independently perform a test for the stacked semiconductor memory20.

The test circuit32may include circuits which may perform tests associated with the plurality of memory chips40to42and the logic chip30at a wafer level and a package level.

The test circuit32may include various memory test-related circuits such as a built-in self test circuit, a self repair circuit and a self stress circuit.

The test circuit32may perform a couplability test of through vias or micro bumps, a boundary scan test, a burn-in stress test, a data input/output test, a data compression test, and so on.

The test circuit32may include a repair logic which replaces a failed memory cell with a redundancy memory cell.

The plurality of memory chips40to42may respectively have data storage spaces for storing data transmitted through the logic chip30from the processor10or the memory controller11.

The plurality of memory chips40to42may further include logic circuits for performing tests in link with the test circuit32of the logic chip30.

The logic chip30and the plurality of memory chips40to42may be configured by a DRAM or a NAND flash.

While it is illustrated as an example that the stacked semiconductor memory20is configured by 4 chips, that is, the logic chip30and the plurality of memory chips40to42which are sequentially stacked on the logic chip30, it is to be noted that an increased number of chips may be stacked.

Each of the chips of the stacked semiconductor memory20may be configured by a DRAM or a NAND flash.

Any one or more chips among the chips of the stacked semiconductor memory20may include the repair circuit100described above with reference toFIG. 2.

Any one or more chips among the chips of the stacked semiconductor memory20may be configured in a type such as the semiconductor apparatus102ofFIG. 7or the semiconductor apparatus103ofFIG. 8.

Meanwhile, any one chip among the chips of the stacked semiconductor memory20may include some components of the repair circuit100ofFIG. 2, and remaining chips may include remaining components excluding the some components of the repair circuit100ofFIG. 2.

For example, the logic chip30among the chips of the stacked semiconductor memory20may be configured to include components excluding the latch array300of the repair circuit100ofFIG. 2.

The fuse array200of the logic chip30may be written with repair address data FDATA, weak cell data and latch address data KDATA corresponding to all failed cells of the memory regions of the plurality of memory chips40to42.

Each of the plurality of memory chips40to42of the stacked semiconductor memory20may include the latch array300.

The latch array300of each of the plurality of memory chips40to42may be provided with repair address data FDATA, weak cell data and latch address data KDATA corresponding to it, from the fuse array200of the logic chip30through electrical coupling paths such as through-silicon vias.

While various embodiments have been described above, it will be understood to those skilled in the art that the embodiments described are examples only. Accordingly, the repair circuit, the semiconductor apparatus and the semiconductor system using the same described herein should not be limited based on the described embodiments.