Method and apparatus for processing control using a multiple redundant processor control system

A system and method for synchronizing a plurality of main processors. At a first time and in response to a first time reference, a first rendezvous signal is sent from a first to a second of the plurality of main processors. At a second time, and in response to a second time reference, a second rendezvous signal is sent from the second of the plurality of main processors, to the first of said plurality of main processors. After the first rendezvous signal is received by the second of the plurality of main processors and the second rendezvous signal is received by the first of said plurality of main processors, substantially simultaneous scanning of control information is initiated by the first and second of the plurality of main processors. In variations, a difference between the first and second times signals a fault condition.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The field of this invention related to computerized control systems for gathering sensor data from field units and triggering alarms or taking other actions based on the sensor data with respect to such control elements. More particularly this invention relates to multiple processor control units which are synchronized and evaluate sensor data for valid data.

2. Related Art

Many multiple processor control systems are available in the related art. These include systems as typified by U.S. Pat. No. 5,455,914 to Hashemi, et al. includes a multiple module processor which is controlled from a central computer station.

U.S. Pat. No. 4,616,312 to Uebel, describes a two-out-of-three selecting facility in a three-computer system for a Triple Redundant Computer System which is especially suitable for use with microprocessors having a large number of outputs. The computers of the three computer system handle the same processor information in parallel, but exchange their results in an asynchronous manner and compares them.

U.S. Pat. No. 4,627,055 to Mori, et al. describes a decentralized processing method and system having a plurality of subsystems of the same type which are connected to one another. Each subsystem has a diagnostic mean for diagnosis of failure in the other subsystems and functions to take suitable counter-measures.

U.S. Pat. No. 5,239,641 to Horst, for a method and a apparatus for synchronizing a plurality of processors. Each processor runs off its own independent clock, indicates the occurrence of a predescribed processor event on one line and receives signals on another line for initiating a processor wait state.

However, the I/O architecture of the present invention is fundamentally different from prior systems, in that the prior systems rely on intelligent I/O modules, with one microprocessor per leg per module, while the present invention relies on centralized I/O logic, with one microprocessor per leg, controlling all the I/O modules. A degree of local intelligence on each I/O module is implemented through gate array logic, acting primarily as a slave to the main processor. This architecture reduces the component cost and eliminates the significant size of such system which are usually housed in a central location. A unique synchronization system keeps the local clocks in synchronization.

The present invention provides a system which is intended to operate adjacent the equipment being controlled.

SUMMARY OF THE INVENTION

The control system of the present invention comprises a fault tolerant controller, control system platform or computer system having a triple modular redundant (TMR) architecture. The controller consist of three identical channels, except for the power modules which are dual-redundant. Each channel independently executes the application program in parallel with the other two channels. A voting system with voting mechanisms which qualify and verify all digital inputs and outputs from the field; analog inputs are subject to a mid-value selection process.

Each channel is isolated from the others, no single-point failure in any channel can pass to another. If a hardware failure occurs in one channel, the faulty channel is overridden by the other channels. Repair consists of removing and replacing the failed module in the faulty channel while the controller is online and without process interruption.

The controller of the present invention features triplicated main processor modules (MP), input/output modules (I/O) and optionally one or two Local Communications modules (LCM). Each I/O module houses the circuitry for three independent channels. Each channel on the input modules reads the process data and passes that information to its respective MP. The three MP communicate with each other using a high-speed bus called Channel11

The system is a scan based system and once per scan, the MP module synchronizes and communicate with the neighboring MPs over the Channel11. The Channel11forwards copies of all analog and digital input data to each MP, and compares output data from each MP. The MPs vote the input data, execute the application program and send outputs generated by the application program to the output modules. In addition, the controller votes the output data on the output modules as close to the field as possible to detect and compensate for any errors that could occur between the Channel11voting and the final output driven to the field. For each I/O module, the controller can support an option hot-spare module. If present, the hot-spare takes control if a fault is detected on the primary module during operation. The hot-spare position is also used for the online-hot repair of a faulty I/O module.

The MP modules each control a separate channel and operates in parallel with the other two MPs. A dedicated I/O control processor on each MP manages the data exchanged between the MP and the I/O modules. A triplicated I/O bus, located on the base plates, extends from one column of I/O modules to another column of I/O modules using I/O bus cables. In this way the system can be expanded. Each MP poles the appropriate channel of the I/O bus and the I/O bus transmits new input data to the MP on the polling channel. The input data is assembled into a table in the MP and is stored in memory for use in the voting process.

Each input table in each MP is transferred to its neighboring MP over the Channel11. After this transfer, voting takes place. The Channel11uses a programmable device with a direct memory access to synchronize, transmit, and compare data among the three MPs.

If a disagreement occurs, the signal value found in two of three tables prevails, and the third table is corrected accordingly. Each MP maintains data about necessary correction in local memory. Any disparity is flagged and used at the end of the scan by built-in fault analyzer routines to determine whether a fault exists on a particular module.

The MPs send corrected data to the application program and then executes the application program in parallel with the neighboring MP and generates a table of output values that are based on the table of input values according to user-defined rules. The I/O control processor on each MP manages the transmission of output data to the output modules by means of the I/O bus.

Using the table out output values, the I/O control processor generates smaller tables, each corresponding to an individual output module. Each small table is transmitted to the appropriate channel of the corresponding output module over the I/O bus. For example, MP A transmits the appropriate table to channel A of each output module over the I/O bus A. The transmittal of output data has priority over the routine scanning of all I/O modules.

Each MP provides a 16-megabyte DRAM for the user-written application program, sequence-of-events (SOE) tracking, and I/O data, diagnostics and communication buffers. The application program is stored in flash EPROM and loaded into DRAM for execution. The MPs receive power from redundant 24 VDC power sources. In the event of an external power failure, all critical retentive data is stored in NVRAM. A failure of one power source does not affect controller performance. If the controller loses power, the application program and all critical data are retained.

In addition, each MP can provide direct development and monitoring computer support and Modbus communication Each MP provides one (IEEE 802.3 Ethernet) Development System computer port for downloading the application program to the Trident controller and uploading diagnostic information., one Modbus RE-232/RS-485 serial port which acts as a slave while an external host computer is the master. Typically, a distributed control system (DCS) monitors and optionally updates the controller data directly through an MP.

The triplicated I/O bus is carried baseplate-to-baseplate using Interconnect Assemblies, extender modules, and I/O bus cables. The redundant logic power distribution system is carried using Interconnect Assemblies and Extender modules.

The Channel11, which is local to the MP baseplate, consists of three independent, serial links operating at 25 Mbaud. It synchronizes the MPs at the beginning of a scan. Then each MP sends its data to its upstream and downstream neighbors. The Channel11takes the following actions: transfers input, diagnostic and communication data, compares data and flags disagreements for the previous scan's output data and application program memory. A single transmitter is used to send data to both the upstream and downstream MPs. This ensures that the same data is received by the upstream processor and the downstream processor.

Field signal distribution is local to each I/O baseplate. Each I/O module transfers signals to or from the field through its associated baseplate assembly. The two I/O module slots on the baseplate tie together as one logical slot. A first position holds the active I/O module and the second position holds the hot-spare I/O module. Each field connection on the baseplate extends to both active and hot-spare I/O modules. Therefore, both the active module and the hot-spare module receive the same information from the field termination wiring.

The 2 Mbaud triplicated I/O bus transfers data between the I/O modules and the MP. The I/O bus is carried along the DIN mounting rail and can be extended to multiple DIN rails. Each channel of the I/O bus runs between one MP and the corresponding channel on the I/O module. The I/O bus extends between DIN rails using a set of three I/O bus cables.

Logic power for the module on each DIN mounting rail draws power from the power rails through redundant DC-DC power converters. Each channel is powered independently from these redundant power sources.

The controller of the present invention incorporates integral online diagnostics. These diagnostics and specialized fault monitoring circuitry are able to detect and alarm all single fault and most multiple fault conditions. The circuitry includes but is not necessarily limited to I/O loop-back, watch-dog timers, and loss-of power sensors. Using the alarm information, the user is able to tailor the response of the system to the specific fault sequence and operating priorities of the application.

Each module can activate the system integrity alarm, which consists of normally closed (NC) relay contacts on each MP Module. Any failure condition, including loss or brown-out of system power, activates the alarm to summon plant maintenance personnel.

The front panel of each module provides light-emitting-diode (LED) indicators that show the status of the module or the external systems to which it may be connected, PASS, FAULT, and ACTIVE are common indicators. Other indicators are module—specific. A common module housing structure which accepts all circuit boards for the various modules

Normal maintenance consists of replacing plug-in modules. A lighted FAULT indicator shows that the module has detected a fault and must be replaced.

All internal diagnostic and alarm status data is available for remote logging and report generation. Reporting is done through a local or remote host computer.

Additional special features include fault testing of channels through a loop-back through the base plate to ensure that the transmitting module is accurately transmitting data, and status information.

The MP modules running in parallel rendezvous each scan to vote, and run the application program. At each rendezvous the modules are time synchronized by the adjustment of their time clocks by a specific amount. Dependent on the disparity between time clocks either a positive or a negative adjustment is made to those clocks out of synchronization.

A System Executive runs the application program developed by a control engineer for a specific industrial site which is downloaded from a development PC. A System Input/Output Executive facilitates communication with the input/output modules and the System Executive. Both the System Executive and the System Input/Output Executive are resident on each MP processor modules.

Each processor module MP consists of two semi-independent designs, the processor section and the input/output section. The processor section is dedicated to the System Executive and associated firmware, the input/output section is dedicated to System Input/Output Executive and associated firmware. There are three processor modules in a system.

The three processor modules communicate with each other via an inter-processor bus called the Channel11. The Channel11is a high speed fault tolerant communication path between the processors and is used primarily used for voting data. The three processor modules are time synchronized with each other by a fault tolerant subsystem called the synchronization system. Each processor module contains two ports that can be used for interface with a development computer system or as a slave interface. Each processor module also contains one optional port for System Executive development or LAN support. The System Executive for each processor module communicates with its companion Input/Output section for that processor via a shared memory interface. Each Input/Output section communicates with at least one Input/Output module via a triplicated communications bus. Each processor module also communicates with at least one communications module via a triplicated communications bus. The communication module provides TCP/IP networking connections to the development PC and DCS hosts. The communication module also provides development and slave interface ports.

Several interconnect legs couple each of the processor modules together to form the System Controller. Each leg of the System controller is controlled by separate processor modules and each processor module operates in parallel with the other two processor modules, as a member of a triad. The input/output executive scans each input/output module via the input/output bus. As each input/output module is scanned, the new input data is transmitted by the input/output module to processor module via shared memory located on the printed circuit board supporting the processor module and the input/output module.

The processor module stores the input data into an input table in its memory for evaluation by the application program.

Prior to the application program evaluation, the input table in each processor module is compared with the input tables on the other processor modules via the Channel11. The Channel11is a three channel parallel to serial/serial to parallel communications interface with DMA controller, hardware loop-back fault detection, CRC checking and processor module to processor module electrical isolation.

The complete input data in the table for each MP/IOP module1is transferred to the other MP/IOP module1in the system and then “voted” by the System Executive firmware SX15′. After the Channel11transfer and input data voting has corrected the input values, the values are evaluated by the application program. The application program is executed in parallel on each processor module by the MPC860 microprocessor which forms the processor module. The application program generates a set of output values based upon the input values, according to the rules built in to the program by the Control Engineer. The processor section transmits the output values to the Input/Output section via a shared memory; The processor section also votes the output values via Channel11access to detect faults, i.e. non-compliant component. The input/output module separates the output data corresponding to individual Input/Output modules in the system. Output data for each input/output module is transmitted via an Input/Output bus to the Input/Output modules for application to field units.

DESCRIPTION OF THE SPECIFIC EMBODIMENT

FIG. 1is an overall block diagram of the control system which includes a Main processor1, I/O modules2, communication modules3and dual redundant power supplies4.

Overview

FIG. 2, shows a typical system configuration in more detail, which includes triple MP/IOP modules1(Sometimes referred to interchangeably as LMP/LIOP in the specification and drawings) having an MP(A)1a, an MP(B)1band an MP(C)1cassembly and may include up to six I/O assemblies of various types of I/O modules. Two I/O modules2aand2bare illustrated. Assemblies are configured into a system on a mounting base plate as shown inFIGS. 5A and 5Busing interconnect assemblies, extenders, I/O bus cables (used to join I/O columns), and I/O bus terminators, I/O modules communicate with the MPs by means of a triplicated, RS-485 bi-directions communication bus, called the I/O bus13.

As noted above the present invention comprises a fault tolerant controller31comprising a triple modular redundant (TMR) architecture. The controller includes three identical channels, Channel A,13a, Channel B,13b, and Channel C13cexcept for the power modules which are dual-redundant. Each MP, MP(A),1a, MP(B),1b, MP(C),1con the channel independently executes the application program in parallel with the other two MPs. Voting mechanisms qualify and verify all digital inputs and outputs from the field34; analog inputs are subject to a mid-value selection process.

Each channel13is isolated from the others, no single-point failure in any channel13can pass to another. If a hardware failure occurs in one channel13, the faultily channel13is overridden by the other channels. Repair consists of removing and replacing the failed module in the faulty channel while the controller is online and without process interruption.

As shown inFIG. 2, each I/O module houses the circuitry for the three independent channels13a,13b, and13ceach channel serviced by an FPGA30a,30b,30c, as shown inFIG. 3. Each FPGA30on the channels on the input modules reads the process data from the field circuitry32a,32b, and32cand passes that information to the respective MP module1.

The three MP/IOP modules1communicate with each other using a high-speed bus inter-MP bus called a channel11. The system is a scan based system and once per scan, the MP modules1synchronize and communicate with the neighboring MP modules1over the Channel11. The Channel11forwards copies of all analog and discrete input data to each MP module1. Each MP module1compares its input table data with the input table data for all other MP modules1. The MP modules1vote the input data, execute the application program and send outputs generated by the application program to the output modules2a,2band2b′. In addition, the controller31votes the output data at the FPGAs30a,30band30con the output modules as close to the field as possible to detect and compensate for any errors that could occur between the Channel11voting and the final output driven to the field34. For each I/O module2, the controller31can support an optional hot-spare module2′ as shown inFIG. 2. If present, the hot-spare takes control if a fault is detected on the primary module during operation. The hot-spare position is also used for the online-hot repair of a faulty I/O modules.

The MP modules1each control a separate channel and operate in parallel with the other two MPs. A dedicated I/O control processor IOX17′ on each MP/IOP module1as shown inFIG. 4manages the data exchanged between the MP/IOP module1and the I/O modules2. A triplicated I/O bus13, located on the base plates may be extended from one column of I/O modules2to another column of I/O modules2using I/O bus cables. In this way the system can be expanded. Each MP module1poles the appropriate channel13of the I/O bus13and the I/O bus transmits new input data to the MP module1on polling the channel. The input data is assembled into an input table in the MP module1and is stored in memory for use in the voting process.

Referring toFIG. 2, each input table in each MP module1is transferred to its neighboring MP module1over the Channel11. After this transfer, voting takes place. The Channel11uses a programmable device with a direct memory access to synchronize, transmit, and compare data among the three MP modules1a,1band1c.

If a disagreement occurs, the signal value found in two of three tables prevails, and the third table is corrected accordingly. Each MP module1maintains data about necessary corrections in local memory. Any disparity is flagged and used at the end of the scan by built-in fault analyzer routines to determine whether a fault exists on a particular module.

Each of the MP modules1sends corrected data to the application program and then executes the application program in parallel with the neighboring MP modules1. The application generates a table of output values that result from the table of input values according to user-defined rules. The I/O control processor IOP17on each MP module1manages the transmission of output data to the output modules2aby means of the I/O bus13. Using the table of output values, the I/O control processor17generates smaller tables, each corresponding to an individual output module2awhere there are multiple output modules2a. Each small table is transmitted to the appropriate channel of the corresponding output module2aover the I/O bus13. For example, MP module (A)1atransmits the appropriate table to channel A of each output module2band2b′ I/O bus(A)13a. The transmittal of output data has priority over the routine scanning of all I/O modules2.

Each MP module1provides a 16-megabyte DRAM for the user-written application program, sequence-of-events (SOE) tracking, and I/O data and data tables, diagnostics and communication buffers. The application program is stored in flash EPROM and loaded into DRAM for execution. The MP modules1receive power from redundant 24 VDC power sources. In the event of an external power failure, all critical retentive data is stored in NVRAM. A failure of one power source does not affect controller performance. If the controller loses power, the application program and all critical data are retained.

In addition each MP module1can provide direct development and monitoring computer6support (Development System) and Modbus5communications. Each MP module1provides one (IEEE 802.3 Ethernet) Development System computer port for downloading the application program to the controller and uploading diagnostic information. One Modbus RE-232/RS-485 serial port which acts as a slave while an external host computer is the master. Typically, a distributed control system (DCS) monitors and optionally updates the controller31data directly through an MP module1connection.

The triplicated I/O bus13is carried baseplate-to-baseplate using interconnect assemblies, extender modules, and I/O bus cables and the like mounted on a rail66as shown inFIGS. 5A & 5B. The redundant logic power distribution system is carried using interconnect assemblies and extender modules on the rail thus permitting expansion on the rail or to multiple rails.

The Channel11, which is local to the MP module baseplate, consists of three independent, serial links operating at 25 Mbaud. The TriBus channel is used to synchronize the MP modules1at the beginning of a scan. Then each MP module1sends its data to its upstream and downstream neighboring MP modules1. The Channel11transfers input, diagnostic and communication data, compares data and disagreements are flagged by the MP modules1for the previous scan's output data and application program memory. A single transmitter is used to send data to both the upstream and downstream MP modules1by a transmitting MP module1. This facilitates reception of the same data by the upstream processor and the downstream processor.

Field34signal distribution is local to each I/O baseplate. Each I/O module transfers signals to (in the case of an output module2) or from the field (in the case of an input module2) through its associated baseplate assembly. There are two I/O module slots on the baseplate tie together as one logical slot as shown inFIGS. 5A and 5B; a first position holds the active I/O module2aand2band the second position holds the hot-spare I/O module2a′ and2b′. Each field34connection on the baseplate extends to both active and hot-spare I/O modules2a′ and2b′. Therefore, both the active module2aand the hot-spare module2a′ receive the same information from the field34termination wiring in the case of Input and in the case of output module2band the hot spare module2b′ are sent the same information in the case of output.

The triplicated I/O bus13transfers data between the I/O modules2and the MP modules1. The I/O13bus is carried on a DIN mounting rail66, as shown inFIGS. 5A and 5Band can be extended to multiple DIN rails66. Each channel13of the I/O bus2runs between one MP module1and the corresponding channel on the I/O module2.

Logic power for the modules on each DIN mounting rail66draws power from the rails through redundant DC-DC power converters. Each channel is powered independently from these redundant power sources.

The MP/IOP module1monitors each of the three input channels13a,13band13cmeasures the input signals from each point on the baseplate asynchronously, determines the respective states of the input signals, and places the values into input tables A, B and C respectively. Each input table in each MP module1is interrogated at regular intervals over the I/O bus13by the IOP processor17located on the corresponding MP/IOP module1, for example, MP module A (1a) would interrogate Input Table A 1 over I/O Bus A (13a).

The I/O modules are specific in application or function and functionality may be expanded as required by the addition of additional functional modules. Referring toFIG. 6, the interfaces for the controller31are shown to include I/O modules2configured as a Digital Input Module2a(DI), a Digital Output module,2b(DO) an Analog Input module2c(AI) an Analog Output module2d(AO), a Relay Output module2e(RO) and a Relay Input Module2f(RI).

The Digital (Discrete) Input Module2acontains the circuitry for three identical channels13as shown inFIG. 3as13a,13band13c(A, B, and C). Although the channels reside on the same module2, they are completely isolated from each other and operate independently. Each channel13contains an application-specific integrated circuit (ASIC) which handles communication with its corresponding MP module1, and supports run-time diagnostics. Each of the three input channels measures the input signals from each point on the baseplate asynchronously, determines the respective states of the input signals, and places the values into input tables A, B and C respectively. Each input table is interrogated at regular intervals over the I/O bus by the I/O communication processor located on the corresponding MP, for example, MP A interrogates Input Table A over I/O Bus A as shown inFIG. 2. A redundant or hot spare is illustrated as26′.

Special self-test circuitry is provided to detect and alarm all stuck-at and accuracy fault conditions in less than 500 milliseconds and allows unrestricted operation under a variety of multiple fault scenarios.

The input diagnostics are specifically designed to monitor devices which hold points in one state for long periods of time. The diagnostics ensure complete fault coverage of each input circuit even if the actual state of the input points never changes.

The DO (Digital Output module) module2balso contains the circuitry for three identical, isolated channels13, Each channel and includes an ASIC which receives its output table from the I/O communication processor17on its corresponding main processor MP module1. All DO modules2buse special quad output circuitry to vote on the individual output signals just before they are applied to the load. This voter circuitry is based on parallel-series paths which pass power if the drivers for channels A and B or channels B and C, or channels A and C command them to close. In other words, 2 out of 3 drivers are voted “on”. The quad output circuitry provides multiple redundancy for all critical signal paths, guaranteeing safety and maximum availability.

A DO module executes an output voter diagnostic (OVD) routine at a predetermined time on each point. OVD detects and alarms two different types of faults. The first is “points”—all stuck-on and stuck-off points are detected in less than 500 milliseconds. The second is “switches”—all stuck on or stuck-off switches or their associated drive circuitry are detected. During OVD execution, the commanded state of each point is momentarily reversed on one of the output drivers, one after another. Loop-back on the module allows each ASIC to read the output value for the point to determine whether a latent fault exists within the output circuit. The output signal transition is less than 2 millisecond and is transparent to most field devices. OVD is designed to check outputs which typically remain in one state for long periods of time. The OVD strategy for a DO Module ensures full fault coverage of the output circuitry even if the commanded state of the points never changes.

On an AI Module2c, as shown inFIG. 6, each I/O FPGA30on channel13measures the input signals asynchronously and places the results into an input table of values. Each input table is passed to the associated MP module1using the corresponding I/O bus13. The input table in each MP module1is also transferred to its neighbors across the Channel11. A middle value is selected by each MP module1, and the input table in each other MP module1is corrected accordingly. In TMR mode, the mid-value data is used by the application program; in duplex mode, an average is used. An analog output (AO) module may also be included for analog adjustment of an analog driven parameter.

The Relay Output (RO) and Relay Input (RI) Module is a non-triplicated module for use on non-critical points which are not compatible with high-side, solid-state output switches; for example, interfacing with enunciator panels. The RO Module receives output signals from the MPs on each of three channels. The three sets of signals are then voted, and the voted data is used to drive the 32 individual relays. Each output has a loop-back circuit which verifies the operation of each relay switch independently of the presence of a load. Ongoing diagnostics test the operational status of the RO Module.

Special self-test circuitry is provided to detect and alarm all stuck-at and accuracy fault conditions in less than 500 milliseconds.

DETAILED DESCRIPTION

Each I/O module2is designed to operate directly from redundant 24 VDS power sources as shown inFIG. 14. Logic power is carried baseplate-to-baseplate, allowing a signal logic power connection per column. The power conditions circuitry is protected against over-voltage, over-temperature, and over-load conditions. Integral diagnostic circuitry checks for out-of-range voltages and over-temperature conditions. A short on a channel13disables the power regulator rather than affecting the power sources.

The controller31of the present invention incorporates integral online diagnostics. These diagnostics and specialized fault monitoring circuitry are able to detect and alarm all single fault and most multiple fault conditions. The circuitry includes but is not necessarily limited to I/O loop-back, watch-dog timers, and loss-of power sensors. Using the alarm information, the user is able to tailor the response of the system to the specific fault sequence and operating priorities of the application.

Each module can activate the system integrity alarm, which consists of normally closed (NC) relay contacts on each MP/IOP module1. Any failure condition, including loss or brown-out of system power, activates the alarm to summon plant maintenance personnel.

The front panel of each module provides light-emitting-diodes (LED)41indicators as shown onFIG. 16that show the status of the module or the external systems to which it may be connected, PASS, FAULT, and ACTIVE are common indicators. Other indicators are module—specific.

Normal maintenance consists of replacing plug-in modules. A lighted FAULT indicator shows that the module has detected a fault and must be replaced.

All internal diagnostic and alarm status data is available for remote logging and report generation. Reporting is done through a local or remote host computer.

Additional special features include fault testing of channels through a loop-back through the base plate to ensure that the transmitting module is accurately transmitting data, and status information.

The MP/IOP modules1running in parallel rendezvous each scan to vote, and run the application program. At each rendezvous the MP/IOP modules1are time synchronized by the adjustment of their time clocks by an amount required to bring them into synchronization. Dependent on the disparity between time clocks either a positive or a negative adjustment is made to those clocks out of synchronization.

Referring again toFIG. 4, the preferred main processor (MP, 15) CPU is a Motorola MPC860 operating at 50 MHz with PLL enabled. The oscillator tolerance is 25 ppm. The MP15uses the following components of the MPC860, RISC CPU, 4 Kbyte data cache, 4 Kbyte instruction cache, MMU, Memory controller, Time base used for a real time clock, Interrupt controller used for all serial and DMA channels, Channel11, and synchronization system interrupts, the PC 860, Parallel port is used for LEDs and miscellaneous I/O, Communications Processor and other communicators.

The Main Processor, MP/IOP module1comprises at least two semi-independent sections, the MP15(main processor) and the IOP17(Input/Output Processor). Also provided are a Modbus port5which is a Modicon protocol port. The system supports acting as a slave to the port5communication link. A development system port6is also provided through which the application program developed may be downloaded from a development PC or other computer and the controller31monitored. Communications between the main processor MP15sections and other main processor sections of other MP/IOP modules1takes place over the Channel11. Communication between the Input/Output, IOP sections17, with other processor IOP sections17takes place over the IOP bus14. Communications between the MPIIOP module1and communications CM module3take place over the LCB bus9.

Each MP/IOP module1is capable of operating in SINGLE, DUAL and TMR (Triple Modular Redundant) modes. Each MP/IOP module1may control up to 56 I/O base-plate assemblies (LIO modules2). The number of I/O base-plate assemblies varies based upon system options and requirements for a given industrial or other installation.

The IOP17uses the following components of the MPC860: a RISC CPU, 4 Kbyte data cache, 4 Kbyte instruction cache, Memory Management Unit, Memory controller, a Time base, use for IOX17′ real time clock, Interrupt controller used for all serial and DMA channels, Parallel port used for IOP17leg synchronization, and LEDs and miscellaneous I/O, a Communications Processor, BDM Port, SCC1used for remote/expansion IOP bus, SCC2used for the LIO bus, SCC3used for upstream IOP communications, SCC4used for downstream IOP17communications, SCM2used for very low level hardware and IOX17′ debug & development. The IOP17clock is derived from the MP1550 MHz clock.

As shown inFIG. 4the MP15is dedicated to SX15′ (the system executive) and associated firmware, the IOP17is dedicated to IOX17′ (the input output executive) and associated firmware. Each MP15section also includes one optional 802.3 port10for SX15′ development or LAN support. Each MP15communicates with its associated IOP17via a shared memory interface18to memory unit16.

The primary function of SX15′ is to provide an execution environment for a application program developed by a Control Engineer for a particular industrial control system. To provide this environment, the SX15′ is engaged in performing the following steps as shown inFIGS. 8A and 8B:

1. Receiving Inputs from the IOP17, step301;

2. Voting Inputs for the application program, step302;

5. Sending outputs to the IOP17, step305;

6. Sending Configuration Information to the IOP17, step306;

7. Processing messages from Communications Modules LCM, step307;

8. Verifying the integrity of the hardware, step308;

10. Return for more inputs, step310.

The SX15′ firmware executes the application program generated by the user and down loaded from a development PC35or other computer system as shown inFIG. 10A. The application program uses Digital and Analog IOP Inputs and sends outputs to the input/output and communication boards. SX15′ controls timing and synchronization between the three MPs15, voting of input data and system data, detection and analysis of I/O faults and internal faults, and communication with the development system35and a diagnostic port.

The SX15′ runs in parallel on each of the three Main Processors1a,1band1ccontrols timing and synchronization between the three MP modules15and the voting of input data and system data. These Processors are kept in real time synchronization by a combination of the time specific hardware and software functions. SX15′ uses real time synchronization to rendezvous all of the Main Processors at a maximum scan rate. The scan rate is selectable by the user within the range of 10 ms to 450 ms. Once the rendezvous occurs, each SX15′ transfers information tables between the three Main Processors. SX15′ then determines what functions need to be done during the scan. These include updating memory, running an application program, and the like.

Referring again toFIG. 2andFIG. 4, the IOX17′ firmware executes on a separate 50 MHz MPC860 CPU, located on the MP/IOP module1. There are three identical copies of IOX17firmware, on each MP/IOP module1. These copies are referred to as legs A, B and C based on the MP15they are running on. Each leg or channel (between MPs) has an upstream leg and a downstream leg, referred to as US and DS. The following table defines the Upstream, US, and Downstream, DS, mapping functions. The relationship is illustrated inFIG. 11showing upstream and downstream paths. Where u=upstream, d=downstream, m=me, T=TTS pulse, L=Loop-back capture, C=Capture.

As shown inFIG. 10A, the typical minimum system of the present invention includes three MP/IOP modules;1a,1band1c. At least one of these modules,1a, may be connected to a application program development computer35over a development connection6to the system executive, SX15′. This connection permits a download of the application program developed on the development system35to at least one of the three processors1a,1b,1cwhich loads the program to the other two. Additionally, an interface over the Modbus5for each of the processors permits distributed processor control system (DCS) and human machine interface (HMI) communications over RS232/RS485 bus ports,5band5c. Each of the processors communicates over an LIO bus13on independent interconnection lines13a,13band13cas shown inFIGS. 10A and 10B. Each of the LIO bus connections interfaces with the LIO modules2aand2b, shown by way of example, each of which have triplicated FPGAs30a,30b, and30cover bus13a,13band13c. Each FPGA is coupled to the field circuitry32a,32band32crespectively which receives field inputs34for the particular control system being monitored. The I/O modules may as noted above be configured for particular services, such as DI, DO, AI, AO, RO, RI and the like.

With reference toFIG. 10B, an alternate configuration of the triplicated main processors1a,1band1cis shown utilizing dual communication modules3aand3bwhich provide the Modbus and Development serial links, but in addition provide external communication links for external communications. In this configuration the Modbus5and Development6ports on the MP/IOP modules1a,1b, and1care disabled. Each of the LCM modules3aand3bcommunicates with each of the respective MP/IOP modules1over communication lines9a,9band9cwhich are coupled to the communication bus (LCB) of each of the main processors.FIG. 10Balso shows additional LIO modules2cand2dattached to the LIO bus to illustrate that multiple LIO modules2may be connected on the same LIO bus13.

While the system of the present invention is shown as triplicated MP/IOP modules1, multiple LIO modules2and optionally one or more LCM modules3, other configurations are possible to provide more or less, redundancy. As shown inFIG. 12, the LCM module3provides two 802.3 TCP/IP networking connections24(for peer to peer linking) and25(for development system35or DCS hosts linking). The LCM also provides RS232/RS485 ports26,27, and28for supplemental bus and development system linking. The LCM is based on a Motorola MPC860T and MC68360 which is used as a communications co-processor.

The system may also run with only one each of the various modules or combinations of multiple MP/IOP modules1, LCM modules3or LIO modules2. The System Executive, SX15′ of each MP/IOP modules1is responsible for executing the application program downloaded from the Development PC35. The System Input/Output Executive, IOX17′, communicates with the FPGAs30of theLIO modules2and the SX15′. Both SX15′ and IOX17′ are resident on the MP/IOP module in the MP15section and the IOP17section respectively. The LIO modules convert physical inputs and outputs to communication messages.

The MP15memory16includes an FPGA77as shown in block diagram form inFIGS. 9A and 9Bwhich contains the following MP/IOP functions: Channel11management, synchronization system management, the MP watchdog, the MP Hard reset management, the IOP watchdog, the IOP Hard reset management, Expansion flash prom decode routine, Modbus/LCM channel MUX, Fault LED control, and Mode LED control. As shown inFIGS. 9A and 9B, the major block descriptions of the FPGA77software is as follows:Rx—channel,80VHDL module containing: Rx—recvr, Rx—pllh, Rx—crc and Rx—ctrl. This module is used twice, once for the upstream channel and once for the downstream channel.Rx—recvr,80aDual 5 bit de-serializer, dual5b4bdecoder, symbol decoder and byte strobe generation. Operates from the received clock.Rx—pllh,80bByte synchronization digital phase lock loop. Syntheses byte strobes from the received byte strobe. Operates from the MPC860 50 Mhz clock divided by 4.Rx—crc,80cCalculates and checks the received CRCs, based upon a nibble polynomial lookup table for CRC32. Operates from the MPC860 50 Mhz clock divided by 4.Rx—ctrl,80dReceive state machine. Decodes and sequences received bytes and request writes to the RX FIFO. Detects and handles receive channel errors. Operates from the MPC860 50 Mhz clock divided by 4.Tx—channel,81VHDL module containing: Tx—xmitr, Tx—crc and Tx—ctrlTx—xmitr,81aDual4b5bencoder, symbol encoder, dual 5 bit transmit shift register and byte strobe generator. Detects and handles Transmit channel errors. Operates from the MPC860 50 Mhz clock divided by 4.Tx—crc.,81bCalculates and sends the transmit CRCs. Based upon a nibble polynomial lookup table for standard CRC32. Operates from the MPC860 50 Mhz clock divided by 4.Tx—ctrl,81cReceive state machine. Generates packet symbol sequences, header, header to data pad and data field sequence. Requests and reads bytes from the TX FIFO. Operates from the MPC860 50 Mhz clock divided by 4.Rx—fifo, 82 Contains 4-32 by 8 dual port SRAMs organized as two 16 by 32 FIFOs. Also contains the receive channel byte to 32 bit word steering MUX.Tx—fifo, 83 Transmit channel FIFO, contains 4-32 by 8 dual port SRAMs organized as one 16 by 32 FIFO and 1 by 32 bit word used for diagnostic CRC word storage. 15 by 32 locations spare.Tb—dma,84DMA bus controller and channel arbiter. Handles requests from the Transmit and receive channels for FIFO bus read and writes. Controls the MPC860 side on the Rx—fifo, Tx—fifo and all DMA address pointers (Tb—addr). Communicates via signal pins with the external Bus PAL for DMA transfers. Operates from the MPC860 50 Mhz clock divided by 2.Tb—addr, 85 All DMA pointers: Transmit buffer descriptor page register TXBDP, Transmit buffer descriptor index pointer TXBDI, Upstream buffer descriptor page register UPBDP, Upstream buffer descriptor index pointer UPBDI, Downstream buffer descriptor page register DNBDP, Downstream buffer descriptor index pointer DNBDI, MPC860 Address bus MUX and peripheral bus read back MUX.Tb—regs,86Holds the Miscellaneous control register, Transmit channel control register, Upstream and downstream control, Channel11interrupts and the peripheral bus interface.Tt,87synchronization system. Contains entire synchronization system functionality described hereafter plus 2 32 by 8 dual port SRAMs used for capture registers. Interfaces to and peripheral bus through Tb—regs. Operates from the MPC860 50 Mhz clock divided by 2.tb—misc,88Contains LED controls, expansion flash prom decode, MP15reset, IOP17reset, MP15watchdog timer and IOP17watchdog timer. Operates from the 16 mhz-baud clock.tb—a4,89FPGA77, also contains clock buffers, parity generator and I/O buffers

FIGS. 11A and 11Bshows the interconnection of the main processor modules MP/IoP module1.FIGS. 11A and 11Billustrates an upstream MP90(U) transmitting a pulse90f(T) over path90a(ud) to the downstream processor92(D) where it is captured by downstream processor92at its downstream capture register92j(dC); over path90bto its upstream loop back capture register90e(uL); along path90c(mu) where it is captured by the My processor91(M) capture register91h(uC) and over path90dto its downstream loop back capture register90g(dL).

Similarly, the My processor91(M) is shown transmitting a pulse91f(T) over path91(um) a to the upstream processor90(U) where it is captured by downstream processor90at its downstream capture register90j(dC); over path91bto its upstream loop back capture register91e(uL); along path91c(md) to the downstream processor92(D) to capture register92h(uC) and over path91dto its downstream loop back capture register 91 g (dL).

The downstream MP92(D) is shown transmitting a pulse92f(T) over path92a(dm) to the next downstream processor91(M) where it is captured by downstream processor91at its downstream capture register91j(dC); over path92bto its upstream loop back capture register92c(uL); along path92c(du) to the upstream processor90(U) to capture register90h(uC) and over path92dto its downstream loop back capture register92g(dL).

The IOP17which contains the IOX17′ provides the following serial communications interfaces: an LIO Bus, a Diagnostic Channel, an RS232 Debug port, a BDM port, a 802.3. 10BaseT Ethernet expansion IOP17bus, RS485 expansion IOP17bus, an I2C channel for communications with the Temperature sensor.

Each IOX17′ implements the complete logic for one of the three legs (A, B or C). It communicates with the other IOX17′ legs through two mechanisms: a synchronization signal and data messages through a serial, HDLC diagnostic bus.

The IOX17′ internal execution architecture is based on deterministic, fixed duration “I/O scans”. The IOX17′ design allows for any predefined scan duration, but is set to use a 1 millisecond scan time. During each I/O scan, execution proceeds in two modes: foreground and background.

The foreground mode is implemented as an interrupt service routine, which takes up most of the I/O scan durations. An internal MPC860 timer interrupt is used to switch the CPU to foreground mode. This I/O scan interrupt is synchronized by software with upstream and downstream IOX sections17′, ensuring that foreground execution on all three legs starts within a maximum of 2 psec of each other.

Following these tasks, the CPU reverts to the background mode, which implements the synchronizing IOX17′ system time with the SX15′ system time informing SX15′ that IOX17′ is still operational processing control messages that SX15′ may have placed in the shared memory, and processing input from, and output to, the debug port.

A diagnostic channel provides a communications link between the IOP legs. The MP15and IOP's section17leg addresses are read through MPC860 parallel port pins.

The MP15and IOP17node addresses are read through MPC860 parallel port pins. Both the MP15and IOP17are connected to the same base-plate address plugs.

Each redundant leg or channel13of the system is mechanically and electrically isolated from adjacent legs in an acceptable mechanical isolation, which is defined as at least equivalent to the trace-to-trace spacing required to achieve 800 VDC electrical isolation. Other isolation techniques such as opt-isolation at all leg-to-leg interfaces may be used as an alternative provided the preferred VDC is achieved.

In the event of an MP/IOP module1failure, the triad, via software control, is dissolved dynamically and the remaining two re-configured into a dual-master configuration. A hot replacement MP/IOP module1is dynamically “re-educated” by transferring re-education data including application program and data over the Channel11on insertion.

Enclosure and Mounting

Referring toFIG. 13, the MP/IOP modules1, LIO2modules, LCM3modules are each housed in a separate configurable enclosure or housing29, which receives the circuit boards which comprise the different modules. The same form of housing29may be used for each module by simply changing the face plate information for the particular module. The cover20and the base21of the housing29are shown inFIG. 13. Both the cover20and the base21are provided with a thermal conductive pad or medium36which is electrically non-conductive. A suitable medium36used for this purpose is a GAP PAD™ 1500 which is a conformable thermally conductive material for filling air gaps. The GAP PAD™ 1500 medium36used in this invention is obtainable from the Bergquist Company at 5300 Edina Industrial Boulevard, Minneapolis, N.Mex. 55439 and the Bergquist Company has been granted patents on such materials as is shown in U.S. Pat. No. 5,679,457 which is incorporated herein by reference.

The thermally conductive medium36is applied to the inner surfaces of the housing29, which preferably includes at least the two major surfaces. As illustrated, four surfaces are covered. Where increased thermal conductivity is desired all or any portion of the internal surfaces may be covered by medium36. Each functionally specific module uses the same general circuit board for providing redundant power. The character or the functionality of the particular module is determined by the module board for the various modules, as previously described, that is the electronic circuit board which implements the MP/IOP module1, LCM module3or the various types of LIO modules2.FIG. 14andFIG. 15show the block diagram for the power board4and the MP/IOP module1for example.

Referring again toFIG. 13, the molded cover20of the housing29includes a planar cover mounting surface38for receiving the thermal conductive medium36, and a face plate39mounted generally at right angles to the mounting surface38. The face plate39is provided with a series of LED conduits40that may be filled with fiber optic tubes or plastic inserts, or other light transmissive medium or a cover for permitting light from LED's41which are mounted on the module circuit boards54to pass from the circuit board to the surface of the faceplate39for viewing. While holes may be left open in the cover20face plate39, dust and debris from the industrial environment may contaminate the circuitry. Accordingly, these conduits are preferably filled to seal the housing29. The extruded cover20of the housing29has a plurality of thermal dissipating fins61on an outer surface38a. The face plate39also has a hole74afor receiving a jack screw50.

The base21of the housing29includes a planar base mounting surface43and a base44which has a plurality of connector holes45and grounding pin holes46for electrical connectors to a base plate49. The grounding pins47aand47bare elongated as shown inFIG. 16so that when the housing29is mounted to the base plate49, the grounding pins47engage prior to engagement of the electrical connectors48. This permits the housing29to be grounded before the power is applied to the module through engagement with the connectors48. The base21further includes opposing sides59aand59bwhich enclose the housing29when the same is assembled with the cover20. The base is also provided with thermal dissipating base fins60mounted on the outer surface43aof the base mounting surface43. In addition, grounding pin placement only permits one-way insertion.

To allow the MP/IOP module1hardware to fit into the system packaging, the MP/IOP module1design is separated into two printed circuit board assemblies as shown inFIG. 16. These are the functionality board51for the particular module being implemented and the power interface board56which are mounted in the system package in the form of a sandwich. A 50 pin connector connects the two PCBs at one end.

As shown inFIG. 16, the power board56and the functionality board57are each sized to fit into the housing29and are connected in the form of a circuit board sandwich37with all of the inter board connectors94at one end. Also shown in the schematic of the circuit board sandwich37the data signals54are input and output at one end and visual signals55generated by LED's41or any other source of light are output at the at the other. The power board56and the functionality board57are electrically connected at the end near the front of the housing29and all of the electrical connections are disposed at the rear of the housing29and are externally accessible. The board sandwich37may be mounted inside the housing in any conventional manner provided that heat generated by the circuit boards is transmitted out of the housing. The thermally conductive medium should therefore be in contact with the circuit board and the inner surfaces of the housing. As shown inFIG. 13, the base21includes mounting pads71for fastening the power circuit board56inside the housing which are disposed in the center at the four corners of the planar mounting surface. Only three of the mounting pads71are visible. It should be noted that other thermal control mechanisms such as coolant tubes and the like may also be used for heat dissipation within the housing29.

As shown inFIG. 17, the cover20face plate39is also provided with a flexible Mylar cover42which is retained in opposing slots58aand58bon the front of the base and are used to identify the type of module (i.e. its function). In this respect, the conduits40are made to accommodate all of the positions for the LED's41for all configurations of LED's for each type of module. The Mylar cover42covers those conduits40not used for the particular functionality intended.

The major elements of the control system include field replaceable modules housed in the protective metal housing50. These modules include a Main Processor Module (MP15), I/O Modules including a Digital Input Module (DI), a Digital Output Module (DO) a Relay Output Module (DI), an Analog Input Module (AI) an Analog Output Module and Extender Module (EM) and such other modules as may be necessary or appropriate.

Each of these modules is fully enclosed to ensure that no components or circuits are exposed even when the module is removed from the baseplate. Offset baseplate connectors make it impossible to plug a module in to the baseplate connectors in the incorrect position. In addition, keys on each module prevent the insertion of modules into the incorrect slots.

FIGS. 18A,18B,18C,18D and18F shows typical MYLAR cover42for the face plate for the housing29for each of the various modules with indicia for functions identification and openings95aligned with the LEDs41of the specific functionality board and with opaque areas covering unused channels40. The specific indicators used for the MP/IOP module1are shown in the following Table III, although other indicators may be used as required. Many of these same indicators may be used in other modules.

TABLE IIIMP/IOP indicatorsFront PanelIndicatorsStatusPowerControl-FunctionLED IndicatorColorup stateled ByModulePassGreenOffNot FaultStatusFaultRedOnMP | IOPActiveGreenOffMPModeRun ModeGreenOnMPRemote ModeGreenOnMPProgram ModeYellowOnMPStop ModeYellowOnMPAlarmsField PowerRedOnMPSystem PowerRedOnMPSystem AlarmRedOnMPProgram AlarmBlueOnMPOver TemperatureRedOffMPLockRedOn/OffMPCommuni-TX/RX ReservedGreen/GreenOffHwcationsStatusTX/RX IO busGreen/GreenOffHwTX/RX COMM BusGreen/GreenOffHwTX/RX ModbusGreen/GreenOffHwLINK/TX/RXGreen/Green/OffHwDevelopmentGreenNetworkHw = Hardware circuit.Note 1MP or IOP, not both, under firmware control.The module status indicators display the operational status on the MP/IOP 1 module. IOP 17 status is passed to the MP 15 via the shared memory interface.Pass - Indicates that both MP 15 and IOP 17 sections have passes all diagnostics. PASS is the inverse of FAULT, and can be read on both MPC860s PA8. PASS is active low. No user action required.Fault - Indicates a fault was detected on the MP 15 or IOP 17 sections. The user is expect to replace the module. The fault is forced ON by a MP/IOP module 1 “hard” reset, or MP 15 or IOP 17 watchdog timer time-out or the FAULT port bit PA11 on the MP or IOP MPC860. The FAULT bit is active high. The FAULT bit is pulled up via a 10 k resistor, so that it defaults to the faulted state. Note: If the fault is detected in a non critical portion on the MP, such as the Debug port or Flash prom, or the MP has re-educated too many times due to transient faults, it is permitted for the MP 15 to continue running is the Fault - Active state. See SX fault handling.Active - Indicates the MP 15 is running the application program. The MP 15 flashes Active LED once for each application program scan executed. SX firmware shall control the ON duty cycle to ensure the LED is visible, even for very fast application programs. The ACTIVE LED is driven from MPC860 port bit PA10, active high.Mode indicatorsRun Mode - Indicates the System of the present invention is in “Run” mode. Run is driven from the Channel 11/synchronization system FPGA 77, see MCR register. The led defaults to ON during hardware reset.Remote Mode - Indicates the System of the present invention is in “Remote” mode. Remote is driven from the Channel 11/synchronization system FPGA 77. The led defaults to ON during hardware reset.Program Mode - Indicates the System of the present invention is in “Program”mode. Program is driven from the Channel 11/synchronization system FPGA 77. The led defaults to ON during hardware reset.Stop Mode - Indicates the System of the present invention is in “Stop” mode. Stop is driven from the Channel 11/synchronization system FPGA 77. The led defaults to ON during hardware reset.System status indicatorsField Power - Indicates that a 24 v field power input on one or more I/O module is missing. If the field power alarm is on, the system alarm is illuminated by SX 17'. Development or Trilog must be queried by the user to determine the actual module(s) reporting the alarm condition. FP—ALRM is active high on PB29.System Power - Indicates that there is a 24 V logic power input missing on one or more MP, I/O or CM module. Development or Trilog must be queried by the user to determine the actual module(s) reporting the alarm condition. If the logic power alarm is on, the system alarm is illuminated by SX 17'. SP—ALRM is active high on PB28.System Alarm - Indicates that a fault or error condition is present in the System of the present invention. Development or Trilog must be queried by the user to determine the actual module(S) reporting the alarm condition. System alarm is driven by the MP port bit PA9. System alarm is driven by the MP port bit PA9. System alarm is active high and pulled up.Program Alarm - Is driven by the application program to indicate an alarm condition detected by the application program, typically bypassed points. Program alarm is driven by the MP 15 port bit PDS. System alarm is active high ans pulled up.Over Temp. - Indicates an MPC860 junction over temperature. Over temp is driven directly from the temperature monitor IC. SX 17' programs the trip temperature via the I2C channel.Lock - Indicates the module is not locked into its base-plate. The unlock status bit is readable on both MPC860's port bit PC9. Unlock is active high and pulled up.Module communications indicatorsCommunications indicators are provided to aide the user/installer in trouble shooting cable installation problems.Reserved TX/RX - Flashes when an expansion IOP 17 is communicating over the RS485 IOP bus.IO Bus TX/RX - Flashes when the IOP 17 is communicating on the LIO bus.COMM Bus TX/RX - Flashes when the MP 15 is communicating to either LCM.Modbus TX/RX - Flashes when the MP 15 is communicating on it's local RS232/RS485 Modbus port.Development Link - Indicates the MPs 15 10BaseT twisted pair receiver has established a hardware connection over RX+ and RX− signals with the Ethernet hub. Note: The hub should also contain a Link LED to indicate a hardware connection has been established with the PMs TX+ and TX− twisted pair signals.Development TX/RX - Flashes when MP 15 is communicating on it's 802.3 10BaseT Development network. Flashes when the MP 15 is communicating on it's 802.3 TriLan port or when the LRXM or expansion IOP is communication over it's 802.3 fiber optic port.The table IV below lists the conditions represented by the top indicators on the DI front panel, FIG. 18B, and provides a description and a recommended action for each condition. An X represents a neutral indicator.

TABLE IVTop Indicator ConditionsPassFaultActiveLockDescriptionActionOnOffOnOffModule is operating normally.No action is required.OnOffOffOffPossible conditions:Application program has not beenIf module is the hot spare,loaded into the MP.no action is required.Application program has beenIf module is active, replaceloaded into the MP, but has notmodule.been started up.Module has just been installed andis currently running start-updiagnostics.The other module is active.OffOnXOffPossible conditions:Module may have failed.See mode indicator statusfor power-up states.Module may be in the process ofIf module's PASS indicatorpower-up self-test.does not go on within fiveminutes, replace module.Module has detected a fault.Module is operational, butshould be replacedXXXOnModule is unlocked from theLock module.baseplate.OnOnXXIndicators/signal circuitry on theReplace module.module are malfunctioning

The following table V lists the conditions that can be represented by the Field Power indicator.

TABLE VField Power Indicator ConditionsFieldPowerDescriptionActionOnField power from oneTo isolate the missing poweror more of thesource, use the Developmentredundant sourcesSystem computer Diagnostic Panel.is missing.Correct the problem in thefield circuit. If these stepsdo not solve the problem,replace module.OffField power isNo action is required.operating normally.

The following table VI lists the possible conditions that can be represented by a point indicator.

TABLE VI32 Point Indicator ConditionsPoint (1–32)DescriptionOnField circuit is energized.OffField circuit is not energized.

The table VII below lists the conditions represented by the top indicators on the DO front panel (seeFIG. 18C) and provides a description and a recommended action for each condition. An X represents a neutral indicator.

TABLE VIIDO Front PanelPassFaultActiveLockDescriptionActionONOffOnOffModule is operating normally.No action is required.OnOffOffOffPossible conditions:Application program has not beenIf module is the hot spare,loaded into the MP.no action is required.Application program has beenIf module is active, replaceloaded into the MP, but has notmodule.been started up.Module has just been installed andis currently running start-updiagnostics.The other module is active.OffOnXOffPossible conditions:Module may have failed.See mode indicator statusfor power-up states.Module may be in the process ofIf module's PASS indicatorpower-up self-test.does not go on within fiveminutes, replace module.Module has detected a fault.Module is operational, butshould be replacedXXXOnModule is unlocked from theLock module.baseplate.OnOnXXIndicators/signal circuitry on theReplace module.module are malfunctioning

The following table VIII lists the conditions that can be represented by the Power/Load indicator.

TABLE VIIIPower/Load Indicator. ConditionsFieldPowerDescriptionActionOnFor at least one point,To isolate the suspectedthe commanded state andpoint, use the Developmentthe measured state doSystem computer Diagnosticnot agree.Panel. To determine theoutput point's commandedstate, use the DevelopmentSystem computer ControlPanel. To determine theoutput's actual state, usea Voltmeter, then correctthe problem in the externalcircuit. If these steps donot solve the problem,replace module.OffAll load connections areNo action is required.functioning properly.

The following table IX lists the possible conditions that can be represented by a point indicator.

TABLE IX16 Point Indicator ConditionsPoint (1–16)DescriptionOnField circuit is energized.OffField circuit is not energized.

The table X below lists the conditions represented by the top indicators on the AI front panel (seeFIG. 18D) and provides a description and a recommended action for each condition. An X represents a neutral indicator.

TABLE XAI Top Indicator ConditionsPassFaultActiveLockDescriptionActionOnOffOnOffModule is operating normally.No action is required.OnOffOffOffPossible conditions:Application program has not beenIf module is the hot spare,loaded into the MP.no action is required.Application program has beenIf module is active, replaceloaded into the MP, but has notmodule.been started up.Module has just been installed andis currently running start-updiagnostics.The other module is active.OffOnXOffPossible conditions:Module may have failed.See mode indicator statusfor power-up states.Module may be in the process ofIf module's PASS indicatorpower-up self-test.does not go on within fiveminutes, replace module.Module has detected a fault.Module is operational, butshould be replacedXXXOnModule is unlocked from theLock module.baseplate.OnOnXXIndicators/signal circuitry on theReplace module.module are malfunctioning

The following table XI lists the conditions that can be represented by the Field Power indicator.

TABLE XIField Power Indicator ConditionsFieldPowerDescriptionActionOnField power from one orTo isolate the missing powermore of the redundantsource, use the Developmentsources is missing.System computer DiagnosticPanel. To determine the output'sactual state, use a Voltmeter,then correct the problem inthe external circuit. If thesesteps do not solve the problem,replace moduleOffField power isNo action is required.operating normally.

The table XII below lists the conditions represented by the top indicators on the Relay Output RO front panel (see Figure E) and provides a description and a recommended action for each condition. An X represents a neutral indicator.

TABLE XIIPassFaultActiveLockDescriptionActionOnOffOnOffModule is operating normally.No action is required.OnOffOffOffPossible conditions:Application program has not beenIf module is the hot spare,loaded into the MP.no action is required.Application program has beenIf module is active, replaceloaded into the MP, but has notmodule.been started up.Module has just been installed andis currently running start-updiagnostics.The other module is active.OffOnXOffPossible conditions:Module may have failed.See mode indicator statusfor power-up states.Module may be in the process ofIf module's PASS indicatorpower-up self-test.does not go on within fiveminutes, replace module.Module has detected a fault.Module is operational, butshould be replacedXXXOnModule is unlocked from theLock module.baseplate.OnOnXXIndicators/signal circuitry on theReplace module.module are malfunctioning

The following table XIII lists the possible conditions that can be represented by a point indicator.

TABLE XIIIPoint (1–32)DescriptionOnField circuit is energized.OffField circuit is not energized.

Indicators for other input/output modules are similarly configured as necessary.

FIG. 17shows the manner in which the cover20interconnects with the base. The cover20includes a cover interlock67which mates with a corresponding base21interlock68. The cover and the base21are then screwed together after insertion of the circuit board sandwich7shown inFIG. 16and the thermal conductive material inside the housing utilizing screws73in cover screw holes69aand69band base screw holes70aand70bas shown inFIG. 13. Although any fastening method may be used.

Alignment of the housing29on insertion can be difficult. Accordingly the single jack screw50as shown inFIG. 13is utilized which has a screw thread51at one end for engaging the base plate49for mounting. The single jack screw50is centered in the housing29and is mounted through the jack screw hole74. The use of a single jack screw50seats the module upon entry and unseats the module on exit, that is, on engagement and disengagement from the connectors. A snap ring52is attached to one end of the jack screw50and engages an annular recess62on the jack screw50to hold the jack screw50in position within the housing at the base44, a handle53holds the jack screw in place at the face plate39. This permits the jack screw50to pull the module out of its connectors on unscrewing the jack screw50which remains mounted to the housing29. The handle53of the jack screw50pulls the housing29into its seat on screwing in of the jack screw50. This configuration allows ease of insertion and removal of the housing29, and provides a safety factor in that the housing29is first grounded on mounting prior to power being applied.

The jack screw50has an LED detector notch63therein which allows the beam from a detector LED, which may be mounted on either circuit board in the housing, but preferably on the power board56, such that the light beam from the LED is to be intercepted when the jack screw50is fully seated. If the jack screw50is not filly seated, the LED beam is interrupted and the system determines that the module is not fully or properly seated.

When “removed status” is detected, the SX15′ evaluates the application program and if the retentive data is invalid, re-education (reload) from another MP15with a valid application program occurs. If no other MP15has a valid application program, the SX15′ waits in the Stop mode for a new application program to be loaded, the MP15is commanded to the Program Run or Remote state, and commanded to download and run.

The “Module Lock Detector” indicates the MP/IOP module is seated and locked into its base-plate65aas shown inFIGS. 5A and 5B. This status is readable by both MPC860s and reflected in the module status message. The Lock detector is implemented using a reflective type opto-interrupter now shown which detects the position of the slot on the jack screw50. The locked state is indicated by the opto-interrupter in the ON (low-conducting) state, i.e. the opto-interrupter signal is blocked by the jack screw50. The opto-interrupter is diagnosable under firmware control which allows at least 1 ms for the opto-interrupter to change state. The UNLOCK led is forced off in hardware by a lock detector diagnostic bit.

Hot-insertion of the MP/IOP1or any other modules into the base-plate is provided using the detectable keyed insertion jack screw50to insure proper installation orientation and correct module type.

Each housing29is mounted on a base-plate65as discussed before as shown inFIGS. 5A and 5B. Each base plate65may support more than one module. The base plates65are mounted to rails66and multiple base plates65may be mounted in a single system.FIGS. 5A and 5Bshow mounting for both a minimum system and a large system.

FIGS. 19A and 19Billustrate the mounting of the baseplate for the main processor module MP/IOP module1showing its baseplate65amounted to the rail and its interconnections.FIGS. 20A and 20Billustrate the mounting of the Digital In module showing its baseplate65bmounted to the rail and its interconnections.FIGS. 21A and 21Billustrate the mounting for the Digital Out module showing its baseplate65cmounted to the rail and its interconnections.FIGS. 22A and 22Billustrate the mounting for the Analog In showing its baseplate65dmounted to the rail and its interconnections.FIGS. 23A and 23Billustrate the mounting for the Relay module showing its baseplate65emounted to the rail and its interconnections.

Rail64mounted base-plate assemblies permit stacking of several modules as shown inFIGS. 5A and 5B. Each module is housed in a unique housing29as described above which provides extended make-first/break-last safety and signal ground pins47. Also, a safety ground connection to the rail is supplied by the base-plate assembly.

Redundant 24 VDC power supplies are provided to provide a back up in the case of power supply failure. In the preferred embodiment, the MP/IOP1is based on the Motorola QUICC microprocessor, the MPC860, as noted above, and includes support for at least 32 M bytes of application memory (DRAM). Error detection via parity, background diagnostic, and voting, correction via leg re-education are also provided as is hereinafter described.

The base-plate contains 3 address plugs (one multi-part address plug connector), one per leg, Base-plate Address plugs are visible with modules and cables installed. The Node address is set via the Address plugs on the MP/IOP base-plate. MP/LIOC address plugs are readable by both MP15and IOP17CPUs. The same Address plugs are used by the expansion IOP17to define the “String number” to support multiple IOP s+I/O module strings from a TMR MP/LIOC.

Synchronization System Synchronized Timing Adjustment

A synchronization system subsystem (TMR Time) is the basis for MP15scan synchronization and rendezvous. The subsystem consists of integrated hardware and firmware components, which allows the MPs15to be loosely coupled in hardware, i.e. run independent of scan, and still maintain very tight leg-to-leg synchronization, i.e., from scan to scan +/−50 us. Tight synchronization is required to minimize the amount of time that the MP/IOP modules1wait to synchronize a Channel11rendezvous. Leg-to-leg (channel to channel) isolation is designed to protection against ground shorts or neighboring legs at 36 volts without causing permanent damage or effecting the operation of the leg.

Each MP/IOP module1rendezvous using synchronization system based upon each MPs15own internal time base, not a common external event or clock synchronization system is used to implement Channel11Synchronization Rendezvous, Leg time synchronization

With reference toFIG. 24registers are used for time synchronization in an FPGA77. A 24 bit Timer register96counts 1μ ticks based the MPC860 50 MHz 25 ppm clock51. The SX15′ may read the Timer register96at any time to obtain relative time. The SX15′ uses relative time of the midpoint processor to determine when to perform its next Channel11rendezvous for voting based on a programmed delta time parameter. For MP-to-MP time synchronization, a Time compare register98generates a synchronization pulse which is applied to the up and downstream MP15sections through amplifiers54and55respectively when the Timer register96matches the Time register97in the FPGA. The SX15′ calculates and loads the Time register97. Four capture registers, two registers99and100for upstream and downstream captured the timer register, and two registers103and104for attenuated loop-back capture are readable by SX15′. The capture registers capture the value of the Timer register when a synchronization pulse is received. The SX15′ uses the delta between the capture registers and its own time to make small adjustments to its Timer register96time base and to detect faults.

The synchronization system hardware is optimized to minimize the real time (instantaneous) work required by SX15′. Synchronization system servicing does not require MPC860 interrupts. Synchronization system is implemented in a FPGA77which is accessible by the SX15′.

An adjustment trim register99is provide to compensate for time base crystal oscillator drift. The adjustment trim register99adjusts the time base by dropping or adding 40 Ns to the time base clock, 1 us clock every M us based on adjustment counter63, where M is programmable from 40.96 us to 0.66666496 seconds in 40.96 us increments.

The synchronization system architecture is scaleable to include at least one additional register not shown, to provide for a Hot spared MP/IOP module1

The synchronization system time synchronization accuracy is selected to minimize Channel11rendezvous window to provide synchronization resolution required for 1 ms sequence of events timing, and to provide time base fault detection and isolation between MP-15legs.

The synchronization system does not drift more that +/−50 us over a 1 second period. To provide a 10× margin, the minimum synchronization system accuracy is +/−50 us/10 s or +/−5 ppm. The synchronization system timer base is accurate to +/−25 ppm (drift+/−25 us per second), therefore the SX15′ trims (adjust) this time base105to provide the required accuracy between MPs15.

The synchronization system and the SX15′ synchronizes the MP15to an accuracy of +/−50 us. This sets the normal Channel11rendezvous window to 100 us. The time base105is derived from the MP15MPC860 50 Mhz 25 ppm crystal oscillator, divided by 4 for time base adjustments, and divided by 12.5 (12 then 13 then 12 . . . ) for the Timer register97. Given an accuracy of +/−50 us, the time resolution of the synchronization system timer and capture registers is approximately an order of magnitude better, or: +/−5 u. Assuming the longest System scan is 500 ms, the timer should roll twice per scan so that SX can detect register roll-over and maintain the high order timer bits in system memory, therefor the timer must not roll twice per scan. 500 ms/1 us<219or 19 bits. In addition, to permit the timer to be diagnosed, the timer should roll over at least once per 10 minutes (diagnose time requirement). 600 s/1 us>229or 29 bits. A timer length of 24 bits satisfies both requirements and minimizes FPGA77hardware. Roll over occurs every 16.77721594 seconds. Capture registers and Time registers are 24 bits and the timer roll flag sets when the timer rolls over to zero.

Referring toFIG. 24the synchronization system FPGA77includes all of the synchronization system registers which are memory mapped and includes a method illustrated inFIG. 25for adjustment of each MP's synchronization system timer time base. This is important since the MP15time synchronization pulses may arrive at any time relative to an MP's timer's value. The timer FPGA77method generates a pulse when the Timer register96matches the Time register97. The capture registers latch the contents of the Timer (double synchronized to the time base clock/2 and latched on the next microsecond) on the rising edge of each synchronization pulse. The Synchronization pulses are at least 3 us wide to allow the MP-MPC860 time to poll for the presence of the pulses during power up diagnostics and SX15′ startup.

Referring toFIG. 25, the operation of the time synchronization is shown by way of example. Processor A initiates a synchronization pulse108, processor B initiates a synchronization pulse109ten microseconds from the leading edge of the A pulse108. Processor C initiates a synchronization pulse110twenty microseconds from the leading edge of the B109pulse. Assuming, the clocks of each processor are running at a different count, e.g. A at 500, B at 100, C at 1000, the each processor would synchronize the clocks as follows:

MY (A) captures its clock111aat 500 on generation of its synchronization pulse. On receipt of the downstream MY (B) synchronization pulse, MY (A) captures its clock111cat 510 On receipt of the upstream MY (C) synchronization pulse, MY (A) captures its clock111bat 530.

On receipt of the upstream MY (A) synchronization pulse, MY (B) captures its clock112bat 90. MY (B) captures its clock112aat 100 on generation of its synchronization pulse. On receipt of the downstream MY (C) synchronization pulse, MY (B) captures its clock at112cat 120

On receipt of the upstream MY (B) synchronization pulse, MY (C) captures its clock113bat 970. MY (C) captures its clock113aat 1000 on generation of its synchronization pulse. On receipt of the downstream MY (A) synchronization pulse, MY (C) captures its clock113cat 970.

By examining the capture times each processor determines which processor was midpoint. That is in between the pulses of the other processors. Accordingly, (A) picks a count of 510 which adds 10 us to its clock and (C) picks a count of 980 which subtracts 20 us from its clock thereby synchronizing the processors.

The synchronization system Timer register96includes STOP and CLEAR controls. SX15′ polls for synchronization pulses from the other MP modules1(if any) before generating an external synchronization pulse (T). Alternatively, the SX15′ may clear and stop the Timer register96and wait for a synchronization pulse. On receipt of the synchronization pulse, the SX15′ uses the adjust registers to acquire synchronization. The following steps occur in each scan time sequence.

t0, step6011) SX15′ reads the synchronization system capture registers and loop-back status.2) SX15′ checks for roll over and increment, the high order time bits kept in memory.3) SX15′ selects an MP leg (mid-point) to be used for trim calculations.4) SX calculates a real time value for the next synchronization pulse and load time into synchronization system Time register.

t1–t3, step602The synchronization system capture registers99,100,101,102,103and104capture the synchronization system timer register96value to the nearest 1 us when an external synchronization pulse is received. Previous values are over-written.

t2, step603synchronization system generates a synchronization pulse when the Timer register96matches the Timer97.

Note: t0–t4are arbitrary time markers use to illustrate the synchronization system sequence.

The FPGA77contains and decodes the following registers set forth in Table XV.

The T register (Time register) determines when the synchronization system Synchronization Pulse output signal (TTS is generated. The TTS pulse is generated for 3 us when the T register=T counter evaluates true.

The T counter (Timer register) counts 1 us time base clocks. The T counter is free running. The Roll bit indicates when the T counter has rolled past the 24 bit Capture and Time register boundary and the software of the MP15accounts for this when capturing time.

Referring again toFIG. 24and Table XV, the upstream attenuated loop-back capture register99latches the value of the T counter96when the Upstream attenuated loop-back detects a output synchronization pulse (TTS). The T counter Roll and Stop bits are also captured. This register detects faults in the “MY to Upstream” Synchronization pulse driver and backplane pins. The upstream loop-back capture register99is unknown until the first TTS pulse is detected. Roll and Stop indicate the state of the ROLL and stop flags when the capture occurred. TT—COF (capture overflow) indicates that TT—INT was already set when the capture occurred. The TT—COF bit will not clear until the TT—NT bit is cleared and the next TSO capture occurs.

A Downstream attenuated loop-back capture register100latches the value of the T counter96when the Downstream attenuated loop-back detects a output synchronization pulse (TTS). The T counter87Roll and Stop bits are also captured. This register detects faults in the “MY to Downstream” Synchronization pulse driver and backplane pins.

This Downstream Loop-back register100is unknown until the first TTS pulse is detected. Roll and stop indicate the state of the ROLL and stop flags when the capture occurred. TT—COF (capture overflow) indicates that TT—INT was already set when the capture occurred. The TT—COF bit will not clear until the TT—INT bit is cleared and the next TSO capture occurs.

An Upstream capture register103latches the value of the T counter96when the Upstream Synchronization pulse is detected. The T counter Roll and Stop bits are also captured. The Upstream Capture register103is unknown until the first Upstream Synchronization pulse (T) is detected or until the UP—LBEN (Upstream loop-back enable) bit is set in the control register and a synchronization system Synchronization Pulse (TTS) is generated. Roll and stop indicate the state of the ROLL and stop flags when the capture occurred. UP—COF (capture overflow) indicates that UP—CF was already set when the capture occurred. The UP—COF bit will not clear until the UP—CF bit is cleared and the next UP—S capture occurs. (See TT control register)

The Downstream capture register104latches the value of the T counter when the Downstream Synchronization pulse is detected. The T counter96Roll and Stop bits are also captured. The Downstream Capture register104is unknown until the first Downstream Synchronization pulse is detected or until the DN—LBEN (downstream loop-back enable) bit is set in the control register and a synchronization system Synchronization Pulse is generated. Roll and stop indicate the state of the ROLL and stop flags when the capture occurred. DN—COF (capture overflow) indicates that DN—CF was already set when the capture occurred. The DN—COF bit will not clear until the DN—CF bit is cleared and the next DN—S capture occurs.

The control register97provides miscellaneous functional and diagnostic control of the synchronization system subsystem.

Channel Data Transfer and Voting

There are three MP/IOP modules1in a preferred system of the present invention as noted above. As shown inFIGS. 10A and 10Bthe three MP/IOP modules communicate with each other via an inter-MP bus or channel.11. The Channel11is a three channel parallel to serial/serial to parallel communications interface with a DMA controller, hardware loop-back fault detection, CRC checking and MP to MP electrical isolation is a high speed communication path between the three MPs15primarily used for voting. The three MPs15a,15band15care time synchronized with each other by a synchronization system.

In operation as shown inFIG. 2each leg (Channel A, B, C) of the system controller is controlled by a separate MP/IOP module1. Each MP/IOP module1operates in parallel with the other two MP/IOP modules1, as a member of a triad. Each IOP17scans each LIO module2installed in the system of the present invention via the RS485 2 Mb LIO bus13at a predetermined time interval (set by the initial programming). As each module is scanned, new input data is transmitted by the IOP17to MP15via the shared memory module16located on the MP/IOP printed circuit board. The SX15′ assembles the input data and stores the input data in an input table in its memory16for application program evaluation.

Channel Voting

Prior to application program evaluation, the input table in memory16is compared with the input tables in memory16on the other MPs15via the channel.11.

The input data in each MP15is transferred to the other MP15modules in the system and “voted” by the SX15′ firmware. If a disagreement is discovered, the value found in two out of three tables prevails, and the third table is corrected accordingly. Each MP15maintains history data for corrections and faults. Any continuing disparity with the same leg, register or the like is recorded for future handling at a predetermined occasion by the SX15′ Fault Analyzer routines.

The SX votes inputs before passing them to the application program to insure that the inputs are correct. Voting will be based on a majority vote on comparison and the defaulting MP/IOP module1data will be corrected. The SX15′ votes the inputs in accordance with the following Table XVI dependent on the number of MP/IOP module1processors in the system and whether the data is analog (a number) or discrete (on or off).

Accordingly, when in TMR mode, i.e. three processors enabled, Digital or Discrete voting is conducted on 2 out of 3 matching. For Analog voting the Midpoint value is selected.

When in Duplex Mode, i.e. two processors enabled, Digital or Discrete voting is concluded on a 2 out of 2 matching. For Analog voting the Average value is selected. For single processor voting the value presented is the value selected for either Discrete or Analog voting.

After such comparison is made the selected value is restored to any table having different values.

In addition to Input comparisons, the SX15′ will also compare the outputs every scan. It will be considered a safety fault, if a MP15output data does not compare with the other MP's output data in accordance with Table XVI. Internal variables will also be compared on a periodic basis as is predetermined by the SX15′ code which can test every scan. The application program code will also be compared on a periodic basis as is predetermined by the SX15′ code which can also be every scan. Any comparison failure is considered a safety fault.

After the channel11transfer and input data voting has corrected the input values, the values are evaluated by the application program. The Development developed application program is executed by the SX15′ in parallel on each MP15using an MPC860 microprocessor which is a suitable CPU for the MP15. The application program generates a set of control system output values based upon the control system input values, according to the rules built in to the program by a Control Engineer for a particular installation. The MP15transmits the output values to the IOP17via shared memory16over interface18. The MP15also votes the control system output values via channel.11to detect faults. The IOP17separates the output data corresponding to individual LIO Modules2in the system. Output data for each LIO module2is transmitted via the LIO bus13to the output modules.

Channel Data Transfer

At predetermined times each MP15rendezvous with the other active members of the triad via the synchronization system and compares and votes all application program input data. During this comparison the actual data is voted a using a majority override mechanism as noted above and all discrepancies corrected where appropriate. Each MP15is transferred a copy of the other's data to compare against and correct it's own copy as required over the channel11. Along with the input data, portions of the MP15memory and hardware status shall transferred to the other MPs15via Channel11and compared by firmware. Discrepancies constitute a fault.

Voting is performed by SX instructions. The Channel11is similar to a generic multi-channel communications controller using buffer descriptors except that Channel11is optimized for TMR SX15′ operation and includes, real time fault detection and fault location of most faults via attenuated transmit loop-backs, no single Channel11failure disables more than one MP15, no physical Channel11interface signal interfaces with more than one other MP15. (Physical interfaces are point-to-point).

A typical channel11transfer used for voting purposes consists of the following steps:Rendezvous (synchronization system) step701Transferring of data to be voted (Channel11) step702Analyzing transfer results (SX), CRC, status, and the like, step703Transferring 1st results data resulting from analyzing transfer results to other MP Modules1(Channel11) step704Accumulating transfer results (SX), received from other MP Modules, step705Transferring 2nd results data indicating voting mode to be taken (Channel11) step706Analyzing and Voting the data, step707

Voting Mode Selection

A combination of firmware algorithms (lookup table) and Channel11attenuated loop-back information permits the MPs15in the triad to detect, locate and contain any single leg Channel11faults to the faulted leg. In addition, the fault status information also allows the non-faulted MPs15in the triad to unanimously agree on the voting mechanism (TMR, Dual or Single). It is important that all MPs15vote using the same voting mode, since voting TMR will result in different (although correct) analog values V/S voting in Dual mode. To insure that all MPs participating in the vote arrive at the same voting mode in the presence of a Channel11fault, the following Channel11result accumulation tables is used.

In order for voting to accurately determine a result the following rules are set regarding the Channel11results:True=Data Transfer Worked, good CRC and good sequence number.False=Data Transfer failed/missing or bad CRC or bad sequence number.All transfers are “written”. I.E. One leg can not pretend to be another.Only one leg faulted at a time.A false value can not be made true by passing it through the bad leg. False values stay false.A true value may be made false (or stay true) by passing it through the bad leg. I.E. True values may go false when passed through the bad leg.A true value passed through a good leg stays true.Loop-back status always correctly detects the fault location.

Abbreviations

Note: These terms are concatenated to form first and second hand status information used to determine the voting mode.

M=my viewU=Up's viewD=Down's viewv=vote is . . .f=fault located at . . .Operators: !=not, |=logical “OR”, &=Logical “AND”RM=my view of another legs data packet status through My receiverRU=Ups view of another legs data packet status through UPs receiverRD=Downs view of another legs data packet status through DNs receiverTM=my view of my loop-back statusTU=Ups view of Ups loop-back statusTD=Downs view of Downs loop-back statusum=result of transfer from path Up to MYdm=result of transfer from path Dn to MYlmu=result of my hardware loop-back from Up to MY pathlmd=result of my hardware loop-back from Dn to MY pathmu=result of transfer from path MY to Updu=result of transfer from path Dn to Uplum=result of Up hardware loop-back from Up to MY pathlud=result of Up hardware loop-back from Up to Dn pathud=result of transfer from path Up to Dnmd=result of transfer from path MY to Dnldm=result of Dn hardware loop-back from Dn to MY pathldu=result of Dn hardware loop-back from Dn to Up pathSkip—OK=Ok to skip a scan. This term prevents the MP from skipping consecutive scans or too many scans per TBD time period.TMRmode=Last vote was TMRvote. Used to determine.DUALmode=Last vote was DUALvote. Used to determine.SINGLEmode=Last vote was Single vote.TMRvote=Voting TMR this scan.DUALvote=Voting DUAL this scan.SINGLEvote=Voting Single this scan.

The method of voting mode selection includes the following steps: The SX system checks the lookup truth table, and the capture register values, step801. The system then checks for any faults or any processor leg, step802. If no faults are detected, then the system enters TMR voting mode. If a fault is discovered, step802, the system determines if more than one processor is faulted, step803. If so, the system continues in single processor voting mode, step804. If all of the processors are faulted, the system halts.

A hardware clock calendar circuit is used to maintain the time and date during the MP power-off state and for OSE. The synchronization system FPGA firmware based clock calendar routines are used to maintain the time and date during the MP power-on state. This time is voted between the MPs.

Attenuated Hardware Communication Interface Loop-Back

TriBus channel transmit data loop-back receiver-checkers independently check the upstream and downstream transmit data drivers. As shown inFIG. 24Loop-back registers99and100are connected through the base-plate so that the transmit data driver base-plate connectors pins will also be diagnosed. The loop-back receivers are slightly attenuated with respect the MPs upstream and downstream receivers so that a weak transmitter will be detected by the loop-back receiver before it is detected by the up or downstream receiver. This feature provides extremely accurate fault identification and location.

When data signals are transmitted to adjacent processors on the various processor legs as shown inFIGS. 11A and 11B, each processor90,91and92has an upstream and downstream loop backpath,90b,90d,91b,91d,92band92d, respectively. The loop back capture registers capture the level of the signal. The signals are attenuated to switch the signal value received by the other upstream and downstream processors. Since the loop-back signal is first received by the transmitting processor, the expected return value can be evaluated.

TERMS AND ACRONYMS USED IN THIS SPECIFICATIONChannel (AlsoAn independent I/O Input−>MP−>I/O Output pathknow as Leg)LCMLocal Communication ModuleLCM BusBus between MP and Local Communication moduleLIO or IOBusInterface between IOP s and IO modulesIOPSystem Input Output ProcessorIOP BusBus between MP/IOP and expansion IOP sLIOX or IOXSystem Input/Output Executive firmwareMPSystem Main ProcessorLRXM or RXMSystem Remote Extender ModuleLSX or SXExecutive firmware System of the present inventionMAUMedia Adapter Unit - for 803.2 networksTMRTriple Modular RedundantTRICONTRICONEX Fault Tolerant PLCchannel.MP inter-processor communications busTriLanTriplicated Peer to Peer BusTrinodeA System MP on TriLansynchronizationMP Time synchronization subsystemsystemDMADirect memory accessTCP/IPTransmission Control Protocol/Internet ProtocolPCPersonal computerDCS HostDistributed processor control systems hostLANLocal area networkLegsChannelLMP/LIOP orMain processor/input output moduleMP/IOPModbusA Modicon protocol busLCBLocal communications busControlProgram developed by user for control of industrialProgramenvironmentFRSField replaceable subsystem

While specific embodiments of this invention has been described above, those skilled in the art will readily appreciate that many modifications are possible in the specific embodiment, without materially departing from the novel teachings and advantages of this invention. Accordingly, all such modifications are intended to be included within the scope of this invention.

Having thus described the invention what is claimed is: