System-on-chip and method of operating the same

A system-on-chip is provided. The system-on-chip includes a system bus, a plurality of IP units connected to the system bus, a processor unit including a plurality of cores configured to control the plurality of IP units via the system bus, a monitoring unit configured to monitor a state of the processor unit, and an error detection unit configured to operate as a master device for the plurality of IP units and monitor a register in which error information indicating whether an error has occurred in each of the plurality of IP units is stored.

BACKGROUND

Methods and apparatuses consistent with example embodiments relate to a system-on-chip and a method of operating the same.

System-on-chips are semiconductor devices that include various intellectual property (IP) units, along with processor units including a core that performs major operations. System-on-chips are used as main components of autonomous vehicles, as well as a variety of electronic devices including computer devices, and the application range thereof is expanding.

SUMMARY

One or more example embodiments provide a system-on-chip in which, whether an error has occurred may be quickly detected and the generated error may be stably processed, by actively monitoring a register storing error information indicating whether an error has occurred in each of a plurality of IP units, and a method of operating the same.

According to an aspect of an example embodiment, a system-on-chip includes a system bus, a plurality of IP units connected to the system bus, a processor unit including a plurality of cores configured to control the plurality of IP units via the system bus, a monitoring unit configured to monitor a state of the processor unit, and an error detection unit configured to operate as a master device for the plurality of IP units and monitor a register in which error information indicating whether an error has occurred in each of the plurality of IP units is stored.

According to an aspect of an example embodiment, a system-on-chip includes a system bus, a processor unit having a plurality of cores, a plurality of IP units configured to operate based on a control command received from the processor unit via the system bus, each of the plurality of IP units comprising a register configured to store error information indicating whether an error has occurred, and an error detection unit configured to monitor the register in each of the plurality of IP units, identify whether the error has occurred based on the error information, and transfer the error information to the processor unit based on the error information stored in the register not being initialized for a predetermined period of time after identifying the error has occurred.

According to an aspect of an example embodiment, a system-on-chip includes a processor unit having a plurality of cores, an interrupt controller configured to transfer an interrupt to the processor unit, a plurality of IP units having a register in which error information indicating whether an error has occurred is stored, and an error detection unit configured to monitor the register in each of the plurality of IP units to identify whether an error has occurred in each of the plurality of IP units, and transmit information indicating an IP unit among the plurality of IP units in which an error has occurred to the processor unit through the interrupt controller. The error detection unit is configured to reset the IP unit in which the error has occurred based on the error information not being initialized in the register of the IP unit in which the error has occurred after transmitting the information indicating the IP unit to the processor unit through the interrupt controller.

DETAILED DESCRIPTION

FIGS.1A,1B, and2are diagrams schematically illustrating apparatuses in which a system-on-chip according to an example embodiment may be mounted.

First, referring toFIGS.1A and1B, an apparatus in which a system-on-chip according to an example embodiment is mounted may be an electronic device1. Referring toFIGS.1A and1B, the electronic device1is illustrated as being a smartphone, but in addition thereto, a system-on-chip according to an example embodiment may be mounted in various devices such as a desktop computer, a laptop computer, a tablet PC, and the like.

Referring toFIG.1A, the electronic device1according to an example embodiment may include a case2, a display5provided on a front surface of the case2, front cameras6and7, and the like. The display5is disposed on the front surface of the case2and may substantially cover the entire front surface of the case2. For example, most of the front surface of the case2may be allocated to a display area of the display5.

The front cameras6and7may have different angles of view, pixel numbers and aperture values, and a user may capture various types of images using the front cameras6and7. For example, at least one of the plurality of front cameras6and7may be used for obtaining biometric information by recognizing a face, an iris, or the like of the user.

Next, referring toFIG.1B, the electronic device1may include a case2, a rear camera8, and the like. Unlike the example embodiment illustrated inFIG.1B, the rear camera8may include a plurality of cameras. In a case in which the rear camera8includes a plurality of cameras, the plurality of cameras may have different pixel numbers, angles of view, aperture values, and the like.

Inside the case2of the electronic device1, various components may be mounted as illustrated inFIG.1B. The components are components for implementing various functions of the electronic device1and examples of the components may include a semiconductor device, a circuit board, a battery, circuit devices, and the like. For example, a circuit board10may be mounted inside the case2of the electronic device1, and various semiconductor devices including a system-on-chip20, and circuit devices, may be mounted on the circuit board10. The system-on-chip20may exchange data and/or power with other semiconductor devices, circuit devices, batteries, and the like through the circuit board10.

In an example, the system-on-chip20may be an application processor, and in addition to a processor unit having cores that execute computational and control operations, may include a graphics processing unit (GPU) processing graphics, a memory controller controlling a dynamic random access memory (DRAM) and/or a flash memory, and IP units, which may include blocks of circuitry performing specific functions, such as an input/output interface connected to other semiconductor devices or the like. The processor unit and various IP units included in the system-on-chip20may exchange data with each other through a system bus inside the system-on-chip20. For example, an IP unit may have a design that includes a trade secret.

The system-on-chip20according to an example embodiment may include an error detection unit actively detecting an error that may occur in a plurality of IP units included therein. The error detection unit may operate in a master-slave manner with the IP units inside the system-on-chip20. For example, the error detection unit may act as a master device for the IP units, and the IP units may act as slave devices.

Each of the plurality of IP units may include a register that stores error information. The error detection unit may monitor the register in each of the IP units irrespective of the operating state of the IP units. Therefore, the error detection unit may actively detect the error information indicating the occurrence of an error in each of the IP units, and may quickly solve the error of the IP units by quickly transmitting the error information to the processor unit or the like.

Next, referring toFIG.2, a system-on-chip31according to an example embodiment may be mounted on a vehicle30. The vehicle30on which the system-on-chip31according to an example embodiment is mounted may be an autonomous vehicle capable of driving by itself without a driver's manipulation. InFIG.2, the system-on-chip31is illustrated as being mounted at the rear of the vehicle30, but an example embodiment thereof is not necessarily limited thereto.

The vehicle30may include various devices required for autonomous driving. For example, the vehicle30may include a front camera32and a rear camera33for capturing an external image, a front sensor34and a rear sensor35for detecting an object around the vehicle, a global positioning system (GPS) sensor36for detecting a position of the vehicle30, and the like. In addition, a body control module (BCM)37that controls overall driving of the vehicle30, a brake device38, a driving recorder39, and the like may be mounted in the vehicle30.

The devices32to39mounted in the vehicle30may be controlled by the system-on-chip31. The system-on-chip31may control the driving of the vehicle30, based on surrounding information and location information collected through the front camera32and the rear camera33, the front sensor34and the rear sensor35, the GPS sensor36and the like. For example, the cameras, for example, the front and read cameras32and33, may be implemented as a general image sensor or a time-of-flight (ToF) sensor, and the sensors, for example, the front and rear sensors34and35, may include a radar device. The arrangement and the number of the cameras32and33and the sensors34and35may be variously modified according to example embodiments.

In the vehicle30having an autonomous driving function, an error occurring in the system-on-chip31may lead to a significant accident. For example, if an error occurring in a portion of IP units included in the system-on-chip31is not solved quickly, a traffic accident or the like may occur. In an example embodiment, unlike the related art method in which respective IP units output error information by themselves and inform a processor unit with an interrupt signal or the like, a separate error detection unit mounted in the system-on-chip31may actively detect error information of IP units. Accordingly, an interrupt signal is generated by IP units in which an error has occurred, and thus, whether or not an error has occurred may be determined faster than that in the related art method recognized by a processor unit, and stability and reliability of the system-on-chip31may be improved.

FIGS.3and4are schematic diagrams illustrating a system-on-chip according to an example embodiment.

Referring toFIG.3, a system-on-chip100according to an example embodiment may be mounted in an electronic device40together with other peripheral devices200. The electronic device40may correspond to various devices such as a home appliance, a server and an autonomous vehicle, in addition to a computer device such as a smartphone, a tablet PC, a desktop, and the like. The peripheral devices200may include a camera210, a sensor module220, a communication terminal230, a vehicle body control module240, and the like. The number and type of the peripheral devices200may vary depending on the type of electronic device40.

The system-on-chip100may include a processor unit110, a monitoring unit120, an error detection unit130, and other various IP units101to108. The number and type of the IP units101to108may be changed depending on a function provided by the system-on-chip100. For example, one or more additional IP units different from the IP units101to108may be added to the system-on-chip100, or at least one of the IP units101to108may be removed from the system-on-chip100. In the example embodiment illustrated inFIG.3, the IP units (101to108) may include an internal memory101, an audio processing unit102, a graphics processing unit103, an input/output interface104, an image processing processor105, a power management unit106, a memory controller107, a security unit108, and the like.

The processor unit110may include one or more cores that perform operations and generate and process instructions. The processor unit110may control an overall operation of the system-on-chip100. The processor unit110may be connected to the monitoring unit120including a watchdog timer circuit and the like.

The processor unit110may periodically reset the watchdog timer included in the monitoring unit120. The monitoring unit120may determine that an error has occurred in the processor unit110when the watchdog timer is not reset at a predetermined cycle. In an example, the monitoring unit120may be implemented to be programmable. When it is determined that an error has occurred in the processor unit110, the monitoring unit120may perform a process including a method of resetting the processor unit110, re-supplying power after being disconnected, or activating a safe mode.

The error detection unit130may monitor a register in which error information is stored, and the register is included in each of the plurality of IP units101to108. Each of the plurality of IP units101to108may have a register in which error information indicating whether an error has occurred is stored. The error detection unit130may operate as a master device for the plurality of IP units101to108, and may detect whether an error has occurred by monitoring a register of each of the plurality of IP units101to108that operate as slave devices.

In general, each of the plurality of IP units101to108changes a value of the error information stored in a register when an error has occurred, and reports an error occurrence to the processor unit110or a separate error processing unit using an interrupt signal or the like. Therefore, it may take additional time until the error occurrence is transmitted to the processor unit110, the error processing unit, or the like.

The plurality of IP units101to108may notify the processor unit110that an error has occurred through an interrupt controller connected to the processor unit110, or may notify the processor unit110and/or the error processing unit that an error has occurred via a system bus. Therefore, in a case in which an error also occurs in an interrupt controller or a system bus, the error occurrence may not be normally notified to the processor unit110and/or the error processing unit.

Thus, in an example embodiment, the error detection unit130may actively monitor a register in which error information is stored in each of the plurality of IP units101to108. The error detection unit130operates as a master device for the plurality of IP units101to108, and may monitor a register in which error information is stored regardless of whether the plurality of IP units101to108are actually operating. For example, the error detection unit130may monitor the register even when the plurality of IP units101to108are in an idle state.

Therefore, in the system-on-chip100according to an example embodiment, an error occurrence of each of the plurality of IP units101to108may be quickly detected and processed. The error detection unit130may notify the processor unit110and/or the error processing unit of information of an IP unit determined to have an error among the plurality of IP units101to108. In an example embodiment, the error detection unit130may notify the information of the IP unit in which the error has occurred through an interrupt controller or a system bus. In addition, when it is also determined that an error has occurred in the interrupt controller or the system bus, the error detection unit130may directly notify the processor unit110and/or the error processing unit of the information of the IP unit in which the error has occurred.

Next, referring toFIG.4, a system-on-chip300according to an example embodiment may include a system bus305, a processor unit310, an interrupt controller320, an error detection unit330, a monitoring unit340, and other various IP units350to390. In the example embodiment illustrated inFIG.4, the IP units (350to590) may include a memory controller350, an internal memory360, an input/output interface370, a graphics processing unit380, a power management unit390, and the like.

The processor unit310may exchange data with the IP units350to390through the system bus305. The interrupt controller320may generate an interrupt signal by receiving a request of the processor unit310and the IP units350to390. The error detection unit330may determine whether an error has occurred in the respective IP units350to390by monitoring a register in which error information is stored in each of the IP units350to390.

The monitoring unit340may include a watchdog timer circuit and the like. The monitoring unit340may communicate directly with the processor unit310without going through the system bus305, and may determine that an error has occurred in the processor unit310when the watchdog timer is not reset by the processor unit310at a predetermined period or timing.

In an example embodiment, the error detection unit330may monitor the register even when the IP units350to390are in an idle state. For example, when error information is detected as an error state in a register of the IP units350to390that are in an idle state, the error detection unit330may notify the processor unit310of the error information. In detail, before the IP units350to390are switched from the idle state to an active mode, the processor unit310may process an error, and the IP units350to390are activated and may operate normally. Therefore, the reliability of the system-on-chip300may be improved.

The error detection unit330may also detect whether an error occurs in the system bus305and the interrupt controller320. As an example, when it is detected that an error has occurred, based on an error information of a register of at least one of the IP units350to390, the error detection unit330may request that the interrupt controller320generate an interrupt. When the interrupt controller320receives the request of the error detection unit330, the interrupt controller320may transmit information of the IP unit in which the error has occurred to the processor unit310, and the processor unit310may process the error occurring in the IP unit and may initialize error information stored in the register. For example, when the interrupt controller320does not operate normally and the interrupt is not generated despite the request, the error information stored in the register of the IP units350to390in which the error has occurred may not be initialized.

In this case, in an example embodiment, after the error detection unit330detects error information from the register of at least one of the IP units350to390and transmits an interrupt generation request to the interrupt controller320, when the error information of the register is not initialized during a predetermined period of time, it may be determined that an error has occurred in the interrupt controller320. In this case, the error detection unit330may directly notify the processor unit310of an abnormal state of the IP units350to390in which the error information is detected as an error state, without passing through the interrupt controller320. The processor unit310may execute a process of restarting the interrupt controller320by controlling the power management unit390to solve the abnormal state of the interrupt controller320.

In addition, for example, when an error occurs in the system bus305, after the error detection unit330detects an error information and requests that the interrupt controller320generate an interrupt, the error information may not be initialized for a predetermined period of time. In this case, the error detection unit330may notify the processor unit310of the abnormality of the system bus305. The processor unit310may apply a process such as restarting the system bus305through the power management unit390to solve the abnormal state of the system bus305.

In an example embodiment, the error detection unit330may operate based on a code expressed in hardware form available at a Register Transfer Level (RTL) or a gate level at which a gate to perform the function is implemented. Accordingly, the error detection unit330may monitor a register in which the error information is stored in the IP units350to390without increasing a resource of the system-on-chip300.

FIG.5is a diagram schematically illustrating a processor unit included in a system-on-chip according to an example embodiment.

Referring toFIG.5, a processor unit400according to an example embodiment may include a plurality of cores410to440. The plurality of cores410to440may include a first core410, a second core420, a third core430and a fourth core440. The plurality of cores410to440may perform a function such as executing an operation or generating and processing an instruction. The number of cores410to440included in the processor unit400may vary according to example embodiments, and the cores410to440may have the same or different architectures.

The plurality of cores410to440may include cache memories415to445, respectively. The first core410may include a first cache415, the second core420may include a second cache425, the third core430may include a third cache435, and the fourth core440may include a fourth cache445. The processor unit400may include a common cache memory450shared by the plurality of cores410to440. The cache memories415to445and the common cache memory450may be implemented by the same or different types of memories. In an example, the cache memories415to445and the common cache memory450may be all implemented as dynamic random access memories (DRAMs), or the cache memories415to445may be implemented as static random access memories (SRAMs) and the common cache memory450may be implemented by a dynamic random access memory (DRAM). A storage capacity of the common cache memory450may be greater than a storage capacity of each of the cache memories415to445. The common cache memory450and the cache memories415to445may be used to improve the speed of exchanging data with a main memory outside the system-on-chip.

FIGS.6to8are flowcharts illustrating a method of operating a system-on-chip according to example embodiments.

First, referring toFIG.6, a method of operating a system-on-chip according to an example embodiment include an error detection unit monitoring a register in which error information is stored in each of a plurality of IP units (S10). Each of the IP units may update a register in which error information is stored when an error has occurred. The error detection unit may determine whether error information indicating an error occurrence is retrieved from the register of each of the IP units (S11).

When an error has occurred in at least one of the IP units, the IP unit may update the register so that the error information indicates an error occurrence, and may notify a processor unit that the error has occurred through an interrupt controller or the like. When the processor unit is normally notified that an error has occurred, the processor unit may handle the error of the IP unit and return the error information stored in the register to the initial state.

The error detection unit may retrieve the error information and may determine whether the error information stored in the register is initialized after a predetermined time has elapsed (S12). When the error information of the IP unit is normally notified to the processor unit and the error is resolved, the error detection unit may confirm that the error information has been initialized in operation S12. On the other hand, when the error of the IP unit is not resolved due to a problem of an interrupt controller, a system bus, or other components, the error detection unit may confirm that the error information is not initialized in operation S12.

When it is determined in operation S12that the error information has not initialized after the predetermined time has elapsed, the error detection unit may transmit information of the IP unit in which the error information has been detected, to the processor unit (S13). For example, in operation S13, the error detection unit may directly transmit information of the IP unit in which the error information has been detected, to the processor unit without intervention of the interrupt controller. Alternatively, the error detection unit may request a power management unit or the like to perform an operation such as resetting the IP unit in which the error information has been detected or the like.

Next, referring toFIG.7, a method of operating a system-on-chip according to an example embodiment may include an error detection unit monitoring a register in which error information is stored in each of a plurality of IP units (S20). The monitoring operation of operation S20may be applied not only to activated IP units that exchange data with a processor unit and the like through a system bus, but also to IP units in an idle state, which are not activated.

In detail, an example embodiment employs an operating manner in which the error detection unit operates as a master device for the IP units to actively monitor the register in which the error information is stored, not a manner in which IP units determine whether an error has occurred by themselves and change error information stored in a register and then output the information when an error has occurred. Therefore, whether an error has occurred may be quickly determined, and in a case in which an error occurs in IP units in an idle state, the error may be proactively processed before the IP units are activated, thereby preventing malfunctioning of the system-on-chip in advance.

The error detection unit may determine whether error information stored in a register of at least one of the IP units indicates the occurrence of an error, during the monitoring operation (S21). When error information indicating the occurrence of an error is not detected as a result of the determination in operation S21, the monitoring operation may continue. When error information indicating the occurrence of an error is detected in operation S21, the error detection unit may transfer information of the IP unit in which the error information indicating the occurrence of an error has been detected, to the processor unit through an interrupt controller (S22).

As an example, in operation S22, the error detection unit may request that the interrupt controller generate an interrupt for notifying the information of the IP unit in which error information indicating the occurrence of an error has been detected. The processor unit receiving the interrupt from the interrupt controller may process an error occurring in the IP unit and may initialize the error information stored in the register. The error detection unit may determine whether the error information is initialized in the register of the IP unit in which the error information indicating the occurrence of the error has been detected (S23).

When the error information is initialized in operation S23, the error detection unit may end the error processing operation without any additional operation. On the other hand, when the error information is not initialized in operation S23, the error detection unit may determine that an error has occurred in the interrupt controller. Therefore, the error detection unit may directly transmit information of the IP unit in which the error information has been detected, to the processor unit without intervention of the interrupt controller (S24).

Next, referring toFIG.8, a method of operating a system-on-chip according to an example embodiment may include an error detection unit monitoring a register in which error information is stored in each of a plurality of IP units (S30). Similarly as described with reference toFIG.7, the monitoring operation of operation S20may be applied to IP units in an idle state, which are not activated, as well as activated IP units.

During the monitoring operation, the error detection unit may determine whether error information stored in a register of at least one of IP units indicates an error occurrence (S31). When error information indicating the occurrence of an error is not detected as a result of the determination in operation S31, the monitoring operation may continue. When error information indicating the occurrence of an error is detected in operation S31, the error detection unit may transfer information of the IP unit in which the error information has been detected, to a processor unit through the interrupt controller (S32).

When the interrupt controller receives a request of the error detection unit and transmits information of the IP unit in which the error has occurred, to the processor unit, the processor unit may process an error occurring in the IP unit and may initialize error information stored in the register. The error detection unit may determine whether the error information is initialized in the register of the IP unit in which the error has occurred (S33).

When the error information is initialized in operation S33, the error detection unit may end the error processing operation without any additional operation. On the other hand, when the error information is not initialized in operation S33, the error detection unit may forcibly reset the IP unit in which the error information has been detected (S34). As an example, the error detection unit may perform the reset operation of operation S34by forcibly restarting the IP unit in which the error has occurred, through a power management unit mounted on the system-on-chip.

The operations according to the example embodiments described with reference toFIGS.6to8may also be combined with each other. For example, the reset operation of operation S34described with reference toFIG.8may be performed after the operation S13described with reference toFIG.6and/or the operation of operation S24described with reference toFIG.7. In the example embodiment illustrated inFIG.7, the error detection unit may determine whether the error information is initialized by monitoring the register of the IP unit in which the error has occurred after executing the operation of operation S24. When the error information is not initialized, the error detection unit may determine that an abnormality has occurred in the system bus or the like, and may execute the reset operation of operation S34of forcibly resetting the IP unit in which the error has occurred.

FIGS.9and10are diagrams illustrating a method of operating a system-on-chip according to an example embodiment.FIGS.11and12are timing diagrams illustrating a method of operating a system-on-chip according to an example embodiment.

A system-on-chip500according to an example embodiment illustrated inFIGS.9and10may include a system bus505, a processor unit510, an interrupt controller520, an error detection unit530, a monitoring unit540, and a plurality of IP units550to590.

Referring first toFIG.9, the error detection unit530may monitor a register in which error information is stored in each of the IP units550to590. The IP units550to590may include memory controller550, internal memory560, input/output interface570, graphics processing unit580and power management unit590. When error information indicating an error occurrence is detected in a register of at least one of the IP units550to590, the error detection unit530may request that the interrupt controller520generate an interrupt. When the interrupt is normally generated and delivered to the processor unit510, the processor unit510may process the error of the IP units550to590in which error information has been detected, for example, the error of a memory controller550, an input/output interface570, a graphics processing unit580, and the like and may initialize the error information.

FIG.11is a timing diagram illustrating an operation of the system-on-chip500illustrated inFIG.9. Referring to the timing diagram ofFIG.11, the state of the register in which error information is stored in each of the memory controller550, the input/output interface570, and the graphics processing unit580is illustrated together with an internal clock signal CLK of the system-on-chip500.

For example, when an error occurs in the memory controller550, the input/output interface570, and the graphics processing unit580, each of the memory controller550, the input/output interface570, and the graphics processing unit580may change error information stored in a register from an initial state (INIT.) to an error state (ERROR). The error detection unit530may detect that the error information has changed to the error state ERROR, and may request that the interrupt controller520generate an interrupt.

Upon receiving the interrupt generation request, the interrupt controller520may output the interrupt to the processor unit510at a first time point t1. Upon receiving the interrupt, the processor unit510may process an error occurring in the memory controller550, the input/output interface570and the graphics processing unit580, and may initialize the error information of the register to an initial state (INIT.). When the error information returns to the initial state (INIT.), the interrupt output of the interrupt controller520may also be initialized at a second time point t2.

Next, in an example embodiment illustrated inFIG.10, when error information indicating an error occurrence is detected in a register of at least one of the IP units550to590, the error detection unit530may directly transmit the error information to the processor unit510without passing through the interrupt controller520. The example embodiment illustrated inFIG.10may correspond to a case in which an error occurs in the interrupt controller520and the interrupt is not output to the processor unit510despite the request of the error detection unit530.

As an example, the error detection unit530may transmit information of the units in which error information indicating an error occurrence has been detected, among the IP units550to590, for example, the information of the memory controller550, the input/output interface570and the graphics processing unit, directly to the processor unit510. The processor unit510may process errors of the memory controller550, the input/output interface570, and the graphics processing unit580, and initialize error information of the register.

FIG.12is a timing diagram illustrating an operation of the system-on-chip500illustrated inFIG.10. Referring to the timing diagram ofFIG.12, the state of a register in which error information is stored in each of the memory controller550, the input/output interface570, and the graphics processing unit580is illustrated together with the internal clock signal CLK of the system-on-chip500.

In the example embodiment illustrated inFIG.12, the error detection unit530detects error information from the memory controller550, the input/output interface570and the graphics processing unit580, and may request that the interrupt controller520generate an interrupt. However, as in the example case described above, due to an abnormality occurring in the interrupt controller520, the interrupt may not be transmitted from the interrupt controller520to the processor unit510.

After the error detection unit530requests that the interrupt controller520generate an interrupt, the error detection unit530may monitor a register in which error information is stored in each of the memory controller550, the input/output interface570, and the graphics processing unit580. When the error information stored in the register maintains the error state (ERROR) even after requesting the interrupt generation and a predetermined time has elapsed, the error detection unit530may directly notify the processor unit510of the occurrence of error without passing through the interrupt controller520.

Alternatively, the error detection unit530may request the interrupt controller520to generate an interrupt and may monitor the output of the interrupt controller520. When the interrupt is not output from the interrupt controller520even after requesting to generate an interrupt and a predetermined time has elapsed, the error detection unit530directly notifies the processor unit510that the error has occurred without passing through the interrupt controller520. The processor unit510notified of the error occurrence may process an error of the IP units550,570and580in which the error has occurred, and may return the error information stored in the register to the initial state (INIT.).

FIG.13is a diagram schematically illustrating a system-on-chip according to an example embodiment.

Referring toFIG.13, a system-on-chip600according to an example embodiment may include a system bus605, a processor unit610, an interrupt controller620, an error detection unit630, and an error processing unit635, a monitoring unit640, and other various IP units650to690. In an example embodiment illustrated inFIG.13, the IP units (650to690) may include a memory controller650, an internal memory660, an input/output interface670, a graphics processing unit680, a power management unit690, and the like.

The system-on-chip600according to the example embodiment illustrated inFIG.13may include an error processing unit635operating in an operating system different from that of the processor unit610. Cores included in the processor unit610and the error processing unit635, respectively, may have different architectures. Therefore, even in a case in which an abnormality occurs in the processor unit610, the error processing unit635may operate normally.

The error processing unit635may handle an error occurring in each of the IP units650to690. The error processing unit635may process an error in the IP units650to690in which an error has occurred, or may restart the IP units650to690in which the error has occurred. The error processing unit635may have control authority for the power management unit690, to restart the IP units650to690in which the error has occurred.

FIG.14is a flowchart illustrating a method of operating a system-on-chip according to an example embodiment.

Referring toFIG.14, a method of operating a system-on-chip according to an example embodiment may include an error detection unit monitoring a register in which error information is stored in each of a plurality of IP units (S40). The monitoring operation of operation S40may be applied to IP units in an idle state, which are not activated, as well as activated IP units that exchange data with the processor unit and the like through the system bus. Therefore, in an example embodiment, when an error occurs in IP units in an idle state, the malfunction of the system-on-chip may be prevented by preemptively processing the error before the IP units are activated.

During the monitoring operation, the error detection unit may determine whether error information stored in a register of at least one of the IP units indicates an error occurrence (S41). When error information indicating the occurrence of an error is not detected as a result of the determination in operation S41, the monitoring operation may continue. On the other hand, when error information indicating the occurrence of an error is detected in operation S41, the error detection unit may transfer information of an IP unit in which the error has occurred, to the error processing unit through an interrupt controller (S42).

As an example, in operation S42, the error detection unit may transfer information of an IP unit in which an error has occurred directly to the error processing unit without passing through a system bus. In this case, even when an error occurs in the system bus, the error processing unit may quickly process an error of the IP unit. The error detection unit may determine whether the error information is initialized in the register of the IP unit in which the error has occurred (S43).

When the error information is initialized in operation S43, the error detection unit may end the error processing operation without an additional operation. On the other hand, when the error information is not initialized in operation S43, the error detection unit may determine that an error has occurred in the interrupt controller or the system bus. In this case, the error detection unit may transfer information of the IP unit in which the error has occurred, directly to the processor unit or to the process unit through the interrupt controller (S44).

FIGS.15and16are diagrams illustrating a method of operating a system-on-chip according to an example embodiment.FIGS.17and18are timing diagrams illustrating a method of operating a system-on-chip according to an example embodiment.

A system-on-chip700according to an example embodiment illustrated inFIGS.15and16may include a system bus705, a processor unit710, an interrupt controller720, an error detection unit730, and an error processing unit735, a monitoring unit740, and a plurality of IP units750to790. For example, the plurality of IP units may include memory controller750, internal memory760, input/output interface770, graphics processing unit780and power management unit790. The error processing unit735may operate based on an operating system different from that of the processor unit710.

Referring first toFIG.15, the error detection unit730may monitor a register in which error information is stored in each of the IP units750to790. When error information is detected in an error state in a register of at least one of the IP units750to790, the error detection unit730may notify the error processing unit735that the error has occurred. In an example, the error detection unit730may notify the error processing unit735of the information of the IP unit in which the error has occurred. The error processing unit735may process errors of the IP units in which the error has occurred, for example, the memory controller750, the input/output interface770, the graphics processing unit780, and may initialize the error information.

FIG.17is a timing diagram for describing an operation of the system-on-chip700illustrated inFIG.15. Referring to the timing diagram ofFIG.17, the state of a register in which error information is stored in each of the memory controller750, the input/output interface770and the graphics processing unit780is illustrated together with an internal clock signal CLK of the system-on-chip700.

For example, when an error occurs in the memory controller750, the input/output interface770, and the graphics processing unit780, error information stored in a register of each of the memory controller750, the input/output interface770, and the graphics processing unit780may be changed from an initial state (INIT.) to an error state (ERROR). When the error detection unit730detects that the error information is changed to the error state ERROR, the error detection unit730may notify the error processing unit735that an error has occurred in the memory controller750, the input/output interface770and the graphics processing unit780.

The error processing unit735that is notified the error has occurred may process an error of the memory controller750, the input/output interface770, and the graphics processing unit780. When the error is processed, the error information stored in the registers of the memory controller750, the input/output interface770, and the graphics processing unit780may be initialized to an initial state (INIT.).

Next, in an example embodiment illustrated inFIG.16, when error information is detected in an error state in a register of at least one of the IP units750to790, the error detection unit730may notify the error processing unit735of information of the IP unit in which an error has occurred. However, the example embodiment illustrated inFIG.16may correspond to a case in which an error occurs in the error processing unit735and the error processing unit735fails to process the error despite the request of the error detection unit730.

The error detection unit730notifies the error processing unit735that the error has occurred, and then may continuously monitor registers of the memory controller750, the input/output interface770, and the graphics processing unit780, in which the error has occurred. The error processing unit735is notified that an error has occurred, and after a predetermined time has elapsed, when the error information of the register is not initialized to the initial state (INIT.), the error detection unit730may request the interrupt controller720to generate an interrupt. In an example embodiment illustrated inFIG.18, the error detection unit730may transmit the generated interrupt to the interrupt controller720at a first time point t1.

The interrupt controller720may output an interrupt for notifying the processor unit710that an error has occurred in the memory controller750, the input/output interface770, and the graphics processing unit780, in response to a request from the error detection unit730. The processor unit710may process an error of the memory controller750, the input/output interface770, and the graphics processing unit780in response to the interrupt, and may return the error information of the register to the initial state (INIT.).

FIG.19is a flowchart illustrating a method of operating a system-on-chip according to an example embodiment.

Referring toFIG.19, a method of operating a system-on-chip according to an example embodiment may include an error detection unit monitoring whether an IP unit is in an idle state (S50). In an example, the idle state of the IP unit may be defined as a state in which the IP unit does not operate by actually inputting/outputting or processing data. The error detection unit may determine whether the IP unit is in an idle state through the monitoring operation (S51).

When it is determined that the IP unit is in the idle state as a result of the determination in operation S51, the error detection unit may request execution of a diagnostic process from the IP unit in the idle state (S52). Upon receiving the request from the error detection unit, the IP unit may execute a diagnostic process to determine whether a problem exists (S53).

When there is a problem as a result of the determination in operation S53, in detail, it is determined that an error has occurred, the IP unit may update the error information of the register to indicate the occurrence of the error. In addition, information about the IP unit in which the error information has been detected may be transmitted through the interrupt controller (S54). Operation S54may be executed by the IP unit or may be executed by the error detection unit.

The error detection unit may monitor the register in which the error information of the IP unit is stored and may determine whether the error information is initialized (S55). In an example, when the IP unit or error detection unit succeeds in delivering error information to the processor unit via the interrupt controller, the error information may be initialized. Therefore, when the error information is not initialized, the error detection unit may determine that a problem occurred in the interrupt controller, the system bus or the like, so that the error of the IP unit is not normally processed.

When the error information is not initialized in operation S55, the error detection unit may directly transmit information of the IP unit in which the error information has been detected, to the processor unit without intervention of the interrupt controller (S56). Alternatively, the error detection unit may transfer information of the IP unit in which the error information has been detected to a separate error processing unit, or may reset the IP unit in which the error information has been detected by controlling the power management unit. In detail, the error detection unit notifies the processor unit of information of the IP unit in which the error information has been detected through the interrupt controller and even after a predetermined time has elapsed, when the error information of the IP unit is not initialized, the error detection unit may perform processes for handling errors of the IP unit via various routes.

The system-on-chip according to various embodiments described above may be applied to an autonomous vehicle. When the error detection unit of the system-on-chip applied to the autonomous vehicle detects an error from at least one of the IP units, the error processing unit or the processor unit may handle the error. However, when the error is not handled for a predetermined period of time, the system-on-chip may forcibly stop the autonomous vehicle and enter a safety mode to diagnose the system.

The method of handling an error occurring in the IP units may include restarting the IP unit in which the error has occurred, forcibly turning off the IP unit in which the error has occurred by controlling the power management unit, or the like. On the other hand, in a case in which the above operations are executed during the operation of the autonomous vehicle, a safety accident may occur, and thus, the system-on-chip may first stop the vehicle and then perform the above operations.

As set forth above, according to an example embodiment, an error detection unit operating as a master device for a plurality of IP units is included in a system-on-chip, and the error detection unit may monitor a register in which error information is stored in each of the plurality of IP units. When error information is detected, the error detection unit may deliver the error information to a processor unit and/or a separate error processing unit directly or via an interrupter. By implementing an error detection unit that operates as a master device for a plurality of IP units in hardware to be implemented inside the system-on-chip, an error may be processed quickly and stably without increasing resources of the system-on-chip.