Current differential buffer

The present technique relates to a method and apparatus for operating a differential buffer. In the differential buffer, a first stage may include a differential pair configured to receive input signals and generate output signals. The first stage may also include adjustment circuitry coupled to the differential pair and configured to adjust an amount of current dissipated by the differential buffer. Further, a second stage may include current pulse circuitry coupled to the differential pair and the adjustment circuitry, wherein the current pulse circuitry is configured to generate a current pulse that is coincident with the switching of the differential pair. Finally, the second stage may also include grounding circuitry coupled to the current pulse circuitry and the differential pair, wherein the grounding circuitry is configured to receive the current pulse to prevent the output signals from switching during a transition of the output signals. As such, the differential buffer provides low or no static current dissipation with improved signal integrity for high-speed operation.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to semiconductor devices and, more particularly, to a differential buffering technique for use in a device, such as a memory device or application specific integrated circuit.

2. Description of the Related Art

Microprocessor-controlled integrated circuits are used in a wide variety of applications. Such applications include personal computers, telephones, control systems, networks, and a host of consumer products. Microprocessors are essentially generic devices that perform specific functions under the control of a software program. This program is stored in a memory device, such as a dynamic random access memory (DRAM), static random access memory (SRAM) or other suitable type of memory that may be coupled to the microprocessor. Not only does the microprocessor access the memory devices to retrieve program instructions, but it also stores and retrieves data created during the execution of the program in one or more memory devices.

To enhance communication between components, such as the microprocessor and memory devices, various structures and circuitry may be utilized. For instance, these structures may enable the exchange of data signals between semiconductor chips and other devices. One structure that may be utilized is a buffer, which may store, delay and regenerate data signals. These buffers may be implemented in a variety of devices, such as DRAMs, SRAMs, memory buses, processors, network processors, application specific integrated circuits (ASICs), and intra-chip buses. As such, the buffers may be utilized to enhance the operation of the device.

Typical buffers may operate at speeds that are too slow for high-speed communication. As a result, differential buffers, along with a current mirror generated source, may be utilized as buffers. The differential buffers utilize a data signal and its compliment to provide faster sensing of changes in the data signal. This approach provides for faster data sensing because the data signals are complimentary signals. However, the differential buffers, which may be loaded with resistors or FETs, dissipate current at a static level, which consumes power unnecessarily. That is, the static level of current dissipation is not adjustable to allow the device to conserve power. Thus, differential buffers that provide a static level of current dissipation may be problematic.

SUMMARY OF THE INVENTION

Certain aspects commensurate in scope with the disclosed embodiments are set forth below. It should be understood that these aspects are presented merely to provide the reader with a brief summary of certain forms the invention might take and that these aspects are not intended to limit the scope of the invention. Indeed, the invention may encompass a variety of aspects that may not be set forth below.

Embodiments of the invention provide a differential buffer that may provide low or no static current dissipation with enhanced signal integrity for differential buffering. A method and apparatus for operating a differential buffer that adjusts or eliminates current dissipation is provided. More particularly, in an explempary embodiment, a differential buffer may include a first stage, which includes a diode biased differential pair coupled to adjustment circuitry to control the supply bounce created during a transition of the output signals. The adjustment circuitry may be utilized to adjust the output swing level and adjust the current dissipation for the differential buffer. Further, in a second stage, current pulse circuitry may be utilized with the adjustment circuitry to provide a current pulse that is coincident with the switching of the output signals in the differential pair. This current pulse is mirrored to a bias device to control the voltage differential for the differential pair, which adjusts the current generated in the output signals.

DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS

The present technique is an improved approach for utilizing a differential buffer that adjusts or eliminates the current dissipation in a differential buffer. In accordance with the present technique, a first stage, which includes a diode biased differential pair coupled to adjustment circuitry, controls the supply bounce created during a transition of the output signals. The adjustment circuitry is utilized to adjust the output swing level and to adjust the current dissipation for the differential buffer. Further, a second stage, which includes current pulse circuitry, is utilized with the adjustment circuitry to provide a current pulse that is coincident with the switching of the output signals on the differential pair. This current pulse is mirrored to a bias device to control the voltage level of a drain of a dissipation transistor. As a result, the operation of the device may be enhanced because the differential buffer supports high drive capability and enhances signal integrity for high-speed circuit operation.

Turning now to the drawings, and referring initially toFIG. 1, a block diagram depicting an exemplary processor-based device, generally designated by the reference numeral100, is illustrated. The device100may be any of a variety of different types, such as a computer, pager, cellular telephone, personal organizer, control circuit, etc. In a typical processor-based device, a processor102, such as a microprocessor, controls many of the functions of the device100.

The device100typically includes a power supply104. For instance, if the device100is portable, the power supply104may include permanent batteries, replaceable batteries, and/or rechargeable batteries. The power supply104may also include an A/C adapter, so that the device may be plugged into a wall outlet, for instance. The power supply104may also include a D/C adapter, so that the device100may be plugged into a vehicle's cigarette lighter, for instance.

Various other devices may be coupled to the processor102to provide mechanisms for interacting with a user. For instance, a user interface106may be coupled to the processor102to allow a user to enter data into the device100. The user interface106may include buttons, switches, a keyboard, a light pen, a mouse, and/or a voice recognition system, for instance. A display108may also be coupled to the processor102to present the user with information. The display108may include a liquid-crystal display (LCD), a cathode ray tube (CRT), light-emitting diodes (LEDs), and/or an audio display.

Furthermore, other devices may be coupled to the processor102, which may depend upon the functions that the device100performs. For example, a radio frequency (RF) subsystem/baseband processor110may also be coupled to the processor102to communicate with other devices through a wireless link. The RF subsystem/baseband processor110may include an antenna that is coupled to an RF receiver and to an RF transmitter (not shown). Also, a communication port112may be coupled to the processor102for addition communication with other devices through a physical link. The communication port112may be adapted to be coupled to a peripheral device114, such as a modem, a printer, or a computer, for instance. Further, depending on the particular device100, an application specific integrated circuit (ASIC)118may be utilized in the processor-based device to perform specific functions, such as those associated with a cellular telephone, medical instrument, automobile safety system, and/or high-performance security camera, for example.

Because the processor102controls the functioning of the device100, which is generally under the control of software programming, memory is coupled to the processor102to store and facilitate execution of the program. For instance, the processor102may be coupled to a memory device116, which may include volatile memory, such as dynamic random access memory (DRAM) and/or static random access memory (SRAM), for instance. The amount of DRAM and SRAM may depend on the specific design of the device100. The memory device116may also include non-volatile memory, such as read only memory (ROM)or erasable programmable ROM (EPROM), that is utilized in conjunction with the volatile memory. The size of the ROM is typically selected to be just large enough to store any necessary operating system, application programs, and fixed data. The volatile memory, on the other hand, is typically quite large so that it can store dynamically loaded applications. Additionally, the non-volatile memory may include a high capacity memory, such as a disk or tape drive memory. As will be apppeciated the memory device116may actually include any number of desirable types of memory devices.

The processor-based device100may include numerous semiconductor chips in the various components that are utilized to provide the functionality to the device100. For instance, the memory device116may be one or more semiconductor chips that are coupled to the processor-based device100to store the software programming for the operation of the processor-based device100. The semiconductor chips may exchange signals between each other and other components of the device100to perform their respective functions. As such, improvements in each of the semiconductor chips may improve the efficiency of the processor-based device100and provide reliable access to the information stored in the memory device116. An exemplary embodiment of a memory device, such as the volatile memory, is explained in greater detail inFIG. 2.

Turning now toFIG. 2, a block diagram depicting an exemplary embodiment of a memory device is illustrated. The description of the memory device116has been simplified for illustrative purposes and is not intended to be a complete description of each feature in a memory device116. Differential buffers in accordance with aspects of the present techniques, which are described in more detail with reference toFIG. 4, may be utilized in row-address buffers210, column address buffers214, data-in circuitry220, data-out-circuitry222, address buffers230, and/or data buffers232, as discussed below. Similarly, the present technique may not be limited to implementation in a memory device116but may be applicable to other devices, such as memory buses, processors, network processors, and intra-chip buses, which may benefit from high drive capability and enhanced signal integrity for high speed circuit operation. As such, various devices may implement the differential buffers in accordance with aspects of the present technique.

During operation, the memory device116may receive various inputs that are utilized by various circuits within the memory device116. For instance, individual inputs, such as control information, address information, and data, may be provided over a memory bus to the memory device116. These individual representations of inputs are illustrated by a data bus or lines202, address bus or lines204, and various discrete lines directed to control logic206. The memory device116includes a memory array208, which comprises rows and columns of addressable memory cells. To provide access to the memory cells, each memory cell in a row is coupled to a word line. Additionally, each memory cell in a column is coupled to a bit line. The word line and bit line may be utilized to access, a storage capacitor through an access transistor in each cell of the memory array208, for instance.

The memory device116interfaces with, for example, a processor102, such as a microprocessor, through address lines204and data lines202. Alternatively, the memory device116may interface with other devices, such as a memory controller, a microcontroller, a chip set, or another electronic system. The processor102may also provide a number of control signals to the memory device116. Such control signals may include row and column address strobe signals RAS and CAS, a write enable signal WE, a clock enable signal CKE, and other conventional control signals. The control logic206controls many available functions of the memory device116. In addition, various other control circuits and signals, not detailed herein, contribute to the operation of the memory device116.

Row-address buffers210and a row decoder212receive and decode row addresses from row address signals provided on the address lines204via the address buffers230. Each unique row address corresponds to a row of cells in the memory array208. The row decoder212typically includes a word line driver, an address decoder tree, and circuitry, which translates a given row address received from the row-address buffers210and selectively activates the appropriate word line of the memory array208via the word line drivers.

A column address buffer214and a column decoder216receive and decode column address signals provided on the address lines204. The column decoder216may also determine when a column is defective, as well as the address of a replacement column. The column decoder216is coupled to sense amplifiers218. The sense amplifiers218are coupled to complimentary pairs of bit lines of the memory array208, for example.

The sense amplifiers218are coupled to data-in (i.e., write) circuitry220and data-out (i.e., read) circuitry222. The data-in circuitry220and the data-out circuitry222include data drivers and latches. During a write operation, the data lines202provide data from the address buffers230to the data-in circuitry220. The sense amplifier218receives data from-the data-in circuitry220and stores the data in the memory array208as a charge on a capacitor of a cell at an address specified on the address lines204.

During a read operation, the memory device116transfers data to the processor102from the memory array208. Complimentary bit lines for the accessed cell are equilibrated during a precharge operation to a reference voltage provided by an equilibration circuit and a reference voltage supply. The charge stored in the accessed cell is then shared with the associated bit lines. The sense amplifier218detects and amplifies a difference in voltage between the complimentary bit lines. Address information received on address lines204facilitates selection of a subset of the bit lines and coupling of them to complimentary pairs of input/output (I/O) wires or lines. The I/O wires pass the amplified voltage signals to the data-out circuitry222and eventually to the data bus202. The data-out circuitry222may include a data driver (not shown) to drive data out onto the data bus202in response to a read request directed to the memory array208. Further, the data-out circuitry222may include a data latch (not shown) to latch the read data until the data driver drives it onto the data bus202.

In exchanging data, the column-address buffers214, the row-address buffers210, the data-in circuitry220, the data-out-circuitry222, address buffers230, and data buffers232may utilize buffers to delay, regenerate and store data signals communicated between the various components. These buffers may include various types of buffers. However, as discussed above, problems with signal integrity may result from noise that alters the signal in some types of buffers. Further, some types of buffers may operate slower, which would be disadvantageous for high-speed operation.

Accordingly, one buffering technique that may be utilized is a differential buffer. In a differential buffer, a data signal and its compliment are utilized to provide faster sensing of changes in the data signal. This approach provides for faster data sensing because the data signals are complimentary signals. Accordingly, a differential buffer with a current mirror generated current source may be utilized. However, in this design, the current mirror generated current source may limit the current produced from the output terminals of the differential buffer. However, it may have problems with power consumption because the current mirror generated current source may provide a static level of current dissipation and may be loaded with either FET or resistor devices. As can be appreciated, it may be advantageous to reduce or eliminate the static current dissipation.

To provide higher performance data buffering, a differential buffer or device may include additional circuitry to reduce the power consumption and maintain signal integrity for high-speed operations. For instance, the differential buffer may include a diode biased differential pair with adjustment circuitry, such as adjustment transistors, to provide current dissipation adjustability. In addition, the differential buffer may include a current mode common mode control circuit. The current mode common mode control circuit may include current pulse circuitry, such as pulse transistors, that provide a current pulse that is coincident with the switching of the output signals of the differential pair and grounding circuitry, such as grounding transistors, that times the switching of a current pulse to match the transition of the output signals from the differential pair. The differential buffer, which may be implemented in column-address buffers214, row-address buffers210, data-in circuit220, data-out-circuit222, address buffers230and/or data buffers232, is described in greater detail with reference toFIG. 4.

As previously discussed, the improved differential buffer may also be implemented in the ASIC118.FIG. 3shows an exemplary application specific integrated circuit (ASIC) in the processor-based device ofFIG. 1that may utilize embodiments of the differential buffer. The description of the ASIC118has been simplified for illustrative purposes and is not intended to be a complete description of each feature in the ASIC118. Differential buffers in accordance with the present technique, which are described inFIG. 4, may be utilized in clock buffer310, a first input/output (I/O) buffer318, a second I/O buffer320, a first logic buffer322, and/or a second logic buffer324, as discussed below. As such, various devices may implement the differential buffers in accordance with aspects of the present technique to hold or delay data signals and to regenerate data signals for high-speed operations.

The ASIC118may include a first core logic304and second core logic306, which are utilized to perform specific tasks. For instance, the first and second core logic304and306may be utilized as complementary metal-oxide semiconductor (CMOS) image sensors to provide high-resolution video capabilities. These CMOS image sensors may be utilized in cellular telephones, medical procedures, automobiles safety systems, and/or high-performance security cameras. Further, the first core logic304may be a command decoder/scheduler block and the second core logic306may be a memory controller block. As a command decoder/scheduler block, the first core logic304may interpret and schedule externally received commands, which are then formatted to be executed by the second core logic306. The second core logic306would issue commands to an I/O blocks to transmit and/or receive data signals. Alternatively, first core logic304may also be a processor or a microcontroller that issues commands/requests to the second core logic306, which may be a chip-to-chip interface control block. The second core logic306may utilize PCI, PCI Express, or hypertransport to communicate with the appropriate I/O block.

Various inputs and signals may be utilized by the core logic304and306to perform specific functions and communicate with other devices and circuitry. For instance, a clock source308may be utilized to provide clock signals to the first core logic304and various other components within the ASIC118. The clock signals may be provided to clock buffers310to synchronize the clock signals throughout the ASIC118. Also, individual inputs, such as control information and data, may be provided via a data bus or lines302to the ASIC118from other devices, such as the processor102and the memory device116ofFIG. 1. To interact with other devices, a first I/O block312, a second I/O block314and a third I/O block316may be utilized as an interface between external devices and the first core logic304and/or the second core logic306. Alternatively, the ASIC118may interface with other devices, such as a memory controller, a microcontroller, or another electronic system.

During operation, signals exchanged between the components of the ASIC118may utilize different buffers to temporarily hold or regenerate data signals. These buffers may include the clock buffers310, a first input/output buffer318, a second I/O buffer320, a first logic buffer322, and/or a second logic buffer324, which may include differential buffers. As an example, the I/O blocks312and314, along with the first core logic304, may receive clock signals from the clock buffer310to synchronize the exchange of data signals. Similarly, the I/O blocks312and314, along with the second core logic306, may utilize the buffers318,320and322, respectively, to communicate with the first core logic304. Finally, the second core logic306may utilize the second logic buffer324to communicate with the third I/O block316. Each of these buffers310,318,320,322and324may be utilized to synchronize and regenerate data signals that are exchanged between the various logic devices internal to the ASIC118.

As discussed above, typical buffers may have problems with signal integrity that results from noise on the signals, which may alter the signal, and with excessive power consumption. As can be appreciated, a differential buffer may include a diode biased differential pair with adjustment circuitry and a current mode common mode control circuit that has current pulse circuitry and grounding circuitry to reduce the power consumption and maintain signal integrity for high-speed operations. These differential buffers, which may be implemented in clock buffers310, a first input/output buffer318, a second I/O buffer320, a first logic buffer322, and/or a second logic buffer324, are described in greater detail inFIG. 4.

Beneficially, the present differential buffers utilize a differential signaling technology to support high-speed operations. Unlike other differential buffers that provide a static level of dissipation, the present embodiment of a differential buffer reduces or even eliminates the static current dissipation found in traditional differential buffers. In the exemplary embodiment shown inFIG. 4, a negative-channel metal-oxide semiconductor (NMOS) differential pair with a positive-channel metal-oxide semiconductor (PMOS) load is illustrated. However, this differential buffer may alternatively be constructed with PMOS devices to address a low voltage potential instead of a high voltage potential. An exemplary embodiment of a differential buffer is explained in greater detail below with reference toFIG. 4.

FIG. 4illustrates a schematic diagram of an exemplary embodiment of a differential buffer used in the memory device ofFIG. 2and the ASIC ofFIG. 3in accordance with aspects of the present technique. The differential buffer400may be divided into a first stage402that provides current adjustability for the differential buffer400and a second stage404that sets the output swing of the differential buffer400. Beneficially, by utilizing these two stages402and404, the differential buffer400provides low or no static current dissipation with the enhanced benefits of improved signal integrity related to using differential signaling for high-speed circuit operation. Accordingly, the differential buffer400may be utilized in the memory device116and the ASIC118ofFIGS. 2-3.

The first stage402of the differential buffer400may include a diode biased differential pair, such as a first transistor418and a second transistor424, along with adjustment circuitry, such as a first adjustment transistor406and a second adjustment transistor408, to provide the static current adjustability for the differential buffer400. The first and second adjustment transistors406and408provide the ability to adjust the output swing level and adjust the amount of static current dissipation for the differential buffer400. Also, the first and second adjustment transistors406and408may be turned “off” or eliminated to have zero static current draw. Accordingly, the first and second adjustment transistors406and408provide a designer with some control over how much supply bounce is created during a transition of the output buffer from low to high or high to low with a corresponding increase in the amount of static current dissipation. In addition, the first stage402may include a bias device or circuitry, such as the first dissipation transistor432and the second dissipation transistor434. These dissipation transistors432and434may be utilized to adjust the voltage level at the drain of the differential pair. As such, the first stage402may reduce the current dissipated from the differential buffer400.

To operate, the first stage402of the differential buffer400may be coupled to input signals, such as the data signal DATA1and the complimentary data signal DATA2. The first stage402may provide an output signal OUTPUT1and a complimentary output signal OUTPUT2. The input signals are delivered to the input terminals of the first stage402, which include a first input terminal410and a second input terminal412. The first stage402may utilize the input signals, such as data signals DATA1and DATA2, which are received at the input terminals410and412to produce output signals OUTPUT1and OUTPUT2at a first output terminal414and a second output terminal416.

To provide the output signals, the first and second input terminals410and412are coupled to various transistors in the first stage402. For instance, the first input terminal410is connected to a gate of a first transistor418and a gate of a second transistor420via a node422, while the second input terminal506is connected to a gate of a third transistor424and a gate of a fourth transistor426via a node428. The first transistor418may be coupled in series between the second transistor420, the first adjustment transistor406, and output terminal416connected at a node430and a first dissipation transistor432, a gate of a second dissipation transistor434and the third transistor424at a node436. The second transistor420and the first adjustment transistor406, which are coupled in parallel, are coupled in series between a first voltage source Vccand the node430. Further, the first dissipation transistor432and the second dissipation transistor434are coupled in series between the node436and the second voltage source Vssalong with gates to the first and second adjustment transistors406and408at a node440. The second voltage source Vssmay be ground or a voltage source of lower potential than the first voltage source Vcc. The third transistor424may be coupled in series between the fourth transistor426, the second adjustment transistor408, and the second output terminal414via a node442and the first dissipation transistor432via the node436. The fourth transistor426and the second adjustment transistor408, which are coupled in parallel, are coupled in series between the first voltage source Vccand the node442.

In an exemplary embodiment of the first stage402, the various transistors may be PMOS and NMOS transistors. For instance, the first transistor418, the third transistor424, the first dissipation transistor432and the second dissipation transistor434may be NMOS transistors, while the second transistor420, fourth transistor426, first adjustment transistor406, and second adjustment transistor408may be PMOS transistors.

From the first stage402, three general types of signals may be produced. First, if the voltage applied to the first input terminal410is “high” and the voltage applied to the second input terminal412is “low,” then the signal on the first output terminal414is “high” and the signal at the second output terminal416is “low”, because more current flows across the fourth transistor426. Secondly, if the voltage applied to the first input terminal410is “low” and the voltage applied to the second input terminal412is “high,” then the signal on the first output terminal414is “low”, and the signal on the second output terminal416is “high”, because more current flows across the second transistor420. Finally, if the voltages applied to the first input terminal410and to the second input terminal412are both “low” or both “high,” then the signals on the first output terminal414and the second output terminal416are “indeterminate,” because the current flow across the second transistor420and the fourth transistor426is approximately equal. In this final situation, the signal at the output terminals414and416is neither “low” nor “high,” but is “indeterminate” because it is between the two levels. Accordingly, the second stage402may be utilized to bias the current produced from the output terminals414and416, as discussed further below.

The second stage404of the differential buffer400may be a current controlled common mode voltage control circuit. The second stage404may be utilized with the first and second adjustment transistors406and408to set the output swing of the differential buffer400. The second stage404of the differential buffer400may be coupled to the node422, node428, node436, the first voltage source Vccand the second voltage source Vssof the first stage402to operate. In this second stage404, current pulse circuitry, which may include a first pulse transistor444, a second pulse transistor446, a third pulse transistor448, and a fourth pulse transistor450, may be utilized to provide a current pulse, which is coincident with the switching of the output signals in the differential pair. Further, grounding circuitry, such as a first grounding transistor452, a second grounding transistor454, a third grounding transistor456, a fourth grounding transistor460, and a fifth grounding transistor462, may be utilized to prevent the current from the differential pair from forcing the output signals to shift during a transition. This current pulse is mirrored to a bias device, such as first dissipation transistor432, to control the voltage level at the drain of the first dissipation transistor432. That is, the second stage404times the switching of the current pulse to match the transition of the output signal of the differential pair (i.e., the first transistor418and third transistor424). Beneficially, this type of circuitry supports high drive capabilities.

To operate the second stage404, the node422, node428, node436, first voltage source Vccand second voltage source Vssare coupled to various transistors in the second stage404. For instance, a gate of the first pulse transistor444, a gate of the second pulse transistor446, and a gate of a second grounding transistor454may receive signals from the node428, while a gate of the third pulse transistor448, a gate of the fourth pulse transistor450, and a gate of a fourth grounding transistor460may receive signals from the node422. The first pulse transistor444may be coupled in series between the second pulse transistor446that is coupled to the first voltage source Vccand a gate and source/drain of a first grounding transistor452, a second grounding transistor454, a gate of a third grounding transistor456, and a fourth grounding transistor460at a node458. The third pulse transistor448may be coupled in series between the fourth pulse transistor450that is coupled to the first voltage source Vccand the transistors coupled to the node458. Further, the first grounding transistor452is coupled in series with the fifth grounding transistor462that is coupled to the second voltage source Vss. A gate for the fifth grounding transistor462is coupled between the first grounding transistor452and the fifth grounding transistor462at a node464. Also, the second grounding transistor454and the fourth grounding transistor460, which are coupled in parallel, are coupled in series between the node458and the second voltage source Vss. Finally, the third grounding transistor456is coupled in series between the node428and the second voltage source Vss.

Within the second stage404, the various transistors may be PMOS and NMOS transistors. For instance, the first pulse transistor444, third pulse transistor448, first grounding transistor452, second grounding transistor454, third grounding transistor456, fourth grounding transistor460, and a fifth grounding transistor462may be NMOS transistors, while the second pulse transistor446and fourth pulse transistor450may be PMOS transistors. To operate the second stage404, the data signals DATA1and DATA2, which are complimentary signals, may be applied to the input terminals410and412. Based on the data signals DATA1and DATA2, the current drawn by the first transistor418and the third transistor424may spike during an output signal transition of output signals OUTPUT1and OUTPUT2. Similarly, the second pulse transistor446may also have a current spike during the transition of output signals OUTPUT1and OUTPUT2. This additional current is provided to the first grounding transistor452, which results in a current pulse on the third grounding transistor456. The current on the third grounding transistor456prevents the current on the first and third transistors418and424from forcing the output voltage to shift during a transition. The operation and interaction of the first and second stages402and404may be further understood with reference to the timing diagrams inFIGS. 5A-5E.

TheFIGS. 5A-5Eillustrate a group of graphs depicting current verses time for different transistors within the first and second stages402and404of the differential buffer400. These graphs depict the current draws of different transistors based on the data signals DATA1and DATA2and resulting output signals OUTPUT1and OUTPUT2in the differential buffer400. The different current draws occur at transition times, such as transition times TP1-TP10, when the output signals change from a “low” to “high” value or a “high” to “low” value. The “low” value may indicate a low current amount or voltage level, while the “high” value may represent a higher current value or voltage level. Accordingly, each of the graphs include the transition times TP1-TP10, which correspond to the transition period for the output signals. As such,FIGS. 5A-5Emay further describe the operation of the transistors in the first stage402and the second stage404of the differential buffer400, which may be best understood in conjunction withFIG. 4.

InFIG. 5A, a graph, which is herein referred to by reference numeral500and labeled “First Output Current,” corresponds to the current draw from the first voltage source Vccby the fourth transistor426at different periods of time. In this graph500, a first output current502is shown at a base current level Ib1with different current spikes to a spike current level IP1. The current spikes, such as a current spike504, occur during a transition of the output signal OUTPUT1from a “low” value to a “high” value during the transition times TP1, TP3, TP5, TP7and TP9. Particularly, the current spike504represents the current draw of the fourth transistor426during a transition of the output signal OUTPUT1at the transition time TP1. The output signal OUTPUT1transitions based on the changes in the data signal DATA1, which transitions between a “low” value and a “high” value.

Similarly, inFIG. 5B, a graph, which is herein referred to by reference numeral506and labeled “Second Output Current,” corresponds to the current draw from the first voltage source Vccby the second transistor420at different periods of time. In this graph506, a second output current508is shown with a base current level Ib2and current spike levels IP2. The current spikes, such as a current spike510, occur during a transition of the output signal OUTPUT2from a “low” value to a “high” value during the transition times TP2, TP4, TP6, TP8and TP10. Specifically, this current spike510represents the current draw of the second transistor420during a transition of the output signal OUTPUT2at a second transition time TP2. The output signal OUTPUT2transitions based on the changes in the data signal DATA2, which transitions between a “low” value and a “high” value.

InFIG. 5C, a graph, which is herein referred to by reference numeral512and labeled “Second Pulse Current,” corresponds to the current draw from the first voltage source Vccby the second pulse transistor446at different periods of time. In this graph512, a second pulse current514is shown with a base current level Ib3and different current spike levels IP3. The current spikes, such as a current spike516, occur during a transition of the output signal OUTPUT1at the transition times TP1, TP3, TP5, TP7and TP9. Specifically, the current spike516represents the current draw of the top of the common mode control mirror or current pulse circuitry, which is the second pulse transistor446, during the transition time TP1. Accordingly, the second pulse current514has a current spike each time the fourth transistor426has a current spike, which is discussed above inFIG. 5A. As can be appreciated, the fourth pulse transistor450may have similar current spikes for transition times TP2, TP4, TP6, TP8and TP10, which are associated with current spikes of the second transistor420, as well. As such, the current pulse circuitry may provide the grounding circuitry with a current pulse for each of the transition times TP1-TP10.

InFIG. 5D, a graph, which is herein referred to by reference numeral518and labeled “First Grounding Current,” corresponds to the current received from the second pulse transistor446and the fourth pulse transistor450at different periods of time. In this graph518, a first grounding current520is shown with a base current level Ib4and current spike levels IP4. The current spikes, such as a current spike522, occur during a transition of either of the output signals OUTPUT1and OUTPUT2during each of the transition times TP1-TP10. Specifically, the current spike516represents the current provides to the first grounding transistor452from the second pulse transistor446during the transition time TP1. Accordingly, the first grounding current520has a current spike with every transition of the output signals, which is provided to the third grounding transistor456, as discussed inFIG. 5E.

InFIG. 5E, a graph, which is herein referred to by reference numeral524and labeled “Third Grounding Current,” corresponds to the current at the third grounding transistor456at different periods of time. In this graph524, a third grounding current526is shown with a base current level Ib5and different current spike levels IP5. The current spikes, such as a current spike528, occur during a transition of either of the output signals OUTPUT1and OUTPUT2during each of the transition times TP1-TP10, which is similar to the current spikes on the first grounding transistor452. The current spikes are a result of the current provided to the first grounding transistor452and are utilized to prevent the current from the second and fourth transistors420and426from forcing the output signals to shift during the transition times TP1-TP10.

Beneficially, the second stage404may be utilized to prevent the current generated during transitions in the first stage402from causing output shifts. Specifically, by configuring the pulse circuitry, such as transistors444,446,448, and450, along with the grounding circuitry, such as transistors452,454,456,462and464, to generate a current during the transitions, the second stage402may be utilized to prevent the output voltages from shifting during transitions. As a result, the low or no static current dissipation may be utilized to conserve power and maintain signal integrity within the differential buffer.

In addition, the differential buffer400may be altered to provide some additional control over the adjustment circuitry. With reference toFIG. 4, the gates of the first adjustment transistor406and the second adjustment transistor408may receive control signals from other circuitry to control the adjustment circuitry. For example, the gates of the first adjustment transistor406and the second adjustment transistor408may be coupled to another input terminal in the differential buffer. This may allow circuitry outside of the differential buffer to adjust the adjustment transistors406and408. Also, the gates of the first adjustment transistor406and the second adjustment transistor408may be coupled to other circuitry within the differential buffer that may provide controls signals to operate the adjustment transistors406and408. Thus, the adjustment circuitry may be controlled by other circuitry to provide control over the differential buffer400.

Further, it should be appreciated that the transistors inFIG. 4may be biased by a voltage, such as the first voltage source Vccor the second voltage source Vss. For instance, the adjustment transistors406and408, second transistor420, fourth transistor426, second pulse transistor446and fourth pulse transistor450may be biased by the first voltage source Vcc. Also, the first transistor418, second transistor424, first dissipation transistors432, second dissipation transistors434, first pulse transistor444, third pulse transistor448, and the grounding transistors452,454,456,460and462may be biased by the second voltage source Vss. Thus, each of the transistors may be biased to improve the performance of the differential buffer400.