STRUCTURE FOR BACKSIDE SIGNAL AND POWER

According to the embodiment of the present invention, a semiconductor device includes a first nanodevice comprised of a plurality of first transistors and a second nanodevice comprised of a plurality of second transistors. The second nanodevice is located adjacent to and parallel to the first nanodevice along an x-axis. A first backside signal line and a second backside signal line are located at a cell boundary of the first nanodevice. A first gap exists between the first backside signal line and the second backside signal line.

BACKGROUND

The present invention relates generally to the field of microelectronics, and more particularly to a semiconductor device structure, and a method for forming a semiconductor device.

A nanosheet (NS) is the lead device architecture in continuing CMOS scaling. However, nanosheet technology has shown issues when scaling down such that as the devices become smaller and closer together, they are interfering with each other. Furthermore, as the devices become smaller and closer together, forming the connections to a backside power network is becoming more difficult.

SUMMARY

According to the embodiment of the present invention, a semiconductor device includes a first nanodevice comprised of a plurality of first transistors and a second nanodevice comprised of a plurality of second transistors. The second nanodevice is located adjacent to and parallel to the first nanodevice along an x-axis. A first backside signal line and a second backside signal line are located at a cell boundary of the first nanodevice. A first gap exists between the first backside signal line and the second backside signal line.

According to the embodiment of the present invention, a width of the first gap parallel to the x-axis is from 5 nanometers (nm) to 100 nm.

According to the embodiment of the present invention, the semiconductor device further comprises a first backside power rail (BPR) located adjacent to and parallel to the first backside signal line and the second backside signal line along the x-axis. A width of the first BPR parallel to the x-axis is greater than a width of the first backside signal line and the second backside signal line parallel to the x-axis.

According to the embodiment of the present invention, the semiconductor device further comprises a second BPR located adjacent to and parallel to the first BPR along the x-axis. A width of the second BPR parallel to the x-axis is equivalent to the width of the first BPR parallel to the x-axis.

According to the embodiment of the present invention, the width of the first backside signal line and the second backside signal line parallel to the x-axis is 20 nm.

According to the embodiment of the present invention, the width of the first BPR and the second BPR parallel to the x-axis is 40 nm.

According to the embodiment of the present invention, a semiconductor device includes a first nanodevice comprised of a plurality of first transistors and a second nanodevice comprised of a plurality of second transistors. The second nanodevice is located adjacent to and parallel to the first nanodevice along an x-axis. A first backside signal line and a second backside signal line are located at a cell boundary of the first nanodevice. A first gap exists between the first backside signal line and the second backside signal line. A third backside signal line and a fourth backside signal line are located at a cell boundary of the second nanodevice. A second gap exists between the third backside signal line and the fourth backside signal line.

According to the embodiment of the present invention, a width of the first gap parallel to the x-axis is from 5 nm to 100 nm. A width of the second gap parallel to the x-axis is equivalent to the width of the first gap parallel to the x-axis.

According to the embodiment of the present invention, the semiconductor device further comprises a first BPR and a second BPR located between the first backside signal line, the second backside signal line, the third backside signal line, and the fourth backside signal line. A width of the first BPR and the second BPR parallel to the x-axis is greater than a width of the first backside signal line, the second backside signal line, the third backside signal line, and the fourth backside signal line parallel to the x-axis.

According to the embodiment of the present invention, the first BPR, the second BPR, the first backside signal line, the second backside signal line, the third backside signal line, and the fourth backside signal line are substantially in a same plane.

According to the embodiment of the present invention, the width of the first backside signal line, the second backside signal line, the third backside signal line, and the fourth backside signal line parallel to the x-axis is 20 nm.

According to the embodiment of the present invention, the width of the first BPR and the second BPR parallel to the x-axis is 40 nm.

According to the embodiment of the present invention, the semiconductor device further comprises a source/drain contact including a via (VBPS). The VBPS extends downwards to connect to a frontside of the third backside signal line.

According to the embodiment of the present invention, a source/drain is in direct contact with a backside of the source/drain contact. The third backside signal line is connected to the source/drain by the VBPS.

According to the embodiment of the present invention, a semiconductor device includes a first nanodevice comprised of a plurality of first transistors and a second nanodevice comprised of a plurality of second transistors. The first nanodevice includes a first BPR. The second nanodevice includes a second BPR. The second nanodevice is located adjacent to and parallel to the first nanodevice along an x-axis. A first backside signal line, a second backside signal line, and a third backside signal line extend perpendicular to the x-axis along a y-axis through the first nanodevice and the second nanodevice. The first backside signal line, the second backside signal line, and the third backside signal line overlap the first BPR and the second BPR along the y-axis.

According to the embodiment of the present invention, the third backside signal line bypasses the first BPR and the second BPR along the y-axis.

According to the embodiment of the present invention, the semiconductor device further comprises a fourth backside signal line located at a cell boundary of the first nanodevice and a fifth backside signal line located at a cell boundary of the second nanodevice.

According to the embodiment of the present invention, the first backside signal line, the second backside signal line, the third backside signal line, the fourth backside signal line, and the fifth backside signal line are substantially in a same plane.

According to the embodiment of the present invention, the first BPR and the second BPR lie in a different plane than the first backside signal line, the second backside signal line, the third backside signal line, the fourth backside signal line, and the fifth backside signal line.

According to the embodiment of the present invention, a length of the first backside signal line, the second backside signal line, the third backside signal line, the fourth backside signal line, and the fifth backside signal line parallel to the y-axis is from 25 nm to 500 nm.

DETAILED DESCRIPTION

As used herein, the term “about” modifying the quantity of an ingredient, component, or reactant of the invention employed refers to variation in the numerical quantity that can occur, for example, through typical measuring and liquid handling procedures used for making concentrations or solutions. Furthermore, variation can occur from inadvertent error in measuring procedures, differences in manufacture, source, or purity of the ingredients employed to make the compositions or carry out the methods, and the like. The terms “about” or “substantially” are intended to include the degree of error associated with measurement of the particular quantity based upon the equipment available at the time of the filing of the application. For example, about can include a range of ±8%, or 5%, or 2% of a given value. In another aspect, the term “about” means within 5% of the reported numerical value. In another aspect, the term “about” means within 10, 9, 8, 7, 6, 5, 4, 3, 2, or 1% of the reported numerical value.

Various processes which are used to form a micro-chip that will be packaged into an integrated circuit (IC) fall in four general categories, namely, film deposition, removal/etching, semiconductor doping and patterning/lithography. Deposition is any process that grows, coats, or otherwise transfers a material onto the wafer. Available technologies include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and more recently, atomic layer deposition (ALD) among others. Removal/etching is any process that removes material from the wafer. Examples include etching process (either wet or dry), reactive ion etching (RIE), and chemical-mechanical planarization (CMP), and the like. Semiconductor doping is the modification of electrical properties by doping, for example, transistor sources and drains, generally by diffusion and/or by ion implantation. These doping processes are followed by furnace annealing or by rapid thermal annealing (RTA). Annealing serves to activate the implant dopants. Films of both conductors (e.g., aluminum, copper, etc.) and insulators (e.g., various forms of silicon dioxide, silicon nitride, etc.) are used to connect and isolate electrical components. Selective doping of various regions of the semiconductor substrate allows the conductivity of the substrate to be changed with the application of voltage.

Reference will now be made in detail to the embodiments of the present invention, examples of which are illustrated in the accompanying drawings, where like reference numerals refer to like elements throughout.

When a via to the backside power rail (VBPR) extends downwards from a frontside contact the VBPR may be located between two active regions on a nanodevice. The downwards extending VBPR is connected to a component, for example, a backside power rail. Therefore, backside wiring is currently only used for power distribution. Utilizing the backside wiring in this manner results in a larger cell size.

By inserting a power distribution network containing power rails and signal lines on the backside of a nanodevice, the cell size may be reduced. Additionally, by arranging the backside power rails and signal lines on different backside metal levels of the nanodevice, more wiring tracks may be freed on an upper metal level. The present invention does not require that all advantages need to be incorporated into every embodiment of the invention.

The present invention is directed to forming backside power rails and signal lines in substantially a same plane across a circuit row such that the signal lines are located at cell boundaries and a via connects a source/drain contact to a backside signal line and a backside contact connects a backside power rail to a source/drain. The backside power rails and signal lines are formed through a multistage processing, where the first stage forms a first trench by removing a sacrificial backside contact placeholder made of SiGe. The second stage fills the first trench with a conductive metal, forming the backside contact. The third stage forms the backside power rails and signal lines within a backside interlayer dielectric layer in substantially the same plane. The fourth stage forms the backside interconnect above the backside power rails and signal lines and the backside interlayer dielectric layer.

FIG.1illustrates a top-down view of a plurality of nanodevices ND1, ND2, in accordance with the embodiment of the present invention. The adjacent and parallel devices along the x-axis include a first nanodevice ND1comprised of a plurality of first transistors, and a second nanodevice ND2comprised of a plurality of second transistors. Cross-section X is a cross section perpendicular to the gates along the horizontal axis of the second nanodevice ND2. Cross-section Y1is a cross section parallel to the gates in the source/drain region102across the plurality of nanodevices ND1, ND2. Cross-section Y2is a cross section parallel to the gates in a different source/drain region104across the plurality of nanodevices ND1, ND2. It may be appreciated that the embodiment of the present invention is not limited to nanodevices ND1, ND2and that other devices including, but not limited to, FinFET, nanowire, and a planar device may also be used.

FIGS.2-4illustrate cross sections X, Y1, and Y2, respectively, of the plurality of nanodevices ND1, ND2after nanosheet120,130,140formation, shallow trench isolation (STI) region114formation, dummy gate145formation, gate hard mask150formation, and etch stop layer110formation, in accordance with the embodiment of the present invention. The plurality of nanodevices ND1, ND2include a substrate105, an etch stop layer110, an underlying substrate layer112, an STI region114, a first sacrificial layer115, a second sacrificial layer118, a first nanosheet120, a third sacrificial layer125, a second nanosheet130, a fourth sacrificial layer135, a third nanosheet140, a dummy gate145, and a gate hard mask150. The substrate105and the etch stop layer110can be, for example, a material including, but not necessarily limited to, silicon (Si), silicon germanium (SiGe), Si: C (carbon doped silicon), carbon doped silicon germanium (SiGe: C), III-V, II-V compound semiconductor or another like semiconductor. In addition, multiple layers of the semiconductor materials can be used as the semiconductor material of the substrate105. In some embodiments, the substrate105includes both semiconductor materials and dielectric materials. The semiconductor substrate105may also comprise an organic semiconductor or a layered semiconductor such as, for example, Si/SiGe, a silicon-on-insulator or a SiGe-on-insulator. A portion or the entire semiconductor substrate105may also be comprised of an amorphous, polycrystalline, or monocrystalline. The semiconductor substrate105and the etch stop layer110may be doped, undoped or contain doped regions and undoped regions therein.

The first sacrificial layer115is formed directly atop the underlying substrate layer112. The second sacrificial layer118is formed directly atop the first sacrificial layer115. The first nanosheet120is formed directly atop the second sacrificial layer118. The third sacrificial layer125is formed directly atop the first nanosheet120. The second nanosheet130is formed directly atop the third sacrificial layer125. The fourth sacrificial layer135is formed directly atop the second nanosheet130. The third nanosheet140is formed directly atop the fourth sacrificial layer135. The dummy gate145is formed directly atop the third nanosheet140. The gate hard mask150is formed directly atop the dummy gate145. The first sacrificial layer115, the second sacrificial layer118, the third sacrificial layer125, and the fourth sacrificial layer135are hereinafter referred to as the plurality of sacrificial layers115,118,125,135. In addition, the first nanosheet120, the second nanosheet130, and the third nanosheet140are hereinafter referred to as the plurality of nanosheets120,130,140. The plurality of sacrificial layers115,118,125,135may be comprised of, for example, SiGe, where Ge is about 35%. The plurality of nanosheets120,130,140may be comprised of, for example, Si. The number of nanosheets and the number of sacrificial layers described above are not intended to be limiting, and it may be appreciated that in the embodiment of the present invention the number of nanosheets and the number of sacrificial layers may vary. After formation of the plurality of nanosheets120,130,140and the plurality of sacrificial layers115,118,125,135, together the nanosheet stack, the nanosheet stack (comprising alternative Si and SiGe layers over a bottom most high Ge % SiGe layer) may be further patterned using conventional lithography and etching processes. After nanosheet stack formation and patterning, the STI region114is formed by dielectric filling, CMP, and dielectric recess.

FIGS.5-7illustrate cross sections X, Y1, and Y2, respectively, of the plurality of nanodevices ND1, ND2after gate spacer160formation, bottom dielectric isolation (BDI) layer155formation, and reactive ion etching (RIE), in accordance with the embodiment of the present invention. The bottom most high Ge % SiGe layer is selectively removed, followed by gate spacer160and BDI layer155formation by a conformal dielectric liner deposition followed by anisotropic etch. InFIG.5, the BDI layer155is located directly atop the underlying substrate layer112.

FIGS.8-10illustrate cross sections X, Y1, and Y2, respectively, of the plurality of nanodevices ND1, ND2after inner spacer165formation, in accordance with the embodiment of the present invention. The nanosheet stack at the S/D regions102,104are recessed, followed by indentation of sacrificial SiGe and inner spacer165formation. InFIGS.9-10, the BDI layer155is located directly atop the underlying substrate layer112and between two inner spacers165. The two inner spacers165and the BDI layer155form a contiguous unitary structure made of the same or a different dielectric material.

FIGS.11-13illustrate cross sections X, Y1, and Y2, respectively, of the plurality of nanodevices ND1, ND2after the formation of a sacrificial backside contact placeholder170, in accordance with the embodiment of the present invention. A portion of the BDI layer155and the underlying substrate layer112are selectively removed and a material (e.g., SiGe) is deposited in a space created by the removal of the portion of the BDI layer155and the underlying substrate layer112to form the sacrificial backside contact placeholder170.

FIGS.14-16illustrate cross sections X, Y1, and Y2, respectively, of the plurality of nanodevices ND1, ND2after interlayer dielectric (ILD)185deposition, CMP, and gate175formation and source/drain180A,180B,180C,180D,180E formation, in accordance with the embodiment of the present invention. The first source/drain180A, the second source/drain180B, the third source/drain180C, the fourth source/drain180D, and the fifth source/drain180E are epitaxially grown over exposed sidewalls of the plurality of nanosheets120,130,140, followed by ILD185deposition and CMP to remove the gate hard mask150and the dummy gate145. Then, the sacrificial SiGe are removed, followed by gate175formation. The first source/drain180A, the second source/drain180B, the fourth source/drain180D, and the fifth source/drain180E are formed directly atop the BDI layer155. The third source/drain180C is formed directly atop the sacrificial backside contact placeholder170. The first source/drain180A, the fourth source/drain180D, and the fifth source/drain180E are surrounded on three sides by the contiguous unitary structure.

The first source/drain180A, the second source/drain180B, the third source/drain180C, the fourth source/drain180D, and the fifth source/drain180E can be for example, a n-type epitaxy, or a p-type epitaxy. For n-type epitaxy, an n-type dopant selected from a group of phosphorus (P), arsenic (As) and/or antimony (Sb) can be used. For p-type epitaxy, a p-type dopant selected from a group of boron (B), gallium (Ga), indium (In), and/or thallium (Tl) can be used. Other doping techniques such as ion implantation, gas phase doping, plasma doping, plasma immersion ion implantation, cluster doping, infusion doping, liquid phase doping, solid phase doping, and/or any suitable combination of those techniques can be used. In some embodiments, dopants are activated by thermal annealing such as laser annealing, flash annealing, rapid thermal annealing (RTA) or any suitable combination of those techniques.

InFIG.14, the ILD185is formed directly atop the first source/drain180A, the second source/drain180B, and the third source/drain180C and surrounds one side of the gate spacer155. InFIG.15, the ILD185is formed directly atop the first source/drain180A, the fourth source/drain180D, the contiguous unitary structure, and the STI region114. InFIG.16, the ILD185is formed directly atop the third source/drain180C, the fifth source/drain180E, the contiguous unitary structure, and the STI region114.

InFIG.14, a gate material is deposited in the space created by the removal of the second sacrificial layer118, the third sacrificial layer125, and the fourth sacrificial layer135and directly atop the third nanosheet140to form a replacement gate (i.e., the gate175). The gate175can be comprised of, for example, a gate dielectric liner, such as a high-k dielectric like HfO2, ZrO2, HfLaOx, etc., and work function layers, such as TIN, TiAlC, TiC, etc., and conductive metal fills, like W.

FIGS.17-19illustrate cross sections X, Y1, and Y2, respectively, of the plurality of nanodevices ND1, ND2after the formation of a via to the backside signal (VBPS)195and a plurality of source/drain contacts190A,190B,190C, and190D, in accordance with the embodiment of the present invention. InFIG.17, an additional ILD187is formed directly atop the ILD185, the gate spacer160, and the gate175. The first source/drain contact190A is located directly atop the first source/drain180A. The second source/drain contact190B is located directly atop the second source/drain180B.

InFIG.18, the additional ILD187is formed directly atop the ILD185. The first source/drain contact190A is located directly atop the first source/drain180A. The third source/drain contact190C is located directly atop the fourth source/drain180D. A bottom surface of the VBPS195is in contact with the STI region114. A portion of the sidewalls of the VBPS195are in contact with the STI region114, the ILD185, or the ILD185and the first source/drain contact190A, respectively. Dashed box197illustrates the source/drain contact-VBPS link. The source/drain contact-VBPS link is located between the VBPS195and the first source/drain contact190A. The source/drain contact-VBPS link connects the first source/drain contact190A to the VBPS195.

InFIG.19, the additional ILD187is formed directly atop the ILD185. The fourth source/drain contact190D is located directly atop the fifth source/drain180E.

FIGS.20-22illustrate cross sections X, Y1, and Y2, respectively, of the plurality of nanodevices ND1, ND2after the formation of a back-end-of-line (BEOL) layer200and bonding to a carrier wafer205, in accordance with the embodiment of the present invention. The BEOL layer200may contain multiple metal layers and vias in between. InFIG.20, the BEOL layer200is formed directly atop the first source/drain contact190A, the second source/drain contact190B, and the additional ILD187. InFIG.21, the BEOL layer200is formed directly atop the first source/drain contact190A, the third source/drain contact190C, the VBPS195, the source/drain contact-VBPS link, and the additional ILD187. InFIG.22, the BEOL layer200is formed directly atop the fourth source/drain contact190D and the additional ILD187. InFIGS.20-22, the carrier wafer205is formed directly atop the BEOL layer200by bonding processes (e.g., oxide-oxide bonding).

FIGS.1-22illustrate the processing of the frontside of the substrate105, whileFIGS.23-57illustrate the processing of the backside of the substrate105.FIGS.23-25illustrate cross sections X, Y1, and Y2, respectively, of the plurality of nanodevices ND1, ND2after the carrier wafer205is flipped and the substrate105is removed, in accordance with the embodiment of the present invention. The carrier wafer205is flipped and the carrier wafer205becomes a handler wafer. The substrate105is removed by, for example, a combination of processes such as wafer grinding, CMP, and/or selective dry/wet etch, stopping on the etch stop layer110.

FIGS.26-28illustrate cross sections X, Y1, and Y2, respectively, of the plurality of nanodevices ND1, ND2after the removal of the etch stop layer110and the underlying substrate layer112, in accordance with the embodiment of the present invention. The etch stop layer110is removed to expose the underlying substrate layer112. The underlying substrate layer112is removed by, for example, a selective wet or dry etch process.

FIGS.29-31illustrate cross sections X, Y1, and Y2, respectively, of the plurality of nanodevices ND1, ND2after backside ILD (BILD) layer210deposition and CMP, in accordance with the embodiment of the present invention. InFIG.29, the BILD layer210is deposited directly atop the BDI layer155and the sacrificial backside contact placeholder170. InFIG.30, the BILD layer210is deposited directly atop the BDI layer155and the STI region114. InFIG.31, the BILD layer210is deposited directly atop the BDI layer155, the STI region114, and the sacrificial backside contact placeholder170. InFIGS.29-31, a portion of the BILD layer210is selectively removed by, for example, CMP. A top surface of the sacrificial backside contact placeholder170is exposed.

FIGS.32-34illustrate cross sections X, Y1, and Y2, respectively, of the plurality of nanodevices ND1, ND2after the formation of a trench215, in accordance with the embodiment of the present invention. The sacrificial backside contact placeholder170is removed by, for example, CMP to form the trench215. A bottom surface of the trench215exposes a top surface of the third source/drain180C.

FIGS.35-37illustrate cross sections X, Y1, and Y2, respectively, of the plurality of nanodevices ND1, ND2after the formation of a backside contact220and CMP, in accordance with the embodiment of the present invention. The trench215is filled with a conductive metal (e.g., including a silicide liner, such as Ni. Ti, NiPt, an adhesion metal liner, such as TiN and conductive metal fill, such as W, Co, or Ru) to form the backside contact220. Then, a portion of the BILD layer210and the STI region114are selectively removed by, for example, CMP to expose a top surface of the VBPS195and a top surface of the backside contact220.

FIGS.38-40illustrate cross sections X, Y1, and Y2, respectively, of the plurality of nanodevices ND1, ND2after the formation of a plurality of backside power rails (BPRs)225A,225B and backside signal lines230A,230B,230C,230D, in accordance with the embodiment of the present invention. The first BPR225A, the second BPR225B, the first backside signal line230A, the second backside signal line230B, the third backside signal line230C, and the fourth backside signal line230D are patterned using conventional lithography and etching processes, followed by metallization (e.g., Cu, Co or Ru fill with adhesion liner such as TiN).

InFIG.38, the first BPR225A is formed directly atop the BILD layer210and the backside contact220. A top surface of backside contact220is connected to the first BPR225A.

InFIG.39, an additional BILD layer227is deposited directly atop the BILD layer210, the VBPS195, and the STI region114. The first BPR225A and the second BPR225B are formed directly atop the BILD layer210. A bottom surface of the first BPR225A and the second BPR225B are in direct contact with the BILD layer210. The sidewalls of the first BPR225A and the second BPR225B are in direct contact with the additional BILD layer227. The first backside signal line230A is formed directly atop the STI region114. The second backside signal line230B is formed directly atop the VBPS195. A bottom surface of the second backside signal line230B is connected to the VBPS195. The first source/drain contact190A (i.e., the source/drain contact in the claims) includes the VBPS195. The VBPS195extends downwards to connect to a frontside of the second backside signal line230B (i.e., the third backside signal line in the claims). The first source/drain180A (i.e., the source/drain in the claims) is in direct contact with a backside of the first source/drain contact190A. The second backside signal line230B is connected to the first source/drain180A by the VBPS195. The sidewalls of the first backside signal line230A and the second backside signal line230B are in direct contact with the additional BILD layer227.

InFIG.40, the additional BILD layer227is deposited directly atop the BILD layer210, the backside contact220, and the STI region114. The first BPR225A is formed directly atop the backside contact220. The top surface of the backside contact220is connected to the first BPR225A. The second BPR225B is formed directly atop the BILD layer210. A bottom surface of the second BPR225B is in direct contact with the BILD layer210. The sidewalls of the first BPR225A and the second BPR225B are in direct contact with the additional BILD layer227. The third backside signal line230C and the fourth backside signal line230D are formed directly atop the STI region114. The sidewalls of the third backside signal line230C and the fourth backside signal line230D are in direct contact with the additional BILD layer227. InFIGS.39-40, the first BPR225A, the second BPR225B, and the plurality of backside signal lines230A,230B,230C,230D are substantially in a same plane.

FIG.41illustrates a top-down view of the plurality of nanodevices ND1, ND2after the formation of the VBPS195, the plurality of source/drain contacts190A,190B,190C,190D,190E, the backside contact220, the plurality of BPRs225A,225B, and the plurality of backside signal lines230A,230B,230C,230D, in accordance with the embodiment of the present invention.FIG.41is meant to illustrate the final structure of the semiconductor device. The second nanodevice ND2includes the first source/drain contact190A (i.e., the source/drain contact in the claims), the second source/drain contact190B, and the backside contact220. The first nanodevice ND1includes the third source/drain contact190C, the fourth source/drain contact190D, and a fifth source/drain contact190E. The second source/drain contact190B and the fifth source/drain contact190E are located between two gates175. The first BPR225A is located adjacent to and parallel to the first backside signal line230A and the third backside signal line230C along the x-axis. The second BPR225B is located adjacent to and parallel to the second backside signal line230B and the fourth backside signal line230D along the x-axis. The first backside signal line230A and the third backside signal line230C (i.e., the second backside signal line in the claims) are located at a cell boundary of the first nanodevice ND1. The second backside signal line230B (i.e., the third backside signal line in the claims) and the fourth backside signal line230D are located at a cell boundary of the second nanodevice ND2. The first BPR225A and the second BPR225B are located between the first backside signal line230A, the second backside signal line230B, the third backside signal line230C, and the fourth backside signal line230D. The first BPR225A, the second BPR225B, the first backside signal line230A, the second backside signal line230B, the third backside signal line230C, and the fourth backside signal line230D are substantially in a same plane.

A first gap G1 exists between the first backside signal line230A and the third backside signal line230C. A second gap G2 exists between the second backside signal line230B and the fourth backside signal line230D. A width of the first gap G1 parallel to the x-axis is from 5 nanometers (nm) to 100 nm. A width of the second gap G2 parallel to the x-axis is equivalent to the width of the first gap G1 parallel to the x-axis. A width WP1 of the first BPR225A and a width WP2 of the second BPR225B parallel to the x-axis is greater than a width WS1 of the first backside signal line230A, a width WS2 of the second backside signal line230B, a width WS3 of the third backside signal line230C, and a width WS4 of the fourth backside signal line230D parallel to the x-axis. The width WP1 of the first BPR225A parallel to the x-axis is equivalent to the width WP2 of the second BRR225B parallel to the x-axis. The width WP1 of the first BPR225A and the width WP2 of the second BRP225B parallel to the x-axis is from 40 nm to 2 microns. The width WS1 of the first backside signal line230A, the width WS2 of the second backside signal line230B, the width WS3 of the third backside signal line230C, and the width WS4 of the fourth backside signal line230D parallel to the x-axis is from 20 nm to 400 nm.

FIGS.42-44illustrate cross sections X, Y1, and Y2, respectively, of the plurality of nanodevices ND1, ND2after the formation of a backside power distribution network (BSPDN)235, in accordance with the embodiment of the present invention. InFIG.42, the BSPDN235is formed directly atop the first BPR225A. InFIG.43, the BSPDN235is formed directly atop the additional BILD layer227, the first BPR225A, the second BPR225B, the first backside signal line230A, and the second backside signal line230B. InFIG.44, the BSPDN235is formed directly atop the additional BILD layer227, the first BPR225A, the second BPR225B, the third backside signal line230C and the fourth backside signal line230D.

FIGS.45-47illustrate cross sections X, Y1, and Y2, respectively, of the plurality of nanodevices ND1, ND2after the formation of a backside contact420and CMP, in accordance with the embodiment of the present invention. The trench215is filled with a conductive metal (e.g., including a silicide liner, such as Ni. Ti, NiPt, an adhesion metal liner, such as TiN and conductive metal fill, such as W, Co, or Ru) to form the backside contact420. Then, a portion of the BILD layer410and the STI region314are selectively removed by, for example, CMP to expose a top surface of the VBPS395and a top surface of the backside contact420.

FIGS.48-50illustrate cross sections X, Y1, and Y2, respectively, of the plurality of nanodevices ND1, ND2after the formation of a plurality of BPRs425A,425B, in accordance with the embodiment of the present invention. The first BPR425A and the second BPR425B are patterned using conventional lithography and etching processes, followed by metallization (e.g., Cu, Co or Ru fill with adhesion liner such as TiN).

InFIG.48, the first BPR425A is formed directly atop the BILD layer410and the backside contact420. A top surface of backside contact420is connected to the first BPR425A.

InFIG.49, an additional BILD layer427is deposited directly atop the BILD layer410, the VBPS395, and the STI region314. The first BPR425A and the second BPR425B are formed directly atop the BILD layer410. A bottom surface of the first BPR425A and the second BPR425B are in direct contact with the BILD layer410. The sidewalls of the first BPR425A and the second BPR425B are in direct contact with the additional BILD layer427.

InFIG.50, the additional BILD layer427is deposited directly atop the BILD layer410, the backside contact420, and the STI region314. The first BPR425A is formed directly atop the backside contact420. The top surface of the backside contact420is connected to the first BPR425A. The second BPR425B is formed directly atop the BILD layer410. A bottom surface of the second BPR425B is in direct contact with the BILD layer410. The sidewalls of the first BPR425A and the second BPR425B are in direct contact with the additional BILD layer427.

FIGS.51-53illustrate cross sections X, Y1, and Y2, respectively, of the plurality of nanodevices ND1, ND2after the formation of a plurality of backside signal lines430A,430B,430C,430D and a skip via440, in accordance with the embodiment of the present invention. The first backside signal line430A, the second backside signal line430B, the third backside signal line430C, and the fourth backside signal line430D are patterned using conventional lithography and etching processes, followed by metallization (e.g., Cu, Co or Ru fill with adhesion liner such as TiN).

InFIG.51, a second additional BILD layer435is deposited directly atop the first BPR425A. The first backside signal line430A, the second backside signal line430B, and the third backside signal line430C are formed directly atop the second additional BILD layer435. A third additional BILD layer437is deposited directly atop the second additional BILD layer435and the first backside signal line430A, the second backside signal line430B, and the third backside signal line430C. At least one sidewall of the first backside signal line430A and the third backside signal line430C is in direct contact with the third additional BILD layer437. The sidewalls of the second backside signal line430B are in direct contact with the third additional BILD layer437.

InFIG.52, the second additional BILD layer435is deposited directly atop the first BPR425A, the second BPR425B, and the additional BILD layer427. The skip via440is located directly atop the VBPS395. A bottom surface of the skip via440is connected to the VBPS395. The first backside signal line430A is connected to the VBPS395by the skip via440. A portion of the sidewalls of the skip via440are in contact with the second additional BILD layer435, or the additional BILD layer427, respectively. The first backside signal line430A is formed directly atop the second additional BILD layer435and the skip via440. The VBPS395is connected to the first backside signal line430A by the skip via440. The third additional BILD layer437is deposited directly atop the second additional BILD layer435, the first backside signal line430A, and the fourth backside signal line430D. At least one sidewall of the first backside signal line430A and the fourth backside signal line430D is in direct contact with the third additional BILD layer437.

InFIG.53, the second additional BILD layer435is deposited directly atop the first BPR425A, the second BPR425B, and the additional BILD layer427. The third backside signal line430C is formed directly atop the second additional BILD layer435. The third additional BILD layer437is deposited directly atop the third backside signal line430C. The third backside signal line430C is located between the second additional BILD layer435and the third additional BILD layer437. The third backside signal line430C bypasses the first BPR425A and the second BPR425B along a y-axis.

FIG.54illustrates a top-down view of the plurality of nanodevices ND1, ND2after the formation of the VBPS395, the skip via440, the plurality of source/drain contacts390A,390B,390C,390D,390E, the backside contact420, the plurality of BPRs425A,425B, and the plurality of backside signal lines430A,430B,430C,430D,430E, in accordance with the embodiment of the present invention.FIG.54is meant to illustrate the final structure of the semiconductor device. The second nanodevice ND2includes the first source/drain contact390A, the second source/drain contact390B, and the backside contact420. The first nanodevice ND1includes the third source/drain contact390C, the fourth source/drain contact390D, and the fifth source/drain contact390E. The second source/drain contact390B and the fifth source/drain contact390E are located between two gates375. The second nanodevice ND2includes the first BPR425A (i.e., the second BPR in the claims). The first nanodevice ND1includes the second BPR425B (i.e., the first BPR in the claims). The first BPR425A is located adjacent and parallel to the second BPR425B along the x-axis. The first backside signal line430A, the second backside signal line430B, and the third backside signal line430C extend perpendicular to the x-axis along the y-axis through the first nanodevice ND1and the second nanodevice ND2. The first backside signal line430A, the second backside signal line430B, and the third backside signal line430C overlap the first BPR425A and the second BPR425B along the y-axis. The fourth backside signal line430D is located at a cell boundary of the first nanodevice ND1. The fifth backside signal line430E is located at a cell boundary of the second nanodevice ND2. The first backside signal line430A, the second backside signal line430B, the third backside signal line430C, the fourth backside signal line430D, and the fifth backside signal line430E are substantially in a same plane. The first BPR425A and the second BPR425B lie in a different plane than the first backside signal line430A, the second backside signal line430B, the third backside signal line430C, the fourth backside signal line430D, and the fifth backside signal line430E.

The length LS1 of the first backside signal line430A, the length LS2 of the second backside signal line430B, the length LS3 of the third backside signal line430C, the length LS4 of the fourth backside signal line430D, and the length LS5 of the fifth backside signal line430E perpendicular to the x-axis and parallel to the y-axis is from 25 nm to 500 nm.

FIGS.55-57illustrate cross sections X, Y1, and Y2, respectively, of the plurality of nanodevices ND1, ND2after the formation of a BSPDN445, in accordance with the embodiment of the present invention. InFIG.55, a portion of the third additional BILD layer437is selectively removed by, for example, CMP to expose a top surface of the first backside signal line430A, the second backside signal line430B, and the third backside signal line430C. The BSPDN445is formed directly atop the third additional BILD layer437, the first backside signal line430A, the second backside signal line430B, and the third backside signal line430C.

InFIG.56, a portion of the third additional BILD layer437is selectively removed by, for example, CMP to expose a top surface of the first backside signal line430A and the fourth backside signal line430D. The BSPDN445is formed directly atop the third additional BILD layer437, the first backside signal line430A, and the fourth backside signal line430D.

InFIG.57, the third additional BILD layer437is removed by, for example, CMP. The BSPDN445is formed directly atop the third backside signal line430C.

The plurality of backside signal lines230A,230B,230C,230D are located at cell boundaries of the plurality of nanodevices ND1, ND2. The first gap G1 exists between the first backside power line230A and the third backside power line230C. The second gap G2 exists between the second backside power line230B and the fourth backside power line230D. The first backside signal line230A, the second backside signal line230B, the third backside signal line230C, and the fourth backside signal line230D extend the first width WS1, second width WS2, third width WS3, and fourth width WS4, respectively, parallel to the x-axis. The first BPR225A and the second BPR225B extend the first width WP1 and second width WP2, respectively, parallel to the x-axis, where the first width WP1 and the second width WP2 are equivalent. The widths WP1, WP2 of the plurality of BPRs225A,225B parallel to the x-axis are greater than the widths WS1, WS2, WS3, WS4 of the plurality of backside signal lines230A,230B,230C,230D parallel to the x-axis.

The first backside signal line430A, the second backside signal line430B, the third backside signal line430C, the fourth backside signal line430D, and the fifth backside signal line430E extend the first length LS1, second length LS2, third length LS3, fourth length LS4, and fifth length LS5, respectively, parallel to the y-axis. The first backside signal line430A, the second backside signal line430B, and the third backside signal line430C overlap the first BPR425A and the second BPR425B along the y-axis. The third backside signal line430C overlaps and bypasses the first BPR425A and the second BPR425B along the y-axis. The fourth backside signal line430D is located at the cell boundary of the first nanodevice ND1. The fifth backside signal line430E is located at the cell boundary of the second nanodevice ND2.

It may be appreciated thatFIGS.1-57provide only an illustration of one implementation and do not imply any limitations with regard to how different embodiments may be implemented. Many modifications to the depicted environments may be made based on design and implementation requirements.