Method for making a FINFET having reduced contact resistance

A method for making a FINFET may include forming spaced apart source and drain regions in a semiconductor fin with a channel region extending therebetween. At least one of the source and drain regions may be divided into a lower region and an upper region by a dopant diffusion blocking superlattice with the upper region having a same conductivity and higher dopant concentration than the lower region. The method may further include forming a gate on the channel region, depositing at least one metal layer on the upper region, and applying heat to move upward non-semiconductor atoms from the non-semiconductor monolayers to react with the at least one metal layer to form a contact insulating interface between the upper region and adjacent portions of the at least one metal layer.

TECHNICAL FIELD

The present disclosure generally relates to semiconductor devices and, more particularly, to semiconductor devices with enhanced contact configurations and related methods.

BACKGROUND

Structures and techniques have been proposed to enhance the performance of semiconductor devices, such as by enhancing the mobility of the charge carriers. For example, U.S. Patent Application No. 2003/0057416 to Currie et al. discloses strained material layers of silicon, silicon-germanium, and relaxed silicon and also including impurity-free zones that would otherwise cause performance degradation. The resulting biaxial strain in the upper silicon layer alters the carrier mobilities enabling higher speed and/or lower power devices. Published U.S. Patent Application No. 2003/0034529 to Fitzgerald et al. discloses a CMOS inverter also based upon similar strained silicon technology.

U.S. Pat. No. 6,472,685 B2 to Takagi discloses a semiconductor device including a silicon and carbon layer sandwiched between silicon layers so that the conduction band and valence band of the second silicon layer receive a tensile strain. Electrons having a smaller effective mass, and which have been induced by an electric field applied to the gate electrode, are confined in the second silicon layer, thus, an n-channel MOSFET is asserted to have a higher mobility.

U.S. Pat. No. 4,937,204 to Ishibashi et al. discloses a superlattice in which a plurality of layers, less than eight monolayers, and containing a fractional or binary or a binary compound semiconductor layer, are alternately and epitaxially grown. The direction of main current flow is perpendicular to the layers of the superlattice.

U.S. Pat. No. 5,357,119 to Wang et al. discloses a Si—Ge short period superlattice with higher mobility achieved by reducing alloy scattering in the superlattice. Along these lines, U.S. Pat. No. 5,683,934 to Candelaria discloses an enhanced mobility MOSFET including a channel layer comprising an alloy of silicon and a second material substitutionally present in the silicon lattice at a percentage that places the channel layer under tensile stress.

U.S. Pat. No. 5,216,262 to Tsu discloses a quantum well structure comprising two barrier regions and a thin epitaxially grown semiconductor layer sandwiched between the barriers. Each barrier region consists of alternate layers of SiO2/Si with a thickness generally in a range of two to six monolayers. A much thicker section of silicon is sandwiched between the barriers.

An article entitled “Phenomena in silicon nanostructure devices” also to Tsu and published online Sep. 6, 2000 by Applied Physics and Materials Science & Processing, pp. 391-402 discloses a semiconductor-atomic superlattice (SAS) of silicon and oxygen. The Si/O superlattice is disclosed as useful in a silicon quantum and light-emitting devices. In particular, a green electroluminescence diode structure was constructed and tested. Current flow in the diode structure is vertical, that is, perpendicular to the layers of the SAS. The disclosed SAS may include semiconductor layers separated by adsorbed species such as oxygen atoms, and CO molecules. The silicon growth beyond the adsorbed monolayer of oxygen is described as epitaxial with a fairly low defect density. One SAS structure included a 1.1 nm thick silicon portion that is about eight atomic layers of silicon, and another structure had twice this thickness of silicon. An article to Luo et al. entitled “Chemical Design of Direct-Gap Light-Emitting Silicon” published in Physical Review Letters, Vol. 89, No. 7 (Aug. 12, 2002) further discusses the light emitting SAS structures of Tsu.

U.S. Pat. No. 7,105,895 to Wang et al. discloses a barrier building block of thin silicon and oxygen, carbon, nitrogen, phosphorous, antimony, arsenic or hydrogen to thereby reduce current flowing vertically through the lattice more than four orders of magnitude. The insulating layer/barrier layer allows for low defect epitaxial silicon to be deposited next to the insulating layer.

Published Great Britain Patent Application 2,347,520 to Mears et al. discloses that principles of Aperiodic Photonic Band-Gap (APBG) structures may be adapted for electronic bandgap engineering. In particular, the application discloses that material parameters, for example, the location of band minima, effective mass, etc., can be tailored to yield new aperiodic materials with desirable band-structure characteristics. Other parameters, such as electrical conductivity, thermal conductivity and dielectric permittivity or magnetic permeability are disclosed as also possible to be designed into the material.

Furthermore, U.S. Pat. No. 6,376,337 to Wang et al. discloses a method for producing an insulating or barrier layer for semiconductor devices which includes depositing a layer of silicon and at least one additional element on the silicon substrate whereby the deposited layer is substantially free of defects such that epitaxial silicon substantially free of defects can be deposited on the deposited layer. Alternatively, a monolayer of one or more elements, preferably comprising oxygen, is absorbed on a silicon substrate. A plurality of insulating layers sandwiched between epitaxial silicon forms a barrier composite.

Despite the existence of such approaches, further enhancements may be desirable for using advanced semiconductor materials and processing techniques to achieve improved performance in semiconductor devices.

SUMMARY

A method for making a FINFET may include forming spaced apart source and drain regions in a semiconductor fin with a channel region extending therebetween. At least one of the source and drain regions may be divided into a lower region and an upper region by a dopant diffusion blocking superlattice with the upper region having a same conductivity and higher dopant concentration than the lower region. The dopant diffusion blocking superlattice may include a respective plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming a gate on the channel region, depositing at least one metal layer on the upper region, and applying heat to move upward non-semiconductor atoms from the non-semiconductor monolayers to react with the at least one metal layer to form a contact insulating interface between the upper region and adjacent portions of the at least one metal layer.

More particularly, each of the source and drain regions may be divided into lower and upper regions by a respective dopant blocking superlattice. In one example implementation, the upper region may be raised above an upper surface of the semiconductor fin. Furthermore, the lower region may comprise a different material than the upper region. By way of example, the lower region may comprise silicon, and the upper region may comprise silicon germanium. In accordance with another example, the lower region may comprise silicon germanium, and the upper region may comprise silicon.

In addition, the at least one metal layer may comprise a lower metal layer and an upper metal layer different than the lower metal layer. By way of example, the at least one metal layer may comprise at least one of titanium, cobalt, nickel and platinum. Also by way of example, the base semiconductor monolayers may comprise silicon, and the at least one non-semiconductor monolayer may comprise oxygen.

DETAILED DESCRIPTION

Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings, in which the example embodiments are shown. The embodiments may, however, be implemented in many different forms and should not be construed as limited to the specific examples set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete. Like numbers refer to like elements throughout, and prime and multiple prime notation are used to indicate similar elements in different embodiments.

Generally speaking, the present disclosure relates to utilizing enhanced superlattice materials within source and drain regions to reduce Schottky barrier height and thereby decrease source and drain contact resistance. The enhanced semiconductor superlattice is also referred to as an “MST” layer or “MST technology” in this disclosure and the accompanying drawings.

More particularly, the MST technology relates to advanced semiconductor materials such as the superlattice25described further below. Applicant theorizes, without wishing to be bound thereto, that certain superlattices as described herein reduce the effective mass of charge carriers and that this thereby leads to higher charge carrier mobility. Effective mass is described with various definitions in the literature. As a measure of the improvement in effective mass Applicants use a “conductivity reciprocal effective mass tensor”, Me−1and Mh−1for electrons and holes respectively, defined as:

Mh,ij-1⁡(EF,T)=-∑E<EF⁢∫B.Z.⁢(∇k⁢E⁡(k,n))i⁢(∇k⁢E⁡(k,n))j⁢∂f⁡(E⁡(k,n),EF,T)∂E⁢d3⁢k∑E<EF⁢∫B.Z.⁢(1-f⁡(E⁡(k,n),EF,T))⁢d3⁢k
for holes, where f is the Fermi-Dirac distribution, EFis the Fermi energy, T is the temperature, E(k,n) is the energy of an electron in the state corresponding to wave vector k and the nthenergy band, the indices i and j refer to Cartesian coordinates x, y and z, the integrals are taken over the Brillouin zone (B.Z.), and the summations are taken over bands with energies above and below the Fermi energy for electrons and holes respectively.

Applicant's definition of the conductivity reciprocal effective mass tensor is such that a tensorial component of the conductivity of the material is greater for greater values of the corresponding component of the conductivity reciprocal effective mass tensor. Again Applicant theorizes without wishing to be bound thereto that the superlattices described herein set the values of the conductivity reciprocal effective mass tensor so as to enhance the conductive properties of the material, such as typically for a preferred direction of charge carrier transport. The inverse of the appropriate tensor element is referred to as the conductivity effective mass. In other words, to characterize semiconductor material structures, the conductivity effective mass for electrons/holes as described above and calculated in the direction of intended carrier transport is used to distinguish improved materials.

Applicant has identified improved materials or structures for use in semiconductor devices. More specifically, Applicant has identified materials or structures having energy band structures for which the appropriate conductivity effective masses for electrons and/or holes are substantially less than the corresponding values for silicon. In addition to the enhanced mobility characteristics of these structures, they may also be formed or used in such a manner that they provide piezoelectric, pyroelectric, and/or ferroelectric properties that are advantageous for use in a variety of different types of devices, as will be discussed further below.

Referring now toFIGS. 1 and 2, the materials or structures are in the form of a superlattice25whose structure is controlled at the atomic or molecular level and may be formed using known techniques of atomic or molecular layer deposition. The superlattice25includes a plurality of layer groups45a-45narranged in stacked relation, as perhaps best understood with specific reference to the schematic cross-sectional view ofFIG. 1.

Each group of layers45a-45nof the superlattice25illustratively includes a plurality of stacked base semiconductor monolayers46defining a respective base semiconductor portion46a-46nand an energy band-modifying layer50thereon. The energy band-modifying layers50are indicated by stippling inFIG. 1for clarity of illustration.

The energy band-modifying layer50illustratively includes one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. By “constrained within a crystal lattice of adjacent base semiconductor portions” it is meant that at least some semiconductor atoms from opposing base semiconductor portions46a-46nare chemically bound together through the non-semiconductor monolayer50therebetween, as seen inFIG. 2. Generally speaking, this configuration is made possible by controlling the amount of non-semiconductor material that is deposited on semiconductor portions46a-46nthrough atomic layer deposition techniques so that not all (i.e., less than full or 100% coverage) of the available semiconductor bonding sites are populated with bonds to non-semiconductor atoms, as will be discussed further below. Thus, as further monolayers46of semiconductor material are deposited on or over a non-semiconductor monolayer50, the newly deposited semiconductor atoms will populate the remaining vacant bonding sites of the semiconductor atoms below the non-semiconductor monolayer.

In other embodiments, more than one such non-semiconductor monolayer may be possible. It should be noted that reference herein to a non-semiconductor or semiconductor monolayer means that the material used for the monolayer would be a non-semiconductor or semiconductor if formed in bulk. That is, a single monolayer of a material, such as silicon, may not necessarily exhibit the same properties that it would if formed in bulk or in a relatively thick layer, as will be appreciated by those skilled in the art.

Applicant theorizes without wishing to be bound thereto that energy band-modifying layers50and adjacent base semiconductor portions46a-46ncause the superlattice25to have a lower appropriate conductivity effective mass for the charge carriers in the parallel layer direction than would otherwise be present. Considered another way, this parallel direction is orthogonal to the stacking direction. The band modifying layers50may also cause the superlattice25to have a common energy band structure, while also advantageously functioning as an insulator between layers or regions vertically above and below the superlattice.

Moreover, this superlattice structure may also advantageously act as a barrier to dopant and/or material diffusion between layers vertically above and below the superlattice25. These properties may thus advantageously allow the superlattice25to provide an interface for high-K dielectrics which not only reduces diffusion of the high-K material into the channel region, but which may also advantageously reduce unwanted scattering effects and improve device mobility, as will be appreciated by those skilled in the art.

It is also theorized that semiconductor devices including the superlattice25may enjoy a higher charge carrier mobility based upon the lower conductivity effective mass than would otherwise be present. In some embodiments, and as a result of the band engineering achieved by the present invention, the superlattice25may further have a substantially direct energy bandgap that may be particularly advantageous for opto-electronic devices, for example.

The superlattice25also illustratively includes a cap layer52on an upper layer group45n. The cap layer52may comprise a plurality of base semiconductor monolayers46. The cap layer52may have between 2 to 100 monolayers of the base semiconductor, and, more preferably between 10 to 50 monolayers. The base semiconductor layers46aare on a semiconductor substrate21.

Each base semiconductor portion46a-46nmay comprise a base semiconductor selected from the group consisting of Group IV semiconductors, Group III-V semiconductors, and Group II-VI semiconductors. Of course, the term Group IV semiconductors also includes Group IV-IV semiconductors, as will be appreciated by those skilled in the art. More particularly, the base semiconductor may comprise at least one of silicon and germanium, for example.

Each energy band-modifying layer50may comprise a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, carbon and carbon-oxygen, for example. The non-semiconductor is also desirably thermally stable through deposition of a next layer to thereby facilitate manufacturing. In other embodiments, the non-semiconductor may be another inorganic or organic element or compound that is compatible with the given semiconductor processing as will be appreciated by those skilled in the art. More particularly, the base semiconductor may comprise at least one of silicon and germanium, for example

It should be noted that the term monolayer is meant to include a single atomic layer and also a single molecular layer. It is also noted that the energy band-modifying layer50provided by a single monolayer is also meant to include a monolayer wherein not all of the possible sites are occupied (i.e., there is less than full or 100% coverage). For example, with particular reference to the atomic diagram ofFIG. 2, a 4/1 repeating structure is illustrated for silicon as the base semiconductor material, and oxygen as the energy band-modifying material. Only half of the possible sites for oxygen are occupied in the illustrated example.

In other embodiments and/or with different materials this one-half occupation would not necessarily be the case as will be appreciated by those skilled in the art. Indeed it can be seen even in this schematic diagram, that individual atoms of oxygen in a given monolayer are not precisely aligned along a flat plane as will also be appreciated by those of skill in the art of atomic deposition. By way of example, a preferred occupation range is from about one-eighth to one-half of the possible oxygen sites being full, although other numbers may be used in certain embodiments.

Silicon and oxygen are currently widely used in conventional semiconductor processing, and, hence, manufacturers will be readily able to use these materials as described herein. Atomic or monolayer deposition is also now widely used. Accordingly, semiconductor devices incorporating the superlattice25in accordance with the invention may be readily adopted and implemented, as will be appreciated by those skilled in the art.

It is theorized without Applicant wishing to be bound thereto that for a superlattice, such as the Si/O superlattice, for example, that the number of silicon monolayers should desirably be seven or less so that the energy band of the superlattice is common or relatively uniform throughout to achieve the desired advantages. The 4/1 repeating structure shown inFIGS. 1 and 2, for Si/O has been modeled to indicate an enhanced mobility for electrons and holes in the X direction. For example, the calculated conductivity effective mass for electrons (isotropic for bulk silicon) is 0.26 and for the 4/1 SiO superlattice in the X direction it is 0.12 resulting in a ratio of 0.46. Similarly, the calculation for holes yields values of 0.36 for bulk silicon and 0.16 for the 4/1 Si/O superlattice resulting in a ratio of 0.44.

While such a directionally preferential feature may be desired in certain semiconductor devices, other devices may benefit from a more uniform increase in mobility in any direction parallel to the groups of layers. It may also be beneficial to have an increased mobility for both electrons and holes, or just one of these types of charge carriers as will be appreciated by those skilled in the art.

The lower conductivity effective mass for the 4/1 Si/O embodiment of the superlattice25may be less than two-thirds the conductivity effective mass than would otherwise occur, and this applies for both electrons and holes. Of course, the superlattice25may further comprise at least one type of conductivity dopant therein, as will also be appreciated by those skilled in the art.

Indeed, referring now additionally toFIG. 3, another embodiment of a superlattice25′ in accordance with the invention having different properties is now described. In this embodiment, a repeating pattern of 3/1/5/1 is illustrated. More particularly, the lowest base semiconductor portion46a′has three monolayers, and the second lowest base semiconductor portion46b′has five monolayers. This pattern repeats throughout the superlattice25′. The energy band-modifying layers50′ may each include a single monolayer. For such a superlattice25′ including Si/O, the enhancement of charge carrier mobility is independent of orientation in the plane of the layers. Those other elements ofFIG. 3not specifically mentioned are similar to those discussed above with reference toFIG. 1and need no further discussion herein.

In some device embodiments, all of the base semiconductor portions of a superlattice may be a same number of monolayers thick. In other embodiments, at least some of the base semiconductor portions may be a different number of monolayers thick. In still other embodiments, all of the base semiconductor portions may be a different number of monolayers thick.

InFIGS. 4A-4C, band structures calculated using Density Functional Theory (DFT) are presented. It is well known in the art that DFT underestimates the absolute value of the bandgap. Hence all bands above the gap may be shifted by an appropriate “scissors correction.” However the shape of the band is known to be much more reliable. The vertical energy axes should be interpreted in this light.

FIG. 4Ashows the calculated band structure from the gamma point (G) for both bulk silicon (represented by continuous lines) and for the 4/1 Si/O superlattice25shown inFIG. 1(represented by dotted lines). The directions refer to the unit cell of the 4/1 Si/O structure and not to the conventional unit cell of Si, although the (001) direction in the figure does correspond to the (001) direction of the conventional unit cell of Si, and, hence, shows the expected location of the Si conduction band minimum. The (100) and (010) directions in the figure correspond to the (110) and (−110) directions of the conventional Si unit cell. Those skilled in the art will appreciate that the bands of Si on the figure are folded to represent them on the appropriate reciprocal lattice directions for the 4/1 Si/O structure.

It can be seen that the conduction band minimum for the 4/1 Si/O structure is located at the gamma point in contrast to bulk silicon (Si), whereas the valence band minimum occurs at the edge of the Brillouin zone in the (001) direction which we refer to as the Z point. One may also note the greater curvature of the conduction band minimum for the 4/1 Si/O structure compared to the curvature of the conduction band minimum for Si owing to the band splitting due to the perturbation introduced by the additional oxygen layer.

FIG. 4Bshows the calculated band structure from the Z point for both bulk silicon (continuous lines) and for the 4/1 Si/O superlattice25(dotted lines). This figure illustrates the enhanced curvature of the valence band in the (100) direction.

FIG. 4Cshows the calculated band structure from both the gamma and Z point for both bulk silicon (continuous lines) and for the 5/1/3/1 Si/O structure of the superlattice25′ ofFIG. 3(dotted lines). Due to the symmetry of the 5/1/3/1 Si/O structure, the calculated band structures in the (100) and (010) directions are equivalent. Thus the conductivity effective mass and mobility are expected to be isotropic in the plane parallel to the layers, i.e. perpendicular to the (001) stacking direction. Note that in the 5/1/3/1 Si/O example the conduction band minimum and the valence band maximum are both at or close to the Z point.

Although increased curvature is an indication of reduced effective mass, the appropriate comparison and discrimination may be made via the conductivity reciprocal effective mass tensor calculation. This leads Applicant to further theorize that the 5/1/3/1 superlattice25′ should be substantially direct bandgap. As will be understood by those skilled in the art, the appropriate matrix element for optical transition is another indicator of the distinction between direct and indirect bandgap behavior.

Having now described the structure and formation of example MST materials, various embodiments of semiconductor devices and method for their manufacture will now be described which advantageously provide for metal-silicon contacts with proximate dopants using the above-described MST materials. By way of background, it is typical in semiconductor devices for electrons to be transferred between a semiconductor (such as silicon) and conducting metal “interconnects” which transfer charge between semiconductor devices. Electrical resistance between the semiconductor and metal increases the energy required and reduces the maximum speed of computations and other functions performed by circuits using the devices. It is thus advantageous to minimize this electrical resistance.

When electrons are transferred between a metal and a semiconductor such as silicon, there is a potential barrier encountered by the electron. This barrier is typically referred to as the “Schottky barrier.” Electrons can either have sufficient kinetic energy to overcome the Schottky barrier directly, or electrons with lower kinetic energy may pass between the metal and semiconductor via quantum mechanical tunneling. Such tunneling is more likely the spatially thinner the Schottky barrier. A typical way to attain a reduced barrier is to increase the electric field. Higher levels of ionized impurities (“dopants”) typically yield higher electric fields and thus increase the tunneling probability, increasing the electron flux between the metal and the semiconductor, thus reducing the effective electrical resistance. But in addition to increasing the electric field, high levels of impurities may additionally reduce the Schottky barrier itself, by reducing the effective band gap of the semiconductor immediately adjacent to the metal-semiconductor interface (and via other chemical effects). This effect is evident from density functional theory calculations.

Oxygen insertion (OI) layers (or other non-semiconductor layers), such as provided in an MST film, for example, may contribute to a lower Schottky and/or thinner barrier by trapping dopants. Density functional theory calculations have shown that OI layers provide for the favorable substitution of specific dopant atoms for silicon atoms within one or two atomic layers of the OI layer. By trapping dopants immediately proximate to, for example, separated by one or two atomic layers from, a metal-semiconductor interface, OI layers may thus contribute to a relatively higher concentration of dopants immediately adjacent to the metal-semiconductor interface, increasing the electric field, and additionally reducing the Schottky barrier.

In addition to trapping dopants, OI layers may immobilize them by trapping point defects that would otherwise aid the diffusion of dopants. So, while an OI layer proximate to a metal-semiconductor layer may trap dopants immediately adjacent to that interface, additional OI layers further from but still proximate to the interface may trap point defects that would otherwise aid in the diffusion of dopants away from the interface. Thus, it may be beneficial to have more than one, for example two, three, or four, OI layers proximate to the interface.

Generally speaking, the embodiments described herein utilize one or more oxygen insertion (“OI” or “MST”) layers in close proximity to a metal-semiconductor interface in conjunction with a high (for example, in excess of 1021/cm3, or 2% of crystalline sites in the silicon lattice) of ionized impurities such as boron, phosphorus, arsenic, antimony, indium, or gallium in the near proximity (for example, closer than 1 nm) to the metal-silicon interface. Examples of metals include aluminum, tungsten, nickel, titanium, copper, cobalt, indium, gold, platinum, erbium, ytterbium, and compounds of any of these metals with silicon or germanium.

Since the OI layers may provide for favorable substitution by dopant atoms of silicon atoms one or two atomic layers away, the most favorable separation of an OI layer from a metal-semiconductor interface is one or two atomic layers, allowing for the trapping of a high concentration of dopants up to and immediately adjacent to the metal-semiconductor interface. But benefits may also be provided with other separations, for example three, or four atomic layers. Additionally, there may be a benefit in including additional oxygen insertion layers in addition to this first oxygen insertion layer.

Examples of this approach are represented in the graph500ofFIG. 15, in which: Si=Silicon atom; M=Metal atom (e.g. titanium); O=Oxygen atom; and D=Dopant atom (e.g. boron). The oxygen atoms as drawn are part of oxygen insertion layers, where the oxygen is bonded with adjacent silicon atoms. While oxygen atoms are necessarily present in the OI layers, there may also additionally be nitrogen atoms, which are not represented in the figure. The presence of nitrogen may be beneficial for the trapping of dopants or for the thermal stability of the OI layers, for example.

Similarly, the represented dopants are replacing silicon atoms in the crystalline lattice, as opposed to occupying “interstitial” positions or in dopant clusters where they will fail to contribute to free carriers in the semiconductor. However, while substitutional dopants are represented in the figure, a high concentration of dopants trapped near the metal-semiconductor interface may reduce a Schottky barrier with alternate atomic configurations. The positions of dopants in the diagram are a schematic representative for illustrational purposes. An actual distribution of dopant atoms will be in part random, influenced by the specific atomic configuration of oxygen atoms, and the local bonding of atoms. The illustrated configurations represent the distance of atoms from the metal-semiconductor interface, not specific positions of atoms within layers. The illustrated configurations are as follows:(a) OI layer in contact with metal, trapping dopants below the OI layer;(b) OI layer separated by one atomic layer of silicon from the metal, trapping dopants both above and below the OI layer;(c) OI layer separated by two atomic layers from the metal, trapping dopants both above and below the OI layer;(d) OI layer separated by three atomic layers from the metal, trapping dopants both above and below the OI layer, but in this example not reaching the metal interface itself;(e) OI layer separated by four atomic layers from the metal, trapping dopants both above and below the OI layer, but in this example not reaching the metal interface itself.

In addition to these configurations, additional configurations with multiple OI layers are also possible, for example one layer separated from the metal-semiconductor interface by two silicon layers, and an additional layer separated by an additional four atomic layers. These multiple layers may provide for dopant trapping both at the metal-semiconductor interface, and additionally below the metal-semiconductor interface, the former contributing to chemical Schottky barrier lowering and a higher electric field, the latter contributing primarily through higher electric field. The embodiments set forth herein are generally defined by the presence of a layer proximate to the metal-semiconductor interface in conjunction with a high concentration of dopants, but does not exclude additional layers or dopant atoms not proximate to OI layer(s). A specific advantage of additional OI layers is these additional layers may increase the stability of the structure, for example blocking the loss of oxygen from the layer closest to the metal-semiconductor interface, or trapping point defects which otherwise would contribute to a loss of dopant atoms from the region proximate to the metal-semiconductor interface.

Referring now toFIG. 5, the above-described superlattice structures may advantageously be used in semiconductor devices to provide reduced source/drain contact resistance by applying the above-described principles. In typical semiconductor processes, the reduction of metal to semiconductor contact area requires lower contact resistivity (e.g., ρc<1E-8 ohm.cm2). Contact resistivity is determined by two parameters, which are:
ND: active dopant concentration at metal/semiconductor interface; and
ΦFBo: Schottky barrier height at metal/semiconductor interface
Furthermore, the metal-semiconductor Schottky barrier height is “pinned” for different metals. Moreover, an interfacial insulator can “de-pin” the Fermi level depending on thickness, bandgap, and permittivity.

In the semiconductor device100shown inFIG. 5(a FET), a dopant diffusion blocking superlattice125(such as those described above inFIGS. 1-4C) is used to advantageously increase surface dopant concentration to allow a higher NDduring in-situ doped epitaxial processing by preventing diffusion into a channel region130of the device. More particularly, the device100illustratively includes a semiconductor layer or substrate101, and spaced apart source and drain regions102,103formed in the semiconductor layer with the channel region130extending therebetween. The dopant diffusion blocking superlattice125illustratively extends through the source region102to divide the source region into a lower source region104and an upper source region105, and also extends through the drain region103to divide the drain region into a lower drain region106and an upper drain region107.

The dopant diffusion blocking superlattice125may also conceptually be considered as a source dopant blocking superlattice within the source region102, a drain dopant blocking superlattice within the drain region103, and a body dopant blocking superlattice beneath the channel130, although in this configuration all three of these are provided by a single blanket deposition of the MST material across the substrate101as a continuous film. The semiconductor material above the dopant blocking superlattice125in which the upper source/drain regions105,107and channel region130are defined may be epitaxially grown on the dopant blocking superlattice125either as a thick superlattice cap layer or bulk semiconductor layer, as discussed further above. In the illustrated example, the upper source/drain regions105,107may each be level with an upper surface of this semiconductor layer (i.e., they are implanted within this layer).

As such, the upper source/drain regions105,107may advantageously have a same conductivity as the lower source/drain regions104,106, yet with a higher dopant concentration. In the illustrated example, the upper source/drain regions105,107and the lower source/drain regions104,106are N-type for a N-channel device, but these regions may also be P-type for an P-channel device as well (this applies to other configurations described herein as well). Surface dopant may be introduced by ion implantation, for example. Yet, the dopant diffusion is reduced by the MST film material of the diffusion blocking superlattice125because it traps point defects/interstitials introduced by ion implantation which mediate dopant diffusion.

The semiconductor device100further illustratively includes a gate108on the channel region130. The gate illustratively includes a gate insulating layer109gate electrode110. Sidewall spacers111are also provided in the illustrated example.

Referring now toFIG. 6, in accordance with another example implementation a semiconductor device200(FET) illustratively includes a semiconductor layer or substrate201, and spaced apart source and drain regions202,203with a channel region230extending therebetween. In the illustrated embodiment, a source diffusion blocking superlattice225sillustratively extends through the source region202to divide the source region into a lower source region204and an upper source region205. Similarly, a drain diffusion blocking superlattice225dextends through the drain region203to divide the drain region into a lower drain region206and an upper drain region207. Considered alternatively, the upper source and drain regions205,207are each raised above an upper surface of the semiconductor layer201, and there is no superlattice extending between the source and drain regions202,203as in the example ofFIG. 5(i.e., beneath gate208). The gate208illustratively includes a gate insulator209and gate electrode210, and gate sidewall spacers211may also be provided.

In this implementation, the surface dopant in the upper source/drain regions205,207may be introduced by selectively growing MST films, followed by in-situ doped epi film formation. Here again, the MST material of the source/drain dopant diffusion blocking superlattices225s,225badvantageously helps prevent dopant diffusion into the channel region230, and thus allows higher surface dopant concentration as noted above.

In accordance with another example implementation now described with reference toFIGS. 7A-7C, further processing steps may be performed to the semiconductor device100shown inFIG. 5to perform Schottky barrier height modulation by controlling a thickness and composition of an interfacial insulator. With traditional metal contacts, too thick of a source/drain insulator results in high contact resistivity due to high tunneling resistance. However, the superlattice125′ advantageously provides desired non-semiconductor (e.g., oxygen) dose control for Fermi-level de-pinning and tunneling resistance. After formation of the gate108′ on the channel region130′, co-implantation of N, C, or F may further modulate insulator composition for lower permittivity (e.g., C and F used for low-k ILD film to modulate SiO2composition), as illustrated inFIG. 7A. The MST film of the superlattice125′ effectively accumulates these elements into the surface region. It should be noted that in some embodiments N and C may be incorporated into silicon surface by gaseous form (e.g., N2anneal or CO, CH4anneal) instead of co-implantation.

A thermal treatment and metal deposition may then be performed (FIGS. 7B-7C). The thermal treatment moves upward non-semiconductor atoms (oxygen in the present example) from the non-semiconductor monolayers of the dopant diffusion blocking superlattices125′ which react with the metal to form respective source and drain contact insulating interfaces140′,141′ between the upper source and drain regions and adjacent portions of metal layers142′,143′ formed by the metal deposition. Stated alternatively, as the oxygen atoms disassociate from the superlattice125′ in the source and drain regions and move upward to form the contact insulating interfaces140′,141′ so that there is no longer a defined superlattice layer separating the lower/upper source regions104′,105′ and lower/upper drain regions106′,107′ (seeFIG. 7B).

In accordance with one example implementation, a Co/Co0.75Ti0.25(2 nm) metal deposition may be performed at a temperature in a range of about +200˜400 C for approximately 10 min. to form the source and drain contact insulating interfaces140′,141′ and metal layers142′,143′. Moreover, in some implementations, an additional metal deposition (e.g., Co) may be performed to form upper source/drain metal contact layers144′,145′ in the semiconductor device100′.

Another example embodiment similar to the semiconductor device200is now described with reference to FIG.8. In this illustrated example, the source and drain dopant diffusion blocking superlattices225s′,225d′advantageously provide for Schottky barrier height modulation via hetero-epitaxial film integration. More particularly, the lower source and drain regions204′,206′ include a different material than the upper source and drain regions205′,207′. In this example, the lower source and drain regions204′,206′ are silicon, and the upper source and drain regions205′,207′ are SiGeC, although different materials may be used in different embodiments. Lower metal layers (Ti)242′,243′ are formed on the upper source and drain regions (SiGeC layers)205′,207′. Upper metal layers (Co)244′,245′ are formed on the lower metal layers242′,243′, respectively.

Because the MST material is effective in integrating hetero-epitaxial semiconductor material, incorporation of C(1-2%) to Si or SiGe on Si may induce a positive conduction band offset. More particularly, this is a SiGeC/MST/n+ Si structure that is effective for reducing Schottky barrier height.

Referring additionally toFIG. 9, another similar semiconductor device200″ advantageously provides for Schottky barrier height modulation via hetero-epitaxial film integration. In the illustrated example, the semiconductor layer/substrate201″ is silicon germanium, and the lower source/drain regions204″,206″ are P+ SiGe. Moreover, the upper source/drain regions205″,207″ are also silicon, and a respective metal (e.g. platinum) contact layer242″,243″ is formed on each of the upper source/drain regions. The upper source/drain regions205″,207″ may be formed in a relatively thin epitaxial silicon layer (e.g., 2-5 nm). Here again, the MST material is effective in integrating hetero-epitaxial semiconductor material, and strained Si on SiGe (or Ge) may advantageously induce negative valence band offset. As a result, the illustrated s-Si/MST/p+ SiGe structure may be effective for reducing Schottky barrier height as well.

Turning now additionally toFIG. 10, certain of the above-described planar FET configurations may also advantageously be implemented in vertical semiconductor devices as well. An example FINFET300illustratively includes a semiconductor layer or substrate301(e.g., silicon), an insulating layer350on the substrate (e.g., SiO2), and one or more semiconductor fins351extending vertically upward from the substrate through the insulating layer.

Spaced apart source and drain regions302,303are formed in each semiconductor fin351with a channel region330extending therebetween. A source dopant diffusion blocking superlattice325sextends through the source region302to divide the source region into a lower source region304and an upper source region305, and a drain dopant diffusion blocking superlattice325dextends through the drain region303to divide the drain region into a lower drain region306and an upper drain region307. Similar to the embodiment ofFIG. 6, the upper source/drain regions305,307have a same conductivity and higher dopant concentration (N++) than the lower source/drain regions304,306(N+). Moreover, the upper source/drain regions305,307extend above an upper surface of the semiconductor fin351. That is, superlattices325s,325dmay be formed on the top of the semiconductor fin351, and the upper source/drain regions305,307may be epitaxially grown on the respective superlattices. In this regard, the upper source/drain regions305,307may be first formed and then implanted with a dopant, or they may be in-situ doped epitaxial layers as described above.

The FINFET300also illustratively includes a gate308overlying the channel regions330of the fins351. The gate308illustratively includes a gate insulator309and a gate electrode310on the gate insulator.

In accordance with another example implementation, a FINFET300′ may be fabricated using a similar process to that described above with respect toFIGS. 7A-7C, i.e., involving a thermal treatment and metal deposition to define source/drain insulating layers340′,341′ between the upper source/drain regions305′,307′ and metal layers342′,343′ (e.g., CoTix) respectively. Upper metal layers344′,345′ (e.g., Co) may also be formed on the lower metal layers342′,343′ in some embodiments. Here again, the heat treatment causes the non-semiconductor atoms in the source/drain dopant blocking superlattice layers to move upward, leaving no superlattice between the upper source/drain regions305′,307′ and the lower source/drain regions304′,306′ in the final FINFET300′. Here again, this approach advantageously provides for Schottky barrier height modulation by controlling the thickness and composition of the interfacial insulators340′,341′.

Referring additionally toFIG. 13, a FINFET300″ is provided which is similar to embodiment ofFIG. 8above, in that the source and drain dopant blocking superlattices325s″,325d″advantageously provide for Schottky barrier height modulation via hetero-epitaxial film integration. More particularly, the lower source and drain regions304″,306″ include a different material than the upper source and drain regions305″,307″. In this example, the lower source and drain304″,306″ regions are silicon, and the upper source and drain regions305″,307″ are SiGeC, although different materials may be used in different embodiments. Also, the lower metal layers342″,343″ are titanium, and the upper metal layers344″,345″ are cobalt in the illustrated example.

In still another example shown inFIG. 14, similar to the embodiment ofFIG. 9the FINFET300′″ may also provide for Schottky barrier height modulation via hetero-epitaxial film integration. In the illustrated example, the semiconductor fin351″′ is silicon germanium, and the lower source/drain regions304″′,306″′ are P+ SiGe. Moreover, the upper source/drain regions305″′,307″′ are silicon, and a respective platinum contact layer342″′,343″′ is formed on each of the upper source/drain regions. Here again, the upper source/drain regions305″′,307″′ may be formed in a relatively thin epitaxial silicon layer (e.g., 2-5 nm).

In the above-described examples, a dopant blocking superlattice is shown in both of the source and drain regions of the illustrated devices. However, it should be noted that in some embodiments both of the source and drain regions need not have a dopant blocking superlattice. That is, the dopant blocking superlattice may be in just one of the source or drain regions in some embodiments.

Furthermore, turning now toFIG. 16, in some embodiments a dopant blocking superlattice may also be incorporated in a body contact to provide reduced body contact resistance in addition to, or instead of, in the source/drain regions. In the illustrated example, a semiconductor device400(here a planar FET) includes a semiconductor layer or substrate401, spaced apart source and drain regions402,403(which have respective lightly doped source/drain extensions404,405in this example) in the semiconductor layer401with a channel region430extending therebetween, and a gate408on the channel region with sidewall spacers411. As similarly described above, the gate408illustratively includes a gate insulator409and a gate electrode410. The semiconductor device400further illustratively includes a body contact420in the semiconductor layer401and comprising a body contact dopant diffusion blocking superlattice425extending through the body contact to divide the body contact into a first body contact region421and a second body contact region422. As similarly described above, the second body contact region422has a same conductivity and higher dopant concentration than the first body contact region421. Here again, the body contact dopant diffusion blocking superlattice425may be similar to those superlattice structures described above, and the materials used for, and dopant concentrations within, the first and second body contact regions421,422may also be similar to those described above to provide desired contact resistance reduction.

In another example device400′ shown inFIG. 17, a similar configuration is provided which has a back-side body contact420′ instead of the top-side or front-side body contact420shown inFIG. 16. The remaining components are similar to those discussed with reference toFIG. 16and accordingly require no further discussion herein. It should be noted that in the back-side implementation the first and second regions421′,422′ are flipped vertically with respect to the first and second regions421,422in the device400, as they are on the opposite side of the device400′.

Turning now toFIG. 18, another example contact structure500is now described which may be also be used in certain implementations of source/drain, body, or other contacts to provide reduced Schottky barrier height and thereby decreased contact resistance. The contact500is formed in a semiconductor layer501. The contact illustratively includes one or more oxygen monolayers550constrained within a crystal lattice of adjacent semiconductor portions546a,546bof the semiconductor layer501. The oxygen monolayer(s)550is and spaced apart from a surface of the semiconductor layer501by between one and four monolayers (a four monolayer spacing is shown in the semiconductor portion546bin the illustrated example). Furthermore, a metal layer531(which may include the same metals discussed above) is formed on the surface of the semiconductor layer501above the oxygen monolayer(s)550. The contact500may be formed on a semiconductor layer or substrate521.

By way of example, a dopant concentration within the portion546b(i.e., between the oxygen monolayer(s)550and the metal layer531) may be 1×1021atoms/cm3or greater (although lower concentrations may also be used in different embodiments). Considered alternatively, a dopant concentration equivalent to approximately 2% of the crystalline sites in a silicon lattice may advantageously be occupied by dopant atoms in an example configuration. This is based upon an estimate for the maximum distance range over which the oxygen monolayer can directly trap dopants (e.g., boron) sufficiently close to the metal to directly reduce the Schottky barrier of the contact, as opposed to reducing diffusion, yet while otherwise retaining a conventional doped metal-semiconductor interface with a bulk-line environment for the dopant atoms, and the minimum concentration of dopants where a benefit will be realized.