SELF-ALIGNED FLOATING GATE FORMATION IN NONVOLATILE MEMORY DEVICE FABRICATION

A method for forming floating gates in a non-volatile memory array is disclosed, comprising: patterning and etching portions of a hard-mask dielectric layer, a conductive layer and a tunneling oxide layer to define stacked structures over a substrate; conformally depositing a spacer dielectric layer over the substrate; etching a portion of the spacer dielectric layer to form spacers along sidewalls of each stacked structure; etching a portion of the substrate to form trenches so that the trenches and the stacked structures are alternately arranged in each row; and, growing liners on silicon walls of the trenches. Here, the hard-mask dielectric layer and the spacer dielectric layer comprise an oxidation-blocking material. Accordingly, the poly-silicon floating-gates are encapsulated in the hard-mask dielectric layer and the spacers such that the shapes of floating-gates and the tunneling oxide thickness are well preserved.

BACKGROUND OF THE INVENTION

Field of the Invention

The invention relates to the fabrication method for floating-gate Non-Volatile Memory (NVM) devices. In particular, the process method of this invention resolves the tunneling oxide non-uniformity of NVM cell devices in memory arrays caused by the floating-gate over-oxidation in the self-aligned floating-gate/Shallow Trench Isolation (STI) process for the conventional floating-gate non-volatile memory device fabrication. The self-aligned floating-gate/STI process of this invention not only dramatically improves the floating-gate NVM devices' tunneling oxide uniformity but also extends the capability to scale down the cell device sizes of the floating-gate NVM devices to the minimum feature sizes provided by the advanced nanometer fabrication process technology.

Description of the Related Art

Semiconductor Non-Volatile Memory, and particularly Electrically Erasable, Programmable Read-Only Memories (EEPROM), exhibit wide spread applicability in a range of electronic equipment from computers, to telecommunication hardware, to consumer appliances. In general, EEPROM serves a niche in the NVM space as a mechanism for storing firmware and data that can be kept even with power off and can be altered as needed.

Data is stored in an EEPROM cell device by modulating the threshold voltage (device on/off voltage) of the Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) through the injection of charge carriers into the charge-storage layer from the substrate of the MOSFET device. For example, with respect to an N-channel MOSFET device, an accumulation of electrons in the conducting floating-gate, or in a dielectric layer, or in nano-crystals above the FET channel region, causes the MOSFET device to exhibit a relatively high threshold voltage state. Data is erased in an EEPROM cell device by removing the stored charges from the storage layer.

Flash EEPROM may be regarded as a specifically configured EEPROM into cell array that may be erased only on a global or sector-by-sector basis. Flash EEPROM arrays are also categorized as NOR flash array (parallel connections) and NAND flash array (series connections) according to the configurations of the memory cell device connections in the flash memory arrays. Since the flash EEPROM with poly-silicon floating-gate110for charge storage shown inFIG.1provides high quality of reliable non-volatile data storage the fabrication process technology for floating-gate NVM devices has become the major manufacturing method for NAND flash memory and NOR flash memory.

While in the road of scaling down flash memory for higher density and lower manufacturing cost, the alignment has become the most critical issue for the two process masking steps regarding the formation of floating-gates110and the formation of memory device active areas (devices' channel regions120) in the sub-micron floating-gate NVM fabrication process technology. As the cross-section view of floating-gate NVM devices in memory array shown inFIG.2, the two-mask misalignment between floating-gates110and device active areas120in the memory array could cause devices' functional failure leading to low yields in flash memory manufacturing. To resolve the misalignment issue and improve the flash memory yields, a self-aligned floating-gate/Shallow Trench Isolation (STI) process was first introduced in the sub-micron fabrication process technology. The self-aligned floating-gate/STI process applying only one single floating-gate/active-area mask provides the process method to form floating-gates and memory device active areas in one masking step.

Referring toFIGS.3-4, the process flow brief for the conventional self-aligned floating-gate/STI process are the followings: (1) well formation of NVM device cell array by ion implantation; (2) tunneling oxide140grown on the silicon substrate10for NVM devices' tunneling oxide; (3) poly-silicon film110deposited on top of tunneling oxide140for NVM devices' floating-gate; (4) N-type impurity implanted into the poly-silicon film110for floating-gate conductivity; (5) dielectric material film deposited on the poly-silicon110for the etching hard mask (not shown); (6) the floating-gate/STI mask applied to etch the dielectric material film to form the hard mask patterns (not shown); (7) RIE (Reactive Ion Etch) sequence to etch poly-silicon110/tunneling oxide140/silicon substrate10for forming the self-aligned floating-gates110and the shallow trenches130as the cross-section view as shown inFIG.3; (8) high temperature (ranging from 750° C.˜1100° C.) oxidation process applied for the formation of oxide liners161along the shallow trench walls as shown inFIG.4; (9) oxides deposited on to silicon wafer for filling the shallow trenches130; (10) Chemical Mechanical Polish (CMP) polishing the filled oxides to flatten the silicon wafer surface; (11) field oxide recess etch to the level height of silicon substrate10; (12) hard mask (not shown) stripped to complete the whole self-aligned floating-gate/STI process.

While the conventional self-aligned floating-gate/Shallow Trench Isolation (STI) process has resolved the misalignment issue for NVM devices' floating-gates and active areas, the other fabrication issue in the self-aligned floating-gate/STI process caused by the floating-gate oxidation in the high temperature oxidation process for the formation of trench liners (step (8) in the above process flow brief) has also arisen for the smaller geometrical in the nanometer fabrication process technology. As seen inFIG.4, the oxide shapes of the so-called birds' beaks are grown to enlarge the thickness of tunneling oxide140near the poly-silicon floating-gate edges and shrink the poly-silicon floating-gate dimensions. The somehow less controllable over-grown oxides for the poly-silicon floating-gates110have the tremendous impact on the uniformity of NVM cell devices in memory arrays. In some extreme cases, the floating-gate NVM device with irregular shapes of floating-gate could fail devices' electrical operations (read, programming, and erase) totally, specially for the operations applied with the Fowler-Nordheim tunneling scheme. The irregular shapes of floating-gates for the floating-gate NVM devices in memory array are also one of the major barriers for floating-gate flash memory to scale down the cell device size to the minimum feature sizes provided by the advanced nanometer fabrication process technology.

To resolve the floating-gate over-oxidation issue in the STI trench liner formation process, we add oxidation blocking dielectric spacers along the side walls of floating-gates to encapsulate the poly-silicon floating gates from oxidization during trench oxide liner formation such that the tunneling oxide thickness and the original after-etched floating-gate dimensions are preserved. The added process of this invention can further extend the device scaling capability to the minimum feature cell sizes provided by the advanced nanometer fabrication process technology.

SUMMARY OF THE INVENTION

In order to illustrate the basic idea of this invention, we show the snap shots of silicon cross-section views in the memory arrays after different process steps (fromFIG.5toFIG.11) for the self-aligned floating-gate/STI process.FIG.5shows the cross-section view of silicon wafer in the memory arrays after the process of (1) well formation, (2) growing tunneling oxide210, and (3) depositing poly-silicon film221. A hard mask dielectric film230is then deposited on top of the ploy-silicon film221. The floating-gate/STI mask is applied to etch the hard mask dielectric film230to leave a patterned hard mask (not shown). According to the patterned hard mask, a RIE etch sequence is applied to etch the ploy-silicon film (floating-gate)221and tunneling oxide210stopping at silicon substrate10to form multiple parallel and spaced-apart stacked structures20A as the cross-section view shown inFIG.6. A dielectric film240with oxidation blocking capability is conformally deposited on the silicon surfaces10as the cross-section view shown inFIG.7. The oxidation blocking dielectric film240is then etched to form oxidation blocking dielectric spacers250along the side walls of the floating-gates221(or the side walls of the stacked structures20A) as shown inFIG.8. The RIE for silicon continues to etch the silicon substrate10to form the shallow trenches30as shown inFIG.9. With the oxidation blocking dielectric spacers250on the side walls of floating-gates221, the trench oxide liners310is grown on the trench silicon walls by an oxidation process as shown inFIG.10. The oxidation process for growing the trench oxide liners310includes, but is not limited to, silicon oxidation process, the high temperature (ranging from 750° C.˜1100° C.) oxidation process, and ISSG (In-Situ Steam Generation). Any existing or yet-to-be developed oxidation process may be used for growing the trench oxide liners310.FIG.11shows the final cross-section view of the floating-gates221and the device active areas after (1) oxide deposition for filling trenches, (2) CMP for flattening the silicon surface, (3) oxide recess etch for leveling field oxides320to the silicon substrate10, and (4) hard mask dielectric film230and oxidation blocking dielectric spacers250stripped. Note that due to the oxidation blocking dielectric spacers250along the floating-gate side walls (or the side walls of the stacked structures20A) and the hard mask dielectric film230on top of floating-gates221, the encapsulated floating-gate ploy-silicon are not oxidized during the trench oxide liner formation process such that the shapes of floating-gates221and the tunneling oxide thickness are well preserved.

DETAILED DESCRIPTION OF THE INVENTION

The following detailed description is meant to be illustrative only and not limiting. It is to be understood that other embodiment may be utilized and element changes may be made without departing from the scope of the present invention. Also, it is to be understood that the various dielectric material for hard mask and oxidation blocking dielectric material for spacers used herein are for the purpose of description and should not be regarded as limiting. Any existing or yet-to-be developed oxidation-blocking material may be used for hard mask230and spacers240. Those of ordinary skill in the art will immediately realize that the embodiment of the present invention described herein in the context of methods and schematics are illustrative only and are not intended to be in any way limiting. Other embodiment of the present invention will readily suggest themselves to such skilled persons having the benefits of this disclosure.

In one embodiment, we apply nitride films for the hard mask material230and oxidation blocking material240inFIG.7. It is known that nitride film is a good oxidation blocking material to block oxygen diffusion through nitride film into poly-silicon for oxidation during the high temperature silicon-dioxide grown process. In the embodiment, after nitride hard mask231with a depth of 600 angstroms to 1000 angstroms is deposited on the silicon surface10and then etched into patterns of the floating-gate/STI mask to leave a patterned nitride hard mask (not shown), the cross-section view in arrays is shown inFIG.12. After applying the RIE to etch poly-silicon221and tunneling oxide210stopping at silicon substrate10based on the patterned nitride hard mask to form multiple parallel and space-apart stacked structures20B, another nitride blocking film241with a thickness of 30 angstroms to 100 angstroms is conformally deposited on the silicon surface10as shown inFIG.13. Then the first RIE for etching nitride film stopping at silicon substrate10is applied to etch the nitride blocking film241to form the oxidation blocking nitride spacers251along the floating-gate side walls (or the side walls of the stacked structures20B) shown inFIG.14. The second RIE continues to etch silicon substrate10to form shallow trenches511shown inFIG.15. The silicon wafer is then taken for the silicon oxidation process to form the trench oxide liners611on the trenches' silicon walls as shown inFIG.16. Note that due to the ultra-low permeability for oxygen diffusion into nitride film (231&251), the encapsulated floating-gate ploy-silicon221are not oxidized during the trench oxide liner formation process such that the shapes of floating-gates221and the tunneling oxide thickness are well preserved. Oxides are then deposited on wafer to fill the trenches511followed by a CMP process stopping at nitride hard mask231for flattening silicon surface around the height of nitride hard mask231. An oxide recess etch process is then applied to etch the field oxides711to about the silicon substrate level as the cross-section view shown inFIG.17. After nitride hard mask231and nitride spacers251are stripped for the completion of self-aligned floating-gate/STI process, the cross-section view of floating-gates and device active areas in memory arrays is shown inFIG.18.

In another embodiment, we apply oxynitride for the hard mask material230and nitride for the spacer material240inFIG.7. It is known that oxynitride and nitride can block oxygen diffusion through oxynitride and nitride films into poly-silicon during the high temperature silicon-dioxide grown process. In this embodiment, after oxynitride hard mask191with a depth of 600 angstroms to 1000 angstroms etched into patterns of the floating-gate/STI mask to leave a patterned oxynitride hard mask (not shown), the cross-section view in arrays is shown inFIG.19. After applying the RIE sequence for etching poly-silicon221and tunneling oxide210stopping at the silicon substrate10based on the patterned oxynitride hard mask to form multiple parallel and space-apart stacked structures20C, a nitride blocking film201with a thickness of 30 angstroms to 100 angstroms is conformally deposited on the silicon surface as shown inFIG.20. The first RIE for etching the nitride blocking film201stopping at silicon substrate10is applied to etch the nitride blocking film201to form the nitride spacers212along the floating-gate side walls shown inFIG.21. The second RIE for etching silicon substrate is applied to etch the silicon substrate10to form shallow trenches281in silicon substrate as shown inFIG.22. The silicon wafer is then taken for silicon oxidation process to form the trench oxide liners282on the trenches' silicon walls as shown inFIG.23. Note that due to the ultra-low permeability for oxygen diffusion in oxynitride and nitride, the encapsulated floating-gate ploy-silicon221are not oxidized during the trench oxide liner formation process such that the shapes of floating-gates221and the tunneling oxide thickness are well preserved. The nitride spacers212is then stripped followed by an oxide film deposition to fill the isolation trenches281. A CMP process stopping at oxynitride hard mask191is applied to flatten the silicon surface followed by oxide recess etch process to etch the field oxides283to the silicon substrate level as the cross-section view in memory arrays shown inFIG.24. Finally,FIG.25shows the cross-section view of floating-gate and device active areas in memory arrays after oxynitride hard mask191stripped for the completion of self-aligned floating-gate/STI process.

The aforementioned description of the preferred embodiment of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form or to exemplary embodiment disclosed. Accordingly, the description should be regarded as illustrative rather than restrictive. The embodiment is chosen and described in order to best explain the principles of the invention and its best mode practical application, thereby to enable persons skilled in the art to understand the invention for various embodiment and with various modifications as are suited to the particular use or implementation contemplated. It is intended that the scope of the invention be defined by the claims appended hereto and their equivalents in which all terms are meant in their broadest reasonable sense unless otherwise indicated. The abstract of the disclosure is provided to comply with the rules requiring an abstract, which will allow a searcher to quickly ascertain the subject matter of the technical disclosure of any patent issued from this disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Any advantages and benefits described may not apply to all embodiment of the invention. It should be appreciated that variations may be made in the embodiment described by persons skilled in the art without departing from the scope of the present invention as defined by the following claims. Moreover, no element and component in the present disclosure is intended to be dedicated to the public regardless of whether the element or component is explicitly recited in the following claims.