Method for manufacturing a semiconductor device based on epitaxial growth

This invention relates to a method for manufacturing a semiconductor device and semiconductor manufactured thereby, including growing, from a seed island mesa, an abrupt hetero-junction comprising a semiconductor crystal with few crystal defects on a dissimilar substrate that can be used as light emitting and photovoltaic device.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is the United States National Phase of PCT Patent Application No. PCT/SE2013/050355 filed on 28 Mar. 2013, which claims priority to U.S. Provisional Patent Application No. 61/624,110 filed 13 Apr. 2012, both of which are incorporated herein by reference.

FIELD OF THE INVENTION

The present invention relates to semiconductor devices and manufacturing thereof, in particular the present invention relates to a method for manufacturing a semiconductor device having a hetero structure. The present invention also relates to semiconductor devices manufactured by means of the method.

BACKGROUND

Semiconductor devices can be manufactured for instance by means of so-called “wafer bonding”. Wafer bonding is a packaging technology on wafer-level suitable for the fabrication of for instance micro-electromechanical systems (MEMS), nano-electromechanical systems (NEMS), microelectronics and optoelectronics. Typically, wafer bonding ensures a mechanically stable and hermetically sealed encapsulation. Typically, wafers manufactured, comprising semiconductors, can have a diameter ranging from 100 mm to 200 mm (from 4 inch to 8 inch) for MEMS/NEMS and up to 300 mm (12 inch) for the production of semiconductor devices such as microelectronics and optoelectronics.

Unfortunately, for some applications, the cost of a semiconductor device made by wafer bonding will be high and the yield of the method for manufacturing the device will be low because of limited available wafer size of bonded semiconductors on a substrate, such as a dissimilar substrate. Wafer bonding is also limited to available effective wafer size of the substrate, which is typically much smaller than the regular size of the dissimilar substrate. Conformability between semiconductor material and dissimilar substrate can also be questioned and may in worst case lead to material bonding problems. Failure of bonding between two materials during operation of a semiconductor device could be catastrophic.

Also, other techniques have found application for manufacturing semiconductor devices, such as techniques using epitaxial technology, and in particular “selective epitaxial growth”. This is described for instance in “Multiple Layers of Silicon-on-Insulator Islands Fabrication by Selective Epitaxial Growth, S. Pae, et. al. IEEE ELECTRON DEVICE LETTERS, VOL. 20, NO. 5, MAY 1999”, IEEE.

SUMMARY OF THE INVENTION

According to an aspect of the present invention, there is provided a method for manufacturing a semiconductor device based on epitaxial growth. The size of a semiconductor device that can be manufactured using the method according to the invention will only be determined by the available wafer size of the dissimilar substrate, which typically can be as large as 12 inch for a silicon (Si) substrate. Moreover, conformability between the semiconductor material and the dissimilar substrate is superior to prior art methods due to the inherent characteristic of epitaxial growth.

Herein, the term “semiconductor device” includes any semiconductor device precursor, such as a semiconductor substrate, up to and including a semiconductor device such as a semiconductor laser ready for use.

Herein, the term “dissimilar” means that the grown semiconductor and the substrate are made of different materials.

According to an embodiment of the present invention, there is provided a method for manufacturing a semiconductor device, such as a semiconductor substrate. The method comprises the steps of: forming a buffer layer and a seed layer on a dissimilar semiconductor substrate on a front side thereof, followed by processing to provide one or more seed island mesas, typically having a particular orientation on the dissimilar semiconductor substrate. An insulating mask layer is then formed on the at least one seed island mesa. The insulating mask layer has an opening provided on the seed island mesa. If not, an opening is created in the insulating mask layer. Then a semiconductor growth layer having consecutive semiconductor regions grown onto each other is grown from the opening of the insulating mask layer. The growth is selective: epitaxially, vertically and laterally, wherein a first region having high defect density is only grown vertically from the opening, while the other regions are grown until at least one semiconductor region having low defect density coalesces with the front side of the semiconductor substrate. The first region and a second region of the semiconductor growth layer with high defect density can be removed by etching and a third region with low defect density is not etched, typically protected from etching to prepare a semiconductor layer for semiconductor device fabrication.

In this way, a semiconductor device having a hetero-structure, for instance a semiconductor substrate, with low defect density can be manufactured on a dissimilar substrate.

In general, a mesa is an elevated area of land with a flat top, surrounded on all sides by steep cliffs. Herein, the term “mesa” means an area on a semiconductor substrate where a semiconductor has not been etched away. Typically, a mesa rises above a surrounding semiconductor substrate, and the height of the elevated area is typically a few microns.

In this way, there is provided a method for processing a dissimilar substrate wherein seed island mesas of a semiconductor material is covered by a insulating mask layer, typically an insulating mask over an exposed surface of the seed island mesa. Openings are created in the insulating mask layer. An overgrowth crystalline layer of a semiconductor material is grown, filling the openings, covering the mask on the seed island mesas and then growing both laterally and downward to cover the exposed surface of the dissimilar substrate surrounding of seed island. The region(s) with high defect density in the grown semiconductor layer is/are typically removed by etching and the region(s) with low defect density is/are left behind from etching, or in other words, they are not etched, and semiconductor devices including templates of semiconductor material with low defect density are manufactured on the dissimilar substrate.

Herein, the term “template” means any kind of semiconductor precursor having a semiconductor layer prepared for manufacturing a semiconductor device such as a semiconductor laser diode device.

According to another embodiment of the present invention, there is provided a method for manufacturing a semiconductor device, wherein an insulating mask layer is formed thereon, and an opening is created in the insulating mask layer, herein on top of the mesa islands. Then a semiconductor growth layer having consecutive semiconductor regions grown onto each other is grown from the opening of the insulating mask layer, epitaxially, vertically and laterally, wherein a first region having high defect density is only grown vertically from the opening, while the other regions are grown until at least one semiconductor region having low defect density coalesces with the insulating mask layer72.

Typically, the process steps up to seed island mesa formation, buffer layer, seed layer and seed island mesa formation are the same for the various embodiments of the methods according to the invention.

According to another embodiment of the present invention, there is provided a semiconductor device manufactured by the method disclosed above.

According to another aspect of the present invention, a semiconductor hetero-structure having low defect density comprises a semiconductor layer on a dissimilar substrate manufactured by the method disclosed above. This substrate can be a semiconductor with indirect band-gap. The semiconductor layer can have direct band-gap. Both a conduction and valence band edge energy of the dissimilar substrate semiconductor material is higher than that of the semiconductor layer. The constituent semiconductor materials form a type-II hetero-junction where the electrons are confined on the side of the semiconductor layer with direct band-gap and the holes are confined on the side of the dissimilar substrate with indirect band-gap. The electron and holes recombine radiatively at the interface of hetero-junction due to tunneling effect and light with energy lower than the band-gap of both hetero-junction constituent materials can be emitted. This type-II hetero-junction can be used to absorb photons with energy lower than the band-gap of constituent semiconductors. Electrons in a valence band of the indirect semiconductor are excited to conduction band of direct semiconductor.

Herein the term “hetero-junction” means the interface that occurs between two layers or regions of dissimilar crystalline semiconductors. These semiconducting materials have unequal band gaps. The combination of multiple hetero-junctions together in a device is called a “hetero-structure” although the two terms are commonly used interchangeably. Herein, both terms apply to the invention without reducing the scope of protection. Herein, another definition of the term “hetero-junction” is the interface between any two solid-state materials, including crystalline and amorphous structures of metallic, insulating, fast ion conducting and semiconducting materials.

According to another aspect of the present invention, there is provided a multi-junction solar cell comprising a silicon sub-cell and sub-cells of semiconductors with band-gap matching to solar spectrum, for example GaAs, GaInP, GaP, and Si sub-cells. The sub-cells are electrically serially connected and two electrodes are used to connect the multi-junction solar cell to a load. The Si sub-cell is fabricated into the Si substrate. On top of the Si substrate with the Si sub-cell, semiconductor templates are grown by the invented method. The sub-cells, which are made of semiconductors with suitable band-gaps, are grown on the semiconductor templates on Si. In order to increase efficiency even further, more sub-cells having different band-gaps can be provided.

According to another aspect of the present invention, there is provided a multi-junction solar cell comprising a silicon sub-cell and sub-cells of semiconductors with band-gap matching to solar spectrum, for example GaAs, GaInP, GaP and Si sub-cells. The Si sub-cell and other sub-cells are electrically isolated and are connected to load with separated electrode pairs. The Si sub-cell is fabricated into the Si substrate. On top of the Si substrate with Si sub-cell hetero-structure of semiconductors are grown by the invented method. The sub-cells made of semiconductors with suitable band-gap are grown on the semiconductor hetero-structure on Si.

Embodiments of the present invention will now be described in more detail with reference to the accompanying drawing figures, of which:

DETAILED DESCRIPTION OF THE INVENTION

The present invention will be described below with reference to the accompanying drawings. The same or similar parts are mainly denoted by the same reference numerals throughout the drawings.

FIG. 1aillustrates a schematic sectional view of a semiconductor device, herein a substrate, being manufactured by means of the method according to an embodiment of the present invention. Herein, it is also referred toFIG. 9illustrating the method step by step in a flow chart. First of all, a dissimilar substrate50made of for example Si is provided (not illustrated inFIG. 9). A buffer layer52made of, for example, GaAs is formed,100a, for instance grown at low temperature by Molecular Beam Epitaxy (MBE) or MOVPE, on a front side50aof the substrate50. Herein, the term “MOVPE” is an acronym for Metal Organic Vapor Phase Epitaxy (MOVPE), also known as Organometallic Vapour Phase Epitaxy or Metal Organic Chemical Vapor Deposition (MOCVD). Then on top of the buffer layer52, a seed layer54made of, for example, InP is formed,100a, for instance grown by MOVPE. The buffer layer52can have a thickness of 100 nm or more and the seed layer54can have thickness of 1 μm or more. Because of a large lattice mismatch between Si and InP, the seed layer54can have high defect density, including defects such as threading dislocation, and stacking faults. The seed layer54and buffer layer52are processed,100b, to one or more seed island mesa(s)51, of which only one mesa51is illustrated, by conventional photolithography and etching. Then, an insulating mask layer62, such as a selective growth mask layer, made of, for example, a layer of SiO2having a thickness of 300 Å or more is formed,101, for instance deposited by PECVD (Plasma-enhanced chemical vapor deposition). The insulating mask layer62, is processed to cover a top surface (explained in more detail with reference toFIG. 2b) and sidewalls (explained in more detail with reference toFIG. 2b) of the mesa51, wherein a surface portion50aof the substrate50not covered by the mesa(s)51or the insulating mask layer62is exposed. Then, an opening58is created,102, in the insulating mask layer62and the surface portion54aof the seed layer54is exposed in the opening58. Then, a semiconductor growth layer80made of, for example InP, is grown,103, from the opening58, from the exposed surface portion54aof the seed layer54on the mesa51for instance by using gaseous group III and V element sources. The semiconductor growth layer80first grows vertically to form a first semiconductor region80I. Dislocations in the seed layer54will grow into the first semiconductor region80I and extend to an outer surface of growth of the grown semiconductor growth layer80. When the grown semiconductor growth layer80becomes thicker than the thickness of the insulating mask layer62, the growth will extend laterally over the insulating mask layer62and form a second semiconductor region80II. A defect density in the second semiconductor region80II is lower than a defect density in the seed layer54. Especially, a third semiconductor region80III of the semiconductor growth layer80adjacent to the insulating mask layer62has much higher crystal quality than in the first growth region80I close to the surface portion54aof the seed layer54in the second growth region80II. This is indicated by the whole first semiconductor region (80I, and part of the second region80II, but not the third region80III being oblique stroked and labeled “dislocation” intended to illustrate that dislocations are not present in the third semiconductor region80III, but only in the first and second semiconductor regions80I and80II. When the semiconductor growth layer80continues to grow laterally and exceeds an edge of the mesa51covered by the insulating mask layer62, the semiconductor layer80will grow both laterally and vertically, and toward the front side50aof the substrate50, which will form the third semiconductor region80III of the semiconductor growth layer80. The growth in the third semiconductor region80III can be viewed as seeded from the semiconductor growth layer80adjacent to the insulating mask layer62in the second growth region80II, which has high crystal quality. In addition the growth direction of the semiconductor growth layer80in the third growth region80III is opposite to the direction of threading dislocation originated from the seed layer54. The growth of the semiconductor growth layer80in the third semiconductor region80III will therefore have very low defect density. When the growth of the semiconductor growth layer80continues, contact between the semiconductor growth layer80and the substrate50is created in a semiconductor layer81adjacent to the mesa51and the growth of the semiconductor growth layer80will extend laterally over the substrate50. This will be described and illustrated in more detail as follows.

Typically, a plurality of contacts will be provided of a plurality of mesas. Since the semiconductor growth layer80is not deposited on the substrate50directly but rather by a homo-epitaxial mechanism, no dislocations, such as misfit dislocations and associated threading dislocations will be created at the interface50abetween the substrate50and the third semiconductor region80III in the semiconductor growth layer80.

InFIGS. 1 to 6, only one of a plurality of mesas51is illustrated as an example, but the invention is by no means limited to only one mesa51.

The dissimilar substrate50is not specifically limited to the example described above as long as it is made of a material different from the grown semiconductor growth layer80. For example, a substrate50made of Si can be used for the growth of III-V semiconductors; an insulating substrate like a sapphire substrate having a C plane ((0001) plane), an R plane ((1102) plane), or an A plane ((1120) plane) as a major surface or spinnel (MgAl2O4), and SiC (including 6H, 4H, and 3C), a ZnS substrate, a GaAs substrate, or a Si substrate can be used for the growth of nitride semiconductors.

As seen in a left inset ofFIG. 1b, in order to have a high aspect ratio between vertical growth rate and lateral growth rate for the semiconductor growth layer80, the orientation angle α of the mesa51of the seed layer54and the buffer layer52has to be selected carefully according to an embodiment of the present invention to a particular orientation angle α.

For example, for the growth of a GaxIn1−xAsyP1−y (0<x<1; 0<y<1) on a (001) Si substrate, the mesas51have to be oriented along an orientation angle α from a crystal direction <110>. According to an embodiment, the orientation angle α can be between 0 to ±45 degrees. Typically, the orientation angle α is selected according to a crystalline plane of the substrate and growth parameters, such as temperature, dopant, pressure, etc. According to an embodiment of the present invention, the openings58in the insulating mask layer62on top60of the seed island mesas51are oriented at the same direction as the mesas51.

FIGS. 2ato2gare sectional views for further explaining the principle of a method for manufacturing a semiconductor according to an embodiment of the present invention essentially step by step, wherein a few steps are illustrated in combination. InFIGS. 2ato2g, the process flow how to manufacture a hetero-structure comprising a semiconductor substrate50and lattice mismatched grown semiconductor layer with very low defect density is illustrated. As seen inFIG. 2a, buffer layer52made of, for example GaAs, is formed,100a, for instance grown, or has been grown, on the substrate50, such as a (001) Si substrate by MOPVE at low temperature. The seed layer54made of, for example InP is, or has been, continuously grown by MOVPE and can have a thickness of approximately 2 μm. A protective mesa mask56made of, for example SiO2or SiNxis, or has been, deposited by PECVD and patterned to a plurality of stripes by photolithography. Typically, the protective mesa mask56can have thickness of more than 300 Å and a width corresponding to a desired mesa width.

As illustrated inFIG. 2b, the seed layer54and the buffer layer52are, or have been, processed,100b, to a plurality of, herein two, mesas51typically by dry etching. A insulating mask layer62made of, for example Si3N4, has been formed over the substrate50and the protective mesa mask56, and is typically deposited by PECVD. The insulating mask layer62can have a thickness of more than 300 Å.

As illustrated inFIG. 2c, the insulating mask layer62is, or has been, etched by SF6and CH4in a reactive ion etching reactor. Chemical CHF3can also be used to etch the insulating mask layer62in the reactive ion etching reactor. The insulating mask layer62is etched away completely from a top surface60of the mesas51and the substrate50, whereas the insulating mask layer62on the side walls60a, bof the mesas51is protected, for instance by polymers formed during etching and is intact after etching. Thus, the top surface60of the mesa51and the front side50aof the substrate50can be exposed. The front side50aof the substrate50can be exposed by processes such as photolithography with photoresist reflow and chemical or dry etching of the insulating mask layer62.

As illustrated inFIG. 2d, a plurality of openings58are, or have been, created,102, by photolithography and etched in the insulating mask layer62. As illustrated inFIG. 2e, epitaxial growth of the semiconductor growth layer80made of, for example InP is carried out,103, in Hydride Vapor Phase Epitaxy (HVPE). The front side50aof the substrate50made of, for example Si is cleaned properly before the substrate50being brought to an HVPE growth chamber. A solution of H2SO4:H2:O2and NH4OH:H2O2is used to remove the organic impurities and particles. Following a wet chemical ex-situ cleaning process, the substrate50made of Si is dipped in a solution of 1HF:10H2O for 10 seconds to remove oxide. As an example, the growth temperature in the HVPE growth chamber is 620° C. and the pressure is 20 mBar. With sufficient growth time, which is obvious to the skilled person, the selective growths from adjacent mesas51will result in wide third semiconductor regions80III, which will coalesce to form a continuous grown semiconductor layer81on the front side50aof the substrate50.

As illustrated inFIG. 2f, the vertical and lateral growth portion of the semiconductor growth layer80is etched away by for example, chemical mechanical etching. The etching process is stopped at the top surface60of the growth layer. A surface81aof the grown semiconductor layer81, which is the vertical growth of the third semiconductor region80III of the semiconductor growth layer80, is further polished to an epi-ready surface, by means of a polishing method, known to the skilled person per se, which polishing method provides low metal contamination from the polishing and a surface roughness of 2-3 Å. Herein, epi-ready means that the carbon and native oxide layers on the epi-ready surface can be removed by in situ cleaning in an MOVPE reactor.

As seen inFIG. 2g, according to an embodiment of the present invention, the mesa51of the seed layer54and buffer layer52and insulating mask layer62are, or have been, etched away by chemical etching after the grown semiconductor layer81has been protected by a photo-resist. The grown semiconductor layer81has very low defect density and an abrupt hetero-junction105is formed between the semiconductor layer81and the front side50aof the substrate50. This hetero-junction105can be used in a semiconductor device as an active structure, for example as a light emission region in a laser diode or a light emitting diode and absorption region for photons with energy lower than the constituent semiconductors in a light sensitive semiconductor device such as a photodiode, solar cell, or photo-detector. This hetero-junction105can alternatively be used to manufacture an avalanche photodiode where the grown semiconductor layer81is configured for light absorption and the dissimilar substrate50is used for electron impact ionization. The grown semiconductor layer81can also be used as a substrate for manufacturing semiconductor device fabrication, for example laser diode, photodiode, high speed field effect transistor (FET) made of III-V semiconductor on silicon substrate50. Other examples are high power electronic devices having wide band-gap GaN materials on silicon for electronics.

FIGS. 2hto2jare sectional views intended to explain the application of the method for manufacturing a semiconductor according to an embodiment of the invention on a corrugated dissimilar substrate surface50. As illustrated inFIG. 2h, a plurality of corrugations70are created on the front side50aof the dissimilar substrate50before the grown semiconductor layer81is fabricated. The corrugations70can have any kinds of shape, dimension, and depth. The corrugations70can be repeated in any kinds of manner on the front side50aof the dissimilar substrate.FIG. 2iillustrates a cross section along a line A-A′ of the dissimilar substrate having the corrugations70providing a corrugated surface. The method steps for manufacturing the semiconductor layer81that is explained inFIGS. 2eto2gcan be carried out also on a corrugated surface of the dissimilar substrate50. The grown semiconductor layer81will then fill up the corrugations70on the dissimilar substrate50as illustrated inFIG. 2j.

FIGS. 3ato3fare sectional views for explaining an alternative method for manufacturing a semiconductor device according to another embodiment of the present invention. Herein, it is also referred toFIG. 10which is a flow-chart illustrating the method steps. The process flow to manufacture a hetero-structure comprising a dissimilar substrate50, an insulating mask layer72and a grown semiconductor layer91with low defect density is illustrated.

As shown inFIG. 3a, buffer layer52made of, for example GaAs, is grown,100a, on a substrate50, such as a (001) Si substrate by MOPVE at low temperature. The seed layer54made of, for example InP is continuously grown by MOVPE and can have a thickness of approximately 2 μm. A protective mesa mask56made of, for example SiO2is deposited,101, by PECVD and patterned to stripes, of which two are illustrated, by photolithography. The mesa mask56can have thickness of more than 300 Å.

As shown inFIG. 3b, after the buffer layer52and seed layer54are processed,100b, to a mesa51by a photolithography and etching process, for example, reactive ion etching, an insulating mask layer, or isolator72, for example Si3N4is deposited,101b, on the whole substrate50by PECVD. As shown inFIG. 3c, openings58bare created,102, in the insulating mask layer72on top of the buffer and seed layer52,54to expose a surface region54aof the seed layer54.

As shown inFIG. 3d, a semiconductor layer90made of, for example InP, is grown,103, by hydride vapor phase epitaxy (HVPE). After sufficient growth time, the selective growth from adjacent mesas51will combine to form a uniform grown semiconductor layer90.

As seen inFIG. 3e, the vertical and lateral growth portions of the semiconductor layer90are etched by, for example chemical mechanical etching. The etching stopped at the surface72aof the insulating mask layer72. The surface91aof the grown semiconductor layer91is polished to be epi-ready.

As seen inFIG. 3f, the mesa51of the seed layer54and the buffer layer52and the side walls70a, bof the insulating mask layer72are etched away after the grown semiconductor layer91is, or has been, protected by photo-resist and processed by photolithography. A hetero-structure comprising a dissimilar substrate50, an insulating mask layer72and a grown semiconductor layer91with very low defect density is manufactured.

As is obvious from the above description, the grown semiconductor layers91, grown by the method of the present invention have very few defects, and can effectively be used as semiconductor devices, such as substrates for supporting a predetermined semiconductor device thereon, providing a “semiconductor on insulator structure”. For instance, the “semiconductor on insulator structure” has the advantage of low parasitic capacitance, which provides a superior structure for high speed electronic devices compared to prior art structures.

The predetermined semiconductor device to be supported on the semiconductor structures of the present invention is not specifically limited as long as it has a predetermined device function, typically a hetero-junction, and includes a laser diode device structure, a multi-junction solar cell device, and the like. However, the devices are not limited to any of these examples mentioned.

FIG. 4is a schematic sectional view showing a laser diode (LD) device formed on a semiconductor device manufactured according to the present invention. As illustrated inFIG. 4, the semiconductor substrate50is made of at room temperature degenerately doped p-type Si. The grown semiconductor layer81is made of sulfur doped or undoped GaxIn1−xAsyP1−y (0<x<1; 0<y<1) and manufactured by the method according to an embodiment of the present invention. The GaxIn1−xAsyP1−y semiconductor layer81has a thickness of <2 μm. The undoped GaxIn1−xAsyP1−y layer81is further doped by diffusion or implantation of n type impurity, e.g. S to have degenerated dopant concentration at room temperature. An n-side contact layer27, preferably made of n-type InP doped with n-type impurity, e.g., S is formed on the semiconductor layer81. An n-electrode8is formed on the entire surface of the n-side contact layer27. The substrate50is thinned down to 100 μm. The rear-side50bof the substrate50is shallow implanted with p-type dopant such as B or Ga to form a heavily doped rear-side contact region6upon annealing and dopant activation. A p-side electrode2is formed on the rear-side contact region6. A facet of laser diode is formed by cleaving and light emits from an edge of the device. As illustrated inFIG. 4, an abrupt hetero-junction105, on the front side50a, is formed between the substrate50and the grown semiconductor layer81.

As shown inFIG. 5, the hetero-junction105can have type-II staggered band lineup if the substrate50is made of Si and the grown semiconductor layer81is made of GaxIn1−xAsyP1−y where an alloy composition ratio x and y are selected to rise the electron affinity of the grown semiconductor layer81higher than 4.01 eV, which is the electron affinity of Si. This combination of materials both makes the conduction and the valence band edges of Si shifted upward relative to GaxIn1−xAsyP1−y, and the residual gap at an interface of the hetero-junction105is labeled “Er”. As illustrated inFIG. 6, both n-type GaxIn1−xAsyP1−y semiconductor layer81and p-type Si substrate50are doped degenerately. Under forward bias Vapp, the band bends at the interface of hetero-junction105. Two types of carrier confinement wells develop on the two sides of the interface. Associated with a well formation, free electrons and holes accumulate in the wells. The interface of the GaxIn1−xAsyP1−y/Si hetero-junction obtained by the present invention is sufficiently abrupt. Because of tunneling effect across the interface, the wave functions of the electrons and holes will overlap strongly. The high concentration of accumulated electron-hole pairs in the spatially separated wells can have efficient radiative recombination, although Si is an indirect-band gap semiconductor.

FIG. 7schematically illustrates a cross-section of a multi-junction solar cell device including a Si sub-cell180, a GaAs sub-cell202, and an InGaP sub-cell206formed on the semiconductor substrate according to an embodiment of the present invention. Prior to the growth of the buffer layer52and seed layer54in MOVPE as illustrated inFIG. 2b, the Si substrate50is processed to a Si sub-cell as illustrated inFIGS. 8aand8b. As illustrated inFIG. 8a, a front surface300ais implanted by a beam310with an n-type dopant such as P or As. An n-type emitter region300is formed by annealing and dopant activation at elevated temperature. Other alternatives may include diffusion instead of implantation and annealing. The depth of the emitter region300is thin and no more than 1 μm. The front surface300aof the Si substrate is further doped with a higher dose n-type dopant beam320by implantation with annealing and dopant activation or diffusion to form a heavily doped surface region305to facilitate electrical contact, as illustrated inFIG. 8b. The thickness of the heavily doped surface region305is thin and no more than 100 nm. Thus, a silicon p-n solar sub-cell180is formed. A p+-GaAs semiconductor layer81is grown, by the method of the present invention described with reference toFIGS. 1a, band2a-g, on top of the substrate50made of p-type Si with p-n solar sub-cell180. After the growth of the p+-GaAs semiconductor layer81by the method according to an embodiment of the present invention, a GaAs sub-cell202and an InGaP sub-cell206can be manufactured on the p+-GaAs semiconductor layer81just as is done in a conventional triple junction solar cell. The GaAs sub-cell and InGaP sub-cell are connected by a tunnel junction204made of heavily doped n+ and p+InGaP. On top of the InGaP sub-cell a window layer208made of n+-InAlP and a contact layer210made of n+-GaAs are grown. The n+-GaAs contact layer210is processed to have openings (grey area), where an AR coating211is deposited. On top of the n+-GaAs contact layer210an n contact212is formed. After thinning the Si substrate50down to 100 μm, the rear-side50bof the p-type Si substrate50is shallow implanted with p-type dopant such as B or Ga to form a heavily doped rear side contact region6upon annealing and dopant activation. A p-side electrode6ais formed on the rear-side contact region6.

FIG. 11schematically shows a cross-section of a multi-junction solar cell device according to an embodiment of the present invention, including an Si sub-cell180, a GaAs sub-cell202, and an InGaP sub-cell206formed on the semiconductor device50, herein a substrate of the second embodiment of the present invention illustrated and described with reference toFIGS. 3a-3f. Prior to the growth of the buffer layer52and seed layer54in MOVPE as illustrated inFIG. 2b, the Si substrate50is processed to a Si sub-cell as illustrated inFIGS. 8aand8b. As illustrated inFIG. 8a, the front surface300ais implanted by a beam310with an n-type dopant such as P or As. An n-type emitter region300is formed by annealing and dopant activation at elevated temperature. Other alternatives may include diffusion instead of implantation and annealing. The depth of the n-type emitter region300is thin and no more than 1 μm. The front surface300aof the Si substrate is further doped with a higher dose n-type dopant beam320by implantation with annealing and dopant activation or diffusion to form a heavily doped surface region305to facilitate electrical contact, as illustrated inFIG. 8b. The thickness of the heavily doped surface region305is thin and no more than 100 nm. In this way, a silicon p-n solar sub-cell180is formed onto which an insulating layer, or insulator72is provided. A p+-GaAs semiconductor layer91is grown, by the method of the present invention described with reference toFIGS. 1a-band2a-g, on top of the substrate50made of p-type Si with p-n solar sub-cell180. After the growth of the p+-GaAs semiconductor layer91by the method according to an embodiment of the present invention, a GaAs sub-cell202and an InGaP sub-cell206can be fabricated on the p+-GaAs semiconductor layer91just as is done in a conventional triple junction solar cell. GaAs sub-cell and an InGaP sub-cell204is connected by a tunnel junction made of heavily doped n+ and p+InGaP. On top of the InGaP sub-cell204a window layer208made of n+-InAIP and contact layer210made of n+-GaAs are grown. The n+-GaAs contact layer210is processed to have openings211, where an AR coating is deposited. On top of the n+-GaAs contact layer210an n-contact IIIV212is formed. A via opening is formed through the stacking of epitaxial layers to the surface of p+-GaAs semiconductor layer91and the heavily doped surface region n+-Si305is exposed respectively. A p contact IIIV213is formed on top of the p+-GaAs semiconductor91and an n-contact Si214is formed on top of the surface region n+-Si305. After thinning the Si substrate50down to 100 μm, the rear-side215of the p-type Si substrate50is shallow implanted with p-type dopant such as B or Ga to form a heavily doped rear-side contact region6upon annealing and dopant activation. A p-side electrode p contact Si216is formed on the rear-side contact region6. The n/p contact Si214,216and n/p contact IIIV212,213are connected to load separately. Current matching between silicon bottom cell and sub-cells of the so-called “compound semiconductor” is not necessary. High short circuit current of silicon sub-cell will contribute to the total conversion efficiency more efficiently.

The method can be used for manufacturing compound semiconductor light emitting and photovoltaic devices on silicon substrate.