Forming phase change memory arrays

A phase change memory may be formed to have a dimension that is sub-lithographic in one embodiment by forming a surface feature over the phase change material, and coating the surface feature with a mask of sub-lithographic dimensions. The horizontal portions of the mask and the surface feature may then be removed and the remaining portions of the mask may be used to define a dimension of said phase change material. Another dimension of the phase change material may be defined using an upper electrode extending over said phase change material as a mask to etch the phase change material.

BACKGROUND

This invention relates generally to memory devices and, particularly, to memory devices using phase change materials.

Phase change memory devices use phase change materials, i.e., materials that may be electrically switched between a generally amorphous and a generally crystalline state, as an electronic memory. One type of memory element utilizes a phase change material that may be, in one application, electrically switched between generally amorphous and generally crystalline local orders or between the different detectable states of local order across the entire spectrum between completely amorphous and completely crystalline states.

Typical materials suitable for such an application include various chalcogenide elements. The state of the phase change materials is also non-volatile. When the memory is set in either a crystalline, semi-crystalline, amorphous, or semi-amorphous state representing a resistance value, that value is retained until reprogrammed, even if power is removed. This is because the program value represents a phase or physical state of the memory (e.g., crystalline or amorphous).

Thus, there is a need for alternate ways to provide phase change memories.

DETAILED DESCRIPTION

Referring toFIG. 1, a phase change memory10may include bitlines12, indicated as BL1and BL2, and wordlines14, indicated as WL1and WL2. Of course an orthogonal array of wordlines and bitlines may be provided which includes a much larger number of wordlines and bitlines than those depicted inFIG. 1. In addition, while the terms “wordline” and “bitline” are used herein, any addressing line may be utilized in some embodiments of the present invention. Through the addressing lines12and14, a particular cell represented by a stack16may be addressed. The stack16may include layers of material, including at least one layer which includes a phase change memory material.

Each stack16may have an extremely small critical dimension or width in the bitline direction and a somewhat greater length extending in the wordline direction in one embodiment. Because of the extremely small dimension in at least one direction, a large number of cells may be contained in a relatively small footprint in some embodiments of the present invention.

A memory array corresponding to that shown inFIG. 1may be fabricated beginning with the structure shown inFIG. 2. The wordlines14have already been formed over a substrate18. In one embodiment, the wordlines14may be formed by trenching an insulating layer15and depositing a conductive material, such as copper, in the trenches. The structure may be planarized to form the wordlines14that extend into the page inFIG. 2.

The phase change memory stack16may be defined over the wordlines14. In one embodiment of the present invention, the stack16may include at least two electrodes and at least one layer of phase change memory material. In addition, in some embodiments, the stack16may also include an access device such as an MOS transistor, a diode, or a permanently programmed phase change memory element.

Over the stack16is formed a sacrificial film portion20. One film portion20may be aligned over adjacent pairs of wordlines14. The film portion20may be overcoated with a hard mask22in one embodiment of the present invention. The sacrificial film portion20may be formed of nitride in one embodiment of the present invention. The hard mask22may be an oxide, for example.

As shown inFIG. 3, the horizontal portions of the hard mask22may be etched back. Once the sacrificial film portion20is exposed, the sacrificial film portion20may be removed by a selective etch, leaving the vertical remnants22aand22bof the hard mask22. Thus, the hard mask remnants22aand22bmay be utilized as a mask to define one dimension of two phase change memory stacks16.

Referring toFIG. 4, showing the same structure shown inFIG. 3viewed along the direction of the wordline14, the hard mask remnants22aand22bare longer in the wordline direction (FIG. 4) than they are in the direction transverse thereto (FIG. 3) in this embodiment.

A self-aligned etch may be utilized to etch the stack16. Thereafter, the remnants22may be removed. As a result of the self-aligned etch, thin self-aligned stacks16are formed as shown inFIG. 5, aligned underneath what was the hard mask remnants22aand22b. The stacks16may be relatively thin in the direction transverse to the length of the wordlines14because the hard mask remnants22aand22bwere quite thin in that direction as well. By using the remnants22of a thin hard mask22as the etch mask, stacks16with a sub-lithographic dimension may be formed.

As shown inFIG. 5, the stacks16may be covered by an encapsulation layer24in one embodiment of the present invention. The encapsulation layer24may be a nitride material or other material to prevent oxygen or moisture infiltration into the phase change material included in the stack16.

After the encapsulation layer24has been formed, the structure may be covered with a dielectric film material26as shown inFIG. 6. The deposited film material26may then be subjected to a planarization step, such as chemical mechanical planarization.

Thereafter, a damascene process may be utilized to form the bitlines12in one embodiment. Trenches27may be formed through the film material26down to the upper surface of the encapsulation layers24and ultimately down to the top of the stacks16as shown inFIG. 7. The trenches27may then be filled with a conductive material such as copper to form the bitlines12as shown inFIG. 9.

To reduce the number of masks, the bitlines12may be used to pattern the stacks16in the direction along the lengths of the wordlines14in a self-aligned etch. The width of the stack16along the column direction is still defined by the spacer hard mask22. However, in a damascene process, the bitline12can be used as a mask to define the stack16along the row direction as shown inFIGS. 8 and 10. Alternatively, in a process technology with aluminum bitlines, photoresists may be patterned by a column mask used to form the column and the stack in a self-aligned etch.

In one embodiment of the present invention, just three masks are needed for the process. Moreover, the second mask, which defines the position of the spacer hard mask, is the only one that requires critical registration in one embodiment.

In accordance with another embodiment of the present invention, the stack16may be arranged in a circular or tubular column instead of a rectangular arrangement. Other shapes may be utilized as well.

Referring toFIG. 11, the stack16may include a selection device58formed of a phase change material including a top electrode71, a phase change material72, and a bottom electrode70in one embodiment. The selection device58may be permanently in the reset state in one embodiment. While an embodiment is illustrated in which the selection device58is positioned over the phase change memory element56, the opposite orientation may be used as well.

Conversely, the phase change memory element56may be capable of assuming either a set or reset state, explained in more detail hereinafter. The phase change memory element56may include an insulator62, a phase change memory material64, a top electrode66, and a barrier film68, in one embodiment of the present invention. A lower electrode60may be defined within the insulator62in one embodiment of the present invention.

In one embodiment, the phase change material64may be a phase change material suitable for non-volatile memory data storage. A phase change material may be a material having electrical properties (e.g., resistance) that may be changed through the application of energy such as, for example, heat, light, voltage potential, or electrical current.

Examples of phase change materials may include a chalcogenide material or an ovonic material. An ovonic material may be a material that undergoes electronic or structural changes and acts as a semiconductor once subjected to application of a voltage potential, electrical current, light, heat, etc. A chalcogenide material may be a material that includes at least one element from column VI of the periodic table or may be a material that includes one or more of the chalcogen elements, e.g., any of the elements of tellurium, sulfur, or selenium. Ovonic and chalcogenide materials may be non-volatile memory materials that may be used to store information.

In one embodiment, the memory material64may be chalcogenide element composition from the class of tellurium-germanium-antimony (TexGeySbz) material or a GeSbTe alloy, although the scope of the present invention is not limited to just these materials.

In one embodiment, if the memory material64is a non-volatile, phase change material, the memory material may be programmed into one of at least two memory states by applying an electrical signal to the memory material. An electrical signal may alter the phase of the memory material between a substantially crystalline state and a substantially amorphous state, wherein the electrical resistance of the memory material64in the substantially amorphous state is greater than the resistance of the memory material in the substantially crystalline state. Accordingly, in this embodiment, the memory material64may be adapted to be altered to a particular one of a number of resistance values within a range of resistance values to provide digital or analog storage of information.

Programming of the memory material to alter the state or phase of the material may be accomplished by applying voltage potentials to the lines12and14, thereby generating a voltage potential across the memory material64. An electrical current may flow through a portion of the memory material64in response to the applied voltage potentials, and may result in heating of the memory material64.

This heating and subsequent cooling may alter the memory state or phase of the memory material64. Altering the phase or state of the memory material64may alter an electrical characteristic of the memory material64. For example, resistance of the material64may be altered by altering the phase of the memory material64. The memory material64may also be referred to as a programmable resistive material or simply a programmable resistance material.

In one embodiment, a voltage potential difference of about 0.5 to 1.5 volts may be applied across a portion of the memory material by applying about 0 volts to a line14and about 0.5 to 1.5 volts to the line12. A current flowing through the memory material64in response to the applied voltage potentials may result in heating of the memory material. This heating and subsequent cooling may alter the memory state or phase of the material.

In a “reset” state, the memory material may be in an amorphous or semi-amorphous state and in a “set” state, the memory material may be in a crystalline or semi-crystalline state. The resistance of the memory material in the amorphous or semi-amorphous state may be greater than the resistance of the material in the crystalline or semi-crystalline state. The association of reset and set with amorphous and crystalline states, respectively, is a convention. Other conventions may be adopted.

Due to electrical current, the memory material64may be heated to a relatively higher temperature to amorphisize memory material and “reset” memory material. Heating the volume or memory material to a relatively lower crystallization temperature may crystallize memory material and “set” memory material. Various resistances of memory material may be achieved to store information by varying the amount of current flow and duration through the volume of memory material.

The information stored in memory material64may be read by measuring the resistance of the memory material. As an example, a read current may be provided to the memory material using opposed lines12,14and a resulting read voltage across the memory material may be compared against a reference voltage using, for example, a sense amplifier. The read voltage may be proportional to the resistance exhibited by the memory storage element.

In order to select a stack16on a bitline12and wordline14, the selection device58for the selected cell at that location may be operated. The selection device58activation allows current to flow through the memory element56in one embodiment of the present invention.

In a low voltage or low field regime A, the device58is off and may exhibit very high resistance in some embodiments. The off resistance can, for example, range from 100,000 ohms to greater than 10 gigaohms at a bias of half the threshold voltage. The device58may remain in its off state until a threshold voltage VTor threshold current ITswitches the device58to a highly conductive, low resistance on state. The voltage across the device58after turn on drops to a slightly lower voltage, called the holding voltage VHand remains very close to the threshold voltage. In one embodiment of the present invention, as an example, the threshold voltage may be on the order of 1.1 volts and the holding voltage may be on the order of 0.9 volts.

After passing through the snapback region, in the on state, the device58voltage drop remains close to the holding voltage as the current passing through the device is increased up to a certain, relatively high, current level. Above that current level the device remains on but displays a finite differential resistance with the voltage drop increasing with increasing current. The device58may remain on until the current through the device58is dropped below a characteristic holding current value that is dependent on the size and the material utilized to form the device58.

In some embodiments of the present invention, the selection device58does not change phase. It remains permanently amorphous and its current-voltage characteristics may remain the same throughout its operating life.

As an example, for a 0.5 micrometer diameter device58formed of TeAsGeSSe having respective atomic percents of 16/13/15/1/55, the holding current may be on the order of 0.1 to 100 micro-ohms in one embodiment. Below this holding current, the device58turns off and returns to the high resistance regime at low voltage, low field. The threshold current for the device58may generally be of the same order as the holding current. The holding current may be altered by changing process variables, such as the top and bottom electrode material and the chalcogenide material. The device58may provide high “on current” for a given area of device compared to conventional access devices such as metal oxide semiconductor field effect transistors or bipolar junction transistors.

In some embodiments, the higher current density of the device58in the on state allows for higher programming current available to the memory element56. Where the memory element56is a phase change memory, this enables the use of larger programming current phase change memory devices, reducing the need for sub-lithographic feature structures and the commensurate process complexity, cost, process variation, and device parameter variation.

One technique for addressing the array uses a voltage V applied to the selected bitline12and a zero voltage applied to the selected wordline14. For the case where the device56is a phase change memory, the voltage V is chosen to be greater than the device58maximum threshold voltage plus the memory element56reset maximum threshold voltage, but less than two times the device58minimum threshold voltage. In other words, the maximum threshold voltage of the device58plus the maximum reset threshold voltage of the device56may be less than V and V may be less than two times the minimum threshold voltage of the device58in some embodiments. All of the unselected rows and columns may be biased at V/2.

With this approach, there is no bias voltage between the unselected rows and unselected columns. This reduces background leakage current.

After biasing the array in this manner, the memory elements56may be programmed and read by whatever means is needed for the particular memory technology involved. A memory element56that uses a phase change material may be programmed by forcing the current needed for memory element phase change or the memory array can be read by forcing a lower current to determine the device56resistance.

For the case of a phase change memory element56, programming a given selected bit in the memory10can be as follows. Unselected rows and columns may be biased as described for addressing. Zero volts is applied to the selected row. A current is forced on the selected column with a compliance that is greater than the maximum threshold voltage of the device58plus the maximum threshold voltage of the device56. The current amplitude, duration, and pulse shape may be selected to place the memory element56in the desired phase and thus, the desired memory state.

Reading a phase change memory element56can be performed as follows. Unselected rows and columns may be biased as described previously. Zero volts is applied to the selected row. A voltage is forced at a value greater than the maximum threshold voltage of the device58, but less than the minimum threshold voltage of the device58plus the minimum threshold voltage of the element56on the selected column. The current compliance of this forced voltage is less than the current that could program or disturb the present phase of the memory element56. If the phase change memory element56is set, the access device58switches on and presents a low voltage, high current condition to a sense amplifier. If the element56is reset, a larger voltage, lower current condition may be presented to the sense amplifier. The sense amplifier can either compare the resulting column voltage to a reference voltage or compare the resulting column current to a reference current.

The above-described reading and programming protocols are merely examples of techniques that may be utilized. Other techniques may be utilized by those skilled in the art.

To avoid disturbing a set bit of memory element56that is a phase change memory, the peak current may equal the threshold voltage of the device58minus the holding voltage of the device58that quantity divided by the total series resistance including the resistance of the device58, external resistance of device56, plus the set resistance of device56. This value may be less than the maximum programming current that will begin to reset a set bit for a short duration pulse.

Turning toFIG. 12, a portion of a system500in accordance with an embodiment of the present invention is described. System500may be used in wireless devices such as, for example, a personal digital assistant (PDA), a laptop or portable computer with wireless capability, a web tablet, a wireless telephone, a pager, an instant messaging device, a digital music player, a digital camera, or other devices that may be adapted to transmit and/or receive information wirelessly. System500may be used in any of the following systems: a wireless local area network (WLAN) system, a wireless personal area network (WPAN) system, or a cellular network, although the scope of the present invention is not limited in this respect.

System500may include a controller510, an input/output (I/O) device520(e.g. a keypad, display), a memory530, a wireless interface540, and a static random access memory (SRAM)560and coupled to each other via a bus550. A battery580may supply power to the system500in one embodiment. It should be noted that the scope of the present invention is not limited to embodiments having any or all of these components.

Controller510may comprise, for example, one or more microprocessors, digital signal processors, micro-controllers, or the like. Memory530may be used to store messages transmitted to or by system500. Memory530may also optionally be used to store instructions that are executed by controller510during the operation of system500, and may be used to store user data. The instructions may be stored as digital information and the user data, as disclosed herein, may be stored in one section of the memory as digital data and in another section as analog memory. As another example, a given section at one time may be labeled as such and store digital information, and then later may be relabeled and reconfigured to store analog information. Memory530may be provided by one or more different types of memory. For example, memory530may comprise a volatile memory (any type of random access memory), a non-volatile memory such as a flash memory, and/or phase change memory10illustrated inFIG. 1.

The I/O device520may be used to generate a message. The system500may use the wireless interface540to transmit and receive messages to and from a wireless communication network with a radio frequency (RF) signal. Examples of the wireless interface540may include an antenna, or a wireless transceiver, such as a dipole antenna, although the scope of the present invention is not limited in this respect. Also, the I/O device520may deliver a voltage reflecting what is stored as either a digital output (if digital information was stored), or it may be analog information (if analog information was stored).

While an example in a wireless application is provided above, embodiments of the present invention may also be used in non-wireless applications as well.