Array substrate and its manufacturing method and display device

The present disclosure provides an array substrate, a manufacturing method thereof and a display. By forming a source pattern layer on the base substrate in the present disclosure, the source pattern layer crossing the gate pattern layer maybe mutually insulated from the gate pattern layer through the insulating buffer layer, thus eliminating the dielectric layer in the prior art which is formed to insulate the source pattern layer and the gate pattern layer, further simplifying the structure of the array substrate, and reducing the process steps and process costs.

TECHNICAL FIELD

The present disclosure relates to the field of display technologies, and in particular, to an array substrate, a manufacturing method thereof, and a display device.

BACKGROUND

A thin film transistor in an array substrate consists of a plurality of film layers combined with each other, which are provided with different functions and different materials, and a source electrode and a gate electrode of the thin film transistor are disposed at different layers and cross each other. Therefore, in order to insulate the position where the source electrode and the gate electrode cross each other, an insulating dielectric layer needs to be configured between the source electrode and the drain electrode. Therefore, when manufacturing the array substrate, it is needed to add the process of forming the dielectric layer.

SUMMARY

The present disclosure mainly provides an array substrate, a manufacturing method thereof and a display device, aiming at solving the problem of adding the process of forming a dielectric layer in order to insulate the source electrode and the gate electrode from each other.

In order to solve the above technical problem, one of the technical solutions in the present disclosure is to provide a display device, and the display device including an array substrate. The array substrate including: a base substrate, and a source pattern layer and a light shielding layer formed on the base substrate; a buffer layer covering the source pattern layer, the buffer layer defining a first via hole through which the source pattern layer is exposed; a semiconductor pattern layer formed on the buffer layer, the semiconductor pattern layer disposed corresponding to the light shielding layer, a gate insulating layer covering the semiconductor pattern layer, the gate insulating layer defining a second via hole and a third via hole, one end of the semiconductor pattern layer exposed through the second via hole, the third via hole connected to the first via hole, and the other end of the semiconductor pattern layer exposed through the third via hole; a gate pattern layer, a drain pattern layer, and a connection pattern layer formed on the gate insulating layer, the drain pattern layer connected to one end of the semiconductor pattern layer through the second via hole, the connection pattern layer filled in the first via hole and the third via hole to connect the source pattern layer with the other end of the semiconductor pattern layer; and a protective layer, a planar layer, and a pixel electrode layer, which are sequentially formed, the protective layer and the planar layer defining a fourth via hole through which the drain pattern layer is exposed, the fourth via hole connected with the second via hole, and the pixel electrode layer connected to the drain pattern layer through the fourth via hole.

In order to solve the above technical problem, another technical solution in the present disclosure is to provide an array substrate. The array substrate including: a base substrate, and a source pattern layer formed on the base substrate; a buffer layer covering the source pattern layer, the buffer layer defining a first via hole through which the source pattern layer is exposed; a semiconductor pattern layer formed on the buffer layer; a gate insulating layer covering the semiconductor pattern layer, the gate insulating layer defining a second via hole and a third via hole, one end of the semiconductor pattern layer exposed through the second via hole, the third via hole connected to the first via hole, and the other end of the semiconductor pattern layer exposed through the third via hole; and a gate pattern layer, a drain pattern layer, and a connection pattern layer formed on the gate insulating layer, the drain pattern layer connected to one end of the semiconductor pattern layer through the second via hole, the connection pattern layer filled in the first via hole and the third via hole to connect the source pattern layer with the other end of the semiconductor pattern layer.

In order to solve the above technical problem, another technical solution in the present disclosure is to provide a manufacturing method of an array substrate. The method including: providing a base substrate and forming a source pattern layer on the base substrate; forming a buffer layer covering the source pattern layer, the buffer layer defining a first via hole through which the source pattern layer is exposed; forming a semiconductor pattern layer on the buffer layer; forming a gate insulating layer covering the semiconductor pattern layer, the gate insulating layer defining a second via hole and a third via hole, one end of the semiconductor pattern layer exposed through the second via hole, the third via hole connected to the first via hole, and the other end of the semiconductor pattern layer exposed through the third via hole; and forming a gate pattern layer, a drain pattern layer and a connection pattern layer on the gate insulating layer, the drain pattern layer connected to one end of the semiconductor layer through the second via hole, the connection pattern layer filled into the first via hole and the third via hole to connect the source pattern layer with the other end of the semiconductor pattern layer.

The effects of the present disclosure lies in that, differing from the prior art, in the present disclosure, with a source pattern layer formed on a base substrate, and through the connection pattern layer filled in the first via hole of the buffer layer and the third via hole of the gate insulating layer, the source pattern layer may be connected with a semiconductor pattern layer disposed on the buffer layer, such that the source pattern layer crossing the gate pattern layer may be insulated from the gate pattern layer through the insulating buffer layer, in which case, the dielectric layer in the prior art which is formed to insulate the source pattern layer and the gate pattern layer, may be eliminated, thus simplifying the structure of the array substrate, and reducing the process steps and process costs.

DETAILED DESCRIPTION

The technical solution in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are merely a part of the embodiments of the present disclosure, not all of the embodiments. All other embodiments obtained by one with ordinary skills in the art based on the embodiments of the present disclosure without any creative efforts shall fall into the protection scope of the present disclosure.

Referring toFIG. 1,FIG. 1is a schematic structural view of an embodiment of an array substrate provided by the present disclosure. The array substrate of the present embodiment may include a base substrate101, a source pattern layer102, a buffer layer103, a semiconductor pattern layer104, a gate insulating layer105, a gate pattern layer106, a drain pattern layer107, and a connection pattern layer108.

Referring toFIG. 1andFIG. 2, the base substrate101may be, but not limited to, a glass substrate, a ceramic substrate, and a silicon wafer substrate.

The source pattern layer102may be formed on the base substrate101.

The buffer layer103may be formed on the base substrate101and may cover the source pattern layer102, wherein the buffer layer103may be an insulating layer made of silicon nitride and/or silicon oxide.

The buffer layer103may define a first via hole1031through which the source pattern layer102is exposed.

Referring toFIG. 2andFIG. 3, the semiconductor pattern layer104may be formed on the buffer layer103.

Alternatively, the semiconductor pattern layer104may be a doped polysilicon layer.

The gate insulating layer105may be formed on the buffer layer103and may cover the semiconductor pattern layer104.

The gate insulating layer105may define a second via hole105aand a third via hole105b. One end of the semiconductor pattern layer104may be exposed through the second via hole105a, the third via hole105bmay be connected to the first via hole1031and the other end of the semiconductor pattern layer104may be exposed through the third via hole105b.

The third via hole105bmay be divided into a first hole segment1051and a second hole segment1052. The first hole segment1051may be disposed corresponding to the first via hole1031and may be connected to the first via hole1031, and the second hole segment1052may be disposed corresponding to the other end of the semiconductor pattern layer104and the other end of the semiconductor pattern layer104may be exposed through the second hole segment1052.

Referring toFIG. 3andFIG. 4, the gate pattern layer106, the drain pattern layer107, and the connection pattern layer108may be formed on the gate insulating layer105, and may be spaced apart from each other.

The drain pattern layer107may be connected to one end of the semiconductor pattern layer104through the second via hole105a, and the connection pattern layer108may be filled in the first via hole1031and the third via hole105bto connect the source pattern layer102and the other end of the semiconductor pattern layer104.

Further referring toFIG. 1, the array substrate of the present embodiment may also include a light shielding layer109formed on the base substrate101and disposed corresponding to the semiconductor pattern layer104.

The light shielding layer109may be a metal light shielding layer, and the metal light shielding layer may be spaced apart from the source pattern layer102.

Furthermore, the array substrate of the embodiment may also include a protective layer110, a planar layer111, and a pixel electrode layer112, which may be sequentially formed.

Referring toFIG. 1andFIG. 5, the protective layer110may be formed on the gate insulating layer105and may cover the gate pattern layer106, the drain pattern layer107, and the connection pattern layer108.

A common electrode layer113may be formed on the protective layer110, and the planar layer111may be formed on the protective layer110and may cover the common electrode layer113.

The protective layer110and the planar layer111may define a fourth via hole1101through which the drain pattern layer107is exposed, and the fourth via hole1101may be connected to the second via hole105a.

The pixel electrode layer112may be formed on the planar layer111, and may be connected to the drain pattern layer107through the fourth via hole1101.

Referring toFIG. 6,FIG. 6is a schematic flowchart of an embodiment of a manufacturing method of the array substrate provided by the present disclosure. The method of this embodiment may specifically include following blocks.

In S11, the method may include providing a base substrate and forming a source pattern layer on the substrate.

Referring toFIG. 1andFIG. 2, a substrate101may be, but not limited to, a glass substrate, a ceramic substrate, and a silicon wafer substrate, may be provided. After the substrate101is cleaned, metal may be deposited on the substrate101to form a metal layer, and then the metal layer may be patterned by a photolithography process of photoresist coating, exposure, development, etching, and lift-off, and the patterned metal layer may be regarded as the source pattern layer102in this embodiment.

Alternatively, the metal includes, but not limited to, molybdenum, aluminum or copper.

In S12, the method may include forming a light shielding layer on the base substrate.

The light shielding layer109may be a metal light shielding layer. Specifically, a metal layer may be formed through depositing metal on the base substrate101, then the metal layer may be patterned by a photolithography process of photoresist coating, exposure, development, etching, and lift-off, the patterned metal layer may be spaced apart from the source pattern layer102, and the patterned metal layer may be the light shielding layer109in the present embodiment.

It can be understood that the metal used to form the light shielding layer109in the block S12may be different from the metal used to form the source pattern layer102in the above block S11.

Alternatively, the block S12may be performed before the step S11, that is, the sequence between the step S11and the step S12is not limited.

In S13, the method may include forming a buffer layer covering the source pattern layer.

Specifically, an insulating material of silicon oxide and/or silicon nitride may be deposited on the base substrate101to cover the source pattern layer102and the light shielding layer109, through a physical vapor deposition method or a plasma vapor deposition method, so as to form an insulating layer to be the buffer layer103.

The buffer layer103may define a first via hole1031through which the source pattern layer102is exposed.

Specifically, after the insulating material is deposited to form the insulating layer, the first via hole1031., through which the source pattern layer102is exposed, may be formed on the insulating layer through a photolithography process of photoresist coating, exposure, development, etching, and lift-off.

In S14, the method may include forming a semiconductor pattern layer on the buffer layer.

Referring toFIG. 2andFIG. 3, amorphous silicon may be deposited on the buffer layer103, and amorphous silicon may be converted into polysilicon by a crystallization process to form a semiconductor layer, then through a photolithography process of photoresist coating, exposure, development, etching, and lift-off, the semiconductor layer may be patterned, and the patterned semiconductor layer may be ion doped, to form the semiconductor pattern layer104.

The semiconductor pattern layer104may be disposed corresponding to the light shielding layer109.

In S15, the method may include forming a gate insulating layer covering the semiconductor pattern layer.

Specifically, silicon nitride and/or silicon oxide may be deposited on the buffer layer103to form a gate insulating layer105through a physical vapor deposition method or a chemical vapor deposition method.

The gate insulating layer105may define a second via hole105aand a third via hole105b. One end of the semiconductor pattern layer104may be exposed through the second via hole105a, the third via hole105bmay connect to the first via hole1031, and the other end of the semiconductor pattern layer104may be exposed through the third via hole105b.

Specifically, after the gate insulating layer105is formed, through a photolithography process of photoresist coating, exposure, development, etching, and lift-off, the second via hole105athrough which one end of the semiconductor pattern layer104is exposed, may be formed on the gate insulating layer105, and a third via hole1031connecting to the first via hole1031and through which the other end of the semiconductor pattern layer104is exposed, may be formed on the gate insulating layer105.

The third via hole105bmay include a first hole segment1051and a second hole segment1052. The first hole segment1051may be disposed corresponding to the first via hole1031and may be connected to the first via hole1031, and the second hole segment1052may be disposed corresponding to the other end of the semiconductor pattern layer104and the other end of the semiconductor pattern layer104may be exposed through the second hole segment1052.

In S16, the method may include forming a gate pattern layer, a drain pattern layer, and a connection pattern layer on the gate insulating layer.

Referring toFIG. 3andFIG. 4, a metal may be deposited on the gate insulating layer105and in the first via hole1031, the second via hole105a, and the third via hole105b, to form a metal layer, and then the metal layer may be processed through a photolithography process of photoresist coating, exposure, development, etching, and lift-off to form the gate pattern layer106, the drain pattern layer107, and the connection pattern layer108. The drain pattern layer107may be connected to one end of the semiconductor pattern layer104through the second via hole105a, and the connection pattern layer108may be filled in the first via hole1031and the third via hole105bto connect the source pattern layer102and the other end of the semiconductor pattern layer104.

Further referring toFIG. 6, the manufacturing method of this embodiment may further include following blocks.

In S17, the method may include sequentially forming a protective layer, a planar layer, and a pixel electrode layer.

Referring toFIG. 1andFIG. 5, the protective layer110may be formed on the gate insulating layer105by a physical vapor deposition method or a plasma vapor deposition method, and the protective layer110may cover the gate pattern layer106, the drain pattern layer107and the connecting the pattern layer108, and a planar layer111may be formed on the protective layer110by a physical vapor deposition method or a plasma vapor deposition method.

The protective layer110and the planar layer111may define a fourth via hole1101through which the drain pattern layer107is exposed, the fourth via hole1101may be connected to the second via hole105a, and the pixel electrode layer112may be connected to the drain pattern layer107through the fourth via hole1101.

Specifically, after the planar layer111is formed, the fourth via hole1101through which the drain pattern layer107is exposed, may be formed by a photolithography process of photoresist coating, exposure, development, etching, and lift-off, and then the pixel electrode layer112may be formed on the planar layer111and in the fourth via hole1101such that the pixel electrode layer112may be connected to the drain pattern layer107through the fourth via hole1101.

The present disclosure also provides a display including the array substrate in the above embodiment.

Differing from the prior art, in the present disclosure, with a source pattern layer formed on a base substrate, and through the connection pattern layer filled in the first via hole of the buffer layer and the third via hole of the gate insulating layer, the source pattern layer may be connected with a semiconductor pattern layer disposed on the buffer layer, such that the source pattern layer crossing the gate pattern layer may be insulated from the gate pattern layer through the insulating buffer layer, in which case, the dielectric layer in the prior art which is formed to insulate the source pattern layer and the gate pattern layer, may be eliminated, thus simplifying the structure of the array substrate, and reducing the process steps and process costs.

The above description depicts merely some exemplary embodiments of the disclosure, but is not meant to limit the scope of the disclosure. Any equivalent structure or flow transformations made according to the disclosure, or any direct or indirect applications of the disclosure on other related fields, shall all fall into the protection scope of the disclosure.