Semiconductor memory device having reverse base current bipolar transistor-field effect transistor memory cell

A semiconductor memory device, which has a memory cell comprising the following transistors: a transistor for selecting; and a bipolar transistor for memorizing, which has a base region whose base concentration as either lower than an ordinary base concentration or higher than an ordinary base concentration and which is constructed so as to generate a reverse base current.

BACKGROUND OF THE INVENTION 
1. Field of the Invention 
This invention relates to a semiconductor memory device, for example, a 
semiconductor memory device which is suited for static RAM (random access 
memory). 
2. Description of the Prior Art 
Recently, a new memory cell for static RAM comprising one bipolar 
transistor and one MOS transistor has been announced by Toshiba 
Corporation at 1988 IEDM (International Electrical Devices Meeting) (for 
further details, refer to Sakui, K., Hasegawa, T., Fuse, T., Watanabe, S., 
Ohuchi, K. and Masuoka, F.: "A new static memory cell based on reverse 
base current (RBC) effect of bipolar transistor", 1988 International 
Electrical Devices Meeting, Technical Digest, thesis No. 3.2, pp. 44-47, 
December 1988, or pp. 283-285 of the Nikkei Electronics, 1989. 2. 20 (No. 
467)). Aiming at large capacity memory with over 16M bit, this memory cell 
has a memory principle which is entirely different from that of the 
conventional static RAM or dynamic RAM in that the two transistors 
constituting the memory cell, a P-channel MIOS transistor and an NPN 
transistor, respectively, are used as a transistor for selecting and a 
transistor for memorizing. And the output of said memory cell shows a high 
level when the base-emitter voltage of said NPN transistor is about 0.9 V, 
and a low level when said voltage is 0 V (that is, the NPN transistor 
takes bistable states), and these two states, respectively, are equivalent 
to "1" or "0". 
The operating principle of said memory cell and its problems will be 
described hereunder with reference to FIGS. 12 and 13. 
The operating principle of this memory cell is to utilize a physical 
phenomenon, called impact ionization, of the NPN transistor: as shown in 
FIG. 12, when a collector-emitter voltage V.sub.CE of about 6 V is applied 
to the NPN transistor which has an emitter-collector dielectric breakdown 
voltage of about 13 V, electron-hole pairs by impact ionization are 
generated at a base-collector PN junction region by electrons injected 
from the emitter at this time. Out of the electron-hole pairs, the 
electrons move to the collector, and the holes to the base, and an 
ordinary forward hole current I.sub.BF, which flows from a base to the 
emitter, is restricted by a base-emitter voltage V.sub.BE, so that the 
holes generated by impact ionization flow as a reverse hole current 
(hereinafter may be called simply reverse base current) I.sub.BR in a 
direction reverse to the ordinary hole current I.sub.BF. 
Furthermore, the base current I.sub.B when impact ionization is going on 
may be expressed as follows: 
##EQU1## 
wherein I.sub.C is a collector current, and M is an impact ionization 
coefficient. M is expressed by the following formula: 
EQU M=1/[1-(V.sub.BC /BV.sub.CBO).sup.n ] 
wherein V.sub.BC is a voltage applied between the base, and the collector, 
and BV.sub.CBO is an insulation breakdown voltage of the base-collector PN 
junction. In this case the test results and the actual calculations are 
considered to agree when n is assumed as 4.6. 
In a cell actually produced for trial, as shown in FIG. 13, when 0.57 
V&lt;V.sub.BE &lt;0.90 V, the reverse hole current I.sub.BR becomes greater than 
the forward hole current I.sub.BR, and when the base-emitter voltage 
V.sub.BE is set at around 0.9 V, both the reverse and forward currents 
become equal, leading the base current I.sub.B to stop apparently. Even 
though the P-channel MOS transistor for selecting is closed in such a 
state, V.sub.BE remains at about 0.9 V, and this state is "1". In 
addition, when V.sub.BE is set at 0 V, the base current I.sub.B does not 
flow, presenting a state of "0". 
In practice, when the P-channel MOS transistor is closed with V.sub.BE set 
at 0.5 V or higher, the hole current stops, leading to V.sub.BE of about 
0.9 V, so that it is not necessary to set it at 0.9 V from the outset. 
Furthermore, when V.sub.BE is smaller than 0.5 V, it likewise becomes 0 V. 
As described above, the operating principle of the foregoing memory cell 
lies in impact ionization in the NPN transistor, wherein a memory 
operation is performed by finding a logical state of memory in the 
base-emitter voltage V.sub.BE when the base current I.sub.B becomes 0 
through utilization of the positive-negative inversion of said base 
current I.sub.B caused by the outflow of holes (the reverse hole current 
I.sub.BR) from a base electrode, said holes being those of the 
electron-hole pairs generated by impact ionization at the collector-base 
PN-junction region. 
Said base current I.sub.B, as shown in FIG. 13, changes in the order of 
"+", "-" and "+" accompanied by the change of the base-emitter voltage 
V.sub.BE, and the range of the base-emitter voltage during the flow of 
negative current is 0.57 V&lt;V.sub.BE &lt;0.90 V. However, when the device is 
used within the above-mentioned voltage range in an ordinary bipolar 
transistor, though depending upon the shape of transistor, a relatively 
large collector current I.sub.C inevitably flows. This causes a very big 
problem in producing a large capacity static RAM as described above. 
Actually in the memory cell announced by Toshiba Corp. it has been 
confirmed that said memory cell induces the flow of a collector current 
such as 500 uA per bipolar transistor for memorizing. Hence this leads to 
a very high consumption of power in consideration of a large capacity 
static RAM in practice. 
Incidentally, FIG. 14 shows the V.sub.BE -I.sub.B and I.sub.C 
characteristic of said NPN transistor based on the so-called Gummel plot 
when the collector-emitter voltage V.sub.CE is set at 6.25 V. 
OBJECT AND SUMMARY OF THE INVENTION 
The object of this invention is to provide a semiconductor memory device 
which may reduce the consumption of electric current for a bipolar 
transistor for memorizing, and thus produce a low power dissipation and 
large capacity static RAM or the like. 
In other words, this invention provides a semiconductor memory device 
having a memory cell which includes the following transistors: a 
transistor for selecting; and a bipolar transistor for memorizing, which 
has a base region whose base concentration is either lower than an 
ordinary base concentration or higher than an ordinary base concentration, 
and which is constructed so as to generate a reverse base current.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
The embodiments of this invention will be described hereunder. 
First, the structure of a device in accordance with an embodiment in which 
this invention is applied to a static RAM will be described with reference 
to FIGS. 1 and 2. 
With a P-type epitaxial layer 2 provided on one main surface of a P.sup.- 
-type silicon substrate 1 via an N.sup.+ -type buried layer 3, as shown in 
FIG. 1, a P-type base region 8 and an N.sup.+ -type diffusion region 6, 
respectively, are formed by a diffusion technique in an N-type diffusion 
region (N-well) formed on the N.sup.+ -type buried region 3. And in the 
P.sup.+ -type base region 8 an N.sup.+ -type collector region 9 and a 
P.sup.- -type base electrode take-out region 10, respectively, are formed 
by the diffusion technique, and in the N.sup.+ -type diffusion region 6 an 
N.sup.+ -type emitter electrode take-out region 7 is formed by the 
diffusion technique. Hence in this NPN-type vertical bipolar transistor 
(transistor for memorizing) BN the emitter electrode take-out region 7 and 
a base region 8 are connected via the N-type diffusion region 4, the 
N.sup.+ -type burled layer 3 and the N.sup.+ -type diffusion region 6. 
On the other hand a P.sup.+ -type drain region 11 and a P.sup.+ -type 
source region 12 are formed in a predetermined pattern in the N-type 
diffusion region 4 provided on the N.sup.+ -type buried layer 3, and a 
P-channel MOS transistor (transistor for selecting) PM is constructed with 
a gate electrode 21 provided between said regions via a gate oxide film 
13. 
As shown in FIG. 1, the base contact region 10 of the NPN transistor BN and 
the drain region 11 of the P-channel MOS transistor PM are connected by a 
distribution layer 18 formed via contact holes 15, leading to the 
construction of a memory cell as shown in the equivalent circuitry diagram 
in FIG. 3. In the diagram, in addition, the numeral 5 is field oxide film, 
14 is an insulating layer, 16 is an emitter electrode, 17 is a collector 
electrode, 19 is a word line, 20 is a bit line, and FIG. 2 is a plane view 
of FIG. 1 (FIG. 1 is a cross-sectional view taken along the line I--I in 
FIG. 2). 
Here, what is important in this embodiment is that a base-emitter voltage 
V.sub.BE causing impact ionization by optimizing the impurity 
concentration profile of each region in the NPN transistor BN is set at 
lower than a PN-junction built-in potential (charged voltage) of 0.6 V, 
thus enabling the "+" and "-" inversion of the above described base 
current I.sub.B. That is, in this example, as described above, the 
construction is made so that the range of the base-emitter voltage 
V.sub.BE allowing the flow of the reverse base current I.sub.BR is set not 
at 0.57 to 0.9 V, but at an extremely low voltage range of 0.3 to 0.48 V 
to generate the reverse base current I.sub.BR and thereby reduce the 
consumption of current (collector current I.sub.C ) for the NPN transistor 
BN as shown in FIG. 4 and that the above-mentioned memory operation is 
performed under the condition that the base-emitter voltage V.sub.BE is 
set at a voltage range of 0.2 to 0.5 V. 
With regard to the impurity concentration of each region of an ordinary NPN 
transistor, the emitter (an arsenic or phosphorus concentration, for 
example) has a high concentration of 10.sup.20 cm.sup.-3, the collector (a 
phosphorus concentration, for example) has 10.sup.15 cm.sup.-3, and the 
base (a boron concentration, for example) has 10.sup.18 cm.sup.-3, so that 
unless a high collector-emitter voltage V.sub.CE of 6 V is used, as 
described above, there is no reverse base current I.sub.BR generated by 
impact ionization. In addition, to generate a reverse base current 
I.sub.BR within the range of a low base-emitter voltage V.sub.BE as in 
this example, it is thought that a relatively high collector-emitter 
voltage V.sub.CE must be given in the NPN transistor in the 
above-mentioned concentration relationship. 
Thus, in this example the relationship of impurity concentration in each 
region is set in the NPN transistor BN with the above-mentioned structure, 
as follows: the base region concentration (boron concentration, for 
example) is preferably 10.sup.17 cm.sup.-3 order or less as its upper 
limit and preferably 10.sup.14 cm.sup.-3 order or more as its lower limit, 
and more preferably 2.times.10.sup.16 cm.sup.-3 order or less as the upper 
limit and more preferably 10.sup.15 cm.sup.-3 order or more as the lower 
limit; the collector region concentration (arsenic concentration, for 
example) is preferably 10.sup.18 cm.sup.-3 or more and 10.sup.22 cm.sup.-3 
or less, more preferably 10.sup.19 cm.sup.-3 or more and 5.times.10.sup.21 
cm.sup.-3 or less, and the emitter region concentration (phosphorus 
concentration, for example) is preferably 2.times.10.sup.13 cm.sup.-3 or 
more and 10.sup.17 cm.sup.-3 or less, more preferably 10.sup.14 cm.sup.-3 
or more and 10.sup.16 cm.sup.-3 or less. 
The above-mentioned device may be readily produced by, for example, an 
ordinary bi-MOS technique (a combination of bipolar technique and MOS 
technique), and an impurity to concentration in each region may also be 
readily set by controlling ion implantation or other conditions at the 
time of manufacture. 
The V.sub.BE -I.sub.B characteristic in the NPN transistor BN in the 
above-mentioned impurity concentration relationship is, as shown in FIG. 
4, that as the base-emitter voltage V.sub.BE is raised from 0 V, the base 
current I.sub.B changes in the order of "+" (region I in the diagram), "-" 
(region II in the diagram), "+" (region III in the diagram), "-" (region 
IV in the diagram), and "+" (region V in the diagram), thus resulting in 
two-time inversion to a "-" base current I.sub.B (in this example, 
however, the collector region concentration is set at 1.23.times.10.sup.20 
cm.sup.-3, the base region concentration at 3.0 .times.10.sup.15 cm.sup.-3 
and the emitter region concentration at 1.3.times.10.sup.. cm.sup.-1). In 
addition, the V.sub.BE -I.sub.B and I.sub.C characteristic as shown in 
FIG. 4 is illustrated by the so-called Gummel plot and both the base 
current ("+" base current) flowing into the base and the base current ("-" 
base current) flowing out of the base are shown on the same graph. 
Next, the V.sub.BE -I.sub.B and I.sub.C characteristic as shown in FIG. 4 
will be described hereunder together with the energy band diagram in FIG. 
5 and the h.sub.FE characteristic in FIG. 6. 
However, FIG. 6 shows a current amplification factor h.sub.FE when the 
collector-emitter voltage V.sub.CE is varied to be 1 V, 3 V or 3.9 V, 
indicating the point immediately before impact ionization becomes marked 
(that is, when almost no reverse base current I.sub.BR flows as yet). 
Here, an important point in FIG. 6 is described. That is, what is 
important in FIG. 6 is that the base-emitter voltage V.sub.BE when the 
current amplification factor h.sub.FE rises up is found to be about 0.2 V 
as shown in the diagram. Moreover, when V.sub.BE becomes 0.3 V, especially 
when a high collector-emitter voltage V.sub.CE is applied, there is a 
rapid increase in the current amplification factor h.sub.FE, and when said 
V.sub.BE is 0.3 V, the inversion of the base current I.sub.B has started 
as shown in FIG. 4. In other words, the cause of the initial base current 
conversion, which constitutes the most important characteristic of this 
invention in a low current region, is found in the rapid rise of the 
current amplification h.sub.FE in the neighborhood of 0.3 V. 
Hereunder is a description of the mechanism for the inversion of the base 
current I.sub.B in each of the regions I to V in FIG. 4. 
[Region I: V.sub.BE =0 to 0.3 (V)] 
A region in which a micro base current I.sub.B in the "+" direction flows 
in the same manner as in an ordinary bipolar transistor. Many of the 
components of the base current I.sub.B are those obtained by 
recombination. 
[Region II: V.sub.BE =0.3 to 0.48 (V)] 
Within this voltage range the collector current I.sub.C is small as shown 
in the diagram, and as shown in FIG. 6, the current amplification factor 
##EQU2## 
rises up from the level where V.sub.BE is about 0.2 V. In other words, the 
collector current I.sub.C starts to increase in line with the elevation of 
V.sub.BE, thus allowing electrons to be injected from the emitter region 
as a ground (earth) potential into the base region and then diffused in 
the base region. In addition, in the boundary region of the base and 
collector regions, the collector region, as described above, has a 
concentration of 1.23.times.10.sup.20 cm.sup.-3, higher than that of the 
base region, and also has a steep junction, thus reducing the extension of 
a depletion layer, so that the electric field in said boundary region 
becomes higher. Hence among the above-mentioned electrons diffused in the 
base region, those accelerated by the electric field in said boundary 
region collide against a crystal lattice in the collector region and then 
beat out the electron-hole pairs. At this time, those electrons of the 
electron-hole pairs beaten out are absorbed by the collector region, 
whereas holes are diffused from the base region and observed (see FIG. 5) 
as a "-" base current I.sub.B (that is, a reverse base current I.sub.BR). 
In this example, furthermore, the respective impurity concentrations in 
the emitter and collector regions of the NPN transistor BN for memorizing 
are set at a high level of 1.28.times.10.sup.20 cm.sup.-3 in the collector 
region and at a low level of 1.3.times.10.sup.15 cm.sup.-3 in the emitter 
region (that is to say, the NPN transistor BN is used by reversing the 
relationship between the collector and emitter impurity concentrations in 
an ordinary NPN transistor). Hence this leads to a low efficiency of 
carrier injection from the emitter and a marked increase in hole injection 
from the base region (that is, the forward base current I.sub.BF becomes 
larger), leading to an increase in the base current I.sub.B to that 
extent. However, this increase in the base current I.sub.B results in no 
increase in the collector current to reduce h.sub.FE (see FIG. 6), so that 
the base current I.sub.B stops its increase in the "-" direction when 
V.sub.BE reaches about 0.48 V, and thus exhibits the peak of the base 
current I.sub.B in the "-" direction, then rapidly increasing in the "+" 
direction. 
[Region III: V.sub.BE =0.48 to 0.625 (V)] 
As shown in FIG. 6, while h.sub.FE decreases, a great volume of carriers is 
injected into the base region, in which the base current I.sub.B increases 
in the "+" direction with the elevation of the base-emitter voltage 
V.sub.BE in the same manner as in an ordinary bipolar transistor. And the 
base current I.sub.B peaks at a certain point and then again decreases, 
thus growing substantially in the "-" direction. This is because electrons 
accelerated in the depletion layer between the base and the emitter 
further increase and collide against the crystal lattice in the emitter 
region due to the great volume of carriers injected from the base region, 
thus causing holes to suppress the holes injected from the base region and 
again flow out. 
[Region IV: V.sub.BE =0.625 to 0.8 (V)] 
In this region, since the base-emitter voltage V.sub.BE exceeds a built-in 
voltage, the collector current I.sub.C is extremely large as shown in FIG. 
4, resulting in the highest impact ionization, so that a large reverse 
base current I.sub.BR is generated. It is this region that is used in the 
example shown in FIGS. 12 and 13 and it is very difficult, as described 
above, to put it into practical use as a memory cell because the collector 
current I.sub.C as great as about 500 .mu.A flows. 
[Region V: V.sub.BE =0.8 (V) or more] 
In this region the carriers (electrons) flowing into the base region due to 
a high base-emitter voltage V.sub.BE finally suppresses and erases the 
holes produced by impact ionization, thus making the collector current 
I.sub.C extremely large. 
In addition, FIGS. 7A and 7B show one example of impurity concentration 
profile in each region in accordance with this embodiment, and FIG. 7B is 
an enlarged illustration of the collector, base and emitter boundary 
region shown within a circle in FIG. 7A. 
The operation of a memory cell in accordance with this embodiment will be 
described in the following paragraph. Used as memory in the operation of 
said memory cell is the base-emitter voltage region V.sub.BE =0.8 to 0.48 
(V) (region II in FIG. 4) up until the base current I.sub.B first 
appearing in the above-mentioned FIG. 4 changes to the "-" direction and 
further reaches a peak in the "-" direction to be again I.sub.B =0. 
In other words, when a voltage (V.sub.BE) of about 0.3 V is as shown in 
FIG. 3, applied to the base electrode of the NPN transistor BN for 
memorizing through the bit line by turning on the P-channel MOS transistor 
PM for selecting, the base current I.sub.B becomes zero as described 
above, which represents "0" in a logical state. Even when the P-channel 
MOS transistor PM for selecting is turned off in such a state, said 
logical state is maintained (that is, the base-emitter voltage V.sub.BE 
=0.3 (V) is maintained: writing of data "0"). Furthermore, when a voltage 
(V.sub.BE) of about 0.48 V is applied to the base electrode of the NPN 
transistor BN for memorizing through the bit line in the same manner as 
described above, the base current I.sub.B likewise becomes 0, and the 
base-emitter voltage V.sub.BE at this time becomes "1" in the logical 
state. In this case this logical state is maintained in the same manner as 
described above (that is, the base-emitter voltage V.sub.BE =0.48 (V) is 
maintained: writing of data "1"). Hence the reading of memory is performed 
by reading out the above-mentioned two respective V.sub.BE data through 
the bit line with the P-channel MOS transistor PM for selecting. 
In accordance with this embodiment, as described above, the bipolar 
transistor BN for memorizing has a base region whose base concentration is 
lower than the ordinary base concentration and is constructed so as to 
generate a reverse base current I.sub.BR, thus enabling the inversion of 
the base current I.sub.B within a low voltage range of the base-emitter 
voltage V.sub.BE from 0.3 to 0.48 V (that is, facilitating the occurrence 
of impact ionization in a region at a low level of said V.sub.BE by using 
a low base concentration as well as by means of the collector region 
having a steep junction and thus allowing the inversion of the initial 
base current I.sub.B to be readily generated) and arrival at a bistable 
state. Therefore, this enables the substantial reduction of the collector 
current I.sub.C as well as the construction of a low power consumption 
memory cell. In this embodiment, furthermore, the impurity concentration 
for the collector region is increased as compared with that for the 
emitter region and the first decline of h.sub.FE was brought by lowering 
the efficiency of carrier injection from the emitter region, thus enabling 
the inversion of the above-mentioned base current I.sub.B more 
effectively. As described above, moreover, by increasing the impurity 
concentration for the collector region and producing a steep junction, the 
extension of the depletion layer between the base and the collector is 
controlled to be small to have a large electric field in this region, 
facilitating the acceleration of carriers. That is to say, the reduction 
of the base-collector breakdown voltage to some extent facilitates impact 
ionization and enables the memory operation at a lower voltage (that is, 
the collector-emitter voltage V.sub.CE : 4.9 (V) in this example). This is 
very favorable in view of matching with the 5 V power source that has been 
conventionally used. 
In addition, the semiconductor memory device in accordance with this 
embodiment may readily provide a large capacity static RAM or the like, 
because it has a memory cell including a P-channel MOS transistor PM for 
selecting and a bipolar transistor BN for memorizing as described above. 
FIGS. 8 and 9 show an example when an N-channel MOS transistor is used as a 
transistor for selecting for the memory cell in place of the P-channel MOS 
transistor PM in the above described example. However, for the parts 
similar to those of the above described example, their explanations may be 
omitted by putting the same numerals for the sake of convenience in 
description. 
Referring mainly to the different points from the above described example, 
as shown in FIG. 8, a polysilicon layer 44 is formed on an N.sup.+ -type 
collector region 9 in the NPN transistor BN for memorizing and, moreover, 
an aluminum distribution layer 17 is formed as a collector electrode via a 
TiSi.sub.2 layer 43 which is provided on said polysilicon layer 44. In 
addition, a titanium silicide layer 48 is, as shown in the drawing, formed 
on the diffusion region each of the numerals 10, 31, 32 and 41. With an 
N.sup.+ -type diffusion region 6, formed in an N-well 4, as an emitter 
electrode take-out region, a titanium silicide layer 43 is formed on said 
N.sup.+ -type diffusion region 6 and, moreover, an aluminum distribution 
layer 16 provided via a contact hole 15 is formed as an emitter electrode. 
On the other hand, an N.sup.+ -type drain region 31 and an N.sup.+ -type 
source region 32 are formed in a predetermined pattern in a P-type 
diffusion region (P-type well) 40 provided in a P-type epitaxial layer 2, 
and a rate electrode 35 is provided between these regions via a rate oxide 
film 33, thus leading to the construction of an N-channel MOS transistor 
(transistor for selecting) NM1. 
Then, a base electrode take-out region 10 of the NPN transistor BN and a 
drain region 31 of the N-channel transistor NM1 are, as shown in FIG. 8, 
connected by a titanium nitride layer 28 formed on the N.sup.+ -type drain 
region 31 and the P.sup.+ -type base electrode take-out region 10 and 
further on a field oxide film 5 located between the above two regions, 
thus leading to the construction of a memory cell as shown by an 
equivalent circuitry diagram in FIG. 10. In the drawing, the numerals 24 
and 34 are insulating layers, 41 is a P.sup.+ -type diffusion region for 
prevention of latch-up, 42 is a side wall silicon oxide film, and FIG. 9 
is a plane view of FIG. 8 (FIG. 8 is a cross-sectional view taken along 
the line VIII--VIII in FIG. 9). 
As described above, the construction of a memory cell with use of the 
N-channel MOS transistor NM1 as a transistor for selecting makes it 
unnecessary, as shown in FIG. 9, to provide an isolation region between a 
region in which the NPN-transistor BN for memorizing is formed and a 
region in which the N-channel MOS transistor NM1 for selecting is formed 
(that is, using the P-type well 40 formed in the P-type epitaxial layer 2, 
the N-channel MOS transistor NM1 for selecting may be formed in a region 
adjacent to the NPN transistor BN by providing the N.sup.+ -type source 32 
and the drain 31 inside said P-type well), thus resulting in a great 
convenience in terms of layout. 
FIGS. 10 and 11, respectively, are an equivalent circuitry diagram and a 
timing chart to confirm the data writing and reading operation in the 
memory cell in accordance with the above-mentioned example. However, since 
using any of a P-channel MOS transistor and an N-channel MOS transistor as 
a transistor for selecting results in the same memory operation in the 
memory cell, a description here is made about an example using an 
N-channel MOS transistor as the transistor for selecting. 
An N-channel MOS transistor NM2 in FIG. 10 is to control the writing 
operation, and the memory operation as shown below is determined by a 
combination of the N-channel MOB transistors NM2 and NM1. Furthermore, the 
point "A" turns into a floating state when both the N-channel MOS 
transistors NM1 and NM2 are turned off. 
______________________________________ 
NM1 ON ON 
NM2 ON OFF 
Operation Writing Reading 
______________________________________ 
In addition, the region each for writing and reading of 
In addition, the region each for writing and reading of the data "1" and 
writing and reading of the data "0" in the timing chart shown in FIG. 11 
will be described below. 
[Region for Writing of "1"] 
Both the N-channel MOS transistors NM1 and NM2 are in the state of ON, with 
entry of "1" made as data. At this time the base of the NPN transistor BN 
is forward-biased to induce impact ionization and then turns into a memory 
state. 
[Region for Reading of "1"] 
This is in the state that the N-channel MOS transistor NM1 is ON and the 
N-channel MOS transistor NM2 is OFF. Since at this time the point "A" (bit 
line) is cut off from the signal of data and connected with the base of 
the NPN transistor BN, it follows that the base potential appears directly 
at the point "A". That is, here appears "1" which has been memorized in 
advance. 
[Region for Writing of "0"] 
After the data input is set at "0" in advance, the N-channel MOS 
transistors NM1 and NM2 are turned on. When the bit line is observed at 
this time, "1" has been maintained all the time at the point "A", which 
has been a floating node, but the potential rapidly declines to a level of 
"0". At this time the data is written in the NPN transistor BN. 
[Region for Reading of "0"] 
This region is in the state that the N-channel MOS transistor NM1 is ON and 
the N-channel MOS transistor NM2 is OFF, and the data input is again cut 
off from the point "A". At this time the timing of data input is 
determined in advance at the point "A" in consideration of the foregoing 
thing. In the operation at the time of reading out the point "A" is a 
floating node immediately before reading, and a floating capacity 
parasitic to each electrode is charged at "1". The NPN transistor BN then 
comes to pull out this stored charge when "0" level is read from the base. 
It will be evident that various modifications may be made to the above 
described embodiments without departing from the scope of this invention. 
In the above described embodiment, for example, an NPN-type transistor has 
been used as a bipolar transistor for memorizing, but a PNP-type 
transistor may be used instead. In this case as well it is preferable to 
have a base region whose base concentration is lower than the ordinary 
base concentration, but this invention is also applicable to a device 
which has a base region whose base concentration is, on the contrary, 
higher than the ordinary base concentration. The expression "the base 
concentration is higher than the ordinary base concentration" as referred 
to above means that the base concentration in this case is, for example, 
preferably 10.sup.18 cm.sup.-3 or more and 10.sup.23 cm.sup.-3 or less, 
more preferably 10.sup.19 cm.sup.-3 or more and 10.sup.22 cm.sup.-3 or 
less. 
In the above described embodiment, in addition, a vertical bipolar 
transistor has been used, but a lateral bipolar transistor may be use and 
the device structure may be modified in various ways. 
Furthermore, as the transistor for selecting a bipolar transistor or other 
appropriate ones may be adopted not limiting to a P-channel MOS transistor 
or an N-channel MOS transistor. 
Since the device in accordance with this invention, as described above, has 
a memory cell using a bipolar transistor for memorizing, the base 
concentration of which is either lower or higher than an ordinary base 
concentration and which is constructed so as to generate a reverse base 
current, it may perform the memory operation at a low base-emitter voltage 
V.sub.BE ranging, for example, from 0.3 to 0.48 V and thus substantially 
reduce the consumption of current at the memory cell. In addition, since 
the above-mentioned memory cell comprises a transistor for selecting and 
said bipolar transistor for memorizing, this invention may provide a low 
power consumption yet large capacity semi-conductor memory device.