Semiconductor apparatus and method of manufacturing same, and method of detecting defects in semiconductor apparatus

A semiconductor apparatus includes a semiconductor substrate having a device region and a periphery region surrounding the device region; a semiconductor device provided in the device region of the semiconductor substrate; a first electrode pad provided on the semiconductor substrate; a second electrode pad provided on the semiconductor substrate; a strip-like, first conductivity type semiconductor pattern; and a strip-like, second conductivity type semiconductor pattern. The strip-like, first conductivity type semiconductor pattern extends in the periphery region of the semiconductor substrate, and the first electrode pad is electrically connected to one end of the first conductivity type semiconductor pattern. The strip-like, second conductivity type semiconductor pattern constitutes a p-n junction in conjunction with the first conductivity type semiconductor pattern. The first and second electrode pads are electrically connected to both ends of the second conductivity type semiconductor pattern.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2004-172452, filed on Jun. 10, 2004; the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to a semiconductor apparatus, and more particularly is used for detecting defects such as cracks and breaks in a semiconductor chip at the time of packaging.

2. Background Art

In recent years, portable devices as typified by mobile phones have been enhanced with various capabilities such as addition of a camera, and the number of components used therefor tends to increase. However, portable devices still continue to be downsized, which increases the demand for using smaller and slimmer components. For this reason, the chip size of semiconductor apparatuses such as power amplifier modules has been reduced, and mount module boards and packages have been made smaller and slimmer. Moreover, the field of packaging techniques has seen an introduction of flip chip bump packaging, which involves smaller packaging area than in using wire bonding.

On the other hand, the above-described power amplifier generates a large amount of heat because of its operation at an extremely high power density, and thus requires close attention to its thermal stability. One of the measures to address this is to improve heat dissipation. One of the technical trends therefor is to reduce the thickness of the chip.

This involves a problem of causing cracks and breaks in a semiconductor chip due to mechanical and thermal stress at the time of packaging such as the mounting and bonding of the semiconductor chip.

Methods of detecting cracks and breaks in a semiconductor chip are disclosed in Japanese Laid-Open Patent Applications 6-244254 (1994) and 6-347509 (1994). In these known arts, as shown inFIG. 10, a conductive pattern is arranged in the chip periphery region. A chip crack will disconnect the conductive pattern. The presence of chip crack is detected by sensing the change of electric characteristics of the pattern. InFIG. 10, a strip-like conductive pattern102made of aluminum or silver paste is formed in the periphery region of a semiconductor chip101made of compound semiconductor such as a gallium arsenide (GaAs) substrate. The conductive pattern102generally circumscribes the semiconductor chip101. Detecting pads103adjacent to each other are connected to both ends of the conductive pattern102, and configured to detect cracks and breaks in the semiconductor chip101by measuring the value of current between the pads.

However, fine cracks (microcracks) may cause only a slight change of electric characteristics because the conductive pattern does not lead to disconnection or the damage to the conductive pattern is not significant. Therefore this method still has a problem that chip cracks cannot be detected reliably.

To solve this problem, a method of using p-n junction is proposed in Japanese Laid-Open Patent Application 6-77300 (1994). This method takes advantage of the fact that a microcrack crossing a p-n junction produces a path of surface current, which changes the electric characteristics of the junction. More specifically, it is suggested that chip cracks, and also microcracks, can be detected by examining leak current under a reverse bias to the p-n junction.

However, the inventor's investigation has revealed a problem that chip cracks cannot be always detected reliably by application of the above approach to a chip of compound semiconductor such as GaAs. More specifically, compound semiconductor as typified by GaAs often incurs a smooth cleavage surface by nature. For this reason, application of the above approach to a chip of compound semiconductor such as GaAs does not always lead to a large leak current. A problem is thus found that chip cracks cannot be detected reliably by examining the electric characteristics of p-n junction.

SUMMARY OF THE INVENTION

According to an aspect of the invention, there is provided a semiconductor apparatus comprising:

a semiconductor substrate having a device region and a periphery region surrounding the device region;

a semiconductor device provided in the device region of the semiconductor substrate;

a first electrode pad provided on the semiconductor substrate;

a second electrode pad provided on the semiconductor substrate;

a strip-like, first conductivity type semiconductor pattern extending in the periphery region of the semiconductor substrate, the first electrode pad being electrically connected to one end of the first conductivity type semiconductor pattern; and

a strip-like, second conductivity type semiconductor pattern provided on the first conductivity type semiconductor pattern and constituting a p-n junction in conjunction with the first conductivity type semiconductor pattern, the first and second electrode pads being electrically connected to both ends of the second conductivity type semiconductor pattern.

According to other aspect of the invention, there is provided a semiconductor apparatus comprising:

a semiconductor substrate having a device region and a periphery region surrounding the device region;

a semiconductor device provided in the device region of the semiconductor substrate;

a first electrode pad provided on the semiconductor substrate;

a second electrode pad provided on the semiconductor substrate;

a third electrode pad provided on the semiconductor substrate;

a strip-like, first conductivity type semiconductor pattern extending in the periphery region of the semiconductor substrate and electrically connected to the first electrode pad;

a strip-like, second conductivity type semiconductor pattern provided on the first conductivity type semiconductor pattern and constituting a p-n junction in conjunction with the first conductivity type semiconductor pattern, the second electrode pad being electrically connected to one end of the second conductivity type semiconductor pattern; and

a first conductivity type semiconductor layer electrically connected to the third electrode pad and provided on the other end of the second conductivity type semiconductor pattern to constitute at least in part a p-n junction, thereby constituting a transistor in conjunction with the first and second conductivity type semiconductor patterns.

According to other aspect of the invention, there is provided a method of detecting defects in a semiconductor apparatus including:a semiconductor substrate having a device region and a periphery region surrounding the device region;a semiconductor device provided in the device region of the semiconductor substrate;a first electrode pad provided on the semiconductor substrate;a second electrode pad provided on the semiconductor substrate;a strip-like, first conductivity type semiconductor pattern extending in the periphery region of the semiconductor substrate, the first electrode pad being electrically connected to one end of the first conductivity type semiconductor pattern; anda strip-like, second conductivity type semiconductor pattern provided on the first conductivity type semiconductor pattern and constituting a p-n junction in conjunction with the first conductivity type semiconductor pattern, the first and second electrode pads being electrically connected to both ends of the second conductivity type semiconductor pattern,

the method comprising:

detecting cracks or breaks in the semiconductor apparatus by applying voltage between the first and second electrode pads to sense current flowing between the first and second electrode pads.

According to other aspect of the invention, there is provided a method of detecting defects in a semiconductor apparatus including:a semiconductor substrate having a device region and a periphery region surrounding the device region;a semiconductor device provided in the device region of the semiconductor substrate;a first electrode pad provided on the semiconductor substrate;a second electrode pad provided on the semiconductor substrate;a third electrode pad provided on the semiconductor substrate;a strip-like, first conductivity type semiconductor pattern extending in the periphery region of the semiconductor substrate and electrically connected to the first electrode pad;a strip-like, second conductivity type semiconductor pattern provided on the first conductivity type semiconductor pattern and constituting a p-n junction in conjunction with the first conductivity type semiconductor pattern, the second electrode pad being electrically connected to one end of the second conductivity type semiconductor pattern; anda first conductivity type semiconductor layer electrically connected to the third electrode pad and provided on the other end of the second conductivity type semiconductor pattern to constitute at least in part a p-n junction, thereby constituting a transistor in conjunction with the first and second conductivity type semiconductor patterns,

the method comprising:

detecting cracks or breaks in the semiconductor apparatus by applying voltage between the second and third electrode pads while applying voltage between the first and third electrode pads to sense current flowing between the first and third electrode pads.

DETAILED DESCRIPTION OF THE INVENTION

In an embodiment of the invention, a strip-like pattern of p-n junction is formed in the periphery region of a semiconductor chip to surround the device region at the center of the chip. A pattern of one conductivity type is formed in a circular configuration and has two pads electrically connected to both ends of the pattern of the one conductivity type. A pattern of the other conductivity type is configured to have one end electrically connected to one of the two pads. Cracks and breaks in the semiconductor chip can be detected with excellent sensitivity by measuring the electric characteristics between the two pads.

In the following, the embodiment for carrying out the invention will be described with reference to examples.

EXAMPLES

First Example

FIG. 1is a plan view of a semiconductor chip according to the first example of the invention.FIG. 2is a graph showing current-voltage characteristics of a semiconductor chip according to the first example of the invention.FIGS. 3A to 3Dare equivalent circuit diagrams of a detection circuit according to the first example of the invention.FIG. 4is a cross-sectional view of the part along line A-A′ inFIG. 1.

The semiconductor chip1is made of compound semiconductor such as a semi-insulating gallium arsenide (GaAs) substrate. The semiconductor chip1has, for example, a power amplifier or other device (not shown) formed on a device region1B except a periphery region1A. This figure shows the chip in which device formation and formation of internal interconnect (not shown) are completed. Detecting pads3(3a,3b) are arranged on the semiconductor chip1. The detecting pads3are connection electrodes that are made of aluminum, gold, platinum, or titanium, or laminated film thereof, and that are electrically connected to the device or internal interconnect. Strip-like semiconductor patterns5,6are formed from conductive semiconductor layers in the periphery region1A of the semiconductor chip1to surround the device region of the semiconductor chip1. Semiconductor patterns5,6have a two-layer structure. The lower layer is an n-type semiconductor layer (n-type semiconductor pattern)5, on which a p-type semiconductor layer (p-type semiconductor pattern)6is formed, and the two layers constitute a p-n junction2. The n-type semiconductor pattern5is formed in the periphery region of the semiconductor chip1to surround the device region, and is ohmically connected to the pad3bat one end. The p-type semiconductor pattern6is ohmically connected to the pads3aand3bat both ends. The wiring layer11is appropriately provided between the semiconductor layer and the pads.

More specifically, an n+-type semiconductor layer9is formed on the semi-insulating GaAs substrate. On the n+-type semiconductor layer9, a conductive layer having an impurity concentration of 5×1018/cm3and a thickness of 500 nm, for example, is formed as the n-type semiconductor layer5, on which a conductive layer having an impurity concentration of 4×1019/cm3and a thickness of 60 nm, for example, is formed as the p-type semiconductor layer6. The n+-type semiconductor layer9and n-type semiconductor layer5are patterned by increasing resistance around them using boron (B+) ion implantation, and processed into a circular pattern having a width of 50 μm. The p-type semiconductor layer6is patterned by etching and processed into a strip-like pattern having a width of 40 μm on the n-type semiconductor layer5.

FIG. 2shows the electric characteristics between the two pads3aand3bin this situation.FIGS. 3A to 3Dare the associated equivalent circuit diagrams.

Without chip cracks, the two pads3aand3bare interconnected via the p-type semiconductor pattern6. Therefore, current flows through a path P1shown inFIG. 3B. When the voltage between the pads is increased to a value (VF) at which the p-n junction2is turned on, current flows also in the n-type semiconductor pattern5through a path P2. Therefore, in normal condition, the current-voltage characteristics (I-V characteristics)200as shown inFIG. 2is observed. The discontinuity200A in the I-V characteristics is a point at which the p-n junction is turned on and current begins to flow through the path P2.

In order to make the discontinuity200A more distinct, the sheet resistance of the n-type semiconductor pattern5is preferably selected to have a smaller value than that of the p-type semiconductor pattern6. To this end, as shown inFIG. 4, for example, the n-type semiconductor pattern5may have a larger width and/or thickness than that of the p-type semiconductor pattern6.

Next, the case where a chip crack occurs is described.

As shown inFIG. 3C, when a chip crack18destroys a p-n junction2to allow leak current P3to flow across the p-n junction, increase of current value under a voltage below the turn-on voltage is observed in the I-V characteristics using an ammeter4as shown by current-voltage characteristics210inFIG. 2(abnormal1). The chip crack can thus be detected by observing the increase of current.

However, a GaAs substrate is typically easy to incur a smooth cleavage. For this reason, in the case of a chip crack involving a cleavage surface, leak current at the p-n junction can be scarcely detected. Therefore this method may fail to detect the chip crack because the current-voltage characteristics210shown inFIG. 2are not observed.

However, in this case, the chip crack damages the n-type semiconductor pattern5and p-type semiconductor pattern6per se. Therefore decrease of current value is observed as shown by current-voltage characteristics220inFIG. 2(abnormal2), which allows the chip crack to be detected.

FIG. 4is a cross-sectional view showing the internal structure of the semiconductor chip. The n-type semiconductor layer5and p-type semiconductor layer6are formed on the n+-type semiconductor layer9to form a p-n junction in the periphery region of the semiconductor chip1made of a GaAs substrate in which a device separation region8is formed. The process of forming this p-n junction is also used for simultaneously forming a p-n junction constituting the circuit in the device region. Another n-type semiconductor layer is stacked thereon to form an npn transistor10. The transistor10is provided with an interconnect layer, and a protection insulating film7made of polyimide and the like.

As described above, the structure of this example can be used to detect chip cracks with high sensitivity by sensing leak current at a p-n junction for a fine chip crack and by sensing the variation of resistor value for a large and clean chip crack that shows a cleavage surface.

In addition, the p-n junction formed in this example is formed in conjunction with the p-n junction in the device region. Therefore there is no increase of manufacturing steps.

FIGS. 5A to 5Dare process cross-sectional views showing part of a process of manufacturing a semiconductor apparatus of this example.

More specifically, as shown inFIG. 5A, an n+-type semiconductor layer9, n-type semiconductor layer5, and p-type semiconductor layer6are stacked in this order on a semi-insulating GaAs substrate1.

Next, as shown inFIG. 5B, a device separation region8having high resistance is formed using boron (B+) ion implantation to pattern the semiconductor layers9,5, and6in the periphery region1A and device region1B, respectively.

Next, as shown inFIG. 5D, part of the p-type semiconductor layer6and n-type semiconductor layer5, respectively, are etched to carry out the patterning of the p-type semiconductor layer6.

Subsequently, the etching mask17is removed, and insulating film and interconnect structure are formed thereon to complete a semiconductor apparatus as shown inFIG. 4.

As described above, according to this example, the p-n junctions in the periphery region1A and in the device region1B can be formed simultaneously. Therefore there is no increase of manufacturing steps for forming the structure in the periphery region1A.

Second Example

Next, the second example will be described with reference toFIGS. 6 to 9.

FIG. 6is a plan view of a semiconductor chip according to the second example of the invention.FIG. 7is a graph showing current-voltage characteristics of a semiconductor chip according to the second example of the invention.FIGS. 8A and 8Bare equivalent circuit diagrams of a detection circuit according to the second example of the invention.FIG. 9is a circuit diagram illustrating a surge protection circuit function of the second example.

As with the first example, the semiconductor chip21made of compound semiconductor such as a semi-insulating gallium arsenide (GaAs) substrate is shown in which formation of, for example, a power amplifier or other device and of internal interconnect (not shown) are completed.

Detecting pads23(23a,23b,23c) are arranged on the semiconductor chip21. The detecting pads23are connection electrodes that are made of aluminum, gold, platinum, or titanium, or laminated film thereof, and that are electrically connected to the device or internal interconnect. Strip-like semiconductor patterns25,26are formed from conductive semiconductor layers in the periphery region of the semiconductor chip21to surround the device region of the semiconductor chip21. The semiconductor patterns25,26have a two-layer structure. As with that described above with reference toFIG. 4, the lower layer is an n-type semiconductor layer (n-type semiconductor pattern)25, on which a p-type semiconductor layer (p-type semiconductor pattern)26is formed, and the two layers constitute a p-n junction22. The n-type semiconductor pattern25is formed in the periphery region of the semiconductor chip21as a loop surrounding the device region, and is ohmically connected to the pad23aat one end. The p-type semiconductor pattern26is ohmically connected to the pad23bat one end.

In this example, a third pad23cis further provided. Part of an n-type semiconductor layer (n-type semiconductor pattern)27is stacked on the p-type semiconductor pattern26, and the contacting portion between them constitutes a p-n junction29. The pad23cis ohmically connected to the n-type semiconductor pattern27. The n-type semiconductor pattern25, p-type semiconductor pattern26, and n-type semiconductor layer (n-type semiconductor pattern)27constitute an npn transistor30in their stacked portion.

It is understood that the stacking order of the n-type semiconductor pattern25, p-type semiconductor pattern26, and n-type semiconductor pattern27may be reversed. That is, the p-type semiconductor pattern26may be stacked on the n-type semiconductor pattern27, and the n-type semiconductor pattern25may be further stacked on the p-type semiconductor pattern26.

More specifically, on the semi-insulating GaAs substrate, a conductive layer having an impurity concentration of 5×1018/cm3and a thickness of 500 nm, for example, is formed as the n-type semiconductor pattern25, on which a conductive layer having an impurity concentration of 4×1019/cm3and a thickness of 60 nm, for example, is formed as the p-type semiconductor pattern26. The n-type semiconductor layer27stacked on the p-type semiconductor pattern26is formed in the condition of an impurity concentration of 5×1017/cm3and a thickness of 300 nm, for example. The n-type semiconductor layer25is patterned by eliminating its conductivity using boron (B+) ion implantation, and processed into a circular pattern having a width of 50 μm. The p-type semiconductor pattern26is patterned by etching and processed into a strip-like pattern having a width of 40 μm on the n-type semiconductor pattern25. The n-type semiconductor layer27on the p-type semiconductor pattern26is patterned by etching and the portion connected to the n-type semiconductor pattern is processed into an island shape having a width and length of 30 μm. The n-type semiconductor pattern27is electrically connected to the third pad23cby internal connect11.

FIG. 7is a graph illustrating the current flowing between the pads23aand23cversus the voltage applied to the pad23b. That is, the horizontal axis of this figure indicates the voltage applied to the pad23b, and the vertical axis indicates the current flowing between the pads23aand23c.

A voltage of 3 V, for example, is applied to the pad23aconnected to the underlying n-type semiconductor pattern25, and the pad23cconnected to the overlying n-type semiconductor layer27is set to ground (0 V). In this condition, the voltage applied to the pad23bconnected to the p-type semiconductor pattern26is gradually increased. In normal condition, that is, when there is no chip crack, base current of the npn transistor begins to flow at a voltage near the turn-on voltage230A of the p-n junction. This causes current to flow between the pads23aand23c, which is sensed by an ammeter28to obtain current-voltage characteristics230shown inFIG. 7(normal).

In this case again, in order to make the turn-on voltage230A more distinct, the sheet resistance of the n-type semiconductor pattern25is preferably selected to have a smaller value than the that of the p-type semiconductor pattern26. To this end, as described above with reference toFIG. 4, for example, the n-type semiconductor pattern25may have a larger width and/or thickness than that of the p-type semiconductor pattern26.

On the other hand, when a chip crack destroys a p-n junction to result in a situation where leak current flows across the pn junction (see the equivalent circuit diagram inFIG. 8A), leak current P4occurs between the pads23aand23b. As a result, base current P4flows through the npn transistor without application of voltage to the pad23b. Therefore, increase of current value under a voltage below the turn-on voltage is observed in the I-V characteristics as shown by current-voltage characteristics240inFIG. 7(abnormal1), which allows the chip crack to be detected. However, in the case of a clean chip crack showing a cleavage surface, leak current can be scarcely detected. Therefore the current-voltage characteristics240is not observed.

However, the chip crack damages the p-type semiconductor pattern26per se. Therefore the current path is blocked as shown inFIG. 8B. As a result, base current does not flow even in the voltage region above the turn-on voltage as shown by characteristics250inFIG. 7(not detected by the ammeter24(abnormal2)), which allows the chip crack to be detected.

As described above, according to the method of this example, distinction in the I-V characteristics between normal and abnormal conditions is clearer than in the first example, which allows detection of chip cracks with higher sensitivity.

In addition, since the pads are interconnected through p-n junctions, they are in an open circuit condition in terms of direct current when the applied voltage is below the turn-on voltage of p-n junction. For example, the operation of the circuit is not affected if the pad23bis connected to the ground terminal in an actual circuit rather than to the p-type semiconductor pattern26and the other pads23aand23care connected to terminals subjected to voltages above 0 V, for example, to a control terminal or RF terminal. Therefore no additional pad is needed for a detection circuit as in the first example, and thereby the chip can be downsized. Moreover, chip cracks can be detected by using the terminals of a packaged circuit, which serves to downsize the package.

Furthermore, since a large p-n junction22is formed between the pads23aand23b, it can also serve as a surge protection circuit. That is, advantageously, this example has another function in addition to merely serving as a chip crack detection circuit.

FIG. 9is a circuit diagram illustrating the surge protection circuit function of this example. Current P5does not flow into the protected circuit38formed in the device region even when ESD of negative voltage is applied to the pads23a,23b, and23d. Therefore the protected circuit38is not destroyed.

As described above, according to the invention, a strip-like pattern of p-n junction is formed in the periphery region of a semiconductor chip to surround the device region. A pattern of one conductivity type is formed in a circular configuration and has pads electrically connected to the pattern. A pattern of the other conductivity type is configured to have one end electrically connected to one of the pads, and the other end electrically connected to another pad. As a result, the invention can provide a semiconductor apparatus characterized in that cracks and breaks in the semiconductor chip can be detected with excellent sensitivity.

It is understood that the conductive semiconductor layer in the above examples may be a conductive semiconductor layer of a semiconductor substrate formed for use in HBT (Heterojunction Bipolar Transistor) or HEMT (High Electron Mobility Transistor), or may be a conductive semiconductor layer formed by ion implantation or annealing.

While boron ion implantation is used for patterning n-type semiconductor, device separation by mesa etching may also be used. In addition, while GaAs is used for the semiconductor substrate, any substrate of compound semiconductor made of group III and group V elements in the periodic table such as InP can also be used in the invention because such a substrate has the same cleavage property and achieves similar effects.