CCD comb filters

Comb filter which includes a first CCD delay line for imparting a delay equal to one horizontal line time plus the delay inserted by N additional stages and second and third CCD delay lines, each having N stages. Video signal is applied to the first and second delay lines and its complement to the third delay line. The gains of the second and third CCD delay lines are controlled to make them equal to that of the first CCD delay line to control the depth of the rejection notches of the filter to desired levels. In one embodiment, feedback from the output of the first and second lines is employed to control the gain of the second line and feedback from the output of the first and third lines is employed to control the gain of the third line. In another embodiment, the respective gains are controlled in open loop fashion by controlling the residual charge in the input storage well of CCD's operated in the skimming mode.

The present invention relates to gain control circuits for charge coupled 
devices (CCD's) and particularly to comb filters including such circuits.

Copending U.S application Ser. No. 758,184 for "Linear CCD Input Circuit," 
filed Jan. 10, 1977 by J. E. Carnes, P. A. Levine (the present inventor), 
and D. J. Sauer and assigned to the same assignee as the present 
application, discusses a particular kind of input circuit for a buried 
channel CCD. This circuit colloquially is now referred to as a "fan and 
skim" input circuit. It is especially useful in CCD delay lines employed 
to delay analog signals such as the video signals of television as it 
permits linear signal translation. 
The CCD signal register shown in section in FIG. 1 and in plan view in FIG. 
2, except for the gain control circuit, is similar to the CCD register 
described in the above-identified application. However, the present 
system, by way of example, utilizes self-aligned barrier implants such as 
85 and 87 under the second layer of gate electrodes (rather than DC 
offsets between electrode pairs) to obtain asymmetrical potential wells in 
the substrate for permitting unidirectional charge propagation with two 
phase clocking. Typical processing parameters for a buried N-channel CCD 
with with the structure are: (1) Substrate: P-type 30-50 .OMEGA.-cm 
resistivity; (2) N-type buried layers implant: Phosphorous, 
Dose=1.3.times.10.sup.12 /cm.sup.2, Energy=150 keV, junction depth X.sub.j 
=0.75 micron; (3) P-type barrier implant: Boron, Dose=4.times.10.sup.11 
/cm.sup.2, Energy=100 keV. 
As in the register of the copending application, the present CCD includes 
electrodes G.sub.1, G.sub.2 and G.sub.3 and these are followed by multiple 
phase electrodes. The electrodes G.sub.1, G.sub.2 and G.sub.3 are operated 
in such a way that a residual charge level Q.sub.F (FIG. 4) always remains 
stored in the potential well beneath electrode G.sub.2. This residual 
charge level places the operating point of the circuit at a desired point 
in the linear region of the input transfer characteristic of the CCD. 
Superimposed over this residual charge level Q.sub.F is an additional 
charge which may comprise a bias plus signal charge Q.sub.(B+S). This 
additional charge subsequently is "skimmed" from the potential well 
beneath electrode G.sub.2 and transmitted down the CCD register. The CCD 
channel is relatively wide in the region of electrodes G.sub.1, G.sub.2 
and G.sub.3 and tapers down in width by an amount such that the maximum 
bias plus signal charge Q.sub.(B+S) will fill the first potential well in 
the narrowest channel region. In the example illustrated, the channel 
tapers from width 2 W to width W. 
The operation above is depicted in the substrate potential profiles of FIG. 
4 when considered in connection with the operating waveforms of FIG. 3. At 
time t.sub.2, the voltage V.sub.S applied to diffusion S causes this 
diffusion to operate as a source of charge carriers (electrons) and these 
flow into the potential well 90 beneath electrode G.sub.2. At time 
t.sub.3, the voltage V.sub.S is at a more positive level sufficiently so 
to cause the diffusion S to operate as a drain, and excess charge spills 
from the potential well 90 back into the diffusion S. There remains in 
potential well 90 a residual charge level Q.sub.F and a bias plus signal 
charge Q.sub.(B+S). This bias plus signal charge includes a direct voltage 
component whose value is dependent on the voltage V.sub.1 applied to gate 
electrode G.sub.1. That is, this bias component is dependent on the level 
of potential barrier 92 in the absence of input signal. In the case of a 
symmetrical input signal V.sub.IN, the voltage V.sub.1 will establish a 
potential barrier 92 such that the bias component of the charge 
Q.sub.(B+S) will be at the center of the linear region of the input 
characteristic. This may correspond, for example, to 1/2 the capacity of 
the potential well beneath electrode 94 in the main portion of the CCD 
channel, that is, the narrowed down portion of the CCD channel as shown in 
FIG. 2. For an asymmetrical input signal, the voltage V.sub.1 can be made 
to cause an operating point close to either end of the linear region of 
the input characteristic of the CCD, depending upon the direction of 
asymmetry of the input signal. In one limiting case, V.sub.1 may be at a 
level such that Q.sub.B is zero. In another it may be at a level such that 
the input potential well is full in the absence of a signal V.sub.IN. 
At time t.sub.4, when the voltage V.sub.3 applied to the gate electrode 
G.sub.3 is at its most positive value and when .phi..sub.1 is also at its 
most positive value, the charge Q.sub.(B+S) has transferred from well 90 
to the potential well 96 now present beneath the first phase 1 
(.phi..sub.1) electrode 98. In other words, this charge Q.sub.(B+S) has 
been skimmed from the potential well 90, leaving behind the residual 
charge level Q.sub.F. The charge Q.sub.(B+S) subsequently is propagated 
down the CCD in conventional fashion. 
In the operation of the system of the copending application identified 
above, the voltage V.sub.2 applied to gate electrode G.sub.2 is held at a 
fixed level so that the residual charge Q.sub.F also remains at a fixed 
level. The amount of charge propagated from potential well 90 (FIG. 4) to 
potential well 96, is a function of the difference in substrate potentials 
.DELTA.V.sub.X between substrate potentials at 92 and 99. These, in turn, 
are a function of the difference in potential V.sub.G1 -V.sub.3 applied to 
gate electrodes G.sub.1 and G.sub.3, respectively, where V.sub.G1 includes 
both the DC and AC components applied to gate electrode G.sub.1 . 
The present invention resides, in part, in the discovery that the gain of 
the input circuit to the CCD is a function of the voltage V.sub.2 applied 
to gate electrode G.sub.2, that is, it is a function of the residual 
charge level Q.sub.F. The present inventor has found that for a given 
.DELTA.V.sub.X, if V.sub.2 is made more positive, that is, if the size of 
the residual charge packet Q.sub.F is increased, the gain of the input 
circuit is increased and vice-versa. This is illustrated in FIG. 4 by the 
last three substrate potential profiles. At time t.sub.4, the voltage 
V.sub.2 is at a level such that a residual charge level Q.sub.F remains in 
potential well 90 for a given difference in potential .DELTA.V.sub.X 
between surface potentials 92 and 99. The transferred charge is 
Q.sub.(B+S) which subsequently is propagated down the CCD. If V.sub.2 is 
increased while the difference between surface potentials 92 and 99 
remains the same, the amount of transferred charge Q.sub.(B+S) ' 
increases. This is illustrated by the potential profiles at time t.sub.3 ' 
and t.sub.4 '. In the former, which illustrates the spill portion of the 
cycle corresponding to t.sub.3, V.sub.2 has been made more positive so 
that the residual charge component Q.sub.F ' has been increased, that is, 
Q.sub.F '&gt;Q.sub.F. At time t.sub.4 ' corresponding to time t.sub.4, the 
difference .DELTA.V.sub.X between substrate potentials 92 and 99 is equal 
to V.sub.Y ; however, the amount of charge transferred Q.sub.(B+S) ' is 
greater than Q.sub.(B+S). 
The reason for the above is not completely understood. However, the 
following model may provide a basis for an explanation. It is believed 
that as the voltage V.sub.2 applied to the gate electrode G.sub.2 is 
increased, the depth of the potential minimum of the conduction band 
increases and the potential valley in the conduction band moves toward the 
surface 17 of the N-type silicon layer as illustrated in the energy band 
diagram of FIG. 5. The solid line illustrates the substrate potentials for 
a lower value of V.sub.2 and the dashed line the shift which occurs when 
the voltage V.sub.2 is increased in a sense to increase the residual 
charge level Q.sub.F. Note the shift in the potential minimum from 37 to 
37a, 37a being closer to surface 17. This change in the position of the 
potential minimum is believed to be manifested as an effective increase in 
the capacitance C of the CCD channel, and as the charge signal amplitude 
Q.sub.SIG is a function of this capacitance C, this increases Q.sub.SIG. 
The expression these quantities is: 
EQU Q.sub.SIG .alpha..DELTA.(V.sub.3 -V.sub.G1)C 
the family of curves of FIG. 6 illustrates the operation of the present 
gain control circuit. Each curve was obtained by applying a linear ramp 
V.sub.G1 to a gate electrode corresponding to G.sub.1 while maintaining 
fixed the voltage V.sub.3 applied to a gate electrode corresponding to 
G.sub.3. Each curve is for a different voltage level V.sub.2 applied to an 
electrode corresponding to G.sub.2. The ordinate of the curves is output 
current. It was measured by sensing the current produced in the output 
circuit (a drain diffusion, not shown) of the CCD in response to the 
applied voltages. Note that at any particular value of voltage V.sub.G1, 
such as V.sub.Z, the input gain (slope) obtained is higher at higher 
values of V.sub.2 than at lower values of V.sub.2 (except, of course, 
where the curves converge at the zero output current crossing of the 
V.sub.G1 axis). 
FIG. 7 illustrates an important use of the gain control circuit of the 
present application. This figure shows schematically, a comb filter which 
may be employed for commercial television. Details of this filter are 
given in copending application Ser. No. 781,303 for "Electronic Signal 
Processing Apparatus" filed Mar. 25, 1977 by Dalton H. Pritchard issued 
June 20, 1978, as U.S. Pat. No. 4,096,516 and assigned to the same 
assignee as the present application. In brief, it includes a 1H (1 
horizontal line period) plug N CCD stage delay line 20 in one branch, an 
inverter 22 and a N-stage CCD delay line 24 in a second branch and a 
N-stage CCD delay line 26 in a third branch. For a clock frequency of 
approximately 10.7 megahertz (MHz) (which is equal to three times the 
color sub-carrier frequency of 3.58 MHz) applied to the three lines 20, 24 
and 26, a 1H delay is obtained with 6821/2 stages, as indicated in the 
above-identified patent. In this particular example, N is assumed to be 2. 
Each 2 -stage delay line has an input circuit such as shown in FIG. 1. The 
video signal is capacitively coupled to gate electrode G.sub.1 of lines 20 
and 26 and the inverted video signal is capacitively coupled to gate 
electrode G.sub.1 of line 24. One gain control voltage (V.sub.2) is 
applied to gate G.sub.2 of line 24 and another gain control voltage (call 
it V.sub.2 ') is applied to gate G.sub.2 of line 26. The long delay line 
20 also has an input circuit such as shown in FIG. 1; however, the voltage 
V.sub.2 supplied to its gate electrode need not be made controllable but 
can be left at a fixed level. The output signal of the long delay line 20 
is combined with that of the short (two-stage) delay line 26 to produce 
the luminance signal, and the output signal of the long delay line 20 is 
combined with the output signal of the short (two-stage) delay line 24 to 
produce the chrominance signal. It is necessary to adjust the relative 
gains of the short delay lines 24 and 26 to obtain rejection notches of 
sufficient depth at the color subcarrier frequency, 3.58 MHz (megahertz). 
The gain control circuit of the present application employed in each short 
delay line 24 and 26 provides sufficient range to make this adjustment. 
The present gain control is a significant improvement over a previous 
approach known to the present inventor for controlling the respective 
gains of the chrominance and luminance channels which required 
considerable on-chip transistor circuitry to balance the signals in these 
channels. With the present circuit it has been found possible to achieve 
gain variation of about .+-.20%, for a voltage range of 6-14 volts applied 
to electrode G.sub.2. The means for producing a voltage in this range may 
simply be a potentiometer such as illustrated at 30 in FIG. 1 or may be a 
feedback circuit for automatically controlling the gain of electrode 
G.sub.2. This gain variation is more than adequate for the balance control 
just described for the comb filter of FIG. 7. 
FIG. 8 illustrates a comb filter such as shown in FIG. 7 but with automatic 
control of the gains of the short delay lines 24 and 26 by negative 
feedback circuits. The long and short delay lines have the same structure 
as described in connection with FIG. 7. The circuit includes, in addition, 
four band pass filters 30, 32, 34 and 36 and two differential amplifiers 
38 and 40. The band pass filters are all tuned to the same particular 
frequency at or close to the center frequency 3.58 MHz of the color 
subcarrier components of the signals being passes through these lines. 
In operation, the output signal of short delay line 24 is supplied through 
filter 32 to the inverting terminal of differential amplifier 38 and the 
output of the long delay line 20 is supplied through band pass filter 30 
to the non-inverting terminal of the differential amplifier 38. In 
complementary fashion, the output of short delay 38. In complementary 
fashion, the output of short delay line 26 is supplied through band pass 
filter 34 to the non-inverting terminal of differential amplifier 40 and 
the output of the long delay line 20 is applied through filter 36 to the 
inverting terminal of differential amplifier 40. The differential 
amplifiers compare the signals they receive and adjust the gain of the 
short delay lines to control the output signal amplitude of these delay 
lines at the particular frequency to which the band pass filters are tuned 
which as already mentioned, is at or close to the color subcarrier 
frequency of 3.58 MHz. The control is in a sense to make the gain of the 
short delay lines equal to that of the long delay lines at this frequency. 
The result of operating in this way is to automatically control the depth 
of the rejection notches produced by the comb filter to their minimum 
levels. 
While the present invention has been illustrated as embodied in a two-phase 
CCD, it is to be understood that it is equally applicable to CCD's 
operated by any practical number of phases. Further, while two layer 
electrodes are shown, the invention is applicable also to single layer, 
triple layer and other well-known CCD structures. With respect to 
two-phase structure, means other than the ion implants illustrated may be 
employed for providing asymmetrical potential wells. Further, while in the 
illustrated system the substrate is of P-type and the surface layer of 
N-type, the reverse may be the case with corresponding change in operating 
voltage polarity. Finally, it is to be understood that the present 
invention is also applicable to other (than "fill and spill") forms of 
buried channel CCD's which employ a residual charge which continually is 
present in an input potential well.