Driver circuit receiving input voltage and providing corresponding output voltage

A first comparator compares a voltage of a pair of primary terminals of a pulse transformer with a first reference voltage, to apply an output voltage corresponding to the voltage difference therebetween to a gate of an N channel MOSFET. The N channel MOSFET is responsive to the output voltage for controlling current flowing through a primary side of a pulse transformer. Consequently, even if the impedance of a load connector to a pair of secondary terminals of the pulse transformer is fluctuated, a voltage between the pair of secondary terminals is kept constant. A second comparator compares the output voltage of the first comparator with a second reference voltage, to apply an output voltage corresponding to the voltage difference therebetween to a gate of a P channel MOSFET. When the load impedance becomes low, the P channel MOSFET performs control such that the output voltage of the second comparator does not exceed a predetermined value. Consequently, current flowing through the primary side of the pulse transformer is limited not to exceed a constant value. Thus, a voltage between output terminals does not exceed a constant value.

BACKGROUND OF THE INVENTION 
1. Field of the Invention 
The present invention relates generally to driver circuits for providing 
predetermined output voltages corresponding to respective output load 
impedances depending on fluctuations in output load. 
2. Description of the Background Art 
FIG. 1 is a diagram showing a structure of a basic interface of an ISDN 
(Integrated Services Digital Network) described in Recommendation I. 430 
of the CCITT. This basic interface of the ISDN is employed for high-speed 
digital communication using the existing two-wire telephone line 
(subscriber's line) at a data rate of 192 Kbps. 
In FIG. 1, a station 300 and a network termination 200 are connected 
through a subscriber's line 500. A maximum of 8 terminal equipments 100 
are connected to the network termination 200 through a subscriber's bus 
400. The network termination 200 and each of the terminal equipments 100 
are respectively provided with driver circuits line drivers) 10 for 
respectively driving the subscriber's bus 400. Outputs of the driver 
circuits 10 in the eight terminal equipments 100 are connected in parallel 
to an input of the network termination 200. An output of the driver 
circuit 10 in the network termination 200 is connected to inputs of the 
eight terminal equipments 100. Thus, an output load impedance of each of 
the driver circuits 10 is changed depending on an operating state of 
another terminal equipment 100 or the network termination 200. 
According to the Recommendation I. 430 of the CCITT, a pulse mask showing 
an allowable value of an output pulse shape of a driver circuit is 
determined for cases where load impedances are respectively 5.6.OMEGA., 
50.OMEGA. and 400.OMEGA.. FIG. 2A shows the pulse mask at the time of the 
load of 50.OMEGA., and FIG. 2B shows the pulse mask at the time of the 
load of 400.OMEGA.. FIGS. 2A and 2B mean that the output pulse shape must 
be included in an allowable region encircled by hatching. In addition, it 
is determined that an amplitude value (peak value) of the output pulse at 
the time of the load of 5.6.OMEGA. must be 20% (150mV) or less of an 
amplitude value of a nominal pulse shown in FIG. 2A. As obvious from FIGS. 
2A and 2B, the amplitude value of the output pulse must be 150mV or less 
at the time of the load of 5.6.OMEGA., in the range of 675 to 825mV at the 
time of the load of 50.OMEGA., and in the range of 675 to 1200mV at the 
time of the load of 400.OMEGA.. Thus, an output voltage of the driver 
circuit 10 must be changed depending on the load impedance. 
FIG. 3 is a diagram showing one example of a driver circuit satisfying the 
above described determination, which is described in, for example, 
Proceedings of 1986 National Conference of Institute of Electronics and 
Communication Engineers of Japan (2013, pp. 9-42). 
In FIG. 3, when an input signal I.sub.+ attains an "H" level, a potential 
difference .DELTA.V occurs between a base of a bipolar transistor Q7 and a 
base of a bipolar transistor Q8. Since the bipolar transistor has the 
property that a voltage between base and emitter becomes constant, i.e., 
approximately 0.6V at the on-time, this potential difference .DELTA.V is 
applied between primary terminals of a pulse transformer PT1 without any 
fluctuations. Consequently, a voltage of a value obtained by dividing the 
potential difference .DELTA.V by the turns ratio appears between secondary 
output terminals O1 and O2. Therefore, if a load impedance of a load 
connected between the output terminals O1 and O2 varies, an equal voltage 
is outputted. Thus, if the circuit constant is set such that a voltage 
appearing between the output terminals O1 and O2 becomes 750mV, a pulse 
mask at the time of the loads of 50.OMEGA. and 400.OMEGA. can be 
satisfied. 
On the other hand, when the load impedance becomes small, current flowing 
through the pulse transformer PT1 attempts to increase to keep the voltage 
between the output terminals O1 and O2 at a constant voltage. However, 
base potentials are respectively applied to bipolar transistors Q9 and Q10 
by diodes D1 and D2. Therefore, current of a given value or more does not 
flow through the transistors Q9 and Q10. Thus, the current flowing through 
the transistors Q9 and Q10 is limited, so that a voltage of the output 
pulse at the time of the load of 5.6.OMEGA. is suppressed to 150mV or 
less. Meanwhile, at the time of the loads of 50.OMEGA. and 400.OMEGA., the 
current flowing through the transistors Q9 and Q10 is less, so that the 
above described current limiting mechanism does not work. 
Additionally, when an input signal I.sub.- is brought to the "H" level, 
pulses in the opposite directions are respectively outputted from the 
output terminals O1 and O2. Thus, in this driver circuit, a pulse of both 
positive and negative polarities can be outputted. 
However, the above described driver circuit is constituted by a bipolar 
transistor. Thus, in order to form this driver circuit, along with another 
digital circuit, as an LSI (Large-Scaled Integrated Circuit), the digital 
circuit must be constituted by a bipolar device, or a digital circuit 
comprising a MOS device and a driver circuit comprising a bipolar device 
must be incorporated with each other in hybrid configuration using a 
special process such as an expensive Bi-CMOS (Bipolar-Complementary Metal 
Oxide Semiconductor) process. With respect to a large-scaled digital 
circuit, it is desirable that the digital circuit is constituted by a CMOS 
device, in which case the cost is lowered, and high density and low power 
consumption can be achieved. Thus, in either one of the above described 
methods, the cost is raised in order to form a driver circuit, along with 
another digital circuit, as an LSI. 
Additionally, FIG. 4 is a diagram showing another example of the driver 
circuit satisfying the pulse mask in Recommendation I. 430 of the CCITT. 
This driver circuit is described in DIGEST OF TECHNICAL PAPERS OF 1988 
IEEE International Solid-State Circuits Conference, pp. 108-109, pp. 317. 
This driver circuit comprises two controllable current sources J1 and J2, 
MOS transistors Q11 and Q12 constituting a first current mirror circuit, 
and MOS transistors Q13 and Q14 constituting a second current mirror 
circuit. A pulse is outputted between output terminals O1 and O2 connected 
to a secondary side of a pulse transformer Tx in response to a control 
signal applied to the current source J1 or a control signal applied to the 
current source J2. 
In this driver circuit, a pulse voltage is adjusted by current control. 
Current flowing through the pulse transformer Tx is determined depending 
on resistance values of resisters R6 to R8 and the MOS transistors Q11 to 
Q14. However, it seems that it is difficult to precisely set the 
resistance values of the devices to predetermine values, respectively, in 
manufacturing processes. In addition, the resistance values of the devices 
are changed depending on the temperature. Thus, adjustment is required. In 
general, it is more difficult in circuit techniques to precisely keep 
constant current flowing through a circuit, as compared with to precisely 
keep constant a voltage. 
SUMMARY OF THE INVENTION 
An object of the present invention is to provide a driver circuit capable 
of accurately outputting predetermined output voltages corresponding to 
respective output load impedances depending on fluctuations in output load 
impedance. 
Another object of the present invention is to provide a driver circuit 
capable of accurately outputting predetermined output voltages 
corresponding to respective output load impedances depending on 
fluctuations in output load impedance which circuit is incorporated with a 
CMOS digital circuit in hybrid configuration at low cost. 
Still another object of the present invention is to provide a driver 
circuit capable of accurately outputting a predetermined output voltage 
which circuit is capable of simple manufacture. 
A further object of the present invention is to provide a driver circuit 
capable of obtaining an output pulse shape satisfying a pulse mask 
determined in Recommendation I. 430 of the CCITT. 
In order to attain the above described objects, the driver circuit 
according to the present invention comprises a pair of input terminals, a 
pair of output terminals, voltage transforming means, first comparing 
means, a first field effect device, second comparing means, and a second 
field effect device. The voltage transforming means has a pair of primary 
terminals connected to the pair of input terminals and a pair of secondary 
terminals connected to the pair of output terminals. The first comparing 
means compares a voltage between the pair of input terminals with a 
predetermined first reference voltage, to provide an output voltage 
corresponding to the difference therebetween. The first field effect 
device has a control terminal receiving an output voltage of the first 
comparing means, which controls current flowing through the voltage 
transforming means such that the voltage between the pair of input 
terminals becomes equal to the first reference voltage. The second 
comparing means compares the output voltage of the first comparing means 
with a predetermined second reference voltage, to provide an output 
voltage corresponding to the difference therebetween. The second field 
effect device has a control terminal receiving the output voltage of the 
second comparing means, which performs control such that the absolute 
value of the output voltage of the first comparing means does not exceed a 
predetermined value. 
The first field effect device in the driver circuit according to the 
present invention is responsive to the output voltage of the first 
comparing means for controlling current flowing on a primary side of the 
voltage transforming means such that the voltage between the pair of input 
terminals becomes equal to the first reference voltage. Therefore, even if 
the impedance of a load connected between the pair of output terminals is 
fluctuated, a voltage between the output terminals is kept constant. 
Additionally, when the load impedance becomes low, the current flowing on 
the primary side of the voltage transforming means is increased to attempt 
to keep constant the voltage between the output terminals, so that the 
output voltage of the first comparing means is increased. However, when 
the load impedance becomes lower than a constant value, the second field 
effect device performs control such that the output voltage of the second 
comparing means does not exceed a predetermined value, so that the current 
flowing on the primary side of the voltage transforming means is limited 
not to exceed a constant value. Therefore, the voltage between the output 
terminals does not exceed a constant value. Thus, if the load impedance is 
large to some extent, control is performed such that the output voltage 
becomes a predetermined constant voltage. On the contrary, when the load 
impedance is small, control is performed such that the output voltage does 
not exceed a predetermined constant voltage. 
Meanwhile, in circuit techniques, it is easy to generate exact reference 
voltages. In addition, it is possible to make a voltage ratio constant 
irrespective of fluctuations in temperature and power-supply voltage. In 
the driver circuit according to the present invention, the voltage between 
the output terminals is controlled by comparison of voltages, so that 
voltage control can be precisely performed. 
As described in the foregoing, according to the present invention, even if 
the load impedance connected between the output terminals fluctuates, the 
output voltage is kept at a predetermined constant value, and control is 
performed such that the output voltage does not exceed a predetermined 
voltage if the output load impedance becomes a constant value or less. In 
addition, since the driver circuit according to the present invention 
comprises two comparing means and two field effect devices, the driver 
circuit can be constituted by a CMOS circuit, so that the driver circuit 
is incorporated together with another digital CMOS circuit in hybrid 
configuration at low cost. Furthermore, since the output voltage is 
adjusted by comparison of voltages, precise voltage adjustment can be made 
irrespective of the change in temperature and fluctuations in power-supply 
voltage, so that trimming is not required. 
The foregoing and other objects, features, aspects and advantages of the 
present invention will become more apparent from the following detailed 
description of the present invention when taken in conjunction with the 
accompanying drawings.

DESCRIPTION OF THE PREFERRED EMBODIMENTS 
Referring to the figures, an embodiment of the present invention will be 
described. 
FIG. 5 is a circuit diagram showing a structure of a driver circuit 
according to one embodiment of the present invention. 
This driver circuit comprises a first comparator 1 comprising an 
operational amplifier, a second comparator 2 comprising an operational 
amplifier, a pulse transformer 3, a switching device 4, N channel MOSFETs 
M1, M2 and M5, and P channel MOSFETs M3, M4 and M6. The MOSFET M1 is 
coupled between a node N1 and a node N3, which has its gate receiving an 
input signal I1.sub.+. The MOSFET M2 is coupled between a node N2 and the 
node N3, which has its gate receiving an input signal I1.sub.-. The MOSFET 
M3 is coupled between a power-supply potential V.sub.DD and the node N1, 
which has its gate receiving an input signal I2.sub.-. The MOSFET M4 is 
coupled between the power-supply potential V.sub.DD and the node N2, which 
has its gate receiving an input signal I2.sub.+. In addition, primary 
terminals of the pulse transformer 3 are respectively connected to the 
nodes N1 and N2. Secondary terminals of the pulse transformer 3 are 
respectively connected to output terminals O1 and O2. The turns ratio of 
the pulse transformer 3 is n:1. The switching device 4 has a terminal a 
connected to the node N1 and a terminal b connected to the node N2. 
The comparator 1 has its non-inverted input terminal receiving a controlled 
voltage Vr from a switching terminal c of the switching device 4 and its 
inverted input terminal receiving a first reference voltage Vref.sub.1. 
The second comparator 2 has its non-inverted input terminal receiving an 
output voltage V.sub.G of the first comparator 1 and its non-inverted 
input terminal receiving a second reference voltage Vref.sub.2. 
Furthermore, the MOSFET M5 is connected between the node N3 and a ground 
potential, which has its gate receiving the output voltage V.sub.G of the 
first comparator 1. The MOSFET M6 is coupled between an output terminal of 
the first comparator 1 and the ground potential, which has its gate 
receiving an output voltage of the second comparator 2. The digital 
control circuit 5 is responsive to a control input for outputting the 
above described four input signals I.sub.1+, I.sub.1- I.sub.2+, I.sub.2-. 
A reference voltage generating circuit 6 generates the first reference 
voltage Vref.sub.1 and the second reference voltage Vref.sub.2. 
Description is now made on an operation of this driver circuit. When the 
input signals I.sub.1+ and I.sub.2- are at an "H" level and the input 
signals I1.sub.- and I2.sub.+ are at an "L" level, the MOSFETs M1 and M4 
are turned on, so that current flows from the power-supply potential to 
the ground potential through the MOSFET M4, the pulse transformer 3, the 
MOSFET M1 and the MOSFET M5. Consequently, a positive pulse is outputted 
between the output terminals O1 and O2. 
On the contrary, when the input signals I.sub.1- and I.sub.2+ are at the 
"H" level and the input signals I.sub.1+ and I.sub.2- are at the "L" 
level, the MOSFETs M2 and M3 are turned on, so that current flows from the 
power-supply potential V.sub.DD to the ground potential through the MOSFET 
M3, the pulse transformer 3, the MOSFET M2 and the MOSFET M5. 
Consequently, a negative pulse is outputted between the output terminals 
O1 and O2. In the above described manner, this driver circuit can output a 
pulse of both positive and negative polarities. 
The switching device 4, the first comparator 1, the second comparator 2 and 
the MOSFET M6 constitute a control system. This control system is employed 
in common with respect to both positive and negative pulses, which has a 
structure favorable to generate the positive and negative pulses in a 
balanced manner. The switching device 4 is switched to the side of the 
terminal a when the positive pulse is outputted while being switched to 
the side of the terminal b when the negative pulse is outputted. 
Description is now made on control of the height of an output pulse by this 
control system. A case is herein described in which the positive pulse is 
outputted. 
Since the turns ratio of the pulse transformer 3 is n:1, n times the height 
of a pulse outputted between the output terminals O1 and O2 is the 
difference between a potential V2 of the node N2 and a potential V1 of the 
node N1. If the positive pulse is outputted, we obtain V2&gt;V1. Assuming 
that on-resistance of the MOSFET M4 is small, the potential V2 of the node 
N2 becomes equal to the power-supply potential V.sub.DD. Thus, a voltage 
applied to the primary side of the pulse transformer 3 is considered to 
be: 
EQU V2-V1.perspectiveto.V.sub.DD -V1 
In this case, assuming that a desired output voltage is Vexp, it is 
necessary to perform control such that the output voltage Vexp becomes 
equal to (V.sub.DD -V1)/n. (V.sub.DD -V1)/n is compared with the output 
voltage Vexp, so that current is decreased if (V.sub.DD -V1)/n is larger 
while being increased if (V.sub.DD -V1)/n is smaller. This current control 
is performed by the first comparator 1. 
If and when the positive pulse is outputted, the switching device 4 is 
switched to the side of the terminal a, resulting in Vr=V1. Thus, the 
potential V1 of the node N1 is applied to the non-inverted input terminal 
of the first comparator 1. If V1&gt;Vref.sub.1, the output voltage of the 
first comparator 1, i.e., the gate voltage V.sub.G of the MOSFET M5 
becomes high. Consequently, more current flows on the primary side of the 
pulse transformer 3. On the contrary, if V1&lt;Vref.sub.1, the output volta 
V.sub.G of the first comparator 1 becomes low. Consequently, current 
flowing on the primary side of the pulse transformer 3 becomes less. In 
the above described manner, the current flowing through the pulse 
transformer 3 is controlled such that V1=Vref.sub.1. Assuming that the 
first reference voltage Vref.sub.1 is set such that 
EQU Vref.sub.1 =V.sub.DD -Vexp.multidot.n 
we obtain: 
EQU V1=Vref.sub.1 =V.sub.DD -Vexp.multidot.n 
EQU V.sub.DD -V1=Vexp.multidot.n 
EQU V2-V1.apprxeq.Vexp.multidot.n 
EQU .thrfore.(V2-V1)/n=Vexp 
Thus, control is performed such that the height of the output pulse becomes 
Vexp. 
Meanwhile, if and when the negative pulse is outputted, a control method is 
the same as that in the above described case except that points where 
Vr=V2 differ from each other. 
In the above described manner, the heights of the output pulse at the time 
of loads of 50.OMEGA. and 400.OMEGA. can be controlled to 750mV. 
Then, when the load becomes small, for example, 5.6.OMEGA., the current 
flowing through the pulse transformer 3 attempts to increase to keep 
constant the output voltage. However, at the time of the load of 
5.6.OMEGA., it is determined that the height of the output pulse is 150mV 
or less, so that the increase in current must be prevented. When the load 
is low, a second comparator 2 controls the height of the output pulse to a 
constant value or less. 
The second comparator 2 compares the output voltage V.sub.G of the first 
comparator 1 with a second reference voltage Vref.sub.2. When 
VG&lt;Vref.sub.2, the output voltage of the second comparator 2 is high, so 
that the MOSFET M6 is turned off. When VG&gt;Vref.sub.2, the output voltage 
of the second comparator 2 becomes low, so that the MOSFET M6 is turned 
on, to be operated to lower the output voltage of the first comparator 1, 
i.e., the gate volta V.sub.G of the MOSFET M5. In the above described 
manner, control is performed such that the output voltage V.sub.G is not 
the second reference voltage Vref.sub.2 or more. Thus, the current which 
can flow through the MOSFET M5 is controlled by the second reference 
voltage Vref.sub.2, so that control is performed such that the height of 
the pulse is not a given value or more when the load is small. 
As described in the foregoing the height of the output pulse is adjusted to 
a constant value by the function of the first comparator 1 when the load 
is large to some extent while being limited not to exceed a constant value 
by the function of the second comparator when the load is small. Thus, a 
driver circuit is achieved which satisfies the pulse mask determined in 
the above described Recommendation I. 430 of the CCITT. 
Meanwhile, the first reference voltage Vref.sub.1 is adjusted so that the 
height of the output pulse can be adjusted. In addition, the second 
reference voltage Vref.sub.2 is adjusted so that a limited value of an 
output current can be changed. 
FIG. 6 is a circuit diagram showing a circuit structure of the first 
comparator 1 shown in FIG. 5. 
The first comparator 1 is structured by a CMOS circuit comprising P channel 
MOSFETs Q31 to Q36 and N channel MOSFETs Q37 to Q42. The MOSFET Q37 has 
its gate receiving a controlled voltage Vr, and the MOSFET Q41 has its 
gate receiving a first reference voltage Vref.sub.1. An output voltage 
V.sub.G is derived from a node of the MOSFETs Q35 and Q40. 
Meanwhile, in the first comparator 1, each of the MOSFETs Q31, Q32, Q35 and 
Q36 has its gate receiving a control signal .phi.0. This control signal 
.phi.0 is generally at a ground level. However, the control signal .phi.0 
is brought to a V.sub.DD level at the standby time, so that current 
flowing from a power-supply potential V.sub.DD to a ground potential is 
disconnected. As a result, current consumption is reduced. 
FIG. 7 is a circuit diagram showing a circuit structure of the second 
comparator 2 shown in FIG. 5. 
The second comparator 2 is constituted by a CMOS circuit comprising P 
channel MOSFETs Q43 and Q44 and N channel MOSFETs Q45 to Q47. The MOSFET 
Q55 has its gate receiving an output voltage V.sub.G of the first 
comparator 1, and the MOSFET Q46 has its gate receiving a second reference 
voltage Vref.sub.2. An output voltage is derived from a node of the 
MOSFETs Q43 and Q45. The MOSFET Q47 has its gate receiving a control 
signal .phi.1. This control signal .phi.1 is generally at a level. 
However, the control signal .phi.1 is brought to a ground level at the 
standby time, so that current consumption is reduced. 
FIG. 8 is a diagram showing a circuit structure of the switching device 4 
shown in FIG. 5. 
The switching device 4 is structured by a CMOS circuit comprising N channel 
MOSFETs Q48 and Q49 and P channel MOSFETs Q50 and Q51. The MOSFET Q48 has 
its gate receiving an input signal I1.sub.+, and the MOSFET Q50 has its 
gate receiving the inverted signal I1.sub.+. The MOSFET Q49 has its gate 
receiving an input signal I1.sub.-, and the MOSFET Q51 has its gate 
receiving the inverted signal I1.sub.-. When the input signal I1.sub.+ is 
at an "H" level, a terminal a is connected to a terminal c. When the input 
signal I.sub.1- is at an "H" level, a terminal b is connected to the 
terminal c. 
FIG. 9 is a diagram showing a circuit structure of the digital control 
circuit 5 shown in FIG. 5. 
The digital control circuit 5 is constituted by a CMOS circuit comprising 
inverters 61 to 75, NAND gates 76 to 79, P channel MOS transistors Q61 to 
Q64, and N channel MOS transistors Q65 to Q68. A positive pulse output 
signal AMIX1 is applied to the inverter 61, and a negative pulse output 
signal AMIX2 is applied to the inverter 62. A clock signal CLK is applied 
to the inverter 72, and a standby signal STDBY is applied to the inverter 
74. At the time of a standby mode, the standby signal STDBY attains an "H" 
level. 
An input signal I1.sub.+ to the MOSFET M1 is outputted from the inverter 
64, and an input signal I1.sub.- to the MOSFET M2 is outputted from the 
inverter 63. In addition, an input signal I2.sub.- to the MOSFET M3 is 
outputted from the inverter 66, and an input signal I2.sub.+ to the 
MOSFET M4 is outputted from the inverter 65. A control signal .phi.3 in 
phase with the clock signal CLK is outputted from the inverter 73, and a 
control signal .phi.4 out of phase with the clock signal CLK is outputted 
from the inverter 72. A control signal .phi.0 in phase with the standby 
signal STDBY is outputted from the inverter 75, and a control signal 
.phi.1 out of phase with the standby signal STDBY is outputted from the 
inverter 74. 
Referring now to a timing chart of FIG. 10, description is made on an 
operation of the digital control circuit 5. 
When the positive pulse output signal AMIX1 is at the "H" level and the 
negative pulse output signal AMIX2 is at the "L" level, the input signals 
I1.sub.+ and I2.sub.- attain the "H" level and the input signals 
I1.sub.- and I2.sub.+ attain the "L" level. Consequently, the MOSFETs M1 
and M4 are turned on and the MOSFETs M2 and M3 are turned off, so that a 
positive pulse is outputted between output terminals O1 and O2. On the 
contrary, when the positive pulse output signal AMIX1 is at the "L" level 
and the negative pulse output signal AMIX2 is at the "H" level, the input 
signals I1.sub.- and I2.sub.+ attain the "H" level and the input signals 
I1.sub.+ and I2.sub.- attain the "L" level. Consequently, the MOSFETs M2 
and M3 are turned on and the MOSFETs M1 and M4 are turned off, so that a 
negative pulse is outputted between the output terminals O1 and O2. 
Meanwhile, when both the positive pulse output signal AMIX1 and the 
negative pulse output signal AMIX2 are at the "L" level, the input signals 
I1.sub.+ and I1.sub.- attain the "L" level and the input signals 
I2.sub.+ and I2.sub.- attain the "H" level, so that all the MOSFETs M1 
to M4 are turned off. Consequently, a high impedance state is achieved 
between the output terminals O1 and O2. Thus, a terminal which does not 
provide a pulse never affects another terminal. 
Meanwhile, transition is suddenly made from a state in which a pulse is 
outputted to a state in which all the MOSFETs M1 to M4 are turned off, 
undershoot generally occurs in a final end of the pulse. In the digital 
control circuit 5 shown in FIG. 9, there is provided a delay circuit 
portion 60 to prevent occurrence of this undershoot. Thus, after the input 
signals I1.sub.+ and I1.sub.- fall to the "L" level, so that the MOSFETs 
M1 and M2 are turned off, the input signals I2.sub.+ and I2.sub.- fall 
to the "L" level only during a period corresponding to one cycle T of the 
clock signal CLK. Consequently, the MOSFETs M3 and M4 are turned on during 
the period T and then, turned off, so that occurrence of the undershoot is 
prevented. 
Although in the above described embodiment, both positive and negative 
pulses can be generated, only either one of the positive and negative 
pulses may be generated, in which case either one of a set of the MOSFETs 
M1 and M4 and a set of the MOSFETs M2 and M3 and the switching device 4 
are not generated. In this case, the non-inverted input terminal of the 
first comparator 1 is connected to one at the lower potential out of the 
nodes N1 and N2. 
Additionally, in the above described embodiment, the voltage V2-V1 applied 
to the primary side of the pulse transformer 3 is approximated by V.sub.DD 
-V1. Furthermore, if and when the accuracy is required, it is necessary to 
employ a circuit shown in FIG. 11. In FIG. 11, when a positive pulse is 
outputted, a switching device 4 is switched as represented by a solid 
line. Consequently, a potential V1 of a node N1 is applied to an inverted 
input terminal of an operational amplifier 6 through a resistor R12, and a 
potential V2 of a node N2 is applied to a non-inverted input terminal of 
the operational amplifier 6 through a resistor R11. In addition, when a 
negative pulse is outputted, the switching device 4 is switched as 
represented by a broken line. Consequently, the potential of the node N1 
is applied to the non-inverted input terminal of the operational amplifier 
6 through the resistor R11, and the potential V2 of the node N2 is applied 
to the inverted input terminal of the operational amplifier 6 through the 
register R12. A controlled voltage Vr outputted from the operational 
amplifier 6 becomes V1-V2. 
As described in the foregoing, the driver circuit shown in FIG. 5 can be 
constituted by the CMOS circuit shown in FIGS. 6 to 9. Thus, the driver 
circuit in the above described embodiment can be incorporated together 
with another CMOS digital circuit in hybrid configuration at low cost. 
Although the present invention has been described and illustrated in 
detail, it is clearly understood that the same is by way of illustration 
and example only and is not to be taken by way of limitation, the spirit 
and scope of the present invention being limited only by the terms of the 
appended claims.