Semiconductor device with NMOS transistors arranged continuously

A semiconductor device includes a plurality of PMOS transistors formed on a semiconductor substrate; and a plurality of NMOS transistors formed on the semiconductor substrate. The plurality of PMOS transistors are electrically isolated from each other by a device isolation structure formed in the semiconductor substrate. The plurality of NMOS transistors are continuously formed in a first direction such that a sequence of N-type diffusion layers of the plurality of NMOS transistors extends in the first direction. One of the plurality of PMOS transistors and one of the plurality of NMOS transistors share a gate electrode.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device. More particularly, the present invention relates to a semiconductor device including PMOS transistors and NMOS transistors, and a manufacturing method of the same.

2. Description of the Related Art

It is indispensable in designing an LSI (Large-Scaled Integrated Semiconductor Device) to use a computer for the sake of reduction in time for designing and confirmation and to eliminate man-caused mistakes. A semiconductor device design supporting system using the computer in this manner is referred to as a CAD (Computer Aided Design) system. According to a LSI designing method of cell base, cells of a plurality of types are configured as a library. A designer executes designing of LSI by utilizing CAD and allocating a desired cell in a layout space defined on the computer.

FIG. 1shows basic cells (primitive cells) for designing a conventional semiconductor device. In each of the basic cells, a power supply line102for supplying a power supply voltage VDD and a ground line103for supplying a ground voltage GND are arranged along a X-direction. The power supply line102and the ground line103are connected to a N-type diffusion layer104and P-type diffusion layer105for applying substrate voltages via contacts, respectively. Further, PMOS transistors P1to P4and NMOS transistors N1to N4are formed in a region between by the power supply line102and the ground line103. Specifically, a gate electrode110is formed along a Y-direction. P-type diffusion layers112are formed in a region for the PMOS transistors to be formed to put the gate electrode110therebetween, and N-type diffusion layers113are formed in a region for the NMOS transistors to be formed to put the gate electrode110therebetween. Further, for the sake of isolation or separation of elements, a STI (Shallow Trench Isolation) structure120is formed as an element isolation structure.

In a semiconductor device field, in many cases, a plurality of transistors are used collectively. For this reason, each of the basic cells is formed in such a manner that a “transistor group” composed of a plurality of transistors is surrounded by a STI structure120. For example, inFIG. 1, the PMOS transistor group P1and P2is surrounded by the STI structure120, and the PMOS transistor group P3and P4is surrounded by the STI structure120. That is, the PMOS transistor group P1and P2and the PMOS transistor group P3and P4are isolated or separated by the STI structures120. Further, an NMOS transistor group N1and N2is surrounded by the STI structure120and an NMOS transistor group N3and N4is surrounded by the STI structure120. That is, the NMOS transistor group N1and N2and the NMOS transistor group N3and N4are isolated by the STI structures120. Meanwhile, the length of one transistor group in the X-direction is referred to as a “diffusion layer length DL”. In other words, the diffusion layer length DL can be defined as the length between STI structures120in the X-direction.

In conjunction with the above description, a semiconductor device is disclosed in Japanese Laid open Patent Publication (JP-P2003-203989A). In this conventional example, the semiconductor device includes P-channel field effect transistors connected in a lattice form. In the semiconductor device of this type, a long active region extending over a plurality of transistors is divided for every gate electrode such that a compression stress is applied to a channel portion of the P-channel field effect transistor. A sufficiently thin STI structure is arranged between the gate electrodes.

Also, a semiconductor integrated circuit device is disclosed in Japanese Laid Open Patent Publication (JP-P2001-345430A), in which element structure MISFET and element isolation MISFET are formed on a main surface of a semiconductor substrate. The element structure MISFET and the element isolation MISFET of include a source and a drain which are formed in a semiconductor substrate, a gate insulating film formed between the source and the drain on the semiconductor substrate, and a doped gate electrode formed on the gate insulating film. Besides, a difference in work function between the gate electrode of the element isolation MISFET and the main surface of the semiconductor substrate is greater than a difference in work function between the gate electrode of the element constitution MISFET and the main surface of the semiconductor substrate.

A stress generated due to isolation of elements by the STI structure (hereinafter, to be also referred to as a STI structure stress) changes the crystal structure. The change in the crystal structure has an influence upon characteristics of transistors, for example, driving capability of a transistor. In recent years, miniaturization of the element has made remarkable progress, and the STI structure stress has become a significant problem. Namely, as the element is miniaturized, the STI structure stress that influences the driving capability of the transistor has become one of factors which cannot be ignored. For example, it is known that magnitude of ON current Ion of the transistor (drain current) fluctuates depending on change in the STI structure stress. Since the STI structure stress depends upon the above diffusion layer length DL as a distance between STI structures, the diffusion layer length DL has an effect upon magnitude of ON current Ion.

FIG. 2shows dependence of ON current Ion on the diffusion layer length DL. A vertical axis represents ON current IonN of the NMOS transistor and ON current IonP of the PMOS transistor. A horizontal axis represents the diffusion layer length DL. As shown inFIG. 2, in the PMOS transistor, when the diffusion layer length DL is shorter, the ON current IonP is larger. Contrary, in the NMOS transistor, when the diffusion layer length DL is longer, the ON current IonN is larger. In other words, the characteristics of the PMOS transistors can be improved with the shorter diffusion layer length DL and the characteristics of the NMOS transistors can be improved with the longer diffusion layer length DL.

In consideration of miniaturization of the elements, it is desired to provide a technique that can improve the characteristics of ON current (drain current) as much as possible for both the PMOS transistors and the NMOS transistors. When the diffusion layer length DL is simply elongated in the NMOS transistor, many NMOS transistors are arranged in a region between the STI structures. In this case, it is not possible to use a desired number of NMOS transistors among many NMOS transistors. In other words, if the diffusion layer length DL is simply elongated, isolation of a desired number of elements is not possible and handling of a desired number of elements is not possible accordingly.

SUMMARY OF THE INVENTION

In an aspect of the present invention, a semiconductor device includes a plurality of PMOS transistors formed on a semiconductor substrate; and a plurality of NMOS transistors formed on the semiconductor substrate. The plurality of PMOS transistors are electrically isolated from each other by a device isolation structure formed in the semiconductor substrate. The plurality of NMOS transistors are continuously formed in a first direction such that a sequence of N-type diffusion layers of the plurality of NMOS transistors extends in the first direction. One of the plurality of PMOS transistors and one of the plurality of NMOS transistors share a gate electrode.

Here, the semiconductor device may further include gate structures formed on the semiconductor substrate to extend in a second direction orthogonal to the first direction over the sequence of the N-type diffusion layers.

In this case, a voltage of the gate structures may be fixed to a ground voltage. Instead, the voltage of the gate structures may be fixed to a power supply voltage.

The gate structures may isolate the plurality of NMOS transistors in units of a predetermined number of NMOS transistors. In this case, the predetermined number may be one of two, four and six.

Also, two of the gate electrodes of the two NMOS transistors may be connected to each other. Also, four of the gate electrodes of the four NMOS transistors may be connected to each other.

Also, in another aspect of the present invention, a semiconductor device includes a plurality of transistor cells arranged in a first direction. Each of the plurality of transistor cells includes a first PMOS transistor formed on a semiconductor substrate; a second PMOS transistor formed on the semiconductor substrate adjacently to the first PMOS transistor; a device isolation structure configured to isolate the first and second PMOS transistors from each other; a first NMOS transistor formed on the semiconductor substrate; and a second NMOS transistor formed on the semiconductor substrate adjacently to the first NMOS transistor. N-type diffusion layers of the first and second NMOS transistors are arranged in the first direction.

Here, the N-type diffusion layers may reach at least one of two opposing sides of the cell orthogonal to the first direction. Especially, the N-type diffusion layers may reach the two opposing sides of the cell orthogonal to the first direction.

In this case, the cell may further include a half of a gate structure provided on the semiconductor substrate to extend over the N-type diffusion layers in a second direction orthogonal to the first direction. A remaining half of the gate structure is provided in one cell adjacent to the cell.

Also, the semiconductor device may further include a device isolation cell provided for every predetermined number of the plurality of transistor cells. The device isolation cell includes a gate structure provided on the semiconductor substrate to extend in a second direction orthogonal to the first direction; and N-type diffusion layers formed in the semiconductor substrate to be adjacent to the gate structure. The N-type diffusion layers of the device isolation cell reach two opposing sides of the device isolation cell orthogonal to the first direction.

Here, the predetermined number may be one of two, four and six.

Also, two of the gate electrodes of the two NMOS transistors may be connected to each other, and four of the gate electrodes of the fourth NMOS transistors may be connected to each other.

In another aspect of the present invention, a method of manufacturing a semiconductor device, is achieved by (A) providing a basic cell and a device isolation cell; wherein the basic cell includes: a PMOS transistor surrounded by the device isolation structure; and a first N-type diffusion layer of an NMOS transistor configured to contacting one of two opposing sides of the basic cell, and the device isolation cell includes: a second group of N-type diffusion layers configured to contact two opposing sides of the device isolation cells; and a gate structure provided on a semiconductor substrate in a region put in the second group of N-type diffusion layers, and the first N-type diffusion layer of the basic cell is formed to be aligned with the first N-type diffusion layer of another basic cell, and the second group of N-type diffusion layers the device isolation cell in a first direction, by (B) arranging the basic cell repeatedly in the first direction; and by (C) arranges the device isolation cell to be adjacent to the arranged basic cell in the first direction.

Here, the gate structure of the device isolation cell may be grounded.

Also, the basic cell may have a gate electrode of the PMOS transistor and the NMOS transistor, and the gate electrode may be formed to extend in a second direction orthogonal to the first direction.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Hereinafter, a semiconductor device and a method of manufacturing the same according to the present invention will be described in detail with reference to the attached drawings. The semiconductor device according to the present invention includes PMOS transistors and NMOS transistors.

First Embodiment

FIG. 3is a plan view showing a pattern structure of a semiconductor device1according to the first embodiment of the present invention. Referring toFIG. 3, a power supply line2for supplying a power supply voltage VDD and a ground line3for supplying a ground voltage GND are arranged to extend in an X-direction. The power supply line2is connected to an N-type diffusion layer4via contacts6to apply a power supply voltage as a substrate voltage. Further, the ground line3is connected to a P-type diffusion layer5via contacts7to apply a ground voltage as the substrate voltage. A plurality of PMOS transistors P1to P6and a plurality of NMOS transistors N1to N6are formed in a region put between the power supply line2and the ground line3. Specifically, the plurality of PMOS transistors P1to P6are formed in a PMOS region to be aligned with each other along an X-direction. Also, the plurality of NMOS transistors N1to N6are formed in a NMOS region to be aligned with each other along the X-direction.

A plurality of gate electrodes10are formed for the plurality of PMOS transistors P1to P6and the plurality of NMOS transistors N1to N6. These gate electrodes10are formed to extend in a Y-direction orthogonal to the X-direction. Also, each of the gate electrodes10is shared by one PMOS transistor and one NMOS transistor. In the PMOS region, P-type diffusion layers12are formed to put the gate electrode10therebetween. Also, in the NMOS region, N-type diffusion layers13are formed to put the gate electrode10therebetween. Further, a STI structure20is formed as an element separation structure. According to the present invention, in the PMOS region, each of the plurality of PMOS transistors P1to P6is surrounded by the STI structure20. For example, the STI structure20is formed between the PMOS transistors P1and P2. On the other hand, in the NMOS region, the plurality of NMOS transistors N1to N6are surrounded as a whole by the STI structure20. For example, the STI structure20is not formed between the NMOS transistors N2and N3. That is, the plurality of NMOS transistors N1to N6are continuously formed to be adjacent to each other and constitute a “NMOS transistor group”. In other words, one NMOS transistor group includes a large number of NMOS transistors. Meanwhile, one PMOS transistor group includes only one PMOS transistor. The length of one transistor group in the X-direction is defined to be “diffusion layer length DL”. Further, the diffusion layer length DL can be defined to be a distance between the STI structures20in the X-direction. According to the present invention, the diffusion layer length DL in the NMOS transistor group is longer than the diffusion layer length DL in the PMOS transistor group.

As shown above, each of the PMOS transistors is separated by using the STI structure20. Each of the plurality of NMOS transistors of the NMOS transistor group should be separated. Here, in order to keep the diffusion layer length DL long to a maximum extent, a separation structure other than the STI structure20should be employed. To attain this, according to the present invention, as shown inFIG. 3, a gate structure30is formed at a predetermined position in the NMOS region. The gate structure30is located in a region between adjacent NMOS transistors. Also, the gate structure30is formed on the N-type diffusion layer13to extend in the Y-direction, like the gate electrode10. The gate structure30is connected to the ground line3or the P-type diffusion layer5that is connected to the ground line3via a contact31. That is, the gate structure30is grounded and the voltage thereof is fixed to the ground voltage GND. Since the voltage of the gate structure30is the ground voltage, its gate structure30is equivalent to a transistor in OFF state. Therefore, it is possible to isolate the NMOS transistors themselves at a predetermined position in the NMOS region without using the STI structure20. For example, a gate structure30aisolates a set of the NMOS transistors N1and N2from a set of the NMOS transistors N3and N4. Further, a gate structure30bisolates a set of the NMOS transistors N3and N4from a set of the NMOS transistors N5and N6. In this way, according to the present invention, element isolation for NMOS transistors can be realized using the gate structure30in place of the STI structure20.

FIG. 4Ais a cross sectional view of the semiconductor device along the line A-A′ inFIG. 3. As shown inFIG. 4A, the PMOS transistors P3and P4are formed on N-type regions8nof a substrate8adjacently to each other. In each of the PMOS transistors, the gate electrode10is formed on the substrate8via a gate insulating film9. Also, the P-type diffusion layers12are formed in the N-type regions8nof the substrate8under the gate electrode10. Each of PMOS transistors is surrounded by the STI structure20, and the STI structure20is formed in the substrate8between the PMOS transistors P3and P4. The length of a region surrounded by the STI structure20is a diffusion layer length DL.

Also,FIG. 4Bis a sectional view of the semiconductor device along the line B-B′ inFIG. 3. As shown inFIG. 4B, the NMOS transistors N3and N4are formed on a P-type region8pof the substrate8adjacently to each other. In each of the NMOS transistors, the gate electrode10is formed on the substrate8via the gate insulating film9. The N-type diffusion layers13are formed in the P-type region8pof the substrate8in a region under the gate electrode10. Further, the gate structures30aand30bare formed on the substrate8via the gate insulating film9. The N-type diffusion layers13are formed in the substrate8in region below the gate structure30. Further, the ground voltage GND is applied to the gate structures30aand30b.

By using the semiconductor device1as shown above, and connecting appropriately the PMOS transistors and the NMOS transistors, various logic circuits are realized. The semiconductor device1shown inFIG. 3may be used in a gate array fashion. The semiconductor device1shown inFIG. 3may be provided as a foundation layer of ASIC (Application Specific Integrated Circuit). In case of ASIC, its foundation layer is used in common to many purposes and wirings meeting user requirements are formed in a customized layer as an upper layer of the foundation layer. With this configuration, a desired LSI is obtained in a short time.

As described above, according to the semiconductor device1according to the first embodiment of the present invention, the PMOS transistors are formed one by one to be surrounded by an element separation STI structure20. For this reason, the diffusion layer length DL becomes minimum and characteristics of ON current can be improved as shown inFIG. 2. On the other hand, the NMOS transistors are arranged continuously to constitute the NMOS transistor group. In the NMOS transistor group, each of the NMOS transistors is not isolated by the STI structure20. Therefore, the diffusion layer length DL becomes longer and characteristics of ON current can be improved as shown inFIG. 2. In this way, characteristics of ON current can be improved in both the PMOS transistors and the NMOS transistors. Since driving capabilities of both the PMOS transistors and the NMOS transistors are improved, the delay time is reduced.

Also, according to the first embodiment, a voltage of the gate structure30formed in the NMOS region is fixed to the ground voltage GND. Thus, it is possible to electrically isolate adjacent NMOS transistors from each other at the position of the gate structure30. That is, the element separation or isolation can be carried out by using the gate structure30without using the STI structure20that is related to deterioration of characteristics of ON current. Thus, elongation of the diffusion layer length DL in the NMOS region and the element isolation in the NMOS region are both accomplished by the gate structure30according to the first embodiment. Further, since the element separation or isolation is realized in the NMOS region, it is possible to handle the desired number of NMOS transistors in the NMOS transistor group. Thus, the designing can be carried out freely. For example, when transistors are to be used in units of two, the gate structures30aand30bmay simply be formed at the positions shown inFIG. 3. According to the first embodiment, it is possible to carry out element separation without consideration of effects by the diffusion layer length DL. Therefore, characteristic of ON current is improved and at the same time, the degree of freedom in designing is improved.

Further, according to the first embodiment, reduction of chip area usage efficiency in layout can be prevented. The diffusion layer length DL in the PMOS transistor is shortened and the diffusion layer length DL in the NMOS transistors is lengthened. Therefore, the diffusion layer lengths DL between the PMOS region and the NMOS region are different. If the element isolation is not made for the NMOS transistors, a dimension of one PROS transistor and a dimension of one NMOS transistor are different. As a result, when one NMOS transistor is allocated to one PMOS transistor, a useless region will be generated due to their dimension difference. However, according to the first embodiment, since the element isolation is realized by the gate structure30, it is possible to make the dimension of one PMOS transistor coincident with that of one NMOS transistor. Thus, since no useless region is generated, the reduction in chip area usage efficiency is prevented.

Second Embodiment

The semiconductor device1according to the present invention can be designed by cell-base technique and manufactured. For example, the structure shown inFIG. 3can be realized by a combination of a first cell41, a second cell42and a third cell43. The first cell41includes PMOS transistors P1and P2, NMOS transistors N1and N2and half of the gate structure30a. The second cell42includes PMOS transistors P3and P4, NMOS transistors N3and N4, half of the gate structure30aand half of the gate structure30b. The third cell43includes PMOS transistors P5and P6, NMOS transistors N5and N6and half of the gate structure30b. The first cell41and the second cell42are arranged so that the gate structure30ais formed when they are adjacent to each other. Further, the second cell42and the third cell43are arranged so that the gate structure30bis formed when they are adjacent to each other.

Further, the semiconductor device1according to the present invention can be also realized by a combination of cell groups of different types.FIG. 5is a plan view showing arrangement of cells in the semiconductor device according to the second embodiment of the present invention. As shown inFIG. 5, a plurality of fourth cells44and a plurality of fifth cells45are arranged in the X-direction. The fourth cell44is a basic cell. On the other hand, the fifth cell45is an element isolation cell to be used for the element isolation. The element isolation cell45is arranged adjacent to the plurality of basic cells44.

The PMOS transistors and the NMOS transistors shown inFIG. 5are formed in the basic cell (fourth cell). Specifically, the gate electrode10is formed to extend in the Y-direction orthogonal to the X-direction. One gate electrode10is shared by one PMOS transistor and one NMOS transistor. Further, the P-type diffusion layers12are formed in the PMOS region to put the gate electrode10therebetween, and the N-type diffusion layers13are formed in the NMOS region to put the gate electrode10therebetween. The N-type diffusion layer (group)13is formed to extend to an end portion of the basic cell44in the X-direction. That is, the N-type diffusion layer13is in contact with at least one of two opposing sides of the basic cell44. Meanwhile, the PMOS transistor is surrounded by the STI structure20.

The gate structure30shown inFIG. 5is formed in the element isolation cell (fifth cell)45. Specifically, the gate structure30is located in a region put between two N-type diffusion layers13(N-type diffusion layer group). The two N-type diffusion layers13extend to the ends of the element isolation cell45in the X-direction and an opposing direction. That is, each of two N-type diffusion layers13is contact with one of two opposing sides of the element isolation cell45. The gate structure30is connected to the ground line3and voltage thereof is fixed to the ground voltage GND.

As shown inFIG. 5, the N-type diffusion layers13of a certain basic cell44are lined up with the N-type diffusion layers13of other basic cell44along the X-direction. Also, the N-type diffusion layers13of the basic cell44are lined up with the N-type diffusion layers13of the element isolation cell45in the X-direction. Conversely, it is designed that when the basic cells44and the element isolation cells45are arranged continuously along the X-direction, the N-type diffusion layers13are lined up. Therefore, it is possible to elongate the diffusion layer length DL to a desired length in the NMOS region by repeatedly providing the basic cells44and the element isolation cells45. The element isolation cell45may simply be inserted appropriately at a position where electrical isolation is necessary.

FIG. 6is a sectional view of the semiconductor device along the line A-A′ and the line B-B′ inFIG. 5. In the basic cell44, the PMOS transistors and the NMOS transistors are formed on the substrate8. In each of the transistors, the gate electrode10is formed on the substrate8via the gate insulating film9. The P-type diffusion layers12and the N-type diffusion layers13are formed in the substrate8to be adjacent to a region under the gate electrode10. Further, the PMOS transistors are surrounded by the STI structure20and the STI structure20is formed in the substrate8between adjacent PMOS transistors. It is supposed that the length of the basic cell4in the X-direction is Wa. Further, in the element isolation cell45, the gate structure30is formed on the substrate8via the gate insulating film9. The N-type diffusion layers13that are equivalent to the diffusion layers of the NMOS transistor are formed to be adjacent to a region under the gate structure30. It is supposed that the length of the element isolation cell45in the X-direction is Wb. According to an example shown inFIG. 5, one basic cell44includes two PMOS transistors and two NMOS transistors. However, the number of transistors is not necessarily limited to two. For example, one basic cell44may include one PMOS transistor and one NMOS transistor. Further, one basic cell44may include four PMOS transistors and four NMOS transistors. Designing of the semiconductor device1is carried out by arranging the basic cells44and the element isolation cells45appropriately.

FIG. 7is a block diagram showing a system (CAD) for supporting design of the semiconductor device1. This semiconductor device design supporting system50includes a cell library40, a processing unit51, a memory52, a design program53, an input unit54and a display unit55. Data showing a plurality of cells are stored as a library in the cell library40. The fourth cell44and the fifth cell45for the element isolation are included in the plurality of cells. Further, as the plurality of cells, the first cell41to the third cell43may be used. The cell library40is realized by, for example, a hard disc unit.

The memory52is used as a working area in which a layout is formed and a layout space is constructed therein. The processing unit51can access the cell library40and the memory52. The design program (automatic layout tool)53is a computer program (software product) executed by the processing unit51. As the input unit54, a keyboard or a mouse is exemplified. A user (design person) can enter various commands using the input unit54while referring to information displayed on the display unit55. The user can produce a layout data showing the layout of the semiconductor device1by use of semiconductor device designing system50.

The processing unit51executes the following operation according to commands given from the design program53. First, the processing unit51builds up a layout space on the memory52. Next, the processing unit51reads out a data showing a cell to be used from the cell library40. The cell is then arranged at a predetermined position on the layout space. For example, as shown inFIG. 5, the basic cell44is arranged repeatedly in the X-direction. Then, at a predetermined position, the element isolation cell45is arranged to be adjacent to the basic cells44arranged as mentioned. Thus, it is possible to elongate the diffusion layer length DL to a desired length in the NMOS region by arranging the basic cells44and the element isolation cells45repeatedly. The element isolation cell45may be inserted appropriately in the position that needs electrical isolation. Following this, wirings for connecting transistors are provided according to a logic circuit to be designed and manufactured.

Third Embodiment

FIG. 8Ashows an example of wirings to be used for the structure of inverters as the semiconductor device according to the third embodiment of the present invention. A source of the PMOS transistor P1is connected to a power supply line by a wiring61. A source of the PMOS transistor P2is connected to the power supply line by a wiring62. A source of the NMOS transistor N1is connected to a ground line by a wiring63. A source of the NMOS transistor N2is connected to the ground line by a wiring64. A drain of the PMOS transistor P1is connected to a drain of the NMOS transistor N1by a wiring65. A drain of the PMOS transistor P2is connected to a drain of the NMOS transistor N2by a wiring66. Further, the wiring65and the wiring66are connected to each other. Further, a gate electrode10-1of the PMOS transistor P1and the NMOS transistor N1, and a gate electrode10-2of the PMOS transistor P2and the NMOS transistor N2are connected via a wiring67. With this configuration, a so-called “×2 inverter” is constituted.

Further, a source of the PMOS transistor P3is connected to the power supply line by a wiring71. A source of the PMOS transistor P4is connected to the power supply line by a wiring72. A source of the NMOS transistor N3is connected to the ground line by a wiring73. A source of the NMOS transistor N4is connected to the ground line by a wiring74. A drain of the PMOS transistor P3is connected to a drain of the NMOS transistor N3by a wiring75. A drain of the PMOS transistor P4is connected to a drain of the NMOS transistor N4by a wiring76. Besides, the wiring75and the wiring76are connected to each other. Further, a gate electrode10-3of the PMOS transistor P3and the NMOS transistor N3, and a gate electrode10-4of the PMOS transistor P4and the NMOS transistor N4are connected via a wiring77. With this configuration, a so-called “×2 inverter” is constituted.

Fourth Embodiment

FIG. 8Bis a top plan view showing another structure of inverters as the semiconductor device according to the fourth embodiment of the present invention. InFIG. 8B, identical reference numerals or symbols are used for the same components as those shown inFIG. 8Aand description thereof is omitted. InFIG. 8B, gate electrodes10-1to10-4are connected to each other via a wiring80. With this configuration, a so-called “×4 inverter” is constituted. An inverter having greater driving capability than the inverter shown inFIG. 8Ais thus realized.

In the LSI, various driving capabilities are required for inverters. According to the present embodiments, it is possible to realize inverters with various driving capabilities by changing wirings between transistors. Further, when a so-called “×8 inverter” is required, the number of repetitions of the basic cell44should be altered. Not limited to inverters, it is possible to design and manufacture various logic circuits by altering the number of times of repetition of the basic cell44and position of the element isolation cell45. Further, it is possible to carry out the element isolation by inserting the element isolation cell45having the gate structure30in the desired position without effects by the diffusion layer length DL. According to the present invention, the degree of freedom in designing is improved. Therefore, it is possible to cope minutely with user's needs.

As shown inFIG. 5, the gate electrode10is preferably formed to extend along the Y-direction. In recent years, concept of DFM (Design for Manufacturing) are attracting attentions. In the DFM, a design rule is prepared considering a manufacturing process. For example, in order to reduce a circuit region, when a gate electrode is designed to pass through a complicated route, there is a possibility of generation of deviation in the width of gate polysilicon in actual manufacturing stage. That is, a gate electrode with a complicated configuration may result in deviation in the gate length L of transistors at manufacturing. The deviation in the gate length L is one of factors of deviation in characteristics of transistors. For this reason, according to the concept of DFM, it is preferable that the gate electrode10be designed to be a linear straight line at designing stage. With this consideration, the deviation in the gate length L is suppressed at actual designing stage. Therefore, performances of transistors are improved. According to the present invention, time and effort for considering effects of the diffusion layer length DL (STI structure stress) and deviation in the gate length L are eliminated.

Fifth Embodiment

FIG. 9is a top plan view of the semiconductor device according to the fifth embodiment of the present invention. InFIG. 9, the same reference numerals or symbols are used for same components as those shown inFIG. 3, and the description thereof is omitted appropriately. In a semiconductor device1′ according to the fifth embodiment, a gate structure90is used instead of the gate structure30connected to the ground line3. For example, inFIG. 9, a gate structure90ais arranged between NMOS transistors N2and N3. Besides, a gate structure90bis arranged between NMOS transistors N3and N4. These gate structures90are connected to the power supply line2and the voltage thereof is fixed to the power supply voltage VDD.

FIG. 10Ais a sectional view of the semiconductor device according to the fifth embodiment along the line A-A′ inFIG. 9. As shown inFIG. 10A, the PMOS transistors P3and P4are formed on the N-type regions8nof the substrate8adjacently to each other. In each of PMOS transistors, the gate electrode10is formed on the substrate8via the gate insulating film9. Further, the P-type diffusion layers12are formed in the N-type regions8nof the substrate8to be adjacent to a region under the gate electrode10. Each of the PMOS transistors is surrounded by the STI structure20and the STI structure20is formed in the substrate8between the PMOS transistors P3and P4. Further, the gate structures90aand90bare formed on the STI structure20via the gate insulating film9. Also,FIG. 10Bis a sectional view of the semiconductor device according to the fifth embodiment along the line B-B′ inFIG. 9. As shown inFIG. 10B, the NMOS transistors N3and N4are formed on the =type region8pof the substrate8adjacently to each other. In each of NMOS transistors, the gate electrode10is formed on the substrate8via the gate insulating film9. The N-type diffusion layers13are formed in the substrate8to be adjacent to a region under the gate electrode10. Further, the gate structures90aand90bare formed on the substrate8via the gate insulating film9. The N-type diffusion layers13are formed in the substrate8to be adjacent to a region under the gate structure90. Further, power supply voltage VDD is applied to the gate structures90aand90b.

By using the gate structure90as mentioned above, it is possible to realize a circuit in which the number of PMOS transistors and the number of NMOS transistors are asymmetrical. For example, it is possible to realize a circuit of two PMOS transistors and four NMOS transistors. As a matter of fact, the grounded gate structure30may simply be formed in the position in which electrical isolation is needed, with a similar manner as the first embodiment. With this configuration, the element isolation is also realized. Such a structure is possible simply because no STI structure20is formed in the NMOS region. The gate structure is formed between adjacent NMOS transistors instead of the STI structure20, and a voltage to be applied to the gate structure may be determined depending on the desired circuit.

According to the fifth embodiment, in a similar manner to the first embodiment, the characteristic of ON current can be improved for both the PMOS transistors and the NMOS transistors. Since driving capabilities of both PMOS transistors and the NMOS transistors can be improved, a delay time is reduced. Further, the semiconductor device1′ may be designed and manufactured based on the cell-base technique in a similar manner as the second embodiment. In such a case, in addition to the fourth cell (basic cell)44and the fifth cell (element isolation cell)45, a sixth cell46shown inFIG. 9may be used. It becomes possible to realize various logic circuits by disposing the fourth cell44repeatedly and by inserting the fifth cell45or the sixth cell46at the desired position.