Methods for fabricating semiconductor device

Methods for fabricating a semiconductor device include forming a composite film, forming a rough pattern on the composite film, forming a smooth pattern by subjecting the rough pattern to ion implantation and a plasma treatment, and patterning the composite film using the smooth pattern as a first mask.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority from Korean Patent Application No. 10-2015-0109463 filed on Aug. 3, 2015 in the Korean Intellectual Property Office, and all the benefits accruing therefrom under 35 U.S.C. 119, the contents of which in its entirety are herein incorporated by reference.

BACKGROUND

Technical Field

Example embodiments of the present disclosure relate to methods for fabricating a semiconductor device.

Description of the Related Art

As miniaturization of the semiconductor device increases, uniformity in the widths of the patterns inside of the semiconductor device can affect the intervals of the patterns or thickness thereof. Specifically, due to the resolution limits, the line edge roughness (LER) of a linear pattern has become an important factor to consider, to achieve reliability of the semiconductor device patterned by photolithography.

SUMMARY

Example embodiments of the present disclosure relate to methods for fabricating a semiconductor device having enhanced line edge roughness of a pattern.

According to some example embodiments of the present inventive concepts, there is provided a method for fabricating a semiconductor device, the method including forming a composite film, forming a rough pattern on the composite film, forming a smooth pattern by subjecting the rough pattern to ion implantation and plasma treatment and patterning the composite film using the smooth pattern as a first mask.

The rough pattern may have a line edge roughness (LER) greater than a LER of the smooth pattern.

The forming a rough pattern may comprise forming a photo resist (PR).

The forming a rough pattern may comprise forming a mask film on the composite film, forming a shielding film partially exposing the mask film, and subjecting the exposed mask film to exposure.

The subjecting the exposed mask film to exposure may comprise irradiating an argon fluoride (ArF) laser or an extreme ultra violet (EUV) laser.

The forming a rough pattern may comprise forming an amorphous carbon layer (ACL).

The forming a rough pattern may comprise depositing the rough pattern by chemical vapor deposition (CVD).

The subjecting the rough pattern to ion implantation may include applying ions selected from at least one of C, Ar, H2and O2to the rough pattern.

The subjecting the rough pattern to a plasma treatment may comprise using HBr or He plasma.

The ion implantation and the plasma treatment may be performed in-situ.

The forming a composite film may comprise forming a hard mask film and a first sacrificial layer on the hard mask film. The patterning the composite film using the smooth pattern as a first mask may comprise forming a first sacrificial pattern by patterning the first sacrificial layer, forming a first spacer on a sidewall of the first sacrificial pattern, and patterning the hard mask film using the first spacer as a second mask.

The forming a composite film may further comprise forming a second sacrificial layer on the first sacrificial layer. The forming a first sacrificial pattern may comprise forming a second sacrificial pattern by patterning the second sacrificial layer using the smooth pattern as the first mask, and forming a second spacer on a sidewall of the second sacrificial pattern, and wherein the forming a first sacrificial pattern by patterning the first sacrificial layer includes using the second spacer as a third mask.

According to some example embodiments of the present inventive concepts, there is provided a method for fabricating a semiconductor device, the method comprising forming a hard mask film and a first sacrificial layer sequentially on a substrate, forming a rough pattern on the first sacrificial layer, forming a smooth pattern by subjecting be rough pattern to ion implantation and plasma treatment, forming a first sacrificial pattern by patterning the first sacrificial layer using the smooth pattern as a first mask, forming a first spacer on a sidewall of the first sacrificial pattern, forming a hard mask pattern by patterning the hard mask film using the first spacer as a second mask, and forming a first fin-type pattern and a second fin-type pattern by patterning the substrate using the hard mask pattern as a third mask, a distance between the first fin-type pattern and the second fin-type pattern being equal to a width of the first sacrificial pattern.

The method may further comprise forming a second sacrificial layer on the first sacrificial layer, the rough pattern being formed on the second sacrificial layer. The forming the first sacrificial pattern may comprise forming a second sacrificial pattern by patterning the second sacrificial layer using the smooth pattern as the first mask, and forming a second spacer on a sidewall of the second sacrificial pattern, the forming a first sacrificial pattern by patterning the first sacrificial layer further includes using the second spacer as a third mask.

The method may further comprise forming a second sacrificial layer on the first sacrificial layer in a first region of the substrate, the rough pattern being formed on the second sacrificial layer. The forming a smooth pattern may comprise forming a first smooth pattern by performing the ion implantation and the plasma treatment in the first region, and forming a second smooth pattern by performing the plasma treatment in a second region of the substrate. The forming a first sacrificial pattern may comprise forming, in the first region, a second sacrificial pattern by patterning the second sacrificial layer using the first smooth pattern as a third mask, forming a second spacer on a sidewall of the second sacrificial pattern, the patterning the first sacrificial layer further including using the second spacer as a fourth mask, and forming, in the second region, a first sacrificial pattern by patterning the first sacrificial layer using the second smooth pattern as a fifth mask.

According to example embodiments, a method of fabricating a semiconductor device includes reducing a line edge roughness (LER) of a rough pattern, using ion implantation and a plasma treatment, to form a smooth pattern, the rough pattern being on a composite film, and the composite film being on a substrate; patterning the composite film using the smooth pattern as a first mask to form a composite pattern; and patterning the substrate using the composite pattern as a second mask to form a fin-type pattern.

The reducing a line edge roughness (LER) of the rough pattern may include (i) reducing the LER of the rough pattern to form a first smooth pattern, and (ii) reducing a LER of the first smooth pattern to form a second smooth pattern.

The reducing the LER of the rough pattern may include implanting ions in the rough pattern, and the reducing the LER of the first smooth pattern may include performing the plasma treatment on the first smooth pattern.

The reducing the LER of the rough pattern may include performing the plasma treatment on the rough pattern. The reducing the LER of the first smooth pattern may include implanting ions in the first smooth pattern.

The method may include providing a first rough pattern on a first region of the composite film, the first region including a first sacrificial layer and a hard mask film, and providing a second rough pattern on a second region of the composite film, the second region including a second sacrificial layer, the first sacrificial layer, and the hard mask film. The reducing a line edge roughness (LER) of the rough pattern may include reducing a LER of the first and second rough patterns by implanting ions in the first and second rough patterns to form a first smooth pattern and a second smooth pattern, respectively, providing a shielding film over the first smooth pattern, and reducing a LER of the second smooth pattern performing the plasma treatment on the second smooth pattern.

DETAILED DESCRIPTION

Various example embodiments will now be described more fully with reference to the accompanying drawings in which some example embodiments are shown. However, specific structural and functional details disclosed herein are merely representative for purposes of describing example embodiments. Thus, the invention may be embodied in many alternate forms and should not be construed as limited to only example embodiments set forth herein. Therefore, it should be understood that there is no intent to limit example embodiments to the particular forms disclosed, but on the contrary, example embodiments are to cover all modifications, equivalents, and alternatives falling within the scope.

In the drawings, the thicknesses of layers and regions may be exaggerated for clarity, and like numbers refer to like elements throughout the description of the figures.

It will be understood that, if an element is referred to as being ibe various elements, these elements should not be limited by these terms. These term to the other element or intervening elements may be present. In contrast, if an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. Other words used to describe the relationship between elements should be interpreted in a like fashion (e.g., “between” versus “directly between,” “adjacent” versus “t will be understood that,

Spatially relative terms e.g., or the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, un it will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, for example, the term “below” can encompass both an orientation that is above, as well as, below. The device may be otherwise oriented (rotated 90 degrees or viewed or referenced at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

Herein below, a method for fabricating a semiconductor device according to some example embodiments will be explained with reference toFIGS. 1 to 14.

FIGS. 1 to 14are views illustrating intermediate stages of fabrication, provided to explain a method for fabricating a semiconductor device according to some example embodiments.FIG. 2is a cross sectional view taken on line A-A ofFIG. 1, andFIG. 7is a cross sectional view taken on line B-B ofFIG. 6,

Referring toFIGS. 1 and 2, a composite film200is formed on a substrate100. The composite film200includes a hard mask film210and a first sacrificial layer220. The hard mask film210and the first sacrificial layer220may be stacked in sequence on the substrate100. Specifically, the hard mask film210may be formed on the substrate100and the first sacrificial layer220may be formed on the hard mask film210.

The substrate100may be a silicon substrate, a bulk silicon or a silicon-on-insulator (SOI), for example. Alternatively, the substrate100may include an element semiconductor such as germanium, or a compound semiconductor such as a IV-IV group compound semiconductor or a group compound semiconductor, for example. Alternatively, the substrate100may be a base substrate having an epitaxial layer formed thereon.

Take the IV-IV group compound semiconductor for instance, this may be a binary compound or a ternary compound including at least two or more of carbon (C), silicon (Si), germanium (Ge), and tin (Sn), or such binary or ternary compound doped with a IV group element.

Take a III-V group compound semiconductor for instance, this may be one of a binary compound, ternary compound and quaternary compound which is formed by a combination of at least one of aluminum (Al), gallium (Ga), and indium (In) as a III group element, with one of phosphorus (P), arsenic and antimony (Sb) as a V group element.

The hard mask film210may include silicon nitride SixNy. For example, the hard mask film210may include Si3N4. Alternatively, the hard mask film210may include SiO2. In some example embodiments, the hard mask film210may be formed of a plurality of layers. The plurality of layers may each include at least one of silicon-containing material such as silicon oxide (SiOx), silicon oxynitride (SiON), silicon nitride (SixNy), tetraethyl orthosilicate (TEOS) or polycrystalline silicon, carbon-containing material such as amorphous carbon layer (ACL) or spin-on hardmask (SOH) and metal. However, example embodiments are not limited to the example given above.

The first sacrificial layer220may include any one of polycrystalline silicon, ACL and SOH.

Although not illustrated inFIG. 2, anti-reflection layers may be formed between the hard mask film210and the first sacrificial layer220, and between the first sacrificial layer220and a rough pattern RP. The anti-reflection layer may be formed of silicon oxynitride film (SiON). The anti-reflection layers are the layers provided to prevent reflection of light against underlying layers during photolithography process. The hard mask film210and the first sacrificial layer220, and the anti-reflection layer may be for by the process such as atomic layer deposition (ALD), chemical vapor deposition (CVD) or spin coating, possibly added with baking or curing depending on materials used.

The rough pattern RP may be formed on the first sacrificial layer220. The rough pattern RP may extend in the first direction Y. There may be a plurality of rough patterns RP, which may be spaced apart from each other in a second direction X, Compared to a first smooth pattern SP1and a second smooth pattern SP2which will be described below, the rough pattern RP may have a relatively greater line edge roughness LER. That is, edges may be relatively more jagged

The rough pattern RP may include a photo resist (PR). The rough pattern RP may be formed by exposing a mask film and then patterning the same. At this time, the light source for use in exposure may be a krypton fluoride (ktF) laser, an argon fluoride (ArF) laser, or an extreme ultra violet (EUV) laser. At this time, the argon fluoride laser may expose finer pattern than the krypton fluoride laser, and the extreme ultra violet laser may expose the finest pattern.

Accordingly, when exposed to an argon fluoride laser and an extreme ultra violet, the patterns may have finer intervals and widths. Given this, the light edge roughness can be considered relatively more important than in the case of exposure with the krypton fluoride laser. That is, the high line edge roughness among the finer patterns may increase a risk of short among the patterns, which will increase need for an enhancement process thereof.

The rough pattern RP may additionally include an amorphous carbon layer (ACL). At this time, the rough pattern RP may be formed by the chemical vapor deposition (CVD) and then patterned by partial etching. In the above example, again, it is necessary to enhance the LER of the rough pattern RP. Accordingly, the rough pattern RP may be changed into a first smooth pattern SP1and a second smooth pattern SP2in the subsequent processes.

Referring toFIGS. 3 and 4, the rough pattern RP may be subject to ion implantation300. The ion implantation300may involve a method of introducing ions e rough pattern RP to thus enhance the line edge roughness of the rough pattern RP.

At this time, the ions (I) for the ion implantation300may be at least one substance of C, Ar, H2and O2. For example, the ions (I) may be carbon (C) ions.

The rough pattern RP may become the first smooth pattern SP1by the ion implantation300. Compared to the rough pattern RP, the first smooth pattern SP1may have enhanced LER. The first smooth pattern SP1may be in such a condition that ions (I) are introduced therewithin by the ion implantation300.

Referring toFIG. 5, the first smooth pattern SP1may be subject to plasma treatment400. The plasma treatment400may be performed in-situ of the ion implantation300. However, example embodiments are not limited thereto. Accordingly, the plasma treatment400may be performed ex-situ of the ion implantation300.

The plasma treatment400may use HBr or He plasma. However, example embodiments are not limited to the example given above. The first smooth pattern SP1may have further enhanced LER due to the plasma treatment400. That is, the first smooth pattern SP1may have more even edges by the plasma treatment.

Referring toFIGS. 6 and 7, the first smooth pattern SP1may become the second smooth pattern SP2by the plasma treatment400. The second smooth pattern SP2may have relatively enhanced LER than the first smooth pattern SP1. That is, the second smooth pattern SP2may have relatively smoother edges than those of the first smooth pattern SP1.

As a result, the rough pattern RP may become the second smooth pattern SP2of enhanced LER, by the ion implantation300and the plasma treatment400. The second smooth pattern SP2may be the pattern of enhanced LER which is greater than the LER of the rough pattern RP as well as the first smooth pattern SP1. The LER of the second smooth pattern SP2may influence the LERs of the patterns to be formed, considering that it may be used as a mask for the double patterning technology (DPT) or quadruple patter technology (QPT) which will follow. That is, when the LER of the second smooth pattern SP2is enhanced, the LERs of the to-be-formed patterns can be automatically enhanced. It is possible to enhance reliability and performance of the semiconductor device by enhancing the LER of the second smooth pattern SP2, especially in a process that forms micro patterns with the double patterning technology or quadruple patterning technology.

Referring toFIG. 8, the first sacrificial layer220may be patterned with the second smooth pattern SP2as a mask. The first sacrificial layer220may be patterned with the second smooth pattern SP2as a mask, by anisotropic etching. The first sacrificial layer220may be patterned into a first sacrificial pattern220P. The first sacrificial pattern220P may be transferred by the second smooth pattern SP2so that it is formed with similar LER. That is, the more the LER of the second smooth pattern SP2is enhanced, the more the LER of the first sacrificial pattern220P may be enhanced.

Referring toFIG. 9, the second smooth pattern SP2may be removed. The second smooth pattern SP2may be removed by ashing or etching. However, example embodiments are not limited to the example given above. The removal of the second smooth pattern SP2may allow the upper surface of the first sacrificial pattern220P to be exposed.

Referring toFIG. 10, a first spacer500may be formed on a sidewall of the first sacrificial pattern220P. The material for the first spacer500may include a material with an etch selectivity to the first sacrificial pattern220P. For example, when the first sacrificial pattern220P is formed of any one of polycrystalline silicon, amorphous carbon layer (ACL) and spin-on hardmask (SOH), the material for the first spacer500may be formed of silicon oxide or silicon nitride. The first spacer500may be formed by patterning the film formed by the atomic layer deposition (ALD). However, example embodiments are not limited to the example given above.

The LER of the first spacer500may be influenced by the LER of the first sacrificial pattern220P. Accordingly, the more the LER of the first sacrificial pattern220P is enhanced, the more the LER of the first spacer500can be enhanced.

Although not illustrated, trimming process may be added to adjust width of the first spacer500. The width of the first spacer500can determine the width of fin-type patterns F1, F2to be formed later. The trimming process may be performed by wet etching. The etchant may be HF-based, although not limited thereto.

Referring toFIG. 11, the first sacrificial pattern220P may be removed. As described above, the first sacrificial pattern220P has an etch selectivity to the first spacer500. Accordingly, selective removal may be performed so that the first spacer500is not removed. With the removal of the first sacrificial pattern220P, the first spacer500may have the interval corresponding to the width of the first sacrificial pattern220P in the second direction X.

Referring toFIG. 12, the hard mask film210may be patterned with the first spacer500as a mask. That is, the hard mask film210may be selectively removed, leaving only the area overlapped with the first spacer500. As a result, the hard mask film210may be patterned into a hard mask pattern210P in a bar-shaped pattern. The hard mask pattern210P may be positioned at a same or similar interval as the first spacer500.

The LER of the hard mask pattern210P may be influenced by the LER of the first spacer500. Accordingly, the more the LER, of the first spacer500is enhanced, the more the LER of the hard mask pattern210P can be enhanced.

Referring toFIG. 13, the first spacer500is removed, and the substrate100is patterned with the hard mask pattern210P as a mask so that fin-type patterns F1, F2are formed.

The fin-type patterns F1, F2may include a first fin-type pattern F1and a second fin-type pattern F2. The first fin-type pattern F1and the second fin-type pattern F2may respectively correspond to the two first spacers500formed on both sidewalls of the first sacrificial pattern220P. The interval in the second direction X between the first fin-type pattern F1and the second fin-type pattern F2may be same as the width of the first sacrificial pattern220P in the second direction X. The expression “same” as used herein is the concept that encompasses presence of minute stepped portions.

The LER of the fin-type patterns F1, F2may be influenced by the LER of the hard mask pattern210P. Accordingly, the more the LER of the hard mask pattern210P is enhanced, the more the LER of the fin-type patterns F1, F2can be enhanced. That is, as the LER, of the rough pattern RP is enhanced to the LER of the second smooth pattern SP2, it can be enhanced to the LER of the fin-type patterns F1, F2. In the case of micro pattern forming process such as DPT process, enhanced LER of the fin-type patterns F1, F2can result in a reduced risk of short between the fin-type patterns F1F2. As a result, the reliability of the semiconductor device can be enhanced significantly.

Referring toFIG. 14, the hard mask pattern210P may be removed. The removal of the hard mask pattern210P may allow the upper surfaces of the fin-type patterns F1, F2to be exposed.

The fin cut process may be added after forming of the fin-type patterns F1, F2to partially remove the fin-type patterns F1, F2. Next, an interlayer insulating film may be so formed as to partially cover the fin-type patterns F1, F2, and a gate electrode may be formed on the fin-type patterns F1, F2in the second direction X. A transistor may then be formed by forming source/drain on both sides of the gate electrode in the first direction Y.

As described above, in certain example embodiments, the LER of the rough patter RP may be enhanced to thus enhance LERs of the patterns to be formed later. The enhanced LER can ensure reliability of the semiconductor device which is formed in micro patterns.

Herein below, a method for fabricating a semiconductor device according to some example embodiments will be explained with reference toFIGS. 1, 2, 8 to 14, and 15 to 17. In the following description, description overlapped with the exemplary embodiments already provided above will not be described or described as brief as possible for the sake of brevity.

FIGS. 15 to 17are views illustrating intermediate stages of fabrication, provided to explain a method for fabricating a semiconductor device according to some example embodiments.

Example embodiments will be described with reference toFIG. 15, while the example embodiments described above with reference toFIGS. 1 and 2will not be described in detail for the sake of brevity. According to example embodiments described above, ion implantation may be first performed, followed by the plasma treatment, although the sequence of the treatments may vary depending on embodiments.

That is, referring toFIG. 15, the plasma treatment400may be performed on the rough pattern RP before the ion implantation300.

The plasma treatment400may use HBr or He plasma. However, example embodiments are not limited to the example given above. That is, the rough pattern RP may have further enhanced LER by the plasma treatment400. That is, the rough pattern RP may have more even edges by the plasma treatment. The rough pattern RP may become a third smooth pattern SP3by the plasma treatment400,

Referring toFIGS. 16 and 17, after the third smooth pattern SP3is formed by the plasma treatment400, the ion implantation300may be performed on the third smooth pattern SP3.

The ion implantation300may involve a method of introducing ions (I) into the third smooth pattern SP3to thus enhance the LER of the third smooth pattern SP3.

At this time, the ions (I) for the ion implantation300may be at least one substance of C, Ar, H2and O2. For example, the ions (I) may be carbon (C) ions.

The rough pattern RP may become a fourth smooth pattern SP4by the ion implantation300. Compared to the third smooth pattern SP3, the fourth smooth pattern SP4may have relatively enhanced LER. The fourth smooth pattern SP4may be in such a condition that ions (I) are introduced therewithin by the ion implantation300.

The ion implantation300may be performed in-situ of the plasma treatment400. However, example embodiments are not limited thereto. Accordingly, the ion implantation300may be performed ex-situ of the plasma treatment400.

Next, the fin-type patterns F1, F2may be formed as illustrated inFIGS. 8 to 14. This will not be redundantly described as the same has already been described above.

Herein below, a method for fabricating a semiconductor device according to some example embodiments will be explained with reference toFIGS. 1 to 7, and 18 to 26. In the following description, description overlapped with the example embodiments already provided above will not be described or described as brief as possible for the sake of brevity.

FIGS. 18 to 26are views illustrating intermediate stages of fabrication, provided to explain a method for fabricating a semiconductor device according to some example embodiments.

Referring toFIGS. 1 to 7 and 18, compared to the example embodiments described above, the composite film200may additionally include a second sacrificial layer230. The rough pattern RP may become the second smooth pattern SP2of enhanced LER, by the ion implantation300and the plasma treatment400.

The second sacrificial layer230may include any one of polycrystalline silicon, ACL and SOH. Although not illustrated, anti-reflection layers may be formed between the first sacrificial layer220and the second sacrificial layer230, and between the second sacrificial layer230and the rough pattern RP. The anti-reflection layer may be formed of silicon oxynitride film (SiON). The anti-reflection layers are the layers provided to prevent reflection of light against underlying layers during photolithography process. The second sacrificial layer230and the anti-reflection layer may be formed by the process such as atomic layer deposition (ALD), chemical vapor deposition (CVD) or spin coating, possibly added with baking or curing depending on materials used.

Referring toFIG. 19, the second sacrificial layer230may be patterned with the second smooth pattern SP2as a mask. The second sacrificial layer230may be patterned with the second smooth pattern SP2as a mask, by anisotropic etching. The second sacrificial layer230may be patterned into the second sacrificial pattern230P. The second sacrificial pattern230P may be transferred by the second smooth pattern SP2so that it is formed with similar LER. That is, the more the LER of the second smooth pattern SP2is enhanced, the more the LER of the second sacrificial pattern230P can be enhanced.

Referring toFIG. 20, the second smooth pattern SP2may be removed. The second smooth pattern SP2may be removed by ashing or etching. However, example embodiments are not limited to the example given above. The removal of the second smooth pattern SP2may allow the upper surface of the second sacrificial pattern230P to be exposed.

A second spacer550may then be formed on a sidewall of the second sacrificial pattern230P. The material for the second spacer550may include a material with an etch selectivity to the second sacrificial pattern230P. For example, when the second sacrificial pattern230P is formed of any one of polycrystalline silicon, amorphous carbon layer (ACL) and spin-on hardmask (SOH), the material for the second spacer550may be formed of silicon oxide or silicon nitride. The second spacer550may be formed by patterning the film formed by the atomic layer deposition (ALD). However, example embodiments are not limited to the example given above.

The LER of the second spacer550may be influenced by the LER of the second sacrificial pattern230P. Accordingly, as the LER of the second sacrificial pattern230P is enhanced, the LER of the second spacer550can be enhanced.

Although not illustrated, trimming process may be added to adjust width of the second spacer550. The width of the second spacer550can determine the interval of the fin-type patterns F1, F2to be formed later. The trimming process may be performed by wet etching. At this time, the etchant may be HF-based, although example embodiments are not limited thereto.

Referring toFIG. 21, the second sacrificial pattern230P may be removed. As described above, the second sacrificial pattern230P has an etch selectivity to the second spacer550. Accordingly, selective removal may be performed so that the second spacer550is not removed. With the removal of the second sacrificial pattern230P, the second spacer550may have the interval corresponding to the width of the second sacrificial pattern230P in the second direction X.

Referring toFIG. 22, the first sacrificial layer220may be patterned with the second spacer550as a mask. That is, the first sacrificial layer220may be selectively removed, leaving only the area overlapped with the second spacer550. As a result, the first sacrificial layer220may be patterned into a first sacrificial pattern220P which is a bar-shaped pattern. The first sacrificial pattern220P may be positioned at a same or similar interval as the second spacer550.

The LER of the first sacrificial pattern220P may be influenced by the LER of the second spacer550. Accordingly, the more the of the second spacer550is enhanced, the more the LER of the first sacrificial pattern220P can be enhanced.

Referring toFIG. 23, the second spacer550may be removed, and the first spacer500may be formed on a sidewall of the first sacrificial pattern220P. The material for the first spacer500may include a material with an etch selectivity the first sacrificial pattern220P. The first spacer500may be formed by patterning the film formed by the atomic layer deposition (ALD). However, example embodiments are not limited to the example given above.

The LER of the first spacer500may be influenced by the LER of the first sacrificial pattern220P. Accordingly, the more the LER of the first sacrificial pattern220P is enhanced, the more the LER of the first spacer500can be enhanced.

Although not illustrated, trimming process may be added to adjust width of the first spacer500. The width of the first spacer500can determine the width of fin-type patterns F1, F2to be formed later. The trimming process may be performed by wet etching. At this time, the etchant may be HF-based, although example embodiments are not limited thereto,

Referring toFIG. 24, the first sacrificial pattern220P may be removed. As described above, the first sacrificial pattern20P has an etch selectivity to the first spacer500. Accordingly, a selective removal may be performed so that the first spacer500is not removed. With the removal of the first sacrificial pattern220P, the first spacer500may have the interval corresponding to the width of the first sacrificial pattern220P in the second direction X.

Next, the hard mask film210may be patterned with the first spacer500as a mask. That is, the hard mask film210may be selectively removed, leaving only the area overlapped with the first spacer500. As a result, the hard mask film210may be patterned into a hard mask pattern210P in a bar-shaped pattern. The hard mask pattern210P may be positioned at a same or similar interval as the first spacer500.

The LER of the hard mask pattern210P may be influenced by the LER of the first spacer500. Accordingly, the more the LER of the first spacer500is enhanced, the more the LER of the hard mask pattern210P can be enhanced.

Referring toFIG. 25, the first spacer500may be removed, and the substrate100may be patterned with the hard mask pattern210P as a mask so that fin-type patterns F1, F2are formed.

The fin-type patterns F1, F2may include a first fin-type pattern F1and a second fin-type pattern F2. The first fin-type pattern F1and the second fin-type pattern F2may respectively correspond to the two first spacers500formed on both sidewalls of the first sacrificial pattern220P. The interval in the second direction X between the first fin-type pattern F1and the second fin-type pattern F2may be same as the width of the first sacrificial pattern220P in the second direction X. The expression “same” as used herein is the concept that encompasses presence of minute stepped portions.

The LER of the fin-type patterns F1, F2may be influenced by the LER, of the hard mask pattern210P. Accordingly, the more the LER of the hard mask pattern210P is enhanced, the more the LER of the fin-type patterns F1, F2can be enhanced. That is, as the LER, of the rough pattern RP is enhanced to the LER of the second smooth pattern SP2, it can be enhanced to the LER of the fin-type patterns F1, F2. In the case of micro pattern forming process such as QPT process, enhanced LER of the fin-type patterns F1, F2can result in a reduced risk of short between the fin-type patterns F1, F2. As a result, the reliability of the semiconductor device can be enhanced significantly,

Referring toFIG. 26, the hard mask pattern210P may be removed. The removal of the hard mask pattern210P may allow the upper surfaces of the fin-type patterns F1, F2to be exposed.

The fin cut process may be added after forming of the fin-type patterns F1, F2to partially remove the fin-type patterns F1, F2. Next, an interlayer insulating film may be so formed as to partially cover the fin-type patterns F1, F2, and a gate electrode may be formed on the fin-type patterns F1, F2in the second direction X. A transistor may then be formed by forming source/drain on both sides of the gate electrode in the first direction Y.

As described above, in certain example embodiments, the LER of the rough pattern RP may be enhanced to thus enhance LERs of the patterns to be formed later. The enhanced LER, can ensure reliability of the semiconductor device formed in micro patterns.

Herein below, a method for fabricating a semiconductor device according to some example embodiments will be explained with reference toFIGS. 27 to 39. In the following description, description overlapped with the example embodiments already provided above will not be described or described as brief as possible for the sake of brevity.

FIGS. 27 to 39are views illustrating intermediate stages of fabrication, provided to explain a method for fabricating a semiconductor device according to some example embodiments.

Referring toFIG. 27, the substrate100may include a first region I and a second region II. The first region I and the second region II may be the regions adjacent to each other or spaced apart from each other. In the first region I, the composite film200on the substrate100may include the hard mask film210and the first sacrificial layer220. In the second region II, the composite film200on the substrate100may include the hard mask film210, the first sacrificial layer220and the second sacrificial layer230.

In the first region I, the rough pattern RP may be formed on the first sacrificial layer220, and in the second region II, the rough pattern RP may be formed on the second sacrificial layer230.

Although not illustrated in the drawings, anti-reflection layers may be formed between the hard mask film210and the first sacrificial layer220, between the first sacrificial layer220and the rough pattern RP, and between the second sacrificial layer230and the rough pattern RP. The anti-reflection layer may be formed of silicon oxynitride film (SiON). The anti-reflection layers are the layers provided to prevent reflection of light against underlying layers during photolithography process. The hard mask film210, the first sacrificial layer220, the second sacrificial layer230, and the anti-reflection layer may be formed by the process such as atomic layer deposition (ALD), chemical vapor deposition (CVD) or spin coating, possibly added with baking or curing depending on materials used.

Referring toFIGS. 28 and 29, the rough pattern RP in the first region I and the second region II may be subject to ion implantation300. The ion implantation300may involve a method of introducing ions (I) into the rough pattern RP to thus enhance the line edge roughness of the rough pattern RP.

At this time, the ions (I) for the ion implantation300may be at least one substance of C, Ar, H2and O2. For example, the ions (I) may be carbon (C) ions.

The rough pattern RP may become the first smooth pattern SP1by the ion implantation300. Compared to the rough pattern RP, the first smooth pattern SP1may have relatively enhanced LER. The first smooth pattern SP1may be in such a condition that ions (I) are introduced therewithin by the ion implantation300.

Referring toFIG. 30, a shielding film600may be formed in the first region I. The shielding film600may not be formed in the second region II. The shielding film600may protect the first region I from the plasma treatment400.

The first region I may later form the fin-type patterns F1, F2by the DPT, and the second region II may later form the fin-type patterns F1, F2by the QPT. Accordingly, the second region II may form finer patterns compared to the first region I. As the patterns become finer, the LERs of the patterns may have further increased correlatively with the reliability of the semiconductor device. That is, for the finer patterns, it is more necessary that the LER is enhanced to ensure the reliability of the semiconductor device.

On the contrary, the plasma treatment400may generate defects in the portions other than the patterns for enhancing LER, and may influence the etch rate in the following etching process, which can possibly compromise the uniformity in the fabricating process. Accordingly, the ways to achieve durability and uniformity of the device can be contemplated, by minimizing the use of plasma treatment400for the fine pattern regions, and skipping the plasma treatment400for the rest regions.

Accordingly, in the second region II where the QPT process is applied, the first smooth pattern SP1may be changed into the second smooth pattern SP2by the plasma treatment400, while in the first region I where the DPT process is applied, the shielding film600may be used to prevent the plasma treatment400from progressing.

Referring toFIG. 31, compared to the first smooth pattern SP1in the first region I which is not affected by the plasma treatment400due to the presence of the shielding film600, the first smooth pattern SP1in the second region II may be changed into the second smooth pattern SP2by the plasma treatment400.

Referring toFIG. 32, the shielding film600may be removed from the first region I. In the second region II, the second sacrificial layer230may be patterned with the second smooth pattern SP2as a mask. The second sacrificial layer230may be patterned to form the second sacrificial pattern230P.

The second sacrificial pattern230P may be transferred by the second smooth pattern SP2so that it is formed with similar LER. That is, the more the LER of the second smooth pattern SP2is enhanced, the more the LER of the second sacrificial pattern230P can be enhanced.

The second spacer550may then be formed on both sidewalls of the second sacrificial pattern230P. That is, the first smooth pattern SP1may remain on the first sacrificial layer220in the first region I, while there may be the second sacrificial pattern230P and the second spacer550positioned on the first sacrificial layer220in the second region II. The second spacer550may have an etch selectivity to the second sacrificial pattern230P.

Although not illustrated, trimming process may be added to adjust width of the second spacer550. The width of the second spacer550can determine the interval of the fin-type patterns F1, F2to be formed later.

The LER of the second spacer550may be influenced by the LER of the second sacrificial pattern230P. Accordingly, as the LER of the second sacrificial pattern230P is enhanced, the LER of the second spacer550can be enhanced.

Referring toFIG. 33, the second sacrificial pattern230P may be removed. As described above, the second sacrificial pattern230P has an etch selectivity to the second spacer550. Accordingly, selective removal may be performed so that the second spacer550is not removed. With the removal of the second sacrificial pattern230P, the second spacer550may have the interval corresponding to the width of the second sacrificial pattern230P in the second direction X.

Referring toFIG. 34, the first sacrificial layer20may be patterned with the first smooth pattern SP1as a mask in the first region I, and with the second spacer550as a mask in the second region II. The first sacrificial layer220may be patterned to form the first sacrificial pattern20P. The first sacrificial pattern220P may have a smaller width in the second region II than in the first region I.

The LER of the first sacrificial pattern220P may be influenced by the LERs of the first smooth pattern SP1and the second spacer550. Accordingly, the more the LER of the second spacer550is enhanced, the more the LER of the first sacrificial pattern220P can be enhanced.

Referring toFIG. 35, a first spacer500may be formed on a sidewall of the first sacrificial pattern220P. The material for the first spacer500may include a material with an etch selectivity to the first sacrificial pattern220P. The first spacer500may be formed by patterning the film formed by the atomic layer deposition (ALD). However, example embodiments are not limited to the example given above.

The LER of the first spacer500may be influenced by the LER of the first sacrificial pattern220P. Accordingly, the more the LER of the first sacrificial pattern220P is enhanced, the more the LER of the first spacer500can be enhanced.

Again, trimming process may be added for the first spacer500to adjust width in the second direction. The width of the first spacer500can determine the width of fin-type patterns F1, F2which will be formed later.

Referring toFIG. 36, the first sacrificial pattern220P may be removed. As described above, the first sacrificial pattern220P has an etch selectivity to the first spacer500. Accordingly, a selective removal may be performed so that the first spacer500is not removed. With the removal of the first sacrificial pattern220P, the first spacer500may have the interval corresponding to the width of the first sacrificial pattern220P in the second direction X.

In this situation, the interval of the first spacers500in the first region I may be wider than the interval of the first spacers500in the second region II.

Referring toFIG. 37, the hard mask film210may be patterned with the first spacer500as a mask. That is, the hard mask film210may be selectively removed, leaving only the area overlapped with the first spacer500. As a result, the hard mask film210may be patterned into a hard mask pattern210P in a bar-shaped pattern. The hard mask pattern210P may be positioned at a same or similar interval as the first spacer500.

The LER of the hard mask pattern210P may be influenced by the LER of the first spacer500. Accordingly, the more the LER of the first spacer500is enhanced, the more the LER of the hard mask pattern210P can be enhanced.

In this situation, the interval of the hard mask pattern210P in the first region I may be wider than the interval of the hard mask pattern210P in the second region II.

Referring toFIG. 38, the first spacer500may be removed, and the substrate100may be patterned with the hard mask pattern210P as a mask so that fin-type patterns F1, F2are formed.

The fin-type patterns F1, F2may include a first fin-type pattern F1and a second fin-type pattern F2. The first fin-type pattern F1and the second fin-type pattern F2may respectively correspond to the two first spacers500formed on both sidewalls of the first sacrificial pattern220P. The interval in the second direction X between the first fin-type pattern F1and the second fin-type pattern F2may be same as the width of the first sacrificial pattern220P in the second direction X. Accordingly, the interval between the first fin-type pattern F1and the second fin-type pattern F2in the first region I may be wider than the interval between the first fin-type pattern F1and the second fin-type pattern F2in the second region II.

The LER of the fin-type patterns F1, F2may be influenced by the LER of the hard mask pattern210P. Accordingly, the more the LER of the hard mask pattern210P is enhanced, the more the LER of the fin-type patterns F1, F2can be enhanced. That is, as the LER of the rough pattern RP is enhanced to the LERs of the first smooth pattern SP1and the second smooth pattern SP2, it can be enhanced to the LER of the fin-type patterns F1, F2. In the case of micro pattern forming process such as DPT or QPT process, enhanced LER of the fin-type patterns F1, F2can result in a reduced risk of short between the fin-type patterns F1, F2. As a result, the reliability of the semiconductor device can be enhanced significantly.

Referring toFIG. 39, the hard mask pattern210P may be removed. The removal of the hard mask pattern210P may allow the upper surfaces of the fin-type patterns F1, F2to be exposed.

The fin cut process may be added after forming of the fin-type patterns F1, F2to partially remove the fin-type patterns F1, F2. Next, an interlayer insulating film may be so formed as to partially cover the fin-type patterns F1, F2, and a gate electrode may be formed on the fin-type patterns F1, F2in the second direction X. A transistor may then be formed by forming source/drain on both sides of the gate electrode in the first direction Y.

According to example embodiments of the present disclosure, relatively high LER enhancement can be obtained at a portion such as QPT portion where the micro pattern is formed by performing the ion implantation300and the plasma treatment400together, while the LER enhancement can be obtained by the ion implantation300only (i.e., without plasma treatment400) at a DPT processing portion having less degree of pattern fineness than QPT to thus achieve uniformity of the fabricating process.

FIG. 40is a block diagram of an electronic system comprising a semiconductor device fabricated according to a method for fabricating a semiconductor device according to some example embodiments.

Referring toFIG. 40, an electronic system1100according to some example embodiments may include a controller1110, an input/output (I/O) device1120, a memory device1130, an interface1140and a bus1150. The controller1110, the I/O device1120, the memory device1130and/or the interface1140may be coupled with one another via the bus1150. The bus1150corresponds to a path through which data travels.

The controller1110may include at least one of microprocessor, digital signal process, micro controller and logic devices capable of performing functions similar to those mentioned above. The I/O device1120may include a keypad, a keyboard, a display device and so on. The memory device1130may store data and/or commands. The interface1140may perform a function of transmitting or receiving data to or from communication networks. The interface1140may be wired or wireless. For example, the interface1140may include an antenna or a wired/wireless transceiver.

Although not illustrated, the electronic system1100may additionally include an operation memory configured to enhance operation of the controller1110, such as a high-speed dynamic random-access memory (DRAM) and/or a static random access memory (SRAM).

According to the example embodiments described above, the semiconductor device may be provided within the memory device1130, or provided as a part of the controller1110, the I/O device1120, and so on.

The electronic system1100is applicable to a personal digital assistant (PDA) portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player, a memory card, or almost all electronic products that are capable of transmitting and/or receiving data in wireless environment.