Methods of forming gated devices

Some embodiments include methods of forming gated devices. An upper region of a semiconductor material is patterned into a plurality of walls that extend primarily along a first direction. The walls are spaced from one another by trenches that extend primarily along the first direction. Steps are formed along bottoms of the trenches. Gatelines are formed on the steps and along lower regions of the walls. After the gatelines are formed, the walls are patterned into spaced-apart pillars that have bottom regions below the gatelines. In some embodiments the gated devices may be transistors or thyristors.

TECHNICAL FIELD

Methods of forming gated devices.

BACKGROUND

Memory is one type of integrated circuitry, and is used in computer systems for storing data. Integrated memory is usually fabricated in one or more arrays of individual memory cells. The memory cells are configured to retain or store information in at least two different selectable states. In a binary system, the states are considered as either a “0” or a “1”. In other systems, at least some individual memory cells may be configured to store more than two levels or states of information.

Gated devices may be utilized in memory and other integrated circuitry. Example gated devices are field effect transistors (FETs), gated bipolar junction transistors (gated BJTs) and gated thyristors. The processing utilized for fabrication of gated devices can be complex. Such complexities can be problematic in semiconductor fabrication processes in that they may increase costs, reduce throughput, and create risks of misalignment or other errors. Accordingly, it is desired to develop new methods of fabricating gated devices.

DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS

Some embodiments include new methods of forming gated devices. A couple of example gated devices are shown inFIGS. 1 and 2; withFIG. 1showing a gated transistor10andFIG. 2showing a gated thyristor30.

The transistor10ofFIG. 1comprises a vertical pillar12having three doped regions14,16and18therein (dashed lines are utilized to show approximate boundaries of the doped regions). The vertical pillar12may comprise any suitable semiconductor material; and in some embodiments may comprise, consist essentially of, or consist of monocrystalline silicon. In the shown embodiment, the regions14,16and18are n-type, p-type and n-type, respectively, so that the device10is an NPN device. In other embodiments, the conductivity types of regions14,16and18may be reversed so that the device is a PNP device.

Gate dielectric material20is along sidewalls of pillar12, and electrically conductive gate material22is along the gate dielectric and adjacent doped region16. The gate material22forms gatelines24that may extend in and out of the page relative to the cross-section ofFIG. 1. Although there appear to be two separate gatelines on the opposing sides of pillar12, in practice such gatelines may be electrically connected to one another in a location outside of the page so that they are part of a single continuous gateline. Such gateline may extend only along the two opposing sides of pillar12, or may wrap entirely around the pillar.

The transistor10ofFIG. 1may be a FET, or a gated BJT.

The thyristor30ofFIG. 2comprises a vertical pillar32having four doped regions34,36,38and40therein (dashed lines are utilized to show approximate boundaries of the doped regions). The vertical pillar32may comprise any suitable semiconductor material; and in some embodiments may comprise, consist essentially of, or consist of monocrystalline silicon. In the shown embodiment, the regions34,36,38and40are n-type, p-type, n-type, and p-type, respectively, so that the device30is an NPNP device. In other embodiments, the conductivity types of regions34,36,38and40may be reversed so that the device is a PNPN device.

Gate dielectric material20is along sidewalls of pillar32, and electrically conductive gate material22is along the gate dielectric and adjacent doped region36. The gate material22forms gatelines24that may extend in and out of the page relative to the cross-section ofFIG. 2. Although there appear to be two separate gatelines on the opposing sides of pillar32, in practice such gatelines may be electrically connected to one another in a location outside of the page so that they are part of a single continuous gateline. Such gateline may extend only along the two opposing sides of pillar32, or may wrap entirely around the pillar.

An example embodiment method which may be utilized for forming gated devices of the types described with reference toFIGS. 1 and 2, or other gated devices, is described with reference toFIGS. 3-17.

Referring toFIG. 3, a semiconductor construction50comprises a semiconductor material52having masking materials54and56thereover. The masking materials54and56may comprise silicon dioxide and silicon nitride, respectively; with the silicon dioxide54being a pad oxide to alleviate stresses that could otherwise occur if the silicon nitride56directly contacted semiconductor material52.

The semiconductor material52may comprise, consist essentially of, or consist of monocrystalline silicon, and may be referred to as a semiconductor substrate, or as a portion of a semiconductor substrate. The terms “semiconductive substrate,” “semiconductor construction” and “semiconductor substrate” mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above. In some embodiments, the semiconductor material52may be part of a semiconductor substrate containing one or more materials associated with integrated circuit fabrication. In such embodiments, such materials may correspond to one or more of refractory metal materials, barrier materials, diffusion materials, insulator materials, etc.; and may be part of one or more integrated levels within or below the illustrated material52. In some embodiments, the bottom of material52may comprise a plurality of electrically conductive bitlines, as discussed below with reference toFIGS. 18 and 19.

The material52ofFIG. 3may contain one or more doped regions analogous to the regions discussed above with reference toFIGS. 1 and 2. Alternatively, or additionally, such doped regions may be formed at a processing stage subsequent to that ofFIG. 3.

A patterned mask57is formed over material56, with such mask having masking features58and60. The features58and60are lines extending primarily along a direction of an illustrated axis5. In the shown embodiment, the lines are straight and extend exactly along axis5. In other embodiments, the lines may be curved or wavy, but may still extend primarily along the direction of axis5.

The patterned mask57may comprise any suitable material, such as a photolithographically-patterned photoresist and/or materials patterned utilizing pitch-multiplication methodologies. Accordingly, the lines58and60may have lithographic dimensions in some embodiments, and may have sub-lithographic dimensions in other embodiments.

Referring toFIG. 4, a pattern of lines58and60of masking material57(FIG. 3) is transferred through the masking materials54and56, and into an upper region semiconductor material52; and subsequently masking material57is removed. In some embodiments, such transfer may comprise a first step of transferring the pattern into masking material56to form material56into a patterned hard mask, followed by a transfer of the pattern from the patterned hard mask into semiconductor material52. Such patterned hard mask comprises lines62and64which extend primarily along the direction of axis5. In some embodiments, the patterned hard mask comprising lines62and64may be referred to as a “first patterned mask” to distinguish it from other patterned masks formed in subsequent processing stages. In such embodiments, the first patterned mask may be considered to comprise a series of first lines exemplified by the lines62and64.

The patterned upper region of the semiconductor material52comprises walls66and68which extend primarily along the direction of axis5; and such walls are spaced from one another by a trench70which also extends primarily along the direction of axis5. AlthoughFIGS. 3 and 4show the semiconductor material52patterned into two walls, such walls are exemplary of a large number of walls that may be simultaneously formed within the semiconductor material, and similarly trench70is exemplary of a large number of trenches may be formed utilizing the processing ofFIGS. 3 and 4.FIG. 4shows portions of other trenches69and71on opposing sides of the walls66and68from trench70.

Referring toFIG. 5, a dielectric material72is formed within trenches69-71. In some embodiments, the dielectric material72may be formed to overfill trenches69-71, and subsequently planarization (for instance chemical-mechanical polishing (CMP)) may be utilized to form the shown planarized surface73extending across materials56and72. The dielectric material72may comprise any suitable composition or combination of compositions; and in some embodiments may comprise, consist essentially of, or consist of silicon dioxide.

Referring toFIG. 6, the dielectric material72is recessed within trenches69-71to form material72into steps75-77at the bottoms of trenches69-71, respectively. The steps75-77are ultimately utilized for setting the locations of gatelines (described below with reference toFIG. 8) and may have any suitable heights for placing the gatelines at desired locations. The dielectric material72may be etched back with any suitable process, including, for example, a dry etch process.

Referring toFIG. 7, gate dielectric78and electrically conductive gate material80are formed over the steps75-77within trenches69-71, and over the walls66and68of semiconductor material52.

The gate dielectric78may comprise any suitable composition or combination of compositions; and in some embodiments may comprise, consist essentially of, or consist of silicon dioxide and/or any of various suitable high-k dielectric materials.

The electrically conductive gate material80may comprise any suitable composition or combination of compositions; and in some embodiments may comprise, consist essentially of or consist of one or more of various metals (for instance, titanium, tungsten, etc.), metal-containing compounds (for instance, metal silicides, metal nitrides, metal carbides, etc.), and conductively-doped semiconductor materials (for instance, conductively-doped silicon, conductively-doped germanium, etc.).

Referring toFIG. 8, the electrically conductive gate material80is etched to form electrically conductive gatelines81-84along lower regions of walls66and68; with the gatelines being spaced from the walls by the gate dielectric78. The gatelines extend along the walls, and thus extend primarily along the first direction of axis5. The etch may be any suitable etch, and in some embodiments may be a dry etch.

The gatelines81-84have heights H. Such heights may be tailored by the type and duration of the etch utilized to form the gatelines.

Protective material86is formed over the gatelines; and in the shown embodiment is formed within trenches69-71and over walls66and68. The protective material may protect the gatelines81-84from being exposed to oxidative materials in subsequent processing, and may comprise any suitable composition or combination of compositions. In some embodiments, the protective material86may comprise, consist essentially of, or consist of silicon nitride. The protective material86may be omitted in some embodiments, such as embodiments in which the gatelines will not be exposed to oxidative conditions in the absence of protective material86.

In some embodiments, the protective material86may be considered to narrow trenches69-71.

Referring toFIG. 9, dielectric material88is formed within the narrowed trenches69-71. The dielectric material88may comprise any suitable composition or combination of compositions; and in some embodiments may comprise, consist essentially of, or consist of silicon dioxide. In some embodiments, such silicon dioxide may be formed by a two-step process which comprises: (1) initially depositing low-density silicon oxide; and then (2) subjecting the low-density silicon oxide to oxidizing conditions and a suitable anneal to densify the oxide. In such embodiments, protective material86can protect the gatelines81-84from exposure to the oxidizing conditions utilized during the densification. In some embodiments, dielectric material88may be a composition which can be formed directly against gatelines81-84without exposing such gatelines to oxidizing conditions, and in such embodiments protective material86may be omitted. In some embodiments, the dielectric materials72and88may be referred to as first and second dielectric materials, respectively, to distinguish them from one another.

Referring toFIG. 11, the materials78,86and88are recessed to a level below the patterned masking materials54and56, which opens upper regions of the trenches69-71and exposes upper regions of the walls66and68. In the shown embodiment, the materials78,86and88are recessed to be below a bottom surface of material54by a distance “D”. Such distance may be any suitable distance, and in some embodiments may be from about 10 nm to about 100 nm. The recessing of materials78,86and88may be accomplished with any suitable etch, or combination of etches; and may be done with a protective mask, such as a photoresist mask, (not shown) being formed across material56in some embodiments, and without such protective mask in other embodiments.

Referring toFIG. 12, carbon-containing material90is formed within the upper regions of trenches69-71. Such carbon-containing material may comprise any suitable composition; and in some embodiments may comprise, consist essentially of, or consist of carbon-containing polymer, amorphous carbon and/or transparent carbon. The carbon-containing material may be initially formed to overfill the trenches and extend across upper surfaces of lines62and64, and subsequently a dry etch-back and/or any suitable planarization (for instance, CMP) may be utilized to form the shown surface91extending across materials56and90.

Referring toFIG. 13, patterned masking material92is formed on the surface91. The masking material92is patterned into lines94and96that extend along a second direction that intersects the first direction of the lines62and64. Specifically, the lines62and64extend primarily along a direction of an axis5(as discussed above with reference toFIG. 4) and the lines94and96extend primarily along a direction of an axis7, which is shown to intersect the axis5. In the shown embodiment, the axes5and7are orthogonal to one another. In other embodiments (not shown), the axes may be at other angles relative to one another. The masking material92may be a carbon-containing material, such as, for example, photolithographically-patterned photoresist. The lines94and96may have lithographic dimensions if they are formed of photolithographically-patterned photoresist. Alternatively, the lines94and96may have sub-lithographic dimensions if they are formed utilizing other patterning methods either in addition to, or alternatively to, photolithographic processing; with an example of such other methods being pitch-multiplication methodology.

In some embodiments, the lines94and96may be considered to be comprised by a second patterned mask which extends over the first patterned mask comprising lines62and64, over the walls66and68, and over the dielectric material88. In some embodiments, materials90and92may be considered to be patterned into first and second carbon-containing masks, respectively.

Referring toFIG. 14, materials52,54and56are selectively etched relative to carbon-containing materials90and92to transfer the pattern of lines94and96into the underlying materials52,54and56. Such patterns the walls66and68(FIG. 13) into pillars100and102under line92, and into analogous pillars104and106(not visible inFIG. 14, but shown inFIG. 15) under line96. The pillars100and102are spaced apart from one another by a region comprising dielectric material88. Also, the pillars under line94are spaced from those under line96by spaces108and110(not visible inFIG. 14, but shown inFIG. 15). The semiconductor material52is selectively etched relative to materials72and78(which may both consist of silicon dioxide in some embodiments) during formation of pillars100and102in the shown embodiment.

The etching into material52is conducted for suitable duration and under suitable conditions so that the pillars (for instance, pillars100and102) have bottom regions103below the gatelines81-84, and in the shown embodiment have bottom regions below the steps75-77.

Referring toFIG. 15, the lines94and96(FIG. 14) of masking material92are removed. In embodiments in which material92comprises carbon, and in which material90(FIG. 14) also comprises carbon, the conditions utilized to remove material92may also remove material90, as shown.

Referring toFIG. 16, dielectric material112is formed within spaces between pillars100,102,104and106(FIG. 15). The dielectric material112may comprise any suitable composition or combination of compositions; and in some embodiments may comprise, consist essentially of, or consist of silicon dioxide. The dielectric material112may be initially formed to overfill the spaces between the pillars, and subsequently planarization (for instance, CMP) may be utilized to form the shown planarized surface113extending across materials56and112.

Referring toFIG. 17, additional planarization (or other suitable processing) is conducted to remove materials54and56(FIG. 15) and form the shown planarized surface115extending across the semiconductor material52of pillars100,102,104and106, as well as across material112.

The pillars100,102,104and106may be appropriately doped to be incorporated into gated devices, such as, for example, transistors or thyristors. For instance,FIG. 18shows a cross-sectional view along the line A-A ofFIG. 17of an example embodiment in which the pillars100and102are configured for incorporation into transistors120and122, respectively. The pillars comprise doped regions14,16and18of the types described above with reference toFIG. 1. The doping may occur at any suitable processing stage or combination of stages. For instance, in some embodiments at least some of the doping may occur prior to the processing stage ofFIG. 3. As another example, the doped region18may be formed after removal of materials54and56(FIG. 15) during fabrication of the configuration ofFIG. 17.

The pillars100and102are shown to be electrically connected to a bitline130that extends under the pillars in the shown embodiment (the bitline could be over the pillars100and102in other embodiments). The bitline may comprise any suitable composition or combination of compositions; and in some embodiments may comprise, consist essentially of, or consist of one or more of various metals (for instance, titanium, tungsten, etc.), metal-containing compounds (for instance, metal silicides, metal nitrides, metal carbides, etc.), and conductively-doped semiconductor materials (for instance, conductively-doped silicon, conductively-doped germanium, etc.). For instance, the bitline may comprise a conductively-doped region of semiconductor material52. The bitline may be formed at any suitable processing stage; and in some embodiments may be formed prior to the processing stage ofFIG. 3. The bitline may extend along the direction of axis7(FIG. 17), and accordingly may be orthogonal to the gatelines81-84in some embodiments. The gatelines on opposing sides of a pillar may be paired with one another as discussed above with reference toFIG. 1(i.e., electrically coupled with one another through a connection outside of the page relative to the view ofFIG. 18); and accordingly gatelines83and84may be paired together to form a single wordline132extending in and out of the page relative to the cross-sectional view ofFIG. 18, and similarly the gatelines81and82may be paired together to form a single wordline134extending in and out of the page relative to the cross-sectional view ofFIG. 18. The bitline130may be one of a series of bitlines, and the transistors120and122may be part of an array of transistors which are uniquely addressed through the combination of a bitline and a wordline.

The upper doped regions18of pillars100and102are shown to be electrically connected to devices140and142, respectively. In some embodiments, such devices may be capacitors. In such embodiments, the transistors120and122and the capacitors140and142may be part of a DRAM array. In other embodiments, the devices140and142may be other circuit elements suitable for forming other types of memory arrays and/or logic arrays utilizing transistors120and122.

FIG. 19shows a cross-sectional view along the line A-A ofFIG. 17of an example embodiment in which the pillars100and102are configured for incorporation into gated thyristors150and152, respectively. The pillars comprise doped regions34,36,38and40of the types described above with reference toFIG. 2. The doping may occur at any suitable processing stage or combination of stages. For instance, in some embodiments at least some of the doping may occur prior to the processing stage ofFIG. 3. As another example, the doped region40may be formed after removal of materials54and56(FIG. 15) during fabrication of the configuration ofFIG. 17.

The pillars100and102are shown to be electrically connected to the bitline130that extends under the pillars in the shown embodiment (the bitline could be over the pillars100and102in other embodiments). The gatelines83and84are shown to be paired together to form the wordline132extending in and out of the page relative to the cross-sectional view ofFIG. 18, and similarly the gatelines81and82are shown to be paired together to form the wordline134. Accordingly, the gated thyristors150and152may be part of an array of gated thyristors which are uniquely addressed through the combination of a bitline and a wordline.

The upper doped regions40of pillars100and102are shown to be electrically connected to devices160and162, respectively. The devices160and162may be any circuit elements suitable for forming memory arrays and/or logic arrays utilizing thyristors150and152.

The electronic devices discussed above may be incorporated into electronic systems. Such electronic systems may be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and may include multilayer, multichip modules. The electronic systems may be any of a broad range of systems, such as, for example, clocks, televisions, cell phones, personal computers, automobiles, industrial control systems, aircraft, etc.

The cross-sectional views of the accompanying illustrations only show features within the planes of the cross-sections, and do not show materials behind the planes of the cross-sections in order to simplify the drawings.

When a structure is referred to above as being “on” or “against” another structure, it can be directly on the other structure or intervening structures may also be present. In contrast, when a structure is referred to as being “directly on” or “directly against” another structure, there are no intervening structures present. When a structure is referred to as being “connected” or “coupled” to another structure, it can be directly connected or coupled to the other structure, or intervening structures may be present. In contrast, when a structure is referred to as being “directly connected” or “directly coupled” to another structure, there are no intervening structures present.

For purposes of interpreting this disclosure and the claims that follow, a first material is considered to be “selectively removed” (or “selectively etched’) relative to a second material if the first material is removed at a faster rate than the second material; which can include, but is not limited to, embodiments in which the first material is removed under conditions which are100percent selective for the first material relative to the second material.

Some embodiments include a method of forming gated devices. An upper region of a semiconductor material is patterned into a plurality of walls that extend primarily along a first direction. The walls are spaced from one another by trenches that extend primarily along the first direction. Steps are formed along bottoms of the trenches, and gatelines are formed on the steps and along lower regions of the walls. After the gatelines are formed, the walls are patterned into spaced-apart pillars that have bottom regions below the gatelines.

Some embodiments include a method of forming gated devices. A first patterned mask is formed over a semiconductor material. The first patterned mask comprises a series of first lines extending primarily along a first direction. A pattern is transferred from the first patterned mask into the semiconductor material to form a plurality of walls that extend primarily along the first direction. The walls are spaced from one another by trenches that extend primarily along the first direction. First dielectric material steps are formed along bottoms of the trenches. Gate dielectric is formed along the walls. Gate material is formed over the steps and is spaced from the walls by the gate dielectric. The gate material is etched to form gatelines along lower regions of the walls. Second dielectric material is formed within the trenches and over the gatelines. A second patterned mask is formed over the walls and the second dielectric material. The second patterned mask comprises a series of second lines that extend primarily along a second direction that intersects the first direction. A pattern is transferred from the second patterned mask through the walls to pattern the walls into spaced-apart pillars having bottom regions below the gatelines.

Some embodiments include a method of forming gated devices. A first patterned mask is formed over a monocrystalline silicon substrate. The first patterned mask comprises a series of first lines that extend primarily along a first direction. A pattern is transferred from the first patterned mask into monocrystalline silicon of the substrate to form a plurality of walls that extend primarily along the first direction. The walls are spaced from one another by trenches that extend primarily along the first direction. First dielectric material steps are formed along bottoms of the trenches. Gate dielectric is formed along the walls. Gate material is formed over the steps and is spaced from the walls by the gate dielectric. The gate material is etched to form gatelines along lower regions of the walls. Second dielectric material is formed within the trenches and over the first patterned mask. The second dielectric material is recessed to a level below the first patterned mask to open upper regions of the trenches and expose upper regions of the walls. Carbon-containing material is formed within the upper regions of the trenches. A second patterned mask is formed over the first patterned mask and the carbon-containing material. The second patterned mask comprises a series of second lines that extend primarily along a second direction that intersects the first direction. A pattern is transferred from the second patterned mask through the first patterned mask and the walls to pattern the walls into spaced-apart pillars having bottom regions below the gatelines.