An incremental analog-to-digital converter (ADC) with high accuracy. The incremental ADC has a delta-sigma modulator, performing delta-sigma modulation on an analog input signal to output a quantized signal, and a digital filter, receiving the quantized signal to generate a digital representation of the analog input signal. A loop filter of the delta-sigma modulator has a preset circuit. In the preset circuit, the output terminal of the loop filter is preset rather than being reset during the reset phase of the incremental ADC.

BACKGROUND OF THE INVENTION

Field of the Invention

The present invention relates to incremental analog-to-digital converters (ADCs).

Description of the Related Art

Delta-sigma analog-to-digital converters (ΔΣ ADCs) are used in many applications because of the reduced cost and circuit complexity. Wireless communication systems (e.g., telecommunication systems, television, radio and other media systems, data communication networks, and other systems to convey information between remote points using wireless transmitters and wireless receivers) usually use delta-sigma ADCs.

A delta-sigma ADC includes a delta-sigma modulator and a digital filter. An analog input signal (Ain) is processed by the delta-sigma modulators, and the output of the delta-sigma modulator is a quantized signal which is digitally integrated by the digital filter to generate a digital representation (Dout) of the analog input signal (Ain). In the delta-sigma modulator, a rough estimate of the analog input signal (Ain) is fed back and subtracted from the analog input signal (Ain), and the difference is integrated to compensate for the difference. A delta-sigma ADC may be referred to as an nth-order delta-sigma ADC, wherein n equals the number of cascaded analog integrators within the delta-sigma modulator. The number of order of digital integral provided by the digital filter is preferably the same as the number of analog integrators cascaded in the delta-sigma modulator.

A particular type of delta-sigma ADC is known as an incremental ADC, wherein the analog and digital integrators within the ADC are reset after each analog-to-digital conversion cycle, ready for the next analog-to-digital conversion cycle.

However, the reset procedure on the analog integrators may induce a non-linear problem which considerably affects the accuracy of the incremental ADC.

BRIEF SUMMARY OF THE INVENTION

An incremental analog-to-digital converter (ADC) with high accuracy is introduced in the present invention.

An incremental ADC in accordance with an exemplary embodiment includes a delta-sigma modulator and a digital filter. The delta-sigma modulator performs delta-sigma modulation on an analog input signal to output a quantized signal. The digital filter receives the quantized signal to generate a digital representation of the analog input signal. The delta-sigma modulator includes a quantizer, a digital-to-analog converter, and a loop filter. The quantizer outputs the quantized signal. The digital-to-analog converter is coupled to an output terminal of the quantizer and generates an estimate of the quantized signal. The loop filter operates according to the difference between the analog input signal and the estimate, and the output terminal of the loop filter is coupled to the input terminal of the quantizer. The loop filter has a preset circuit that presets the output terminal of the loop filter during the reset phase of the incremental analog-to-digital converter.

In an exemplary embodiment, the loop filter comprises a plurality of analog integrators cascaded in a series. The preset circuit includes a plurality of preset elements corresponding to the plurality of analog integrators one by one. Each preset element and a feedback capacitor of the corresponding analog integrator are connected in parallel during the reset phase of the incremental analog-to-digital converter.

In an exemplary embodiment, the loop filter comprises a first analog integrator. The first analog integrator has a first operational amplifier and a first feedback capacitor coupled between an input terminal and an output terminal of the first operational amplifier. The preset circuit comprises a first switch and a first preset element connected in series between the input terminal and the output terminal of the first operational amplifier. The first switch is closed during the reset phase of the incremental analog-to-digital converter. In an exemplary embodiment, the loop filter further comprises a second analog integrator coupled between the first analog integrator and the quantizer. The second analog integrator has a second operational amplifier and a second feedback capacitor coupled between the input terminal and the output terminal of the second operational amplifier. The preset circuit further comprises a second switch and a second preset element connected in series between the input terminal and the output terminal of the second operational amplifier. The second switch is closed during the reset phase of the incremental analog-to-digital converter. In an exemplary embodiment, the second analog integrator comprises an input resistor coupled between the output terminal of the first operational amplifier and the input terminal of the second operational amplifier. The preset circuit further comprises a third switch and a third preset element connected in series between the output terminal of the first operational amplifier and the input terminal of the second operational amplifier. The third switch is closed during the reset phase of the incremental analog-to-digital converter.

In an exemplary embodiment, the loop filter comprises a plurality of analog integrators cascaded in a series. The preset circuit couples the analog input signal to output terminals of the analog integrators during the reset phase of the incremental analog-to-digital converter. In an exemplary embodiment, the analog integrators are reset during the reset phase of the incremental analog-to-digital converter.

In an exemplary embodiment, the loop filter comprises a first analog integrator. The preset circuit comprises a first switch and a first preset element connected in series. The first switch is closed during the reset phase of the incremental analog-to-digital converter. The analog input signal is coupled to an output terminal of the first analog integrator by the first preset element when the first switch is closed. In an exemplary embodiment, the loop filter further comprises a second analog integrator coupled between the first analog integrator and the quantizer. The preset circuit comprises a second switch and a second preset element connected in series between the output terminal of the first analog integrator and an output terminal of the second analog integrator. The second switch is closed during the reset phase of the incremental analog-to-digital converter. In an exemplary embodiment, the first and second analog integrators are reset during the reset phase of the incremental analog-to-digital converter.

In an exemplary embodiment, the digital filter comprises a digital integrator that is reset during the reset phase of the incremental analog-to-digital converter. In an exemplary embodiment, the quantizer is reset during the reset phase of the incremental analog-to-digital converter.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1is a block diagram depicting an incremental analog-to-digital converter (ADC)100in accordance with an exemplary embodiment of the present invention. The incremental ADC100includes a delta-sigma modulator102, a digital filter104and a reset signal generator106. An analog input signal Ain is processed by the delta-sigma modulator102, and the output of the delta-sigma modulator102is a quantized signal Do which is digitally integrated by the digital filter104to form a digital representation Dout of the analog input signal Ain.

The delta-sigma modulator102includes a loop filter112(having L (>=1) analog integrators), a quantizer114, a digital-to-analog converter (DAC)116, and an adder118. The DAC116outputs a signal120(a rough estimate of the input signal Ain) to be subtracted from the input signal Ain by the adder118. The difference122is processed by the loop filter112and then is quantized by the quantizer114as the quantized signal Do. Not only being fed to the digital filter104, the quantized signal Do is also fed back as the input of the DAC116. In an analog-to-digital conversion cycle, the difference122is compensated for, and the integral (calculated by the loop filter112) of the difference122reaches a stable value. The quantized signal Do that is gradually stabilized is digitally integrated by the digital filter104to generate a digital representation Dout of the analog input signal Ain.

As shown, the reset signal generator106generates a reset signal RST to reset the incremental ADC100during a reset phase after each analog-to-digital conversion cycle. According to the reset signal RST, the digital integrators within the digital filter104are reset. Specifically, the quantizer114is also reset according to the reset signal RST to output a reset value (e.g., Do=0) to the digital filter104to completely clean the capacitors of the digital integrators within the digital filter104. The reset phase makes a one-to-one mapping between the analog input signal Ain and digital representation Dout. To prevent the reset value (e.g., Do=0) from the quantizer114from being fed into the next analog-to-digital conversion cycle, a preset circuit is introduced for the output terminal of the loop filter112. The preset circuit presets the output terminal124of the loop filter112during the reset phase of the incremental ADC100. At the beginning of each analog-to-digital conversion cycle, the signal transmitted from output terminal of the loop filter112to the quantizer114is a preset value (preset during the reset phase) rather than zero. The non-zero preset value is fed back the loop filter112through the quantizer114, the DAC116and the adder118, which effectively limit the difference122. The analog integrators within the loop filter112, therefore, all operate within their linear regions. The non-linear errors due to a dramatic variation of the difference122at the beginning of each analog-to-digital conversion cycle are reduced.

FIG. 2shows the waveform of the reset signal RST. The reset signal generator106may generate the reset signal RST according to a clock signal CLK. As shown, between the analog-to-digital conversion cycles, a reset phase is required. During the reset phase of the incremental ADC100, the output terminal of the loop filter112is preset.

FIG. 3depicts an incremental ADC300in accordance with an exemplary embodiment of the present invention, which is a continuous time ADC.

As shown inFIG. 3, the loop filter112ofFIG. 1may include a first stage circuit302and a second stage circuit304as shown inFIG. 3, wherein each stage circuit relates to an integral calculation. An integral output INT1of the first stage circuit302and an integral output INT2of the second stage circuit304are preset (rather than being cleaned to zero) during the reset phase of the incremental ADC300.

In the first stage circuit302, there is an operational amplifier op1, a feedback capacitor C1, a preset element PE1, and a switch SW1. The difference122is coupled to an input terminal ‘-’ of the operational amplifier op1. The integral output INT1is generated at an output terminal of the operational amplifier op1. The feedback capacitor C1is coupled between the input terminal ‘-’ and the output terminal of the operational amplifier op1. The preset element PE1and the switch SW1are connected in series between the input terminal ‘-’ and the output terminal of the operational amplifier op1. During the reset phase of the incremental ADC300, the switch SW1is closed by the reset signal RST and thereby the preset element PE1is connected in parallel with the feedback capacitor C1. The feedback capacitor C1is not being completely cleaned, so that the integral output INT1is preset rather than being cleaned to zero during the reset phase of the incremental ADC300.

In the second stage circuit304, there is an operational amplifier op2, a feedback capacitor C2, an input resistor Rin, a preset element PE2, and a switch SW2. The integral output INT1from the first stage circuit302is coupled to an input terminal ‘-’ of the operational amplifier op2through the input resistor Rin. The integral output INT2is generated at an output terminal of the operational amplifier op2. The feedback capacitor C2is coupled between the input terminal ‘-’ and the output terminal of the operational amplifier op2. The preset element PE2and the switch SW2are connected in series between the input terminal ‘-’ and the output terminal of the operational amplifier op2. During the reset phase of the incremental ADC300, the switch SW2is closed by the reset signal RST and thereby the preset element PE2is connected in parallel with the feedback capacitor C2. The feedback capacitor C2is not being completely cleaned, so that the integral output INT2is preset rather than being reset to zero during the reset phase of the incremental ADC300.

InFIG. 3, the second stage circuit304further has a preset element PE3and a switch SW3. The preset element PE3and the switch SW3are connected in series between the output terminal of the operational amplifier op1and the input terminal ‘-’ of the operational amplifier op2. During the reset phase of the incremental ADC300, the switch SW3is closed by the reset signal RST and thereby the preset element PE3is connected in parallel with the input resistor Rin. The preset integral output INT1is coupled to the second stage circuit304via the preset elements PE3and the input resistor Rin which are connected in parallel. The preset element PE3and a switch SW3are optional.

InFIG. 3, the preset elements PE1, PE2and PE3are resistors but not limited thereto. The preset elements PE1, PE2and PE3may be buffers, or any active or passive components.

The switches SW1, SW2and SW3and the preset elements PE1, PE2and PE3form the preset circuit that presets the output terminal124of the loop filter112during the reset phase of the incremental ADC.

FIG. 4shows the transient waveforms of the integral outputs INT1and INT2and the quantized signal Do. The solid lines402,404and406are the transient waveforms of the integral output INT1, the integral output INT2and the quantized signal Do of the incremental ADC100. The dotted lines408,410and412are the transient waveforms of signals of a conventional incremental ADC in which an output terminal of a loop filter is also reset during the reset phase of ADC. Referring to the solid lines402and404in the present invention, the integral outputs INT1and INT2are preset (during the time interval400, corresponding to the reset phase of ADC) rather than being reset and the shorter settling time (in comparison with the dotted lines408and410) is shown. In comparison with the dotted line412, the quantized signal Do shown by the solid line406is quickly raised to the desired value because of the preset integral outputs INT1and INT2. The transient response of the incremental ADC is obviously improved in the present invention.

FIG. 5depicts an incremental ADC500in accordance with an exemplary embodiment of the present invention, which is a discrete time ADC.

As shown inFIG. 5, the loop filter112ofFIG. 1may include two cascaded switched-capacitor integrators502and504, a switch SWa, a preset element PEa, a switch SWb and a preset element PEb. The switch SWa and the preset element PEa are connected in series. The switch SWb and the preset element PEb are connected in series. The switched-capacitor integrator502outputs an integral output INTL The switched-capacitor integrator504outputs an integral output INT2. When the switches SWa and SWb are closed according to the reset signal RST of the incremental ADC500, the analog input signal Ain is coupled to the integral output INT1through the preset element PEa, and the integral output INT1is coupled to the integral output INT2through the preset element PEb. Thus, when entering the following analog-to-digital conversion cycle, the quantized signal Do is not zero, which effectively limit the difference122. The switched-capacitor integrators502and504, therefore, all operate within their linear region. The non-linear errors due to a dramatic variation of the difference122at the beginning of each analog-to-digital conversion cycle are reduced.

In the example shown inFIG. 5, the switched-capacitor integrators502and504are resettable. According to the reset signal RST, the capacitors within the switched-capacitor integrators502and504are cleaned. The preset status of the integral outputs INT1and INT2are achieved by the closed switches SWa and SWb and the preset elements PEa and PEb. The preset elements PEa and PEb may be resistors, buffers, or any active or passive components.

The switches SWa and SWb and the preset elements Pea and PEb form the preset circuit that presets the output terminal124of the loop filter112during the reset phase of the incremental ADC.

In another exemplary embodiment, the switched-capacitor integrators502and504vmay be replaced by RC integrators.

InFIG. 3andFIG. 5, only two cascaded integrators are shown. However, the number of cascaded integrators within the loop filter112is not limited to two. Any circuit design presetting the output terminal124of the loop filter112during the reset phase of the whole ADC should be regarded within the scope of the present invention.

Based on the concept ofFIG. 3, the loop filter112may comprise a plurality of analog integrators cascaded in a series, and the preset circuit of the loop filter112includes a plurality of preset elements (PE #) corresponding to the plurality of analog integrators one by one. Each preset element and a feedback capacitor of the corresponding analog integrator are connected in parallel during the reset phase of the incremental analog-to-digital converter.

Based on the concept ofFIG. 5, the loop filter112may comprise a plurality of analog integrators cascaded in a series, and the preset circuit of the loop filter112couples the analog input signal to output terminals of the analog integrators during the reset phase of the incremental analog-to-digital converter.