Non-volatile memory systems with multi-write direction memory units

Non-volatile memory systems with multi-write direction memory units are disclosed. In one implementation an apparatus comprises a non-volatile memory and a controller in communication with the non-volatile memory. The controller is configured to select an empty memory block of the non-volatile memory for the storage of data; examine an identifier associated with the memory block to determine a write direction for the storage of data; and write data to the memory block beginning with an initial word line of the memory block or a last word line of the memory block dependent on the write direction. The controller is further configured to erase the memory unit and, in response to erasing the memory unit, modify the identifier to change the write direction for a subsequent write of data to the memory block.

BACKGROUND

In conventional non-volatile memory systems such as flash memory systems, controllers program rows of a NAND array in a prescribed sequential order beginning with a row along an initial word line that is closest to an end of memory cell strings connected to a ground or another common potential. The controller then programs a row of memory cells along a next sequential word line moving away from the initial word line, and so on, through a memory block.

As the controller programs the word lines closest to an end of memory cell strings connected to a ground or another common potential, voltage disturbances accumulate on the unprogrammed word lines farthest from the initial word line. Generally, during a programming operation, as the controller deselects word lines, some voltage may still be applied to the deselected word lines. For erased word lines, the voltage may be high enough to cause disturbance to memory cells, even though the voltage may not be high enough to trigger actual programming of the memory cells. Word lines that the controller has already programmed experience much less voltage disturbance because the potential difference is lower due to some charge being present on the floating gate associated with the word line. Because the word lines furthest from an initially programmed word line often remain erased often during programming, the word lines furthest from the initially programmed word line often accumulate the most voltage disturbance. These accumulate of voltage disturbances result in memory cell degradation and affect the perform of the memory system during any activity. This accumulation of voltage can cause word lines to fail or increase a rate at which memory cells break down, thereby affecting an endurance of the memory system.

DETAILED DESCRIPTION OF THE DRAWINGS

The present disclosure is directed to non-volatile memory systems with multi-write direction memory units. As discussed above, when a controller of a non-volatile memory system writes data to an empty memory unit, such as a memory block, beginning with an initial word line of the memory unit, disturbances are generated at word lines at the end of the memory unit. These disturbances accumulate over time on word lines at the end of the memory unit as the controller repeatedly writes data to the memory unit. As the disturbances accumulate, the overall disturbance on the word lines at the end of the memory unit increases, which can result in the word lines at the end of the memory unit failing earlier than the word lines at the beginning of the memory unit.

In the non-volatile memory systems described in present application, a controller of the non-volatile memory system is able to reverse a direction with which the controller writes data to a memory unit. For example, the controller may write data to a memory unit in a forward direction beginning with an initial word line of the memory unit and then a next sequential word line of the memory unit. During the writes in a forward direction, disturbances may accumulate on word lines at an end of the memory unit.

After the memory unit is erased, the controller may reverse the write direction for a next data write to the memory unit. Accordingly, the controller may write data to the memory unit in a reverse direction beginning with a last word line of the memory unit and then a previous sequential word line of the memory unit. During the writes in a reverse direction, disturbances may accumulate on word lines at a beginning of the memory unit.

It will be appreciated that because the controller reverses the data write directions, over time the disturbances are distributed across the word lines at the beginning of the memory unit and the word lines at the end of the memory unit. Therefore, by periodically reversing a write direction, an overall disturbance on the word lines at the end of the memory unit are less over time when compared to the overall disturbances that typically accumulate on word lines at an end of a memory block when controllers only write data to a memory block in a forward direction. The distribution of disturbances across the word lines at the beginning and end of the memory unit reduces a maximum disturbance that will accumulate on any one word line, thereby increasing an endurance of the memory unit.

In one embodiment, a method is disclosed. The elements of the method occur in a controller of a non-volatile memory system. In the method, an empty memory unit of a non-volatile memory of the non-volatile memory system is selected for the storage of data. An identifier associated with the memory unit is examined to determine a write direction for the storage of data in the memory unit. Data is then written to the memory unit in the write direction.

In another embodiment, an apparatus disclosed. The apparatus comprises a non-volatile memory and a controller in communication with the processing circuitry. The controller is configured to select an empty memory block of a the non-volatile memory for the storage of data; examine a counter associated with the memory block to determine a write direction for the storage of data; and write data to the memory block beginning with an initial word line of the memory block or a last word line of the memory block dependent on the write direction.

In yet another embodiment, another method is disclosed. The elements of the method occur in a controller of a non-volatile memory system. In the method, a determination is made of whether to write data to a memory unit of a non-volatile memory of the non-volatile memory system in a forward direction or a reverse direction based on a previous write direction with which the controller wrote data to the memory unit. Data is then written to the memory unit beginning with one of an initial word line or a last word line associated with the memory unit based on the determination of whether to write data to the memory unit in the forward direction or the reverse direction.

Other embodiments and implementations are possible, and each of the embodiments can be used alone or together in combination. Accordingly, various embodiments and implementations will be described with reference to the attached drawings.

Memory systems suitable for use in implementing aspects of these embodiments are shown inFIGS. 1A-1C.FIG. 1Ais a block diagram illustrating a non-volatile memory system according to an embodiment of the subject matter described herein. Referring toFIG. 1A, non-volatile memory system100includes a controller102and non-volatile memory that may be made up of one or more non-volatile memory die104. As used herein, the term die refers to the collection of non-volatile memory cells, and associated circuitry for managing the physical operation of those non-volatile memory cells, that are formed on a single semiconductor substrate. Controller102interfaces with a host system and transmits command sequences for read, program, and erase operations to non-volatile memory die104.

Non-volatile memory die104may include any suitable non-volatile storage medium, including NAND flash memory cells and/or NOR flash memory cells. The memory cells can take the form of solid-state (e.g., flash) memory cells and can be one-time programmable, few-time programmable, or many-time programmable. The memory cells can also be single-level cells (SLC), multiple-level cells (MLC), triple-level cells (TLC), or use other memory technologies, now known or later developed. Also, the memory cells can be arranged in a two-dimensional or three-dimensional fashion.

The interface between controller102and non-volatile memory die104may be any suitable flash interface, such as Toggle Mode 200, 400, or 800. In one embodiment, memory system100may be a card based system, such as a secure digital (SD) or a micro secure digital (micro-SD) card. In an alternate embodiment, memory system100may be part of an embedded memory system.

Although, in the example illustrated inFIG. 1A, non-volatile memory system100includes a single channel between controller102and non-volatile memory die104, the subject matter described herein is not limited to having a single memory channel. For example, in some NAND memory system architectures, 2, 4, 8 or more NAND channels may exist between the controller and the NAND memory device, depending on controller capabilities. In any of the embodiments described herein, more than a single channel may exist between the controller and the memory die, even if a single channel is shown in the drawings.

FIG. 1Billustrates a storage module200that includes plural non-volatile memory systems100. As such, storage module200may include a storage controller202that interfaces with a host and with storage system204, which includes a plurality of non-volatile memory systems100. The interface between storage controller202and non-volatile memory systems100may be a bus interface, such as a serial advanced technology attachment (SATA) or peripheral component interface express (PCIe) interface. Storage module200, in one embodiment, may be a solid state drive (SSD), such as found in portable computing devices, such as laptop computers, and tablet computers.

FIG. 1Cis a block diagram illustrating a hierarchical storage system. A hierarchical storage system250includes a plurality of storage controllers202, each of which controls a respective storage system204. Host systems252may access memories within the storage system via a bus interface. In one embodiment, the bus interface may be a fiber channel over Ethernet (FCoE) interface. In one embodiment, the system illustrated inFIG. 1Cmay be a rack mountable mass storage system that is accessible by multiple host computers, such as would be found in a data center or other location where mass storage is needed.

FIG. 2Ais a block diagram illustrating exemplary components of controller102in more detail. Controller102includes a front end module108that interfaces with a host, a back end module110that interfaces with the one or more non-volatile memory die104, and various other modules that perform functions which will now be described in detail. A module may take the form of a packaged functional hardware unit designed for use with other components, a portion of a program code (e.g., software or firmware) executable by a (micro)processor or processing circuitry that usually performs a particular function of related functions, or a self-contained hardware or software component that interfaces with a larger system, for example.

Modules of the controller102may include a write direction module112that is present on the same die as the controller102. As explained in more detail below in conjunction withFIGS. 7 and 8, the memory write direction module112may perform operations that direct the controller102to change a direction with which data is written to a memory unit such as a memory block. In some implementations, the write direction module112may change the write direction between a forward direction and a reverse direction.

In some implementations, when writing data to a memory unit in a forward direction, the controller102writes data to a memory unit beginning with a first word line of the memory unit and may continue writing to the memory unit utilizing a next sequential word line in a direction towards a last word line of the memory unit. When writing data to the memory unit in a reverse direction, the controller102writes data to the memory unit beginning with the last word line of the memory unit and may continue writing to the memory unit utilizing a next sequential word line in a direction towards the first word line.

Referring again to modules of the controller102, a buffer manager/bus controller114manages buffers in random access memory (RAM)116and controls the internal bus arbitration of controller102. A read only memory (ROM)118stores system boot code. Although illustrated inFIG. 2Aas located separately from the controller102, in other embodiments one or both of the RAM116and ROM118may be located within the controller. In yet other embodiments, portions of RAM and ROM may be located both within the controller102and outside the controller. Further, in some implementations, the controller102, RAM116, and ROM118may be located on separate semiconductor die.

Front end module108includes a host interface120and a physical layer interface (PHY)122that provide the electrical interface with the host or next level storage controller. The choice of the type of host interface120can depend on the type of memory being used. Examples of host interfaces120include, but are not limited to, SATA, SATA Express, SAS, Fibre Channel, USB, PCIe, and NVMe. The host interface120typically facilitates transfer for data, control signals, and timing signals.

Additional components of system100illustrated inFIG. 2Ainclude media management layer138to perform wear leveling of memory cells of non-volatile memory die104. System100also includes other discrete components140, such as external electrical interfaces, external RAM, resistors, capacitors, or other components that may interface with controller102. In alternative embodiments, one or more of the physical layer interface122, RAID module128, media management layer138and buffer management/bus controller114are optional components that are not necessary in the controller102.

FIG. 2Bis a block diagram illustrating exemplary components of non-volatile memory die104in more detail. Non-volatile memory die104includes peripheral circuitry141and non-volatile memory array142. Non-volatile memory array142includes the non-volatile memory cells used to store data. The non-volatile memory cells may be any suitable non-volatile memory cells, including NAND flash memory cells and/or NOR flash memory cells in a two dimensional and/or three dimensional configuration. Peripheral circuitry141includes a state machine152that provides status information to controller102. Non-volatile memory die104further includes a data cache156that caches data.

Each non-volatile memory die104may contain an array of memory cells organized into multiple planes. An example NAND array is illustrated inFIG. 3A.

While a large number of global bit lines are provided in a NAND array, only four such lines302-308are shown inFIG. 3Afor simplicity of explanation. A number of series connected memory cell strings310-324are connected between one of these bit lines and a reference potential. Using the memory cell string314as representative, a plurality of charge storage memory cells326-332are connected in series with select transistors334and336at either end of the string. When the select transistors of a string are rendered conductive, the string is connected between its bit line and the reference potential. One memory cell within that string is then programmed or read at a time.

Word lines338-344ofFIG. 3Aindividually extend across the charge storage element of one memory cell in each of a number of strings of memory cells, and gates346and350control the states of the select transistors at each end of the strings. The memory cell strings that share common word and control gate lines338-350are made to form a block352of memory cells that are erased together. This block of cells contains the minimum number of cells that are physically erasable at one time. One row of memory cells, those along one of the word lines338-344, are programmed at a time.

Conventionally, the rows of a NAND array are programmed in a prescribed sequential order, in this case beginning with the row along the word line344closest to the end of the strings connected to ground or another common potential. The row of memory cells along the word line342is programmed next, and so on, throughout the block352.

A second block354is similar, its strings of memory cells being connected to the same global bit lines as the strings in the first block352but having a different set of word and control gate lines. The word and control gate lines are driven to their proper operating voltages by row control circuits. If there is more than one plane in the system, one memory architecture uses common word lines extending between them. There can alternatively be more than two planes that share common word lines. In other memory architectures, the word lines of individual planes are separately driven.

While the example NAND array illustrated inFIG. 3Ahas been used to describe a process for writing data to a memory block in a forward direction, to write data to a memory block in either a forward direction or a reverse direction, a controller may change which end of the memory cell strings is connected is connected a ground or other common potential.

FIG. 3Billustrates an example NAND array and circuitry that is able to write data to a memory block358in a forward direction and a reverse direction. As shown, a drain bus360and a source bus362are in communication with a number of global bit lines364-0,364-1, . . .364-nassociated with the memory block358.

A bus switch366is in communication with the drain bus360and the source bus362. The bus switch366is additionally in communication with a set of control logic and amplifiers368and a common potential bus370. In some implementations, the drain bus360, source bus362, bus switch366, control logic and amplifiers368, and the common potential bus370are part of the NAND memory and present on a die of the NAND.

The bus switch is configured to operate in at least two modes to apply the control logic and amps268or the common potential bus370to the drain bus360and the source bus362.

In a first mode, the bus switch366applies the set of control logic and amplifiers368to the drain bus260and applies the common potential bus370to the source bus362. When operating in the first mode, data is written to the memory block in a forward direction similar to that described above in conjunction withFIG. 3A. The controller writes data to the memory block358beginning at a first word line372-0, and may continue writing data in a forward direction at a next subsequent word line372-1.

In a second mode, the bus switch366applies the set of control logic and amplifiers368to the source bus262and applies the common potential bus370to the drain bus360. By changing which of the control logic and amps368and the common potential bus370are applied to the drain bus360and the source bus362from the first mode, the controller is able to change the write direction to write data to the memory block358in a reverse direction. When operating in the second mode, the controller initially writes data to the memory block358beginning at a last word line372-n, and may continue writing data in a reverse direction at a previous sequential word line372-n−1.

The write detection module374of the controller is in communication with the bus switch366and may control whether the bus switch366applies the control logic and amplifiers368or the common potential bus370to the drain bus360or the source bus362. In one implementation, the write detection module374may instruct the bus switch366through the use of a control bit.

As shown inFIG. 3B, the write detection module374may use a control bit value of zero to instruct the bus switch366to connect the control logic and amplifiers368to the drain bus360and to connect the common potential bus370to the source bus362. Further, the write detection module374may use a control bit value of one to instruct the bus switch366to connect the control logic and amplifiers368to the source bus362and to connect the common potential bus370to the drain bus360.

The memory cells may be operated to store two levels of charge so that a single bit of data is stored in each cell. This is typically referred to as a binary or single level cell (SLC) memory. Alternatively, the memory cells may be operated to store more than two detectable levels of charge in each charge storage element or region, thereby to store more than one bit of data in each. This latter configuration is referred to as multi level cell (MLC) memory. Both types of memory cells may be used in a memory. For example, binary flash memory may be used for caching data and MLC memory may be used for longer term storage. The charge storage elements of the memory cells are most commonly conductive floating gates but may alternatively be non-conductive dielectric charge trapping material.

In implementations of MLC memory operated to store two bits of data in each memory cell, each memory cell is configured to store four levels of charge corresponding to values of “11,” “01,” “10,” and “00.” Each bit of the two bits of data may represent a page bit of a lower page or a page bit of an upper page, where the lower page and upper page span across a series of memory cells sharing a common word line. Typically, the less significant bit of the two bits of data represents a page bit of a lower page and the more significant bit of the two bits of data represents a page bit of an upper page.

FIG. 4illustrates one implementation of the four charge levels used to represent two bits of data in a memory cell. A value of “11” corresponds to an un-programmed state of the memory cell. When programming pulses are applied to the memory cell to program a page bit of the lower page, the level of charge is increased to represent a value of “10” corresponding to a programmed state of the page bit of the lower page.

For a page bit of an upper page, when the page bit of the lower page is programmed (a value of “10”), programming pulses are applied to the memory cell for the page bit of the upper page to increase the level of charge to correspond to a value of “00” or “10” depending on the desired value of the page bit of the upper page. However, if the page bit of the lower page is not programmed such that the memory cell is in an un-programmed state (a value of “11”), applying programming pulses to the memory cell to program the page bit of the upper page increases the level of charge to represent a value of “01” corresponding to a programmed state of the page bit of the upper page.

FIG. 5conceptually illustrates a multiple plane arrangement showing four planes502-508of memory cells. These planes502-508may be on a single die, on two die (two of the planes on each die) or on four separate die. Of course, other numbers of planes, such as 1, 2, 8, 16 or more may exist in each die of a system. The planes are individually divided into blocks of memory cells shown inFIG. 5by rectangles, such as blocks510,512,514and516, located in respective planes502-508. There can be dozens or hundreds or thousands or more of blocks in each plane.

As mentioned above, a block of memory cells is the unit of erase, the smallest number of memory cells that are physically erasable together. Some non-volatile memory systems, for increased parallelism, operate the blocks in larger metablock units. However, other memory systems may utilize asynchronous memory die formations rather than operating in larger metablock units.

In non-volatile memory systems utilizing metablock units, one block from each plane is logically linked together to form the metablock. The four blocks510-516are shown to form one metablock518. All of the cells within a metablock are typically erased together. The blocks used to form a metablock need not be restricted to the same relative locations within their respective planes, as is shown in a second metablock520made up of blocks522-528. Although it is usually preferable to extend the metablocks across all of the planes, for high system performance, the non-volatile memory systems can be operated with the ability to dynamically form metablocks of any or all of one, two or three blocks in different planes. This allows the size of the metablock to be more closely matched with the amount of data available for storage in one programming operation.

The individual blocks are in turn divided for operational purposes into pages of memory cells, as illustrated inFIG. 6. The memory cells of each of the blocks510-516, for example, are each divided into eight pages P0-P7. Alternatively, there may be 16, 32, 64 or more pages of memory cells within each block. The page is the unit of data programming and reading within a block, containing the minimum amount of data that are programmed or read at one time. However, in order to increase the memory system operational parallelism, such pages within two or more blocks may be logically linked into metapages. A metapage628is illustrated inFIG. 6, being formed of one physical page from each of the four blocks510-516. The metapage628, for example, includes the page P2in each of the four blocks but the pages of a metapage need not necessarily have the same relative position within each of the blocks.

As mentioned above, when a controller of a non-volatile memory system writes data to an empty memory unit, such as a memory block, beginning with an initial word line of the memory unit, voltage disturbances are generated at word lines at the end of the memory unit. These disturbances accumulate over time on word lines at the end of the memory unit as the controller repeatedly writes data to the memory unit. As the disturbances accumulate, the overall disturbance on the word lines at the end of the memory unit increases, which can result in the word lines at the end of the memory unit failing earlier than the word lines at the beginning of the memory unit.

In the non-volatile memory systems described in the present application, a controller of the non-volatile memory system is able to reverse a direction with which the controller writes data to a memory unit. For example, the controller may write data to a memory unit in a forward direction beginning with an initial word line of the memory unit. Then, after the memory unit is erased, the controller may then write data to the memory unit in a reverse direction beginning with a last word line of the memory unit. It will be appreciated that because the controller reverses the data write direction, over time the disturbances are distributed across the word lines at the beginning of the memory unit and the word lines at the end of the memory unit.

FIG. 7is a flow chart of one implementation of a method of writing data to multi-write direction memory units. In the method described below, the memory unit is a memory block. However, other memory units may be used.

At step702, a controller of a non-volatile storage system selects a memory block of a non-volatile memory of the non-volatile storage system for the storage of data. In some implementations the controller may select an empty memory block from a free block list of the non-volatile memory system. As known in the art, a free block list is a listing of memory blocks at the non-volatile memory system that are available for the storage of data.

At step704, a write direction module of the controller examines an identifier associated with the memory block to determine a write direction for the memory block. The identifier may be a parity bit of a program/erase cycle counter for the memory block (also known as a hot counter), a counter not directly related to a program/erase cycle count of the memory block, or any other type of identifier that informs the write direction module a write direction that the controller previously wrote to the memory block and/or a write direction that the controller should presently write data to the memory block.

For example, when the identifier is a parity bit of a program/erase cycle counter, the write direction module may determine that the controller should write data to the memory block in a forward direction when the value of the parity bit is zero and that the controller should write to the memory block in a reverse direction when the value of the parity bit is one.

Similarly, when the identifier is a counter, the write direction may determine that the controller should write data to the memory block in a forward direction when the value of the counter is an even number and that the controller should write to the memory block in a reverse direction when the value of the counter is an odd number. As explained in more detail below, the counter may be incremented each time the memory block is erased.

Other arrangements could be implemented with a counter such that the write direction is changed after the counter is incremented a defined number of times. For example, the write direction module could reverse direction of data writes after the counter is incremented five times (corresponding to the memory block being erased five times). Therefore, the controller would write to data to the memory block five times in a forward direction, then five times in a reverse, and then change back to writing data to the memory block in a forward direction.

At step706, the write direction module selects a starting word line for the data write based on the determination at step704. When the write direction module determines that the controller should write data to the memory block in a forward direction, the write direction module selects an initial word line of the memory block to begin the data write. Alternatively, when the write direction module determine that the controller should write data to the memory block in a reverse direction, the write direction module selects a last word line of the memory block to begin the data write.

As discussed above in conjunction withFIGS. 3A and 3B, conventional non-volatile memory systems program a memory block only in a forward direction starting with an initial word line of the memory block and continuing to program one or more word lines in a sequential order towards a last word line of the memory block. In the present application, in addition to programming a memory block in a forward direction, a controller is also able to program a memory block in a reverse direction. In the reverse direction, the controller begins with programming a last word line of the memory block and continues to program one or more word lines in a sequential order towards the first word line.

At step708, the controller writes data to the selected word line. At step710, the controller determines whether the memory block is full after the data write at step708or whether the data write is complete. When the memory block is not full and the data write is not complete, the controller selects a next word line of the memory block for the storage of data at step712.

When writing data in a forward direction, the controller may select a next sequential word line moving away from the initial word line and towards the last word line for the storage of data. Alternatively, when writing data in a reverse direction, the controller may select a next sequential word line moving away from the last word line and towards the initial word line for the storage of data.

The process is repeated beginning at step708until the memory block is full or the memory block is not yet full but the controller has completed the memory write.

The controller continues utilizing the memory block and writing data to the memory block until the controller determines to erase the memory block. It will be appreciated that the write direction module should not shift a write direction for the memory block until the memory block is erased for reuse.

FIG. 8is a flow chart of one method for erasing a multi-direction memory unit. In the method described below, the memory unit is a memory block. However, other memory units may be used.

At step802, the controller determines a need to reuse the memory block. For example, the controller may determine to reuse the memory block because the memory block no longer contains valid data, because data is being moved from the memory block, and/or during a garbage collection operation on the memory block.

At step804, the controller erases the memory block, and at step806, the write direction module of the controller adjusts the identifier associated with the memory block that informs the write direction module a write direction that the controller previously wrote to the memory block and/or a write direction that the controller should write data to the memory block in a next data write. For example, when the identifier is a counter, the write direction module may increment the counter.

At step808, after erasing the memory block and adjusting the identifier, the controller may perform actions such as placing the memory block on a free block list or performing the operations described above in conjunction withFIG. 7to write new data to the memory block.

FIGS. 1-8illustrate non-volatile memory systems with multi-write direction memory units. In implementations of the non-volatile memory systems described above, a write direction module of a controller of the non-volatile memory system is able to reverse a direction with which the controller writes data to a memory unit. Because the controller reverses the data write direction, over time disturbances caused during data writes to a memory unit are distributed across word lines at the beginning of the memory unit and word lines at the end of the memory unit. Therefore, by periodically reversing a write direction, an overall disturbance on the word lines at the end of the memory unit are less over time when compared to the overall disturbances that typically accumulate on word lines at an end of a memory block when controllers only write data to a memory block in a forward direction. The distribution of disturbances across the word lines at the beginning and end of the memory unit reduces a maximum disturbance that will accumulate on any one word line, thereby increasing an endurance of the memory unit.

One of skill in the art will recognize that this invention is not limited to the two dimensional and three dimensional exemplary structures described but cover all relevant memory structures within the spirit and scope of the invention as described herein and as understood by one of skill in the art.