Interfacing a switch array

An interface circuit for a switch array having an array of switches, each closeable to couple a row conductor of a plurality of row conductors to a column conductor of one or more column conductors, comprises a current generator and a current detector. The current generator has a plurality of row interface ports for coupling to different ones of the row conductors and is arranged to generate a switch array current for coupling to the row interface ports, the switch array current having a different one of a plurality of different switch array current magnitudes for different ones of the row interface ports, and generate one or more reference currents each having a different reference current magnitude. The current detector has one or more column interface ports for coupling to the one or more column conductors and is arranged to detect the switch array current flowing at any one of the one or more column interface ports, and generate a row indication indicative of which of the row conductors a closed one of the switches is coupled to by determining which one of the switch array current magnitudes the detected switch array current has by comparing the detected switch array current with the one or more reference currents.

FIELD OF THE DISCLOSURE

The present disclosure relates to an interface circuit for a switch array, for example for interfacing a keyboard to a processing device, and to a method of operating an interface circuit for a switch array.

BACKGROUND TO THE DISCLOSURE

There is an increasing requirement for a high level of integration of electronic circuits, particularly involving different types of circuitry such as RF circuits, analogue baseband circuits and digital circuits. For example, there is a requirement for a mobile telephone or a television receiver integrated in a single monolithic chip, or in a single package containing more than one chip, to contain circuitry for implementing at least some of the following elements: a fast memory interface, various digital interfaces such as a Universal Serial Bus (USB) and a Inter-Integrated Circuit (IIC) bus, a digital processing unit, analogue and mixed signal blocks, a radio frequency (RF) receiver and transmitter, a power management unit, and peripheral interfaces to devices such as a display, camera and keyboard. Elements having an output with a high voltage swing and a high frequency, such as an RF transmitter, a DC to DC converter or a class D audio amplifier, can cause electrical interference to elements having a sensitive RF input, or a sensitive analogue input, such as a microphone input or a high resolution analogue to digital converter.

To some extent, such electrical interference can be reduced by careful positioning of input and output terminals on a chip or package. For example, a keyboard interface may have a low operating frequency and cause relatively little interference, and therefore the terminals for the keyboard interface may be positioned close to RF input terminals. However, even where a keyboard interface uses a low scanning frequency, high order harmonics may be emitted. To achieve a high performance in an RF receiver, the high frequency emissions coming from a keyboard interface need to be minimised.

Another problem is the RF interference a keyboard interface can experience if its terminals are placed close to an output of an integrated RF transmitter. A high power transmitter may induce spurious signals into high impedance inputs of a keyboard interface, which may cause an undesired operation. Therefore, there is a requirement for a keyboard interface that is insensitive to RF interference and which has low high frequency emissions.

SUMMARY OF THE DISCLOSURE

According to a first aspect, there is provided an interface circuit for a switch array having an array of switches each closeable to couple a row conductor of a plurality of row conductors to a column conductor of one or more column conductors, the interface circuit comprising:

a current generator having a plurality of row interface ports for coupling to different ones of the row conductors and arranged togenerate a switch array current for coupling to the row interface ports, the switch array current having a different one of a plurality of different switch array current magnitudes for different ones of the row interface ports, andgenerate one or more reference currents each having a different reference current magnitude, and

a current detector having one or more column interface ports for coupling to different ones of the one or more column conductors and arranged todetect the switch array current flowing at any one of the one or more column interface ports, andgenerate a row indication indicative of which of the row conductors a closed one of the switches is coupled to by determining which one of the switch array current magnitudes the detected switch array current has by comparing the detected switch array current (IM) with the one or more reference currents.

According to a second aspect, there is provided a method of interfacing a switch array, the switch array having an array of switches each closeable to couple a row conductor of a plurality of row conductors to a column conductor of one or more column conductors, the method comprising:generating a switch array current for coupling to the plurality of row conductors, the switch array current having a different one of a plurality of different switch array current magnitudes for different ones of the row conductors;generating one or more reference currents each having a different reference current magnitude;detecting the switch array current flowing at any one of the one or more column conductors; andgenerating a row indication indicative of which of the row conductors a closed one of the switches is coupled to by determining which one of the switch array current magnitudes the detected switch array current has by comparing the detected switch array current with the one or more reference currents.

The interface circuit and the method of operating an interface circuit may therefore employ a common switch array current that flows through both the row conductor and the column conductor to which a closed switch is coupled, and which has a magnitude dependent on which one of the row conductors the switch array current is flowing in. The row conductor to which the closed switch is coupled may be determined dependent on the magnitude of the switch array current by comparing the detected switch array current with the one or more reference currents, either directly or indirectly. The interface circuit and the method of interfacing enables static currents to be used, rather than oscillating signals, thereby reducing the emission of electrical interference. When none of the switches is closed, the switch array current may not flow, thereby reducing electrical interference and power consumption. The generation and detection of currents, rather than voltage, enables circuitry having a low input impedance to be employed, which is resistant to external electrical interference. The use of a common current for row and column conductors enables a simple implementation within a small silicon area of a chip.

The current detector may comprise a comparison means arranged to compare the detected switch array current with the one or more reference currents by comparing a comparison current having one of a plurality of different comparison current magnitudes dependent on the detected switch array current with a threshold current having one or more different threshold current magnitudes dependent on the one or more reference currents. Likewise, the method may comprise comparing the detected switch array current with the one or more reference currents by comparing a comparison current having one of a plurality of different comparison current magnitudes dependent on the detected switch array current with a threshold current having one or more different threshold current magnitudes dependent on the one or more reference currents. Therefore, a comparison may be made between the comparison current and the threshold current, either of which may be, but need not be, equal to, respectively, the detected switch array current and one of the one or more reference currents. This enables the comparison current and/or the threshold current to be smaller than respectively, the detected switch array current and any of the one or more reference currents, enabling conservation of power. The use of a switch array current that is relatively high can reduce susceptibility to received electrical interference.

The comparison current magnitudes may be arranged to take values intermediate of a plurality of the one or more threshold current magnitudes. This enables a high immunity to received electrical interference by providing an error margin for the comparison current magnitude and the one or more threshold current magnitudes, within which desired operation can be maintained.

The comparison means may be coupled to the one or more column interface ports by a switch array current mirroring means arranged to generate the comparison current by mirroring the detected switch array current. Likewise, the method may comprise generating the comparison current by mirroring the detected switch array current. This enables the comparison current to be closely matched for each of a plurality of column interface ports at each magnitude employed, and for the close matching to be maintained despite variations in temperature and integration process.

In one example, the comparison current magnitudes may be equal to the switch array current magnitudes. This enables a simple implementation, with the comparison current being identical to the detected switch array current, or with the comparison current being generated from the detected switch array current by employing, for example, current mirrors using transistors of equal dimensions, thereby giving a unity mirroring ratio.

In another example, the switch array current mirroring means may be arranged to apply scaling such that the comparison current magnitudes are equal to scaled down values of the switch current magnitudes. This enables reduced power consumption.

The current detector may comprise a selection means for selecting sequentially different ones of a plurality of the one or more reference currents, and the comparison means may be arranged to compare the comparison current with, sequentially, the threshold current having the different threshold current magnitudes dependent on the reference current magnitude of the selected reference current. Likewise, the method may comprise selecting sequentially different ones of a plurality of the one or more reference currents and comparing the comparison current with, sequentially, the threshold current having the different threshold current magnitudes dependent on the reference current magnitude of the selected reference current. This enables a simple implementation for detecting the presence of, and determining the magnitude of, the switch array current. Typically the comparison means may comprise a plurality of current comparators equal to the number of column interface ports, that is, the number of column conductors, and one of the current comparators may be coupled to each of the column interface ports.

The comparison means may be coupled to the selection means by a reference current mirroring means arranged to generate the threshold current by mirroring the selected reference current. Likewise, the method may comprise generating the threshold current by mirroring the selected reference current. This enables the threshold current supplied to the comparison means, or each of the current comparisons, to be closely matched at each threshold current magnitude employed, and for the close matching to be maintained despite variations in temperature and integration process. The use of mirroring enables current to be generated using a low chip area, by avoiding the need for high value resistors which occupy a large chip area.

In one example, the threshold current magnitude of the threshold current may be equal to the reference current magnitude of the selected reference current. This enables a simple implementation, with the threshold current being identical to the selected one of the reference currents, or with the threshold current being generated from the selected one of the reference currents by employing, for example, current mirrors using transistors of equal dimensions, thereby giving a unity mirroring ratio.

In another example, the threshold current magnitude of the threshold current may be equal to a magnitude of a scaled down version of the selected reference current. This enables reduced power consumption.

The current detector may comprise a counter for counting pulses of a clock signal and for controlling the selection means to select sequentially the different ones of the plurality of the one or more reference currents with sequentially increasing reference current magnitudes dependent on the count. Likewise, the method may comprise counting pulses of a clock signal and selecting sequentially the different ones of the plurality of the one or more reference currents with sequentially increasing reference current magnitudes dependent on the count. This enables a low complexity.

The current detector may be arranged to start the counter in response to detecting the switch array current flowing at any of the one or more column interface ports, and to stop the counter in response to detecting the threshold current having a smallest one of a plurality of the one or more threshold current magnitudes which exceeds the comparison current magnitude of the comparison current. Likewise, the method may comprise starting the counting in response to detecting the switch array current flowing at any of the one or more column conductors, and stopping the counting in response to detecting the threshold current having a smallest one of a plurality of the one or more threshold current magnitudes which exceeds the comparison current magnitude of the comparison current. This enables power consumption to be low, by operating the counter, or by counting, for only a period required to determine the magnitude of the switch array current.

The comparison means may comprise at least one current comparator comprising: a first comparator current mirror having a first comparator port for the threshold current and a second comparator port for a mirror of current at the first comparator port; a second comparator current mirror having a third comparator port for the comparison current and a fourth comparator port for a mirror of current at the third comparator port; a third comparator current mirror having a fifth comparator port coupled to the fourth comparator port and a sixth comparator port for a mirror of current at the fifth comparator port, wherein the sixth comparator port is coupled to the second comparator port; and a limiting means having a limiting means input coupled to the second comparator port and a limiting means output coupled to a current comparison means output of the current comparison means. Such a comparator architecture can have a low input impedance, increasing the immunity of the interface circuit to received electrical interference.

The current generator may comprise a reference current generation means arranged to generate the one or more reference currents by mirroring a first input current and a switch array current generation means arranged to generate the switch array current by mirroring a second input current. Likewise, the method may comprise generating each of the one or more reference currents by mirroring a first input current and generating the switch array current by mirroring a second input current. This enables the reference currents and the switch array current with different magnitudes to be generated having precise relative magnitudes, and for the relative magnitudes to be maintained despite variations in temperature and integration process. The reference current generation means and the switch array current generation means may comprise current mirrors, and currents having different magnitudes may be generated by employing transistors of different sizes for the current mirrors. In particular, the current generator may be arranged to apply scaling such that the switch array current magnitudes are equal to scaled up values of a magnitude of the second input current. This can reduce the susceptibility to received electrical interference by enabling the switch array current to be relatively high. In some embodiments, the second input current may be the first input current.

The current detector may comprise a key bounce protection circuit arranged to prevent the generation of the row indication in response to the switch array current having a pulse duration less than a threshold. Likewise, the method may comprise preventing the generation of the row indication in response to the switch array current having a pulse duration less than a threshold. This can reduce the occurrence of spurious output signals from the interface circuit, caused by electrical interference or key bounce.

The current detector may be arranged to generate a column indication indicative of which of the one or more column conductors a closed one of the switches is coupled to, dependent on which of the one or more column interface ports the detected switch array current is flowing at. Likewise, the method may comprise generating a column indication indicative of which of the one or more column conductors a closed one of the switches is coupled to, dependent on which of the one or more column conductors the detected switch array current is flowing at. In this way, the detected switch array current may be used to determine both the column conductor and row conductor that a closed one of the switches is coupled to.

There is also provided an electronic device comprising the interface circuit and the switch array.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Referring toFIG. 1, an interface circuit100in accordance with a preferred embodiment of the present disclosure is coupled to a switch array10having an array of switches Sij, i=1 . . . 4, j=1 . . . 3. The switch array10has four row conductors X1. . . X4and three column conductors Y1. . . Y3. Each of the switches Sijis coupled between one of the row conductors X1. . . X4and one of the column conductors Y1. . . Y3. The switches Sijare normally non-conducting, and when activated, that is closed, provide a conduction path between the respective row conductor X1. . . X4and column conductor Y1. . . Y3to which they are coupled. Therefore, the array of switches Sij, i=1 . . . 4, j=1 . . . 3 is arranged as a matrix.

The interface circuit100comprises a current generator20and a current detector30. The current generator20generates a switch array current IMfor application to the switch array10. The current generator20has row interface ports24a. . .24dwhich are coupled to respective row conductors X1. . . X4of the switch array10and which deliver the switch array current IMto the respective row conductors X1. . . X4. The current detector30has column interface ports32a,32b,32cwhich are coupled to different ones of the column conductors Y1. . . Y3of the switch array10and which receive the switch array current IMfrom the column conductors Y1. . . Y3.

The flow of the switch array current IMis dependent on at least one of the switches Sijbeing closed, such that closure of one of the switches Sijallows the switch array current IMto flow. For example, if only switch S12, which is coupled between row conductor X1and column conductor Y2, is closed, the switch array current IMflows through row conductor X1and column conductor Y2to the column interface port32bof the current detector30. When none of the switches Sijis closed, the switch array current IMcannot flow. The current generator20does not need to deliver the switch array current IMwhile none of the switches Sijis closed, enabling power to be conserved, and when one of the switches Sijis closed, delivers the switch array current IMto only the row conductor X1. . . X4to which the closed switch is coupled.

The switch array current IMcan have any of a plurality of different switch array current magnitudes, depending on which row conductor X1. . . X4the switch array current IMis applied to. To assist explanation, the switch array current IMhaving four different switch array current magnitudes is denoted respectively, IM1, IM2, IM3, IM4, with the switch array current IM1having a first switch array current magnitude M1being applied to the first row conductor X1, the switch array current IM2having a second switch array current magnitude M2being applied to the second row conductor X2, the switch array current IM3having a third switch array current magnitude M3being applied to the third row conductor X3, and the switch array current IM4having a fourth switch array current magnitude M4being applied to the fourth row conductor X4. Depending on which one of the switches Sijis closed, the switch array current IMhaving any of the first, second, third or fourth magnitudes M1, M2, M3, M4, can flow through any of the column conductors Y1. . . Y3to any of the column interface ports32a,32b,32cof the current generator30.

The current generator20also generates reference currents IR1. . . IR5. The reference currents IR1. . . IR5each have different reference current magnitudes R1. . . R5, that is, each of the reference currents IR1. . . IR5has a reference current magnitude R1. . . R5that is different from the reference current magnitude R1. . . R5of each of the other reference currents IR1. . . IR5. The current generator20has reference current outputs22a. . .22ewhich are coupled to respective inputs of the current detector30and which deliver the reference currents IR1. . . IR5to the current detector30. The current detector30employs the reference currents IR1. . . IR5and the switch array current IMreceived at any one of the column interface ports32a,32b,32cof the current detector30to determine, as described below, which one of the switches Sijis closed and to generate an indication of the closed switch Sij.

In particular, the current detector30determines which column conductor Y1. . . Y3the closed switch Sijis coupled to by detecting the presence of the switch array current IMflowing at any one of the column interface ports32a,32b,32c. For this purpose, it is not necessary for the current detector30to be able to determine the switch array current magnitude M1. . . M4of the detected switch array current IM, but merely to be able to determine which of the column conductors Y1. . . Y3is conducting current. The current detector30then generates a column indication at a column indication output36aof the interface circuit100indicative of which column conductor Y1. . . Y3the closed switch Sijis coupled to.

In addition, the current detector30determines the row conductor X1. . . X4the closed switch Sijis coupled to by determining the switch array current magnitude M1. . . M4of the switch array current IMreceived at the column interface ports32a,32b,32crelative to the reference current magnitudes R1. . . R5of the reference currents IR1. . . IR5, by comparing the switch array current received at the column interface ports32a,32b,32cwith the reference currents IR1. . . IR5, either directly or indirectly. Therefore, the reference current magnitudes R1. . . R5of the reference currents IR1. . . IR5are used to define decision thresholds for determining the switch array current magnitude M1. . . M4of the switch array current IMreceived at the column interface ports32a,32b,32c. The current detector30then generates a row indication at a row indication output36bof the interface circuit100indicative of which row conductor X1. . . X4the closed switch Sijis coupled to. Further details about how the magnitudes are employed are provided below.

A method of operating the interface circuit100when one of the switches Sijis closed is illustrated in the flow chart ofFIG. 2. At step401, the switch array current IMis generated for coupling to the row interface ports24a. . .24d. The switch array current IMhas a different one of the first, second, third and fourth switch array current magnitudes M1. . . M4for different ones of the row interface ports24a. . .24d. The switch array current IMis applied to, that is flows in, only the row interface port24a. . .24dto which the closed switch Sijis coupled, as the other ones of the row interface ports24a. . .24dare open circuit. At step402, the reference currents IR1. . . IR5are generated, either simultaneously or sequentially, each having a different reference current magnitude R1. . . R5. At step403, the switch array current IMflowing at any one of the column interface ports32a. . .32cis detected. At step404, dependent on which of the column interface ports32a. . .32cthe switch array current IMis detected as flowing in, a column indication indicative of which of the column conductors Y1. . . Y3the closed switch Sijis coupled to is generated. At step405, the magnitude of the detected switch array current IMis determined using the reference currents IR1. . . IR5to define decision thresholds, and by determining which one of the first, second, third and fourth switch array current magnitudes M1. . . M4the detected switch array current IMhas with respect to the decision thresholds. At step406, dependent on the determined switch current magnitude M1. . . M4of the detected switch array current IM, a row indication indicative of which of the row conductors X1. . . X4the closed switch Sijis coupled to is generated.

An example of the current generator20is illustrated inFIG. 3. There is a current input26to the current generator20for a generator input current IINgen. The generator input current IINgenmay be generated within the interface circuit100or may be provided externally to the interface circuit100. There are a plurality of reference current mirror transistors202each coupled to one of the reference current outputs22a. . .22eof the current generator20, and each arranged to generate one of the reference currents IR1. . . IR5by mirroring the generator input current IINgenthrough a current generator input transistor206arranged in a diode configuration. There are a plurality of switch array current mirror transistors204each coupled to one of the row interface ports24a. . .24dof the current generator20, and each arranged to generate the switch array current IMat a different magnitude by mirroring the generator input current IINgenthrough the current generator input transistor206. The magnitudes of the reference currents IR1. . . IR5and of the switch array current IMmay each be scaled up values of a magnitude of the generator input current IINgen. Each of the reference current mirror transistors202and the switch array current mirror transistors204are coupled between a voltage rail208and the respective reference current outputs22a. . .22eor row interface ports24a. . .24d. The current generator input transistor206is coupled between the voltage rail208and the current input26. A gate of each of the reference current mirror transistors202, the switch array current mirror transistors204and the current generator input transistor206is coupled to the current input26.

An example of the current detector30will now be described with reference toFIG. 4. A multiplexer (MUX)302has inputs for the reference currents IR1. . . IR5received from the current generator20. The multiplexer302selects sequentially different ones of the reference currents IR1. . . IR5to deliver at a multiplexer output303of the multiplexer302. The selection of the different ones of the reference currents IR1. . . IR5is determined by a counter390which is coupled to the multiplexer302.

A current distributor304has an input coupled to the multiplexer output303for receiving the selected one of the reference currents IR1. . . IR5, and delivers at each of a plurality of current distributor outputs305a threshold current I1dependent on the selected one of the reference currents IR1. . . IR5. In one example, the current distributor304generates each instance of the threshold current I1by means of a respective current distributor current mirror transistor306which mirrors the selected one of the reference currents IR1. . . IR5through a current distributor input transistor308arranged in a diode configuration. Each of the current distributor current mirror transistors306are coupled between a ground307and the respective current distributor outputs305. The current distributor input transistor308is coupled between the ground and the multiplexer output303, and a gate of each of the current distributor current mirror transistors306and the current distributor input transistor308is coupled to the multiplexer output303. The threshold current I1may be equal to the selected one of the reference currents IR1. . . IR5, or may be a scaled version, in particular a scaled down version, of the selected one of the reference currents IR1. . . IR5, such that the threshold current I1is proportional to, and smaller than, the selected one of the reference currents IR1. . . IR5.

A first, second and third comparator320a,320b,320ceach have a first input322a,322b,322ccoupled to respective current distributor outputs305for receiving the threshold current I1. The first, second and third comparators320a,320b,320ceach have a second input324a,324b,324ccoupled to the respective column interface ports32a,32b,32cof the current detector30by means of a respective scaling current mirror310a,310b,310c.

The threshold current I1is applied simultaneously and with equal magnitude to the respective first input322a,322b,322cof each of the first, second and third comparators320a,320b,320c. The comparison current I2is applied to the second input324a,324b,324cof only one of the first, second and third comparators320a,320b,320cat any one time, depending on which of the column conductors Y1. . . Y3the switch array current IMis flowing in, and no current flows at the second input324a,324b,324cof the other two of the first, second and third comparators320a,320b,320c. In one example, the scaling current mirrors310a,310b,310cprovide scaling, in particular scaling down, such that the comparison current I2is proportional to, and smaller than, the switch array current IMat the respective column interface ports32a,32b,32c. In another example, the scaling current mirrors310a,310b,310cmay employ a unity scaling factor, such that the comparison current I2is equal to the switch array current IMat the respective column interface ports32a,32b,32c. Equivalently, instead of employing a unity scaling factor, the scaling current mirrors310a,310b,310cmay be omitted, and so the second inputs324a,324b,324cof the first, second and third comparators320a,320b,320cmay be coupled directly to the respective column interface ports32a,32b,32c. The first, second and third comparators320a,320b,320ceach have a respective output326a,326b,326cfor an indication of whether the threshold current I1applied to their respective first input322a,322b,322cis larger or smaller than the current flowing at their respective second input324a,324b,324c. Therefore, the threshold current I1at the respective first input322a,322b,322cof each of the first, second and third comparators320a,320b,320cdefines a decision threshold.

FIG. 6illustrates current magnitudes for the case where the current distributor304does not perform scaling, such that the threshold current magnitudes A1, A3, A5, A7, A9, are equal to the reference current magnitudes R1. . . R5. The reference current magnitudes R1. . . R5increase from the smallest reference current IR1having reference current magnitude R1through to the largest reference current IR5having reference current magnitude R5. Also in the example ofFIG. 6, the scaling current mirrors310a,310b,310cperform scaling down. In particular, the switch array current IMhaving switch array current magnitudes M1, M2, M3and M4, or more specifically the switch array currents IM1, IM2, IM3and IM4, are scaled down to the comparison current magnitudes A2, A4, A6and A8respectively.

FIG. 7illustrates current magnitudes for the case where the current distributor304and the scaling current mirrors310a,310b,310ceach perform scaling down, with the scaling factor employed by the current distributor304being smaller than the scaling factor employed by the scaling current mirrors310a,310b,310c. In this example, the reference currents IR1. . . IR5having respective reference current magnitudes R1, R2, R3, R4and R5are scaled down to the threshold current magnitudes A1, A3, A5, A7and A9respectively, and, as inFIG. 6, the switch array current IMhaving switch array current magnitudes M1, M2, M3and M4are scaled down to the comparison current magnitudes A2, A4, A6and A8respectively. The reference currents IR1. . . IR5having the different reference current magnitudes R1, R2, R3, R4and R5, and the switch array current IMhaving the different switch array current magnitudes M1, M2, M3and M4, may be generated by employing different size transistors for the reference current mirror transistors202and the switch array current mirror transistors204.

In an initial quiescent condition when none of the switches Sijare closed, the counter390is not counting, the multiplexer302delivers the smallest reference current IR1, resulting in the threshold current I1having the threshold current magnitude A1, the switch array current IMdoes not flow, resulting in the comparison current I2being zero, and the outputs326a,326b,326cof the first, second and third comparators320a,320b,320call deliver a binary 0 signal, indicating that the threshold current I1is larger than the comparison current I2.

When one of the switches Sijis closed, the switch array current IMflows, resulting in, depending on which of the columns Y1, Y2, Y3the closed switch Sijis coupled to, an increase in the comparison current I2at the second input324a,324b,324cof one of the first, second and third comparators320a,320b,320c. As a result, the output326a,326b,326cof the affected first, second or third comparator320a,320b,320cchanges to a binary 1 signal, indicating that the comparison current I2is larger than the threshold current I1, for that comparator320a,320b,320c. Therefore, the outputs326a,326b,326cof the first, second and third comparators320a,320b,320ctogether provide a digital word indicative of which of the columns Y1, Y2, Y3the closed switch Sijis coupled to. This digital word is a column indication and is delivered to the column indication output36aof the interface circuit100via some intervening circuitry that is described below.

A first OR gate350ahas inputs352coupled to each of the outputs326a,326b,326cof the first, second and third comparators320a,320b,320c, and generates at an output354of the first OR gate350aa binary 1 signal whenever any one of the outputs326a,326b,326cof the first, second and third comparators320a,320b,320cchanges to a binary 1 signal, indicating that one of the switches Sijis closed. The output354of the first OR gate350ais coupled to a start input392of the counter390by means of a switch bounce protection circuit380. The switch bounce protection circuit380has an input382coupled to the output354of the first OR gate350a. A first delay element385has an input coupled to the input382of the switch bounce protection circuit380. A first AND gate (&)384has a first input coupled to the input382of the switch bounce protection circuit380and a second input coupled to an output of the first delay element385. An output of the first AND gate384is coupled to an input of a first flip flop386for latching a signal at the output of the first AND gate384, and an output of the first flip flop386is coupled to an output388of the switch bounce protection circuit380. A binary 1 signal at the output354of the first OR gate350apropagates through to the output388of the switch bounce protection circuit380provided it is present for a period exceeding a delay introduced by the first delay element385. Otherwise, a binary 1 signal at the output354of the first OR gate350ahaving a shorter duration is suppressed by the switch bounce protection circuit380and therefore does not appear at the output388of the switch bounce protection circuit380. The binary 1 signal at the output388of the switch bounce protection circuit380provides a START signal which enables the counter390to commence counting pulses of a clock signal CLK provided at a clock input396of the counter. The clock signal CLK may be generated internally or externally to the interface circuit100.

Second, third and fourth AND gates330a,330b,330ceach have a first input coupled to respective outputs326a,326b,326cof the first, second and third comparators320a,320b,320cand a second input coupled to the output388of the switch bounce protection circuit380. An output of each of the second, third and fourth AND gates330a,330b,330cis coupled to an input of respective second, third and fourth flip flops340a,340b,340c, and outputs of the second, third and fourth flip flops340a,340b,340care coupled to the column indication output36a. In operation, a binary 1 signal at the output326a,326b,326cof any of the first, second and third comparators320a,320b,320cpropagates through the respective one of the second, third and fourth AND gates330a,330b,330cto the respective one of the second, third and fourth flip flops340a,340b,340cwhere it is latched, provided that it is of sufficient duration to propagate through the switch bounce protection circuit380.

An output of the counter390is coupled to the multiplexer303and controls the multiplexer303to select the reference currents IR1. . . IR5in order of increasing magnitude, and therefore to cause the magnitude of the threshold current I1to increase in a stepwise manner. When the threshold current I1has a magnitude exceeding the magnitude of the comparison current I2, the binary 1 signal at the respective output326a,326b,326cof the first, second and third comparators320a,320b,320cwill revert to a binary 0 signal. Consequently, the outputs of the second, third and fourth AND gates330a,330b,330cwill each present a binary 0 signal. This condition is detected by a second OR gate350bwhich has inputs coupled to the output of each of the second, third and fourth AND gates330a,330b,330c, and an output of the second OR gate350bis coupled to a stop input394of the counter390, by means of a fifth flip flop352which latches the signal at the output of the second OR gate350bto provide a STOP signal to stop the counter390from counting when the threshold current I1has a magnitude exceeding the magnitude of the comparison current I2. When the counter390stops counting, the count value at its output is indicative of the row conductor R1. . . R4to which the closed switch Sijis coupled. The count value at the output of the counter390, which is a row indication, is coupled to the row indication output36bof the interface circuit100.

For example, in the embodiment ofFIG. 4, the counter390has a three-bit output, with the three bits represented inFIG. 4as D0, D1, and D2, with D0being the least significant bit and D2being the most significant bit. When the output count is binary 000, the multiplexer303selects the smallest reference current IR1, having the reference current magnitude R1. If switch S43coupled to the fourth row conductor X4and third column conductor Y3is closed, then the switch array current IMhaving the switch array current magnitude M4will flow, which, according to the scheme illustrated inFIGS. 6 and 7, results in the comparison current I2having the comparison current magnitude A8. As the count value at the output of the counter390increases, the magnitude of the threshold current I1increases in a stepwise manner through the threshold current magnitudes A1, A3, A5, A7, A9until it reaches the threshold current magnitude A9, which is the smallest threshold current magnitude exceeding the comparison current magnitude A8of the comparison current I2. At this point, the output of the second OR gate350reverts from a binary 1 signal to a binary 0 signal, which causes the counter390to stop counting, having reached a count value of binary 100.

Referring toFIG. 4, the output of the fifth flip flop352is also coupled to an output37, so that the STOP signal that stops the counter390from counting may also be used as an interrupt signal IRQ to prompt a non-illustrated processor to read the column indication at the column indication output36aand the row indication at the row indication output36b. Such a processor may be integral to the interface circuit100or external.

A reset circuit370has a second delay element371having an input coupled to the output388of the switch bounce protection circuit380and an output coupled to an input of a pulse generator373. The pulse generator373has an output coupled to a first input of a third OR gate375, and an output of the third OR gate375provides an output of the reset circuit370. The output of the reset circuit370is coupled to reset inputs378of the counter390, the first, second, third, fourth and fifth flip flops386,340a,340b,340c,352and the second delay element371thereby, in response to a binary 1 signal at the output388of the switch bounce protection circuit308, providing a RESET signal for resetting these elements to their initial quiescent condition delivering binary 0 signals at their respective outputs, after a delay defined by the second delay element371. For clarity, couplings between the output of the reset circuit370and the reset inputs378of the counter390, the first, second, third and fourth flip flops386,340a,340b,340c,352and the second delay element371omitted fromFIG. 4. The RESET signal at the output of the reset circuit370may also be coupled to other elements internal or external to the current detector30, or internal or external to the interface circuit100, if desired. Additionally, the second delay element371and the third OR gate375have a further reset input379for an external reset signal generated externally to the current detector30and either internally or externally to the interface circuit100. For example, the external reset signal may be generated by the processor that reads the row and column indication outputs36a,36b.

FIG. 8illustrates the timing of currents and binary signals within the interface circuit100. Graph a) shows the threshold current I1, which has the lowest threshold current magnitude A1in the initial quiescent state at time t0when none of the switches Sijare closed, and the comparison current I2which is zero at time t0. At time t1the switch S43is closed. The comparison current I2commences to flow, increasing gradually to the highest comparison current magnitude A8. When the comparison current I2exceeds the threshold current I1, the output of the third comparator320cswitches from a binary 0 signal to a binary 1 signal, as shown in graph b). Due to switch bounce, there is some transient variation of the comparison current I2which causes the output of the third comparator320cto vary, but at time t2the output of the third comparator320cbecomes a steady binary 1 signal. Graph c) shows pulses of the clock signal CLK which the counter390counts, graph d) shows the least significant bit D0at the output of the counter390, graph e) shows the next least significant bit D1at the output of the counter390, graph f) shows the most significant bit D2at the output of the counter390, and graph g) shows the START signal. At time t3the counter390commences counting in response to the START signal, the delay between time t2and time t3being determined by the switch bounce protection circuit380. Consequently, at time t3the least significant bit D0at the output of the counter390switches to a binary 1, such that the output of the counter390delivers a binary value 001, and the threshold current I1switches to the second lowest threshold current magnitude A3. At time t4the least significant bit D0at the output of the counter390switches to a binary 0 and the next least significant bit D1switches to a binary 1, such that the output of the counter390delivers a binary value 010, and the threshold current I1switches to the third lowest threshold current magnitude A5. At time t5the least significant bit D0switches to a binary 1, such that the output of the counter390delivers a binary value 011, and the threshold current I1switches to the fourth lowest threshold current magnitude A7. At time t6the least significant bit D0switches to a binary 0, the next least significant bit D1switches to a binary 0, and the most significant bit D2switches to a binary 1, such that the output of the counter390delivers a binary value 100, and the threshold current I1switches to the highest threshold current magnitude A9. At this stage, the current detector30detects that the threshold current I1exceeds the comparison current I2. After a short delay due to the propagation of signals within the interface circuit100, at time t7the STOP signal switches to a binary 1 and the counter390stops counting, with the counter output bits D0, D1and D2being held at their current values to enable them to be read at the row indication output36bbefore time t8. Also during the period t7to t8the column indication output36ais read. Also at time t7, the threshold current I1, is reduced to zero. At time t8the reset circuit370generates the RESET signal, which causes the output of the counter390to be reset to binary value 000, and the START and STOP signals to be reset to a binary 0. At this stage the interface circuit100returns to the initial quiescent condition.

FIG. 9illustrates an example embodiment of the first comparator320a, and the second and third comparators320b,320cmay have a similar structure. A first comparator current mirror321ahas a first comparator port323afor the threshold current and a second comparator port325afor a mirror of a current at the first comparator port323a. A second comparator current mirror321bhas a third comparator port323bfor the comparison current I2and a fourth comparator port325bfor a mirror of a current at the third comparator port323b. A third comparator current mirror321chas a fifth comparator port323ccoupled to the fourth comparator port325band a sixth comparator port325cfor a mirror of a current at the fifth comparator port323c. The sixth comparator port325cis coupled to the second comparator port325a. An inverter327has an inverter input328coupled to the second comparator port325aand an inverter output329for coupling to the output326aof the first comparator320a. Instead of the inverter327, more generally general any limiting device that provides a binary signal at its output indicative of whether a signal at its input is above or below a threshold level may be used. The limiting device, or limiter, may employ, for example, a high gain amplifier, and specifically a limiting amplifier. The limiting device need not provide inversion.

FIG. 10illustrates an electronic device500comprising the interface circuit100. The electronic device500has a microcontroller520for controlling the operation of the electronic device500. A wireless transceiver540may is coupled to the microcontroller520to enable wireless communication between the electronic device500and non-illustrated external devices. A display530is coupled to the microcontroller520for displaying information to a user of the electronic device500, and a keypad510enables the user to controller the operation of the electronic device500. The keypad510comprises the switch array10, and the switch array10is coupled to the interface circuit100by means of the row interface ports24a. . .24dand the column interface ports32a,32b,32c. The interface circuit100is coupled to the microcontroller520by means of the column indication output36aand the row indication output36bfor delivering the column indication and row indication to the microcontroller520. Such an electronic device500, may be, for example, a mobile telephone, personal audio player, broadcast receiver, a positioning device, a gaming device or a security device.

Although embodiments of the interface circuit100have been described for use with a switch array10having four row conductors X1. . . X4and three column conductors Y1. . . Y3, the interface circuit100, and the method of operating the interface circuit100, is not limited to any particular number of row conductors X1. . . X4or column conductors Y1. . . Y3.

FIG. 11illustrates an embodiment of the interface circuit100for use with the switch array10having an arbitrary number α of row conductors X1. . . Xα, an arbitrary number β of column conductors Y1. . . Yβ, and an arbitrary number α·β of switches Sij, i=1 . . . α, j=1 . . . β. The current generator20generates switch array currents IM1. . . IMα, for application to the switch array10. The current generator20has row interface ports24a. . .24α which are coupled to respective row conductors X1. . . Xαof the switch array10and which deliver the switch array currents IM1. . . IMαto the respective row conductors X1. . . Xα. The current detector30has column interface ports32a. . .32β which are coupled to respective column conductors Y1. . . Yβof the switch array10and which receive the switch array current IM1. . . IMαfrom the column conductors Y1. . . Yβ. The current generator20also generates reference currents IR1. . . IR(α+1). The current generator20has reference current outputs22a. . .22(α+1) which are coupled to respective inputs of the current detector30and which deliver the reference currents IR1. . . IR(α+1)to the current detector30. The current detector30employs the reference currents IR1. . . IR(α+1)and the one of the switch array currents IM1. . . IMαreceived at any one of the column interface ports32a. . .32β of the current detector30to determine a closed switch of the switch array10.

In particular, the switch array10may have a single column conductor, that is, β=1. In this case, the current detector30may have a single one of the column interface ports (32a. . .32c) and therefore does not need to determine which one of a plurality of the column interface ports (32a. . .32c) the detected switch array current IMis flowing at, and therefore may not generate the column indication. In this case step404ofFIG. 2may be omitted.

In general, the required number of different reference current magnitudes (R1. . . R5) is, at minimum, one less than the number of row conductors (X1. . . X4) or row interface ports (24a. . .24d). So, for example, if the interface circuit (100) has two row interface ports (24a. . .24d), for coupling to two row conductors (X1. . . X4), a single reference current magnitude (R1. . . R5), and therefore a single reference current (IR1. . . IR5), is sufficient to provide a single threshold current magnitude (A1, A3, A5, A7, A9) and therefore provide a single decision threshold for distinguishing between two magnitudes of the comparison current (I2). However, it is preferable to provide more than the minimum number of reference current magnitudes (R1. . . R5) in order to provide a quiescent threshold current I1having a magnitude smaller than the smallest magnitude of the comparison current I2, and to provide a threshold current I1having a magnitude larger than the largest magnitude of the comparison current I2, in order to provide immunity from noise and to facilitate generation of the row indication and the column indication as described.

FIG. 12illustrates an embodiment of the current generator20that may be used instead of the embodiment illustrated inFIG. 3, and which is particularly suited for use where the scaling current mirrors310,310b,310cprovide scaling down. In the embodiment ofFIG. 12, the input26for the generator input current IINgenis coupled to a gate of the current generator input transistor206by means of a current mirror stage203which generates a first input current IIN1for delivery to the current generator input transistor206, by mirroring the generator input current IINgen. The current generator input transistor206is arranged in a diode configuration and is coupled between the voltage rail208and the current mirror stage203, The reference current mirror transistors202are each coupled to one of the reference current outputs22a. . .22eof the current generator20, and are each arranged to generate one of the reference currents IR1. . . IR5by mirroring the first input current IIN1through the current generator input transistor206. The current mirror stage203is also coupled to a gate of a secondary current generator input transistor207, which is also arranged in a diode configuration and is coupled between the voltage rail208and the current mirror stage203. The current mirror stage203generates a second input current IIN2for delivery to the secondary current generator input transistor207by mirroring the generator input current IINgen. Each of the switch array current mirror transistors204are coupled between the voltage rail208and the respective row interface ports24a. . .24d. A gate of each of the switch array current mirror transistors204and the secondary current generator input transistor207are coupled together and the switch array current mirror transistors204are each arranged to generate the switch array current IMat a different magnitude by mirroring the second input current IIN2. The switch array current mirror transistors204in combination with the secondary current generator input transistor207may perform scaling, and in particular scaling up, such that the different magnitudes of the switch array current IMare equal to scaled values of a magnitude of the second input current IIN2and therefore are equal to scaled values of the magnitude of the generator input current IINgen. Similarly, the magnitudes of the reference currents IR1. . . IR5may each be scaled values, and in particular scaled up values, of the magnitude of the generator input current IINgen.

Although embodiments have been described in which the switch array current IMis applied to row conductors X1. . . X4, the designation of the conductors of the switch array10as either a row conductor X1. . . X4or a column conductor Y1. . . Y3is intended to be arbitrary, provided that each of the switches Sijis arranged to couple one of the row conductors X1. . . X4to one of the column conductors Y1. . . Y3, and the designation is not intended to imply any physical arrangement or orientation of the conductors. Therefore, the disclosure is applicable with the designation of row and column conductors interchanged.

Although embodiments have been described in which the term generate, when applied to a current, indicates the sourcing of the current, the disclosure is equally applicable where the term generate indicates sinking the current. In this context, the term generate, when applied to a current, is therefore intended to encompass both sourcing the current and sinking the current.

Although embodiments have been described in which a multiplexer302is employed for coupling sequentially different ones of the reference currents IR1. . . IR5to a plurality of current comparators (320a,320b,320c), alternatively, additional current comparators may be employed for coupling simultaneously to different ones of the reference currents.

The operation of the interface circuit100has been described for the circumstances in which only one of the switches Sijis closed. Additional provision may be included for detecting the simultaneous closure of more than one of the switches Sij. For example, if more than one switch Sijcoupled to the same one of the row conductors X1. . . X4but different ones of the column conductors Y1. . . Y3are closed simultaneously, the switch array current IMwill flow simultaneously at more than one of the column interface ports32a,32b,32c, resulting in a binary 1 signal at the output326a,326b,326cof more than one of the current comparators. This circumstance may be detected within the interface circuit100, and appropriate action taken, for example suppressing the column indication at the column indication output36aand the row indication at the row indication output36b, or an external device may detect this condition at the column indication output36a. Similarly, if more than one switch Sijcoupled to the same one of the column conductors Y1. . . Y3but different ones of the row conductors X1. . . X4are closed simultaneously, the switch array current IM, and consequently the comparison current I2, may have a magnitude outside of the expected values of the switch array current magnitude M1. . . M4and the comparison current magnitude A2, A4, A6, A8. This circumstance may be detected within the interface circuit100, for example as an unexpectedly high count value, and appropriate action taken, for example suppressing the column indication at the column indication output36aand the row indication at the row indication output36b.

It will be understood that the embodiments described above are only examples and that modifications may be made to the embodiments without departing from the scope of the claims.

Other variations and modifications will be apparent to the skilled person. Such variations and modifications may involve equivalent and other features which are already known and which may be used instead of, or in addition to, features described herein. Features that are described in the context of separate embodiments may be provided in combination in a single embodiment. Conversely, features which are described in the context of a single embodiment may also be provided separately or in any suitable sub-combination.

It should be noted that the term “comprising” does not exclude other elements or steps, the term “a” or “an” does not exclude a plurality, a single feature may fulfil the functions of several features recited in the claims and reference signs in the claims shall not be construed as limiting the scope of the claims. It should also be noted that the Figures are not necessarily to scale; emphasis instead generally being placed upon illustrating the principles of the present invention.