Image sensor including a plurality of pixel regions and an isolation region including device isolation structures

Provided is an image sensor including an organic photoelectric layer capable of enhancing color reproduction. An image sensor includes a semiconductor substrate including a plurality of pixel regions spaced apart from each other and an isolation region therebetween. Each of the plurality of pixel regions has a unit pixel. The image sensor also includes a device isolation layer in the isolation region and surrounding the unit pixel, a first transparent electrode layer, an organic photoelectric layer, and a second transparent electrode layer. The image sensor further includes a via plug electrically connected to the first transparent electrode layer, and arranged between the device isolation layers in the isolation region. The via plug passes through the isolation region. The first transparent electrode layer, the organic photoelectric layer and the second transparent electrode layer are sequentially arranged over the semiconductor substrate.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the benefit of priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2017-0058093, filed on May 10, 2017, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

BACKGROUND

The present disclosure relates to an image sensor, and more particularly, to an image sensor including an organic photoelectric layer.

An image sensor for converting light waves into an electrical signal is used to generate an image in a camera mounted in an automobile, a security device, and a robot as well as consumer electronics (CE) devices such as a digital camera, a camera for a portable phone, and a portable camcorder.

Image sensors having a smaller size and higher resolution have become more prevalent, and thus, an image sensor including an organic photoelectric layer is adopted to reduce a pixel size.

SUMMARY

The present disclosure provides an image sensor including an organic photoelectric layer capable of enhancing color reproduction.

According to an aspect of the disclosed embodiments, there is provided an image sensor including a semiconductor substrate including a plurality of pixel regions spaced apart from each other and an isolation region therebetween. Each of the plurality of pixel regions has a unit pixel. The image sensor also includes a device isolation layer disposed in the isolation region and surrounding the unit pixel, a first transparent electrode layer, an organic photoelectric layer, a second transparent electrode layer, and a via plug electrically connected to the first transparent electrode layer. The via plug is disposed between the device isolation layers in the isolation region, and passes through the isolation region. The first transparent electrode layer, the organic photoelectric layer, the second transparent electrode layer are sequentially disposed over the semiconductor substrate.

According to another aspect, there is provided an image sensor including a semiconductor substrate including a plurality of pixel regions spaced apart from each other and an isolation region. A device isolation layer is disposed between two adjacent pixel regions among the plurality of pixel regions. Each of the plurality of pixel regions has a unit pixel. The image sensor also includes a first transparent electrode layer disposed over the semiconductor substrate and in each of the plurality of pixel regions to correspond to the unit pixel, a second transparent electrode layer formed as an integral part over the plurality of pixel regions, and an organic photoelectric layer disposed between the first transparent electrode layer and the second transparent electrode layer. The image sensor further includes a via plug disposed between the device isolation layers and electrically connecting the first transparent electrode layer and the unit pixel by passing through the isolation region of the semiconductor substrate.

According to another aspect, there is provided an image sensor including a semiconductor substrate comprising a plurality of pixel regions spaced apart from each other and an isolation region therebetween. Each of the plurality of pixel regions has a unit pixel, and a device isolation layer is arranged in each isolation region. The image sensor also includes a first transparent electrode layer arranged over the semiconductor substrate and in each of the plurality of pixel regions to correspond to the unit pixel, a second transparent electrode layer formed as an integral part over the plurality of pixel regions, and an organic photoelectric layer between the first transparent electrode layer and the second transparent electrode layer. The image sensor further includes a via plug arranged between the device isolation layers and electrically connecting the first transparent electrode layer and the unit pixel by passing through the isolation region of the semiconductor substrate. Between two adjacent unit pixels, a width of the via plug is less than a width of the device isolation layer.

DETAILED DESCRIPTION OF THE EMBODIMENTS

FIGS. 1A and 1Billustrate vertical cross-sectional views showing portions of an image sensor according to an example embodiment.

Referring toFIGS. 1A and 1B, an image sensor100includes a semiconductor substrate200, a plurality of pixel regions PR and an isolation region IR disposed between adjacent pixel regions PR. A unit pixel UPX may be disposed in each of the pixel regions PR. In the semiconductor substrate200, each of the pixel regions PR may be spaced apart from each other by an isolation region IR.

In the present example, the unit pixel UPX may include at least two photodiodes vertically stacked to detect light of at least two different wavelength bands. In the present specification, it is illustrated, for example, that a unit pixel UPX detects light of two different wavelength bands, but is not limited thereto. In some embodiments, the unit pixel UPX may include a first unit pixel UPX1capable of detecting red light and green light and a second unit pixel UPX2capable of detecting blue light and green light. The first and second unit pixels UPX1and UPX2may collectively constitute a single color pixel. In some embodiments, the unit pixel UPX may detect blue light, red light, and green light, and, thus, one unit pixel UPX may constitute one color pixel.

The semiconductor substrate200may be, for example, any one of a bulk substrate, an epitaxial substrate or a silicon on insulator (SOI) substrate. The semiconductor substrate200may include, for example, silicon (Si). Alternatively, the semiconductor substrate200may include a semiconductor element such as germanium (Ge) or a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). The semiconductor substrate200may be configured based on a semiconductor substrate having the first conductive type. The semiconductor substrate200may be, for example, a p-type semiconductor substrate.

In the semiconductor substrate200of the pixel regions PR, a plurality of photoelectric conversion devices204may be disposed. In some embodiments, a photoelectric conversion device204may be disposed in each of the pixel regions PR. The photoelectric conversion device204may be a photodiode. The photoelectric conversion device204may include a first impurity region204aand a second impurity region204b. The first impurity region204amay be deeply formed far from a first surface201aof the semiconductor substrate200. The second impurity region204bmay be thinly formed on the first surface201aof the semiconductor substrate200. The first impurity region204aand the second impurity region204bmay have different conductive types from each other. For example, the first impurity region204amay be doped with n-type impurities, and the second impurity region204bmay be doped with p-type impurities.

In the semiconductor substrate200of a plurality of pixel regions PR in which each photoelectric conversion device204is disposed, a storage node region206may be disposed to be spaced apart from the photoelectric conversion device204. The storage node region206, for example, may be doped with n-type impurities. The storage node region206may be formed as a single doping region. The storage node region206may have a horizontal area smaller than that of the photoelectric conversion device204.

In the semiconductor substrate200, device isolation layers202and210may be disposed in the isolation region IR. The device isolation layers202and210may include the first device isolation layer202and the second device isolation layer210. The first device isolation layer202may extend from the first surface201ato a second surface201b, of the semiconductor substrate200, while having a relatively low height. The second device isolation layer210may extend between the first surface201aand the second surface201b, of the semiconductor substrate200, while having a relatively great height. That is, the second device isolation layer210may be higher than the first device isolation layer202. For example, the first device isolation layer202may be a shallow trench isolation (STI), and the second device isolation layer210may be a deep trench isolation (DTI).

The second device isolation layer210may be formed to fill a trench205extending between the first surface201aand the second surface201bof the semiconductor substrate200. In some embodiments, the trench205may extend from the first surface201ato the second surface201b, of the semiconductor substrate200, but is not limited thereto. In some embodiments, the trench205may extend from the first surface201atowards the second surface201bof the semiconductor substrate200, but may not extend up to the second surface201b. In some embodiments, the trench205may extend from the second surface201btowards the first surface201aof the semiconductor substrate200, but may not extend up to the first surface201a. Accordingly, the second device isolation layer210may extend from any one surface of the first surface201aand the second surface201bof the semiconductor substrate200towards another surface, or may extend from just the first surface201ato the second surface201b.

The first device isolation layer202may be formed of, for example, oxide, nitride, oxynitride, or a combination thereof. The second device isolation layer210may be formed of, for example, oxide, nitride, oxynitride, or a combination thereof. In some embodiments, the second device isolation layer210may cover a core isolation layer formed of a metal or a semiconductor material and a side wall of the core isolation layer, and may include a cover isolation layer formed of an insulation material such as a high-k dielectric.

A wire structure220is disposed on the first surface201aof the semiconductor substrate200. The wire structure220may include a front side interlayer insulating layer221and a plurality of front side wires223. The front side interlayer insulating layer221may include a high density plasma (HDP) oxide, a TEOS oxide, a Tonen SilaZene (TOSZ), a spin on glass (SOG), an undoped silica glass (USG), a low-k dielectric material, or the like. The front side wires223may include, for example, a metal material or a conductive metal nitride such as copper (Cu), aluminum (Al), titanium (Ti), titanium nitride (TiN), or tungsten (W).

In some embodiments, a supporting layer208may be attached on the wire structure220. The supporting layer208may be used to enhance the strength of the semiconductor substrate200that is thinned due to a polishing process. The supporting layer208may be formed of, for example, silicon oxide, silicon nitride and/or a semiconductor material. In some embodiments, the supporting layer208may be omitted.

The wire structure220may include a contact via213contacting the storage node region206and extending in the wire structure220, and a buffer layer217disposed in the wire structure220and contacting the contact via213. Thus, the buffer layer217may be electrically connected to the storage node region206formed in the semiconductor substrate200through the contact via213. The buffer layer217may include, for example, a metal material such as copper (Cu), aluminum (Al), titanium (Ti), a conductive metal nitride such as titanium nitride (TiN), or carbon nanotube.

In some embodiments, a horizontal area of the contact via213may be gradually increased as it gets farther away from the first surface201aof the semiconductor substrate200. The contact via213may be formed of, for example, a metal or a conductive metal nitride such as copper (Cu), aluminum (Al), titanium (Ti), titanium nitride (TiN), or tungsten (W). In some embodiments, between the contact via213and the front side interlayer insulating layer221, a protection insulating layer (not shown) may be disposed. The protection insulating layer may be formed of oxide or nitride.

In some portions of the isolation region IR of the image sensor100, a via hole225may be formed, extending through the semiconductor substrate200from the second surface201bto the first surface201aof the semiconductor substrate200. In some embodiments, the via hole225may extend from the second surface201bof the semiconductor substrate200to the buffer layer217. In some embodiments, the via hole225may be formed to pass through the first device isolation layer202.

A side surface insulating layer227may be formed at a side surface of the via hole225. The side surface insulating layer227may be formed of oxide or nitride. The via hole225may be filled with a first via plug229. The first via plug229may fully fill the via hole225to contact the side surface insulating layer227. Thus, the first via plug229may pass through the semiconductor substrate200. The first via plug229may be formed of, for example, a metal or a conductive metal nitride such as copper (Cu), aluminum (Al), titanium (Ti), titanium nitride (TiN), or tungsten (W).

In some embodiments, some of the via hole225, the side surface insulating layer227, and the first via plug229may separately constitute portions formed in the semiconductor substrate200and portions formed in the wire structure220.

The side surface insulating layer227and the first via plug229may be collectively referred to as a penetrating via structure227and229.

Over the second surface201bof the semiconductor substrate200, a color filter layer240may be formed between antireflective layers230. The color filter layer240may allow light that is incident through a micro lens286to pass, and light with a required wavelength may only be incident to the photoelectric conversion device204through the second surface201b.

In some embodiments, the color filter layer240may include a first color filter layer242and a second color filter layer244. Each of the first unit pixel UPX1and the second unit pixel UPX2may respectively include the first color filter layer242and the second color filter layer244corresponding to the photoelectric conversion device204formed in each thereof. In some embodiments, the first color filter layer242included in the first unit pixel UPX1may be a red (R) color filer, and the second color filter layer244included in the second unit pixel UPX2may be a blue (B) color filter. Accordingly, in the first unit pixel UPX1, red light wavelength may pass through the first color filter layer242to reach the photoelectric conversion device204. Furthermore, in the second unit pixel UPX2, blue light wavelength may pass through the second color filter layer244to reach the photoelectric conversion device204.

Over the second surface201bof the semiconductor substrate200, a first cover insulating layer234covering the color filter layer240may be formed. The first cover insulating layer234may be formed of, for example, an oxide, a nitride, a low-k dielectric, a resin, or a combination thereof. In some embodiments the first cover insulating layer234may have a multi-layered structure. In some embodiments, some portions of the first cover insulating layer234may be disposed between the color filter layer240and the antireflective layer230. In some embodiments, the color filter layer240may contact the antireflective layer230.

In the first cover insulating layer234, a second via plug252electrically connected to the first via plug229and passing through the first cover insulating layer234may be formed. The second via plug252may extend from an upper surface of the first cover insulating layer234to a bottom surface of the first cover insulating layer234. The second via plug252may be formed as an integral part from the upper surface to the bottom surface of the first cover insulating layer234, but is not limited thereto. For example, the second via plug252may be formed in a multi-layered structure from the upper surface to the bottom surface of the first cover insulating layer234. The second via plug252may be formed of, for example, a metal or a conductive metal nitride such as copper (Cu), aluminum (Al), titanium (Ti), titanium nitride (TiN), or tungsten (W). At least some portions of the second via plug252may be formed of a transparent conductive material. In some embodiments, the second via plug252may be formed with a first portion including a metal material, and a second portion disposed on the first portion and including a transparent conductive material. The second portion of the second via plug252may form an integral part with a lower transparent electrode layer272, which will be described herein later. In this case, the second via plug252may extend from the lower transparent electrode layer272to the second surface201bof the semiconductor substrate200, and may be a portion of a conductive material electrically connecting the lower transparent electrode layer272and the first via plug229to each other.

The lower transparent electrode layer272may be formed over the first cover insulating layer234. The lower transparent electrode layer272may be formed as a plurality of parts spaced apart from each other to respectively correspond to a plurality of photoelectric conversion devices204. The lower transparent electrode layer272may be formed of, for example, a transparent conductive material such as ITO, IZO, ZnO, SnO2, antimony-doped tin oxide (ATO), Al-doped zinc oxide (AZO), gallium-doped zinc oxide (GZO), TiO2, or fluorine-doped tin oxide (FTO).

In some embodiments, the lower transparent electrode layer272may be formed by a damascene method. For example, the lower transparent electrode layer272may be formed in an upper side of the first cover insulating layer234to fill a plurality of recess spaces spaced apart from each other. A lower transparent electrode material may be formed to cover the first cover insulating layer234. Some portions of the lower transparent electrode material may be removed to expose an upper surface of the first cover insulating layer234. The lower transparent electrode layer272including a plurality of parts may be formed to respectively fill the plurality of recess spaces. An upper surface of the lower transparent electrode layer272and an uppermost surface of the first cover insulating layer234may be at a same level as each other. That is, the upper surface of the lower transparent electrode layer272and the upper surface of the first cover insulating layer234may form a flat surface and have a same height.

In some embodiments, a plurality of holes passing through at least some portions of the first cover insulating layer234may be formed from each of the recess spaces towards the substrate200. The lower transparent electrode material filling the holes and the recess spaces and covering the first cover insulating layer234may be formed. Then, a dual damascene method in which some portions of the lower transparent electrode material are removed to expose an upper surface of the first cover insulating layer234may be performed. As a result, the lower transparent electrode layer272and at least some portions of the second via plug252, which may be formed as an integral part with the lower transparent electrode layer272, may be formed. In this case, as described above, at least some portions of the second via plug252may be formed of a transparent conductive material. When the second via plug252is formed with a first portion including a metal material, a second portion may be arranged on the first portion and including a transparent conductive material. The first portion of the second via plug252may be exposed at a bottom surface of the hole during a process of forming the recess space and the hole.

The lower transparent electrode layer272may be electrically connected to the first via plug229. For example, the second via plug252may be disposed between the lower transparent electrode layer272and the first via plug229. The lower transparent electrode layer272may be electrically connected to the second via plug252, and the second via plug252may be electrically connected to the first via plug229.

An organic photoelectric layer274may be formed on the lower transparent electrode layer272. The organic photoelectric layer274may be formed as an integral part on a plurality of lower transparent electrode layers272. The organic photoelectric layer274may be formed to cross over a flat surface, including an upper surface of the lower transparent electrode layer272and an upper surface of the first cover insulating layer234which are at a same level as each other. In some embodiments, the organic photoelectric layer274may be an organic material in which photoelectric conversion only occurs at a specific light wavelength. For example, photoelectric conversion may occur in the organic photoelectric layer274only at a green light wavelength. For example, the organic photoelectric layer274may present the maximum absorption wavelength λmax in a range of about 500 nm to about 600 nm.

The organic photoelectric layer274may be formed in a single-layer or a multi-layered form in which a p-type semiconductor material and an n-type semiconductor material are formed as a p-n flat junction or a bulk heterojunction. The organic photoelectric layer274may be a layer in which an exciton is generated after receiving incident light and then the generated exciton is divided into a hole and an electron. The p-type semiconductor material and the n-type semiconductor material may each absorb light in a green wavelength band, and present the maximum absorption peak in a wavelength band of about 500 nm to about 600 nm. The p-type semiconductor material and the n-type semiconductor material may each have a bandgap of about 1.5 eV to 3.5 eV, for example, a bandgap of about 2.0 eV to about 2.5 eV. As the p-type semiconductor material and the n-type semiconductor material have the bandgap with the range described above, light in a green wavelength band may be absorbed, and, particularly, the maximum absorption peak may be presented in a wavelength band of about 500 nm to about 600 nm.

The organic photoelectric layer274may be a single-layer or a multi-layered form. The organic photoelectric layer274may be various combinations such as, for example, an intrinsic layer (I layer), a p-type layer/I layer, an I layer/n-type layer, a p-type layer/I layer/n-type layer, a p-type layer/n-type layer, or the like. The intrinsic layer (I layer) may include the p-type semiconductor compound and the n-type semiconductor compound that are mixed at a ratio of about 1:100 to about 100:1. The p-type semiconductor compound and the n-type semiconductor compound may be included at a ratio of about 1:50 to about 50:1, at a ratio of about 1:10 to about 10:1, or at a ratio of about 1:1, from among the ratios described above. As the p-type semiconductor and the n-type semiconductor compounds have a formulation ratio described above, an exciton is effectively generated and a p-n flat junction is effectively formed. A p-type layer may include the p-type semiconductor compound, and an n-type layer may include the n-type semiconductor compound.

The organic photoelectric layer274may have, for example, a thickness of about 1 nm to about 500 nm. In some embodiments, the organic photoelectric layer274may have a thickness of about 5 nm to about 300 nm. As the organic photoelectric layer274effectively absorbs light, and effectively separates and delivers holes and electrons, the organic photoelectric layer274may have a thickness capable of effectively improving photoelectric conversion efficiency.

An upper transparent electrode layer276may be formed on the organic photoelectric layer274. The upper transparent electrode layer276may be formed of, for example, ITO, IZO, ZnO, SnO2, ATO, AZO, GZO, TiO2, or FTO. The upper transparent electrode layer276may be formed as an integral part over an active pixel region APR and a black pixel region BPR. That is, the upper transparent electrode layer276may be formed as an integral part over the plurality of photoelectric conversion devices204. In some embodiments, the upper transparent electrode layer276may be formed to cover all of an upper surface and a side surface of the organic photoelectric layer274.

The upper transparent electrode layer276may be formed to extend as an integral part over the plurality of pixel regions PR. Thus, the lower transparent electrode layer272, the organic photoelectric layer274, and the upper transparent electrode layer276may be sequentially disposed over the semiconductor substrate200.

In the present specification, a transparent electrode layer including a plurality of parts that are spaced apart from each other and respectively correspond to each of the unit pixel regions (e.g., the lower transparent electrode layer272) may be referred to as a first transparent electrode layer. A transparent electrode layer formed as an integral part over the unit pixel regions (e.g., the upper transparent electrode layer276) may be referred to as a second transparent electrode layer.

The first via plug229may be electrically connected to the storage node region206. Thus, the storage node region206may be electrically connected to the lower transparent electrode layer272through the first via plug229. In some embodiments, the first via plug229may be electrically connected to the buffer layer217, and the buffer layer217may be electrically connected to the storage node region206through the contact via213.

In this regard, charge generated by photoelectric conversion that is caused by light absorbed in the organic photoelectric layer274may be stored in the storage node region206through the lower transparent electrode layer272and the first via plug229.

Since the first via plug229is in the isolation region IR, there is no need for a space for forming the first via plug229, in the unit pixel UPX. Thus, a horizontal area of the unit pixel UPX is secured, and photoelectric conversion efficiency of the image sensor100may be improved.

Furthermore, a side surface of the first via plug229is covered by the side surface insulating layer227, and thus, even when the first via plug229is disposed in the isolation region IR, an electrical and optical crosstalk between adjacent unit pixels UPX may not occur. In other words, the second device isolation layer210, the side surface insulating layer227and the first via plug229formed in the isolation region IR between adjacent pixel regions PR may collectively constitute a device isolation structure for preventing an electrical and optical crosstalk between adjacent unit pixels UPX.

A second cover insulating layer282may be formed on the upper transparent electrode layer276. The second cover insulating layer282may be formed of a transparent insulation material. The second cover insulating layer282may be formed of, for example, a silicon oxide or a metal oxide.

In some embodiments, a third cover insulating layer284may be formed on the second cover insulating layer282. The third cover insulating layer284may be formed of a transparent insulation material. The third cover insulating layer284may be formed of, for example, a silicon oxynitride. In some embodiments, the third cover insulating layer284may be omitted.

The micro lens286corresponding to the color filter layer240may be formed on the third cover insulating layer284. In some embodiments, when the third cover insulating layer284is omitted, the micro lens286may be formed on the second cover insulating layer282. The micro lens286may be formed to overlap the corresponding color filter layer240. The micro lens286may be formed as a plurality of parts to correspond to a plurality of color filter layers240. The micro lens286may change a path of light incident through a region other than the photoelectric conversion device204and then concentrate the light into the photoelectric conversion device204.

FIGS. 2A to 2Dillustrate horizontal cross-sectional views showing a method of manufacturing an image sensor according to an example embodiment, andFIGS. 3A and 3Brespectively illustrate a horizontal cross-sectional view of a portion of an image sensor according to an example embodiment and an enlarged vertical cross-sectional view showing some portions thereof. In detail,FIGS. 2A to 2D, andFIG. 3Aare horizontal cross-sectional views taken along a line A-A′ ofFIGS. 1A and 1Bin a direction parallel to the first surface201aof the semiconductor substrate200, andFIG. 3Bis a vertical cross-sectional view showing an enlarged portion taken along a line A-A′ ofFIGS. 1A and 1Band a line B-B′ ofFIG. 3A. Configuration components ofFIGS. 1A and 1Bmay also be referred to herebelow.

Referring toFIG. 2A, some portions of the semiconductor substrate200are removed to form the trench205. The trench205may extend in a vertical direction between the first surface201aand the second surface201bof the semiconductor substrate200. The trench205may be formed to surround the unit pixel UPX. In some embodiments, the trench205may be formed to be continuously connected so as to fully surround an edge of the unit pixel UPX. The trench205may be formed in the isolation region IR disposed between adjacent pixel regions PR. In some embodiments, the trench205may be formed to extend from the first surface201ato the second surface201bof the semiconductor substrate200. In some embodiments, the trench205may be formed to extend from the first surface201atowards the second surface201bof the semiconductor substrate200, but may not extend up to the second surface201b. In some embodiments, the trench205may extend from the second surface201btowards the first surface201aof the semiconductor substrate200, but may not extend up to the first surface201a.

In some embodiments, the first device isolation layer202may be formed earlier than the trench205.

Referring toFIG. 2B, the second device isolation layer210filling the trench205is formed as follows. An insulation material layer may be formed to fill the trench205and cover the semiconductor substrate200. Then, some portions of the insulation material layer, formed in a region other than an inner portion of the trench205, may be removed to form the second device isolation layer210.

In some embodiments, after the second device isolation layer210is formed, configuration components in the unit pixel UPX (e.g., the photoelectric conversion device204, the storage node region206, and the wire structure220) may be formed.

Referring toFIG. 2C, the via hole225extending from the second surface201bto the first surface201aof the semiconductor substrate200, by passing through the semiconductor substrate200, is formed. In some embodiments, the via hole225may extend from the second surface201bof the semiconductor substrate200into the wire structure220, for example, to reach the buffer layer217.

The via hole225may be formed to disconnect some portions of the second device isolation layer210surrounding the unit pixel UPX by removing some portions of the second device isolation layer210. In some embodiments, the via hole225may be formed by removing some portions of the semiconductor substrate200which are adjacent to the removed portions of the second device isolation layer210.

Referring toFIG. 2D, the side surface insulating layer227covering an inner side surface of the via hole225is formed. An insulation material layer may be formed to conformally cover an inner side and bottom surfaces of the via hole225and the second surface201bof the semiconductor substrate, and then some portions of the insulation material layer, formed in a region other than the inner side surface of the via hole225, may be removed to form the side surface insulating layer227. Thus, the side surface insulating layer227may not cover the bottom surface of the via hole225.

Referring toFIGS. 3A and 3B, the first via plug229filling the via hole225of which an inner side surface is covered by the side surface insulating layer227is formed. Next, the color filter layer240, the lower transparent electrode layer272, the organic photoelectric layer274, the upper transparent electrode layer276, the micro lens286, and the like described with reference toFIGS. 1A and 1Bmay be formed to constitute the image sensor100.

The image sensor100includes a plurality of pixel regions PR spaced apart from each other, and each of the plurality of pixel regions PR has the unit pixel UPX and the semiconductor substrate200including the isolation region IR between adjacent pixel regions PR.

The first via plug229may be disposed between the second device isolation layers210in the isolation region IR and pass through the semiconductor substrate200. The side surface insulating layer227may cover a side surface of the first via plug229to surround the first via plug229.

The first via plug229may be electrically connected to the unit pixel UPX. In detail, the first via plug229may electrically connect the lower transparent electrode layer272and the storage node region206so that, as described with reference toFIGS. 1A and 1B, charge generated by a photoelectric conversion that is caused by light absorbed in the organic photoelectric layer274may be delivered to the storage node region206in the unit pixel UPX.

Between the first via plug229and the second device isolation layer210, the side surface insulating layer227covering a side surface of the via hole225may be disposed. In a direction between two adjacent unit pixels UPX, a width of the via hole225may be greater than a width of the second device isolation layer210. In other words, between two adjacent unit pixels UPX, a total width of the side surface insulating layer227and the first via plug229(e.g., a width of the penetrating via structure227and229) may be greater than the width of the second device isolation layer210.

Thus, the unit pixel UPX may be entirely surrounded by the second device isolation layer210, the first via plug229, and the side surface insulating layer227. As a result, due to the second device isolation layer210, the first via plug229, and the side surface insulating layer227, electrical and optical crosstalk between adjacent unit pixels UPX may not occur.

The first via plug229is disposed between two adjacent unit pixels UPX and may electrically connect the lower transparent electrode layer272disposed in one of two adjacent unit pixels UPX and the storage node region206to each other.

FIGS. 4A to 4Cillustrate horizontal cross-sectional views of a portion of an image sensor according to an example embodiment.

Referring toFIG. 4A, the image sensor100aincludes the second device isolation layer210, a side surface insulating layer227a, and a first via plug229adisposed in the isolation region IR. The side surface insulating layer227amay cover an inner side surface of a via hole225a, and the first via plug229amay fill an inside of the via hole225aof which an inner side surface is covered by the side surface insulating layer227a. Between two adjacent unit pixels UPX, a width of the via hole225amay be formed to be the same as a width of the second device isolation layer210. In other words, between two adjacent unit pixels UPX, a total width of the side surface insulating layer227aand the first via plug229amay be the same as a width of the second device isolation layer210.

Referring toFIG. 4B, an image sensor100bincludes the second device isolation layer210, a side surface insulating layer227b, and a first via plug229B disposed in the isolation region IR.

A via hole225band the first via plug229B are disposed between four adjacent unit pixels UPX, and the first via plug229B may electrically connect the lower transparent electrode layer272disposed in any one of the four adjacent unit pixels UPX and the storage node region206to each other.

In other words, in the image sensor100ofFIG. 3A, the first via plug229is located at a side line of the unit pixel UPX, but in the image sensor100bofFIG. 4B, the first via plug229B may be located at a corner of the unit pixel UPX.

Referring toFIG. 4C, an image sensor100cincludes the second device isolation layer210, a side surface insulating layer227cand a first via plug229cdisposed in the isolation region IR.

The first via plug229cmay be disposed between four adjacent unit pixels UPX. A width of a via hole225cmay be formed to be the same as a width of the second device isolation layer210. In other words, a total width of the side surface insulating layer227cand the first via plug229cmay be the same as a width of the second device isolation layer210.

FIG. 5illustrates a horizontal cross-sectional view showing a method of manufacturing an image sensor according to an example embodiment, andFIGS. 6A and 6Brespectively illustrate a horizontal cross-sectional view of a portion of an image sensor according to an example embodiment and an enlarged vertical cross-sectional view showing some portions thereof. In detail,FIG. 5is a horizontal cross-sectional view showing a process after the process shown inFIG. 2B, and configuration components ofFIGS. 1A and 1Bmay also be referred to herebelow. Also,FIG. 6Bis a vertical cross-sectional view showing an enlarged portion taken along a line A-A′ ofFIGS. 1A and 1Band a line B1-B1′ ofFIG. 6A.

Referring toFIG. 5, a via hole225dextending from the second surface201bto the first surface201aof the semiconductor substrate200, by passing through the semiconductor substrate200is formed. In some embodiments, the via hole225dmay extend from the second surface201bof the semiconductor substrate200into the wire structure220, for example, up to the buffer layer217.

Between two adjacent unit pixels UPX, a width of the via hole225dmay be formed to be smaller than a width of the second device isolation layer210. That is, some portions of the second device isolation layer210may remain between a portion of the semiconductor substrate200disposed in the unit pixel UPX and the via hole225d.

In this regard, some portions of the semiconductor substrate200disposed in the unit pixel UPX are exposed through some portions of an inner side surface of the via hole225ofFIG. 2C, and the second device isolation layer210may only be exposed through an inner side surface of the via hole225dofFIG. 5.

Referring toFIGS. 6A and 6B, a first via plug229dfilling the via hole225dis formed to constitute an image sensor100d. Between two adjacent unit pixels UPX, a width of the first via plug229dmay be smaller than a width of the second device isolation layer210. A portion of the second device isolation layer210, located along an inner side surface of the via hole225d, may insulate the first via plug229dfrom the semiconductor substrate200, and thus, the side surface insulating layer227as described inFIG. 3Amay not be separately formed. In this regard, the first via plug229dand the second device isolation layer210may directly contact each other. As a result, the first via plug229dand a portion of the second device isolation layer210that covers a side surface of the first via plug229dto surround the first via plug229dmay serve as a penetrating via structure.

FIG. 7illustrates a horizontal cross-sectional view of a portion of an image sensor according to an example embodiment.

Referring toFIG. 7, in an image sensor100e, a via hole225eand a first via plug229eare disposed between four adjacent unit pixels UPX, and the first via plug229emay electrically connect the lower transparent electrode layer272disposed in one of the four adjacent unit pixels UPX and the storage node region206to each other.

FIGS. 8A and 8Billustrate horizontal cross-sectional views showing a method of manufacturing an image sensor according to an example embodiment, andFIGS. 9A and 9Brespectively illustrate a horizontal cross-sectional view of a portion of an image sensor according to an example embodiment and an enlarged vertical cross-sectional view showing some portions thereof. In detail,FIG. 8Ais a horizontal cross-sectional view showing a process after the process shown inFIG. 2A, andFIG. 9Bis a vertical cross-sectional view showing an enlarged portion taken along a line A-A′ ofFIGS. 1A and 1Band a line B2-B2′ ofFIG. 9A. Configuration components ofFIGS. 1A and 1Bmay also be referred to herebelow.

Referring toFIG. 8A, a cover isolation layer212covering an inner side surface of the trench205is formed. For example, the cover isolation layer212may have a dielectric constant of about 10 to about 25. In some embodiments, the cover isolation layer212may be formed of at least one material selected from hafnium oxide (HfO), hafnium silicon oxide (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicon oxide (ZrSiO), zirconium oxynitride (ZrON), zirconium silicon oxynitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), or lead scandium tantalum oxide (PbScTaO).

In some embodiments, the cover isolation layer212may cover both of an inner side surface and a bottom surface of the trench205.

Referring toFIG. 8B, a core isolation layer214filling the trench205of which an inner side surface is covered by the cover isolation layer212is formed, and then a second device isolation layer210aincluding the cover isolation layer212and the core isolation layer214is formed. In some embodiments, the core isolation layer214may be formed of a conductive material. The core isolation layer214may be formed of, for example, a semiconductor material such as polysilicon, at least one metal selected from Ti, Ta, Al, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, and Pd, a metal nitride including at least one metal, a metal doped with carbon, or a metal compound such as a metal nitride doped with carbon.

Referring toFIGS. 9A and 9B, in a method similar to the method described with reference toFIGS. 2C, 2D, and 3A, the via hole225, the side surface insulating layer227covering an inner side surface of the via hole225, and the first via plug229filling an inside of the via hole225of which an inner side surface is covered by the side surface insulating layer227are formed to constitute an image sensor100f.

Between the core isolation layer214of the second device isolation layer210aand the first via plug229, the side surface insulating layer227covering a side surface of the via hole225may be disposed. In other words, the side surface insulating layer227may directly contact the core isolation layer214.

In the second device isolation layer210a, the cover isolation layer212may prevent an electrical crosstalk between adjacent unit pixels UPX, and the core isolation layer214may prevent an optical crosstalk. Also, the side surface insulating layer227may prevent an electrical crosstalk between adjacent unit pixels UPX with the cover isolation layer212, and the first via plug229may prevent an optical crosstalk with the core insulating layer.

The first via plug229may be electrically connected to the unit pixel UPX. In detail, as described with reference toFIGS. 1A and 1B, the first via plug229may electrically connect the lower transparent electrode layer272and the storage node region206so that charge generated by a photoelectric conversion that is caused by light absorbed in the organic photoelectric layer274are delivered to the storage node region206included in the unit pixel UPX. Otherwise, when the core isolation layer214has conductivity, the first via plug229may be electrically connected to the unit pixel UPX.

FIGS. 10A to 10Dillustrate horizontal cross-sectional views showing a method of manufacturing an image sensor according to an example embodiment, andFIG. 11illustrates a horizontal cross-sectional view of a portion of an image sensor according to an example embodiment. Configuration components ofFIGS. 1A and 1Bmay also be referred to herebelow.

Referring toFIG. 10A, some portions of the semiconductor substrate200are removed to form a trench205a. The trench205amay be formed to surround some portions of the unit pixel UPX. In some portions of the isolation region IR, between two facing ends205E of the trench205a, some portions200G of the semiconductor substrate200may be disposed. In the isolation region IR, a distance between the two facing ends205E of the trench205a(e.g., a width of the some portions200G of the semiconductor substrate200) may be a first width200GW.

Referring toFIG. 10B, a second device isolation layer210bfilling the trench205ais formed. The second device isolation layer210bmay be formed using a similar method to the forming of the second device isolation layer210described inFIG. 2B.

Referring toFIGS. 10B and 10C, the via hole225is formed using a similar method as described with reference toFIG. 2C. When the via hole225is formed, some portions200G of the semiconductor substrate200disposed between the two facing ends205E of the trench205ain the isolation region IR may be removed. Thus, the second device isolation layer210bmay be exposed through some portions of an inner side surface of the via hole225.

In a direction in which two ends210E of the second device isolation layer210bface each other in the isolation regions IR, a width of the via hole225may be the second width225W. In some embodiments, the second width225W may be equal to or greater than the first width200GW.

Referring toFIG. 10D, the side surface insulating layer227covering an inner side surface of the via hole225is formed.

Also referring toFIG. 11, the first via plug229filling an inside of the via hole225of which an inner side surface is covered by the side surface insulating layer227is formed to constitute an image sensor100g.

The image sensor100gofFIG. 11may include the side surface insulating layer227covering a side surface of the via hole225between the first via plug229and the second device isolation layer210bin a similar manner as the image sensor100ofFIGS. 3A and 3B.

FIGS. 12A and 12Billustrate horizontal cross-sectional views showing a method of manufacturing an image sensor according to an example embodiment, andFIGS. 13A and 13Brespectively illustrate a horizontal cross-sectional view of a portion of an image sensor according to an example embodiment and an enlarged vertical cross-sectional view showing some portions thereof. In detail,FIG. 12Ais a horizontal cross-sectional view showing a process after the process shown inFIG. 10B, and configuration components ofFIGS. 1A and 1Bmay also be referred to herebelow. Also,FIG. 13Bis a vertical cross-sectional view showing an enlarged portion taken along a line A-A′ ofFIGS. 1A and 1Band a line B3-B3′ ofFIG. 13A.

Also, although not illustrated separately, a width of the via hole225may be formed to be similar to a width of the second device isolation layer210bas shown inFIG. 4A, or the first via plug229may be formed to be located at a corner of the unit pixel UPX as shown inFIGS. 4B and 4C.

Referring toFIG. 12A, the via hole225is formed in a similar method as described with reference toFIG. 10C. When the via hole225is formed, some portions200G of the semiconductor substrate200disposed between two facing ends205E of the trench205ain the isolation region IR may not be entirely removed and may remain as a remained semiconductor layer200GR. As the remained semiconductor layer200GR is a portion of the semiconductor substrate200, the remained semiconductor layer200GR may be formed of the same material as the semiconductor substrate200. In some embodiments, the second device isolation layer210bmay not be exposed through an inner side surface of the via hole225.

In a direction in which two ends210E of the second device isolation layer210bface each other in the isolation region IR, a width of the via hole225, which is a second width225Wa, may be smaller than a width between the two ends210E of the second device isolation layer210b, which is the first width200GW.

In some embodiments, one of the two ends210E of the second device isolation layer210bfacing each other with respect to the via hole225may be exposed through an inner side surface of the via hole225, and the other may not be exposed through an inner side surface of the via hole225. In this case, the remained semiconductor layer200GR may be disposed only between one of the two ends210E of the second device isolation layer210bfacing each other with respect to the via hole225and the via hole225.

Referring toFIG. 12B, the side surface insulating layer227covering an inner side surface of the via hole225is formed.

Referring toFIGS. 13A and 13B, the first via plug229filling an inside of the via hole225of which an inner side surface is covered by the side surface insulating layer227is formed to constitute an image sensor100h.

Between the first via plug229and the second device isolation layer210b, the side surface insulating layer227covering a side surface of the via hole225and the remained semiconductor layer200GR may be disposed.

In some embodiments, the remained semiconductor layer200GR may be disposed only between the via hole225and one of the two ends210E of the second device isolation layer210bfacing each other with respect to the first via plug229. In other words, the side surface insulating layer227and the remaining semiconductor layer200GR may be between the first via plug229and one of the two ends210E of the second device isolation layer210bfacing each other with respect to the first via plug229, and the side surface insulating layer227may be only between the first via plug229and the other end of the two ends210E of the second device isolation layer210b.

In addition, although not illustrated separately, a width of the via hole225may be formed to be similar to a width of the second device isolation layer210bas shown inFIG. 4A, or the first via plug229may be formed to be located at a corner of the unit pixel UPX as shown inFIGS. 4B and 4C.

FIGS. 14A to 14Cillustrate horizontal cross-sectional views showing a method of manufacturing an image sensor according to an example embodiment, andFIGS. 15A and 15Brespectively illustrate a horizontal cross-sectional view of a portion of an image sensor according to an example embodiment and an enlarged vertical cross-sectional view showing some portions thereof. In detail,FIG. 14Ais a horizontal cross-sectional view showing a process after the process shown inFIG. 10A, and configuration components ofFIGS. 1A and 1Bmay also be referred to herebelow. Also,FIG. 15Bis a vertical cross-sectional view showing an enlarged portion taken along a line A-A′ ofFIGS. 1A and 1Band a line B4-B4′ ofFIG. 15A.

Referring toFIG. 14A, a cover isolation layer212acovering an inner side surface of the trench205ais formed. In some embodiments, the cover isolation layer212amay cover both an inner side surface and a bottom surface of the trench205a.

Referring toFIG. 14B, a core isolation layer214afilling an inside of the trench205aof which an inner side surface is covered by the cover isolation layer212ais formed, and then a second device isolation layer210cincluding the cover isolation layer212aand the core isolation layer214ais formed.

Referring toFIGS. 14B and 14C, the via hole225is formed in a similar method as described with reference toFIG. 10C. When the via hole225is formed, some portions200G of the semiconductor substrate200disposed between two facing ends205Ea of the trench205ain the isolations region IR may be removed. Thus, the cover isolation layer212aof the second device isolation layer210cmay be exposed through some portions of an inner side surface of the via hole225.

In a direction in which two ends210Ea of the second device isolation layer210cface each other in the isolation region IR, a width of the via hole225may be the second width225W. In some embodiments, the second width225W may be equal to or greater than the first width200GW.

Referring toFIGS. 15A and 15B, the side surface insulating layer227covering an inner side surface of the via hole225and the first via plug229filling an inside of the via hole225of which an inner side surface is covered by the side surface insulating layer227are formed to form an image sensor100i.

The side surface insulating layer227may be disposed between the first via plug229and the second device isolation layer210c. As the second device isolation layer210cincludes the cover isolation layer212aand the core isolation layer214a, the cover isolation layer212aand the side surface insulating layer227may be disposed between the core isolation layer214aand the first via plug229.

In addition, although not illustrated separately, a width of the via hole225may be formed to be similar to a width of the second device isolation layer210cas illustrated inFIG. 4A, or the first via plug229may be formed to be located at a corner of the unit pixel UPX as illustrated inFIGS. 4B and 4C.

FIG. 16illustrates a horizontal cross-sectional view showing a method of manufacturing an image sensor according to an example embodiment, andFIGS. 17A and 17Brespectively illustrate a horizontal cross-sectional view of a portion of an image sensor according to an example embodiment and an enlarged vertical cross-sectional view showing some portions thereof. In detail,FIG. 16is a horizontal cross-sectional view showing a process after the process shown inFIG. 14B, and configuration components ofFIGS. 1A and 1Bmay also be referred to herebelow. Also,FIG. 17Bis a vertical cross-sectional view showing an enlarged portion taken along a line A-A′ ofFIGS. 1A and 1Band a line B5-B5′ ofFIG. 17A.

Referring toFIG. 16, the via hole225is formed in a similar method as described with reference toFIG. 12A. When the via hole225is formed, some portions (200G ofFIG. 14B) of the semiconductor substrate200disposed between two facing ends205Ea of the trench205ain the isolation region IR may not be fully removed and thus may remain as the remained semiconductor layer200GR. In some embodiments, the second device isolation layer210cthat is the cover isolation layer212amay not be exposed through an inner side surface of the via hole225.

In a direction in which two ends210Ea of the second device isolation layer210cface each other in the isolation region IR, a width of the via hole225, which is a second width225Wa, may be smaller than a width between two ends210Ea of the second device isolation layer210c, which is the first width200GW.

Referring toFIGS. 17A and 17B, the side surface insulating layer227covering an inner side surface of the via hole225and the first via plug229filling an inside of the via hole225of which an inner side surface is covered by the side surface insulating layer227are formed to constitute an image sensor100j.

The side surface insulating layer227and the remained semiconductor layer200GR may be disposed between the first via plug229and the second device isolation layer210c. As the second device isolation layer210cincludes the cover isolation layer212aand the core isolation layer214a, the cover isolation layer212a, the remained semiconductor layer200GR, and the side surface insulating layer227may be disposed between the core isolation layer214aand the first via plug229.

In some embodiments, the remained semiconductor layer200GR may only be disposed between the via hole225and one of two ends210Ea of the second device isolation layer210cfacing each other with respect to the first via plug229. In other words, the side surface insulating layer227and the remained semiconductor layer200GR may be between the first via plug229and one of the two ends210Ea of the second device isolation layer210cfacing each other with respect to the first via plug229, and the side surface insulating layer227may be only between the first via plug229and the other end of the two ends210Ea of the second device isolation layer210c.

Also, although not illustrated separately, a width of the via hole225may be formed to be similar to a width of the second device isolation layer210cas shown inFIG. 4A, and the first via plug229may be formed to be located at a corner of the unit pixel UPX as shown inFIGS. 4B and 4C.

FIG. 18illustrates a horizontal cross-sectional view showing a method of manufacturing an image sensor according to an example embodiment.

Referring toFIG. 18, some portions of the semiconductor substrate200are removed to form a trench205b. The trench205bmay be formed to surround some portions of the unit pixel UPX. Some portions200Ga of the semiconductor substrate200may be disposed between two facing ends205Eb of the trench205bin some portions of the isolation region IR.

Four trenches205bspaced apart from each other may be disposed around a unit pixel UPX. The four trenches205bmay be respectively arranged along four sides of the unit pixel UPX. Also, some portions200Ga of the semiconductor substrate200may be arranged close to an area between ends205Eb of trenches205bthat is a corner of the unit pixel UPX. In some portions200Ga of the semiconductor substrate200disposed close to four corners of the unit pixel UPX, the via hole225b, a side surface insulating layer227b, and a first via plug229bmay be formed as shown inFIG. 4B, or a via hole225c, a side surface insulating layer227c, and a first via plug229cmay be formed as shown inFIG. 4C.

The second device isolation layer210ofFIG. 4B or 4Cmay be formed in each of four trenches205b, or a second device isolation layer similar to the second device isolation layers210aand210cofFIG. 9AorFIG. 15Amay be formed therein.

FIG. 19illustrates a readout circuit diagram of an image sensor according to an example embodiment.

Referring toFIG. 19, OPD and B_PD share a floating diffusion region FD. Also, in another example, OPD and R_PD share the floating diffusion region FD. The floating diffusion region FD may be referred to as a floating diffusion node. In terms of pixels, a green pixel and a red pixel share the floating diffusion region FD. Also, the green pixel and a blue pixel share the floating diffusion region FD.

A readout circuit includes first and second transmission transistors TG1and TG2, the floating diffusion region FD, a reset transistor RX, a drive transistor DX, and a selection transistor SX.

The first transmission transistor TG1operates in response to a first transmission control signal TS1, the second transmission transistor TG2operates in response to a second transmission control signal TS2, the reset transistor RX operates in response to a reset control signal RS, and the selection transistor SX operates in response to a selection signal SEL.

If an activation time of the first transmission control signal TS1and an activation time of the second transmission control signal TS2are appropriately controlled, a signal corresponding to electric charge generated by B_PD or R_PD and a signal corresponding to electric charge generated by OPD may be transmitted to a column line COL, respectively, according to operations of the drive and selection transistors DX and SX.

Here, OPD, B_PD, or R_PD may be embodied as a photo transistor, a photo gate, a pinned photo diode (PPD), or a combination thereof.

For example, OPD may be configured by the organic photoelectric layer274ofFIGS. 1A and 1B. For example, B_PD or R_PD may be configured by the photoelectric conversion device204inFIGS. 1A and 1B. For example, B_PD may be configured by the photoelectric conversion device204corresponding to the first color filter layer24, as inFIGS. 1A and 1B. For example, R_PD may be configured by the photoelectric conversion device204corresponding to the second color filter layer244, as inFIGS. 1A and 1B.

In some embodiments, each of the floating diffusion region FD, the reset transistor RX, the drive transistor DX, and the selection transistor SX may be separately included in a first readout circuit that reads out electric charge generated by O_PD or R_PD and includes the first transmission transistor TG1, and included in a second readout circuit that reads out electric charge generated by the first readout circuit and OPD and includes the second transmission transistor TG2.

An image sensor according to the disclosed embodiments does not need to secure a space for forming a penetrating electrode structure in a unit pixel since the penetrating electrode structure including a via plug is disposed in an isolation region where a device isolation layer is disposed. Thus, a horizontal area of the unit pixel is secured and photoelectric conversion efficiency of the image sensor may be improved.

As the penetrating electrode structure may also play a role of the device isolation layer, an electrical and optical crosstalk between adjacent unit pixels may not occur.

As a result, an image sensor according to the disclosed embodiments may improve color reproduction and reduce a pixel size.

While the concepts have been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.