Systems and methods for monitoring and controlling binary state devices using a memory device

A static random access memory (SRAM) includes an input read register (IRR) for monitoring the state of external binary devices and an output drive register (ODR) for controlling the state of external binary devices. The SRAM can be a multi-port device for access by multiple processors or controllers. Each bit of the IRR can mirror the state of a connected external binary device, and can be read to a connected processor using a standard read instruction. Each bit of the ODR can manipulate the state of a connected external binary device by providing the device with a path to the SRAM supply voltage. Each bit of the ODR can also be read without changing the state, or interrupting the operation of, the connected external binary device. When set to the proper mode, the addresses used for the IRR and ODR can be used with the SRAM main memory array for standard memory operations.

BACKGROUND OF THE INVENTION

1. Field of the Invention

Generally, the invention relates to static random access memories (SRAMs). More specifically, the invention relates to multi-port SRAMs that include input read registers and output drive registers for controlling and monitoring binary state devices.

2. Description of the Related Art

Microprocessors and microcontrollers have become a ubiquitous part of everyday life. They can be found in virtually all types of products available today: from transportation and manufacturing equipment, to consumer electronics, household appliances and children's toys. Processors control and monitor all or part of the functionality of these products using their general-purpose input/output (GPI/O) connections. This control can typically include such things as turning binary devices on and off for functional signaling to an end-user (e.g., toggling light emitting diode power to indicate whether a product is on or off, etc.) and monitoring the state of binary devices for system oversight (e.g., checking switch state to see whether a certain product function has been selected).

However, the number of GPI/O connections available for any given microprocessor or microcontroller is limited by, among other factors, the physical size of the processor. As the system demands on the GPI/O connections increase in number, a system designer is forced to choose between competing demands, selecting some at the expense of others. If the system designer desires to facilitate more demands than a processor's GPI/O connections can accommodate, the system designer must include external circuitry or use external input/output (I/O) processors to handle the overflow or excess demands. Both of these I/O overflow solutions are time, space, power and cost inefficient.

Also used within the typical microcontroller system of today is a random access memory (RAM), particularly a static RAM, or SRAM. An SRAM is a type of read/write memory that holds its data, without external refresh, for as long as power is supplied to it. An SRAM is typically used as external cache memory for processors and controllers. Cache memory is commonly used to store and retrieve commands, instructions and/or data that are frequently needed or used by the processor. In some applications, an SRAM can also be used as the main memory of a processor. An SRAM capable of interfacing with multiple processors, for example as cache memory and/or main memory, is commonly known as a multi-port SRAM (e.g., a dual-port device interfaces with two processors, etc.).

FIG. 1illustrates a typical block diagram for a system100with multiple processors that control and/or monitor binary state devices190, among other functions, and that access a multi-port SRAM150. As shown inFIG. 1, N processors111-113are each connected to N ports121-123, respectively, of the multi-port SRAM150. Each of the N processors111-113is further connected to a variety of binary state devices190using the processors' GPI/O connections (not shown). The typical command within a processor to control a binary state device is a read/write to the GPI/O port that is coupled to that device. As an example of a limitation of the system inFIG. 1, assume that there are nine binary state devices190. Further assume that N equals 3 and that each of three processors111-113has three GPI/O connections. In this case, all nine of the binary state devices190can be controlled or monitored by the processors111-113(i.e., each of the three processors111-113can be connected to three of the nine binary state devices190).

However, with continued reference toFIG. 1, consider a further example where the number of binary state devices190in the system100exceeds the cumulative number of GPI/O connections for all of the N processors111-113(e.g., N equals one, total number of GPI/O equals three and the number of devices equals four). In this example, either additional, external means for controlling and/or monitoring the excess device(s) must be added to system100, or the excess device(s) must be eliminated from the system100. As previously discussed, adding external circuitry, such as external input/output (I/O) processors, to system100for handling the excess device(s) is time, space, power and cost inefficient. Likewise, excluding a binary state device190from control by the processors111-113may not be an option based on customer demands and system requirements.

Thus, what is needed is an external means for one or more processors to control and/or monitor binary state devices without adding additional circuit elements to the processor-based system, thus freeing up or expanding the functionality of the processors' GPI/O connections.

SUMMARY OF THE INVENTION

A static random access memory (SRAM) includes an input read register (IRR) for monitoring the state of external binary devices and an output drive register (ODR) for controlling the state of external binary devices. The SRAM can be a multi-port device for access by multiple processors or controllers. Each bit of the IRR can mirror the state of a connected external binary device, and can be read to a connected processor using a standard read instruction. Each bit of the ODR can manipulate the state of a connected external binary device by providing the device with a path to ground. Each bit of the ODR can also be read without changing the state, or interrupting the operation of, the connected external binary device. When set to the proper mode, the addresses used for the IRR and ODR can be used with the SRAM main memory array for standard memory operations.

A memory device according to further aspects of the invention can include one or more ports, with each port including an address bus, input/output control lines and input/output control logic. The memory devise can also include a memory array coupled to the one or more ports and having multiple memory locations associated with multiple memory addresses. Further the memory device can include an input read register associated with a first memory address that is coupled to the ports and to a first set of external binary device lines. The memory device can additionally include an output drive register associated with a second memory address and coupled to the ports and to a second set of external binary devices lines. The input read register of the invention can include a first set of bits that are capable of reflecting a first set of state signals associated with the first set of external binary device lines. The output drive register of the invention can include a second set of bits that are capable of reflecting a second set of state signals associated with the second set of external binary device lines and are further capable of altering the second set of state signals associated with the second set of external binary device lines.

A method according to aspects of the invention can be used for controlling states of external binary devices coupled to a memory device. This exemplary method can include a step for coupling one or more processors to the memory device. Another step can read, using the processors, to a first memory location of the memory device, wherein the first memory location includes at least one bit that reflects a first state of a first external binary device. A further step can read, using the processors, to a second memory location of the memory device, wherein the second memory location includes at least one bit that reflects a second state of a second external binary device. The method can include an additional step for writing, using the processors, to the second memory location of the memory device, wherein the bit of the second memory location controls the change of the second state to a third state of the second external binary device.

A further method according to aspects of the invention can be used for controlling states of external binary devices coupled to a memory device. This exemplary method includes a means for coupling processors to the memory device, a means for monitoring a first state of a first external binary device, and a means for manipulating a second state of a second external binary device.

A system for controlling and monitoring one or more binary state devices can include a multi-port memory device and a plurality of processors. The multi-port memory device can include a memory array coupled to a plurality of ports, the memory array having a plurality of memory locations, each memory location associate with a memory address. The multi-port memory device can further include one or more input read registers and one or more output drive registers. Each input read register can be associated with a first memory address and can be coupled to a first set of binary state devices and can have a corresponding first set of input read register bits, such that each first set bit is capable of reflecting a state of each corresponding first set device. Each output drive register can be associated with a second memory address and can be coupled to a second set of the binary state devices and can have a corresponding second set of output drive register bits, such that each second set bit is capable of reflecting a state of each corresponding second set device and is further capable of controlling the state of each corresponding second set device. Additionally, the plurality of processors can be coupled to the plurality of ports, wherein each processor is capable of executing an instruction that reads to the first memory address, and reads and writes to the second memory address.

Additional aspects of the invention will be set forth in part in the detailed description which follows, and in part will be apparent from this disclosure, or may be learned by practice of the invention. The aspects of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims. It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention as claimed.

DETAILED DESCRIPTION OF THE INVENTION

The invention will now be described in detail with reference to the drawings, which are provided as illustrative examples of the invention so as to enable those skilled in the art to practice the invention and are not meant to limit the scope of the invention. Where certain elements of the invention can be partially or fully implemented using known components, only those portions of such known components that are necessary for an understanding of the invention will be described, while detailed descriptions of other portions of such known components will be omitted so as to not obscure the invention. Further, the invention encompasses present and future known equivalents to the components referred to herein by way of illustration.

FIG. 2illustrates a generalized multi-port static random access memory (SRAM) according to some embodiments of the invention. As shown inFIG. 2, the multi-port SRAM250includes N ports121-123that are coupled to N processors111-113, respectively. As used herein, the terms processor, controller, microprocessor and microcontroller generally indicate any type of computing device or combination of devices (e.g., electronic, optical, organic, discrete, highly-integrated, etc.) capable of executing an instruction set (e.g., reduced instruction set, complex instruction set, etc.) that at least includes a read instruction and a write instruction to a memory device. Each term, whether used in the singular or plural form, is meant to indicate one or more of such computing devices or combinations of devices.

The exemplary multi-port SRAM250also includes one or more input read registers230and one or more output drive registers260. Input read registers230and output drive registers260allow for monitoring and controlling binary state devices190by any of the N processors111-113through the standard interface between processors111-113and ports121-123of the multi-port SRAM250. Any of the N processors111-113can access input read registers230and output drive registers260by simply reading or writing to the memory address associated with the register. Once a read or write request is detected to one of these registers and the appropriate read enable or write enable signal is set (discussed in further detail below), the requesting processor will be allowed to read or write to the appropriate register, thereby monitoring or controlling the binary state devices190. When not set to control or monitor binary state devices190, the addresses used for the input read registers230and output drive registers260of the present invention can be used by the SRAM main memory array for standard memory operations. The inclusion of the input read register (IRR)230and the output drive register (ODR)260frees up the processor general-purpose input/output (GPI/O) connections, or pins, for other or additional tasks, and does so without forcing the system designer to include additional I/O-handling circuitry in the design; an SRAM can be there anyway.

Some embodiments of the invention utilize the dual-port SRAM.FIG. 3illustrates a dual-port SRAM according to some embodiments of the invention. As shown inFIG. 3, two processors111,112can simultaneously utilize the dual-port SRAM350. The embodiments illustrated include an input read register (IRR)330that can capture the state of external binary state devices340, for example two external devices, and make their states available to either processor111,112. The illustrated embodiments further include an output drive register (ODR)360that can control and monitor the state of external binary state devices370, for example five external devices, and make this control and status available to either processor111,112. In some embodiments, for example, the two sets of external binary state devices340and370can include one or more of the same external binary devices; while in other embodiments, the two sets can be mutually exclusive. It will be evident to those skilled in the art after review of this disclosure that these embodiments can be readily modified for more or less than two processors, more or less than one IRR and/or one ODR, and a varying number of external binary state devices. Such modifications are intended to be within the scope of the present invention.

In some embodiments, IRR330of the invention can capture the status, or states, of external binary state devices340(e.g., switches, etc.) that are connected to the input read pins of dual-port SRAM350. IRR330can be given memory address x0000, although other addresses can be assigned without deviating from the scope of the invention. The contents of IRR330can be read as a standard memory access to address x0000 from any of the processors111,112(of which, for example only, two are shown inFIG. 3) and the data can be output via standard inputs and outputs (I/Os) of SRAM350. For example,FIG. 4illustrates an example of a two-device IRR330of the dual-port SRAM350according to some embodiments of the invention.

The embodiment of dual-port SRAM350shown inFIG. 4includes IRR330, which can be a 16-bit memory location at memory address x0000. However, embodiments of the invention are equally applicable to memories of any bit-size. The SRAM350can utilize bit0(IRR0) and bit1(IRR1) of IRR330to monitor the status of, for example, two external binary state devices: device1441and device2442, respectively. The address used by IRR330(i.e., x0000) can also be set for use by the SRAM350main memory array451for standard memory operations. Any of the processors111,112can access IRR330, and thus the status of devices441,442. However, it is not necessary to some embodiments of the present invention that every processor111,112be couple to IRR330.

For example, processor1111can execute a read command to SRAM address x0000 using address lines A0L-A12L. The states of devices441and442can be read from IRR330to input/output lines I/O0L-I/O15Lvia the address and I/O control455of SRAM350. In the example shown inFIG. 4, device1441is on, which is reflected in bit IRR0as being high or “1”. Likewise, device2442is off, which is reflected in bit IRR1as being low or “0”. Processor2112, can also access the states of the two devices441,442in a similar manner.

Table 1, below, defines the operation of embodiments of a dual-port SRAM350that includes an IRR330in accordance with the invention. As shown in Table 1, whenSFEN=VIL, IRR330is active (i.e., IRR read mode is available to the processors) and address x0000 is not available for standard memory operations. During IRR read mode of address x0000, I/O0and I/O1are valid bits and I/O2through I/O15are “don't care” bits. As will now be apparent to those skilled in the art, the invention can include a varying number of valid and “don't care” IRR bits. Writes to address x0000 are not allowed from either processor port during IRR read mode because SRAM350mirrors the on/off status of devices441and442to IRR330. When SRAM350special function enable input (SFEN)=VIH, IRR330is inactive (i.e., standard memory mode is available to the processors) and address x0000 can be used with the SRAM main memory array451for standard memory operations. This exemplary IRR330can support inputs up to approximately 3.5V (e.g., VIL<=˜0.4 V, VIH>=˜1.4 V). However, as will be evident to those skilled in the art upon review of this disclosure, varying input levels and alternative logic schemes for IRR330can also be used with aspects of some embodiments of the present invention. Such variations and alternatives are intended to be within the scope of the present invention.

In some embodiments, referring again toFIG. 3, ODR360of the invention can determine and manipulate the status, or states, of external binary state devices370(e.g., LEDs) by providing a path to VSSand/or ground for the circuit of the external devices370. The status of ODR360, and thus external devices370, can be set using standard write access from any of the processors111,112to address x0001 of SRAM350, with a “1” corresponding to “on” for the associated device and a “0” corresponding to “off”. The status of the ODR can also be read (without changing the status of the bits) via a standard read to address x0001 of the SRAM350. For example,FIG. 5illustrates a five-device output drive register (ODR)360of a dual-port SRAM350according to some embodiments of the invention.

The embodiment of dual-port SRAM350shown inFIG. 5includes ODR360, which can be a 16-bit memory location at memory address x0001. However, embodiments of the invention are equally applicable to memories of any bit-size. SRAM350can utilize bit0(ODR0) through bit4(ODR4) of ODR360to control and monitor the status of, for example, five external binary state devices: device1571through device5575, respectively. ODR360can also be used as part of the regular memory array451of SRAM350. Any of the processors111,112can access ODR330, and thus control and monitor the state of the devices571-575. However, it is not necessary to some embodiments of the present invention that every processor111,112be couple to ODR360.

For example, processor1111can execute a write command to SRAM address x0001 using address lines A0L-A12Land input/output lines I/O0L-I/O15L. Since, in this embodiment of dual-port SRAM350there are five external binary devices571-575, bits0-4of the ODR360(i.e., ODR0through ODR4) can be used to control and monitor the exemplary five devices, respectively. To turn on one of the devices, the processor writes a “1” to the corresponding bit of the ODR360for that device. When a bit of ODR360is set to “1”, ODR360can provide a path to the SRAM350supply voltage(s) and/or ground (not shown) via one of two output voltages, OVSS1and OVSS2581,581. The number and amplitude of output supply voltage(s) can vary by application. For example, the drive voltage for this exemplary ODR360might be between approximately 1.5 volts and about 3.5 volts, which can limit the total current draw of all attached devices to, for example, approximately 40 milliamps (mA) total. Likewise, to turn off one of the devices, the processor writes a “0” to that device's corresponding bit of the ODR360, which opens the output supply voltage path for that device.

The status of devices571through575can also be read from the ODR360to any of the processors111or112without affecting the state or operation of the devices. This read operation is performed in a similar manner as with IRR330. In the example shown inFIG. 5, device1571is on, which is reflected in bit ODR0as being high or “1”. Likewise, device5575is off, which is reflected in bit ODR1as being low or “0”. Further, a processor could change the on/off status of devices1and5571,575by executing a write to address x0001 of the SRAM350that changes the state of ODR0to low or “0” and the state of ODR1to high or “1”. Processor2112, can also control and monitor the states of devices571through575in a similar manner.

Table 2, below, defines the operation of embodiments of a dual-port SRAM350that includes an ODR360in accordance with the invention. As shown in Table 2, whenSFEN=VIL, ODR360is active (i.e., ODR read/write mode is available to the processors) and address x0001 is not available for standard memory operations. During ODR read/write mode of address x0001, I/O0through I/O4are valid bits and I/O5through O/O15are “don't care” bits. As will now be apparent to those skilled in the art, the invention can include a varying number of valid and “don't care” ODR bits. In this mode, writes to address x0001 are allowed from any of the processors111or112when R/W=“L”, and reads are allowed when R/W=“H”. WhenSFEN=VIH, ODR360is inactive (i.e., standard memory mode is available to the processors) and address x0001 can be used with the SRAM main memory array451for standard memory operations. However, as will be evident to those skilled in the art upon review of this disclosure, varying input/output levels and alternative logic schemes for ODR360can also be used with aspects of some embodiments of the present invention. Such variations and alternatives are intended to be within the scope of the present invention.

FIG. 6illustrates a functional block diagram600with signal routing for a dual-port SRAM according to some embodiments of the invention. As shown in exemplaryFIG. 6, the block diagram600of the exemplary dual-port SRAM can include some blocks of the typical dual-port SRAM, for example: memory array651; address decoders652L/R; I/O control653L/R; I/O logic654L/R; and arbitration, interrupt and semaphore logic658. Further, the signal pins of this exemplary SRAM can include some typical signal, for example:CEL/R;OEL/R; and R/WL/R. However, an SRAM according to the present invention can also include the IRR/ODR functional block330/360, which uses the signalsSFEN, IRR0-1and ODR0-4.

Although embodiments of the present invention have been particularly described with reference to embodiments thereof, it should be readily apparent to those of ordinary skill in the art that various changes, modifications and substitutes can be made without departing from the spirit and scope of the invention. Such changes, modifications and substitutes are intended to be within the scope of the claimed invention. Accordingly, it will be appreciated that in numerous instances, some features of the invention will be employed without a corresponding use of other features. Further, those skilled in the art will understand that variations can be made in the number and arrangement of components illustrated in the above figures. For example, while specific reference is made to a static random access memory device, other memory types can also employ embodiments of the invention described herein. Additionally, while the processors used in the above examples are impliedly external to the memory device, those skilled in the art will recognize that a single integrated circuit chip might contain multiple processor cores as well as the memory device of the present invention (i.e., a system-on-a-chip). Further, some simple controllers that do not include GPI/O pins can now be given that I/O functionality by implementing embodiments of the invention. It is intended that the scope of the appended claims include such changes, modifications and substitutions.