Numerically controlled oscillator (NCO) output clock phase smoothing

A system and method for performing output clock phase smoothing. A phase smoothing circuit is described and includes a numerically-controlled oscillator (NCO) configured to produce a plurality of NCO clock pulses at a selectable frequency that is based on an input clock. Edges of the plurality of NCO clock pulses are aligned to edges of the input clock. A phase error calculation module is coupled to the NCO and is configured to generate a corresponding phase error for each of the plurality of NCO clock pulses. A clock phase selectable delay is coupled to the phase error calculation module and is configured to adjust each of the plurality of NCO clock pulses according to the corresponding phase error to generate an output clock at the selectable frequency that are phase-adjusted to more closely match an ideal output clock phase. Edges of the output clock need not necessarily align to the edges of the input clock.

BACKGROUND OF THE INVENTION

1. Field of the Invention

Embodiments of the present invention relate to the field of numerically-controlled oscillators. More particularly, embodiments of the present invention relate generally to minimizing jitter in a clock generated by a numerically-controlled oscillator.

2. Related Art

Numerically-controlled oscillators (NCOs) are digital circuits that are commonly used for clock frequency synthesis and control based on an accumulator and control register. An NCO's output clock average frequency can be made to be arbitrarily accurate over some duration that includes many output clock cycles. Frequency precision is determined by the input clock frequency and NCO accumulator width. In particular, NCOs are often used in digital PLL implementations and are analogous in function to voltage-controlled oscillators (VCOs) in analog PLLs. NCOs have a advantage over analog VCOs in that the frequency output can be controlled exactly and there are not the inherent issues of noise, drift, etc, that are present with VCOs.

However NCOs, being digital in nature, do suffer from jitter induced by the time discretization of clock phase. That is, any leading edge of a clock pulse of an NCO clock signal is constrained to align with the occurrence of an input clock edge. Therefore, the time from one NCO clock edge to the next can vary by one input clock period. While the average frequency of the NCO clock can be made as precise as desired, there is always jitter on the clock that is equal to the period of the input clock.

SUMMARY OF THE INVENTION

Specifically, in one embodiment, a phase smoothing system is described that includes a numerically-controlled oscillator (NCO) configured to produce a plurality of NCO clock pulses at a selectable frequency that is based on an input clock. Edges of the plurality of NCO clock pulses are aligned to edges of the input clock. A phase error calculation module is coupled to the NCO and is configured to generate a corresponding phase error for each of the plurality of NCO clock pulses. A clock phase selectable delay is coupled to the phase error calculation module and is configured to adjust the phase of each of the plurality of NCO clock pulses according to the corresponding phase error to generate an output clock at the selectable frequency. Edges of the output clock are adjusted according to the phase error to better approximate the ideal phase and need not necessarily align to the edges of the input clock.

DETAILED DESCRIPTION OF THE INVENTION

Reference will now be made in detail to the preferred embodiments of the present invention, a system and method for minimizing jitter in a clock generated by an NCO, examples of which are illustrated in the accompanying drawings.

Accordingly, various embodiments of the present invention disclose a system and method for performing NCO output clock phase smoothing. Embodiments of the present invention provide the above accomplishments and further provide for minimizing jitter in a output clock signal generated by an NCO.

The following detailed description is of example embodiments of the presently claimed invention with references to the accompanying drawings. Such description is intended to be illustrative and not limiting with respect to the scope of the present invention. Such embodiments are described in sufficient detail to enable one of ordinary skill in the art to practice the subject invention, and it will be understood that other embodiments may be practiced with some variations without departing from the spirit or scope of the subject invention.

Notation and Nomenclature

Embodiments of the present invention can be implemented on hardware or software running on a computer system in conjunction with an imaging system, such as an LCD display (e.g., television display). The computer system can be a personal computer, notebook computer, server computer, mainframe, networked computer, workstation, and the like. This software program is operable for providing NCO clock phase smoothing. In one embodiment, the computer system includes a processor coupled to a bus and memory storage coupled to the bus. The memory storage can be volatile or non-volatile and can include removable storage media. The computer can also include a display, provision for data input and output, etc.

Some portions of the detailed descriptions which follow are presented in terms of procedures, steps, logic blocks, processing, and other symbolic representations of operations on data bits that can be performed on computer memory. These descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. A procedure, computer executed step, logic block, process, etc., is here, and generally, conceived to be a self-consistent sequence of operations or instructions leading to a desired result. The operations are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated in a computer system. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

NCO Clock Phase Smoothing

Embodiments of the present invention implement an NCO clock for the purpose of deriving a secondary clock from a primary clock that exhibits minimal jitter. In particular, embodiments of the present invention are capable of reducing the jitter on the output of the NCO clock when compared to the jitter produced by the discretization produced by conventional NCO clock outputs.

FIG. 1is a block diagram of a phase smoothing system100that is capable of minimizing the jitter of a clock produced by an NCO, in accordance with one embodiment of the present invention. The NCO clock jitter is reduced by the addition of a clock phase selectable delay module following the NCO110. The NCO clock jitter is reduced from one clock period of the input clock in conventional NCO systems by a selectable factor, L, described more fully below.

The phase smoothing system100comprises an NCO110that is configured to produce an NCO clock180comprising a plurality of NCO clock pulses at a selectable frequency. The NCO clock is based on an input clock160and a reference input, the frequency control input150. While the NCO clock180generates a very precise average clock frequency, the NCO clock180exhibits clock cycle-to-cycle jitter at this point. That is, edges (e.g., leading edges) of the plurality of NCO clock pulses of the NCO clock180are aligned to the edge of the input clock160. As such, the resulting jitter is equal to the period of the input clock160, Tckin, for example.

In one embodiment, the NCO110comprises an accumulator140that is configured to receive the input clock160and provide a previous accumulated value (e.g., N−1) at a leading edge of the input clock. The output of the accumulator is sent to the summation block and the phase error calculation module130. For purposes of illustration, embodiments of the present invention are described as being triggered upon leading edges of the input clock160. However, other embodiments are well suited to being triggered upon falling edges of the input clock160.

The summation block120is coupled to the accumulator140and is configured to sum the previous accumulated value (e.g., N−1) with the frequency control input150at the edge of the input clock. The summation block120generates a next previous accumulated value (e.g., N) for storing in the accumulator140.

As a result, the accumulator140continually sums a stored value with the frequency control input150at each leading edge of the input clock. As a result, the accumulator140is capable of producing the plurality of NCO clock pulses of the NCO clock180. In particular, in one embodiment the accumulator140generates an NCO clock pulse (e.g., N−1) based upon the accumulated value in the accumulator. In one embodiment, accumulator140generates the NCO clock pulse based on a bit of the accumulated value. In another embodiment, accumulator140generates the NCO clock pulse based on a most significant bit (MSB) of the accumulated value outputted by the accumulator140. In still another embodiment, accumulator140generates the NCO clock pulse when the MSB is 1.

In particular, the average output frequency of the NCO110is given in Equation 1, as follows:

In equation 1, the term,fNCO∈, refers to the NCO output180average frequency in Hz. Also, the term, fCLKIN∈, refers to the input clock160frequency in Hz. The term, MNCO∈, refers to the accumulator140magnitude, which in one embodiment is a power of 2 (e.g., MNCO=2N) Also, the term, N∈, refers to the number of bits in the accumulator140. The term, Δ∈, refers to the NCO frequency control input150.

The NCO110also comprises a phase error calculation module130. In one embodiment, the phase error calculation module is coupled to the accumulator140and is configured to receive the outputs (e.g., N−1) of the accumulator140. For each pulse of the NCO clock180, the phase error calculation module is configured to generate a corresponding phase error.

In particular, the phase error calculation module130generates a select input, SCOMP135, that represents the corresponding phase error of the NCO clock pulse (e.g., N−1). This select input is used to generate a phase delay applied to the NCO clock pulse in order to reduce the jitter of the NCO clock180.

In one embodiment, the phase error calculation module130is configured to determine a phase error of the NCO clock pulse (e.g., N−1) generated by the accumulator140. The phase error is determined by comparing the actual phase of the NCO clock pulse to a phase of an ideal NCO clock at the selectable frequency, as will be described more fully below. Additionally, the phase error is based on fractional bits of the accumulated value in the accumulator140, in one embodiment, or a combination of the accumulated value in the accumulator140and the frequency control input150, in accordance with another embodiment.

In one embodiment, a delay pipeline is introduced after the phase error calculation module. The delay pipeline comprises at least one phase of the clock input and is applied to the output clock190uniformly. The delay pipeline is introduced to allow for the phase error calculation module130to execute its calculations, in one embodiment.

The phase smoothing system100also comprises a clock phase selectable delay170that is coupled to the phase error calculation module130. The clock phase selectable delay170is configured to adjust each of the plurality of NCO clock pulses of the NCO clock180according to its corresponding phase error (e.g., the select inputs generated by the phase error calculation module130) to generate an output clock with reduced jitter at the selectable frequency. In particular, the leading edges of the output clock need not necessarily align to the leading edges of the input clock. More specifically, edges of the output clock are phase-adjusted to more closely approximate the ideal output phase and need not necessarily align to the edges of the input clock.

In particular, the phase error of an NCO clock pulse generated by the NCO110is determined below. At any given time, the value of the accumulator140may be considered to represent the phase of the NCO clock pulse (e.g., N−1) in a digital format, as represented by Equation 2, below:

In equation 2, A(t) is the instantaneous value of the accumulator140. Since the NCO clock180is the MSB of the accumulator140, in one embodiment, this can be considered a gross approximation of the true phase, which is accurate to 180 degrees of resolution.

From equation 1, the incremental normalized phase change of the accumulator is given by Equation 3, below:

This is also the upper bound of the phase error when an NCO clock edge occurs. At every edge of the NCO clock180, the normalized phase error of the corresponding NCO clock pulse is given by Equation 4, below:
0≦φERRNCO<∂φNCO(4)

Additionally, the actual phase of the corresponding NCO clock pulse can also be determined from the fractional bits of the accumulator140, in one embodiment. The fractional bits (AFRAC) is all the values less the MSB in the accumulator140. The actual phase is given by Equation 5, below:

The actual phase is used to remove the phase error caused by the discretization of the edge of the NCO clock180, in one embodiment. In particular, Equation 5 represents the normalized phase error, which is the difference between the ideal clock edge (e.g., 0 degrees) and the actual phase of the NCO clock pulse of the NCO clock180generated by the NCO110. This is normalized to the NCO clock frequency. However, since this phase error is bounded per Equation 4, compensation for the phase error is only necessary within this boundary. As such, the phase error is expressed as a normalized error with respect to the input clock period in Equation 6, below:

FIG. 3is a timing diagram300illustrating the timing of signals generated by the system100, in accordance with one embodiment of the present invention. For instance,FIG. 3illustrates the timing of the clock input signal (CLKIN)310. Also, the actual NCO clock (NCO CLK)320is shown. In one embodiment, actual NCO CLK is analogous to the NCO clock180ofFIG. 1. In addition,FIG. 3also illustrates the compensated NCO clock (NCO CLK)340that compensates for the phase error produced by the NCO110.

In particular, the phase error calculated in Equation 6 illustrates the difference in phase between the ideal NCO CLK320and the actual clock pulse of the NCO CLK330. For example, the difference is shown by the φERRCLK350.

The normalized error (e.g., φERRCLK350) calculated in Equation 6 represents a “lag” in the actual phase of the actual NCO CLOCK330. This lag occurs since an error of zero implies that the NCO clock edge of the actual NCO CLK330occurs exactly where it should have ideally in the ideal NCO CLK320. As such, a positive error indicates that the actual NCO clock edge from the actual NCO CLK330occurs later than ideally by an amount that is equal to the phase error calculated in Equation 6. In one embodiment, to compensate for this phase error calculated in Equation 6, it is necessary to add phase delay that is one minus the phase error, as calculated below in Equation 7:
φCOMP=1−φERRCLK(7)
The compensated phase error calculated in Equation 7 is shown as φCOMP360inFIG. 3.

In addition, as shown inFIG. 3, the phase delay of the NCO phase compensation can be made constant, as shown below in Equation 8:
φTOTAL=φEERCLK+φCOMP=1 (=TCLKIN)  (8)
The total phase, φCOMP370, is also shown inFIG. 3as being constant. As shown in Equation 8, regardless of the phase error introduced by the discretization of the NCO110, this phase error is removed by the compensation scheme to produce a fixed phase delay, with minimal, or no jitter.

Turning now toFIG. 2, a block diagram of the clock phase selectable delay (CPSD) module170is illustrated in more detail, in accordance with one embodiment of the present invention. The CPSD module170produces phased-delayed versions of the NCO clock pulse (e.g., N−1) of the NCO clock180based on select inputs, Scomp135, outputted by the phase error calculation module.

The CPSD module170produces the phase compensation in Equation 7. The CPSD module170comprises a delay-locked loop (DLL)240that is configured to receive the input clock160. In particular, the DLL240locks the input clock160to L equal phases, in one embodiment. That is, the DLL locks the input clock160such that L equal phases of the period, Tckin, of the input clock160is represented by the delay stages in the buffer string245as shown by buffer L.

In particular, the input clock160is continually locked by the phase frequency detector (PFD)247and the charge pump249. That is, the PFD247is coupled to the string of buffers245and is configured to calculate a difference error when the L equal phases do not equal the input clock period, Tckin. Further, the charge pump249is coupled to the PFD247and is configured to correct for the difference in order to lock the string of buffers245to the input clock, which yields L equally spaced phases over the input clock period, Tckin.

In addition, the CPSD module170comprises a voltage controlled delay line (VCDL)230that is coupled to the accumulator140. The VCDL230is configured to receive the plurality of NCO clock pulses of the NCO clock180. In addition, the VCDL230is configured to generate L equal phases of the input clock period, Tckin. That is, the DLL240generates a controlled voltage260which controls the voltage across the delay stages of the buffer string235represented by buffer L in the VCDL230.

The VCDL235has identical and matching delay stages in buffer string235as the buffer string245in the DLL240. As such, the VCDL230forms a delay line whose delay is exactly equal to one input clock period, Tckin, and whose phases are each represented by Tckin/L.

The CPSD module170also comprises a multiplexer190that is coupled to the phase error calculation module130. The multiplexer is configured to receive the corresponding phase error of an input NCO clock pulse (e.g., N−1) and to select an appropriate phase delay based on the corresponding phase error. The appropriate phase delay is applied to the corresponding NCO clock pulse (e.g., N−1) of said plurality of NCO clock pulses to generate the output clock190.

In particular, the NCO clock pulse (e.g., N−1) is passed through the VCDL230with the appropriate phase delay selected from the select signal Scomp135, as previously described. That is, the multiplexor selects the appropriate tap point in the buffer string235to add the appropriate phase delay to the NCO clock pulse (e.g., N−1) to reduce jitter, in one embodiment.

In one embodiment, since there is a discrete number of phase selections available, the phase compensation of Equation 7 is modified in Equation 9 to generate SCOMP135.

SCOMP=ϕERRCLK⁢L=AFRACΔ⁢L(9)
In Equation 9, SCOMPis truncated to the nearest integer value, in one embodiment. As seen inFIG. 2, a lower value of SCOMPselects a larger phase delay to implement the inverse relationship of Equation 7. In embodiments of the present invention, L can be varied to increase the number of phase taps in the delay line of the buffer string235in order to meet jitter requirements of the overall system.

In another embodiment, the output clock190is designed to be glitchless. In particular, the select input SCOMPis changed only when all of the elements of the VCDL buffer string235are at the same value (e.g., all low). When the multiplexer220is glitchless under these conditions, jitter in the output clock190is minimized, and glitchless, in on embodiment.

FIG. 4is a flow diagram400illustrating steps in a method for providing phase smoothing to an NCO clock, in accordance with one embodiment of the present invention. That is, the present embodiment minimizes jitter in an output clock generated by an NCO.

At410, the present embodiment produces a plurality of NCO clock pulses at a selectable frequency that is based on an input clock. In particular, the NCO110produces the plurality of NCO clock pulses at the selectable frequency. Leading edges of the plurality of NCO clock pulses are aligned to leading edges of the input clock.

More particularly, at a leading edge of the input clock, the present embodiment sums a previous accumulated value with a frequency control input to generate a current accumulated value. The current accumulated value comprises the next previous accumulated value for the next cycle introduced by the next leading edge of the input clock.

Also, the present embodiment generates an NCO clock pulse of the plurality of NCO clock pulses when a MSB of the previous accumulated value is 1. That is, whenever the MSB of the accumulated value in the accumulator140ofFIG. 1asserts a value of 1, the accumulator generates an NCO clock pulse (e.g., N−1).

At420, the present embodiment determines a corresponding phase error for each of the plurality of NCO clock pulses. In particular, the phase error calculation module130determines the phase error. The phase error is calculated by comparing the actual phase of a corresponding NCO clock pulse to an ideal phase of an ideal NCO clock of the selectable frequency.

In particular, the present embodiment determines a normalized phase error of the NCO clock pulse based on fractional bits of the previous accumulated value and the frequency control input. The normalized phase error is compensated by subtracting the normalized phase error from 1 to generate the corresponding phase error of the corresponding NCO clock pulse.

At430, the present embodiment applies the corresponding phase error to each of the plurality of NCO clock pulses. In particular, the CPSD module170applies the corresponding phase error to generate an output clock at the selectable frequency, which minimizes jitter. In particular, leading edges of the output clock need not necessarily align to leading edges of the input clock.

In particular, the present embodiment forms a delay line comprising L tap points that correspond to L equal phases of the input clock, for example in a VCDL. That is, the input clock is locked to L equal phases, for example in a DLL that controls the VCDL. After receiving the NCO clock pulse, the present embodiment is capable of selecting an appropriate tap point in the delay line based on the corresponding phase error to apply an appropriate phase delay to the corresponding NCO clock pulse. Thereafter, the present embodiment is capable of outputting the corresponding NCO clock pulse with the appropriate phase delay as part of the output clock.

In summary, the method of flow diagram400uses a CPSD module170, which is made up of a DLL240which controls a VCDL230. The CPSD module170produces L equally spaced delays of the input clock period, Tckin, which is selected by a select input to the CPSD module170. The appropriate delay is selected based on the NCO fractional bits on every NCO clock output. The output of the CPSD function is the output clock delayed by i*Tckin, wherein i=0, 1, . . . , L−1. As such, this has the desired effect of reducing the NCO clock jitter from Tckinto Tckin/L, in one embodiment.

Accordingly, various embodiments of the present invention disclose a system and method for performing NCO output clock phase smoothing. Embodiments of the present invention provide the above accomplishments and further provide for minimizing jitter in a output clock signal generated by an NCO.