Removal of a reinforcement ring from a wafer

A method of removing a reinforcement ring from a wafer is described. The method includes forming a ring-shaped recess in a first surface of the wafer and separating the reinforcement ring from an inner region of the wafer along the ring-shaped recess.

CROSS-REFERENCE TO RELATED APPLICATION

This Utility Patent Application claims priority to German Patent Application No. 10 2016 110 378.0, filed Jun. 6, 2016, which is incorporated herein by reference.

BACKGROUND

This disclosure relates in general to the technique of wafer processing, and more particularly to the technique of separating a ring-shaped reinforcement part from the wafer. Wafer handling is a challenging task, in particular if the wafer has a large diameter, is small in thickness or includes micromechanical structures which are shock-sensitive and/or may reduce the stability of the wafer. Inadvertent wafer damage or wafer fragmentation may cause a significant loss in production yield and reduces the cost efficiency of the overall manufacturing process. On the other hand, overly cautious wafer handling is costly and time consuming. Hence, safe, cost-effective and reliable wafer handling is a key aspect in modern wafer processing technology.

SUMMARY

Various embodiments pertain to a method of removing a reinforcement ring from a wafer. The method may include forming a ring-shaped recess in a first surface of the wafer; and separating the reinforcement ring from an inner region of the wafer along the ring-shaped recess.

Various embodiments pertain to a wafer, the wafer including a reinforcement ring extending along a periphery of the wafer. The wafer may further include a ring-shaped recess in a first surface of the wafer and a usable area of the wafer surrounded by the ring-shaped recess. An inner periphery of the ring-shaped recess neighbors the usable area of the wafer.

DETAILED DESCRIPTION

Further, as employed in this specification, the terms “bonded”, “attached”, “connected”, “coupled” and/or “electrically connected/electrically coupled” are not meant to mean that the elements or layers must directly be contacted together; intervening elements or layers may be provided between the “bonded”, “attached”, “connected”, “coupled” and/or “electrically connected/electrically coupled” elements, respectively. However, in accordance with the disclosure, the above-mentioned or similar terms may, optionally, also have the specific meaning that the elements or layers are directly contacted together, i.e. that no intervening elements or layers are provided between the “bonded”, “attached”, “connected”, “coupled” and/or “electrically connected/electrically coupled” elements, respectively.

Further, the word “over” used with regard to a part, element or material layer formed or located “over” a surface may be used herein to mean that the part, element or material layer be located (e.g. placed, formed, deposited, etc.) “indirectly on” the implied surface with one or more additional parts, elements or layers being arranged between the implied surface and the part, element or material layer. However, the word “over” used with regard to a part, element or material layer formed or located “over” a surface may also have the specific meaning that the element or material layer be located (e.g. placed, formed, deposited, etc.) “directly on”, e.g. in direct contact with, the implied surface. The same applies analogously to the terms “under”, “below”, “beneath”, etc.

The wafer described herein may be of various materials, among them crystalline, polycrystalline or amorphous materials. By way of example, the wafer may be of a semiconductor material, such as, e.g., Si, SiC, SiGe, GaAs, GaN, AlGaN, InGaAs, InAlAs, etc, and, furthermore, may contain inorganic and/or organic materials that are not semiconductors.

The term “wafer” as used in this disclosure may have a broad meaning. It may, e.g., denote a monocrystalline, polycrystalline or amorphous plate of a semiconductor material. Such bulk semiconductor wafers are known to be used in semiconductor device fabrication. Further, the term “wafer” may refer to a multi-layer structure or stacked structure using one or more semiconductor plates and, e.g., one or more insulating material plates (e.g. glass plates) bonded together to provide a multi-layer structure. It is to be noted that the wafer may be processed by typical wafer processing steps used in wafer processing technologies, e.g. doping, depositing insulating layers, depositing conducting layers, structuring insulating or conducting layers, etc.

The wafer may comprise integrated circuits (IC) and/or microelectromechanical structures (MEMS) formed at least in one of its main surfaces. After wafer processing for generating the ICs and/or MEMSs, the semiconductor wafer is divided into single chips (dies).

The wafer may comprise bonding pads (chip electrodes) to allow electrical contact to be made with the ICs or MEMSs included in the wafer. The bonding pads may include one or more metal layers which are applied to the semiconductor material of the wafer. The metal layers may be manufactured with any desired geometric shape and any desired material composition. The metal layers may, for example, be in the form of a layer or land covering an area. By way of example, any desired metal capable of forming a solder bond or diffusion solder bond, for example Cu, Al, Au, Ni, AlCu, NiSn, Ag, Pt, Pd, In, Sn, and an alloy of one or more of these metals may be used as the material. The metal layers need not be homogenous or manufactured from just one material, that is to say various compositions and concentrations of the materials contained in the metal layers are possible.

The integrated circuits (ICs) described herein may be of different type and may include, for example, monolithic integrated electrical, electro-optical or electro-mechanical circuits or passives. The integrated circuits may, for example, be designed, e.g., as logic integrated circuits, analog integrated circuits, mixed signal integrated circuits, power integrated circuits, memory circuits, level shifters, drivers, microcontrollers, batteries or integrated passives such as, e.g., so-called PID (passive integrated device).

The wafer described herein may further include MEMSs. The MEMSs may be of different type and may include, for example, holes, recesses, membranes, cantilevers or other resilient, rotatable or displaceable micromechanical elements. By way of example, the MEMSs may form a microphone, an acceleration sensor, a position sensor, a pressure sensor, a gas sensor, a speaker, etc.

FIG. 1illustrates an exemplary method of removing a reinforcement ring from a wafer. At S1, a ring-shaped recess is formed in a first surface of the wafer. This recess may decrease the remaining thickness of the wafer to a value which allows an easy separation of the reinforcement ring from the wafer by a subsequent reinforcement ring removal processes. Further, the recess may create a spacing between a dicing tape e.g. covering the first surface of the wafer and the recessed wafer material. The spacing may protect the dicing tape from damage which otherwise could occur during separating the reinforcement ring from the wafer during reinforcement ring removal.

At S2, the reinforcement ring is separated from an inner region of the wafer along the ring-shaped recess. Separating of the reinforcement ring may be performed by using conventional wafer processing techniques such as wafer processing techniques used for generating MEMS structures (e.g. holes, recesses, membranes, cantilevers, etc.) in the wafer.

FIGS. 2A-2Dillustrate cross-sectional views of stages of an exemplary process of generating a reinforcement ring and a ring-shaped recess on a wafer in accordance with various embodiments.

FIG. 2Aillustrates a semiconductor wafer100. The semiconductor wafer100has a first surface101and a second surface102opposite the first surface101. The semiconductor wafer100may be of any semiconductor material, e.g. the semiconductor materials mentioned above. The semiconductor wafer100may, e.g., be made of a monocrystalline semiconductor material.

The semiconductor wafer may have a disc-like shape. The diameter of the semiconductor wafer may, e.g., be equal to or greater than 200 mm, 220 mm, 240 mm, 260 mm, 280 mm, 300 mm, 320 mm, 340 mm, 360 mm, 380 mm, or 400 mm. The thickness T of the semiconductor wafer100may be equal to or greater than 200 μm, 300 μm, 400 μm 500 μm, 600 μm, 700 μm, 800 μm, 900 μm, or 1000 μm. The semiconductor wafer100may be made of a bulk semiconductor material or may, e.g. be made of a multi-layer structure comprising at least one layer of semiconductor material.

The semiconductor wafer100may be subjected to (front-end) semiconductor wafer processing. Semiconductor wafer processing may include the generation of integrated circuits (ICs) in the second surface102of the semiconductor wafer100. The second surface102of the semiconductor wafer100may thus be referred to as the front side of the semiconductor wafer100. Wafer processing may include doping, oxide layer forming, metallization layer forming, layer structuring and any other process known in semiconductor technology to form integrated circuits such as, e.g., micro-controllers, memories, logic circuits, etc. Wafer processing is schematically indicated inFIG. 2Aby arrows WP.

The wafer100may then optionally be flipped and a reinforcement ring110may be formed.FIG. 2Billustrates the semiconductor wafer100after the reinforcement ring110has been formed at the wafer100. The reinforcement ring110may be formed, e.g., by thinning the first surface101(backside) of the wafer anywhere except at a peripheral ring-shaped region. This peripheral ring-shaped region then forms the reinforcement ring110of the wafer100.

Before thinning the wafer100, a protective layer (not shown) may be applied to the second surface102(front side) of the wafer100to protect the (e.g. already processed) front side of the wafer100during the thinning process.

The reinforcement ring110adds stability and rigidity to the wafer100. The reinforcement ring110allows the wafer100to be handled or manipulated at a much lower risk of damage than without reinforcement ring110(and same thickness as generated by thinning). The reinforcement ring110is also known in the art as a TAIKO-ring (registered trademark) in the art. Analogously, a wafer100having an inner thinned region and a peripheral reinforcement ring110is often referred to as a TAIKO-wafer in the art.

The reinforcement ring110may have the same thickness T as the initial wafer100. A thinned region101asubjected to the thinning process may have a substantial smaller thickness Tg. The thickness Tg may be equal to or greater than or less than 150 μm, 200 μm, 250 μm, 300 μm, 350 μm, 400 μm, 450 μm, or 500 μm.

A maximum lateral dimension L of the reinforcement ring110may be equal to or greater 1 mm, 2 mm, 3 mm, 4 mm, 5 mm, 6 mm, 7 mm, 8 mm, 9 mm, or 10 mm. It is to be noted that the reinforcement ring110may have but does not need to have a (top view) circular shape. By way of example, it also may have a polygonal shape or any other suitable shape. L may thus denote the maximum lateral dimension of the reinforcement ring110.

The reinforcement ring110may, e.g., continuously surround the thinned region101aof the wafer100. That is, the reinforcement ring110may be a closed ring structure, i.e. a ring structure without any interruptions or gaps dividing the ring into several spaced-apart segments.

The thinning of the wafer100in the thinned region101amay, e.g., be performed by grinding the backside (first surface101) of the wafer100. Wafer grinding is known in the art and a detailed description thereof can therefore be omitted.

It is to be noted that the reinforcement ring110has to be removed from the thinned inner region101aof the wafer100at a later stage of the manufacturing process. Removal of a reinforcement ring110may be difficult or even impossible if the thickness Tg of the thinned region101ais equal to or greater than a certain limit. The following disclosure, inter alia, points out approaches to safely remove the reinforcement ring110from the wafer100.

Referring toFIG. 2C, a resist120may be applied onto a part or the entirety of the first surface101, and in particular onto the thinned region101athereof.

Referring toFIG. 2D, a pattern may be formed in the resist120by performing a patterning process. By way of example, a photomask150may be positioned over the first surface101of the wafer100and is aligned with the position of the wafer100. The photomask150may be provided with a ring-shaped opening151designed in accordance with the shape of a ring-shaped recess to be formed in the first surface101(or, more particularly, in the thinned region101a) of the wafer100. The photomask150may optionally be further equipped with openings152of a shape commensurate with a desired shape of circuit structures to be formed in the first surface101(or, more particularly, in the thinned region101a) of the wafer100. The circuit structures to be formed in the first surface101may, e.g., be MEMS structures such as, e.g., holes, recesses, membranes, cantilevers or other resilient, rotatable or displaceable micromechanical elements.

Then, exposure and development may be performed to transfer the mask pattern of the photomask150to the first surface101of the wafer100. Openings122corresponding in shape to the openings152of the photomask150are formed in the resist120. Further, a ring-shaped opening121corresponding in shape to the ring-shaped opening151of the photomask150is formed in the resist120.

As an alternative to the above-described process of using the same photomask150for generating the ring-shaped opening121and the openings122(for producing the circuit structures) it is also possible to use different photomasks150. Further, it is possible to generate the openings122by a stepper process in which exposure of the resist120to produce the openings122is performed sequentially across a set of partial zones of the thinned region101aof the first surface101. However, using a common photomask150, as described above, may facilitate the alignment step and may reduce the process time needed for the overall patterning process.

After patterning of the resist120, the ring-shaped recess (not shown inFIG. 2D) and, e.g., the circuit structures (if any) will be formed in the first surface101of the wafer100. The formation of the ring-shaped recess may be performed by an etching process. The formation of the circuit structures (not shown inFIG. 2D) may also be performed by an etching process. It is to be noted that both the ring-shaped recess and the circuit structures may be formed by the same or subsequent etching process(es).

Alternatively, it is possible that the ring-shaped recess is generated by any other (direct) process such as, e.g., milling (i.e. recess-grinding), laser ablation, etc. If a mechanical wafer machining process is used, the formation of the ring-shaped recess should be performed before generating the circuit structures (not shown inFIG. 2D) in the wafer100in order to avoid any risk of damaging the circuit structures by vibrations, concussions, grinding fluids, chemical agents or other environmental impact caused by wafer machining.

FIGS. 3A and 3Billustrate in a more detailed representation (in which a central portion of the wafer is omitted for the sake of illustrative ease) two different types of a ring-shaped recess to be formed in the wafer100. The hatched areas of the wafer100, as depicted inFIGS. 3A and 3B, illustrate wafer material which is to be removed when the ring-shaped recess310A,310B is formed.

According toFIG. 3A, the ring-shaped recess310A may extend across a peripheral part of the thinned region101a, along, e.g., a side wall101bof the thinned region101aand over a surface101cof the reinforcement ring110. That is, the ring-shaped recess310A may have the shape of a continuous, circumferential ring which extends in a radial direction between an edge of the wafer100at R0and R3within the thinned region101aof the first surface101. R1refers to the radial position of the side wall101bbefore thinning.

Referring toFIG. 3B, the ring-shaped recess310B may have the shape of a ring-shaped trench. The ring-shaped trench310B may extend in a radial direction between R3(i.e. the inner outline of the ring-shaped trench310B) and R2(i.e. the outer outline of the ring-shape trench310B). R2and R3are measured at the level of the first surface101of the wafer100after thinning, i.e. at the level of the surface of the thinned region101a. It is to be noted that

Referring toFIGS. 3A and 3B, the distance between R1and R3(i.e. between an outline of the thinned region101aand an inner outline of the ring-shaped recess310A,310B) may be equal to or less than 100 μm, 200 μm, 400 μm, 600 μm, 800 μm, 1000 μm, 1200 μm, 1400 μm, 1600 μm, 1800 μm, or 2000 μm. The distance between R1and R2(i.e. between the outline of the thinned region101aand the outer outline of the ring-shaped trench310B) may be equal to or less than 100 μm, 200 μm, 300 μm, 400 μm, 500 μm, 600 μm, 700 μm, 800 μm, 900 μm, or 1000 μm. The ring-shaped trench310B may thus have a width (distance between R2and R3) of equal to or less than or greater than 100 μm, 200 μm, 300 μm, 400 μm, 500 μm, 600 μm, 700 μm, 800 μm, 900 μm, or 1000 μm. The reinforcement ring110may have a width L (distance between R0and R1) as already mentioned above. The thickness of the reinforcement ring110may, e.g., be equal to the thickness T of the initial wafer110as already mentioned above or may, e.g., be the thickness T reduced by the depth Td of the ring-shaped recess310A (e.g. seeFIG. 3A).

By way of example, if Tg is about 250-400 μm, Td may be about 75-325 μm (±25 μm) so as to provide for a residual wafer thickness Tr of, e.g., 75-175 μm (±25 μm). The residual wafer thickness Tr should be small enough to allow the reinforcement ring110to be easily separated from an inner region of the wafer comprised in the thinned region101a.

FIGS. 4A and 4Billustrate embodiments of a wafer100including a reinforcement ring110extending along a periphery of the wafer100in correspondence toFIGS. 3A and 3B, respectively. Thus, the wafer100is equipped with a ring-shaped recess310A,310B in the first surface101and further includes a usable area surrounded by the ring-shaped recess310A,310B, wherein the inner outline (at R3) of the ring-shaped recess310A,310B neighbors the usable area of the wafer100.

FIGS. 4A, 4Bfurther illustrate circuit structures410A,410B optionally formed in the first surface101of the usable area of the wafer100. The circuit structures410A,410B may have been formed in accordance with the description ofFIG. 2D. The circuit structures410A,410B may represent MEMS structures as used in a MEMS device, e.g. in any of the above-mentioned MEMS devices. The second surface102of the wafer may, e.g., comprise ICs (not shown) within the usable area of the wafer100. As apparent fromFIGS. 3A, 3B and 4A, 4Bthe usable area of the wafer (i.e. the area between R3-R3) may be a central portion of the thinned region101aof the first surface101.

It is to be noted that further structures such as, e.g., electrodes (e.g. chip pads) may be formed in the first surface101(backside) and/or the second surface102(front side) within the usable area of the wafer100. Such electrodes (not shown) may, e.g., be electrically connected to the MEMS structures and/or to the ICs.

Referring toFIGS. 5A and 5B, a dicing tape520may be attached to the first surface101of the wafer100. As can be seen inFIGS. 5A and 5B, the dicing tape520may be spaced-apart from at least a part of the first surface101within the ring-shaped recess310A,310B. More specifically, in case of the first type of the ring-shaped recess310A, the dicing tape520may be distant from the bottom of the ring-shaped recess310A at a location near an inner edge region511of the ring-shaped recess310A. Referring toFIG. 5B, the dicing tape520may be spaced apart from the first surface101of the wafer100across the entire extension of the second type ring-shaped recess310B, i.e. may span over the ring-shaped trench310B from the inner edge region511to an outer edge region512of the ring-shaped trench310B.

Then, the reinforcement ring110is separated from an inner region530of the wafer100(which includes the usable area of the wafer100) along the ring-shaped recess310A,310B. More specifically, the separation may be performed at arrow X. The separation may be performed at a location where the dicing tape520is spaced apart from the first surface101of the wafer100. By way of example, the separation may be performed near to the inner edge region511of the ring-shaped recess310A and/or near to the center of the ring-shaped trench310B.

The separation of the reinforcement ring110from the inner region530of the wafer100may be performed by ablation laser cutting. More specifically, a ring-shaped, e.g. circular, ablation laser cut may be applied at arrow X. The ablation laser may be a UV laser. Using an ablation laser is beneficial for avoiding the use of milling or grinding fluids, etching agents or other substances which could harm circuit structures (e.g., MEMS structures) of the wafer100. However, other separation methods may also be feasible, e.g., etching, milling (i.e. separation-grinding), etc. These processes may similarly provide for a ring cut at arrow X.

Due to the distance between the cut wafer material and the dicing tape520, the separation process can be performed without severely damaging the dicing tape520. In other words, the dicing tape520may remain intact at the location of separation. By way of example, if an ablation laser is used to separate the reinforcement ring110from the inner region530of the wafer100, the laser is out of focus when hitting the dicing tape520. That way, the laser causes small or negligible damage to the dicing tape520, and it is therefore possible to use a variety of dicing tapes520, e.g. dicing tapes which are not specifically designed for ablation laser cutting.

By way of example, it is possible to use a dicing tape520which is designed for stealth (laser) dicing. Stealth dicing may be one of the favourable dicing methods used to ultimately separate chips out of the inner region530of the wafer100. Stealth dicing is different from ablation laser cutting, i.e. different lasers may be employed. Since stealth dicing does not produce kerf between adjacent chips to be separated, the stealth laser dicing tape520has to be expandable. Such stealth laser dicing tape520(or other dicing tapes) are typically prone to foil damage if hit by an ablation laser as used for reinforcement ring110separation. Therefore, the distance between the dicing tape520and the location where the reinforcement ring110is separated from the inner region530of the wafer100allows, e.g., the usage of a dicing tape520which is specifically fitted to the later wafer dicing process (i.e. the process to produce the chips).

FIGS. 6A and 6Billustrate the wafer100when the inner region530of the wafer100is separated from the reinforcement ring110at a ring-shaped opening610. The ring-shaped opening610extends along and opens into the ring-shaped recess310A and310B, respectively. The dicing tape520remains intact at the location of separation. Thus, the wafer100can still be securely handled after the separation of the reinforcement ring110. On the other hand, the reduction of the material thickness at the location of separation by the ring-shaped recess310A,310B significantly mitigates the difficulties and risks in connection with the separation of the reinforcement ring110. This does specifically apply for the separation of the reinforcement ring110for large wafers such as, e.g., 12″ wafers, where the reinforcement ring separation is much more difficult than for smaller wafers such as, e.g., 8″ wafers, because larger wafers are more fragile than smaller wafers.

Further, the process described herein may significantly facilitate the separation of the reinforcement ring110for wafers100of a relatively large thickness Tg of equal to or more than 200 μm and/or of wafers100which include sensitive structures. In particular, both these aspects often apply to MEMS structures, so that the disclosure herein may be used with particular advantage for MEMS wafers and the manufacturing of MEMS devices.