Low distortion class-D amplifier

An amplifier that receives an input signal and outputs an amplified output signal includes an integration stage, a comparison stage, and a full bridge circuit. The integration stage is be used for receiving a constant common mode voltage, for receiving a first signal representing the input signal of the amplifier, and for generating a ramp signal. The comparison stage coupled to the integration stage is used for generating a pulse width modulation signal according to the ramp signal and according to a hysteretic signal. The full bridge circuit coupled to the comparison stage is used for receiving a power supply and the pulse width modulation signal, and for generating the output of the amplifier.

BACKGROUND ART

One advantage of a class-D amplifier over a linear amplifier (e.g., a class-AB amplifier) is a relatively high efficiency of the class-D amplifier. Because the output pulses of the class-D amplifier can have a fixed amplitude, the switching elements are switched either on or off, rather than being operated in a linear mode. One exemplary application for a class-D amplifier is a driver for a loudspeaker.

However, some class-D amplifiers that employ standard implementations may have propagation delays and may have low power supply rejection ratios.

SUMMARY

In one embodiment, an amplifier that receives an input signal and outputs an amplified output signal includes an integration stage, a comparison stage, and a full bridge circuit. In one embodiment, the integration stage is used for receiving a constant common mode voltage, for receiving a first signal representing the input signal of the amplifier, and for generating a ramp signal. The comparison stage coupled to the integration stage is used for generating a pulse width modulation signal according to the ramp signal and according to a hysteretic signal. The full bridge circuit coupled to the comparison stage is used for receiving a power supply and the pulse width modulation signal, and for generating the output of the amplifier.

DETAILED DESCRIPTION

FIG. 1shows a block diagram of a class-D amplifier100, in accordance with one embodiment of the present invention. The class-D amplifier100has a relatively high power supply rejection ratio. As shown inFIG. 1, the class-D amplifier100includes a power supply terminal110for receiving a power supply VDC, an amplification stage180, and an output stage160, in one embodiment.

The amplification stage180can receive an input signal170and generate a ramp signal130. The amplification stage180can generate a pulse width modulation signal140according to the ramp signal130and a hysteretic signal132to drive the output stage160. The ramp signal130and the hysteretic signal132are positioned at a voltage level that is half of the voltage level of the power supply VDCand that varies proportionally with the power supply VDC, in one embodiment. For example, the ramp signal130and the hysteretic signal132are centered at the voltage level that is half of the voltage level of the power supply VDC, in one embodiment.

The output stage160coupled to the power supply terminal110can receive the pulse width modulation signal140from the amplification stage180and can generate an amplified output signal190. In one embodiment, the output stage160can be a full bridge circuit.

As shown inFIG. 1, the amplification stage180includes a first circuit shown as the translation stage101coupled to the full bridge circuit160for receiving the input signal170and for producing a translated signal120that is positioned at a voltage level that is half of the voltage level of the power supply VDC. More specifically, when the input voltage V170is equal to zero, a voltage level of the translated signal120can be equal to half of the voltage level of the power supply VDC.

The amplification stage180further includes a second circuit shown as the integration stage (e.g., an integrator)102that can receive the translated signal120from the translation stage101and an integrating signal122from the full bridge circuit160, and can generate the ramp signal130therefrom. Advantageously, an oscillator and a ramp generator can be omitted, in one embodiment.

A comparison stage103can receive the ramp signal130and the hysteretic signal132, and can generate the pulse width modulation signal140to drive the full bridge circuit160. In one embodiment, the ramp signal130is within a hysteretic window of the hysteretic signal132.

To summarize, in one embodiment, the amplifier100inFIG. 1includes a power supply terminal110for receiving power, a full bridge circuit160coupled to the power supply terminal110for providing an amplified output190, a translation stage101coupled to the full bridge circuit160for receiving an input signal170and producing a translated signal120, an integration stage102that can receive the translated signal120from the translation stage101and an integrating signal122from the full bridge circuit160, and generate a ramp signal130therefrom, and a comparison stage103that can receive the ramp signal130from the integration stage102and a hysteretic signal132from the full bridge circuit160, and generate a pulse width modulation signal140to drive the full bridge circuit160.

In one embodiment, the ramp signal130and the hysteretic signal132are positioned at a voltage level that is half of the voltage level of the power supply VDCand that varies proportionally with the power supply VDC. For example, the hysteretic signal132can have a maximum and a minimum value, and the range between the maximum and the minimum values of the hysteretic signal132is centered at half of the voltage level of the power supply VDC. Similarly, the ramp signal130can have a maximum and a minimum value, and the range between the maximum and the minimum values of the ramp signal130is centered at half of the voltage level of the power supply VDC.

FIG. 2shows a detailed circuit diagram of the amplifier100inFIG. 1coupled to a loud speaker230, in accordance with one embodiment of the present invention. Elements labeled the same as inFIG. 1have similar functions and will not be repetitively described herein for purposes of brevity and clarity.

The amplifier100inFIG. 2further includes a first resistor divider, shown as resistor260and resistor262, coupled between the first switching node LX1and the second switching node LX2of the full bridge circuit160for providing the hysteretic signal132to the comparison stage103.

The first resistor divider includes a first resistor260and a second resistor262. In one embodiment, the first resistor260includes a first resistance R1less a second resistance ΔR1. In one embodiment, the second resistor262includes the first resistance R1added to the second resistance ΔR1. Therefore, R260=R1−ΔR1and R262=R1+ΔR1.

The amplifier100further includes a second resistor divider, shown as resistor250and resistor252, coupled between the first switching node LX1and the second switching node LX2of the full bridge circuit160for providing the integrating signal122to the integration stage102.

The second resistor divider includes a first resistor250and a second resistor252. In one embodiment, the first resistor250includes a first resistance R2added to a second resistance ΔR2. In one embodiment, the second resistor252includes the first resistance R2less the second resistance ΔR2. Therefore, R250=R2+ΔR2and R252=R2−ΔR2.

In one embodiment, the translation stage101includes an operational transconductance amplifier202which is coupled to the integration stage102for converting the input signal170to an input current Iin. The amplifier100further includes a resistor divider, shown as resistor240and resistor242, coupled between LX1and LX2for receiving the input current Iinand producing a translated signal120. The translated signal120can be equal to half of the voltage level of the power supply VDCwhen a voltage V170of the input signal170is equal to zero, in one embodiment. The resistor240and the resistor242have the same resistance R, in one embodiment.

The integration stage102includes an operational amplifier204and a capacitor234. The integration stage102can receive the translated signal120and the integrating signal122, and generate a ramp signal130to the comparison stage103, in one embodiment.

The comparison stage shown as the comparator103can compare the hysteretic signal132with the ramp signal130, and generate a pulse width modulation signal140to drive the full bridge circuit160, in one embodiment. The output capacitor232that is coupled between the first switching node LX1and the second switching node LX2can provide the amplified output signal to the speaker230. As such, the speaker230can receive the amplified audio signal and generate audible sound therefrom.

In operation, the operational transconductance amplifier202can convert the input voltage V170to an input current Iinand can use the resistor divider, shown as resistors240and242, to create a translated signal120. If a gain of the operational transconductance amplifier202is g, then the voltage of the translated signal120can be given by:
V120=g*(R/2)*V170+VDC/2.  (1)

In one embodiment, the first switching node LX1and the second switching node LX2of the full bridge circuit160are out of phase. Therefore, an integrating current flowing through the capacitor234can have two different levels I122and I122′ depending on the states of the switching nodes LX1and LX2. In one embodiment, when the pulse width modulation signal140is high, the voltage at LX1is VDCand the voltage at LX2is zero. In contrast, when the pulse width modulation signal140is low, the voltage at LX1is zero and the voltage at LX2is VDC.

In one embodiment, since a voltage Vintat the inverting input (negative terminal) of the operational amplifier204is equal to the voltage V120at the non-inverting input (positive terminal) of the operational amplifier204, the integrating current I122when the pulse width modulation signal140is high and the integrating current I122′ when the pulse width modulation signal140is low can be respectively given by:
I122=(VDC−V120)/(R2+ΔR2)−V120/(R2−ΔR2),  (2)
when the pulse width modulation signal140is high;
I122′=(VDC−V120)/(R2−ΔR2)−V120/(R2+ΔR2),  (3)
when the pulse width modulation signal140is low.

Based on equation (1), equations (2) and (3) can be rewritten as:
I122=(−VDC*ΔR2−g*R*V170*R2)/(R22−ΔR22),  (4)
when the pulse width modulation signal140is high;
I122′=(VDC*ΔR2−g*R*V170*R2)/(R22−ΔR22),  (5)
when the pulse width modulation signal140is low.

In addition, according to the level of the pulse width modulation signal 140, the voltage V132of the hysteretic signal132can be given by:
V132=VDC*(R1+ΔR1)/2R1=VDC/2+VDC*ΔR1/2R1,  (6)
when the pulse width modulation signal140is high;
V132′=VDC*(R1−ΔR1)/2R1=VDC/2−VDC*ΔR1/2R1,  (7)
when the pulse width modulation signal140is low.

In one embodiment, an amplitude A130of the ramp signal130is equal to a voltage difference between V132and V132′. Therefore, the amplitude A130can be given by:
A130=VDC*ΔR1/R1.  (8)

As such, a parameter limit of the ramp signal130can be defined by the first resistance R1and the second resistance ΔR1of the resistor divider, shown as resistors260and262. In one embodiment, the aforementioned parameter limit of the ramp signal130includes the amplitude A130of the ramp signal130.

FIG. 3shows exemplary waveforms for the hysteretic signal132and the ramp signal130, in accordance with one embodiment of the present invention. In the example ofFIG. 3, T1is the period when the pulse width modulation signal140is high, and T2is the period when the pulse width modulation signal140is low.FIG. 3is described in combination withFIG. 2.

As shown inFIG. 3, the ramp signal130is within a hysteretic window302of the hysteretic signal132. In the example ofFIG. 3, during period T1, the voltage level of the hysteretic signal132is above the VDC/2 level according to equation (6). In addition, during period T2, the voltage level of the hysteretic signal132is below the VDC/2 level according to equation (7), in one embodiment. In one embodiment, when the hysteretic signal132is greater than the ramp signal130, the pulse modulation signal140is high, such that the current I122can flow through the capacitor234and a voltage level of the ramp signal130can increase until the level of the ramp signal130reaches the level of the hysteretic signal132at a certain point. Then the comparator103can output a low level signal140. As a result, the hysteretic signal132can drop below the VDC/2 level, such that the current I122′ can flow through the capacitor234and the ramp signal130can gradually decrease towards the hysteretic signal132as shown in period T2. The comparator103continues to output a low voltage signal140until the level of the ramp signal130decreases to the level of the hysteretic signal132.

Advantageously, the pulse width modulation signal140can be generated according to the ramp signal130and the hysteretic signal132, and both hysteretic signal132and ramp signal130can be positioned at a voltage level that is half of the power supply voltage VDC, in one embodiment. More specifically, the range between the maximum and the minimum values of the hysteretic signal132is centered at half of the voltage level of the power supply VDC. Similarly, the range between the maximum and the minimum values of the ramp signal130is centered at the half of voltage level of the power supply VDC.

Advantageously, in one embodiment, the hysteretic window302of the hysteretic signal132is defined by the states of the switching nodes LX1and LX2of the full bridge circuit160, which can reduce/eliminate the errors associated with the propagation delays on the drivers and the power switches in the full bridge circuit160and can also reduce/eliminate the errors caused by the power switches un-matching.

In one embodiment, if the period T1is relatively short, the current I122during the period T1can regarded as a constant. Similarly, if the period T2is relatively short, the current I122′ during the period T2can regarded as a constant. Therefore, the charge change ΔQ of the capacitor234in the integration stage102inFIG. 1can be given by:
ΔQ=C234*A130=−I122*T1=I122′*T2.  (9)
Therefore, when equations (3) and (4) are substituted into equation (9), the following equation can be obtained:
VDC*(T2−T1)/(T2+T1)=g*R*R2/ΔR2*V170.  (10)

An equivalent theoretical voltage V190of the output signal190across the output capacitor232is equal to:

V190=⁢T1/(T1+T2)*VDC-T2/(T1+T2)*VDC=⁢(T1-T2)/(T1+T2)*VDC.(11)
Therefore, a gain A of the amplifier100can be given by:
A=V190/V170=−g*R*R2/ΔR2.  (12)

Advantageously, the gain A of the amplifier100does not depend on the power supply VDC, which can ensure relatively high power supply rejection ratio of the amplifier100, in one embodiment.

According to equation (9), the switching frequency of the full bridge circuit160can be given by:
fsw=1/(T1+T2)=1/((−C234*A130/I122)+(C234*A130/I122′))  (13)
When equation (2) and (3) are substituted into equation (13), the switching frequency becomes:
fsw=(VDC2*ΔR22−g2*R2*V1702*R22)/(C234*A130*(R22−ΔR22)*2*VDC*ΔR2)  (14)
When equation (8) is substituted into equation (14), the switching frequency becomes:
fsw=R1*ΔR2/(2C234*ΔR1*(R22−ΔR22))−g2*R2*V1702*R22*R1/(2C234*ΔR1*VDC2*ΔR22*(R22−ΔR22))  (15)

If assume that K1=R1*ΔR2/(2C234*ΔR1*(R22−ΔR22)) and K2=g2*R2*R22*R1/(2C234*ΔR1*ΔR22*(R22−ΔR22)), then equation (15) becomes:
fsw=K1−K2*(V170/VDC)2(16)

K1and K2are constant. Therefore, the switching frequency fswrelates to the input voltage V170and the supply voltage VDC. As such, the switching frequency fswof the full bridge circuit160remains constant when the input signal170is zero, in one embodiment.

Accordingly, the present invention provides a low distortion class-D amplifier with high power supply rejection ratio. The gain of the class-D amplifier does not depend on the power supply, in one embodiment. In addition, no oscillator and ramp generator is required, in one embodiment. Furthermore, the present disclosure also provides an audio system comprising a low distortion class-D amplifier for receiving an audio signal, and a speaker coupled to the low distortion class-D amplifier for converting the audio signal to audible/audio sound.

FIG. 4shows a block diagram of an audio system400, in accordance with one embodiment of the present invention. Elements that are labeled similar as inFIG. 1andFIG. 2have similar functions and will not be repetitively described herein for purposes of brevity and clarity. As shown inFIG. 4, the audio system400includes an amplifier404coupled to a speaker230. The amplifier404can be used for receiving an input signal170and for generating an output signal190. The speaker230coupled to the amplifier404can be used for converting the output signal190to audible/audio sound.

More specifically, the amplifier404includes an integration stage402(e.g., an integrator) for receiving a constant common mode voltage VCM, for receiving a first signal423representing the input signal170of the amplifier404, and for generating a ramp signal430. Additionally, the amplifier404includes a comparison stage403coupled to the integration stage402for generating a pulse width modulation signal140according to the ramp signal430and a hysteretic signal432. The amplifier404further includes a full bridge circuit460coupled to the comparison stage403for receiving a power supply VDC(at terminal110) and the pulse width modulation signal140, and for generating the output190of the amplifier404.

In one embodiment, the amplifier404further includes a translation stage401coupled to the integration stage402for receiving the input signal170, and for generating a signal423representing the input signal170to the integration stage402. In one embodiment, the full bridge circuit460can be used for providing the hysteretic signal432to the comparison stage403, and for providing a signal420to the integration stage402.

Advantageously, by using the translation stage401, the integration stage402, the comparison stage403and the full bridge circuit460, a gain of the amplifier404can remain constant even if the power supply VDCvaries, in one embodiment. Furthermore, in one embodiment, a switching frequency of the full bridge circuit460can remain constant if the input signal170is zero.

FIG. 5Ashows a detailed circuit diagram of the amplifier404coupled to the speaker230, in accordance with one embodiment of the present invention. Elements that are labeled similar as inFIG. 1,FIG. 2andFIG. 4have similar functions and will not be repetitively described herein for purposes of brevity and clarity.

As shown inFIG. 5A, the amplifier404further includes a resistor divider, shown as resistor560and resistor562, coupled between a first switching node LX1and a second switching node LX2of the full bridge circuit460for providing the hysteretic signal432. In one embodiment, the resistor divider has a first resistor560that includes a first resistance R1less a second resistance ΔR1, and a second resistor562that includes the first resistance R1added to the second resistance ΔR1. Therefore, R560=R1−ΔR1and R562=R1+ΔR1.

In one embodiment, the amplifier404further includes a resistor divider, shown as resistor550and resistor552, coupled between a first switching node LX1and a second switching node LX2of the full bridge circuit460for providing a signal422to the integration stage402. In one embodiment, the resistor divider has a first resistor550that includes a first resistance R2added to a second resistance ΔR2, and a second resistor552that includes the first resistance R2less the second resistance ΔR2. Therefore, R550=R2+ΔR2and R552=R2−ΔR2.

In one embodiment, the translation stage401includes an operational transconductance amplifier502coupled to the integration stage402for converting the input signal170to an input current I170. As such, the signal423includes the input current I170. If a gain of the operational transconductance amplifier502is g502and a voltage of the input signal170is V170, the input current I170can be given by:
I170=g502* V170.  (17)

In one embodiment, the integration stage402includes an operational amplifier504and a capacitor510. In one embodiment, the translation stage401can be coupled to a negative (inverting) terminal of the operational amplifier504. In one embodiment, the amplifier404further includes a resistor divider, shown as resistor540and resistor542, coupled between a first switching node LX1and a second switching node LX2of the full bridge circuit460for providing the signal420to the integration stage402. In one embodiment, the resistor divider, shown as resistors540and542, includes a resistor540and a resistor542having the same resistance R. In one embodiment, the resistor divider, shown as resistors540and542, can be coupled to a positive (non-inverting) terminal of the operational amplifier504. As such, in one embodiment, if a voltage of the power supply (at terminal110) is VDC, a voltage V420of the signal420can be given by V420=VDC/2. In other words, the voltage level of the signal420can be equal to half of the voltage level of the power supply VDC, in one embodiment.

In one embodiment, a voltage V422of the signal422at the negative terminal of the operational amplifier504is equal to the voltage V420of the signal420at the positive terminal of the operational amplifier504. Therefore, the voltage V422of the signal422can be given by
V422=VDC/2.  (18)
As such, the voltage level of the signal422can be equal to half of the voltage level of the power supply VDC. In other words, a voltage level of the common mode voltage VCM(VCM=(V420+V422)/2) of the integration stage402is constant, and more specifically, is equal to half of a voltage level of the power supply VDC.

Advantageously, since the common mode voltage VCMof the operational amplifier504is constant and is independent of the input voltage V170, an influence that may be caused by the input voltage V170on a common mode rejection ratio (CMRR) of the operational amplifier504can be eliminated, in one embodiment.

Furthermore, in one embodiment, a current-shunt feedback (e.g., the capacitor510) of the integration stage402can lower an input impedance at the negative terminal of the operational amplifier504, such that the output impedance of the operational transconductance amplifier502which is coupled to the negative terminal of the operational amplifier504can be lowered. Advantageously, the capability of the operational transconductance amplifier502for providing high current and for driving high capacitive load can be enhanced. Additionally, a signal-to-noise ration of the amplifier404can be improved, in one embodiment.

In one embodiment, the first switching node LX1and the second switching node LX2of the full bridge circuit460are out of phase. Therefore, a current flowing through the capacitor510of the integration stage402can have two different levels depending on the state of the switching nodes LX1and LX2. In one embodiment, when the pulse width modulation signal140is high, the voltage at LX1is VDCand voltage at LX2is zero. In contrast, when the pulse width modulation signal140is low, the voltage at LX1is zero and the voltage at LX2is VDC.

More specifically, when the pulse width modulation signal140is high, an integrating current I510flowing through the capacitor510can be calculated as:
I510=(VDC−V422)/(R2+ΔR2)−V422/(R2−ΔR2)+I170.  (19a)
When the pulse width modulation signal140is low, an integrating current I510′ flowing through the capacitor510can be calculated as:
I510′=(VDC−V422)/(R2−ΔR2)−V422/(R2+ΔR2)+I170.  (19b)

Based on equation (17) and equation (18), equations (19a) and (19b) can be rewritten as
I510=−VDC*ΔR2/(R22−ΔR22)+g502*V170(20a)
and
I510′=VDC*ΔR2/(R22−ΔR22)+g502*V170(20b)
respectively.

Similarly, in one embodiment, a voltage level of the hysteretic signal432also have two different levels depending on the states of the switching nodes LX1and LX2. When the pulse width modulation signal140is high, a voltage V432of the hysteretic signal432can be calculated as:
V432=VDC*(R1+ΔR1)/2R1=VDC/2+VDC*ΔR1/2R1.  (21a)
When the pulse width modulation signal140is low, a voltage V432′ of the hysteretic signal432can be calculated as:
V432′=VDC*(R1−ΔR1)/2R1=VDC/2−VDC*ΔR1/2R1.  (21b)
As such, the voltage level of the hysteretic signal432can be centered at half of the voltage level of the power supply VDC. More specifically, the range between the maximum and the minimum value of the hysteretic signal432is centered at half of the voltage level of the power supply VDC.

Since an amplitude A430of the ramp signal430can be a difference between V432and V432′, the amplitude A430can be given by
A430=|V432−V432′|=VDC*ΔR1/R1.  (22)
As such, a parameter limit, e.g., amplitude A430, of the ramp signal430can be controlled by the resistor divider, shown as resistors560and562.

Similarly, the voltage level of the ramp signal430can be centered at half of the voltage level of the power supply VDC. More specifically, the range between the maximum and the minimum values of the ramp signal430is centered at half of the voltage level of the power supply VDC.

If assume that T1is a period during which the pulse width modulation signal140is high, and T2is a period during which the pulse width modulation signal140is low, a charge change ΔQ510of the capacitor510in the integration stage402can be given by:
ΔQ510=C510*A430=−I510*T1=I510′*T2,  (23)
where C510is a capacitance of the capacitor510. Therefore, when equation (20a) and equation (20b) are substituted into equation (23), the following equation can be obtained:
(VDC*ΔR2/(R22−ΔR22)−g502*V170)*T1=(VDC*ΔR2/(R22−ΔR22)+g502*V170)*T2.
Therefore
VDC*(T1−T2)/(T1+T2)=g502*V170*(R22−ΔR22)/ΔR2.  (24)

Since an equivalent theoretical voltage V190eqof the output signal190can be given by:

V190⁢eq=⁢T1/(T1+T2)*VDC-T2/(T1+T2)*VDC=⁢(T1-T2)/(T1+T2)*VDC,(25)
the gain A404of the amplifier404can be calculated as
A404=V190eq/V170=g502*(R22−ΔR22)/ΔR2,  (26)
in one embodiment. Advantageously, in one embodiment, the gain A404of the amplifier404can remain constant if the power supply VDCvaries. Therefore, the gain of the amplifier404does not depend on the power supply VDC, which can assure high power supply rejection ratio, in one embodiment.

According to equation (23), a switching frequency f460of the full bridge circuit460can be given by
f460=1/(T1+T2)=1/((−C510*A430/I510)+(C510*A430/I510′)).  (27a)
When equations (20a), (20b) and (22) are substituted into equation (27a), the switching frequency f460can be rewritten as:
f460=R1*ΔR2/(2C510*ΔR1*(R22−ΔR22))−(g5022*R1*(R22−ΔR22)/(2C510*ΔR1*ΔR2))*(V170/VDC)2.  (27b)
Therefore, the following equation can be obtained:
f460=K3+K4*(V170/VDC)2,  (28)
where K3is a constant that is equal to R1*ΔR2/(2C510*ΔR1*(R22−ΔR22)), and K4is a constant that is equal to −g5022*R1*(R22−ΔR22)/(2C510*ΔR1*ΔR2).

Therefore, the switching frequency f460relates to the input voltage V170and the supply voltage VDC, in one embodiment. In addition, the switching frequency f460of the full bridge circuit460can remain constant if the input signal170is zero.

FIG. 5Bshows a block diagram of an amplifier404′ coupled to the speaker230, in accordance with one embodiment of the present invention. Elements that are labeled the same as inFIG. 5Ahave similar functions and will not be repetitively described herein for purpose of clarity and brevity. In one embodiment, the aforementioned resistor divider shown as resistors560and562inFIG. 5A, and the aforementioned resistor divider shown as resistors550and552inFIG. 5A, can be compacted to a single resistor divider, shown as resistor570, resistor572and resistor574inFIG. 5B.

In one embodiment, the resistor divider, shown as resistors570,572and574, coupled between a first switching node LX1and a second switching node LX2of the full bridge circuit460can be used for proving the hysteretic signal432and the signal422.

More specifically, in one embodiment, the resistor570includes a first resistance R3less a second resistance ΔR3, the resistor572includes a resistance that is twice as the second resistance ΔR3, and the resistor574includes the first resistance R3less the second resistance ΔR3. Therefore, R570=R3−ΔR3, R572=2ΔR3, and R574=R3−ΔR3.

The operation and functionality of the amplifier inFIG. 5Bis similar as that inFIG. 5A. In one embodiment, when the pulse width modulation signal140is high, an integrating current I510bflowing through the capacitor510can be calculated as
I510b=−VDC*ΔR3/(R32−ΔR32)+g502*V170.  (29a)
When the pulse width modulation signal140is low, an integrating current I510b′ flowing through the capacitor510can be calculated as
I510b′=VDC*ΔR3/(R32−ΔR32)+g502*V170(29b)

According to one embodiment inFIG. 5B, the following equations can be obtained:
VDC*(T1−T2)/(T1+T2)=g502*V170*(R32−ΔR32)/ΔR3,  (30)
V190eq=(T1−T2)/(T1+T2)*VDC,  (31)
and
A404b=V190eq/V170=g502*(R32−ΔR32)/ΔR3,  (32)
where A404bis a gain of the amplifier404′ and can remain constant if the power supply VDCvaries.

When the pulse width modulation signal140is high, a voltage V432bof the hysteretic signal432can be calculated as:

V432⁢b=⁢V422+(VDC-V422)*R572/(R570+R572)=⁢(VDC/2)*(1+2⁢⁢Δ⁢⁢R3/(R3+Δ⁢⁢R3)).(33⁢a)
When the pulse width modulation signal140is low, a voltage V432b′ of the hysteretic signal432can be calculated as:

As such, a switching frequency f460bof the full bridge circuit460inFIG. 5Bcan be calculated as

Similarly, the switching frequency f460brelates to the input voltage V170and the supply voltage VDC, in one embodiment. In addition, the switching frequency f460bof the full bridge circuit460can remain constant if the input signal170is zero.

In the examples ofFIG. 5AandFIG. 5B, each of the aforementioned amplifiers404and404′ can generate a hysteretic signal432that has a voltage level that can be centered at VDC/2 and generate a ramp signal430that has a voltage level that can also be centered at VDC/2. However, a voltage level of the hysteretic signal432and/or ramp signal430can also be centered at a voltage level that is different from VDC/2.FIG. 5Cshows a block diagram of an amplifier404″ coupled to the speaker230, in accordance with one embodiment of the present invention. Elements that are labeled the same asFIG. 5AandFIG. 5Bhave similar functions and will not be repetitively described herein for purpose of clarity and brevity.

For example, a resistor576shown inFIG. 5Ccan be coupled between the resistor divider (shown as resistors560and562) and ground for shifting the voltage level of the hysteretic signal432. If a resistance of the resistor576is R1, a voltage V432cof the hysteretic signal432can be calculated as:

As such, a switching frequency f460cof the full bridge circuit460inFIG. 5Ccan be calculated as:
f460c=((3R12−ΔR12)/(2C510*R1*ΔR1))*(ΔR2/(R22−ΔR22)−((R22−ΔR22)*g5022/ΔR2)*(V170/VDC)2).  (39)
Therefore, the following equation can be obtained:
f460c=K7+K8*(V170/VDC)2,  (40)
where K7is a constant that is equal to (3R12−ΔR12)*ΔR2/(2C510*R1*ΔR1*(R22−ΔR22)) and K8is a constant that is equal to −(3R12−ΔR12)*(R22−ΔR22)*g5022/(2C510*R1*ΔR1*ΔR2). Similarly, the switching frequency f460cof the full bridge circuit460can remain constant if the input signal170is zero.

The calculations for the gain A404Cof the amplifier404″ in the example ofFIG. 5Care similar as the calculations in the example ofFIG. 5A. In one embodiment, the gain A404Cof the amplifier404″ can be calculated as: A404C=g502*(R22−ΔR22)/ΔR2. Similarly, the gain A404Cof the amplifier404″ can remain constant if the power supply VDC varies.

In one embodiment, the resistor576can also have other resistance. In another embodiment, a resistor (not shown inFIG. 5Cfor purposes of brevity and clarity) can also be coupled between the resistor divider (shown as resistors560and562) and the power supply (at terminal110) for shifting the voltage level of the hysteretic signal432. Similar calculations for the amplitude of the ramp signal430and the switching frequency of the full bridge circuit460will not be described herein for purposes of brevity and clarity.

FIG. 6shows a flowchart600of operations performed by an amplifier that can amplify an input signal170, in accordance with one embodiment of the present invention.FIG. 6is described in combination withFIG. 4,FIG. 5A,FIG. 5BandFIG. 5C.

As shown in block602, an integration stage402can generate a ramp signal430based on a constant common mode voltage VCMof the integration stage402and the input signal170. In one embodiment, a translation stage401can be implemented for converting the input signal170to an input current received by the integration stage102. In one embodiment, a voltage level of the constant common mode voltage VCMcan be equal to half of a voltage level of a power supply VDC.

In one embodiment, a comparison stage103can be implemented for comparing the ramp signal with a hysteretic signal from the full bridge circuit460, and for generating a pulse width modulation signal140for driving the full bridge circuit460. In other words, in block604, the amplifier can generate a pulse width modulation signal140according to the ramp signal430and the hysteretic signal432.

As such, the full bridge circuit460can generate an output190of the amplifier according to the power supply VDCof the full bridge circuit460and the pulse width modulation signal140, in block606. Advantageously, in one embodiment, the amplifier can produce a gain that can remain constant even if the power supply VDCvaries.

Accordingly, the present invention provides a class-D amplifier that can amplify an input signal to an output signal by a full bridge circuit, an integration stage, and a comparison stage. A ramp signal generated by the integration stage according to the input signal can be compared with a hysteretic signal from the full bridge circuit by a comparison stage in order to generate a pulse width modulation signal. In one embodiment, a duty cycle of the pulse width modulation signal that can be used for driving the full bridge circuit can be defined by the input signal. As such, the full bridge circuit can generate an amplified output signal that is proportional to the input signal, in one embodiment. A gain of the amplifier can be independent of a power supply powering the amplifier, such that the power supply rejection ratio of the amplifier can be increased.