Sense amplifier with precharge delay circuit connected to output

Single-ended sense amplifier circuit. An example of the sense amplifier circuit includes an inverter coupled to a bit line to read a bit cell. The sense amplifier circuit also includes a first circuit responsive to a control signal to charge the bit line for a predefined time. Further, the sense amplifier circuit includes a second circuit coupled to the bit line and responsive to a read 1 operation to retain voltage of the bit line above a first threshold to render the inverter to read 1 from the bit cell.

REFERENCE TO PRIORITY APPLICATION

This application claims priority from Indian Provisional Application No. 2821/CHE/2008 filed on Nov. 17, 2008, entitled “A HIGH-SPEED SINGLE-ENDED SENSE AMPLIFIER FOR ROMs, CAMs, AND SINGLE-ENDED-READ RAMs”, naming Texas Instruments Incorporated (the intended assignee) as the Applicant, and naming the same inventors as in the present application as inventors, which is incorporated herein by reference in its entirety.

TECHNICAL FIELD

Embodiments of the disclosure relate to a single-ended sense amplifier circuit.

BACKGROUND

A sense amplifier circuit is used in a memory, for example a complementary metal oxide semiconductor (CMOS) memory, to detect or sense stored data from a bit cell. Performance of the sense amplifier circuit impacts memory access time and power dissipation. A single-ended sense amplifier circuit requires low power and one input data signal, and provides high noise immunity as compared to a differential sense amplifier circuit.

A conventional single-ended sense amplifier circuit100, hereinafter referred to as the circuit100, is illustrated inFIG. 1(Prior Art). The circuit100is responsive to a control signal (SENB) to perform read operations. Initially, SENB is at logic level HI and DIN is at logic level LO. A transistor105is active. SENB then moves to a logic level LO. A transistor110becomes active and charges a bit line115through a diode120. If operation is a read “0” operation then a bit cell coupled to the bit line115forces the bit line115to logic level LO. Hence, strength of the diode120is made less in order to prevent opposition of the bit cell by the diode120and to read “0” at output of an inverter125. However, having the diode120with less strength leads to undesired delay during a read “1” operation. The bit line115is charged slowly due to presence of the diode120. Also, strength of a transistor130is made high as compared to a transistor stack135to prevent opposition by the transistor stack135during a read “0” operation. However, having the transistor stack135with less strength leads to undesired delay during a read “1” operation. The undesired delay due to the diode120and the transistor stack135may lead to false reading. Moreover, the false reading increases with process, voltage and temperature variations.

SUMMARY

An example of a sense amplifier circuit includes an inverter coupled to a bit line to read a bit cell. The sense amplifier circuit also includes a first circuit responsive to a control signal to charge the bit line for a predefined time. Further, the sense amplifier circuit includes a second circuit coupled to the bit line and responsive to a read 1 operation to retain voltage of the bit line above a first threshold to render the inverter to read 1 from the bit cell.

An example of a circuit includes an inverter coupled to a bit line to read a bit cell. The circuit also includes a pre-charge circuit coupled to the bit line and responsive to a control signal to charge the bit line for a predefined time. Further, the circuit includes a diode coupled to the bit line and responsive to a read 1 operation to retain voltage of the bit line above a first threshold to render the inverter to read 1 from the bit cell. Moreover, the circuit includes a pull-up circuit coupled to the bit line and responsive to the read 1 operation to compensate charge sharing on the bit line between the inverter and the bit cell to prevent glitch at the inverter.

An example of a method for reading a bit cell includes charging a bit line for a predefined time. The method also includes retaining voltage of the bit line over a first threshold if it is a read 1 operation to generate a read 1 output. Further, the method includes discharging the bit line if it is a read 0 operation to generate a read 0 output.

DETAILED DESCRIPTION OF THE EMBODIMENTS

FIG. 2illustrates a single-ended sense amplifier circuit200, hereinafter referred to as the circuit200. The circuit200includes an inverter205. The inverter205includes a positive metal oxide semiconductor (PMOS) transistor210A and a negative metal oxide semiconductor (NMOS) transistor215A. The PMOS transistor210A is skewed with respect to the NMOS transistor215A for proper functioning across process, voltage and temperature variations. The circuit connection for the inverter205is as follows: A gate of the PMOS transistor210A and a gate of the NMOS transistor215A are coupled to a bit line220(DIN). A drain of the PMOS transistor210A and a drain of the NMOS transistor215A are coupled to an input terminal of an inverter225A. The gate of the PMOS transistor210A is also coupled to the gate of the NMOS transistor215A, a source of the PMOS transistor210A is coupled to a power supply (VDD), and a drain of the PMOS transistor210A is coupled to the drain of the NMOS transistor215A. A source of the NMOS transistor215A is coupled to a ground supply (GND).

The circuit200also includes a first circuit, for example a pre-charge circuit230. The circuit connection for the pre-charge circuit230is explained as follows: The pre-charge circuit230is coupled to the inverter205through the inverter225A. The pre-charge circuit230includes a delay circuit235. The delay circuit235includes one or more inverters, for example an inverter225C, an inverter225D, an inverter225E, and an inverter225F. The circuit connection for the delay circuit235is explained as follows: an input terminal of the inverter225C is coupled to an output terminal of the inverter225A and an output terminal of the inverter225C is coupled to an input terminal of the inverter225D. The output terminal of the inverter225D is coupled to an input terminal of the inverter225E. The output terminal of the inverter225E is coupled to an input terminal of the inverter225F.

The pre-charge circuit230also includes an inverter225B, one or more PMOS transistors, for example a PMOS transistor210B, a PMOS transistor210C, a PMOS transistor210D, a PMOS transistor210J, and a PMOS transistor210I. The pre-charge circuit230further includes one or more NMOS transistors, for example, an NMOS transistor215B, an NMOS transistor215C and an NMOS transistor215D. The circuit connection of the delay circuit235with the one or more PMOS transistors and the one or more NMOS transistors is explained as follows: the output terminal of the inverter225F is coupled to a gate of the NMOS transistor215B. The NMOS transistor215B has a drain coupled to an input terminal of an inverter225B, a drain of the PMOS transistor210J, a drain of the NMOS transistor215C and a drain of the PMOS transistor210C. A source of the NMOS transistor215B is coupled to the ground supply. The gate of the NMOS transistor215B is also coupled to the gate of the PMOS transistor210J. The PMOS transistor210C has the drain coupled to the input terminal of an inverter225B, a drain of the PMOS transistor210J, a drain of the NMOS transistor215C. The PMOS transistor210C has a gate coupled to a gate of the NMOS transistor215C, and a source coupled to the power supply. The gate of the NMOS transistor215C and the gate of the PMOS transistor210C are responsive to a control signal, for example a signal S1. Control signals, for example the signal S1and a signal S2, can be generated by a circuit external to the circuit200. The signal S1and the signal S2enable the circuit200to read data stored in a bit cell260coupled to the bit line220. The signal S2is an inverted version of the signal S1. The NMOS transistor215C has a source coupled to a drain of the NMOS transistor215D and the drain coupled to the input terminal of an inverter225B. The NMOS transistor215D has a source coupled to the ground supply, and a gate coupled to a gate of the PMOS transistor210I and a gate of the PMOS transistor210B. The PMOS transistor210I has a source coupled to the power supply, the gate coupled to the gate of the PMOS transistor210B, and a drain coupled to a drain of the PMOS transistor210J. An output terminal of the inverter225B is coupled to the gate of the PMOS transistor210B, a gate of the NMOS transistor215D, and a gate of the PMOS transistor210I. The PMOS transistor210B has a source coupled to a drain of the PMOS transistor210D, and a drain coupled to the bit line220The PMOS transistor210D has a source coupled to the power supply, and a gate responsive to the signal S2. In some embodiments, the pre-charge circuit230may not include the delay circuit235and other transistors. The pre-charge circuit230can include the PMOS transistor210D and the PMOS transistor210B, and signals S2and a signal PRE at a node265can be generated externally and provided to the pre-charge circuit230.

The circuit200also includes a second circuit240. The second circuit240includes a pull-up circuit250and a diode255A. The pull-up circuit250includes a plurality of diodes, for example a diode255B, and a diode255C. The plurality of diodes may be transistor based diodes. The circuit connection for the diode225A is explained as follows: The diode255A is coupled to the bit line220. The diode255A can be a transistor based diode having a source coupled to a drain of the PMOS transistor210G and a source of the PMOS transistor210F, a drain and a gate coupled to the bit line220. The diode255A has a threshold equivalent to that of the PMOS transistor210A, and hence the diode255A can be referred to as a mirror-match of the PMOS transistor210A. The circuit connection of the diode225A with the pull-up circuit250is explained as follows The PMOS transistor210G has a source coupled to the power supply, a drain coupled to a source of the PMOS transistor210F, and a gate responsive to a signal N3generated by a feedback circuit. For example, the feedback circuit may include a PMOS transistor210G coupled to the inverter205through the diode225A. The signal N3may be an output signal generated by the inverter205at a node270. The PMOS transistor210F has a drain coupled to the bit line220, and a gate coupled to the diode255C, a drain of the PMOS transistor210E, the diode255B. The PMOS transistor210E has a source coupled to power supply, a gate coupled to a gate of the NMOS transistor215E and the bit line220, and the drain coupled to the diode255C and the diode255B. The NMOS transistor215E has a gate coupled to the bit line220a source coupled to the ground supply, and has a drain coupled to the diode255B.

The circuit200also includes a third circuit245. The third circuit245includes one or more transistors, for example a PMOS transistor210H, a NMOS transistor215G, a NMOS transistor215F. The third circuit245also includes a transistor based diode, for example a diode255D. The circuit connection for the third circuit is explained as follows: The PMOS transistor210H has a gate responsive to the signal S2, a source coupled to the power supply, and a drain coupled to the diode255D and a drain of the NMOS transistor215F. The diode255D is further coupled to a drain of the NMOS transistor215G. The NMOS transistor215G has a source coupled to the ground supply, and a gate responsive to the signal S1. The drain of the NMOS transistor215G is also coupled to a source of the NMOS transistor215F. The NMOS transistor215F, a gate coupled to the diode255D, and a drain coupled to the node270of the inverter205.

The bit line220is also coupled to a drain of a NMOS transistor215J. The NMOS transistor has a gate responsive to the signal S2and a source coupled to the ground supply.

The circuit200is a single-ended sense amplifier circuit. The circuit200is used to detect or sense or read data stored in a bit cell260coupled to the bit line220. The bit cell260is at least one of a read only memory, a content-addressable memory and a single-ended-read random access memory. The working of the circuit200can be divided into phases, for example a first phase and a second phase. The first phase can be referred to as initial phase where the circuit200is initialized for enabling reading of the bit cell260in the second phase.

The pre-charge circuit230is responsive to the signal S1to charge the bit line220for a predefined time in the first phase. The diode255A is responsive to a read 1 operation in the second phase to retain voltage of the bit line220above a first threshold to render the inverter205to read 1 from the bit cell260. The first threshold can be defined as a maximum value of a voltage of the bit line that can activate the PMOS transistor210A and hence lead to a false read operation. The pull-up circuit250is responsive to the read 1 operation in the second phase to compensate charge sharing on the bit line220between the inverter205and the bit cell260to prevent glitch at the inverter205. The third circuit245is responsive to the signal S1and the signal S2to render the inverter205to read 1 from the bit cell260when a voltage supply of the PMOS transistor210A falls below or becomes equal to a second threshold. The second threshold is a maximum value of the voltage supply that can activate the PMOS transistor210A and hence lead to the false read operation.

The working of the circuit200in different phases is described in detail as follows: Initially, the signal S1is at a logic level LO and the signal S2is at a logic level HI. The signal S1activates the PMOS transistor210C to bring the signal PRE at the node265to the logic level LO. In the first phase, the signal S1moves from the logic level LO to the logic level HI. The signal S2moves to the logic level LO and activates the PMOS transistor210D. The bit line220gets charged as the PMOS transistor210D and the PMOS transistor210B are active. The bit line220is charged for a predefined time. The predefined time can be defined as time needed to charge the bit line220. In one aspect, the predefined time is the time during which the signal PRE at the node265is at the logic level LO. When the signal PRE at the node265moves to the logic level HI, the PMOS transistor210B becomes inactive and stops the charging of the bit line220. The signal PRE at the node265can be moved to the logic level HI using the delay circuit235. The NMOS transistor215B is active to drive the signal PRE at the node265to the logic level HI.

The signal S1at the logic level HI activates the NMOS transistor215G of the third circuit245. The signal S2at logic level LO drives the PMOS transistor210H to activate the NMOS transistor215F. The NMOS transistor215F and the NMOS transistor215G drive the signal N3at the node270to the logic level LO.

The second phase starts when the signal PRE at the node265moves to logic level HI which in turn inactivates the pre-charge circuit230. In the second phase, the circuit200performs a read 1 operation or enables a read 0 operation.

In case of a read 1 operation, the bit cell260is inactive. In one example, the bit cell260is an NMOS transistor which is inactive. The bit line220having a signal at the logic level HI, due to the charging, activates the NMOS transistor215E and pulls a signal PULL at a node275below a voltage sufficient to activate the PMOS transistor210F. The PMOS transistor210E is inactive. The signal N3at the node270is provided as a feedback to the PMOS transistor210G. The signal N3at the logic level LO activates the PMOS transistor210G pulling the bit line220above VDD-VTH, where VTH is a threshold voltage of the PMOS transistor210A and the diode255A. The diode255A retains the voltage of the bit line220above the first threshold. In one example, the PMOS transistor210A and the diode255A are coupled to same word line to ensure similar threshold voltage. The word line may be a read word line in the memory cell. The word line controls the bit line220to access the bit cell260. To read the bit from the bit cell260a full voltage may be applied to the read word line. The PMOS transistor210F and the PMOS transistor210G are active and compensates charge sharing on the bit line220to prevent glitch at the inverter205. The charge sharing can occur between one or more capacitors coupled to one or more multiplexers. The one or more multiplexers may be coupled between the bit cell260and the inverter205. For example, a capacitor285A coupled between a LMUX215H and the bit cell260, a capacitor285B coupled between to a GMUX215I and the LMUX215H, and a capacitor285C coupled to the bit line220and the GMUX215I.

The pull-up circuit250also prevents voltage of the bit line220from falling below or becoming equal to VDD-VTH due to charge sharing and hence prevents activation of the PMOS transistor210A which may lead to a false read operation.

The NMOS transistor215A is active to enable the circuit200to read 1 from the bit cell260. The signal N3at the node270is at the logic level LO and an output signal (COUT) at a node280is at the logic level HI. The output signal at the logic level HI at the node280is referred to as reading 1 from the bit cell260.

It might happen that the voltage supply falls below or becomes equal to the second threshold which in turn may lead to inactivation of the NMOS transistor215A. The third circuit245, for example a bleeder NMOS circuit, ensures that the signal N3at the node270is maintained at the logic level LO when the voltage supply falls below or becomes equal to the threshold. Hence the output signal at the node280is maintained at the logic level HI and wider range of the voltage supply can be used. The read operation is performed using the inverter205which reads from the bit cell260.

In case of a read 0 operation, the bit cell260, for example the NMOS transistor, is active. The bit cell260pulls a signal at the bit line220to the logic level LO. The PMOS transistor210E becomes active, and pulls the signal PULL at the node275to the logic level HI which in turn inactivates the PMOS transistor210F. The signal at the logic level LO at the bit line220activates the PMOS transistor210A. The PMOS transistor210A pulls the signal N3at the node270to the logic level HI. The output signal moves to the logic level LO at the node280and hence a read 0 is performed. The third circuit245is weaker as compared to the PMOS transistor210A. The signal N3at the logic level HI at the node270inactivates the PMOS transistor210G and hence cuts-off the diode255A and the pull-up circuit240from the bit line220.

It is noted that the bit cell260can be a PMOS transistor or an NMOS transistor or a combination of PMOS transistors and NMOS transistors.

FIG. 3is a flow diagram illustrating a method for reading a bit cell.

At step305, a bit line, for example the bit line220of the circuit220, is charged for the predefined time.

At step310, voltage of the bit line is retained, for example by using a diode, for example the diode255A, over the first threshold for a read 1 operation to generate a read 1 output. If the voltage of the bit line falls below the first threshold a false read operation may be performed. The voltage of the bit line may fall below the first threshold due to charge sharing on the bit line. The compensation of charge sharing, for example by using the pull-up circuit250, retains the bit line over the first threshold. The bit line is also retained above the first threshold, for example by using the third circuit245, when the voltage supply falls below or becomes equal to the second threshold to generate the read 1 output.

At step315, the bit line is discharged for a read 0 operation to generate a read 0 output. A feedback signal can be generated to cut-off a circuit that performs step310. The feedback signal may be generated by the pre-charge circuit230.

FIG. 4Ais a graphical representation of signals for a read 0 operation. Y-axis represents voltage, in volts, and X-axis represents time in seconds. A waveform405corresponds to the signal S1, a waveform410corresponds to the signal PRE, a waveform415corresponds to the bit line220, a waveform420corresponds to the signal PULL, and a waveform425corresponds to the N3signal.

The first phase ends at 1.35 nanoseconds. During the first phase, the waveform405is at the logic level HI, the waveform410is at the logic level HI, the waveform415is at the logic level HI, the waveform420is at 0.5 volts, and the waveform425is at the logic level LO.

The second phase starts at 1.35 nanoseconds. During the second phase, the waveform405is at the logic level HI, the waveform410is at the logic level HI, the waveform415is at the logic level LO, the waveform420is at the logic level HI, and the waveform425is at the logic level HI.

FIG. 4Bis a graphical representation of the signals for a read 1 operation. Y-axis represents voltage, in volts, and X-axis represents time in seconds. The first phase ends at 1 nanosecond. During the first phase, the waveform405is at the logic level HI, the waveform410is at the logic level LO, the waveform415is at the logic level HI, the waveform420is at 0.4 volts, and the waveform425is at the logic level HI.

The second phase starts at 1 nanosecond. During the second phase, the waveform405is at the logic level HI, the waveform410is at the logic level HI, the waveform415is at 0.6 volts, the waveform420is at 0.5 volts, and the waveform425is at the logic level LO.

Various embodiments of the present disclosure help in achieving robust read 0 and read 1 operation. The circuit200ensures higher speed during read operations.

In the foregoing discussion, the term “coupled” refers to either a direct electrical connection between the devices coupled or an indirect connection through intermediary devices. The term “circuit” means at least either a single component or a multiplicity of components, that are coupled together to provide a desired function. The term “signal” means at least one current, voltage, charge, data, or other signal.