SEMICONDUCTOR MODULE AND METHOD FOR MANUFACTURING SEMICONDUCTOR MODULE

There are provided a semiconductor module capable of preventing the adhesion of an epoxy resin to a terminal to which at least one of a high current and a high voltage is supplied and a method for manufacturing a semiconductor module. A semiconductor module includes: a case having an inner wall defining a casting region and a peripheral edge portion arranged outside the inner wall; an intermediate terminal arranged in along side portion of a peripheral edge portion and having a fastening surface to which a cable is fastened; a structure arranged in a long side portion of the inner wall to be adjacent to the long side portion where the intermediate terminal is arranged and higher than the fastening surface; and a sealing section formed of an epoxy resin, having weld lines formed close to the side of the structure on a surface, and cast into a casting region to seal transistors.

TECHNICAL FIELD

The present invention relates to a semiconductor module applied to power converters and the like and a method for manufacturing a semiconductor module.

BACKGROUND ART

PTL 1 discloses “To provide a surface mount piezoelectric component free from a risk that droplets of sealing solder adheres to a quartz oscillator in a step of hermetically sealing a container and a lid, the surface mount piezoelectric component contains the container including a recessed portion and the lid, in which a piezoelectric element is hermetically sealed into the recessed portion, and the surface mount piezoelectric component is configured such that a notch is provided in the outer periphery of a position where the container and the lid are sealed, which is the outer peripheral edge in contact with the lid of the container, and the notch is filled with a sealing member”.

PTL 2 discloses a semiconductor module including: a base plate; a resin case provided on the base plate; three main terminals attached to the resin case; a plurality of semiconductor chips provided on the base plate in a hollow space of the resin case; and a sealing material injected into the hollow space. PTL 3 discloses a semiconductor module including: a plurality of semiconductor chips; a resin case housing the plurality of semiconductor chips; an input terminal and a three-phase output terminal connected to a main power supply provided on the surface of the resin case; and a resin sealing the plurality of semiconductor chips. PTL 4 discloses a semiconductor module including: a plurality of transistors; a package housing the plurality of transistors; and an input terminal for power supply fixed to the package and an output terminal connected to a motor.

CITATION LIST

Patent Literatures

SUMMARY OF INVENTION

Technical Problem

PTL 1 describes disadvantages that, when the sealing solder is heated and melted in the step of sealing the container and the lid, droplets are generated from the melted solder and adhere to the quartz oscillator, causing characteristic defects, such as a change in the resonance frequency or oscillation stop, so that the manufacturing yield of the surface mount piezoelectric component is lowered. However, PTL 1 does not describe a semiconductor module.

To the main terminals of the semiconductor module disclosed in PTL 2, the input terminal or the three-phase output terminal of the semiconductor module disclosed in PTL 3, and the input terminal or the output terminal of the semiconductor module disclosed in PTL 4, a large current flows or a high voltage is applied, as compared with control terminals connected to control terminals of semiconductor chips or transistors. In conventional semiconductor modules, an epoxy resin forming a sealing material sometimes adheres to such terminals to which a large current flows or a high voltage is applied. The epoxy resin is an insulating material. Therefore, the adhesion of the epoxy resin to the terminals to which a large current flows or a high voltage is applied increases the contact resistance between predetermined cables connected to the terminals and the terminals, so that the terminals generate heat or a desired current does not flow to the terminals or a desired voltage is not applied to the terminals in some cases. Thus, the semiconductor modules have posed problems, such as a reduction in the efficiency for driving a load, such as a motor, and the inability to drive the load.

It is an object of the present invention to provide a semiconductor module and a high voltage is supplied and a method for manufacturing a semiconductor module capable of preventing the adhesion of an epoxy resin to a terminal to which at least one of a high current.

Solution to Problem

To achieve the above-described object, a semiconductor module according to one aspect of the present invention includes: a case having an inner wall defining a space where a plurality of switching elements is arranged and a peripheral edge portion arranged outside the inner wall and formed in a rectangular annular shape; an intermediate terminal arranged in one of a pair of long side portions forming apart of the peripheral edge portion and facing each other, having a fastening surface to which a cable connected to a load as a drive target is fastened, and connected to the plurality of switching elements; a structure arranged in a partial region of the inner wall to be adjacent to the long side portion where the intermediate terminal is arranged and higher than the fastening surface; and a sealing section formed of an epoxy resin, having weld lines formed close to the side of the structure on the surface, and cast into the space to seal the plurality of switching elements.

To achieve the above-described object, a method for manufacturing a semiconductor module according to one aspect of the present invention is a method for manufacturing a semiconductor module, the semiconductor module being the semiconductor module of the present invention described above, and the method includes: arranging a nozzle included in a casting device configured to cast the epoxy resin into the space at a predetermined position in the space from above the case; discharging the epoxy resin from the nozzle into the space while moving the nozzle in a direction toward and away from the one of the pair of long side portions; stopping the movement of the nozzle at a position close to the side of the structure in the space; and stopping the discharge of the epoxy resin into the space and completing the formation of the sealing section.

Advantageous Effects of Invention

One aspect of the present invention can prevent the adhesion of an epoxy resin to terminals to which at least one of a large current and a high voltage is supplied.

DESCRIPTION OF EMBODIMENTS

Each embodiment of the present invention exemplifies devices or methods for embodying the technical idea of the present invention. The technical idea of the present invention does not specify materials, shapes, structures, arrangement, and the like of constituent parts to the materials, shapes, structures, arrangement, and the like described below. The technical idea of the present invention can be variously altered within the technical scope specified by claims.

A semiconductor module and a method for manufacturing a semiconductor module according to one embodiment of the present invention are described usingFIGS.1to9. First, the schematic configuration of the semiconductor module according to this embodiment is described usingFIGS.1to3. In this embodiment, a power conversion module capable of performing DC/AC conversion as a semiconductor module is described as an example.

(Entire Configuration of Semiconductor Module)

FIG.1is a schematic plan view illustrating a schematic configuration example of a semiconductor module1according to this embodiment. For ease of understanding,FIG.1illustrates predetermined centers and virtual straight lines that are not originally provided on the surfaces of sealing sections in the semiconductor module1.FIG.2is a schematic cross-sectional view of the semiconductor module1cut along the α-α line illustrated inFIG.1.FIG.2illustrates a presence region of an inverter circuit provided in the semiconductor module1and does not illustrate transistors and the like constituting the inverter circuit. Further,FIG.2does not illustrate bonding wires connecting each main control terminal and the transistors provided in the semiconductor module1.FIG.3is a circuit diagram of an inverter circuit of a U-phase inverter section provided in the semiconductor module1.

As illustrated inFIG.1, the semiconductor module1according to this embodiment includes a case11having an inner wall112defining casting regions (an example of the space)113u,113v,113wwhere a plurality of transistors (an example of the switching elements)211,221,231,241,251,261,271,281(not illustrated inFIG.1, seeFIG.3) is arranged and a peripheral edge portion111arranged outside the inner walls112and formed in a rectangular annular shape. Hereinafter, the transistors211,221,231,241,251,261,271,281are sometimes abbreviated as “transistors211to281”.

The peripheral edge portion111has a pair of long side portions111a,111barranged to face each other and a pair of short side portions111c,111dlaid between both end portions of the pair of long side portions111a,111b. The inner wall112has a pair of long side portions112a,112barranged to face each other and partition sections112c,112dpartitioning a space surrounded by the peripheral edge portion111into the casting regions113u,113v,113w. The long side portion112ais arranged adjacent to the long side portion111aof the peripheral edge portion111. The long side portion112bis arranged adjacent to the long side portion111bof the peripheral edge portion111. The partition section112cpartitions the space surrounded by the peripheral edge portion111into the casting region113uand the other region. The partition section112dpartitions the other region into the casting region113vand the casting region113w.

Therefore, the casting region113uis a region surrounded by the short side portion111cof the peripheral edge portion111and the long side portion112a, the partition section112c, and the long side portion112bof the inner wall112. The casting region113vis a region surrounded by the partition section112c, the long side portion112a, the partition section112dand the long side portion112bof the inner wall112. The casting region113wis a region surrounded by the partition section112dand the long side portion112aof the inner wall112, the short side portion111dof the peripheral edge portion111, and the long side portion112bof the inner wall112.

The peripheral edge portion111and the inner wall112are integrally formed, for example. More specifically, the peripheral edge portion111and the inner wall112, i.e., the case11, are made of a thermoplastic resin, for example.

The semiconductor module1includes an intermediate terminal Mu arranged in the long side portion111a(an example of the one of long side portions) of the pair of long side portions111a,111bforming a part of the peripheral edge portion111and facing each other, having a fastening surface751uto which a cable (not illustrated) connected to a load as a drive target is fastened, and connected to the transistors211to281. The semiconductor module1includes a U-phase positive electrode terminal Pu connected to the positive electrode side of DC power. The semiconductor module1includes a U-phase negative electrode terminal Nu arranged next to the positive electrode terminal Pu and connected to the negative electrode side of the DC power. The positive electrode terminal Pu and the negative electrode terminal Nu are arranged in the long side portion111bwhich is the other one of the pair of long side portions111a,111bforming a part of the peripheral edge portion111and facing each other. The positive electrode terminal Pu and the negative electrode terminal Nu, and the intermediate terminal Mu are arranged in the peripheral edge portion111with the casting region113uinterposed therebetween.

The intermediate terminal Mu, the positive electrode terminal Pu, and the negative electrode terminal Nu are connected to the transistors211to281arranged in the casting region113u. The positive electrode terminal Pu and the negative electrode terminal Nu supply DC power to be input to the transistors211to281arranged in the casting region113u. The transistors211to281arranged in the casting region113uare controlled by a control device (not illustrated) and convert the DC power input from the positive electrode terminal Pu and the negative electrode terminal Nu into U-phase AC power. The U-phase AC power generated by the transistors211to281arranged in the casting region113uis output to the outside via the intermediate terminal Mu. Thus, the intermediate terminal Mu serves as an output terminal from which the U-phase AC power is output.

The semiconductor module1includes an intermediate terminal My arranged in the long side portion111a(an example of the one of long side portions) of the pair of long side portions111a,111bforming a part of the peripheral edge portion111and facing each other, having a fastening surface751vto which a cable (not illustrated) connected to a load as a drive target is fastened, and connected to the transistors211to281. The semiconductor module1includes a V-phase positive electrode terminal Pv connected to the positive electrode side of DC power. The semiconductor module1includes a V-phase negative electrode terminal Nv arranged next to the positive electrode terminal Pv and connected to the negative electrode side of the DC power. The positive electrode terminal Pv and the negative electrode terminal Nv are arranged in the long side portion111bwhich is the other one of the pair of long side portions111a,111bforming a part of the peripheral edge portion111and facing each other. The positive electrode terminal Pv and the negative electrode terminal Nv, and the intermediate terminal Mv are arranged in the peripheral edge portion111with the casting region113vinterposed therebetween.

The intermediate terminal Mv, the positive electrode terminal Pv, and the negative electrode terminal Nv are connected to the transistors211to281arranged in the casting region113v. The positive electrode terminal Pv and the negative electrode terminal Nv supply DC power to be input to the transistors211to281arranged in the casting region113v. The transistors211to281arranged in the casting region113vare controlled by the control device (not illustrated) and convert the DC power input from the positive electrode terminal Pv and the negative electrode terminal Nv into V-phase AC power. The V-phase AC power generated by the transistors211to281arranged in the casting region113vis output to the outside via the intermediate terminal Mv. Thus, the intermediate terminal Mv serves as an output terminal from which the V-phase AC power is output.

The semiconductor module1includes an intermediate terminal Mw arranged in the long side portion111a(an example of the one of long side portions) of the pair of long side portions111a,111bforming a part of the peripheral edge portion111and facing each other, having a fastening surface751wto which a cable (not illustrated) connected to a load as a drive target is fastened, and connected to the transistors211to281. The semiconductor module1includes a W-phase positive electrode terminal Pw connected to the positive electrode side of DC power. The semiconductor module1includes a W-phase negative electrode terminal Nw arranged next to the positive electrode terminal Pw and connected to the negative electrode side of the DC power. The positive electrode terminal Pw and the negative electrode terminal Nw are arranged in the long side portion111bwhich is the other one of the pair of long side portions111a,111bforming a part of the peripheral edge portion111and facing each other. The positive electrode terminal Pw and the negative electrode terminal Nw, and the intermediate terminal Mw are arranged in the peripheral edge portion111with the casting region113winterposed therebetween.

The intermediate terminal Mw, the positive electrode terminal Pw, and the negative electrode terminal Nw are connected to the transistors211to281arranged in the casting region113w. The positive electrode terminal Pw and the negative electrode terminal Nw supply DC power to be input to the transistors211to281arranged in the casting region113w. The transistors211to281arranged in the casting region113ware controlled by a control device (not illustrated) and convert the DC power input from the positive electrode terminal Pw and the negative electrode terminal Nw into W-phase AC power. The W-phase AC power generated by the transistors211to281arranged in the casting region113wis output to the outside via the intermediate terminal Mw. Thus, the intermediate terminal Mw serves as an output terminal from which the W-phase AC power is output.

In a portion defining the casting region113uof the long side portion112aof the inner wall112, gate signal output terminals41,43,45,47,51,53,55,57and current detection terminals42,44,46,48,52,54,56,58connected to the transistors211to281(not illustrated inFIG.1), respectively, provided in a U-phase inverter section12uare arranged. Hereinafter, the gate signal output terminals41,43,45,47,51,53,55,57are abbreviated as “gate signal output terminals41to57”, and the current detection terminals42,44,46,48,52,54,56,58are abbreviated as “current detection terminals42to58” in some cases.

In a portion defining the casting region113vof the long side portion112aof the inner wall112, the gate signal output terminals41to57and the current detection terminals42to58connected to the transistors211to281(not illustrated inFIG.1), respectively, provided in a V-phase inverter section12vare arranged. The gate signal output terminals41to57and the current detection terminals42to58provided in the V-phase inverter section12vhave the same structures as those of the gate signal output terminals41to57and the current detection terminals42to58provided in the U-phase inverter section12u.

In a portion defining the casting region113wof the long side portion112aof the inner wall112, the gate signal output terminals41to57and the current detection terminals42to58connected to the transistors211to281(not illustrated inFIG.1), respectively, provided in a W-phase inverter section12ware arranged. The gate signal output terminals41to57and the current detection terminals42to58provided in the W-phase inverter section12whave the same structures as those of the gate signal output terminals41to57and the current detection terminals42to58provided in the U-phase inverter section12u.

As illustrated inFIGS.1and2, the semiconductor module1includes a structure31uarranged in the long side portion112a(an example of the partial region) of the inner wall112to be adjacent to the long side portion111awhere the intermediate terminal Mu is arranged and higher than the fastening surface751u. In this embodiment, the structure31uhas the gate signal output terminals41to57and the current detection terminals42to58connected to the transistors211to281, respectively, arranged in the casting region113u.

As illustrated inFIG.2, the gate signal output terminal47provided in the U-phase inverter section12uis higher than the fastening surface751uof the intermediate terminal Mu with a surface114of the case11on the side to which a direct bonded copper (DBC) substrate14uis attached as a reference. Although not illustrated, the gate signal output terminals41,43,45,51,53,55,57have the same structure as that of the gate signal output terminal47, and are provided in the case11in the same manner as the gate signal output terminal47. Therefore, the gate signal output terminals41,43,45,51,53,55,57are also higher than the fastening surface751uwith the surface114of case11as a reference.

As illustrated inFIG.2, the current detection terminal48provided in the U-phase inverter section12uis higher than the fastening surface751uof the intermediate terminal Mu with the surface114of the case11as a reference. Although not illustrated, the current detection terminals42,44,46,52,54,56,58have the same structure as that of the current detection terminal48, and are provided in the case11in the same manner as the current detection terminal48. Therefore, the current detection terminals42,44,46,52,54,56,58are also higher than the fastening surface751uwith the surface114of the case11as a reference.

Returning toFIG.1, the semiconductor module1includes a structure31varranged in the long side portion112a(an example of the partial region) of the inner wall112to be adjacent to the long side portion111awhere the intermediate terminal My is arranged and higher than the fastening surface751v. In this embodiment, the structure31vhas the gate signal output terminals41to57and the current detection terminals42to58connected to the transistors211to281, respectively, arranged in the casting region113v.

Although not illustrated, the gate signal output terminals41to57provided in the V-phase inverter section12vhave the same structure as that of the gate signal output terminal47provided in the U-phase inverter section12u, and are provided in the case11in the same manner as the gate signal output terminal47provided in the U-phase inverter section12u. Therefore, the gate signal output terminals41to57provided in the V-phase inverter section12vare higher than the fastening surface751vof the intermediate terminal My with the surface114of the case11as a reference.

Although not illustrated, the current detection terminals42to58provided in the V-phase inverter section12vhave the same structure as that of the current detection terminal48provided in the U-phase inverter section12u, and are provided in the case11in the same manner as the gate signal output terminal47provided in the U-phase inverter section12u. Therefore, the current detection terminals42to58provided in the V-phase inverter section12vare higher than the fastening surface751vof the intermediate terminal My with the surface114of the case11as a reference.

As illustratedFIG.1, the semiconductor module1includes a structure31warranged in the long side portion112a(an example of the partial region) of the inner wall112to be adjacent to the long side portion111awhere the intermediate terminal Mw is arranged and higher than the fastening surface751w. In this embodiment, the structure31whas the gate signal output terminals41to57and the current detection terminals42to58connected to the transistors211to281, respectively, arranged in the casting region113w.

Although not illustrated, the gate signal output terminals41to57provided in the W-phase inverter section12whave the same structure as that of the gate signal output terminal47provided in the U-phase inverter section12u, and are provided in the case11in the same manner as the gate signal output terminal47provided in the U-phase inverter section12u. Therefore, the gate signal output terminals41to57provided in the W-phase inverter section12ware higher than the fastening surface751W of the intermediate terminal Mw with the surface114of the case11as a reference.

Although not illustrated, the current detection terminals42to58provided in the W-phase inverter section12whave the same structure as that of the current detection terminal48provided in the U-phase inverter section12u, and are provided in the case11in the same manner as the gate signal output terminal47provided in the U-phase inverter section12u. Therefore, the current detection terminals42to58provided in the W-phase inverter section12ware higher than the fastening surface751wof the intermediate terminal Mw with the surface114of the case11as a reference.

Therefore, in the semiconductor module1, the structure31uprovided in the U-phase inverter section12uis higher than the fastening surface751u, the structure31vprovided in the V-phase inverter section12vis higher than the fastening surface751v, and the structure31wprovided in the W-phase inverter section12wis higher than the fastening surface751w.

As illustrated inFIGS.1and2, the semiconductor module1includes a sealing section81umade of an epoxy resin, having weld lines WLu formed close to the side of the structure31uon a surface811u, and cast into the casting region113uto seal the transistors211to281.

As viewed in a direction intersecting the surface811uof the sealing section81u(i.e., in a plan view), the weld lines WLu formed in the sealing section81uare formed in a region of the surface811uof the sealing section81uincluded between a virtual straight line VL1uincluding a center C1uin a direction in which the pair of long side portions111a,111bof the peripheral edge portion111constituting the case11are arranged and intersecting the direction and the long side portion112aof the inner wall112.

As viewed in the direction intersecting the surface811uof the sealing section81u, at least parts of the weld lines WLu formed in the sealing section81uhave a linearly symmetrical shape with a virtual straight line VL2uincluding the center C1uand parallel to the direction in which the pair of long side portions111a,111bare arranged as the axis.

As viewed in the direction intersecting the surface811uof the sealing section81u, at least parts of the weld lines WLu formed in the sealing section81uhave a shape spreading in a circular shape with a region A1u(an example of the predetermined region) of the surface811upositioned in front of the structure31uas the center. As viewed in the direction intersecting the surface811uof the sealing section81u, at least parts of the weld lines WLu formed in the sealing section81uhave a shape spreading in a circular shape with a region A2u(an example of the predetermined region) of the surface811upositioned in front of the structure31uas the center.

Although details are described later, in the semiconductor module1, epoxy resins are discharged into the casting region113ufrom two nozzles to form the sealing section81u. The regions A1u, A2ucorrespond to the positions where these two nozzles finally stop. The weld lines WLu are generated by the flow of the epoxy resins discharged at the final stop positions of the two nozzles in the casting region113u.

As illustrated inFIG.2, the long side portion111aof the peripheral edge portion111and the long side portion112aof the inner wall112have a step shape in which the DBC substrate14uside projects toward the casting region113urelative to the fastening surface751uside of the intermediate terminal Mu. In this step portion, end portions of the gate signal output terminals41to57and the current detection terminals42to58, which are bent in an L shape, are arranged to be exposed into the casting region113u. To the end portions, bonding wires (not illustrated) are connected, the bonding wires connecting the transistors211to281(not illustrated inFIG.2, seeFIG.3) arranged in a presence region121aof an inverter circuit121u, and the gate signal output terminals41to57and the current detection terminal42to58. Therefore, when the transistors211to281, the bonding wires, and the like arranged in the casting region113uare regarded as one constituent component group, the constituent component group is entirely relatively higher in the long side portion112aside than in the long side portion112bside of the inner wall112. Therefore, the sealing section81uis formed such that the thickness of the long side portion112aside of the inner wall112is larger than the thickness of the long side portion112bside of the inner wall112, so that the entire constituent component group can be reliably sealed.

Although details are described later, the epoxy resins sometimes remain at the tips of the nozzles after the completion of the discharge of the epoxy resins into the casting regions113u,113v,113win the manufacture of the semiconductor module1. Before retracting the nozzles from the semiconductor module1, bubbles generated in the epoxy resins remaining at the tips of the nozzles are broken, so that droplets of the epoxy resins are scattered in some cases. However, in the vicinity of the positions where the nozzles stop, the structure31uis arranged which has the gate signal output terminals41to57and the current detection terminals42to58and which is higher than the fastening surface751uof the intermediate terminal Mu. This enables the semiconductor module1to shield the fastening surface751uof the intermediate terminal Mu from the droplets from the epoxy resins remaining at the tips of the nozzles with the structure31uand prevent the adhesion of the droplets to the fastening surface751uof the intermediate terminal Mu.

Returning toFIG.1, the semiconductor module1includes a sealing section81vmade of an epoxy resin, having weld lines WLv formed close to the side of the structure31von a surface811v, and cast into the casting region113vto seal the transistors211to281.

As viewed in a direction intersecting the surface811vof the sealing section81v(i.e., in a plan view), the weld lines WLv formed in the sealing section81vare formed in a region of the surface811vof the sealing section81vincluded between a virtual straight line VL1vincluding a center C1vin the direction in which the pair of long side portions111a,111bof the peripheral edge portion111constituting the case11are arranged and intersecting the direction and the long side portion112aof the inner wall112.

As viewed in the direction intersecting the surface811vof the sealing section81v, at least parts of the weld lines WLv formed in the sealing section81vhave a linearly symmetrical shape with a virtual straight line VL2vincluding the center C1vand parallel to the direction in which the pair of long side portions111a,111bare arranged as the axis.

As viewed in the direction intersecting the surface811vof the sealing section81v, at least parts of the weld lines WLv formed in the sealing section81vhave a shape spreading in a circular shape with a region A1v(an example of the predetermined region) of the surface811vpositioned in front of the structure31vas the center. As viewed in the direction intersecting the surface811vof the sealing section81v, at least parts of the weld lines WLv formed in the sealing section81vhave a shape spreading in a circular shape with a region A2v(an example of the predetermined region) of the surface811vpositioned in front of the structure31vas the center.

The intermediate terminal My is provided in the case11such that the fastening surface751vis substantially flush with the fastening surface751uof the intermediate terminal Mu. The gate signal output terminals41to57and the current detection terminals42to58of the V-phase inverter section12vare provided in the case11in substantially the same manner as the gate signal output terminals41to57and the current detection terminals42to58of the U-phase inverter section12u. The relative positions of the regions A1v, A2vwith respect to the casting region113vare substantially the same as the relative positions of the regions A1u, A2uwith respect to the casting region113u. The regions A1v, A2vcorrespond to the final stop positions of two nozzles discharging epoxy resins for forming the sealing section81vin the casting region113v. This enables the semiconductor module1to shield the fastening surface751vof the intermediate terminal Mv from droplets from the epoxy resins remaining at the tips of the nozzles after the completion of the discharge of the epoxy resins into the casting region113vwith the structure31vand prevent the adhesion of the droplets to the fastening surface751vof the intermediate terminal Mv.

As illustrated inFIG.1, the semiconductor module1includes a sealing section81wmade of an epoxy resin, having weld lines WLw formed close to the side of the structure31won a surface811w, and cast into the casting region113wto seal the transistors211to281(not illustrated inFIG.1, seeFIG.3).

As viewed in a direction intersecting the surface811wof the sealing section81w(i.e., in a plan view), the weld lines WLw formed in the sealing section81ware formed in a region of the surface811wof the sealing section81wincluded between a virtual straight line VL1wincluding a center C1win the direction in which the pair of long side portions111a,111bof the peripheral edge portion111constituting the case11are arranged and intersecting the direction and the long side portion112aof the inner wall112.

As viewed in the direction intersecting the surface811wof the sealing section81w, at least parts of the weld lines WLw formed in the sealing section81whave a linearly symmetrical shape with a virtual straight line VL2wincluding the center C1wand parallel to the direction in which the pair of long side portions111a,111bare arranged as the axis.

As viewed in the direction intersecting the surface811wof the sealing section81w, at least parts of the weld lines WLw formed in the sealing section81whave a shape spreading in a circular shape with a region A1w(an example of the predetermined region) of the surface811wpositioned in front of the structure31was the center. As viewed in the direction intersecting the surface811wof the sealing section81w, at least parts of the weld lines WLw formed in the sealing section81whave a shape spreading in a circular shape with a region A2w(an example of the predetermined region) of the surface811wpositioned in front of the structure31was the center.

The intermediate terminal Mw is provided in the case11such that the fastening surface751wis substantially flush with the fastening surface751uof the intermediate terminal Mu. The gate signal output terminals41to57and the current detection terminals42to58of the W-phase inverter section12ware provided in the case11in substantially the same manner as the gate signal output terminals41to57and the current detection terminals42to58of the W-phase inverter section12w. The relative positions of the regions A1w, A2wwith respect to the casting region113ware substantially the same as the relative positions of the regions A1u, A2uwith respect to the casting region113u. The regions A1w, A2wcorrespond to the final stop positions of two nozzles discharging epoxy resins for forming the sealing section81winto the casting region113w. This enables the semiconductor module1to shield the fastening surface751wof the intermediate terminal Mw from droplets from the epoxy resins remaining at the tips of the nozzles after the completion of the discharge of the epoxy resins into the casting region113wwith the structure31wand prevent the adhesion of the droplets to the fastening surface751wof the intermediate terminal Mw.

The weld lines WLu, WLv, WLw are formed by the flow of the epoxy resins discharged into the casting regions113u,113v,113wto form the sealing sections81u,81v,81w, respectively. Therefore, the weld lines WLu, WLv, WLw do not always have exactly the same shape. However, the weld lines WLu, WLv, WLw each have the shapes of the above-described characteristics, and have at least similar shapes to each other.

The case11has a fixation section115uformed at each of the four corners of the casting region113u, a fixation section115vformed at each of the four corners of the casting region113v, and a fixation section115wformed at each of the four corners of the casting region113w. Two fixation sections of the fixation sections115u,115v,115ware arranged in each of the long side portions112a,112bof the inner wall112. The fixation sections115u,115v,115ware formed to be higher than the peripheral edge portion111of the case11with a surface114(not illustrated inFIG.1, seeFIG.2) of the case11as a reference. The peripheral edge portion111, the inner wall112, and the fixation sections115u,115v,115ware integrally formed. Therefore, the fixation sections115u,115v,115ware also made of a thermoplastic resin, for example.

The four fixation sections115uare provided to fix a circuit board (not illustrated) mounted with the control device (not illustrated) for controlling the inverter circuit121u(not illustrated inFIG.1, seeFIG.3) provided in the U-phase inverter section12u. The four fixation sections115vare provided to fix a circuit board (not illustrated) mounted with the control device (not illustrated) for controlling an inverter circuit121v(not illustrated in FIG.1, seeFIG.3) provided in the V-phase inverter section12v. The four fixation sections115ware provided to fix a circuit board (not illustrated) mounted with the control device (not illustrated) for controlling an inverter circuit121w(not illustrated inFIG.1, seeFIG.3) provided in the W-phase inverter section12w.

Although details are described later, the transistor211, the transistor221, the transistor231, and the transistor241provided in the U-phase inverter section12uare connected in parallel, and the transistor251, the transistor261, the transistor271, and the transistor281are connected in parallel. The transistors211,221,231,241connected in parallel and the transistors251,261,271,281connected in parallel are connected in series between the positive electrode terminal Pu and the negative electrode terminal Nu in the U-phase inverter section12u. In the U-phase inverter section12u, connection portions where the transistors211to281are connected to each other are connected to the intermediate terminal Mu from which the U-phase AC power is output. More specifically, the transistors211,221,231,241each provided in the U-phase inverter section12uform a part of constituent components constituting an upper arm Uup (not illustrated inFIG.1, seeFIG.3) of the U-phase AC power. The transistors251,261,271,281each provided in the U-phase inverter section12uform a part of constituent components constituting a lower arm Ulo (not illustrated inFIG.1, seeFIG.3) of the U-phase AC power.

The transistors211to281provided in the V-phase inverter section12vare connected between the positive electrode terminal Pv and the negative electrode terminal Nv in the same manner as the connection state of the transistors211to281provided in the U-phase inverter section12ubetween the positive electrode terminal Pu and the negative electrode terminal Nu. Therefore, the transistors211,221,231,241each provided in the V-phase inverter section12vform a part of constituent components constituting an upper arm Vup (not illustrated inFIG.1, seeFIG.3) of the V-phase AC power. The transistors251,261,271,281each provided in the V-phase inverter section12vform a part of constituent components constituting a lower arm Vlo (not illustrated inFIG.1, seeFIG.3) of the V-phase AC power.

The transistors211to281provided in the W-phase inverter section12ware connected between the positive electrode terminal Pw and the negative electrode terminal Nw in the same manner as the connection state of the transistors211to281provided in the U-phase inverter section12ubetween the positive electrode terminal Pu and the negative electrode terminal Nu. Therefore, the transistors211,221,231,241each provided in the W-phase inverter section12wform a part of constituent components constituting an upper arm Wup (not illustrated inFIG.1, seeFIG.3) of the W-phase AC power. The transistors251,261,271,281each provided in the W-phase inverter section12wform a part of constituent components constituting a lower arm Wlo (not illustrated inFIG.1, seeFIG.3) of the W-phase AC power.

Next, the schematic configurations of the U-phase inverter section12u, the V-phase inverter section12v, and the W-phase inverter section12wprovided in the semiconductor module1are described usingFIG.3referring toFIGS.1and2. The U-phase inverter section12u, the V-phase inverter section12v, and the W-phase inverter section12whave the same configuration. Therefore, the schematic configurations of the U-phase inverter section12u, the V-phase inverter section12v, and the W-phase inverter section12ware described taking the U-phase inverter section12uas an example.

As illustrated inFIG.2, the U-phase inverter section12uhas the DBC substrate14uand the inverter circuit121uformed on the DBC substrate14u. InFIG.2, the illustration of the specific configuration of the inverter circuit121uis omitted and the inverter circuit121uis illustrated as the presence region121apresent on the DBC substrate14u. The DBC substrate14uhas an insulating substrate140having substantially the same area as that of an opening of the casting region113uand formed in a rectangular flat plate shape. The DBC substrate14uhas a plurality of wiring patters (not illustrated) having a predetermined shape made of a conductive material (for example, copper) on the insulating substrate140on the side sealed by the sealing section81u. The DBC substrate14uhas a rectangular flat plate-shaped heat transfer pattern (not illustrated) formed on the insulating substrate140on the back surface side on the side sealed by the sealing section81u. The DBC substrate14uis attached to the case11by an adhesive (not illustrated).

To the plurality of wiring patterns, semiconductor elements21,22,23,24,25,26,27(not illustrated inFIG.2, seeFIG.3) having the transistors211to281are mounted and the intermediate terminal Mu, the positive electrode terminal Pu, and the negative electrode terminal Nu are electrically and mechanically connected. Hereinafter, the semiconductor elements21,22,23,24,25,26,27are sometimes abbreviated as “semiconductor elements21to27”.

The semiconductor module1has a cooling unit (not illustrated) provided on the surface114side of the case11and attached to the case11in a state where the cooling unit contacts the heat transfer pattern. The cooling unit is mechanically fixed to the case11by an adhesive, for example. The DBC substrate14uis soldered, for example, to the cooling unit. This enables the semiconductor module1to release the heat generated from the transistors211to281provided on the DBC substrate14uto the outside via the cooling unit.

Herein, the connection relationships among the positive electrode terminal Pu, the negative electrode terminal Nu, the intermediate terminal Mu, the transistors211to281, and the like provided in the semiconductor module1are described using the circuit diagram of the inverter circuit121uillustrated inFIG.3.FIG.3illustrates not only the reference numerals of the positive electrode terminal Pu, the negative electrode terminal Nu, the intermediate terminal Mu, the inverter circuit121u, the upper arm Uup, and the lower arm Ulo for the U-phase but the reference numerals of the positive electrode terminals Pv, Pw, the negative electrode terminals Nv, Nw, the intermediate terminals Mv, Mw, the inverter circuits121v,121w, the upper arms Vup, Wup, and the lower arms Vlo, Wlo for the V-phase and the W-phase, respectively.

As illustrated inFIG.3, the semiconductor module1includes the transistors211,221,231,241and freewheel diodes212,222,232,242. The semiconductor module1includes the transistors251,261,271,281and freewheel diodes252,262,272,282.

The transistors211to281are configured by an N-type metal-oxide-semiconductor field-effect transistor (MOSFET), for example. The freewheel diode212is connected to the transistor211in anti-parallel. A drain of the transistor211and a cathode of the freewheel diode212are connected, and a source of the transistor211and an anode of the freewheel diode212are connected. The transistor211and the freewheel diode212constitute the semiconductor element21. In the semiconductor element21, the transistor211and the freewheel diode212may be formed on different semiconductor substrates and the transistor211and the freewheel diode212may be formed on the same semiconductor substrate and integrated into one chip.

The freewheel diode222is connected to the transistor221in anti-parallel. A drain of the transistor221and a cathode of the freewheel diode222are connected, and a source of the transistor221and an anode of the freewheel diode222are connected. The transistor221and the freewheel diode222constitute the semiconductor element22. In the semiconductor element22, the transistor221and the freewheel diode222may be formed on different semiconductor substrates and the transistor221and the freewheel diode222may be formed on the same semiconductor substrate and integrated into one chip.

A drain of the transistor211, a cathode of the freewheel diode212, a drain of the transistor221, and a cathode of the freewheel diode222are connected to each other. The drain of the transistor211, the cathode of the freewheel diode212, the drain of the transistor221, and the cathode of the freewheel diode222are electrically connected to the positive electrode terminal Pu.

The source of the transistor211and the anode of the freewheel diode212are electrically connected. The source of the transistor221and the anode of the freewheel diode222are electrically connected. The source of the transistor211, the anode of the freewheel diode212, the source of the transistor221, and the anode of the freewheel diode222are connected to each other. The source of the transistor211, the anode of the freewheel diode212, the source of the transistor221, and the anode of the freewheel diode222are electrically connected to the intermediate terminal Mu.

The freewheel diode232is connected to the transistor231in anti-parallel. The transistor231and the freewheel diode232constitute the semiconductor element23. In the semiconductor element23, the transistor231and the freewheel diode232may be formed on different semiconductor substrates and the transistor231and the freewheel diode232may be formed on the same semiconductor substrate and integrated into one chip.

The freewheel diode242is connected to the transistor241in anti-parallel. The transistor241and the freewheel diode242constitute the semiconductor element24. In the semiconductor element24, the transistor241and the freewheel diode242may be formed on different semiconductor substrates (not illustrated) and the transistor241and the freewheel diode242may be formed on the same semiconductor substrate and integrated into one chip.

A drain of the transistor231, a cathode of the freewheel diode232, a drain of the transistor241, and a cathode of the freewheel diode242are connected to each other. The drain of the transistor231, the cathode of the freewheel diode232, the drain of the transistor241, and the cathode of the freewheel diode242are electrically connected to the drain of the transistor211, the cathode of the freewheel diode212, the drain of the transistor221, the cathode of the freewheel diode222, and the positive electrode terminal Pu.

A source of the transistor231and an anode of the freewheel diode232are electrically connected. A source of the transistor241and the anode of the freewheel diode222are electrically connected. The source of the transistor231, the anode of the freewheel diode232, the source of the transistor241, and the anode of the freewheel diode242are connected to each other. The source of the transistor231, the anode of the freewheel diode232, the source of the transistor241, and the anode of the freewheel diode242are electrically connected to the source of the transistor211, the anode of the freewheel diode212, the source of the transistor221, the anode of the freewheel diode222, and the intermediate terminal Mu.

Thus, the transistor211, the freewheel diode212, the transistor221, the freewheel diode222, the transistor231, the freewheel diode232, the transistor241, and the freewheel diode242are connected in parallel between the positive electrode terminal Pu and the intermediate terminal Mu. Therefore, the semiconductor elements21,22,23,24are connected in parallel between the positive electrode terminal Pu and the intermediate terminal Mu to form the upper arm Uup.

The freewheel diode252is connected to the transistor251in anti-parallel. The transistor251and the freewheel diode252constitute the semiconductor element25. In the semiconductor element25, the transistor251and the freewheel diode252may be formed on different semiconductor substrates and the transistor251and the freewheel diode252may be formed on the same semiconductor substrate and integrated into one chip.

The freewheel diode262is connected to the transistor261in anti-parallel. The transistor261and the freewheel diode262constitute the semiconductor element26. In the semiconductor element26, the transistor261and the freewheel diode262may be formed on different semiconductor substrates and the transistor261and the freewheel diode262may be formed on the same semiconductor substrate and integrated into one chip.

A drain of the transistor251, a cathode of the freewheel diode252, a drain of the transistor261, and a cathode of the freewheel diode262are connected to each other. The drain of the transistor251, the cathode of the freewheel diode252, the drain of the transistor261, and the cathode of the freewheel diode262are electrically connected to the drain of the transistor211, the cathode of the freewheel diode212, the drain of the transistor221, the cathode of the freewheel diode222, and the intermediate terminal Mu.

A source of the transistor251and an anode of the freewheel diode252are electrically connected. A source of the transistor261and an anode of the freewheel diode262are electrically connected. The source of the transistor251, the anode of the freewheel diode252, the source of the transistor261, and the anode of the freewheel diode262are connected to each other. The source of the transistor251, the anode of the freewheel diode252, the source of the transistor261, and the anode of the freewheel diode262are electrically connected to the negative electrode terminal Nu.

The freewheel diode272is connected to the transistor271in anti-parallel. The transistor271and the freewheel diode272constitute the semiconductor element27. In the semiconductor element27, the transistor271and the freewheel diode272may be formed on different semiconductor substrates and the transistor271and the freewheel diode272may be formed on the same semiconductor substrate and integrated into one chip.

The freewheel diode282is connected to the transistor281in anti-parallel. The transistor281and the freewheel diode282constitute the semiconductor element28. In the semiconductor element28, the transistor281and the freewheel diode282may be formed on different semiconductor substrates and the transistor281and the freewheel diode282may be formed on the same semiconductor substrate and integrated into one chip.

A drain of the transistor271, a cathode of the freewheel diode272, a drain of the transistor281, and a cathode of the freewheel diode282are connected to each other. The drain of the transistor271, the cathode of the freewheel diode272, the drain of the transistor281, and the cathode of the freewheel diode282are connected to the drain of the transistor251, the cathode of the freewheel diode252, the drain of the transistor261, the cathode of the freewheel diode262, and the intermediate terminal Mu.

A source of the transistor271and an anode of the freewheel diode272are electrically connected. A source of the transistor281and an anode of the freewheel diode282are electrically connected. The source of the transistor271, the anode of the freewheel diode272, the source of the transistor281, and the anode of the freewheel diode282are connected to each other. The source of the transistor271, the anode of the freewheel diode272, the source of the transistor281, and the anode of the freewheel diode282are electrically connected to the source of the transistor251, the anode of the freewheel diode252, the source of the transistor261, the anode of the freewheel diode262, and the negative electrode terminal Nu.

The transistor251, the freewheel diode252, the transistor261, the freewheel diode262, the transistor271, the freewheel diode272, the transistor281, and the freewheel diode282are connected in parallel between the intermediate terminal Mu and the negative electrode terminal Nu. Therefore, the semiconductor elements25,26,27,28are connected in parallel between the intermediate terminal Mu and the negative electrode terminal Nu to form the lower arm Ulo.

When the connection relationships among the semiconductor elements21,22,23,24,25,26,27,28, the positive electrode terminal Pu, the negative electrode terminal Nu, and the intermediate terminal Mu are structurally viewed, the semiconductor elements21,22connected in parallel and the semiconductor elements25,26connected in parallel are connected in series between the positive electrode terminal Pu and the negative electrode terminal Nu. The semiconductor elements23,24connected in parallel and the semiconductor elements27,28connected in parallel are connected in series between the positive electrode terminal Pu and the negative electrode terminal Nu. The semiconductor elements21,22,25,26connected in series between the positive electrode terminal Pu and the negative electrode terminal Nu and the semiconductor elements23,24,27,28connected in series between the positive electrode terminal Pu and the negative electrode terminal Nu are connected by the intermediate terminal Mu.

Therefore, when the connection relationships among the semiconductor elements21,22,23,24,25,26,27,28, the positive electrode terminal Pu, the negative electrode terminal Nu, and the intermediate terminal Mu are electrically viewed, the semiconductor elements21,22,23,24connected in parallel and the semiconductor elements25,26,27,28connected in parallel are connected in series between the positive electrode terminal Pu and the negative electrode terminal Nu. In the semiconductor elements21,22,23,24connected in parallel and the semiconductor elements25,26,27,28connected in parallel, the intermediate terminal Mu is connected to the connection portion between the positive electrode terminal Pu and the negative electrode terminal Nu.

A gate of the transistor211is connected to the gate signal output terminal41. By the connection between the gate of the transistor211and the gate signal output terminal41, a gate signal output from the control device is input into the gate of the transistor211via the gate signal output terminal41.

A source (auxiliary source) of a current detecting transistor (not illustrated) provided in the transistor211is connected to the current detection terminal42. By the connection between the source of the current detecting transistor and the current detection terminal42, a current flowing from the source of the current detecting transistor is input into the control device.

A gate of the transistor221is connected to the gate signal output terminal43. By the connection between the gate of the transistor221and the gate signal output terminal43, a gate signal output from the control device is input into the gate of the transistor221via the gate signal output terminal43.

A source (auxiliary source) of a current detecting transistor (not illustrated) provided in the transistor221is connected to the current detection terminal44. By the connection between the source of the current detecting transistor and the current detection terminal44, a current flowing from the source of the current detecting transistor is input into the control device.

A gate of the transistor231is connected to the gate signal output terminal45. By the connection between the gate of the transistor231and the gate signal output terminal45, a gate signal output from the control device is input into the gate of the transistor231via the gate signal output terminal45.

A source (auxiliary source) of a current detecting transistor (not illustrated) provided in the transistor231is connected to the current detection terminal46. By the connection between the source of the current detecting transistor and the current detection terminal46, a current flowing from the source of the current detecting transistor is input into the control device.

A gate of the transistor241is connected to the gate signal output terminal47. By the connection between the gate of the transistor241and the gate signal output terminal47, a gate signal output from the control device is input into the gate of the transistor241via the gate signal output terminal47.

A source (auxiliary source) of a current detecting transistor (not illustrated) provided in the transistor241is connected to the current detection terminal48. By the connection between the source of the current detecting transistor and the current detection terminal48, a current flowing from the source of the current detecting transistor is input into the control device.

A gate of the transistor251is connected to the gate signal output terminal51. By the connection between the gate of the transistor251and the gate signal output terminal51, a gate signal output from the control device is input into the gate of the transistor251via the gate signal output terminal51.

A source (auxiliary source) of a current detecting transistor (not illustrated) provided in the transistor251is connected to the current detection terminal52. By the connection between the source of the current detecting transistor and the current detection terminal52, a current flowing from the source of the current detecting transistor is input into the control device.

A gate of the transistor261is connected to the gate signal output terminal53. By the connection between the gate of the transistor261and the gate signal output terminal53, a gate signal output from the control device is input into the gate of the transistor261via the gate signal output terminal53.

A source (auxiliary source) of a current detecting transistor (not illustrated) provided in the transistor261is connected to the current detection terminal54. By the connection between the source of the current detecting transistor and the current detection terminal54, a current flowing from the current detecting transistor is input into the control device.

A gate of the transistor271is connected to the gate signal output terminal55. By the connection between the gate of the transistor271and the gate signal output terminal55, a gate signal output from the control device is output to the gate of the transistor271via the gate signal output terminal55.

A source (auxiliary source) of a current detecting transistor (not illustrated) provided in the transistor271is connected to the current detection terminal56. By the connection between the source of the current detecting transistor and the current detection terminal56, a current flowing from the current detecting transistor is input into the control device.

A gate of the transistor281is connected to the gate signal output terminal57. By the connection between the gate of the transistor281and the gate signal output terminal57, a gate signal output from the control device is input into the gate of the transistor281via the gate signal output terminal57.

A source (auxiliary source) of a current detecting transistor (not illustrated) provided in the transistor281is connected to the current detection terminal58. By the connection between the source of the current detecting transistor and the current detection terminal58, a current flowing from the current detecting transistor is input into the control device.

The gate signal is a pulse-like signal. The same gate signal is input into each of the transistors211,221,231,241. A potential difference between the low potential level and the high potential level of the gate signals output from the gate signal output terminals41,43,45,47becomes a gate-source voltage to be applied to the transistors211,221,231,241. Therefore, when the potential level of the gate signals output from the gate signal output terminals41,43,45,47is a high potential level, the transistors211,221,231,241are turned on (conduction state). On the other hand, when the potential level of the gate signals output from the gate signal output terminals41,43,45,47is a low potential level, the transistors211,221,231,241are turned off (non-conduction state).

The same gate signal is input into each of the transistors251,261,271,281. A potential difference between the low potential level and the high potential level of the gate signals output from the gate signal output terminals51,53,55,57becomes a gate-source voltage to be applied to the transistors251,261,271,281. Therefore, when the potential level of the gate signals output from the gate signal output terminals51,53,55,57is a high potential level, the transistors251,261,271,281are turned on (conduction state). On the other hand, when the potential level of the gate signals output from the gate signal output terminals51,53,55,57is a low potential level, the transistors251,261,271,281are turned off (non-conduction state).

The gate signals output from the gate signal output terminals41,43,45,47are signals having polarities opposite to those of the gate signals output from the gate signal output terminals51,53,55,57. Therefore, the control device controls On/Off of the transistors211,221,231,241in a predetermined cycle and controls Off/On of the transistors251,261,271,281in the cycle, which enables the U-phase inverter section12uto convert a DC voltage to be applied between the positive electrode terminal Pu and the negative electrode terminal Nu into an AC voltage and output the AC voltage from the intermediate terminal Mu to the load.

(Method for Manufacturing Semiconductor Module)

A method for manufacturing a semiconductor module according to this embodiment is described usingFIGS.4to8.FIG.4is a schematic plan view of the semiconductor module1for explaining the method for manufacturing the semiconductor module1, and is a view for explaining the initial positions and the movement state in the discharge of epoxy resins82of nozzles62u,63uprovided in a casting device6.FIG.5is a cross-sectional view of the semiconductor module1cut along the α-α line illustrated inFIG.4for explaining the method for manufacturing the semiconductor module1, and is a view for explaining the initial positions of the nozzles62u,63uprovided in the casting device6.FIG.6is a cross-sectional view of the semiconductor module1cut at a position corresponding to the α-α line illustrated inFIG.4for explaining the method for manufacturing the semiconductor module1, and is a view for explaining the movement state in the discharge of the epoxy resins82of the nozzles62u,63uprovided in the casting device6.FIG.7is a schematic plan view of the semiconductor module1for explaining the method for manufacturing the semiconductor module1, and is a view for explaining the positions where the nozzles62u,63uprovided in the casting device6complete the discharge of the epoxy resins82and stop.FIG.8is a schematic cross-sectional view of the semiconductor module1cut along the α-α line illustrated inFIG.7for explaining the method for manufacturing the semiconductor module1, and is a view for explaining the positions where the nozzles62u,63uprovided in the casting device6complete the discharge of the epoxy resins82and stop.

In the method for manufacturing the semiconductor module1according to this embodiment, the case11to which the gate signal output terminals41to57and the current detection terminals42to58for each of the U-phase, the V-phase, and the W-phase are attached is attached, by an adhesive, for example, to a base portion (not illustrated) provided with the DBC substrate14uand DBC substrates14v,14wmounted with the inverter circuits121u,121v,121w, respectively, and the cooling unit. This forms the casting region113uin which an upper part of the case11is opened and which is surrounded by the inner wall112of the case11and the DBC substrate14u, the casting region113vin which an upper part of the case11is opened and which is surrounded by the inner wall112of the case11and the DBC substrate14v, and the casting region113win which an upper part of the case11is opened and which is surrounded by the inner wall112of the case11and the DBC substrate14w.

In each of the U-phase inverter section12u, the V-phase inverter section12v, and the W-phase inverter section12w, corresponding points among the gate signal output terminals41to57and the current detection terminals42to58, and the semiconductor elements21to27are connected by bonding wires. Further, in each of the U-phase inverter section12u, the V-phase inverter section12v, and the W-phase inverter section12w, corresponding points among the positive electrode terminals Pu, Pv, Pw, the negative electrode terminals Nu, Nv, Nw, and the intermediate terminals Mu, Mv, Mw, and the wiring patterns formed on the DBC substrates14u,14v,14ware connected. Thus, the semiconductor module1is brought into a state in which parts other than the sealing sections81u,81v,81wand the control device outputting the gate signals are assembled. The semiconductor module1in this state is placed in a reduced-pressure environment.

Next, as illustrated inFIGS.4and5, the method for manufacturing the semiconductor module1includes arranging the nozzles62u,63uprovided in the casting device6casting the epoxy resins82into the casting regions113u,113v,113wat predetermined positions of the casting region113ufrom above the case11. The “above the case11” is the side where the casting regions113u,113v,113ware opened, i.e., the side opposite to the surface114, and where the fastening surface751u,751v,751wof the intermediate terminals Mu, Mv, Mw, respectively, are arranged. The two nozzles62u,63uare arranged from above the case11with a predetermined gap in a direction intersecting the direction in which the pair of long side portions111a,111bof the peripheral edge portion111constituting the case11are arranged. More specifically, as viewed in a direction orthogonal to the fastening surface751uof the intermediate terminal Mu (i.e., in a plan view), the nozzle62uis arranged at the center, as the predetermined position, of one region of regions obtained by bisecting the casting region113uin a direction in which the short side portion111cof the case11and the partition section112cof the inner wall112are arranged. The nozzle63uis arranged at the center of the other region of the bisected regions as the predetermined position. As illustrated inFIG.4, the nozzles62u,63uare arranged substantially on a line in the direction in which the short side portion111cof the case11and the partition section112cof the inner wall112are arranged, but, inFIG.5andFIGS.6and8described later, the nozzles62u,63uare displaced for ease of understanding.

The nozzles62v,63vprovided in the casting device6casting the epoxy resins82into the casting regions113u,113v,113ware arranged at the predetermined positions of the casting region113vfrom above the case11. The two nozzles62v,63vare arranged from above the case11with a predetermined gap in the direction intersecting the direction in which the pair of long side portions111a,111bof the peripheral edge portion111constituting the case11are arranged. More specifically, as viewed in a direction orthogonal to the fastening surface751vof the intermediate terminal My (i.e., in a plan view), the nozzle62vis arranged at the center, as the predetermined position, of one region of regions obtained by bisecting the casting region113vin a direction in which the partition section112cand the partition section112dof the inner wall112of the case11are arranged. The nozzle63vis arranged at the center of the other region of the bisected regions as the predetermined position. The nozzles62v,63vare arranged substantially on a line in the direction in which the partition section112cand the partition section112dof the inner wall112of the case11are arranged.

The nozzles62w,63wprovided in the casting device6casting the epoxy resins82into the casting regions113u,113v,113ware arranged at the predetermined positions of the casting region113wfrom above the case11. The two nozzles62w,63ware arranged from above the case11with a predetermined gap in the direction intersecting the direction in which the pair of long side portions111a,111bof the peripheral edge portion111constituting the case11are arranged. More specifically, as viewed in a direction orthogonal to the fastening surface751wof the intermediate terminal Mw (i.e., in a plan view), the nozzle62wis arranged at the center, as the predetermined position, of one region of regions obtained by bisecting the casting region113win a direction in which the partition section112dof the inner wall112of the case11and the short side portion111dof the peripheral edge portion111of the case11are arranged. The nozzle63wis arranged at the center of the other region of the bisected regions as the predetermined position. The nozzles62w,63ware arranged substantially on a line in the direction in which the partition section112dof the inner wall112of the case11and the short side portion111dof the peripheral edge portion111of the case11are arranged.

In this embodiment, the casting device6has the two nozzles62u,63u,62v,63v, and62w,63wfor each of the U-phase, the V-phase and the W-phase, respectively but may be configured to have two nozzles and sequentially discharge the epoxy resins82from the two nozzles into the casting regions113u,113v,113w.

Next, as illustrated inFIG.6, the epoxy resins82are discharged from the nozzles62u,63uinto the casting region113uwhile moving the nozzles62u,63uin the direction toward and away from the long side portion111a(an example of the one of the pair of long side portions111a,111b) of the pair of long side portions111a,111bof the peripheral edge portion111constituting the case11. The two nozzles62u,63uoperate similarly to each other under the control by a nozzle control unit61. Specifically, the nozzle control unit61provided in the casting device6moves the nozzles62u,63uin the direction toward the long side portion111aof the peripheral edge portion111while controlling the discharge amounts of the epoxy resins82(not illustrated inFIG.4) as illustrated by arrows Y1inFIGS.4and6. When the nozzle control unit61brings the nozzles62u,63uclose to the long side portion111aof the peripheral edge portion111up to a predetermined distance, the nozzle control unit61then moves the nozzles62u,63uin the direction away from the long side portion111aof the peripheral edge portion111while controlling the discharge amounts of the epoxy resins82as illustrated by arrows Y2inFIGS.4and6. Thus, the nozzle control unit61reciprocates the nozzles62u,63ua plurality of times in the longitudinal direction of the casting region113u, and fills the casting region113uwith the epoxy resins82.

The epoxy resins82are discharged from the nozzles62v,63vinto the casting region113vwhile moving the nozzles62v,63vin the direction toward and away from the long side portion111a(an example of the one of the pair of long side portions111a,111b) of the pair of long side portions111a,111bof the peripheral edge portion111constituting the case11. The two nozzles62v,63voperate similarly to each other under the control by the nozzle control unit61. Specifically, the nozzle control unit61provided in the casting device6moves the nozzles62v,63vin the direction toward the long side portion111aof the peripheral edge portion111while controlling the discharge amounts of the epoxy resins82as illustrated by arrows Y1inFIGS.4and6. When the nozzle control unit61brings the nozzles62v,63vclose to the long side portion111aof the peripheral edge portion111up to a predetermined distance, the nozzle control unit61then moves the nozzles62v,63vin the direction away from the long side portion111aof the peripheral edge portion111while controlling the discharge amounts of the epoxy resins82as illustrated by arrows Y2inFIGS.4and6. Thus, the nozzle control unit61reciprocates the nozzles62v,63va plurality of times in the longitudinal direction of the casting region113v, and fills the casting region113vwith the epoxy resins82.

The epoxy resins82are discharged from the nozzles62w,63winto the casting region113wwhile moving the nozzles62w,63win the direction toward and away from the long side portion111a(an example of the one of the pair of long side portions111a,111b) of the pair of long side portions111a,111bof the peripheral edge portion111constituting the case11. The two nozzles62w,63woperate similarly to each other under the control by the nozzle control unit61. Specifically, the nozzle control unit61provided in the casting device6moves the nozzles62w,63win the direction toward the long side portion111aof the peripheral edge portion111while controlling the discharge amounts of the epoxy resins82as illustrated by arrows Y1inFIGS.4and6. When the nozzle control unit61brings the nozzles62w,63wclose to the long side portion111aof the peripheral edge portion111up to a predetermined distance, the nozzle control unit61then moves the nozzles62w,63win the direction away from the long side portion111aof the peripheral edge portion111while controlling the discharge amounts of the epoxy resins82as illustrated by arrows Y2inFIGS.4and6. Thus, the nozzle control unit61reciprocates the nozzles62w,63wa plurality of times in the longitudinal direction of the casting region113w, and fills the casting region113wwith the epoxy resins82.

The nozzle control unit61reciprocates the nozzles62u,63ua plurality of times (for example, twice) in the longitudinal direction of the casting region113u, and then moves the nozzles62u,63uin the direction toward the long side portion111aof the peripheral edge portion111. As illustrated inFIGS.7and8, the nozzle control unit61stops the movement of the nozzles62u,63uat positions close to the structure31uside of the casting region113u, and stops the discharge of the epoxy resins82into the casting region113uand completes the formation of the sealing section81u.

When the casting region113uis viewed from above the case11(i.e., in a plan view), the nozzle control unit61provided in the casting device6stops the movement of the nozzles62u,63uin a region of the casting region113uincluded between a virtual straight line VL3uincluding a center C2uof the casting region113uin the direction in which the pair of long side portions111a,111bof the peripheral edge portion111constituting the case11are arranged and intersecting the direction and the structure31u. In a plan view, the center C2ucoincides with the center C1u(seeFIG.1) and the virtual straight line VL3ucoincides with the virtual straight line VL1u(seeFIG.1).

The position where the nozzle62ustops is a position above the region A1u. The position where the nozzle63ustops is a position above the region A2u. Therefore, in the step of forming the sealing section81u, the epoxy resin82is finally discharged from the nozzle62uinto the casting region113uat the position corresponding to the region A1uduring the formation of the sealing section81u. The number of times in which the nozzles62u,63umove to enter is larger in the region of the casting region113uincluded between the virtual straight line VL3uand the structure31uthan in the region of the casting region113uincluded between the virtual straight line VL3uand the long side portion112bof the inner wall112. Therefore, the discharge amounts of the epoxy resins82are larger in the region of the casting region113uincluded between the virtual straight line VL3uand the structure31uthan in the region of the casting region113uincluded between the virtual straight line VL3uand the long side portion112bof the inner wall112. Thus, in the sealing section81ufinally formed in the casting region113u, the thickness of the region of the casting region113uincluded between the virtual straight line VL3uand the structure31uis larger than the thickness of the region of the casting region113uincluded between the virtual straight line VL3uand the long side portion112bof the inner wall112as illustrated inFIG.8. Further, in the surface811uof the sealing section81ufinally formed in the casting region113u, the weld lines WLu concentrically spreading around the regions A1u, A2uas the centers are generated close to the structure31uas illustrated inFIG.7.

The nozzle control unit61reciprocates the nozzles62v,63va plurality of times (for example, twice) in the longitudinal direction of the casting region113v, and then moves the nozzles62v,63vtoward the long side portion111aof the peripheral edge portion111. As illustrated inFIG.7, the nozzle control unit61stops the movement of the nozzles62v,63vat positions close to the structure31vside of the casting region113v, and stops the discharge of the epoxy resins82into the casting region113vand completes the formation of the sealing section81v.

When the casting region113vis viewed from above the case11(i.e., in a plan view), the nozzle control unit61provided in the casting device6stops the movement of the nozzles62v,63vin a region of the casting region113vincluded between a virtual straight line VL3vincluding a center C2vof the casting region113vin the direction in which the pair of long side portions111a,111bof the peripheral edge portion111constituting the case11are arranged and intersecting the direction and the structure31v. In a plan view, the center C2vcoincides with the center C1v(seeFIG.1) and the virtual straight line VL3vcoincides with the virtual straight line VL1v(seeFIG.1).

The position where the nozzle62vstops is a position above the region A1v. The position where the nozzle63vstops is a position above the region A2v. Therefore, in the step of forming the sealing section81v, the epoxy resin82is finally discharged from the nozzle62vinto the casting region113vat the position corresponding to the region A1vduring the formation of the sealing section81v. The number of times in which the nozzles62v,63vmove to enter is larger in the region of the casting region113vincluded between the virtual straight line VL3vand the structure31vthan in the region of the casting region113vincluded between the virtual straight line VL3vand the long side portion112bof the inner wall112. Therefore, the discharge amounts of the epoxy resins82are larger in the region of the casting region113vincluded between the virtual straight line VL3vand the structure31vthan in the region of the casting region113vincluded between the virtual straight line VL3vand the long side portion112bof the inner wall112. Thus, in the sealing section81vfinally formed in the casting region113v, the thickness of the region of the casting region113vincluded between the virtual straight line VL3vand the structure31vis larger than the thickness of the region of the casting region113vincluded between the virtual straight line VL3vand the long side portion112bof the inner wall112. Further, in the surface811vof the sealing section81vfinally formed in the casting region113v, the weld lines WLv concentrically spreading with the regions A1v, A2vas the centers are generated close to the structure31vas illustrated inFIG.7.

The nozzle control unit61reciprocates the nozzles62w,63wa plurality of times (for example, twice) in the longitudinal direction of the casting region113w, and then moves the nozzles62w,63wtoward the long side portion111aof the peripheral edge portion111. As illustrated inFIG.7, the nozzle control unit61stops the movement of the nozzles62w,63wat positions close to the structure31wside of the casting region113w, and stops the discharge of the epoxy resins82into the casting region113wand completes the formation of the sealing section81w.

When the casting region113wis viewed from above the case11(i.e., in a plan view), the nozzle control unit61provided in the casting device6stops the movement of the nozzles62w,63win a region of the casting region113wincluded between a virtual straight line VL3wincluding a center C2wof the casting region113win the direction in which the pair of long side portions111a,111bof the peripheral edge portion111constituting the case11are arranged and intersecting the direction and the structure31w. In a plan view, the center C2wcoincides with the center C1w(seeFIG.1) and the virtual straight line VL3wcoincides with the virtual straight line VL1w(seeFIG.1).

The position where the nozzle62wstops is a position above the region A1w. The position where the nozzle63wstops is a position above the region A2w. Therefore, in the step of forming the sealing section81w, the epoxy resin82is finally discharged from the nozzle62winto the casting region113wat the position corresponding to the region A1wduring the formation of the sealing section81w. The number of times in which the nozzles62w,63wmove to enter is larger in the region of the casting region113wincluded between the virtual straight line VL3wand the structure31wthan in the region of the casting region113wincluded between the virtual straight line VL3wand the long side portion112bof the inner wall112. Therefore, the discharge amounts of the epoxy resins82are larger in the region of the casting region113wincluded between the virtual straight line VL3wand the structure31wthan in the region of the casting region113wincluded between the virtual straight line VL3wand the long side portion112bof the inner wall112. Thus, in the sealing section81wfinally formed in the casting region113w, the thickness of the region of the casting region113wincluded between the virtual straight line VL3wand the structure31wis larger than the thickness of the region of the casting region113wincluded between the virtual straight line VL3wand the long side portion112bof the inner wall112. Further, in the surface811wof the sealing section81wfinally formed in the casting region113w, the weld lines WLw concentrically spreading with the regions A1w, A2was the centers are generated close to the structure31was illustrated inFIG.7.

When the casting of the epoxy resins82into the casting regions113u,113v,113wis completed, the nozzle control unit61provided in the casting device6retracts the nozzles62u,63u,63v,63v,62w,63wfrom above the case11. Thereafter, the control device is attached to the case11, and the epoxy resins82cast into the casting regions113u,113v,113ware cured to form the sealing sections81u,81v,81w, so that the semiconductor module1is completed.

(Effects of Semiconductor Module and Method for Manufacturing Semiconductor Module)

The effects of the semiconductor module and the method for manufacturing a semiconductor module according to this embodiment are described usingFIG.9referring toFIGS.5and7. In this embodiment, the effects in the U-phase inverter section12u, the V-phase inverter section12v, and the W-phase inverter section12ware the same. Therefore, hereinafter, the effects of the semiconductor module1and the method for manufacturing the semiconductor module1are described taking the U-phase inverter section12uas an example.FIG.9is a view for explaining the effects of the semiconductor module1and the method for manufacturing the semiconductor module1according to this embodiment, in which the nozzles62u,63uin the state where the casting of the epoxy resins82is completed are also illustrated in the schematic cross-sectional view of the semiconductor module1cut along the α-α line illustrated inFIG.7.

When an epoxy resin is cast into a casting region, an unexpected bubble is sometimes generated in the epoxy resin. The casting, i.e., sealing, of the epoxy resin is carried out under reduced pressure. Therefore, when the epoxy resin is cast, droplets of resin materials formed by the breakage of the bubble are sometimes scattered far away such that the droplets reach a peripheral edge portion of a case with a place where the bubble is broken as the starting point.

As illustrated inFIG.9, the semiconductor module1includes the structure31u. The structure31uis arranged between the nozzles62u,63uand the fastening surface751uof the intermediate terminal Mu. The structure31uhas the gate signal output terminals41to57and the current detection terminals42to58. Portions projecting from the long side portion112aof the inner wall112of the gate signal output terminals41to57and the current detection terminals42to58are higher than a discharge port621of the nozzle62u, a discharge port631of the nozzle63u, and the fastening surface751uof the intermediate terminal Mu with the surface114of the case11as a reference. Therefore, when viewed from the sides of the nozzles62u,63u, the structure31uis arranged to shield the fastening surface751uof the intermediate terminal Mu by the gate signal output terminals41to57and the current detection terminals42to58.

As illustrated inFIG.9, the nozzles62u,63ustop at positions where the discharge ports621,631of the epoxy resins82of the nozzles62u,63u, respectively, at the time when the discharge of the epoxy resin82is completed, are lower than the structure31u. The epoxy resins82remain in the discharge port621of the nozzle62uand the discharge port631of the nozzle63uat the time when the discharge of the epoxy resins82is completed.

The semiconductor module1includes the structure31uhaving the gate signal output terminals41to57and the current detection terminals42to58arranged to shield the fastening surface751uof the intermediate terminal Mu. As illustrated inFIG.7, the gate signal output terminals41to57and the current detection terminals42to58are arranged in a plurality of rows in the direction in which the pair of long side portions111a,111bof the peripheral edge portion111constituting the case11are arranged and each have a surface having a predetermined spread when viewed in the direction in which the pair of long side portions111a,111bare arranged. Therefore, even when bubbles are generated in the epoxy resins82remaining in the discharge port621of the nozzle62uand the discharge port631of the nozzle63u, and the generated bubbles are broken and droplets DR are scattered toward the intermediate terminal Mu, the droplets DR adhere to at least one of the surfaces of the gate signal output terminals41to57and the current detection terminals42to58as illustrated inFIG.9.

When viewed in the direction in which the pair of long side portions111a,111bare arranged, the adjacent terminals among the gate signal output terminals41to57and the current detection terminals42to58are arranged not to overlap each other and are arranged at intervals of 0.5 mm or less, for example.

Between the gate signal output terminals41to57and the current detection terminals42to58, and the intermediate terminal Mu, conductive substances, such as terminals having a workload larger than that of the gate signal output terminals41to57and the current detection terminals42to58, are not present. The droplets DR have a property of being drawn to the conductive substances. Therefore, even when the gate signal output terminals41to57and the current detection terminals42to58are arranged such that the terminals, which are adjacent to each other when viewed in the direction in which the pair of long side portions111a,111bare arranged (i.e., a direction in which the droplets DR move toward the intermediate terminal Mu side), are arranged at intervals, the droplets DR are drawn to any of the gate signal output terminals41to57and the current detection terminals42to58and adhere to the surfaces of the drawn terminals.

Further, even when the droplet DR flies beyond the gate signal output terminals41to57and the current detection terminals42to58toward the intermediate terminal Mu side, problems do not occur in a case where the droplet DR reaches not the fastening surface751uof the intermediate terminal Mu but the outside of the case11. As illustrated inFIG.9, a distance parallel to the fastening surface751uof the intermediate terminal Mu from the structure31uto the outer peripheral end of the case11is defined as D1. A distance parallel to the fastening surface751uof the intermediate terminal Mu from the virtual straight line VL3u(seeFIG.7) including the center C2u(seeFIG.7) of the casting region113uto the structure31uis defined as D2.

As illustrated inFIG.9, it is assumed that the nozzles62u,63ustop within the range of a distance D3in which the distance from the structure31uto the casting region113uis equal to the distance D1. In this case, the droplets DR collide with the structure31uor the inner wall112regardless of the magnitude of the energy generated when the bubbles generated in the epoxy resins82remaining in the discharge ports621,631of the nozzles62u,63u, respectively, are broken, and therefore the droplets DR do not adhere to the fastening surface751uof the terminal Mu.

Alternatively, it is assumed that the nozzles62u,63ustop within a distance D4in which the distance from the structure31uto the casting region113uis longer than the distance D3and is equal to or less than the length up to the center C2u. In this case, when the energy generated when the bubbles generated in the epoxy resins82remaining in the discharge ports621,631of the nozzles62u,63u, respectively, are broken is small, the droplets DR collide with the structure31uor the inner wall112, and therefore do not adhere to the fastening surface751uof the intermediate terminal Mu.

On the other hand, when the nozzles62u,63ustop within the range of the distance D4and the energy generated when the bubbles generated in the epoxy resins82remaining in the discharge ports621,631of the nozzles62u,63u, respectively, are broken is large, the droplet DR flies beyond the intermediate terminal Mu and reaches the outside of the case11, and therefore do not adhere to the fastening surface751uof the intermediate terminal Mu.

Further, it is assumed that the nozzles62u,63ustop in the range where the distance from the structure31uto the casting region113uis longer than the distance D2. In this case, the droplets DR collide with the structure31uor the inner wall112or do not reach the structure31uor the inner wall112regardless of the magnitude of the energy generated when the bubbles generated in the epoxy resins82remaining in the discharge ports621,631of the nozzles62u,63u, respectively, are broken, and therefore the droplets DR do not adhere to the fastening surface751uof the intermediate terminal Mu.

Thus, in the manufacture of the semiconductor module1, the droplets DR can be prevented from reaching the fastening surface751uof the intermediate terminal Mu. As a result, the semiconductor module1can prevent an increase in contact resistance between the fastening surface751uof the intermediate terminal Mu and a cable, and therefore can prevent the heat generation in the intermediate terminal Mu and can cause a desired current to flow to the load from the U-phase inverter section12u. Further, the semiconductor module1prevents the adhesion of the droplets DR to the fastening surface751uof the intermediate terminal Mu, and therefore is free from a problem that a worker who fastens the cable to the intermediate terminal Mu fastens the cable to the intermediate terminal Mu without noticing the droplets DR.

The semiconductor module1includes the structure31vhaving the same configuration as that of the structure31uin the V-phase inverter section12vand the structure31whaving the same configuration as that of the structure31uin the W-phase inverter section12w, as with the U-phase inverter section12u. Further, in the manufacture of the semiconductor module1, the movement of the nozzles62v,63v(seeFIG.7) is stopped at the positions close to the structure31vside of the casting region113v(i.e., within the range of distance D2), and the discharge of the epoxy resins82into the casting region113vis stopped. Similarly, in the manufacture of the semiconductor module1, the movement of the nozzles62w,63w(seeFIG.7) is stopped at the positions close to the structure31wside of the casting region113w(i.e., within the range of distance D2), and the discharge of the epoxy resins82into the casting region113wis stopped. Thus, the semiconductor module1can prevent the adhesion of the droplets DR to the intermediate terminals Mv, Mw, and therefore can prevent the heat generation in the intermediate terminals Mv, Mw and can cause a desired current to flow to the load from each of the V-phase inverter section12vand the W-phase inverter section12w, respectively. Further, the semiconductor module1is free from a problem that a worker who fastens the cable to the intermediate terminals Mv, Mw fastens cables to the intermediate terminals Mv, Mw without noticing the droplets DR.

To the gate signal output terminals41to57and the current detection terminals42to58, a current smaller than the current flowing to the intermediate terminals Mu, Mv, Mw flows, and a voltage lower than the voltage applied to the intermediate terminals Mu, Mv, Mw is applied. Therefore, even when the droplets DR adhere to the gate signal output terminals41to57and the current detection terminals42to58, problems, such as the heat generation and the inability to transmit desired gate signals and to the transistors211to281and the inability to input currents flowing from the current detecting transistors to the control device, do not occur.

As described above, the semiconductor module1according to this embodiment includes: the case11having the inner wall112defining the casting regions113u,113v,113wwhere the transistors211to281are arranged and the peripheral edge portion111arranged outside the inner wall112and formed in a rectangular annular shape; the intermediate terminals Mu, Mv, Mw arranged in the long side portion111aof the pair of long side portions111a,111bforming a part of the peripheral edge portion111and facing each other, having the fastening surfaces751u,751v,751w, respectively, to which a cable connected to a load as a drive target is fastened, and connected to the transistors211to281; the structures31u,31v,31warranged in the long side portion112aof the inner wall112to be adjacent to the long side portion111awhere the intermediate terminals Mu, Mv, Mw are arranged and higher than the fastening surfaces751u,751v,751w, respectively; and the sealing sections81u,81v,81wmade of the epoxy resins82, having the weld lines WLu, WLv, WLw formed close to the sides of the structures31u,31v,31won the surfaces811u,811v,811w, and cast into the casting regions113u,113v,113w, respectively, to seal the transistors211to281.

The method for manufacturing the semiconductor module1according to this embodiment is a method for manufacturing a semiconductor module, the semiconductor module being the semiconductor module1according to this embodiment, and the method includes: arranging the nozzles62u,63u,62v,63v,62w,63wprovided in the casting device6casting the epoxy resins82into the casting regions113u,113v,113wat the predetermined positions of the casting regions113u,113v,113w, respectively, from above the case11; discharging the epoxy resins82from the nozzles62u,63u,62v,63v,62w,63winto the casting regions113u,113v,113wwhile moving the nozzles62u,63u,62v,63v,62w,63win the direction toward and away from the long side portion111aof the pair of long side portions111a,111bof the peripheral edge portion111; stopping the movement of the nozzles62u,63u,62v,63v,62w,63wat the positions close to the sides of the structures31u,31v,31wof the casting regions113u,113v,113w(regions A1u, A2u, A1v, A2v, A1w, A2w), respectively; and stopping the discharge of the epoxy resins82into the casting regions113u,113v,113wand completing the formation of the sealing sections81u,81v,81w, respectively.

This enables the semiconductor module1to prevent the adhesion of an epoxy resin to terminals to which at least one of a large current and a high voltage is supplied.

The present invention can be variously modified without being limited to the embodiment described above.

The semiconductor module according to the embodiment described above has the structures having the gate signal output terminals and the current detection terminals, but the present invention is not limited thereto. The structure may have configurations other than the gate signal output terminals and the current detection terminals insofar as the structure is arranged between the sealing section and the intermediate terminal. For example, even when the structure has a long side portion of an inner wall formed higher than a fastening surface of an intermediate terminal, the same effects as those of the semiconductor module according to the embodiment described above can be obtained.

In the method for manufacturing a semiconductor module according to the embodiment described above, two nozzles are used for each casting region, but the present invention is not limited thereto. For example, one or three or more nozzles may be used for each casting region.

In the embodiment described above, the transistor provided in each of the semiconductor elements are configured by a MOSFET but may be configured by an insulated gate bipolar transistor (IGBT).

In the embodiment described above, the gate signal output terminals and the current detection terminals are arranged in two rows, but may be arranged in one row or three or more rows.

In the embodiment described above, the gate signal output terminals and the current detection terminals each have a surface having a predetermined spread toward the casting regions, but may be press-fit terminals having a through hole in the surface.

The semiconductor module according to the embodiment described above has the inner wall constituting the case having substantially the same height as that of the fastening surface of each of the positive electrode terminals and the negative electrode terminals, but the present invention is not limited thereto. The inner wall constituting the case may have a height higher than the fastening surface of each of the positive electrode terminals and the negative electrode terminals. This enables the semiconductor module to prevent the adhesion of droplets to the fastening surfaces of the positive electrode terminals and the negative electrode terminals in manufacturing.

The technical scope of the present invention is not limited to the illustrated and described exemplary embodiment, and also includes all embodiments that provide effects equivalent to the effects intended by the present invention. Further, the technical scope of the present invention is not limited to combinations of the features of the invention defined by claims, and can be defined by any desired combination of specific features among all the disclosed features.

REFERENCE SIGNS LIST