APPARATUS, COMPUTER-READABLE MEDIUM, AND METHOD FOR HIGH-THROUGHPUT SCREEN SHARING

Methods, apparatus, systems, and articles of manufacture are disclosed for high-throughput screen sharing. In some examples, host-viewer synchronizer circuitry determines whether a share mode is in an application or desktop share mode. In some examples, the host-viewer synchronizer circuitry tracks a visual display arrangement information of visual data on a host machine. The host-viewer synchronizer circuitry then displays the tracked visual display arrangement on a viewer machine through either replicating the tracked visual display arrangement information for one or more screen captures or for an amount of application data, depending on the type of share mode.

FIELD OF THE DISCLOSURE

This disclosure relates generally to sharing a screen across two or more computer systems.

BACKGROUND

Many modern computers utilize applications to share user screens among users who can be remote from each other. This is an effective way to share information and collaborate when people are not in the same room. Screen sharing involves continuously capturing the content of the screen of a host system being shared and sending a stream of the screen captures to one or more remote viewer systems. The remote systems display the stream to see what the sharing screen is displaying to essentially create as close to a real-time video stream as possible that is uploaded by the host system and simultaneously downloaded by each remote viewer system.

The figures are not to scale. In general, the same reference numbers will be used throughout the drawing(s) and accompanying written description to refer to the same or like parts. As used herein, connection references (e.g., attached, coupled, connected, and joined) may include intermediate members between the elements referenced by the connection reference and/or relative movement between those elements unless otherwise indicated. As such, connection references do not necessarily infer that two elements are directly connected and/or in fixed relation to each other. As used herein, stating that any part is in “contact” with another part is defined to mean that there is no intermediate part between the two parts.

Unless specifically stated otherwise, descriptors such as “first,” “second,” “third,” etc., are used herein without imputing or otherwise indicating any meaning of priority, physical order, arrangement in a list, and/or ordering in any way, but are merely used as labels and/or arbitrary names to distinguish elements for ease of understanding the disclosed examples. In some examples, the descriptor “first” may be used to refer to an element in the detailed description, while the same element may be referred to in a claim with a different descriptor such as “second” or “third.” In such instances, it should be understood that such descriptors are used merely for identifying those elements distinctly that might, for example, otherwise share a same name. As used herein, “approximately” and “about” refer to dimensions that may not be exact due to manufacturing tolerances and/or other real world imperfections. As used herein “substantially real time” refers to occurrence in a near instantaneous manner recognizing there may be real world delays for computing time, transmission, etc. Thus, unless otherwise specified, “substantially real time” refers to real time+/−1 second. As used herein, the phrase “in communication,” including variations thereof, encompasses direct communication and/or indirect communication through one or more intermediary components, and does not require direct physical (e.g., wired) communication and/or constant communication, but rather additionally includes selective communication at periodic intervals, scheduled intervals, aperiodic intervals, and/or one-time events. As used herein, “processor circuitry” is defined to include (i) one or more special purpose electrical circuits structured to perform specific operation(s) and including one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors), and/or (ii) one or more general purpose semiconductor-based electrical circuits programmed with instructions to perform specific operations and including one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors). Examples of processor circuitry include programmed microprocessors, Field Programmable Gate Arrays (FPGAs) that may instantiate instructions, Central Processor Units (CPUs), Graphics Processor Units (GPUs), Digital Signal Processors (DSPs), XPUs, or microcontrollers and integrated circuits such as Application Specific Integrated Circuits (ASICs). For example, an XPU may be implemented by a heterogeneous computing system including multiple types of processor circuitry (e.g., one or more FPGAs, one or more CPUs, one or more GPUs, one or more DSPs, etc., and/or a combination thereof) and application programming interface(s) (API(s)) that may assign computing task(s) to whichever one(s) of the multiple types of the processing circuitry is/are best suited to execute the computing task(s).

DETAILED DESCRIPTION

Screen sharing applications are beneficial for collaboration and information sharing among remote systems. Unfortunately, a stream of screen captures (e.g., frames) at the host system sharing the screen is similar to a video stream. It is common knowledge that the majority of Internet bandwidth is used by video streams because of the significant data sizes of a stream of video frames. In many situations the bandwidth requirements are greater than what is available for a smooth stream. Thus, users commonly see frame rates drop and/or latency increase as a result. In screen sharing applications, latency and low bandwidth makes collaborating on a video/screen sharing call much more cumbersome because of dropped or delayed frames and unwanted poor resolution issues.

FIG. 1is an example schematic illustration of example circuitry to implement high-throughput screen sharing across multiple computer systems. In the illustrated example, an example host machine100and an example viewer machine102are shown. In some examples, the host machine100shares information displayed on a host display/screen with the viewer machine100. Although the description will focus on the host machine100sharing information with the viewer machine102, in other examples, the host machine100and the viewer machine102may reverse roles (e.g., the host becomes the viewer and the viewer becomes the host) because, in a screen sharing environment among remote systems, the viewer may need to share the viewer screen to the host, which is common in a collaborative setting.

Returning to the host machine100, in some examples it is a desktop computer, a laptop, a workstation, a server, a mobile phone, a watch, a tablet, a personal handheld device, or any one or more other types of computer systems.

In the illustrated example inFIG. 1, the host machine100includes example processor circuitry104(described in more detail as example processor circuitry812inFIG. 8). In some examples, the processor circuitry104is a general purpose central processing unit (CPU), a fixed programmable gate array (FPGA), or another type of processor. The example processor circuitry104includes an example host-viewer synchronizer106A, an example application data uploader108A, and an example remote viewer data transferer110A.

In some examples, the host machine100also includes one or more applications running on the system such as example application112A. The example application112A may be a word processing application, a spreadsheet application, a presentation application, a web browser, or any other type of application capable of being run on the processor circuitry104. In some examples, the host machine100has an operating system (OS) being executed by the processor circuitry100to manage resources, applications, peripherals, etc.

In some examples, the operating system includes an example OS kernel114that manages low level services and other subsystems utilized by the host machine100. In some examples, the OS kernel114interfaces with one or more peripheral input drivers, such as the example peripheral input driver116. The example peripheral input driver116provides an interface to a peripheral communicatively coupled to the host machine100, such as example peripheral120.

The term “communicatively coupled” refers to the peripheral120and the host machine100being capable of passing information/data back and forth (either in a wired or wireless format). For example, if the peripheral120is an electronic mouse, the mouse may receive user input (e.g., movement and clicks) and provide that information to the OS kernel114through the peripheral input driver116. In another example, the peripheral120is a display. In this example, an example graphics driver118provides an interface between the host machine100and the display. The example host machine100may send information from a graphics processing unit (GPU) or other circuitry capable of providing display data to the graphics driver118for display purposes on the display peripheral.

In some examples, there are multiple peripherals communicatively coupled to the host machine (e.g., a display, a keyboard, a mouse, a printer, a projector, and/or one or more speakers, among other peripherals).

In the illustrated example inFIG. 1, there is also the example viewer machine102. In some examples, the viewer machine102is a computer system that has been tasked with viewing a shared screen (e.g., being shared by the host machine100). In some examples, the viewer machine100is a desktop computer, a laptop, a workstation, a server, a mobile phone, a watch, a tablet, a personal handheld device, or any one or more other types of computer systems. In some examples, the host machine100and the viewer machine102can be two copies of a set of homogenous computer systems. In other examples, the host machine100and the viewer machine102can two completely different and unique (i.e., heterogeneous) computer systems.

In the illustrated example inFIG. 1, the viewer machine102includes example processor circuitry122(also described in more detail as example processor circuitry812inFIG. 8). In some examples, the processor circuitry122is a general purpose central processing unit (CPU), a fixed programmable gate array (FPGA), or another type of processor. The example processor circuitry122also includes an example host-viewer synchronizer106B, an example application data uploader108B, and an example remote viewer data transferer110B. In some examples, the elements106A and B,108A and B, and110A and B (in host machine100and viewer machine102, respectively), are two instances of the same logic circuitry on two different systems (e.g., host machine100and viewer machine102).

In some examples, the viewer machine102also includes one or more applications running on the system such as example application112B. The example application112B may be a word processing application, a spreadsheet application, a presentation application, a web browser, or any other type of application capable of being run on the processor circuitry122. In some examples, the application112A and the application112B are two instances of the same application running on the two computer systems (e.g., host machine100and viewer machine102).

In some examples, the viewer machine102also has an OS being executed by the processor circuitry122to manage resources, applications, peripherals, etc.

In some examples, the OS includes an example OS kernel124that manages low level services and other subsystems utilized by the viewer machine102. In some examples, the OS kernel124interfaces with one or more peripheral input drivers, such as an example peripheral input driver126. The example peripheral input driver126provides an interface to a peripheral communicatively coupled to the viewer machine102, such as example peripheral130.

For example, if the peripheral130is a keyboard, the keyboard may receive user input (e.g., typing input) and provide that information to the OS kernel124through the peripheral input driver126. In another example, the peripheral130is a display. In this example a graphics driver128provides an interface between the viewer machine102and the display. The example viewer machine102may send information from a graphics processing unit (GPU) or other circuitry capable of providing display data to the graphics driver128for display purposes on the display peripheral.

In some examples, the host machine100and viewer machine102are communicatively coupled through an example communication link132. The communication link may be wired or wireless and can use any known communication protocol that circuitry within each of the machines is capable of transmitting and receiving to effectively communicate. For example, the communication link132may utilize an ethernet protocol, one of many wireless protocols, cellular protocols, or any other known protocol that provides a standard method for sending and receiving data between two or more systems.

In some examples, the host machine100shares information displayed on its screen/display (e.g., a display peripheral coupled to the host machine100) with the viewer machine. The remaining elements ofFIG. 1will be described in the context of the example flow charts illustrated inFIGS. 2-7, which are discussed below.

FIG. 2is a flowchart representative of example machine readable instructions that may be executed by example processor circuitry to implement a high-throughput screen sharing process. In some examples, the process flow is performed by the host-viewer synchronizer circuitry106A inFIG. 1and the host-viewer synchronizer circuitry106B inFIG. 1.

In the illustrated example ofFIG. 2, the process begins when the host machine (100inFIG. 1) begins sharing visual data on the screen with a remote viewer machine (102inFIG. 1).

At block200, the example host-viewer synchronizer circuitry106A determines whether a share mode to share the visual data from the host machine100is in an application share mode or a desktop share mode. The application share mode is defined as a share mode where the host machine100visually shares the present content of an application (e.g., application112A) running on and being displayed by the host machine100with the viewer machine102. The desktop share mode is defined as a share mode where the host machine100visually shares screen captures of the present content of the host machine's100OS's desktop. In some examples, this may include the wallpaper, icons, and any open application windows on the desktop, among other items.

In some examples, the share mode is determined automatically by the focus (e.g., the active window in the OS) of what is displayed on the host machine100screen. For example, if the active window is an application such as a word processor, then the share mode may be set to that application. In other examples, the share mode is a manual determination for the user when sharing their screen. For example, a selection window in a user interface of the sharing application may allow the user to decide if they want an application as the focus or the desktop as the focus.

Returning toFIG. 1, the share mode determination may be implemented as reading an example share mode flag (S/M FLAG)146A in an example host-viewer synchronizer memory structure144A. In some examples, the host-viewer synchronizer memory structure144A is a structure initialized in a memory in the host machine100when the host machine100begins sharing its screen/display contents. The example host-viewer synchronizer memory structure144A may be located in a main system memory, in a local memory to the processor, in a cache in the processor circuitry104, implemented in one or more registers associated with the processor circuitry104, in a non-volatile storage system in the host machine, or anywhere else capable of storing a memory structure.

InFIG. 2, at block202, regardless of which share mode is currently active, the example host-viewer synchronizer circuitry106A then begins to track visual display arrangement information of visual data on the host machine's100screen/display. In some examples, the example host-viewer synchronizer circuitry106A has access to a graphics driver118frame buffer of the host machine100screen as well as access to inputs from any peripherals through one or more peripheral input driver(s)116. The visual display arrangement information is defined as the informational I/O aspects of how the host machine100screen presently looks and the reasons behind any changes. For example, the host-viewer synchronizer circuitry106A has access to inputs that modify and manipulate the content of the host machine100screen/display as well as to the actual output of the host machine100display.

InFIG. 1, in some examples, the host-viewer synchronizer circuitry106A initializes and maintains an example tracking buffer148A (e.g., stored in the host-viewer synchronizer memory structure144A) to keep track of the visual display arrangement information of the visual data on the host machine100screen. In some examples, the inputs and outputs discussed above are stored in the tracking buffer148A for use by the host-viewer synchronizer circuitry106A when sending visual data/information to the viewer machine102.

InFIG. 2, after gathering the visual display arrangement information of the visual data (and storing it in the tracking buffer148A), the example host-viewer synchronizer circuitry106A transfers the visual display arrangement information to the example host-viewer synchronizer circuitry106B on the viewer machine102(e.g., across the communication link132).

InFIG. 1, in some examples, an example synchronizer data packet134is defined for any instance of the host-viewer synchronizer circuitry, such as106A and B. In some examples, the packet definition includes any necessary data to be transferred between a host and a viewer. For example, packets may include example visual display arrangement information136, example application data138, example peripheral usage data140, and/or example screen capture data142. In some examples, the specific data sent per synchronizer data packet134is added depending on the current need of the host-to-viewer share stream type.

In some examples, an example packet constructor/deconstructor memory space150A in the host-viewer synchronization memory structure144A provides the host-viewer synchronizer circuitry106A a range of memory that can be used to construct the synchronizer data packet(s)134as the host. In some examples, the viewer machine102also has an example host-viewer synchronizer memory structure144B with the same elements, such as an example share mode flag location146B, an example tracking buffer148B (e.g., when the viewer turns into the host), and an example packet constructor/deconstructor memory space150B (e.g., to deconstruct the arriving packet(s)134as the viewer).

InFIG. 2, once the visual display arrangement information has been tracked and transferred to the viewer machine102, then, if the share mode was determined to be in desktop share mode, at block204, the host-viewer synchronizer circuitry106B replicates the tracked visual display arrangement on the viewer machine100by displaying an amount of visual data of one or more screen captures of the host machine's100OS desktop. In some examples, the screen captures are constructed from the screen capture data142in the synchronizer data packet(s)134. More details of the processes that take place in the desktop mode are discussed below in the description ofFIGS. 3-4.

In some examples, once the visual display arrangement information has been tracked and transferred to the viewer machine102, then, if the share mode was determined to be in application share mode, at block206, the host-viewer synchronizer circuitry106B replicates the tracked visual display arrangement information on the viewer machine100by displaying the visual data as the application data in an instance of the application112B on the viewer machine102.

For example, if the application being shared is a word processor application, then application data in the form of a file of the word processor format is shared/sent from the host-viewer synchronization circuitry106A in the host machine100to the host-viewer synchronization circuitry106B in the view machine102. Instead of sending a series of screen captures, the host machine initially sends the file (e.g., the application data) and the viewer machine102then has a local copy of the file and loads it in a local copy of the application112B. In some examples, very little data is required to be transferred from the host machine100to the viewer machine102after the host machine100sends the initial file. In some examples, the application data (e.g., the file(s)) is sent in one or more synchronizer data packets134in an app data section/format138.

In the illustrated flowchart inFIG. 2, after both blocks204and206, the process continues at block208where the example host-viewer synchronizer circuitry106A determines if the screen share has ended. If so, the process inFIG. 2is finished. Otherwise, the process returns to block200to continue screen sharing.

In some examples, the screen share process is initiated by the host machine100and a start-screen-share synchronizer data packet134is sent from the host-viewer synchronizer circuitry106A in the host machine100to the host-viewer synchronizer circuitry106B in the viewer machine102to indicate the start. In some examples, when the host-viewer synchronizer circuitry106B receives the start-screen-share packet, it initializes the host-viewer synchronizer memory structure144B to be ready to receive visual data in the form of synchronizer data packets134across the communication link132. In some examples, the host-viewer synchronizer circuitry106A in the host machine100sends a stop-screen-share synchronizer data packet134to the host-viewer synchronizer circuitry106B in the viewer machine102to indicate the screen share is over. Once the screen share is over, both the host-viewer synchronizer circuitry106A in the host machine100and the host-viewer synchronizer circuitry106B in the viewer machine102can initiate any memory clean up procedures (as well as any other clean up procedures) related to their operation. At this point, the process illustrated inFIG. 2is complete.

FIG. 3is a flowchart representative of example machine readable instructions that may be executed by example processor circuitry to implement a replication process of a visual display high-throughput screen sharing process using screen capture sharing technique. In some examples, the process flow is performed by the host-viewer synchronizer circuitry106A inFIG. 1and the host-viewer synchronizer circuitry106B inFIG. 1. In some examples, the process described inFIG. 3is included as at least a portion of the process within block204inFIG. 2.

In the illustrated example ofFIG. 3, the process begins, at block300, when the example host-viewer synchronizer circuitry106A in the host machine100segments the visual data on the host machine into two visual portions. In some examples, the two visual portions are separated by the host-viewer synchronizer circuitry106A determining, between two screen captures at two differing timestamps, whether the screen has changed (e.g. been modified) by a threshold modification level of pixels.

In some examples, the visual portions are allowed to be designated by an X,Y coordinate system of pixels on the host machine100. Thus, in some examples, the two visual portions are limited to being separated by either a horizontal line or a vertical line. In other examples, additional portions may be designated in an X,Y coordinate system to break up the visual data into additional portions. In the two portion example, a first portion of the screen may be normally without movement. For example, in a word processor, the top rectangular bar of the screen may include a quick access menu of drop down menus and buttons. When a document is being manipulated, there is generally less movement in the menu area of the word processor while there is more movement in the document display area. Thus, in some examples, the host-viewer synchronizer circuitry106A segments the two visual portions based on a threshold modification level of the visual data on the screen.

At block302, the example host-viewer synchronizer circuitry106A transfers the first visual portion from the host machine100to the viewer machine102at a first frame rate. In some examples, the first visual portion may exceed a threshold modification level of the visual data between a plurality of screen captures. In some examples, if the threshold is exceeded, the frame rate may be a standard screen sharing frame rate of the visually changing portion of the screen to minimize choppiness.

At block304, the example host-viewer synchronizer circuitry106A transfers the second visual portion from the host machine100to the viewer machine102at a second frame rate. In some examples, the second framerate is lower, which may not affect viewing the visual data in the second portion if there is no or little movement.

In some examples, the example host-viewer synchronizer circuitry106B on the viewer machine102takes the two visual portions and reconstructs frames to display. In some examples, the reconstruction of the frames takes place in the packet construction memory range150B in the host-viewer synchronizer memory structure144B. For example, if the first visual portion of the data is sent in packets at 30 frames per second and the second visual portion of the data is sent in packets at1frame per second, the host-viewer synchronizer circuitry106B on the viewer machine102uses the same second visual portion of the data for 30 consecutive frames while using 30 unique first visual portions of the data. This methodology lowers screen sharing bandwidth requirements because entire frames of the screen are not being sent at the higher framerate.

In other examples, the two visual portions are based on a first portion (a smaller X,Y box) of higher movement data surrounding a mouse cursor that is moving around the screen and a second visual portion of the entire screen (in X,Y). Here, the example host-viewer synchronizer circuitry106A sends the first visual portion of data covering the moving smaller X,Y box at the higher framerate and overlays it over the portion of the larger second visual portion at the accurate location for the small box.

At this point, the process illustrated inFIG. 3is complete.

FIG. 4is a flowchart representative of example machine readable instructions that may be executed by example processor circuitry to implement another replication process of a visual display high-throughput screen sharing process using screen capture sharing technique. In some examples, the process flow is performed by the host-viewer synchronizer circuitry106A inFIG. 1and the host-viewer synchronizer circuitry106B inFIG. 1. In some examples, the process described inFIG. 4is included as at least a portion of the process within block204inFIG. 2.

In the illustrated example ofFIG. 4, the process begins, at block400, when the example host-viewer synchronizer circuitry106A in the host machine100segments the visual data on the host machine into two visual portions. In some examples, the reasoning behind the separation of the two visual portions is the same between theFIG. 3process and theFIG. 4process. Again, in some examples, the two visual portions are separated by the host-viewer synchronizer circuitry106A determining, between two screen captures at two differing timestamps, whether the screen has changed (e.g., has been modified) by a threshold modification level of pixels.

At block402, the example host-viewer synchronizer circuitry106A transfers the first visual portion from the host machine100to the viewer machine102at a first resolution (e.g., a first image resolution of pixels per inch). In some examples, the first visual portion pixel resolution may a higher resolution to show a sharp screen capture in an area of focus.

At block404, the example host-viewer synchronizer circuitry106A transfers the second visual portion from the host machine100to the viewer machine102at a second resolution. In some examples, the second resolution is lower number of pixels per inch, which may be acceptable to a viewer if the second visual portion is in an area of lesser focus.

For example, take the word processor example again, the quick access drop down menus and buttons may not be needed in high resolution for viewing because the active content in a screen sharing collaboration is only in the word processing document viewing window. In this example, the entire screen capture image is sent in every frame, but a portion of the frame is less dense in pixel resolution, thus allowing for a reduced transfer bandwidth of visual data across the communication link132, which may not affect viewing the visual data in the second portion if there is no or little movement.

In some examples, the example host-viewer synchronizer circuitry106B in the viewer machine102may need to reconstruct the two visual portions of each frame when received if they are separated. At this point, the process illustrated inFIG. 4is complete.

FIG. 5is a flowchart representative of example machine readable instructions that may be executed by example processor circuitry to implement a replication process of a visual display high-throughput screen sharing process using an application data sharing technique. In some examples, the process flow is performed by the application data uploader circuitry108A in the host machine100inFIG. 1and the application data uploader circuitry108B in the viewer machine200inFIG. 1. In some examples, the process described inFIG. 5is included as at least a portion of the process within block206inFIG. 2.

In the illustrated example ofFIG. 5, the process begins, at block500, when the example application data uploader circuitry108B loads an instance of the application being shared on the viewer machine102. In some examples, the application data uploader circuitry108A in host machine100sends a start-screen-share initialization synchronizer data packet134(or later sends an update-screen-share synchronizer data packet134packet). Within one or more of these packets an indicator of the application being shared, thus, the application data uploader circuitry108B in the viewer machine102is given awareness of an application to share and loads the application112B for use.

At block502, the example application data uploader circuitry108A in the host machine100transfers a copy of the application data from the host machine100to the viewer machine102. In some examples, the copy of the application data is a copy of a document, spreadsheet, presentation, etc., that is capable of being loaded in the associated application112B. The local copy of the application data at the viewer machine102provides the viewer machine102access to the source application data and removes a need to provide screen captures across the communication link132. At this point, the process illustrated inFIG. 5is complete.

FIG. 6is a flowchart representative of example machine readable instructions that may be executed by example processor circuitry to implement another replication process of a visual display high-throughput screen sharing process using an application data sharing technique. In some examples, the process flow is performed by the host-viewer synchronizer circuitry106A in the host machine100inFIG. 1and host-viewer synchronizer circuitry106B in the viewer machine200inFIG. 1. In some examples, the process described inFIG. 6is included as at least a portion of the process within block206inFIG. 2.

In the illustrated example ofFIG. 6, the process begins, at block600, when the example host-viewer synchronizer circuitry106A tracks input peripheral usage data for a host machine100input peripheral (e.g., peripheral120). For example, with an electronic mouse, the mouse is manipulated by a user (at host machine100) and provides a series of movement and click data to the associated (mouse) peripheral input driver116. This stream of mouse input usage data is tracked by the host-viewer synchronizer circuitry106A and stored in a tracking buffer148A in the host-viewer synchronizer memory structure144A.

In some examples, the host-viewer synchronizer circuitry106A then constructs one or more synchronizer data packets134in the packet constructor memory space150A in the host-viewer synchronizer memory structure144A. In some examples, the host-viewer synchronizer circuitry106A utilizes an example peripheral usage data format140stored as part of the visual display arrangement information136in the packet and the packet is then transferred across the communication link132to the viewer machine102. In some examples, the host-viewer synchronizer circuitry106B in the viewer machine102deconstructs the packet and retrieves the peripheral usage data.

At block602, the example host-viewer synchronizer circuitry106B replicates the input peripheral usage data as local input peripheral data on the viewer machine102. In some examples, the input peripheral usage data from the one or more packets is saved in the local tracking buffer148B in the host-viewer synchronizer memory structure144B on the viewer machine102.

At block604, the example host-viewer synchronizer circuitry106B manipulates the application data (received at the viewer machine102from the process completed inFIG. 5) in the instance of the application that has been loaded onto the viewer machine102using the input peripheral data loaded in the tracking buffer148B.

In some examples, the input peripheral data causes the application data (e.g., a file) to be manipulated in the local instance of the application. No screen captures are transferred in this process. Rather, in the illustrated example, the application data is transferred at the beginning of the process (seeFIG. 5), followed by the peripheral usage data to allow for a local manipulation of the application data mimicking how the manipulation is taking place on the host device100. In some examples, the local copy of the application data on the viewer machine102is locked from modifications by a local user at the viewer machine (e.g., only the peripheral data can manipulate the application data). At this point, the process illustrated inFIG. 6is complete.

In some examples, the application112A being shared is an Internet webpage browser. In some examples, the transferred application data138for the Internet webpage browser is an Internet address (e.g., a uniform resource locator (URL)). In some examples, the application data uploader108B loads the Internet webpage browser application112B on the viewer machine102and the host-viewer synchronizer circuitry106B inputs the Internet address into the Internet webpage browser to load the application data into the local instance of the application112B in the viewer machine102.

FIG. 7is a flowchart representative of example machine readable instructions that may be executed by example processor circuitry to implement a process for a qualitative attribution threshold check to determine the level of high-throughput screen sharing needed. In some examples, the process flow is performed by the remote viewer data transfer circuitry110A in the host machine100inFIG. 1and the remote viewer data transfer circuitry110B in the viewer machine200inFIG. 1.

In the illustrated example ofFIG. 7, the process begins, at block700, when the example remote viewer data transfer circuitry110A and/or110B makes a qualitative attribute check of the data link between the host machine100and the viewer machine102. In some examples, the remote viewer data transfer circuitry110A/B tests a latency between packets being sent and received across the communication link132.

Additionally or alternatively, in some examples, the remote viewer data transfer circuitry110A/B tests a bandwidth over time of a series of packets being sent and received across the communication link. In some examples, a prompt at each machine requests user input for a quality of signal and utilizes that input on a sliding scale to make a determination as to a qualitative attribute check of the communication link132. In yet other examples, a combination of two or more of these qualitative attribute checks are combined for additional accuracy in a determination of one or more qualitative attributes of the data link (e.g., data stream) across the communication link132.

In some examples, if the qualitative attribute exceeds the threshold modification level (or equal the attribute threshold), then no change in technique is needed to reduce the bandwidth. In some examples, the attribute threshold is a minimum quality standard to maintain a specific type of screen sharing. In some examples, if the qualitative attribute is determined to be below the attribute threshold, then at block702, the example remote viewer data transfer circuitry110A and/or110B sends a notification to the local host-viewer synchronizer106A or106B. In some examples, the local host-viewer synchronizer106A/B, initiates one or more of the processes described above inFIGS. 2-6in response to the notification being received (e.g., when the notification is received). In some examples, there are multiple tiers of qualitative thresholds. In some embodiments, for each lower tier, a screen sharing technique with greater bandwidth savings is implemented. At this point, the process illustrated inFIG. 6is complete.

In some examples, the screen sharing system shown between the host machine100and the viewer machine102is only a small part of a larger network of machine, many of which have an instantiation of the system illustrated inFIG. 1.

While an example manner of implementing the host-viewer synchronizer circuitry106A and106B, the application data uploader circuitry108A and108B, and the remote viewer data transfer circuitry110A and110B ofFIG. 1is illustrated inFIG. 8, one or more of the elements, processes, and/or devices illustrated inFIG. 8may be combined, divided, re-arranged, omitted, eliminated, and/or implemented in any other way. Further, the example host-viewer synchronizer circuitry106A and106B, the application data uploader circuitry108A and108B, and the remote viewer data transfer circuitry110A and110B may be implemented by hardware alone or by hardware in combination with software and/or firmware. Thus, for example, any of the example the example host-viewer synchronizer circuitry106A and106B, the application data uploader circuitry108A and108B, and the remote viewer data transfer circuitry110A and110B could be implemented by processor circuitry, analog circuit(s), digital circuit(s), logic circuit(s), programmable processor(s), programmable microcontroller(s), graphics processing unit(s) (GPU(s)), digital signal processor(s) (DSP(s)), application specific integrated circuit(s) (ASIC(s)), programmable logic device(s) (PLD(s)), and/or field programmable logic device(s) (FPLD(s)) such as Field Programmable Gate Arrays (FPGAs). Further still, the example the example host-viewer synchronizer circuitry106A and106B, the application data uploader circuitry108A and108B, and the remote viewer data transfer circuitry110A and110B may include one or more elements, processes, and/or devices in addition to, or instead of, those illustrated inFIG. 8, and/or may include more than one of any or all of the illustrated elements, processes and devices.

FIG. 8is a block diagram of an example processor platform800structured to execute and/or instantiate the machine readable instructions and/or operations ofFIGS. 2-7to implement the host machine100and/or the viewer machine102ofFIG. 1. The processor platform800can be, for example, a server, a personal computer, a workstation, a self-learning machine (e.g., a neural network), a mobile device (e.g., a cell phone, a smart phone, a tablet such as an iPad), a personal digital assistant (PDA), an Internet appliance, a DVD player, a CD player, a digital video recorder, a Blu-ray player, a gaming console, a personal video recorder, a set top box, a headset (e.g., an augmented reality (AR) headset, a virtual reality (VR) headset, etc.) or other wearable device, or any other type of computing device.

The processor platform800of the illustrated example includes processor circuitry812. The processor circuitry812of the illustrated example is hardware. For example, the processor circuitry812can be implemented by one or more integrated circuits, logic circuits, FPGAs microprocessors, CPUs, GPUs, DSPs, and/or microcontrollers from any desired family or manufacturer. The processor circuitry812may be implemented by one or more semiconductor based (e.g., silicon based) devices. In this example, the processor circuitry812implements the host-viewer synchronizer106A, the application data uploader circuitry108A, and the remote viewer data transfer circuitry110A when the processor platform800implements the host machine100. In this example, the processor circuitry812implements the host-viewer synchronizer106B, the application data uploader circuitry108B, and the remote viewer data transfer circuitry110B when the processor platform800implements the viewer machine102.

The processor platform800of the illustrated example also includes interface circuitry820. The interface circuitry820may be implemented by hardware in accordance with any type of interface standard, such as an Ethernet interface, a universal serial bus (USB) interface, a Bluetooth® interface, a near field communication (NFC) interface, a PCI interface, and/or a PCIe interface.

In the illustrated example, one or more input devices822are connected to the interface circuitry820. The input device(s)822permit(s) a user to enter data and/or commands into the processor circuitry812. The input device(s)822can be implemented by, for example, an audio sensor, a microphone, a camera (still or video), a keyboard, a button, a mouse, a touchscreen, a track-pad, a trackball, an isopoint device, and/or a voice recognition system.

The processor platform800of the illustrated example also includes one or more mass storage devices828to store software and/or data. Examples of such mass storage devices828include magnetic storage devices, optical storage devices, floppy disk drives, HDDs, CDs, Blu-ray disk drives, redundant array of independent disks (RAID) systems, solid state storage devices such as flash memory devices, and DVD drives.

The machine executable instructions832, which may be implemented by the machine readable instructions ofFIGS. 3-8, may be stored in the mass storage device828, in the volatile memory814, in the non-volatile memory816, and/or on a removable non-transitory computer readable storage medium such as a CD or DVD.

FIG. 9is a block diagram of an example implementation of the processor circuitry812ofFIG. 8. In this example, the processor circuitry812ofFIG. 8is implemented by a microprocessor900. For example, the microprocessor900may implement multi-core hardware circuitry such as a CPU, a DSP, a GPU, an XPU, etc. Although it may include any number of example cores902(e.g.,1core), the microprocessor900of this example is a multi-core semiconductor device including N cores. The cores902of the microprocessor900may operate independently or may cooperate to execute machine readable instructions. For example, machine code corresponding to a firmware program, an embedded software program, or a software program may be executed by one of the cores902or may be executed by multiple ones of the cores902at the same or different times. In some examples, the machine code corresponding to the firmware program, the embedded software program, or the software program is split into threads and executed in parallel by two or more of the cores902. The software program may correspond to a portion or all of the machine readable instructions and/or operations represented by the flowcharts ofFIGS. 2-7.

The cores902may communicate by an example bus904. In some examples, the bus904may implement a communication bus to effectuate communication associated with one(s) of the cores902. For example, the bus904may implement at least one of an Inter-Integrated Circuit (I2C) bus, a Serial Peripheral Interface (SPI) bus, a PCI bus, or a PCIe bus. Additionally or alternatively, the bus904may implement any other type of computing or electrical bus. The cores902may access data, instructions, and/or signals from one or more external devices by example interface circuitry906. The cores902may output data, instructions, and/or signals to the one or more external devices by the interface circuitry906. Although the cores902of this example include example local memory920(e.g., Level 1 (L1) cache that may be split into an L1 data cache and an L1 instruction cache), the microprocessor900also includes example shared memory910that may be shared by the cores (e.g., Level 2 (L2_ cache)) for high-speed access to data and/or instructions. Data and/or instructions may be transferred (e.g., shared) by writing to and/or reading from the shared memory910. The local memory920of each of the cores902and the shared memory910may be part of a hierarchy of storage devices including multiple levels of cache memory and the main memory (e.g., the main memory814,816ofFIG. 8). Typically, higher levels of memory in the hierarchy exhibit lower access time and have smaller storage capacity than lower levels of memory. Changes in the various levels of the cache hierarchy are managed (e.g., coordinated) by a cache coherency policy.

Each core902may be referred to as a CPU, DSP, GPU, etc., or any other type of hardware circuitry. Each core902includes control unit circuitry914, arithmetic and logic (AL) circuitry (sometimes referred to as an ALU)916, a plurality of registers918, the L1 cache920, and an example bus922. Other structures may be present. For example, each core902may include vector unit circuitry, single instruction multiple data (SIMD) unit circuitry, load/store unit (LSU) circuitry, branch/jump unit circuitry, floating-point unit (FPU) circuitry, etc. The control unit circuitry914includes semiconductor-based circuits structured to control (e.g., coordinate) data movement within the corresponding core902. The AL circuitry916includes semiconductor-based circuits structured to perform one or more mathematic and/or logic operations on the data within the corresponding core902. The AL circuitry916of some examples performs integer based operations. In other examples, the AL circuitry916also performs floating point operations. In yet other examples, the AL circuitry916may include first AL circuitry that performs integer based operations and second AL circuitry that performs floating point operations. In some examples, the AL circuitry916may be referred to as an Arithmetic Logic Unit (ALU). The registers918are semiconductor-based structures to store data and/or instructions such as results of one or more of the operations performed by the AL circuitry916of the corresponding core902. For example, the registers918may include vector register(s), SIMD register(s), general purpose register(s), flag register(s), segment register(s), machine specific register(s), instruction pointer register(s), control register(s), debug register(s), memory management register(s), machine check register(s), etc. The registers918may be arranged in a bank as shown inFIG. 9. Alternatively, the registers918may be organized in any other arrangement, format, or structure including distributed throughout the core902to shorten access time. The bus920may implement at least one of an I2C bus, a SPI bus, a PCI bus, or a PCIe bus

FIG. 10is a block diagram of another example implementation of the processor circuitry812ofFIG. 8. In this example, the processor circuitry1012is implemented by FPGA circuitry1000. The FPGA circuitry1000can be used, for example, to perform operations that could otherwise be performed by the example microprocessor900ofFIG. 9executing corresponding machine readable instructions. However, once configured, the FPGA circuitry1000instantiates the machine readable instructions in hardware and, thus, can often execute the operations faster than they could be performed by a general purpose microprocessor executing the corresponding software.

In the example ofFIG. 10, the FPGA circuitry1000is structured to be programmed (and/or reprogrammed one or more times) by an end user by a hardware description language (HDL) such as Verilog. The FPGA circuitry1000ofFIG. 10, includes example input/output (I/O) circuitry1002to access and/or output data to/from example configuration circuitry1004and/or external hardware (e.g., external hardware circuitry)1006. For example, the configuration circuitry1004may implement interface circuitry that may access machine readable instructions to configure the FPGA circuitry1000, or portion(s) thereof. In some such examples, the configuration circuitry1004may access the machine readable instructions from a user, a machine (e.g., hardware circuitry (e.g., programmed or dedicated circuitry) that may implement an Artificial Intelligence/Machine Learning (AI/ML) model to generate the instructions), etc. In some examples, the external hardware1006may implement the microprocessor900ofFIG. 9. The FPGA circuitry1000also includes an array of example logic gate circuitry1008, a plurality of example configurable interconnections1010, and example storage circuitry1012. The logic gate circuitry1008and interconnections1010are configurable to instantiate one or more operations that may correspond to at least some of the machine readable instructions ofFIGS. 2-7and/or other desired operations. The logic gate circuitry1008shown inFIG. 10is fabricated in groups or blocks. Each block includes semiconductor-based electrical structures that may be configured into logic circuits. In some examples, the electrical structures include logic gates (e.g., And gates, Or gates, Nor gates, etc.) that provide basic building blocks for logic circuits. Electrically controllable switches (e.g., transistors) are present within each of the logic gate circuitry1008to enable configuration of the electrical structures and/or the logic gates to form circuits to perform desired operations. The logic gate circuitry1008may include other electrical structures such as look-up tables (LUTs), registers (e.g., flip-flops or latches), multiplexers, etc.

The storage circuitry1012of the illustrated example is structured to store result(s) of the one or more of the operations performed by corresponding logic gates. The storage circuitry1012may be implemented by registers or the like. In the illustrated example, the storage circuitry1012is distributed amongst the logic gate circuitry1008to facilitate access and increase execution speed.

The example FPGA circuitry1000ofFIG. 10also includes example Dedicated Operations Circuitry1014. In this example, the Dedicated Operations Circuitry1014includes special purpose circuitry1016that may be invoked to implement commonly used functions to avoid the need to program those functions in the field. Examples of such special purpose circuitry1016include memory (e.g., DRAM) controller circuitry, PCIe controller circuitry, clock circuitry, transceiver circuitry, memory, and multiplier-accumulator circuitry. Other types of special purpose circuitry may be present. In some examples, the FPGA circuitry1000may also include example general purpose programmable circuitry1018such as an example CPU1020and/or an example DSP1022. Other general purpose programmable circuitry1018may additionally or alternatively be present such as a GPU, an XPU, etc., that can be programmed to perform other operations.

AlthoughFIGS. 9 and 10illustrate two example implementations of the processor circuitry1012ofFIG. 10, many other approaches are contemplated. For example, as mentioned above, modern FPGA circuitry may include an on-board CPU, such as one or more of the example CPU1020ofFIG. 10. Therefore, the processor circuitry812ofFIG. 8may additionally be implemented by combining the example microprocessor900ofFIG. 9and the example FPGA circuitry1000ofFIG. 10. In some such hybrid examples, a first portion of the machine readable instructions represented by the flowcharts ofFIGS. 2-7may be executed by one or more of the cores902ofFIG. 9and a second portion of the machine readable instructions represented by the flowcharts ofFIGS. 2-7may be executed by the FPGA circuitry1000ofFIG. 10.

In some examples, the processor circuitry812ofFIG. 8may be in one or more packages. For example, the processor circuitry900ofFIG. 9and/or the FPGA circuitry1000ofFIG. 10may be in one or more packages. In some examples, an XPU may be implemented by the processor circuitry1012ofFIG. 10, which may be in one or more packages. For example, the XPU may include a CPU in one package, a DSP in another package, a GPU in yet another package, and an FPGA in still yet another package.

A block diagram illustrating an example software distribution platform1105to distribute software such as the example machine readable instructions832ofFIG. 8to hardware devices owned and/or operated by third parties is illustrated inFIG. 11. The example software distribution platform1105may be implemented by any computer server, data facility, cloud service, etc., capable of storing and transmitting software to other computing devices. The third parties may be customers of the entity owning and/or operating the software distribution platform1105. For example, the entity that owns and/or operates the software distribution platform1105may be a developer, a seller, and/or a licensor of software such as the example machine readable instructions832ofFIG. 8. The third parties may be consumers, users, retailers, OEMs, etc., who purchase and/or license the software for use and/or re-sale and/or sub-licensing. In the illustrated example, the software distribution platform1105includes one or more servers and one or more storage devices. The storage devices store the machine readable instructions832, which may correspond to the example machine readable instructions ofFIGS. 2-7, as described above. The one or more servers of the example software distribution platform1105are in communication with a network1110, which may correspond to any one or more of the Internet and/or the example network826described above. In some examples, the one or more servers are responsive to requests to transmit the software to a requesting party as part of a commercial transaction. Payment for the delivery, sale, and/or license of the software may be handled by the one or more servers of the software distribution platform and/or by a third party payment entity. The servers enable purchasers and/or licensors to download the machine readable instructions832from the software distribution platform1105. For example, the software, which may correspond to the example machine readable instructions ofFIG. 11, may be downloaded to the example processor platform800, which is to execute the machine readable instructions832to implement the host machine100and/or the viewer machine102. In some example, one or more servers of the software distribution platform1105periodically offer, transmit, and/or force updates to the software (e.g., the example machine readable instructions832ofFIG. 8) to ensure improvements, patches, updates, etc., are distributed and applied to the software at the end user devices.

From the foregoing, it will be appreciated that example systems, methods, apparatus, and articles of manufacture have been disclosed to implement high-throughput screen sharing. The disclosed systems, methods, apparatus, and articles of manufacture decrease the amount of data needed across a communication link between any two computer systems that are screen sharing with each other. The disclosed systems, methods, apparatus, and articles of manufacture are accordingly directed to one or more improvement(s) in the operation of a machine such as a computer or other electronic and/or mechanical device.

Example 1 includes an apparatus to implement screen sharing, the apparatus comprising processor circuitry including one or more of at least one of a central processing unit, a graphic processing unit or a digital signal processor, the at least one of the central processing unit, the graphic processing unit or the digital signal processor having control circuitry to control data movement within the processor circuitry, arithmetic and logic circuitry to perform one or more first operations corresponding to instructions, and one or more registers to store a result of the one or more first operations, the instructions in the apparatus, a Field Programmable Gate Array (FPGA), the FPGA including logic gate circuitry, a plurality of configurable interconnections, and storage circuitry, the logic gate circuitry and interconnections to perform one or more second operations, the storage circuitry to store a result of the one or more second operations, or an Application Specific Integrate Circuitry (ASIC) including logic gate circuitry to perform one or more third operations, the processor circuitry to perform at least one of the one or more first operations, the one or more second operations or the one or more third operations to instantiate host-viewer synchronizer circuitry to determine whether a share mode to share visual data from a host machine to a viewer machine is in an application share mode to share application data associated with an application or in a desktop share mode to share one or more screen captures of an operating system desktop, track visual display arrangement information of an amount of the visual data on the host machine, display the amount of visual data on the viewer machine as one or more screen captures of the operating system desktop from the host machine by replicating a first amount of the tracked visual display arrangement information on the viewer machine in response to the share mode being in the desktop share mode, and display the amount of visual data on the viewer machine as the application data in an instance of the application by replicating a second amount of the tracked visual display arrangement information on the viewer machine in response to the share mode being in the application share mode.

Example 2 includes the apparatus of example 1, wherein the processor circuitry is to perform at least one of the one or more first operations, the one or more second operations or the one or more third operations to instantiate application data uploader circuitry to in response to the share mode being in the application share mode, load the instance of the application on the viewer machine, and transfer a copy of the application data from the host machine to the viewer machine, the application data based on the second amount of the tracked visual display arrangement information.

Example 3 includes the apparatus of example 2, wherein the host-viewer synchronizer circuitry is to track an amount of input peripheral usage data for at least one input peripheral associated with the host machine, the amount of input peripheral usage data being at least a portion of the second amount of the tracked visual display arrangement information, and replicate at least a portion of the amount of input peripheral usage data as input peripheral data on the viewer machine.

Example 4 includes the apparatus of example 3, wherein to replicate the second amount of the tracked visual display arrangement information in the instance of the application on the viewer screen, the host-viewer synchronizer circuitry is to manipulate the application data in the instance of the application on the viewer machine based on the input peripheral data.

Example 5 includes the apparatus of any one of examples 1 to 4, wherein the host-viewer synchronizer circuitry is to in response to the application being an Internet browsing application viewing a webpage at an address, load the address in the instance of the application on the viewer machine to display the webpage, the address being at least a portion of the second amount of the tracked visual display arrangement information.

Example 6 includes the apparatus of example 1, wherein the host-viewer synchronizer circuitry is to in response to the share mode being in the desktop share mode, segment the visual data of the one or more screen captures into at least two visual portions, wherein a first visual portion of the at least two visual portions is above a threshold modification level of the visual data between the plurality of screen captures, a second visual portion of the at least two visual portions is below a threshold modification level of the visual data between the plurality of screen captures, and the at least two visual portions are at least a portion of the first amount of the tracked visual display arrangement information.

Example 7 includes the apparatus of example 6, wherein the host-viewer synchronizer circuitry is to transfer the first visual portion of the visual data from the host machine to the viewer machine at a first framerate, and transfer the second visual portion of the visual data from the host machine to the viewer machine at a second framerate, wherein the second framerate is less than the first framerate.

Example 8 includes the apparatus of example 7, wherein the host-viewer synchronizer circuitry is to create a plurality of frames of the visual data on the viewer machine by combining the first visual portion and the second visual portion of the visual data.

Example 9 includes the apparatus of example 6, wherein the host-viewer synchronizer circuitry is to transfer the first visual portion of the visual data from the host machine to the viewer machine at a first pixel resolution, and transfer the second visual portion of the visual data from the host machine to the viewer machine at a second pixel resolution, wherein the second pixel resolution is less than the first pixel resolution.

Example 10 includes the apparatus of any one of examples 1 to 9, further including the processor circuitry to perform at least one of the one or more first operations, the one or more second operations or the one or more third operations to instantiate remote viewer data transfer circuitry to determine whether at least one qualitative attribute of a data link between the host machine and the viewer machine is below an attribute threshold, and send an attribute threshold notification to the host-viewer synchronizer circuitry in response to the at least one qualitative attribute being below the attribute threshold.

Example 11 includes the apparatus of any one of examples 1 to 10, wherein the host-viewer synchronizer circuitry is to transfer at least one synchronizer data packet between the host machine and the viewer machine, the at least one synchronizer data packet including at least a portion of the amount of the visual data.

Example 12 includes at least one non-transitory computer-readable storage medium comprising instructions that, when executed, cause one or more processors to at least determine whether a share mode to share visual data from a host machine to a viewer machine is in an application share mode to share application data associated with an application or in a desktop share mode to share one or more screen captures of an operating system desktop, track a visual display arrangement information of an amount of the visual data on the host machine, display the amount of visual data on the viewer machine as one or more screen captures of the operating system desktop from the host machine by replicating a first amount of the tracked visual display arrangement information on the viewer machine in response to the share mode being in the desktop share mode, and display the amount of visual data on the viewer machine as the application data in an instance of the application by replicating a second amount of the tracked visual display arrangement information on the viewer machine in response to the share mode being in the application share mode.

Example 13 includes the at least one non-transitory computer-readable storage medium of example 12, wherein the instructions, when executed, cause the one or more processors to in response to the share mode being in the application share mode, load the instance of the application on the viewer machine, and transfer a copy of the application data from the host machine to the viewer machine, the application data based on the second amount of the tracked visual display arrangement information.

Example 14 includes the at least one non-transitory computer-readable storage medium of example 13, wherein the instructions, when executed, cause the one or more processors to track an amount of input peripheral usage data for at least one input peripheral associated with the host machine, the amount of input peripheral usage data being at least a portion of the second amount of the tracked visual display arrangement information, and replicate at least a portion of the amount of input peripheral usage data as input peripheral data on the viewer machine.

Example 15 includes the at least one non-transitory computer-readable storage medium of example 14, wherein the instructions, when executed, cause the one or more processors to manipulate the application data in the instance of the application on the viewer machine based on the input peripheral data.

Example 16 includes the at least one non-transitory computer-readable storage medium of any one of examples 12 to 15, wherein the instructions, when executed, cause the one or more processors to, in response to the application being an Internet browsing application viewing a webpage at an address, the address being at least a portion of the second amount of the tracked visual display arrangement information, load the address in the instance of the application on the viewer machine to display the webpage.

Example 17 includes the at least one non-transitory computer-readable storage medium of example 12, wherein the instructions, when executed, cause the one or more processors to in response to the share mode being in the desktop share mode, segment the visual data of a plurality of screen captures into at least two visual portions, wherein a first visual portion of the at least two visual portions is above a threshold modification level of the visual data between the plurality of screen captures, a second visual portion of the at least two visual portions is below a threshold modification level of the visual data between the plurality of screen captures, and the at least two visual portions are at least a portion of the first amount of the tracked visual display arrangement information.

Example 18 includes the non-transitory computer-readable storage medium of example 17, wherein the instructions, when executed, cause the one or more processors to transfer the first visual portion of the visual data from the host machine to the viewer machine at a first framerate, and transfer the second visual portion of the visual data from the host machine to the viewer machine at a second framerate, wherein the second framerate is less than the first framerate.

Example 19 includes the non-transitory computer-readable storage medium of example 18, wherein the instructions, when executed, cause the one or more processors to create a plurality of frames of the visual data on the viewer machine by combining the first visual portion and the second visual portion of the visual data.

Example 20 includes the non-transitory computer-readable storage medium of example 19, wherein the instructions, when executed, cause the one or more processors to transfer the first visual portion of the visual data from the host machine to the viewer machine at a first pixel resolution, and transfer the second visual portion of the visual data from the host machine to the viewer machine at a second pixel resolution, wherein the second pixel resolution is less than the first pixel resolution.

Example 21 includes the non-transitory computer-readable storage medium of any one of examples 12 to 20, wherein the instructions, when executed, cause the one or more processors to determine whether at least one qualitative attribute of a data link between the host machine and the viewer machine is below an attribute threshold, and send an attribute threshold notification to a host-viewer synchronizer circuitry in response to the at least one qualitative attribute being below the attribute threshold.

Example 22 includes the non-transitory computer-readable storage medium of any one of examples 12 to 20, wherein the instructions, when executed, cause the one or more processors to at least transfer at least one synchronizer data packet between the host machine and the viewer machine, the at least one synchronizer data packet including at least a portion of the amount of the visual data.

Example 23 includes a method to perform screen sharing, the method comprising determining whether a share mode to share visual data from a host machine to a viewer machine is in an application share mode to share application data associated with an application or in a desktop share mode to share one or more screen captures of an operating system desktop, tracking a visual display arrangement information of an amount of the visual data on the host machine, displaying the amount of visual data on the viewer machine as one or more screen captures of the operating system desktop from the host machine by replicating a first amount of the tracked visual display arrangement information on the viewer machine in response to the share mode being in the desktop share mode, and displaying the amount of visual data on the viewer machine as the application data in an instance of the application by replicating a second amount of the tracked visual display arrangement information on the viewer machine in response to the share mode being in the application share mode.

Example 24 includes the method of example 23, further including in response to the share mode being in the application share mode, loading the instance of the application on the viewer machine, and transferring a copy of the application data from the host machine to the viewer machine, the application data based on the second amount of the tracked visual display arrangement information.

Example 25 includes the method of example 23, further including in response to the share mode being in the desktop share mode, segmenting the visual data of a plurality of screen captures into at least two visual portions, wherein a first visual portion of the at least two visual portions exceeds a threshold modification level of the visual data between the plurality of screen captures, a second visual portion of the at least two visual portions is below a threshold modification level of the visual data between the plurality of screen captures, and the at least two visual portions are at least a portion of the first amount of the tracked visual display arrangement information.