Trench metal oxide semiconductor with recessed trench material and remote contacts

Remote contacts to the polysilicon regions of a trench metal oxide semiconductor (MOS) barrier Schottky (TMBS) device, as well as to the polysilicon regions of a MOS field effect transistor (MOSFET) section and of a TMBS section in a monolithically integrated TMBS and MOSFET (SKYFET) device, are employed. The polysilicon is recessed relative to adjacent mesas. Contact of the source metal to the polysilicon regions of the TMBS section is made through an extension of the polysilicon to outside the active region of the TMBS section. This change in the device architecture relieves the need to remove all of the oxides from both the polysilicon and silicon mesa regions of the TMBS section prior to the contact step. As a consequence, encroachment of contact metal into the sidewalls of the trenches in a TMBS device, or in a SKYFET device, is avoided.

FIELD OF THE INVENTION

Embodiments in accordance with the present invention generally pertain to semiconductor devices.

BACKGROUND

In a trench metal oxide semiconductor (MOS) barrier Schottky (TMBS) device, polysilicon is contained inside a trench that is formed in a silicon substrate. The polysilicon inside the trench and the silicon mesa (the surface between adjacent trenches) are connected locally using a metal contact.

In a monolithically integrated TMBS and MOS field effect transistor (MOSFET) device, which may be referred to herein as a SKYFET device, polysilicon is contained inside a trench that is formed in a silicon substrate. The source of the MOSFET section and the TMBS section are connected by the same contact metal.

In both of these types of devices, the polysilicon is separated from the sidewalls of the trench by an oxide layer. During fabrication, a portion of the oxide layer and a portion of the polysilicon are etched away prior to deposition of the contact metal. Unfortunately, the etch process can result in the encroachment of the metal into the sidewalls of the trench (into the mesa), resulting in excessive current leakage often attributed as edge leakage in Schottky diode technology.

SUMMARY

A method and/or device that that eliminates or reduces edge leakage in TMBS and SKYFET devices would be advantageous. Embodiments in accordance with the present invention provide this and other advantages.

Embodiments in accordance with the present invention resolve the problem of edge leakage by employing remote contacts to the polysilicon regions of a TMBS device, as well as to the polysilicon regions of a MOSFET section and a TMBS section of a SKYFET device.

Contact of the source metal to the polysilicon regions of the TMBS section is made through an extension of the polysilicon to outside the TMBS section. The polysilicon is recessed relative to adjacent mesas and isolated from the contact metal by an oxide layer. These changes in device architecture relieve the need to remove all of the oxides from both the polysilicon and silicon mesa regions of the TMBS section prior to deposition of the contact metal. As a consequence, encroachment of contact metal into the sidewalls of the trenches in a TMBS device, or in a SKYFET device, is avoided.

These and other objects and advantages of the present invention will be recognized by one skilled in the art after having read the following detailed description, which are illustrated in the various drawing figures.

DETAILED DESCRIPTION

In the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be recognized by one skilled in the art that the present invention may be practiced without these specific details or with equivalents thereof. In other instances, well-known methods, procedures, components, and circuits have not been described in detail as not to unnecessarily obscure aspects of the present invention.

Some portions of the detailed descriptions that follow are presented in terms of procedures, logic blocks, processing, and other symbolic representations of operations for fabricating semiconductor devices. These descriptions and representations are the means used by those skilled in the art of semiconductor device fabrication to most effectively convey the substance of their work to others skilled in the art. In the present application, a procedure, logic block, process, or the like, is conceived to be a self-consistent sequence of steps or instructions leading to a desired result. The steps are those requiring physical manipulations of physical quantities. It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise as apparent from the following discussions, it is appreciated that throughout the present application, discussions utilizing terms such as “forming,” “performing,” “producing,” “depositing,” “etching” or the like, refer to actions and processes (e.g., flowchart100ofFIG. 1) of semiconductor device fabrication.

The figures are not drawn to scale, and only portions of the structures, as well as the various layers that form those structures, may be shown. Furthermore, other fabrication processes and steps may be performed along with the processes and steps discussed herein; that is, there may be a number of process steps before, in between and/or after the steps shown and described herein. Importantly, embodiments in accordance with the present invention can be implemented in conjunction with these other (perhaps conventional) processes and steps without significantly perturbing them. Generally speaking, embodiments in accordance with the present invention can replace portions of a conventional process without significantly affecting peripheral processes and steps.

FIG. 1is a flowchart100of one embodiment of a process that is used in the fabrication of a semiconductor device, specifically a monolithically integrated TMBS and MOSFET device, or SKYFET. Although the process of flowchart100is described in the context of a SKYFET such as that shown inFIG. 10, a subset of the process can be utilized to form only a TMBS device such as that shown inFIG. 11(that is, only the steps used to form the TMBS section of a SKYFET may be performed, in which case the steps used to form the MOSFET section are not necessarily performed).

Although specific steps are disclosed inFIG. 1, such steps are exemplary. That is, the present invention is well suited to performing various other steps or variations of the steps recited inFIG. 1.FIG. 1is discussed in conjunction withFIGS. 2 through 9, which are cross-sectional views showing selected stages in the fabrication of a semiconductor device according to an embodiment of the present invention, and also in conjunction withFIGS. 10 and 11, which are top-down views of portions of embodiments of semiconductor devices that can be manufactured using the process of flowchart100.

In block105ofFIG. 1, with reference also toFIG. 2, a first mask220(e.g., photoresist) is patterned onto substrate205(e.g., a p-type silicon substrate) in order to define trenches such as trenches210,211,212,213,214and215. The trenches210-215are formed by etching the substrate205in areas not covered by the mask220. Trench215, which may be used as a channel stopper (e.g., its contents may later be doped with an n-type impurity), is optional. After the trenches are formed, the mask220is removed and the resulting structure is cleaned. Etching and sacrificial oxidation may follow the cleaning to improve trench sidewall quality.

In block110ofFIG. 1, with reference also toFIG. 3, a gate oxide layer310is grown in each of the trenches210-215, and polysilicon320is deposited into each of the trenches210-215. These steps may be followed by doping, blanket etch back, and polysilicon re-oxidation. Significantly, the top surfaces of the regions of polysilicon320are recessed relative to the tops of the trenches210-215. More specifically, the sidewalls of the trenches (or, correspondingly, the sidewalls of the mesas) have a height H1, while the polysilicon320is deposited within the trenches to a height H2, where H2is less than H1.

In block115ofFIG. 1, with reference also toFIG. 4, a second mask410is applied to define regions in which a body implant420(e.g., a p-body implant) is subsequently admitted. The mask410can then be stripped, the resulting structure can be cleaned, and the body implant420can be annealed and diffused to the desired junction depth.

In block120ofFIG. 1, with reference also toFIG. 5, a third mask510is applied to define regions in which a source implant520(e.g., an n+source implant) is subsequently admitted. Significantly, the source implant520is not admitted into either the termination areas around the trenches212and214or the regions between the trenches212-214, which correspond to the active region of a TMBS section of a SKYFET. The source implant520is permitted into the optional channel stopper (trench215). The mask510can then be stripped and the resulting structure can be cleaned.

In block125ofFIG. 1, with reference also toFIG. 6, a dielectric stack is deposited across the entire surface of the structure and densified. In one embodiment, the dielectric stack includes a layer610of tetraethylorthosilicate (TEOS) and a layer620of borophosphosilicate glass (BPSG).

In block130ofFIG. 1, with reference also toFIG. 7, a fourth mask710is applied to define the contact openings720,721and722in the active region of the MOSFET section(s) of the SKYFET. Because, prior to the etch, the upper surface of the structure is relatively flat, a thinner resist mask can be used. The source implant layer520, the TEOS layer610and the BPSG layer620are etched, except for the areas under the mask710, to form the contact openings720-722. Significantly, the active area of the TMBS section is masked by mask710.

When contact metal is deposited in a subsequent step (block140), the contact openings720-722permit contact between the n-type implants (layer520) and the contact metal; however, the contact metal will not contact the regions of polysilicon320. That is, the same metal does not contact both the source implants520and the polysilicon320.

Importantly, the sidewalls of the trenches210-215are not exposed to the etch used to form the contact openings720-722, thus avoiding the problem of encroachment of the contact metal (deposited in block140) into the sidewalls of the trenches210-215and thereby eliminating or reducing edge leakage often attributed to such metal encroachment.

With reference also toFIGS. 10 and 11, in order to contact the regions of polysilicon320, the fourth mask710also defines contact openings in the gate pickup area (e.g., contacts1010and1011) and in the polysilicon pickup area of the TMBS section (e.g., contact1020). From the perspective ofFIG. 7, for example, the polysilicon regions320extend a distance into the page, as shown inFIGS. 10 and 11. The contacts1010and1011contact the polysilicon320that is in the MOSFET section, and the contact1020contacts the polysilicon320that is in the TMBS section.

After contact oxide etches and a silicon etch, contact clamping implant and shallow contact implant are performed and the fourth mask710can be stripped. The contact clamping and shallow contact implants improve the contact resistance to the body and also shift avalanche breakdown from the trenches to the center of each mesa.

After the mask710is stripped, the resulting structure can then be subjected to high temperature reflow in order to activate the contact implant, activate the source implant if it has not be activated, drive the source implant to its target junction depth, densify the dielectric stack if needed, and contour the dielectric stack if desired in order to soften the topography of the structure.

In block135ofFIG. 1, with reference also toFIG. 8, a fifth mask810is used to pattern only the active area of the TMBS section, in order to etch away portions of the dielectric stack (e.g., TEOS layer610and BPSG layer620) prior to deposition of barrier and contact metal. In one embodiment, after etching of the dielectric stack, any remaining oxide layered on the surfaces of the mesas in the TMBS section (e.g., mesas820and821) is cleaned from those surfaces. In one embodiment, the oxide on the TMBS mesa surfaces is dry etched to a thickness of approximately 1000 Angstroms, and then a buffered oxide etch (BOE) (e.g., a 9:1 BOE wet dip) is applied to remove any remaining oxide, so that good contact can be made between the mesa surfaces and the contact metal (deposited in block140). An objective of the wet overetch is to clean the oxide from the TMBS mesa surfaces, but not necessarily from inside the trenches212-214. Significantly, the top surface of the polysilicon320in trenches212-214remains recessed relative to the mesa surfaces820-821, covered by a remaining thickness of the gate oxide layer310.

In block140ofFIG. 1, with reference also toFIG. 9, a source metal layer910is formed. More specifically, barrier and contact metal (e.g., titanium nitride, titanium, aluminum) is deposited to form the layer910. The deposited metal can be subsequently patterned using a sixth mask (not shown). The source metal layer910contacts the TMBS mesas820-821but not the regions of polysilicon320. That is, the source metal layer910is isolated from the polysilicon320by the oxide310.

In block145ofFIG. 1, a passivation layer, if used, can be deposited and patterned using a seventh mask (not shown). The structure can then be ground and back metal can be applied.

A device that includes only a TMBS section can be formed by skipping the steps described in blocks115,120and130, for example.

Refer now toFIGS. 10 and 11, which show a top down view of a portion of a SKYFET device (including MOSFET sections and a TMBS section) and a similar view of a TMBS device, respectively, according to embodiments of the invention. In the example ofFIG. 10, the different regions of polysilicon320in the trenches of each MOSFET section are connected to each other and then to contacts1010and1011outside the active regions of the MOSFET section(s). Given the orientation ofFIG. 10, the polysilicon320extends to the contacts1010and1011, which are each beyond the edge of the source metal layer910that is disposed over the trenches210-211and215(FIG. 2) in the MOSFET sections that contain the polysilicon320. Thus, electrical contact between the MOSFET polysilicon320and the gate metal is made via the contacts1010and1011. However, contacts1010and1011are outside the active region of the MOSFET sections shown inFIG. 10. That is, contacts1010and1011are outside the region of the source metal layer910that lies over the trenches in the MOSFET sections that contain the polysilicon320.

Similarly, the different regions of polysilicon320in the trenches of each TMBS section are connected to each other and then to contact1020, which is outside the active TMBS section ofFIGS. 10 and 11. Given the orientation ofFIGS. 10 and 11, the polysilicon320extends further than the mesas820-821(FIG. 8) in the lateral direction. The source metal layer910is disposed over the trenches212-214(FIG. 2) in the TMBS section that contain the polysilicon320and the mesas between those trenches.

As mentioned above, the source metal layer910is in electrical contact with the mesas but is isolated from the polysilicon320in the trenches. Contacts1040represent the connections between the Schottky contact metal (source metal layer910) and the mesas820-821(FIG. 8) in the TMBS section ofFIG. 10. Electrical contact between the polysilicon320and the source metal layer910is made via the contact1020. However, contact1020is outside the active region of the TMBS section shown inFIGS. 10 and 11. That is, contact1020is outside the region of the source metal layer910that lies over the trenches in the TMBS section that contain the polysilicon320and that also lies over the mesas between those trenches.

Also shown are MOSFET source contacts1030that provide electrical contact to the source implants520(FIG. 7).

In summary, embodiments in accordance with the present invention resolve the problem of excessive leakage by employing remote contacts (e.g., contact1020) to the polysilicon regions of a TMBS device, as well as to the polysilicon regions of TMBS section(s) and MOSFET section(s) of a SKYFET device. The polysilicon320is recessed relative to adjacent mesas. A stacked layer of TEOS610and BPSG620(FIG. 6) is employed to selectively leave a thin layer of oxide on top of the polysilicon320while making sure that the mesa surfaces in the TMBS section (e.g., mesas820-821) are open for contact metal, but without exposing trench sidewalls to etching.

These changes in the device architecture relieve the need to remove all of the oxides from both the polysilicon and silicon mesa regions of the TMBS section prior to the contact step. Oxide is etched completely only from the silicon mesas in the TMBS section. Contact of the source metal to the polysilicon regions of the TMBS section is made through an extension of the polysilicon to outside the TMBS section. As a consequence of these features as well as the process used to fabricate these features, encroachment of contact metal into the sidewalls of the trenches in a TMBS device, or in a SKYFET device, is avoided.