CMOS image sensor with high full-well-capacity

An image sensor with a high full-well capacity includes a photosensitive region, a transfer gate, and sidewall spacers. The photosensitive region is formed to accumulate an image charge in response to light. The transfer gate disposed adjacent to the photosensitive region and coupled to selectively transfer the image charge from the photosensitive region to other pixel circuitry. First and second sidewall spacers are disposed on either side of the transfer gate. The first sidewall spacer closest to the photosensitive region is narrower than the second sidewall spacer. In some cases, the first sidewall spacer may be omitted.

TECHNICAL FIELD

This disclosure relates generally to image sensors, and in particular but not exclusively, relates to CMOS image sensors having a high full-well-capacity.

BACKGROUND INFORMATION

Image sensors have become ubiquitous. They are widely used in digital still cameras, cellular phones, security cameras, as well as, medical, automobile, and other applications. The technology used to manufacture image sensors, and in particular, complementary metal-oxide-semiconductor (“CMOS”) image sensors (“CIS”), has continued to advance at great pace. For example, the demands of higher resolution and lower power consumption have encouraged the further miniaturization and integration of these image sensors.

FIG. 1shows a cross-sectional view of a conventional active pixel cell100that uses four transistors. This is known in the art as a 4T pixel cell. 4T pixel cell100includes a photodiode PD, a transfer transistor T1, a reset transistor T2, a source-follower (“SF”) or amplifier (“AMP”) transistor T3, and a row select (“RS”) transistor T4.

During operation, transfer transistor T1receives a transfer signal TX, which transfers the charge accumulated in photodiode PD to a floating drain/diffusion node FD. Reset transistor T2is coupled between a power rail VDD and the node FD to reset the pixel (e.g., discharge or charge the FD and the PD to a preset voltage) under control of a reset signal RST. The node FD is coupled to control the gate of AMP transistor T3. AMP transistor T3is coupled between the power rail VDD and RS transistor T4. AMP transistor T3operates as a source-follower providing a high impedance connection to the floating diffusion FD. Finally, RS transistor T4selectively couples the output of the pixel circuitry to the readout column line under control of a signal RS. Often the photodiode PD of a pixel cell is passivated with a shallow pinning layer to reduce surface defects. In an example where an N type PD is implanted into a P-epitaxial layer, the pinning is formed by a shallow P type implant.

In normal operation, the photodiode PD and node FD are reset to the supply voltage VDD by temporarily asserting the reset signal RST and the transfer signal TX. The image accumulation window (exposure period) is commenced by de-asserting the transfer signal TX and permitting incident light to charge the photodiode PD. As photogenerated electrons accumulate on the photodiode PD, its voltage decreases (electrons are negative charge carriers). The voltage or charge on photodiode PD is indicative of the intensity of the light incident on the photodiode PD during the exposure period. At the end of the exposure period, the reset signal RST is de-asserted to isolate node FD and the transfer signal TX is asserted to couple the photodiode to node FD and hence the gate of AMP transistor T3. The charge transfer causes the voltage of node FD to drop from VDD to a second voltage indicative of the amount of charge (e.g., photogenerated electrons accumulated on the photodiode PD during the exposure period). This second voltage biases AMP transistor T3, which is coupled to the readout column line when the signal RS is asserted on RS transistor T4.

As the pixel-size of CIS become smaller for higher pixel density and lower cost, the active area of the PD has also been reduced. For pinned photodiodes, which are commonly used for CIS, the smaller photodiode area leads to a smaller full-well-capacity (the maximum charge that the PD can hold). The reduced full-well-capacity means lower dynamic range and lower signal-to-noise ratio. Therefore, it is often desirable to increase the full-well-capacity of a pinned photodiode.

In a p-n-p pinned photodiode (illustrated) most commonly used for CIS, a common way to increase the full-well-capacity is to increase the doping level of the N-type PD region by increasing the implantation dosage. However, the N type doping level cannot be too high without causing significant image lag, diode leakage current, and other defect pixels (commonly referred to as white pixels).

Multiple p-n-p-n junctions have been proposed to increase the size of the PD region for charge storage and therefore the full-well-capacity. With optimized implants and layout, a full-well-capacity increase of 50% has been demonstrated without increase in pinning voltage or image lag.

Other techniques for increasing the full-well-capacity have also been suggested. For example, it has been proposed to use solid source diffusion (SSD) or plasma doping to form ultra-shallow junctions. The claimed benefit of these techniques is to reduce the surface P type layer thickness and improve blue sensitivity. Another related technique is to grow epitaxial silicon selectively over the surface of the PD to reduce image lag. While it may be possible that these techniques result in high photodiode capacitance, they also introduce additional thermal fabrication steps that can degrade logic circuit performance. The benefit to increasing the PD full well capacity may be limited because thermal diffusion often leads to long dopant tails and therefore reduced capacitance.

FIGS. 2A through 2Dillustrate the conventional process for fabricating a CIS. After the gate layer (e.g., transistors T1-T4) has been formed (FIG. 2A; only the transfer gate is illustrated), the PD region is implanted next to the gate of the transfer transistor T1(FIG. 2B). After the PD region is implanted, but before the sidewall spacers of the transfer transistors are formed, the pinning layer is implanted (FIG. 2C). This order of fabrication provides pinning under the sidewall spacers, which helps to reduce dark current and white pixels. However, the thermal processing for sidewall spacer formation (FIG. 2D) also causes the P type dopants of the pinning layer to diffuse, resulting in a less abrupt p-n junction and therefore a lower full-well-capacity.

DETAILED DESCRIPTION

Embodiments of an apparatus and method for fabricating a CMOS image sensor having a high full-well-capacity are described herein. In the following description numerous specific details are set forth to provide a thorough understanding of the embodiments. One skilled in the relevant art will recognize, however, that the techniques described herein can be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring certain aspects.

FIG. 3is a cross-sectional view of an image sensor300having a high full-well-capacity, in accordance with an embodiment of the invention. Image sensor300is illustrated with a four transistor (“4T”) pixel architecture; however, it should be appreciated that embodiments of the invention are equally applicable to other pixel architectures such as 5T, 6T, or otherwise.

The illustrated embodiment of image sensor300includes a photodiode PD, a transfer transistor T1, a floating diffusion node FD, a reset transistor T2, a source-follower (“SF”) or amplifier (“AMP”) transistor T3, a row select (“RS”) transistor T4, and a pinning layer305. The illustrated embodiment of transfer transistor T1includes a thinned sidewall spacer310, a regular sidewall spacer315, and a gate320. In one embodiment, image sensor300is formed on a P-epitaxial layer325with a N type doped PD and a P type pinning layer305. However, it should be appreciated that embodiments of the invention are equally applicable to image sensors having P type PD regions formed in an N-epitaxial layer. AlthoughFIG. 3illustrates a single image sensor, it should be appreciated that the structure of image sensor300may be replicated in a grid-like pattern to form a CMOS imaging array where each pixel is separated from adjacent pixels by shallow trench isolations (“STI”) (e.g., seeFIG. 7).

Embodiments of the present invention facilitate a very shallow pinning layer305having an abrupt p-n junction (dopant profile). The abrupt p-n junction is achieved with the addition of only one masking step and no thermal processing changes to the CMOS process. The shallow depth and abrupt junction of pinning layer305has the overall effect of increasing the full-well-capacity of image sensor300versus conventional image sensors.

In one embodiment, the shallow depth and abrupt junction of pinning layer305is achieved by implanting pinning layer305after formation of sidewall spacers310and315. Reordering pinning layer305implantation after sidewall spacer formation improves the fidelity of the p-n junction because sidewall spacer formation is a relatively high temperature processing step, which cause dopant diffusion and a less abrupt boundary of the p-n junction. To compensate for process reordering, thinned sidewall spacer310is thinned relative to regular sidewall spacer315. If not thinned, a pinning layer gap would be left under the sidewall spacer adjacent to the PD, which could increase the incidence of dark current and white pixels. In some embodiments, thinned sidewall spacer310could be entirely removed so that the side of transfer gate320adjacent to the PD is not covered by a sidewall spacer.

In one embodiment, sidewalls spacers310and315are formed from a multilayer spacer film (e.g., oxide-nitride-oxide multilayer film) and etched in a manner such that thinned sidewall spacer310is significantly narrower than regular sidewall spacer315. In one embodiment thinned sidewall spacer310is at least 2 or 3 times narrower than regular sidewall spacer315. For example, thinned sidewall spacer310may be only300angstroms wide.

FIG. 4is a flow chart illustrating a process400for fabricating image sensor300having a high full-well-capacity, in accordance with an embodiment of the invention. The order in which some or all of the process blocks appear in process400should not be deemed limiting. Rather, one of ordinary skill in the art having the benefit of the present disclosure will understand that some of the process blocks may be executed in a variety of orders not illustrated.

In a process block405, conventional CMOS image sensor (“CIS”) fabrication flow is followed up to formation of pixel circuitry formation (including transfer gate320). In a process block410, photosensor PD is formed (seeFIG. 5A). In one embodiment, the PD region may be implanted with N type dopants to form an N type doped PD region.

In a process block415, a spacer film505is conformally formed over the top surface of the pixel including transfer gate320and the PD region (seeFIG. 5B). Spacer film505may be formed of a variety of insulating materials. In one embodiment, spacer film505is a multilayer film formed by sequentially depositing layers of oxide-nitride-oxide (illustrated inFIG. 5Bwith dashed lines).

In a process block420, a photolithography and etching mask510is formed over the surface of the pixel to protect the pixel circuitry (floating diffusion, AMP transistor, reset transistor, RS transistor) and peripheral logic circuitry while exposing the PD region and a portion of transfer gate320adjacent to the PD region (seeFIG. 5C). Once mask510has been patterned, the exposed portions of spacer film505are etched (process block425). As illustrated inFIG. 5C, the exposed portion of spacer film505is thinned. In one embodiment, spacer film505is thinned by removing the top layer of oxide from the multilayer oxide-nitride-oxide spacer film.

After thinning the exposed portions of spacer film505, mask510is removed (process block430) and the normal spacer dry etch is performed to form sidewall spacers310and315(process block435). Since the portion of spacer film505lapping over the corner of transfer gate320adjacent to the PD region was already thinned, spacer310is significantly narrower than spacer315after the spacer etch. For example, regular sidewall spacer315may be 2 or 3 times wider than thinned sidewall spacer310. Of course, other relative widths, either greater or lesser, may be used as well. In one embodiment, thinned sidewall spacer310is approximately 300 angstroms wide.

In a process block440, a doping mask515is formed and pinning layer305implanted to passivate the surface of the PD region. In one embodiment, the dopants are implanted at a small angle (e.g., 5 to 10 degrees) so that pinning layer305extends under thinned sidewall spacer310. Finally, conventional CIS fabrication procedures are followed to completion. These final processes may include source/drain implantation, source/drain anneal, silicidation, formation of the backend metal stack, polymer planarization, microlens formation, and otherwise. Alternatively, implantation of pinning layer305may be performed after source/drain anneal, but prior to the salicidation anneal in order to further preserve the pinning profile.

In an alternative embodiment, mask510may be used as both an etching mask and doping mask. In this alternative embodiment, mask515is not used and pinning layer305is implanted prior to removal of mask510. Instead, the pinning layer dopants are implanted through the thinned portion of spacer film505prior to the spacer etch performed in process block435.

Since process400moves formation of pinning layer305to a later fabrication stage after the high temperature deposition of spacer film505, process400generates a shallow pinning layer305and an abrupt p-n junction over the PD region. Additionally, a small increase in the light transmission into the PD region is achieved due to the thinning of sidewall spacer310.

FIG. 6is a flow chart illustrating an alternative process600for fabricating image sensor300having a high full-well-capacity, in accordance with an embodiment of the invention. Again, the order in which some or all of the process blocks appear in process600should not be deemed limiting. Rather, one of ordinary skill in the art having the benefit of the present disclosure will understand that some of the process blocks may be executed in a variety of orders not illustrated.

Process600is the same as process400up to and including process block635, with the exception of process block625. In process block625, the exposed portion of spacer film505is completely removed, as opposed to merely thinned. However, in one embodiment of process400, spacer film505is also completely removed in the exposed portions, except for the immediately adjacent to the sidewall of transfer gate320.

In a process block640, a silicide protection oxide is formed over the PD region using a low temperature chemical vapor deposition (“CVD”) technique. In a process block645, pinning layer305is implanted into the interface between the silicide protection oxide and the top surface of the PD region. The implant energy can be chosen to place the dopant profile peak at the silicon-oxide interface. This helps reduce the thickness of pinning layer305and enhance collection of blue light for a front-side illumination configuration. Accordingly, in this alternative embodiment, the pinning implant is performed after deposition of the silicide protection oxide to further enhance the fidelity of the p-n junction between pinning layer305and the PD region.

Finally, in a process block650, conventional CIS fabrication procedures are followed to completion. These final processes may include source/drain implantation, source/drain anneal, silicide anneal, formation of the backend metal stack, polymer planarization, microlens formation, and otherwise.

FIG. 7is a block diagram illustrating an imaging system700, in accordance with an embodiment of the invention. The illustrated embodiment of imaging system700includes an image sensor array705, readout circuitry710, function logic715, and control circuitry720.

Image sensor array705is a two-dimensional (“2D”) array of image sensors or pixels (e.g., pixels P1, P2. . . , Pn). In one embodiment, each pixel P1-Pn may be implemented with a high full-well-capacity image sensor, such as image sensor300illustrated inFIG. 3. In one embodiment, each pixel is a complementary metal-oxide-semiconductor (“CMOS”) imaging pixel. Image sensor array705may be implemented as either a front side illuminated image sensor array or a backside illuminated image sensor array. In one embodiment, image sensor array705includes a color filter pattern, such as a Bayer pattern or mosaic of red, green, and blue additive filters (e.g., RGB, RGBG or GRGB), a color filter pattern of cyan, magenta, yellow, and key (black) subtractive filters (e.g., CMYK), a combination of both, or otherwise. As illustrated, each pixel is arranged into a row (e.g., rows R1to Ry) and a column (e.g., column C1to Cx) to acquire image data of a person, place, or object, which can then be used to render a 2D image of the person, place, or object.

After each pixel has acquired its image data or image charge, the image data is readout by readout circuitry710and transferred to function logic715. Readout circuitry710may include amplification circuitry, analog-to-digital (“ADC”) conversion circuitry, or otherwise. Function logic715may simply store the image data or even manipulate the image data by applying post image effects (e.g., crop, rotate, remove red eye, adjust brightness, adjust contrast, or otherwise). In one embodiment, readout circuitry710may readout a row of image data at a time along readout column lines (illustrated) or may readout the image data using a variety of other techniques (not illustrated), such as a column readout, a serial readout, or a full parallel readout of all pixels simultaneously.

Control circuitry720is coupled to image sensor array705to control operational characteristic of image sensor array705. For example, control circuitry720may generate a shutter signal for controlling image acquisition. In one embodiment, the shutter signal is a global shutter signal for simultaneously enabling all pixels within image sensor array705to simultaneously capture their respective image data during a single acquisition window (exposure period). In an alternative embodiment, the shutter signal is a rolling shutter signal whereby each row, column, or group of pixels is sequentially enabled during consecutive acquisition windows.

FIG. 8is a circuit diagram illustrating pixel circuitry800of two four-transistor (“4T”) pixels within an image sensor array, in accordance with an embodiment of the invention. Pixel circuitry800is one possible pixel circuitry architecture for implementing each pixel within image sensor array705ofFIG. 7. However, it should be appreciated that embodiments of the present invention are not limited to 4T pixel architectures; rather, one of ordinary skill in the art having the benefit of the instant disclosure will understand that the present teachings are also applicable to 3T designs, 5T designs, and various other pixel architectures.

InFIG. 8, pixels Pa and Pb are arranged in two rows and one column. The illustrated embodiment of each pixel circuitry800includes a photodiode PD, a transfer transistor T1, a reset transistor T2, a source-follower (“SF”) transistor T3, and a select transistor T4. During operation, transfer transistor T1receives a transfer signal TX, which transfers the charge accumulated in photodiode PD to a floating diffusion node FD. In one embodiment, floating diffusion node FD may be coupled to a storage capacitor for temporarily storing image charges.

Reset transistor T2is coupled between a power rail VDD and the floating diffusion node FD to reset the pixel (e.g., discharge or charge the FD and the PD to a preset voltage) under control of a reset signal RST. The floating diffusion node FD is coupled to control the gate of SF transistor T3. SF transistor T3is coupled between the power rail VDD and select transistor T4. SF transistor T3operates as a source-follower providing a high impedance connection to the floating diffusion FD. Finally, select transistor T4selectively couples the output of pixel circuitry800to the readout column line under control of a select signal SEL.

In one embodiment, the TX signal, the RST signal, and the SEL signal are generated by control circuitry720. In an embodiment where image sensor array705operates with a global shutter, the global shutter signal is coupled to the gate of each transfer transistor T1in the entire image sensor array705to simultaneously commence charge transfer from each pixel's photodiode PD. Alternatively, rolling shutter signals may be applied to groups of transfer transistors T1.