Semiconductor device with gate inside U-shaped channel and methods of making such a device

One illustrative method disclosed herein includes, among other things, forming a trench in a semiconductor substrate, forming a liner semiconductor material above the entire interior surface of the trench, the liner semiconductor material defining a transistor cavity, forming a gate structure that is at least partially positioned within the transistor cavity, and performing at least one epitaxial deposition process to form a source region structure and a drain region structure on opposite sides of the gate structure, wherein at least a portion of each of the source region structure and the drain region structure is positioned within the transistor cavity.

BACKGROUND OF THE INVENTION

1. Field of the Invention

Generally, the present disclosure relates to the manufacture of FET semiconductor devices, and, more specifically, to various semiconductor devices with a gate positioned at least partially inside a generally U-shaped channel semiconductor material and various methods of making such devices.

2. Description of the Related Art

In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially field effect transistors (FETs), are provided and operated on a restricted chip area. FETs come in a variety of different configurations, e.g., planar devices, FinFET devices, horizontal and vertical nanowire devices, etc. These FET devices are typically operated in a switched mode, that is, these devices exhibit a highly conductive state (on-state) and a high impedance state (off-state). The state of the field effect transistor is controlled by a gate electrode, which controls, upon application of an appropriate control voltage, the conductivity of a channel region formed between a drain region and a source region. The gate structures for such transistor devices may be manufactured using so-called “gate-first” or “replacement gate” (gate-last) manufacturing techniques.

To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the years. More specifically, the channel length of FETs has been significantly decreased, which has resulted in improving the switching speed of FETs. However, decreasing the channel length of a FET also decreases the distance between the source region and the drain region. In some cases, this decrease in the separation between the source and the drain makes it difficult to efficiently inhibit the electrical potential of the source region and the channel from being adversely affected by the electrical potential of the drain. This is sometimes referred to as a so-called short channel effect, wherein the characteristic of the FET as an active switch is degraded. In contrast to a planar transistor device, which as the name implies has a generally planar structure, a so-called FinFET device has a three-dimensional (3D) structure. That is, the gate structure of a FinFET device may be positioned around both the sides and the upper surface of a portion of a fin that was previously defined in the substrate to thereby form a tri-gate structure so as to use a channel having a three-dimensional structure instead of a planar structure. That is, unlike a planar FET, in a FinFET device, a channel is formed perpendicular to a surface of the semiconducting substrate so as to reduce the physical size of the semiconductor device. Also, in a FinFET, the junction capacitance at the drain region of the device is greatly reduced, which tends to significantly reduce short channel effects. For a given foot-print, FinFETs tend to be able to generate significantly higher drive current density than planar transistor devices.

Another known transistor device is typically referred to as a nanowire device or sometimes a “gate all around” device. In a nanowire device, at least the channel region of the device is comprised of one or more very small diameter, wire-like semiconductor structures. As with the other types of transistor devices discussed above, current flow through a nanowire device is controlled by setting the voltage applied to the gate electrode. When an appropriate voltage is applied to the gate electrode, the channel region of the nanowire device becomes conductive, and electrical current is permitted to flow between the source region and the drain region through the conductive channel region, i.e., current flows through the nanowire structure.

As device dimensions have decreased, it is becoming ever more challenging to maintain adequate control of the channel region of transistor devices during operation. Device designers have used various techniques to insure that there is adequate capacitive coupling between the gate electrode of the device and the channel region of the device during operation. Absent proper capacitive coupling, control of the channel region is difficult and may result in devices having less desirable electrical performance capabilities.

Device designers are under constant pressure to increase the operating speed and electrical performance of transistors and integrated circuit products that employ such transistors. Given that the gate length (the distance between the source and drain regions) on modern transistor devices may be approximately 30-50 nm, and that further gate length reduction below 15 nm is anticipated in the future, device designers have employed a variety of techniques in an effort to improve device performance, e.g., the use of high-k dielectrics, the use of metal gate electrode structures, the incorporation of work function metals in the gate electrode structure and the use of channel stress engineering techniques on transistors (create a tensile stress in the channel region for NMOS transistors and create a compressive stress in the channel region for PMOS transistors). Device designers are also under constant pressure to reduce the physical size of integrated circuit products, especially products intended for mobile applications such as laptop computers, cell phones, etc. Thus, increasing the packing density of transistor devices in such integrated circuit products is always a desirable goal.

The present disclosure is directed to various semiconductor devices with a gate positioned at least partially inside a generally U-shaped channel semiconductor material and various methods of making such devices that may reduce or eliminate one or more of the problems identified above.

SUMMARY OF THE INVENTION

Generally, the present disclosure is directed to various semiconductor devices with a gate positioned at least partially inside a generally U-shaped channel semiconductor material and various methods of making such devices.

One illustrative method disclosed herein includes, among other things, forming a trench in a semiconductor substrate, forming a liner semiconductor material above the entire interior surface of the trench, the liner semiconductor material defining a transistor cavity, forming a gate structure that is at least partially positioned within the transistor cavity and performing at least one epitaxial deposition process to form a source region structure and a drain region structure on opposite sides of the gate structure, wherein at least a portion of each of the source region structure and the drain region structure is positioned within the transistor cavity.

Another illustrative method disclosed herein involves, among other things, forming a trench in a semiconductor substrate, forming a generally U-shaped liner semiconductor within the trench wherein the liner semiconductor material defines a transistor cavity, forming a gate structure within the transistor cavity wherein the gate structure has an upper surface that is positioned above or level with an upper surface of the transistor cavity, and performing at least one epitaxial deposition process to form a source region structure and a drain region structure on opposite sides of the gate structure, wherein at least a portion of each of the source region structure and the drain region structure is positioned within the transistor cavity.

One illustrative device disclosed herein includes, among other things, a trench defined in a semiconductor substrate, a liner semiconductor material positioned within the trench, the liner semiconductor material defining a transistor cavity, a gate structure that is at least partially positioned within the transistor cavity and a source region structure and a drain region structure positioned on opposite sides of the gate structure, wherein at least a portion of each of the source region structure and the drain region structure is positioned within the transistor cavity.

DETAILED DESCRIPTION

The present disclosure is directed to various semiconductor devices with a gate positioned at least partially inside a cavity defined by a generally U-shaped liner channel semiconductor material and various methods of making such devices. The present disclosure is also directed to other illustrative methods disclosed herein of forming source/drain regions that are positioned at least partially inside a generally U-shaped semiconductor material by using a plurality of placeholder source/drain structures. As will be readily apparent to those skilled in the art upon a complete reading of the present application, the present method is applicable to a variety of devices, including, but not limited to, logic devices, memory devices, etc., and the methods disclosed herein may be employed to form N-type or P-type semiconductor devices. With reference to the attached figures, various illustrative embodiments of the methods and devices disclosed herein will now be described in more detail.

FIGS. 1A-1Tdepict various illustrative methods disclosed herein of forming various semiconductor devices with a gate positioned at least partially inside a generally U-shaped channel semiconductor material.FIG. 1Ais provided to depict where various cross-sectional views are depicted in the attached drawings. In general, a trench12will be formed in a semiconductor substrate14and a thin generally U-shaped liner semiconductor material (when viewed in a cross-section taken through the channel region of the device in a direction parallel to the gate width (GW) direction of the device) will be formed in the trench12, e.g., grown on the sidewalls and bottom of the trench12. Additionally, as will be appreciated by those skilled in the art after a complete reading of the present application, the trench12can be very long and cut into shorter trenches after the thin generally U-shaped liner semiconductor material (i.e., the epi liner) is formed in the trench12. The gate structure and the source/drain regions for the device will be formed at least partially (and in some cases entirely) within the generally U-shaped liner semiconductor material. As depicted inFIG. 1A, the shape of the initial trench and the corresponding generally U-shaped liner semiconductor material can vary depending upon the particular application. For example,FIG. 1Adepicts a generally rectangular shaped trench12, a tapered trench12A, a more U-shaped trench12B, an “inverted Omega” shaped trench12C, a “V” shaped trench depicted by the dashed line12D, etc. As used herein and in the attached claims, when reference is made to the trench, the liner semiconductor material and/or the gate materials as having a “generally U-shaped cross-sectional configuration” and/or being “generally U-shaped,” such language should be understood and interpreted to cover any desired shape of the initial trench e.g., the trenches12,12A,12B,12C and12D where the trench has sidewalls and a bottom surface. In the following drawings, the view “X-X” is a cross-sectional view taken through the channel region of the device in a direction parallel to the gate width (GW) direction of the device; the view “Y-Y” is a cross-sectional view taken through one of the source/drain regions of the device in a direction parallel to the gate width direction of the device; and the view “Z-Z” is a cross-sectional view taken through the channel region and both of the source/drain regions of the device in a direction corresponding the gate length (GL—current transport) direction of the device.

As depicted inFIG. 1B, one illustrative embodiment of the device10will be formed in and above a semiconductor substrate14, such as a silicon substrate. However, the terms “substrate” or “semiconductor substrate” should be understood to cover all semiconducting materials and all forms of such materials. The device10may be either an NMOS or a PMOS transistor. The gate structure of the device10may be formed using either so-called “gate-first” or “replacement gate” (“gate-last”) techniques. Additionally, various doped regions, e.g., source/drain regions, halo implant regions, well regions and the like, are not depicted in the attached drawings. Of course, the inventions disclosed herein should not be considered to be limited to the illustrative examples depicted and described herein. The various components and structures of the device10disclosed herein may be formed using a variety of different materials and by performing a variety of known techniques, e.g., a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, a thermal growth process, epi growth processes, spin-coating techniques, etc. The thicknesses of these various layers of material may also vary depending upon the particular application.

FIG. 1Bdepicts the device10after several process operations were performed. First, an isolation implant region18was formed in the substrate14by performing an ion implantation process through an implant mask (not shown), such as a patterned layer of photoresist material. In the case of an NMOS device10, P-type dopants will be implanted to form the isolation implant region18. Conversely, in the case of a PMOS device10, N-type dopants will be implanted to form the isolation implant region18. The dopant concentration of the isolation implant region18should be such that it functions to electrically isolate the portion of the substrate14positioned above the isolation implant region18from the portion of the substrate14positioned below the isolation implant region18. The actual concentration of dopants in the isolation implant region18may vary depending upon the particular application, e.g., 1015-1016ions/cm3. In one embodiment, the isolation implant region18may have a vertical thickness that is at least about 20 nm or more. An anneal process may or may not be performed after the ions are implanted into the substrate14before performing any other process operations. Also depicted inFIG. 1Bis a patterned hard mask layer20, e.g., silicon dioxide, with an opening20A formed therein that corresponds to the trench to be formed in the substrate14. The patterned hard mask20may be formed by depositing the hard mask material and patterning the hard mask material by performing known masking and etching processes.

FIG. 1Cdepicts the device10after an etching process, e.g., an anisotropic etching process, was performed through the patterned hard mask layer20to define one example of the illustrative trench12in the substrate14wherein the trench12has a generally U-shaped cross-sectional configuration (a rectangular cross-sectional configuration in the example depicted in the drawings). As mentioned earlier, the trench may have other configurations, such as the trenches12A,12B,12C and12D shown inFIG. 1A. Unless otherwise noted, in the illustrative examples depicted in the attached drawings, the trench12shown inFIG. 1Cwill be shown. However, in an actual real-world device, the sidewalls of the trench12may be somewhat inwardly tapered, like the trench12A shown inFIG. 1A. In some cases, the trench may tend to have a more rounded configuration or non-linear configuration (like the trenches12B,12C shown inFIG. 1A) as compared to the generally rectangular configuration of the trench12shown inFIG. 1C. Thus, the size and configuration of the trenches with the generally U-shaped cross-sectional configuration, and the manner in which they are made, should not be considered a limitation of the present invention. The width and height of the trench12may vary depending upon the particular application. In one illustrative embodiment, the trench12may have a lateral width12W (in the gate width direction—see view X-X) at the upper surface14S of the substrate of about 20 nm and a vertical depth of about 30 nm.

FIG. 1Ddepicts the device10after a relatively thin liner layer of semiconductor material22was formed in the trench12by performing any of a variety of known epitaxial deposition processes. The liner semiconductor material22will substantially conform to the configuration of the generally U-shaped trench12. The thickness and material of construction of the generally U-shaped liner semiconductor material22may vary depending upon the particular application. In one embodiment, the liner semiconductor material22is formed to a thickness that is less than a critical thickness for the semiconductor material such that the liner semiconductor material22is fully strained and substantially defect free. For example, in one embodiment, the liner semiconductor material22may be comprised of a layer of silicon-germanium (Si(1-x)Ge(x)), and it may have a thickness of about 2-4 nm. In one example, the liner semiconductor material22may be a layer of silicon-germanium (Si(1-x)Ge(x)), where the value of x falls within the range of about 0.10-0.80 (e.g., SiGe(0.1)-SiGe(0.8)). In one illustrative embodiment, the liner semiconductor material22may be made of materials that are specifically tailored for N-type or P-type devices, e.g., SiGe for PMOS devices and SiC for NMOS devices, by masking appropriate areas when forming the liner semiconductor material22. If desired, various materials, such as carbon, may be incorporated into the liner semiconductor material22as it is being formed. In one illustrative embodiment, the semiconductor material22may be one of a III-V material, InGaAs, GaAs, InAs, GaSb, InSbAs, SiGe, Ge, etc. In general, as will be explained more fully below, the liner semiconductor material22should be made of a material that permits the material of the substrate14to be selectively etched and removed relative to the liner semiconductor material22.

The generally U-shaped liner semiconductor material22has a bottom22A, a plurality of substantially vertically oriented sidewalls22B and an upper surface22S. The liner semiconductor material22defines a transistor cavity15wherein at least portions of the gate structure and source/drain structures for the device10will be positioned in the completed device10. In one illustrative embodiment, the transistor cavity15may have a lateral interior width15W (in the gate width direction—see view X-X) at the upper surface14S of the substrate14of about 14 nm and a vertical depth of about 27 nm. In the depicted example, the liner semiconductor material22is comprised of a single layer of semiconductor material that is formed above and on and in direct physical contact with the interior surfaces of the trench12. However, in some applications, two or more generally U-shaped liner semiconductor materials may be sequentially formed within the trench12wherein, in that case, the inner most liner layer within the trench12would serve to define the transistor cavity15, while the first (outermost) liner layer within the trench12would need to be made of a material that permits the material of the substrate14to be selectively etched and removed relative to the outermost liner semiconductor material.

As indicated above, the gate structure for the device10may be formed using either “gate-first” or “replacement gate” processing techniques. The following drawings will depict the illustrative situation where the gate structure is formed using a replacement gate technique. Accordingly,FIG. 1Edepicts the device10after an illustrative dummy or sacrificial gate structure24was formed in the transistor cavity15using well-known techniques. The gate-length (GL) and gate-width (GW) direction of the device10are depicted in the plan view drawing. In one illustrative embodiment, the schematically depicted sacrificial gate structure24includes an illustrative sacrificial gate insulation layer24A and an illustrative sacrificial gate electrode24B. An illustrative gate cap layer26(e.g., silicon nitride) may also be formed above the sacrificial gate electrode24B. A sidewall spacer28(e.g., silicon nitride) has also been formed adjacent the sacrificial gate structure24. The sacrificial gate structure24, the gate cap layer26and the spacer28may all be formed using traditional manufacturing techniques. The sacrificial gate insulation layer24A may be comprised of a variety of different materials, such as, for example, silicon dioxide, etc., and its thickness may vary depending upon the particular application, e.g., it may have a physical thickness of about 0.5-3 nm. Similarly, the sacrificial gate electrode24B may also be made of a variety of conductive materials, e.g., polysilicon, amorphous silicon, etc. As depicted, a substantial portion of the sacrificial gate structure24is positioned within the interior of the transistor cavity15, i.e., within the generally U-shaped liner semiconductor material22. In operation, portions of the liner semiconductor material22positioned adjacent the sacrificial gate structure24will act as the channel region of the completed device10. Formation of the replacement gate structure24results in the creation of source/drain cavities22X within the transistor cavity15.

FIG. 1Fdepicts the device10after an epitaxial growth process was performed to form source/drain structures30in the source/drain cavities22X, i.e., on the exposed portions of the sidewalls22B and the bottom22A of the transistor cavity15. The source/drain structures30may be comprised of a variety of different semiconductor materials. For example, the source/drain structures30may be comprised of silicon, SiGe, Ge, SiC, a III-V material, InGaAs, GaAs, InAs, GaSb, InSbAs, etc. Depending upon the materials selected for the source/drain structures30and the liner semiconductor material22, the liner semiconductor material22may or may not be readily visible and distinctive from the source/drain structures30after the source/drain structures30are formed, i.e., the liner semiconductor material22may effectively merge into the source/drain structures30. Appropriate N or P type dopant materials may be added to the source/drain structures30as they are being formed, i.e., in situ doping, or the N or P type dopant materials may be added to the source/drain structures30after they are formed by performing one or more ion implantation processes. The physical size of the source/drain structures30may vary depending upon the particular application. In the example shown inFIG. 1F, the epi growth process was stopped at a point wherein the epi material just substantially fills the source/drain cavities22X, note the beginning of tapered edge30A of epi material reflecting the shape the epi material will take when growing in an unconfined space due to the crystallographic orientation of the liner semiconductor material22. In the illustrative embodiment shown inFIG. 1F, the source/drain structures30may have a lateral width30W (in the gate width direction—see view Y-Y) over the entire vertical height of the source/drain structures30that is less than the lateral width12W (seeFIG. 1C) of the trench12at the upper surface14S of the substrate14.FIG. 1Odepicts an example wherein the epi process is performed to form larger (taller) and wider epi source/drain structures30X. In the case where a transistor device10spans multiple of the generally U-shaped semiconductor material regions22(formed in spaced-apart trenches), the source drain regions (30,30X) may remain unmerged or they may be merged together by continuing to grow epi material.

FIG. 1Gdepicts the device10after a layer of insulating material32was formed on the device10. The layer of insulating material32may be comprised of a variety of different materials, such as, for example, silicon dioxide.

FIG. 1Hdepicts the device10after one or more chemical mechanical polishing (CMP) processes were performed to planarize the upper surface of the layer of insulating material32using the upper surface of the sacrificial gate electrode24B as a polish-stop layer. This polishing process removes the gate cap layer26and exposes the sacrificial gate electrode24B for removal.

FIG. 1Idepicts the device10after one or more etching processes were performed to remove the sacrificial gate structure24, i.e., the sacrificial gate electrode24B and the sacrificial gate insulation layer24A, and thereby define a replacement gate cavity36.

The next major process operation involves the formation of the materials for the final gate structure37for the device10. Accordingly,FIG. 1Jdepicts the device10after an illustrative gate insulation layer38and the material (or multiple materials) for an illustrative gate electrode40were deposited into the gate cavity36and after a CMP process was performed to remove excess materials positioned outside of the gate cavity36above the insulating material32. The gate insulation layer38may be comprised of a variety of different materials, such as, for example, silicon dioxide, a so-called high-k (k value greater than 10) insulation material (where k is the relative dielectric constant), etc. The thickness of the gate insulation layer38may also vary depending upon the particular application, e.g., it may have a physical thickness of about 0.5-3 nm. Similarly, the gate electrode40may also be of a variety of conductive materials, such as highly doped polysilicon or amorphous silicon, or it may be comprised of one metal layer or a stack of metal layers that act as the gate electrode. The gate electrode may also be comprised of one metal layer to match the required work function of the device and a metal layer cap to prevent oxidation and provide good contact adhesion and low contact resistance. As will be recognized by those skilled in the art after a complete reading of the present application, the final gate structure37, i.e., the gate insulation layer and the gate electrode, is intended to be representative in nature. That is, the final gate structure37may be comprised of a variety of different materials and it may have a variety of configurations.

FIG. 1Kdepicts the device10after one or more recess etching processes were performed to recess the materials of the final gate structure37within the gate cavity36so as to make room for a gate cap layer42. Thereafter, a layer of gate cap material, e.g., silicon nitride, was deposited so as to overfill the cavity36above the recessed gate materials and a CMP process operation was performed to remove excess amounts of the gate cap material positioned outside of the gate cavity36so as to thereby define the gate cap layer42. As depicted, the final gate structure37is positioned adjacent the sidewalls22B and the bottom surface22A of the generally U-shaped liner semiconductor material22. As noted above, in operation, portions of the liner semiconductor material22that surrounds three sides of the final gate structure37will act as the channel region of the device10while other portions of the liner semiconductor material22extend into the source/drain regions of the device10and contact or become part of the source/drain structures30. In the example depicted inFIG. 1K(view X-X), the gate materials were recessed such that the upper surface37S of the final gate structure37is approximately level with the upper surface22S of the transistor cavity15. However, in some cases, the upper surface37S of the of the final gate structure37may be lower or higher than that depicted inFIG. 1K. Ideally, the upper surface37S of the final gate structure37will be located level with or slightly above the upper surface22S of the transistor cavity15such that the full vertical height of the liner semiconductor sidewalls22B may be used as part of the channel region of the device, i.e., so that the entire volume of the liner semiconductor material22in the channel region of the device may be utilized. Such a gate-liner configuration will maximize the drive current that the device10may generate. However, in other cases, the recessing of the gate materials may result in the upper surface37S of the final gate structure37being positioned slightly below the upper surface22S of the transistor cavity15, but nevertheless result in a fully functional device.

FIG. 1Ldepicts the device10after a brief recess etching process was performed to remove the portions of the spacer28positioned above the surface14S of the substrate14(see view X-X). In the case where the spacer28and the gate cap layer42are made of the same material (e.g., silicon nitride), this process operation will also result in some thinning of the gate cap layer42as depicted in the drawing.

FIG. 1Mdepicts the device10after an etching process, such as a wet etching process or a combination of a dry etching process and a wet etching process, was performed to remove the material of the substrate14relative to the generally U-shaped liner semiconductor material22in the general area of the channel region of the device10and thereby define a cavity50that surrounds (on three sides) the liner semiconductor material22in the channel region of the device10. In one embodiment, the cavity50is formed such that a portion52of the cavity extends under the liner semiconductor material22, i.e., under the transistor cavity15, in the gate width direction of the device. In one embodiment, the etching process is performed such that a residual portion14B of the substrate material14remains positioned between the bottom of the semiconductor material22and the isolation implant region18. In one particularly illustrative embodiment, there may be little to none of the residual substrate material14B at a location above the implant region18(i.e., a portion of the cavity52may extend into or contact the implant region18) so as to provide good isolation between the source and drain regions. As depicted in view Z-Z (gate length cross-section) the cavity50may be formed such that the portion52of the cavity50extends laterally under the entire channel of the device10and partially under the source/drain structures30.

FIG. 1Ndepicts the device10after several process operations were performed to essentially fill the cavity50with insulating material54. In one embodiment, the layer of insulating material54may be deposited so as to overfill the cavity50. Thereafter, a CMP process may be performed to remove excess portions of the layer of insulating material54using the layer of insulating material38as a polish-stop layer. The layer of insulating material54may be comprised of a variety of different materials, such as, for example, silicon dioxide, silicon oxynitride or any other dielectric material in common use in the semiconductor manufacturing industry, and it may be formed by performing a variety of techniques, e.g., CVD, ALD, etc. The layer of insulating material54may be comprised of the same material as that of the layer of insulating material20, or it may be comprised of a different material. In the depicted example, the final gate structure37is positioned entirely within the generally U-shaped liner semiconductor material22(see view X-X) and the channel region portion of the liner semiconductor material22are surrounded on three sides by the insulating material54. At the point of fabrication depicted inFIG. 1N, traditional manufacturing techniques may be performed to complete the manufacture of the device10. For example, contacts and metallization layers may be formed above the device10using traditional techniques.

As indicated above, the devices disclosed herein may be formed in trenches having a variety of configurations.FIGS. 1P and 1Qare examples of devices10formed in trenches having the configuration of the trenches12A and12B, respectively, shown inFIG. 1A.

As indicated above, the gate structure for the device10may be formed using gate first techniques as well as replacement gate techniques. In the case of a gate first technique, the sacrificial gate structure24shown inFIG. 1Ewould instead be a final gate structure.FIG. 1Rdepicts a final gate structure25for the device formed using a gate first technique. As shown therein, the gate structure25is comprised of a gate insulation layer27, e.g., silicon dioxide, and a gate electrode29comprised of polysilicon.FIG. 1Sdepicts a gate structure25that is comprised of a high-k gate insulation layer27A, e.g., silicon dioxide, a work function adjusting metal layer31and one or more conductive materials (e.g., polysilicon and/or other metals) that define a gate electrode33. In a gate first technique, the gate materials may be sequentially deposited (along with a gate cap material) above the substrate14after the trenches12are formed and subsequently patterned to define the overall gate structure.

FIG. 1Tdepicts an embodiment wherein the gate structures described herein may be positioned such that portions of the overall gate structure47of the device are positioned partially with multiple, e.g., three, of the U-shaped liner semiconductor materials22formed in three spaced-apart trenches12defined in the substrate14so as to effectively increase the gate width of such a transistor device. The gate structure47shown inFIG. 1Tis simplistically depicted in that the various individual layers of material, like the gate insulation layer, are not separately depicted. Also shown inFIG. 1Tis a gate cap layer47.

FIGS. 2A-2Edepict yet other illustrative methods disclosed herein of forming source/drain regions that are positioned at least partially inside a generally U-shaped semiconductor material by using a plurality of placeholder source/drain structures.FIG. 2Adepicts a device100at a point in fabrication that corresponds to that shown inFIG. 1D, i.e., after the U-shaped liner semiconductor material22was grown in the trench12so as to define the transistor cavity15.

FIG. 2Bdepicts the device100after a source/drain placeholder material60was deposited into the transistor cavity15and patterned so as to define a gate cavity62between the spaced-apart source/drain placeholder structures. Portions of the bottom22A and sidewalls22B of the liner semiconductor material22are exposed within the gate cavity62. The placeholder material60may be made of a variety of materials, e.g., silicon nitride, and its overall thickness may vary depending upon the particular application.

FIG. 2Cdepicts the device100after the above-described final gate structure37and gate cap layer42were formed in the gate cavity62.

FIG. 2Ddepicts the device100after an etching process was performed through a patterned etch mask (not shown), such as a patterned photoresist mask, to remove the majority of the placeholder material60and thereby define a plurality of source/drain cavities66. Portions of the placeholder material60are left in place adjacent the gate structure37so as to serve the function of sidewall spacers60X to protect and, along with the gate cap layer42, encapsulate the gate materials.

FIG. 2Edepicts the device100after one or more conductive materials, such as a metal or a metal alloy, such as tungsten, cobalt-nickel, nickel, nickel-platinum, etc., was formed in the source/drain cavities66so as to define the final source/drain structures70for the device100. The source/drain structures70may be formed by depositing the appropriate layers of material (if present), e.g., barrier layer, adhesion layer, fill layer, etc., across the substrate14so as to overfill the source/drain cavities66and thereafter performing one or more CMP processes to remove excess materials positioned outside of the source/drain cavities66using the gate cap layer42and the layer of insulating material20as polish-stop materials. To the extent that barrier layers, adhesion layers and the like are formed, they should be considered to be part of the source/drain contact structures70. At the point of fabrication depicted inFIG. 2E, traditional manufacturing techniques may be performed to complete the manufacture of the device100. For example, contacts and metallization layers may be formed above the device100using traditional techniques.

As will be appreciated by those skilled in the art after a complete reading of the present application, the unique architecture and structure of the devices disclosed herein provide many unique benefits. For example, since the liner semiconductor material22may be formed to a thickness that is less than a critical thickness for the semiconductor material22, the U-shaped liner semiconductor material22may be fully strained and substantially defect free. The devices also have a large effective channel volume due to the two substantially vertically oriented legs22B and the bottom portion22A of the liner semiconductor material22, thereby enabling the devices to generate large on-state currents. Additionally, since, in some embodiments (i.e., a transistor formed in a single trench12), the maximum lateral width (in the channel width direction of the device) of the overall finished device is substantially defined by the lateral width12W of the trench12, the devices disclosed herein may be more densely packed than, for example, FinFET devices. As an example, a typical fin pitch used when forming multiple fins for FinFET devices in a substrate may be about 40 nm to insure that when epi material is grown on the fins in the source/drain regions of the devices there is sufficient space between the fins so that no undesirable contact between the epi semiconductor material occurs on adjacent devices. In contrast, since the lateral width12W of the trenches12substantially define the maximum overall lateral width of the overall device (except in cases where additional epi material is grown as shown inFIG. 1O), the trenches12may be formed very close to one another. For example, with reference toFIG. 1T, the lateral space12Z between the trenches12(in the gate width direction of the devices) may be on the order of about 10 nm or even smaller, thereby leading to greater packing densities. With respect to the device100, the formation of the source/drain regions comprised of a metal or metal alloy provides the physical possibility of creating low resistive source/drain contacts for MOSFET devices to thereby improve their operational characteristics.