Display device and manufacturing method thereof

A display device which can prevent a contact defect of a driver IC and a manufacturing method thereof are disclosed. According to the method, a plurality of pattern lines and a plurality of contact electrodes on a substrate are formed. Each pattern line and each contact electrode are connected each other. Anisotropic conductive films, in which a plurality of conductive balls are included, on the substrate are arranged. A plurality of driving circuits on the substrate and allowing bumps of the driving circuits to be opposite the anisotropic conductive films are arranged. Pressure and heat are applied to the driving circuits such that the bumps of the driving circuits allow the conductive balls to be electrically connected to the contact electrodes. A plurality of contact layers connected with the conductive balls are formed by irradiating laser light on contact regions to melt the pattern lines and the contact electrodes.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 U.S.C. 119 to Korean Patent Application No. 10-20080123994, filed on Dec. 8, 2008 and 10-2009-0054001, filed on Jun. 17, 2009 which is hereby incorporated by reference in its entirety.

BACKGROUND

1. Field of the Disclosure

This disclosure relates to a display device, and more particularly to the display device of a chip-on-glass (COG) type preventing a contact defect of a driver integrated circuit chip, and a manufacturing method thereof.

2. Description of the Related Art

As the information society grows, flat display devices capable of displaying information have been widely developed. These flat display devices include liquid crystal display (LCD) devices, organic electro-luminescence display (OLED) devices, plasma display devices, and field emission display devices. Among the above display devices, LCD devices have the advantages that they are light and small and can provide a low power drive and a full color scheme. Accordingly, LCD devices have been widely used for mobile phones, navigation systems, portable computers, televisions and so on.

LCD devices include two substrates and a liquid crystal layer interposed between the substrates. A driver-integrated circuit is disposed on the peripheral region of the liquid crystal panel. The driver-integrated circuit is classified into a chip on glass (COG) type, a tape carrier package (TCP) type, or a chip on film (COF) type according to its loaded shape on the liquid crystal panel. Among these types, the COG type is mainly applied to liquid crystal panels of middle and small sizes because of its simple configuration and easy loading method.

FIG. 1is a planar view showing an LCD device of the COG type according to the related art. As shown inFIG. 1, an LCD device of the COG type according to the related art includes first and second substrates11and13, a liquid crystal layer (not shown) interposed between the substrates11and13. A portion of the device in which the first and second substrates11and13overlap each other, is defined as a display area9displaying an image. The other portion of the device in which the first and second substrates11and13do not overlap each other is defined as a non-display area10.

On the non-display area10of the first substrate11, a flexible printed circuit (FPC) board3is connected with the first substrate11, and gate-driving integrated circuits5and data-driving integrated circuits25to27are mounted. Such a configuration corresponds to the above COG type because the gate-driving integrated circuits5and the data-driving integrated circuits25to27are mounted on substrate11, which is a glass material.

A plurality of pattern lines15ato15d,17a, and17bare formed on the non-display area10. More specifically, the plural pattern lines include gate pattern lines17aand17bconnecting the gate-driving integrated circuits5with the FPC board3, and data pattern lines15ato15dconnecting the data-driving integrated circuits25to27with the FPC board3. The data-driving integrated circuits25to27are cascade-connected to one another by the data pattern lines15ato15d.

The gate-driving integrated circuits5are connected to the display area9by means of gate lines21. The data-driving integrated circuits25to27are connected to the display area9by means of data lines23.

A first data-driving integrated circuit25receives power signals VDD, VDD_gnd, VCC, and VCC_gnd, as well as a gamma voltage, a data signal, and a control signal, which are applied from the FPC board3through the data pattern lines15ato15d. Data voltages derived from the power signals VDD, VDD_gnd, VCC, and VCC_gnd, the gamma voltage, the data signal, and the control signal are applied to the display area9through the data lines23.

Parts of the power signals VDD and VDD_gnd are reference voltages, while the rest of the power signals VCC, and VCC_gnd are drive voltages for driving the data-driving integrated circuits25to27. These power signals VDD, VDD_gnd, VCC, and VCC_gnd have values desired by a specification (or a standard), but can be easily varied. The variation induces the data voltages output from the data-driving integrated circuits25to27to vary as well, thereby causing noise or a dim defect (A: area of causing block dim or block noise,FIG. 1). Actually, the power signals VDD, VDD_gnd, VCC, and VCC_gnd are varied by a contact defect between the data-driving integrated circuits25to27and the data pattern lines15ato15dupon the connection of the data-driving integrated circuits25to27and the data pattern lines15ato15d.

FIG. 2is a planar view showing the data-driving integrated circuits shown inFIG. 1. As shown inFIG. 1, each of the data-driving integrated circuits25to27includes a plurality of bumps31,33, and35. The bumps31,33,35function as cross-linking members which connect the respective data-driving integrated circuits25,26, or27to the data pattern lines15ato15d.

The bumps31,33, and35include input bumps31and output bumps33which are arranged on both horizontal edges of the respective data-driving integrated circuit25,26, or27. They also include data signal output bumps35arranged on a longitudinal edge of the respective data-driving integrated circuit25,26, or27. The input bumps31receive the power signals VDD, VDD_gnd, VCC, and VCC_gnd, as well as the gamma voltage, the data signal, and the control signal. The output bumps33output the power signals VDD, VDD_gnd, VCC, and VCC_gnd, and the gamma voltage, the data signal, and the control signal. The data signal output bumps35output the data voltages.

Similarly, the gate-driving integrated circuit5includes bumps which connect the gate-driving integrated circuit5to the gate pattern lines17aand17band the gate lines21.

FIG. 3is a cross-sectional view showing the data-driving integrated circuit and the first substrate taken along the line I-I′ shown inFIG. 2. As shown inFIG. 3, the substrate11includes a gate insulation film43, data pattern lines45, a passivation (or protective) film47, and contact electrodes48. The reference number “41” is a substrate. The gate insulation film43is formed on the non-display area10of the substrate11. The data pattern lines45are formed separately from each other on the gate insulation film43. In other words, the data pattern lines45are formed in input terminal portions and output terminal portions of the data-driving integrated circuits25,26or27, respectively. The passivation film47is formed to expose the data pattern lines45on the gate insulation film43. The contact electrodes48are formed on the exposed data pattern lines45. The contact electrodes48can electrically connect the respective data-driving integrated circuits25,26, or27to the data pattern lines45.

The first substrate11further includes an anisotropic conductive film (ACF)49having a plurality of conductive balls50and disposed on its non-display area10. The data-driving integrated circuit26which includes bumps31and33is disposed on the ACF49. When the data-driving integrated circuit26is depressed by pressure upon heat, the bumps31and33of the depressed data driver integrated circuit26in turn depress the ACF49, and the ACF49is molten. Thus, the conductive balls50included into the ACF49are electrically connected to the contact electrodes48.

However, it is well-known that adhesions between the ACF49and/or the conductive balls50and contact electrodes48are so bad. In addition, as shown inFIG. 4, as the time passes by, the ACF49is hardened. Thus, the ACF49including the conductive balls50is detached from the contact electrodes48such that the conductive balls50are not connected to the contact electrodes48any more. Therefore, contact defects are generated in contact areas of the input terminal portions and/or the output terminal portions of the data-driving integrated circuits25,26or27. The contact defects can be defined as dimensions in which the bumps31and33overlap with the contact electrodes48, respectively.

Furthermore, it is well-known that adhesions between the contact electrodes48and the data pattern lines45are comparatively bad. Contact defects are further generated in contact areas of the input terminal portions and/or the output terminal portions of the data-driving integrated circuits25,26or27.

Due to this contact defect, a contact resistance between the bump31or33of the data-driving integrated circuit26and the contact electrode48increases. Accordingly, the power signals VDD, VDD_gnd, VCC, and VCC_gnd, as well as the gamma voltage, the data signal, and the control signal vary due to the increased contact resistance. For instance, voltage levels of the power signals VDD and VCC decreases, whereas voltage levels of the power signals VDD_gnd and VCC_gnd increases. The power signals VCC and VCC_gnd are used to drive each data-driving integrated circuit25,26and27, and the power signals VDD and VDD_gnd are used as reference voltages for generating the gamma voltage.

As shown inFIG. 5, in the case where the power signals VCC and VCC_gnd are set at voltages of “2.7” and “0” according to design specifications (or standards), the power signal VCC drops to a voltage of “2.6” but the power signal VCC_gnd rises to a voltage of “0.4” when the contact resistance between the contact electrode48and the bump31or33of the data-driving integrated circuit is increased. As such, the margin width of VCC (i.e., a voltage difference between VCC and VCC_gnd) reduces from a voltage of “2.7V” down to a voltage of “2.2V”. The data-driving integrated circuit26is then not driven due to the reduced margin width.

More specifically, contact defects can be generated at the input terminal portions and the output terminal portions of the data-driving integrated circuits25to27, which are cascaded to one another and have a margin width with a voltage of “2.3”. In this case, the margin width between the power signal VCC and the power signal VCC_gnd is increasingly reduced according to the procession of from the first data-driving integrated circuit25to the last data-driving integrated circuit27. As such, the last integrated date driver circuit27and other data-driving integrated circuits (for example, a middle data driver integrated circuit26) adjacent to it are not driven and no data voltages are applied to portions of the display area9opposite to the last integrated date driver circuit27and other adjacent data-driving integrated circuits26. This can cause a block noise.

In addition, the increased contact resistance forces the power signal VDD to be lowered and the power signal VDD_gnd to be higher. This causes the generation of varied gamma voltages instead of the desired gamma voltages. The varied gamma voltages generate variations in the data voltages output from the data-driving integrated circuits25to27, thereby causing a gray distortion. Such a gray distortion is more serious according to the procession of from the first data-driving integrated circuit25to the last data-driving integrated circuit27. To rectify this, the gray distortion is generated on the data lines of the display area, which are connected to the last data-driving integrated circuit and the adjacent data-driving integrated circuits, due to the variation of the power signals VDD and VDD-gnd by the contact defect, resulting in a picture defect such as block dim is caused.

The contact defect is also generated between the bump31or33, the data-driving integrated circuit26and the data line23. The data voltage applied from the data-driving integrated circuit26to the data line23is distorted due to the contact defect.

In view of these points, it is necessary to fundamentally prevent the contact defect.

BRIEF SUMMARY

Accordingly, the present embodiments are directed to a display device that substantially obviates one or more of problems due to the limitations and disadvantages of the related art, as well as a manufacturing method thereof.

An object of the present embodiment is to provide a display device that electrically connects all conductive balls within a contact region to a contact electrode so as to prevent a contact defect, as well as a manufacturing method thereof.

Additional features and advantages of the embodiments will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the embodiments. The advantages of the embodiments will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

According to one general aspect of the present embodiment, A method of manufacturing a display device includes: forming a plurality of pattern lines and a plurality of contact electrodes on a substrate, each pattern line and each contact electrode are connected each other; arranging anisotropic conductive films, in which a plurality of conductive balls are included, on the substrate; arranging a plurality of driving circuits on the substrate and allowing bumps of the driving circuits to be opposite the anisotropic conductive films; applying pressure and heat to the driving circuits such that the bumps of the driving circuits allow the conductive balls to be electrically connected to the contact electrodes; and forming a plurality of contact layers connected with the conductive balls by irradiating laser light on contact regions to melt the pattern lines and the contact electrodes.

A display device according to another aspect of the present embodiment includes: a substrate formed with a pattern line and a contact electrode; a driving circuit having a bump; an anisotropic conductive film having a plurality of conductive balls; and a contact layer formed by melting the pattern line and the contact electrode, wherein the contact layer is connected with the conductive balls.

DETAILED DESCRIPTION

Reference will now be made in detail to the embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. These embodiments introduced hereinafter are provided as examples in order to convey their spirits to the ordinary skilled person in the art. Therefore, these embodiments might be embodied in a different shape, so are not limited to these embodiments described here. Also, the size and thickness of the device might be expressed to be exaggerated for the sake of convenience in the drawings. Wherever possible, the same reference numbers will be used throughout this disclosure including the drawings to refer to the same or like parts.

FIG. 6is a planar view showing an LCD device of a COG type according to an embodiment of the present disclosure. Referring toFIG. 6, an LCD device of a COG type according to an embodiment of the present disclosure includes first and second substrates111and113and a liquid crystal layer (not shown) interposed between the substrates111and113. The first and second substrates111and113together with the liquid crystal layer configure a liquid crystal panel101. A portion of the panel in which the first and second substrates111and113overlap each other is defined as a display area125displaying an image. The other portion of the panel in which the first and second substrates111and113do not overlap each other is defined as a non-display area129. The display area125is divided into a plurality of sub-display areas126a,126b,127a,127b,128a,128b,129aand129b.

On the non-display area129of the first substrate111, a flexible printed circuit (FPC) board103is connected with the first substrate111, and gate-driving integrated circuits105and data-driving integrated circuits116a,116b,117a,117b,118a,118b,119a, and119bare mounted. Such a configuration is called as a COG type because the gate-driving integrated circuits105and data-driving integrated circuits116a,116b,117a,117b,118a,118b,119a, and119bare mounted on the substrate111which is a glass material.

In this embodiment, a portion of the LCD panel in which the data-driving integrated circuits116a,116b,117a,117b,118a,118b,119a, and119bare arranged, is divided into a plurality of data driving regions116to119. For instance, the data driving regions116to119each include two data-driving integrated circuits116aand116b,117a,117b,118aand118b,119aand119b. The data-driving integrated circuits116a,116b,117a,117b,118a,118b,119aand119bare opposite to the plurality of the sub-display areas126a,126b,127a,127b,128a,128b,129aand129b, respectively. Data signals from each of the data-driving integrated circuits116a,116b,117a,117b,118a,118b,119aand119bare displayed on each of the sub-display areas126a,126b,127a,127b,128a,128b,129aand129b, respectively.

More specifically, data signals from the data-driving integrated circuit116aof the first data driving region116are displayed on the sub-display area126a. Data signals from the data-driving integrated circuit116bof the first data driving region116are displayed on the second display region126b. Data signals from the data-driving integrated circuit117aof the second data driving region117are displayed on the sub-display region127a. Data signals from the data-driving integrated circuit117bof the second data driving region117are displayed on the sub-display region127b.

The data-driving integrated circuits116a,116b,117a,117b,118a,118b,119a, and119bon each of the data drive regions116to119are in a cascade. For example, the data-driving integrated circuits116aand116bdisposed on the first data driving region116are in a cascade to each other. The data-driving integrated circuits117aand117bdisposed on the second data driving region117are in a cascade to each other. The integrated data driver integrated circuits118aand118bdisposed on the third data driving region118are in a cascade to each other. The data-driving integrated circuits119aand119bdisposed on the fourth data driving region119are in a cascade to each other.

Power signals VDD, VDD_gnd, VCC, and VCC_gnd, as well as gamma voltages, a data signal, and a control signal, which are provided from the FPC board103, are applied to the first to fourth data driving regions116to119. The power signals VDD and VDD_gnd are reference voltages of the gamma voltages, while the power signals VCC and VCC-gnd are drive voltages used to drive the data-driving integrated circuits116ato119b.

The power signals VDD, VDD_gnd, VCC, and VCC_gnd, the gamma voltages, the data signal, and the control signal, which are provided from the FPC board103, are applied to first data-driving integrated circuits116a,117a,118a, and119aeach contained in the first to fourth data driving regions116to119. The power signals VDD, VDD_gnd, VCC, and VCC_gnd, the gamma voltages, the data signal, and the control signal, which are applied to the first data-driving integrated circuits116a,117a,118a, and119a, are transferred to the second data-driving integrated circuits116b,117b,118b, and119bwhich are disposed adjacent to the first data-driving integrated circuits116a,117a,118a, and119ain a cascade. In this manner, the power signals VDD, VDD_gnd, VCC, and VCC_gnd, the gamma voltages, the data signal, and the control signal from the first data-driving integrated circuit116a,117a,118a, or119aon each of the data drive regions116to119can sequentially be transferred to the last of the cascaded data-driving integrated circuits.

More specifically, in the first data driving region116, the power signals VDD, VDD_gnd, VCC, and VCC_gnd, the gamma voltages, the data signal, and the control signal, which are supplied to the first data-driving integrated circuit116a, are transferred to the second data-driving integrated circuit116bwhich are disposed adjacent to the first data-driving integrated circuit116ain a cascade. In this manner, the power signals VDD, VDD_gnd, VCC, and VCC_gnd, the gamma voltages, the data signal, and the control signal can be applied to the last data-driving integrated circuit on the first data driving region116a.

In the second data driving region117, the power signals VDD, VDD_gnd, VCC, and VCC_gnd, the gamma voltages, the data signal, and the control signal, which are also supplied to the first data-driving integrated circuit117a, are transferred to the second data-driving integrated circuit117bwhich are disposed adjacent to the first data-driving integrated circuit117ain a cascade. In this manner, the power signals VDD, VDD_gnd, VCC, and VCC_gnd, the gamma voltages, the data signal, and the control signal can be applied to the last data-driving integrated circuit on the second data driving region117.

In the third data driving region118, the power signals VDD, VDD_gnd, VCC, and VCC_gnd, the gamma voltages, the data signal, and the control signal, which are supplied to the first data-driving integrated circuit118a, are transferred to the second data-driving integrated circuit118bwhich are disposed adjacent to the first data-driving integrated circuit118ain a cascade. In this manner, the power signals VDD, VDD_gnd, VCC, and VCC_gnd, the gamma voltages, the data signal, and the control signal can be applied to the last data-driving integrated circuit on the third data driving region118.

In the fourth data driving region119, the power signals VDD, VDD_gnd, VCC, and VCC_gnd, the gamma voltages, the data signal, and the control signal, which are supplied to the first data-driving integrated circuit119a, are transferred to the second data-driving integrated circuit119bwhich are disposed adjacent to the first data-driving integrated circuits119ain a cascade. In this manner, the power signals VDD, VDD_gnd, VCC, and VCC_gnd, the gamma voltages, the data signal, and the control signal can be applied to the last data-driving integrated circuit on the fourth data driving region119.

Data signals applied from the data-driving integrated circuits116aand116b,117aand117b,118aand118b, or119aand119b, which are included in each of the data drive regions116to119, can be displayed on the respective sub-display area126a,126b,127a,127b,128a,128b,129aand129bopposite to each of the data-driving integrated circuits116aand116b,117aand117b,118aand118b, or119aand119b, as an image.

A plurality of pattern lines107,147a, and147bare formed on the non-display area129. More specifically, the pattern lines include gate pattern lines107connecting the gate-driving integrated circuits105with the FPC board103, data pattern lines147aconnecting the data-driving integrated circuits116a,117a,118a, and119awith the FPC board103, and data pattern lines147bconnecting between the data-driving integrated circuits116aand116b,117aand117b,118aand118b, and119aand119badjacent to each other.

The gate-driving integrated circuits105are connected to the display area125by means of gate lines121. The data-driving integrated circuits116a,116b,117a,117b,118a,118b,119a, and119bare connected to the display area125by means of data lines123.

Each of the gate-driving integrated circuit105and the data-driving integrated circuits116a,116b,117a,117b,118a,118b,119a, and119bincludes a plurality of bumps (not shown). The bumps function as cross-linking members which connect the gate-driving integrated circuit105to the gate pattern lines107and connect the respective data-driving integrated circuit116a,116b,117a,117b,118a,118b,119a, and119bto the data pattern lines147aand147b.

The bumps include input bumps electrically connected to input pattern lines147aon input terminal portions of the gate-driving integrated circuit105and the data-driving integrated circuit116a,116b,117a,117b,118a,118b,119aand119b, output bumps electrically connected to output pattern lines147bon output terminal portions of the gate-driving integrated circuit105and the data-driving integrated circuit116a,116b,117a,117b,118a,118b,119aand119b, and data signal output bumps electrically connected to the gate lines121and the data lines123on signal output terminal portions of the gate-driving integrated circuit105and the data-driving integrated circuit116a,116b,117a,117b,118a,118b,119aand119b.

The power signals VDD, VDD_gnd, VCC, and VCC_gnd, the gamma voltage, the data signal, and the control signal received by the input bumps of each of the data-driving integrated circuits116a,117a,118a, and119aare supplied to the input bumps of the other adjacent data-driving integrated circuits116b,117b,118b, and119bthrough the output bumps of each of the data-driving integrated circuits116a,117a,118a,119a. Data signals from the data signal output bumps of each data-driving integrated circuit116a,116b,117a,117b,118a,118b,119a, and119bare applied to each sub-display area126a,126b,127a,127b,128a,128b,129aand129bof the display area125through the data lines123, respectively.

On contact regions defined between the bumps and the data pattern lines147aand147b, contact defects can be generated, due to the fact that conductive balls contained in ACF are detached from contact electrodes, and adhesions between the contact electrodes and the data pattern lines are comparatively bad.

In this way, the LCD device of the present embodiment divides two data-driving integrated circuits116aand116b,117aand117b,118aand118b,119aand119bon each of the data driving regions116to119in a cascade each other. Thus, power signals VDD, VDD_gnd, VCC, and VCC_gnd, the gamma voltages, the data signal, and the control signal from the FPC103are individually applied to each of the data driving regions116to119.

As such, the number of the data-driving integrated circuits116aand116b,117aand117b,118aand118b, or119aand119bincluded in each of the data drive regions116to119is remarkably reduced compared with the related art, so that the power signals VDD, VDD_gnd, VCC, and VCC_gnd, the gamma voltages, the data signal, and the control signal applied to the last data-driving integrated circuit116b,117b,118b, or119bon each of the data drive regions116to119are hardly ever varied. Therefore, a block dim and/or noise is not generated.

FIGS. 7A to 7Fare cross-sectional views showing a method of manufacturing an LCD device according to a first embodiment of the present disclosure. The method for manufacturing the data-driving integrated circuit117ashown inFIGS. 7A to 7Fcan be applied to others of the data-driving integrated circuits divisionally included in the data driving regions, as described above. In addition, althoughFIGS. 7A to 7Fwill be limitedly explained referring only to a method of manufacturing an LCD device which prevents the above contact defects between bumps156of the data-driving integrated circuit117aand data pattern lines147aand147b, the method according to an embodiment of the present disclosure is not limited to this. In other words,FIGS. 7A to 7Fcan be equally applied to another method of manufacturing an LCD device for preventing contact defects between bumps156of the data-driving integrated circuit117aand data lines123.

A method of manufacturing an LCD device will now be explained referring toFIGS. 6 and 7Ato7F.

As shown inFIG. 7A, a first substrate111shown inFIG. 6is manufactured by forming a gate insulation film133, data pattern lines147aand147b, contact electrodes141and143and a passivation (or protective) film139on a substrate131.

More specifically, gate lines121(not shown), gate electrodes (not shown), and gate pattern lines107are provided by forming a gate metal film (not shown) made of gate metal material on the substrate131and patterning the gate metal film. The gate lines121are formed on the display area125. A plurality of pixels is defined on the display area125. The gate lines121are formed extending onto the non-display area129as well as on the display area125. The gate electrodes are formed on the respective pixels, and the gate pattern lines107are formed between the gate-driving integrated circuits105as well as between the gate-driving integrated circuits105and the FPC board103.

The gate insulation film133is formed of a gate insulation material on an overall area of the substrate131which includes the gate lines121.

Semiconductor layer patterns (not shown) are provided by forming and patterning a semiconductor material on the gate insulation film133. Also, data lines123, source/drain electrodes (not shown), and data pattern lines147aand147bare provided by forming and patterning a data metal film (not shown) made of data metal material on the substrate131including the semiconductor layer patterns. The data lines123are formed crossing the gate lines121. The pixels are defined by the data lines123and the gate lines121crossing each other on the display area125. The data lines123may be formed extending onto the non-display area129as well as on the display area125. The source/drain electrodes are formed separately from each other at fixed intervals on the gate insulation film133opposite to the gate electrode. The data pattern lines147aand147bare formed between the data-driving integrated circuits116aand116b,117aand117b,118aand118b, and119aand119b, and between the data-driving integrated circuits116a,117a,118a,119aand the FPC board103. The data metal material is identical to or is different from the gate metal material.

The gate electrode, the gate insulation film133, the semiconductor layer pattern, and the source/drain electrodes may configure a thin film transistor. The thin film transistor is connected to the gate line121and the data line123defining the pixel.

The passivation (or protective) film139is formed of an organic or inorganic material on the substrate131which includes the data pattern lines147aand147b. Sequentially, the passivation film139is patterned, thereby forming drain contact holes (not shown) partially exposing the drain electrodes, data contact holes (not shown) exposing one ends of the data lines123extended to the non-display area129, and data pattern line contact holes149partially exposing the data pattern lines147aand147b. In addition, the passivation film139and the gate insulation film133are patterned, thereby forming gate contact holes (not shown) exposing one ends of the gate lines121extended to the non-display area129, and gate pattern line contact holes (not shown) partially exposing the gate pattern lines107.

Pixel electrodes (not shown), gate contact electrodes (not shown), and data contact electrodes141and143are provided by forming and patterning a transparent conductive material film, such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO), on the passivation film139. The pixel electrode is formed on the respective pixel and is electrically connected to the respective drain electrode through the respective drain contact hole. The gate contact electrodes are formed to be electrically connected with the gate line121through the gate contact holes. The gate contact electrodes are formed to be electrically connected with the gate pattern lines107through the gate pattern line contact holes. The data contact electrodes141and143are formed to be electrically connected with the data lines123through the data contact holes. The data contact electrodes141and143are formed to be electrically connected with the data pattern lines147aand147bthrough the data pattern line contact holes.

As shown inFIG. 7B, ACFs150are arranged on the non-display area129of the first substrate111. Each of the ACFs150includes a plurality of conductive balls152randomly distributed in a region in which the gate-driving integrated circuits105and the data-driving integrated circuits116a,116b,117a,117b,118a,118b,119a, and119bare disposed. In other words, the ACFs150can be positioned under bumps of the gate- and data-driving integrated circuits105,116a,116b,117a,117b,118a,118b,119a, and119b. More specifically, the ACFs150may be disposed on one ends of the gate lines121, one ends of the data lines123, both ends of the gate pattern lines107, and both ends of the respective data pattern lines147aand147.

The gate-driving integrated circuits105and the data-driving integrated circuits116a,116b,117a,117b,118a,118b,119a, and119bare disposed to allow their bumps156to be opposite each of the ACFs150.

Sequentially, as shown inFIG. 7C, the gate-driving integrated circuits105and the data-driving integrated circuits116a,116b,117a,117b,118a,118b,119a, and119bare depressed by pressure upon heat, so that the bumps of the gate-driving integrated circuits105and the bumps156of the data-driving integrated circuits116a,116b,117a,117b,118a,118b,119a, and119ballow the conductive balls152to be connected to the gate lines121, the gate pattern lines107, the data lines123, and the data pattern lines147aand147b.

More specifically, when the gate-driving integrated circuits105and the data-driving integrated circuits116a,116b,117a,117b,118a,118b,119a, and119bare depressed, the bumps in the gate-driving integrated circuits105and the bumps156in the data-driving integrated circuits116a,116b,117a,117b,118a,118b,119a, and119bdepress and melt the respective ACFs150. Accordingly, the bumps in the gate-driving integrated circuits105and the bumps156in the data-driving integrated circuits116a,116b,117a,117b,118a,118b,119a, and119bcan be electrically connected to the gate contact electrodes and the data contact electrodes141and143. Specially, the conductive balls152contained in each of the ACFs150can electrically be connected to the gate contact electrodes and the data contact electrodes141and143.

Although all of the gate-driving integrated circuits105and the data-driving integrated circuits116a,116b,117a,117b,118a,118b,119a, and119bare simultaneously mounted on the first substrate111, the method of the present embodiment is not limited to this. In other words, the gate-driving integrated circuits105and the data-driving integrated circuits116a,116b,117a,117b,118a,118b,119a, and119bcan be sequentially mounted on the first substrate111.

However, as shown inFIG. 7D, the ACFs150are hardened as the time passes by, and adhesions between the conductive balls152and ACFs150and the gate contact electrodes and data contact electrodes141and143and between the gate contact electrodes and data contact electrodes141and143and the gate lines121, the gate pattern lines107, the data lines123and the data pattern lines147aand147are so bad. Thus, the conductive balls152and ACFs150are detached from the gate contact electrodes and data contact electrodes141and143. In addition, the gate contact electrodes and data contact electrodes141and143may be detached from the gate lines121, the gate pattern lines107, the data lines123and the data pattern lines147aand147. Contact defects are generated in contact areas of the input terminal portions, the output terminal portions, and the signal output terminal portions of the gate- and data-driving integrated circuits25,26or27. Due to these contact defects, a contact resistance within the contact region increases and thus a defect involving a block dim or a block noise is generated.

To resolve these problems, as shown inFIG. 7E, laser light (or laser beams) are irradiated from below the substrate131onto the inner contact region of the substrate131and thus two layers which are formed within the contact region, namely the gate lines121and the gate contact electrodes, the gate pattern lines107and the gate contact electrodes, the data lines123and the data contact electrodes141and143, and the data pattern lines147aand147band the data contact electrodes141and143are molten such that contact layers158are formed within each contact region. At the same time, a plurality of peaks158aare formed on an upper surface of each contact layer158by laser light. The peaks158acontact each conductive ball152. The contact layer158is formed by melting two layers which are formed within the contact region, namely the gate lines121and the gate contact electrodes, the gate pattern lines107and the gate contact electrodes, the data lines123and the data contact electrodes141and143, and the data pattern lines147aand147band the data contact electrodes141and143.

As shown inFIG. 7F, after the irradiation of laser light is over, as the time passes by, the peaks158acontacted with each conductive ball152flow down along a surface of each conductive ball152to join each other together. In addition, the joined peaks158band the contact layers158are hardened. Thus, the conductive balls152is firmly attached and connected to the contact layer158, in detail the joined peaks158within the contact region.

For the laser, any one of a ruby laser, a neodymium-doped yttrium aluminum garnet (Nd:YAG) laser, a KCl laser, a RbCl laser, and so on can be employed. It is preferable, however, to use a solid laser including Nd:YAG. The method of the present embodiment can use a pulse laser emitting pulsed laser light which has a power range of about 60 to 120 mJ.

In this way, since the conductive balls152within the contact regions are able to contact with the contact layers158, the contact resistance is greatly reduced. Accordingly, desired power signals can be accurately transferred between the gate-driving integrated circuits105and the gate lines121or the gate pattern lines107, and between the data-driving integrated circuits116a,116b,117a,117b,118a,118b,119a, and119band the data lines123or the data pattern lines147aand147b, without variation.

More specifically, since the power signals VDD, VDD_gnd, VCC, and VCC_gnd, the gamma voltages, the data signal, and the control signal sensitive to the contact resistance between the data-driving integrated circuits116a,116b,117a,117b,118a,118b,119a, and119band the data pattern lines147aand147bhave no variation, none of a block dim and block noise is generated.

FIGS. 8A to 8Eare cross-sectional views showing a method of manufacturing an LCD device according to a second embodiment of the present disclosure.

As shown inFIG. 8A, a first substrate111shown inFIG. 6is manufactured by forming data pattern lines147aand147b, a gate insulation film133, a passivation (or protective) film139, and contact electrodes141and143on a substrate131.

More specifically, gate lines121, gate electrodes (not shown), gate pattern lines107, and data pattern lines147aand147bare provided by forming a gate metal film (not shown) made of gate metal material on the substrate131and patterning the gate metal film. The gate lines121are formed on the display area125. A plurality of pixels is defined on the display area125. The gate lines121are formed extending onto the non-display area129as well as on the display area125. The gate electrodes are formed on the respective pixels, the gate pattern lines107are formed between the gate-driving integrated circuits105and between the gate-driving integrated circuits105and the FPC board103, and the data pattern lines147aand147bare formed between the data-driving integrated circuits116aand116b,117aand117b,118aand118b, and119aand119b, and between the data-driving integrated circuits116a,117a,118a,119aand the FPC board103.

The gate insulation film133is formed of a gate insulation material on an overall area of the substrate131which includes the data pattern lines147aand147b.

Semiconductor layer patterns (not shown) are provided by forming and patterning a semiconductor material on the gate insulation film133. Also, data lines123and source/drain electrodes (not shown) are provided by forming and patterning a data metal film (not shown) made of data metal material on the substrate131including the semiconductor layer patterns. The source/drain electrodes are formed separately from each other at fixed intervals on the gate insulation film133opposite to the gate electrode. The data metal material is identical to or is different from the gate metal material. The data lines123are formed crossing the gate lines121. The pixels are defined by the data lines123and the gate lines121crossing each other on the display area125. The data lines123may be formed extending onto the non-display area129as well as on the display area125.

The gate electrode, the gate insulation film133, the semiconductor layer pattern, and the source/drain electrodes may configure a thin film transistor. The thin film transistor is connected to the gate line121and the data line123defining the pixel.

The passivation (or protective) film139is formed of an organic or inorganic material on the substrate131which includes the data lines123. Sequentially, the passivation film139is patterned, thereby forming drain contact holes (not shown) partially exposing the drain electrodes, and data contact holes (not shown) exposing one ends of the data lines123extended to the non-display area129. In addition, the passivation film139and the gate insulation film133are patterned, thereby forming gate contact holes (not shown) exposing one ends of the gate lines121extended to the non-display area129, gate pattern line contact holes (not shown) partially exposing the gate pattern lines107, and data pattern line contact holes161partially exposing the data pattern lines147aand147b.

Pixel electrodes (not shown), gate contact electrodes (not shown), and data contact electrodes141and143are provided by forming and patterning a transparent conductive material film, such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO), on the passivation film139. The pixel electrode is formed on the respective pixel and is electrically connected to the respective drain electrode through the respective drain contact hole. The gate contact electrodes are formed to be electrically connected with the gate line121through the gate contact holes. The gate contact electrodes are formed to be electrically connected with the gate pattern lines107through the gate pattern line contact holes. The data contact electrodes141and143are formed to be electrically connected with the data lines123through the data contact holes. The data contact electrodes141and143are formed to be electrically connected with the data pattern lines147aand147bthrough the data pattern line contact holes161.

FIGS. 8B to 8Eare approximately similar toFIGS. 7B to 7Fexcept the data pattern lines147aand147b.

As shown inFIG. 8B, ACFs150are arranged on the non-display area129of the first substrate111. Each of the ACFs150includes a plurality of conductive balls152randomly distributed in a region in which the gate-driving integrated circuits105and the data-driving integrated circuits116a,116b,117a,117b,118a,118b,119a, and119bare disposed. In other words, the ACFs150can be positioned under bumps of the gate- and data-driving integrated circuits107,116a,116b,117a,117b,118a,118b,119a, and119b. More specifically, the ACFs150may be disposed on one ends of the gate lines121, one ends of the data lines123, both ends of the gate pattern lines107, and both ends of the respective data pattern lines147aand147b.

The gate-driving integrated circuits105and the data-driving integrated circuits116a,116b,117a,117b,118a,118b,119a, and119bare disposed to allow their bumps156to be opposite each of the ACFs150.

Sequentially, the gate-driving integrated circuits105and the data-driving integrated circuits116a,116b,117a,117b,118a,118b,119a, and119bare depressed by pressure upon heat, so that the bumps of the gate-driving integrated circuits105and the bumps156of the data-driving integrated circuits116a,116b,117a,117b,118a,118b,119a, and119bare connected to the gate lines121, the gate pattern lines107, the data lines123, and the data pattern lines147aand147b.

More specifically, when the gate-driving integrated circuits105and the data-driving integrated circuits116a,116b,117a,117b,118a,118b,119a, and119bare depressed, the bumps in the gate-driving integrated circuits105and the bumps156in the data-driving integrated circuits116a,116b,117a,117b,118a,118b,119a, and119bdepress and melt the respective ACFs150. Accordingly, the bumps in the gate-driving integrated circuits105and the bumps156in the data-driving integrated circuits116a,116b,117a,117b,118a,118b,119a, and119ballow the conductive balls152to be electrically connected to the gate contact electrodes and the data contact electrodes141and143.

Although all of the gate-driving integrated circuits105and the data-driving integrated circuits116a,116b,117a,117b,118a,118b,119a, and119bare simultaneously mounted on the first substrate111, the method of the present embodiment is not limited to this. In other words, the gate-driving integrated circuits105and the data-driving integrated circuits116a,116b,117a,117b,118a,118b,119a, and119bcan be sequentially mounted on the first substrate111.

However, as shown inFIG. 8C, the ACFs150are hardened as the time passes by, and adhesions between the conductive balls152and ACFs150and the gate contact electrodes and data contact electrodes141and143and between the gate contact electrodes and data contact electrodes141and143and the gate lines121, the gate pattern lines107, the data lines123and the data pattern lines147aand147are so bad. Thus, the contact balls152and ACFs150are detached from the gate contact electrodes and data contact electrodes141and143. In addition, the gate contact electrodes and data contact electrodes141and143may be detached from the gate lines121, the gate pattern lines107, the data lines123and the data pattern lines147aand147. Contact defects are generated in contact areas of the input terminal portions, the output terminal portions, and the signal output terminal portions of the gate- and data-driving integrated circuits25,26or27. Due to these contact defects, a contact resistance within the contact region increases and thus a defect involving a block dim or a block noise is generated.

To resolve these problems, as shown inFIG. 8D, laser light (or laser beams) are irradiated from below the substrate131onto the inner contact region of the substrate131and thus two layers which are formed within the contact region, namely the gate lines121and the gate contact electrodes, the gate pattern lines107and the gate contact electrodes, the data lines123and the data contact electrodes141and143, and the data pattern lines147aand147band the data contact electrodes141and143are molten such that contact layers158are formed within each contact region. At the same time, a plurality of peaks158aare formed on an upper surface of each contact layer158by laser light. The peaks158acontact each conductive ball152. The contact layer158is formed by melting two layers which are formed within the contact region, namely the gate lines121and the gate contact electrodes, the gate pattern lines107and the gate contact electrodes, the data lines123and the data contact electrodes141and143, and the data pattern lines147aand147band the data contact electrodes141and143.

As shown inFIG. 8E, after the irradiation of laser light is over, as the time passes by, the peaks158acontacted with each conductive ball152flow down along a surface of each conductive ball152to join each other together. In addition, the joined peaks158band the contact layers158are hardened. Thus, the conductive balls152is firmly attached and connected to the contact layer158, in detail the joined peaks158within the contact region.

As described above, the present disclosure irradiate laser light on the contact regions and melt the data pattern lines and the data contact electrodes, forming the contact layers including the data pattern lines and the data contact electrodes. As such, the conductive balls causing the contact defect are forcibly connected to the contact layers, preventing a defect involving a block dim or a noise. In addition, the data pattern lines and the data contact electrodes are molten by laser light to mix the data pattern lines and the data contact electrodes. Thus, there is no adhesion problem between the gate lines and the gate contact electrodes, between the gate pattern lines and the gate contact electrodes, between the data lines and the data contact electrodes, and between the data pattern lines and the data contact electrodes. As a result, as contact defects are not generated picture-quality can be improved.

Although the embodiments of the present disclosure have been limitedly explained referring only to the LCD device described above, it should be understood that the present disclosure is not limited to these embodiments, but rather that various changes or modifications thereof are possible without departing from the spirit of the present disclosure. For example, the embodiments of the present disclosure can be applied to organic electro-luminescence display devices. Accordingly, the scope of the present disclosure shall be determined only by the appended claims and their equivalents.