Memory system and operating method thereof

Embodiments of the present disclosure relate to a memory system and a method for operating the memory system. According to embodiments of the present disclosure, a memory system may determine a target write data which is to be written to one of a plurality of super memory blocks, and may write the target write data based on a size of the target write data, to a first super memory block which includes at least one bad word line or a second super memory block which includes no bad word line.

CROSS-REFERENCES TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. 119(a) to Korean patent application number 10-2021-0072086 filed on Jun. 3, 2021, which is incorporated herein by reference in its entirety.

BACKGROUND

1. Technical Field

The embodiments of the present disclosure relate to a memory system and an operating method thereof.

2. Related Art

A memory system includes a data storage device that stores data on the basis of a request from a host, such as a computer, servers, a smartphone, a tablet PC, or other electronic devices. Examples of the memory system span from a traditional magnetic-disk-based hard disk drive (HDD) to a semiconductor-based data storage device such as a solid state drive (SSD), a universal flash storage device (UFS), or an embedded MMC (eMMC) device.

The memory system may further include a memory controller for controlling a memory device. The memory controller may receive a command from the host and, on the basis of the received command, may execute the command or control read/write/erase operations on the memory devices in the memory system. The memory controller may be used to execute firmware operations for performing a logical operation for controlling such operations.

The memory device included in the memory system may include a plurality of memory blocks. In this case, as the storage capacity of a memory block increases, the number of word lines included in the memory block increases.

SUMMARY

Embodiments of the present disclosure are directed to a memory system and an operating method that are capable of using super memory block containing a bad word line more efficiently.

Embodiments of the present disclosure are directed to a memory system and an operating method that are capable of minimizing write performance degradation by a bad word line.

In one aspect, embodiments of the present disclosure may provide a memory system including a memory device including a plurality of memory blocks and a memory controller for communicating with the memory device and controlling the memory device.

The memory controller may determine a target write data which is to be written to one of a plurality of super memory blocks, wherein each super memory block includes one or more of the plurality of memory blocks.

The memory controller may write the target data, based on a size of the target write data, to a first super memory block which includes at least one bad word line or a second super memory block which includes no bad word line.

The memory controller may write the target write data to the first super memory block when a size of the target write data is equal to or less than a set threshold size, and write the target data to the second super memory block when the size of the target write data is greater than the set threshold size.

In another aspect, embodiments of the present disclosure may provide a method for operating a memory system including a memory device including a plurality of memory blocks.

The method for operating a memory system may include setting a plurality of super memory blocks each including one or more of the plurality of memory blocks.

The method for operating a memory system may include determining a target write data which is to be written to one of the plurality of super memory blocks.

The method for operating a memory system may include writing the target write data based on a size of the target write data, to a first super memory block which includes at least one bad word line or a second super memory block which includes no bad word line.

Writing the target write data based on size of the target write data, to the first super memory block or the second super memory block may include writing the target write data to the first super memory block when a size of the target write data is equal to or less than a set threshold size and writing the target data to the second super memory block when the size of the target write data is greater than the set threshold size.

Embodiments of the present disclosure may provide an advantage of using super memory blocks containing a bad word line more efficiently and minimizing write performance degradation by the bad word line.

DETAIL DESCRIPTION

Hereinafter, embodiments of the present disclosure are described in detail with reference to the accompanying drawings. Throughout the specification, reference to “an embodiment,” “another embodiment” or the like is not necessarily to only one embodiment, and different references to any such phrase are not necessarily to the same embodiment(s). The term “embodiments” when used herein does not necessarily refer to all embodiments.

Various embodiments of the present invention are described below in more detail with reference to the accompanying drawings. However, the present invention may be embodied in different forms and variations, and should not be construed as being limited to the embodiments set forth herein. Rather, the described embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the present invention to those skilled in the art to which this invention pertains. Throughout the disclosure, like reference numerals refer to like parts throughout the various figures and embodiments of the present invention.

When implemented at least partially in software, the controllers, processors, devices, modules, units, multiplexers, generators, logic, interfaces, decoders, drivers, generators and other signal generating and signal processing features may include, for example, a memory or other storage device for storing code or instructions to be executed, for example, by a computer, processor, microprocessor, controller, or other signal processing device.

FIG.1is a diagram illustrating the schematic configuration of a memory system100based on an embodiment of the disclosed technology.

In some implementations, the memory system100may include a memory device110configured to store data, and a memory controller120configured to control the memory device110.

The memory device110may include multiple memory blocks each including a plurality of memory cells for storing data. The memory device110may be configured to operate in response to control signals received from the memory controller120. Operations of the memory device110may include, for example, a read operation, a program operation (also referred to as a “write operation”), an erasure operation, and the like.

The memory cells in the memory device110are used to store data and may be arranged in a memory cell array. The memory cell array may be divided into memory blocks of memory cells and each block includes different pages of memory cells. In typical implementations of NAND flash memory devices, a page of memory cells is the smallest memory unit that can be programmed or written, and the data stored in memory cells can be erased at the block level.

The memory device110may be implemented in a three-dimensional array structure. Some embodiments of the disclosed technology are applicable to any type of flash memory devices having an electric charge storage layer. In an implementation, the electric charge storage layer may be formed of a conductive material, and such an electric charge storage layer can be called a floating gate. In another implementation, the electric charge storage layer may be formed of an insulating material, and such a flash memory device can be called a charge trap flash (CTF).

The memory device110may be configured to receive a command and an address from the memory controller120to access an area of the memory cell array selected using the address. That is, the memory device110may perform an operation corresponding to the received command on a memory area of the memory device having a physical address corresponding to the received address from the memory controller120.

In some implementations, the memory device110may perform a program operation, a read operation, an erasure operation, and the like. During the program operation, the memory device110may write data in the area selected by the address. During the read operation, the memory device110may read data from a memory area selected by the address. During the erasure operation, the memory device110may erase data stored in a memory area selected by the address.

The memory controller120may control write (program), read, erasure, and background operations that are performed on the memory device110. The background operation may include, for example, operations that are implemented to optimize the overall performance of the memory device110, such as a garbage collection (GC) operation, a wear leveling (WL) operation, and a bad block management (BBM) operation.

The memory controller120may control the operation of the memory device110at the request of a host. Alternatively, the memory controller120may control the operation of the memory device110even in absence of request from the host when it performs such background operations of the memory device.

The memory controller120and the host may be separate devices. In some implementations, the memory controller120and the host may be integrated and implemented as a single device. In the following description, the memory controller120and the host will be discussed as separate devices as an example.

Referring toFIG.1, the memory controller120may include a memory interface122, a control circuit123, and a host interface121.

The host interface121may be configured to provide an interface for communication with the host.

When receiving a command from the host HOST, the control circuit123may receive the command through the host interface121and may perform an operation of processing the received command.

The memory interface122may be directly or indirectly connected to the memory device110to provide an interface for communication with the memory device110. That is, the memory interface122may be configured to provide the memory device110and the memory controller120with an interface for the memory controller120to perform memory operations on the memory device110based on control signals and instructions from the control circuit123.

The control circuit123may be configured to control the operation of the memory device110through the memory controller120. For example, the control circuit123may include a processor124and a working memory125. The control circuit123may further include an error detection/correction circuit (ECC circuit)126and the like.

The processor124may control the overall operation of the memory controller120. The processor124may perform a logical operation. The processor124may communicate with the host HOST through the host interface121. The processor124may communicate with the memory device110through the memory interface122.

The processor124may be used to perform operations associated with a flash translation layer (FTL) to effectively manage the memory operations on the memory system100. The processor124may translate a logical block address (LBA) provided by the host into a physical block address (PBA) through the FTL. The FTL may receive the LBA and translate the LBA into the PBA by using a mapping table.

There are various address mapping methods which may be employed by the FTL, based on the mapping unit. Typical address mapping methods may include a page mapping method, a block mapping method, and a hybrid mapping method.

The processor124may be configured to randomize data received from the host to write the randomized data to the memory cell array. For example, the processor124may randomize data received from the host by using a randomizing seed. The randomized data is provided to the memory device110and written to the memory cell array.

The processor124may be configured to derandomize data received from the memory device110during a read operation. For example, the processor124may derandomize data received from the memory device110by using a derandomizing seed. The derandomized data may be output to the host HOST.

The processor124may execute firmware (FW) to control the operation of the memory controller120. The processor124may control the overall operation of the memory controller120and, in order to perform a logical operation, may execute (drive) firmware loaded into the working memory125during booting.

The firmware refers to a program or software stored on a certain nonvolatile memory and is executed inside the memory system100.

In some implementations, the firmware may include various functional layers. For example, the firmware may include at least one of a flash translation layer (FTL) configured to translate a logical address in the host HOST requests to a physical address of the memory device110, a host interface layer (HIL) configured to interpret a command that the host HOST issues to a data storage device such as the memory system100and to deliver the command to the FTL, and a flash interface layer (FIL) configured to deliver a command issued by the FTL to the memory device110.

For example, the firmware may be stored in the memory device110, and then loaded into the working memory125.

The working memory125may store firmware, program codes, commands, or pieces of data necessary to operate the memory controller120. The working memory125may include, for example, at least one among a static RAM (SRAM), a dynamic RAM (DRAM), and a synchronous RAM (SDRAM) as a volatile memory.

The error detection/correction circuit126may be configured to detect and correct one or more erroneous bits in the data by using an error detection and correction code. In some implementations, the data that is subject to the error detection and correction may include data stored in the working memory125, and data retrieved from the memory device110.

The error detection/correction circuit126may be implemented to decode data by using the error correction code. The error detection/correction circuit126may be implemented by using various decoding schemes. For example, a decoder that performs nonsystematic code decoding or a decoder that performs systematic code decoding may be used.

In some implementations, the error detection/correction circuit126may detect one or more erroneous bits on a sector basis. That is, each piece of read data may include multiple sectors. In the present disclosure, a sector may refer to a data unit that is smaller than the read unit (e.g., page) of a flash memory. Sectors constituting each piece of read data may be mapped based on addresses.

In some implementations, the error detection/correction circuit126may calculate a bit error rate (BER) and determine whether the number of erroneous bits in the data is within the error correction capability sector by sector. For example, if the BER is higher than a reference value, the error detection/correction circuit126may determine that the erroneous bits in the corresponding sector are uncorrectable and the corresponding sector is marked “fail.” If the BER is lower than or equals to the reference value, the error detection/correction circuit126may determine that the corresponding sector is correctable or the corresponding sector can be marked “pass.”

The error detection/correction circuit126may perform error detection and correction operations successively on all read data. When a sector included in the read data is correctable, the error detection/correction circuit126may move on to the next sector to check whether an error correction operation is needed on the next sector. Upon completion of the error detection and correction operations on all the read data in this manner, the error detection/correction circuit126may acquire information as to which sector is deemed uncorrectable in the read data. The error detection/correction circuit126may provide such information (e.g., address of uncorrectable bits) to the processor124.

The memory system100may also include a bus127to provide a channel between the constituent elements121,122,124,125, and126of the memory controller120. The bus127may include, for example, a control bus for delivering various types of control signals and commands, and a data bus for delivering various types of data.

By way of example,FIG.1illustrates the above-mentioned constituent elements121,122,124,125, and126of the memory controller120. It is noted that some of the elements illustrated in the drawings may be omitted, or some of the above-mentioned constituent elements121,122,124,125, and126of the memory controller120may be integrated into a single element. In addition, in some implementations, one or more other constituent elements may be added to the above-mentioned constituent elements of the memory controller120.

FIG.2is a block diagram a schematically illustrating a memory device110based on an embodiment of the disclosed technology.

In some implementations, the memory device110based on an embodiment of the disclosed technology may include a memory cell array210, an address decoder220, a read/write circuit230, a control logic240, and a voltage generation circuit250.

The memory cell array210may include multiple memory blocks BLK1-BLKz, where z is a natural number equal to or larger than 2.

In the multiple memory blocks BLK1-BLKz, multiple word lines WL and multiple bit lines BL may be disposed in rows and columns, and multiple memory cells MC may be arranged.

The multiple memory blocks BLK1-BLKz may be connected to the address decoder220through the multiple word lines WL. The multiple memory blocks BLK1-BLKz may be connected to the read/write circuit230through the multiple bit lines BL.

Each of the multiple memory blocks BLK1-BLKz may include multiple memory cells. For example, the multiple memory cells are nonvolatile memory cells. In some implementations, such nonvolatile memory cells may be arranged in a vertical channel structure.

The memory cell array210may be configured as a memory cell array having a two-dimensional structure. In some implementations, the memory cell array210may be arranged in a three-dimensional structure.

Each of the multiple memory cells included in the memory cell array210may store at least one bit of data. For example, each of the multiple memory cells included in the memory cell array210may be a single-level cell (SLC) configured to store one bit of data. As another example, each of the multiple memory cells included in the memory cell array210may be a multi-level cell (MLC) configured to store two bits of data per memory cell. As another example, each of the multiple memory cells included in the memory cell array210may be a triple-level cell (TLC) configured to store three bits of data per memory cell. As another example, each of the multiple memory cells included in the memory cell array210may be a quad-level cell (QLC) configured to store four bits of data per memory cell. As another example, the memory cell array210may include multiple memory cells, each of which may be configured to store at least five bits of data per memory cell.

Referring toFIG.2, the address decoder220, the read/write circuit230, the control logic240, and the voltage generation circuit250may operate as peripheral circuits configured to drive the memory cell array210.

The address decoder220may be connected to the memory cell array210through the multiple word lines WL.

The address decoder220may be configured to operate in response to command and control signals of the control logic240.

The address decoder220may receive addresses through an input/output buffer inside the memory device110. The address decoder220may be configured to decode a block address among the received addresses. The address decoder220may select at least one memory block based on the decoded block address.

The address decoder220may receive a read voltage Vread and a pass voltage Vpass from the voltage generation circuit250.

The address decoder220may, during a read operation, apply the read voltage Vread to a selected word line WL inside a selected memory block and apply the pass voltage Vpass to the remaining non-selected word lines WL.

The address decoder220may apply a verification voltage generated by the voltage generation circuit250to a selected word line WL inside a selected memory block, during a program verification operation, and may apply the pass voltage Vpass to the remaining non-selected word lines WL.

The address decoder220may be configured to decode a column address among the received addresses. The address decoder220may transmit the decoded column address to the read/write circuit230.

The memory device110may perform the read operation and the program operation page by page. Addresses received when the read operation and the program operation are requested may include at least one of a block address, a row address, and a column address.

The address decoder220may select one memory block and one word line based on the block address and the row address. The column address may be decoded by the address decoder220and provided to the read/write circuit230.

The address decoder220may include at least one of a block decoder, a row decoder, a column decoder, and an address buffer.

The read/write circuit230may include multiple page buffers PB. The read/write circuit230may operate as a “read circuit” when the memory cell array210performs a read operation, and may operate as a “write circuit” when the memory cell array210performs a write operation.

The above-mentioned read/write circuit230is also referred to as a page buffer circuit including multiple page buffers PB, or a data register circuit. The read/write circuit230may include a data buffer that participates in a data processing function and, in some implementations, may further include a cache buffer for data caching.

The multiple page buffers PB may be connected to the memory cell array210through the multiple bit lines BL. In order to detect or sense the threshold voltage Vth of the memory cells during a read operation and a program verification operation, the multiple page buffers PB may continuously supply a sensing current to the bit lines BL connected to the memory cells to detect, at a sensing node, a change proportional to the amount of current that varies depending on the program state of a corresponding memory cell, and may hold or latch the corresponding voltage as sensing data.

The read/write circuit230may operate in response to page buffer control signals output from the control logic240.

During a read operation, the read/write circuit230senses a voltage value of a memory cell and the voltage value is read out as data. The read/write circuit230temporarily stores the retrieved data, and outputs the data DATA to the input/output buffer of the memory device110. In an embodiment, the read/write circuit230may include a column selection circuit, in addition to the page buffers PB or page registers.

The control logic240may be connected to the address decoder220, the read/write circuit230, and the voltage generation circuit250. The control logic240may receive a command CMD and a control signal CTRL through the input/output buffer of the memory device110.

The control logic240may be configured to control the overall operation of the memory device110in response to the control signal CTRL. The control logic240may output a control signal for adjusting the voltage level of sensing nodes of multiple page buffers PB to a pre-charge voltage level.

The control logic240may control the read/write circuit230to perform a read operation in the memory cell array210. The voltage generation circuit250may generate a read voltage tread and a pass voltage Vpass, which are used during the read operation, in response to a voltage generation circuit control signal output from the control logic240.

A memory block BLK included in the memory device110may include multiple pages PG. In some implementations, a plurality of memory cells arranged in columns form memory cell strings, and a plurality of memory cells arranged in rows form memory blocks. Each of the multiple pages PG is coupled to one of word lanes WL, and each of the memory cell strings STR is coupled to one of bit lines BL.

In the memory block BLK, multiple word lines WL and multiple bit lines BL may be arranged in rows and columns. For example, each of the multiple word lines WL may be arranged in the row direction, and each of the multiple bit lines BL may be arranged in the column direction. As another example, each of the multiple word lines WL may be arranged in the column direction, and each of the multiple bit lines BL may be arranged in the row direction.

In some implementations, the multiple word lines WL and the multiple bit lines BL may intersect with each other, thereby addressing a single memory cell in the array of multiple memory cells MC. In some implementations, each memory cell MC may include a transistor TR that includes a material layer that can hold an electrical charge.

For example, the transistor TR arranged in each memory cell MC may include a drain, a source, and a gate. The drain (or source) of the transistor TR may be connected to the corresponding bit line BL directly or via another transistor TR. The source (or drain) of the transistor TR may be connected to the source line (which may be the ground) directly or via another transistor TR. The gate of the transistor TR may include a floating gate (FG) surrounded by an insulator, and a control gate (CG) to which a gate voltage is applied from a word line WL.

In each of the multiple memory blocks BLK1-BLKz, a first selection line (also referred to as a source selection line or a drain selection line) may be additionally arranged outside the first outermost word line, which is closer to the read/write circuit230among two outermost word lines, and a second selection line (also referred to as a drain selection line or a source selection line) may be additionally arranged outside the other second outermost word line.

In some implementations, at least one dummy word line may be additionally arranged between the first outermost word line and the first selection line. In addition, at least one dummy word line may be additionally arranged between the second outermost word line and the second selection line.

A read operation and a program operation (write operation) of the memory block may be performed page by page, and an erasure operation may be performed memory block by memory block.

FIG.3is a diagram illustrating a structure of word lines WL and bit lines BL of a memory device110based on an embodiment of the disclosed technology.

Referring toFIG.3, the memory device110has a core area in which memory cells MC are arranged, and an auxiliary area (the remaining area other than the core area) to include circuitry that is used to perform the operations of the memory cell array210.

In the core area, a certain number of memory cells arranged in one direction can be called “page” PG, and a certain number of memory cells that are coupled in series can be called “memory cell string” STR.

The word lines WL1-WL9may be connected to a row decoder310. The bit lines BL may be connected to a column decoder320. A data register330, which corresponds to the read/write circuit230ofFIG.2, may exist between the multiple bit lines BL and the column decoder320.

The multiple word lines WL1-WL9may correspond to multiple pages PG.

For example, each of the multiple word lines WL1-WL9may correspond to one page PG as illustrated inFIG.3. When each of the multiple word lines WL1-WL9has a large size, each of the multiple word lines WL1-WL9may correspond to at least two (e.g., two or four) pages PG. Each page PG is the smallest unit in a program operation and a read operation, and all memory cells MC within the same page PG may perform simultaneous operations when conducting a program operation and a read operation.

The multiple bit lines BL may be connected to the column decoder320. In some implementations, the multiple bit lines BL may be divided into odd-numbered bit lines BL and even-numbered bit lines BL such that a pair of odd-numbered bit line and even-numbered bit line is coupled in common to a column decoder320.

In accessing a memory cell MC, the row decoder310and the column decoder320are used to locate a desired memory cell based on the address.

In some implementations, the data register330plays an important role because all data processing by the memory device110, including program and read operations, occurs via the data register330. If data processing by the data register330is delayed, all of the other areas need to wait until the data register330finishes the data processing, degrading the overall performance of the memory device110.

Referring to the example illustrated inFIG.3, in one memory cell string STR, multiple transistors TR1-TR9may be connected to multiple word lines WL1-WL9, respectively. In some implementations, the multiple transistors TR1-TR9correspond to memory cells MC. In this example, the multiple transistors TR1-TR9include control gates CG and floating gates FG.

The multiple word lines WL1-WL9include two outermost word lines WL1and WL9. A first selection line DSL may be additionally arranged outside the first outermost word line WL1, which is closer to the data register330and has a shorter signal path compared to the other outermost word line WL9. A second selection line SSL may be additionally arranged outside the other second outermost word line WL9.

The first selection transistor D-TR, which is controlled to turn on/off by the first selection line DSL, has a gate electrode connected to the first selection line DSL, but includes no floating gate FG. The second selection transistor S-TR, which is controlled to turn on/off by the second selection line SSL, has a gate electrode connected to the second selection line SSL, but includes no floating gate FG.

The first selection transistor D-TR is used as a switch circuit that connects the corresponding memory cell string STR to the data register330. The second selection transistor S-TR is used as a switch that connects the corresponding memory cell string STR to the source line SL. That is, the first selection transistor D-TR and the second selection transistor S-TR can be used to enable or disable the corresponding memory cell string STR.

In some implementations, the memory system100applies a predetermined turn-on voltage Vcc to the gate electrode of the first selection transistor D-TR, thereby turning on the first selection transistor D-TR, and applies a predetermined turn-off voltage (e.g., 0V) to the gate electrode of the second selection transistor S-TR, thereby turning off the second selection transistor S-TR.

The memory system100turns on both of the first and second selection transistors D-TR and S-TR during a read operation or a verification operation. Accordingly, during a read operation or a verification operation, an electric current may flow through the corresponding memory cell string STR and drain to the source line SL, which corresponds to the ground, such that the voltage level of the bit line BL can be measured. However, during a read operation, there may be a time difference in the on/off timing between the first selection transistor D-TR and the second selection transistor S-TR.

The memory system100may apply a predetermined voltage (e.g., +20V) to the substrate through a source line SL during an erasure operation. The memory system100applies a certain voltage to allow both the first selection transistor D-TR and the second selection transistor S-TR to float during an erasure operation. As a result, the applied erasure voltage can remove electrical charges from the floating gates FG of the selected memory cells.

FIG.4is a schematic diagram illustrating an operation of a memory system according to embodiments of the present disclosure.

Referring toFIG.4, a memory controller120in memory system100may determine a target write data TGT_WR_DATA, which is to be written to one of a plurality of super memory blocks SBLK included in a memory device110.

The memory controller120may group a plurality of memory blocks BLK included in a memory device110into the plurality of super memory blocks SBLK.

Each of the super memory blocks SBLK may include one or more of the plurality of memory blocks BLK included in the memory device110.

At this time, one or more of the plurality of memory blocks BLK included in a super memory block SBLK may be selected according to specific conditions.

In one embodiment, each of one or more of the plurality of memory blocks BLK included in a super memory block SBLK may be located on different memory die in the memory device110or located on different plane in the same memory die.

In another embodiment, each of one or more of the plurality of memory blocks BLK included in a super memory block SBLK may have same index value.

In still another embodiment, each of one or more of the plurality of memory blocks BLK included in a super memory block SBLK may be selected randomly from the plurality of memory blocks BLK included in the memory device110.

An example of writing target write data TGT_WR_DATA to one of the super memory block SBLK included in memory device110will be described further hereinafter inFIG.5.

FIG.5is a diagram illustrating an operation in which the memory system writes the target write data to the memory device according to embodiments of the present disclosure.

Referring toFIG.5, the memory controller120in memory system100may write the target write data TGT_WR_DATA to a first super memory block SBLK_1or a second super memory block SBLK_2.

The first super memory block SBLK_1is a super memory block SBLK which includes at least one bad word line. A bad word line may be included in one of the plurality of memory blocks BLK included in the first super memory block SBLK_1.

The bad word line is a word line in which a failure may occur while programming data to a page corresponding to the word line or reading data from the page corresponding to the word line. The bad word line can be generated at the time of manufacturing the memory system100or while the memory controller120executes a read, write or erase operation for the memory device110. The memory controller120may manage a had word line which exists in the memory device110by a specific data structure (e.g., a table, a list, an array) in which information about the bad word line which exists in the memory device is recorded.

A super memory block SBLK may include a plurality of pages. Each of the plurality of pages included in the super memory block SBLK is a page corresponding to a bad word line or a page corresponding to a normal word line which is not a bad word line. Hereinafter, a page corresponding to the bad word line may be referred to as a bad page and a page corresponding to the normal word line may be referred to as a normal page.

If data is written into the page corresponding to a bad word line, uncorrectable errors are more likely to occur while accessing data stored in the page corresponding to the bad word line.

Therefore, the memory controller120may control the memory device100, when data is written to the first super memory block SBLK_1in the memory device110, not to write the data to a page corresponding to a bad word line.

On the other hand, the second super memory block SBLK_2is a super memory block SBLK which includes no bad word line. All pages included in the second super memory block SBLK_2may be normal pages. When data is written to the second super memory block, the data can be written to any page in the second super memory block SBLK_2.

In an embodiment of the present disclosure, the memory controller120may write the target write data TGT_WR_DATA {circle around (1)} to the first super memory block SBLK_1or {circle around (2)} to the second super memory block SBLK_2based on a size of the target write data TGT_WR_DATA.

The reason why the memory controller120determines a super memory block to which the target write data TGT_WR_DATA is written based on a size of the target write data TGT_WR_DATA is as follows.

When data is written to a super memory block SBLK, the memory device110may write the data by an interleaving method to maximize write performance.

Interleaving means that writing data to the plurality of memory blocks BLK included in a super memory block SBLK in parallel by distributing to a set size (e.g., a page size), When the memory device110writes the data to the super memory block SBLK by an interleaving method, the portion of the data may be written to the plurality of memory blocks BLK included in the super memory block SBLK simultaneously. So data write performance can be improved.

But, if the data is written to the page corresponding to a bad word line when the data is written to the super memory block SBLK by an interleaving method, failure can occur while accessing the data written in the super memory block SBLK. Therefore, the memory controller120may control the memory device110not to write data to the page corresponding to a bad word line while writing data to the super memory block SBLK.

For example, the memory controller120may set a memory block, among the plurality of memory blocks BLK included in the super memory block SBLK, containing a bad word line as a bad memory block and control the memory device110not to write data to the bad memory block.

In this case, a super memory block SBLK is used inefficiently because a normal page included in the bad memory block is not used. When the bad memory block is replaced by another memory block from an over-provisioning area, lifespan of the memory system100may be decreased.

Also, the number of memory blocks to which data is written simultaneously may be decreased when the data is written to the super memory block SBLK by an interleaving method. So the size of the data written to the plurality of memory blocks in a super memory block may be decreased and, as a result, data write performance may be degraded.

To solve the problem that occurs when target write data TGT_WR_DATA is written, by an interleaving method, to the super memory block SBLK including a bad word line, the memory block120may determine that it is okay to write the target write data TGT_WR_DATA to the super memory block SBLK including a bad word line by an interleaving method.

If it is determined to be okay to write the target write data TGT_WR_DATA to the super memory block SBLK including a bad word line by an interleaving method, the memory controller120may write the target data to the super memory block SBLK including a bad word line. The memory controller120may write a portion of the target data to a normal page and may not write a portion of the target data to a bad page.

But, if it is not okay to write the target write data TGT_WR_DATA to the super memory block SBLK including a bad word line by an interleaving method, the memory controller120may write the target data to the super memory block SBLK including no bad word line.

Specifically, when it is determined to be okay to write the target write data TGT_WR_DATA to the first super memory block SBLK_1including a bad word line by an interleaving method, the memory controller120may write the target write data TGT_WR_DATA to the first super memory block SBLK_1. The memory controller120may use a super memory block SBLK more efficiently by only using a normal page in the super memory block SBLK including a bad word line. The memory controller120may use information indicating whether a page in the super memory block SBLK is a normal page or a bad page to use only a normal page in the super memory block SBLK. The memory controller120may increase data write performance by increasing the number of memory blocks to which data is written simultaneously while writing the target write data TGT_WR_DATA.

On the other hand, when it is determined not to be okay to write the target write data TGT_WR_DATA to the first super memory block SBLK_1by an interleaving method because of a bad word line, the memory controller120may write the target write data TGT_WR_DATA to the second super memory block SBLK_2. By writing the target write data TGT_WR_DATA to the second super memory block, the memory controller120may avoid the risk of uncorrectable error caused by a bad word line, while writing the target write data by an interleaving method.

Whether it is okay to write the target write data TGT_WR_DATA to the first super memory block SBLK_1including a bad word line by an interleaving method may be determined according to whether the size of target write data TGT_WR_DATA is less than or equal to the maximum value of the data size that can be written to the first super memory block SBLK_1by an interleaving method. The memory controller120may determine the super memory block SBLK to which the target write data TGT_WR_DATA is written, based on the size of the target write data TGT_WR_DATA.

In the above, the operation in which the memory controller120of the memory system100determines the super memory block SBLK to which the target write data TGT_WR_DATA is to be written to when the memory controller120is to write the target write data TGT_WR_DATA to the super memory block SBLK in the memory device110is described.

Hereinafter, a detailed embodiment thereof will be described. First, a specific example of the target write data TGT_WR_DATA will be described.

In an embodiment of the present disclosure, the target write data TGT_WR_DATA may be meta-data. Meta-data is data storing meta information which is used to manage user data stored in the memory device110. Meta-data may be stored in the spare area in the memory device110.

In an embodiment, meta-data may include log data or history data corresponding to the data which is stored in the memory device110, updated in the memory device110or deleted from the memory device.

In another embodiment, meta-data may be map data including mapping information between a logical address LA and a physical address PA.

FIG.6is a diagram illustrating a target write data according to embodiments of the present disclosure.

Referring toFIG.6, the target write data TGT_WR_DATA may be map data including mapping information between a logical address LA and a physical address PA. Map data is used by the memory controller120to convert the logical address LA provided by host to the physical address PA for accessing the memory device110through flash translation layer FTL. When the mapping information between a specific logical address LA and a specific physical address PA is updated by executing a data write operation or background operation (e.g. garbage collection, wear leveling, read reclaim), the memory controller120may write the map data including updated map information to the memory device110.

The memory controller120may determine the size of the map data to be written to the memory device110in advance, because the format of the map data is predetermined. The memory controller120may determine a super memory block to which the map data is written based on the size of the map data.

FIG.7is a diagram illustrating another target write data according to embodiments of the present disclosure.

Referring toFIG.7, the target write data TGT_WR_DATA may be at least a part of user data received from the host HOST.

To write user data to the memory system100, the host HOST may transmit the user data and command to request to write the user data to the memory controller120in the memory system100.

The memory controller120may write the user data received from the host HOST to the memory device110after storing the user data in a buffer BUF temporarily. For example, the buffer BUF may be a memory area in the working memory125described inFIG.1

In this case, instead of immediately writing the user data received from the host to the memory device110, the memory controller120may temporarily store the user data received from the host HOST to the buffer BUF until a specific condition is satisfied.

Since it is impossible to determine the target write data TGT_WR_DATA to be written to the memory device110while the memory controller120stores the user data received from the host HOST in the buffer BUF temporarily. The memory controller120may determine the target write data TGT_WR_DATA when the specific condition is satisfied.

For example, the memory controller120may determine the target write data TGT_WR_DATA when the size of user data stored in the buffer BUF temporarily is greater than or equal to a reference size. At this time, the reference size may be a unit size in which data can be written to the super memory block SBLK at a time and the size of the target write data TGT_WR_DATA may be the reference size.

For another example, the memory controller120may determine the target write data TGT_WR_DATA according to a command received from the host HOST, even though the size of user data temporarily stored in the buffer BUF is less than the set reference size. Hereinafter, this will be described with reference toFIG.8.

FIG.8is a diagram lustrating an operation in which the memory system determines the target write data inFIG.7according to embodiments of the present disclosure.

Referring toFIG.8, the memory controller120of the memory system100may determine the target write data TGT_WR_DATA from the user data received from the host, when receiving a flush command, barrier command, or synchronization command from the host.

A flush command is a command indicating the memory system100to write the data requested to be written to the memory device110forcibly, before the host HOST transmits the flush command to the memory system100, wherein the data is not written to the memory device110yet and is temporarily stored in the buffer BUF of the memory controller120.

A barrier command is a command indicating a write order between 1) the data requested to be written before the host HOST transmits the barrier command to the memory system100and 2) the data requested to be written after the host HOST transmits the barrier command to the memory system100. In this case, the data requested to be written before the host HOST transmits the barrier command to the memory system100should be written to the memory device110before the data requested to be written after the host HOST transmits the barrier command to the memory system100.

A synchronization command is a command indicating the memory system100to synchronize 1) the data requested by the host HOST and 2) the data written to the memory device110.

When the memory controller120receives the flush command, the barrier command or the synchronization command, the memory controller120may write the user data which is temporarily stored in the buffer BUF to the memory device110immediately without waiting for additional user data from the host HOST. Accordingly, the memory controller120may determine the target write data TGT_WR_DATA to be written to the memory device110.

In the above, a specific method for the memory controller120to determine the target write data TGT_WR_DATA has been described.

Hereinafter, a detailed method for the memory controller120to determine the super memory block SBLK to write the target write data TGT_WR_DATA will be described.

FIG.9is a flowchart illustrating an operation in which the memory system determines a super memory block to which the target write data is written according to embodiments of the present disclosure.

Referring toFIG.9, the memory controller120of the memory system110may check the size of the target write data TGT_WR_DATA to be written to the memory device110(S910).

The memory controller120may determine whether the size of the target write data TGT_WR_DATA is less than or equal to a set threshold size (S920).

When the size of the target write data TGT_WR_DATA is less than or equal to the set threshold size (S920-Y), the memory controller120may write the target write data TGT_WR_DATA to the first super memory block SBLK_1described inFIG.5(S930).

On the other hand, when the size of the target write data TGT_WR_DATA is greater than the set threshold size (S920-N), the memory controller120may write the target write data TGT_WR_DATA to the second super memory block SBLK_2described inFIG.5(S940).

That is, the memory controller120may determine the super memory block to which the target write data TGT_WR_DATA is to be written based on the set threshold size. Accordingly, the set threshold size may affect the determination of the super memory block to which the target write data TGT_WR_DATA is to be written.

FIG.10is a diagram illustrating an operation in which the memory system determines the threshold size disclosed inFIG.9according to embodiments of the present disclosure.

Referring toFIG.10, the memory controller120of the memory system100may determine the threshold size based on a target super page TGT_SPG. The target super page TGT_SPG is a page into which data is to be written within the first super memory block SBLK_1and the target super page is one of a plurality of super pages SPG each including two or more pages in the first super memory block SBLK_1.

In an embodiment of the present disclosure, a super memory block SBLK may include a plurality of super pages SPG. A super page SPG may include two or more pages in the super memory block SBLK and the size of the super page may be the unit size in which data is written to the super memory block SBLK. Also, the first super memory block SBLK_1may include a plurality of super pages SPG.

Each of the plurality of super pages SPG included in the first super memory block SBLK_1may include two or more pages PG included in the first super memory block SBLK_1. While writing data to the first super memory block SBLK_1, the memory controller120may control the memory device110to write data in units of super pages SPG.

In this case, each of the pages PG included in one super page SPG may be, for example, a page included in different memory blocks BLK respectively. The index of the word line corresponding to each of the pages PG included in a super page SPG may be the same. Or, the index of the word line corresponding to each of the pages PG included in a super page SPG may be different based on start position of the super page.

Among the plurality of super pages SPG included in the first super memory block SBLK_1, some are super pages to which valid or invalid data is already written and the rest are super pages in an erase state, to which new data is enabled to be written.

Among the plurality of super pages SPG included in the first super memory block SBLK_1, the memory controller120may determine a target super page TGT_SPG, which is a super page SPG to which data is to be written next, from among the remaining super pages SPG except for the super page to which data has already been written.

The memory controller120may determine the threshold size as the maximum value available to store data within the target super page TGT_SPG of the first super memory block SBLK_1. If the size of the target write data TGT_WR_DATA is greater than the threshold size of the target super page TGT_SPG within the first super memory block SBLK_1, the memory controller120may write the target write data TGT_WR_DATA to the second super memory block SBLK_2because the target write data TGT_WR_DATA cannot be written to the target super page TGT_SPG of the first super memory block SBLK_1.

On the other hand, if the size of the target write data TGT_WR_DATA is less than or equal to the threshold size of the target super page TGT_SPG within the first super memory block SBLK_1, the memory controller120may write the target write data TGT_WR_DATA to the first super memory block SBLK_1because the target write data TGT_WR_DATA can be written to the target super page TGT_SPG within the first super memory block SBLK_1. In this case, the threshold size of the target super page TGT_SPG may be maximum value of the data size that can be written to the target super page TGT_SPG.

FIG.11is a diagram illustrating an operation in which the memory system determines the threshold size based on target super page disclose inFIG.10according to embodiments of the present disclosure.

Referring toFIG.11, the memory controller120of the memory system100may determine the threshold size based on the number of normal pages PG and a storage capacity of each of the normal pages PG. The normal pages are pages other than a bad page corresponding to the bad word line within the target super page TGT_SPG.

When a page corresponding to a bad word line exists in the target super page TGT_SPG, data is not written to the page corresponding to the bad word line. This is because a fail may occur while writing data to the page corresponding to the bad word line. The memory controller120may check whether a page in the target super page TGT_SPG is a page corresponding to a bad word line or not, and may skip writing data to the page if the page corresponds to a bad word line.

So, the memory controller120may determine, as the threshold size, the maximum value of the storage capacity of the normal pages other than the bad page corresponding to the bad word line within the target super page TGT_SPG.

As an example, the target super page TGT_SPG includes 4 pages PG and the storage capacity of each page PG is 4 KB.

For example, if 2 pages PG among pages included in the target super page TGT_SPG are bad pages corresponding to bad word lines, the threshold size of the target super page TGT_SPG is determined as 8 KB, which is a value obtained by multiplying the number of remaining pages of the target super page TGT_SPG excluding the page corresponding to the bad word line 2=4−2 by the storage capacity of each page (PG) 4 KB.

For another example, if 1 pages PG among pages included in the target super page TGT_SPG is a bad page corresponding to a bad word line, the threshold size of the target super page TGT_SPG is determined as 12 KB, which is a value obtained by multiplying the number of remaining pages of the target super page TGT_SPG excluding the page corresponding to the bad word line 3=4−1 by the storage capacity of each page (PG) 4 KB.

FIG.12is a flowchart illustrating a method for operating the memory system according to an embodiment of the present disclosure.

Referring toFIG.12, a method for operating the memory system100may include setting a plurality of super memory blocks SBLK each including one or more of the plurality of memory blocks BLK included in the memory device110(S1210).

In addition, a method for operating the memory system100may include determining a target write data TGT_WR_DATA which is to be written to one of the plurality of super memory blocks SBLK (S1220).

In this case, the target write data TGT_WR_DATA may be meta-data. For example, the target write data TGT_WR_DATA may be map data which includes mapping information between a logical address and a physical address.

For another example, the target write data TGT_WR_DATA may be at least a part of user data received from a host, wherein the host requests the memory system100to write the user data. The memory system100may determine the target write data TGT_WR_DATA when receiving a flush command, barrier command or synchronization command from the host HOST.

In addition, a method for operating the memory system100may include writing the determined target write data TGT_WR_DATA to a first super memory block SBLK_1which includes at least one bad word line or a second super memory block SBLK_2which includes no bad word line (S1230).

The memory system100may write the target write data to the first super memory block when the size of the target write data is less than or equal to a set threshold size. And the memory system100may write the target data to the second super memory block when the size of the target write data is greater than the set threshold size.

In this case, the memory system100may set the threshold size based on a target super page TGT_SPG, into which the target data is written within the first super memory block SBLK_1. The target super page TGT_SPG may include two or more pages in the first super memory block SBLK_1.

The threshold size may be set based on the number of normal pages and a storage capacity of each of the normal pages, wherein the normal pages are pages other than a bad page corresponding to a bad word line within the target super page TGT_SPG.

FIG.13is a diagram illustrating the configuration of a computing system1300based on an embodiment of the disclosed technology.

Referring toFIG.13, the computing system1300based on an embodiment of the disclosed technology may include: a memory system100electrically connected to a system bus1360; a CPU1310configured to control the overall operation of the computing system1300; a RAM1320configured to store data and information related to operations of the computing system1300; a user interface/user experience (UI/UX) module1330configured to provide the user with a user environment; a communication module1340configured to communicate with an external device as a wired and/or wireless type; and a power management module1350configured to manage power used by the computing system1300.

The computing system1300may be a personal computer (PC) or may include a mobile terminal such as a smartphone, a tablet or various electronic devices.

The computing system1300may further include a battery for supplying an operating voltage, and may further include an application chipset, a graphic-related module, a camera image processor, and a DRAM. Other elements would be apparent to a person skilled in the art.

The memory system100may Include not only a device configured to store data in a magnetic disk such as a hard disk drive (HDD), but also a device configured to store data in a nonvolatile memory such as a solid state drive (SSD), a universal flash storage device, or an embedded MMC (eMMC) device. The non-volatile memory may include a read only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable and programmable ROM (EEPROM), a flash memory, a phase-change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), a ferroelectric RAM (FRAM), and the like. In addition, the memory system100may be implemented as storage devices of various types and mounted inside various electronic devices.

Based on embodiments of the disclosed technology described above, the operation delay time of the memory system may be advantageously reduced or minimized. In addition, based on an embodiment of the disclosed technology, an overhead occurring in the process of calling a specific function may be advantageously reduced or minimized. Although various embodiments of the disclosed technology have been described with particular specifics and varying details for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions may be made based on what is disclosed or illustrated in the present disclosure without departing from the spirit and scope of the invention as defined in the following claims. Furthermore, the embodiments may be combined to form additional embodiments.