IC structure including porous semiconductor layer under trench isolations adjacent source/drain regions

An integrated circuit (IC) structure includes an active device over a bulk semiconductor substrate, and an isolation structure around the active device in the bulk semiconductor substrate. The active device includes a semiconductor layer having a center region, a first end region laterally spaced from the center region by a first trench isolation, a second end region laterally spaced from the center region by a second trench isolation, a gate over the center region, and a source/drain region in each of the first and second end regions. The isolation structure includes: a polycrystalline isolation layer under the active device, a third trench isolation around the active device, and a porous semiconductor layer between the first trench isolation and the polycrystalline isolation layer and between the second trench isolation and the polycrystalline isolation layer.

BACKGROUND

The present disclosure relates to integrated circuit (IC) structures, and more specifically, to an IC structure, such as a radio frequency switch, including a porous semiconductor layer under trench isolations adjacent source/drain regions to provide additional isolation for the active device.

In integrated circuit (IC) structures, active devices are electrically isolated by dielectrics such as trench isolations. In radio frequency (RF) device applications such as switches, power amplifiers and other devices, additional isolation layers to reduce harmonics and parasitic losses are advantageous. One current approach uses a trap-rich, high resistivity polycrystalline isolation layer between the buried insulator and the semiconductor substrate in a semiconductor-on-insulator (SOI) substrate. The high resistivity, polycrystalline isolation layer is located below the RF active devices and provides additional isolation to the devices. This approach works well for SOI substrates. However, bulk semiconductor substrates including a high resistivity, polycrystalline isolation layer exhibit higher harmonics and substrate leakage current than SOI substrates.

SUMMARY

An aspect of the disclosure is directed to an integrated circuit (IC) structure, comprising: an active device over a bulk semiconductor substrate, the active device including a semiconductor layer having a center region, a first end region laterally spaced from the center region by a first trench isolation, a second end region laterally spaced from the center region by a second trench isolation, a gate over the center region, and a source/drain region in each of the first and second end regions; and an isolation structure around the active device in the bulk semiconductor substrate, the isolation structure including: a polycrystalline isolation layer under the active device, a third trench isolation around the active device, and a porous semiconductor layer between the first trench isolation and the polycrystalline isolation layer and between the second trench isolation and the polycrystalline isolation layer.

Another aspect of the disclosure includes an integrated circuit (IC) structure, comprising: an active device over a bulk semiconductor substrate, the active device including a semiconductor layer having a center region, a first end region laterally spaced from the center region by a first trench isolation, a second end region laterally spaced from the center region by a second trench isolation, a gate over the center region, and a raised source/drain region over each of the first and second trench isolation; and an isolation structure around the active device in the bulk semiconductor substrate, the isolation structure including: a polycrystalline isolation layer under the active device, a third trench isolation around the active device, and a porous semiconductor layer between the first trench isolation and the polycrystalline isolation layer and the between second trench isolation and the polycrystalline isolation layer.

An aspect of the disclosure related to a method, comprising: forming a semiconductor layer over a bulk semiconductor substrate, the semiconductor layer including a center region, a first end region laterally spaced from the center region by a first opening, and a second end region laterally spaced from the center region by a second opening, wherein a protective cap layer extends over the center region, the first end region and the second end region; forming a porous semiconductor layer in exposed regions of the bulk semiconductor substrate through the first and second openings and adjacent to the first and second end regions; forming an insulator over the semiconductor layer to create first and second trench isolation in the first and second openings and a third trench isolation about the semiconductor layer; forming a polycrystalline isolation layer below the semiconductor layer; and forming an active device with the semiconductor layer.

The foregoing and other features of the disclosure will be apparent from the following more particular description of embodiments of the disclosure.

DETAILED DESCRIPTION

Reference in the specification to “one embodiment” or “an embodiment” of the present disclosure, as well as other variations thereof, means that a particular feature, structure, characteristic, and so forth described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the phrases “in one embodiment” or “in an embodiment,” as well as any other variations appearing in various places throughout the specification are not necessarily all referring to the same embodiment. It is to be appreciated that the use of any of the following “/,” “and/or,” and “at least one of,” for example, in the cases of “A/B,” “A and/or B” and “at least one of A and B,” is intended to encompass the selection of the first listed option (a) only, or the selection of the second listed option (B) only, or the selection of both options (A and B). As a further example, in the cases of “A, B, and/or C” and “at least one of A, B, and C,” such phrasing is intended to encompass the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of the third listed option (C) only, or the selection of the first and the second listed options (A and B), or the selection of the first and third listed options (A and C) only, or the selection of the second and third listed options (B and C) only, or the selection of all three options (A and B and C). This may be extended, as readily apparent by one of ordinary skill in the art, for as many items listed.

Embodiments of the disclosure include an integrated circuit (IC) structure including an active device over a bulk semiconductor substrate, and an isolation structure around the active device in the bulk semiconductor substrate. The active device includes a semiconductor layer having a center region, a first end region laterally spaced from the center region by a first trench isolation, and a second end region laterally spaced from the center region by a second trench isolation. The active device also includes a gate over the center region, and either a source/drain region in each of the first and second end regions or a raised source/drain region over the first and second trench isolations. The isolation structure includes: a polycrystalline isolation layer under the active device, a third trench isolation around the active device, and a porous semiconductor layer between the first trench isolation and the polycrystalline isolation layer and between the second trench isolation and the polycrystalline isolation layer. The IC structure employs a lower cost, low resistivity bulk semiconductor substrate rather than a semiconductor-on-insulator (SOI) substrate, yet it has better performance characteristics for radio frequency (RF) devices than an SOI substrate. For example, the IC structure with the porous semiconductor layer under the trench isolations adjacent the source/drain regions exhibits better current leakage, harmonic distortion, cross-talk resistance, effective resistivity, effective permittivity, and attenuation, compared to current SOI substrate devices.

FIG.1shows a cross-sectional view of an IC structure100, according to embodiments of the disclosure. IC structure100includes an active device102over a bulk semiconductor substrate104. Bulk semiconductor substrate104includes a low resistivity semiconductor material, which is relatively inexpensive to produce compared to a higher resistivity SOI substrate. Bulk semiconductor substrate104may include any semiconductor material that can be made porous, as described herein, including but not limited to silicon. Bulk semiconductor substrate104is monocrystalline. A portion of or entirety of bulk semiconductor substrate104may be strained.

Active device102may include any now known or later developed transistor. IC structure100may have several applications. For example, as noted herein, it finds advantageous application as a radio frequency (RF) switch200(FIGS.1,10,11). Active device102may include a semiconductor layer106having a center region108, a first end region110laterally spaced from center region108by a first trench isolation112, a second end region114laterally spaced from center region108by a second trench isolation116. Active device102may also include, for example, a gate120over center region108, and a source/drain region122S,122D in each of the first and second end regions110,114, respectively. Here, center region108provides a channel region124for active device102. Source/drain regions122S,122D may include any appropriate dopant within end regions110,114. Gate120may be a metal or polysilicon gate and may include one or more conductive components for providing a gate terminal of a transistor. For example, metal gates120may include a high dielectric constant (high-K) layer, a work function metal layer and a gate conductor (none shown for clarity). A gate cap (not shown) may also be formed over gate120.

Gate dielectric layer128may include any now known or later developed gate dielectric materials such as but not limited to hafnium silicate (HfSiO), hafnium oxide (HfO2), zirconium silicate (ZrSiOx), zirconium oxide (ZrO2), silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), high-k material or any combination of these materials. Spacer126may include any now known or later developed spacer material such as silicon nitride. A silicide layer130for contacts (not shown) may be provided over source/drain122S in first end region110and first trench isolation112, and over source/drain122D in second end region114. Silicide layer130may also be provided over gate120.

In certain embodiments, semiconductor layer106may include a semiconductor epitaxial layer in which source/drain regions122S,122D are formed. (While source/drain regions are denoted with reference numbers122S,122D, the location of the source or drain can be different than inferred by the letter notations). Semiconductor layer106has a resistivity higher than bulk semiconductor substrate104. Hence, center region108, first end region110and second end region114have a resistivity higher than bulk semiconductor substrate104. In one example, bulk semiconductor substrate104may have a resistivity of less than approximately 4.0 Ohms per square centimeter (Ω/cm2), and center region108, first end region110and second end region114may have a resistivity of greater than approximately 1000 Ω/cm2. The terms “epitaxial” and “epitaxially formed and/or grown” means the growth of a semiconductor material on a deposition surface of bulk semiconductor substrate104may have the same crystalline characteristics as the semiconductor material of the deposition surface. In an epitaxial growth process, the chemical reactants provided by the source gases are controlled and the system parameters are set so that the depositing atoms arrive at the deposition surface of the semiconductor substrate with sufficient energy to move around on the surface and orient themselves to the crystal arrangement of the atoms of the deposition surface.

IC structure100also includes an isolation structure140around active device102in bulk semiconductor substrate104. Isolation structure140may include a polycrystalline isolation layer142under active device102. As illustrated, semiconductor layer106is over polycrystalline isolation layer142. As will be described herein, polycrystalline isolation layer142may be formed by introducing noble gas ions into bulk semiconductor substrate104, and annealing. In one example, bulk semiconductor substrate104may have a resistivity of less than approximately 4.0 Ω/cm2, and polycrystalline isolation layer142(and semiconductor layer106) may have a resistivity of greater than approximately 1000 Ω/cm2. Hence, polycrystalline isolation layer142exhibits a high resistance compared to bulk semiconductor substrate104, and thus acts to electrically isolate an underside of active device102.

Isolation structure140also includes a third trench isolation144around active device102. Trench isolations (TI)112,116,144include trenches etched into semiconductor layer106and/or bulk semiconductor substrate104, and filled with an insulator. TIs112,116, isolation end regions110,114and TI144isolate active device102at adjacent regions of the substrate. Hence, TIs112,116,144may be formed simultaneously, as will be described. As will also be described, prior to forming TIs112,116,144, a porous semiconductor layer146in parts of bulk semiconductor substrate104so it is under first TI112, second TI116and third TI144. Each TI,112,116,144may be formed of electrical insulation, and as examples may include: silicon nitride (Si3N4), silicon oxide (SiO2), fluorinated SiO2(FSG), hydrogenated silicon oxycarbide (SiCOH), boro-phospho-silicate glass (BPSG), silsesquioxanes, carbon (C) doped oxides (i.e., organosilicates) that include atoms of silicon (Si), carbon (C), oxygen (O), and/or hydrogen (H), thermosetting polyarylene ethers, a spin-on silicon-carbon containing polymer material, near frictionless carbon (NFC), or layers thereof. TIs112,116,144may be provided as shallow trench isolations (STI) (shown) or deep trench isolations (DTI). First and second TIs112,116separate end regions110,114from center region108, i.e., linearly into and out of the page. Third TI144surrounds active device102, and thus also couples with ends of first and second TIs112,116at locations into and out of the page.

Isolation structure140also includes a porous semiconductor layer146between first trench isolation112and polycrystalline isolation layer142, and between second trench isolation116and polycrystalline isolation layer142. Notably, porous semiconductor layer146includes portions148,150between respective trench isolations112,116. Portions148,150are separated by portions152of bulk semiconductor substrate104. Optionally, porous semiconductor layer146may also include portions154between third trench isolation144and bulk semiconductor substrate104. Porous semiconductor layer146provides additional resistance to electrically isolate active device102from bulk semiconductor substrate104. Porous semiconductor layer146allows IC structure100to have electrical isolation that is as good as or better than IC structures built on more expensive, high resistivity SOI substrates. Porous semiconductor layer146may include the same material as bulk semiconductor substrate104, but made porous as described herein. In one example, porous semiconductor layer146and bulk semiconductor substrate104may include silicon (Si). In one example, porous semiconductor layer146has a depth of between 100 nanometers (nm) to 10 micrometers (μm). In some conventional applications, porous silicon has been used as a trench isolation. However, according to embodiments of the disclosure, TIs,112,116,144and porous semiconductor layer146do not include the same material.

Polycrystalline isolation layer142does not extend under third TI144. Polycrystalline isolation layer142may include an endwall160however contacting at least one of third TI144and portions154of porous semiconductor layer146, e.g., depending on a vertical positioning and/or depth of polycrystalline isolation layer142, third TI144and/or portions154of porous semiconductor layer146. Similarly, porous semiconductor layer146may include a sidewall162in contact with bulk semiconductor substrate104(portion152) and perhaps polycrystalline isolation layer142.

Isolation structure140thus includes polycrystalline isolation layer142under active device102. Isolation structure140also includes TIs112,116,144, and includes porous semiconductor layer146between first and second TIs112,116and polycrystalline isolation layer142, and perhaps between third TI144and bulk semiconductor substrate104. TIs112,116,144do not include the same material as porous semiconductor layer146, e.g., TIs112,116,144may include silicon oxide where porous semiconductor layer146includes oxidized porous silicon.

Referring toFIGS.2-8, cross-sectional views of one embodiment of a method of forming IC structure100are shown.

FIGS.2-3show forming center region108, first end region110and second end region114(FIG.3), creating an active region168(FIG.8), over bulk semiconductor substrate104using a protective cap layer172. In the example shown inFIG.2, forming active region168includes forming semiconductor layer106having a resistivity higher than bulk semiconductor substrate104.FIG.2shows forming semiconductor layer106over bulk semiconductor substrate104. As shown inFIG.3, semiconductor layer106is eventually formed to include center region108, first end region110laterally spaced from center region108by first opening180, and a second end region114laterally spaced from center region108by second opening182. A protective cap layer172will extend over center region108, first end region110and second end region114, during some of the processing. Semiconductor layer146may be formed through, for example, epitaxial growth in or on bulk semiconductor substrate104. As noted, bulk semiconductor substrate104may have a resistivity of less than approximately 4.0 Ω/cm2, and semiconductor layer146may have a resistivity of greater than approximately 1000 Ω/cm2.

FIG.2also shows formation of protective cap layer172. In the example shown, protective cap layer172includes a number of sub-layers174,176of, for example, oxide in sub-layer174and nitride in sub-layer176; however, other materials are also possible. Protective cap layer172may be formed by any appropriate deposition technique(s) for the material formed, e.g., chemical vapor deposition (CVD), atomic layer deposition (ALD), among others. A mask178may be used to pattern active region168(FIG.3), e.g., by etching. Mask178may include any appropriate mask material for the etching process and material (e.g., silicon) to be etched. Any appropriate etching process may be used, e.g., a RIE or wet etch. As shown inFIG.3, the etching (arrows inFIG.2) creates first opening180between first end region110and center region108, and second opening182between second end region114and center region108. The etching also creates an opening184around active region168. Openings180,182,184are connected, i.e., at ends of openings180,182. Forming openings180,182,184also creates exposed regions186of bulk semiconductor substrate104. At this stage, mask178(FIG.2) can be removed using any appropriate technique, e.g., an ashing process.

FIG.4shows an optional step of (additionally) forming protective cap layer172along a sidewall188of active region168. More particularly, portions190of protective cap layer172extend over a sidewall of first end region110and second end region114. In the example shown, a single nitride layer is used; however, a variety of materials and any number of layers may be used. Portions190of protective cap layer172provide additional protection of end regions110,114during subsequent formation of porous semiconductor layer146(FIG.6). It is noted, however, that portions190of protective layer172are not necessary because the processing (FIGS.5-6) to form porous semiconductor layer146may be made selective to bulk semiconductor substrate104. That is, end portions110,114are immune to the processing.

FIGS.5-6show forming porous semiconductor layer146in exposed regions186(FIG.5) of bulk semiconductor substrate104through first and second openings180,182and adjacent to first and second end regions110,114. The porous layer forming may include, as shown inFIG.5, exposing exposed regions186to an electrolyte solution192, and applying a voltage (V) across bulk semiconductor substrate104. While a variety of techniques are possible, in one example, electrolyte solution192may include hydrofluoric (HF) acid that etches the semiconductor material and makes it porous. Other techniques for forming a porous semiconductor layer are known, and thus no additional details are necessary. A depth and width of porous semiconductor layer146(FIG.6) can be controlled by, for example, the duration of exposure to electrolyte solution192, the electrolyte material and concentration, a width and/or depth of openings180,182, and the voltage applied. In one example, porous semiconductor layer146(FIG.6) may have a depth of between 100 nanometers (nm) to 10 micrometers (μm). As illustrated inFIG.6, portion148of porous semiconductor layer146is formed in bulk semiconductor substrate104via opening180, and portion150of porous semiconductor layer146is formed in bulk semiconductor substrate104via opening182. Portions148,150are separated by (remaining) portions152of bulk semiconductor substrate104. Optionally, porous semiconductor layer146may also include portions154in bulk semiconductor substrate104. As shown, porous semiconductor layer146may include endwall162(of portions154) in contact with bulk semiconductor substrate104, i.e., portion152thereof. Hence, porous semiconductor layer146does not constitute an entirety of substrate104nor does it extend along an entire length of substrate104. At this stage, protective cap layer172(FIG.5), including portions190(FIG.5), if provided, can be removed using any appropriate technique, e.g., a selective etch.

FIG.7shows forming an insulator194over porous semiconductor layer146to create first TI112and second TI116in first and second openings180,182(FIG.5), respectively, and third TI144around semiconductor layer106(i.e., active region168). In the latter case, insulator194surrounds semiconductor layer106and hence active region168(FIG.1) to be formed therein. First and second TIs112,116connect to third TI144at ends thereof (not shown, into and out of page). Insulator194may include any of the materials previously listed herein for TIs112,116,144, e.g., silicon oxide, and may be formed by any appropriate deposition technique, e.g., CVD, ALD, among others. Any necessary planarization step may then occur, e.g., chemical mechanical planarization, to remove any excess insulator194.

FIG.8shows forming polycrystalline isolation layer142below semiconductor layer106, so it is below the eventually formed active region168(FIG.1). Polycrystalline Polycrystalline isolation layer142may be formed, for example, by doping an area under active region168, i.e., under center region108, first end region110, second end region114, and TIs112,116. There are a number of ways to dope the desired area to form polycrystalline isolation layer142. In one example, the process may include implanting a dopant (straight arrows inFIG.8) into active region168, and potentially other areas of semiconductor substrate104, not shown. As illustrated, the dopant is implanted into monocrystalline semiconductor substrate104. Implanting (or more generally, doping) is the process of introducing impurities (dopants) into a material. An ion implanter is typically employed for the actual implantation. An inert carrier gas such as nitrogen is usually used to bring in the impurity source (dopant). A dosage and an energy level appropriate for the particular bulk semiconductor substrate104and desired doping may be specified and/or a resulting doping level may be specified. An example of doping is implanting with argon (Ar) with a dosage of between about 1E12 and 1E13 atoms/cm2, and an energy of about 40 to 500 keV to produce a doping level of between 1E17 and 1E18 atoms/cm3. In this case, as shown inFIG.8, the doping is carried out to damage the monocrystalline material to which it is applied.

FIG.8also shows one or more thermal cycle(s), e.g., an anneal indicated by curved arrows, that re-orders the damaged and disordered crystallographic material into polycrystalline material. The thermal cycle(s) may include one or more intentionally added recrystallization anneal(s) shortly after implant, or the normal high temperature (>600° C.) process(es) associated with semiconductor manufacturing. In this manner, the process converts monocrystalline bulk semiconductor substrate104(under active region168) to polycrystalline isolation region142. The dopant implanted may be include any material capable of creating polycrystalline material including but not limited to: germanium (Ge); a noble gas such as argon (Ar) or xenon (Xe); or a combination of the previously listed materials such as Ge—Ar or Ge—Xe. The vertical location at which polycrystalline isolation layer142starts and the depth of layer142can be controlled by the duration and energy of the ion implanting used. As noted, endwall162of porous semiconductor layer146may be in contact with polycrystalline isolation layer142and bulk semiconductor substrate104. Polycrystalline isolation layer142does not extend under third TI144. In an alternative embodiment, polycrystalline isolation layer142may be formed in bulk semiconductor substrate104prior to any of the processing shown inFIGS.2-8, and active region169and TIs112,116,144may be formed thereover. In any event, polycrystalline isolation layer142may have a resistivity of, for example, greater than 1000 Ω/cm2, providing relatively strong resistance to current leakage from under active device102(FIG.1).

Returning toFIG.1, forming an active device102with semiconductor layer106is illustrated. Active device102may be formed using any now known or later developed semiconductor fabrication techniques, the options of which are well known and will not be described in detail. In any event, forming active device102may include forming gate120over center region108, first source/drain region122S in first end region110and second source/drain region122D in second end region114. Gate(s)120may be formed using any now known or later developed processes. In one non-limiting example, gate(s)120material may be deposited and patterned using photolithography, and spacer126formed thereabout, e.g., by depositing a nitride and etching back. A nitride cap (not shown) may be formed over gate(s)120. Gate(s)120may include dummy gate material, e.g., including sacrificial material to be replaced with the final gate material after source/drain region122S,122D formation, or they may include the final gate material, e.g., polysilicon or metal gate material. Source/drain regions122S,122D may be formed using any appropriate process, e.g., masked doping and annealing.

FIG.1also shows processing after forming silicide layer130over each of pair of source/drain regions122S,122D. Silicide layer130may include any silicide for coupling to contacts (not shown) through an interlayer dielectric (ILD) (not shown). Silicide layer130may be formed using any now known or later developed technique, e.g., performing an in-situ pre-clean, depositing a metal such as titanium, nickel, cobalt, platinum, etc., annealing to have the metal react with silicon of end regions110,114, and removing unreacted metal. Normally, silicide layer130would not form on first and second TIs112,116. However, TIs112,116are sufficiently small that silicide layer130spans over the TIs, and hence is shown as a contiguous layer. An ILD (not shown) may be deposited and include any now known or later developed ILD material. Any desired interconnects, e.g., contacts and wiring (not shown), may be formed through the ILD in a known fashion.

FIGS.9and10show cross-sectional views of forming IC structure100, according to an alternative embodiment of the disclosure. More particularly,FIGS.9and10show forming a first raised source/drain (RSD) region198S over first TI112, and forming a second raised source/drain (RSD) region198D over second TI116. (While the raised source/drain regions are denoted with reference numbers198S,198D, the location of the source or drain can be different than inferred by the letter notations.)FIG.9follows the processes ofFIG.8. RSD regions198S,198D may be formed in any now known or later developed fashion. In the example shown inFIG.9, a number of processes have occurred.FIG.9shows forming a first polysilicon section210on first TI112, a second polysilicon section212on second TI116, and a silicon layer214over semiconductor layer106between first polysilicon section210and second polysilicon section212. This process may include epitaxially growing first polysilicon section210over first TI112, second polysilicon section212over second TI116, and silicon layer214over semiconductor layer116. Where the growth occurs on TIs112,116,144, polysilicon is formed, and where growth occurs on semiconductor layer106, silicon is formed. Polysilicon section(s)216(dashed lines) that would form on third TI144are removed, e.g., by forming any necessary mask and etching to remove the polysilicon from over third TI144. Polysilicon sections210,212have a width to match, as close as possible, that of RSD regions198S,198D (FIG.10) to be formed thereover. In one non-limiting example, the width may range between 300-600 nanometers (nm). Polysilicon sections210,212may have a thickness of, for example, 10-60 nm.

FIG.9also shows forming a first silicon section220over first polysilicon section210and a second silicon section222over second polysilicon section212. Silicon sections220,222may be formed as a continuance of the epitaxial growth from semiconductor layer106and polysilicon sections210,212. Silicon sections220,222may have any thickness desired for RSD regions198S,198D (FIG.10). In one embodiment, a thickness of silicon sections220,222over polysilicon sections210,212is made to approach that of SOI layers in SOI substrates to obtain similar performance as SOI substrates even though transistor100is formed on bulk semiconductor substrate104. In one non-limiting example, silicon sections220,222may have a thickness in the range 10-60 nm.

FIG.10shows a cross-sectional view of forming active device102by forming gate120over a region of silicon layer214between first silicon section220and second silicon section222. As illustrated, upper surfaces (below silicide layer130) of first and second silicon sections220,222are higher than a lower surface230of gate120. Silicon layer214provides channel region124between eventually formed first RSD region198S and second RSD region198D.FIG.10also shows forming active device102includes forming an RSD region198S,198D over each of first and second TIs112,116. More particularly, forming active device102includes forming first RSD region198S in first silicon section220over first TI112, and forming second RSD region198D in second silicon section222over second TI116. Gate(s)120and RSD regions198,198D may be formed using any now known or later developed processes, as previously described herein. For example, RSD regions198S,198D may be formed by doping silicon sections220,222with appropriate dopants (e.g., using ion implanting), and annealing to drive in the dopants. The dopants used may vary depending on the type of transistor to be formed. Silicide layer130may be formed, as previously described herein. InFIG.10, silicide layer130is over first RSD region198S over first TI112, and over second RSD region198D over second TI116.

FIGS.11and12show cross-sectional views of forming IC structure100, according to another alternative embodiment of the disclosure. IC structure100inFIG.11includes, in addition to the structure shown inFIG.10, a first air gap240in first TI112(i.e., under RSD198S) and a second air gap142in second TI116(i.e., under RSD198D). IC structure100also includes a nitride plug244,246extending through each of RSD regions198S,198D, i.e., to plug the air gaps.

In terms of process,FIG.12show a cross-sectional view of forming first air gap240(FIG.11) in first TI112(i.e., under RSD198S), and second air gap242(FIG.11) in second TI116(i.e., second RSD region198D).FIG.12proceeds after the processing shown inFIG.9. Air gaps240,242forming under first and second RSD regions198S,198D may include forming a first vent hole250through first silicon section220and first polysilicon section210, and a second vent hole252through second silicon section222and second polysilicon section212(or through RSD regions198S,198D if already formed in silicon sections220,222). Vent holes250,252may be formed using any now known or later developed process, e.g., forming a patterned mask having small openings matching the location of vent holes250,252, and etching (e.g., a RIE).FIG.12also shows removing a first portion of first TI112under first polysilicon section210through first vent hole250, and removing a second portion of second TI116under second polysilicon section212through second vent hole252. The removing may include etching portions of TIs112,116using, for example, hot ammonia (NH3) and/or hydrochloric acid, through vent holes250,252, as known in the art. Semiconductor layer106may define inner sidewall surface254(shown for right air gap242only for clarity) of each of air gap240,242, and TIs112,116may define lower surface256of each air gap240,242. As shown inFIG.11, sides of first air gap240and second air gap242are aligned to edges of gate120(i.e., spacer126thereof) and channel region124in silicon layer214. After the portions of TIs112,116are removed, an optional thermal oxidation to passivate the air gap semiconductor surfaces may be performed. The removal of the portions of TIs112,116leaves gas in the spaces, e.g., air.

Returning toFIG.11, sealing first and second vent holes250,252(FIG.12) to form/complete first air gap240and second air gap242may include filling the vent holes, creating filled vent holes or plugs244,246. Sealing may be carried out, for example, by depositing a dielectric such as nitride and/or a spacer nitride. The sealing may occur simultaneously with formation of spacer126of gate120. As shown, forming first and second air gaps240,242may include forming a nitride plug244,246extending through first and second RSD regions198S,198D. It is noted that vent holes250,252(FIG.12) have a sufficiently small lateral size (across or into page inFIG.12) compared to eventually formed RSD regions198S,198D (FIG.11), so that sealing them does not adversely impact the electrical properties of RSD regions198S,198D (FIG.11). Forming active device102, including forming gate120, first RSD region198S and second RSD region198D, may be occur thereafter as described relative toFIG.10. Silicide layer130may be formed, as previously described herein. InFIG.11, however, nitride plugs244,246extend through silicide layer130. That is, silicide layer130does not form on nitride plugs244,246, it only forms on first RSD region198S and second RSD region198D.

Embodiments of the disclosure provide IC structure100that uses a lower cost, low resistivity bulk semiconductor substrate104rather than a more expensive, higher resistivity SOI substrate. Despite the lower cost substrate, IC structure100with isolation structure140has better performance characteristics than a device in an SOI substrate, e.g., for radio frequency (RF) switches. For example, IC structure100exhibits better current leakage, harmonic distortion, cross-talk resistance, effective resistivity, effective permittivity, and attenuation, compared to current SOI substrate devices. One example SOI n-type field effect (NFET) RF switch that includes a high resistivity polycrystalline isolation layer exhibits an ‘under trench isolation’ resistance of about 1E6Ω, and a leakage current of approximate 10 micro-Amperes (μA). In contrast, a similar NFET RF switch200employing IC structure100according to embodiments of the disclosure may exhibit an under trench isolation of about 300-400 nanometers (nm), and a leakage current of less than approximately 1.0 μA. RSD regions198S,198D with or without air gaps240,242thereunder may also be employed to further improve performance. The reduction in CDSby air gaps240,242under RSD regions198S,198D may be up to approximately 50%, which can reduce off capacitance (Coff) by up to 25% to approach or match that value in SOI substrates. While air gaps240,242provide this advantage, they are not located under channel region124under gate120, thus eliminating any mechanical stresses caused by that arrangement. Other operational parameters exhibit similar improvements.