Semiconductor device and passive component integration in a semiconductor package

According to one exemplary embodiment, a semiconductor package includes a substrate having lower and upper surfaces. The semiconductor package further includes at least one passive component coupled to first and second conductive pads on the upper surface of the substrate. The semiconductor package further includes at least one semiconductor device coupled to a first conductive pad on the lower surface of the substrate. The at least one semiconductor device has a first electrode for electrical and mechanical connection to a conductive pad external to the semiconductor package. The at least one semiconductor device can have a second electrode electrically and mechanically coupled to the first conductive pad on the lower surface of the substrate.

BACKGROUND OF THE INVENTION

Moreover, the present application is related to issued U.S. Pat. Nos. 7,230,333 and 7,368,325. The respective disclosures in these two patents is hereby incorporated fully by reference into the present application. Further, the present application is related to United States published application number 2008-0066303. The disclosure in this published application is also hereby incorporated fully by reference into the present application.

DEFINITION

In the present application, “group III-V semiconductor” refers to a compound semiconductor that includes at least one group III element and at least one group V element, such as, but not limited to, gallium nitride (GaN), gallium arsenide (GaAs), indium aluminum gallium nitride (InAlGaN), indium gallium nitride (InGaN) and the like. Analogously, “III-nitride refers to a compound semiconductor that includes nitrogen and at least one group III element such as, but not limited to, GaN, AlGaN, InN, InGaN, InAlGaN and the like.”

FIELD OF THE INVENTION

The present invention is generally in the field of semiconductors. More particularly, the invention is in the field of semiconductor packages.

BACKGROUND ART

Power processing circuits, such as DC-DC converters, voltage regulators, and the like, can include one or more semiconductor devices, such as power field effect transistors (FETs), and an integrated circuit (IC) semiconductor die (also referred to simply as an “IC die” in the present application) to control the operation of the semiconductor devices. A power processing circuit, such as a DC-DC converter or voltage regulator, can also include passive components, such as capacitors, resistors, and inductors. However, since circuit board space is typically limited in electronic devices that utilize a power processing circuit, such as a DC-DC converter or voltage regulator, it is desirable to reduce the overall circuit board area consumed by the power processing circuit.

In a conventional arrangement, a power processing circuit, such as a DC-DC converter, a voltage regulator, or the like, including an IC die and one or more semiconductor devices, such as power FETs, can be mounted on an insulative substrate in a semiconductor package. The semiconductor package can, in turn, be mounted on a circuit board, such as a printed circuit board. In order to reduce the overall footprint of the power processing circuit, passive components that are necessary for proper operation of the power processing circuit can be mounted on the circuit board in close proximity to the semiconductor package. However, the conventional arrangement can still consume an undesirable amount of circuit board area.

SUMMARY OF THE INVENTION

Semiconductor device and passive component integration in a semiconductor package, substantially as shown in and/or described in connection with at least one of the figures, and as set forth more completely in the claims.

DETAILED DESCRIPTION OF THE INVENTION

The present invention is directed to semiconductor device and passive component integration in a semiconductor package. The following description contains specific information pertaining to the implementation of the present invention. One skilled in the art will recognize that the present invention may be implemented in a manner different from that specifically discussed in the present application. Moreover, some of the specific details of the invention are not discussed in order not to obscure the invention.

FIG. 1Ashows a top view of an exemplary semiconductor package in accordance with one embodiment of the present invention. Semiconductor package100includes substrate102, IC die104, passive components106,108,110, and112(hereinafter “passive components106through112”), metallic body114, and conductive pads116,118,120, and122(hereinafter “conductive pads116through122”). Semiconductor package100can also include at least one semiconductor device (not shown inFIG. 1A) and additional conductive pads, which are situated on a lower surface of substrate102. Semiconductor package100can also include conductive traces (not shown inFIG. 1A) on upper surface124of substrate102for providing interconnections between IC die104and passive components106through112. Semiconductor package100can be, for example, a package for a power processing circuit, such as a DC-DC converter, a voltage regulator, or the like. In one embodiment, semiconductor package100can be a package for a power stage of a buck converter. It is noted that inFIG. 1A, only conductive pads116through122are specifically discussed herein to preserve brevity.

As shown inFIG. 1A, IC die104, conductive pads116through122, and metallic plate114are situated on upper surface124of substrate102. IC die104can comprise, for example, a controller for controlling semiconductor devices, such as power FETs, situated on a lower surface of substrate102, in an embodiment of the invention. In one embodiment, IC die104can provide drive signals, such pulse width modulation (PWM) drive signals, to semiconductor devices (not shown inFIG. 1A) situated on the lower surface of substrate102in semiconductor package100. IC die104can include temperature sensing circuitry and/or short circuit detection circuitry in an embodiment of the invention. In one embodiment, IC die104may not be utilized. IC die104can include multiple input/output (I/O) electrodes (not shown inFIG. 1A), which can be electrically and mechanically connected to underlying contact pads (not shown inFIG. 1A) situated on upper surface124of substrate102.

Metallic body114, such as a metallic plate, can be provided on upper surface124of substrate102for dissipating heat generated by one or more semiconductor devices situated on the lower surface of substrate102. To provide additional heat dissipation, a heat sink or the like can be thermally coupled to metallic body114. In one embodiment, metallic body114may not be utilized. Metallic body114and conductive pads116through122can comprise, for example, copper, aluminum, or other metal or metal stack. Substrate102can be a laminate substrate and can comprise an insulating material, such as Flame Retardant 4 (FR4). In one embodiment, substrate102can comprise a thermally conductive material, such as aluminum oxide (Al2O3) or the like. In another embodiment, substrate102can comprise a ceramic material. Substrate102can also include multiple conductive vias, which are not shown inFIG. 1A.

Also shown inFIG. 1A, passive components106through112are situated on upper surface124of substrate102and can be electrically and mechanically coupled to conductive pads, such as conductive pads116through122. Passive components106through112can be, for example, surface mount components. In one embodiment, one or more of passive components106through112may not be directly electrically and mechanically coupled to conductive pads on upper surface124of substrate102. For example, passive component112can be electrically and mechanically connected to conductive pads116and118and passive component106can be electrically and mechanically connected to conductive pads120and122. Passive components106through112can each be electrically and mechanically connected to a pair of conductive pads on upper surface124by utilizing a conductive adhesive, such as solder, a conductive epoxy, or the like.

Passive components106through112can each be, for example, a capacitor, a resistor, an inductor, a diode, or other type of passive component. In an embodiment of the invention, passive components106through112can each be a bypass capacitor, a filter capacitor, a coupling capacitor, an output capacitor, or other type of capacitor. Each of passive components106through112can be electrically coupled to conductive vias (not shown inFIG. 1A) in substrate102or to I/O electrodes of IC die104by, for example, conductive traces (not shown inFIG. 1A) situated on upper surface124of substrate102. Passive components106through112can be utilized in a circuit, such as a power processing circuit, that includes IC die104and at least one semiconductor device (not shown inFIG. 1A) situated on the bottom surface of substrate102. For example, passive components106through112, IC die104, and two semiconductor devices situated on the bottom surface of substrate102can be utilized in a DC-DC converter.

FIG. 1Bshows a bottom view of semiconductor package100inFIG. 1A. InFIGS. 1A and 1B, like numerals identify like features. In addition to the features shown inFIG. 1A, semiconductor package100also includes semiconductor dies126and128and conductive pads130,132,134, and136(hereinafter “conductive pads130through136”), which are situated on lower surface138of substrate102. Semiconductor device126includes source electrode140, gate electrode142, and a drain electrode (not shown inFIG. 1B) and semiconductor device128includes source electrode144, gate electrode146, and a drain electrode (not shown inFIG. 1B). It is noted that inFIG. 1B, only conductive pads130through136are specifically discussed herein to preserve brevity.

As shown inFIG. 1B, semiconductor devices126and128are situated on lower surface138of substrate102and can each be, for example, a power semiconductor device. For example, semiconductor devices126and128can each be a power FET, such as a power MOSFET. In one embodiment of the invention, semiconductor devices126and128can each be an isolated gate bipolar transistor (IGBT). In one embodiment, semiconductor devices126and128can each be a group III-V semiconductor device, such as a III-nitride device. In an embodiment of the invention, semiconductor devices126and128can each be a gallium nitride (GaN) device or other III-nitride device.

Also shown inFIG. 1B, source electrode140and gate electrode142of semiconductor device126are situated on surface148of semiconductor device126and a drain electrode (not shown inFIG. 1B) is situated on an opposite surface of semiconductor device126. Further shown inFIG. 1B, source electrode144and gate electrode146of semiconductor device128are situated on surface150of semiconductor device128and a drain electrode (not shown inFIG. 1B) is situated on an opposite surface of semiconductor device128. In an embodiment in which semiconductor devices126and128are each an IGBT having base, emitter, and collector electrodes, the base and emitter electrodes can be situated on one surface of the semiconductor device and the collector electrode can be situated on an opposite surface of the semiconductor device.

Semiconductor devices126and128can be electrically and mechanically connected to respective conductive pads (not shown inFIG. 1B) situated on lower surface138of substrate102. For example, the drain electrodes (not shown inFIG. 1B) of semiconductor devices126and128can be electrically and mechanically connected to respective conductive pads on lower surface138of substrate102by using a conductive adhesive, such as solder, a conductive epoxy, or the like. Source electrode140and gate electrode142of semiconductor device126can be readied for connection to corresponding conductive pads on a circuit board (not shown inFIG. 1B) using a conductive adhesive such as solder, conductive epoxy, or the like. For example, source electrode140and gate electrode142can be rendered solderable so that they can be electrically and mechanically connected to respective conductive pads on a circuit board by utilizing solder.

Similarly, source electrode144and gate electrode146of semiconductor device128can be readied for connection to corresponding conductive pads on a circuit board utilizing a conductive adhesive such as solder, conductive epoxy, or the like. In an embodiment in which semiconductor devices126and128each comprise a GaN device, the backside of the GaN device can be readied for electrical and mechanical connection to a corresponding conductive pad on a circuit board using a conductive adhesive such as solder, conductive epoxy, or the like. In an embodiment in which semiconductor package100is utilized as a power stage of a buck converter, semiconductor device126can be utilized as a control switch while semiconductor device128can be utilized as a synchronous switch in the buck converter.

Also shown inFIG. 1B, conductive pads130through136are situated on lower surface138of substrate102. InFIG. 1B, conductive pads, such as conductive pads130,132, and134, extend along the perimeter of substrate102. In another embodiment, conductive pads situated on lower surface138of substrate102may extend along only a portion of the perimeter of the substrate. Conductive pads130through136can comprise the same material as conductive pads116through122(shown inFIG. 1A) on upper surface124of substrate102.

FIG. 1Cshows a cross-sectional view of semiconductor package100across line2C-2C inFIG. 1A. InFIGS. 1A,1B and1C, like numerals identify like features. In addition to the features shown inFIGS. 1A and 1B, semiconductor package100further includes conductive pads152,154, and156. As shown inFIG. 1C, conductive pads152and154are situated on upper surface124of substrate102and conductive pad156is situated on lower surface138of substrate102. Conductive pads152,154, and156can comprise the same material as conductive pads116through122shown inFIG. 1A. Also shown inFIG. 1C, IC die104includes I/O electrodes158and160, which are electrically and mechanically coupled to respective contact pads152and154by conductive adhesive162, which can be solder, a conductive epoxy, or the like.

Conductive pads on upper surface124of substrate102, such as conductive pads152and154, to which I/O electrodes of IC die104, such as I/O electrodes158and160, are electrically and mechanically connected, can be electrically coupled to respective contact pads, such as contact pads130and132, on lower surface138of substrate102. For example, conductive vias (not shown inFIG. 1C) extending from upper surface124to lower surface138of substrate102can be utilized to provide a conductive path between the upper and lower surfaces of the substrate. Thus, each I/O electrode of IC die104can be electrically coupled from a conductive pad on upper surface124of substrate102to a conductive pad on lower surface138of substrate102by a conductive via extending through substrate102. More specifically, conductive traces or the like on lower surface138of substrate102can be utilized to provide an electrical connection between conductive vias (not shown inFIG. 1C) in substrate102and conductive pads on lower surface138of substrate102.

Conductive pads, such as conductive pads130through136, on lower surface138of substrate102can be utilized to provide external connectivity to I/O electrodes, such as I/O electrodes158and160, on IC die104. For example, a conductive pad on lower surface138can be utilized to supply power to IC die104and another conductive pad on lower surface138can be utilized to provide a ground connection to IC die104. For example, a control signal from IC die104can be routed to gate electrode142of semiconductor device126by utilizing a conductive pad on lower surface138of substrate102and conductive pads and traces in an external circuit board (not shown inFIG. 1C).

Further shown inFIG. 1C, drain electrode164of semiconductor device126is situated on surface166of semiconductor device126and also situated on conductive pad156, which is situated on lower surface138of substrate102. Drain electrode164can be electrically and mechanically connected to conductive pad156by utilizing a conductive adhesive, such as solder, a conductive epoxy, or the like. Although not shown inFIG. 1C, the drain electrode of semiconductor device128can be electrically and mechanically coupled to a conductive pad similar to conductive pad156on lower surface138of substrate102.

Also shown inFIG. 1C, passive component112is situated on conductive pads116and118on top surface124of substrate102. Passive component112can be electrically and mechanically coupled to conductive pads116and118by utilizing a conductive adhesive, such as solder, a conductive epoxy, or the like. Passive components, such as passive component112, can be integrated with IC die104and semiconductor devices, such as semiconductor device126, in semiconductor package100to provide an integrated circuit, such as a power converter, a voltage regulator, or other power processing circuit. Further shown inFIG. 1C, solder balls168and169are situated on respective conductive pads130and134. Solder balls, such as solder balls168and169, can be formed on conductive pads, such as conductive pads130and134, situated on lower surface138of substrate102to enable the conductive pads to be electrically and mechanically coupled to corresponding conductive pads on a circuit board (not shown inFIG. 1C) or the like. In one embodiment, a conductive epoxy or the like can be utilized in place of solder balls168and169.

By integrating passive components, such as passive component112and passive components106,108, and110(shown inFIG. 1A), with semiconductor devices, such as semiconductor device126, and IC die104on substrate102, short conductive traces can be provided to interconnect the passive components with the semiconductor devices and the IC die. As a result, parasitics, such as control loop parasitics, can be advantageously reduced in a power processing circuit, such as a DC-DC converter or the like. Also, passive components, such as decoupling capacitors, can be placed close to a voltage input node of a power processing circuit, such as a DC-DC converter, thereby advantageously improving transient response and reducing loss.

FIG. 1Dshows a top view of semiconductor package100with IC die104and underlying conductive pads removed to show exemplary conductive vias.FIG. 1Dcorresponds toFIG. 1Awith IC die104removed. InFIG. 1D, conductive pads underlying IC die104, such as conductive pads252and254(shown inFIG. 1C), have also been removed to show conductive vias, such as conductive vias103,105, and107. Thus, in addition to the features shown inFIGS. 1A,1B, and1C, semiconductor package100further includes conductive vias, such as conductive vias103,105, and107. It is noted that inFIG. 1D, only conductive vias103,105, and107are specifically discussed herein to preserve brevity.

As shown inFIG. 1D, conductive vias103,105, and107are situated in a region of substrate102underlying IC die104(shown inFIGS. 1A and 1C), which is indicated by dashed line109. Conductive vias103,105, and107can be formed, for example, by etching forming via openings that extend through substrate102and filling the via openings with a conductive material, such as tungsten or other metal or metal stack. Conductive vias, such as conductive vias103,105, and107, can also serve as thermal vias for dissipating heat generated by IC die104and semiconductor devices, such as semiconductor device126. Conductive vias103,105, and107can be each be coupled by a conductive pad, such as conductive pad152or154(shown inFIG. 1C), to an I/O electrode, such as I/O electrode158or160(shown inFIG. 1C) on IC die104. Conductive vias, such as conductive vias103,105, and107can be electrically connected to conductive pads on lower surface138of substrate102, such as conductive pads130through136(shown inFIG. 1B).

Thus, conductive vias, such as conductive vias103,105, and107can provide electrically connectivity between I/O electrodes on IC die104and conductive pads on lower surface138of substrate102. Also, other conductive vias (not shown inFIG. 1D) can be formed in substrate102to provide electrically connectivity between passive devices, such as passive devices106through112, and semiconductor device, such as semiconductor devices126and128(shown inFIG. 1B), situated on lower surface138of substrate102.

FIG. 2shows a cross-sectional view of an exemplary semiconductor package readied for mounting on an exemplary circuit board in accordance with one embodiment of the present invention. InFIG. 2, semiconductor package200corresponds to semiconductor package100inFIGS. 1A through 1D. In particular, the cross-sectional view of semiconductor package200corresponds to the cross-sectional view of semiconductor package100inFIG. 1C. Thus, inFIG. 2, substrate202, IC die204, passive component212, metallic body214, conductive pads216,218,230,234,252,254, and256, upper surface224, lower surface238, source electrode240, gate electrode242, surfaces248and266, conductive adhesive262, and solder balls268and269correspond, respectively, to substrate102, IC die104, passive component112, metallic body114, conductive pads116,118,130,134,152,154, and156, upper surface124, lower surface138, source electrode140, gate electrode142, surfaces148and166, conductive adhesive162, and solder balls168and169inFIG. 1C.

InFIG. 2, circuit board270, which can be a printed circuit board, includes conductive pads272,274,276, and278, which are situated on upper surface280of circuit board270. Conductive pad276can be a conductive source pad for receiving source electrode240of semiconductor device226and conductive pad278can be a conductive gate pad for receiving gate electrode242of semiconductor device226.

As shown inFIG. 2, mounting semiconductor package200onto circuit board270can include electrically and mechanically coupling conductive pads230and234on lower surface238of substrate202to corresponding conductive pads272and274on upper surface280of circuit board270by using respective solder balls268and270on conductive pads230and234and solder paste284, which can be applied to conductive pads272and274of circuit board270. Mounting semiconductor package200onto circuit board270can further include electrically and mechanically coupling source electrode240and gate electrode242of semiconductor device226to respective conductive pads276and278of circuit board270by using conductive adhesive263, which is situated on source electrode240and gate electrode242. Conductive adhesive263can comprise solder, a conductive epoxy, or the like. Conductive adhesive263can also be applied to conductive pads276and278of circuit board270prior to mounting semiconductor package100onto circuit board270.

Circuit board270can also include conductive traces (not shown inFIG. 2) to provide electrically connectivity between conductive pads272,274,276, and278on upper surface280of circuit board270. Thus, for example, a control signal from IC die204can be routed from a conductive pad, such as conductive pad230, on lower surface238of substrate202to gate electrode242of semiconductor device226through conductive pads and a conductive trace on circuit board270.

Thus, as discussed above, an embodiment of the invention provides a semiconductor package wherein passive components, an IC die, and at least one semiconductor device (for example, two or more semiconductor devices) can be integrated on a substrate. In contrast, in a conventional arrangement, passive components can be situated adjacent to a semiconductor package on a circuit board. By integrating passive components with an IC die and semiconductor devices in a semiconductor package, an embodiment of the invention advantageously provides a semiconductor package that can consume less area on a circuit board compared to the conventional arrangement, wherein the passive components are situated adjacent to the semiconductor package. Also, by integrating passive components on a substrate with an IC die and semiconductor devices, an embodiment of the invention can advantageously provide reduced parasitics as a result of the proximity of the passive components to the IC die and semiconductor devices.

Additionally, an embodiment of the invention provides a semiconductor package including a metallic body situated on an upper surface of a substrate and at least one semiconductor device (for example, two or more semiconductor devices) electrically and mechanically coupled to respective conductive pads on a lower surface of the substrate. As a result, an embodiment of the invention can utilize the metallic body on the upper surface of the substrate to provide dissipation of heat generated by the at least one semiconductor device mounted on conductive pads on the lower surface of the substrate. Furthermore, additional heat dissipation can be provided by attaching a heat sink to the metallic body.