Non-volatile flash memory device having at least two different channel concentrations and method of fabricating the same

In a non-volatile flash memory device, and a method of fabricating the same, the device includes a semiconductor substrate, a source region and a drain region disposed in the semiconductor substrate to be spaced apart from each other, a tunneling layer pattern, a charge trap layer pattern and a shielding layer pattern, which are sequentially stacked on the semiconductor substrate between the source region and the drain region, adjacent to the source region, a first channel region disposed in the semiconductor substrate below the tunneling layer pattern, a gate insulating layer disposed on the semiconductor substrate between the drain region and the first channel region, a second channel region disposed in the semiconductor substrate below the gate insulating layer, a concentration of the second channel region being different from that of the first channel region, and a gate electrode covering the shielding layer pattern and the gate insulating layer.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor memory device and method of fabricating the same. More particularly, the present invention relates to a non-volatile flash memory device having at least two different channel concentrations and a method of fabricating the same.

2. Description of Related Art

A feature of non-volatile memory devices is that previous data are maintained even when power is not supplied, unlike volatile memory devices. Recently, non-volatile memories such as a ferroelectric random access memory (FRAM), an erasable and programmable read only memory (EPROM), and electrically erasable and programmable read only memory (EEPROM) have been publicized. EPROM and EEPROM store charges on a floating gate store memorize data according to a variation of a threshold voltage depending on whether or not the charges exist. The EEPROM, which is a type of flash memory, erases data in the entire memory cell array or divides the memory cell array into blocks and erases the data in blocks. Non-volatile memory devices such as flash memories are widely used in file systems, memory cards, portable devices, and other applications.

A flash memory cell is divided into two types: a floating gate type and a floating trap type. A polysilicon-oxide-nitride-oxide-silicon (SONOS) structure is well known as a floating trap type device.

A floating gate type device includes a mechanism that stores charges on a floating gate, whereas a SONOS device includes a mechanism that stores charges in traps in a silicon nitride layer. The floating gate type device has a limitation in reducing a cell size and has to use a high voltage for programming and erasing. The SONOS device, however, may satisfy a demand for low power and low voltage and achieve high integration.

FIG. 1Aillustrates a cross-sectional view of a conventional non-volatile flash memory device.FIG. 1Bis a graph showing a variation of threshold voltage depending on program and erase operations of the conventional non-volatile flash memory device shown inFIG. 1A.

Referring toFIG. 1A, an isolation layer12, which defines an active region, is disposed on a semiconductor substrate10. Source and drain regions35, which are separated by a channel region17, are disposed in the active region. The channel region17includes a first region L1and a second region L2. A tunneling layer20, a charge trap layer22, and a shielding layer30aare disposed on the first region L1. A gate insulating layer30bis disposed on the second region L2. The shielding layer30aand the gate insulating layer30bare simultaneously formed of the same material layer and are connected. A gate electrode32covers both the shielding layer30aand the gate insulating layer30b.

Referring toFIG. 1B, an x-axis denotes a gate length Lgateof the conventional non-volatile flash memory device ofFIG. 1A, and a y-axis denotes a threshold voltage Vth. In order to program the non-volatile flash memory device ofFIG. 1A, electrons pass through the tunneling layer20by a channel-hot electron injection (CHEI) mechanism or a Fowler-Nordheim (FN) tunneling mechanism and are trapped in the charge trap layer22. A threshold voltage Vthin the first region L1increases due to the trapped charges. The non-volatile flash memory device varies in threshold voltage according to an amount of trapped electrons and has an “on” level or an “off” level according to a variation of the threshold voltage.

During an erase operation, the trapped electrons are detrapped by a hot hole injection mechanism. Thus, a threshold voltage in the first region L1decreases. However, the second region L2has a fixed threshold voltage due to the gate insulating layer30b. Thus, a sensing margin during program and erase operations is determined by a variation SM1of the threshold voltage, as shown inFIG. 1B. When a threshold voltage in the second region L2is reduced by ΔVth, the sensing margin increases, i.e., SM2. One method of reducing the threshold voltage in the second region L2is to reduce a thickness of the gate insulating layer30b. However, since the gate insulating layer30bis formed at the same time as the shielding layer30a, reducing the thickness of the shielding layer30adeteriorates cell retention characteristics. Thus, there is a need for research into reducing the threshold voltage in the second region L2while maintaining the thickness of the gate insulating layer30b.

SUMMARY OF THE INVENTION

The present invention is therefore directed to a non-volatile flash memory device having at least two different channel concentrations and a method of fabricating the same, which substantially overcome one or more of the problems due to the limitations and disadvantages of the related art.

It is a feature of an embodiment of the present invention to provide a non-volatile flash memory device, and a method of fabricating the same, which reduces a threshold voltage during an erase operation while maintaining a thickness of a gate insulating layer thereof.

It is another feature of an embodiment of the present invention to provide a non-volatile flash memory device, and a method of fabricating the same, which can increase a variation of a threshold voltage depending on program and erase operations, thereby increasing a sensing margin.

At least one of the above and other features and advantages of the present invention may be realized by providing a non-volatile flash memory device including a semiconductor substrate, a source region and a drain region disposed in the semiconductor substrate to be spaced apart from each other, a tunneling layer pattern, a charge trap layer pattern and a shielding layer pattern, which are sequentially stacked on the semiconductor substrate between the source region and the drain region, adjacent to the source region, a first channel region disposed in the semiconductor substrate below the tunneling layer pattern, a gate insulating layer disposed on the semiconductor substrate between the drain region and the first channel region, a second channel region disposed in the semiconductor substrate below the gate insulating layer, a concentration of the second channel region being different from that of the first channel region, and a gate electrode covering the shielding layer pattern and the gate insulating layer.

In this device, an impurity concentration of the second channel region may be less than that of the first channel region.

At least one of the above and other features and advantages of the present invention may be realized by providing a non-volatile flash memory device including a semiconductor substrate, a source region and a drain region disposed in the semiconductor substrate to be spaced apart from each other, tunneling layer patterns, charge trap layer patterns and shielding layer patterns, which are sequentially stacked and spaced apart from each other on the semiconductor substrate between the source region and the drain region, one of the tunneling layer patterns, charge trap layer patterns and shielding layer patterns being adjacent to the source region and one of the tunneling layer patterns, charge trap layer patterns and shielding layer patterns being adjacent to the drain region, first channel regions disposed in the semiconductor substrate below the tunneling layer patterns, a gate insulating layer disposed on the semiconductor substrate between the first channel regions, a second channel region disposed in the semiconductor substrate below the gate insulating layer, a concentration of the second channel region being different from that of the first channel regions, and a gate electrode covering the shielding layer patterns and the gate insulating layer.

In this device, an impurity concentration of the second channel region may be less than that of the first channel regions.

At least one of the above and other features and advantages of the present invention may be realized by providing a method of fabricating a non-volatile flash memory device including defining a cell active region in a semiconductor substrate, performing a first ion implantation into the cell active region to form a first channel region, sequentially stacking a tunneling layer, a charge trap layer and a passivation layer on the semiconductor substrate having the first channel region, forming a first photoresist pattern on the semiconductor substrate having the passivation layer, the first photoresist pattern exposing a portion of the passivation layer on the first channel region, performing a second ion implantation using the first photoresist pattern as a mask to form a second channel region in the semiconductor substrate, sequentially patterning the passivation layer, the charge trap layer and the tunneling layer using the first photoresist pattern as a mask, and removing the first photoresist pattern.

The method may further include defining a peripheral circuit active region adjacent to the cell active region while defining the cell active region in the semiconductor substrate. Forming the cell active region and the peripheral circuit active region may be performed at the same time. The method may further include forming a preliminary peripheral circuit channel region in the peripheral circuit active region after forming the first channel region, wherein forming the first photoresist pattern includes forming a first photoresist pattern, which exposes a portion of the passivation layer on the first channel region and the preliminary peripheral circuit channel region, and forming the second channel region includes performing the second ion implantation using the first photoresist pattern as a mask to form the peripheral circuit channel region and the second channel region in the semiconductor substrate.

At least one of the above and other features and advantages of the present invention may be realized by providing a method of fabricating a non-volatile flash memory device including defining an active region in a semiconductor substrate, performing a first ion implantation into the active region to form a first channel region, sequentially stacking a tunneling layer, a charge trap layer and a passivation layer on the semiconductor substrate having the first channel region, forming a first photoresist pattern on the semiconductor substrate having the passivation layer, the first photoresist pattern exposing a portion of the passivation layer on the first channel region, sequentially patterning the passivation layer, the charge trap layer and the tunneling layer using the first photoresist pattern as a mask, performing a second ion implantation using the first photoresist pattern as a mask to form a second channel region in the semiconductor substrate, and removing the first photoresist pattern.

In either of these methods, forming the first photoresist pattern may include forming an opening that crosses over a center of the cell active region, wherein the first channel region is divided into a pair of first sub channel regions by the second channel region.

In either of these methods, the first photoresist pattern may be formed to cover one end of the cell active region, and the first and second channel regions may be formed to be adjacent to each other in the cell active region.

Either of these methods may further include, after removing the first photoresist pattern, sequentially forming an insulating layer and a gate electrode layer on the semiconductor substrate, and sequentially patterning the gate electrode layer, the insulating layer, the passivation layer, the charge trap layer, and the tunneling layer to form a tunneling layer pattern, a charge trap layer pattern and a shielding layer pattern, respectively, which are sequentially stacked on the pair of first sub channel regions, the shielding layer pattern being composed of the insulating layer and the passivation layer, and forming a gate insulating layer on the second channel region while forming a gate electrode covering the shielding layer pattern and the gate insulating layer.

Either of these methods may further include performing a third ion implantation using the gate electrode as a mask to form a source region and a drain region in the cell active region adjacent to one of the pair of first sub channel regions, respectively.

Forming the second channel region may include forming the second channel region to have an impurity concentration less than that of the first channel region.

Performing the second ion implantation may include using an impurity conductivity type opposite to that used in the first ion implantation.

At least one of the above and other features and advantages of the present invention may be realized by providing a method of fabricating a non-volatile flash memory device including defining a cell region and a peripheral circuit region in a semiconductor substrate, forming a cell active region and a peripheral circuit active region in the cell region and the peripheral circuit region, respectively, performing a first ion implantation into the cell active region to form a first channel region, performing a second ion implantation into the peripheral circuit active region to form a peripheral circuit channel region, sequentially stacking a tunneling layer, a charge trap layer and a passivation layer on the semiconductor substrate, forming a first photoresist pattern on the semiconductor substrate having the passivation layer, the first photoresist pattern covering a portion of the passivation layer on the first channel region, sequentially patterning the passivation layer, the charge trap layer and the tunneling layer using the first photoresist pattern as a mask, removing the first photoresist pattern, forming a second photoresist pattern covering the passivation layer and the peripheral circuit region, performing a third ion implantation using the second photoresist pattern as a mask to form a second channel region in the cell active region, and removing the second photoresist pattern.

Forming the first photoresist pattern may include forming an opening that crosses over a center of the cell active region and exposes the peripheral circuit active region, wherein the first channel region is divided into a pair of first sub channel regions by the second channel region.

The first photoresist pattern may be formed to cover one end of the cell active region and expose the peripheral circuit active region, and the first and second channel regions are formed to be adjacent to each other in the cell active region.

The method may further include, after removing the second photoresist pattern, sequentially forming an insulating layer and a gate electrode layer on the semiconductor substrate, and sequentially patterning the gate electrode layer, the insulating layer, the passivation layer, the charge trap layer, and the tunneling layer to form a tunneling layer pattern, a charge trap layer pattern and a shielding layer pattern, respectively, which are sequentially stacked on the pair of first sub channel regions, the shielding layer pattern being composed of the insulating layer and the passivation layer, and forming a gate insulating layer on the second channel region while forming a gate electrode covering the shielding layer pattern and the gate insulating layer.

The method may further include performing a fourth ion implantation using the gate electrode as a mask to form a source region and a drain region in the cell active region adjacent to the pair of first sub channel regions.

At least one of the above and other features and advantages of the present invention may be realized by providing a method of fabricating a non-volatile flash memory device including defining a cell region and a peripheral circuit region in a semiconductor substrate, forming a cell active region and a peripheral circuit active region in the cell region and the peripheral circuit region, respectively, performing a first ion implantation into the cell active region to form a first channel region, performing a second ion implantation into the peripheral circuit active region to form a peripheral circuit channel region, sequentially stacking a tunneling layer, a charge trap layer and a passivation layer on the semiconductor substrate, forming a first photoresist pattern covering a portion of the passivation layer on the cell active region and the peripheral circuit region, performing a third ion implantation using the first photoresist pattern as a mask to form a second channel region in the cell active region, removing the first photoresist pattern, forming a second photoresist pattern covering a top surface of the first channel region on the semiconductor substrate having the passivation layer, sequentially patterning the passivation layer, the charge trap layer, and the tunneling layer using the second photoresist pattern as a mask, and removing the second photoresist pattern.

Forming the first photoresist pattern may include forming an opening that crosses over a center of the cell active region and covers the entire peripheral circuit active region, wherein the first channel region is divided into a pair of first sub channel regions by the second channel regions.

The first photoresist pattern may be formed to cover one end of the cell active region and cover the entire peripheral circuit active region, and the first and second channel regions are formed to be adjacent to each other in the cell active region.

The method may further include, after removing the second photoresist pattern, sequentially forming an insulating layer and a gate electrode layer on the semiconductor substrate, and sequentially patterning the gate electrode layer, the insulating layer, the passivation layer, the charge trap layer, and the tunneling layer to form a tunneling layer pattern, a charge trap layer pattern and a shielding layer pattern, respectively, which are sequentially stacked on the pair of first sub channel regions, the shielding layer pattern being composed of the insulating layer and the passivation layer, and forming a gate insulating layer on the second channel region while forming a gate electrode covering the shielding layer pattern and the gate insulating layer.

The method may further include performing a fourth ion implantation using the gate electrode as a mask to form a source region and a drain region in the cell active region adjacent to the pair of first sub channel regions, respectively.

In either of these methods, forming the second channel region may include forming the second channel region to have an impurity concentration less than that of the first channel region.

In either of these methods, performing the third ion implantation may include using an impurity conductivity type opposite to that used in the first ion implantation.

DETAILED DESCRIPTION OF THE INVENTION

Korean Patent Application No. 2004-45142, filed on Jun. 17, 2004, in the Korean Intellectual Property Office, and entitled: “Non-Volatile Flash Memory Device Having At Least Two Different Channel Concentrations and Methods of Fabricating the Same,” is incorporated by reference herein in its entirety.

FIGS. 2A through 2Eillustrate cross-sectional views of stages in a method of fabricating a non-volatile flash memory device according to a first embodiment of the present invention.

Referring toFIG. 2A, a cell region C and a peripheral circuit region P are defined in a semiconductor substrate210. An isolation layer212is formed in the cell region C and the peripheral circuit region P. The isolation layer212may be formed by a trench isolation method. Impurity ions are implanted into an active region of the cell region C to form a first channel region217. Impurity ions are then implanted into an active region of the peripheral circuit region P to form a preliminary peripheral circuit channel region215. The preliminary peripheral circuit channel region215is formed with a different concentration from that which will be finally required of a peripheral circuit channel region. That is, a concentration of the preliminary peripheral circuit channel region215is determined in consideration of a concentration variation that will result from a subsequent ion implantation process.

A tunneling layer220, a charge trap layer222and a passivation layer225are sequentially formed on the semiconductor substrate210. The tunneling layer220may be formed of a silicon oxide layer or a silicon oxynitride (SiON) layer and may be formed by a thermal oxidation process. The charge trap layer222may be formed of a high-k dielectric layer. In particular, the charge trap layer222may be formed of a silicon nitride layer. The passivation layer225, which may be formed of a silicon oxide layer or a silicon oxynitride layer, protects the charge trap layer222during a subsequent process. The charge trap layer222and the passivation layer225may be formed by a chemical vapor deposition (CVD) method or an atomic layer deposition (ALD) method.

Referring toFIG. 2B, a photoresist layer is formed on the semiconductor substrate having the passivation layer225. The photoresist layer is patterned to form a photoresist pattern227covering a portion of the passivation layer225on the first channel region217. An ion implantation process is then performed using the photoresist pattern227as a mask. Impurities used for the ion implantation process preferably have a conductivity type opposite to that of the first channel region217. As a result, a channel concentration of the preliminary peripheral circuit channel region215changes due to the ion implantation process. Thus, the preliminary peripheral circuit channel region215becomes a peripheral circuit channel region215a. At the same time, a portion of the first channel region217exposed to the ion implantation process becomes a second channel region217a, which has a channel concentration reduced by the implantation of the opposite conductivity type impurities.

Referring toFIG. 2C, the passivation layer225, the charge trap layer222and the tunneling layer220are sequentially patterned using the photoresist pattern227as a mask. As a result, a patterned passivation layer225a, a patterned charge trap layer222a, and a patterned tunneling layer220aare formed and top surfaces of the peripheral circuit region P and the second channel region217aare exposed.

Referring toFIG. 2D, the photoresist pattern227is removed. Then, a cleaning process is performed for a subsequent deposition process. At this time, a part or an entirety of the patterned passivation layer225amay be etched. Thereafter, an insulating layer230and a gate electrode layer232are sequentially formed on the semiconductor substrate210. The insulating layer230may be formed of an oxide layer and may be formed by a CVD method. The gate electrode layer232may be formed of a polysilicon layer or a metal layer.

Referring toFIG. 2E, the gate electrode layer232, the insulating layer230, the patterned charge trap layer222a, and the patterned tunneling layer220aare sequentially patterned. As a result, a tunneling layer pattern220b, a charge trap layer pattern222band a shielding layer pattern230a, which are sequentially stacked, are formed on the first channel region217. Here, the shielding layer pattern230ais composed of the insulating layer230. When a part of the patterned passivation layer225aremains, the shielding layer pattern230ais composed of the insulating layer230and the remaining patterned passivation layer225a. At the same time, a gate insulating layer230bis formed on the second channel region217a, and a gate electrode232ais formed to cover both the shielding layer230aand the gate insulating layer230b. The first channel region217, the tunneling layer pattern220b, the charge trap layer pattern222b, the shielding layer pattern230a, and the gate electrode232aconstitute a first gate region. The second channel region217a, the gate insulating layer230band the gate electrode232aconstitute a second gate region.

Also at the same time, a peripheral circuit gate insulating layer230cand a peripheral circuit gate electrode232b, which are sequentially stacked on the peripheral circuit channel region215a, are formed in the peripheral circuit region P. A thickness of the peripheral circuit gate insulating layer230cdepends on additional photolithography/etching/oxidation processes to be suitable for an operating voltage of peripheral circuits.

Thereafter, an ion implantation process is performed using the gate electrode232aas a mask. As a result, a source region S1and a drain region D1may be formed in the cell active region adjacent to the tunneling layer pattern220band the gate insulating layer230b, respectively. Also, an ion implantation process is performed using the peripheral circuit gate electrode232bas a mask. As a result, a source region S2and a drain region D2are formed in the peripheral circuit active region adjacent to the peripheral circuit gate electrode232b.

The non-volatile flash memory device formed by the above described method includes two channel regions217and217a, which have different impurity concentrations, formed between the source and drain regions S1and D1. Thus, it is possible to independently vary a threshold voltage in the first gate region and the second gate region according to the concentrations of the two channel regions217and217a. In particular, an amount of the on-cell current in the second gate region may be increased by making an impurity concentration of the second channel region217aless than that of the first channel region217. Thus, a threshold voltage in the second gate region is reduced. As a result, as described inFIG. 1B, a sensing margin of “on” or “off” operations of the non-volatile flash memory device may be increased by increasing a variation SM2of a threshold voltage during program and erase operations of the non-volatile flash memory device.

FIGS. 3A and 3Billustrate cross-sectional views of stages in a method of fabricating a non-volatile flash memory device according to a second embodiment of the present invention.

Referring toFIG. 3A, as described in connection withFIG. 2A, the cell region C and the peripheral circuit region P are defined in the semiconductor substrate210. The isolation layer212is formed in the cell region C and the peripheral circuit region P. The first channel region217and the preliminary peripheral circuit channel region215are formed in the semiconductor substrate210. The tunneling layer220, the charge trap layer222, and the passivation layer225are sequentially formed on the semiconductor substrate210. Then, a photoresist layer is formed on the semiconductor substrate having the passivation layer225. The photoresist layer is patterned to form the photoresist pattern227covering a portion of the passivation layer225on the first channel region217.

Referring toFIG. 3B, the passivation layer225, the charge trap layer222and the tunneling layer220are sequentially patterned using the photoresist pattern227as a mask. As a result, the patterned passivation layer225a, the patterned charge trap layer222aand the patterned tunneling layer220aare formed, and the peripheral circuit region P and a portion of the top surface of the first channel region217are exposed. Here, a portion of the tunneling layer220that is not etched may be used as a buffer layer A.

Subsequently, an ion implantation process is performed using the photoresist pattern227as a mask. Here, an impurity conductivity type is preferably opposite to an impurity conductivity type of the first channel region217. As a result, the preliminary peripheral circuit channel region215has a channel concentration varied by the ion implantation and thus becomes the peripheral circuit channel region215a, and a portion of the first channel region217that is exposed to the ion implantation becomes the second channel region217a, which has a channel concentration reduced by the implantation of the opposite conductivity type impurities.

Subsequent processes are substantially similar to those described in connection withFIGS. 2D and 2Eand will not be repeated. The buffer layer A is removed during the cleaning process ofFIG. 2D.

FIGS. 4A through 4Eillustrate cross-sectional views of stages in a method of fabricating a non-volatile flash memory device according to a third embodiment of the present invention.

Referring toFIG. 4A, a cell region C and a peripheral circuit region P are defined in a semiconductor substrate410. An isolation layer412is formed in the cell region C and the peripheral circuit region P. The isolation layer412may be formed by a trench isolation method. Impurity ions are implanted into an active region of the cell region C to form a first channel region417. Impurity ions are then implanted into an active region of the peripheral circuit region P to form a peripheral circuit channel region415.

A tunneling layer420, a charge trap layer422and a passivation layer425are sequentially formed on the semiconductor substrate410. The tunneling layer420may be formed of a silicon oxide layer or a silicon oxynitride (SiON) layer and may be formed by a thermal oxidation process. The charge trap layer422may be formed of a high-k dielectric layer. In particular, the charge trap layer422may be formed of a silicon nitride layer. The passivation layer425, which may be formed of a silicon oxide layer or a silicon oxynitride layer, protects the charge trap layer422during a subsequent process. The charge trap layer422and the passivation layer425may be formed by a CVD method or an ALD method.

Referring toFIG. 4B, a first photoresist layer is formed on the semiconductor substrate having the passivation layer425. The first photoresist layer is patterned to form a first photoresist pattern427covering a portion of the passivation layer425on the first channel region417.

The passivation layer425, the charge trap layer422and the tunneling layer420are sequentially patterned using the first photoresist pattern427as a mask. As a result, a patterned passivation layer425a, a patterned charge trap layer422a, and a patterned tunneling layer420aare formed, and the peripheral circuit region P and a portion of the top surface of the first channel region417are exposed. If, however, a portion of the tunneling layer420is not etched, the top surface of the first channel region417is not exposed. Rather, the tunneling layer420is exposed and may be used as the buffer layer A.

Referring toFIG. 4C, the first photoresist pattern427is removed and a second photoresist layer is formed over the semiconductor substrate410. The second photoresist layer is patterned to form a second photoresist pattern428covering the peripheral circuit region P and the patterned passivation layer425a. An ion implantation process is then performed using the second photoresist pattern428as a mask. Impurities used for the ion implantation process preferably have a conductivity type opposite to that of the first channel region417. As a result, a portion of the first channel region417, which is exposed to the ion implantation, becomes a second channel region417a, which has a channel concentration reduced by the implantation of the opposite conductivity type impurities. The buffer layer A prevents the semiconductor substrate410from being damaged during the ion implantation process.

Referring toFIG. 4D, the second photoresist pattern428is removed. Then, a cleaning process is performed for a subsequent deposition process. At this time, the buffer layer A is completely removed, and a part or an entirety of the patterned passivation layer425amay be etched. Thereafter, an insulating layer430and a gate electrode layer432are sequentially formed on the semiconductor substrate410. The insulating layer430may be formed of an oxide layer and may be formed by a CVD method. The gate electrode layer432may be formed of a polysilicon layer or a metal layer.

Referring toFIG. 4E, the gate electrode layer432, the insulating layer430, the patterned charge trap layer422a, and the patterned tunneling layer420aare sequentially patterned. As a result, a tunneling layer pattern420b, a charge trap layer pattern422band a shielding layer pattern430a, which are sequentially stacked, are formed on the first channel region417. Here, the shielding layer pattern430ais composed of the insulating layer430. When a part of the patterned passivation layer425aremains, the shielding layer pattern430ais composed of the insulating layer430and the remaining patterned passivation layer425a. At the same time, a gate insulating layer430bis formed on the second channel region417a, and a gate electrode432ais formed to cover both the shielding layer430aand the gate insulating layer430b.

Also at the same time, a peripheral circuit gate insulating layer430cand a peripheral circuit gate electrode432b, which are sequentially stacked over the peripheral circuit channel region415, are formed in the peripheral circuit region P. A thickness of the peripheral circuit gate insulating layer430cdepends on additional photolithography/etching/oxidation processes to be suitable for an operating voltage of peripheral circuits.

Thereafter, an ion implantation process is performed using the gate electrode432aas a mask. As a result, a source region S1and a drain region D1may be formed in the cell active region adjacent to the tunneling layer pattern420band the gate insulating layer430b, respectively. Also, an ion implantation process is performed using the peripheral circuit gate electrode432bas a mask. As a result, a source region S2and a drain region D2are formed in the peripheral circuit active region adjacent to the peripheral circuit gate electrode432b.

FIGS. 5A and 5Billustrate cross-sectional views of stages in a method of fabricating a non-volatile flash memory device according to a fourth embodiment of the present invention.

Referring toFIG. 5A, as described in connection withFIG. 4A, the cell region C and the peripheral circuit region P are defined in a semiconductor substrate410. The isolation layer412is formed in the cell region C and the peripheral circuit region P. The first channel region417and the peripheral circuit channel region415are formed in the semiconductor substrate410. The tunneling layer420, the charge trap layer422, and the passivation layer425are sequentially formed on the semiconductor substrate410. Then, a second photoresist layer is formed on the semiconductor substrate having the passivation layer425. The second photoresist layer is patterned to form the second photoresist pattern428exposing a portion of the passivation layer425on the first channel region417.

An ion implantation process is performed using the second photoresist pattern428as a mask. Impurities used for the ion implantation process preferably have a conductivity type opposite to that of the first channel region417. As a result, a portion of the first channel region417, which is exposed to the ion implantation, becomes the second channel region417a, which has a channel concentration reduced by the implantation of the opposite conductivity type impurities.

Referring toFIG. 5B, the second photoresist pattern428is removed. Then, a first photoresist layer is formed on the semiconductor substrate having the passivation layer425. The first photoresist layer is patterned to form the first photoresist pattern427covering the passivation layer425on the first channel region417.

The passivation layer425, the charge trap layer422and the tunneling layer420are sequentially patterned using the first photoresist pattern427as a mask. As a result, a patterned passivation layer425a, a patterned charge trap layer422aand a patterned tunneling layer420aare formed, and top surfaces of the peripheral circuit region P and the second channel region417aare exposed.

Thereafter, the first photoresist pattern427is removed. Subsequent processes are substantially similar to those described in connection withFIGS. 4D and 4Eand will not be repeated.

FIGS. 6A through 6Eillustrate cross-sectional views of stages in a method of fabricating a non-volatile flash memory device according to a fifth embodiment of the present invention.

Referring toFIG. 6A, an isolation layer612is formed in a semiconductor substrate610to define an active region. The isolation layer612may be formed by a trench isolation method. Impurity ions are implanted into the active region to form a first channel region617.

A tunneling layer620, a charge trap layer622and a passivation layer625are sequentially formed on the semiconductor substrate610. The tunneling layer620may be formed of a silicon oxide layer or a silicon oxynitride (SiON) layer and may be formed by a thermal oxidation process. The charge trap layer622may be formed of a high-k dielectric layer. In particular, the charge trap layer622may be formed of a silicon nitride layer. The passivation layer625, which may be formed of a silicon oxide layer or a silicon oxynitride layer, protects the charge trap layer622during a subsequent process. The charge trap layer622and the passivation layer625may be formed by a CVD method or an ALD method.

Referring toFIG. 6B, a photoresist layer is formed on the semiconductor substrate having the passivation layer625. The photoresist layer is patterned to form a photoresist pattern627exposing a portion of the passivation layer625on the first channel region617. An ion implantation process is then performed using the photoresist pattern627as a mask. Impurities used for the ion implantation preferably have a conductivity type opposite to that of the first channel region617. As a result, a portion of the first channel region617which is exposed to the ion implantation becomes a second channel region617a, which has a channel concentration reduced by the implantation of the opposite conductivity type impurities. As a result, a pair of first channel regions617, e.g., first sub channel regions, are formed to be separated by the second channel region617a.

Referring toFIG. 6C, the passivation layer625, the charge trap layer622and the tunneling layer620are sequentially patterned using the photoresist pattern627as a mask. As a result, a patterned passivation layer625a, a patterned charge trap layer622a, and a patterned tunneling layer620aare formed, and a top surface of the second channel region617ais exposed.

Referring toFIG. 6D, the photoresist pattern627is removed. Then, a cleaning process is performed for a subsequent deposition process. At this time, a part or an entirety of the patterned passivation layer625amay be etched. Thereafter, an insulating layer630and a gate electrode layer632are sequentially formed over the semiconductor substrate610. The insulating layer630may be formed of an oxide layer and may be formed by a CVD method. The gate electrode layer632may be formed of a polysilicon layer or a metal layer.

Referring toFIG. 6E, the gate electrode layer632, the insulating layer630, the patterned charge trap layer622a, and the patterned tunneling layer620aare sequentially patterned. As a result, tunneling layer patterns620b, charge trap layer patterns622band shielding layer patterns630a, which are sequentially stacked, are formed on each of the first channel regions617. Here, the shielding layer patterns630aare composed of the insulating layer630. When a part of the patterned passivation layer625aremains, the shielding layer patterns630aare composed of the insulating layer630and the remaining patterned passivation layer625a. At the same time, a gate insulating layer630bis formed on the second channel region617a, and a gate electrode632ais formed to cover both the shielding layer630aand the gate insulating layer630b.

Thereafter, an ion implantation process is performed using the gate electrode632aas a mask. As a result, a source region S1and a drain region D1may be formed in the cell active region adjacent to the tunneling layer patterns620b.

The resultant non-volatile flash memory device according to the fifth embodiment of the present invention will now be further described with reference toFIG. 6E.

Referring toFIG. 6E, the source region S1and the drain region D1are disposed to be spaced apart from each other in the semiconductor substrate610. Tunneling layer patterns620b, charge trap layer patterns622band shielding layer patterns630a, which are adjacent to, but spaced apart from, the source region S1and the drain region D1, are disposed on the semiconductor substrate610between the source region S1and the drain region D1. The tunneling layer patterns620bmay be a silicon oxide layer or a silicon oxynitride layer. The charge trap layer patterns622bmay be a high-k dielectric layer. In particular, the charge trap layer patterns622bmay be a silicon nitride layer.

First channel regions617, i.e., the first sub channel regions, are disposed in the semiconductor substrate below the tunneling layer patterns620b. The gate insulating layer630bis disposed on the semiconductor substrate between the first channel regions617. The shielding layer patterns630aand the gate insulating layer630bare formed of the same material layer and are connected. The shielding layer patterns630aand the gate insulating layer630bmay be an oxide layer and may have the same thickness.

The second channel region617ais disposed in the semiconductor substrate below the gate insulating layer630b. It is preferable that an impurity concentration of the second channel region617ais less than that of the first channel region617. The gate electrode632acovers both the shielding layer patterns630aand the gate insulating layer630b. The gate electrode632amay be a polysilicon layer or a metal layer.

FIG. 7illustrates a cross-sectional view of a resultant non-volatile flash memory device according to an embodiment of the present invention.

Referring toFIG. 7, a source region S1and a drain region D1are disposed to be spaced apart from each other in a semiconductor substrate710including an isolation region712. A tunneling layer pattern720, a charge trap layer pattern722and a shielding layer pattern730a, which are sequentially stacked to be adjacent to the source region S1, are disposed on the semiconductor substrate between the source region S1and the drain region D1. The tunneling layer pattern720may be a silicon oxide layer or a silicon oxynitride layer. The charge trap layer pattern722may be a high-k dielectric layer. In particular, the charge trap layer pattern722may be a silicon nitride layer.

A first channel region717is disposed in the semiconductor substrate710below the tunneling layer pattern720. A gate insulating layer730bis disposed on the semiconductor substrate710between the drain region D1and the first channel region717. The shielding layer pattern730aand the gate insulating layer730bare formed of the same material layer and are connected. The shielding layer pattern730aand the gate insulating layer730bmay be an oxide layer and may have the same thickness.

A second channel region717ais disposed in the semiconductor substrate710below the gate insulating layer730b. It is preferable that an impurity concentration of the second channel region717ais less than that of the first channel region717. A gate electrode732covers both the shielding layer pattern730aand the gate insulating layer730b. The gate electrode732may be a polysilicon layer or a metal layer.

As described above, by forming a channel region below the tunneling layer to have a different channel concentration from a channel region below the gate insulating layer, a variation of a threshold voltage during program and erase operations may be increased, and thus a sensing margin of the non-volatile flash memory device may be increased. In particular, by forming a channel region below the gate insulating layer to have a concentration less than a channel region below the tunneling layer, a threshold voltage during an erase operation may be significantly reduced, thereby significantly improving a sensing margin. As a result, a non-volatile flash memory device having excellent characteristics may be achieved.