Semiconductor devices and methods of fabricating the same

A semiconductor device includes capacitors connected in parallel. Electrode active portions and a discharge active portion are defined on a semiconductor substrate, and capping electrodes are disposed respectively on the electrode active portions. A capacitor-dielectric layer is disposed between each of the capping electrodes and each of the electrode active portions that overlap each other. A counter doped region is disposed in the discharge active portion. A lower interlayer dielectric covers the entire surface of the semiconductor substrate. Electrode contact plugs respectively contact the capping electrodes through the lower interlayer dielectric, and a discharge contact plug contacts the counter doped region through the lower interlayer dielectric. A lower interconnection is disposed on the lower interlayer dielectric and contacts the electrode contact plugs and the discharge contact plug.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2010-0019541, filed on Mar. 4, 2010, the entire contents of which are hereby incorporated by reference.

BACKGROUND

1. Technical Field

The present disclosure relates to semiconductor devices, and more particularly, to semiconductor devices and methods of fabricating the same.

2. Discussion of the Related Art

Due to the usefulness of small size, lightweight, low power consumption and/or multifunctional characteristics, semiconductor devices are important elements in the electronic industry. Specifications for the characteristics of semiconductor devices are subject to ever greater expectations. For example, the requirements for the reliability of semiconductor devices are on the increase. The requirements for the operational continuance, operational uniformity and/or durability of semiconductor devices against external environments are on the increase.

However, the reliability of semiconductor devices may degrade due to various factors. For example, the reliability of a semiconductor device may degrade due to the characteristic degradation of each unitary element in the semiconductor device, the interference between the unitary elements, and/or the characteristic degradation of the semiconductor device by external environments. The required characteristics of semiconductor devices are increasingly diversified with the rapid development of the semiconductor industry. Accordingly, factors degrading the reliability of semiconductor devices are increasingly diversified, and the reliability of semiconductor devices is an increasingly important characteristic.

SUMMARY

Exemplary embodiments of the present disclosure provide for semiconductor devices with high reliability and methods of fabricating the same.

Exemplary embodiments of the present disclosure provide semiconductor devices including MOS-type capacitors with improved reliability and methods of fabricating the same.

In some exemplary embodiments of the inventive concept, semiconductor devices include a discharge active portion and a plurality of electrode active portions defined by a device isolation pattern on a semiconductor substrate and doped with a first-type dopant, the electrode active portions being electrically connected to each other. A plurality of capping electrodes is disposed respectively on the electrode active portions. A capacitor-dielectric layer is disposed between each of the capping electrodes and each of the electrode active portions that overlap each other. A counter doped region is disposed in the discharge active portion and are doped with a second-type dopant. A lower interlayer dielectric is disposed on the entire surface of the semiconductor substrate. Each of a plurality of electrode contact plugs respectively contacts the capping electrodes through the lower interlayer dielectric. A discharge contact plug contacts the counter doped region through the lower interlayer dielectric. A lower interconnection is disposed on the lower interlayer dielectric and contacts top surfaces of the electrode contact plugs and the top surface of the discharge contact plug.

In some exemplary embodiments, the semiconductor devices further include a connection doped region doped with the first-type dopant, the connection doped region being disposed in the semiconductor substrate and connected to bottom surfaces of the electrode active portions and the discharge active portion.

In some exemplary embodiments, in an operation mode, a first voltage may be applied to the connection doped region and a second voltage different from the first voltage may be applied to the lower interconnection. Herein, the counter doped region and the discharge active portion may forms a PN junction, and a reverse bias may be provided to the PN junction by the first voltage and the second voltage.

In some exemplary embodiments, parasitic charges in the capping electrodes may be discharged through the lower interconnection, the discharge contact plug, the counter doped region and the discharge active portion.

In some exemplary embodiments, the semiconductor devices may further include an upper interlayer dielectric covering the lower interconnection and the lower interlayer dielectric. An upper interconnection is disposed on the upper interlayer dielectric.

In some exemplary embodiments, there may be a plurality of upper interlayer dielectrics and there may be a plurality of upper interconnections. In this case, the upper interlayer dielectrics and the upper interconnections may be alternately stacked, and the stacked upper interconnections may be electrically connected to the lower interconnection.

In some exemplary embodiments, the semiconductor devices may further include a dummy doped region disposed in the discharge active portion and doped with the second-type dopant. A dummy gate electrode is disposed on the discharge active portion between the counter doped region and the dummy doped region. A dummy gate dielectric layer is disposed between the dummy gate electrode and the discharge active portion.

In some exemplary embodiments, the dummy gate electrode, the dummy doped region and the electrode active portions may be electrically connected to each other.

In some exemplary embodiments, the semiconductor devices may further include a landing active portion defined by the device isolation pattern, spaced apart from the electrode active portions and the discharge active portion, and doped with the first-type dopant. First, second and third contact plugs are connected respectively to the dummy gate electrode, the dummy doped region and the landing active portion through the lower interlayer dielectric. A local interconnection is spaced apart laterally from the lower interconnection and disposed on the lower interlayer dielectric and contact the first, second and third contact plugs. A connection doped region is doped with the first-type dopant and is disposed in the semiconductor substrate and is connected to bottom surfaces of the electrode active portions, the discharge active portion and the landing active portion.

In some exemplary embodiments, the semiconductor devices may further include a heavily-doped region disposed in the landing active portion and doped with the first-type dopant. Herein, the heavily-doped region may have a higher dopant concentration than the landing active portion.

In some exemplary embodiments, the lower interconnection may include a metal.

In some exemplary embodiments of the inventive concept, methods of fabricating a semiconductor device include forming a well region, doped with a first-type dopant, in a semiconductor substrate. A device isolation pattern is formed in the well region and defines a discharge active portion and a plurality of electrode active portions. A capacitor-dielectric layer is formed on the electrode active portions. A plurality of capping electrodes is formed on the capacitor-dielectric layer and covers the electrode active portions. A counter doped region, doped with a second-type dopant, is formed in the discharge active portion. A lower interlayer dielectric is formed covering the entire surface of the semiconductor substrate. An electrode contact plug contacting each of the capping electrodes is formed through the lower interlayer dielectric, and a discharge contact plug contacting the counter doped region is formed through the lower interlayer dielectric. A lower interconnection is formed on the lower interlayer dielectric and contacts the electrode contact plug and the discharge contact plug.

In some exemplary embodiments, parasitic charges in the capping electrodes may be discharged through the lower interconnection, the discharge contact plug, the counter doped region and the discharge active portion.

In some exemplary embodiments, the parasitic charges may be generated by plasma-based processes among the processes performed after the foaming of the capping electrodes.

In some exemplary embodiments, after the forming of the lower interconnection, the methods may further include forming an upper interlayer dielectric on the semiconductor substrate. An interconnection contact plug is formed connecting to the lower interconnection through the upper interlayer dielectric. An upper interconnection is formed on the upper interlayer dielectric.

In some exemplary embodiments, the methods may further include forming a dummy gate dielectric layer and a dummy gate electrode sequentially stacked on the discharge active portion. A dummy doped region, doped with the second-type dopant, is formed in the discharge active portion at one side of the dummy gate electrode. Herein, the counter doped region may be formed at the other side of the dummy gate electrode, and the counter doped region may be formed substantially simultaneously with the dummy doped region.

In some exemplary embodiments, the device isolation pattern may further define a landing active portion in the well region. The landing active portion may be spaced apart from the electrode active portions and the discharge active portion. The methods may further include forming first, second and third contact plugs connected respectively to the dummy gate electrode, the dummy doped region and the landing active portion through the lower interlayer dielectric. A local interconnection is formed, connected to the first, second and third contact plugs, on the lower interlayer dielectric. Herein, the local interconnection may be laterally spaced apart from the lower interconnection.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

It will be understood that when a layer (or film) is referred to as being ‘on’ another layer or substrate, it can be directly on the other layer or substrate, or one or more intervening layers may also be present. It will also be understood that when a layer is referred to as being ‘under’ another layer, it can be directly under the other layer, or one or more intervening layers may also be present. It will also be understood that when a layer is referred to as being ‘between’ two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. In the drawings, the dimensions of layers (or films) and regions may be exaggerated for clarity of illustration. Throughout the specification, like reference numerals may refer to like elements.

FIG. 1is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the inventive concept.

Referring toFIG. 1, a device isolation pattern108may be disposed in a semiconductor substrate100. The device isolation pattern108defines a discharge active portion112and a plurality of electrode active portions110. The discharge active portion112is laterally spaced apart from the electrode active portions110. The semiconductor substrate100may be a silicon substrate. However, the inventive concept is not limited thereto. The semiconductor substrate100may be a germanium substrate or a silicon-germanium substrate. The device isolation pattern108may fill a trench formed in the semiconductor substrate100. The device isolation pattern108may include oxide, nitride and/or oxynitride.

Each of the electrode active portions110and the discharge active portion112may correspond to a portion of the semiconductor substrate100surrounded by the device isolation pattern108. The electrode active portions110may be arrange two-dimensionally in plan view. The discharge active portion112may be disposed at one side of the electrode active portions110. Alternatively, or additionally, the discharge active portion112may be disposed between the electrode active portions110. For example, the discharge active portion112may be located at substantially the same distances from the outermost some of the two-dimensionally arranged electrode active portions110. The electrode active portions110and the discharge active portion112are doped with a first-type dopant. The electrode active portions110may be electrically connected to each other. Also, the electrode active portions110and the discharge active portion112may be electrically connected to each other.

A connection doped region105amay be disposed in or on the semiconductor substrate100. The connection doped region105ais doped with the first-type dopant. The connection doped region105amay be disposed below the device isolation pattern108, the electrode active portions110, and/or the discharge active portion112. The connection doped region105amay contact bottom surfaces of the electrode active portions110and the discharge active portion112. The electrode active portions110and the discharge active portion112may be electrically connected to each other by the connection doped region105a. For example, a well region doped with the first-type dopant is formed in the semiconductor substrate100, and the device isolation pattern108may be formed in the well region to define the electrode active portions110and the discharge active portion112in the well region. A portion of the well region disposed lower than the device isolation pattern108, the electrode active portions110and the discharge active portion112may correspond to the connection doped region105a.

A plurality of capping electrodes120is disposed respectively on the electrode active portions110. A capacitor-dielectric layer is disposed between each of the electrode active portions110and each of the capping electrodes120that overlap each other. The electrode active portion110, capacitor-dielectric layer115and capping electrode120, are sequentially stacked, and may constitute a capacitor CAP. The electrode active portion110and capping electrode120overlap each other and correspond respectively to the lower electrode and upper electrode of the capacitor. The capacitor CAP includes the electrode active portion110and the capping electrode120, such that the capacitor CAP may be a MOS-type capacitor. A plurality of capacitors CAP may be two-dimensionally arranged at the semiconductor substrate100in plan view. The capacitors CAP may be connected in parallel to each other. Hereinafter, the capacitors CAP connected in parallel to each other will be referred to as the parallel capacitors CAP.

The capping electrodes120are formed of a conductive material. For example, the capping electrodes120may include at least one of a doped semiconductor material (e.g., a doped silicon), a conductive metal nitride (e.g., a titanium nitride and a tantalum nitride) or a conductive metal-semiconductor compound (e.g., a tungsten silicide and a titanium silicide). The capacitor-dielectric layer115is formed of a dielectric material. For example, the capacitor-dielectric layer115may include at least one of oxide, nitride, oxynitride or a high-k dielectric material (e.g., a dielectric metal oxide such as an aluminum oxide and a hafnium oxide). The capacitor-dielectric layer115may have a thickness of about 15 angstroms to about 1500 angstroms.

A counter doped region125doped with a second-type dopant is disposed in the discharge active portion112. The bottom surface of the counter doped region125may be higher than the bottom surface of the device isolation pattern108. For example, the bottom surface of the counter doped region125may be higher than the bottom surface of the discharge active portion112. The second-type dopant is different in type from the first-type dopant. One of the first-type and second-type dopants is an n-type dopant and the other is a p-type dopant. Accordingly, the counter doped region125and the discharge active portion112may form a PN junction. For example, the counter doped region125and the discharge active portion112may constitute a PN diode127.

A lower interlayer dielectric130may cover the entire surface of the semiconductor substrate100. The lower interlayer dielectric130may cover the capping electrodes120, the device isolation pattern108and the active portions110and112. The lower interlayer dielectric130may include an oxide, a nitride and/or an oxynitride. The top surface of the lower interlayer dielectric130may be in a planarized state.

Electrode contact plugs135may respectively contact the capping electrodes120through the lower interlayer dielectric130. One electrode contact plug135may contact each capping electrode120. Alternatively, a plurality of electrode contact plugs135may be provided on each capping electrode120. For example, a plurality of electrode contact plugs135may contact each capping electrode120. A discharge contact plug137may contact the counter doped region125through the lower interlayer dielectric130. The discharge contact plug137may be formed of the same conductive material as the electrode contact plugs135. For example, the electrode and discharge contact plugs135and137may include at least one of a doped semiconductor (e.g., a doped silicon), a conductive metal nitride (e.g., a titanium nitride and a tantalum nitride), a conductive metal-semiconductor compound (e.g., a titanium silicide and a tantalum silicide) and a metal (e.g., titanium, tantalum, tungsten, copper and aluminum).

A lower interconnection140is disposed on the lower interlayer dielectric130. The lower interconnection140is connected to the electrode contact plugs135. Also, the lower interconnection140is connected to the discharge contact plug137. For example, the lower interconnection140may contact the top surfaces of the electrode contact plugs135and the top surface of the discharge contact plug137. The lower interconnection140may be electrically connected to the plurality of the capping electrodes120by the electrode contact plugs135. Thus, the capacitors CAP may be connected in parallel to each other by the lower interconnection140and the connection doped region105a. The lower interconnection140may include a metal. For example, the lower interconnection140may include at least one of aluminum, tungsten and copper. Also, the lower interconnection140may further include a conductive barrier material (e.g., a conductive metal nitride such as a tantalum nitride and a titanium nitride). Also, the lower interconnection140may further include an adhesion layer (e.g., titanium or tantalum).

Parasitic charges may be present in the capping electrodes120. The parasitic charges may be discharged to the counter doped region125and the discharge active portion112via the lower interconnection140and the discharge contact plug137. The parasitic charges may be discharged through the discharge active portion112to the connection doped region105aand/or the semiconductor substrate100. The discharge contact plug137, the counter doped region125and the discharge active portion112may be used exclusively to discharge the parasitic charges. For example, the discharge contact plug137, the counter doped region125and the discharge active portion112may not engage in the operation of the parallel capacitors CAP.

At least one level of upper interlay dielectric and at least one level of lower interconnection may be stacked on the lower interconnection140and the lower interlayer dielectric130. For example, a plurality of interconnections spaced apart from each other may be stacked on the lower interlayer dielectric130. The upper interlayer dielectric may be disposed between the interconnections adjacent vertically to each other. The lower interconnection140is disposed at the lowermost one of the stacked interconnections. As an example,FIG. 1illustrates a semiconductor device including three levels of interconnections. However, the inventive concept is not limited thereto. According to an exemplary embodiment, the semiconductor device may include two levels of stacked interconnections or four or more layers of stacked interconnections.

Referring toFIG. 1, a first upper interlayer dielectric145may be disposed on the lower interconnection140and the lower interlayer dielectric130. The first upper interlayer dielectric145may include an oxide. For example, the first upper interlayer dielectric145may include an oxide formed by a plasma enhanced chemical vapor deposition (PECVD) process. A first interconnection contact plug147may be connected to the lower interconnection140through the first upper interlayer dielectric145. A first upper interconnection150may be disposed on the first upper interlayer dielectric145. The first upper interconnection150may be connected to the first interconnection contact plug147. The first upper interconnection150may be electrically connected to the lower interconnection140through the first interconnection contact plug147. A plurality of the first interconnection contact plug147may be provided in the first upper interlayer dielectric145between the first upper interconnection150and the lower interconnection140. Accordingly, the first upper interconnection150may be electrically connected to the lower interconnection140by the first interconnection contact plugs147. The first interconnection contact plug147may include a metal (e.g., tungsten, aluminum and/or copper). Also, the first interconnection contact plug147may further include a conductive barrier material (e.g., a titanium nitride and a tantalum nitride) and/or an adhesion layer (e.g., titanium and tantalum). The first upper interconnection150may include a metal (e.g., tungsten, aluminum and/or copper). Also, the first upper interconnection150may further include a conductive barrier material (e.g., a titanium nitride and a tantalum nitride) and/or an adhesion layer (e.g., titanium and tantalum).

A second upper interlayer dielectric155may be disposed on the first upper interconnection150and the first upper interlayer dielectric145. The second upper interlayer dielectric155may include an oxide (e.g., an oxide formed by a PECVD process). A second interconnection contact plug157may be connected to the first upper interconnection150through the second upper interlayer dielectric155. A second upper interconnection160may be disposed on the second upper interlayer dielectric155. The second upper interconnection160may be connected to the second interconnection contact plug157. The second upper interconnection160may be electrically connected to the lower interconnection140through the second interconnection contact plug157and the first upper interconnection150. The second interconnection contact plug157may be provided in plurality in the second upper interlayer dielectric155between the second upper interconnection160and the first upper interconnection150. The second upper interconnection160may be electrically connected to the first upper interconnection150through the second interconnection contact plugs157. The second interconnection contact plug157may include a metal (e.g., tungsten, aluminum and/or copper). Also, the second interconnection contact plug157may further include a conductive barrier material (e.g., a titanium nitride and a tantalum nitride) and/or an adhesion layer (e.g., titanium and tantalum). The second upper interconnection160may include a metal (e.g., tungsten, aluminum and/or copper). Also, the second upper interconnection160may further include a conductive barrier material (e.g., a titanium nitride and a tantalum nitride) and/or an adhesion layer (e.g., titanium and tantalum).

According to the above-described semiconductor device, parasitic charges, that may be present in the capping electrodes120, may be discharged through the counter doped region125and the discharge active portion112via the discharge contact plug137and the lowermost lower interconnection140among the interconnections140,150and160. Accordingly, the semiconductor device can have high reliability. The parasitic charges may be generated by the semiconductor device fabrication processes that are performed after the forming of the capping electrodes120. For example, the parasitic charges may be generated by the plasma-based subsequent processes among the subsequent processes. For example, charges generated by plasma used in the subsequent process may be accumulated in the capping capacitors120to generate the parasitic charges.

If the parasitic charges are accumulated in the capping electrodes120, the accumulated parasitic charges may cause defects in the capacitor CAP including the capping electrode120, the capacitor-dielectric layer115and the electrode active portion110. For example, the accumulated parasitic charges may degrade the capacitor-dielectric layer115to degrade the characteristics of the capacitor CAP. However, according to an exemplary embodiment of the inventive concept, the parasitic charges are discharged through the lower interconnection140, the discharge contact plug137, the counter doped region125and the discharge active portion112. Accordingly, the characteristic degradation of the capacitors CAP can be minimized. Consequently, a semiconductor device with high reliability can be implemented.

Also, the parasitic charges are discharges through the discharge contact plug137and the lowermost lower interconnection140among the interconnections140,150and160, thereby minimizing the discharge path of the parasitic charges. Accordingly, the parasitic charges can be discharged very rapidly, thus making it possible to implement a semiconductor device with high reliability.

As described above, the lower interconnection140, the discharge contact plug137, the counter doped region125and the discharge active portion112may be used to discharge the parasitic charges, and may not engage in the operation of the parallel capacitors CAP. This will be described below in detail with reference toFIGS. 2A and 2B.

FIG. 2Ais a circuit diagram of an example of a semiconductor device according to an exemplary embodiment of the inventive concept.

Referring toFIGS. 1 and 2A, capping electrodes120corresponding to one terminals of capacitors CAP may be electrically connected to each other by a lower interconnection140, and electrode active portions110corresponding to the other terminals of the capacitors CAP may be electrically connected to each other by a connection doped region105a. Accordingly, the capacitors CAP are connected in parallel to each other as illustrated inFIG. 2A. Both terminals of a PN diode127by the PN junction of the counter doped region125and the discharge active portion112may be respectively connected to the lower interconnection140and the connection doped region105a. One terminal of the PN diode127and the lower interconnection140may be connected by the discharge contact plug137.

In an operation of the semiconductor device (i.e., an operation of the parallel capacitors CAP), a first voltage V1may be applied to the connection doped region105aand a second voltage V2may be applied to the lower interconnection140. The first voltage V1and the second voltage V2are different from each other. The first voltage V1may be a reference voltage. The second voltage V2may be applied to the lower interconnection140via the second and first upper interconnections160and150. Although not illustrated in the drawings, the first voltage V1may be supplied to the connection doped region105athrough a contact structure (not illustrated) that is formed in the upper interlayer dielectrics155and145and the lower interlayer dielectric130and is connected to the connection doped region105a. The absolute value of the difference between the first voltage V1and the second voltage V2may be about 1.5 V to about 100 V.

A reverse bias is provided to the PN diode127by the first and second voltages V1and V2. For example, as illustrated inFIG. 2A, if the second voltage V2is higher than the first voltage V1, the PN diode127may be disposed such that a current flowing from the lower interconnection140to the connection doped region105ais blocked. If the second voltage V2is higher than the first voltage V1, the first-type dopant may be a p-type dopant and the second-type dopant may be an n-type dopant. That is, the discharge active portion112may be doped with a p-type dopant, and the counter doped region125may be doped with an n-type dopant. Because the reverse bias is provided to the PN diode127by the first and second voltages V1and V2, a current does not flow through the PN diode127. Consequently, the PN diode127may not engage in the operation of the parallel capacitors CAP.

One end of the lower interconnection140and one end of the connection doped region105amay be electrically connected to an integrated circuit200. Accordingly, the first and second voltages V1and V2may be provided to the integrated circuit200via the parallel capacitors CAP. The integrated circuit200may be a logic circuit, a driving circuit and/or a memory cell array. In this case, the parallel capacitors CAP may be decoupling capacitors that stably supply the first and second voltages V1and V2. However, the inventive concept is not limited thereto. According to an exemplary embodiment, the parallel capacitors CAP may be included in a boosting circuit that boosts a voltage. The semiconductor device ofFIG. 1may further include a region for the integrated circuit200.FIG. 2illustrates that the PN diode127including the counter doped region125and the discharge active portion112is disposed at one side of the parallel capacitors CAP. However, the inventive concept is not limited thereto. As described with reference toFIG. 1, the PN diode127may be disposed between the parallel capacitors CAP.

On the other hand, the first voltage V1may be higher than the second voltage V2. This will be described below with reference to the drawings.

FIG. 2Bis a circuit diagram of an example of a semiconductor device according to an exemplary embodiment of the inventive concept.

Referring toFIGS. 1 and 2B, if the first voltage V1is higher than the second voltage V2, a PN diode127by the PN junction of a counter doped region125and a discharge active portion112may be disposed such that a current flowing from the connection doped region105ato the lower interconnection140is blocked, as illustrated inFIG. 2B. In this case, the first-type dopant may be an n-type dopant and the second-type dopant may be a p-type dopant. For example, the discharge active portion112may be doped with an n-type dopant, and the counter doped region125may be doped with a p-type dopant.

Hereinafter, a description will be given of a method of fabricating a semiconductor device according to an exemplary embodiment of the inventive concept.

FIGS. 3A to 3Fare cross-sectional views illustrating a method of fabricating a semiconductor device according to an exemplary embodiment of the inventive concept.

Referring toFIG. 3A, a well region105doped with a first-type dopant may be formed in a semiconductor substrate100. The well region105may be formed by implanting the first-type dopant into the semiconductor substrate100through an ion implantation process.

Referring toFIG. 3B, a device isolation pattern108may be formed in the well region105and may define a discharge active portion112and a plurality of electrode active portions110. The electrode active portions110may be spaced apart from each other. Also, the discharge active portion112may be spaced apart from the electrode active portions110. Each of the active portions110and112may be a portion of the semiconductor substrate100surrounded by the device isolation pattern108. Because the device isolation pattern108is formed in the well region105, the active portions110and112are doped with the first-type dopant. A portion of the well region105located under the device isolation pattern108and the active portions110and112may correspond to a connection doped region105adescribed above with reference toFIG. 1.

Referring toFIG. 3C, a capacitor-dielectric layer115is formed on the entire surface of the semiconductor substrate100, and an electrode conductive layer is formed on the capacitor-dielectric layer115. The electrode conductive layer and the capacitor-dielectric layer115are sequentially patterned thereby forming capping electrodes120. The capping electrodes120may be disposed respectively on the electrode active portions110.

A second-type dopant may be implanted into the discharge active portion112thereby forming a counter doped region125. The counter doped region125and the discharge active portion112may form a PN-junction constituting a PN diode127. The counter doped region125may be formed before the forming of the capacitor-dielectric layer115or after the forming of the capping electrodes120.

Referring toFIG. 3D, a lower interlayer dielectric130is formed on the semiconductor substrate100having the capping electrodes120and the counter doped region125. Thereafter, electrode contact plugs135and a discharge contact plug137is formed piercing the lower interlayer dielectric130. The electrode contact plugs135contact the capping electrodes120, and the discharge contact plug137contacts the counter doped region125. The lower interlayer dielectric130may be patterned such that contact holes that respectively expose the capping electrode120and the counter doped region122are formed. A conductive layer may be formed filling the contact holes. The conductive layer may be planarized forming the electrode and discharge contact plugs135and137.

Thereafter, a lower interconnection140is formed on the lower interlayer dielectric130. The lower interconnection may contact the top surfaces of the electrode contact plugs135and the top surface of the discharge contact plug137. A lower conductive layer may be formed on the lower interlayer dielectric130, and the lower conductive layer may be patterned forming the lower interconnection140. The patterning of the lower conductive layer may include a photolithography process and an anisotropic etching process.

Parasitic charges that may be present in the capping electrodes120may be discharged through the lower interconnection140, the discharge contact plug137, the counter doped region125and the discharge active portion112.

The parasitic charges may be generated by plasma of the subsequent process after the forming of the capping electrode120. For example, the parasitic charges may be formed by plasma used in the patterning process for forming the contact holes for the contact plugs135and137(e.g., plasma used in the anisotropic etching process included in the patterning process), and/or plasma used in the patterning process for forming the lower interconnection140(e.g., plasma used in the anisotropic etching process including in the patterning process).

Referring toFIG. 3E, a first upper interlayer dielectric145may be formed on the first semiconductor substrate100having the lower interconnection140. The first upper interlayer dielectric145may include an oxide layer. Specifically, the first upper interlayer dielectric145may include an oxide layer formed through a PECVD process. If the first upper interlayer dielectric145is formed through a PECVD process, parasitic charges caused by a plasma damage may be generated in the capping electrodes120. Herein, the parasitic charges may be rapidly discharged to the counter doped region125and the discharge active portion112through the lower interconnection140and the discharge contact plug137. For example, during the performing the PECVD process for the first upper interlayer dielectric145, the semiconductor substrate100may be disposed on a grounded chuck in a process chamber. In this case, the parasitic charges discharged to the counter doped region125and the discharge active portion112may be discharged to the grounded chuck through the semiconductor substrate100.

At least one first interconnection contact plug147may be formed connected to the lower interconnection140through the first upper interlayer dielectric145. The first upper interlayer dielectric145may be patterned forming a first interconnection contact hole exposing the lower interconnection140, and the first interconnection contact plug147may be formed filling the first interconnection contact hole.

A first upper interconnection150may be formed on the first upper interlayer dielectric145. The first upper interconnection150may contact the top surface of the first interconnection contact plug147. A first upper conductive layer may be formed on the first upper interlayer dielectric145, and the first upper conductive layer may be patterned forming the first upper interconnection150.

When the processes for forming the first interconnection contact plug147and the processes for forming the first upper interconnection150use plasma, parasitic charges may be generated by the plasma. The parasitic charges may be discharged through the lower interconnection140, the discharge contact plug137, the counter doped region125and the discharge active portion112.

Referring toFIG. 3F, a second upper interlayer dielectric155may be formed covering the semiconductor substrate100. The second upper interlayer dielectric155may include an oxide layer. Specifically, the second upper interlayer dielectric155may include an oxide layer formed through a PECVD process. A second interconnection contact plug157may be formed connected to the first upper interconnection150through the second upper interlayer dielectric155. The second interconnection contact plug157may be formed in plurality. The second upper interlayer dielectric155may be patterned forming a second interconnection contact hole exposing the first upper interconnection150, and the second interconnection contact plug157may be formed filling the second interconnection contact hole. The patterning process for forming the second interconnection contact hole may include a photolithography process and a plasma-based anisotropic etching process. Thereafter, the second upper interconnection160ofFIG. 1may be formed on the second upper interlayer dielectric155. Accordingly, the semiconductor device illustrated inFIG. 1may be formed. The forming of the second upper interconnection160may include forming a second upper conductive layer on the second upper interlayer dielectric155and patterning the second upper conductive layer.

When the second upper interlayer dielectric155is formed through a PECVD process, parasitic charges may be generated by the plasma. The parasitic charges may be accumulated in the capping electrode120via the first upper interconnection150and the lower interconnection140. The parasitic charges in the capping electrode120may be discharge through the lower interconnection140, the discharge contact plug137, the counter doped region125and the discharge active portion112. Likewise, parasitic charges, which are generated by a plasma damage that may be caused in the forming process of the second interconnection contact hole and/or the forming process of the second upper interconnection160, may be discharged via the lower interconnection140and the discharge contact plug137.

According to the method for forming a semiconductor device described above, parasitic charges that are generated by plasma used in a semiconductor process after the forming of the capping electrodes120may be discharged through the discharge contact plug137and the lower interconnection140connected to the capping electrodes120. Accordingly, a semiconductor device with high reliability can be implemented.

FIG. 4is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the inventive concept.

Referring toFIG. 4, a device isolation pattern108may be disposed defining a plurality of electrode active portions110, a discharge active portion212and a landing active portion213in a semiconductor substrate100. The electrode active portions110, the discharge active portion212and the landing active portion213may be spaced apart from each other. Each of the active portions110,212and213may correspond to a portion of the semiconductor substrate100surrounded the device isolation pattern108. The electrode, discharge and landing active portions110,212and213may be doped with a first-type dopant, and may be electrically connected to each other. A connection doped region105bmay be disposed in the semiconductor substrate100. The connection doped region105bmay be doped with the first-type dopant, and may contact the bottom surfaces of the active portions110,212and213. The active portions110,212and213may be electrically connected to each other by the connection doped region105b.

A plurality of capping electrodes120are disposed respectively on the electrode active portions110, and a capacitor-dielectric layer115is disposed between each the electrode active portion110and each the capping electrode120that overlap each other. As described above with respect toFIGS. 1-3, the sequentially-stacked electrode active portion110, capacitor-dielectric layer115and capping electrode120constitute a capacitor CAP.

A dummy gate electrode121may be disposed on the discharge active portion212, and a dummy gate dielectric layer116may be disposed between the dummy gate electrode121and the discharge active portion212. The dummy gate electrode121may be formed of the same material as the capping electrode120. The dummy gate dielectric layer116may be formed of the same material as the capacitor-dielectric layer115. According to an exemplary embodiment, the dummy gate electrode121may have substantially the same size as the capping electrode120.

A counter doped region125amay be disposed in the discharge active portion212at one side of the dummy gate electrode121, and a dummy doped region126may be disposed in the discharge active portion212at the other side of the dummy gate electrode121. The counter doped region125aand the dummy doped region126are doped with a second-type dopant. The dummy gate electrode121, the counter doped region125aand the dummy doped region126may be included in a dummy transistor. The counter doped region125amay correspond to a first source/drain of the dummy transistor, and the dummy doped region126may correspond to a second source/drain of the dummy transistor. The dummy gate electrode121and the dummy doped region126may be electrically connected to the electrode active portions110. Thus, the dummy gate electrode121and the dummy doped region126may also be electrically connected to the discharge active portion212. The dummy gate electrode121and the dummy doped region126may be electrically connected to the electrode active portions110and the discharge active portion212via the landing active portion213and the connection doped region105b.

One of the first-type and second-type dopants is an n-type dopant, and the other is a p-type dopant. Thus, the counter doped region125aand the discharge active portion212forms a PN junction.

A lower interlayer dielectric130may be disposed over the semiconductor substrate100including the capping electrodes120and the dummy gate electrode121. As described above with respect toFIGS. 1-3, electrode contact plugs135may respectively contact the capping electrodes120through the lower interlayer dielectric130. A discharge contact plug137amay contact the counter doped region125athrough the lower interlayer dielectric130. A lower interconnection140ais disposed on the lower interlayer dielectric130. The lower interconnection140amay contact the top surfaces of the electrode contact plugs135and the top surface of the discharge contact plug137a. Accordingly, the capping electrodes120may be electrically connected to each other by the lower interconnection140a. The capacitors CAP may be connected in parallel to each other by the lower interconnection140aand the connection doped region105b.

A local interconnection140bmay be disposed on the lower interlayer dielectric130. The local interconnection140bmay be laterally spaced apart from the lower interconnection140a. The local interconnection140bmay be electrically insulated from the lower interconnection140a. The local interconnection140bmay be located at the same level as the lower interconnection140a.

The dummy gate electrode121, the dummy doped region126and the connection doped region105bmay be electrically connected to each other by the local interconnection140b. For example, a first contact plug222, a second contact plug224and a third contact plug226may penetrate the lower interlayer dielectric130. The first contact plug222may be connected to the dummy gate electrode121. The second contact plug224may be connected to the dummy doped region126. The third contact plug226may be connected to the landing active portion213. The local interconnection140bmay contact top surfaces of the first, second and third contact plugs222,224and226. A heavily-doped region220doped with the first-type dopant may be disposed in the landing active portion213. For example, the heavily-doped region220is doped with the same-type dopant as the landing active portion213. The heavily-doped region220has a higher dopant concentration than the landing active portion213. The third contact plug226may contact the heavily-doped region220. The contact resistance between the third contact plug226and the landing active portion213may be reduced by the heavily-doped region220.

The discharge contact plug137amay be formed of the same material as the electrode contact plug135. The first, second and third contact plugs222,224and226may also be formed of the same material as the electrode contact plug135. The lower interconnection140bis formed of the same material as the lower interconnection140described above with respect toFIGS. 1-3. The local interconnection140bmay be formed of the same material as the lower interconnection140a.

Parasitic charges may be present in the capping electrodes120. The parasitic charges may be discharged to the discharge active portion212via the lower interconnection140a, the discharge contact plug137aand the counter doped region125a. The parasitic charges may be discharged to the outside through the semiconductor substrate100and/or the connection doped region105b. A dummy transistor including the dummy gate electrode121does not engage in the operation of the parallel capacitors. Specifically, because the dummy gate electrode121and the dummy doped region126are electrically connected to each other, the dummy transistor may not operate when the semiconductor device operates. Also, because the counter doped region125aand the discharge active portion212form a PN junction, a current may not flow through the discharge contact plug137aeven when the different first and second voltages are applied respectively to the connection doped region105band the lower interconnection140a.

Referring toFIG. 4, a first upper interlayer dielectric145may be disposed on the lower interconnection140a, the local interconnection140band the lower interlayer dielectric130, and at least one first interconnection contact plug147may be connected to the lower interconnection140athrough the first upper interlayer dielectric145. A first upper interconnection150may be disposed on the first upper interlayer dielectric145contacting the top surface of the first interconnection contact plug147. Accordingly, the first upper interconnection150may be electrically connected to the lower interconnection140a. The first upper interconnection150may be insulated from the local interconnection140b.

A second upper interlayer dielectric155may be disposed on the first upper interconnection150and the first upper interlayer dielectric145, and at least second interconnection contact plug157may be connected to the first upper interconnection150through the second upper interlayer dielectric155. A second upper interconnection160may be disposed on the second upper interlayer dielectric155and may contact the top surface of the second interconnection contact plug157. The second upper interconnection160may be electrically connected to the lower interconnection140avia the upper interconnection150.

FIG. 4illustrates three levels of stacked interconnections140a,150and160. Herein, the lower interconnection140amay be located at the lowermost one of the stacked interconnections140a,150and160. As described above with respect toFIGS. 1-3, the semiconductor device according to an exemplary embodiment may include two levels of stacked interconnections or four or more levels of stacked interconnections. Also, in this case, the lower interconnection140amay be located at the lowermost one of the stacked interconnections.

In the above-described semiconductor device, the parasitic charges that may be present in the capping electrodes120may be discharged to the semiconductor substrate100and/or the connection doped region105bthrough the lowermost lower interconnection140aamong the interconnections140a,150and160and the discharge contact plug137aconnected thereto. Consequently, a semiconductor device with high reliability can be implemented. Also, the lowermost lower interconnection140aand the discharge contact plug137acan minimize the discharge path of the parasitic charges. The parasitic charges may be generated in the same way as described above with respect toFIGS. 1-3.

As described above, the discharge contact plug137amay be used only to discharge the parasitic charges, and may not engage in the operation of the semiconductor device (e.g., the operation of the parallel capacitors). This will be described below in detail with reference toFIG. 5.

FIG. 5is a circuit diagram of a semiconductor device according to an exemplary embodiment of the inventive concept.

Referring toFIGS. 4 and 5, a plurality of capacitors CAP may be connected in parallel to each other by a lower interconnection140aand a connection doped region105b. InFIG. 5, a reference symbol ‘DTR’ denotes a dummy transistor DTR including the dummy doped region126, the counter doped region125aand the dummy gate electrode121ofFIG. 4. The counter doped region125a(corresponding to a first source/drain) of the dummy transistor DTR is electrically connected to the lower interconnection140aby a discharge contact plug137a. The counter doped region125aof the dummy transistor DTR may form a PN junction with a discharge active portion212to constitute a PN diode. The dummy doped region126(corresponding to a second source/drain) of the dummy transistor DTR may be electrically connected to the dummy gate electrode121(corresponding to the gate) of the dummy transistor DTR. The dummy gate electrode121and the dummy doped region126of the dummy transistor DTR may be electrically connected to the connection doped region105b. The discharge active portion212may also be connected to the connection doped region105b. Accordingly, a body region of the dummy transistor DTR may also be connected to the connection doped region105b. A channel region may be defined in the body region of the dummy transistor DTR.

In an operation of the semiconductor device, a first voltage V1is applied to the connection doped region105band a second voltage V2is applied to the lower interconnection140a. The first voltage V1and the second voltage V2are different from each other. A PN diode by the PN junction of the counter doped region125aand the discharge active portion212may be disposed for being provided a reverse bias by the first and second voltages V1and V2.

As illustrated inFIG. 5, according to an exemplary embodiment, the second voltage V2may be higher than the first voltage V1. In this case, the PN diode by the counter doped region125aand the discharge active portion212may be disposed blocking a current flowing from the lower interconnection140ato the connection doped region105b. In this case, the first-type dopant may be a p-type dopant and the second-type dopant may be an n-type dopant. Accordingly, the counter doped region125amay be doped with an n-type dopant, and the discharge active portion212may be doped with a p-type dopant. Also, the dummy transistor DTR may be an NMOS transistor. The body region, the dummy gate electrode121and the dummy doped region126of the dummy transistor DTR may be provided with the same voltage when the first voltage V1is supplied thereto. Accordingly, the dummy transistor DTR may also become an off state.

Consequently, the dummy transistor DTR and the PN diode by the counter doped region125aand the discharge active portion212are all turned off in an operation of the semiconductor device. Accordingly, the dummy transistor DTR and the PN diode may not engage in the operation of the semiconductor device (e.g., the operation of the parallel capacitors CAP, and the discharge contact plug137aand the counter doped region125amay be used only to discharge the parasitic charges.

As illustrated inFIG. 5, one end of the lower interconnection140aand one end of the connection doped region105bmay be electrically connected to an integrated circuit200. Accordingly, the first and second voltages V1and V2may be provided to the integrated circuit200via the parallel capacitors CAP. The integrated circuit200may be a logic circuit, a driving circuit and/or a memory cell array. In this case, the parallel capacitors CAP may be decoupling capacitors that stably supply the first and second voltages V1and V2. However, the inventive concept is not limited thereto. The parallel capacitors CAP may be included in a boosting circuit that boosts a voltage. The semiconductor device ofFIG. 4may further include a region for the integrated circuit200.

According to an exemplary embodiment, the first voltage V1may be higher than the second voltage V2. In this case, the first-type dopant may be an n-type dopant and the second-type dopant may be a p-type dopant. Accordingly, the counter doped region125amay be doped with a p-type dopant, and the discharge active portion212may be doped with an n-type dopant. In this case, the PN diode by the counter doped region125aand the discharge active portion112may be disposed blocking a current flowing from the connection doped region105bto the lower interconnection140a. Also, in this case, the dummy transistor DTR may be a PMOS transistor.

FIGS. 6A to 6Eare cross-sectional views illustrating a method of fabricating a semiconductor device according to an exemplary embodiment of the inventive concept.

Referring toFIGS. 6A and 6B, a first-type dopant may be ion-implanted into a semiconductor substrate100forming a well region105. A device isolation pattern108may be formed in the well region105defining a plurality of electrode active portions110, a discharge active portion212and a landing active portion213. Each of the active portions110,212and213may correspond to a portion of the semiconductor substrate100surrounded by the device isolation pattern108. When the device isolation pattern108is formed in the well region105, the active portions110,212and213are doped with the first-type dopant. A portion of the well region105located under the device isolation pattern108and the active portions110,212and213may correspond to a connection doped region105bdescribed with reference toFIG. 4.

Referring toFIG. 6C, a capacitor-dielectric layer115is formed on the entire surface of the semiconductor substrate100, and an electrode conductive layer is formed on the capacitor-dielectric layer115. The electrode conductive layer and the capacitor-dielectric layer115are sequentially patterned forming a plurality of capping electrodes120and a dummy gate electrode121. The capping electrodes120may be formed respectively on the electrode active portions110, and the dummy gate electrode121may be formed on the discharge active portion212.

A second-type dopant may be implanted into the discharge active portion212at both sides of the dummy gate electrode121forming a counter doped region125aand a dummy doped region126. The counter doped region125aand the dummy doped region126may be foamed simultaneously. The first-type dopant may be implanted into the landing active portion213forming a heavily-doped region220. The heavily-doped region220may be formed after the forming of the counter and dummy doped regions125aand126. According to an exemplary embodiment, the counter and dummy doped regions125aand126may be formed after the forming of the heavily-doped region220.

Referring toFIG. 6D, a lower interlayer dielectric130may be formed on the entire surface of the semiconductor substrate100. As described above with respect toFIGS. 1-3, the lower interlayer dielectric130may include an oxide layer (e.g., an oxide layer formed through a PECVD process).

Electrode contact plugs135, a discharge contact plug137a, a first contact plug222, a second contact plug224and a third contact plug226may be formed such that they pierce the lower interlayer dielectric130. The electrode contact plugs135respectively contact the capping electrodes120, and the discharge contact plug137acontacts the counter doped region125a. The first contact plug222contacts the dummy gate electrode121, and the second contact plug224contacts the dummy doped region126. The third contact plug226contacts the landing active portion213, particularly to the heavily-doped region220. The lower interlayer dielectric130may be patterned forming contact holes, and the contact plugs135,137a,222,224and226may be formed filling the contact holes.

Thereafter, a lower interconnection140aand a local interconnection140bare formed on the lower interlayer dielectric130such that they are laterally spaced apart from each other. The lower interconnection140acontacts the top surfaces of the electrode contact plugs135and the top surface of the discharge contact plug137a. The local interconnection140bmay contact the top surfaces of the first, second and third contact plugs222,224and226. The lower interconnection140aand the local interconnection140bmay be formed through a patterning process.

A first upper interlayer dielectric145may be formed on the lower interconnection140a, the local interconnection140band the lower interlayer dielectric130. The material and/or characteristics of the first upper interlayer dielectric145are the same as those described above with respect toFIGS. 1-3, and thus a description thereof will be omitted for conciseness.

Referring toFIG. 6E, at least one first interconnection contact plug147may be formed and may connect to the lower interconnection140athrough the first upper interlayer dielectric145, and a first upper interconnection150may be formed on the first upper interlayer dielectric145and may contact the top surface of the first interconnection contact plug147.

A second upper interlayer dielectric155may be formed on the first upper interconnection150and the first upper interlayer dielectric145. At least one second interconnection contact plug157may be formed and may contact the first upper interconnection150through the second upper interlayer dielectric155. Thereafter, a second upper interconnection160ofFIG. 4may be formed. Accordingly, the semiconductor device ofFIG. 4can be implemented. The methods for forming the first interconnection contact plug147, the first upper interconnection150, the second upper interlayer dielectric155, the second interconnection contact plug157and the second upper interconnection160may be the same as those described above with respect toFIGS. 1-3.

In the above-described semiconductor device fabrication method, parasitic charges may be generated by the plasma-based semiconductor processes among the subsequent semiconductor processes after the forming of the capping electrodes120. The parasitic charges may be accumulated in the capping electrodes120. The parasitic charges in the capping electrode120may be discharged through the lower interconnection140aand the discharge contact plug137a. The parasitic charges are discharged through the discharge contact plug137aand the lower interconnection140alowermost among the stacked interconnections, thereby minimizing the discharge path of the parasitic charges. Accordingly, a semiconductor device with high reliability can be implemented. As described above with respect toFIGS. 1-3, the parasitic charges may be discharged during the performing of the plasma-based subsequent process. However, the inventive concept is not limited thereto. The parasitic charges may be discharged after the performing of the plasma-based subsequent process.

According to the semiconductor device described above, the parasitic charges, which may be present in the capping electrodes, may be discharged through the lower interconnection and the discharge contact plug. Accordingly, a semiconductor device with high reliability can be implemented. Also, the parasitic charges are discharged through the lower interconnection and the discharge contact plug contacting the counted doped region, thereby minimizing the discharge path of the parasitic charges. The parasitic charges can be discharged rapidly.

The above-disclosed subject matter is to be considered illustrative and not restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments, which fall within the true spirit and scope of the inventive concept.