Integrated circuit device with interconnects arranged parallel to each other and connected to contact via, and method for manufacturing same

According to one embodiment, an integrated circuit device includes a plurality of interconnects and a contact via. The plurality of interconnects are arranged parallel to each other. The contact via is connected to the each of the interconnects. A protrusion is formed at a portion of each of the interconnects connected to the contact via to protrude in a direction of the arrangement. A recess is formed at a portion of the each of the interconnects separated from the portion having the protrusion to recede in the direction. The protrusion formed on one interconnect of two mutually-adjacent interconnects among the plurality of interconnects is opposed to the recess formed in one other interconnect of the two mutually-adjacent interconnects. The portion having the recess is separated from portions on two sides thereof and is separated also from the portion having the protrusion.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2011-089082, filed on Apr. 13, 2011; the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to in integrated circuit device and a method for manufacturing the same.

BACKGROUND

In recent years, the downscaling of interconnect spacing has progressed as higher integration of integrated circuit devices has progressed. In particular, many interconnects are arranged parallel to each other in memory devices such as MRAM (Magneto resistive Random Access Memory) and the like because the interconnects are drawn out from multiple memory cells arranged in a matrix configuration. It is possible to utilize a sidewall process to reduce the arrangement period of the interconnects thus arranged parallel to each other. The sidewall process is a method in which core members are formed in line configurations, slimming of the core members is performed, sidewalls are formed on two sides of the core members, and the core members are subsequently removed. Thereby, multiple sidewalls having an arrangement period of half of the arrangement period of the core members can be formed; and it is possible to form fine interconnects by using the sidewalls as a mask.

However, it is also necessary to downscale the diameters of the contact vias connected to the interconnects as the interconnects are downscaled using the sidewall process.

Thereby, the formation of the contact vias becomes difficult; the contact vias become finer; and the resistance undesirably increases.

DETAILED DESCRIPTION

In general, according to one embodiment, an integrated circuit device includes a plurality of interconnects and a contact via. The plurality of interconnects are arranged parallel to each other. The contact via is connected to each of the interconnects. A protrusion is formed at a portion of the each of the interconnects connected to the contact via to protrude in a direction of the arrangement. A recess is formed at a portion of the each of the interconnects separated from the portion having the protrusion to recede in the direction of the arrangement. The protrusion formed on one interconnect of two mutually-adjacent interconnects among the plurality of interconnects is opposed to the recess formed in one other interconnect of the two mutually-adjacent interconnects. The portion having the recess is separated from portions on two sides of the portion having the recess and is separated also from the portion having the protrusion, in the each of the interconnects.

In general, according to one embodiment, an integrated circuit device includes a plurality of interconnects and a contact via. The plurality of interconnects are arranged parallel to each other. The contact via is connected to each of the interconnects. A bent portion is formed at a portion of the each of the interconnects connected to the contact via to curve to form a protrusion in one direction of the arrangement. The plurality of interconnects includes a first interconnect and a second interconnect. The second interconnect is adjacent the first interconnect and disposed in the direction of the protrusion of the bent portion of the first interconnect as viewed from the first interconnect. An opposing portion of the second interconnect is opposed to the bent portion of the first interconnect. The opposing portion of the second interconnect is separated from portions of the second interconnect on two sides of the opposing portion and is separated also from the bent portion of the second interconnect.

In general, according to one embodiment, an integrated circuit device includes a plurality of interconnects and a contact via. The plurality of interconnects are arranged parallel to each other. The contact via is connected to each of the interconnects. A bent portion is formed at a portion of the each of the interconnects separated from a portion of the each of the interconnects connected to the contact via to curve to form a protrusion in one direction of the arrangement. The portion having the bent portion is separated from portions on two sides of the portion having the bent portion and is separated also from the portion connected to the contact via, in the each of the interconnects. The plurality of interconnects includes a first interconnect and a second interconnect. The second interconnect is adjacent the first interconnect. The bent portion of the first interconnect is opposed to a portion of the second interconnect connected to the contact via. The protrusion of the bent portion of the first interconnect is formed in a direction away from the portion of the second interconnect connected to the contact via.

In general, according to one embodiment, a semiconductor device includes a plurality of first interconnects, a plurality of second interconnects, and a contact via. The plurality of first interconnects are formed over a semiconductor substrate and arranged parallel to each other in a first direction. The plurality of second interconnects are formed on an inter-layer insulating film covered the plurality of first interconnects and arranged parallel to each other in a direction perpendicular to the first direction. The contact via is formed at a cross region between a lower interconnect of the plurality of first interconnects and an upper interconnect of the plurality of second interconnects. The lower interconnect includes a protrusion formed at a portion connected to the contact via. The protrusion is protruded in the first direction. One of the plurality of first interconnects is adjacent to the lower interconnection. The one of the plurality of first interconnects includes a recess formed at an opposite side to the protrusion and separated from the protrusion.

In general, according to one embodiment, a method is disclosed for manufacturing an integrated circuit device. The method can include forming an insulating film on a substrate. The method can include forming a plurality of core members extending in one direction on the insulating film. Each of the plurality of core members includes a protrusion protruding in a width direction and a recess receding in the width direction at positions mutually separated in the one direction. The method can include making the core members finer. The method can include forming sidewalls on side surfaces of the core members. The method can include removing the core members. The method can include forming pillars in a first portion and a second portion of a region between two mutually-adjacent sidewalls to link the two mutually-adjacent sidewalls to each other. The first portion is between a portion of the region having a narrow spacing between the sidewalls and a portion of the region having a wide spacing between the sidewalls. The portion of the region has the narrow spacing between the sidewalls being interposed between the first portion and the second portion. The method can include making a trench in the insulating film by performing etching using the sidewalls and the pillars as a mask. The method can include forming interconnects by filling a conductive material into the trench. In addition, the method can include forming a contact via to connect to a portion of each of the interconnects having a width wider than widths of the other portions of the each of the interconnects.

In general, according to one embodiment, a method is disclosed for manufacturing an integrated circuit device. The method can include forming a conductive film on a substrate. The method can include forming a plurality of core members extending in one direction on the conductive film. Each of the plurality of core members includes a protrusion protruding in a width direction or a recess receding in the width direction formed in one side surface of a first portion and a protrusion protruding in the width direction or a recess receding in the width direction formed in one other side surface of a second portion. The method can include making the core members finer. The method can include forming sidewalls on side surfaces of the core members. The method can include removing the core members. The method can include patterning the conductive film into a plurality of interconnects by performing etching using the sidewalls as a mask. A bent portion is formed in one location of each of the plurality of interconnects to curve into a protruding configuration. The plurality of interconnects have a first interconnect and a second interconnect. The second interconnect is adjacent the first interconnect and disposed in the direction of the protrusion of the bent portion of the first interconnect as viewed from the first interconnect. The method can include separating an opposing portion of the second interconnect opposing the bent portion of the first interconnect from portions of the second interconnect on two sides of the opposing portion while separating the opposing portion from the bent portion of the second interconnect. In addition, the method can include forming a contact via to connect to the bent portion.

In general, according to one embodiment, a method is disclosed for manufacturing an integrated circuit device. The method can include forming a conductive film on a substrate. The method can include forming a plurality of core members extending in one direction on the conductive film. Each of the plurality of core members includes a protrusion protruding in a width direction or a recess receding in the width direction formed in one side surface of a first portion and a protrusion protruding in the width direction or a recess receding in the width direction formed in one other side surface of a second portion. The method can include making the core members finer. The method can include forming sidewalls on side surfaces of the core members. The method can include removing the core members. The method can include patterning the conductive film into a plurality of interconnects by performing etching using the sidewalls as a mask. A bent portion is formed in one location of each of the plurality of interconnects to curve into a protruding configuration. The plurality of interconnects have a first interconnect and a second interconnect. The second interconnect is adjacent the first interconnect. The protrusion of the bent portion of the second interconnect is formed in a direction away from the first interconnect. The method can include separating the bent portion of the first interconnect from portions of the first interconnect on two sides of the bent portion of the first interconnect while separating the bent portion of the first interconnect from an opposing portion of the first interconnect. The opposing portion is opposed to the bent portion of the second interconnect. In addition, the method can include forming a contact via to connect to the opposing portion of each of the interconnects.

First, a first embodiment will be described.

FIG. 1illustrates an integrated circuit device according to the embodiment.

FIG. 2is a plan view illustrating a draw-out region of the integrated circuit device according to the embodiment.

For easier viewing of the drawing inFIG. 2, only conductive portions are illustrated; and insulating portions are not illustrated. This is similar also for similar plan views described below.

As illustrated inFIG. 1, the integrated circuit device1according to the embodiment is a memory device, e.g., an MRAM. In the integrated circuit device1, a silicon substrate10(referring toFIG. 3) is provided; memory array regions11aand11bof two mutually-separated locations are provided in the front surface of the silicon substrate10; and a draw-out region12is provided between the memory array regions11aand11b.

Hereinbelow, for convenience of description, a direction from the memory array region11atoward the memory array region11bis taken as a +X direction; the reverse direction is taken as a −X direction; and the +X direction and the −X direction are generally referred to as the X direction. Directions perpendicular to the front surface of the silicon substrate10are taken as a +Z direction and a −Z direction; and directions orthogonal to both the X direction and the Z direction are taken as a +Y direction and a −Y direction.

Multiple memory cells MC are arranged in a matrix configuration in each of the memory array regions11aand11b. A common interconnect14ais drawn out from the multiple memory cells MC of the memory array region11aarranged in one column along the X direction to reach the draw-out region12. Similarly, a common interconnect14bis drawn out from the multiple memory cells MC of the memory array region11barranged in one column along the X direction to reach the draw-out region12.

A sense amplifier region13is provided on the −Y direction side as viewed from the draw-out region12. Multiple interconnects15extending in the Y direction are provided between the draw-out region12and the sense amplifier region13. One end of each of the interconnects15is connected to the interconnect14aor14bby a contact via16in the draw-out region12. In other words, in the draw-out region12, the interconnects14aand14bdrawn out in the X direction (hereinbelow generally referred to as the interconnects14) are connected one-to-one to the interconnects15drawn out in the Y direction by contact vias extending in the Z direction.

As illustrated inFIG. 3, an inter-layer insulating film21is provided on the silicon substrate10; and the interconnects14are provided on the inter-layer insulating film21. An inter-layer insulating film22is provided on the inter-layer insulating film21to cover the interconnects14; and the contact vias16are buried inside the inter-layer insulating film22. The interconnects15are provided on the inter-layer insulating film22; and an inter-layer insulating film23is provided to cover the interconnects15. The interconnects14are connected to the lower ends of the contact vias16; and the interconnects15are connected to the upper ends of the contact vias16.

As illustrated inFIG. 2, the interconnect14aand the interconnect14bare arranged to be parallel to each other at uniform spacing. The interconnect14aand the interconnect14bare arranged alternately in the Y direction. Protrusions31are formed in the portions of the interconnects14where the contact vias16are connected. The positions of the interconnects14where the contact vias16are connected are different from each other in the X direction. In each of the interconnects14, a recess32is formed in a portion separated in the X direction from the portion where the protrusion31is formed. In each of the interconnects14, the protrusion31is formed on a side surface on the +Y direction side of the interconnect14to protrude in the +Y direction. The recess32is formed in a side surface on the −Y direction side of the interconnect14to recede in the +Y direction. In other words, in the interconnects14, the protrusions31protrude in the same direction (the +Y direction); and the recesses32recede in the same direction (the +Y direction).

In two mutually-adjacent interconnects14, i.e., one interconnect14aand the interconnect14badjacent to the interconnect14a, the protrusion31formed in one interconnect14opposes the recess32formed in the other interconnect14; and the configurations substantially correspond. In other words, as viewed from the Z direction, the positions in the X direction and the dimensional relationships are substantially the same for the portion of one interconnect14corresponding to the protrusion31of the outer edge on the +Y direction side and the portion corresponding to the recess32of the outer edge on the −Y direction side of the adjacent interconnect14positioned on the +Y direction side as viewed from the one interconnect14.

The slits33are made in two locations of each of the interconnects14; and each of the interconnects14is divided into three portions. Thereby, in each of the interconnects14, the portion where the recess32is formed is separated from portions on two sides of the portion where the recess32is formed. The portion where the recess32is formed also is separated from the portion where the protrusion31is formed.

That is, the integrated circuit device1is a semiconductor device. The device1includes the plurality of interconnects14, the plurality of interconnects15, and the contact vias16. The interconnects14are formed over the semiconductor substrate10. The interconnects14are arranged parallel to each other in the X direction. The interconnects15are formed on the inter-layer insulating film21covered the interconnects14. The interconnects15are arranged parallel to each other in the Y direction perpendicular to the X direction. The contact vias16are formed at a cross region between a lower interconnect and an upper interconnect. The lower interconnect is one of the plurality of interconnects14. The upper interconnect is one of the plurality of interconnects15. The lower interconnect includes the protrusion31formed at a portion connected to the contact via16. The protrusion31is protruded in the X direction. One of the interconnects14that is adjacent to the lower interconnection includes the recess32formed at an opposite side to the protrusion31. The recess32is separated from the protrusion31.

A method for manufacturing the integrated circuit device according to the embodiment will now be described.

FIGS. 4A to 4Dare process plan views and cross-sectional views of processes, illustrating the method for manufacturing the integrated circuit device according to the embodiment.

In each of the drawings, the drawing on the left is a process plan view; and the drawing on the right is a cross-sectional view of the process. The cross-sectional views of processes are cross-sectional views along line B-B′ of the process plan views respectively. For convenience of illustration in the process plan views, the core members, the sidewalls, the pillars, and the interconnects are marked with dots. This is similar forFIGS. 7A to 7D,FIGS. 9A to 9D,FIGS. 11A to 11D, andFIGS. 12A to 12Ddescribed below.

In the embodiment, the interconnect14is formed using a sidewall process and a damascene process.

First, as illustrated inFIG. 3, a prescribed drive circuit is formed in the front surface of the silicon substrate10. For example, the memory cells MC (referring toFIG. 1) are formed in the memory array regions11aand11bwhile forming sense amplifiers (not illustrated) in the sense amplifier region13. Then, the inter-layer insulating film21is formed on the silicon substrate10.

Then, as illustrated inFIG. 4A, an insulating film41is formed on the inter-layer insulating film21. Continuing, multiple core members42are formed on the insulating film41. Each of the core members42is formed in a line configuration extending in the X direction; and a protrusion43and a recess44are formed at positions mutually separated in the X direction. The protrusion43protrudes from the side surface of the core member42on the +Y direction side by the dimension t in the +Y direction. On the other hand, the recess44recedes from the side surface of the core member42on the −Y direction side by the dimension t in the +Y direction. In the multiple core members42, all of the positions of the protrusions43and the positions of the recesses44in the X direction are different from each other.

Continuing as illustrated inFIG. 4B, slimming is performed on the core members42to make the core members42finer. At this time, the protruded amount of the protrusion43and the receded amount of the recess44are reduced but remain.

Then, as illustrated inFIG. 4C, sidewalls45are formed on the side surfaces of the core members42by depositing, for example, a silicon nitride film on the entire surface and performing etch-back. Continuing, the core members42are removed. Thereby, the multiple sidewalls45extending in the X direction remain on the insulating film41. At this time, the arrangement period of the sidewalls45is half of the arrangement period of the core members42. The portion of the sidewall45formed on the side surface of the protrusion43of the core member42is a curved portion46that is curved along the side surface of the protrusion43. Similarly, the portion of the sidewall45formed on the side surface of the recess44of the core member42is a curved portion46that is curved along the side surface of the recess44. Because the position of the curved portion46in the X direction is different between the multiple sidewalls45, the straight portions of the adjacent sidewalls45are positioned adjacently in the two Y directions as viewed from the curved portion46of one sidewall45. Accordingly, as illustrated as a region a inFIG. 4C, there is a narrow spacing to the adjacent sidewall45on the side of the protrusion of the curved portion46. On the other hand, as illustrated as a region β inFIG. 4C, there is a wide spacing to the adjacent sidewall45on the side of the recess of the curved portion46.

Continuing, pillars47are formed in a portion of the region between the mutually-adjacent sidewalls45to link the sidewalls45to each other. Specifically, the pillars47are formed in a first portion and a second portion of the region between the mutually-adjacent sidewalls45. The first portion is between a portion of the region between the mutually-adjacent sidewalls45where the spacing between the sidewalls45is narrow and a portion of the region between the mutually-adjacent sidewalls45where the spacing between the sidewalls45is wide. The portion where the spacing between the sidewalls45is narrow is interposed between the first portion and the second portion. The pillars47are formed by, for example, depositing a mask material on the entire surface and by subsequently selectively removing the mask material using lithography. The pillars47are formed of a material that has etching selectivity with the insulating film41and the sidewalls45. The pillars47are formed of, for example, a coating-type organic film in the case where, for example, the insulating film41is formed of silicon oxide and the sidewalls45are formed of silicon nitride. Specifically, the pillars47are formed by forming an organic film by coating, forming a silicon oxide film thereon by coating, forming a resist film thereon, patterning the resist film, transferring the pattern of the resist film onto the silicon oxide film, and then transferring the pattern onto the organic film.

Then, as illustrated inFIG. 4D, etching such as RIE (reactive ion etching), etc., is performed using the sidewalls45and the pillars47as a mask. Thereby, multiple trenches48are made in the portions of the insulating film41excluding the regions directly under the sidewalls45and the pillars47. In other words, the pattern of the sidewalls45and the pillars47is inverted and transferred onto the insulating film41of the lower layer. In each of the trenches48, a portion having a width wider than those of the other portions and a portion having a width narrower than those of the other portions are formed on two sides of the region directly under the curved portion46of the sidewall45. The trenches48are discontinuous in the regions directly under the pillars47. Subsequently, the sidewalls45and the pillars47are removed.

Continuing, a conductive material is filled into the trenches48. Thereby, the interconnects14are formed inside the trenches48. At this time, the protrusion31and the recess32are formed respectively in the interconnects14on two sides of the region directly under the curved portion46of the sidewall45. The region directly under the pillar47becomes the slit33without the interconnect14being formed. In such a case, in the process illustrated inFIG. 4Adescribed above, all of the positions of the protrusions31in the X direction are different from each other because all of the positions of the protrusions43and the positions of the recesses44in the X direction are different from each other.

Then, as illustrated inFIG. 2andFIG. 3, the inter-layer insulating film22is formed on the insulating film41and the interconnects14. Continuing, contact via holes are made in the inter-layer insulating film22using, for example, lithography. The contact via hole is made to reach the portion of each of the interconnects14having the width wider than those of the other portions, i.e., the portion where the protrusion31is formed. Then, the contact vias16are formed by filling a conductive material into the contact via holes. The lower end of the contact via16is connected to the portion of each of the interconnects14having the width wider than those of the other portions. Thus, one of the contact vias16is connected to each of the interconnects14. Then, the multiple interconnects15extending in the Y direction are formed on the inter-layer insulating film22. Each of the interconnects15is connected to the upper end of one of the contact vias16. Then, the inter-layer insulating film23is formed on the inter-layer insulating film22to cover the interconnects15. Thereby, the integrated circuit device1is manufactured.

Operational effects of the embodiment will now be described.

In the embodiment, the arrangement period of the interconnects14can be smaller because the interconnects14are formed using the sidewall process. Thereby, higher integration of the integrated circuit device1can be realized.

Normally, in the sidewall process, the widths and the spacing of the interconnects are uniform because the widths of the sidewalls are uniform.

Conversely, in the embodiment, the protrusion43and the recess44are formed in the core member42in the process illustrated inFIG. 4A. Thereby, the curved portion46is formed in the sidewall45in the process illustrated inFIG. 4C; and the protrusion31and the recess32are formed in the interconnect14in the process illustrated inFIG. 4D. As a result, the portion of the interconnect14where the protrusion31is formed is wider than the other portions. Because the contact via16is connected to the portion where the protrusion31is formed, the diameter of the contact via16can be larger even when anticipating margins for the alignment shift and the fluctuation of the dimensions of the contact via16. Therefore, the degree of difficulty of the lithography when making the contact via holes in the inter-layer insulating film22is reduced; and the formation of the contact vias16is easier. Thereby, the cost of the manufacturing equipment can be reduced; and the manufacturing cost can be reduced. The resistance of the contact vias16can be reduced by increasing the diameters of the contact vias16. Thereby, the reliability and the yield of the integrated circuit device increase.

Because the protrusion31and the recess32of the interconnect14are formed on two sides of the curved portion46of the sidewall45, the protrusion31of one interconnect14of two mutually-adjacent interconnects14opposes the recess32of the other interconnect14. Thereby, the interconnects14do not short easily to each other even in the case where the protrusions31are formed because the distance between the interconnects14is maintained at substantially a constant.

In the embodiment, the pillars47are formed at prescribed positions between the sidewalls45in the process illustrated inFIG. 4C. Thereby, the slits33are made in the interconnect14; and the portion of the interconnect14where the recess32is formed is separated from portions of the same interconnect14on two X-direction sides while being separated from the portion where the protrusion31is formed, i.e., the portion where the contact via16is connected; and the portion of the interconnect14where the recess32is formed is in an electrically floating state. Therefore, even in the case where the contact via16connected to one interconnect14is shorted to the recess32of an adjacent interconnect14, problems do not occur because the shorted portion of the adjacent interconnect14is in a floating state.

A comparative example of the embodiment will now be described.

FIG. 5is a plan view illustrating the draw-out region of an integrated circuit device according to the comparative example.

In the comparative example as illustrated inFIG. 5, interconnects114are formed using a normal sidewall process. Each of the interconnects114is divided in one location.

As illustrated inFIG. 5, although it is possible to reduce the arrangement period of the interconnects114in the case where the interconnects114are formed using the sidewall process, the widths and the spacing of the interconnects114are uniform. Therefore, in the case where a contact via116is formed to connect to each of the interconnects114, it is necessary to make the contact via116sufficiently fine to prevent the contact via116from shorting to the interconnect114adjacent to the interconnect114to be connected to. As a result, as the interconnects114are downscaled, the contact vias116also become finer; the formation of the contact vias116becomes difficult; and the resistance of the contact vias116undesirably increases.

For example, it is assumed that there is no dimensional fluctuation of the contact via and that the alignment shift of the contact via is not more than half of the arrangement period of the interconnects. In such a case, in the comparative example, it is necessary for the diameter of the contact via116to be not more than half of the arrangement period of the interconnects114to prevent the contact via116from shorting to the interconnect114adjacent to the interconnect114to be connected to. As downscaling is performed, in addition to the formation of the contact vias themselves becoming difficult, the resistance increase of the contact vias also can no longer be ignored. Conversely, in the first embodiment, the diameter of the contact via16can be increased to 1.5 times the arrangement period of the interconnects14because problems do not occur even in the case where the contact via16is shorted to the interconnect14adjacent to the interconnect14to be connected to.

A second embodiment will now be described.

FIG. 6is a plan view illustrating the draw-out region of an integrated circuit device according to the embodiment.

As illustrated inFIG. 6, the integrated circuit device2according to the embodiment differs from the integrated circuit device1according to the first embodiment described above (referring toFIG. 2) in that the directions in which the protrusions31of two mutually-adjacent interconnects14protrude are opposite to each other. For example, in the example illustrated inFIG. 6, the protrusion31of the interconnect14aprotrudes in the −Y direction; and the protrusion31of the interconnect14bprotrudes in the +Y direction.

A method for manufacturing the integrated circuit device according to the embodiment will now be described.

FIGS. 7A to 7Dare process plan views and cross-sectional views of processes, illustrating the method for manufacturing the integrated circuit device according to the embodiment.

In the embodiment as illustrated inFIG. 7A, the protrusion43and the recess44are formed in the side surface on the same side of the core member42, e.g., in the side surface on the +Y direction side, when forming the core members42on the insulating film41. In other words, the protrusion43protrudes from the side surface of the core member42on the +Y direction side by the dimension a in the +Y direction. On the other hand, the recess44recedes from the side surface of the core member42on the +Y direction side by the dimension a in the −Y direction.

The subsequent processes are similar to those of the first embodiment described above. In other words, slimming of the core members42is performed as illustrated inFIG. 7B; and the sidewalls45are formed on the two side surfaces of the core members42as illustrated inFIG. 7C. In such a case, a sidewall45having the curved portion46formed in two locations is arranged alternately with a sidewall45in which the curved portions46are not formed. The curved portions46formed in the two locations of the same sidewall45have protrusions in mutually opposite directions. Then, the trenches48are made by etching the insulating film41using the sidewalls45and the pillars47as a mask; and the interconnects14are formed by filling a conductive material into the trenches48. Thereby, the integrated circuit device2illustrated inFIG. 6is manufactured.

Otherwise, the configuration, the manufacturing method, and the operational effects of the embodiment are similar to those of the first embodiment described above.

A third embodiment will now be described.

FIG. 8is a plan view illustrating the draw-out region of an integrated circuit device according to the embodiment.

As illustrated inFIG. 8, the integrated circuit device3according to the embodiment differs from the integrated circuit device1according to the first embodiment described above (referring toFIG. 2) in that a bent portion (a curved portion)51is formed in each of the interconnects14instead of the protrusion31(referring toFIG. 2). At the bent portion51, the interconnect14is curved to form a protrusion toward one direction. In the embodiment, the direction of the protrusion of the bent portion51, e.g., the +Y direction, is the same for all of the interconnects14. The width of the interconnect at the bent portion51is substantially the same as the widths of the portions of the interconnect14other than the bent portion51.

The position of the bent portion51in the X direction is different between the interconnects14. Therefore, the straight portions of the adjacent interconnects14are positioned adjacently in the two Y directions as viewed from the bent portion51of one interconnect14. Accordingly, as illustrated as the region a inFIG. 8, there is a narrow spacing to the adjacent interconnect14on the side of the protrusion of one bent portion51as viewed from the bent portion51. On the other hand, as illustrated as the region1inFIG. 8, there is a wide spacing to the adjacent interconnect14on the side of the recess of the bent portion51. The lower end of the contact via16is connected to the bent portion51of each of the interconnects14. Because the bent portion51has a protrusion in the +Y direction, the central axis of the contact via16is displaced toward the +Y direction side with respect to the central axis of the portions of the interconnect14other than the bent portion51as viewed from the Z direction.

The slits33are made in two locations of each of the interconnects14; and each of the interconnects14is divided into three. In other words, an opposing portion52of a second interconnect14adjacent to a first interconnect14and disposed in the direction of the protrusion of the bent portion51of the first interconnect14as viewed from the first interconnect14to oppose the bent portion51of the first interconnect14is separated from portions of the second interconnect14on two sides of the opposing portion52and is separated also from the bent portion51of the second interconnect14. Accordingly, the opposing portion52is in an electrically floating state.

Otherwise, the configuration of the embodiment is similar to that of the first embodiment described above.

A method for manufacturing the integrated circuit device according to the embodiment will now be described.

FIGS. 9A to 9Dare process plan views and cross-sectional views of processes, illustrating the method for manufacturing the integrated circuit device according to the embodiment.

In the embodiment, the interconnects14are formed using the sidewall process and etching.

First, as illustrated inFIG. 9A, the inter-layer insulating film21is formed on the silicon substrate10(referring toFIG. 3); and a conductive film61is formed thereon. Then, multiple core members62extending in the X direction are formed on the conductive film61. The configuration of the core members62is the same as the configuration of the core members42of the first embodiment described above (referring toFIG. 4A). In other words, a protrusion63protruding by the dimension t in the +Y direction is formed on the side surface on the +Y direction side of the first portion of each of the core members62; and a recess64receding by the dimension t in the +Y direction is formed in the side surface on the −Y direction side of the second portion separated from the first portion. For the multiple core members62, all of the positions of the protrusions63and the positions of the recesses64in the X direction are different from each other.

Then, as illustrated inFIG. 9B, slimming is performed on the core members62to make the core members62finer.

Continuing as illustrated inFIG. 9C, sidewalls65are formed on the side surfaces of the core members62. Then, the core members62are removed. The configuration of the sidewalls65is the same as that of the sidewalls45of the first embodiment described above (referring toFIG. 4C). In other words, the portion of the sidewall65formed on the side surface of the protrusion63of the core member62is a curved portion66that is curved along the side surface of the protrusion63. Similarly, the portion of the sidewall65formed on the side surface of the recess64of the core member62is a curved portion66that is curved along the side surface of the recess64. Because the position of the curved portion66in the X direction is different between the multiple sidewalls65, the straight portions of the adjacent sidewalls65are positioned adjacently in the two Y directions as viewed from the curved portion66of one sidewall65. Accordingly, as viewed from the curved portion66, there is a narrow spacing to the adjacent sidewall65on the side of the protrusion of the curved portion66as illustrated as the region a; and there is a wide spacing to the adjacent sidewall65on the side of the recess of the curved portion66as illustrated as the region β.

Then, as illustrated inFIG. 9D, etching such as RIE, etc., is performed using the sidewalls65as a mask. Thereby, the conductive film61is patterned into the multiple interconnects14by removing the portions of the conductive film61excluding the regions directly under the sidewalls65. At this time, the portions of the conductive film61positioned in the regions directly under the sidewalls65become the interconnects14; and the portions positioned in the regions directly under the curved portions66become the bent portions51. In other words, the pattern of the sidewalls65is transferred as-is onto the conductive film61of the lower layer. Subsequently, the sidewalls65are removed.

Continuing as illustrated inFIG. 8, a resist mask (not illustrated) is formed by forming a resist film to cover the interconnects14and by patterning by exposing and developing. Then, the interconnects14are selectively removed by etching using the resist mask as a mask. Thereby, each of the interconnects14is divided into three by making the slits33in two locations of each of the interconnects14. At this time, the opposing portion52of the second interconnect14adjacent to the first interconnect14and disposed in the direction of the protrusion of the bent portion51as viewed from the first interconnect14to oppose the bent portion51of the first interconnect14is separated from portions of the second interconnect14on two sides of the opposing portion52and is separated also from the bent portion51of the second interconnect14. Also, at this time, two slits having straight line configurations extending in the Y direction are made in the resist mask; and portions of the interconnects14extending around the two end portions of the sidewalls65are divided simultaneously. The patterning of the interconnects14is performed, for example, by etching once using one resist pattern.

Then, the inter-layer insulating film22is formed on the inter-layer insulating film21and the interconnects14. Continuing, contact via holes are made in the inter-layer insulating film22using, for example, lithography. The contact via hole is made to reach the portion of each of the interconnects14where the bent portion51is formed. In such a case, the central axis of the contact via hole is positioned on the central axis of the bent portion51as viewed from the Z direction. Because the bent portion51has a protrusion on the +Y direction side, the contact via hole is displaced further toward the +Y direction side than are the portions of the interconnect14other than the bent portion51.

Continuing, the contact vias16are formed by filling a conductive material into the contact via holes. The lower end of the contact via16is connected to the bent portion51of each of the interconnects14. Then, the multiple interconnects15extending in the Y direction are formed on the inter-layer insulating film22; and the inter-layer insulating film23is formed to cover the interconnects15. Thereby, the integrated circuit device3is manufactured.

Otherwise, the manufacturing method of the embodiment is similar to that of the first embodiment described above.

Operational effects of the embodiment will now be described.

In the embodiment as well, similarly to the first and second embodiments described above, the arrangement period of the interconnects14can be smaller because the interconnects14are formed using the sidewall process. Thereby, higher integration of the integrated circuit device3can be realized.

In the embodiment, the protrusion63and the recess64are formed in the core member62in the process illustrated inFIG. 9A. Thereby, the curved portion66is formed in the sidewall65in the process illustrated inFIG. 9C; and the bent portion51is formed in the interconnect14in the process illustrated inFIG. 9D. Then, the contact via16is connected to the portion where the bent portion51is formed. Therefore, the central axis of the contact via16is displaced further toward the +Y direction side than is the central axis of the interconnect14.

Thereby, the distance from the contact via16connected to the first interconnect14to the adjacent second interconnect14positioned on the −Y direction side as viewed from the first interconnect14is large; and the contact via16does not easily short to the second interconnect14. On the other hand, although the distance from the contact via16connected to the first interconnect14to an adjacent third interconnect14positioned on the +Y direction side as viewed from the first interconnect14is small, problems do not occur even in the case where the contact via16is shorted to the third interconnect14because the opposing portion52of the third interconnect14opposing the bent portion51of the first interconnect14is in an electrically floating state. Thereby, the diameters of the contact vias16can be larger even when anticipating margins for the alignment shift and the fluctuation of the dimensions of the contact vias16. As a result, the formation of the contact vias16is easy and the resistance of the contact vias16decreases.

In the embodiment, the slits33are made in the interconnects14in the same process as the division of the portions of the interconnects14extending around the sidewalls65; and these are performed, for example, by etching once using the same single resist mask. The division of the portions extending around the sidewalls65is a process necessary to separate the interconnects14from each other even in the case where the bent portions51are not formed in the interconnects14. Accordingly, in the embodiment, it is unnecessary to provide a new process to make the slits33.

A fourth embodiment will now be described.

FIG. 10is a plan view illustrating the draw-out region of an integrated circuit device according to the embodiment.

As illustrated inFIG. 10, the integrated circuit device4according to the embodiment differs from the integrated circuit device3according to the third embodiment described above (referring toFIG. 8) in that the directions of the protrusions of the bent portions51of the two mutually-adjacent interconnects14are opposite to each other. For example, the bent portion51of the interconnect14ahas a protrusion in the −Y direction; and the bent portion51of the interconnect14bhas a protrusion in the +Y direction.

A method for manufacturing the integrated circuit device according to the embodiment will now be described.

FIGS. 11A to 11Dare process plan views and cross-sectional views of processes, illustrating the method for manufacturing the integrated circuit device according to the embodiment.

In the embodiment as illustrated inFIG. 11A, the protrusion63is formed in two locations of the core member62when forming the core members62on the conductive film61. In other words, in each of the core members62, the protrusion63protruding by the dimension t in the +Y direction is formed on the side surface on the +Y direction side of a first portion; and the protrusion63protruding by the dimension t in the −Y direction is formed on the side surface on the −Y direction side of a second portion separated from the first portion. For the multiple core members62, all of the positions of the protrusions63in the X direction are different from each other. In the embodiment, the recesses64(referring toFIG. 9A) are not formed in the core members62.

The subsequent processes are similar to those of the third embodiment described above. In other words, slimming of the core members62is performed as illustrated inFIG. 11B; and the sidewalls65are formed on the two side surfaces of the core members62as illustrated inFIG. 11C. At this time, the curved portions66of two mutually-adjacent sidewalls65have protrusions in mutually opposite directions. Then, the conductive film61is patterned into the multiple interconnects14by etching the conductive film61using the sidewalls65as a mask. Thereby, the integrated circuit device4illustrated inFIG. 10is manufactured.

In the embodiment, it is sufficient to form only the protrusion63in the core member62in the process illustrated inFIG. 11A; and the formation of the core members62is easy because it is unnecessary to form the recess64.

Otherwise, the configuration, the manufacturing method, and the operational effects of the embodiment are similar to those of the third embodiment described above.

A fifth embodiment will now be described.

The configuration of the integrated circuit device according to the embodiment is similar to that of the fourth embodiment described above (referring toFIG. 10).

FIGS. 12A to 12Dare process plan views and cross-sectional views of processes, illustrating the method for manufacturing the integrated circuit device according to the embodiment.

The embodiment differs from the fourth embodiment described above in that the recess64is formed instead of the protrusion63when forming the core members62.

In other words, as illustrated inFIG. 12A, the recess64is formed in two locations of the core member62when forming the core members62on the conductive film61. In other words, the recess64receding by the dimension t in the −Y direction is formed in the side surface on the +Y direction side of the first portion of each of the core members62; and the recess64receding by the dimension t in the +Y direction is formed in the side surface on the −Y direction side of the second portion separated from the first portion. For the multiple core members62, all of the positions of the recesses64in the X direction are different from each other. In the embodiment, the protrusions63(referring toFIG. 9A) are not formed on the core members62. The subsequent processes are similar to those of the third embodiment described above.

Otherwise, the configuration, the manufacturing method, and the operational effects of the embodiment are similar to those of the fourth embodiment described above.

A sixth embodiment will now be described.

FIG. 13is a plan view illustrating the draw-out region of an integrated circuit device according to the embodiment.

As illustrated inFIG. 13, the integrated circuit device6according to the embodiment differs from the integrated circuit device3according to the third embodiment described above (referring toFIG. 8) in that the contact via16is connected to the straight portion of the interconnect14instead of the bent portion51of the interconnect14.

In each of the interconnects14, the bent portion51curved to form a protrusion in the +Y direction is formed in a portion separated from the portion where the contact via16is connected. The bent portion51is curved to detour around the contact via16connected to the adjacent interconnect14. In other words, the bent portion51of the first interconnect14opposes the portion of the second interconnect14adjacent to the first interconnect14where the contact via16is connected and has a protrusion in a direction away from the portion of the second interconnect14where the contact via16is connected. In each of the interconnects14, the portion where the bent portion51is formed is separated from portions on two sides thereof and is separated also from the portion where the contact via16is connected. Accordingly, the portion of the interconnect14where the bent portion51is formed is in an electrically floating state.

A method for manufacturing the integrated circuit device according to the embodiment will now be described.

First, the multiple interconnects14having the bent portion51formed in one location of each are formed on the inter-layer insulating film21using the methods illustrated inFIGS. 9A to 9D.

Then, as illustrated inFIG. 13, a resist mask (not illustrated) is formed by forming a resist film to cover the interconnects14and by patterning by exposing and developing. Continuing, the interconnects14are selectively removed by performing etching using the resist mask as a mask. Thereby, each of the interconnects14is divided into three portions by making the slits33in two locations of each of the interconnects14.

At this time, in each of the interconnects14, the bent portion51is separated from portions on two sides thereof and is separated also from the portion where the contact via16is to be connected. In other words, the bent portion51of the first interconnect14is separated from portions of the first interconnect14on two sides of the bent portion51and is separated from the opposing portion52of the first interconnect14that opposes the bent portion51of the second interconnect14adjacent to the first interconnect, where the bent portion51of the second interconnect14has a protrusion in a direction away from the first interconnect14.

At this time, two slits having straight line configurations extending in the Y direction are made in the resist mask; and the portions of the interconnects14extending around the two end portions of the sidewalls65are divided simultaneously. The patterning of the interconnects14is performed, for example, by etching once using one resist pattern.

Then, the inter-layer insulating film22is formed on the inter-layer insulating film21and the interconnects14. Continuing, contact via holes are made in the inter-layer insulating film22using, for example, lithography. The contact via holes are formed to reach the opposing portions52. Then, the contact vias16are formed by filling a conductive material into the contact via holes. Continuing, the multiple interconnects15extending in the Y direction are formed on the inter-layer insulating film22; and the inter-layer insulating film23is formed to cover the interconnects15. Thereby, the integrated circuit device6is manufactured.

Operational effects of the embodiment will now be described.

In the embodiment as well, similarly to the embodiments described above, the arrangement period of the interconnects14can be smaller because the interconnects14are formed using the sidewall process. Thereby, higher integration of the integrated circuit device3can be realized.

In the embodiment as well, for reasons described below, the diameter of the contact via16can be increased. In other words, one interconnect14is taken as a first interconnect; the adjacent interconnect14disposed on the +Y direction side as viewed from the first interconnect is taken as a second interconnect; and the adjacent interconnect14disposed on the −Y direction side as viewed from the first interconnect is taken as a third interconnect. For example, inFIG. 13, a distance L1between a second interconnect14fand the contact via16connected to a first interconnect14ecan be increased and shorts can be prevented because the bent portion51of the second interconnect14fhas a protrusion in a direction away from the contact via16connected to the first interconnect, where the interconnects14e,14f, and14gare the first, the second, and the third interconnect, respectively. On the other hand, a distance L2between the first interconnect14eand the bent portion51of the third interconnect14gis small because the bent portion51of the third interconnect14ghas a protrusion in a direction toward the first interconnect. However, problems do not occur even in the case where the bent portion51of the third interconnect14gis shorted to the first interconnect14ebecause the bent portion51of each of the interconnects14is in an electrically floating state. Thereby, the contact via16can be formed with a larger diameter. As a result, the formation of the contact vias16is easy and the resistance of the contact vias16decreases.

In the embodiment, similarly to the third embodiment described above, the slits33of the interconnects14are made in the same process as the division of the portions of the interconnects14extending around the sidewalls65. Therefore, it is unnecessary to provide a new process to make the slits33.

Otherwise, the configuration, the manufacturing method, and the operational effects of the embodiment are similar to those of the third embodiment described above.

A variation of the sixth embodiment will now be described.

FIG. 14is a plan view illustrating the draw-out region of an integrated circuit device according to the variation.

As illustrated inFIG. 14, the integrated circuit device6aaccording to the variation differs from the integrated circuit device6according to the sixth embodiment described above (referring toFIG. 13) in that the bent portion51of the interconnect14contacts the adjacent interconnect14. In the case where the protruded amount of the bent portion51is not less than half of the arrangement period of the interconnects14due to, for example, fluctuation of the process conditions, etc., when manufacturing the integrated circuit device6(referring toFIG. 13), the bent portion51undesirably contacts and shorts to the adjacent interconnect14as in the variation. However, problems do not occur even in such a case because the bent portion51is in a floating state.

Otherwise, the configuration, the manufacturing method, and the operational effects of the variation are similar to those of the sixth embodiment described above.

A seventh embodiment will now be described.

FIG. 15is a plan view illustrating the draw-out region of an integrated circuit device according to the embodiment.

As illustrated inFIG. 15, the integrated circuit device7according to the embodiment differs from the integrated circuit device6according to the sixth embodiment described above (referring toFIG. 13) in that the directions of the protrusions of the bent portions51of the two mutually-adjacent interconnects14are opposite to each other. For example, the bent portion51of the interconnect14ahas a protrusion in the +Y direction; and the bent portion51of the interconnect14bhas a protrusion in the −Y direction.

A method for manufacturing the integrated circuit device according to the embodiment will now be described.

In the embodiment, for example, the interconnects14are formed by the methods illustrated inFIGS. 11A to 11D. In other words, the multiple interconnects14are formed using the sidewall process and etching using the core members62in which the protrusion63is formed on both side surfaces. Or, the interconnects14are formed by the methods illustrated inFIGS. 12A to 12D. In other words, the multiple interconnects14are formed using the sidewall process and etching using the core members62in which the recess64is formed on both side surfaces. Thereby, the directions of the protrusions of the bent portions51of the two mutually-adjacent interconnects14are opposite to each other.

Then, the contact vias16are formed using methods similar to those of the sixth embodiment described above to connect to the opposing portions52of the interconnects14, where the bent portions51of the adjacent interconnects14detour around the opposing portions52. Subsequently, the interconnects15are formed. Thus, the integrated circuit device7is manufactured.

Otherwise, the configuration, the manufacturing method, and the operational effects of the embodiment are similar to those of the sixth embodiment described above.

A variation of the seventh embodiment will now be described.

FIG. 16is a plan view illustrating the draw-out region of an integrated circuit device according to the variation.

In the integrated circuit device7aaccording to the variation as illustrated inFIG. 16, the bent portions51of two interconnects14cand14dhave protrusions in directions toward each other. Therefore, the distance between the interconnect14cand the interconnect14dis small. However, problems do not occur even in the case where the interconnect14cshorts to the interconnect14dbecause both of the interconnects14cand14dare in electrically floating states.

Otherwise, the configuration, the manufacturing method, and the operational effects of the variation are similar to those of the seventh embodiment described above.

According to the embodiments described above, an integrated circuit device in which the contact vias are formed easily and have low resistance and a method for manufacturing the same can be realized.