Gated diode having at least one lightly-doped drain (LDD) implant blocked and circuits and methods employing same

Gated diodes, manufacturing methods, and related circuits are provided wherein at least one lightly-doped drain (LDD) implant is blocked in the gated diode to reduce its capacitance. In this manner, the gated diode may be used in circuits and other applications whose performance is sensitive to load capacitance while still obtaining the performance characteristics of a gated diode. These characteristics include fast turn-on times and high conductance, making the gated diodes disclosed herein well-suited for electro-static discharge (ESD) protection circuits as one application example. The examples of the gated diode disclosed herein include a semiconductor substrate having a well region and insulating layer thereupon. A gate electrode is formed over the insulating layer. Anode and cathode regions are provided in the well region, wherein a P-N junction is formed. At least one LDD implant is blocked in the gated diode to reduce capacitance.

BACKGROUND

I. Field of the Disclosure

The technology of the present application relates to gated diodes and their use in circuits and related methods, including protection circuits, electro-static discharge (ESD) protection circuits, and high speed or switching circuits.

Electro-static discharge (ESD) is a major reliability issue in integrated circuits (ICs). ESD is a transient surge in voltage (negative or positive) that may induce a large current in a circuit. To protect circuits against damage from ESD surges, protection schemes attempt to provide a discharge path for both positive and negative ESD surges. Conventional diodes can be employed in ESD protection circuits to clamp the voltage of positive and negative ESD surges to shunt current and prevent excessive voltage from being applied to a protected circuit.FIG. 1illustrates a conventional ESD protection circuit in this regard. As illustrated inFIG. 1, a voltage rail (Vdd)10and a ground rail (GND)12are provided to power a protected circuit14. The protected circuit14can be any type of circuit and provided in any form desired. In this example, a terminal in the form of a signal pin16provides a signal path to the protected circuit14for providing information and/or control to the protected circuit14. For example, the protected circuit14may be included in an IC, with the signal pin16being an externally available pin on the IC chip.

A conventional ESD protection circuit18may be coupled between the voltage rail10and ground rail12to protect the protected circuit14from ESD surges. The exemplary ESD protection circuit18inFIG. 1includes two conventional diodes: a positive ESD surge diode20and a negative ESD surge diode22. The positive ESD surge diode20and the negative ESD surge diode22are coupled in series. The positive ESD surge diode20clamps positive voltage on the signal pin16to one diode drop above the voltage rail10. The negative ESD surge diode22clamps negative voltage on the signal pin16to one diode drop below the ground rail12. A cathode (k) of the positive ESD surge diode20is coupled to the voltage rail10. An anode (a) of the positive ESD diode20is coupled to the signal pin16at a node24on the signal path between the signal pin16and the protected circuit14. A cathode (k) of the negative ESD surge diode22is also coupled to the node24on the signal path from the signal pin16to the protected circuit14. An anode (a) of the negative ESD surge diode22is coupled to the ground rail12.

For positive ESD surges on the signal pin16, the positive ESD surge diode20will become forward biased and clamp voltage on the signal pin16to one diode drop above the voltage rail10to protect the protected circuit14. Energy from such an ESD surge will be conducted through the positive ESD surge diode20in a forward biased mode and dispersed into the voltage rail10. Appropriate ESD protection structures may be implemented (not shown) in the voltage rail10to eventually dissipate a positive ESD surge to the ground rail12. For negative ESD surges on the signal pin16, the surge is similarly dissipated. A negative ESD surge on the signal pin16will place the negative ESD surge diode22in a forward biased mode thus providing a low-impedance path relative to the protected circuit14. Energy from the negative ESD surge will be dissipated into the ground rail12.

Because circuits are increasingly being provided in system-on-a-chip (SOC) configurations due to higher transistor counts, providing ESD protection in SOC technologies is becoming increasingly important. SOC technologies may employ field effect transistors (FETs) that provide a relatively thin oxide gate dielectric. These relatively thin dielectrics are susceptible to destructive breakdown and damage by excessive voltages from an ESD surge event. Further, conventional diodes, such as the ESD surge diodes20,22provided inFIG. 1, may not provide sufficient conduction for ESD protection in SOC technology.

To address these shortcomings in ESD protection, and for SOC technologies in particular, shallow trench isolation (STI) diodes have been provided in ESD protection circuits. Gated diodes are also being employed in ESD protection circuits. It has been shown that use of a gated diode has superior conductance per unit length as well as turn-on speed due to the transient path of its carriers. Turn-on speed of an ESD protection circuit is important for meeting charge device modeling (CDM) specifications where large amounts of current (e.g., several amps) can flow in a very small fraction of time (e.g., less than a nanosecond) during ESD events. However, even with these advantages of gated diodes, STI diodes are predominantly used in ESD protection circuits for high speed circuits. Gated diodes can unacceptably decrease performance. A gated diode has greater perimeter capacitance per unit diffusion or active length than an STI diode. This is illustrated by example in the modeling graph26ofFIG. 2, where input capacitance (C) of a gated diode pair28and an STI diode pair30corresponding toFIG. 1is plotted versus input voltage (V). This example assumes a 65 nanometer (nm) process. As shown, the input capacitance (C) of the gated diode pair28, which is normalized to the maximum capacitance of the STI diode pair30, is higher than the input capacitance (C) of the STI diode pair30for given voltage (V), length, and width of the diodes (approximately 8.0 and 0.45 micrometers (μm), respectively). For example, at the rail voltage (Vdd), the normalized capacitance (C) of the gated diode pair28is nearly 1.8 whereas the normalized capacitance (C) of the STI diode pair30is approximately 1.0. This equates to the gated diode pair28having an approximately eighty percent (80%) increase in capacitance over the STI diode pair30in this example.

Increased perimeter capacitance in a gated diode increases the load capacitance when the gated diode is added to a protected circuit. Increasing load capacitance can negatively affect protected circuits. For example, increased load capacitance can decrease switching times and frequency performance of a protected circuit, because charging time will be increased due to the ESD protection circuit being coupled to the protected circuit in an R-C circuit arrangement. Further, increased capacitance provided as a result of inserting an ESD protection circuit can decrease the sensitivity of radio frequency (RF) components, such as a low noise amplifier (LNA). However, use of an STI diode having a lower capacitance in an ESD protection circuit also has a trade off over a gated diode. Use of an STI diode in an ESD protection circuit can result in low CDM voltage tolerances for the protected circuit for both positive and negative surges, and especially for protected circuits and related processes employing thin oxide gate oxide dielectric devices coupled to a pad that can be found in large SOC chips.

To preserve performance, chip manufacturers and customers have had to accept the lower CDM voltage tolerances provided by use of STI diodes in ESD protection circuits, which results in greater ESD-related exposure and failures. Thus, a need exists to provide an ESD protection circuit that exhibits superior conductance and turn-on time as well as a low capacitance so as to not adversely affect performance of a protected circuit.

SUMMARY OF THE DISCLOSURE

Embodiments disclosed in the detailed description include examples of gated diodes, exemplary methods of manufacture of the same, and related circuits and methods. The gated diode examples all have at least one lightly-doped drain (LDD) implant blocked to reduce capacitance of the gated diode. In this manner, the gated diode may be employed in circuits and other circuit applications whose performance may be sensitive to load capacitance, but also desire or require the performance characteristics of a gated diode. Benefits of a gated diode include, but are not limited to, fast turn-on times and high conductance.

In embodiments disclosed herein, the gated diode includes a semiconductor substrate having a well region. The well region includes a semiconducting material having an impurity. Impurities include either a P-doped or N-doped impurity. An insulating layer is provided on the well region. A gate electrode is formed over the insulating layer. An anode region and a cathode region are implanted in the well region on opposite sides of the gate electrode. Depending on the gated diode design, the anode region or cathode region has an impurity of opposite polarity from a well region to form a P-N junction. In one example, for a diode contained within an N-well region, the anode region has an impurity of opposite polarity impurity from the N-well region to form a P-N junction between the anode and well region. In another example, for a diode contained within a P-well region, the cathode region has an impurity of opposite polarity impurity from the P-well region to form a P-N junction between the cathode and well region. The well regions have at least one LDD implant blocked between either the anode region, the cathode region, or both the anode and cathode regions.

The gated diode having at least one blocked LDD implant can be included in any circuit, integrated circuit, or circuit application. One example includes an electro-static discharge (ESD) protection circuit. An ESD protection circuit is enhanced by fast turn-on times and high conductance characteristics of the gated diode. However, if the ESD protection circuit employs one or more of the gated diodes having at least one LDD implant blocked, the capacitance of the ESD protection circuit is reduced as well. This may allow the ESD protection circuit to be employed to protect circuits whose performance is sensitive to load capacitance while still achieving the ESD characteristics of gated diodes. Otherwise, use of gated diodes in the ESD protection circuit may not be possible without affecting the protected circuit's performance in an unacceptable manner. Other examples of protected circuits whose performance may be sensitive to load capacitance and thus may benefit from the gated diodes disclosed herein include high speed differential input/output circuits and radio frequency (RF) circuits, including but not limited to low noise amplifiers (LNAs).

DETAILED DESCRIPTION

With reference now to the drawing figures, several exemplary embodiments of the present disclosure are described. The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

Embodiments disclosed in the detailed description include examples of gated diodes, exemplary methods of manufacture of the same, and related circuits and methods. The gated diode examples all have at least one lightly-doped drain (LDD) implant blocked to reduce capacitance of the gated diode. In this manner, the gated diode may be employed in circuits and other circuit applications whose performance may be sensitive to load capacitance, but also desire or require the performance characteristics of a gated diode. Benefits of a gated diode include, but are not limited to, fast turn-on times and high conductance.

In embodiments disclosed herein, the gated diode includes a semiconductor substrate having a well region. The well region includes a semiconducting material having an impurity. Impurities include either a P-doped or N-doped impurity. An insulating layer is provided on the well region. A gate electrode is formed over the insulating layer. An anode region and a cathode region are implanted in the well region on opposite sides of the gate electrode. Depending on the gated diode design, the anode region or cathode region has an impurity of opposite polarity from a well region to form a P-N junction. In one example, for a diode contained within an N-well region, the anode region has an impurity of opposite polarity impurity from the N-well region to form a P-N junction between the anode and well region. In another example, for a diode contained within a P-well region, the cathode region has an impurity of opposite polarity impurity from the P-well region to form a P-N junction between the cathode and well region. The well regions have at least one LDD implant blocked between either the anode region, the cathode region, or both the anode and cathode regions.

Before discussing particular examples of gated diodes having one or more blocked lightly-doped drain (LDDs) implants, an example of a gated diode having LDD implants is first explained.FIG. 3illustrates a gated diode32having LDD implants. The gated diode32is based on a metal oxide semiconductor (MOS) design, which is also used for MOS field effect transistors (MOSFETs). The gated diode32demonstrates superior forward bias conductance (e.g., 100 mS/μm of stripe length) as well fast turn-on times, (e.g., on the order of one-hundred (100) picoseconds or less). As illustrated, the gated diode32includes a base semiconductor substrate34for depositing of other materials to form the gated diode32. The semiconductor substrate34may be formed from a Silicon (Si) wafer, because Silicon wafers are relatively inexpensive. Alternatively, the semiconductor substrate34may be formed from any other semiconducting material desired. The semiconductor substrate34illustrated is an N-type gated diode having a P-well semiconducting material36forming a channel in a P-type substrate38. However, the semiconductor substrate34could also be a P-type gated diode having an N-well semiconducting material formed in a P-type substrate having voltages and operations complimentary to an N-type gated diode. Other variants can include the diode structure ofFIG. 3surrounded by a deep N-well that is implanted into the P-type substrate38.

Several semiconducting sub-regions are provided in the P-well semiconducting material36that are tailored to form the active device region of the gated diode32. The sub-regions comprise an N+ doped region40, an N-type LDD implant42, a P+ doped region44, and a P-type LDD implant46. The N+ doped region40form an anode region, and the P+ doped region44forms a cathode region. These symbols indicate the type and amount of relative impurities introduced into the P-well semiconducting material36. The N+ doped region40may be coupled to an electrical conductor to provide a cathode (k), or a source (S) node terminal48for the gated diode32. The P+ doped region44may also be coupled to an electrical conductor to provide an anode (a), or a drain (D) node terminal50for the gated diode32. The gated diode32also includes a gate electrode (G)52that is isolated from the P-well semiconducting material36, the cathode terminal48, and the anode terminal50by an insulating layer56. The insulating layer56is often referred to as an oxide layer, although other insulating materials are possible. The insulating layer56may be of any thickness desired, but typically is very thin and may have a thickness between approximately 12 Angstroms (Å) and 80 Å as an example. The gate electrode52may be formed from a conventional conducting material, but is provided in the form of polycrystalline silicon (“Polysilicon”) in this example, as is well known.

Spacer regions58A,58B are also provided on each side of a gate terminal54as a result of a leftover residual insulating material placed over the gated diode32that were subsequently etched. The spacer regions58A,58B allow the N-type and P-type implants40,44to be formed in the P-well semiconducting material36after spacer formation. The N-type and P-type LDD implants42,46are formed before spacer deposition. In MOSFETs, LDD implants are included to increase operating voltage and long term reliability of MOSFETs. Specifically, the LDD implants reduce the electro-static cross section of the drain so that electrostatic coupling between the drain and source is small. Otherwise, an electro-static drain to source coupling field will cause increase off state or leakage current though drain induced barrier lowering (DIBL) when the MOSFET's gate to source potential is in the off state. Since MOSFETs can be bi-directional and because of process constraints, the LDD is applied to both sides of the MOSFET gate. Thus, by providing N-type and P-type LDD implants42,46in a MOSFET, a much smaller electro-static cross section is present so that an electric field at either the source or drain terminal is spread out and is not as intense so as to provide the MOSFET with a low leakage current. Also, the field reduction at the drain through application of the LDD implant improves hot electron reliability. These N-type and P-type LDD implants42,46are included in the gated diode32since the gated diode32is based on a MOSFET design and mask.

Thus in summary, the gated diode32is a three-terminal device as illustrated inFIG. 4. The three terminals are the cathode terminal48, the anode terminal50, and the gate terminal54. A P-N junction exists between the P-well semiconducting material36and the N+ doped region40. Current can flow with relative ease from the anode terminal50to the cathode terminal48coupled to the N+ doped region40when a positive voltage difference is present between the anode terminal50and the cathode terminal48. The gate terminal54is attached to the terminal whose diffusion region polarity is the same well region polarity. In the case ofFIG. 3, the gate terminal54would be coupled to the anode terminal50since the anode terminal50is coupled to the P+ doped region44which is of the same polarity as the P-well semiconducting material36. The coupling arrangement is made to minimize capacitive loading on the cathode terminal48which, for this polarity diode, can be coupled to the input/output (I/O) pad while the anode is coupled to a second voltage rail or ground. The gate has no electrical purpose in the operation of the diode as a protection element and is used as a fabrication vehicle to separate the N+ doped region40and P+ doped region44without an intervening STI region.

The gated diode32has several sources of parasitic capacitances that all add together to generate a total capacitance for the gated diode32. As noted earlier, for the diode polarity ofFIG. 3, the node coupled to the I/O is the cathode terminal48which should have as little capacitance as possible with respect to the power supply coupled to the anode terminal50. For the common configuration, the gate terminal54is tied to the anode terminal50. For the cathode terminal48which couples to a signal pad, a first parasitic capacitance is present due to the perimeter capacitance caused by the gate electrode52(hereinafter “gate capacitance”) overlapping the N-type LDD implant42. The insulating layer56between these materials acts as a dielectric to form the parallel plate capacitance. For example, a parasitic capacitance component is provided across the insulating layer56between the gate electrode52and the N-type LDD implant42overlapping the insulating layer56labeled “C G-NLDD” inFIG. 3. A parasitic capacitance can also be similarly formed between the gate electrode52and the P-type LDD implant46overlapping the insulating layer56labeled “C G-PLDD”. Capacitance increases inversely proportional to the width of the insulating layer56. The cathode of the gated diode32has a larger parasitic capacitance than a STI diode, because the STI diode has no gate electrode. Higher perimeter capacitance equates to a higher overall capacitance which can adversely impact the performance of a protected circuit when the gated diode32is employed in an ESD protection circuit.

Another parasitic capacitance is formed between the sidewall of the N-type LDD implant42between the P-well semiconducting material36labeled “C NLDD-P-well”. A higher concentration in doping of the P-well semiconducting material36between the insulating layer56and the N-type LDD implant42also contributes to an increase in this parasitic capacitance. These factors all contribute to an overall increase in parasitic capacitance of the cathode of the gated diode32.

It was discovered in certain modeling that approximately one-third of the total parasitic capacitance of the gated diode32came from the gate overlap capacitance. This is illustrated by example in the modeling graph60ofFIG. 5. Therein, the percentage of input gate overlap component of capacitance to the total input capacitance of the pad input16ofFIG. 1using two complimentary gated diodes wherein the capacitance is referenced to signal grounds12and10. The gated diode32whose anode is coupled to a second voltage rail or ground and a complimentary P+/N-well diode whose cathode is coupled to Vdd(1.2V) gated is plotted on line62versus voltage (V). As previously discussed, the gate capacitance is the capacitance caused as a result of the presence of the gate electrode52. The gate electrode52may cause a perimeter parasitic capacitance across the insulating layer56between other materials of the gated diode32, including the LDD implants42,46and the other regions. As shown, the percentage of gate capacitance as a percentage of total capacitance of the gated diode32ranges between approximately thirty-two percent (32%) and thirty-four percent (34%) over the input voltage (V) range.

In embodiments disclosed herein, the parasitic capacitance of a gated diode is reduced by blocking either an N-type LDD implant, a P-type LDD implant, or both from a gated diode mask. Blocking means that the LDD implant is left out of the formation of the gated diode32. This is illustrated by example inFIG. 6. Therein, an exemplary gated diode32′ is shown. The gated diode32′ is provided in a semiconductor package that is integrated into a semiconductor die and which can be mounted in a printed circuit board (PCB). The gated diode32′ has the same characteristics of the gated diode32ofFIG. 3, except that the N-type LDD implant42is blocked in the gated diode32′ inFIG. 6. Blocking of the N-type LDD implant42reduces parasitic capacitance that would have been formed between the side wall of the N-type LDD implant42and the P-well semiconducting material36(shown as “C NLDD-P-well” inFIG. 3), because the N-type LDD implant42is no longer present. Also, the strong gate electrode52overlap of the N-type LDD implant42capacitance is eliminated. For example, the total parasitic capacitance of the gated diode32′ inFIG. 6may be between 0.6 fF/μm of Stripe Length and 1.2 fF/μm of Stripe Length. A small fringe parasitic capacitance will still be present between the gate electrode52and the N+ doped region40, but it will be much lower due to the increased distance between the N+ doped region40and the gate electrode52.

Blocking the N-type LDD implant42will not adversely affect the gated diode32′ as it would a MOSFET, as previously described above, because of the issues of hot electrons and drain induced barrier lowering present in MOSFETs. These issues do not affect the gated diode32′, because there is no surface conduction. Blocking of the N-type LDD implant42will also not adversely impact the turn-on time or conductance of the gated diode32′. Further, the failure current level of the gated diode32′ may be higher when the N-type LDD implant42is blocked thus increasing the current shunting performance of ESD protection circuits employing the gated diode32′. This is because the failure current level of the gated diode32′ is in part dependent on heating effects. Heating effects have a greater effect on the gated diode32′ if an LDD implant is provided due to the lower temperature at which the intrinsic carrier concentration exceeds the doping level of the LDD. The heavier doped N+ region has a higher doping level and, therefore, a higher intrinsic temperature than the LDD region. Above the intrinsic temperature, the temperature coefficient goes from negative to a large positive value causing runaway heating.

FIG. 7illustrates an example of a complimentary P-type gated diode32″ having a reduced parasitic capacitance by blocking of a P-type LDD implant. In this example, the P-type LDD implant46in the gated diode32ofFIG. 3is blocked as opposed to the N-type LDD implant42. This is illustrated in the gated diode32″ ofFIG. 7. In this example, a semiconductor substrate34″ is provided in the form of an N-well semiconducting material64formed in a P-type substrate66to form a P-type gated diode. A P-N junction is formed between the N-well semiconducting material64and P+ doped region44. This is opposed to the N-type gated diode32′ inFIG. 6. Filled-in shallow trench isolation (STI) trenches68A,68B are also included between the N+ and P+ doped regions40,44, the cathode and anode terminals48,50, respectively, and the semiconductor substrate34″. The filled-in STI trenches68A,68B provide isolation to prevent or reduce electrical current leakage between the cathode and anode terminals48,50and the semiconductor substrate34″.

The P-type LDD implant46is blocked in the gated diode32″ ofFIG. 7leaving the N-type LDD implant42unblocked. Blocking of the P-type LDD implant46reduces parasitic capacitance that would have been formed between the side wall of the P-type LDD implant46and the N-well semiconducting material64had the P-type LDD implant46not been blocked. For example, the total parasitic capacitance of the gated diode32″ inFIG. 7may be between 0.6 fF/μm of Stripe Length and 1.2 fF/μm of Stripe Length. Some parasitic capacitance will still be present between the gate electrode52and the P+ doped region44, but it will be much lower due to the increased distance between the P+ doped region40and the gate electrode52.

Again, blocking the P-type LDD implant46will not adversely affect the gated diode32″ as it would a MOSFET for example, as previously described above, because of the issues of hot electrons and drain induced barrier lowering (DIBL). These issues do not affect the gated diode32″, because the diode relies on bulk conduction via junction based carrier injection and not on a gate induced surface inversion layer and because DIBL does not affect leakage current. Blocking of the P-type LDD implant46will also not adversely impact the turn-on time or conductance of the gated diode32″. Further, the failure current level of the gated diode32″ may be higher when the P-type LDD implant46is blocked, thus increasing the current shunting performance of ESD protection circuits employing the gated diode32″. This is because the failure current level of the gated diode32″ is in part dependent on heating effects. Heating effects have a greater effect on the gated diode32″ if an LDD implant is provided due to the intrinsic carrier concentration provided by the addition of an LDD implant.

Blocking the N-type LDD implant42, as illustrated in the gated diode32″ inFIG. 7, is not necessary. However, masking of the gated diode32″ may be well facilitated if the blocking is done over the entire gated diode32″ rather than trying to divide up the masking along the middle of the gate electrode52. In this regard,FIG. 8illustrates yet another example of a P-type gated diode32′″. In this example, the P-type gated diode32′″ has a reduced parasitic capacitance by blocking both N-type and P-type LDD implants. In this example, both the N-type and P-type LDD implants42,46are blocked in the gated diode32′″. This is illustrated in the gated diode32′″ inFIG. 8. In this example, a semiconductor substrate34′″ is provided in the form of the N-well semiconducting material64formed in the P-type substrate66to form a P-type gated diode, as provided in the gated diode32″ ofFIG. 7. Filled-in shallow trench isolation (STI) trenches68A,68B are also included between the N+ and P+ doped regions40,44, the cathode and anode terminals48,50, and the semiconductor substrate34′″. The filled-in STI trenches68A,68B provide isolation to prevent or reduce electrical current leakage between the cathode and anode terminals48,50and the semiconductor substrate34′″.

Both the N-type and P-type LDD implants42,46are blocked in the gated diode32′″ ofFIG. 8. Blocking of the N-type and P-type LDD implants42,46reduces the parasitic capacitance that would have been formed between the side walls of the N-type and P-type LDD implants42,46and the N-well semiconducting material64had the N-type and P-type LDD implants42,46not been blocked. For example, the total parasitic capacitance of the gated diode32′″ inFIG. 8may be between 0.6 fF/μm of Stripe Length and 1.2 fF/μm of Stripe Length. Some parasitic capacitance will still be present between the gate electrode52and the N+ and P+ doped regions40,44, but it will be much lower due to the increased distance between the N+ and P+ doped regions40,44and the gate electrode52. Further, blocking the N-type and P-type LDD implants42,46will not adversely affect the gated diode32′″ as it would a MOSFET for example, as previously described above.

A gated diode having at least one blocked LDD implant, such as the gated diodes32,32′,32″ and32′″ discussed above, can be included in any circuit, integrated circuit, or circuit application. One example includes an electro-static discharge (ESD) protection circuit. The ESD protection circuit may be configured like the ESD protection circuit18illustrated inFIG. 1, where one or more of the conventional ESD surge diodes20,22are replaced by one or more gated diodes having at least one blocked LDD implant. Employing one or more gated diodes having at least one LDD implant blocked in an ESD protection circuit enhances voltage clamping times due to the fast turn-on time of a gated diode as well as shunting excessive current as a result of the gated diode's high conductance properties. Also, the use of one or more gated diodes having at least one LDD implant blocked reduces the load capacitance of an ESD protection circuit. This may allow an ESD protection circuit to be employed to protect circuits whose performance is sensitive to load capacitance while still achieving the ESD characteristics of gated diodes. Reducing load capacitance may be important in the protected circuit operating properly, including at desired performance, speed, and/or sensitivity.

A gated diode having at least one LDD implant blocked may be used in any device or circuit, and may be used particularly for circuits whose performance may be sensitive to load capacitance. Examples of such devices and circuits include high speed differential input/output circuits and radio frequency (RF) circuits, including but not limited to low noise amplifiers (LNAs).FIG. 9illustrates a transceiver70as one possible device and/or integrated circuit for providing a protection circuit employing one or more gated diodes having at least one LDD implant blocked to protect a low noise amplifier (LNA). The gated diode or diodes employed in the protection circuit may be one or more of the gated diodes32′,32″,32′″ previously described. The transceiver70may be implemented in semiconductor-on-insulator (SOI) and/or SOC technology. The transceiver70may be employed in any device, including, as examples, a mobile telephone or terminal, personal digital assistant (PDA), wireless Local Area Network (LAN), or other similar wireless communication device(s).

As illustrated inFIG. 9, the transceiver70may include a receiver front end72, a radio frequency (RF) transmitter74, an antenna76, a switch78, and a processor80. The receiver front end72receives information bearing radio frequency signals from one or more remote transmitters (not shown). A low noise amplifier (LNA)82amplifies an incoming signal received by the antenna76. A protection circuit84is added to the receiver front end72to protect the LNA82and downstream circuitry from surges, including ESD surges. However, adding load capacitance to the LNA82could decrease its sensitivity. In this regard, the protection circuit84can incorporate at least one gated diode having at least one LDD implant blocked. In this manner, the added load capacitance from the protection circuit84is reduced while still providing the superior turn-on time and high conductance handling capability through use of a gated diode in the protection circuit84. The gated diode or diodes employed in the ESD protection circuit84may be one or more of the gated diodes32′,32″,32′″ previously described. Further, the protection circuit84may be an ESD protection circuit and may be configured like the ESD protection arrangement and ESD protection circuit18illustrated inFIG. 1, or any other arrangement or circuit desired. For example, a gated diode may be provided to clamp an excessive positive voltage, an excessive negative voltage, or both, to shunt excessive current generated as a result.

The amplified signal leaving the LNA82may be provided to an RF subsystem86where it then may be digitized using an analog-to-digital (A/D) converter88. From there, the digitized signal may be provided to an asynchronous/synchronous integrated circuit (ASIC) or other processor80to be processed according to the application. For example, the ASIC or processor80can process the digitized, received signal to extract the information or data bits conveyed in the received signal. This processing may include demodulation, decoding, and error correction operations. The ASIC or processor80may be implemented in one or more digital signal processors (DSPs).

On the transmit side, the ASIC or processor80can receive digitized data generated as a result of the received signal, which it encodes for transmission. After encoding the data, the ASIC or processor80outputs the encoded data to the RF transmitter74. A modulator90receives the data from the ASIC or processor80and in this embodiment, operates according to one or more modulation schemes to provide a modulated signal to power amplifier circuitry92. The power amplifier circuitry92amplifies the modulated signal from the modulator90to a level appropriate for transmission from the antenna76.

FIG. 10illustrates an exemplary ESD protection circuit that may be employed as the protection circuit84in the transceiver70ofFIG. 9.FIG. 10illustrates the protection circuit84configured to protect an input of the LNA82. As illustrated, the protection circuit84includes two gated diodes93,94coupled to a bonding pad96and a transient clamp98coupled to Vdd100and Vss102. The gated diodes93,94each have at least one LDD implant blocked and may be provided according to any of the gated diodes discussed above, as examples. The protected LNA82includes a thin oxide amplifying N-channel field effect transistor (NFET)104and a source degeneration inductor106between the source (S) of the NFET104and Vss102. If a positive current is injected into the bonding pad96with respect to Vss102during a CDM event, current will flow from the bonding pad96through gated diode93to Vdd100and then from Vdd100to Vss102through the transient clamp98. The transient clamp98comprises an NFET108coupled from Vdd100to Vss102, a resistor capacitor (RC) transient detector or RC circuit110, and an inverter112acting as a buffer between the RC transient detector110and the NFET108. During a high-speed transient voltage appearing from Vdd100to Vss102, the RC transient detector110turns on the NFET108thereby allowing the NFET108to shunt a large current with a small voltage drop. During normal operation, the NFET108is biased off by the RC transient detector110.

As an example, the voltage drop between the bonding pad96and Vss102should be low enough to keep the gate (G) to source (S) voltage across the NFET104below the gate oxide rupture voltage for a pulse width of 1 nanosecond (ns), which approximately corresponds to a CDM pulse width. For a 20 Å thick oxide, the gate (G) to source (S) rupture voltage of the NFET104is approximately 6.9V for a 1 ns pulse. The source degeneration inductor106has a small effect on the gate (G) to source (S) voltage drop across the NFET104. Thus, for a positive pad to Vss102current, the gated diode93and the NFET108have a cumulative voltage drop of less than 6.9 V for CDM current amplitudes of several amps.

A gated diode or integrated circuit according to embodiments disclosed herein may be included or integrated in a semiconductor die and/or in any other device, including an electronic device. Examples of such devices include, without limitation, a set top box, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, a mobile location data unit, a mobile phone, a cellular phone, a computer, a portable computer, a desktop computer, a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a video player, a digital video player, a digital video disc (DVD) player, and a portable digital video player.

Various modifications may be made to the above gated diode structures. In particular, depending on the composition of the various layers and etches used, the order in which certain layers are placed or deposited can be varied. It will also be recognized that the order of layers and the materials forming those layers in a gated diode in the above embodiments are merely exemplary. In addition, although in the illustrated embodiment the support structures are generally depicted as round or having rounded corners, in alternate embodiments the support structures may have different shapes. Moreover, in some embodiments, other layers (not shown) may be placed or deposited and processed to form portions of a gated diode device or to form other structures on the substrate. In other embodiments, these layers may be formed using alternative deposition, patterning, and etching materials and processes, may be placed or deposited in a different order, or composed of different materials, as would be known to one of skill in the art.

It is also noted that the operational tasks described in any of the exemplary embodiments herein are described to provide examples and discussion. The operations described may be performed in numerous different sequences other than the illustrated sequences. Furthermore, operations described in a single operational task may actually be performed in a number of different tasks. Additionally, one or more operational tasks discussed in the exemplary embodiments may be combined. Those of ordinary skill in the art would also understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.