Local word line decoder for memory with 2 1/2 MOS devices

A method, a circuit, and a structure are disclosed by which the semiconductor area is reduced that a local word line decoder for a memory array requires. This reduction in area size has been achieved by eliminating one transistor of a three transistor local wordline decoder and introducing a fifth transistor which is shared by two local wordline decoders. The area occupied by the two eliminated transistors is no longer needed because the fifth transistor can be fitted between two existing transistors without an increase in area.

RELATED PATENT APPLICATION 
V1S85-130, LOCAL WORD LINE DECODER FOR MEMORY WITH 2 MOS DEVICES, filing 
date Oct. 6,1997, Ser. No. 08/944,571, assigned to a common assignee. 
BACKGROUND OF THE INVENTION 
1. Field of the Invention 
The invention relates to the field of semiconductor memory arrays, and in 
particular to reducing the semiconductor area of a wordline decoder. 
2. Description of the Related Art 
Two classes of local wordline decoders each utilizing three transistors are 
known in the related art. The circuits for these local wordline decoders 
are shown in FIGS. 1a and 1b. A circuit 100 for decoding a line 0 and an 
identical circuit 110 for decoding a line 1 are shown. P-channel 
transistor 101 (P1) and n-channel transistor 102 (N1) are connected in 
series between wordline driver input 107 and a reference potential 109. 
Input 104 (mwln0) connects to the gate of transistor 101 and 102. Output 
106 (lwl0) is connected to the junction of transistors 101 and 102. Drain 
and source of n-channel transistor 103 (N11) are connected between output 
106 and reference potential 109. The gate of transistor 103 is connected 
to input 108 (wldrn), which is the inverse of input 107. 
Referring now to FIG. 1b, circuit 110 is explained next. P-channel 
transistor 111 (P2) and n-channel transistor 112 (N2) are connected in 
series between wordline driver input 107 and a reference potential 109. 
Input 114 (mwln1) connects to the gate of transistor 111 and 112. Output 
116 (lwl1) is connected to the junction of transistors 111 and 112. Drain 
and source of n-channel transistor 113 (N21) are connected between output 
116 and reference potential 109. The gate of transistor 113 is connected 
to input 108 (wldrn), which is the inverse of input 107. 
Referring now to FIG. 2, we show a physical layout for the circuit of FIGS. 
1a/1b. Transistors 101 (P1), 102 (N1), 103 (N11), 111 (P2), 112 (N2), and 
113 (N21) are shown in an orthogonal arrangement of three columns and two 
rows. Dimension y is determined by the memory cell pitch. Referring now to 
FIG. 3, we show a more detailed layout of transistors N1, and N2. 401 and 
402 are the active areas (AA) or n-type regions (source and drain) of 
transistor N1. Region 405 is the metal oxide gate of N1. 403 and 404 are 
the AA or n-type regions (source and drain) of transistor N2. Region 406 
is the metal oxide gate of N2. N-type regions 402 and 403 connect to 
outputs 106 (lwl0) and 116 (lwl1) respectively. 
U.S. Pat. No. 5,446,698 (McClure) discloses a redundant global wordline for 
local wordlines, however, the details of the local wordline decoder are 
not discussed. U.S. Pat. No. 5,587,960 (Ferris) describes a semiconductor 
memory with sub-wordlines but does not describe the details of the 
sub-wordline decoder. 
SUMMARY OF THE INVENTION 
It is an object of the present invention to provide a method, a circuit, 
and a structure by which to reduce the semiconductor area that a local 
word line decoder for a memory array requires. 
It is another object of the present invention to reduce the chip size 
required for a memory array. 
A further object of the present invention is to improve cell utilization. 
These objects have been achieved by eliminating one transistor of a three 
transistor local wordline decoder and introducing a fifth transistor which 
is shared by two local wordline decoders. The area occupied by the two 
eliminated transistors is no longer needed because the fifth transistor 
can be fitted between two existing transistors without an increase in area 
.

DESCRIPTION OF THE PREFERRED EMBODIMENT 
Referring now to the block diagram of FIG. 4, we show a method depicting 
the present invention of sharing a n-channel metal oxide semiconductor 
(NMOS) device between a first and a second local word line decoder in a 
semiconductor memory. Block 501 provides a first local wordline decoder 
with a first local wordline lwl0 as output. Block 502 provides a second 
local wordline decoder with a second local wordline lwl1 as output. Next, 
Block 503 provides a NMOS device which connects it between the first local 
wordline lwl0 and the second local wordline lwl1. Block 503 is, thus, 
shared between the first local wordline decoder and the second local 
wordline decoder and participates in the decoding of the first and second 
local wordline. 
Referring now to FIG. 5 we show a circuit diagram depicting the preferred 
embodiment of the present invention. Decoder 500 comprises two local word 
line decoders and device 503. The first local wordline decoder 501 with a 
main word line input 104 (mwln0), p-channel transistor 101 (P1), n-channel 
transistor 102 (N1), and a first local wordline output 106 (lwl0) to 
decode the first main word line. The second local wordline decoder 502 
with a main word line input 114 (mwln1), transistors 111 (P2) and 112 (N2) 
and a second local wordline output 116 (lwl1) to decode the second main 
word line. Device 503, a n-channel transistor connects between outputs 
lwl0 and lwl1 and shares in the decoding of both outputs. P-channel 
transistor 101 (P1) and n-channel transistor 102 (N1) are connected in 
series between wordline driver 107 (wldr) and a reference potential 109. 
P-channel transistor 111 (P2) and n-channel transistor 112 (N2) are 
connected likewise. The gates of transistors 101 and 102 connect to input 
104, while the gates of transistors 111 and 112 connect to input 114. 
Output 106 connects to the junction of transistors 101 and 102, and output 
116 connects to the junction of transistors 111 and 112. N-channel 
transistor 108 (N3) source and drain connect between lwl0 and lwl1, the 
gate of 108 is connected to the inverse word line driver 108 (wldrn). 
Referring now to FIG. 6 we show the input and output signals of the circuit 
of FIG. 5. Curves 1 and 2 are inputs 104 (mwln0) and 114 (mwln1) 
respectively, where, as an illustrative example, mwln1 is at constant 
potential v.sub.h. Curves 3 and 4 are the wordline driver inputs wldr 107 
and wldrn 108 respectively. Curve 5 depicts output 106 (lwl0) at a 
positive potential for one cycle as a result of the decoding circuit of 
FIG. 5. Curve 6 shows, in this example, output 116 (lwl1) at a constant 0 
volt potential since local word line decoder 502 was not selected. 
Referring now to FIG. 7, we show for the circuit of FIG. 5 the transistor 
placement on a silicon semiconductor wafer. Transistors 101 (P1), 102 
(N1), 111 (P2), and 112 (N2) are shown in an orthogonal arrangement where 
P1 and P2 are in one column and N1 and N2 are in another but adjacent 
column and where transistors P1 and N1 are in one row and transistors P2 
and N2 are in another but adjacent row. Sandwiched between N1 and N2 is 
n-channel transistor N3 (113). Note that a third column formerly occupied 
by transistors 103 (N11) and 113 (N21) has been eliminated by this present 
invention with a considerable savings in space. 
Referring now to FIG. 8, we show a more detailed layout of transistors N1, 
N2, and N3. 401 and 402 are the active area (AA) or n-type regions (source 
and drain) of transistor N1. Region 405 is the metal oxide gate of N1, 
which attaches to input mwln0. 403 and 404 are the AA or n-type regions 
(source and drain) of transistor N2. Region 406 is the metal oxide gate of 
N2, which attaches to input mwln1. Transistor N3 (113) is now fitted 
between the AA or n-type regions 402 and 403 by utilizing regions 402 and 
403 as the source and drain of transistor N3. The separation between 402 
and 403 is no longer needed because of inserting n-channel transistor N3 
and thus relaxes the n-type separation rule for process and improves the 
yield. Metal oxide gate 407 is placed between regions 402 and 403 and 
becomes the gate of transistor N3. Metal oxide gate 407 attaches to input 
wldrn. N-type regions 402 and 403 connect to outputs lwl0 and lwl1 
respectively. Transistor N3 requires, therefore, no extra space with the 
result that the layout size will nearly be the same as that just using two 
MOS devices (P1 and N1) per local word line decoder. 
As is evident from FIG.'s 7 and 8, the metal oxide gates separating the 
n-type regions are parallel to each other, similarly the n-type regions 
are parallel to each other and to the metal oxide gates. Transistors P1 
and P2 are constructed in a fashion similar to the n-channel transistors 
N1 and N2, having p-type regions, corresponding to source and drain and 
having a metal oxide gate which separates the p-type regions. P-channel 
transistors P1 and P2 are in close proximity to the n-channel transistors 
N1 and N2. 
The advantages of this present invention are a reduced size local wordline 
decoder which results in a reduction of the chip size and an improvement 
of cell utilization by relaxing the n-type separation rule for process; it 
also improves the yield. The improvement is significant since, as the 
device fabrication process moves to 0.35 .mu.m and 0.25 .mu.m, cell size 
is shrinking faster than wordline pitch calling for local word line 
decoders for each main wordline. With the use of local wordlines the 
decoder size in turn needs to be reduced since many decoder circuits are 
required. 
While the invention has been particularly shown and described with 
reference to the preferred embodiments thereof, it will be understood by 
those skilled in the art that various changes in form and details may be 
made without departing from the spirit and scope of the invention.