Sensor manufacturing method

A sensor manufacturing method and a microphone structure produced by using the same. Wherein, thermal oxidation method is used to form a sacrifice layer of an insulation layer on a silicon-on-insulator (SOI) substrate or a silicon substrate, to fill patterned via in said substrate. Next, form a conduction wiring layer on the insulation layer. Since the conduction wiring layer is provided with holes, thus etching gas can be led in through said hole, to remove filling in the patterned via, to obtain an MEMS sensor. Or after etching of the conduction wiring layer, deep reactive-ion etching is used to etch the silicon substrate into patterned via, to connect the substrate electrically to a circuit chip. The manufacturing process is simple and the technology is stable and mature, thus the conduction wiring layer and the insulation layer are used to realize electrical isolation.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a sensor technology, and in particular to a sensor manufacturing method and a microphone structure made by using the same.

2. The Prior Arts

In the past thirty years, the complementary metal oxide semiconductor (CMOS) has been used extensively in the manufacturing of Integrated Circuits (IC). The development and innovation of IC have progressed by leaps and bounds, due to huge amount of research manpower and investment put in, to raise significantly its reliability and yields; meanwhile, its production cost is reduced drastically. Presently, that technology has reached a mature and stable level, such that for the continued development of the semiconductor, in addition to keeping up the present trend of technical development, it is essential to achieve breakthrough to provide special production process, and enhance system integration of high concentration.

In this respect, the Micro Electro-Mechanical System (MEMS) is a new processing technology completely different from the convention technology. It mainly utilizes the semiconductor technology to produce MEMS structure; meanwhile it is capable of making products having electronic and mechanical functions. As such, it has the advantages of batch processing, miniaturization, and high performance, and is very suitable for use in Production Industries requiring mass production at reduced cost. Therefore, for this stable and progressing CMOS technology, the integration of MEMS and circuitry can be a better approach to achieve system integration.

For the processing of most of the MEMS elements, poly-silicon is utilized to make active elements, such that it utilizes one or more oxides as the release layer, the silicon nitride as the isolation layer, and metal layer as a reflector and internal connection. In processing the MEMS elements, it could encounter an especially difficult release problem, such that in this process, a silicon oxide sacrifice layer is dissolved, and a gap thus created is to separate various elements. In this respect, the MEMS elements, including the electrostatic suspension arms, the deflection mirrors, and the torsion regulator are released through dissolving the sacrifice layer by means of the wet chemical process. In general, that process is performed on a single piece of MEMS circuit chip, rather on a whole wafer. At this time, the static friction is liable to cause decrease of yield. The static friction refers to two adjacent surfaces stick to each other, as caused by the capillary forces produced by drying up the liquid between two micro-structures, thus leading to decrease of yield. Most of the MEMS elements are made through using oxide sacrifice layers. Usually, a water containing hydrofluoric acid is used to dissolve an oxide sacrifice layer to achieve release. In another approach, a hydrofluoric acid vapor is used to release MEMS elements having oxide sacrifice layer.

In a thesis of Stanford University, “Wafer Scale Encapsulation Of Large Lateral Deflection MEMS Structure”, the MEMS element is produced by first performing Deep Reactive-Ion Etching of a silicon-on-insulator (SOI) substrate. Next, grow a layer of silicon dioxide thereon, and then planarize its surface. Subsequently, form a first epitaxy layer, and then perform deep reactive-ion etching to remove a part of the silicon layer. Finally, grow a second epitaxy layer to seal off the etched holes on the first epitaxy layer, to form an electrode serving as a connection pad. In addition, in U.S. Pat. No. 7,621,183, another MEMS element manufacturing method is disclosed. Wherein, firstly, form an oxide layer on a cap wafer, then form a balance structure and a germanium layer on a gyroscope wafer, to connect the gyroscope wafer onto the cap wafer. Finally, connect a reference wafer electrically to the germanium layer, to fix it on the gyroscope wafer. From the descriptions above it can be known that, the former cited case utilizes the epitaxy technology requiring high price metal; while for the latter cited case, its production process is rather complicated.

Therefore, presently, the design and performance of the MEMS element manufacturing method is not quite satisfactory, and it has much room for improvements.

SUMMARY OF THE INVENTION

In view of the problems and shortcomings of the prior art, the present invention provides a sensor manufacturing method and a microphone structure made by using the same, that is simple in implementation, to overcome the deficiency and drawback of the prior art.

A major objective of the present invention is to provide a sensor manufacturing method, that utilizes the stable and mature technology, such as thermal oxidation method, metal wiring, deep reactive-ion etching, and Plasma Enhanced Chemical Vapor Deposition (PECVD), to realize cost reduction and replace the exitaxial technology, and provide various types of manufacturing processes; meanwhile achieving voltage separation through a conduction wiring layer.

In order to achieve the above objective, the present invention provides a sensor manufacturing method, comprising the following steps. Firstly, provide a silicon-on-insulator (SOI) substrate, a silicon layer of the silicon-on-insulator (SOI) substrate is provided with at least a trench penetrating itself. Then, provide at least a patterned via penetrating the silicon layer, and form a sacrifice layer on the silicon layer by means of a thermal oxidation method, to fill the trench and the patterned via. Subsequently, remove a part of the sacrifice layer, to expose the silicon layer, and also form a conduction wiring layer on the sacrifice layer, to connect electrically to the silicon layer. Wherein, the top surface of the conduction wiring layer is provided with at least a hole, with its position corresponding to that of the patterned via. Finally, through the hole, remove the sacrifice layer in the patterned via.

The present invention also provides another sensor manufacturing method, comprising the following steps. Firstly, provide a silicon substrate, that is provided with at least a trench penetrating itself. Then, utilize a thermal oxidation method to form a sacrifice layer on the silicon substrate, to fill the trench; or use PECVD to fill the trench. Subsequently, remove a part of the sacrifice layer, to expose the silicon substrate, and form a conduction wiring layer on the sacrifice layer, to connect electrically to the silicon substrate. Wherein the top surface of the conduction wiring layer is provided with at least a hole, with its position corresponding to that of the sacrifice layer on the inner side of the conduction wiring layer. Through the hole, the sacrifice layer on the inner side of the conduction wiring layer can be removed. After the removal, form at least a patterned via penetrating the silicon substrate by means of deep reactive-ion etching.

Moreover, the present invention provides a microphone structure, including a silicon substrate, and is provided with an opening. On the silicon substrate is provided with a silicon layer. The silicon layer includes at least a first silicon block and at least a second silicon block, such that they are spaced by at least two different co-planar gaps, and connects with the opening.

Further scope of the applicability of the present invention will become apparent from the detailed descriptions given hereinafter. However, it should be understood that the detailed descriptions and specific examples, while indicating preferred embodiments of the present invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the present invention will become apparent to those skilled in the art from this detailed descriptions.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

The purpose, construction, features, functions and advantages of the present invention can be appreciated and understood more thoroughly through the following detailed description with reference to the attached drawings.

The present invention relates to a Micro Electro-Mechanical System (MEMS) sensor manufacturing method, that utilizes the stable and mature technology, such as thermal oxidation method, metal wiring, deep reactive-ion etching, and Plasma Enhanced Chemical Vapor Deposition (PECVD), to realize cost reduction and replace the epitaxy technology, and provide various types of manufacturing processes; meanwhile achieving voltage separation through a conduction wiring layer.

Refer toFIGS. 1(a) to1(m) for cross section views of structures corresponding to various steps of a sensor manufacturing method according to a first embodiment of the present invention. As shown inFIG. 1(a), firstly, provide a silicon-on-insulator (SOI) substrate10, that is provided with a silicon layer12. Next, as shown inFIG. 1(b), form at least a trench14penetrating the silicon layer12by means of a Deep Reactive-Ion Etching, to expose a silicon dioxide layer16. Then, as shown inFIG. 1(c), utilize a thermal oxidation method or PECVD to form an oxidation layer18on the silicon layer12, to fill the trench14. Subsequently, as shown inFIG. 1(d), utilize Reactive-Ion Etching (RIE) to dry etch and remove part of the oxidation layer18, and utilize the Deep Reactive-Ion Etching to etch the silicon layer12below, to form at least a patterned via22. Then, as shown inFIG. 1(e), fill a sacrifice structure24into the patterned via22, to form a sacrifice layer26on the silicon layer12. Namely, the sacrifice layer26includes the oxidation layer18and the sacrifice structure24, and both can be made of silicon dioxide.

Upon finishing the sacrifice layer26, as shown inFIG. 1(f), remove part of the sacrifice layer26, to expose the silicon layer12, to make the sacrifice layer26to have a first sacrifice block261and the second sacrifice block262, such that the latter is on the outer perimeter of the former. Wherein, for the requirement of the subsequent conduction wiring layer, adjustment can be made in the manufacturing process, so that the first sacrifice block261is made of silicon dioxide, while the second sacrifice block262is made of silicon dioxide, silicon carbide, or undoping polysilicon

Then, as shown inFIG. 1(g), form a first metal layer28made of aluminum on the sacrifice layer26, and connect it electrically to the silicon layer12. Subsequently, as shown inFIG. 1(h), form at least an opening30on the first metal layer28corresponding to the patterned via22and the trench14, to expose the sacrifice layer26. Then, form a first insulation layer32made of silicon dioxide to fill the opening30, as shown inFIG. 1(i). Afterwards, as shown inFIG. 1(j), form a first insulation block34made of silicon dioxide on the first insulation layer32, and to form a second insulation block36made of silicon dioxide and a metal block38made of tungsten (W) on the first metal layer28. The metal block38is used as a conduction via or conduction plug, such that the first insulation block34, the second insulation block36are adjacent to the metal block38, and are located inside and outside of the metal block38, to form a second metal layer40made of aluminum and having at least a hole42, on the first insulation block34, the second insulation block36, and the metal block38. Wherein, the hole42is located corresponding to the patterned via44and the trench14, and a second insulation layer44made of silicon dioxide is formed in the opening42to be located on the first insulation block34, so as to form a conduction wiring layer45on the sacrifice layer26.

Alternatively, as shown in the step ofFIG. 1(j), a metal wiring layer46having an opening42and including the first insulation block34, the second insulation block36, the metal block38, the second metal layer40, and the second insulation layer44can be formed directly on the first insulation layer32and the first metal layer28. Wherein, the relative positions of the first insulation block34, the second insulation block36, the metal block38, the second metal layer40, and the second insulation layer44are the same as mentioned above.

Upon forming the conduction wiring layer45, as shown inFIG. 1(k), pour in the Hydrogen Fluoride (HF) vapor through the hole42, or utilize wet etching through the hole42, to remove in sequence the second insulation layer44, the first insulation block34, the first insulation layer32, the sacrifice layer26inside the first metal layer28, the sacrifice layer26in the patterned via22, and the silicon dioxide layer16of the silicon-on-insulator (SOI) substrate10. Meanwhile, remove the sacrifice layer26in the trench14. The sacrifice layer26removed mentioned above is the part of the first sacrifice block261.

In case the first sacrifice block261is not in contact with the trench14, and the second sacrifice block262is in contact with the trench14, so that the opening30and the hole42are not aligned with the trench14, then in the step ofFIG. 1(k), the sacrifice layer26in the trench14can not be removed.

In case it is desired to make other types of sensors, the following steps can be taken.

Subsequently, as shown inFIG. 1(l), deposit at least an insulation layer47and a metal layer48on the second metal layer40of the conduction wiring layer45, to seal off the hole42. Finally, as shown inFIG. 1(m), remove a part of the metal layer48and the insulation layer47below, to expose the second metal layer40used for electrical conduction.

The step inFIG. 1(a) mentioned above can be omitted, namely provide directly an SOI substrate10containing a silicon layer12having a trench14, as shown inFIG. 1(b). In addition, after the step ofFIG. 1(b), a patterned via22can be formed directly in the silicon layer12, and the sacrifice layer26is formed on the silicon layer12, to fill the trench14and the patterned via22, so as to complete the structure as shown inFIG. 1(e). Moreover, after the step as shown inFIG. 1(f), the conduction wiring layer45can be formed directly on the sacrifice layer26.

In the following, the second embodiment is described. Refer toFIGS. 2(a) to2(l) for the cross section views of structures corresponding to various steps of a sensor manufacturing method according to a second embodiment of the present invention. Wherein, the steps ofFIGS. 2(a) to2(j) are the same as those ofFIGS. 1(a) to1(j), and they will not be repeated here for brevity.

Upon completing the steps ofFIG. 2(j), then as shown inFIG. 2(k), utilize Induced Coupling Plasma (ICP) to etch the backplane silicon substrate491, to form an opening492exposing the silicon dioxide layer16. The position of opening492corresponds to that of the patterned via22. Then, as shown inFIG. 2(l), use Hydrogen Fluoride (HF) vapor through the hole42, or utilize wet etching through the hole42, to remove in sequence the second insulation layer44, the first insulation block34, the first insulation layer32, the sacrifice layer26inside the first metal layer28, the sacrifice layer26in the patterned via22, and the silicon dioxide layer16of the silicon-on-insulator (SOI) substrate10. Meanwhile, remove the sacrifice layer26in the trench14, so that the opening492connects with the patterned via22. The sacrifice layer26removed mentioned above is the part of the first sacrifice block261.

Up to this point, a microphone, a potential meter, or a non-seal packaged MEMS element can be produced. A capacitor type microphone without backplane can be designed based on the second embodiment as shown inFIG. 3, and that is also the top view of the silicon layer12ofFIG. 2(l), indicating a microphone structure. In this figure it shows two electrodes of different potentials, shown respectively by cross section dash lines and blanks. The cross section dash lines indicate the electrode is a stator electrode, while the blank indicates the electrode is a rotor electrode. For the microphone structure, in addition to the silicon substrate491having the opening492, it further includes the silicon layer12on the silicon substrate491. The silicon layer12includes at least a first silicon block121serving as a rotor electrode, and at least a second silicon block122serving as a stator electrode. The first silicon block121and the second silicon block122are separated by at least two different co-planar gaps, such that the co-planar gaps connect with the opening492. Wherein, the portion of the first silicon block121is used as a vibration diaphragm, and is located inside the second silicon block122.

The stator electrode and the rotor electrode are separated by co-planar gaps D1, D2, and D3, to form horizontal type capacitor structure, while the co-planar gaps D1, D2, and D3are for example 1.5 μm, 3 μm, and 1.5 μm respectively. In other words, when a voltage is applied between the stator electrode and the rotor electrode to perform acoustic pressure sensing, the sensor electrode of the microphone will produce capacitance variations, and the capacitance sensing is referred to as gap closing sensing. Its structure is simpler, capable of saving quite a few production steps, as compared with the ordinary capacitor type microphone requiring vertical type capacitor structure of diaphragm, backplane, and cavity.

In the following, the third embodiment of the present invention is described. Refer toFIGS. 4(a) to4(l) for cross section views of structures corresponding to various steps of a sensor manufacturing method according to a third embodiment of the present invention.

Firstly, as shown inFIG. 4(a), provide a silicon substrate50. Next, as shown inFIG. 4(b), utilize deep reactive-ion etching to form at least a trench52through the silicon substrate50. Next, as shown inFIG. 4(c), use thermal oxidation method or PECVD to form a sacrifice layer56made of silicon dioxide on the silicon substrate50, to fill the trench52. Then, as shown inFIG. 4(d), remove a part of the sacrifice layer56, to expose the silicon substrate50, so that the sacrifice layer56has a first sacrifice block561and a second sacrifice block562, and the second sacrifice block562is on the outer perimeter of the first sacrifice block561. Wherein, for the requirement of the subsequent conduction wiring layer, adjustment can be made in the manufacturing process, such that the first sacrifice block561is made of silicon dioxide, while the second sacrifice block562is made of silicon dioxide, silicon carbide, or polysilicon of high impedance.

After the removal, as shown inFIG. 4(e), a second metal layer58made of aluminum is formed on the sacrifice layer56, to connect electrically to the silicon substrate50. Afterwards, as shown inFIG. 4(f), form at least an opening60in the second metal layer58corresponding to the sacrifice layer56inside the second metal layer58, to expose the sacrifice layer56. Then, as shown inFIG. 4(g), form a second insulation layer62made of silicon dioxide to fill the opening60. After filling, as shown inFIG. 4(h), form a first insulation block64made of silicon dioxide on the second insulation layer62, and form a second insulation block66made of silicon dioxide and a metal block68made of tungsten (W) on the first metal layer58. The metal block68is used as a conduction via or conduction plug, such that the first insulation block64, the second insulation block66are adjacent to the metal block68, and are located inside and outside of the metal block68, to form a second metal layer70made of aluminum and having at least a hole72, on the first insulation block64, the second insulation block66, and the metal block68. Also, form a third insulation layer74made of silicon dioxide in the hole72, and is located on the first insulation block64, so that a conduction wiring layer76is formed on the sacrifice layer56. Wherein, the hole72is located corresponding to the sacrifice layer56inside the conduction wiring layer, namely the first sacrifice block561.

Alternatively, as shown in the step ofFIG. 4(h), a metal wiring layer77having an hole72and including the first insulation block64, the second insulation block66, the metal block68, the second metal layer70, and the third insulation layer74can be formed directly on the second insulation layer62and the first metal layer58. Wherein, the relative positions of the first insulation block64, the second insulation block66, the metal block68, the second metal layer70, and the third insulation layer74are the same as that mentioned above.

Then, as shown inFIG. 4(i), pour in the hydrofluoric acid vapor through the hole72, or utilize wet etching of hydrofluoric acid liquid, to remove in sequence the third insulation layer74, the first insulation block64, the second insulation layer62, the sacrifice layer56inside the first metal layer58of the conduction wiring layer76. The sacrifice layer is the first sacrifice block561. After the removal, as shown inFIG. 4(j), deposit in sequence the first insulation layer78made of silicon dioxide and a connection layer80made of aluminum on the second metal layer70of the conduction wiring layer76, so as to seal off the hole72. Then, as shown inFIG. 2(k), at a position corresponding to the hole72, utilize the deep reactive-ion etching to form at least a patterned via82through the silicon substrate50; and form at least a first connection pad84at the bottom surface of the silicon substrate50. Finally, as shown inFIG. 4(l), provide at least a circuit chip88having at least a second connection pad86, and utilize the bonding to each other of the first connection pad84and the second connection pad86, to fix the circuit chip88onto the silicon substrate50. The first connection pad84and the second connection pad86are connected in a hermetic way, and that belong to the fusion bonding, glass fit bonding, and eutectic bonding of the prior art. Wherein, in case the bonding technology is of a fusion bonding, then the step of forming the first connection pad84can be omitted, so that the second connection pad86is bonded directly onto the silicon substrate50.

In the descriptions mentioned above, the step ofFIG. 4(a) can be omitted, namely, to provide directly a silicon substrate50having a trench52, as shown inFIG. 4(b). Furthermore, after the step ofFIG. 4(d), the conduction wiring layer76can be formed directly on the sacrifice layer56.

In addition, in the process flow of the third embodiment, after the step ofFIG. 4(i), the steps ofFIGS. 4(j) and4(l), and the step of forming the first connection pad84ofFIG. 4(k) can be omitted, to perform directly the step of forming patterned via82ofFIG. 4(k), to complete the manufacturing process of the sensor.

In the following, the fourth embodiment of the present invention is described. Refer toFIGS. 5(a) to5(m) for cross section views of structures corresponding to various steps of a sensor manufacturing method according to a fourth embodiment of the present invention. Wherein, the steps ofFIGS. 5(a) to5(j) are the same as those ofFIGS. 4(a) to4(j), and they will not be repeated here for brevity.

Upon forming the first insulation layer78and the connection layer80on the second metal layer70of the conduction wiring layer76, as shown inFIG. 5(k), provide a support substrate92, with its top surface provided with at least a slot94for aligning positions, and connect the support substrate92to the connection layer80, for fixing the support substrate92onto the conduction wiring layer76. Wherein, the support substrate92is realized with a silicon substrate.

Then, as shown inFIG. 5(l), at the position corresponding to the hole72, utilize the deep reactive-ion etching, to form at least a patterned via82through the silicon substrate50. Also, form at least a first connection pad84on the bottom of the silicon substrate50, to remove the slot94. Finally, as shown inFIG. 5(m), provide at least a circuit chip88having at least a second connection pad86, and utilize the bonding of the first connection pad84and the second connection pad86, to fix the circuit chip88onto the silicon substrate50. Similarly, the first connection pad84and the second connection pad86are connected in a hermetic way, and that belongs to the fusion bonding, glass fit bonding, and eutectic bonding of the prior art. Wherein, in case the bonding technology is of fusion bonding, then the step of forming the first connection bonding84can be omitted, so that the second connection pad86is bonded directly onto the silicon substrate50. Wherein, the first connection pad84and the second connection pad86can be made of silicon dioxide or metal.

Through the manufacturing processes mentioned above, various MEMS sensors, such as accelerator, gyroscope, magnetic field sensor, or oscillator etc. can be produced.

Summing up the above, the manufacturing technology of the present invention is stable, mature, and is capable of reducing cost and meeting the requirements of MEMS technology.

The above detailed description of the preferred embodiment is intended to describe more clearly the characteristics and spirit of the present invention. However, the preferred embodiments disclosed above are not intended to be any restrictions to the scope of the present invention. Conversely, its purpose is to include the various changes and equivalent arrangements which are within the scope of the appended claims.