Apparatus having process, voltage and temperature-independent line transient management

A voltage regulator and a gate control circuit for an aid transistor coupled to assist a pass element for the voltage regulator during line transients having a given slope are disclosed. The gate control circuit includes a first circuit coupled to receive an output voltage of the voltage regulator on a first node and to provide a gate control voltage that mirrors the output voltage on a second node. A low pass filter is coupled to receive the gate control voltage and to provide a filtered gate control voltage to the gate of the aid transistor.

FIELD OF THE DISCLOSURE

Disclosed embodiments relate generally to the field of line transient management. More particularly, and not by way of any limitation, the present disclosure is directed to an apparatus having process, voltage and temperature-independent line transient management.

BACKGROUND

Voltage regulators and other circuits that supply power to integrated circuit chips are relied on to deliver a consistent voltage, even when the power received by the voltage regulator varies widely. Sudden transients, such as a drop or spike in an input voltage, can cause output voltage transients that can result in reset of the circuitry supplied by the voltage regulator. Improvements to existing circuits are needed.

SUMMARY

Disclosed embodiments provide a control circuit for an aid transistor in a low-dropout (LDO) voltage regulator or other circuit. The control circuit is process, voltage and temperature-independent and does not interfere with the main voltage regulation loop. The output voltage is converted to a second voltage that does not change as quickly as the output voltage. This second voltage is used to drive the gate of an aid transistor whose source is coupled to the output voltage. When the output voltage changes suddenly, the lag in the second voltage causes the aid transistor to turn ON and assist the pass element. As the second voltage “catches up” to the output voltage, aid transistor is turned OFF. Slower changes in the output voltage do not cause the aid transistor to turn ON.

In one aspect, an embodiment of a control circuit for an aid transistor coupled to assist a pass element for a voltage regulator during line transients having a given slope is disclosed. The control circuit includes a first circuit coupled to receive an output voltage of the voltage regulator on a first node and to provide a gate control voltage that mirrors the output voltage on a second node; and a low pass filter coupled to receive the gate control voltage and to provide a filtered gate control voltage to the gate of the aid transistor.

In another aspect, an embodiment of a low-dropout regulator is disclosed. The low-dropout regulator includes a pass element coupled between an upper rail and a lower rail and further coupled to provide an output voltage on an output node; a first aid transistor coupled to pull the output voltage in a first direction; and a first gate control circuit coupled to sense the output voltage and to convert the sensed output voltage to a gate control voltage that is provided to the gate of the first aid transistor, wherein the control gate voltage turns ON the first aid transistor only during a transient having a first slope, the first gate control circuit being substantially independent of process, temperature and voltage changes.

In yet another aspect, an embodiment of a low-dropout (LDO) regulator is disclosed. The LDO includes a first P-type metal oxide silicon (PMOS) transistor coupled as a pass element in series with a voltage divider between an upper rail and a lower rail and further coupled to provide an output voltage on an output node; an error amplifier coupled to receive a reference voltage on a first terminal and a feedback voltage on a second terminal and to control the gate of the PMOS pass element, the feedback voltage being taken from a point internal to the voltage divider; a first N-type metal oxide silicon (NMOS) transistor coupled as an NMOS aid transistor to pull the output voltage toward the upper rail when turned ON; a second PMOS transistor coupled as a PMOS aid transistor to pull the output voltage toward the lower rail when turned ON; a first gate control circuit coupled to receive the output voltage and to convert the received output voltage to a first filtered gate control voltage that is provided to the gate of the NMOS aid transistor, wherein the first filtered gate control voltage turns ON the NMOS aid transistor only during a transient having a negative slope; a second gate control circuit coupled to receive the output voltage and to convert the received output voltage to a second filtered gate control voltage that is provided to the gate of the PMOS aid transistor, wherein the second filtered gate control voltage turns ON the PMOS aid transistor only during a transient having a positive slope, the first gate control circuit and the second gate control circuit being substantially independent of process, temperature and voltage changes.

DETAILED DESCRIPTION OF THE DRAWINGS

A low-dropout or LDO regulator is a DC linear voltage regulator that can regulate an output voltage even when the supply voltage is very close to the output voltage. The advantages of a low dropout voltage regulator include the absence of switching noise, as no switching takes place, smaller device size, and greater design simplicity. In one automotive application, LDOs are required that can provide low-dropout voltage as high as 5 volts while supporting a stable load current at low voltage levels from a battery. The power from the battery can drop below 6 volts, e.g., during cold crank conditions.

The pass element or output transistor of the LDO can be implemented using an N-type metal oxide semiconductor (NMOS) transistor, a P-type metal oxide semiconductor (PMOS) transistor, junction field effect transistor, etc. For high voltage applications, NMOS transistors are often preferred for the pass element, while for low voltage applications, PMOS transistor are more commonly preferred. The NMOS transistor requires a gate voltage higher than its source voltage, i.e., the output of the LDO. Therefore a charge pump may be necessary to increase the voltage level of the gate in an embodiment that utilizes an NMOS transistor. The charge pump requires additional die area and adds to circuit complexity. In contrast, the PMOS transistor has a better dropout performance since its gate voltage is always lower than its source voltage. Thus, the appropriate choice for low voltage applications without the use of charge pumps is the use of a PMOS LDO. However, the line transient response of a PMOS LDO is inferior compared to that of an NMOS LDO. Line transient performance is especially important in automotive applications where the battery voltage can fluctuate considerably in a very short time, e.g., 10 V/μs. Therefore, there is a need in automotive applications for an LDO that can support both low battery operation and provide the necessary line transient immunity.

FIG. 10is a schematic diagram of an LDO voltage regulator1000according to the prior art. LDO voltage regulator1000includes a PMOS pass element, which in the disclosed embodiments is transistor MP1and an error amplifier1002. Pass transistor MP1has a source coupled to supply voltage VSUP, a gate controlled by the output of error amplifier1002, and a drain coupled through node1004to the output node, which provides the output voltage VOUT. Resistors R1and R2are coupled in series between node1004and the lower rail and form a voltage divider1006. A feedback voltage VFBis taken from a point between resistor R1and resistor R2and is provided to the non-inverting input of error amplifier1002. Reference voltage VREFis provided to the inverting input of error amplifier1002. If the feedback voltage becomes greater than the reference voltage, control signal1008changes the on-state of pass transistor MP1to effectively increase the resistance of the voltage regulator circuit and maintain a constant output voltage VOUT. Capacitor C1is coupled between VOUTand the lower rail and serves to stabilize the output voltage VOUT. LDO voltage regulator1000does not include any form of line transient protection. Because of the lack of line transient protection, circuitry supplied by a voltage regulator utilizing this configuration can experience a reset when the supply voltage drops suddenly, because the feedback loop is not able to respond quickly enough to prevent a large drop in the output voltage.

FIG. 11depicts a schematic diagram of an LDO1100according to the prior art. LDO1100contains all of the elements of LDO1000and also contains an NMOS aid transistor MN1. NMOS aid transistor MN1is coupled between the upper rail and the output voltage and the gate of MN1is controlled by a regulated voltage that is generated using, e.g., a shunt regulator1102. Shunt regulator1102receives a supply voltage from VSUP; when VSUPdrops, node1004drops, inherently turning ON aid transistor MN1, which then acts to pull up output voltage VOUT.

One problem with this circuit, however, is that because of process and temperature variations, the gate voltage applied to the aid transistor has no relationship to the output voltage of the LDO or the threshold voltage of the aid transistor. Therefore, it is possible for the shunt regulator1102to turn ON aid transistor MN1unnecessarily, i.e., during normal operations, which interferes with the operation of the pass transistor. When this occurs, aid transistor MN1can pull up output voltage VOUTto a point that causes pass transistor MP1to shut down; at such times, no real voltage regulation can be provided. If a transient event has passed and the aid transistor continues to support the load current, the accuracy of the regulated output voltage is affected. Another problem encountered is gain reduction in the main loop, which affects stability because the majority of the load current is being supported by the NMOS aid transistor and not by the main PMOS transistor. Another issue arises when different output voltages are desired from the LDO. In this event, the reference gate voltage for the aid transistor must be re-adjusted. When both NMOS and PMOS aid transistors are used, both of their reference gate voltages have to be individually trimmed so that the possibility of cross conduction current between the aid transistors is avoided.

Referring now toFIG. 1, a schematic diagram of an LDO circuit100is shown according to an embodiment of the disclosure. LDO circuit100includes LDO102and gate control circuit104. LDO102contains all of the elements of prior art LDO voltage regulator1000and also includes NMOS aid transistor MN1to pull up output voltage VOUTduring transient drops. The gate of NMOS aid transistor MN1is controlled by gate control circuit104.

Gate control circuit104includes a current mirror circuitry106and a low pass filter108. One leg of the current mirror is formed by PMOS transistor MP3, NMOS transistor MN2and resistor R3, which are coupled in series between supply voltage VSUP, which forms the upper rail, and the lower rail. A second leg of the current mirror is formed by PMOS transistor MP4, resistor R5, NMOS transistors MN3and MN4, and variable resistor R4, which are also coupled in series between the upper rail and the lower rail. PMOS transistor MP3is diode-coupled and the gates of PMOS transistors MP3and MP4are coupled together; both of NMOS transistors MN3and MN4are diode coupled.

Gate control circuit104receives the output voltage VOUTat node110, which in the embodiment shown is the gate of NMOS transistor MN2, and converts VOUTinto a current using resistor R3. The current through transistor MN2is mirrored using the current mirror106and used to provide a gate control voltage VG. Gate control voltage VGis filtered using a low-pass filter (LPF)108to generate filtered gate control voltage VGF, which controls the action of NMOS aid transistor MN1. The value of gate control voltage VGand therefore of filtered gate control voltage VGFis set by the two diode-connected NMOS transistors, MN3, MN4, and resistor R4. The ratio between resistors R4and R3is selected so that during normal operation, gate control voltage VGis set slightly below the threshold voltage of NMOS aid transistor MN1, thereby placing aid transistor MN1at the verge of conduction. Resistor R4is designed as a variable resistor and the value of resistor R4can be set by the customer to adjust the sensitivity of aid transistor MN1to transients to fit current requirements.

During a line transient having a negative slope, supply voltage VSUPdecreases rapidly. The voltage regulation loop formed by voltage divider1006and error amplifier1002is slow to respond, i.e., the loop has a finite bandwidth, so a temporary voltage dip in output voltage VOUToccurs. This voltage dip in turn causes the current through both legs of current mirror106to decrease and also decreases gate control voltage VG. However, the low pass filter108filters out this sudden drop in the gate control voltage VGso that filtered gate control voltage VGFstays relatively stable and drops over a longer time period. This stability of filtered gate control voltage VGFincreases the gate-to-source voltage of NMOS aid transistor MN1above the threshold voltage of transistor MN1as output voltage VOUTdecreases and turns ON aid transistor MN1. Aid transistor MN1is able to pull up output voltage VOUTand reduce the voltage dip in VOUT. As the value of filtered gate control voltage VGFslowly drops to the value of gate control voltage VG, aid transistor MN1will be turned OFF. During the time that aid transistor MN1is turned on, pass transistor MP1recovers the ability to provide the required output voltage due to the action of the associated voltage regulation loop. It is noteworthy at this point that if the output voltage VOUTdrops over a longer period of time such that the voltage regulation loop is able to adjust, the aid transistor will not be turned ON.

In order to make gate control circuit104process and temperature independent, NMOS transistors MN3, MN4are each matched to one of NMOS aid transistor MN1and NMOS transistor MN2; PMOS transistors MP3, MP4are matched to each other; and the resistors R3and R4are matched. The use of matching transistors and the fact that control of the NMOS aid transistor is responsive to the output voltage VOUTprovides another advantage. In the prior art, the values of the reference voltage VREFand of resistors R1, R2can be exposed to the customer, allowing the output voltage VOUTto be adjusted. However, when an aid transistor is utilized, as in prior art LDO1100, there was no possibility of adjusting the values necessary to ensure proper operation of the aid transistor. In contrast, the disclosed embodiments can detect when the output voltage VOUTis modified and will automatically adjust to ensure proper operation of the aid transistors.

The embodiment disclosed inFIG. 1is designed to handle only transients having a negative slope. However, with appropriate adjustments, the disclosed circuit can be utilized to handle transients having a positive slope.FIG. 2depicts a schematic diagram of an LDO circuit200according to an embodiment of the disclosure. LDO circuit200includes LDO202and gate control circuit204. LDO202contains all of the elements of prior art LDO voltage regulator1000and also includes a PMOS aid transistor MP2, which is coupled between the output node and the lower rail and acts to pull down output voltage VOUTduring transient increases. The gate of PMOS aid transistor MP2is controlled by gate control circuit204.

Gate control circuit204includes a current mirror circuitry206and a low pass filter208. One leg of the current mirror is formed by NMOS transistor MN5, PMOS transistor MP5and resistor R6, which are coupled in series between the lower rail and supply voltage VSUP. A second leg of the current mirror is formed by NMOS transistor MN6, resistor R8, PMOS transistors MP6and MP7, and variable resistor R7, which are coupled in series between the lower rail and the upper rail. NMOS transistor MN5is diode-coupled and the gates of NMOS transistors MN5and MN6have their gate coupled together; both of PMOS transistors MP6and MP7are diode coupled.

Gate control circuit204receives the output voltage VOUTat node210, which in the embodiment shown is the gate of PMOS transistor MP5, and converts VOUTinto a current using resistor R6. The current through transistor MP5is mirrored using the current mirror206and used to provide a gate control voltage VG, also referred to herein as a mirror voltage. Gate control voltage VGis filtered using low-pass filter208to generate filtered gate control voltage VGF, which controls the action of PMOS aid transistor MP2. The value of gate control voltage VGand therefore of filtered gate control voltage VGFis set by the two diode-connected transistors, MP6, MP7, and resistor R7. The ratio between resistors R7and R6is selected so that during normal operation, gate control voltage VGis set slightly below the threshold voltage of PMOS aid transistor MP2, thereby placing aid transistor MP2at the verge of conduction. Resistor R7is a variable resistor whose value can be set by the customer to adjust the sensitivity of aid transistor MP2to transients to fit current requirements.

During a positive slope line transient, supply voltage VSUPincreases rapidly. As previously noted, the voltage regulation loop formed by voltage divider1006and error amplifier1002is slow to respond, so a temporary voltage bump in output voltage VOUToccurs. This voltage bump in turn causes the current through both legs of current mirror206to decrease and in turn increases gate control voltage VG. However, the low pass filter208filters out this sudden rise in the gate control voltage VGso that filtered gate control voltage VGFstays relatively stable and rises over a longer time period. This relative stability of filtered gate control voltage VGFas VOUTrises produces a negative gate-to-source voltage on PMOS aid transistor MP2that exceeds the threshold voltage and turns ON PMOS aid transistor MP2. PMOS aid transistor MP2is able to pull down output voltage VOUTand reduce the voltage rise at VOUT. As the value of filtered gate control voltage VGFslowly rises to the value of gate control voltage VG, PMOS aid transistor MP2will be turned OFF. During the time that aid transistor MP2is turned on, pass transistor MP1is able to resume regulation of required output voltage. It is again noteworthy that if the output voltage VOUTrises over a longer period of time such that the voltage regulation loop is able to adjust, the PMOS aid transistor MP2will not be turned ON.

To ensure that gate control circuit204is process and temperature independent, PMOS transistors MP6, MP7are each matched to one of PMOS transistor MP5and PMOS aid transistor MP2; NMOS transistors MN5, MN6are matched to each other; and the resistors R6and R7are matched. As in the previous example, the disclosed embodiments detect when the output voltage VOUTis modified and will automatically adjust to ensure proper operation of the aid transistor.

As shown inFIG. 3, both an NMOS aid transistor and a PMOS aid transistor having separate gate control circuits can be implemented in a single package. LDO circuit300includes LDO302and gate control circuit304. LDO302contains both an NMOS aid transistor MN1and a PMOS aid transistor MP2. Gate control circuit304includes gate control circuit104and gate control circuit204. Gate control circuit104receives output voltage VOUTon node110and provides both a gate control voltage VG1and a filtered gate control voltage VGF1. Filtered gate control voltage VGF1is provided to the gate of NMOS aid transistor MN1. Likewise, gate control circuit204receives output voltage VOUTfrom node110and provides both a gate control voltage VG2and a filtered gate control voltage VGF2. Filtered gate control voltage VGF2is provided to the gate of PMOS aid transistor MP2.

FIGS. 4-9depict a series of simulated tests run on each of the prior art embodiments and the presently disclosed embodiment as shown inFIG. 1. These tests simulate use in an automotive application, in which the car battery that provides the supply voltage can suddenly drop from an exemplary 14 volts as low as 6 volts when certain demands are made on the battery, such as a cold start.FIG. 4depicts a series of graphs of simulated results for both the prior art and the disclosed embodiments under nominal conditions and a 1 mA load. Section402depicts supply voltage VSUP, which is initially at 14 V, but suddenly drops to 8 V, a drop of 6 V in 6 μs; voltage supply VSUPthen continues at 8 V. Section404of the graph depicts VOUTfor each of the embodiments ofFIG. 10(prior1),FIG. 11(prior2) andFIG. 3(method). Output voltage VOUTin each of the example embodiments is set to provide a voltage of 5 V. In the embodiment ofFIG. 10, where no aid transistor is utilized, VOUTdrops all the way to 1.066 V before recovering. In the embodiment ofFIG. 11, where the aid transistor is controlled by a shunt regulator, output voltage VOUTdrops to 3.261 V before recovering. The disclosed embodiment does not drop as far, dropping only to 3.39 V before recovering. Section406depicts the gate voltage on the aid transistor for the embodiment ofFIG. 11and the present embodiment. The gate voltage for the embodiment ofFIG. 11rises more quickly, while the present embodiment performs a slow, steady increase. Sections408and410depict the voltage provided by the pass transistor and the aid transistor respectively. For the two embodiments that have aid transistors, the pass transistor and the aid transistor appear to work harmoniously in these ideal conditions.

FIG. 5depicts simulated results for both the prior art use of an aid transistor and the disclosed embodiment to compare operation at the process variation and temperature corners with a 1 mA load. In this set of graphs, multiple results are shown for each embodiment, with section502depicting supply voltage VSUPduring the same type of drop in voltage, section504depicting output voltage VOUTfor the embodiment ofFIG. 11and section506depicting VOUTfor the disclosed embodiment. Sections508,512and514depict the voltage on the aid transistor gate and currents through the pass transistor and the aid transistor respectively for the embodiment ofFIG. 11, while sections510,516and518depict the voltage on the aid transistor gate and currents through the pass transistor and the aid transistor respectively for the present embodiment. For the prior art embodiment, it can be observed that output voltage VOUTvaried in different conditions, even when no transients were present. For the embodiment ofFIG. 11, VOUTreached a high of 5.31 V, which was out of regulation for the required 5 V, while the disclosed embodiments remained in regulation throughout the tests. The cause of the out of regulation readings can be seen by looking at the graphs showing the current from the pass transistor and the aid transistor. In the prior art model, the aid transistor was turned ON in most of the tests, even when no transients were present. The action of the aid transistor in pulling up output voltage VOUTthen caused the pass transistor to be turned OFF. In a number of instances, no regulation of the voltage was possible due to the over activity of the aid transistor. In contrast, in the presently disclosed embodiments, the aid transistor remained OFF, except when the aid transistor was necessary to supplement current that the pass transistor was temporarily unable to supply.

The same tests depicted inFIG. 5were also run to provide the graphs shown inFIGS. 6 and 7.FIG. 6depicts the simulated results at the process variation and temperature corners with a lowered load of 0.1 mA, whileFIG. 7depicts the simulated results at the process variation and temperature corners with a 5 mA load. In both of these instances, the prior art embodiment demonstrated values of output voltage VOUTthat were out of regulation and that resulted from the aid transistor turning ON inappropriately. In each instance, the disclosed embodiment operated correctly and provided the desired 5 V output.

FIG. 8depicts the ability of the disclosed embodiment to be utilized with an adjustable output voltage level. The graph ofFIG. 8depicts operation of a circuit that was previously operated with an output voltage of 5 V and is currently being operated with an output voltage of 3 V; both prior art embodiments are shown, as well as the disclosed embodiment. In these simulations, the value of reference voltage VREFhas been changed to obtain a 3 V regulator output voltage. Section802again depicts the supply voltage VSUP, which is initially at 14 volts and drops to 8 volts. Section804depicts output voltage VOUTfor both prior art embodiments and the disclosed embodiment and section806depicts the voltage on the gate of the pass transistor for the two embodiments that have a pass transistor. Section808depicts the current provided by the pass transistor for all three embodiments while section810depicts the current provided by the aid transistor in the embodiment ofFIG. 11and the disclosed embodiment. The prior art embodiment with no aid transistor (prior1) is able to provide the desired output voltage of 3 V, but goes out of regulation during the voltage drop on supply voltage VSUP. In the prior art embodiment that utilizes an aid transistor (prior2), the aid transistor is unable to adjust to the new voltage and turns on during the entire test. Since the aid transistor is ON all of the time, the pass transistor MP1did not turn on during this test and the output voltage was higher than the requested 3 V. However, in the disclosed embodiment, the gate control voltage is set by the output voltage of the LDO, so no further adjustments were necessary to achieve the desired 3 V output voltage and retain the ability to withstand transients.

FIG. 9depicts simulated results for the disclosed embodiments at both 5 V and 3 V outputs. Section902of the graph illustrates the supply voltage, which drops from 14 V to 8 V. Section904illustrates output voltage VOUTat both 5 V and 3 V and section906illustrates the voltage on the gate of the aid transistor at each of these voltages. Finally, section908illustrates the current provided by pass transistor MP1and section910illustrates the current provided by NMOS aid transistor MN1at both the desired voltages. In both these tests, the aid transistor remains OFF, except when the pass transistor is temporarily unable to provide the desired output current, demonstrating how the disclosed embodiment is able to operate at multiple voltages. No components in the gate control section need to be adjusted to achieve this result.

Applicant has disclosed a control circuit to handle line transients that is process, voltage and temperature-independent. The control circuit has been disclosed in an embodiment of a linear voltage regulator, but is not limited to use in linear voltage regulators. The disclosed control circuit turns on the aid transistor only during line transients and does not interfere with the main voltage regulation loop. Using the disclosed control circuit and aid transistor(s), recovery after a line transient is inherently faster because the main loop never loses the full regulation control. In low quiescent or low output load current applications, the disclosed circuit ensures proper voltage regulation and minimum current consumption in the aid transistor over process, voltage and temperature conditions.

The disclosed circuit can be utilized for devices with adjustable output voltage levels, since the gate control voltage is set by the output voltage of the LDO. There is no need to re-adjust the components in the gate control block when the output voltage is changed Additionally, because of the architecture, the gate control voltage (VGF) is trimmable, which allows programmability of the strength of the aid transistor. The lowest dip voltage can be increased by increasing the size of the aid transistor without interfering with the main loop. The circuit is simple and does not require complicated additional circuitry. Although the disclosed LDO contains a capacitor to stabilize the output voltage, the disclosed circuit is also beneficial for use in cap-less LDOs where an external output capacitor is not present.

While the disclosed embodiments utilize a PMOS pass transistor, it will be understood that the disclosed gate control circuit can also be employed in applications that utilize an NMOS pass transistor.

Although various embodiments have been shown and described in detail, the claims are not limited to any particular embodiment or example. None of the above Detailed Description should be read as implying that any particular component, element, step, act, or function is essential such that it must be included in the scope of the claims. Reference to an element in the singular is not intended to mean “one and only one” unless explicitly so stated, but rather “one or more.” All structural and functional equivalents to the elements of the above-described embodiments that are known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be encompassed by the present claims. Accordingly, those skilled in the art will recognize that the exemplary embodiments described herein can be practiced with various modifications and alterations within the spirit and scope of the claims appended below.