Sloped trench etching process

Method and apparatus for etching a tapered trench in a layer of material with a highly controllable wall profile. The layer of material has a mask adjacent a surface thereof having an opening which defines a location on the layer of material at which the trench is to be formed. Vertical etch process steps and opening enlarging process steps are then performed in an alternating manner until the trench has been etched to a desired depth. The method permits very deep tapered trenches of up to 80-100 um or more to be formed in a silicon substrate or other layer of material in a highly controllable manner. The method can be incorporated into processes for manufacturing numerous devices including MEMS devices and high power RF devices such as LDMOS and VDMOS devices.

DETAILED DESCRIPTION OF PRESENTLY PREFERRED EMBODIMENTS FIGS. 1 - 7 schematically illustrate steps of a sloped trench etching process according to a presently preferred embodiment of the invention, and FIG. 8 is a flow chart which summarizes steps of the process. FIG. 1 illustrates a semiconductor substrate, for example, a silicon substrate, in which a trench is to be formed. The substrate is generally designated by reference number 10 ; and, as shown in FIG. 1 , is initially provided with a mask member in the form of a resist layer 20 on upper surface 22 thereof from which the trench is to extend into the substrate. The substrate 10 having the resist layer 20 thereon is sometimes generally referred to herein as a wafer 30 . As also shown in FIG. 1 , the resist layer 20 includes a suitably formed and located opening 24 therein which defines an exposed area or region 25 on the surface 22 of the substrate 10 at which the trench is to be formed. Although it is not essential to the practice of the method of the present invention, it is preferred that the profile of the resist layer 20 around the periphery of opening 24 be suitably rounded as illustrated at 26 in FIG. 2 (step 50 in FIG. 8 ) so that the thickness of the resist layer will be tapered at the resist-substrate interface. This is preferably accomplished by hard baking the wafer at a high temperature of, for example, >145° C., for a short period of time so that the resist layer will flow somewhat around the opening creating the rounded structure indicated at 26 . As will become apparent hereinafter, tapering the resist layer around the opening (in FIG. 2 , the opening is designated by reference number 24 a, and defines exposed region 25 a on surface 22 ) facilitates enlarging the opening during subsequent steps of the trench etching process. A first vertical etch process step is then performed using an etch process having a high selectivity to the resist layer to create a shallow trench structure comprised of trench portion 34 a which extends into the substrate 10 from surface 22 as illustrated in FIG. 3 (step 60 in FIG. 8 ). Trench portion 34 a has lateral dimensions which are defined by the size and shape of the mask opening 24 a, and has vertically oriented sidewalls. The depth of portion 34 a is a function of various parameters of the overall vertical etch process step as is well-known to those skilled in the art including the pressure, power, gas flows and time duration of the step. As will be discussed more fully hereinafter, an important aspect of the present invention is that each of these various parameters can be independently controlled so as to provide substantial control of the overall trench forming process. Following the first vertical etch process step, a first resist etch process step is performed to enlarge the size of the opening 24 a defined by the resist layer (the enlarged opening is designated by reference number 24 b in FIG. 4 ) so as to expose a slightly larger region 25 b of the substrate surface (step 70 in FIG. 8 ). Because, as was mentioned above, the resist layer 20 is tapered around the opening, the amount by which the opening is enlarged by the resist etch process step is, in effect, built into the design of the resist layer; and, thus, can be quite easily controlled so as to reduce the risk of unforseen loss of critical dimension. Also, since the resist layer is quite thin in the vicinity just around the opening, the enlarging step can be accomplished in a relatively short period of time. Following the first resist etch process step, a second vertical etch process step is performed. As illustrated in FIG. 5 , this step extends the depth of trench portion 34 a (without changing its lateral dimensions); and, at the same time, creates a second trench portion 34 b having vertical sidewalls and lateral dimensions which are defined by the enlarged opening 24 b in the resist layer. As should be apparent from FIG. 5 , the result of the second vertical etch process step is to form an overall trench structure having a generally stepped or staircase-like configuration. Following the second vertical etch process step, a second resist etch process step is performed to further enlarge the opening 24 in the resist layer; and, thereafter, vertical etch process steps and resist etch process steps are performed in an alternating manner. As the steps are performed, the depth of the trench is gradually increased; and, at the same time, the lateral dimensions of the trench are caused to gradually increase in a step-wise fashion from the bottom to the top of the trench. The vertical etch process step and the resist etch process step are continued in an alternating manner, as shown by the NO output of question block 80 in FIG. 8 , until the trench has been formed to the desired depth, as indicated by the YES output of question block 80 in FIG. 8 . A completed trench 40 formed to a desired depth from a large number of trench portions is illustrated in FIG. 6 . After the trench has been formed to the desired depth, the remaining resist layer is removed from the substrate 10 as shown in FIG. 7 , and subsequent processing may then be performed depending on the particular application for which the trench has been fabricated (step 90 in FIG. 8 ). FIG. 7 also emphasizes that in a typical application of the method of the present invention, the trench 40 is formed in a large number of steps and comprises a large number of trench portions such that each individual portion is quite small, and the sidewalls of the completed trench will, in effect, function as substantially smooth surfaces. With the present invention, trenches can be formed in a substrate having substantially any desired depth from, for example, rather shallow trenches of up to about 10 um deep to very deep trenches of about 80-100 um deep or more. The trenches can also be formed to have substantially any desired slope, for example, from about 45 degrees to about 80 degrees; while, at the same time, maintaining excellent control over the sidewall profile. By way of example, trenches having a depth of about 80 um and a slope of about 80 degrees have been accurately formed in silicon substrates using the method of the present invention. The method according to the present invention can be performed as a multi-step process or as a pulsed etch process depending on the type of etching tool used. The applicant has, for example, effectively used an ICP RIE tool with the capability of performing a cyclical etch process. It should be recognized, however, that it is not intended to limit the invention to the use of any particular type of tool or tools, or to limit the invention to any particular vertical etch process or resist etch process. As one example of an application of the present invention, a tapered trench having a depth of 80 um and sidewalls sloped at 80 degrees can be fabricated by building up the trench with approximately 150-160 or more trench segments. Each trench segment can be formed to have a depth of about 0.4-0.5 um during each vertical etch process step; and by enlarging the opening in the resist layer by about 0.1-0.2 um during each resist etch process step. The process can be efficiently carried out using an ICP RIE tool or another suitable tool in a time period of, for example, 80-100 minutes. In general, the process can be implemented with any etch tool that has the capability to run two etch processes alternately such as an STS multiplex ICP etch system. It should also be understood that the above is intended to be one example only of an application of the present invention, as the invention may be varied significantly depending on the type of tool used and on many other factors. The tapered trench fabrication process according to the present invention can readily be integrated into overall procedures typically performed in the manufacture of semiconductor integrated circuits, MEMS devices, RF power semiconductor devices and the like. For example, the trench etching process of the present invention can be followed up by any suitable metal deposition procedures. Due to the slope of the trench, the deposition is very conformal in nature; and the procedure has been successfully used in applications which use 3-dimensional device structures with final metal interconnect. To emphasize the wide applicability of the present invention, FIGS. 9 - 12 schematically illustrate steps for fabricating a Z-axis accelerometer according to one presently preferred embodiment of the invention. Conventional accelerometers have silicon beams on the same plane. Hence, they are able to sense movement only in the x-axis or the y-axis. In order to also sense movement in the z-axis, it is necessary to make beams which are positioned in two planes. This can readily be accomplished using the sloped trench etching process of the present invention. Initially, as shown in FIGS. 9 a - 9 c, the cavity for the z-axis is defined. Specifically, a substrate 100 is provided with a resist layer 104 within which a suitably formed and located opening 103 has been provided ( FIG. 9 a ); and then the resist layer is rounded around the opening as shown at 105 in FIG. 9 b. A tapered cavity 102 is then etched in the silicon substrate 100 as shown in FIG. 9 c utilizing the trench etching process described above with reference to FIGS. 1 - 8 . Thereafter, as shown in FIGS. 10 a - 10 c, the remaining resist layer 104 is removed ( FIG. 10 a ), a masking oxide deposition procedure is performed to apply an oxide layer 106 onto the exposed surfaces of the substrate ( FIG. 10 b ), and a sensor masking and cavity oxide etch procedure is carried out to define the masks 110 for the sensor beams ( FIG. 10 c ). Thereafter, silicon trenches are etched as shown in FIG. 11 a. These trenches are formed in different planes. Subsequently, a layer of oxide is deposited and etched back using an RIE process. This forms oxide spacers by the side of the silicon beams 112 , 114 and 116 as shown in FIG. 11 b. Then silicon beams 112 and 114 are undercut and release etched ( FIG. 12 a ) to form a sensor beam 1 and sensor beam 2 at two planes. Finally, the spacer oxide is stripped along with the masking oxide ( FIG. 12 c ). The tapered trench etching method according to the present invention can be advantageously incorporated into processes for the fabrication of numerous structures including MEMS devices and RF power semiconductor devices such as LDMOS and VDMOS devices. By utilizing the method according to the present invention to fabricate a trench LDMOS, for example, a reduction of P&plus;sinker resistance between the source and the substrate is achieved with a reduction of 7-8 hours in implant drive-in time. In general, the tapered trench fabricating method according to the present invention provides a number of significant advantages over existing fabricating procedures. Among such advantages include the following: 1. As mentioned previously, the method according to the present invention can be used to etch very deep sloped trenches (up to a depth of 80-100 um or more); while, at the same time, the method is just as effective in etching shallower trenches (about 10 um or less). Existing procedures, on the other hand, are generally effective in forming sloped trenches up to a depth of only about 10 um. 2. In many prior techniques, particularly in earlier techniques, trench etching in silicon is done using a combination of HCl, HBr, SiCl 4 and BCl 3 which are not only hazardous in nature, but also react with the process chamber walls and rapidly reduce their useful life. They also produce by-products that redeposit themselves on the chamber walls and, hence, necessitate frequent maintenance. The process according to the present invention can be carried out using only harmless gases such as SF 6 and O 2 which produce by-products which are highly volatile and thus necessitate very little maintenance. 3. The prior art frequently uses chlorine or bromine chemistry to etch silicon trenches. The use of these materials imposes an additional post-etch cleaning process to clear the by-products from the wafer to avoid corrosion with aluminum interconnects. In practicing the present invention, a process such as a SF 6 /C 4 F 8 /O 2 process may be utilized which does not pose any risk of corrosion to aluminum interconnects. 4. The present invention, by using SF 6 /C 4 F 8 /O 2 chemistry also provides a very high selectivity to the resist during the vertical etch step (i.e., 50-60:1) as compared to prior techniques which give a selectivity typically in the range of about 2-3:1. This provides the freedom to control the vertical etch rate independently from the resist etch process steps which control the slope. 5. The prior art often achieves a sloped etch by depositing additional polymeric material to progressively narrow down the trench opening. This results in the reaction chamber becoming very dirty and also requires frequent cleaning of the chamber. The method according to the present invention does not generate any polymeric materials; and, instead, removes the resist slowly. 6. The present invention also provides the advantage of being able to independently control the vertical etch rate and the slope angle by appropriately adjusting the cycle time in the process. Such independent control is not present in the prior art. 7. In the prior art, it is often necessary to use a dielectric mask layer such as oxide or nitride which needs to be deposited and patterned before starting the sloped trench etch process. This results in extra processing steps being necessary. In the method according to the present invention, however, only resist need be used to etch the silicon trenches. This greatly reduces the processing steps and the overall processing cost. While what has been described herein constitutes presently preferred embodiments of the invention, it should be recognized that the invention can be varied in numerous ways. Accordingly, it should be understood that the present invention should be limited only insofar as is required by the scope of the following claims.