MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE

A manufacturing method for a semiconductor device includes: obtaining a pre-processed semiconductor structure, wherein the pre-processed semiconductor structure comprises a metal layer (103) having a first exposed surface (1032), and the first exposed surface (1032) of the metal layer has a protrusion portion (1031); arranging a protective layer (104) on the first exposed surface (1032) of the metal layer, wherein the protective layer (104) at least covers part of the metal layer (103) that excludes the protrusion portion (1031); removing the protrusion portion (1031) to form on the metal layer (103) a second exposed surface (1033) of the metal layer (103); and forming a dielectric layer (105) on an area where the first exposed surface (1032) is located, wherein the dielectric layer (105) completely covers the area where the first exposed surface (1032) is located.

TECHNICAL FIELD

The present disclosure relates to the field of manufacturing semiconductor devices, and in particular to a method of manufacturing a semiconductor device and a semiconductor device.

BACKGROUND

An electrical test may be performed to determine quality of a semiconductor device while manufacturing the semiconductor device. However, a probe for performing the electrical test may be stuck into a metal layer of the device, causing deformation of the metal layer. A height of deformation may be as high as 3 micrometers or more. After the electrical test, a post-processing, such as bonding, photolithography and so on, may be performed on the semiconductor device. While performing the post-processing, a probe mark on a surface of an aluminum pad may cause processing abnormalities, and the device may be scrapped. In the art, no particular process is available to treat the surface of the metal layer that has the probe mark. Therefore, the electrical test for the semiconductor device may be omitted, and the post-processing may be performed directly. Other tests may be performed after all processes are completed. However, when the electrical test is omitted in the manufacturing process and performed after all processes being completed, it may be difficult to find out whether an electrical abnormality is caused before the post-processing or in the post-processing. When the semiconductor device has the electrical abnormality before the post-processing, failure of identifying the abnormality may cause waste of the post-processing processes and material.

SUMMARY OF THE DISCLOSURE

According to a first aspect of the present disclosure, a method of manufacturing a semiconductor device is provided and includes: obtaining a pre-treated semiconductor structure, wherein the pre-treated semiconductor structure comprises a metal layer having a first exposed surface, and the first exposed surface of the metal layer has a protruded portion; forming a protective layer on the first exposed surface of the metal layer, wherein the protective layer at least covers the rest of the metal layer other than the protruded portion; removing the protruded portion to expose a part of the first exposed surface of the metal layer, wherein the exposed part of the first surface of the metal layer is defined as a second exposed surface of the metal layer; and forming a dielectric layer on an area where the first exposed surface is located, wherein the dielectric layer covers the entire area where the first exposed surface is located.

In some embodiments, the obtaining a pre-treated semiconductor structure includes: providing a semiconductor structure, wherein the semiconductor structure comprises a substrate, a capping layer disposed on a surface of the substrate, and a metal layer disposed in the capping layer of the substrate; forming an opening in the capping layer to expose a part of the metal layer to form the first exposed surface; and inserting a probe into the first exposed surface of the metal layer to perform an electrical test for the semiconductor structure, allowing the protruded portion to be formed on the first exposed surface of the metal layer.

In some embodiments, the obtaining a pre-treated semiconductor structure, includes: providing a semiconductor structure, wherein the semiconductor structure comprises a substrate and a metal layer disposed on a surface of the substrate, an exposed surface of the metal layer serves as the first exposed surface; and inserting a probe into the first exposed surface of the metal layer to perform an electrical test for the semiconductor structure, allowing the protruded portion to be formed on the surface of the metal layer.

In some embodiments, the forming a protective layer on the first exposed surface of the metal layer, includes: depositing the protective layer on the first exposed surface of the metal layer, wherein a thickness of a portion of the protective layer, which covers the protruded portion, is less than a thickness of another portion of the protective layer, which covers the rest of the metal layer other than the protruded portion.

In some embodiments, the protective layer is deposited on the first exposed surface of the metal layer by chemical vapor deposition, and the protective layer is any one of a silicon dioxide layer and a silicon nitride layer.

In some embodiments, the removing the protruded portion to allow a second exposed surface to be formed on the metal layer, includes: removing the portion of the protective layer covering the protruded portion by performing dry etching to expose the protruded portion, while reducing the thickness of the another portion of the protective layer covering the rest of the metal layer other than the protruded portion simultaneously; and performing wet etching on the exposed protruded portion to form the second exposed surface of the metal layer.

In some embodiments, the removing the protruded portion to allow a second exposed surface to be formed on the metal layer, includes: removing the exposed protruded portion by cutting.

In some embodiments, the removing the protruded portion to allow a second exposed surface to be formed on the metal layer, includes: removing the protruded portion and the protective layer covering the protruded portion by cutting.

In some embodiments, after the forming a dielectric layer on an area where the first exposed surface is located, wherein the dielectric layer covers the entire area where the first exposed surface is located, the method further includes: planarizing a surface of the dielectric layer.

In some embodiments, after the planarizing a surface of the dielectric layer, the method further includes: forming a conductive plug in the dielectric layer, wherein an end of the conductive plug is connected to the first exposed surface of the metal layer, and the conductive plug is configured to achieve electrical lead-out for the metal layer.

In some embodiments, the forming a conductive plug on the dielectric layer, includes: forming a through hole in the planarized dielectric layer and/or the protective layer, to expose a part of the metal layer; and filling conductive material in the through hole.

In some embodiments, the metal layer is made of aluminum, and the conductive plug is made of copper.

In some embodiments, an end of the conductive plug in the through hole is exposed from the dielectric layer, and a surface of the exposed end of the conductive plug aligns with a surface of the dielectric layer away from the metal layer.

According to another aspect of the present disclosure, a semiconductor device, which is manufacture by the above method, is provided. The semiconductor device includes: a substrate, a metal layer, a protective layer, a dielectric layer. The metal layer has a first surface. The metal layer is formed on the substrate, and the first surface of the metal layer is a surface of the metal layer far away from the substrate. The protective layer covers a first area of the first surface of the metal layer, and does not cover a second area of the first surface of the metal layer. The dielectric layer is formed on the protective layer and the second area of the first surface of the metal layer.

In some embodiments, the second area of the first surface of the metal layer is an area of removing a protruded portion formed on the first surface of the metal layer, and the protruded portion is formed by inserting a probe into the first surface of the metal layer to perform an electrical test.

In some embodiments, a recess is defined in the first area of the first surface, a wall of the recess is covered by the protective layer, and a portion of the protective layer is received in the recess.

In some embodiments, the recess is formed by inserting the probe into the first surface of the metal layer to perform an electrical test.

In some embodiments, a through hole is formed in the dielectric layer and/or the protective layer, and a conductive plug is formed in the through hole and connected to the first surface of the metal layer, to achieve electrical lead-out for the metal layer.

In some embodiments, an end of the conductive plug in the through hole is exposed from the dielectric layer, and a surface of the exposed end of the conductive plug aligns with a surface of the dielectric layer away from the metal layer.

In some embodiments, the metal layer is made of aluminum, and the conductive plug is made of copper.

DETAILED DESCRIPTION

Technical solutions in embodiments of the present disclosure will be clearly and completely described below by referring to accompanying drawings in the embodiments of the present disclosure. Apparently, the described embodiments are only a part of but not all of the embodiments of the present disclosure.

As shown inFIG.1andFIGS.2ato2g,FIG.1is a flow chart of a method of manufacturing a semiconductor device according to the present disclosure, andFIGS.1ato1gare structural schematic views of products corresponding to operations of the method of manufacturing the semiconductor device shown inFIG.1. The method of manufacturing the semiconductor device of the present embodiment may include following operations.

In an operation S11, a pre-treated semiconductor structure may be obtained. The pre-treated semiconductor structure may include a metal layer having a first exposed surface, and the first exposed surface of the metal layer may have a protruded portion.

In detail, the semiconductor structure may be provided. As shown inFIG.2a, the semiconductor structure may include a substrate101, and a metal layer103disposed on a surface of the substrate101. The exposed surface of the metal layer103may be a first exposure surface1032. In detail, the first exposure surface1032may be a surface of the metal layer103away from the substrate101and a side face of the metal layer103. A probe may be inserted into the first exposed surface1032of the metal layer103to perform an electrical test on the semiconductor structure, allowing the protruded portion1031to be formed on the first exposed surface1032of the metal layer103. In another embodiment, as shown inFIG.2b, the semiconductor structure may include the substrate101, a capping layer102disposed on the surface of the substrate101, and the metal layer103disposed in the capping layer102. An opening may be defined in the capping layer10to expose a part of the metal layer103. An exposed surface of the metal layer103may be the first exposed surface1032. The probe may be inserted into the first exposed surface1032of the metal layer103to perform the electrical test on the semiconductor structure, allowing the protruded portion1031to be formed on the first exposed surface1032of the metal layer103.

In an operation S12, a protective layer may be formed on the first exposed surface of the metal layer, and the protective layer may at least cover the rest of the metal layer other than the protruded portion.

In detail, as shown inFIG.2c, the protective layer104may be deposited on the first exposed surface1032of the metal layer103to provide a step coverage for the first exposed surface1032of the metal layer103, such that a thickness of the protective layer104, which covers the protruded portion103, may be less than a thickness of the protective layer104, which covers the rest portion of the metal layer103other than the protruded portion103. The protective layer104that covers the protruded portion103may be removed by performing dry etching. At the same time, the thickness of the protective layer104, which covers the rest portion of the metal layer103other than the protruded portion103, may be reduced. In another embodiment, as shown inFIG.2d, the protective layer104may be deposited on the first exposed surface1032of the metal layer103. The protective layer104may cover the rest portion of the metal layer other than the protruded portion1031, and the protective layer104that covers the protruded portion1031may not need to be removed.

In an embodiment, the protective layer104may be deposited on the first exposed surface1032of the metal layer103by chemical vapor deposition, and the protective layer104may be a silicon dioxide layer or a silicon nitride layer.

In an operation S13, the protruded portion may be removed, allowing a second exposed surface to be formed on the metal layer.

In detail, as shown inFIG.2e, dry etching may be performed on the protruded portion1031to expose the protruded portion1031firstly, and subsequently, wet etching may be performed on the exposed protruded portion1031to form the second exposed surface1033on the metal layer103. In an embodiment, the exposed protruded portion1031may be removed by cutting the protruded portion1031to form the second exposed surface1033on the metal layer103. In an embodiment, when the protective layer104covering the protruded portion1031is not removed, the protruded portion1031and the protective layer104covering the protruded portion1031may be removed together by cutting, such that the second exposed surface1033may be formed on the metal layer103.

In an operation S14, a dielectric layer may be formed on an area where the first exposed surface is located, such that the dielectric layer may completely cover the area where the first exposed surface is located.

In detail, the dielectric layer105may be deposited by chemical vapor deposition on the metal layer103that has the protruded portion1031removed, such that the dielectric layer105may cover the area1032where the first exposed surface is located. That is, the dielectric layer105may cover the protective layer104and the second exposed surface1033.

In an embodiment, as shown inFIG.2f, the dielectric layer105may be formed on the area where the first exposed surface1032is located, such that the dielectric layer105may completely cover the area where the first exposed surface1032is located. The area where the first exposed surface1032is located may be a part of the surface of the metal layer103exposed through the opening in the capping layer102. The area where the first exposed surface1032is located before the protruded portion1031being removed and the area where the first exposed surface1032is located after the protruded portion1031being removed may be a same area.

In another embodiment, as shown inFIG.2g, the dielectric layer105may be formed on the area where the metal layer103is located, such that the dielectric layer105may completely cover the area where the metal layer103is located. The area where the first exposed surface1032is located may be a part of the surface of the metal layer103that does not contact the substrate101. The area where the first exposed surface1032is located before the protruded portion1031being removed and the area where the first exposed surface1032is located after the protruded portion1031being removed may be a same area.

The dielectric layer105may be a silicon oxide layer, a silicon nitride layer or a composite layer of silicon oxide and silicon nitride. The dielectric layer105may be configured for protecting the metal layer103in subsequent processes. A surface of the dielectric layer105may be planarized. In an embodiment, a conductive plug may be formed in the dielectric layer105. An end of the conductive plug may be connected to the first exposed surface1032of the metal layer103that has the protruded portion1031removed. The conductive plug is used to electrically lead out the metal layer103. In an embodiment, the surface of the dielectric layer105may be planarized. The planarized surface of the dielectric layer105may not be lower than the surface of the metal layer103. A through hole may be defined in the planarized dielectric layer105, such that the metal layer103may be partially exposed. Conductive material may be received in and fill the through hole. Material of the metal layer103may be aluminum, and material of the conductive plug may be copper.

Subsequently, the method may further include other processing, such as bonding, photolithography, and so on.

As shown inFIGS.3and4a-4k,FIG.3is a flow chart of a method of manufacturing a semiconductor device according to an embodiment of the present disclosure, andFIGS.3ato3kare structural schematic views of products corresponding to operations of the method of manufacturing the semiconductor device shown inFIG.3. The method of manufacturing the semiconductor device of the present embodiment may include following operations.

In an operation S201, the semiconductor structure may be provided. The semiconductor structure may include the substrate, the capping layer disposed on the surface of the substrate, and the metal layer disposed in the capping layer.

In detail, the provided semiconductor structure10may be a wafer or other semiconductor structure10. In the present embodiment, the semiconductor structure10may be the wafer. As shown inFIG.4a, the semiconductor structure10may include the substrate101, the capping layer102, and the metal layer103. The capping layer102may cover the surface of the substrate101. The metal layer103may be disposed in the capping layer102.

In an embodiment, the substrate101may be made of semiconductor material. For example, the substrate101may be a Si substrate, a Ge substrate, a SiGe substrate, a Silicon On Insulator (SOI), or a Germanium On Insulator (GOI), and so on. In an embodiment, the substrate101may also be a substrate101that includes other elements or compounds, such as GaAs, InP, SiC, and so on. In an embodiment, the substrate101may be a structure having laminated layers, such as Si/SiGe, and so on. In an embodiment, the substrate101may be an epitaxial structure, such as a silicon germanium on insulator (SGOI) and so on. In the present embodiment, the substrate101may be the Si substrate.

In an embodiment, the capping layer102may be an insulating dielectric layer. The cover102may be a single layer or a structure having laminated layers. For example, material of the capping layer102may be silicon nitride, silicon oxide, or a combination thereof. The silicon oxide may be Fluorinated Silicate Glass (FSG). The capping layer102may serve as a barrier to prevent elements of the metal layer103from diffusing into the substrate101.

In an embodiment, the metal layer103may be disposed in one capping layer102or between stacked adjacent capping layers102. The material of the metal layer103may be one of copper, aluminum, tungsten and so on, or may be other conductive materials. In the present embodiment, the material of the metal layer103may be aluminum.

In an operation S202, the opening may be formed in the capping layer, such that the first exposure surface may be formed on the metal layer.

In detail, as shown inFIG.4b, the surface of the capping layer102away from the substrate101may be dry etched, allowing the surface of the metal layer103in the capping layer102to be exposed to form the first exposure surface1032. In an embodiment, a width of the opening defined in the capping layer102may be less than a width of the metal layer103. In detail, a position of the capping layer102to define the opening may be determined, and plasma etching may be performed, till the surface of the metal layer103in the capping layer102is exposed. The exposed surface of the metal layer103may be the first exposed surface1032. Other dry etching operations may be performed to expose the surface of the metal layer103.

In an operation S203, the probe may be inserted into the first exposed surface of the metal layer to perform the electrical test on the semiconductor structure, allowing the protruded portion to be formed on the first exposed surface of the metal layer.

In detail, the electrical test may be performed on the semiconductor structure10. The probe for the electrical test may be inserted to an inside of the metal layer103from the first exposed surface1032of the metal layer103exposed at the opening of the capping layer102. The protruded portion1031may be formed on the first exposed surface1032of the metal layer103in an area adjacent to a position where the probe is inserted. Electrical properties of the semiconductor structure10may be tested to determine whether the semiconductor structure10is defective. When the test is completed, the probe may be pulled out, a recessed area and the protruded portion1031may be formed on the first exposed surface1032of the metal layer103, as shown inFIG.4c. In this way, the semiconductor structure10after a pre-treatment may be obtained.

In an operation S204, the protective layer may be deposited on the first exposed surface of the metal layer. The thickness of the protective layer covering the protruded portion may be less than the thickness of the protective layer covering the rest of the metal layer other than the protruded portion.

In detail, the protective layer104may be deposited on the first exposed surface1032of the metal layer103by chemical vapor deposition, such that the thickness of the protective layer104deposited on the protruded portion1031may be less than the thickness of the protective layer104deposited on a surface of the rest of the metal layer103other than the protruded portion1031. In another embodiment, the protective layer may also be disposed on the metal layer103by thermal oxidation film formation, gluing, metal sputtering, and so on. In this way, the thickness of the protective layer104covering the surface of the protruded portion1031may be less than the thickness of the protective layer104covering the surface of the rest of the metal layer other than the protruded portion1031, such that the protective layer104that covers the metal layer103may exhibit step coverage, as shown inFIG.4d. In another embodiment, the protective layer104may be made of nitride material or oxide material. In the present embodiment, the material of the protective layer104may be silicon dioxide or silicon nitride.

In an operation S205, the protective layer covering the protruded portion may be removed by dry etching to expose the protruded portion, and at the same time, the thickness of the protective layer covering the rest of the metal layer other than the protruded portion may be reduced.

In detail, as shown inFIG.4e, the protective layer104that provides the step coverage for the metal layer103may be etched. In an embodiment, the protective layer104on the metal layer103may be etched by plasma etching until the entire protective layer104covering the protruded portion103of the metal layer103is removed. The surface of the rest of the metal layer103other than the protruded portion may still be covered by the protective layer104. Etching gas may include NF3, CH3F, CHF3, and oxygen-containing gas. The fluorine (F) may be used to react with the silicon dioxide or the silicon nitride of the protective layer. The protruded portion103of the metal layer103may be exposed, and at the same time, the thickness of the protective layer104that covers the surface of the rest of the metal layer103other than the protruded portion1031may be reduced. In this way, a semiconductor structure10that the surface of the rest of the metal layer103other than the protruded portion1031is covered by the protective layer104may be obtained.

In an operation S206, the exposed protruded portion may be wet etched to form the second exposed surface on the metal layer.

In detail, as shown inFIG.4f, the exposed protruded portion1031of the metal layer103may be removed by wet etching. In an embodiment, the protruded portion1031on the metal layer103that is not covered by the protective layer104may be etched by acid washing or alkaline washing to obtain the second exposed surface1033of the metal layer103. In this way, the protruded portion1031caused by the electrical test probe may be trimmed to prevent the protruded portion1031from affecting subsequent processing on the pre-treated semiconductor structure10. To be noted that, while the exposed protruded portion is being wet etched, the protective layer104covering the surface of the rest of the metal layer103other than the protruded portion1031may also be partially or completely removed. An area of the second exposed surface1033of the metal layer103obtained in this way may be larger than an area of the second exposed surface1033of the metal layer103that has only the protruded portion1031removed. The present disclosure does not limit the areas.

In an operation S207, the dielectric layer may be formed on the area where the first exposed surface is located, such that the dielectric layer may cover the entire area where the first exposed surface is located.

In detail, as shown inFIG.4g, the dielectric layer105may be deposited by chemical vapor deposition on the second exposed surface1033of the metal layer103and on the remaining protective layer104covering the surface of the metal layer103that has the protruded portion1031removed. In this way, a deposited thickness of the dielectric layer105may not be less than a distance from the surface of the capping layer102away from the substrate101to the metal layer103. In another embodiment, the dielectric layer105may be deposited by thermal oxidation film formation, gluing, metal sputtering, and so on, on the second exposed surface1033and on the remaining protective layer104covering the surface of the metal layer103that has the protruded portion1031removed. In an embodiment, the dielectric layer105may be made of one or combination of the nitride material and the oxide material. The material of the dielectric layer105may be the same as the material of the capping layer102. The dielectric layer105may be configured to protect the metal layer103in the subsequent processes.

In an operation S208, the surface of the dielectric layer may be planarized to obtain a dielectric layer having a planarized surface.

In detail, as shown inFIG.4h, the exposed surface of the dielectric layer105may be flat. In an embodiment, a surface of the dielectric layer105away from the metal layer103may be planarized by performing a physical mechanical grinding process. In this way, the exposed surface of the dielectric layer105may be flat, and therefore, the dielectric layer105having the planarized surface may be obtained.

In an operation S209, a through hole may be defined in the dielectric layer after the planarization, allowing the metal layer to be partially exposed.

In detail, as shown inFIG.4i, a mask layer108may be disposed on the dielectric layer105after the planarization. A window may be defined in a surface of the mask layer108as required. In an embodiment, the mask layer108may be a photoresist. In detail, after a surface of the photoresist away from the dielectric layer105is covered with the mask, light irradiation may be performed. A portion of the photoresist that is not irradiated may be washed away to form a through hole. In this way, the irradiated portion may form the mask layer108, and a part of the surface of the dielectric layer105may be exposed through the through hole. The dielectric layer105exposed through the through hole may be removed by dry etching. A through hole106may be defined in the dielectric layer105, and a portion of the metal layer103may be exposed through the through hole106. As shown inFIG.4j, the mask layer108on the dielectric layer105may be removed, such that the surface of the dielectric layer105away from the metal layer103may be exposed. Alternatively, the through hole106may be defined in the dielectric layer105in other ways to expose the part of the metal layer103. It can be understood that in other embodiments, the mask layer108may not be removed at first. The mask layer108may be removed while performing the planarization after metal is received in and fill the through hole106.

It shall be understood that the through hole106may be a through hole in other forms to allow the metal to connect to an external component. The above embodiment only shows an example of the through hole, but does not limit features of the through hole.

In an operation S210, metal may be received in and fill the through hole to form the conductive plug.

In detail, as shown inFIG.4k, metal may be deposited in the through hole106at first, such that a seed layer may be formed on an inner wall of the through hole106. Further, electroplating may be performed to fill the metal into the through hole106, such that the conductive plug107may be formed in the through hole106. An end of the conductive plug may be connected to a part of the metal layer covered by the protective layer104. The metal deposited and electroplated on the dielectric layer105may be grinded, such that the surface of the dielectric layer105away from the metal layer103may be exposed. In addition, an end of the conductive plug107in the through hole106may be exposed, and a surface of the exposed end of the conductive plug107may align with the surface of the dielectric layer105away from the metal layer103. In an embodiment, excessive deposited and electroplated metal may be removed by performing a mechanical grinding process.

In an operation S211, bonding is performed to electrically bond the semiconductor structure to another semiconductor structure by the conductive plug.

In detail, bonding may be performed to electrically bond the semiconductor structure10obtained in the above operations to another semiconductor structure10by the conductive plug107.

According to the method of manufacturing the semiconductor device in the present disclosure, the pre-treated semiconductor structure may be obtained. The pre-treated semiconductor structure may include the metal layer having the first exposed surface. The first exposed surface of the metal layer may have the protruded portion. The protective layer may be disposed on the first exposed surface of the metal layer. The protective layer may at least cover the rest of the metal layer other than the protruded portion. The protruded portion may be removed to form the second exposed surface on the metal layer. The dielectric layer may be disposed on the area where the first exposed surface is located, and the dielectric layer may completely cover the area where the first exposed surface is located. According to the method of manufacturing the semiconductor device in the present disclosure, the protective layer may be disposed on the rest of the metal layer other than the protruded portion to protect the metal layer. The protruded portion may be etched, and the surface of the metal layer of the semiconductor structure may be trimmed. In this way, the height of the protruded portion may not be excessively high, and the dielectric layer covering the metal layer may not be excessively thick. Further, since the protruded portion may not be present, gaps may not be defined around the protruded portion while filling the dielectric layer to cover the metal layer, and subsequent processing of the semiconductor structure may not be affected. Covering the metal layer with the protective layer enabling the surface of the semiconductor structure to be flat, enabling the subsequent processing of the semiconductor structure to be performed easily. The method may be simple and may be implemented easily.

As shown inFIGS.5and6a-6d,FIG.5is a flow chart of a method of manufacturing a semiconductor device according to another embodiment of the present disclosure, andFIGS.5ato5dare structural schematic views of products corresponding to operations of the method of manufacturing the semiconductor device shown inFIG.5. The method of manufacturing the semiconductor device of the present disclosure may include following operations.

In an operation S401, the semiconductor structure may be provided. The semiconductor structure may include the substrate, the capping layer disposed on the surface of the substrate, and the metal layer disposed in the capping layer.

In an operation S402, the opening may be defined in the capping layer, such that the first exposure surface may be formed on the metal layer.

In an operation S403, the probe may be inserted into the first exposed surface of the metal layer to perform the electrical test on the semiconductor structure, allowing the protruded portion to be formed on the first exposed surface of the metal layer.

In an operation S404, the protective layer may be deposited on the first exposed surface of the metal layer. The thickness of the protective layer covering the protruded portion may be less than the thickness of the protective layer covering the rest of the metal layer other than the protruded portion.

In an operation S405, the protective layer covering the protruded portion may be removed by dry etching to expose the protruded portion, and at the same time, the thickness of the protective layer covering the rest of the metal layer other than the protruded portion may be reduced.

In an operation S406, the exposed protruded portion may be wet etched to form the second exposed surface on the metal layer.

In an operation S407, the dielectric layer may be formed on the area where the first exposed surface is located, such that the dielectric layer may cover the entire area where the first exposed surface is located.

The operations of S401to S407of the present disclosure may be the same as the operations of S201to S207in the above embodiments.

In an operation S408, a through hole may be defined in the dielectric layer to allow the metal layer to be partially exposed.

In detail, as shown inFIG.6a, the semiconductor structure50may include a substrate501, a capping layer502, and a metal layer503. The metal layer503may be covered by a protective layer504. A dielectric layer505may be deposited on the protective layer504. A mask layer508may be disposed on the untreated dielectric layer505. A window may be defined in a planarized surface of the mask layer508as needed. In an embodiment, the mask layer508may be a photoresist. In detail, the mask may be disposed on and cover a surface of the photoresist away from the dielectric layer505. The mask may be irradiated after being placed on a flat area of the photoresist. The flat area of the photoresist may be the flat area of the metal layer503. The portion of the photoresist that is not irradiated may be washed away to form the through hole, such that the portion that is irradiated may form the mask layer508, and a portion of the surface of the dielectric layer505may be exposed through the through hole. As shown inFIG.6b, the dielectric layer505exposed through the through hole may be removed by performing the dry etching, a through hole506may be defined in the dielectric layer505, and a portion of the metal layer503may be exposed through the through hole506. The mask layer508on the dielectric layer505may be removed to expose the surface of the dielectric layer505away from the metal layer503. Alternatively, other means may be performed to define the through hole506in the dielectric layer505to expose a part of the metal layer503. It can be understood that in other embodiments, the mask layer508may not be removed at first. The mask layer508may be removed while performing the planarization, after metal is placed to fill the through hole506.

In an operation S409, metal may be received in and fill the through hole to form the conductive plug.

In detail, as shown inFIG.6c, metal may be deposited in the through hole506at first, such that the metal may form a seed layer on the inner wall of the through hole506. Subsequently, metal may be received in and fill the through hole506by electroplating, such that the conductive plug507may be formed in the through hole506.

In an operation S410, the surface of the dielectric layer may be planarized to obtain the semiconductor structure having a planarized surface.

In detail, as shown inFIG.6d, the surface of the dielectric layer505away from the metal layer503may be planarized. At the same time, the mask layer508disposed on the dielectric layer505and the deposited electroplated metal may be removed. In this way, the surface of the dielectric layer505away from the metal layer503may be exposed. At the same time, the conductive plug507may be treated, such that the surface of the exposed end of the conductive plug507may align with the surface of the planarized dielectric layer505away from the metal layer503to obtain the semiconductor structure50having the planarized surface.

In an operation S411, bonding may be performed to electrically bond one semiconductor structure to another semiconductor structure by the conductive plug.

In detail, bonding may be performed to electrically bond the semiconductor structure50obtained from the above operations to another semiconductor structure50the conductive plug507.

According to the method of manufacturing the semiconductor device in the present disclosure, the pre-treated semiconductor structure may be obtained. The pre-treated semiconductor structure may include the metal layer having the first exposed surface. The first exposed surface of the metal layer may have the protruded portion. The protective layer may be disposed on the first exposed surface of the metal layer. The protective layer may at least cover the rest of the metal layer other than the protruded portion. The protruded portion may be removed to form the second exposed surface on the metal layer. The dielectric layer may be formed above the first exposed surface and the second exposed surface and may protect the metal layer. According to the method of manufacturing the semiconductor device in the present disclosure, the protective layer may be disposed on the rest of the metal layer other than the protruded portion to protect the metal layer. The protruded portion may be etched, and the surface of the metal layer of the semiconductor structure may be trimmed. In this way, the height of the protruded portion may not be excessively high, and the dielectric layer covering the metal layer may not be excessively thick. Further, since the protruded portion may not be present, gaps may not be defined around the protruded portion while filling the dielectric layer to cover the metal layer, and subsequent processing of the semiconductor structure may not be affected. The metal layer is covered with the protective layer, such that the surface of the semiconductor structure can be flat and the subsequent processing of the semiconductor structure can be performed easily. The method may be simple and may be implemented easily.

According to another aspect of the present disclosure, a semiconductor device, which is manufacture by the above method, is provided. The semiconductor device includes: a substrate, a metal layer, a protective layer, a dielectric layer. The metal layer has a first surface. The metal layer is formed on the substrate, and the first surface of the metal layer is a surface of the metal layer far away from the substrate. The protective layer covers a first area of the first surface of the metal layer, and does not cover a second area of the first surface of the metal layer. The dielectric layer is formed on the protective layer and the second area of the first surface of the metal layer.

In some embodiments, the second area of the first surface of the metal layer is an area of removing a protruded portion formed on the first surface of the metal layer, and the protruded portion is formed by inserting a probe into the first surface of the metal layer to perform an electrical test.

In some embodiments, a recess is defined in the first area of the first surface, a wall of the recess is covered by the protective layer, and a portion of the protective layer is received in the recess.

In some embodiments, the recess is formed by inserting the probe into the first surface of the metal layer to perform an electrical test.

In some embodiments, a through hole is formed in the dielectric layer and/or the protective layer, and a conductive plug is formed in the through hole and connected to the first surface of the metal layer, to achieve electrical lead-out for the metal layer.

In some embodiments, an end of the conductive plug in the through hole is exposed from the dielectric layer, and a surface of the exposed end of the conductive plug aligns with a surface of the dielectric layer away from the metal layer.

In some embodiments, the metal layer is made of aluminum, and the conductive plug is made of copper.

The above description is only an embodiment of the present disclosure and does not limit the scope of the present disclosure. Any equivalent structure or equivalent process transformation based on the contents of the specification and the accompanying drawings of the present disclosure, directly or indirectly applied in other related fields, shall be equally covered by the scope of the present disclosure.