CROSS COUPLE DESIGN FOR HIGH DENSITY STANDARD CELLS

The present disclosure relates to semiconductor structures and, more particularly, to a cross couple design for high density standard cells and methods of manufacture. The structure includes a first contact connected in a cross couple circuit to at least two gate structures, and a second contact connected to the first contact at a location which is devoid of any via connection.

BACKGROUND

The present disclosure relates to semiconductor structures and, more particularly, to a cross couple design for high density standard cells and methods of manufacture.

As technology scales, the importance of logic scaling also grows. However, traditional approaches to scaling of standard cells (e.g., the building blocks of logic design) are not effective due to lithographic limitations. Cross-coupling techniques have been implemented to mitigate the effects of such lithographic limitations to provide continued scaling of standard cells. For example, a cross couple may be implemented by inserting a dummy polysilicon gate, which causes an area bloat, or by using a sub-ground rule special construct in a middle of the line (MOL). However, complex layout designs such as the cross couple are also becoming increasingly difficult to enable as technology scales.

SUMMARY

In an aspect of the disclosure, a structure comprises: a first contact connected in a cross couple circuit to at least two gate structures; and a second contact connected to the first contact at a location which is devoid of any via connections.

In an aspect of the disclosure, a structure comprises: a first gate line; a second gate line separated from and diagonally positioned from the first gate line; a contact that connects to both the first gate line and the second gate line, on a first wiring layer; and a  wiring structure connecting to the contact and active regions of the first gate line and the second gate line.

In an aspect of the disclosure, a method comprises: forming a first contact connected in a cross couple circuit to at least two gate structures; and forming a second contact to the first contact at a location which is devoid of any via connections.

DETAILED DESCRIPTION

The present disclosure relates to semiconductor structures and, more particularly, to a cross couple design for high density standard cells and methods of manufacture. In embodiments, two adjacent gates may be cut into segments, with a diagonal contact connected to two segments, and a horizontal co-planar contact connected to the diagonal gate contact on a same level as the diagonal contact. Advantageously, logic area scaling is improved, and no additional mask adders are required in comparison to known circuit layouts.

In contrast to known circuits, the present disclosure includes an additional diagonal contact added to directly connect polysilicon gate segments on a single mask layer. Further, an additional horizontal contact may be used for a middle of line (MOL) connection to the diagonal contact in a standard cell. Thus, in contrast to known circuits, the present disclosure improves logic area scaling, does not require any additional mask adders, and improves MOL congestion.

In more specific embodiments of the present disclosure, a structure includes: a first gate contact connected to at least two gate segments in a cross couple circuit, and a second MOL contact connected to the first gate contact at a contact point of the cross couple circuit. In further aspects, a logic gate circuit includes: a first set of polysilicon gate lines connected through a base metal layer; a second set of polysilicon gate lines connected to the first set of polysilicon gate lines through a first metal line; a second metal line connected to the first metal line through a plurality of metal layers higher than the base metal layer; and the second metal line co-planar with the first metal line.

FIGS.1A and1Bshow a cross couple design and a cross couple circuit, respectively, in accordance with aspects of the present disclosure. In embodiments, the structure10may be formed using semiconductor-on-insulator (SOI), a bulk wafer, or utilizing FinFet technologies. In an example, the structure10may include a semiconductor-on-insulator (SOI) substrate composed of any suitable semiconductor material including, but not limited to, Si, SiGe, SiGeC, SiC, GaAs, InAs, InP, and other III/V or II/VI compound semiconductors. Also, a standard flip-flop logic circuit may include three cross couple circuits (e.g., three cross couple circuits60inFIG.1B). Further, the flip-flop logic circuit may be approximately 40% of the logic content by area. Therefore, the present disclosure enables an approximate 10% area savings in sequential logic (e.g., flip flop area) which corresponds to an approximate 4% reduction in logic scaling area.

The structure10shown inFIGS.1A and1Bincludes upper FETs70,80and lower FETs90,100. In embodiments, the FETs70,80may be PFETs, whereas, the FETs100may be NFETs. In embodiments, the FETs70,90and FETs80,100may be separated by a gate cut30. As should be understood by those of skill in the art, the PFETs80and the NFETs90,100form a cross couple circuit60as depicted in the circuit ofFIG.1B. And, as should further be understood, the structure10may be used for specific layout connections prevalent in a sequential logic.

A standard gate contact20contacts each of the FETs80,90. A diagonal gate contact40connects the FETs70,100. The diagonal contact40spans across or over the gate cut30. The standard gate contact20, the gate cut30, and the diagonal contact40are within shallow trench isolation (STI) regions. The diagonal gate contact40allows a connection between the FETs70,100, without requiring insertion of a dummy gate structure (which also saves area). A metal layer25(on a first metal layer, M1), extends over the diagonal gate contact40and connects to the active regions50. A gate structure (i.e., transistor)55may be provided on sides of the FETs70,80,90,100.

Still referring toFIGS.1A and1B, each FET70,80,90,100may be polysilicon gate structures (i.e., a polysilicon gate line), which traverse, e.g., extend across, multiple active regions in a vertical direction. As an example, the FET70(e.g., gate line) may be separated from and diagonally positioned from of the FET100(e.g., gate line) in a cross couple circuit configuration. The diagonal gate contact40may connect to the FET70and the FET100. The base metal layer (i.e., the metal layer25) may be a wiring structure connected to at least one of the source/drain nodes of the FETs70,80,90,100through the  active regions50. For example, as shown inFIG.1A, the metal layer25may be a wiring structure connected to the diagonal gate contact40and the active regions50of the gate lines corresponding to the FETs70,100. The FETs80,90are parallel to the FETs70,100and are separated from one another by the gate cut30.

It should be understood by those of skill in the art, though, that the FETs70,80,100may be polysilicon gate structures (i.e., a polysilicon gate line) or metal gate structures using conventional workfunction metals, e.g., tungsten, etc. Also, in embodiments, the FETs70,80,90,100may be fabricated using known first gate processes or replacement gate processes such that no further explanation is required herein for a complete understanding of the present disclosure. For example, the FETs70,90,100may be finFETs manufactured using conventional sidewall image transfer (SIT) or self-aligned couple patterning (SADP) processes. In embodiments, the diagonal gate contact40may have a same material or different material as the FETs70,80,90,100.

InFIG.1A, the standard gate contact20may be co-planar with the diagonal gate contact40(i.e., on a same layer/level) and may connect to the gates of the FETs80,90. In this way, it is possible to simplify the fabrication processes by saving masking processes. In addition, the diagonal gate contact40may be directly contacting the FETs100in a MOL layer without the need for any additional via or MOL connections.

FIG.2shows a cross couple design with a horizontal contact in accordance with aspects of the present disclosure.FIG.2is similar toFIG.1A, with the exception of the horizontal contact120, via contacts130, and area135. In particular, the structure10bofFIG.2includes the standard gate contacts20, the gate cut30, the diagonal gate contact the active region50, a horizontal contact120, contact122, FET133, the FETs70,80,100, via contacts130, and area135. The standard gate contact20is remote from the diagonal gate contact40and connects to gates of the FETs80,90. Further, the standard gate contact20is on a same wiring level as the diagonal contact40and the horizontal contact120.

InFIG.2, the horizontal contact120may be a rectangular shape connecting to the diagonal gate contact40. In embodiments, the horizontal contact120connects to the diagonal gate contact40through a plurality of metal lines which are higher than the base metal layer (i.e., the metal layer25shown inFIG.1A). The diagonal gate contact40may include a convex shape at the ends, i.e., shapes which are parallel to the gates of the FETs100. That is, in embodiments, the diagonal gate contact40may have a shape comprising a diagonal portion spanning between the FETs70,100(i.e., extend over the gates of the FETs70and100), with ends that run parallel to the direction of the FETs80,

In the embodiment shown inFIG.2, the horizontal contact120may be separated or isolated from the gates of FETs70,80,90,100due to a nitride liner cap in between. In more specific embodiments, a silicon carbon nitride (SiCN) liner cap may be used as an etch stop over the gates of FETs70,80,90,100. As a result, the standard gate contact20contacts (i.e., directly contacts) the gates of FETs80,90and the horizontal contact120; however, the horizontal contact120does not connect to the FETs80,90.

InFIG.2, via congestion is avoided by having no via connection at area135(i.e., an area devoid of any via connections at a location in which the horizontal contact120connects to the diagonal gate contact40). Further, the horizontal contact120extends over the gate cut30, which separates gates of the FETs80,100. In this way, it is possible to have the horizontal contact120and the diagonal gate contact40co-planar to each other and at a same wiring level. The horizontal contact120and the diagonal gate contact may include a same material, i.e., tungsten. Accordingly, it is possible to have an approximately 10% area savings in sequential logic and 4% total logic scaling, with no additional masks required.

FIGS.3-7show alternative cross couple designs with different connection schemes in accordance with aspects of the present disclosure. For example, in structure ofFIG.3, the horizontal contact120may be connected to the gate of FET133. Also, inFIG.3, there is only one gate cut such that the horizontal contact120spans over the gate of FET133. The gate of FET134may connect to the gate of FET70by the diagonal contact40. The connection between the horizontal contact120and the gate may be at a metal layer or at a gate contact.

InFIG.4, the structure10dincludes a contact138connected to the horizontal contact120and a tab portion139of the active region. The contact138may be an L-shape extending between the diagonal gate contact40and the active region50. The contact138may also extend over a single gate cut30. The remaining features of the structure10dmay be similar to the structure shown inFIG.3such that no further explanation is required for a complete understanding of the present disclosure.

InFIG.5, the structure10eincludes a vertical contact140connected to the diagonal contact40and extends parallel to the FETs70,80,90,100. In embodiments, the vertical contact140may be parallel to and extends directly over the gate of the FET70, and the diagonal contact40has an end that extends over the gate of the FET70; although other configurations are also possible, e.g., directly over any of the FETs, depending on the design. The vertical contact140may connect directly to the FET70. In another embodiment, the vertical contact140may not connect directly to the FET70. The remaining features of the structure10emay be similar to the structure shown inFIG.1such that no further explanation is required for a complete understanding of the present disclosure.

InFIG.6, the structure10fincludes the diagonal gate contact40with a straight profile, i.e., no convex or convex shape at the ends. Also, in this embodiment, the diagonal gate contact40may extend beyond the FETs70,100. The remaining features of the structure10fmay be similar to the structure shown inFIG.1such that no further explanation is required for a complete understanding of the present disclosure

InFIG.7, the structure10gincludes the diagonal gate contact40in an inverted S-shape or elongated Z-shape (e.g., concave head style), for example. In this configuration, the gate contact has ends which are perpendicular to a length of gates of the FETs70,100. The remaining features of the structure10gmay be similar to the structure shown inFIG.1such that no further explanation is required for a complete understanding of the present disclosure.

The cross couple design for high density standard cells may be utilized in system on chip (SoC) technology. The SoC is an integrated circuit (also known as a “chip”) that integrates all components of an electronic system on a single chip or substrate. As the components are integrated on a single substrate, SoCs consume much less power and take up much less area than multi-chip designs with equivalent functionality. Because of this, SoCs are becoming the dominant force in the mobile computing (such as in Smartphones) and edge computing markets. SoC is also used in embedded systems and the Internet of Things.