Semiconductor package and method for manufacturing the same

One embodiment provides a semiconductor package by forming a redistribution layer extending from a bonding pad of a semiconductor chip using a photoresist pattern plated with the seed layer. Fabrication of the semiconductor package is relatively simple thereby shortening a manufacturing time and reducing the manufacturing cost, and which can increase an adhered area of input/output terminals and can prevent delamination by connecting and welding the input/output terminals to a pair of redistribution layers.

TECHNICAL FIELD

The present application relates to a semiconductor package and a method for manufacturing the same, and more particularly, to a semiconductor package having a new redistribution layer in a fine pitch, and a method for manufacturing the same.

BACKGROUND

In general, manufacturing of a wafer level semiconductor package of a chip scale includes integrating circuits, such as transistors, on a wafer state semiconductor chip, forming a passivation film on a surface of the semiconductor chip to protect the semiconductor chip from external impacts, and forming a redistribution layer (RDL) that is a conductive metal interconnection line.

FIGS. 6A to 6Gare cross-sectional views sequentially illustrating process operations of a method for manufacturing a conventional semiconductor package. A process of forming a conventional redistribution layer will now be described with reference toFIGS. 6A to 6G.

First, in an operation of providing a wafer, a designed circuit is integrated in a wafer-state semiconductor chip10, and a bonding pad12is formed at a potential portion of an electrical input/output path of the circuit.

A die passivation14for protecting the integrated circuit is formed on the entire surface of the wafer-state semiconductor chip10, and a first passivation film16is formed on the die passivation14(seeFIG. 6A).

Here, a plurality of metal pads12, sometimes called bonding pads12, are formed on the semiconductor chip10in a predetermined array and exposed to the outside. Ends of a redistribution layer (RDL)18(FIG. 6C) are formed on the exposed bonding pads12. The redistribution layer18includes metal interconnection lines for receiving a voltage for driving the circuit integrated in the semiconductor chip10.

A seed layer20includes plating conductive lines for forming the redistribution layer18. The seed layer20is formed throughout top surfaces of the first passivation film16and the bonding pad12by sputtering (seeFIG. 6B).

Subsequently, photoresist22is coated throughout the surface of the wafer state semiconductor chip10, and general exposure and development operations are performed on the photoresist22, thereby exposing potential portions of the bonding pad12and the seed layer20on the semiconductor chip10(seeFIG. 6B).

Subsequently, an electroplating process for forming the redistribution layer18is performed on the bonding pad12of the exposed semiconductor chip10and a potential region of a redistribution layer. If current is allowed to flow through the seed layer20in a state in which the seed layer20is put into a solution containing metal ions, the redistribution layer18is formed on a surface of the seed layer20, that is, on a surface of the seed layer20formed on the bonding pad12and a surface of the potential region of a redistribution layer (seeFIG. 6C).

Next, the photoresist22is stripped for removal (seeFIG. 6D), and the remaining seed layer20, except for the seed layer20existing under the redistribution layer18, is removed through an etching process (seeFIG. 6E), thereby completing formation of the redistribution layer18having predetermined area and length.

Meanwhile, a second passivation film24for preventing external impacts, moisture or other foreign materials from being applied to the redistribution layer18and preventing an electrical short from occurring to neighboring redistribution layers18is formed while encapsulating the redistribution layer18throughout the surfaces of the first passivation film16and the redistribution layer18. An under bump metal (UBM)30that is a metallic electrode terminal is formed by plating a seed layer (not shown) at the other end of the redistribution layer18(seeFIG. 6F).

Thereafter, the input/output terminal32, such as a solder ball, is finally welded onto the under bump metal30(seeFIG. 6G), thereby completing the wafer level package.

However, since a large number of process operations and an extended manufacturing time are required, the manufacturing method of the conventional wafer level package is problematic.

That is to say, after a photoresist for forming a redistribution layer is subjected to patterning and exposure and alignment, it is necessary to perform etching operations for removing the photoresist and the seed layer. That is to say, quite many process operations and extended time are required, resulting in an increase in the manufacturing cost.

In addition, as the wafer level package is manufactured to have a very small size, which is substantially the same as the size of each semiconductor chip, the input/output terminal32, such as a solder ball, welded onto the under bump metal30needs to be very small. Accordingly, an adhered area of the input/output terminal32is very small, suggesting that the input/output terminal32has a weak adhesion strength at its adhering boundary. Thus, the input/output terminal32is prone to delamination even by trivial impacts.

DETAILED DESCRIPTION

One embodiment features that a fine pitch redistribution layer can be formed just by sputtering without using separate removal operations of photoresist and a seed layer.

Referring toFIGS. 1A,1B,1C,1D,1E, cross-sectional views sequentially illustrating process operations of a method for manufacturing a semiconductor package according to an embodiment is illustrated.

As illustrated inFIG. 1A, a photoresist118is first attached to an active surface119of a semiconductor chip100including a bonding pad102as an input/output path of an electrical signal.

Next, referring toFIG. 1B, a patterning process is performed by covering a mask121on a potential region of a redistribution layer pattern in the entire area of the photoresist118and performing exposure and development operations on the other region of the photoresist118.

As the result of the patterning process, referring now toFIGS. 1B,1C together, the region other than the potential region of the redistribution layer pattern is removed from the entire area of the photoresist118, thereby forming a single unit redistribution layer pattern110extending from a portion around the bonding pad102of the semiconductor chip100to a predetermined position131(FIG. 2B) of the semiconductor chip100.

FIG. 2Ais a schematic plan view illustrating the semiconductor package ofFIGS. 1A-1Eat a further stage of fabrication in according to one embodiment.FIG. 2Bis an enlarged plan view of the region IIB of the semiconductor package ofFIG. 2A.FIG. 3is a cross-sectional view of the semiconductor package taken along the line III-III ofFIG. 2B.FIG. 4is a cross-sectional view of the semiconductor package taken along the line IV-IV ofFIG. 2B.FIG. 5is a cross-sectional view of the semiconductor package taken along the line V-V ofFIG. 2B.

Referring now toFIGS. 1C,2A,2B, and3together, the redistribution layer pattern110includes a first ring type photoresist pattern112formed to protrude around the bonding pad102of the semiconductor chip100.

Referring now toFIGS. 2A,2B, and4together, the redistribution layer pattern110further includes a linear photoresist pattern114extending from the first ring type photoresist pattern112to a predetermined position131of the semiconductor chip100.

Referring now toFIGS. 2A,2B, and5together, the redistribution layer pattern110further includes a single unit second ring type photoresist pattern116formed at an end of the linear photoresist pattern114.

Here, the first and second ring type photoresist patterns112and116are shaped of a circular, elliptic or rectangular ring. In particular, the first ring type photoresist pattern112is shaped of a circular ring surrounding the bonding pad102of the semiconductor chip100.

In addition, the first and second ring type photoresist patterns112and116and the linear photoresist pattern114are simultaneously patterned by the exposure and development operations performed on the photoresist118attached to the semiconductor chip100to have the same height.

Next, referring toFIG. 1D, a seed layer120is formed, e.g., plated or sputtered, on the semiconductor chip100including the redistribution layer pattern110and any other features/layers formed thereon. More particularly, the seed layer120is formed on the bonding pad102of the semiconductor chip100, the predetermined position131of the semiconductor chip100, and the redistribution layer pattern110, sometimes called a portion, connecting the bonding pad102of the semiconductor chip100to the predetermined position131of the semiconductor chip100.

The seed layer120includes a first seed layer122plated on the bonding pad102of the semiconductor chip100and second and third seed layers124and126. More particularly, the seed layer120includes three electrically isolated portions that are the first seed layer122, the second seed layer124, and the third seed layer126.

In more detail, referring toFIGS. 1D,2A,2B, and3together, the first seed layer122is plated on the bonding pad102of the semiconductor chip100existing in an interior region of the first ring type photoresist pattern112.

Referring toFIGS. 1D,2A,2B,3,4, and5together, the single unit second seed layer124is plated on the first and second ring type photoresist patterns112and116and the linear photoresist pattern114.

Referring toFIGS. 2A,2B, and5together, the third seed layer126is plated on the passivation film of the semiconductor chip100existing in an interior region of the second ring type photoresist pattern116.

Here, since the first, second, and third seed layers122,124, and126are independently formed, i.e., physically separated from one another, they have not been conductively connected yet.

Accordingly, referring toFIGS. 1E,2A,2B, and3together, in order to conductively connect the first seed layer122to the second and third seed layers124and126, the bonding pad102of the semiconductor chip100is conductively connected to the seed layer120plated on the predetermined position of the semiconductor chip100by the conductive connection member132.

That is to say, the first seed layer122plated on the bonding pad102of the semiconductor chip100and the second seed layer124plated on the first ring type photoresist pattern112are enclosed within and conductively connected to each other by means of the first conductive connection member130.

In addition, referring now toFIGS. 2A,2B, and5together, the second seed layer124plated on the second ring type photoresist pattern116and the third seed layer126plated on the passivation film of the semiconductor chip100existing in the interior region of the second ring type photoresist pattern116are enclosed within and conductively connected to each other by means of the second conductive connection member134.

In one embodiment, the second conductive connection member134forms an input/output terminal for the semiconductor package. The second conductive connection member134is connected and welded to both the second seed layer124and the third seed layer126, sometimes called a pair of redistribution layers. This prevents delamination of the second conductive connection member134. Delamination is further prevented by connecting and welding the second conductive connection member134to the third seed layer126thus increasing the adherence area, i.e., the area to which the second conductive connection member134is connected.

The first and second conductive connection members132and134may be solder paste or solder ball.

Therefore, the first seed layer122plated on the bonding pad102of the semiconductor chip100and the second seed layer124plated on the first ring type photoresist pattern112are conductively connected to each other by means of solder paste or solder ball, i.e., the first conductive connection member132. The second seed layer124plated on the second ring type photoresist pattern116and the third seed layer126existing in an interior region of the second seed layer124are conductively connected to each other by means of solder paste or solder ball, i.e., the second conductive connection member134, thereby completing the semiconductor package according to one embodiment.

As described above, a redistribution layer140is formed from the redistribution layer pattern110including the seed layers122,124,126and the conductive connection members132,134. Since the redistribution layer140extending from the bonding pad102of the semiconductor chip100to the predetermined position131of the semiconductor chip100is configured by a redistribution layer pattern110of a photoresist118and a seed layer plated120thereon, removal operations of the redistribution layer pattern110and the seed layer120can be obviated, unlike the conventional redistribution layer, a manufacturing time can be shortened and the manufacturing cost can be reduced.

Meanwhile, an output signal of the semiconductor chip100may be output to a mother board of an electronic product sequentially passing by the bonding pad102, the first seed layer122, the first conductive connection member132, the second seed layer124and the second conductive connection member134.

This disclosure provides exemplary embodiments of the present invention. The scope of the present invention is not limited by these exemplary embodiments. Numerous variations, whether explicitly provided for by the specification or implied by the specification, such as variations in structure, dimension, type of material and manufacturing process, may be implemented by one skilled in the art in view of this disclosure.