Integrated circuits and methods for forming the same

An integrated circuit including a first memory array and a logic circuit coupled with the first memory array. All active transistors of all memory cells of the first memory array and all active transistors of the logic circuit are Fin field effect transistors (FinFETs) and have gate electrodes arranged along a direction a first longitudinal direction.

CROSS-REFERENCE TO RELATED APPLICATIONS

TECHNICAL FIELD

The present application relates generally to the field of semiconductor devices, and more particularly, to integrated circuits and methods for forming the integrated circuits.

BACKGROUND

Memory circuits have been used in various applications. Conventionally, memory circuits can include DRAM, SRAM, and non-volatile memory circuits. An SRAM circuit includes a plurality of memory cells. For a conventional 6-T static memory in which arrays of memory cells are provided, each of the memory cells consists of six transistors. The 6-T SRAM memory cell is coupled with a bit line (BL), a bit line bar (BLB), and a word line (WL). Four of the six transistors form two cross-coupled inverters for storing a datum representing “0” or “1”. The remaining two transistors serve as access transistors to control the access of the datum stored within the memory cell.

SUMMARY

In one embodiment, an integrated circuit including a first memory array and a logic circuit coupled with the first memory array. All active transistors of all memory cells of the first memory array and all active transistors of the logic circuit are Fin field effect transistors (FinFETs) and have gate electrodes arranged along a first longitudinal direction.

In another embodiment, a method for forming an integrated circuit includes forming a plurality of first active areas for all active transistors of a first memory array over a substrate and a plurality of second active areas for all active transistors of a logic circuit over the substrate. A plurality of first gate electrodes for the all active transistors of the first memory array and a plurality of second gate electrodes for the all active transistors of the logic circuit are formed. The first gate electrodes are arranged along a direction perpendicular to the first active area and the second gate electrodes are arranged along a direction perpendicular to the second active areas and parallel with the first gate electrodes.

These and other embodiments, as well as its features are described in more detail in conjunction with the text below and attached figures.

DETAILED DESCRIPTION

A conventional SRAM circuit has a memory array and at least one control logic circuit. Each of the memory array and the control logic circuit has a plurality of transistors. The transistors have active areas and gate electrodes. The active areas are formed within a substrate and generally referred to as planar active areas. Conventionally, routing directions of the gate electrodes and the active areas of the transistors of the control logic circuit are usually along two directions perpendicular to each other. To form source/drain (S/D) regions of the transistors in the active areas of the control logic circuit, four ion implantation processes are used. Each of the ion implantation processes is performed while the substrate carrying the conventional SRAM circuit is processed at 0°, 90°, 180°, and 270° positions. The four ion implantation processes increase the manufacturing cost of the integrated circuit.

From the foregoing, memory circuits and methods for forming the memory circuits are desired.

FIG. 1is a schematic drawing illustrating an exemplary integrated circuit including at least one memory array. InFIG. 1, an integrated circuit100can include at least one memory array, e.g., a memory array101and a logic circuit105. The logic circuit105can be coupled with the memory array101. All active transistors of all memory cells of the memory array101and all active transistors of the logic circuit105can have gate electrodes arranged along the same longitudinal direction. In embodiments, word lines of all active transistors of the memory array101and word lines of all active transistors of the logic circuit105are arranged along the same longitudinal direction.

The memory array101can include a plurality of word lines WLs and a plurality of bit lines BLs and BLBs. In some embodiments, the memory array101can be a static random access memory (SRAM) array, an embedded SRAM array, dynamic random access memory (DRAM) array, an embedded DRAM array, a non-volatile memory array, e.g., FLASH, EPROM, E2PROME, a field-programmable gate array, a logic circuit array, and/or other memory array.

For embodiments using a 6-T SRAM memory cell, the memory array101can include a plurality of memory cells, e.g., a memory cell101a,repetitively disposed in the memory array101. The memory cell101acan be coupled with a bit line BL, a bit line bar BLB, and a word line WL. It is noted that though only one memory cell101ais depicted, other memory cells (not shown) can be coupled with their corresponding word lines WLs and bit lines BLs of the memory array. A portion of the memory array101may have 8, 16, 32, 64, 128, or more columns that can be arranged in word widths. In embodiments, the word lines can be laid out substantially orthogonally to the bit lines. In other embodiments, other arrangements of the word lines and bit lines can be provided. It is noted that the description of the memory cell101ais merely exemplary. In other embodiments, the memory cell101acan be an 8-T SRAM memory cell, 1-T SRAM memory cell, or any type memory cell.

Referring again toFIG. 1, the memory cell101acan include active transistors110,115,120,125,130, and135. The active transistors110,115,120,125,130, and135can be operable for a memory cell operation, e.g., read or write. In one embodiment, the active transistors110,120and115,125can be operable as two cross-latch inverters forming a flip-flop for storing the datum in the memory cell101a.The active transistors130and135can be operable as two pass transistors, access transistors, or pass gates. In some embodiments, the active transistors110and115can be referred to as pull-up transistors and the active transistors120and125can be referred to as pull-down transistors. The pull-up transistors can be configured to pull a voltage level towards a power source voltage level, e.g., VDD. The pull-down transistors can be configured to pull a voltage level towards another power source voltage level, e.g., VSS.

In embodiments, a drain of the active transistor110can be electrically coupled with a source of the active transistor130, a drain of the active transistor120, and a gate of the active transistor115. A drain of the active transistor115can be electrically coupled with a source of the active transistor135, a drain of the active transistor125, and a gate of the active transistor110. The gate of the active transistor110can be coupled with the gate of the active transistor120. The gate of the active transistor115can be coupled with the gate of the active transistor125.

Drains of the active transistors130and135can be electrically coupled with the bit line BL and bit line bar BLB, respectively. The gates of the active transistors130and135can be electrically coupled with the word line WL. The bit lines BL, BLB and the word line WL may extend to other memory cells of the memory array. It is noted that the number, type, and disposition of the active transistors110,115,120,125,130, and135are merely exemplary. One of skill in the art is able to modify the number, type, and disposition of the active transistors to achieve a desired memory array.

FIG. 2Ais a schematic drawing illustrating a top view including active areas, gate electrodes, and contacts of an exemplary memory cell. InFIG. 2A, the memory cell101acan have gate electrodes210a-210darranged along a first longitudinal direction. The memory cell101acan have active regions215a-215darranged along a second longitudinal direction. The second longitudinal direction is substantially perpendicular to the first longitudinal direction. As noted, the memory array101can include a plurality of memory cells. Each of the memory cells can have a structure similar to that of the memory cell101adisposed in the memory array101. From the foregoing, the gate electrodes of all active transistors of all memory cells of the memory array101can be aligned in the same longitudinal direction.

FIG. 2Bis a schematic drawing lustrating a top view including active areas, gate electrodes, and contacts of a portion of an exemplary logic circuit. A portion of the logic circuit105can include a plurality of active transistors, e.g., active transistors220a-220f.The active transistors220a-220fare operable for a memory cell operation, e.g., read or write. The active transistors220a-220fcan have a plurality of gate electrodes, e.g., gate electrodes225a-225c,and active areas, e.g., active areas230a-230b.The longitudinal direction of the gate electrodes225a-225ccan be the same as that of the gate electrodes210a-210dof the memory cell101a.The longitudinal direction of the gate electrodes225a-225ccan be substantially perpendicular to that of the active areas230a-230b.In embodiments, the logic circuit105can include a control logic, an input/output (IO) interface, an address register, an input buffer, a sense amplifier, an output buffer, or any combinations thereof.

As noted, all gate electrodes of all active transistors of all memory cells of the memory array101and the gate electrodes of all active transistors of the logic circuit105can be disposed along the same longitudinal direction, e.g., horizontal direction. All active areas for all active transistors of the memory array101and all active areas for all active transistors of the logic circuit105can be disposed along the same longitudinal direction, e.g., vertical direction. As such, all source/drain (S/D) regions (not labeled) for the active transistors of the memory array101and the logic circuit105can be merely subjected to two ion implantation processes along the direction substantially parallel with the longitudinal direction of the gate electrodes.

In embodiment, the gate electrodes of all active transistors of all memory cells of the memory array101can have the same pitch. For example, the pitch defined between the edges of the gate electrodes210cand210dcan be the same as that between the edge of the gate electrode210dand the edge of another gate electrode (not shown) neighboring and below the gate electrode210d.

In embodiment, each of the active transistors110,115,120,125,130,135, and220a-220fcan be a Fin field effect transistor (FinFET).FIG. 3is a cross-sectional view of exemplary FinFETs. InFIG. 3, FinFETs300a-300ccan be disposed over a substrate301. The substrate301can include a plurality of active areas305a-305c.In embodiments, the active areas305a-305ccan be referred to as non-planar active areas over a surface301aof the substrate301.

In embodiments, the substrate301may include an elementary semiconductor material, a compound semiconductor material, an alloy semiconductor material, or any other suitable material or combinations thereof. The elementary semiconductor material can include silicon or germanium in crystal, polycrystalline, or an amorphous structure. The compound semiconductor material can include silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide. The alloy semiconductor material can include SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP. In one embodiment, the alloy semiconductor substrate may have a gradient SiGe feature in which the Si and Ge composition change from one ratio at one location to another ratio at another location. In another embodiment, the alloy SiGe is formed over a silicon substrate. In another embodiment, a SiGe substrate is strained. Furthermore, the semiconductor substrate may be a semiconductor on insulator, such as a silicon on insulator (SOI), or a thin film transistor (TFT). In some examples, the semiconductor substrate may include a doped epitaxial layer or a buried layer. In other examples, the compound semiconductor substrate may have a multilayer structure, or the substrate may include a multilayer compound semiconductor structure.

Referring again toFIG. 3, an isolation material310can be disposed over the surface301aof the substrate301. The isolation material310can be disposed around the active areas305a-305cof the FinFETs300a-300c.The isolation material310can electrically isolate two neighboring active areas305a,305bor305b,305c.The isolation material310can include a shallow trench isolation (STI) structure, a local oxidation of silicon (LOCOS) structure, other isolation structure, or any combination thereof.

In embodiments, a gate dielectric (not shown) can be formed over the active areas305a-305c.The gate dielectric can include a single layer or a multi-layer structure. In embodiments having a multi-layer structure, the gate dielectric can include an interfacial dielectric layer and a high-k dielectric layer. The interfacial dielectric layer may be formed by any suitable process and any suitable thickness. For example, the interfacial dielectric layer may include a material such as oxide, nitride, oxynitride, other gate dielectric materials, and/or combinations thereof. The interfacial dielectric layer can b formed by thermal processes, CVD processes, ALD processes, epitaxial processes, and/or combinations thereof.

Referring again toFIG. 3, a gate electrode320can be disposed over the active areas305a-305c.In embodiments, the gate electrode320can include one or more materials including polysilicon, Ti, TiN, TaN, Ta, TaC, TaSiN, W, WN, MoN, MoON, RuO2, and/or other suitable materials. The gate electrode320may include one or more layers formed by physical vapor deposition (PVD), CVD, ALD, plating, and/or other suitable processes. In embodiments, the gate electrode320can include a work function metal layer such that it provides an N-metal work function or P-metal work function of a metal gate. P-type work function materials include compositions such as ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, and/or other suitable materials. N-type metal materials include compositions such as hafnium, zirconium, titanium, tantalum, aluminum, metal carbides (e.g., hafnium carbide, zirconium carbide, titanium carbide, aluminum carbide), aluminides, and/or other suitable materials.

In embodiments, the memory array101(shown inFIG. 1) can include at least one dummy memory cell (not shown). The dummy memory cell can be disposed adjacent at least one of the all active transistors of the memory array101. In embodiments, the dummy memory cell can be disposed at the peripheral areas and/or edges of the memory array101. The dummy memory cell can be configured for desirably reducing the process loading difference at the center and edges of the memory array101. The dummy memory cell is free from providing any operation, e.g., read or write, of the memory cell101a.In embodiments, the routing direction of the gate electrode of the dummy memory cell can be parallel with the longitudinal direction of the gate electrodes210a-210dor the active areas215a-215d.

FIG. 4is a schematic drawing illustrating another exemplary integrated circuit. InFIG. 4, an integrated circuit400can include multiple memory arrays, e.g., memory arrays401and451, electrically coupled with a control logic405. Items ofFIG. 4that are the same items inFIG. 1are indicated by the same reference numerals, increased by300. In embodiments, the memory array451can have the same or different memory capacity of the memory array401. The memory cell451acan have the same or different structure of the memory cell401a.The memory cell451acan include active transistors460,465,470,475,480, and485. The active transistors460,465,470,475,480, and485can be similar to the active transistors110,115,120,125,130, and135, respectively.

For embodiments using a 6-T SRAM memory cell, the memory array451can include a plurality of word lines WLs and a plurality of bit lines BLs and BLBs. The memory array451can include at least one memory cell451a.The memory cell451acan be coupled with a bit line BL, a bit line bar BLB, and a word line WL. It is noted that though only one memory cell451ais depicted, other memory cells (not shown) can be coupled with the plurality of word lines WLs and bit lines BLs of the memory array. A portion of the memory array451may have 8, 16, 32, 64, 128 or more columns that can be arranged in word widths. In embodiments, the word lines can be laid out substantially orthogonally to the bit lines. In other embodiments, other arrangements of the word lines and bit lines can be provided.

FIG. 5is a schematic drawing illustrating a top view including active areas, gate electrodes, and contacts of another exemplary memory cell. InFIG. 5, the memory cell451acan have gate electrodes510a-510darranged along a first longitudinal direction. The memory cell451acan have active regions515a-515farranged along a second longitudinal direction. The second longitudinal direction is substantially perpendicular to the first longitudinal direction. As noted, the memory array451can include a plurality of memory cells. Each of the memory cells can have a structure similar to that of the memory cell451aand be disposed in the memory array451. From the foregoing, the gate electrodes of all active transistors of all memory cells of the memory array451can be arranged along the same longitudinal direction. In embodiments, the gate electrodes of all active transistors of the memory array401, the logic circuit405, and the memory array451can arranged along the same longitudinal direction, e.g., a horizontal direction. The active areas for all active transistors of the memory array401, the logic circuit405, and the memory array451can be arranged along the same longitudinal direction, e.g., vertical direction.

FIG. 6is a flowchart illustrating an exemplary method for forming an integrated circuit. InFIG. 6, a method600of forming an integrated circuit can include Step610for forming a plurality of first active areas for all active transistors of a first memory array over a substrate and a plurality of second active areas for all active transistors of a logic circuit over the substrate. For example, Step610can form the active areas215a-215dand230a-230b(shown inFIGS. 2A-2B) over a substrate. In embodiments, the active areas215a-215dand230a-230bcan be defined by recessing portions of the substrate. In other embodiments, the active areas215a-215dand230a-230bcan be formed by an epitaxial process, CVD process, other methods that are capable of forming the active areas215a-215dand230a-230b,and/or combinations thereof.

Referring toFIG. 6, Step620can form a plurality of first gate electrodes for all active transistors of the first memory array and a plurality of second gate electrodes for all active transistors of the logic circuit. The first gate electrodes are perpendicular to the first active area, and the second gate electrodes are perpendicular to the second active areas and parallel with the first gate electrodes. For example, Step620can form the gate electrodes210a-210dand225a-225c(shown inFIGS. 2A-2B) over the active areas215a-215dand230a-230b.The gate electrodes210a-210dand225a-225ccan be formed by forming a deposition layer by physical vapor deposition (PVD), CVD, ALD, plating, and/or other suitable processes. The deposition layer can be defined by, e.g., photolithographic process and/or etch process for forming the gate electrodes210a-210dand225a-225c.

Referring toFIG. 6, Step630can form source/drain (S/D) regions of all active transistors of the first memory array and all active transistors of the logic circuit. For example, S/D regions (not labeled) of the active transistors110,115,120,125,130, and135of the memory cell101aand the active transistors220a-220fof the logic circuit105.

In embodiments, Step630can include only two ion implantation processes for implanting ions in the source/drain regions of the active transistors110,115,120,125,130,135, and220a-220f.The direction of the ion implantation processes can be substantially perpendicular to the longitudinal direction of the active areas of the215a-215dand230a-230b.Each of the two ion implantation processes can be performed on each longitudinal side of the active areas of the215a-215dand230a-230b.Since only two ion implantation processes are performed for injecting ions, the cost of manufacturing the integrated circuit can be desirably reduced.

In embodiments, the S/D regions can be N-type S/D regions or p-type S/D regions. The n-type S/D regions can have dopants such as Arsenic (As), Phosphorus (P), other group V element, or the combinations thereof. The p-type S/D regions247aand247bcan have dopants such as Boron (B) or other group III element. In embodiments, a thermal process and/or rapid thermal process (RTP) is performed after the ion implantation processes.

In embodiments, the method600can include forming at least one dummy memory cell adjacent to at least one of the active transistors of the memory array101. The at least one dummy memory cell has a gate electrode that is parallel with the active areas215a-215dor the gate electrodes210a-210d(shown inFIG. 2A). For example, the gate electrode of the dummy memory cell can be formed by the same process forming the gate electrodes210a-210d.

In embodiments, the method600can include forming another memory array, e.g., the memory array451, coupled with the logic circuit405. The method600can include forming a plurality of active areas515a-515ffor the active transistors460,465,470,475,480, and485of the memory array451. The method600can further include forming a plurality of the gate electrodes510a-510dfor the all active transistors of the memory array451. The gate electrodes510a-510dare perpendicular to the active area215a-215dand parallel with the gate electrodes210a-210d.The gate electrodes510a-510dof the active transistors460,465,470,475,480, and485can be formed by the same process forming the gate electrodes210a-210d.The active areas515a-515fof the active transistors460,465,470,475,480, and485can be formed by the same process forming the active areas215a-215d.

FIG. 7is a schematic drawing illustrating a system including an exemplary integrated circuit disposed over a substrate board. InFIG. 7, a system700can include an integrated circuit702disposed over a substrate board701. The substrate board701can include a printed circuit board (PCB), a printed wiring board and/or other carrier that is capable of carrying an integrated circuit. The integrated circuit702can be similar to the integrated circuit100described above in conjunction withFIG. 1. The integrated circuit702can be electrically coupled with the substrate board701. In embodiments, the integrated circuit702can be electrically coupled with the substrate board701through bumps705. In other embodiments, the integrated circuit702can be electrically coupled with the substrate board501through wire bonding. The system700can be part of an electronic system such as computers, wireless communication devices, computer-related peripherals, entertainment devices, or the like.

In embodiments, the system700including the integrated circuit702can provide an entire system in one IC, so-called system on a chip (SOC) or system on integrated circuit (SOIC) devices. These SOC devices may provide, for example, all of the circuitry needed to implement a cell phone, personal data assistant (PDA), digital VCR, digital camcorder, digital camera, MP3 player, or the like in a single integrated circuit.