A multi-chip structure that implements a configurable Network-on-Chip (NoC) for communication between chips is described herein. In an example, an apparatus includes a first chip comprising a first processing system and a first configurable NoC connected to the first processing system, and includes a second chip comprising a second processing system and a second configurable NoC connected to the second processing system. The first and second configurable NoCs are connected together via an external connector. The first and second processing systems are operable to obtain first and second information from off of the first and second chip and configure the first and second configurable NoCs based on the first and second information, respectively. The first and second processing systems are communicatively coupled with each other via the first and second configurable NoCs when the first and second configurable NoCs are configured based on the first and second information, respectively.

TECHNICAL FIELD

Examples of the present disclosure generally relate to multi-chip structures and, in particular, to multi-chip structures that implement a configurable Network-on-Chip (NoC) for communication between chips.

BACKGROUND

Advances in integrated circuit technology have made it possible to embed an entire system, such as including a processor core, a memory controller, and a bus, in a single semiconductor chip. This type of chip is commonly referred to as a system-on-chip (SoC). Other SoCs can have different components embedded therein for different applications. The SoC provides many advantages over traditional processor-based designs. It is an attractive alternative to multi-chip designs because the integration of components into a single device increases overall speed while decreasing size. The SoC is also an attractive alternative to fully customized chips, such as an application specific integrated circuit (ASIC), because ASIC designs tend to have a significantly longer development time and larger development costs. A configurable SoC (CSoC), which includes programmable logic, has been developed to implement a programmable semiconductor chip that can obtain benefits of both programmable logic and SoC.

SUMMARY

A multi-chip structure that implements a configurable Network-on-Chip (NoC) for communication between chips is described herein. A minimal configuration for the configurable NoC of each chip can be enabled to establish communications between the chips to permit communications for further configuration.

An example of the present disclosure is an apparatus. The apparatus includes a first chip comprising a first processing system and a first configurable Network-on-Chip (NoC) connected to the first processing system, and includes a second chip comprising a second processing system and a second configurable NoC connected to the second processing system. The first configurable NoC is connected to the second configurable NoC via an external connector. The first processing system is operable to obtain first information from off of the first chip and configure the first configurable NoC based on the first information. The second processing system is operable to obtain second information from off of the second chip and configure the second configurable NoC based on the second information. The first processing system and the second processing system are communicatively coupled with each other via the first configurable NoC and the second configurable NoC when the first configurable NoC and the second configurable NoC are configured based on the first information and the second information, respectively.

Another example of the present disclosure is a method for operating multiple integrated circuits. Locally at each chip of multiple chips by a controller of the respective chip, a configurable Network-on-Chip (NoC) of the respective chip is configured based on initial configuration data. The configurable NoCs of the multiple chips are connected via external connectors external to the multiple chips. System configuration data is communicated between the controllers of the multiple chips via the configurable NoCs of the multiple chips configured based on the initial configuration data. Locally at each chip by the controller of the respective chip, the configurable NoC of the respective chip is configured based on the system configuration data.

Another example of the present disclosure is a method for operating multiple integrated circuits. A first processing system on a first chip is communicatively connected to a second processing system on a second chip via a first configurable Network-on-Chip (NoC) on the first chip and a second configurable NoC on the second chip. A first transaction request is transmitted from the first processing system through the first configurable NoC and the second configurable NoC to the second processing system. A second transaction request corresponding to the first transaction request is transmitted from the second processing system to a configurable component on the second chip via a peripheral interconnect on the second chip. The second processing system is operable to configure the second configurable NoC via the peripheral interconnect.

DETAILED DESCRIPTION

Examples described herein provide for a multi-chip structure that implements a configurable Network-on-Chip (NoC) for communication between chips. In some examples, each chip of the multi-chip structure reads data from off-chip that indicates how a configurable NoC of the respective chip is to be configured for a minimal configuration to establish communications between the chips. Each chip configures its NoC according to the minimal configuration, and thereafter, the chips may communicate with others of the chips through the NoCs. The communication between the chips may include communicating system-level configuration data, which may be used to re-configure the NoCs, for example. The NoCs may be configured using a peripheral interconnect to write data to register blocks of switches of the respective NoC. Further, once the NoCs are configured to permit communication between chips, a master on one chip can communicate with slave endpoint circuits (e.g., the register blocks of the switches) on another chip via the interconnected NoCs and the peripheral interconnect of the chip on which the slave endpoint circuit is disposed.

FIG. 1is a block diagram of a multi-chip structure, such as a two-and-a-half-dimensional integrated circuit (2.5DIC) structure, according to an example. The 2.5DIC structure includes a first chip51, a second chip52, a third chip53, and a memory chip62attached to an interposer70or another substrate. In other examples, the 2.5DIC structure may have fewer or more chips, and the memory chip62may be outside of, but communicatively coupled to, the 2.5DIC structure. Each of the first chip51, second chip52, and third chip53can include is an integrated circuit (IC), such as a system-on-chip (SoC) as described below. The memory chip62can comprise any form of memory for storing data, such as a configuration file. The first chip51, second chip52, third chip53, and memory chip62are attached to the interposer70by electrical connectors72, such as microbumps, controlled collapse chip connection (C4) bumps, or the like. Electrical connectors74on a side of the interposer70opposite from the chips51,52,53,62for attaching the 2.5DIC structure to another substrate, such as a package substrate, for example. The electrical connectors74may be C4 bumps, ball grid array (BGA) balls, or the like.

The interposer70includes electrical interconnects that electrically connect various ones of the chips51,52,53,62. The electrical interconnects can include one or more metallization layers or redistribution layers on the side of the interposer70on which the chips51,52,53,62are attached, one or more through substrate vias (TSVs) through the bulk substrate (e.g., silicon substrate) of the interposer70, and/or one or more metallization layers or redistribution layers on the side of the interposer70opposing the side on which the chips51,52,53,62are attached. Hence, various signals, packets, etc. can be communicated between various ones of the chips51,52,53,62.

In other examples, more or fewer chips may be included, and the chips may be in other configurations. For example, more or fewer chips that include a SoC may be implemented, such as two, four, or more chips, and more or fewer memory chips may be included. In some examples, the multi-chip structure can include various stacked chips, such as in a three-dimensional IC (3DIC) structure. For example, two or more memory chips may be stacked on each other with the bottom memory chip being attached to the interposer70. Other multi-chip structures may be implemented in other examples, such as without an interposer. Various modifications may be made that would be readily apparent to a person having ordinary skill in the art.

FIG. 2is a block diagram depicting a multi-chip structure with multiple chips each having a SoC according to an example. The multi-chip structure includes a first SoC101(e.g., on the first chip51ofFIG. 1), a second SoC102(e.g., on the second chip52), and a third SoC103(e.g., on the third chip53). Each SoC101,102,103is an IC comprising a processing system104, a network-on-chip (NoC)106, a configuration interconnect108, and one or more programmable logic regions110. Each SoC101,102,103can be coupled to external circuits, and as illustrated, the first SoC101is coupled to nonvolatile memory (NVM)112(e.g., on the memory chip62inFIG. 1). The NVM112can store data that can be loaded to the SoCs101,102,103for configuring the SoCs101,102,103, such as configuring the NoC106and the programmable logic region(s)110. As illustrated inFIGS. 1 and 2, the NVM112is on the memory chip62attached to the interposer70; however, in other examples, memory, such as flash memory, can be external to the multi-chip structure and communicatively coupled to the SoC101, such as via an serial peripheral interface (SPI). For example, the memory may be attached to a same package substrate to which the multi-chip structure is attached, and may communicate with the SoC101via the package substrate. In general, the processing system104of each SoC101,102,103is connected to the programmable logic region(s)110through the NoC106and through the configuration interconnect108.

The processing system104of each SoC101,102,103can include one or more processor cores. For example, the processing system104can include a number of ARM-based embedded processor cores. The programmable logic region(s)110of each SoC101,102,103can include any number of configurable logic blocks (CLBs), which may be programmed or configured using the processing system104through the configuration interconnect108of the respective SoC101,102,103. For example, the configuration interconnect108can enable, for example, frame-based programming of the fabric of the programmable logic region(s)110by a processor core of the processing system104(such as a platform management controller (PMC) described further below).

The NoC106includes end-to-end Quality-of-Service (QoS) features for controlling data-flows therein. In examples, the NoC106first separates data-flows into designated traffic classes. Data-flows in the same traffic class can either share or have independent virtual or physical transmission paths. The QoS scheme applies two levels of priority across traffic classes. Within and across traffic classes, the NoC106applies a weighted arbitration scheme to shape the traffic flows and provide bandwidth and latency that meets the user requirements. Examples of the NoC106are discussed further below. The NoC106is independent from the configuration interconnect108, for example. The processing system104, programmable logic regions110, and/or other components of each SoC101,102,103can be selectively communicatively connected together via the NoC106of the respective SoC101,102,103. Further, the NoCs106of the SoCs101,102,103are communicatively connected, such as through external electrical connections on an interposer (e.g., interposer70).

FIG. 3is a block diagram depicting the NoC106of a SoC according to an example. The NoC106includes NoC master units (NMUs)202, NoC slave units (NSUs)204, a network214, NoC peripheral interconnect (NPI)210, and register blocks212. Each NMU202is an ingress circuit that connects a master circuit to the NoC106. Each NSU204is an egress circuit that connects the NoC106to a slave endpoint circuit. The NMUs202are connected to the NSUs204through the network214. In an example, the network214includes NoC packet switches206and routing208between the NoC packet switches206. Each NoC packet switch206performs switching of NoC packets. The NoC packet switches206are connected to each other and to the NMUs202and NSUs204through the routing208to implement a plurality of physical channels. The NoC packet switches206also support multiple virtual channels per physical channel. The NPI210includes circuitry to program the NMUs202, NSUs204, and NoC packet switches206. For example, the NMUs202, NSUs204, and NoC packet switches206can include register blocks212that determine functionality thereof. The NPI210includes a peripheral interconnect coupled to the register blocks212for programming thereof to set functionality. The register blocks212in the NoC106support interrupts, QoS, error handling and reporting, transaction control, power management, and address mapping control. Configuration data for the NoC106can be stored in the NVM112and provided to the NPI210for programming the NoC106and/or other slave endpoint circuits.

FIG. 4is a block diagram depicting connections between endpoint circuits in a SoC through the NoC106according to an example. In the example, endpoint circuits302are connected to endpoint circuits304through the NoC106. The endpoint circuits302are master circuits, which are coupled to NMUs202of the NoC106. The endpoint circuits304are slave circuits coupled to the NSUs204of the NoC106. Each endpoint circuit302and304can be a circuit in the processing system104, a circuit in a programmable logic region110, or a circuit in another subsystem. Each endpoint circuit in the programmable logic region110can be a dedicated circuit (e.g., a hardened circuit) or a circuit configured in programmable logic.

The network214includes a plurality of physical channels306. The physical channels306are implemented by programming the NoC106. Each physical channel306includes one or more NoC packet switches206and associated routing208. An NMU202connects with an NSU204through at least one physical channel306. A physical channel306can also have one or more virtual channels308.

FIG. 5is a block diagram depicting a NoC packet switch206according to an example. As illustrated, the NoC packet switch206has four bi-directional connections or ports (each labeled a “side” for convenience). In other examples, a NoC packet switch206can have more or fewer connections or ports. The NoC packet switch206has a first side Side 0, a second side Side 1, a third side Side 2, and a fourth side Side 3. The NoC packet switch206includes a register block212for configuring the functionality of the NoC packet switch206. The register block212includes addressable registers, for example. The register block212includes a configuration register and a routing table. The configuration register can set a configuration mode of the NoC packet switch206, as described inFIG. 6, for example, and the routing table can identify how packets received at the NoC packet switch206are to be routed based on the configuration mode.

FIG. 6illustrates example configurations of a NoC packet switch206according to an example.FIG. 6shows a first configuration602, a second configuration604, and a third configuration606. A NoC packet switch206can have more, fewer, or different configurations in other examples. The configurations can be implemented using the configuration register and routing table in the NoC packet switch206. In a default configuration, the NoC packet switch206acts as a pass-through. A packet entering on the first side Side 0 exits on the third side Side 2, and vice versa. Further, a packet entering on the second side Side 1 exits on the fourth side Side 3, and vice versa. In the first configuration602, a packet entering on the first side Side 0 exits on the second side Side 1, and a packet entering on the second side Side 1 exits on the first side Side 0. In the second configuration604, a packet entering on one of the first side Side 0, the third side Side 2, or the fourth side Side 3 exits on another one of the first side Side 0, the third side Side 2, or the fourth side Side 3 based on a destination identification of the packet being routed. In the third configuration606, a packet entering on one of the first side Side 0, the second side Side 1, or the third side Side 2 exits on another one of the first side Side 0, the second side Side 1, or the third side Side 2 based on a destination identification of the packet being routed. The NoC packet switch206illustrated inFIG. 6has connectivity using 3 sides, and in other examples, connectivity can use fewer (e.g., 2) connections or more (e.g., 4) connections depending on where connectivity is desired to be established. Additional details of example configurations will be described in the context of further examples.

FIG. 7is a block diagram depicting connections to a register block212of a NoC packet switch206through the NPI210in a SoC101,102,103according to an example. To connect to a register block212, the NPI210includes a root node404, interconnected NPI switches408, and a protocol block410. The root node404resides on a platform management controller (PMC)402, which as show in subsequent examples, further resides in the processing system104of the SoC101,102,103. The PMC402includes a local boot read only memory (ROM)403for storing boot sequence instructions, for example.

Generally, the root node404can packetize a transaction request, such as a write or read request, into a format implemented by the NPI210and can transmit a memory-mapped transaction request to interconnected NPI switches408. The transaction request can be routed through the interconnected NPI switches408to a protocol block410connected to the register block212to which the transaction request is directed. The protocol block410can then translate the memory-mapped transaction request into a format implemented by the register block212and transmit the translated request to the register block212for processing. The register block212can further transmit a response to the transaction request through the protocol block410and the interconnected NPI switches408to the root node404, which then responds to the master circuit that issued the transaction request.

The root node404can translate a transaction request between a protocol used by the one or more master circuits, such as the PMC402, and a protocol used by the NPI210. For example, the master circuits can implement the Advanced eXtensible Interface fourth generation (AXI4) protocol, and the NPI210can implement an NPI Protocol. The protocol blocks410can also translate the transaction request from the protocol implemented on the NPI210to a protocol implemented by the register blocks212of the NoC packet switches206. In some examples, the protocol blocks410can translate between NPI Protocol and the Advanced Microcontroller Bus Architecture (AMBA) 3 Advanced Peripheral Bus (APB3) protocol.

As described in further detail subsequently, within and separately for each SoC101,102,103, the PMC402may execute instructions stored in the boot ROM403to issue transaction requests (e.g., write requests) through the NPI210(e.g., the root node404, interconnected NPI switches408, and protocol blocks410) to register blocks212of NoC packet switches206to initially program the NoC packet switches206to initially configure the NoC106for that respective SoC101,102,103. The PMC402may subsequently reprogram the NoC packet switches206.

The PMC402is further connected to the configuration interconnect108, which is in turn connected to the programmable logic regions110. The PMC402is configured to program the fabric of the programmable logic regions110using, for example, a frame-based programming mechanism through the configuration interconnect108. The configuration interconnect108is a delivery mechanism for programming programmable units on the respective SoC that is independent of the delivery mechanism of the NPI210for programming other programmable units (e.g., slave endpoint circuits like the register blocks212of the NoC packet switches206) on the respective SoC101,102,103.

FIG. 8is a block diagram depicting a multi-chip structure with interconnected NoCs106according to an example.FIG. 8illustrates some aspects of the multi-chip structure ofFIG. 2in more detail while omitting other aspects so as not to obscure aspects described here. Generally, each SoC101,102,103includes a processing system (PS)104, programmable logic regions (PL)110, and components that form a NoC106. The processing system104includes a PMC402, which further includes boot ROM403and a root node404of an NPI210. The processing system104and programmable logic regions110include various ones of NMUs202(boxes labeled with an “M” inFIG. 8) and NSUs204(boxes labeled with an “S”). The NoC106includes routing208and NoC packet switches206(boxes labeled with an “x”) at various intersections of routing208. The NMUs202are connected to the routing208, and the NSUs204are also connected to the routing208. The NoC packet switches206are capable of being configured to connect and direct communications between various ones of the NMUs202and the NSUs204. The NPI210of the NoC106is generally illustrated as dashed lines emanating from the root node404. More specifically, the NPI210includes interconnected NPI switches408and protocol blocks410connected to register blocks212of the NoC packet switches206, as described with respect toFIG. 7previously.

Routing208of each NoC106is connected to external connectors802to interconnect the NoCs106of the SoCs101,102,103. The external connectors802can be or include, for example, bumps attaching the respective chips to an interposer and/or metallization layers or redistribution layers on the interposer, such as described with respect toFIG. 1. Routing208of the NoC106of SoC101is connected to routing208of the NoC106of SoC102via external connectors802, and routing of the NoC106of SoC102is connected to routing208of the NoC106of SoC103via external connectors802.

Generally, each SoC101,102,103undergoes a multi-stage boot sequence. In a first stage, each SoC101,102,103configures, for example, a minimal number of NoC packet switches206to establish communication between the SoCs101,102,103through the NoCs106. In some examples described herein, communications between the SoCs101,102,103only occurs through the interconnected NoCs106and external connectors802, as shown inFIG. 8. With communications between the SoCs101,102,103established through the NoCs106, system configuration data for a system-level configuration can be communicated between the SoCs101,102,103on the interconnected NoCs106for configuring programmable components of the SoCs101,102,103, in a second stage of the boot sequence. After the system-level configuration is established, fabric configuration data for programming the fabric of programmable logic regions110can be communicated between the SoCs101,102,103on the interconnected NoCs106.

In the first stage of the boot sequence, the PMC402of each SoC101,102,103executes boot instructions stored on the boot ROM403. The execution of these instructions cause the PMC402to read data from off-chip of the respective SoC101,102,103. The data can be stored on another chip attached to the interposer to which the chip of the SoC101,102,103is attached and/or input by a user implementing the SoC101,102,103. In some examples, the data is stored on e-fuses on a memory device attached to the interposer. Various hardened input/output (IO) interfaces may be implemented to read the data from off-chip, which is not specifically illustrated inFIG. 8. The information that is read identifies which NoC packet switches206on the respective SoC101,102,103are to be configured in the first stage, identifies the configuration of those NoC packet switches206, and identifies where the chip of the respective SoC101,102,103is in relation to the other chips of the other SoCs101,102,103(e.g., wherein the chip is in the stack of chips). By being configured to read this information from off-chip, each chip of the SoCs101,102,103can be manufactured by the same processes, e.g., the chips of the SoCs101,102,103can be the same, and the arrangement of the chips on, e.g., the interposer can determine what information is read to configure the SoCs101,102,103.

Execution of the instructions from the boot ROM403further causes each PMC402, based on the information that has been read, to transmit memory-mapped transaction requests through the root node404and NPI210to the register blocks212of the NoC packet switches206identified by the read information to write information to those register blocks212and thereby configure the NoC packet switches206. With the NoC packet switches206configured, communication between the PMCs402of the SoCs101,102,103can commence over the NoCs106, which can permit inter-chip communication to communicate system-level configuration data, for example. More details are described in the context of the example ofFIG. 8.

In the context ofFIG. 8, each PMC402of the SoCs101,102,103reads data from off-chip. The PMC402of the SoC101reads data that indicates that the SoC101is to be the master and first chip (e.g., identified as ‘00’) in the configuration of SoCs101,102,103, that two NoC packet switches206aand206bare to be configured, and that indicates the identification and configuration of the NoC packet switches206aand206b. For example, the identification and configuration for the data that indicates the identification and configuration of the NoC packet switches206aand206bcan include an identification (e.g., a 9-bit identification) and configuration code (e.g., 2-bit code) of the respective NoC packet switch206a,206b. The PMC402of the SoC101can determine addresses of register blocks212of the NoC packet switch206a,206bfor programming routing tables of the NoC packet switch206a,206bbased on the identification data that was read, and can determine a configuration of the NoC packet switch206a,206bbased on the configuration code. The PMC402of the SoC101then, through the root node404and NPI210of the SoC101, writes the configuration and routing tables to register blocks212of the NoC packet switches206aand206b. For example, the configuration of NoC packet switch206acan be the first configuration602ofFIG. 6, and the configuration of NoC packet switch206bcan be the second configuration604ofFIG. 6. The routing tables of the NoC packet switch206bcan direct memory-mapped packets through different sides of the NoC packet switch206bbased on an address in the respective memory-mapped packet. A chip identification can be appended to addresses of the memory-mapped packets, and the NoC packet switch206bcan direct packets based on the chip identification. For example, packets having a chip identification of ‘00’ (e.g., for the SoC101) are routed to the fourth side Side 3 of the NoC packet switch206b, and packets having a chip identification greater than ‘00’ are routed to the first side Side 0 of the NoC packet switch206b.

The PMC402of the SoC102reads data that indicates that the SoC102is to be a slave and second chip (e.g., identified as ‘01’) in the configuration of SoCs101,102,103, that two NoC packet switches206cand206dare to be configured, and that indicates the identification and configuration of the NoC packet switches206cand206d, as described above in the context of the SoC101. The PMC402of the SoC102can determine addresses of register blocks212of the NoC packet switch206c,206dfor programming routing tables of the NoC packet switch206c,206dbased on the identification data that was read, and can determine a configuration of the NoC packet switch206c,206dbased on the configuration code. The PMC402of the SoC102then, through the root node404and NPI210of the SoC102, writes the configuration and routing tables to register blocks212of the NoC packet switches206cand206d. For example, the configuration of NoC packet switch206ccan be the first configuration602ofFIG. 6, and the configuration of NoC packet switch206dcan be the second configuration604ofFIG. 6. The routing tables of the NoC packet switch206dcan direct memory-mapped packets through different sides of the NoC packet switch206dbased on an address in the respective memory-mapped packet. For example, packets having a chip identification of ‘01’ (e.g., for the SoC102) are routed to the fourth side Side 3 of the NoC packet switch206d; packets having a chip identification greater than ‘01’ are routed to the first side Side 0 of the NoC packet switch206d; and packets having a chip identification less than ‘01’ are routed to the third side Side 2 of the NoC packet switch206d.

The PMC402of the SoC103reads data that indicates that the SoC103is to be a slave and third chip (e.g., identified as ‘10’) in the configuration of SoCs101,102,103, that two NoC packet switches206eand206fare to be configured, and that indicates the identification and configuration of the NoC packet switches206eand206f, as described above in the context of the SoC101. The PMC402of the SoC103can determine addresses of register blocks212of the NoC packet switch206e,206ffor programming routing tables of the NoC packet switch206e,206fbased on the identification data that was read, and can determine a configuration of the NoC packet switch206e,206fbased on the configuration code. The PMC402of the SoC103then, through the root node404and NPI210of the SoC103, writes the configuration and routing tables to register blocks212of the NoC packet switches206eand206f. For example, the configuration of NoC packet switch206ecan be the first configuration602ofFIG. 6, and the configuration of NoC packet switch206fcan be the second configuration604ofFIG. 6. The routing tables of the NoC packet switch206fcan direct memory-mapped packets through different sides of the NoC packet switch206fbased on an address in the respective memory-mapped packet. For example, packets having a chip identification of ‘10’ (e.g., for the SoC102) are routed to the fourth side Side 3 of the NoC packet switch206f, and packets having a chip identification less than ‘10’ are routed to the third side Side 2 of the NoC packet switch206f.

With the respective SoCs101,102,103having configured the NoC packet switches206a-f, communication can be established between the SoCs101,102,103. For example, the PMC402of the SoC101can communicate with the PMC402of the SoC102via the NMU202aon the processing system104of the SoC101, the NoC packet switches206a,206b,206d,206cand corresponding routing208, and the NSU204aon the processing system104of the SoC102. Similarly, the PMC402of the SoC101can communicate with the PMC402of the SoC103via the NMU202aon the processing system104of the SoC101, the NoC packet switches206a,206b,206d,206f,206eand corresponding routing208, and the NSU204bon the processing system104of the SoC103. Each PMC402has a dedicated portion of the address map of the NoC106. With this portion of the address map, the PMCs402of the SoCs101,102,103can communicate with each other by including the chip identification (e.g., ‘00’, ‘01’, and ‘10’) in the memory-mapped packet to be communicated via the interconnected NoCs106. The NoC packet switches206a-fcan route the packets according to the chip identification, as described above. In some examples, the communication via the interconnected NoCs106is according to the Advanced eXtensible Interface fourth generation (AXI4) protocol.

With the PMCs402of the SoCs101,102,103being able to communicate between each other, system configuration data can be communicated from the PMC402of the SoC101to the PMCs of the SoCs102,103. For example, the PMC402of the SoC101can access system configuration data from memory, e.g., flash memory, that is off-chip from the SoC101. For example, the memory may be the NVM112on the memory chip62inFIGS. 1 and 2. The SoC101can implement any IO interface and other IP to enable the PMC402to access the system configuration data from the memory. For example, a memory controller may be connected to the processing system104(e.g., to the PMC402), and the memory controller can be connected through an IO interface to memory. The PMC402of the SoC101can then communicate this system configuration data to the PMCs402of the slave SoCs102,103via the interconnected NoCs106(e.g., with the configured NoC packet switches206a-f).

With the system configuration data communicated to the individual PMCs402of the SoCs101,102,103, the NoC106can be quiesced locally, and the PMCs402on each SoC101,102,103can further configure components, including the local NoC106, for system-level operations. The configuration of the NoC packet switches206a-fmay remain or may be changed by the system configuration data. The NoCs106of the SoCs101,102,103can be reconfigured, and such reconfiguration can maintain communication through interconnected NoCs106between the SoCs101,102,103. With the configuration of the NoCs106, various functionality of the NoC packet switches206can be configured, such as routing tables, QoS setting, and others.

With the system configured according to the system configuration data, the fabric configuration data can be accessed via the processing system104(e.g., PMC402) of the SoC101and communicated to the other processing systems104of the SoCs102,103. The fabric configuration data may be accessed through an interface with a user device such that the fabric configuration data is downloaded from the user device, or may be accessed from off-chip memory, for example. Appropriate10interfaces may be implemented to access the fabric configuration data. The processing system104(e.g., PMC402) of the SoC101then communicates the fabric configuration data to the other processing systems104of the SoCs102,103via the interconnected NoCs106, which are configured according to the system configuration data, for example.

With the fabric configuration data received at the various processing systems104of the SoCs101,102,103, the PMC402of the respective processing system104programs one or more programmable logic regions110via the local configuration interconnect108of the respective SoC101,102,103. The programmable logic regions110of the SoCs101,102,103can be subsequently executed, which may permit communication between different programmable logic regions110via the NoC106of the respective SoC101,102,103for local communications and/or via the interconnected NoCs of the SoCs101,102,103for communications between SoCs101,102,103.

FIG. 9is a flowchart for operating a multi-chip structure according to an example. At block902, at each chip, data is read from off-chip. The data indicates, among other things, which NoC packet switches206are to be configured on the respective chip and the configuration of those NoC packet switches206. At block904, at each chip, the NoC packet switches206indicated by the read data are configured via the NPI210of the chip and based on the read data. Configuring these NoC packet switches206establishes at least a minimal interconnection between the chips through the NoCs106. At block906, the master obtains system configuration data from off-chip, and at block908, the master communicates the system configuration data to the slaves via the interconnected NoCs106. At block910, at each chip, a system-level configuration is implemented based on the received system configuration data. At block912, the master obtains fabric configuration data from off-chip, and at block914, the fabric configuration data is communicated to slaves via the interconnected NoCs106. In block916, the fabric configuration data is implemented in the fabric of the respective SoC (e.g., in the programmable logic region(s)) based on the fabric configuration data.

With the NoCs106configured on and interconnected between the SoCs101,102,103, a master PMC402(such as the PMC402on the SoC101) can communicate with programmable slave endpoint circuits on other SoCs101,102,103via the interconnected NoCs106and the NPI210local to the SoC101,102,103of the respective programmable slave endpoint circuit. The NoCs106can be configured for such communications by the first stage boot sequence to establish minimal interconnections for communications between the SoCs101,102,103and/or by the second stage boot sequence to establish a system-level configuration. Referring back toFIG. 7, register blocks212were described as being in the NoC packet switches206for configuring the NoC packet switches206. In other examples, other programmable slave endpoint circuits can also include register blocks212for configuring those slave endpoint circuits or maintaining data generated by those slave endpoint circuits, such as performance data. Some example programmable slave endpoint circuits can include a memory controller, a clock generator, a temperature sensor, etc.

For example, assume that the processing system104of the SoC101needs to re-configure or read data from a clock generator on the SoC102. The processing system104(e.g., PMC402) of the SoC101creates a memory-mapped transaction request (e.g., an AXI4 read or write request), and transmits that memory-mapped transaction request from an NMU202(e.g., NMU202a) into the NoC106on the SoC101. The NoC packet switches206of the NoC106of the SoC101route the memory-mapped transaction request to external connectors802, which are connected to the NoC106of the SoC102. The NoC packet switches206of the NoC106of the SoC102then route the memory-mapped transaction request to an NSU204(e.g., NSU204a) of the processing system104of the SoC102. The PMC402of the processing system104of the SoC102then passes the memory-mapped transaction request to the root node404, which translates the memory-mapped transaction request to another format implemented on the NPI210of the SoC102. The root node404of the SoC102transmits the translated memory-mapped transaction request through the interconnected NPI switches408and appropriate protocol block410of the NPI210on the SoC102to the clock generator on the SoC102. The clock generator can process the transaction request and transmit a response. The response can be communicated along the same route in reverse order, e.g., through the protocol block410, interconnected NPI switches408, and root node404of the NPI210, PMC402, NSU204, and NoC106on the SoC102, and the NoC106and NMU202to the processing system104on the SoC101.

FIG. 10is a flowchart for operating a multi-chip structure according to an example. At block1002, a memory-mapped transaction request is transmitted from a master on a first chip through a NoC106on the first chip. The NoC106on the first chip is connected to a NoC106on a second chip. At block1004, the memory-mapped transaction request is received at a slave on the second chip through the NoC106on the second chip. At block1006, the memory-mapped transaction request is transmitted through an NPI210on the second chip. At block1008, the memory-mapped transaction request is received and processed at the slave endpoint circuit on the second chip. At block1010, the slave endpoint circuit on the second chip transmits a response to the memory-mapped transaction request to the master on the first chip via the NPI210on the second chip and the NoCs106on the first and second chips.

Examples described herein can achieve benefits. For example, configuration data of the SoCs can be moved off-chip from the SoCs, thereby reducing space and resources on the SoC. Memory chips may be easily and cheaply manufactured and programmed, and separate chips of the SoCs and memory chips may reduce cost and complexity of producing the systems. Further, by implementing a configurable NoC, a flexible, low-overhead communications interconnect can be implemented in the SoCs. The information read from off-chip by the chips can enable a minimal configuration for the NoCs to establish communications between the SoCs to permit communications for further configuration. Other benefits and advantages may be obtained by various examples.