Electronic component package

An electronic component package according to an embodiment of the present disclosure includes a first substrate, a sealing member, a second substrate, and connectors. The first substrate has a first top surface on which a first electronic component is mounted. The sealing member is positioned on the first top surface and configured to seal the first electronic component and a second electronic component. The second substrate has a second top surface on which the second electronic component is mounted, and is positioned within the sealing member. The connectors electrically couple the first substrate and the second substrate.

CROSS REFERENCE TO RELATED APPLICATION

The present application is a National Phase of International Application Number PCT/JP2016/083592, filed Nov. 11, 2016, which claims priority to Japanese Application Number 2015-221684, filed Nov. 11, 2015. The entire contents of Japanese Patent Application No. 2015-221684 filed on Nov. 11, 2015, are incorporated herein by reference.

TECHNICAL FIELD

The present disclosure relates to an electronic component package that includes a POP (Package On Package) in which at least two electronic component mounting substrates having electronic component mounted thereon are stacked.

BACKGROUND

To meet demand for increasingly compact electronic devices, electronic component packages known as POP (Package On Package) in which semiconductor packages are vertically stacked and integrally layered are conventionally used. PLT 1 set forth below describes a multilayer substrate as an example of a prior art electronic component packages.

This prior art electronic component packages includes a first substrate having a first electronic component mounted thereon, a second substrate having a second electronic component mounted thereon, and a frame serving as a connector for electrically coupling the first substrate and the second substrate by joining a periphery of the first substrate and a periphery of the second substrate.

CITATION LIST

Patent Literature

SUMMARY

An electronic component package according to one of embodiments of the present disclosure includes a first substrate, a sealing member, a second substrate, and a connector. The first substrate includes a first surface having a first electronic component mounted thereon. The sealing member is positioned on the first surface and configured to seal the first electronic component and a second electronic component. The second substrate includes a second surface having the second electronic component mounted thereon and is positioned within the sealing member. The connector electrically couples the first substrate and the second substrate.

DETAILED DESCRIPTION

In a conventional electronic component package in which two or more substrates each having electronic components mounted thereon are joined together by a frame around the substrates and solder bumps alone, an upper substrate is supported by a contact or a surface smaller than an area of the upper substrate. In the electronic component package according to the present disclosure, a second substrate arranged on top of a first substrate is positioned within a sealing member having a columnar shape provided on the first substrate. The electronic component package according to the present disclosure includes the sealing member that integrally supports the first substrate and the second substrate, and thus joins them more strongly than the electronic component package in which the substrates are joined together by the frame and the solder bumps alone. According to the present embodiment, positioned within the sealing member includes being inscribed within a side surface of the sealing member. Hereinafter, the electronic component package of the present disclosure will be described in detail.

FIG. 1is a cross-sectional view of an electronic component package1according to an embodiment.FIG. 2is a plan view of the electronic component package1in which a sealing member is omitted.FIG. 1is a cross-sectional diagram taken from line A-A ofFIG. 2.FIG. 3is a cross-sectional diagram taken from line B-B ofFIG. 2. The electronic component package1includes a first substrate4that has a first top surface6on which a first electronic component3is mounted, and a second substrate7that has a second top surface10on which a second electronic component5is mounted. The first top surface6is a first surface. The second top surface10is a second surface. The second substrate7is arranged substantially parallel with the first substrate4over the first top surface6of the first substrate4with a space ΔL1therebetween in a direction Z orthogonal to the first top surface6. The second substrate7is smaller than the first substrate4. In a plan view of the first substrate4and the second substrate7viewed from a position remote from the second substrate7in a direction opposite to the Z direction, an area of the second substrate7is included in an area of the first substrate4. In the plan view viewed in the direction opposite to the Z-direction, a periphery of the second substrate7may partially coincide with a periphery of the first substrate4. According to some embodiments, the first substrate4and the second substrate7each have a rectangular shape with two sides that are perpendicular to each other and extending along a first direction X and a second direction Y, respectively. The second substrate7has a length in the first direction X the same as the length of the first substrate4in the first direction X and a length in the second direction Y shorter than the length of the first substrate4in the second direction Y. Note that “parallel” used herein does not need to be strictly parallel but may allow a slight error or inclination caused during manufacturing.

The sealing member2is positioned on the first top surface6of the first substrate4. The sealing member2may extend throughout the periphery of the first top surface6. The sealing member2may be positioned on the first top surface6in its entirety. Note that “in its entirety” used herein may exclude a contact point electrically coupled to another element. The second substrate7is positioned within the sealing member2. The second substrate7is substantially parallel with the first substrate4, allowing some deviation caused by a manufacturing error etc. In the electronic component package1, the sealing member2is integrally formed in a first space12, a second space13, and a third space14. The first space12is a space between the first substrate4and the second substrate7. The second space13is a space on the second substrate7. The third space14may be a clearance yielded by portions of the second substrate7narrower than the first substrate4in a plan view. The third space14is a space above a portion of the first substrate4protruding from the second substrate7in plan view. The sealing member2seals the first electronic component3on the first substrate4and the second electronic component5on the second substrate7. The electronic component package1may be referred to as a POP (Package On Package).

The first substrate4includes a first wiring conductor forming a predetermined wiring pattern on the first top surface6. The first wiring conductor is coupled to the first electronic component3. The first electronic component3may include an active electronic component, such as an IC chip, that generates heat during operation. The second substrate7includes the second top surface10having the second electronic component5mounted thereon. The second substrate7includes a second connection conductor forming a predetermined wiring pattern on the second top surface10. The second connection conductor is coupled to the second electronic component5. The second electronic component5includes the active electronic component, such as the IC chip, that generates heat during operation. On the first top surface6and the second top surface10, in addition to the first electronic component3and the second electronic component5, various electronic components including a chip inductor, a chip capacitor, a diode, a chip resistor, etc. may be mounted. InFIGS. 1 to 3, these electronic components are indicated simply by rectangles without reference numerals. According to the present disclosure, the first wiring conductor and the second wiring conductor may be collectively referred to as a wiring conductor without distinction.

Materials for the first substrate4and the second substrate7may be respectively selected from organic insulating materials, inorganic insulating materials, and composite insulating materials obtained by binding an inorganic insulating material with a thermosetting resin such as an epoxy resin. The organic insulating materials include thermoplastic resins such as glass epoxy resin, polyimide, fluorine resin, polynorbornene, and benzocyclobutene. The inorganic insulating materials include aluminum sintered compact oxide, aluminum sintered compact nitride, silicon carbide sintered compact, a silicon nitride sintered compact, a mullite sintered compact, and glass ceramics.

In particular, the first electronic component3and the second electronic component5described above may include, on their rear surfaces, a signal terminal, a power terminal, and a ground terminal. Each of the terminals is electrically coupled to surface-mounted electrode pads constituting portions of the first wiring conductor arranged on the first top surface6of the first substrate4and the second wiring conductor arranged on the second top surface10of the second substrate7, via a surface-mounted conductive bump. According to the present disclosure, the electric and mechanical coupling may be referred to as mounting. The surface-mounted conductive bump is a solder bump composed of tin-lead (Sn—Pb) alloy or tin-silver-copper (Sn—Ag—Cu) alloy, or made of gold (Au).

The surface-mounted electrode pads are each electrically coupled to the predetermined circuit wiring through at least one of the wiring conductors arranged on the first substrate4and the second substrate7, inner conductors arranged inside the first substrate4and the second substrate7, through-conductors such as via-conductors formed from the surfaces of the first substrate4and the second substrate7to the insides thereof, and connectors16, which will be described below. The terminals of the first electronic component3and the terminals of the second electronic component5are electrically coupled to corresponding circuit wiring via the surface-mounted electrode pads. In another example, the first electronic component3and the second electronic component5may be coupled to the wiring conductors of the first substrate4and the second substrate7, respectively, via bonding wires.

Materials for the wiring conductor described above include, for example, copper (Cu), nickel (Ni), gold (Au), and silver (Ag). The wiring conductor may contain a metal material with a low melting point. The metal material with a low melting point may be used for wiring conductors organic substrates. The wiring conductor may be formed by a metal layer forming technique including thick-film methods and thin-film methods.

The first substrate4and the second substrate7may each be configured as organic substrates. Organic substrates include copper-clad substrates. Copper-clad substrates may have copper foil provided on top of, for example, a glass epoxy resin plate composed of a mixture of a base material made of an organic material such as the epoxy resin and glass fibers or glass powder. The wiring conductors may be formed by removing portions of the copper foil from the copper-clad substrate by pattern etching.

The first substrate4and the second substrate7may each utilize an inorganic insulating material. Substrates utilizing an inorganic insulating material may be produced by substrate forming methods including, for example, ceramic green sheet laminating and extrusion molding. The inorganic insulating material may include glass ceramics, alumina ceramics, aluminum nitride ceramics, etc.

Wiring conductors for the inorganic insulating materials may be formed from a sintered body that contains at least one of copper, gold, silver, tungsten, and molybdenum. The thickness of the wiring conductor may range from 5 μm to 50 μm.

The second substrate7includes a second bottom surface15. The second bottom surface15faces the first top surface6of the first substrate4. The electronic component package1includes a connector16. The connector16mechanically couples the first top surface6of the first substrate4and the second bottom surface15of the second substrate7. The connector16electrically couples the first wiring conductor of the first substrate4and the second wiring conductor of the second substrate7. The connector16may serve as an interposer. The interposer may include a conducting pattern. The conducting pattern transmits an electrical signal between the first substrate4and the second substrate7. A base material for the interposer may be, for example, an insulating material including an epoxy resin. The interposer may have a prism form extending in the second direction Y. The connector16serving as the interposer may be denoted as connector16a. The connector16may be referred to as connector16bwhen realized as solder bumps, as will be described below.

The first substrate4and the second substrate7are rectangular plates. The periphery8of the first substrate4includes four side portions17a,17b,17c, and17d. The periphery9of the second substrate7includes four side portions18a,18b,18c, and18d. The second substrate7is shorter than the first substrate4in the second direction Y. Among the four side portions18ato18dof the second substrate7, the side portions18aand18bextending in a first direction X are positioned within the sealing member2throughout their lengths. The side portions18aand18bmay be in contact with the sealing member2throughout their lengths. The side portions18cand18dextending in the second direction Y are exposed from side faces of the sealing member2. A part of the second substrate7is exposed from the side faces of the sealing member2. According to another embodiment, the side portion18aalone, or all of the four side portions18ato8dof the second substrate7may be positioned within the side faces of the sealing member2.

The sealing member2may be made of an insulating resin. Insulating resins include cured resin materials. Resin materials include thermosetting resin materials. The sealing member2may include a filler. Fillers may include insulating fillers and conductive fillers. Fillers having at least one of thermal conductivity and thermal expansion coefficient close to a desired range may be used. Thermosetting resin materials include, for example, epoxy-based thermosetting resins, polyimide-based thermoplastic resins, and bismaleimide-based thermosetting resins. The filler may include metals, metal oxides, and metal nitrides. Metal oxides may include aluminum oxide (Al2O3) and beryllium oxide (BeO). Metal nitrides include aluminum nitride (AlN). The filler may include a carbon-containing material, such as silicon carbide (SiC) and diamond.

A part of the second substrate7is positioned within the sealing member2formed across the first top surface6of the first substrate4. The second substrate7may be substantially parallel with the first substrate4. The sealing member2is integrally formed in the first space12between the first top surface6of the first substrate4and the second bottom surface15of the second substrate7, the second space13on the second top surface10of the second substrate7, and the third space14outside the side portions18aand18bof the second substrate7. In a plan view, the third space14is positioned between the side portion17aand the side portion18a, and between the side portion17band the side portion18b. The sealing member2integrally supports the first substrate4and the second substrate7. The electronic component package1is highly resistant against, for example, separation between the first substrate4and the second substrate7.

A part of the second substrate7is exposed from the side surface of the sealing member2. The first substrate4and the second substrate7may be rectangular plates in a plan view. Because the side portions18cand18dof the second substrate7are exposed from the side faces of the sealing member2, the second substrate7the area for mounting the second electronic component5thereon can be increased. The connectors16extends along the side portions17cand17dof the first substrate4and the side portions18cand18dof the second substrate7that are exposed from the side surfaces of the sealing member2. A large area of the first substrate4between the connectors16for mounting the first electronic component3can be maintained. When the connectors16are prism interposers extending between the first substrate4and the second substrate7, a number of electrodes can be coupled via a conductor between the first substrate4and the second substrate7. When the connectors16are formed as large bumps, connection resistance between the first substrate4and the second substrate7may be reduced.

The first electronic component3and the second electronic component5are sealed by the sealing member2that is contiguously formed. Thus, heat generated by one or both of the first electronic component3and the second electronic component5can diffuse into the sealing member2provided throughout the first to third spaces12to14. The diffused heat can dissipate into the air from the surface of the sealing member2in its entirety formed throughout the first to third spaces12to14. The heat generated by one or both of the first electronic component3and the second electronic component5can be diffused by thermal conduction to the sealing member2in its entirety formed throughout the first to third spaces12to14.

The first substrate4and the second substrate7are rectangular plates. The sealing member2extends integrally through a portion in the first space12and a portion in the second space13via a portion in the third space14. Even when the heat generated by the first electronic component3is different from heat generated by the second electronic component5, the generated heat can be diffused across the first to third spaces12to14and dissipated into the air from the surface of the sealing member2in its entirety.

The third space14having the sealing member2formed therein is positioned outside the side portions18aand18b. The sealing member2is made up of the portion in the first space12and the portion in the second space13coupled together via two portions in the third space14. The electronic component package1has a high thermal conductivity between the sealing member2in the first space12and the sealing member2in the second space13. Even when the heat generated by the first electronic component3is different from the heat generated by the second electronic component5, the electronic component package1is capable of balanced diffusion of heat in the portion of the sealing member2in the first space12and the portion in the second space13.

Portions of the sealing member2extends outside the side portions18aand18bthroughout their lengths. The sealing member2can maintain a wide heat exchange path between the first space12and second space13.

Because the sealing member2is formed from a thermosetting resin, in a state where the first substrate4having the first electronic component3mounted thereon and the second substrate7having the second electronic component5mounted thereon are vertically stacked, the thermosetting resin can be printed in a liquid state. A precursor of the thermosetting resin may be filled or applied in such a manner as to cover the first electronic component3mounted on the first substrate4and the second electronic component5mounted on the second substrate7. The precursor of the thermosetting resin in the liquid state thermally cures, thus forming the sealing member2throughout the first to third spaces12to14. In this way, the electronic component package1that is highly airtight and includes the first substrate4having the first electronic component3is mounted on the first top surface6and the second substrate7having the second electronic component5is mounted on the second top surface10may be produced.

The connector16formed by the interposer or a solder bump joins the first top surface6of the first substrate4and the second bottom surface15of the second substrate7. The second bottom surface15of the second substrate7is electrically coupled to the wiring pattern on the second top surface10. The first substrate4and the second substrate7are electrically coupled. The first substrate4and the second substrate7are mechanically and electrically coupled while vertically stacked. The connector16is positioned along the side portions17cand17dof the first substrate4and the side portions18cand18dof the second substrate7which are exposed from the side surfaces of the sealing member2.

FIG. 4is a plan view of a first substrate base member21. The first substrate base member21includes regions that constitute the first substrate4. The first substrate base member21is made of the same material as the first substrate4. The first substrate base member21may be a rectangular plate with, for example, a length of 70 mm on one side and a thickness of 100 μm to 400 μm. Electronic components are mounted on the first substrate base member21in the following manner by way of example: an IC and other electronic components are placed on the first substrate base member21, followed by reflow soldering of the first substrate base member21and the electronic components.

The first substrate base member21is subdivided into segments by dicing. Each segment corresponds to the first substrate4. The first substrate base member21is subdivided along subdividing lines23xand subdividing lines23y. The subdividing lines23xextend along the first direction X. The subdividing lines23xare arranged at intervals of ΔL2in the second direction Y. The subdividing lines23yare arranged at intervals of ΔL3in the first direction X. The subdividing lines23yextend along the second direction Y. For example, the intervals of ΔL2are 5.05 mm, and the intervals of ΔL3are 5.30 mm. For example, the subdividing lines23xeach have a width m1of 0.15 mm, and the subdividing lines23yeach have a width m2of 0.15 mm. The subdividing lines23xand23ymay be a series of grooves. The subdividing lines23xand23ymay be holes arranged at predetermined intervals.

According to some embodiments, each subdividing line23yof the first substrate base member21is provided with a connector16aw. The connector16awis base material to be subdivided to form an interposer. The connector16awmay be provided along both sides of the subdividing line23y. In this case, the connector16awincludes a conductor that serves as the conducting pattern after being subdivided along the subdividing line23y. The connector16awis subdivided by dicing along the subdividing line23and forms the connector16a, which is the interposer of each electronic component package1.

As illustrated inFIG. 4C, the connector16may be a connector16bformed by a solder bump for coupling the substrates. Connectors16bare arranged on along both sides of the subdividing lines23y. The connectors16bmay be arranged along the subdividing lines23xin addition to the subdividing lines23y.

FIG. 5is a plan view of a second substrate base member22. The second substrate base member22is made of the same material as the second substrate7. The second substrate base member22is a rectangular plate having, for example, a length of 70 mm in one side and a thickness of 100 μm to 400 μm. The second substrate base member22includes slits25. Electronic components are mounted on the second substrate base member22in the following manner: the IC and other electronic components are placed on the second substrate base member22, followed by reflow soldering of the electronic components and the second substrate base member22.

The second substrate base member22is subdivided into the segments by, for example, dicing. Each segment corresponds to the second substrate7. The second substrate base member22is subdivided along subdividing lines24xand subdividing lines24y. The subdividing lines24xextend along the first direction X. The subdividing lines24xare arranged at intervals of ΔL4in the second direction Y. The subdividing lines24yare arranged at intervals of ΔL5in the first direction X. The subdividing lines24yextend along the second direction Y. For example, the intervals of ΔL5in the first direction X are 5.30 mm, and the intervals of ΔL4in the second direction Y are 5.05 mm. For example, the lines24xeach have a width m3of 0.15 mm, and the lines24yeach have a width m4of 0.15 mm. The subdividing lines24xand24ymay be a series of grooves. The subdividing lines24xand24ymay be holes arranged at predetermined intervals.

The second substrate base member22includes slits25. The slits25of the second substrate base member22extend in the first direction X. The slits25may be formed by various processes including, for example, mold stamping or dicing. Each of the slits25may be continuous to any one of the subdividing lines24x. The slits25each have a width ΔL6that is parallel with the second direction Y and wider than the width m3of the subdividing line24x. The width ΔL6of the slit25may be, for example, 1.00 mm.

FIG. 6andFIG. 7are flowcharts illustrating an example of the manufacturing process of the electronic component package1.FIG. 8AtoFIG. 8Care cross-sectional diagrams illustrating an example of the manufacturing process of the electronic component package1in a simplified manner.

In step s1, solder paste is applied to the wiring conductor of the first substrate base member21. The solder paste is applied to the wiring conductor including the first wiring conductor of the first substrate4after being subdivided. The solder paste is applied to a region including a region where the solder bumps serving as the connectors16bare to be formed. The solder paste is applied by printing including, for example, screen printing. In step s2, the first electronic component3and other electronic components are arranged on the first wiring conductor. In step s3, the first substrate base member21having the first electronic component3and other electronic components arranged thereon is subjected to reflow soldering. By reflow soldering, the first electronic component3and other electronic components are mounted on the first substrate base member21via solder. The solder paste is melt by the reflow soldering and forms the solder bumps serving as the connectors16b. In step s4, the first substrate base member21having the first electronic component3, other electronic components, and the connectors16mounted thereon as illustrated inFIG. 8Ais washed. InFIG. 8A, the boundaries to be subdivided into the segments by dicing, which will be described below (step s11), are indicated by the dashed lines. The washing removes particles and organic substances adhering to the first substrate base member21. In step s5, the first substrate base member21having the first electronic component3, other electronic components, and the connectors16mounted thereon is subjected to visual inspection.

In the example of the manufacturing process of the electronic component package1, steps s21to s25are executed in parallel with steps s1to s5. In step s21, solder paste is printed on the wiring conductor of the second substrate base member22having the slits25. The solder paste is applied to the wiring conductor including the second wiring conductor on the second top surface10of the second substrate7after being subdivided. The solder paste is applied by printing including, for example, the screen printing. In step s22, the second electronic component5and other electronic components are arranged on the second wiring conductor. In step s23, the second substrate base member22having the second electronic component5and other electronic components arranged thereon is subjected to reflow soldering. By reflow soldering, the second electronic component5and other electronic components are mounted on the second substrate base member22via solder. In step s24, the second substrate base member22having the second electronic component5and other electronic components mounted thereon is washed. The washing removes particles and organic substances adhering to the second substrate base member22. In step s25, the second substrate base member22is subjected to visual inspection.

By following steps s1to s5described above, the first substrate base member21having the first electronic component3, other electronic components, and the connector16mounted thereon is prepared. By following steps s21to s25, the second substrate base member22having the second electronic component5and other electronic components mounted thereon is prepared. In step s6, the second substrate base member22is placed on top of the first substrate base member21via the connector16. In step s7, in a state in which the second substrate base member22is placed on top of the first substrate base member21via the connector16, the first and second substrate base members21and22are subjected to reflow soldering. By reflow soldering, the bump serving as the connector16bmelts and electrically couples the first substrate base member21and the second substrate base member22as illustrated inFIG. 8B.

In step s8, the assembled substrate in which the second substrate base member22is mounted on the first substrate base member21is washed. The washing removes particles and organic substances adhering to the assembly substrate. In step s9, a resin precursor of the thermosetting resin in a liquid state is printed on the assembled substrate of the first substrate base member21and the second substrate base member22using a metal mask. By printing, the resin precursor in the liquid state is filled between the first substrate base member21and the second substrate base member22and covers the second electronic component5and other electronic components mounted on the second substrate base member22. In other words, the resin precursor is filled in spaces corresponding to the first to third spaces12to14.

In step s10, the resin precursor filled in or applied to the assembled substrate of the first substrate base member21and the second substrate base member22cures in heat in a batch furnace. When cured, the resin precursor serves as the sealing member2filling the first space12to third space14. In step s11, the assembled substrate of the first substrate base member21and the second substrate base member22is subjected to dicing. The dicing is performed in the first direction X and the second direction Y. By dicing, the assembled substrate of the first substrate base member21and the second substrate base member22is subdivided into the segments as illustrated inFIG. 8C. Each segment after subdividing serves as the electronic component package1. As illustrated inFIG. 8C, each segment after subdividing includes the sealing member2formed across the first top surface6of the first substrate4. After subdividing, each segment the second substrate7is positioned within the sealing member2.

The side portions18aand18bof the second substrate7each correspond to a portion of the slit25. The third space14corresponds to a space on the first substrate base member21inside the slit25in a plan view.

The connector16may be a connector16cconfigured with a connection conductor enclosed in an insulating sleeve. In the connector16c, the connection conductor has a substantially cylindrical shape and is enclosed in the insulating sleeve formed from an insulating resin. The first wiring conductor of the first substrate base member21and the second wiring conductor of the second substrate base member22may be electrically coupled via the connector16c. The connector16cis arranged on the first substrate base member21in step s2and mounted thereon in step s3.FIGS. 9A to 9Care diagrams each illustrating a part of the manufacturing process using the connector16cthat includes the insulating sleeve.FIGS. 9A to 9Ccorrespond toFIGS. 8A to 8C, respectively.

The side portions18a,18b,18c, and18dof the second substrate7do not need to be exposed throughout their entire lengths from the side surface of the sealing member2. In other words, the third space14may extend over the side portions18ato18din plan view.

The sealing member2configured as described above enables the first substrate4and the second substrate7to be joined with high strength. The third space14of the sealing member2enables an increase in a heat transfer area between the first space12and the second space13. Even when a large amount of heat is generated in one of the first electronic component3and the second electronic component5, the generated heat is rapidly diffused into the sealing member2in the first to third spaces12to14.

The electronic component package1may include a film-like conductive member on the surface of the sealing member2. The film-like conductive member is formed by, for example, vapor deposition to the surface of the sealing member2. The first substrate4and the second substrate7are molded according to the film-like conductive member. The film-like conductive member of the electronic component package1serves as an electromagnetic shield.

The electronic component package1may include a conductive member on the entire surface or a part of the surface of the sealing member2. The electronic component package1may include the conductive member on a region that requires electromagnetic shielding. By having the conductive member on the surface of the sealing member2, the electronic component package1can separately provide a sealing function with the thermosetting resin and an electromagnetic shielding property with the conductive member.

The sealing member2may be a mixture of a thermosetting resin such as an epoxy resin and a magnetic material such as ferrite. The sealing member2in this configuration has airtight properties and electromagnetic shielding properties.

After the visual inspection in step s25as described above, the second substrate base member22may be subjected to dicing along the subdividing lines24xand24y. In this case, the second substrate7of each segment is mounted on the first substrate base member21in step s6.

The present disclosure is not limited to the electronic component package1having a two-layer structure of the first substrate4and the second substrate7but includes an electronic component package having a structure with three or more layers.

The electronic component package of the present disclosure is applicable also to a wireless module having an antenna. An electronic component package31according to one of embodiments of the present disclosure is illustrated inFIG. 10. The electronic component package31includes the first substrate4having a radio module32mounted thereon and the second substrate7having an antenna33mounted thereon. A resonator34capable of functioning as a frequency selective surface (FSS) may be arranged between the antenna33and the second substrate7. The resonator34may be arranged inside of, or on the bottom surface of, the second substrate7. InFIG. 10, elements the same as or similar to those of the embodiment inFIG. 1toFIG. 3are denoted by the same reference signs, and descriptions thereof will be omitted.

The resonator34may be configured to resonate in response to incident of electromagnetic waves and may have unit conductors for reflecting electromagnetic waves of a predetermined wavelength cyclically arranged in a two-dimensional manner. The unit conductor may be, for example, a thin metal film. The FSS, in combination with an electrically grounded portion, may function as an artificial magnetic conductor (AMC). The AMC may reflect incident electromagnetic wave substantially in phase.

In the electronic component package31, the antenna33may be positioned in the vicinity of a conductive surface. Radio waves having a frequency close to the resonance frequency of the resonator34radiated from the antenna33may reduce the destructive interference with the radio wave reflected on the conductive surface and radiate to the side opposite to the conductor surface. For example, the electronic component package31may be arranged in the vicinity of a top surface of a flat metal battery such as a button cell. The resonator34may be arranged on a top surface of the radio module32or between the first substrate4and the radio module32.

It is to be appreciated that the present disclosure is not limited to the embodiments set forth above and may include various changes within the scope of the present disclosure.

REFERENCE SIGNS LIST