Voltage clamper capable of controlling a voltage drop according to an external input voltage

A voltage clamper for controlling an input voltage to generate an output voltage is provided. The voltage clamper includes a bias circuit for generating at least a bias voltage according to the input voltage, a voltage drop circuit for applying a voltage drop to the input voltage, and a voltage detection circuit electrically connected to the voltage drop circuit and the bias circuit for generating the output voltage through adjusting the voltage drop generated from the voltage drop circuit according to the bias voltage.

BACKGROUND OF INVENTION

1. Field of the Invention

The present invention provides a voltage clamper, and more particularly, to a voltage clamper capable of providing a corresponding voltage drop according to an external input voltage.

2. Description of the Prior Art

With the progressive development of semiconductor processes, many different circuits are integrated into integrated circuits to drive the development of electronic products. For example, one memory chip may comprise a plurality of memory cells for storing data. Owing to the development of semiconductor processes, more memory cells are accommodated in a same area on a memory chip. Typically, the operation voltages of internal devices are limited in a voltage range according to the spec of integrated circuits. For example, the operation voltage of the above-mentioned memory chip must be limited in a voltage range to allow the memory chip to function normally. When the operation voltage supplied to the memory chip is too high, structural damage to the memory cells in the memory chip may cause reliability issues in data storage of memory cells. Oppositely, the operation voltage may not be able to successfully drive the memory cells to store data in a predetermined period of time when the operation voltage supplied to the memory chip is too low. Therefore, the memory chip must operate under a low clock. In other words, an operation voltage that is too low will affect the performance of the memory chip greatly.

Generally speaking, the same memory chip can be applied to different devices and used for storing data temporarily. However, different devices may be supplied with different external voltages. For example, the power supply module of one device provides a voltage level of 3.6V, but the power supply module of another device provides a voltage level of 1.6V. Therefore, the prior art memory chip utilizes a voltage drop circuit to transform the external voltage to the internal operation voltage that is applicable to the memory chip. For example, the voltage drop circuit may generate a fixed voltage drop of 1V. Under the circumstances, the range of the operation voltage of the memory chip to function normally is 2.6V-1.6V, based on the spec of the voltage drop circuit. In other words, the memory chip having such a voltage drop circuit can be only applied to devices supplied with an external voltage ranging from 3.6V to 2.6V. When the memory chip having such a voltage drop circuit is applied to a device supplied with an external voltage of 4V, the operation voltage of the memory chip will exceed the normally functional range of the operation voltage of the memory chip (2.6V-1.6V), since the operation voltage of the memory chip, used for driving the internal memory cells, is 3V after the voltage drop circuit applies a voltage drop of 1V to the external voltage. As a result, reliability issues arise when the memory chip is storing data. Similarly, the operation voltage of the memory chip, used for driving the internal memory cells, is 1V after the voltage drop circuit applies a voltage drop of 1V to the external voltage when the memory chip having such a voltage drop circuit is applied to a device supplied with an external voltage of 2V. Since 1V is not within the normally functional range of the operation voltage of the memory chip (2.6V-1.6V), the performance of the memory chip is greatly affected due to this operation voltage that is too low, as mentioned previously.

Since a fixed voltage drop is generated by the voltage drop circuit utilized in the prior art memory chip, the application range of the memory chip is limited by the fixed voltage drop. As mentioned previously, the memory chip can be only applied to devices supplied with an external voltage ranging from 3.6V to 2.6V because a 1V voltage drop is generated by the voltage drop circuit and the normally functional range of the operation voltage of the memory chip is 2.6V-1.6V. When the memory chip is applied to a device supplied with an external voltage of 4V, the voltage drop circuit on the memory chip needs to be re-designed to lift the voltage drop generated by itself. Similarly, when the memory chip is applied to a device supplied with an external voltage of 2V, the voltage drop circuit on the memory chip also needs to be re-designed to reduce the voltage drop generated by itself. Therefore, the production cost of the memory chip is greatly raised to make the memory chip not competitive.

SUMMARY OF INVENTION

It is therefore a primary objective of the present invention to provide a voltage clamper to determine a corresponding voltage drop according to an external input voltage to resolve the above-mentioned problems.

According to the claimed invention, a voltage clamper for generating an output voltage by adjusting an input voltage age is disclosed. The voltage clamper comprises a bias circuit for generating at least a bias voltage according to the input voltage, a voltage drop circuit for applying a voltage drop to the input voltage, and a voltage detection circuit electrically connected to the voltage drop circuit and the bias circuit for generating the output voltage through adjusting the voltage drop generated from the voltage drop circuit according to the bias voltage.

According to the claimed invention, a voltage adjusting method for generating an output voltage by adjusting an input voltage is disclosed. The voltage adjusting method comprises setting a plurality of voltage segments corresponding to a plurality of different voltage drop setting values, and utilizing one of the voltage drop setting values to trigger a voltage difference between the output voltage and the input voltage corresponding to the voltage drop setting value when the input voltage is within one of the voltage segments.

It is an advantage of the claimed invention that the present invention voltage clamper dynamically determines the voltage drop applied in the voltage drop operation according to the voltage level of the external input voltage, rather than applying a fixed voltage drop. Therefore, the present invention voltage clamper can maintain the output voltage within the corresponding range of the operation voltage of the device utilizing the present invention voltage clamper, no matter if the external input voltage has a high voltage level or a low voltage level. As a result, the phenomena of insufficient voltage drop and over high voltage drop, which usually occur when utilizing the prior art voltage clamper, do not occur when utilizing the present invention voltage clamper.

These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.

DETAILED DESCRIPTION

Please refer to FIG.1.FIG. 1is a function block diagram of a voltage clamper10of the present invention. The present invention voltage clamper10comprises a bias circuit12, a voltage detection circuit14, and a voltage drop circuit16. The bias circuit12is used for generating a bias voltage according to an input voltage Vin. The voltage detection circuit14determines how much voltage drop the voltage drop circuit16applies to the input voltage Vinaccording to the bias voltage so as to generate an output voltage Vout. In this preferred embodiment, a plurality of bias units18are installed in the bias circuit12, a plurality of voltage detection units20are installed in the voltage detection circuit14, and a plurality of voltage drop units22and a predetermined voltage drop unit23are installed in the voltage drop circuit16. Without altering the teachings of the invention, only three bias units18a,18b,18n, three voltage detection units20a,20b,20n, and three voltage drop units22a,22b,22nare shown inFIG. 1for simplicity. When the input voltage Vinis input to the bias circuit12, the bias unit18awill generate a bias voltage V1according to the input voltage Vin, the bias unit18bwill generate a bias voltage V2according to the input voltage Vin, and the bias unit18nwill generate a bias voltage Vnaccording to the input voltage Vin. The voltage levels of the bias voltages V1, V2, Vnare different from each other. Assume that the bias voltage V1is greater than the bias voltage V2, and the bias voltage V2is greater than the bias voltage Vn. Although the bias voltages V1, V2, Vnchange when the magnitude of the input voltage changes, the relative magnitude relationship of the bias voltages V1, V2, Vndoes not change. For example, if the bias voltages V1, V2, Vnare 2V, 1.8V, and 1.5V, respectively, when the input voltage V1nis 5V, the bias voltages V1, V2, Vnare reduced to 1.6V, 1.4V, and 1.2V, respectively, when the input voltage V1nis reduced to 4V. Therefore, the bias voltage V1is still greater than the bias voltage V2, and the bias voltage V2is still greater than the bias voltage Vn.

The voltage detection unit20areceives the bias voltage V1to generate a control signal D1according to the bias voltage V1, the voltage detection unit20breceives the bias voltage V2to generate a control signal D2according to the bias voltage V2, and the voltage detection unit20nreceives the bias voltage Vnto generate a control signal Dnaccording to the bias voltage Vn. In this preferred embodiment, each voltage detection unit20a,20b,20nin the voltage detection circuit14is used for detecting a same predetermined voltage level. That means, each voltage detection unit20a,20b,20nsieves the bias voltages V1, V2, Vnaccording to the predetermined voltage level and decides whether to output the control signal D1, D2, Dnto activate the voltage drop unit22a,22b,22nor not. Each voltage drop unit22a,22b,22nis used to apply a different voltage drop to the input voltage Vinto adjust the voltage level of the output voltage Vout. For example, the voltage drop unit22amay make the input voltage Vingenerate a voltage drop of dV1. That means, the output voltage Voutwill be approximately equal to Vin−dV1when the voltage drop unit22ais activated. Similarly, the voltage drop unit22bmay make the input voltage Vingenerate a voltage drop of dV2. That means, the output voltage Voutwill be approximately equal to Vin−dV2when the voltage drop unit22bis activated. The voltage drop unit22nmay make the input voltage Vingenerate a voltage drop of dVn. That means, the output voltage Voutwill be approximately equal to VindVnwhen the voltage drop unit22nis activated. Therefore, the voltage drops between the output voltage Voutand the input voltage Vinare controlled by the voltage drop units22a,22b,22n. Furthermore, a predetermined voltage drop unit23is installed in the voltage drop circuit16to apply an initial voltage drop to the input voltage Vinto affect the output voltage Voutwhen the voltage age clamper10is activated.

Please refer to FIG.2.FIG. 2is a circuit diagram of the voltage clamper10shown in FIG.1. In order to illustrate more conveniently, only two bias units18a,18b, two voltage detection units20a,20b, two voltage drop units22a,22b, and one predetermined voltage drop unit23are shown in the voltage clamper10shown in FIG.2. As shown inFIG. 1, please note that the numbers of the bias units, the voltage detection units, and the voltage drop units are not limited in the present invention voltage clamper10. In this preferred embodiment, a current I1flowing through the bias unit18ais different from a current I2flowing through the bias unit18bunder the same input voltage Vinby applying different connection structures to transistors24a,24b,24c,24dand transistors26a,26b,26c,26din the bias units18a,18b. Finally, the bias voltage V1is controlled to be greater than the bias voltage V2. In addition, the bias units18a,18bmay utilize other kind of circuits (such as a voltage dividing circuit comprising only resistors) to achieve the objective that different bias voltages V1, V2are generated under the same input voltage Vin. The bias voltage V1generated by the bias unit18ais input to an input terminal A of the voltage detection unit20a. The voltage detection unit20athus decides whether to conduct transistors28a,28bor not according to the bias voltage V1. If the bias voltage V1is greater than a predetermined voltage level, the transistor28bis turned on to drive the control signal D1to approach a high logic level “1”. Oppositely, the transistor28ais turned on and the transistor28bis not turned on to drive the control signal D1to approach a low logic level “0” if the bias voltage V1is smaller than the predetermined voltage level. In addition, the bias voltage V2generated by the bias unit18bis input to an input terminal B of the voltage detection unit20b. Similarly, the voltage detection unit20bthus decides whether to turn on the transistors30a,30bor not according to the bias voltage V2. If the bias voltage V2is greater than the same predetermined voltage level, the transistor30bis turned on to drive the control signal D2to approach the low logic level “0”. Oppositely, the transistor30ais turned on and the transistor30bis not turned on to drive the control signal D2to approach the high logic level “1” if the bias voltage V2is smaller than the same predetermined voltage level.

In the voltage detection unit20a, the operation of inverters32a,32b,32cis similar to that of a prior art Schmitt trigger, and an inverter32dfunctions as a buffer. In addition, a substrate, a source, and a drain of a transistor28fare connected to ground. Therefore, the transistor28ffunctions as a capacitor module to stabilize the control signal D1. When the transistor28bis turned on, the loop formed by the inverters32b,32cwill maintain an input terminal of the inverter32dat the low logic level “0”, and the transistor28eis turned on. When the transistor28bis not turned on, the loop formed by the inverters32b,32cwill maintain the input terminal of the inverter32dat the high logic level “1”, and the transistor28eis not turned on. For the voltage detection unit20b, the operation of inverters34a,34b,34cis similar to that of the prior art Schmitt trigger, and inverters34d,34efunction as buffers. In addition, a substrate, a source, and a drain of a transistor30fare connected to ground. Therefore, the transistor30ffunctions as a capacitor module to stabilize the control signal D2. When the transistor30bis turned on, the loop formed by the inverters34b,34cwill maintain an input terminal of the inverter34dat the low logic level “0”, and a transistor30eis turned on. When the transistor30bis not turned on, the loop formed by the inverters34b,34cwill maintain the input terminal of the inverter34dat the high logic level “1”, and the transistor30eis not turned on.

The voltage drop unit22acomprises a transistor36, and the voltage drop unit22bcomprises a transistor38. In this preferred embodiment, the transistor36is a P-type metal-oxide-semiconductor (PMOS) transistor, and the transistor38is an N-type metal-oxide-semiconductor (NMOS) transistor. As well known by those skilled in the art, a P-type metal-oxide-semiconductor transistor is a good switch device, and an N-type metal-oxide-semiconductor transistor is a bad switch device, when transferring a high logic level “1”. In other words, the voltage level at a drain of the transistor36is approximately equal to that at a source of the transistor36(that means the input voltage Vin) when the transistor36is turned on. However, the voltage level at a drain of the transistor38is greater than that at a source of the transistor38when the transistor38is turned on. In other words, the voltage level at the source of the transistor38is approximately equal to Vin−Vt, rather than the input voltage Vin. It is worth noting that Vtis the threshold voltage corresponding to a channel of the transistor38. In addition, the predetermined voltage drop unit23comprises two transistors40a,40bin this preferred embodiment, and transistors40a,40bare both N-type metal-oxide-semiconductor transistors. As shown inFIG. 2, a drain of the transistor40ais connected to a gate of the transistor40a, and a drain of the transistor40bis connected to a gate of the transistor40b. Therefore, the transistors40a,40bare always turned on and operate within a saturation region. As mentioned previously, an N-type metal-oxide-semiconductor transistor is a bad switch device when transferring a high logic level “1”. If the transistors40a,40bhave the same threshold voltage Vtas the transistor38, the voltage level at a source of the transistor40beventually approaches Vin−2Vt. InFIG. 2, a transistor42utilized in the voltage clamper10functions as a capacitor module to stabilize the voltage level of the output voltage Vout. In this preferred embodiment, a gate and a drain of the transistor are electrically connected to the output voltage Vout, and a substrate and a source of the transistor42are connected to ground. It is very obvious that the transistor42will be kept in a conductive state when the voltage clamper10is operating. Therefore, the transistor42may be regarded as a resistor in parallel with a capacitor. In comparison with the transistors28f,30f, the transistor42has a greater RC time constant to maintain the output voltage Voutmore stably.

Please refer to FIG.2and FIG.3.FIG. 3is a schematic diagram of the output voltage of the voltage clamper10shown in FIG.2. InFIG. 3, the horizontal axis represents the input voltage Vin, and the vertical axis represents the output voltage Vout. It is known from the above description that the bias voltage V1output by the bias unit18ais greater than the bias voltage V2output by the bias unit18bwith the same input voltage Vin, and the voltage detection units20a,20bdetect a predetermined voltage level to decide whether to activate the voltage drop units22a,22bor not. When the input voltage Vinis equal to the voltage level of (Vs)2, the bias voltage V2is equal to the predetermined voltage level. At this time, the bias voltage V1is greater than the predetermined voltage level since the bias voltage V1is greater than the bias voltage V2. In other words, the transistor30bin the voltage detection unit20bwill keep conducting until the bias voltage V2starts to be smaller than the predetermined voltage level. The control signal D2is thus at the high logic level “1” to activate the corresponding voltage drop unit22b. When the input voltage Vinis equal to the voltage level of (Vs)1, the bias voltage V1is equal to the predetermined voltage level. At this time, the bias voltage V2is smaller than the predetermined voltage level since the bias voltage V2is smaller than the bias voltage V1. In other words, the transistor28bin the voltage detection unit20awill keep conducting until the bias voltage V1starts to be smaller than the predetermined voltage level. The control signal D1is thus at the low logic level “0” to activate the corresponding voltage drop unit22a. It is worth noting that the transistor30bin the voltage detection unit20bwill be kept in a non-conductive state since the bias voltage V2is smaller than the predetermined voltage. The control signal D2is thus kept at the high logic level “1”. As a result, the corresponding voltage drop unit22bis kept in an active state.

As shown inFIG. 3, an oblique line L1represents that the output voltage Voutis equal to the input voltage Vin. When the input voltage Vinis greater than the voltage level of (Vs)2, the bias voltages V1, V2corresponding to the input voltage Vinare both greater than the above-mentioned predetermined voltage level. At this time, only the predetermined voltage drop unit23will affect the output voltage Vout. That means, the voltage difference between the output voltage Voutand the input voltage Vincorresponds to the voltage difference applied by the transistors40a,40b(2*Vt), when the input voltage Vinis greater than the voltage level of (Vs)2, and the relationship between the output voltage Voutand the input voltage Vinis shown in segment S1. When the input voltage Vinis smaller than the voltage level of (Vs)2and is greater than the voltage level of (Vs)1, the bias voltage V2corresponding to the input voltage Vinis smaller than the predetermined voltage level, and the bias voltage V1corresponding to the input voltage Vinis still greater than the predetermined voltage level, as mentioned previously. At this time, both the voltage drop unit22band the predetermined voltage drop unit23are activated. It is worth noting that the predetermined voltage drop unit23will apply a voltage difference of 2*Vt to the input voltage Vin, and the voltage drop unit22bwill only apply a voltage difference of Vtto the input voltage Vin. Since the transistor42is used as a capacitor module, the voltage drop unit22bwill charge the transistor42and trigger the voltage difference between the output voltage Voutand the input voltage Vincorresponding to the voltage difference applied by the transistor38(Vt), and the relationship between the output voltage Voutand the input voltage Vinis shown in segment S2. When the input voltage Vinis smaller than the voltage level of (Vs)1, the bias voltages V1, V2corresponding to the input voltage Vinare both smaller than the predetermined voltage level, as mentioned previously. At this time, the voltage drop units22a,22band the predetermined voltage drop unit23are all activated. It is worth noting that the predetermined voltage drop unit23will apply a voltage difference of 2*Vtto the input voltage Vin, and the voltage drop unit22bwill apply a voltage difference of Vtto the input voltage Vin, and the voltage drop unit22awill not apply any voltage difference to the input voltage Vin. That means, the voltage drop unit22atransfers the input voltage Vinto trigger the output voltage Vout. Since the transistor42is used as a capacitor module, the voltage drop unit22awill charge the transistor42to trigger the output voltage Voutto be approximately equal to the input voltage Vin. The relationship between the output voltage Voutand the input voltage Vinis shown in segment S3.

It is worth noting that gates of the transistors28c,28dof the voltage detection unit20aare all triggered by a control signal CEB in the voltage clamper10in FIG.2. Similarly, gates of the transistors30c,30dof the voltage detection unit20bare all triggered by the same control signal CEB. The present invention voltage clamper10supports chip enable control to achieve the objective of low current consumption. The voltage clamper10can switch to a standby mode or a normal mode according to the external control signal CEB. For example, the voltage clamper10will enter the standby mode when the control signal CEB is at the high voltage level. At this time, the transistors28c,30care not turned on, and the control signal CEB will turn on the transistors28d,30d. In other words, only the predetermined voltage drop unit23is activated when the voltage clamper10enters the standby mode, and the voltage drop units22a,22bcannot be turned on to adjust the output voltage Vout. Therefore, a greater voltage difference (that is 2*Vt) exists between the output voltage Voutand the input voltage Vin. For a device utilizing the voltage clamper10, the device will output the control signal CEB to the voltage clamper10when entering the standby mode. Since the output voltage Voutof the voltage clamper10in the standby mode is lower, the current consumed by the device in the standby mode is smaller to reduce power consumption. Oppositely, the control signal CEB will be at the low voltage level to trigger the voltage clamper10to enter the normal mode when the device wants to exit the standby mode and enter the normal mode. As shown inFIG. 2, the transistors28c,30care thus turned on to transfer the input voltage Vinto the transistors28a,30a. In addition, the transistors28d,30dwill be kept in a non-conductive state. Therefore, the activation of the voltage drop units22a,22bare controlled by the bias voltages V1, V2. That means, the relationship between the input voltage Vinand the output voltage Voutis shown as FIG.3.

If the present invention voltage clamper10is applied to a memory chip, and the normally functional range of the operation voltage of the memory chip is between the voltage level of Vtopand the voltage level of Vbot, the memory chip can operate smoothly when the input voltage Vinis between the voltage level of Vtopand the voltage level of VH(VH>Vbot), as shown from the relationship between the output voltage Voutand the input voltage Vinin FIG.3. Therefore, the greater the input voltage Vinis, the greater voltage drop between the input voltage Vinand the output voltage Voutis triggered by the voltage clamper10. Oppositely, the smaller the input voltage Vinis, the smaller voltage drop between the input voltage Vinand the output voltage Voutis triggered by the voltage clamper10. For example, the normally functional range of the operation voltage of the memory chip is 2.6V-1.6V. When the power supply module of a device supplies a high driving voltage of (2.6+2*Vt), the voltage clamper10will help to transform the input voltage (2.6+2*Vt) into an output voltage of 2.6V and transfer the output voltage (2.6V) to the memory chip to trigger the memory chip. The memory chip thus operates smoothly under such a high driving voltage. However, when the power supply module of a device supplies a low driving voltage of 1.6V, the voltage clamper10will not adjust the output voltage. That means, the output voltage is equal to the input voltage 1.6V, and the voltage clamper10will transfer the output voltage (1.6V) to the memory chip to trigger the memory chip. As a result, the memory chip can function normally under a low external voltage.

When the driving voltage supplied by the power supply module in a device is between the voltage level of VHand the voltage level of (Vs)2, the memory chip utilizing the voltage damper10can function normally in the device. Similarly, the memory chip utilizing the voltage damper10can function normally in the device when the driving voltage supplied by the power supply module is between the voltage level of (Vs)1and the voltage level of (Vs)2, and between the voltage level of Vbotand the voltage level of (Vs)1. However, there is a problem when the driving voltage supplied by the power supply module approaches (Vs)1or (Vs)2. It is known that the predetermined voltage level originally set by the voltage detection units20a,20bwill control the voltage damper10to trigger the output voltage Voutto generate changes of the voltage levels, when the voltage levels of Voutthe input voltage Vinare (VS)1and (VS)2. In other words, the output voltage Voutwill hop between two voltage levels if vibration of the driving voltage supplied by the power supply module occurs in the neighborhood of the voltage level of (Vs)1or (Vs)2. As a result, the memory chip generates unexpected errors. In order to resolve the problem, the voltage detection unit20afurther comprises an adjusting module44and the voltage detection unit20bfurther comprises an adjusting module46. The adjusting modules44,46are used for adjusting the predetermined voltage levels detected by the voltage detection units20a,20b.Please refer to FIG.4.FIG. 4is a circuit diagram of the adjusting module shown in FIG.2. It is worth noting that only the adjusting module44is illustrated because the configuration and the operation of the adjusting module44and the adjusting module46are the same. The adjusting module44comprises a plurality of transistors48. A drain of each of the transistors48is connected to a node A′ of the voltage detection unit20a,and a gate of each of the transistor48is selectively connected to a source of the transistor or an input terminal A of the voltage detection unit20a.When the gate of the transistor48is connected to the input terminal A of the voltage detection unit20a,the transistor48is regarded as being in parallel with the transistor28b.Therefore, the transistor48can be utilized to adjust the predetermined voltage level at the input terminal A detected by the voltage detection unit20a.Oppositely, the transistor48cannot be turned on and will not affect the operation of the voltage detection unit20awhen the gate of the transistor is connected to the source of the transistor. In this preferred embodiment, the gate of each of the transistor48is connected to the node A′ or the source of the transistor is programmed by an upper level metal layer. That means the metal layer is utilized to program the adjusting module44. For example, the initial setting of the adjustment module44is achieved by programming the upper level metal layer through a mask pattern design during the semiconductor processes for forming the voltage damper10, and the initial setting of the adjusting module44is that the gates of half of the transistors48are connected to the input terminal A and the gates of half of the transistors48are connected to the sources of the corresponding transistors48. At this time, the characteristic of the input voltage Vinand the output voltage Voutof the voltage damper10is shown in FIG.3. If it is known that the driving voltage supplied by the power supply module in a device approaches the voltage level of (Vs)t, another mask pattern design is utilized during the semiconductor processes for forming the voltage damper10. The numbers of the transistors48having the gates connected to the sources of the transistors48and the numbers of the transistors48having the gates connected to the input terminal A are thus adjusted to bias the voltage level of (Vs)1. In addition, the adjust module44can lower the voltage level of (Vs)1or lift the voltage level of (Vs)1. Therefore, the problem that the output voltage Voutprobably changes greatly due to the input voltage Vinapproaching the original voltage level of (Vs)1is avoided. Since the operation of the adjusting module46is the same as that of the adjusting module44, the adjust module46can lower the voltage level of (Vs)2or lift the voltage level of (Vs)2in this preferred embodiment. As a result, the problem that the output voltage Voutprobably changes greatly due to the input voltage approaching the original voltage level of (Vs)2is avoided. In summary, the devices having the voltage damper10can operate more stably by utilizing the adjusting modules44,46.

As mentioned previously, the operation of the voltage clamper10is to set the voltage detection units20a,20b,20nto detect the same predetermined voltage level, and each of the bias unit18a,18b,18ngenerates each of the different bias voltages V1, V2, Vnaccording to the input voltage Vin. Therefore, the magnitude of the input voltage Vinis determined according to the bias voltages V1, V2, Vnand the predetermined voltage level to control the activation of the voltage drop units22a,22b,22n. As a result, the voltage drop between the input voltage Vinand the output voltage Voutis adjusted. However, the objective of dynamically determining the voltage drop applied in the voltage drop operation according to the voltage level of the input voltage can be achieved by setting the voltage detection units20a,20b,20nto detect different predetermined voltage levels and each of the bias units18a,18b,18nto generate a same bias voltage according to the input voltage Vin. For example, each of the bias units18a,18bis set to generate a same bias voltage Vbaccording to the input voltage Vin. That means, the high input voltage Vinis transformed into the low bias voltage Vb. In addition, each of the voltage detection units20a,20bis set to detect different predetermined voltage levels of Vd1, Vd2, and the predetermined voltage level of Vd1is smaller than the predetermined voltage level of Vd2. It is very obvious that the greater the input voltage Vinis, the greater the bias voltage Vbis. Oppositely, the smaller the input voltage Vinis, the smaller the bias voltage Vbis. Therefore, the bias voltage Vbcan be used to represent the magnitude of the input voltage Vin. When the bias voltage Vbis greater than the predetermined voltage level of Vd2, only the predetermined voltage drop unit23is activated. When the bias voltage Vbis between the predetermined voltage level of Vd1and the predetermined voltage level of Vd2, both the predetermined voltage drop unit23and the voltage drop unit22bare activated. When the bias voltage Vbis smaller than the predetermined voltage level of Vd1, the predetermined voltage drop unit23and the voltage drop units22a,22bare activated. Consequently, the above-mentioned relationship between the input voltage Vinand the output voltage Voutis shown in FIG.3. Therefore, the bias circuit12and the voltage detection circuit14may be set in such a manner as to trigger the voltage drop circuit16, according to the voltage level of the input voltage Vin, so that the voltage difference between the output voltage Voutand the input voltage Vincorresponds to different voltage drops according to different voltage levels of the input voltage Vin.

Compared to the prior art voltage clamper, the present invention voltage clamper utilizes the bias circuit and the voltage detection circuit to judge the voltage level of the now applied external input voltage, and determine the corresponding voltage difference between the output voltage and the input voltage according to the voltage level. According to the present invention voltage clamper, a plurality of voltage segments are set and each of the voltage segments corresponds to a specific voltage drop to adjust the output voltage. A greater voltage drop is applied to the input voltage corresponding to the voltage segment having a higher voltage level to generate the expected output voltage. Oppositely, a smaller voltage drop is applied to the input voltage corresponding to the voltage segment having a lower voltage level to generate the expected output voltage. In other words, the present invention voltage clamper will apply a greater voltage drop, according to the input voltage, to greatly reduce the output voltage when the input voltage has a high voltage level. Therefore, the problem that one device (such as a memory chip), triggered by the output voltage generated by the voltage clamper according to the external input voltage, cannot function normally owing to the output voltage exceeding the normally functional range of the operation voltage of the device is avoided. In addition, the present invention voltage clamper will not perform the voltage drop operation when the input voltage has a low voltage level. Therefore, the performance of one device (such as a memory chip), triggered by the output voltage generated by the voltage clamper according to the external input voltage, is not greatly affected due to the output voltage being smaller than the normally functional range of the operation voltage of the device. In summary, the present invention voltage clamper dynamically determines the voltage drop applied in the voltage drop operation according to the voltage level of the external input voltage, rather than applying a fixed voltage drop. The present invention voltage clamper thus can maintain the output voltage within the range of the operation voltage of the device utilizing the present invention voltage clamper, no matter if the external input voltage has a high voltage level or a low voltage level. As a result, the phenomena of an insufficient voltage drop and an overly high voltage drop, which usually occur when utilizing the prior art voltage clamper, do not occur when utilizing the present invention voltage clamper.