Solid-state imaging apparatus and method of driving the same

A solid-state imaging apparatus includes: a plurality of pixels arranged in a matrix; a plurality of amplifier circuits each arranged correspondingly to each of columns of the pixels, for amplifying a signal from the pixel; and a current source transistor whose source is supplied with a power source voltage and which supplies the amplifier circuit with a bias current. When the current source transistor is operating in the saturation region, the gate voltage of the current source transistor that is supplied from the bias line is sampled and held. The gate voltage of the current source transistor with respect to the power source voltage is controlled to the sampled voltage, thereby suppressing variation. This suppression can, in turn, suppress occurrence of line noise and a lateral smear due to difference of drop in voltage of a power source line concerning a column circuit on each row.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a solid-state imaging apparatus and a method of driving the same.

2. Description of the Related Art

In recent years, solid-state imaging apparatuses, such as CMOS image sensors, have been achieving high performance and high functionality. One of these achievements is advancement in multi-pixel configuration of imaging devices for providing high resolution images. Accordingly, the number of circuits for reading pixel signals is increased, which in turn increases consumption current and also increases drop in voltage of a power source line. Thus, operating points of read out circuits connected to a common power source line are different depending on the positions, which causes horizontal shading.

To address this problem, Japanese Patent Application Laid-Open No. 2001-197378 takes measures to hold the gate voltage of a current source transistor, which supplies current to read out circuits (column circuits) arranged for respective columns, in a capacitor connected between a reference potential and the gate of the current source transistor during the column circuit being not in operation. In a period when the column circuit does not operate, that is, without drop in voltage of a power source line, the gate voltage of the current source transistor is held in the capacitor connected to the reference potential. Accordingly, even if the power source (reference) voltage drops after the column circuit operates, the gate voltage, i.e. voltage Vgs, of the current source transistor with respect to the reference potential becomes constant and thus the current values of the column circuits become the same. The problem of horizontal shading is therefore alleviated and solved.

SUMMARY OF THE INVENTION

Unfortunately, in a solid-state imaging apparatus that horizontally transfers a pixel signal concurrently with an operation of reading the pixel signal and performs analog-to-digital conversion in a chip to output a digital signal, the duration of time for reading one row is largely affected by time required for the operation of reading the pixel signal. Accordingly, a period in which a column circuit is in an off state (non-operating state) is shortened or not afforded. In the case without a period for causing the column circuit to be in the off state, following problems can occur.

For instance, in consideration of conditions where the following both terms (1) and (2) are satisfied in the identical imaging surface, sampled gate voltages differ among column circuits.

(1) A column where strong light is incident to saturate the column circuit when a certain row is read and a current source transistor operates in a linear region

(2) A column without strong light where the current source transistor of the column circuit operates in a saturation region

That is, in the state of term (1) where the current source transistor is in the linear operation, the drop in voltage of the power source line is small. Accordingly, the gate voltage of the current source transistor sampled at this time is different from a gate voltage sampled in the state of term (2). This difference may cause line noise, in which output levels differ among rows, and a lateral smear, in which output levels at the lateral ends of a highly bright object differ from levels at the other part to result in a streaky strip.

According one an aspect of the present invention, a solid-state imaging apparatus comprises: a plurality of pixels arranged in a matrix; a plurality of amplifier circuits each arranged correspondingly to each of columns of the pixels, the amplifier configured to amplify a signal from the pixel; a current source transistor arranged correspondingly to each of amplifier circuits, the current source transistor configured to supply a bias current to a corresponding one of the amplifier circuits and the current source transistor having a source supplied with a power source voltage; a sampling unit configured to sample, as a sampling voltage, a gate voltage of the current source transistor supplied from a bias line; and a holding unit configured to hold the voltage sampled by the sampling unit, and control a gate voltage thereafter of the current source transistor into the sampling voltage, wherein, in a period of operating the current source transistor in a saturation region, the gate voltage of the current source transistor is sampled and held.

DESCRIPTION OF THE EMBODIMENTS

First, a solid-state imaging apparatus according to one embodiment of the present invention will now be described.

FIG. 1is a block diagram illustrating an example of the configuration of a solid-state imaging apparatus according to the embodiment of the present invention. The solid-state imaging apparatus includes a pixel region101, a read out circuit102, a column analog-to-digital converter (column ADC)103, a horizontal scanning circuit104, a vertical scanning circuit105, a digital signal processor (DSP)106and a timing generator107.

The pixel region101is provided with a plurality of pixels including photoelectric conversion elements as illustrated inFIG. 2. The pixels are arranged in a matrix (in a row direction and a column direction). In the read out circuit102, circuits that read a pixel signal from the pixels of the pixel region101and amplify the signal are arranged correspondingly to the respective columns of the pixel region101. The column ADC103performs analog-to-digital conversion on the read pixel signal. The horizontal scanning circuit104reads the digital signal subjected to the analog-to-digital conversion by the column ADC103and sequentially transfers the signal to the DSP106. The vertical scanning circuit105performs control for reading the pixel signal in the pixel region101sequentially in the vertical direction. The DSP106performs a prescribed process on the digital signal transferred from the horizontal scanning circuit104. The timing generator107outputs control pulses to thereby control the read out circuit102, the column ADC103, the horizontal scanning circuit104, the vertical scanning circuit105and the DSP106.

FIG. 2is a diagram illustrating an example of a circuit configuration of the pixel in this embodiment. Each pixel in the pixel region101includes a photoelectric conversion element201and three MOS transistors202,203and204. The photoelectric conversion element201generates charge by photoelectric conversion. The photoelectric conversion element201is, for instance, a photodiode (PD). The transistor202is a transfer transistor (transfer switch) for transferring charge accumulated by photoelectric conversion in the photoelectric conversion element201to a floating diffusion portion205. The transistor203is a reset transistor (reset switch) for resetting the floating diffusion portion205and the photoelectric conversion element201. The transistor204is a source follower transistor (amplifier circuit) for determining the voltage of a pixel signal output line206by the potential of the floating diffusion portion205. In the transistor204, the gate is connected to the floating diffusion portion205, the source is connected to the pixel signal output line206, and the drain is connected to a power source.

A power source line VRES, which is for resetting the floating diffusion portion205, is connected to the drain of the reset transistor203. The potential of the power source line VRES is set to a high potential VRESH for resetting the floating diffusion portion205to a high potential, and set to a low potential VRESL for resetting the floating diffusion portion205to a low potential. pRES is connected to the gate of the reset transistor203, and set to a high level for writing the potential of the power source line VRES into the floating diffusion portion205. pTX is a control line for transferring, to the floating diffusion portion205, the charge photoelectrically converted by the photoelectric conversion element201, and is connected to the gate of the transfer transistor202and set to a high level for reading the photoelectric conversion element201.

FIG. 3is a diagram illustrating an example of a configuration of a signal read out unit in this embodiment. InFIG. 3, identical symbols are assigned to components identical to the components illustrated inFIG. 2. The redundant description is omitted.

InFIG. 3, a clip transistor302fixes the pixel signal output line206to any voltage. In resetting of the floating diffusion portion205, a switch303is turned on to thereby apply a voltage VCLIPH to the gate of the clip transistor302. When the transfer transistor202is turned on and charge in the photoelectric conversion element201is read, a switch304is turned on to thereby apply a voltage VCLIPL to the gate of the clip transistor302. The switch303is controlled by a signal pclip. The switch304is controlled by a signal pclip_b, which is an inverted signal of the signal pclip.

A clip circuit including the clip transistor302and the switches303and304is a voltage fixing unit for fixing the pixel signal output line206, i.e. the input of an amplifier circuit, to any voltage. For instance, when strong light is incident, the clip circuit suppresses decrease in potential of the floating diffusion portion205due to charge overflowing from the photoelectric conversion element201and thereby suppresses decrease in voltage of the pixel signal output line206. The suppression secures the dynamic range of the pixel signal output line206, and suppresses being blocked up shadows (losing a gradation) when a highly bright object is imaged.

A load current source301is for the source follower transistor204and the clip transistor302. An amplifier circuit306is arranged correspondingly to each column, and amplifies a signal read from the pixel. A clamp capacitor305clamps the voltage of the pixel signal output line206. A feedback capacitor307feeds the output of the amplifier circuit306back to the input of the amplifier circuit306. The ratio between the capacitance value of the capacitor305and the capacitance value of the capacitor307determines the gain of the amplifier circuit306. A switch308resets the clamp capacitor305and is controlled according to a signal pc0r. With reference to the voltage of the pixel signal output line206clamped in the clamp capacitor305when the switch308is on (set in a conductive state), an amount of change therefrom in voltage of the pixel signal output line206is amplified by a factor of the gain in the amplifier circuit306and output.

The amplifier circuit306includes, for instance, a source-grounded amplifier circuit or an operational amplifier. A load current source309is for the amplifier circuit306, and supplies the amplifier circuit306with a bias current. The current source309includes a PMOS transistor in this embodiment. The reference voltage is a power source voltage. The gate voltage of the current source transistor309is supplied from a bias line pb. A holding unit310holds the gate voltage of the current source transistor309. A sampling unit311samples the gate voltage of the current source transistor309for the holding unit310. The holding unit310holds the voltage sampled by the sampling unit311, and controls the gate voltage of the current source transistor309with reference to the reference voltage to be the sampled voltage. As exemplified inFIG. 4, the sampling unit311is, for instance, a switch401controlled according to a signal p_spbias. The holding unit310is, for instance, a capacitor402. The bias line pb and the gate of the current source transistor309are connected to each other via the switch401. The capacitor402is connected between the gate of the current source transistor309and the power source line, through which the power source voltage as the reference voltage of the current source transistor309is supplied.

Next, an operation of the solid-state imaging apparatus according to the embodiment of the present invention will be described. In the following description, the high level of a pulse (signal) is denoted by “H” and the low level of the pulse (signal) is denoted by “L”.

First Embodiment

FIG. 5is a timing chart illustrating drive timing of the solid-state imaging apparatus according to a first embodiment. In the following description, during a period of an operation of reading a signal from the pixel, the read out circuit102is not set to an off state (non-operating state).

First, each pulse will be described.

A read out start signal HD is for a certain row in the pixel region101. The read out start signal HD is supplied to the timing generator107, thereby allowing the timing generator107to generate and output each control pulse, which will be described below.

A control pulse pclip controls the switch303of the clip circuit illustrated inFIG. 3. When the control pulse pclip is “H”, the switch303is on (conductive state) and the gate voltage of the clip transistor302is set to the voltage VCLIPH. The switch304of the clip circuit is supplied with the signal pclip_b as the control pulse, which is the inverted signal of the control pulse pclip. When the control pulse pclip_b is “H” (the control pulse pclip is “L”), the switch304is on (conductive state) and the gate voltage of the clip transistor302is set to the voltage VCLIPL.

Control pulses pres are supplied to the gate of the reset transistor203of the pixel to be read, for controlling the reset transistor203. When the control pulse pres is “H”, the reset transistor203is on (conductive state).

A power source vres is connected to the drain of the reset transistor203of the pixel to be read. The high level is an arbitrary potential VRESH. The low level is an arbitrary potential VRESL.

Control pulses ptx are supplied to the gate of the transfer transistor202of the pixel to be read, for controlling the transfer transistor202. When the control pulse ptx is “H”, the transfer transistor202is on (conductive state).

Control pulses pres_sh are supplied to the gate of the reset transistor203of the pixel to be subjected to an electronic shutter, for controlling the reset transistor203. When the control pulse pres_sh is “H”, the reset transistor203is on (conductive state).

A power source vres_sh is connected to the drain of the reset transistor203of the pixel to be subjected to the electronic shutter. The high level and the low level in the power source vres_sh are the same as those of the power source vres.

Control pulses ptx_sh are supplied to the gate of the transfer transistor202of the pixel to be subjected to the electronic shutter, for controlling the transfer transistor202. When the control pulse ptx_sh is “H”, the transfer transistor202is on (conductive state).

Control pulses pc0rare applied to the switch308illustrated inFIG. 3, for resetting the clamp capacitor305of the amplifier circuit. When the control pulse pc0ris “H”, the switch308is on (conductive state) to reset the amplifier circuit.

Control pulses p_spbias control the switch401, which is the sampling unit311, to sample the potential of the bias line pb in the capacitor402, which is the holding unit310. When the control pulse p_spbias is “H”, the switch401is on (conductive state).

In the drawing, ADCD denotes an execution period of an A/D conversion operation. During “H”, the A/D conversion operation is performed. A potential VOUT1is of the image signal output line206. An output potential VOUT2is of the amplifier circuit. A saturation level LVS, and a reset level LVR are illustrated.

At time t0, the read out start signal HD becomes “L”, the timing generator106generates the respective control pulses, and an operation of reading a certain row is started.

At time t3, the control pulses pclip are set to “H”, the switch303of the clip circuit is turned on and the gate voltage of the clip transistor302is set to the voltage VCLIPH. Furthermore, the control pulses pc0rare set to “H”, and the amplifier circuit306is reset.

At this time, the gate voltage of the clip transistor302is set to the voltage VCLIPH, thereby allowing the voltage of the pixel signal output line206to be clipped by the clip transistor302, and the voltage becomes Vline1represented in following (Equation 1).
Vline1=VCLIPH−Vth−ΔVod(1)
where Vth is a threshold voltage of the clip transistor302and ΔVod is an overdrive voltage of the clip transistor302.

The amplifier circuit306is reset. Accordingly, the output of the amplifier circuit306is initialized irrespective of the voltage of the pixel signal output line206, and the current source transistor309, which is an output load of the amplifier circuit, operates in the saturation region.

At time t4, the power source vres is set to “H”; that is, the voltage of the drain of the reset transistor203on the pixel row to be read is set to the voltage VRESH.

At time t5, the control pulses pres is set to “H”, the reset transistor203on the pixel row to be read is turned on, and the potential of the floating diffusion portion205is reset to the voltage VRESH.

This operation is for allowing the voltage of the pixel signal output line206to be determined by the gate voltage of the source follower transistor204of the pixel to be read, and called a selecting operation.

At this time, the voltage of the pixel signal output line206becomes Vline2represented in following (Equation 2).
Vline2=VRESH−Vthsf−ΔVodsf(2)
where Vthsf is the threshold voltage of the source follower transistor204and ΔVodsf is the overdrive voltage of the source follower transistor204.

The magnitude relationship between the voltage Vline1of the pixel signal output line206that is clipped by the clip transistor302and the voltage Vline2of the pixel signal output line when the source follower transistor204of the pixel to be read is on is Vline1<Vline2.

At time t6, the control pulse pres is set to “L”, the reset transistor203is turned off, the floating diffusion portion205is set floating, and the selecting operation on the pixel to be read is finished.

At time t7, the control pulse pc0ris set to “L”, the switch308is turned off, and the reset operation on the amplifier circuit306is finished.

Subsequently, when the voltage of the pixel signal output line206is changed, the amount of change is amplified by the amplifier circuit306and supplied to the subsequent circuit (A/D converter in this embodiment).

At time t8, an A/D conversion process on the reset level (N signal) of the floating diffusion portion205is started. At time t9, the A/D conversion process on the N signal is finished.

At time t10, the control pulse pclip is set to “L”, the switch303is turned off and the switch304is turned on. Accordingly, the gate voltage of the clip transistor302is set to the voltage VCLIPL. The control pulse ptx is set to “H”, the transfer transistor202of the pixel to be read is turned on, and the charge accumulated by photoelectric conversion in the photoelectric conversion element201is transferred to the floating diffusion portion205. Accordingly, the voltage of the pixel signal output line206is reduced by the amount of charge accumulated in the photoelectric conversion element201. The reduced voltage is inverted and amplified by the amplifier circuit306. At this time, the amount of photoelectrically converted charge is large. Accordingly, if the output of the amplifier circuit306is saturated, the drain voltage of the current source transistor309is increased and the current source transistor309operates according to a linear operation. In this embodiment, at time t10, the output of the amplifier circuit306is saturated, and the current source transistor309operates according to the linear operation.

At time t11, the control pulse ptx is set to “L”, the transfer transistor202of the pixel to be read is turned off, and reading (transfer) of the charge photoelectrically converted by the photoelectric conversion element201to the floating diffusion portion205is finished.

At time t12, an A/D conversion process on the signal (S signal) read from the photoelectric conversion element201is started. At time t13, the A/D conversion process on the S signal is finished.

At time t14, the power source vres of the pixel to be read is set to “L”, that is, the voltage of the drain of the reset transistor203on the pixel row to be read is set to the voltage VRESL. The power source vres_sh is set to “H”, that is, the voltage of the drain of the reset transistor203of the pixel to be subjected to the electronic shutter is set to the voltage VRESH.

At time t15, the control pulse pres of the pixel to be read is set to “H”, the potential of the floating diffusion portion205is reset to VRESL, and a non-selecting operation is performed. The control pulse pres_sh is set to “H”, the reset transistor203of the pixel to be subjected to the electronic shutter is turned on, and the potential of the floating diffusion portion205is set to the voltage VRESH.

The gate voltage of the source follower transistor204of the pixel to be subjected to the electronic shutter is set to the voltage VRESH. Accordingly, the voltage of the pixel signal output line206becomes Vline3represented in following (Equation 3).
Vline3=VRESH−Vthsf−ΔVodsf(3)
where Vthsf is the threshold voltage of the source follower transistor204and ΔVodsf is the overdrive voltage of the source follower transistor204. At this time, if the pixels on a plurality of rows are to be simultaneously reset, the value of current caused to flow by one source follower transistor204decreases and the overdrive voltage ΔVodsf decreases. Accordingly, the voltage Vline3of the pixel signal output line206where the potential of the floating diffusion portion205of the pixel to be subjected to the electronic shutter is reset to the voltage VRESH becomes higher than the voltage Vline2. However, this point is not essential in this embodiment. Accordingly, for simplicity's sake, it is set such that Vline2=Vline3.

The voltage of the pixel signal output line206is increased to a level that is close to the level when the pixel to be read is subjected to the selecting operation. Accordingly, the output of the amplifier circuit306is reduced, and the current source transistor309returns to the operation in the saturation region again.

At time t16, the control pulse ptx_sh is set to “H”, the transfer transistor202of the pixel to be subjected to the electronic shutter is turned on, and the photoelectric conversion element201is reset via the reset transistor203and the transfer transistor202.

At time t17, the control pulse ptx_sh is set to “L”, the transfer transistor202of the pixel to be subjected to the electronic shutter is turned off, and resetting of the photoelectric conversion element201is finished.

At time t18, the power source vres_sh is set to “L”, that is, the voltage of the drain of the reset transistor203of the pixel row to be subjected to the electronic shutter is set to the voltage VRESL. Since the reset transistor of the pixel to be subjected to the electronic shutter is still on at this time, the potential of the floating diffusion portion205is set to voltage VRESL. Accordingly, the voltage of the pixel signal output line206is reduced again, and the output of the amplifier circuit306is saturated.

At time t19, the control pulse pres_sh is set to “L”, the reset transistor203of the pixel subjected to the electronic shutter is turned off.

Here,FIG. 5illustrates a selecting operation period T501for the pixel to be read, a reset period T502for the amplifier circuit306, a sampling period T503for the gate voltage (the potential of the bias line pb) of the current source transistor309, and a horizontal transfer period T504. The drawing further illustrates an A/D conversion period T505for the N signal, a charge read out period T506for the pixel to be read, an A/D conversion period T507for the S signal, a non-selecting operation period T508for the pixel to be read out, an electronic shutter period T509, a non-selecting operation period T510for the pixel to be subjected to the electronic shutter, and a horizontal transfer period T511.

In this embodiment, as illustrated as the period T503, before time t3at which the control pulse pc0ris set to “H”, the control pulse p_spbias is set to “H” and the switch401as the sampling unit311is turned on. Thus, writing of the potential of the bias line pb (the gate voltage of the current source transistor309) into the capacitor402as the holding unit310is started. Before time t7at which the control pulse pc0ris set to “L”, the control pulse p_spbias is set to “L”, the switch401as the sampling unit311is turned off, and writing of the potential of the bias line pb into the capacitor402as the holding unit310is finished.

That is, in the period during which the amplifier circuit306is reset (in the period during which the current source transistor309operates in the saturation region), writing of the potential of the bias line pb (the gate voltage of the current source transistor309) into the holding unit310is finished. Thus, according to the first embodiment, the potential of the bias line pb is sampled and held in a state where the current source transistor309is operating in the saturation region, thereby allowing variation in gate voltage of the current source transistor309with respect to the reference potential to be suppressed. This suppression can, in turn, suppress occurrence of line noise and a lateral smear due to difference of drop in voltage of the power source line concerning the column circuit on each row even when horizontal transfer of the pixel signal and reading of the pixel signal are concurrently performed. Accordingly, a high quality image can be provided.

Second Embodiment

FIG. 6is a timing chart illustrating driving timing of a solid-state imaging apparatus according to a second embodiment. Operations for each of control pulses and at time t0, t3to t19are analogous to those in the first embodiment. Accordingly, the description thereof is omitted.FIG. 6illustrates a selecting operation period T601for the pixel to be read, a reset period T602for amplifier circuit306, a sampling period T603for the gate voltage (the potential of the bias line pb) for the current source transistor309, and a horizontal transfer period T604. The drawing also illustrates an A/D conversion period T605for the N signal, a charge read out period T606for the pixel to be read, an A/D conversion period T607is for the S signal, and a non-selecting operation period T608for the pixel to be read. The drawing further illustrates an electronic shutter period T609, a non-selecting operation period T610for the pixel to be subjected to the electronic shutter, and a horizontal transfer period T611.

In the second embodiment, as illustrated as the period T603inFIG. 6, before time t5at which the control pulse pres is set to “H”, the control pulse p_spbias is set to “H” and the switch401as the sampling unit311is turned on. Thus, writing of the potential of the bias line pb (the gate voltage of the current source transistor309) into the capacitor402as the holding unit310is started. After the control pulses pres is set to “L” and before time t8at which A/D conversion process is started, the control pulse p_spbias is set to “L”. Thus, the switch401as the sampling unit311is turned off, and writing of the potential of the bias line pb into the capacitor402as the holding unit310is finished.

That is, the selecting operation on the pixel to be read is performed, and the voltage of the pixel signal output line206is returned to the initial state; in this state, the potential of the bias line pb (the gate voltage of the current source transistor309) is written into the holding unit310. At this time, the input level of the amplifier circuit306is in a state close to the initial state. Accordingly, the amplifier circuit306operates in a normal operating point, and the current source transistor309operates in the saturation region. Thus, according to the second embodiment, in the state where the current source transistor309is operating in the saturation region, the potential of the bias line pb is sampled and held, thereby allowing variation in gate voltage of the current source transistor309with respect to the reference potential to be suppressed. Accordingly, even when the horizontal transfer of the pixel signal and reading of the pixel signal are concurrently performed, occurrence of line noise and a lateral smear due to difference of drop in voltage of the power source line concerning the column circuit on each row can be suppressed. Accordingly, a high quality image can be provided.

Third Embodiment

FIG. 7is a timing chart illustrating driving timing of a solid-state imaging apparatus according to a third embodiment. Operations for each of control pulses and at time t0, t3to t19are analogous to those in the first embodiment. Accordingly, the description thereof is omitted.FIG. 7illustrates a selecting operation period T701for the pixel to be read, a reset period T702for the amplifier circuit306, and a horizontal transfer period T703. The drawing also illustrates an A/D conversion period T704for the N signal, a charge read out period T705for the pixel to be read, an A/D conversion period T706for the S signal, and a non-selecting operation period T707for the pixel to be read. The drawing further illustrates an electronic shutter period T708, a sampling period T709for the gate voltage of the current source transistor309(the potential of the bias line pb), a non-selecting operation period T710for the pixel to be subjected to the electronic shutter, and a horizontal transfer period T711.

In the third embodiment, as illustrated as the period T709inFIG. 7, at the substantially same time as time t15when the control pulse pres_sh is set to “H”, the control pulse p_spbias is set to “H” and the switch401as the sampling unit311is turned on. Thus, writing of the potential of the bias line pb (the gate voltage of the current source transistor309) into the capacitor402as the holding unit310is started. Before time t18at which the control pulse pres_sh is set to “L”, the control pulse p_spbias is set to “L”, the switch401as the sampling unit311is turned off, and writing of the potential of the bias line pb into the capacitor402as the holding unit310is finished.

That is, in the state where the node205of the pixel to be subjected to the electronic shutter has a high potential and where the voltage of the pixel signal output line206has a voltage close to that in the initial state, the potential of the bias line pb (the gate voltage of the current source transistor309) is written into the holding unit310. At this time, the input level of the amplifier circuit306is in a state close to the initial state. Accordingly, the amplifier circuit306operates on the normal operating point, and the current source transistor309operates in the saturation region. Thus, according to the third embodiment, in the state where the current source transistor309is operating in the saturation region, the potential of the bias line pb is sampled and held, thereby allowing variation in gate voltage of the current source transistor309to be suppressed with respect to the reference potential. Accordingly, occurrence of line noise and a lateral smear due to difference of drop in voltage of the power source line concerning the column circuit on each row even when horizontal transfer of the pixel signal and reading of the pixel signal are concurrently performed. Accordingly, a high quality image can be provided.

Fourth Embodiment

FIG. 8is a timing chart of drive timing of a solid-state imaging apparatus according to a fourth embodiment. Operations for each of control pulses and at time t0, t3to t19are analogous to those in the first embodiment. Accordingly, the description thereof is omitted.FIG. 8illustrates a selecting operation period T801for the pixel to be read, a reset period T802for the amplifier circuit306, a sampling period T803for the gate voltage of the current source transistor309(the potential of the bias line pb), and a horizontal transfer period T804. The drawing also illustrates an A/D conversion period T805for the N signal, a charge read out period T806for the pixel to be read, an A/D conversion period T807for the S signal, and a non-selecting operation period T808for the pixel to be read. The drawing further illustrates an electronic shutter period T809, a non-selecting operation period T810for the pixel to be subjected to the electronic shutter, and a horizontal transfer period T811.

In the fourth embodiment, as illustrates as the period T803inFIG. 8, before time t3at which the control pulse pclip is set to “H”, the control pulse p_spbias is set to “H” and the switch401as the sampling unit311is turned on. Thus, writing of the potential of the bias line pb (the gate voltage of the current source transistor309) into the capacitor402as the holding unit310is started. Before time t10at which the control pulse pclip is set to “L” and before time t8at which the A/D conversion process is started, the control pulse p_spbias is set to “L”. Thus, the switch401as the sampling unit311is turned off, and writing of the potential of the bias line pb into the capacitor402as the holding unit310is finished.

InFIG. 8, at time t6when the control pulse pres is set to “L”, the voltage of the pixel signal output line206is start to decrease. This decrease indicates that charge overflows from the photoelectric conversion element201to the node205when the highly bright object is imaged or the photoelectric conversion element201is irradiated with light to thereby reduce the potential of the node205. At this time, during a period when the control pulse pclip is “H”, the voltage of the pixel signal output line206is not reduced below the voltage Vline1owing to an operation of the clip transistor302.

As illustrated inFIG. 8, if the voltage of the pixel signal output line206is changed by imaging of the highly bright object at and after time t7when resetting of the amplifier circuit306is finished, the output of the amplifier circuit306is increased. However, as described above, the voltage of the pixel signal output line206is not reduced below the voltage Vline1owing to the operation of the clip transistor302. Accordingly, the output of the amplifier circuit306is not saturated, and the current source transistor309does not operate according to the linear operation.

Thus, according to the fourth embodiment, in a period during which the gate voltage of the clip transistor302is high, the potential of the bias line pb (the gate voltage of the current source transistor309) is sampled and held. Thus, variation in gate voltage with respect to the reference potential of the current source transistor309can be suppressed. Accordingly, occurrence of line noise and a lateral smear due to difference of drop in voltage of the power source line concerning the column circuit on each row even when horizontal transfer of the pixel signal and reading of the pixel signal are concurrently performed. Accordingly, a high quality image can be provided.

The first to fourth embodiments have specified rising of the control pulses p_spbias. However, the rising position is not limited thereto, and can be freely set instead. Furthermore, one time per HD has been described. More specifically, the voltage of the bias line pb is written into the holding unit310one time per HD. However, writing per HD is not necessary. For instance, writing may be performed one time per frame.

The embodiments have only described the examples of specific implementation of the present invention. The technical scope of the present invention should not be construed in a limited manner. That is, the present invention can be implemented in various forms without departing from the technical spirit or main characteristics thereof.

This application claims the benefit of Japanese Patent Application No. 2011-223340, filed Oct. 7, 2011, which is hereby incorporated by reference herein in its entirety.