NON-VOLATILE MEMORY DEVICE HAVING PN DIODE

A non-volatile memory device includes: an insulation layer; a PN diode, which is formed in a monocrystalline silicon layer, a monocrystalline germanium layer or a monocrystalline gallium arsenide layer on the insulation layer; a writing wire which is conductive and is electrically connected to the anode end of the PN diode; a memory unit on the PN diode, the memory unit being electrically connected to a cathode end of the PN diode; and a selection wire on the memory unit, the selection wire being electrically connected to the memory unit; wherein when the non-volatile memory device is selected for a data to be written into, a first current flows through the PN diode to write the data into the memory unit.

CROSS REFERENCE

The present invention claims priority to TW 110102241 filed on Jan. 21, 2021.

BACKGROUND OF THE INVENTION

Field of Invention

The present invention relates to a non-volatile memory device; particularly, it relates to such non-volatile memory device having a PN diode.

Description of Related Art

Please refer toFIG. 1AandFIG. 1B, which show a cross-sectional diagram and a three-dimensional diagram of a conventional phase change random access memory (PCRAM) device10, respectively. The PCRAM device10is a type of non-volatile memory device and can be applied in an electronic circuit to store data. When the electronic circuit is turned OFF and there is no power, the data can still be kept in a phase change area of the PCRAM device10without lost.

As shown inFIG. 1AandFIG. 1B, the PCRAM device10is formed on a substrate11. The PCRAM device10includes: a source/drain12, a bi-directional selector13, metal plugs141and142, a phase change area15, a ground wire16and a bit wire17. An addressing operation by the bi-directional selector13and the bit wire17determines a specific address of the phase change area15of the PCRAM device10, so as to write data into the address. To be more specific, a channel between the source/drain12can be conducted through controlling the bi-directional selector13, whereby a current is controlled to flow from the metal plug141, through the source/drain12, the above-mentioned channel between the source/drain12, the metal plug142and the phase change area15, to ground wire16; this current is controlled by controlling a voltage of the bit wire17, so as to change a crystallization status of the material in the phase change area15. Different crystallization statuses result in different resistances of the phase change area15, which can be used to indicate different stored data. The material in the phase change area15for example can be a GeSbTe (GST) alloy; the GST alloy has different resistances in its crystallization status and amorphous status. The PCRAM device10can write a data indicative of “1” or “0” into the phase change area15through the above-mentioned addressing operation and resistance-changing operation, which is well known to those skilled in the art, so the details thereof are not redundantly explained here.

Please refer toFIG. 2AandFIG. 2B, which show a cross-sectional diagram and a three-dimensional diagram of a conventional spin transfer torque (STT) type magnetoresistive random access memory (MRAM) device20, respectively. The STT type MRAM (abbreviated as “STT-MRAM”) device20is a type of MRAM device and is also a type of non-volatile memory device, which can be applied in an electronic circuit to store data. When the electronic circuit is turned OFF and there is no power, the data can still be kept in a magnetic area of the MRAM device20without lost. The STT-MRAM device20includes: a top electrode and a bottom electrode, both of which are made of ferromagnetic material; and an oxide layer (e.g., a magnesium oxide layer) interposed between the top electrode and the bottom electrode. In a case where a magnetization orientation between the top ferromagnetic layer and the bottom ferromagnetic layer (i.e., the top electrode and the bottom electrode) changes from a parallel orientation to an antiparallel orientation, the resistance of the MRAM device will become relatively larger. On the contrary, in a case where the magnetization orientation between the top ferromagnetic layer and the bottom ferromagnetic layer (i.e., the top electrode and the bottom electrode) changes from an antiparallel orientation to a parallel orientation, the resistance of the STT-MRAM device20will become relatively smaller. In light of this, by different resistances of the magnetic area, the STT-MRAM device20can indicate different stored data.

As shown inFIG. 2AandFIG. 2B, the STT-MRAM device20is formed on a substrate21. The STT-MRAM device20includes: a source/drain22, a bi-directional selector23, metal plugs241and242, a magnetic area25, connection wires261and262and a bit wire27. An addressing operation by the bi-directional selector23and the bit wire27determines a specific address of the magnetic area25of the STT-MRAM device20, so as to write data into the address. To be more specific, a channel between the source/drain22can be conducted through controlling the bi-directional selector23, whereby a current is controlled to flow from the magnetic area25, through the connection wire261, the metal plug241, the source/drain22, the above-mentioned channel between the source/drain22and the metal plug142, to the connection wire262; this current is controlled by controlling a voltage of the bit wire27, so as to change a magnetization orientation of the material in the magnetic area25. As described above, different magnetization orientations between the top ferromagnetic layer and the bottom ferromagnetic layer can cause the magnetic area25to have different resistances, which can be used to indicate different stored data. The material in the magnetic area25for example can be a CoFe alloy or a CoFeB alloy. The STT-MRAM device20can write a data indicative of “1” or “0” into the magnetic area25through the above-mentioned mechanism, which is well known to those skilled in the art, so the details thereof are not redundantly explained here.

Please refer toFIG. 3AandFIG. 3B, which show a cross-sectional diagram and a three-dimensional diagram of a conventional resistive random access memory (RRAM) device30, respectively. The RRAM device30is a type of non-volatile memory device and can be applied in an electronic circuit to store data. When the electronic circuit is turned OFF and there is no power, the data can still be kept in a resistance change area of the RRAM device30without lost.

As shown inFIG. 3AandFIG. 3B, the RRAM device30is formed on a substrate31. The RRAM device30includes: a source/drain32, a bi-directional selector33, metal plugs341and342, a resistance change area35, a ground wire36and a bit wire37. An addressing operation by the bi-directional selector33and the bit wire37determines a specific address of the resistance change area35of the RRAM device30, so as to write data into the address. To be more specific, a channel between the source/drain32can be conducted through controlling the bi-directional selector33, whereby a current is controlled to flow from the metal plug341, through the source/drain32, the above-mentioned channel between the source/drain32, the metal plug342, and the resistance change area35, to ground wire36; this current can be controlled through controlling a voltage of the bit wire37, so as to change a resistance in the resistance change area35, whereby the resistance change area35can have different resistances to indicate different stored data. The resistance change area35includes two metal layers and a dielectric layer which separates the two metal layers from each other. The material in the metal layers for example can be a copper telluride (CuTe) alloy or a copper germanium (CuGe) alloy. The RRAM device30can write a data indicative of “1” or “0” into the resistance change area35through the above-mentioned addressing operation and resistance-changing operation, which is well known to those skilled in the art, so the details thereof are not redundantly explained here.

In a conventional non-volatile memory device, a selector which operates for writing data into a data storage cell is a bi-directional switch, such as the above-mentioned bi-directional selectors13,23and33; the above-mentioned bi-directional selectors13,23and33are typically made of a metal oxide semiconductor (MOS) device. This results in at least the following drawbacks: first, the MOS device is required to have a source, a gate and a drain, so the area occupied by the MOS device is larger as compared to a diode (e.g., a PN diode). As a result, the conventional non-volatile memory device is fundamentally inferior to shrink its size. Second, because the MOS device has a saturation region, its conduction current is lower as compared to a diode (e.g., a PN diode), i.e., the conduction current of the MOS device is limited by its electric characteristics. Taking an MRAM device as an example, in a case where a bi-directional selector is made of a MOS device, a current to write data into a magnetic area needs to reach a level of 107A/cm2. To reach such level of 107A/cm2, as compared to a PN diode, the area required for the MOS device will be tremendously larger. Lastly, a channel of the MOS device formed in a semiconductor substrate has a relatively larger leakage current. Thus, the conventional non-volatile memory device using a MOS device as a bi-directional selector is disadvantageous in shrinking size and in increasing current per unit area.

Another relevant prior art of which the inventor is aware is a 90 nm PCRAM device having 512 MB memory, disclosed by J. H. Oh et al. in “DOI No.: 10.1109/IEDM.2006346905”. This prior art discloses a PCRAM device manufactured by a standard CMOS manufacturing process. The manufacturing process steps for this prior art PCRAM device include: first, an epitaxial silicon layer is formed on a silicon substrate heavily doped by N-type impurities. Second, a PN diode is formed in the epitaxial silicon layer, to serve as a selector of the prior art PCRAM device. In this prior art PCRAM device, because the PN diode is formed in the epitaxial silicon layer, its conduction resistance is higher than the conduction resistance of a case wherein the PN diode is formed in a monocrystalline silicon layer. Besides, the silicon substrate heavily doped cannot be effectively insulated from other devices, so this prior art PCRAM device will undesirably have a larger leakage current. Moreover, the size of this prior art PCRAM device is difficult to be shrunk.

In view of the above, to overcome the drawbacks in the prior art, the present invention proposes a non-volatile memory device having a PN diode, which occupies less area and provides higher current per unit area. Consequently and desirably, the application range of such non-volatile memory device is greatly broadened.

SUMMARY OF THE INVENTION

From one perspective, the present invention provides a non-volatile memory device, comprising: an insulation layer, which is electrically insulative; a first PN diode, which is formed in a monocrystalline silicon layer, a monocrystalline germanium layer or a monocrystalline gallium arsenide layer on the insulation layer; a first writing wire which is conductive, wherein the first writing wire is electrically connected to a first anode end of the first PN diode; a memory unit, which is located on the first PN diode, wherein the memory unit is electrically connected to a first cathode end of the first PN diode; and a selection wire which is conductive, wherein the selection wire is located on the memory unit and is electrically connected to the memory unit; wherein in a case where the non-volatile memory device is selected for a first data to be written into, a first current flows through the first PN diode, so as to write the first data into the memory unit.

From another perspective, the present invention provides a non-volatile memory circuit, comprising: a non-volatile memory device array including a plurality of non-volatile memory devices; and a control circuit configured to operably control the non-volatile memory device array so as to read from or write into the non-volatile memory devices; wherein the non-volatile memory device includes: an insulation layer, which is electrically insulative; a first PN diode, which is formed in a monocrystalline silicon layer, a monocrystalline germanium layer or a monocrystalline gallium arsenide layer on the insulation layer; a first writing wire which is conductive, wherein the first writing wire is electrically connected to a first anode end of the first PN diode; a memory unit, which is located on the first PN diode, wherein the memory unit is electrically connected to a first cathode end of the first PN diode; and a selection wire which is conductive, wherein the selection wire is located on the memory unit and is electrically connected to the memory unit; wherein in a case where the non-volatile memory device is selected for a first data to be written into, a first current flows through the first PN diode, so as to write the first data into the memory unit.

In one embodiment, the first PN diode is stacked and connected on the insulation layer.

In one embodiment, the first writing wire is stacked and connected on the insulation layer, and the first PN diode is stacked and connected on the first writing wire.

In one embodiment, the non-volatile memory device further comprises: a second PN diode, which is formed in the monocrystalline silicon layer, the monocrystalline germanium layer or the monocrystalline gallium arsenide layer on the insulation layer; a second writing wire which is conductive, wherein the second writing wire is electrically connected to a second cathode end of the second PN diode; wherein in a case where the non-volatile memory device is selected for a second data to be written into, a second current flows through the second PN diode, so as to write the second data into the memory unit.

In one embodiment, the second PN diode is stacked and connected on the insulation layer.

In one embodiment, the second writing wire is stacked and connected on the insulation layer, and the second PN diode is stacked and connected on the second writing wire.

In one embodiment, the non-volatile memory device further comprises: a first connection conduction unit, which is configured to electrically connect the memory unit to the first cathode end of the first PN diode, wherein a portion of the first connection conduction unit is stacked and connected on the first cathode end of the first PN diode; and a second connection conduction unit, which is configured to electrically connect the first connection conduction unit to the second anode end of the second PN diode, so that the memory unit is electrically connected to the second anode end of the second PN diode; wherein the first writing wire is stacked and connected on the insulation layer, and wherein the first anode end of the first PN diode is stacked and connected on the first writing wire, and wherein the first cathode end is stacked and connected on the first anode end; wherein a first portion of the second connection conduction unit is stacked and connected on the insulation layer, and

wherein a second portion of the second connection conduction unit is stacked and connected on the first portion of the second connection conduction unit, and wherein another portion of the first connection conduction unit is stacked and connected on the second portion of the second connection conduction unit; wherein the second anode end is stacked and connected on the first portion of the second connection conduction unit, and wherein the second cathode end is stacked and connected on the second anode end, and wherein the second writing wire is stacked and connected on the second cathode end; wherein the first writing wire and the first portion of the second connection conduction unit are formed by one same metal line formation process; wherein the first anode end and the second anode end are formed by one same ion implantation process or by one same epitaxial process; wherein the first cathode end and the second cathode end are formed by one same ion implantation process or by one same epitaxial process.

In one embodiment, the non-volatile memory device further comprises: a first connection conduction unit, which is electrically connected between the first PN diode and the memory unit, wherein the first connection conduction unit is configured to electrically connect the memory unit to the first cathode end of the first PN diode.

In one embodiment, the non-volatile memory device further comprises: a second connection conduction unit, which is electrically connected between the second PN diode and the memory unit, wherein the second connection conduction unit is configured to electrically connect the memory unit to the second anode end of the second PN diode.

In one embodiment, the non-volatile memory device is a phase change random access memory (PCRAM)), a magnetoresistive random access memory (MRAM) or a resistive random access memory (RRAM).

In one embodiment, the first writing wire is a metal wire.

In one embodiment, the first writing wire and the second writing wire are both metal wires.

In one embodiment, the non-volatile memory device is formed on a semiconductor-on-insulator (SOI) substrate or a semiconductor-metal-on-insulator (SMOI) substrate.

In one embodiment, the first connection conduction unit and the second writing wire are formed by one same metal line formation process.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The drawings as referred to throughout the description of the present invention are for illustration only, to show the interrelations among the layers of the device configuration, while the shapes, thicknesses, and widths are not drawn in actual scale.

Please refer toFIG. 4AandFIG. 4B, which respectively show a cross-sectional diagram and a three-dimensional diagram of a non-volatile memory device according to an embodiment of the present invention. A non-volatile memory device40according to the present invention is formed on a semiconductor substrate41. The non-volatile memory device40includes: an insulation layer42, a PN diode43, a writing wire44, a memory unit45and a selection wire46. The insulation layer42is formed on the semiconductor substrate41, wherein the insulation layer42is electrically insulative. The PN diode43is formed in a monocrystalline silicon layer, a monocrystalline germanium layer or a monocrystalline gallium arsenide layer on the insulation layer42. The PN diode43can be formed by, for example but not limited to, ion implantation process steps which respectively implants P-conductivity type impurities and N-conductivity type impurities in an anode end43aand a cathode end43bof the PN diode43in the form of accelerated ions, to form the PN diode43. The writing wire44is conductive and the writing wire44is electrically connected to the anode end43a(i.e., P-conductivity type end in this embodiment) of the PN diode43. The PN diode43has a characteristic of one-way conduction. The memory unit45is located on the PN diode43. The memory unit45is electrically connected to the cathode end43b(i.e., N-conductivity type end in this embodiment) of the PN diode43. The selection wire46is conductive, wherein the selection wire46is located on the memory unit45and is electrically connected to the memory unit45. In a case where the non-volatile memory device40is selected for a data to be written into, a first current I0flows through the PN diode43, so as to write the data into the memory unit45.

An addressing operation by the selection wire46and the writing wire44determines a specific address of the memory unit45, so as to write data into the address of. That is, by adjusting a voltage level of the selection wire46and a voltage level of the writing wire44to conduct the PN diode43, the first current I0flows from the writing wire44, through the PN diode43and the memory unit45, to the selection wire46, so as to write data into the memory unit45. According to the present invention, the memory unit45can be a phase change area of a PCRAM device, a magnetic area of an MRAM device or a resistance change area of a RRAM device. The “data” can be, for example but not limited to, an electric characteristic indicative of “1” or “0”. Such electric characteristic can be, for example but not limited to, a crystallization status, a magnetization orientation, or a resistance of a material.

Please refer toFIG. 4C, which shows a cross-sectional diagram, illustrating an embodiment as to how plural non-volatile memory devices40ofFIG. 4AandFIG. 4Bcan be arranged to connect to one selection wire46. As shown inFIG. 4C, in one embodiment, plural non-volatile memory devices40can be arranged along one same selection wire46in consecutive fashion. Thus, when there are plural selection wires46, a non-volatile memory device array is formed by plural non-volatile memory devices40arranged by rows and columns.

Please refer toFIG. 4D, which shows a cross-sectional diagram of a non-volatile memory device according to an embodiment of the present invention. This embodiment ofFIG. 4Dis different from the embodiment ofFIG. 4AandFIG. 4Bin that: in this embodiment, the writing wire44is stacked and connected on the anode end43a(i.e., P-conductivity type end in this embodiment) of the PN diode43, which is different from the writing wire44in the embodiment ofFIG. 4Awherein the writing wire44is electrically connected to the anode end43aof the PN diode43along a horizontal direction. That is, the writing wire44can be electrically connected to the anode end43aof the PN diode43at its lateral side along a horizontal direction, as shown inFIG. 4A; or, the writing wire44can be electrically connected to the anode end43aof the PN diode43along a vertical direction, as shown inFIG. 4D.

FIG. 4Fshows a schematic diagram of a non-volatile memory circuit according to an embodiment of the present invention. As shown inFIG. 4Fand also referring toFIGS. 4A-4C, the non-volatile memory circuit4includes: a non-volatile memory device array400including plural non-volatile memory devices40; and a control circuit410controlling the non-volatile memory device array400so as to read from or write into the non-volatile memory devices40; wherein the non-volatile memory device40, as shown byFIGS. 4A-4C, includes: an insulation layer42, which is electrically insulative; a PN diode43, which is formed in a monocrystalline silicon layer, a monocrystalline germanium layer or a monocrystalline gallium arsenide layer on the insulation layer42; a writing wire44which is conductive, wherein the writing wire44is electrically connected to an anode end43aof the PN diode43; a memory unit45, which is located on the PN diode43, wherein the memory unit45is electrically connected to a cathode end43bof the PN diode43; and a selection wire46which is conductive, wherein the selection wire46is located on the memory unit45and is electrically connected to the memory unit45; wherein in a case where the non-volatile memory device40is selected for a data to be written into, a current I0flows through the PN diode43, so as to write the data into the memory unit45.

The present invention is advantageous over the prior art due to at least the following reasons: first, according to the present invention, the non-volatile memory device can adopt a one-way conduction type selector (i.e., PN diode) rather than a two-way conduction type selector as adopted by the prior art. Because the PN diode occupies a relatively smaller area, the present invention can save the space occupied by the selector and the device size is smaller. Second, according to the present invention, because the non-volatile memory device can adopt a one-way conduction type selector (i.e., PN diode), the present invention will not be limited by the electric characteristics of a two-way conduction type selector (e.g., MOS device) as adopted by the prior art. As the present invention adopts for example a PN diode as the selector, because the conduction current of the PN diode is larger than the conduction current of the MOS device, the present invention can have a broader application range. Third, as compared to the prior art where a two-way conduction type selector (e.g., MOS device) is adopted, because a one-way conduction type selector (i.e., PN diode) adopted by the non-volatile memory device of the present invention is directly electrically connected to the writing wire44, the leakage current is significantly reduced. Moreover, in one embodiment, the writing wire44of the present invention can be formed on the insulation layer, which can provide good electric insulation from other conductive regions and thus has a better insulation effect than the prior arts to further reduce the leakage current. Under such implementation, for example, in one embodiment, the writing wire44of the non-volatile memory device40of this embodiment can be formed on the insulation layer42. Furthermore, when the present invention is applied to an application including plural PN diodes (the details of which will be more fully explained later), the present invention can be used to replace the bi-directional channel or multi-directional control (e.g., in an SOT-MRAM device), to ensure the currents flowing through the bi-directional channel to be substantially equal to each other.

Please refer toFIG. 5AandFIG. 5B, which respectively show a cross-sectional diagram and a three-dimensional diagram of a non-volatile memory device according to an embodiment of the present invention. A non-volatile memory device50according to the present invention is formed on a semiconductor substrate51. The non-volatile memory device50includes: an insulation layer52, a PN diode53, a writing wire54, a memory unit55, a selection wire56and a connection conduction unit57. The insulation layer52is formed on the semiconductor substrate51, wherein the insulation layer52is electrically insulative. The PN diode53is formed in a monocrystalline silicon layer a monocrystalline silicon layer, a monocrystalline germanium layer or a monocrystalline gallium arsenide layer on the insulation layer52. The PN diode43can be formed by, for example but not limited to, ion implantation process steps which respectively implants P-conductivity type impurities and N-conductivity type impurities in an anode end53aand a cathode end53bof the PN diode53in the form of accelerated ions, to form the PN diode53. The writing wire54is conductive and the writing wire54is electrically connected to the anode end53a(i.e., P-conductivity type end in this embodiment) of the PN diode53. The PN diode53has a characteristic of one-way conduction. The memory unit55is located above the PN diode53. The memory unit55is electrically connected to the cathode end53b(i.e., N-conductivity type end in this embodiment) of the PN diode53. The selection wire56is conductive, wherein the selection wire56is located on the memory unit55and is electrically connected to the memory unit55. In a case where the non-volatile memory device50is selected for a data to be written into, a first current I0flows through the PN diode53, so as to write the data into the memory unit55.

This embodiment ofFIG. 5AandFIG. 5Bis different from the embodiment ofFIG. 4AandFIG. 4Bin that: in this embodiment, the non-volatile memory device50further incudes the connection conduction unit57, which is conductive. The connection conduction unit57is configured to electrically connect the memory unit55to the cathode end53b(i.e., N-conductivity type end in this embodiment) of the PN diode53. In this embodiment, as shown inFIG. 5AandFIG. 5B, the connection conduction unit57can be, for example but not limited to, stacked and connected on the cathode end53bof the PN diode53. And, the memory unit55is stacked and connected on the connection conduction unit57.

Please refer toFIG. 6AandFIG. 6B, which respectively show a cross-sectional diagram and a three-dimensional diagram of a non-volatile memory device according to an embodiment of the present invention. A non-volatile memory device60according to the present invention is formed on a semiconductor substrate61. In this embodiment, the non-volatile memory device60includes: an insulation layer62, writing wires641and642, PN diodes631and632, a memory unit65, a selection wire66and a connection conduction unit67. The insulation layer62is formed on the semiconductor substrate61, wherein the insulation layer62is electrically insulative. The PN diode631is formed in a monocrystalline silicon layer, a monocrystalline germanium layer or a monocrystalline gallium arsenide layer on the insulation layer62. The PN diode631can be formed by, for example but not limited to, ion implantation process steps which respectively implant P-conductivity type impurities and N-conductivity type impurities in an anode end631aand a cathode end631bof the PN diode631in the form of accelerated ions, to form the PN diode631. In this embodiment, the PN diode631is stacked and connected on the insulation layer62. And, the anode end631aand the cathode end631bof the PN diode631can be, for example but not limited to, adjacently connected to each other (i.e. in contact with each other) along a horizontal direction. The non-volatile memory device60of this embodiment further includes the PN diode632. The PN diode632is formed in the monocrystalline silicon layer, the monocrystalline germanium layer or the monocrystalline arsenide layer on the insulation layer62. The PN diode632can be formed by, for example but not limited to, ion implantation process steps which respectively implant N-conductivity type impurities and P-conductivity type impurities in an cathode end632aand a anode end632bof the PN diode632in the form of accelerated ions, to form the PN diode632. In this embodiment, the PN diode632is stacked and connected on the insulation layer62. And, the cathode end632aand the anode end632bof the PN diode632can be, for example but not limited to, adjacently connected to each other (i.e. in contact with each other) along a horizontal direction.

The writing wire641is conductive and the writing wire641is electrically connected to the anode end631a(i.e., P-conductivity type end in this embodiment) of the PN diode631. In this embodiment, the writing wire641can be, for example but not limited to, stacked and connected on the anode end631a. The writing wire642is conductive and the writing wire642is electrically connected to the cathode end632a(i.e., N-conductivity type end in this embodiment) of the PN diode632. In this embodiment, the writing wire642can be, for example but not limited to, stacked and connected on the cathode end632a. The memory unit65is located above the PN diodes631and632. The memory unit65is electrically connected to the cathode end631b(i.e., N-conductivity type end in this embodiment) of the PN diode631and the anode end632b(i.e., P-conductivity type end in this embodiment) of the PN diode632by the connection conduction unit67. In this embodiment, the connection conduction unit67lies between the cathode end631band the anode end632b. In this embodiment, the selection wire66is located on the memory unit65and is electrically connected to the memory unit65. In a case where the non-volatile memory device60is selected for a data to be written into, a first current I0flows through the PN diode631, so as to write the data into the memory unit65. In a case where the non-volatile memory device60for another data to be written into, a second current I1flows through the PN diode632, so as to write the other data into the memory unit65. It is noteworthy that, in this embodiment, the flowing direction of the first current I0through the memory unit65is opposite to the flowing direction of the second current I1through the memory unit65.

In one embodiment, the PN diodes631and632are formed in the monocrystalline silicon layer, the monocrystalline germanium layer or the monocrystalline gallium arsenide layer on the insulation layer62. As shown inFIG. 6A, in one preferred embodiment, the PN diodes631and632are both two-end devices (e.g., not diode-connected MOS devices). The PN diodes631and632can be formed through doping P-conductivity type impurities and N-conductivity type impurities in the monocrystalline silicon layer, the monocrystalline germanium layer or the monocrystalline gallium arsenide layer, so as to form a PN junction for the PN diode631and a PN junction for the PN diode632. It is noteworthy that, according to the present invention, the directions of the PN junctions of the PN diodes631and632can be modified; the directions of the PN junctions of the PN diodes631and632are not limited to the implementation as shown, wherein the N-conductivity type region is at the left side ofFIG. 6A, and the P-conductivity type region is at right side ofFIG. 6A. It should be understood that such implementation in the above-mentioned preferred embodiment ofFIG. 6Ais only an illustrative example, but not for limiting the broadest scope of the present invention. In other embodiments, it is also practicable and within the scope of the present invention that the P-conductivity type region is at an upper position while the N-conductivity type region is at a lower position, or the P-conductivity type region is a lower position while the N-conductivity type region is an upper position (i.e., the P-conductivity type region and N-conductivity type region can be arranged to be in contact with each other along a vertical direction rather than along a horizontal direction). In one embodiment, the writing wires641and642are made of metal. Such metal wire can include, for example but not limited to, metal materials made of aluminum (Al), copper (Cu) or AlCu alloy. In one embodiment, the selection wires and the writing wires of the present invention can be both made of metal.

According to the present invention, in one embodiment, as shown in this embodiment, the non-volatile memory device is formed on a semiconductor-on-insulator (SOI) substrate or a semiconductor-metal-on-insulator (SMOI) substrate. SOI substrate and SMOI substrate are well known to those skilled in the art, so the details thereof are not redundantly explained here.

Please refer toFIG. 7AandFIG. 7B, which respectively show a cross-sectional diagram and a three-dimensional diagram of a non-volatile memory device according to an embodiment of the present invention.

As shown inFIG. 7A, a non-volatile memory device70according to the present invention is formed on a semiconductor substrate71. The non-volatile memory device70includes: an insulation layer72, a writing wire74, a PN diode73, a memory unit75, a selection wire76and a connection conduction unit77. The insulation layer72is formed on the semiconductor substrate71, wherein the insulation layer72is electrically insulative. The PN diode73is located on the insulation layer and is formed in a monocrystalline silicon layer, a monocrystalline germanium layer or a monocrystalline gallium arsenide layer. The writing wire74is conductive and the writing wire74is electrically connected to an anode end73a(i.e., P-conductivity type end in this embodiment) of the PN diode73. The PN diode73has a characteristic of one-way conduction. The memory unit75is located above the PN diode73. The memory unit is electrically connected to a cathode end73b(i.e., N-conductivity type end in this embodiment) of the PN diode73. The selection wire76is conductive, wherein the selection wire76is located on the memory unit75and is electrically connected to the memory unit75. In a case where the non-volatile memory device70for a data to be written into, a first current I0flows through the PN diode73, so as to write the data into the memory unit75.

This embodiment ofFIG. 7AandFIG. 7Bis different from the embodiment ofFIG. 4AandFIG. 4B, in that: in this embodiment, the non-volatile memory device70further incudes the connection conduction unit77, which is electrically connected between the PN diode73and the memory unit75. The connection conduction unit77is conductive and for example can be made of a metal wire or a metal connection plug. The connection conduction unit77is configured to electrically connect the memory unit75to the cathode end73bof the PN diode73. Additionally, in this embodiment, the cathode end73bof the PN diode73is stacked and connected on the anode end73aof the PN diode73. According to the present invention, in one embodiment, the cathode end73bof the PN diode73can be implemented as being connected to the anode end73aof the PN diode73along a horizontal direction, as shown inFIG. 4AandFIG. 4B; or, in another embodiment, the cathode end73bof the PN diode73can be implemented as being stacked and connected on the anode end73aof the PN diode73along a vertical direction, as shown inFIG. 7AandFIG. 7B.

It is noteworthy that, as the non-volatile memory device70is adopted in different applications, the first current I0can accordingly have different corresponding current flow paths. For example, referring toFIG. 7A, in a case where the non-volatile memory device70is a PCRAM device, the memory unit75is correspondingly a phase change area. Under such circumstance, as shown inFIG. 7A, the first current I0flows along a current flow path in which the first current I0flows from the PN diode73, through the connection conduction unit77to the memory unit75, to change crystallization status of the material in the memory unit75. Under such circumstance, the selection wire76for example can be electrically connected to a ground level. For another example, as shown inFIG. 7B, in a case where the non-volatile memory device70is a spin orbit torque (SOT) type MRAM device, the memory unit75is correspondingly a magnetic area. Under such circumstance, as shown inFIG. 7B, the first current I0flows along a current flow path in which the first current I0flows from the PN diode73through the connection conduction unit77without flowing through the memory unit75(as shown by the arrow inFIG. 7B), to change a magnetization orientation of the electrode in the memory unit75so as to change the resistance of the memory unit75, whereby data can be written into the memory unit75.

Please refer toFIG. 8A,FIG. 8BandFIG. 8C.FIG. 8AandFIG. 8Brespectively show a cross-sectional diagram and a three-dimensional diagram of a non-volatile memory device according to an embodiment of the present invention, while,FIG. 8Cshows an operation table corresponding to an operation ofFIG. 8AandFIG. 8B. As shown inFIG. 8AandFIG. 8B, a non-volatile memory device80according to the present invention is a three-end device and is formed on a semiconductor substrate81. The non-volatile memory device80includes: an insulation layer82, writing wires841and842, PN diodes831and832, a memory unit85, a selection wire86and a connection conduction unit87. The three ends of the non-volatile memory device80are: the writing wire841, the writing wire842and the selection wire86, respectively.

The insulation layer82is formed on the semiconductor substrate81, wherein the insulation layer82is electrically insulative. The PN diode831and the PN diode832are formed in a monocrystalline silicon layer, a monocrystalline germanium layer or a monocrystalline gallium arsenide layer on the insulation layer82. The writing wire841and the writing wire842are conductive. The writing wire841is electrically connected to an anode end831a(i.e., P-conductivity type end in this embodiment) of the PN diode831, whereas, the writing wire842is electrically connected to a cathode end832a(i.e., N-conductivity type end in this embodiment) of the PN diode832. And, the PN diode831and the PN diode832are one-way conductive. The memory unit85is located above the PN diodes831and832. The memory unit85is electrically connected to the cathode end831b(i.e., N-conductivity type end in this embodiment) of the PN diode831and the anode end832b(i.e., P-conductivity type end in this embodiment) of the PN diode832by the connection conduction unit87. The selection wire86is located on the memory unit85and is electrically connected to the memory unit85. In a case where the non-volatile memory device80is selected for a data to be written into, a first current I0flows through the PN diode831, so as to write the data into the memory unit85. In a case where the non-volatile memory device80is selected for another data to be written into, a second current I1flows through the PN diode832, so as to write the other data into the memory unit85. It is noteworthy that, in this embodiment, the flowing direction of the first current I0through the memory unit85is opposite to the flowing direction of the second current I1through the memory unit85.

In one embodiment as an example, as shown by the operation table inFIG. 8C, when an addressing operation selects the non-volatile memory device80, to write a data indicative of “0” (or “1” depending on the definition of the bit) into the memory unit85, the writing wire841is electrically connected to a writing voltage Vw and the selection wire86is electrically connected to a ground level, so as to generate the first current10. As a result, the thus generated first current I0flows from the writing wire841, through the PN diode831(wherein the P-conductivity type region is at a lower position whereas the N-conductivity type region is at an upper position), the connection conduction unit87and the memory unit85, to the selection wire86. By this current, the non-volatile memory device80can write a data indicative of “0” into the memory unit85through changing a crystallization status of a material of a phase change area, a magnetization orientation of a magnetic area or a resistance of a resistance change area in the memory unit85. In regard to the writing wire842, under such situation, the writing wire842is electrically floating. With respect to unselected non-volatile memory devices80, the writing wires841and842and the selection wire86of the unselected non-volatile memory devices80for example can also be electrically floating.

On the other hand, for another example, as shown by the operation table inFIG. 8C, when an addressing operation selects the non-volatile memory device80, to write a data indicative of “1” (or “0” depending on the definition of the bit) into the memory unit85, the selection wire86is electrically connected to the writing voltage Vw and the writing wire842is electrically connected to the ground level, so as to generate the second current I1. As a result, the thus generated second current I1flows from the selection wire86, through the memory unit85, the connection conduction unit87and the PN diode832(wherein the N-conductivity type region is at a lower position whereas the P-conductivity type region is at an upper position), to the writing wire842. By this current, the non-volatile memory device80can write a data indicative of “1” into the memory unit85through changing a crystallization status of a material of a phase change area, a magnetization orientation of a magnetic area or a resistance of a resistance change area in the memory unit85. In regard to the writing wire841, under such situation, the writing wire841is electrically floating. With respect to unselected non-volatile memory devices80, the writing wires841and842and the selection wire86of the unselected non-volatile memory devices80for example can also be electrically floating. The writing voltage Vw for example can be a positive voltage and is at least higher than a forward conduction voltage of a PN diode, so that a current can flow from an end electrically connected to the writing voltage Vw to another end electrically connected to the ground level.

In one embodiment, the non-volatile memory device80can read data stored in the memory unit85by, for example, electrically connecting the selection wire86to a reading voltage Vr, and determining that the data stored in the memory unit85is “0” or “1” according to a voltage of the writing wire842.

Please refer toFIG. 8D, which shows a three-dimensional diagram of a non-volatile memory device according to an embodiment of the present invention. This embodiment ofFIG. 8Dis different from the embodiment ofFIG. 8AandFIG. 8B, in that: in this embodiment, the connection conduction unit87includes: a first portion871, a second portion872and a third portion873. The second portion872is stacked and connected on a cathode end831b(i.e., N-conductivity type end in this embodiment) of a PN diode831. The third portion873is stacked and connected on a anode end832b(i.e., P-conductivity type end in this embodiment) of a PN diode832. The first portion871is stacked and connected on the second portion872and the third portion873, so as to electrically connect the PN diode831and the PN diode832to the memory unit85. Additionally, unlike the embodiment wherein the anode end831aand the cathode end831bof the PN diode831is connected to each other along a vertical direction and the cathode end832aand the anode end832bof the PN diode832is connected to each other along a vertical direction (as shown inFIG. 8AandFIG. 8B), in this embodiment, the anode end831aand the cathode end831bof the PN diode831are connected to each other along a horizontal direction and the cathode end832aand the anode end832bof the PN diode832are connected to each other along a horizontal direction.

Please refer toFIG. 9A,FIG. 9BandFIG. 9C.FIG. 9AandFIG. 9Brespectively show a cross-sectional diagram and a three-dimensional diagram of a non-volatile memory device according to an embodiment of the present invention, while,FIG. 9Cshows an operation table corresponding to an operation ofFIG. 9AandFIG. 9B. As shown inFIG. 9AandFIG. 9B, a non-volatile memory device90according to the present invention is formed on a semiconductor substrate91. The non-volatile memory device90includes: an insulation layer92, writing wires942and971, PN diodes931and932, a memory unit95, a selection wire96and connection conduction units94and972. This embodiment can be applied in, for example but not limited to, a STT-MRAM device or a bi-directional RRAM device.

The insulation layer92is formed on the semiconductor substrate91, wherein the insulation layer92is electrically insulative. The writing wire942and the writing wire971are conductive. The writing wire942is electrically connected to the anode end931a(i.e., P-conductivity type end in this embodiment) of the PN diode931, whereas, the writing wire971is electrically connected to the cathode end932a(i.e., N-conductivity type end in this embodiment) of the PN diode932. The PN diode931and the PN diode932are formed in a monocrystalline silicon layer, a monocrystalline germanium layer or a monocrystalline gallium arsenide layer on a first conductive layer940on the insulation layer92. The memory unit95is located above the PN diodes931and932. The memory unit95is electrically connected to the cathode end931b(i.e., N-conductivity type end in this embodiment) of the PN diode931and the anode end932b(i.e., P-conductivity type end in this embodiment) of the PN diode932. The selection wire96is located on the memory unit95and is electrically connected to the memory unit95. In a case where the non-volatile memory device90is selected for a data to be written into, a first current I0flows through the PN diode931, so as to write the data into the memory unit95. In a case where the non-volatile memory device90is selected for another data to be written into, a second current I1flows through the PN diode932, so as to write the other data into the memory unit95. It is noteworthy that, in this embodiment, the flowing direction of the first current I0through the memory unit95is opposite to the flowing direction of the second current I1through the memory unit95.

In this embodiment, the connection conduction unit972is configured to electrically connect the memory unit95to the cathode end931b(i.e., N-conductivity type end in this embodiment) of the PN diode931. A portion of the connection conduction unit972is stacked and connected on the cathode end931bof the PN diode931. The connection conduction unit94is configured to electrically connect the connection conduction unit972to the anode end932bof the PN diode932, so as to electrically connect the memory unit95to the anode end932b. The first writing wire942is stacked and connected on the insulation layer92; the anode end931ais stacked and connected on the first writing wire942; the cathode end931bis stacked and connected on the anode end931a. A first portion941of the connection conduction unit94is stacked and connected on the insulation layer92; a second portion921of the connection conduction unit94is stacked and connected on the first portion941; another portion of the connection conduction unit972is stacked and connected on the second portion921. The anode end932bof the PN diode932is stacked and connected on the first portion941; the cathode end932aof the PN diode932is stacked and connected on the anode end932b; the writing wire971is stacked and connected on the cathode end932a.

The writing wires942and a first portion941of the connection conduction unit94are formed by one same metal line formation process. The anode end931aand the anode end932bare formed by one same ion implantation process or by one same epitaxial process. The cathode end931band the cathode end932aare formed by one same ion implantation process or by one same epitaxial process. For example, the writing wires942and the first portion of the connection conduction unit941are formed in the first conductive layer940, which is located on and connected to the insulation layer92.

As one of average skill in the art readily understands, “one same metal line formation process”, refers to a process which first forms a metal layer by a metal deposition process, and next by one same lithography process wherein one same mask is adopted, a layout of metal lines in the metal layer is defined; and next the metal lines are formed by one same etching process. Besides, as one of average skill in the art readily understands, “one same ion implantation process”, refers to an impurities doping process where a single type or plural types of impurities of a same species are implanted into a same depth of a semiconductor layer in the form of accelerated ions by a same accelerating voltage. Moreover, as one of average skill in the art readily understands, “same epitaxial process”, refers to a process wherein new crystal is grown on an existing monocrystalline silicon layer, so as to create a new semiconductor layer. Such process is also named as “epitaxial growth process”. The above-mentioned three processes are well known to those skilled in the art, so the details thereof are not redundantly explained here.

In one embodiment as an example, as shown by the operation table inFIG. 9C, when an addressing operation selects the non-volatile memory device90to write a data indicative of “0” (or “1” depending on the definition of the bit) into the memory unit95, the writing wire942is electrically connected to a writing voltage Vw and the selection wire96is electrically connected to a ground level, so as to generate the first current I0. As a result, the thus generated first current I0flows from the writing wire942, through the PN diode931(where the P-conductivity type region is at a lower position whereas the N-conductivity type region is at an upper position), the connection conduction unit972and the memory unit95, to the selection wire96. By this current, the non-volatile memory device90can write a data indicative of “0” into the memory unit95through changing a crystallization status of a material of a phase change area, a magnetization orientation of a magnetic area or a resistance of a resistance change area in the memory unit95. In regard to the writing wire971, under such situation, the writing wire971is electrically floating. With respect to unselected non-volatile memory devices90, the writing wires942and971and the selection wire96of the unselected non-volatile memory devices90for example can also be electrically floating.

On the other hand, for another example, as shown by the operation table inFIG. 9C, when an addressing operation selects the non-volatile memory device90to write a data indicative of “1” (or “0” depending on the definition of the bit) into the memory unit95, the selection wire96is electrically connected to the writing voltage Vw and the writing wire971is electrically connected to the ground level, so as to generate the second current I1. As a result, the thus generated second current I1flows from the selection wire96, through the memory unit95, a second portion921and a first portion941of the connection conduction unit94, the PN diode932(where the P-conductivity type region is at a lower position whereas the N-conductivity type region is at an upper position), to the writing wire971. By this current, the non-volatile memory device90can write a data indicative of “1” into the memory unit95through changing a crystallization status of a material of a phase change area, a magnetization orientation of a magnetic area or a resistance of a resistance change area in the memory unit95. In regard to the writing wire942, under such situation, the writing wire942is electrically floating. With respect to unselected non-volatile memory devices90, the writing wires942and971and the selection wire96of the unselected non-volatile memory devices90for example can also be electrically floating.

In one embodiment, the non-volatile memory device90can read data stored in the memory unit95by electrically connecting the selection wire96to a reading voltage Vr, and determining that the data stored in the memory unit95is “0” or “1” according to a voltage of the writing wire971.

In regard to the details as to how a monocrystalline silicon layer is formed on a metal layer, please refer to US Patent Publication No. 2010/0044670A1. However, this prior art describes that it can be applied in a PCRAM device and an MRAM device, which is incorrect. An MRAM device requires two currents of different current flow directions, so this prior art having one single PN diode cannot achieve an MRAM device.

FIG. 9Dshows a schematic diagram of a non-volatile memory circuit according to an embodiment of the present invention. As shown inFIG. 9Dand also referring toFIGS. 9A-9B, the non-volatile memory circuit9includes: a non-volatile memory device array900including plural non-volatile memory devices90; and a control circuit910controlling the non-volatile memory device array900so as to read from or write into the non-volatile memory devices90; wherein the non-volatile memory device90, as shown by Fig.FIGS. 9A-9B, includes: an insulation layer92, which is electrically insulative; PN diodes931and932, which are formed in a monocrystalline silicon layer, a monocrystalline germanium layer or a monocrystalline gallium arsenide layer on the insulation layer92; writing wires942and971which are conductive, wherein the writing wires942and971are respectively electrically connected to an anode end931aof the PN diode931, and a cathode end932aof the PN diode932; a memory unit95, which is located on the PN diodes931and932, wherein the memory unit95is electrically connected to a cathode end931bof the PN diode931and an anode end932bof the PN diode932; and a selection wire96which is conductive, wherein the selection wire96is located on the memory unit95and is electrically connected to the memory unit95; wherein in a case where the non-volatile memory device90is selected for a data to be written into, a first current I0flows through the PN diode931, so as to write the data into the memory unit95, and in a case where the non-volatile memory device90is selected for another data to be written into, a second current I1flows through the PN diode932, so as to write the other data into the memory unit95. The flowing direction of the first current I0is opposite to the flowing direction of the second current I1.

Please refer toFIG. 10, which shows a three-dimensional diagram of a non-volatile memory device according to an embodiment of the present invention. This embodiment demonstrates how plural non-volatile memory devices can be arranged and connected. As shown inFIG. 10, the non-volatile memory devices90and90′ for example can share one writing wire942and one writing wire971.

Please refer toFIG. 11AandFIG. 11B.FIG. 11Ashows a three-dimensional diagram of a non-volatile memory device according to an embodiment of the present invention, while,FIG. 11Bshows an operation table corresponding to an operation ofFIG. 11A. As shown inFIG. 11A, a non-volatile memory device100according to the present invention is a five end device and is formed on a semiconductor substrate (not shown; please refer to other embodiments, such as the semiconductor substrate91shown inFIG. 9A). The non-volatile memory device100includes: an insulation layer102, writing wires1041,1042,1072and1073, PN diodes1031,1032,1033and1034, conductive plugs1021and1022, a memory unit105, a selection wire106and connection conduction units1071,1043and1044. The five ends of non-volatile memory device100are the writing wires1041and1042and the selection wire106.

The insulation layer102is formed on the semiconductor substrate (not shown), wherein the insulation layer102is electrically insulative. The writing wires1041,1042,1072and1073are conductive. The PN diodes1031,1032,1033and1034have a characteristic of one-way conduction, which can be, for example but not limited to, PN diodes shown inFIG. 11A. The memory unit105is located above the PN diodes1031,1032,1033and1034and the connection conduction unit1071. The selection wire106is located on the memory unit105and is electrically connected to the memory unit105. In a case where the non-volatile memory device100is selected for a data to be written into, a first current I0flows through the PN diodes1031and1032, so as to write the data into the memory unit105. In a case where the non-volatile memory device100is selected for another data to be written into, a second current I1flows through the PN diodes1033and1034, so as to write the other data into the memory unit105. This embodiment can be applied, for example but not limited to, a spin orbit torque (SOT) type MRAM (SOT-MRAM) device.

In one embodiment as an example, as shown by the operation table inFIG. 11B, when an addressing operation selects the non-volatile memory device100to write a data indicative of “0” (or “1” depending on the definition of the bit) into the memory unit105, the writing wire1041is electrically connected to a writing voltage Vw and the writing wire1072is electrically connected to a ground level, so as to generate the first current I0. As a result, the thus generated first current I0flows from the writing wire1041, through the PN diode1031(where the P-conductivity type region is at a lower position whereas the N-conductivity type region is at an upper position), the connection conduction unit1071, the conductive plug1021, the connection conduction unit1043, and the PN diode1032(where the P-conductivity type region is at a lower position whereas the N-conductivity type region is at an upper position), to the writing wire1072. Because the first current I0flows through the connection conduction unit1071electrically connected to the electrode of the memory unit105, a magnetization orientation of a magnetic area in the memory unit105is changed, whereby a data indicative of “0” is written into the memory unit105. In regard to the writing wires1042and1073and the selection wire106, under such situation, the writing wires1042and1073and the selection wire106are electrically floating. With respect to unselected non-volatile memory devices100, the writing wires1041,1042,1072and1073and the selection wire106of the unselected non-volatile memory devices100for example can also be electrically floating.

On the other hand, for another example, as shown by the operation table inFIG. 11B, when an addressing operation selects the non-volatile memory device100, to write a data indicative of “1” (or “0” depending on the definition of the bit) into the memory unit105, the writing wire1042is electrically connected to the writing voltage Vw and the writing wire1073is electrically connected to the ground level, so as to generate the second current I1. As a result, the thus generated second current I1flows from the writing wire1042, through the PN diode1033(where the P-conductivity type region is at a lower position whereas the N-conductivity type region is at an upper position), through the connection conduction unit1071, the conductive plug1022, the connection conduction unit1044, and the PN diode1034(where the P-conductivity type region is at a lower position whereas the N-conductivity type region is at an upper position), to the writing wire1073. Because the second current I1flows through the connection conduction unit1071electrically connected to the electrode of the memory unit105a magnetization orientation of a magnetic area in the memory unit105is changed, but the direction along which the second current I1flows through the memory unit105is opposite to the direction along which the first current I0flows through the memory unit105to write a data indicative of “0”, so a data indicative of “1” is written into the memory unit105. In regard to the writing wires1041and1072and the selection wire106, under such situation, the writing wires1041and1072and the selection wire106are electrically floating. With respect to unselected non-volatile memory devices100, the writing wires1041,1042,1072and1073and the selection wire106of the unselected non-volatile memory devices100for example can also be electrically floating.

In one embodiment, the non-volatile memory device100can read data stored in the memory unit105by electrically connecting the selection wire106to a reading voltage Vr, and determining that the data stored in the memory unit105is “0” or “1” according to a voltage of the writing wire1042.

FIG. 11Cshows a schematic diagram of a non-volatile memory circuit according to an embodiment of the present invention. As shown inFIG. 11Cand also referring toFIG. 11A, the non-volatile memory circuit101includes: a non-volatile memory device array1000including plural non-volatile memory devices100; and a control circuit1100controlling the non-volatile memory device array1000so as to read from or write into the non-volatile memory devices100; wherein the non-volatile memory device100, as shown byFIG. 11A, includes: an insulation layer102, which is electrically insulative; PN diodes1031,1032,1033and1034, which are formed in a monocrystalline silicon layer, a monocrystalline germanium layer or a monocrystalline gallium arsenide layer on the insulation layer102; writing wires1041,1042,1072and1073which are conductive, wherein the writing wires1041,1042,1072and1073are respectively electrically connected to an anode end of the PN diode1031, an anode end of the PN diode1033, a cathode end of the PN diode1032, and a cathode end of the PN diode1034; a memory unit105, which is located on the PN diodes1031,1032,1033and1034, wherein the memory unit105is electrically connected to the cathode ends of the PN diodes1031and1033; and a selection wire106which is conductive, wherein the selection wire106is located on the memory unit105and is electrically connected to the memory unit105; wherein in a case where the non-volatile memory device100is selected for a data to be written into, a first current I0flows through the PN diodes1031and1033, so as to write the data into the memory unit105, and in a case where the non-volatile memory device100is selected for another data to be written into, a second current I1flows through the PN diodes1032and1034, so as to write the other data into the memory unit105. The flowing direction of the first current I0is opposite to the flowing direction of the second current I1.

The present invention has been described in considerable detail with reference to certain preferred embodiments thereof. It should be understood that the description is for illustrative purpose, not for limiting the broadest scope of the present invention. An embodiment or a claim of the present invention does not need to achieve all the objectives or advantages of the present invention. The title and abstract are provided for assisting searches but not for limiting the scope of the present invention. Those skilled in this art can readily conceive variations and modifications within the spirit of the present invention. For example, a manufacturing process or a structure which does not substantially influence the primary function of the device can be inserted between any two structures in the shown embodiments. It is not limited for each of the embodiments described hereinbefore to be used alone; under the spirit of the present invention, two or more of the embodiments described hereinbefore can be used in combination. For example, two or more of the embodiments can be used together, or, a part of one embodiment can be used to replace a corresponding part of another embodiment. In view of the foregoing, the spirit of the present invention should cover all such and other modifications and variations, which should be interpreted to fall within the scope of the following claims and their equivalents.