Clock embedded differential data receiving system for ternary lines differential signaling

A clock embedded differential data receiving system for ternary lines differential signaling. The clock embedded differential data receiving system includes a monitoring portion which monitors voltage levels of first, second and third transfer signals to generate a clock signal, a first pre-data and a second pre-data, a data generating portion which detects the first pre-data and the second pre-data in response to a sampling control signal, and generates an output data group with decoding of the first pre-data and the second pre-data, and a timing controller to delay the transition time point of the clock signal with a delay phase which generates the sampling control signal.

This application claims priority to Korean Patent Application No. 10-2007-0101020, filed on Oct. 8, 2007, all of the benefits accruing therefrom under 35 U.S.C. §119, the contents of which in its entirety is incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a differential data receiving system, more particularly, to a clock embedded differential data receiving system for ternary lines differential signaling.

2. Description of the Related Art

Differential signaling is widely used for transferring data. The differential signaling is a conventional method for transferring differential data. The differential data is a fair of plus (+) signal and minus (−) signal. The differential signaling has advantages in low electromagnetic interference (EMI), high noise immunity and high speed, comparing with single-ended signaling. However, the number of the transfer lines is increased for the differential signaling. Accordingly, the differential signaling has a disadvantage in layout area.

Therefore, many methods of differential signaling are developed to reduce the number of the transfer lines. And, Ternary Lines Differential Signaling (TDLS) is one of them.

According to TDLS, a ternary set is consisted of ternary lines. With TDLS, the number of transferred data bit per transfer line is increased.

However, there is no differential data receiving system to efficiently receive the differential data transferred by TDLS.

BRIEF SUMMARY OF THE INVENTION

The present invention has made an effort to solve the above stated problems, and an aspect of the present invention provides a differential data receiving system to receive the differential data transferred by TDLS.

According to an exemplary embodiment, the present invention provides a clock embedded differential data receiving system for receiving first, second and third transfer signals transferred via ternary lines. The clock embedded differential data receiving system includes a monitoring portion which monitors voltage levels of the first, second and third transfer signals, and generates a clock signal, a first pre-data and a second pre-data, wherein the clock signal includes a logic state according to a comparison of the voltage levels between the first transfer signal and the second transfer signal, and wherein the first pre-data includes a logic state according to a comparison of the voltage levels between the second transfer signal and the third transfer signal, and wherein the second pre-data includes a logic state according to a comparison of the voltage levels between the third transfer signal and the first transfer signal, a data generating portion which detects the first pre-data and the second pre-data in response to a sampling control signal, and generates an output data group which decodes the first pre-data and the second pre-data, and a timing controller which delays the transition time point of the clock signal with a delay phase and generates the sampling control signal.

DESCRIPTION OF THE INVENTION

It will be understood that when an element is referred to as being “on” another element, it can be directly on the other element or intervening elements may be present therebetween. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. It will be understood that, although the terms first, second, third etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

FIG. 1is a diagram of an exemplary embodiment a clock embedded differential data receiving system according to the present invention. Referring toFIG. 1, the clock embedded differential data receiving system of the present invention receives first, second and third transfer signals VST1to VST3transferred via ternary lines LTR1, LTR2and LTR3, respectively.

At this time, according to an exemplary embodiment, six data states can be assigned based on a comparison of the voltage levels in the three transfer signals VST1to VST3. If a relation of the voltage levels in two transfer signals is set, the number of the data states to be assigned is 3.

According to an exemplary embodiment, when a clock signal VCLK includes a logic state according to a relation of the voltage levels in two transfer signals VST1and VST2, the number of the data states to be assigned per data period is 3. Therefore, the number of the data states to be assigned per two data period is 9.

FIGS. 2A and 2Bare diagrams of an exemplary embodiment for explaining a clock embedded differential data transferred by TDLS, according to the present invention. Referring toFIGS. 2A and 2B, according to an exemplary embodiment, a relation of the voltage levels in two transfer signals VST1and VST2is used for the clock signal VCLK. Therefore, the relation of the voltage levels in two transfer signals VST1and VST2during a first data period PE1and a second data period PE2is set.

According to an exemplary embodiment of the present invention, a data period is the unit period in which the relation of the voltage levels in three transfer signals is maintained.

InFIGS. 2A and 2B, according to an exemplary embodiment, during the first data period PE1, the voltage level of the first transfer signal VST1is higher than that of the second transfer signal VST2. And, during the second data period PE2, the voltage level of the first transfer signal VST1is lower than that of the second transfer signal VST2.

FromFIGS. 2A and 2B, the order of the voltage levels in three transfer signals VST1, VST2and VST3is easily understood for corresponding data state. For example, at the data state S123, the voltage level of the first transfer signal VST1is higher than that of the second transfer signal VST2, and the voltage level of the second transfer signal VST2is higher than that of the third transfer signal VST3.

Further, according to an exemplary embodiment, at the data state S231, the voltage level of the second transfer signal VST2is higher than that of the third transfer signal VST3, and the voltage level of the third transfer signal VST3is higher than that of the first transfer signal VST1.

Further, the values of the first, second and third bit data are easily understood for corresponding data states during the first period PE1and the second period PE2.

According to an exemplary embodiment, when the data state during the first period PE1is ‘S123’ and the data state during the second period PE2is ‘S231’, the values of the first, second and third bit data are ‘011’. Further, when the data state during the first period PE1is ‘S132’ and the data state during the second period PE2is ‘S321’, the values of the first to third bit data are ‘110’.

Particularly, according to another exemplary embodiment, a special case SPST is supposed. For the special case SPST, the data state during the first period PE1is ‘S132’ and the data state during the second period PE2is ‘S231’. That is, for the special case SPST, the voltage level of the first transfer signal VST1is between the voltage levels of the second transfer signal VST2and the third transfer signal VST3during both of the first period PE1and the second period PE2.

Consequently, using the relation of the voltage levels in three transfer signals VST1, VST2and VST3during the two data periods, three bit data can be transferred with the clock signal. In the current exemplary embodiment, the special state SPST is provided which is used for a special purpose.

Returning toFIG. 1, the clock embedded differential data receiving system of the present invention further includes a monitoring portion100, a data generating portion200and a timing controller300.

According to an exemplary embodiment, the monitoring portion100monitors the voltage levels of the first, second and third transfer signals VST1, VST2and VST3, and generates the clock signal VCLK, a first pre-data PRDAT1and a second pre-data PRDAT2.

At this time, the logic state of the clock signal VCLK is determined according to a comparison of the voltage levels between the first transfer signal VST1and the second transfer signal VST2. The logic state of the first pre-data PRDAT1is determined according to a comparison of the voltage levels between the second transfer signal VST2and the third transfer signal. VST3, and the logic state of the second pre-data PRDAT2is determined according to a comparison of the voltage levels between the third transfer signal VST3and the first transfer signal VST1.

In the current exemplary embodiment, the monitoring portion100includes a first comparator110, a second comparator120and a third comparator130. The first comparator110compares the voltage level of the first transfer signal VST1with that of the second transfer signal VST2, and generates the clock signal VCLK. When the voltage level of the first transfer signal VST1is higher than that of the second transfer signal VST2, the clock signal VCLK is “H”. In contrast, when the voltage level of the first transfer signal VST1is lower than that of the second transfer signal VST2, the clock signal is “L”.

The second comparator120compares the voltage level of the second transfer signal VST2with that of the third transfer signal VST3, and generates the first pre-data PRDAT1. According to an exemplary embodiment, when the voltage level of the second transfer signal VST2is higher than that of the third transfer signal VST3, the first pre-data PRDAT1is “H”. In contrast, when the voltage level of the second transfer signal VST2is lower than that of the third transfer signal VST3, the first pre-data PRDAT1is “L”.

According to an exemplary embodiment, the third comparator130compares the voltage level of the third transfer signal VST3with that of the first transfer signal VST1, and generates the second pre-data PRDAT2. When the voltage level of the third transfer signal VST3is higher than that of the first transfer signal VST1, the second pre-data PRDAT2is “H”. In contrast, when the voltage level of the third transfer signal VST3is lower than that of the first transfer signal VST1, the second pre-data PRDAT2is “L”.

The data generating portion200detects the first pre-data PRDAT1and the second pre-data PRDAT2in response to a sampling control signal VSAM. That is, the data generating portion200detects the logic states the first pre-data PRDAT1and the second pre-data PRDAT2at the transition of the sampling control signal VSAM. In the current exemplary embodiment, the sampling control signal VSAM provided from the timing controller300is generated by delaying the clock signal VCLK with a delay phase Pd.

According to an exemplary embodiment, the delay phase Pd is approximately π/2. However, in another exemplary embodiment, the delay phase Pd can be approximately π/3.

The data generating portion200generates an output data group GDOUT with decoding the first pre-data PRDAT1and the second pre-data PRDAT2. In this exemplary embodiment, the output data group GDOUT includes 3 data bits, which are first, second and third output data DATA1, DATA2and DATA3.

In the current exemplary embodiment, the data generating portion200generates a special confirm signal SC with decoding the first pre-data PRDAT1and the second pre-data PRDAT2.

The special confirm signal SC is activated when the voltage levels of the first, second and third transfer signals VST1, VST2and VST3are in a special order. That is, the special confirm signal SC is activated at the special state SPST.

According to an exemplary embodiment, the data generating portion200includes a data sampling unit210and a decoder230. The data sampling unit210generates a first leading data LEDAT1, a second leading data LEDAT2, a first legging data LGDAT1and a second legging data LGDAT2. According to the current exemplary embodiment, the value of the first leading data LEDAT1is determined by the value of the first pre-data PRDAT1at a leading transition of the sampling control signal VSAM. Further, the value of the second leading data LEDAT2is determined by the value of the second pre-data PRDAT2at the leading transition of the sampling control signal VSAM. In addition, the value of the first legging data LGDAT1is determined by the value of the first pre-data PRDAT1at the legging transition of the sampling control signal VSAM. Also, the value of the second legging data LGDAT2is determined by the value of the second pre-data PRDAT2at the legging transition of the sampling control signal VSAM.

In the current exemplary embodiment, the leading transition of the sampling control signal VSAM means the transition from “L” to “H. Further, the legging transition of the sampling control signal VSAM means the transition from “H” to “L”.

According to an exemplary embodiment, the data sampling unit210includes a first flip-flop211, a second flip-flop212, a third flip-flop213, a fourth flip-flop214, a fifth flip-flop215and a sixth flip-flop216.

In the current exemplary embodiment, the first flip-flop211generates a first flip output FDAT1. The first flip output FDAT1depends on the first pre-data PRDAT1at the leading transition of the sampling control signal VSAM of the first data period PE1.

The second flip-flop212generates a second flip output FDAT2. The second flip output FDAT2depends on the second pre-data PRDAT2at the leading transition of the sampling control signal VSAM of the first data period PE1.

The third flip-flop213generates the first leading data LEDAT1. The first leading data LEDAT1depends on the first flip output FDAT1at the legging transition of the sampling control signal VSAM of the second data period PE2.

The fourth flip-flop214generates the second leading data LEDAT2. The second leading data LEDAT2depends on the second flip output FDAT1at the legging transition of the sampling control signal VSAM of the second data period PE2.

The fifth flip-flop215generates the first legging data LGDAT1. The first legging data LGDAT1depends on the first pre-data PRDAT1at the legging transition of the sampling control signal VSAM of the second data period PE2.

The sixth flip-flop216generates the second legging data LGDAT2. The second legging data LGDAT2depends on the second pre-data at the legging transition of the sampling control signal VSAM of the second data period PE2.

Therefore, all of the first leading data LEDAT1, the second leading data LEDAT2, the first legging data LGDAT1and the second legging data LGDAT2are generated in response to the legging transition of the sampling control signal VSAM of the second data period PE2.

Meanwhile, the decoder230decodes the first leading data LEDAT1, the second leading data LEDAT2, the first legging data LGDAT1and the second legging data LGDAT2in order to generate the output data group GDOUT, which includes the first, second and third output data DATA1, DATA2and DATA3. The values of the first, second and third output data DATA1, DATA2and DATA3can be easily understood fromFIG. 2AandFIG. 2B.

Further, according to an exemplary embodiment, the decoder230generates the special confirm signal SC.

FIG. 3is a diagram of an exemplary embodiment for explaining the operation of the main signal inFIG. 1, on the condition of the special state, according to the present invention.

Referring toFIG. 3while referencingFIG. 1, during the first data period PE1, the first, second and third transfer signal VST1, VST2and VST3in the state ‘S132’ are transferred. Then, the clock signal VCLK and the first pre-data PRDAT1are “H”, and the second pre-data PRDAT2is “L”.

And, the sampling signal VSAM is transited to logic “H” at the time t2. In the current exemplary embodiment, the time t2is the delayed time with the delay phase Pd from the leading transition time t1of the clock signal VCLK. At this time, the first flip output FDAT1and the second flip output FDAT2are generated. Further, the logic state of the first flip output FDAT1is same as that of the first pre-data PRDAT1. The logic state of the second flip output FDAT2is same as that of the second pre-data PRDAT2.

That is, the clock signal VCLK is simultaneously transited with the first flip output FDAT1and the second pre-data PRDAT2. Meanwhile, the transition time of the sampling signal VSAM is delayed from the transition time of the first flip output FDAT1and the second pre-data PRDAT2.

In the current exemplary embodiment, a first flip-flop211in the data generation portion200generates the first flip output FDAT1in response to the sampling signal VSAM, not to the clock signal VCLK. Also, a second flip-flop212in the data generation portion200generates the second flip output FDAT2with responding to the sampling signal VSAM, not to the clock signal VCLK.

Therefore, the sampling margin is increased for sampling the first pre-data PRDAT1and the second pre-data PRDAT2by the first flip-flop211and the second flip-flop212.

Continuously referring toFIG. 3while referencingFIG. 1, during the second data period PE2, the first, second and third transfer signal VST1, VST2and VST3in the state ‘S231’ are transferred. Then, the clock signal VCLK and the first pre-data PRDAT1are “L”, and the second pre-data PRDAT2is Further, the sampling signal VSAM is transited to logic “L” at the time t4. In the current exemplary embodiment, the time t4is the delayed time with the delay phase Pd from the legging transition time t3of the clock signal VCLK. At this time, the first leading data LEDAT1and the second leading data LEDAT2are generated. And, the logic state of the first leading data LEDAT1is same as that of the first flip output FDAT1. The logic state of the leading data LEDAT2is same as that of the second flip output FDAT2.

Also, the first legging data LGDAT1and the second legging data LGDAT2are generated in response to the transition to “L” of the sampling signal VSAM. And, the logic state of the first legging data LGDAT1is same as that of the first pre-data PRDA1. The logic state of the legging data LGDAT2is same as that of the second pre-data PRDAT2.

In the current exemplary embodiment, a fifth flip-flop215in the data generation portion200generates the first legging data LGDAT1in response to the sampling signal VSAM, not to the clock signal VCLK. Also, a sixth flip-flop216in the data generation portion200generates the second legging data LGDAT2in response to the sampling signal VSAM, not to the clock signal VCLK.

Therefore, the sampling margin is increased for sampling the first pre-data PRDAT1and the second pre-data PRDAT2by the fifth flip-flop215and the sixth flip-flop216.

Then, according to an exemplary embodiment, the special confirm signal SC is generated with decoding the first leading data LEDAT1, the second leading data LEDAT2, the first legging data LGDAT1and the second legging data LGDAT2. In case ofFIG. 3, the special confirm signal SC activated to “H”.

Thus, in the clock embedded differential data receiving system according to an exemplary embodiment of the present invention, 3-bits data can be received with the clock signal VCLK. That is, the clock embedded differential data receiving system of the present invention receives 3-bits data with the clock signal VCLK using the voltage levels of the first, second and third transfer signal VST1, VST2and VST3during the successive two data period.

Referring back toFIG. 1, the timing controller300delays the transition time point of the clock signal VCLK with a delay phase Pd to generate the sampling control signal VSAM.

In the current exemplary embodiment, the timing controller300is enabled with responding to the activation of the special confirm signal SC. When the special confirm signal SC is activated, that is, when the first, second and third transfer signals VST1, VST2and VST3are in the special state SPST, the duty of the clock signal VCLK is most stable. Therefore, in the current exemplary embodiment, when the timing controller300is enabled in response to the activation of the special confirm signal SC, the sampling margin is improved.

FIG. 4is a diagram of an exemplary embodiment of the timing controller ofFIG. 1. The timing controller ofFIG. 4includes a delay unit410, a logic confirming unit430and a sampling signal generating unit450. The delay unit410delays the clock signal VCLK to generate a plurality of delay signals FDEL_1through FDEL_n. In the current exemplary embodiment, the delay signals FDEL_1through FDEL_n are sequentially delayed for the clock signal VCLK. According to the present invention, the number of delay signals is not limited to a particular number, and may vary as necessary.

The logic confirming unit430includes a plurality of flip-flops431_1˜431—n. In the current exemplary embodiment, the construction of each of the flip-flops431_1˜431—nis same as that of the flip-flop211-216of the data sampling unit210.

Each of the flip-flops431_1˜431—nreceives the clock signal VCLK as a clock input node, and receives the corresponding delay signal FDEL_1through FDEL_n as an input node. And, each of the flip-flops431_1˜431—ngenerates the corresponding logic confirming signal FLCF_1to FLCF_n.

Therefore, according to an exemplary embodiment, the logic states of the logic confirming signals FLCF_1through FLCF_n depend on the corresponding delay signal FDEL_1through FDEL_n, which is received as the input node of the corresponding flip-flop431_1˜431—n. That is, the logic states of the logic confirming signals FLCF_1through FLCF_n depend on the delayed amount of the corresponding delay signal FDEL_1through FDEL_n for the clock signal VCLK.

According to an exemplary embodiment, when the delayed amount of the corresponding delay signal FDEL_1through FDEL_n for the clock signal VCLK is less than a critical amount, then, the logic state of the corresponding logic confirming signal FLCF_1through FLCF_n is same as that of the clock signal VCLK before transitioning. The delayed amount of the corresponding delay signal FDEL_1through FDEL_n for the clock signal VCLK is more than the critical amount, the logic state of the corresponding logic confirming signal FLCF_1through FLCF_n is same as that of the clock signal VCLK after transitioning.

The sampling signal generating unit450detects the logic states of the logic confirming signals FLCF_1through FLCF_n to generate the sampling signal VSAM. Concretely, the sampling signal generating unit450selects one of the delay signals FDEL_1through FDEL_n according to an edge confirming signal VEC, and the selected delay signal FDEL_1through FDEL_n is generated as the sampling signal VSAM. At this time, the edge confirming signal VEC is the selected one of the logic confirming signals FLCF_1through FLCF_n. Further, the logic state of the logic confirming signal FLCF_1through FLCF_n which is selected as the edge confirming signal VEC is different from that of adjacent logic confirming signal FLCF_1through FLCF_n.

And, the sampling signal generating unit450generates the sampling signal VSAM with selecting one of the delay signals FDEL_1through FDEL_n according to the edge confirming signal VEC.

In the current exemplary embodiment, the sampling signal generating unit450is enabled in response to the special confirm signal SC.

The mux453selects one of the delay signals FDEL_1through FDEL_n using the edge confirm signal VEC. And, the selected delay signals FDEL_1through FDEL_n is generated as the sampling signal VSAM.

According to an exemplary embodiment, the phase difference between the selected delay signals FDEL_1through FDEL_n and the edge confirm signal VEC is approximately π/2. However, in another exemplary embodiment, the phase difference between the selected delay signals FDEL_1through FDEL_n and the edge confirm signal VEC can be approximately π/3.

FIG. 5is another exemplary embodiment of the timing controller ofFIG. 1according to the present invention. The timing controller ofFIG. 5includes a delay unit510and a bias signal generating unit530.

The delay unit510delays the clock signal VCLK, and thereby generates a phase detect signal VDEPH1and the sampling signal VSAM. At this time, the phase difference between the phase detect signal VDEPH1and the clock signal VCLK is controlled by the voltage level of a bias signal VBIAS1. According to an exemplary embodiment, the bias signal VBIAS1is provided from the bias signal generating unit530.

Referring toFIG. 5, when the phase detect signal VDEPH1includes a first phase difference PHDA1for the clock signal, the sampling signal VSAM includes a second phase difference PHDA2for the clock signal VCLK. In the current exemplary embodiment, the first phase difference PHDA1is approximately π, and the second phase difference PHDA2is approximately ½ of the first phase difference PHDA1.

According to an exemplary embodiment, the bias signal generating unit530compares the phase of the phase detect signal VDEPH1with that of the clock signal VCLK, and generates the bias signal VBIAS1. The voltage level of the bias signal VBIAS1depends on the phase difference between the phase detect signal VDEPH1and the clock signal VCLK. The bias signal VBIAS1is controlled, so that the phase detect signal VDEPH1includes the first phase difference PHDA1for the clock signal VCLK.

In the current exemplary embodiment, the phase difference between the delay signals FDEL_1through FDEL_n selected as the sampling signal VSAM and the edge confirm signal VEC is approximately π/2 or π/3.

In the current exemplary embodiment, the bias signal generating unit530is enabled responding to the special confirm signal SC.

As shown inFIG. 5, the bias signal generating unit530includes a bias generator531and a phase controller533. The bias generator531generates the bias signal VBIAS1. And, the voltage of the bias signal VBIAS1is controlled in response to a detection control signal VCOM.

The phase controller533generates the detection control signal VCOM when detecting the phase difference between the phase detect signal VDEPH1and the clock signal VCLK. And, the detection control signal VCOM includes information for whether the phase difference of the phase detect signal VDEPH1to the clock signal VCLK is larger that the first phase difference PHDA1.

In the current exemplary embodiment, the phase controller533is enabled in response to the special confirm signal SC.

FIG. 6is a diagram of another exemplary embodiment of the timing controller ofFIG. 1, according to the present invention. The timing controller ofFIG. 6includes a delay unit610, a mux630and a phase detection unit650.

The delay unit610delays the clock signal VCLK to generate a plurality of delay signals KDEL_1˜KDEL_n. And, each of the delay signals KDEL_1˜KDEL_n is sequentially delayed for the clock signal VCLK.

The mux630selects one of the delay signals KDEL_1through KDEL_n as the sampling signal VSAM according to a detection control signal VDTC. The mux630selects another one of the delay signals. KDEL_1through KDEL_n as a phase detect signal VDEPH2. When the phase detect signal VDEPH2includes a first phase difference PHDB1for the clock signal VCLK, the sampling signal VSAM includes a second phase difference PHDB2for the clock signal VCLK. According to an exemplary embodiment, the first phase difference PHDB1is approximately π, and the second phase difference PHDB2is approximately ½ of the first phase difference PHDB1.

The phase detection unit650compares the phase of the phase detect signal VDEPH2with that of the clock signal VCLK, and generates the detection control signal VDTC. That is, according to the detection control signal VDTC, the mux630controlled to select the delay signal, which has the first phase difference PHDB1for the clock signal VCLK, as the phase detect signal VDEPH2.

In the current exemplary embodiment, the phase detection unit650is enabled in response to the special confirm signal SC.

FIG. 7is a diagram of another exemplary embodiment of the timing controller ofFIG. 1, according to the present invention. The timing controller ofFIG. 7includes a delay unit710.

The delay unit710delays the clock signal VCLK in order to generate the sampling signal VSAM.

According to the clock embedded differential data receiving system of the present invention, three bit data can be transferred with the clock signal by ternary lines differential signaling. That is, using the relation of the voltage levels in three transfer signals VST1, VST2and VST3during the two data periods, three bit data can be transferred with the clock signal by ternary lines differential signaling.

Also, the data generating portion200is controlled to sample the first pre-data PRDAT1and the second pre-data PRDAT2in response to the leading and legging transition of the sampling control signal VSAM.

Therefore, according to an exemplary embodiment, in the clock embedded differential data receiving system of the present invention, the sampling margin is increased for sampling the first pre-data PRDAT1and the second pre-data PRDAT2.

The exemplary embodiments above are described such that the timing controller, the edge detector, the phase controller and the phase detection unit are enabled in response to the special confirm signal.

Otherwise, it is available for the present invention to be embodied in the feature that the timing controller, the edge detector, the phase controller and the phase detection unit are enabled at every data period without responding to the special confirm signal.

While the present invention has been shown and described with reference to some exemplary embodiments thereof, it should be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the appending claims.