Circuit device with serial bus isolation

In a particular embodiment, a circuit device includes a first circuit having a first plurality of serial terminals including a first data receive terminal and a first data transmit terminal. The first plurality of serial terminals is communicatively coupled to a particular circuit via isolation circuitry to communicate first serial data. The circuit device further includes a second circuit having a second plurality of serial terminals including a second data receive terminal coupled to the first data transmit terminal and including a second data transmit terminal coupled to the first data receive terminal to communicate second serial data to the particular circuit via the first data receive and transmit terminals.

FIELD

The present disclosure is generally related to a circuit device with serial bus isolation, and more particularly, but not by limitation to, a subscriber line interface circuit having shared serial bus isolation.

BACKGROUND

Circuit devices often communicate data and control signals via serial buses, which may be bi-directional. In some instances, isolation circuitry may be provided to electrically isolate the circuit devices. One example of a circuit device that uses isolated serial buses to communicate data is a subscriber line interface circuit (SLIC), which can be coupled to communication lines, such as tip and ring lines of a telephone network, to send and receive information via the network communication lines. The SLIC may be adapted to communicate with another circuit via multiple pulse code modulation (PCM) buses and multiple serial peripheral interface (SPI) buses. Each bus typically includes an isolation circuit to electrically isolate the SLIC from the other circuit. Such isolation circuits can include capacitors, transformers, optical isolation circuits, other isolation circuits, or any combination thereof. However, such isolation circuits can increase the overall cost of a device. Hence, there is a need for an improved communication interface between circuit devices.

SUMMARY

In a particular embodiment, a circuit device includes a first circuit having a first plurality of serial terminals including a first data receive terminal and a first data transmit terminal. The first plurality of serial terminals is communicatively coupled to a particular circuit via isolation circuitry to communicate first serial data. The circuit device further includes a second circuit having a second plurality of serial terminals including a second data receive terminal coupled to the first data transmit terminal and including a second data transmit terminal coupled to the first data receive terminal to communicate second serial data to the particular circuit via the first data receive and transmit terminals.

In another particular embodiment, a subscriber line interface circuit (SLIC) device includes a pulse code modulation (PCM) circuit adapted to communicate voice data and a serial peripheral interface (SPI) circuit adapted to communicate control signals to a system. The PCM circuit includes a PCM frame synchronization terminal to receive a PCM frame synchronization signal from the system via a first isolated serial bus and a PCM clock terminal to receive a PCM clock signal from the system via a second isolated serial bus. The PCM circuit further includes a PCM data transmit terminal to transmit PCM data signals to the system via a third isolated serial bus and a PCM data receive terminal to receive PCM data signals from the system via a fourth isolated serial bus. The SPI circuit includes an SPI chip select terminal to receive an SPI chip enable signal to selectively activate the SPI circuit. The SPI circuit further includes an SPI data output terminal coupled to the fourth isolated serial bus and an SPI data input terminal coupled to the third isolated serial bus. The SPI circuit is adapted to communicate SPI data to the system via the third and fourth isolated serial buses.

In still another particular embodiment, a circuit device is disclosed that includes a first circuit having a first plurality of terminals adapted to couple to a respective plurality of serial buses to communicate first serial data via isolation circuitry to a system. The first plurality of terminals includes a first serial data transmit terminal adapted to couple to a first data bus of the respective plurality of data buses, a first serial data receive terminal adapted to couple to a second data bus of the respective plurality of data buses, and a first synchronization terminal adapted to couple to a first synchronization bus of the respective plurality of data buses. The circuit device further includes a second circuit to selectively communicate second serial data via the first serial data receive and transmit terminals in response to receiving the chip select signal. The second circuit includes a second data receive terminal coupled to the first serial data transmit terminal, a second data transmit terminal coupled to the first serial data receive terminal, and a chip select terminal to receive a chip select signal.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

In a particular embodiment, a circuit device is disclosed that has two serial communications circuits, such as a pulse code modulated (PCM) circuit and a serial peripheral interface (SPI) circuit. Pins or terminals associated with the two serial communications circuits are interconnected and the bus signals are multiplexed using a frame synchronization signal to communicate first serial data from a first circuit and second serial data from a second circuit via the same isolated serial buses. By multiplexing the bus signals and by interconnecting the pins (or terminals), the number of external serial buses can be reduced, reducing a number of isolation circuits, reducing overall costs, and reducing consumption of circuit real estate. In a particular example, the number of isolation circuits can be reduced from eight to five by interconnecting data buses of the two circuits and by coupling a frame synchronization terminal of the first circuit to a chip select terminal of the second circuit. In another particular example, the number of isolation circuits can be reduced from eight to four by sharing a clock signal, by sharing the data buses, and by utilizing a counter circuit to generate the chip select signal from a frame synchronization signal and a count of the clock signal.

FIG. 1is a block diagram of a representative embodiment of a circuit device100including a first circuit102and a second circuit104that are adapted to communicate serial data, such as pulse code modulated (PCM) voice data samples and serial peripheral interface (SPI) control data via independent, serial buses. Isolation circuitry106electrically isolates the first and second circuits104. In a particular embodiment, the first circuit102can be a system on a chip (SoC) and the second circuit104can be a subscriber line interface circuit (SLIC), which can be adapted to communicate with a telephone network. As used herein, the term “system on a chip” or “SoC” refers to a circuit device that includes multiple circuit components, such as a processor, a memory, analog circuits, external interfaces, timers, counters, voltage regulators, other circuitry, or any combination thereof on a single silicon chip, enabling the chip to operate as a stand-alone system. Further, as used herein, the term “subscriber line interface circuit” and “SLIC” refers to a circuit that interfaces a device or system to a communications network, such as a telephone network. In another particular embodiment, the first and second circuits102and104can be adapted to communicate via one or more serial data transfer formats via serial buses. In a particular embodiment, the first and second circuits102and104communicate via the isolation circuitry106, which is coupled to the serial buses. While the following discussion assumes that the serial data includes PCM data and SPI data, it should be understood that the first and second circuits102and104can communicate other types of serial data.

The first circuit102includes a first PCM frame synchronization terminal108that is coupled to a second PCM frame synchronization terminal112of the second circuit104via a PCM frame synchronization isolation circuit110. The first circuit102further includes a first PCM clock terminal114that is coupled to a second PCM clock terminal118of the second circuit104via a PCM clock isolation circuit116. The first circuit102also includes a first PCM data transmit terminal120that is coupled to a second PCM data transmit terminal124of the second circuit104via a transmit isolation circuit122. Additionally, the first circuit102includes a first PCM data receive terminal126that is coupled to a second PCM data receive terminal130of the second circuit104via a receive isolation circuit128.

Additionally, the first circuit102includes a first serial peripheral interface (SPI) data input terminal132that is coupled to a second SPI data output terminal136of the second circuit104via an SPI data isolation circuit134. The first circuit102further includes a first SPI data output138that is coupled to a second SPI data input142of the second circuit104via an SPI isolation circuit140. The first circuit102also includes a first SPI chip select terminal144coupled to a second SPI chip select terminal148of the second circuit104via a chip select isolation circuit146. Additionally, the first circuit102includes a first SPI clock terminal150that is coupled to a second SPI clock terminal154of the second circuit104via an SPI clock isolation circuit152.

In the embodiment shown, the first circuit102is adapted to communicate with the second circuit104via four PCM buses and four SPI buses. The isolation circuitry106includes eight isolation circuits, including isolation circuits110,116,122,128,134,140,146, and152to provide isolation for the PCM and SPI buses. However, each isolation circuit consumes circuit area and contributes to the overall cost of the circuit device100.

FIG. 2is a block diagram of a particular illustrative embodiment of a circuit device200including a first circuit202coupled to a second circuit204via multiplexed, serial buses having shared isolation circuitry206. In a particular example, the first circuit202can be a system on a chip (SoC) and the second circuit204can be a subscriber line interface circuit (SLIC). The first circuit202includes a first pulse code modulated (PCM) frame synchronization terminal208that is coupled to a second PCM frame synchronization terminal212of the second circuit204via an isolation circuit210. The first PCM frame synchronization terminal208is also coupled to an interrupt (INT) terminal of the first circuit202. In a particular embodiment, the interrupt terminal can trigger the first circuit202to communicate SPI data to the second circuit204based on a value of a PCM frame synchronization signal at the first PCM frame synchronization terminal208. The first circuit202further includes a first PCM clock terminal214that is coupled to a second PCM clock terminal218of the second circuit204via an isolation circuit216. The first circuit202also includes a first PCM data transmit terminal220that is coupled to a second PCM data transmit terminal224of the second circuit204via an isolation circuit222. Further, the first circuit202includes a first PCM data receive terminal226that is coupled to a second PCM data receive terminal230via an isolation circuit228. The PCM data transmit terminals220and224and the PCM data receive terminals226and230are adapted to communicate PCM voice data samples.

Additionally, the first circuit202includes a serial peripheral interface (SPI) data input terminal232that is coupled to the first PCM data receive terminal226. The second circuit204includes a corresponding SPI data output terminal234that is coupled to the second PCM data receive terminal230. The first circuit202also includes an SPI data output terminal236that is coupled to the first PCM data transmit terminal220, and the second circuit204includes a corresponding SPI data input terminal238that is coupled to the second PCM data transmission terminal224. The SPI data input and output terminals238and234can be used to communicate control data.

The first circuit202includes a first chip select terminal240, which is not coupled to the second circuit204. In a particular embodiment, the first chip select terminal240can be used to provide signals to other circuit components, or the terminal240may be omitted. The second circuit204includes a second chip select terminal242that is coupled to the second PCM frame synchronization terminal212. In this example, a PCM frame synchronization signal received via the second PCM frame synchronization terminal242can be used to control the chip select enable or disable state of a SPI circuit associated with the second circuit204. The first circuit202includes a SPI clock terminal250that is coupled to a corresponding SPI clock terminal254of the second circuit204via a clock isolation circuit.

In a particular embodiment, by multiplexing the SPI data input and output terminals232and236of the first circuit202onto the first PCM receive and transmit terminals226and220, respectively, both PCM and SPI data can be communicated between the first and second circuits202and204via shared isolation circuits222and228, reducing the number of isolation circuits206needed to provide serial bus isolation between the first and second circuits202and204. In a particular example, by reducing the number of isolation circuits202and204, the overall cost to produce the circuit200is reduced and the circuit area consumed by the circuit200is also reduced. Further, the chip select terminal240of the first circuit202can be omitted or can be used for other purposes, such as to provide control signals to another circuit device (not shown).

Further, additional isolation circuitry can be omitted by utilizing the frame synchronization signal as a chip select signal. In this instance, the first and second PCM frame synchronization terminals208and212, together with the isolation circuit210, can be coupled to the second SPI chip select terminal242, eliminating an isolation circuit that might otherwise be needed to provide chip select isolation. In this particular instance, the rising or falling edge of the PCM frame synchronization signal can be used as a chip select enable signal to selectively initiate communication of the SPI control data.

In a particular embodiment, an SPI clock signal is transmitted from the first circuit202to the second circuit204via the first SPI clock terminal250, the isolation circuit252, and the second SPI clock terminal254. A PCM clock signal is sent from the first circuit202to the second circuit204via the first PCM receive and transmit terminals226and220, respectively. The SPI clock signal and the PCM clock signal are sent independently. In this particular instance, the first and second circuits202and204are either communicating SPI control data or PCM voice data samples via the first and second PCM data transmit and receive terminals220,224,226, and230, depending on a logic level of the PCM frame synchronization signal.

FIG. 3is a particular illustrative embodiment of a timing diagram300for the circuit device200ofFIG. 2. The diagram300includes a frame synchronization (FSYNCH)/chip select (CS) signal302. The diagram300also includes a pulse code modulated (PCM) clock signal308, a data transmit signal310, a data receive signal316, and a serial peripheral interface (SPI) clock signal322. In a particular example, the FSYNCH/CS signal302is used to selectively enable communication of PCM voice data samples and SPI control data. At the rising edge304of the FSYNCH/CS signal302, PCM voice data transmission is enabled. The PCM data312from the data transmit signal310is clocked into a buffer at a second circuit (such as the second circuit204illustrated inFIG. 2) according to the PCM clock signal308. Additionally, PCM data318from the data receive signal316is received at a first circuit (such as the first circuit202illustrated inFIG. 2).

When the FSYNCH/CS signal302transitions at a falling edge306from a logic high to a logic low level, communication of SPI control data is enabled. In this instance, the SPI clock322is used to clock SPI data314from the data transmit signal310to an SPI buffer at the second circuit and to receive SPI data320via the data receive signal316at the first circuit. In this particular instance, the logic level of the FSYNCH/CS signal302operates as a chip select signal, while the rising and falling edges of the FSYNCH/CS signal302operate to synchronize the PCM frame transmissions.

In a particular embodiment, the circuit device may include different frame synchronization modes. In a particular example, when a long frame setting is used, the PCM frame is segmented such that a first portion of the PCM frame (when the FSYNCH/CS signal302is at a logic high level) is used to send and receive PCM data312and318and the second portion of the PCM frame (when the FSYNCH/CS signal302is at a logic low level) is used to send and receive SPI data314and320(or vice versa). By utilizing the PCM data transmit and receive terminals to send and receive both PCM and SPI data, the SPI terminals or pins of the first circuit are not needed to transmit the data. This allows those SPI terminals or pins to be used for other purposes or the pins can be eliminated. Additionally, isolation circuitry for the PCM buses can be shared for both PCM and SPI data transfers, reducing the number of isolation circuits, which reduces overall circuit costs and reduces the overall circuit area consumed.

FIG. 4is a block diagram of a particular illustrative embodiment of a circuit device400including a first circuit402coupled to a second circuit404via multiplexed, serial buses having shared isolation circuitry406. The first circuit402includes a first pulse code modulated (PCM) frame synchronization terminal408that is coupled to a second PCM frame synchronization terminal412of the second circuit404via an isolation circuit410. The first circuit402further includes a first PCM clock terminal414that is coupled to a second PCM clock terminal418of the second circuit404via an isolation circuit416. The first circuit402also includes a first PCM data transmit terminal420that is coupled to a second PCM data transmit terminal424of the second circuit404via an isolation circuit422. Further, the first circuit402includes a first PCM data receive terminal426that is coupled to a second PCM data receive circuit430via an isolation terminal428.

The first circuit402may also include serial peripheral interface (SPI) terminals (or pins), such as an SPI data input pin, an SPI data output pin, a chip select pin, and an SPI clock pin. In a particular embodiment, the SPI terminals or pins can be repurposed, allowing them to be used to control other circuit operations. In another particular embodiment, the SPI terminals or pins can be omitted from the first circuit402, reducing the number of pins or terminals and simplifying routing. The first circuit402may include a multiplexing circuit feature (not shown) that can be internal to the first circuit402to couple SPI data transmit and receive pins to the first PCM data transmit and receive terminals420and426.

The second circuit404includes an SPI data output terminal434coupled to the second PCM data receive terminal430. Additionally, the second circuit404includes an SPI data input terminal438that is coupled to the second PCM data transmit terminal424. Further, the second circuit404includes an SPI clock terminal454that is coupled to the second PCM clock terminal418.

The circuit device400includes a chip select (CS) generator counter452that is coupled to the second PCM frame synchronization terminal412to receive a PCM frame synchronization signal and to the second PCM clock terminal418to receive a PCM clock signal and includes an output coupled to a CS terminal442of the second circuit404. The CS generator counter452can be used to generate a chip select signal based on at least one of the frame synchronization signal and the PCM clock signal. The CS generator counter452is adapted to apply the generated chip select signal to the CS terminal442. In a particular example, the CS generator counter452can be a low cost hardware counter, such as a five-bit counter, to generate a designated chip select time slot within a given PCM frame. In a particular example, the second circuit404can be enabled to communicate SPI data via the second PCM data receive and transmit terminals430and424.

In a particular embodiment, by utilizing the PCM clock signal as a clock for both the second PCM clock terminal418and the SPI clock terminal454, the clock isolation circuitry for the SPI clock signal can be eliminated (as compared to the clock isolation circuit252of the circuit device200illustrated inFIG. 2). Further, in this particular embodiment, the CS generator counter452can be utilized to provide more clock-based PCM and SPI signaling based on a count of the PCM clock signal pulses. In this instance, instead of dividing the PCM frame into a first and second portion to carry PCM and SPI data respectively, the CS generator counter452can divide the PCM frame according to a PCM pulse count. In a particular embodiment, the CS generator counter452may be coupled to a programmable register (such as a programmable register460), which may be configured to control a PCM pulse count threshold that determines when the CS generator counter452enables the SPI circuitry of the second circuit404. In a particular example, the CS generator counter452can enable transmission of SPI control data during a first five PCM clock pulses, and then the CS generator counter452can enable transmission of PCM voice data samples, until a next PCM frame synchronization signal is received. In another particular embodiment, the CS generator counter452can be a low-cost hardware counter, such as a five-bit counter.

FIG. 5is a particular illustrative embodiment of a timing diagram500for the circuit device400ofFIG. 4. In this particular instance, the PCM and SPI circuits can share the same data terminals and the same clock terminals. Each PCM frame can include designated PCM and SPI time slots. The first circuit can send a NO-OPERATION (NO-OP) command on unused SPI frames.

The diagram500includes a frame synchronization (FSYNCH)/chip select (CS) signal502. The diagram500also includes a pulse code modulated (PCM) clock signal508, a data transmit signal510, a data receive signal516, and a chip select signal522. At the rising edge504of the FSYNCH/CS signal502, SPI data512from the data transmit signal510can be clocked into a buffer at a second circuit (such as the second circuit404illustrated inFIG. 4) according to the PCM clock signal508. Additionally, SPI PCM data518from the data receive signal516is received at a first circuit (such as the first circuit402illustrated inFIG. 4). The CS generator counter circuit452illustrated inFIG. 4may begin counting pulses of the PCM clock signal508in response to the rising edge504or falling edge506of the PCM frame synchronization pulse502. After a number of pulses are counted (such as five pulses, 10 pulses, or some other number of pulses), the CS generator counter circuit452can adjust a chip select signal522to a logic high level. After the chip select signal522changes to a logic high level at524, PCM data514and520can be sent via the data transmit signal510and received via the data receive signal516, respectively.

In this particular example, the generated chip select signal522can reset to a logic low level on an edge of the PCM frame synchronization signal502, such as the rising edge504. Further, after the chip select signal522is reset, the CS generator counter circuit452can count a number pulses of the PCM clock signal508and change to a logic high signal level (at524) when the number of PCM clock pulses is reached. In a particular example, the chip select generator counter circuit can be programmable to adjust the number of pulses to be counted. In a particular embodiment, by sharing the PCM clock signal and multiplexing the SPI and PCM data via the data lines, the number of isolation circuits can be reduced. Further, using a chip select counter generator, the number of isolation circuits can be cut in half (from eight to four). Reducing the number of isolation circuits and reducing the number of serial buses simplifies routing, reduces overall circuit costs, and reduces circuit area usage.

FIG. 6is a diagram of a particular illustrative embodiment of a chip select circuit600to selectively activate portions of a circuit, such as serial peripheral interface (SPI) circuits associated with a serial line interface circuit (SLIC), such as the SLIC circuit illustrated inFIG. 8. The chip select circuit600includes a chip select (CS) generator counter circuit452, such as the CS generator counter circuit452illustrated inFIG. 4, which is adapted to receive a pulse code modulated (PCM) clock signal via a PCM terminal or bus418and to receive a PCM frame synchronization signal via a PCM frame synchronization terminal or bus412.

The CS generator counter circuit452includes a logical NOR gate602having a gate output606that is coupled to a logic circuit604, such as a counter circuit. The logic circuit604can be a low cost hardware counter, such as a five-bit counter, to generate a designated chip select time slot. The logic circuit604includes a frame synchronization input608coupled to the PCM frame synchronization bus412. The logic circuit604further includes an output610that is coupled to a chip select pin or terminal, such as the chip select terminal442illustrated inFIG. 4. Further, the output610is coupled to a first input612of the logical NOR gate602. The logical NOR gate602further includes a second input614that is coupled to the PCM clock bus or terminal418.

In a particular embodiment, the logic circuit604can be a counter that is initialized by an edge (rising or falling edge) of the PCM frame synchronization signal received via the frame synchronization input608coupled to the PCM frame synchronization bus or terminal412. Once initialized, the output610of the logic circuit604can be held at a logic low level until a number of PCM clock signals are counted. The output signal having a logic low level is applied to the first input612of the logical NOR gate602, causing an inverted version of the PCM clock signal received via the second input614from the PCM clock bus or terminal418to be applied to the gate output606. The logic circuit604can count the inverted PCM clock pulses until a pre-determined (or programmed) number of clock pulses are counted. Once the pre-determined (or programmed) number of clock pulses are counted, the logic circuit604can apply a logic high level to the output610, which is also applied to the first input612of the logical NOR gate602. In this instance, the PCM clock signal received via the second input614is negated by the NOR gate602. The logic circuit604can continue to provide a logic high level at the output610until a next edge (rising or falling edge) of the PCM frame synchronization signal is received via the frame synchronization input608.

FIG. 7is a block diagram of a second particular illustrative embodiment of a chip select circuit700to produce a chip selection signal based on a data bit from a data transmit bus, where the chip selection signal is used to selectively activate portions of a circuit, such as the second circuits illustrated inFIGS. 2 and 4and serial peripheral interface (SPI) circuits associated with a serial line interface circuit (SLIC), such as the SLIC circuit illustrated inFIG. 8. The chip select circuit700includes a chip select (CS) generator counter circuit452, such as the CS generator counter circuit452illustrated inFIG. 4, which is adapted to receive a pulse code modulated (PCM) clock signal via a PCM terminal or bus418, a PCM frame synchronization signal via a PCM frame synchronization terminal or bus412, and at least one bit of a data transmit signal received from the data transmit terminal or bus424.

The CS generator counter circuit452includes a logical NOR gate702having a gate output706that is coupled to a logic circuit704, such as a counter circuit. The logic circuit704can be a low cost hardware counter, such as a five-bit counter, to generate a designated chip select time slot. The logic circuit704includes an enable input708coupled to the PCM frame synchronization bus412via a logical AND gate720. The logical AND gate720includes a first input coupled to the PCM frame synchronization bus412and a second input coupled to the data transmit (DTX) bus424. Further, the logical AND gate720includes an output coupled to the enable input708. The logic circuit704further includes an output710that is coupled to a chip select pin or terminal, such as the chip select terminal442illustrated inFIG. 4. Further, the output710is coupled to a first input712of the logical NOR gate702. The logical NOR gate702further includes a second input714that is coupled to the PCM clock bus or terminal418.

In a particular embodiment, the logic circuit704can be a counter that is enabled by an edge (rising or falling edge) of the output of the logical AND gate720received via the enable input708coupled to the PCM frame synchronization bus or terminal412and to the data transmit bus or terminal424. In a particular embodiment, a data bit, such as bit zero (bit0) of the data transmit signal, may be used to signal when serial peripheral interface (SPI) data is to be communicated between circuits. In this particular example, when the data bit has a value of zero, no SPI data is communicated via the PCM bus, and when the data bit has a value of one, the SPI data is communicated via the PCM bus. In this particular embodiment, SPI communications can be signaled or controlled based on a value of a particular data bit within the data transmit (DTX) payload. In this instance, the circuits communicate SPI data only when the particular bit is set, and the “No-Op” command described with respect toFIG. 5can be omitted.

FIG. 8is a block diagram of a particular illustrative embodiment of a portion of a communications device800including a circuit device802that is coupled to a system on a chip (SoC)860via multiplexed, serial buses866and shared isolation circuitry803. In a particular embodiment, the circuit device802can be a low-voltage integrated circuit adapted to couple to a high voltage line feed integrated circuit804. In a particular example, the line feed circuit804includes a first line feed circuit806that is coupled to a first channel (channel1) having a first tip line808and a first ring line810and includes a second line feed circuit812that is coupled to a second channel (channel2) having a second tip line814and a second ring line816. In this particular example, the line feed circuit804is adapted to connect to two different phone lines. In a particular embodiment, the circuit device802can operate as a subscriber line interface circuit (SLIC) including coder-decoder (CODEC) functionality, dual tone multi-frequency (DTMF) detection, and signal generation functions used for two complete analog telephone interfaces, including battery, over-voltage, ringing, supervision, CODEC, hybrid, and test functions (such as metallic loop testing capabilities).

The circuit device802includes a first SLIC circuit820and a second SLIC circuit822that are coupled to the first and second line feed circuits806and812, respectively. The first SLIC circuit820can include a first line feed control circuit840and a first line feed monitor circuit842, which are coupled to the first line feed circuit806to control and monitor the first line feed circuit806. The second SLIC circuit822can include a second line feed control circuit844and a second line feed monitor circuit846, which are coupled to the second line feed circuit812to control and monitor the second line feed circuit812. The circuit device802further includes first and second CODEC circuits824and826, which are coupled to the first and second SLIC circuits820and822, respectively. The first CODEC circuit824can include a first analog-to-digital converter (ADC)848and a first digital-to-analog converter (DAC)850. The second CODEC circuit826includes a second ADC852and a second DAC854. The first and second CODEC circuits824and826can provide standard voice-band (e.g., 200 Hz to 3.4 kHz) audio processing capabilities, including both wideband (50 Hz to 8 kHz) and standard voice-band (200 Hz to 3.4 kHz) operating modes. The wide band mode can provide an expanded audio band with a 16 kHz sample rate for enhanced audio quality while the standard voice-band mode provides telephony audio compatibility.

The circuit device802further includes a digital signal processor828that can be used to process received digital samples. Additionally, the circuit device802includes pulse code modulated (PCM)/common gateway interface (CGI) interface circuitry830that is adapted to communicate with the SoC860. The circuit device802further includes a serial peripheral interface (SPI) control interface circuit832, which may include a chip select (CS) generator counter833(such as the chip select generator counter circuit452illustrated inFIG. 4). While the CS generator counter833is illustrated as being included within the circuit device802, it should be understood that, in another embodiment, the CS generator counter833can be external to the circuit device802. Further, the CS generator counter833can be programmable via register settings.

The circuit device802further includes a phase locked loop (PLL) circuit834to synchronizing timing. The circuit device802can include one or more direct current (DC)-to-DC controllers836, which may communicate with a bill of materials818(e.g., additional circuitry). The circuit device802can also include other circuitry838, such as a general purpose processor, encryption/decryption circuitry, other circuits, or any combination thereof.

In a particular embodiment, the first and second line feed circuits806and812provide programmable on-hook loop voltage, off-hook loop current, reverse battery operation, loop or ground start operation, and on-hook transmission functionality, which may be controlled and monitored via the first and second line feed control and monitor circuits840,842,844, and846. The loop current and voltage can be monitored using the ADCs848and852of the CODECs824and826.

Further, the circuit device802integrates complete audio transmit and receive paths, including alternating current (AC) impedance and hybrid gain. In a particular example, the audio transmit and receive paths can be software-programmable, allowing the circuit device802to be utilized with multiple different requirements. For example, the digital signal processor828can be used to calculate coefficients to match the output impedance of the first and second SLIC circuits820and822to reduce signal reflections. Further, the digital signal processor828can implement a hybrid balance function to cancel reflected receive path signals from the transmit path using coefficient generator software to determine adjustable filter coefficients. Digital voice data transfers can be sent to the SoC860via the PCM/CGI interface830, and control data can be transferred using the SPI control interface832.

In a particular embodiment, the SPI control interface832can be a four-wire interface modeled after microcontroller and serial peripheral devices. The SPI control interface832includes an SPI clock terminal or pin (SCLK), an SPI chip select terminal or pin (CS), an SPI serial data input (SDI), and an SPI serial data output (SDO). The PCM/CGI interface830includes a flexible, programmable interface for the transmission and reception of digital PCM samples. PCM data transfer can be controlled by a PCM clock signal and a PCM frame synchronization signal received at a PCM clock terminal or pin (PCLK) and at a PCM frame synchronization pin or terminal (FSC), respectively. The PCM/CGI interface830includes PCM mode select, PCM transmit start, and PCM receive start settings, which allow for programming of the PCM/CGI interface830for various operating modes. Additionally, the PCM/CGI interface830includes a PCM data transmit (DTX) terminal (or pin) and a PCM data receive (DRX) terminal (or pin). In a particular embodiment, the PCM/CGI interface830can be configured to support from four to 128 8-bit time slots in each 125 μs frame, corresponding to a PCM clock frequency range of 256 kHz to 8.192 MHz.

In a particular embodiment, the circuit device802is adapted to communicate voice data and corresponding frame synchronization and PCM clock signals via the DTX, DRX, FSC, and PCLK terminals and via the isolation circuitry803to corresponding DTX, DRX, FSC, and PCLK terminals862of the SoC860. Further, the circuit device802is adapted to utilize a chip select signal from the chip select generator counter833to selectively activate the SPI control interface832to communicate control data via the PCM DTX and DRX terminals and via the isolation circuitry803to the SoC860.

In a particular example, the isolate circuitry803can include multiple isolation circuits, which can be shared by the serial buses866to send both control and voice data over the same serial buses at different times or points within the PCM frame, as shown with respect to the diagrams300and500illustrated inFIGS. 3 and 5, which times or points may correspond to particular pulses of an SPI clock or a PCM clock. Further, by multiplexing the SPI control data onto the PCM data lines (DTX and DRX) and by utilizing the PCM clock and the frame synchronization signals to control chip selection, at least four isolation circuits can be eliminated. Further, SPI control pins864of the SoC860can be repurposed to communicate with other circuitry or can be eliminated. Additionally, the CS generator counter833can use a low-cost hardware counter, such as a five-bit counter, to generate a SPI time slot for transmission of SPI control data.

While the above-example relates to a communications device, it should be understood that other types of electronic devices and other types of circuits may utilize serial data transmission protocols. By using a frame synchronization signal to multiplex serial data from two different serial interface circuits onto the same serial lines, the number of isolation circuits can be reduced, reducing overall costs. Further, by eliminating some of the isolation circuits (without sacrificing electrical isolation), pins of one of the circuits (such as the SoC860inFIG. 8) can be repurposed for other functions or eliminated. Additionally, by reducing the number of isolation circuits, the overall circuit area can be reduced.

FIG. 9is a flow diagram of a particular illustrative embodiment of a method of multiplexing selected serial buses to communicate serial data between two circuit devices. At902, voice data is communicated from a first pulse code modulated (PCM) interface circuit of a first circuit device to a second PCM circuit of a second circuit device via first and second serial buses respectively during a first portion of a PCM synchronization frame, where the first and second serial buses include isolation circuitry to electrically isolate the first and second circuit devices. In a particular embodiment, the first circuit device can include multiple serial bus terminals, including a frame synchronization terminal and a clock terminal, which may be used to synchronize and perform chip selection for communicating different types of serial data from different circuits within configured slots of a PCM frame. Continuing to904, control data is communicate between a first serial peripheral interface (SPI) circuit of the first circuit device and a second SPI circuit of the second circuit device via the first and second serial buses during a second portion of the synchronization frame. Advancing to906, the first and second circuit devices are synchronized using at least one clock signal associated with the first serial interface circuit and provided to the second circuit device. The method terminates at908.

In a particular embodiment, the at least one clock signal includes a PCM clock signal and an SPI clock signal, which are transmitted from the first circuit device to the second circuit device via clock serial buses that include isolation circuitry to electrically isolate the first and second circuit devices. In another particular embodiment, the PCM clock signal is utilized for both the PCM clock and the SPI clock. In a particular embodiment, a PCM frame synchronization signal is used for frame synchronization and for chip selection of the second SPI circuit.

In conjunction with the circuit devices and methods disclosed above with respect toFIGS. 2-9, a circuit device is disclosed that is adapted to communicate serial data between two circuit devices via shared isolation circuitry. In a particular example, the first and second circuit devices may each include a pulse code modulated (PCM) circuit and a serial peripheral interface (SPI) circuit, and the PCM and SPI circuits can communicate via a shared pair of serial buses. In a particular example, the total number of external serial buses for a circuit device can be reduced, reducing the customer costs for bus isolation. In particular, the number of bus signals (isolated buses) is reduced by multiplexing the PCM and SPI buses, using the frame synchronization signal to multiplex the SPI and PCM buses. In a particular example, the frame synchronization signal and the PCM clock signal can be used in combination to produce a chip selection signal that can be used to selectively activate at least one of the circuits for communicating data.

It should be understood that, while the above-examples and embodiments have been directed to circuits that include PCM circuitry and SPI circuitry and that communicate PCM and SPI data, the circuit devices can be used with any circuitry that uses serial data communication protocols. Further, though the primary example has been described with respect to a telephonic communication system (such as the circuit device ofFIG. 8), the serial data multiplexing arrangement can be utilized with other types of circuits and with other types of serial data.