Semiconductor device having a fin and method of manufacturing the same

A semiconductor device includes a Fin, a source region and a drain region, a first extension region, a second extension region and a channel region. The Fin is formed on a major surface of a semiconductor substrate. The source region and drain region are formed at both end portions of the Fin. The first extension region is formed between the source region and the drain region within the Fin in contact with the source region. The second extension region is formed between the source region and the drain region within the Fin in contact with the drain region. The channel region is located between the first extension region and the second extension region within the Fin, a height of the Fin of the channel region being greater than a height of the Fin of each of the first extension region and the second extension region.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2006-012278, filed Jan. 20, 2006, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to a structure of a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device including a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) having a Fin channel and a method of manufacturing the same.

2. Description of the Related Art

There has been proposed a Fin-type MOSFET (Fin-FET) which is designed to maintain a current driving ability in a MOSFET with a fine structure. The Fin-FET is a multi-gate MOSFET with a three-dimensional structure, which can be fabricated only from an upward direction of a substrate of the Fin-FET.

The Fin-FET has a projection-shaped semiconductor layer (Fin) on the substrate, and both side surfaces of the Fin are used as channel regions. Suppression of an off-leak current that flows through the Fin, that is, punch-through, is a very important task in order to prevent degradation in cut-off characteristics. Related techniques on the Fin-FET have already been disclosed (see, for instance, Masaki Kondo et al., “A FinFET Design Based on Three-Dimensional Process and Device Simulations”, Toshiba Corporation, IEEE, 2003).

BRIEF SUMMARY OF THE INVENTION

According to an aspect of the invention, there is provided a semiconductor device comprising: a Fin which is formed on a major surface of a semiconductor substrate and extends in a first direction; a source region and a drain region which are formed at both end portions in the first direction of the Fin; a first extension region which is formed between the source region and the drain region within the Fin in contact with the source region, the first extension region having a lower impurity concentration than the source region; a second extension region which is formed between the source region and the drain region within the Fin in contact with the drain region, the second extension region having a lower impurity concentration than the drain region; a channel region which is located between the first extension region and the second extension region within the Fin, a height of the Fin of the channel region being greater than a height of the Fin of each of the first extension region and the second extension region; an insulation film which covers both side surfaces and an upper surface of the channel region; and a gate electrode which covers the channel region via the insulation film.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: etching a major surface of a semiconductor substrate by masking a part of the major surface of the semiconductor substrate, thus forming a Fin with a mask layer covering an upper surface of at least a channel region within the Fin, the Fin extending in a first direction; forming an insulation film such that the insulation film covers both side surfaces of the channel region; forming a gate electrode material such that the gate electrode material covers both side surfaces of the channel region via the insulation film and the mask layer; forming a hard mask on an upper surface of the gate electrode material, the hard mask covering the channel region in a direction crossing the first direction of the Fin; performing etching using the hard mask as a mask, thereby forming a gate electrode, and decreasing a height of the Fin in a region excluding the channel region; forming first spacers on both side surfaces in the first direction of the gate electrode, and doping impurities in the Fin using the first spacers as a mask, thereby forming a first extension region and a second extension region; and forming second spacers on both side surfaces in the first direction of the first spacers, doping impurities using the second spacers as a mask with a higher impurity concentration than in the first and second extension regions, thereby forming a source region and a drain region at both end portions in the first direction of the Fin, the source region and the drain region sandwiching the channel region and the first and second extension regions.

According to still another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: etching a major surface of a semiconductor substrate by masking a part of the major surface of the semiconductor substrate, thus forming a Fin which extends in a first direction; forming an insulation film such that the insulation film covers both side surfaces and an upper surface of a channel region within the Fin; forming a gate electrode material on the Fin such that the gate electrode material covers both side surfaces and the upper surface of the channel region via the insulation film; forming a hard mask on an upper surface of the gate electrode material, the hard mask covering the channel region in a direction crossing the first direction of the Fin; performing etching using the hard mask as a mask, thereby forming a gate electrode, and decreasing a height of the Fin in a region excluding the channel region; forming first spacers on both side surfaces in the first direction of the gate electrode, and doping impurities in the Fin using the first spacers as a mask, thereby forming a first extension region and a second extension region; and forming second spacers on both side surfaces in the first direction of the first spacers, doping impurities using the second spacers as a mask with a higher impurity concentration than in the first and second extension regions, thereby forming a source region and a drain region at both end portions in the first direction of the Fin, the source region and the drain region sandwiching the channel region and the first and second extension regions.

DETAILED DESCRIPTION OF THE INVENTION

Embodiments of the present invention will now be described in detail with reference to the accompanying drawings. In the description below, elements with the same functions and structures are denoted by like reference numerals.

FIRST EMBODIMENT

FIG. 1is a perspective view showing a main part of a semiconductor device according to a first embodiment of the present invention.FIG. 2is a plan view of the semiconductor device shown inFIG. 1.FIG. 3Ais a cross-sectional view taken along line B-B′ inFIG. 2, andFIG. 3Bis a cross-sectional view taken along line A-A′ inFIG. 2.

A projection-shaped semiconductor layer, or a Fin14, is provided on a semiconductor substrate11shown inFIG. 1. A device isolation region (STI: Shallow Trench Isolation)15, which effects electrical isolation from other devices, is provided on the semiconductor substrate11so as to cover lower side surfaces of the Fin14.

FIG. 3Bshows that a source region26, a first extension region22, a channel region23, a second extension region24and a drain region28are formed in the named order in the Fin14in a first direction in which the Fin14extends along line A-A′ inFIG. 2. The channel region23is located between the first extension region22and second extension region24, and is present under an area where the Fin14is covered with a mask layer19, which is formed of an insulator, inFIG. 2.

As shown inFIG. 3A, gate insulation films17A and17B, which are formed of, e.g. SiO2, are provided on both side surfaces of the channel region23of the Fin14. An insulation film12of, e.g. SiO2is provided on an upper surface of the channel region23of the Fin14. A mask layer13of an insulator, e.g. SiN, is provided on the insulation film12.

Also as shown inFIG. 3A, a gate electrode18is provided so as to cover both side surfaces of the channel region23of the Fin14and the mask layer13that is provided on the channel region23of the Fin14. The gate electrode18is formed of, e.g. polysilicon. By the presence of the mask layer13, the gate electrode18functions only at both side surfaces of the channel region23of the Fin14. That is, a double-gate structure is formed. In this manner, a double-gate Fin-MOSFET (hereinafter referred to as Fin-FET) is fabricated.

As is shown inFIG. 3B, in the Fin-FET of this embodiment, the height of the channel region23(in the direction vertical to the surface of the substrate) which is present under the insulation film12is greater than the height of the neighboring first extension region22and second extension region24.

Specifically, the height of the Fin14from its bottom to its top, that is, the height from the boundary plane between the STI15and gate electrode18to the top of the Fin inFIG. 3A, is defined as the height of the Fin. As is shown inFIG. 3B, the relationship, Hch>Hex, is established, where Hchis the height of the Fin of the channel region23, and Hexis the height of the first and second extension regions22and24.

Next, a method of manufacturing the semiconductor device according to the first embodiment of the invention is described with reference toFIG. 4toFIG. 20.FIG. 4toFIG. 14(exceptFIG. 6) are cross-sectional views taken along line B-B′ inFIG. 2.FIG. 15AtoFIG. 19AandFIG. 21Aare cross-sectional views taken along line B-B′ inFIG. 2.FIG. 15BtoFIG. 19BandFIG. 21Bare cross-sectional views taken along line A-A′ inFIG. 2.FIG. 20andFIG. 22are cross-sectional views taken along line B-B′ inFIG. 2.

To begin with, a semiconductor substrate11is prepared. In this example, a bulk Si substrate is used as the semiconductor substrate11. Then, as shown inFIG. 4, an insulation film12(e.g. SiO2) and a mask layer13of an insulator (e.g. SiN) are successively stacked on the semiconductor substrate11by, e.g. CVD (Chemical Vapor Deposition).

Subsequently, as shown inFIG. 5, the insulation film12and mask layer13are etched by lithography and RIE (Reactive Ion Etching) so as to have the same plan-view pattern as a Fin which is to be described later. The plan-view pattern in this case is as shown inFIG. 6(plan view).

As shown inFIG. 7, using the mask layer13as a mask, the major surface of the semiconductor substrate11is etched down to a desired depth by means of, e.g. RIE. Thereby, a Fin14, which is a projection-shaped semiconductor layer, is formed on the major surface of the semiconductor substrate11.

Next, as shown inFIG. 8, an insulation layer15is deposited by, e.g. CVD, so as to cover the mask layer13over the semiconductor substrate11. As the insulation layer15, SiN, SiO2, TEOS (Tetra-Ethyl-Ortho-Silicate), etc. is used. The insulation layer15is polished, as shown inFIG. 9, by CMP (Chemical Mechanical Polishing) down to a level of the surface of the mask layer13, and thus the surface of the insulation layer15is planarized.

Subsequently, as shown inFIG. 10, the insulation film15is etched by RIE so as to have a desired height (or thickness). This height is set to be lower than the top of the Fin14(Fin top). Thus, a device isolation region (STI)15is formed on the semiconductor substrate11.

Thereafter, as shown inFIG. 11, the Fin14is subjected to thermal oxidation, and gate insulation films17A and17B are formed on both side surfaces of the Fin14. As shown inFIG. 12, using, e.g. CVD, a conductor (e.g. polysilicon)18, which is a gate electrode material, is deposited so as to cover the mask layer13over the insulation film15.

The polysilicon layer18, as shown inFIG. 13, is polished by CMP to the level of the surface of the mask layer13, and thus the polysilicon layer18is planarized. The mask layer13functions as a stopper for planarizing the polysilicon layer18without damaging the Fin14, and also functions to realize a double-gate structure.

Next, as shown inFIG. 14, polysilicon is deposited once again. In this manner, the polysilicon layer18with the planarized surface is formed.

As shown inFIG. 15, an insulation layer19(e.g. SiN) is deposited on the polysilicon layer18. Using lithography, a mask (not shown) having a plan-view pattern of the gate electrode is formed on the insulation layer19.

Using this mask, as shown inFIG. 16B, the insulation layer19is etched by, e.g. RIE down to the surface of the polysilicon layer18. A hard mask19of, e.g. SiN is thus formed on the polysilicon layer18.

Subsequently, as shown inFIG. 17B, using the hard mask19as a mask, the polysilicon layer18and mask layer13are etched. In this case, that part of the insulation film12on the upper surface of the Fin14, which is other than the part under the hard mask19, is removed. In this manner, the gate electrode18of the double-gate structure is formed on both side surfaces of the channel region23of the Fin14.

Further, as shown inFIG. 18B, over-etching is performed at the time of the above-described etching, or anisotropic etching is conducted on the Fin14from which the insulation film has been removed. Thereby, stepped parts are formed so as to make the height (Hex) of the Fin of first and second extension regions, which are to be formed subsequently, less than the height (Hch) of the channel region23.

As shown inFIG. 19B, using, e.g. CVD and RIE, first spacers (offset spacers)20of, e.g. SiN are formed on both side surfaces of the gate electrode18(i.e. side surfaces extending in the direction of extension of the Fin14, that is, the direction of line A-A′ inFIG. 2).

The first spacers20are used in order to form extension regions. Using the first spacers20as a mask, low-concentration impurities are ion-implanted in the Fin14. Thereby, a first extension region22and a second extension region24are formed in the Fin14.

The impurity concentration in the first extension region22and second extension region24is set to be lower than that in source and drain regions which are to be formed subsequently. The first extension region22and second extension region24are provided to decrease electric field intensity in the channel region23. The provision of the first extension region22and second extension region24can suppress a short-channel effect of the transistor and can enhance a current driving ability.

In usual cases, the ion implantation of impurities is followed by heat treatment such as anneal. As a result, in general, impurities are diffused and widely distributed. Thus, as shown inFIG. 20, the first extension region22and second extension region24may diffuse into the channel region23.

Following the step inFIG. 19B, as shown inFIG. 21B, second spacers21of, e.g. SiN are formed by, e.g. CVD and RIE on both side surfaces of the gate electrode18(i.e. both side surfaces of the first spacers20).

If the SiN, for example, which is deposited on both ends of the Fin14in the direction of A-A′ (i.e. direction of extension of Fin14) at the time of formation of the first spacers20and second spacers21, is etched by RIE, the structure as shown inFIG. 3Bis obtained. At last, using the second spacers21as a mask, ion implantation is performed at both ends of the Fin14, and thus a source region26and a drain region28are formed. The impurity concentration in the source region26and drain region28is set to be higher than that in the first extension region22and second extension region24.FIG. 22is a cross-sectional view taken along line B-B′ of a semiconductor device according to the present embodiment in a case where the first extension region22and second extension region24diffuse into the channel region23, as shown inFIG. 20.

In the case of a Fin-FET with a conventional structure wherein the height of the Fin of the channel region23is equal to the height of the first extension region22and second extension region24, an off-leak current, which flows through the Fin, mainly flows at a Fin top of the Fin. In the present embodiment, however, the height of the channel region23is set to be greater than the height of the first extension region22and second extension region24, thereby increasing a current path of a current that flows from the first extension region22to the second extension region24via the Fin top of the channel region23. As a result, the off-leak current, i.e. punch-through, flowing through the Fin top can be reduced.

FIG. 23is a graph showing, by simulation, current density distributions of off-leak current in the right half part of the cross section of the Fin14shown inFIG. 3A, in the case of the Fin-FET with the conventional structure and in the case of the Fin-FET of the embodiment of the invention. It is assumed that the height of the Fin of the channel region is equal between the conventional structure and the structure of the embodiment (Hch=70 nm). In the structure of the present embodiment, it is assumed that the height of the Fin of the first and second extension regions22and24is less than the height of the channel region23by 20 nm, that is, Hch−Hex=20 nm.

It is understood fromFIG. 23that compared to the Fin-FET of the conventional structure, the Fin-FET of the structure of the present embodiment can more effectively suppress punch-through, in particular, at the Fin top.

FIG. 24shows drain current versus gate voltage characteristics in the case of the Fin-FET with the conventional structure and in the case of the Fin-FET of the embodiment of the invention. In this case, too, it is assumed that the height of the Fin of the channel region is equal between the conventional structure and the structure of the embodiment (Hch=70 nm), and that in the structure of the present embodiment the height of the Fin of the first and second extension regions22and24is less than the height of the channel region23by 20 nm, that is, Hex=50 nm. It is understood that with the structure of the Fin-FET of the present embodiment, an off-leak current can totally be reduced in a region below the threshold voltage.

The comparison based on the simulation demonstrates that the optimal characteristics can be obtained when the height of the Fin of the channel region is greater than the height of the Fin of the first and second extension regions by 20 nm.

In the present embodiment, as shown inFIG. 3B, the part of the Fin, at which the height of the Fin of the channel region23is greater than the height of the Fin of the first extension region22and second extension region24, is represented by a projecting rectangular shape. However, as shown inFIG. 25, this part of the Fin may have a projecting shape with rounded corners, and the same advantageous effects as in the present embodiment can be obtained. Moreover, in this embodiment, the bulk Si substrate is used as the semiconductor substrate11. Alternatively, an SOI (Silicon On Insulator) may be used as the substrate11.

SECOND EMBODIMENT

A perspective view and a plan view, which show a main part of a semiconductor device according to a second embodiment of the invention, are the same asFIG. 1andFIG. 2.FIG. 26Ais a cross-sectional view taken along line B-B′ inFIG. 2, showing the semiconductor device according to the second embodiment, andFIG. 26Bis a cross-sectional view taken along line A-A′.

A projection-shaped semiconductor layer, or a Fin14, is provided on a semiconductor substrate11shown inFIG. 1. A device isolation region (STI: Shallow Trench Isolation)15, which effects electrical isolation from other devices, is provided on the semiconductor substrate11so as to cover lower side surfaces of the Fin14.

FIG. 26Bshows that a source region26, a first extension region22, a channel region23, a second extension region24and a drain region28are formed in the named order in the Fin14in a first direction in which the Fin14extends along line A-A′ inFIG. 2. The channel region23is present under an area where the Fin14is covered with a mask layer19, which is formed of an insulator, inFIG. 2.

As shown inFIG. 26A, a gate insulation film17of, e.g. SiO2is provided on both side surfaces and an upper surface of the channel region23of the Fin14.

Also as shown inFIG. 26A, a gate electrode18is provided so as to cover both side surfaces and upper surface of the channel region23of the Fin14. The gate electrode18is formed of, e.g. polysilicon. The gate electrode18functions at both side surfaces and upper surface of the channel region23of the Fin14. That is, a tri-gate structure is formed. In this manner, a tri-gate Fin-FET is fabricated.

In this Fin-FET, the channel region23is present under the insulation film17inFIG. 26B. The bottom of the Fin14is positioned at the level of the boundary plane between the STI115and gate electrode18shown inFIG. 26A. In this embodiment, like the first embodiment, the height (Hch) of the channel region23is set to be greater than the height (Hex) of the neighboring first extension region22and second extension region24. That is, the relationship, Hch>Hex, is established.

Next, a method of manufacturing the semiconductor device according to the second embodiment is described with reference toFIG. 27toFIG. 36.FIG. 27 to 30are cross-sectional views taken along line B-B′ inFIG. 2.FIG. 31AtoFIG. 36Aare cross-sectional views taken along line B-B′ inFIG. 2.FIG. 31BtoFIG. 36Bare cross-sectional views taken along line A-A′ inFIG. 2.

As regards the fabrication steps illustrated inFIG. 4toFIG. 10, the manufacturing method of the semiconductor device of the second embodiment is common to that of the first embodiment. Subsequently, as shown inFIG. 27, the mask layer13and insulation layer12are entirely etched away by, e.g. RIE.

Thereafter, as shown inFIG. 28, the Fin14is subjected to thermal oxidation, and a gate insulation film17is formed on both side surfaces and upper surface of the Fin14. As shown inFIG. 29, a conductor (e.g. polysilicon)18, which is a gate electrode material, is deposited so as to cover the Fin14over the insulation film15.

The surface of the polysilicon layer18, as shown inFIG. 30, is planarized by, e.g. CMP. Then, as shown inFIG. 31, polysilicon is deposited once again and an insulation layer19(e.g. SiN) is deposited on the polysilicon layer18. Using lithography, a mask (not shown) having a plan-view pattern of the gate electrode is formed on the insulation layer19.

Using this mask, as shown inFIG. 32B, the insulation layer19is etched by, e.g. RIE down to the surface of the polysilicon layer18. A hard mask19of, e.g. SiN is thus formed on the polysilicon layer18.

Subsequently, as shown inFIG. 33B, using the hard mask19as a mask, the polysilicon layer18is etched by, e.g. RIE so as to have a desired plan-view pattern. In this case, that part of the insulation film17on the upper surface of the Fin14, which is other than the part under the hard mask19, is removed. In this manner, the gate electrode18of the tri-gate structure is formed on both side surfaces and upper surface of the channel region23of the Fin14.

Subsequent fabrication steps illustrated inFIG. 34A,34B toFIG. 36A,36B andFIG. 26A,26B, which is the cross-sectional view of the semiconductor device of the second embodiment, are the same as in the first embodiment.FIG. 37is a cross-sectional view taken along line B-B′ of a semiconductor device according to the present embodiment in a case where the first extension region22and second extension region24diffuse into the channel region23.

With the semiconductor device of the present embodiment, too, the height of the Fin of the channel region23is set to be greater than the height of the Fin of the first extension region22and second extension region24, thereby increasing a current path of a current that flows from the first extension region22to the second extension region24via the Fin top of the channel region23. As a result, a punch-through current flowing through the Fin top can be reduced.

In the present embodiment, too, as shown inFIG. 26B, the part of the Fin, at which the height of the Fin of the channel region23is greater than the height of the first extension region22and second extension region24, is represented by a projecting rectangular shape. However, as shown inFIG. 25, this part of the Fin may have a projecting shape with rounded corners, and the same advantageous effects as in the present embodiment can be obtained. Moreover, in this embodiment, the bulk Si substrate is used as the semiconductor substrate11. Alternatively, an SOI (Silicon On Insulator) may be used as the substrate11.

One aspect of the present invention can provide a semiconductor device including a Fin-FET with suppressed punch-through, and a method of manufacturing the semiconductor device.