Dependency scheduling for control stream in parallel processor

Techniques are disclosed relating to processing a control stream such as a compute control stream. In some embodiments, the control stream includes kernels and commands for multiple substreams. In some embodiments, multiple substream processors are each configured to: fetch and parse portions of the control stream corresponding to an assigned substream and, in response to a neighbor barrier command in the assigned substream that identifies another substream, communicate the identified other substream to a barrier clearing circuitry. In some embodiments, the barrier clearing circuitry is configured to determine whether to allow the assigned substream to proceed past the neighbor barrier command based on communication of a most-recently-completed command from a substream processor to which the other substream is assigned (e.g., based on whether the most-recently-completed command meets a command identifier communicated in the neighbor barrier command). The disclosed techniques may facilitate parallel control stream parsing and substream synchronization.

BACKGROUND

Technical Field

This disclosure relates generally to parallel processor architectures and more particularly to dependencies within a control stream.

Description of the Related Art

Given their growing compute capabilities, graphics processing units (GPUs) are now being used extensively for large-scale compute workloads. APIs such as Metal and OpenCL give software developers an interface to access the compute power of the GPU for their applications. In recent times, software developers have been moving substantial portions of their applications to using the GPU. Furthermore, GPUs are becoming more powerful in new generations.

Work to be performed on a parallel processor is often specified as a control stream that includes commands and kernels. For example, a program executed by a central processing unit may use one or more compute kernels that are compiled for another processor such as a GPU or digital signal processor (DSP). Compute workloads are often specified using task graphs and may include a mix of dependent and non-dependent kernels. When one kernel depends on another, it should wait for the other kernel to finish before it begins. Non-dependent kernels may execute in parallel, however.

This specification includes references to various embodiments, to indicate that the present disclosure is not intended to refer to one particular implementation, but rather a range of embodiments that fall within the spirit of the present disclosure, including the appended claims. Particular features, structures, or characteristics may be combined in any suitable manner consistent with this disclosure.

Within this disclosure, different entities (which may variously be referred to as “units,” “circuits,” other components, etc.) may be described or claimed as “configured” to perform one or more tasks or operations. This formulation—[entity] configured to [perform one or more tasks]—is used herein to refer to structure (i.e., something physical, such as an electronic circuit). More specifically, this formulation is used to indicate that this structure is arranged to perform the one or more tasks during operation. A structure can be said to be “configured to” perform some task even if the structure is not currently being operated. “A substream processor configured to parse a portion of a control stream” is intended to cover, for example, a circuit that performs this function during operation, even if the circuit in question is not currently being used (e.g., power is not connected to it). Thus, an entity described or recited as “configured to” perform some task refers to something physical, such as a device, circuit, memory storing program instructions executable to implement the task, etc. This phrase is not used herein to refer to something intangible.

The term “configured to” is not intended to mean “configurable to.” An unprogrammed FPGA, for example, would not be considered to be “configured to” perform some specific function, although it may be “configurable to” perform that function. After appropriate programming, the FPGA may then be configured to perform that function.

Further, as used herein, the terms “first,” “second,” “third,” etc. do not necessarily imply an ordering (e.g., temporal) between elements. For example, a referring to a “first” graphics operation and a “second” graphics operation does not imply an ordering of the graphics operation, absent additional language constraining the temporal relationship between these operations. In short, references such as “first,” “second,” etc. are used as labels for ease of reference in the description and the appended claims.

DETAILED DESCRIPTION

Overview of Substream Processing and Barrier Clearing

In various embodiments, a control stream (e.g., a compute control stream) includes multiple substreams and commands and may specify dependencies between substreams. For example, one substream may synchronize with another by waiting for the other substream to reach a specified point. In some embodiments, a processor includes a separate substream processor for each substream, which may allow indirect execution within each substream. In some embodiments, barrier clearing circuitry is configured to track substream progress and control synchronization between the substream processors.

FIG. 1is a block diagram illustrating an example processor (e.g., a graphics processor) with substream synchronization, according to some embodiments. In the illustrated embodiment the processor includes barrier clearing circuitry120and multiple substream processors110A-110N that process a control stream105.

Substream processors110, in the illustrated embodiment, are configured to process different substreams of control stream105. For example, N different substream processors may separately parse N different substreams. In some embodiments, all substream processors110also process a global substream. Each substream processor may separately fetch the entire control stream but may parse only their assigned substream and the global substream. Different substreams and the global substream may be differentiated using headers in the control stream105, for example. Embodiments of sub stream processors110are described in further detail below with reference toFIG. 4.

In some embodiments, control stream105includes kernels, links (which may redirect execution and may or may not include a return), and commands (e.g., barrier, cache flush, cache flush invalidate, wait on flush, etc.). Kernels may be compiled for a highly parallel processor such as a GPU. One common kernel organization is a three-dimensional kernel that includes a number of workgroups in each of the x, y, and z dimensions. As one example, a three-dimensional kernel may have a certain number of workitems in each of the x, y, and z dimensions. Workitems may be executed similarly to graphics threads. Kernels are often compiled routines for high throughput accelerators such as GPUs or DSPs. Kernels may be specified in their own programming language (e.g., OpenCL C), managed by a graphics API such as OpenGL, or embedded directly in application code (e.g., using C++AMP). In some embodiments, workitems are aggregated into structures called workgroups. Thus, a kernel may also have a certain number of workgroups in each of the multiple dimensions. The term “workgroup” is intended to be construed according to its well-understood meaning, which includes a portion of the operations in a compute kernel. Typically, compute work is sent to a shader core at workgroup granularity. Each workgroup may include multiple workitems. A “shader core” or “shader unit” refers to a processing element configured to execute shader programs. Typically, a GPU includes a large number of shader units for parallel processing. In addition to pixel and vertex shading programs, for example, shader cores may also be used to execute compute programs.

Note that, although shader cores and GPUs are discussed herein for purposes of illustration, the disclosed techniques are not limited to graphics processors, but may be applied to various parallel processor architectures. Similarly, although compute control streams are discussed herein, the disclosed techniques may be applied to any of various control streams, including control streams for vector or pixel work, for example.

Global barrier commands may indicate that all prior work in all sub streams should complete before proceeding past the barrier. Neighbor barrier commands may be used for substream synchronization, as discussed in further detail below. Note that the specific formatting and types of commands may vary among different implementations, including for different hardware that executes instructions of the same API.

Barrier clearing circuitry120, in some embodiments, is configured to receive state and barrier information from substream processors110and control their processing. For example, when one substream is dependent on another substream, barrier clearing circuitry120may pause the corresponding substream processor until the other substream has reached a specified point.

Example Control Stream

FIG. 2is a diagram illustrating example control stream elements, according to some embodiments. In the illustrated embodiment, control stream105includes two headers215A and215B, two commands210A and210B, and four kernels220A-220D. In the illustrated embodiment, control stream elements that are closer to the right-hand side ofFIG. 2are younger than control stream elements closer to the left.

Headers, in some embodiments, indicate the substream of subsequent commands and kernels, e.g., using a substream identifier217. In the illustrated example, kernels220A and220B are in one substream, as specified by substream identifier217A, while kernels220C-220D and commands210A and210B are in another substream, as specified by substream identifier217B. In some embodiments, each substream processor110is configured to store and parse control stream elements for its substream and discard or ignore elements for other substreams.

Commands210, in the illustrated embodiment, each include a command identifier212. In some embodiments, command identifiers are assigned according to a monotonic function, e.g., monotonically increasing. In some embodiments, command identifiers are uniquely assigned among all substreams in a control stream while in other embodiments command identifiers may be uniquely assigned within a substream (e.g., such that commands in different substreams may potentially have the same command identifier). In some embodiments, if a particular command does not have associated synchronization, then it may not be assigned a new command ID. In other embodiments, any of various appropriate techniques may be used to encode relative ages of commands within the overall stream or within substreams. In some embodiments, if software runs out of command identifiers for a control stream, it may reset and use a global barrier to ensure that the reset does not cause improper results.

As discussed above, a substream identifier217may identify a global substream that may be processed by all substream processors parsing the command stream. In some embodiments, this substream includes one or more global barriers that all substream processors should reach before any continue past the global barrier.

Neighbor barrier command210B, in the illustrated embodiment, includes two fields that may be used for synchronization with another substream. Identifier214specifies another substream on which the current substream depends. Command identifier213specifies a command identifier that the other substream should reach before the current substream continues. Compute workloads are often specified using task graphs with a mix of dependent and non-dependent kernels. The disclosed techniques may facilitate parsing and execution of such workloads. In particular, the disclosed circuitry and control stream encoding techniques may advantageously facilitate parallel processing of substreams for non-dependent kernels while efficiently handling kernel dependencies across substreams.

Example Synchronization for Neighbor Barrier

FIG. 3is a diagram illustrating example synchronization between substreams, according to some embodiments. In the illustrated embodiment, substream1includes a neighbor barrier command, which identifies substream3and a command identifier of “1234.” The substream processor for substream1sends the substream and command identifier of the neighbor barrier to barrier clearing circuitry120, which pauses parsing of substream1because substream3has not reached the indicated command identifier. Substream3includes command A and command N, with respective identifiers of “1220” and “1234.” In some embodiments, each time it processes a command, substream3indicates its most-recently-completed command identifier to barrier clearing circuitry120. In other embodiments, a substream processor may indicate its most-recently-completed command identifier in response to a command ID synchronization packet in its substream. In these embodiments, synchronization packets may be attached to other commands (e.g., cache flush, barrier, etc.) but are not attached for neighbor barrier commands. This may allow command ID synchronization points to stay in order relative to other commands and kernels.

In response to receiving an indication of completion of command N (which has a command identifier that is greater than or equal to the identifier from the neighbor barrier), barrier clearing circuitry120allows continued processing of substream1. In some embodiments, for a global barrier command, barrier clearing circuitry120stops all controlled substreams until they have all reached the global barrier command.

Detailed Example Substream Processors

FIG. 4is a block diagram illustrating substream processors in more detail, according to some embodiments. In the illustrated embodiment, a processor includes substream processors110A-110N, barrier clearing circuitry120, and kernel processor450. Each substream processor110, in the illustrated embodiment, includes a stream fetcher425, fetch parser430, indirect fetch circuitry435, execute parser440, and execute manager445.

Stream fetcher425, in some embodiments, is configured to fetch control stream data and store the data in a control stream data buffer. In some embodiments, a write pointer indicates the location for the next control stream data in the buffer. In some embodiments, stream fetcher425is configured to fetch control stream data sequentially until it is re-directed or stopped by downstream processing. This may result in pre-fetching control stream data that is not actually used, but may provide performance benefits, e.g., by avoiding memory fetch latency that may consume a substantial number of cycles. In some embodiments, the compute control stream data is stored sequentially, but also includes link packets that redirect the fetch address and indirect kernel packets that require indirect data accesses.

Fetch parser430, in some embodiments, is configured to examine at least a portion of the packet indicated by a fetch parse pointer to identify its packet type. In some embodiments, if the packet is a link, fetch parser430is configured to redirect stream fetcher425and invalidate all younger data and requests in the control stream data buffer and the memory hierarchy (not shown). Fetch parser430, in the illustrated embodiment, is configured to send indirect kernels to indirect fetcher435.

Indirect fetcher435, in some embodiments, is configured to perform indirect fetches (e.g., via a cache/memory hierarchy) and store return data. An “indirect” kernel refers to a kernel for which a memory access outside the compute command stream is needed. For example, a direct kernel may specify the size of the kernel in each dimension within the compute command stream while an indirect kernel may specify an address in the compute command stream. Indirect fetcher435may access this address in memory to determine information for the structure (such as the size of the kernel). Once return data is stored, indirect fetcher435is configured to notify downstream logic (e.g., execute parser440) that data is available. In some embodiments, indirect fetcher435includes a request queue for indirect kernels from fetch parser430. In some embodiments, this allows the fetch parser to work past indirect kernels in the control stream while waiting for indirect fetch returns.

In some embodiments, indirect fetches should not prefetch behind certain memory ordering operations such as barrier or wait-on-flush operations, e.g., because an instruction before these operations may alter the indirect data. Therefore, in some embodiments, fetch parser430is configured to maintain a counter that indicates the number of outstanding memory ordering operations. For example, fetch parser430may increment the counter for each encountered barrier and wait-on-flush and decrement the counter when one of those operations is executed. In some embodiments, fetch parser430may send indirect kernels to indirect fetcher435only when the counter value indicates that there are no outstanding older memory ordering operations of one or more monitored types. In some embodiments, the value of the counter may be re-loaded on a context load, e.g., by analyzing restored data in the control stream data buffer.

Execute parser440, in some embodiments, is configured to process packets identified by the execution parse pointer. Execute parser440may receive control stream data from two sources: the control stream data buffer of stream fetcher425and the indirect fetcher435. During operation, an execution parse pointer may lag behind the fetch parse pointer, which may increase ability to hide memory latency (e.g., by allowing the fetch parser430to identify links and indirect kernels quickly and begin handling these situations before execution parser440is ready for the packets). In the illustrated embodiment, for indirect kernels, indirect fetcher435is configured to indicate when the data is available to execute parser440. In some embodiments, once all of a given packet's data is present, execute parser440sends the packet in full form to execute manager445and increments the execution parse pointer. For example, full form compute kernels may be stored in a decoded format that is recognized by downstream circuitry (e.g., kernel processor450).

Execute manager445, in some embodiments, maintains a command queue, manages dependencies, and dispatches commands and kernels for execution. Kernel processor450, in some embodiments, is configured to break down kernels into smaller portions (e.g., workgroups or workitems) and dispatch the portions to execution circuitry (e.g., programmable graphics shader circuitry). In some embodiments, execute manager445maintains state information indicating the most-recently-completed command identifier for the substream processor and communicates this information to barrier clearing circuitry120. Barrier clearing circuitry120, in the illustrated embodiment, is configured to inform an execute manager445when it can proceed past a barrier command.

Example Method

FIG. 5is a flow diagram illustrating a method for processing a control stream, according to some embodiments. The method shown inFIG. 5may be used in conjunction with any of the computer circuitry, systems, devices, elements, or components disclosed herein, among others. In various embodiments, some of the method elements shown may be performed concurrently, in a different order than shown, or may be omitted. Additional method elements may also be performed as desired.

At510, in the illustrated embodiment, one or more storage elements store a control stream that includes kernels and commands for multiple substreams. In some embodiments, the command stream includes a global substream that is parsed by all substream processors in a set of substream processors parsing the control stream. In some embodiments, the stream is a compute control stream whose kernels are executed by a graphics processor.

At520, in the illustrated embodiment, substream processors in a set of multiple sub stream processors each fetch and parse portions of the control stream corresponding to an assigned substream. Note that this may include each substream controller fetching the entire substream and parsing out its assigned substream and the global substream. In some embodiments, the control stream includes header information that indicates the substream of subsequent kernels and commands and the substream processors may process their assigned substream based on the header information.

At530, in the illustrated embodiment, a substream processor, in response to a neighbor barrier command in the assigned substream that identifies another substream, communicates the identified other substream to the barrier clearing circuitry. In some embodiments, the substream processor, in response to the neighbor barrier command, communicates a first command identifier of the neighbor barrier command. In some embodiments, command identifiers are assigned to commands according to a monotonic function.

At540, in the illustrated embodiment, the barrier clearing circuitry determines whether to allow the assigned substream to proceed past the neighbor barrier command based on communication of a most-recently-completed command from of a substream processor to which the other substream is assigned.

In some embodiments, in response to a global barrier command in the global substream, a substream processor indicates the global barrier to the barrier clearing circuitry and the barrier clearing circuitry prevents the substream processors in the set from proceeding past the global barrier until each substream processor in the set has reached the global barrier command.

In some embodiments, a substream processor in the set is configured to process a stream link command in its assigned substream to fetch and parse a secondary control stream. The stream link command may be a stream link with return, which may redirect back to the assigned substream after processing the secondary control stream.

Example Device

Referring now toFIG. 6, a block diagram illustrating an example embodiment of a device600is shown. In some embodiments, elements of device600may be included within a system on a chip. In some embodiments, device600may be included in a mobile device, which may be battery-powered. Therefore, power consumption by device600may be an important design consideration. In the illustrated embodiment, device600includes fabric610, compute complex620input/output (I/O) bridge650, cache/memory controller645, graphics unit670, and display unit665. In some embodiments, device600may include other components (not shown) in addition to and/or in place of the illustrated components, such as video processor encoders and decoders, image processing or recognition elements, computer vision elements, etc.

The techniques disclosed herein may be utilized in various processors of various types of computing devices. For example, graphics unit670may include substream processors configured to parse kernels for execution by programmable shader675.

Fabric610may include various interconnects, buses, MUX's, controllers, etc., and may be configured to facilitate communication between various elements of device600. In some embodiments, portions of fabric610may be configured to implement various different communication protocols. In other embodiments, fabric610may implement a single communication protocol and elements coupled to fabric610may convert from the single communication protocol to other communication protocols internally.

In the illustrated embodiment, compute complex620includes bus interface unit (BIU)625, cache630, and cores635and640. In various embodiments, compute complex620may include various numbers of processors, processor cores and/or caches. For example, compute complex620may include1,2, or4processor cores, or any other suitable number. In one embodiment, cache630is a set associative L2 cache. In some embodiments, cores635and/or640may include internal instruction and/or data caches. In some embodiments, a coherency unit (not shown) in fabric610, cache630, or elsewhere in device600may be configured to maintain coherency between various caches of device600. BIU625may be configured to manage communication between compute complex620and other elements of device600. Processor cores such as cores635and640may be configured to execute instructions of a particular instruction set architecture (ISA) which may include operating system instructions and user application instructions.

Cache/memory controller645may be configured to manage transfer of data between fabric610and one or more caches and/or memories. For example, cache/memory controller645may be coupled to an L3 cache, which may in turn be coupled to a system memory. In other embodiments, cache/memory controller645may be directly coupled to a memory. In some embodiments, cache/memory controller645may include one or more internal caches.

As used herein, the term “coupled to” may indicate one or more connections between elements, and a coupling may include intervening elements. For example, inFIG. 6, graphics unit670may be described as “coupled to” a memory through fabric610and cache/memory controller645. In contrast, in the illustrated embodiment ofFIG. 6, graphics unit670is “directly coupled” to fabric610because there are no intervening elements.

Graphics unit670may include one or more processors and/or one or more graphics processing units (GPU's). Graphics unit670may receive graphics-oriented instructions, such as OPENGL®, Metal, or DIRECT3D® instructions, for example. Graphics unit670may execute specialized GPU instructions or perform other operations based on the received graphics-oriented instructions. Graphics unit670may generally be configured to process large blocks of data in parallel and may build images in a frame buffer for output to a display. Graphics unit670may include transform, lighting, triangle, and/or rendering engines in one or more graphics processing pipelines. Graphics unit670may output pixel information for display images. Programmable shader675, in various embodiments, may include highly parallel execution cores configured to execute graphics programs, which may include pixel tasks, vertex tasks, and compute tasks (which may or may not be graphics-related).

Display unit665may be configured to read data from a frame buffer and provide a stream of pixel values for display. Display unit665may be configured as a display pipeline in some embodiments. Additionally, display unit665may be configured to blend multiple frames to produce an output frame. Further, display unit665may include one or more interfaces (e.g., MIPI® or embedded display port (eDP)) for coupling to a user display (e.g., a touchscreen or an external display).

Example Computer-Readable Medium

The present disclosure has described various example circuits in detail above. It is intended that the present disclosure cover not only embodiments that include such circuitry, but also a computer-readable storage medium that includes design information that specifies such circuitry. Accordingly, the present disclosure is intended to support claims that cover not only an apparatus that includes the disclosed circuitry, but also a storage medium that specifies the circuitry in a format that is recognized by a fabrication system configured to produce hardware (e.g., an integrated circuit) that includes the disclosed circuitry. Claims to such a storage medium are intended to cover, for example, an entity that produces a circuit design, but does not itself fabricate the design.

FIG. 7is a block diagram illustrating an example non-transitory computer-readable storage medium that stores circuit design information, according to some embodiments. In the illustrated embodiment semiconductor fabrication system720is configured to process the design information715stored on non-transitory computer-readable medium710and fabricate integrated circuit730based on the design information715.

Design information715may be specified using any of various appropriate computer languages, including hardware description languages such as, without limitation: VHDL, Verilog, SystemC, SystemVerilog, RHDL, M, MyHDL, etc. Design information715may be usable by semiconductor fabrication system720to fabricate at least a portion of integrated circuit730. The format of design information715may be recognized by at least one semiconductor fabrication system720. In some embodiments, design information715may also include one or more cell libraries which specify the synthesis and/or layout of integrated circuit730. In some embodiments, the design information is specified in whole or in part in the form of a netlist that specifies cell library elements and their connectivity. Design information715, taken alone, may or may not include sufficient information for fabrication of a corresponding integrated circuit. For example, design information715may specify the circuit elements to be fabricated but not their physical layout. In this case, design information715may need to be combined with layout information to actually fabricate the specified circuitry.

Integrated circuit730may, in various embodiments, include one or more custom macrocells, such as memories, analog or mixed-signal circuits, and the like. In such cases, design information715may include information related to included macrocells. Such information may include, without limitation, schematics capture database, mask design data, behavioral models, and device or transistor level netlists. As used herein, mask design data may be formatted according to graphic data system (GDSII), or any other suitable format.

Semiconductor fabrication system720may include any of various appropriate elements configured to fabricate integrated circuits. This may include, for example, elements for depositing semiconductor materials (e.g., on a wafer, which may include masking), removing materials, altering the shape of deposited materials, modifying materials (e.g., by doping materials or modifying dielectric constants using ultraviolet processing), etc. Semiconductor fabrication system720may also be configured to perform various testing of fabricated circuits for correct operation.

In various embodiments, integrated circuit730is configured to operate according to a circuit design specified by design information715, which may include performing any of the functionality described herein. For example, integrated circuit730may include any of various elements shown inFIG. 1, 4, or6. Further, integrated circuit730may be configured to perform various functions described herein in conjunction with other components. Further, the functionality described herein may be performed by multiple connected integrated circuits.