Transformerless parallel AFE with ground current regulator

A transformerless parallel active rectifier system includes N multiphase common mode inductors directly connected to a shared multiphase AC input with no intervening transformer, and N active rectifiers coupled to respective ones of the N multiphase common mode inductors and having respective DC outputs coupled to a shared DC bus, where N is an integer greater than 1. The N active rectifiers have ground current regulators and are synchronized to provide DPWM switching control signals synchronized to one another to regulate their respective ground currents and concurrently regulate the shared DC bus voltage.

BACKGROUND INFORMATION

Active rectifiers, such as active front end (AFE) converters can rectify AC input power to generate DC output power, as well as regenerate power to a grid, control and regulate an output DC bus voltage with a boost factor, and provide unity power factor with minimum current distortion, such as less than 5% according to IEEE-519 standards. The active frond end converter can be used in motor drive applications where the DC output is connected to multiple inverters or to one inverter controlling motor speed and/or torque. The active front end converter can be also used in grid tie applications where the DC side is connected to DC bus supply such as one or more batteries, fuel cells, or solar cells, etc. Certain applications require parallel operation of two or more power converters. In one example, the DC outputs of two or more AFE power converters are connected together at a common DC bus. One application is a “hot standby” or a “high redundancy” system where parallel power converters support a critical load with the ability to continue operation when one converter fails or is taken offline for maintenance. In this example, the AFE converters are controlled autonomously and there is no direct communication between the AFE units. In other applications, parallel AFE converters operate concurrently using additional control means to coordinate the operation of the parallel units for balanced load sharing. One example is referred to as droop control, which can also be used in other applications such as paralleling electrical generators feeding the same grid.

BRIEF DESCRIPTION

In one aspect, a system includes first and second common mode inductors directly connected to a multiphase AC input with no intervening transformer, as well as first and second active rectifiers. The first active rectifier has a first rectifier AC input coupled to the first multiphase common mode inductor, a first rectifier DC output having first and second DC nodes, a first switch circuit, and a first controller. The second active rectifier has a second rectifier AC input coupled to the second multiphase common mode inductor, a second rectifier DC output coupled to the first rectifier DC output, a second switch circuit, and a second controller. The first and second controllers generate respective first and second DPWM switching control signals synchronized to one another to operate the respective switch circuits to regulate respective first and second ground currents and to regulate a DC bus voltage across the first and second DC nodes.

In another aspect, an apparatus includes a multiphase common mode inductor configured to be directly connected to a multiphase AC input, and an active rectifier. The active rectifier has a rectifier AC input, a rectifier DC output, a switch circuit, and a controller. The rectifier AC input is coupled to the multiphase common mode inductor, the rectifier DC output has first and second DC nodes, and the switch circuit is configured to selectively couple nodes of the rectifier AC input to the first and second DC nodes according to discontinuous pulse width modulation (DPWM) switching control signals. The controller is configured to generate the DPWM switching control signals to regulate a ground current of the active rectifier and to regulate a DC bus voltage across the first and second DC nodes.

In a further aspect, a method includes sampling AC input phase currents of a rectifier AC input, computing a ground current of an active rectifier based on the AC input phase currents, computing a ground current regulator output based on the ground current to regulate the ground current, computing a DC bus regulator modulation index to regulate a DC bus voltage, computing an adjusted modulation index based on the DC bus regulator modulation index and the ground current regulator output to concurrently regulate the ground current and the DC bus voltage, and generating discontinuous pulse width modulation (DPWM) switching control signals to operate a switch circuit of the active rectifier based on the adjusted modulation index.

DETAILED DESCRIPTION

Referring now to the figures, several embodiments or implementations are hereinafter described in conjunction with the drawings, wherein like reference numerals are used to refer to like elements throughout, and wherein the various features are not necessarily drawn to scale.

FIGS.1and1Ashow a power conversion system100having a multiphase power source102(e.g., a utility, generator or grid) that provides AC input power on a multiphase AC input103. The system100has a first multiphase common mode inductor104directly connected to a multiphase AC input, and a second multiphase common mode inductor105directly connected to the multiphase AC input. The illustrated example is a three-phase system with three AC phases A, B, and C, and the respective common mode inductors104and105(e.g., common mode reactors) have three windings would around a shared core to provide a common mode flux path. In one example, the respective common mode inductors104and105are MTE RXL-0600-001 reactors from MTE Corporation of Menomonee Falls, Wis. Further common mode inductors are described in U.S. Pat. No. 7,768,373, granted Aug. 3, 2010 to Shudarek and U.S. Pat. No. 9,613,745, granted Apr. 4, 2017 to Shudarek, which are incorporated by reference herein.

The system100includes parallel active rectifiers coupled to a shared or common DC bus106having a first DC node107(e.g., labeled “−” inFIG.1) and a second DC node108(e.g., labeled “+” inFIG.1) to provide and control a DC bus voltage VDC across the first and second DC nodes107and108. One or more DC loads109can be connected to the DC bus106, such as inverters to drive an AC motor, as well as one or more batteries, fuel cells, or solar cells, etc. that can selectively consume DC power from the bus106or supply power to the bus106for regeneration by the active rectifier(s) to supply AC power to the multiphase power source102.

A first active rectifier110has a first rectifier AC input coupled to the first multiphase common mode inductor104. The first active rectifier110has a first rectifier DC output that forms or is coupled to the first and second DC nodes107and108. The first active rectifier110includes a communications interface or link circuit111to provide a communications connection first active rectifier110and one or more further active rectifiers for synchronizing pulse width modulation (PWM) switching control signals thereof.

The first active rectifier110in one example includes a first multiphase LCL filter112and a first switch circuit113. The first multiphase LCL filter112is coupled between the first multiphase common mode inductor104and the first switch circuit113. The first multiphase LCL filter112is a three-phase filter with individual LCL phase circuits having a first inductor and a second inductor coupled in series between an associated phase line of the first multiphase common mode inductor104and an associated phase line of the first switch circuit113, as well as a capacitor coupled between the node that joins the two inductors and a common connection, where the three filter capacitors are connected to one another at the common connection. In one example, the common connection of the first multiphase LCL filter112is grounded, for example, to a ground reference of the multiphase power source102. In another example, the common connection of the first multiphase LCL filter112is connected to another reference node of the system100. In another example, the common connection of the first multiphase LCL filter112is floating. In another implementation, the multiphase LCL filter112is replaced with a different input filter, such as a multiphase LC filter circuit (not shown). In another implementation, the multiphase LCL filter112is omitted.

The first active rectifier110includes a first switch circuit113with AC nodes coupled to the first multiphase common mode inductor104through the first multiphase LCL filter112(or coupled directly to the first multiphase common mode inductor104if the filter112is omitted). The first switch circuit113also provides the first rectifier DC output that forms or is coupled to the first and second DC nodes107and108.FIG.1Ashows one example, in which the first switch circuit113includes switching devices S1-S6individually connected between a corresponding one of the respective AC nodes and a corresponding DC node107or108of the shared DC bus. The individual switching devices S1-S6are configured to selectively couple a respective one of the AC nodes with a respective one of the first and second DC nodes107and108according to a respective switching control signal.

The first active rectifier110includes a first controller that includes a first ground current regulator114configured to regulate a first ground current I01(e.g., zero sequence current I0) of the first active rectifier110. In one example, the first ground current regulator114regulates the first ground current I01to zero to mitigate (e.g., minimize) the ground current in the first active rectifier110in a closed loop fashion. The first active rectifier110includes current sensors115configured to sense respective AC input phase currents Ia1, Ib1, and Ic1of the first rectifier AC input. The first ground current regulator114provides a first ground current regulator output GCRO1as a signal or value used by the first controller to regulate the ground current I0.

The first controller of the first active rectifier110includes a first DC bus regulator116configured to regulate the DC bus voltage VDC. The first DC bus regulator116has an input to receive a DC bus voltage feedback signal and an output that provides a first bus regulator modulation index MI1as a signal or value to regulate the DC bus voltage VDC based on the DC bus voltage feedback signal and a setpoint signal or value. The first controller includes a first summer117with inputs that receive the first ground current regulator output GCRO1and the first bus regulator modulation index MIL The first summer117has an output that provides a first adjusted or final modulation index MIF1based on the DC bus regulator modulation index MI1and the ground current regulator output GCRO1to concurrently regulate the ground current I01and the DC bus voltage VDC. In one implementation, the first summer117provides the first adjusted or final modulation index MIF1as the sum of the DC bus regulator modulation index MI1and the ground current regulator output GCRO1(e.g., MIF1=MI1+GCRO1).

The first controller of the first active rectifier110in one example includes a limiter118that limits the modulation index to be less than a limit value, such as 1.15. In another implementation, the limiter118is omitted. In the illustrated example, the limiter118limits the first adjusted modulation index MIF1to less than 1.15 and provides a first limited modulation index MIL1as a signal or value. Other limit values can be used in other examples. In another implementation, the limiter118is omitted.

The first controller of the first active rectifier110also includes a first discontinuous pulse width modulation (DPWM) signal generator119that generates first DPWM switching control signals141for operating the first switch circuit113based on the first ground current regulator output GCRO1of the first ground current regulator114and the first bus regulator modulation index MI1of the first DC bus regulator116to regulate the first ground current I01of the first active rectifier110and to regulate the DC bus voltage VDC. In the illustrated example, the first DPWM signal generator119generates the first DPWM switching control signals141based on the first limited modulation index MIL1(or on the first adjusted modulation index MIF1if the limiter118is omitted. In one example, the first DPWM signal generator119generates the first DPWM switching control signals141at a switching frequency of 10 kHz or less, such as 1-5 kHz, for example, 3-4 kHz.

The first switch circuit113is configured to selectively couple nodes of the first rectifier AC input (directly or through any included LC OR LCL filter112) to the first and second DC nodes107and108according to the first DPWM switching control signals141. The switching circuit113inFIG.1Aincludes a driver circuit140that provides the switching control signals141to the respective switching devices S1-S6under control of a processor150of the first controller. When powered and operating, the first controller operates the switches S1-S6of the first switch circuit113to convert AC power to provide and regulate the DC bus voltage VDC in a first operating mode, or to regenerate power from the DC bus106to deliver three-phase AC power to the multiphase AC input103in a second (e.g., regenerating) operating mode. Moreover, the first controller concurrently regulates the first ground current I01of the first active rectifier110to zero to mitigate (e.g., minimize) the ground current in the first active rectifier110in a closed loop fashion while regulating the DC bus voltage VDC.

The system100also includes a second active rectifier120. The first communications interface circuit111provides a high-speed communications link130between the first active rectifier110and the second active rectifier120to synchronize the first DPWM switching control signals141of the first active rectifier110to second DPWM switching control signals142of the second active rectifier120. In one example, the first communications interface circuit111is coupled to a communications interface circuit121of the second active rectifier120, for example, by a fiber optic connection, to synchronize the switching control signals141and142of the respective active rectifiers110and120to one another, for example, within a time tolerance of 3 us. In one implementation, the communications interface circuits111and121are or include two TLink option modules installed in two or more drives or dedicated active rectifiers110and120that are connected by a fiber-optic cable to provide the communications link130. In one example, the first active rectifier110is considered the leader and the second active rectifier120is considered a follower. The TLink option modules111and121provide synchronization of the active rectifiers110and120to share data from the leader to one or more followers.

As shown inFIG.1, the system100includes the second multiphase common mode inductor105and the second active rectifier120coupled in parallel with the first multiphase common mode inductor104and the first active rectifier110between the multiphase AC input103and the DC bus106. In another example, the system100includes more than two parallel active rectifiers and associated multiphase common mode inductors. In one example, the second active rectifier120is constructed similarly to the first active rectifier110as shown inFIG.1A. The second active rectifier120inFIG.1has a second rectifier AC input coupled to the second multiphase common mode inductor105. The second active rectifier120has a second rectifier DC output that forms or is coupled to the first and second DC nodes107and108. The second active rectifier120includes a communications interface or link circuit121to provide a communications connection second active rectifier120and one or more further active rectifiers for synchronizing pulse width modulation (PWM) switching control signals thereof.

The second active rectifier120in one example includes a second multiphase LCL filter122and a second switch circuit123. The second multiphase LCL filter122is coupled between the second multiphase common mode inductor105and the second switch circuit123. The second multiphase LCL filter122is a three-phase filter with individual LCL phase circuits having a first inductor and a second inductor coupled in series between an associated phase line of the second multiphase common mode inductor105and an associated phase line of the second switch circuit123, as well as a capacitor coupled between the node that joins the two inductors and a common connection, where the three filter capacitors are connected to one another at the common connection. In one example, the common connection of the second multiphase LCL filter122is grounded, for example, to the ground reference of the multiphase power source102. In another example, the common connection of the second multiphase LCL filter122is connected to another reference node of the system100. In another example, the common connection of the second multiphase LCL filter122is floating. In another implementation, the multiphase LCL filter122is replaced with a different input filter, such as a multiphase LC filter circuit (not shown). In another implementation, the multiphase LCL filter122is omitted.

The second active rectifier120includes a second switch circuit123with AC nodes coupled to the second multiphase common mode inductor105through the second multiphase LCL filter122(or coupled directly to the second multiphase common mode inductor105if the filter122is omitted). The second switch circuit123also provides the second rectifier DC output that forms or is coupled to the first and second DC nodes107and108. The second switch circuit123in one implementation includes switching devices (e.g., similar to switches S1-S6of the first switching circuit113inFIG.1A) individually connected between a corresponding one of the respective AC nodes and a corresponding DC node107or108of the shared DC bus to selectively couple a respective one of the AC nodes with a respective one of the first and second DC nodes107and108according to a respective second DPWM switching control signal142.

The second active rectifier120includes a second controller that includes a second ground current regulator124configured to regulate a second ground current I02(e.g., zero sequence current I02) of the second active rectifier120. In one example, the second ground current regulator124regulates the second ground current I02to zero to mitigate (e.g., minimize) the ground current in the second active rectifier120in a closed loop fashion. The second active rectifier120includes current sensors125configured to sense respective AC input phase currents Ia2, Ib2, and Ic2of the second rectifier AC input. The second ground current regulator124provides a second ground current regulator output GCRO2as a signal or value used by the second controller to regulate the second ground current I02. The second controller of the second active rectifier120includes a second DC bus regulator126configured to regulate the DC bus voltage VDC. The second DC bus regulator126has an input to receive the DC bus voltage feedback signal and an output that provides a second bus regulator modulation index MI2as a signal or value to regulate the DC bus voltage VDC based on the DC bus voltage feedback signal and based on a setpoint signal or value. The second controller includes a second summer127with inputs that receive the second ground current regulator output GCRO2and the second bus regulator modulation index MI2. The second summer127has an output that provides a second adjusted or final modulation index MIF2based on the DC bus regulator modulation index MI2and the ground current regulator output GCRO2to concurrently regulate the second ground current I02and the DC bus voltage VDC. In one implementation, the second summer127provides the second adjusted or final modulation index MIF2as the sum of the DC bus regulator modulation index MI2and the ground current regulator output GCRO2(e.g., MIF2=MI2+GCRO2).

The second controller of the second active rectifier120in one example includes a limiter128that limits the modulation index to be less than a limit value, such as 1.15. In another implementation, the limiter128is omitted. In the illustrated example, the limiter128limits the second adjusted modulation index MIF2to less than 1.15 and provides a second limited modulation index MIL2as a signal or value. Other limit values can be used in other examples. In another implementation, the limiter128is omitted.

The second controller of the second active rectifier120also includes a second discontinuous pulse width modulation (DPWM) signal generator129that generates second DPWM switching control signals142for operating the second switch circuit123based on the second ground current regulator output GCRO2of the second ground current regulator124and the second bus regulator modulation index MI2of the second DC bus regulator126to regulate the second ground current I02of the second active rectifier120and to regulate the DC bus voltage VDC. In the illustrated example, the second DPWM signal generator129generates the second DPWM switching control signals142based on the second limited modulation index MIL2(or on the second adjusted modulation index MIF2if the limiter128is omitted. In one example, the second DPWM signal generator129generates the second DPWM switching control signals142at a switching frequency of 10 kHz or less, such as 1-5 kHz, for example, 3-4 kHz.

The second switch circuit123is configured to selectively couple nodes of the second rectifier AC input (directly or through any included LC OR LCL filter122) to the first and second DC nodes107and108according to the second DPWM switching control signals142. The switching circuit123in one example includes a driver circuit (e.g., similar to the driver circuit140inFIG.1A) that provides the switching control signals142to the respective switching devices of the second switch circuit123under control of a processor of the second controller (e.g., similar to processor150inFIG.1A). When powered and operating, the second controller operates the switches S1-S6of the second switch circuit123to convert AC power to provide and regulate the DC bus voltage VDC in a first operating mode, or to regenerate power from the DC bus106to deliver three-phase AC power to the multiphase AC input103in a second (e.g., regenerating) operating mode. Moreover, the second controller concurrently regulates the second ground current I02of the second active rectifier120to zero to mitigate (e.g., minimize) the ground current in the second active rectifier120in a closed loop fashion while regulating the DC bus voltage VDC.

In one implementation, the first and second controllers are implemented by a corresponding processor of the respective active rectifiers110and120.FIG.1Ashows one example of the first controller implemented as processor executable program instructions stored in an electronic memory152for execution by the processor150. In this example, the processor150executes program instructions to implement the ground current regulator114, the DC bus regulator116, the summer117, the limiter118and the DPWM signal generator119. The communications connection111,121,130between the first and second controllers provides synchronization, and the first and second controllers generate the respective first and second DPWM switching control signals141and142synchronized to one another.

The system100inFIGS.1and1Aadvantageously facilitates parallel active rectifier operation without an isolation transformer, while regulating ground currents in the individual rectifiers110and120. Isolation transformers add significant extra cost and size to parallel rectifier systems and may require extra protection components in the system. For existing facilities, adding an extra transformer may not be feasible or possible, and the disclosed example provide a cost effective and compact solution with controlled circulating ground currents and DC bus voltage regulation.

FIG.2shows a method200that can be implemented concurrently in the individual active rectifiers110and120of the above system100. The method200includes sampling AC input phase currents at202(e.g., currents Ia, Ib, Ic of a rectifier AC input). At204, the ground current (I0) of the active rectifier is computed based on the AC input phase currents. In one example, the rectifier ground current I0is computed at204as the sum of the sampled AC input phase currents (e.g., I0=Ia+Ib+Ic). At206, a ground current regulator output GCRO is computed based on the computed ground current I0to regulate the ground current I0. In one example, the first and second ground current regulators114and124are or include proportional-integral (PI) controllers or regulators that compute the respective ground current regulator outputs GCRO1and GCRO2based on the respective computed ground currents I01and I02and proportional and integral scaling factors or constants Kp and Ki, respectively (e.g., GCRO=(Kp+Ki/s)*I0), where the PI factors Kp and Ki can be the same or different for the respective first and second ground current regulators114and124.

The method200continues at208with computing the DC bus regulator output modulation index MI1to regulate the DC bus voltage VDC. In one example, the DC bus voltage regulators116and126are or include PI controllers programmed with corresponding factors Kp and Ki and the DC bus voltage regulators116and126compute the respective bus regulator output modulation indexes MI1and MI2based on the DC bus voltage feedback signal and a setpoint signal or value at208. At210, the controllers compute the adjusted modulation index MIF based on the DC bus regulator modulation index MI and the ground current regulator output GCRO1for the respective active rectifiers110and120to concurrently regulate the ground current I0and the DC bus voltage VDC (e.g., MIF=MI+CGRO). At212, the method200includes limiting the adjusted modulation index MIF to less than 1.15. In another implementation, the limiting at212is omitted. At214, the DPWM switching control signals141and142are generated by the DPWM signal generators119and129to operate the respective switch circuits113and123of the active rectifiers110and120based on the adjusted modulation indexes MIF1and MIF2. At216in one example, the DPWM switching control signals141and142are synchronized, for example to within 3 us. The method200then repeats for further rectifier switching control cycles.

FIG.3shows another example transformerless system300with N parallel active rectifiers and N associated, where N is an integer greater than 1. The system300includes a first active rectifier110and an Nth active rectifier320having respective multiphase common mode inductors104and305coupled to a shared multiphase AC input, as well as current sensors (not shown) to sense respective AC input phase currents Ia1, Ib1, Id1and IaN, IbN, IcN of the rectifier AC inputs. The individual active rectifiers have features as described above with internal ground current regulators (e.g.,114above). The N active rectifiers are synchronized (e.g., by a communications interface130) to provide DPWM switching control signals synchronized to one another as discussed above to regulate their respective ground currents and operate to concurrently regulate the shared DC bus voltage VDC.

Various embodiments have been described with reference to the accompanying drawings. Modifications and changes may be made thereto, and additional embodiments may be implemented, without departing from the broader scope of the invention as set forth in the claims that follow. The specification and drawings are accordingly to be regarded in an illustrative rather than restrictive sense. The above examples are merely illustrative of several possible embodiments of various aspects of the present disclosure, wherein equivalent alterations and/or modifications will occur to others skilled in the art upon reading and understanding this specification and the annexed drawings. In addition, although a particular feature of the disclosure may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular application. Also, to the extent that the terms “including”, “includes”, “having”, “has”, “with”, or variants thereof are used in the detailed description and/or in the claims, such terms are intended to be inclusive in a manner similar to the term “comprising”.