Semiconductor device including relay chip

A semiconductor device includes a relay chip configured to be connected to a host; a first chip connected to the relay chip via a first channel; and a second chip connected to the relay chip via a second channel. The relay chip is configured to receive, from the host, a first enable signal for selecting the first channel and a second enable signal for selecting the second channel. During a first period in which the first enable signal is maintained at a non-active level and the second enable signal is maintained at an active level, the relay chip is configured to perform, in parallel, a first data transfer operation via the first channel and a first command issuing operation via the second channel.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2021-096711, filed Jun. 9, 2021, the entire contents of which are incorporated herein by reference.

FIELD

BACKGROUND

A semiconductor device in which a relay chip is interposed between an external terminal connected to a host and a plurality of chips is known. In such a semiconductor device, an access from the host to the plurality of chips is performed via the relay chip. It is generally desired to access the chips with a high speed.

DETAILED DESCRIPTION

Embodiments provide a semiconductor device capable of accessing a plurality of chips at a high speed.

In general, according to one embodiment, a semiconductor device includes a relay chip configured to be connected to a host; a first chip connected to the relay chip via a first channel; and a second chip connected to the relay chip via a second channel. The relay chip is configured to receive, from the host, a first enable signal for selecting the first channel and a second enable signal for selecting the second channel. During a first period in which the first enable signal is maintained at a non-active level and the second enable signal is maintained at an active level, the relay chip is configured to perform, in parallel, a first data transfer operation via the first channel and a first command issuing operation via the second channel.

Hereinafter, semiconductor devices according to embodiments will be described in detail with reference to the accompanying drawings. The present disclosure is not limited to the embodiments.

First Embodiment

A semiconductor device according to a first embodiment is equipped with a plurality of chips and may be connected to a host via a communication path. The semiconductor device is, for example, a nonvolatile memory device including a NAND flash memory, and includes a plurality of chips each of which is, for example, a NAND flash memory chip. With the speed of the communication path increasing, there is a demand for an increase in the number of chips connected to the communication path to increase the capacity of the semiconductor device. Recently, the number of chips mounted on the semiconductor device has been increasing to improve the mounting density, and the mounting density is improved by stacking the chips. At this time, a relay chip called a frequency boosting interface (FBI) chip may be added between the communication path and the plurality of chips. In such a semiconductor device, the relay chip is configured to be connected to the communication path, and the relay chip and the plurality of chips are configured to communicate with each other via a plurality of channels. As a result, the load of a transmission line may be distributed and a high-speed operation is possible even when a large number of chips are mounted on the semiconductor device.

However, in this configuration, data between the host and the plurality of chips is transferred via the relay chip. At this time, in the semiconductor device, if data transfer cannot be performed via one of the plurality of channels while another one of the plurality of channels is being selected, the latency in the data transfer tends to increase. This might deteriorate the data transfer performance between the host and the plurality of chips.

Therefore, in the semiconductor device of the present embodiment, the relay chip enables the operation of accessing the plurality of chips in parallel via the plurality of channels (inter-channel interleaving operation), thereby improving the data transfer performance between the host and the plurality of chips via the relay chip.

Specifically, the relay chip that may be connected to the host is connected to a first chip via a first channel, and connected to a second chip via a second channel, to configure the semiconductor device. The relay chip receives a first enable signal and a second enable signal from the host. The first enable signal is a signal for selecting the first channel. The second enable signal is a signal for selecting the second channel. During a first period in which the first enable signal is maintained at a non-active level and the second enable signal is maintained at an active level, the relay chip is able to perform, in parallel, a data transfer operation via the first channel and a command issuing operation via the second channel As a result, the data transfer between the host and the plurality of chips via the relay chip may be efficiently performed. That is, the data transfer performance between the host and the plurality of chips may be improved.

More specifically, a memory system100that includes a semiconductor device1is configured as illustrated inFIG.1.FIG.1is a diagram illustrating the configuration of the memory system100that includes the semiconductor device1.

The memory system100includes a host HA and the semiconductor device1. The semiconductor device1includes a relay chip IF and a plurality of chips MC0-1to MC0-4and MC1-1to MC1-4. Hereinafter, any one of the plurality of chips MC0-1to MC0-4may be referred to as a chip MC0. Similarly, any one of the plurality of chips MC1-1to MC1-4may be referred to as a chip MC1. In the semiconductor device1, the chips MC0-1to MC0-4may be stacked and the chips MC1-1to MC1-4may be stacked separately from the chips MC0-1to MC0-4. In the semiconductor device1, the periphery of the relay chip IF and the plurality of chips MC0-1to MC0-4and MC1-1to MC1-4may be sealed with a mold resin.FIG.1illustrates a configuration where the four chips MC0-1to MC0-4are connected to the relay chip IF via a channel Ch0, and the four chips MC1-1to MC1-4are connected to the relay chip IF via a channel Ch1. That is, the semiconductor device1may be configured as a multi-chip module including the plurality of (here, eight) chips MC0-1to MC0-4and MC1-1to MC1-4. For example, the semiconductor device1is a nonvolatile memory such as a NAND flash memory, and each of the chips MC0-1to MC0-4and MC1-1to MC1-4is a memory chip.

The host HA may be a device such as a controller, or a processor provided in an electronic apparatus such as a computer or a mobile terminal to control the semiconductor device1. The semiconductor device1may be connected to the host HA via a communication path. The communication path is, for example, a serial bus. The communication path functions as a channel which is a collection of communication paths between the host HA and the semiconductor device1. Hereinafter, the communication path will be referred to as a host channel HCh to distinguish from the channels (e.g., Ch0 and Ch1) inside the semiconductor device1. The semiconductor device1and the host HA are connected to each other via the host channel HCh configured based on a predetermined standard. When the host is a computer, a mobile terminal, or the like and each of the chips MC0-1to MC0-4and MC1-1to MC1-4is a NAND flash memory, the predetermined standard is, for example, an eMMC standard, a PCIe standard, an M-PHY standard, or the like. For example, the host channel HCh functions as an eMMC interface. When the host is a memory controller, and each of the chips MC0-1to MC0-4and MC1-1to MC1-4is a NAND flash memory, the predetermined standard is, for example, a toggle DDR standard, an ONFI standard, or the like. For example, the host channel HCh functions as a toggle DDR interface.

The relay chip IF is electrically connected between the host channel HCh and a plurality of (here, two) channels Ch0 and Ch1. The relay chip IF may be electrically connected to the host HA via the host channel HCh. The plurality of chips MC0-1to MC0-4and MC1-1to MC1-4are connected to the relay chip IF via the plurality of channels Ch0 and Ch1. The relay chip IF and each of the chips MC0-1to MC0-4and MC1-1to MC1-4are connected via the channels Ch0 and Ch1 respectively that are configured based on a predetermined standard.

Each chip MC may be configured as illustrated inFIG.2.FIG.2is a diagram illustrating an example of the configuration of a chip MC.

The chip MC is, for example, a memory chip and includes a memory cell array2, a peripheral circuit3, a register4, an input/output circuit5, and a terminal group6. The terminal group6of the chip MC and a terminal group22of the relay chip IF are connected via the channel Ch.

In the memory cell array2, a plurality of memory cells are arranged two-dimensionally or three-dimensionally. The peripheral circuit3and the register4are respectively arranged around the memory cell array2and connected to the memory cell array2. The peripheral circuit3may be disposed between the register4, the input/output circuit5, and the terminal group6, and connected to the register4, the input/output circuit5, and the terminal group6. The input/output circuit5may be disposed between the register4and the terminal group6, and connected to the register4and the terminal group6.

The peripheral circuit3controls an access to each memory cell of the memory cell array2, by using the register4and the input/output circuit5, in response to a command received from the relay chip IF via the channel Ch and the terminal group6. When the peripheral circuit3receives a read command from the relay chip IF via the channel Ch and the terminal group6, the peripheral circuit3performs a read process to each memory cell of the memory cell array2.

For example, the read process for the memory cell array2is performed in a sequence illustrated inFIGS.3A and3B.FIGS.3A and3Bare diagrams illustrating the sequence of the read process.FIGS.3A and3Brepresent a waveform of each signal exchanged between the host HA and the semiconductor device1in the read process.

A chip enable signal CE−is a signal for enabling a chip at an active level (low(L) level). A command latch enable signal CLE is a signal for notifying that a data signal DQ is a command at an active level (high(H) level). An address latch enable signal ALE is a signal for notifying that the data signal DQ is an address at an active level (H level). The write enable signal WE−is a signal for enabling a write access at an active level (L level). Read enable signals RE−/RE are a signal for enabling a read process at an active level (L level/H level). The read enable signal RE−and the read enable signal RE form a pair of differential signals. Data strobe signals DQS/DQS−are a timing signal for notifying the host HA to fetch transferred data in read process. The data strobe signal DQS and the data strobe signal DQS−form a pair of differential signals. The data signal DQ is a data signal exchanged between the host HA and the semiconductor device1. A ready busy signal R/B−is a signal indicating whether or not the semiconductor device1is accessible. The ready busy signal R/B−indicates that the semiconductor device1is in a ready state (accessible) at an H level, and indicates that the semiconductor device1is in a busy state (inaccessible) at an L level.

In the sequence of the read process, each signal transitions as illustrated inFIG.3A. At timing t1, when the chip enable signal CE−is asserted, and the command latch enable signal CLE is asserted, a page designation command “01h/02h/03h” to designate a read target page (e.g., lower page, middle page, or upper page) and a sense operation command “00h” are transferred in this order as the data signal DQ from the host HA to the semiconductor device1.

At timing t2, when the command latch enable signal CLE is de-asserted, and the address latch enable signal ALE is asserted, addresses “ADD” such as a column address and a row address are transferred as the data signal DQ from the host HA to the semiconductor device1.

At timing t3, when the address latch enable signal ALE is de-asserted, and the command latch enable signal CLE is asserted, a sense start command “30h” is transferred as the data signal DQ from the host HA to the semiconductor device1.

In response to the sense start command “30h”, in a period tR of timing t4to t5, the peripheral circuit3of the chip MC sets the voltage of a selected word line to a read voltage, and sets the voltage of a non-selected word lines to a non-selective voltage. The peripheral circuit3of the chip MC performs a sense operation on a designated page of a memory cell group designated by the row address. The peripheral circuit3of the chip MC transfers data for one page read by the sense operation to the register4, and stores the data in the register4. During the period tR, the ready busy signal R/B−is maintained busy (low level). Meanwhile, before and after the period tR, the ready busy signal R/B−is maintained as ready (high level).

At timing t6, when the command latch enable signal CLE is asserted, a transfer command “05h” is transferred as the data signal DQ from the host HA to the semiconductor device1.

At timing t7, when the command latch enable signal CLE is de-asserted, and the address latch enable signal ALE is asserted, addresses “ADD” such as a column address and a row address are transferred as the data signal DQ from the host HA to the semiconductor device1.

At timing t8, when the address latch enable signal ALE is de-asserted, and the command latch enable signal CLE is asserted, an output start command “E0h” is transferred as the data signal DQ from the host HA to the semiconductor device1.

In response to the output start command “E0h”, the relay chip IF performs a prefetch operation during a period tWHR2of timings t9to t10. That is, the peripheral circuit3of the chip MC transfers data in the register4designated by the column address to the input/output circuit5, and transfers at least some of the data which have been transferred to the input/output circuit5, to the relay chip IF via the terminal group6, the channel Ch, and the terminal group22. The relay chip IF stores (prefetches) the transferred data in a predetermined circuit.

At timing t11, the read enable signals RE−/RE from the host HA to the semiconductor device1start to be toggled.

In response to the read enable signals RE−/RE, during a period from timing t12to t13, the relay chip IF toggles the data strobe signals DQS/DQS−according to the read enable signal RE−/RE, outputs the data strobe signals DQS/DQS−to the host HA, and outputs the data signal DQ which is transferred from the chip MC to the host HA.

In the following, the command sequence of the read process illustrated inFIG.3Ais simplified as illustrated inFIG.3B. That is, the commands of the timings t1to t4are represented by “00h to 30h”, the commands of the timings t6to t9are represented by “05h to E0h”, and the operations of the timings t12to t13are represented by “DOUT”. The sense operation according to “00h to 30h” is performed in the period tR of the timings t4to t5. The prefetch operation according to “05h to E0h” is performed in the period tWHR2of the timings t9to t10. Further, a period that includes the period of “05h to E0h”, the period tWHR2, and a period of “DOUT” is defined as tTR. During the period of “05h to E0h”, a command for data transfer is issued. In the period tWHR2, the data transfer (prefetch) operation from the chip MC to the relay chip IF via the channel Ch is performed. During the period of “DOUT”, the data transfer operation from the chip MC or the predetermined circuit to the host HA via the channel Ch and the relay chip IF is performed. Hereinafter, a process including the command issuing operation for the data transfer and the data transfer operation is called a data transfer process. The period tTR is a period during which the data transfer process is performed.

As illustrated inFIG.4, the semiconductor device1is able to perform an inter-channel interleaving operation.FIG.4is a diagram illustrating the operation of the semiconductor device1, and represents the inter-channel interleaving operation performed while alternately selecting the channels Ch0 and Ch1 for the read process. InFIG.4, the illustration of the sense operation is omitted for the sake of simplicity.

The host HA generates different chip enable signals CE0−and CE1−for the channels Ch0 and Ch1 and transmits the chip enable signals to the semiconductor device1via the host channel HCh. The chip enable signal CE0−is transmitted as a signal for selecting the channel Ch0 from the host HA. The chip enable signal CE0−indicates that the channel Ch0 should be selected at an active level (e.g., low level) and that the channel Ch0 should be non-selected at a non-active level (e.g., high level). The chip enable signal CE1−is transmitted as a signal for selecting the channel Ch1 from the host HA. The chip enable signal CE1−indicates that the channel Ch1 should be selected at an active level (e.g., low level) and that the channel Ch1 should be non-selected at a non-active level (e.g., high level).

When the chip enable signals CE0−and CE1−are received from the host HA via the host channel HCh, the semiconductor device1performs an operation according to the levels of the chip enable signals CE0−and CE1.

For example, when a period TP1starts, the relay chip IF selects the channel Ch0 according to the transition of the chip enable signal CE0−to the active level, and keeps the channel Ch1 non-selected as the chip enable signal CE1−is maintained at the non-active level. In this state, the relay chip IF transfers the commands “00h to 30h” received via the host channel HCh to the chip MC0as a data signal DQ[Ch0] via the channel Ch0.

When the period TP1ends and a period TP2starts, the relay chip IF non-selects the channel Ch0 according to the transition of the chip enable signal CE0−to the non-active level, and selects the channel Ch1 according to the transition of the chip enable signal CE1−to the active level. In this state, the relay chip IF transfers the commands “00h to 30h” received via the host channel HCh to the chip MC1as a data signal DQ[Ch1] via the channel Ch1.

In periods TP3to TP8, the same operation as the period TP1and the same operation as the period TP2are alternately performed.

When the period TP8ends and a period TP9starts, the relay chip IF selects the channel Ch0 according to the transition of the chip enable signal CE0−to the active level and non-selects the channel Ch1 according to the transition of the chip enable signal CE1−to the non-active level. In this state, the relay chip IF transfers the commands “05h to E0h” received via the host channel HCh to the chip MC0as the data signal DQ[Ch0] via the channel Ch0.

When the period TP9ends and a period TP10starts, the relay chip IF non-selects the channel Ch0 according to the transition of the chip enable signal CE0−to the non-active level, and selects the channel Ch1 according to the transition of the chip enable signal CE1−to the active level. In this state, the relay chip IF transfers the commands “05h to E0h” received via the host channel HCh to the chip MC1as the data signal DQ[Ch1] via the channel Ch1.

At this time, the relay chip IF performs a prefetch operation via the non-selected channel Ch0. That is, the peripheral circuit3of the chip MC0transfers the read data in the register4designated by the column address to the input/output circuit5, and transfers at least some of the read data which have been transferred to the input/output circuit5, to the relay chip IF as the data signal DQ[Ch0] via the terminal group6and the channel Ch0. The relay chip IF stores (prefetches) the transferred data signal DQ[Ch0] in a predetermined circuit.

When the period TP10ends and a period TP11starts, the relay chip IF selects the channel Ch0 according to the transition of the chip enable signal CE0−to the active level, and non-selects the channel Ch1 according to the transition of the chip enable signal CE1−to the non-active level. In this state, the relay chip IF performs the data transfer operation from the chip MC0or the predetermined circuit to the host HA via the relay chip IF. During the period TP11, first, the relay chip IF transfers the prefetched data signal DQ[Ch0] to the host HA as the data signal DQ[HCh] via the host channel HCh. In parallel to the transfer of the prefetched data signal DQ[Ch0], the relay chip IF stores the data signal DQ[Ch0] transferred from the chip MC0via the channel Ch0 in response to the operation “DOUT”, and transfers the stored data signal DQ[Ch0] to the host HA as the data signal DQ[HCh] via the host channel HCh.

At this time, the relay chip IF performs a prefetch operation via the non-selected channel Ch1. That is, the peripheral circuit3of the chip MC1transfers the read data in the register4designated by the column address to the input/output circuit5, and transfers at least some of the read data which have been transferred to the input/output circuit5, to the relay chip IF as the data signal DQ[Ch1] via the terminal group6and the channel Ch1. The relay chip IF stores (prefetches) the transferred data signal DQ[Ch1] in a predetermined circuit.

When the data transfer to the host HA is completed, the relay chip IF transfers the commands “00h to 30h” received via the host channel HCh to the chip MC0as the data signal DQ[Ch0] via the channel Ch0. Further, the relay chip IF transfers the commands “05h to E0h” received via the host channel HCh to the chip MC0as the data signal DQ[Ch0] via the channel Ch0.

When the period TP11ends and a period TP12starts, the relay chip IF non-selects the channel Ch0 according to the transition of the chip enable signal CE0−to the non-active level, and selects the channel Ch1 according to the transition of the chip enable signal CE1−to the active level. In this state, the relay chip IF performs the data transfer operation from the chip MC1or the predetermined circuit to the host HA via the relay chip IF. During the period TP12, first, the relay chip IF transfers the prefetched data signal DQ[Ch1] to the host HA as the data signal DQ[HCh] via the host channel HCh. In parallel to the transfer of the prefetched data signal DQ[Ch1], the relay chip IF stores the data signal DQ[Ch1] transferred from the chip MC1via the channel Ch1 in response to the operation “DOUT”, and transfers the stored data signal DQ[Ch1] to the host HA as the data signal DQ[HCh] via the host channel HCh.

At this time, the relay chip IF performs a prefetch operation via the non-selected channel Ch0. That is, the peripheral circuit3of the chip MC0transfers the read data in the register4designated by the column address to the input/output circuit5, and transfers at least some of the read data which have been transferred to the input/output circuit5, to the relay chip IF as the data signal DQ[Ch0] via the terminal group6and the channel Ch0. The relay chip IF stores (prefetches) the transferred data signal DQ[Ch0] in a predetermined circuit.

When the data transfer to the host HA is completed, the relay chip IF transfers the commands “00h to 30h” received via the host channel HCh to the chip MC1as the data signal DQ[Ch1] via the channel Ch1. Further, the relay chip IF transfers the commands “05h to E0h” received via the host channel HCh to the chip MC1as the data signal DQ[Ch1] via the channel Ch1.

In periods TP13to TP15, the same operation as the period TP11and the same operation as the period TP12are alternately performed.

The operation illustrated inFIG.4may be represented for each chip as illustrated inFIG.5.FIG.5is a waveform diagram illustrating the operation of the semiconductor device1for each chip. For the sake of simplicity, the chips MC0-1, MC0-2, MC0-3, and MC0-4connected to the channel Ch0 are also referred to as chips (1), (3), (5), and (7), respectively, and the chips MC1-1, MC1-2, MC1-3, and MC1-4connected to the channel Ch1 are also referred to as chips (2), (4), (6), and (8), respectively.

The chip (1) of the channel Ch0 is addressed by the commands “05h to E0h” of the period TP9. The chip (2) of the channel Ch1 is addressed by the commands “05h to E0h” of the period TP10. The chip (3) of the channel Ch0 is addressed by the commands “05h to E0h” in the second half of the period TP11. The chip (4) of the channel Ch1 is addressed by the commands “05h to E0h” in the second half of the period TP12. The chip (5) of the channel Ch0 is addressed by the commands “05h to E0h” in the second half of the period TP13. The chip (6) of the channel Ch1 is addressed by the commands “05h to E0h” in the second half of the period TP14. The chip (7) of the channel Ch0 is addressed by the commands “05h to E0h” in the second half of the period TP15. The chip (8) of the channel Ch1 is addressed by the commands “05h to E0h” in the second half of the period TP16.

Here, the period tWHR2for performing the prefetch operation is assigned the chip number (N: N=1 to 8) to be expressed as tWHR2(N). That is, a period tWHR2(1) is the period TP10, a period tWHR2(2) is the period TP11, a period tWHR2(3) is the period TP12, a period tWHR2(4) is the period TP13, a period tWHR2(5) is the period TP14, a period tWHR2(6) is the period TP15, a period tWHR2(7) is the period TP16, and a period tWHR2(8) is the period TP17.

As illustrated inFIG.5, the periods tWHR2(1) to tWHR2(8) are exclusively and sequentially started and ended. The periods tWHR2(1) to tWHR2(8) are alternately started and ended for the channel Ch0 and the channel Ch1. In the periods tWHR2(1) to tWHR2(8), the prefetch operation is performed via a non-selected channel Ch, and the command issuance or the like is performed via a selected channel Ch. As a result, the periods tWHR2(1) to tWHR2(8) can be concealed from the data signal DQ[HCh].

Similarly to the period tWHR2, here, the period tTR during which the data transfer process is performed is assigned the chip number (N: N=1 to 8) to be expressed as tTR(N). That is, a period tTR(1) is from the period TP9to the first half of the period TP11, a period tTR(2) is from the period TP10to the first half of the period TP12, a period tTR(3) is from the second half of the period TP11to the first half of the period TP13, a period tTR(4) is from the second half of the period TP12to the first half of the period TP14, a period tTR(5) is from the second half of the period TP13to the first half of the period TP15, a period tTR(6) is from the second half of the period TP14to the first half of the period TP16, a period tTR(7) is from the second half of the period TP15to the first half of the period TP17, and a period tTR(8) is from the second half of the period TP16to the first half of the period TP18.

As illustrated inFIG.5, the periods tTR(1) to tTR(8) start sequentially in a pipeline-manner, progress partially in parallel, and end in sequence. The periods tTR(1) to tTR(8) start and end alternately for the channel Ch0 and the channel Ch1. As a result, the data transfer process of the plurality of chips (1) to (8) may be efficiently performed while concealing the periods tWHR2(1) to tWHR2(8) from the data signal DQ[HCh].

Similarly to the commands “05h to E0h”, the chip (1) of the channel Ch0 is addressed by the commands “00h to 30h” of the period TP1. The chip (2) of the channel Ch1 is addressed by the commands “00h to 30h” of the period TP2. The chip (3) of the channel Ch0 is addressed by the commands “00h to 30h” of the period TP3. The chip (4) of the channel Ch1 is addressed by the commands “00h to 30h” of the period TP4. The chip (5) of the channel Ch0 is addressed by the commands “00h to 30h” of the period TP5. The chip (6) of the channel Ch1 is addressed by the commands “00h to 30h” of the period TP6. The chip (7) of the channel Ch0 is addressed by the commands “00h to 30h” of the period TP7. The chip (8) of the channel Ch1 is addressed by the commands “00h to 30h” of the period TP8.

Here, the period tR for performing the sense operation is expressed as tR(N) by assigning the chip number (N: N=1 to 8). The periods tR(1) to tR(8) start sequentially in a pipeline-manner, progress in parallel with each other, and end in sequence. The periods tR(1) to tR(8) start and end alternately for the channel Ch0 and the channel Ch1. As a result, the sense operation of the plurality of chips (1) to (8) may be performed in parallel between the channel Ch0 and the channel Ch1.

Next, the configuration of the relay chip IF for performing the inter-channel interleaving operation in the read process will be described with reference toFIG.6.FIG.6is a diagram illustrating the configuration of the relay chip IF.

The relay chip IF includes a switching circuit11, a switching circuit12, a first-in-first-out (FIFO) circuit13, a FIFO circuit14, an oscillator15, a control circuit16, a selector17, a selector18, a terminal group21, and the terminal group22.

The terminal group21may be connected to the host HA via the host channel HCh. The host channel HCh includes a data signal line DQ<7:0>, strobe signal lines DQS and DQS−, read enable signal lines RE and RE−, and chip enable signal lines CE0−and CE1−. Correspondingly, the terminal group21includes a terminal group21afor the data signal DQ<7:0>, a terminal group21bfor the strobe signals DQS and DQS−, a terminal group21cfor the read enable signals RE and RE−, a terminal21dfor the chip enable signal CE0−, and a terminal21efor the chip enable signal CE1−.

The terminal group22may be connected to the chip MC0via the channel Ch0, and may be connected to the chip MC1via the channel Ch1. The channel Ch0 includes a data signal line DQ0<7:0>, strobe signal lines DQS0 and DQS0−, read enable signal lines RE0 and RE0−, and a chip enable signal line CE0−. Correspondingly, the terminal group22includes a terminal group22afor the data signal DQ0<7:0>, a terminal group22bfor the strobe signals DQS0 and DQS0−, a terminal group22cfor the read enable signals RE0 and RE0−, and a terminal22dfor the chip enable signal CE0. The channel Ch1 includes a data signal line DQ1<7:0>, strobe signal lines DQS1 and DQS1−, read enable signal lines RE1 and RE1−, and a chip enable signal line CE1−. Correspondingly, the terminal group22includes a terminal group22efor the data signal DQ1<7:0>, a terminal group22ffor the strobe signals DQS1 and DQS1−, a terminal group22gfor the read enable signals RE1 and RE1−, and a terminal22hfor the chip enable signal CE1−.

The FIFO circuit13is disposed between the terminal groups21a,21b, and21cand the terminal groups22aand22b, and electrically connected between the switching circuits11and12and the terminal groups22aand22b. On the FIFO circuit13, a data node13amay be connected to the terminal group21avia the switching circuit11, a clock node13bmay be connected to the terminal group21cvia the switching circuit12, a data node13cis connected to the terminal group22a, and a clock node13dis connected to the terminal group22b.

The FIFO circuit13is a bidirectional circuit and has a plurality of queue entries. The FIFO circuit13performs a bypass connection between the data nodes13aand13cfor the plurality of queue entries in response to the read enable signals RE and RE−received at the clock node13bbeing maintained at the non-active level. That is, when the data signal DQ is received at the data node13awhile the read enable signals RE and RE−are maintained at the non-active level, the FIFO circuit13transfers the data signal DQ from the data node13cto the terminal group22avia the bypass connection. Alternatively, when the data signal DQ is received at the data node13cwhile the read enable signals RE and RE−are maintained at the non-active level, the FIFO circuit13transfers the data signal DQ from the data node13ato the terminal group21avia the bypass connection. In the read process, the FIFO circuit13cancels the bypass connection in response to the toggle of the read enable signals RE and RE−received at the clock node13b. That is, the FIFO circuit13enqueues, in response to the toggle of the data strobe signals DQS0 and DQS0−, the data signal DQ received at the data node13cin the head of the queue entries. The FIFO circuit13shifts, in response to the toggle of the read enable signals RE and RE−, the data signal DQ enqueued in each queue entry by one entry. The FIFO circuit13also dequeues, in response to the toggle of the read enable signals RE and RE−, the data signal DQ from the tail of the queue entries and transfers the dequeued data signal DQ from the data node13ato the terminal group21a.

The FIFO circuit14is disposed between the terminal groups21a,21b, and21cand the terminal groups22eand22f, and electrically connected between the switching circuits11and12and the terminal groups22eand22f. On the FIFO circuit14, a data node14amay be connected to the terminal group21avia the switching circuit11, a clock node14bmay be connected to the terminal group21cvia the switching circuit12, a data node14cis connected to the terminal group22e, and a clock node14dis connected to the terminal group22f.

The FIFO circuit14is a bidirectional circuit and has a plurality of queue entries. The FIFO circuit14performs a bypass connection between the data nodes14aand14cfor the plurality of queue entries in response to the read enable signals RE and RE−received at the clock node14bbeing maintained at the non-active level. That is, when the data signal DQ is received at the data node14awhile the read enable signals RE and RE−are maintained at the non-active level, the FIFO circuit14transfers the data signal DQ from the data node14cto the terminal group22evia the bypass connection. Alternatively, when the data signal DQ is received at the data node14cwhile the read enable signals RE and RE−are maintained at the non-active level, the FIFO circuit14transfers the data signal DQ from the data node14ato the terminal group21avia the bypass connection. In the read process, the FIFO circuit14cancels the bypass connection in response to the toggle of the read enable signals RE and RE−received at the clock node14b. That is, the FIFO circuit14enqueues, in response to the toggle of the data strobe signals DQS1 and DQS1−, the data signal DQ received at the data node14cin the head of the queue entries. The FIFO circuit14shifts, in response to the toggle of the read enable signals RE and RE−, the data signal DQ enqueued in each queue entry by one entry. The FIFO circuit14also dequeues, in response to the toggle of the read enable signals RE and RE−, the data signal DQ from the tail of the queue entries and transfers the dequeued data signal DQ from the data node14ato the terminal group21a.

The switching circuit11switches between a first connection state and a second connection state according to the chip enable signal CE0−and the chip enable signal CE1. The first connection state is a state in which the terminal group21aand the data node13aof the FIFO circuit13are connected. The second connection state is a state in which the terminal group21aand the data node14aof the FIFO circuit14are connected. The switching circuit11switches to the first connection state in response to the chip enable signal CE0−being at the active level and the chip enable signal CE1−being at the non-active level, and switches to the second connection state in response to the chip enable signal CE0−being at the non-active level and the chip enable signal CE1−being at the active level.

The switching circuit12switches between a third connection state and a fourth connection state according to the chip enable signal CE0−and the chip enable signal CE1−. The third connection state is a state in which the terminal group21cand the clock node13bof the FIFO circuit13are connected. The fourth connection state is a state in which the terminal group21cand the clock node14bof the FIFO circuit14are connected. The switching circuit12switches to the third connection state in response to the chip enable signal CE0−being at the active level and the chip enable signal CE1−being at the non-active level, and switches to the fourth connection state in response to the chip enable signal CE0−being at the non-active level and the chip enable signal CE1−being at the active level.

On the oscillator15, an output node15ais electrically connected to the control circuit16. On the control circuit16, an input node16ais connected to the oscillator15, an output node group16bis connected to the terminal group22c, an output node16cis connected to the selector17, an output node group16dis connected to the terminal group22g, and an output node16eis connected to the selector18. On the selector17, an input node17ais connected to the terminal21d, an input node17bis connected to the control circuit16, and an output node17cis connected to the terminal22d. On the selector18, an input node18ais connected to the terminal21e, an input node18bis connected to the control circuit16, and an output node18cis connected to the terminal22h.

In response to the chip enable signal CE0−being at the active level and the chip enable signal CE1−being at the non-active level, the control circuit16generates the read enable signals RE0 and RE0−to be toggled and supplies the generated signals to the chip MC0, and generates the read enable signals RE1 and RE1−to be toggled and the chip enable signal CE1−of the active level, and supplies the generated signals to the chip MC1. In response to the chip enable signal CE0−being at the non-active level and the chip enable signal CE1−being at the active level, the control circuit16generates the read enable signals RE0 and RE0−to be toggled and the chip enable signal CE0−of the active level, and supplies the generated signals to the chip MC0, and generates the read enable signals RE1 and RE1−to be toggled and supplies the generated signals to the chip MC1.

As a result, the relay chip IF may supply an active level chip enable signal to the chip MC connected to a non-selected channel Ch. Further, the relay chip IF may supply the read enable signals RE0, RE0−, RE1, and RE1−generated by the control circuit16, instead of the read enable signals RE and RE−received from the host HA, to the chips MC0and MC1. That is, the relay chip IF may replace the read enable signals, which are to be supplied to the chip MC via the channel Ch, from the read enable signal RE and RE−of the host HA to the read enable signal RE0, RE0−, RE1, and RE1−of the control circuit16.

The relay chip IF may operate as illustrated inFIGS.7A to7D.FIGS.7A to7Dare diagrams illustrating examples of the operation of the relay chip IF.FIGS.7A to7Dillustrate examples of the operation of the relay chip IF during the periods TP11to TP12illustrated inFIG.4.

At the period TP11, as illustrated inFIG.7A, according to the transition of the chip enable signal CE0−to the active level and the transition of the chip enable signal CE1−to the non-active level, the switching circuit11switches to the first connection state and the switching circuit12switches to the third connection state.

The read enable signals RE and RE−are toggled. The relay chip IF returns the read enable signals RE and RE−as the data strobe signals DQS/DQS−to the host HA. The selector17selects the input node17a, and transfers the chip enable signal CE0−received at the terminal21dto the chip MC0via the channel Ch0. The FIFO circuit13transmits some of the prefetched read data to the host HA in response to the toggled read enable signals RE and RE−. Further, the control circuit16uses an oscillation signal from the oscillator15to generate the toggled read enable signals RE0 and RE0−, and supplies the signals to the chip MC0via the channel Ch0. The chip MC0transfers the remaining portion of the read data and the data strobe signals DQS0 and DQS0−to the FIFO circuit13via the channel Ch0. The FIFO circuit13stores the transferred read data according to the data strobe signals DQS0 and DQS0−and transmits the stored read data to the host HA according to the toggled read enable signals RE and RE−.

In parallel, the control circuit16uses the oscillation signal to generate the toggled read enable signals RE1 and RE1−and also generate the active level chip enable signal CE1. The control circuit16transfers the read enable signals RE1 and RE1−to the chip MC1via the channel Ch1. The selector18selects the input node18b, and transfers the chip enable signal CE1−generated by the control circuit16to the chip MC1via the channel Ch1. In response, the chip MC1transfers at least some of the read data and the data strobe signals DQS1 and DQS1−to the FIFO circuit14via the channel Ch1. The FIFO circuit14stores (prefetches) the transferred read data in response to the data strobe signals DQS1 and DQS1−.

In the second half of the period TP11, as illustrated inFIG.7B, the read enable signals RE and RE−end to be toggled and are maintained at the non-active level. The selector17selects the input node17a, and transfers the chip enable signal CE0−received at the terminal21dto the chip MC0via the channel Ch0. In response to the read enable signals RE and RE−being maintained at the non-active level, using the bypass connection, the FIFO circuit13sequentially transfers the commands “00h to 30h” and the commands “05h to E0h”, which are received at the terminal group21a, to the chip MC0via the channel Ch0 as the data signal DQ0.

At this time, the FIFO circuit14completes the prefetch of the read data transferred via the channel Ch1.

At the period TP12, as illustrated inFIG.7C, according to the transition of the chip enable signal CE0−to the non-active level and the transition of the chip enable signal CE1−to the active level, the switching circuit11switches to the second connection state and the switching circuit12switches to the fourth connection state.

The read enable signals RE and RE−are toggled. The relay chip IF returns the read enable signals RE and RE−as the data strobe signals DQS/DQS−to the host HA. The selector18selects the input node18a, and transfers the chip enable signal CE1−received at the terminal21eto the chip MC1via the channel Ch1. The FIFO circuit14transmits some of the prefetched read data to the host HA in response to the toggled read enable signals RE and RE−. Further, the control circuit16uses the oscillation signal from the oscillator15to generate the toggled read enable signals RE1 and RE1−, and supplies the signals to the chip MC1via the channel Ch1. The chip MC1transfers the remaining portion of the read data and the data strobe signals DQS1 and DQS1−to the FIFO circuit14via the channel Ch1. The FIFO circuit14stores the transferred read data according to the data strobe signals DQS1 and DQS1−and transmits the stored read data to the host HA according to the toggled read enable signals RE and RE−.

In parallel, the control circuit16uses the oscillation signal to generate the toggled read enable signals RE0 and RE0−and also generate the active level chip enable signal CE0−. The control circuit16transfers the read enable signals RE0 and RE0−to the chip MC0via the channel Ch0. The selector17selects the input node17b, and transfers the chip enable signal CE0−generated by the control circuit16to the chip MC0via the channel Ch0. In response, the chip MC0transfers at least some of the read data and the data strobe signals DQS0 and DQS0−to the FIFO circuit13via the channel Ch0. The FIFO circuit13stores (prefetches) the transferred read data in response to the data strobe signals DQS0 and DQS0−.

In the second half of the period TP12, as illustrated inFIG.7D, the read enable signals RE and RE−end to be toggled and are maintained at the non-active level. The selector18selects the input node18a, and transfers the chip enable signal CE1−received at the terminal21eto the chip MC1via the channel Ch1. In response to the read enable signals RE and RE−being maintained at the non-active level, using the bypass connection, the FIFO circuit14sequentially transfers the commands “00h to 30h” and the commands “05h to E0h”, which are received at the terminal group21a, to the chip MC1via the channel Ch1 as the data signal DQ1.

As described above, in the first embodiment, in the semiconductor device1, the relay chip IF enables an access operation (that is, the inter-channel interleaving operation) for the plurality of chips MC0and MC1in parallel via the plurality of channels Ch0 and Ch1. Thereby, for example, in the read process, the data transfer between the host HA and the plurality of chips MC0and MC1via the relay chip IF can be implemented while concealing the period tWHR2for the prefetch operation. As a result, the data transfer performance between the host HA and the plurality of chips MC0and MC1via the relay chip IF can be improved.

Note that, the relay chip IF for performing the inter-channel interleaving operation in the read process may be configured to pass the read enable signals RE and RE−of the host HA, as illustrated inFIG.8.FIG.8is a diagram illustrating the configuration of the relay chip IF in a modification of the first embodiment. The relay chip IF illustrated inFIG.8is different from the relay chip IF illustrated inFIG.6in that a selector19and a selector20are added, a line extending from the switching circuit12to the FIFO circuit13branches and extends to the selector19, and a line extending from the switching circuit12to the FIFO circuit14branches and extends to the selector20. On the selector19, an input node19ais connected to the switching circuit12, an input node19bis connected to the control circuit16, and an output node19cis connected to the terminal22c. On the selector20, an input node20ais connected to the switching circuit12, an input node20bis connected to the control circuit16, and an output node20cis connected to the terminal22g.

When the switching circuit12switches to the third connection state, the selector19selects the input node19a, the relay chip IF passes the read enable signals RE and RE−from the host HA to the chip MC0as the read enable signals RE0 and RE0 via the channel Ch0. When the switching circuit12switches to the fourth connection state, the selector20selects the input node20a, the relay chip IF passes the read enable signals RE and RE−from the host HA to the chip MC1as the read enable signals RE1 and RE1−via the channel Ch1.

Further, as illustrated inFIGS.9A to9D, the operation of the relay chip IF illustrated inFIG.8is different from that of the relay chip IF illustrated inFIG.6in the following points.FIGS.9A to9Drepresent an example of the operation of the relay chip IF during the periods TP11to TP12illustrated inFIG.4. The description about the same portions as those inFIGS.7A to7Dwill be omitted.

At the period TP11, as illustrated inFIG.9A, when the read enable signals RE and RE−are toggled, the relay chip IF returns the toggled read enable signals RE and RE−to the host HA as the data strobe signals DQS/DQS−and transfers the toggled read enable signals RE and RE−to the FIFO circuit13via the switching circuit12. This is the same as the relay chip IF illustrated inFIG.6. The relay chip IF supplies the toggled read enable signals RE and RE−to the selector19via the switching circuit12. The selector19selects the input node19a, and transfers the toggled read enable signals RE and RE−to the chip MC0as the read enable signals RE0 and RE0−via the channel Ch0.

At this time, the selector20selects the input node20b, receives the toggled read enable signals RE1 and RE1−from the control circuit16, and transfers the signals to the chip MC1via the channel Ch1. In response, the chip MC1transfers at least some of the read data to the FIFO circuit14via the channel Ch1, and the FIFO circuit14stores (prefetches) the read data transferred via the channel Ch1. This is the same as the relay chip IF illustrated inFIG.6.

Thereafter, as illustrated inFIG.9B, the read enable signals RE and RE−end to be toggled and are maintained at the non-active level. At this time, the selector20selects the input node20b, receives the toggled read enable signals RE1 and RE1 from the control circuit16, and transfers them to the chip MC1via the channel Ch1.

At the period TP12, as illustrated inFIG.9C, when the read enable signals RE and RE−are toggled, the relay chip IF returns the toggled read enable signals RE and RE−to the host HA as the data strobe signals DQS/DQS−, and transfers the toggled read enable signals RE and RE−to the FIFO circuit14via the switching circuit12. This is the same as the relay chip IF illustrated inFIG.6. The relay chip IF supplies the toggled read enable signals RE and RE−to the selector20via the switching circuit12. The selector20selects the input node20a, and transfers the toggled read enable signals RE and RE−to the chip MC1as the read enable signals RE1 and RE1−via the channel Ch1.

At this time, the selector19selects the input node19b, receives the toggled read enable signals RE0 and RE0−from the control circuit16, and transfers the signals to the chip MC0via the channel Ch0. In response, the chip MC0transfers at least some of the read data to the FIFO circuit13via the channel Ch0, and the FIFO circuit13stores (prefetches) the read data transferred via the channel Ch0. This is the same as the relay chip IF illustrated inFIG.6.

Thereafter, as illustrated inFIG.9D, the read enable signals RE and RE−end to be toggled and are maintained at the non-active level. At this time, the selector19selects the input node19b, receives the toggled read enable signals RE0 and RE0 from the control circuit16, and transfers the signals to the chip MC0via the channel Ch0.

In this way, the inter-channel interleaving operation in the read process can be performed by the relay chip IF illustrated inFIG.8.

Second Embodiment

Next, a semiconductor device1according to a second embodiment will be described. Hereinafter, portions different from the first embodiment will be mainly described.

In the first embodiment, the operation of concealing the period tWHR2of the read process by the function of the inter-channel interleaving operation is illustrated. In the second embodiment, an operation of increasing the speed of the data transfer of the read process by the function of the inter-channel interleaving operation is illustrated.

For example, when the maximum speed of the host channel HCh is twice the maximum speed of each of the channels Ch0 and Ch1, the semiconductor device1may double the speed of the data transfer in the semiconductor device1by an operation illustrated inFIG.10.FIG.10is a waveform diagram illustrating the operation of the semiconductor device1according to the second embodiment.FIG.10illustrates the operations of periods corresponding to the periods TP9to TP14illustrated inFIGS.4and5.

InFIG.10, the end timing of the operation “DOUT” designed to be almost the same for each channel Ch and the host channel HCh. Considering that the maximum speed of the host channel HCh is twice the maximum speed of the channel Ch, the amount of data prefetched by the relay chip IF in a period is half the amount of data transferred to the host HA in the same period.FIG.10illustrates a case where the amount of data transferred to the host HA is 16 kB, and the amount of data prefetched by the relay chip IF is 8 kB.

InFIG.10, the illustration of the commands “00h to 30h” is omitted for the sake of simplicity. The operations of periods TP28to TP34illustrated inFIG.10correspond to the operations of the periods TP8to TP14illustrated inFIG.5. However, the operation of the period TP31is different from the operation of the period TP11in that the timing at which the chip enable signal CE0−transitions from the non-active level to the active level is timing t21delayed from the start of the period TP31.

When the period TP28ends and the period TP29starts, the relay chip IF selects the channel Ch0 according to the transition of the chip enable signal CE0−to the active level, and non-selects the channel Ch1 according to the transition of the chip enable signal CE1−to the non-active level. In this state, the relay chip IF transfers the commands “05h to E0h” received via the host channel HCh to the chip (1) as the data signal DQ[Ch0] via the channel Ch0.

At timing t20, the period TP29ends, and the period TP30starts. The relay chip IF non-selects the channel Ch0 according to the transition of the chip enable signal CE0−to the non-active level, and selects the channel Ch1 according to the transition of the chip enable signal CE1−to the active level. In this state, the relay chip IF transfers the commands “05h to E0h” received via the host channel HCh to the chip (2) as the data signal DQ[Ch1] via the channel Ch1.

At this time, the relay chip IF starts the prefetch operation for the chip (1) via the non-selected channel Ch0. That is, the chip (1) transfers at least some of the read data to the relay chip IF as the data signal DQ[Ch0] via the channel Ch0. The relay chip IF starts storing (prefetching) the transferred data signal DQ[Ch0] in the FIFO circuit13.

When the period TP30ends and the period TP31starts, the chip enable signal CE0−is maintained at the non-active level because the prefetch operation is continuing for the chip (1). In response, the relay chip IF keeps the channel Ch0 non-selected. At the same time, the relay chip IF non-selects the channel Ch1 according to the transition of the chip enable signal CE1−to the non-active level.

At this time, the relay chip IF starts the prefetch operation for the chip (2) via the non-selected channel Ch1. That is, the chip (2) transfers at least some of the read data to the relay chip IF as the data signal DQ[Ch1] via the channel Ch1. The relay chip IF starts storing (prefetching) the transferred data signal DQ[Ch1] in the FIFO circuit14.

At the timing t21, the prefetch operation for the chip (1) is completed. The relay chip IF keeps channel Ch1 non-selected because the chip enable signal CE1−is maintained at the non-active level, and selects the channel Ch0 according to the transition of the chip enable signal CE0−to the active level. The relay chip IF transfers the prefetched data signal DQ[Ch0] to the host HA as the data signal DQ[HCh] via the host channel HCh. At the same time, in response to the operation “DOUT”, the relay chip IF continues storing in the FIFO circuit13the data signal DQ[Ch0] transferred from the chip (1) via the channel Ch0 and internally shifts the stored data signal DQ[Ch0] between the plurality of queue entries. Also at this time, the relay chip IF continues the prefetch operation for the chip (2).

At timing t22, the transfer of the prefetched data signal DQ[Ch0] to the host HA is completed. The relay chip IF starts transferring the stored data signal DQ[Ch0], which has started to be stored from timing t21, to the host HA as the data signal DQ[HCh] via the host channel HCh. At this time, the relay chip IF completes the prefetch operation for the chip (2).

At timing t23, the transfer of the data signal DQ[Ch0] from the chip (1) to the relay chip IF via the channel Ch0 is completed. The relay chip IF internally shifts the data signal DQ[Ch0], which have been transferred from the chip (1) via the channel Ch0 and stored in the FIFO circuit13, between the plurality of queue entries, and then, completes the transfer of the stored data signal DQ[Ch0] to the host HA. Since the period of the internal shift operation of the data signal DQ[Ch0] in the FIFO circuit13is so short to be ignored, the timing of the completion of transfer of the data signal DQ[Ch0] of the chip (1) to the relay chip IF and the timing of the completion of transfer of the stored data signal DQ[Ch0] to the host HA may be considered to be substantially at the same time.

As described above, for the data signal DQ[Ch0] of the chip (1), the relay chip IF prefetches half of the amount of data to be transferred, during a non-selection period of the channel Ch0 (e.g., the period of the timings t20to t21), and uses a selection period of the channel Ch0 (e.g., the period from the timing t21to t23) for the data transfer to the host HA. As a result, the amount of data transferred from the relay chip IF to the host HA during the period from the timing t21to t23can be 16 kB which is double of the amount of data (8 kB) transferred from the chip (1) to the relay chip IF via the channel Ch0 in the same period. That is, in the read process, the data transfer via the channel Ch0 in the semiconductor device1may be substantially doubled beyond the maximum speed of the channel Ch0.

For the data signal DQ[Ch1] of the chip (2), the relay chip IF prefetches half of the amount of data to be transferred, during a non-selection period of the channel Ch1 (e.g., the first half of the period TP31), and uses a selection period of the channel Ch1 (e.g., the period from timing t24to t25) for the data transfer to the host HA. As a result, the amount of data transferred from the relay chip IF to the host HA during the period from the timing t24to t25can be 16 kB which is double of the amount of data (8 kB) transferred from the chip (2) to the relay chip IF via the channel Ch1. That is, in the read process, the data transfer via the channel Ch1 in the semiconductor device1may be substantially doubled beyond the maximum speed of the channel Ch1.

The data transfer for the subsequent chips (i.e., chips (3) to (7)) is the same as that for the chip (1) or (2).

As described above, in the semiconductor device1of the second embodiment, the data transfer via the channel Ch in the semiconductor device1in the read process can be speeded up beyond the maximum speed of the channel Ch by the function of the inter-channel interleaving operation.

Third Embodiment

Next, a semiconductor device1according to a third embodiment will be described. Hereinafter, portions different from the first and second embodiments will be mainly described.

An example of the read process by the function of the inter-channel interleaving operation is described in the first and second embodiments describe. In the third embodiment, an example of a write process by the function of the inter-channel interleaving operation will be described.

For example, the write process for the memory cell array2of each chip MC is performed in a sequence illustrated inFIGS.11A and11B.FIGS.11A and11Bare diagrams illustrating a sequence of the write process, and represent a waveform of each signal exchanged between the host HA and the semiconductor device1in the write process.

In the sequence of the write process, each signal transitions as illustrated inFIG.11A. At timing t31, when the chip enable signal CE is asserted, and the command latch enable signal CLE is asserted, a program start command “80h” is transferred as the data signal DQ from the host HA to the semiconductor device1.

At timing t32, when the command latch enable signal CLE is de-asserted, and the address latch enable signal ALE is asserted, addresses “ADD” such as a column address and a row address are transferred as the data signal DQ from the host HA to the semiconductor device1.

At timing t33, the address latch enable signal ALE is de-asserted, and at timing t34, the data strobe signals DQS/DQS from the host HA to the semiconductor device1start to be toggled.

Accordingly, in a period from t35to t36, write data are transferred as the data signal DQ from the host HA to the semiconductor device1. That is, the peripheral circuit3of the chip MC transfers the write data received at the input/output circuit5to the register4and stores the data in the register4.

At timing t37, when the command latch enable signal CLE is asserted, a program execution command “10h” is transferred as the data signal DQ from the host HA to the semiconductor device1.

Accordingly, the semiconductor device1performs a program operation in a period tPROG of timings t38to t39. That is, the peripheral circuit3of the chip MC transfers the write data from the register4to the memory cell array2, and performs the program operation. The peripheral circuit3of the chip MC writes the write data in a designated page of a memory cell group designated by the row address.

In the following, the command sequence of the write process illustrated inFIG.11Awill be simplified as illustrated inFIG.11B. That is, the commands of the timings t31to t33are represented by “80h-”, the operations of the timings t35to t36are represented by “DIN”, and the commands of the timings t37to t38are represented by “10h”. The program operation according to “10h” is performed in the period tPROG of the timings t38to t39. Further, a period that includes the period of “80h-” and the period of “DIN” is defined as tTR′. During the period of “80h-”, a command for data transfer is issued. During the period of “DIN”, the data transfer operation from the host HA to the chip MC via the relay chip IF and the channel Ch is performed. Hereinafter, a process including the command issuing operation for the data transfer and the data transfer operation is called a data transfer process. The period tTR′ is a period during which the data transfer process is performed.

As illustrated inFIG.12, the semiconductor device1is able to perform the inter-channel interleaving operation for the write process.FIG.12is a diagram illustrating the operation of the semiconductor device1.FIG.12exemplifies the inter-channel interleaving operation performed while alternately selecting the channels Ch0 and Ch1 for the write process. InFIG.12, the program operation is omitted for the sake of simplicity.

The host HA generates different chip enable signals CE0−and CE1−for the channels Ch0 and Ch1 and transmits the chip enable signals to the semiconductor device1via the host channel HCh. The chip enable signal CE0−is transmitted a signal for selecting the channel Ch0 from the host HA as. The chip enable signal CE1−is transmitted as a signal for selecting the channel Ch1 from the host HA. When the chip enable signals CE0 and CE1−are received from the host HA via the host channel HCh, the semiconductor device1performs an operation according to the levels of the chip enable signals CE0−and CE1−.

InFIG.12, the start timing of the operation “DIN” is almost the same for the host channel HCh and the channel Ch0. Considering that the maximum speed of the host channel HCh is twice the maximum speed of the channel Ch, the amount of data that the relay chip IF stores therein in a period is to be half or more of the amount of data transferred from the host HA in the same period.FIG.12illustrates a case where the amount of data transferred from the host HA is 16 kB, and the amount of data that can be stored in the relay chip IF is 8 kB or more.

FIG.12illustrates the operation of the semiconductor device1for each chip. For the sake of simplicity, the chips MC0-1, MC0-2, MC0-3, and MC0-4connected to the channel Ch0 are also referred to as chips (1), (3), (5), and (7), respectively, and the chips MC1-1, MC1-2, MC1-3, and MC1-4connected to the channel Ch1 are also referred to as chips (2), (4), (6), and (8), respectively.

The chip (1) of the channel Ch0 is addressed by the commands “80h−” of a period TP41. The chip (2) of the channel Ch1 is addressed by the commands “80h−” of a period TP42. The chip (3) of the channel Ch0 is addressed by the commands “80h−” of a period TP43. The chip (4) of the channel Ch1 is addressed by the commands “80h−” of a period TP44. The chip (5) of the channel Ch0 is addressed by the commands “80h−” of a period TP45.

Here, the period tTR′ during which the data transfer process is performed is assigned the chip number (N: N=1 to 8) to be expressed as tTR′(N). As partially illustrated inFIG.12, the periods tTR′(1) to tTR′(8) sequentially start in a pipeline-manner, progress partially in parallel, and end in sequence. The periods tTR′(1) to tTR′(8) start and end alternately for the channel Ch0 and the channel Ch1. As a result, the data transfer operation of the plurality of chips (1) to (8) may be efficiently performed.

For example, when the period TP41starts, the relay chip IF selects the channel Ch0 as the chip enable signal CE0−transitions to the active level, and keeps the channel Ch1 non-selected as the chip enable signal CE1−is maintained at the non-active level. In this state, the relay chip IF transfers the commands “80h−” received via the host channel HCh to the chip (1) as the data signal DQ[Ch0] via the channel Ch0.

At timing t41, the data strobe signals DQS/DQS−start to be toggled, and the write data for the chip (1) starts to be transferred from the host HA to the relay chip IF via the host channel HCh. In response to the operation “DIN”, the relay chip IF starts transferring the write data, which have been received from the host HA via the host channel HCh, to the chip (1) as the data signal DQ[Ch0] via the channel Ch0. That is, the relay chip IF starts the data transfer operation of the write data via the channel Ch0.

At timing t42, the period TP41ends and the period TP42starts, in response to the completion of the transfer of the write data from the host HA to the relay chip IF via the host channel HCh. The relay chip IF non-selects the channel Ch0 according to the transition of the chip enable signal CE0−to the non-active level, and selects the channel Ch1 according to the transition of the chip enable signal CE1−to the active level. In this state, the relay chip IF transfers the commands “80h−” received via the host channel HCh to the chip (2) as the data signal DQ[Ch1] via the channel Ch1.

At this time, the relay chip IF stores therein the write data of the remaining half of the data amount to be transferred for the chip (1), and continues the data transfer operation of the write data via the non-selected channel Ch0.

At timing t43, the data strobe signals DQS/DQS−start to be toggled, and the write data for the chip (2) starts to be transferred from the host HA to the relay chip IF via the host channel HCh. In response to the operation “DIN”, the relay chip IF starts transferring the write data, which have been received from the host HA via the host channel HCh, to the chip (2) as the data signal DQ[Ch1] via the channel Ch1. That is, the relay chip IF starts the data transfer operation of the write data of the chip (2) via the channel Ch1.

At this time, the relay chip IF continues the data transfer operation of the write data of the chip (1) via the non-selected channel Ch0.

At timing t44, the data transfer operation of the write data of the chip (1) via the non-selected channel Ch0 is completed.

For the chip (1), the relay chip IF receives the total amount of data from the host HA during a selection period of the channel Ch0 (e.g., a period of timings t41to t42), transfers the half amount of data to the chip (1) within that period, and transfers the remaining half amount of data to the chip (1) during a non-selection period of the channel Ch0 (e.g., a period of timings t42to t44). As a result, the amount of data transferred from the host HA during the period of timings t41to t42can be 16 kB which is double of the amount of data (8 kB) transferred via the channel Ch0. That is, in the write process, the data transfer via the channel Ch0 in the semiconductor device1may be substantially doubled beyond the maximum speed of the channel Ch0.

For the chip (2), the relay chip IF receives the total amount of data from the host HA during a selection period of the channel Ch1 (e.g., a period from timings t43to t45), transfers the half amount of data to the chip (2) within that period, and transfers the remaining half amount of data to the chip (2) during a non-selection period of the channel Ch1 (e.g., a period from timings t45to t47). As a result, the amount of data transferred from the host HA during the period of timings t43to t45can be 16 kB which is double of the amount of data (8 kB) transferred via the channel Ch1. That is, in the write process, the data transfer via the channel Ch1 in the semiconductor device1may be substantially doubled beyond the maximum speed of the channel Ch1.

The data transfer for the subsequent chips (i.e., chips (3) to (7)) is the same as that for the chip (1) or (2).

Similarly to the period tTR′, here, the period tPROG for performing the program operation is assigned the chip number (N: N=1 to 8) to be expressed as tPROG(N). As partially illustrated inFIG.12, periods tPROG(1) to tPROG (6), tPROG(7), tPROG(8) overlap the periods tTR′ (3) to tTR′(8), tTR′(1), and tTR′(2), respectively. That is, the program operations of the plurality of chips (1) to (8) may be performed in parallel with the data transfer operation from the relay chip IF to the plurality of chips (1) to (8).

Next, the configuration of the relay chip IF for performing the inter-channel interleaving operation in the write process will be described with reference toFIG.13. FIG. is a diagram illustrating the configuration of the relay chip IF.

The relay chip IF illustrated inFIG.13has a control circuit116, instead of the control circuit16(seeFIG.6). InFIG.13, the illustration of the terminal group21cof the terminal group21that is not used in the write process is omitted, and the illustration of the terminal groups22cand22gof the terminal group22that are not used in the write process is omitted. On the control circuit116, an output node group116bis connected to the terminal group22b, and an output node group116dis connected to the terminal group22f.

In response to the chip enable signal CE0−being at the active level and the chip enable signal CE1−being at the non-active level, the control circuit116generates the data strobe signals DQS1 and DQS1−to be toggled and the chip enable signal CE1−of the active level, and supplies the generated signals to the chip MC1. In response to the chip enable signal CE0−being at the non-active level and the chip enable signal CE1−being at the active level, the control circuit116generates the data strobe signals DQS0 and DQS0−to be toggled and the chip enable signal CE0−of the active level, and supplies the generated signals to the chip MC0.

The relay chip IF may operate as illustrated inFIGS.14A to14D.FIGS.14A to14Dare diagrams illustrating examples of the operation of the relay chip IF.FIGS.14A to14Dillustrate examples of the operation of the relay chip IF during the periods TP42to TP43illustrated inFIG.12.

When the period TP41ends and the period TP42starts, the chip enable signal CE0−transitions to the non-active level and the chip enable signal CE1−transitions to the active level, and accordingly, as illustrated inFIG.14A, the switching circuit11switches to the second connection state and the switching circuit12switches to the fourth connection state. Note that the fourth connection state in the third embodiment is a state in which the terminal group21band the clock node14bof the FIFO circuit14are connected.

The data strobe signals DQS and DQS−are maintained at the non-active level. The selector18selects the input node18a, and transfers the chip enable signal CE1−received at the terminal21eto the chip MC1via the channel Ch1. In response, the FIFO circuit14transfers the commands “80h−” to the chip MC1as the data signal DQ via the channel Ch1.

At this time, the control circuit116uses an oscillation signal from the oscillator15to generate the toggled data strobe signals DQS0 and DQS0, and the chip enable signal CE0−of the active level. The control circuit116supplies the data strobe signals DQS0 and DQS0−to the FIFO circuit13and to the chip MC0via the channel Ch0. The selector17selects the input node17b, and transfers the chip enable signal CE0−generated by the control circuit116to the chip MC0via the channel Ch0. In response, the FIFO circuit13continues to transfer the write data to the chip MC0via the channel Ch0 while storing the write data received from the host HA at the terminal group21a.

As illustrated inFIG.14B, when the data strobe signals DQS/DQS−start to be toggled, the FIFO circuit14transfers the data signal DQ from the host HA to the chip MC1via the channel Ch1 while storing therein the data signal DQ as the write data, in response to the toggled data strobe signal DQS/DQS−. At this time, the FIFO circuit13continues to transfer the write data stored therein to the chip MC0via the channel Ch0.

Thereafter, the FIFO circuit13completes the transfer of the write data to the chip MC0via the channel Ch0. At this time, the control circuit116uses the oscillation signal from the oscillator15to generate the toggled data strobe signals DQS1 and DQS1−, and supplies the signals to the FIFO circuit14. The FIFO circuit14continues to transfer the write data to the chip MC1via the channel Ch1 while storing the write data received from the host HA at the terminal group21a.

When the period TP42ends and the period TP43starts, as illustrated inFIG.14C, the chip enable signal CE0−transitions to the active level and the chip enable signal CE1−transitions to the non-active level, and accordingly, the switching circuit switches to the first connection state and the switching circuit12switches to the third connection state. Note that the third connection state in the third embodiment is a state in which the terminal group21band the clock node13bof the FIFO circuit13are connected.

The data strobe signals DQS and DQS−are maintained at the non-active level. The selector17selects the input node17a, and transfers the chip enable signal CE0−received at the terminal21dto the chip MC0via the channel Ch0. In response, the FIFO circuit13sequentially transfers the commands “10h−” and “80h−” to the chip MC0as the data signal DQ via the channel Ch0.

At this time, the control circuit116uses the oscillation signal from the oscillator15to generate the toggled data strobe signals DQS1 and DQS1−, and the chip enable signal CE1−of the active level. The control circuit116supplies the data strobe signals DQS1 and DQS1−to the FIFO circuit14and to the chip MC1via the channel Ch1. The selector18selects the input node18b, and transfers the chip enable signal CE1−generated by the control circuit116to the chip MC1via the channel Ch1. In response, the FIFO circuit14continues to transfer the write data to the chip MC1via the channel Ch1 while storing the write data received from the host HA at the terminal group21a.

As illustrated inFIG.14D, when the data strobe signals DQS/DQS−start to be toggled, the FIFO circuit13transfers the data signal DQ from the host HA to the chip MC0via the channel Ch0 while storing therein the data signal DQ as the write data, in response to the toggled data strobe signal DQS/DQS−. At this time, the FIFO circuit14continues to transfer the write data stored therein to the chip MC1via the channel Ch1.

Thereafter, the FIFO circuit14completes the transfer of the write data to the chip MC1via the channel Ch1. At this time, the control circuit116uses the oscillation signal from the oscillator15to generate the toggled data strobe signals DQS0 and DQS0, and supplies the signals to the FIFO circuit13. The FIFO circuit13continues to transfer the write data to the chip MC0via the channel Ch0 while storing the write data received from the host HA at the terminal group21a.

As described above, in the semiconductor device1of the third embodiment, the data transfer via the channel Ch in the semiconductor device1in the write process can be speeded up beyond the maximum speed of the channel Ch by the function of the inter-channel interleaving operation.

Fourth Embodiment

Next, a semiconductor device1according to a fourth embodiment will be described. Hereinafter, portions different from the first to third embodiments will be mainly described.

In the first embodiment, the inter-channel interleaving operation in the case of alternately selecting the plurality of channels Ch0 and Ch1 is illustrated, but in the fourth embodiment, an inter-channel interleaving operation in a case of simultaneously selecting the plurality of channels Ch0 and Ch1 is illustrated. Hereinafter, the inter-channel interleaving operation in the case of simultaneously selecting the plurality of channels Ch0 and Ch1 will be referred to as a simultaneous-access inter-channel interleaving operation.

The simultaneous-access inter-channel interleaving operation is performed as illustrated inFIGS.15A to15D.FIGS.15A to15Dare diagrams illustrating the operation of the semiconductor device1.FIGS.15A to15Dschematically illustrate the simultaneous-access inter-channel interleaving operation.

The relay chip IF receives the chip enable signal CE0−for selecting the channel Ch0 and the chip enable signal CE1 for selecting the channel Ch1 from the host HA. The relay chip IF may perform the data transfer operation via the channel Ch0 and the data transfer operation via the channel Ch1 in parallel when the chip enable signal CE0−is maintained at the active level and the chip enable signal CE1−is maintained at the active level.

When a command “CMD+ADD(0)” is received via the host channel HCh in a period TP51during which the chip enable signal CE0−is maintained at the active level and the chip enable signal CE1−is maintained at the non-active level, the relay chip IF issues the command “CMD+ADD(0)” to the chip MC0via the selected channel Ch0. When a command “CMD+ADD(1)” is received via the host channel HCh in a period TP52during which the chip enable signal CE0−is maintained at the non-active level and the chip enable signal CE1−is maintained at the active level, the relay chip IF issues the command “CMD+ADD(1)” to the chip MC1via the selected channel Ch1. The period TP52is a period after the period TP51. In a period TP53during which the chip enable signal CE0−is maintained at the active level and the chip enable signal CE1−is maintained at the active level, the relay chip IF performs the data transfer operation “DIN/DOUT×1” according to the command “CMD+ADD(0)” via the selected channel Ch0, and performs the data transfer operation “DIN/DOUT×1” according to the command “CMD+ADD(1)” via the selected channel Ch1. The period TP53is a period after the period TP52. “DIN” represents a data transfer operation performed in the write process, and “DOUT” represents a data transfer operation performed in the read process.

For example, as illustrated inFIG.16, the semiconductor device1may perform the simultaneous-access inter-channel interleaving operation for the read process.FIG.16is a diagram illustrating the operation of the semiconductor device1, and represents the inter-channel interleaving operation performed by simultaneously selecting the channels Ch0 and Ch1 for the read process.FIG.16illustrates the operations of periods corresponding to the periods TP9to TP14illustrated inFIGS.4and5.

Here, it is assumed as an example that the maximum speed of the host channel HCh is twice the maximum speed of each of the channels Ch0 and Ch1.

When the period TP61starts, the relay chip IF selects the channel Ch0 as the chip enable signal CE0−transitions to the active level, and keeps the channel Ch1 non-selected as the chip enable signal CE1−is maintained at the non-active level. In this state, the relay chip IF transfers the commands “05h to E0h” received via the host channel HCh to the chip (1) as the data signal DQ[Ch0] via the channel Ch0.

When the period TP61ends and a period TP62starts, the relay chip IF non-selects the channel Ch0 as the chip enable signal CE0−transitions to the non-active level, and selects the channel chip Ch1 as the chip enable signal CE1−transitions to the active level. In this state, the relay chip IF transfers the commands “05h to E0h” received via the host channel HCh to the chip (2) as the data signal DQ[Ch1] via the channel Ch1.

At this time, the relay chip IF starts the prefetch operation for the chip (1) via the non-selected channel Ch0. That is, the chip (1) transfers at least some of the read data to the relay chip IF as the data signal DQ[Ch0] via the channel Ch0. The relay chip IF starts storing (prefetching) the transferred data signal DQ[Ch0] in the FIFO circuit13.

When the period TP62ends, the chip enable signal CE0−is maintained at the non-active level because the prefetch operation is being continued for the chip (1). In response, the relay chip IF keeps the channel Ch0 non-selected. At the same time, the relay chip IF non-selects the channel Ch1 as the chip enable signal CE1−transitions to the non-active level.

At this time, the relay chip IF starts the prefetch operation for the chip (2) via the non-selected channel Ch1. That is, the chip (2) transfers at least some of the read data to the relay chip IF as the data signal DQ[Ch1] via the channel Ch1. The relay chip IF starts storing (prefetching) the transferred data signal DQ[Ch1] in the FIFO circuit14.

Thereafter, the prefetch operation for the chip (1) is completed, and further, the prefetch operation for the chip (2) is completed.

When a period TP63starts, the relay chip IF selects the channel Ch0 as the chip enable signal CE0−transitions to the active level, and selects the channel Ch1 as the chip enable signal CE1−transitions to the active level. In this state, the relay chip IF transfers the prefetched data signal DQ of the chip (1) and the prefetched data signal DQ of the chip (2) to the host HA in a time-division manner via the host channel HCh. In parallel, the relay chip IF internally shifts the prefetched data signal DQ transferred from the chip (1) between the plurality of queue entries of the FIFO circuit13, and internally shifts the prefetched data signal DQ transferred from the chip (2) between the plurality of queue entries of the FIFO circuit14. Then, the relay chip IF transfers the data signal DQ transferred from the chip (1) in the period TP63and transfers the data signal DQ transferred from the chip (2) in the period TP63, to the host HA in a time-division manner via the host channel HCh.

At the timing when the period TP63ends, the relay chip IF completes the transfer of the data signal DQ of the chip (1) and the data signal DQ of the chip (2) to the host HA.

Thereafter, in periods TP71to TP73as well, the same operations as in the periods TP61to TP63are performed.

Here, for the data signals DQ of the chips (1) and (2), the relay chip IF performs the data transfer from the chip (1) to the host HA via the channel Ch0 and the data transfer from the chip (2) to the host HA via the channel Ch1 in a time-divided manner in a selection period (e.g., the period TP63) for the simultaneous access of the channels Ch0 and Ch1. As a result, in the read process, the data transfer from the semiconductor device1to the host HA can be substantially doubled beyond the maximum speeds of the channels Ch0 and Ch1.

The data transfer for the subsequent chips (i.e., chips (3) to (7)) are the same as that for the chips (1) and (2).

As illustrated inFIG.17, the configuration of the relay chip IF for performing the simultaneous-access inter-channel interleaving operation in the read process is different from the first embodiment in the following points.FIG.17is a diagram illustrating the configuration of the relay chip IF.

The relay chip IF includes a multiplexer (MUX)211and a frequency dividing circuit212instead of the switching circuit11and the switching circuit12(seeFIG.6).

The multiplexer211switches between a fifth connection state and a sixth connection state according to the chip enable signal CE0−, the chip enable signal CE1−, and the read enable signals RE and RE−. The fifth connection state is a state in which the terminal group21aand the data node13aof the FIFO circuit13are connected to each other. The sixth connection state is a state in which the terminal group21aand the data node14aof the FIFO circuit14are connected to each other.

When the chip enable signal CE0−is at the active level, the chip enable signal CE1−is at the active level, and the read enable signals RE and RE−are toggled, the multiplexer211switches to the fifth connection state according to the even-numbered edges of the toggle of the read enable signals RE and RE−, and switches to the sixth connection state according to the odd-numbered edges of the toggle of the read enable signals RE and RE−.

The multiplexer211operates in the same way as the switching circuit11in that the multiplexer211switches to the fifth connection state as the chip enable signal CE0−is at the active level and the chip enable signal CE1−is at the non-active level, and switches to the sixth connection state as the chip enable signal CE0−is at the non-active level and the chip enable signal CE1−is at the active level.

When the read enable signals RE and RE−are toggled, the frequency dividing circuit212divides the frequency of the read enable signals RE and RE−by two to generate read enable signals RE′ and RE−′. The generated read enable signals RE′ and RE−′ toggle at the half speed of the read enable signals RE and RE−. The frequency dividing circuit212supplies the read enable signals RE′ and RE−′ to the FIFO circuits13and14.

As the chip enable signal CE0−is at the active level and the chip enable signal CE1−is at the active level, the control circuit16generates the read enable signals RE0 and RE0−to be toggled and supplies the signals to the chip MC0, and generates the read enable signals RE1 and RE1−to be toggled and supplies the signals to the chip MC1. As a result, the relay chip IF can change the read enable signals to be supplied to the chip MC via the channel Ch from the read enable signals RE and RE−of the host HA to the read enable signal RE0, RE0−, RE1, and RE1 of the control circuit16.

As illustrated inFIGS.18and19A to19D, the relay chip IF transmits the data signals DQ of the chips MC0and MC1to the host HA in a time-division manner in a selection period for the simultaneous access of the channels Ch0 and Ch1.FIG.18is a waveform diagram illustrating the operation of the relay chip IF.FIGS.19A to19Dare diagrams illustrating the operation of the relay chip IF.FIGS.19A to19Dillustrate the operation of the relay chip IF in the period TP63illustrated inFIG.16.

FIG.18illustrates a case where the maximum speed of the host channel HCh is twice the maximum speed of each of the channels Ch0 and Ch1.

The toggle frequency of the read enable signals RE and RE−supplied from the host HA to the relay chip IF via the host channel HCh is twice the toggle frequency of the read enable signals RE0 and RE0−generated by the control circuit16and supplied to the chip MC0via the channel Ch0. The toggle frequency of the read enable signals RE and RE−is twice the toggle frequency of the read enable signals RE1 and RE1 generated by the control circuit16and supplied to the chip MC1via the channel Ch1.

The toggle frequency of the data strobe signals DQS and DQS−supplied from the relay chip IF to the host HA via the host channel HCh is twice the toggle frequency of the data strobe signals DQS0 and DQS0−supplied from the chip MC0to the relay chip IF via the channel Ch0. The toggle frequency of the data strobe signals DQS and DQS−is twice the toggle frequency of the data strobe signals DQS1 and DQS1−supplied from the chip MC1to the relay chip IF via the channel Ch1.

Immediately before timing t51, the relay chip IF selects the channel Ch0 as the chip enable signal CE0−transitions to the active level, and selects the channel Ch1 as the chip enable signal CE1−transitions to the active level. Thereafter, the selectors17and18maintain the input nodes17aand18aat the selected state, and supply the chip enable signals CE0−and CE1−from the host HA to the chips MC0and MC1via the channels Ch0 and Ch1, respectively.

By this time, in the relay chip IF, the FIFO circuit13has prefetched the data signal DQ[Ch0] of the chip MC0via the channel Ch0, and the FIFO circuit14has prefetched the data signal DQ[Ch1] of the chip MC1via the channel Ch1.

At timing t51, the read enable signals RE and RE−start to be toggled. As illustrated inFIGS.18and19A, the relay chip IF transmits the prefetched data signal DQ[Ch0] of the chip MC0to the host HA, according to the 0th edge of the read enable signals RE and RE−.

At timing t52, as illustrated inFIGS.18and19B, the relay chip IF transmits the prefetched data signal DQ[Ch1] of the chip MC1to the host HA, according to the first edge of the read enable signals RE and RE−.

At timing t53, as illustrated inFIGS.18and19A, the relay chip IF transmits the prefetched data signal DQ[Ch0] of the chip MC0to the host HA, according to the second edge of the read enable signals RE and RE−.

At this time, in response to the data strobe signals DQS0 and DQS0−, the relay chip IF stores in the FIFO circuit13the data signal DQ[Ch0] transferred from the chip MC0via the channel Ch0. Further, in response to the data strobe signals DQS1 and DQS1−, the relay chip IF stores in the FIFO circuit14the data signal DQ[Ch1] transferred from the chip MC1via the channel Ch1.

At timing t54, as illustrated inFIGS.18and19B, the relay chip IF transmits the prefetched data signal DQ[Ch1] of the chip MC1to the host HA, according to the third edge of the read enable signals RE and RE−.

At timing t55, as illustrated inFIGS.18and19C, the relay chip IF transmits the data signal DQ[Ch0] of the chip MC0transferred via the channel Ch0 to the host HA, according to the fourth edge of the read enable signals RE and RE−.

At this time, in response to the data strobe signals DQS0 and DQS0−, the relay chip IF stores in the FIFO circuit13the data signal DQ[Ch0] transferred from the chip MC0via the channel Ch0. Further, in response to the data strobe signals DQS1 and DQS1−, the relay chip IF stores in the FIFO circuit14the data signal DQ[Ch1] transferred from the chip MC1via the channel Ch1.

At timing t56, as illustrated inFIGS.18and19D, the relay chip IF transmits the data signal DQ[Ch1] of the chip MC1transferred via the channel Ch1 to the host HA, according to the fifth edge of the read enable signals RE and RE−.

Thereafter, the same operations as timings t55and t56are alternately repeated for each edge of the read enable signals RE and RE−until the transfer of the total amount of data to be transmitted to the host HA is completed.

The amount of data prefetched in the FIFO circuits13and14immediately before timing t51may be experimentally obtained in advance based on the amount of data that can be transmitted to the host HA from the FIFO circuits13and14until the data signal transferred from the chip can be transmitted to the host HA after the timing t51(in the case ofFIG.18, the data amount corresponding to four toggles of the read enable signals RE and RE−). As a result, the data transfer from the relay chip IF to the host HA can be started at an early timing.

As described above, in the fourth embodiment, the semiconductor device1can speed up the data transfer via the channel Ch in the semiconductor device1in the read process beyond the maximum speed of the channel Ch by the function of the simultaneous-access inter-channel interleaving operation.

As illustrated inFIG.20, the relay chip IF for performing the simultaneous-access inter-channel interleaving operation in the read process may be configured to pass the read enable signals RE and RE−of the host HA.FIG.20is a diagram illustrating the configuration of a relay chip IF in a modification of the fourth embodiment. The relay chip IF illustrated inFIG.20is different from the relay chip IF illustrated inFIG.17in that the oscillator15, the control circuit16, the selector17, and the selector18are omitted and lines extending from the frequency dividing circuit212to the FIFO circuits13and14branch and extend to the terminals22cand22g, respectively. The terminal21dis connected to the terminal22d, and the chip enable signal CE0−from the host HA is supplied to the chip MC0via the channel Ch0. The terminal21eis connected to the terminal22h, and the chip enable signal CE1−from the host HA is supplied to the chip MC1via the channel Ch1.

When the read enable signals RE and RE−are toggled, the frequency dividing circuit212divides the frequency of the read enable signals RE and RE−by two according to the even-numbered edges of the toggle of the read enable signals RE and RE−to generate the read enable signals RE0 and RE0−to be toggled at the half speed of the read enable signals RE and RE−. The frequency dividing circuit212supplies the read enable signals RE0 and RE0−to be toggled at the half speed to the FIFO circuit13, and also supplies them to the chip MC0via the channel Ch0. That is, the relay chip IF substantially passes the read enable signals RE and RE−from the host HA while dividing the frequency thereof, and supplies the divided read enable signals RE and RE−to the chip MC0via the channel Ch0.

Further, the frequency dividing circuit212logically inverts the read enable signals RE and RE−and divides the frequency thereof by two according to the odd-numbered edges of the toggle of the read enable signals RE and RE−, to generate the read enable signals RE1 and RE1−to be toggled at the half speed of the read enable signals RE and RE−. The frequency dividing circuit212supplies the read enable signals RE1 and RE1−to be toggled at the half speed to the FIFO circuit14, and also supplies them to the chip MC1via the channel Ch1. That is, the relay chip IF substantially passes the read enable signals RE and RE−from the host HA while dividing the frequency thereof, and supplies the divided read enable signals RE and RE−to the chip MC1via the channel Ch1.

Further, as illustrated inFIGS.21and22A to22D, the operation of the relay chip IF illustrated inFIG.20is different from that of the relay chip IF illustrated inFIG.17in the following points.FIGS.21and22A to22Dillustrate the operation of the relay chip IF in the period TP63illustrated inFIG.16. The description of the same portions as those inFIGS.18and19A to19Dwill be omitted.

At timing t61, the read enable signals RE and RE−start to be toggled. As illustrated inFIGS.21and22A, the relay chip IF transmits the prefetched data signal DQ[Ch0] of the chip MC0to the host HA, according to the 0th edge of the read enable signals RE and RE−.

At this time, the frequency dividing circuit212divides the frequency of the read enable signals RE and RE−by two to generate the read enable signals RE0 and RE0−, supplies the read enable signals RE0 and RE0−to the FIFO circuit13, and also supplies them to the chip MC0via the channel Ch0.

At timing t62, as illustrated inFIGS.21and22B, the relay chip IF transmits the prefetched data signal DQ[Ch1] of the chip MC1to the host HA, according to the first edge of the read enable signals RE and RE−.

At this time, the frequency dividing circuit212logically inverts the read enable signals RE and RE−, divides the frequency thereof by two to generate the read enable signals RE1 and RE1−, supplies the read enable signals RE1 and RE1−to the FIFO circuit14, and also supplies the signals to the chip MC1via the channel Ch1.

At timing t63, as illustrated inFIGS.21and22A, the relay chip IF transmits the prefetched data signal DQ[Ch0] of the chip MC0to the host HA, according to the second edge of the read enable signals RE and RE−.

At this time, in response to the data strobe signals DQS0 and DQS0−, the relay chip IF stores in the FIFO circuit13the data signal DQ[Ch0] transferred from the chip MC0via the channel Ch0 by the amount of data having been transmitted to the host HA.

At timing t64, as illustrated inFIGS.21and22B, the relay chip IF transmits the prefetched data signal DQ[Ch1] of the chip MC1to the host HA, according to the third edge of the read enable signals RE and RE−.

At this time, in response to the data strobe signals DQS1 and DQS1−, the relay chip IF stores in the FIFO circuit14the data signal DQ[Ch1] transferred from the chip MC1via the channel Ch1 by the amount of data having been transmitted to the host HA.

At timing t65, as illustrated inFIGS.21and22C, the relay chip IF transmits the data signal DQ[Ch0] of the chip MC0transferred via the channel Ch0 to the host HA, according to the fourth edge of the read enable signals RE and RE−.

At this time, in response to the data strobe signals DQS0 and DQS0−, the relay chip IF stores in the FIFO circuit13the data signal DQ[Ch0] transferred from the chip MC0via the channel Ch0 by the amount of data having been transmitted to the host HA.

At timing t66, as illustrated inFIGS.21and22D, the relay chip IF transmits the data signal DQ[Ch1] of the chip MC1transferred via the channel Ch1 to the host HA, according to the fifth edge of the read enable signals RE and RE−.

At this time, in response to the data strobe signals DQS1 and DQS1−, the relay chip IF stores in the FIFO circuit14the data signal DQ[Ch1] transferred from the chip MC1via the channel Ch1 by the amount of data having been transmitted to the host HA.

In this way, the relay chip IF illustrated inFIG.20can perform the simultaneous-access inter-channel interleaving operation in the read process.

Fifth Embodiment

Next, a semiconductor device1according to a fifth embodiment will be described. Hereinafter, portions different from the first to fourth embodiments will be mainly described.

In the fourth embodiment, the read process by the function of the simultaneous-access inter-channel interleaving operation is illustrated, but in the fifth embodiment, a write process by the function of the simultaneous-access inter-channel interleaving operation will be illustrated.

As illustrated inFIG.23, the semiconductor device1may perform the simultaneous-access inter-channel interleaving operation for the write process.FIG.23is a diagram illustrating the operation of the semiconductor device1.FIG.23illustrates the inter-channel interleaving operation performed by simultaneously selecting the channels Ch0 and Ch1 for the write process.FIG.23illustrates the operation of periods corresponding to the period TP41to the first half of the period TP43illustrated inFIG.12.

Here, it is assumed as an example that the maximum speed of the host channel HCh is twice the maximum speed of each of the channels Ch0 and Ch1.

When a period TP81starts, the relay chip IF selects the channel Ch0 as the chip enable signal CE0−transitions to the active level, and keeps the channel Ch1 non-selected as the chip enable signal CE1−is maintained at the non-active level. In this state, the relay chip IF transmits the commands “80h−” received via the host channel HCh to the chip (1) as the data signal DQ[Ch0] via the channel Ch0.

When the period TP81ends and a period TP82starts, the relay chip IF non-selects the channel Ch0 as the chip enable signal CE0−transitions to the non-active level, and selects the channel Ch1 as the chip enable signal CE1−transitions to the active level. In this state, the relay chip IF transfers the commands “80h−” received via the host channel HCh to the chip (2) as the data signal DQ[Ch1] via the channel Ch1.

When the period TP82ends and a period TP83starts, the relay chip IF selects the channel Ch0 as the chip enable signal CE0−transitions to the active level, and keeps the channel Ch1 selected as the chip enable signal CE1−is maintained at the active level. In this state, the relay chip IF receives the write data for the chip (1) and the write data for the chip (2) from the host HA in a time-division manner via the host channel HCh. In parallel, the relay chip IF starts transferring the write data to the chip (1) via the channel Ch0 and transferring the write data to the chip (2) via the channel Ch1 in a time-division manner according to the operation “DIN”. As a result, the relay chip IF performs the write data transfer operation to the chip (1) via the channel Ch0 and the write data transfer operation to the chip (2) via the channel Ch1 in parallel with each other.

When the operation “DIN” is completed, the relay chip IF receives the command “10h” for the chip (1) and the command “10h” for the chip (2) from the host HA in a time-division manner via the host channel HCh. In parallel, the relay chip IF starts the transfer of the command “10h” to the chip (1) via the channel Ch0 and the transfer of the command “10h” to the chip (2) via the channel Ch1 in a time-division manner. As a result, the relay chip IF performs the issuing operation of the command “10h” to the chip (1) via the channel Ch0 and the issuing operation of the command “10h” to the chip (2) via the channel Ch1 in parallel with each other.

At the timing when the period TP83ends, the relay chip IF completes the issuing operation of the command “10h” to the chip (1) and the issuing operation of the command “10h” to the chip (2).

Thereafter, in periods TP91to TP93as well, the same operations as in the periods TP81to TP83are performed.

Here, for the data signals DQ of the chips (1) and (2), the relay chip IF performs the reception of the write data for the chip (1) and the write data for the chip (2) from the host HA, and performs the transfer of the write data for the chip (1) and the write data of the chip (2) to the chips MC0and MC1via the channels Ch0 and Ch1, respectively, in a time-divided manner in a selection period (e.g., during the period TP83) for the simultaneous access of the channels Ch0 and Ch1. As a result, in the write process, the data transfer from the host HA to the semiconductor device1can be substantially doubled beyond the maximum speeds of the channels Ch0 and Ch1.

The data transfer for the subsequent chips (i.e., chips (3) to (7)) are the same as that for the chips (1) and (2).

As illustrated inFIG.24, the configuration of the relay chip IF for performing the simultaneous-access inter-channel interleaving operation in the write process is different from that of the third embodiment in the following points.FIG.24is a diagram illustrating the configuration of the relay chip IF.

The relay chip IF includes a sampler311and a frequency dividing circuit312, instead of the switching circuit11and the switching circuit12(seeFIG.13).

On the sampler311, a data node311ais connected to the terminal group21a, a clock node311bis connected to the terminal group21b, an output node311cis connected to the FIFO circuit13, and an output node311dis connected to the FIFO circuit14. The sampler311samples the data signal DQ and switches an output destination of the sampled data signal DQ according to the chip enable signal CE0−, the chip enable signal CE1−, and the data strobe signals DQS and DQS−.

When the chip enable signal CE0−is at the active level, the chip enable signal CE1−is at the active level, and the data strobe signals DQS and DQS−are toggled, the sampler311switches the output destination to the FIFO circuit13according to the even-numbered edge of the toggle of the data strobe signals DQS and DQS−, and switches the output destination to the FIFO circuit14according to the odd-numbered edges of the toggle of the data strobe signals DQS and DQS−.

The sampler311also switches the output destination to the FIFO circuit13as the chip enable signal CE0−is at the active level and the chip enable signal CE1−is at the non-active level, and also switches the output destination to the FIFO circuit14as the chip enable signal CE0−is at the non-active level and the chip enable signal CE1−is at the active level to transfer the data signal DQ. This is the same as the operation of the switching circuit11.

When the data strobe signals DQS and DQS−are toggled, the frequency dividing circuit312divides the frequency of the data strobe signals DQS and DQS−by two to generate data strobe signals DQS′ and DQS−′. The generated data strobe signals DQS′ and DQS−′ toggle at the half speed of the data strobe signals DQS and DQS−. The frequency dividing circuit312supplies the data strobe signals DQS′ and DQS−′ to the FIFO circuits13and14.

As the chip enable signal CE0−is at the active level and the chip enable signal CE1−is at the active level, the control circuit16generates the data strobe signals DQS0 and DQS0−to be toggled and supplies the signals to the chip MC0, and generates the data strobe signals DQS1 and DQS1−to be toggled and supplies the signals to the chip MC1. As a result, the relay chip IF can change the data strobe signals to be supplied to the chip MC via the channel Ch from the data strobe signals DQS and DQS−of the host HA to the data strobe signals DQS0, DQS0−, DQS1, and DQS1 of the control circuit16.

As illustrated inFIGS.25and26A to26D, the relay chip IF receives the data signals DQ for the chips MC0and MC1from the host HA in a time-division manner and transfers them to the chips MC0and MC1in a time-division manner in a selection period for the simultaneous access of the channels Ch0 and Ch1.FIG.25is a waveform diagram illustrating the operation of the relay chip IF.FIGS.26A to26Dare diagrams illustrating the operation of the relay chip IF.FIGS.26A to26Dillustrate the operation “DIN” of the relay chip IF in the period TP83illustrated inFIG.23.

FIG.25illustrates a case where the maximum speed of the host channel HCh is twice the maximum speed of each of the channels Ch0 and Ch1.

The toggle frequency of the data strobe signals DQS and DQS−supplied from the host HA to the relay chip IF via the host channel HCh is twice the toggle frequency of the data strobe signals DQS0 and DQS0−supplied from the control circuit16to the FIFO circuit13and the chip MC0via the channel Ch0. The toggle frequency of the data strobe signals DQS and DQS−is twice the toggle frequency of the data strobe signals DQS1 and DQS1 supplied from the control circuit16to the FIFO circuit14and the chip MC1via the channel Ch1.

Immediately before timing t71, the relay chip IF selects the channel Ch0 as the chip enable signal CE0−transitions to the active level, and selects the channel Ch1 as the chip enable signal CE1−transitions to the active level. Thereafter, the selectors17and18maintain the input nodes17aand18aat the selected state, and supply the chip enable signals CE0−and CE1−from the host HA to the chips MC0and MC1via the channels Ch0 and Ch1, respectively.

At the timing t71, the data strobe signals DQS and DQS start to be toggled. As illustrated inFIGS.25and26A, the relay chip IF receives the write data for the chip MC0via the host channel HCh and stores the write data in the FIFO circuit13, according to the 0th edge of the data strobe signals DQS and DQS−.

At timing t72, as illustrated inFIGS.25and26B, the relay chip IF receives the write data for the chip MC1via the host channel HCh and stores the write data in the FIFO circuit14, according to the first edge of the data strobe signals DQS and DQS−. At this time, the FIFO circuit13keeps the write data of the chip MC0stored therein.

At timing t73, as illustrated inFIGS.25and26C, the relay chip IF receives the write data for the chip MC0via the host channel HCh and stores the write data in the FIFO circuit13, according to the second edge of the data strobe signals DQS and DQS−.

At this time, the relay chip IF transfers the write data for the chip MC0stored in the FIFO circuit13to the chip MC0via the channel Ch0 in response to the data strobe signals DQS0 and DQS0−. Further, the relay chip IF transfers the write data for the chip MC1stored in the FIFO circuit14to the chip MC1via the channel Ch1 in response to the data strobe signals DQS1 and DQS1−.

At timing t74, as illustrated inFIGS.25and26D, the relay chip IF receives the write data for the chip MC1via the host channel HCh and stores the write data in the FIFO circuit14, according to the third edge of the data strobe signals DQS and DQS−. At this time, the FIFO circuit13keeps the write data of the chip MC0stored therein.

Thereafter, until the transfer of the total amount of data received from the host HA is completed, the same operations as the timings t73and t74are alternately repeated for each edge of the toggle of the data strobe signals DQS and DQS−.

As described above, in the fifth embodiment, the semiconductor device1can speed up the data transfer via the channel Ch in the semiconductor device1in the write process beyond the maximum speed of the channel Ch by the function of the simultaneous-access inter-channel interleaving operation.

As illustrated inFIG.27, the relay chip IF for performing the simultaneous-access inter-channel interleaving operation in the write process may be configured to pass the data strobe signals DQS and DQS−of the host HA.FIG.27is a diagram illustrating the configuration of a relay chip IF in a modification of the fifth embodiment. The relay chip IF illustrated inFIG.27is different from the relay chip IF illustrated inFIG.24in that the FIFO circuit13, the FIFO circuit14, the oscillator15, the control circuit16, the selector17, and the selector18are omitted and lines extend from the frequency dividing circuit312to the terminals22band22f. The terminal21dis connected to the terminal22d, and the chip enable signal CE0−from the host HA is supplied to the chip MC0via the channel Ch0. The terminal21eis connected to the terminal22h, and the chip enable signal CE1−from the host HA is supplied to the chip MC1via the channel Ch1.

When the data strobe signals DQS and DQS−are toggled, the frequency dividing circuit312divides the frequency of the data strobe signals DQS and DQS−by two according to the even-numbered edges of the toggle of the data strobe signals DQS and DQS−to generate the data strobe signals DQS0 and DQS0−to be toggled at the half speed of the data strobe signals DQS and DQS−. The frequency dividing circuit312supplies the data strobe signals DQS0 and DQS0−to be toggled at the half speed to the chip MC0via the channel Ch0. That is, the relay chip IF substantially passes the data strobe signals DQS and DQS from the host HA while dividing the frequency thereof, and supplies the divided data strobe signals DQS and DQS−to the chip MC0via the channel Ch0.

Further, the frequency dividing circuit312logically inverts the data strobe signals DQS and DQS−and divides the frequency thereof by two according to the odd-numbered edges of the toggle of the data strobe signals DQS and DQS−, to generate the data strobe signals DQS1 and DQS1−to be toggled at the half speed of the data strobe signals DQS and DQS−. The frequency dividing circuit312supplies the data strobe signals DQS1 and DQS1−to be toggled at the half speed to the chip MC1via the channel Ch1. That is, the relay chip IF substantially passes the data strobe signals DQS and DQS−from the host HA while dividing the frequency thereof, and supplies the divided data strobe signals DQS and DQS−to the chip MC1via the channel Ch1.

Further, as illustrated inFIGS.28,29A, and29B, the operation of the relay chip IF illustrated inFIG.27is different from that of the relay chip IF illustrated inFIG.24in the following points.FIGS.28,29A, and29Billustrate the operation “DIN” of the relay chip IF in the period TP83illustrated inFIG.23. The description of the same portions as those inFIGS.25and26A to26Cwill be omitted.

At timing t81, the data strobe signals DQS and DQS−start to be toggled. As illustrated inFIGS.28and29A, the relay chip IF transfers the data signal DQ for the chip MC0received via the host channel HCh to the chip MC0, according to the 0th edge of the data strobe signals DQS and DQS−.

At this time, the frequency dividing circuit312divides the frequency of the data strobe signals DQS and DQS−by two to generate the data strobe signals DQS0 and DQS0−. The frequency dividing circuit312transfers the data strobe signals DQS0 and DQS0−to the chip MC0via the channel Ch0.

At timing t82, as illustrated inFIGS.28and29B, the relay chip IF transfers the data signal DQ for the chip MC1received via the host channel HCh to the chip MC1via the channel Ch1, according to the first edge of the data strobe signals DQS and DQS−.

At this time, the frequency dividing circuit312logically inverts the data strobe signals DQS and DQS−and divides the frequency thereof by two to generate the data strobe signals DQS1 and DQS1−. The frequency dividing circuit312transfers the data strobe signals DQS1 and DQS1−to the chip MC1via the channel Ch1.

At timing t83, as illustrated inFIGS.28and29A, the relay chip IF transfers the data signal DQ for the chip MC0received via the host channel HCh to the chip MC0via the channel Ch0, according to the second edge of the data strobe signals DQS and DQS−.

At this time, the frequency dividing circuit312divides the data strobe signals DQS and DQS−by two to generate the data strobe signals DQS0 and DQS0−. The frequency dividing circuit312transfers the data strobe signals DQS0 and DQS0−to the chip MC0via the channel Ch0.

Thereafter, the same operations as the timings t82and t83are alternately repeated for each edge of the data strobe signals DQS and DQS−until the transfer of the total amount of data received from the host HA is completed.

In this way, the relay chip IF illustrated inFIG.27can also perform the simultaneous-access inter-channel interleaving operation in the write process.

Sixth Embodiment

Next, a semiconductor device1according to a sixth embodiment will be described. Hereinafter, portions different from the first to fifth embodiments will be mainly described.

In the first embodiment, the simplified configuration of the relay chip IF is illustrated, but in the sixth embodiment, another example of the configuration of the relay chip IF will be illustrated.

The relay chip IF is configured to store a command when the command is to be issued to a chip MC via a selected channel Ch. Thereby, it is possible to control the data transfer according to the command with respect to the chip MC after the channel Ch becomes non-selected. Further, it is possible to control the data transfer according to the command with the host HA after the channel Ch becomes selected again.

For example, the relay chip IF may be configured as illustrated inFIG.30.FIG.30is a diagram illustrating the configuration of the relay chip IF.

The relay chip IF includes a host interface (I/F) circuit411, a selector412, a FIFO circuit413, a FIFO circuit414, a command storage circuit415, a command storage circuit416, a channel interface (I/F) circuit417, a channel interface (I/F) circuit418, an ALE/CLE/WE−switching circuit419, a terminal group421, and a terminal group422.

The terminal group421further includes a terminal group21fin addition to the terminal group21(seeFIG.6). The terminal group21fincludes a terminal for an address latch enable signal H_ALE, a terminal for a command latch enable signal H_CLE, and a terminal for a write enable signal H_WE−.

The terminal group422further includes terminal groups22iand22jin addition to the terminal group22(seeFIG.6). The terminal group22iincludes a terminal for an address latch enable signal N0_ALE, a terminal for a command latch enable signal N0_CLE, and a terminal for a write enable signal N0_WE−. The terminal group22jincludes a terminal for an address latch enable signal N1_ALE, a terminal for a command latch enable signal N1_CLE, and a terminal for a write enable signal N1_WE−.

The ALE/CLE/WE−switching circuit419is disposed between the terminal group21fand the terminal groups22iand22j. The ALE/CLE/WE−switching circuit419switches the connection between the terminal group21fand the terminal groups22iand22jaccording to chip enable signals H_CE0−and H_CE1−. The ALE/CLE/WE−switching circuit419connects the terminal group21fto the terminal group22iwhen the chip enable signal H_CE0 is at the active level and the chip enable signal H_CE1−is at the non-active level. The ALE/CLE/WE−switching circuit419connects the terminal group21fto the terminal group22jwhen the chip enable signal H_CE0−is at the non-active level and the chip enable signal H_CE1−is at the active level.

The FIFO circuit413is electrically connected between the host interface circuit411and the channel interface circuit417. The FIFO circuit413is a circuit for the channel Ch0 and has the same function as the FIFO circuit13(seeFIG.6).

The FIFO circuit414is electrically connected between the host interface circuit411and the channel interface circuit418. The FIFO circuit414is a circuit for the channel Ch1 and has the same function as the FIFO circuit14(seeFIG.6).

The command storage circuit415is electrically connected between the terminal group421, the selector412, and the channel interface circuit417. The command storage circuit415is a circuit for the channel Ch0. When the command latch enable signal H_CLE is at the active level and the chip enable signal H_CE0−is at the active level, the command storage circuit415stores a command in a data signal DQ<7:0> from the host HA. The command storage circuit415generates a control signal S0corresponding to the channel Ch0 according to the stored command and supplies the control signal S0to the selector412and the channel interface circuit417.

The command storage circuit416is electrically connected between the terminal group421, the selector412, and the channel interface circuit418. The command storage circuit416is a circuit for the channel Ch1. When the command latch enable signal H_CLE is at the active level and the chip enable signal H_CE1−is at the active level, the command storage circuit416stores a command in the data signal DQ<7:0> from the host HA. The command storage circuit416generates a control signal S1corresponding to the channel Ch1 according to the stored command and supplies the control signal S1to the selector412and the channel interface circuit418.

On the selector412, an input node412ais connected to the command storage circuit415, an input node412bis connected to the command storage circuit416, and an output node412cis connected to the host interface circuit411. The selector412supplies the control signal S0to the host interface circuit411by selecting the input node412a, and supplies the control signal S1to the host interface circuit411by selecting the input node412b.

The host interface circuit411is electrically connected among the terminal group421, the selector412, the FIFO circuit413, and the FIFO circuit414, and performs an interface operation for the host HA.

The host interface circuit411switches between the first connection state and the second connection state according to the control signal S0and the control signal S1. The first connection state is a state in which the terminal group21aand the FIFO circuit413are connected to each other. The second connection state is a state in which the terminal group21aand the FIFO circuit414are connected to each other. The host interface circuit411switches to the first connection state in response to an instruction by the control signal S0to select the channel Ch0 and to perform data transfer, and switches to the second connection state in response to an instruction by the control signal S1to select the channel Ch1 and to perform data transfer.

The host interface circuit411also switches between the third connection state and the fourth connection state according to the control signal S0and the control signal S1. The third connection state is a state in which the terminal group21cand the FIFO circuit413are connected to each other. The fourth connection state is a state in which the terminal group21cand the FIFO circuit414are connected to each other. The host interface circuit411switches to the third connection state in response to an instruction by the control signal S0to select the channel Ch0 and to perform the data transfer, and switches to the fourth connection state in response to an instruction by the control signal S1to select the channel Ch1 and to perform the data transfer.

The channel interface circuit417is electrically connected among the FIFO circuit413, the command storage circuit415, and the terminal group422. The channel interface circuit417is a circuit for the channel Ch0 and performs an interface operation for the channel Ch0. The channel interface circuit417issues a command in response to an instruction by the control signal S0to select the channel Ch0 and to issue o the command, and supplies it as a data signal N0_DQ<7:0> to the chip MC0via the channel Ch0. The channel interface circuit417generates a read enable signal N0_RE−to be toggled in response to an instruction to non-select the channel Ch0 and to perform the data transfer, supplies the signal to the chip MC0via the channel Ch0, and transfers the data signal N0_DQ<7:0> and a data strobe signal NO DQS, which are transferred from the chip MC0via the channel Ch0, to the FIFO circuit413. The channel interface circuit417also generates the read enable signal NO RE to be toggled in response to an instruction to select the channel Ch0 and to perform the data transfer, supplies the signal to the chip MC0via the channel Ch0, and transfers the data signal NO DQ<7:0> and the data strobe signal NO DQS, which are transferred from the chip MC0via the channel Ch0, to the FIFO circuit413.

The channel interface circuit418is electrically connected among the FIFO circuit414, the command storage circuit416, and the terminal group422. The channel interface circuit418is a circuit for the channel Ch1 and performs an interface operation for the channel Ch1. The channel interface circuit418issues a command in response to an instruction by the control signal S1to select the channel Ch1 and to issue the command, and supplies it as a data signal N1_DQ<7:0> to the chip MC1via the channel Ch1. The channel interface circuit418generates a read enable signal N1_RE−to be toggled in response to an instruction to non-select the channel Ch0 and to perform the data transfer, supplies the signal to the chip MC1via the channel Ch1, and transfers the data signal N1_DQ<7:0> and a data strobe signal N1_DQS, which are transferred from the chip MC1via the channel Ch1, to the FIFO circuit414. The channel interface circuit418also generates the read enable signal N1_RE−to be toggled in response to an instruction to select the channel Ch1 and to perform the data transfer, supplies the signal to the chip MC1via the channel Ch1, and transfers the data signal N1_DQ<7:0> and the data strobe signal N1_DQS, which are transferred from the chip MC1via the channel Ch1, to the FIFO circuit414.

As described above, in the sixth embodiment, the semiconductor device1can implement the inter-channel interleaving operation with the configuration as illustrated inFIG.30.

Seventh Embodiment

Next, a semiconductor device1according to a seventh embodiment will be described. Hereinafter, portions different from the first to sixth embodiments will be mainly described.

In the fifth embodiment, the configuration in the case where the maximum speed of the channel Ch in the semiconductor device1is lower than (e.g., ½ times) the maximum speed of the host channel HCh is illustrated, but in the seventh embodiment, a configuration in a case where the maximum speed of the channel Ch in the semiconductor device1is equal to or higher than the maximum speed of the host channel HCh is illustrated.

In order to take advantage of the high speed of the channel Ch in the semiconductor device1, it is desired to reduce the number lines between the relay chip IF and chips MC to speed up a data transfer timing signal.

For example, the relay chip IF may be configured as illustrated inFIG.31.FIG.31is a diagram illustrating the configuration of the relay chip IF.

In the semiconductor device1according to the seventh embodiment, the channel Ch1 and the chips MC1-1to MC1-4are omitted. The relay chip IF includes a sampler511, a FIFO circuit513, a counter circuit514, an oscillator515, a control circuit516, a terminal group21, and a terminal group22.

The sampler511is electrically connected between the terminal group21and the FIFO circuit513. On the sampler511, a data node511ais connected to the terminal group21a, a clock node511bis connected to the terminal group21b, and an output node511cis connected to the FIFO circuit513. The sampler511samples a data signal H_DQ and outputs the sampled data signal H_DQ to the FIFO circuit513in response to a data strobe signal H_DQS.

The FIFO circuit513is electrically connected between the terminal group21, the sampler511, and the terminal group22. On the FIFO circuit513, a data node513ais connected to the sampler511, a clock node513bis connected to the terminal group21b, a data node513cis connected to the terminal group22a, and a clock node513dis connected to the terminal group22b. The FIFO circuit513has the same function as the FIFO circuit13(seeFIG.24), but differs from the FIFO circuit13in that the FIFO circuit513receives the data signal H_DQ in response to the data strobe signal H_DQS from the host HA.

The counter circuit514is electrically connected between the terminal group21and the control circuit516. On the counter circuit514, an input node514ais connected to the terminal group21b, and an output node514bis connected to the control circuit516. When the data strobe signal H_DQS is toggled, the counter circuit514counts the number of toggles of the data strobe signal H_DQS and outputs the count result to the control circuit516.

The oscillator515performs an oscillation operation to generate an oscillation signal. The frequency of the oscillation signal may be equal to the toggle frequency of the data strobe signal H_DQS, or may be higher than the frequency of the data strobe signal H_DQS. The oscillator515outputs the oscillation signal to the control circuit516.

The control circuit516is electrically connected among the counter circuit514, the oscillator515, the FIFO circuit513, and the terminal group22. On the control circuit516, an input node516ais connected to the oscillator515, an input node516bis connected to the counter circuit514, and an output node516cis connected to the FIFO circuit513and the terminal group22.

The control circuit516uses the oscillation signal to generate a data strobe signal N_DQS to be toggled at a frequency equal to or higher than the frequency of the data strobe signal H_DQS, supplies the data strobe signal N_DQS to the FIFO circuit513and to the chip MC0via the channel Ch0. In response to the data strobe signal N_DQS, the FIFO circuit513can internally shift the data signal N_DQ between the plurality of queue entries, and transfer the data signal N_DQ to the chip MC0via the channel Ch0.

Further, when it is determined based on the count value of the counter circuit514that the FIFO circuit513is empty, the control circuit516stops the toggle of the data strobe signal N_DQS. When it is determined based on the count value of the counter circuit514that the FIFO circuit513starts storing the data signal H_DQ again, the control circuit516restarts the toggle of the data strobe signal N_DQS. As a result, the power consumption of the relay chip IF can be reduced.

For example, when the maximum speed of the channel Ch in the semiconductor device1is higher than the maximum speed of the host channel HCh, the relay chip IF may operate as illustrated inFIG.32.FIG.32is a waveform diagram illustrating the operation of the relay chip IF.

At timing t91, the data strobe signal H_DQS starts to be toggled, and the counter circuit514starts counting the number of toggles of the data strobe signal H_DQS. The relay chip IF receives the data signal H_DQ for the chip MC0via the host channel HCh according to the edge of the data strobe signal H_DQS and stores the data signal in the FIFO circuit513.

At timing t92, the control circuit516starts toggling the data strobe signal N_DQS, supplies the data strobe signal N_DQS to the FIFO circuit513, and supplies the data strobe signal N_DQS to the chip MC0via the channel Ch0.

At timing t93, the control circuit516determines that the FIFO circuit513becomes empty in response to the fact that the number of toggles of the data strobe signal H_DQS becomes equal to the number of toggles of the data strobe signal N_DQS generated by the control circuit516, and stops the toggle of the data strobe signal N_DQS.

At timing t94, the control circuit516determines that the FIFO circuit513starts storing the data signal H_DQ again in response to the fact that the number of toggles of the data strobe signal H_DQS becomes larger than the number of toggles of the data strobe signal N_DQS, and restarts the toggle of the data strobe signal N_DQS.

Thereafter, the same operations as the timings t92to t94are repeated. By this operation, as indicated by a dotted arrow, it may be seen that the data signal H_DQ is transferred as the data signal N_DQ from the host HA to the chip MC0without excess or deficiency.

As described above, in the seventh embodiment, the semiconductor device1can increase the data transfer speed in the semiconductor device1beyond the maximum speed of the host channel HCh.