Semiconductor device and method of manufacturing the same

A semiconductor device includes a first bottom electrode, a second bottom electrode, a switching layer and a top electrode. The first bottom electrode has two edges opposite to each other, and an upper surface. The second bottom electrode is between the edges of the first bottom electrode and exposed from the upper surface of the first bottom electrode. The switching layer is over the first bottom electrode and the second bottom electrode. The top electrode is over the switching layer.

BACKGROUND

Electronic memory may be volatile memory or non-volatile memory. Non-volatile memory is able to store data when power is removed, whereas volatile memory is not. Resistive random access memory (RRAM) is one promising candidate for next generation non-volatile memory technology due to its simple structure and its compatibility with complementary metal-oxide-semiconductor (CMOS) logic fabrication processes. The RRAM, however, still suffers from narrow switching window and leakage issues.

DETAILED DESCRIPTION

In some embodiments, a semiconductor device such as a resistive random access memory (RRAM) or a conductive bridging random access memory (CBRAM) includes a bottom electrode, a top electrode and a switching layer interposed therebetween. The bottom electrode includes a first bottom electrode with a lower work function and/or lower conductivity, and a higher work function and/or higher conductivity. The first bottom electrode is aligned with edges of the switching layer, and the second bottom electrode is aligned with center of the switching layer. The second bottom electrode is configured to concentrate the electrical field at the center of the switching layer when a voltage is applied across the top electrode and the bottom electrode. The electric field concentrated at the center of the switching layer makes it easy to form the conductive filament(s) near the center of the switching layer away from the edge. Accordingly, the switching window can be increased after cycling and baking, and the forming voltage can be reduced.

FIG. 1is a flow chart illustrating a method for manufacturing a semiconductor device according to various aspects of one or more embodiments of the present disclosure. The method100begins with operation110in which a first bottom electrode and a second bottom electrode are formed over a substrate. The second bottom electrode is between two edges of the first bottom electrode and exposed from an upper surface of the first bottom electrode. The method100continues with operation120in which a switching layer is formed over the first bottom electrode and the second bottom electrode. The method100proceeds with operation130in which a top electrode is formed over the switching layer.

The method100is merely an example, and is not intended to limit the present disclosure beyond what is explicitly recited in the claims. Additional operations can be provided before, during, and after the method100, and some operations described can be replaced, eliminated, or moved around for additional embodiments of the method.

FIG. 2A,FIG. 2B,FIG. 2C,FIG. 2D,FIG. 2E,FIG. 2FandFIG. 2Gare schematic views at one of various operations of manufacturing a semiconductor device according to one or more embodiments of the present disclosure. As depicted inFIG. 2A, a substrate10is received. In some embodiments, the substrate10includes a semiconductor substrate. By way of example, the material of the substrate10may include elementary semiconductor such as silicon or germanium; a compound semiconductor such as silicon germanium, silicon carbide, gallium arsenic, gallium phosphide, indium phosphide or indium arsenide; or combinations thereof.

In some embodiments, a bottom interconnect structure12is formed over the substrate10. In some embodiments, the bottom interconnect structure12includes a bottom metallization layer121, and a bottom inter-layer dielectric (ILD) layer122laterally surrounding the bottom metallization layer121. In some embodiments, the bottom metallization layer121may be one layer of the back-end-of-the line (BEOL). In some embodiments, the material of the bottom metallization layer121may include metal or alloy such as copper, tungsten, alloy thereof or the like. The material of the bottom ILD layer122may include dielectric material such as low-k dielectric material with a dielectric constant less than 2.0 or the like, but is not limited thereto.

As depicted inFIG. 2B, a dielectric layer14is formed over the substrate10. In some embodiments, the dielectric layer14is formed over the bottom interconnect structure12and includes a gap14G exposing the bottom metallization layer121. In some embodiments, the material of the dielectric layer14may include dielectric material such as silicon oxide, silicon nitride, silicon oxynitride or the like. In some embodiments, a first conductive layer16is formed over the dielectric layer14and covering the gap14H. In some embodiments, a recess16R recessed from a portion of an upper surface16U of the first conductive layer16is formed due to the profile of the gap14H when the first conductive layer16is formed over the dielectric layer14. In some embodiments, a second conductive layer18is formed over the first conductive layer16and filled in the recess16R. In some embodiments, a work function of the second conductive layer18is higher than a work function of the first conductive layer16. For example, a work function difference between the second conductive layer18and the first conductive layer16is substantially greater than 0.3 eV. In some embodiments, a conductivity of the second conductive layer18is higher than a conductivity of the first conductive layer16. For example, a conductivity ratio of the second conductive layer18to the first conductive layer16is substantially greater than 2. In some embodiments, the materials for the first conductive layer16and the second conductive layer18may include conductive materials with different ingredients, or conductive materials with a same ingredient and with different ingredient ratios as long as the work function of the second conductive layer18is higher than the work function of the first conductive layer16and/or the conductivity of the second conductive layer18is higher than the conductivity of the first conductive layer16. In some embodiments, the material of the first conductive layer16may include a first metal, and the material of the second conductive layer18may include a second metal which has higher work function and conductivity than the first metal of the first conductive layer16. In some embodiments, the material of the first conductive layer16may include a metal, and the material of the second conductive layer18may include a metal compound which has higher work function and conductivity than the metal of the first conductive layer16. In some embodiments, the material of the first conductive layer16may include a metal compound, and the material of the second conductive layer18may include a metal which has higher work function and conductivity than the metal compound of the first conductive layer16. In some embodiments, the material of the first conductive layer16may include a first metal compound, and the material of the second conductive layer18may include a second metal compound which has higher work function and conductivity than the first metal compound of the first conductive layer16. In some embodiments, the first metal compound and the second metal compound include the same ingredient such as titanium nitride but have different nitrogen concentrations. By way of example, the first metal compound may include titanium nitride or tantalum nitride with higher nitrogen concentration, while the second metal compound may include titanium nitride or tantalum nitride with lower nitrogen concentration.

Examples of materials for the first conductive layer16and the second conductive layer18are listed in Table 1.

As depicted inFIG. 2C, a portion of the second conductive layer18is removed to form a second bottom electrode20. In some embodiments, the portion of the second conductive layer18outside the recess16R is removed such that the second conductive layer18remaining in the recess16R forms the second bottom electrode20. In some embodiments, the portion of the second conductive layer18outside the recess16R is removed by a planarization operation such as chemical mechanical polishing (CMP). In some embodiments, an upper surface20U of the second bottom electrode20and the upper surface16U of the first conductive layer16are substantially coplanar.

As depicted inFIG. 2D, a switching layer22is formed over the first conductive layer16. In some embodiments, the switching layer22is configured to have a variable resistance depending on different electric fields are applied. In some embodiments, the switching layer22is, but not limited to be, a high-k dielectric having a dielectric constant greater than 3.9. In some embodiments, the material of the switching layer22includes, but is not limited to, metal oxide such as hafnium oxide, tantalum oxide, aluminum oxide, silicon oxide, hafnium tantalum oxide, hafnium aluminum oxide, aluminum tantalum oxide or the like. In some embodiments, the material of the switching layer22includes, but is not limited to, semiconductive material such as amorphous silicon, germanium selenide, germanium telluride or the like. In some embodiments, the first conductive layer16and the second bottom electrode20may be in contact with the switching layer22. In some embodiments, a third conductive layer24is formed over the switching layer22. In some embodiments, the material of the third conductive layer24may include metal or alloy such as copper, tungsten, alloy thereof or the like.

As depicted inFIG. 2E, the third conductive layer24is patterned by, e.g., photolithography and etching technique, to form a top electrode26. In some embodiments, the switching layer22is patterned, and configured as a data storage layer. In some embodiments, the switching layer22may be patterned along with the third conductive layer24, but not limited thereto. In some embodiments, the first conductive layer16is patterned to form a first bottom electrode28. In some embodiments, the first conductive layer16may be patterned along with the switching layer22, but not limited thereto. The first bottom electrode28has two edges28E opposite to each other, and an upper surface28U. In some embodiments, the upper surface28U of the first bottom electrode28and the upper surface20U of the second bottom electrode20are substantially coplanar. In some embodiments, the second bottom electrode20is between the edges28E of the first bottom electrode28and exposed from the upper surface28U of the first bottom electrode28.

As depicted inFIG. 2F, a passivation layer30can be optionally formed. In some embodiments, the passivation layer30is insulative. In some embodiments, the passivation layer30covers the top electrode26. In some embodiments, the passivation layer30covers the switching layer22. In some embodiments, the material of the passivation layer30includes dielectric material such as silicon oxide, silicon nitride, silicon oxynitride or the like, but is not limited thereto. In some embodiments, a top inter-layer dielectric (ILD) layer322is formed over the substrate10, covering the passivation layer30. In some embodiments, the material of the top ILD layer322may include dielectric material such as low-k dielectric material with a dielectric constant less than 2.0 or the like, but is not limited thereto.

As depicted inFIG. 2G, the top ILD layer322and the passivation layer30may be patterned by, e.g., photolithography and etching technique, to expose a portion of the top electrode26. In some embodiments, a top metallization layer321is formed, and electrically connected to the top electrode26to form a semiconductor device1. In some embodiments, the material of the top metallization layer321may include metal or alloy such as copper, tungsten, alloy thereof or the like. In some embodiments, the top metallization layer321and the top ILD layer322form a top interconnect structure32.

FIG. 3is a schematic cross-sectional view of a semiconductor device according to one or more embodiments of the present disclosure. As shown inFIG. 3, the semiconductor device1includes a bottom electrode including a first bottom electrode28and a second bottom electrode20laterally surrounded by the first bottom electrode28. In some embodiments, the second bottom electrode20is partially embedded in the first bottom electrode28, and exposed from the upper surface28U of the first bottom electrode28. In some embodiments, a bottom surface20B and at least two edges20E of the second bottom electrode20are surrounded by the first bottom electrode28. In some embodiments, the first bottom electrode28and the second bottom electrode20are in contact with the switching layer22. In some embodiments, an intervening layer may be interposed between the switching layer22and the first and second bottom electrodes28,20.

The second bottom electrode20has a higher work function than the first bottom electrode28. In some embodiments, the work function difference between the second bottom electrode20and the first bottom electrode28is, but not limited to be, substantially greater than 0.3 eV. The second bottom electrode20has a higher conductivity (i.e. lower resistivity) than the first bottom electrode28. In some embodiments, the conductivity ratio of the second bottom electrode20to the first bottom electrode28is, but not limited to be, substantially greater than 2, i.e., the resistivity ratio of the second bottom electrode20to the first bottom electrode28is, but not limited to be, substantially less than ½.

In some embodiments, the semiconductor device1may be memory device such as a resistive random access memory (RRAM), a conductive bridging random access memory (CBRAM) or the like. In operation and during manufacture, voltages may be applied between the top electrode26and the first and second bottom electrode28,20. For example, a voltage may be applied between the top electrode26and the first and second bottom electrodes28,20to form the one or more conductive filaments34and/or to trigger reactions in the switching layer22. As another example, a voltage may be applied between the top electrode26and the first and second bottom electrodes28,20to read, set or erase the semiconductor device1. In some embodiments, the switching layer22includes a data storage region having a variable resistance representing a unit of data, such as a bit of data. The variable resistance is configured to vary in response to external electric fields generated by the top electrode26and the first and second bottom electrodes28,20. The variable resistance varies between comparatively low and high resistance states depending upon whether one or more conductive filaments34are fully or partially formed in switching layer22. For example, the variable resistance is in a low resistance state when the one or more conductive filaments34are fully formed, and the variable resistance is in a comparatively high resistance state when the one or more conductive filaments34are partially formed.

The work function of the second bottom electrode20is higher than the work function of the first bottom electrode28, and thus the second bottom electrode20gets more negative than the first bottom electrode28when a negative voltage is applied to the bottom electrode. Consequently, the higher work function of the second bottom electrode20aligned near the center of the switching layer22makes the electrical field36near the central region higher than the electrical field36at the edge of the switching layer22. Accordingly, the conductive filament34is apt to form near the center than the edge of the switching layer22. Since the interaction of the conductive filament34and the edge of the switching layer22may cause leakage and tailing and reliability issue, the conductive filament34located away from the edge of the switching layer22is able to reduce tailing bits during cycling (endurance test) or baking (retention test).FIG. 4is a schematic diagram illustrating a variance of switching window of a semiconductor device with and without a second bottom electrode with higher work function and higher conductivity incorporated in a first bottom electrode with lower work function and lower conductivity according to one or more embodiments of the present disclosure. As shown inFIG. 4, with the second bottom electrode with higher work function and higher conductivity, the switching window SW is increased by a current gain. Also, the forming voltage can be decreased since the electric field is concentrated at the center of the switching layer22with the second bottom electrode20having high work function and high conductivity located near the center of the switching layer22.

In one exemplary aspect, a semiconductor device includes a first bottom electrode, a second bottom electrode, a switching layer and a top electrode. The first bottom electrode has two edges opposite to each other, and an upper surface. The second bottom electrode is between the edges of the first bottom electrode and exposed from the upper surface of the first bottom electrode. The switching layer is over the first bottom electrode and the second bottom electrode. The top electrode is over the switching layer.

In another aspect, a semiconductor device includes a first bottom electrode, a second bottom electrode, a switching layer and a top electrode. The second bottom electrode is at least partially embedded in the first bottom electrode, wherein a work function of the second bottom electrode is higher than a work function of the first bottom electrode, and a conductivity of the second bottom electrode is higher than a conductivity of the first bottom electrode. The switching layer is over the first bottom electrode and the second bottom electrode. The top electrode is over the switching layer.

In yet another aspect, a method for manufacturing a semiconductor device is provided. A first bottom electrode and a second bottom electrode are formed over a substrate, wherein the second bottom electrode is between two edges of the first bottom electrode and exposed from an upper surface of the first bottom electrode. A switching layer is formed over the first bottom electrode and the second bottom electrode. A top electrode is formed over the switching layer.