Superconducting circuit multi-chip synchronization system

One example includes a superconducting circuit chip. The chip includes superconducting circuitry that operates based on a clock signal. The chip also includes a ring oscillator configured to receive a synchronization signal from a ring oscillator associated with another superconducting circuit chip. The ring oscillator is also configured to provide a trigger signal to the superconducting circuitry at a given phase of the clock signal relative to a phase of the clock signal of a trigger signal associated with the other one of the superconducting circuit chips based on the synchronization signal.

TECHNICAL FIELD

The present invention relates generally to computer systems, and specifically to a superconducting circuit multi-chip synchronization system.

BACKGROUND

Modern computer systems implement many different circuits that reside on different chips across one or more circuit boards. A clock signal is typically provided to the different chips to provide timing for operations of the circuit. Multi-chip computer systems are typically designed to operate and communicate with each other, such that synchronization of the timing of the chips, such as via the clock signal(s), allows operations of the computer system to be implemented quickly and efficiently. The synchronization of the timing of the chips can be such that operations can be performed on the same clock cycle or within a known number of clock cycles of operations provided from other chips. Such synchronization can become challenging as clock speeds increase in frequency. As an example, superconducting computer systems can implement very high speed pulses and high frequency clock signals, but it is still desirable to implement synchronization of different superconducting circuit chips.

SUMMARY

One example includes a superconducting circuit chip. The chip includes superconducting circuitry that operates based on a clock signal. The chip also includes a ring oscillator configured to receive a synchronization signal from a ring oscillator associated with another superconducting circuit chip. The ring oscillator is also configured to provide a trigger signal to the superconducting circuitry at a given phase of the clock signal relative to a phase of the clock signal of a trigger signal associated with the other one of the superconducting circuit chips based on the synchronization signal.

Another example includes a method for synchronizing a plurality of superconducting circuit chips to a clock signal. The method includes providing an initialization signal to a first ring oscillator associated with a first superconducting circuit chip comprising first superconducting circuitry that operates based on the clock signal. The method also includes generating a first trigger signal to the first superconducting circuitry at a first phase of the clock signal via the first ring oscillator. The method also includes providing a synchronization signal from the first ring oscillator to a second ring oscillator associated with a second superconducting circuit chip comprising second superconducting circuitry that operates based on the clock signal. The method further includes providing a second trigger signal to the second superconducting circuitry at the first phase of the clock signal via the second ring oscillator based on the synchronization signal.

Another example includes a superconducting circuit synchronization system. The system includes a first superconducting circuit chip comprising first superconducting circuitry that operates based on a clock signal and a first ring oscillator. The first ring oscillator can be configured to provide a synchronization signal and a first trigger signal. The first trigger signal can be provided to the first superconducting circuitry at a given phase of the clock signal. The system also includes a second superconducting circuit chip comprising second superconducting circuitry that operates based on the clock signal and a second ring oscillator. The second ring oscillator can be configured to receive the synchronization signal and to provide a second trigger signal. The second trigger signal can be provided to the second superconducting circuitry at the given phase of the clock signal based on the synchronization signal. The system further includes a synchronization controller configured to provide an initialization signal to the first ring oscillator of the first the superconducting circuit chip to activate the first ring oscillator.

DETAILED DESCRIPTION

The present invention relates generally to computer systems, and specifically to a superconducting circuit multi-chip synchronization system. A superconducting circuit system can include a plurality of superconducting circuit chips that each include superconducting circuitry configured to implement a circuit function based on a clock signal. As an example, the superconducting circuit system can be configured as a reciprocal quantum logic (RQL) system, such that the clock signal can be an RQL quadrature clock that operates at each of 90° increments. Each of the superconducting circuit chips can also include a ring oscillator that is implemented for synchronization of the superconducting circuit system. As an example, the ring oscillator of each of the superconducting circuit chips can include a plurality of Josephson transmission line (JTL) segments that are arranged in a loop to propagate a fluxon (e.g., an RQL pulse that includes a fluxon and an anti-fluxon) about the loop.

As an example, the superconducting circuit chips can be interconnected via passive transmission lines (PTLs) that propagate synchronization signals between the ring oscillators of the respective superconducting circuit chips. Therefore, the ring oscillator of a given superconducting circuit chip can be configured to receive a first synchronization signal from the ring oscillator of a first other superconducting circuit chip, and can transmit a second synchronization signal to the ring oscillator of a second other superconducting circuit chip. The synchronization signals can be provided to and can initialize a given ring oscillator at a known phase of the clock signal, thereby providing a relative propagation of the fluxon in each of the ring oscillators at a relative phase relationship in each of the superconducting circuit chips. The synchronization signals can propagate on the PTLs based on a known phase relationship with respect to the clock signal, and can be both transmitted from and received at the respective ring oscillators at known phases of the clock signal.

Each of the ring oscillators is also configured to provide a trigger signal to the superconducting circuitry of the respective superconducting circuit chip. Based on the arrangement of the ring oscillator (e.g., based on the arrangement of the JTL segments in the ring oscillator), the trigger signal can be provided at a known phase relationship with respect to the received synchronization signal. Therefore, based on a phase relationship between when a given synchronization signal is generated from a first ring oscillator and is received at a second ring oscillator, the first and second ring oscillators can provide the respective trigger signals at a known phase relationship with respect to each other. For example, the trigger signals can be provided at the same phase of the clock signal, such as concurrently. Accordingly, the trigger signals can provide synchronized circuit functions of the superconducting circuitry.

FIG.1illustrates an example block diagram of a superconducting circuit system100. The superconducting circuit system100can be implemented in any of a variety of computing applications, such as including both superconducting and classical computing environments. The superconducting circuit system100includes a plurality N of superconducting circuit chips102, where N is a positive integer. Each of the superconducting circuit chips102includes superconducting circuitry (“CIRCUITRY”)104that is configured to perform a computer function based on a clock signal, demonstrated in the example ofFIG.1as a clock signal CLK. As an example, the superconducting circuit system100can be configured as a reciprocal quantum logic (RQL) system, such that the clock signal CLK can be an RQL quadrature clock that operates at each of 90° increments, or in increments therebetween (e.g., 45°). In the example ofFIG.1, the clock signal CLK is thus demonstrated as being provided to each of the superconducting circuit chips102.

Each of the superconducting circuit chips102also includes a ring oscillator106. The ring oscillator106of each of the superconducting circuit chips102can be arranged similarly with respect to each other to provide a respective timing reference for each of the superconducting circuit chips102based on the clock signal CLK. As an example, the ring oscillators106can each include a plurality of Josephson transmission line (JTL) segments arranged in a loop, such that the JTL segments can propagate a fluxon about the loop based on the clock signal CLK. For example, the JTL segments can propagate an RQL fluxon and a corresponding RQL anti-fluxon about the loop based on the clock signal. In the example ofFIG.1, the ring oscillator106of each of the superconducting circuit chips102is configured to provide a trigger signal, demonstrated as trigger signals TRG1through TRGN, to the superconducting circuitry104of the respective one of the superconducting circuit chips102. As described herein, the trigger signals TRG1through TRGNcan be provided in a manner that is synchronized to known phases of the clock signal CLK. As an example, the trigger signals TRG1through TRGNcan be synchronized to a same phase of the clock signal CLK, such as provided concurrently.

The superconducting circuit system100also includes a synchronization controller108that is configured to initiate synchronization of the superconducting circuit chips102, as described herein. As an example, the synchronization controller108can be provided in a room-temperature environment while the superconducting circuit chips102can be provided in a cryogenic superconducting environment (e.g., less than 10 Kelvin). The synchronization controller108is configured to provide an initialization signal INIT to the ring oscillator106of the first superconducting circuit chip (“SUPERCONDUCTING CIRCUIT CHIP1”)102. The initialization signal INIT is thus configured to activate the ring oscillator106to generate the fluxon that propagates about the loop formed by the ring oscillator106. In the example ofFIG.1, the ring oscillators106are configured to provide synchronization signals SYNC to ring oscillators106of other superconducting circuit chips102in a sequence. The synchronization signals SYNC are demonstrated as a first synchronization signal SYNC1provided from the ring oscillator106of the first superconducting circuit chip102to the ring oscillator106of the second superconducting circuit chip (“SUPERCONDUCTING CIRCUIT CHIP2”)102, a second synchronization signal SYNC2provided from the ring oscillator106of the second superconducting circuit chip102to the ring oscillator106of a third superconducting circuit chip102, to a last synchronization signal SYNCN-1provided from the ring oscillator106of the N−1 superconducting circuit chip102to the Nth superconducting circuit chip (“SUPERCONDUCTING CIRCUIT CHIP N”)102. Similar to the initialization signal INIT, each of the synchronization signals SYNC is configured to activate the ring oscillator106to which it is sent to generate the fluxon that propagates about the loop formed by the respective ring oscillator106.

In addition to activating the ring oscillator106of the superconducting circuit chip102to which it is sent, each of the synchronization signals SYNC can provide a timing reference for the ring oscillator106to which it is sent relative to the ring oscillator106from which it is sent based on the clock signal CLK. As an example, a synchronization signal SYNC can be provided from a ring oscillator106of a superconducting circuit chip102at a given phase of the clock signal CLK, and can be received by the ring oscillator106of the next superconducting circuit chip102in the sequence at another given phase (e.g., the same or different) of the clock signal CLK. As another example, the synchronization signals SYNC can be sent on passive transmission lines (PTLs) that have respective lengths that can be associated with the phases of the clock signal CLK. Therefore, the length of the PTLs can be determinative of the phase of the clock signal CLK at which the synchronization signal SYNC is received at the ring oscillator106of a superconducting circuit chip102. Accordingly, the timing relationship of each of the ring oscillators106can be determined relative to each other. As a result, the trigger signals TRG1through TRGNcan be synchronized with respect to timing of the phases of the clock signal CLK. As a result, the trigger signals TRG1through TRGNcan be provided at known phase timing of the clock signal CLK with respect to each other, such as concurrently.

In the example ofFIG.1, the synchronization controller108is further configured to provide a reset signal RST to the ring oscillator106of each of the superconducting circuit chips102. The reset signal RST can be configured to deactivate the ring oscillators106of the respective superconducting circuit chips102. As an example, the reset signal RST can be provided during a reset of the superconducting circuit system100, such as to troubleshoot or clear fault situations. The superconducting circuit system100can thus subsequently be restarted, and the initialization signal INIT can be provided to re-establish synchronization of the superconducting circuit chips102.

Based on the operation of the ring oscillators106and the a priori known relative timing relationship between the ring oscillators106in response to the synchronization signals SYNC, the trigger signals TRG1and TRGNcan be implemented by the superconducting circuitry104to provide the circuit functions in a manner that can be synchronized across the superconducting circuit chips102. Accordingly, the superconducting circuit system100can operate efficiently and effectively across the superconducting circuit chips in a synchronized manner, even at the high computational speeds of a superconducting environment.

FIG.2illustrates an example diagram of a ring oscillator200. The ring oscillator200can correspond to the ring oscillator106of one or more of the superconducting circuit chips102in the example ofFIG.1. Therefore, reference is to be made to the example ofFIG.1in the following description of the example ofFIG.2. In the example ofFIG.2, the ring oscillator200can be the ring oscillator106of the Xth superconducting circuit chip102, which can correspond to any one of the N superconducting circuit chips102in the example ofFIG.1.

The ring oscillator200is composed primarily of JTL segments202that are arranged in a loop. In the example ofFIG.2, each of the JTL segments202can be biased by a given phase of the clock signal CLK (not shown). For example, each JTL segment202can be biased by a phase of the clock signal CLK that is 90° subsequent to the phase of the clock signal CLK that biased the immediately preceding JTL segment202. Therefore, a fluxon (e.g., an RQL fluxon and subsequent RQL anti-fluxon) can propagate about the loop via the JTL segments202at each of subsequent phases of the clock signal CLK.

The ring oscillator200includes a superconducting receiver204that is configured to receive the synchronization signal SYNCX-1that is provided from the ring oscillator106of the immediately preceding superconducting circuit chip102(e.g., the X−1 superconducting circuit chip102) of the sequence. For example, the synchronization signal SYNCX-1can be provided from a PTL that interconnects the ring oscillator106of the X−1 superconducting circuit chip102and the ring oscillator200. The superconducting receiver204can thus provide data capture (e.g., sample) the synchronization signal SYNCX-1from the PTL to generate a fluxon, demonstrated as a signal FLX, at a specific phase of the clock signal CLK. As an example, the specific phase of the clock signal CLK can be relative to both a specific known phase of transmission of the synchronization signal SYNCX-1and a length of the PTL with respect to the phases of the clock signal CLK. For example, the PTL on which the synchronization signal SYNCX-1propagates can have a known length for which a time of propagation of the synchronization signal SYNCX-1can likewise be known. Therefore, the propagation of the synchronization signal SYNCX-1can be related to the phases of the clock signal CLK, such that the phase of the clock signal CLK at which the superconducting receiver204receives the synchronization signal SYNCX-1can be the same or subsequent to the phase at which the synchronization signal SYNCX-1is generated from the ring oscillator106of the preceding superconducting circuit chip102, as based on the length of the PTL.

The fluxon FLX generated by the superconducting receiver204can be provided as an input to an OR-gate206. The OR-gate206therefore provides the fluxon FLX as an output (e.g., propagates the fluxon FLX) to a first JTL segment, demonstrated at208, of the JTL segments202. Therefore, in response to receiving the synchronization signal SYNCX-1, the ring oscillator200can be activated. Thus, in response to the fluxon being introduced into the loop of JTL segments202, the fluxon FLX can continue to propagate through the JTL segments202around the loop indefinitely, thereby providing a timing reference for the associated superconducting circuit chip102in which the ring oscillator200is included.

In addition, in the example ofFIG.2, the JTL segments202include a second JTL segment, demonstrated at210, that is configured to provide the trigger signal TRGX. As described above in the example ofFIG.1, the trigger signal TRGXcan be provided to the superconducting circuitry104to facilitate circuit functions. The second JTL segment210can have a known phase relationship with respect to the first JTL segment208. Additionally, as described above, the superconducting receiver204has a known phase relationship with the ring oscillator106of the preceding superconducting circuit chip102from which the synchronization signal SYNCX-1is provided. Therefore, because the first JTL segment208has a known phase relationship with the superconducting receiver204, and because the superconducting receiver204has a known phase relationship with the ring oscillator106of the preceding superconducting circuit chip102, then the trigger signal TRGXcan have a known phase relationship with a trigger signal TRGX-1that is generated by the ring oscillator106of the preceding superconducting circuit chip102. For example, based on the arrangement of the JTL segments202in the ring oscillator200and the arrangement of the JTL segments in the ring oscillator106in the preceding superconducting circuit chip102, the trigger signal TRGXcan be provided concurrently with the trigger signal TRGX-1that is generated by the ring oscillator106of the preceding superconducting circuit chip102. Accordingly, the trigger signal TRGX-1and the trigger signal TRGXcan be synchronized to synchronize circuit functions of the superconducting circuitry104of the respective superconducting circuit chips102, as described herein.

The ring oscillator200includes a superconducting driver212that is configured to generate a synchronization signal SYNCXbased on the fluxon FLX. The synchronization signal SYNCXcan thus be provided on a PTL from the ring oscillator200to the next superconducting circuit chip102(e.g., the X+1 superconducting circuit chip102) of the sequence. For example, the synchronization signal SYNCXcan be provided on a PTL that interconnects the ring oscillator200to the ring oscillator106of the X+1 superconducting circuit chip102. The superconducting receiver204can thus convert the fluxon FLX to a high voltage signal corresponding to the synchronization signal SYNCXthat is provided on the PTL at a specific phase of the clock signal CLK. The synchronization signal SYNCXcan thus be received by a superconducting receiver of the ring oscillator106of the X+1 superconducting circuit chip102, such as similar to the superconducting receiver204described above.

As an example, the specific phase of the clock signal CLK can be relative to a specific known phase of the trigger signal TRGX. Therefore, similar to as described above, transmission of the synchronization signal SYNCXand a length of the PTL with respect to the phases of the clock signal CLK can be related to the phase of the clock signal CLK on which the synchronization signal SYNCXcan be received by the superconducting receiver of the ring oscillator106of the next superconducting circuit chip102. Therefore, the propagation of the synchronization signal SYNCXcan be related to the phases of the clock signal CLK on which a trigger signal TRGX-1can be generated by the ring oscillator106of the next superconducting circuit chip102. As a result, similar to as described above, the trigger signal TRGXand the trigger signal TRGX-1can be synchronized to synchronize circuit functions of the superconducting circuitry104of the respective superconducting circuit chips102, as described herein. The synchronization of the trigger signals TRG can thus be provided in a similar manner for all of the superconducting circuit chips102of the superconducting circuit system100, as described herein.

In the example ofFIG.2, the ring oscillator200is demonstrated as receiving the initialization signal INIT. For example, the ring oscillator200can be configured as the ring oscillator106of the first superconducting circuit chip102(e.g., X=1). In this example, the initialization signal INIT can be provided to the ring oscillator200as an alternative of including the superconducting receiver204. Therefore, the superconducting receiver204may be obviated in the first superconducting circuit chip102, and the initialization signal INIT may be obviated in the rest of the superconducting circuit chips102. The initialization signal INIT can thus provide an alternative of activation of the ring oscillator200.

The initialization signal INIT is provided as an input to an OR-gate214. The OR-gate214therefore provides the fluxon FLX as an output to the JTL segments202. Therefore, in response to receiving the initialization signal INIT, the ring oscillator200can be activated. Thus, in response to the fluxon being introduced into the loop of JTL segments202, the fluxon FLX can continue to propagate through the JTL segments202around the loop indefinitely, thereby providing a timing reference for the associated superconducting circuit chip102in which the ring oscillator200is included, similar to as described above.

The ring oscillator200is demonstrated as receiving the reset signal RST, as well. The reset signal RST is provided to an inverting input of an AND-gate216. Therefore, in response to receiving the reset signal RST, the AND-gate216does not propagate the fluxon FLX, which can cease the indefinite propagation of the fluxon FLX about the loop of JTL segments202. Accordingly, the reset signal RST can be implemented to deactivate the ring oscillator200, similar to as described above. The ring oscillator200can be reactivated in response to receiving the synchronization signal SYNCX-1or the initialization signal INIT, as described above.

In view of the foregoing structural and functional features described above, a methodology in accordance with various aspects of the disclosure will be better appreciated with reference toFIG.3. It is to be understood and appreciated that the method ofFIG.3is not limited by the illustrated order, as some aspects could, in accordance with the present disclosure, occur in different orders and/or concurrently with other aspects from that shown and described herein. Moreover, not all illustrated features may be required to implement a methodology in accordance with an aspect of the present examples.

FIG.3illustrates an example of a method300for synchronizing a plurality of superconducting circuit chips (e.g., the superconducting circuit chips102) to a clock signal (e.g., the clock signal CLK). At302, an initialization signal (e.g., the initialization signal INIT) is provided to a first ring oscillator (e.g., a ring oscillator106) associated with a first superconducting circuit chip comprising first superconducting circuitry (e.g., the superconducting circuitry104) that operates based on the clock signal. At304, a first trigger signal (e.g., the trigger signal TRG1) is provided to the first superconducting circuitry at a first phase of the clock signal via the first ring oscillator. At306, a synchronization signal (e.g., the synchronization signal SYNC1) is provided from the first ring oscillator to a second ring oscillator associated with a second superconducting circuit chip comprising second superconducting circuitry that operates based on the clock signal. At308, a second trigger signal (e.g., the trigger signal TRG2) is provided to the second superconducting circuitry at the first phase of the clock signal via the second ring oscillator based on the synchronization signal.