POWER SEMICONDUCTOR DEVICE AND POWER CONVERTER

A power semiconductor is disclosed and for high-voltage and high-power operation. An example power semiconductor comprises: a substrate; a drift layer formed in the substrate including an active area having doped regions and a termination area configured to surround the active area; and a junction termination extension (JTE) in the termination area. In some aspects, the substrate and the drift layer comprise a first conductivity type, the doped regions and the JTE comprise a second conductivity type, the JTE comprises at least one blocking region adjacent to an edge of the active area and a plurality of separation regions, each separation region of the plurality of separation regions comprises two or more separation sub-regions, and the two or more separation sub-regions are configured to have a different dopant concentrations

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims the benefits of priority to Korean Patent Application No. 10-2023-0108439, filed on Aug. 18, 2023, all of which are incorporated herein by reference in their entireties.

BACKGROUND

1. Technical Field

The instant disclosure relates to a power semiconductor device and a power converter.

2. Description of the Related Art

Unlike a system semiconductor or a memory that processes and stores information or signals, a power semiconductor converts, stores, distributes, and controls power entering electronic devices, and is widely used in most electronic products.

In recent years, in line with the global trend of strengthening environmental protection, electric or hydrogen-based eco-friendly vehicles have been widely spotlighted instead of existing fossil fuel-based vehicles. Numerous power semiconductor devices are used in these eco-friendly vehicles. Here, the eco-friendly vehicle includes a hybrid electric vehicle (HEV), a plug-in hybrid vehicle (PHEV), an electric vehicle (EV), a fuel cell electric vehicle (PCEV) or the like.

In the related art, a silicon (Si) power semiconductor device has been widely used, but the development of a new power semiconductor device is needed for low power, low dielectric breakdown characteristics, and low thermal conductivity.

Accordingly, research on a power semiconductor based on a semiconductor compound having an energy band gap that is about three times higher than that of the Si power semiconductor device in the related art has been actively conducted. The power semiconductors based on the semiconductor compound include high power, high dielectric breakdown characteristics, and high thermal conductivity.

Recently, power semiconductors are adopted for ultra-high voltage transmission facilities or electric vehicles, a high breakdown voltage is required. For example, a breakdown voltage of 1,200V or more is required.

To this end, research on the design and layout of a power semiconductor device having a satisfactory breakdown voltage is being actively conducted.

SUMMARY

The instant disclosure is related to addressing the foregoing and other problems.

Another object of the aspect is to provide a power semiconductor device and a power converter having a novel structure.

Another object of the aspect is to provide a power semiconductor device and a power converter capable of withstanding a high breakdown voltage.

Another object of the embodiments is to provide a power semiconductor device and a power converter capable of designing an optimized space without design rule restrictions.

The technical problems of the embodiments are not limited to those described in this section, and include those that may be understood through the description of the disclosure.

According to a first aspect of the aspect to achieve the above or other object, a power semiconductor device, comprising: a substrate comprising an active area and a termination area configured to surround the active area: a drift layer on the substrate: bodies on the drift layer in the active area; and a junction termination extension (JTE) on the drift layer in the termination area, wherein the substrate and the drift layer comprise a first conductivity type dopant, wherein the bodes and the JTE comprise a second conductivity type dopant, wherein the JTE comprises at least one blocking region and a plurality of separation regions located farther from the outermost body than the at least one blocking region, wherein each of the plurality of separation regions comprises two or more sub-regions, and wherein the two or more sub-regions have different doses.

Each of the plurality of separation regions may comprise a first sub-region comprising a first dose; and a second sub-region comprising a second dose, and the first dose may be greater than the second dose.

The first sub-region may be located closer to the outermost body than the second sub-region.

When a plurality of separation intervals are defined by a first separation interval and the remaining separation intervals, the first separation interval may be smaller than each of the remaining separation intervals, the first separation interval may be an interval between a first sub-region of a first separation region closest to the blocking region among the plurality of separation regions and the blocking region, and the remaining spacing intervals may be intervals between the plurality of first sub-regions of the plurality of separation regions.

As the distance from the outermost body increases, the first separation interval and the remaining separation intervals may increase.

The first sub-region and the second sub-region may have different thicknesses.

The upper side of the first sub-region and the upper side of the second sub-region may be located at the same horizontal line, and the lower side of the second sub-region may be located lower than the lower side of the first sub-region.

Each of the plurality of separation regions may comprise an overlapping region comprising a part of the first sub-region and a part of the second sub-region.

The lower side of the second sub-region may be located below the overlapping region.

A first dose of the first sub-region or a second dose of the second sub-region may be equal to the dose of the body.

According to a second aspect of the aspect to achieve the above or other object, a power semiconductor device, comprising: a substrate comprising an active area and a termination area configured to surround the active area: a drift layer on the substrate; bodies on the drift layer in the active area; and a JTE on the drift layer in the termination area, wherein the substrate and the drift layer comprise a first conductivity type dopant, wherein the body and the JTE comprise a second conductivity type dopant, wherein the JTE comprises at least one blocking region and a plurality of separation regions, wherein the at least one blocking region is in contact with the side portion of the outermost body, wherein the plurality of separation regions are disposed along a lateral direction of the at least one blocking region, wherein each of the plurality of separation regions comprises: a first sub region having a first dose; and a second sub-region having a second dose, wherein the first dose is greater than the second dose.

When a plurality of separation intervals are defined by a first separation interval and the remaining separation intervals, the first separation interval may be smaller than each of the remaining separation intervals, the first separation interval may be an interval between a first sub-region of a first separation region closest to the blocking region among the plurality of separation regions and the blocking region, and the remaining spacing intervals may be intervals between the plurality of first sub-regions of the plurality of separation regions.

As the distance from the outermost body increases, the first separation interval and the remaining separation intervals may increase.

The first sub-region and the second sub-region may have different thicknesses.

The upper side of the first sub-region and the upper side of the second sub-region may be located at the same horizontal line, and the lower side of the second sub-region may be located lower than the lower side of the first sub-region.

Each of the plurality of separation regions may comprise an overlapping region comprising a part of the first sub-region and a part of the second sub-region.

The lower side of the second sub-region may be located below the overlapping region.

A first dose of the first sub-region or a second dose of the second sub-region may be equal to the dose of the body.

The at least one blocking region and the plurality of separation regions may have a ring shape.

According to a third aspect of the embodiments to achieve the above or other object, a power converter, comprising: a plurality of power semiconductor modules, wherein each of the plurality of power semiconductor modules comprises a plurality of power semiconductor devices, wherein each of the plurality of power semiconductor devices comprises: a substrate comprising an active area and a termination area configured to surround the active area: a drift layer on the substrate: bodies on the drift layer in the active area; and a JTE on the drift layer in the termination area, wherein the substrate and the drift layer comprise a first conductivity type dopant, wherein the bodes and the JTE comprise a second conductivity type dopant, wherein the JTE comprises at least one blocking region and a plurality of separation regions located farther from the outermost body than the at least one blocking region, wherein each of the plurality of separation regions comprises two or more sub-regions, and wherein the two or more sub-regions have different doses.

Effects of the power semiconductor device and the power converter according to the aspect will be described below.

As shown inFIGS.7and8, the power semiconductor device according to the aspect may comprise a termination area207disposed on a side portion214aof a body located at the outermost part of an active area206(hereinafter, the outermost body214-3). The termination area207comprises a blocking region221in contact with the outermost body214-3and a plurality of separation regions222-1to222-ndisposed along a lateral direction of the blocking region221.

The plurality of separation regions222-1to222-nmay comprise two or more sub-regions. For example, a plurality of first sub-regions222-1ato222-naof the plurality of separation regions222-1to222-nmay be located closer to the outermost body214-3than a plurality of second sub-regions222-1bto222-nb.

Since a plurality of separation intervals d21to d23are minimized by the first sub-regions222-1ato222-na, an optimized space may be designed without design rule restrictions. The second sub-regions222-1bto222-nbmay appropriately disperse the electric field. Accordingly, according to the aspect, an optimized space may be designed without design rule restrictions through the first sub-regions222-1ato222-na, and the desired withstanding voltage may be achieved through the second sub-regions222-1bto222-nb.

For example, the first sub-regions222-1ato222-naof the first separation region222-1adjacent to the outermost body214-3may be formed with a first separation interval d21of 1 micrometer or less from the outermost body214-3. In addition, the plurality of first sub-regions222-1ato222-naof the plurality of separation regions222-1to222-nmay be formed such that the remaining separation intervals d22and d23are also set very narrow. Therefore, it is possible to design an optimized space without design rule restrictions.

For example, since each of the plurality of separation regions222-1to222-nmay comprise the second sub-region222-1bto222-nbhaving a second dose smaller than a first dose of the first sub-regions222-1ato222-na, even a very large electric field may be appropriately dispersed by the second sub-regions222-1bto222-nbof the plurality of separation regions222-1to222-n, respectively. Thus, a further increased withstanding voltage may be secured

A further scope of applicability of the aspect will become apparent from the detailed description that follows. However, since various changes and modifications within the spirit and scope of the aspect may be clearly understood by those skilled in the art, it should be understood that the detailed description and specific aspect, such as preferred aspect, are given by way of example only.

DETAILED DESCRIPTION

Hereinafter, the aspect disclosed in this specification will be described in detail with reference to the accompanying drawings, but the same or similar elements are given the same reference numerals regardless of reference numerals, and redundant descriptions thereof will be omitted. The suffixes “module” and “unit” for the elements used in the following descriptions are given or used interchangeably in consideration of ease of writing the specification, and do not themselves have a meaning or role that is distinct from each other. In addition, the accompanying drawings are for easy understanding of the aspect disclosed in this specification, and the technical idea disclosed in this specification is not limited by the accompanying drawings. Also, when an element such as a layer, region or substrate is referred to as being ‘on’ another element, this means that there may be directly on the other element or be other intermediate elements therebetween.

In an aspect, the power converter is used for inverters or converters such as computers, home appliances, automobiles, solar power, and smart grids. In an aspect, the power converter may comprise one power semiconductor module or a plurality of power semiconductor modules. In addition, the power semiconductor module may comprise a plurality of power semiconductor devices.

In the following aspects, for example as shown inFIGS.1and11, an inverter for driving a motor of a vehicle is described as a power semiconductor device, but the power converter of the aspect may be applied to any suitable inverter or converter. In some cases, the vehicle may be an eco-friendly vehicle, and may comprise an electric vehicle (EV), a hybrid EV (HEV), a plugin hybrid EV (PHEV), passenger car equivalent vehicles (PCEV) or the like.

In the following aspect, a withstanding voltage and a breakdown voltage may be used interchangeably.

In the following aspects, a switching device and a power semiconductor device may be used interchangeably and a leg and a power semiconductor module may be used interchangeably.

FIG.1is a circuit diagram illustrating an automotive inverter according to a first aspect.

Referring toFIG.1, an inverter1000according to the first aspect may convert a direct current (DC) power into alternating current (AC) power and supply the converted AC power to a load1200to drive the load1200. In the inverter1000according to the first aspect, a battery may be connected to an input terminal so that DC power of the battery may be converted into AC power. Although not shown, a converter may be connected to the input terminal of the battery, and an input terminal of the converter may be connected to a charger of a charging station. In this case, AC power supplied through the charger may be converted into DC power by the converter to charge the battery. In addition, the DC power charged in the battery may be converted into AC power by the inverter1000according to the first aspect and may be used to drive the load.

The circuit configuration of the converter may be similar or identical to that of the inverter.

The load1200may be a motor but is not limited thereto.

The inverter1000according to the first aspect may comprise a 3-phase inverter but is not limited thereto. For example, a 3-phase inverter may output AC currents having a phase difference of 120 degrees between the first phase, the second phase, and the third phase. The inverter1000according to the first aspect may comprise a plurality of legs100A,100B, and100C. For example, the first leg100A, the second leg100B, and the third leg100C may be connected in parallel to the load, i.e., the motor through a first node N1, a second node N2, and a third node N3, respectively. The first leg100A may include a first arm100aand a second arm100bconnected in series with each other, and the second leg100B may include a third arm100cand a fourth arm100dconnected in series with each other, and the third leg100C may include a fifth arm100eand a sixth arm100fconnected in series with each other. The first arm100a, the third arm100c, and the fifth arm100emay be called an upper arm, and the second arm100b, the fourth arm100d, and the sixth arm100fare called a lower arm. Each of the first arm100ato sixth arms100fmay be referred to as a switching module or submodule.

The first arm100ato the sixth arm100fmay include switching devices100a-1,100b-1,100c-1,100d-1,100e-1, and100f-1and diodes100a-2and100b-2,100c-2,100d-2,100e-2, and100f-2, respectively. The switching devices100a-1,100b-1,100c-1,100d-1,100e-1,100f-1and the diodes100a-2,100b-2,100c-2,100d-2,100e-2,100f-2) may be formed simultaneously using the same semiconductor process. The switching devices100a-1,100b-1,100c-1,100d-1,100e-1, and100f-1may include a power semiconductor device, respectively.

To convert DC power into AC power by the inverter according to the first aspect, the switching devices100a-1,100b-1,100c-1, and100d-1,100e-1, and100f-1of each of the first arm100ato the sixth arm100fmay be on/off controlled.

For example, when the first switching device100a-1of the first arm100aof the first leg100A is in an on state, the diode100d-1of the fourth arm100dof the second leg100B and/or the sixth switching device100f-1of the sixth arm100fof the third leg100C may be turned on. Accordingly, DC power may be supplied to the first phase inductor of the motor.

For example, when the second switching device100b-1of the second arm100bof the second leg100B is in an on state, the sixth switching device100f-1of the sixth arm100fof the third leg100C and/or the second switching device100b-1of the second arm100bof the first leg100A may be turned on. Accordingly, DC power may be supplied to the second phase inductor of the motor. The second phase may be delayed by 120 degrees from the first phase.

For example, when the third switching device100c-1of the third arm100cof the third leg100C is in an on state, the second switching device100b-1of the second arm100bof the first leg100A and/or the diode100d-1of the fourth arm100dof the second leg100B may be turned on. Accordingly, DC power may be supplied to the third phase inductor of the motor. The third phase may be delayed by 120 degrees from the second phase.

Accordingly, AC power may be generated by the DC power supplied to each of the first phase inductor, the second phase inductor, and the third phase inductor.

Meanwhile, although not shown, the switching devices of each of the first arm100ato sixth arm100f, that is, the switching devices100a-1,100b-1,100c-1,100d-1,100e-1,100f-1may be connected in series with each other.

Although not shown, the switching devices of each of the first arm100ato sixth arm100f, that is, the switching devices100a-1,100b-1,100c-1,100d-1,100e-1,100f-1may be provided in a plurality connected in parallel with each other.

In some cases, the switching devices100a-1,100b-1,100c-1,100d-1,100e-1, and100f-1and the diode100a-2,100b-2,100c-2,100d-2,100e-2,100f-2corresponding to the first arm100ato the sixth arm100fmay be packaged and configured as a power semiconductor module

As an example, each of the first leg100A, the second leg100B, and the third leg100C may be configured as a power semiconductor module. That is, the first arm100aand the second arm100bof the first leg100A may be packaged to form a first power semiconductor module. The third arm100cand the fourth arm100dof the second leg100B may be packaged to form a second power semiconductor module. The fifth arm100eand the sixth arm100fof the third leg100C may be packaged to form a third power semiconductor module.

As another example, the first leg100A, the second leg100B, and the third leg100C may be configured as a single power semiconductor module. That is, the first arm100aand the second arm100bof the first leg100A, the third arm100cand the fourth arm100dof the second leg100B, and the fifth arm100eand the sixth arm100fof the third leg100C may be packaged to form a single power semiconductor module.

A power semiconductor device will be described below with reference toFIGS.2to9. In the following description, components with doped regions having the same dose and formed on the same layer may be simultaneously formed through the same ion implantation process using the same mask. Alternatively, components having the same dose and formed on the same layer may be formed at different times with different masks.

The ion implantation process physically implants ions using a source gas into the substrate212. The ions may be collectively referred to as impurities. Through the ion implantation process, various regions having different or identical doses may be formed by increasing a conductivity of an insulating material or changing it to semiconductive.

Hereinafter, a substrate, a drift layer, a body, a contact region, a source region, a blocking region, a separation region, or two or more sub-regions included in the separation region may be formed through the above-described ion implantation process. Different energies may be used in the various regions where ions are implanted according to their dopant concentration or position. For example, low energy may be used to implement a shallow junction, and high energy may be used to implement a deep junction, but this are not limited thereto.

In the following description, the terms dose, dose amount, and dopant concentration have the same meaning and may be used interchangeably.

FIG.2is a plan view illustrating a power semiconductor device according to an aspect.

Referring toFIG.2, the power semiconductor device according to the aspect may be divided into an active area206and a termination area207. The power semiconductor device according to the may be a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), but is not limited thereto.

The active area206may comprise a plurality of active cells. Each active cell may comprise a semiconductor device including a gate electrode217, a source electrode219, and a drain electrode211to perform a predetermined operation. Accordingly, a plurality of semiconductor devices may be configured by a plurality of active cells.

Since the plurality of active cells are defined in a matrix, a plurality of semiconductor devices may also be arranged in a matrix.

The termination area207may surround the active area206. The termination area207may be located along an edge of the active area206. The termination area207may enable a high breakdown voltage by dispersing an electric field.

In illustrated aspects, the power semiconductor device according to the aspect is shown as having a rectangular shape when viewed from the top, but the power semiconductor may have other shapes.

A gate pad201and a source pad202may be positioned in the active area206. The gate pad201is connected to the gate electrode217of each active cell through a gate line208so that a gate signal may be supplied to the gate electrode217. The source pad202is connected to the source electrode219of each active cell so that a source voltage may be supplied to the source electrode219. Although not shown, a drain pad may be located on a lower side of the power semiconductor device according to the aspect. The drain pad may be connected to the drain electrodes211of each active cell so that a drain voltage may be supplied to the drain electrodes211.

The gate electrode217may be called a gate, a gate poly, a gate contact, or the like. The source electrode219may be referred to as a source contact, and the gate electrode217may be referred to as a gate contact. Although not shown, the source pad202may be collectively referred to as the source electrode219without being distinguished from the source electrode219, and the drain pad may be collectively referred to as the drain electrode211without being distinguished from the drain electrode211.

FIG.3is an enlarged plan view illustrating a region X ofFIG.2.FIG.4is a cross-sectional view in which a region X shown inFIG.3is taken along line C-C′.FIG.5is a cross-sectional view in which a region X shown inFIG.3is taken along line D-D′.

As shown inFIG.3, six semiconductor devices are shown in the region X.

One active cell may include one semiconductor device, but is not limited thereto. For example, one active cell may include two or more semiconductor devices.

The power semiconductor device according to the aspect may comprise a drain electrode211, a substrate212, a drift layer213, bodies214-1and214-2, source regions215(e.g., source regions215-1and215-2), and contact regions216(e.g., contact regions216-1and216-2), a gate electrode217, an insulating layer218, and a source electrode219. A semiconductor device including an active cell may comprise the substrate212, the drift layer213, the bodies214-1and214-2, the source regions215-1and215-2, and the contact regions216-1and216-2, the gate electrode217, the insulating layer218, and the source electrode219. Alternatively or additionally, the power semiconductor device according to the aspect may comprise additional components.

The drain electrode211may be disposed below the substrate212. The drain electrode211may supply a drain voltage to the substrate212. The drain electrode211may include a drain pad or a drain pad may be separately disposed below the drain electrode211. The drain electrode211may be formed of Ni or other suitable material that forms an ohmic contact with an N-type silicon carbide (SiC).

The substrate212and/or the drift layer213may comprise a semiconductor compound such as SiC, gallium nitride (GaN), gallium oxide (Ga2O3), or the like. For example, the substrate212and/or the drift layer213may comprise a 4H-SiC material but is not limited thereto. For example, the substrate212and/or the drift layer213may comprise 3C-SiC or 6H-SiC.

The drift layer213may be disposed on the substrate212. The drift layer213may be the substrate212or an epitaxial layer. The substrate212and the drift layer213may constitute a drain region, but are not limited thereto.

The drift layer213may comprise at least one or more drift region, but is not limited thereto. The drift layer213may be referred to as a drift region.

The substrate212and the drift layer213may have the same type of conductivity. For example, the substrate212and the drift layer213may have a first conductivity type. The first conductivity type may be N type, but is not limited thereto. To this end, the substrate212and the drift layer213may comprise an N-type dopant.

The bodies214-1and214-2may be formed separated from each other within the drift layer213. The bodies214-1and214-2may have a second conductivity type. The bodies214-1and214-2may, for example, comprise a P-type dopant. When the bodies214-1and214-2comprise a P-type dopant, the bodies214-1and214-2may be referred to as a P-well. The bodies214-1and214-2may be referred to as a base region.

The contact regions216-1and216-2and the source regions215-1and215-2may be disposed in the bodies214-1and214-2. The contact regions216-1and216-2may have the same conductivity type as the bodies214-1and214-2, that is, the second conductivity type. The source regions215-1and215-2may have the same conductivity type as the drift region, that is, the first conductivity type. The source regions215-1and215-2and the contact regions216-1and216-2may be disposed adjacent to each other. The dopant concentration (P+) of the contact regions216-1and216-2may be greater than the dopant concentration (P−) of the bodies214-1and214-2.

As shown inFIG.3, the source regions215-1and215-2may have a stripe shape extending along one direction (e.g., the Y-axis direction). In contrast, the contact regions216-1and216-2may contact the bodies214-1and214-2by passing through the source regions215-1and215-2. The contact regions216-1and216-2may be formed for each active cell but are not limited thereto.

The source electrode219may contact the contact regions216-1and216-2and the source regions215-1and215-2. The source electrode219may be formed of nickel (Ni) or the like. An annealing process may be performed for the source electrode219to form an ohmic contact with the contact regions216-1and216-2and/or the source regions215-1and215-2.

The source electrode219may be disposed on an entire area of the active area206. The source electrode219may be disposed on the gate electrode217. Although not shown, the source electrode219may not be disposed on the gate electrode217but may be disposed only on the contact regions216-1and216-2and the source regions215-1and215-2.

The gate electrode217may be disposed on the drift layer213between the bodies214-1and214-2separated from each other. The gate electrode217may be surrounded by the insulating layer218. The insulating layer218may be referred to as a gate oxide film. Another insulating layer may be disposed below the source electrode219but is not limited thereto.

In the semiconductor device having the above structure, channel layers between the drift layer213and the source regions215-1and215-2are conductive when the gate voltage is supplied to the gate electrode217and a current may flow between the source regions215-1and215-2and the drift layer213. Therefore, the channel layers between the drift layer213and the source regions215-1and215-2may be conduct current or block current according to the gate voltage, thereby implementing a switching function.

First Aspect

FIG.6is a cross-sectional view illustrating a power semiconductor device according to a first aspect.FIG.6is a cross-sectional view taken along line A-A′ and line B-B′, respectively in the power semiconductor device according to the aspect shown inFIG.2.

As shown inFIG.6, the power semiconductor device200A may be divided into an active area206and a termination area207. As described above, the active area206may comprise a plurality of active cells206-1to206-4each constituting a semiconductor device, and the termination area207may be located along the perimeter of the active area206. The termination area207may provide a high breakdown voltage by dispersing an electric field. In one example, a breakdown voltage of 1, 200V or more may be generated by electric fields applied when the plurality of semiconductor devices included in the active area206operate. In this case, the termination area207may be positioned along the perimeter of the active area206. Accordingly, since the electric fields are dispersed by the termination area207, the power semiconductor device200A may withstand a high breakdown voltage.

The power semiconductor device200A according to the first aspect may comprise a drain electrode211, a substrate212, a drift layer213, bodies214-1and214-2, and source regions215-1and215-2, contact regions216-1and216-2, a gate electrode217, an insulating layer218, and a source electrode219.

The substrate212may comprise the active area206and the termination area207. The active area206may comprise the plurality of active cells206-1to206-4.

The drain electrode211is disposed below the substrate212, and the drift layer213, the bodies214-1and214-2, the source regions215-1and215-2, the contact regions216-1and216-2, the gate electrode217, the insulating layer218, and the source electrode219may be disposed on the substrate212.

The drain electrode211and the drift layer213may be respectively disposed on an entire area of the substrate212. The bodies214-1and214-2may be disposed on the drift layer213between adjacent active cells206-1to206-4. The source regions215-1and215-2, the gate electrode217, and the insulating layer218may be disposed in each of the active cells206-1to206-4. The source regions215-1and215-2are disposed on the bodies214-1and214-2, the gate electrode217is disposed on the drift layer213, and the insulating layer218may surround the gate electrode. In particular, the insulating layer218may be positioned between the drift layer213and the gate electrode217to function as a gate oxide film. The contact regions216-1and216-2may be disposed between adjacent active cells206-1to206-4. The contact regions216-1and216-2may be disposed on bodies214-1and214-2. The contact regions216-1and216-2may contact the bodies214-1and214-2through the source regions215-1and215-2disposed between the adjacent active cells206-1to206-4.

The source electrode219may be disposed on an entire area of the substrate212. The source electrode219may be disposed on the active area206. The source electrode219may not be disposed on the gate electrode217, but may be disposed on the source regions215-1and215-2.

A semiconductor device may be configured for each of the active cells206-1to206-4by the drain electrode211, the substrate212, the drift layer213, the bodies214-1and214-2, the source regions215-1and215-2, the contact regions216-1and216-2, the gate electrode217, the insulating layer218, and the source electrode219.

Since four active cells206-1to206-4are shown inFIG.6, four semiconductor devices corresponding to the active cells206-1to206-4may be included in the active area206.

Meanwhile, the termination area207may be located at an outer edge (e.g., a border) of the active cell. As described above, the termination area207may surround the active cells206-1to206-4. Accordingly, the active cells206-1to206-4and the termination area207may be positioned horizontally.

A junction termination extension (JTE)220may be disposed in the termination area207. The JTE220may have the same conductivity type as a doped body located at the outermost part of the active area206(hereinafter referred to as the outermost body214-3). The JTE220may have a second conductivity type. The termination area207is configured to disperse an electric field and is a very important region capable of increasing a breakdown voltage. To increase the breakdown voltage of the power semiconductor device200A, an optimization design for the termination area207is required.

In some aspects, the bodies214-1and214-2described in relation to the JTE220in the termination area207may refer to the outermost body214-3unless otherwise described.

The JTE220may be disposed along the perimeter of the active area206. The JTE220may be disposed horizontally with the outermost body214-3. The outermost body214-3and the JTE220are formed on the drift layer213and may have the same conductivity type. The upper side of the outermost body214-3and the upper side of the JTE220may be located at the same horizontal line.

The lower side of the outermost body214-3may be positioned lower than the lower side of the JTE220, but is not limited thereto.

The JTE220may comprise at least one blocking region221and a plurality of separation regions222-1to222-n. The blocking region221and/or the plurality of separation regions222-1to222-nmay have a ring shape but are not limited thereto. For example, the blocking region221may have a ring shape along the circumference of the active area206. Each of the plurality of separation regions222-1to222-nmay have a ring shape along the circumference of the active area206. Each of the plurality of separation regions222-1to222-nmay have a ring shape along the circumference of the blocking region221.

The blocking region221is referred to as a single junction, and the plurality of separation regions222-1to222-neach having a ring shape may be referred to as a Floating Field Ring (FFR).

The blocking region221may primarily block an electric field. For example, the electric field generated in the active area206may be primarily blocked by the blocking region221.

The blocking region221may be horizontally disposed on a side portion214aof the outermost body214-3. The blocking region221may contact the side portion214aof the outermost body214-3but is not limited thereto. A lower side of the outermost body214-3may be positioned lower than a lower side of the blocking region221. The depth of the blocking region221may be smaller than the depth of the outermost body214-3but is not limited thereto.

Meanwhile, the plurality of separation regions222-1to222-nmay serve to further block an electric field remaining even after being primarily blocked by the blocking region221.

The plurality of separation regions222-1to222-nmay be disposed along a lateral direction of the blocking region221. The blocking region221and the plurality of separation regions222-1to222-nmay be horizontally disposed. The plurality of separation regions222-1to222-nmay be located farther from the outermost body214-3than the blocking region221. The plurality of separation regions222-1to222-nmay be sequentially disposed from the outermost body214-3toward the edge of the substrate212. The blocking region221and each of the plurality of separation regions222-1to222-nmay have the same depth, but are not limited thereto.

The blocking region221and the plurality of separation regions222-1to222-nmay have the same conductivity type, for example, a second conductivity type. The blocking region221and the plurality of separation regions222-1to222-nmay be formed using the same mask. The bodies214-1and214-2(including the outermost body214-3), the blocking region221, and the plurality of separation regions222-1to222-nmay be formed using the same mask.

A plurality of separation intervals d11to d13may formed between the blocking region221and the plurality of separation regions222-1to222-n. For example, an interval between the first separation regions222-1closest to the blocking region221among the plurality of separation regions222-1to222-nand the blocking region221may be defined as a first separation interval d11. For example, intervals between the plurality of separation regions222-1to222-nmay be the remaining separation intervals d12and d13.

As an example, the first separation interval d11may be smaller than each of the remaining separation intervals d12to d13.

As another example, the first separation interval d11and the remaining separation intervals d12to d13may increase as the distance from the outermost body214-3increases.

As another example, the first separation interval d11and each of the remaining separation intervals d12to d13may be the same.

The blocking region221may include at least one sub-blocking region221athat is disposed within the blocking region221. The sub-blocking regions221amay be separated from each other. The blocking region221and the at least one sub-blocking region221amay have the same conductivity type as the contact regions216-1and216-2, for example, a second conductivity type. A dopant concentration (P+) of the sub-blocking region221amay be greater than a dopant concentration (P−) of the blocking region221. Dispersion of the electric field may be achieved even better by at least one or more sub-blocking region221a.

Meanwhile, the blocking region221and the plurality of separation regions222-1to222-nare deep junctions, and high implant energy is required to implement them. Accordingly, design rules are to increase the number of the plurality of separation regions222-1to222-nwhile maintaining the predetermined distances d11to d13. When the design rule is applied to a semiconductor design, the size of the power semiconductor device200A increases. In addition, when the design rule is applied to a semiconductor design, it becomes difficult to design an optimized space and the breakdown voltage of the semiconductor design is lowered.

In particular, the first separation interval d11is the smallest among the plurality of separation intervals d11to d13, and is required to be, for example, 1 micrometer or less. This is because, as the first separation interval d11is smaller, an optimized space may be designed without a desired design rule limitation. Therefore, the first separation regions222-1may be formed with a first distance d11of 1 micrometer or less from the outermost body214-3so that there is a need for a new structure that may design an optimized space without design rule restrictions.

Hereinafter, a power semiconductor device200B having a new structure for solving the above problems will be described with reference toFIGS.7to9. That is, according to the power semiconductor device200B according to the second aspect, it is possible to improve the optimal space design and withstand voltage performance.

Second Aspect

FIG.7is a cross-sectional view illustrating a power semiconductor device according to a second aspect.FIG.8is an enlarged cross-sectional view illustrating a JTE in the power semiconductor device according to the second aspect shown inFIG.7.

The second aspect is the same as the first aspect except for the plurality of separation regions222-1to222-neach comprising at least two or more sub-regions. In the second aspect, the same reference numerals are given to components having the same structure, shape and/or function as those in the first aspect, and detailed descriptions are omitted. The description omitted below may be replaced with the description of the first aspect (e.g.,FIG.6), and may be easily understood by the description of the first aspect inFIG.6.

Referring toFIG.7andFIG.8, the power semiconductor device200B according to the second aspect may comprise a drain electrode211, a substrate212, a drift layer213, bodies214-1and214-2, source regions215-1and215-2, contact regions216-1and216-2, a gate electrode217, an insulating layer218, and a source electrode219.

An active area206and a termination area207may be disposed on the substrate212. As shown inFIG.2toFIG.5andFIG.7, the active area206may comprise a plurality of active cells206-1to206-4, and the termination area207may surround the active area206.

The drift layer213may be disposed on the substrate212, and the drain electrode211may be disposed below the substrate212. The bodies214-1and214-2are disposed in the drift layer213in the active area206, and the contact regions216-1and216-2and the source regions215-1and215-2are disposed in the bodies214-1and214-2. In addition, a gate electrode217and the insulating layer218may be disposed on the drift layer213between the adjacent bodies214-1and214-2. In this case, the insulating layer218may surround the gate electrode217. The source electrode219may be disposed on the substrate212. The source electrode219may be disposed on the active area206but is not limited thereto.

A semiconductor device may be configured by the drain electrode211, the substrate212, the drift layer213, the bodies214-1and214-2included in each of the plurality of active cells206-1to206-4of the active area206, the contact regions216-1and216-2, the source regions215-1and215-2, the gate electrode217, the insulating layer218, and the source electrode219.

In addition, a JTE220may be disposed in the termination area207. The JTE220may comprise at least one or more blocking regions221and a plurality of separation regions222-1to222-n. The blocking region221and the separation regions222-1to222-nmay have the same conductivity type, for example, a second conductivity type. The blocking region221and the separation regions222-1to222-nmay have the same conductivity type as the bodies214-1and214-2(including the outermost body214-3). A dopant concentration of the blocking region221may be equal to or greater than a dopant concentration of each the bodies214-1and214-2. The dopant concentration of each of the separation regions222-1to222-nmay be equal to or greater than the dopant concentration of each of the bodies214-1and214-2.

The blocking region221may be disposed adjacent to the outermost body214-3. The blocking region221may be disposed horizontally with the outermost body214-3. The blocking region221may be disposed on a side portion214aof the outermost body214-3. The blocking region221may contact the outermost body214-3.

The depth of each of the bodies214-1and214-2(including the outermost body214-3) may be greater than the depth of the blocking region221or the depth of each of each of the separation regions222-1to222-n. At least one or more separation region among the plurality of separation regions222-1to222-nmay have the same conductivity type as the blocking region221. The at least one or more separation region among the plurality of separation regions222-1to222-nmay have the same conductivity type as the bodies214-1and214-2.

Meanwhile, each of the plurality of separation regions222-1to222-nmay comprise two or more sub-regions. The two or more sub-regions may have the same conductivity type as the blocking region221. The two or more sub-regions may have the same conductivity type as the bodies214-1and214-2.

For example, the two or more sub-regions may comprise first sub-regions222-1ato222-naand second sub-regions222-1bto222-nb.

The first sub-regions222-1ato222-naand the second sub-regions222-1bto222-nbmay have different dopant concentrations. The first sub-regions222-1ato222-naand the second sub-regions222-1bto222-nbmay be adjacent to each other. For example, the first sub-regions222-1ato222-namay be located closer to the outermost body214-3than the second sub-regions222-1bto222-nb. For example, the second sub-regions222-1bto222-nbmay be located farther from the outermost body214-3than the first sub-regions222-1ato222-na.

The dose of each of the first sub-regions222-1ato222-namay be the same as the dose of each of the bodies214-1and214-2(including the outermost body214-3). The dose of each of the second sub-regions222-1bto222-nbmay be the same as the dose of each of the bodies214-1and214-2. A first dose of each of the first sub-regions222-1ato222-namay be greater than a second dose of each of the second sub-regions222-1bto222-nb. The first dose of each of the first sub-regions222-1ato222-namay be greater than the dose of each of the bodies214-1and214-2. A second dose of each of the second sub-region222-1bto222-nbmay be the same as the dose of the blocking region221. For example, the blocking region221and the second sub regions222-1bto222-nbmay be formed on the drift layer213using the same mask, but this is not limited thereto.

Meanwhile, a plurality of separation intervals d21to d23may be defined between the blocking region221and the plurality of separation regions222-1to222-n. For example, an interval between the first sub-region222-1aof the first separation region222-1among the plurality of separation regions222-1to222-nand the blocking region221may be defined as the first separation interval d21. For example, intervals between the plurality of first sub-regions222-1ato222-naof the plurality of separation regions222-1to222-nmay be defined as the remaining separation intervals d22and d23.

Alternatively, the plurality of separation intervals d21to d23may be defined based on the second sub-regions222-1bto222-nbincluded in the plurality of separation regions222-1to222-n, respectively., but are not limited thereto

As an example, the first separation interval d21may be smaller than each of the remaining separation intervals d22and d23.

As another example, the first separation interval d21and the remaining separation intervals d22and d23may increase as the distance from the outermost body214-3increases.

Since the first separation interval d21is implemented as a shallow junction and is formed by the first sub-regions222-1ato222-naeach having a first dopant concentration greater than a second dopant concentration of each of the second sub-regions222-1bto222-nb, the first separation interval d21may be smaller than the first separation interval d11of the first aspect (FIG.6). Accordingly, in the second aspect, since the first separation interval d21is at least 1 micrometer or less, an optimized space may be achieved without design rule restrictions.

In some cases, the first sub-regions222-1ato222-naand the second sub-regions222-1bto222-nbmay have different depths T1and T2. For example, the first sub-regions222-1ato222-namay be shallow junctions, and the second sub-regions222-1bto222-nbmay be deep junctions. For example, the first dopant concentration of each of the first sub-regions222-1ato222-namay be greater than the second dopant concentration of each of the second sub-regions222-1bto222-nb. Accordingly, the first sub-regions222-1ato222-naare located shallowly near the surface of the drift layer213and may be formed by an ion implantation process using low energy. In contrast, since the second sub-regions222-1bto222-nbare located deeper than at least the first sub-regions222-1ato222-nafrom the surface of the drift layer213and may be formed by an ion implantation process using high energy.

During the high-energy ion implantation process, since the second sub-regions222-1bto222-nbare formed deeply, the separation intervals between the second sub-regions222-1bto222-nbmay create issues. However, since the second sub-regions222-1bto222-nbare located deeper than the first sub-regions222-1ato222-na, the electric field may be more appropriately dispersed.

Meanwhile, since the first sub-regions222-1ato222-naare formed shallowly during the low-energy ion implantation process, the separation intervals between the first sub-regions222-1ato222-namay be reduced as much as possible. Therefore, the first sub-regions222-1aof the first separation region222-1that are closest to the outermost body214-3may be formed with a first separation interval d21of at least 1 micrometer or less from the outermost body214-3. By reducing the first separation interval d21as much as possible, the electric field may be greatly dispersed by the first sub-region222-1aof the first separation region222-1among the plurality of separation regions222-1to222-n.

Similarly, the remaining separation intervals d22and d23, which are intervals between sub-regions of each of the plurality of separation regions222-1to222-nmay also be formed narrowly by an ion implantation process having low energy. Accordingly, even if a very strong electric field is formed in the power semiconductor device200B, the electric field that is generated during operation may be appropriately dispersed by the blocking region221and the plurality of separation regions222-1to222-n, which each include at least two or more sub-regions, so that a breakdown voltage may be further increased. As shown inFIG.9, the power semiconductor device200B capable of withstanding a breakdown voltage of at least 1,600V or more may be implemented.

According to the second aspect, since each of the plurality of separation regions222-1to222-ncomprise two or more sub-regions, each of the plurality of separation intervals d21to d23may be smaller than each of the plurality of separation intervals d11to d13of the first aspect inFIG.6.

As described above, each of the plurality of separation regions222-1to222-nin the first aspect (FIG.6) may be composed of a single region. At this time, since the ion implantation process is performed with high energy to realize a deep junction for forming the single region, it is difficult to narrow the plurality of separation intervals d11to d13.

In contrast, according to the second aspect inFIG.7andFIG.8, the plurality of separation regions222-1to222-nmay comprise two or more sub-regions, that is, the first sub-regions222-1ato222-naand the second sub-regions222-1bto222-nb. In this case, an ion implantation process having relatively low energy may be performed so that the first sub-regions222-1ato222-nacloser to the outermost body214-3are implemented as shallow junctions. Accordingly, the plurality of separation intervals d21to d23may be narrowed as compared to the first aspect inFIG.6and an optimized space may be designed without the design rule restrictions noted above.

In addition, since the electric field may appropriately be dispersed by the second sub-regions222-1bto222-nb, with each having a second dopant concentration smaller than a first dopant concentration of each of the first sub-regions222-1ato222-na, a desired breakdown voltage may be achieved. In other words, in each of the plurality of separation regions222-1to222-n, an optimized space may be designed by the first sub-regions222-1ato222-nathat comports with the design rule restrictions, and a desired breakdown voltage may be achieved through a dispersion of electric field by the second sub-region222-1bto222-nb.

When the dopant concentration of each of the separation regions222-1to222-nis lowered to disperse the electric field, the design rule may increase due to the high-energy ion implantation process performed to implement the deep junction. Conversely, when the dose of each of the separation regions222-1to222-nis increased to reduce the design rule, the electric field is concentrated in the separation regions222-1to222-n, and the withstanding voltage may rather decrease. The second aspect may have a unique technical effect that may simultaneously solve the contradiction between the two. That is, in the second aspect, two or more sub-regions are included in each of the plurality of separation regions222-1to222-nso that, for example, design rules may be reduced by the first sub-regions222-1ato222-nacloser to the outermost body214-3, and for example, a breakdown voltage of 1, 600V or more may be achieved by appropriate dispersion of an electric field by the second sub-regions222-1bto222-nbas shown inFIG.9. Since the product reliability of the power semiconductor device200B according to the second aspect from which the corresponding technical effect may be obtained, it may be applied to various downstream industries requiring a higher breakdown voltage, such as ultra-high voltage power generation, power transmission and distribution facilities, or electric vehicles.

Meanwhile, the upper sides1A of the first sub-regions222-1ato222-naand the upper sides1B of the second sub-regions222-1bto222-nbare located at the same horizontal line, and the lower sides ID of the second sub-regions222-1bto222-nbmay be located lower than the lower sides IC of the first sub-regions222-1ato222-na.

The first sub-regions222-1ato222-naand/or the second sub-regions222-1bto222-nbmay be formed on the drift layer213using an ion implantation process. When the upper side of the drift layer213has a flat surface, the first sub-regions222-1ato222-naand/or the second sub-regions222-1ato222-naare formed by impurities including ions implanted through the upper side of the drift layer213. area may be formed. Accordingly, the upper side IA of the first sub-regions222-1ato222-naformed in the drift layer213and the upper side1B of the second sub-regions222-1bto222-nbmay be located at the same horizontal line.

An ion implantation process may be performed using different energies to form the first sub-regions222-1ato222-naand the second sub-regions222-1bto222-nb. For example, the first sub-regions222-1ato222-namay be formed by an ion implantation process with low energy, and the second sub-regions222-1bto222-nbmay be formed by an ion implantation process with high energy. Accordingly, the lower sides ID of the second sub-regions222-1bto222-nbformed by the high-energy ion implantation process may be positioned lower than the lower sides IC of the first sub-regions222-1ato222-naformed by the low-energy ion implantation process. That is, the impurities forming the second sub-regions222-1bto222-nbmay be formed deeper from the upper side of the drift layer213than the impurities forming the first sub-regions222-1ato222-na. The lower sides ID of the deeper second sub-regions222-1bto222-nbmay be positioned lower than the lower sides IC of the first sub-regions222-1ato222-na.

Meanwhile, the plurality of separation regions222-1to222-nmay comprise overlapping regions222-1cto222-nc, respectively. The overlapping region222-1cto222-ncmay comprise a part of the first sub-region222-1ato222-naand a part of the second sub-region222-1bto222-nb. That is, the overlapping region222-1cto222-ncmay be formed by mixing the first impurities for forming the first sub-regions222-1ato222-naand the second impurities for forming the second sub-regions222-1bto222-nb.

For example, after the first sub-regions222-1ato222-naare formed in the drift layer213using the first impurity, the second sub-region222-1bto222-nbmay be formed in some parts of the pre-formed first sub-regions222-1ato222-naand the drift layer213in contact with some parts of the first sub-regions222-1ato222-na. Thus, the overlapping regions222-1cto222-ncmay be formed in some parts of the first sub-regions222-1ato222-na, and the second sub-regions222-1bto222-nbmay be formed in the first sub-regions222-1ato222-na.

The lower sides ID of the second sub-regions222-1bto222-nbmay be located below the overlapping regions222-1cto222-nc. As described above, the energy of the ion implantation process used to form the second sub-regions222-1bto222-nbmay be greater than the energy of the implantation process used to form the first sub-regions222-1ato222-na. Accordingly, the second impurities may be implanted into some parts of the pre-formed first sub-regions222-1ato222-naand the drift layer213in contact with some parts of the first sub-regions222-1ato222-nathrough an ion implantation process having high energy. Thus, some of the second impurities may be implanted into some parts of the first sub-regions222-1ato222-na, and they may be mixed with the first impurities included in some parts of the first sub-regions222-1ato222-nato form the overlapping regions222-1cto222-nc. Another part of the second impurity is implanted into the drift layer213on the lower portion of some parts of the first sub-region222-1ato222-naby passing through some parts of the first sub-regions222-1ato222-naso that a part of the second sub-region222-1bto222-nbmay be formed. Another part of the second impurity is implanted into the drift layer213in contact with some parts of the first sub-regions222-1ato222-nato form the second sub-regions222-1bto222-nb. Therefore, the lower side ID of the second sub-regions222-1bto222-nbmay be located below the overlapping regions222-1cto222-nc.

Although it has been described that the second sub-regions222-1bto222-nbare formed after the first sub-regions222-1ato222-naare formed, the order may be changed.

Meanwhile, as shown inFIG.9, since the plurality of separation regions222-1to222-nare included, it may be seen that a constant breakdown voltage is maintained regardless of the increase or decrease in dopant concentration (e.g., dopant concentrations can be the same as a previous process) in the aspect compared to the comparative example. The comparative example is a power semiconductor device without a plurality of separation regions222-1to222-n, and the aspect is a power semiconductor device with a plurality of separation regions222-1to222-n. In particular, the aspect is a power semiconductor device in which a plurality of separation regions222-1to222-nare separated into two or more sub-regions, and a breakdown voltage of at least 1, 600V or more may be maintained constant regardless of an increase or decrease in dose.

The above detailed description should not be construed as limiting in all respects and should be considered illustrative. The scope of the aspect should be determined by reasonable interpretation of the appended claims, and all changes within the equivalent range of the aspect are included in the scope of the aspect.