Current supply for an opto-electronic device

A device, including a first current supply configured to provide a bias current to a load and a main current supply having a source terminal coupled in parallel with the load and configured to reduce a current value to the load below the bias current, is provided. The device includes a termination resistor coupled in series with the source terminal of the main current supply and configured to receive current from the source terminal of the main current supply when the source terminal of the main current supply is activated. The device also includes an auxiliary current supply having a sink terminal coupled to the termination resistor at a common node, and configured to maintain the common node at common mode voltage when current flows from the source terminal of the main current supply to the sink terminal of the auxiliary current supply and through the termination resistor.

TECHNICAL FIELD

Embodiments described herein are generally related to the field of opto-electronic device transducers. More specifically, embodiments described herein are related to compact and efficient current supplies for opto-electronic data conversion.

BACKGROUND

Current opto-electronic systems are expected to operate at high data rates that impose stringent conditions on the capacitive response of the driver terminations. To reduce ground impedance for high frequency alternate current (AC) components and to maintain a stable charge level for the device, current solutions implement large capacitors in the driver circuits. However, these large capacitors reduce the area efficiency of the circuit and add to a sluggish response of the device. In some approaches, a voltage source may be added to the circuitry to maintain a common mode voltage and guarantee that the device response is stable, regardless of the data conditions to which it is subjected.

SUMMARY

In certain aspects, a device as disclosed herein includes a first current supply configured to provide a bias current to a load, a main current supply having a source terminal coupled in parallel with the load and configured to reduce a current value to the load below the bias current. The device also includes a termination resistor coupled in series with the source terminal of the main current supply and configured to receive a current from the source terminal of the main current supply when the source terminal of the main current supply is activated and an auxiliary current supply having a sink terminal coupled to the termination resistor at a common node, and configured to maintain the common node at a common mode voltage when a current flows from the source terminal of the main current supply to the sink terminal of the auxiliary current supply and through the termination resistor.

In certain aspects, a system as disclosed herein includes a light emitting device, a data channel configured to provide a data signal and a complementary signal to the data signal, and a first current supply configured to provide a bias current to the light emitting device. The system also includes a main current supply having a source terminal coupled in parallel with the light emitting device and configured to reduce a current value to the light emitting device below the bias current and a termination resistor coupled in series with the source terminal of the main current supply and configured to receive a current from the source terminal of the main current supply when the source terminal of the main current supply is activated. The system also includes an auxiliary current supply having a sink terminal coupled to the termination resistor at a common node, and configured to maintain the common node at a common mode voltage when a current flows from the source terminal of the main current supply to the sink terminal of the auxiliary current supply and through the termination resistor.

In certain aspects, a serial interface includes an opto-electronic data link. The opto-electronic data link includes a light emitting device, a data channel configured to provide a data signal and a complementary data signal, and a first current supply configured to provide a bias current to the light emitting device. The opto-electronic data link also includes a main current supply having a source terminal coupled in parallel with the light emitting device and configured to reduce a current value to the light emitting device below the bias current, a termination resistor coupled in series with the source terminal of the main current supply and configured to receive a current from the source terminal of the main current supply when the source terminal of the main current supply is activated. The opto-electronic data link also includes an auxiliary current supply having a sink terminal coupled to the termination resistor at a common node, and configured to maintain the common node at a common mode voltage when a current flows from the source terminal of the main current supply to the sink terminal of the auxiliary current supply and through the termination resistor, and a processor configured to determine an auxiliary current from the auxiliary current supply and a main current from the main current supply based on an updated value of a resistance of the light emitting device and of the termination resistor.

In certain aspects, a system is described including a means for emitting light. The system further includes a means to provide a current to the means for emitting light. The means to provide a current includes a data channel configured to provide a data signal and a complementary signal to the data signal, and a first current supply configured to provide a bias current to the light emitting device. The means to provide a current also includes a main current supply having a source terminal coupled in parallel with the light emitting device and configured to reduce a current value to the light emitting device below the bias current and a termination resistor coupled in series with the source terminal of the main current supply and configured to receive a current from the source terminal of the main current supply when the source terminal of the main current supply is activated. The means to provide a current also includes an auxiliary current supply having a sink terminal coupled to the termination resistor at a common node, and configured to maintain the common node at a common mode voltage when a current flows from the source terminal of the main current supply to the sink terminal of the auxiliary current supply and through the termination resistor.

In the figures, elements and steps denoted by the same or similar reference numerals are associated with the same or similar elements and steps, unless indicated otherwise.

DETAILED DESCRIPTION

General Overview

Drivers for application specific integrated circuit (ASIC) input/output (IO) are typically terminated with a resistance equal to the characteristic impendence of the channel they are driving. This termination is required in order to prevent any reflections coming back from the load or other discontinuities from reflecting a second time and corrupting the transmitted signal. To accomplish this termination, a resistor is usually connected between the driver output and either the VSS or VDD voltage sources. These sources act as an AC ground for the termination resistor. However, in some circumstances, the voltage source used may need to be a value other than VDD and VSS. This invention uses two auxiliary current sources to produce a virtual voltage source for the termination resistor of an ASIC IO driver.

The disclosed system provides a solution to the problem of stabilizing the voltage at the common node of the termination resistor that provides a substantial reduction of capacitive resources and on-chip real estate. When a voltage source other than VDD and VSS is required to be an AC ground for a termination resistor, there are three common ways to solve the problem. One approach provides an additional voltage source to the ASIC, which adds an additional pin to the package. Another approach is to put a regulator on chip and derive the new voltage from an existing voltage. However, voltage regulators typically take large areas of the chip and use substantial amount of power. Some approaches use a large capacitor to act as an AC ground in place of the voltage source. However, these approaches involve large capacitive resources and also consume large on-chip area. Embodiments disclosed herein overcome these problems by using a dual stage current source, and a relatively smaller capacitor as the AC ground for the termination resistor.

FIG. 1illustrates an opto-electronic system10including a dual stage current supply100, according to some embodiments. Opto-electronic system10includes a light emitting device120, and a data channel50configured to provide a data signal51a(‘datap’) to a main current supply101and to provide a complementary data signal51b(‘datan’) to an auxiliary current supply102. Complementary data signal51bmay be characterized in that it is ‘low’ when data signal51ais ‘high,’ and it is high when data signal51ais low. Hereinafter, data signal51aand complementary data signal51bwill be collectively referred to as “data signals51.” Dual stage current supply100is powered by a high voltage supply111(Vdd) and a low voltage supply112, or sink (Vss, e.g., ground).

A first current supply110in dual stage current supply100is configured to provide a bias current to light emitting device120. Main current supply101, has a source terminal101a, is coupled in parallel with light emitting device120and is configured to reduce a current value to light emitting device120below the bias current. Dual stage current supply100also includes a termination resistor130coupled with source terminal101aand configured to receive a current from source terminal101awhen it is activated. Auxiliary current supply102has a sink terminal102bcoupled to termination resistor130at a common node161, is configured to maintain common node161at a common mode voltage when a current flows from source terminal101ato sink terminal102band through termination resistor130. Termination resistor130includes an output node163at the opposite side of common node163. Dual stage current supply100is configured such that depending on data signals51from data channel50, a current through resistor130may flow from common node161to output node163, or from output node163to common node161, while a voltage (Vcm) of common node161is held constant.

In some embodiments, data channel50is configured to activate source terminal101aand sink terminal102bwhen data signal51ais a low value (e.g., complementary data signal51bis a high value), thereby lowering a current to light emitting device120below the bias current value, and reducing optical power output from opto-electronic system10. Likewise, data channel50is configured to activate source terminal102aand sink terminal101bwhen data signal51ais a high value (e.g., complementary data signal51bis a low value), thereby increasing a current to light emitting device120above the bias current value, and increasing optical power output from opto-electronic system10.

FIG. 2illustrates a dual-stage current supply200including a main current supply201and an auxiliary current supply202(cf. dual-stage current supply100, main current supply101and auxiliary current supply102), according to some embodiments. Dual-stage current supply200may also include a first current supply210configured to provide a bias current to a load220. Dual stage current supply200includes a main current supply201, which has a source terminal201acoupled in parallel with load220and configured to reduce a current value to load220below the bias current. Dual stage current supply200includes a termination resistor230(cf. termination resistor130) coupled in series with source terminal201aof the main current supply and configured to receive a current from source terminal201awhen source terminal201ais activated. In some embodiments, termination resistor230is coupled in series with source terminal201athrough a switch203athat is activated with data signal51a(cf. opto-electronic system10). In some embodiments, switch203amay include a transistor, such as a field-effect transistor (FET). For example, in some embodiments, switch203aincludes a positive channel FET (PFET) configured to be turned ‘on’ by a low value of data signal51a, and turned ‘off’ by a high value of data signal51a.

Dual stage current supply200also includes auxiliary current supply202having a sink terminal202bcoupled to termination resistor230at a common node261(cf common node161). Sink terminal202bis configured to maintain common node261at a common mode voltage (Vcm) when a current flows from source terminal201ato the sink terminal202bthrough termination resistor230. In some embodiments, load220is a vertical emitting laser diode, and common mode voltage261includes a middle value between a ‘one’ and a ‘zero’ state of the vertical emitting laser diode. In some embodiments, sink terminal202bis coupled to termination resistor230through a switch205bthat is activated with complementary data signal51b(cf opto-electronic system10). Switch205bmay include a transistor, such as a field-effect transistor (FET). For example, in some embodiments, switch203aincludes a negative channel FET (NFET) configured to be turned ‘on’ by a high value of complementary data signal51b, and turned ‘off’ by a low value of complementary data signal51b. In some embodiments, Vcmmay be driven and held fixed by a voltage source, at the cost of device real state and circuit complexity.

In some embodiments, dual stage current supply200includes a capacitor250coupled in parallel to sink terminal202bat common node261. In some embodiments, capacitor250is configured to provide a ground termination to an alternate current signal from termination resistor230. Accordingly, capacitor250and termination resistor230are configured to provide a time constant of multiple clock signals for load220, wherein a clock signal is defined by data signals51(e.g., a low-to-high or high-to-low transition). In some embodiments, capacitor250acts as an alternate-current (AC) ground for the resistor.

In some embodiments, load220represents the characteristic impendence of the channel being driven on a resistive load. In some embodiments, first current supply110may provide a direct-current (DC) bias current of about 6 mA for load220. As data signal51aswitches from low to high value, dual-stage current supply200modulates current around the DC bias point of 6 mA. Accordingly, a first portion of the current provided by main current supply101(Imain) is directed to load220and a second portion of Imainis directed toward resistor230, according to a resistor divider formed between resistor230and load220. In some embodiments, when resistor230is equal to load220, a current directed toward load220will be Imain/2. The current in resistor230may flow from common node261to an output node263, or in the opposite direction, depending of the value of data signals51.

In some embodiments, capacitor250supplies a current to hold Vcmconstant as Imainfluctuates between a pull up and a pull down condition, or when data signals51include a long string of high values (‘1's’) or low values (‘0's’). In some embodiments, this current may be provided by a large capacitor250. In some cases, capacitor250may be too large to be practical and a voltage regulator be included in the circuit to supply the Vcmvoltage. To alleviate these constraints, complementary data signal51bis configured to turn ‘on’ auxiliary current source202to supply current (Iaux) to resistor230and maintain Vcmconstant.

In some embodiments, auxiliary current supply202further comprises a source terminal202acoupled with resistor230at common node261. Source terminal202ais configured to provide a current, Iaux, to maintain the common node at Vcm, when the source terminal of the main current supply is deactivated and the current value to the load is above the bias current.

In some embodiments, main current supply201includes a sink terminal201b, coupled with resistor230at output node263. Accordingly, sink terminal201bmay be configured to provide a current through resistor230from common node261to output node263. This results in an increase of the current value to load220above the bias current when the source terminal of the main current supply is deactivated.

In some embodiments, main current supply201and auxiliary current supply202are configured such that a ratio between Imainand Iauxis proportional to a ratio between a resistor230(Rtem) and a resistance of load220(Rload), as follows:
ImainandIaux·Iaux/Imain=Rload/(Rtem+Rload)  (1)

In some embodiments, source terminal201aand sink terminal201bare coupled to a complementary channel set of field-effect transistors (e.g., PFET for source terminal201a, and NFET for sink terminal201b). Likewise, in some embodiments, source terminal202aand sink terminal202bmay include a complementary channel set of field effect transistors (e.g., PFET for source terminal202a, and NFET for sink terminal202b).

FIG. 3Aillustrates a partial view300A of dual-stage current supply200configured to pull a signal in an opto-electronic system (cf. opto-electronic system10) from a low state to a high state, according to some embodiments. Data signal51ais high, thereby turning switch203b(e.g., an NFET), and sink terminal201b, on. Complementary data signal51bis low, thereby turning switch205a(e.g., a PFET) on. Accordingly, auxiliary current supply202provides Iauxfrom source terminal202ato maintain Vcmfixed when source terminal201ais deactivated. Current Iauxflows through resistor230from common node261to output node263, thus pulling down the voltage of output node263(Vcmis held fixed). Accordingly, the voltage drop across load220increases, inducing a current value through load220to rise above the bias current provided by first current supply210. Capacitor250provides an AC ground for resistor230.

FIG. 3Billustrates a partial view300B of dual-stage current supply200configured to pull a signal in an opto-electronic system (cf. opto-electronic system10) from a high state to a low state, according to some embodiments. Data signal51ais low, thereby turning switch203a(e.g., a PFET) on. Complementary data signal51bis high, thereby turning switch205b(e.g., a PFET) on. Accordingly, main current supply201provides Iauxfrom source terminal201a, and sink terminal202bmaintains Vcmat a constant value when a portion of Imainflows through resistor230from output node263to common node261. Accordingly, the voltage of output node263is raised, thereby reducing a voltage drop across load220. This reduces a current value through load220below the bias current provided by first current supply210. Capacitor250provides an AC ground for resistor230.

FIG. 4illustrates a serial interface400for transducing an electrical signal411from a transmitter401into an optical signal412for a receiver402, according to some embodiments. Serial interface400includes an opto-electronic data link410(cf. opto-electronic data link10). In embodiments consistent with the present disclosure, opto-electronic data link410may include a light emitting device, a data channel configured to provide a data signal, a complementary data channel configured to provide a complementary signal to the data signal, a first current supply configured to provide a bias current to the light emitting device, and a main current supply having a source terminal coupled in parallel with the light emitting device and configured to reduce a current value to the light emitting device below the bias current (cf. light-emitting device120, data channel50, data signals51, first current supplies110and210, main current supplies101and201). Opto-electronic data link410may also include a termination resistor coupled in series with the source terminal of the main current supply and configured to receive a current from the source terminal of the main current supply when the source terminal of the main current supply is activated, and an auxiliary current supply having a sink terminal coupled to the termination resistor at a common node, as disclosed herein (cf. auxiliary current supplies102and202, and termination resistors130and230).

In some embodiments, serial interface400also includes a processor420configured to determine an auxiliary current form the auxiliary current supply and a main current from the main current supply based on an updated value of a resistance of the light emitting device and of the termination resistor.

In one aspect, a term field effect transistor (FET) may refer to any of a variety of multi-terminal transistors generally operating on the principals of controlling an electric field to control the shape and hence the conductivity of a channel of one type of charge carrier in a semiconductor material, including, but not limited to, a metal oxide semiconductor field effect transistor (MOSFET), a junction FET (JFET), a metal semiconductor FET (MESFET), a high electron mobility transistor (HEMT), a modulation doped FET (MODFET), an insulated gate bipolar transistor (IGBT), a fast reverse epitaxial diode FET (FREDFET), and an ion-sensitive FET (ISFET).