DISPLAY DEVICE

A display device includes a display panel including first and second areas each including a plurality of element areas and a peripheral area, a first light blocking pattern disposed on the display panel and overlapping the second area, and a second light blocking pattern disposed on the display panel, overlapping the second area, and disposed farther away from the display panel than the first light blocking pattern. Each of first, second and third element areas of the second area includes a plurality of light emitting areas and a non-light-emitting area disposed between the light emitting areas, the first light blocking pattern overlaps the non-light-emitting area of the second element area, and the second light blocking pattern overlaps the non-light-emitting area of the first element area and the non-light-emitting area of the third element area.

CROSS REFERENCE TO RELATED APPLICATION

This application claims priority from and the benefit of Korean Patent Application No. 10-2021-0134304, filed on Oct. 8, 2021, which is hereby incorporated by reference for all purposes as if fully set forth herein.

BACKGROUND

Field

Embodiments of the invention relate generally to a display device and more specifically, to a display device having various operating modes.

Discussion of the Background

Electronic devices, such as smartphones, tablet computers, notebook computers, car navigation units, smart televisions, etc., have been developed. The electronic devices include a display device to provide information to users.

The users have demanded the high quality of images that fits the usage situation of the display device. The users have demanded a brighter image at outdoors where natural light affects the quality of the images displayed by the display device. When personal information is displayed on the display device, the users have requested an image displayed with a narrow viewing angle.

SUMMARY

Applicant discovered that when a display device is operated in a private mode (e.g., a narrow viewing mode), the image quality of the display device is degraded due to, e.g., a color shift phenomenon.

Display devices constructed according to the principles of the invention are capable of preventing the image degradation when the display devices are operated in the narrow viewing mode by providing light blocking layers having specific patterns. Further, the display devices are capable of providing a display panel with a constant color purity at a specific viewing angle.

According to the above, the light blocking layer adjacent to a relatively small element area is disposed closer to the display panel than the light blocking layer adjacent to a relatively larger element area. Thus, the display device including the private mode, in which the color shift phenomenon is reduced, is provided.

According to an aspect of the invention, a display device includes a display panel including a first area and a second area, the first area including a first-first element area for emitting a first color light, a first-second element area for emitting a second color light, a first-third element area for emitting a third color light, and a first peripheral area, the second area including a second-first element area for emitting the first color light, a second-second element area for emitting the second color light, a second-third element area for emitting the third color light, and a second peripheral area, the second-second element area having a size smaller than a size of the second-first element area and a size of the second-third element area; a first light blocking pattern disposed on the display panel, the first light blocking pattern not overlapping the first area and overlapping the second-second element area of the second area; and a second light blocking pattern disposed on the display panel, the second light blocking pattern not overlapping the first area and overlapping the second-first element area and the second-third element area of the second area, wherein: each of the second-first element area, the second-second element area, and the second-third element area of the second area comprises a plurality of light emitting areas and a non-light-emitting area disposed between the plurality of light emitting areas, the first light blocking pattern overlaps the non-light-emitting area of the second-second element area of the second area, and the second light blocking pattern overlaps the non-light-emitting area of the second-first element area of the second area and the non-light-emitting area of the second-third element area of the second area, and wherein the first light blocking pattern and the second light blocking pattern are disposed on different layers.

The second light blocking pattern may be disposed farther away from the display panel than the first light blocking pattern.

The display device may further include an input sensor disposed on the display panel and including sensing electrodes overlapping the first peripheral area or the second peripheral area and at least one sensing insulating layer and a first cover layer disposed on an upper sensing insulating layer at an uppermost position of the at least one sensing insulating layer. The second light blocking pattern may be disposed on the first cover layer.

The first light blocking pattern may be disposed on the upper sensing insulating layer and covered by the first cover layer.

The display device may further include an additional cover layer disposed between the upper sensing insulating layer and the first cover layer to cover the sensing electrodes, and the first light blocking pattern is in contact with the sensing electrodes and covered by the additional cover layer.

The display device may further include a second cover layer disposed on the first cover layer and covering the second light blocking pattern, and the first cover layer and the second cover layer may include an organic material.

The first cover layer may have a thickness greater than a thickness of the second cover layer.

The display device may further include an input sensor disposed on the display panel and including sensing electrodes overlapping the first peripheral area or the second peripheral area and at least one sensing insulating layer, and the first light blocking pattern may be provided integrally with the sensing electrodes.

The first light blocking pattern may have a first line width greater than a line width of the sensing electrodes.

The sensing electrodes may overlap the non-light-emitting area of each of the second-first element area and the second-third element area of the second area.

The sensing electrodes overlapping the second light blocking pattern and the non-light-emitting area of each of the second-first element area and the second-third element area among the sensing electrodes may have a second line width smaller than the first line width.

The sensing electrodes overlapping the first area among the sensing electrodes may have a third line width smaller than the second line width.

The display panel may further include: first light emitting elements disposed in each of the first-first element area of the first area and the second-first element area of the second area, second light emitting elements disposed in each of the first-second element area of the first area and the second-second element area of the second area, and third light emitting elements disposed in each of the first-third element area of the first area and the second-third element area of the second area, wherein the first light emitting elements, the second light emitting elements, and the third light emitting elements may be for respectively providing lights having different colors, wherein each of the first light emitting elements, the second light emitting elements, and the third light emitting elements may include a first electrode, a second electrode, and a light emitting layer disposed between the first electrode and the second electrode, and wherein the display panel may further include a first pixel definition layer having openings defined therethrough to expose at least a portion of the first electrode of each of the first light emitting elements, the second light emitting elements, and the third light emitting elements.

The display panel may include a second pixel definition layer disposed on the first electrodes exposed through the openings of the first pixel definition layer and overlapping the non-light-emitting areas of the second area.

The display panel may further include an additional pixel definition layer disposed on the first electrodes exposed through the openings in the first area, and each of the first-first element area, the first-second element area, and the first-third element area of the first area comprises a plurality of light emitting areas separated from each other by the additional pixel definition layer.

The number of the plurality of light emitting areas of each of the second-first element area, the second-second element area, and the second-third element area of the second area may be equal to the number of the plurality of light emitting areas of each of the first-first element area, the first-second element area, and the first-third element area of the first area.

Each of the light emitting areas included in the third element area of the second area has a size smaller than a size of each of the light emitting areas included in the first element area of the second area and greater than a size of each of the light emitting areas included in the second element area of the second area.

The display panel may be to activate the first light emitting element, the second light emitting element, and the third light emitting element in the first area and the first light emitting element, the second light emitting element, and the third light emitting element in the second area in a first operation mode, and the display panel may be to deactivate the first light emitting element, the second light emitting element, and the third light emitting element in the first area and to activate the first light emitting element, the second light emitting element, and the third light emitting element in the second area in a second operation mode.

The plurality of light emitting areas respectively included in the first element area, the second element area, and the third element area of the second area may have a same size as each other.

The number of the light emitting areas in the second-second element area of the second area is smaller than the number of the light emitting areas in the second-first element area of the second area or the number of the light emitting areas in the second-third element area of the second area.

The display device may further include an anti-reflective layer disposed on the second light blocking pattern.

The display device may further include a first additional light blocking pattern overlapping the second peripheral area adjacent to the second-second element area of the second area and provided integrally with the first light blocking pattern.

The display device may further include a second additional light blocking pattern overlapping the second peripheral area disposed between the second-first element area and the second-third element area of the second area and provided integrally with the second light blocking pattern.

According to another aspect of the invention, a display device includes: a display panel operating in a first mode and a second mode and comprising a first area and a second area, the first area including a first-first light emitting area for emitting a first color light, a first-second light emitting area for emitting a second color light, a first-third light emitting area for emitting a third color light, a first-fourth light emitting area for emitting the second color light, and a first peripheral area, the second area including a plurality of second-first light emitting areas for emitting the first color light, a plurality of second-second light emitting areas for emitting the second color light, a plurality of second-third light emitting areas for emitting the third color light, a plurality of second-fourth light emitting areas for emitting the second color light, and a second peripheral area; a first light blocking pattern disposed on the second peripheral area of the second area of the display panel, the first light blocking pattern surrounding and exposing the plurality of second-second light emitting areas and the plurality of second-fourth light emitting areas when viewed in plan; and a second light blocking pattern disposed on the second peripheral area of the second area of the display panel, the second light blocking pattern surrounding and exposing the plurality of second-first light emitting areas and the plurality of second-third light emitting areas of the second area when viewed in plan, wherein the first light blocking pattern and the second light blocking pattern are disposed on different layers.

The first mode may be a wide viewing mode, and the second mode may be a narrow viewing mode.

The second light blocking pattern may be disposed at a higher level than the first light blocking pattern.

DETAILED DESCRIPTION

Hereinafter, embodiments will be described with reference to accompanying drawings.

FIG.1is a perspective view of a display device DD according to an embodiment.FIG.2is a cross-sectional view of the display device DD according to an embodiment.FIG.3is a plan view of a portion of a display panel according to an embodiment.FIG.4Ais a cross-sectional view taken along a line I-I′ ofFIG.3.FIG.4Bis a cross-sectional view taken along a line II-II′ ofFIG.3.

FIG.1is a perspective view of the display device DD according to an embodiment.

The display device DD may generate an image and may sense an external input. The display device DD may include a display area1000A and a non-display area1000N. A pixel PX may be disposed in the display area1000A. The pixel PX may include a first color pixel, a second color pixel, and a third color pixel, which generate lights having different colors.

An image may be displayed in the display area1000A. The display area1000A may include a plane defined by a first direction DR1 and a second direction DR2. The display area1000A may further include curved surfaces bent from at least two sides of the plane. However, the shape of the display area1000A should not be limited thereto or thereby. As an example, the display area1000A may include a flat surface. For example, the display area1000A may further include two or more curved surfaces, e.g., four curved surfaces respectively bent from four sides of the flat surface.

FIG.2is a cross-sectional view of the display device DD according to an embodiment. Referring toFIG.2, the display device DD may include a display panel100, an input sensor200, a light control layer300, an anti-reflective layer400, and a window500.

The display panel100may be a light emitting type display panel. For example, the display panel100may be an organic light emitting display panel, an inorganic light emitting display panel, a micro-LED display panel, a nano-LED display panel, or a quantum dot display panel. The display panel100may include a base layer110, a circuit layer120, a light emitting element layer130, and an encapsulation layer140.

The base layer110may provide a base surface on which the circuit layer120is disposed. The base layer110may be a rigid substrate or a flexible substrate that is bendable, foldable, or rollable. The base layer110may be a glass substrate, a metal substrate, or a polymer substrate, however, embodiments are not limited thereto or thereby. According to an embodiment, the base layer110may be an inorganic layer, an organic layer, or a composite material layer.

The base layer110may have a multi-layer structure. For instance, the base layer110may include a first synthetic resin layer, an inorganic layer having a single-layer structure or a multi-layer structure, and a second synthetic resin layer disposed on the inorganic layer having the single-layer structure or a multi-layer structure. Each of the first and second synthetic resin layers may include a polyimide-based resin, however, embodiments are not limited thereto.

The circuit layer120may be disposed on the base layer110. The circuit layer120may include an insulating layer, a semiconductor pattern, a conductive pattern, and a signal line. The circuit layer120may include a driving circuit of the pixel PX described with reference toFIG.1.

The light emitting element layer130may be disposed on the circuit layer120. The light emitting element layer130may include a light emitting element of the pixel PX described with reference toFIG.1. For example, the light emitting element may include an organic light emitting material, an inorganic light emitting material, an organic-inorganic light emitting material, a quantum dot, a quantum rod, a micro-LED, or a nano-LED.

The encapsulation layer140may be disposed on the light emitting element layer130. The encapsulation layer140may protect the light emitting element layer130from moisture, oxygen, and a foreign substance such as dust particles. The encapsulation layer140may include at least one inorganic layer. The encapsulation layer140may include a stack structure in which an inorganic layer, an organic layer, and an inorganic layer are sequentially stacked.

The input sensor200may be disposed on the display panel100. The input sensor200may sense an external input applied thereto from the outside. The external input may include a variety of external inputs, such as a user's body (e.g., finger), light, heat, pen, or pressure.

The input sensor200may be formed on the display panel100through successive processes. In this case, the input sensor200may be disposed directly on the display panel100. In the descriptions, the expression “a component A is disposed directly on a component B” means that no intervening elements are present between the component A and the component B. For example, an adhesive layer may not be disposed between the input sensor200and the display panel100.

The light control layer300may be disposed on the input sensor200. The light control layer300may control a transmission rate of a light provided from the light emitting element layer130to correspond to areas of the display panel100. The light control layer300will be described in detail later.

The anti-reflective layer400may be disposed on the light control layer300. The anti-reflective layer400may be coupled to the light control layer300by an adhesive layer. The adhesive layer may be a pressure sensitive adhesive (PSA) film or an optically clear adhesive (OCA).

The anti-reflective layer400may reduce a reflectance of an external light. The anti-reflective layer400may include an optical film. The optical film may include a polarizing film. The optical film may further include a retarder film. The retarder film may include at least one of a λ/2 retarder film or a λ/4 retarder film.

The window500may include at least one base layer. The base layer may be a glass substrate or a synthetic resin film. The window500may have a multi-layer structure. The window500may include a thin film glass substrate and a synthetic resin film disposed on the thin film glass substrate. The thin film glass substrate may be coupled to the synthetic resin film by an adhesive layer, and the adhesive layer and the synthetic resin film may be separated from the thin glass substrate to be replaced. The window500may further include a functional layer disposed on the base layer. The functional layer may include an anti-reflective layer, an anti-fingerprint layer, or the like.

FIG.3shows element areas included in different areas of the display panel100(refer toFIG.2). The display panel100may include a first area A1and a second area A2. The first area A1and the second area A2may be disposed spaced apart from each other in first and second diagonal directions CDR1and CDR2.

The first area A1may include a first-first element area AE1-B, a first-second element area AE1-G, a first-third element area AE1-R, and a first peripheral area NPXA1. The first peripheral area NPXA1may surround the first-first element area AE1-B, the first-second element area AE1-G, and the first-third element area AE1-R. The first peripheral area NPXA1may overlap at least a portion of an edge of each of the first-first element area AE1-B, the first-second element area AE1-G, and the first-third element area AE1-R when viewed in plan.

In the descriptions, each of the first-first element area AE1-B, the first-second element area AE1-G, and the first-third element area AE1-R may be defined as an area in which a first electrode included in light emitting elements for providing lights having different colors from each other is disposed.

As an example, the first-first element area AE1-B may be defined as an area in which a first electrode AE of a first-first light emitting element LD1-B for providing a light having a first color (e.g., blue) is disposed as shown inFIG.4A.

The first area A1of the display panel100may include a first-first light emitting area PXA-B1that is defined as an area from which the light generated by the first-first light emitting element LD1-B is substantially emitted.

The first-second element area AE1-G may be defined as an area in which a first electrode AE of a first-second light emitting element LD1-G (refer toFIG.8) for providing a light having a second color (e.g., green) is disposed.

According to an embodiment, two first-second element areas AE1-G may be provided in one first area A1. One first-second element area AE1-G may be spaced apart from the first-first element area AE1-B in the first diagonal direction CDR1and may be spaced apart from the first-third element area AE1-R in the second diagonal direction CDR2. The first-second element areas AE1-G may be spaced apart from each other in the first direction DR1. The other first-second element area AE1-G may be spaced apart from the first-first element area AE1-B in the second diagonal direction CDR2and may be spaced apart from the first-third element area AE1-R in the first diagonal direction CDR1.

The first area A1of the display panel100may include a first-second light emitting area PXA-G1that is defined as an area from which the light generated by the first-second light emitting element LD1-G is substantially emitted. One first area A1may include a plurality of first-second light emitting areas PXA-G1. The position and the number of the first-second light emitting areas PXA-G1may correspond to the position and the number of the first-second element areas AE1-G.

The first-third element area AE1-R may be defined as an area in which a first electrode AE of a first-third light emitting element LD1-R (refer toFIG.8) for providing a light having a third color (e.g., red) is disposed.

The first area A1of the display panel100may include a first-third light emitting area PXA-R1that is defined as an area from which the light generated by the first-third light emitting element LD1-R is substantially emitted.

In an embodiment, each of the first-first light emitting area PXA-B1, the first-second light emitting area PXA-G1, and the first-third light emitting area PXA-R1of the first area A1may be defined to correspond to a size of a corresponding opening among first openings OP1(refer toFIG.4A) defined through a pixel definition layer PDL (refer toFIG.4A) disposed in the first area A1.

The second area A2may include a second-first element area AE2-B, a second-second element area AE2-G, a second-third element area AE2-R, and a second peripheral area NPXA2. The second peripheral area NPXA2may surround the second-first element area AE2-B, the second-second element area AE2-G, the second-third element area AE2-R.

The second-first element area AE2-B may include a plurality of second-first light emitting areas PXA-B2, a first non-light-emitting area NCA-B, and a first boundary area BA-B.

The second-second element area AE2-G may include a plurality of second-second light emitting areas PXA-G2, a second non-light-emitting area NCA-G, and a second boundary area BA-G.

The second-third element area AE2-R may include a plurality of second-third light emitting areas PXA-R2, a third non-light-emitting area NCA-R, and a third boundary area BA-R.

The first boundary area BA-B, the second boundary area BA-G, and the third boundary area BA-R, which are respectively included in the second-first element area AE2-B, the second-second element areas AE2-G, the second-third element area AE2-R, may be defined as an area in which a portion of a first electrode AE (refer toFIG.4B) is covered by a first pixel definition layer PDL1described later.

In the descriptions, each of the second-first element area AE2-B, the second-second element area AE2-G, and the second-third element area AE2-R may be defined as an area in which the first electrode included in the light emitting elements for providing the lights having different colors from each other is provided.

As an example, the second-first element area AE2-B may be defined as an area in which a first electrode AE of a second-first light emitting element LD2-B for providing the light having the first color (e.g., blue) is disposed as shown inFIG.4B.

The second-first element area AE2-B of the display panel100may include the second-first light emitting areas PXA-B2defined as an area from which the light generated by the second-first light emitting element LD2-B is substantially emitted.

According to an embodiment, the second-first element area AE2-B may be provided as four second-first light emitting areas PXA-B2spaced apart from each other in the first direction DR1 and the second direction DR2 or in the first diagonal direction CDR1and the second diagonal direction CDR2with the first non-light-emitting area NCA-B interposed therebetween.

The second-second element area AE2-G may be defined as an area in which a first electrode AE of a second-second light emitting element LD2-G (refer toFIG.9) for providing the light having the second color (e.g., green) is disposed.

According to an embodiment, two second-second element areas AE2-G may be provided in one second area A2. The second-second element areas AE2-G may be spaced apart from each other in the first direction DR1.

One second-second element area AE2-G may be spaced apart from the second-first element area AE2-B in the first diagonal direction CDR1and may be spaced from the second-third element area AE2-R in the second diagonal direction CDR2. The other second-second element area AE2-G may be spaced apart from the second-first element area AE2-B in the second diagonal direction CDR2and may be spaced apart from the second-third element area AE2-R in the first diagonal direction CDR1.

The second-second element area AE2-G of the display panel100may include the second-second light emitting areas PXA-G2defined as an area from which the light generated by the second-second light emitting element LD2-G is substantially emitted.

The second-second light emitting areas PXA-G2may be grouped into two groups. The second-second light emitting areas PXA-G2of a first group may overlap one second-second element area AE2-G, and the second-second light emitting areas PXA-G2of a second group may overlap the other second-second element area AE2-G.

Each of the first group and the second group may include four second-second light emitting areas PXA-G2.

The second-second light emitting areas PXA-G2of the first group may be spaced apart from the second-first light emitting areas PXA-B2in the first diagonal direction CDR1and may be spaced apart from the second-third light emitting areas PXA-R2in the second diagonal direction CDR2.

The second-second light emitting areas PXA-G2of the second group may be spaced apart from the second-second light emitting areas PXA-G2of the first group in the first direction DR1, may be spaced apart from the second-first light emitting areas PXA-B2in the second diagonal direction CDR2, and may be spaced apart from the second-third light emitting areas PXA-R2in the first diagonal direction CDR1.

The second-second light emitting areas PXA-G2included in each of the first and second groups may be provided as four second-second light emitting areas PXA-G2spaced apart from each other with the second non-light-emitting area NCA-G interposed therebetween in the first direction DR1 and the second direction DR2 or in the first diagonal direction CDR1and the second diagonal direction CDR2.

The second-third element area AE2-R may be defined as an area in which a first electrode AE of a second-third light emitting element LD2-R (refer toFIG.9) for providing the light having the third color is disposed. The first color, the second color, and the third color of the lights may be different from each other.

The second-third element area AE2-R of the display panel100may include the second-third light emitting areas PXA-R2defined as an area from which the light generated by the second-third light emitting element LD2-R is substantially emitted.

The second-third element area AE2-R may be provided as four second-third light emitting areas PXA-R2spaced apart from each other with the third non-light-emitting area NCA-R interposed therebetween in the first direction DR1 and the second direction DR2 or in the first diagonal direction CDR1and the second diagonal direction CDR2.

According to an embodiment, a size of the first-first element area AE1-B, which provides the light having the first color, in the first area A1, may be smaller than a size of the second-first element area AE2-B, which provides the light having the first color, in the second area A2.

In addition, a size of the first-second element area AE1-G, which provides the light having the second color, in the first area A1, may be smaller than a size of the second-second element area AE2-G, which provides the light having the second color, in the second area A2, and a size of the first-third element area AE1-R, which provides the light having the third color, in the first area A1, may be smaller than a size of the second-third element area AE2-R, which provides the light having the third color, in the second area A2.

According to an embodiment, a size of each of the second-third light emitting areas PXA-R2may be greater than a size of each of the second-second light emitting areas PXA-G2and may be smaller than a size of each of the second-first light emitting areas PXA-B2.

The first area A1and the second area A2may be provided in plural in the display area1000A (refer toFIG.1). The first areas A1and the second areas A2may be arranged spaced apart from each other in the first diagonal direction CDR1and the second diagonal direction CDR2.

The display device DD (refer toFIG.1) may be operated in two modes. A first operation mode may be a state in which the first-first element area AE1-B, the first-second element areas AE1-G, and the first-third element area AE1-R included in the first areas A1of the display panel100and the second-first element area AE2-B, the second-second element areas AE2-G, the second-third element area AE2-R included in the second areas A2of the display panel100are activated to provide the light to a corresponding light emitting area. A second operation mode may be a state in which the first-first element area AE1-B, the first-second element areas AE1-G, and the first-third element area AE1-R included in the first area A1are deactivated and only the second-first element area AE2-B, the second-second element areas AE2-G, the second-third element area AE2-R included in the second area A2are activated to provide the light to the corresponding light emitting area.

Accordingly, a size of the activated light emitting areas in the second operation mode may be relatively smaller than a size of the activated light emitting areas in the first operation mode, and thus, a low pixel image may be provided to a user.

The first operation mode may correspond to a mode in which the display device DD is normally operated. The second operation mode may be used when using the display device DD for a specific purpose. As an example, when the display device is operated in the second mode, the display area is not easily seen by people near the display area but is recognized only by the user. As a result, exposure of personal information of the user may be prevented or minimized.

When the user watches the display device DD from a side, a portion of each of the second-first light emitting area PXA-B2, the second-second light emitting area PXA-G2, and the second-third light emitting area PXA-R2disposed in the second area A2may be covered by a light blocking portion (described later) disposed thereabove. In a case where the second-first light emitting area PXA-B2, the second-second light emitting area PXA-G2, and the second-third light emitting area PXA-R2have different sizes, sizes of the areas covered by the light blocking portion may be different from each other, and as a result, a color shift phenomenon may occur at a specific angle.

FIG.4Ashows a cross-section of an area overlapping the first-first element area AE1-B in the first area A1as a representative example. Accordingly, details of the first-first element area described with reference to the cross-section ofFIG.4Amay be commonly applied to the first-second element area AE1-G and the first-third element area AE1-R of the first area A1.

FIG.4Bshows a cross-section of an area overlapping the second-first element area AE2-B in the second area A2. Accordingly, details of the second-first element area described with reference to the cross-section ofFIG.4Bmay be commonly applied to the second-second element area AE2-G and the second-third element area AE2-R of the second area A2.

FIG.4Ashows the first-first light emitting element LD1-B and a transistor TFT connected to the first-first light emitting element LD1-B, andFIG.4Bshows the second-first light emitting element LD2-B and a transistor TFT connected to the second-first light emitting element LD2-B. The transistor TFT may be one of a plurality of transistors included in the driving circuit of the pixel PX (refer toFIG.1). In an embodiment, the transistor TFT will be described as a silicon transistor, however, according to an embodiment, the transistor TFT may be a metal oxide transistor. Hereinafter, common configurations of the first area A1and the second area A2will be described together for descriptive convenience.

The base layer110may correspond to the base layer110described with reference toFIG.3. A barrier layer10brmay be disposed on the base layer110. The barrier layer10brmay prevent a foreign substance from entering or permeating thereinto from the outside. The barrier layer10brmay include at least one inorganic layer. The barrier layer10brmay include a silicon oxide layer and a silicon nitride layer. Each of the silicon oxide layer and the silicon nitride layer may be provided in plural, and the silicon oxide layers and the silicon nitride layers may be alternately stacked with each other.

A light shielding electrode BMLa may be disposed on the barrier layer10br. The light shielding electrode BMLa may include a metal material. The light shielding electrode BMLa may include molybdenum (Mo), an alloy including molybdenum (Mo), titanium (Ti), or an alloy including titanium (Ti), which has a good heat resistance. The light shielding electrode BMLa may receive a bias voltage.

The light shielding electrode BMLa may prevent an electric potential, which is caused by a polarization phenomenon, from exerting influence on the silicon transistor TFT. The light shielding electrode BMLa may prevent an external light from reaching the silicon transistor TFT. According to an embodiment, the light shielding electrode BMLa may be a floating electrode isolated from other electrodes or lines.

A buffer layer10bfmay be disposed on the barrier layer10br. The buffer layer10bfmay prevent metal atoms or impurities from being diffused to a semiconductor pattern SC1disposed thereon. The buffer layer10bfmay include at least one inorganic layer. The buffer layer10bfmay include a silicon oxide layer and a silicon nitride layer.

The semiconductor pattern SC1may be disposed on the buffer layer10bf. The semiconductor pattern SC1may include a silicon semiconductor. As an example, the semiconductor pattern SC1may include amorphous silicon or polycrystalline silicon. For example, the semiconductor pattern SC1may include low temperature polycrystalline silicon.

The semiconductor pattern may include a first region having a relatively high conductivity and a second region having a relatively low conductivity. The first region may be doped with an N-type dopant or a P-type dopant. A P-type transistor may include a doped region doped with the P-type dopant, and an N-type transistor may include a doped region doped with the N-type dopant. The second region may be a non-doped region or a region doped at a concentration lower than that of the first region.

The first region may have a conductivity greater than that of the second region and may substantially serve as an electrode or a signal line. The second region may substantially correspond to an active area (e.g., a channel) of the transistor. In other words, a portion of the semiconductor pattern may be the active area of the transistor, another portion of the semiconductor pattern may be a source area or a drain area of the transistor, and the other portion of the semiconductor pattern may be a connection electrode or a connection signal line.

A source area SE1(e.g., a source), the active area AC1(e.g., a channel), and a drain area DE1(e.g., a drain) of the transistor TFT may be formed from the semiconductor pattern. The source area SE1and the drain area DE1may extend in opposite directions to each other from the active area AC1in a cross-section.

A first insulating layer10may be disposed on the buffer layer10bf. The first insulating layer10may commonly overlap the pixels PX (refer toFIG.1) and may cover the semiconductor pattern. The first insulating layer10may include an inorganic layer and/or an organic layer and may have a single-layer structure or a multi-layer structure.

The inorganic layer may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

In an embodiment, the first insulating layer10may have a single-layer structure of a silicon oxide layer. Not only the first insulating layer10, but also an insulating layer of the circuit layer120described later may be an inorganic layer and/or an organic layer and may have a single-layer structure or a multi-layer structure. The inorganic layer may include at least one of the above-mentioned materials, however, embodiments should not be limited thereto or thereby.

A gate GT1of the transistor TFT may be disposed on the first insulating layer10. The gate GT1may be a portion of a metal pattern. The gate GT1may overlap the active area AC1. The gate GT1may be used as a mask in a process of doping the semiconductor pattern. The gate GT1may include titanium (Ti), silver (Ag), an alloy including silver (Ag), molybdenum (Mo), an alloy including molybdenum (Mo), aluminum (Al), an alloy including aluminum (Al), aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), indium tin oxide (ITO), indium zinc oxide (IZO), or the like, however, embodiments should not be particularly limited.

A second insulating layer20may be disposed on the first insulating layer10and may cover the gate GT1. A third insulating layer30may be disposed on the second insulating layer20. A storage electrode CT may be disposed between the second insulating layer20and the third insulating layer30. The storage electrode CT may overlap the gate GT1. The gate GT1and the storage electrode CT may form a capacitor included in the driving circuit of the pixel PX (refer toFIG.1).

A first connection electrode CNE1may be disposed on the third insulating layer30. The first connection electrode CNE1may be connected to the drain area DE1of the transistor TFT via a contact hole defined through the first insulating layer10, the second insulating layer20, and the third insulating layer30.

A fourth insulating layer40may be disposed on the third insulating layer30. A second connection electrode CNE2may be disposed on the fourth insulating layer40. The second connection electrode CNE2may be connected to the first connection electrode CNE1via a contact hole defined through the fourth insulating layer40. A fifth insulating layer50may be disposed on the fourth insulating layer40and may cover the second connection electrode CNE2. The stack structure of the first insulating layer10to the fifth insulating layer50is one example. For example, additional conductive layer and insulating layer may be disposed in addition to the first insulating layer10to fifth insulating layer50.

Each of the fourth insulating layer40and the fifth insulating layer50may include an organic layer. As an example, the organic layer may include a general-purpose polymer such as benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethylmethacrylate (PMMA), or polystyrene (PS), a polymer derivative having a phenolic group, an acrylic-based polymer, an imide-based polymer, an aryl ether-based polymer, an amide-based polymer, a fluorine-based polymer, a p-xylene-based polymer, a vinyl alcohol-based polymer, or blends thereof.

The light emitting elements LD1-B and LD2-B may include the first electrode AE (e.g., a pixel electrode), a light emitting layer EL, and a second electrode CE (e.g., a common electrode). The first electrode AE may be disposed on the fifth insulating layer50. The first electrode AE may be a semi-transmissive electrode, a transmissive electrode, or a reflective electrode. According to an embodiment, the first electrode AE may include a reflective layer formed of Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, or compounds thereof and a transparent or semi-transparent electrode layer formed on the reflective layer. The transparent or semi-transparent electrode layer may include at least one selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium oxide (In2O3), and aluminum-doped zinc oxide (AZO). For instance, the first electrode AE may have a stack structure of ITO/Ag/ITO.

According to an embodiment, the first area A1may include the pixel definition layer PDL. The pixel definition layer PDL may be disposed on the fifth insulating layer50. The pixel definition layer PDL may be provided with the first opening OP1defined therethrough to expose at least a portion of the first electrode AE of the light emitting element LD1-B. The pixel definition layer PDL of the first area A1may cover a portion of the first electrode AE.

As described above, the first-first light emitting area PXA-B1of the first area A1, from which the light generated by the light emitting element LD1-B is provided, may be determined by a size of the first opening OP1defined through the pixel definition layer PDL of the first area A1. The first peripheral area NPXA1defined adjacent to the first-first light emitting area PXA-B1may be defined as an area overlapping the pixel definition layer PDL of the first area A1.

The second area A2may include a first pixel definition layer PDL1and the second pixel definition layer PDL2. The first pixel definition layer PDL1and the second pixel definition layer PDL2may be disposed on the fifth insulating layer50. The first pixel definition layer PDL1may be provided with a second opening OP2defined therethrough to expose at least a portion of the first electrode AE of the second-first light emitting element LD2-B. The first pixel definition layer PDL1of the second area A2may cover a portion of the first electrode AE.

The second pixel definition layer PDL2may be disposed on the first electrode AE exposed through the second opening OP2without being covered by the first pixel definition layer PDL1. The second pixel definition layer PDL2may be disposed on the first electrode AE and may define the first non-light-emitting area NCA-B ofFIG.3. Accordingly, the second-first light emitting areas PXA-B2may be disposed on one first electrode AE disposed in the second area A2of the display panel100. Each of the second-first light emitting areas PXA-B2may be disposed adjacent to a main non-light-emitting area NCA-M and the first non-light-emitting area NCA-B. The main non-light-emitting area NCA-M may overlap the first pixel definition layer PDL1, and the first non-light-emitting area NCA-B may overlap the second pixel definition layer PDL2. The main non-light-emitting area NCA-M may overlap the second peripheral area NPXA2.

According to an embodiment, a boundary between the light emitting areas and the non-light-emitting areas in the second area A2may be determined by light blocking patterns described later.

For example, a hole control layer may be disposed between the first electrode AE and the light emitting layer EL. The hole control layer may include a hole transport layer and may further include a hole injection layer. An electron control layer may be disposed between the light emitting layer EL and the second electrode CE. The electron control layer may include an electron transport layer and may further include an electron injection layer.

The encapsulation layer140may be disposed on the light emitting elements LD1-B and LD2-B. The encapsulation layer140may include an inorganic layer141, an organic layer142, and an inorganic layer143, which are sequentially stacked, however, layers included in the encapsulation layer140should not be limited thereto or thereby.

The inorganic layers141and143may protect the light emitting element layer130from moisture and oxygen, and the organic layer142may protect the light emitting element layer130from a foreign substance such as dust particles. The inorganic layers141and143may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The organic layer may include at least one of an acrylic-based resin, a methacrylic-based resin, a polyisoprene-based resin, a vinyl-based resin, an epoxy-based resin, a urethane-based resin, a cellulose-based resin, a siloxane-based resin, a polyimide-based resin, a polyamide-based resin, and a perylene-based resin.

FIG.5is a plan view of the input sensor200according to an embodiment.

Referring toFIG.5, the input sensor200may include a sensing area200A and a non-sensing area200NA adjacent to the sensing area200A. The sensing area200A and the non-sensing area200NA may correspond to the display area1000A and the non-display area1000N shown inFIG.1, respectively.

The input sensor200may include first sensing electrodes E1-1to E1-5and second sensing electrodes E2-1to E2-4, which are disposed in sensing area200A and are insulated from each other while intersecting each other. The external input may be sensed by calculating a variation in mutual capacitance formed between the first sensing electrodes E1-1to E1-5and the second sensing electrodes E2-1to E2-4.

The input sensor200may include first signal lines SL1disposed in the non-sensing area200NA and electrically connected to the first sensing electrodes E1-1to E1-5and second signal lines SL2disposed in the non-sensing area200NA and electrically connected to the second sensing electrodes E2-1to E2-4.

Each of the first sensing electrodes E1-1to E1-5and the second sensing electrodes E2-1to E2-4may include a plurality of conductive lines intersecting each other. Each of the first sensing electrodes E1-1to E1-5and the second sensing electrodes E2-1to E2-4may include mesh lines. The mesh lines may be provided with a plurality of openings defined therethrough to overlap the light emitting areas included in the first area A1and the second area A2.

One of the first sensing electrodes E1-1to E1-5and the second sensing electrodes E2-1to E2-4may be provided integrally. In an embodiment, the first sensing electrodes E1-1to E1-5are integrally provided. The first sensing electrodes E1-1to E1-5may include sensing portions SP1and intermediate portions CP1.

Each of the second sensing electrodes E2-1to E2-4may include sensing patterns SP2and bridge patterns CP2(e.g., connection patterns). Two sensing patterns SP2adjacent to each other may be connected to two bridge patterns CP2via a contact hole CH-I defined through a second sensing insulating layer IL2(refer toFIG.8), however, the number of the bridge patterns should not be particularly limited.

FIG.6Ais an enlarged plan view of an area AA′ ofFIG.5.FIG.6Bis an enlarged plan view of an area AA′ ofFIG.5.FIG.7is an enlarged plan view of an area AA′ ofFIG.5.FIG.8is a cross-sectional view taken along a line III-III′ ofFIGS.6B and7.FIG.9is a cross-sectional view taken along a line IV-IV′ ofFIGS.6B and7.

Referring toFIG.6A, the sensing patterns SP2among the first sensing electrodes E1-1to E1-5(refer toFIG.5) and the second sensing electrodes E2-1to E2-4(refer toFIG.5) may include mesh lines MSL extending in the first diagonal direction CDR1and the second diagonal direction CDR2.

In an embodiment, the mesh lines MSL may include a first line S1and a second line S2. The first line S1may extend in the first diagonal direction CDR1, and the second line S2may extend in the second diagonal direction CDR2. The first lines S1and the second lines S2may be patterns that are integrally provided with each other and extending from each other, however, for the convenience of explanation, the first lines S1and the second lines S2will be described separately from each other.

As the first line S1and the second line S2are disposed to cross each other, the mesh lines MSL may be provided with mesh openings MS-OP1. In an embodiment, the mesh openings MS-OP1may have the substantially same shape as each other.

In an embodiment, each of the first-first light emitting area PXA-B1, first-second light emitting area PXA-G1, and the first-third light emitting area PXA-R1of the first area A1may be surrounded by a corresponding opening among the mesh openings MS-OP1. Accordingly, each of the mesh openings MS-OP1overlapping the first area A1may surround one light emitting area.

The second-first light emitting area PXA-B2, the second-second light emitting area PXA-G2, and the second-third light emitting area PXA-R2of the second area A2may be provided such that light emitting areas for providing the substantially same color are surrounded by one mesh opening MS-OP1. For example, four second-first light emitting areas PXA-B2may be surrounded by one mesh opening MS-OP1, four second-second light emitting areas PXA-G2of the first group may be surrounded by another mesh opening MS-OP1, four second-second light emitting areas PXA-G2of the second group may be surrounded by another mesh opening MS-OP1, and four second-third light emitting areas PXA-R2may be surrounded by the other mesh opening MS-OP1.

FIG.6Bshows an arrangement relationship between the sensing electrodes and the light emitting areas disposed in the first area A1and the second area A2when viewed in plan, andFIG.7shows an arrangement relationship between first and second light blocking portions BM1and BM2disposed on the light control layer300and the light emitting areas disposed in the first area A1and the second area A2.

FIG.8is a cross-sectional view taken along a line III-III′ ofFIGS.6B and7in a state where the display panel100, the input sensor200, the light control layer300, and the anti-reflective layer400are stacked, andFIG.9is a cross-sectional view taken along a line IV-IV′ ofFIGS.6B and7in a state where the display panel100, the input sensor200, the light control layer300, and the anti-reflective layer400are stacked.FIG.10is a graph showing a luminance reduction ratio of the light emitting area according to a distance between the light emitting layer and the light blocking pattern.

Referring toFIG.6B, the sensing patterns SP2among the first sensing electrodes E1-1to E1-5(refer toFIG.5) and the second sensing electrodes E2-1to E2-4(refer toFIG.5) may include the mesh lines MSL extending in the first diagonal direction CDR1and the second diagonal direction CDR2.

The mesh lines MSL may include first mesh lines MSL-1in an area overlapping the first area A1and second mesh lines MSL-2in an area overlapping the second area A2.

The first mesh lines MSL-1may include a first-first line S1and a first-second line S2. The first-first line S1may extend in the first diagonal direction CDR1, and the first-second line S2may extend in the second diagonal direction CDR2.

The first-first line S1and the first-second line S2may be provided with first mesh openings MS-OP1defined therethrough to overlap the first-first light emitting area PXA-B1, the first-second light emitting area PXA-G1, and the first-third light emitting area PXA-R1included in the first area A1.

Accordingly, the light from the first-first light emitting area PXA-B1, the first-second light emitting area PXA-G1, and the first-third light emitting area PXA-R1may be emitted with being influence by the first-first line S1and the first-second line S2.

In an embodiment, each of the first-first light emitting area PXA-B1, the first-second light emitting area PXA-G1, and the first-third light emitting area PXA-R1of the first area A1may be surrounded by a corresponding opening among the first mesh openings MS-OP1. Accordingly, each of the first mesh openings MS-OP1overlapping the first area A1may surround one light emitting area.

The second mesh lines MSL-2may include a second-first line M1and a second-second line M2. The second-first line M1may extend in the first diagonal direction CDR1, and the second-second line M2may extend in the second diagonal direction CDR2.

The second-first line M1and the second-second line M2may be provided with second mesh openings MS-OP2defined therethrough to overlap the second-first light emitting area PXA-B2, the second-second light emitting area PXA-G2, and the second-third light emitting area PXA-R2included in the second area A2.

Accordingly, the light from the second-first light emitting area PXA-B2, the second-second light emitting area PXA-G2, and the second-third light emitting area PXA-R2may be emitted without being influenced by the second-first line M1and the second-second line M2. In an embodiment, each of the first mesh openings MS-OP1has a size greater than a size of each of the second mesh openings MS-OP2.

In an embodiment, each of the second-first light emitting area PXA-B2, the second-second light emitting area PXA-G2, and the second-third light emitting area PXA-R2of the second area A2may be surrounded by a corresponding opening among the second mesh openings MS-OP2. Accordingly, each of the second mesh openings MS-OP2overlapping the second area A2may surround one light emitting area.

Referring toFIG.7, the first light blocking portion BM1and the second light blocking portion BM2, which are disposed on different layers from each other, may be disposed in the second area A2. InFIG.7, mesh lines that do not overlap the first light blocking portion BM1and the second light blocking portion BM2among the mesh lines MSL shown inFIG.6Bare shown by a dotted line. In addition, the first light blocking portion BM1and the second light blocking portion BM2, which are disposed on different layers from each other, are shown by different hatching.

The first light blocking portion BM1and the second light blocking portion BM2may be disposed only in the second area A2and may not overlap the first area A1. According to an embodiment, the first light blocking portion BM1may be disposed adjacent to light emitting areas having the smallest size among the light emitting areas included in the second area A2.

The first light blocking portion BM1may disposed to surround the second-second light emitting areas PXA-G2. The second light blocking portion BM2may be disposed to surround the second-first light emitting areas PXA-B2and the second-third light emitting areas PXA-R2. According to an embodiment, a material for the first light blocking portion BM1and the second light blocking portion BM2should not be particularly limited as long as the material may absorb the light.

The display panel100, the input sensor200, the light control layer300, and the anti-reflective layer400shown inFIGS.8and9may correspond to the display panel100, the input sensor200, the light control layer300, and the anti-reflective layer400described with reference toFIGS.2,4A, and4B.

The input sensor200may include a first sensing insulating layer IL1, the second sensing insulating layer IL2, and a third sensing insulating layer IL3. The first sensing insulating layer IL1may be disposed on the encapsulation layer140.

Among the second sensing electrodes E2-1to E2-4described with reference toFIG.5, the bridge patterns CP2may be disposed on the first sensing insulating layer IL1.

The second sensing insulating layer IL2may be disposed on the first sensing insulating layer IL1. Among the first sensing electrodes E1-1to E1-5and the second sensing electrodes E2-1to E2-4described with reference toFIG.5, the sensing patterns SP2may be disposed on the second sensing insulating layer IL2.

The sensing patterns SP2may be connected to corresponding sensing patterns SP2via a contact hole defined through the second sensing insulating layer IL2. The third sensing insulating layer IL3may be disposed on the second sensing insulating layer IL2. The first, second, and third sensing insulating layers IL1, IL2, and IL3may include an inorganic material.

Hereinafter, sensing electrodes CL described with reference toFIGS.8and9may correspond to one of the sensing patterns SP2of the first sensing electrodes E1-1to E1-5and the second sensing electrodes E2-1to E2-4.

The light control layer300may include a first cover layer OC1, a second cover layer OC2, the first light blocking portion BM1, and the second light blocking portion BM2. The first cover layer OC1may be disposed on the third sensing insulating layer IL3of the input sensor200. Each of the first cover layer OC1and the second cover layer OC2may include an organic material. As an example, at least one of the first cover layer OC1and the second cover layer OC2may include at least one of an acrylic-based resin, a methacrylic-based resin, a polyisoprene-based resin, a vinyl-based resin, an epoxy-based resin, a urethane-based resin, a cellulose-based resin, a siloxane-based resin, a polyimide-based resin, a polyamide-based resin, and a perylene-based resin.

In an embodiment, the first cover layer OC1may have a first thickness TH1greater than a second thickness TH2of the second cover layer OC2. As an example, the first thickness TH1of the first cover layer OC1may be within a range from about 4 μm to about 9 um, and the second thickness TH2of the second cover layer OC2may be within a range from about 0.5 μm to about 3 μm.

Referring toFIG.8, the first light blocking portion BM1and the second light blocking portion BM2may not overlap the first area A1. Accordingly, the first-first light emitting area PXA-B1, the first-second light emitting area PXA-G1, and the first-third light emitting area PXA-R1, from which the lights generated by the first-first element area AE1-B, the first-second element areas AE1-G, and the first-third element area AE1-R are emitted, may be defined by sizes of corresponding openings among the first openings OP1defined through the pixel definition layer PDL. In addition, the first peripheral area NPXA1of the first area A1may overlap the pixel definition layer PDL.

Referring toFIG.9, the first light blocking portion BM1and the second light blocking portion BM2may be disposed only in the second area A2. In an embodiment, the first light blocking portion BM1may be disposed on the third sensing insulating layer IL3and may be covered by the first cover layer OC1. The second light blocking portion BM2may be disposed on the first cover layer OC1and may be covered by the second cover layer OC2. For example, the first light blocking portion BM1and the second light blocking portion BM2may be disposed on different layers, respectively. For example, the first light blocking portion BM1and the second light blocking portion BM2at different levels from the base layer110of the display panel100. For example, the second light blocking portion BM2may be farther away from the display panel100than the first light blocking portion BM1in a vertical direction (e.g., a third direction DR3).

The first light blocking portion BM1may include a first light blocking pattern B1-1and a first additional light blocking pattern B1-2. The first light blocking pattern B1-1may be disposed on the second pixel definition layer PDL2disposed on the first electrode AE of the second-second light emitting element LD2-G. Accordingly, the first light blocking pattern B1-1may be disposed in the second-second element area AE2-G. The first light blocking pattern B1-1may define the second non-light-emitting area NCA-G of the second-second element area AE2-G.

The first additional light blocking pattern B1-2may be disposed on the first pixel definition layer PDL1disposed between the second-first light emitting element LD2-B and the second-second light emitting element LD2-G and the first pixel definition layer PDL1disposed between the second-third light emitting element LD2-R and the second-second light emitting element LD2-G. Accordingly, the first additional light blocking pattern B1-2may define the main non-light-emitting area NCA-M adjacent to the second non-light-emitting area NCA-G.

In an embodiment, the first light blocking pattern B1-1and the first additional light blocking pattern B1-2may include the substantially same material and may be provided integrally with each other as a single pattern.

The second light blocking portion BM2may include a second light blocking pattern B2-1and a second additional light blocking pattern B2-2. The second light blocking pattern B2-1may be disposed on the second pixel definition layer PDL2disposed on the first electrode AE of the second-first light emitting element LD2-B and the first electrode AE of the second-third light emitting element LD2-R. Accordingly, the second light blocking pattern B2-1may be disposed on the second-first element area AE2-B and the second-third element area AE2-R. Accordingly, the second light blocking pattern B2-1may define the first non-light-emitting area NCA-B and the third non-light-emitting area NCA-R.

The second additional light blocking pattern B2-2may be disposed on the first pixel definition layer PDL1disposed between the second-first light emitting element LD2-B and the second-third light emitting element LD2-R (e.g., in a horizontal direction). Accordingly, the second additional light blocking pattern B2-2may define the main non-light-emitting area NCA-M between the first non-light-emitting area NCA-B and the third non-light-emitting area NCA-R.

The second light blocking pattern B2-1and the second additional light blocking pattern B2-2may include the substantially same material and may be integrally provided with each other as a single pattern.

The second-first light emitting area PXA-B2, the second-second light emitting area PXA-G2, and the second-third light emitting area PXA-R2, the first non-light-emitting area NCA-B, the second non-light-emitting area NCA-G, and the third non-light-emitting area NCA-R, and the main non-light-emitting area NCA-M of the second area A2may be defined by positions at which the first light blocking portion BM1and the second light blocking portion BM2including a light blocking material are disposed.

Definitions of the first non-light-emitting area NCA-B, the second non-light-emitting area NCA-G, the third non-light-emitting area NCA-R, and the main non-light-emitting area NCA-M of the second area A2, which will be described hereinafter, are the same as the details described above for descriptive convenience.

According to an embodiment, when the display device DD (refer toFIG.1) is operated in the second operation mode, the display area1000A (refer toFIG.1) may not be visible to people near the display device DD since the display device DD may include the first light blocking portion BM1and the second light blocking portion BM2disposed in the second area A2. Accordingly, the display device DD with improved performance in the private mode may be provided.

According to an embodiment, the second-second element area AE2-G may have a relatively smaller size than that of the second-first element area AE2-B and the second-third element area AE2-R. The first light blocking portion BM1may be disposed in an area adjacent to the second-second element area AE2-G, and the second light blocking portion BM2may be disposed in the second-first element area AE2-B and the second-third element area AE2-R. The second light blocking portion BM2may be placed relatively far from the display panel100than the first light blocking portion BM1.

Since the first and second light blocking portions BM1and BM2are disposed in the second area A2, the size of the light blocking area of the second-first element area AE2-B, the second-second element areas AE2-G, the second-third element area AE2-R included in second area A2may increase as the viewing angle at which the user looks at the display device DD from the side increases.

Different from the embodiments, in a case of a comparative embodiment in which the light blocking portion disposed in the second area A2has the substantially same distance from the display panel100regardless of the size of the element area, the second-second element area AE2-G, which has the smallest area, has a relatively greater light blocking rate (which is defined as a ratio of the size of the area covered by the light blocking portion to the size of the element area) than that of the second-first element area AE2-B and the second-third element area AE2-R at the same viewing angle, and accordingly, an amount of the second color light emitted from the second-second element area AE2-G is reduced. As a result, the color shift phenomenon occurs in the second area A2at a specific angle.

As an example, in a case where the first color light, the second color light, and the third color light, respectively, generated from the second-first element area AE2-B, the second-second element area AE2-G, and the second-third element area AE2-R are the blue, green, and red colors, respectively, in the comparative example, the amount of emission of the second color light is reduced in the second area A2, and thus, the light having a pinkish color is emitted in the second area A2, that is, a pinkish phenomenon occurs.

According to an embodiment, the first light blocking portion BM1is disposed in an area adjacent to the second-second element area AE2-G having the smallest size, and the second light blocking portion BM2is disposed in an area adjacent to the second-first element area AE2-B and the second-third element area AE2-R. Accordingly, the reduction of the emission rate of the second color light in the second area A2may be prevented. Hereinafter, the effect of the embodiments will be described in more detail with reference toFIG.10.

FIG.10is a graph showing a variation of a luminance ratio of the element area with a viewing angle for a distance between the element area and the light blocking portion.

The distance between the element area and the light blocking portion may decrease in the order of a first graph G1, a second graph G2, a third graph G3, and a fourth graph G4. The reduction in the luminance ratio of the element area may decrease from the first graph G1to the fourth graph G4in the same viewing angle. As an example, when the viewing angle is about +15 degrees in the first graph G1, the luminance ratio may have a luminance ratio that is reduced by about 70% or more compared to a viewing angle of about zero (0) degree, and when the viewing angle is about +15 degrees in the fourth graph G4, the luminance ratio may have a luminance ratio that is reduced by about 30% or less compared to the viewing angle of about zero (0) degree.

Accordingly, as the distance between the element area and the light blocking portion decreases, the reduction of the luminance ratio at the specific viewing angle may decrease.

As shown inFIG.10, as the first light blocking portion BM1, which is closer to the display panel100than the second light blocking portion BM2is in the display device DD (refer toFIG.1) in the vertical direction (e.g., the third direction DR3), is disposed in the second-second element area AE2-G having a relatively small area, the reduction of the luminance ratio according to the specific viewing angle may decrease more in the second-second element area AE2-G than in the second-first element area AE2-B and the second-third element area AE2-R. Therefore, the reduction in the emission rate of the second color light generated by the second-second element area AE2-G of the second area A2may be prevented, and thus, the color shift phenomenon may be reduced when the display device DD is operated in the private mode.

FIG.11is a plan view of a relationship between a sensing electrode and light emitting areas according to an embodiment.FIG.12is a plan view of a relationship between the sensing electrode, a light blocking pattern, and the light emitting areas according to an embodiment.FIG.13is a cross-sectional view taken along a line V-V′ ofFIGS.11and12.

FIGS.11and12are enlarged plan views corresponding to the area AA′ ofFIG.5.FIG.11shows an arrangement relationship between the sensing electrodes and the light emitting areas disposed in the first area A1(refer toFIG.3) and the second area A2(refer toFIG.3) when viewed in plan, andFIG.12shows an arrangement relationship between light blocking portions BM1-A and BM2-A disposed in a light control layer300-A and the light emitting areas disposed in the first area A1and the second area A2. InFIG.12, mesh lines that do not overlap the light blocking portions BM1-A and BM2-A among mesh lines MSL shown inFIG.11are illustrated by a dotted line.

The mesh lines MSL described with reference toFIGS.11,12, and13may be included in one of the sensing patterns SP2of the first sensing electrodes E1-1to E1-5and the second sensing electrodes E2-1to E2-4described with reference toFIG.5.

Referring toFIGS.11,12, and13, the first light blocking portion BM-1A included in the light control layer300-A may be disposed on the same layer (e.g., the second sensing insulating layer IL2) as the layer on which the mesh lines MSL are disposed.

First mesh lines MSL-1of the mesh lines MSL may include a first-first line S1and a first-second line S2. The first-first line S1may extend in the first diagonal direction CDR1, and the first-second line S2may extend in the second diagonal direction CDR2. The first mesh lines MSL-1may surround the first-first light emitting area PXA-B1, the first-second light emitting area PXA-G1, and the first-third light emitting area PXA-R1disposed in the first area A1.

Second mesh lines MSL-2of the mesh lines MSL may include a second-first line M1and a second-second line M2. The second-first line M1may extend in the first diagonal direction CDR1, and the second-second line M2may extend in the second diagonal direction CDR2.

The second mesh lines MSL-2may be disposed in a portion of the second area A2. As an example, the second mesh lines MSL-2may surround at least a portion of second-first light emitting area PXA-B2and the second-third light emitting area PXA-R2.

A first light blocking portion BM1-A may not overlap the first area A1and may surround the second-second light emitting areas PXA-G2in the second area A2. In an embodiment, the first light blocking portion BM1-A may be provided integrally with the mesh lines MSL. Accordingly, the first light blocking portion BM1-A may include the substantially same material as that of the mesh lines MSL and may be provided integrally after patterning through the same process as the process by which the mesh lines MSL are formed.

A second light blocking portion BM2-A may be disposed on a layer different from a layer on which the first light blocking portion BM1-A and the mesh lines MSL are disposed. The second light blocking portion BM2-A may not overlap the first area A1and may surround the second-first light emitting area PXA-B2and the second-third light emitting area PXA-R2of the second area A2.

A display device DD-1may include a display panel100, an input sensor200-A, the light control layer300-A, an anti-reflective layer400, and a window500(refer toFIG.2).

The input sensor200-A may include a first sensing insulating layer IL1, a second sensing insulating layer IL2, and a third sensing insulating layer IL3. The first sensing insulating layer IL1may be disposed on an encapsulation layer140. The bridge patterns CP2of the second sensing electrodes E2-1to E2-4described with reference toFIG.5may be disposed on the first sensing insulating layer IL1.

The second sensing insulating layer IL2may be disposed on the first sensing insulating layer IL1. Among the first sensing electrodes E1-1to E1-5and the second sensing electrodes E2-1to E2-4described with reference toFIG.5, the sensing patterns SP2may be disposed on the second sensing insulating layer IL2. Sensing electrodes CL-A may correspond to one of the sensing patterns SP2of the first sensing electrodes E1-1to E1-5and the second sensing electrodes E2-1to E2-4. Accordingly, the mesh lines MSL described with reference toFIGS.11and12may form the sensing electrodes CL-A. The third sensing insulating layer IL3may be disposed on the second sensing insulating layer IL2. According to an embodiment, the third sensing insulating layer IL3may be omitted. In this case, a first cover layer OC1may cover the second sensing insulating layer IL2.

The light control layer300-A may include the first cover layer OC1, a second cover layer OC2, the first light blocking portion BM1-A, and the second light blocking portion BM2-A. The first cover layer OC1may be disposed on the third sensing insulating layer IL3, and the second cover layer OC2may be disposed on the first cover layer OC1.

The second light blocking portion BM2-A may include a second light blocking pattern B2-1A and a second additional light blocking pattern B2-2A. The second light blocking portion BM2-A may be disposed on the first cover layer OC1and may be covered by the second cover layer OC2. The second light blocking portion BM2-A may correspond to the second light blocking portion BM2described with reference toFIG.9.

In an embodiment, the first light blocking portion BM1-A may include a first light blocking pattern B1-1A and a first additional light blocking pattern B1-2A. The first light blocking portion BM1-A and the sensing electrodes CL-A may be disposed on the second sensing insulating layer IL2and may be covered by the third sensing insulating layer IL3.

In an embodiment, the first light blocking portion BM1-A may be provided integrally with the sensing electrodes CL-A. For example, the first light blocking portion BM1-A may include the substantially same material as that of the sensing electrodes CL-A and may be patterned through the same process as the process by which the sensing electrodes CL-A are formed. Accordingly, the first light blocking portion BM1-A may be connected to one of the sensing patterns SP2of the first sensing electrodes E1-1to E1-5and the second sensing electrodes E2-1to E2-4described with reference toFIG.5and may serve as a sensing electrode. Accordingly, the first light blocking portion BM1-A may include a conductive material.

The first light blocking pattern B1-1A may overlap a second non-light-emitting area NCA-G, and the first additional light blocking pattern B1-2A may overlap a main non-light-emitting area NCA-M adjacent to the second non-light-emitting area NCA-G.

According to an embodiment, the first light blocking pattern B1-1A may have a first line width WD1. The first additional light blocking pattern B1-2A may have a second line width WD2smaller than the first line width WD1, and the sensing electrodes CL-A may have a third line width WD3smaller than the first line width WD1and the second line width WD2.

In addition, the first light blocking pattern B1-1A and the first additional light blocking pattern B1-2A may have a width smaller than a width of an overlapping pixel definition layer. As an example, the first line width WD1of the first light blocking pattern B1-1A may be smaller than the line width of an overlapping second pixel definition layer PDL2, and the second line width WD2of the first additional light blocking pattern B1-2A may be smaller than the line width of an overlapping first pixel definition layer PDL1.

Even though the first light blocking portion BM1-A is disposed on the same layer as the layer on which the sensing electrodes CL-A are disposed, the first light blocking portion BM1-A may have a line width greater than that of the sensing electrodes CL-A. Accordingly, the light generated from the second element area AE2-G may be effectively blocked. In addition, since the first light blocking portion BM1-A is formed through the same process as the process, by which the sensing electrodes CL-A are formed, a process of forming a separate light blocking portion disposed adjacent to the second element area AE2-G may be omitted.

FIG.14is a plan view of a display panel100aaccording to an embodiment.FIG.15is a plan view of a display panel100baccording to an embodiment.FIG.16is a plan view of a display panel100caccording to an embodiment. InFIGS.14,15, and16, the same reference numerals denote the same elements inFIGS.1to9, and thus, detailed descriptions of the same elements will be omitted for descriptive convenience.

FIGS.14,15, and16show embodiments of various shapes of element areas and light emitting areas of a first area A1and a second area A2, and details with respect to first and second light blocking portions BM1and BM2are the same as those described above. The first and second light blocking portions BM1and BM2are illustrated by different hatchings.

Referring toFIG.14, the display panel100amay include the first area A1and the second area A2. The first area A1may include a first-first element area AE1-Ba, a first-second element area AE1-Ga, a first-third element area AE1-Ra, and a first peripheral area NPXA1. The second area A2may include a second-first element area AE2-Ba, a second-second element area AE2-Ga, a second-third element area AE2-Ra, and a second peripheral area NPXA2.

The first area A1may include a first-first light emitting area PXA-B1a, a first-second light emitting area PXA-G1a, and a first-third light emitting area PXA-R1arespectively corresponding to the first-first element area AE1-Ba, the first-second element area AE1-Ga, the first-third element area AE1-Ra.

The first-third light emitting area PXA-R1amay have a size smaller than a size of the first-first light emitting area PXA-B1aand may be greater than a size of the first-second light emitting area PXA-G1a.

In an embodiment, the second-first element area AE2-Ba may include four second-first light emitting areas PXA-B2aspaced apart from each other. The second-second element area AE2-Ga may include two second-second light emitting areas PXA-G2aspaced apart from each other. The second-third element area AE2-Ra may include four second-third light emitting areas PXA-R2aspaced apart from each other.

A size of each of the light emitting areas of the second area A2may be determined by a size of the light emitting area for providing a light having the substantially same color in the first area A1. As an example, a size of one second-third light emitting area PXA-R2amay be smaller than a size of one second-first light emitting area PXA-B2aand may be greater than a size of one second-second light emitting area PXA-G2a.

According to an embodiment, a size of the first-first element area AE1-Ba generating a first color light may be smaller than a size of the second-first element area AE2-Ba. A size of the first-second element area AE1-Ga generating a second color light may be smaller than a size of the second-second element area AE2-Ga. A size of the first-third element area AE1-Ra generating a third color light may be smaller than a size of the second-third element area AE2-Ra.

FIG.14shows a structure in which the second-third element area AE2-Ra includes four second-third light emitting areas PXA-R2a, however, embodiments should not be particularly limited. The number of the second-third light emitting areas PXA-R2aincluded in the second-third element area AE2-Ra having an intermediate size may have an intermediate value of the number of the second-first light emitting area PXA-B2aand the second-second light emitting area PXA-G2a. For example, the second-third element area AE2-Ra may include three second-third light emitting areas PXA-R2a.

Referring toFIG.15, the display panel100bmay include a first area A1and a second area A2. The first area A1may include a first-first element area AE1-Bb, a first-second element area AE1-Gb, a first-third element area AE1-Rb, and a first peripheral area NPXA1. The second area A2may include a second-first element area AE2-Bb, a second-second element area AE2-Gb, a second-third element area AE2-Rb, and a second peripheral area NPXA2.

The first area A1may include a first-first light emitting area PXA-B1b, a first-second light emitting area PXA-G1b, and a first-third light emitting area PXA-R1brespectively corresponding to the first-first element area AE1-Bb, the first-second element area AE1-Gb, and the first-third element area AE1-Rb.

In an embodiment, the first-first light emitting area PXA-B1b, the first-second light emitting area PXA-G1b, and the first-third light emitting area PXA-R1bmay have the substantially same size as each other.

In an embodiment, the second-first element area AE2-Bb may include four second-first light emitting areas PXA-B2bspaced apart from each other. The second-second element area AE2-Gb may include four second-second light emitting areas PXA-G2bspaced apart from each other. The second-third element area AE2-Rb may include four second-third light emitting areas PXA-R2bspaced apart from each other.

The second-first light emitting area PXA-B2b, the second-second light emitting area PXA-G2b, and the second-third light emitting area PXA-R2bmay have the substantially same size as each other.

In an embodiment, a size of the first-first element area AE1-Bb generating a first color light may be smaller than a size of the second-first element area AE2-Bb. A size of the first-second element area AE1-Gb generating a second color light may be smaller than a size of the second-second element area AE2-Gb. A size of the first-third element area AE1-Rb generating a third color light may be smaller than a size of the second-third element area AE2-Rb.

Referring toFIG.16, the display panel100cmay include a first area A1and a second area A2. The first area A1may include a first-first element area AE1-Bc, a first-second element area AE1-Gc, a first-third element area AE1-Rc, and a first peripheral area NPXA1. The second area A2may include a second-first element area AE2-Bc, a second-second element area AE2-Gc, a second-third element area AE2-Rc, and a second peripheral area NPXA2.

In an embodiment, the display panel100cmay further include an additional pixel defining layer disposed on the first electrodes AE (refer toFIG.4A) exposed from the pixel defining layer PDL (refer toFIG.4A) by the first openings OP1(refer toFIG.4A) in the first area A1. Accordingly, the first-first element area AE1-Bc, the first-second element area AE1-Gc, the first-third element area AE1-Rc may include a plurality of first-first light emitting areas PXA-B1c, a plurality of first-second light emitting areas PXA-G1c, and a plurality of first-third light emitting areas PXA-R1cdivided by the additional pixel definition layer, respectively. For example, the first-first element area AE1-Bc may include four first-first light emitting areas PXA-B1cspaced apart from each other. The first-second element area AE1-Gc may include four first-second light emitting areas PXA-G1cspaced apart from each other. The first-third element area AE1-Rc may include four first-third light emitting areas PXA-R2cspaced apart from each other. The first-first element areas PXA-B1c, the first-second element areas PXA-G1c, and the first-third light emitting areas PXA-R1cmay have the substantially same size as each other.

In an embodiment, the second-first element area AE2-Bc may include four second-first light emitting areas PXA-B2cspaced apart from each other. The second-second element area AE2-Gc may include four second-second light emitting areas PXA-G2cspaced apart from each other. The second-third element area AE2-Rc may include four second-third light emitting areas PXA-R2cspaced apart from each other. The second-first light emitting areas PXA-B2c, the second-second light emitting areas PXA-G2c, and the second-third light emitting areas PXA-R2cmay have the substantially same size as each other.

In an embodiment, a size of the first-first element area AE1-Bc generating a first color light may be the substantially same as a size of the second-first element area AE2-Bc. A size of the first-second element area AE1-Gc generating a second color light may be the substantially same as a size of the second-second element area AE2-Gc. A size of the first-third element area AE1-Rc generating a third color light may be the substantially same as a size of the second-third element area AE2-Rc.