Semiconductor device and method of forming an IPD over a high-resistivity encapsulant separated from other IPDS and baseband circuit

A semiconductor device has a first conductive layer formed over a sacrificial substrate. A first integrated passive device (IPD) is formed in a first region over the first conductive layer. A conductive pillar is formed over the first conductive layer. A high-resistivity encapsulant greater than 1.0 kohm-cm is formed over the first IPD to a top surface of the conductive pillar. A second IPD is formed over the encapsulant. The first encapsulant has a thickness of at least 50 micrometers to vertically separate the first and second IPDs. An insulating layer is formed over the second IPD. The sacrificial substrate is removed and a second semiconductor die is disposed on the first conductive layer. A first semiconductor die is formed in a second region over the substrate. A second encapsulant is formed over the second semiconductor die and a thermally conductive layer is formed over the second encapsulant.

FIELD OF THE INVENTION

The present invention relates in general to semiconductor devices and, more particularly, to a semiconductor device having an integrated passive device (IPD) formed over a high-resistivity encapsulant and separated from other IPDs and baseband circuits.

BACKGROUND OF THE INVENTION

Semiconductor devices perform a wide range of functions such as high-speed calculations, transmitting and receiving electromagnetic signals, controlling electronic devices, transforming sunlight to electricity, and creating visual projections for television displays. Semiconductor devices are found in the fields of entertainment, communications, power generation, networks, computers, and consumer products. Semiconductor devices are also found in electronic products including military, aviation, automotive, industrial controllers, and office equipment.

Semiconductor devices exploit the electrical properties of semiconductor materials. The atomic structure of semiconductor material allows its electrical conductivity to be manipulated by the application of an electric field or through the process of doping. Doping introduces impurities into the semiconductor material.

A semiconductor device contains active and passive electrical structures. Active structures, including transistors, control the flow of electrical current. By varying levels of doping and application of an electric field, the transistor either promotes or restricts the flow of electrical current. Passive structures, including resistors, diodes, and inductors, create a relationship between voltage and current necessary to perform a variety of electrical functions. The passive and active structures are electrically connected to form logic circuits, which enable the semiconductor device to perform high-speed calculations and other useful functions.

Semiconductor devices are generally manufactured using two complex manufacturing processes, i.e., front-end manufacturing, and back-end manufacturing, each involving potentially hundreds of steps. Front-end manufacturing involves the formation of a plurality of die on the surface of a semiconductor wafer. Each die is identical and contains circuits formed by electrically connecting active and passive components. Back-end manufacturing involves singulating individual die from the finished wafer and packaging the die to provide structural support and environmental isolation.

One goal of semiconductor manufacturing is to produce smaller semiconductor devices. Smaller devices typically consume less power, can be produced more efficiently, and have higher performance. In addition, smaller semiconductor devices have a smaller footprint, which is desirable for smaller end products. A smaller die size may be achieved by improvements in the front-end process resulting in die with smaller, higher density active and passive components. Back-end processes may result in semiconductor device packages with a smaller footprint by improvements in electrical interconnection and packaging materials.

Another goal of semiconductor manufacturing is to produce higher performance semiconductor devices. Increases in device performance can be accomplished by forming active components that are capable of operating at higher speeds. In high frequency applications, such as radio frequency (RF) wireless communications, integrated passive devices (IPDs) are often contained within the semiconductor device. Examples of IPDs include resistors, capacitors, and inductors. A typical RF system requires multiple IPDs in one or more semiconductor packages to perform the necessary electrical functions. However, high frequency electrical devices generate or are susceptible to undesired electromagnetic interference (EMI) and radio frequency interference (RFI), or other inter-device interference, such as capacitive, inductive, or conductive coupling, also known as cross-talk.

Another goal of semiconductor manufacturing is to produce semiconductor devices with adequate heat dissipation. High frequency semiconductor devices generally generate more heat. Without effective heat dissipation, the generated heat can reduce performance, decrease reliability, and reduce the useful lifetime of the semiconductor device.

High-quality (Q) IPDs used in high frequency applications typically require a high-cost substrate having a high-resistivity, e.g., greater than 1.0 kohm-cm. The IPDs are typically formed side-by-side, or on the same wafer level, which consumes silicon area. In addition, the IPD processes needed to produce high-quality capacitors and resistors require high temperatures to deposit the requisite dielectric layers for these devices. The high-resistivity substrate and high temperature IPD processes adds cost and increases overall package size.

SUMMARY OF THE INVENTION

A need exists for a semiconductor device having high-quality IPDs without using a high-cost substrate. Accordingly, in one embodiment, the present invention is a method of manufacturing a semiconductor device comprising the steps of providing a sacrificial substrate, forming a first insulation layer over the sacrificial substrate, forming a first conductive layer over the first insulating layer, forming a first IPD in a first region over the first conductive layer, forming a plurality of conductive pillars over the first conductive layer, and disposing a first semiconductor die in a second region over the sacrificial substrate. The second region is separate from the first region. The method further includes the step of forming a first encapsulant over the first IPD to a top surface of the conductive pillars. The first encapsulant has a resistivity greater than 1.0 kohm-cm. The method further includes the steps of forming a second IPD over the first encapsulant, forming a first insulating layer over the second IPD, removing the sacrificial substrate, and disposing a second semiconductor die over the first conductive layer.

In another embodiment, the present invention is a method of manufacturing a semiconductor device comprising the steps of providing a sacrificial substrate, forming a first conductive layer over the sacrificial substrate, forming a first IPD in a first region over the first conductive layer, forming a conductive pillar over the first conductive layer, forming a high-resistivity encapsulant over the first IPD to a top surface of the conductive pillar, and forming a second IPD over the high-resistivity encapsulant.

In another embodiment, the present invention is a method of manufacturing a semiconductor device comprising the steps of providing a substrate, forming a first conductive layer over the substrate, forming a first IPD over the first conductive layer, forming a conductive pillar over the first conductive layer, forming an encapsulant over the first IPD to a top surface of the conductive pillar, and forming a second IPD over the encapsulant.

In another embodiment, the present invention is a semiconductor device comprising a substrate and first conductive layer formed over the substrate. A first IPD is formed in a first region over the first conductive layer. A conductive pillar is formed over the first conductive layer. A high-resistivity encapsulant is formed over the first IPD to a top surface of the conductive pillar. A second IPD is formed over the high-resistivity encapsulant.

DETAILED DESCRIPTION OF THE DRAWINGS

Semiconductor devices are generally manufactured using two complex manufacturing processes: front-end manufacturing and back-end manufacturing. Front-end manufacturing involves the formation of a plurality of die on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components which are electrically connected to form circuits. Active electrical components, such as transistors, have the ability to control the flow of electrical current. Passive electrical components, such as capacitors, inductors, resistors, and transformers, create a relationship between voltage and current necessary to perform electrical circuit functions.

Passive and active components are formed on the surface of the semiconductor wafer by a series of process steps including doping, thin film deposition, photolithography, etching, and planarization. Doping introduces impurities into the semiconductor material by techniques such as ion implantation or thermal diffusion. The doping process modifies the electrical conductivity of semiconductor material in active devices, transforming the semiconductor material into a permanent insulator, permanent conductor, or changing the way the semiconductor material changes in conductivity in response to an electric field. Transistors contain regions of varying types and degrees of doping arranged as necessary to enable the transistor to promote or restrict the flow of electrical current upon the application of an electric field.

Active and passive components are formed by layers of materials with different electrical properties. The layers can be formed by thin film deposition. The type of material being deposited determines the thin film deposition technique. The thin film deposition techniques include chemical vapor deposition (CVD), physical vapor deposition (PVD), electrolytic plating, and electroless plating processes. Each layer is generally patterned to form portions of active components, passive components, or electrical connections between components.

The layers can be patterned using photolithography, which involves the deposition of light sensitive material, e.g., photoresist, over the layer to be patterned. A pattern is transferred from a photomask to the photoresist using light. The portion of the photoresist pattern subjected to light is removed using a solvent, exposing portions of the underlying layer to be patterned. The remainder of the photoresist is removed, leaving behind a patterned layer. Some types of materials are patterned without being etched; instead patterns are formed by directly depositing the material into the areas or voids formed by a previous deposition/etch process using techniques such as electrolytic plating.

FIG. 1illustrates electronic device10having a chip carrier substrate or printed circuit board (PCB)12with a plurality of semiconductor packages mounted on its surface. Electronic device10may have one type of semiconductor package, or multiple types of semiconductor packages, depending on the application. The different types of semiconductor packages are shown inFIG. 1for purposes of illustration.

Electronic device10may be a stand-alone system that uses the semiconductor packages to perform an electrical function. Alternatively, electronic device10may be a subcomponent of a larger system. For example, electronic device10may be a graphics card, network interface card, or other signal processing card that can be inserted into a computer. The semiconductor package can include microprocessors, memories, application specific integrated circuits (ASICs), logic circuits, analog circuits, RF circuits, discrete devices, or other semiconductor die or electrical components.

InFIG. 1, PCB12provides a general substrate for structural support and electrical interconnect of the semiconductor packages mounted on the PCB. Conductive signal traces14are formed on a surface or within layers of PCB12using evaporation, electrolytic plating, electroless plating, screen printing, or other suitable metal deposition process. Signal traces14provide for electrical communication between each of the semiconductor packages, mounted components, and other external system components. Traces14also provide power and ground connections to each of the semiconductor packages.

In some embodiments, a semiconductor device has two packaging levels. First level packaging is the technique for mechanically and electrically attaching the semiconductor die to a carrier. Second level packaging involves mechanically and electrically attaching the carrier to the PCB. In other embodiments, a semiconductor device may only have the first level packaging where the die is mechanically and electrically attached directly to the PCB.

For the purpose of illustration, several types of first level packaging, including wire bond package16and flip chip18, are shown on PCB12. Additionally, several types of second level packaging, including ball grid array (BGA)20, bump chip carrier (BCC)22, dual in-line package (DIP)24, land grid array (LGA)26, multi-chip module (MCM)28, quad flat non-leaded package (QFN)30, and quad flat package32, are shown mounted on PCB12. Depending upon the system requirements, any combination of semiconductor packages, configured with any combination of first and second level packaging styles, as well as other electronic components, can be connected to PCB12. In some embodiments, electronic device10includes a single attached semiconductor package, while other embodiments call for multiple interconnected packages. By combining one or more semiconductor packages over a single substrate, manufacturers can incorporate pre-made components into electronic devices and systems. Because the semiconductor packages include sophisticated functionality, electronic devices can be manufactured using cheaper components and a shorter manufacturing process. The resulting devices are less likely to fail and less expensive to manufacture resulting in lower costs for consumers.

FIG. 2aillustrates further detail of DIP24mounted on PCB12. DIP24includes semiconductor die34having contact pads36. Semiconductor die34includes an active area containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within semiconductor die34and are electrically interconnected according to the electrical design of the die. For example, the circuit may include one or more transistors, diodes, inductors, capacitors, resistors, and other circuit elements formed within the active area of die34. Contact pads36are made with a conductive material, such as aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), or silver (Ag), and are electrically connected to the circuit elements formed within die34. Contact pads36are formed by PVD, CVD, electrolytic plating, or electroless plating process. During assembly of DIP24, semiconductor die34is mounted to a carrier38using a gold-silicon eutectic layer or adhesive material such as thermal epoxy. The package body includes an insulative packaging material such as plastic or ceramic. Conductor leads40are connected to carrier38and wire bonds42are formed between leads40and contact pads36of die34as a first level packaging. Encapsulant44is deposited over the package for environmental protection by preventing moisture and particles from entering the package and contaminating die34, contact pads36, or wire bonds42. DIP24is connected to PCB12by inserting leads40into holes formed through PCB12. Solder material46is flowed around leads40and into the holes to physically and electrically connect DIP24to PCB12. Solder material46can be any metal or electrically conductive material, e.g., Sn, lead (Pb), Au, Ag, Cu, zinc (Zn), bismuthinite (Bi), and alloys thereof, with an optional flux material. For example, the solder material can be eutectic Sn/Pb, high-lead, or lead-free.

FIG. 2billustrates further detail of BCC22mounted on PCB12. Semiconductor die16is connected to a carrier by wire bond style first level packaging. BCC22is mounted to PCB12with a BCC style second level packaging. Semiconductor die16having contact pads48is mounted over a carrier using an underfill or epoxy-resin adhesive material50. Semiconductor die16includes an active area containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within semiconductor die16and are electrically interconnected according to the electrical design of the die. For example, the circuit may include one or more transistors, diodes, inductors, capacitors, resistors, and other circuit elements formed within the active area of die16. Contact pads48are made with a conductive material, such as Al, Cu, Sn, Ni, Au, or Ag, and are electrically connected to the circuit elements formed within die16. Contact pads48are formed by PVD, CVD, electrolytic plating, or electroless plating process. Wire bonds54and bond pads56and58electrically connect contact pads48of semiconductor die16to contact pads52of BCC22forming the first level packaging. Mold compound or encapsulant60is deposited over semiconductor die16, wire bonds54, contact pads48, and contact pads52to provide physical support and electrical isolation for the device. Contact pads64are formed on a surface of PCB12using evaporation, electrolytic plating, electroless plating, screen printing, or other suitable metal deposition process and are typically plated to prevent oxidation. Contact pads64electrically connect to one or more conductive signal traces14. Solder material is deposited between contact pads52of BCC22and contact pads64of PCB12. The solder material is reflowed to form bumps66which form a mechanical and electrical connection between BCC22and PCB12.

InFIG. 2c, semiconductor die18is mounted face down to carrier76with a flip chip style first level packaging. BGA20is attached to PCB12with a BGA style second level packaging. Active area70containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within semiconductor die18is electrically interconnected according to the electrical design of the die. For example, the circuit may include one or more transistors, diodes, inductors, capacitors, resistors, and other circuit elements formed within active area70of semiconductor die18. Semiconductor die18is electrically and mechanically attached to the carrier76through a large number of individual conductive solder bumps or balls78. Solder bumps78are formed on bump pads or interconnect sites80, which are disposed on active areas70. Bump pads80are made with a conductive material, such as Al, Cu, Sn, Ni, Au, or Ag, and are electrically connected to the circuit elements formed in active area70. Bump pads80are formed by PVD, CVD, electrolytic plating, or electroless plating process. Solder bumps78are electrically and mechanically connected to contact pads or interconnect sites82on carrier76by a solder reflow process.

BGA20is electrically and mechanically attached to PCB12by a large number of individual conductive solder bumps or balls86. The solder bumps are formed on bump pads or interconnect sites84. The bump pads84are electrically connected to interconnect sites82through conductive lines90routed through carrier76. Contact pads88are formed on a surface of PCB12using evaporation, electrolytic plating, electroless plating, screen printing, or other suitable metal deposition process and are typically plated to prevent oxidation. Contact pads88electrically connect to one or more conductive signal traces14. The solder bumps86are electrically and mechanically connected to contact pads or bonding pads88on PCB12by a solder reflow process. Mold compound or encapsulant92is deposited over semiconductor die18and carrier76to provide physical support and electrical isolation for the device. The flip chip semiconductor device provides a short electrical conduction path from the active devices on semiconductor die18to conduction tracks on PCB12in order to reduce signal propagation distance, lower capacitance, and achieve overall better circuit performance. In another embodiment, the semiconductor die18can be mechanically and electrically attached directly to PCB12using flip chip style first level packaging without carrier76.

FIGS. 3a-3eillustrate a process of forming an integrated passive device (IPD) over a high-resistivity molding compound on wafer100. InFIG. 3a, an insulating layer104is formed on substrate102. Substrate102is a dummy or sacrificial base material such as silicon (Si), ceramic, glass, or other suitable low-cost, rigid material. The insulating layer104can be silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentoxide (Ta2O5), zircon (ZrO2), aluminum oxide (Al2O3), or other material having suitable insulating properties. The insulating layer104is patterned or blanket deposited using PVD, CVD, printing, and sintering or thermal oxidation and result in a thickness ranging from 100-20000 Å. The insulating layer104can single or multiple layers. The insulating layer104is optional, provides stress relief and operates as an etch stop.

In one embodiment, a portion of insulating layer104is removed to form vias106. An electrically conductive layer108is formed on insulating layer104using a patterning and deposition process to form individual portions or sections108a-108f. The individual portions of conductive layer108can be electrically common or electrically isolated depending on the connectivity of the individual semiconductor die formed on wafer100. Conductive layer108fills vias106. In one embodiment, conductive layer108is stacked Ti/NiV/Cu or Al/NiV/Cu with Ti or AL as an adhesive layer, nickel vanadium (NiV) as a barrier layer, and Cu as a wetting layer. Alternately, conductive layer108can be Al, Cu, Sn, Ni, Au, Ag, or other suitable material with optional adhesion and barrier layers containing titanium (Ti), titanium tungsten (TiW), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN). The deposition of conductive layer108uses PVD, CVD, electrolytic plating, or electroless plating process.

An insulating layer112is formed over resistive layer110ausing a patterning and deposition process. The insulating layer112is Si3N4, SiO2, SiON, Ta2O5, ZnO, ZrO2, Al2O3, or other suitable dielectric material. The deposition of insulating layer112may involve PVD or CVD. Resistive layer110and insulating layer112are formed with the same mask and etched at the same time. Alternatively, resistive layer110and insulating layer112can be patterned and etched with a different mask.

Conductive pillars or posts118are formed over conductive layer116. Conductive pillars118can be Cu, Al, W, Au, solder, or other suitable material. To form conductive pillars, a thick layer of photoresist, e.g., 100-200 μm, is deposited over conductive layer116. The photoresist can be a liquid or a dry film. Two layers of photoresist may be applied to achieve the desired thickness. The photoresist is patterned and metal is deposited in the patterned areas of the photoresist using PVD, CVD, electrolytic plating, or electroless plating process. The photoresist is stripped away leaving behind individual conductive pillars118.

In another embodiment, the conductive pillars118can be replaced with solder balls or Au stud bumps. An adhesion layer may be deposited and patterned to improve adhesion of conductive layer116on passivation114. The adhesion layer is removed in areas exposed by conductive layer116by an etching process. An additional passivation layer may be formed over passivation layer114and conductive layer116to provide structural support and electrical isolation. The additional passivation layer is patterned to expose portions of conductive layer116. Solder balls are formed over the conductive layer116in the patterned areas of the additional passivation layer.

The structures described inFIGS. 3a-3b, e.g., the combination of conductive layer108, resistive layer110, insulating layer112, and conductive layer116, constitute one or more passive circuit elements or IPDs. For example, conductive layer108b, resistive layer110a, insulating layer112, and conductive layer116is a metal-insulator-metal (MIM) capacitor. Resistive layer110bis a resistor element in the passive circuit. Other active and passive circuit elements can be formed on wafer100as part of the electrically functional semiconductor device.

FIG. 3cshows a semiconductor device120mounted to conductive layer108c-108eusing electrical connections122, e.g., solder bumps, metal bonding, or conductive paste. For example, semiconductor die120can be a baseband digital circuit, such as digital signal processor (DSP) or memory. Note that a top surface of conductive pillar118and semiconductor device120have about the same height. Alternatively, if conductive pillar118and semiconductor device120have different heights, then semiconductor device120is typically made higher. In other embodiments, conductive pillars118are higher than semiconductor device120.

An encapsulant or molding compound124is deposited over the IPD structure, between conductive pillars118, and around semiconductor device120using a printing, compressive molding, transfer molding, liquid encapsulant molding, or other suitable applicator. Encapsulant124extends to a top surface of conductive pillars118. Encapsulant124can be epoxy resin, epoxy acrylate, polymer, or polymer composite material. Encapsulant124is non-conductive and environmentally protects the semiconductor device from external elements and contaminants. Encapsulant124has a coefficient of thermal expansion (CTE) that is adjusted to match that of the base semiconductor material, e.g., Si, with glass transition temperature (Tg) greater than 100° C. The CTE of encapsulant124can be adjusted using a filler such as a powder, fiber, or cloth additive. A suitable encapsulant material is generally characterized by low-shrinkage, high-resistivity of greater than 1.0 kohm-cm, low-dielectric constant of less than 4, and low-loss tangent of less than 0.05 in 500 MHz to 30 GHz range. Encapsulant124undergoes grinding or etch-back to expose conductive pillars118.

InFIG. 3d, an insulating layer128is formed over conductive pillars118, semiconductor device120, and encapsulant124using spin coating or laminate with an adhesive. A portion of insulating layer128is removed using an etching process to expose conductive pillars118. The insulating layer128is optional.

An electrically conductive layer130is formed over encapsulant124, insulating layer128, and conductive pillars118using a patterning and deposition process to form individual portions or sections130a-130g. The individual portions of conductive layer130can be electrically common or electrically isolated depending on the connectivity of the individual semiconductor die formed on wafer100. Conductive layer130can be Al, Cu, Sn, Ni, Au, Ag, or other suitable material. The deposition of conductive layer130uses PVD, CVD, electrolytic plating, or electroless plating process.

An insulating layer132is formed over insulating layer128and conductive layer130using a patterning and deposition process. The insulating layer132can be epoxy matrix polymer, Si3N4, SiO2, SiON, Ta2O5, ZnO, ZrO2, Al2O3, or other suitable insulating material. The deposition of insulating layer132may involve spin coating, printing, molding, or lamination with polymer matrix composite.

The conductive layer130b-130econstitute an IPD, in this case an inductor. The conductive layer130b-130eis typically wound or coiled in plan-view to produce or exhibit the desired inductive properties. Conductive layer130b-130eis formed over encapsulant124and insulating layer128. The inductor130b-130eis separated from the other IPDs, i.e., MIM capacitor and resistive layer110b, by the thickness of encapsulant124and insulating layer128, e.g., about 50 micrometers (μm). By forming the inductor over encapsulant124, which has high resistivity, low loss tangent, low dielectric constant, and matching CTE, high quality IPDs can be realized, without using a high-resistivity substrate. In addition, vertically separating the inductor from the MIM capacitor and resistor with high-resistivity encapsulant124, i.e., stacking the IPDs rather than spacing them laterally across the die, saves silicon area and provides a smaller package. Other types of IPDs, such as capacitors and resistors, can be formed over the high-resistivity encapsulant124and insulating layer128.

Conductive layer130a,130f, and130gelectrically connect to conductive pillars118. The inductor formed by conductive layer130b-130eresides over encapsulant124. In the present embodiment, there is no conductive pillar under the inductor structure130b-130e.

The IPDs contained within wafer100provide the electrical characteristics needed for high frequency applications, such as resonators, high-pass filters, low-pass filters, band-pass filters, symmetric Hi-Q resonant transformers, matching networks, and tuning capacitors. The IPDs can be used as front-end wireless RF components, which can be positioned between the antenna and transceiver. The IPD inductor can be a hi-Q balun, transformer, or coil, operating up to 100 Gigahertz. In some applications, multiple baluns are formed on a same substrate, allowing multi-band operation. For example, two or more baluns are used in a quad-band for mobile phones or other global system for mobile (GSM) communications, each balun dedicated for a frequency band of operation of the quad-band device. A typical RF system requires multiple IPDs and other high frequency circuits in one or more semiconductor packages to perform the necessary electrical functions. However, high frequency electrical devices generate or are susceptible to undesired EMI, RFI, or other inter-device interference, such as capacitive, inductive, or conductive coupling, also known as cross-talk.

Note inFIG. 3dthat high frequency IPDs are contained within region134of wafer100. Baseband components are contained within region136of wafer100. The high frequency IPDs are thus separated from the baseband components to reduce electromagnetic interference (EMI) and radio frequency interference (RFI), and other inter-device interference between the devices, such as capacitive, inductive, or conductive coupling, also known as cross-talk. High frequency components in region134and baseband components in region136constitute a system-in-package (SiP) arrangement.

FIG. 4shows the device fromFIG. 3ewith encapsulant or molding compound150formed on a backside of the wafer over semiconductor devices138,140, and144. The IPDs and semiconductor die generate heat during normal operation. A thermally conductive layer or heat sink152is attached to molding compound150with an adhesive for thermal dissipation and high reliability. Heat sink152conducts heat away from the semiconductor device.

In summary, an upper IPD (e.g. an inductor) is formed over the high-resistivity molding compound, which eliminates the need for a high-cost substrate. The upper IPD is vertically separated from the lower IPDs (e.g. MIM capacitor and resistor) by the high-resistivity encapsulant, i.e. IPDs are stacked and separated by high-resistivity encapsulant, resulting in a small RF SiP with high quality IPDs. The high frequency IPDs are further separated from the baseband components to reduce EMI, RFI, and other inter-device interference.