Automatic selective slow program convergence

Apparatus, methods, and systems are disclosed, including those to improve program voltage distribution width using automatic selective slow program convergence (ASSPC). One such method may include determining whether a threshold voltage (Vt) associated with a memory cell has reached a particular pre-program verify voltage. In response to the determination, a voltage applied to a bit-line coupled to the memory cell may be automatically incremented at least twice as the program voltage is increased, until the cell is properly programmed. Additional embodiments are also described.

BACKGROUND

Nonvolatile memory, including flash memory devices, may be used in personal computers, personal digital assistants (PDAs), digital cameras, and cellular telephones to store program code and system data, such as a basic input/output system (BIOS).

DETAILED DESCRIPTION

In general, some memory devices may use a one-transistor memory cell design that facilitates high memory densities, high reliability, and low power consumption. In some cases, Multi-Level memory Cells (MLCs) may be used in memory devices to further increase density. To provide good performance in an MLC device, it may be useful to reduce the program gate step size to reduce the program threshold voltage (Vt) distribution width. Reducing the program gate step size may also reduce the cell programming time performance.

Various apparatuses and methods that improve the balance between program threshold voltage (Vt) distribution width and program time will now be described.

During a programming operation, various embodiments may operate to determine that the voltage Vt associated with an individual memory cell has reached a particular pre-program verify (PPV) voltage. In response to this determination, a voltage applied to a digit line, such as a bit-line (BL), coupled to the selected memory cell may be incremented. That is, the voltage applied to the digit line will be incremented without determining whether the threshold voltage has reached some other pre-program verify voltage (PPV).

Selective slow program convergence (SSPC) may be used to attain improvement in the program threshold voltage (Vt) distribution width. Referring toFIG. 1A, once a cell approaches a particular target threshold voltage (Vt)10and passes the pre-program verify (PPV) voltage12, a small voltage may be applied to the bit line (BL), which causes the programming of the cell to slow down during the pair of pulses14. A further reduction in the program threshold voltage (Vt) distribution width may be achieved by adding another level of selective slow program convergence (SSPC) as shown inFIG. 1B. Accordingly, two (or multiple) pre-verify levels, including a first pre-verify level (PPV1) and a second pre-verify level (PPV2) may be employed. Pre-verifying the cell will, however, require an additional verify operation, which may cause programming time to be extended.

In various embodiments, increasing the BL bias voltage may be used to achieve a tight Vt distribution without suffering a significant overall device programming time penalty. This is because the programming of selected cells (those that benefit from an increased programming time) may be slowed down by the incremented application of the BL voltage. Incrementing the BL voltage will automatically help minimize the program time as compared to conventional-SSPC or dual-SSPC methods.

FIG. 1is a schematic diagram illustrating a memory array100, according to the various embodiments. The memory array100may comprise a nonvolatile memory array, for example, a flash memory array, such as a portion of a NAND architecture flash memory device. The various embodiments are not limited to any one type of memory array architecture. For example, the various embodiments may also operate in NOR or AND array architectures. The memory array100, for purposes of clarity, may not show all of the elements typically used in a memory array. For example, only two bit-lines (BLs) are shown inFIG. 1(e.g., BL1and BL2), whereas the number of BLs that may be used may generally depend upon the memory density, and consequently may be quite large. In the present discussion, the BLs will be subsequently referred to herein as (BL1-BLN).

The memory array100may comprise an array of memory cells, such as floating gate memory cells110, arranged in a series of chains, such as columns115and116. Each of the floating gate memory cells110may be coupled drain-to-source to form the columns115and116. Each access line, such as word lines (WL0-WL31) spans multiple chains, such as the columns115and116, and may be coupled to, or comprise the control gates of every floating gate memory cell110in a row in order to control their operation. The BLs (BL1-BLN) may be coupled to sense circuitry, such as sense amplifiers (not shown) that may detect the programmed state (e.g., a binary logic state such as 0 or 1) of each cell.

In operation, the word lines (WL0-WL31) may select the individual floating gate memory cells in the columns115and116to be written to or read from and operate the remaining floating gate memory cells110in each of columns115and116in a pass-through mode. The array columns of the floating gate memory cells110, such as columns115and116, may be coupled to a source line (SL)180by source select switches150and160, and to individual BLs (BL1-BLN) by drain select switches155and165. The source select switches150and160may be controlled by a source select control line SC(S)140that may be coupled to gate contacts of the source select switches150and160. The drain select switches155and165may be controlled by a drain select control line SC(D)130.

In a memory programming operation, the selected word line for the flash memory cell110may be biased with a series of incrementing voltage programming pulses (or an incrementing pulse width) that may start at an initial voltage greater than a programming voltage (e.g., approximately 16V, for example). After each programming voltage pulse, a verification operation with a word line voltage of 0V may be performed to determine whether the voltage Vt of the memory cell has increased to a desired programmed level (e.g., 0.5V, for example).

The unselected word lines of the remaining cells may be biased at a voltage that is less than the programming voltage (e.g., approximately 10V, for example) during the program operation. Each of the memory cells of the memory array100may be programmed in a similar fashion.

FIG. 2is a diagram illustrating Vt distributions200for an MLC device, which may include four-level flash memory cells, according to the various embodiments. Memory cells of a NAND array architecture, which may be included in the memory array100ofFIG. 1, may be configured (e.g., programmed) to achieve a desired program state. For example, an electric charge may be placed on or removed from the floating gate of a memory cell to program the memory cell into a number of stored states. For example, a single level cell (SLC) may represent two binary logic states, e.g., 1 or 0.

Flash memory cells may store more than two bits of data in multiple states. Memory cells with more than two stored states may be generally referred to as MLC devices, multi-bit cells, or multi-state cells. MLC devices may thus allow the manufacture of higher density memories without increasing the number of memory cells since each cell can represent more than one bit. MLCs may have more than one programmed state (a cell capable of representing four bits can have fifteen programmed states and an erased state, for example). For example,FIG. 2shows four states of a memory device having four-level memory cells. Three of the states may comprise programmed states “10”, “00”, and “01”, respectively, corresponding to Vt distributions202,203, and204shown inFIG. 2. A Vt distribution201, at negative threshold voltages, may represent an erased state “11.”

The Vt distributions201-204shown inFIG. 2may represent statistical distributions of the measured threshold voltages for a large number of memory cells. When increasing the number of storage levels in a memory cell, other design considerations (for example, data reliability) may come into play. As the number of storage levels in a memory cell increase, the gap210between Vtdistributions may decrease due to limitations in applying higher voltages. As a result, the memory device may be susceptible to various data corruption mechanisms. For example, corruption mechanisms in NAND flash memories may include thermal noise, random telegraph signaling (also known as burst noise), cycle fatigue resulting from repeated program/erase cycles, and disturbances due to read and write operations in adjacent cells. Although digital error correction and detection may be used to overcome the reliability issues resulting from some of the foregoing corruption mechanisms, data reliability may also be enhanced if the distribution width220of stored states can be reduced. For example, this reduction may operate to improve the cell data reliability by providing a larger gap210between stored states202-204.

Although the programmed states shown inFIG. 2comprise only three states, the various embodiments are not so limited, and may include MLC devices with different numbers of programmed states. Also, the disclosed methods are not limited to multi-level flash memory cells and may be applied to other types of MLCs.

FIG. 3is a diagram illustrating a program voltage graph310, an applied BL voltage graph330, and a Vt graph320for a flash memory cell programmed using ASSPC, according to the various embodiments. The program voltage pulses shown by the program voltage graph310may be applied to one of the WLs120ofFIG. 1connected to a memory cell of the memory array100(e.g., memory cell167ofFIG. 1) that is designated for a data write operation. In the various embodiments, the program voltage pulses as shown in program voltage graph310may comprise a series of voltage pulses having incrementally increasing pulse heights and may have identical pulse widths, although other pulses may also be used.

Still referring toFIG. 3, and also again toFIGS. 1-2, it may be seen that the program voltage pulses in the program voltage graph310may start at an initial pulse height (e.g., approximately 16 volts) and increase in increments having a predetermined height (e.g., approximately 0.5 volt). The height increments of the program voltage pulses in the program voltage graph310may be initially followed by substantially identical changes in the voltage Vt of the memory cell167as shown by the graph320. A program target may be set to increase the voltage Vt to a selected value within a range of Vt values corresponding to desired programmed state (e.g., stored state203, as shown inFIG. 2). A program verify (PV) point354may designate such an instance in the program phase360of the memory cell167, which may indicate when the Vt has reached that value within the range of Vt values corresponding to the desired programmed state. At the PV point354, it may be determined that the Vt voltage has increased to the selected PV voltage. The selected PV voltage may comprise a Vt value that is within the Vt range of the desired programmed state, for example the programmed state203, shown inFIG. 2. The determination may comprise sensing the memory cell167, via a sense amplifier coupled to BL2ofFIG. 1, and comparing the content of the memory cell with a desired value (e.g., the PV voltage).

The ASSPC method may be used to decrease (i.e., tighten) the Vt distribution width (e.g., a width of the programmed state203) of an MLC device in the various embodiments. The Vt voltage distribution width may be tightened by using program voltage pulses310with smaller programming increments. However, using smaller programming increments may degrade the programming performance, since it may take more time to program the memory cell. For example, one way to keep the programming increment unchanged while reducing its effect on the voltage Vt, may include applying a carefully designed voltage to the BL coupled to the cell being programmed. This may reduce the voltage drop across the memory cell transistor, which in turn, may reduce the effective programming voltage applied to the memory cell167.

Thus, at a selected PPV point352, the BL voltage pulses shown in the BL voltage graph330may be applied to the BL2ofFIG. 1, which may be coupled to the column116ofFIG. 1, including the memory cell167. The PPV point352may be associated with a PPV voltage that is close to the PV voltage. Accordingly, the PPV point352may be an indication that the Vt of the memory cell167is approaching the PV voltage. As shown by the BL voltage graph330, when starting at a PPV point352, the voltage applied to the BL2may be automatically incremented in particular increments (e.g., approximately 0.25 volt) until the PV point354is reached. In general terms, this may include incrementing the BL voltage multiple times in response to the Vt level reaching a single PPV. The Vt graph320shows that the incremented values of the voltage Vt may have been reduced after the PPV point352is reached.

The reduction in incremented values of the Vt voltage may result in finer movements towards the target PV voltage. At PV point354, when the Vt reaches the target PV voltage, the programming of the memory cell167may enter an additional phase (e.g., an inhibit phase370). In the inhibit phase370, the BL voltage applied to the BL2may be set to a program inhibit voltage (Vinhibit) value, whereas the program voltage pulses shown in graph310may continue to rise in value to allow for continued programming of other memory cells connected to the same WL (i.e., WL29). The program voltage pulses and the BL voltage may be controlled by the control circuitry430shown inFIG. 4, and as described in further detail below.

FIG. 4is a block diagram illustrating a system400for programming flash memory cells using a method, according to various embodiments. The system400may include one or more memory devices420that may be coupled to a processor410. The one or more memory devices420may comprise a nonvolatile memory device such as the memory array460(e.g., a memory array similar to the array100shown inFIG. 1). The processor410may comprise a microprocessor, a controller, or other controlling circuitry. The memory device420and the processor410may form at least a part of an electronic system400, such as a laptop or desktop computer, a cell phone, a personal digital assistant (PDA), a camera, or other similar devices. The system400and memory device420may have any number of additional components not shown inFIG. 4. Accordingly,FIG. 4has been simplified to specifically focus on features of the memory device420.

Address buffer circuitry440may be provided to latch address signals provided on address input connections414. The address signals may be received and decoded by a row decoder462and a column decoder464to access the memory array460. The number of address input connections may depend on the density and architecture of the memory array460and, for example, may increase with an increased number of memory cells in the memory array460.

The memory device420may read data in the memory array460by sensing voltage or current changes in the memory array columns using read/write circuitry466. Data input and output (I/O) buffer circuitry450may perform bi-directional data communication over a plurality of data connections416with the processor410. The read/write circuitry466may also facilitate writing data to the memory array460.

Control circuitry430may decode signals provided on control connections412by the processor410. These signals may be used to control the operations on the memory array460, including data read, data write, and erase operations. In the various embodiments, the control circuitry430may execute any one or more of the method, or portions of the methods described herein. The control circuitry430may comprise a state machine, a sequencer, or other suitable controller circuitry. The system400may comprise any number of devices, as noted previously, including a single memory storage device, such as a flash memory, including a NAND-type or NOR-type flash memory.

FIG. 5is a flow diagram illustrating a method500of programming flash memory cells using a method, according to various embodiments. Referring also again toFIGS. 1-4, it may be seen that at510, a write command may be received by the control circuitry430ofFIG. 4to write data to one or more memory cells of the memory array460(e.g., memory cell167ofFIG. 1). The data may comprise a single bit or multiple bits that may be represented by one of the program states shown by the Vt voltage distributions ofFIG. 2. As previously described, the programming voltage pulses (310) may be generated at520and applied to a selected control gate (e.g., the control gate of memory cell167shown inFIG. 1).

As part of the program verify at530, the control circuitry430may operate to determine whether the memory cell167has been properly programmed, i.e., whether the Vt associated with the memory cell167has reached the selected PV voltage. To accomplish this determination as part of decision540, the control circuitry430may perform a read of the memory cell167to determine its content and may compare the content against a desired value (such as the PV voltage). When it is determined at decision540that the memory cell167has been satisfactorily programmed, its drain connection (i.e., the bit line BL2ofFIG. 1to which the memory cell167is connected) may be biased during operation550at a program inhibit voltage (e.g., Vinhibit). In the various embodiments, the Vinhibitmay comprise VCC; however, other suitable values may also be used.

When the control circuitry430determines that the memory cell167is not yet programmed with the desired data at decision540, control may pass to decision560. At decision560, the control circuitry430may operate to check Vt for the memory cell167to determine whether it has reached the single PPV voltage level for the desired programmed state (e.g., programmed state203ofFIG. 2). Each programmed state may have a single associated PPV voltage. When the threshold voltage for that programmed state reaches the associated PPV voltage, at570, the control circuitry430may operate to slow down programming of the memory cell167. Programming may be slowed down by automatically incrementing the BL voltage in particular increments, as shown by graph330inFIG. 3, and the BL (e.g., BL2shown inFIG. 1) coupled to the memory cell167. In the various embodiments, the BL voltage may be incremented during a single PPV stage that spans the time from when the Vt reaches the PPV voltage, until the Vt reaches the PV point as shown inFIG. 3. Unlike Dual-SSPC operations, additional pre-verification actions are not needed.

Such a method selectively slows the programming of each memory cell that has passed the PPV point352indicated inFIG. 3to accommodate the desired programmed state being programmed into that memory cell. Other memory cells being programmed may be unaffected by the BL biasing and may be allowed to be programmed at their normal programming speed. Accordingly, the Vt distribution (e.g., Vt distribution203ofFIG. 2) may be narrowed without significantly reducing the programming throughput.

The PPV voltage associated with the PPV point352, as illustrated inFIG. 3and discussed subsequently, may be less than the PV voltage. For example, in the various embodiments, a first programmed state (i.e., “10”) may have a PPV voltage of 0.3V and a PV voltage of 0.5V. In accordance with the various embodiments, these and other voltages may be used. For example, the PV voltage may be associated with a measured value of drain current for the memory cell being programmed. Biasing the BL in this way may reduce the voltage drop across the memory cell transistor, thus reducing the effective programming voltage applied to the memory cell. Accordingly, a lower programming voltage may generally include a slower movement of the voltage Vt for that memory cell. For example, the BL bias voltage range may comprise 0.5 to 0.9 volts. The various embodiments are not limited to any one voltage or range of voltages.

After the BL voltage has been incremented at570, the control circuitry430may operate to increase the program voltage during580by a program step voltage, and the programming process may repeat by generating another program voltage pulse during520. For example, the program increment voltage may comprise a 200 mV increment voltage, although the program increment voltage is not specifically limited to value, so that other values may be used.

At decision560, when it is determined that the voltage Vt has not reached the PPV voltage, the control circuitry430may operate to increase the program voltage at590by the program increment voltage. The control circuitry430may pass control at520so that the programming process can repeat until the PPV voltage level is reached. The control circuitry430may operate to adjust the BL voltage to slow the programming of the memory cell167, and the memory cell167may be eventually programmed such that the BL voltage is increased to the inhibit voltage.

FIG. 6is a diagram illustrating an ASSPC method600, according to the various embodiments. The ASSPC method600shows the increments in Vt for a programmed memory cell (e.g., memory cell167ofFIG. 1) as leaps610-640across a Vt voltage axis650. The leaps610-640may correspond to Vt steps resulting from application of the program voltage pulses shown by graph310ofFIG. 3.

The PPV voltage, as shown inFIG. 6, may be smaller than the PV voltage by an amount approximately equal to about three-fourths of a program voltage step (e.g., three-fourths of a voltage Vg step, or 3 Vg/4 in various embodiments). The second leap620may take the voltage Vt past the PPV voltage. As a result, the control circuitry430ofFIG. 4may operate to automatically increase the BL voltage (e.g., BL2shown inFIG. 1) in multiple increments. InFIG. 6, the Vt increment (e.g., second leap620) before PPV is substantially equal to a program step (e.g., one times the voltage Vg step, or Vg, in various embodiments). However, as a result of the increase in the BL voltage by approximately one-half Vg step, the next Vt step, shown as leap630, is decreased to approximately one-half Vg step (or Vg/2). A subsequent increment in the BL voltage may cause further slowing in the programming operation by reducing the Vt step voltage to about one-fourth Vg step (or Vg/4) at leap640. This last step has eventually landed the voltage Vt approximately in the middle of the target Vt distribution642. In various embodiments, the PV voltage may be associated with a measured value of drain current for the memory cell being programmed. The last step change in the voltage Vt may operate to complete the programming of the memory cell167.

Other memory cells may be programmed in a substantially similar manner. The Vt distribution642indicates that the majority of memory cells of the memory array100ofFIG. 1may behave similarly to memory cell167. In other words, the Vt voltage distribution at each point on the Vt voltage axis650may indicate the possibility that such a method may operate to distribute the voltage Vt of certain memory cells at that point.

One benefit of the one or more methods discussed herein, as compared to more conventional methods (e.g., selective slow program convergence (SSPC) and Dual SSPC methods), is that such a method may result in a Vt distribution that is reduced by approximately 50% (about half the width) of the Vt distribution in an SSPC method, with fewer program verify stages than the Dual SSPC method. One of many benefits may include rendering the memory array more reliable and facilitate implementing MLCs with more programmed states (i.e. capable of storing more bits). A second benefit (i.e., fewer PPV stages) may include speeding up the programming time of memory cells.

Example methods of improving program voltage distribution using methods according to various embodiments, along with devices and systems that include them, have been described. Although various embodiments have been described, it will be evident that additional various modifications and changes may be made to these embodiments. Accordingly, the specification and drawings are to be regarded as illustrative rather than in a restrictive sense.

The accompanying drawings that form a part hereof, show by way of illustration, and not of limitation, various embodiments in which the subject matter may be practiced. The various embodiments illustrated are described in sufficient detail to enable those skilled in the art to practice the teachings disclosed herein. Other additional embodiments may be utilized and derived therefrom, such that structural and logical substitutions and changes may be made without departing from the scope of this disclosure. This Detailed Description, therefore, is not to be taken in any limiting sense, and the scope of various embodiments is defined only by the appended claims, along with the full range of equivalents to which such claims are entitled.