PROCESSOR FOR EXECUTING INSTRUCTIONS IN UNITS THAT ARE UNRELATED TO THE UNITS IN WHICH INSTRUCTIONS ARE READ, AND A COMPILER, AN OPTIMIZATION APPARATUS, AN ASSEMBLER, A LINKER, A DEBUGGER AND A DISASSEMBLER FOR SUCH PROCESSOR

When a branch instruction is decoded by the instruction decoders 409a˜409c, the upper 29 bits of the PC relative value included in the branch instruction are sent to the upper PC calculator 411 and the lower 3 bits are sent to the lower PC calculator 405. The lower PC calculator 405 adds the lower 3 bits of the PC relative value and the lower 3 bits of the present lower PC 404 and sends the result to the lower PC 404 as the updated lower PC. The upper PC calculator 411 adds the upper 29 bits of the PC relative value, the upper 29 bits of the present upper PC 403, and a carry that may be received from the lower PC calculator 405, and sends the result to the upper PC 403 as the updated upper PC.

This application is based on an application No. H10-118326 filed in Japan, the content of which is hereby incorporated by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a processor for executing instructions in units that are unrelated to the units in which instructions are read, and a compiler, an optimization apparatus, an assembler, a linker, a debugger and a disassembler for such processor.

2. Description of the Prior Art

Processors conventionally read and execute instructions stored in memory according to a program counter.FIG. 1is a block diagram showing the basic construction of an example processor.

The instruction memory4301stores four 8-bit instructions as one instruction packet.

The program counter4300indicates the address of an instruction packet in the instruction memory4301.

The instruction reading unit4302reads the instruction packet indicated by the program counter4300from the instruction memory4301.

The instruction executing unit4303executes all four instructions included in the read instruction packet in one cycle.

In this way, a conventional processor can read an instruction packet that is indicated by the program counter and can execute four instructions in the instruction packet.

The above processor has to execute all of the instructions in the read instruction packet in one cycle. Accordingly, when one or more instructions in an instruction packet cannot be executed due to problems with computer system resources such as memory or I/O, none of the instructions in the instruction packet can be executed until such problems are resolved. This slows program execution.

SUMMARY OF THE INVENTION

In view of the stated problems, it is a primary object of the present invention to provide a processor that executes instructions in units that are unrelated to the units in which instructions are read from a program and a program development environment for generating suitable programs.

This primary object is achieved by a processor for reading instructions from a memory according to a program counter, the memory storing instructions in one-byte units, and for executing the read instructions, the program counter including a first program counter and a second program counter, the first program counter indicating a storage position of a processing packet in the memory, the processing packet being composed of an integer number of the one-byte units, the second program counter indicating a position of processing target instruction in the processing packet, the processing target instruction being an operation to be executed by the processor.

With the stated construction, the first program counter indicates a storage position in the memory of a processing packet whose size is an integer number of bytes. Reads from the memory are performed based on this first program counter. The second program counter can indicate any position of a processing target instruction included in the processing packet read from the memory. As a result, the instruction(s) to be executed can be freely set regardless of the amount of data read in one read operation. This means that instructions whose word length is not an integer number of bytes can be executed even when read operations from the memory to the processor are performed in units of an integer number of bytes.

Here, the processor may include a first program counter updating unit and a second program counter updating unit, the second program counter updating unit incrementing a value of the second program counter in accordance with an amount of instructions that were executed in a preceding cycle and sending any carry generated in an incrementing to the first program counter updating unit, and the first program counter updating unit adding the carry received from the second program counter updating unit to the value of the first program counter.

With the stated construction, the value of the program counter is incremented by the amount of instructions that have just been executed, so that the program counter can be updated to indicate the first position of the instructions to be executed in the next cycle.

Here, the processor may further include: a program counter relative value extracting unit for extracting, when an instruction being executed includes a program counter relative value that is based on an address of a first instruction executed in a present cycle, the program counter relative value; and a calculating unit for adding the program counter relative value to the value of the first program counter and the value of the second program counter, and setting an addition result as the value of the first program counter and the value of the second program counter.

When the processor executes a branch instruction, the value of the program counter is added to a program counter relative value that is a difference in addresses between the present branch instruction and the branch destination instruction. The result of this addition is then set as the new value of the program counter to have the program counter indicate the branch destination instruction.

Here, the calculating unit may include a first calculating unit and a second calculating unit, the second calculating unit adding the value of the second program counter and lower bits of the program counter relative value, setting a result of an addition as the value of the second program counter, and sending any carry generated in the addition to the first calculating unit, and the first calculating unit adding the value of the first program counter, upper bits of the program counter relative value, and any carry received from the second calculating unit, and setting a result of an addition as the value of the first program counter.

When the processor executes a branch instruction and the program counter and a program counter relative value are added, a carry generated when calculating the lower bits is properly considered when calculating the upper bits. In this way, addresses can be calculated with proper continuity between the calculation of the lower bits and the calculation of the upper bits.

Here, the calculating unit may include a first calculating unit and a second calculating unit, the second calculating unit adding the value of the second program counter and lower bits of the program counter relative value without generating a carry, and setting a result of an addition as the value of the second program counter, the first calculating unit adding the value of the first program counter and upper bits of the program counter relative value, and setting a result of an addition as the value of the first program counter.

When the processor executes a branch instruction, calculation of the lower bits of the value of the program counter and the program counter relative value by the second calculating unit does not generate a carry to the calculation of the upper bits of the value of the program counter and the program counter relative value by the first calculating unit. As a result, the calculations of the first and second calculators can be performed independently of one another, so that a simplified hardware construction can be used.

Here, the calculating unit may add the value of the first program counter and upper bits of the program counter relative value, sets a result of an addition as the value of the first program counter, and sets lower bits of the program counter relative value as the value of the second program counter.

When the processor executes a branch instruction, no calculation using the value of the second program counter and the lower bits of the program counter relative value is required, so that the processor can execute branch instructions at a higher speed.

Here, the calculating unit may add the program counter relative value and a value whose upper bits are the value of the first program counter and lower bits are the value of the second program counter, and sets upper bits of a result of an addition as the value of the first program countermand lower bits of the result as the second program counter.

When the processor executes a branch instruction, the calculation using the value of the program counter and the program counter relative value can be performed by a standard calculator. This means the hardware construction of the processor can be simplified.

Here, the processor may further include: a program counter relative value extracting unit for extracting, when an executed instruction includes a program counter relative value that is based on an address of the executed instruction, the program counter relative value; a program counter amending unit for amending the value of the first program counter and the value of the second program counter to indicate an address of the executed instruction; and a calculating unit for adding the program counter relative value, the value of the first program counter, and the value of the second program counter, and setting a result of an addition as the value of the first program counter and the value of the second program counter.

The program counter relative value is the difference in addresses between a branch instruction and the branch destination instruction, so that it will not be necessary to change the program counter relative value even when there is a change in the boundaries marking which instructions in the program will be executed in parallel.

Here, the processor may further include: a program counter relative value calculating instruction decoding unit for decoding a program counter relative value calculating instruction that performs an addition using a program counter relative value and one of (a) a value of the program counter stored in a register, and (b) the value of the first program counter and the value of the second program counter; a calculating unit for performing the addition indicated by the program counter relative value calculating instruction to generate an addition result; and a program counter value updating unit for storing the addition result in one of (a) the register, and (b) the first program counter and the second program counter.

With the stated construction, it is possible to use an instruction that indicates a calculation using the value of the program counter and a program counter relative value in place of an instruction that stores the absolute address of a function into a register. A program counter relative value has a shorter bit width that the absolute address of an instruction, so that the overall code size can be reduced. When using PIC codes where the addresses of instructions in memory are only determined when the program is executed, absolute addresses cannot be used, so that calculation instructions that use the program counter and a program counter relative value are essential.

Here, the first program counter may indicate a memory address, the memory address being a storage position in the memory of a processing packet that is given by bit shifting the value in the first program counter by log2n bits in a leftward direction, n being a length of a processing packet in bytes.

With the stated construction, while separate addresses are assigned to each one-byte storage packet in the memory, the value of the first program counter corresponds with the address of a processing packet in the the memory. As a result, the processor can easily specify a processing packet in the memory.

Here, the processor may further include: an instruction buffer for temporarily storing instructions; and an instruction reading unit for transferring instructions with a minimum transfer size of one one-byte unit from the memory to the instruction buffer, in accordance with available space in the instruction buffer but regardless of a size of a processing packet.

With the stated construction, the amount of data read by the processor from the memory in one read operation can be freely set, so that the construction in the processor for reading instructions can be made highly flexible.

The stated primary object can also be achieved by an instruction sequence optimizing apparatus, for generating optimized code from an instruction sequence, including: an address assigning unit for estimating a size of each instruction in the instruction sequence and assigning an address to each instruction, upper bits of each address indicating a memory address at which a processing packet is stored and lower bits of each address indicating a processing target instruction in the processing packet; a label detecting unit (1) for detecting a label, which should be resolved by an address of a specified instruct on, from the instruction sequence, and obtaining the address of the specified instruction, and (2) for detecting a label, which should be resolved by a difference in addresses of two specified instructions, from the instruction sequence, and obtaining the addresses of the two specified instructions; a program counter relative value calculating unit for calculating, when a label which should be resolved by a difference in addresses of two specified instructions has been detected, a program counter relative value by subtracting an address of one of the two specified instructions from an address of another of the two specified instructions; a converting unit (1) for converting an instruction that has a label that should be resolved by an address of a specified instruction into an instruction with a size that is based on a size of the address of the specified instruction, (2) for converting an instruction that has a label that should be resolved by a difference in addresses of two specified instructions into an instruction with a size that is based on a size of the program counter relative value calculated from the addresses of the two specified instructions; and an optimized code generating unit for generating optimized code by converting addresses of instructions in accordance with the sizes of instructions after conversion by the converting unit.

The above construction achieves an optimization apparatus for generating programs for a processor that executes branch instructions.

Here, the program counter relative value calculating unit may include a lower bit subtracting unit and an upper bit subtracting unit, the lower bit subtracting unit subtracting lower bits of the address of the one of the two specified instructions from lower bits of the address of the other of the two specified instructions, for setting a result of a subtraction as lower bits of the program counter relative value, and sending any carry generated in the subtraction to the upper bit subtracting unit, and the upper bit subtracting unit subtracting upper bits of the address of one of the two specified instructions and any carry received from the lower bit subtracting unit from upper bits of the address of the other of the two specified instructions, and for setting a result of a subtraction as upper bits of the program counter relative value.

The above construction achieves an optimization apparatus for generating programs for a processor which, when executing a branch instruction, calculates the address of a branch destination instruction using a carry method.

Here, the program counter relative value calculating unit may include a lower bit subtracting unit and an upper bit subtracting unit, the lower bit subtracting unit subtracting lower bits of the address of one of the two specified instructions from lower bits of the address of the other of the two specified instructions without generating a carry and setting a result of a subtraction as lower bits of the program counter relative value, and the upper bit subtracting unit subtracting upper bits of the address of one of the two specified instructions from upper bits of the address of the other of the two specified instructions, and for setting a result of a subtraction as upper bits of the program counter relative value.

The above construction achieves an optimization apparatus for generating programs for a processor which, when executing a branch instruction, calculates the address of a branch destination instruction without using a carry.

Here, the program counter relative value calculating unit may subtract upper bits of an address of one of the two specified instructions from upper bits of an address of the other of the two specified instructions, set a result of a subtraction as upper bits of the program counter relative value, and set lower bits of the other of the two specified instructions as lower bits of the program counter relative value.

The above construction achieves an optimization apparatus for generating programs for a processor which, when executing a branch instruction, calculates the address of a branch destination instruction using an absolute value.

The stated primary object can also be achieved by an assembler that generates relocatable code from an instruction sequence, each address of an instruction in the instruction sequence having upper bits that indicate a memory address at which a processing packet is stored and lower bits that indicate a position of processing target instruction that is included in the processing packet, the assembler including: a label detecting unit for detecting a label in the instruction sequence that should be resolved by a difference in addresses between two specified instructions, and obtaining the addresses of the two specifies instructions; a program counter relative value calculating unit for calculating a program counter relative value by subtracting an address of one of the two specified instructions from an address of another of the two specified instructions; and a replacing unit for replacing the label with the program counter relative value calculated by the program counter relative value calculating unit.

The above construction achieves an assembler for generating programs for a processor that executes branch instructions.

Here, the program counter relative value calculating unit may include a lower bit subtracting unit and an upper hit subtracting unit, the lower bit subtracting unit subtracting lower bits of the address of the one of the two specified instructions from lower bits of the address of the other of the two specified instructions, for setting a result of a subtraction as lower bits of the program counter relative value, and sending any carry generated in the subtraction to the upper bit subtracting unit, and the upper bit subtracting unit subtracting upper bits of the address of one of the two specified instructions and any carry received from the lower bit subtracting unit from upper bits of the address of the other of the two specified instructions, and for setting a result of a subtraction as upper bits of the program counter relative value.

The above construction achieves an assembler for generating programs for a processor which, when executing a branch instruction, calculates the address of a branch destination instruction using a carry method.

Here, the program counter relative value calculating unit may include a lower bit subtracting unit and an upper bit subtracting unit, the lower bit subtracting unit subtracting lower bits of the address of one of the two specified instructions from lower bits of the address of the other of the two specified instructions without generating a carry and setting a result of a subtraction as lower bits of the program counter relative value, and the upper bit subtracting unit subtracting upper bits of the address of one of the two specified instructions from upper bits of the address of the other of the two specified instructions, and for setting a result of a subtraction as upper bits of the program counter relative value.

The above construction achieves an assembler for generating programs for a processor which, when executing a branch instruction, calculates the address of a branch destination instruction without using a carry.

Here, the program counter relative value calculating unit may subtract upper bits of an address of one of the two specified instructions from upper bits of an address of the other of the two specified instructions, set a result of a subtraction as upper bits of the program counter relative value, and set lower bits of the other of the two specified instructions as lower bits of the program counter relative value.

The above construction achieves an optimization apparatus for generating programs for a processor which, when executing a branch instruction, calculates the address of a branch destination instruction using an absolute value.

The stated primary object can also be achieved by a linker that generates object code by combining relocatable code, each address of an instruction in the relocatable code having upper bits that indicate a memory address at which a processing packet is stored and lower bits that indicate a position of processing target instruction that is included in the processing packet, the linker including: a relocation information detecting unit for detecting a label in the relocatable code that should be resolved by a difference in addresses between two specified instructions, and obtaining the addresses of the two specified instructions; a program counter relative value calculating unit for calculating a program counter relative value by subtracting an address of one of the two specified instructions from an address of another of the two specified instructions; and a replacing unit for replacing the label with the program counter relative value calculated by the program counter relative value calculating unit.

The above construction achieves a linker for generating programs for a processor that executes branch instructions.

Here, the program counter relative value calculating unit may include a lower bit subtracting unit and an upper bit subtracting unit, the lower bit subtracting unit subtracting lower bits of the address of the one of the two specified instructions from lower bits of the address of the other of the two specified instructions, for setting a result of a subtraction as lower bits of the program counter relative value, and sending any carry generated in the subtraction to the upper bit subtracting unit, and the upper bit subtracting unit subtracting upper bits of the address of one of the two specified instructions and any carry received from the lower bit subtracting unit from upper bits of the address of the other of the two specified instructions, and for setting a result of a subtraction as upper bits of the program counter relative value.

The above construction achieves a linker for generating programs for a processor which, when executing a branch instruction, calculates the address of a branch destination instruction using a carry method.

Here, the program counter relative value calculating unit may include a lower bit subtracting unit and an upper bit subtracting unit, the lower bit subtracting unit subtracting lower bits of the address of one of the two specified instructions from lower bits of the address of the other of the two specified instructions without generating a carry and setting a result of a subtraction as lower bits of the program counter relative value, and the upper bit subtracting unit subtracting upper bits of the address of one of the two specified instructions from upper bits of the address of the other of the two specified instructions, and for setting a result of a subtraction as upper bits of the program counter relative value.

The above construction achieves a linker for generating programs for a processor which, when executing a branch instruction, calculates the address of a branch destination instruction without using a carry.

Here, the program counter relative value calculating unit may subtract upper bits of an address of one of the two specified instructions from upper bits of an address of the other of the two specified instructions, set a result of a subtraction as upper bits of the program counter relative value, and set lower bits of the other of the two specified instructions as lower bits of the program counter relative value.

The above construction achieves a linker for generating programs for a processor which, when executing a branch instruction, calculates the address of a branch destination instruction using an absolute value.

The stated primary object can also be achieved by a disassembler that receives an indication of an address of an instruction in object code and outputs an assembler name of the instruction at the indicated address, each address of an instruction in the object code having upper bits that indicate a memory address at which a processing packet is stored and lower bits that indicate a position of processing target instruction that is included in the processing packet, the disassembler including: a program counter relative value extracting unit for extracting, when the indicated instruction includes a program counter relative value, the program counter relative value from the indicated instruction; a label addressing calculating unit for adding an address of the indicated instruction to the extracted program counter relative value and setting an addition result as a label address; a storing unit for storing a label name corresponding to each label address; and a searching unit for searching the storing unit for a label name that corresponds to the calculated label address and outputting the corresponding label name.

The stated construction can disassemble a program that includes a branch instruction. When the disassembled instruction is a branch instruction, the address of the branch destination instruction can be calculated from the program counter relative value. This address is then used to search the label table and so obtain the label name. As a result, the branch destination can be displayed to the user in the readily understandable form of a label name, even when program counter relative values are used in branch instructions.

Here, the label address calculating unit may include a lower bit calculating unit and an upper bit calculating unit, the lower bit calculating unit for adding lower bits of the address of the indicated instruction and lower bits of the program counter relative value, setting a result of an addition as lower bits of a label address, and sending any carry generated by the addition to the upper bit calculating unit, and the upper bit calculating unit adding upper bits of the address of the indicated instruction, upper bits of the program counter relative value, and any carry received from the lower bit calculating unit, and setting a result of the an addition as upper bits of the label address.

The above construction achieves a disassembler that can disassemble programs for a processor which, when executing a branch instruction, calculates an address of a branch destination instruction using a carry.

Here, the label address calculating unit may include a lower bit calculating unit and an upper bit calculating unit, the lower bit calculating unit adding lower bits of the program counter relative value without generating a carry, and setting a result of an addition as lower bits of a label address, and the upper bit calculating unit adding upper bits of the address of the indicated instruction and upper bits of the program counter relative value, and setting a result of an addition as upper bits of the label address.

The above construction achieves a disassembler that can disassemble programs for a processor which, when executing a branch instruction, calculates an address of a branch destination instruction without using a carry.

Here, the label address calculating unit may add upper bits of the address of the indicated instruction and upper bits of the program counter relative value, set a result of an addition as upper bits of the label address, and set lower bits of the program counter relative value as lower bits of the label address.

The above construction achieves a disassembler that can disassemble programs for a processor which, when executing a branch instruction, calculates an address of a branch destination instruction using an absolute value.

The stated primary object can also be achieved by a debugger that receives an indication of an address of an instruction in object code and replaces the instruction at the indicated address with a replacement instruction, each address of an instruction in the object code having upper bits that indicate a memory address at which a processing packet is stored and lower bits that indicate a position of processing target instruction that is included in the processing packet, the debugger including: a processing packet reading unit for reading a processing packet that is indicated by upper bits or the indicated address from the memory and writing the processing packet into an instruction buffer; an instruction writing unit for writing the replacement instruction into the processing packet in the instruction buffer over an instruction that is indicated by the lower bits of the indicated address; and a processing packet writing unit for writing the processing packet in the instruction buffer back into the memory after the replacement instruction has been written.

The above construction reads instructions in units of processing packets from a memory that stores instructions in one-byte storage packets, rewrites instructions in an instruct on buffer, and writes instructions back into the memory in units of processing packets. This achieves a debugger that can debug instructions whose length is not an integer number of bytes.

The stated primary object can also be achieved by a compiler that generates an instruction sequence from source code, the compiler generating a program counter relative value calculating instruction that is executed by a processor, the program counter relative value calculating instruction being an instruction that performs a calculation using a first value and a program counter relative value and uses a result of the calculation to update the first value, the first value being one of (a) a value of the program counter stored in a register, and (b) the value stored in a program counter of the processor, wherein upper bits of the first value indicate a memory address at which a processing packet is stored, and lower bits of the first value of the program counter indicate a processing target instruction that is included in the processing packet.

The above construction achieves a compiler that generates programs for a processor that executes program counter relative value calculating instructions.

Here, the processor may include a lower bit calculating unit and an upper bit calculating unit, the program counter relative value calculating instruction having the lower bit calculating unit perform a lower bit calculation and the upper bit calculating unit perform an upper bit calculation, the lower bit calculation being an addition using lower bits of the first value and lower bits of the value of the program counter relative value, where a result of the lower bit calculation is set as the lower bits of the first value and any generated carry is sent to the upper bit calculating unit, and the upper bit calculation being an addition using upper bits of the first value, upper bits of the value of the program counter relative value and any carry received from the lower bit calculation is set as the upper bits of the first value.

The above construction achieves a compiler that generates a program for a processor which, when executing a program counter relative value calculating instruction, performs a calculation using a value of the program counter and the program counter relative value according to a carry method.

Here, the processor may include a lower bit calculating unit and an upper bit calculating unit, the program counter relative value calculating instruction having the lower bit calculating unit perform a lower bit calculation and the upper bit calculating unit perform an upper bit calculation, the lower bit calculation being an addition using lower bits of the first value and lower bits of the value of the program counter relative value that does not generate a carry, where a result of the lower bit calculation is set as the lower bits of the first value, and the upper bit calculation being a calculation using upper bits of the first value and upper bits of the value of the program counter relative value, where a result of the upper bit calculation is set as the upper bits of the first value.

The above construction achieves a compiler that generates a program for a processor which, when executing a program counter relative value calculating instruction, performs a calculation using a value of the program counter and the program counter relative value without generating a carry.

Here, the processor may includes an upper bit calculating unit, the program counter relative value calculating instruction having the upper bit calculating unit perform an upper bit calculation and setting lower bits of the program counter relative value as lower bits of the first value, and the upper bit calculation being an addition using upper bits of the first value and upper bits of the value of the program counter relative value, where a result of the upper bit calculation is set as the upper bits of the first value.

The above construction achieves a compiler that generates a program for a processor which, when executing a program counter relative value calculating instruction, performs a calculation using a value of the program counter and the program counter relative value according to an absolute value calculating method.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The following is a detailed description of several embodiments of the present invention, with reference to the accompanying drawings.

First Embodiment

This first embodiment relates to an optimization apparatus, an assembler, and a linker that generate programs where read operations and execute operations have different units, and to a processor for executing such programs.

Formats of the Instructions Executed by the Processor

The following explains the formats of the instructions executed by the processor of this first embodiment. These formats are shown inFIGS. 2A-2E. The instructions executed by the present processor are constructed so that 21 bits is set as one instruction unit. For the present processor, there are both one-unit (i.e., 21-bit) and two unit (i.e., 42-bit) instructions.

The format information101is written as one bit and shows the length of each instruction. When the format information101is “0”, this shows that the unit including this format information101forms one complete instruction, which is to say, a 21-bit instruction. When the format information101is “1”, this shows that the unit including this format information101and the following unit together form one two-unit instruction, which is to say, a 42-bit instruction.

The parallel execution boundary information100is also written as one bit and shows whether a parallel execution boundary exists between the instruction formed by the present unit and the following instruction. When the parallel execution boundary information100is “1”, this shows that a parallel execution boundary exists between the instruction including this parallel execution boundary information100and the following instruction, so that these instructions will be executed in different cycles. When the parallel execution boundary information100is “0”, this shows that no parallel execution boundary exists between the instruction including this parallel execution boundary information100and the following instruction, so that these instructions will be executed the same cycle.

The remaining bits in each instruction are used to show an operation. This means that 19 bits can be used to indicate, the operation in a 21-bit instruction and that 40 bits can be used to indicate the operation in a 42-bit instruction. The fields marked “Op1”, “Op2”, “Op3”, and “Op4” are used to store opcodes that indicate the type of operations to be performed. The field marked “Rs” is used to store the register number of a register used as the source operand and the field marked “Rd” is used to store the register number of a register used as the destination operand. The fields marked “imm5” and “imm32” are respectively used to store 5-bit and 32-bit immediates that are used in calculations. Finally, the fields marked “disp13” and “disp32” are respectively used to store 13-bit and 32-bit displacements.

Transfer instructions and arithmetic instructions that handle long (such as 32-bit) constants and branch instructions that use large displacements are defined as 42-bit instructions. Most other instructions are defined as 21-bit instructions. Of the two units used to compose a 42-bit instruction, the latter unit is only used to store part of the long constant or displacement, and so does not store the opcode of the instruction.

Reading and Execution of Instructions by the Processor

The following explains the operation of the present processor when reading and executing instructions. Note that the processor of the present embodiment has a premise that static parallel scheduling is used.FIG. 3Ashows an instruction packet that is the unit used for storing and reading instructions. Each instruction packet is composed of three instruction units (63 bits) and dummy data (1 bit). In each cycle, the processor reads instructions using this fixed 64-bit packet length. Packets of this size are used because the 21-bit unit size of instruction is not suited to reading from memory. Accordingly, a number of such instructions are read together with dummy data to make the total packet size equal to an integer number or bytes. In this example, since the number of instruction units in each instruction packet is not a power of two, there is the following special effect. This effect overcomes the problems that occur when positions of the units inside instruction packets are expressed using binary. In the following explanation, the three units in an instruction packet are called the first, second and third units in order starting from the unit with the lowest address value.

FIG. 3Bshows the read order of instructions. As shown in the figure, one instruction packet is read in each cycle.

FIG. 3Cshows the execution order of instructions. In each cycle, instructions are executed as far as the next parallel execution boundary. This means that the instructions are executed up to and including an instruction whose parallel execution boundary information100is “1”. Instruction units that are read but not executed are accumulated in the instruction buffer, and are executed in a later cycle.

As described above, the processor of the present embodiments reads instructions using packets of a fixed length, but only executes a suitable number of units in each cycle depending on parallelism of the instructions. The reason that the present processor can start the execution of instructions in one cycle at any of the instruction units in an instruction packet is that an in-packet address specifies an instruction unit in an instruction packet. This is described in more detail later.

FIG. 4shows an example of the methods used by a conventional processor to store and read instructions that are not byte-aligned. When 21-bit instructions that are not byte-aligned are to be read in byte-units, three unused bits have to be added to the end of each instruction to make the instruction length 24-bits. This means that what are essentially 21-bit instructions are stored into and read from memory in 24-bit units. The length of three of such instructions is 72 bits, so that the storage of three instructions in a 64-bit packet in the present embodiment reduces overall program size.

Note that while the present embodiment describes the packet construction when 21-bit instructions are used, the invention is not limited to this instruction length. It is equally possible to construct instruction packets of instructions of a different length and to read the instructions using such instruction packets. As one example, when instructions are n-bits long, values of m and may be selected so as to give a maximum value of n*m+(n*m+r) subject to (n*m+r)mod8=0. One packet is then composed of m instruction units (each being n bits long) and r-bit dummy data. By doing so, instruction packets can be composed of multiple-byte size using relatively little dummy data.

Method for Expressing Instruction Addresses

The following explains the method used to express instruction addresses in the present embodiment. Here, an instruct on address refers to the address used to specify the position of a unit and is expressed as 32 bits.

The upper 29-bits of a 32-bit address are used to specify an instruction packet and so are called the “packet address”. This packet address is expressed as a 29-bit hexadecimal figure in a format such as “29′h01234567”. A value produced by shifting the value of this packet address by 3-bits to the left is the memory address at which the instruction packet is stored.

The lower 3-bits in a 32-bit address are used to specify an instruction unit included in the instruction packet and so are called the “in-packet address”. This in-packet address is expressed as a 3-bit binary value in a format such as “3′b001”. As examples, the in-packet address “3′b001” specifies the first unit in an instruction packet, the in-packet address “3′b010” specifies the second unit, and the in-packet address “3′b010” specifies the third unit. However, the in-packet addresses are not limited to these specific values. Other values may be used provided that the instruction units in an instruction packet are each specified using their own value.

The indicating of addresses in this embodiment is such that only 3 bits are assigned for eight-bytes of instructions. This gives the same results as when a conventional processor assigns a separate address to each byte, since the upper 29-bits of addresses assigned to eight-bytes of instructions will be the same.

Method for Generating the Object Code Executed by the Processor

The following explains the method for generating the object code that is executed by the processor of the present embodiment.

First, the terminology to be used in this explanation is defined.

A “PC relative value” is the difference between the addresses of two instructions.

A “label” is either an “instruction address-resolved label” or a “PC relative value-resolved label”. Absolute address-resolved labels are replaced with absolute addresses of instructions during the processing that converts a program into object code. An example of such a label is the label “L2” in the transfer instruction “mov L2,r1” that transfers an instruction stored in memory to the register r1. PC relative value-resolved labels are replaced with PC relative values during the processing that converts a program into object code. An example of such a label is the label “L1” in the unconditional branch instruction “bra L1” that performs an unconditional branch using the PC relative value. “Local labels” and “external labels” also exist as other types of label. When a label and the instruction including the label are included in the same module (a module being a subprogram composed of an instruction sequence achieving one processing function), such label is called a local label, while when the label and instruction including the label are included in different modules, such label is called an external label.

FIG. 5shows the procedure by which the object code to be executed by the processor is generated by a compiler, optimization apparatus, assembler, and linker. An overview of the functions of these components is given below.

The compiler301analyzes the content of the source code300that is written in a high-level language like C and outputs assembler code302.

The optimization apparatus303assigns temporary addresses to the assembler code302, links the instruction sequences in groups of three instruction units, and outputs optimized code304as the linked results. In this process, local labels are calculated as PC relative values or instruction addresses. The instruction size, which is to say, whether an instruction should be expected as a one-unit instruction or as a two-unit instruction, is then determined based on the value of the PC relative value or the instruction address.

The assembler305outputs relocatable codes306which it generates from the optimized code304. This processing converts local labels that should be resolved with PC relative, values into PC relative values.

The linker307combines a plurality of modules. That is, the linker307combines a plurality of relocatable codes306and outputs the resulting object code308. In this processing, unresolved labels are converted into PC relative values or instruction addresses.

The processor309executes the object code308.

As described above, a program written in a high-level language is converted by the compiler301, the optimization apparatus303, the assembler305, and the linker307into object code that is in a format executable by the processor. Each label in the program is converted into a PC relative value or an instruction address by one of the steps in the above procedure. Address resolution for local labels that should be resolved by a PC relative value is performed by the assembler305. Address resolution for local lapels that should be resolved by an instruction address and address resolution for external labels are performed by the linker307.

The following describes the construction and operation of the processor309, the linker307, the assembler305, and the optimization apparatus303shown in FIG.4.

Processor

FIG. 6is a block diagram showing the details of the processor309and the external memory.

The processor309is capable of executing a maximum of three instructions in parallel. This processor309includes calculators401a˜401c, general registers402, an upper PC403, a lower PC404, an upper PC calculator411, a lower PC calculator405, an INC412, an instruction buffer408, an prefetch upper counter410, a prefetch lower counter413, instruction decoder409a-409c, a PC relative value selector420, an immediate selector421, an operand data buffer423, and an operand address buffer422. The external memory includes the data memory406and the instruction memory407.

In the following explanation, the upper PC403and the lower PC404will be collectively referred to as the “PC”, and the upper PC calculator411and the lower PC calculator405will be collectively referred to as the “PC calculator”.

The first calculator401a, the second calculator401b, and the third calculator401ceach perform one calculation. These calculators are capable of calculating at the same time.

The general registers402store data, addresses and other data.

The upper PC403stores the upper 29 bits of the address of the first instruction in a set of instructions to be executed in the next cycle, which is to say, a packet address.

The lower PC404stores the lower 3 bits of the address of the first instruction in a set of instructions to be executed in the next cycle, which is to say, an in-packet address.

The instruction memory407stores instructions that are expressed by the object code308.

The instruction buffer408stores instructions that have been read from the instruction memory407.

The first instruction decoder409a, the second instruction decoder409b, and third instruction decoder409cdecode instructions and, if the respective instructions are executable, give indications to other components in the processor to have the instructions executed. The first instruction decoder409areceives an input of the first instruction stored in the instruction buffer408, the second instruction decoder409ban input of the next instruction, and the third instruction decoder409can input of a next instruction. These instruction decoders409a˜409cinvestigate whether there is a parallel execution boundary between the instruction units and only have the instructions that should be executed in the present cycle executed. As one example, when an instruction performs a calculation using a constant, the constant is sent to the first calculator401avia the immediate selector421and the first calculator401ais instructed to perform the calculation. For a branch instruction, a PC relative value is sent via the PC relative value selector420to the lower PC calculator405and upper PC calculator411that are then instructed to update the PC. The instruction decoders409a˜409csend control signals showing the number of executed instruction units to have the INC412update the PC increment, and send control signals showing the number of executed instruction units to the instruction buffer408to have the executed instruction units deleted from the instruction buffer408.

The PC relative value selector420outputs the PC relative value outputted by the instruction decoders409a˜409cto the lower PC calculator405and the upper PC calculator411.

The immediate selector421outputs an immediate outputted by the instruction decoders409a˜409cto the general registers402and the calculators401a˜401c.

The INC412receives information regarding the number of executed instruction units via control signals sent by the instruction decoders409a˜409c, and increments the value of the upper PC403and the lower PC404in accordance with this number. By doing so, the INC412sets the packet address of the first instruction in the set of instructions to be executed in the next cycle in the upper PC403and the in-packet address of the first instruction in the set of instructions to be executed in the next cycle in the lower PC404.

The upper PC calculator411and lower PC calculator405respectively update the upper PC403and the lower PC404. When a branch instruction is decoded by the instruction decoders409a˜409c, the upper PC calculator411and lower PC calculator405respectively receive the upper 29 bits and the lower 3 bits of the PC relative value included in the branch instruction of the PC relative value. The lower PC calculator405increases or decreases the present value of the lower PC404by the lower 3 bits in the PC relative value and sends the calculation result to the lower PC404as the new lower PC. The upper PC calculator411increases or decreases the present value of the upper PC403by the upper 29 bits in the PC relative value and sends the calculation result to the upper PC403as the new upper PC. This operation of the PC calculators is described later in this specification. As described above, when a branch instruction is executed, the packet address of the branch destination instruction that is to be executed next is set in the upper PC403and the in-packet address is set in the lower PC404. There are also cases where the upper PC calculator411and lower PC calculator405update the PC by calculating an address using a PC relative value and an address stored in the general registers402.

The prefetch upper counter410shows the upper 29 bits of the address of the first instruction in the set of instructions to be read from the instruction memory407, which is to say, the packet address. The prefetch upper counter410normally increments this value by one in each cycle. When a branch instruction was executed in the previous cycle, the packet address of the branch destination instruction set in the upper PC403is sent to the prefetch upper counter410where it is set in place of the present value in the prefetch upper counter410.

The prefetch lower counter413shows the lower 3 bits of the address of the first instruction in the set of instructions read from the instruction memory407, which is to say, the in-packet address. In this embodiment, the value “3′b000” is set in the prefetch lower counter413. As a result, the instructions to be read are indicated in packet units, so that one packet is sent from the instruction memory407to the instruction buffer408in each cycle.

The data memory406stores operand data.

The operand data buffer423and operand address buffer422are buffers that are located between the data memory406and the processor.

The following explains the incrementing method and calculating method for instruction addresses. This is the most characteristic feature of the present embodiment.

Incrementing Method for Instruction Addresses

The incrementing of addresses is performed by adding an increment value to the in-packet address of an instruction, and adding any carry produced by the addition to the packet address.

FIG. 7is an increment table showing the rules used to increment the in-packet address. As shown in the figure, when the in-packet address is “3′b000” or “3′b010”, the incrementing of the instruction address is performed by adding 2 to the in-packet address. When the in-packet address is “3′b100”, a carry to the packet address is produced (which is to say, 1 is to be added to the upper 29 bits of the instruction address) and the in-packet address is updated to “3′b000”. This means that the incrementing of the in-packet address is a calculation that cycles through the three values “3′b000”, “3′b010”, and “3′b100”. As one example, when the increment value is “2” and the value of the in-packet address before incrementing is “3′b100”, the packet address after incrementing is “3′b010” and a carry of “1” to the packet address is generated.

Note that in the present embodiment, the in-packet address does not need to be expressed in binary. This is especially effective when the number of instruction units in an instruction packet is not a power of 2. When this is the case, it is not possible to express the position of an instruction unit in an instruction packet in binary and use a binary calculation to shift the position of an instruction unit. However, in the present embodiment, the position of an instruction unit in an instruction packet is expressed using m different values. By using a calculation that cycles through these m values, the specifying of instruction units and the calculations for shifting the instruction position can be achieved even if the number of instruction units in an instruction packet is not a power of 2.

Method for Calculating the Instruction Address

The following explains the carry method which is one of the methods used for calculating the instruction addresses in the present invention. Other methods used to calculate addresses are a separation method, an absolute position indicating method, and a linear addressing method, though these will be described later in this specification. In the carry method, the upper 29 bits and lower 3 bits of an instruction address are calculated separately. However, when calculating the upper bits, any carry to or from the upper 29 bits that occurred when calculating the lower 3 bits is taken into account.

The following explains the method by which the present processor adds the address of a branch instruction and a PC relative value to find a branch destination address. The lower PC calculator405shown inFIG. 6adds the lower 3 bits of the address of a branch instruction to addition table showing the addition rules used when adding the lower 3 bits of the address of a branch instruction to the lower 3 bits of the PC relative value. As shown inFIG. 8A, this addition of the lower 3-bit values differs from a binary calculation in being a calculation that cycles through the three values “3′b000”, “3′b010”, and “3′b100”. When a carry occurs as shown inFIG. 8A, the lower PC calculator405sends the carry to the upper PC value to the upper PC calculator411.

The upper PC calculator411shown inFIG. 6adds the upper 29 bits of the address of a branch instruction to the upper 29 bits of the PC relative value. When doing so, if the calculation of the lower PC calculator405has resulted in a carry to the upper PC, the upper PC calculator411also adds this carry. This addition is a normal addition of binary values.

The addition results of the lower PC calculator405and upper PC calculator411form the address of the branch destination instruction. The addition result for the lower 3 bits is set in the lower PC404and the addition result for the upper 29 bits is set in the upper PC403.

The following explains the calculations of the optimization apparatus303, assembler305, and linker307for finding the PC relative value, which is to say the subtraction of the branch instruction address from the branch destination address. Like the addition described above, this subtraction is performed separately for the upper 29 bits and lower 3 bits. The lower address subtraction means907of the optimization apparatus303, the lower address subtraction means806of the assembler305, and the lower address subtraction means706of the linker307subtract the lower 3 bits of the branch instruction address from the lower 3 bits of the branch destination address.FIG. 8Bis a subtraction table showing the subtraction rules used when subtracting the lower 3 bits of the PC relative value from the lower 3 bits of a branch destination address. As shown inFIG. 8B, this subtraction of the lower 3-bit values differs from a binary calculation in being a calculation that cycles through the three values “3′b000”, “3′b010”, and “3′b100”. When a carry occurs as shown inFIG. 8B, the lower address subtraction means that performs the calculation (such as lower address subtraction means907) sends the carry from the upper PC value to the corresponding upper address subtraction means (such as upper address subtraction means910). The various upper address subtraction means are described in more detail later.

The upper address subtraction means910in the optimization apparatus303, the upper address subtraction means809in the assembler305, and upper address subtraction means709in the linker307subtract the upper 29 bits6fthe address of a branch instruction from the upper 29 bits of the address of the branch destination instruction. When doing so, if the calculation of the lower address subtraction means907(or similar) has resulted in a carry from the upper PC, the upper address subtraction means910(or similar) also subtracts this carry. This subtraction is a normal subtraction of binary values.

These subtraction results respectively form the lower 3 bits and the higher 29 bits of the PC relative value. This method is also used when the processor finds the address of a branch destination instruction by executing a subtraction on the address of a branch instruction and a PC relative value.

The optimization apparatus303, assembler305, and linker307, which calculate a PC relative value from the difference between the address of a branch destination instruction and the address of a branch instruction, and the processor309, which calculates the address of a branch destination instruction using this PC relative value, calculate addresses using the same carry method. As a result, when executing a branch instruction, the processor can correctly calculate the address of a branch destination instruction from the PC relative value. This address calculation method that uses a carry has a feature in that it can calculate addresses perform separate calculations for upper bits and lower bits while maintaining the continuity between the two.

Optimization Apparatus

FIG. 9is a block diagram showing the components and input/output data of the optimization apparatus303shown in FIG.5. This optimization apparatus303optimizes the assembler code302generated by the compiler301, links the instruction sequences together in packets of three instruction units, and outputs the resulting optimized code304. The optimization apparatus303includes a code optimization apparatus902, an address assigning means904, a label detecting means905, a lower address subtraction means907, an upper address subtraction means910, an address difference calculating means912, and a label information resolving means914.

The code optimization apparatus902optimizes the assembler code302and so generates the optimization processing code903. This processing of the code optimization apparatus902is the same as any well-known optimization apparatus, and so will not be described.

The address assigning means904estimates an address for each instruction in the optimization processing code903produced by the code optimization apparatus902and assigned an estimated address to each instruction. These addresses are called provisional addresses in this specification. As a result, the address assigning means904outputs the address assigned codes916.

The label detecting means905detects local labels from the address assigned code916. On detecting a label that should be resolved by an instruction address, the label detecting means905obtains the provisional address of the instruction including this label. Conversely, on detecting a label that should be resolved by a PC relative value, the label detecting means905obtains the provisional addresses of the instruction including this label and the branch destination instruction. After this, the label detecting means905outputs the label information906that shows the instructions that include labels and information on values for resolving these labels.

The lower address subtraction means907, the upper address subtraction means910, and the address difference calculating means912calculate the PC relative values for labels, in the label information906, that should be resolved by PC relative values.

The lower address subtraction means907subtracts the lower 3 bits of the provisional address of a branch instruction from the lower 3 bits of the provisional address of the branch destination instruction and outputs the resulting carry value908and lower subtraction result909.

The upper address subtraction means910subtracts the upper 29 bits of the provisional address of a branch instruction and the carry value908calculated by the lower address subtraction means907from the upper 29 bits of the provisional address of the branch destination instruction and outputs the resulting upper subtraction result911.

The address difference calculating means912finds the address difference913by setting the lower subtraction result909calculated by the lower address subtraction means907as the lower 3 bits and the upper subtraction result911calculated by the upper address subtraction means910as the upper 29 bits.

The label information resolving means914converts an instruction in the optimization processing code903including the present label into an instruction of a suitable size, based on an address that was estimated and assigned by the address assigning means904or the address difference913found by the address difference calculating means912. If the assigned address or the address difference913can be expressed using no more than 13 bits, the labels information resolving means914converts the instruction into a 21-bit instruction, or if not the label information resolving means914converts the instruction into a 42-bit instruction.

After the labels have been resolved, the label information resolving means914links the instruction sequences into packets of three instruction units and outputs the result as the optimized code304.

The following describes a specific operation of the optimization apparatus303.

FIG. 10is a flowchart showing the operation procedure of the optimization apparatus.

First, the code optimization apparatus902optimizes the assembler code302and generates optimization processing code903. Part of the optimization processing code903: generated by the code optimization apparatus902is shown in FIG.11. Of the instructions inFIG. 11, “L1:mov r2,r1”1000shows the position of the label L1and is an instruction that indicates a transfer from register r2to resister r1. The instruction “jsr f” is a function call that performs a relative branch to the label f (an external label). A return from the function call to this address is performed by a “ret” instruction. The instruction “add r0,r4” adds the values of registers r0and r4and stores the result in register r4. The instruction “and r1,r3”1003calculates a logical AND for the values in register r1and r3and stores the result in register r3. The instruction “mov L2,r2”1004transfers the address of the instruction located at the label L2into the register r2. The instruction “ld (r2),r0”1005transfers the data stored at the address stored in register r2into the register r0. The instruction “bra L1”1006performs an indirect branch to the label L1(a local label). Note that inFIG. 11, the instructions that continue after instruction1007have been omitted, though these instructions do not include an instruction located at the label f (step S9001).

The address assigning means904assigns a provisional address to each instruction in the optimization processing code903, and so generates address assigned codes916.FIG. 12shows the address assigned codes916generated from the optimization processing code903shown in FIG.11. In this example, provisional addresses starting from the value “32′b00000800” have been assigned (step S9002).

The label detecting means905detects local labels in the address assigned codes916and outputs label information906composed of instructions that include the detected labels and information on the values used to resolve those labels.FIG. 13shows the label information906that is generated from the address assigned codes916shown in FIG.12. As shown in this figure, label L2of instruction1104is detected as a label that should be resolved by an instruction address and label L1is detected as a label that should be resolved by a PC relative value.

Information showing the address for resolving the label L2is appended to the instruction “mov L2,r2” that includes the label L2, and information showing the addresses of the branch destination instruction and branch instruction to be used for calculating a PC relative value is appended to the instruction “bra L1” that includes the label L1. Note that since the label f in instruction1101is an external label, it is not optimized (steps S9003, S9004).

When the label information906includes a label that should be resolved by a PC relative value, processing to calculate this PC relative value is performed. The lower address subtraction means907calculates the lower 3 bits of the value shown by the label L1that is a PC relative value. The lower address subtraction means907subtracts the lower 3 bits “3′b000” of the provisional address “32′h00000812” of the branch instruction1106from the lower 3 bits “3′b000” of the provisional address “32′h00000800” of the branch destination instruction1100. As a result, “1” is obtained as the carry value908, and “3′b100” is obtained as the lower subtraction result909(steps S9005, S9006).

The upper address subtraction means910calculates the upper 29 bits of the value shown by the label L1that is a PC relative value. The upper address subtraction means910subtracts the upper 29 bits “29′h00000102” of the provisional address of the branch instruction1106and the carry value908“1” generated by the lower address subtraction means907from the upper 29 bits “29′h00000100” of the provisional address of the branch destination instruction1100. As a result, “29′h1ffffffd” (“−3” in base 10, minus numbers being hereafter shown using a complement) is obtained as the upper subtraction result911(step S9007).

The address difference calculating means912finds the address difference, which is to say the PC relative value, by setting the lower subtraction result909as the lower bits and the upper subtraction result911as the upper bits in this example, the address difference calculating means912sets “3′b100” as the lower bits and “29′h1ffffffd” as the upper bits, giving an address difference of “32′hffffffec” (step S9008).

The label information resolving means914judges whether the value used to resolve the label in the label information906can be expressed by a 13-bit value. The value that resolves the label L2shown inFIG. 13is “32′h12345678”, so that this value cannot be expressed as a 13-bit value, meaning that instruction1104including this label L2will become a 42-bit instruction. On the other hand, the value used to resolve label L1is “32′hffffffec”, which can be expressed by a 13-bit value. Accordingly, the instruction1106that includes label L1will become a 21-bit instruction (steps s9009, S9010, S9011).

The label information resolving means914links the instruction sequences into packets of three instruction units, based on the address assigned codes916. When doing so, the label information resolving means914converts instructions that include labels into instructions of the determined size. Here, one instruction unit is used for 21-bit instructions, and two units are used for 42-bit instructions. After this, the label information resolving means914outputs the instruction sequences that it has converted into packets as the optimized code304.FIG. 14shows the optimized code304generated from the address assigned codes916shown in FIG.12. InFIG. 14, each row shows the instructions that form one instruction packet, with the marks “||” showing the boundaries between instructions in a packet. Curved brackets “( )” are used in this drawing to indicate 42-bit instructions that each occupy two units (step S9012).

As described above, addresses are estimated with a calculation method that uses a carry. In this way, a suitable optimization apparatus for a processor that uses a carry method can be achieved.

Note that the provisional addresses assigned by the address assigning means904and the PC relative values calculated by the address difference calculating means912are values that are estimated for determining the sizes of all instructions that include labels. There are cases when these estimates differ from the actual values, so that these values are not used hereafter in the processing.

Assembler

FIG. 15is a block diagram that shows the construction of the assembler305shown in FIG.5and the input/output data related to the assembler305. This assembler305converts the optimized code304generated by the optimization apparatus303into relocatable codes306that have a relocatable address format. The assembler305includes a machine language code generating means802, a label detecting means804, a lower address subtraction means806, an upper address subtraction means809, an address difference calculating means811, and a label information resolving means813. The machine language code generating means802converts the optimized code304into machine language codes803that can be executed by the processor309. However, labels whose values have not been resolved, are not converted and are stored in the machine language codes803as they are. The machine language code generating means802assigns a packet address and an in-packet address to each machine language code. As described later, the labels are later resolved using these addresses.

The label detecting means804finds a label that should be resolved by a PC relative value, which is to say, a difference in addresses between two instructions and obtains the addresses of the branch instruction and the branch destination instruction. After this, the label detecting means804outputs label information305that is composed of the instructions that include labels and the values that resolve these labels.

To resolve the label information805obtained by the label detecting means804, the lower address subtraction means806, the upper address subtraction means809, and the address difference calculating means811calculate a PC relative value as follows.

The lower address subtraction means806subtracts the lower 3 bits of the address of a branch instruction from the lower 3 bits of the address of the branch destination instruction and outputs the carry value807and the lower subtraction result808.

The upper address subtraction means809subtracts the upper 29 bits of the address of a branch instruction and the carry value807calculated by the lower address subtraction means806from the upper 29 bits of the address of the branch destination instruction and outputs the resulting upper subtraction result810.

The address difference calculating means811finds the address difference812by setting the lower subtraction result808calculated by the lower address subtraction means8016as the lower 3 bits and the upper subtraction result810calculated by the upper address subtraction means809as the upper 29 bits.

The label information resolving means813replaces the labels in the machine language codes903with the address differences812calculated by the address difference calculating means811, and outputs the resulting relocatable codes306.

The following explains a specific example of the processing of the assembler305on receiving an input of the optimized code304ofFIG. 14that has been outputted by the optimization apparatus303.

FIG. 16is a flowchart showing the operation of the assembler.

First, the machine language code generating means802converts each packet in the optimized code304into machine language codes803that are suited to the processor309. However, the machine language code generating means802does not convert labels whose values have not been resolved, so that these labels are stored as they are in the machine language codes803. After this, the machine language code generating means802assigns packet addresses (hereafter also called “local packet addresses”) and in-packet addresses to each instruction in the machine language codes803.FIG. 17shows the machine language codes80that are generated from the optimized code304shown in FIG.14. Note that the actual machine language codes are expressed in binary as sequences of zeros and ones, though for ease of understanding these machine language codes are shown inFIG. 17in mnemonic form. The parallel execution boundary information100and the format information101will also be clear at this stage, but are not illustrated to simplify the figure. InFIG. 17, packet addresses (local packet addresses) are assigned starting from the value “29′h00000000”. The label f in the instruction “jsr f” in packet1300, the label L2in the instruction “mov L2,r2” in packet1301, and the label L1in the instruction “bra L1” in packet1302have not yet been resolved, so that these instructions are not converted (steps S1500, S1501).

Next, the label detecting means804detects labels, out of the unresolved labels in the machine language codes803, which are local labels that should be resolved by a PC relative value, and obtains the address of the instruction including the label, which is to say, the branch instruction, and the address of the branch destination instruction. The label detecting means804then outputs label information805that includes information snowing the instruction including the label and the value that resolves the label.FIG. 18shows the label information805that is generated from the machine language codes shown in FIG.17. Here, label L1is detected as a local label that should be resolved by a PC relative value, “32′h00000012” is obtained as the address of the branch instruction, and “32′h000000000” is obtained as the address of the branch destination instruction (steps S1502, S1503).

The lower address subtraction means B06then calculates the lower bits of the value L1that is a PC relative value. The lower address subtraction means806subtracts the lower 3 bits “3′b010” of the address “32′h00000012” of the branch instruction1409from the lower 3 bits “3′b000” of the address “32′h00000000” of the branch destination instruction1401. As a result, “1” is obtained as the carry value807and “3′b100” is obtained as the lower subtraction result808(step S1504).

Next, the upper address subtraction means809calculates the upper bits of the value L1that is a PC relative value. The upper address subtraction means809subtracts the upper 29 bits “29′h00000002” of the address of the branch instruction1409and the carry value807“1” from the upper 29 bits “29′h00000000” of the address of the branch destination instruction1401. As a result, “29′h1ffffffd” (“−3” in base 10, minus numbers being hereafter shown using a complement) is obtained as the upper subtraction result810(step S1505).

The address difference calculating means811finds the address difference, which is to say the PC relative value, by setting the lower subtraction result808as the lower bits and the upper subtraction result810as the upper bits. In this example, the address difference calculating means811sets “3′b100” as the lower bits and “29′h1fffffd” as the upper bits, giving an address difference of “32′hffffffec” (step S1506).

The label information resolving means813judges whether the address difference812can be expressed by only its lower 13 bits. If so, the label information resolving means813sets the lower 13 bits of the address difference812as the PC relative value, or if not, the label information resolving means813sets the entire address difference812as the PC relative value. As a result, a label in the machine language codes803is converted into a PC relative value. The address difference that resolves label L1in the label information inFIG. 17is “32′hffffffec”, which can be expressed by the lower 13-bit value “181fec”, so that the label L1in the machine language codes shown inFIG. 17is converted into the lower 13-bit value.FIG. 19shows the relocatable codes that are generated from the machine language codes803shown in FIG.17. InFIG. 19, the instruction1609has been produced by converting the label L1into a PC relative value.FIG. 19shows the parallel execution boundary information100and format information101of each instruction that had already been established when the machine language codes803were outputted, and also shows the unused bit in each instruction packet (steps S1507, S1508, S1509).

As described above, by finding a PC relative value by performing address calculation according to a carry method, an assembler corresponding to a processor that uses a carry method can be realized.

Linker

FIG. 20is a block diagram showing the construction of the linker307shown in FIG.5and the I/O (input/output) data of the linker307. This linker307combines a plurality of relocatable codes701, determines the addresses of each instruction, and outputs the object code714that is executable by the processor309and is in absolute address format. The linker307includes the code combining means702, the relocation information detecting means704, the lower address subtraction means706, the upper address subtraction means709, the address difference calculating means711, and the relocation information resolving means713.

The code combining means702combines a plurality of inputted relocatable codes701and determines the addresses of all instructions. The code combining means702then resolves, the labels that should be resolved by instruction addressed using the determined addresses and outputs the combined codes703that result from its operation.

The relocation information detecting means704searches for external labels that should be resolved by PC relative addresses and obtains the addresses of branch instructions and the branch destination instructions. After doing so, the relocation information detecting means704outputs relocation information705includes information showing instructions that include labels and values to be used to resolve the labels. To resolve the resulting relocation information705, the lower address subtraction means706, the upper address subtraction means709, and the address difference calculating means711calculate PC relative values, as described below.

The lower address subtraction means706subtracts the lower 3 bits of the address of the branch instruction from the lower 3 bits of the address of the branch destination instruction, and so generates a carry value707and a lower subtraction result708.

The upper address subtraction means709subtracts the upper 29 bits of the address of the branch instruction and the carry value707generated by the lower address subtraction means706from the upper 29 bits of the address of the branch destination instruction, and so generates the upper subtraction result710.

The address difference calculating means711sets the lower subtraction result706calculated by the lower address subtraction means706as the lower 3 bits and the upper subtraction result710calculated by the upper address subtraction means709as the upper 29 bits to generate the address difference712.

The relocation information resolving means713replaces labels in the combined codes703with address differences712calculated by the address difference calculating means711, and outputs the resulting object code308.

The operation of the linker307is explained below using an example where the relocatable codes306shown inFIG. 19that have been outputted by the assembler305have been inputted.

FIG. 21is a flowchart showing the operation of the linker307.

First, the code combining means702combines a plurality of relocatable codes701.FIG. 23shows the state when the relocatable codes814shown inFIG. 19have been combined with the relocatable code shown in FIG.22. The code combining means702combines these relocatable codes with the packet address of the first relocatable code inFIG. 22as “29′h00000000” and the packet address of the first relocatable code inFIG. 19as “29′h00000001” (step S2000, S2001).

The addresses of all instructions are determined in this way, so that the code combining means702can resolve the addresses of labels that should be resolved by instruction addresses and then output the resulting combined codes703.FIG. 23shows that the address of label L2in instruction1810“mov L2,r2” is the starting address of instruction packet1815. This address has been set at “32′h12345680”, so that the code combining means702uses this value to replace the label L2.FIG. 24shows the resulting combined codes703. In instruction1910inFIG. 24, the label L2has been replaced with this address “32′h12345680” (step S2002).

Next, the relocation information detecting means704finds external labels in the combined codes703that should be resolved by PC relative values and extracts the addresses of the instructions that include these labels and the addresses of the instructions where these labels are located, which is to say, the addresses of branch instructions and branch destination instructions. After this, the relocation information detecting means704outputs relocation information705that is composed of information showing the instructions including labels and the values to be used to resolve these labels.FIG. 25shows the label information that is generated from the combined codes703shown in FIG.24. Here, label f is found as an external label that should be resolved by a PC relative value, so that “32′h0000000a” is obtained as the address of a branch instruction and “32′h00000000” as the address of the branch destination instruction (steps S2003, S2004).

The lower address subtraction means706then calculates the lower bits of the value f that is a PC relative value. The lower address subtraction means706subtracts the lower 3 bits “3′b010” of the address “32′h0000000a” of the branch instruction1906from the lower 3 bits “3′b000” of the address “32′h00000000” of the branch destination instruction1901. As a result, “1” is obtained as the carry value707and “3′b100” is obtained as the lower subtraction result708(step S2005).

Next, the upper address subtraction means709calculates the upper bits of the value f that is a PC relative value. The upper address subtraction means709subtracts the upper 29 bits “29′h00000002” of the address “32′h0000000a” of the branch instruction1906and the carry value707“1” from the upper 29 bits “29′h00000000” of the address of the branch destination instruction1901. As a result, “29′h1ffffffe” is obtained as the upper subtraction result710(step S2006).

The address difference calculating means711finds the address difference712, which is to say the PC relative value, by setting the lower subtraction result708as the lower bits and the upper subtraction result710as the upper bits. In this example, the address difference calculating means811sets “3′b100” as the lower bits and “29′h1ffffffe” as the upper bits, giving an address difference of “32′hfffffff4” (step S2007).

Next, the relocation information resolving means713converts a label in the combined codes703into a PC relative value, setting the lower 13 bits of the address difference712as the PC relative value if this address difference712can be expressed by the lower 13 bits, or otherwise setting the entire address difference712as the PC relative value. The address difference that resolves the label f in the relocation information inFIG. 24is “32′hffffff4”, which can be expressed by the lower 13-bit value “13′h1ff4”, so that the label f in the combined codes703shot inFIG. 23is converted into this lower 13-bit value to produce the object code. The resulting object code is shown in FIG.26. In instruction2106inFIG. 26, the label f has been converted into the lower 13-bit value “13′h1ff4” (steps S2008, S2009, S2010).

As described above, the present linker finds PC relative values using an address calculation including a carry, and so is suited to a processor that uses a carry.

Specific Operation of the Processor

The following describes the operation of the processor when the object code shown inFIG. 26has been stored in the instruction memory407.

At the start of execution of this object code, the upper PC403is set at “29′h00000000” and the lower PC404is set at “3′b000”. The prefetch upper counter410receives an input from the upper PC403and so is set at “29′h00000000”.

The read of instructions from the instruction memory407is performed in packet units according to the value in the prefetch upper counter410. In detail, instruction packet2100that is indicated by the prefetch upper counter410is read from the instruction sequence stored in the instruction memory407and is stored in the instruction buffer408. The value of the prefetch upper counter410is incremented by one in each cycle, and so here becomes “29′h00000001”. Hereafter, an instruction packet indicated by the prefetch upper counter410is read from the instruction memory407and written into the instruction buffer408in each cycle.

The following explains the operations for decoding and executing instructions for the case when instruction packet2104is indicated by the upper PC403and instruction2107in instruction packet2104is indicated by the lower PC404. The instructions stored in the instruction buffer408are interpreted by the instruction decoders409a˜409c. The first instruction decoder409areceives an input of the first unit, unit2107, in the instruction packet2104and investigates whether unit2107is a one-unit instruction and whether there is a parallel execution boundary. Since unit2107is a one-unit instruction and there is no parallel execution boundary, the second instruction decoder409breceives an input of the next unit, unit2109, and investigates whether unit2109is a one-unit instruction and whether there is a parallel execution boundary. Since unit2109is a one-unit instruction and there is no parallel execution boundary, the third instruction decoder409creceives an input of the next unit and investigates whether this next unit is a one unit instruction and whether there is a parallel execution boundary. Since this unit is not a one-unit instruction, the third instruction decoder409calso receives an input of the following unit. The third instruction decoder409cthen finds that this following unit includes a parallel execution boundary. As a result, the instructions2107,2109, and2110are executed in parallel.

The first instruction decoder409adecodes the instruction “add r0,r4” and outputs control signals to the first calculator401a. The first calculator401aadds the values of registers r0and r4and stores the result in register r4. The second instruction decoder409bdecodes the instruction “and r1,r3” and outputs control signals to the second calculator401b. The second calculator401bperforms a logical operation on the values of registers r1and r3, and stores the result in register r3. The third instruction decoder409cdecodes the instruction “mov 32′h12345680,r2” and so has the immediate “32′h12345680” transferred into register r2.

In this case, the instruction decoders409a-409cinform the INC412that a total of four instruction units have been executed. The INC412increments the values in upper PC403and the lower PC404by four units. As a result, the lower PC404becomes “3′b000”, a carry of two to the upper PC403is generated, and the upper PC403becomes “29′h00000003”. This means that the first instruction to be executed in the next cycle is instruction2112.

The first instruction decoder409areceives an input of the first unit, unit2112, and investigates whether unit2112is a one-unit instruction and whether there is a parallel execution boundary. Since unit2112is a one-unit instruction and there is no parallel execution boundary, the second instruction decoder409breceives an input of the next unit, unit2113, and investigates whether unit2113is a one-unit instruction and whether there1ga parallel execution boundary. Here, the second instruction decoder409bfinds that unit2109is a one-unit instruction and that there is a parallel execution boundary. As a result, the processor309finds that instructions2112and2113can be executed in parallel.

The first instruction decoder409adecodes the instruction “ld (r2),r0”, has the operand data, which has the value in register r2as the operand address, read from the data memory406and stored in register r0. The second instruction decoder409bdecodes the instruction “bra 13′h1fec”, and, since this is a branch instruction, updates the values in the upper PC403and lower PC404using the address of the branch destination instruction.

First, the address indicated by the upper PC403and lower PC404is amended. While a PC relative value shows the difference in addresses between a branch instruction and its branch destination instruction, the upper PC403and lower PC404show the address of the first address to be executed in the same cycle as the branch instruction, so that the upper PC403and lower PC404are amended so that they indicate the address of the branch instruction. In detail, the INC412increments the values of the upper PC403and lower PC404by one unit to show that the branch instruction2113is preceded by one instruction unit, the first instruction2112. As a result, the lower PC404becomes “3′b010” and the upper PC403stays at “29′h00000003”.

Following this, the upper PC calculator411and the lower PC calculator405add the PC relative value “13′h1fec” obtained by the second instruction decoder409bto the upper PC403and the lower PC404. Here, the sign-extended 32-bit value “32′hffffffec” is used as the PC relative value. This addition is split into additions of the upper 29 bits and the lower 3 bits.

The lower PC calculator405adds the lower 3 bits “3′b100” of the PC relative value to the value “3′b010” of the lower PC404. As a result, a carry of one and the lower calculation result “3′b000” are obtained. The lower PC calculator405sends the carry to the upper PC calculator411, and sends the lower calculation result to the lower PC404.

Next, the upper PC calculator411adds the upper 29 bits “29′h1ffffffd” of the PC relative value and the carry value “1” received from the lower PC calculator405to the value “2 P′h00000003” of the upper PC403. The upper PC calculator411sends the upper calculation result of “29′h00000001” to the upper PC403, which sends the value on to the prefetch upper counter410. As a result of this processing, the prefetch upper counter410is set at “29′h00000003”, so that the next instruction packet to be prefetched will be instruction packet2104. Also, since the upper PC403is “29′h00000001” and the lower PC404is “3′b000”, the first instruction to be executed in the next cycle is instruction2105.

Hereafter, codes in the object code are successively read and executed in the same way, so that no explanation will be given for the other instructions.

This completes the detailed explanation of the constructions of the processor309, linker307, assembler305and optimization apparatus303shown inFIG. 5. Aconventional compiler can be used as the compiler301, so that no explanation of such will be given.

Note that while the processor of this embodiment includes three instruction decoders409a˜409cand three calculators401a-401c, the present invention is not limited to this construction, so that only one instruction decoder and one calculator may by provided. It is also possible for the functions of the optimization apparatus303to be incorporated into the compiler301, and to have the object code308generated from the source code300by the compiler301, the assembler305, and the linker307.

In the present embodiment, the prefetch lower counter413was described as having the fixed value of “3′b000”, though this need not be the case. As one example, this value may be incremented by one in each cycle. This results in one byte of data being read from the instruction memory407and written into the instruction buffer408in each cycle.

Second Embodiment

The second embodiment of the present invention relates to a modification of the processor, optimization apparatus, assembler, and linker of the first embodiment. This modification uses a different value as the PC relative value for resolving labels in branch instructions.

In the first embodiment, the PC relative value in a branch instruction is a difference in addresses between the branch instruction and the branch destination instruction, while in this second embodiment, the PC relative value in a branch instruction is a difference between the address of the branch destination instruction and the address of the first instruction in same set of instructions as the branch instruction.

In this way, the PC relative value has a slightly different meaning than in the present embodiment. However, if the devices used to generate a program (i.e., the optimization apparatus303, assembler305, and linker307that calculate the PC relative value) use the same meaning as the device that executes the program (i.e., a processor that calculates an address based on the PC relative value), the processor will be able to correctly change the program counter to the address of a branch destination instruction when executing a branch instruction.

The following explains the optimization apparatus303, assembler305, linker307, and processor.

The label detecting means905of the optimization apparatus303generates the label information906for labels that should be resolved by PC relative values in the following way. Instead of generating label information after obtaining the provisional addresses of the branch instruction and the branch destination instruction in the same way as in the first embodiment, the label detecting means995generates the label information906after obtaining the provisional addresses of the branch destination instruction and the address of the first instruction in the same set of instructions as the branch instruction. In the same way as in the first embodiment, this label information906is then used to calculate the address difference913that is the difference between two provisional addresses and is used in the optimized code304. The assembler and linker also operate in this way.

The following describes a specific example of the object code308generated in this embodiment.

The assembler305replaces the label L1in instruction1409in the machine language codes shown inFIG. 17with the subtraction value “13h′1ff0” produced by subtracting the address “32′h00000010” of instruction1408, which is the first instruction in same set of instructions as instruction1409, from the address “32′h00000000” of the branch destination instruction. In the same way, the linker307replaces the label f in instruction1906in the combined codes shown inFIG. 24with the subtraction value “13′h1ff8” produced by subtracting the address “32′h00000008” of the instruction1907, which is the first instruction in came set of instructions as instruction1906, from the address “32′h00000000” of the branch destination instruction.FIG. 27shows that the PC relative value of instruction2213differs from that shown in FIG.26.

The following describes the processor of the present embodiment.

The processor309executes object code that have been generated as described above. When the processor309executes a branch instruction, the PC relative value in the branch instruction is a difference in addresses between the branch destination instruction and the first instruction in same set of instructions as the branch instruction. Accordingly, the processor309does not amend the values of the upper PC403and lower PC404, and, in the same way as in the first embodiment, adds the PC relative value to the values in the upper PC403and lower PC404and updates the values in the upper PC403and lower PC404using the addition results. When this processor309executes the object code shown inFIG. 27, the execution of instruction2213results in the PC relative value “13h1ff8” being added to the present PC “32′h00000008”, resulting in the PC being updated to “32′h00000000”.

As described above, the processor of the present embodiment does not need to amend the value of the program counter in the same way as in the first embodiment whenever a branch instruction is executed. The address of a branch destination instruction can instead be obtained by directly adding a PC relative value to the PC. This reduces the total execution time.

Third Embodiment

The third embodiment of the present invention relates to a processor that can indicate the execution position of an instruction by fully utilizing the lower 3 bits of instruction addresses.

In the first embodiment, the lower 3 bits of the instruction address are used to indicate a position that is one of three units. In the present embodiment, however, full use is made of these 3 bits by having them indicate one of eight units.

FIG. 28Ashows the construction of an instruction packet in the present embodiment. This instruction packet is composed of eight instruction units. Each instruction unit in an instruction packet is 8 bits long, so that the total length of one instruction packet is 64 bits. The processor in this embodiment reads one instruction packet (64 bits) in one cycle.

FIG. 28Bshows the types of instructions used in this embodiment. Each instruction is composed of 8-bit instruction units, with there being one-, two-, three-, four-, five-, and six-unit instructions.

FIG. 28Cshows the relation between in-packet addresses and the instruction units in a packet. In the same way as in the first embodiment, a position in an instruction packet is indicated by the lower 3 bits of an instruction address. As shown inFIG. 28C, the in-packet address “3′b000” indicates the first unit, the in-packet address “3′b001” indicates the second unit, the in-packet address “3′b010” indicates the third unit, the in-packet address “3′b011” indicates the fourth unit, the in-packet address “3′b100” indicates the fifth unit, the in-packet address “3′b101” indicates the sixth unit, the in-packet address “3′b110” indicates the seventh unit, and the in-packet address “3′b111” indicates the eighth unit.

As described above, the processor of the present embodiment indicates the execution position of an instruction making full use of the lower 3 bits of the instruction address. As a result, instructions can be executed with a greater variation of execution units for one cycle.

Fourth Embodiment

The fourth embodiment of the present invention relates to a method for calculating instruction addresses without using a carry.

The first embodiment teaches a processor for executing a program, and an optimization apparatus, assembler, and linker for generating a suitable program. All of these devices use a common method for calculating an instruction address using a carry. This has the effect that the processor can correctly generate the address of a branch destination instruction using a PC relative value. However, this effect can be achieved if the processor, optimization apparatus, assembler, and linker use a common address calculation method that does not use a carry. This present embodiment relates to such a calculation method that calculates addresses without using a carry.

This calculation method that does not use a carry resembles the calculation method in the first embodiment in that the calculation of address is performed separately for the upper 29 bits and lower 3 bits. However, the present method differs by not using a carry.

The following explains the method by which the processor finds the address of a branch destination instruction by adding the address of a branch instruction and a PC relative value. The lower PC calculator405shown inFIG. 6adds the lower 3 bits of the address of the branch instruction and the lower 3 bits of the PC relative value.FIG. 29Ais an addition table showing the addition rules for adding the lower 3 bits of the address of the branch instruction and the lower 3 bits of the PC relative value in the present calculation method. As shown in the figure, this calculation differs from a normal addition of binary values in that it cycles between the three states “3′b000”, “3′b010”, and “3′b100”. Note that no carry is generated.

The upper PC calculator411shown inFIG. 6adds the upper 24 bits of the address of the branch instruction and the upper 29 bits of the PC relative value. This is a normal addition of binary values.

The results of the above additions form the address of a branch destination instruction. In detail, the addition result for the lower 3 bits is set in the lower PC404and the addition result for the upper 29 bits is set in the upper PC403.

The following explains the method used by the optimization apparatus, assembler, and linker to calculate the PC relative value, which is to say, to subtract the address of the branch destination instruction from the address of the branch instruction. This subtraction is split into an upper 29 bits and lower 3 bits like the addition performed by the processor. The lower address subtraction means907of the optimization apparatus303, the lower address subtraction means806of the assembler305, and the lower address subtraction means706of the linker307subtract the lower 3 bits of the address of a branch instruction from the lower 3 bits of the address of the branch destination instruction.FIG. 29Bis a subtraction table showing the subtraction rules for subtracting the lower 3 bits of the address of the branch instruction from the lower 3 bits of the address of the branch destination instruction. As shown in the figure, this calculation differs from a normal subtraction of binary values in that it cycles between the three states “3′b000”, “3′b010”, and “3′b100”. Note that no carry is generated.

The upper address subtraction means910of the optimization apparatus303, the upper address subtraction means809of the assembler305, and the upper address subtraction means709of the linker307subtract the upper 29 bits of the address of the branch instruction from the upper 29 bits of the address of the branch destination instruction. This is a normal subtraction of binary values.

The PC relative value is then found by setting the result of the above subtraction for the lower 3 bits as the lower 3 bits and the result of the above subtraction for the upper 29 bits as the upper 29 bits.

FIG. 30shows the object code that is generated by the above address calculation method of the present values of instructions2406and2413differ to those in FIG.26. The following explains the calculation of the PC relative value of instruction2406.

The lower address subtraction means706subtracts the lower 3 bits “3′b010” of the address of instruction2406from the, lower 3 bits “3′b000” of the address of instruction2401in accordance with the subtraction table shown it FIG.29B. This produces the lower subtraction result “3′b100”.

The upper address subtraction means709subtracts the upper 29 bits “29′h00000001” of the address of instruction2406from the upper 29 bits “29′h00000000” of the address of instruction2401. This produces the upper subtraction result “29′h1fffffff”.

The address difference calculating means711generates the address difference “32′h1ffffffc” by setting the upper subtraction result “29′h1fffffff” as the upper 29 bits and the lower subtraction result “3′b100” as the lower 3 bits.

The relocation information resolving means713judges that the address difference “32′h1ffffffc” can be expressed by just the lower 13 bits “13′h1ffc” and so replaces a label with this value “13′h1ffc” as a PC relative value to generate instruction2406.

The processor309executes the object code generated as described above. When executing a branch instruction, the processor309adds the upper PC403and lower PC404, which have been amended to correctly indicate the branch instruction, to the PC relative value in the branch instruction without generating a carry.

When the processor309executes instruction2406in the object code shown inFIG. 30, the lower PC calculator405adds the amended lower PC404“3′b010” and the lower 3 bits “3′b100” of the PC relative value and updates the lower PC404to the resulting addition value “3′b000”. The upper PC calculator411adds the amended upper PC403“29′h00000001” and the upper 29 bits “29′h1fffffff” of the PC relative value and updates the lower PC404to the resulting addition value “29′h00000000”.

As described above, the present calculation method can calculate addresses without a carry being sent between the lower PC calculator405and the upper PC calculator411. This means that address calculation can be performed with a simpler hardware construction.

Fifth Embodiment

The fifth embodiment of the present invention teaches a method for calculating instruction addresses using absolute values.

This calculation method that uses absolute values resembles the calculation method in the first embodiment in that the calculation of address is performed separately for the upper 29 bits and lower 3 bits. However, the present method differs from the carry method in that the value of the lower 3 bits of an instruction address are set as the lower 3 bits of the calculation result.

The following explains the method by which the processor finds the address of a branch destination instruction by adding the address of a branch instruction and a PC relative value. The lower PC calculator405shown inFIG. 6adds the lower 3 bits of the address of the branch instruction and the lower 3 bits of the PC relative value.FIG. 31Ais an addition table showing the addition rules for adding the lower 3 bits of the address of the branch instruction and the lower 3 bits of the PC relative value in the present calculation method that uses absolute values. As shown in the figure, the lower 3 bits of the PC relative value are set as the lower 3 bits of the addition result.

The upper PC calculator411shown inFIG. 6adds the upper 29 bits of the address of the branch instruction and the upper 29 bits of the PC relative value. This is a normal addition of binary values. The results of the above additions form the address of a branch destination instruction. In detail, the addition result for the lower 3 bits is set in the lower PC404and the addition result for the upper 29 bits is set in the upper PC403.

The following explains the method used by the optimization apparatus303, assembler305, and linker307to calculate the PC relative value, which is to say, to subtract the address of the branch destination instruction from the address of the branch instruction. This subtraction is split into an upper 29 bits and lower 3 bits, like the addition performed by the processor. The lower address subtraction means907of the optimization apparatus303, the lower address subtraction means806of the assembler305, and the lower address subtraction means706of the linker307subtract the lower 3 bits of the address of a branch instruction from the lower 3 bits of the address of the branch destination instruction.FIG. 31Bis a subtraction table showing the subtraction rules for subtracting the lower 3 bits of the address of the branch instruction from the lower 3 bits of the address of the branch destination instruction in this calculation method that uses absolute values. As shown in the figure, the lower 3 bits of the branch destination address are set as the subtraction result for the lower 3 bits.

The upper address subtraction means910of the optimization apparatus303, the upper address subtraction means809of the assembler305, and the upper address subtraction means709of the linker307subtract the upper 29 bits of the address of the branch instruction from the upper 29 bits of the address of the branch destination instruction. This is a normal subtraction of binary values.

The PC relative value is then found by setting the result of the above subtraction for the lower 3 bits as the lower 3 bits and the result of the above subtraction for the upper 29 bits as the upper 29 bits.

FIG. 32shows the object code that is generated by the above address calculation method of the present embodiment that uses absolute values. The PC relative values of instructions2606and2613differ to those in FIG.26. The following explains the calculation of the PC relative value of instruction2606.

The lower address subtraction means706subtracts the lower 3 bits “3′b010” of the address of instruction2406from the lower 3 bits “3′b000” of the address of instruction2401in accordance with the subtraction table shown in FIG.31B. This produces the lower subtraction result “3′b000”.

The upper address subtraction means709subtracts the upper 29 bits “29′h00000001” of the address of instruction2406from the upper 29 bits “29′h00000000” of the address of instruction2401. This produces the upper subtraction result “29′h1fffffff”.

The address difference calculating means711generates the address difference “32′h1ffffff8” by setting the upper subtraction result “29′h1fffffff” as the upper 29 bits and the lower subtraction result “3′b000” as the lower 3 bits.

The relocation information resolving means713judges that the address difference “32′h1ffffff8” can be expressed by just the lower 13 bits “13′h1ff8” and so replaces a label with this value “13′h1ff8” as a PC relative value to generate instruction2606.

The processor309executes the object code generated as described above. When executing a branch instruction, the processor309adds the upper PC403and lower PC404, which have been amended to correctly indicate the branch instruction, to the PC relative value in the branch instruction using the present absolute value method.

When the processor309executes instruction2606in the object code shown inFIG. 32, the lower PC calculator405adds the amended lower PC404“3′b010” and the lower 3 bits “3′b000” of the PC relative value and updates the lower PC404to the resulting addition value “3′b000”. The upper PC calculator411adds the amended upper PC403“29′h00000001” and the upper 29 bits “29′h1fffffff” of the PC relative value and updates the lower PC404to the resulting addition value “29′h00000000”.

As described above, the present calculation method can calculate addresses without needing to calculate the lower bits, so that the speed for calculating addresses can be improved.

Sixth Embodiment

The sixth embodiment of the present invention relates to a linear calculation method for addresses. Unlike the other embodiments, this linear calculation method calculates instruction addresses without splitting the calculation into an upper 29 bits and lower 3 bits.

The following explains the present method for finding the address of a branch destination instruction from the address of a branch instruction and a PC relative value. While the processor that uses the carry method is equipped with an upper PC calculator411for calculating the upper 29 bits and a lower PC calculator405for calculating the lower 3 bits, a processor that uses the present linear calculation method is only equipped with one PC calculator for calculating a 32-bit address. The PC calculator in this linear calculation method adds a 32-bit address of a branch instruction and a 32-bit PC relative value. This calculation is a normal binary addition.

The addition result of the PC calculator is set as the address of the branch destination instruction. This means that the lower 3 bits of the addition result are set in the lower PC404and the upper 29 bits of the addition result are set in the upper PC403.

The following explains the calculation of the PC relative value by the optimization apparatus303, assembler305, and linker307, which is to say, the subtraction of the address of the branch instruction from the address of the branch destination instruction. Like the processor in this embodiment, the optimization apparatus303, assembler305, and linker307are each provided with only one calculator, the address subtraction means, for calculating a 32-bit address. The address subtraction means in this linear calculation method subtracts the address of a branch instruction from the address of a branch destination instruction. This calculation is a normal binary subtraction. The subtraction result is then set as the PC relative value.

FIG. 33shows the object code that has been generated using the linear calculation method of the present embodiment. InFIG. 33, the PC relative values in instructions2706and2713differ to those shown in FIG.26. The following describes the method for calculating the PC relative value for instruction2706.

The address subtraction means in the linear calculation method subtracts the 32-bit address “32′h00000000” of instruction2701from the 32-bit address “32′h0000000a” of instruction2706and so obtains the address difference “32′hfffffff6”.

The relocation information resolving means713judges that the address difference “32′hfffffff6” can be expressed by just its lower 13 bits “13′h1ff6”, and so replaces the label with “13′h1ff6” as the PC relative value to generate instruction2706.

The processor309executes the object code generated as described above. When executing a branch instruction, the processor309adds the upper PC403and lower PC404that have been amended to indicate the address of the branch instruction to the PC relative value using the present linear calculation method.

When the processor309executes instruction2706in the object code shown inFIG. 33, the PC calculator in this embodiment adds a 32-bit PC value “32′h0000000a”, which has the amended value of the upper PC403as the upper 29 bits and the amended value of the lower PC404as the lower 3 bits, to the PC relative value “32′hfffffff6” and so obtains the addition result “32′h00000000”. After this, the PC calculator updates the lower PC404to the lower 3 bits “3′b000” of this addition value, and the upper PC403to the upper 29 bits “29′h00000000” of this addition value.

In this way, the present linear calculation method can calculate addresses using a standard calculator as the PC calculator. This simplifies the structure of the processor.

Seventh Embodiment

The seventh embodiment of the present invention relates to a processor that interprets and executes PC adding instructions and PC subtracting instructions and to a compiler that generates such instructions.

FIG. 34shows the processor of the present embodiment. The processor of the present embodiment differs from the processor in the first embodiment in that it further includes a second lower PC calculator2800and a second upper PC calculator2802and in that the first instruction decoder2801a, the second instruction decoder2801b, and the third instruction decoder2801care all provided with new functions.

The instruction decoders2801a˜2801care provided with an extra function for decoding PC adding instructions and PC subtracting instructions.FIG. 35Ashows the operation that corresponds to a PC adding instruction which is shown in mnemonic form. As shown inFIG. 35A, a PC adding instruction adds a PC relative value “disp” to the value of the PC that is stored in a register and stores the addition result in the same register.FIG. 35Bshows the operation that corresponds to a PC subtracting instruction which is shown in mnemonic form. As shown inFIG. 35B, a PC adding instruction subtracts a PC relative value “disp” from the value of the PC that is stored in a register and stores the subtraction result in the same register.

The second lower PC calculator2800and the second upper PC calculator2802perform the PC adding instruction and PC subtraction instruction described above, using the same calculation rules as the lower PC calculator405and the upper PC calculator411described in the first embodiment.

FIG. 36shows the construction of the compiler of the present embodiment.

The source code2901is a program written in a high-level language such as C.

The intermediate code converting unit2902converts the source code2901into intermediate code2903which is an internal expression for the compiler. This intermediate code converting unit2902is a well-known technology and so will not be described.

The PC value adding instruction converting unit2904converts each intermediate code in the intermediate code2903that adds a value of the PC and a variable into an assembler code2906for a PC adding instruction that is shown in FIG.34.

The instruction converting unit2905converts the other intermediate codes into assembler code2906. This instruction converting unit2905is a well-known technology and so will not be described.

The following describes a specific example of the operation of the present compiler.FIG. 37is a flowchart showing the operation of this compiler.

First, the compiler receives an input of source code.FIG. 38shows source code which is written in C language. InFIG. 38, the external functions g1, g2, g3, and g4are declared, and the function f is defined as a function that receives the int-type variable “i”. This function f includes code that substitutes the address of function g1into the pointer fp if the value of “i” is 1, substitutes the address of function g2into the pointer fp if the value of “i” is 2, substitutes the address of function g3into the pointer fp if the value of “i” is 3, substitutes the “i” is 4, and finally calls the function indicated by the pointer fp (step3600).

Next, the intermediate code converting unit2902converts the source code into intermediate codes. When doing so, the intermediate code converting unit2902coverts (a) a source code that substitutes a pointer to an external function into a pointer variable into (b) an intermediate code that adds the difference between the address of the start of present function and the address of the start of the external function to a temporary variable that stores the address of the start of the present function, and substitutes the addition result into the pointer variable.

FIG. 39shows the intermediate codes that have been generated from the source program shown in FIG.38. The intermediate code3201shown inFIG. 39is an intermediate code that has the label f marking the start of the function and that substitutes the present value of the PC, which is to say, the first address of function f, into the temporary variable tmp. The intermediate code3202is intermediate code that judges whether the value of variable i is not “1”. The intermediate code3203is an intermediate code that branches to the label L when the judgement by intermediate code3203is true, that is, variable i is not “1”. The intermediate code3204is executed when variable i is “1”, and adds a difference, obtained by subtracting a first address of function f from the first address of function g1, to the temporary variable tmp into which the first address of function f has been substituted, and has the addition result substituted into the variable fp. The intermediate code3205is an intermediate code that branches to the label L.

The intermediate code3206includes the label L1, and is an intermediate code that judges whether variable i is not equal to “2”. The intermediate code3207branches to label L2when the judgement in intermediate code3206is true, which is to say, when variable i is not “2”. The intermediate code3208is executed when variable i is equal to “2”, and is an intermediate code that adds a difference, obtained by subtracting a first address of function f from the first address of function g2, to the temporary variable tmp into which the first address of function f has been substituted, and has the addition result substituted into the variable fp. The intermediate code3209is an intermediate code that branches to the label L.

The intermediate code3210includes the label L2, and is an intermediate code that judges whether variable i is not equal to “3” The intermediate code3211branches to label L3when the judgement in intermediate code3210is true, which is to say, when variable i is not “3”. The intermediate code3212is executed when variable i is equal to “3”, and is an intermediate code that adds a difference, obtained by subtracting a first address of function f from the first address of function g3, to the temporary variable tmp into which the first address of function f has been substituted, and has the addition result substituted into the variable fp. The intermediate code3213is an intermediate code that branches to the label L.

The intermediate code3214includes the label L4, and is an intermediate code that adds a difference, obtained by subtracting a first address of function f from the first address of function g4, to the temporary variable tmp into which the first address of function f has been substituted, and has the addition result substituted into the variable fp. The intermediate code3215includes the label L and is an intermediate code that calls the function indicated by the variable fp.

As described above, the intermediate codes inFIG. 39do not simply substitute the absolute address of the function g1, g2, g3or g4into the variable fp, but instead add a difference between the first address of function f and the first address of one of the functions g1, g2, g3, and g4to the first address of the function f and substitute the addition result into the variable fp (steps S3601˜S3603).

Next, the PC value adding instruction converting unit2904converts the intermediate codes into assembler code. The PC value adding instruction converting unit2904searches for intermediate codes that add the value of the PC to a PC relative value and converts such codes into assembler code that uses the second lower PC calculator2800and the second upper PC calculator2802. The instruction converting unit2905then converts the remaining intermediate codes into assembler code.

The PC value adding instruction converting unit2904ascertains that the operand tmp in intermediate code3204inFIG. 39has been set at the value of the PC by the intermediate code3201and that the operator “+” indicates an addition of the value of the PC and a PC relative value, and so converts intermediate code3204into the assembler code addpc that performs an addition using the second lower PC calculator2800and the second upper PC calculator2802. In the same way, the PC value adding instruction converting unit2904converts intermediate codes3208,3212, and3214into assembler codes addpc. The other intermediate codes inFIG. 39are converted into assembler codes by the instruction converting unit2905.

FIG. 40shows the assembler code that has been produced by converting the intermediate codes shown in FIG.39. InFIG. 40, the assembler code3301has the label f marking the start of a function and is an instruction that transfers the value of the PC into register r1. The assembler code2802is an instruction that judges whether the constant “1” and the value of register r0are not equal. The assembler code3303is an instruction that branches to label L1when the judgement in assembler code2802is true. The assembler code3304has the second lower PC calculator2800and the second upper PC calculator2802add the PC relative value that is the difference between the first address of function g1and the first address of function f to the value of the PC which is the first address of function f and is stored in the register r1, and has the result transferred into register r1. The assembler code3305is an instruction that branches to the label L.

The assembler code3306has the label L1and is an instruction that judges whether the constant “2” and the value of register r0are not equal. The assembler code3307is an instruction that branches to label L2when the judgement in assembler code3306is true. The assembler code3308has the second lower PC calculator2800and the second upper PC calculator2802add the PC relative value that is the difference between the first address of function g2and the first address of function f to the value of the PC which is the first address of function f and is stored in the register r1, and has the result transferred into register r1. The assembler code3309is an instruction that branches to the label L.

The assembler code3310has the label L2and is an instruction that judges whether the constant “3” and the value of register r0are not equal. The assembler code3311is an instruction that branches to label L3when the judgement in assembler code3310is true. The assembler code3311has the second lower PC calculator2800and the second upper PC calculator2802add the PC relative value that is the difference between the first address of function g3and the first address of function f to the value of the PC which is the first address of function f and is stored in the register r1, and has the result transferred into register r1. The assembler code3313is an instruction that branches to the label L.

The assembler code3314has the label L3and is an instruction that has the second lower PC calculator2800and the second upper PC calculator2802add the PC relative value that is the difference between the first address of function g4and the first address of function f to the value of the PC which is the first address of function f and is stored in the register r1, and has the result transferred into register r1. The assembler code3315has the label L and is an instruction that calls the function indicated by register r1. The assembler code3316is an instruction that ends the function.

As described above, when there is a source code in function f that substitutes a pointer to the external function g into a pointer variable, the present compiler does not generate an instruction (such as “mov r1,g”) that transfers the address of the external function g into register r1, but instead generates an instruction (addpc g−f, r1) that has adds a difference (g−f) in addresses between function f and function g to the address of function f that is stored in register r1, and has the result transferred into register r1. Since the value of the PC relative value g−f is smaller that the absolute address g, the overall code size of programs can be reduced by using such addpc instructions. This has a further benefit for PIC codes where the addresses of a program in memory are determined when the program is executed, since calculation instructions that use such PC relative values must be used.

In the same way as in the first embodiment, the assembler code produced by the compiler of the present embodiment is converted into object code that can be executed by the processor by an optimization apparatus303, an assembler305and a linker307. The processor executes the PC adding instruction “addpc g−f,r1” in the generated object code using the second lower PC calculator2800and the second upper PC calculator2802. In detail, the second lower PC calculator2800adds the lower 3 bits of the constant “g−f” and the lower 3 bits of the value stored in register r1and sends any carry that is generated to the second upper PC calculator2802. The second upper PC calculator2802adds the upper 29 bits of the constant “g−f”, the upper 29 bits of the value stored in register r1, and any carry it has received from the second lower PC calculator2800. A value given by setting the addition result of the second lower PC calculator2800as the lower 3 bits and the addition result of the second upper PC calculator2802as the upper 29 bits is then set in register r1.

Note that while the instructions shown inFIGS. 35A and 35Brespectively are an addition and a subtraction of a constant and the value in a register, this need not be the case. An addition and a subtraction of values in registers, or an addition and a subtraction of a value in a register and the PC may equally be used.

The calculation method used by the second lower PC calculator2800and the second upper PC calculator2802also need not be the carry method used in the first embodiment. Provided the same method is used by the optimization apparatus303, assembler305, and linker307that generate the object code to be executed by the processor, any of a no-carry method, a linear method, and an absolute value method may be used.

Eighth Embodiment

The eighth embodiment of the present invention relates to a debugger and a disassembler.

FIG. 41is a block diagram showing the construction of the debugger and disassembler of the present embodiment.

The input control unit4000receives an input from the user and controls the other components according to this input.

The packet address specifying unit4001calculates the upper 29 bits of the address of the inputted instruction.

The in-packet address specifying unit4002calculates the lower 3 bits of the address of the inputted instruction.

The instruction memory4004stores the instructions to be processed by the debugger and disassembler. As in the first embodiment, the addresses of instructions are 32 bits in length and are composed of a packet address as the upper 29 bits and an in-packet address as the lower 3 bits.FIG. 41shows how the instructions shown inFIG. 25are stored.

The instruction reading unit4003reads an instruction packet indicated by the packet address specified by the packet address specifying unit4001from the instruction memory4004.

The instruction buffer4005stores the instruction packet read from the instruction memory4004by the instruction reading unit4003.

The instruction decoding unit4006extracts the instruction unit with the in-packet address specified by the in-picket address specifying unit4002from the instruction buffer4005and decodes the extracted instruction unit. When the instruction unit is a branch instruction, the instruction decoding unit4006sends the PC relative value4007to the lower PC calculator4008and the upper PC calculator4009.

The label table4011is a table storing each label name associated with a corresponding instruction address. This label table4011is generated by extracting described in the first embodiment generates machine language codes.

InFIG. 41, the address “32′h00000000” corresponds to the label f, the address “32′h00000008” corresponds to the label L1, and the address “32′h12345680” corresponds to the label L2.

The display unit4012displays the results of a disassembling of an instruction.

The instruction replacing unit4013writes the instruction that has been replaced into the instruction unit(s) in the instruction buffer4005that is/are indicated by the in-packet address specified by the in-packet address specifying unit4002.

The instruction writing unit4014rewrites the instruction packet in the instruction memory4004with the packet address specified by the packet address specifying unit4001using the amended instruction packet stored in the instruction buffer4005.

The upper PC calculator4009performs a calculation on the upper 29 bits of the instruction address specified by the packet address specifying unit4001and the upper 29 bits of the PC relative value4007.

The lower PC calculator4008performs a calculation on the lower 3 bits of the instruction address specified by the in-packet address specifying unit4002and the lower 3 bits of the PC relative value4007. The calculation methods used by these PC calculators is the same as that used when generating the object code.

The following describes a specific example of the operation of the present disassembler.FIG. 42is a flowchart showing the operating procedure of this disassembler.

First, the input control unit4000receives a command indicating the disassembling of an instruction and an input of the address of the instruction to be disassembled. In this specific example, the input control unit4000receives “32′h0000001a” as the instruction address (step S4100).

Next, the packet address specifying unit4001specifies the packet address from the upper 29 bits of the instruction address. The instruction reading unit4003then reads the instruction packet with the specified packet address from the instruction memory4004and stores it in the instruction buffer4005. In this example, “29′h00000003” is specified as the packet address, and the instruction sequence “ld (r2),r0||bra 13′h1fec||add r2,r3” is stored in the instruction buffer4005(step S4101).

The in-packet address specifying unit4002then specifies the in-packet address from the lower 3 bits of the instruction address and informs the instruction decoding, unit4006of the instruction unit that has the specified in-packet address. The instruction decoding unit4006then extracts the indicated instruction unit from the instruction buffer4005. In this example, “3′b010” is specified as the in-packet address and the instruction “bra 13′h1fec” that is the second unit in the instruction buffer4005is inputted into the instruction decoding unit4006(step S4102).

The instruction decoding unit4006judges whether the inputted instruction is a branch instruction. In this example, the inputted instruction “bra 13′h1fec” is a branch instruction, so that this judgement is true (step S4103).

When the instruction is a branch instruction, a calculation is performed on the PC relative value4007indicated in the instruction and address of the inputted instruction. The lower PC calculator4008performs an addition or a subtraction on the in-packet address of the inputted instruction and on the lower 3 bits of the PC relative value4007and sends the calculation result to the label search unit4010. The upper PC calculator4009performs an addition or a subtraction on the packet address of the inputted instruction and on the upper 29 bits of the PC relative value4007and sends the calculation result to the label search unit4010. The label search unit4010specifies the address of a label from the calculation result for the upper bits and the calculation result for the lower bits. In this example, the label address “32′h00000008” is specified by a calculation using the address “32′h0000001a” of the inputted instruction and the PC relative value4007“13′h1fec” (steps S4103, S4104).

The label search unit4010then refers to the label table4011and finds the label name that has the specified address. In this example, the label L1corresponds to the address “32′h00000008” (Step S4107).

The display unit4612displays the assembler name of the branch instruction and the label name found by the label search unit4010. In this example, the display unit4012displays the assembler name “bra” of the branch instruction and the corresponding label name “Label L1” (step S4108).

The instruction decoding unit4006has the display unit40112display only the assembler name when the extracted instruction is not an assembler instruction (Step S4109).

The following describes a specific example of the operation of the present debugger.

FIG. 43is a flowchart showing the operation of the present debugger.

First, the input control unit4000receives a command indicating the debugging of an instruction, the address of an instruction to be replaced, and the instruction to be used to replace of this instruction. In this specific example, the input control unit4000receives “32′h0000001a” as the instruction address and the subtraction instruction “sub r0,r1” as the replacement instruction (step S4200).

Nest, the packet address specifying unit4001specifies the packet address from the upper 29 bits of the instruction address. The instruction reading unit4003then reads the instruction packet with the specified packet address from the instruction memory4004and stores it in the instruction buffer4005. In this example, “29′h00000003” is specified as the packet address, and the instruction sequence “ld (r2),r0||bra 13′h1fec||add r2,r3” is stored in the instruction buffer4005(step S4201).

The in-packet address specifying unit4002then specifies the in-packet address from the lower 3 bits of the instruction address. In this example, the in-packet address “3′b010” is specified (step S4202).

If, the specified in-packet address is “3′b000”, the first unit in the instruction packet in the instruction buffer4005is replaced with the inputted replacement instruction. If the specified in-packet address is “3′b010”, the second unit in the instruction packet in the instruction buffer4005is replaced with the inputted replacement instruction. If the specified in-packet address is “3′b100”, the third unit in the instruction packet in the instruction buffer4005is replaced with the inputted replacement instruction. In this example, the specified in-packet address is “3′b010”, so that the instruction “bra 13′h1fec” in the second unit in the instruction packet in the instruction buffer4005is replaced with the inputted replacement instruction “sub r0,r1”. As a result, the instruction packet in the instruction buffer4005becomes “ld (r2).r0||sub r0,r1||add r2,r3” (steps S4203˜S4207).

The instruction writing unit4014replaces the instruction packet at the indicated packet address in the instruction memory4004with the instruction packet stored in the instruction buffer4005. In this example, the instruction packet “ld (r2),r0||bra 13′h1fec||add r2,r3” at the packet address “29′h00000003” in the instruction memory4004is replaced with the instruction packet “ld (r2),r0||sub r0,r1||add r2,r3” in the instruction buffer4005.

As, described above, the disassembler of the present embodiment can disassemble instructions that are executable for the processor309of the first embodiment. When an instruction is disassembled, instead of just displaying the PC relative value, the disassembler has the upper PC calculator and lower PC calculator calculate the address at which the label is located, uses the address to search the label table, and so displays the appropriate label name.

The debugger of the present embodiment reads instructions from the memory in units of instruction packets that are byte-aligned, rewrites an instruction in the instruction buffer, and writes the instructions back into the memory in units of instruction packets. This method is suited to the debugging of instructions that are not byte-aligned.

Note that the calculation methods used by the lower PC calculator and the upper PC calculator do not need to be the carry method described in the first embodiment, so that another method, such as a separation method, an absolute value method, or a linear method, can be used.

The compiler, optimization apparatus, assembler, linker, processor, disassembler, and debugger of the present invention have been explained by way of the first to eighth embodiments of the present invention, though it should be obvious that the present invention is not limited to these. Two example modifications are given below.

(1) In the first to sixth embodiments, the assembler code302, the optimized code304, the relocatable codes306, and the object code308may be stored in a mask ROM, a semiconductor memory such as flash memory, a magnetic storage medium such as a floppy disk or a hard disk, or an optical disc such as a CD-ROM or DVD.

(2) In the seventh embodiment, the assembler codes2906may be stored in a mask ROM, a semiconductor memory such as flash memory, a magnetic storage medium such as a floppy disk or a hard disk, or an optical disc such as a CD-ROM or DVD.