Common plate capacitor array connections, and processes of making same

A process of forming a semiconductive capacitor device for a memory circuit includes forming a first capacitor cell recess and a second capacitor cell recess that are spaced apart by a capacitor cell boundary of a first height. The process includes lowering the first height of the capacitor cell boundary to a second height. A common plate capacitor bridges between the first recess and the second recess over the boundary above the second height and below the first height.

TECHNICAL FIELD

Disclosed embodiments relate to semiconductor capacitor devices and processes of making them.

BACKGROUND

Many layers of connectivity are required in typical backend processing for semiconductor chips such as for cell and plate fabrication of dynamic random-access memory cells. Several techniques have been used including forming a plate metal layer that is used to connect to the tops of individual capacitors. This requires an extra metal layer, complete with the usual lithography requirements, etch requirements, capacitor cell-filling requirements, and polishing associated with dual-damascene processing. Another method is to separately pattern a plate connection directly on top of the capacitor cell, which also requires several processes.

DETAILED DESCRIPTION

Reference will now be made to the drawings wherein like structures may be provided with like suffix reference designations. In order to show the structures of various embodiments most clearly, the drawings included herein are diagrammatic representations of integrated circuit structures. Thus, the actual appearance of the fabricated structures, for example in a photomicrograph, may appear different while still incorporating the claimed structures of the illustrated embodiments. Moreover, the drawings may only show the structures necessary to understand the illustrated embodiments. Additional structures known in the art may not have been included to maintain the clarity of the drawings. Although a processor chip and a memory chip may be mentioned in the same sentence, it should not be construed that they are equivalent structures.

Reference throughout this disclosure to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. The appearance of the phrases “in one embodiment” or “in an embodiment” in various places throughout this disclosure are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

FIG. 1ais a cross-section elevation of a capacitor structure100during processing according to an example embodiment. A dielectric layer110has been overlaid with a base dielectric layer112. The base dielectric layer112is spaced apart from a semiconductive substrate by the dielectric layer110. The semiconductive substrate is direct-contact interfaced at the bottom111of the dielectric layer110. The base dielectric layer112has been overlaid with a capacitor cell interlayer dielectric layer114. A mask116has been formed and patterned above the interlayer dielectric layer114to prepare for a directional etch that will result in capacitor cell recesses.

FIG. 1bis a cross-section elevation of a capacitor structure depicted inFIG. 1aafter further during processing according to an embodiment. The capacitor structure101has been directionally etched such that the capacitor cell interlayer dielectric layer114has been fully penetrated as well as the base dielectric layer112. Directional etching has stopped on the dielectric layer110. The directional etching has further exposed capacitor cell bit-line contacts118that are in contact with the semiconductive substrate.

The directional etching has also resulted in the capacitor cell interlayer dielectric layer114forming a capacitor cell boundary (two occurrences are illustrated inFIG. 1bat120and122) having a first height124. Ecthing has also resulted in a first capacitor cell recess126and an adjacent second capacitor cell recess128that is spaced apart in a first direction by the capacitor cell boundary120. Further as a result of etching, a subsequent capacitor cell recess130is adjacent the second capacitor cell recess128and is spaced apart by the capacitor cell boundary122. Unpenetrated portions of the capacitor cell interlayer dielectric layer114also exhibit the first height124. The first capacitor cell recess126and an adjacent second capacitor cell recess128are spaced apart from the semiconductive substrate in a second direction by the dielectric layer110.

In an embodiment, the number of capacitor cell recesses is determined by requirements for a memory circuit such as a dynamic random-access memory (DRAM) array number. In an embodiment, the number of capacitor cell recesses is related to an embedded DRAM (eDRAM) array on a processor device. In an embodiment, the number of capacitor cell recesses is related to a dedicated DRAM array on a memory device.

FIG. 1cis a cross-section elevation of a capacitor structure depicted inFIG. 1bafter further during processing according to an embodiment. The capacitor structure102has been subject to further etching that has resulted in the first height (124,FIG. 1b) of the boundaries120and122being lowered to a second height125, and the boundaries120and122inFIG. 1bare altered and enumerated as the boundaries121and123. A faceting132has occurred between a top surface134of the capacitor cell interlayer dielectric layer114and a wall surface136of the first recess126. The degree of faceting132is dependent upon etch conditions such as etch intensity and the degree of directionality of the etch. The degree of faceting132is also dependent upon thickness108of the boundaries121and123.

In an embodiment, etching is more directional such that clipping of the boundaries120and122(FIG. 1b) result in the boundaries121and123at the second height125as illustrated inFIG. 1c. In an embodiment, etching is more isotropic such that faceting132is more pronounced. Such etching is referred to as flare etching such that the faceting132appears as a flaring of the boundaries121and123to reach the second height125. The degree of faceting132, whether by a predominantly clipping effect or a flaring effect, is dependent upon thickness108of the boundaries121and123. Faceting of the capacitor cell interlayer dielectric layer114may result in a facet angle138. Further as a result of etching, faceting of the capacitor cell boundary123may result in a facet angle140

FIG. 1dis a cross-section elevation of a capacitor structure depicted inFIG. 1cafter further during processing according to an embodiment. The capacitor structure103has been processed by conformally depositing a capacitor electrode film142into the recesses. In an embodiment, formation of the capacitor electrode film142is done simultaneously with clipping of the boundaries120and122(FIG. 1b) to obtain the boundaries121and122at the second height125. Processing may include a plasma physical vapor deposition (PVD, also referred to as sputtering) of the capacitor electrode film142under conditions that cause the boundaries120and122to become the lowered boundaries121and123, respectively. In an embodiment, a plasma sputtering of tantalum is carried out, beginning with the capacitor structure101depicted inFIG. 1b, to achieve the capacitor electrode film142depicted inFIG. 1d. In an embodiment, tantalum nitride is sputtered to form the capacitor electrode film142. In an embodiment, titanium is sputtered to form the capacitor electrode film142. In an embodiment, titanium nitride is sputtered to form the capacitor electrode film142.

After formation of the capacitor electrode film142, a sacrificial filler144is blanket formed over the capacitor structure103and etched back to a third height146as depicted. The third height146is less than the second height125(FIG. 1c). In an embodiment, the sacrificial filler144is a dielectric that responds differently to etching processes than the capacitor electrode film142such that the capacitor electrode film142is virtually unaltered during etchback to form the sacrificial filler144.

FIG. 1eis a cross-section elevation of a capacitor structure depicted inFIG. 1dafter further during processing according to an embodiment. The capacitor structure104has been processed by isotropic etching such that the capacitor electrode film142has been removed in areas not protected by the sacrificial filler144. Consequently the capacitor electrode film142has been altered in structure to achieve singulated capacitor electrodes.FIG. 1eillustrates singulated capacitor electrodes including a first capacitor electrode148, a second capacitor electrode150, and a subsequent capacitor electrode152.

FIG. 1fis a cross-section elevation of a capacitor structure depicted inFIG. 1eafter further during processing according to an embodiment. The capacitor structure105has been processed by a conformal deposition of a capacitor cell dielectric film154within the respective recesses and upon the top surface134of the interlayer dielectric layer114. In an embodiment, the capacitor cell dielectric film154is a high-k material such as. High-k dielectric materials may be materials with a dielectric constant greater than that of silicon dioxide, which is about 4. In an embodiment, the high-k dielectric material is tantalum pentoxide (Ta2O5). In an embodiment, the high-k dielectric material is hafnium oxide (HfO2). In an embodiment, the high-k dielectric material is zirconium oxide (ZrO2). In an embodiment, the high-k dielectric material is aluminum oxide (Al2O3). In an embodiment, the high-k dielectric material is barium strontium titanate (BaSrTiO3). In an embodiment, the high-k dielectric material that forms the capacitor cell dielectric film154is a composite such as laminates of ZrO2/Al2O3/ZrO2.

In an embodiment, a barrier film156is deposited onto the capacitor cell dielectric film154to facilitate the formation of a common plate capacitor. In an embodiment, the barrier film156is a tantalum (Ta) material. In an embodiment, the barrier film156is a tantalum nitride (TaxNy) material, where x and y may represent stoichiometric and non-stoichiometric ratios. In an embodiment, the barrier film is a titanium (Ti) material. In an embodiment, the barrier film156is a titanium nitride (TixNy) material, where x and y may represent stoichiometric and non-stoichiometric ratios. The barrier film156is to make physical contact with a common plate capacitor. After formation of the barrier film156, if it is present, a blanket deposition of a common plate capacitor precursor158is formed over the capacitor cell dielectric film154.

FIG. 1gis a cross-section elevation of a capacitor structure depicted inFIG. 1fafter further during processing according to an embodiment. The capacitor structure106has been processed by a height-reduction procedure on the common plate capacitor precursor158(FIG. 1f) to achieve a common plate capacitor159. In an embodiment, processing is done by a chemical-mechanical polishing (CMP) procedure that stops on the capacitor cell dielectric film154and/or the capacitor cell interlayer dielectric layer114. The polishing procedure results in a fourth height160, measured from the bottom of the recesses, which is greater than the second height125, which is the height of the boundaries121and123after clipping or flaring has been accomplished as set forth above.

As a consequence of the polishing procedure, the common plate capacitor159forms a capacitance bridge162between the first capacitor electrode148and the second capacitor electrode150. Further as a consequence of the polishing procedure, the common plate capacitor159also forms a capacitance bridge164between the second capacitor electrode150and the subsequent capacitor electrode152. The common plate capacitor159has a solid-plug form factor within each recess. Consequently, the common plate capacitor159completes each capacitor structure and the array of capacitors is a common plate structure by virtue of the capacitance bridges162and164.

FIG. 2is a computer-image reproduction of a photomicrograph200in cross section elevation of a capacitor cell boundary during processing according to an embodiment. The photomicrograph relates partially to the illustrated capacitance bridge sections162and164according to various embodiments. As illustrated, the height of a capacitor cell boundary221was lowered, but it retained a substantially rectangular form factor.

The capacitor cell boundary221is illustrated that includes a capacitor cell dielectric film254that was formed. In an embodiment, the capacitor cell boundary221is etched by a clipping procedure to achieve a lowered, second height compared to a first height. In an embodiment, the capacitor cell boundary221is etched by a flaring procedure to achieve a lowered, second height compared to a first height.

In an embodiment, a barrier film256was formed conformally upon the capacitor cell dielectric film254.

FIG. 3is a computer-image reproduction of a photomicrograph300in cross section elevation of a capacitor cell boundary during processing according to an embodiment. The photomicrograph also relates partially to the illustrated capacitance bridge sections162and164according to various embodiments. As illustrated, the height of a capacitor cell boundary121was lowered, but it also achieved a substantially truncated cone form factor.

The capacitor cell boundary321is illustrated that includes a capacitor cell dielectric film354that was formed. In an embodiment, the capacitor cell boundary321is etched by a clipping procedure to achieve a lowered, second height compared to a first height. In an embodiment, the capacitor cell boundary321is etched by a flaring procedure to achieve a lowered, second height compared to a first height.

FIG. 4is a process flow diagram400according to an embodiment.

At410the process includes forming a first capacitor cell recess and a second capacitor cell recess that are spaced apart by a capacitor cell boundary of a first height.

At420, the process includes lowering the capacitor cell boundary from the first height to a second height.

At430, the process includes completing a first capacitor in the first capacitor cell recess and a second capacitor in the second capacitor cell recess.

At421, the process of lowering of the first height includes a clipping etch. At422the clipping etch includes simultaneously forming a capacitor cell electrode film.

At423, the process of lowering of the first height includes a flaring etch. At424the flaring etch includes simultaneously forming a capacitor cell electrode film.

At425, the process includes forming a capacitor cell dielectric layer.

At426, the process includes forming a barrier film on the capacitor cell dielectric layer. In a non-limiting example embodiment, a tantalum barrier film is formed. In a non-limiting example embodiment, a tantalum nitride barrier film is formed. In a non-limiting example embodiment, a titanium barrier film is formed. In a non-limiting example embodiment, a titanium nitride barrier film is formed.

At430, where the process of completing the first capacitor cell and the second capacitor cell are done, the process includes forming a common capacitor cell plate. In a non-limiting example embodiment, forming the common plate capacitor structure includes a blanket deposition of a plate structure such as a copper metal, followed by a CMP procedure that leaves the bridge162in the case of the first capacitor electrode148and the second capacitor electrode150.

FIG. 5is a schematic of an electronic system according to an embodiment. The electronic system500as depicted can embody a semiconductive capacitor device that includes a common plate capacitor that bridges between a first capacitor cell and a second capacitor cell, over a boundary according to any of the several disclosed embodiments and their equivalents as set forth in this disclosure. In an embodiment, the electronic system500is a computer system that includes a system bus520to electrically couple the various components of the electronic system500. The system bus520is a single bus or any combination of busses according to various embodiments. The electronic system500includes a voltage source530that provides power to the integrated circuit510. In some embodiments, the voltage source530supplies current to the integrated circuit510through the system bus520.

The integrated circuit510is electrically coupled to the system bus520and includes any circuit, or combination of circuits according to an embodiment. In an embodiment, the integrated circuit510includes a processor512that can be of any type. As used herein, the processor512may mean any type of circuit such as, but not limited to, a microprocessor, a microcontroller, a graphics processor, a digital signal processor, or another processor. Other types of circuits that can be included in the integrated circuit510are a custom circuit or an application-specific integrated circuit (ASIC), such as a communications circuit514for use in wireless devices such as cellular telephones, pagers, portable computers, two-way radios, and similar electronic systems. In an embodiment, the processor510includes on-die memory516such as static random-access memory (SRAM). In an embodiment, the processor510includes embedded on-die memory516such as embedded dynamic random-access memory (eDRAM).

In an embodiment, the electronic system500also includes an external memory540that in turn may include one or more memory elements suitable to the particular application, such as a main memory542in the form of RAM, one or more hard drives544, and/or one or more drives that handle removable media546, such as diskettes, compact disks (CDs), digital variable disks (DVDs), flash memory keys, and other removable media known in the art.

In an embodiment, the electronic system500also includes a display device550, an audio output560. In an embodiment, the electronic system500includes a controller570, such as a keyboard, mouse, trackball, game controller, microphone, voice-recognition device, or any other device that inputs information into the electronic system500.

As shown herein, the integrated circuit510can be implemented in a number of different embodiments, including a semiconductive capacitor device that includes a common plate capacitor that bridges between a first capacitor cell and a second capacitor cell, over a boundary according to any of the several disclosed embodiments and their equivalents, an electronic system, a computer system, one or more methods of fabricating an integrated circuit, and one or more methods of fabricating an electronic assembly that includes a semiconductive capacitor device that includes a common plate capacitor that bridges between a first capacitor cell and a second capacitor cell, over a boundary according to any of the several disclosed embodiments as set forth herein in the various embodiments and their art-recognized equivalents. The elements, materials, geometries, dimensions, and sequence of operations can all be varied to suit particular semiconductive capacitor device embodiments that include a common plate capacitor that bridges between a first capacitor cell and a second capacitor cell over a boundary.

It will be readily understood to those skilled in the art that various other changes in the details, material, and arrangements of the parts and method stages which have been described and illustrated in order to explain the nature of this invention may be made without departing from the principles and scope of the invention as expressed in the subjoined claims.