A three-dimensional phase-change memory array. In one embodiment of the invention, the memory array includes a first plurality of diodes, a second plurality of diodes disposed above the first plurality of diodes, a first plurality phase-change memory elements disposed above the first and second plurality of diodes and a second plurality of memory elements disposed above the first plurality of memory elements.

FIELD OF THE INVENTION

The present invention is related to electrically operated phase-change memory. In particular, the present invention relates to a three-dimensional memory array comprising electrically operated phase-change memory.

BACKGROUND OF THE INVENTION

Programmable resistance memory elements formed from materials that can be programmed to exhibit at least a high or low stable ohmic state are known in the art. Such programmable resistance elements may be programmed to a high resistance state to store, for example, a logic ONE data bit or programmed to a low resistance state to store a logic ZERO data bit.

One type of material that can be used as the memory material for programmable resistance elements is phase-change material. Phase-change materials may be programmed between a first structural state where the material is generally more amorphous (less ordered) and a second structural state where the material is generally more crystalline (more ordered). The term “amorphous”, as used herein, refers to a condition which is relatively structurally less ordered or more disordered than a single crystal and has a detectable characteristic, such as high electrical resistivity. The term “crystalline”, as used herein, refers to a condition which is relatively structurally more ordered than amorphous and has lower electrical resistivity than the amorphous state.

The phase-change materials may be programmed between different detectable states of local order across the entire spectrum between completely amorphous and completely crystalline states. That is, the programming of such materials is not required to take place between completely amorphous and completely crystalline states but rather the material can be programmed in incremental steps reflecting (1) changes of local order, or (2) changes in volume of two or more materials having different local order so as to provide a “gray scale” represented by a multiplicity of conditions of local order spanning the spectrum between the completely amorphous and the completely crystalline states. For example, phase-change materials may be programmed between 3 or more resistive states to store more than 1 bit of information in one memory cell. For example, phase-change materials may be programmed between four resistance states to store 2 bits of information in a memory cell.

A volume of phase-change material may be programmed between a more ordered, low resistance state and a less ordered, high resistance state. A volume of phase-change is capable of being transformed from a high resistance state to a low resistance state in response to the input of a single pulse of energy referred to as a “set pulse”. The set pulse is sufficient to transform a volume of memory material from the high resistance state to the low resistance state. It is believed that application of a set pulse to a volume of memory material changes the local order of at least a portion of the volume of memory material. Specifically, it is believed that the set pulse is sufficient to change at least a portion of a volume of memory material from a less-ordered amorphous state to a more-ordered crystalline state.

A volume of memory material is also capable of being transformed from the low resistance state to the high resistance state in response to the input of a single pulse of energy which is referred to as a “reset pulse”. The reset pulse is sufficient to transform a volume of memory material from the low resistance state to the high resistance state. While not wishing to be bound by theory, it is believed that application of a reset pulse to a volume of memory material changes the local order of at least a portion of the volume of memory material. Specifically, it is believed that the reset pulse is sufficient to change at least a portion of the volume of memory material from a more-ordered crystalline state to a less-ordered amorphous state.

The use of phase-change materials for electronic memory applications is known in the art. Phase-change materials and electrically programmable memory elements formed from such materials are disclosed, for example, in U.S. Pat. Nos. 5,166,758, 5,296,716, 5,414,271, 5,359,205, 5,341,328, 5,536,947, 5,534,712, 5,687,112, and 5,825,046 the disclosures of which are all incorporated by reference herein. Still another example of a phase-change memory element is provided in U.S. patent application Ser. No. 09/276,273, the disclosure of which is also incorporated herein by reference.

It is important to be able to accurately read the resistance states of programmable resistance elements which are arranged in a memory array. The present invention describes an apparatus and method for accurately determining the resistance states of programmable resistance elements arranged as memory cells in a memory array. Background art circuitry is provided in U.S. Pat. No. 4,272,833 which describes a reading apparatus based upon the variation in the threshold levels of memory elements, and U.S. Pat. No. 5,883,827 which describes an apparatus using a fixed resistance element to generate reference signals. Both U.S. Pat. No. 4,272,833 and U.S. Pat. No. 5,883,827 are incorporated by reference herein.

SUMMARY OF THE INVENTION

An aspect of the present invention is a memory array, comprising: a plurality of first isolation elements; a plurality of second isolation elements disposed above the first isolation elements; a plurality of first phase-change memory elements disposed above the second isolation elements, each of the first memory elements electrically coupled to a corresponding one of the first isolation elements; and a plurality of second phase-change memory elements disposed above the first memory elements, each of the second memory elements electrically coupled to a corresponding one of the plurality of second isolation elements.

Another aspect of the present invention is a memory array, comprising: a plurality of lower first conductive lines; a plurality of upper first conductive lines disposed above the lower first conductive lines; a plurality of lower second conductive lines disposed above the upper first conductive lines, the lower second conductive lines crossing the lower and upper first conductive lines; a plurality of upper second conductive lines disposed above the lower second conductive lines, the upper second conductive lines crossing the lower and upper first conductive lines; a plurality of first phase-change memory cells, each of the first phase-change memory cells coupled between a corresponding lower first conductive line and a lower second conductive line; and a plurality of second phase-change memory cells, each of the second phase-change memory cells coupled between a corresponding upper first conductive line and a corresponding upper second conductive line.

Another aspect of the present invention is an integrated circuit, comprising: a memory array, comprising: a plurality of first address lines, each of the first address lines having a width W1; a plurality of second address lines crossing the first address lines, each of the second address lines having a width W2; and a plurality of phase-change memory cells, each of the memory cells electrically coupled between a corresponding one of the first address lines and a corresponding one of the second address lines, wherein the cell size of the memory array is less than 4(W1) (W2). It is, of course, noted that the notation 4(W1) (W2) means: 4 times W1times W2.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 18shows an isometric view of an embodiment of a three-dimensional memory array of the present invention.FIGS. 1 through 18are three-dimensional isometric views illustrating the step-by-step fabrication of the three-dimensional memory array shown inFIG. 18.FIGS. 19A,19B,19C and19D show cross-sectional views of the memory array shown inFIG. 18through the cross-sections XA-XA, XB-XB, YA-YA and YB-YB, respectively. The cross-section through diode strip DSU1is the same as the cross-section YA-YA and the cross-section through diode strip DSL1is the same as the cross-section YB-YB. Likewise, the cross-section through lower memory strip MSL2is the same as the cross-section XA-XA and the cross-section through upper memory strip MSU2is the same as the cross-section XB-XB.

FIG. 20shows that same three-dimensional memory array fromFIG. 18except that the dielectric layers have been removed so that the components of the memory array can more clearly be seen.FIGS. 21A,21B,21C and21D show cross-sectional views of the memory array shown inFIG. 20through the cross-sections XA-XA, XB-XB, XC-XC and XD-XD, respectively.FIG. 23Ashows a top view of the three-dimensional memory array shown inFIG. 20.

The step-by-step fabrication of the memory array shown inFIG. 18andFIG. 20will now be discussed. At each step of the process, the reader is also referred to the cross-sectional views XA-XA, XB-XB, YA-YA, YB-YB, shown inFIGS. 19A through 19D, respectively. Referring toFIG. 1, a conductive layer110is formed on a semiconductor substrate10. The substrate10may be a conventional silicon monocrystalline substrate with a dielectric layer, such as silicon dioxide, deposited thereon. Alternately, the substrate10may be a silicon-on-sapphire substrate, a dielectrically isolated substrate or a silicon-on-insulator substrate, each with a dielectric layer, such as silicon dioxide deposited thereon. The substrate10may include peripheral circuitry such as driver circuitry and/or address circuitry.

An n+ type silicon layer112is then deposited on the conductive layer110and an n type silicon layer114is deposited on the n+ type layer112. The layer112and the layer114are preferably deposited either as amorphous silicon or as polysilicon. Referring toFIG. 2, the n type layer114may then be appropriately masked and portions of the n type layer114may then be doped (using, for example, ion implantation or diffusion techniques) to form p+ type strips116in the n type layer114. The p+ type strips116may have a width in the X-direction of about ( 5/3)F. “F” is the minimum photolithographic feature size. The minimum feature size may be the limit achievable by lithographic techniques. In one embodiment, the feature size F may be about 1000 Angstroms or less.

After the structure shown inFIG. 2is completed so that the p+ strips116are formed, the structure is subjected to a recrystallization process. This process converts the amorphous silicon material or polysilicon material of the n+ type layers112, the n type layers114and the p+ type layers116to a substantially monocrystalline material.

Referring toFIG. 3, the layers110,112,114and116are masked and etched to form lower diode strips DSL1and DSL2. The diode strip DSL1includes a lower conductive line110a. The diode strip DSL1also includes a lower diode DL11and a lower diode DL12defined by the semiconductor junctions between the n type layer114and the p+ type regions116. Diodes DL11and DL12are electrically coupled to the conductive line110a.

Likewise, diode strip DSL2includes a lower conductive line110b. The diode strip DSL2also includes a lower diode DL21and a lower diode DL22defined by the semiconductor junctions between the n type layer114and the p+ type regions116of diode strip DSL2. Diodes DL21and DL22are electrically coupled to the conductive line110b.

The conductive lines110aand110bmay serve as address lines for the memory array. In the embodiment shown, the conductive line110ais designated as a first lower row line RL1for the memory array while the conductive line110bis designated as a second lower row line RL2for the memory array. The lower row lines may also be referred to as lower word lines. The lower row lines RL1and RL2are laterally spaced apart in the Y-direction. The space between the lines may be equal to the width of the row lines.

In an embodiment of the invention, the lower diodes strips DSL1and DSL2may each be formed so as to have a width in the Y-direction of about ( 5/3)F. Hence, the corresponding lower row lines RL1, RL2may have the same width in the Y-direction of about ( 5/3F). The lower diodes DL11, DL12, DL21, DL22may thus have a lateral dimension in the X-direction and a lateral dimension in the Y-direction of about ( 5/3)F.

As shown inFIG. 4, a dielectric material150is disposed between as well as over the lower diode strips and planarized using chemically mechanically polished (CMP) to form the structure shown inFIG. 4. As shown inFIG. 4, the dielectric layer150includes a first portion150awhich fills the gaps between the diode strips DSL1and DSL2as well as a second portion150bwhich is disposed above the diode strips. As shown inFIGS. 19A-D, the height of the second portion150bis represented as dZ1. The distance dZ1represents the thickness of the second portion150b. In another embodiment, a spin-on-glass (SOG) may be used to fill the voids between the adjacent diode strips. In this case, alternative planarization approaches can be used, such as plasma etching, for example. Other fill and planarization methods may be used.

Referring toFIG. 5, a conductive layer210is formed over the dielectric layer150, an n+ type silicon layer212is formed over the conductive layer210, and an n type silicon layer214is formed over the n+ type layer212. The n+ type layer as well as the n type layer may be deposited as amorphous silicon or as polysilicon. The n type layer214is then appropriately masked and doped to form p+ strips216as shown inFIG. 6using patterning and dopant introduction techniques well known in the art (where dopant introduction techniques include, for example, ion implantation or diffusion techniques). The p+ strips216may have a width in the X-dimension of about ( 5/3)F.

After the structure shown inFIG. 6is completed so that the p+ strips216are formed, the structure is subjected to a recrystallization process. This process converts the amorphous silicon material or polysilicon material of the n+ type layers212, the n type layers214and the p+ type layers216to a substantially monocrystalline material.

The conductive layer210, n+ type layer212, n type layer214and the p+ strips216are then masked and etched to form the upper diode strips DSU1and DSU2as shown inFIG. 7. The upper diode strip DSU1includes a conductive line210a. The diode strip DSU1also includes a first upper diode DU11and a second upper diode DU12defined by the semiconductor junctions between the n type layer214and the p+ type regions216of upper diode strip DSU1. Diodes DU11and DU12are electrically coupled to the conductive line210a.

Likewise, upper diode strip DSU2includes a conductive line210b. The diode strip DSU2also includes a first upper diode DU21and a second upper diode DU22defined by the semiconductor junctions between the n type layer214and the p+ type regions216of diode strip DSU2. Diodes DU21and DU22are electrically coupled to the conductive line210b. The conductive lines210aand210bmay also serve as address lines for the memory array. In the embodiment shown, the conductive line210ais designated as a first upper row line RU1for the memory array. Likewise, the conductive line210bis designated as a second upper row line RU2for the memory array. The upper and lower row lines RU1, RU2, RL1and RL2are laterally spaced apart in the Y-direction. The space between the lines may be equal to the width of the row lines. Hence, the space between the lines may have a lateral distance in the Y direction which may be ( 5/3)F.

It is noted that the upper row lines RU1, RU2are disposed above the lower row lines. In addition, the upper row lines RU1, RU2are staggered with respect to the lower row lines RL1, RL2. The placement of the lower and upper row lines alternate in the Y-direction so that a lower row line is following by an upper row line and an upper row line is followed by a lower row line. In one embodiment, the upper and lower row lines may not overlap at all. In another embodiment, there may be some overlap between the upper and lower row lines.

In an embodiment of the invention, the upper diode strips DSU1and DSU2may be formed so as to have a width in the Y-direction of about ( 5/3)F. Hence, the corresponding row lines RU1, RU2may also have a width in the Y-direction of about ( 5/3)F. The diodes DU11, DU12, DU21, DU22may thus have a lateral dimension in the Y-dimension equal to about ( 5/3)F as well as a lateral dimension in the X-dimension of about ( 5/3)F.

It is noted that the upper diode strips DSU1, DSU2are formed above the lower diode strips DSL1, DSL2. The upper and lower strips are separated vertically by a distance dZ1which is the thickness of the dielectric layer portion150b. The upper diode strips DSU1, DSU2are disposed above the lower diode strips even through they do not overlap the lower diode strips in the embodiment shown inFIG. 7. In another embodiment of the invention, it is possible that the upper diode strips may overlap the lower diode strips.

A dielectric material250is disposed between the upper diode strips DSU1and DSU2as well as over the diode strips DSU1and DSU2and then chemically mechanically polished (CMP) to form the planarized structure shown inFIG. 8. As shown, the dielectric layer250includes a first portion250adisposed between the upper diode strips DSU1and DSU2as well as a second portion250bdisposed above the upper diode strips DSU1and DSU2. The height of the second dielectric portion250bis designated as dZ2as shown inFIGS. 19A-D.

Referring toFIG. 9(as well as the cross-sectional views shown inFIGS. 19A and 19D), openings264are formed through the dielectric layer250(which includes dielectric layer portions250aand250b) and dielectric layer portion150bso as to expose the top surfaces of p+ regions116of lower diodes DL11, DL12, DL21and DL22. In the embodiment shown, the openings264have a circular cross section. However, in other embodiments, the openings may be formed to have a square or rectangular cross section. The openings264may be formed using standard lithographic techniques. The width (e.g. diameter) of the openings264may be about one feature size F. In other embodiments of the openings may be made to have a smaller width (e.g. diameter) by placing dielectric spacers along the sidewalls of the openings.

Referring toFIG. 10, each of the openings264are filled with a conductive material266(which is chemically mechanically polished) to form lower conductive plugs PL11, PL12, PL21and PL22that are electrically coupled to the p+ material116of the lower diodes DL11, DL12, DL21and DL22, respectively. The lower conductive plugs have a width (e.g. diameter) that corresponds to the width of the openings264. Hence, in an embodiment of the invention, the width (e.g. diameter) of the conductive plugs may be about one feature size F.

Referring toFIG. 11, a phase-change material310is then formed over the top surface of the conductive plugs as well as over the top surface of dielectric layer250(more specifically, over dielectric layer portion250a). A conductive layer312is formed over the phase-change material layer310.

Referring toFIG. 12, the layers310and312are masked and etched to form lower memory strips MSL1and MSL2. Lower memory strip MSL1is positioned so that the phase-change material310of lower memory strip MSL1is formed over the top surface of the lower conductive plug PL11and over the top surface of lower conductive plug PL21. Likewise, lower memory strip MSL2is positioned so that the phase-change material310of lower memory strip MSL2is formed over the top surface of lower conductive plug PL12and over the top surface of lower conductive plug PL22. The lower memory strip MSL1includes a conductive layer312awhich forms a first lower column line CL1for the memory array. Likewise, the lower memory strip MSL2includes a conductive layer312bwhich forms a second lower column line CL2for the memory array.

In an embodiment of the invention, the lower memory strips MSL1and MSL2may each be formed so as to have a width in the X-direction of about ( 5/3)F. Hence, the corresponding lower column lines CL1, CL2may also have a width in the X-direction of about ( 5/3)F.

Referring toFIG. 13, a dielectric material350is deposited between the lower memory strips MSL1and MSL2as well as over the lower memory strips MSL1, MSL2. The dielectric material is then chemically mechanically polished. The dielectric layer350may be viewed as having a first portion350awhich fills the gaps between the memory strips as well as a second portion350bwhich is formed above the memory strips. The height of the second portion350bis designated as dZ3as shown inFIGS. 19A-D.

Referring toFIG. 14(as well as cross-section shown inFIGS. 19B and 19D), openings364are formed through the dielectric layer350(including both dielectric layer portions350band350a) as well as dielectric layer portion250bso that the openings364expose the top surfaces of the p+ regions216of upper diodes DU11, DU12, DU21and DU22. In the embodiment shown, the openings364have a circular cross-section. More generally, the cross-section may be of any shape including, but not limited to, square and rectangular. In an embodiment, the openings364may have a width (e.g. a diameter) of about one feature size F. In another embodiment of the invention, the openings may be made smaller by forming dielectric sidewall spacers on the sidewalls of the openings.

Referring toFIG. 15, each of the openings364are filled with a conductive material366and the conductive material is chemically mechanically polished (CMP) to form upper conductive plugs PU11, PU12, PU21and PU22that are electrically coupled to the top surfaces of the p+ regions216of upper diodes DU11, DU12, DU21and DU22, respectfully. The width of the conductive plugs corresponds to the width of the openings364. Hence, the width of each of the conductive plugs may be about one feature size F.

Referring toFIG. 16, a phase-change material410is then formed over the top surface of the upper conductive plugs as well as over dielectric layer portion350bof the dielectric layer350. A conductive layer412is formed over the phase-change material layer410.

Referring toFIG. 17, the layers310and312are masked and etched to form upper memory strips MSU1and MSU2. The upper memory strip MSU1is positioned so that the phase-change material410of upper memory strip MSU1is formed over the top surface of the upper conductive plug PU11and over the top surface of upper conductive plug PU21. Likewise, upper memory strip MSU2is positioned so that the phase-change material410of upper memory strip MSU2is formed over the top surface of upper conductive plug PU12and over the top surface of upper conductive plug PU22. The upper memory strip MSU1includes a conductive layer412awhich serves as a first upper column line CU1for the memory array. The upper memory strip MSU2includes a conductive layer412bwhich serves as a second upper column line CU2for the memory array.

In an embodiment of the invention, the upper memory strips MSU1and MSU2may be formed so as to have a width in the X-direction of about ( 5/3)F. Hence, the corresponding upper column lines CU1, CU2may also have a width in the X-direction of about ( 5/3)F.

In the embodiment shown inFIG. 17, the upper memory strips MSU1, MSU2are disposed above the lower memory strips MSL1, MSL2. The upper memory strips are vertically separated from the lower memory strips by the thickness of the dielectric layer portion350bwhich is dZ3. In the embodiment shown inFIG. 17, the upper memory strips are disposed above the lower memory strips even though the upper memory strips do not overlap the lower memory strips. However, in alternate embodiments of the invention, it is possible that the upper and lower memory strips may overlap.

Referring toFIG. 18, a dielectric layer500is formed between upper memory strips MSU1, MSU2as well as over upper memory strips MSU1and MSU2. The dielectric layer500may be viewed as having a first portion500adisposed between the upper memory strips MSU1, MSU2as well as a second portion500bdisposed above the upper memory strips MSU1, MSU2.

As noted above,FIG. 20shows a view of the three-dimensional memory array fromFIG. 18except that all of the dielectric layers have been removed for clarity.FIG. 20shows the lower diode strips DSL1, DSL2as well as the upper diode strips DSU1, DSU2.FIG. 20also shows the lower memory strips MSL1, MSL2as well as the upper memory strips MSU1, MSU2.FIG. 20also shows the lower plugs PL11, PL12, PL21, PL22as well as upper plugs PU11, PU12, PU21, PU22.

FIGS. 21A,21B,21C,21D show cross-sectional views of the memory structure shown inFIG. 20through the cross-sections XA-XA, XB-XB, XC-XC and XD-XD, respectively. The dashed lines are not part of the cross-section but show background components. For example,FIG. 21Ashows the memory structure inFIG. 20through cross-section XA-XA which goes through the conductive plugs PL11and PL21(while plugs PU11, PU21and memory strip MSU1are shown in the background).FIG. 21Bshows the memory structure inFIG. 20through the cross-section XB-XB which goes through the plugs PU11, PU21(while plugs PL12, PL22and memory strip MSL2are shown as background).FIG. 21Cshows the memory structure ofFIG. 20through the cross-section XC-XC which goes through the plugs PL12, PL22(while plugs PU12, PU22are shown as background). Likewise,FIG. 21Dshows the memory structure ofFIG. 20through the cross-section XD-XD which goes through the plugs PU12, PU22.

The lower memory strips MSL1and MSL2in combination with the four lower conductive plugs PL11, PL12, PL21and PL22form four lower memory elements ML11, ML12, ML21and ML22, respectively. Referring toFIG. 21A, portions of lower column line CL1and lower conductive plug PL11serve as a top and bottom electrical contacts (also referred to as electrodes), respectively, for the memory element ML11. Likewise, portions of lower column line CL1and lower conductive plug PL21serve as a top and bottom electrical contacts, respectively, for the lower memory element ML21. Referring toFIG. 21C, portions of lower column line CL2and lower conductive plug PL12serve as a top and bottom electrical contacts, respectively, for the lower memory element ML12. Portions of lower column line CL2and lower conductive plug PL22serve as a top and bottom electrical contacts, respectively, for the memory element ML22. Lower memory elements ML11, ML12, ML21and ML22are phase-change memory elements comprising phase-change material310.

The upper memory strips MSU1and MSU2in combination with the four upper conductive plugs PU11, PU12, PU21and PU22form four upper memory elements MU11, MU12, MU21and MU22, respectively. Referring toFIG. 21B, portions of upper column line CU1and upper conductive plug PU11serve as a top and bottom electrodes, respectively, for the memory element MU11. Electrodes may also be referred to as electrical contacts. Portions of upper column line CU1and upper conductive plug PU21serve as a top and bottom electrodes, respectively, for the upper memory element MU21. Referring toFIG. 21D, portions of upper column line CU2and upper conductive plug PU12serve as a top and bottom electrodes, respectively, for the upper memory element MU12. Portions of upper column line CU2and upper conductive plug PU22serve as a top and bottom electrodes, respectively, for the memory element MU22. Upper memory elements MU11, MU12, MU21and MU22are phase-change memory elements comprising phase-change material410.

FIG. 22is a schematic diagram of the three-dimensional memory array fromFIGS. 18 and 20. Referring toFIG. 22, it is seen that each of the diodes is electrically coupled in series with a corresponding memory element to form a corresponding memory cell. Each of the lower diodes is electrically coupled to a corresponding lower memory element. Diode DL11is electrically coupled in series with memory element ML11by conductive plug PL11between row line RL1and column line CL1. Diode DL12is electrically coupled in series with memory element ML12by conductive plug PL12between row line RL1and column line CL2. Diode DL21is electrically coupled in series with memory element ML21by conductive plug PL21between row line RL2and column line CL1. Diode DL22is electrically coupled in series with memory element ML22by conductive plug PL22between row line RL2and column line CL2.

Likewise, the upper diodes are electrically coupled to corresponding upper memory elements. Diode DU11is electrically coupled in series with memory element MU11by conductive plug PL11between row line RU1and column line CU1. Diode DU12is electrically coupled in series with memory element MU12by conductive plug PU12between row line RU1and column line CU2. Diode DU21is electrically coupled in series with memory element MU21by conductive plug PU21between row line RU2and column line CU1. Diode DU22is electrically coupled in series with memory element MU22by conductive plug PU22between row line RU2and column line CU2.

FIG. 22shows that the three-dimensional memory array comprises four device levels. The first device level Device Level1includes the four lower diodes DL11, DL12, DL21and DL22. The second device level Device Level2includes the four upper diodes DU11, DU12, DU21and DU22. The third device level Device Level3includes the four lower memory elements ML11, ML12, ML21and ML22. The fourth device level Device Level4includes the four upper memory elements MU11, MU12, MU21and MU22. Each of the device levels is formed above the preceding device level. That is, Device Level2is formed above Device Level1, Device Level3is formed above Device Level2, and Device Level4is formed above Device Level3. In one embodiment of the invention, each device level of elements is arranged in a horizontally disposed layer above the substrate. Preferably, there is some vertical distance separating each device level from the adjacent device level.

Referring again to the cross-sectional views ofFIG. 19A through 19D(and, more specifically toFIGS. 19A and 19B), it is seen that the upper diode strips DSU1, DSU2are disposed above the lower diode strips DSL1, DSL2and separated from the lower diodes strips DSL1, DSL2by a distance dZ1in the Z-direction. The distance dZ1is equal to the thickness of the dielectric layer portion150b.

It is preferable that the thickness of the dielectric layer portion150bis greater than 0 (so that the distance dZ1is also greater than 0). It is possible that the thickness of the dielectric layer portion150bbe small or relatively thin.

FIGS. 19A-Dalso show that, it is seen that the lower memory strips MSL1, MSL2are disposed above the upper diode strips DSU1, DSU2and separated from the upper diode strips by a distance dZ2in the Z-direction. The distance is equal to the thickness of the dielectric layer portion250b. The distance dZ2is preferably greater than 0 so that the dielectric layer portion250bhas some thickness, however, it is possible that dZ2be relatively small such that the thickness of the of the dielectric layer portion250bis relatively thin.

It is also seen that the upper memory strips MSU1, MSU2are disposed above the lower memory strips MSL1, MSL2and separated from the lower memory strips by a distance dZ3in the Z-direction. The distance dZ3is equal to the thickness of the dielectric layer portion350b. The distance dZ3is preferably greater than 0 so that the dielectric layer portion350bhas some thickness. However, it is possible that dZ3be relatively small such that the thickness of the dielectric layer portion350bis relatively thin.

FIG. 23Ashows a top view of the memory array structure fromFIG. 20.FIG. 23Ashows the lower diode strips DSL1, DSL2(and the corresponding lower row lines RL1, RL2), the upper diode strips DSU1, DSU2(and the corresponding upper row lines RU1, RU2), the lower memory strips MSL1, MSL2(and the corresponding lower column lines CL1, CL2), the upper memory strips MSU1, MSU2(and the corresponding upper column lines CU1, CU2), lower plugs PL11, PL12, PL21, PL22and upper plugs PU11, PU12, PU21, PU22.FIG. 23Aalso shows the locations of the lower diodes DL11, DL12, DL21and DL22as well as the locations of the upper diodes DU11, DU12, DU21and DU22.

Referring toFIG. 23Aas well asFIGS. 19A-Dit is seen that the upper row lines RU1, RU2are separated from the lower row lines RL1, RL2in the Y-direction by the distance dY1. Likewise, the upper diode strips DSU1, DSU2are laterally separated from the lower diodes strips DSL1, DSL2in the Y-direction by a distance dY1.

Also, the upper column lines CU1, CU2are separated from the lower column lines CL1, CL2in the X-direction by the distance dX1. Likewise, the upper memory strips MSU1, MSU2are separated from the lower memory strips MSL1, MSL2in the X-direction by a distance dX1. In addition, each upper diode DU11, DU21, DU12, DU22is separated from its closest neighboring lower diodes DL11, DL21, DL12, DL22by a distance dX1in the X-direction and a distance dY1in the Y-direction.

In the embodiment shown in FIGS.23A and19A-D, dY1is greater than 0. In this case, there is separation (and no overlap) between the upper row lines RU1, RU2and lower row lines RL1, RL2. Likewise, there is separation (and no overlap) between the upper diode strips and the lower diode strips. In the embodiment of FIGS.23A and19A-D, dX1is also greater than 0. In this case, there is separation (and no overlap) between the upper column lines CU1, CU2and the lower column lines CL2, CL2. Likewise, there is also separation (and no overlap) between the upper memory strips DSU1, DSU2and lower memory strips DSL1, DSL2.

However, in other embodiments of the invention it is possible that the distances dX1and/or dY1be equal to 0. Also, in still further embodiments of the invention, it is possible that dX1and/or dY1be less than 0. If dY1is less than 0, then the upper row lines overlap the lower row lines (and the corresponding upper diode strips overlap the lower diode strips). If dX1is less than 0, then the upper column lines overlap the lower column lines (and the upper memory strips overlap the lower memory strips).

FIG. 23Bshows an embodiment of the invention where dY1is less than 0 and dX1is greater than 0. In this embodiment, the upper row lines overlap the lower tow lines (and the corresponding upper diode strips overlap the corresponding lower diode strips). Another embodiment of the invention is shown inFIG. 23Cwhere dY1is greater than 0 and dX1is less than 0. In this case, the upper column lines overlap the lower column lines (and the corresponding upper memory strips overlap the corresponding lower memory strips).

Another embodiment of the invention is shown inFIG. 23Dwhere both dX1is less than 0 and dY1is less than 0. In this case, the upper row lines overlap the lower row lines and the upper column lines overlap the lower column lines. Likewise, the upper diode strips overlap the lower diode strips and the upper memory strips overlap the lower memory strips. In addition, when both dX1is less than 0 and dY1is less than 0, then the upper diodes overlap the lower diodes.

FIGS.19A′ and19B′ shows cross-sections of the memory array through the cross-sections XA-XA and XB-XB, respectively when dY1is less than 0 and the upper and lower row lines overlap (and the corresponding upper and lower diode strips overlap). Referring to FIG.19A′, it is seen how upper diode strip DSU1overlaps lower diode strip DSL1and also overlaps lower diode strip DSL2. It is also seen how upper diode strip DSU2overlaps lower diode strip DSL2. Likewise, FIGS.19C′ and19D′ show cross-sectional views of the memory array through the cross-section YA-YA, YB-YB, respectively when dX1is less than 0 and the upper and lower column lines overlap (and the corresponding upper and lower memory strips-overlap).

It is noted that the upper and lower row lines may overlap provided that the upper row lines do not contact the conductive plug material266. Likewise, the upper and lower column lines may overlap provided that the lower column lines do not contact the conductive plug material366. Overlap of the row lines and/or the column lines may be used to further increase the density of the memory array.

In all of the embodiments shown in the top view ofFIGS. 23A-D(as well as cross-sectional views ofFIGS. 19A-Dand the cross-sectional views of FIGS.19A′-D′) the upper row lines and lower row lines are staggered in the Y-direction. The upper and lower row lines alternate such that a lower row line (e.g. RL1) is followed by an upper row line (e.g. RU1), and an upper row line (e.g. RU1) is following by a lower row line (e.g. RL2).

Also, the upper column lines and lower column lines are staggered in the X-direction. The upper and lower column lines alternate such that a lower column line (e.g. CL1) is followed by an upper column line (e.g. CU1), and an upper column line (e.g. CU1) is following by a lower column line (e.g. CL2). Hence, a staggered arrangement of the row lines may be achieved with or without overlap. Likewise, a staggered arrangement of the column lines may be achieved with or without overlap.

In the embodiments shown inFIG. 23A-D, the footprints (e.g. projections onto the substrate) of the lower diodes form a checkerboard configuration with the footprints of the upper diodes. This checkerboard configuration may be achieved with or without overlap between the upper and lower diodes. In the embodiments shown inFIGS. 23A-D, the lower diodes DL11, DL12, DL21, DL22are arranged in rows and columns. Likewise, the upper diodes DU11, DU12, DU21, DU22are also arranged in rows and columns. The upper diodes are staggered with respect to the lower diodes. Also, the upper diodes are staggered diagonally with respect to the lower diodes. The upper diodes alternate with the lower diodes along diagonals. For example, the lower diode DL11is followed by the upper diode DU11. The upper diode DU11is followed by a lower diode DL22. The lower diode DL22is followed by the upper diode DU22.

Likewise, in the embodiments shown inFIGS. 23A-D, the upper memory elements may be staggered with respect to the lower memory elements. Likewise, in the embodiments shown inFIGS. 23A-D, the upper memory elements may alternate with the lower memory elements along the diagonals. The lower memory elements may be diagonally staggered with respect to the upper memory elements.

In the embodiment of the invention shown inFIGS. 23A-D, the lower row lines RL1, RL2and the upper row lines RU1, RU2each have a width WYin the Y-direction (likewise, the corresponding lower diode strips and the upper diode strips each have a width WYin the Y-direction. Also, the lower column lines CL1, CL2and the upper column lines CU1, CU2each have a width WXthe X-direction (likewise, the corresponding lower memory strips and upper memory strips each have a width WXin the X-direction). The lower and upper diodes have a lateral dimension WXin the X-direction and a lateral dimension WYin the Y-direction. The dimension WXas well as the dimension WYmay be the same dimension W. In an embodiment of the invention, the dimension W may be around ( 5/3)F. It is noted that in general, the dimensions (e.g., widths, lengths, heights, thicknesses) of each of the row lines, column lines, diode strips, memory strips, diodes and memory elements is not limited to any particular dimension. In an embodiment of the invention, it is even possible that the widths of two or more column lines (or two or more row lines) are different.

FIG. 25Ashows a top view of the three-dimensional memory array fromFIG. 23A.FIG. 25Ashows a top view of a unit volume1010of the three-dimensional array. The unit volume includes two memory cells. The unit volume1010has a lateral dimension in the X-direction of 2WX+2dX1. The unit volume1010has a lateral dimension in the Y-direction of 2WY+2dY1. Since the unit volume includes two memory cells, the cell size is one-half the size of the footprint of the unit volume.
dX1>0 and dY1>0  Case 1
(separation in both the X-direction and Y-direction)
In this case,

footprint size is 4(WX+dX1)(WY+dY1), and

cell size is 2(WX+dX1)(WY+dY1)

It is seen that even though dX1>0 and dY1>0, the cell size of the three-dimensional array may be made less than 4(WX) (WY) by appropriately choosing the values of dX1and dY1(e.g. making them small enough). Likewise, the cell size of the three-dimensional array may be made less than 3(WX) (WY) by choosing the appropriate values of dX1and dY1.
dX1=dY1=0  Case 2
In this case,

footprint size is 4(WX) (WY), and

footprint size is less than 4(WX) (WY), and

cell size is less than 2(WX) (WY)

An example of a two-dimensional array is shown inFIG. 25B. In this example, there are only two row lines R1, R2and only two column lines C1, C2. Each of the row lines may also have a width WYin the Y-dimension and each of the column lines may also have a width WXin the X-dimension. There is also a space of width WXbetween each of the column lines and a space of width WYbetween each of the row lines.FIG. 25Bshows the unit volume1020of the two-dimensional array. The unit volume includes a single memory cell and has a lateral dimension in the X-direction of 2WXand a lateral dimension in the Y-direction of 2WY. The total footprint area of the unit volume1020is 4(WX) (WY). Since, the unit volume1020includes only a single memory cell, the cell size of the array is also 4(WX) (WY). In an embodiment of the invention, WX=WY=W which may be about ( 5/3)F.

Hence, it is seen that the three-dimensional memory array of the present invention may have memory cell size which is less than the memory cell size of a two-dimensional array. This is an advantage of the three-dimensional memory array.

Another advantage of the three-dimensional memory array is that since the memory cells need not contact the substrate, the substrate is available for use other than for defining the memory cells. In one embodiment of the present invention, the area in the substrate may be used for at least portions of the row decoders, column decoders, I/O multiplexors, and read/write circuits. This helps to minimize the fraction of the die surface area not devoted to memory cells.

In the embodiments of the memory array shown inFIGS. 23A-D, there are two lower row lines RL1, RL2and two upper row lines RU1, RU2. In other embodiments of the invention, the memory array may include more than two lower row lines and more than two upper row lines. More generally, the memory array of the present invention may include at least one lower row line and at least one upper row line.

Likewise, in the embodiments of the memory array shown inFIGS. 23A-D, there are two lower column lines CL1, CL2and two upper row lines CU1, CU2. In other embodiments of the invention, the memory array may include more than two lower column lines and more than two upper column lines. More generally, the memory array of the present invention may include at least one lower column line and at least one upper column line.

In an embodiment of the invention, a lower memory cell may be electrically coupled between each of the lower row lines and each of the lower column lines. Likewise, an upper memory cell may be electrically coupled between each of the upper row lines and each of the upper column lines. Each lower memory cell includes a lower phase-change memory element in series with a lower diode. Each upper memory cell includes an upper phase-change memory element in series with an upper diode. It is possible that upper and lower diodes be replaced with other types of isolation elements. In an embodiment, there may be at least one upper memory cell. In an embodiment, there may be a plurality of upper memory cells. In an embodiment, there may be at least one lower memory cell. In an embodiment, there may be a plurality of lower memory cells.

Referring again toFIGS. 3 and 7, it is noted that the conductive lines110a,110band210a,210bwere designated as the row lines for the memory array while the conductive lines312a,312band412a,412bwere all designated as the column lines for the memory array. In an alternate embodiment of the invention, it is possible that the conductive lines110a,110band210a,210bmay be designated as the columns lines for the memory array while the conductive lines312a,312band412a,412bmay be designated as the row lines for the array.

In addition, in the embodiments shown inFIG. 7, the conductive lines312a,312band412a,412bare perpendicular to the conductive lines110a,110band210a,210b. However, in other embodiments of the invention, they may not be perpendicular. Instead they may merely cross each other at some angle.

Referring toFIG. 2, in an alternate embodiment of the invention, layer112may be formed of a p+ type material, layer114may be formed of a p type material and layer116may be formed of an n+ type material. Likewise, referring toFIG. 6, layer212may be formed of a p+ type material, layer214may be formed of a p type material and layer216may be formed of an n+ type material.

In one or more other embodiments of the invention, the lower diodes and upper diodes may be formed in other ways. In addition, the lower diodes and upper diodes may be replaced with other types of isolation devices. For example, other types of isolation devices include, without limitation, transistors and threshold switches (such as chalcogenide threshold switches and S-type threshold switches).

It is noted that one or more additional conductive layers may placed between the phase-change material and the conductive plugs to form other types and structure for the bottom electrodes of the memory elements. Likewise, one or more additional conductive layers may be placed between the phase-change material and the column lines CL1, CL2, CU1and CU2to form other types and structure for the top electrodes of the memory elements.FIG. 24shows the use of a lower electrode700formed by placing a conductive material within a smaller opening660defined by dielectric sidewall spacer600. The material is planarized to form a smaller plug. The electrode700provides for a smaller area of contact with the phase-change material than that provided by the plug PL11.

Examples of materials which may be used as the dielectric layers150,250,350and500include oxides and nitrides. Examples of oxides include silicon oxide. Examples of nitrides include silicon nitride.

The memory material may be a phase-change material. The phase-change materials may be any phase-change memory material known in the art. The phase-change materials may be capable of exhibiting a first order phase transition. Examples of materials are described in U.S. Pat. Nos. 5,166,758, 5,296,716, 5,414,271, 5,359,205, 5,341,328, 5,536,947, 5,534,712, 5,687,112, and 5,825,046 the disclosures of which are all incorporated by reference herein.

The phase-change materials may be formed from a plurality of atomic elements. Preferably, the memory material includes at least one chalcogen element. Hence, the phase-change material may be a chalcogenide material. The chalcogen element may be chosen from the group consisting of Te, Se, S and mixtures or alloys thereof. The memory material may further include at least one element selected from the group consisting of Ge, Sb, Bi, Pb, Sn, As, S, Si, P, O, and mixtures or alloys thereof. In one embodiment, the memory material comprises the elements Te, Ge and Sb. In another embodiment, the memory material consists essentially of Ge, Sb and Te. An example of a memory material which may be used is Ge2Sb2Te5.

The memory material may include at least one transition metal element. The term “transition metal” as used herein includes elements21to30,39to48,57and72to80. Preferably, the one or more transition metal elements are selected from the group consisting of Cr, Fe, Ni, Nb, Pd, Pt, Co, Ti and mixtures or alloys thereof. The memory materials which include transition metals may be elementally modified forms of the memory materials in the Te—Ge—Sb ternary system. This elemental modification may be achieved by the incorporation of transition metals into the basic Te—Ge—Sb ternary system, with or without an additional chalcogen element, such as Se.

It is to be understood that the disclosure set forth herein is presented in the form of detailed embodiments described for the purpose of making a full and complete disclosure of the present invention, and that such details are not to be interpreted as limiting the true scope of this invention as set forth and defined in the appended claims.