Control of a power transistor with a drive circuit

A system includes a first transistor having a first control input and first and second current terminals. The first current terminal couples to an input voltage node. A second transistor has a second control input and third and fourth current terminals. The third current terminal couples to the second current terminal at a first node. The fourth current terminal couples to an output voltage node. A drive circuit is configured to charge a capacitor maintain the first transistor in an off state responsive to a negative voltage on the input voltage node, and, responsive to a negative voltage on the input voltage node, to cause the charge from the capacitor to be used to turn off the first transistor. The system provides a voltage to a load coupled to the output voltage node.

CROSS-REFERENCE TO RELATIONED APPLICATIONS

This application claims priority to India Provisional Application Nos. 201841025235 and 201841025248, filed Jul. 6, 2018, which is hereby incorporated by reference.

BACKGROUND

In some applications (e.g., industrial applications), an “E-fuse” switch is included in the power path between a power source and a downstream load. The E-fuse switch protects the load against over-voltage and over-current events.

SUMMARY

In one example, a circuit includes a first transistor having a first control input and first and second current terminals. The first current terminal is coupled to an input voltage node. A second transistor has a second control input and third and fourth current terminals. The third current terminal is coupled to the second current terminal at a first node. The fourth current terminal is coupled to an output voltage node. A third transistor has a third control input and fifth and sixth current terminals. The fifth current terminal is coupled to the first control input. The sixth current terminal is coupled to the first current terminal. A comparator has first and second comparator inputs. The first comparator input is coupled to the output voltage node. The second comparator input is coupled to a bias voltage node configured to be biased at a voltage greater than an input voltage on the input voltage node. The comparator has an output configured to control a power state of the third transistor.

DETAILED DESCRIPTION

As described herein, an E-fuse switch protects loads against power supply perturbations. One such perturbation is a large negative voltage transient on the power supply voltage to the E-fuse switch. Large negative voltage transients can occur due to, for example, power surges and reverse polarity events. During large negative voltage transients, reverse current is limited (e.g., stopped) from the output port of the E-fuse switch to its input port. The described E-fuse switch rapidly detects a reverse current or negative input voltage and turns off a solid-state switch contained in the E-fuse switch to thereby protect the load connected thereto.

FIG. 1shows an example of an integrated circuit (IC)100. In one example implementation, IC100is an E-fuse switch. IC100in this example comprises transistors M1and M2and drive circuit110. Transistors M1and M2comprise n-type metal oxide semiconductor field effect transistors (NMOS). The body diode of the transistors M1and M3also are shown. Body diode D1is shown between the source and drain of transistor M1, and body diode D2is shown between the source and drain of transistor M2. Drive circuit110generates control signals112and114for driving the gates of transistors M1and M2, respectively. Drive circuit110controls the gate-to-source voltage (Vgs) of transistor M2to limit current to/from the load as necessary, and operates transistor M1as a switch to turn it off upon detection of a negative VIN. The IC100has an input terminal120configured to receive an input supply voltage (VIN), and an output terminal130to provide an output voltage (VOUT) to a downstream load.

When VIN is provided to the IC100and transistors M1and M2are both on as controlled by the drive circuit110, VOUT is generally equal to VIN. If an anomalous condition (e.g., negative VIN) is detected by drive circuit110, the drive circuit110turns of transistor M1to protect the load. In one example, IC100is rated for an input voltage VIN being between 4 and 36 volts. As such, the output voltage VOUT also is between 4 and 36 volts. In accordance with the described examples, in response to drive circuit110detecting a negative VIN voltage, the drive circuit110turns off transistor M1.

Reference140shows that the substrate of the IC100is grounded. Because the substrate is grounded, the drive circuit110as described herein is operative to turn off transistor M1responsive to a negative input voltage VIN. In some implementations, the IC100can turn off transistor M1with a negative VIN as low as, for example, −60 V. Further, VIN can slew downward at very high rates during some surge events (e.g., during lightning strikes to equipment or buildings containing equipment that includes the IC100) and the disclosed drive circuit110is configured to provide fast detection to VIN falling below larger negative voltages, such that the disclosed drive circuit110may turn off transistor M1to avoid the gate-to-drain capacitance (Cgd) and gate-to-source capacitance (Cgs) of transistors M1and M2from creating a high shoot-through current path through the transistors, which could damage the transistors. A shoot-through current path can be created by voltage division caused by the transistor's parasitic capacitances if VIN were to slew at a high rate. The disclosed drive circuit110also is configured to provide a relatively high drive strength to turn off transistor M1rapidly. In one example, if the slew rate of VIN is 60 V/microsecond, and Cgd of transistor M1is 1 nF, then the gate current will be equal to Cgd*dv/dt=60 mA. The pull-down resistance on the gate of transistor M1should be small enough to avoid creating so large of a gate voltage that transistor M1will not turn off. In this example, a drive strength for the gate of transistor M1of 5 ohms or less would be sufficient. Further, situations may occur in which no active input voltage VIN is provided to the input terminal120, but the voltage on the input terminal120is negative anyway (e.g., due to a lightning strike). In such a condition, the drive circuit110advantageously ensures that the current path through transistors M1and M2is continuously off despite not having a positive supply voltage VIN to control the components of the drive circuit110.

FIGS. 2A through 7illustrate at least portions of the drive circuit110andFIG. 8combines the circuits ofFIGS. 2A-7into one complete schematic.FIG. 2Ashows an example gate control circuit200. The example gate control circuit200comprises transistor M1as well as transistors M3and M4, resistors R1and R2, and current source device I1. Transistor M3in this example comprises an NMOS device and transistor M4comprises a drain-extended p-type metal oxide semiconductor field effect transistor (PMOS). The drain of transistor M3connects to the gate of transistor M1and to current source I1. The source of transistor M3connects to the source of transistor M1, and to the drain of transistor M4to receive VIN. Resistors R1and R2are connected in series between an N-doped buried layer202of transistor M3and ground.FIG. 2Bshows a cross-section of transistor M3. The N-doped buried layer (NBL)250is shown formed on a P-doped substrate260(M3's source). Because the substrate260is P-doped and the NBL is N-doped, a parasitic diode255is formed. The connection point between resistors R1and R2is labeled node N3and is connected to the gate of transistor M4. The N-doped buried layer202and resistor R1are also connected to the source of transistor M4(node N2). The voltage on the N-doped buried layer202should not become negative because otherwise the parasitic diode255will turn on and conduct current.FIG. 2Balso shows an epitaxial (epi) layer270. The epi layer270is p-doped in this example and is a local substrate to transistor M3. The epi layer270can be connected to ground or to the source of transistor M3.

During normal operation, transistor M1is on and the positive input voltage VIN is provided through transistor M1onto node N1. As the drain and source of transistor M3are connected across the gate and source of transistor M1, turning on transistor M3forces the Vgs of transistor M1to be approximately 0V and thus less than the threshold voltage of transistor M1, thereby turning off transistor M1. With transistor M3off, transistor M1is caused to be on due to current from current source I1. Advantageously, gate control circuit200turns off transistor M1responsive, as explained below, to VIN being a negative voltage.

Transistor M4and resistors R1and R2protect internal circuits of the IC100from VIN in the situation in which VIN is a negative voltage. When VIN is positive, the body diode of transistor M4brings the voltage on node N2to a positive voltage within one diode voltage drop of VIN. The series-connected resistors R1and R2provide a voltage on node N3that is lower than the voltage on node N2. Node N3is connected to the gate of transistor M4, and thus the Vgs of transistor M4is sufficient to turn on transistor M4when VIN is positive. When VIN is negative, the body diode of transistor M4is reverse biased and the voltage on node N2is zero, which in turn forces off transistor M4thereby protecting internal circuits from a negative VIN.

FIG. 3shows an example of a negative input voltage detection circuit300for driving the gate of transistor M3. Transistor M3is shown in bothFIGS. 2 and 3. The example negative input voltage detection circuit300shown inFIG. 3includes a comparator302, a bias voltage source304, transistors M4and M5, and resistor R3. Resistor R3is connected between the gate and source of transistor M3. Transistor M5is a PMOS transistor whose drain is connected to resistor R3and whose source is connected to an internally-generated supply voltage labeled DRVR_VDD (described below). The internally-generated supply voltage DRVR_VDD operates comparator302. The negative input of the comparator302receives the output voltage VOUT and the positive input to comparator302receives the input voltage VIN plus the bias voltage from bias voltage source304. The voltage of the bias voltage source304is relatively low and just needs to be large enough to determine accurately whether VIN is less than VOUT, which would happen if VIN becomes negative (VOUT does not fall below 0V). In one example, the voltage of bias voltage source304is 15 mV.

Under normal conditions (when VIN is positive), VOUT equals VIN, and due to the voltage of bias voltage source304, the positive input to comparator302is larger than VOUT on the negative input to comparator302. As such, the output of the comparator is high thereby turning off transistor M5. With transistor M5off, no current flows through resistor R3, and thus the Vgs of transistor M3is zero thereby maintaining transistor M3in an off condition (and transistor M1on). If the input voltage VIN becomes negative, the output of comparator302will be low enough to turn on transistor M5which causes current to flow from the internally-generated supply voltage node DRVR_VDD, through transistor M5and resistor R3, thereby generating a sufficiently large Vgs for transistor M3to turn. As explained above, turning on transistor M3causes transistor M1to turn off. Advantageously, negative input voltage detection circuit300causes transistor M3to turn on responsive VIN being negative.

The input voltage VIN can slew downward at a relatively high rate during a surge event. As such, transistor M1should be turned off quickly to avoid damage to internal components of the IC100and the load.FIG. 4shows an example charge storage circuit400including a charge pump410to maintain a capacitor C1in a charged state. The charge on the capacitor C1can be used to drive the voltage rail DRVR_VDD to power the comparator302ofFIG. 3and turn on transistor M5despite VIN rapidly falling to negative voltage levels.

The example charge storage circuit400includes transistors M7and M8(both NMOS transistors in this example), current source devices I2and I3, capacitor C1, resistor R4, bias voltage generator412, and a charge pump410. The source of transistor M4is connected to one input of charge pump410and to bias voltage generator412. The bias voltage generator412generates a bias voltage413using the input voltage VIN and provides the bias voltage413to the charge pump410. The output of charge pump410provides voltage to the voltage rail VCP, which connects to current source device is I2and I3. The drain of transistor M7is connected to the current source device I2, and the drain of transistor M8is connected to current source device I3. The gates of transistors M7and M8are connected together and to the drain of transistor M8. The source of transistor M7is connected to one plate of capacitor C1, and the source of transistor M8is connected to resistor R4. The other terminals of capacitor C1and R4are connected together and to the source of transistor M4, the bias voltage generator412, and charge pump410. The voltage rail DRVR_VDD is taken from the node interconnecting the source of transistor and M7and capacitor C1as shown.

The function of negative input voltage detection circuit300inFIG. 3is to turn on transistor M3and to do so rapidly. To turn on transistor M3rapidly, a sufficient amount of charge should be transferred to the gate of transistor M3. Advantageously, the charge storage circuit400inFIG. 4is operative to charge capacitor C1when VIN is positive, and then to transfer the charge from capacitor C1via the DRVR_VDD internally-generated supply rail to the source of transistor M5inFIG. 3to thereby provide significant drive current to transistor M3to turn on transistor M3quickly. In one example, charge pump410generates a voltage on supply rail VCP that is 12V higher than VIN. Based on the size of resistor R4, a voltage is developed across resistor R4that is, in one example, 5 V. Transistors M7and M8form a current mirror, and as a result, a similar voltage (e.g. 5 V) is formed across capacitor C1. As such, the internally-generated supply voltage rail DRVR_VDD is, in one example, 5 V, and charge from capacitor C1can be quickly delivered to the gate of transistor M3to turn on transistor M3when needed. The capacitance of capacitor C1is large enough to provide sufficient charge to charge the gate of transistor M3to turn it on quickly. In one example, C1is a 150 pF capacitor.

The charge storage circuit400ofFIG. 4is operative to pre-charge capacitor C1when a positive input voltage VN is present. However, it is also possible that a positive input voltage VIN has not yet been provided to the IC100. If a positive input voltage has not yet been provided to IC100, then it would not be possible to have capacitor C1in a pre-charged state. During such a condition (capacitor C1is not pre-charged), it is also possible to have a negative voltage surge event in which VIN is forced to lower and lower negative voltages.

FIG. 5shows an example of a negative voltage circuit500that is operative to turn on transistor M3thereby turning off transistor M1when VIN was not positive in the first place to have pre-charged capacitor C1. In the example ofFIG. 5, negative voltage circuit500comprises resistors R3, R4, and R5, diode D3, and transistors M9, M10, M11, and M12. Transistors M9-M12comprise PMOS transistors in this example. Transistors M9and M10are coupled together to form one current mirror, and transistors M11and M12are coupled together to form another current mirror. Resistor R3connects between the gate of transistor M3and VIN. The anode of diode D3is connected to node N1, and the cathode of diode D3is connected to the sources of transistors M11and M12. The gates of transistors M11and M12are connected together as well as to the drain of transistor M12. The drain of transistor M12also connects to resistor R5, and the other terminal of resistor R5connects to the source of transistor M4. The drain of transistor M11connects to the sources of transistors M9and M10. The gates of transistors M9and M10are connected together and to the drain of transistor M9. The drain of transistor M9is also connected to resistor R4, and the other terminal of resistor R4is connected to the drain of M4and to resistor R3at node N4.

A load circuit will often have either or both of a load capacitor or a combination of a diode and a resistor connected between VOUT and ground. As a result, VOUT will not fall below zero. This means that if there is no input voltage VN, VOUT will be 0 V, and if VIN happens to become negative, VOUT will remain at 0V. Due to the output capacitor associated with the load, however, VOUT could be slightly positive even if there is no input voltage VIN. If VOUT is 0 V or slightly positive, the voltage on node N1will also be 0V (or slightly positive) when M2is on. If VIN becomes a negative voltage, the voltage on node N4will be negative because node N4is at the same potential as VIN. Thus, a positive voltage will be present on node N1relative to node N4. This positive voltage (illustrated inFIG. 5as VN14) can be used to produce a current through the diode D3, transistor M11, and transistors M9and resistor R4to node N4. The current through transistor M9is controlled, at least in part, by the resistance of resistor R4. The current mirror ratio between transistors M9and M10is 1:1 (but can be other than 1:1), and thus the current through transistor M10is equal to the current through transistor M9. The current through transistor M9flows through resistor R3to node4. Resistor R3is connected between the gate and source of transistor M3, and thus any voltage that is developed across resistor R3is the Vgs of transistor M3. The resistance values for resistors R3and R4are chosen such that the resulting voltage developed across resistor R3(the Vgs of transistor M3) is sufficiently high to exceed the threshold voltage of transistor M3. As a result, when VIN becomes negative, even if capacitor C1was never charged, transistor M3can still be turned on to thereby turn off transistor M1. Advantageously, negative voltage circuit500is operative to turn on transistor M3when VIN is negative even if capacitor C1was not able to be charged.

FIG. 6shows a circuit similar to that ofFIG. 5, but includes an additional parasitic control circuit600. Parasitic control circuit600is connected to the ground node and is operative to also try to force a current through transistor M9to turn on transistor M3. Parasitic control circuit600includes a diode D4, resistor R6, and transistors M13, M14, and M15. The anode of diode D4is connected to the ground node, and the cathode of the diode D4is connected to the drain of transistor M13and the gates of transistors M13and M14. The sources of transistors M13and M14are connected together and to the drain of transistor M9. The drain of transistor M15also is connected to ground and to the anode of diode D4. Resistor R6is connected between the source and gate of transistor M15, as well as to the drain of transistor M14.

If VIN becomes negative, the body diode of transistor M15turns on, and a voltage one diode voltage drop below ground is imposed on the sources of transistors M9and M10. Circuit600senses the drain-to-source voltage (Vds) of transistor M9, and by causing current to flow through transistor M9also causes a current to flow into resistor R3. Transistors M9and M10have PNP parasitics, as illustrated at601. The N-doped buried layers of transistors M9and M10are represented by602and are connected to the drain of transistor M15. The P-doped drains of transistors M9and M10are represented by603. Reference numeral604represents the P-doped substrate of transistor M9and M10. If the sources of transistors M9and M10fall below −0.7 V, the PNP parasitics (601) of the transistors will start to conduct current possibly leading to an uncontrolled current injection into the gate of transistor M3, which could then lead to a voltage on the gate of transistor M3sufficiently high to destroy the gate oxide of that transistor. Advantageously, parasitic control circuit600ensures that the PNP diode parasitics of transistors M9and M10do not turn on. Turning on the PNP parasitics of M9and M10could lead to uncontrolled current injection into resistor R3, which would lead to a high gate voltage on the gate of the transistor M3and destroy the gate of oxide of transistor M3.

FIG. 7shows a modification to the negative voltage circuit500circuit ofFIG. 5. The modification includes resistor R7and capacitors C2and C3. Resistor R7degenerates the source of transistor M11to cause transistor M11to provide a prescribed amount of current. The current into resistor R3is the minimum of the drain current through transistor M11and the drain current through transistor M9. If the drain current through transistor M9is smaller than the drain current through transistor M11, the smaller drain current through transistor M9is the current that flows into resistor R3. The voltage on the source of transistor M9is increased as a result to limit the VDS of transistor M11. Capacitor C2is connected in parallel across resistor R4, and capacitor C3is connected in parallel across resistor R5. The resistors R4and R5are thus shunted by their respective capacitors in the event of a fast transient. In one example, resistor R3, R4, and R5have resistances of 133 kilo-ohms, 6 megaohms, and 4 mega-ohms, respectively. Advantageously, the modified negative voltage circuit ofFIG. 7is operative to turn on transistor M3when VIN is negative even if capacitor C1was not able to be charged.

FIG. 8shows a drive circuit800comprising several features of the circuits ofFIGS. 2-7in one schematic. As such, a description of the components shown inFIG. 8is not repeated here. The bias voltage source304ofFIG. 3is shown in the example circuit ofFIG. 8as a current source device I4connected to resistor R8. A fixed current from the current source device I4causes a voltage to be generated across resistor R8. The voltage across resistor R8represents the bias voltage provided to the positive input of the comparator302. The drive circuit800ifFIG. 8advantageously turns off transistor M1responsive at least to VIN being a negative voltage.

FIG. 9provides an example timing diagram illustrating the operation of the circuit ofFIG. 8. The waveforms shown inFIG. 9include VIN, the gate voltage of transistor M3, the gate voltage of transistor M5, the Vgs of M1, and the drain current through transistor M11, I(M11). At910, VIN is above 0 (e.g., positive 24 V), and VOUT is equal to VIN. The gate voltage of transistor M5is high because the positive input to comparator302is larger than the negative input to comparator302. With the M5gate voltage being high, M5(which is a PMOS device) will be off, and thus the gate of transistor M3will be low and transistor M3will be off as well. With transistor M3off, the Vgs of transistor M1will be high enough to keep transistor M1on.

FIG. 9illustrates the reaction to the circuit when VIN drops quickly, as shown at915. A sudden drop in VIN may result in VIN being lower than VOUT, which does not drop as quickly. The difference in the voltages of VIN and VOUT causes the output of comparator to become low (925) thereby causing transistor M5to turn on. With transistor M5on, current flows through resistor R3, thereby developing a sufficiently large gate voltage (920) across transistor M3to turn on transistor M3. With transistor M3on, the Vgs of transistor M1becomes low thereby turning off transistor M1at930. Current I(M11) represents the drain current through transistor M11, and the current through resistor R3as explained above. When VIN drops rapidly, I(M11) increases rapidly as shown at940thereby rapidly turning on transistor M3before I(M11) settles at its DC value at942.

As noted above, while VOUT does not drop below 0V, it is possible that VIN becomes negative. In fact, VIN could have a large negative voltage (e.g., −60V). VOUT, in one example, could be 36V. If VOUT is 36V and VIN suddenly falls to −60V, VN14inFIG. 5would rapidly become 96V. Transistors M9-M11comprise drain-extended PMOS transistors and, as such, are rated to relatively high Vds voltages, but the rating of Vds is less than 96V. In one example, the maximum Vds of transistors M9-M11is 85V.

FIG. 10shows a modification to the negative voltage circuit500ofFIG. 5to ensure that the Vds of transistors M9-M11do not exceed the maximum Vds rating of the transistors. The circuit example ofFIG. 10includes a voltage clamp circuit1000to control the gates of M9/M10to distribute the VN14voltage across M11and M9/M10so that M11does not have a Vds larger than its rated value, and similarly neither M9nor M10have a Vds larger than their rated values.

Voltage clamp circuit1000includes transistors M16, M17, and M18, resistor R9, and Zener diodes Z1and Z2. In this example, transistor M16is a PMOS transistor, and transistors M17and M18are NMOS transistors. The source of transistor M16is connected to the sources of transistors M11and M12, and the drain of transistor M16is connected to the drains and gates of transistors M17and M18. The source of transistor M17is connected to the anode of Zener diode Z2, and the anode of Zener diode Z2is connected to the gates of transistors M9and M10. The source of transistor M18is connected to resistor R9and to the cathode of Zener diode Z1. Zener diode Z1is connected across resistor R9.

With VOUT being approximately 0V, the voltage on node N1is approximately 0V. If VIN becomes increasingly negative, eventually VIN will be negative enough to turn on Zener diode Z1. Once Zener diode Z1turns on, the voltage across resistor R9is clamped at the breakdown voltage of the Zener diode. The gate voltage for transistors M17and M18will be approximately one threshold voltage (e.g., 1 V) above the breakdown voltage of the Zener diode Z1. A threshold voltage drop will be seen between the gate and source of transistor M17, and thus the voltage on the source of transistor M17will be approximately equal to the voltage on the cathode of Zener diode Z1. Zener diode Z2will be also be on, and thus the voltage on its anode will be approximately 0V due to breakdown voltage drop caused by Zener diode Z1. As such, the voltage on the gates of transistors M9and M10will be approximately 0V responsive to VIN becoming negative enough to turn on Zener diode Z1.

If the voltage on the gates of transistors M9and M10is approximately 0V, then the voltage drop between node N1and the gates of transistors M9and M10will be VOUT. In one example, IC100is rated for a maximum VOUT of 36V, and thus at most VOUT (e.g., 36V) is dropped between the source and drain of transistor M11. The remaining voltage (VN14minus the Vds of transistor M11) is thus dropped across transistors M9and M10. In an example worst case scenario in which VN14is 96V, the maximum voltage between the drains and sources of transistors M9and M10will be 60V, and thus within the maximum Vds rating (85V) of transistors M9and M10. Advantageously, voltage clamp circuit1000clamps the voltage on the gate of transistor M10to adequately distribute the VN14voltage between nodes N1and N4so as not to damage transistors M9, M10, or M11.

FIG. 11shows the circuit ofFIG. 8but including voltage clamp circuit1000. As such, a description of the components shown inFIG. 11is not repeated here.

FIG. 12shows an example system1200in which the IC100can be used. Various external components to the IC100are shown including transistors M1and M3as well as resistors R20, R21, R22, R23, R24, R25, and R26, capacitor C20, and Zener diodes Z20. In this example, IC100includes transistor M2and some or all of the components shown in the preceding schematics (except for transistors M1and M3, which are not provided on the same die as IC100). The drain of transistor M1is connected to the input pin IN, and the VIN is connected directly to the input pint IN_SYS. The B_GATE pin is connected to the gate of transistor M1and the drain of transistor M3. The UVLO input is used to set the programmable under-voltage lockout threshold. The OVP input is used to set the programmable overvoltage protection threshold. VOUT is taken from the output pin OUT. Resistors R23and R24form a voltage divider to divide down VOUT to provide a scaled version of VOUT to the PGTH input for the internal comparator302(FIG. 3). IMON is an output that provides a signal indicative of the current through M2. Resistor R25between ILIM and ground sets the overload and short-circuit current limit. Capacitor C20between dv/dv and ground sets the output voltage slew rate.