Liquid crystal display panel and fabricating method thereof

A liquid crystal display panel including a thin film transistor array substrate structure including, a substrate, a gate line and a data line disposed on the substrate and insulated from each other by a gate insulating pattern, a thin film transistor provided at intersection of the gate and data lines, a protective film disposed to protect the thin film transistor, and a pad structure connected to a respective one of the gate line and data line, the pad structure including a transparent conductive film and a data metal layer; and a color filter array substrate structure joined with the thin film transistor array substrate structure, wherein the protective film is disposed within an area where the color filter array substrate structure overlaps with the thin film transistor array substrate structure, and exposing either the data metal layer or the transparent conductive film along a side portion of the substrate.

This application claims the benefit of Korean Patent Application Nos. 2003-0071392 filed in Korea on Oct. 14, 2003, and 2003-0071394 filed in Korea on Oct. 14, 2003, which are hereby incorporated by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to a liquid crystal display, and more particularly, to a liquid crystal display panel and a fabricating method thereof for reducing the number of mask processes as well as preventing a corrosion of a shorting line.

2. Description of the Related Art

In general, a liquid crystal display (LCD) drives a liquid crystal by an electric field formed between a pixel electrode and a common electrode arranged opposite from each other on upper and lower substrates. The LCD controls the application of the electric field across a liquid crystal, and accordingly light transmittance of the liquid crystal, thereby displaying a desired picture.

The LCD includes a thin film transistor array substrate structure and a color filter array substrate that are joined opposite from each other, a spacer for constantly keeping a cell gap between the two substrates, and a liquid crystal filled in the cell gap. The thin film transistor substrate structure comprises of a plurality of signal wirings and thin film transistors, and an alignment film coated thereon for the aligning the liquid crystal. The color filter array substrate structure is comprised of a color filter for implementing a color, a black matrix for preventing a light leakage, and an alignment film coated thereon for alignment of the liquid crystal.

In such a LCD, the thin film transistor substrate structure has a complicated fabrication process involving a semiconductor process that requires a plurality of mask processes. These processes lead to a significantly increased in the manufacturing cost of the liquid crystal display panel. To solve this, a thin film transistor array substrate structure has been developed with a reduced number of mask processes. Since one mask process can accommodate several processes, such as thin film deposition, cleaning, photolithography, etching, photo-resist stripping, and inspection processes, etc., the total number of mask processes can be reduced. Recently, a four-round mask process, one less mask process from the existent five-round mask process is becoming a standard mask process of the thin film transistor.

FIG. 1is a plan view illustrating a related art lower transistor array substrate adopting a four-round mask process, andFIG. 2is a cross-sectional view of the thin film transistor array substrate structure taken along line II–II′ ofFIG. 1. Referring toFIGS. 1 and 2, the thin film transistor array substrate structure includes a gate line2and a data line4provided on a lower substrate1intersecting each other and having a gate insulating pattern12therebetween. The gate line2is provided to apply a gate signal and the data line4is provided to a data signal at an intersection structure to define a pixel area5. Furthermore, the thin film transistor array substrate includes a thin film transistor30provided at each intersection, a pixel electrode22provided at a cell area defined by an intersection, a gate pad50connected to the gate line2, and a data pad60connected to the data line4.

The thin film transistor30includes a gate electrode6connected to the gate line2, a source electrode8connected to the data line4, and a drain electrode10connected to the pixel electrode22. The thin film transistor30allows a pixel signal on the data line4to be charged and maintained at the pixel electrode22in response to a gate signal from the gate line2. Further, the thin film transistor30includes an active layer14overlapping the gate electrode6having a gate insulating pattern12therebetween to define a channel between the source electrode8and the drain electrode10.

The active layer14also overlaps the data line4and a lower data pad electrode62. On the active layer14, an ohmic contract layer16is provided for making a contact with the data line4, the source electrode8, with the drain electrode10and the lower data pad electrode62. The pixel electrode22is connected to the drain electrode10of the thin film transistor30via a first contact hole20passing through a protective film18and is provided at a pixel area5.

Thus, an electric field is formed between the pixel electrode22to which a pixel signal is supplied via the thin film transistor30and a common electrode (not shown) supplied with a reference voltage. Liquid crystal molecules between the thin film transistor array substrate structure and the color filter array substrate structure rotates due to a dielectric anisotropy induced by such an electric field. Transmittance of a light onto the pixel area5is varied depending upon a rotation extent of the liquid crystal molecules, thereby implementing a gray level scale.

The gate pad50is connected to a gate driver (not shown) to apply a gate signal to the gate line2. The gate pad50consists of a lower gate pad electrode52extended from the gate line2, and an upper gate pad electrode54connected to the lower gate pad electrode52via a second contact hole56passing through the gate insulating pattern12and the protective film18.

The data pad60is connected to a data driver (not shown) to apply a data signal to the data line4. The data pad60comprises a lower data pad electrode62extended from the data line4, and an upper data pad electrode64connected to an upper data pad electrode64connected to the lower data pad electrode62via a third contact hole66passing through the protective film18.

Hereinafter, a method of fabricating the thin film transistor array substrate structure having the above-mentioned structure adopting the four-round mask process will be described in detail with reference toFIG. 3AtoFIG. 3D. Referring toFIG. 3A, a first conductive pattern group including the gate line2, the gate electrode6, and the lower gate pad electrode52are provided on the lower substrate1by the first mask process. More specifically, a gate metal film is formed on the lower substrate1by a deposition technique such as sputtering. Then, the gate metal film is patterned by photolithography and etching process using a first mask to form the first conductive pattern group including the gate line2, the gate electrode6, and the lower gate pad electrode52. The gate metal film is made from an aluminum group metal, and the like.

Referring toFIG. 3B, the gate insulating pattern12is coated over the lower substrate1provided with the first conductive pattern group. Further, semiconductor pattern including the active layer14and the ohmic contact layer16; and a second conductive pattern group including the data line4, the source electrode8, the drain electrode10, and the lower data pad electrode62are formed on the gate insulating pattern12by the second mask process.

More specifically, a plurality of layers are sequentially provided on the lower substrate1. The gate insulating pattern12, an amorphous silicon layer, a n+amorphous silicon layer, and a data metal layer are sequentially disposed on the lower substrate1provided with the first conductive pattern group formed by the deposition techniques such as plasma enhanced chemical vapor deposition (PECVD) and the sputtering, etc. Herein, the gate insulating pattern12is formed from an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx). The data metal layer is selected from molybdenum (Mo), titanium (Ti), tantalum (Ta) or a molybdenum alloy, etc.

Then, a photo-resist pattern is formed on the data metal layer by photolithography using a second mask process. In this process, a diffractive exposure mask having a diffractive exposing part at a channel portion of the thin film transistor is used, thereby allowing a photo-resist pattern of the channel portion to have a lower height than other source/drain pattern portion. Subsequently, the source/drain metal layer is patterned by a wet etching process using the photo-resist pattern to provide the second conductive pattern group including the data line4, the source electrode8, and the drain electrode10which is integral to the source electrode8.

Next, the n+amorphous silicon layer and the amorphous silicon layer are patterned simultaneously by a dry etching process using the same photo-resist pattern to provide the ohmic contact layer16and the active layer14. The photo-resist pattern having a relatively low height is removed from the channel portion by the ashing process and thereafter the source/drain metal layer and the ohmic contact layer16of the channel portion are etched by the dry etching process. The active layer14of the channel portion is exposed to disconnect the source electrode8from the drain electrode10. Then, the photo-resist pattern left on the second conductive pattern group is removed by the stripping process.

Referring toFIG. 3C, the protective film18including the first to third contact holes20,56and66are formed on the gate insulating pattern12provided with the second conductive pattern group. The protective film18is entirely formed on the gate insulating pattern12by a deposition technique such as the plasma enhanced chemical vapor deposition (PECVD). Then, the protective film18is patterned by the photolithography and the etching process using a third mask to define the first to third contact holes20,56and66. The first contact hole20passes through the protective film18to expose the drain electrode10, whereas the second contact hole56passes through the protective film18and the gate insulating pattern12to expose the lower gate pad electrode52. The third contact hole66passes through the protective film18to expose the lower gate pad electrode52. Herein, when a metal having a large dry etching ratio, such as molybdenum (Mo), is used as the data metal layer, the first and third contact holes20and66pass through the drain electrode10and the lower data pad electrode62, respectively, to expose the side surfaces thereof. The protective film18is made from an inorganic insulating material identical to the gate insulating pattern12, or an organic insulating material such as an acrylic organic compound having a small dielectric constant, BCB (benzocyclobutene) or PFCB (perfluorocyclobutane), etc.

Referring toFIG. 3D, the third conductive pattern group including the pixel electrode22, the upper gate pad electrode54, and the upper data pad electrode64are provided on the protective film18by the fourth mask process. More specifically, a transparent conductive film is coated onto the protective film18by a deposition technique such as the sputtering, etc. Then, the transparent conductive film is patterned by the photolithography and the etching process using a fourth mask to provide the third conductive pattern group including the pixel electrode22, the upper gate pad electrode54, and the upper data pad electrode64. The pixel electrode22is electrically connected to the drain electrode10via the first contact hole20. The upper gate pad electrode54is electrically connected to the lower gate pad electrode52via the second contact hole56. The upper data pad electrode64is electrically connected to the lower data pad electrode62, via the third contact hole66. The transparent conductive film is formed from indium-tin-oxide (ITO), tin-oxide (TO), indium-tin-zinc-oxide (ITZO) or indium-zinc-oxide (IZO).

As described above, the related art thin film transistor array substrate structure and the fabricating method thereof adopts the four-round mask process, thereby reducing the total number of fabricating processes and hence reducing a manufacturing cost proportional to the fabrication with the five-round mask process. However, since the four-round mask process still has a complicate fabricating process to limit the cost reduction, there has been required a scheme capable of more simplifying the fabricating process to further reduce the manufacturing cost.

Furthermore, as shown inFIG. 4A, the thin film transistor array substrate structure of the related art liquid crystal display panel includes a gate shorting bar80connected to the gate pad50via a gate shorting line82, and a data shorting bar90connected to the data pad60via a data shorting line92. This feature is included to conduct a quality check to inspect a short and a breakage of the signal line after it was provided by the four-round mask process. As shown inFIG. 4B, when the lower substrate1is taken along the scribing line SCL (line crossing through the gate shorting line82and the data shorting line92) after a poor performance of the liquid crystal display panel was detected by the shorting bars80and90, then the gate shorting line82and the data shorting line92would have been exposed along the side surface of the lower substrate1. In this case, a metal possessing a poor corrosion resistance, for example, the gate shorting line82formed from aluminum or copper, etc. becomes liable for a metal corrosion at a high temperature and in a humid environment. In addition, application of an electric field for driving of the TFT can cause the metal corrosion. These corrosion phenomenon can cause further problems such that the metal corrosion can extend into the gate pad50and the data pad60as well as the gate line2and the data line4when given sufficient time.

SUMMARY OF THE INVENTION

Accordingly, the present invention is directed to a liquid crystal display panel and a fabricating method thereof that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.

An object of the present invention is to provide a liquid crystal display panel and a fabricating method thereof that is adaptive for preventing a corrosion of a shorting line when connecting a shorting bar to a pad.

Additional advantages of the invention will be set forth in the description which follows, and in part will become apparent from the description, or may be learnt by practice of the invention. These advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a liquid crystal display panel including a thin film transistor array substrate structure including a substrate, a gate line and a data line disposed on the substrate and insulated from each other by a gate insulating pattern therebetween, a thin film transistor disposed at an intersection of the gate line and the data line, a protective film disposed to protect the thin film transistor, and a pad structure connected to a respective one of the gate line and data line, the pad structure including a transparent conductive film and a data metal layer, and a color filter array substrate structure joined with the thin film transistor array substrate structure, wherein the protective film is disposed within an area where the color filter array substrate structure overlaps with the thin film transistor array substrate structure so that either the data metal layer or the transparent conductive film is exposed along a side portion of the substrate.

In another aspect, a method of fabricating a liquid crystal display panel including the steps of forming a first conductive pattern group including a gate line, a gate electrode, a gate pad and a data pad each including a transparent conductive film, and a pixel electrode on a substrate, forming a semiconductor pattern and a gate insulating pattern on the substrate which is provided with the first conductive pattern group and the pixel electrode, forming a second conductive pattern group including a data line, a source electrode, and, a drain electrode on the substrate which is provided with the semiconductor pattern and the gate insulating pattern, forming a thin film transistor by the first conductive pattern group, the semiconductor pattern, gate insulating pattern, and the second conductive pattern group, providing a protective film on the substrate and the thin film transistor to protect the thin film transistor, forming an alignment film on the protective film at an area other than a pad area which includes the gate pad and the data pad, removing the protective film from a portion of the pad area by utilizing the alignment film as a mask to expose the transparent conductive film included in the pad area, and scribing the substrate along a scribing line where the scribing line crosses a shorting line connected to the data pad and the gate pad, wherein the shorting line is provided so that at least one of the transparent conductive film and a data metal layer is exposed along a side portion of the substrate during the scribing step.

In another aspect, the method of fabricating a liquid crystal display panel including the steps of providing a thin film transistor array substrate structure having a gate line and a data line disposed on a substrate and insulated from each other by a gate insulating pattern therebetween, a thin film transistor disposed at an intersection of the gate line and the data line, a pixel electrode connected to the thin film transistor, a protective film disposed to protect the thin film transistor, a pad structure connected to a respective one of the gate line and data line and including a transparent conductive film and a data metal layer, joining a color filter array substrate structure with the thin film transistor array substrate structure, and providing a protective film within an area where the color filter array substrate structure overlaps with the thin film transistor array substrate structure so that either the data metal layer or the transparent conductive film is exposed along a side portion of the substrate.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference toFIGS. 5 to 22.

FIG. 5is a plan view showing a structure of a thin film transistor array substrate structure according to a first embodiment of the present invention, andFIG. 6is a cross-sectional view of the thin film transistor array substrate structure taken along the line VI-VI′ ofFIG. 5. Referring toFIG. 5andFIG. 6, the thin film transistor array substrate structure includes a display portion for implementing a picture, a pad portion for applying driving signals to signal lines of the display portion, and a shorting portion for inspecting a performance of the display part.

The display portion includes a gate line102and a data line104provided on a lower substrate101intersecting each other and having a gate insulating pattern112disposed therebetween. The gate line102is provided to apply a gate signal and the data line104is provided to apply a data signal at the intersection structure to define the pixel area105. The display portion further includes a thin film transistor130provided at the intersection, and a pixel electrode122provided at a pixel area defined by the intersection structure. The thin film transistor130allows a pixel signal on the data line104to be charged and maintained at the pixel electrode122in response to a gate signal on the gate line102.

The thin film transistor130includes a gate electrode106connected to the gate line102, a source electrode108connected to the data line104, and a drain electrode110connected to the pixel electrode122. Further, the thin film transistor130includes an active layer114overlapping the gate electrode106with having the gate insulating pattern112disposed therebetween to define a channel between the source electrode108and the drain electrode110. An ohmic contract layer116for making a contact with the data line104and the drain electrode110is further provided on the active layer114.

The pixel electrode122is directly connected to the drain electrode110of the thin film transistor130, and is provided at a pixel area105. The pixel electrode122includes a transparent conductive film170which is exposed and formed at the pixel area105, and a gate metal film172is provided at the portion appropriate to the drain electrode110on the transparent conductive film170.

Accordingly, an electric field is formed between the pixel electrode122to which a pixel signal is applied via the thin film transistor130and a common electrode (not shown) supplied with a reference voltage. Such an electric field rotates liquid crystal molecules between the thin film transistor array substrate and the color filter array substrate structure owing to a dielectric anisotropy. Transmittance of a light to the pixel area105is varied depending upon a rotation extent of the liquid crystal molecules, thereby implementing a gray level scale.

The pad portion includes a gate pad150extended from the gate line102, and a data pad160extended from the data line104. The gate pad150is connected to a gate driver (not shown) which generates a gate signal and applies the gate signal to the gate line102via a gate link152. The gate pad150has a structure in which the transparent conductive film170included in both gate pad150and gate link152connected to the gate line102is exposed. The data pad160is connected to a data driver (not shown) which generates a data signal and applies the data signal to the data line104via a data link168. The data pad160has a structure in which the transparent conductive film170included in the data link168connected to the data line104is exposed. Herein, the data link168comprises a lower data link electrode162formed simultaneously with the gate link152, and an upper data link electrode166connected to the data line104.

The shorting portion includes a shorting bar supplied with an inspection signal to inspect a performance of the signal line including the gate line102and the data line104, and a performance of the thin film transistor130. Further, the shorting bar is connected to a ground voltage source GND to shut off a static electricity transferred into the signal lines of the liquid crystal display panel during the fabrication process to protect the thin film transistor130from the static electricity.

The shorting bar includes a gate shorting bar180connected to the gale line102via the gate pad150, and a data shorting bar190connected to the date line104via the data pad160. The gate shorting bar180has a structure in which the transparent conductive film170and the gate metal film172formed thereon are exposed. The gate shorting bar180is electrically connected to the gate pad150via a gate shorting line182. The data shorting bar190has a structure in which the transparent conductive film170and the gate metal film172formed thereon are exposed. The data shorting bar190is electrically connected to the data pad160via a data shorting line192. The gate shorting line182and the data shorting line192are formed of a metal identical to the data line, for example, a metal having a strong corrosion resistance such as molybdenum (Mo), chrome (Cr), titanium (Ti), tantalum (Ta) or MoW.

The gate shorting line182is connected to both the gate shorting bar180and the gate pad150via a shorting contacting hole184and a second contact hole186, respectively. Both the first and second contact holes184and186are formed to pass through the insulating film112, the active layer114, and the ohmic contact layer116. The data shorting line192is connected to both the data shorting bar190and the data pad160via a third shorting contact hole194and a fourth shorting contact hole196, respectively. Both the third and fourth shorting contact holes194and196are formed to pass through the gate pad160via insulating film112, the active layer114, and the ohmic contact layer116.

The gate shorting line182and the date shorting line192are formed of a metal having a strong resistance to an electrochemical corrosion. The data metal layer109used to form the shorting lines182and192are exposed along the side surface of the lower substrate101during the scribing process. This prevents a corrosion of the shorting lines182and192and furthermore prevents a corrosion of the gate pad150and the data pad160.

FIG. 7AtoFIG. 7Care cross-sectional views taken along the lines VI-VI′, for explaining a method of fabricating the thin film transistor array substrate structure according to the first embodiment of the present invention. Referring toFIG. 7A, the pixel electrode122; and a first conductive pattern group including the gate line102, the gate electrode106, the gate link152, the gate pad150, the data pad160, the lower data link electrode162, the gate shorting bar180, and the data shorting bar190formed on the lower substrate101by the first mask process.

More specifically, the transparent conductive film170and the gate metal film172are sequentially disposed on the lower substrate101by a deposition technique such as the sputtering. The transparent conductive film170is made from a transparent conductive material such as indium-tin-oxide (ITO), tin-oxide (TO), indium-tin-zinc-oxide (ITZO), indium-zinc-oxide (IZO) or the like. The gate metal film172is made from a metal such as an aluminum group metal, molybdenum (Mo), copper (Cu) or the like. Then, the transparent conductive film170and the gate metal film172are patterned by photolithography and etching processes using a first mask to provide the pixel electrode122and the first conductive pattern group.

Referring toFIG. 7B, a gate insulating pattern112and a semiconductor pattern including the active layer114and the ohmic contact layer116are formed by the second mask process on the lower substrate101already provided with the first conductive pattern group. More specifically, the gate insulating pattern112and the active layer114, and the ohmic contact layer116are sequentially formed by a deposition technique such as the PEVCD, the sputtering or the like on the lower substrate101. The gate insulating pattern112is formed from an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx). The active layer114(i.e., first semiconductor layer) is formed from amorphous silicon not doped with an impurity. The ohmic contact layer116(i.e., second semiconductor layer) is formed from amorphous silicon doped with an N-type or P-type impurity. Then, the gate insulating pattern112and the first and second semiconductor layers are patterned by the etching process using a second mask to provide the gate insulating pattern112overlapping the gate line102, the gate electrode106, the gate link152, and the data link162and the semiconductor pattern.

The semiconductor pattern includes the active layer114and the ohmic contact layer116formed on the gate insulating pattern112. The semiconductor pattern is provided with a larger width than the first conductive pattern group to prevent a deterioration of channel characteristic which may occur if the semiconductor pattern has a smaller width than the gate electrode106. Further, the first to fourth shorting contact holes184,186,194and196are provided to expose a portion of the gate shorting bar180, the gate pad150, the data shorting bar190, and the data pad160, respectively.

Referring toFIG. 7C, a second conductive pattern group including the data line104, the source electrode108, the drain electrode110, the upper data link electrode166, the gate shorting line182and the data shorting line192are formed on the lower substrate101already provided with the gate insulating pattern112, the semiconductor pattern, and the first to fourth shorting contact holes184,186,194and196created by a third mask process. In addition, portions of the gate metal film172included in the data pad160, the gate pad150and the pixel electrode122are removed to expose the transparent conductive film170.

The third mask process will be described with reference toFIG. 8AtoFIG. 8Ebelow. As shown inFIG. 8A, a data metal layer109and a photo-resist film228are sequentially formed on the lower substrate101already provided with the semiconductor pattern by a deposition technique such as the sputtering, etc. The data metal layer109is formed from a metal such as molybdenum (Mo), copper (Cu) or the like. Then, the third mask220, that is a partial exposure mask, is aligned at the upper portion of the lower substrate101. The third mask220includes a mask substrate222made from a transparent material, a shielding part224provided at a shielding area S1of the mask substrate222, and a diffractive exposure part (or transflective part)226provided at a partial exposure area S3of the mask substrate222. The remaining portions of the mask substrate222(area not used as S1or S3) becomes an exposure area S2.

As shown inFIG. 8B, the photo-resist film228is removed using the third mask220and then developed to provide a photo-resist pattern230having step coverage at the shielding area S1and the partial exposure area S3in correspondence with the shielding part224and the diffractive exposure part226of the third mask220. The photo-resist pattern230has a lower height at the partial exposure part S3than to the shielding area S1.

The data metal layer109is patterned by the wet etching process using the photo-resist pattern230as a mask, thereby providing a second conductive pattern group. The second conductive pattern group includes the data line104, the source electrode108and the drain electrode110connected to one side of the data line104, the upper data link electrode166connected to other side of the data line104, the gate shorting line182, and the data shorting line192. Further, the gate metal film172in the second conductive pattern group is removed by utilizing the gate insulating pattern112as a mask, thereby exposing portions of the transparent conductive film170included in the data pad160, the gate pad150and the pixel electrode122. Next, the active layer114and the ohmic contact layer116are formed with respect to the second conductive pattern group by the dry etching using the photo-resist pattern230as a mask. At this time, the active layer114and the ohmic contact layer116disposed at an area other than the second conductive pattern group are removed. This aims at preventing a short between the liquid crystal cells caused by the semiconductor pattern including the active layer114and the ohmic contact layer116.

Then, as shown inFIG. 8C, the photo-resist pattern230having a lower height at the partial exposure area S3is removed by the ashing process using oxygen (O2) plasma. The photo-resist pattern230at the shielding area S1becomes a lower height than an initial height. The data metal layer109and the ohmic contact layer116provided at the partial exposure area S3(the channel portion of the thin film transistor) are removed by the etching process using the photo-resist pattern230, thereby disconnecting the drain electrode110from the source electrode108. Further, as shown inFIG. 8D, the photo-resist pattern230left on the second conductive pattern group is removed by the stripping process. Subsequently, as shown inFIG. 8E, a protective film118is formed over an entire surface of the substrate101. The protective film118is made from an inorganic insulating material identical to the gate insulating pattern112, or an organic insulating material such as an acrylic organic compound having a small dielectric constant, BCB (benzocyclobutene) or PFCB (perfluorocyclobutane), etc.

FIG. 9is a plan view showing a structure of a thin film transistor array substrate structure according to a second embodiment of the present invention, andFIG. 10is a cross-cross-sectional view of the thin film transistor array substrate structure taken along line X-X′ ofFIG. 9. The thin film transistor array substrate structure shown inFIG. 9andFIG. 10has similar elements as that of shown inFIG. 5andFIG. 6except that a gate shorting bar280and a data shorting bar290are formed from a metal having a strong resistance to an electro-chemical corrosion. Thus, a detailed explanation of the similar elements will be omitted.

The gate shorting bar280is formed from a metal identical to the data line104, for example, a metal having a strong corrosion resistance such as molybdenum (Mo), chrome (Cr), titanium (Ti), tantalum (Ta) or MoW. The gate shorting bar280is electrically connected to the gate pad150via a gate shorting line282. The gate shorting line282includes a first gate shorting line282aextended from the gate shorting bar280crossing a scribing line SCL, and a second gate shorting line282bextended from the gate pad150. The first and second gate shorting lines282aand282bare electrically connected to the gate insulating pattern112via a first shorting contact hole284passing through the active layer114and the ohmic contact layer116. The first gate shorting line282ais formed from a metal having a strong resistance to the electro-chemical corrosion, in a similar manner to the gate shorting bar280. The second gate shorting line282bis comprised of the transparent conductive film170and the gate metal film172formed in a similar manner to that of the gate pad150.

The data shorting bar290is formed from a metal identical to the data line104, for example, a metal having a strong corrosion resistance such as molybdenum (Mo), chrome (Cr), titanium (Ti), tantalum (Ta) or MoW. The data shorting bar290is electrically connected to the data pad160via a data shorting line292and includes a first data shorting line292aextended from the data shorting bar290crossing the scribing line SCL, and a second data shorting line292bextended from the data pad160. The first and second data shorting lines292aand292bare electrically connected to the gate insulating pattern112via a second shorting contact hole294passing through the active layer114and the ohmic contact layer116. The first data shorting line292ais formed from a metal having a strong resistance to the electro-chemical corrosion in a similar manner to that of the data shorting bar290. The second data shorting line292bis comprised of the transparent conductive film170and the gate metal film172formed in similar manner to that of the data pad160.

As mentioned above, the shorting lines282aand292aprovided at an area corresponding to the scribing area are formed from a metal identical to the data line104, which has a strong resistance to the electrochemical corrosion. During the scribing process, metal forming the shorting lines282and292are exposed along the side surface of the lower substrate101. This prevents a corrosion of the shorting lines282and292and furthermore prevents a corrosion of the gate pad150and the data pad160.

Next, a method of fabricating a thin film transistor array substrate structure of the liquid crystal display panel according to the second embodiment will be described below. As shown inFIG. 11A, a first conductive pattern group including the gate line102, the gate electrode106, the second gate shorting line282b, the second data shorting line292b, the gate pad150and the data pad160are provided on the lower substrate101by the first mask process. As shown inFIG. 11B, the gate insulating pattern112having first and second shorting contact holes284and294and the semiconductor pattern (the active layer114and ohmic contact layer116) are provided by the second mask process. As shown inFIG. 11C, a second conductive pattern group including the gate shorting bar280, the data shorting bar290, the first gate shorting line282a, the first data shorting line292a, the source electrode108, the drain electrode110, the data line104and the upper data link electrode166are provided. The portions of transparent conductive film170included in the gate pad150, the data pad160and the pixel electrode122are exposed by the third mask process. Then, the protective film118for protecting the thin film transistor130is provided over the entire surface of the lower substrate101.

FIG. 12is a plan view showing a structure of a thin film transistor array substrate structure according to a third embodiment of the present invention, andFIG. 13is a cross-sectional view of the thin film transistor array substrate structure taken along line XIII-XIII′ ofFIG. 12. The thin film transistor array substrate structure shown inFIG. 12andFIG. 13have similar elements as that ofFIG. 5andFIG. 6except that the transparent conductive film170included in a gate shorting bar380and a data shorting bar390are exposed. Thus, a detailed explanation of the similar elements will be omitted.

The gate shorting bar380is electrically connected to the gate pad150, via a gate shorting line382. The gate shorting bar380has a structure in that the area forming the gate shorting line382is enclosed by the transparent conductive film170and the gate metal film172. Remaining area of the gate shorting bar380has the gate metal film172removed, thus exposing the transparent conductive film170. The data shorting bar390is electrically connected to the data pad160via a data shorting line392. The data shorting bar390has a structure in that the area forming the data shorting line392is enclosed by the transparent conductive film170and the gate metal film172. Remaining area of the data shorting bar390has the gate metal film172removed, thus exposing the transparent conductive film170. The gate shorting line382and the data shorting line392are formed from a metal identical to the data line104, for example, a metal having a strong corrosion resistance such as molybdenum (Mo), chrome (Cr), titanium (Ti), tantalum (Ta) or MoW. The gate shorting line382is directly connected to portions of the gate metal film172included in each of the gate shorting bar380and the gate pad150. The data shorting line392is connected to portions of gate metal film172included in each of the data shorting bar390and the data pad160.

As mentioned above, the shorting lines382and392are formed from a metal having a strong resistance to electrochemical corrosion. During the scribing process, metal forming the shorting lines382and392are exposed along the side surface of the lower substrate101. This prevents a corrosion of the shorting lines382and392and prevents corrosion of the gate pad150and the data pad160.

Next, a method of fabricating a thin film transistor array substrate structure of the liquid crystal display panel according to the third embodiment will be described below.

As shown inFIG. 14A, a first conductive pattern group including the gate line102, the gate electrode106, the gate shorting bar380, the gate pad150, the data shorting bar390, and the data pad160; and the pixel electrode122including the gate metal film172are provided by the first mask process.FIG. 14Bshows the gate insulating pattern112exposing the gate shorting bar380, the gate pad150, the data shorting bar390, and the data pad160by the second mask process. The second mask process also provides the semiconductor pattern which includes active layer114and ohmic contact layer116. InFIG. 14C, a second conductive pattern group including the data line104, the source electrode108, the drain electrode110, the gate shorting line382and the data shorting line392are provided by the third mask process. The portions of gate metal film172included in the pixel electrode122, the gate shorting bar380, the gate pad150, the data shorting bar390, and the data pad160are patterned by utilizing the second conductive pattern as a mask, thereby exposing the transparent conductive film170included in them.

FIG. 15is a plan view showing a structure of a thin film transistor array substrate structure according to a fourth embodiment of the present invention, andFIG. 16is a cross-sectional view of the thin film transistor array substrate structure taken along line XVI-XVI′ ofFIG. 15. The thin film transistor array substrate structure shown inFIG. 15andFIG. 16has similar elements as that shown inFIG. 5andFIG. 6except that a transparent conductive film of a shorting line is exposed along a scribing line. Thus, a detailed explanation of the similar elements will be omitted.

The gate shorting bar480is electrically connected to the gate pad150via a gate shorting line482. The gate shorting bar480has a structure in which the area forming the shorting line482along the scribing line SCL exposes the transparent conductive film170. The data shorting bar490is electrically connected, via a data shorting line492, to the data pad160. The data shorting bar490has a structure in that the area forming the data shorting line492along the scribing line SCL exposes the transparent conductive film170.

At least one of the data shorting line482and the gate shorting line492is comprised of the transparent conductive film170and the gate metal film172in which the transparent conductive film170is partially exposed. In other words, the shorting lines482and492are provided in such a manner to expose the transparent conductive film170at an area corresponding to the scribing line SCL of the lower substrate101. This aims at preventing the gate metal film172from being exposed along the side surface thereof and corrosion of the shorting lines482and492by the scribing process when the shorting lines482and492are provided with a gate metal film172at area corresponding to the scribing line SCL. The gate metal film172formed on the shorting lines482and492is removed in the scribing process. Accordingly, the transparent conductive film170is exposed when the lower substrate101is taken along the scribing line SCL, thereby eliminating a risk of corrosion.

FIG. 17AtoFIG. 17Care cross-sectional views taken along line XVI-XVI′ ofFIG. 15for explaining a method of fabricating the thin film transistor array substrate structure according to the fourth embodiment of the present invention. Referring toFIG. 17A, the pixel electrode122; and a first conductive pattern group including the gate line102, the gate electrode106, the gate link152, the gate pad150, the data pad160, the lower data link electrode162, the gate shorting bar480, the gate shorting line482, the data shorting bar490and the data shorting line492are formed on the lower substrate101by the first mask process.

More specifically, the transparent conductive film170and the gate metal film172are sequentially formed on the lower substrate101by a deposition technique such as the sputtering. The transparent conductive film170is made from a transparent conductive material such as indium-tin-oxide (ITO), tin-oxide (TO), indium-tin-zinc-oxide (ITZO), indium-zinc-oxide (IZO) or the like. The gate metal film172is made from a metal such as an aluminum group metal, molybdenum (Mo), copper (Cu) or the like. Then, the transparent conductive film170and the gate metal layer172are patterned by the photolithography and the etching process using a first mask to provide the pixel electrode122, and the first conductive pattern group.

Referring toFIG. 17B, a gate insulating pattern112; and a semiconductor pattern including the active layer114and the ohmic contact layer116are formed on the lower substrate101already provided with the first pattern group by the second mask process. A gate insulating pattern112, the active layer114, and the ohmic control layer116are sequentially formed on the lower substrate101by a deposition technique such as the PEVCD, the sputtering or the like. The gate insulating pattern112is formed from an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx). The active layer114is formed from amorphous silicon not doped with an impurity while the ohmic contact layer116is formed from amorphous silicon doped with an N-type or P-type impurity. Then, the gate insulating pattern112, the active layer114, and ohmic contact layer116are patterned by the etching process using a second mask to provide the gate insulating pattern112overlapping the gate line102, the gate electrode106, the gate link152and the data link162, and the semiconductor pattern. The semiconductor pattern formed on the gate insulating pattern112has a larger width than the first conductive pattern group.

Referring toFIG. 17C, a second conductive pattern group including the data line104, the source electrode108, the drain electrode110and the upper data link electrode166is formed on the lower substrate101already provided with the gate insulating pattern112and the semiconductor pattern. Further, the gate metal films172included in the data pad160, the gate pad150, the pixel electrode122, the gate shorting line482and the data shorting line492are removed to expose the transparent conductive film170.

A third mask process according to the fourth embodiment, will be described in detail with reference toFIG. 18AtoFIG. 18Ebelow. As shown inFIG. 18A, a data metal layer109and a photo-resist film228are sequentially formed by a deposition technique such as the sputtering, etc. on the entire lower substrate101. The data metal layer109is formed from a metal such as molybdenum (Mo), copper (Cu) or the like. Then, a third mask220, that is a partial exposure mask, is aligned at the upper portion of the lower substrate101. The third mask220includes a mask substrate222made from a transparent material, a shielding part224provided at a shielding area S1of the mask substrate222, and a diffractive exposure part (or transflective part)226provided at a partial exposure area S3of the mask substrate222. The remaining portions of the mask substrate222(areas not used as S1or S3) becomes an exposure area S2.

As shown inFIG. 18B, the photo-resist film228is removed using the third mask220and then developed to provide a photo-resist pattern230having step coverage at the shielding area S1and the partial exposure area S3in correspondence with the shielding part224and the diffractive exposure part226of the third mask220. The photo-resist pattern230has a lower height at the partial exposure part S3than the shielding area S1.

InFIG. 18B, the data metal layer109is patterned by the wet etching process using the photo-resist pattern230as a mask, to provide a second conductive pattern group. The second conductive pattern group includes the data line104, the source electrode108and the drain electrode110connected to one side of the data line104, and the upper data link electrode166connected to the other side of the data line104. Further, the portions of gate metal film172provided in the second conductive pattern group are removed by utilizing the gate insulating pattern112as a mask, thereby exposing the transparent conductive films170included in the data pad160, the gate pad150, the pixel electrode122, the gate shorting line482, and the data shorting line492. Next, the active layer114and the ohmic contact layer116are formed with respect to the second conductive pattern group by the dry etching using the photo-resist pattern230as a mask. At this time, the active layer114and the ohmic contact layer116disposed at an area other than the second conductive pattern group are removed to prevent a short between the liquid crystal cells caused by the semiconductor pattern including the active layer114and the ohmic contact layer116.

Then, as shown inFIG. 18C, by the ashing process using oxygen (O2) plasma, the photo-resist pattern230at the partial exposure area S3is removed. And, the photo-resist pattern230at the shielding area S1is left with a lower height than an initial height. The data metal layer109and the ohmic contact layer116provided at the partial exposure area S3, (the channel portion of the thin film transistor) are removed by the etching process using the photo-resist pattern230, thereby disconnecting the drain electrode110from the source electrode108. Further, as shown inFIG. 18D, the photo-resist pattern230left on the second conductive pattern group is removed by the stripping process.

Subsequently, as shown inFIG. 18E, protective film118is formed over the entire surface of the substrate101. The protective film118is made from an inorganic insulating material identical to the gate insulating pattern112, or an organic insulating material such as an acrylic organic compound having a small dielectric constant, BCB (benzocyclobutene) or PFCB (perfluorocyclobutane), etc.

FIG. 19is a cross-sectional view showing a liquid crystal display panel including the thin film transistor array substrate structure according to a fifth embodiment of the present invention. Referring toFIG. 19, the liquid crystal display panel includes a thin film transistor array substrate structure302and a color filter array substrate structure300that are joined to each other by a sealant254. In the color filter array substrate structure300, a color filter array252including black matrices, color filters and common electrodes are provided on an upper substrate250. The thin film transistor array substrate structure302is provided such that an area overlapping the color filter array substrate structure300is protected by a protective film118, whereas portions of the transparent conductive film170included in the gate pad150and the data pad160at a pad area that does not overlap with the color filter array substrate structure300are exposed.

A method of fabricating the liquid crystal display panel according to the fifth embodiment will be described below.

According to the fifth embodiment, the color filter array substrate structure300and the thin film transistor array substrate structure302shown inFIG. 19are prepared separately and thereafter joined to each other by the sealant254. Then, the protective film118of the thin film transistor array substrate structure302shown inFIG. 19is patterned by a pad opening process using the color filter array substrate structure300as a mask, thereby providing the transparent conductive films170in the gate pad150and the data pad160at the display area. Subsequently, a non-display area including the gate shorting portion (portion of gate pad150, gate shorting line182, shorting contact hole186) and the data shorting portion (portion of date pad160, data shoring line192, shorting contact hole196) are removed from the scribing line by the scribing process. InFIG. 20, the data metal layer109is exposed at scribing line. InFIG. 21, the transparent conductive film170is exposed along the side surface of the substrate101which has the data metal layer109removed along the scribing line SCL, thus preventing corrosion.

FIG. 22is a cross-sectional view showing other example of a liquid crystal display panel including the thin film transistor array substrate structure according to the fifth embodiments of the present invention. Referring toFIG. 22, the liquid crystal display panel includes an color filter array substrate structure300and a thin film transistor array substrate structure302that are joined to each other by a sealant254. In the color filter array substrate structure300, a color filter array252including black matrices, color filters, and common electrodes are provided on an upper substrate250.

The thin film transistor array substrate structure302is provided such that an area defined by an alignment film256is protected by a protective film118while the transparent conductive films170included in the pad area that does not overlap with the alignment film256is exposed. In this case, the protective film118is patterned by the etching process using the alignment film256as a mask. Subsequently, a non-display area including the gate shorting portion (portion of gate pad150, gate shorting line182, shorting contact hole186) and the data shorting portion (portion of date pad160, data shoring line192, shorting contact hole196) are removed from the scribing line by the scribing process. InFIG. 20, the data metal layer109is exposed. InFIG. 21, the transparent conductive film170is exposed along the side surface of the substrate101which has the data metal layer109removed along the scribing line SCL, thus preventing corrosion.

Meanwhile, the pad opening process sequentially scans each pad exposed by the color filter array substrate structure300using a plasma generated by an atmosphere plasma generator, or collectively scans the color filter array substrate structure300for each pad, thereby exposing the transparent conductive films170of the gate pad150and the data pad160. Alternatively, a plurality of liquid crystal cells made by joining the color filter array substrate structure300with the thin film transistor array substrate structure302are introduced as a chamber. Thereafter the protective film118at the pad area is exposed by the color filter array substrate structure300with the aid of a normal-pressure plasma etching, and furthermore exposing the transparent conductive films170of the gate pad150and the data pad160. Otherwise, the entire liquid crystal display panel having the color filter array substrate structure300and the thin film transistor array substrate structure302joined with each other is immersed into an etching liquid, or the pad area corresponding only to the gate pad150and the data pad160is immersed into the etching liquid, thereby exposing the transparent conductive films170of the gate pad150and the data pad160.

As described above, according to the present invention, the shorting lines provided at an area corresponding to a scribing area (area where the shorting lines crossing the scribing line SCL) are formed from a metal identical to the data line, which has a strong resistance to electro-chemical corrosion. During the scribing process, metal forming the shorting lines are exposed at the scribing area to connect the pad with the shorting bar. In other words, the shorting line is formed from a data metal layer109containing molybdenum (Mo), chrome (Cr), titanium (Ti), tantalum (Ta) or MoW, or a transparent conductive material containing ITO or IZO. Accordingly, a metal strong to electro-chemical corrosion is exposed along the side surface of the substrate after the scribing process, thus preventing a corrosion phenomenon of the signal line.