Method and apparatus for minimizing threshold variation from body charge in silicon-on-insulator circuitry

Circuitry used to de-skew data channels coupling parallel data signals over a communication link employs SOI circuitry that is subject to generating pulse distortion due to the history effect modifying threshold voltages. To substantially eliminate the pulse distortion, data signals are XOR with a repeating scramble data pattern that generates scrambled data with a minimum average ratio of logic ones to logic zeros logic zeros to logic ones. The scrambled data is sent over the communication link and de-skewed in the SOI circuitry with little or no pulse distortion. The scramble data pattern is again generated at the receiver side of the communication link after a delay time to synchronize the logic states of the scramble data pattern that generated the scrambled data with the scrambled data at the receiver side. The delayed scrambled data pattern is again XOR'ed with the scrambled data to recover the data signal.

TECHNICAL FIELD

The present invention relates in general to complementary metal oxide semiconductor (CMOS) circuitry and in particular to Silicon-on-Insulator (SOI) CMOS circuitry.

BACKGROUND INFORMATION

In a typical data communications system, data must be sent from some driving latch and captured at a receiving latch.FIG. 1shows basic block diagrams of such a data communications system implemented as either a chip-to-chip interface100or an on-chip interface120. In a chip-to-chip interface100, various components such as off-chip drivers (e.g.,103) and receivers (e.g.,105), transmission lines (e.g.,104) (printed wiring boards and/or cables), and some amount of logic circuitry (e.g.,106) will exist in the communications path. In contrast, an on-chip interface will typically comprise only internal logic gates (e.g.,109,110, and111) in the communications path.

Either of these communications systems may be implemented using SOI technology which give rise to the “history effect” which cause pulse width distortions. The history effect occurs when an SOI gate sustains a steady logic state (logic one or logic zero). The steady logic state tends to modify the body charge on SOI devices which in turn changes the gate threshold voltage which determines voltage levels at which logic state switching occurs. If one logic transition to a logic state occurs with one body charge condition and the next transition occurs with another different body charge condition, then the resulting pulse width will be modified (history effect) which may lead to timing errors. This history effect is typically fixed by using body-contacted devices; however, at high enough frequencies the body (dis)charge time constant is larger than the pulse width so the history effect may remain even with body-contacted devices. If the SOI devices are not body-contacted, then they are floating-body devices and as such have a much longer body charge/discharge time constant which may be exploited.

FIG. 2is a timing diagram that illustrates the pulse modification in a SOI device due to the history effect discussed above. Of particular interest is what happens to the data as it passes through the blocks labeled “logic gates” inFIG. 1since these blocks have the greatest impact on the SOI history effect depending on the total delay through these sections. To explain the pulse modification on an input (trace201) due to the history effect, some basic time delays through the logic gates are defined. Propagation delay T prop is the amount of time that it takes for a signal to travel through the logic gates. The amount of delay due to the history effect is defined as T hist. Ideally, (trace202) the first and second consecutive logic state transitions at a given frequency will propagate through the logic gates with a delay of T prop as shown inFIG. 2. However, in SOI technology, the first logic transition is delayed (T prop+T hist) whereas the second consecutive logic transition is delayed by only T prop resulting in the pulse distortion shown in trace203FIG. 2.

In an exemplary chip-to-chip interface100, the logic gates106after the transmission line receiver105ofFIG. 1is replaced by a programmable delay circuitry which may selectable delay from zero picoseconds (0 psec)–500 psec for correcting the delay differences between parallel data channels. If the history effect caused a 10% history effect, then the delay circuitry would have a worst case 50psec pulse distortion. These channels may be clocked from 2 Gigabits per second (Gbps) to 5Gbps. At 5 Gbps, a 200 psec pulse would compress to 150 psec. This amount of pulse distortion along with the uncertainties of jitter and latch setup/hold times will result in high bit-error rates if un-compensated. One method of reducing the pulse distortion produced in such delay circuitry is to replace the delay circuitry with logic (not shown) that is clocked with multiple phases of a phase shifted clock configured to emulate the function of the delay circuitry. This resolves the problem because now a continuous pattern is being driven through the logic and the body voltage of the field effect transistor (FET) devices in the clocked logic maintains a constant charge and thus a fixed threshold voltage. However, this solution requires far more power and is thus less efficient requiring more power which is exacerbated by high frequency.

There is, therefore, a need for a method and circuitry to minimize the shift in gate threshold in SOI CMOS devices while maintaining the power efficiency of the delay circuitry for de-skewing parallel data channels.

SUMMARY OF THE INVENTION

A repeating scramble pattern having predetermined characteristics is exclusive OR'ed (XOR'ed) with the data generating a scrambled data pattern. The scramble pattern is configured to insure that the ratio of logic ones to logic zeros or the ratio of logic zeros to logic ones in the scrambled data pattern lie in a region between a predetermined minimum percentage (e.g., 25%) that has been determined to keep the body voltage substantially fixed and 50%. The scrambled data pattern is sent over the communication channel where it is received and coupled as the input to the delay circuitry which has been programmed to de-skew the parallel communication channels. The scramble pattern is a repeating pattern that is gated to start at a predetermined clock cycle. It is known that the logic transition of the predetermined clock cycle will propagate to the receiving side in the de-skewed propagation time. Therefore, a de-scramble pattern is synchronized with the scramble pattern to start at the predetermined clock cycle delayed by the propagation time. The de-scramble pattern is the same as the scramble pattern. The de-scramble pattern is XOR'ed with the received scrambled data pattern to recover the original data. Since the scrambled data has a guaranteed minimum average transition activity designed to keep the body voltage stable, the recovered data does not have pulse width modification.

DETAILED DESCRIPTION

FIG. 1illustrates a chip-to-chip communication path100and an intra-chip communication path120. In the chip-to-chip communication path100, a data signal101is clocked into latch102by a clock signal121and then off-chip driver103drives the data signal through transmission line104to receiver105. Logic gates106are used to process the bit stream represented by data signal101which is then latched in latch107in response to a clock signal122synchronous with the clock signal121. In the inter-chip communication path120, a data108is latched into a latch109and then passes through logic gates110to a latch111.

FIG. 2illustrates what happens to an input data signal201as it experiences the history effect when passing through an SOI logic circuit (not shown). Trace202illustrates an “ideal” output wherein the SOI logic circuit would simply delay each edge by a propagation time Tprop. Trace203illustrates the output from the SOI logic circuit with the history effect. The first transition has a delay that includes the propagation delay Tprop and the delay Thist due to threshold modification of the history effect. In this instance, input201remaining at a logic zero for an extended period of time causes the body voltage to increase the threshold so that the transition from a logic zero to a logic one adds additional delay.

FIG. 3is a circuit diagram of a circuit path for transmitting a data signal320from a latch302in one chip to a latch308in another chip using source synchronous interface. Data signal320is latched into latch302and driver303outputs data signal320to input304of transmission line305. Receiver306receives data signal320a delay time later. Logic gates307form a programmable delay circuit that is used to synchronize data signal320with clock314at the output315of receiver309. Clock314on output315clocks data320into latch308. If the logic gates307forming the delay circuitry are SOI and the frequency of data320is high enough, then periods of extended logic one or logic zero states on data signal320may lead to pulse distortion in logic gates307.

FIG. 4is a circuit diagram of scramble circuitry used to prevent history effect using source synchronous interface with SOI circuitry. A sync signal418is used to start scramble pattern generator419. N bit scramble bit pattern420is combined with data401in exclusive OR (XOR) gate401. N bit scramble bit pattern420is configured to insure that the output of XOR gate401has sufficient transitions to prevent the history effect from causing pulse distortion. The scrambled data423is latched into latch403with clock417in the first IC circuit. Driver404drives the scrambled data423over transmission line405to receiver406. The SOI circuitry407for processing data signal420now processes scrambled data423generating output408. Since scramble data423has a predetermined state change activity, there is little pulse distortion in SOI circuitry407. N bit scramble bit pattern424on output408is then combined with scramble data pattern408in XOR gate409to recover the original logic states of data signal401. N bit scramble bit patterns420and424are the same pattern shifted a propagation delay time. A calibration cycle is employed to synchronize sync signal418and sync signal412so that N bit scramble bit pattern424is generated synchronous with the logic states produced by corresponding bits of N bit scramble bit pattern420in XOR gate402. Clock signal417is processed through latch416, driver415, transmission line414, and receiver413to produce clock422. If SOI circuitry407assures that data signal401and clock422are source synchronous, then de-scrambled data signal (detected data)410and clock422will be likewise source synchronous with little or no pulse distortion of data signal401due to the history effect in SOI circuitry407when latched into latch421.

The only potential problem that may result is that the data signal401and the N bit scramble bit pattern420are one in the same. While this is a low probability, it will generate a scrambled data pattern with only one logic transition over the particular length of the N bit scramble bit pattern420. However, this event will only happen once within the scramble pattern cycle. Because of the time constant of the body voltage, it will not change significantly over this time period. On the next N bit scramble bit pattern cycle, the N bit scramble bit pattern420will resume with a normal distribution of logic state transitions as the data signal401and the scramble data pattern423will again be different.

FIG. 5illustrates a 64-bit scramble data pattern500that has attributes501–506and is suitable for practicing embodiments of the present invention. Attribute501is an equal number of logic ones and logic zeros, in this case, 32 logic ones and 32 logic zeros. Scramble data pattern500loops back to form a 64 bit repeating pattern (attribute502). To assure synchronization within scramble data pattern500, there is only one instance of the 0001 pattern (attribute503) which occurs over bits61,62,63and0. If the scramble data pattern500is stored in a shift register, then a logic AND of 4 consecutive bits can locate the 0001 pattern to synchronize outputting scramble data pattern500to combine with a data signal (e.g., data signal401). Attribute504assures some occurrences of lone logic zeros and attribute505assures some occurrences of lone logic ones. Finally, attribute506assures that when considering 8-bit beats (e.g., bit0, bit8, bit16, etc.) there is only one occurrence of a logic one (bit0). While other scramble data patterns are possible and within the scope of the present invention, scramble data pattern500assures that there will be on average a minimum of 25% ratio of logic ones to logic zeros or logic zeros to logic ones in a scrambled data (e.g., scrambled data423). Scramble data pattern cycles with less that 25% ratio occur with an infrequency that the body voltage time constant does not allow significant threshold voltage variations.

FIG. 6is a high level functional block diagram of a representative data processing system600suitable for practicing the principles of the present invention. Data processing system600includes a central processing system (CPU)610operating in conjunction with a system bus612. System bus612operates in accordance with a standard bus protocol, such as the ISA protocol, compatible with CPU610. CPU610operates in conjunction with electronically erasable programmable read-only memory (EEPROM)616and random access memory (RAM)614. Among other things, EEPROM616supports storage of the Basic Input Output System (BIOS) data and recovery code. RAM614includes, DRAM (Dynamic Random Access Memory) system memory and SRAM (Static Random Access Memory) external cache. I/O Adapter618allows for an interconnection between the devices on system bus612and external peripherals, such as mass storage devices (e.g., a hard drive, floppy drive or CD/ROM drive), or a printer640. A peripheral device620is, for example, coupled to a peripheral control interface (PCI) bus, and I/O adapter618therefore may be a PCI bus bridge. User interface adapter622couples various user input devices, such as a keyboard624or mouse626to the processing devices on bus612. Display638which may be, for example, a cathode ray tube (CRT), liquid crystal display (LCD) or similar conventional display units. Display adapter636may include, among other things, a conventional display controller and frame buffer memory. Data processing system600may be selectively coupled to a computer or telecommunications network641through communications adapter634. Communications adapter634may include, for example, a modem for connection to a telecom network and/or hardware and software for connecting to a computer network such as a local area network (LAN) or a wide area network (WAN). CPU610and other components of data processing system600may contain DLL circuitry for local generation of clocks wherein the DLL circuitry employs a phase detector according to embodiments of the present invention to conserve power and to reduce phase jitter.