Semiconductor junction model and method for use in a circuit modeling tool

A semiconductor junction (13) is represented as a junction capacitance (21) in parallel with a junction resistance (23) and junction inductance (22). The junction capacitance, junction resistance and junction inductance are functions of the voltage across the semiconductor junction and are determined using a probability of charge stored across the semiconductor junction. Junction parameters are determined with parameter extraction processes. A circuit simulation tool is used to simulate the performance of a circuit that includes the semiconductor junction. Accordingly, diode junctions are more accurately modeled above their built-in potential and below their reverse break-down voltage.

FIELD OF THE INVENTION 
This invention relates in general to the field of circuit simulation, in 
particular to models of semiconductor devices and more particularly to 
models of semiconductor junctions for use in circuit simulation. 
BACKGROUND OF THE INVENTION 
Circuit simulation tools are used to predict the performance of a circuit. 
Circuit simulation tools use models of semiconductor devices to predict 
the performance of the semiconductor devices within the circuit. Typical 
semiconductor device models include the parasitic effects of the 
semiconductor substrate around the semiconductor junction, but do not 
accurately model the semiconductor junction itself. Diode models, for 
example, currently in use throughout the semiconductor industry, 
incorrectly determine the junction capacitance at applied junction 
voltages above the built-in potential and below the reverse break-down 
voltage. This results in large signal simulation errors due to incorrect 
charge distribution and the associated conservation of that charge within 
the junction. Further, the currently used junction models do not account 
for the associated variation in junction inductance about the built-in 
potential and reverse-breakdown. This also leads to large signal 
simulation errors because the energy stored in the form of magnetic fields 
and the associated conservation of the magnetic flux is not considered. 
Under forward conduction well above the built-in potential, and under 
reverse breakdown well below the reverse breakdown voltage, typical 
semiconductor junction models incorrectly predict exponential growth of 
charge carriers and the associated current with increases in applied 
junction voltage. 
Thus what is needed is an improved method for estimating the performance of 
a semiconductor junction and an improved circuit model that represents a 
semiconductor junction. What is also needed is a method and circuit model 
that more accurately predicts the junction capacitance at junction 
voltages above the built-in potential of the junction and at junction 
voltages below the reverse break-down voltage of the junction. What is 
also needed is a method and circuit model that takes into account the 
charge distribution and the associated conservation of that charge within 
the junction. What is also needed is a method and circuit model that takes 
into account variation in junction inductance about the built-in potential 
and reverse-breakdown. What is also needed is a method and circuit model 
that takes into account the energy stored in the form of magnetic fields 
and the associated conservation of the magnetic flux within the 
semiconductor junction. What is also needed is a method and circuit model 
with improved large-signal performance predictability. What is also needed 
is a method and circuit model that more accurately predicts charge 
carriers and the associated current with increases in applied junction 
voltage. 
What is also needed is an improved circuit simulation tool that more 
accurately predicts the junction capacitance, junction resistance and 
junction inductance at junction voltages above the built-in potential of 
the junction and at junction voltages below the reverse break-down voltage 
of the junction.

The exemplification set out herein illustrates a preferred embodiment of 
the invention in one form thereof, and such exemplification is not 
intended to be construed as limiting in any manner. 
DETAILED DESCRIPTION OF THE DRAWINGS 
The present invention provides, among other things an improved method for 
estimating the performance of a semiconductor junction and an improved 
circuit model that represents the semiconductor junction. In accordance 
with the preferred embodiments, the semiconductor junction is represented 
as a junction capacitance in parallel with a junction resistance and 
junction inductance. The junction capacitance, junction resistance and 
junction inductance are functions of the voltage across the semiconductor 
junction and are determined using a probability of charge stored across 
the semiconductor junction. Junction parameters are determined with 
parameter extraction processes. A circuit simulation tool is used to 
simulate the performance of a circuit that includes the semiconductor 
junction. Accordingly, diode junctions are more accurately modeled above 
their built-in potential and below their reverse break-down voltage. 
The present invention also provides a method and circuit model that more 
accurately predicts the junction capacitance at junction voltages above 
the built-in potential of the junction and at junction voltages below the 
reverse break-down voltage of the junction. The present invention also 
provides a method and circuit model that takes into account the charge 
distribution and the associated conservation of that charge within the 
junction. The present invention also provides a method and circuit model 
that takes into account variation in junction inductance about the 
built-in potential and reverse-breakdown. The present invention also 
provides a method and circuit model that takes into account the energy 
stored in the form of magnetic fields and the associated conservation of 
the magnetic flux within the semiconductor junction. The present invention 
also provides a method and circuit model with improved large-signal 
performance predictability. The present invention also provides a method 
and circuit model that more accurately predicts charge carriers and the 
associated current with increases in applied junction voltage. 
The present invention also provides an improved circuit simulation tool 
that more accurately predicts the junction capacitance, junction 
resistance and junction inductance at junction voltages above the built-in 
potential of the junction and at junction voltages below the reverse 
break-down voltage of the junction. 
FIG. 1 is a model of a semiconductor device that includes substrate 
parasitics. Semiconductor device model 10 includes resistance (R.sub.s) 11 
in series with inductance (L.sub.s) 12 in series with semiconductor 
junction 13. Semiconductor device model 10 also includes capacitance 
(C.sub.p) 14 in parallel with resistance (R.sub.p) 15 in parallel with 
junction 13. Resistance 11 is the conductor series parasitic resistance of 
the semiconductor device model 10. Inductance 12 is the conductor series 
parasitic inductance of diode model 10. Capacitance 14 is the substrate 
parallel parasitic capacitance of the substrate around the semiconductor 
junction of diode model 10. Resistance 15 is the substrate parasitic 
parallel resistance around the semiconductor junction of diode model 10. 
Although semiconductor junction 13 is shown as a diode with a forward bias 
junction for more positive voltages at node 17 than node 16, the present 
invention is also suitable for any semiconductor junction with either 
forward-bias or reverse-bias relative orientations. 
Device model 10 may be viewed as a complete semiconductor device model that 
takes into account the effects of the semiconductor substrate. When device 
model 10 is used in circuit simulation tools, a device voltage is applied 
across nodes 18 and 17 and a device current flows accordingly. The voltage 
across the semiconductor junction 13 is the voltage between nodes 16 and 
17 and the current through the semiconductor junction is the current that 
flows from node through junction 13. R.sub.s, L.sub.s, R.sub.p and C.sub.p 
are preferably determined experimentally but may also be estimated. 
FIG. 2 is a simplified model of a semiconductor junction in accordance with 
a preferred embodiment of the present invention. Semiconductor junction 
model 20 represents semiconductor junction 13 (FIG. 1) of semiconductor 
device 10 (FIG. 1). Model 20 comprises a junction capacitance (C.sub.j) 21 
in parallel with a junction resistance (R.sub.j) 23. In the preferred 
embodiment, model 20 also comprises a junction inductance (L.sub.j) 22 in 
series with the junction resistance 23 and in parallel with the junction 
capacitance 21. The junction capacitance 21, the junction resistance 23 
and the junction inductance 22 are functions of the junction voltage. The 
junction voltage (V.sub.j) is the voltage potential between nodes 24 and 
25 and the junction current (I.sub.j) is the current that flows from node 
24 to node 25. Nodes 16 and 17 of junction model 20 correspond with nodes 
16 and 17 respectively of device model 10 (FIG. 1). The junction 
capacitance 21, the junction resistance 23 and the junction inductance 22 
are each preferably based on a probability of charge stored across the 
semiconductor junction. Accordingly, the performance of a circuit that 
includes junction 13 depends on the probability of charge stored across 
the semiconductor junction. 
Junction capacitance (C.sub.j) 21 is preferably calculated using the 
following equation: 
##EQU1## 
wherein: V.sub.j is the junction voltage across the semiconductor 
junction; 
C.sub.jo is a capacitance of the semiconductor junction at V.sub.j =0; 
P.sub..pi. (V.sub.j) is a cumulative probability of charge stored across 
the semiconductor junction as a function of the junction voltage; 
V.sub.Bi is a built in potential of the semiconductor junction; 
P.sub.Bf (V.sub.j)cum is a cumulative probability of forward conduction 
charge stored across the semiconductor junction as a function of the 
junction voltage; 
k is a predetermined constant, desirably greater than zero and preferably 
between one and ten; and 
M is a junction grading coefficient for the semiconductor junction. 
The junction resistance 23 (R.sub.j) is preferably calculated using the 
following equation: 
##EQU2## 
wherein R.sub.jo is a measured resistance of the semiconductor junction at 
V.sub.j =0. R.sub.jo may be a function of the junction voltage depending 
on the fabrication method and type of semiconduction junction. 
The junction inductance 22 (L.sub.j) is preferably calculated with the 
following equation: 
EQU L.sub.j (V.sub.j)=L.sub.MaxR P.sub.Br (V.sub.j)+L.sub.MaxF P.sub.Bf 
(V.sub.j) 
wherein: 
P.sub.Bf (V.sub.j) is a probability function for forward conduction charge 
stored across the semiconductor junction as a function of the junction 
voltage; 
P.sub.Br (V.sub.j) is a probability function for reverse breakdown charge 
stored across the semiconductor junction as a function of the junction 
voltage; 
L.sub.maxR is a reverse breakdown junction inductance when V.sub.j is a 
reverse breakdown voltage of the semiconductor junction; and 
L.sub.maxF is a forward junction inductance when V.sub.j is a built-in 
potential of the semiconductor junction. 
FIG. 3 illustrates normalized probability functions for charge across a 
semiconductor junction as a function of junction voltage. Probability 
function 31 (P.sub.Br (V.sub.j)) is a normalized probability function for 
reverse breakdown charge stored across the semiconductor junction as a 
function of the junction voltage. Probability function 32 (P.sub.Bf 
(V.sub.j)) is a normalized probability function for forward conduction 
charge stored across the semiconductor junction as a function of the 
junction voltage. Voltage 34 is the reverse bias breakdown voltage for the 
semiconductor junction. Voltage 35 is the forward bias voltage for the 
semiconductor junction. Although FIG. 3 illustrates voltages which are 
typical for silicon semiconductor junctions of N-type doping on P-type 
substrates, or vice-versa, other dopings and substrates, and other 
material semiconductor junctions including Gallium Arsenide (GaAs) are 
equally suitable for use with the present invention. 
Probability function 33 (P.sub..pi. (V.sub.j)) is a cumulative probability 
of charge stored across the semiconductor junction as a function of the 
junction voltage, and includes charge resulting from both forward 
conduction and reverse breakdown. P.sub..pi. (V.sub.j) is preferably 
calculated using the following equation: 
EQU P.sub..pi. (V)=P.sub.Br (V).sub.cum (1-P.sub.Bf (V).sub.cum) 
P.sub.Bfcum (V.sub.j) is a cumulative probability of forward conduction 
charge stored across the semiconductor junction as a function of the 
junction voltage. P.sub.Brcum (V.sub.j) is a cumulative probability of 
reverse breakdown charge stored across the semiconductor junction as a 
function of the junction voltage. To determine the cumulative 
probabilities, P.sub.Bfcum (V.sub.j) and P.sub.Brcum (V.sub.j), the 
probability functions are integrated from negative infinity to the 
junction voltage to determine the total charge stored about the 
semiconductor junction. For example, P.sub.Bfcum (V.sub.j) and P.sub.Brcum 
(V.sub.j) may be calculated as follows: 
##EQU3## 
The probability functions P.sub.Bf (V.sub.j) and P.sub.Br (V.sub.j) are 
typical probability functions each having a mean value and a distribution 
(.sigma.). In the preferred embodiment, Gaussian probability functions are 
used. In other embodiments of the present invention, the probability 
function used depends on the way the semiconductor is formed as well as 
the type of semiconductor material. The mean value for probability 
function P.sub.Bf (V.sub.j) is the forward conduction voltage (V.sub.Bf) 
(built-in potential) of the semiconductor junction, and the mean value for 
probability function P.sub.Br (V.sub.j) is the reverse breakdown voltage 
(V.sub.Br) of the semiconductor junction. V.sub.Bf and V.sub.Br may be 
determined experimentally or may be approximated from known 
characteristics of the semiconductor junction. For silicon junctions, 
V.sub.Bf is typically around 0.6 volts and V.sub.Br is typically around 
-15.0 volts. The charge distributions (.sigma.) are determined 
experimentally. The forward bias charge distribution .sigma..sub.Bf is 
typically on the order 0.30 and the reverse bias charge distribution 
.sigma..sub.Br is typically on the order 0.10 for silicon semiconductor 
junctions. The forward bias and reverse bias charge distributions are 
preferably determined experimentally on an actual semiconductor junction 
such as a diode. 
L.sub.max and L.sub.maxF are preferably determined experimentally and 
determined from a combination of the junction capacitance and reactance 
curves of the semiconduction junction. L.sub.maxR is typically on the 
order of 1.5 nH and L.sub.maxF is typically on the order of 0.9 nH for 
silicon semiconductor junctions. 
Thus, a semiconductor junction model and method has been described which 
overcomes specific problems and accomplishes certain advantages relative 
to prior art methods and mechanisms. The improvements over known 
technology are significant. For example, the method and model for the 
semiconductor junction predicts exponential carrier relationships up to 
and just beyond the built-in potential and reverse breakdown voltages and 
transitions to substantially linear relationships thereafter due to 
parasitic effects of the extrinsic model (e.g., model 10 of FIG. 1) 
resulting in improved prediction capability for large signal applications. 
The model and method of the present invention is based on actual diode 
physical parameters, which are either calculated or measured and parameter 
extracted. The model and method of the present invention account for the 
operation of the semiconductor junction from forward burnout to reverse 
burnout using physically based derivations and physical parameters that 
are determined by measurement. The model and method of the present 
invention includes a junction inductance provided for improved 
simulations, especially for performance of Nth order intermodulation 
products. 
The foregoing description of the specific embodiments will so fully reveal 
the general nature of the invention that others can, by applying current 
knowledge, readily modify and/or adapt for various applications such 
specific embodiments without departing from the generic concept, and 
therefore such adaptations and modifications should and are intended to be 
comprehended within the meaning and range of equivalents of the disclosed 
embodiments. 
It is to be understood that the phraseology or terminology employed herein 
is for the purpose of description and not of limitation. Accordingly, the 
invention is intended to embrace all such alternatives, modifications, 
equivalents and variations as fall within the spirit and broad scope of 
the appended claims.