Information processing apparatus and context switching method

An information processing apparatus which, when executing a plurality of predetermined units of processing, executes the predetermined units of processing in parallel by a processor by switching between contexts associated with the respective predetermined units. The processing apparatus comprises a plurality of register banks that respectively store the contexts associated with the respective predetermined units of processing, the processor that, after the context switching, executes processing associated with a foreground context, and a save/restore controller that, in parallel with the processor executing the processing associated with the foreground context, saves a background context to memory and restores the context of a unit of processing to be executed the next time from the memory to a background register bank.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority from Japanese Patent Application No. 2004-274219 filed on Sep. 21, 2004, which is herein incorporated by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an information processing apparatus and a context switching method.

2. Description of the Related Art

In recent years, computer systems that are embedded iii various machines and apparatuses and perform control tc) realize specific functions, so-called embedded systems, have been drawing attention, and their application to personal computer peripherals, audio-video equipment, electric appliances, and the like has been spreading rapidly. Moreover, so-called real-time capability to respond and process in a given time period after accepting a request to process is required of software (embedded software) for use in embedded systems. Hence, for embedded systems, a real-time operating system (hereinafter, called a “real-time OS”) is often adopted.

As mentioned above, the real-time OS must ensure a response in a given time period, and hence adopt a multithread function or a multitask function as indispensable technology. The multithread function is a function wherein in a processor such as a CPU or MPU, one application process is divided into threads that are units of processing thereof and the execution rights of the threads are switched thereby processing the threads in parallel. The multitask function is a function wherein in a processor, each thread is further divided into a plurality of tasks that are units of processing and the execution rights of the plurality of tasks are switched thereby processing the tasks in parallel.

When a plurality of units of processing (threads, tasks processes, or the like) are switched, “contexts” for use in the units of processing are usually switched. Note that the context is associated with a respective unit of processing and includes current flag status of a register set (general purpose registers, status registers, a program counter, and the like) and information for execution of the unit of processing. The definition of the context is according to that described in Michael Barr, “Programming Embedded Systems with C and C++”, Ohm-sha, Ltd., April 2000, pp. 180-181 (or O'Reilly, January 1999).

FIG. 9is a diagram for explaining the operation of context switching in a conventional embedded system (hereinafter, called “conventional example 1”). As shown in the Figure, the conventional embedded system essentially comprises a CPU10, a register bank11that stores a context, and a memory12external to the CPU10for saving/restoring contexts. After accepting a request to switch contexts from the real-time OS (step0), the CPU10saves a context A now being executed from the register bank11into the memory12by a store instruction (step1). Then, the CPU10restores a next context B from the memory12and updates the contents of the register bank11therewith by a load instruction (step2). Such a conventional example 1 is disclosed in, for example, Japanese Patent Application Laid-Open Publication No. H09-212371.

FIG. 10is a diagram for explaining the operation of context switching in another conventional embedded system (hereinafter, called “conventional example 2”). As shown in the Figure, the conventional embedded system essentially comprises a CPU10, a plurality of register banks11that are associated with and exclusively used by respective tasks, a selector13that selects one of respective contexts stored in the plurality of register banks11. Here, assume that the CPU10is executing a task A with a context A stored in a register bank11(#0) via the selector13(step0). After accepting a request to switch contexts from the real-time OS, the CPU10selects a register bank11(#1) storing a context B with the selector13(step1). As a result, context switching from context A to context B is carried out (step2). That is, in conventional example 2, without saving/restoring a context into/from an external memory, context switching is carried out only by switching the register banks11. Such conventional example 2 is disclosed in, for example, Japanese Patent Application Laid-Open Publication No. H07-141208.

FIG. 11shows how contexts A to C associated with respective tasks A to C are also switched as the tasks A to C are switched according to a given task scheduling (of A to B to C to A to . . . ) in conventional example 1 ofFIG. 9. In conventional example 1, when switching contexts, the CPU10saves the status of the context currently granted an execution right into the memory12by a store instruction, and restores the status of a context to be granted an execution right from the memory12by a load instruction.

That is, in conventional example 1, the CPU10saves/restores contexts by repeating execution of a store instruction/load-instruction. As a result, context switching takes some time (overhead), and accordingly responsiveness in task switching and execution, so-called real-time capability is poorer. Furthermore, the CPU10cannot execute another application during the saving/restoring, thus affecting adversely the real-time capability.

Meanwhile, in conventional example 2 ofFIG. 10saving/restoring of contexts into/from an external memory is not performed, and accordingly high-speed context switching can be achieved. However, a hardware resource usually provided as register banks is limited, and thus this configuration is hardly realistic for other than embedded systems on a relatively small scale with a small number of contexts to be handled.

SUMMARY OF THE INVENTION

To solve the above problem, according to a main aspect of the present invention there is provided an information processing apparatus which, when executing a plurality of predetermined units of processing, executes the predetermined units of processing in parallel by switching between contexts associated with the respective predetermined units, the processing apparatus comprising a plurality of register banks; that respectively store the contexts associated with the respective predetermined units of processing, a processor that, in the context switching, grants a right of execution to a context stored in one of the plurality of register banks and executes a unit of processing associated with the context having the right of execution granted, and a save/restore controller that performs saving and restoring wherein the saving executes to read out a context having handed over the right of execution from one of the other register banks than the one register bank storing the context having the right of execution granted and write into a memory accessible by the processor, and the restoring executes to read out a context to be granted the right of execution the next time from the memory and write into the one of the other register banks.

According to the present invention, there is provided an information processing apparatus and its context switching method suitable for a real-time system.

Features and objects of the present invention other than the above will become clear by reading the description of the present specification with reference to the accompanying drawings.

DETAILED DESCRIPTION OF THE INVENTION

At least the following matters will be made clear by the explanation in the present specification and the description of the accompanying drawings.

<Basic Configuration/Operation of an Information Processing Apparatus>

FIG. 1illustrates the configuration of an information processing apparatus200according to an embodiment of the present invention. The information processing apparatus200is embodied in the form of a semiconductor integrated circuit as an embedded system having incorporated therein a real-time OS (ITRON (Industrial TRON; TRON stands for “The Real-time Operating system Nucleus”), or the like) whose application to personal computer peripherals, audio-video equipment, electric appliances, and the like has been spreading in recent years.

Moreover, assume that in the information processing apparatus200, the multithread/multitask function is realized by the real-time OS. That is, when having a processor22execute predetermined units of processing (thread/task/process) in plurality, the information processing apparatus200switches contexts associated with the respective units of processing, each of the contexts including current flag status of a register set (general-purpose registers status registers, a program counter, and the like) and information for execution of the unit of processing, thereby having the processor21execute the plurality of units of processing in parallel.

The information processing apparatus200comprises the processor21, two register banks20(#0, #1), a first selector22, a second selector23, a storage element24, an inverter element25, a save area address register26, a restore area address register27, and a save/restore controller28. Note that a memory29may be provided external to the information processing apparatus200or incorporated in the information processing apparatus200.

The two register banks20(#0, #1) are each a register file group managed as a bank, and store a context that is in a state of being granted a right of execution by the processor21and a context to be saved/restored, respectively. As such the information processing apparatus200is configured simply to have two register banks20.

The two register banks20(#0, #1) have a configuration as shown inFIG. 2, for example. As shown inFIG. 2, the two register banks20(#0, #1) each comprise a first general-purpose register set made up of A, B, C, D, E, H, L registers and a flag register F; a second general-purpose register set that is alternative to the first general-purpose register set; and a specific-purpose register set made up of an interrupt vector I, a memory refresh R, index registers IX, IY, a stack pointer SP, and a program counter PC. That is, in the context switching, one of the first and second general-purpose register sets is selected as a foreground register bank and the other is selected as a background register bank. Meanwhile, the specific-purpose register set is unchanged.

The processor21is in charge of general CPU basic processing such as instruction fetch, instruction decoding, instruction execution, the writing back of execution results, and the like. The processor21comprises an arithmetic logic unit that performs arithmetic/logic operations, an instruction decoder that decodes instructions read out from the memory29, register sets that stores a context being currently executed in the processor21, a memory access unit that controls access to the memory29associated with the store-instruction/load-instruction, and an interrupt controller that controls hardware/software interruptions.

That is, the processor21has the configuration of a general microcomputer such as a Z80-based microcomputer. Note that the above configuration of the processor21is described in, for example, Shinichi Jinpo, “Latest Microprocessor Technology”, Nikkei Business Publications, Inc., December 1999, p. 259,FIG. 1.

Furthermore, the processor21performs the following processing to implement the multithread/multitask function under the real-time OS environment. When performing context switching in association with the switching of units of processing, the processor21grants an execution right to the context stored in one of the two register banks20(#0, #1) and executes the unit of processing associated with the context having the execution right granted.

When switching contexts, the processor21sends a select instruction to the first and second selectors22,23, a save area address to the save area address register26, a restore area address to the restore area address register27, and a save/restore start signal to the save/restore controller28.

Hereinafter, a context having the execution right granted by the processor21and being currently used by the processor21is called a “foreground context”, and a register bank20storing the foreground context is called a “foreground register bank”. And a context having handed over the execution right and to be used in the future by the processor21is called a “background context”, and a register bank20storing the background context is called a “background register bank”.

The first selector22selects a foreground register bank storing a foreground context to be granted an execution right from the two register banks20(#0, #1) according to a first select signal generated based on a select instruction from the processor21, and supplies the foreground context to be granted an execution right to the processor21.

The second selector23selects a background register bank storing a background context to be saved/restored from the two register banks20(#0, #1) according to a second select signal generated based on the select instruction from the processor21, and allows the background context to be transferred between the background register bank and the save/restore controller28.

The storage element24is for holding the state of the select instruction output from the processor21to the first and second selectors22,23until the next select instruction is generated. The select instruction held in the storage element24is the first select signal for the first selector22, and a signal that the first select signal is inverted into by the inverter element25is the second select signal for the second selector23. The storage element24may be, for example, a flip flop element.

The inverter element25is provided to have the first and second selectors22,23select respective ones of the two register banks20(#0, #1), that is, the foreground register bank and the background register bank such that they do not select the same register bank. That is, by providing the inverter element25, it can be certainly avoided that the first and second selectors22,23select the same register bank20conflictingly.

The save area address register26stores the save area address of the memory29to which a to-be-saved contexts designated by the processor21is written.

The restore area address register27stores the restore area address of the memory29from which a to-be-restored context designated by the processor21is read out.

As such, the save area address register26and the restore area address register27are separate. Hence, the processor21can freely designate the save area address and the restore area address.

The save/restore controller28reads out a background context having handed over the execution right from the background register bank20, which is the other than the foreground register bank20storing a foreground context, and writes into the memory29at the save area address designated by the save area address register26(saving). Then, the controller28reads out a context to be granted an execution right the next time from the memory29at the restore area address designated by the restore area address register27and writes into the background register bank20(restoring).

When receiving a save/restore start signal from the processor21, the save/restore controller28saves and/or restores a background context between the background register bank selected by the second selector23and the memory29.

Furthermore, in parallel with the unit of processing associated with the foreground context being executed by the processor21, the save/restore controller28saves and/or restores the background context. For example, during the time when a task A of a context A is being executed by the processor21, the save/restore controller28saves the context C of a task C that was being executed in the preceding time period and restores the context of a task B to be executed in the next time period.

Incidentally, the save/restore controller28may be embodied to be divided into a save controller that performs only saving and a restore controller that performs only restoring. That is, since the saving and the restoring are carried out by respective dedicated controllers, the saving and the restoring are each improved in degrees of freedom.

Adopted as the memory29is, for example, a main memory (SDRAM, DRAM, or the like) directly accessible by the processor21. That is, compared with the background register bank20, the memory29is slower in write/read speed and larger in storage capacity. Alternatively, a cache memory provided in between the processor21and the main memory may be adopted as the memory29.

Note that the storage area provided by the memory29is partitioned into areas to respectively store contexts associated with a respective plurality of units of processing. Moreover, the processor21is in charge of address management for the partitioned areas, and with the addresses, the save area address and the restore area address can be designated. As a result, the save/restore controller28saves/restores a context into/from the memory29in an ordered manner. Also, without a need to manage the addresses of the memory29, the save/restore controller28can dedicate itself to saving/restoring accordingly.

===Basic Operation of the Information Processing Apparatus===

The basic operation of the information processing apparatus200will be described based onFIGS. 3,4.FIGS. 3,4show the case where in one processor21, tasks A, B, C are executed according to a round-robin method periodically in predetermined periods and in a predetermined order (A to B to C to A to . . . ).

Referring toFIG. 3, in step1, the register bank20(#0) and the register bank20(#1) are already selected respectively as the foreground register bank20and the background register bank20, and the processor21executes task A with context A stored in the register bank20(#0) (step1).

Then, in response to an instruction from the multitask OS to switch contexts (context A to B), the processor21selects the register bank20(#1) as the foreground register bank20, and stores context B therein. Then, the processor21executes task B with context B stored in the register bank20(#1). Also in parallel with the execution of task B, the processor21supplies an address A designating the save area for context A to the save area address register26. As a result, the save/restore controller28reads out the context A from the register bank20(#0) as the background register bank20and writes the context A into the save area of the memory29designated by the address A stored in the save area address register26(step2).

Likewise, in response to the next instruction from the multitask OS to switch contexts (context B to C), the processor21selects the register bank20(#0) as the foreground register bank20, and stores context C therein. Then, the processor21executes task C with context C stored in the register bank20(#0). Also in parallel with the execution of task C, the processor21supplies an address B designating the save area for context B to the save area address register26. As a result, the save/restore controller28reads out the context B from the register bank20(#1) as the background register bank20and writes the context B into the save area of the memory29designated by the address B stored in the save area address register26(step3).

Further, in parallel with the execution of task C, the processor21supplies an address A of the memory29at which the context A is stored to the restore area address register27. As a result, the save/restore controller28reads out the context A from the memory29at the address A designated by the restore area address register27and updates the status of the register bank20(#1) with the context A (step4).

In response to the next instruction from the multitask OS to switch contexts (context C to A), the processor21executes task A, and in parallel therewith, the save/restore controller28saves context C to the memory29(step5). Further, the save/restore controller28restores context B from the memory29(step6).

In response to the next instruction from the multitask OS to switch contexts (context A to B), the processor21executes task B, and in parallel therewith, the save/restore controller28saves context A to the memory29(step7), and restores context C from the memory29(step8).

Referring toFIG. 4, (a) ofFIG. 4shows task switching points *, (b) ofFIG. 4shows transition of the status (task) of the foreground context being currently used in the processor21, (c) ofFIG. 4shows transition of the status (task) of the register bank20(#0), (d) ofFIG. 4shows transition of the status (task) of the register bank20(#1), (e) ofFIG. 4shows transition of the first select signal, (f) ofFIG. 4shows transition of the status (task) of the background context subject to saving/restoring, and (g) ofFIG. 4shows the type of access (Write/Read) to the memory29by the save/restore controller28.

For example, in the time period between task switching points *(1) and *(2) (see (a) ofFIG. 4according to the first select signal of (a) ofFIG. 4, the register bank20(#0) is selected as the foreground register bank20and according to the second select signal (not shown) that the first select signal is inverted into, the register bank20(#1) is selected as the background register bank20. During this time period, context C associated with task C is stored in the register bank20(#0), and the processor21executes task C with context C (see (c) ofFIG. 4).

In this time period, after writing context B associated with task B, which was being executed by the processor21in the preceding time period, from the register bank20(#1) into the memory29, the save/restore controller28reads out context A associated with task A to be executed the next time from the memory29and updates the status of the register bank20(#1) therewith (see (f), (g) ofFIG. 4).

Thereafter, at task switching point *(2), switching from task C to task A is performed. At this time, the register bank20(#1) and the register bank20(#0) are selected as the foreground register bank20and the background register bank20respectively.

Here, context A associated with task A is stored in the register bank20(#1), the processor21executes task A with context A (see (c) ofFIG. 4). Also, in parallel with the execution of task A by the processor21, after writing context C associated with task C, which was being executed by the processor21in the preceding time period, from the register bank20(#0) into the memory29, the save/restore controller28reads out context B of task B to be executed the next time from the memory29and updates the status of the register bank20(#0) therewith (see (f), (g) ofFIG. 4).

===Detailed Operation of the Information Processing Apparatus===

The detailed operation of the information processing apparatus200will be described based onFIG. 5.

In step1, the processor21executes task A with a context stored in the foreground register bank20(#0), and a context B1and stack pointer SP(B) of task B to be executed the next time are stored in the background register bank20(#1) (step1).

Then, the processor21appreciates a timer interruption through a timer interrupt signal generated by a timer (not shown) in the processor21. As a result, the processor21suspends task A being currently executed, the value PC(A) of the program counter at which the execution of task A is to be resumed and a context A0of task A are saved into the stack area for task A in the memory29(step2). And in the processor21, control is passed to a predetermined execution start address (interrupt vector) in a timer interrupt routine where the timer interrupt signal is cleared and the timer is reset and activated for the next timer interruption.

The processor21, in the above situation, executes the following context switching. That is, the processor21acquires the address (save area address SA) of the storage area to/from which the context of task A is saved/restored from a system area in the memory29. Then, the processor21supplies the acquired save area address SA to the save area address register26. And the save/restore controller28places the save area address SA stored in the save area address register26into its own save pointer register281.

Further, the processor21acquires the address (restore area address SC) of the storage area to/from which the context of task C is saved/restored from the system area in the memory29. Then, the processor21supplies the acquired restore area address SC to the restore area address register27. And the save/restore controller28places the restore area address SC stored in the restore area address register27into its own restore pointer register282. Then, the processor21updates task management information stored in the system area in the memory29for the next task and context switching (up to here, step3).

Then, the processor21supplies the select instruction to the first and second selectors22,23and the save/restore start signal to the save/restore controller28. As a result, the foreground register bank20(#0) storing a context A1(the rest of context except A0) of task A is changed by the first and second selectors22,23into a background register bank20(#0), and the background register bank20(#1) storing the context B1of task B is changed into a foreground register bank20(#1).

Then, the stack pointer SP(B) of task B is restored, and the stack area in the memory29that is used by the processor21switches to the stack area for task B designated by the stack pointer SP(B) (up to here, step4).

Then, the processor21executes a RTI (Return From Interrupt) instruction, thereby exiting the timer interrupt routine. At this time, a context B0and a program counter PC (B) of task B are read out from the stack area for task E, designated by the stack pointer SP(B) and stored into the foreground register bank20(#1) (step5). As a result, the processor21resumes the execution of task B (step6).

In parallel with the execution of task B by the processor21, the save/restore controller28saves the context A1of task A stored in the background register bank20(#0) into the save area for task A in the memory29designated by the save area address SA stored in the save pointer register281. At this time, the stack pointer SP(A) is also saved into the save area for task A in the memory29(up to here, step7).

Further, in parallel with the execution of task B by the processor21, the save/restore controller28re-stores a context C2of task C stored in the restore area for task C in the memory29designated by the restore area address SC stored in the restore pointer register282into the background register bank20(#0). At this time, the stack pointer SP (C) is also restored into the background register bank20(#0) (up to here, step8).

As above, according to the information processing apparatus200and the context switching method of the present invention, the save/restore controller28, a save/restore dedicated hardware separate from the processor21, saves the background context having handed over the execution right from the background register bank20into the memory29and restores the context to be granted a right of execution from the memory29into the background register bank20. Thus, the load on the processor21associated with the saving/restoring is reduced and the saving/restoring is speeded up.

In parallel with a unit of processing associated with the foreground context granted a right of execution being executed by the processor21, the save/restore controller28saves/restores. Thus, the processor21can execute a plurality of units of processing in parallel with switching between them in terms of the right of execution, without being affected by the time required for the context switching.

As such, according to the information processing apparatus200of the present invention, the total time required for executing a plurality of units of processing can be reduced and a high-performance real-time system excellent in the real-time capability can be realized.

<Other Configurations and Operations of the Information Processing Apparatus>

===Integration of the Address Registers===

With the above embodiment, consider the case where the memory29is partitioned according to a predetermined regularity into divisions for storing contexts respectively which divisions are such as units of, for example,64addresses placed consecutively. In this case, the save area address register26and the restore area address register27can be combined into one address register without a need to be separate.

That is, the processor21supplies either a save area address or a restore area address to the one address register. And the save/restore controller28can calculate the other address from the save area address or the restore area address stored in the one address register based on the predetermined regularity of the divisions of the memory29.

In the above case where the memory29is partitioned into divisions of, for example,64addresses, the save/restore controller28can obtain a restore area address by calculating a designated save area address plus64. Note that when calculating the first restore area address from the last restore area address, the overflow of the sum of the designated save area address plus64need only be masked.

As such, the save area address register26and the restore area address register27are combined into one address register, thereby reducing the circuit scale. Moreover, the processor21need only designate either save area addresses or restore area addresses in a predetermined order, accordingly reducing the load thereon.

===Selection of Modes for Saving/Restoring===

In the above embodiment, the processor21may supply the save/restore controller28with a mode selection signal to designate one of a first mode wherein the processor21executes saving and restoring consecutively, a second mode wherein the processor21executes only the saving, and a third mode wherein the processor21executes only the restoring. And the save/restore controller28selects one of the first to third modes according to the mode selection signal supplied from the processor21.

That is, as shown in steps1,2,3ofFIG. 3, at the initial and end stages of executing a plurality of units of processing in parallel, only the saving or the restoring is needed. Hence, by configuring the processor21to be able to designate one of the first to third modes, it does not happen to have the save/restore controller28perform wasteful processing.

===Saving/Restoring in an Idle Time Period===

In the above embodiment, the processor21may supply a status signal to indicate the status of access to the memory29by it to the save/restore controller28. And the save/restore controller28identifies idle time periods during which the processor21does not access the memory29on the basis of the status signal supplied from the processor21, and performs saving/restoring only during the idle time periods.

FIG. 6illustrates the operation of the information processing apparatus200when saving/restoring in idle time periods on the basis of the status signal. Here, (a) ofFIG. 6shows task switching points *, (b) ofFIG. 6shows transition of the status (task) of the foreground context being currently used in the processor21, (c) ofFIG. 6shows transition of the status (task) of the register bank20(#0), (d) ofFIG. 6shows transition of the status (task) of the register bank20(#1), (e) ofFIG. 6shows transition of the first select signal, (f) ofFIG. 6shows transition of the status signal, (g) ofFIG. 6shows transition of the status (task) of the background context subject to saving/restoring, and (h) ofFIG. 6shows the type of access (Write/Read) to the memory29by the save/restore controller28.

For example, before a task switching point *(0) (see (a) ofFIG. 6), the register bank20(#1) storing context A of task A is selected as the foreground register bank20, and the register bank20(#0) storing context B of task B is selected as the background register bank20. And the processor21executes task A with context A stored in the register bank20(#1) (see (b) ofFIG. 6).

Then, at the task switching point *(0), switching from task A to task B is performed, where the register bank20(#0) changes to the foreground register bank20, and the register bank20(#1) changes to the background register bank20.

At this time, context B associated with task B is stored in the register bank20(#0), and the processor21executes task B with context B (see (c) ofFIG. 6). In parallel with task B being executed by the processor21, the save/restore controller28writes context A of task A that was being executed in the preceding time period into the memory29, and reads out context C of task C to be executed the next time from the memory29and updates the status of the register bank20(#1) therewith.

Consider the case where, while writing context A into the memory29(saving), or while reading context C from the memory29(restoring), the save/restore controller28recognizes that the processor21is accessing the memory29on the basis of the status signal supplied from the processor21(see (f) ofFIG. 6). In this case, the save/restore controller28suspends the writing of context A into the memory29until an idle time period is recognized to appear again on the basis of the status signal supplied from the processor21(see (h) ofFIG. 6).

As such, the save/restore controller28is allowed to save/restore in idle time periods during which the processor21does not access the memory29. As a result, the save/restore controller28can save/restore without interrupting access to the memory29by the processor21.

In the above embodiment, while saving or restoring, the save/restore controller28may supply a busy signal indicating that saving/restoring is under way to the processor21. And the processor21delays the start of saving/restoring until the busy signal from the save/restore controller28is negated.

For example, the processor21refrains from supplying the save/restore start signal to the save/restore controller28until the busy signal is negated. As a result, the start of saving/restoring can be delayed. Alternatively, the save/restore controller28may be configured to not respond to the save/restore start signal from the processor21at all until the busy signal is negated. Also in this case, the start of saving/restoring can be delayed.

That is, in the time period that the processor21is executing a unit of processing with the foreground context the saving and restoring of the background contexts may not be finished. Accordingly, the processor21delays the start of saving/restoring until the busy signal indicating that saving/restoring is under way is negated, thereby avoiding the above incident.

Note that the save/restore controller28may perform saving/restoring with intentionally avoiding time periods of access to the memory29by the processor21on the basis of the status signal supplied from the processor21. That is access to the memory29by the processor21is prioritized over the saving/restoring. In this case, needless to say, the busy signal is not needed.

===Case Where Total Number of Tasks≦Total Number of Register Banks===

In the above embodiment, when the total number of units of processing to be executed in parallel is at or below the total number of register banks20, the processor21may supply a save/restore prohibition signal to prohibit the saving/restoring to the save/restore controller28. When receiving the save/restore prohibition signal from the processor21, the save/restore controller28does not perform the saving/restoring.

That is, when the total number of units of processing to be executed in parallel is at or below the total number of register banks20, there is no need to save/restore a context into/from the memory29. In this case, if prohibiting the saving/restoring, the processor21can perform context switching at high speed only by switching between the register banks20(the foreground and background register banks).

===Configuration with Three or More Register Banks===

In the above embodiment, interrupt control register banks30are further provided. Thus, three or more register banks (20,30) are provided in the information processing apparatus200.

FIG. 7illustrates the configuration of the information processing apparatus200further provided with two interrupt control register banks30(#0, #1) according to another embodiment of the present invention.FIG. 8illustrates the basic operation of the information processing apparatus200further provided with the two interrupt control register banks30(#0, #1). Here, (a) ofFIG. 8shows task switching points *, (b) ofFIG. 8shows timings * of accepting interruption for an interrupt factor X, (c) ofFIG. 8shows timings * of accepting interruption for an interrupt factor Y, (d) ofFIG. 8shows transition of the status (task) of the foreground context being currently used in the processor21, (e) ofFIG. 8shows transition of the status (task) of the register bank20(#0), (f) ofFIG. 8shows transition of the status (task) of the register bank20(#1), (g) ofFIG. 8shows transition of the status (interrupt factor X) of the interrupt control register bank30(#3), (h) ofFIG. 8shows transition of the status (interrupt factor Y) of the interrupt control register bank30(#4), (i) ofFIG. 8shows transition of the first select signal, (j) ofFIG. 8shows transition of the second select signal, (k) ofFIG. 8shows transition of the status (task) of the background context subject to saving/restoring, and (l) ofFIG. 8shows the type of access (Write/Read) to the memory29.

For example, between task switching points *(2) and *(4) (see (a) ofFIG. 8), the register bank20(#0) storing context C of task C is selected as the foreground register bank20, and the register bank20(#1) storing context B of task B is selected as the background register bank20.

Thus, the processor21executes task C with context C stored in the register bank20(#0) (see (d) ofFIG. 8). In parallel with task C being executed by the processor21, the save/restore controller28writes the context B of task B that was being executed in the preceding time period from the register bank20(#1) into the memory29, and reads out context A of task A to be executed the next time from the memory29and updates the status of the register bank20(#1) therewith (see (k), (l) ofFIG. 8).

Here, suppose that at timing *(3) of accepting interruption, the processor21accepts interruption due to the interrupt factor Y while executing task C (see (d) ofFIG. 8). At this time, the status of the interrupt control register bank30(#4) becomes a context Y associated with the interrupt factor Y without affecting the status of the register banks20(#0, #1) (see (h) ofFIG. 8).

That is, even if interruption due to the interrupt factor Y occurs, the status of the register bank20(#0) continues to be the context C of task C. Also, the save/restore controller28continues the saving of the context B into the memory29and the restoring of the context A from the memory29.

That is, by providing the interrupt control register banks30, even if interruption occurs in the processor21such as hardware interruption and software interruption (exception, watchdog timer, etc.), the save/restore controller28can continue to save/restore.

Although the preferred embodiments of the present invention have been described, the above embodiments are provided to facilitate the understanding of the present invention and not intended to limit the present invention. It should be understood that various changes and alterations can be made therein without departing from spirit and scope of the invention and that the present invention includes its equivalents.