Singulation of semiconductor dies with contact metallization by electrical discharge machining

A method of separating individual dies of a semiconductor wafer includes forming a metal layer on a first surface of a semiconductor wafer, the semiconductor wafer including a plurality of dies, separating the plurality of dies from one another, and electrical discharge machining the metal layer into individual segments each of which remains attached to one of the dies. A corresponding semiconductor die produced by such a method is also provided.

TECHNICAL FIELD

The present application relates to singulation of dies fabricated on a semiconductor wafer, in particular defect-free singulation of such dies.

BACKGROUND

Singulation (i.e. separation) of dies (chips) fabricated on a semiconductor wafer is conventionally performed by mechanical dicing (sawing), dry laser dicing, water-jet guided laser dicing, stealth dicing via pulsed laser or plasma dicing. In the case of thin dies with a thick backside metal layer needed for mechanical stabilization, the structuring of the backside metal stack composed of a variety of different metal layers such as Cu on the wafer is necessary prior to the separation of the semiconductor dies in order to avoid chipping and metal burr formation. This structuring of the thick backside metallization is typically done by pattern plating or wet etching, which are both limited to thin metal stabilization layers of approximately 20 μm to 40 μm thick. Wet chemical structuring of thick backside metal stacks with thicknesses of approximately 40 μm to 100 μm and larger is very expensive and results in lateral etching and hence non-perpendicular metal sidewalls. In the case of mechanical dicing, the sidewalls of the dies can be damaged with cracks which propagate during the sawing process.

In the case of laser-based dicing, the penetration depth of the laser radiation into the bulk semiconductor causes excessive heating of the underlying semiconductor dies. This excessive heating leads to chemical formation of metal-semiconductor compounds such as Cu-silicide on the sidewalls of the dies. The metal-semiconductor compound diffuses into the semiconductor bulk and degrades the electrical performance of the dies to be separated. The excessive heating resulting from laser-based dicing also causes localized melting of the backside metallization.

SUMMARY

According to an embodiment of a method of separating individual dies of a semiconductor wafer, the method comprises: forming a metal layer on a first surface of a semiconductor wafer, the semiconductor wafer including a plurality of dies; separating the plurality of dies from one another; and electrical discharge machining the metal layer into individual segments each of which remains attached to one of the dies. The metal layer can be electrical discharge machined into individual segments by positioning at least one electrode over a region of the metal layer between adjacent ones of the dies and applying high voltage, high frequency pulses to the at least one electrode and the metal layer sufficient to free metal ions from each region of the metal layer covered by the at least one electrode.

According to an embodiment of a semiconductor die, the die comprises a semiconductor substrate having a first surface, a second surface opposite the first surface, and sidewalls extending perpendicular between the first and second surfaces. The semiconductor die further comprises a metal layer covering the first surface of the semiconductor substrate. The metal layer has a first surface facing the first surface of the semiconductor substrate, a second surface opposite the first surface, and sidewalls extending perpendicular between the first and second surfaces. The sidewalls of the semiconductor substrate are devoid of metal-semiconductor compounds. The sidewalls of the metal layer are devoid of melted regions and burrs.

DETAILED DESCRIPTION

The embodiments described herein provide for structuring a metal layer disposed on a semiconductor wafer by electrical discharge machining, which involves removing metal by micro-sparking only in the region of the metal layer under the electrode used to implement the electrical discharge machining. The metal layer on the wafer can be realized by any standard metallization technique such as e.g. electrochemical deposition, PVD (physical vapor deposition), sputtering, etc. or by a attaching a metal foil to the semiconductor wafer by any standard attach techniques such as diffusion soldering, anodic bonding, glue attach, etc. prior to or after die singulation (i.e. separation).

FIG. 1, which includesFIGS. 1A through 1O, illustrates an embodiment of a method of separating individual dies (chips) of a semiconductor wafer by electrical discharge machining (also commonly referred to as micro-sparking).FIGS. 1A through 1Oshow respective partial cross-sectional views of a semiconductor wafer at different stages of the method.FIGS. 1A through 1Cillustrate purely optional steps for attaching a support substrate to the semiconductor wafer prior to the metal layer structuring. These optional steps are particularly useful for semiconductor wafers that are to be thinned e.g. to between 500 nm and 100 μm and/or for wafers that have kerf sites with test structures. The test structures in the kerf sites are used for process control and to predict the behavior of the dies, since the kerf sites are processed in the same environment and by the same methods as the dies.

InFIG. 1A, a second surface104of the semiconductor wafer100is coated by a positive resist106. The positive resist106is exposed using a photolithographic mask108with openings110and then developed to form a mask with openings112that expose test structures114of kerf sites116at the second surface104of the semiconductor wafer100. Alternatively, a negative resist could be used and exposed using a photolithographic mask with reversed polarity.

InFIG. 1B, the test structures114of the kerf sites116are removed e.g. by wet etching. In the case of copper-based test structures114, this can involve AlSiCu metal wet etching.

InFIG. 1C, any residual oxide118in the kerf sites116can be removed e.g. also by wet etching.

InFIG. 1D, the resist106is removed e.g. using NMP (1-methyl-2-pyrrolidon) and a support substrate120such as an adhesive film, glass carrier, ceramic, etc. is attached to the second surface104of the semiconductor wafer100e.g. by an adhesive122. An opposite first surface102of the semiconductor wafer100can be thinned e.g. to 40 μm or thinner if desired to yield thinner dies (chips). The first surface102of the wafer100corresponds to the backside of the dies according to this embodiment.

InFIGS. 1A through 1D, only a part of the semiconductor wafer100between two adjacent dies is shown for ease of illustration. The wafer100can include many dies as is standard practice in the semiconductor industry.

InFIG. 1E, the first surface102of the semiconductor wafer100is coated with a negative resist124. A mask126such as a Cr mask is positioned over the resist124and used to expose and develop the resist124to form a mask with openings128that expose dicing or sawing streets130between adjacent ones of the dies. Alternatively a positive resist could be used and exposed using a photolithographic mask with reversed polarity. The dicing/sawing streets130are regions of the semiconductor wafer100devoid of any devices pertaining to the individual dies, and represent regions of the wafer100to be singulated e.g. by sawing, laser ablation, etching, etc. in order to separate the individual dies.

InFIG. 1F, the individual dies have been singulated along the dicing/sawing streets130. Any standard die singulation process can be used to separate the individual dies. For example, the singulation process can be carried out in discrete etching steps followed by polymer deposition on the sidewalls132of the dies. The etching process can stop on the adhesive122or other material used to attach the semiconductor wafer100to the support substrate (if provided)120. The discrete application of a polymer134to the sidewalls132of the dies protects the die sidewalls132during the subsequent etching steps.

InFIG. 1G, the resist124and the polymer134on the sidewalls132of the dies have been removed by any suitable standard process such as etching.

InFIG. 1H, a metallization attach material136such as an adhesive, solder, an advanced diffusion soldering material like AuSn, etc. is provided on the first surface102of the semiconductor wafer100. In the case of an advanced diffusion soldering material, the metallization attach material136can be deposited by sputtering in a plasma environment into the singulation trenches138between adjacent ones of the dies.

InFIG. 1I, a metal layer140such as a metal foil is attached to the first surface102of the semiconductor wafer100by the metallization attach material136as indicated by the downward facing arrows inFIG. 1I. The metal layer140can comprise any standard metallization such as Cu, Mo, W, etc. or alloys thereof. Still other types of metal layers can be used. In general, the metal layer140is a covering piece of metal material that lies over at least part of the semiconductor wafer100. In the case of Cu material systems, the metal layer140can be attached to the first surface102of the semiconductor wafer100in a vacuum oven with formic acid pre-cleaning.

FIG. 1Jshows the case of the metal layer140attached to the first surface102of the semiconductor wafer100by advanced diffusion soldering. In this case, a thin metal layer (e.g. 1-10 μm thick) inter-diffuses with the metal layer140during a thermal process to yield an intermetallic compound layer with a re-melting temperature higher than the bonding temperature. CuSn and AuSn are common advanced diffusion soldering systems. Other advanced diffusion soldering systems may be used.

FIGS. 1K through 1Millustrate the process of electrical discharge machining the metal layer140into individual segments142each of which remains attached to one of the dies. InFIG. 1K, the metal layer140is immersed in a dielectric liquid144such as e.g. deionized water or a liquid containing hydrocarbons like e.g. kerosene. In some cases, the dielectric liquid144can be omitted. At least one electrode146is positioned over a region of the metal layer140between adjacent ones of the dies. InFIG. 1K, an array of electrodes146is positioned over each region of the metal layer140to be cut by micro-sparking. Alternatively, a single electrode146shaped to cover all regions of the metal layer140to be electrical discharge machined can be positioned over the wafer100.

In either case, high voltage, high frequency pulses are applied to each electrode146and the metal layer140. The voltage and frequency of the pulses are sufficient to free metal ions148from each region of the metal layer140covered by an electrode146. In one embodiment, the high voltage, high frequency pulses applied to each electrode146range between 1 mV and several kV and between 103Hz to 106Hz to cut through the metal layer140by micro-sparking.

Also inFIG. 1K, the electrodes146form the anode (+) for the electrical discharge machining process and the metal layer140forms the cathode (−). Sparking generated by the high voltage, high frequency pulses causes small erosion craters to form in the metal layer140, with the freed metal ions148being removed by the dielectric liquid144. Each electrode146is moved in a vertical direction (X) in the dielectric liquid144toward the first surface102of the semiconductor wafer100as the metal ions148are removed by the dielectric liquid144and dissolved. The vertical electrode movement is indicated by the downward facing arrows labeled ‘feed’ inFIG. 1K. In one embodiment, each electrode146moves toward the first surface102of the semiconductor wafer100at a constant feed speed which can be determined as a function of the micro-sparking voltage and frequency and the type of metal layer140being be electrical discharge machined.

FIG. 1Lshows the semiconductor wafer100as the electrical discharge machining process continues, with the electrodes146moving closer to the first surface102of the semiconductor wafer100as additional metal ions148continue to be freed from the metal layer140and removed by the dielectric liquid144. By applying a constant feed speed, the electrodes146move into the metal layer140and spark out metal ions and create deep trenches150in the metal layer140with smooth metal sidewalls152.

InFIG. 1M, the electrical discharge machining process stops when the electrodes146reach the previously created gap138between adjacent ones of the singulated (separated) dies. The micro-sparking stops once all metal directly under the electrodes146is removed.

FIG. 1Nshows the semiconductor wafer100after the electrical discharge machining process has completed. Each semiconductor die has a semiconductor substrate154with a first surface102, a second surface104opposite the first surface102, and sidewalls132extending perpendicular between the first and second surfaces102,104. A segment142of the metal layer140covers the first surface102of each individual semiconductor substrate154, and was previously segmented by the electrical discharge machining process. Each metal segment142has a first surface156facing the first surface102of the corresponding semiconductor substrate154, a second surface158opposite the first surface156, and sidewalls152extending perpendicular between the first and second surfaces156,158. The sidewalls132of each semiconductor substrate154are devoid of metal-semiconductor compounds. The sidewalls152of each metal segment142realized by the electrical discharge machining process are devoid of melted regions and burrs.

FIG. 1Oshows the post-electrical discharged machined semiconductor wafer after lamination and mounting of the structure to a frame160e.g. by an adhesive. The support substrate (if provided)120at the opposite side of the structure can be removed as indicated by the downward facing arrows shown inFIG. 1O.

FIG. 2, which includesFIGS. 2A through 2H, illustrates another embodiment of a method of separating individual dies (chips) of a semiconductor wafer100by electrical discharge machining.FIGS. 2A through 2Hshow respective partial cross-sectional views of a semiconductor wafer100at different stages of the method. The embodiment shown inFIG. 2is similar to the embodiment shown inFIG. 1, however, the dies are separated from one another after the metal layer140is electrical discharge machined into the individual segments142.

InFIG. 2A, the semiconductor wafer100is attached to a support substrate120e.g. after removal of kerf test structures if provided. Any standard support substrate120can be used such as an adhesive film, glass carrier, ceramic, etc. and attached to the second surface104of the semiconductor wafer100e.g. by an adhesive122. The opposite first surface102of the semiconductor wafer100can be thinned e.g. to 40 μm or thinner if desired to yield thinner dies. The first surface102of the wafer100corresponds to the backside of the dies according to this embodiment. InFIG. 1A, only a part of the semiconductor wafer100between two adjacent dies is shown for ease of illustration. The wafer100can include many dies as is standard practice in the semiconductor industry.

InFIG. 2B, a metallization attach material136such as an adhesive, solder, an advanced diffusion soldering material like AuSn, etc. is provided on the first surface102of the semiconductor wafer100. A metal layer140such as a metal foil is attached to the first surface102of the semiconductor wafer100by the metallization attach material136as indicated by the downward facing arrows inFIG. 2B. The metal layer140can comprise any standard metallization such as Cu, Mo, W, etc. or alloys thereof. Still other types of metal layers can be used. In general, the metal layer140is a covering piece of metal material that lies over at least part of the semiconductor wafer100. In the case of Cu material systems, the metal layer140can be attached to the first surface102of the semiconductor wafer100in a vacuum oven with formic acid pre-cleaning.

FIG. 2Cshows the case of the metal layer140attached to the first surface102of the semiconductor wafer100by advanced diffusion soldering. In this case, a thin metal layer (e.g. 1-10 μm thick) inter-diffuses with the metal layer140to yield an intermetallic compound layer as previously described herein.

FIGS. 2D through 2Fillustrate the process of electrical discharge machining the metal layer140into individual segments142each of which remains attached to one of the dies. InFIG. 2D, the metal layer140is immersed in a dielectric liquid144such as e.g. deionized water or a liquid containing hydrocarbons like e.g. kerosene. In some cases, the dielectric liquid can be omitted. At least one electrode146is positioned over a region of the metal layer140between adjacent ones of the dies. InFIG. 2D, an array of electrodes146is positioned over each region of the metal layer140to be cut by micro-sparking. Alternatively, a single electrode146shaped to cover all regions of the metal layer140to be electrical discharge machined can be positioned over the wafer100.

In either case, high voltage, high frequency pulses are applied to each electrode146and the metal layer140. The voltage and frequency of the pulses are sufficient to free metal ions148from each region of the metal layer140covered by an electrode146as previously described herein.

Also inFIG. 2D, the electrodes146form the anode (+) for the electrical discharge machining process and the metal layer140forms the cathode (−). Micro-sparking generated by the high voltage, high frequency pulses causes small erosion craters to form in the metal layer140, with the metal ions148being removed by the dielectric liquid144and dissolved. Each electrode146is moved in a vertical direction (V) in the dielectric liquid144toward the first surface102of the semiconductor wafer100as the metal ions148are removed by the dielectric liquid144. The vertical electrode movement is indicated by the downward facing arrows labeled ‘feed’ inFIG. 2D. Each electrode146can move toward the first surface102of the semiconductor wafer100at a constant feed speed as previously described herein.

FIG. 2Eshows the semiconductor wafer100as the electrical discharge machining process continues, with the electrodes146moving closer to the first surface102of the semiconductor wafer100as additional metal ions148are freed from the metal layer140and removed by the dielectric liquid144, forming deep trenches150in the metal layer140with smooth metal sidewalls152.

InFIG. 2F, the electrical discharge machining process stops when the electrodes146reach the first surface102of the semiconductor wafer100. The micro-sparking stops once all metal directly under the electrodes146is removed, including the advanced diffusion soldering layer136if provided.

InFIG. 2G, the individual dies are singulated along dicing/sawing streets130. The singulation process is indicated by downward facing arrows inFIG. 2G. The metal layer140is not cut during this process since the metal layer140was previously segmented by the electrical discharge machining process shown inFIGS. 2D through 2F. Any standard die singulation process can be used to separate the individual dies such as mechanical dicing, dry laser dicing, water-jet guided laser dicing, stealth dicing, plasma dicing, etc. For example, the singulation process can be carried out in discrete etching steps followed by deposition of a polymer134on the sidewalls132of the dies.FIG. 2Gshows the structure after one of the discrete etching/polymer deposition steps.

InFIG. 2H, the etching process stops on the adhesive122or other material used to attach the semiconductor wafer100to the support substrate (if provided)120. The discrete application of the polymer134to the sidewalls132of the dies protects the die sidewalls132during the subsequent etching steps. The polymer134on the sidewalls132of the dies can then be removed by any suitable standard process such as etching, and subsequent standard processing performed such as mounting of the final structure to a frame and removal of the support substrate (if provided)120e.g. as shown inFIG. 1O. Each resulting semiconductor die has a semiconductor substrate154with a first surface102, a second surface104opposite the first surface102, and sidewalls132extending perpendicular between the first and second surfaces102,104. A segment142of the metal layer140covers the first surface102of each individual semiconductor substrate154, and was previously segmented by the electrical discharge machining process. Each metal segment142has a first surface156facing the first surface102of the corresponding semiconductor substrate154, a second surface158opposite the first surface156, and sidewalls152extending perpendicular between the first and second surfaces158. The sidewalls132of each semiconductor substrate154are devoid of metal-semiconductor compounds. The sidewalls152of each metal segment142realized by the electrical discharge machining process are devoid of melted regions and burrs.

The electrical discharge machining process described herein is highly selective to metal (typically about 50 to 100 more times more selective on metal as compared to semiconductor materials such as Si, GaN, GaAs, etc.), and automatically stops after the metal layer140is completely segmented in the desired regions142. Metal is not evaporated as part of the electrical discharge machining process, but rather metal ions148are freed from the metal layer140in the desired regions by micro-sparking and dissolved in the dielectric liquid144. As such, the sidewalls132of the dies are devoid of metal-semiconductor compounds such as Cu-Silicide. Also, the sidewalls152of the trenches150formed in the metal layer140are devoid of melted regions and burrs by using electrical discharge machining because the electrical discharge machining process does not cause excessive localized heating of the metal sidewalls152.

The electrical discharge machining process described herein allows for patterning of very thick backside metals (e.g. 20 μm to 200 μm or even thicker). The electrical discharge machining process described herein can also be used for structuring thick metal layers on the frontside of semiconductor dies. That is, the metal layer140shown inFIGS. 1 and 2can be on the backside or frontside of the dies. In addition, the methods ofFIGS. 1 and 2can include forming an additional metal layer on the opposite surface of the semiconductor wafer100as the original metal layer140. Both (opposing) metal layers can be electrical discharge machined into individual segments each of which remains attached to one of the dies. This way, each die has a thick metal layer on both opposing main surfaces of the die that was processed by electrical discharge machining.

Patterning of semiconductor substrates in-situ (one equipment, one process step) is also possible with the electrical discharge machining process described herein. Each electrical discharge machining electrode146can be properly aligned with a corresponding kerf site116using any standard front-side or back-side alignment techniques such as optical inspection with cameras, backside inspection in the case of a glass support substrate120, etc. The electrical discharge machining process described herein can be adapted to any dicing process and any metal layer stacks deposited on a wafer backside or frontside. As a result, thick metal layers processed by the electrical discharge machining methods described herein have uniform properties post-processing such as uniform hardness, uniform crystallographic orientation of the metal grains, uniform elastic modulus, etc. By adjusting the micro-sparking parameters such as electrode voltage and/or frequency, cutting by micro-sparking can also be done through the semiconductor material (e.g. Si, SiC, GaN, GaAs, etc.) in order to separate the semiconductor dies.

The width of the trenches150formed in the metal layer140by the electrical discharge machining process described herein is determined by the electrode dimensions, and can be adjusted by using different electrode geometrical shapes and sizes. For example, a wider electrode146yields a corresponding wider trench150through the metal layer140. Conversely, a narrower electrode146yields a narrower trench150through the metal layer140. The angle and contour of the trench sidewalls152are also determined by the electrode dimensions. The sidewalls of the electrode146can extend generally perpendicular with respect to the first surface102of the semiconductor wafer100, yielding generally perpendicular trench sidewalls152in the metal layer140. The term ‘perpendicular’ as used herein with regard to the shape of the electrode146and trench sidewalls152refers to a direction perpendicular to the first surface102of the semiconductor wafer100. Alternatively, the electrode sidewalls can be angled to yield correspondingly angled trench sidewalls152in the metal layer140.

FIGS. 3A and 3Billustrate an embodiment of electrical discharge machining a metal layer140that covers at least part of a semiconductor wafer100into individual segments. According to this embodiment, at least one electrical discharge machining electrode146has a narrower (W1) first part200disposed closest to the metal layer140to be segmented and a wider (W2) second part202disposed further from the metal layer140than the first electrode part200. This way, a step204is formed in the metal layer140as the electrode146moves closer to the first surface102of the semiconductor wafer100as shown in the transition fromFIG. 3AtoFIG. 3B. The step204corresponds to the width difference between the first and second parts200,202of the electrode146. The electrode146can have other shapes and dimensions, depending on the trench profile to be formed in the metal layer140.