METAL-INSULATOR-METAL (MIM) CAPACITOR AND METHOD OF FORMING AN MIM CAPACITOR

A metal-insulator-metal (MIM) capacitor includes (a) a bottom electrode including (i) a bottom electrode plate and (ii) a bottom electrode cup formed from a conformal fill metal, (b) an insulator cup formed on the bottom electrode cup, (c) a top electrode formed in an opening defined by the insulator cup, and (d) a top electrode connection pad connected to the top electrode. The MIM capacitor may be formed concurrently with an interconnect structure including a lower interconnect element, an upper interconnect element, and interconnect via connected between the lower and upper interconnect elements. The bottom electrode plate and lower interconnect element may be formed in a lower metal layer, the top electrode connection pad and upper interconnect element may be formed in an upper metal layer, and the bottom electrode cup, insulator cup, top electrode, and interconnect vias may be formed between the lower and upper metal layers.

TECHNICAL FIELD

The present disclosure relates to metal-insulator-metal (MIM) capacitors formed in integrated circuit structures.

BACKGROUND

A metal-insulator-metal (MIM) capacitor is a capacitor constructed with a metal top plate, a metal bottom plate, and an insulator (dielectric) sandwiched between the two metal plates.

MIM capacitors are important components in many electrical circuits, for example many analog, mixed-signal, and radio-frequency complementary metal-oxide semiconductors (RF CMOS) circuits. MIM capacitors typically provide better performance than alternatives, such as POP (poly-oxide-poly) capacitors and MOM (metal-oxide-metal lateral flux) capacitors, due to lower resistance, better matching for analog circuits (e.g., matching device characteristics such as resistance and capacitance), and/or better signal/noise ratio.

MIM capacitors are typically constructed between two interconnect metal layers, referred to as metal layers Mxand Mx+1, for example, using an existing metal layer Mxas the bottom plate (bottom electrode), constructing a top plate (top electrode) with a different metal (e.g., titanium/titanium nitride (Ti/TiN), tantalum/tantalum nitride (Ta/TaN), or tungsten (W)), and connecting an overlying metal layer Mx+1(e.g., top metal layer) to the top and bottom plates by respective vias. The top plate typically has a higher resistance then than bottom plate, e.g., because the top plate may be limited by thickness constraints and the material of choice, thus limiting the performance of conventional MIM capacitors.

FIG. 1shows a side cross-sectional view of an example conventional MIM capacitor100built on a copper (Cu) interconnect. MIM capacitor100includes an insulator layer112formed between (a) a Cu bottom plate114formed in a metal layer Mxand (b) a metal top plate116, e.g., comprising tantalum (Ta), tantalum nitride (TaN), or titanium nitride (TiN)). A top plate cap118, e.g., comprising silicon nitride (SiN), may be formed over the metal top plate116. At least one photomask layer is used to form the metal top plate116, for example to provide a location to contact the bottom plate114, e.g., by the contact via(s)126discussed below.

The Cu bottom plate114and metal top plate116are each connected to a respective top metal connection pad120,122formed in a metal layer Mx+1by one or more respective vias124,126, for example by filling respective via holes with copper or other suitable metal. A dielectric barrier layer130may be formed over the top metal connection pads120and122. Insulator layer112also acts as a dielectric diffusion barrier for the copper of bottom plate114.

As used herein, a “via” refers to a conductive via formed by plugging or otherwise depositing a conductive material in a via hole having a small diameter or width, e.g., a diameter or width below 1 μm, and thus having a relatively large resistance, e.g., a resistance of at least 1 ohm per via. For example, conventional vias (e.g., contact vias124and126shown inFIGS. 1 and 2E) typically have a small diameter in the range of 0.1 μm to 0.5 μm, and may have a resistance of about 10 ohms/via, for example, especially for vias formed from tungsten or other highly resistive material. Thus, conventional MIM capacitors often include multiple vias (e.g., multiple vias between the top plate and top plate connection pad and/or multiple vias between the bottom plate and bottom plate connection pad) to reduce the overall resistance to some extent.

Conventional MIM capacitors, such as MIM capacitor100for example, are typically expensive to build, e.g., as compared with other certain types of capacitors. For example, MIM capacitors typically require additional mask layers and many additional process steps. In addition, conventional MIM capacitors, e.g., MIM capacitor100, typically require relatively large areas of silicon, resulting in inefficient area usage, particularly with large MIM capacitors. Further, in a conventional MIM capacitor, the top plate is thin and thus provides a high series resistance, as the vertical thickness of the top plate is limited by the vertical distance between the adjacent metal layers in which the MIM capacitor is formed (e.g., between metal layers Mxand Mx+1.).

There is a need for MIM capacitors that can be manufactured at lower cost, with fewer or no added mask layers (e.g., as compared with a background integrated circuit manufacturing process) and/or more efficient spatial construction.

SUMMARY

Examples of the present disclosure provide a three-dimensional (3D) MIM capacitor formed in an integrated circuit structure, and methods of forming such MIM capacitor. In some examples the MIM capacitor is formed concurrently with an interconnect structure using components of shared material layers. The interconnect structure may include a lower interconnect element, an upper interconnect element, and interconnect vias connected between the lower and upper interconnect elements. The MIM capacitor may include (a) a bottom electrode including a bottom electrode plate and a bottom electrode cup, (b) an insulator cup formed on the bottom electrode cup, (c) a top electrode formed in an opening defined by the insulator cup, (d) a dielectric etch stop layer covering the bottom electrode cup, insulator cup, and top electrode, and (e) a top electrode connection pad connected to the top electrode. The lower interconnect element and the bottom electrode plate of the MIM capacitor may be formed concurrently in the lower metal layer (Mx). The upper interconnect element, and the top electrode connection pad of the MIM capacitor may be formed concurrently in the upper metal layer (Mx+1). The interconnect vias, along with the bottom electrode cup, insulator cup, and top electrode of the MIM capacitor may be formed concurrently in a via layer between the lower and upper metal layers.

In some examples, the MIM capacitor may be formed without adding any photomask processes to the background manufacturing process for the relevant integrated circuit device. For example, in some examples the bottom electrode cup, the insulator cup, and top electrode may be formed in a tub opening using a damascene process.

One aspect provides a method of forming an MIM capacitor in an integrated circuit structure. A bottom electrode plate is formed in the lower metal layer (Mx). A dielectric layer is deposited over the bottom electrode plate, and patterned and etched to form (a) a tub opening over the bottom electrode plate, and (b) a bottom electrode via opening. A conformal fill metal (e.g., tungsten or other material suitable to form a conformal layer) is deposited in the tub opening and the bottom electrode via opening. An insulator layer is deposited over the conformal fill metal in the tub opening, followed by deposition of a top electrode layer over the insulator layer and extending into the tub opening. A chemical mechanical planarization (CMP) process is performed to remove upper portions of the top electrode layer, upper portions of the insulator layer, and upper portions of the metal fill material, such that (a) a portion of the metal fill material in the tub opening defines a bottom electrode cup, (b) a portion of the metal fill material in the bottom electrode via opening defines a bottom electrode via, (c) a portion of the insulator layer in the tub opening defines an insulator cup, and (d) a portion of the top electrode layer in the tub opening defines a top electrode. After the CMP process, a top electrode connection pad and a bottom electrode connection pad are formed in the upper metal layer. The bottom electrode connection pad is conductively connected to the bottom electrode cup through the bottom electrode via.

In one example, forming the bottom electrode plate in the lower metal layer comprises forming a metal silicide on a polysilicon region. Further, in some examples the top electrode connection pad is formed by a damascene process.

In another example, the lower metal layer comprises a metal interconnect layer.

In one example, depositing the conductive material comprises depositing a conformal fill metal between the lower metal layer and upper metal layer.

In one example, after forming the tub opening, the bottom electrode cup, the insulator cup, and the top electrode are formed without using any photomasks.

In one example, after the CMP process and before forming the top electrode connection pad in the upper metal layer, an etch stop layer is deposited over the bottom electrode cup, the insulator cup, and the top electrode.

In one example, the bottom electrode via opening is laterally spaced apart from the tub opening. In another example, the bottom electrode via opening is a laterally elongated opening extending laterally from the tub opening.

Another aspect provides a method of forming an integrated circuit structure including an MIM capacitor and an interconnect structure. A lower interconnect element and a bottom electrode plate are formed in the lower metal layer (Mx). A dielectric layer is deposited over the lower interconnect element and bottom electrode plate, and patterned and etched to form (a) a plurality of interconnect via openings over the lower interconnect element, (b) a tub opening over the bottom electrode plate, and (c) a bottom electrode via opening. A via fill metal, e.g., tungsten, is conformally deposited into the plurality of interconnect via openings, the tub opening, and the bottom electrode via opening. An insulator layer is deposited over the via fill metal in the tub opening. A top electrode layer is deposited over the insulator layer and extends into the tub opening. A CMP process is then performed to remove upper portions of the top electrode layer, insulator layer, and via fill material, such that (a) a portion of the via fill metal in each interconnect via opening defines an interconnect via, (b) a portion of the via fill metal in the tub opening defines a bottom electrode cup, (c) a portion of the vial layer in the bottom electrode via opening defines a bottom electrode via, (d) a portion of the insulator layer in the tub opening defines an insulator cup, and (e) a portion of the top electrode layer in the tub opening defines a top electrode. After the CMP process, an upper interconnect element, a top electrode connection pad, and a bottom electrode connection pad are formed in the upper metal layer above the lower metal layer. The bottom electrode connection pad is conductively connected to the bottom electrode cup through the bottom electrode via.

In one example, the lower metal layer comprises a silicided polysilicon layer, wherein the lower interconnect element comprises a first metal silicide region on a first polysilicon region and the bottom electrode plate comprises a second metal silicide region on a second polysilicon region.

In one example, the upper interconnect element, the top electrode connection pad, and the bottom electrode are formed by a damascene process.

In one example, the lower metal layer comprises a first metal interconnect layer (i.e., metal-1 layer).

In one example, after forming the tub opening, the bottom electrode cup, the insulator cup, and the top electrode are formed without using any photomasks.

In one example, after the CMP process and before forming the top electrode connection pad and the bottom electrode connection pad in the upper metal layer, an etch stop layer is deposited over the bottom electrode cup, the bottom electrode via, the insulator cup, and the top electrode.

Another aspect provides an integrated circuit structure including an MIM capacitor having (a) a bottom electrode including (i) a bottom electrode plate and (ii) a bottom electrode cup formed from a conformal fill metal, (b) an insulator cup formed on the bottom electrode cup, (c) a top electrode formed in an opening defined by the insulator cup, and (d) a top electrode connection pad connected to the top electrode.

In one example, the integrated circuit structure further includes an interconnect structure including a lower interconnect element, an upper interconnect element, and an interconnect via between the lower interconnect element and the upper interconnect element, wherein the bottom electrode cup and the interconnect via are formed in a common via layer from the conformal fill metal.

In one example, the lower interconnect element and the bottom electrode plate are formed in a lower metal layer, and the upper interconnect element and the top electrode connection pad are formed in an upper metal layer.

In one example, the lower metal layer comprises a silicide polysilicon layer, and the upper metal layer comprises a damascene metal layer.

In one example, the lower interconnect element and the bottom electrode plate are formed in a lower metal layer, and the upper interconnect element and the top electrode connection pad are formed in an upper metal layer above the lower metal layer. The bottom electrode cup, the insulator cup, and the top electrode may be formed between the lower metal layer and upper metal layer, e.g., in a tub opening formed in a via layer between the lower metal layer and upper metal layer.

In one example, the integrated circuit structure further includes a bottom electrode via and a bottom electrode connection pad connected to the bottom electrode via. The bottom electrode connection pad is conductively connected to the bottom electrode cup through the bottom electrode via, and the bottom electrode cup and the bottom electrode via are formed from the conformal fill metal.

In one example, bottom electrode via is laterally spaced apart from the bottom electrode cup. In another example, the bottom electrode via comprises a laterally elongated via extending laterally from the bottom electrode cup.

It should be understood that the reference number for any illustrated element that appears in multiple different figures has the same meaning across the multiple figures, and the mention or discussion herein of any illustrated element in the context of any particular figure also applies to each other figure, if any, in which that same illustrated element is shown.

DETAILED DESCRIPTION

The present disclosure provides for a three-dimensional (3D) MIM capacitor formed in an integrated circuit structure, and methods of forming such MIM capacitor. In some examples, the MIM capacitor may be formed without adding any photomask or photomask process, as compared with a background integrated circuit manufacturing process. In some examples the MIM capacitor is formed concurrently with an interconnect structure using components of shared material layers. The interconnect structure may include a lower interconnect element, an upper interconnect element, and a plurality of interconnect vias between the lower and upper interconnect layers. The MIM capacitor may include (a) a bottom electrode including a bottom electrode plate and a bottom electrode cup, (b) an insulator cup formed on the bottom electrode cup, (c) a top electrode formed in an opening defined by the insulator cup, (d) a dielectric etch stop layer covering the bottom electrode cup, insulator cup, and top electrode, and (e) a top electrode connection pad connected to the top electrode. The lower interconnect element and the bottom electrode plate of the MIM capacitor may be formed concurrently in the lower metal layer Mx. The upper interconnect element and the top electrode connection pad of the MIM capacitor may be formed in an upper metal layer Mx+1. The interconnect vias, and the bottom electrode cup insulator cup, and top electrode, and bottom electrode via may be formed concurrently in a via layer between the lower and upper metal layers, e.g., using a damascene process.

As used herein, a “metal layer,” for example in the context of the lower metal layer Mxor upper metal layer Mx+1, may comprise any metal or metalized layer or layers, including (a) a metal interconnect layer, e.g., comprising copper, aluminum or other metal deposited by a subtractive patterning process (e.g., deposition, patterning, and etching of a metal layer) or using a damascene process, or (b) a silicide polysilicon layer including a number of polysilicon regions each having a layer or region of metal silicide formed thereon, or (c) any other patterned layer including at least one metal structure defining at least one component of a MIM capacitor. For example, in some examples the lower metal layer Mxmay be a silicided polysilicon layer and the upper metal layer Mx+1may comprise a first metal interconnect layer, often referred to as metal-1. In such examples, x=0 such that the lower metal layer Mx=M0and the upper metal layer Mx+1=M1(i.e., metal-1). Further, as used herein, an “interconnect structure,” e.g., in the context of the interconnect structures204,504,604, and704disclosed herein, may include any type or types of metal layers as defined above.

FIGS. 2A and 2Bcollectively show an example integrated circuit structure200including a MIM capacitor202and an interconnect structure204formed concurrently, according to one example. In particular,FIG. 2Ashows a top view of integrated circuit structure200, andFIG. 2Bshows a cross-sectional side view taken through line2B-2B shown inFIG. 2A. As discussed below with reference toFIGS. 4A-4G, in one example the MIM capacitor202may be constructed without adding any mask operations to the background integrated circuit fabrication process.

As shown inFIGS. 2A-2B, the interconnect structure204may include a lower interconnect element310formed in a lower metal layer Mx(for example, where x=0 for a silicided polysilicon layer as discussed above) and an upper interconnect element312, e.g., metal-1 layer, formed in an upper metal layer Mx+1and connected to the lower interconnect element310by at least one interconnect via314formed in a via layer Vxby depositing a conformal via material, e.g., tungsten, into respective via openings.

Each of the lower interconnect element310and upper interconnect element312may comprise a wire or other laterally elongated structure, or a discrete pad (e.g., having a square or substantially square shape from a top view), or any other suitable shape and structure.

The MIM capacitor202includes a bottom electrode320, a top electrode322, and an insulator cup324sandwiched between the bottom electrode320and top electrode322. The MIM bottom electrode320includes (a) a bottom electrode plate326formed in the lower metal layer Mxand (b) a bottom electrode cup328formed on the bottom electrode plate326. The bottom electrode plate326is formed in the lower metal layer Mx, e.g., as discussed below in more detail.

Lower interconnect element310comprises a first metal silicide region346aformed on a first polysilicon region344a, and bottom electrode plate326comprises a second metal silicide region346bformed on a second polysilicon region344b. The bottom electrode cup328is formed on the bottom electrode plate326and includes (a) a laterally-extending bottom electrode cup base330and (b) multiple vertically-extending bottom electrode cup sidewalls332extending upwardly from the laterally-extending bottom electrode cup base330. The bottom electrode cup328may formed concurrently with the at least one interconnect via314by depositing the conformal via material, e.g., tungsten, into a tub opening formed in the via layer Vx.

The bottom electrode cup base330may have a rectangular perimeter (e.g., having a square or non-square rectangular shape) defining four lateral sides when viewed from above, with four vertically-extending bottom electrode cup sidewalls332extending upwardly from the four lateral sides of the rectangular perimeter, as shown inFIGS. 2A and 2Bviewed collectively. In another example, the bottom electrode cup328may include two vertically-extending bottom electrode cup sidewalls332extending upwardly from two opposing lateral sides of the bottom electrode cup base330, for example the two bottom electrode cup sidewalls332visible in FIG.2B. The bottom electrode cup328may include any other number of vertically-extending bottom electrode cup sidewalls332extending upwardly from the bottom electrode cup base330.

The laterally-extending bottom electrode cup base330and vertically-extending bottom electrode cup sidewalls332define an interior opening336of the bottom electrode cup328. As shown, the insulator cup324is formed in the interior opening336of the bottom electrode cup328and has a cup-shape including a laterally-extending insulator cup base340, formed over the bottom electrode cup base330, and multiple vertically-extending insulator sidewalls342extending upwardly from the laterally-extending insulator cup base340, with each vertically-extending insulator sidewall342formed on (laterally adjacent) a respective bottom electrode cup sidewall332. Insulator cup324may comprise silicon nitride (SiN) with a thickness of about 500 Å. Alternatively, insulator cup324may comprise Al2O3, ZrO2, HfO2, ZrSiOx, HfSiOx, HfAlOx, or Ta2O5, or other suitable capacitor insulator material.

The top electrode322is formed inside the insulator cup324, and covers the insulator cup base340and is laterally adjacent the multiple vertically-extending insulator sidewalls342, so as to fill the interior opening336. The top electrode322may comprise Al, Ti, TiN, W, TiW, Co, Ta, TaN, Cu, or any combination thereof, for example, TiN plus Al, TiN plus W, or a Ta/TaN bilayer plus Cu.

The MIM capacitor202also includes a top electrode connection pad358and a bottom electrode connection pad360formed in the upper metal layer Mx+1. The top electrode connection pad358may be formed directly on the top electrode322. The bottom electrode connection pad360may be connected to the bottom electrode plate326by a bottom electrode via362. In the example shown inFIGS. 2A-2BandFIGS. 4A-4H, the bottom electrode via362may be formed laterally spaced apart from the bottom electrode cup328, and may have a shape and size similar to the interconnect via314, and may comprise multiple bottom electrode vias362. In another example, as shown inFIGS. 7A-7Bdiscussed below, a bottom electrode via362′ may be formed as an extension of the bottom electrode cup328, which configuration provides a reduced electrical resistance between the bottom electrode cup328and the bottom electrode connection pad360, e.g., as compared with the examples shown inFIGS. 2A-2BandFIGS. 4A-4Hin which the electrical resistance between the bottom electrode cup328and bottom electrode connection pad360may be defined by the physical properties of the second metal silicide region346bof the bottom electrode326.

Each of the top electrode connection pad358and bottom electrode connection pad360may have any suitable shape and size. For example, each of the top electrode connection pad358and bottom electrode connection pad360may have a generally square shape in the x-y plane, e.g., as shown in the example top views shown inFIG. 2A,FIG. 3A, andFIG. 7A. In another example (not shown) each of the top electrode connection pad358and bottom electrode connection pad360may have a generally circular shape in the x-y plane. As another example, the top electrode connection pad358and/or bottom electrode connection pad360may be substantially elongated, e.g., running laterally across the wafer in the x-direction and/or the y-direction.

The top electrode322is capacitively coupled to both the bottom electrode cup base330and the bottom electrode cup sidewalls332of the bottom electrode cup328(which bottom electrode cup328is conductively coupled to the bottom electrode plate326), which defines a substantially larger area of capacitive coupling between the top electrode322and bottom electrode320, as compared with conventional designs. In particular, MIM capacitor202defines the following capacitive couplings between the top electrode322and bottom electrode320:

(a) capacitive coupling between the top electrode322and bottom electrode320by a displacement current path through the insulator cup base340and through the bottom electrode cup base330, as indicted by arrow350; and

(b) capacitive coupling between the top electrode322and bottom electrode320by a displacement current path through each vertically-extending insulator sidewall342and through the corresponding vertically-extending bottom electrode cup sidewall332, as indicated by arrow352.

The laterally-extending insulator cup base340effectively defines a plate capacitor, with the top and bottom plates extending horizontally (x-y plane), and each vertically-extending insulator sidewall342effectively defines an additional plate capacitor, with the top and bottom plates extending vertically (x-z plane or y-z plane). Thus, MIM capacitor202may be referred to as a “three-dimensional” or “3D” MIM capacitor.

The lower interconnect element310of interconnect structure204and the bottom electrode plate326of the MIM capacitor202may each comprise a lower metal structure380formed concurrently in the lower metal layer Mx. Similarly, the upper interconnect element312of interconnect structure204, and the top electrode connection pad358and bottom electrode connection pad360of the MIM capacitor202, may each comprise an upper metal structure384formed concurrently in the upper metal layer Mx+1.

Each of the lower metal layer Mxand upper metal layer Mx+1may comprise any metal or metalized layer or layers. For example, each of the lower metal layer Mxand upper metal layer Mx+1may comprise a copper or aluminum interconnect layer, bond pad layer, or other metal layer. As another example, the lower metal layer Mxmay be a silicided polysilicon layer (e.g., where Mxis M0), as discussed below.

Lower metal structures380and upper metal structures384may be formed in the lower metal layer Mxand upper metal layer Mx+1, respectively, in any suitable manner, for example using a subtractive patterning process (e.g., deposition, patterning, and etching of a metal layer), or using a damascene process, or by forming a metal silicide region on patterned polysilicon regions, or any other suitable process.

In the example implementation shown inFIG. 2B, lower metal structures380are formed in a silicided polysilicon layer Mx, wherein Mx=M0, and upper metal structure384are formed in a copper damascene layer Mx+1, wherein Mx+1=M1. Each lower metal structure380formed in the silicided polysilicon layer Mxcomprises a metal silicide region formed on a respective polysilicon region. In particular, and as described above, lower interconnect element310comprises a first metal silicide region346aformed on a first polysilicon region344a, and bottom electrode plate326comprises a second metal silicide region346bformed on a second polysilicon region344b. Upper metal structures384(including the upper interconnect element312, top electrode connection pad358, and bottom electrode connection pad360) may comprise copper damascene elements, each formed over a barrier layer359(e.g., a Ta/TaN bilayer) in a respective trench in a dielectric layer392.

In other examples, lower metal structures380and upper metal structures384may be formed in lower metal layer Mxand upper metal layer Mx+1, respectively, in any other suitable manner. For example, lower metal structures380and upper metal structures384may be formed as copper damascene structures. As another example, as shown inFIG. 5discussed below, lower metal structures380may be formed by subtractive patterning of the lower metal layer Mx(e.g., deposition, patterning, and etching of an aluminum layer), while upper metal structures384may be formed as copper damascene structures in the upper metal layer Mx+1.

A dielectric barrier layer382, e.g., SiN, SiC, or a high-k dielectric material (e.g., having a dielectric constant above 7) may be formed prior to formation of the upper metal layer Mx+1to provide an etch stop for a subsequent Mx+1trench metal etch (for forming upper metal structures384) and provide an effective termination layer for the edge electric field of the MIM capacitor202to improve the breakdown voltage of the MIM capacitor202.

Thus, as shown inFIG. 2Band discussed herein, the bottom electrode cup328, insulator cup324, top electrode322, and bottom electrode via362, may be formed concurrently with the interconnect vias314in the via layer Vxbetween the lower metal layer Mxand upper metal layer Mx+1. For example, as shown inFIG. 4A-4Gdiscussed below, the bottom electrode cup328, insulator cup324, and top electrode322may be formed by a damascene process including forming a tub opening406bin an inter-metal dielectric (IMD) layer390, depositing suitable materials for forming the bottom electrode cup328, insulator cup324, and top electrode322, and performing a CMP process to remove portions of the deposited materials above the tub opening406b.

In some embodiments, the MIM capacitor202discussed above may be constructed separate from the construction of interconnect structure204or other interconnection structures, using similar techniques as disclosed herein, e.g., as discussed below with reference toFIGS. 4A-4G,FIG. 5,FIG. 6, and/orFIGS. 7A-7B. Thus,FIGS. 2A and 2Bcollectively show an example integrated circuit structure300including the MIM capacitor202shown inFIGS. 3A and 3B, wherein the MIM capacitor202may be constructed separate from the construction of interconnect structure204or other interconnection structures, according to one example. In particular,FIG. 3Ashows a top view of integrated circuit structure300including MIM capacitor202, andFIG. 3Bshows a cross-sectional side view taken through line3B-3B shown inFIG. 3A. As discussed below with reference to4A-4G, in one example the MIM capacitor202may be constructed without adding any mask operations to the background integrated circuit fabrication process.

FIGS. 4A-4Gshow cross-sectional views illustrating an example process for forming the example integrated circuit structure200shown inFIGS. 2A-2B, including MIM capacitor202and nearby interconnect structure204, according to one example. EachFIG. 4A-4Gshows cross-sectional views at two locations of an integrated circuit structure under construction, namely a first location (labelled “202: MIM Capacitor”) at which MIM capacitor202is formed and a second location (labelled “204: Interconnect Structure”) at which interconnect structure204is formed.

First, as shown inFIG. 4A, the lower metal structures380, including the lower interconnect element310of interconnect structure204and the bottom electrode plate326of MIM capacitor202, are formed in the lower metal layer Mx. In particular, a polysilicon layer343is deposited, patterned, and etched to form the first polysilicon region344aand second polysilicon region344b. A self-aligned silicide (salicide) process may be performed to form the first metal silicide region346aon the first polysilicon region344aand the second metal silicide region346bon the second polysilicon region344b. The first and second metal silicide regions346aand346bmay comprise titanium silicide, cobalt silicide, nickel silicide, or other silicide having a thickness in the range of 100-500 Å. Although the first and second metal silicide regions346aand346bmay be very thin compared with the underlying first and second polysilicon region344aand344b, the silicided polysilicon layer (including lower interconnect element310and bottom electrode plate326) defines a lower metal layer Mxfor the purposes of the present disclosure. In this example, the silicided polysilicon layer Mxmay define a lower metal layer M0(where x=0) below a first metal interconnect layer M1(where Mx+1=M1), often referred to as the metal-1 layer.

Next, as shown inFIG. 4Ban inter-metal dielectric (IMD) layer390may be deposited on the structure200and planarized by a CMP process, followed by deposition and patterning of a photoresist layer400over the IMD layer390. IMD layer390may include one or more dielectric materials, e.g., at least one of silicon oxide, PSG (phosphosilicate glass), FSG (fluorine doped glass), OSG (organosilicate glass), porous OSG, or other low-k dielectric material, e.g., having a dielectric constant less than 3.6. The photoresist layer400may be deposited on the IMD layer390and patterned to simultaneously define various mask openings402a-402c, including interconnect via mask openings402a, a tub mask opening402b, and a bottom electrode via mask opening402c.

The IMD layer390may be etched through the mask openings402a-402cto concurrently form corresponding IMD openings406a-406c, including (a) interconnect via openings406afor forming interconnect vias314, (b) a tub opening406bfor forming the bottom electrode cup328, the insulator cup324, and the top electrode322, (c) and a bottom electrode via opening406cfor forming the bottom electrode via362. IMD openings406a-406cmay be formed using a plasma etch or other suitable etch, followed by a resist strip or other suitable process to remove remaining portions of photoresist layer400.

With respect to interconnect structure204, the interconnect via openings406amay be via openings having a width (or diameter or Critical Dimension (CD)) Wviain both the x-direction and y-direction in the range of 0.1-0.5 μm, for example. The interconnect width Wviamay significantly affect the performance of the IC device being formed.

With respect to MIM capacitor202, the bottom electrode via opening406cmay be formed as a via opening with a width (or diameter or Critical Dimension (CD)) Wcontact. In some examples, the bottom electrode via opening406cis formed the same as each of the interconnect via openings406a, thus Wvia=Wcontact, and may have similar dimensions in both the x-direction and y-direction. In contrast, tub opening406bmay have a substantially width in the x-direction (Wtub_x) and/or y-direction (Wtub_y) than interconnect via openings406aand the bottom electrode via opening406c. The shape and dimensions of the tub opening406bmay be selected based on various parameters, e.g., for effective manufacturing of the MIM capacitor202(e.g., effective deposition of the top plate material (e.g., aluminum) into the tub opening406b) and/or for desired performance characteristics of the resulting MIM capacitor202. In one example, the tub opening406bmay have a square or rectangular shape from the top view. In other examples, tub opening406bmay have a circular or oval shape from the top view.

As noted above, a width of tub opening406bin the x-direction (Wtub_x), y-direction (Wtub_y), or both the x-direction and y-direction (Wtub_xand Wtub_y) may be substantially larger than the width WViaof via openings406ain the x-direction, y-direction, or both the x-direction and y-direction. For example, in some examples, each width of Wtub_xand Wtub_yof tub opening406bis at least twice as large as the width WViaof via openings406a. In particular examples, each width of Wtub_xand Wtub_yof tub opening406bis at least five time as large as the width WViaof via openings406a. In some examples, Wtub_xand Wtub_yare each in the range of 1-100 μm.

Further, tub opening406bmay be formed with a height-to-width aspect ratio of less than or equal to 2.0 in both the x-direction and y-direction, e.g., to allow effective filling of the tub opening406bby conformal materials. For example, tub opening406bmay be formed with aspect ratios Htub/Wtub_xand Htub/Wtub_yeach in the range of 0.1-2.0, for example in the range of 0.5-2.0. In some examples, aspect ratios Htub/Wtub_xand Htub/Wtub_yare each less than or equal to 1.5, e.g., for effective filling of tub opening406bby conformal materials, e.g., tungsten. For example, tub opening406bmay be formed with aspect ratios Htub/Wtub_xand Htub/Wtub_yeach in the range of 0.5-1.5, or more particularly in the range of 0.8-1.2.

Although the bottom electrode via opening406cshown inFIG. 4Bmay have a similar shape and size as each of the interconnect via openings406a, in other examples the bottom electrode via opening406cmay comprise a larger opening, for example elongated in the x-direction and/or y-direction as compared with the via openings having Wvia. For example, the bottom electrode via opening406cmay comprise an extension of the tub opening406bconfigured to form a laterally elongated (in the x-direction) bottom electrode via362, which may be referred to as a rectangular via or “slotted via,” that directly connects the bottom electrode cup328with the bottom electrode connection pad360.FIGS. 7A-7Bdiscussed below illustrate one example of such implementation.

Next, as shown inFIG. 4C, a TiN liner408is deposited over the IMD layer390and extends down into the IMD openings406a-406c, followed by deposition of a conformal fill metal410, for example tungsten or other metal suitable for conformal deposition, which also extends down into the IMD openings406a-406c. As shown, the deposited via fill metal410(a) fills interconnect via openings406ato form interconnect vias314, (b) covers the interior surfaces of the tub opening406bto form a cup-shaped bottom electrode region327defining interior opening336, (c) and fills the bottom electrode via opening406cto form the bottom electrode via362. As discussed above, the cup-shaped bottom electrode region327includes multiple vertically-extending bottom electrode cup sidewalls332extending upwardly from the laterally-extending bottom electrode cup base330. In one example, the via fill metal410comprises tungsten deposited with a thickness of 1000 Å to 5000 Å. In other examples, the via fill metal410may comprise Al, Co, or TiN. The via fill metal410may be deposited by a conformal chemical vapor deposition (CVD) process or other suitable deposition process.

Next, as shown inFIG. 4D, an insulator layer423, e.g., a silicon nitride (SiN) layer with a thickness of about 500 Å, is deposited over the via fill metal410and extends down into the interior opening336of the cup-shaped bottom electrode region327(shown inFIG. 4C) to define a cup-shaped insulator region323defining an interior opening337. In other examples, the insulator layer423may comprise high-k dielectric materials, for example Al2O3, ZrO2, HfO2, ZrSiOx, HfSiOx, HfAlOx, or Ta2O5, or other suitable capacitor insulator material.

Next, as shown inFIG. 4F, a chemical mechanical planarization (CMP) process is performed to remove upper portions of the top electrode layer426, insulator layer423, via fill metal410, and liner408to define (a) the top electrode322from remaining portions of the top electrode layer426, (b) the insulator cup324from remaining portions of the cup-shaped insulator region323, and (c) the bottom electrode cup328from remaining portions of the cup-shaped bottom electrode region327.

As discussed above with reference toFIGS. 2A-2B, the insulator cup324and the bottom electrode plate326collectively define the bottom electrode320. Further, as discussed above, MIM capacitor202defines the following capacitive couplings between the top electrode322and bottom electrode320:

(a) capacitive coupling between the top electrode322and bottom electrode320by a displacement current path through the insulator cup base340and through the bottom electrode cup base330, as indicted by arrow350; and

(b) capacitive coupling between the top electrode322and bottom electrode320by a displacement current path through each vertically-extending insulator sidewall342and through the corresponding vertically-extending bottom electrode cup sidewall332, as indicated by arrow352.

Next, as shown inFIG. 4G, an etch stop layer382is deposited on the structure200. The etch stop layer382may comprise SiN, SiC, or a high-k dielectric material (e.g., having a dielectric constant greater than 7). The etch stop layer382may provide an etch stop for a damascene process etch for forming the upper metal layer Mx+1, as discussed below. The etch stop layer382may also terminate the edge of the electric field of the MIM capacitor202, which may relieve edge electric field crowding to help provide a high breakdown voltage. The etch stop layer382may also act as a dielectric diffusion barrier, e.g., if the top electrode322is formed from copper.

Finally, as shown inFIG. 4H, the upper metal layer Mx+1is formed with discrete upper metal structures384, including the upper interconnect element312of interconnect structure204, and the top electrode connection pad358and bottom electrode connection pad360of MIM capacitor202, using a single damascene process. This single damascene process may include depositing dielectric layer392, forming a metal layer trench by patterning and etching, depositing a copper diffusion barrier layer (typically Ta, TaN, or a bi-layer of both) followed by a copper seed layer in the damascene trenches, depositing a metal394to fill the damascene trenches, performing an anneal, and finally a chemical mechanical planarization (CMP) process to remove portions of the metal394above the dielectric layer392and define the discrete upper metal structures384. The dielectric layer392may comprise comprising silicon oxide (SiO2), fluorosilicate glass (FSG), organosilicate glass (OSG), porous OSG, or other suitable dielectric material. The metal394may comprise copper, which may be deposited using an electro-chemical plating process.

After forming upper metal structures384in upper metal layer Mx+1, the process may continue with additional interconnect construction.

FIG. 5shows a side cross-sectional view of an example integrated circuit structure500including a MIM capacitor502and nearby interconnect structure504formed concurrently. Integrated circuit structure500is similar to integrated circuit structure200discussed above, except lower metal structures380formed in the lower metal layer Mx(including lower interconnect element310and bottom electrode plate326) are formed from aluminum using a subtractive patterning process, including deposition, patterning, and etching of an aluminum layer.

FIG. 6shows a side cross-sectional view of another example integrated circuit structure600including a MIM capacitor602and nearby interconnect structure604formed concurrently. Integrated circuit structure600is similar to integrated circuit structure200discussed above, except lower metal structures380formed in the lower metal layer Mx(including lower interconnect element310and MIM bottom electrode plate326) comprise copper damascene structures, each formed over a barrier layer381(e.g., a Ta/TaN bilayer) in a respective trench, followed by deposition of a dielectric barrier layer383, e.g., comprising SiN or SiC, over the copper damascene structures380.

FIGS. 7A and 7Bshow a top view and a side cross-sectional side view, respectively, of an example MIM capacitor702that may be formed in integrated circuit structure200, in place of MIM capacitor202discussed above. The example MIM capacitor702is similar to MIM capacitor202discussed above, but includes a bottom electrode via362′ formed in via layer Vxthat provides a direct conductive path between the bottom electrode cup328and the bottom electrode connection pad360, which may provide a reduced resistance as compared with MIM capacitor202discussed above. The bottom electrode via362′ may define a lateral extension from the bottom electrode cup328, and may be formed concurrently with the bottom electrode cup328, e.g., by depositing the via fill metal410(e.g., tungsten or other conformal metal) into a laterally elongated opening extending from the tub opening used to form the bottom electrode cup328.

As noted above, in some examples the MIM capacitor202or702can be constructed between any two metal layers Mxand Mx+1at any depth in the relevant integrated circuit structure. In some examples each metal layer Mxand Mx+1may comprise a metal interconnect layer, e.g., an aluminum or copper interconnect layer, wherein the lower metal structures380in the lower metal layer Mxand upper metal structures384in the upper metal layer Mx+1are formed by subtractive patterning (e.g., deposition, patterning, and etching), or using a damascene process, or in any other suitable manner.