Digital control of switched boundary mode power converter without current sensor

A circuit arrangement for switched boundary mode power conversion, a corresponding signal processor and a method of switched boundary mode power conversion are provided. The circuit arrangement comprises an input for receiving an input voltage from a power supply, an output to provide an output voltage to a load, an energy storage device, a controllable switching device, and a signal processor. The signal processor is connected to the controllable switching device and being configured for zero-current switching of the switching device, wherein the signal processor is further configured to determine at least one switching point for the zero-current switching from a first voltage signal and a second voltage signal, wherein the first voltage signal corresponds to the input voltage and the second voltage signal corresponds to the output voltage.

TECHNICAL FIELD

The present disclosure relates to power converters and, more particularly, to control of a boundary mode power converter.

BACKGROUND

Power converters and in particular switched-mode power converters are used in a variety of applications to provide AC/DC and DC/DC conversion. For example, switched-mode power converters, also referred to as switched-mode power supplies (SMPS), are widely used in computer and mobile phone power supply units to provide the necessary operating voltages from typical 120V/240V AC mains lines.

Typical items of concern when designing power converters relate to conversion efficiency and cost. It should be readily apparent that power losses should be minimized to increase the overall efficiency of the converter and also to reduce the generation of heat, which may be difficult to dissipate depending on the design and the respective application.

It is known to operate switched-mode power converters in boundary conduction mode or short “boundary mode” (BCM). Unlike a continuous operation in CCM (continuous conduction mode), in boundary conduction mode it is aimed to operate the switch of the power converter when no or no substantial current flows through the switch. This operational mode reduces switching losses and also allows to use less expensive components, for example less expensive boost diodes in a boost switched-mode power converter setup due to no reverse-recovery losses. In addition, BCM also allows for power factor correction (PFC), in view that the input current follows the input voltage waveform.

A by-product of BCM is that the converter inherently uses a variable switching frequency. The frequency depends primarily on the selected output voltage, the instantaneous value of the input voltage, the parameters of the energy storage used, e.g., inductance or capacitance and the output power delivered to the load. The lowest frequency occurs at the peak of sinusoidal line voltage.

To operate properly in boundary conduction mode, it is necessary to determine the exact moment when the current through the switch reaches zero. In typical circuits, current sensing is used, for example using a current transformer, using a coupled inductance, such as a further winding close to a main inductance, or using CT or hall effect sensors. However, all of these approaches add cost and complexity to the circuit.

SUMMARY

An object thus exists to provide a cost-effective circuit arrangement and method for switched-mode power conversion that allows to operate efficiently in boundary conduction mode.

The object is solved by a circuit arrangement, a signal processor, and a method for switched boundary mode power conversion. The dependent claims as well as the following description contain various embodiments of the invention.

In one aspect, a circuit arrangement for switched boundary mode power conversion is provided that comprises an input for receiving an input voltage from a power supply; an output to provide an output voltage to a load; an energy storage device; a controllable switching device; and a signal processor. The signal processor is connected to the controllable switching device and is configured for zero-current switching of the switching device; wherein the signal processor is further configured to determine at least one switching point for the zero-current switching from a first voltage signal and a second voltage signal, wherein the first voltage signal corresponds to the input voltage and the second voltage signal corresponds to the output voltage.

A basic idea of the invention is to allow operating a switched-mode power converter efficiently in boundary conduction mode by eliminating current sensing. This allows to reduce the cost of a corresponding converter. As the inventors of the instant invention have ascertained, eliminating current sensing in boundary conduction mode converters also removes problems with the detection, since the use of magnetic components for the current sensing introduces a significant delay. The delay makes a proper detection of a zero-current point difficult. At last, some embodiments allow an increased power density, i.e., a smaller converter size.

DETAILED DESCRIPTION

Technical features described in this application can be used to construct various embodiments of integrated circuit devices. Some embodiments of the invention are discussed so as to enable one skilled in the art to make and use the invention.

As discussed in the preceding, and in one aspect, a circuit arrangement for switched boundary mode power conversion is provided that comprises an input for receiving an input voltage from a power supply; an output to provide an output voltage to a load; an energy storage device; a controllable switching device; and a signal processor. The signal processor is connected to the controllable switching device and is configured for zero-current switching of the switching device; wherein the signal processor is further configured to determine at least one switching point for the zero-current switching from a first voltage signal and a second voltage signal, wherein the first voltage signal corresponds to the input voltage and the second voltage signal corresponds to the output voltage.

In the context of the present discussion, the term “switched boundary mode power conversion” is understood as switched-mode electric power conversion in boundary conduction mode (BCM). A corresponding converter circuit comprises at least an energy storage device and a switching device for storing input energy temporarily and then releasing that energy to the output at a different voltage.

In BCM, a new switching period is initiated when the current through the energy storage device returns to zero, which is at the boundary of continuous conduction (CCM) and discontinuous conduction mode (DCM).

An “energy storage device” in the present context is understood as a device for storing electrical energy at least temporarily. For example, an energy storage device may comprise one or more inductors/inductances and/or one or more capacitors/capacitances.

In some embodiments, the value of the energy storage device such as an inductor should be large in comparison to the total resistance in the circuit. The resistance (R) could be present in the form of inductor resistance, switching device resistance, filter resistance, board trace resistance, etc. The inductor current in some embodiments follows a path based on the final value of current during ON time as If*e{circumflex over ( )}(−t/ζ) where If=Vin/R, ζ=L/R. The inductor current appears as a straight line if ζ is large. One way to increase the value of ζ is to reduce the resistance (R) value by using efficient switches and inductors. During the OFF time, the load resistance contributes to R in addition to other resistances. The value of L may be set in some embodiments by the input voltage, load range, and switching frequency limits.

The switching device in the present context may be of any suitable type to control an electrical current. The switching device may comprise for example one or more semiconductor switches, such as bipolar transistors, field-effect transistors, MOSFETs, IGBTs, SiCs, GANs etc.

According to the present aspect, the circuit arrangement comprises the signal processor. In this context, a signal processor is understood as a device that allows for cycled controlling of the switching device, for example according to a pulse-width-modulation (PWM) with a frequency in the kHz range. In some examples, the signal processor is configured to control the switch in PWM with a frequency of approximately 500 kHz. In some embodiments, the signal processor is a digital signal processor (DSP), which allows faster execution of routines for zero-current determination.

The signal processor according to the present aspect is configured for zero-current switching. In this context, “zero-current switching” is understood as controlling the switching device when no or just a minor current of, e.g., less than 100 μA is flowing. As will be apparent in view that the circuit arrangement is configured for boundary conduction mode operation, zero-current switching in particular relates to the control from an off state, i.e., non-conductive state of the switching device, to an on state, i.e., a conductive state of the switching device when no or just a minor current is flowing.

A “zero-current point” of the energy storage device in the context of the present explanation is understood as the point in time when the energy storage device is completely discharged after a charge/discharge cycle, also referred to as “switching cycle” herein.

A “switching cycle” in this context is understood as the combined time of the respective controllable switching device being set conductive, i.e., in the on-state, and the controllable switching device subsequently being set non-conductive, i.e., in the off-state. In case of a PWM control, the switching cycle corresponds to the PWM cycle time T.

A “mid-cycle” time corresponds to half the switching cycle period and is thus a point in time in each switching cycle that is equally spaced between two subsequent zero-current points of the energy storage device.

Reference will now be made to the drawings in which the various elements of embodiments will be given numerical designations and in which further embodiments will be discussed.

Specific references to components, modules, units, devices, sections, parts, process steps, and other elements are not intended to be limiting. Further, it is understood that like parts bear the same or similar reference numerals, when referring to alternate figures. It is further noted that the figures are schematic and provided for guidance to the skilled reader and are not necessarily drawn to scale. Rather, the various drawing scales, aspect ratios, and numbers of components shown in the figures may be purposely distorted to make certain features or relationships easier to understand.

FIG. 1shows a schematic block diagram of an embodiment of a circuit arrangement for switched boundary mode power conversion, namely in the instant embodiment, a switched-mode BCM boost converter circuit1.

The boost converter circuit1comprises an input or input stage2, configured for connection to a typical mains connection, e.g., at 110V, 60 Hz or 240V, 50 Hz. A bridge rectifier3is provided at the input2to obtain positive half-waves. The boost converter circuit1further comprises an energy storage device in the form of an inductor4, MOSFET switching device5, flyback diode6, output capacitor7, output8, signal processor9, and pulse-width-modulation (PWM) driver10.

The general operation of circuit1corresponds to that of a typical boost converter: inductor4is charged when MOSFET5is in the on state. Once inductor4is charged, MOSFET5is switched to the off state, so that the only remaining current path is through the flyback diode6and load11, the latter of which is shown inFIG. 1as a variable resistance. The voltage increases in view of the increased current from both, the inductance4and the input2. The energy stored in the inductor4during the on state is discharged into the load11through diode6, when the MOSFET5is in the off state.

The operation of circuit1is controlled by signal processor9and PWM driver10. As shown, signal processor9is connected to PWM driver10and provides a PWM control signal to the driver10. The driver10controls the MOSFET5and comprises a level shifter, which changes the drive signal from 0-3.3V to the levels required by MOSFET5, e.g., in this embodiment 0-12V. Additionally, PWM driver10drives the MOSFET5with a faster rise and fall times, which are beneficial for reducing switching losses. The MOSFET ON voltage decides its resistance. Higher voltage leads to lower ON resistance.

The signal processor9in the present embodiment is a digital signal processor of dsPIC33EP series type, available from Microchip Technology Inc., Chandler, Ariz., USA. As discussed in the preceding, the circuit1is configured for boundary conduction mode (BCM) operation, which is controlled by signal processor9.

In typical BCM operation, a new switching period of the PWM is initiated when the current through the inductor4, IL, returns to zero.FIG. 2shows a diagram of the inductor current ILin an exemplary schematic PWM switching cycle. The rising current slope typically may correspond to VIN/L and the falling current slope may typically correspond to

As can be seen from the bottom part ofFIG. 2, a PWM control signal is applied to MOSFET5. When the PWM signal is high, MOSFET5is conductive and the current ILin the inductor4increases. This time period is described herein as TONtime. Once the desired charge of inductor4is reached, the PWM signal is controlled to low and MOSFET5is set non-conductive. The current ILgradually decreases until the inductor4is fully discharged. This time period is described herein as TOFFtime. Both, TONand TOFFare a PWM/switching cycle T.

When the inductor4is fully discharged, i.e., at a “zero-current point” in time in the PWM cycle, the next PWM cycle begins. The PWM signal correspondingly is controlled high and MOSFET5is switched conductive.

As discussed in the preceding, BCM avoids switching losses in view that the MOSFET5is controlled from an off-state to an on-state when no substantial current flows, which is referred to herein as “zero-current switching”.

FIG. 3shows diagrams of the operation of the circuit1during a full cycle of AC input voltage VIN. As will be apparent from the FIG., the inductor4is charged and discharged multiple times in each half-cycle of the input voltage in accordance with the PWM signal, shown inFIG. 3as VPWM. The converter circuit1operates with a variable switching frequency, which depends primarily on the desired output reference voltage VO,ref, the instantaneous value of the input voltage VIN, the inductor value of inductor4, and the output power delivered to the load RL11.

The operating frequency changes as the input current follows the sinusoidal input voltage waveform, as shown inFIG. 3. The lowest frequency occurs at the peak of sinusoidal input, i.e., line voltage. As will be apparent fromFIG. 3, and since the current waveform of ILis roughly triangular, the average value in each PWM period is proportional to the input voltage VIN. Thus, provided a sinusoidal VIN, the input current IINof the circuit1follows the waveform of VINwith high accuracy and draws a sinusoidal input current from the mains. Accordingly, operating the converter1in BCM is ideal for power factor correction (PFC).

Reverting toFIG. 1, to allow BCM operation, the signal processor9is configured to receive a first voltage signal that corresponds to the rectified mains voltage VINat a first voltage input12. A second voltage signal is provided to second voltage input13. The second voltage signal corresponds to the output voltage VOUT. Both voltage signals in the embodiment ofFIG. 1are obtained over corresponding voltage dividers, formed by resistors Rxand Ry. It is noted that while the output-side voltage divider inFIG. 1is shown outside of circuit arrangement1, certainly, this voltage divider may be provided as a part of the circuit arrangement1.

The signal processor9takes samples of the first voltage signal and the second voltage signal. The sampling of the input and output voltage signal should be done ideally at T/2, i.e., at half of a switching cycle for obtaining suitable averages.

Signal processor9is configured to sample the voltage signals at T/2 when the duty cycle of the PWM is lower than 50%, i.e., when VIN>VOUT/2. This provides that the period corresponds to the average of the input voltage. The bulk of the power transfer occurs during this interval. Since the duty cycle and the frequency are low in this case, there is adequate time for calculating the next zero-current point and the switching period.

For the remainder of the input voltage half-wave, the sampling frequency goes higher towards the zero-current point and there is no adequate time for computation if sampling would be done at T/2. Instead, for a duty cycle of equal to or higher than 50%, the signal processor9is configured to sample the voltage signals near the start of the cycle, for example after a small delay of 100 ns for switching transients to die down. Since the input voltage is small compared to its peak, the difference between the values sampled at start and T/2 is not significant.

Using the two voltage signals, corresponding to VINand VOUT, as well as a predefined voltage reference VO,REF, provided by an internal memory (not shown) of signal processor9, the signal processor9calculates the zero-current points in each PWM cycle, i.e., the point in time, where the inductor current ILreaches zero. It is noted, that signal processor9in this embodiment does not measure the inductor current ILdirectly, which provides a particularly cost effective and compact setup.

FIG. 4shows a schematic block diagram of an embodiment of the operation of signal processor9ofFIG. 1.

The first (corresponding to VIN) and second (corr. to VOUT) voltage signals are received at the respective inputs12and13. The predefined voltage reference VO,REFis obtained from memory40. The two voltage signals are provided to operational amplifiers41a,41bfor signal conditioning and then provided to analog-to-digital (ADC) circuits42a,42b. The two ADC circuits42a,42bconvert the voltage signals to digital information and are of 12 bit type with a Vmin: 0V and a Vmax: 3.3V.

Signal processor9further comprises multiple modules to provide the total PWM cycle time T and the on-time TONto PWM driver10. As shown in the upper part ofFIG. 4, subtraction module43and division module44provide

VOUT(VOUT-VIN)
to multiplication module45. The upper path, shown inFIG. 4, is a high frequency execution path to compute the PWM period value, operating at a maximum frequency in this embodiment of 500 kHz.

In the lower part ofFIG. 4, the on-time for the PWM, TON, is calculated from VOUT, i.e., the current output voltage and the predefined voltage reference VO,REF. Summing node46compares the current output voltage VOUTwith the “set point” VO,REF. The resulting error signal is provided to filter/compensator47, which runs at a relatively low frequency, e.g., 10 Hz, to remove second harmonic components, typically present in the output voltage VOUT.

The filtered error signal is provided to limiter48. The limiter48provides safety, in particular in a load side short circuit situation. During a short circuit on the output/load side, the ON time of MOSFET5tends to go higher. Limiter48limits the maximum on time TON, and thus the maximum power, fed to the output. Accordingly, a short circuit situation is safely handled. If both, the input voltage and the on-time are within limits, an over power condition does not arise.

Multiplier45receives the correspondingly processed error signal as on-time TONand correspondingly provides

VOUT(VOUT-VIN)×TON
to delay49and subsequently to PWM driver10as total PWM period time T. TONalso directly provided to PWM driver10. Using T and TON, PWM driver can apply the appropriate PWM timing settings to the gate of MOSFET5. In view that the calculation is based upon VOUTand VIN, the zero-current point in each PWM cycle reliably determined.

As mentioned in the preceding, delay49is coupled between multiplier45and the PWM driver10. The delay49provides to slightly delay the moment, the MOSFET5is switched to the on-state past the “true” moment, the current in inductor4reaches zero. The reason being that considering typical parasitic capacitances, in particular in MOSFET5, the actual zero moment of the inductor4is not ideal for the switching in view the voltage across the parasitic capacitance of MOSFET5in this case would discharge through the MOSFET5. To counter this loss, delay49is provided. Delay49further compensates a propagation delay, introduced by the driver10. The delay time is predefined, based on the parasitic capacitance value. Typical delay times range between 100 ns and 500 ns. Accordingly, it is noted that in view of the rather small delay introduced in the switching of MOSFET5, the delayed switching points are still considered as zero-current points herein.

FIG. 5shows the diode current iDnear the peak of the input voltage.FIG. 6shows the diode current iDnear zero of the input voltage.

FIG. 7shows a further embodiment of a boost converter circuit1ain a schematic block diagram. The embodiment of circuit arrangement1acorresponds to the embodiment ofFIG. 1with the following exception. As can be seen fromFIG. 7, a bypass diode D2for the inductor4is arranged, which is facilitates starting up the circuit1a.

While the invention has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are to be considered illustrative or exemplary and not restrictive; the invention is not limited to the disclosed embodiments. For example, it is possible to operate the invention in an embodiment in which:instead of or in addition to inductor4, a capacitor is used as an energy storage device;an EMI (electromagnetic interference) filter is included and designed to pass lower frequency components and attenuate the higher frequency components; and/orfilter/compensator47is a 2P2Z or a PID controller;

The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measured cannot be used to advantage. Any reference signs in the claims should not be construed as limiting the scope.

APPENDIX

Embodiments of the present disclosure include microcontrollers, systems, integrated circuit devices, and methods for digital control of boundary mode PFC without a current sensor. Such PFC may be implemented by any suitable combination of analog circuitry, digital circuitry, instructions for execution by a processor, or combination thereof. Embodiments of the present disclosure may further be implemented in power supplies or controllers for power supplies.

FIG. 1is an illustration of an example circuit for implementing control of boundary mode PFC without current sensor.

Boundary mode PFC may include a variable frequency topology wherein the switching frequency is varying over an alternating current (AC) line cycle. The variable frequency may be due to zero-inductor-current PWM switching. The frequency may be primarily dependent on the input voltage, output load, and inductor value. The frequency may be highest near the input voltage zero and lowest near the input voltage peak. An EMI filter may be included and designed to pass lower frequency components and attenuate the higher frequency components.

Boundary mode PFC may also include a boost topology, AC input, direct current (DC) output, an outer voltage loop, constant ON time, a switch to be turned off at zero current, and variable frequency.

Embodiments of the present disclosure may interleave two or more boost PFC stages. The embodiments may achieve both zero current switching and 50% phase difference. Implementations of such embodiments and algorithms thereof may cause significant amounts of delay in the current detection circuitry. Such delay may arise from a mismatch between calculated and actual zero detection time. One solution to this issue may require complex magnetic design changes. Another solution may include embodiments wherein current detection is eliminated. The current detection may be eliminated for the PFC stages or for boundary mode PFC. Boundary mode PFC may achieve high power factor and high efficiency due to zero current switching in a front-end AC-DC converter. However, boundary mode PFC may otherwise require complicated current sensing either using a current transformer or zero current sensing using coupled inductor technique. Instead, embodiments of the present disclosure may take advantage of the computing power of an integrated circuit device that otherwise is responsible for PFC, such as a microcontroller, ASIC, or dsPIC, to achieve the advantages of the boundary mode PFC, without the use of any current sensors. The proposed solution may lead to a solution having low cost and higher power density.

InFIG. 1, in an interleaved multistage boundary mode PFC, boundary mode PFC may be achieved wherein the current is switched at zero instance. This may lead to higher efficiency due to lower switching losses. The input to the circuit is a power supply at, for example, 110V, 60 Hz or 230V, 50 Hz. The input voltage may be rectified using a bridge rectifier and fed to a boost circuit including an inductor, switch and diode. The rectified input voltage and the output voltage may be sampled by an analog-to-digital converter (ADC). The ADC may be inherent in the dsPIC. Other solutions may rely on either inductor current sensing using a CT or hall effect sensor or zero cross detection circuits utilizing coupled inductance. However, these circuits add additional cost to the hardware. Further there is a significant amount of delay in the circuits due to reliance on the magnetic components for detection. The dsPIC may run a compensator such as 2P2Z or PID for the voltage loop at a relatively low frequency to obtain the TONtime. The output of the compensator may provide the ON time for the pulsed-width modulation (PWM) circuit. A higher bandwidth loop may compute the PWM period value based on the values of input and output voltages. The PWM may truncate at the instant the current goes to zero. In reality, a zero current point may not be not ideal for the switching as the voltage across parasitic capacitance of the switch (implemented as, for example, a MOSFET) would discharge through the switch. This may lead to additional power losses in the switch. To counter this loss, a delay may be added to the switch depending on the parasitic capacitance value. Thus, embodiments of the present disclosure may meet the objective of zero current switching without current sensing. The risk of not having a current sense circuit is felt during conditions such as load short circuit. During short circuit the output voltage falls low, and the ON time of the switch tends to go higher. By setting the maximum ON time of the switch, a condition such as overload or short circuit may be addressed, as the power fed to the output is limited. The input current may depend on the value of the ON time and input voltage. If both the input voltage and ON time are within limits, over power conditions might not arise. The input voltage is monitored separately and a fault is flagged if it is outside the working range.

Most system designers and developers would resist the concept of removing current sensing from such a circuits due to perception of reduced safety. However, embodiments of the present disclosure may still handle safety conditions and requirements under all necessary load conditions. Furthermore, the topology of embodiments of the present disclosure under consideration may require a significant amount of MIPS to compute and estimate the current zero crossing time, considering the variable frequency operation of the PFC. This may cause a need for significant expertise in implementing the solutions.

Embodiments of the present disclosure may eliminate the need for complicated current sensing circuitry thereby reducing the size of the power supply. Further it also reduces the need for additional pins and processing of the current signal using a microcontroller.

FIGS. 2 and 3illustrate example performance of the system in terms of current with respect to time periods and a PWM signal.

FIG. 4is an illustration of an algorithm of operation of the PFC, according to embodiments of the present disclosure.

FIG. 5illustrates inductor current near peak, according to embodiments of the present disclosure.

FIG. 6illustrates inductor current near zero, according to embodiments of the present disclosure.

FIG. 7is another illustration of a block diagram of a PFC power supply, according to embodiments of the present disclosure.

Although particular embodiments have been illustrated in the present disclosure, additions, modifications, subtractions, and other alterations may be made to the example embodiments of the present disclosure without departing from the spirit and teachings of the present disclosure.

An integrated circuit device, may comprise a control circuit; and a plurality of boost converter stages, each boost converter stage including an inductor, a diode, and a switch; wherein the control circuit is configured to synchronize a new pulsed-width modulation (PWM) switching cycle upon a zero-inductor current through respective boost converter stages.