Routing design to minimize electromigration damage to solder bumps

A novel pad structure for an integrated circuit component that utilizes a bump interconnect for connection to other integrated circuit components that produces a relatively uniform current distribution within the bump of the bump interconnect is presented. The pad structure includes an inner pad implemented on an inner conductive layer of the integrated circuit component, an outer pad implemented on an outer conductive layer of the integrated circuit component, and a plurality of vias connecting the inner pad and outer pad. The outer pad is sealed preferably around its edges with a passivation layer, which includes an opening exposing a portion of the outer pad. The vias connecting the inner pad and outer pad are preferably implemented to lie in a via region within the footprint of the pad opening.

BACKGROUND OF THE INVENTION

The present invention relates generally to flip chip packaging technologies for integrated circuits more particularly to a methodology and trace design for minimizing electromigration damage to integrated circuit connection joints such as solder bumps in a flip-chip assembly.

Electromigration is the movement of material within a conductor that is caused by the flow of electrical current. Electromigration can cause the complete depletion of material within a conductor leading to the loss of continuity. The effect is more apparent at interconnect junctions, for example, in a solder bump connecting a flip-chip die and substrate, and is dependent on the current density (higher being worse than lower), the material (some materials resisting the effects of electromigration more than others), and the geometry of the structure.

Electromigration is a problem commonly seen in high-current-flow bumps of flip-chip assemblies, so named because during formation, the die pads are formed on the top layer of the integrated circuit die, bumps are added, and the die is then “flipped” over and connected directly to the chip substrate via the bumps. More specifically, and with reference toFIGS. 1 and 2, circuit components are formed on a semiconductor wafer using standard fabrication techniques, with local interconnect layers (formed of interleaved metal and dielectric layers) situated closer to the functional circuitry and global interconnect layers formed further up the sequence of layers. Die pads22are formed in the uppermost metal layer. Bumps are then added, and the wafer is diced into individual integrated circuit die14for packaging. An individual die14is then “flipped” over and attached directly to a substrate12or board through the bumps16, as shown inFIG. 1.

Bumps16are formed through one of several different processes, including solder bumping, using processes that are well known in the art.FIG. 2illustrates a portion of a flip-chip assembly10which utilizes solder bumps16. In the solder bumping process, an under bump metallization (UBM)26is applied to the chip bond pads, by sputtering, plating, or other means, to replace the insulating passivation layer24(typically comprising a polymer such as Benzoclyclobutene or “BCB”) typically applied over the top metal layer, and to define and limit the solder-wetted area. Solder is deposited over the UBM26by evaporation, electroplating, screen printing solder paste, or needle-depositing.

FIG. 1illustrates an example of a typical path of current flow18in a flip-chip assembly10that utilizes a conductive bump16for interconnecting the pads (not visible) of an integrated circuit die14to pads (not visible) on a chip substrate12. As shown, a typical current path18flows from circuitry (not visible) on the substrate12, through a bump16a, through circuitry (not visible) on the die14, and finally from the die14through another bump16band into other circuitry (not visible) on the substrate12. A bump16is the element in the current flow path18that is often the most susceptible to electromigration damage due to its material, typically a solder, and the fact that the current flow must change directions.

As shown in more detail inFIG. 2, current flowing through the trace20and pad22within the die14must change direction in order to flow through an opening25, through the conductive pad-to-bump interface (referred to hereinafter as the UBM)26, through the bump16itself, and finally into the substrate pad28. As indicated with dotted arrows15inFIG. 2, this turning causes the current to “crowd” at the upstream side of the bump16, resulting in a higher current density, J, in the location of crowding. The mean time to fail (MTTF) under electromigration conditions is generally approximated to be

where A incorporates the effects of temperature and other factors and the power n is in the range of 1 to 2 for lead solders. High local values of the current density, J, may cause failures that are premature in time when compared with the failures that occur when the current is uniformly distributed in the bump16.

The amelioration of electromigration in bump interconnects is the subject of much study. One prior art solution includes the use of a “bus” structure for high current bumps in order to limit the routable regions within the metal layer(s) used for the bus.

The cross-sectional area of a bump affects the rate of electromigration in the bump. Bump cross-sectional area is partially dictated by the bump-to-bump spacing, with higher spacing typically permitting greater cross-sectional area of the bumps. However, with the competition for smaller and faster packaging, the trend has been towards shrinking the bump-to-bump spacing. Thus, future bumps may have smaller cross-sections, leading to the problem of higher current densities in the bumps.

The choice of material used to implement the bump can also play a significant factor in the electromigration properties of the bump. Presently, bump material is typically made of either a 90% Pb (lead) solder that is known to exhibit some electromigration resistance or a lead-tin eutectic solder that has significantly less resistance to electromigration damage. Future designs may use lead-free materials which have unknown electromigration issues. The ability to remove the electromigration design restrictions as materials change could be an important design asset.

Present designs employ multiple bumps for high current circuits. More electromigration resistant designs may enhance present configurations by carrying these high currents in fewer bumps, thereby reducing chip size and cost or by freeing up bumps for other functions. Future designs could also enjoy these benefits. These advantages may also be shared by lower current signal bumps where, for example, traces may be made narrower which would result in routing enhancements.

In view of the foregoing, it would be desirable to have a technique for equalizing the distribution of current flow through bumps of BGAs or flip-chip packages in order to reduce electromigration caused by current crowding in one area of the bump, and a novel pad structure that produces the same.

SUMMARY OF THE INVENTION

A novel pad structure and current routing design for pads of an integrated circuit component are described in detail hereinafter. The pad structure of the invention includes a first pad implemented on an inner conductive layer of an integrated circuit component, a second pad implemented on an outer conductive layer of the integrated circuit, and a plurality of vias each directly connecting the inner pad to the outer pad. A current delivering trace is connected to the first pad. The second, or “outer”, pad is sealed around its edges with a passivation layer, which includes an opening exposing the conductive outer pad. The exposed area of the conductive outer pad is hereinafter referred to as the “pad opening”. The vias connecting the inner pad to the outer pad are positioned within the footprint of the pad opening. Thus, as current is delivered to the inner pad from the trace, the via impedances, which are each higher than the impedance of the current delivering trace, causes the current to divide and flow to the outer pad over the plurality of vias, thus distributing the current and reducing current crowding at the inner pad. At a minimum this results in a reduction in the maximum current density seen on the outer pad, and therefore a reduction in electromigration damage in the solder bump caused by current crowding. With a small amount of additional planning with regards to the selection of the number and layout of the vias connecting the inner and outer pads within the footprint of the pad opening, the current flow to the outer pad can be optimized to produce a relatively uniform current density.

More generally, the pad structure of the invention may be implemented in any integrated circuit component that employs pads for interconnection to other circuit components and that is fabricated with interleaved conductive and dielectric layers. Integrated circuit components that may use the pad structure and routing design of the invention include integrated circuit dies, integrated circuit substrates, integrated circuit packages, and printed circuit boards (PCBs).

DETAILED DESCRIPTION

A novel design for integrated circuit component pads is described in detail below that seeks to achieve a reasonably uniform current distribution on the outer pad interface to assist in reducing electromigration damage in a joint (e.g., flip-chip bump) connected to the pad. For purposes of comparison, the configuration of a traditional prior art solder bump in a flip-chip assembly is shown inFIGS. 3A,3B,3C,3D, and3E. More particularly,FIG. 3Ais a cross-sectional side view,FIG. 3Bis a cross-sectional front view,FIG. 3Cis an isometric view, andFIG. 3Dis a top plan view of the components included in a single bump junction of the flip-chip assembly10ofFIG. 1.FIG. 3Eis a perspective view of the trace20and pad22ofFIGS. 3A–3D. As illustrated inFIGS. 3A,3B,3C, and3D, the trace20is conductively connected to the pad22on the outermost trace layer of the integrated circuit14(ofFIG. 1). The pad22is capped with a passivation layer24, typically comprising either a nitride or a polymer. An opening25is etched into the passivation layer24and the UBM26is plated over both the opening25and a portion of the passivation layer24. Solder attaches to the UBM26during the bumping process to form bump16, which conductively connects the UBM26and the substrate pad28when the die is flipped and attached to the substrate12. The substrate pad28is connected to substrate via30for routing to circuitry implemented on or otherwise connected to the substrate12.

In the traditional configuration, as shown inFIG. 3D, current enters the pad22from the trace20along the path18, and, as illustrated inFIG. 2, causes the greatest current densities in the solder bump16in the area indicated at15near the opening to the pad22closest to the trace20.

In a design implemented according to the present invention, as shown inFIGS. 4A and 4B, the trace20is conductively connected to a first (or “inner”) pad42implemented on an internal metal layer Mn of the die. The inner pad42is conductively connected to a second (or “outer”) pad46implemented on an outer metal layer M1of the die by way of a plurality of conductive vias44a–44iwithin a via region44. Each via44a–44iin the via region44passes through each of intervening layers of metal Mn−1 and dielectric D1, . . . , Dn. The outer pad46is capped with a passivation layer48. An opening25to the pad is etched into the passivation layer48and the UBM26is plated over both the pad opening25and a portion of the passivation layer48. Solder attaches to the USM26during the bumping process to form bump16, which conductively connects the UBM26and the substrate pad28when the die is flipped and attached to the substrate12. The substrate pad28is connected to substrate via30for routing to circuitry implemented oil or otherwise connected to the substrate12. The metal layers M1, . . . , Mn, vias, and UBM are preferably implemented using highly conductive material and the layers D1, . . . , Dn−1 and48are preferably implemented in dielectric materials.

The number of vias44a–44iimplemented in a given pad structure will depend on the requirements of the particular integrated circuit design, the tradeoff of current distribution in the pad to reduce electromigration damage in the bump16being increased resistance in the pad, and therefore increased power dissipation by the chip.FIG. 4Bshows an example top plan view of the pad structure with a number of vias44a–44iarranged in an example uniformly distributed configuration. As shown, the connection of the vias to the outer pad46lies in a via region44is within the footprint of the pad opening25. As defined herein, the “footprint” is coaxial with the pad opening25, and is identical in both shape and orientation to the pad opening25, but lies on the opposite face of the outer pad46. The selection of the number of vias44a–44iwithin the via region44as well as the selection of the relative area of the via region44with respect to that of the opening25dictate the maximum current density within the bump16.

The vias44a–44iprovide two benefits. The first is That the impedances of the vias44a–44i,which may be adjusted during the design phase to obtain a desirable current distribution, causes current flow (indicated by arrow50) passing from the trace20to the bump18to distribute more uniformly within the inner pad42that is connected directly to the trace20, thereby reducing the current crowding at an upstream location of the pad structure. The second benefit of the vias44a–44iis that when the vias44a–44iare positioned for connection within the footprint of the pad opening25(i.e., the footprint of the outer-pad-to-UBM interface), adverse current concentration effects that occur when current enters the outer pad opening25to the UBM26from a radial location outside the footprint of the outer pad opening25are minimized.

A sample analysis of the traditional pad structure ofFIGS. 3A–3Eand the invention-based pad structure ofFIGS. 4A and 4Busing three-dimensional finite element models in which the current density distribution within the bump (and, in particular, at the interface with the UBM) is determined shows that the pad structure40of the invention has significantly lower maximum current densities at the critical pad-to-UBM interface location than those in the traditional pad structure10. The maximum current densities are taken to be indicative of the electromigration life of the bumps16in each configuration.

Select physical dimensions used in the analysis are as follows: The planar dimensions of the pads22,42, and46are 80 um×80 um. The diameter of the BCB opening is 60 um. The thickness of the metal layers M1, . . . , Mn are each 0.9 um. The diameter of the UBM26is 110um. The width of the trace20is 20 um. The height of each of the vias44a–44iis 0.65 um. Due to the discrete nature of the vias44a–44i,the areal coverage of metal on the pads42,46by connection of the vias44a–44ito the pads42,46is approximately 12% (this partial coverage by the via metal leads to the resistance that aids the spreading of the current in the inner trace42). In the analysis, the diameter of the region containing the vias44a–44iwas varied between 10 and 70 um. The circular region containing the vias was centered on the center of the opening25.

FIG. 5shows a graph of the maximum current densities at the UBM side of the bumps, a critical location for the configurations considered, resulting from the analysis. As illustrated byFIG. 5, the use of a plurality of vias44a–44ibetween the inner current carrying metal layer Mn and the outer pad layer M1produces current density values of approximately 1.2 for a prior art pad structure and 0.9 for the pad structure ofFIGS. 4A and 4Bfor a via diameter of 70 um, corresponding to a drop in maximum current densities for the pad structure of the invention on the order of 25% for this case.

FIG. 5also illustrates that the placement of each of the vias44a–44ifor connection to the outer pad46within the footprint of the pad opening25can produce additional decreases in maximum current densities. This is seen for the case of via-containing-region diameters of 30–40 um, where the pad structure40of the invention roughly halves the maximum current density when compared with the pad structure10of the traditional design.

FIG. 6is a graph illustrating the relative electromigration life of a bump16using the pad structure40of the invention versus the diameter of the region containing the vias44a–44ifor various values of the power exponent n, thereby illustrating the possible increases in electromigration life associated with the results of the analysis described above. The exponent, n, is varied from 1 to 2, which are in line with known data for lead solders. For the design conditions examined, a pad structure40of the invention may have electromigration life improvements of two to four times that of pad structures10of traditional designs.

It will be appreciated by those skilled in the art that the same invention-based design philosophy may be applied, for example, within the pad/via/trace design in the substrate.

Analysis and comparison of traditional and invention-based pad configurations in determining the current density distribution within the bump and, in particular, at the pad-to-UBM interface, shows that a design implemented according to the principles of the invention has significantly lower maximum current densities at the critical pad-to-UBM interface location than those in the traditional design. The maximum current densities are taken to be metrics for the electromigration life of the bumps in each configuration.

In summary, the novel pad structure and routing design of the invention serves to distribute current flowing in from a current delivering trace across the inner pad and into a plurality of vias connecting the inner pad to the outer pad to achieve a relatively uniform current distribution on the outer pad, thereby ameliorating electromigration in integrated circuit joints connected to the outer pad (such as flip-chip bumps) due to current crowding.

While the illustrative embodiments of the invention as presented herein address the metal traces within the die, the invention is applicable generally any integrated circuit component that includes interleaved layers of metal and dielectrics, for example, an integrated circuit die, an integrated circuit substrate, an integrated circuit chip package, a printed circuit board, etc., and which utilizes a joint such as a bump to another same or different such integrated circuit component. For example, the pad structure of the invention may be implemented within an integrated circuit substrate, a PCB, and/or an interconnect layer of a chip package at pads of the respective substrate, PCB, and/or package where the combination of current levels, changes in current direction and material sensitivity lead to electromigration problems.

Although this preferred embodiment of the present invention has been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims. It is also possible that other benefits or uses of the currently disclosed invention will become apparent over time.