Memory sub-system management based on dynamic control of wordline start voltage

A request to perform a write operation at a memory device is received. Current wordline start voltage (WLSV) information associated with a particular memory segment of the plurality of memory segments is retrieved. The write operation is performed on the particular memory segment. In a firmware record in a memory sub-system controller, information is stored indicative of a last written memory page associated with the particular memory segment on which the write operation is performed. The firmware record is managed in view of the information indicative of the last written memory page associated with the performed write operation. Each entry of the firmware record comprises one or more identifying indicia associated with a respective memory segment, at least one of the identifying indicia being a wordline start voltage (WLSV) associated with the respective memory segment.

TECHNICAL FIELD

Embodiments of the disclosure are generally related to memory sub-systems, and more specifically, are related to memory sub-system management based on wordline start voltage (WSLV) dynamically controlled by firmware.

BACKGROUND

DETAILED DESCRIPTION

Aspects of the present disclosure are directed to memory sub-system management based on dynamic control of wordline start voltage (WLSV). A memory sub-system can be a storage device, a memory module, or a combination of a storage device and memory module. Examples of storage devices and memory modules are described below in conjunction withFIG.1. In general, a host system can utilize a memory sub-system that includes one or more components, such as memory devices that store data. The host system can provide data to be stored at the memory sub-system and can request data to be retrieved from the memory sub-system.

A memory device can be made up of bits arranged in a two-dimensional grid. Memory cells are etched onto a silicon wafer in an array of columns (also hereinafter referred to as bitlines) and rows (also hereinafter referred to as wordlines). A wordline (WL) can refer to one or more rows of memory cells of a memory device that are used with one or more bitlines to generate the address of each of the memory cells. The intersection of a bitline and wordline constitutes the address of the memory cell. A block hereinafter refers to a unit of the memory device used to store data and can include a group of memory cells, a wordline group, a wordline, or individual memory cells. One or more blocks can be grouped together to form a plane of the memory device in order to allow concurrent operations to take place on each plane. The memory device can include circuitry that performs concurrent memory page accesses of two or more memory planes. For example, the memory device can include a respective access line driver circuit and power circuit for each plane of the memory device to facilitate concurrent access of pages of two or more memory planes, including different page types.

One of the existing techniques for memory management is a dynamic wordline start voltage (DWLSV) operation. In an automated dynamic wordline start voltage (ADWLSV) operation controlled at the memory device level, a page map is associated with a particular block of memory cells of a memory device. The memory device can apply one or more of an automated sequence of incremented voltages to determine the lowest voltage (e.g., wordline start voltage) at which the first page of the wordline can be programmed with valid data. The other pages of the same wordline can be programmed by the wordline start voltage determined for the first page of the wordline.

In some embodiments, a program operation does not write all the wordlines in a particular block, which leaves the particular block as an open block. An “open” block can refer to a physical block of memory cells where the pages of the block have not been completely written. In some embodiments, the block can remain open until a last page of the block is programmed. The block is closed after the last page of block is programmed. When a block is closed, the WLSV entry (i.e. the value of WLSV) for a particular block can be released and be made available for another block. Therefore, it is important to keep track of open and closed blocks in a memory sub-system in order to increase overall programming efficiency, as indicated by programming time (tprog).

Typically there is only one DWSLV storage element (a user accessible register) allotted per die to store WLSV information. This poses substantial restriction in terms of the maximum number of open blocks in a die of which the memory device can keep track, as the available space for WLSV information can be quickly exhausted as the number of open blocks increases. Additional logic circuits and storage elements would need to be incorporated in the memory device in order to perform ADWLSV at a larger scale where a large number of open blocks can be tracked.

Aspects of the present disclosure address the above and other deficiencies by moving the dynamic wordline start voltage (DWLSV) operation from being performed at a memory device level to being performed at a memory sub-system controller level by manually or semi-automatically configuring firmware of the memory sub-system controller to determine an appropriate wordline start voltage for the first page of a particular wordline. The firmware controlled DWSLV operation is abbreviated as “manual” DWSLV, or MDWLSV, though the term “manual” encompasses a certain degree of automatic operation in conjunction with manual configuration of the firmware by a user. Therefore the phrase “manual or semi-automatic” is often used in the specification. Since MDWLSV is not limited to just one storage element per die to store WLSV records, a large scale DWLSV operation is feasible, involving a large number of (e.g., hundreds of) open blocks being tracked. By moving the DWLSV operation to the firmware, the memory device design can remain unchanged, while the number of open blocks being tracked can increase from single digit to hundreds or even thousands.

Advantages of controlling the DWLSV operation at the memory sub-system controller level rather than the memory device level include, but are not limited to, shorter overall programming time (tprog), i.e. less programming time penalty without having to change storage capacity at the memory device level. Moreover, MDWLSV can also be performed for a multi-plane program operation, where multiple planes of a die can be written in parallel (e.g., concurrently), further increasing programming efficiency.

The memory sub-system110includes a DWLSV manager113that can manually or semi-automatically control WLSV for programming open blocks in the memory devices. The memory sub-system controller115can include firmware (f/w) record114accessed by the DWLSV manager113. As shown inFIG.2, the firmware record114can have identifying indicia (such as block index, page index, plane index, plane mask information) etc. stored therein. In some embodiments, the firmware record114can be a part of the DWLSV manager113. In some embodiments, the firmware record114can be a part of the local memory119. In some embodiments, at least a part of the DWLSV manager113is part of the host system110, an application, or an operating system. It is possible that in some embodiments, local media controller135includes at least a portion of DWLSV manager113and is configured to perform the functionality described herein, though one of the objectives of the present disclosure is to control the DWSLV operation at the firmware level rather than at the memory device level, and therefore local media controller135may not have any part of DWLSV manager113.

FIG.2illustrates an example data structure200of a firmware record (e.g., firmware record114) containing identifying indicia of multiple memory segments of a memory device, in accordance with some embodiments of the present disclosure. The term “memory segment” encompasses a block of memory, or a sub-block within a block of memory. A memory segment can include multiple memory pages. The physical cells of a memory block can be distributed among one or more planes. The firmware record114can also store plane mask information. The plane mask of firmware record114identifies the planes and the status of the memory blocks of those planes (e.g., good or bad). As an example, if the plane mask is 4b′0000, “4b′” identifies that 4 bits are used to describe four planes of the block. “0000” represent the planes and the status of the blocks for the planes. The least significant bit (LSB) (most right position) represents plane 0, the 2ndLSB (second most right position) represents plane 1, the second most significant bit (MSB) (second most left position) represents plane 2, and the MSB (most left position) represents plane 3. In some embodiments, more than one of the planes can be planes of the same die. “0” represents a good block. “1” represents a bad block. A bad block is a block that is no longer used to store information. “0000” represents that all the blocks of plane 0-3 are good blocks. “0001” represents that blocks of plane 1-3 are good blocks, and block of plane 0 is a bad block.

In the data structure200shown inFIG.2, an example of firmware record114is labeled as firmware DWLSV list per Logical Unit Number (LUN). Each entry of the list has multiple identifying indicia, such as block index, plane index, page index, WLSV value, and plane mask information. Each entry is referred to as a “slot” in the firmware DWLSV list. The slots are numbered as 0, 1, . . . , 7. Though eight slots are shown in the figure, the number of slots can be any arbitrary number that can be supported by the system design. In the example shown inFIG.2, a current programming request directed to a particular LUN specifies the block index, plane index, and page index. The firmware-based DWSLV manager113determines which slot has an open block (e.g., slot 2 in the example shown), retrieves WLSV information stored in the memory device for that slot. After the firmware DWLSV list is managed (i.e. cleared or updated, as discussed below with respect to the flowcharts), the WLSV value can be updated at the memory device to match the stored WLSV value at the firmware.

At operation305, the processing logic receives a request to perform a write operation at a memory device. Note that “write” operation is sometimes also referred at as “programming” operation. As mentioned above, the memory device has multiple segments (e.g., blocks), each segment containing multiple pages. Note that a block can have multiple sub-blocks, where a sub-block can refer to a collection of pages that are programmed using some common parameters. For example, the collection of pages can be associated with the same wordline with a predetermined (or retrieved) WLSV.

At operation310, the processing logic retrieves, from the memory device, current WLSV information for a particular segment of the memory device. The segment can be chosen based on whether the segment has additional capacity (“open block”) to write more data or not.

At operation315, the processing logic performs the program operation, i.e. writes data on the memory device. At operation320, the processing logic stores information (for example at local memory119) indicative of the last written memory page in the particular memory segment on which the write operation is performed. The last written memory page can indicate whether additional data can be written in the memory segment. The information stored can include one or more identifying indicia, such as block index, plane index, and plane mask of the last written page. In some embodiments, the processing logic can additionally save the WLSV of the last written page. To determine whether to also save the WLSV of the last written place, additional logic operations can be performed, as described in the example flowcharts400and500.

At operation325, the processing logic manages the firmware record (as described inFIGS.1and2) in view of the performed write operation. Managing the firmware record can involve the operation of determining whether the last written page is a last memory page of multiple pages associated with a common wordline. Responsive to determining that the last written memory page is indeed the last memory page associated with the common wordline, the WLSV in the firmware entry for the particular memory segment is cleared. This operation saves programming time, because a clearing of the firmware entry indicates that the block is not an “open’ block, but is rather a closed block. So that there is no need to keep track of WLSV value, and the WLSV value can be reused for subsequent programming operations. On the other hand, if it is determined that the last written memory page is not the last memory page associated with the common wordline, the processing logic updates the WLSV in the firmware entry for the particular memory segment. This way, the open blocks and their WLSVs are tracked. Note that the processing logic can check whether a plane mask for a memory page of the particular memory segment is compatible with the plane mask for another memory page of the particular memory segment. If the plane masks are compatible, then multiple memory pages can be programmed together.

FIG.4is a flow diagram of an example method of modifying a firmware record prior to performing a write operation, in accordance with embodiments of the present disclosure. The method400can be performed by processing logic that can include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the method400is performed by the DWLSV manager113ofFIG.1. Although shown in a particular sequence or order, unless otherwise specified, the order of the processes can be modified. Thus, the illustrated embodiments should be understood only as examples, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. Additionally, one or more processes can be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are possible.

At operation405, the processing device in the controller115maintains a record (such as firmware record114inFIG.1, also shown as firmware DWSLV list200inFIG.2) corresponding to multiple memory segments in a memory device. Each entry of the firmware record includes one or more identifying indicia associated with a respective memory segment of the multiple memory segments. At least one of the identifying indicia is a WLSV associated with the respective memory segment.

At operation410, the processing device receives a request to perform a write operation at the memory device. This operation is similar to operation305in method300.

At operation415, the processing logic retrieves current WLSV information associated with a particular memory segment. Note that processing logic can retrieve the current WLSV information from the memory device (as in operation310in method300). In some embodiments, the processing logic can retrieve the WLSV information stored currently in the firmware record, such as firmware DWSLV list200shown inFIG.2.

At operation420, the processing logic determines, based on at least one of the one or more identifying indicia associated with the particular memory segment and the current WLSV information retrieved from the memory device, whether to modify a corresponding entry for the particular memory segment in the firmware record before the requested write operation is performed. The decision of whether to modify the firmware record involves determining whether the last written memory page is a last memory page of multiple pages associated with a common wordline. Responsive to determining that the last written memory page is indeed the last memory page associated with the common wordline, the WLSV in the firmware entry for the particular memory segment is cleared (operation430). On the other hand, responsive to determining that the last written memory page is not the last memory page associated with the common wordline, the WLSV in the firmware entry is updated (operation425) for the particular memory segment. Either way, this modification of the firmware record is performed prior to the write operation (operation435). Usually MDWLSV management is not performed before the erase operation, but before the write operation.

The subsequent write operation after MDWLSV can use a “Least Recently Used” (LRU) algorithm in order to make space available for a newer entry associated with a newer memory segment. The LRU algorithm checks whether a number of entries of the firmware record satisfies a threshold number of entries. If the number of entries satisfies the threshold number of entries, a command is issued to remove, from the firmware record, the corresponding entry associated with an older memory segment.

At operation505, the processing logic receives a request to perform a write operation.

At operation510, the processing logic checks if the block record of the memory device is valid. If the block record is valid, then subsequent optimization operations are performed. Otherwise, regular programming operation is continued at operation555without the need or scope for any further optimization.

At operation515, the processing logic checks if current block matches block record entry retrieved from the memory device. If there is no match, regular programming operation is continued at operation555without the optimization. If there is a match, the operation proceeds to520.

At operation520, the processing logic checks if plane masks match for multiple pages that can be programmed using a common WL, but are distributed among multiple planes. If the plane masks match, then the method continues at operation555. On the other hand, the plane masks do not have to exactly match if they are compatible to each other. Compatibility of plane mask means block per plane information is the same between two masks, if not identical. Plane mask compatibility is used to force the memory device to resample. The programming operation can be modified (e.g., a 4-plane operation can be modified to a 3-plane operation if a plane is identified to have ‘bad’ blocks) to ensure plane mask compatibility. As mentioned above, the plane mask of firmware record114identifies the planes and the status of the memory blocks of those planes (e.g., good or bad). As illustrative examples, 4b′1110, 4b′1101, 4b′1011 and 4b′0111 are compatible. However, 4b′1001, 4b′1100 and 4b′0011 are not compatible.

At operation540, the processing logic checks whether the last written page of the firmware entry is the last page of a wordline. If it is indeed the last page, then the WLSV value for the firmware entry is cleared (operation545), indicating a closed block. If the last written page is not the last page of the wordline, then the block is still open, and the method proceeds to retrieve WLSV entry from the memory device (operation550).

The example computer system600includes a processing device602, a main memory604(e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or RDRAM, etc.), a static memory606(e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system618, which communicate with each other via a bus630.