Two step method of rapid curing a semiconductor polymer layer

A semiconductor device and method of making the semiconductor device is described. A semiconductor die is provided. A polymer layer is formed over the semiconductor die. A via is formed in the polymer layer. The polymer layer is crosslinked in a first process. The polymer layer is thermally cured in a second process. The polymer layer can comprise polybenzoxazoles (PBO), polyimide, benzocyclobutene (BCB), or siloxane-based polymers. A surface of the polymer layer can be crosslinked by a UV bake to control a slope of the via during subsequent curing. The second process can further comprise thermally curing the polymer layer using conduction, convection, infrared, or microwave heating. The polymer layer can be thermally cured by increasing a temperature of the polymer at a rate greater than or equal to 10 degrees Celsius per minute, and can be completely cured in less than or equal to 60 minutes.

TECHNICAL FIELD

The disclosure relates in general to semiconductor devices and, more particularly, to the curing of protective polymer layers on semiconductor devices by using a rapid thermal cure after crosslinking a surface of the polymer layer, for example, by subjecting the polymer layer to an ultraviolet (UV) bake.

BACKGROUND

Semiconductor devices are generally manufactured using two complex manufacturing processes, that is, front-end manufacturing, and back-end manufacturing. Front-end manufacturing involves the formation of a plurality of semiconductor die on the surface of a semiconductor wafer. Each semiconductor die is typically identical and contains circuits formed by electrically connecting active and passive components. Back-end manufacturing, especially wafer-level or panel level packaging, typically involves providing an environmentally robust encapsulation or protection of the device, formation of broader pitch interconnect structures, testing and singulation of individual semiconductor die from the finished wafer or panel. The term “semiconductor die” as used herein refers to both the singular and plural form of the words, and accordingly can refer to both a single semiconductor device and multiple semiconductor devices.

One goal of semiconductor manufacturing is to produce smaller semiconductor devices. Smaller devices typically consume less power, have higher performance, and can be produced more efficiently. In addition, smaller semiconductor devices have a smaller footprint, which is desirable for smaller end products. A smaller semiconductor die size can be achieved by improvements in the front-end process resulting in semiconductor die with smaller, higher density active and passive components. Back-end processes may result in semiconductor device packages with a smaller footprint by improvements in electrical interconnection and packaging materials.

Back-end processing can often include use of one or more insulating or polymer layers, such as PBO. PBO is a polymer used in the electronics packaging industry as an inter-level dielectric in packaging applications such as wafer level chip scale packaging (WLCSP) applications. PBO, like other insulating and polymer layers, can be photosensitive or non-photosensitive.

Insulating and polymer layers that are photosensitive can be patterned using photolithography. Photolithography involves the deposition of light sensitive material, e.g., a layer of photosensitive PBO. A pattern is typically transferred from a form of photomask to the photosensitive material using light. In an embodiment, the portion of the photosensitive material subjected to light is removed using a developer chemistry, exposing portions of the underlying layer. In another embodiment, the portion of the photosensitive material not subjected to light is removed using a developer chemistry, exposing portions of the underlying layer. The portions of the photosensitive film remaining can become a permanent part of the device structure.

Insulating and polymer layers that are not photosensitive can be patterned using photolithography and subtractive etching. Photolithography in this case involves the deposition of light sensitive material, e.g., photoresist, over the layer to be patterned, e.g., a layer of PBO. A pattern is typically transferred from a form of photomask to the photoresist using light. In one embodiment, the portion of the photoresist pattern subjected to light is removed using a solvent, exposing portions of the underlying layer to be patterned. In another embodiment, the portion of the photoresist pattern not subjected to light is removed using a solvent, exposing portions of the underlying layer to be patterned. The remaining photoresist serves as a mask protecting portions of the underlying layer. The exposed portions of the underlying layer are then removed by a subtractive etch process, typically wet etching, plasma etching, or laser ablation. The process used for the subtractive etch must have good selectivity to the photoresist layer, i.e., it must etch the underlying PBO or polymer layer while leaving the photoresist mask intact. Following the subtractive etch, the remainder of the photoresist is removed, leaving behind a patterned layer which becomes a permanent part of the device structure.

After photo processing the insulating, polymer, or PBO layer (i.e. by coating, exposing, and developing the photosensitive PBO or by covering the non-photosensitive PBO with a photoresist and performing subtractive etching) the polymer is cured at high temperatures to optimize the final film properties, reliability, and performance of the device.

As practiced in the prior art, and as per vendor recommendations, PBO or polymer curing is generally performed in a box oven or in a vertical furnace in a controlled nitrogen (N2) environment that requires slowly increasing a temperature of the box oven or vertical furnace for the curing of the PBO or polymer. Two types of PBOs, polymers, or insulating layers are commonly available in the market today: (1) a high cure temperature version, here referred to as standard PBO, standard polymer, or standard insulating layer; and a low cure temperature version, referred to as low temperature PBO, low temperature polymer, or low temperature insulating layer.FIG. 1Aillustrates a typical temperature profile2for curing standard PBO in a box oven or vertical furnace as known in the art. A first or ramp-up portion4of temperature profile2is the period in which temperature is increased from room temperature (about 20-25° C.) to a maximum curing temperature. During ramp-up portion4, temperature is slowly increased at a rate of approximately 2.1° C. per minute. A top or peak portion6of temperature profile2, inFIG. 1Ashows a desirable curing temperature of about 340° C. is achieved and maintained for a period of approximately one hour or 60 minutes. Typical peak temperatures for curing standard PBO in box ovens range from approximately 320° C. to 340° C. A final or ramp-down portion8of temperature profile2shows that the temperature is slowly decreased at a rate of approximately 3.2° C. per minute until the PBO layer and box oven or vertical furnace has cooled from the curing temperature to room temperature.

FIG. 1Billustrates a typical temperature profile10for curing low temperature PBO in a box oven or vertical furnace as known in the art. A first or ramp-up portion12of temperature profile10is the period in which temperature is increased rapidly from room temperature (about 20-25° C.) to 100° C. The temperature is held at approximately 100° C. for a period of approximately 30 minutes, as indicated by second or constant portion13of temperature profile10. Another ramp-up or third portion14of temperature profile10is the period in which temperature is increased from approximately 100° C. to a maximum curing temperature as indicated by top or peak portion15. During ramp-up portion14, temperature is slowly increased at a rate of approximately 1.67° C. per minute. Top or peak portion15of temperature profile10, inFIG. 1Bshows a desirable curing temperature of about 200° C. is achieved and maintained for a period of approximately one hour or 60 minutes. Typical peak temperatures for curing low cure PBO in box ovens range from 175° C. to 200° C. A final or ramp-down portion16of temperature profile10shows that the temperature is slowly decreased at a rate of approximately 2.2° C. per minute until the PBO layer and box oven or vertical furnace has cooled from the curing temperature to room temperature.

By slowing a rate at which temperature increases, particularly, for example, during ramp-up portion4of temperature profile2or during ramp up portion14of temperature profile10, a contour or slope of the vias formed within the PBO layer is maintained and does not undesirably deform during heating or curing. As shown inFIGS. 1A and 1B, an entire cure cycle as practiced in the prior art generally requires multiple hours to complete, 4 to 5 hours being typical. See, e.g., HD8820 Process Guide, published by HD Microsystems (August 2005) relating to standard PBO treatment, and HD8930 Process Guide, published by HD Microsystems (May 2009) relating to low temperature PBO treatment. Curing of PBO using the conventional techniques described above with respect toFIGS. 1A and 1Bis performed by major Outsourced Semiconductor Assembly and Test (OSAT) providers and WLCSP providers in the fabrication of WLCSPs such as, for example, Amkor, Advanced Semiconductor Engineering (ASE), Taiwan Semiconductor Manufacturing Company (TSMC), Siliconware Precision Industries Co. Ltd. (SPIL), and Stats-Chippac.

SUMMARY

The foregoing and other aspects, features, and advantages will be apparent to those artisans of ordinary skill in the art from the DESCRIPTION and DRAWINGS, and from the CLAIMS. Accordingly, in an aspect, a method of making a semiconductor device can comprise providing semiconductor die, forming a polymer layer over the semiconductor die, forming a via in the polymer layer, crosslinking a surface of the polymer layer in a first process, and thermally curing the polymer layer in a second process.

The method of making the semiconductor device can further comprise forming the polymer layer as a layer of polybenzoxazoles (PBO), polyimide, benzocyclobutene (BCB), siloxane-based polymer, or epoxy-based polymers. The polymer layer can be exposed to ultraviolet (UV) radiation to crosslink the surface of the polymer layer in the first process to subsequently control a slope of the via during the second process. The polymer layer can be cured in the second process by using at least one thermal process selected from the group consisting of conduction, convection, infrared, and microwave heating. The polymer layer can be cured by increasing a temperature of the polymer layer at a rate greater than or equal to 10 degrees Celsius per minute. The polymer layer can be completely thermally cured, comprising a temperature ramp up, a peak temperature dwell, a temperature ramp down, and a complete thermal anneal, in a time of less than or equal to 60 minutes. The polymer layer can be formed as a permanent portion of the semiconductor device. The polymer layer can be thermally cured by heating the polymer layer at a temperature greater than or equal to 200 degrees Celsius for a time of less than 30 minutes. The polymer layer can be exposed to UV radiation at an elevated temperature in a range of 100-200 degrees Celsius. The polymer layer can be thermally cured in a low O2environment in which O2comprises less than or equal to 100 parts per million of the low O2environment. A witness mark can be formed as a discontinuity in a slope of the via along a portion of the via.

In another aspect, a method of making a semiconductor device can comprise forming a polymer layer, forming a via in the polymer layer, crosslinking the polymer layer, and curing the polymer layer.

The method of making the semiconductor device can further comprise forming the polymer layer as a layer of PBO, polyimide, BCB, siloxane-based polymer, epoxy-based polymer, or other polymer formed as a permanent portion of the semiconductor device. The polymer layer can be exposed to UV radiation to crosslink a surface of the polymer layer and to subsequently control a slope of the via during the curing. The polymer layer can be thermally cured by using at least one thermal process selected from the group consisting of conduction, convection, infrared, and microwave heating. The polymer layer can be thermally cured by increasing a temperature of the polymer layer at a rate greater than or equal to 10 degrees Celsius per minute. The polymer layer can be completely thermally cured, comprising a temperature ramp up, a peak temperature dwell, a temperature ramp down, and a complete thermal anneal, in a time less than or equal to 60 minutes. The polymer layer can be cured to a tensile strength of greater than or equal to 110 megapascals, an elongation to failure of greater than or equal to 45 percent, and a modulus of elasticity of less than or equal to 2.4 gigapascals. The via can be formed with an average wall angle greater than or equal to 50 degrees. The polymer layer can be exposed to UV radiation at an elevated temperature in a range of 100-200 degrees Celsius. A witness mark can be formed along a portion of the via.

In another aspect, a method of making a semiconductor device can comprise forming a via in an insulating layer, stabilizing the insulating layer, and curing the insulating layer after stabilizing the insulating layer.

The method of making the semiconductor device can further comprise forming the insulating layer as polymer layer comprising PBO, polyimide, BCB, siloxane-based polymer, or epoxy-based polymer. A surface of the insulating layer can be stabilized to control a slope of the via during curing. The insulating layer can be thermally cured using at least one thermal process selected from the group consisting of conduction, convection, infrared, and microwave heating. The insulating layer can be thermally cured by increasing a temperature of the insulating layer at a rate greater than or equal to 10 degrees Celsius per minute. The insulating layer can be completely thermally cured in a time less than or equal to 60 minutes. The insulating layer can be UV baked at a temperature different than a temperature at which the insulating layer is cured. The insulating layer can be cured in an environment of less than or equal to 100 parts per million O2. A witness mark can be formed around the via.

DETAILED DESCRIPTION

The present disclosure includes one or more embodiments in the following description with reference to the figures, in which like numerals represent the same or similar elements. It will be appreciated by those skilled in the art that the description is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the disclosure as defined by the appended claims and their equivalents as supported by the following disclosure and drawings. In the description, numerous specific details are set forth, such as specific configurations, compositions, and processes, etc., in order to provide a thorough understanding of the disclosure. In other instances, well-known processes and manufacturing techniques have not been described in particular detail in order to not unnecessarily obscure the disclosure. Furthermore, the various embodiments shown in the FIGs. are illustrative representations and are not necessarily drawn to scale.

The layers can be patterned using photolithography. Patterning is the basic operation by which portions of the top layers on the semiconductor wafer surface are removed. Portions of the semiconductor wafer can be removed using photolithography, photomasking, masking, oxide or metal removal, photography and stenciling, and microlithography. Photolithography includes forming a pattern in reticles or a photomask and transferring the pattern into the layer to be patterned such as surface layers of the semiconductor wafer. Photolithography forms the horizontal dimensions of active and passive components on the surface of the semiconductor wafer in a two-step process. First, the pattern on the reticle or masks is transferred into a layer of photoresist. Photoresist is a light-sensitive material that undergoes changes in structure and properties when exposed to light. The process of changing the structure and properties of the photoresist occurs as either negative-acting photoresist or positive-acting photoresist. Second, the photoresist layer is transferred into the wafer surface. The transfer occurs when etching removes the portion of the top layers of semiconductor wafer not covered by the photoresist. Alternatively, some types of materials are patterned by directly depositing material into the areas or voids formed by the photoresist or by a previous deposition/etch process using techniques such as electroless and electrolytic plating. The chemistry of photoresists is such that the photoresist remains substantially intact and resists removal by chemical etching solutions or plating chemistries while the portion of the top layers of the semiconductor wafer not covered by the photoresist is removed or is added to by plating. The process of forming, exposing, and removing the photoresist, as well as the process of removing a portion of the semiconductor wafer or adding to a portion of the wafer can be modified according to the particular resist used and the desired results.

In negative-acting photoresists, photoresist is exposed to light and is changed from a soluble condition to an insoluble condition in a process known as polymerization. In polymerization, unpolymerized material is exposed to a light or energy source and polymers form a cross-linked material that is etch-resistant. In most negative resists, the polymers are polyisopremes. Removing the soluble portions (i.e. the portions not exposed to light) with chemical solvents or developers leaves a hole in the resist layer that corresponds to the opaque pattern on the reticle. A mask whose pattern exists in the opaque regions is called a clear-field mask.

In positive-acting photoresists, photoresist is exposed to light and is changed from relatively nonsoluble condition to much more soluble condition in a process known as photosolubilization. In photosolubilization, the relatively insoluble resist is exposed to the proper light energy and is converted to a more soluble state. The photosolubilized part of the resist can be removed by a solvent in the development process. The basic positive photoresist polymer is the phenol-formaldehyde polymer, also called the phenol-formaldehyde novolak resin. Removing the soluble portions (i.e. the portions exposed to light) with chemical solvents or developers leaves a hole in the resist layer that corresponds to the transparent pattern on the reticle. A mask whose pattern exists in the transparent regions is called a dark-field mask.

After removal of the top portion of the semiconductor wafer not covered by the photoresist, the remainder of the photoresist is removed, leaving behind a patterned layer.

Alternatively, photolithography can be accomplished without the use of a photoresist when the material to be patterned is itself photosensitive. In this case, the photosensitive material is coated on the device surface using spin coating, lamination, or other suitable deposition technique. A pattern is then transferred from a photomask to the photosensitive material using light in an operation typically called exposure. In an embodiment, the portion of the photosensitive material subjected to light is removed, or developed, using a solvent, exposing portions of the underlying layer. Alternatively, in another embodiment, the portion of the photosensitive material not subjected to light is removed, or developed, using a solvent, exposing portions of the underlying layer. The remaining portions of the photosensitive film can become a permanent part of the device structure.

Depositing a thin film of material over an existing pattern can exaggerate the underlying pattern and create a non-uniformly flat surface. A uniformly flat surface is required to produce smaller and more densely packed active and passive components. Planarization can be used to remove material from the surface of the wafer and produce a uniformly flat surface. Planarization involves polishing the surface of the wafer with a polishing pad. An abrasive material and corrosive chemical are added to the surface of the wafer during polishing. Alternatively, mechanical abrasion without the use of corrosive chemicals is used for planarization. In some embodiments, purely mechanical abrasion is achieved by using a belt grinding machine, a standard wafer backgrinder, or other similar machine. The combined mechanical action of the abrasive and corrosive action of the chemical removes any irregular topography, resulting in a uniformly flat surface.

The electrical system can be a stand-alone system that uses the semiconductor device to perform one or more electrical functions. Alternatively, the electrical system can be a subcomponent of a larger system. For example, the electrical system can be part of a cellular phone, personal digital assistant (PDA), digital video camera (DVC), or other electronic communication device. Alternatively, the electrical system can be a graphics card, network interface card, or other signal processing card that can be inserted into a computer. The semiconductor package can include microprocessors, memories, application specific integrated circuits (ASIC), logic circuits, analog circuits, RF circuits, discrete devices, or other semiconductor die or electrical components. Miniaturization and weight reduction are essential for the products to be accepted by the market. The distance between semiconductor devices must be decreased to achieve higher density.

By combining one or more semiconductor packages over a single substrate, manufacturers can incorporate pre-made components into electronic devices and systems. Because the semiconductor packages include sophisticated functionality, electronic devices can be manufactured using less expensive components and a streamlined manufacturing process. The resulting devices are less likely to fail and less expensive to manufacture resulting in a lower cost for consumers.

FIG. 2Ashows a cross-sectional view of a portion of semiconductor device or package20similar to the devices described above. Semiconductor device20can comprise a number of layers of PBO used as semiconductor die packaging for forming insulating layers within the semiconductor device. More specifically, semiconductor device20comprises a semiconductor die22comprising active surface24and contact pad26disposed within, and surrounded by, encapsulant28. Semiconductor device20can comprise a first polymer or insulating layer30, that also includes PBO, polyimide, benzocyclobutene (BCB), siloxane-based polymer, epoxy-based polymer, or other suitable material, which is disposed over active surface24and partially covers contact pad26. First polymer layer30can be a standard PBO layer or a low temperature PBO layer. A via or opening32with a sloped sidewall34is formed completely through first polymer layer30to expose a portion of contact pad26. A conductive interconnect structure40, such as a copper pillar, is formed over contact pad26, over polymer layer30and within via32, and partially surrounded by encapsulant28to provide electrical interconnection between semiconductor die22and points external to semiconductor device20.

A second polymer or insulating layer42, that also includes PBO, polyimide, BCB, siloxane-based polymer, epoxy-based polymer, or other suitable material, is formed over encapsulant28and interconnect structure40. In an embodiment, second polymer layer42can be a low cure PBO layer or a standard PBO layer. A via or opening44with a sloped sidewall46is formed completely through second polymer layer42to expose a portion of interconnect structure40. A conductive layer48comprising one or more conductive layers is formed as part of a redistribution layer (RDL), such as a fan-out RDL, to route or direct electrical signals from semiconductor die22to points external to semiconductor device20.

A third polymer or insulating layer50, that also includes PBO, polyimide, BCB, siloxane-based polymer, epoxy-based polymer, or other suitable material, is formed over conductive layer48and second polymer layer42. In an embodiment, third polymer layer50can be a low cure PBO layer instead of a standard PBO layer. A via or opening52with a sloped sidewall54is formed completely through the third polymer layer50to expose a portion of conductive layer48. An under bump metallization (UBM) layer56comprising one or more conductive layers is formed within via52through third polymer layer50to assist in routing or directing electrical signals from semiconductor die22to points external to semiconductor device20and improve a mechanical and electrical connection between conductive layer48and a subsequently formed interconnect structure such as a conductive bump or solder bump58.

Thus,FIG. 2Ashows three vias, vias32,44, and52, are formed in three polymer or insulating layers, that is polymer layers30,42, and50, respectively. In an embodiment, polymer layer30is either a standard or low temperature polymer layer, while polymer layers42and50are low cure polymer layers, such as low cure PBO. Vias32,44, and52can be formed using laser drilling, mechanical drilling, deep reactive ion etching (DRIE), or other suitable process. In an embodiment, polymer layers32,44, and52are photoimagable layers that are formed and patterned (by coating, exposing, and developing as described above) to create vias32,44, and52, which can extend completely through the polymer layers. After formation of vias32,44, and52, polymer layers30,42, and50are cured.

FIG. 2Bshows a cross-sectional view of a portion of semiconductor device or package58similar to the devices described above, including semiconductor device20ofFIG. 2A. Semiconductor device58can comprise a number of layers of PBO used as semiconductor die packaging for forming insulating layers within the semiconductor device. More specifically, semiconductor device58comprises a semiconductor die22comprising active surface24and contact pad26, similar to semiconductor die22of semiconductor device20shown inFIG. 2A. Semiconductor die22can also be disposed within, and surrounded by, an encapsulant. Semiconductor device58, similar to semiconductor device20, can comprise a first polymer or insulating layer30, that also includes PBO, polyimide, BCB, siloxane-based polymer, epoxy-based polymer, or other suitable material, which is disposed over active surface24and partially covers contact pad26. First polymer layer30can be a standard PBO layer or a low temperature PBO layer. A via or opening32with a sloped sidewall34is formed completely through first polymer layer30to expose a portion of contact pad26.

A second polymer or insulating layer59, that also includes PBO, polyimide, BCB, siloxane-based polymer, epoxy-based polymer, or other suitable material, is formed over semiconductor die22, contact pad26, and first polymer layer30. In an embodiment, second polymer layer59can be a low cure PBO layer or a standard PBO layer. A via or opening60with a sloped sidewall46is formed completely through second polymer layer59to expose a portion of contact pad26. A conductive layer62comprising one or more conductive layers is formed as part of an RDL, such as a fan-out RDL, to route or direct electrical signals from semiconductor die22to points external to semiconductor device58.

A third polymer or insulating layer63, that also includes PBO, polyimide, BCB, siloxane-based polymer, epoxy-based polymer, or other suitable material, is formed over conductive layer62and second polymer layer59. In an embodiment, third polymer layer63can be a low cure PBO layer or a standard PBO layer. A via or opening64with a sloped sidewall65is formed completely through the third polymer layer63to expose a portion of conductive layer62. A UBM layer66comprising one or more conductive layers is formed within via64through third polymer layer63to assist in routing or directing electrical signals from semiconductor die22to points external to semiconductor device58and improve a mechanical and electrical connection between conductive layer62and a subsequently formed interconnect structure such as a conductive bump or solder bump67.

Thus,FIG. 2Bshows three vias, vias32,60, and64, are formed in three polymer or insulating layers, that is polymer layers30,59, and63, respectively. In an embodiment, polymer layer30is either a standard or low temperature polymer layer, while polymer layers59and63are low cure polymer layers, such as low cure PBO. Vias32,60, and64can be formed using laser drilling, mechanical drilling, DRIE, or other suitable process. In an embodiment, polymer layers32,60, and64are photoimagable layers that are formed and patterned (by coating, exposing, and developing as described above) to create vias32,60, and64, which can extend completely through the polymer layers. After formation of vias32,60, and64, polymer layers30,59, and63are cured.

A primary factor limiting the curing speed of polymer layers in semiconductor devices or packages, such as polymer layers30,42, and50of semiconductor device20inFIG. 2Aand polymer layers30,59, and63of semiconductor device58inFIG. 2Bis control of sloped sidewalls34,46, and54, as well as sloped sidewalls34,61, and65, respectively. A slope of via sidewalls that is initially steep after formation of the via tends to round significantly and become less steep if the polymer layer in which the via is formed is cured through a process in which temperature is increased too rapidly. Thus, as discussed above with respect toFIGS. 1A and 1B, as known in the prior art, curing of polymer layers, such as PBO layers, has typically been achieved by increasing a temperature of the polymer or PBO at a rate on the order of approximately 2° C. per minute. Accounting for rounded vias with less steeply formed sidewalls can require larger metal capture pads such as portions of contact pad26, interconnect structure40, conductive layers48and63, as well as UBM layers56and66in order to provide good electrical interconnection through the vias while effectively covering the vias. Enlarging contact pads or capture pads increases an effective pitch of packaging, which requires a larger area for a same number of connections. Increasing the pitch of package interconnections is contrary to the objective of providing smaller, more compact packages and semiconductor devices. Accordingly, less steeply formed sidewalls have been avoided by requiring gradual increases in temperature for the curing polymer layers and PBO layers used within semiconductor packaging. A comparison of via slope with respect to curing the material in which the via is formed is made below with respect toFIGS. 3A-3C.

Each ofFIGS. 3A-3Cshows vias including sidewalls of different profiles, contours, or slopes formed in the polymer layers. The different slopes of the via sidewalls, as discussed in greater detail below, result from how the polymer layers are cured after the vias are formed in the polymer layers.FIG. 3Ashows an enlarged cross sectional view of a representative profile, contour, or via slope for a via formed in a polymer or insulating layer, such as PBO, polyimide, BCB, siloxane-based polymer, epoxy-based polymer, or other suitable material that is cured using a traditional oven cure at 340° C. for approximately 5 hours.FIG. 3Ashows a substrate70that can include a semiconductor die similar to semiconductor die22, shown previously inFIGS. 2A and 2B. Similarly, substrate70can include a composite substrate or wafer including a number of features or elements such as semiconductor die, interconnect structures, RDLs, and encapsulant. A polymer or insulating layer72, which can be similar to any of polymer layers30,42,50,59, or63is formed over substrate70. A via or opening74can be formed in polymer layer72using laser drilling, mechanical drilling, DRIE, or other suitable process. In an embodiment, polymer layer72can be a photoimagable PBO layer that is formed and patterned (by coating, exposing, and developing as described above) to create via74. Via74can extend completely through polymer layer72to expose a portion of substrate70. The exposed portion of substrate70can include a contact pad, RDL, interconnect structure, or other conductive feature for transmitting electrical signals between points on substrate70and points external to the substrate. Via74includes via sidewall76that is sloped and substantially vertical after the formation of the via. In an embodiment, sidewall76of via74is formed with an angle relative to substrate70that is greater than or equal to 50 degrees.

Substrate70and PBO layer72can be cured at an elevated temperature using a conventional box oven or vertical furnace so that the profile of sidewall76of via74are set or fixed with a profile or vertical slope that is similar, or substantially identical, to the profile or vertical slope of sidewall76before curing. A similarity in the profile or vertical slope of sidewall76before and after curing allows for package design and layout constraints based on similar via shapes and sizes. However, the long cure cycle time of approximately 4-5 hours for box oven or vertical furnace curing adds significantly to the overall process cycle time for the packaging of semiconductor devices such as WLCSPs. The delay can be increased for multiple cures performed for multiple layers. The long cure cycle time results in an economic disadvantage of more parts required for work in progress (WIP) in order to deliver the same number of parts at a given rate. Thus, curing using conventional box ovens and vertical furnaces results in higher inventory numbers, additional costs, and more parts at risk of misprocessing during a given cure cycle.

After formation, via74can be subsequently filled with Al, Cu, Sn, Ni, Au, Ag, titanium (Ti), tungsten (W), poly-silicon, or other suitable electrically conductive material using PVD, CVD, electrolytic plating, electroless plating process, or other suitable metal deposition process for subsequent electrical interconnection.

FIG. 3Bshows a representative profile, contour, or vertical via slope for a via formed in a polymer layer such as PBO, polyimide, BCB, siloxane-based polymer, epoxy-based polymer, or other suitable material that is cured in a one-step process using thermal curing. For example, thermal curing can be accomplished using a hotplate for a rapid 15 minute cure. The cure is accomplished without an additional step of crosslinking a surface of the polymer, by using, e.g., a UV bake.FIG. 3Bshows a substrate80and a polymer or insulating layer82similar to substrate70and PBO layer72, respectively, fromFIG. 3A. A via or opening84, similar to via74fromFIG. 3A, can be formed in PBO layer82using laser drilling, mechanical drilling, DRIE, or other suitable process. In an embodiment, polymer layer82is a photoimagable layer that is formed and patterned (by coating, exposing, and developing as described above) to create via84. Via84can extend completely through insulating layer82to expose a portion of substrate80. The exposed portion of substrate80can include a contact pad, RDL, interconnect structure, or other conductive feature for transmitting electrical signals between points on substrate80and points external to the substrate. Via84includes via sidewall86comprising a profile, slope, or taper that can be substantially vertical after its initial formation and before undergoing thermal curing.

Substrate80and polymer layer82are rapidly heated using a thermal process comprising conduction, convection, infrared, microwave heating, or other suitable process, and can also be heated on a hot plate. Polymer layer82can be thermally cured by increasing a temperature of the polymer layer at a rate greater than or equal to about 10 degrees Celsius per minute. Polymer layer82can also be thermally cured by heating the polymer layer to a temperature greater than or equal to 200 degrees Celsius and then maintaining the temperature of greater than or equal to 200 degrees Celsius for a period of time less than or equal to about 30 minutes such that complete thermal curing the polymer layer, comprising a temperature ramp up, a peak temperature dwell, a temperature ramp down, and a complete thermal anneal, are accomplished in a time of less than or equal to about 60 minutes. In an embodiment, substrate80and polymer layer82can be almost instantaneously heated within a period of about 1-60 seconds, for example on a hot plate, from a temperature of about 20-25° C. to a temperature of about 350° C. for a standard PBO layer or about 220° C. for low temperature PBO layer. Polymer or PBO layer82can then remain at a temperature of about 220° C. or 350° C., respectively, for a time of less than 30 minutes, for a time of approximately 15 minutes, or for a time of less than 15 minutes to thermally cure the polymer layer.

As a result of the rapid heating of polymer layer82, a profile, slope, or taper of sidewall86of via84after thermal curing is not constant, set, or fixed with respect to a profile, slope, or taper of sidewall86before curing. Instead, the rapid heating of polymer layer82causes the polymer layer to soften and for sidewall86to relax and flow to form a smaller relative angle, or average relative angle, between substrate80and a top or upper surface of polymer layer82opposite substrate80, as shown inFIG. 3B. According to a possible theory, the relaxation and flow of sidewall86is due to the rapidly increasing or ramping temperature exceeding a glass transition temperature (Tg) of polymer layer82, which advances during the thermal cure. If the increasing or ramping temperature of polymer layer82exceeds the Tgof the polymer layer before the polymer layer has had an opportunity to thermally cross-link, the polymer layer will tend to soften and flow, thereby creating a shallower via profile or a profile with a smaller average relative angle between a surface of substrate80and a surface of polymer layer82opposite the surface of the substrate.

A dissimilarity in the profile or vertical slope of sidewall86before and after curing requires package design and layout constraints to account for via sizes before and after curing, which typically increases via pitch. A dissimilarity in the profile or vertical slope of sidewall86before and after curing is also reflected in the differences in slope betweenFIGS. 3A and 3Bsince the slope shown inFIG. 3Aapproximates the slope of via84before undergoing rapid thermal curing, as described above. After formation, via84can be subsequently filled with Al, Cu, Sn, Ni, Au, Ag, Ti, W, poly-silicon, or other suitable electrically conductive material using PVD, CVD, electrolytic plating, electroless plating process, or other suitable metal deposition process for subsequent electrical interconnection.

FIG. 3Cshows a representative profile, contour, or vertical via slope for a via formed in a polymer layer such as PBO, polyimide, BCB, siloxane-based polymer, epoxy-based polymer, or other suitable material that is cured in a two-step process comprising crosslinking a surface of the polymer in a first process and thermally curing the polymer layer in a second process. For example, thermal curing can be accomplished using a hotplate for a rapid 15 minute cure after crosslinking a surface of the polymer, by using, e.g., a UV bake.FIG. 3Cshows a substrate90and a polymer or insulating layer92similar to substrate80and PBO layer82, respectively, fromFIG. 3B. A via or opening94is formed in polymer layer92using laser drilling, mechanical drilling, DRIE, or other suitable process. In an embodiment, polymer layer92is a photoimagable layer that is formed and patterned (by coating, exposing, and developing as described above) to create via94. Via94can extend completely through polymer layer92to expose a portion of substrate90. The exposed portion of substrate90can include a contact pad, RDL, interconnect structure, or other conductive feature for transmitting electrical signals between points on substrate90and points external to the substrate. Via94includes via sidewall96that is sloped and can be substantially vertical after the formation of the via. In an embodiment, sidewall96of via94is formed with an average angle relative to substrate90that is greater than or equal to about 50 degrees.

After formation of via94and before curing of polymer layer92using a thermal process comprising conduction, convection, infrared, microwave heating, or other suitable process, the polymer layer undergoes a first process to crosslink a surface of the polymer layer, such as a UV bake. In an embodiment, the UV bake can occur at a temperature in a range of about 100-200° C. for 0-3 minutes or 1-2 minutes. Additionally, the UV bake can occur at a temperature of 140-180° C. for a period of about 60-140 seconds. By treating polymer layer92with UV exposure at an elevated temperature prior to the cure step, a profile of via94, including the slope or contour of sidewall96, is stabilized by cross-linking the surface of polymer layer92. The temperature of the UV bake should be below the glass transition temperature (Tg) of polymer layer92to prevent flow of the polymer layer and cause undesired via flow or deformation of the via. On the other hand, the temperature of the UV bake should be high enough to ensure sufficient cross-linking of a surface of polymer layer92, including a surface or sidewall96, to stabilize the polymer layer during a subsequent second process such as thermal curing. The stabilized surface of polymer layer92, including sidewall96, prevents the polymer layer from softening or flowing such that a profile, contour, or slope of sidewall96does not relax and flow to form a smaller average relative angle between substrate90and a top or upper surface of polymer layer92opposite substrate90during the thermal curing process.

After the crosslinking of the surface of polymer layer92, including via94, substrate90and polymer layer92undergo a second process. The second process can comprise rapid thermal curing comprising conduction, convection, infrared, microwave heating, or other suitable process, and can also be heated on a hot plate. Polymer layer92can be thermally cured by increasing a temperature of the polymer layer at a rate greater than or equal to about 10 degrees Celsius per minute. Polymer layer92can also be thermally cured by heating the polymer layer to a temperature greater than or equal to 200 degrees Celsius and then maintaining the temperature of greater than or equal to 200 degrees Celsius for a period of time less than or equal to about 30 minutes such that complete thermal curing the polymer layer, comprising a temperature ramp up, a peak temperature dwell, a temperature ramp down, and a complete thermal anneal, are accomplished in a time of less than or equal to about 60 minutes. In an embodiment, substrate90and polymer layer92can be almost instantaneously heated within a period of about 1-60 seconds, for example on a hot plate, from a temperature of about 20-25° C. to a temperature of greater than or equal to about 200° C. Polymer layer92can then remain at a temperature of greater than or equal to about 200° C., respectively, for a time of less than 30 minutes, for a time of approximately 15 minutes, or for a time of less than 15 minutes to thermally cure the polymer layer. Optionally, the thermal curing process can be in a low oxygen environment in which O2comprises less than or equal to 100 parts per million of the low oxygen environment.

In an embodiment, polymer layer92is a layer of standard PBO that is almost instantaneously heated from room temperature to a temperature of about 350° C. in a low oxygen environment. A low oxygen environment can include an environment in which the ambient atmosphere includes a concentration of O2less than 100 parts per million (PPM). In an embodiment, Substrate90and polymer layer92are heated by a hot plate from a temperature of about 20-25° C. to a temperature of about 350° C. within a period of about 1-60 seconds. Polymer layer92then remains at a temperature of 350° C. for a time of less than 30 minutes, for a time of approximately 15 minutes, or for a time of less than 15 minutes to thermally cure the PBO layer and to establish final film properties for the PBO layer. As shown inFIG. 3C, an average slope or angle of sidewall96is similar to the average slope or angle of sidewall76that results from a conventional 4-5 hour curing process that includes a gradual increase in temperature within a box over or vertical furnace as described above with respect toFIG. 1andFIG. 3A. Because the UV bake of polymer layer92causes cross-linking of the PBO layer, the rapid heating of polymer layer92does not cause the PBO layer to soften and for sidewall96to relax and flow to form a smaller average relative angle as shown inFIG. 3Bwith respect to sidewall86of via84.

In another embodiment, polymer layer92can be a low cure PBO that is almost instantaneously heated from room temperature to a temperature of about 220° C. in a low oxygen environment. A low oxygen environment can include an environment in which the ambient atmosphere includes a concentration of O2less than 100 PPM oxygen. In an embodiment, Substrate90and polymer layer92are heated by a hot plate from a temperature of about 20-25° C. to a temperature of about 220° C. within a period of about 1-60 seconds. Polymer layer92then remains at a temperature of 220° C. for a time of less than 30 minutes, for a time of approximately 15 minutes, or for a time of less than 15 minutes to thermally cure the PBO layer and to establish final film properties for the PBO layer. As shown inFIG. 3C, an average slope or angle of sidewall96is similar to the average slope or angle of sidewall76that results from a conventional 4-5 hour curing process that includes a gradual increase in temperature within a box over or vertical furnace as described above with respect toFIG. 1andFIG. 3A. Because the UV bake of polymer layer92causes cross-linking of the PBO layer, the rapid heating of polymer layer92does not cause the PBO layer to soften and for sidewall96to relax and flow to form a smaller average relative angle as shown inFIG. 3Bwith respect to sidewall86of via84.

As a result, the profile, contour, or slope of sidewall96of via94, as shown inFIG. 3C, is controlled such that the average slope is similar to the average slope of sidewall76of via74, shown inFIG. 3A, which results from a conventional box oven or vertical oven curing process employing a gradual increase or ramp up temperature. The average slope of sidewall96of via94is also similar before and after curing of polymer layer92. Therefore, the more rounded and shallower via profile shown inFIG. 3B, which results from a rapid hot plate cure without the UV bake, is avoided. By maintaining a similar profile or average slope for sidewall96before and after curing, packaging can be designed by considering a single, or similar, set of layout constraints that account for via size both before and after curing.

The profile, contour, or slope of sidewall96of via94, as shown inFIG. 3C, can further comprise a witness mark95. Witness mark95can be formed as a discontinuity in a slope of via94that extends along a portion of sidewall96of via94. Witness mark95can extend along an entirety of the sidewall96of via94to completely encircle at least a portion of the via, and be disposed completely around the via. Witness mark95can be formed on a surface or skin of polymer layer92, and accordingly to one possible theory is formed as a stretch mark, particularly on a surface of PBO, that results from the described two-step process, including crosslinking a surface of the polymer layer, using for example, a UV bake, and thermally curing the polymer layer after the crosslinking or UV bake. Witness mark95can be seen in a cross-sectional side view as well as a plan or top view of sidewalls96of via94. Witness mark95can serve as an indication in a semiconductor device or product that a two-step polymer curing process, as described herein, has been utilized.

After formation of via94, including witness mark95, via94can be subsequently filled with Al, Cu, Sn, Ni, Au, Ag, Ti, W, poly-silicon, or other suitable electrically conductive material using PVD, CVD, electrolytic plating, electroless plating process, or other suitable metal deposition process for subsequent electrical interconnection.

FIGS. 4A-4Cillustrate, in graphical form, how mechanical material properties of standard PBO films vary based on cure conditions.FIG. 4Ashows results for the tensile strength of materials cured under four different curing conditions: (1) a six minute hot plate cure in a low O2environment, (2) a 15 minute hot plate cure in a low O2environment, (3) a 30 minute hot plate cure in a low O2environment, and (4) a 4-5 hour conventional box oven cure. The tensile strength values for each of the four conditions are an average of the values obtained for five different units.

FIG. 4Bshows results, in graphical form, of elongation for materials cured under four different curing conditions: (1) a six minute hot plate cure in a low O2environment, (2) a 15 minute hot plate cure in a low O2environment, (3) a 30 minute hot plate cure in a low O2environment, and (4) a 4-5 hour conventional box oven cure. The elongation percentages for each of the four conditions are an average of the values obtained for five different units.

FIG. 4Cshows, in graphical form, results of a modulus of elasticity for materials cured under four different curing conditions: (1) a six minute hot plate cure in a low O2environment, (2) a 15 minute hot plate cure in a low O2environment, (3) a 30 minute hot plate cure in a low O2environment, and (4) a 4-5 hour conventional box oven cure. The modulus of elasticity for each of the four conditions is an average of the values obtained for five different units.

The information shown graphically inFIGS. 4A-4Cis also reproduced below in tabular form as part of Table 1. The values presented in Table 1 are an average value for lots of 5 units tested after having been cured under the conditions indicated.

Thus, as shown inFIGS. 4A-4Cand in Table 1, mechanical properties are within acceptable operating tolerances and are essentially equivalent for a PBO layer cured using a conventional box oven at 340° C. for 60 minutes and for rapid cures of PBO at 350° C. for 15 minutes.

Additional information regarding weight loss temperature is also presented below in Table 2 for lots 1-4 based on the four different curing conditions of: (1) a six minute hot plate cure in a low O2environment, (2) a 15 minute hot plate cure in a low O2environment, (3) a 30 minute hot plate cure in a low O2environment, and (4) a 4-5 hour conventional box oven cure. As shown below in Table 2, weight loss temperature increases with increasing cure time and substantially plateaus for hot plate cures performed at 350° C. for about 15 minutes.

FIGS. 5A-5Cillustrate, in graphical form, how mechanical material properties of low temperature PBO films vary based on cure conditions.FIG. 5Ashows results for the tensile strength of materials cured under four different curing conditions: (1) a six minute hot plate cure in a low O2environment, (2) a 15 minute hot plate cure in a low O2environment, (3) a 30 minute hot plate cure in a low O2environment, and (4) a 4-5 hour conventional box oven cure. The tensile strength values for each of the four conditions are an average of the values obtained for five different units.

FIG. 5Bshows results, in graphical form, of elongation for materials cured under four different curing conditions: (1) a six minute hot plate cure in a low O2environment, (2) a 15 minute hot plate cure in a low O2environment, (3) a 30 minute hot plate cure in a low O2environment, and (4) a 4-5 hour conventional box oven cure. The elongation percentages for each of the four conditions are an average of the values obtained for five different units.

FIG. 5Cshows, in graphical form, results of a modulus of elasticity for materials cured under four different curing conditions: (1) a six minute hot plate cure in a low O2environment, (2) a 15 minute hot plate cure in a low O2environment, (3) a 30 minute hot plate cure in a low O2environment, and (4) a 4-5 hour conventional box oven cure. The modulus of elasticity for each of the four conditions is an average of the values obtained for five different units.

The information shown graphically inFIGS. 5A-5Cis also reproduced below in tabular form as part of Table 3. The values presented in Table 3 are an average value for lots of 5 units tested after having been cured under the conditions indicated.

Thus, as shown inFIGS. 5A-5Cand in Table 3, mechanical properties are within acceptable operating tolerances and are essentially equivalent for a PBO layer cured using a conventional box oven at 200° C. for 60 minutes and for rapid cures of PBO at 220° C. for 15 minutes.

Additional information regarding weight loss temperature is also presented below in Table 4 for lots 1-4 based on the four different curing conditions of: (1) a six minute hot plate cure in a low O2environment, (2) a 15 minute hot plate cure in a low O2environment, (3) a 30 minute hot plate cure in a low O2environment, and (4) a 4-5 hour conventional box oven cure. As shown below in Table 4, weight loss temperature increases with increasing cure time but substantially plateaus for hot plate cures at 220° C. in the range of 15 minutes.

FIG. 6shows a number of steps for a method100of efficiently forming a polymer, PBO, or insulating layer comprising vias as part of a semiconductor package. Method100comprises a number of steps, including providing semiconductor die,102. Forming a polymer layer over the semiconductor die; step104. Forming a via in the polymer layer; step106. Crosslinking a surface of the polymer layer in a first process; step108. Thermally curing the polymer layer in a second process; step110. The curing of the polymer layer can provide for final film properties, in a short period of time, that allow for a steep via wall profile to be maintained during the rapid temperature increase of the cure.

As a result, a polymer layer can be more simply cured to have desirable film properties, and can be cured at a rate more than 10 times faster than with conventional processes using a box oven or a vertical furnace. The reduction in processing time increases throughput for manufacturing by increasing the number of units that can be made for a given period of time. Use of a hot plate for polymer curing also reduces a number of wafers at risk for misprocessing in a given cure cycle. As indicated above, method100of curing a polymer layer can be applicable to various polymers and insulating layers, including high temperature dielectric materials for advanced packaging or electronics applications.

In the foregoing specification, various embodiments of the disclosure have been described. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the inventions as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense.