SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING

A semiconductor device and method of manufacture are provided. In some embodiments isolation regions are formed by modifying a dielectric material of a dielectric layer such that a first portion of the dielectric layer is more readily removed by an etching process than a second portion of the dielectric layer. The modifying of the dielectric material facilitates subsequent processing steps that allow for the tuning of a profile of the isolation regions to a desired geometry based on the different material properties of the modified dielectric material.

BACKGROUND

DETAILED DESCRIPTION

Embodiments will now be described with respect to particular embodiments which form isolation regions with selectively tuned geometric profiles in a fin field effect transistor (finFET). However, the embodiments described herein may be applied in a wide variety of devices and methods, such as nanostructure transistors, and all such embodiments are fully intended to be included within the scope of the embodiments.

FIG.1illustrates an example of a FinFET100in a three-dimensional view, in accordance with some embodiments. The FinFET100comprises a fin52on a substrate50(e.g., a semiconductor substrate). Isolation regions56are disposed in the substrate50, and the fin52protrudes above and from between neighboring isolation regions56. Although the isolation regions56are described/illustrated as being separate from the substrate50, as used herein the term “substrate” may be used to refer to just the semiconductor substrate or a semiconductor substrate inclusive of isolation regions. Additionally, although the fin52is illustrated as a single, continuous material as the substrate50, the fin52and/or the substrate50may comprise a single material or a plurality of materials. In this context, the fin52refers to the portion extending between the neighboring isolation regions56.

A gate dielectric layer92is along sidewalls and over a first top surface of the fin52, and a gate electrode94is over the gate dielectric layer92. Source/drain regions82are disposed in opposite sides of the fin52with respect to the gate dielectric layer92and gate electrode94.FIG.1further illustrates reference cross-sections that are used in later figures. Cross-section A-A is along a longitudinal axis of the gate electrode94and in a direction, for example, perpendicular to the direction of current flow between the source/drain regions82of the FinFET100. Cross-section B-B is perpendicular to cross-section A-A and is along a longitudinal axis of the fin52and in a direction of, for example, a current flow between the source/drain regions82of the FinFET100. Cross-section C-C is parallel to cross-section A-A and extends through a source/drain region of the FinFET100. Subsequent figures refer to these reference cross-sections for clarity.

Some embodiments discussed herein are discussed in the context of FinFETs formed using a gate-last process. In other embodiments, a gate-first process may be used. Also, some embodiments contemplate aspects used in planar devices, such as planar FETs.

FIGS.2through19Bare cross-sectional views of intermediate stages in the manufacturing of FinFETs100, in accordance with some embodiments.FIGS.2through10illustrate reference cross-section A-A illustrated inFIG.1, except for multiple fins/FinFETs.FIGS.11A,12A,13A,14A,15A,16A,17A,18A, and19Aare illustrated along reference cross-section A-A illustrated inFIG.1, andFIGS.11B,12B,13B,14B,15B,16B,17B,17C,18B, and19B are illustrated along a similar cross-section B-B illustrated inFIG.1, except for multiple fins/FinFETs.FIGS.13C and13Dare illustrated along reference cross-section C-C illustrated inFIG.1, except for multiple fins/FinFETs.

The substrate50has a region SON and a region50P. The region SON can be for forming n-type devices, such as NMOS transistors, e.g., n-type FinFETs. The region50P can be for forming p-type devices, such as PMOS transistors, e.g., p-type FinFETs. The region SON may or may not be physically separated from the region50P (as illustrated by divider51), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) may be disposed between the region SON and the region50P.

InFIG.3, fins52are formed in the substrate50. The fins52are semiconductor strips. In some embodiments, the fins52may be formed in the substrate50by etching trenches in the substrate50. The etching may be any acceptable etch process, such as a reactive ion etch (RIE), neutral beam etch (NBE), the like, or a combination thereof. The etch may be anisotropic.

The fins may be patterned by any suitable method. For example, the fins may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins. In some embodiments, the fins52are formed such that neighboring fins52have a first distance D1, the first distance D1in the range of 10 nm to 80 nm.

InFIG.4, a first precursor film401, such as a first monolayer, is formed on exposed surfaces of the fins52(i.e. vertical sidewalls of the fins52and the first top surface of the fins52) as well as on exposed portions of the substrate50(e.g. a second top surface of the substrate50between neighboring fins52). In some embodiments, the first precursor film401may comprise a first precursor used to form a first dielectric material503and a second dielectric material505(not illustrated inFIG.4but illustrated and discussed further below with respect toFIG.5). In accordance with some embodiments the first precursor film401may be deposited by an atomic layer deposition (ALD) process or a conformal chemical vapor deposition (CVD) process. However, any suitable deposition process may be utilized.

In accordance with some embodiments in which an ALD process is utilized, the first precursor film401is deposited over the fins52and over the substrate50during an initial iteration of a first half-cycle step403of a first deposition process601(seeFIG.6). The first half-cycle step403forms the first precursor film401by introducing through an ALD process one or more precursors comprising a first element of the first dielectric material503and the second dielectric material505.

For example, in an embodiment wherein the first dielectric material503and the second dielectric material505comprise silicon, such as silicon nitride, silicon oxide, silicon carbide, or the like, the first precursor film401may be formed by carrying out one or more precursor-forming steps (e.g. a silicon-forming step forming a film comprising silicon over the fins52and over the substrate50). In some embodiments, the silicon-forming step may be performed using silicon-forming precursors such as SiH4, SiH2Cl2, SiH2I2, the like, or combinations thereof. The silicon-forming step may be performed in a process chamber (not separately illustrated) at a process temperature in the range of 250° C. to 400° C., though other temperatures may be used. In some embodiments, the silicon-forming step precursors may be pulsed into the process chamber at a flow rate in the range of 5 sccm to 100 sccm, for a pulse duration in the range of 0.1 seconds to 0.5 seconds. The silicon-forming step may have a pressure in the range of 10 Torr to 30 Torr. After pulsing the silicon-forming step precursors, a purge may be performed for a duration in the range of 0.1 seconds to 5 seconds. After the silicon-forming step the film (e.g. the first precursor film401) comprises reactive bonding sites of silicon formed on the exposed surfaces of the fins52and on the exposed surfaces of the substrate50.

InFIG.5, the first dielectric material503and the second dielectric material505are formed by performing a second half-cycle step501. The second half-cycle step501introduces one or more precursors comprising a second element of the first dielectric material503and the second dielectric material505by an ALD process to the first precursor film401. During the second half-cycle step501the second element introduced by the one or more precursors may react and bond with the first element at the reactive bonding sites present in the first precursor film401to form the first dielectric material503and the second dielectric material505.

For example, in an embodiment wherein the first dielectric material503and the second dielectric material505comprises nitrogen, such as silicon nitride, and the first half-cycle step403utilized the silicon forming step, a nitrogen-forming step may be performed using nitrogen-forming precursors such as N2, NH3, the like, or combinations thereof during the second half-cycle step501. The second half-cycle step501introduces nitrogen as the second element used in forming the first dielectric material503and the second dielectric material505. The nitrogen-forming step may be performed in a process chamber (not separately illustrated) at a process temperature in the range of 250° C. to 400° C., though other temperatures may be used. The nitrogen-forming step precursors may be pulsed into the process chamber at a flow rate in the range of 10 sccm to 500 sccm, for a pulse duration in the range of 0.1 seconds and 1 second. The nitrogen-forming step may have a pressure in the range of 10 Torr to 30 Torr. After pulsing the nitrogen-forming step precursors, a purge may be performed for a duration in the range of 0.1 seconds to 1 second. The nitrogen produced during the nitrogen-forming step able to bond with the silicon produced during the silicon-forming step.

In an embodiment, the first dielectric material503and the second dielectric material505are formed during the second half-cycle step501by an ALD process performed using an anisotropic plasma. Performing the second half-cycle step501using the anisotropic plasma directionally deposits the precursors utilized in the ALD process of the second half-cycle step501onto the first precursor film401. In this embodiment, the anisotropic plasma utilized during the ALD process of the second half-cycle step501may be generated either remotely (e.g., by a remote plasma) or else may be generated in the deposition chamber itself, and may be generated by a radio-frequency (RF) power for a duration in the range of 0.1 seconds to 5 seconds. The plasma may be generated by the RF power, the RF power in the range of 100 Watts to 800 Watts.

In this embodiment, during the ALD process of the second half-cycle step501using the anisotropic plasma a higher concentration of the precursors are deposited vertically downward onto the first precursor film401such that a greater amount of the precursors utilized during the second half-cycle step501are introduced onto horizontal portions of the first precursor film401than are introduced onto vertical portions of the first precursor film401. In this embodiment a greater quantity of the second element is able to react with the first element on the horizontal portions of the first precursor film401(e.g. the first precursor film401over a top surface of the fins52and the first precursor film401over the substrate50) forming the first dielectric material503than the quantity of the second element able to react with the first element on the vertical portions of the first precursor film401(e.g. the first precursor film401over vertical sidewalls of the fins52) forming the second dielectric material505. As such, the first dielectric material503contains a higher concentration of the second element than the concentration of the second element present in the second dielectric material505.

In this embodiment of the first dielectric material503containing the higher concentration of the second element than the concentration of the second element present in the second dielectric material505, the first dielectric material503has different material properties than the second dielectric material505(e.g. different densities, growth rate, etch rate, etc.). In an embodiment the first dielectric material503has a first density, the first density in a range of 2.8 g/cm3to 2.9 g/cm3, and the second dielectric material505has a second density, the second density in the range of 2.5 g/cm3to 2.7 g/cm3, such that the first density is greater than the second density. Further, the first dielectric material503has a first etch rate using a particular etchant (described further below with respect toFIG.7) in the range of 1 Å/min to 5 Å/min, and the second dielectric material505has a second etch rate in the range of 5 Å/min to 50 Å/min, such that the first etch rate is lower than the second etch rate. However, any suitable densities and etch rates may be utilized.

In an embodiment where the first dielectric material503and the second dielectric material505comprise silicon nitride formed using the silicon-forming step of the first half-cycle step403and the nitrogen-forming step of the second half-cycle step501under the anisotropic plasma ALD process, the first dielectric material503comprises silicon nitride and the second dielectric material505also comprises silicon nitride. However, in this embodiment the concentration of nitrogen present in the first dielectric material503is greater than the concentration of nitrogen present in the second dielectric material505. Hence, the differences in concentration are utilized in order to adjust the material properties of the first dielectric material503relative to the material properties of the second dielectric material505.

However, while the first dielectric material503and the second dielectric material505may be silicon nitride as discussed above, the material used for the first dielectric material503and the second dielectric material505is not intended to be limited to silicon nitride. In other embodiments, the first dielectric material503may be silicon oxide, silicon carbide, combinations of these, or the like. Further, the principles discussed above with respect to the first half-cycle step403and the second half-cycle step501apply to embodiments where the first dielectric material503and the second dielectric material505comprise silicon oxide or silicon carbide, but the first dielectric material503contains a higher concentration of oxygen or carbon than the second dielectric material505, respectively and similarly, therefore the first dielectric material503will have different material properties than the second dielectric material505.

It should be noted that the precursors and parameters discussed with respect to both the silicon-forming step and the nitrogen-forming step utilized in the formation of the first dielectric material503and the second dielectric material505is merely one example of an embodiment, and other embodiments utilizing other precursors and parameters in the formation of the first dielectric material503and the second dielectric material505are fully intended to be included within the scope of this disclosure. The example precursors and parameter values, and other precursors and parameter values may further be used in combination and may be used in other embodiments. Further, the term material properties is intended to include, but is not limited to, physical properties, chemical properties, electrical properties, atomic properties, magnetic properties, mechanical properties, thermal properties, etc.

Optionally, in accordance with some embodiments, after the second half-cycle step501and after the first dielectric material503and the second dielectric material505have been formed, an inert gas treatment step may be utilized to further affect the material properties differentiating the first dielectric material503from the second dielectric material505. In some embodiments an inert gas, such as argon or helium is introduced as a plasma after the second half-cycle step501. The additional introduction of the plasma containing the inert gas after the second half-cycle step501modifies the material properties of the first dielectric material503and the second dielectric material505differentiating the material property differences between the first dielectric material503and the second dielectric material505.

In still other embodiments, the inert gas treatment step may be used to modify the material properties of the first dielectric material503and the second dielectric material505without the use of the anisotropic plasma during the second half-cycle step501. In this embodiment the inert gas treatment step occurs following the second half-cycle step501in which the ALD process does not occur under the anisotropic plasma and the differentiation in material properties between the first dielectric material503and the second dielectric material505is a result of the inert gas treatment step.

InFIG.6, the first half-cycle step403, which deposits the first precursor film401, and the second half-cycle step501(and optionally the inert gas treatment step), which forms the first dielectric material503and the second dielectric material505, may be performed one or more times as part of the first deposition process601. In an embodiment where the first deposition process601comprises multiple iterations of the first half-cycle step403and the second half-cycle step501(and optionally the inert gas treatment step) a first iteration forms the first precursor film401on the fins52and the substrate50and forms the first dielectric material503on the horizontal surfaces and the second dielectric material on the vertical surfaces using the first precursor film401and subsequent iterations forms a new layer of the first precursor film401over the previously formed first dielectric material503and second dielectric material505and a new layer of the first dielectric material503is formed over the previously formed first dielectric material503and a new layer of the second dielectric material505is formed over the previously formed second dielectric material505.

The resulting repetition of the first half-cycle step403and the second half-cycle step501(and optionally the inert gas treatment step) comprises the first deposition process601. The first deposition process601forms a first top dielectric layer603comprising the first dielectric material503, a first bottom dielectric layer605comprising the first dielectric material503, and a first vertical dielectric layer607comprising the second dielectric material505.

For every repetition of the first half-cycle step403and the second half-cycle step501(and optionally the inert gas treatment step) the horizontal area available for the formation of the first dielectric material503of the first bottom dielectric layer605decreases. In particular, during each iteration the horizontal buildup of the second dielectric material505from the previous repetition of the first half-cycle step403and the second half-cycle step501(and optionally the inert gas treatment step) expands further outwards from the fins52and reducing the horizontal surface available to form the first bottom dielectric layer605. As such, this results in the first bottom dielectric layer605having a tapered profile.

In an embodiment, the first half-cycle step403and the second half-cycle step501(and optionally the inert gas treatment step) may be repeated such that the first top dielectric layer603and the first bottom dielectric layer605have a first thickness Th1, the first thickness Th1in the range of 2 nm to 7 nm and the first vertical dielectric layer607has a second thickness Th2, the second thickness Th2in the range of 1 nm to 3 nm.

InFIG.7, the second dielectric material505of the first vertical dielectric layer607is removed by a first etching process701. In accordance with some embodiments the first etching process701utilizes a first etchant that more readily removes the second dielectric material505than the first dielectric material503due to the differences in material properties between the first dielectric material503and the second dielectric material505. In an embodiment, the first etching process701removes the second dielectric material505of the first vertical dielectric layer607while leaving the first dielectric material503substantially intact. In some embodiments, the first etching process701may be a wet etch using an etchant such as dilute HF, a dry etch, a dry/wet etch integration, the like, or a combination thereof. However, any suitable etching process and any suitable etchant may be utilized for the first etching process701.

Further, in accordance with some embodiments, the first top dielectric layer603is also removed either before or after the removal of the second dielectric material505. The first top dielectric layer603may be removed utilizing a protection layer (not separately illustrated) and a planarization process. The protection layer is formed in between the neighboring fins52over the first bottom dielectric layer605(and in some embodiments, over the first top dielectric layer603as well). In some embodiments the protection layer may be formed of a polymer, spin-on carbon, spin-on carbon with at least one O—H group, or the like and may be formed by spin-on coating, flowable chemical vapor deposition, or the like. However, any suitable material and formation process for forming the protection layer may be utilized. In an embodiment where the protection layer covers the first top dielectric layer603a first planarization process may be performed to expose the first top dielectric layer603. The first planarization process may be a chemical-mechanical polish (CMP) process, however, any suitable planarization process may be utilized for the first planarization process. Following the formation of the protection layer the first top dielectric layer603may be removed by a second planarization process, an etch process (since the first top dielectric layer603is now exposed), combinations of these, or the like. The second planarization process may be a CMP process, however, any suitable planarization process may be utilized for the second planarization process. Following the removal of the first top dielectric layer603the protection layer is removed. The protection layer may be removed by any suitable method such as an etching process, an ashing process, etc.

In some embodiments, the first top dielectric layer603is removed before the first vertical dielectric layer607is removed. In some embodiments, the first top dielectric layer603is removed after the first vertical dielectric layer607has been removed.

Following the removal of both the first top dielectric layer603and the first vertical dielectric layer607the first bottom dielectric layer605is present over the second top surface of the substrate50between neighboring fins52. In some embodiments, the remaining first bottom dielectric layer605has a first bottom surface with a first width W1, the first width W1in the range of 10 nm to 80 nm and has a third top surface with a second width W2, the second width W2in the range of 8 nm to 78 nm, such that the first width W1is greater than the second width W2. In an embodiment the first width W1is equal to the first distance D1. In an embodiment where the first bottom dielectric layer605has the tapered profile, the tapered profile may have a first profile angle θ1between the first bottom surface of the first bottom dielectric layer605and the third top surface of the first bottom dielectric layer605, the first profile angle θ1in the range of 35 degrees to 50 degrees.

InFIG.8, a third dielectric material801is formed on exposed surfaces of the fins52(e.g. vertical sidewalls of the fins52and the first top surface of the fins52) as well as over the first bottom dielectric layer605following the removal of the first top dielectric layer603and the first vertical dielectric layer607. In some embodiments, the third dielectric material801may be silicon nitride, silicon oxide, silicon carbide, or the like. In some embodiments, the third dielectric material801has similar density but slightly higher etch rate than the first dielectric material503. In accordance with some embodiments the third dielectric material801may be deposited by an ALD process or a CVD process to a thickness of between in the range of 2 nm to 5 nm. However, any suitable deposition process and any suitable thickness may be utilized.

InFIG.9, a first portion of the third dielectric material801and a second portion of the first dielectric material503of the first bottom dielectric layer605are removed. In accordance with some embodiments, the first portion of the third dielectric material801and the second portion of the first dielectric material503are removed by a second etching process901utilizing a second etchant. The second etching process901may be a dry etch (e.g. a radical dry etch), a wet etch (e.g. a dHF wet etch), a dry/wet etch integration, an isotropic etch, the like, or a combination thereof. However, any suitable etching process and any suitable etchant may be utilized for the second etching process901. Following the second etching process901a third portion903of the third dielectric material801and a fourth portion905of the first dielectric material503remains over the second top surface of the substrate50in between neighboring fins52. In some embodiments, the third portion903of the third dielectric material801and the fourth portion905of the first dielectric material503forms the isolation regions56.

In an embodiment where the third dielectric material801has a similar density but slightly higher etch rate than the first dielectric material503, following the second etching process901the isolation regions56have a flat profile. In some embodiments, the flat profile of the isolation regions56has a third thickness Th3, wherein the third thickness Th3is in the range of 1 nm to 5 nm. However, any suitable thickness may be utilized.

Additionally, the process described with respect toFIGS.2through9is just one example of how the fins52and isolation regions56may be formed. In some embodiments, the fins52may be formed by an epitaxial growth process. For example, a dielectric layer can be formed over a top surface of the substrate50, and trenches can be etched through the dielectric layer to expose the underlying substrate50. Homoepitaxial structures can be epitaxially grown in the trenches, and the dielectric layer can be recessed such that the homoepitaxial structures protrude from the dielectric layer to form the fins52. Additionally, in some embodiments, heteroepitaxial structures can be used for the fins52. For example, the fins52can be recessed, and a material different from the fins52may be epitaxially grown over the recessed fins52. In such embodiments, the fins52comprise the recessed material as well as the epitaxially grown material disposed over the recessed material. In an even further embodiment, a dielectric layer can be formed over a top surface of the substrate50, and trenches can be etched through the dielectric layer. Heteroepitaxial structures can then be epitaxially grown in the trenches using a material different from the substrate50, and the dielectric layer can be recessed such that the heteroepitaxial structures protrude from the dielectric layer to form the fins52. In some embodiments where homoepitaxial or heteroepitaxial structures are epitaxially grown, the epitaxially grown materials may be in situ doped during growth, which may obviate prior and subsequent implantations although in situ and implantation doping may be used together.

Still further, it may be advantageous to epitaxially grow a material in region50N (e.g., an NMOS region) different from the material in region50P (e.g., a PMOS region). In various embodiments, upper portions of the fins52may be formed from silicon germanium (SixGe1-x, where x can be in the range of 0 to 1), silicon carbide, pure or substantially pure germanium, a III-V compound semiconductor, a II-VI compound semiconductor, or the like. For example, the available materials for forming III-V compound semiconductor include, but are not limited to, InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP, and the like.

Further inFIG.9, appropriate wells (not shown) may be formed in the fins52and/or the substrate50. In some embodiments, a P well may be formed in the region50N, and an N well may be formed in the region50P. In some embodiments, a P well or an N well are formed in both the region50N and the region50P.

In the embodiments with different well types, the different implant steps for the region50N and the region50P may be achieved using a photoresist or other masks (not shown). For example, a photoresist may be formed over the fins52and the STI regions56in the region50N. The photoresist is patterned to expose the region50P of the substrate50, such as a PMOS region. The photoresist can be formed by using a spin-on technique and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, an n-type impurity implant is performed in the region50P, and the photoresist may act as a mask to substantially prevent n-type impurities from being implanted into the region50N, such as an NMOS region. The n-type impurities may be phosphorus, arsenic, antimony, or the like implanted in the region to a concentration of equal to or less than 1018cm−3, such as between about 1017cm−3and about 1018cm−3. After the implant, the photoresist is removed, such as by an acceptable ashing process.

Following the implanting of the region50P, a photoresist is formed over the fins52and the STI regions56in the region50P. The photoresist is patterned to expose the region50N of the substrate50, such as the NMOS region. The photoresist can be formed by using a spin-on technique and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, a p-type impurity implant may be performed in the region50N, and the photoresist may act as a mask to substantially prevent p-type impurities from being implanted into the region50P, such as the PMOS region. The p-type impurities may be boron, BF2, indium, or the like implanted in the region to a concentration of equal to or less than 1018cm−3, such as between about 1017cm−3and about 1018cm−3. After the implant, the photoresist may be removed, such as by an acceptable ashing process.

After the implants of the region50N and the region50P, an anneal may be performed to activate the p-type and/or n-type impurities that were implanted. In some embodiments, the grown materials of epitaxial fins may be in situ doped during growth, which may obviate the implantations, although in situ and implantation doping may be used together.

InFIG.10, a dummy dielectric layer60is formed on the fins52. The dummy dielectric layer60may be, for example, silicon oxide, silicon nitride, a combination thereof, or the like, and may be deposited or thermally grown according to acceptable techniques. A dummy gate layer62is formed over the dummy dielectric layer60, and a mask layer64is formed over the dummy gate layer62. The dummy gate layer62may be deposited over the dummy dielectric layer60and then planarized, such as by a CMP. The mask layer64may be deposited over the dummy gate layer62. The dummy gate layer62may be a conductive material and may be selected from a group including amorphous silicon, polycrystalline-silicon (polysilicon), poly-crystalline silicon-germanium (poly-SiGe), metallic nitrides, metallic silicides, metallic oxides, and metals. The dummy gate layer62may be deposited by physical vapor deposition (PVD), CVD, sputter deposition, or other techniques known and used in the art for depositing conductive materials. The dummy gate layer62may be made of other materials that have a high etching selectivity from the etching of isolation regions. The mask layer64may include, for example, SiN, SiON, or the like. In this example, a single dummy gate layer62and a single mask layer64are formed across the region50N and the region50P. It is noted that the dummy dielectric layer60is shown covering only the fins52for illustrative purposes only. In some embodiments, the dummy dielectric layer60may be deposited such that the dummy dielectric layer60covers the STI regions56, extending between the dummy gate layer62and the STI regions56.

FIGS.11A through19Billustrate various additional steps in the manufacturing of embodiment devices.FIGS.11A through19Billustrate features in either of the region50N and the region50P. For example, the structures illustrated inFIGS.11A through19Bmay be applicable to both the region50N and the region50P. Differences (if any) in the structures of the region50N and the region50P are described in the text accompanying each figure.

InFIGS.11A and11B, the mask layer64(seeFIG.10) may be patterned using acceptable photolithography and etching techniques to form masks74. The pattern of the masks74then may be transferred to the dummy gate layer62. In some embodiments (not illustrated), the pattern of the masks74may also be transferred to the dummy dielectric layer60by an acceptable etching technique to form dummy gates72. The dummy gates72cover respective channel regions58of the fins52. The pattern of the masks74may be used to physically separate each of the dummy gates72from adjacent dummy gates. The dummy gates72may also have a lengthwise direction substantially perpendicular to the lengthwise direction of respective epitaxial fins52.

Further inFIGS.11A and11B, gate seal spacers80can be formed on exposed surfaces of the dummy gates72, the masks74, and/or the fins52. A thermal oxidation or a deposition followed by an anisotropic etch may form the gate seal spacers80.

After the formation of the gate seal spacers80, implants for lightly doped source/drain (LDD) regions (not explicitly illustrated) may be performed. In the embodiments with different device types, similar to the implants discussed above inFIG.9, a mask, such as a photoresist, may be formed over the region50N, while exposing the region50P, and appropriate type (e.g., p-type) impurities may be implanted into the exposed fins52in the region50P. The mask may then be removed. Subsequently, a mask, such as a photoresist, may be formed over the region50P while exposing the region50N, and appropriate type impurities (e.g., n-type) may be implanted into the exposed fins52in the region50N. The mask may then be removed. The n-type impurities may be the any of the n-type impurities previously discussed, and the p-type impurities may be the any of the p-type impurities previously discussed. The lightly doped source/drain regions may have a concentration of impurities of from about 1015cm−3to about 1016cm−3. An anneal may be used to activate the implanted impurities.

InFIGS.12A and12B, gate spacers86are formed on the gate seal spacers80along sidewalls of the dummy gates72and the masks74. The gate spacers86may be formed by conformally depositing an insulating material and subsequently anisotropically etching the insulating material. The insulating material of the gate spacers86may be silicon nitride, SiCN, a combination thereof, or the like.

InFIGS.13A and13Bepitaxial source/drain regions82are formed in the fins52to exert stress in the respective channel regions58, thereby improving performance. The epitaxial source/drain regions82are formed in the fins52such that each dummy gate72is disposed between respective neighboring pairs of the epitaxial source/drain regions82. In some embodiments the epitaxial source/drain regions82may extend into, and may also penetrate through, the fins52. In some embodiments, the gate spacers86are used to separate the epitaxial source/drain regions82from the dummy gates72by an appropriate lateral distance so that the epitaxial source/drain regions82do not short out subsequently formed gates of the resulting FinFETs100.

The epitaxial source/drain regions82in the region50N, e.g., the NMOS region, may be formed by masking the region50P, e.g., the PMOS region, and etching source/drain regions of the fins52in the region50N to form recesses in the fins52. Then, the epitaxial source/drain regions82in the region50N are epitaxially grown in the recesses. The epitaxial source/drain regions82may include any acceptable material, such as appropriate for n-type FinFETs. For example, if the fin52is silicon, the epitaxial source/drain regions82in the region50N may include materials exerting a tensile strain in the channel region58, such as silicon, SiC, SiCP, SiP, or the like. The epitaxial source/drain regions82in the region50N may have surfaces raised from respective surfaces of the fins52and may have facets.

The epitaxial source/drain regions82in the region50P, e.g., the PMOS region, may be formed by masking the region50N, e.g., the NMOS region, and etching source/drain regions of the fins52in the region50P are etched to form recesses in the fins52. Then, the epitaxial source/drain regions82in the region50P are epitaxially grown in the recesses. The epitaxial source/drain regions82may include any acceptable material, such as appropriate for p-type FinFETs. For example, if the fin52is silicon, the epitaxial source/drain regions82in the region50P may comprise materials exerting a compressive strain in the channel region58, such as SiGe, SiGeB, Ge, GeSn, or the like. The epitaxial source/drain regions82in the region50P may also have surfaces raised from respective surfaces of the fins52and may have facets.

The epitaxial source/drain regions82and/or the fins52may be implanted with dopants to form source/drain regions, similar to the process previously discussed for forming lightly-doped source/drain regions, followed by an anneal. The source/drain regions may have an impurity concentration of between about 1019cm−3and about 1021cm−3. The n-type and/or p-type impurities for source/drain regions may be any of the impurities previously discussed. In some embodiments, the epitaxial source/drain regions82may be in situ doped during growth.

As a result of the epitaxy processes used to form the epitaxial source/drain regions82in the region50N and the region50P, upper surfaces of the epitaxial source/drain regions have facets which expand laterally outward beyond sidewalls of the fins52. In some embodiments, these facets cause adjacent source/drain regions82of a same FinFET100to merge as illustrated byFIG.13C. In other embodiments, adjacent source/drain regions82remain separated after the epitaxy process is completed as illustrated byFIG.13D.

InFIGS.14A and14B, a first ILD88is deposited over the structure illustrated inFIGS.13A and13B. The first ILD88may be formed of a dielectric material, and may be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. Dielectric materials may include Phospho-Silicate Glass (PSG), Boro-Silicate Glass (BSG), Boron-Doped Phospho-Silicate Glass (BPSG), undoped Silicate Glass (USG), or the like. Other insulation materials formed by any acceptable process may be used. In some embodiments, a contact etch stop layer (CESL)87is disposed between the first ILD88and the epitaxial source/drain regions82, the masks74, and the gate spacers86. The CESL87may comprise a dielectric material, such as, silicon nitride, silicon oxide, silicon oxynitride, or the like, having a different etch rate than the material of the overlying first ILD88.

InFIGS.15A and15B, a planarization process, such as a CMP, may be performed to level the top surface of the first ILD88with the top surfaces of the dummy gates72or the masks74. The planarization process may also remove the masks74on the dummy gates72, and portions of the gate seal spacers80and the gate spacers86along sidewalls of the masks74. After the planarization process, top surfaces of the dummy gates72, the gate seal spacers80, the gate spacers86, and the first ILD88are level. Accordingly, the top surfaces of the dummy gates72are exposed through the first ILD88. In some embodiments, the masks74may remain, in which case the planarization process levels the top surface of the first ILD88with the top surfaces of the top surface of the masks74.

InFIGS.16A and16B, the dummy gates72, and the masks74if present, are removed in an etching step(s), so that recesses90are formed. Portions of the dummy dielectric layer60in the recesses90may also be removed. In some embodiments, only the dummy gates72are removed and the dummy dielectric layer60remains and is exposed by the recesses90. In some embodiments, the dummy dielectric layer60is removed from recesses90in a first region of a die (e.g., a core logic region) and remains in recesses90in a second region of the die (e.g., an input/output region). In some embodiments, the dummy gates72are removed by an anisotropic dry etch process. For example, the etching process may include a dry etch process using reaction gas(es) that selectively etch the dummy gates72without etching the first ILD88or the gate spacers86. Each recess90exposes a channel region58of a respective fin52. Each channel region58is disposed between neighboring pairs of the epitaxial source/drain regions82. During the removal, the dummy dielectric layer60may be used as an etch stop layer when the dummy gates72are etched. The dummy dielectric layer60may then be optionally removed after the removal of the dummy gates72.

InFIGS.17A and17B, gate dielectric layers92and gate electrodes94are formed for replacement gates.FIG.17Cillustrates a detailed view of region89ofFIG.17B. Gate dielectric layers92are deposited conformally in the recesses90, such as on the top surfaces and the sidewalls of the fins52and on sidewalls of the gate seal spacers80/gate spacers86. The gate dielectric layers92may also be formed on top surface of the first ILD88. In accordance with some embodiments, the gate dielectric layers92comprise silicon oxide, silicon nitride, or multilayers thereof. In some embodiments, the gate dielectric layers92include a high-k dielectric material, and in these embodiments, the gate dielectric layers92may have a k value greater than about 7.0, and may include a metal oxide or a silicate of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, and combinations thereof. The formation methods of the gate dielectric layers92may include Molecular-Beam Deposition (MBD), ALD, PECVD, and the like. In embodiments where portions of the dummy dielectric layer60remains in the recesses90, the gate dielectric layers92include a material of the dummy dielectric layer60(e.g., SiO2).

The gate electrodes94are deposited over the gate dielectric layers92, respectively, and fill the remaining portions of the recesses90. The gate electrodes94may include a metal-containing material such as TiN, TiO, TaN, TaC, Co, Ru, Al, W, combinations thereof, or multi-layers thereof. For example, although a single layer gate electrode94is illustrated inFIG.17B, the gate electrode94may comprise any number of liner layers94A, any number of work function tuning layers94B, and a fill material94C as illustrated byFIG.17C. After the filling of the gate electrodes94, a planarization process, such as a CMP, may be performed to remove the excess portions of the gate dielectric layers92and the material of the gate electrodes94, which excess portions are over the top surface of the first ILD88. The remaining portions of material of the gate electrodes94and the gate dielectric layers92thus form replacement gates of the resulting FinFETs100. The gate electrodes94and the gate dielectric layers92may be collectively referred to as a “gate stack.” The gate and the gate stacks may extend along sidewalls of a channel region58of the fins52.

The formation of the gate dielectric layers92in the region50N and the region50P may occur simultaneously such that the gate dielectric layers92in each region are formed from the same materials, and the formation of the gate electrodes94may occur simultaneously such that the gate electrodes94in each region are formed from the same materials. In some embodiments, the gate dielectric layers92in each region may be formed by distinct processes, such that the gate dielectric layers92may be different materials, and/or the gate electrodes94in each region may be formed by distinct processes, such that the gate electrodes94may be different materials. Various masking steps may be used to mask and expose appropriate regions when using distinct processes.

InFIGS.18A and18B, a second ILD108is deposited over the first ILD88. In some embodiment, the second ILD108is a flowable film formed by a flowable CVD method. In some embodiments, the second ILD108is formed of a dielectric material such as PSG, BSG, BPSG, USG, or the like, and may be deposited by any suitable method, such as CVD and PECVD. In accordance with some embodiments, before the formation of the second ILD108, the gate stack (including a gate dielectric layer92and a corresponding overlying gate electrode94) is recessed, so that a recess is formed directly over the gate stack and between opposing portions of gate spacers86, as illustrated inFIGS.18A and18B. A gate mask96comprising one or more layers of dielectric material, such as silicon nitride, silicon oxynitride, or the like, is filled in the recess, followed by a planarization process to remove excess portions of the dielectric material extending over the first ILD88. The subsequently formed gate contacts110(FIGS.19A and19B) penetrate through the gate mask96to contact the top surface of the recessed gate electrode94.

InFIGS.19A and19B, gate contacts110and source/drain contacts112are formed through the second ILD108and the first ILD88in accordance with some embodiments. Openings for the source/drain contacts112are formed through the first and first ILDs88and second ILDs108, and openings for the gate contact110are formed through the second ILD108and the gate mask96. The openings may be formed using acceptable photolithography and etching techniques. A liner, such as a diffusion barrier layer, an adhesion layer, or the like, and a conductive material are formed in the openings. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as a CMP, may be performed to remove excess material from a surface of the second ILD108. The remaining liner and conductive material form the source/drain contacts112and gate contacts110in the openings. An anneal process may be performed to form a silicide at the interface between the epitaxial source/drain regions82and the source/drain contacts112. The source/drain contacts112are physically and electrically coupled to the epitaxial source/drain regions82, and the gate contacts110are physically and electrically coupled to the gate electrodes106. The source/drain contacts112and gate contacts110may be formed in different processes, or may be formed in the same process. Although shown as being formed in the same cross-sections, it should be appreciated that each of the source/drain contacts112and gate contacts110may be formed in different cross-sections, which may avoid shorting of the contacts.

Advantages of the present embodiments include the ability to form isolation regions56with finely tuned geometric profiles by utilizing the differences in material properties (e.g. density, etch rate, etc.) between dielectric materials (e.g. the first dielectric material503, the second dielectric material505, and the third dielectric material801) deposited using such processes such as an ALD process or CVD process to better control the etching processes (e.g. the first etching process701and the second etching process901) used to form the isolation regions56in situations with requiring the formation of isolation regions in high aspect ratio regions such as between the fins52with small openings such as the first distance D1between the fins52.

FIGS.20A and20Billustrate another embodiment in which the third portion903of the third dielectric material801and the fourth portion905of the first dielectric material503form the isolation regions56in a similar manner as discussed above except the third dielectric material801has different material properties than the first dielectric material503. The selection of the third dielectric material801and the first dielectric material503based on differences in material properties between the third dielectric material801and the first dielectric material503allows for the tuning of a profile geometry of the isolation regions56.

In some embodiments, the third dielectric material801may be a dielectric material such as silicon nitride, for example, while the first dielectric material503may also be silicon nitride, for example, but having a different concentration of nitrogen than the third dielectric material801resulting in the differences in material properties between the third dielectric material801and the first dielectric material503allowing for the tuning of the profile geometry of the isolation regions56. In some embodiments, the third dielectric material801may be a dielectric material such as silicon oxide, for example, while the first dielectric material is silicon nitride, for example, the different compounds having different material properties allowing for the tuning of the profile geometry of the isolation regions56.

InFIG.20A, the isolation regions56are depicted as having a concave profile. In an embodiment where the third dielectric material801has a higher density than the density of the first dielectric material503and the third dielectric material801has a lower etch rate than the first dielectric material503the second etching process901removes the first dielectric material503more readily than the third dielectric material801resulting in the third portion903of the third dielectric material801and the fourth portion905of the first dielectric material503forming the isolation regions56having a concave profile. In this embodiment, the third dielectric material801may have a density in the range of 2.7 g/cm3to 3.0 g/cm3and may have an etch rate in the range of 1 Å/min to 5 Å/min. In this embodiment, the isolation regions56may have a second profile angle θ2between a fourth top surface of the third portion903of the third dielectric material801and a fifth top surface of the fourth portion905of the first dielectric material503. The second profile angle θ2in the range of 130 degrees to 145 degrees.

InFIG.20B, a cross-section of the resulting FinFETs100formed as discussed with respect toFIG.19Ais depicted with the exception of the isolation regions56having the concave profile as discussed with respect toFIG.20A. As such, the profile geometry of the isolation regions56is directly related to the material properties of the first dielectric material503, the third dielectric material801, and the parameters of the second etching process901.

InFIGS.21A and21Bcross-sectional views of various stages of forming the FinFET100are depicted in an embodiment in which the isolation regions56have a convex profile.FIG.21Adepicts the formation of the isolation regions56as formed in a similar manner as discussed above with respect toFIGS.2through9with the exception that in this embodiment the formation of the third dielectric material801and subsequent second etching process901may be omitted. In this embodiment, the isolation regions56have the convex profile as produced from the repetition of the first half-cycle step403and the second half-cycle step501(and optionally the inert gas treatment step). In this embodiment, the convex profile may have the first profile angle θ1. In this embodiment, the convex profile may have the first thickness Th1, the first bottom surface with the first width W1, and the third top surface with the second width W2, where the first width W1is equal to the first distance D1.FIG.21Bdepicts a cross-section of the resulting FinFETs100formed as discussed with respect toFIG.19Awith the exception of the isolation regions56having the convex profile as discussed with respect toFIG.21A.

The disclosed FinFET embodiments could also be applied to gate-all-around (GAA) device as such as nanostructure (e.g., nanosheet, nanowire, or the like) field effect transistors (NSFETs). In an NSFET embodiment, the fins are replaced by nanostructures formed by patterning a stack of alternating layers of channel layers and sacrificial layers. Dummy gate stacks and source/drain regions are formed in a manner similar to the above-described embodiments. After the dummy gate stacks are removed, the sacrificial layers can be partially or fully removed in channel regions. The replacement gate structures are formed in a manner similar to the above-described embodiments, the replacement gate structures may partially or completely fill openings left by removing the sacrificial layers, and the replacement gate structures may partially or completely surround the channel layers in the channel regions of the NSFET devices. ILDs and contacts to the replacement gate structures and the source/drain regions may be formed in a manner similar to the above-described embodiments. A nanostructure device can be formed as disclosed in U.S. Pat. No. 9,647,071, which is incorporated herein by reference in its entirety.

The embodiments discussed herein provide advantages by utilizing the different material properties of various dielectric materials to shape the isolation regions56to have a desired profile geometry. By forming the first precursor film401into the first dielectric material503and the second dielectric material505, the first dielectric material503having different material properties than the second dielectric material505, the first etching process701may remove the second dielectric material505while leaving a substantial portion of the first dielectric material503intact. The remaining first dielectric material503forming the basis for the isolation regions56, the isolation regions56having the convex profile. The convex profile of the isolation regions56can further be modified to have the flat profile or concave profile as desired by adding and etching the third dielectric material801, the material properties of the third dielectric material801being directly related to the geometric profile of the isolation regions56following the second etching process901.

In accordance with some embodiments of the present disclosure a method of forming a semiconductor device includes: forming a fin over a semiconductor substrate; forming a precursor film over the fin and the semiconductor substrate; treating the precursor film, wherein the treating the precursor film forms a first dielectric material from a first portion of the precursor film and forms a second dielectric material from a second portion of the precursor film, wherein the first dielectric material has a first density and the second dielectric material has a second density, the first density being different from the second density; and removing the second dielectric material, wherein after the removing the second dielectric material an isolation structure is formed comprising the first dielectric material over the semiconductor substrate and adjacent to the fin. In an embodiment after the removing the second dielectric material the isolation structure has a convex profile. In an embodiment the convex profile has a first profile angle, the first profile angle in a range of 35 degrees to 50 degrees. In an embodiment further including: forming a third dielectric material over the fin, the semiconductor substrate, and the first dielectric material after the removing the second dielectric material; and performing an etching process on the first dielectric material and the third dielectric material. In an embodiment following the etching process the isolation structure has a flat profile. In an embodiment following the etching process the isolation structure has a concave profile. In an embodiment following the etching process the concave profile has a second profile angle, the second profile angle in a range of 130 degrees to 145 degrees.

In accordance with some embodiments of the present disclosure a semiconductor device includes: a first fin over a semiconductor substrate; and a first dielectric material over the semiconductor substrate adjacent to the first fin, the first dielectric material having a convex profile with a tapered angle, the tapered angle in a range of 35 degrees to 50 degrees, the first dielectric material having a width that gets smaller as the first dielectric material extends away from the semiconductor substrate. In an embodiment the first dielectric material includes silicon nitride, silicon oxide, or silicon carbide. In an embodiment the first dielectric material has a thickness, the thickness in a range of 1 nm to 5 nm. In an embodiment the first dielectric material has a density, the density in the range of 2.8 g/cm3to 2.9 g/cm3. In an embodiment the tapered angle is located at an intersection between the first fin and the semiconductor substrate. In an embodiment further including a second fin over the semiconductor substrate, the second fin being a distance away from the first fin and the first dielectric material having a bottom width, the bottom width equal to the distance. In an embodiment further including a second dielectric material over the tapered angle of the first dielectric material, the second dielectric material having different material properties than the first dielectric material.

In accordance with some embodiments of the present disclosure a method of forming a semiconductor device includes: forming a first semiconductor fin over a substrate; depositing a layer of silicon over the first semiconductor fin and over the substrate adjacent to the first semiconductor fin; applying an anisotropic plasma to the layer of silicon with an element, wherein the applying the anisotropic plasma forms a first dielectric material from horizontal portions of the layer of silicon and forms a second dielectric material from vertical portions of the layer of silicon, the first dielectric material having a first concentration of the element and the second dielectric material having a second concentration of the element, the first concentration being different from than the second concentration; and performing an etching process to remove the second dielectric material. In an embodiment further including removing the first dielectric material formed on a first top surface of the first semiconductor fin. In an embodiment further including forming a second semiconductor fin over the substrate adjacent to the first semiconductor fin, wherein the second semiconductor fin is a distance away from the first semiconductor fin, the distance being equal to a first width of a bottom surface of the second dielectric material. In an embodiment the first dielectric material has a second top surface with a second width, the first width being greater than the second width. In an embodiment the second dielectric material comprises silicon nitride and has a first density, the first density in the range of 2.5 g/cm3to 2.7 g/cm3. In an embodiment the first dielectric material comprises silicon nitride and has a second density, the second density in the range of 2.8 g/cm3to 2.9 g/cm3.