Method and apparatus for controlling a voltage controlled oscillator tuning range in a frequency synthesizer

A frequency synthesizer (100, 500) provides multiple selectable voltage controlled oscillator (VCO) frequency ranges. A VCO control circuit (114) controls the selectable VCO frequency ranges based on lock conditions of selected VCOs within a VCO array (112) or a single variable VCO circuit (502), to provide an extended tuning range to the frequency synthesizer (100, 500).

TECHNICAL FIELD 
This invention relates in general to frequency synthesizers and more 
specifically to voltage controlled oscillator circuits used in frequency 
synthesizers. 
BACKGROUND 
Recent radio technology trends have focused on producing highly integrated 
products that operate at lower voltages. The advantages associated with 
these trends include smaller packaging and lower current drain 
consumption. However, the use of low voltage high density integrated 
circuit technologies presents problems to the electrical designer 
including low breakdown thresholds and limited available supply range for 
the circuit design. Present day radio frequency (RF) synthesizer circuits 
requiring a wide tuning range are typically achieved using one to two 
manually selected VCO circuits, each employing a very high tuning voltage, 
typically around 12-15 volts. Careful characterization and/or trim 
operations of these VCOs are required in order to cover a fixed frequency 
range. The required tuning operations and characterizations currently 
performed are expensive and are not readily applicable in a monolithic 
environment. 
Achieving a wide tuning loop bandwidth in an all-integrated synthesizer 
presents the issue of controlling an integrated VCO over a wide tuning 
range. With the advent of lower operating supply voltages and lower 
breakdown voltages in integrated circuit (IC) technologies, there is a 
need for an improved VCO circuit to adapt to this new environment.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
FIG. 1 of the accompanying drawings shows a block diagram of a frequency 
synthesizer 100 in accordance with a first embodiment of the present 
invention. A reference frequency signal, f.sub.ref, generated from a 
reference oscillator 102 is received at phase detector 104. Phase detector 
104 phase compares the reference frequency signal, fref, to a divided 
output frequency, f.sub.v, received from a loop divider 106. Phase 
detector 104 generates an error signal 108 which is transferred to loop 
filter 110. The loop filter 110 generates a control voltage signal, Vctrl, 
in response to the error signal 108. In accordance with the present 
invention, the control voltage signal, Vctrl, is used as an input to a 
plurality of voltage controlled oscillator (VCO) circuits 112 (VCO.sub.1 
-VCO.sub.n). In accordance with the present invention, a VCO control 
circuit 114 alternately enables each of the plurality of VCO circuits 112 
through select ports (sel.sub.1 -sel.sub.n) in order to alternately 
generate output frequencies with which the synthesizer 100 can attempt to 
lack on frequency. Thus, VCO control circuit 114 provides for the 
automatic selection of a VCO frequency from amongst a plurality of 
selectable VCO frequency ranges. The plurality of VCO circuits 112 will 
also be referred as a VCO array 112. The VCOs within VCO array 112 
preferably have overlapping frequency ranges to provide a wideband tuning 
range for synthesizer 100. 
The VCO control circuit 114 begins an iteration of alternately enabling and 
disabling individual VCOs within VCO array 112 in response to a trigger 
signal 115 generated from a trigger source (not shown), such as a 
controller. The output frequency generated from a currently enabled VCO is 
fed through buffer 116 as output frequency, f.sub.out, and then fed back 
to loop divider 106. Loop divider 106 receives inputs from a controller 
(not shown) which programs the loop divider to divide the output 
frequency, f.sub.out, by a predetermined amount (/n). The divided output 
frequency, f.sub.v, is then fed back to phase detector 104. By 
individually enabling the VCOs one at a time as described by the 
invention, the tuning range provided to synthesizer 100 extends across the 
overlapping frequency ranges of the plurality of VCOs 112. 
The synthesizer 100 also includes a means of detecting locked and unlocked 
synthesizer conditions, preferably through a lock detect circuit 118 which 
uses the control voltage signal, V.sub.ctrl, to determine whether the 
synthesizer 100 has locked on frequency with a currently enabled VCO 
circuit. Lock detect circuit 118 generates a lock indicator signal 120 
indicating either a locked or unlocked condition and feeds the lock 
indicator signal to the VCO control circuit 114. VCO control circuit 114 
continues to alternately enable and disable each of the plurality of VCO 
circuits 112 until the lock indicator signal 120 indicates that the 
synthesizer has locked on frequency with one of the VCOs. Once the 
synthesizer 100 has locked on frequency, the currently selected VCO, loop 
divider 106, phase detector 104, and loop filter 110 generally form a 
locked phase lock loop (PLL). The phase lock loop maintains divided 
frequency output signal, f.sub.v, in phase with the frequency signal, 
f.sub.ref, by producing the error signal 108 at the phase detector output 
which manipulates the currently selected VCO to correct for differences 
between f.sub.v and f.sub.ref. 
In accordance with the present invention, VCO control circuit 114 can also 
track the number of the currently enabled VCO relative to the total number 
of VCOs within VCO array 112. Once each of the VCOs within VCO array 112 
has been alternately enabled without a successful lock, an out of range 
indicator, range.sub.x, enables an out of range condition that terminates 
the alternate enabling and disabling process. The out of range indicator 
is also preferably coupled back to a controller (not shown) to inform the 
controller that no successful lock was achieved with any of the selected 
VCO circuits within VCO array 112. Hence, the VCO control circuit 114 as 
described by the invention can continue to make attempts to lock the 
synthesizer 100 on frequency until either a lock condition is met or an 
out of range condition is indicated. When the VCOs within VCO array 112 
provide different yet overlapping tuning ranges, the synthesizer 100 can 
provide a wideband voltage controlled oscillator tuning range. The 
iterative process can be restarted with a new trigger signal 115 which 
resets the VCO control circuit 114. 
The frequency synthesizer 100 is preferably fabricated using 
bipolar-complimentary metal oxide semiconductor (Bi-CMOS) technology as 
part of a single integrated circuit (IC). Other IC technologies, such as 
gallium arsenide (GaAs) or bipolar, also lend themselves well to providing 
the wide tuning range achieved by providing multiple selectable integrated 
VCO circuits. Using the array of VCO circuits described by the invention, 
eliminates the need for a single VCO with a large tuning voltage range, a 
practice common in synthesizers with a wide frequency range in present 
art. Hence, the integrated circuit design makes synthesizer 100 attractive 
for low voltage applications, particularly those using operating voltages 
below 3 volts. By using the VCO control circuit 114 described by the 
invention to automatically select and de-select VCO frequency ranges 
within synthesizer 100, the need for VCO characterization and trimming is 
minimized. The VCO control circuit 114 and lock detect circuit 118 may be 
implemented in a number of ways with the preferred embodiments to be 
described herein. While the first embodiment describes a series of VCOs 
having partially overlapping tuning ranges, one skilled in the art 
realizes that there may be applications where it is desirable to have gaps 
between some of the tuning ranges. 
Referring now to FIG. 2, there is shown a preferred implementation of the 
VCO control circuit in accordance with the present invention. Common 
signal names have been maintained between FIGS. 1 and 2 where applicable. 
The VCO control circuit 200 preferably includes a counter 202, a binary 
decoder 204, a timer 206, first, second, and third flip-flops 208, 210, 
212, shown as D flip-flops, an OR gate 214, and an inverter 216. In 
operation, the number of the selected (active) VCO is stored in the 
contents of the counter 202 and provided as a binary output to the binary 
decoder 204. The binary decoder 204 receives the binary input and 
transmits a single bit output to pins sel.sub.1 -sel.sub.n. The selection 
process is initiated by input signal trigger 115, preferably generated by 
a controller (not shown), which resets all counters and flip-flops in the 
design. At initiation, the value stored in counter 202 is 0, resulting in 
a logic high setting for output sel.sub.1. At the time of initiation, 
timer 206 begins counting clock cycles of the frequency reference signal, 
f.sub.ref. The combination of the length of the clock cycle time and the 
period of the frequency reference signal are used to produce a time delay 
greater than the settling time of the synthesizer. When timer 206 
completes its cycle, an overflow output is set to a logic high, clocking a 
first flip-flop 208. When clocked, first flip-flop 208 stores the lock 
indicator signal, lock.sub.x, from the lock detector of FIG. 1 which is 
first inverted through inverter 216. If the phase lock loop locks with the 
currently selected VCO frequency (lock.sub.x set to a logic level low), 
the first flip-flop lock output signal is set to a logic level high, and 
the clock input, clk, of the timer 206 is disabled through logic gate 214, 
and the value at the select outputs, sel.sub.1 -sel.sub.n, is latched and 
held. If the phase lock loop fails to lock with the currently selected VCO 
frequency (lock.sub.x is set to a logic level high), the overflow output 
of timer 206 enables first and second delay producing flip-flops 210 and 
212 which in turn cause counter 202 to increment its binary output count. 
The incremented count of counter 202 allows the binary decoder 204 to 
increment to the next select output, in this case sel.sub.2. This process 
is repeated until a lock condition is reached or until counter 202 
overflows. An overflow condition at counter 202 exists when its overflow 
output, range.sub.x, is a logic level high which terminates the search 
process through logic gate 214. The range.sub.x signal is also preferably 
fed back to a controller (not shown) to indicate that an out of range 
condition exists. 
FIG. 3 shows an electrical circuit diagram of the preferred embodiment of 
the lock detect circuit in accordance with the present invention. Common 
signal names have been maintained between FIGS. 1 and 3 where applicable. 
The lock detect circuitry 300 preferably comprises first and second 
comparators 302, 304, a first voltage divider 306 coupled to the 
non-inverting input of the first comparator 302, and a second voltage 
divider 308 coupled to the inverting input of the second comparator 304. A 
logic gate, NAND gate 310, is preferably coupled to the outputs of the 
first and second comparators 302, 304 to provide the lock detect signal, 
lock.sub.x. The analog lock detect circuitry 300 samples the control 
voltage, Vctrl, generated at the output of the loop filter 110 of FIG. 1 
and compares it to preset threshold limits of first and second comparators 
302 and 304. The phase lock loop of FIG. 1 will cause the control voltage, 
Vctrl, to approach either supply or ground, when the PLL is unlocked. This 
feature reduces the variations in loop dynamics over frequency and 
temperature. First voltage divider 306 determines the upper limit 
threshold of first comparator 302 while second voltage divider 308 
determines the lower limit threshold of second comparator 304. Comparator 
302 generates a logic level high (supply) signal when the control voltage, 
Vctrl, is lower than the upper limit threshold. When the control voltage 
is higher than the upper limit threshold, the first comparator 302 
generates a logic level low (ground). Second comparator 304 generates a 
logic level high when the control voltage, Vctrl, is higher than the lower 
limit threshold and a logic level low signal otherwise. The NAND gate 310 
generates a logic level low only when both inputs are high, when the 
control voltage, Vctrl, is between the upper and lower limit thresholds. 
This is an indication that the synthesizer 100 is locked on frequency. 
When the NAND gate 310 output is a logic level high the synthesizer 100 is 
unlocked. 
While the lock detector 300 has been described using an analog approach, an 
alternate digital implementation can also be realized by sampling the 
edges of the error signal 108 at the output of the phase detector 104. 
This digital sampling technique is described in a U.S. Pat. No. 4,764,787 
by Kaatz entitled "Frequency Synthesizer Having Phase Detector with 
Optimal Steering and Level-Type Lock Indication" and is hereby 
incorporated by reference. In this implementation, the VCO frequency 
ranges are preferably increasing monotonically, and by sampling the edges 
of the error signal 108, positive and negative out of lock conditions can 
be determined. This allows the control circuit 114 to do a non-sequential 
search through the VCO array 112, skipping several VCO circuits at a time, 
when an unlocked condition occurs. Thus, it is not necessary for each VCO 
circuit to be enabled in order to determine out of range conditions. 
Various other lock detect schemes available in the art can also be 
employed to determine lock and unlocked conditions of the frequency 
synthesizer. 
It may also be desirable for a controller (not shown) to store information 
as to which VCO actually locks on frequency. Thus, when control circuit 
114 is re-triggered it can respond by starting a non-sequential search 
with the last enabled VCO that locked on frequency. By restarting the 
search with the last enabled VCO, lock times can potentially be reduced. 
Referring now to FIG. 4, there is shown a flowchart of an iterative process 
400 for controlling a VCO tuning range in a frequency synthesizer in 
accordance with the present invention. Step 402 starts the iterative 
process 400 by resetting all the VCO control circuits, step 404 sets a 
counter to a predetermined value, in this case a value of zero (i=0), and 
step 406 increments the counter by a predetermined value, in this case by 
an increment of 1. Step 408 enables VCO.sub.i and then delays the clock 
for a predetermined amount of time, for example 100 microseconds at step 
410. Step 412 determines if a lock condition is detected and if so, 
terminates the iterative process at step 414. If a lock condition is not 
detected at step 412, an out of range condition is then checked at step 
416. Step 416 determines if an out of range condition is present by 
comparing the counter to a predetermined threshold. If an out of range 
condition is met, the currently enabled VCO is disabled at step 418 and 
the iterative process is stopped at step 420. If an out of range condition 
is not determined in step 416, the currently enabled VCO is disabled at 
step 422, and the iterative process is returned to step 406 where the 
counter is incremented to enable a new VCO at step 408. When the tuning 
ranges from one VCO to the next partially overlap, the result of the 
iterative process is a broadband VCO tuning range within which the 
frequency synthesizer can lock. 
As previously described, it may also be desirable to sequence through the 
VCOs in a non-sequential manner, even skipping several VCOs at a time. The 
iterative process 400 can be adapted to respond to positive and negative 
unlocked conditions in order to provide the non-sequential search through 
the VCOs. Thus, the iterative process can be adapted to suit specific 
application needs. 
While the preferred embodiment of the invention has been illustrated and 
described, it will be clear that the invention is not so limited. While 
the preferred embodiment of synthesizer circuit 100 shows separate VCO 
circuits coupled in a parallel like fashion off the VCO control circuit 
114, an alternative approach could include a single VCO with multiple pin 
switches or switched varactor tuning ranges to provide a plurality of 
selectable VCO tuning frequencies. This alternative embodiment of the 
frequency synthesizer is shown in FIG. 5 of the accompanying drawings. 
Like reference designators have been used between FIGS. 1 and 5 where 
applicable. In accordance with this alternative embodiment, frequency 
synthesizer 500 includes VCO control circuit 114 and lock detect circuit 
118 to control a phase lock loop formed of phase detector 104, loop filter 
110, loop divider 106, and a variable voltage controlled oscillator (VCO) 
502 preferably having an N-bit band selection. Variable VCO 502 is shown 
in more detail in the electronic circuit diagram of FIG. 6. Once again, in 
accordance with the present invention, the VCO control circuit 114 
provides for the automatic selection of a VCO frequency from amongst a 
plurality of selectable VCO frequency ranges within synthesizer 500. By 
determining unlocked conditions and using these conditions to control a 
plurality of selectable VCO frequency ranges, a broad overall tuning range 
is provided to synthesizer 500. 
Referring now to FIG. 6, variable VCO 502 generally includes capacitors 
612, varactor 608, resonator 610, transistor 614, and current sink 616. 
Other biasing circuitry has been omitted for simplicity. In accordance 
with this alternative embodiment of the invention, variable VCO 502 
further includes switches 604, preferably field effect transistors (FETs), 
which are enabled through select lines sel.sub.1 -sel.sub.n from the VCO 
control circuit 114. FETs 604 selectively engage capacitors (C through 
C.sub.x 2.sup.n) 606 either singularly or in combinations thereof to 
provide various selectable tuning ranges to synthesizer 500. The VCO 
control circuit 114 of FIG. 1 can be implemented to provide the N-bit 
binary outputs to select ports (sel.sub.1 -sel.sub.n) as opposed to the 
single bit binary output described in the embodiment of FIG. 2. Hence, the 
single variable VCO 502 provides fine tuning over a broad range of 
selectable tuning frequencies with which to lock synthesizer 500. 
In FIG. 7, a communication device such as a two way radio 700 is shown. 
Radio 700 includes conventional transmitter, receiver, and controller 
circuits for transmitting and receiving information. Preferably, radio 700 
includes a frequency synthesizer having a selectable VCO tuning range as 
described by the invention. Thus, radio 700 provides the benefit of a 
broad range of tuning frequencies with which to obtain communication 
links. Other communication devices such as televisions and cellular 
telephones can also benefit from the improvements provided by the 
frequency synthesizer having selectable tuning ranges described by the 
present invention. 
Accordingly, wideband frequency synthesizers can now be achieved by 
implementing and controlling multiple VCOs or a single variable VCO as 
described by the invention. By using a VCO array or a single variable VCO 
and determining out of lock conditions, the need for individual VCO 
characterization and trim operations is significantly reduced. The 
iterative process of controlling a VCO tuning range, as described by the 
invention, allows a single integrated synthesizer to cover a broader range 
of communication applications and hence has a greater appeal in the market 
place than present day synthesizers. 
Numerous other modifications, changes, variations, substitutions, and 
equivalents will occur to those skilled in the art without departing from 
the spirit and scope of the present invention as defined by the appended 
claims.