POWER AMPLIFIER

A power amplifier includes a power transistor configured to amplify an input radio-frequency (RF) signal, and a bias circuit configured to provide a bias current to the power transistor, and in a first power mode, detect a first signal corresponding to a first level or more in the input RF signal and generate the bias current corresponding to the first signal, or detect a second signal corresponding to a second level or less in the input RF signal and generate the bias current corresponding to the second signal, and in a second power mode, detect a third signal corresponding to a third level or more in the input RF signal and generate the bias current corresponding to the third signal, or detect a fourth signal corresponding to a fourth level or less in the input RF signal and generate the bias current corresponding to the fourth signal.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit under 35 USC 119(a) of Korean Patent Application Nos. 10-2022-0128073 filed on Oct. 6, 2022, and 10-2023-0053468 filed on Apr. 24, 2023, in the Korean Intellectual Property Office, the entire disclosures of which are incorporated herein by reference for all purposes.

BACKGROUND

The following description relates to a power amplifier.

2. Description of Related Art

Wireless communication systems apply various digital modulation and demodulation schemes according to the evolution of communication standards. The existing code-division multiple access (CDMA) communication system adopts the quadrature phase-shift keying (QPSK) method, and the existing wireless LAN following the IEEE communication standard adopts the orthogonal frequency-division multiplexing (OFDM) method. In addition, the long-term evolution (LTE) and LTE (Advance (LTE+ or LTE-A) standards, which are recent 3GPP standards, adopt QPSK, quadrature amplitude modulation (QAM), and OFDM schemes. These wireless communication standards implement a linear modulation scheme that necessitates that the intensity or phase of a transmission signal is maintained during transmission.

A power amplifier amplifies the input radio-frequency (RF) signal and transmits it to an antenna. The power amplifier may include a power transistor and a bias circuit providing a bias current to the power transistor. The performance of the power amplifier may be influenced by the direct current sourcing capability (DSC) of the bias circuit. When the DSC is low, a base voltage droop and a gain compression of the power transistor may occur. In addition, when the DSC is high, a gain expansion of the power transistor may occur. That is, the linearity of the power amplifier may deteriorate due to the gain compression or the gain expansion.

SUMMARY

In one general aspect, a power amplifier includes a power transistor configured to amplify an input radio-frequency (RF) signal; and a bias circuit configured to provide a bias current to the power transistor, wherein the bias circuit is configured to, in a first power mode, detect a first signal corresponding to a first level or more in the input RF signal and generate the bias current as a bias current corresponding to the first signal, or detect a second signal corresponding to a second level or less in the input RF signal and generate the bias current as a bias current corresponding to the second signal, and in a second power mode, detect a third signal corresponding to a third level or more in the input RF signal and generate the bias current as a bias current corresponding to the third signal, or detect a fourth signal corresponding to a fourth level or less in the input RF signal and generate the bias current as a bias current corresponding to the fourth signal.

In the first power mode, the bias current may increase in response to the first signal or the bias current may decrease in response to the second signal, and in the second power mode, the bias current may increase in response to the third signal or the bias current may decrease in response to the fourth signal.

The first signal may correspond to a signal having the first level or more in an upper envelope signal of the input RF signal, the second signal may correspond to a signal having the second level or less in a lower envelope signal of the input RF signal, the third signal may correspond to a signal having the third level or more in the upper envelope signal of the input RF signal, and the fourth signal may correspond to a signal having the fourth level or less in the lower envelope signal of the input RF signal.

The bias circuit may include a main bias circuit configured to generate a main bias current using a reference current; a first signal detection circuit configured to generate the first signal or the third signal using the input RF signal; a second signal detection circuit configured to generate the second signal or the fourth signal using the input RF signal; and an adjustment bias circuit configured to generate an adjustment bias current corresponding to the first signal, or the second signal, or the third signal, or the fourth signal, and the bias current may be equal to a sum of the main bias current and the adjustment bias current.

The main bias circuit may include a first transistor configured to provide the main bias current to the power transistor, and the adjustment bias circuit may include a second transistor configured to provide the adjustment bias current to the power transistor.

The first transistor may include a control terminal to which a current corresponding to the reference current is input, and a first terminal from which the main bias current is output, the second transistor may include a control terminal to which the first signal, or the second signal, or the third signal, or the fourth signal is input, and a first terminal from which the adjustment bias current is output, the first terminal of the first transistor and the first terminal of the second transistor may be connected to each other, and the adjustment bias circuit may further include a first resistor connected between the control terminal of the first transistor and the control terminal of the second transistor.

The first power mode may be any one of a high power mode, a medium power mode, and a low power mode, and the second power mode may be any one of the high power mode, the medium power mode, and the low power mode that is not the first power mode.

The bias circuit may further include a switch configured to select any one of the first to fourth signals according to the first and second power modes and output the selected any one signal to the adjustment bias circuit.

The first signal detection circuit may be further configured to, in the first power mode, generate the first signal as a first signal corresponding to a signal having the first level or more in an upper envelope signal of the input RF signal, and in the second power mode, generate the third signal as a third signal corresponding to a signal having the third level or more in an upper envelope signal of the input RF signal.

The second signal detection circuit may be further configured to, in the first power mode, generate the second signal as a second signal corresponding to a signal having the second level or less in a lower envelope signal of the input RF signal, and in the second power mode, generate the fourth signal as a fourth signal corresponding to a signal having the fourth level or less in a lower envelope signal of the input RF signal.

The first level may be the same as the third level, and the second level may be the same as the fourth level.

In another general aspect, a power amplifier includes a power transistor configured to amplify an input radio-frequency (RF) signal; and a bias circuit configured to provide a bias current to the power transistor, wherein the bias circuit is further configured to detect a first signal corresponding to a first level or more in the input RF signal and generate the bias current as a bias current corresponding to the first signal.

The first signal may be a signal corresponding to the first level or more in a upper envelope signal of the input RF signal.

The bias current may increase in response to the first signal.

The bias circuit may include a main bias circuit configured to generate a main bias current using a reference current; a signal detection circuit configured to detect the first signal using the input RF signal; and an adjustment bias circuit configured to generate an adjustment bias current corresponding to the first signal, wherein the bias current may be equal to a sum of the main bias current and the adjustment bias current.

The main bias circuit may include a first transistor configured to provide the main bias current to the power transistor, and the adjustment bias circuit may include a second transistor configured to provide the adjustment bias current to the power transistor.

The first transistor may include a control terminal to which a current corresponding to the reference current is input, and a first terminal from which the main bias current is output, the second transistor may include a control terminal to which the first signal is input, and a first terminal from which the adjustment bias current is output, the first terminal of the first transistor and the first terminal of the second transistor may be connected to each other, and the adjustment bias circuit may further include a first resistor connected between the control terminal of the first transistor and the control terminal of the second transistor.

The signal detection circuit may include a first terminal to which the input RF signal is input; a diode having an anode connected to the first terminal; a bias voltage generating circuit configured to provide a bias voltage to the anode of the diode; a capacitor connected between a cathode of the diode and a ground; and a second terminal configured to output the first signal.

The bias voltage generating circuit may be further configured to generate the bias voltage as a bias voltage having a value that varies according to a power mode.

The signal detection circuit may further include a first resistor connected between the bias voltage generating circuit and the anode of the diode; a variable resistor having one end connected to the cathode of the diode and a resistance that varies according to the power mode; and a second resistor connected between another end of the variable resistor and the ground.

The variable resistor may have a first resistance in a first power mode and a second resistance lower than the first resistance in a second power mode, and the first power mode may be a power mode requiring a higher power than the second power mode.

The bias voltage generating circuit may include a transistor including a control terminal, a first terminal, and a second terminal, wherein the first terminal is configured to be connected to a power supply voltage; a first resistor having one end connected to the second terminal of the transistor; a second resistor connected between another end of the first resistor and the ground; and a switch configured to output the bias voltage by selecting a voltage at the second terminal of the transistor or a voltage at another end of the first resistor according to the power mode.

The bias voltage may have a first voltage value in a first power mode and a second voltage value higher than the first voltage value in a second power mode, and the first power mode may be a power mode requiring a higher power than the second power mode.

The signal detection circuit may further include a first resistor connected between the bias voltage generating circuit and the anode of the diode; a variable gain amplifier having an input terminal connected to the cathode of the diode and having a gain that varies according to the power mode; and a second resistor connected between an output terminal of the variable gain amplifier and the ground.

The gain may have a first gain value in a first power mode and a second gain higher than the first gain in a second power mode, and the first power mode may be a power mode requiring a higher power than the second power mode.

In another general aspect, a power amplifier includes a power transistor configured to amplify an input radio-frequency (RF) signal; and a bias circuit configured to provide a bias current to the power transistor, wherein the bias circuit is further configured to detect a first signal corresponding to a first level or less in the input RF signal and generate the bias current as a bias current corresponding to the first signal.

The first signal may be a signal corresponding to the first level or less in a lower envelope signal of the input RF signal.

The bias current may decrease in response to the first signal.

The bias circuit may include a main bias circuit configured to generate a main bias current using a reference current; a signal detection circuit configured to detect the first signal using the input RF signal; and an adjustment bias circuit configured to generate an adjustment bias current corresponding to the first signal, wherein the bias current may equal to a sum of the main bias current and the adjustment bias current.

The signal detection circuit may include a first terminal to which the input RF signal is input; a diode having a cathode connected to the first terminal; a bias voltage generating circuit configured to provide a bias voltage to an anode of the diode; a capacitor connected between the anode of the diode and a ground; and a second terminal configured to output the first signal.

The bias voltage generating circuit may be further configured to generate the bias voltage as a bias voltage having a value that varies according to a power mode.

The signal detection circuit may further include a first resistor connected between the cathode of the diode and the ground; a variable resistor having one end connected to the anode of the diode and having a resistance that varies according to the power mode; and a second resistor connected between the bias voltage generating circuit and another end of the variable resistor.

The variable resistor may have a first resistance in a first power mode and a second resistance lower than the first resistance in a second power mode, and the first power mode may be a power mode requiring a higher power than the second power mode.

The signal detection circuit may further include a first resistor connected between the cathode of the diode and the ground; a variable gain amplifier having an input terminal connected to the anode of the diode and having a gain that varies according to the power mode; and a second resistor connected between the bias voltage generating circuit and an output terminal of the variable gain amplifier.

The gain may be a first gain in a first power mode and a second gain higher than the first gain in a second power mode, and the first power mode may be a power mode requiring a higher power than the second power mode.

The bias voltage may have a first voltage value in a first power mode and a second voltage value higher than the first voltage value in a second power mode, and the first power mode may be a power mode requiring a higher power than the second power mode.

In another general aspect, a power amplifier includes a first power transistor configured to amplify a first input radio-frequency (RF) signal; a first bias circuit configured to provide a first bias current to the first power transistor; a second power transistor configured to amplify a second input RF signal; and a second bias circuit configured to provide a second bias current to the second power transistor, wherein the first bias circuit is further configured to detect a first signal corresponding to a first level or more in the first input RF signal and generate the first bias current as a first bias current corresponding to the first signal, and the second bias circuit is further configured to detect a second signal corresponding to a second level or less in the second input RF signal and generate the second bias current as a second bias current corresponding to the second signal.

The second input RF signal may be an RF signal amplified and output by the first power transistor.

The first bias current may increase in response to the first signal, and the second bias current may decrease in response to the second signal.

The first signal may be a first signal corresponding to the first level or more in a upper envelope signal of the first input RF signal, and the second signal may be a second signal corresponding to the second level or less in a lower envelope signal of the second input RF signal.

The first bias circuit may include a first main bias circuit configured to generate a first main bias current using a first reference current; a first signal detection circuit configured to generate the first signal using the first input RF signal; and a first adjustment bias circuit configured to generate a first adjustment bias current corresponding to the first signal, and the second bias circuit may include a second main bias circuit configured to generate a second main bias current using the second reference current; a second signal detection circuit configured to generate the second signal using the second input RF signal; and a second adjustment bias circuit configured to generate a second adjustment bias current corresponding to the second signal, wherein the first bias current may be equal to a sum of the first main bias current and the first adjustment bias current, and the second bias current may be equal to a sum of the second main bias current and the second adjustment bias current.

The first main bias circuit may include a first transistor configured to provide the first main bias current to the first power transistor, the first adjustment bias circuit may include a second transistor configured to provide the first adjustment bias current to the first power transistor, the second main bias circuit may include a third transistor configured to provide the second main bias current to the second power transistor, and the second adjustment bias circuit may include a fourth transistor configured to provide the second adjustment bias current to the second power transistor.

The first signal detection circuit may be further configured to generate the first signal as a first signal corresponding to a signal having the first level or more in an upper envelope signal of the first input RF signal, and the second signal detection circuit may be further configured to generate the second signal as a second signal corresponding to a signal having the second level or less in a lower envelope signal of the second input RF signal.

The first power transistor and the first bias circuit may constitute a first stage amplifier, and the second power transistor and the second bias circuit may constitute a second stage amplifier.

Throughout the drawings and the detailed description, the same reference numerals refer to the same elements. The drawings may not be to scale, and the relative sizes, proportions, and depictions of elements in the drawings may be exaggerated for clarity, illustration, and convenience.

DETAILED DESCRIPTION

FIG.1Ais a graph showing a gain compression that occurs in a general power amplifier.

InFIG.1A, the horizontal axis represents the magnitude of the input RF signal input to the power amplifier, and the vertical axis represents the gain of the power amplifier. As described in the Background section, when the DSC of the bias circuit is low, a gain compression may occur. The gain decreases as the magnitude of the input RF signal increases. The gain initially decreases gradually, and then decreases more sharply near the output saturation power of the power amplifier. Particularly, referring to S110ofFIG.1A, the gain may decrease more sharply as the magnitude of the input RF signal increases near the output saturation power. The magnitude of the input RF signal may indicate an absolute value of the level of the input RF signal.

FIG.1Bis a graph showing a gain expansion that occurs in a general power amplifier.

InFIG.1B, the horizontal axis represents the magnitude of the input RF signal input to the power amplifier, and the vertical axis represents the gain of the power amplifier. As described in the Background section, when the DSC of the bias circuit is high, a gain expansion may occur. The gain increases as the magnitude of the input RF signal increases. The gain initially increases gradually, and then increases more sharply near the output saturation power of the power amplifier. Particularly, referring to S120ofFIG.1B, the gain may increase more sharply as the magnitude of the input RF signal increases near the output saturation power.

Examples of improving the gain compression shown inFIG.1Aor the gain expression shown inFIG.1Bare described below. Examples described below may improve linearity by controlling the bias current in response to the level of the input RF signal. As one example, when the power amplifier has a gain compression characteristic, the power amplifier may generate a bias current by detecting a signal having a predetermined level or more in the input RF signal. As another example, when the power amplifier has a gain expansion characteristic, the power amplifier may generate a bias current by detecting a signal having a predetermined level or less in the input RF signal.

FIG.2illustrates a power amplifier1000A according to an example.

As shown inFIG.2, the power amplifier1000A may include a power transistor100, a bias circuit200A, a capacitor C1, and an inductor L1.

InFIG.2, an input RF signal input to the power amplifier1000A is denoted by ‘RFIN’, and an output RF signal output from the power amplifier1000A is denoted by ‘RFOUT’.

The power transistor100may include an input terminal and an output terminal. The input terminal may be the base of the power transistor100, and the output terminal may be the collector of the power transistor. The power transistor100may amplify a power of the input RF RFINinput to the input terminal (for example, the base) and output the amplified power to the output terminal (for example, the collector). An emitter of the power transistor100may be connected to a ground, and although not shown inFIG.2, a resistor may be connected between the emitter of the power transistor100and the ground. In addition, the collector of the power transistor100may be connected to a power supply voltage VCCthrough the inductor L1, and the power transistor100may be operated by the power supply voltage VCC. The inductor L1may be connected between the power supply voltage VCCand the collector of the power transistor100and may perform an RF choke function.

The power transistor100may be implemented by various types of transistors such as a heterojunction bipolar transistor (HBT), a bipolar junction transistor (BJT), and an insulated gate bipolar transistor (IGBT). In addition, although the power transistor100is shown as an n-type transistor inFIG.2, it may be replaced with a p-type transistor.

The capacitor C1is a coupling capacitor and may be connected to the input terminal (for example, the base) of the power transistor100. That is, the input RF signal RFINmay be input to one end of the capacitor C1, and the other end of the capacitor C1may be connected to the base of the power transistor100. The capacitor C1may perform a function of blocking a direct current (DC) component in the input RF signal RFIN.

The bias circuit200A may receive a reference current IREFand a power supply voltage VBATfrom the outside. The power supply voltage VBATmay be a voltage supplied from a battery. The bias circuit200A may generate a bias current IBIAS_Arequired by the power transistor100using the reference current IREFand the power supply voltage VBAT. The bias current IBIAS_Ais supplied to the input terminal (for example, the base) of the power transistor100, and a bias level (a bias point) of the power transistor100may be set by the bias current IBIAS_A.

A power amplifier may be designed in advance to have a gain compression characteristic as shown inFIG.1Aaccording to a purpose or design direction. In order to improve the linearity of a power amplifier having a gain compression characteristic, the power amplifier1000A may detect a signal having a predetermined level or more in the input RF signal RFIN, and generate the bias current IBIAS_Acorresponding to the detected signal.

As shown inFIG.2, the bias circuit200A may include a main bias circuit210, an adjustment bias circuit220A, and a signal detection circuit230A.

The main bias circuit210may receive the reference current IREFand the power supply voltage VBATfrom the outside. The main bias circuit210may generate a main bias current IMAIN_Ausing the reference current IREFand the power supply voltage VBAT.

The signal detection circuit230A may receive the input RF signal RFINand generate a detection signal VDET_Acorresponding to a signal having a predetermined level or more in the input RF signal RFIN. The detection signal VDET_Ais input to the adjustment bias circuit220A. The detection signal VDET_Amay be a voltage signal. In more detail, the signal detection circuit230A may generate the detection signal VDET_A, which is a signal corresponding to a predetermined level or more in an upper envelope signal of the input RF signal RFIN. That is, the signal detection circuit230A may generate the detection signal VDET_Ausing an upper envelope signal of the input RF signal RFIN. Examples of the signal detection circuit230A will be described with reference toFIGS.4A and4Bbelow. The upper envelope signal of the input RF signal RFINmay mean an envelope for an RF signal having a higher level than the average signal level of the input RF signal RFIN. For example, when the average signal level of the input RF signal RFINis 0 V, the upper envelope signal may mean an envelope for an RF signal higher than 0 V in the input RF signal RFIN.

The adjustment bias circuit220A may receive the power supply voltage VBATfrom the outside and may receive the detection signal VDET_Afrom the signal detection circuit230A. The adjustment bias circuit220A may generate an adjustment bias current IADJ_Ausing the power supply voltage VBATand the detection signal VDET_A. The adjustment bias current IADJ_Amay vary in response to the detection signal VDET_A. Since the detection signal VDET_Acorresponds to the input RF signal RFIN, the adjustment bias current IADJ_Amay vary in response to the input RF signal RFIN.

The adjustment bias circuit220A and the main bias circuit210are connected to each other, which will be described in more detail inFIG.3below.

The main bias current IMAIN_Agenerated by the main bias circuit210and the adjustment bias current IADJ_Agenerated by the adjustment bias circuit220A are added together and provided to the input terminal (base) of the power transistor100. That is, the bias current IBIAS_A, the main bias current IMAIN_A, and the adjustment bias current IADJ_Amay have a relationship expressed by Equation 1 below.

Assuming that the main bias current IMAIN_Ahas a fixed value, the bias current IBIAS_Amay vary according to the adjustment bias current IADJ_A. As described above, since the adjustment bias current IADJ_Avaries in response to the input RF signal RFIN, the bias current IBIAS_Amay vary in response to the input RF signal RFIN. When the input RF signal RFINhas a value equal to or greater than a predetermined level, the adjustment bias current IADJ_Amay increase. By increasing the adjustment bias current IADJ_A, a gain compression as shown inFIG.1Amay be improved. Improvement of the gain compression may mean that a linearity of the power amplifier1000A is improved.

FIG.3is a diagram showing internal configurations of the main bias circuit210and the adjustment bias circuit220A ofFIG.2.

As shown inFIG.3, the main bias circuit210may include a transistor T1, a transistor T2, a transistor T3, a resistor R1, a resistor R2, a resistor R3, and a capacitor C2.

The transistors T1to T3may be implemented by various types of transistors such as a heterojunction bipolar transistor (HBT), a bipolar junction transistor (BJT), and an insulated gate bipolar transistor (IGBT). In addition, although the transistors T1to T3are shown as n-type transistors inFIG.3, they may be replaced with p-type transistors.

Since the bases of the transistors T1to T3serve as control terminals, the term ‘control terminal’ may be used. Since the collectors of the transistors T1to T3are one terminal of the transistor, the terms ‘first terminal’ or ‘second terminal’ may be used. In addition, since the emitters of the transistors T1to T3are also one terminal of the transistor, the terms ‘second terminal’ or ‘first terminal’ may be used.

A base and a collector of the transistor T1may be connected to each other in a diode connection structure, and a collector of the transistor T1may receive the reference current IREFthrough the resistor R1. Transistor T1serves to sink a current I2from the reference current IREF. The reference current IREFmay be a current source.

A base and a collector of the transistor T2may be connected to each other in a diode connection structure, and the collector of the transistor T2may be connected to the emitter of the transistor T1. An emitter of the transistor T2may be connected to a ground. Although not shown inFIG.3, a resistor may be connected between the emitter of the transistor T2and the ground.

A collector of the transistor T3may be connected to the power supply voltage VBATthrough the resistor R2, and a base of the transistor T3may be connected to the base of the transistor T1. InFIG.3, a base voltage of the transistor T3is denoted by ‘VB3’. In addition, an emitter of the transistor T3may be connected to the input terminal (for example, the base) of the power transistor100through the resistor R3. A current flowing through the emitter of the transistor T3is the main bias current IMAIN_Adescribed inFIG.2. That is, the emitter of the transistor T3may provide the main bias current IMAIN_A.

The capacitor C2may be connected between the base of transistor T3and the ground. The capacitor C2may stabilize the base voltage VB3of the transistor T3and reduce an impedance of the transistor T3.

The reference current IREFis divided into a current I1and the current I2, and the current I1may be input to the base of the transistor T3. Accordingly, the main bias current IMAIN_Amay be determined corresponding to the current I1. Also, the main bias current IMAIN_Amay be determined corresponding to the base voltage VB3of the transistor T3.

As shown inFIG.3, the adjustment bias circuit220A may include a transistor T4and a resistor R4.

The transistor T4may be implemented by various types of transistors such as a heterojunction bipolar transistor (HBT), a bipolar junction transistor (BJT), and an insulated gate bipolar transistor (IGBT). In addition, although the transistor T4is shown as an n-type transistor inFIG.3, it may be replaced with a p-type transistor.

Since a base of the transistor T4serves as a control terminal, the term ‘control terminal’ may be used. Since a collector of the transistor T4is one terminal of the transistor, the terms ‘first terminal’ or ‘second terminal’ may be used. Also, since an emitter of the transistor T4is also one terminal of the transistor, the terms ‘second terminal’ or ‘first terminal’ may be used.

A collector of the transistor T4may be connected to the power supply voltage VBATthrough the resistor R2, and a base of the transistor T4may be connected to the base of transistor T3through the resistor R4. Also, the base of the transistor T4is connected to the signal detection circuit230A to receive the detection signal VDET_A. InFIG.3, the base voltage of the transistor T4is denoted by ‘VB4_A’, and the node where the base of the transistor T4, the signal detection circuit230A, and the resistor R4are connected to each other is denoted by ‘NA’.

The resistor R4may be connected between the base of the transistor T3and the base of the transistor T4. When the value of the resistor R4is set to a high value, the base voltage VB3of the transistor T3may affect the base voltage VB4_Aof the transistor T4from a direct current (DC) point of view. A voltage due to this affection is denoted by ‘VB34’ inFIG.3. In addition, when the value of the resistor R4is set to a high value, the base voltage VB3of the transistor T3and the base voltage VB4_Aof the transistor T4may not affect each other from the viewpoint of alternating current (AC). Accordingly, from the viewpoint of an AC signal (i.e., an RF signal), the detection signal VDET_Amay not affect the base voltage VB3of the transistor T3. Because of the resistor R4, a separate power supply biasing the base of the transistor T4may not be required.

The base voltage VB4_Aof the transistor T4may be equal to a sum of the voltage VB34and the detection signal VDET_A. That is, the base voltage VB4_Aof the transistor T4, the voltage VB34, and the detection signal VDET_Amay have a relationship expressed by Equation 2 below.

The detection signal VDET_Amay be an RF signal (i.e., an AC signal), and the voltage VB34may be a DC signal.

The emitter of the transistor T4may be connected to the input terminal (i.e., base) of the power transistor100through the resistor R3. That is, the emitter of the transistor T3and the emitter of the transistor T4may be connected to each other. One end of the resistor R3may be connected to the emitter of the transistor T3and the emitter of the transistor T4, and the other end of the resistor R3may be connected to the base of the power transistor100. A current flowing through the emitter of the transistor T4is the adjustment bias current IADJ_Adescribed inFIG.2. That is, the emitter of the transistor T4may provide the adjustment bias current IADJ_A.

The adjustment bias current IADJ_Amay vary in response to the base voltage VB4_Aof the transistor T4. In Equation 2, assuming that the voltage VB34is a fixed value, the base voltage VB4_Aof the transistor T4may vary in response to the detection signal VDET_A. Accordingly, the adjustment bias current IADJ_Amay vary in response to the detection signal VDET_A. When the base voltage VB3of the transistor T3is a fixed value, the main bias current IMAIN_Amay be a fixed value and the voltage VB34may also be a fixed value. Accordingly, when Equations 1 and 2 are considered together, the bias current IBIAS_Amay vary in response to the detection signal VDET_A.

FIG.4Ais a diagram illustrating the signal detection circuit230A ofFIG.2according to an example.

As shown inFIG.4A, the signal detection circuit230A according to an example may include a plurality of terminals P1, P2, P3, and P4, a capacitor C3, a bias voltage generating circuit231, a resistor R5, a diode D1, a capacitor C4, a variable resistor R6, a resistor R7, and a capacitor C5.

The input RF signal RFINis input to the terminal P1, and the detection signal VDET_Ais output from the terminal P2. That is, the terminal P1may be connected to one end of the capacitor C1, and the terminal P2may be connected to the base (i.e., node NA) of the transistor T4. In addition, the power supply voltage VBATmay be input to the terminal P4.

A power mode is input to the terminal P3. As an example, the power mode may include a high power mode (HPM) and a low power mode (LPM). As another example, the power mode may include a high power mode (HPM), a medium power mode (MPM), and a low power mode (LPM).

One end of the capacitor C3may be connected to the terminal P1. The capacitor C3is a coupling capacitor, and may perform a function of blocking a direct current (DC) component of the input RF signal RFIN.

An anode of the diode D1may be connected to the other end of the capacitor C3. InFIG.4A, a node where the diode D1and the capacitor C3are connected to each other is denoted by ‘NB’. The capacitor C4may be connected between a cathode of the diode D1and a ground.

One end of the variable resistor R6may be connected to the cathode of the diode D1, and the resistor R7may be connected between the other end of the variable resistor R6and the ground. A resistance of the variable resistor R6may vary according to the power mode. In order to set the magnitude of the detection signal VDET_Ato a similar magnitude regardless of the power mode, the variable resistor R6may have different resistances in different power modes. That is, a signal attenuation may be set differently according to the power mode by the resistance of the variable resistor R6that varies according to the power mode. Since the magnitude of the input RF signal RFINis large in the high power mode, the variable resistor R6may have a large resistance in the high power mode. Also, since the magnitude of the input RF signal RFINis small in the low power mode, the variable resistor R6may have a small resistance in the low power mode. That is, the resistance of the variable resistor R6may be set to a larger resistance in the high power mode than in the low power mode.

The capacitor C5may be connected between the other end of the variable resistor R6and the terminal P2. The capacitor C5is a coupling capacitor, and may perform a function of blocking a direct current (DC) component the detection signal VDET_A.

The bias voltage generating circuit231may generate a bias voltage VBIASusing the power supply voltage VBATinput through the terminal P4. The bias voltage generation circuit231may generate the bias voltage VBIAShaving a different value according to the power mode input through the terminal P3. The resistor R5is connected between the bias voltage generating circuit231and the node NB, and the bias voltage VBIASmay be applied to the anode of the diode D1through the resistor R5. By means of the bias voltage VBIAS, an operating voltage of the diode D1may be set differently according to the power mode.

FIG.4Bis a diagram illustrating a signal detection circuit230A′ according to another example.

As shown inFIG.4B, the signal detection circuit230A′ according to another example may include a plurality of terminals P1, P2, P3, and P4, a capacitor C3, a bias voltage generating circuit231, and a resistor R5, a diode D1, a capacitor C4, a variable gain amplifier AMP1, a resistor R7, and a capacitor C5. The signal detection circuit230A′ ofFIG.4Bis the same as the signal detection circuit230A ofFIG.4Aexcept that the variable resistor R6is replaced with the variable gain amplifier AMP1. Accordingly, overlapping descriptions may be omitted.

An input terminal of the variable gain amplifier AMP1may be connected to the cathode of the diode D1, and an output terminal of the variable gain amplifier AMP1may be connected to one end of the resistor R7. The resistor R7may be connected between the output terminal of the variable gain amplifier AMP1and the ground.

The gain of the variable gain amplifier AMP1may vary according to the power mode. In order to set the magnitude of the detection signal VDET_Ato a similar magnitude regardless of the power mode, the variable gain amplifier AMP1may have a different gains in different power modes. That is, the degree of signal amplification may be set differently according to the power mode by the gain of the variable gain amplifier AMP1that varies according to the power mode. Since the magnitude of the input RF signal RFINis large in the high power mode, the variable gain amplifier AMP1may have a low gain in the high power mode. Also, since the magnitude of the input RF signal RFINis small in the low power mode, the variable gain amplifier AMP1may have a high gain in the low power mode. That is, the gain of the variable gain amplifier AMP1may be smaller in the high power mode than in the low power mode. A method of adjusting the gain of the variable gain amplifier AMP1according to the power mode is known to those skilled in the art, so a detailed description thereof will be omitted.

FIG.5is a diagram illustrating the bias voltage generating circuit231ofFIGS.4A and4Baccording to an example.

As shown inFIG.5, the bias voltage generating circuit231according to an example may include a transistor T5, a resistor R8, a resistor R9, a resistor R10, and a switch SW1.

The transistor T5may be implemented by various types of transistors such as a heterojunction bipolar transistor (HBT), a bipolar junction transistor (BJT), and an insulated gate bipolar transistor (IGBT). In addition, although the transistor T5is shown as an n-type inFIG.3, it may be replaced with a p-type.

Since the base of the transistor T5serves as a control terminal, the term ‘control terminal’ may be used. Since the collector of the transistor T5is one terminal of the transistor, the terms ‘first terminal’ or ‘second terminal’ may be used. Also, since the emitter of the transistor T5is one terminal of the transistor, the terms ‘second terminal’ or ‘first terminal’ may be used.

The collector of the transistor T5may be connected to the power supply voltage VBATthrough the resistor R8, and the base of the transistor T5may be connected to the node NAofFIG.3. That is, the base of the transistor T5may be connected to the base of the transistor T3through the resistor R4. The resistor R4allows the base of the transistor T5to be DC biased similarly to the base of the transistor T3or the base of the transistor T4.

One end of the resistor R9may be connected to the emitter of the transistor T5, and the resistor R10may be connected between the other end of the resistor R9and the ground. InFIG.5, the voltage at the node where the emitter of the transistor T5and one end of the resistor R9are connected is denoted by ‘VBIAS_LPM’. In addition, the voltage at the node where the resistor R9and the resistor R10are connected to each other is denoted by ‘VBIAS_HPM’. The transistor T5is set to an operating state by the voltage VB34inFIG.3, and at this time, the bias voltage VBIAS_LPMis set to a higher value than the bias voltage VBIAS_HPM.

As an example, when the base voltage of the transistor T5is set to 2.4 V (i.e., when the voltage of the node NAis 2.4 V), the emitter voltage of the transistor T5may be 1.2 V. That is, the bias voltage VBIAS_LPMmay be 1.2 V. Here, it is assumed that the turn-on voltage of the base-emitter diode of the transistor T5is 1.2 V. By setting the values of the resistor R9and the resistor R10to appropriate values, the bias voltage VBIAS_HPMmay be set to 0.8 V.

The switch SW1may include two input terminals P1_1and P1_2, one output terminal P2_1, and a control terminal P_CON. The input terminal P1_1is connected to the emitter of the transistor T5and receives the bias voltage VBIAS_LPM. The input terminal P1_2is connected to the other end of the resistor R9and receives the bias voltage VBIAS_HPM. The output terminal P2_1is a terminal for outputting the bias voltage VBIASand may be connected to the resistor R5ofFIG.4A or4B. The control terminal P_CON is connected to the terminal P3ofFIG.4AorFIG.4Band receives the power mode. As an example, the switch SW1may be a double-pole single-throw (DPST) switch.

When the power mode is the low power mode (LPM), the switch SW1connects the input terminal P1_1and the output terminal P2_1to each other. At this time, the bias voltage VBIAS_LPMis output as the bias voltage VBIAS. That is, the bias voltage generating circuit231may output the bias voltage VBIAS_LPMin the low power mode.

When the power mode is the high power mode (HPM), the switch SW1connects the input terminal P1_2and the output terminal P2_1to each other. At this time, the bias voltage VBIAS_HPMis output as the bias voltage VBIAS. That is, the bias voltage generating circuit231may output the bias voltage VBIAS_HPMin the high power mode.

FIG.6is a graph showing a current (I)-voltage (V) characteristic of the diode D1ofFIGS.4A and4Bwhen using the bias voltage generating circuit231ofFIG.5.

InFIG.6, S600denotes the turn-on voltage of diode D1. When the bias voltage VBIASis applied to the anode of the diode D1, the operating voltage of the diode D1may vary.

When the bias voltage VBIAS_HPMcorresponding to the high power mode HPM is applied to the anode of the diode D1, the operating voltage of the diode D1may be between the 0 V voltage and the turn-on voltage S600. As an example, the operating voltage of the diode D1may be located at S610.

When the bias voltage VBIAS_LPMcorresponding to the low power mode LPM is applied to the anode of the diode D1, the operating voltage of the diode D1may be located near the turn-on voltage S600. As an example, the operating voltage of the diode D1may be located at S620.

In this way, the bias voltage VBIASis set differently according to the power mode, so that the position relative to the operating voltage of the diode D1may vary. Through this, regardless of the magnitude of the input RF signal RFIN, the signal detection circuits230A and230A′ may generate the detection signal VDET_Acorresponding to a predetermined level or more in the envelope signal of the input RF signal RFIN.

FIG.7is a diagram illustrating a bias voltage generating circuit231′ according to another example.

As shown inFIG.7, the bias voltage generating circuit231′ according to another example may include a resistor R8, a resistor R9, a resistor R10, a resistor R11, and a switch SW1′. The bias voltage generating circuit231′ ofFIG.7may be similar to the bias voltage generating circuit231ofFIG.5except that the resistor R11is added and the switch SW1′ and the power modes are changed. The power modes may further include a medium power mode (MPM) in addition to the high power mode (HPM) and the low power mode (LPM).

One end of the resistor R9may be connected to the emitter of the transistor T5, and one end of the resistor R11may be connected to the other end of the resistor R9. The resistor R10may be connected between the other end of the resistor R11and the ground. InFIG.7, the voltage at the node where the emitter of the transistor T5and one end of the resistor R9are connected to each other is denoted by ‘VBIAS_LPM’. The voltage at the node where resistor R9and resistor R11are connected to each other is denoted by ‘VBIAS_MPM’. The voltage at the node where the resistor R11and R10are connected to each other is denoted by ‘VBIAS_HPM’. The transistor T5is set to an operating state by the voltage VB34inFIG.3, and at this time, the bias voltage VBIAS_LPMis set to a higher value than the bias voltage VBIAS_MPM, and the bias voltage VBIAS_MPMis set to a higher value than the bias voltage VBIAS_HPM.

The switch SW1′ may include three input terminals P11, P1_2, and P1_3, one output terminal P2_1, and a control terminal P_CON. The input terminal P1_1is connected to the emitter of the transistor T5and receives the bias voltage VBIAS_LPM. The input terminal P1_3is connected to the other end of the resistor R9and receives the bias voltage VBIAS_MPM. The input terminal P1_2is connected to the other end of the resistor R11and receives the bias voltage VBIAS_HPM. The output terminal P2_1is a terminal for outputting the bias voltage VBIASand may be connected to the resistor R5ofFIG.4AorFIG.4B. The control terminal P_CON is connected to the terminal P3ofFIG.4AorFIG.4Band receives the power mode. As an example, the switch SW1′ may be a three-pole single-throw (3PST) switch.

When the power mode is the low power mode (LPM), the switch SW1′ connects the input terminal P1_1and the output terminal P2_1to each other. At this time, the bias voltage VBIAS_LPMis output as the bias voltage VBIAS. That is, the bias voltage generating circuit231′ may output the bias voltage VBIAS_LPMin the low power mode.

When the power mode is the medium power mode (MPM), the switch SW1′ connects the input terminal P1_3and the output terminal P2_1to each other. At this time, the bias voltage VBIAS_MPMmay be output as the bias voltage VBIAS. That is, the bias voltage generating circuit231′ may output the bias voltage VBIAS_MPMin the medium power mode.

When the power mode is the high power mode, the switch SW1′ connects the input terminal P1_2and the output terminal P2_1to each other. At this time, the bias voltage VBIAS_HPMmay be output as the bias voltage VBIAS. That is, the bias voltage generating circuit231′ may output the bias voltage VBIAS_HPMin the high power mode.

FIG.8is a graph showing a current (I)-voltage (V) characteristic of the diode D1ofFIGS.4A and4Bwhen using the bias voltage generating circuit231′ ofFIG.7.

The graph ofFIG.8may be similar to the graph ofFIG.6except that the operating voltage for the bias voltage VBIAS_MPMis added.

Referring toFIG.8, when the bias voltage VBIAS_MPMcorresponding to the medium power mode MPM is applied to the anode of the diode D1, the operating voltage of the diode D1may be located between S610and S620. As an example, the operating voltage of the diode D1may be located at S630.

FIG.9is a diagram showing an example of signals in the signal detection circuits230A and230A′ ofFIGS.4A and4B.

InFIG.9, S900denotes an example of an input RF signal RFIN. S910denotes an example of an upper envelope signal in the input RF signal RFIN. In the signal detection circuits230A and230A′, the diode D1and the capacitor C4act as a rectifying circuit. That is, an upper envelope of the input RF signal RFINmay be detected by the diode D1and the capacitor C4.

InFIG.9, a dotted line S920denotes a value corresponding to the bias voltage VBIAS. Due to the bias voltage VBIASapplied to the diode D1, the signal detection circuits230A and230A′ may detect only values exceeding S920in the upper envelope signal S910. Accordingly, the detection signal VDET_Amay have signal such as S930. In other words, the signal detection circuits230A and230A′ may generate a detection signal VDET_Acorresponding to a signal having a predetermined level or more in the input RF signal RFIN. The predetermined level may correspond to the bias voltage VBIAS.

FIG.10Ais a graph conceptually illustrating the main bias current IMAIN_A.

InFIG.10A, the horizontal axis represents time (t), and the vertical axis represents the main bias current IMAIN_A.

As shown inFIG.10A, the main bias circuit200A may generate a main bias current IMAIN_Ahaving a constant value. The main bias current IMAIN_Amay be set at a constant value by the base voltage VB3of the transistor T3. As an example, the main bias current IMAIN_Amay be set to 90 mA.

FIG.10Bis a graph conceptually illustrating the adjustment bias current IADJ_A.

InFIG.10B, the horizontal axis represents time (t), and the vertical axis represents the adjustment bias current IADJ_A.

As described above with reference toFIG.3, the adjustment bias current IADJ_Amay vary in response to the base voltage VB4_Aof the transistor T4. As can be seen from Equation 2 above, since the base voltage VB4_Acorresponds to the voltage VB34having a constant value, the adjustment bias current IADJ_Amay include a constant current component. As an example, a constant current component of the adjustment bias current IADJ_Amay be 10 mA. As can be seen from Equation 2 above, the adjustment bias current IADJ_Amay vary in response to the detection signal VDET_A. When the detection signal VDET_Ahas the same waveform as S930ofFIG.9, the adjustment bias current IADJ_Amay have a current value similar to S930. As an example, the adjustment bias current IADJ_Amay vary between 10 mA and 20 mA. That is, the adjustment bias current IADJ_Amay have portions increasing from 10 mA.

FIG.10Cis a graph conceptually illustrating the bias current IBIAS_A.

InFIG.10C, the horizontal axis represents time (t), and the vertical axis represents the bias current IBIAS_A.

Referring to Equation 1, the bias current IBIAS_Ais equal to a sum of the main bias current IMAIN_Aand the adjustment bias current IADJ_A. Accordingly, the bias current IBIAS_Amay be as shown inFIG.10C. That is, when the main bias current IMAIN_Ashown inFIG.10Aand the adjustment bias current IADJ_Ashown inFIG.10Bare added together, the bias current IBIAS_Ashown inFIG.10Cmay be obtained. The bias current IBIAS_Amay have portions increasing from 100 mA. The gain compression characteristic of the power amplifier1000A may be improved due to the current in the increasing portions.

FIG.11is a graph showing a linearity improvement of the power amplifier1000A according to an example.

S1100indicates a gain compression characteristic, and S1110indicates an improved gain compression characteristic. The power amplifier1000A according to an example may improve linearity by detecting a signal having a predetermined level or more in the input RF signal RFIN, and generating a bias current IBIAS_Ain response to the detected signal. More specifically, the power amplifier1000A detects the detection signal VDET_A, which is a signal corresponding to a predetermined level or more in the upper envelope signal of the input RF signal RFIN, and additionally generates the adjustment bias current IADJ_Acorresponding to the detection signal VDET_A. Through this, linearity may be improved. That is, the gain compression characteristic of the power amplifier1000A may be improved due to the current in the increasing portions described inFIG.10C.

FIG.12illustrates a power amplifier1000B according to another example.

As shown inFIG.12, the power amplifier1000B may include a power transistor100, a bias circuit200B, a capacitor C1, and an inductor L1.

Since the power amplifier1000B ofFIG.12is similar to the power amplifier1000A ofFIG.2except that the bias circuit200A is replaced with the bias circuit200B, description of overlapping parts may be omitted.

The bias circuit200B may generate a bias current IBIAS_Brequired by the power transistor100using the reference current IREFand the power supply voltage VBAT. The bias current IBIAS_Bis supplied to the input terminal (for example, the base) of the power transistor100, and a bias level (bias point) of the power transistor100may be set by the bias current IBIAS_B.

The power amplifier may be designed in advance to have a gain expansion characteristic as shown inFIG.1Baccording to a purpose or design direction. In order to improve the linearity of the power amplifier having the gain expansion characteristic, the power amplifier1000B detects a signal having a predetermined level or less in the input RF signal RFIN, and generates a bias current IBIAS_Bcorresponding to the detected signal.

As shown inFIG.12, the bias circuit200B may include a main bias circuit210, an adjustment bias circuit220B, and a signal detection circuit230B. Since the bias circuit200B ofFIG.12is similar to the bias circuit200A ofFIG.2, description of overlapping parts may be omitted.

The main bias circuit210may generate the main bias current IMAIN_Ausing the reference current IREFand the power supply voltage VBAT.

The signal detection circuit230B may receive the input RF signal RFINand generate a detection signal VDET_Bcorresponding to a signal having a predetermined level or less in the input RF signal RFIN. The detection signal VDET_Bis input to the adjustment bias circuit220B. The detection signal VDET_Bmay be a voltage signal.

In more detail, the signal detection circuit230B may generate the detection signal VDET_B, which is a signal corresponding to a predetermined level or less in a lower envelope signal of the input RF signal RFIN. That is, the signal detection circuit230B may generate the detection signal VDET_Busing a lower envelope signal of the input RF signal RFIN. Examples of the signal detection circuit230B will be described with reference toFIGS.14A and14Bbelow. The lower envelope signal of the input RF signal RFINmay mean an envelope of an RF signal having a lower level than the average signal level of the input RF signal RFIN. For example, when the average signal level of the input RF signal RFINis 0 V, the lower envelope signal may mean an envelope for an RF signal lower than 0 V in the input RF signal RFIN.

The adjustment bias circuit220B may receive the power supply voltage VBATfrom the outside and may receive the detection signal VDET_Bfrom the signal detection circuit230B. The adjustment bias circuit220B may generate the adjustment bias current IADJ_Busing the power supply voltage VBATand the detection signal VDET_B. The adjustment bias current IADJ_Bmay vary in response to the detection signal VDET_B. Since the detection signal VDET_Bcorresponds to the input RF signal RFIN, the adjustment bias current IADJ_Bmay vary in response to the input RF signal RFIN.

The bias current IBIAS_B, the main bias current IMAIN_A, and the adjustment bias current IADJ_Bmay have a relationship expressed by Equation 3 below.

Assuming that the main bias current IMAIN_Ais a fixed value, the bias current IBIAS_Bmay vary according to the adjustment bias current IADJ_B. As described above, since the adjustment bias current IADJ_Bvaries in response to the input RF signal RFIN, the bias current IBIAS_Bmay vary in response to the input RF signal RFIN. When the input RF signal RFINhas a value below a predetermined level, the adjustment bias current IADJ_Bmay be reduced. By reducing the adjustment bias current IADJ_B, a gain expansion characteristic as shown inFIG.1Bmay be improved. Improvement in the gain expansion characteristic may mean that a linearity of the power amplifier10001B is improved.

FIG.13is a diagram showing internal configurations of the main bias circuit210and the adjustment bias circuit220B ofFIG.12.

Since the adjustment bias circuit220B ofFIG.13is similar to the adjustment bias circuit220A ofFIG.3except for some signals being changed, description of overlapping parts may be omitted.

The collector of the transistor T4may be connected to the supply voltage VBATthrough the resistor R2, and the base of the transistor T4may be connected to the base of transistor T3through the resistor R4. The base of the transistor T4is connected to the signal detection circuit230B to receive the detection signal VDET_B. InFIG.13, the base voltage of the transistor T4is denoted by ‘VB4_B’, and the node where the base of the transistor T4, the signal detection circuit230B, and the resistor R4are connected to each other is denoted by ‘NA’.

When the value of the resistor R4is set to a high value, the base voltage VB3of the transistor T3and the base voltage VB4_Bof the transistor T4may not affect each other from the viewpoint of alternating current (AC). Accordingly, from the viewpoint of an AC signal (i.e., an RF signal), the detection signal VDET_Bmay not affect the base of the transistor T3. Because of the resistor R4, a separate power supply biasing the base of transistor T4may not be required.

The base voltage VB4_Bof the transistor T4may be equal to a sum of the voltage VB34and the detection signal VDET_B. That is, the base voltage VB4_Bof the transistor T4may have a relationship expressed by Equation 4 below.

The detection signal VDET_Bmay be an RF signal (i.e., AC signal), and the voltage VB34may be a DC signal.

The emitter of the transistor T4may be connected to the input terminal (i.e., base) of the power transistor100through the resistor R3. The emitter of the transistor T3and the emitter of the transistor T4may be connected to each other. One end of the resistor R3may be connected to the emitter of the transistor T3and the emitter of the transistor T4, and the other end of the resistor R3may be connected to the base of the power transistor100. The current flowing through the emitter of the transistor T4is the adjustment bias current IADJ_Bdescribed inFIG.12. That is, the emitter of the transistor T4may output the adjustment bias current IADJ_B.

The adjustment bias current IADJ_Bmay vary in response to the base voltage VB4_Bof the transistor T4. In Equation 4, assuming that the voltage VB34is a fixed value, the base voltage VB4_Bof the transistor T4may vary in response to the detection signal VDET_B. Accordingly, the adjustment bias current IADJ_Bmay vary in response to the detection signal VDET_B. When the base voltage VB3of the transistor T3is a fixed value, the main bias current IMAIN_Amay be a fixed value and the voltage VB34may also be a fixed value. Accordingly, when Equations 3 and 4 are considered together, the bias current IBIAS_Bmay vary in response to the detection signal VDET_B.

FIG.14Ais a diagram illustrating a signal detection circuit230B according to an example.

As shown inFIG.14A, the signal detection circuit230B according to an example includes a plurality of terminals P1, P2, P3, and P4, a capacitor C6, a bias voltage generating circuit231, a resistor R14, a variable resistor R13, a diode D2, a capacitor C7, a resistor R12, and a capacitor C8.

The input RF signal RFINis input to the terminal P1, and the detection signal VDET_Bis output from the terminal P2. The terminal P1may be connected to one end of the capacitor C1, and the terminal P2may be connected to the base (i.e., node NA) of the transistor T4. In addition, the power supply voltage VBATmay be input to the terminal P4.

A power mode is input to the terminal P3. As an example, the power mode may include a high power mode (HPM) and a low power mode (LPM). As another example, the power mode may include a high power mode (HPM), a medium power mode (MPM), and a low power mode (LPM).

One end of the capacitor C6may be connected to the terminal P1. The capacitor C6is a coupling capacitor, and may perform a function of blocking a direct current (DC) component in the input RF signal RFIN.

A cathode of the diode D2may be connected to the other end of capacitor C6. The resistor R12may be connected between the cathode of diode D2and a ground. The capacitor C7may be connected between an anode of the diode D2and the ground. InFIG.14A, a node where the diode D2and the capacitor C7are connected to each other is denoted by ‘Nc’.

One end of the variable resistor R13may be connected to the anode of the diode D2, and the resistor R14may be connected between the other end of the variable resistor R13and the bias voltage generating circuit231. The resistance of the variable resistor R13may vary according to the power mode. In order to set the magnitude of the detection signal VDET_Bto a similar magnitude regardless of the power mode, the variable resistor R13may have different resistances in different power modes. That is, signal attenuation may be set differently according to the power mode by the resistance of the variable resistor R13that varies according to the power mode. Since the magnitude of the input RF signal RFINis large in the high power mode, the variable resistor R13may have a large resistance in the high power mode. Also, since the magnitude of the input RF signal RFINis small in the low power mode, the variable resistor R13may have a small resistance in the low power mode. That is, the resistance of the variable resistor R13may be set to a larger resistance in the high power mode than in the low power mode.

A capacitor C8may be connected between the other end of the variable resistor R13and the terminal P2. The capacitor C8is a coupling capacitor, and may perform a function of blocking a direct current (DC) component from a signal.

The bias voltage generating circuit231may generate a bias voltage VBIASusing the power supply voltage VBATinput through the terminal P4. The bias voltage generating circuit231may generate the bias voltage VBIAShaving a different value according to the power mode input through the terminal P3. The resistor R14is connected between the bias voltage generating circuit231and the other end of the variable resistor R13, and the bias voltage VBIASmay be applied to the anode of the diode D2through the resistor R14and the variable resistor R13

By means of the bias voltage VBIAS, an operating voltage of the diode D2may be set differently according to the power mode.

FIG.14Bis a diagram illustrating a signal detection circuit230B′ according to another example.

As shown inFIG.14B, the signal detection circuit230B′ according to another example includes a plurality of terminals P1, P2, P3, and P4, a capacitor C6, a bias voltage generating circuit231, and a resistor R14, a variable gain amplifier AMP2, a diode D2, a capacitor C7, a resistor R12, and a capacitor C8. The signal detection circuit230B′ ofFIG.14Bis the same as the signal detection circuit230B ofFIG.14Aexcept that the variable resistor R13is replaced with a variable gain amplifier AMP2. Accordingly, overlapping descriptions of each other may be omitted.

An input terminal of the variable gain amplifier AMP2may be connected to the anode of the diode D2, and an output terminal of the variable gain amplifier AMP2may be connected to one end of the capacitor C8. The capacitor C8may be connected between the output terminal of the variable gain amplifier AMP2and the terminal P2.

The gain of the variable gain amplifier AMP2may vary according to the power mode. In order to set the magnitude of the detection signal VDET_Bto a similar magnitude regardless of the power mode, the variable gain amplifier AMP2may have a different gains in different power modes. That is, the degree of signal amplification may be set differently according to the power mode by the gain of the variable gain amplifier AMP2that varies according to the power mode. Since the magnitude of the input RF signal RFINis large in the high power mode, the variable gain amplifier AMP2may have a low gain in the high power mode. Also, since the magnitude of the input RF signal RFINis small in the low power mode, the variable gain amplifier AMP2may have a high gain in the low power mode. That is, the gain of the variable gain amplifier AMP2may be set to a smaller gain in the high power mode than in the low power mode. A method of adjusting the gain of the variable gain amplifier AMP2according to the power mode is known to those skilled in the art, so a detailed description thereof will be omitted.

The specific configuration of the bias voltage generating circuit231ofFIGS.14A and14Bmay have the same configuration as the bias voltage generating circuit231ofFIG.5or the bias voltage generating circuit231′ ofFIG.7. The diode D2ofFIGS.14A and14Bmay operate similarly to the diode D1ofFIGS.4A and4B. Accordingly, the operating voltage of the diode D2may be varied by the bias voltage VBIAS. That is, since the bias voltage VBIASis set differently according to the power mode, the position of the bias voltage VBIASrelative to the operating voltage of the diode D1may vary as shown inFIGS.6and8. Through this, regardless of the magnitude of the input RF signal RFIN, the signal detection circuits230B and230B′ may generate the detection signal VDET_Bcorresponding to a predetermined level or less in the envelope signal of the input RF signal RFIN.

FIG.15is a diagram showing an example of signals in the signal detection circuits230B and230B′ ofFIGS.14A and14B.

InFIG.15, S1500indicates an example of an input RF signal RFIN. S1510indicates an example of a lower envelope signal in the input RF signal RFIN. In the signal detection circuits230B and230B′, the diode D2and the capacitor C7act as a rectifying circuit. That is, a lower envelope of the input RF signal RFINmay be detected by the diode D2and the capacitor C7.

InFIG.15, a dotted line S1520indicates a value corresponding to the bias voltage VBIAS. Due to the bias voltage VBIASapplied to the diode D2, the signal detection circuits230B and230B′ may detect only values corresponding to S1520or less in the lower envelope signal S1510. Accordingly, the detection signal VDET_Bmay have a signal such as S1530. In other words, the signal detection circuits230B and230B′ may generate the detection signal VDET_Bcorresponding to a signal having a predetermined level or less in the input RF signal RFIN. The predetermined level may correspond to the bias voltage VBIAS.

FIG.16Ais a graph conceptually illustrating the main bias current IMAIN_A.

InFIG.16A, the horizontal axis represents time (t), and the vertical axis represents the main bias current IMAIN_A.

As shown inFIG.16A, the main bias circuit200A may generate a main bias current IMAIN_Ahaving a constant value. The main bias current IMAIN_Amay have a constant value set by the base voltage VB3of the transistor T3. As an example, the main bias current IMAIN_Amay be 90 mA.

FIG.16Bis a graph conceptually illustrating the adjustment bias current IADJ_B.

InFIG.16B, the horizontal axis represents time (t), and the vertical axis represents the adjustment bias current IADJ_B.

As described above with reference toFIG.13, the adjustment bias current IADJ_Bmay vary in response to the base voltage VB4_Bof the transistor T4. As can be seen from Equation 4 above, since the base voltage VB4_Bcorresponds to the voltage VB34having a constant value, the adjustment bias current IADJ_Bmay include a constant current component. As an example, a constant current component of the adjustment bias current IADJ_Bmay be 10 mA. As can be seen from Equation 4 above, the adjustment bias current IADJ_Bmay vary in response to the detection signal VDET_B. When the detection signal VDET_Bhas the same waveform as S1530ofFIG.15, the adjustment bias current IADJ_Bmay have a current value similar to S1530. As an example, the adjustment bias current IADJ_Bmay vary between 10 mA and 0 mA. That is, the adjustment bias current IADJ_Bmay have portions decreasing from 10 mA.

FIG.16Cis a graph conceptually illustrating the bias current IBIAS_B.

InFIG.16C, the horizontal axis represents time (t), and the vertical axis represents the main bias current IBIAS_B.

Referring to Equation 3, the bias current IBIAS_Bis equal to a sum of the main bias current IMAIN_Aand the adjustment bias current IADJ_B. Accordingly, the bias current IBIAS_Bmay be as shown inFIG.16C. That is, when the main bias current IMAIN_Ashown inFIG.16Aand the adjustment bias current IADJ_Bshown inFIG.16Bare added together, the bias current IBIAS_Bshown inFIG.16Cmay be obtained. The bias current IBIAS_Bmay have portions decreasing from 100 mA. The gain expansion characteristic of the power amplifier1000B may be improved due to the current in the decreasing portions.

FIG.17is a graph showing a linearity improvement of the power amplifier1000B according to another example.

S1700indicates again expansion characteristic, and S1710indicates an improved gain expansion characteristic. The power amplifier1000B according to another example may improve a linearity of the power amplifier1000B by detecting a signal having a predetermined level or less in the input RF signals RFINand generating a bias current IBIAS_Bin response to the detected signal. More specifically, the power amplifier1000B detects the detection signal VDET_B, which is a signal corresponding to a predetermined level or less in the lower envelope signal of the input RF signal RFIN, and additionally generates the adjustment bias current IADJ_Bcorresponding to the detection signal VDET_B. Through this, the linearity of the power amplifier1000B may be improved. That is, the gain expansion characteristic of the power amplifier1000B may be improved due to the current fin the decreasing portions shown inFIG.16C.

FIG.18is a diagram illustrating a power amplifier1000C according to another example.

As shown inFIG.18, a power amplifier1000C may include a power transistor100, a bias circuit2000, a capacitor C1, and an inductor L1.

Since the power amplifier1000C ofFIG.18is similar to the power amplifier1000A ofFIG.2except that the bias circuit200A is replaced with the bias circuit2000, description of overlapping parts may be omitted.

The bias circuit2000may generate a bias current IBIAS_Aor a bias current IBIAS_Brequired by the power transistor100using the reference current IREFand the power supply voltage VBAT. The bias circuit2000may generate a bias current in response to a power mode. As an example, when the power mode is a first power mode, the bias circuit2000may generate the bias current IBIAS_A. When the power mode is a second power mode, the bias circuit2000may generate the bias current IBIAS_B. The bias current IBIAS_Aor the bias current IBIAS_Bis supplied to the input terminal (for example, the base) of the power transistor100, and a bias level (bias point) of the power transistor100may be set by the bias current IBIAS_Aor the bias current IBIAS_B.

The power amplifier1000C may have a gain compression characteristic or a gain expansion characteristic according to a power mode.

As an example, in the first power mode, the power amplifier1000C may have a gain compression characteristic or a gain expansion characteristic. In order to improve the linearity of the power amplifier1000C, the power amplifier1000C may detect a signal having a first level or more in the input RF signal RFINand generate the bias current IBIAS_Ain response to the detected signal when the power amplifier1000C has a gain compression characteristic. Alternatively, the power amplifier1000C may detect a signal having a second level or less in the input RF signal RFINand generate the bias current IBIAS_Bin response to the detected signal when the power amplifier1000C has a gain expansion characteristic.

As another example, in the second power mode, the power amplifier1000C may have a gain compression characteristic or a gain expansion characteristic. In order to improve the linearity of the power amplifier1000C, the power amplifier1000C may detect a signal having a third level or more in the input RF signal RFINand generate the bias current IBIAS_Ain response to the detected signal when the power amplifier1000C has a gain compression characteristic. Alternatively, the power amplifier1000C may detect a signal having a fourth level or less in the input RF signal RFINand generate the bias current IBIAS_Bin response to the detected signal when the power amplifier1000C has a gain expansion characteristic.

The first power mode may be any one of a high power mode (HPM), a medium power mode (MPM), and a low power mode (LPM), and the second power mode may be any one of a high power mode (HPM), a medium power mode (MPM), and low power mode (LPM) that is not the first power mode.

As shown inFIG.18, the bias circuit2000may include a main bias circuit210, an adjustment bias circuit220C, a signal detection circuit230A, a signal detection circuit230B, and a switch SW2. The bias circuit2000ofFIG.18is a combination of the bias circuit200A ofFIG.2and the bias circuit200B ofFIG.12and description of overlapping parts may be omitted.

The signal detection circuit230A may receive the input RF signal RFINand generate a detection signal VDET_Acorresponding to a signal having a predetermined level or more in the input RF signal RFIN. The detection signal VDET_Ais input to the switch SW2. The detection signal VDET_Amay be a voltage signal. In more detail, the signal detection circuit230A may generate the detection signal VDET_A, which is a signal corresponding to a predetermined level or more in an upper envelope signal of the input RF signal RFIN. That is, the signal detection circuit230A may generate the detection signal VDET_Ausing an upper envelope signal of the input RF signal RFIN. A specific configuration and operation of the signal detection circuit230A may be the same as that ofFIG.4A or4B.

The signal detection circuit230B may receive the input RF signal RFINand generate a detection signal VDET_Bcorresponding to a signal having a predetermined level or less in the input RF signal RFIN. The detection signal VDET_Bis input to the switch SW2. The detection signal VDET_Bmay be a voltage signal. More specifically, the signal detection circuit230B may generate the detection signal VDET_B, which is a signal corresponding to a predetermined level or less in a lower envelope signal of the input RF signal RFIN. That is, the signal detection circuit230B may generate the detection signal VDET_Busing a lower envelope signal of the input RF signal RFIN. A specific configuration and operation of the signal detection circuit230B may be the same as that ofFIG.14A or14B.

The switch SW2may include two input terminals P1_1and P1_2, one output terminal P2_1, and a control terminal P_CON. The input terminal P1_1is connected to the signal detection circuit230A and receives the detection signal VDET_A. The input terminal P1_2is connected to the signal detection circuit230B and receives the detection signal VDET_B. The output terminal P2_1is connected to the adjustment bias circuit220C and outputs the detection signal VDET_Aor the detection signal VDET_Bto the adjustment bias circuit2000. The control terminal P_CON may receive a power mode. The switch SW2may perform a switching operation according to the power mode input to the control terminal P_CON. As an example, the switch SW2may have a double-pole single-throw (DPST) structure.

The power amplifier1000C may have a gain compression characteristic in the first power mode. Accordingly, in the first power mode, the switch SW2may connect the input terminal P1_1and the output terminal P2_1to each other. That is, the switch SW2outputs the detection signal VDET_Ain the first power mode. The detection signal VDET_Agenerated by the signal detection circuit230A may be applied (input) to the adjustment bias circuit220C.

Alternatively, the power amplifier1000C may have a gain expansion characteristic in the first power mode. Accordingly, in the first power mode, the switch SW2may connect the input terminal P1_2and the output terminal P2_1to each other. That is, the switch SW2outputs the detection signal VDET_Bin the first power mode. The detection signal VDET_Bgenerated by the signal detection circuit230B may be applied (input) to the adjustment bias circuit220C.

The power amplifier1000C may have a gain compression characteristic in the second power mode. Accordingly, in the second power mode, the switch SW2may connect the input terminal P1_1and the output terminal P2_1to each other. That is, the switch SW2outputs the detection signal VDET_Ain the second power mode. The detection signal VDET_Agenerated by the signal detection circuit230A may be applied (input) to the adjustment bias circuit220C.

Alternatively, the power amplifier1000C may have a gain expansion characteristic in the second power mode. Accordingly, in the second power mode, the switch SW2may connect the input terminal P1_2and the output terminal P2_1to each other. That is, the switch SW2outputs the detection signal VDET_Bin the second power mode. The detection signal VDET_Bgenerated by the signal detection circuit230B may be applied (input) to the adjustment bias circuit220C.

The adjustment bias circuit220C may receive the power supply voltage VBATfrom the outside and receive the detection signal VDET_Aor the detection signal VDET_Bfrom the switch SW2.

When the detection signal VDET_Ais input from the switch SW2, the adjustment bias circuit220C may generate the adjustment bias current IADJ_Ausing the power supply voltage VBATand the detection signal VDET_A. The adjustment bias current IADJ_Amay vary in response to the detection signal VDET_A. Since the detection signal VDET_Acorresponds to the input RF signal RFIN, the adjustment bias current IADJ_Amay vary in response to the input RF signal RFIN. The bias current IBIAS_A, the main bias current IMAIN_A, and the adjustment bias current IADJ_Amay have the relationship expressed by Equation 1 above. Referring to Equation 1, since the adjustment bias current IADJ_Avaries in response to the input RF signal RFIN, the bias current IBIAS_Amay vary in response to the input RF signal RFIN. When the input RF signal RFINhas a value equal to or greater than a predetermined level, the adjustment bias current IADJ_Amay increase. By increasing the adjustment bias current IADJ_A, a gain compression characteristic may be improved.

When the detection signal VDET_Bis input from the switch SW2, the adjustment bias circuit220C may generate the adjustment bias current IADJ_Busing the power supply voltage VBATand the detection signal VDET_B. The adjustment bias current IADJ_Bmay vary in response to the detection signal VDET_B. Since the detection signal VDET_Bcorresponds to the input RF signal RFIN, the adjustment bias current IADJ_Bmay vary in response to the input RF signal RFIN. The bias current IBIAS_B, the main bias current IMAIN_A, and the adjustment bias current IADJ_Bmay have the relationship expressed by Equation 3 above. Referring to Equation 3, since the adjustment bias current IADJ_Bvaries in response to the input RF signal RFIN, the bias current IBIAS_Bmay vary in response to the input RF signal RFIN. When the input RF signal RFINhas a value below a predetermined level, the adjustment bias current IADJ_Bmay be reduced. By reducing the adjustment bias current IADJ_B, a gain expansion characteristic may be improved.

FIG.19is a diagram showing internal configurations of the main bias circuit210and the adjustment bias circuit220C ofFIG.18.

Since the adjustment bias circuit220C ofFIG.19is similar to the adjustment bias circuit220A ofFIG.3or the adjustment bias circuit220B ofFIG.13except that some signals are changed, description of overlapping parts may be omitted.

The collector of the transistor T4may be connected to the supply voltage VBATthrough the resistor R2, and the base of the transistor T4may be connected to the base of the transistor T3through the resistor R4. In addition, the base of the transistor T4is connected to the output terminal P2_1of the switch SW2to receive the detection signal VDET_Aor the detection signal VDET_B. InFIG.19, when the detection signal VDET_Ais input, the base voltage of the transistor T4is denoted by ‘VB4_A’, and when the detection signal VDET_Bis input, the base voltage of the transistor T4is denoted by ‘VB4_B’. In addition, the node where the base of the transistor T4, the output terminal P2_1of the switch SW2, and the resistor R4are connected to each other is denoted by ‘NA’.

When the detection signal VDET_Ais input from the switch SW2, the base voltage VB4_Aof the transistor T4may have the relationship expressed by Equation 2 above. The adjustment bias current IADJ_Amay vary in response to the base voltage VB4_Aof the transistor T4. Referring to Equation 2, assuming that the voltage VB34is a fixed value, the base voltage VB4_Aof the transistor T4may vary in response to the detection signal VDET_A. Accordingly, the adjustment bias current IADJ_Amay vary in response to the detection signal VDET_A. As an example, the adjustment bias current IADJ_Amay have the same value as that ofFIG.10B. When the base voltage VB3of the transistor T3is a fixed value, the main bias current IMAIN_Amay be a fixed value and the voltage VB34may also be a fixed value. Accordingly, the bias current IBIAS_Amay vary in response to the detection signal VDET_A. As an example, the bias current IBIAS_Amay have the same value as that ofFIG.10C, and a gain compression characteristic of the power amplifier1000C may be improved due to the current in the increasing portions.

When the detection signal VDET_Bis input from the switch SW2, the base voltage VB4_Bof the transistor T4may have the relationship expressed by Equation 4. The adjustment bias current IADJ_Bmay vary in response to the base voltage VB4_Bof the transistor T4. Referring to Equation 4, assuming that the voltage VB34is a fixed value, the base voltage VB4_Bof the transistor T4may vary in response to the detection signal VDET_B. Accordingly, the adjustment bias current IADJ_Bmay vary in response to the detection signal VDET_B. As an example, the adjustment bias current IADJ_Bmay have the same value as that ofFIG.16B. When the base voltage VB3of the transistor T3is a fixed value, the main bias current IMAIN_Amay be a fixed value and the voltage VB34may also be a fixed value. Accordingly, the bias current IBIAS_Bmay vary in response to the detection signal VDET_B. As an example, the bias current IBIAS_Bmay have a value as shown inFIG.16C, and the gain expansion characteristic of the power amplifier1000C may be improved due to the current in the decreasing portions.

FIG.20is a diagram illustrating a power amplifier2000according to another example.

The power amplifier2000ofFIG.20is a multi-stage power amplifier structure. A power transistor100_1, the bias circuit200A, a capacitor C1_1, and an inductor L1_1constitute a first stage amplifier2000_1, and the first stage amplifier2000_1may be similar to is the power amplifier1000A ofFIG.2. A power transistor1002, a bias circuit200B, a capacitor C1_2, and an inductor L1_2constitute a second stage amplifier20002, and the second stage amplifier20001may be similar to is the power amplifier1000B ofFIG.12. The first stage amplifier20001may be a driver amplifier, and the second stage amplifier2000_2may be a power amplifier.

The power transistor100_1may include an input terminal and an output terminal. The input terminal may be a base of the power transistor100_1, and the output terminal may be a collector of the power transistor100_1. The power transistor100_1may amplify a power of an input RF signal RFIN_1input to the input terminal (for example, the base) and output the amplified power to the output terminal (for example, the collector). An emitter of the power transistor100_1may be connected to a ground. Although not shown inFIG.20, a resistor may be additionally connected between the emitter of the power transistor100_1and the ground. In addition, the collector of the power transistor100_1may be connected to the power supply voltage VCCthrough the inductor L1_1, and the power transistor100_1may be operated by the power supply voltage VCC. The inductor L1_1is connected between the power supply voltage VCCand the collector of the power transistor100_1and may perform an RF choke function.

The power transistor100_1may be implemented by various types of transistors such as a heterojunction bipolar transistor (HBT), a bipolar junction transistor (BJT), and an insulated gate bipolar transistor (IGBT). Although the power transistor100_1is shown as an n-type transistor inFIG.20, it may be replaced with a p-type transistor.

The capacitor C1_1is a coupling capacitor and may be connected to the input terminal (for example, the base) of the power transistor100_1. That is, the input RF signal RFIN_1may be input to one end of the capacitor C1_1, and the other end of the capacitor C1_1may be connected to the base of the power transistor100_1. The capacitor C1_1may perform a function of blocking a direct current (DC) component in the input RF signal RFIN_1.

The bias circuit200A may receive a reference current IREFand a power supply voltage VBATfrom the outside. The bias circuit200A may generate the bias current IBIAS_Arequired by the power transistor100_1using the reference current IREFand the power supply voltage VBAT. The bias current IBIAS_Ais supplied to the input terminal (for example, the base) of the power transistor100_1, and the bias level (bias point) of the power transistor100_1may be set by the bias current IBIAS_A.

The first stage amplifier2000_1may have a gain compression characteristic. In order to improve the linearity of the first stage amplifier20001having the gain compression characteristic, the first stage amplifier2000_1detects a signal having a predetermined level or more in the input RF signal RFIN_1and generates a bias current IBIAS_Acorresponding to the detected signal.

As shown inFIG.20, the bias circuit200A may include a main bias circuit210_1, an adjustment bias circuit220A, and a signal detection circuit230A. The bias circuit200A ofFIG.20may have the same configuration and operation as the bias circuit200A ofFIG.2. That is, the main bias circuit210_1may have the same configuration as the main bias circuit210ofFIG.3, and the adjustment bias circuit220A ofFIG.20may have the same configuration as the adjustment bias circuit220A ofFIG.3.

The signal detection circuit230A may receive the input RF signal RFIN_1and generate a detection signal VDET_Acorresponding to a signal having a predetermined level or more in the input RF signal RFIN_1. The detection signal VDET_Ais input to the adjustment bias circuit220A. The detection signal VDET_Amay be a voltage signal. In more detail, the signal detection circuit230A may generate the detection signal VDET_A, which is a signal corresponding to a predetermined level or more in an upper envelope signal of the input RF signal RFIN_1. That is, the signal detection circuit230A may generate the detection signal VDET_Ausing an upper envelope signal of the input RF signal RFIN_1. The specific configuration and operation of the signal detection circuit230A may be the same as that ofFIG.4A or4B.

The adjustment bias circuit220A may receive the power supply voltage VBATfrom the outside and may receive the detection signal VDET_Afrom the signal detection circuit230A. The adjustment bias circuit220A may generate the adjustment bias current IADJ_Ausing the power supply voltage VBATand the detection signal VDET_A. The adjustment bias current IADJ_Amay vary in response to the detection signal VDET_A. Since the detection signal VDET_Acorresponds to the input RF signal RFIN_1, the adjustment bias current IADJ_Amay vary in response to the input RF signal RFIN_1. The bias current IBIAS_A, the main bias current IMAIN_A, and the adjustment bias current IADJ_Amay have the relationship expressed by Equation 1 above. Referring to Equation 1, since the adjustment bias current IADJ_Avaries in response to the input RF signal RFIN_1, the bias current IBIAS_Amay vary in response to the input RF signal RFIN_1. When the input RF signal RFIN_1has a value equal to or greater than a predetermined level, the adjustment bias current IADJ_Amay increase. By increasing the adjustment bias current IADJ_A, a gain compression characteristic may be improved. As an example, the adjustment bias current IADJ_Amay have the same value as that ofFIG.10Band the bias current IBIAS_Amay have the same value as that ofFIG.10C.

The power transistor1002may include an input terminal and an output terminal. The input terminal may be a base of the power transistor100_2, and the output terminal may be a collector of the power transistor. The power transistor100_2may amplify a power of an input RF signal RFIN_2input to the input terminal (for example, the base) and output the amplified power to the output terminal (for example, the collector). An emitter of the power transistor100_2may be connected to a ground. Although not shown inFIG.20, a resistor may be additionally connected between the emitter of the power transistor100_2and the ground. In addition, the collector of the power transistor100_2may be connected to the power supply voltage VCCthrough the inductor L1_2, and the power transistor100_2may be operated by the power supply voltage VCC. The inductor L1_2is connected between the power supply voltage VCCand the collector of the power transistor100_2and may perform an RF choke function.

The power transistor100_2may be implemented by various types of transistors such as a heterojunction bipolar transistor (HBT), a bipolar junction transistor (BJT), and an insulated gate bipolar transistor (IGBT). Although the power transistor100_2is shown as an n-type transistor inFIG.20, it may be replaced with a p-type transistor.

The capacitor C1-2is a coupling capacitor and may be connected between the output terminal (for, the collector) of the power transistor100_1and the input terminal (for example, the base) of the power transistor100_2. The output RF signal RFOUT_1of the first stage amplifier20001may be input to the input terminal (base) of the power transistor100_2through the capacitor C1_2. That is, the output RF signal RFOUT_1of the first stage amplifier2000_1may be the input RF signal RFIN_2of the second stage amplifier2000_2. The capacitor C1-2may perform a function of blocking a direct current (DC) component in the input RF signal RFIN_2.

The bias circuit200B may receive a reference current IREFand a power supply voltage VBATfrom the outside. The bias circuit200B may generate the bias current IBIAS_Brequired by the power transistor100_2using the reference current IREFand the power supply voltage VBAT. The bias current IBIAS_Bis supplied to the input terminal (for example, the base) of the power transistor100_2, and the bias level (bias point) of the power transistor100_2may be set by the bias current IBIAS_B.

The second stage amplifier2000_2may have a gain expansion characteristic. In order to improve the linearity of the second stage amplifier20002having the gain expansion characteristic, the second stage amplifier2000_2detects a signal having a predetermined level or less in the input RF signal RFIN_2and generates the bias current IBIAS_Bcorresponding to the detected signal.

As shown inFIG.20, the bias circuit200B may include a main bias circuit2102, an adjustment bias circuit220B, and a signal detection circuit230B. The bias circuit200B ofFIG.20may have the same configuration and operation as the bias circuit200B ofFIG.12. That is, the main bias circuit210_2may have the same configuration as the main bias circuit210ofFIG.13, and the adjustment bias circuit220B ofFIG.20may have the same configuration as the adjustment bias circuit220B ofFIG.13.

The signal detection circuit230B may receive the input RF signal RFIN_2and generate a detection signal VDET_Bcorresponding to a signal having a predetermined level or less in the input RF signal RFIN_2. The detection signal VDET_Bis input to the adjustment bias circuit220B. The detection signal VDET_Bmay be a voltage signal. In more detail, the signal detection circuit230B may generate the detection signal VDET_B, which is a signal corresponding to a predetermined level or less in a lower envelope signal of the input RF signal RFIN_2. That is, the signal detection circuit230B may generate the detection signal VDET_Busing a lower envelope signal of the input RF signal RFIN_2. The specific configuration and operation of the signal detection circuit230B may be the same as that ofFIG.14A or14B.

The adjustment bias circuit220B may receive the power supply voltage VBATfrom the outside and may receive the detection signal VDET_Bfrom the signal detection circuit230B. The adjustment bias circuit220B may generate the adjustment bias current IADJ_Busing the power supply voltage VBATand the detection signal VDET_B. The adjustment bias current IADJ_Bmay vary in response to the detection signal VDET_B. Since the detection signal VDET_Bcorresponds to the input RF signal RFIN_2, the adjustment bias current IADJ_Bmay vary in response to the input RF signal RFIN_2. The bias current IBIAS_B, the main bias current IMAIN_A, and the adjustment bias current IADJ_Bmay have the relationship expressed by Equation 3 above. Referring to Equation 3, since the adjustment bias current IADJ_Bvaries in response to the input RF signal RFIN_2, the bias current IBIAS_Bmay vary in response to the input RF signal RFIN_2. When the input RF signal RFIN_2has a value equal to or less than a predetermined level, the adjustment bias current IADJ_Bmay decrease. By reducing the adjustment bias current IADJ_B, a gain expansion characteristic may be improved. As an example, the adjustment bias current IADJ_Bmay have the same value as that ofFIG.16Band the bias current IBIAS_Bmay have the same value as that ofFIG.16C.

InFIG.20, the case where the first stage amplifier2000_1has a gain compression characteristic and the second stage amplifier2000_2has a gain expansion characteristic has been described, but the first stage amplifier2000_1may have a gain expansion characteristic and the second stage amplifier2000_2may have a gain compression characteristic. In this case, the bias circuit200A and the bias circuit200B may be interchanged with each other. That is, the first-stage amplifier2000_1may include the bias circuit200B instead of the bias circuit200A, and through this, the gain expansion characteristic may be improved. In addition, the second stage amplifier2000_2may include the bias circuit200A instead of the bias circuit200B, and through this, the gain compression characteristic may be improved.

As described above, according to at least one aspect, a linearity of a power amplifier may be improved by adjusting the bias current in response to the input RF signal.

Also, according to at least one aspect, a gain compression characteristic of the power amplifier may be improved by generating a bias current by detecting a signal having a predetermined level or more in the input RF signal.

Also, according to at least one aspect, a gain expansion characteristic of the power amplifier may be improved by generating a bias current by detecting a signal having a predetermined level or less in the input RF signal.