FIRMWARE UPDATE TECHNOLOGIES

It includes updating firmware on a device during operation of the device by: migrating a service executing on the device for execution on a second device; causing the device to enter a disabled state; storing the firmware for access by the device; and causing the device to reset, wherein the device reset comprises the device executing the stored firmware. It can include selecting a device to operate as a boot strap processor, wherein the selected device is one of a group of devices that are to execute the updated firmware and wherein the boot strap processor performs the causing the device to enter a disabled state, storing the firmware for access by the device, and causing the device to reset. The group of devices can comprise a group of threads within a central processing unit (CPU) socket. The group of devices can comprise central processing units (CPUs) within a CPU package.

BACKGROUND

Computing devices utilize firmware for hardware initialization, low-level hardware management, and managing a boot process. In addition to the platform firmware, computing devices may also include dedicated firmware for controller chips, peripheral devices, or other components. Firmware can be read at runtime and in connection with a boot, but may be updated in connection with a firmware update process.

For example, after a release of a central processing unit (CPU), updating a CPU's firmware may need to occur via a microcode patch to address security, functional or performance issues or problems. Some microcode can be activated at runtime, but some microcode is to be activated by a Basic Input/Output System (BIOS) during an initialization phase, which requires a system reset of the CPU. For example, a system reset may be required in connection with changing CPU fuses or physical layer interface (PHY) settings (e.g., memory or Peripheral Component Interconnect Express (PCIe)). However, resetting a CPU involves disabling the CPU from performing work.

FIG.1depicts an example process to apply a microcode (uCode) patch. At102, uCode activation by a BIOS can initiate a microcode patch, before a Boot Service. At104, BIOS Exit Boot Service can include an indication from the operating system (OS) to the BIOS that the OS has completed using boot services of BIOS. BIOS Exit Boot Service can be called by a Universal Extensible Firmware Interface (UEFI) OS loader image to terminate all boot services. The UEFI OS loader becomes responsible for the continued operation of the system. At106, during OS Runtime, BIOS services, other than Boot Service, can be utilized by the OS. At108, uCode activating at OS kernel can include the OS kernel activating the uCode patch. A system reset can occur after the uCode is activated. For example, some uCode updates involve a socket reset.

Some Cloud Service Providers (CSPs) are sensitive to system reset because an impact to service uptime and system reset could violate a key performance indicator (KPI) of the CPU vendor. Rebooting a CPU can lead to system downtime in which the CPU is not able to execute workloads or latency of workload completion increases. CPU downtime can increase total cost of ownership (TCO) of a data center owner or operator. In some cases, CSPs can queue the patch and wait for a time to schedule the system reset to activate the patch, but this can prolong security risks. Some CSPs transfer the services to redundant servers during a microcode update.

DETAILED DESCRIPTION

In some examples, microcode loading and activating can occur in a serial manner to activate microcode on a first processor by migrating work performed on the first processor to a second processor, placing the first processor in a reduced power state, providing the microcode for access by the first processor, and causing the first processor to wake up, which can also cause loading of the microcode. Microcode can be activated on a processor by changing its state from offline to online.

FIG.2provides an overview of operation. At202, BIOS Exit Boot Service can include an indication from the operating system (OS) to BIOS that the OS has completed using boot services of BIOS. BIOS Exit Boot Service can be called by a Universal Extensible Firmware Interface (UEFI) OS loader image to terminate all boot services and the UEFI OS loader becomes responsible for the continued operation of the system. At204, during OS Runtime, BIOS services, other than Boot Service, can be utilized by the OS. When the process of updating microcode firmware volumes to firmware storage (e.g., Serial Peripheral Interface (SPI) accessible flash) is completed, a System Management Interrupt (SMI) can cause transmission of a notification to the OS to start a process of microcode loading and activation. At206, the OS kernel can migrate services executing on a target processor to another processor and causing the target processor to enter an idle state. At208, uCode live patch activating at Runtime can include making available a microcode firmware volume for execution by the target processor. For example, a uCode patch could be applied at OS runtime by the OS writing to a register. At210, the target processor can enter an operational state and execute the microcode firmware volume. The microcode firmware volume can include a firmware update.

FIG.3depicts an example system. Central processing unit (CPU)302can include cores304-0to304-n, where n is an integer. A core can be an execution core or computational engine that is capable of executing instructions. A core can have access to its own cache and read only memory (ROM), or multiple cores can share a cache or ROM. Cores can be homogeneous and/or heterogeneous devices. Any type of inter-processor communication techniques can be used, such as but not limited to messaging, inter-processor interrupts (IPI), inter-processor communications, and so forth. Cores can be connected in any type of manner, such as but not limited to, bus, ring, or mesh. A core may support one or more instructions sets (e.g., the x86 instruction set (with some extensions that have been added with newer versions)); the MIPS instruction set of MIPS Technologies of Sunnyvale, CA; the ARM instruction set (with optional additional extensions such as NEON) of ARM Holdings of Sunnyvale, CA), including the instruction(s) described herein. In addition or alternative to use of a CPU, an XPU or xPU could be used. An XPU can include one or more of: a graphics processing unit (GPU), general purpose GPU (GPGPU), field programmable gate arrays (FPGA), Accelerated Processing Unit (APU), accelerator, or another processor. In some examples, a CPU socket can provide an electrical connection between CPU302and a connector to a motherboard or circuit board and the motherboard or circuit board can provide an electrical interface to one or more other devices with CPU302, such as devices318, storage320, and trusted entity350.

One or more core340-0to304-ncan execute an operating system (OS). In some examples, the OS can be Linux®, Windows® Server or personal computer, Android®, MacOS®, iOS®, VMware vSphere, or any other operating system. The OS and driver can execute on a CPU or processor sold or designed by Intel®, ARM®, AMD®, Qualcomm®, IBM®, Texas Instruments®, among others.

One or more devices318can include one or more of: an XPU, infrastructure processing unit (IPU), CPU, CPU socket, graphics processing unit (GPU), processor, accelerator device, Board Management Controller (BMC), storage controller, memory controller, display engine, a peripheral device, Intel® Management or Manageability Engine (ME), AMD Platform Security Processor (PSP), ARM core with TrustZone extension, network interface device, Platform Controller Hub (PCH), application specific integrated circuit (ASIC), and so forth.

For example, an ME can include one or more processors and allow for powering on, configuring, controlling, or resetting a computer system via communications received using a network interface. For example, an ME can provide for fan speed control and monitoring of temperature, voltage, current and fan speed sensors. For example, an ME can provide secure audio video communication path. For example, an ME can provide a secure boot process by requiring firmware to be verified by its digital signature prior to boot. A PCH can include a chipset that provides data paths and a display interface, input/output controller, clock, and other circuitry.

Trusted entity350can include a BIOS, BMC or other hardware that can send commands to an ME or other device and write firmware to storage320. For example, trusted entity350can transmit Intelligent Platform Management Interface (IPMI)-consistent commands to an ME or other device. Some examples provide a hot microcode patch update through an in-band channel and a hot microcode patch update through an out of band (OOB) channel. An in-band microcode patch update can be provided by a host such as a host OS. An OOB microcode patch update can be provided by another component than a host such as a BMC.

Boot firmware code or firmware can be associated with a header file that identifies a map of what boot code is to be copied by CPU302. For example, a.h file for a firmware code can have a flash image layout map of which segments of the firmware code are to be copied. When executed by a processor, firmware code can be executed by a processor to perform hardware initialization during a booting process (e.g., power-on startup or restart), and provide runtime services for operating systems and programs. In some examples, boot firmware code or firmware can include one or more of: Basic Input/Output System (BIOS), video BIOS (VBIOS), GPU BIOS, Universal Extensible Firmware Interface (UEFI), or a boot loader. The BIOS firmware can be pre-installed on a personal computer's system board or accessible through an SPI interface from a boot storage (e.g., flash memory). In some examples, firmware can include SPS. In some examples, a Universal Extensible Firmware Interface (UEFI) can be used instead or in addition to a BIOS for booting or restarting cores or processors. UEFI is a specification that defines a software interface between an operating system and platform firmware. UEFI can read from entries from disk partitions by not just booting from a disk or storage but booting from a specific boot loader in a specific location on a specific disk or storage. UEFI can support remote diagnostics and repair of computers, even with no operating system installed. A boot loader can be written for UEFI and can be instructions that a boot code firmware can execute and the boot loader is to boot the operating system(s). A UEFI bootloader can be a bootloader capable of reading from a UEFI type firmware.

A UEFI capsule is a manner of encapsulating a binary image for firmware code updates. But in some examples, the UEFI capsule is used to update a runtime component of the firmware code. The UEFI capsule can include updatable binary images with relocatable Portable Executable (PE) file format for executable or dynamic linked library (dll) files based on COFF (Common Object File Format). For example, the UEFI capsule can include executable (*.exe) files. This UEFI capsule can be deployed to a target platform as an SMM image via existing OS specific techniques (e.g., Windows Update for Azure, or LVFS for Linux).

In some examples, boot controller314can access firmware code322from storage320and copy the firmware code310to a memory device for execution by one or more of cores304-0to304-nand/or one or more of devices318for execution after exiting from idle state. In some examples, as described herein, boot controller314can be implemented by one or more of cores304-0to304-nor a thread of a core. Boot controller314can be implemented as any type of controller (e.g., microcontroller) or processor capable of managing firmware code loading and storage into memory306for access by a core (e.g., any of304-0to304-n) or one or more of devices318. In some examples, boot controller314can be implemented using a CPU core (e.g., any of304-0to304-n) or a thread of a multi-threaded core. In some examples, boot controller314can be coupled to storage320using interface330.

Interface330can provide communication using one or more of the following protocols: serial peripheral interface (SPI), enhanced SPI (eSPI), System Management Bus (SMBus), I2C, MIPI I3C®, Peripheral Component Interconnect Express (PCIe), Compute Express Link (CXL). See, for example, Peripheral Component Interconnect Express (PCIe) Base Specification 1.0 (2002), as well as earlier versions, later versions, and variations thereof. See, for example, Compute Express Link (CXL) Specification revision 2.0, version 0.7 (2019), as well as earlier versions, later versions, and variations thereof. In some examples, storage320can be connected to boot controller314using a fabric or network and a firmware update can be transmitted using one or more packets via a fabric or network interface (not shown).

For a CPU package-wide patch load, microcode can be applied on all processors in a package. For example, changing fit binding microcode may require a reset of all processors in a CPU package. In some examples, for a package-wide uniform patch load, one or more services executed by CPU, whose microcode is to be updated or changed, can be migrated for execution on a CPU in another package. The one or more processors in a target CPU package can be set to offline state. The microcode can be made available for execution by one or more processors in a target CPU package. The one or more processors in the target CPU package can be changed from offline to online as a group in order to activate execution of microcode of the processors on the target CPU package. Accordingly, a new or formerly executed service or function component in firmware image can be added at runtime to a device. Run-time microcode or firmware patches can be deployed for various central processing unit (CPU) firmware engines to fix bugs (errors), introduce newer capabilities, or revert to a prior firmware version. In other words, seamless activation of microcode in a system can occur using CPU hot plugging or hot adding with a CPU partial reset.

In some examples, for a non-uniform patch load, microcode of some but not all processors (e.g., cores) in a CPU package can be updated by initiating microcode update by idling or causing the processors whose microcode is to be reset.

In some examples, a target device whose microcode is to be updated or changed can be a core of a CPU. For a microcode change on a first core, a service executing on the first core can be migrated to execute on a second core in a same or different CPU package as that of the first core. The first core can be disabled and microcode can be loaded to microcode read only memory (ROM) or other memory or storage and available for access for the first core to execute the microcode. The disabled first core can be enabled to enter a reset flow and entering a reset flow can cause the first core to apply the firmware patch.

In some examples, a target CPU whose microcode is to be updated or changed can be a thread of a multi-threaded core. For a microcode change on a first thread, a service executing on the first thread can be migrated to execute on a second thread. The first thread can be disabled and microcode can be available for access for the first thread to execute the microcode. The disabled first thread can be enabled to enter a reset flow and entering a reset flow can cause the first thread to apply the firmware patch.

In some cases, microcode can be loaded from a Firmware Interface Table (FIT) and in order to be fully effective, a system reset occurs.

For example, BIOS Init code to wakeup a device and cause execution of a microcode patch can include a call stack as follows:

Operation of memory (e.g., memory306) and I/O devices (e.g., buses or network interface devices) can be maintained online during microcode updating and activation to attempt to avoid disrupting services on a CPU.

FIG.4depicts an example flow of operations to activate microcode on a device. An orchestrator can send a microcode firmware volume (FV) to be written to a firmware storage. At (1), a host OS (e.g., OS System management mode (SMM)) or BMC can cause the microcode FV image to be written to firmware storage. In some examples, firmware storage can include SPI accessible flash storage. Firmware storage can be written-to or read-from using an in-band channel. In some examples, the BMC can copy the microcode FV image to firmware storage through an out of band (OOB) channel. SMM can be an operating mode of some CPUs in which process execution, including OS execution, is suspended.

At (2), when or after the FV image is copied to firmware storage, the BMC or the OS can trigger a System Management Interrupt (SMI) to the non-target device to initiate boot loading operations on one or more other devices. The non-target device can operate as a bootstrap processor (BSP) for one or more other devices. Various examples of devices are described herein.

At (3), in response to the SMI, the BSP can notify the OS to start microcode FV loading and activation on a target device. At (4), in response to commencement of microcode FV loading and activation on a target device, the BMC can lock writing to the firmware storage to prevent another microcode from being written to the firmware storage during the microcode activation.

At (5), the BMC or OS can cause the BSP to trigger the target device, on which microcode will be activated, to enter an offline state. At (6), the BSP can send a command to cause the target device to enter offline state and disable operation of the target device. The target device can be in a Monitor Wait (MWAIT) or a C state such as C1, C2, C3, C4, C5, or C6 that provide for one or more of: reduced clock frequency to the device, reduced power to the device bus interface, or reduced voltage to the device.

Prior to entering offline state and disabling operation of the target device, the target device can migrate services executing on the target device to one or more other non-target devices and non-BSP device. In some examples, a BIOS executed by a device can request the OS to reschedule a thread on another device that is not being reset. For example, an OS scheduler can monitor levels of activity of devices, including one or more other non-target devices and non-BSP device and determine which online non-target and non-BSP device is to execute the service by load balance execution of services. In some examples, the target device can migrate services for execution on another device. The target device can inform the BSP that the target device is in a dead state or sleep state. The BSP can inform the BMC or OS that the device is in a dead or sleep state. If the device is a CPU, a notification that the CPU is in a dead or sleep state to the BMC or OS can be CPU_DEAD.

At (7), the OS or BMC can send a device online command to the BSP to cause activation of the target device in dead or sleep state and at (8), the BSP can send a command to the target device in dead or sleep state to enter online or higher power state. As part of (8), the BSP can send a INIT-SIPI-SIPI to the target device in dead or sleep state to enter online or higher power state. At (9), the target device in dead or sleep state can be awaken and execute firmware initialization code. Execution of firmware initialization code can cause the patch of microcode FV to be loaded and activated. At (10), the BSP can notify the BMC or OS that a target device, whose microcode FV was loaded and activated, is operational. If the device is a CPU, the notification can be CPU_UP.

One or more of operations or actions (6)-(10) can repeat to load and activate microcode FV on a group of devices by selection of another device to operate as a BSP for another target device, whose microcode FV has not yet been patched, until all target devices have had microcode FV loaded and activated.

At (11), the OS can instruct the BMC to unlock access to the firmware storage and allow microcode to be written to the firmware storage and at (12), the BMC can allow access to the firmware storage and allow other microcode to be written to the firmware storage, such as for another firmware update.

FIG.5depicts an example process that can be used to update firmware on a device. At502, based on receipt of a request to update a firmware of a device, a determination can be made if a device in a group of devices has not had microcode patched. If a device has not had microcode patched, the process continues to504. If all devices in a group of devices have had their microcode patched,502can repeat.

At504, a device can be selected to operate as a boot controller. The device can be a processor whose microcode has been patched in some cases. The device can include one or more of: an XPU, infrastructure processing unit (IPU), CPU, CPU socket, graphics processing unit (GPU), processor, accelerator device, Board Management Controller (BMC), storage controller, memory controller, display engine, a peripheral device, Intel® Management or Manageability Engine (ME), AMD Platform Security Processor (PSP), ARM core with TrustZone extension, network interface device, Platform Controller Hub (PCH), application specific integrated circuit (ASIC), and so forth. At506, a device, that is not boot controller and whose microcode has not been updated, can be selected to be a target device.

At508, the boot controller can cause migration of services executed on the selected target device to execution on another device. The another device can be a processor in a same socket or another device connected to a same motherboard, in a same server, in a rack of servers, or remotely accessible through a network or fabric. At510, the selected device can enter offline mode. At512, the boot controller can cause the selected target device to load the microcode that is to be executed. At514, the boot controller can cause the boot controller to enter online mode. Entering online mode can cause the boot controller to execute the loaded microcode. The process can return to502.

FIG.6depicts a system. Various examples can be used by system600or its components to update or access an updated firmware as described herein. System600includes processor610, which provides processing, operation management, and execution of instructions for system600. Processor610can include any type of microprocessor, central processing unit (CPU), graphics processing unit (GPU), Accelerated Processing Unit (APU), processing core, or other processing hardware to provide processing for system600, or a combination of processors. Processor610controls the overall operation of system600, and can be or include, one or more programmable general-purpose or special-purpose microprocessors, digital signal processors (DSPs), programmable controllers, application specific integrated circuits (ASICs), programmable logic devices (PLDs), or the like, or a combination of such devices. As described herein, microcode of a processor610can be updated by an offline-to-online operation and allowing a workload performed by such processor to be executed by another processor.

In one example, system600includes interface612coupled to processor610, which can represent a higher speed interface or a high throughput interface for system components that needs higher bandwidth connections, such as memory subsystem620or graphics interface640, or accelerators642. Interface612represents an interface circuit, which can be a standalone component or integrated onto a processor die. Where present, graphics interface640interfaces to graphics components for providing a visual display to a user of system600. In one example, graphics interface640can drive a high definition (HD) display that provides an output to a user. High definition can refer to a display having a pixel density of approximately 100 PPI (pixels per inch) or greater and can include formats such as full HD (e.g., 1180p), retina displays, 6K (ultra-high definition or UHD), or others. In one example, the display can include a touchscreen display. In one example, graphics interface640generates a display based on data stored in memory630or based on operations executed by processor610or both. In one example, graphics interface640generates a display based on data stored in memory630or based on operations executed by processor610or both.

Memory subsystem620represents the main memory of system600and provides storage for code to be executed by processor610, or data values to be used in executing a routine. Memory subsystem620can include one or more memory devices630such as read-only memory (ROM), flash memory, one or more varieties of random access memory (RAM) such as DRAM, or other memory devices, or a combination of such devices. Memory630stores and hosts, among other things, operating system (OS)632to provide a software platform for execution of instructions in system600. Additionally, applications634can execute on the software platform of OS632from memory630. Applications634represent programs that have their own operational logic to perform execution of one or more functions. Processes636represent agents or routines that provide auxiliary functions to OS632or one or more applications634or a combination. OS632, applications634, and processes636provide software logic to provide functions for system600. In one example, memory subsystem620includes memory controller622, which is a memory controller to generate and issue commands to memory630. It will be understood that memory controller622could be a physical part of processor610or a physical part of interface612. For example, memory controller622can be an integrated memory controller, integrated onto a circuit with processor610.

In one example, system600includes interface614, which can be coupled to interface612. In one example, interface614represents an interface circuit, which can include standalone components and integrated circuitry. In one example, multiple user interface components or peripheral components, or both, couple to interface614. Network interface650provides system600the ability to communicate with remote devices (e.g., servers or other computing devices) over one or more networks. Network interface650can include an Ethernet adapter, wireless interconnection components, cellular network interconnection components, USB (universal serial bus), or other wired or wireless standards-based or proprietary interfaces. Network interface1050can transmit data to a device that is in the same data center or rack or a remote device, which can include sending data stored in memory. Network interface650can receive data from a remote device, which can include storing received data into memory. As described herein, microcode of a processor610, memory subsystem620, network interface650, or an accelerator642can be updated by an offline-to-online operation and allowing a workload performed by such processor to be executed by another processor or accelerator.

In one example, system600includes one or more input/output (I/O) interface(s)660. I/O interface660can include one or more interface components through which a user interacts with system600(e.g., audio, alphanumeric, tactile/touch, or other interfacing). Peripheral interface670can include any hardware interface not specifically mentioned above. Peripherals refer generally to devices that connect dependently to system600. A dependent connection is one where system600provides the software platform or hardware platform or both on which operation executes, and with which a user interacts.

In one example, system600includes storage subsystem680to store data in a nonvolatile manner. In one example, in certain system implementations, at least certain components of storage680can overlap with components of memory subsystem620. Storage subsystem680includes storage device(s)684, which can be or include any conventional medium for storing large amounts of data in a nonvolatile manner, such as one or more magnetic, solid state, or optical based disks, or a combination. Storage684holds code or instructions and data646in a persistent state (i.e., the value is retained despite interruption of power to system600). Storage684can be generically considered to be a “memory,” although memory630is typically the executing or operating memory to provide instructions to processor610. Whereas storage684is nonvolatile, memory630can include volatile memory (i.e., the value or state of the data is indeterminate if power is interrupted to system600). In one example, storage subsystem680includes controller682to interface with storage684. In one example controller682is a physical part of interface614or processor610or can include circuits or logic in both processor610and interface614.

Various examples can be used in a base station that supports communications using wired or wireless protocols (e.g., 3GPP Long Term Evolution (LTE) (4G) or 3GPP 5G), on-premises data centers, off-premises data centers, edge network elements, edge servers and switches, fog network elements, and/or hybrid data centers (e.g., data center that use virtualization, cloud and software-defined networking to deliver application workloads across physical data centers and distributed multi-cloud environments).

In some examples, network interface and other examples described herein can be used in connection with a base station (e.g., 3G, 4G, 5G and so forth), macro base station (e.g., 5G networks), picostation (e.g., an IEEE 802.11 compatible access point), nanostation (e.g., for Point-to-MultiPoint (PtMP) applications).

Various examples may be implemented using hardware elements, software elements, or a combination of both. In some examples, hardware elements may include devices, components, processors, microprocessors, circuits, circuit elements (e.g., transistors, resistors, capacitors, inductors, and so forth), integrated circuits, ASICs, PLDs, DSPs, FPGAs, memory units, logic gates, registers, semiconductor device, chips, microchips, chip sets, and so forth. In some examples, software elements may include software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, APIs, instruction sets, computing code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof. Determining whether an example is implemented using hardware elements and/or software elements may vary in accordance with any number of factors, such as desired computational rate, power levels, heat tolerances, processing cycle budget, input data rates, output data rates, memory resources, data bus speeds and other design or performance constraints, as desired for a given implementation. A processor can be one or more combination of a hardware state machine, digital control logic, central processing unit, or any hardware, firmware and/or software elements. Some examples may be implemented using or as an article of manufacture or at least one computer-readable medium. A computer-readable medium may include a non-transitory storage medium to store logic. In some examples, the non-transitory storage medium may include one or more types of computer-readable storage media capable of storing electronic data, including volatile memory or non-volatile memory, removable or non-removable memory, erasable or non-erasable memory, writeable or re-writeable memory, and so forth. In some examples, the logic may include various software elements, such as software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, API, instruction sets, computing code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof.

Illustrative examples of the devices, systems, and methods disclosed herein are provided below. An example of the devices, systems, and methods may include any one or more, and any combination of, the examples described below.

Example 1 includes one or more examples and includes a method comprising: updating firmware on a device during operation of the device by: migrating a service executing on the device for execution on a second device; causing the device to enter a disabled state; storing the firmware for access by the device; and causing the device to reset, wherein the device reset comprises the device executing the stored firmware.

Example 2 includes one or more examples and includes selecting a device to operate as a boot strap processor, wherein the selected device is one of a group of devices that are to execute the updated firmware and wherein the boot strap processor performs the causing the device to enter a disabled state, storing the firmware for access by the device, and causing the device to reset.

Example 3 includes one or more examples, wherein the group of devices comprise a group of threads within a central processing unit (CPU) socket.

Example 4 includes one or more examples, wherein the group of devices comprise central processing units (CPUs) within a CPU package.

Example 5 includes one or more examples, wherein the migrating a service executing on the device for execution on a second device comprises: selecting the second device from among one or more processors to which the updated firmware is to be applied.

Example 6 includes one or more examples, wherein the firmware comprises a microcode firmware volume (FV).

Example 7 includes one or more examples, wherein the device comprises one or more of: a multi-thread core, a central processing unit (CPU), an XPU, a graphics processing unit (GPU), a network interface device, or application specific integrated circuit (ASIC).

Example 8 includes one or more examples, and includes a system comprising: at least one processor and circuitry to update firmware on a first processor of the at least one processor during operation of the first processor by: cause migration of a service executing on the first processor to a second processor of the at least one processor; cause the first processor to enter an idle state; and cause the first processor to exit from idle state, wherein the exit from idle state is to cause the first processor to execute the firmware.

Example 9 includes one or more examples, wherein the circuitry is to provide the firmware to the first processor when the first processor is in the idle state.

Example 10 includes one or more examples, wherein the circuitry comprises a boot strap processor and wherein the circuitry comprises a processor to which the updated firmware is to be applied or has been applied.

Example 11 includes one or more examples, wherein the at least one processor comprises a group of one or more threads within a central processing unit (CPU).

Example 12 includes one or more examples, wherein the at least one processor comprises central processing unit (CPU) within a CPU package.

Example 13 includes one or more examples, wherein the second processor is selected based on not having the firmware update applied.

Example 14 includes one or more examples, wherein the firmware comprises a microcode update.

Example 15 includes one or more examples, and includes a baseboard management controller (BMC) to cause the firmware update on the at least one processor.

Example 16 includes one or more examples, wherein the first processor comprises one or more of: a multi-thread core, a central processing unit (CPU), an XPU, a graphics processing unit (GPU), a network interface device, or application specific integrated circuit (ASIC).

Example 17 includes one or more examples, wherein the second processor is in a same CPU package as that of the first processor or the second processor is connected to a same circuit board as that of the first processor.

Example 18 includes one or more examples, and includes a computer-readable medium comprising instructions stored thereon, that if executed by one or more processors, cause the one or more processors to: migrate a service executing on a device for execution on a second device; cause the device to enter a disabled state; store firmware for access by the device; and cause the device to enter a reset flow, wherein the device entering a reset flow comprises the device executing the stored firmware.

Example 19 includes one or more examples, wherein a processor is to operate as a boot strap processor and the boot strap processor performs the cause the device to enter a disabled state, store firmware for access by the device and cause the device to enter a reset flow.

Example 20 includes one or more examples, wherein the migrate a service executing on the device for execution on a second device comprises: selecting the second device from among one or more devices to which the firmware is to be applied.

Example 21 includes one or more examples, wherein the device comprises one or more of: a multi-thread core, a central processing unit (CPU), an XPU, a graphics processing unit (GPU), a network interface device, or application specific integrated circuit (ASIC).