Magnetic disk device and method

According to an embodiment, a magnetic disk is provided with a first area including a plurality of blocks and a second area designated as a write destination by a host. The first memory is a volatile memory that receives write data received from the host. A controller estimates a degree of influence of ATI for each of the plurality of blocks, and sets a first block in which the degree of influence of ATI reaches the first threshold value and two blocks adjacent thereto to be unwritable. The controller selects one of one or more blocks which are not set to be unwritable and have free space among the plurality of blocks, and stores a copy of write data in the first memory in the selected one block at least for a period until the write data is written to the second area.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2023-033560, filed on Mar. 6, 2023; the entire contents of which are incorporated herein by reference.

FIELD

The present embodiment described herein relate generally to a magnetic disk device and a method.

BACKGROUND

In the related art, there is a magnetic disk device having a cache area on a magnetic disk. In such a magnetic disk device, data requested to be written by the host can be temporarily stored in the cache area.

Adjacent track interference (ATI) is known as one of influences on adjacent tracks at the time of writing to a magnetic disk. The influence of ATI received by the adjacent track accumulates according to the number of writes for one track, and the data of the adjacent track is eventually difficult to be read. Therefore, before it is difficult to read the data of the adjacent track, all the data of the adjacent track is rewritten.

DETAILED DESCRIPTION

According to the present embodiment, a magnetic disk device includes a magnetic disk, a first memory, a magnetic head, and a controller. The magnetic disk is provided with a first area including a plurality of blocks and a second area designated as a write destination by a host. The first memory is a volatile memory that receives write data received from the host. The magnetic head writes and reads data to and from the magnetic disk. The controller estimates a degree of influence of adjacent track interference (ATI) for each of the plurality of blocks. The controller sets the first block in which the degree of influence of ATI reaches the first threshold value among the plurality of blocks and the two blocks adjacent to the first block among the plurality of blocks as unwritable. The controller selects one of one or more blocks that are not set to be unwritable and have free space among the plurality of blocks, and stores a copy of write data in the first memory in the selected one block at least for a period until the write data is written to the second area.

Hereinafter, a magnetic disk device and a method according to an embodiment will be described in detail with reference to the accompanying drawings. In addition, the present invention is not limited by the following embodiment.

Embodiment

FIG.1is a schematic diagram illustrating an example of a configuration of a magnetic disk device1according to the embodiment.

The magnetic disk device1is connected to a host2. The magnetic disk device1can receive an access command such as a write command or a read command from the host2.

The magnetic disk device1includes a magnetic disk11having a magnetic layer formed on a surface thereof. The magnetic disk device1writes data to the magnetic disk11or reads data from the magnetic disk11in response to the access command.

The access command includes a logical address. The magnetic disk device1provides a logical address space to the host2. The logical address indicates a position in the address space. The host2designates a position where data is written or a position where data is read by using the logical address. That is, the logical address is position information designated by the host2. The logical address is referred to as a logical block address (LBA).

Data is written and read via a magnetic head22. In addition to the magnetic disk11, the magnetic disk device1includes a spindle motor12, a ramp13, an actuator arm15, a voice coil motor (VCM)16, a motor driver integrated circuit (IC)21, a magnetic head22, a hard disk controller (HDC)23, a head IC24, a read/write channel (RWC)25, a processor26, a RAM27, and a flash read only memory (FROM)28.

The magnetic disk11is rotated at a predetermined rotation speed by the spindle motor12attached coaxially. The spindle motor12is driven by the motor driver IC21.

The processor26controls the rotation of the spindle motor12and the rotation of the VCM16via the motor driver IC21.

The magnetic head22writes and reads information to and from the magnetic disk11by a write core22wand a read core22rprovided therein. The magnetic head22is attached to a distal end of the actuator arm15. The magnetic head22is moved in the radial direction of the magnetic disk11by the VCM16. Note that a plurality of the write cores22wor a plurality of the read core22r, or a plurality of the write cores22wand a plurality of the read core22rprovided in the magnetic head22may be provided for the single magnetic head22.

For example, when the rotation of the magnetic disk11is stopped, the magnetic head22is moved onto the ramp13. The ramp13is configured to hold the magnetic head22at a position spaced apart from the magnetic disk11.

The head IC24amplifies and outputs a signal read from the magnetic disk11by the magnetic head22during the read operation, and supplies the signal to the RWC25. In addition, the head IC24amplifies a signal corresponding to the data to be written supplied from the RWC25and supplies the amplified signal to the magnetic head22during the write operation.

The HDC23controls transmission and reception of data with the host2via the I/F bus.

The RAM27is used as a buffer for data to be written to the magnetic disk11and data read from the magnetic disk11.

The RAM27is used as an operation memory by the processor26. The RAM27is used as an area in which firmware is loaded and an area in which various types of management data are temporarily stored.

The RAM27includes a volatile memory capable of high-speed operation. The type of the memory constituting the RAM27is not limited to a specific type. The RAM27can be configured by, for example, a dynamic random access memory (DRAM), a static random access memory (SRAM), or a combination thereof. Note that the RAM27may include an any nonvolatile memory. Details of a method of using the RAM27will be described later.

The RWC25performs modulation such as error correction coding on data to be written supplied from the HDC23in units of sectors, and supplies the modulated data to the head IC24. In addition, the RWC25demodulates a signal read from the magnetic disk11and supplied from the head IC24, including error correction in units of sectors, to output the demodulated signal to the HDC23as digital data.

The processor26is, for example, a central processing unit (CPU). The RAM27and the flash read only memory (FROM)28are connected to the processor26.

The FROM28is a nonvolatile memory. The FROM28stores firmware (program data), various operation parameters, and the like.

The processor26performs overall control of the magnetic disk device1according to the firmware stored in the FROM28. For example, the processor26loads firmware from the FROM28or the magnetic disk11to the RAM27, and executes control of the motor driver IC21, the head IC24, the RWC25, the HDC23, and the like according to the loaded firmware.

The FROM28is used as a save destination of data in the RAM27when the power supply interruption occurs.

The configuration including the HDC23, the RWC25, and the processor26can also be regarded as a controller30that controls the operation of the magnetic disk device1. In addition to these components, the controller30may include other components (for example, the RAM27, the FROM28, or the like).

The firmware program may be stored in the magnetic disk11. Some or all of the functions of the processor26may be implemented by a hardware circuit such as a field-programmable gate array (FPGA) or an application specific integrated circuit (ASIC).

Note that the number of the magnetic disks11included in the magnetic disk device1is not limited to one. Furthermore, the magnetic disk device1may include actuator arms15and magnetic heads22in a number corresponding to the number of magnetic disks11. In addition, in a case where the magnetic disk device1includes a plurality of magnetic heads22, the plurality of magnetic heads22may be integrally moved, or the plurality of magnetic heads22may constitute a plurality of groups that is independently movable.

FIG.2is a diagram illustrating an example of a configuration of the magnetic disk11according to the embodiment. Servo data used for positioning the magnetic head22is written to the magnetic layer formed on the surface of the magnetic disk11by, for example, a servo writer or self-servo write (SSW).

FIG.2illustrates servo areas41disposed radially as an example of the arrangement of servo areas to which servo data is written. In the circumferential direction, a space between the two servo areas41is a data area42where data can be written. A plurality of concentric tracks43is provided in the radial direction of the magnetic disk11. The data area42on the track43is provided with a plurality of sectors in which data of a predetermined size is written. The predetermined size is a sector size.

The servo data includes a servo mark, a gray code, a burst pattern, and a post code. The servo mark indicates the start of the servo data. The gray code includes an ID for identifying each track43provided in the magnetic disk11, that is, a track number, and an ID for identifying each servo sector (that is, the servo area41) on the track43, that is, a servo sector number. The burst pattern is data used to detect the amount of positional deviation of the track indicated by the track number included in the gray code from the center. The track number included in the gray code is given as, for example, an integer value, and it is possible to obtain an offset amount of decimal places based on the position indicated by the track number by demodulating the burst pattern. That is, the current position of the magnetic head22in the radial direction is obtained by demodulating the burst pattern. The post code is data for correcting positional deviation of the shape of the track43defined by the gray code and the burst pattern from the ideal shape of the track43.

When writing data to the magnetic disk11or reading data from the magnetic disk11, the controller30executes positioning of the magnetic head22based on servo data read from the servo area41by the magnetic head22. The positioning of the magnetic head22includes seek control and tracking control.

The recording face of the magnetic disk11is divided into at least two areas having different uses. One of the at least two areas is an LBA area, and the other of the at least two areas is a media cache area.

FIG.3is a diagram illustrating an example of a plurality of areas disposed in the radial direction of the recording face of the magnetic disk11according to the embodiment.

In the example illustrated inFIG.3, on a recording face100of the magnetic disk11, an LBA area110a, a media cache area120a, an LBA area110b, a media cache area120b, an LBA area110c, a media cache area120c, an LBA area110d, and a media cache area120dare provided in this order from an inner side toward an outer side.

Hereinafter, each of the LBA area110a, the LBA area110b, the LBA area110c, and the LBA area110dmay be referred to as an LBA area110. Each of the media cache area120a, the media cache area120b, the media cache area120c, and the media cache area120dmay be referred to as a media cache area120.

LBAs are mapped to each LBA area110. Therefore, the host2can designate the position of the write destination or the position of the read destination among all the LBA areas110. Each LBA area110is a final storage destination of data (hereinafter, it is referred to as write data) requested to be written by a write command from the host2.

Each media cache area120is used as a temporary storage location of write data.

The number and positions of the media cache areas120provided on the recording face100are not limited to the example illustrated inFIG.3. Furthermore, the number and positions of the LBA areas110provided on the recording face100are not limited to the example illustrated inFIG.3. The recording face100may be provided with an area for an any use in addition to the LBA area110and the media cache area120.

Each media cache area120is an example of a first area. Each LBA area110is an example of a second area.

FIG.4is a schematic diagram illustrating an example of a configuration of a memory (that is, the RAM27and the FROM28) included in the magnetic disk device1according to the embodiment.

A buffer area271is allocated in the RAM27. The buffer area271stores write data received from the host2. That is, the buffer area271receives the write data received from the host2.

The RAM27is a volatile memory. Therefore, the write data stored in the buffer area271is lost from the buffer area271at the time of the power supply interruption. The magnetic disk device1of the embodiment has a power loss protection (PLP) function in order to prevent the write data from being lost from the magnetic disk device1when the write data in the buffer area271is lost.

According to the PLP function, when the power supply interruption occurs, the magnetic disk device1saves the write data in the buffer area271to the FROM28using the preliminary power such as the back electromotive force generated by the SPM12. The saving includes transfer, movement, or copy. The FROM28is provided with a PLP saving area281that is an area for saving write data. Since the FROM28is a nonvolatile memory, the write data saved in the PLP saving area281is not lost even after the power supply interruption. As a result, the write data received in the buffer area271is protected from loss due to the power supply interruption.

In the embodiment, as an example, the capacity of the PLP saving area281is smaller than the capacity of the buffer area271. Therefore, every time the amount of write data newly stored in the buffer area271reaches a predetermined amount of which data can be saved in the PLP saving area281(for example, the same amount as the capacity of the PLP saving area281), the controller30copies the write data newly stored in the buffer area271to any media cache area120. Hereinafter, the predetermined amount is referred to as a first amount.

Among the write data stored in the buffer area271, original write data whose copy has been written to the media cache area120is lost from the buffer area271when the power supply interruption occurs. After the power supply is resumed, the write data as the original write data is restored in the buffer area271based on the copy stored in the media cache area120.

Among the write data stored in the buffer area271, the amount of write data not yet copied to any media cache area120is controlled to be equal to or less than the first amount. Therefore, among the write data stored in the buffer area271, all the write data not yet copied to any of the media cache areas120is saved to the PLP saving area281in response to the power supply interruption.

Therefore, all the write data stored in the buffer area271is prevented from being lost from the magnetic disk device1due to power supply interruption.

Hereinafter, write data that has not yet been written to any LBA area110after being received from the host2will be referred to as temporary stored data. The temporarily stored data includes the write data stored in the buffer area271, a copy of the write data stored in the media cache area120, and the write data saved in the PLP saving area281.

Among the write data in the buffer area271, write data whose copy has not yet been written to any media cache area120will be referred to as unprotected temporarily stored data.

Further, a copy of the write data written to each media cache area120is referred to as copy data.

The RAM27stores an ATI management table50. The ATI management table50is used to estimate the degree of influence of ATI. Each media cache area120is divided into a plurality of blocks, and the degree of influence of ATI is estimated for each block based on the ATI management table50.

FIG.5is a schematic diagram for explaining an example of a plurality of blocks provided in each media cache area120. In the drawing, a media cache area120ais illustrated as a representative of the media cache areas120ato120d.

The media cache area120ais divided into eight MC blocks as a plurality of blocks. Identification numbers #0 to #7 are assigned to the eight MC blocks. The identification number of the MC block is referred to as an MC block number.

Each of the eight MC blocks has a capacity equal to or slightly larger than the first amount. Therefore, a copy of the first amount of unprotected temporarily stored data can be stored in each of the eight MC blocks.

Each of the eight MC blocks may occupy an area of less than one track or may occupy an area of one or more tracks. Each of the eight MC blocks may be configured by one track. The capacity of each of the eight MC blocks is not limited to the example described above. Each of the eight MC blocks may have a capacity that is twice or more the first amount.

The number of MC blocks included in each media cache area120is any number as long as it is plural. The number of MC blocks included in one media cache area120may be common or may not be common among the media cache areas120ato120d.

FIG.6is a schematic diagram illustrating an example of a data structure of the ATI management table50. In the example illustrated in the drawing, the ATI management table50includes a sub-table51for each media cache area120. Each sub-table51is a table in which an ATI counter is recorded for each MC block number.

When new copy data is written to a certain MC block, an ATI counter for an MC block in which copy data of any temporary storage data is already stored among MC blocks adjacent to the MC block to which the new copy data is written to is incremented by “1”. When the original temporarily stored data in the buffer area271corresponding to all the copy data stored in an MC block is written to the LBA area110, the ATI counter for the MC block is reset to “0”.

That is, the ATI counter indicates, regarding an MC block storing copy data, the number of times of writing to an adjacent MC block. In the embodiment, as an example, a difference of an ATI counter of an MC block from the minimum value of ATI counters among a media cache area120to which the MC block belongs to is regarded as the estimation value of the degree of ATI influence which the MC block has received. The difference is referred to as an ATI estimation value.

In general, the influence of ATI received by the adjacent track accumulates according to the number of writes for one track, and the data of the adjacent track is eventually difficult to be read. For example, in each LBA area110, the controller30rewrites all the data to the adjacent track43before it is difficult to read the data of the adjacent track43. Such rewrite for preventing the read from becoming difficult due to the influence of ATI will be referred to as an ATI refresh operation.

Here, a technique compared with that of the embodiment will be described. A technique compared with that of the embodiment is referred to as a comparative example. According to the comparative example, as in the embodiment, copying of temporary storage data to the media cache area is performed in a timely manner so that the amount of unprotected temporary storage data does not exceed the first amount. In addition, the ATI refresh operation is also executed in the media cache area.

In the comparative example, when the ATI refresh operation is executed in the media cache area, the process of copying temporary storage data to the media cache area is delayed by execution of the ATI refresh operation. As a result, the rate of reception of new write data from the host decreases. That is, the write performance of the magnetic disk device may be deteriorated by the ATI refresh operation in the media cache area.

In the embodiment, in order to eliminate the need for the ATI refresh operation in the media cache area120, when the estimation value of the degree of influence of ATI received by a certain MC block (referred to as a first MC block) reaches a predetermined level (referred to as a first threshold value), the controller30sets the MC blocks adjacent to the first MC block to be unwritable. Since writing to the MC blocks adjacent to the first MC block is prohibited, accumulation of the influence of ATI received by the first MC block is stopped. This prevents difficulty in reading data in the first MC block even if the ATI refresh operation is not executed on the first MC block.

Next, details of the operation of the magnetic disk device1of the embodiment will be described.

FIG.7is a flowchart illustrating an example of an operation according to reception of write data of the magnetic disk device1of the embodiment. Note that a series of operations illustrated in this drawing is executed, for example, every time the magnetic disk device1receives write data.

When the magnetic disk device1receives write data from the host2(S101), the controller30stores the write data in the buffer area271(S102). Then, the controller30determines whether the amount of unprotected temporarily stored data in the buffer area271reaches the first amount (S103).

When the amount of the unprotected temporarily stored data in the buffer area271has not reached the first amount (S103: No), the operation related to the write data received by the process of S101ends.

When the amount of unprotected temporarily stored data in the buffer area271reaches the first amount (S103: Yes), the controller30selects one MC block from all MC blocks which are not set to be unwritable and have free space (S104).

In the process of S104, the controller30selects one MC block based on command reordering. That is, the controller30selects the MC block that can be written earliest or as soon as possible based on the current position and moving speed of the magnetic head22and the positions of all the MC blocks that are not set to be unwritable and have free space.

The controller30copies the first amount of unprotected temporarily stored data in the buffer area271to the MC block selected by the process of S104(S105). Then, the operation corresponding to the reception of the write data ends.

FIG.8is a flowchart illustrating an example of an operation related to the PLP function of the magnetic disk device1of the embodiment.

When the power supply from the outside to the magnetic disk device1is stopped, the controller30detects the stop of the power supply as power supply interruption (S201).

For example, the controller30monitors a voltage of a power line (not illustrated) to which power is externally supplied. Then, when the voltage of the power line falls below a predetermined value, the controller30determines that the power supply interruption has occurred. Note that the method of detecting the power supply interruption is not limited thereto.

In response to the detection of the power supply interruption, the controller30saves the unprotected temporarily stored data in the buffer area271to the PLP saving area281(S202). The process of S202is executed using, for example, a back electromotive force generated by the SPM12. The amount of unprotected temporarily stored data in the buffer area271is controlled to be equal to or less than the first amount by a series of operations illustrated inFIG.7. Therefore, in the process of S202, the controller30can save all the unprotected temporarily stored data in the buffer area271to the PLP saving area281.

Following the process of S202, the magnetic disk device1stops the operation (S203).

Thereafter, when the power supply to the magnetic disk device1is resumed, the controller30transfers the temporarily stored data in the PLP saving area281and the copy data in the media cache area120to the buffer area271(S204). As a result, the temporarily stored data stored in the buffer area271immediately before the power supply interruption is restored in the buffer area271. Then, the operation related to the PLP function ends.

FIG.9is a flowchart illustrating an example of an operation of writing temporarily stored data in the buffer area271to the LBA area110in the magnetic disk device1according to the embodiment.

The controller30determines whether the magnetic disk device1is in an idle state (S301). The idle state is, for example, a state in which a period during which no access command is received from the host2exceeds a predetermined time.

When the magnetic disk device1is not in the idle state (S301: No), the process of S301is executed again.

When the magnetic disk device1is in the idle state (S301: Yes), the controller30selects write data related to one write command from the temporarily stored data in the buffer area271(S302). Here, the controller30selects the write data based on the command reordering. That is, write data that can be written to the write destination sector earliest or as soon as possible is selected.

The controller30writes the selected write data to the LBA area110(S303). Then, the controller30invalidates the write data writing of which to the LBA area110in the buffer area271has been completed and the copy data of the write data in the media cache area120(S305). Then, the controller30executes the process of S301again.

Invalidation is making it unusable. The invalidation may be erasing. Hereinafter, the state of data that has not been invalidated is referred to as valid.

In the example illustrated inFIG.9, writing of the temporarily stored data to the LBA area110is executed when the magnetic disk device1is in the idle state. Conditions under which writing of the temporarily stored data to the LBA area110is executed are not limited thereto. For example, writing of the temporarily stored data to the LBA area110may be executed when the buffer area271is full of valid temporarily stored data.

By the operations illustrated inFIGS.7and9, copy data corresponding to the original write data is stored in the MC block during a period from when the original write data is stored in the buffer area271to when the original write data is written to the LBA area110.

FIG.10is a flowchart illustrating an example of an operation of incrementing the ATI counter according to the embodiment.

The controller30executes writing on one MC block (S401). Specifically, the process of S40corresponds to the process of S105illustrated inFIG.7. The MC block in which the copy data is written by the process of S401is referred to as a first target MC block.

Following the process of S401, the controller30increments the ATI counter of the MC block storing the valid copy data by “1” among the MC blocks adjacent to the first target MC block (S402). The operation of incrementing the ATI counter ends.

The series of operations illustrated inFIG.10is executed every time the process of S105illustrated inFIG.7is executed.

FIG.11is a flowchart illustrating an example of an operation of resetting the ATI counter according to the embodiment.

According to the series of operations illustrated inFIG.9, the copy data in each MC block is invalidated in units of write commands. Therefore, valid copy data and invalid copy data may be mixed in one MC block.

When invalidation of all the copy data stored in one MC block is completed by executing the series of operations illustrated inFIG.9one or more times (S501), the controller30resets the ATI counter of the MC block to “0” (S502). Then, the operation of resetting the ATI counter ends.

FIG.12is a flowchart illustrating an example of an operation of unwritable setting based on the ATI counter according to the embodiment.

The controller30determines whether there is an MC block of which an ATI estimation value reaches the first threshold value in any of the media cache areas120(S601). The MC block of which the ATI estimation value reaches the first threshold value is referred to as a second target MC block.

When there is the second target MC block (S601: Yes), the controller30sets the second target MC block and the MC blocks adjacent to the second target MC block to be unwritable (S602). Then, the controller30cancels the setting of other MC blocks (More precisely, all MC blocks except the second target MC block and except MC blocks adjacent to the second target MC block) to be unwritable (S603). When there is no other MC block set to be unwritable, the controller30executes nothing in the process of S603.

When there is no second target MC block (S601: No), the controller30skips the process of S602.

After the process of S603, the controller30executes the process of S601again.

FIGS.13A to13Care schematic diagrams for describing a specific example of the operation illustrated inFIGS.10to12. Each ofFIG.13A to13Cillustrates a sub-table51related to a certain media cache area120among the sub-tables51included in the ATI management table50.

Note that, in the description of the example illustrated inFIGS.13A to13C, the first threshold value is assumed to be “10”.

According to the sub-table51illustrated inFIG.13A, the MC blocks #0 to #3, #5, and #6 are in an empty state, and accordingly, the ATI counter for each of the MC blocks #0 to #3, #5, and #6 is “0”. Valid copy data is stored in the MC block #4, and the ATI counter for the MC block #4 is “9”. Valid copy data is also stored in the MC block #7, and the ATI counter for the MC block #7 is “5”.

“Empty” means that valid copy data is not stored.

When the ATI counter for each MC block is in the state illustrated inFIG.13A, the controller30writes the copy data to the MC block #3 (S701). Then, as illustrated inFIG.13B, the controller30increments the ATI counter for the MC block #4 that is an MC block storing valid copy data among the MC block #2 and the MC block #4 that are MC blocks adjacent to the MC block #3 by “1”. As a result, the difference (which is the ATI estimation value) of the ATI counter for the MC block #4 from “0”, that is the minimum value of the ATI counters recorded in the sub-table51, reaches “10” that is the first threshold value. Therefore, the controller30sets the MC block #4 and the MC blocks #3 and #5 adjacent to the MC block #4 to be unwritable (S702).

That is, in order to prevent further accumulation of the influence of ATI on the MC block #4, writing to the

MC block #5 is prohibited even though the MC block #5 is empty.

Subsequently, as illustrated inFIG.13C, when the controller30completes the invalidation of all the copy data in the MC block #4, the controller30resets the ATI counter for the MC block #4 to “0”, and cancels setting of the MC block #4 and the MC blocks #3 and #5 adjacent to the MC block #4 to be unwritable (S703). As a result, the controller30can write data to the empty MC blocks #4 and #5.

Note that, in the above description, it is described that the controller30writes the copy of the unprotected temporarily stored data to the media cache area120for each first amount. The amount of copy data written to the media cache area120at one time is not limited thereto.

For example, the configuration may be such that the PLP saving area281is not provided in the FROM28, and the controller30copies all temporarily stored data stored in the buffer area271to the media cache area120at an any timing.

In addition, an example of an ATI estimation value is not limited to a difference of an ATI counter of an MC block from the minimum value of ATI counters among a media cache area120to which the MC block belongs to.

In an example, the controller30may treat the ATI counter itself as an ATI estimation value. In another example, a difference of an ATI counter of an MC block from the minimum value of ATI counters among all the media cache areas120may be treated as an ATI estimation value.

As described above, according to the embodiment, the controller30estimates the degree of influence of ATI for each of the plurality of MC blocks, and sets the MC block (referred to as a first MC block) in which the degree of influence of ATI reaches the first threshold value among the plurality of MC blocks and the two MC blocks adjacent to the first MC block among the plurality of MC blocks to be unwritable. The controller30selects one of one or more MC blocks which are not set to be unwritable and have free space among the plurality of blocks, and stores a copy of write data in the buffer area271in the selected one block at least for a period until the write data is written to the LBA area110.

Therefore, it is possible to prevent data reading from becoming difficult due to the influence of ATI without requiring execution of an ATI refresh operation in any media cache area120. Since the ATI refresh operation is not executed in any of the media cache areas120, deterioration of the write performance of the magnetic disk device1is suppressed.

In addition, according to the embodiment, the magnetic disk device1copies the temporarily stored data that has not yet been copied to the media cache area120to the selected MC block every time the amount of the temporarily stored data that has not yet been copied to the media cache area120among the temporarily stored data received in the buffer area271reaches the first amount. When the power supply interruption occurs, the controller30saves temporarily stored data that has not yet been copied to the media cache area120to the PLP saving area281. When the power supply is started after the power supply interruption, the controller30restores the temporarily stored data in the buffer area271based on the copy data stored in the media cache area120and the temporarily stored data saved in the PLP saving area281.

Therefore, the write data in the buffer area271is prevented from being lost from the magnetic disk device1due to the power supply interruption.

In addition, according to the embodiment, the controller30manages a group of the ATI counters for each MC block. When the copy data is written to a certain MC block (referred to as a second MC block), the controller30increments an ATI counter for an MC block storing valid copy data, that is, a copy of temporarily stored data writing of which to the LBA area110has not yet been completed, among two MC blocks adjacent to the second MC block. The controller30resets an ATI counter for an MC block in which the invalidation of all the stored copy data is completed. The controller30estimates the degree of influence of ATI for each MC block based on its ATI counter. Specifically, the controller30identifies the MC block in which the difference of the ATI counter from the minimum value reaches the first threshold value as the first MC block.

Therefore, the controller30can stop accumulation of the influence of ATI received by the first MC block before it is difficult to read the copy data stored in the first MC block.

Note that, as described above, the controller30may use ATI counters as estimation values of the degree of influence of ATI. Furthermore, the controller30may use a difference of an ATI counter of an MC block from the minimum value of ATI counters among all the media cache areas120to which the MC block belongs to as an estimation value of the degree of influence of ATI. That is, the controller30can estimate the degree of influence of ATI based on the ATI counter.