Stacked metal oxide semiconductor (MOS) and metal oxide metal (MOM) capacitor architecture

A device includes a first stacked capacitor comprising a first MOS capacitance and a first MOM capacitance, the first MOS capacitance coupled to a first node, the first node configured to receive a first bias voltage, and a second stacked capacitor comprising a second MOS capacitance and a second MOM capacitance, the second MOS capacitance coupled to the first node.

BACKGROUND

Field

The present disclosure relates generally to electronics, and more specifically to the operation and design of stacked metal oxide semiconductor (MOS) and metal oxide metal (MOM) capacitors.

Background

Metal oxide semiconductor (MOS) capacitors and metal oxide metal (MOM) capacitors are used in many applications, such as in analog filters. A structure referred to as a stacked capacitor (stackcap) can comprise both MOS and MOM capacitors.

MOS capacitors, also may be referred to as metal oxide semiconductor varactors (MOSVARS) of either N- or P-type, having a capacitance which varies with applied voltage across their terminals. MOM capacitors comprise a dielectric, oxide, or insulating layer between two or more metal layers and include, but are not limited to, flux capacitors, fractal capacitors, parallel-plate capacitors, and woven capacitors.

MOS capacitors are generally more area efficient than MOM capacitors and therefore can be used in place of or in conjunction with MOM capacitors in a stackcap architecture to save circuit area. For example, the ratio of capacitance to area can be more than four times greater for a MOS capacitor than for a MOM capacitor. Unfortunately, MOS capacitors may exhibit non-linearity caused by capacitance variation with respect to voltage, the non-linearities of MOS capacitors being significantly greater than non-linearities exhibited by MOM capacitors.

Certain foundries and processes may allow vertical or other means of integration of both a MOS capacitor and MOM capacitor, allowing fabrication of the stackcap. A stackcap generally has a very dense architecture as it combines the area density of both the MOM capacitor and MOS capacitor and accordingly consumes a small amount of circuit area. Unfortunately, when used in high-density circuit applications, use of the stackcap may lead to non-linearities and may prevent a stackcap-only capacitor implementation, and may lead to the need for, or substitution of, additional MOM capacitance to achieve better linearity.

Therefore, a stacked MOS/MOM capacitance with improved linearity that minimizes circuit area is desirable.

DETAILED DESCRIPTION

The terms “MOSCAP” and “MOS capacitance” refer to a capacitance formed using metal oxide semiconductor (MOS) technology.

The terms “MOM,” “MOMCAP” and “MOM capacitance” refer to a capacitance formed using metal oxide metal (MOM) technology.

The terms “stacked capacitor” and “stackcap” refer to a MOM capacitance vertically integrated with a MOS capacitance on a wafer, laminate, or other multi-layer circuit structure.

FIG. 1illustrates a block diagram of a design of a wireless communication device100in which exemplary the techniques of the present disclosure may be implemented.FIG. 1shows an example transceiver design. In general, the conditioning of the signals in a transmitter130and a receiver150may be performed by one or more stages of amplifier, filter, upconverter, downconverter, etc. These circuit blocks may be arranged differently from the configuration shown inFIG. 1. Furthermore, other circuit blocks not shown inFIG. 1may also be used to condition the signals in the transmitter130and receiver150. Unless otherwise noted, any signal inFIG. 1, or any other figure in the drawings, may be either single-ended or differential. Some circuit blocks inFIG. 1may also be omitted.

In the exemplary design shown inFIG. 1, wireless device100includes a transceiver120and a data processor110. The data processor110may include a memory (not shown) to store data and program codes. Transceiver120includes a transmitter130and a receiver150that support bi-directional communication. In general, wireless device100may include any number of transmitters and/or receivers for any number of communication systems and frequency bands. All or a portion of transceiver120may be implemented on one or more analog integrated circuits (ICs), RF ICs (RFICs), mixed-signal ICs, etc.

A transmitter130or a receiver150may be implemented with a super-heterodyne architecture or a direct-conversion architecture. In the super-heterodyne architecture, a signal is frequency-converted between radio frequency (RF) and baseband in multiple stages, e.g., from RF to an intermediate frequency (IF) in one stage, and then from IF to baseband in another stage for a receiver. In the direct-conversion architecture, a signal is frequency converted between RF and baseband in one stage. The super-heterodyne and direct-conversion architectures may use different circuit blocks and/or have different requirements. In the design shown inFIG. 1, transmitter130and receiver150are implemented with the direct-conversion architecture.

In the transmit path, data processor110processes data to be transmitted and provides I and Q analog output signals to transmitter130. In the exemplary embodiment shown, the data processor110includes digital-to-analog-converters (DAC's)114aand114bfor converting digital signals generated by the data processor110into the I and Q analog output signals, e.g., I and Q output currents, for further processing.

Within transmitter130, baseband filters132aand132bfilter the I and Q analog output signals, respectively, to remove undesired images caused by the prior digital-to-analog conversion. Amplifiers (Amp)134aand134bamplify the signals from baseband filters132aand132b, respectively, and provide I and Q baseband signals. An upconverter140upconverts the I and Q baseband signals with I and Q transmit (TX) local oscillator (LO) signals from a TX LO signal generator190and provides an upconverted signal. A filter142filters the upconverted signal to remove undesired images caused by the frequency upconversion as well as noise in a receive frequency band. A power amplifier (PA)144amplifies the signal from filter142to obtain the desired output power level and provides a transmit RF signal. The transmit RF signal is routed through a duplexer or switch146and transmitted via an antenna148.

In the receive path, antenna148receives signals transmitted by base stations and provides a received RF signal, which is routed through duplexer or switch146and provided to a low noise amplifier (LNA)152. The duplexer146is designed to operate with a specific RX-to-TX duplexer frequency separation, such that RX signals are isolated from TX signals. The received RF signal is amplified by LNA152and filtered by a filter154to obtain a desired RF input signal. Downconversion mixers161aand161bmix the output of filter154with I and Q receive (RX) LO signals (i.e., LO_I and LO_Q) from an RX LO signal generator180to generate I and Q baseband signals. The I and Q baseband signals are amplified by amplifiers162aand162band further filtered by base-band filters164aand164bto obtain I and Q analog input signals, which are provided to data processor110. In the exemplary embodiment shown, the data processor110includes analog-to-digital-converters (ADC's)116aand116bfor converting the analog input signals into digital signals to be further processed by the data processor110.

InFIG. 1, TX LO signal generator190generates the I and Q TX LO signals used for frequency upconversion, while RX LO signal generator180generates the I and Q RX LO signals used for frequency downconversion. Each LO signal is a periodic signal with a particular fundamental frequency. A PLL192receives timing information from data processor110and generates a control signal used to adjust the frequency and/or phase of the TX LO signals from LO signal generator190. Similarly, a PLL182receives timing information from data processor110and generates a control signal used to adjust the frequency and/or phase of the RX LO signals from LO signal generator180.

The transceiver120may be coupled to data processor110via a plurality of electrical interface pins (not necessarily explicitly shown inFIG. 1). For example, the outputs of base-band filters164a,164b, which may be differential in certain implementations, may be coupled to the inputs of ADC's116a,116bthrough a plurality of interface pins, e.g., two pins for each of filters164a,164b.

In state-of-the-art wireless devices, it would be desirable to reduce the package size of integrated circuits as well as board size to provide cost-effective solutions. Accordingly, it would be desirable to reduce the chip area of the capacitors used in the baseband filters and other analog low-pass filters in the transceiver120to reduce the overall package and die size, especially for IC's supporting multiple transmitter or receiver paths in a single die.

FIG. 2is a schematic diagram illustrating an exemplary embodiment of a baseband filter that can be implemented using a stacked capacitor architecture. The BBF210is a generic representation of one or more of the BBF instances shown inFIG. 1. The BBF210can comprise a filter element215configured to receive a baseband input signal (BBF_in) over connection212and provide a filtered baseband output signal (BBF_out) over connection214. The filter element215can comprise an active or a passive filter circuit, such as, for example of an active filter circuit, an operational amplifier with feedback; and, for example of a passive filter circuit, only a resistive/capacitive network. A feedback network216is coupled between the output of the filter element215on connection214and the input to the filter element215on connection212. The feedback network216can be implemented using any combination of capacitive, resistive, and/or inductive elements, and is illustrated herein using an adjustable resistance217and an adjustable capacitance218for exemplary purposes only. Exemplary embodiments of the stackcap architectures described herein can be used to implement the adjustable capacitance218.

FIG. 3Ais a graphical illustration300showing the capacitance of a stackcap relative to voltage. In an exemplary embodiment, a stackcap may include one or more MOS capacitances implemented using one or more MOS varactors. A MOS varactor is a particular type of a MOS capacitance and generally comprises a MOS device with a first contact connected to the gate of the MOS device and a second set of contacts connecting the drain and source of the MOS device together, forming a MOS capacitance between the first and second contacts. In an exemplary embodiment, a MOS varactor operating in accumulation-mode is shown inFIG. 3E. Alternatively, a MOS varactor can be implemented using a PMOS capacitor structure in inversion-mode. A MOS varactor is known to those having ordinary skill in the art.

The horizontal axis302represents voltage and the vertical axis304represents capacitance. At 0V, the operation of a stackcap is quite non-linear. In the example shown inFIG. 3A, when unbiased, the region303shows the performance range of the stackcap with 0V bias. In the example shown inFIG. 3A, the region305shows the performance range of the stackcap with an approximate 1V bias voltage. As shown, the region305illustrates that the stackcap behaves more linearly with a bias voltage than it does with zero bias. In an exemplary embodiment, the capacitance and voltage performance shown inFIG. 3Arepresents an accumulation mode MOS varactor.

FIG. 3Bis a schematic diagram310illustrating an exemplary embodiment of a stacked capacitor. In an exemplary embodiment, a MOS capacitor312is coupled in parallel with a MOM capacitor314, which together form a stackcap315. An input voltage, Vin, is provided over connection318and an output voltage, Vout, is provided over connection319. Input and output connections are labeled in terms of voltage to demonstrate voltage dependence, although in a practical application, inputs and outputs could be either in terms of voltage or current.

FIG. 3Cis a diagram illustrating a two-dimensional plan view of a stackcap315. The stackcap315comprises a typical MOS varactor implementation of a MOS capacitor312having a source322and a drain324that are connected together through vias or other interconnects at a node325to one side of an interdigitated finger MOM capacitor314. The node325corresponds to connection318inFIG. 3B. The gate326is connected through vias or other interconnects at a node327to the other side of the interdigitated finger MOM capacitor314. The node327corresponds to connection319inFIG. 3B.

FIG. 3Dis a two-dimensional side view330showing an exemplary embodiment of the stackcap ofFIGS. 3B and 3C. InFIG. 3D, an integrated circuit structure332is shown having a plurality of layers. In an embodiment, the integrated circuit structure332may comprise a silicon die or other multi-layer structure or wafer on which circuit elements can be fabricated. The integrated circuit structure332comprises many different power, ground, circuit, metal, dielectric, and other layers, with metal layers m1-mx334and an active layer336shown for illustrative purposes only. More or fewer than four metal layers334can be included, and the active layer336may comprise one or more material layers, where the “x” in the designation mx refers to an integer number.

In an exemplary embodiment, the MOS capacitance312is fabricated in the active layers336and the MOM capacitance314is fabricated in one or more of the metal layers334, such that the stackcap315is formed with the MOM capacitance314located above the MOS capacitance312.

FIG. 3Eis a schematic diagram illustrating an exemplary embodiment of a MOS varactor. In an exemplary embodiment, the MOS device350is an accumulation-mode MOS varactor having a gate326, drain324, and source322. The drain324and source322of the MOS device350are connected together via the node356such that the MOS capacitance is formed between the two terminals352and356.

FIG. 4Ais a graphical illustration400showing the capacitance of a stackcap in accordance with exemplary techniques of the present disclosure. The horizontal axis402represents voltage and the vertical axis404represents capacitance. The trace409represents the performance of the stackcap shown inFIG. 3A. The trace403shows the performance of an exemplary embodiment of a stackcap. As shown inFIG. 4A, the trace403shows a significantly more linear response from −1V to 1V compared to the trace409.

FIG. 4Bis a schematic diagram410illustrating an exemplary embodiment of a stacked capacitor. A first stackcap415comprises a MOS capacitance412and a MOM capacitance414. A second stackcap425comprises a MOS capacitance422and a MOM capacitance424. In an exemplary embodiment, the MOS capacitance412and the MOS capacitance422are implemented as MOS varactors. The first stackcap415is coupled in series with the second stackcap425in what is referred to as a back-to-back configuration at a common node413. In an exemplary embodiment, the MOM capacitances414and424are connected in series and are connected to the node413.

The term back-to-back is intended to imply that the first stackcap415and the second stackcap425are symmetrically arranged about the common node413such that the drain and source contacts of the MOS varactor used to implement the MOS capacitance412and the MOS varactor used to implement the MOS capacitance422are coupled to the node413, while the gate contacts of the MOS varactor used to implement the capacitance412and the MOS varactor used to implement the MOS capacitance422are connected to Vin or Vout. In an exemplary embodiment, the gate contact of the MOS varactor used to implement the MOS capacitance412is coupled to Vin and the gate contact of the MOS varactor used to implement the MOS capacitance422is coupled to Vout.

A resistance sufficiently large to not disturb the operation of the stackcap415and the stackcap425in its application, such as in the baseband filter210(FIG. 2), Rb416, is coupled between the node413and a bias voltage Vb at connection417. It is desirable that the voltage difference between Vin on connection418or Vout on connection419and Vb be non-zero to ensure that a bias voltage is applied to both the first stackcap415and the second stackcap425to place the first stackcap415and the second stackcap425in a more linear region similar to the region405and similar to the trace403(FIG. 4A).

FIG. 4Cis a schematic diagram430showing an exemplary embodiment of the stacked capacitor ofFIG. 4B. InFIG. 4C, an integrated circuit structure432is shown having a plurality of layers. In an embodiment, the integrated circuit structure432may comprise a silicon die or other multi-layer structure or wafer on which circuit elements can be fabricated. The integrated circuit structure432comprises many different power, ground, circuit, metal, dielectric, and other layers, with metal layers m1-mx434and an active layer436shown for illustrative purposes only. More or fewer than four metal layers434can be included, and the active layer436may comprise one or more material layers, where the “x” in the designation mx refers to an integer number.

In an exemplary embodiment, the MOS capacitances412and422are fabricated in the active layer436and the MOM capacitances414and424are fabricated in one or more of the metal layers434. In this exemplary embodiment, the MOS capacitances are coupled in series in what is referred to as a “back-to-back” orientation, in which either the gates or sources/drains of the MOS capacitances are connected to a common point (such as the node413described above). In this exemplary embodiment, the MOM capacitances are coupled in series in the back-to-back configuration.

In an exemplary embodiment, MOS capacitors412and422can be used alone (without MOM capacitors414and424) in place of the stackcap ofFIG. 4BandFIG. 4Cto provide a linearized MOS capacitor.

FIG. 5Ais a graphical illustration500showing the capacitance of a stackcap in accordance with exemplary techniques of the present disclosure. The horizontal axis502represents voltage and the vertical axis504represents capacitance. The trace509represents the performance of the stackcap shown inFIG. 3A. The trace503represents the performance of the stackcap shown inFIG. 4A. The trace508shows the performance of another exemplary embodiment of a stackcap. As shown inFIG. 5A, the trace508shows an improvement in capacitance compared to the trace503.

FIG. 5Bis a schematic diagram510illustrating an alternative exemplary embodiment of a stacked capacitor architecture. A first stackcap515comprises a MOS capacitance512and a MOM capacitance514. A second stackcap525comprises a MOS capacitance522and a MOM capacitance524. In an exemplary embodiment, the MOS capacitance412and the MOS capacitance422are implemented as MOS varactors. The first stackcap515is coupled in series with the second stackcap525in what is referred to as a back-to-back configuration at a common node513, as described herein.

The first MOM capacitance514and the second MOM capacitance524are coupled in parallel with each other and in parallel with the series coupled first MOS capacitance512and second MOS capacitance522.

A resistance sufficiently large to not disturb the operation of the stackcap515and the stackcap525in its application, such as in the baseband filter210(FIG. 2), Rb516, is coupled between the node513and a bias voltage Vb to ensure that a non-zero bias voltage, such as Vin-Vb or Vout-Vb, is applied to both the first MOS capacitance512and the second MOS capacitance522at node513such that their region of operation is similar to the region505inFIG. 5A.

FIG. 5Cis a schematic diagram530showing an exemplary embodiment of the stackcaps ofFIG. 5B. InFIG. 5C, an integrated circuit structure532is shown having a plurality of layers. In an embodiment, the integrated circuit structure532may comprise a silicon die or other multi-layer structure or wafer on which circuit elements can be fabricated. The integrated circuit structure532comprises many different power, ground, circuit, metal, dielectric, and other layers, with metal layers534and an active layer536shown for illustrative purposes only. More or fewer than four metal layers534can be included, and the active layer536may comprise one or more material layers.

In an exemplary embodiment, the MOS capacitances512and522are fabricated in the active layer536and the MOM capacitances514and524are fabricated in one or more of the four metal layers534. In this exemplary embodiment, the MOS capacitances512and522are coupled in series in what is referred to as a “back-to-back” orientation, in which either the gates or the sources/drains of the MOS capacitances are connected to a common point (such as the node513described above). In this exemplary embodiment, the MOM capacitances514and524are coupled in parallel.

FIG. 6Ais a graphical illustration600showing the individual and sum capacitance over voltage for a stackcap capacitive circuit in accordance with exemplary techniques of the present disclosure. The horizontal axis602represents a voltage drop across a stackcap capacitive circuit and the vertical axis604represents capacitance. The trace603represents a first bias voltage, Vb1, applied to a first stackcap circuit and the trace605represents a second bias voltage, Vb2, applied to a second stackcap circuit. In an exemplary embodiment, the difference in bias voltages Vin-Vb1is opposite in polarity to the difference in bias voltage Vin-Vb2; likewise, Vout-Vb1is opposite in polarity to Vout-Vb2.

FIG. 6Bis a graphical illustration600showing four examples of capacitance over a range of voltage drop |ΔV| for a capacitive circuit at four different bias voltage points. In an exemplary embodiment, |ΔV|=|Vin−Vb1|=|Vin−Vb2|. The trace608ashows capacitance with a bias voltage |ΔV| of 0.75V; the trace608bshows capacitance with a bias voltage |ΔV| of 0.5V; the trace608cshows capacitance with a bias voltage |ΔV| of 0.25V; and the trace608dshows capacitance with a bias voltage |ΔV| of 0V. The choice of bias point affects both the linearity of the overall capacitive circuit as well as the effective capacitance.

FIG. 6Cis a schematic diagram illustrating another exemplary embodiment of a stacked capacitor architecture. In an exemplary embodiment, the stacked capacitor architecture shown inFIG. 6Ccomprises an exemplary embodiment of a capacitive circuit610. The capacitive circuit610comprises a first stackcap unit cell617comprising stackcap615and stackcap625. The stackcap615comprises a MOS capacitance612and a MOM capacitance614. The stackcap625comprises a MOS capacitance622and a MOM capacitance624. The MOS capacitance612is coupled in series to the MOS capacitance622in what is referred to as a back-to-back configuration at a common node613. The MOM capacitance614and the MOM capacitance624are coupled in parallel with each other and in parallel with the series coupled MOS capacitance612and MOS capacitance622. Alternatively, the MOM capacitance614and the MOM capacitance624can be coupled in series in a configuration similar to the configuration shown inFIG. 4B. A relatively large resistance, Rb1616, is coupled between the node613and a bias voltage Vb1to ensure that a non-zero bias voltage, such as Vin-Vb1or Vout-Vb1, is applied to both the MOS capacitance612and the MOS capacitance622at node613such that their region of operation is similar to the region505and the trace508inFIG. 5A.

The capacitive circuit610also comprises a second stackcap unit cell647comprising stackcap645and stackcap655. The stackcap645comprises a MOS capacitance642and a MOM capacitance644. The stackcap655comprises a MOS capacitance652and a MOM capacitance654. The MOS capacitance642is coupled in series to the MOS capacitance652in what is referred to as a back-to-back configuration at a common node643. However, the orientation of the MOS capacitances642and652with respect to the common node643are reversed with respect to the orientation of the MOS capacitances612and622with respect to the common node613. For example, the MOS capacitances642and652have their gate contacts coupled to the node643, whereas the MOS capacitances612and622have their source/drain contacts coupled to the node613.

The MOM capacitance644and the MOM capacitance654are coupled in parallel with each other and in parallel with the series coupled MOS capacitance642and MOS capacitance652. Alternatively, the MOM capacitance644and the MOM capacitance654can be coupled in series in a configuration similar to the configuration shown inFIG. 4B. A relatively large resistance, Rb2646, is coupled between the node643and a bias voltage Vb2to ensure that a non-zero bias voltage, such as Vin-Vb2or Vout-Vb2, is applied to both the MOS capacitance642and the MOS capacitance652at node643such that their region of operation is similar to the region505and the trace508inFIG. 5A.

A switch611can selectively enable usage of the MOS capacitances612and622; and can selectively enable usage of the MOM capacitances614and624in respective stackcaps615and625. Similarly, the switch611can selectively enable usage of the MOS capacitances642and652; and can selectively enable usage of the MOM capacitances644and654in respective stackcaps645and655. In an exemplary embodiment, the switch611can be controlled by a signal from the data processor110(FIG. 1). In an exemplary embodiment, the switch611may comprise one or more switches or switch networks that can independently control the MOS capacitances612and622and the MOM capacitances614and624in respective stackcaps615and625; and the MOS capacitances642and652, and the MOM capacitances644and654in respective stackcaps645and655to compensate for process, voltage, and temperature variations in the MOS capacitances and the MOM capacitances.

In an exemplary embodiment, the values of the MOS capacitance642and the MOS capacitance652in the second stackcap unit cell617can be different than the values of the MOS capacitances in the first stackcap unit cell617. In an exemplary embodiment, the resistance646can be the same or a different value than the resistances Rb1.

The stackcaps615and625are biased such that the MOS capacitances612and622are placed in a linear operating region such as region505shown inFIG. 5A. Because the polarity (Vin-Vb1, Vin-Vb2) and capacitor orientation is opposite, the capacitance of stackcap615can be represented by curve603inFIG. 6Awith increasing capacitance versus Vout-Vin, and stackcap625with opposite orientation can be represented by curve605inFIG. 6Awith decreasing capacitance versus Vout-Vin. The total capacitance of the unit cell617is linearized as a result of both the more linear bias points of stackcaps615and625and the increasing/decreasing capacitance versus Vout-Vin offsetting each other. The stackcaps645and655are similarly affected.

FIG. 7is a schematic diagram illustrating another exemplary embodiment of a stacked capacitor architecture. In an exemplary embodiment, the stacked capacitor architecture shown inFIG. 7comprises an exemplary embodiment of a capacitive circuit710. The capacitive circuit710may include the capacitive circuit610described above and may include additional stackcap capacitance branches to which different bias voltages can be applied. In an exemplary embodiment, the capacitive circuit710comprises a third stackcap unit cell717comprising stackcap715and stackcap725. The stackcap715comprises a MOS capacitance712and a MOM capacitance714. The stackcap725comprises a MOS capacitance722and a MOM capacitance724. The MOS capacitance712is coupled in series to the MOS capacitance722in what is referred to as a back-to-back configuration at a common node713. The orientation of the MOS capacitance712with respect to the common node713is reversed with respect to the orientation of the MOS capacitance612with respect to the common node613. For example, the MOS capacitance712has its gate contact coupled to the node713, whereas the MOS capacitance612has its source/drain contacts coupled to the node613.

The MOM capacitance714and the MOM capacitance724are coupled in parallel with each other and in parallel with the series coupled MOS capacitance712and MOS capacitance722. Alternatively, the MOM capacitance714and the MOM capacitance724can be coupled in series in a configuration similar to the configuration shown inFIG. 4B. A relatively large resistance, Rb3716, is coupled between the node713and a bias voltage Vb3to ensure that a non-zero bias voltage, such as Vin-Vb3or Vout-Vb3, is applied to both the MOS capacitance712and the MOS capacitance722at node713such that their region of operation is similar to the region505and the trace508inFIG. 5A.

In an exemplary embodiment, the values of the MOS capacitance712and the MOS capacitance722in the third stackcap unit cell717can be different than the values of the MOS capacitances in the first stackcap unit cell617and second stackcap unit cell647. In an exemplary embodiment, the resistance716can be the same or a different value than the resistances Rb1and Rb2, and the bias voltage Vb3can be the same or can be different than the bias voltages Vb1and Vb2, and, in an exemplary embodiment, can be negative while the voltages Vb1and Vb2are positive and negative, respectively.

The capacitive circuit710also comprises a fourth stackcap unit cell747comprising stackcap745and stackcap755. The stackcap745comprises a MOS capacitance742and a MOM capacitance744. The stackcap755comprises a MOS capacitance752and a MOM capacitance754. The MOS capacitance742is coupled in series to the MOS capacitance752in what is referred to as a back-to-back configuration at a common node743. The polarity of the MOS capacitance752with respect to the common node743is reversed with respect to the polarity of the MOS capacitance622with respect to the common node613. For example, the MOS capacitance752has its gate contact coupled to the node743, whereas the MOS capacitance622has its source/drain contacts coupled to the node613. Moreover, the gate contact of the MOS capacitance712and the source/drain contacts of the MOS capacitance722are coupled to the node713; and the source/drain contacts of the MOS capacitance742and the gate contact of the MOS capacitance752are coupled to the node743.

The MOM capacitance744and the MOM capacitance754are coupled in parallel with each other and in parallel with the series coupled MOS capacitance742and MOS capacitance752. Alternatively, the MOM capacitance744and the MOM capacitance754can be coupled in series in a configuration similar to the configuration shown inFIG. 4B. A relatively large resistance, Rb4746, is coupled between the node743and a bias voltage Vb4to ensure that a non-zero bias voltage, such as Vin-Vb4or Vout-Vb4, is applied to both the MOS capacitance742and the MOS capacitance752at node743such that their region of operation is similar to the region505and the trace508inFIG. 5A.

In an exemplary embodiment, the values of the MOS capacitance742and the MOS capacitance752in the fourth stackcap unit cell747can be different than the values of the MOS capacitances in the first stackcap unit cell617, second stackcap unit cell647, and third stackcap unit cell717. In an exemplary embodiment, the resistance746can be the same or a different value than the resistances Rb1, Rb2and Rb3, and the bias voltage Vb4can be the same or can be different than the bias voltages Vb1, Vb2and Vb3, and can be positive or negative.

FIG. 8is a schematic view illustrating an example of a switched capacitive circuit800. In an exemplary embodiment, the switched capacitive circuit800comprises a stackcap unit cell817. The stackcap unit cell817is similar to the stackcap unit cell617and comprises stackcap815and stackcap825, which are similar to the stackcaps615and625, respectively, ofFIG. 6. The stackcap unit cell817comprises a MOS capacitance unit cell862comprising the MOS capacitances of the stackcap815and the stackcap825, and a MOM capacitance unit cell864comprising the MOM capacitances of the stackcap815and stackcap825. Other details of the stackcap unit cell817are omitted for simplicity. In the exemplary embodiment ofFIG. 8, the MOS capacitance unit cell862comprises a first switch871coupled to a Vin connection818and the MOM capacitance unit cell864comprises a second switch873coupled to the Vin connection818. The output, Vout, of the MOS capacitance unit cell862and the MOM capacitance unit cell864is provided over connection819. Independently switching the MOS capacitance unit cell862and the MOM capacitance unit cell864allows independent selection of none, either, or both of the MOS and MOM capacitors in the stackcap unit cell817.

In an exemplary embodiment, the MOS capacitance unit cell862comprises a first characteristic capacitance, CMOS. A second MOS capacitance unit cell872comprises a second characteristic capacitance, 2CMOS; and a third MOS capacitance unit cell882comprises a third characteristic capacitance, 4CMOS. The second MOS capacitance unit cell872and the third MOS capacitance unit cell882are similar to the MOS capacitance unit cell862, but include progressively more MOS capacitance. For example, the second MOS capacitance unit cell872can be configured to provide two times the MOS capacitance as the MOS capacitance unit cell862and the third MOS capacitance unit cell882can be configured to provide four times the MOS capacitance as the MOS capacitance unit cell862. Moreover, additional MOS capacitance unit cells can be added to provide any amount of additional MOS capacitance.

In an exemplary embodiment, the switch871can be implemented in a variety of ways using a variety of switching technologies, and, in an exemplary embodiment, can be implemented as a one or more pole, and a one or more throw switch, depending on the implementation. In an exemplary embodiment, each of the MOS capacitance unit cells872and882can be switched similar to the MOS capacitance unit cell862. In an exemplary embodiment, a multiple bit control signal “bMOS” having a number of control bits equal to the number of MOS capacitance unit cells, which in this example comprises bMOS, bMOS1and bMOS2, can be provided by, for example, the data processor110ofFIG. 1, such that the total MOS capacitance is the result of a digitally controlled binary weighted MOS capacitor bank892comprising, in an exemplary embodiment, the MOS capacitance unit cell862, the second MOS capacitance unit cell872, and the third MOS capacitance unit cell882. Alternatively, any arbitrary weighting can be used to control the amount of MOS capacitance.

In an exemplary embodiment, the MOM capacitance unit cell864comprises a first characteristic capacitance, CMOM. A second MOM capacitance unit cell874comprises a second characteristic capacitance, 2CMOM; and a third MOM capacitance unit cell884comprises a third characteristic capacitance, 4CMOM. The second MOM capacitance unit cell874and the third MOM capacitance unit cell884are similar to the MOM capacitance unit cell864, but include progressively more MOM capacitance. For example, the second MOM capacitance unit cell874can be configured to provide two times the MOM capacitance as the MOM capacitance unit cell864and the third MOM capacitance unit cell884can be configured to provide four times the MOM capacitance as the MOM capacitance unit cell864. Moreover, additional MOM capacitance unit cells can be added to provide any amount of additional MOM capacitance, and the number of MOM capacitance unit cells need not be the same as the number of MOS capacitance unit cells.

In an exemplary embodiment, the switch873can be implemented in a variety of ways using a variety of switching technologies, and, in an exemplary embodiment, can be implemented as a one or more pole, and a one or more throw switch, depending on the implementation. In an exemplary embodiment, each of the MOM capacitance unit cells874and884can be switched similar to the MOM capacitance unit cell864. In an exemplary embodiment, a multiple bit control signal “bMOM” having a number of control bits equal to the number of MOM capacitance unit cells, which in this example comprises bMOM0, bMOM1and bMOM2, can be provided by, for example, the data processor110ofFIG. 1, such that the total MOM capacitance is the result of a digitally controlled binary weighted MOM capacitor bank894comprising, in an exemplary embodiment, the MOM capacitance unit cell864, the second MOM capacitance unit cell874, and the third MOM capacitance unit cell884. In the same fashion, the MOS capacitor back can be controlled by bMOS0, bMOS1, bMOS2, for the binary-weighted MOS capacitor bank892. Alternatively, any arbitrary weighting can be used for the MOM894and MOS892capacitor banks.

By independently selecting some, all, or none of the MOM and MOS unit cells864,862and their weighted replicas874,884,872,882, a wide range of capacitance values can be selected by the digital controls bMOSand bMOM. For example, depending on the desired capacitance value and linearity, only MOM capacitors could be selected to attain a smaller total capacitance value with the highest linearity, or both MOM and MOS capacitors could be selected to attain the highest possible capacitance.

Process, voltage, and temperature variations can result in independent variations in capacitance value for the MOS and MOM capacitors as their physical implementations are different. In order to adjust the total capacitance to a target value, in an exemplary embodiment the MOM and MOS capacitors can be selected for the signal path independently of each other based on the digital controls provided by, for example, the data processor110ofFIG. 1. For example, if the effective capacitance after fabrication is less than the desired target value, the digital controls bMOMand bMOScan select more capacitance for the signal path to adjust the effective capacitance to the target value. Any of the combinations of selecting the amount of MOM capacitance, MOS capacitance, or a combination of MOS and MOM capacitance can be used to correct for process, voltage, or temperature variations.

FIG. 9is a block diagram showing an exemplary embodiment of an implementation of the switched capacitive circuit ofFIG. 8in a feedback network. In an exemplary embodiment, the feedback network216can be coupled between the output of the filter element215on connection214and the input to the filter element215on connection212(FIG. 2). The feedback network216can be implemented using any combination of capacitive, resistive and/or inductive elements, and is illustrated herein using an adjustable resistance217and an adjustable capacitance218. The adjustable capacitance218may comprise one or more instances of the switched capacitive circuit800with any of the possible stackcap configurations310(FIG. 3B),410(FIG. 4B),510(FIG. 5B),610(FIG. 6B), or710(FIG. 7) in any orientation. The adjustable capacitance218can be used to tune a RC pole such as the feedback network218inFIG. 2to a variety of different 3 dB bandwidths using a combination of MOM and MOS capacitors, and can be optimized for linearity or capacitance value by selecting either MOM or MOS or any combination thereof.

FIG. 10is a flow chart showing an exemplary embodiment of a method for biasing MOS capacitances in a stacked capacitor architecture.

In block1002, MOS capacitances in a stacked capacitor architecture are connected to a common node.

In block1004, a bias voltage is applied to the common node.

In block1006, the MOS capacitances are biased to operate in a linear region.

Exemplary embodiments of the architecture implement back-to-back MOS capacitances in a configuration which allows the MOS capacitances to be biased via a resistor without disturbing signal path performance.

In an exemplary embodiment, two MOM capacitances in parallel with the MOS capacitances form a stackcap and provide the maximum amount of capacitance from the MOM cap.

In an exemplary embodiment, biasing the MOS capacitances at a voltage other than zero-bias, improves the linearity and the capacitance density of the MOS capacitances.

In an exemplary embodiment, the MOM capacitances can be controlled independently from the MOS capacitances to provide adjustments for RC tuning or can be implemented independently from the MOS capacitances for improved linearity in modes having higher bandwidth or requiring less capacitance.

The stacked MOS and MOM capacitance architecture described herein may be implemented on one or more ICs, analog ICs, RFICs, mixed-signal ICs, ASICs, printed circuit boards (PCBs), electronic devices, etc. The stacked MOS and MOM capacitance architecture may also be fabricated with various IC process technologies such as complementary metal oxide semiconductor (CMOS), N-channel MOS (NMOS), P-channel MOS (PMOS), bipolar junction transistor (BJT), bipolar-CMOS (BiCMOS), silicon germanium (SiGe), gallium arsenide (GaAs), heterojunction bipolar transistors (HBTs), high electron mobility transistors (HEMTs), silicon-on-insulator (SOI), etc.

An apparatus implementing the stacked MOS and MOM capacitance architecture described herein may be a stand-alone device or may be part of a larger device. A device may be (i) a stand-alone IC, (ii) a set of one or more ICs that may include memory ICs for storing data and/or instructions, (iii) an RFIC such as an RF receiver (RFR) or an RF transmitter/receiver (RTR), (iv) an ASIC such as a mobile station modem (MSM), (v) a module that may be embedded within other devices, (vi) a receiver, cellular phone, wireless device, handset, or mobile unit, (vii) etc.