Semiconductor devices having highly integrated sheet and wire patterns therein

A semiconductor device includes a semiconductor substrate having first and second regions therein, a first lower semiconductor pattern, which protrudes from the semiconductor substrate in the first region and extends in a first direction across the semiconductor substrate, and a first gate electrode, which extends across the first lower semiconductor pattern and the semiconductor substrate in a second direction. A plurality of semiconductor sheet patterns are provided, which are spaced apart from each other in a third direction to thereby define a vertical stack of semiconductor sheet patterns, on the first lower semiconductor pattern. A first gate insulating film is provided, which separates the plurality of semiconductor sheet patterns from the first gate electrode. A second lower semiconductor pattern is provided, which protrudes from the semiconductor substrate in the second region. A plurality of wire patterns are provided, which are spaced apart from each other on the second lower semiconductor pattern. A second gate insulating film is wrapped around each of the plurality of wire patterns.

REFERENCE TO PRIORITY APPLICATION

This application claims priority under 35 U.S.C. 119 to Korean Patent Application No. 10-2021-0075786, filed Jun. 11, 2021, the disclosure of which is hereby incorporated herein by reference.

BACKGROUND

The present disclosure relates to semiconductor devices and, more particularly, to highly integrated semiconductor devices with vertically integrated components therein.

As one of many scaling technologies for increasing density of a semiconductor device, a multi gate transistor in which a fin or nanowire-shaped multi-channel active pattern (or a silicon body) is formed on a substrate and a gate is formed on a surface of the multi-channel active pattern, has been proposed. Since such a multi gate transistor utilizes three-dimensional channels, scaling is relatively easily performed. Moreover, even if a gate length of the multi gate transistor is not increased, the current control capability may be improved. The SCE (short channel effect), in which potential of a channel region is influenced by a drain voltage, may also be effectively suppressed. Unfortunately, as a pitch size of a semiconductor device decreases, there is an increasing need for a research for securing a decrease in capacitance and electrical stability between contacts within the semiconductor device.

SUMMARY

Aspects of embodiments of the present invention provide semiconductor devices having improved device performance and reliability.

According to aspects of embodiments of the present invention, there is provided a semiconductor device including a substrate (e.g., semiconductor substrate) having first and second regions therein. A first lower semiconductor pattern is provided, which protrudes from the substrate (in the first region) and extends lengthwise in a first direction. A first gate electrode is provided, which extends in a second direction across the first lower semiconductor pattern. A plurality of sheet patterns are provided, which are spaced apart, in a vertical stack of sheet patterns, from the first lower semiconductor pattern in a third direction, which is orthogonal to the first direction and to the second direction. A first gate insulating film is provided, which wraps around each of the plurality of sheet patterns. A second lower semiconductor pattern is provided, which protrudes from the substrate (in the second region) and extends lengthwise in the first direction. A plurality of wire patterns are provided, which are spaced apart in the third direction from the second lower semiconductor pattern. A second gate insulating film is provided, which wraps around each of the wire patterns. In these embodiments, a thickness of the first gate insulating film is less than a thickness of the second gate insulating film, and a distance at which each of the sheet patterns is spaced in the third direction is smaller than a distance at which each of the wire patterns is spaced in the third direction.

According to another embodiment of the present invention, there is provided a semiconductor device, which includes a first region and a second region of a substrate, a first lower semiconductor pattern which protrudes from the substrate of the first region and extends in a first direction, a first gate electrode which extends in a second direction (orthogonal to the first direction) on the first lower semiconductor pattern, and a plurality of sheet patterns, which are spaced apart from the first lower semiconductor pattern in a third direction (orthogonal to the first and second directions). A first gate insulating film is provided, which wraps around each of the plurality of sheet patterns. This first gate insulating film includes a first interface film, and a first high dielectric constant film on the first interface film. A second lower semiconductor pattern is provided, which protrudes from the substrate (in the second region) and extends in the first direction. A second gate electrode is provided, which extends in the second direction on the second lower semiconductor pattern. A plurality of wire patterns are provided, which are spaced apart from the second lower semiconductor pattern in the third direction. A second gate insulating film is provided, which wraps around each of the wire patterns. The second gate insulating film includes a second interface film and a second high dielectric constant film on the second interface film. A thickness of the first interface film is less than a thickness of the second interface film, in some embodiments of the invention.

According to another embodiment of the invention, a semiconductor device is provided, which includes a substrate having at least first and second regions therein. A first lower semiconductor pattern is provided, which protrudes from the first region and extends lengthwise in a first direction across the substrate. A first gate electrode is provided, which extends across the first lower semiconductor pattern in a second direction that is orthogonal to the first direction. First to third sheet patterns are provided, which are sequentially stacked on the first lower semiconductor pattern in a third direction, which is orthogonal to the first and second directions. A first gate insulating film is provided, which wraps around the first to third sheet patterns. This first gate insulating film includes a first interface film, and a first high dielectric constant film on the first interface film. A second lower semiconductor pattern is provided, which protrudes from the second region and extends lengthwise across the substrate in the first direction. A second gate electrode is provided, which extends in the second direction on the second lower semiconductor pattern. First to third wire patterns are provided, which are vertically stacked in the third direction on the second lower semiconductor pattern. A second gate insulating film is provided, which wraps around the first to third wire patterns. The second gate insulating film includes a second interface film and a second high dielectric constant film on the second interface film. In addition, from a viewpoint of a cross-sectional area, the first wire pattern includes a first surface extending in the second direction, and a second surface connected to both ends of the first surface (and having a concave curved surface with respect to the second lower pattern). Likewise, from a viewpoint of the cross-sectional area, the second wire pattern includes a first sub-wire pattern, in which a width in the second direction gradually increases as it gets farther from the second lower pattern, and a second sub-wire pattern, which is placed on the first sub-wire pattern and has a width in the second direction that gradually decreases as it gets farther from the second lower pattern. A height of the first sub-wire pattern in the third direction may be smaller than a height of the second sub-wire pattern in the third direction. And, from a viewpoint of the cross-sectional area, the third wire pattern may have an elliptical shape in which a width in the second direction is smaller than a width in the third direction.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Although the drawings of a semiconductor device described herein show a fin-type transistor (FinFET) including a channel region of a fin-type pattern shape, a transistor including a nanowire or a nanosheet, and a MBCFET™ (Multi-Bridge Channel Field Effect Transistor) as an example, the embodiments are not limited thereto. For example, the semiconductor device according to some embodiments may include a tunneling transistor (tunneling FET) or a three-dimensional (3D) transistor. The semiconductor device according to some embodiments may also include a planar transistor. In addition, the many technical concepts described in this specification may be applied to transistors based on two-dimensional materials (2D material based FETs) and heterostructures thereof. Furthermore, semiconductor devices according to some embodiments may also include a bipolar junction transistor, a laterally diffused metal oxide semiconductor (LDMOS), or the like.

FIG.1is an exemplary layout diagram for explaining a semiconductor device according to some embodiments.FIG.2is an exemplary cross-sectional view taken along lines A-A′ and B-B′ ofFIG.1, andFIG.3is an exemplary cross-sectional view taken along lines C-C′ and D-D′ ofFIG.1. Referring toFIGS.1to3, the semiconductor device according to some embodiments may include a first substrate100, a second substrate200, a first gate electrode120, a second gate electrode220, a first active contact CA1, a second active contact CA2, a first gate contact160, and a second gate contact260. The first substrate100may be formed in a first region I. The second substrate200may be formed in a second region II. The first region I and the second region II may be, but are not limited to, regions adjacent to each other and may be regions spaced apart from each other.

In some embodiments, the first region I may be, for example, a region in which a first drive voltage transistor is formed. The second region II may be, for example, a region in which a second drive voltage transistor is formed. The first drive voltage may be lower than the second drive voltage. For example, the first transistor may be a transistor used for a low voltage. The second transistor may be a transistor used for a high voltage.

The first substrate100may include a first active region RX1. The second substrate200may include a second active region RX2. Although not shown, a first field region may be formed on both sides of the first active region RX1to be directly adjacent to the first active region RX1. Similarly, a second field region may be formed on both sides of the second active region RX2to be directly adjacent to the second active region RX2. The first active region RX1may be separated by the first field region. The second active region RX2may be separated by the second field region.

Explained by another method, an element isolation film may be placed around the first active region RX1. At this time, a portion of the element isolation film between the first active regions RX1spaced apart from each other may be the first field region. The element isolation film may be placed around the second active region RX2. At this time, a portion of the element isolation film between the second active regions RX2spaced apart from each other may be the second field region.

For example, a portion in which a channel region of the transistor is formed may be the active region, and a portion that divides the channel region of the transistor formed in the active region may be the field region. Alternatively, the active region may be a portion in which a nanosheet or a nanowire used as the channel region of the transistor is formed, and the field region may be a region in which the nanosheet or nanowire used as the channel region is not formed.

In some embodiments, one of the first active region RX1or the second active region RX2may be a PMOS formation region and the other may be an NMOS formation region. In another embodiment, the first active region RX1and the second active region RX2may be the PMOS formation region. In another embodiment, the first active region RX1and the second active region RX2may be the NMOS formation region.

The first substrate100and the second substrate200may be a silicon substrate or a SOI (silicon-on-insulator) substrate, for example. In contrast, the substrate100may include, but is not limited to, silicon germanium, SGOI (silicon germanium on insulator), indium antimonide, lead tellurium compounds, indium arsenic, indium phosphide, gallium arsenide or gallium antimonide.

A first lower pattern BP1may be formed on the first active region RX1. The first lower pattern BP1may protrude from the first substrate100. The first lower pattern BP1may extend long along a first direction X on the first substrate100. For example, the first lower pattern BP1may include a long side extending in the first direction X, and a short side extending in a second direction Y. Here, the first direction X may intersect the second direction Y and a third direction Z. Also, the second direction Y may intersect the third direction Z. A second lower pattern BP2may be formed in the second active region RX2. The second lower pattern BP2may protrude from the second substrate200. The second lower pattern BP2may extend long along the first direction X on the second substrate200. For example, the second lower pattern BP2may include a long side extending in the first direction X, and a short side extending in the second direction Y.

In some embodiments, a plurality of sheet patterns SP may be included on the first lower pattern BP1. Although the three sheet patterns SP are shown, this is only for convenience of explanation, and the embodiments described herein are not limited thereto.

The plurality of sheet patterns SP may include a first sheet pattern SP1, a second sheet pattern SP2, and a third sheet pattern SP3. The first sheet pattern SP1, the second sheet pattern SP2, and the third sheet pattern SP3may be sequentially placed on the first lower pattern BP1. The first sheet pattern SP1, the second sheet pattern SP2, and the third sheet pattern SP3may be spaced apart from each other in the third direction Z (in a vertical stack). The first sheet pattern SP1may be located between the second sheet pattern SP2and the first lower pattern BP1. The second sheet pattern SP2may be located between the third sheet pattern SP3and the first sheet pattern SP1. The sheet pattern SP may penetrate the first gate electrode120and be connected to a first source/drain pattern170. The sheet pattern SP may be a channel pattern which is used as a channel region of a transistor. For example, the sheet pattern SP may be a nanosheet.

A plurality of wire patterns WP may be included on the second lower pattern BP2. Although the three wire patterns WP are shown, this is only for convenience of explanation, and the embodiment is not limited thereto. The plurality of wire patterns WP may include a first wire pattern WP1, a second wire pattern WP2, and a third wire pattern WP3. The first wire pattern WP1, the second wire pattern WP2, and the third wire pattern WP3may be sequentially placed on the second lower pattern BP2. The first wire pattern WP1, the second wire pattern WP2, and the third wire pattern WP3may be spaced apart from each other in the third direction Z. The first wire pattern WP1may be located between the second wire pattern WP2and the first lower pattern BP2. The second wire pattern WP2may be located between the third wire pattern WP3and the first wire pattern WP1.

The wire pattern WP may penetrate the second gate electrode220, and be connected to the second source/drain pattern270. The wire pattern WP may be a channel pattern which is used as the channel region of the transistor. For example, the wire pattern WP may be a nanowire.

The first lower pattern BP1and the sheet pattern SP may each be a part of the first substrate100, and may include an epitaxial layer that is grown from the first substrate100. The second lower pattern BP2and the wire pattern WP may each be a part of the second substrate200, and may include an epitaxial layer that is grown from the second substrate200.

The first lower pattern BP1, the sheet pattern SP, the second lower pattern BP2, and the wire pattern WP may include, for example, silicon or germanium, which are elemental semiconductor materials. Further, the first lower pattern BP1, the sheet pattern SP, the second lower pattern BP2, and the wire pattern WP may include a compound semiconductor, and may include, for example, a group IV-IV compound semiconductor or a group III-V compound semiconductor.

The group IV-IV compound semiconductor may include, for example, a binary compound or a ternary compound including at least two or more of carbon (C), silicon (Si), germanium (Ge), and tin (Sn), or a compound obtained by doping these elements with a group IV element. The group III-V compound semiconductor may be, for example, at least one of a binary compound, a ternary compound or a quaternary compound formed by combining at least one of aluminum (Al), gallium (Ga) and indium (In) as a group III element with one of phosphorus (P), arsenic (As) and antimony (Sb) as a group V element.

A first field insulating film105may be formed on the first substrate100. At least a part of the first field insulating film105may be formed over the first active region RX1. In addition, the first field insulating film105may be formed on a part of a side wall BP1_SW of the first lower pattern BP1. The first lower pattern BP1may protrude upward from the upper surface of the first field insulating film105. That is, an upper surface BP1_US of the first lower pattern BP1may be formed to be higher than the upper surface of the first field insulating film105, as illustrated.

A second field insulating film205may be formed on the second substrate200. At least a part of the second field insulating film205may be formed over the second active region RX2. The second field insulating film205may be formed on a part of a side wall BP2_SW of the second lower pattern BP2. The second lower pattern BP2may protrude upward from the upper surface of the second field insulating film205. That is, an upper surface BP2_US of the second lower pattern BP2may be formed to be higher than the upper surface of the second field insulating film205, as illustrated.

The first field insulating film105and the second field insulating film205may include, for example, an oxide film, a nitride film, an oxynitride film or a combination film thereof. The first gate structure GS1may be placed on the first lower pattern BP1. The second gate structure GS2may be placed on the second lower pattern BP2. The first gate structure GS1may intersect the first lower pattern BP1. The second gate structure GS2may intersect the second lower pattern BP2.

The first gate structure GS1may include, for example, a first gate electrode120, a first gate insulating film130, a first gate spacer140, and a first gate capping pattern150. The second gate structure GS2may include, for example, a second gate electrode220, a second gate insulating film230, a second gate spacer240, and a second gate capping pattern250. The first gate electrode120may be formed on the first lower pattern BP1. The first gate electrode120may intersect the first lower pattern BP1. The first gate electrode120may include a long side extending in the second direction Y, and a short side extending in the first direction X.

An upper surface of the first gate electrode120may be, but is not limited to, a concave curved surface that is recessed toward the first lower pattern BP1. Unlike the shown example, the upper surface of the first gate electrode120may be a flat plane. The second gate electrode220may be formed on the second lower pattern BP2. The second gate electrode220may intersect the second lower pattern BP2. The second gate electrode220may include a long side extending in the second direction Y, and a short side extending in the first direction X. An upper surface of the second gate electrode220may be, but is not limited to, a concave curved surface that is recessed toward the second lower pattern BP2. Unlike the shown example, the upper surface of the second gate electrode220may be a flat plane.

In some embodiments, a volume (and cross-sectional area) of the first gate electrode120may be greater than a volume (and cross-sectional area) of the second gate electrode220. From the viewpoint of a cross-sectional area, a cross-sectional area of the first gate electrode120may be greater than a cross-sectional area of the second gate electrode220. Because the thickness of the first gate insulating film130is thinner than the thickness of the second gate insulating film230, the volume of the first gate electrode120may be greater than the volume of the second gate electrode220.

Each of the first gate electrode120and the second gate electrode220may include a conductive metal oxide, a conductive metal oxynitride, and the like, and may also include an oxidized form of the above-mentioned materials. The first gate spacer140may be placed on the side wall of the first gate electrode120. The first gate spacer140may extend in the second direction Y. The second gate spacer240may be placed on the side wall of the second gate electrode220. The second gate spacer240may extend in the second direction Y.

Each of the first gate spacer140and the second gate spacer240may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon oxycarbonitride (SiOCN), silicon boronitride (SiBN), silicon oxyboronitride (SiOBN), silicon oxycarbide (SiOC), and combinations thereof. The first gate insulating film130may extend along the side wall and bottom surface of the first gate electrode120. The first gate insulating film130may wrap around the sheet pattern SP. The first gate insulating film130may include a first interface film131and a first high dielectric constant film132.

The first interface film131may be placed on the upper surface BP1_US of the first lower pattern BP1and the upper surface of the first field insulating film105. The first interface film131may wrap around the sheet pattern SP. The first interface film131may be placed between the sheet pattern SP and the bottom surface of the first gate electrode120. The first interface film131may not extend along the side wall of the first gate spacer140. Unlike the shown example, the first interface film131may not extend along the upper surface of the first field insulating film105. The first interface film131extends along the upper surface of the first lower pattern BP1and may not extend along the upper surface of the first field insulating film105.

The first high dielectric constant film132may be placed on the first interface film131. The first high dielectric constant film132may wrap around the first interface film131. The first high dielectric constant film132may extend along the side walls and bottom surface of the first gate electrode120. The second gate insulating film230may extend along the side wall and bottom surface of the second gate electrode220. The second gate insulating film230may wrap around the wire pattern WP. The second gate insulating film230may include a second interface film231and a second high dielectric constant film232.

As shown, the second interface film231may be placed on the upper surface BP2_US of the second lower pattern BP2and the upper surface of the second field insulating film205. The second interface film231may wrap around the wire pattern WP. The second interface film231may be placed between the wire pattern WP and the bottom surface of the second gate electrode220. The second interface film231may not extend along the side wall of the second gate spacer240. Unlike the shown example, the second interface film231may not extend along the upper surface of the second field insulating film205. The second interface film231extends along the upper surface of the second lower pattern BP2, and may not extend along the upper surface of the second field insulating film205.

The second high dielectric constant film232may be placed on the second interface film231. The second high dielectric constant film232may wrap around the second interface film231. The second high dielectric constant film232may extend along the side walls and bottom surface of the second gate electrode220. The second high dielectric constant film232may wrap around the second interface film231.

The first interface film131and the second interface film231may include, for example, silicon oxide. The first high dielectric constant film132and the second high dielectric constant film232may include, for example, a high dielectric constant material having a higher dielectric constant than silicon oxide. The high dielectric constant material may include, for example, one or more of boron nitride, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide or lead zinc niobate.

The semiconductor device according to some other embodiments may include an NC (Negative Capacitance) FET using a negative capacitor. For example, the first gate insulating film130and the second gate insulating film230may include a ferroelectric material film having ferroelectric properties, and a paraelectric material film having paraelectric properties. For example, the ferroelectric material film may be configured to have a negative capacitance, and the paraelectric material film may be configured to have a positive capacitance. Thus, when two or more capacitors are connected in series, and the capacitance of each capacitor has a positive value, the entire capacitance decreases from the capacitance of each individual capacitor. On the other hand, when at least one of the capacitances of two or more capacitors connected in series has a negative value, the entire capacitance may be greater than an absolute value of each individual capacitance, while having a positive value.

When the ferroelectric material film having the negative capacitance and the paraelectric material film having the positive capacitance are connected in series, the overall capacitance values of the ferroelectric material film and the paraelectric material film connected in series may increase. By the use of the increased overall capacitance value, a transistor including the ferroelectric material film may have a subthreshold swing (SS) below 60 mV/decade at room temperature.

The ferroelectric material film may have ferroelectric properties. The ferroelectric material film may include, for example, at least one of hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and lead zirconium titanium oxide. Here, as an example, the hafnium zirconium oxide may be a material obtained by doping hafnium oxide with zirconium (Zr). As another example, the hafnium zirconium oxide may be a compound of hafnium (Hf), zirconium (Zr), and oxygen (O).

The ferroelectric material film may further include a dopant. For example, the dopant may include at least one of aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), and tin (Sn). The type of dopant included in the ferroelectric material film may vary, depending on which type of ferroelectric material is included in the ferroelectric material film.

When the ferroelectric material film includes hafnium oxide, the dopant included in the ferroelectric material film may include, for example, at least one of gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al), and yttrium (Y). When the dopant is aluminum (Al), the ferroelectric material film may include 3 to 8 atomic percent (at %) aluminum. Here, a ratio of the dopant may be a ratio of aluminum to the sum of hafnium and aluminum. In contrast, when the dopant is silicon (Si), the ferroelectric material film may include 2 to 10 atomic percent silicon. When the dopant is yttrium (Y), the ferroelectric material film may include 2 to 10 atomic percent yttrium. When the dopant is gadolinium (Gd), the ferroelectric material film may include 1 to 7 atomic percent gadolinium. When the dopant is zirconium (Zr), the ferroelectric material film may include 50 to 80 atomic percent zirconium.

The paraelectric material film may have paraelectric properties. The paraelectric material film may include at least one of, for example, a silicon oxide and a metal oxide having a high dielectric constant. The metal oxide included in the paraelectric material film may include, for example, but is not limited to, at least one of hafnium oxide, zirconium oxide, and aluminum oxide.

The ferroelectric material film and the paraelectric material film may include the same material. The ferroelectric material film has the ferroelectric properties, but the paraelectric material film may not have the ferroelectric properties. For example, when the ferroelectric material film and the paraelectric material film include hafnium oxide, a crystal structure of hafnium oxide included in the ferroelectric material film is different from a crystal structure of hafnium oxide included in the paraelectric material film.

The ferroelectric material film may have a thickness having the ferroelectric properties. A thickness of the ferroelectric material film may be, but is not limited to, for example, 0.5 nm to 10 nm. Since a critical thickness that exhibits the ferroelectric properties may vary for each ferroelectric material, the thickness of the ferroelectric material film may vary depending on the ferroelectric material.

In some embodiments, the first gate insulating film130and the second gate insulating film230may include a single ferroelectric material film. In another embodiment, the first gate insulating film130and the second gate insulating film230may include a plurality of ferroelectric material films spaced apart from each other. The first gate insulating film130and the second gate insulating film230may have a stacked film structure in which a plurality of ferroelectric material films and a plurality of paraelectric material films are stacked in an alternating arrangement of films.

The first gate capping pattern150may be placed on the upper surface of the first gate electrode120and the upper surface of the first gate spacer140. Unlike the shown example, the first gate capping pattern150may be placed between the first gate spacers140. In such a case, the upper surface of the first gate capping pattern150may be placed in the same plane as the upper surface of the first gate spacer140. The upper surface of the first gate capping pattern150may be an upper surface of the first gate structure GS1.

The second gate capping pattern250may be placed on the upper surface of the second gate electrode220and the upper surface of the second gate spacer240. Unlike the shown example, the second gate capping pattern250may be placed between the second gate spacers240. In such a case, the upper surface of the second gate capping pattern250may be placed in the same plane as the upper surface of the second gate spacer240. The upper surface of the second gate capping pattern250may be an upper surface of the second gate structure GS2.

The first gate capping pattern150and the second gate capping pattern250may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and combinations thereof.

A first source/drain pattern170may be formed on the first lower pattern BP1. The first source/drain pattern170may be placed between the first gate structures GS1. The first source/drain pattern170may be placed on the side surface of the first gate structure GS1. The first source/drain pattern170may be placed between the adjacent first gate structures GS1.

In some embodiments, the first source/drain pattern170may be placed on both sides of the first gate structure GS1. Unlike the shown example, the first source/drain pattern170is located on one side of the first gate structure GS1, but may not be placed on the other side of the first gate structure GS1. In addition, a second source/drain pattern270may be formed on the second lower pattern BP2. The second source/drain pattern270may be placed between the second gate structures GS2. The second source/drain pattern270may be placed on the side surface of the second gate structure GS2. The second source/drain pattern270may be placed between adjacent second gate structures GS2.

In other embodiments, the second source/drain pattern270may be placed on both sides of the second gate structure GS2. Unlike the shown example, the second source/drain pattern270is located on one side of the second gate structure GS2, but may not be placed on the other side of the second gate structure GS2.

The first source/drain pattern170and the second source/drain pattern270may include an epitaxial pattern. That is, the first source/drain pattern170may be included in a source/drain region of a transistor that uses the sheet pattern SP as a channel region. The second source/drain pattern270may be included in a source/drain region of a transistor that uses the wire pattern WP as the channel region.

In some embodiments, a first etching stop film176may be placed on the upper surface of the first source/drain pattern170, the side wall of the first gate structure GS1, and the side wall of the first source/drain pattern170. The first etching stop film176may extend to the upper surface of the first gate capping pattern150. A second etching stop film276may be placed on the upper surface of the second source/drain pattern270, the side wall of the second gate structure GS2, and the side wall of the second source/drain pattern270. Although it is not shown, the first etching stop film176and the second etching stop film276may not be formed.

The first etching stop film176and the second etching stop film276may include, for example, a material having an etching selectivity with respect to the first interlayer insulating film190. The first etching stop film176and the second etching stop film276may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), silicon boronitride (SiBN), silicon oxyboronitride (SiOBN), silicon oxycarbide (SiOC), and combinations thereof.

A first active contact CA1may be placed on the first active region RX1. A second active contact CA2may be placed on the second active region RX2. The first active contact CA1may be connected to the first source/drain pattern170formed in the first active region RX1. The second active contact CA2may be connected to a second source/drain pattern270formed in the second active region RX2. In some embodiments, the first active contact CA1may include a first lower active contact180and a first upper active contact. Although it is not shown, the first upper active contact may be placed on the first lower active contact180.

The first lower active contact180may be formed on the first source/drain pattern170. The first lower active contact180may be connected to the first source/drain pattern170. Although the upper surface of the first lower active contact180is shown to be formed higher than the upper surface of the gate electrode120, this is only for convenience of explanation, and the embodiment is not limited thereto. The upper surface of the first lower active contact180may, of course, be formed to be lower than the upper surface of the gate electrode120.

A first silicide film175may be formed between the first lower active contact180and the first source/drain pattern170. Although the first silicide film175is shown to be formed along a profile of an interface between the first source/drain pattern170and the first lower active contact180, the embodiment is not limited thereto. The first silicide film175may include, for example, a metal silicide material.

The first lower active contact180may be formed of multiple films. The first lower active contact180may include, for example, a first lower active contact barrier film180aand a first lower active contact filling film180b. The first lower active contact filling film180bmay be placed on the first lower active contact barrier film180a. The first lower active contact barrier film180amay extend along the side walls and bottom surface of the first lower active contact filling film180b.

The first lower active contact barrier film180amay include, for example, at least one of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), ruthenium (Ru), cobalt (Co), nickel (Ni), nickel boron (NiB), tungsten (W), tungsten nitride (WN), tungsten carbonitride (WCN), zirconium (Zr), zirconium nitride (ZrN), vanadium (V), vanadium nitride (VN), niobium (Nb), niobium nitride (NbN), platinum (Pt), iridium (Ir), rhodium (Rh) and a two-dimensional (2D) material. In the semiconductor device according to some embodiments, the two-dimensional material may be a metallic material and/or a semiconductor material. The two-dimensional (2D material) may include a two-dimensional allotrope or a two-dimensional compound, and may include, but is not limited to, for example, at least one of graphene, molybdenum disulfide (MoS2), molybdenum diselenide (MoSe2), tungsten diselenide (WSe2), and tungsten disulfide (WS2). That is, since the above-mentioned two-dimensional materials are only listed by way of example, the two-dimensional materials that may be included in the semiconductor device of the present disclosure are not limited by the above-mentioned materials. A first lower active contact filling film180bmay include, for example, at least one of aluminum (Al), tungsten (W), cobalt (Co), ruthenium (Ru), silver (Ag), gold (Au), manganese (Mn), and molybdenum (Mo).

The second active contact CA2may include a second lower active contact280and a second upper active contact285. The description of the second lower active contact280may be the same as the description of the first lower active contact180. A second silicide film275may be formed between the second lower active contact280and the second source/drain pattern270. Although the second silicide film275is shown to be formed along a profile of an interface between the second source/drain pattern270and the second lower active contact280, the embodiment is not limited thereto. The second silicide film275may include, for example, a metal silicide material.

The second lower active contact280may be formed of multiple films. The second lower active contact280may include, for example, a second lower active contact barrier film280aand a second lower active contact filling film280b. The second lower active contact filling film280bmay be placed on the second lower active contact barrier film280a. The second lower active contact barrier film280amay be placed along the side walls and bottom surface of the second lower active contact filling film280b.

The description of the materials included in the second lower active contact barrier film280aand the second lower active contact filling film280bmay be the same as the description of the first lower active contact barrier film180aand the first lower active contact filling film180b.

The second upper active contact285may be placed on the second lower active contact280. The second upper active contact285may be connected to the second lower active contact280. That is, the second upper active contact285may be connected to the second source/drain pattern270. The second upper active contact285may extend to the upper surface of the first interlayer insulating film190. That is, the upper surface of the second upper active contact285may be placed on the same plane as the upper surface of the first interlayer insulating film190, the upper surface of the first gate contact160, the upper surface of the second gate capping pattern250, and the upper surface of the first gate capping pattern150. In addition, the second upper active contact285may be formed of multiple films. The second upper active contact285may include, for example, a second upper active contact barrier film285aand a second upper active contact filling film285b. The second upper active contact filling film285bmay be placed on the second upper active contact barrier film285a. The second upper active contact barrier film285amay be placed along the side walls and bottom surface of the second upper active contact filling film285b. The description of the materials included in the second upper active contact barrier film285aand the second upper active contact filling film285bmay be the same as the above description of the first lower active contact barrier film180aand the first lower active contact filling film180b.

The first gate contact160may be placed on the first active region RX1. The second gate contact260may be placed on the second active region RX2. Since the first gate contact160and the second gate contact260may be substantially the same, only the first gate contact160will be described below. The first gate contact160may be placed inside the first gate structure GS1. The first gate contact160may be connected to the first gate electrode120included in the first gate structure GS1. The first gate contact160may be formed to penetrate the first gate capping pattern150in the third direction Z.

The first gate contact160may be placed at a position where it overlaps the first gate structure GS1. In some embodiments, at least a part of the first gate contact160may be placed at a position where it overlaps the sheet pattern SP. The upper surface of the first gate contact160may be placed in the same plane as the upper surface of the first gate capping pattern150. The upper surface of the first gate contact160may be located at the same plane as the upper surface of the second upper active contact285. The upper surface of the first gate contact160may be located in the same plane as the upper surface of the first interlayer insulating film190.

The first gate contact160may be formed of multiple films. The first gate contact160may include, for example, a gate contact barrier film160aand a gate contact filling film160b. The gate contact filling film160bmay be placed on the gate contact barrier film160a. The gate contact barrier film160amay be placed along the side walls and bottom surface of the gate contact filling film160b. The contents of the materials included in the gate contact barrier film160aand the gate contact filling film160bmay be the same as the description of the first lower active contact barrier film180aand the first lower active contact filling film180b.

The first interlayer insulating film190may be formed on the first source/drain pattern170, the second source/drain pattern270, the first field insulating film105, and the second field insulating film205. The first interlayer insulating film190may cover the side wall of the first lower active contact180, the side wall of the second lower active contact280, and the side wall of the second upper active contact285. The first interlayer insulating film190may include, for example, but is not limited to, Fluorinated TetraEthylOrthoSilicate (FTEOS), Hydrogen SilsesQuioxane (HSQ), Bis-benzoCycloButene (BCB), TetraMethylOrthoSilicate (TMOS), OctaMethyleyCloTetraSiloxane (OMCTS), HexaMethylDiSiloxane (HMDS), TriMethylSilyl Borate (TMSB), DiAcetoxyDitertiaryButoSiloxane (DADBS), TriMethylSilil Phosphate (TMSP), PolyTetraFluoroEthylene (PTFE), TOSZ (Tonen SilaZen), FSG (Fluoride Silicate Glass), polyimide nanofoams such as polypropylene oxide, CDO (Carbon Doped silicon Oxide), OSG (Organo Silicate Glass), SiLK, Amorphous Fluorinated Carbon, silica aerogels, silica xerogels, mesoporous silica or combinations thereof.

In some embodiments, a second interlayer insulating film390and a third interlayer insulating film490may be formed on the first interlayer insulating film190. Each of the second interlayer insulating film390and the third interlayer insulating film490may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride and a low dielectric constant material.

In some embodiments, a wiring etching stop film195may extend along the upper surface of the first gate capping pattern150, the upper surface of the first interlayer insulating film190, the upper surface of the second gate capping pattern250and the upper surface of the second upper active contact285. In addition, the second interlayer insulating film390may be placed on the wiring etching stop film195. The wiring etching stop film195may include a material having an etching selectivity with respect to the second interlayer insulating film390. The wiring etching stop film195may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), silicon boronitride (SiBN), silicon oxyboronitride (SiOBN), silicon oxycarbide (SiOC), aluminum oxide (AlO), aluminum nitride (AlN), aluminum oxycarbide (AlOC) and a combination thereof.

The first wiring pattern310may be placed on the first gate contact160and the second upper active contact285. The first wiring pattern310may be connected to the first gate contact160. The first wiring pattern310may be connected to the second upper active contact285. The first wiring pattern310may be formed to penetrate the wiring etching stop film195. The first wiring pattern310may be placed inside the second interlayer insulating film390. The first wiring pattern310may include a portion that comes into direct contact with the second gate capping pattern250.

The first wiring pattern310may have a multiple conductive film structure. The first wiring pattern310may include, for example, a first wiring barrier film310aand a first wiring filling film310b. The first wiring filling film310bmay be placed on the first wiring barrier film310a. The first wiring barrier film310amay be placed along the side walls and bottom surface of the first wiring filling film310b.

In some embodiments, a via structure410and a second wiring pattern420may be included on the first wiring pattern310. The via structure410and the second wiring pattern420may be placed inside the third interlayer insulating film490.

The via structure410may be formed on the first wiring pattern310. The via structure410may be connected to the first wiring pattern310. The via structure410may be multiple films including a via barrier film410aand a via filling film410b. The via filling film410bmay be placed on the via barrier film410a. The via barrier film410amay be placed along the side walls and bottom surface of the via filling film410b.

The second wiring pattern420may be placed on the via structure410. The second wiring pattern420may be multiple films including a second wiring barrier film420aand a second wiring filling film420b. The second wiring filling film420bmay be placed on the second wiring barrier film420a. The second wiring barrier film420amay be placed along the side walls and bottom surface of the second wiring filling film420b. Contents of the materials included in the second wiring barrier film420aand the second wiring filling film420bmay be the same as the description of the materials included in the first wiring barrier film310aand the first wiring filling film310b.

FIG.4is an enlarged view of a region P and a region Q ofFIG.2.FIG.5is an enlarged view of a region R and a region S ofFIG.3. Hereinafter, the sheet pattern SP, the wire pattern WP, the first gate insulating film130, and the second gate insulating film230will be described in a more detail referring toFIGS.4and5.

Referring toFIGS.4and5, a total thickness (t1+t3) of the first gate insulating film130may be smaller than a total thickness (t2+t4) of the second gate insulating film230. In some embodiments, a thickness t1of the first interface film131may be smaller than a thickness t2of the second interface film231. As described above, a first drive voltage of the transistor of the first region I may be lower than a second drive voltage of the transistor of the second region II. Therefore, the thickness t1of the first interface film131may be smaller than the thickness t2of the second interface film231.

A thickness t3of the first high dielectric constant film132may be the same as a thickness t4of the second high dielectric constant film232. The first high dielectric constant film132and the second high dielectric constant film232may be formed at the same level. As used herein, the term “same level” means formation by the same fabricating process. That is, since the thickness t1of the first interface film131is smaller than the thickness t2of the second interface film231, and the thickness t3of the first high dielectric constant film132is the same as the thickness t4of the second high dielectric constant film232, the total thickness (t1+t3) of the first gate insulating film130is smaller than the total thickness (t2+t4) of the second gate insulating film230.

In some embodiments, a distance d1at which the sheet pattern SP is separated in the third direction Z may be smaller than a distance d2at which the wire pattern WP is separated in the third direction Z. That is, the distance d1at which the first sheet pattern SP1and the second sheet pattern SP2are separated may be smaller than the distance d2at which the first wire pattern WP1and the second wire pattern WP2are separated. Because the distance d2at which the first wire pattern WP1and the second wire pattern WP2are separated from each other is greater than the distance d1at which the first sheet pattern SP1and the second sheet pattern SP2are separated from each other, it is possible to easily form the second interface film231as a relatively thick film.

In some embodiments, a height H3from a reference plane RP to the upper surface of the first sheet pattern SP1may be greater than is a height H4from the reference plane RP to the upper surface of the first wire pattern WP1. Here, the reference plane RP may be a virtual plane that passes through a center of the first sheet pattern SP1and a center of the first wire pattern WP1. The reference plane RP may extend in the first direction X and the second direction Y. That is, a width of the sheet pattern SP in the third direction Z may be greater than a width of the wire pattern WP in the third direction Z.

In some embodiments, an upper surface BP1_US of the first lower pattern BP1may be placed in the same plane as an upper surface BP2_US of the second lower pattern BP2. A height H5in the third direction Z from the upper surface BP1_US of the first lower pattern BP1to the reference plane RP may be the same as a height H6from the upper surface BP2_US of the second lower pattern BP2to the reference plane RP. However, the technical idea of the present disclosure is not limited thereto.

In some embodiments, the width of the sheet pattern SP in the first direction X may be the same as the width of the wire pattern WP in the first direction X. The width of the sheet pattern SP in the second direction Y may be greater than the width of the wire pattern WP in the second direction Y.

In some embodiments, a width W3of the upper surface BP1_US of the first lower pattern BP1in the second direction Y may be greater than a width W4of the upper surface BP2_US of the second lower pattern BP2in the second direction Y. However, the technical idea of the present disclosure is not limited thereto. The width W3of the upper surface BP1_US of the first lower pattern BP1in the second direction Y may be the same as the width W4of the upper surface BP2_US of the second lower pattern BP2in the second direction Y.

FIG.6is an enlarged view of a region T ofFIG.5. Hereinafter, the wire pattern will be described in more detail referring toFIG.6. Referring toFIG.6, the wire pattern WP may include a first wire pattern WP1, a second wire pattern WP2, and a third wire pattern WP3. The first wire pattern WP1to the third wire pattern WP3may be placed sequentially. That is, the second wire pattern WP2may be located between the first wire pattern WP1and the third wire pattern WP3.

In some embodiments, the first wire pattern WP1may have a semi-circular shape from the viewpoint of the cross-sectional area. For example, the first wire pattern WP1may include a first surface WP1_aextending in the second direction Y, and a second surface WP1_bhaving a concave curved surface with respect to the first surface WP1_aon the first surface WP1_a. The second surface WP1_bmay be in contact with both ends of the first surface WP1_a. The second surface WP1_bmay have a concave curved surface with respect to the second lower pattern BP2. The first surface WP1_aof the first wire pattern WP1may be, for example, a semicircular diameter. The second surface WP2_bof the first wire pattern WP1may be, for example, a semicircular arc. From the viewpoint of the cross-sectional area, the second wire pattern WP2may include a first sub-wire pattern WP2_1and a second sub-wire pattern WP2_2. The second sub-wire pattern WP2_2may be placed on the first sub-wire pattern WP2_1. The width of the first sub-wire pattern WP2_1in the second direction Y may gradually increase as its distance from the first wire pattern WP1increases. The width of the second sub-wire pattern WP2_2in the second direction Y may gradually decrease as its distance from the first wire pattern WP1increases.

The width of the first sub-wire pattern WP2_1in the second direction Y may gradually increase as its distance from the second lower pattern BP2increases. The width of the second sub-wire pattern WP2_2in the second direction Y may gradually decrease as its distance from the second lower pattern BP2increases. A height H1of the first sub-wire pattern WP2_1in the third direction Z may be smaller than a height H2of the first sub-wire pattern WP2_2in the third direction Z. However, the technical idea of the present disclosure is not limited thereto.

The second wire pattern WP2may have a third surface WP2_aand a fourth surface WP2_b. The fourth surface WP2_bmay be placed on the third surface WP2_a. The third surface WP2_aand the fourth surface WP2_bmay be connected to each other. The third surface WP2_amay be a convex curved surface with respect to the first wire pattern WP1. The fourth surface WP2_bmay be a concave curved surface with respect to the first wire pattern WP1. A length of the third surface WP2_amay be shorter than a length of the fourth surface WP2_b. However, the technical idea of the present disclosure is not limited thereto.

From the viewpoint of the cross-sectional area, the third wire pattern WP3may have an elliptical shape. The third wire pattern WP3may have an elliptical shape in which the width W1in the second direction Y is smaller than the width W2in the third direction Z. The third wire pattern WP3may have a fifth surface WP3_aand a sixth surface WP3_b. The fifth surface WP3_amay be a convex curved surface with respect to the first wire pattern WP1. The sixth surface WP3_bmay be a concave curved surface with respect to the first wire pattern WP1. A length of the fifth surface WP3_amay be the same as a length of the sixth surface WP3_b, but is not limited thereto.

In some embodiments, the volume of the first wire pattern WP1may be greater than the volumes of the second wire pattern WP2and the third wire pattern WP3. The volume of the second wire pattern WP2may be greater than the volume of the third wire pattern WP3. However, the technical idea of the present disclosure is not limited thereto.

FIG.7is a diagram for explaining the semiconductor device according to some embodiments. For convenience of explanation, points different from contents described usingFIGS.1to6will be mainly described. For reference,FIG.7may be a cross-sectional view taken along lines C-C′ and D-D′ ofFIG.1. Referring toFIG.7, the side wall BP2_SW of the second lower pattern BP2may include a curved line.

The second lower pattern BP2may include a first portion BP2_1that overlaps the second field insulating film205in the second direction Y, and a second portion BP2_2that does not overlap the second field insulating film205in the second direction Y. The side wall BP2_SW of the second lower pattern BP2may include a side wall BP2_SW1of the first portion BP2_1of the second lower pattern BP2, and a side wall BP2_SW2of the second portion BP2_2of the second lower pattern BP2.

The side wall BP2_SW1of the first portion BP2_1of the second lower pattern BP2may be a straight line. The side wall BP2_SW2of the second portion BP2_2of the second lower pattern BP2may be a curved line. A slope of the side wall BP2_SW1of the first portion BP2_1of the second lower pattern BP2may be different from a slope of the side wall BP2_SW2of the second portion BP2_2of the second lower pattern BP2. In the process of forming the wire pattern WP, a part of the second lower pattern BP2may be removed. In the process of forming the wire pattern WP, a part of the second portion BP2_2of the second lower pattern BP2may be removed. However, the technical idea of the present disclosure is not limited thereto.

FIG.8is a diagram for explaining a semiconductor device according to some embodiments. For convenience of explanation, points different from contents described usingFIGS.1to6will be mainly described. For reference,FIG.8may be a cross-sectional view taken along lines C-C′ and D-D′ ofFIG.1. Referring toFIG.8, a width W5of the first sheet pattern SP1in the second direction Y may be different from a width W6of the second sheet pattern SP2and the third sheet pattern SP3in the second direction Y. The width W6of the second sheet pattern SP2in the second direction Y may be the same as the width W6of the third sheet pattern SP3in the second direction Y. On the other hand, the width W5of the first sheet pattern SP1in the second direction Y may be greater than the width W6of the second sheet pattern SP2and the third sheet pattern SP3in the second direction Y.

FIG.9is a diagram for explaining a semiconductor device according to some embodiments. For convenience of explanation, points different from contents described usingFIGS.1to6will be mainly described. For reference,FIG.9may be a cross-sectional view taken along lines C-C′ and D-D′ ofFIG.1. Referring toFIG.9, the first to third wire patterns WP1to WP3according to some embodiments may all have the same shape. Each of the first to third wire patterns WP1to WP3may all have, for example, a circular shape. The volumes of each of the first to third wire patterns WP1to WP3may all be the same. However, the technical idea of the present disclosure is not limited thereto. The first to third wire patterns WP1to WP3may, of course, have an elliptical shape.

FIG.10is a diagram for explaining the semiconductor device according to some embodiments. For convenience of explanation, points different from contents described usingFIGS.1to6and9will be mainly described. For reference,FIG.10may be a cross-sectional view taken along lines C-C′ and D-D′ ofFIG.1.

Referring toFIG.10, the wire pattern WP according to some embodiments may have different sizes. For example, from the viewpoint of the cross-sectional area, the size of the first wire pattern WP1may be greater than the sizes of the second wire pattern WP2and the third wire pattern WP3. The size of the second wire pattern WP2may be greater than the size of the third wire pattern WP3. That is, the size of the wire pattern WP may gradually decrease as its distance from the second lower pattern BP2increases. In some embodiments, the volume of the first wire pattern WP1may be greater than the volumes of the second wire pattern WP2and the third wire pattern WP3. The volume of the second wire pattern WP2may be greater than the volume of the third wire pattern WP3.

FIG.11is a diagram for explaining a semiconductor device according to some embodiments.FIG.12is a diagram for explaining a semiconductor device according to some embodiments. For convenience of explanation, points different from contents described usingFIGS.1to6will be mainly described. For reference,FIG.11may be a cross-sectional view taken along lines A-A′ and B-B′ ofFIG.1.FIG.12may be a cross-sectional view taken along lines C-C′ and D-D′ ofFIG.1.

Referring toFIG.11andFIG.12, the upper surface BP1_US of the first lower pattern BP1and the upper surface BP2_US of the second lower pattern BP_2may not be located in the same plane. The upper surface BP1_US of the first lower pattern BP1may be formed to be higher than the upper surface BP2_US of the second lower pattern BP_2. As an example, a height H7from the upper surface150_US of the first gate capping pattern150to the upper surface BP1_US of the first lower pattern BP1may be smaller than a height H8from the upper surface250_US of the second gate capping pattern250to the upper surface BP2_US of the second lower pattern BP2. The upper surface150_US of the first gate capping pattern150may be located in the same plane as the upper surface250_US of the second gate capping pattern250. Accordingly, the upper surface150_US of the first gate capping pattern150may be higher than the upper surface BP2_US of the second lower pattern BP2.

The height from the upper surface of the first substrate100to the upper surface BP1_US of the first lower pattern BP1may be greater than the height from the upper surface of the second substrate200to the upper surface BP2_US of the second lower pattern BP_2. A height of the first lower pattern BP1in the third direction Z may be greater than the height of the second lower pattern BP2in the third direction Z. In the process of forming the wire pattern WP, a part of the second lower pattern BP2is removed, and the upper surface BP2_US of the second lower pattern BP2may be lowered.

FIG.13is a diagram for explaining a semiconductor device according to some embodiments. For convenience of explanation, points different from contents described usingFIGS.1to6will be mainly described. For reference,FIG.13may be a cross-sectional view taken along lines A-A′ and B-B′ ofFIG.1. Referring toFIG.13, a first interface film131on the sheet pattern SP may be placed in a ‘U’ shape. A second interface film231on the wire pattern WP may be placed in a ‘U’ shape. The first interface film131may be placed on the side wall of the first gate spacer140. The first interface film131may be placed between the side wall of the first gate spacer140and the first high dielectric constant film132. The second interface film231may be placed on the side wall of the second gate spacer240. The second interface film231may be placed between the side wall of the second gate spacer240and the second high dielectric constant film232.

FIG.14is a diagram for explaining a semiconductor device according to some embodiments. For convenience of explanation, points different from contents described usingFIGS.1to6will be mainly described. For reference,FIG.14may be a cross-sectional view taken along lines A-A′ and B-B′ ofFIG.1. Referring toFIG.14, the first gate spacer140may include a first outer spacer141and a first inner spacer142. The second gate spacer240may include a second outer spacer241and a second inner spacer242.

The first inner spacer142may be placed between the first source/drain patterns170. The second inner spacer242may be placed between the second source/drain patterns270. The first inner spacer142and the second inner spacer242may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon oxycarbonitride (SiOCN), silicon boronitride (SiBN), silicon oxyboronitride (SiOBN), silicon oxycarbide (SiOC), and combinations thereof.

The first interface film131may not extend along the side wall of the first inner spacer142between the first source/drain patterns170. The first interface film131may be placed between the sheet pattern SP and the first high dielectric constant film132, or between the first lower pattern BP1and the first high dielectric constant film132. The second interface film231may not extend along the side wall of the second inner spacer242between the second source/drain patterns270. The second interface film231may be placed between the wire pattern WP and the second high dielectric constant film232, or between the second lower pattern BP2and the second high dielectric constant film232.

FIG.15is a diagram for explaining a semiconductor device according to some embodiments. For convenience of explanation, points different from contents described usingFIGS.1to6and14will be mainly described. For reference,FIG.15may be a cross-sectional view taken along lines A-A′ and B-B′ ofFIG.1. Referring toFIG.15, the first interface film131on the sheet pattern SP may be placed in a ‘U’ shape. The second interface film231on the wire pattern WP may be placed in a CU′ shape.

The first interface film131may be placed on the side wall of the first outer spacer141. The first interface film131may extend along the side walls of the sheet pattern SP and the first outer spacer141. The first interface film131may be placed on the side wall of the first inner spacer142. The first interface film131may wrap around the first high dielectric constant film132.

The second interface film231may be placed on the side wall of the second outer spacer241. The second interface film231may extend along the side walls of the wire pattern WP and the second outer spacer241. The second interface film231may be placed on the side wall of the second inner spacer242. The second interface film231may wrap around the second high dielectric constant film232.

FIG.16is a diagram for explaining a semiconductor device according to some embodiments.FIG.17is a diagram for explaining a semiconductor device according to some embodiments. For convenience of explanation, points different from contents described usingFIGS.1to6will be mainly described. For reference,FIG.16may be a cross-sectional view taken along lines A-A′ and B-B′ ofFIG.1.FIG.17may be a cross-sectional view taken along lines C-C′ and D-D′ ofFIG.1.

Referring toFIGS.16and17, the number of sheet patterns SP may be greater than the number of wire patterns WP. The sheet patterns SP may include a first sheet pattern SP1, a second sheet pattern SP2, a third sheet pattern SP3, and a fourth sheet pattern SP4which are sequentially placed on the first lower pattern BP1. The first sheet pattern SP1may be located between the first lower pattern BP1and the second sheet pattern SP2. The second sheet pattern SP2may be located between the third sheet pattern SP3and the first sheet pattern SP1. The third sheet pattern SP3may be located between the fourth sheet pattern SP4and the second sheet pattern SP2. Moreover, although the number of sheet patterns SP is shown as four, and the number of wire patterns WP is shown as three, this is only for convenience of explanation, and the numbers thereof are not limited thereto.

FIGS.18to33are cross-sectional views of intermediate structures that illustrate methods of fabricating semiconductor devices according to some embodiments of the present disclosure. Referring toFIG.18, a first lower pattern BP1may be formed on the first substrate100of the first region I. A first field insulating film105may be formed on both sides of the first lower pattern BP1. A first mold film510and a pre-sheet pattern520may be sequentially stacked on the first lower pattern BP1. Although the numbers of first mold films510and pre-sheet patterns520are shown as three, this is only for convenience of explanation, and the numbers thereof are not limited thereto.

A second lower pattern BP2may be formed on the second substrate200of the second region II. A second field insulating film205may be formed on both sides of the second lower pattern BP2. A second mold film610and a pre-wire pattern620may be sequentially stacked on the second lower pattern BP2. Although the numbers of second mold films610and pre-wire patterns620are shown as three, this is only for convenience of explanation, and the numbers thereof are not limited thereto.

In some embodiments, the thickness of the first mold film510and the second mold film610may be, for example, 10 nm to 50 nm. The first mold film510and the second mold film610may be formed at the same level. The pre-sheet pattern520and the pre-wire pattern620may be formed at the same level. However, the technical idea of the present disclosure is not limited thereto. Of course, the thickness of the first mold film510and the thickness of the second mold film610may be different from each other. Although the thicknesses of the first mold film510and the second mold film610are shown as being different from the thicknesses of the pre-sheet pattern520and the pre-wire pattern620, this is only for convenience of explanation, and the embodiment is not limited thereto. The thicknesses of the first mold film510and the second mold film610may be the same as the thicknesses of the pre-sheet pattern520and the pre-wire pattern620.

The first mold film510and the second mold film610may include, for example, silicon germanium (SiGe). The pre-sheet pattern520and the pre-wire pattern620may include, for example, silicon (Si). In some embodiments, the concentration of germanium (Ge) included in the first mold film510and the second mold film610may be 10% to 90%. The concentration of germanium (Ge) included in the first mold film510may be the same as the concentration of germanium (Ge) included in the second mold film610. However, the technical idea of the present disclosure is not limited thereto. The concentration of germanium (Ge) included in the first mold film510may, of course, differ from the concentration of germanium (Ge) included in the second mold film610.

Referring toFIG.19, in the second region II, a protective film700may be formed on the side wall of the second mold film610, the side wall of the pre-wire pattern620, and the upper surface of the pre-wire pattern620. The protective film700may protect the pre-wire pattern620when the sheet pattern is formed. The protective film700may include, for example, but is not limited to, silicon (Si).

Referring toFIG.20, in the second region II, a first sacrificial film810may be formed on the second field insulating film205and the protective film700. The first sacrificial film810may protect the pre-wire pattern620when the sheet pattern is formed. The first sacrificial film810may include, for example, but is not limited to, silicon oxide. Unlike the shown example, the first sacrificial film810may not be formed.

Referring toFIG.21, the sheet pattern SP may be formed by removing the first mold film510. The first mold film510may be selectively removed by utilizing the process of selectively removing silicon germanium. That is, silicon germanium may be removed, but silicon may not be removed.

In some embodiments, the sheet pattern closest to the first lower pattern BP1may be the first sheet pattern SP1. The second sheet pattern SP2may be formed on the first sheet pattern SP1. The second sheet pattern SP2may be spaced apart from the first sheet pattern SP1in the third direction Z. The third sheet pattern SP3may be formed on the second sheet pattern SP2. The third sheet pattern SP3may be spaced apart from the second sheet pattern SP2in the third direction Z.

Referring toFIG.22, the protective film700and the first sacrificial film810may be removed. The first sacrificial film810may be removed to expose the protective film700. Subsequently, the protective film700may be removed to expose the second mold film610and the pre-wire pattern620.

Referring toFIG.23, in the first region I, a second sacrificial film820that wraps the sheet pattern SP may be formed on the first field insulating film105and the first lower pattern BP1. The second sacrificial film820may protect the sheet pattern SP in the process of forming the wire pattern (e.g., WP ofFIG.28). The second sacrificial film820may include, for example, silicon oxide, silicon nitride, and a combination film thereof. The second sacrificial film820may include, for example, but is not limited to, SOH.

Referring toFIG.24, an oxidation process may be performed in the second region II. As the oxidation process is performed, an oxide film900is formed along the side wall of the second mold film610, the side wall of the pre-wire pattern620, and the upper surface of the pre-wire pattern620. The oxide film900may be formed, while oxidizing the second mold film610or the pre-wire pattern620. The oxide film900may include silicon oxide (SiO2). Moreover, silicon germanium (SiGe) included in the second mold film610may be oxidized to form silicon germanium oxide (SiGeO). Subsequently, the silicon germanium oxide (SiGeO) may be oxidized to form silicon oxide (SiO2) and germanium (Ge). Germanium (Ge) may be diffused toward the pre-wire pattern620. Silicon (Si) included in the pre-wire pattern620may be oxidized to form silicon oxide (SiO2).

The oxidation process may include, for example, at least one of a dry oxygen (O2) annealing process of 500° C. or higher, a wet annealing process of 400° C. or higher, and ozone (O3) and hydrogen peroxide (H2O2) annealing process of 300° C. or higher. However, the technical idea of the present disclosure is not limited thereto.

Referring toFIG.25, the thickness of the oxide film900may further increase. For example, as the oxidation process is performed, an amount of oxidation of silicon germanium (SiGe) included in the second mold film610may increase. The amount of oxidation of silicon (Si) included in the pre-wire pattern620may increase. As the amount of oxidation of the second mold film610and the pre-wire pattern620increases, the thickness of the oxide film900may gradually increase. And, as the amount of oxidation of the pre-wire pattern620increases, the width of the pre-wire pattern620may gradually decrease.

Referring toFIG.26, germanium (Ge) generated with oxidation of the second mold film610is may be diffused. Germanium (Ge) may be diffused toward the pre-wire pattern620. Silicon (Si) included in the pre-wire pattern620and diffused germanium (Ge) may be combined to form silicon germanium (Ge). That is, the cross-sectional area of the pre-wire pattern620may decrease from the viewpoint of the cross-sectional area. The cross-sectional area of the second mold film610may increase.

Referring toFIG.27, the cross-sectional area of the pre-wire pattern620may decrease from the viewpoint of the cross-sectional area. Germanium (Ge) formed with oxidation of the second mold film610may be diffused into the pre-wire pattern620. The silicon (Si) included in the pre-wire pattern620may be combined with the diffused germanium (Ge).

Referring toFIG.28, the second mold film610may be removed to form a wire pattern WP. The second mold film610may be selectively removed by utilizing the process of selectively removing silicon germanium (Ge). Silicon germanium (Ge) may be removed and silicon (Si) may not be removed. The wire pattern closest to the second lower pattern BP2may be the first wire pattern WP1. The second wire pattern WP2may be formed on the first wire pattern WP1. The second wire pattern WP2may be spaced apart from the first wire pattern WP1in the third direction Z. The third wire pattern WP3may be formed on the second wire pattern WP2. The third wire pattern WP3may be spaced apart from the second wire pattern WP2in the third direction Z.

Referring toFIGS.6and28, the first wire pattern WP1may have a semi-circular shape. The second wire pattern WP2may have an elliptical shape. The third wire pattern WP3may have an elliptical shape. However, the technical idea of the present disclosure is not limited thereto. The shape of the wire pattern WP may vary, depending on the extent to which the oxidation process is performed.

Referring toFIG.29, the second interface film231may be formed on the upper surface of the second lower pattern BP2and the upper surface of the second field insulating film205in the second region II. The second interface film231may wrap around the wire pattern WP. Referring toFIG.30, a third sacrificial film830that completely covers the second interface film231may be formed in the second region II. The third sacrificial film830may be used to selectively form the first interface film131in the first region I. The third sacrificial film830may include, for example, silicon oxide, silicon nitride, and a combination film thereof. Referring toFIG.31, the first interface film131may be formed on the upper surface of the first lower pattern BP1and the upper surface of the first field insulating film105in the first region I. The first interface film131may wrap around the sheet pattern SP. Referring toFIG.32, the third sacrificial film830may be removed. Subsequently, the first high dielectric constant film132may be formed on the first interface film131. A second high dielectric constant film232may be formed on the second interface film231. The first high dielectric constant film132and the second high dielectric constant film232may be formed at the same level, and the thickness of the first high dielectric constant film132may be the same as the thickness of the second high dielectric constant film232.

Referring toFIG.33, the first gate electrode120may be formed on the first high dielectric constant film132in the first region I. The second gate electrode220may be formed on the second high dielectric constant film232in the second region II. The first gate electrode120and the second gate electrode220may be formed at the same level.