POWER CONVERSION DEVICE CONTROL SYSTEM

A control system is provided for a power conversion system having a power converter that controls a virtual synchronous generator simulating a synchronous generator and interconnected to a power grid. The control system has a virtual synchronous impedance compensation block inputting an output current detection value of the power converter and a set voltage amplitude command value, simulating a voltage drop due to a virtual synchronous impedance, and calculating an output voltage command value and an internal induced voltage according to the simulated voltage drop; a virtual synchronous generator model determining an angular frequency simulating the synchronous generator; and a PCS output voltage control unit performing control so that an output voltage of the power conversion system coincides with the output voltage command value calculated by the virtual synchronous impedance compensation block.

TECHNICAL FIELD

The present invention relates to a control system of a power conversion device (a power conversion system), and relates to a method of simulating a voltage drop generated by a virtual synchronous impedance model according to an output current and controlling an output voltage amplitude in a voltage control-type power converter that controls a virtual synchronous generator simulating a synchronous generator.

BACKGROUND ART

FIG.1shows, at an upper side thereof, a configuration of a PCS (Power Conversion System) in which a power converter that converts DC power of a DC power supply such as a storage battery into AC power is provided and an output of the power converter is interconnected to a power system (a power grid) through an LC filter.FIG.1also shows, at a lower side thereof, a configuration of a virtual synchronous impedance model.

As a conventional virtual synchronous power generation system by the storage battery, a virtual synchronous power generation system disclosed in, for instance, Patent Document 1 has been proposed.

CITATION LIST

Patent Document

SUMMARY OF THE INVENTION

InFIG.1, in a voltage control-type power converter that controls a virtual synchronous generator simulating a synchronous generator, by voltage-controlling a voltage Vac of a filter capacitor C with a value obtained by subtracting an output voltage drop Vz caused by a virtual synchronous impedance Zs from an internal induced voltage Ef of the power conversion system (PCS) being a voltage command value Vac*, a synchronizing power by the virtual synchronous impedance is reproduced.

On the other hand, a voltage amplitude |Vac| needs to coincide with a voltage amplitude command value |Vac|*. Since an amount of the voltage drop by the virtual synchronous impedance is uniquely (univocally) determined by a load current, control that makes the voltage amplitude |Vac| coincide with the voltage amplitude command value |Vac|* according to the voltage drop amount is necessary, and a control system that can quickly respond even at a time of load fluctuation is desirable.

The present invention is an invention that solves the above problem, and an object of the present invention is to provide a control system of a power conversion device (a power conversion system) which is capable of quick response of output voltage amplitude control even at a time of load fluctuation while reproducing the synchronizing power by the virtual synchronous impedance.

A control system of a power conversion system, to solve the above problem, recited in claim1, wherein the power conversion system has a power converter that controls a virtual synchronous generator simulating a synchronous generator and converts DC power of a DC power supply into AC power, wherein an output of the power converter is interconnected to a power grid through an LC filter, the control system comprises: a virtual synchronous impedance compensation block configured to input an output current detection value obtained by detecting an output current of the power converter and a set voltage amplitude command value, simulate a voltage drop generated by flow of the output current of the power converter to a virtual synchronous impedance, and calculate an output voltage command value and an internal induced voltage of the virtual synchronous generator according to the simulated voltage drop; a virtual synchronous generator model configured to determine an angular frequency simulating the synchronous generator; and an output voltage control unit configured to perform control on the basis of the angular frequency determined by the virtual synchronous generator model so that an output voltage of the power conversion system coincides with the output voltage command value calculated by the virtual synchronous impedance compensation block.

As the control system of the power conversion system recited in claim2, in the control system in claim1, the virtual synchronous impedance compensation block is configured to, from the output current detection value Iac, the virtual synchronous impedance Zs and the set voltage amplitude command value |Vac|*, calculate the output voltage command value Vac* and the internal induced voltage Ef of an operating point where an amplitude of the output voltage command value Vac* is |Vac|* and also the internal induced voltage Ef exists on a d-axis, with the internal induced voltage Ef being set as a reference phase.

As the control system of the power conversion system recited in claim3, in the control system in claim1, the virtual synchronous impedance compensation block is configured to, from the output current detection value Iac, the virtual synchronous impedance Zs and the set voltage amplitude command value |Vac|*, calculates the output voltage command value Vac* and the internal induced voltage Ef of an operating point where an amplitude of the output voltage command value Vac* is |Vac|* and also the output voltage command value Vac* exists on a d-axis, with the output voltage command value Vac* being set as a reference phase.

As the control system of the power conversion system recited in claim4, in the control system in claim1, the virtual synchronous impedance compensation block is configured to, with the internal induced voltage Ef being set as a reference phase, calculate a phase difference δ from the output current detection value lac, the virtual synchronous impedance Zs and an internal induced voltage calculated in a previous control cycle, calculate the output voltage command value Vac* by performing a rotational coordinate conversion of the set voltage amplitude command value |Vac|* with the phase difference δ, and calculate the internal induced voltage Ef from the calculated output voltage command value Vac*, the output current detection value Iac and the virtual synchronous impedance Zs.

As the control system of the power conversion system recited in claim5, in the control system in claim1, the virtual synchronous impedance compensation block is configured to, with the internal induced voltage Ef being set as a reference phase, calculate a phase difference δ from the output current detection value lac, the virtual synchronous impedance Zs and the set voltage amplitude command value |Vac|*, calculate the output voltage command value Vac* by performing a rotational coordinate conversion of the set voltage amplitude command value |Vac|* with the phase difference δ, and calculate the internal induced voltage Ef from the calculated output voltage command value Vac*, the output current detection value Iac and the virtual synchronous impedance Zs.

As the control system of the power conversion system recited in claim6, in the control system in claim2, the virtual synchronous impedance compensation block has

a Vz calculation unit configured to calculate voltage drops Vz_d and Vz_q caused by the virtual synchronous impedance Zs by calculating the following expression (1) on the basis of a d-axis current detection value Iac_d and a q-axis current detection value Iac_q each obtained by converting the output current detection value Iac into the d-axis and a q-axis;

(Here, r is a resistance component of Zs, and x is a reactance component of Zs)

a sin−1calculation unit configured to calculate an output voltage phase δ by calculating the following expression (2) on the basis of the voltage drop Vz_q calculated by the Vz calculation unit and the voltage amplitude command value |Vac|*;

a cos calculation unit configured to calculate a cos δ that is a cos component of the output voltage phase δ;

a multiplier configured to, by multiplying the voltage amplitude command value |Vac|* by an output of the cos calculation unit, obtain an output voltage command value Vac_d* of the operating point where the amplitude of the output voltage command value Vac* is |Vac|* and also the internal induced voltage Ef exists on the d-axis; and an adder configured to, by adding the voltage drop Vz_d calculated by the Vz calculation unit to the output voltage command value Vac_d* obtained by the multiplier, obtain the internal induced voltage Ef of the operating point where the amplitude of the output voltage command value Vac* is |Vac|* and also the internal induced voltage Ef exists on the d-axis.

As the control system of the power conversion system recited in claim7, in the control system in claim3, the virtual synchronous impedance compensation block has

a Vz calculation unit configured to calculate voltage drops Vz_d and Vz_q caused by the virtual synchronous impedance Zs by calculating the following expression (1) on the basis of a d-axis current detection value Iac_d and a q-axis current detection value Iac_q each obtained by converting the output current detection value Iac into the d-axis and a q-axis; and

(Here, r is a resistance component of Zs, and x is a reactance component of Zs)

an adder configured to, by adding the voltage drop Vz_d calculated by the Vz calculation unit to the voltage amplitude command value |Vac|*, obtain the internal induced voltage Ef of the operating point where the amplitude of the output voltage command value Vac* is |Vac|* and also the output voltage command value Vac* exists on the d-axis.

As the control system of the power conversion system recited in claim8, in the control system in claim4, the virtual synchronous impedance compensation block has

a Vz calculation unit configured to calculate voltage drops Vz_d and Vz_q caused by the virtual synchronous impedance Zs by calculating the following expression (1) on the basis of a d-axis current detection value Iac_d and a q-axis current detection value Iac_q each obtained by converting the output current detection value Iac into the d-axis and a q-axis;

(Here, r is a resistance component of Zs, and x is a reactance component of Zs)

a buffer configured to temporarily store the internal induced voltage Ef calculated in each control cycle; a tan−1calculation unit configured to obtain the phase difference δ by calculating the following expression (7) on the basis of an internal induced voltage Ef_d (Z−1) calculated in a previous control cycle and stored in the buffer and the voltage drops Vz_d and Vz_q calculated by the Vz calculation unit;

a rotational matrix operation unit configured to calculate the output voltage command value Vac* by performing a rotational coordinate conversion of the voltage amplitude command value |Vac|* with the phase difference δ obtained by the tan−1calculation unit along the following expression (8); and

an adder configured to calculate the internal induced voltage Ef by adding the voltage drop Vz_d calculated by the Vz calculation unit to the output voltage command value Vac* calculated by the rotational matrix operation unit.

As the control system of the power conversion system recited in claim9, in the control system in claim5, the virtual synchronous impedance compensation block has

a Vz calculation unit configured to calculate voltage drops Vz_d and Vz_q caused by the virtual synchronous impedance Zs by calculating the following expression (1) on the basis of a d-axis current detection value Iac_d and a q-axis current detection value Iac_q each obtained by converting the output current detection value Iac into the d-axis and a q-axis;

(Here, r is a resistance component of Zs, and x is a reactance component of Zs)

a tan−1calculation unit configured to obtain the phase difference δ by calculating the following expression (10) on the basis of the voltage amplitude command value |Vac|* and the voltage drops Vz_d and Vz_q calculated by the Vz calculation unit;

a rotational matrix operation unit configured to calculate the output voltage command value Vac* by performing a rotational coordinate conversion of the voltage amplitude command value |Vac|* with the phase difference δ obtained by the tan−1calculation unit; and an adder configured to calculate the internal induced voltage Ef by adding the voltage drop Vz_d calculated by the Vz calculation unit to the output voltage command value Vac* calculated by the rotational matrix operation unit.

A control system of a power conversion system recited in claim10, wherein the power conversion system has a power converter that controls a virtual synchronous generator simulating a synchronous generator and converts DC power of a DC power supply into AC power, wherein an output of the power converter is interconnected to a power grid through an LC filter and an interconnection transformer, the control system comprises: a virtual synchronous impedance compensation block configured to input an output current detection value obtained by detecting an output current of the power converter and a set voltage amplitude command value |V|*, simulate voltage drops generated by flow of the output current of the power converter to a virtual synchronous impedance and the transformer, and calculate an output voltage command value Vac* and an internal induced voltage Ef of the virtual synchronous generator according to the simulated voltage drops; a virtual synchronous generator model configured to determine an angular frequency simulating the synchronous generator; and an output voltage control unit configured to perform control so that an output voltage Vac of the power conversion system coincides with the output voltage command value Vac* calculated by the virtual synchronous impedance compensation block, wherein the virtual synchronous impedance compensation block is configured to, from the output current detection value Iac, the virtual synchronous impedance Zs, an impedance Ztr of the transformer and the set voltage amplitude command value |V|*, calculate the output voltage command value Vac* and the internal induced voltage Ef of an operating point where an amplitude of an interconnection point voltage Vsys of the power grid is |V|* and also the internal induced voltage Ef exists on a d-axis, with the internal induced voltage Ef being set as a reference phase.

As the control system of the power conversion system recited in claim11, in the control system in claim10, the virtual synchronous impedance compensation block has

a Vz calculation unit configured to calculate voltage drops Vz_d and Vz_q caused by the virtual synchronous impedance Zs by calculating the following expression (1) on the basis of a d-axis current detection value Iac_d and a q-axis current detection value Iac_q each obtained by performing a rotational coordinate conversion of the output current detection value Iac with an internal phase that is determined from the angular frequency determined by the virtual synchronous generator model;

(Here, r is a resistance component of Zs, and x is a reactance component of Zs)

a Vtr calculation unit configured to calculate a voltage drop Vtr caused by the transformer by calculating the following expression (11) on the basis of the d-axis current detection value Iac_d and the q-axis current detection value Iac_q each obtained by converting the output current detection value Iac into the d-axis and a q-axis and the impedance Ztr of the transformer;

(Here, Rtr is a resistance component of Ztr, and Xtr is a reactance component of Ztr)

a sin−1calculation unit configured to calculate a grid voltage phase δ by calculating the following expression (12) on the basis of the voltage drop Vz_q calculated by the Vz calculation unit and the voltage amplitude command value |V|*;

a cos calculation unit configured to calculate a cos δ that is a cos component of the grid voltage phase δ;

a multiplier configured to multiply the voltage amplitude command value |V|* by an output of the cos calculation unit;
an adder configured to, by adding the voltage drop Vz_d calculated by the Vz calculation unit to a multiplication output of the multiplier, output an internal induced voltage Ef_d of an operating point where the amplitude of the interconnection point voltage Vsys of the power grid is |V|*, the internal induced voltage Ef exists on the d-axis and also compensation is performed so as to cancel out the voltage drop Vtr due to the transformer; a first subtractor configured to subtract a voltage drop Vtr_d calculated by the Vtr calculation unit from the voltage drop Vz_d calculated by the Vz calculation unit; a second subtractor configured to, by subtracting a subtraction output of the first subtractor from the internal induced voltage Ef_d calculated by the adder, output an output voltage command value Vac_d* of the operating point where the amplitude of the interconnection point voltage Vsys of the power grid is |V|*, the internal induced voltage Ef exists on the d-axis and also compensation is performed so as to cancel out the voltage drop Vtr due to the transformer;
a third subtractor configured to subtract a voltage drop Vtr_q calculated by the Vtr calculation unit from the voltage drop Vz_q calculated by the Vz calculation unit; and
a polarity reverser configured to reverse a polarity of a deviation output of the third subtractor and output an output voltage command value Vac_q*, and
the control of the output voltage control unit is performed on d-q coordinates obtained by performing a rotational coordinate conversion with the internal phase that is determined from the angular frequency determined by the virtual synchronous generator model.

As the control system of the power conversion system recited in claim12, in the control system in claim10, the virtual synchronous impedance compensation block has

a Vz calculation unit configured to calculate voltage drops Vz_d and Vz_q caused by the virtual synchronous impedance Zs by calculating the following expression (1) on the basis of a d-axis current detection value Iac_d and a q-axis current detection value Iac_q each obtained by performing a rotational coordinate conversion of the output current detection value Iac with an internal phase that is determined from the angular frequency determined by the virtual synchronous generator model;

(Here, r is a resistance component of Zs, and x is a reactance component of Zs)

a Vtr calculation unit configured to calculate a voltage drop Vtr caused by the transformer by calculating the following expression (11) on the basis of the d-axis current detection value Iac_d and the q-axis current detection value Iac_q each obtained by converting the output current detection value Iac into the d-axis and a q-axis and the impedance Ztr of the transformer;

(Here, Rtr is a resistance component of Ztr, and Xtr is a reactance component of Ztr)

a first adder configured to add a voltage drop Vtr_d calculated by the Vtr calculation unit to the voltage drop Vz_d calculated by the Vz calculation unit;
a second adder configured to add a voltage drop Vtr_q calculated by the Vtr calculation unit to the voltage drop Vz_q calculated by the Vz calculation unit;
a sin−1calculation unit configured to calculate a grid voltage phase δ by calculating the following expression (16) on the basis of an addition output of the second adder and the voltage amplitude command value |V|;

a cos calculation unit configured to calculate a cos δ that is a cos component of the grid voltage phase δ;

a multiplier configured to multiply the voltage amplitude command value |V|* by an output of the cos calculation unit;
a third adder configured to, by adding an addition output of the first adder to a multiplication output of the multiplier, output an internal induced voltage Ef_d of an operating point where the amplitude of the interconnection point voltage Vsys of the power grid is |V|*, the internal induced voltage Ef exists on the d-axis and also a decrease in the amplitude among the voltage drop due to the transformer is compensated;
a subtractor configured to, by subtracting the voltage drop Vz_d calculated by the Vz calculation unit from the internal induced voltage Ef_d calculated by the third adder, output an output voltage command value Vac_d* of the operating point where the amplitude of the interconnection point voltage Vsys of the power grid is |V|*, the internal induced voltage Ef exists on the d-axis and also the decrease in the amplitude among the voltage drop due to the transformer is compensated; and
a polarity reverser configured to reverse a polarity of the voltage drop Vz_q calculated by the Vz calculation unit and output an output voltage command value Vac_q*, and
the control of the output voltage control unit is performed on d-q coordinates obtained by performing a rotational coordinate conversion with the internal phase that is determined from the angular frequency determined by the virtual synchronous generator model.

(1) According to the inventions described in claims1to9, it is possible to simulate the voltage drop caused by the virtual synchronous impedance and reproduce the synchronizing power while maintaining the amplitude of the output voltage command constant even at a time of load fluctuation.

(2) According to the inventions described in claims3and7, since the output voltage command value Vac* is set as a reference phase, an amount of calculation in the virtual synchronous impedance compensation block is small.

(3) According to the inventions described in claims5and9, in a case where the virtual synchronous impedance is set to such a small value that the error of the phase difference δ does not become a problem, a storage unit (e. g. a buffer) required to temporarily store the internal induced voltage Ef calculated in each control cycle like claim4is not necessary, thereby simplifying the configuration.

(4) According to the inventions described in claims10to12, it is possible to maintain the amplitude of the system voltage (the interconnection point voltage of the power grid) Vsys at the voltage amplitude command value |V|* even at a time of load fluctuation, simulate the voltage drops caused by the virtual synchronous impedance Zs and the impedance Ztr of the interconnection transformer, then reproduce the synchronizing power.

(5) According to the inventions described in claim11, it is possible to calculate the output voltage command value Vac* and the internal induced voltage Ef of the operating point where compensation is performed so as to cancel out the voltage drop due to the interconnection transformer.

(6) According to the inventions described in claim12, it is possible to calculate the output voltage command value Vac* and the internal induced voltage Ef of the operating point where the decrease in the amplitude among the voltage drop due to the interconnection transformer is compensated.

EMBODIMENTS FOR CARRYING OUT THE INVENTION

Embodiments of the present invention will be described below with reference to the drawings. However, the present invention is not limited to the following embodiments.

In the present embodiment, in a PCS (power conversion system) interconnecting a DC power supply such as a storage battery to a system (a grid) through a DC/AC conversion device (a power converter INV), an LC filter and a transformer and particularly having in its control system a virtual synchronous generator model that determines an angular frequency ωr simulating a synchronous generator and a virtual synchronous impedance compensation block that simulates an internal induced voltage Ef and a voltage drop (Vz) caused by a virtual synchronous impedance (Zs) of the synchronous generator, when controlled by voltage control that controls an output voltage of the PCS to a command value, by mathematically obtaining an operating point of a voltage command value Vac* and the internal induced voltage Ef according to the voltage drop (Vz) generated by the virtual synchronous impedance (Zs) by or in the virtual synchronous impedance compensation block, a quick response can be realized even at a time of load fluctuation while reproducing a synchronizing power by the virtual synchronous impedance.

FIG.2shows an example of a general configuration of the control system of the power conversion system according to the present embodiment. InFIG.2, a reference sign1is the DC power supply having, e.g. a storage battery. A reference sign2is the power converter (INV) that converts DC power of the DC power supply1into AC power.

The power converter2is formed by, for instance, bridge-connected IGBTs, and these IGBTs are ON/OFF-controlled by gate signals generated by an after-mentioned PWM unit16.

An AC output side of the power converter2is connected (interconnected) to a power system (or a power grid)5through an LC filter3formed by a reactor Lf and a capacitor Cf and a transformer4(Tr).

A reference sign11is a virtual synchronous impedance compensation block (a Zs compensation block) that inputs an output current detection value Iac obtained by detecting an output current of the power converter2by a current transformer12and a set voltage amplitude command value |Vac|*, simulates a voltage drop Vz generated by flow of the output current of the power converter2to a virtual synchronous impedance Zs, and calculates an output voltage command value Vac* and an internal induced voltage Ef of a virtual synchronous generator according to the simulated voltage drop Vz.

A reference sign13is a virtual synchronous generator model that calculates an electric output (Pe) of the VSG (Virtual Synchronous Generator) model from the internal induced voltage Ef calculated by or in the virtual synchronous impedance compensation block11and the output current detection value Iac and determines an angular frequency ωr simulating a synchronous generator on the basis of a difference (a deviation) between the calculated electric output (Pe) and a set reference power Pref.

A reference sign14is a PCS output voltage control unit (AVR) that generates an output voltage control command Vcmd for performing control so that an output voltage Vac obtained by detecting an output voltage of the PCS (an output voltage of the power converter2) by an instrument transformer15coincides with the output voltage command value Vac* calculated by or in the virtual synchronous impedance compensation block11.

A reference sign16is a PWM unit that generates a gate signal Gate PWM-modulated by the output voltage control command Vcmd generated by or in the PCS output voltage control unit14and a PWM carrier and PWM-controls the power converter2. In a case of synchronous PWM, a PWM carrier having a frequency obtained by multiplying by the angular frequency ωr determined by or in the virtual synchronous generator model13is used. In a case of asynchronous PWM, a PWM carrier having a fixed frequency is used.

Here, inFIG.2, the output current detection value Iac and the output voltage Vac each use a signal obtained by converting three phases u, v and w into a d-axis and a q-axis by a phase obtained by integrating the angular frequency ωr. The output voltage control command Vcmd uses a signal obtained by inverse-dq-converting a d-axis and a q-axis into three phases u, v and w by a phase obtained by integrating the angular frequency ωr.

Details of the virtual synchronous impedance compensation block11are configured as shown in the following each embodiment.

In an embodiment 1, a relationship between the output current detection value Iac, the output voltage command value Vac*, the internal induced voltage Ef, an output voltage phase δ, the voltage amplitude command value |Vac|* and voltage drops Vz_d and Vz_q on a d-axis and a q-axis is shown inFIG.3, with the internal induced voltage Ef being set as a reference phase (on the d-axis).

The virtual synchronous impedance compensation block11in the embodiment 1 calculates, from the output current detection value Iac, the virtual synchronous impedance Zs and the set voltage amplitude command value |Vac|*, the output voltage command value Vac* and the internal induced voltage Ef of an operating point where an amplitude of the output voltage command value Vac* is |Vac|* and also the internal induced voltage Ef exists on the d-axis. The virtual synchronous impedance compensation block11is configured as shown inFIG.4.

InFIG.4, a reference sign20is a Vz calculation unit that calculates the voltage drops Vz_d and Vz_q caused by the virtual synchronous impedance Zs by calculating the following expression (1) on the basis of a d-axis current detection value Iac_d and a q-axis current detection value Iac_q each obtained by converting the output current detection value Iac into the d-axis and the q-axis.

(Here, r is a resistance component of Zs, and x is a reactance component of Zs)

A reference sign21is a sin−1calculation unit that calculates the output voltage phase δ by calculating the following expression (2) on the basis of the voltage drop Vz_q calculated by the Vz calculation unit20and the voltage amplitude command value |Vac|*.

A reference sign22is a cos calculation unit that calculates a cos δ that is a cos component of the output voltage phase δ.

A reference sign23is a multiplier that, by multiplying the voltage amplitude command value |Vac|* by an output of the cos calculation unit22, obtains an output voltage command value Vac_d* of an operating point where the amplitude of the output voltage command value Vac* is |Vac|* and also the internal induced voltage Ef exists on the d-axis.

A reference sign24is a polarity reverser that reverses a polarity of the voltage drop Vz_q calculated by the Vz calculation unit20. An output of the polarity reverser24is output as an output voltage command value Vac_q*.

A reference sign25is an adder that, by adding the voltage drop Vz_d calculated by the Vz calculation unit20to the output voltage command value Vac_d* obtained by the multiplier23, obtains an internal induced voltage Ef_d of an operating point where the amplitude of the output voltage command value Vac* is |Vac|* and also the internal induced voltage Ef exists on the d-axis. Here, an internal induced voltage Ef_q is 0.

In the system configured as above, the PCS output voltage control unit14performs voltage control so that the output voltage Vac (the voltage Vac obtained by detecting a terminal voltage after the LC filter) coincides with the output voltage command value Vac* obtained by subtracting the voltage drop Vz generated by f low of the output current Iac to the virtual synchronous impedance Zs from the internal induced voltage Ef.

When expressing the voltage drop Vz by the virtual synchronous impedance Zs (r and x) and the output current Iac on the d-q coordinates, it becomes the following expression (1) (an expression calculated by the Vz calculation unit20).

From the voltage drop Vz, the operating point where the amplitude of the output voltage command value Vac* is |Vac|* and also the internal induced voltage Ef is positioned on the d-axis can be uniquely (univocally) determined, and it becomes the following expressions (2) to (4).

The above expression (2) can be obtained by the sin−1calculation unit21inFIG.4. The above expression (3) can be obtained by the multiplier23and the polarity reverser24. The above expression (4) can be obtained by the adder25.

In this manner, by sequentially calculating the voltage command value Vac* to be output according to a load current (the output current detection value Iac) and the internal induced voltage Ef by or in the virtual synchronous impedance compensation block11inFIG.4, it is possible to maintain the amplitude of the output voltage command value Vac* at the voltage amplitude command value |Vac|* even at a time of load fluctuation, also simulate the voltage drop Vz caused by the virtual synchronous impedance Zs, then reproduce the synchronizing power.

As described above, according to the embodiment 1, on the coordinates with the internal induced voltage Ef being the reference, by sequentially calculating, according to the load current, the output voltage command value Vac* and the internal induced voltage Ef of the operating point where the amplitude of the output voltage command value Vac* is the voltage amplitude command value |Vac|* and also the internal induced voltage Ef is positioned on the d-axis, it is possible to simulate the voltage drop caused by the virtual synchronous impedance and reproduce the synchronizing power while maintaining the voltage amplitude constant even at a time of load fluctuation.

In an embodiment 2, a relationship between the output current detection value Iac, the output voltage command value Vac*, the internal induced voltage Ef, the output voltage phase δ, the voltage amplitude command value |Vac|* and the voltage drops Vz_d and Vz_q on the d-axis and the q-axis is shown inFIG.5, with the output voltage command value Vac* being set as the reference phase (on the d-axis).

The virtual synchronous impedance compensation block11in the embodiment 2 calculates, from the output current detection value Iac, the virtual synchronous impedance Zs and the set voltage amplitude command value |Vac|*, the output voltage command value Vac* and the internal induced voltage Ef of an operating point where the amplitude of the output voltage command value Vac* is |Vac|* and also the output voltage command value Vac* exists on the d-axis. The virtual synchronous impedance compensation block11is configured as shown inFIG.6.

InFIG.6, the same elements are denoted by the same reference signs as those ofFIG.4. A reference sign26is an adder that, by adding the voltage drop Vz_d calculated by the Vz calculation unit20to the voltage amplitude command value |Vac|*, obtains the internal induced voltage Ef_d of an operating point where the amplitude of the output voltage command value Vac* is |Vac|* and also the output voltage command value Vac* exists on the d-axis.

The voltage drop Vz_q calculated by the Vz calculation unit20is output as the internal induced voltage Ef_q.

Since the output voltage command value Vac* is set on the d-axis, |Vac|* is output as Vac_d*, and the q-axis component Vac_q* is 0.

In the above embodiment 1, the reference phase is the internal induced voltage Ef. However, in the present embodiment 2, as shown inFIG.5, the embodiment 2 is considered with the reference phase being the output voltage command value Vac*. In the same way as the embodiment 1, the voltage drop Vz caused by the virtual synchronous impedance Zs is obtained from the expression (1).

From the voltage drop Vz, the operating point where the amplitude of the output voltage command value Vac* is |Vac|* and also the output voltage command value Vac* is positioned on the d-axis can be uniquely (univocally) determined, and it becomes the following expressions (5) and (6).

Vac_d* and Vac_q* in the expression (5) are output from the virtual synchronous impedance compensation block11inFIGS.2and6, and the expression (6) can be obtained by the adder26inFIG.6.

As described above, according to the embodiment 2, in the same manner as the embodiment 1, it is possible to maintain the amplitude of the output voltage command value Vac* at the voltage amplitude command value |Vac|* even at a time of load fluctuation, also simulate the voltage drop Vz caused by the virtual synchronous impedance Zs, then reproduce the synchronizing power.

Here, in the embodiment 2, since calculation of trigonometric function is not needed, an amount of calculation is smaller than that in the embodiment 1.

In an embodiment 3, a relationship between the output current detection value Iac, the output voltage command value Vac*, the internal induced voltage Ef, the output voltage phase δ, the voltage amplitude command value |Vac|* and the voltage drops Vz_d and Vz_q on the d-axis and the q-axis is shown inFIG.7, with the internal induced voltage Ef being set as the reference phase (on the d-axis).

Here, when calculating the output voltage command value Vac*, as shown inFIG.7A, an internal induced voltage Ef (Z−1) obtained in a previous control cycle is set on the d-axis, and when calculating the internal induced voltage Ef, as shown inFIG.7B, an internal induced voltage Ef in the present control cycle is set on the d-axis.

The virtual synchronous impedance compensation block11in the embodiment 3 calculates a phase difference δ from the output current detection value Iac, the virtual synchronous impedance Zs and the internal induced voltage calculated in the previous control cycle, and calculates the output voltage command value Vac* by performing a rotational coordinate conversion of the set voltage amplitude command value |Vac|* with the phase difference δ, then calculates the internal induced voltage Ef from the calculated output voltage command value Vac*, the output current detection value Iac and the virtual synchronous impedance Zs. The virtual synchronous impedance compensation block11is configured as shown inFIG.8.

InFIG.8, the same elements are denoted by the same reference signs as those ofFIG.4. InFIG.8, a reference sign31is a buffer (Z−1is a unit delay operator) that temporarily stores the internal induced voltage Ef_d calculated by an after-mentioned adder36in each control cycle.

A reference sign32is a subtractor that obtains a difference (a deviation) between an internal induced voltage Ef_d (Z−1) calculated in the previous control cycle and stored in the buffer31and the voltage drop Vz_d calculated by the Vz calculation unit20.

A reference sign33is a subtractor that obtains a difference (a deviation) between a set 0 and the voltage drop Vz_q calculated by the Vz calculation unit20.

A reference sign34is a tan−1calculation unit that obtains the phase difference δ by calculating the following expression (7) on the basis of a difference output (a deviation output) (Ef_d (Z−1)−Vz_d) of the subtractor32and a difference output (a deviation output) (−Vz_q) of the subtractor33.

A reference sign35is a rotational matrix operation unit that calculates the output voltage command values Vac_d* and Vac_q* by performing the rotational coordinate conversion of the voltage amplitude command value |Vac|* with the phase difference δ obtained by the tan−1calculation unit34along the following expression (8).

A reference sign36is an adder that calculates the internal induced voltage Ef_d by adding the voltage drop Vz_d calculated by the Vz calculation unit20to the output voltage command value Vac_d* calculated by the rotational matrix operation unit35.

Ef_d that is an addition output of the adder36is output and stored in the buffer31for calculation in the next control cycle. Here, the internal induced voltage Ef_q approximates to 0.

In the above embodiment 1, the internal induced voltage Ef and the output voltage command value Vac* are obtained at the same time. However, in the present embodiment 3, as shown in the circuit ofFIG.8, the phase difference δ is obtained, as indicated in the following expression (7), by the tan−1calculation unit34from the difference between the internal induced voltage previous value Ef (Z−1) obtained in the previous control cycle and the voltage drop Vz, and the rotational coordinate conversion of the voltage amplitude command value |Vac|* with the phase difference δ is performed, as indicated in the following expression (8), by the rotational matrix operation unit35, then the output voltage command value Vac* is obtained.

The internal induced voltage Ef is indicated by the following expression (9) from the output voltage command value Vac* and the voltage drop Vz.

The above expression (9) is calculated by the adder36.

In the embodiment 3, since the operating point is determined with the internal induced voltage previous value Ef (Z−1) being the reference, a q-axis component may appear in the internal induced voltage Ef. However, since the internal induced voltage Ef is set on the d-axis, the q-axis component approximates to 0. Further, Ef_d is stored in the buffer31for calculation in the next control cycle. Here, an initial value of the buffer31is set to the voltage amplitude command value |Vac|*.

As described above, according to the embodiment 3, by calculating the output voltage command value Vac* using the internal induced voltage previous value Ef (Z−1) of the previous control cycle, it is possible to simulate the voltage drop Vz caused by the virtual synchronous impedance Zs and reproduce the synchronizing power while maintaining the voltage amplitude constant. Because the internal induced voltage previous value Ef (Z−1) of the previous control cycle is used, a response is slow as compared with the embodiments 1 and 2. Further, the internal induced voltage Ef is an approximate value.

In an embodiment 4, a relationship between the output current detection value Iac, the output voltage command value Vac*, the internal induced voltage Ef, the output voltage phase δ, the voltage amplitude command value |Vac|* and the voltage drops Vz_d and Vz_q on the d-axis and the q-axis is shown inFIG.9, with the internal induced voltage Ef being set as the reference phase (on the d-axis). Here, when calculating the output voltage command value Vac*, vectors are shown inFIG.9A, and when calculating the internal induced voltage Ef, vectors are shown inFIG.9B.

The virtual synchronous impedance compensation block11in the embodiment 4 calculates the phase difference δ from the output current detection value Iac, the virtual synchronous impedance Zs and the set voltage amplitude command value |Vac|*, and calculates the output voltage command value Vac* by performing a rotational coordinate conversion of the set voltage amplitude command value |Vac|* with the phase difference δ, then calculates the internal induced voltage Ef from the calculated output voltage command value Vac*, the output current detection value Iac and the virtual synchronous impedance Zs. The virtual synchronous impedance compensation block11is configured as shown inFIG.10.

InFIG.10, the same elements are denoted by the same reference signs as those ofFIG.8. InFIG.10, a reference sign41is a subtractor that obtains a difference (a deviation) between the voltage amplitude command value |Vac|* and the voltage drop Vz_d calculated by the Vz calculation unit20.

A reference sign42is a subtractor that obtains a difference (a deviation) between a set 0 and the voltage drop Vz_q calculated by the Vz calculation unit20.

A reference sign43is a tan−1calculation unit that obtains the phase difference δ by calculating the following expression (10) on the basis of a difference output (a deviation output) (|Vac|*−Vz_d) of the subtractor41and a difference output (a deviation output) (−Vz_q) of the subtractor42.

A reference sign44is a rotational matrix operation unit that calculates the output voltage command values Vac_d* and Vac_q* by performing the rotational coordinate conversion of the voltage amplitude command value |Vac|* with the phase difference δ obtained by the tan−1calculation unit43along the following expression (8).

A reference sign45is an adder that calculates the internal induced voltage Ef_d by adding the voltage drop Vz_d calculated by the Vz calculation unit20to the output voltage command value Vac_d* calculated by the rotational matrix operation unit44. Here, the internal induced voltage Ef_q approximates to 0.

In the above embodiment 3, the previous value of the internal induced voltage Ef is used for the calculation of the phase difference δ. However, in the present embodiment 4, the voltage amplitude command value |Vac|* is used for simplification.

That is, the following expression (10) is calculated by the subtractors41and42and the tan−1calculation unit43, then the phase difference δ is calculated.

The output voltage command values Vac_d* and Vac_q* can be obtained by calculating the expression (8) by the rotational matrix operation unit44in the same manner as the embodiment 3.

The internal induced voltage Ef_d can be obtained by calculating the expression (9) by the adder45in the same manner as the embodiment 3.

Although the phase difference δ has an error as compared with a case, like the embodiment 3, where the phase difference δ is determined by the voltage drop from the internal induced voltage Ef, it is possible to reproduce the synchronizing power while maintaining the voltage amplitude constant.

As compared with the embodiment 3, the present embodiment 4 does not require the buffer31for the internal induced voltage Ef, thereby simplifying the configuration.

It is noted that since the virtual synchronous impedance of the simulated synchronous generator is a parameter in the power converter, it can be freely set without being bound by physical limitations of the synchronous generator. Since it is conceivable that the smaller the virtual synchronous impedance is, the smaller the error of the phase difference δ is, in a case where the virtual synchronous impedance is set to such a small value that the error of the phase difference δ does not become a problem, the manner of the present embodiment 4 can be applied.

FIG.11shows, at an upper side thereof, a configuration of a PCS in which an output of a power converter that converts DC power of a DC power supply such as a storage battery into AC power is interconnected to a power system (a power grid) through an LC filter and an interconnection transformer (Tr).FIG.11also shows, at a lower side thereof, a configuration of a virtual synchronous impedance model.

As shown inFIG.11, when the output of the power converter is interconnected to the power system (the power grid) through the LC filter and the interconnection transformer Tr, a system voltage (voltage at an interconnection point with the power system (the power grid)) Vsys is decreased due to a voltage drop Vtr by the transformer Tr.

When attempting to make a system voltage amplitude |Vsys| coincide with a voltage amplitude command value |V|*, control that makes the system voltage amplitude |Vsys| coincide with the voltage amplitude command value |V|* according to a voltage drop amount is necessary, and a control system that can quickly respond even at a time of load fluctuation is desirable.

Therefore, in an embodiment 5, in a PCS (power conversion system) interconnecting a DC power supply such as a storage battery to a system (a grid) through a DC/AC conversion device (a power converter INV), an LC filter and a transformer and particularly having in its control system a virtual synchronous generator model that determines an angular frequency ωr simulating a synchronous generator and a virtual synchronous impedance compensation block that simulates an internal induced voltage Ef and a voltage drop (Vz) caused by a virtual synchronous impedance (Zs) of the synchronous generator, when controlled by voltage control that controls an output voltage of the PCS to a command value, by mathematically obtaining an operating point of a voltage command value Vac* and the internal induced voltage Ef according to an amount of the voltage drops generated by the virtual synchronous impedance and the transformer by or in the virtual synchronous impedance compensation block, the voltage drop due to the interconnection transformer can be compensated, and a quick response can be realized even at a time of load fluctuation while reproducing a synchronizing power by the virtual synchronous impedance.

FIG.12shows a general configuration of the control system of the power conversion system according to the embodiment 5. The same elements are denoted by the same reference signs as those ofFIG.2. InFIG.12, a reference sign1is the DC power supply having, e.g. a storage battery. A reference sign2is the power converter (INV) that converts DC power of the DC power supply1into AC power.

The power converter2is formed by, for instance, bridge-connected IGBTs, and these IGBTs are ON/OFF-controlled by gate signals generated by an after-mentioned PWM unit16.

An AC output side of the power converter2is connected (interconnected) to a power system (or a power grid)5through an LC filter3formed by a reactor Lf and a capacitor Cf and a transformer4(Tr).

A reference sign11is a virtual synchronous impedance compensation block (a Zs compensation block) that inputs an output current detection value Iac obtained by converting a detection current, which is obtained by detecting an output current of the power converter2by a current transformer12, into a d-axis and a q-axis by an after-mentioned coordinate conversion unit52and a set voltage amplitude command value |V|*, simulates a voltage drop Vz generated by flow of the output current of the power converter2to a virtual synchronous impedance Zs, and calculates an output voltage command value Vac* and an internal induced voltage Ef of a virtual synchronous generator according to the simulated voltage drop Vz.

A reference sign13is a virtual synchronous generator model that calculates an electric output (Pe) of the VSG (Virtual Synchronous Generator) model from the internal induced voltage Ef calculated by or in the virtual synchronous impedance compensation block11and the output current detection value Iac and determines an angular frequency ωr simulating a synchronous generator on the basis of a difference (a deviation) between the calculated electric output (Pe) and a set reference power Pref.

A reference sign14is a PCS output voltage control unit (AVR) that generates a command signal for performing control so that an output voltage detection value Vac obtained by converting a detection voltage, which is obtained by detecting an output voltage of the PCS (an output voltage of the power converter2) by an instrument transformer15, into a d-axis and a q-axis by an after-mentioned coordinate conversion unit53coincides with the output voltage command value Vac* calculated by or in the virtual synchronous impedance compensation block11. The command signal is converted into three phases u, v and w by an after-mentioned coordinate conversion unit54, and a three-phase output voltage control command Vcmd is output.

A reference sign16is a PWM unit that generates a gate signal Gate PWM-modulated by the output voltage control command Vcmd generated by or in the PCS output voltage control unit14and a PWM carrier and PWM-controls the power converter2. In a case of synchronous PWM, a PWM carrier having a frequency obtained by multiplying by the angular frequency car determined by or in the virtual synchronous generator model13is used. In a case of asynchronous PWM, a PWM carrier having a fixed frequency is used.

A reference sign51is an integrator that integrates the angular frequency ωr output from the virtual synchronous generator model13and outputs an internal phase θr.

The coordinate conversion units52,53and54each perform rotational coordinate conversion with the internal phase Gr output from the integrator51.

The virtual impedance model according to the embodiment 5 is shown inFIG.11. In the embodiment 5, a relationship between the output current detection value Iac, the output voltage command value Vac*, the internal induced voltage Ef, the output voltage phase δ, the voltage amplitude command value |V|*, voltage drops Vz_d and Vz_q at the virtual synchronous impedance Zs, the system voltage (the interconnection point voltage) Vsys and voltage drops Vtr_d and Vtr_q due to the interconnection transformer4on the d-axis and the q-axis is shown inFIG.13, with the internal induced voltage Ef being set as a reference phase (on the d-axis).

The virtual synchronous impedance compensation block11in the embodiment 5 is configured as shown inFIG.14.

InFIG.14, a reference sign61is a Vz calculation unit that calculates the voltage drops Vz_d and Vz_q caused by the virtual synchronous impedance Zs by calculating the following expression (1) on the basis of a d-axis current detection value Iac_d and a q-axis current detection value Iac_q each obtained by converting the output current detection value Iac into the d-axis and the q-axis.

(Here, r is a resistance component of Zs, and x is a reactance component of Zs)

A reference sign62is a Vtr calculation unit that calculates the voltage drops Vtr_d and Vtr_q caused by an impedance Ztr of the interconnection transformer4by calculating the following expression (11) on the basis of the d-axis current detection value Iac_d and the q-axis current detection value Iac_q.

(Here, Rtr is a resistance component of Ztr, and Xtr is a reactance component of Ztr)

A reference sign63is a subtractor (a first subtractor) that subtracts the voltage drop Vtr_d calculated by the Vtr calculation unit62from the voltage drop Vz_d calculated by the Vz calculation unit61.

A reference sign64is a subtractor (a third subtractor) that subtracts the voltage drop Vtr_q calculated by the Vtr calculation unit62from the voltage drop Vz_q calculated by the Vz calculation unit61.

A reference sign65is a sin−1calculation unit that calculates the output voltage phase δ by calculating the following expression (12) on the basis of the voltage drop Vz_q calculated by the Vz calculation unit61and the set voltage amplitude command value |V|*.

A reference sign66is a cos calculation unit that calculates a cos δ that is a cos component of the output voltage phase δ.

A reference sign67is a multiplier that multiplies the voltage amplitude command value |V|* by an output of the cos calculation unit66.

A reference sign68is an adder that, by adding the voltage drop Vz_d calculated by the Vz calculation unit61to an output of the multiplier67, outputs an internal induced voltage Ef_d of an operating point where the amplitude of the system voltage (the interconnection point voltage of the power system (the power grid)) Vsys is |V|*, the internal induced voltage Ef exists on the d-axis and also compensation is performed so as to cancel out the voltage drop Vtr due to the transformer4.

A reference sign69is a subtractor (a second subtractor) that, by subtracting a difference output (a deviation output) of the subtractor63from the internal induced voltage Ef_d output from the adder68, outputs an output voltage command value Vac_d* of an operating point where the amplitude of the system voltage (the interconnection point voltage of the power system (the power grid)) Vsys is |V|*, the internal induced voltage Ef exists on the d-axis and also compensation is performed so as to cancel out the voltage drop Vtr due to the transformer4.

A reference sign70is a polarity reverser that reverses a polarity of a difference output (a deviation output) of the subtractor64. An output of the polarity reverser70is output as an output voltage command value Vac_q*. Here, an internal induced voltage Ef_q is 0.

It is noted that a vector “Vz-Vtr” inFIG.13represents a subtraction operation of the subtractor (the first subtractor)63inFIG.14, and vectors “Ef”, “Vz-Vtr” and “Vac*” inFIG.13represent a subtraction operation of the subtractor (the second subtractor)69inFIG.14.

In the system configured as above, the PCS output voltage control unit14performs voltage control so that the output voltage Vac (the voltage Vac obtained by detecting a terminal voltage after the LC filter) coincides with the output voltage command value Vac* obtained by adding the voltage drop generated at the interconnection transformer4to a value obtained by subtracting the voltage drop Vz generated by flow of the output current Iac to the virtual synchronous impedance Zs from the internal induced voltage Ef.

When expressing the voltage drop Vz by the virtual synchronous impedance Zs (r and x) and the output current Iac on the d-q coordinates, it becomes the following expression (1) (an expression calculated by the Vz calculation unit61).

When expressing the voltage drop Vtr estimated by the impedance Ztr (Rtr and Xtr) of the interconnection transformer4and the output current Iac on the d-q coordinates, it becomes the following expression (11).

From the voltage drop Vz, the operating point where the amplitude of the interconnection point voltage Vsys of the power system (the power grid) is |V|* and also the internal induced voltage Ef is positioned on the d-axis can be uniquely (univocally) determined, and it becomes the following expressions (12) to (14).

The above expression (12) can be obtained by the sin−1calculation unit65inFIG.14. The above expression (13) can be obtained by the multiplier67and the adder68. Further, the above expression (14) is clear from a relationship between Ef, Vz_d and Vsys shown in the vector diagram ofFIG.13.

The voltage drop Vtr of the interconnection transformer4is added to the calculated system voltage Vsys as expressed in the following expression (15), then it becomes the output voltage command value Vac*.

The added voltage drop Vtr of the interconnection transformer4is cancelled out by an actually generated voltage drop, so that the system voltage Vsys calculated by the expression (14) appears at an upper side of the interconnection transformer4.

As described above, according to the embodiment 5, by sequentially calculating, according to the load current, the output voltage command value Vac* and the internal induced voltage Ef of the operating point where the amplitude of the system voltage Vsys is the voltage amplitude command value |V|*, the internal induced voltage Ef is positioned on the d-axis and also the voltage drop due to the interconnection transformer is cancelled out, it is possible to simulate the voltage drop caused by the virtual synchronous impedance and reproduce the synchronizing power while maintaining the system voltage amplitude constant even at a time of load fluctuation.

The virtual impedance model according to an embodiment 6 is shown inFIG.15. In the embodiment 6, a relationship between the output current detection value Iac, the output voltage command value Vac*, the internal induced voltage Ef, the output voltage phase δ, the voltage amplitude command value |V|*, the voltage drops Vz_d and Vz_q at the virtual synchronous impedance Zs, the system voltage (the interconnection point voltage) Vsys and the voltage drops Vtr_d and Vtr_q due to the interconnection transformer4on the d-axis and the q-axis is shown inFIG.16, with the internal induced voltage Ef being set as a reference phase (on the d-axis).

In the above embodiment 5, the voltage drop due to the interconnection transformer4is compensated in whole. However, in the present embodiment 6, only an amount of a drop of the system voltage (Vsys) amplitude from the voltage amplitude command value |V|* is compensated. When viewed from the system (the grid) (i.e. from the Vsys side), in the embodiment 5, as shown inFIG.11, it looks as if only the internal induced voltage Ef and the virtual synchronous impedance Zs exist (because the voltage drop due to the interconnection transformer4is cancelled out). on the other hand, in the embodiment 6, as shown inFIG.15, the impedance of the interconnection transformer4can also been seen, which is a different point from the embodiment 5.

The virtual synchronous impedance compensation block11in the embodiment 6 is configured as shown inFIG.17. InFIG.17, the same elements are denoted by the same reference signs as those ofFIG.14.

A reference sign81is an adder (a first adder) that adds the voltage drop Vtr_d calculated by the Vtr calculation unit62to the voltage drop Vz_d calculated by the Vz calculation unit61.

A reference sign82is an adder (a second adder) that adds the voltage drop Vtr_q calculated by the Vtr calculation unit62to the voltage drop Vz_q calculated by the Vz calculation unit61.

A reference sign83is a sin−1calculation unit that calculates the output voltage phase δ by calculating the following expression (16) on the basis of an output of the adder82and the set voltage amplitude command value |V|*.

A reference sign84is a cos calculation unit that calculates a cos δ that is a cos component of the output voltage phase δ.

A reference sign85is a multiplier that multiplies the voltage amplitude command value |V|* by an output of the cos calculation unit84.

A reference sign86is an adder (a third adder) that, by adding an addition output of the adder81to an output of the multiplier85, outputs an internal induced voltage Ef_d of an operating point where the amplitude of the system voltage (the interconnection point voltage of the power system (the power grid)) Vsys is |V|*, the internal induced voltage Ef exists on the d-axis and also a decrease in the amplitude among the voltage drop Vtr due to the transformer4is compensated.

A reference sign87is a subtractor that, by subtracting the voltage drop Vz_d calculated by the Vz calculation unit61from the internal induced voltage Ef_d output from the adder86, outputs an output voltage command value Vac_d* of an operating point where the amplitude of the system voltage (the interconnection point voltage of the power system (the power grid)) Vsys is |V|*, the internal induced voltage Ef exists on the d-axis and also the decrease in the amplitude among the voltage drop Vtr due to the transformer4is compensated.

A reference sign88is a polarity reverser that reverses a polarity of the voltage drop Vz_q output from the Vz calculation unit61. An output of the polarity reverser88is output as an output voltage command value Vac_q*. Here, an internal induced voltage Ef_q is 0.

In the system configured as above, in the same manner as the embodiment 5, the voltage drop Vz by the virtual synchronous impedance Zs is obtained from the the following expression (1). Also, in the same manner as the embodiment 5, the voltage drop Vtr due to the interconnection transformer4is obtained from the following expression (11).

From the voltage drops Vz and Vtr, the operating point where the system voltage (Vsys) amplitude is |V|* and also the internal induced voltage Ef is positioned on the d-axis can be uniquely (univocally) determined, and it becomes the following expressions (16) to (19).

The above expression (16) can be obtained by the sin−1calculation unit83inFIG.17. The above expression (17) can be obtained by the adder86inFIG.17. The above expression (18) is clear from a relationship between vectors Vsys, Ef, Vz and Vtr inFIG.16. Further, the above expression (19) is clear from a relationship between vectors Ef, Vz and Vac* inFIG.16.

As described above, according to the embodiment 6, by sequentially calculating, according to the load current, the output voltage command value Vac* and the internal induced voltage Ef of the operating point where the amplitude of the system voltage Vsys is the voltage amplitude command value |V|*, the internal induced voltage Ef is positioned on the d-axis and also the decrease in the amplitude among the voltage drop due to the interconnection transformer is compensated, it is possible to simulate the voltage drop caused by the virtual synchronous impedance and reproduce the synchronizing power while maintaining the system voltage amplitude constant even at a time of load fluctuation.