Integrated circuit devices

An integrated circuit device includes a fin-type active area extending on a substrate in a first direction, a first gate line and a second gate line extending on the fin-type active area in parallel to each other in a second direction, which is different from the first direction, a first insulating capping layer covering an upper surface of the first gate line and extending in parallel to the first gate line, a second insulating capping layer covering an upper surface of the second gate line and extending in parallel to the second gate line, wherein a height of the first gate line and a height of the second gate line are different from each other.

BACKGROUND

The inventive concepts relate to integrated circuit devices, and more particularly, to integrated circuit devices including a field effect transistor.

With the development of electronic technologies, integrated circuit devices have been rapidly downscaled. Semiconductor devices can benefit from both a high operating speed and an operational accuracy, and thus, research into optimizing the structure of transistors included in the semiconductor devices has been conducted.

As the size of transistors, decreases, a reduced gate length of the transistors can cause threshold voltage variations among a plurality of transistors performing the same function.

SUMMARY

The inventive concepts provide integrated, circuit devices capable of maintaining desired performance by providing a desired threshold voltage without threshold voltage variation among a plurality of transistors performing the same function, even if sizes of the transistors are reduced according to down-scaling of the integrated circuit devices. Thus, such integrated circuit devices may maintain desired performance with transistors having reduced gate lengths.

According to an aspect of the inventive concepts, an integrated circuit device may include a fin-type active area extending on a substrate in a first direction, a first gate line and a second gate line extending on the fin-type active area in parallel to each other in a second direction, which is different from the first direction, a first insulating capping layer covering an upper surface of the first gate line and extending in parallel to the first gate line, a second insulating capping layer covering an upper surface of the second gate line and extending in parallel to the second gate line, wherein a height of the first gate line and a height of the second gate line are different from each other.

According to another aspect of the inventive concepts, an integrated circuit device may include a fin-type active area extending on a substrate in a first direction and including a fin separating recess on an upper surface of the fin-type active area, and a first fin portion and a second fin portion at opposing sides of the fin separating recess, with the fin separating recess interposed between the first fin portion and the second fin portion, a fin separating insulating layer in the fin separating recess, and a plurality of first gate structures extending on the first fin portion in parallel to one another in a second direction that crosses the first direction, wherein each of the plurality of first gate structures includes a first gate line extending in the second direction and a first insulating capping layer on an upper surface of the first gate line and extending in parallel to the first gate line, and the first gate lines of two adjacent first gate structures from among the plurality of first gate structures have different heights.

According to another aspect of the inventive concepts, an integrated circuit device may include a substrate, a fin-type active area on the substrate, wherein the fin-type active area is divided into a first portion and a second portion by a fin separating recess, and a plurality of first gate structures on the first portion of the fin-type active area, respective ones of the plurality of first gate structures comprising a first gate line and a first capping layer on the first gate line. A combined height of the first gate line and the first capping layer of each of the first gate structures may be substantially the same. The first gate line of a first gate structure of the plurality of first gate structures that is nearest the fin separating recess may have a first gate line height that is different than a first gate line height of at least one other first gate structure of the plurality of first gate structures.

DETAILED DESCRIPTION

FIGS. 1A through 1Care views for describing integrated circuit devices according to embodiments of the inventive concepts, whereinFIG. 1Ais a layout diagram of the integrated circuit device100according to the embodiments of the inventive concepts,FIG. 1Bis a cross-sectional view taken along a line B-B′ ofFIG. 1A, andFIG. 1Cis a cross-sectional view taken along lines C1-C1′ and C2-C2′ ofFIG. 1A.

Referring toFIGS. 1A through 1C, the integrated circuit device100may include a substrate110having a fin-type active area FA extending in a first direction (e.g., an X direction).

The fin-type active area FA may protrude upwards from a device isolation layer112as a fin shape, in a direction (e.g., a Z direction) that is perpendicular to a main surface110M of the substrate110. InFIG. 1B, a level of a bottom surface of the fin-type active area FA is indicated as a dotted line BL. The level BL of the bottom surface of the fin-type active area FA may be substantially the same as a level of the main surface110M of the substrate110.

The fin-type active area FA includes a channel area CH in an upper portion thereof. On the substrate110, a bottom side wall of the fin-type active area FA may be covered by the device isolation layer112.

In some embodiments, the channel area CH of the fin-type active area FA may include a single material. For example, all areas of the fin-type active area FA, including the channel area CH, may include Si. In other embodiments, some areas of the fin-type active area FA may include Ge, and other areas of the fin-type active area FA may include Si.

A plurality of gate insulating spacers124defining a plurality of gate spaces OS may be formed on the fin-type active area FA on the substrate110.

An interfacial layer116covering the channel area CH of the fin-type active area. FA may be formed in each of the plurality of gate spaces GS. A gate dielectric layer118, a gate line GL, and an insulating capping layer CA may be sequentially stacked on the interfacial layer116in each of the plurality of gate spaces GS. The gate dielectric layer118, the gate line GL, and the insulating capping layer CA may extend in a second direction (e.g., a Y direction) that crosses the first direction (e.g., the X direction). The gate line GL and the insulating capping layer CA in one gate space GS may form one gate structure GST.

FIGS. 1A through 1Cillustrate that two gate spaces GS are provided on the fin-type active area A. However, the present inventive concepts are not limited thereto. Three or more gate spaces GS extending in parallel to one another may be provided on the fin-type active area FA, and each of the plurality of gate spaces GS may have a structure in which the interfacial layer116, the gate dielectric layer118, the gate line GL, and the insulating capping layer CA are sequentially stacked.

Heights H10of the plurality of gate spaces (IS provided on the fin-type active area FA may be the same or substantially the same. In this specification, unless otherwise defined, “the height of the gate space GS” denotes a size of the gate space GS from an upper surface of the fin-type active area FA in a direction (e.g., the Z direction) perpendicular to the main surface110M of the substrate110.

The interfacial layer116may be formed by oxidizing a surface of the fin-type active area FA in the gate space GS. The interfacial layer116may cure interfacial defects between the fin-type active area FA and the gate dielectric layer118. In some embodiments, the interfacial layer116may be omitted. In some embodiments, the height H10of the gate space GS may include the cumulative height of the components of the gate space GS, such as the gate dielectric layer118, the gate line GL, the insulating capping layer CA, and the interfacial layer116, if present, on the upper surface of the fin-type active area FA.

The gate dielectric layer118and the gate line GL may extend in the gate space GS to cover the upper surface and both side walls of the fin-type active area FA, and an upper surface of the device isolation layer112. A plurality of transistors may be formed at points at which the fin-type active area FA and a plurality of gate lines GL cross each other.FIGS. 1A through 1Cillustrate a first transistor TR11including a first gate line GL11from among the plurality of gate lines GL, and a second transistor TR12including a second gate line GL12from among the plurality of gate lines GL. Each of the first and second transistors TR11and TR12may include a metal oxide semiconductor (MOS) transistor having a three-dimensional structure in which channels are formed at the upper surface and the both side walls of the fin-type active area FA.

The plurality of insulating capping layers CA may cover upper surfaces of the plurality of gate lines GL in the plurality of gate spaces GS. The plurality of insulating capping layers CA may extend in parallel to the plurality of gate lines GL in the second direction (e.g., the Y direction). A first insulating capping layer CA11from among the plurality of insulating capping layers CA may cover the upper surface of the first gate line GL11and may extend in parallel to the first gate line GL11. A second insulating capping layer CA12may cover the upper surface of the second gate line GL12and may extend in parallel to the second gate line GL12. Both side walls of each of the interfacial layer116, the gate dielectric layer118, the gate line GL, and the insulating capping layer CA filling the gate space GS may be covered by the gate insulating spacer124.

Two adjacent gate lines GL from among the plurality of gate lines GL may have different heights from each other. In some embodiments, a height H11A of the first gate line GL11may be greater than a height H12A of the second gate line GL12, and a height H11B of the first insulating capping layer CA11may be less than a height H12B of the second insulating capping layer CA12, as illustrated inFIGS. 1B and 1C. That is, there is a height difference ΔH1between the first gate line GL11and the second gate line GL12.

A sum of the height H11A of the first gate line GL11and the height H11B of the first insulating capping layer CA11may be the same or substantially the same as a sum of the height H12A of the second gate line GL12and the height H12B of the second insulating capping layer CA12. However, the structure illustrated inFIGS. 1B and 1Cis only an example, and the structure may be modified or changed in various ways within the technical scope of the present inventive concepts.

In other embodiments, the height H11A of the first gate line GL11may be less than the height H12A of the second gate line GL12, and the height H11B of the first insulating capping layer CA11may be greater than the height H12B of the second insulating capping layer CA12. In this specification, unless otherwise defined, the height of the gate line GL denotes a height of the gate line GL on the upper surface of the fin-type active area FA. Also, unless otherwise defined, the height of the insulating capping layer CA denotes a height of the insulating capping layer CA on the upper surface of the fin-type active area FA.

The substrate110may include a semiconductor, such as, for example, Si or Ge, and/or a compound semiconductor, such as, for example, SiGe, SiC, GaAs, InAs, and/or InP. In some embodiments, the substrate110may include at least one of a groups III-V material and a group IV material. The groups III-V material may include a binary, ternary, or tetra compound including at least one group III element and at least one group V element. The groups III-V material may include a compound including at least one of, for example, In, Ga, and Al, as a group III element, and at least one of, for example, As, P, and Sb, as a group V element. For example, the groups III-V material may be selected from InP, InzGa1-zAs (0≤z≤1), and AlzGa1-zAs (0≤z≤1). The binary compound may include, for example, any one of InP, GaAs, InAs, InSb, and/or GaSb. The ternary compound may include, for example, any one of InGaP, InGaAs, AlInAs, InGaSb, GaAsSb, and/or GaAsP. The group IV material may include Si or Ge. However, the groups III-IV material and the group IV material which may be included in the integrated circuit device100according to the present inventive concepts are not limited thereto. The groups III-V material, and the group IV material, such as Ge, may be used as a channel material included in a transistor having a high speed and a low power consumption.

A high performance complementary metal-oxide semiconductor (CMOS) may be manufactured by using a semiconductor substrate including, for example, GaAs, a groups III-V material having a higher electron mobility than a material of a Si substrate, and a semiconductor substrate including, for example, Ge, a semiconductor material having a higher hole mobility than the material of the Si substrate. In some embodiments, when an n-channel MOS (NMOS) transistor is formed on the substrate110, the substrate110may include any one of the groups III-V material exemplified above. In other embodiments, when a p-channel MOS (PMOS) transistor is formed on the substrate110, at least a portion of the substrate110may include Ge. As another example, the substrate110may have a silicon on insulator (SOI) structure. The substrate110may include a conductive area, for example, a well doped with impurities, and/or a structure doped with impurities.

The device isolation layer112may be formed by a deposition process or a coating process. In some embodiments, the device isolation layer112may include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a combination thereof. In some embodiments, the device isolation layer112may include an insulating liner (not shown) including a thermal oxide layer, a nitride layer, and/or polysilicon, and a burying insulating layer (not shown) on the insulating liner. In some embodiments, the device isolation layer112may include an oxide layer formed by a flowable chemical vapor deposition (FCVD) process or a spin coating process. For example, the device isolation layer112may include fluoride silicate glass (FSG), uncoped silicate glass (USG), boro-phospho-silicate glass (BPSG), phospho-silicate glass (PSG), flowable oxide (FOX), plasma enhanced tetra-ethyl-ortho-silicate (PE_TEOS), and/or tonen silazene (TOSZ). However, the device isolation layer112is not limited thereto.

The gate insulating spacer124may include a silicon nitride layer, a SiOCN layer, a SiCN layer, or a combination thereof. In this specification, the “silicon nitride layer” may denote a Si3N4layer. “SiOCN” may denote a material containing Si, O, C, and N. “SiCN” may denote a material containing Si, C, and N. The gate insulating spacer124may include a single layer including any one selected from the exemplified materials, or multiple layers in which a plurality of different material layers are sequentially stacked.

Each of a plurality of interfacial layers116may be obtained by oxidizing a partial surface of the fin-type active area FA. The plurality of interfacial layers116may prevent interfacial defects between the fin-type active area FA and the gate dielectric layer113. In some embodiments, the plurality of interfacial layers116may include a low dielectric material layer having a dielectric constant that is equal to or lower than 9. For example, the plurality of interfacial layers116may include a silicon oxide layer, a silicon oxynitride layer, a Ga oxide layer, a Ge oxide layer, or a combination thereof. In other embodiments, the plurality of interfacial layers116may include a silicate, or a combination of a silicate and the low dielectric material layer exemplified above.

A plurality of gate dielectric layers118may include a silicon oxide layer, a high dielectric layer, or a combination thereof. The high dielectric layer may include a material having a higher dielectric constant than a material of the silicon oxide layer. For example, the gate dielectric layer118may have a dielectric constant of about 10 to about 25. The high dielectric layer may include a material selected from hafnium oxide, hafnium oxynitride, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, and a combination thereof. However, materials included in the high dielectric layer are not limited thereto. The gate dielectric layer118may be formed by an atomic layer deposition (ALD) process, a chemical vapor deposition (CVD) process, or a physical vapor deposition (PVD) process. The gate dielectric layer118may be formed to cover a bottom surface and both side walls of the gate line CL.

Each of the plurality of gate lines CL may extend on the gate dielectric layer118in a direction that crosses the fin-type active area FA to cover an upper surface and both side walls of each of fin-type active areas FA.

The plurality of gate lines GL may include a metal containing layer for adjusting a work function. In some embodiments, the plurality of gate lines GL may further include a gap-filling metal containing layer that fills a space formed on the metal containing layer for adjusting a work function. In some embodiments, each of the plurality of gate lines GL may have a structure in which a metal nitride layer, a metal layer, a conductive capping layer, and/or a gap-filling metal layer are sequentially stacked. Each of the metal nitride layer and the metal layer may include at least one metal selected from Ti, W, Ru, Nb, Mo, Ni, Co, Pt, Yb, Tb, Dy, Er, and/or Pd. Each of the metal nitride layer and the metal layer may be firmed by an ALD process, a metal organic ALD (MOALD) process, or a metal organic CVD (MOCVD) process. The conductive capping layer may serve as a protection layer for preventing oxidization of a surface of the metal layer. Also, the conductive capping layer may serve as a wetting layer for making deposition easier when another conductive layer is deposited on the metal layer. The conductive capping layer may include a metal nitride, for example, TiN, TaN, or a combination thereof, but is not limited thereto. The gap-filling metal layer may extend on the conductive capping layer. The gap-filling metal layer may include a W layer. The gap-filling metal layer may be formed, by an ALD process, a CVD process, or a PVD process. The gap-filling metal layer may bury a recessed space, formed due to a step difference portion on an upper surface of the conductive capping layer, without a void. In some embodiments, the plurality of gate lines GL may include a stack of TiAlC/TiN/W, a stack of TiN/TaN/TiAlC/TiN/W, and/or a stack of TiN/TaN/TiN/TiAlC/TiN/W. In those stacks, the TiAlC layer or the TiN layer may serve as the metal containing layer for adjusting a work function.

The plurality of insulating capping layers CA may include a silicon nitride layer, a SiOCN layer, a SiCN layer, or a combination thereof. The plurality of insulating capping layers CA may include a single layer including any one material selected from the materials exemplified above, or multiple layers in which a plurality of different material layers are sequentially stacked.

A plurality of source/drain areas130at both sides of the plurality of gate lines GL may be formed on the fin-type active area FA. The plurality of source/drain areas130may be arranged such that each of the plurality of source/drain areas130is arranged between respective ones of the plurality of gate lines GL.

The source/drain area130may include a semiconductor layer epitaxially grown from the fin-type active area FA. In some embodiments, the source/drain area130may have an embedded SiGe structure including a plurality of SiGe layers epitaxially grown. The plurality of SiGe layers may have different Ge contents. In some embodiments, the source/drain area130may include an epitaxially grown Si layer and/or a epitaxially grown SiC layer.

An inter-gate insulating layer132may be formed between respective ones of the plurality of gate lines GL. The inter-gate insulating layer132may be formed between two adjacent gate lines GL to cover the source/drain area130. The inter-gate insulating layer132may include a silicon oxide layer, but is not limited thereto. In some embodiments, a conductive contact plug (not shown) may be provided to penetrate the inter-gate insulating layer132and be connected to the source/drain area130.

FIGS. 2A through 2Gare views for describing integrated circuit devices100A,100B,100C,100D,100E,100F, and100G according to other embodiments of the inventive concepts.FIGS. 2A through 2Gare cross-sectional views for describing various modified embodiments of the plurality of gate lines GL and the plurality of insulating capping layers CA included in the gate structure GST of the integrated circuit device100illustrated inFIGS. 1A through 1C. Sectional components illustrated inFIGS. 2A through 2Gmay correspond to sectional components taken along the line B-B′ ofFIG. 1A. InFIGS. 2A through 2G, like reference numerals refer to the like elements inFIGS. 1A through 1C, and their detailed descriptions will be omitted.

Referring toFIG. 2A, in the integrated circuit device100A, the first gate line GL11may include a first metal containing layer MA11and a second metal containing layer MB11. The second gate line GL12may include a first metal containing layer MA12and a second metal containing layer MB12.

Each of the first metal containing layer MA11and the second metal containing layer MB11included in the first gate line GL11may contact the first insulating capping layer CA11. Each of the first metal containing layer MA12and the second metal containing layer MB12included in the second gate line GL12may contact the second insulating capping layer CA12.

The first metal containing layer MA11included in the first gate line GL11and the first metal containing layer MA12included in the second gate line GL12may include the same material. However, a height of the first metal containing layer MA11may be greater than a height of the first metal containing layer MA12.

The second metal containing layer MB11included in the first gate line GL11and the second metal containing layer MB12included in the second gate line GL12may include the same material. However, a height of the second metal containing layer MB11may be greater than a height of the second metal containing layer MB12.

The first metal containing layers MA11and MA12may adjust a work function. The second metal containing layers MB11and MB12may fill a recessed space formed on the first metal containing layers MA11and MA12, respectively. In some embodiments, the first metal containing layers MA11and MA12may include a metal, such as Ti, Ta, Al, or a combination thereof. In some embodiments, the first metal containing layers MA11and MA12may include a Ti layer, a TiN layer, a TiON layer, a TiO layer, a Ta layer, a TaN layer, a TaON layer, an oxygen-doped TiAlN (hereinafter, referred to as “TiAlN(O)”) layer, an oxygen-doped TaAlN (hereinafter, referred to as “TaAlN(O)”) layer, or a combination thereof. In some embodiments, the first metal containing layers MA11and MA12may include a single layer or multiple layers. When the first metal containing layers MA11and MA12include multiple layers, the first metal containing layer MA11and the first metal containing layer MA12may have the same stack structure.

The second metal containing layers MB11and MB12may include an upper work function adjustment layer, a conductive barrier layer, a gap-filling metal layer, or a combination thereof. The upper work function adjustment layer may include TiAl, TiAlN, TiC, TaC, HfSi, or a combination thereof, but is not limited thereto. The conductive barrier layer may include a metal nitride, for example, TIN, TaN, or a combination thereof, but is not limited thereto. The gap-filling metal layer may be formed to fill a recessed space on the conductive barrier layer. The gap-filling metal layer may include to W layer. Each of the upper work function adjustment layer, the conductive barrier layer, and the gap-filling metal layer may be formed by an ALD process, a CVD process, or a PVD process. In some embodiments, at least one of the upper work function adjustment layer, the conductive barrier layer, and the gap-filling metal layer may be omitted. In some embodiments, the second metal containing layers MB11and MB12may include a single layer or multiple layers. When the second metal containing layers MB11and MB12include multiple layers, the second metal containing layer MB11and the second metal containing layer MB12may have the same stack structure.

Referring toFIG. 2B, a first gate line GL12and a second gate line GL22of the integrated circuit device100B may have substantially the same structure as the first gate line GL11and the second gate line BL12of the integrated circuit device100A illustrated inFIG. 2A. However, the first gate line GL21of the integrated circuit device100B further includes a first conductive barrier layer MA21and the second gate line GL22of the integrated circuit device100B further includes a second conductive barrier layer MA22.

The first conductive barrier layer MA21of the first gate line GL21may be interposed between the gate dielectric layer118and the first metal containing layer MA11, and the second conductive barrier layer MA22of the second gate line GL22may be interposed between the gate dielectric layer118and the first metal containing layer MA12.

The first conductive barrier layer MA21and the second conductive barrier layer MA22may prevent diffusion of atoms included in the first gate line GL21and the second gate line GL22into the gate dielectric layer118. Each of the first conductive barrier layer MA21and the second conductive barrier layer MA22may include at least one metal selected from Ti, Ta, W, Ru, Nb, Mo, and Hf, or a metal nitride thereof. The first conductive barrier layer MA21and the second conductive barrier layer MA22may include the same material. The first conductive barrier layer MA21and the second conductive barrier layer MA22may have a thickness of dozens of Å. In some embodiments, the first conductive barrier layer MA21and the second conductive barrier layer MA22may include a single layer including a single metal layer or a single metal nitride layer. In other embodiments, the first conductive barrier layer MA21and the second conductive barrier layer MA22may include multiple layers including a plurality of metal layers and/or metal nitride layers.

The first conductive barrier layer MA21may contact the first insulating capping layer CA11. The second conductive barrier layer MA22may contact the second insulating capping layer CA12.

The first conductive barrier layer MA21and the second conductive barrier layer MA22may include the same material. In some embodiments, the first conductive upper barrier layer MAGI and the second conductive upper barrier layer MA22may include a single layer or multiple layers. When each of the first conductive barrier layer MA21and the second conductive barrier layer MA22includes multiple layers, the first conductive harrier layer MA21and the second conductive barrier layer MA22may have the same stack structure. However, a height of the first conductive harrier layer MA21may be greater than a height of the second conductive barrier layer MA22.

Referring toFIG. 2C, a first gate line GL31and a second gate line GL32of the integrated circuit device100C have substantially the same structure as the first gate line GL11and the second gate line GL12of the integrated circuit device100A illustrated inFIG. 2A. However, the first gate line GL31may include a first conductive harrier layer MA31, a first metal containing layer MB31, and a second metal containing layer MC31. Also, the second gate line GL32may include a second conductive barrier layer MA32, a first metal containing layer MB32, and a second metal containing layer MC32.

The first conductive barrier layer MA31and the second conductive barrier layer MA32may have substantially the same structure as the first conductive barrier layer MA21and the second conductive barrier layer MA22described with reference toFIG. 2B. However, the first conductive barrier layer MA31included in the first gate line GL31may not contact the first insulating capping layer CA11. In the first gate line GL31, the first conductive barrier layer MA31and the first insulating capping layer CA11may be apart from each other with the first metal containing layer MB31interposed therebetween.

The first metal containing layer MB31and the second metal containing layer MC31included in the first gate line GL31may have substantially the same structure as the first metal containing layer MA11and the second metal containing layer MB11described with reference toFIG. 2A. However, an upper portion31T of the second metal containing layer MC31included in the first gate line GL31may have a shape, a width of which increases as the upper portion31T of the second metal containing layer MC31is nearer to the first insulating capping layer CA11from the substrate110. Also, an upper portion of the first metal containing layer MB31included in the first gate line GL31may have an angled shape that bends towards the gate dielectric layer118to overlap the first conductive barrier layer MA31included in the first gate line GL31between the first conductive barrier layer MA31and the first insulating capping layer CA11. The angle of the upper portion of the first metal containing layer MB31included in the first gate line GL31may follow the increasing width of the upper portion31T or the second metal containing layer MC31.

The first metal containing layer MB32and the second metal containing layer MC32included in the second gate line GL32may have substantially the same structure as the first metal containing layer MA12and the second metal containing layer MB12described with reference toFIG. 2A.

Referring toFIG. 2D, a first gate line GL41and a second gate line GL42of the integrated circuit device100D may have substantially the same structure as the first gate line GL31and the second gate line GL32of the integrated circuit device100C, illustrated inFIG. 2C. However, the first gate line GL41may further include a first conductive upper barrier layer MD31interposed between the first metal containing layer MB31and the second metal containing layer MC31, and the second gate line GL42may further include a second conductive upper barrier layer MD32interposed between the first metal containing layer MB32and the second metal containing layer MC32.

The first conductive upper barrier layer MD31and the second conductive upper barrier layer MD32may have substantially the same structure as the first conductive barrier layer MA21and the second conductive barrier layer MA22, respectively, described with reference toFIG. 2B.

The first conductive upper barrier layer MD31may contact the first insulating capping layer CA11. The second conductive upper barrier layer MD32may contact the second insulating capping layer CA12.

The first conductive upper barrier layer MD31and the second conductive upper barrier layer MD32may include the same material. In some embodiments, the first conductive upper barrier layer MD31and the second conductive upper barrier layer MD32may include a single layer or multiple layers. When each of the first conductive upper barrier layer MD31and the second conductive upper barrier layer MD32includes multiple layers, the first conductive upper barrier layer MD31and the second conductive upper barrier layer MD32may have the same stack structure. However, a height of the first conductive upper barrier layer MD31may be greater than a height of the second conductive upper barrier layer MD32.

Referring toFIG. 2E, a first gate line GL51and a second gate line GL52of the integrated circuit device100E may have substantially the same structure as the first gate line GL31and the second gate line GL32of the integrated circuit device1000illustrated inFIG. 2C.

However, the first gate line GL51may contact a first insulating capping layer CA51at a first boundary surface CS1which is concave downward. Also, the second gate line GL52may contact a second insulating capping layer CA52at a second boundary surface CS2which is concave downward. A height of the first boundary surface CS1may be greater than a height of the second boundary surface CS2. Thus, a distance from the fin-type active area FA to the first boundary surface CS1may be greater than a distance from the fin-type active area FA to the second boundary surface CS2.

The first gate line GL51may provide the concave first boundary surface CS1, since the first gate line GL51may have an upper surface that is concave downward such that a height of the first gate line GL51decreases as the first gate line G51is nearer to the second metal containing layer MC31from the insulating spacer124. The first insulating capping layer CA51may contact the upper surface of the first gate line GL51, which may be concave downward, and may have a bottom surface that is convex downward, to correspond to the shape of the upper surface of the first gate line GL51. The first insulating capping layer CA51may have substantially the same structure as the first insulating capping layer CA11described with reference toFIGS. 1A through 1C.

The second gate line GL52may provide the concave second boundary surface CS2, since the second gate line GL52may have an upper surface that is concave downward such that a height of the second gate line GL52decreases as the second gate line G52is nearer to the second metal containing layer MC32from the insulating spacer124. The second insulating capping layer CA52may contact the upper surface of the second gate line GL52, which may be concave downward, and may have a bottom surface that is convex downward, to correspond to the shape of the upper surface of the second gate line GL52. The second insulating capping layer CA52may have substantially the same structure as the second insulating capping layer CA12described with reference toFIGS. 1A through 1C.

Referring toFIG. 2F, a first gate line GL61and a second gate line GL62of the integrated circuit device100F may have substantially the same structure as the first gate line GL31and the second gate line GL32of the integrated circuit device1000illustrated InFIG. 2C.

However, the first gate line GL61may include a first conductive barrier layer MA61, a first metal containing layer MB61, and a second metal containing layer MC61. Also, the second gate line GL62may include a second conductive barrier layer MA62, a first metal containing layer MB62, and a second metal containing layer MC62.

In the first gate line GL61, the second metal containing layer MC61may include a first protrusion portion PR1that may protrude upwards from an upper surface of the first metal containing layer MB61, in the second gate line GL62, the second metal containing layer MC62may include a second protrusion portion PR2that may protrude upwards from an upper surface of the first metal containing layer MB62. A height of the first protrusion portion PR1may be greater than a height of the second protrusion portion PR2. Thus, a distance from the fin-type active area FA to the first protrusion portion PR1, may be greater than a distance from the fin-type active area FA to the second protrusion portion PR2.

More detailed structures of the first conductive barrier layer MA61, the first metal containing layer MB61, and the second metal containing layer MC61included in the first gate line GL61may be substantially the same as the detailed structures of the first conductive barrier layer MA31, the first metal containing layer MB31, and the second metal containing layer MC31described with reference toFIG. 2CMore detailed structures of the second conductive barrier layer MC62, the first metal containing layer MB62, and the second metal containing layer MC62included in the second gate line GL62may be substantially the same as the detailed structure of the second conductive barrier layer MA32, the first metal containing layer MB32, and the second metal containing layer MC32described with reference toFIG. 2C.

A first insulating capping layer CA61covering an upper surface of the first gate line GL61and a second insulating capping layer CA62covering an upper surface of the second gate line GL62may have substantially the same structure as the first insulating capping layer CA11and the second insulating capping layer CA12, respectively, described with reference toFIGS. 1A through 1C. However, the first insulating capping layer CA61may contact the first protrusion portion PR1and may have a bottom surface having a concave portion having a shape corresponding to a shape of the first protrusion portion PR1. Also, the second insulating capping layer CA62may contact the second protrusion portion PR2and may have a bottom surface having a concave portion having a shape corresponding to a shape of the second protrusion portion PR2.

Referring toFIG. 2G, a first gate line GL33and a second gate line GL34of the integrated circuit device100G may have substantially the same structure as the first gate line GL31and the second gate line GL32of the integrated circuit device100C illustrated inFIG. 2C.

However, in the integrated circuit device1000, the first gate line GL33may include a first conductive barrier layer MA33that does not contact the first insulating capping layer CA11, and the second gate line GL34may include the second conductive barrier layer MA34that does not contact the second insulating capping layer CA12. A height of the first conductive barrier layer MA33may be the same or substantially the same as a height of the second conductive barrier layer MA34.

In the first gate line GL33, the first conductive barrier layer MA33and the first insulating capping layer CA11may be apart from each other with the first metal containing layer MB31therebetween. In the second gate line GL34, the second conductive barrier layer MA34and the second insulating capping layer CA12may be apart from each other with a first metal containing layer MB34therebetween. The first metal containing layer MB34may be similar to the first metal containing layer MB32described with reference toFIG. 2C. However, an upper portion of the first metal containing layer MB34included in the second gate line GL34may have an angled shape that bends towards the gate dielectric layer118to overlap the second conductive barrier layer MA34included in the second gate line GL34between the second conductive barrier layer MA34and the second insulating capping layer CA12.

More detailed aspects with respect to the first conductive barrier layer MA33and the second conductive barrier layer MA34may be substantially the same as the detailed aspects with respect to the first conductive barrier layer MA31and the second conductive barrier layer MA32described with reference toFIG. 2C.

FIGS. 3A through 3Care views for describing integrated circuit devices according to other embodiments of the inventive concepts, whereinFIG. 3Ais a layout diagram of the integrated circuit device200,FIG. 3Bis a cross-sectional view taken along a line X-X ofFIG. 3A, andFIG. 3Cis a cross-sectional view taken along lines Y1-Y1′, Y2-Y2′, and Y3-Y3′ ofFIG. 3A. InFIGS. 3A through 3C, like reference numerals refer to the like elements inFIGS. 1A through 1C, and their detailed descriptions will be omitted.

Referring toFIGS. 3A through 3C, the integrated circuit device200may include the fin-type active area FA extending on the substrate110in a first direction (e.g., an X direction). A fin separating recess110R may be formed on an upper surface of the tin-type active area FA in a fin separating area FS. The fin-type active area FA may include a first tin portion FA1and a second fin portion FA2at both sides of the fin separating recess110R, with the tin separating recess110R interposed between the first fin portion FA1and the second fin portion FA2.

A fin separating insulating layer210may be formed in the fin separating area FS. The fin separating insulating layer210may include an insulating liner212covering an inner wall of the fin separating recess110R, and a burying insulating layer214filling the fin separating recess110R on the insulating liner212. In some embodiments, the insulating liner212and the burying insulating layer214may include different materials from each other, which may be selected from an oxide layer, a nitride layer, and/or an oxynitride layer. In other embodiments, the insulating liner212and the burying insulating layer214may include the same material as each other, which may be selected from an oxide layer, a nitride layer, and an oxynitride layer. Portions of both side walls of the fin separating layer210may be sequentially covered by an insulating spacer216and the gate insulating spacer124in the fin separating area FS. The insulating spacer216may include an oxide layer, a nitride layer, an oxynitride layer, or a combination thereof. The gate insulating spacer124from among the plurality of gate, insulating spacers124on the fin-type active area FA, which is in the fin separating layer FS, may have a smaller height than a gate insulating spacer124in other areas of the fin-type active area FA.

The shape and the structure of the fin separating insulating layer210illustrated inFIG. 3Bare only examples, and various modifications and changes thereof are possible within the technical scope of the present inventive concepts.

A plurality of first gate structures GST11extending in parallel to one another in a second direction (e.g., a Y direction) that crosses the first direction (e.g., the X direction) may be formed on the first fin portion FA1of the fin-type active area FA. The plurality of first gate structures GST11may include a plurality of first gate lines GL771, GL72, GL73, and GL74extending in the second direction (e.g., the Y direction), and a plurality of first insulating capping layers CA71, CA72, CA73, and CA74covering upper surfaces of the plurality of first gate lines GL71, GL72, GL73, and GL74and extending in parallel to the plurality of first gate lines GL71, GL72, GL73, and GL74. The plurality of first gate structures GST11may have the same or substantially the same heights.

At least two first gate structures GST11from among the plurality of first gate structures GST11may include first gate lines having different heights. For example, as illustrated inFIGS. 3B and 3C, three first gate structures GST11formed on the first fin portion FA1sequentially from the fin separating area FS may include the first gate lines GL71, GL72, and GL73having, different heights. Heights H21, H22, and H23of the three first gate lines GL71, GL72, and GL73may decrease as the three first gate lines GL71, GL72, and GL73are nearer to the fin separating insulating layer210. In some embodiments, the first gate line GL71from among the plurality of first gate lines GL71, GL72, GL73, and GL74on the first fin portion FA1of the fin-type active area FA, which is most adjacent to the fin separating insulating layer210, may have the smallest height H21.

At least two first gate structures GST11from among the plurality of first gate structures GST11may include first gate lines having the same height. For example, as illustrated inFIG. 3B, in the plurality of first gate structures GST11, two adjacent first gate lines GL73and GL74may have, the same or substantially the same heights H23and H24.

FIG. 3Aillustrates that four first gate structures GST11parallel to one another are formed on the first fin portion FA1of the fin-type active area FA. However, the present inventive concepts are not limited thereto. Two, three, or more than five first gate structures GST11parallel to each other or one another may be formed on the first fin portion FA1.

A plurality of second gate structures GST12extending in parallel to one another in the second direction (e.g., the Y direction) that crosses the first direction (e.g., the X direction) may be formed on the second fin portion FA2of the tin-type active area FA. At least one second gate structure GST12from among the plurality of second gate structures GST12may include a second gate line GL76extending in the second direction (e.g., the Y direction), and a second insulating capping layer CA76covering an upper surface of the second gate line GL76and extending in parallel to the second gate line GL76.FIG. 3Aillustrates that two second gate structures GST12parallel to each other are formed on the second fin portion FA2of the fin-type active area FA. However, the present inventive concepts are not limited thereto. In some embodiments, three or more second gate structures GST12parallel to one another may be formed on the second fin portion FA2. The plurality of second gate structures GST12formed on the second fin portion FA2may have the same or substantially the same heights.

The plurality of second gate structures GST12may include second gate lines having different heights, similarly with the plurality of first gate structures GST11. For example, three second gate structures may be formed on the second fin portion FA2sequentially from the fin separating area FS, and may include the second gate lines having different heights. Heights of the three second gate lines may decrease as the three second gate lines are nearer to the fin separating insulating layer210. In some embodiments, the second gate line GL76from among the plurality of second gate lines formed on the second fin portion FA2of the fin-type active area FA, which is most adjacent to the fin separating insulating, layer210, may have a smallest height H26. However, the present inventive concepts are not limited thereto, and various modifications and changes thereof are possible within the technical scope of the present inventive concepts.

In some embodiments, the height H21of the first gate line GL71which is most adjacent to the fin separating insulating layer210on the first fin portion FA1, and the height H26of the second gate line GL76which is most adjacent to the fin separating insulating layer210on the second fin portion FA2may be the same or substantially the same.

In other embodiments, the height H21of the first gate line GL71and the height H26of the second gate line GL76may be different from each other. For example, the height H21of the first gate line GL71may be greater or less than the height H26of the second gate line GL76.

Each of the first gate lines GL71, GL72, GL73, and GL74included in the plurality of first gate structures GST11and the second gate line GL76included in the plurality of second gate structures GST12may have any one structure selected from the structures of the gate lines GL11, GL12, GL21, GL22, GL31, GL32, GL41, GL42, GL51, GL52, GL61, GL62, GL33, and GL34described with reference toFIGS. 2A through 2G, and structures of gate lines that are modified or changed from the gate lines GL11, GL12, GL21, GL22, GL31, GL32, GL41, GL42, GL51, GL52, GL61, GL62, GL33, and GL34within the technical scope of the present inventive concepts.

The plurality of source/drain areas130may be formed on each of the first fin portion FA2and the second fin portion FA2of the fin-type active area FA. The plurality of source/drain areas130may be arranged such that each of the plurality of source/drain areas130is interposed between respective ones of the plurality of first gate structures GST11, and between respective ones of the plurality of second gate structures GST12.

FIG. 4is a cross-sectional view for describing integrated circuit devices300according to other embodiments of the inventive concepts. The cross-sectional view ofFIG. 4may correspond to a cross-sectional view taken along the line X-X′FIG. 3A. InFIG. 4, like reference numerals refer to the like elements inFIGS. 1A through 3C, and their detailed descriptions will be omitted.

Referring toFIG. 4, in the integrated circuit device300, a plurality of first gate structures GST21extending in parallel to one another in a second direction (e.g., a Y direction) that crosses a first direction (e.g., an X direction) may be formed on the first fin portion FA1of the fin-type active area FA. The plurality of first gate structures GST21may include a plurality of first gate lines GL81, GL82, GL83, and GL84extending in the second direction (e.g., the Y direction), and a plurality of first insulating capping layers CA81, CA82, CA83, and CA84covering upper surfaces of the plurality of first gate lines GL81, GL82, GL83, and GL84, respectively, and extending in parallel to the plurality of first gate lines GL81, GL82, GL83, and GL84. The plurality of first gate structures GST21may have the same or substantially the same heights.

At least two first gate structures GST21from among the plurality of first gate structures GST21may include first gate lines having different heights. For example, three first-gate structures GST21formed on the first fin portion FA1sequentially from the fin separating area FS may include the first gate lines GL81, GL82, and GL83having different heights. Heights H31, H32, and H33of the three first gate lines GL81, GL82, and GL83, respectively, may increase as the three first gate lines GL81, GL82, and GL83are nearer to the fin separating insulating layer210. In some embodiments, the first gate line GL81from among the plurality of first gate lines GL81, GL82, GL83, and GL84formed on the first fin portion FA1of the fin-type active area FA, which is most adjacent to the fin separating insulating layer210, may have the greatest height H31.

At least two first gate structures GST21from among the plurality of first gate structures GST21may include first gate lines having the same height. For example, in the plurality of first gate structures GST21, two adjacent first gate lines GL83and GL84may have the same or substantially the same heights H33and H34.

FIG. 4illustrates that four first gate structures GST21which are parallel to one another are formed on the first fin portion FA1of the fin-type active area FA. However, the present inventive concepts are not limited to the embodiment ofFIG. 4. Two, three, or more than five first gate structures GST21, which are parallel to each other or one another, may be formed on the first fin portion FA1.

A plurality of second gate structures extending in parallel to one another in the second direction (e.g., the Y direction) that crosses the first direction (e.g., the X direction) may be formed on the second fin portion FA2of the fin-type active area FA. The plurality of second gate structures may include a second gate structure GST22illustrated inFIG. 4. The second gate structure GST22may include a second gate line GL86extending in the second direction (e.g., the Y direction) and a second insulating capping layer CA86covering an upper surface of the second gate line GL86and extending in parallel to the second gate line GL86,FIG. 4illustrates that one second gate structure GST22is formed on the second fin portion FA2of the fin-type active area FA. However, the present inventive concepts are not limited thereto. In some embodiments, two or more parallel second gate structures GST22may be formed on the second fin portion FA2. The plurality of second gate structures GST22on the second fin portion FA2may have the same or substantially the same heights.

In some embodiments, the plurality of second gate structures may include second gate lines having different heights, similarly with the plurality of first gate structures GST21. For example, three second gate structures may be formed on the second fin portion FA2sequentially from the fin separating area FS, and may include the second gate lines having different heights. Heights of the three second gate lines may increase as the three second gate lines are nearer to the fin separating insulating layer210. In some embodiments, the second gate line GL86from among the plurality of second gate lines formed on the second fin portion FA2of the fin-type active area FA, which is most adjacent to the fin separating insulating layer210, may have the greatest height. However, the present inventive concepts are not limited thereto, and various modifications and changes thereof may be possible within the technical scope of the present inventive concepts.

In some embodiments, a height H36of the second gate line GL86which is most adjacent to the fin separating insulating layer210on the second fin portion FA2may be the same or substantially the same as the height H31of the first gate line GL81which is most adjacent to the fin separating insulating layer210on the first fin portion FA1.

In other embodiments, the height H31of the first gate line GL81and the height H36of the second gate line GL86may be different from each other. For example, the height H31of the first gate line GL81may be greater or less than the height H36of the second gate line GL86.

Each of the first gate lines GL81, GL82, GL83, and GL84included in the plurality of first gate structures GST21and the second gate line GL86included in the second gate structure GST22may have any one structure, selected from the structures of the gate lines GL11, GL12, GL21, GL22, GL31, GL32, GL41, GL42, GL51, GL52, GL61, GL62, and GL34, described with reference toFIGS. 2A through 2C, and may have structures of gate lines modified or changed from the gate lines GL11, GL12, GL22, GL31, GL41, GL51, GL52, GL61, GL62, GL33, and GL34within the technical scope of the present inventive concepts.

FIG. 5is a cross-sectional view for describing an integrated circuit device400according to other embodiments of the inventive concepts. The cross-sectional view ofFIG. 5may correspond to a cross-sectional view taken along the line X-X′ ofFIG. 3A. InFIG. 5, like reference numerals refer to the like elements inFIGS. 1A through 3C, and their detailed descriptions will be omitted.

Referring toFIG. 5, in the integrated circuit device400, a plurality of first gate structures GST31extending in parallel to one another in a second direction (e.g., a Y direction) that crosses a first direction (e.g., an X direction) may be formed on the first fin portion FA1of the fin-type active area FA. The plurality of first gate structures GST31may include a plurality of first gate lines GL91, GL92, GL93, and GL94extending in the second direction (e.g., the Y direction), and a plurality of first insulating capping layers CA91, CA92, CA93, and CA94covering upper surfaces of the plurality of first gate lines GL91, GL92, GL93, and GL94, respectively, and extending in parallel to the plurality of first gate lines GL91, GL92, GL93, and GL94. The plurality of first gate structures GST31may have the same or substantially the same heights.

The first gate line GL91of the first gate structure GST31, from among the plurality of first gate lines included in the plurality of first gate structures GST31, which is most adjacent to the fin separating insulating layer210, may have the smallest height H41. Other first gate lines GL92, GL93, and GL94from among the plurality of gate lines included in the plurality of first gate structures GST31than the first gate line GL91may have the same or substantially the same heights H42, H43, and H44. However, the present inventive concepts are not limited to the example illustrated inFIG. 5. For example, the first gate line GL91from among the plurality of first gate lines included in the plurality of first gate structures GST31, which is most adjacent to the fin separating insulting layer210, may have the greatest height.

A plurality of second gate structures extending in parallel to one another in the second direction (e.g., the Y direction) that crosses the first direction (e.g., the X direction) may be formed on, the second fin portion FA2of the fin-type active area FA. The plurality of second gate structures may include a second gate structure GST32illustrated inFIG. 5. The second gate structure GST32may include a second gate line GL96extending in the second direction (e.g., the Y direction) and a second insulating capping layer CA96covering an upper surface of the second gate line GL96and extending in parallel to the second gate line GL96.FIG. 5illustrates that one second gate structure GST32is formed on the second fin portion FA2of the fin-type active area FA. However, the present inventive concepts are not limited thereto. In some embodiments, two or more parallel second gate structures may be formed on the second fin portion FA2. Other second gate structures from among the plurality of second gate structures formed on the second fin portion FA2than the second gate structure GST32which is most adjacent to the fin separating insulating layer210may have the same or substantially the same heights.

Each of the first gate lines GL91, GL92, GL93, and GL94included in the plurality of first gate structures GST31and the second gate line GL96included in the second gate structure GST32may have any one structure selected from the structures of the gate lines GL11, GL12, GL21GL22, GL31, GL32, GL41, GL42, GL62, GL33, and GL34, described with reference toFIGS. 2A through 2C, and may have structures of gate lines modified or changed from the gate lines GL11, GL12, GL21, GL22, GL32, GL41, GL42, GL51, GL52, GL61, GL62, GL33, and GL34within the technical scope of the present inventive concepts.

The integrated circuit devices100,100A through100G,200,300, and400according to the embodiments described with reference toFIGS. 1A through 5may be included in a logic area or a memory area. The logic area may be standard cells performing desired logic functions, such as a counter, a buffer, etc., and may include various types of logic cells including a plurality of circuit elements, such as a transistor, a register, etc. For example, the logic cells may be included in AND, NAND, OR, NOR, exclusive OR (XOR), exclusive NOR (XNOR), an inverter (INV), an adder (ADD), a buffer (BUF), a delay (DLY), a filter (FIL), a multiplexer (MXT/MXIT), OR/AND/INV (OAI), AND/OR (AO), AND/OR/INV (AOI), a D flip-flip, a reset flip-flop, a master-slave flip-flop, a latch, etc. However, the listed cells are only examples, and the logic cells according to the present inventive concepts are not limited thereto. The memory area may include a static random access memory (SRAM) area, a dynamic random access memory (DRAM) area, a magnetic random access memory (MRAM) area, a resistive random access memory (RRAM) area, and/or a phase-change random access memory (PRAM) area.

The integrated circuit devices100,100A through100G,200,300, and400according to the embodiments described with reference toFIGS. 1A through 5may include the plurality of gate structures on one fin-type active area FA, and the plurality of gate structures may include at least two gate structures having different gate heights. When types and/or strengths of stress regionally applied to the fin-type active area FA are different based on locations of the fin-type active area FA, the different stress may differently affect threshold voltages of the plurality of transistors on the fin-type active area FA. However, according to the present inventive concepts, the threshold voltages of the transistors may be controlled to be substantially constant, or differences between the threshold voltages of the transistors may be minimized within a permitted range, by controlling work functions of the gate lines in the plurality of gate structures by adjusting heights, of the gate lines included in the plurality of gate structures.

For example, in the integrated circuit devices200,300, and400illustrated inFIGS. 3B, 4, and 5, since the fin separating insulating layer210is formed on the fin-type active area FA, particular stress, for example, compressive stress, may be concentrated around the fin separating insulating layer210on the fin-type active area FA. Accordingly, threshold voltages of transistors from among the plurality of transistors formed on the fin-type active area FA, which are adjacent to the fin separating insulating layer210, may be different from threshold voltages of other transistors which are relatively far from the fin separating insulating layer210. Accordingly, a threshold voltage distribution of the plurality of transistors may increase. The integrated circuit devices108,100A through100G,200,300, and400according to the embodiments include the gate lines including metal containing layers having different heights based on distances from the fin separating insulating layer210, and thus, the threshold voltage distribution of the plurality of transistors on the fin-type active area FA may be decreased. The integrated circuit device according to the present inventive concepts may suppress variation of electrical performance based on locations of the electrical performance, the variation occurring due to a complex structure of a highly down-scaled integrated circuit device. Thus, the reliability of the integrated circuit device may be increased.

In some embodiments, when all of the plurality of transistors formed on the fin-type active area FA are PMOS transistors, threshold voltages of the transistors may decrease as the transistors are nearer to the fin separating insulating layer210, due to compressive stress concentrated around the fin separating insulating layer210on the fin-type active area FA. In this case, as in the integrated circuit devices200and400illustrated inFIGS. 3B and 5, the gate line included in the transistor that is most adjacent to the fin separating insulating layer210may be formed to have a smaller height than the gate lines of other transistors that are further from the fin separating insulating layer210, in order to increase the threshold voltage of the transistor most adjacent to the fin separating insulating layer210. In other embodiments, when all of the plurality of transistors formed on the fin-type active area FA are NMOS transistors, threshold voltages of the transistors may increase as the transistors are nearer to the fin separating insulating layer210, due to compressive stress concentrated around the fin separating insulating layer210on the fin-type active area PA. In this case, as in the integrated circuit devices200and480illustrated inFIGS. 3B and 5, the gate line included in the transistor that is most adjacent to the fin separating insulating layer210may be formed to have a smaller height than the gate lines of other transistors that are further from the fin separating insulating layer210, in order to reduce the threshold voltage of the transistor most adjacent to the fin separating insulating layer210. However, the described examples are only for convenience of understanding, and the present inventive concepts are not limited thereto.

Next, a method of manufacturing integrated circuit devices will be described in detail, according to embodiments of the inventive concepts.

FIGS. 6A through 20Bare cross-sectional views for describing an example sequential process of manufacturing integrated circuit devices, according to embodiments of the inventive concepts, whereinFIGS. 6A, 7A, 8 through 13, 14A, 15A, 20Aare the cross-sectional views illustrating, according to the sequential process of manufacturing the integrated circuit devices, a portion corresponding to a sectional plane taken, along the line X-X′ ofFIG. 3A, andFIGS. 6B, 7B, 14B, 15B, . . . ,20B are the cross-sectional views illustrating, according to the sequential process of manufacturing the integrates circuit devices, a portion corresponding to a sectional plane taken along the lines Y1-Y1′, Y2-Y2′, and Y3-Y3′ ofFIG. 3A. An example method of manufacturing the integrated circuit device200illustrated inFIGS. 3A through 3Cwill be described by referring toFIGS. 6A through 20B. InFIGS. 6A through 20B, like reference numerals refer to the like elements inFIGS. 1A through 3C, and their detailed descriptions will be omitted.

Referring toFIGS. 6A and 6B, the fin-type active area FA protruding upwards (e.g., the Z direction) from the main surface110M of the substrate110and extending in the direction (e.g., the X direction) may be formed by etching a portion of the substrate110.

In some embodiments, the substrate110may have a metal oxide semiconductor (MOS) area. For example, the substrate110may have a PMOS area or an NMOS area.

In some embodiments, a portion of the substrate110, which is illustrated inFIGS. 6A and 6B, may be an area for forming any one of a PHOS transistor and an NMOS transistor. The fin-type active area FA may include P-type or N-type impurity diffusion areas (not shown) according to the channel type of the MOS transistor to be formed on the fin-type active area FA.

After an insulating layer covering the fin-type active area FA is formed on the substrate110, the insulating layer may be etched back to form the device isolation layer112. As a result, the fin-type active area FA may protrude upwards from an upper surface of the device isolation layer112and be exposed.

Referring toFIGS. 7A and 7B, a plurality of dummy gate structures DGS extending on the fin-type active area FA in a direction that crosses the fin-type active area FA may be formed.

Each of the plurality of dummy gate structures DGS may include a dummy gate dielectric layer D514, a dummy gate, line D516, and a dummy gate capping layer D518sequentially stacked on the fin-type active area FA. In some embodiments, the dummy gate dielectric layer D514may include silicon oxide. The dummy gate line D516may include polysilicon. The dummy gate capping layer D518may include at least one of silicon oxide, silicon nitride, and silicon oxynitride.

Then, the gate insulating spacer124may be formed at both side walls of the dummy gate structure DOS, An ALD or a CVD process may be used to form the gate insulating spacer124.

Thereafter, the source/drain130may be formed by forming a semiconductor layer on the fin-type active area FA exposed at both sides of the dummy gate structure DGS via an epitaxial growing process. The source/drain area130may have a higher upper surface than the fin-type active area FA. The source/drain area130may have a section that is taken along a Y-Z plane, which has a shape of a polygon, such as a quadrangle, a pentagon, a hexagon, etc., a circle, or an oval. The source/drain area130may include a semiconductor layer doped with impurities. In some embodiments, the source/drain area130may include Si, SiGe, and/or SIC doped with impurities.

Thereafter, the inter-gate insulating layer132covering the source/drain area130, the plurality of dummy gate structures DGS, and the gate insulating spacer124may be formed.

In some embodiments, in order to form the inter-gate insulating layer132, an insulating layer covering the source/drain area130, the plurality of dummy gate structures DGS, and the gate insulating spacer124by a sufficient thickness may be formed. Thereafter, the inter-gate insulating layer132having a planarized upper surface may be formed by planarizing the above insulating layer to expose an upper surface of the dummy gate capping layer D518of each of the plurality of dummy gate structures DGS.

Referring toFIG. 8, a mask pattern520may be formed on the inter-gate insulating layer132. The mask pattern520may have an opening520H exposing the dummy gate structure DGS and a portion of the inter-gate insulating layer132around the dummy gate structure DGS, in the fin separating area FS. Then, the mask pattern520may be used as an etch mask to remove the portion of the inter-gate insulating layer132and the dummy gate structure DGS exposed via the opening520H, in order to form a separating space522exposing the fin-type active area FA via the opening520H.

While the separating space522is formed, a portion of the gate insulating spacer124in the tin separating area FS may be consumed so that a height of the gate insulating spacer124may be reduced.

Referring toFIG. 9, an insulating liner530may be formed on the surface of the mask pattern520and the formed separating space522, in order to cover the gate insulating spacer124and the inter-gate insulating layer132exposed in the separating space522.

The insulating liner530may include an oxide layer, a nitride layer, an oxynitride layer, or a combination thereof.

Referring toFIG. 10, the insulating liner530(refer toFIG. 9) may be etched back so that an insulating spacer530S remains at each of a side wall of the gate insulating spacer124and a side wall of the inter-gate insulating layer132in the separating space522.

After the insulating spacer530S is formed, the fin-type active area FA may be exposed in the separating space522.

Referring toFIG. 11, in the resultant structure ofFIG. 10, the fin-type active area PA exposed in the separating space522may be etched by using the mask pattern520, the insulating spacer530S, the gate insulating spacer124, and the inter-gate insulating layer132as an etch mask to form the fin separating recess110R.

While the fin separating recess110R is formed, a height of the gate insulating spacer124may be reduced, and the insulating spacer530S covering the side wall of the inter-gate insulating layer132may be consumed. Also, a height of the insulating spacer530S covering the side wall of the gate insulating spacer124may be reduced. A portion of the insulating spacer530S, which covers the side wall of the gate insulating spacer124in the separating space522may remain as the insulating spacer216described with reference toFIGS. 3A through 3C.

As the fin separating recess110R is formed in the fin-type active area FA, the fin-type active area FA may be divided into the first fin portion FA1and the second fin portion FA2located at both sides of the fin separating recess110R.

The mask pattern520remaining after the fin separating recess110R is formed may be removed to expose the upper surface of the dummy gate capping layer D518of each of the plurality of dummy gate structures DGS and the upper surface of the inter-gate insulating layer132.

Referring toFIG. 12, the insulating liner212covering an inner wall of the fin separating recess110R, and the burying insulating layer214filling the fin separating recess110R on the insulating liner212may be formed on the entire surface of the resultant structure ofFIG. 11.

Referring toFIG. 13, a portion of the insulating liner212, a portion of the burying insulating layer214, and the plurality of dummy gate capping layers D518included in the plurality of dummy gate structures DGS may be removed and the resultant structure that is obtained thereafter may be planarized to expose the plurality of dummy gate lines D516and planarize the upper surface of the inter-gate insulating layer132.

As a result, the fin separating insulating layer210including the insulating liner212and the burying insulating layer214may remain in the fin separating area FS. While the upper surface of the inter-gate insulating layer132is planarized, a height of the gate insulating spacer124adjacent respective ones of the dummy gate lines D516may decrease.

Referring toFIGS. 14A and 14B, the plurality of dummy gate structures DOS may be removed from the resultant structure ofFIG. 13, to form a plurality of gate spaces GH.

The gate insulating spacer124, the fin-type active area FA, and the device isolation layer112may be exposed through the plurality of gate spaces GH.

A wet etching process may be used to remove the plurality of dummy gate structures DGS. To perform the wet etching, for example, nitride acid (HNO3), diluted fluoride acid (DHF), NH4OH, tetramethyl ammonium hydroxide (TMAH), potassium hydroxide (KOH), or a combination thereof may be used as an etchant. However, the etchant is not limited thereto.

Referring toFIGS. 15A and 15B, the plurality of interfacial layers116, the gate dielectric layer118, and a gate line540may be sequentially formed to fill each of the plurality of gate spaces GH (refer toFIGS. 14A and 14B).

The process of forming the plurality of interfacial layers116may include oxidizing a portion the fin-type active area FA which is exposed in the plurality of gate spaces GH.

The gate dielectric layer118and the gate line540may be formed to fill the plurality of gate spaces GH and cover the upper surface of the inter-gate, insulating layer132.

The gate line540may include a conductive structure of a single layer or multiple layers including a metal layer or a metal containing layer. In some embodiments, the gate line540may have the structures of the gate lines GL11, GL12, GL21, GL22, GL31, GL32, GL41, GL42, GL51, GL52, GL61, GL62, GL33, and GL34described with reference toFIGS. 2A through 2G, and may have structures of various multiple layers modified or changed from the gate lines GL11, GL12, GL21, GL22, GL31, GL32, GL41, GL42, GL51, GL52, GL61, GL62, GL33, and GL34within the technical scope of the present inventive concept. The gate line540may be formed by an ALD, an MOALD, or an MOCVD process. However, it is not limited thereto.

Referring toFIGS. 16A and 16B, unnecessary portions may be removed from the resultant structure ofFIGS. 15A and 15Bvia a planarization process, and the gate line540and the gate dielectric layer118may be divided into the plurality of gate lines540and the plurality of gate dielectric layers118, respectively, which remain in the plurality of gate spaces OH (refer toFIGS. 14A and 14B).

In some embodiments, as a result of the planarization process, a certain thickness of an upper surface of each of the gate insulating spacer124and the inter-gate insulating layer132may be removed.

Referring toFIGS. 17A and 17B, a first recess mask pattern552exposing some of the plurality of gate lines540may be formed on a portion of the resultant structure ofFIGS. 16A and 16B.

Thereafter, a certain thickness of the gate lines540from among the plurality of gate lines540, which are not covered by the first recess mask pattern552, may be removed, in order to form a first recess space RS1.

When the certain thickness of the gate lines540is removed, the gate dielectric layer118exposed in the first recess space RS1may also be removed so that a portion of the gate insulating spacer124may be exposed in the first recess space RS1. However, the present inventive concepts are not limited thereto. For example, when the gate lines540are removed, at least a portion of the gate dielectric layer118exposed in the first recess space RS1may not be removed, and may remain to cover a side wall of the gate insulating spacer124.

The first recess mask pattern552may be formed to expose the gate lines540from among the plurality of gate lines540, which are adjacent to the fin separating insulating layer210at both sides of the fin separating insulating layer210. Accordingly, the first recess space RS1may be formed on each of the gate lines540adjacent to the fin separating insulating layer210at both sides of the fin separating insulating layer210.

The first recess mask pattern552may include a material having an etch selectivity with respect to the plurality of gate lines540and the gate dielectric layer118. In some embodiments, the first recess mask pattern552may include a photoresist pattern, an oxide layer, a nitride layer, or a combination thereof.

Referring toFIGS. 18A and 18B, after the first recess mask pattern552may be removed from the resultant structure ofFIGS. 17A and 17B, a second recess mask pattern554exposing some of the plurality of gate lines540may be formed, and a certain thickness of the gate lines540from among the plurality of gate lines540, which are not covered by the second recess mask pattern554, may be removed in order to increase a depth of the first recess space RS1in some of the plurality of gate lines540, and to form a second recess space RS2in other gate lines540, which are not covered by the second recess mask pattern554.

A depth of the second recess space RS2may be less than the depth of the first recess space RS1.

The second recess mask pattern554may include the same material as the first recess mask pattern552described with reference toFIGS. 17A and 17B.

In some embodiments, in order to form the second recess mask pattern554, the first recess mask pattern552illustrated inFIGS. 17A and 17Bmay not be removed, and a resultant structure obtained by patterning the first recess mask pattern552may be used as the second recess mask pattern554.

When the gate lines540are removed, the gate dielectric layer118exposed in the first recess space RS1and the second recess space RS2may also be removed to expose a portion of the gate insulating spacer124in the first recess space RS1and the second recess space R52. However, the present inventive concepts are not limited thereto. For example, when the gate lines540are removed, at least a portion of the gate dielectric layer118exposed in the first recess space RS1and the second recess space RS2may not be removed, and may remain to cover the side wall of the gate insulating spacer124.

Referring toFIGS. 19A and 19B, after the second recess mask pattern554is removed from the resultant structure ofFIGS. 18A and 18B, a certain thickness of the exposed plurality of gate lines540may be removed, in order to further increase the depth of the first recess space RS1in some gate lines540, to further increase the depth of the second recess space RS in other gate lines540, and to form a third recess space RS3in other gate lines540.

As a result, the first gate lines GL71, GL72, GL73, and GL74and the second gate GL76including remaining portions of the gate lines540may remain, and the first gate lines GL71, GL73, and GL74and the second gate line GL76may be exposed through the first recess space RS1, the second recess space RS2, and the third recess space RS3.

A depth of the third recess space RS3may be less than the depth of the second recess space RS2, and the depth of the second recess space RS2may be less than the depth of the first recess space RS1.

When the certain thickness of the gate lines540is removed, the gate dielectric layer118exposed in the first recess space RS1, the second recess space RS2, and the third recess space RS3may be removed together, and thus, a portion of the gate insulating spacer124may be exposed in the first recess space RS1, the second recess space RS2, and the third recess space RS3. However, the present inventive concepts are not limited thereto. For example, when the certain thickness of the gate lines540is removed, at least a portion of the gate dielectric layer118exposed in the first recess space RS1, the second recess space RS2, and the third recess space RS3may not be removed, and may remain to cover the side wall of the gate insulating spacer124.

In some embodiments, in order for the first gate lines GL73and GL74to have different heights, the processes described with reference toFIGS. 17A and 17Bmay be repeated by being adjusted for a desired condition. That is to say that in some embodiments, additional recess mask patterns may be used to selectively remove portions of the gate lines540to form the first gate lines GL73and GL74to have different heights.

The first gate lines GL71, GL73, and GL74, and the second gate line GL76may have the structures of the gate lines GL11, GL12, GL22, GL31, GL32, GL41, GL42, GL51, GL52, GL61, GL62, GL33, and GL34described with reference toFIGS. 2A through 2G, and may have various other structures modified or changed from the structures of the gate lines GL11, GL12, GL21, GL22, GL31, GL32, GL41, GL42, GL51, GL52, GL61, GL62, GL33, and GL34within the technical scope of the present inventive concepts.

For example, in order to form the first conductive barrier layer MA31, MA61, or MA33not contacting the first insulating capping layer CA11, and the second conductive barrier layer MA34not contacting the second insulating capping layer CA12, as illustrated inFIGS. 2C through 2G, the process of forming the conductive structure for the gate line540described with reference toFIGS. 15A and 15Bmay include forming a conductive barrier layer entirely covering an exposed surface of the gate dielectric layer118and etching back the conductive barrier layer until, a resultant structure of a desired height remains. When the first metal containing layer MB31or MB61is formed on the first conductive barrier layer MA31, MA61, or MA33, an upper surface of the first metal containing layer MB31or MB61may have a recessed portion corresponding to a sectional profile of the first conductive barrier layer MA31, MA61, or MA33. A sequential metal containing layer may be formed on the first metal containing layer MB31or MB61having the upper surface including the recessed portion, to fill the gate space GS. As a result, the second metal containing layer MC31or MC61having the upper portion31T may be obtained as illustrated inFIGS. 2C through 2G. After the conductive structure for the gate line540having various structures is formed by using the method described above, a series of processes described with reference toFIGS. 17A through 19Bmay be performed to form the first gate lines GL71, GL72, GL73, and GL74and the second gate line GL76having the structures of the gate lines GL11, GL12, GL21, GL22, GL31, GL32, GL41, GL42, GL51, GL52, GL61, GL62, GL33, and GL34described with reference toFIGS. 2A through 2G, and various structures modified or changed from the structures of the gate lines GL11, GL12, GL21, GL22, GL31, GL32, GL41, GL42, GL51, GL52, GL61, GL62, GL33, and GL34within the technical scope of the present inventive concepts.

Referring toFIGS. 20A and 20B, the first insulating capping layers CA71, CA72, CA73, and CA74and the second insulating capping layer CA76filling the first recess space RS1, the second recess space RS2, and the third recess space RS3in the resultant structure ofFIGS. 19A and 19Bmay be formed to form the integrated circuit device200illustrated inFIGS. 3A through 3C.

The method of forming the integrated circuit device200ofFIGS. 3A through 3Cis described with reference toFIGS. 6A through 20B. However, one of ordinary skill in the art would easily understand that the integrated circuit devices100,100A through1000,300, and400illustrated inFIGS. 1A through 2G, 4, and 5, and integrated circuit devices having various structures modified or changed from the structures of the integrated circuit devices100,100A through100G,300, and400within the technical scope of the present inventive concepts, may be formed by using the method.

The integrated circuit devices including the FinFET including the three-dimensional cannel, and the methods of manufacturing the same are described with reference toFIGS. 1A through 20B. However, the present inventive concepts are not limited thereto. For example, one of ordinary skill in the art would easily understand that integrated circuit devices including a planar MOSFET and methods of manufacturing the same including the technical characteristics of the present inventive concepts may be provided via various modifications and changes from the technical characteristics of the present inventive concepts, within the technical scope of the present inventive concepts.

FIG. 21is a block diagram of an electronic system2000including integrated circuit devices according to embodiments of the inventive concepts.

The electronic system2000may include a controller2010, an input/output (I/O) device2020, a memory2030, and an interface2040, which are connected to one another via a bus2050.

The controller2010may include at least one of a microprocessor, a digital signal processor, or a processor similar thereto. The I/O device2020may include at least one of a keypad, a keyboard, and a display. The memory2030may be used to store instructions executed by the controller2010. For example, the memory2030may be used to store use data.

The electronic system2000may be included in a wireless communication device, or a device capable of transmitting and/or receiving information under a wireless environment. The interface2040may include a wireless interface, in order to transmit/receive data via a wireless communication network in the electronic system2000. The interface2040may include an antenna and/or a wireless transceiver. In some embodiments, the electronic system2000may be used as a communication interface protocol of a third generation communication system, such as code division multiple access (CDMA), global system for mobile communications (GSM), north American digital cellular (NADC), extended-time division multiple access (E-TDMA), and/or wide band code division multiple access (WCDMA). The electronic system2000may include at least one of the integrated circuit devices100,100A through100G,200,300, and400illustrated inFIGS. 1A through 5, and integrated circuit devices having structures modified or changed from the structures of the integrated circuit devices100,100A through100G,200,300, and400within the technical scope of the present inventive concepts.