Circuit for detecting arcing in an etch tool during wafer processing

According to one exemplary embodiment, a circuit configured to interface with an etch tool comprises an ESC input for receiving a first signal from the etch tool, where the first signal indicates a magnitude of a chuck current passing through a chuck holding a wafer in the etch tool. The circuit further comprises a VRF input for receiving a second signal from the etch tool, which indicates a magnitude of a voltage difference between a plasma and the chuck in the etch tool. The circuit further comprises an arc detect output indicating whether an arc event has occurred. The circuit can be configured to prevent the arc detect output from indicating an occurrence of a chucking spike and a de-chucking spike in the etch tool.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention is generally directed to the field of semiconductor fabrication. More particularly, the present invention is in the field of plasma etch tools for semiconductor fabrication.

2. Related Art

Plasma etch tools have a tendency to generate electric arcs during long high bias processes. Arcing is caused by a higher than desired charge building up on the chuck upon which the wafer is mounted during processing. When the charge built up on the chuck reaches a critical voltage potential difference from the etch tool plasma, an electric arc is generated from the plasma through the wafer to the chuck to dissipate this voltage potential difference. Arcing during plasma processing requires the processed wafer to be scrapped. Further processing of wafers that need to be scrapped wastes time and resources. Also, allowing wafer processing to continue during arcing will cause additional wafers to be scrapped, which lowers the useful yield of the fabrication process and undesirably increases manufacturing costs.

Makers of plasma etch tools have focused on reducing the number of arcing incidents, but these solutions have not resulted in elimination of arcing events, and arced wafers continue to be discovered too late, after completion of an entire time-consuming wafer processing run. A real-time data acquisition tool was developed so that semiconductor fabrication personnel could detect wafer arcing by monitoring the conditions that affect arcing. However, real-time data monitoring requires that a person be present and alert to monitor the etch tool during the entire wafer processing, which can last several hours. Thus, the human-monitor approach is costly and subject to human error. Another approach similar to the human-monitor approach utilizes a computer system to oversee the monitoring and control process instead of a person. However, this approach is costly since it must be customized for each application and requires a computer system.

Thus, there is a need in the art for a cost-effective device that can accurately detect arcing in an etch tool during wafer processing.

SUMMARY OF THE INVENTION

The present invention is directed to circuit for detecting arcing in an etch tool during wafer processing. The present invention addresses and resolves the need in the art for a cost-effective device that can accurately detect arcing in an etch tool during wafer processing.

According to one exemplary embodiment, a circuit configured to interface with an etch tool comprises an ESC input for receiving a first signal from the etch tool, where the first signal indicates a magnitude of a chuck current passing through a chuck holding a wafer in the etch tool. For example, the first signal can indicate an occurrence of a chucking spike, a de-chucking spike, or an arc event in the etch tool. The circuit further comprises a VRF input for receiving a second signal from the etch tool, where the second signal indicates a magnitude of a voltage difference between a plasma and the chuck in the etch tool.

According to this exemplary embodiment, the circuit further comprises an arc detect output indicating whether an arc event has occurred. The circuit can be configured to prevent the arc detect output from indicating an occurrence of a chucking spike and a de-chucking spike in the etch tool. The circuit can further comprise an ESC signal level detector connected to the ESC input, where the ESC signal level detector is configured to provide an output when the first signal indicates the occurrence of the chucking spike, the de-chucking spike, or the arc event. The circuit can further comprise a VRF signal level detector connected to the VRF input, where the VRF signal level detector is configured to provide an output when the second signal indicates that the plasma is activated.

According to this exemplary embodiment, the circuit can further comprise a first gate having a first gate input, a second gate input, and a first gate output, where the first gate input is connected to the ESC input and the second gate input is connected to the VRF input, and where the first gate is configured to output a third signal at the first gate output when the first signal indicates the occurrence of the de-chucking spike and the arc event and not output the third signal at the first gate output when the first signal indicates the occurrence of the chucking spike. The circuit can further comprise a power-on delay connected between the VRF input and the second gate input, where the power-on delay is configured to prevent the first gate from outputting the third signal during the occurrence of the chucking spike.

The circuit can further comprise a second gate having a third gate input, a fourth gate input, and a second gate output, where the third gate input is connected to the first gate output and the fourth gate input is connected to the VRF input, and where the second gate is configured to output a fourth signal at the second gate output during the occurrence of the arc event and not output the fourth signal during the occurrence of the de-chucking spike. Other features and advantages of the present invention will become more readily apparent to those of ordinary skill in the art after reviewing the following detailed description and accompanying drawings.

DETAILED DESCRIPTION OF THE INVENTION

The present invention is directed to circuit for detecting arcing in an etch tool during wafer processing. The following description contains specific information pertaining to the implementation of the present invention. One skilled in the art will recognize that the present invention may be implemented in a manner different from that specifically discussed in the present application. Moreover, some of the specific details of the invention are not discussed in order not to obscure the invention.

FIG. 1shows a diagram of an exemplary etch tool coupled to an exemplary arc detect circuit in accordance with one embodiment of the present invention. Certain details and features have been left out ofFIG. 1, which are apparent to a person of ordinary skill in the art. Diagram100inFIG. 1includes etch tool102coupled to arc detect circuit110. As shown inFIG. 1, etch tool102includes chuck104, wafer106, and plasma108. Etch tool102can be, for example, a plasma etch tool such as the Centura eMAX™ oxide etch tool manufactured by Applied Materials, Inc.

As further shown inFIG. 1, chuck104is situated in etch tool102and can be an electrostatic chuck (ESC). Also shown inFIG. 1, wafer106is situated on chuck104. Wafer106can be secured to chuck104by an electrostatic force during a wafer processing procedure. Further shown inFIG. 1, plasma108is situated inside etch tool102and can be utilized to etch wafer106. Plasma108can be formed, for example, by ionizing a process gas in an electric field by utilizing an RF power source (not shown inFIG. 1). Also shown inFIG. 1, arc detect circuit110is connected to etch tool102by lines112and114. Arc detect circuit110can receive an ESC signal via line112(or “ESC input112”) and a VRF signal via line114(or “VRF input114”), and can be configured to provide a specified output if wafer arcing occurs while arc detect circuit110is in an armed condition.

Before wafer processing, a chucking procedure is used to mount wafer106on chuck104, and after wafer processing, a de-chucking procedure is used to remove wafer106from chuck104. Chucking and de-chucking procedures cause spikes in the chuck current signal that resemble spikes caused by wafer arcing. In the present invention, arc detect circuit110can be configured to ignore spikes that occur during chucking and de-chucking procedures, and to provide a specified output only when a verified wafer arc event occurs. The present invention's arc detect circuit will be described in greater detail in relation toFIG. 2.

FIG. 2shows a block diagram of an exemplary arc detect circuit, in accordance with one embodiment of the present invention. Certain details and features have been left out ofFIG. 2, which are apparent to a person of ordinary skill in the art. Arc detect circuit210includes ESC input212, VRF input214, ESC signal level detector218, VRF signal level detector250, delay module258, AND gate226, storage module230, delay module234, AND gate238, storage module242, and arc detect output246. Arc detect circuit210inFIG. 2corresponds to arc detect circuit110inFIG. 1, and ESC input212corresponds to ESC input112while VRF input214corresponds to VRF input114of arc detect circuit110inFIG. 1.

As shown inFIG. 2, ESC input212is connected to a signal input of ESC signal level detector218. ESC input212can receive an indication of a current flowing through a chuck (“chuck current”) situated in an etch tool, such as chuck104in etch tool102inFIG. 1. As further shown inFIG. 2, low voltage-setting means220is connected to a low range input of ESC signal level detector218and high voltage-setting means222is connected to a high range input of ESC signal level detector218. By way of example, each low voltage-setting means220and high voltage-setting means222can be set to a voltage chosen between −5V and +5V. For example, low voltage-setting means220can provide a lower limit of approximately −0.5V while high voltage-setting means222can provide an upper limit of approximately +0.3V.

ESC signal level detector218can be configured to output a signal when an arc event is detected at the signal input of ESC signal level detector218. For example, when an ESC signal at ESC input212is outside the range of −0.5V to +0.3V, ESC signal level detector218can be configured to output a signal that indicates that a wafer arc event, a chucking spike, or a de-chucking spike, has been indicated at the signal input of ESC signal level detector218. However, signal level detector218does not distinguish between a wafer arc event and chucking and de-chucking spikes at ESC input212.

The output of ESC signal level detector218is connected to a first input of gate226via line224. Gate226can be a 2-to-1 logical AND-gate, and can be configured to provide an output signal, such as a logical one, at an output of gate226that indicates only an occurrence of an arc event or a de-chucking spike at ESC input212. Thus, the signal outputted at the output of gate226does not indicate an occurrence of a chucking spike at ESC input212. The output of gate226is connected to an input of storage module230via line228. Storage module230can be, for example, a latch, and can be configured to store the output signal received from gate226indicating the occurrence of a de-chucking spike or an arc event. The output of storage module230is connected to an input of power-off advance module234via line232. Power-off advance module234can be set to delay an output signal received from storage module230by, for example, from 0 to 8 seconds. In the present embodiment, power-off advance module234can be set to delay the output signal received from storage module230by approximately 8 seconds.

The output of power-off advance module234is connected to a first input of gate238via line236. Gate238can be, for example, a 2-to-1 AND-gate, and can be configured to provide an output signal, such as a logical one, at an output of gate238that indicates an occurrence of an arc event and does not indicate an occurrence of a de-chucking spike. The output of gate238is connected to an input of storage module242via line240. Storage module242can be, for example, a latch, and can be configured to store a signal received from the output of gate238, which indicates an occurrence of an arc event. An output of storage module242is connected to arc detect output246. Thus, the signal stored in storage module242, which indicates an occurrence of an arc event, can be provided at arc detect output246.

Plasma, such as plasma108in etch tool102inFIG. 1, can be in an activated state when the VRF signal at VRF input214is less than a threshold voltage of approximately −0.5V. In one embodiment, the VRF signal at VRF input214can be in a range of approximately −1V to −2V when plasma108is activated. The VRF signal at VRF input214can be obtained, for example, by tapping a line from an RF generator (not shown in any of the figures) that powers plasma108in etch tool102. The RF generator (not shown in any of the figures) can generate from 300 watts to 2000 watts of power, for example. In one embodiment, the VRF signal at VRF input214can be inversely proportional to the power supplied by the RF generator (not shown in any of the figures).

Also shown inFIG. 2, the output of VRF signal level detector250is connected to an input of power-on delay module258and to a second input of gate238at node256. Power-on delay module258can be set to delay a signal provided at the output of VRF signal level detector250by, for example, from 0 to 8 seconds. In the present embodiment, power-on delay module258can be set to delay the output of VRF signal level detector250by approximately 2 seconds. The output of power-on delay module258is connected to a second input of gate226via line260. Power-on delay module258can be configured to prevent the output signal received from the output of VRF signal level detector250from reaching the second input of gate226during a wafer chucking procedure.

FIG. 3shows a timing diagram of an ESC signal and a VRF signal during typical wafer processing, in accordance with one embodiment of the present invention. Certain details and features have been left out ofFIG. 3, which are apparent to a person of ordinary skill in the art. In timing diagram370inFIG. 3, ESC input312and VRF input314correspond respectively to ESC input212and VRF input214inFIG. 2. Timing diagram370includes ESC input312, VRF input314, chuck current372, chucking spike374, de-chucking spike382, wafer arc event378, VRF signal380, chucking region384, RF-ON region386, and de-chucking region388.

As shown inFIG. 3, chuck current372, which is inputted into an arc detect circuit, such as arc detect circuit210inFIG. 2, at ESC input312, includes chucking spike374, de-chucking spike382, and wafer arc event378. Chucking spike374can occur during a wafer chucking procedure and de-chucking spike382can occur during a de-chucking procedure in an etch tool, such as etch tool102inFIG. 1. Wafer arc event378can occur when an electric arc flows through a wafer, such as wafer106, which is situated between a plasma, such as plasma108, and a chuck, such as chuck104. Chuck current372can be between approximately 1.0 microamperes and 2.0 microamperes when chucking spike374, de-chucking spike382, or wafer arc event378are not occurring. During an occurrence of chucking spike374, de-chucking spike382, or wafer arc event378, chuck current372can be between approximately −150 microamperes and +100 microamperes.

Also shown inFIG. 3, VRF signal380, which can be inputted into an arc detect circuit, such as arc detect circuit210, at VRF input314, can have a voltage less than approximately −0.5V in RF-ON region386, which indicates that a plasma, such as plasma108inFIG. 1, is activated. In chucking region384and de-chucking region388, VRF signal380can have an appropriate voltage that is greater than approximately −0.5V, which indicates that a plasma, such as plasma108in etch tool102, is not active.

Thus, in RF-ON region386, the arc detect circuit, such as arc detect circuit210, is armed and configured to detect the occurrence of wafer arc event378. However, in chucking region384and de-chucking region388, plasma is not active and, therefore, no wafer arc event can occur. Thus the arc detect circuit, such as arc detect circuit210, can be configured to ignore chucking spike374, which occurs in chucking region384, and de-chucking spike382, which occurs in de-chucking region388, since chucking spike374and de-chucking spike382do not indicate a wafer arc event.

The operation of the present invention's arc detect circuit will now be discussed in relation toFIGS. 1 and 2. ESC signal level detection can be accomplished by the use of two comparators in ESC signal level detector218. The current flowing through chuck104can be converted to voltage at ESC input212through a standard means, since the comparators in ESC signal level detector218compare an input voltage to high and low threshold voltages. A low-comparator in ESC signal level detector218compares the ESC signal from ESC input212to the low threshold voltage of ESC signal level detector218. If ESC signal at ESC input212is below the low threshold voltage, the low-comparator outputs a logical one. If the ESC signal is not lower than the low-threshold voltage, then a high-comparator compares ESC signal to the high threshold voltage and outputs a logical one if ESC signal is higher than the high threshold voltage. If either comparator outputs a logical one, then ESC signal level detector218outputs a logical one, indicating that the ESC signal at ESC input212is above or below the acceptable range for the ESC signal. When the ESC signal falls within the desired high and low threshold range, ESC signal level detector218outputs a logical zero.

VRF signal level detector250can also utilize a comparator to make a comparison of a VRF signal at VRF input214to a desired threshold, for example, −0.5V, and output a logical one if the VRF signal at VRF input214is below the threshold, or output a logical zero if VRF signal is above the threshold. Initially plasma108has not been activated, and no current is flowing through chuck104. Then, RF voltage is applied to plasma108, and chuck104is charged during a wafer chucking procedure. During normal wafer processing, chuck current can be between approximately 1.0 microamperes and 2.0 microamperes. During an occurrence of chucking spike, a de-chucking spike, or a wafer arc event, chuck current, as measured at ESC input212, can vary from −150 microamperes to +100 microamperes. The chuck current during normal wafer processing, i.e. when a chucking spike, a de-chucking spike, or a wafer arc event is not occurring, translates to a voltage of approximately −0.5V to +0.3V at ESC input212. Thus, a chucking spike will cause the ESC signal at ESC input212to be greater than +0.3V or less than −0.5V. ESC signal level detector218can detect a chucking spike at ESC input212. However, power-on delay module258prevents VRF signal level detector250from sending a logical one to gate226for the approximate two seconds required for a chucking procedure, and thus the signal provided at the output of gate226will not indicate an occurrence of a chucking spike.

After chucking, the chuck current measured at ESC input212returns to a normal non-spiking current in the 1.0 to 2.0 microampere range. If no arc event occurs, both ESC signal level detector218and VRF signal level detector250will transmit logical ones to gate226during an occurrence of a de-chucking spike. Thus, gate226will latch storage module230during a de-chucking spike. However, during de-chucking, power-off advance module234will delay the signal from the signal stored in storage module230until such time as plasma108has been deactivated and VRF signal level detector250no longer detects a signal less than −0.5V at VRF input214. As discussed above, power-off advance for de-chucking can be approximately eight seconds, after which gate238no longer receives a logical one from VRF signal level detector250, and thus is unable to latch storage module242during an occurrence of a de-chucking spike.

If a wafer arc event occurs while arc detect circuit210is armed, gate226will latch storage module230, and after an approximate eight second delay, gate238will latch storage module242. As a result, a logical one will be stored at storage module242, which indicates that a wafer arc event has occurred during wafer processing. The signal stored at storage module242, i.e. the logical one indicating the occurrence of the wafer arc event, can be recalled at a later time at arc detect output246.

Thus, the present invention advantageously achieves an arc detect circuit that can accurately detect arc events in an etch tool while preventing detection of chucking and de-chucking spikes that can occur during respective chucking and de-chucking procedures in the etch tool. Additionally, the present invention advantageously achieves a cost-effective circuit for detecting wafer arcing in an etch tool while not requiring human or computer system monitoring.

Thus, circuit for detecting arcing in an etch tool during wafer processing has been described.