Apparatus and method for reducing the interface resistance in GaN heterojunction FETs

The interface resistance between the source/drain and gate of an HFET may be significantly reduced by engineering the bandgap of the 2DEG outside a gate region such that the charge density is substantially increased. The resistance may be further reduced by using an n+GaN Cap layer over the channel layer and barrier layer such that a horizontal surface of the barrier layer beyond the gate region is covered by the n+GaN Cap layer. This technique is applicable to depletion and enhancement mode HFETs.

FIELD OF THE INVENTION

The present technology relates to a method and apparatus for reducing the resistance between the drain or source of Heterojunction Field Effect Transistor (HFET) and the two dimensional electron gas beneath the gate.

BACKGROUND OF THE INVENTION

Due to the resistive nature of wide bandgap materials, AlXGa1-XN/GaN HFETs have historically suffered from high contact and access resistance, degrading high-frequency and power performance of these devices. Typically, ohmic contacts are made by annealing a Ti/Al-containing metal stack in order to drive metal through the wide bandgap Al-containing Barrier layer and contact the two-dimensional electron gas (2DEG) below. However, this approach has the disadvantages of inconsistent contact resistance, rough metal morphologies, and a lack of flexibility in device design. Ohmic contact regrowth, in which contact material is regrown after processing steps including masking and/or etching, has been explored as an alternative to this technique with limited success [1-4]. If successful, some advantages of ohmic contact regrowth would include: possible etching of the wide bandgap Al-containing Barrier layer in the contact regions, selective growth of bandgap-engineered or highly-doped material for ultra-low contact resistance and electric field profile modification, greater flexibility in device design and scaling such as reducing the effective source-drain distance for improved high-frequency performance, and the possibility of using non-alloyed metal contact stacks.

In “Low-resistance Ohmic contacts for high-power GaN field-effect transistors obtained by selective area growth using plasma-assisted molecular beam epitaxy”, by S. J. Hong and K. Kim, (Appl. Phys. Lett. 89 042101 (2006)), the authors describe using selective area growth of a n+ doped GaN cap layer on the channel layer as a way to reduce the contact resistance. The present technology differs from Hong, et. al. in that Hong does not regrow the n+GaN on top of the barrier layer in the gate region. As a result, there is no bandgap engineering of the 2DEG below the exposed barrier layer near the gate.

Devices processed using the previous approaches, in which n+GaN was regrown in the contact regions generally resulted in relatively high contact and access resistances. An annealing step subsequent to disposing the source or drain contact will not substantially affect the resistance between the source/drain and the channel layer.

SUMMARY OF THE INVENTION

Group III—Nitride wurtzite semiconductors are useful for fabricating Heterojunction Field Effect Transistors because when used in a (Gallium) polar orientation a two dimensional electron gas (2DEG) may be engineered in below the gate region. The ability to engineer the 2DEG below the gate region may be exploited to improve the device's interface resistance. Bandgap engineering is particularly useful for GaN devices although the techniques and technology herein are applicable to other Group III—Nitride compositions.

The problems of high resistance between the source/drain contact and the two dimensional electron gas (2DEG) in the gate region of a field effect transistor is at least partially solved by exposing the Barrier Layer on at least one side of the gate then regrowing a doped Cap layer of crystalline doped Group III—Nitride on the device, including the exposed Barrier Layer. The Barrier layer is exposed outside the gate region to form a ledge. By bandgap engineering through the use of particular thicknesses and compositions of the Barrier Layer and the doped Cap layer, the 2DEG charge density can be increased in the interface area between the source/drain contacts and the channel layer while not substantially perturbing the charge density below the gate. The result is significantly reduced interface resistance between the source/drain and the channel layer, even for enhancement mode devices.

Preferred characteristics of the doped Cap layer are a material of n+GaN with a doping greater than 7×1019per cm3, and a thickness chosen to increase the charge density in the two dimensional electron gas at the interface between the source/drain and the two dimensional electron gas.

In one embodiment, the invention is an HFET device with reduced resistance comprising a substrate, a channel layer disposed on the substrate and a first contact disposed on the channel layer; and a barrier layer disposed on the channel layer such that a gate region is defined. This embodiment comprises a gate contact disposed on the barrier layer such that a portion of the barrier layer between the gate contact and the first contact is not covered by the gate contact and forms an exposed ledge of the barrier layer. In addition, the portion of the channel layer below the exposed ledge of the barrier layer defines an interface and there is a regrown cap layer disposed on the channel layer and on the exposed ledge of the barrier layer such that a charge density in the interface is greater than an alternate charge density without the regrown cap layer.

In other embodiments, the previous embodiment where the regrown cap layer is doped to a concentration greater than 2×1013per cm2, the thickness of the channel layer below the gate region is greater than the thickness of the channel layer not below the gate region, the channel layer comprises GaN and barrier layer comprises AlGaN, the exposed ledge has a width of 20 to 500 nm, a cap layer may be disposed on the barrier layer, the exposed ledge of the barrier layer is delta doped, the delta doped exposed ledge of the barrier layer comprises silicon to a concentration of 2×1013per cm2.

In another embodiment, an HFET device with reduced resistance comprising: a substrate, a channel layer disposed on the substrate and a first contact disposed on the channel layer; a barrier layer disposed on the channel layer such that a gate region is defined; a gate contact disposed on the barrier layer such that a portion of the barrier layer between the gate contact and the first contact is not covered by the gate contact and forms an exposed ledge of the barrier layer; wherein the portion of the channel layer below the exposed ledge of the barrier layer defines an interface; and means for increasing a charge density in the interface. The previous embodiment wherein the channel layer further comprises GaN, the barrier layer further comprises a cap layer, or the cap layer further comprises a dielectric layer.

In another embodiment, the invention is a method of reducing the interface resistance in an HFET device, the method comprising: forming a device comprising a substrate, a channel layer, a barrier layer, a gate and a gate region; exposing a portion of the barrier layer in the gate region to form a ledge; regrowing a cap layer on the channel layer and the exposed ledge of the barrier layer; forming a gate, source and drain on the device. Another embodiment comprises the previous embodiment where the method further comprises thinning the channel layer outside the gate region or cleaning the exposed ledge of the barrier layer. or cleaning of the exposed ledge with hydrogen.

In another embodiment, the invention is a method of reducing the interface resistance in an HFET device, the method comprising: forming a device comprising a substrate, a channel layer, a barrier layer, a gate and a gate region; exposing a portion of the barrier layer in the gate region to form a ledge; engineering a charge density below the exposed ledge of the barrier layer such that the charge density below the exposed ledge of the barrier layer is greater than the charge density not below the exposed ledge of the barrier layer; forming a gate, source and drain on the device whereby engineering the charge density below the exposed ledge of the barrier layer is defined to mean selecting the materials, composition and thicknesses of the barrier layer.

In another embodiment, the method of the previous embodiment further comprising: a step of cleaning the exposed ledge of the barrier layer before engineering the charge density below the exposed ledge of the barrier layer, or the channel layer comprises GaN and the barrier layer comprises AlGaN, or wherein the step of engineering the charge density below the exposed ledge of the barrier layer further comprises regrowing a cap layer on the exposed ledge of the barrier layer, or a step of disposing a cap layer on the barrier layer after exposing a portion of the barrier layer, wherein the regrown cap layer comprises n+GaN.

DETAILED DESCRIPTION

In the following detailed description, only certain exemplary embodiments of the present technology are shown and described, by way of illustration. As those skilled in the art would recognize, the described exemplary embodiments may be modified in various ways, all without departing from the spirit or scope of the present technology. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not restrictive.

The present technology reduces the interface resistance between a source or drain contact and the two dimensional electron gas below the gate through a GaN Ohmic Regrowth and Extension (GORE) technique. CompareFIG. 1AwithFIG. 1B.FIG. 1Ashows a prior art structure for a depletion mode (D-mode) or enhancement mode (E-mode) device100. The device100comprises a Substrate110, an optional Buffer layer120, and a Channel Layer130. The character of the device100(enhancement mode or depletion mode) is determined by the charge density in the 2DEG (two dimensional electronic gas)167between the Barrier layer140and Channel Layer130. The choice of thickness and composition of the Barrier layer is part of the bandgap engineering to produce the 2DEG167below the gate170. Note that inFIG. 1Athe boundary between the Source/Drain region150/180and the Channel layer130in the region163does not overlap with the 2DEG167below the gate nor is the Channel layer130thinned outside the gate region.

FIG. 1Bof the device101of the present technology is similar toFIG. 1Aexcept in the region163and the effect on the 2DEG167in that region. The bandgap engineering of the 2DEG167may include adding particular thicknesses of a Cap layer145. The Cap layer145may be doped to reduce the resistance between the source/drain regions150/180and the channel layer130. By cutting back or etching back the sidewall/passivation layer165the Barrier Layer140is at least partially exposed. The Cap layer160may be regrown to a thickness in the region163such that the charge density in the 2DEG167in the region163is increased. The increased available charge carriers in the 2DEG167in the region163reduces the interface resistance RInterfacebetween the Source/Drain region150/180and the channel130. This interface resistance is further reduced by the n+ doping of the Cap layer160to form a Doped Cap Layer160. In one preferred embodiment of this technology the surface164of the exposed ledge in the region163may be further doped with silicon in a process known as Silicon Delta Doping prior to adding the GaN cap layer. Details of the silicon doping (also known as modulation doping) are described in pending patent application “Doped Channel GaN Double Heterojunction Field Effect Transistor” by Miroslav Micovic and Adam Conway, application Ser. No. 11/396,366 filed Mar. 31, 2006 and incorporated by reference in its entirety as though fully set forth herein.

The GaN Cap layer145is preferably created by molecular beam epitaxy (MBE) to control the number of atomic layers built. This is preferable to starting with a thick layer and then using a dry or wet etch process to thin the Cap layer145to the necessary thickness because a “build up” approach allows for greater control of the built up layers than achievable through wet etching.

Preferred embodiments for the device101inFIG. 1Binclude a SiC substrate110, an optional buffer layer120of AlXGa1-XN where X is approximately 0.04 and the buffer layer is approximately 500 nm, a channel layer130of GaN approximately 40 nm thick and a Barrier layer140comprising AlXGa1-XN where X is approximately 0.25 and the layer is 2.5 to 25 nm thick. Other thicknesses are possible based on the intended operation of the device101(E-Mode or D-Mode) as determined through bandgap engineering of the device101.

FIG. 1Cshows an alternate embodiment of the present technology. This is similar to that shown inFIG. 1Bbut with an added Cap Layer166and an optional dielectric layer168in the gate region. The Cap layer166may be GaN and is part of the bandgap engineering of the 2DEG167. In addition, the etching to expose the Cap Layer166may result in a thinning of the Channel

Layer130and exposure of the Barrier Layer140. This may create a vertical edge169on the Channel layer130at the gate. When the Doped Cap Layer160is added, the RInterfaceis reduced if the vertical edge169is smoothed first. The vertical edge169may be smoothed through hydrogen cleaning or wet etching or other techniques known in the art. The Channel layer130may be doped to further reduce the resistance as described in “Doped Channel GaN DHFET”, application Ser. No. 11/396,366 filed Mar. 31, 2006. Depending on the characteristics of the Cap Layer166and the bandgap engineering, the 2DEG167may allow for depletion mode operation.

Preferred embodiments for the device102inFIG. 1Cinclude a SiC substrate110, an optional buffer layer120of AlXGa1-XN where X is approximately 0.04 and the buffer layer is approximately 500 nm, a channel layer130of GaN approximately 40 nm thick, a Barrier layer140comprising AlXGa1-XN where X is approximately 0.25 and the layer is 2.5 to 25 nm thick and a GaN Cap Layer166approximately 2.5 nm thick. Other thicknesses are possible based on the intended operation of the device102(E-Mode or D-Mode) as determined through bandgap engineering of the device102. Device102has an exposed horizontal surface of the GaN Cap layer166in the region163produced by the removal of passivation or masking layers not shown inFIG. 1C. This ledge or exposed surface of the GaN Cap Layer166in the region163is deliberate. By exposing the Cap Layer166inFIG. 1Cor the barrier layer140inFIG. 1B, the Doped Cap Layer160may be used to increase the charge density at the interface with the Channel layer130. This increased charge density at the interface is understood as being responsible for the reduced RInterfaceof devices101and102.

Without implying a limitation, regrowth of the Doped Cap layer160may be accomplished by Molecular Beam Epitaxy (MBE) or Metal Organic Chemical Vapor Deposition (MOCVD) or other techniques know in the art.

The following table show preferred embodiments of the present technology for the device shown inFIG. 1B.

The following table show preferred embodiments of the present technology for the device shown inFIG. 1C.

InFIG. 2the various components of the resistance between the Source/Drain250/280and the Channel layer230are shown. Of the components shown, the overlap of the Doped Cap layer260over the Barrier layer240in the region263has an unexpected affect on the interface resistance, RINTERFACE.

FIGS. 3A-Fshow the preferred process steps in creating the technology described here. The reader skilled in the art will realize not all the steps necessary are shown and variations on these steps are possible while still preserving the technology described herein

InFIG. 3A, one starts with a Substrate310, an optional Buffer layer320and a Channel layer330. A Barrier layer340of AlXGa1-XN 0≦X≦1 is formed in the gate region. A filler372is used to hold the place of the gate metal. SiN sidewalls365and SiO2 mask375may be added or are the final result of intermediate steps not shown here. If the sidewalls are SiN while the mask is SiO2 then etchants may be hydrogen fluoride or buffered oxide etchant. Alternatively, sidewall365may be formed of SiO2 while the mask may be of SiN. This alternative changes the etchant used to boiling phosphoric acid.

InFIG. 3Bthe mask375is removed through selective wet etch using Buffered Oxide etchant (for a SiO2 mask), HF or other techniques known in the art. This exposes the Barrier layer340in the region363to form a ledge for a width beyond the gate region. This horizontal exposed surface364of the Barrier layer340beyond the gate is preferably between 20 nm and 500 nm with 260 nm preferred. InFIG. 3Ca Doped Cap layer360is regrown, in one embodiment, of n+ doped GaN. Regrowth of the Doped Cap layer360may be accomplished through molecular beam epitaxy (MBE) and metal organic chemical vapor deposition (MOCVD). If MBE is used to regrow the Barrier Layer or Cap layer then regrowth may be in increments of a single monolayer of the regrowth material. For GaN materials the regrowth layer increment may be as little as 0.26 nm thick. The thickness of the Doped Cap layer360over the exposed Barrier layer340is engineered to increase the charge density in the underlying 2DEG. The thickness of a n+GaN Doped Cap layer360is preferably between 20 and 100 nm. The specific thickness of the Doped Cap Layer360is engineered to provide an increased charge density in the 2DEG below the gate at the interface between the Barrier Layer340and the Channel Layer330, i.e. in the region363. If the Doped Cap Layer360is GaN then the regrowth of the Doped Cap layer360results in formation of polycrystalline GaN355in regions such as on top of the Gate372.

InFIG. 3Cthe polycrystalline GaN355(or other material left over from the regrowth process) is removed, by way of example and not limitation, through a wet etch process. The gate filler372shown inFIG. 3D, which may be silicon, may be removed through a sacrificial wet etch process. A metal plating operation is then used to form the gate metal374, as shown inFIG. 3E. The gate metal may be platinum or nickel or other suitable metals known to those in the art. The plating could be electroless or using a metal seed deposited by sputtering, plasma assisted atomic layer deposition or chemical vapor deposition.

Finally, inFIG. 3Fthe device is completed by adding the Source, Drain and Gate Head plating380,350and370respectively. An alternative method of making the Gate374and Gate Head370may be used by depositing nickel or platinum over a silicon filler372then annealing to form NiSi or PtSi.

An alternative embodiment of the present technology resulting in reduced interface resistance includes, by way of example and not limitation, includes intentionally roughening the exposed horizontal surface364of the Barrier layer340in the region363. Other alternatives include treating the horizontal surface364of the exposed Barrier layer340through wet chemical etching, Si delta doping or hydrogen cleaning before regrowth of the Doped Cap layer360.

In one embodiment the Channel layer330may be exposed and thinned with a dry etch process when the Barrier layer340is exposed. Since the dry etch process may damage the Channel Layer330, the dry etch process may be followed by a wet etch process to clean and smooth the vertical edge of the exposed Channel Layer330as well as the vertical edge of the exposed Barrier Layer340. Ammonia diluted in a 10:1 ration may be used as a chemical etchant although diluted KOH may be used also. The process may be further refined by using a photo assisted wet chemical etch.

The exposed ledge364of the Barrier Layer340may be doped in the region363as indicated by the arrow inFIG. 3Bto reduce the interface resistance between the Source/Drain350/380and the Channel layer330. The exposed ledge364of the Barrier Layer340may be delta doped with silicon to a concentration of 2×1013to 1014per cm2by MBE or other techniques know in the art.

In one embodiment, an optional additional step may be added after the Barrier layer340is exposed to use hydrogen cleaning prior to the regrowth of the Doped Cap Layer360. The hydrogen cleaning is accomplished by using hydrogen in a Reactive Ion System etching step or by using an in situ thermally cracked atomic hydrogen source or hydrogen plasma in an MBE apparatus.

In an alternative embodiment, the Channel Layer330may be topped with a Barrier Layer340and a Cap Layer. The Cap Layer is not shown inFIG. 3but shown as166inFIG. 1C. This may necessitate a Dielectric layer168between the Cap Layer166and the Gate170inFIG. 1C.

The sidewall365may include a passivation layer between the gate372and the barrier layer340.

FIG. 4shows the range of Barrier layer340thicknesses in nanometers and compositions for this technology as the striped area401. This striped area401is defined by two straight lines, Thickness in nanometers is approximately −40/45*X+10 8/9 and thickness is approximately −0.5*X+55 where X is the percentage composition of the AlXGa1-XN Barrier layer340and Thickness is the thickness of the Barrier layer340in nanometers. These two lines define the boundary of the barrier composition and thickness for preferred embodiments of this technology. The specific composition and thickness will depend on the desired operation of the device, E-Mode or D-Mode, and the desired thickness of the n+GaN Doped Cap layer360. The corresponding n+GaN Doped Cap layer360thickness over the Barrier layer340is 20-100 nm. The doping level of the n+GaN Doped Cap layer360is 1019per cm3to 1020per cm3. In one preferred embodiment the dopant is silicon.

FIG. 5Ashows the calculated conduction band profiles for AlXGa1-XN/GaN HFETs with varying surface terminations andFIG. 5Bshows the calculated 2DEG densities for AlXGa1-XN/GaN HFETs with varying: surface terminations such as none (unpassivated), metal gate, SiN passivated and a n+GaN cap, AlXGa1-XN Barrier layer compositions (X), and AlXGa1-XN Barrier layer thicknesses. The surface barrier heights inFIG. 5Awere calculated to be 3.2, 2.7, 1.6, and 0 eV for Unpassivated, Gated Metal, SiN passivated, and n+GaN Doped Cap terminated surfaces, respectively.

FIG. 5Bshows the charge density in the 2DEG as a result of bandgap engineering through the choice of Barrier layer340and n+GaN Doped Cap layer360composition and thickness. Significantly, the charge density for the 3 nm Barrier layer340, where X is approximately 1.0 for the AN composition (column 4) was 3.2×1013per cm2while the charge density for the same composition but without the Cap layer360(column 1) was less than 5×1012per cm2for a factor of six increase in charge density. The increase is a factor of 280 for the 2 nm thick Barrier layer, X is approximately 1.0, (column 4) over the unpassivated surface termination (column 1).

The epitaxial structures used were typical polarization-doped double-heterojunction AlXGa1-XN/GaN field-effect transistors. The structure in5A comprised 20 Å GaN Cap Layer360, 150 Å Al0.25Ga0.75N Barrier layer340, 300 Å GaN Channel330, and Al0.04Ga0.96N Buffer layer320. The epi structure in5B comprised 20 Å GaN Cap360, variable composition (X is approximately 0.25, 1.0) and thickness (20 Å, 30 Å, 150 Å and 300 Å), AlXGa1-XN/GaN Barrier layers340, 300 Å GaN channel330, and Al0.04Ga0.96N buffer layer320. The calculated 2DEG densities inFIG. 5Bfor composition X is approximately 1.0 and thickness of 20 Å for unpassivated and gate-metal passivated surfaces (columns 1 and 2) were less than 1011per cm2and are not shown.FIGS. 5Aand B illustrate using an n+GaN cap (column 4 inFIG. 5B) gives the greatest increase in charge density and hence the greatest reduction in interface resistance between the Channel layer and the Source/Drain.

An alternative epi structure comprising 500 Å n+GaN regrowth Cap layer160on an AlN/GaN Barrier layer140with a GaN Channel130and Al0.04Ga0.96N buffer layer120, not shown, had an access resistance of 0.11 Ω-mm.

As used herein, the term “Group III—nitride” refers to those semiconducting compounds formed between Nitrogen and the elements in Group III of the periodic table, usually Aluminum (Al), Gallium (Ga), and or Indium (In). The term also refers to ternary and quaternary compounds, such as AlGaN, InGaN, and AlInGaN. As well understood by those in this art, the Group III elements can combine with Nitrogen to form binary (e.g., GaN), ternary (e.g., AlGaN and AlInN), and quaternary (e.g., AlInGaN) compounds. The embodiments of the technology described above are generally based on a Substrate110of silicon carbide. Other substrate materials are possible such as AN, GaN, Si, Lithium Niobate and Boron Nitride. Alternative Channel Layer130, Barrier Layer140, and Cap layer160materials include the Group III—nitride materials described above.