Method of making circuitized substrate

A method of making a circuitized substrate in which the substrate's commoning bar, used during the plating of the circuitry on the substrate, is terminated from the various conductors using a laser. In a preferred embodiment, the laser acts through a dielectric layer (soldermask) which is applied over the circuitry, including the commoning bar and connected parts. The laser may also be used to expose selected ones of the circuit's other parts, including various pads used to accommodate a wirebond (from a chip) and also solder balls for eventual placement of the substrate on a larger circuit board.

TECHNICAL FIELD

The invention relates to the manufacture of circuitized substrates such as printed circuit boards, chip carriers, and the like. More specifically, it relates to such substrates which include a plated circuit pattern on at least one surface thereof designed to accommodate one or more electronic components such as a semiconductor device (chip).

BACKGROUND OF THE INVENTION

Various types of circuitized substrates having plated, e.g., electroplated, circuitry thereon or as part thereof are known in the art, including those made and sold by the assignee of this invention. Examples of such substrates, including those of the integrated circuit (or semiconductor chip or device) category and various methods of manufacturing same are described in the following U.S. Letters Patents:

One particularly attractive circuitized substrate made and sold by the assignee of the invention is called the HyperBGA chip carrier, which includes a laminate substrate-conductor layer structure on which is positioned one or more semiconductor chips. (HyperBGA is a registered trademark of Endicott Interconnect Technologies, Inc.). The carrier is then positioned on and electrically coupled to a printed circuit board (PCB) or other suitable substrate and this entire subassembly in then utilized in an electronic assembly such as a personal computer, server, etc. The latter assemblies are often referred to generically in the industry as “information handling systems”.

Examples of such a chip carrier are defined in filed applications Ser. No. 10/394,135 and Ser. No. 10/394,107, both filed Mar. 24, 2003 and assigned to the same assignee as the invention.

Yet another chip carrier made and sold by the assignee of this invention is referred to as a wirebond, laminate chip carrier in which the chip is coupled to surface conductors by wirebonds. In the typical HyperBGA carrier, the chip is coupled to the surface conductors on the substrate by solder ball connections.

In the formation of such laminate substrates, if electroplating is utilized, a “commoning bar” is typically used as part of the circuitry to form a common connection to the desired circuit elements, e.,g., pads or lines, being plated up with the desired metal, e.g., copper. Such a process requires the use of various masking steps in combination with photolithographic processing, both adding cost to the final product.

The present invention overcomes the aforementioned disadvantages associated with such substrate manufacture (applicable not only to chip carriers but also to larger PCBs and the like substrates) by eliminating these additional steps while still providing an efficient, less complex process that will still assure an excellent final substrate product. Because of this, the resulting assembly using same will also inherit the beneficial advantages, especially reduced cost, thereof. It is believed that a method of making a circuitized substrate that will provide such advantages will constitute a significant advancement in the art, as will the resulting substrate and the information handling systems which utilize said product.

OBJECTS AND SUMMARY OF THE INVENTION

It is, therefore, a primary object of the present invention to enhance the art of substrate manufacture.

It is another object of the invention to provide a finished substrate which is produced in an efficient, effective manner and which can then be utilized successfully in an assembly such as described hereinabove.

According to one aspect of the invention, there is provided a method of making a circuitized substrate, comprising providing a first dielectric layer having a first surface, forming a first pattern of conductors and a second pattern of conductors spaced from the first pattern and electrically coupled thereto on the first surface of the first dielectric layer, forming a common conductive line on the first surface of the first dielectric layer electrically connected to each of the conductors of the second pattern of conductors, and thereafter terminating the electrical connections between each of the conductors of the second pattern of conductors and the common conductive line using a laser.

According to another aspect of the invention, there is provided a method of making a circuitized substrate, comprising providing a first dielectric layer having a first surface, forming a first pattern of conductors and a second pattern of conductors spaced from the first pattern and electrically coupled thereto on the first surface of the first dielectric layer, forming a common conductive line on the first surface of the first dielectric layer electrically connected to each of the conductors of the second pattern of conductors by a second conductive line, positioning a second dielectric layer substantially over the first and second patterns of conductors and common conductive line, providing openings in the second dielectric layer using a laser to expose at least portions of the conductive lines which electrically couple the second pattern of conductors to the common conductive lines, and thereafter severing the portions of the conductive lines which electrically couple the second pattern of conductor to the common conductive line.

According to yet another aspect of the invention, there is provided a circuitized substrate comprising a first dielectric layer having a first surface, first and second patterns of conductors spacedly positioned on the first surface, a plurality of connecting lines each connecting one of the conductors in the first pattern of conductors to a respective one of the conductors in the second pattern of conductors, a common first conductive line on the first surface of the first dielectric layer and a plurality of laser-severed second conductive lines which previously connected the common conductive line to the second pattern of conductors, and a second dielectric layer positioned on the first surface of the first dielectric layer.

In accordance with still another aspect of the invention there is provided an information handling system comprising an electronic package including a circuitized substrate having a first dielectric layer having a first surface, first and second patterns of conductors spacedly positioned on the first surface, a plurality of connecting lines each connecting one of the conductors in the first pattern of conductors to a respective one of the conductors in the second pattern of conductors, a common first conductive line on the first surface of the first dielectric layer and a plurality of laser-severed second conductive lines which previously connected the common conductive line to the second pattern of conductors, and a second dielectric layer positioned on the first surface of the first dielectric layer.

According to another aspect of the invention there is a method of making a circuitized substrate, comprising provided a first dielectric layer having a first surface and a second opposing surface, forming a first pattern of conductors and a second pattern of conductors spaced from the first pattern and electrically coupled thereto on the first surface of the first dielectric layer, forming a common conductive line on the second opposing surface of the first dielectric layer and electrically connected to each of the conductors of the second pattern of conductors, and thereafter terminating the electrical connections between each of the conductors of the second pattern of conductors and the common conductive line using a laser.

In accordance with still another aspect of the invention there is provided a method of making a circuitized substrate, comprising a first dielectric layer having a first surface and a second opposing surface, forming a first pattern of conductors and a second pattern of conductors spaced from the first pattern and electrically coupled thereto on the first surface of the first dielectric layer, forming a common conductive line on the second opposing surface of the first dielectric layer and electrically connected to each of the conductors of the second pattern of conductors by a second conductive line, positioning a second dielectric layer substantially over the first and second patterns of conductors and a third dielectric layer over the common conductive line, providing openings using a laser to expose at least portions of the conductive lines which electrically couple the second pattern of conductors to the common conductive lines, and thereafter severing the portions of the conductive lines which electrically couple the second pattern of conductors to the common conductive line.

In accordance with yet another aspect of the invention there is provided a circuitized substrate, comprising a first dielectric layer having a first surface and a second, opposing surface, first and second patterns of conductors spacedly positioned on the first surface, a plurality of connecting lines each connecting one of the conductors in the first pattern of conductors to a respective one of the conductors in the second pattern of conductors, a common first conductive line on the second opposing surface of the first dielectric layer and a plurality of laser-severed second conductive lines which previously connected the common conductive line to the second pattern of conductors, and second and third dielectric layers positioned on the first and second opposing surfaces of the first dielectric layer, respectively.

According to another aspect of the invention there is provided an information handling system comprising an electronic package including a circuitized substrate having a first dielectric layer having a first surface and a second opposing surface, first and second patterns of conductors spacedly positioned on the first surface, a plurality of connecting lines each connecting one of the conductors in the first pattern of conductors to a respective one of the conductors in the second pattern of conductors, a common first conductive line on the second opposing surface of the first dielectric layer and a plurality of laser-severed second conductive lines which previously connected the common conductive line to the second pattern of conductors, and second and third dielectric layers positioned on the first and second opposing surfaces of the first dielectric layer, respectively.

In accordance with still another aspect of the invention there is provided a method of making a circuitized substrate, comprising providing a first dielectric layer having a first surface and a second opposing surface, forming a first pattern of conductors on the first surface and a second pattern of conductors on the second surface and electrically coupled to the first pattern of conductors on the first dielectric layer, forming a common conductive line on the second opposing surface of the first dielectric layer electrically connected to each of the conductors of the second pattern of conductors, and thereafter terminating the electrical connections between each of the conductors of the second pattern of conductors and the common conductive line using a laser.

According to yet another aspect of the invention there is provided a method of making a circuitized substrate comprising providing a first dielectric layer having a first surface and a second opposing surface, forming a first pattern of conductors on the first surface and a second pattern of conductors on the second opposing surface and electrically coupled to the first pattern of conductors on the first dielectric layer, forming a common conductive line on the second opposing surface of the first dielectric layer electrically connected to each of the conductors of the second pattern of conductors by a second conductive line, positioning a second dielectric layer substantially over the first pattern of conductors and a third dielectric layer over the second pattern of conductors and common conductive line, providing openings in the third dielectric layer using a laser to expose at least portions of the conductive lines which electrically couple the second pattern of conductors to the common conductive lines, and thereafter severing the portions of the conductive lines which electrically couple the second pattern of conductors to the common conductive line.

In accordance with another aspect of the invention there is provided a circuitized substrate comprising a first dielectric layer having a first surface and a second opposing surface, a first pattern of conductors positioned on the first surface, a second pattern of conductors positioned on the second surface, a plurality of connecting lines each connecting one of the conductors in the first pattern of conductors to a respective one of the conductors in the second pattern of conductors, a common first conductive line on the second surface of the first dielectric layer and a plurality of laser-severed second conductive lines which previously connected the common conductive line to the second pattern of conductors, and second and third dielectric layers positioned on the first and second opposing surfaces of the first dielectric layer, respectively.

Finally, in accordance with still another aspect of the invention there is provided an information handling system comprising an electronic package including a circuitized substrate having a first dielectric layer having a first surface and a second opposing surface, a first pattern of conductors positioned on the first surface, a second pattern of conductors positioned on the second opposing surface, a plurality of connecting lines each connecting one of the conductors in the first pattern of conductors to a respective one of the conductors in the second pattern of conductors, a common first conductive line on the second opposing surface of the first dielectric layer and a plurality of laser-severed second conductive lines which previously connected the common conductive line to the second pattern of conductors, and second and third dielectric layers positioned on the first and second opposing surfaces of the first dielectric layer, respectively.

BEST MODE FOR CARRYING OUT THE INVENTION

For a better understanding of the present invention, together with other and further objects, advantages and capabilities thereof, reference is made to the following disclosure and appended claims in connection with the above-described drawings. It is understood that like numerals will be used to indicate like elements from FIG. to FIG.

“Information Handling System” as used herein shall mean any instrumentality or aggregate of instrumentalities primarily designed to computer, classify, process, transmit, receive, retrieve, originate, switch, store, display, manifest, measure, detect, record, reproduce, handle or utilize any form of information, intelligence or data for business, scientific, control or other purposes. Examples include personal computers and larger processors such as servers, mainframes, etc.

InFIG. 1, there is seen a partial circuitized substrate10according to one aspect of the invention. Substrate10includes a first dielectric layer11having an upper, first surface13thereon. A preferred material for layer11is Teflon (a trademark of E. I. duPont de Nemours and Company), with other suitable dielectric materials being fiberglass-reinforced polymer resin, and polyimide. Such materials are known in the art and further description is not believed necessary.

As stated, a preferred example of the final product utilizing substrate10is a laminate chip carrier or the like such as that made and sold by the assignee of the invention under the product name HyperBGA and the aforementioned wirebonded, laminated chip carrier. The invention is not limited, however, to the manufacture of such substrates but instead is applicable to many other circuitized substrates, including, e.g., PCBs known in the art.

On the upper surface13is formed a first pattern of electrical conductors15and a second pattern of conductors17spaced from respective ones of the first conductors15and electrically coupled thereto, as shown. In a preferred embodiment, both patterns of conductors are made of copper. As will be described below, in a preferred embodiment of the invention, the first pattern of conductors15are designed for being electrically connected directly to a semiconductor chip. In said embodiment, the second, spaced conductors17are in turn adapted for having a solder ball or the like positioned thereon so as to be electrically coupled to an exterior electronic component such as a PCB. Further description will be provided below.

In the preferred method of forming the patterns of conductors as shown inFIG. 1, these conductors are electroplated using a conventional electrolytic plating process which typically involves plating a solid copper layer and then subtractively etching portions thereof to precisely define the desired circuit patterns. In such an electrolytic process, a common conductive line19is also formed on surface13and in turn forms an integral part of the initial circuit pattern as shown inFIG. 1. Common conductive line19thus serves as a common electrical connector to all of the conductors in each pattern during the electrolytic plating. In this initial pattern, each of the first pattern of conductors15is electrically coupled to a respective one of the second pattern of conductors by a conductive line21while each of the second pattern of conductors17is in turn electrically coupled to the common conductive line19by an individual conductive line23. It is understood that the number of conductors in each of the patterns shown inFIG. 1is only representative of one possible arrangement, in that several additional such conductors for each pattern are possible (and more likely). In one example of the invention, a total of 456 internal conductors15were utilized and a corresponding number of 560 outer conductors17used. It is thus understood that respective ones of the inner conductors may be connected to more than one outer conductor according to the teachings herein. The pattern shown is also not meant to limit the invention in that there may be several alternative patterns utilized. For example, the outer conductors17may be oriented in two or more linear rows along each side of the substrate with the respective conductive lines21interleaved through the pattern to reach its corresponding outer conductor.

In a preferred embodiment, the underlying dielectric layer may in fact include several internal conductive planes having signal and/or power connections therein for being electrically coupled, e.g., using conventional plated through hole technology, to respective ones of the outer conductors17as well as inner conductors15, if desired. In the aforementioned filed patent applications defining the HyperBGA chip carrier, the carrier includes various internal conductive layers designed for this purpose. These filed patent applications are thus incorporated herein by reference. Such internal layers are also readily usable in a wirebonded, laminate chip carrier, such as the one mentioned above.

FIG. 2is a side elevational view, slightly enlarged, taken along the line2—2inFIG. 1, showing partly in cross-section, the elements shown inFIG. 1. It is again worth mentioning that although internal conductive planes are not shown in the cross-sectional view ofFIG. 2, such internal planes are preferably utilized in the present invention, as stated above.

InFIG. 3, a second dielectric layer27is shown as being positioned atop surface13of layer11and also covering the circuit pattern, including the inner and outer conductors and common conductive line. In a preferred embodiment, this second dielectric layer is a solder mask of conventional material and is in liquid form and flowed onto layer11and cured. Alternatively, the second (and third, described below) dielectric layers can be provided in dry film form and laminated onto layer11. One example of such a liquid solder mask material is sold under the product name PSR 4000 BN and is available from Taiyo, Inc., having a place of business in Carson City, Nev. With a dielectric layer11having a thickness of about 0.030 inch, and a respective circuitry pattern as shown having an approximate thickness of only about 0.0006 inch to about 0.001 inch, a second (and third, if used—see below) dielectric layer27having a thickness of 0.0015 inch is preferred.

As stated above, it was heretofore necessary in the formation of a substrate of the type taught herein to utilize a photolithographic process also involving the use of various masking steps to define the final product. It will be understood from the following, that the present invention eliminates the need for such a photolithographic process and the added expenses associated therewith.

InFIG. 4, selected portions of the second dielectric layer27are removed above the pattern of first conductors15and the second conductors17. Regarding this first pattern, the second dielectric material27is also removed from the upper surface13between such opposed conductors15, thus leaving a relatively large opening31within the second dielectric material and a relatively large portion of the upper surface13of layer11also exposed. In contrast, only the portions of material27above the respective second conductors17are removed. This is considered important in the present invention if the second conductors17are expected to accommodate a solder ball as described above (and shown below), the second dielectric thus serving as such a solder mask. Significantly, the removal of the second dielectric layer27is accomplished using a laser, e.g., a YAG or CO2laser. Simultaneously with such removal, the desired laser also terminates the connection at line23between each of the outer conductors17and the common conductive line19. Of further importance, the laser removal of material27to complete these termination results in partial removal of the material from upper surface13of layer11, as shown to the right inFIG. 4. That is, the formed opening31′ is deeper than that of large opening31and the respective openings (31″) above each outer conductor17. Partial removal of the dielectric layer11to this extent is desired to assure complete severance of line23which might have contained remnants of conductor therein should such a depth of removal not have occurred.

FIG. 7represents a perspective view of the substrate10at the step shown inFIG. 4, absent the presence of the described second dielectric layer27for enhanced illustration purposes. It is clearly seen that each of the outer conductors17has been severed from its connection to the common conductive line19. The remaining connections between these outer conductors and the corresponding inner conductors15remain intact. Thus the instant invention has shown a method of instantaneously removing desired dielectric material from selected areas above the invention's conductors as well as terminate selected ones of said conductors from the respective common conductive line used during the plating thereof such that the final pattern will not be connected together but able to operate in the desired, individual connection scheme necessary for the final package using substrate10.

In one embodiment, the outer conductive line19will remain in the final substrate but it is also within the scope of the invention to remove this conductive line. Retaining it thus saves manufacturing costs while not distracting from the overall appearance or operational capabilities of the final product.

InFIG. 5, further processing is shown for substrate10, including the addition of a semiconductor chip41and an outer solder ball43. Chip41is preferably positioned on upper surface13of layer11and adhered thereto using an appropriate conventional cement45. Once positioned, the chip's upper contact sites47are in turn electrically coupled to respective ones of the individual conductors15using a plurality of wirebonds49. Wirebond coupling is known in the art and further description is not believed necessary. Following wirebond, an encapsulant material51is positioned as shown to encase the relatively delicate wires49and protect the chip and underlying connections as shown. In addition to chip placement, a solder ball43is positioned on each of the respective outer conductors17using conventional solder ball placement apparatus. In one example, each solder ball was comprised of 63:37 tin/lead, and often referred to as a eutectic solder ball. One ball43is used for each outer conductor17, including 560 such solder balls for the substrate defined hereinabove. The structure shown inFIG. 5is thus operational as an electronic package to electrically couple the semiconductor chip to the respective outer pads17for eventual coupling to an external circuitized substrate such as a printed circuit board61(FIG. 6). When in position, the solder balls43are reflowed and a final connection occurs. The result is an electronic package having the circuitized substrate of the invention as part thereof electrically coupled to a larger circuitized substrate such as a PCB, which can then form an information handling system of the type described herein. Examples of such systems include personal computers, servers, mainframes, etc.

InFIG. 6, a chip41′ has been positioned within the large opening31as provided inFIG. 4, similarly to chip41inFIG. 5. In the embodiment ofFIG. 6, however, chip41′ is positioned over conductors15and electrically coupled thereto using respective solder balls63. Chip41′ is thus referred to as a flip chip and solder balls63are preferably also of a 63:37 tin-lead composition, compared to the composition for the outer solder balls45. An encapsulant51′ is also utilized to seal the chip and underlying connections between the chip's contact sites (not shown) on the chip's under surface to solder balls43and the connection between said solder balls and conductors15.

FIGS. 8 and 9represent an alternative embodiment of the invention. A second dielectric layer27similar to that applied in the above embodiment is applied, preferably by lamination as occurred above. Severance of the outer conductive lines23is preferably accomplished in this embodiment by initial removal (using a laser, as above) of dielectric material above the outer connecting line23, showing a first opening31′″ only to the depth of the conductor23upper surface. (It is understood that simultaneous removal of remaining selected portions of layer27may also occur at this time; however, such removal is not shown inFIGS. 8 and 9for ease of illustration.) In the next step following removal of the dielectric27above line23, the portion of line23to be removed is now removed, preferably using an etchant which etches through the line to the upper surface13of layer11. Severance of line23thus occurs. Understandably, this dual operation occurs for each of the outer connecting lines23in the desired circuit pattern for substrate10. The preferred etchant is cupric chloride, one example being available from Mallinckrodt Baker of Phillipsburg, N.J.

InFIG. 10, there is shown an alternative embodiment of the invention. In comparison to the substrate ofFIGS. 1 and 2, the substrate ofFIG. 10includes only the pattern of first conductors15on the dielectric layer's first (top) surface and the second pattern of conductors17is instead formed (preferably simultaneously with the first pattern) on the layer's second (bottom) opposing surface. Electrical coupling between patterns is through the dielectric layer using a plated through hole70. A connecting conductive line21′ couples each conductor15to the land of through hole70, as shown, and a conductive line21″ completes the coupling to conductor17on the undersurface. Conductors17and common line19(also formed on the bottom, undersurface) are coupled by conductive line23′. Understandably, line23′ is severed by the described laser to terminate the conductor-common line connection. In theFIG. 10embodiment, second and third dielectric layers27′ and27″ are applied, respectively, to the upper and lower surfaces of the substrate's initial dielectric layer and are preferably of the liquid soldermask material mentioned above.

Thus it is seen in theFIG. 10structure that the larger conductors (pads)17, which will preferably have the aforementioned solder balls bonded thereto for coupling to a second substrate (e.g., PCB) are located on the lower, undersurface of the substrate. Use of the circuitry arrangement ofFIG. 10allows for greater utilization of top surface real estate, e.g., for greater circuitry (not shown).

The embodiment ofFIG. 11is similar to that ofFIG. 10except that the second pattern of conductors17are formed on the upper surface of the substrate, as in theFIG. 1embodiment. Connection between conductors17and common line19(located on the lower, opposing surface) is accomplished using plated through holes70and two conductive lines23′ and23″. The termination (severance) is preferably accomplished at line23″ but could be achieved on the substrate's upper surface at line23′. Both second and third dielectric layers are also seen inFIG. 11. Of significance, it is possible to form common conductive line19“in board” of through hole70as opposed to the position shown in solid. This alternative position for line19is shown to the left of hole70inFIG. 11and represents a significant savings in substrate real estate, which can be used for other purposes, especially more circuitry. Understandably, only one such common line19will be used in theFIG. 11embodiment.

In both of the embodiments ofFIGS. 10 and 11, the circuitry on both sides is preferably formed simultaneously, in the manner defined for the circuitry of theFIG. 1embodiment. Further description is not believed necessary.

Thus there has been shown and described a method of making a circuitized substrate in a new and unique manner which eliminates the need for previously utilized processing steps (especially photolithographic processing) to produce an acceptable final product for market. The method as taught herein can be accomplished in a facile manner and in relatively less time than the method described in the Background above. The resulting substrate, as defined, is readily adaptable as part of an information handling system.