Method of making borderless contacts in an integrated circuit

According to one embodiment (100), a method of forming borderless contacts may include forming a composite layer over a first insulating layer (102). A contact hole may be formed through a composite layer and a first insulating layer (104). A conducting layer may then be formed (106), including within a contact hole. Portions of a conducting layer may then be removed with a composite layer as a polish stop (108), and a contact structure may be formed. A first interconnect structure and a second insulating layer may then be formed over a first insulating layer (110 and 112). A borderless contact pattern may then be etched with a composite layer as an etch stop (114).

TECHNICAL FIELD

The present invention relates generally to the fabrication of integrated circuits, and more particularly the formation of contacts in an integrated circuit.

BACKGROUND OF THE INVENTION

Many types of integrated circuits are fabricated using layers of conductive, semiconductive, and/or insulating materials. For example, an integrated circuit may include a substrate in which a number of active devices (such as transistors) are formed. Such active devices may be connected to one another by one or more conductive or semiconductive layers (referred to herein as “conducting layers”). The interconnecting conducting layers may be separated from one another by insulating layers. Insulating and conducting layers are typically deposited according to a predetermined deposition “recipe” which may define the various materials, conditions and environment used to deposit a layer. Recipes may also be used to etch or pattern an insulating or conducting layer. For example, an etch recipe may be used to form contact holes in an insulating layer, while another set of recipes may be used to pattern a conducting layer.

A conducting layer may be formed from a single conductive (or semiconductive) material. In addition, a conducting layer may also be a composite of one or more conductive (or semiconductive) materials. As just a few examples, a conducting layer may include a first layer of conventionally doped polycrystalline silicon (polysilicon) and a second layer of “silicide” (silicon-metal alloy). Alternatively, a conducting layer can include one or more metal layers and/or alloys. As just a few examples, a conducting layer can include aluminum, copper, or more complex arrangements, such as a titanium(Ti)-tungsten(W) alloy layered onto bulk aluminum, with an underlying barrier layer comprising Ti, Ti-nitride (TiN), or a Ti alloy.

Similarly, an insulating layer may be formed from a single material or a composite of materials. As just one example, an insulating layer may include a “doped” silicon dioxide (“oxide”) and/or an “undoped” silicon oxide. The doped silicon oxide can include dopant elements, such as boron and phosphorous, while the undoped silicon oxide will be essentially free of dopant elements.

An insulating layer may perform a variety of functions in an integrated circuit. For example, an insulating layer may serve to electrically isolate one conducting layer or structure from another. Further, an insulating layer may serve as the surface on which subsequent layers are formed and patterned. Therefore, in many cases it may desirable for an insulating layer to provide a relatively planar surface.

Different conducting layers may be connected to one another and/or to a substrate by contacts and/or vias. Contacts and/or vias can include contact holes that extend through one or more insulating layers. Conventionally, a contact may connect a substrate to a conducting layer, while a via may connect two different conducting layers to one another.

A conventional way of forming a contact hole in one or more insulating layers may include lithography and etch steps. Lithography can be used to form a pattern over an insulating layer (that includes the location of contact holes). An etch step can transfer the pattern onto one or more lower situated insulating layers.

One concern with certain contact structures can be the alignment of a contact with a lower conducting layer. Because a contact is usually formed by etching a hole through an insulating layer to an underlying conducting layer, it is desirable for the etched hole to be situated directly over the desired contact location in the lower conducting layer. To make the alignment of a contact with an underlying conducting layer easier, an underlying conducting layer can be formed with “borders” (also referred to as landings). A border can be a wider portion in a conducting line that provides a larger area to align a contact with. Borders may thus be used to compensate for alignment errors between a lower conducting layer and a contact hole.

A drawback to borders in conductive patterns is the increased area that such structures may require. Line pitches may have to be increased and/or the layout of conductive patterns with borders may be more complex.

One approach to reducing the area of a contact and/or via is a “borderless contact.” A borderless contact may provide a conductive connection between two different conducting layers without a border structure.

A conventional borderless contact may be formed by one or more etch steps that may define an interconnect pattern in an insulating layer. Conducting material(s) may then be deposited into the etched pattern. Portions of a conducting material on a surface of the insulating material may be removed, leaving conducting material(s) in an interconnect pattern etched within an insulating layer.

Another type of contact that may compensate for alignment errors is a “self-aligned” contact (SAC). A self-aligned contact may include a lower conducting structure (such as a transistor gate) that includes a top insulating layer and a side insulating layer (such as a “sidewall”). With such an arrangement, a contact hole can be etched without a minimum spacing requirement with respect to the lower conducting structure.

After a conducting layer has been deposited to form a contact or via, it may be desirable to remove portions of the deposited layer. As just two examples, the conducting layer may be etched back or polished back. One way to improve the controllability of such removal process is to form a “stop” layer. Compared with a layer that is being removed, a stop layer may have a slower removal rate.

Borderless contacts and/or self-aligned contacts/vias may increase the density of an integrated circuit. However, integrating particular self-aligned contacts methods into the same manufacturing process as borderless contacts may result in some drawbacks. One example of such a drawback will be described with respect to a manufacturing process shown inFIGS. 7Ato7J.

FIG. 7Ashows a side-cross sectional view of a substrate700on which a conducting structure702may be formed. A top insulating structure704and a side insulating structure706may be formed over a conducting structure702. In the particular arrangement ofFIG. 7A, a conducting structure702may include the gate of an insulated gate field effect transistor (IGFET).

InFIG. 7Ba first insulating layer708has been formed over a conducting structure702and a substrate700. InFIG. 7C, a second insulating layer710has been formed over the first insulating layer708. A first insulating layer708, as just one example, may include doped silicon dioxide. A second insulating layer710, as just one example, may include undoped silicon dioxide.

As shown inFIG. 7D, a second insulating layer710may be patterned with a lithography and etch step. A layer of photoresist712may be formed over a second insulating layer710. A pattern may be developed in a layer of photoresist712that includes a contact mask opening714at contact hole locations.

A photoresist layer712may be removed, to form a “hard” etch mask in a second insulating layer710. A self-aligned contact etch may form a self-aligned contact hole716through a first insulating layer708. A structure following such a step is shown in FIG.7E.

FIG. 7Fshows a self-aligned contact hole following a deposition of a first conducting material718into a self-aligned contact hole716.

FIG. 7Gshows a contact structure following a step that removes a portion of a first conducting material718to form a contact structure720. Such a removal step may include chemical mechanical polishing (CMP). A second insulating layer710may be a CMP stop layer that may prevents the over-polishing of a resulting contact structure. Thus, in the particular arrangement illustrated byFIGS. 7A-7K, a second insulating layer710may be a hard mask and a CMP stop layer.

As shown inFIG. 7H, a first interconnect structure722may be formed over a second insulating layer710. A first interconnect structure722may make ohmic contact with a contact structure720. A first interconnect structure722may be formed by depositing a conducting layer, and then patterning such a layer with conventional photolithographic and etch steps.

Referring now toFIG. 71, a third insulating layer724may be deposited over a first interconnect structure722and resulting contact structure720.

A third insulating layer724may be etched according to a borderless contact etch mask726to form pattern openings730in a third insulating layer724. An integrated circuit structure following a first borderless contact etch is shownFIG. 7K-Athird insulating layer724, as just one example, may include undoped silicon dioxide.

FIG. 7Kalso shows a drawback associated that may be associated the approach ofFIGS. 7A-7K. In particular, in the event there is no substantial selectivity between a first, second and third insulating layer (708,710and724), contact/via overetch, shown by overetch portion730, may occur.

SUMMARY OF THE INVENTION

According to the disclosed embodiments of the invention, methods and structures for forming an integrated circuit contact and/or via structure may include forming an insulating layer that can serve as a removal stop for a conducting material in the formation of a first contact or via. Such an insulating layer may also form an etch stop for a subsequently formed borderless contact pattern.

According to one aspect of the disclosed embodiments, an insulating layer may form a self-aligned contact hard etch mask and an etch stop for a subsequently formed borderless contact pattern.

According to another aspect of the disclosed embodiments, an insulating layer may form a self-aligned contact hard etch mask, a removal stop for a conducting material in the formation of a first contact or via, and an etch stop for a subsequently formed borderless contact pattern.

According to another aspect of the disclosed embodiments, an insulating layer may be a capping layer for a lower insulating layer and form an etch stop for a subsequently formed contact or via hole.

According to another aspect of the disclosed embodiment, an integrated circuit may include a first insulating layer, and a second insulating layer formed over the first insulating layer. The second insulating layer may be a composite of two insulating materials, and form a removal stop for a conducting material in the formation of a first contact or via and an etch stop for a subsequently formed borderless contact pattern.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Various embodiments will now be described in conjunction with a number of charts and diagrams. The embodiments set forth approaches to forming an integrated circuit that may include a “stop” layer for a borderless contact etch. Such a stop layer may also form one or more of the following: a stop layer for a lower contact structure, a “hard” contact etch mask for a lower contact structure, or a “cap” layer for a lower insulating layer.

Referring now toFIG. 1, a flow chart shows steps in a manufacturing process according to a first embodiment.FIGS. 2Ato2G are side cross sectional views illustrating various steps of the first embodiment. A first embodiment method is designated by the general reference character100, and is show to include a step102of forming a composite layer over a first insulating layer.

A portion of an integrated circuit following a step102is shown inFIG. 2A. Acomposite layer200may be formed on a first insulating layer202. A composite layer200may include at least two materials that have different responses to an applied etch. In particular, a composite layer200may include a first composite material200-1and a second composite material200-2. When a particular etch is applied to a composite layer200, a first composite material200-1may etch at a slower rate than a second composite material200-2(or vice versa).

It is understood that while the various embodiments may refer to insulating and/or conducting layers as a “first” such layers, such a term should not be construed as being limited to a first layer formed in a manufacturing process. Other layers may be formed below and/or prior to a “first” layer. Along these same lines, while an insulating or conducting layer may be referred to as a subsequent (e.g., “second,” “third” etc.) such layer, other layers may be formed between a first layer and a subsequent such layer.

A first embodiment100may continue by forming a contact hole (step104). As shown inFIG. 2B, a contact hole204may extend through a composite layer200and a first insulating layer202. A contact hole204may expose a lower conducting layer (not shown), such as an interconnect layer or a substrate. Such a lower conducting layer may include conductive and/or semiconductive materials.

It is understood that a “contact” hole may also refer to a hole formed for a contact or via. As just two examples, a contact hole may be formed between a substrate and an interconnect layer or between two interconnect layers.

Once a contact hole204has been opened, a conducting layer may be formed (step106). As shown inFIG. 2C, a conducting layer206may fill a contact hole204, and may also be formed over a composite layer200.

As shown inFIG. 1, the first embodiment100may continue with a step that removes a conducting layer with a composite layer as a stop (step108). Such a removal step108may include, as just two examples, an etch back step or more preferably, a chemical-mechanical polishing step. An integrated circuit following a step108is shown in FIG.2D. Portions of a conducting layer206have been removed, exposing a composite layer200and forming a contact structure208.

A first interconnect structure may then be formed (step110). As shown inFIG. 2E, a first interconnect structure210may be formed on, and make contact with, a contact structure208. In the particular example ofFIG. 2E, a first interconnect structure210is offset with respect to a contact structure208.

As shown by step112andFIG. 2F, a second insulating layer212may be deposited over a contact first interconnect structure210and a composite layer200.

A borderless contact pattern may then be etched through a second insulating layer212with a composite layer200as an etch stop (step114). As shown inFIG. 2G, a borderless contact pattern214may expose a first interconnect structure210. In the particular arrangement ofFIG. 2G, a first composite material200-1in composite layer200may serve as an etch stop, etching at a slower rate than a second insulating layer212.

In this way, a composite layer200may serve as a conducting material removal stop, and as a borderless contact pattern etch stop.

FIG. 3is a flow diagram of a second embodiment.FIGS. 4A-4Hare side cross sectional views of an integrated circuit manufactured according to a second embodiment.

The second embodiment is designated by the general reference character300and may include forming a first insulating layer over a conductive structure with a sidewall (step302). An integrated circuit following a step302is shown inFIG. 4A. Aconductive structure400having an insulating sidewall402may be formed on a substrate404. In the particular arrangement ofFIG. 4A, a conductive structure may include a top insulating structure406. A first insulating layer408may be formed over the conductive structure400.

A step304may include forming a composite layer over a first insulating layer. A resulting structure is shown inFIG. 4B. Acomposite layer410may be situated over first insulating layer408. In one arrangement, a composite layer410may have the same general structure as composite layer200ofFIGS. 2A-2G, including a first composite material410-1and a second composite material410-2. First composite material410-1may have a different response to an applied etch than second composite material410-2.

A second embodiment300may continue by forming a “hard” contact etch mask out of a composite layer (step306). A “hard” etch contact etch may be an etch mask formed from an integrated circuit material, rather than a layer of developed photoresist. A hard contact etch mask may include a hard etch mask opening412in a location where a contact may be formed.

Once a hard contact etch mask is formed, a contact hole may be etched (step308). An integrated circuit following a step308is illustrated inFIG. 4D. Acontact hole etch may remove a portion of a first insulating layer408that is exposed by a hard etch mask opening412and form a contact hole414therein. In the particular arrangement ofFIG. 4D, a self-aligned contact to substrate404may be formed with respect to conductive structure400.

Following the formation of a contact hole414with a composite layer410as a hard etch mask, a contact structure may be formed (step310).FIG. 4Eshows a contact structure416formed within a contact hole414. A contact structure416may include a conductive material and provide a conductive path between a substrate404and a subsequently formed conductive layer.

It is understood that whileFIG. 4Eillustrates a self-aligned contact to a substrate404, a second embodiment may include other such contacts. Self-aligned contacts may be made to thin film transistors instead of transistors formed in a bulk silicon substrate, to name but one example.

It is also understood that a contact structure416may be formed in a variety of ways. To name but two examples, a conducting layer may be deposited and then patterned, or a conducting layer may be deposited and then chemically-mechanically polished and/or etched back to form a “plug” contact structure,

A first interconnect structure may then be formed (step312). A first interconnect structure may have the same general arrangement as the first interconnect structure210described in conjunction with FIG.2E.

The second embodiment300may further include a forming a second insulating layer over a first interconnect structure (step314). A resulting integrated circuit is shown inFIG. 4G, and includes a second insulating layer420formed over a first interconnect structure418and composite layer410.

The second embodiment300may continue with a borderless contact pattern etch (step316). As shown inFIG. 4H, a borderless contact pattern422may expose a first interconnect structure418. As in the case ofFIG. 2G, in the particular arrangement ofFIG. 4H, a first composite material410-1in composite layer410may serve as an etch stop, etching at a slower rate than a second insulating layer420.

In this way, composite layer410may serve as a hard contact etch mask, and as a borderless contact pattern etch stop.

A third embodiment is shown inFIG. 5, designated by the general reference character500. A number of cross sectional views are set forth inFIGS. 6A-6Qillustrating an integrated circuit formed according to the third embodiment500.

A third embodiment500may include depositing a first insulating layer over a gate with sidewalls (step502). InFIG. 6A, a gate600may be formed on a gate insulator602over a substrate604. Sidewalls606may be formed on the sides of a gate600. A gate600may form one part of an insulated gate field effect transistor.

A first insulating layer608may be formed over a gate600. A first insulating layer608may include doped silicon dioxide. As just a two examples, a first insulating layer608may include silicon dioxide, more preferably silicon dioxide that is doped with phosphorous (phosphosilicate glass or “PSG”). Alternatively, a first insulating layer may be doped with boron and phosphorous (borophosphosilicate glass or “BPSG”).

A first insulating layer may be deposited using chemical vapor deposition (CVD), or plasma enhanced or plasma assisted CVD (PECVD and PACVD), or high density plasma (HDP) deposition, to name but a few examples. A PSG or BPSG layer can be subject to a “reflow” and/or planarization step. BPSG and/or PSG may provide advantageous reflow and/or space filling properties.

It is understood that while a first insulating layer has been discussed as including a single material (e.g., BPSG or PSG), such a first insulating layer may include layers of different materials.

A first insulating layer608may be planarized after it is deposited (step504). Planarization may include a chemical-mechanical polishing (CMP) step, as just one example. Alternatively, planarizing may be accomplished by an isotropic etching step, or by a relatively low temperature and/or short duration reflow step, but CMP is preferred. An integrated circuit following the planarization of a first insulating layer608is shown in FIG.6B.

Once a first insulating layer608has been planarized, a third embodiment500can continue with a deposition of a composite layer over a first insulating layer608(step506). Such a step506may include depositing a first composite layer material610-1on a first insulating layer608. A first composite layer material610-1may include silicon nitride. Such a silicon nitride layer may have a thickness in the range of 1500 Å to 100 Å, preferably in the range of 1000 Å to 250 Å, more preferably about 500 Å. A step506may further include depositing a second composite layer material610-2on a first composite layer material610-1. A second composite layer material610-2may include doped or undoped silicon dioxide, preferably undoped silicon dioxide (undoped silicate glass or USG). Such a USG layer may have a thickness in the range of 3000 Å to 250 Å, preferably in the range of 2000 Å to 500 Å, and more preferably about 1500 Å.

A silicon nitride layer in a composite layer may provide a different etch response than a silicon dioxide layer in a composite layer. As just one example, a silicon nitride layer may provide a high degree of selectivity to an “oxide” etch (an etch for removing silicon dioxide).

It is understood that while a composite layer610has been described that includes silicon dioxide and silicon nitride for a degree of etch selectivity, other materials may be used. As just two examples, a composite layer610may include a layer of silicon oxynitride and a layer of silicon dioxide, or a layer of silicon nitride and a layer of silicon oxynitride.

Silicon nitride may be formed by plasma enhanced chemical vapor deposition (PECVD) with silane (SiH4) as a source of silicon and ammonia (NH3), and/or nitrogen (N2) and possibly nitrous oxide (N20) as a source of nitrogen, to name but a few examples.

Silicon oxynitride may be formed by PECVD with silane or dichlorosilane (SiCl2H2) as a source of silicon and nitrous oxide as a source of nitrogen and oxygen, to name but a few examples.

A USG layer may be formed by PECVD methods, with tetraorthoethylsilicate (TEOS) as a source material. Alternatively, a USG layer may be formed with silane or dichlorosilane as a source of silicon, and nitrous oxide or nitric oxide (NO) as sources of oxygen, to name but a few examples.

A composite layer610may serve as a “capping” layer for first insulating layer608, preventing the migration of dopants from a first insulating layer and/or preventing moisture from migrating into a first insulating layer.

As shown inFIG. 5, a third embodiment500may continue by forming a contact mask over a composite layer (step508). As shown inFIG. 6D, a step508may include forming a contact mask612having a contact mask opening614therein. In one particular approach, a contact mask612may include a layer of photoresist that is deposited and then developed. To provide favorable photolithographic results, a photoresist layer may also include an antireflective coating. A contact mask opening614may be situated over locations where a contact may be formed.

It is noted that a contact hole may be formed through a composite layer610and first insulating layer608with a contact mask612functioning as an etch mask. However, in the particular approach illustrated byFIGS. 6Ato6Q, a composite layer610may be a “hard” etch mask. Accordingly, the third embodiment500may include forming an opening in the composite layer (step510). Such a step510may include etching through a composite layer610. As just one example, an opening may be formed with a reactive ion etch (RIE). An RIE etch may be a single etch step with a recipe that does not include substantial selectivity between the materials of a composite layer610. Alternatively, such an etch may include multiple etch steps that remove various composite layer610materials (such as610-1and610-2) separately. An example of integrated circuit following a step510is shown inFIG. 6E, and includes a hard mask opening616.

Using a hard mask in the place of a conventional mask of photoresist may result in advantageous improvements in contact aspect ratio. One approach illustrating such a hard mask is set forth in commonly-owned copending U.S. patent application Ser. No. 09/326,432, entitled METHOD AND STRUCTURE FOR MAKING SELF-ALIGNED CONTACTS, the contents of which are incorporated by reference herein.

After forming openings in a composite layer610, a contact mask614may be removed (step512). If a contact mask614is formed from photoresist, such a step may include removing the photoresist with a plasma etch (“ashing”).

With a hard mask in place (formed from the composite layer610), a third embodiment500may continue with a self-aligned contact etch (step514). As shown inFIG. 6G, a self-aligned contact etch may form a contact hole618to a substrate604that is self-aligned with respect to a gate600. A self-aligned contact etch, as just one example, may preferably include a substantially anisotropic RIE. Of course, other etch methods may be used in a self-aligned contact, such as a wet chemical etch, to name but one example.

In the particular method ofFIG. 5, a conducting “liner” may be deposited (step516). A conducting liner may be a material, or combination of materials, that can provide a diffusion barrier for a subsequently deposited material and/or provide a conductive layer that adheres to lower layers. A step516may include sputtering a layer of titanium (Ti), followed by a layer of titanium nitride (TiN), as just one example.FIG. 6Hshows an integrated circuit following a conducting liner deposition. A conducting liner620may be formed over a composite layer610and into a contact hole618, including an exposed portion of a substrate604. A conducting liner620may then be alloyed to a substrate (step518).

A first conducting layer may then be deposited (step520). As shown inFIG. 6I, a first conducting layer622may fill a contact hole618and be formed over a composite layer610. A first conducting layer622may include tungsten (W). A tungsten layer may be deposited with plasma vapor deposition (PVD) or CVD techniques using silane and tungsten hexaflouride (WF6) as reactant gases, as just two examples.

Portions of a first conducting layer may then be removed with a composite layer as a stop (step522). In the particular arrangement ofFIG. 6J, a step522may include a CMP step. With composite layer610functioning as a stop, first conducting layer622may be removed exposing a composite layer610and forming a “plug” contact structure624.

A third embodiment500may further include depositing a second conducting layer (step524). As shown inFIG. 6K, a second conducting layer626may be formed over a composite layer610and a contact structure624. A second conducting layer626may include titanium (Ti) as but one example. Such a titanium layer may preferably be formed by sputtering, as just one example.

A first interconnect mask may then be formed (step524). As just one example, a first interconnect mask may be formed with conventional photolithographic and etch techniques. An integrated circuit following a step524is shown inFIG. 6L. Afirst interconnect mask portion628can be formed over a second conducting layer626where a first interconnect structure may be formed.

A first interconnect structure may then be etched (step528). An etch step may remove portions of a second conducting layer to form a first interconnect structure. A first interconnect mask may then be removed. InFIG. 6M, a first interconnect structure is shown as item630.

A third embodiment500may continue by depositing a second insulating layer (step530). As shown inFIG. 6N, a second insulating layer;632may be formed over a composite layer610and contact structure624. In one particular arrangement, a second insulating layer632may include silicon dioxide. Silicon dioxide may be formed by PECVD with tetraorthoethylsilicate (TEOS) as a source material. Alternatively, silicon dioxide may be formed with silane or dichlorosilane as a source of silicon, and nitrous oxide or nitric oxide (NO) as sources of oxygen, to name but a few examples.

A second insulating layer may be subsequently planarized according to conventional techniques, such as a chemical mechanical polishing and/or an etch back step, to name but two examples.

A borderless contact mask may then be formed over a second insulating layer (step532). As shown inFIG. 60, a borderless contact mask634may include pattern openings636corresponding to a desired contact pattern. A borderless contact mask634may be formed with conventional photolithographic techniques that develop a layer of photoresist. Alternate methods may include forming a “hard” mask, as just one example.

With a borderless contact mask in place, a borderless contact etch may take place (step534). As shown inFIG. 6P, a borderless contact etch may remove exposed portions of a second insulating layer632and a borderless contact pattern638may be formed. A borderless contact etch may be selective between a portion of a composite layer610and a second insulating layer632. As just one example, a second insulating layer632may include silicon dioxide while a composite layer610may include silicon nitride and/or silicon oxynitride. In such an arrangement, a borderless contact etch may be an oxide (i.e., silicon dioxide) etch.

With a borderless contact pattern formed in a second insulating layer, a borderless contact structure may be formed (step536). As shown inFIG. 6Q, a borderless contact pattern may be removed, and a third conducting layer may be deposited into a borderless contact pattern638. In one particular arrangement, a third conducting layer may include aluminum, deposited by sputtering and/or plasma enhanced chemical vapor deposition techniques. Portions of a third conducting layer may then be removed, by way of an etch back step and/or a chemical-mechanical polishing step, to name but two examples. A borderless contact structure640may be coupled to a first interconnect structure630and/or a contact structure624.

It is understood that in the particular arrangement illustrated byFIG. 6Q, a borderless contact structure640is not a contact or via, but may include a conductive line extending through a second insulating layer632that is connected to one or more first interconnect structures (such as630). Further, while the arrangement ofFIGS. 6Ato6Q illustrates a borderless contact structure formed with a single etch step, other borderless contact structures may be formed. As just one example, a borderless contact pattern may be formed with multiple etch steps and/or include integral contacts and/or vias. A conventional “dual damascene” borderless contact arrangement is but one example of such an alternate arrangement.

In this way, a third embodiment500may include a composite layer that may be a capping layer for an underlying insulating layer, a hard etch mask for an underlying insulating layer, a stop layer for a conducting layer removal step (such as CMP), and a stop layer for a borderless contact pattern etch.

A structure formed according to the various embodiments may include a first insulating layer, an intermediate layer (such as a composite layer), and a second insulating layer formed over the intermediate layer. A contact or via structure may extend through a first insulating layer and intermediate layer. An intermediate layer may include a material that may function as a removal stop (such as a CMP stop or etch back stop).

A structure formed according to the various embodiments may further include a borderless contact structure that extends through a second insulating layer and has a conductive connection to a contact or via. An intermediate layer may further include a material having different etch properties than a second insulating layer and may function as an etch stop for a borderless contact pattern formed in the second insulating layer.

It is understood that while the various particular embodiments have been set forth herein, methods and structures according to the present invention could be subject to various changes, substitutions, and alterations without departing from the spirit and scope of the invention.