Memory system power management

An aspect includes a method for receiving a memory allocation request for a logical partition. Partition mirroring is enabled for the logical partition. Unscrubbed memory is allocated to both a first and a second copy of the logical partition, with the second copy of the logical partition mirroring the first copy of the logical partition. Scrubbing of the first and second copy of the logical partitions is initiated. Subsequent to initiating the scrubbing one of the first and second copy of the logical partition is selected and partition mirroring is disabled for the logical partition. The first copy of the logical partition is deallocated based on selecting the second copy of the logical partition. The second copy of the logical partition is deallocated based on selecting the first copy of the logical partition. The copy that is selected will continue to be scrubbed on a periodic based.

BACKGROUND

The present invention relates to computer memory systems, and more specifically, to memory system power management.

Error-correcting code (ECC) memory is a type of computer data storage that can detect and correct the most common kinds of internal data corruption. Typically, ECC memory maintains a memory system that is immune to single-bit-errors. Data that is read from each memory location (e.g., a word) is always the same as the data that had been written to the location, even if one or more bits actually stored have been flipped to the wrong state. Dynamic random access memory (DRAM) devices often include extra memory bits and logic to exploit these extra memory bits to correct single bit errors in a memory bit word.

In contemporary memory systems, a memory controller scans systematically through locations in a DRAM to perform a scrub operation on each memory location in the DRAM. Memory scrub operations include reading from a memory location in a memory device, correcting single bit errors (if any) in the read data with an ECC, and writing the corrected data back to the same memory location. During the scrub process, an ECC decoder that is internal to the DRAM is used to detect and correct bit errors. By scrubbing each memory location on a frequent enough basis, the probability of encountering uncorrectable multiple bit errors is reduced. Though scrubbing provides benefits in terms of increased reliability, availability, and serviceability (RAS), it also requires additional logic in a memory controller to manage the read operation by inserting cycles in the scheduler queue, and it consumes additional power.

The trend of increasing memory system capacity has led to an increase in the amount of unused memory and thus, an increase in the power penalties experienced by memory systems when they scrub unused memory. One approach to decreasing the power penalties is to scrub unused memory right before allocation. This approach can result in an impact to performance as memory allocations will experiences relatively significant delays due to the allocation having to include a scrub of the memory. Another approach is to scrub unused memory at a slower rate, which may have the drawback of a decreased ability to detect a soft error rate, and thus RAS is traded for power savings.

SUMMARY

Embodiments include a method, system, and computer program product for power management of a memory in a computer system. A method includes receiving a memory allocation request for a logical partition. Partition mirroring is enabled for the logical partition. Unscrubbed memory is allocated to both a first and a second copy of the logical partition, with the second copy of the logical partition mirroring the first copy of the logical partition. Scrubbing of the first and second copy of the logical partitions is initiated. Subsequent to completing the scrubbing, one of the first and second copy of the logical partition is selected and partition mirroring is disabled for the logical partition. The first copy of the logical partition is deallocated based on selecting the second copy of the logical partition. The second copy of the logical partition is deallocated based on selecting the first copy of the logical partition. The copy that is selected will continue to be scrubbed on a periodic based.

DETAILED DESCRIPTION

Embodiments described herein are directed to conserving power in a memory system by scrubbing only memory that is currently being used, and not scrubbing memory that is currently unused. To mitigate the risk of encountering undetected uncorrectable errors in unscrubbed memory, embodiments utilize memory mirroring to provide backup memory until at least one copy is determined to be free of uncorrectable errors. Embodiments utilize the partition memory features of a hypervisor to enable mirroring for the memory allocation process, with unscrubbed memory being allocated to both the mirrored and mirroring copies. Both copies can be scrubbed at a predetermined rate and if an error is identified in one copy the error can be mitigated, by recovering data from the other copy. Embodiments continue to scrub both copies until at least one copy is proven to be good as determined, for example, by detecting less than a threshold number of errors during the scrub process. Once a good copy is identified, the mirroring is turned off and the other copy is deallocated and moved to an unused pool of memory. The scrub process is no longer performed once the other copy is moved to the unused pool of memory. As described herein, embodiments can mitigate the risk of not scrubbing before allocating unused memory and at the same time save the “time” overhead of scrubbing before allocation, by uniquely leveraging partition mirroring.

In virtualized computer systems, a hypervisor manages the memory allocation and deallocation (or release) processes of logical partitions. In contemporary virtualized computer systems both allocated and unallocated memory portions are scrubbed to ensure that unused memory is kept ready without any errors. In these computer systems, RAS is valued over power savings as unused memory that is bad (e.g., has more than a threshold number of errors detected during scrubbing) can be removed from the free memory pool. Since the unallocated memory portion does not contain data that is being used by a logical partition, the scrubbing of unallocated memory portion may not be useful and it uses memory system power. The amount of memory system power wasted, or the power penalty, caused by scrubbing unallocated memory locations increases proportionally to the size of the unused memory area (e.g., less memory usage by applications has more penalty and vice versa).

Embodiments described herein can be utilized to optimize the scrub operation in virtualized systems in order to conserve memory system power without compromising on RAS capabilities.

In contemporary memory systems, a memory controller typically drives a data scrub operation by specifying a word location to be scrubbed. The memory controller passes the address of the word location to be scrubbed to the memory by registering the scrub command.

As used herein, the term DRAM is used to refer to one particular type of memory that may be utilized by embodiments. Other types of memory devices such as, but not limited to: static random access memory (SRAM) and embedded DRAM (EDRAM) may also be utilized by embodiments.

FIG. 1illustrates a block diagram of a system100, which is a computer system that supports memory system power management in accordance with one or more embodiments. The system100depicted inFIG. 1includes a computer processor102, memory106including multiple memory devices (e.g., DRAMs), and a memory controller104for reading and storing data in the memory106via an interface110. Collectively, the memory controller104and the memory106are referred to as a memory system105. The computer processor102can be a single core or multi-core processor. In one or more embodiments the memory controller104is coupled to the computer processor102and receives read or write requests from the computer processor102.

The system100is one example of a configuration that may be utilized to perform the processing described herein. Although the system100has been depicted with only a memory106, memory controller104, and computer processor102, it will be understood that other embodiments would also operate in other systems including additional elements, e.g., multiple computers processors102and multiple levels of memory106. In an embodiment, the memory106, memory controller104, and computer processor102are not located within the same computer. For example, the memory106and memory controller104may be located in one physical location (e.g., on a memory module) while the computer processor102is located in another physical location (e.g., the computer processor102accesses the memory controller104via a network). In addition, portions of the processing described herein may span one or more of the memory106, memory controller104, and computer processor102.

Turning now toFIG. 2, a block diagram of components of an exemplary system for memory system power management is generally shown according to one or more embodiments. The system shown inFIG. 2can be characterized as a virtual machine design, or virtualized system, that includes partitions202, a hypervisor204, and memory206. The system shown inFIG. 2includes a plurality of logical partitions202that share common processing resources among multiple processes. The system shown inFIG. 2may include a single computing machine having one or more processors208. The logical partitions202can logically comprise a portion of a system's physical processor(s)208and memory206. Each logical partition202can operate as if it is a separate computer and can host an operating system that includes virtual processors.

The hypervisor204shown inFIG. 2can assign physical resources to each logical partition202. The hypervisor204can manage the system's processor, memory (or storage), and other resources to allocate resources to operating systems executing in the logical partitions202. As shown inFIG. 2the hypervisor204can access memory mirroring logic210that is configured to enable and disable memory mirroring. In addition, the hypervisor204can access memory power management logic212that is configured to optimize the scrub operation in virtualized systems in order to conserve memory system power. In an embodiment, the hypervisor204is implemented by the POWER Hypervisor™ from IBM. The scrub logic cycles through each of the physical memory locations in the memory206used by a logical partition202to write corrected data values to physical memory206. In embodiment, the scrub logic is applied only to allocated memory214(memory that is currently being used by a partition202or the hypervisor204) in the physical memory206. In this manner, power is saved because only memory that is currently in use is being scrubbed, the rest of the memory206that is currently unused, the unallocated memory214remains unscrubbed (the scrub process is not currently being applied). In an embodiment, the scrub process also includes keeping track of a number of bit errors detected during the scrub process.

Turning now toFIG. 3, a block diagram of contents of a memory, such as memory206inFIG. 2, is generally shown according to one or more embodiments. Block302shows an example of contents of a memory prior to memory being allocated to a new partition. Block302ofFIG. 3includes a portion of the memory being used by a hypervisor and another portion being used by an existing partition. In an embodiment, both of these portions of the memory are physically located in allocated memory, such as allocated memory214inFIG. 2, which is being scrubbed. The portion of the memory labeled “unallocated” in block302is not currently being used and currently not being scrubbed (i.e., it is “unscrubbed” memory). In an embodiment, the unallocated portion of the memory is physically located in unallocated memory, such as unallocated memory216inFIG. 2, which is unscrubbed memory.

Block304shows an example of contents of a memory after memory has been allocated to a new partition and to a mirrored copy of the new partition. Similar to block302, block304ofFIG. 3includes a portion of the memory being used by the hypervisor and another portion being used by the existing partition. In addition, block304includes a portion of the memory being used by a new partition and a mirrored copy of the new partition labeled “new partition” and “new partition.” In an embodiment, all 4 of these portions of the memory are physically located in allocated memory which is currently being scrubbed. The portion of the memory labeled “unallocated” in block304is not currently being used and currently not being scrubbed (i.e., it is “unscrubbed” memory).

Block306ofFIG. 3shows an example of contents of a memory after the scrubbing process has been completed, and one of the mirrored and mirroring copies of the new partition has been selected and the other deallocated. Block306includes a portion of the memory being used by the hypervisor and another portion being used by the existing partition and the new partition. In an embodiment, all 3 of these portions of the memory are physically located in allocated memory which is currently being scrubbed. The rest of the memory labeled “unallocated” in block306is not currently being used and currently not being scrubbed (i.e., it is “unscrubbed” memory).

Turning now toFIG. 4, a process flow of memory system power management is generally shown according to one or more embodiments. The processing shown inFIG. 4can be performed by a processor such as CPU102, processor208and/or processor502. At block402, a memory allocation request for a logical partition is received, for example, by a hypervisor. Processing continues at block404where partition mirroring is enabled for the requested logical partition. At block406, unscrubbed memory is allocated to both a first (or mirrored) and a second (or mirroring) copy of the logical partition, where the second copy of the logical partition mirrors the first copy of the logical partition.

In an embodiment, a memory controller, such as memory controller104, is designed to be able to send a given write to two locations, for example two different physical dual in-line memory modules (DIMMs). The memory controller can then read from either copy, and fetch from the second copy if the first copy is bad. The memory controller can provide an address map to the hypervisor, such as hypervisor204, where the physical addresses of the two DIMMs, for example, are mapped as two different system address regions. The first system address region can be non-mirrored and can have a 1-to-1 relationship between physical and system addresses. The second system address can be mirrored and can have a 2-to-1 relationship between physical and system addresses. The mirrored and non-mirrored regions can be mapped to different system address ranges. Since the hypervisor has access to the full system address range, it can decide whether to allocate a given partition in the mirrored range or non-mirrored range. To disable mirroring for a mirrored partition, the hypervisor redefines which system address range the partition occupies.

At block408, scrubbing is initiated on both the first and second copies of the logical partition. In an embodiment, the scrubbing is performed for a predetermined time period that is selected to ensure that all of the physical memory locations are scrubbed at least once.

Processing continues at block410where it is determined whether an error (e.g., an uncorrectable error) is identified in one of the copies of the logical partition. If an error is identified, then it can be mitigated at block412by recovering data from the other copy and processing continues at block410. In an embodiment, every read done by the partition goes through an ECC check in the memory controller. If the memory controller detects an uncorrectable error on a given read, it re-does that read from the mirrored copy.

If it is determined at block410that no error is detected, then processing continues at block414where it is determined whether one of the copies of the logical partition is “good.” In an embodiment, a copy of the logical partition is determined to be a good copy when no uncorrectable errors and less than a threshold number of correctable errors are detected in the physical memory of the logical partition during the scrub process. In some cases, both copies of the logical partition may be good copies. A good copy is selected for the logical partition and at block416the mirroring is turned off, or disabled, for the logical partition.

At block418, the memory of the other non-selected copy is freed up (deallocated) and moved to the unallocated pool. As described previously, in accordance with embodiments scrubbing is not performed on the unallocated memory, and thus, the unallocated memory is unscrubbed memory.

Turning now toFIG. 5is a block diagram of a processor for memory system power management is generally shown according to one or more embodiments. The methods described herein can be implemented in hardware, software (e.g., firmware), or a combination thereof. In an exemplary embodiment, the methods described herein are implemented in hardware as part of the microprocessor of a computer, such as a personal computer, workstation, minicomputer, or mainframe computer. The system therefore includes computer501as illustrated inFIG. 5.

In an exemplary embodiment, the computer501includes processor502ofFIG. 1that is operable to perform memory system power management. The computer501further includes memory510(e.g., main memory) coupled to a memory controller515, and one or more input and/or output (I/O) devices540,545(or peripherals) that are communicatively coupled via a local input/output controller535. The input/output controller535can be, for example but not limited to, one or more buses or other wired or wireless connections, as is known in the art. The input/output controller535may have additional elements, which are omitted for simplicity, such as controllers, buffers (caches), drivers, repeaters, and receivers, to enable communications. Further, the local interface may include address, control, and/or data connections to enable appropriate communications among the aforementioned components.

The processor502is a hardware device for executing software, particularly that stored in storage520, such as cache storage, or memory510. The processor502can be any custom made or commercially available processor, a central processing unit (CPU), an auxiliary processor among several processors associated with the computer501, a semiconductor based microprocessor (in the form of a microchip or chip set), a macroprocessor, or generally any device for executing instructions.

The memory510can include any one or combination of volatile memory elements (e.g., random access memory (RAM, such as DRAM, SRAM, SDRAM, etc.)) and nonvolatile memory elements (e.g., ROM, erasable programmable read only memory (EPROM), electronically erasable programmable read only memory (EEPROM), programmable read only memory (PROM), tape, compact disc read only memory (CD-ROM), disk, diskette, cartridge, cassette or the like, etc.). Moreover, the memory510may incorporate electronic, magnetic, optical, and/or other types of storage media. Note that the memory510can have a distributed architecture, where various components are situated remote from one another, but can be accessed by the processor502.

The instructions in memory510may include one or more separate programs, each of which comprises an ordered listing of executable instructions for implementing logical functions. In the example ofFIG. 5, the instructions in the memory510can include a suitable operating system (OS)511. The operating system511essentially controls the execution of other computer programs and provides scheduling, input-output control, file and data management, memory management, and communication control and related services.

In an exemplary embodiment, a conventional keyboard550and mouse555can be coupled to the input/output controller535. Other output devices such as the I/O devices540,545may include input devices, for example but not limited to a printer, a scanner, microphone, and the like. Finally, the I/O devices540,545may further include devices that communicate both inputs and outputs, for instance but not limited to, a network interface card (NIC) or modulator/demodulator (for accessing other files, devices, systems, or a network), a radio frequency (RF) or other transceiver, a telephonic interface, a bridge, a router, and the like. The system can further include a display controller525coupled to a display530. In an exemplary embodiment, the system can further include a network interface560for coupling to a network565. The network565can be an IP-based network for communication between the computer501and any external server, client and the like via a broadband connection. The network565transmits and receives data between the computer501and external systems. In an exemplary embodiment, network565can be a managed IP network administered by a service provider. The network565may be implemented in a wireless fashion, e.g., using wireless protocols and technologies, such as WiFi, WiMax, etc. The network565can also be a packet-switched network such as a local area network, wide area network, metropolitan area network, Internet network, or other similar type of network environment. The network565may be a fixed wireless network, a wireless local area network (LAN), a wireless wide area network (WAN) a personal area network (PAN), a virtual private network (VPN), intranet or other suitable network system and includes equipment for receiving and transmitting signals.

If the computer501is a PC, workstation, intelligent device or the like, the instructions in the memory510may further include a basic input output system (BIOS) (omitted for simplicity). The BIOS is a set of essential software routines that initialize and test hardware at startup, start the OS511, and support the transfer of data among the hardware devices. The BIOS is stored in ROM so that the BIOS can be executed when the computer501is activated. BIOS or other instructions in memory510or storage520may trigger and manage execution of a stress test mode as part of a built-in self-test process.

When the computer501is in operation, the processor502is configured to fetch and execute instructions stored within the memory510, to communicate data to and from the memory510, and to generally control operations of the computer501pursuant to the instructions.

In an exemplary embodiment, where the memory system power management is implemented in hardware, the methods described herein, such as the processing shown inFIG. 4, can be implemented with any or a combination of the following technologies, which are each well known in the art: a discrete logic circuit(s) having logic gates for implementing logic functions upon data signals, an application specific integrated circuit (ASIC) having appropriate combinational logic gates, a programmable gate array(s) (PGA), a field programmable gate array (FPGA), etc.

Technical effects and benefits include the ability to optimize the scrub operation in virtualized systems in order to conserve memory system power without compromising on RAS capabilities.