Flash memory device and method for fabricating the same

A flash memory device and a method for fabricating the same is disclosed that reduces or prevents mis-operation and improves integration, which includes a semiconductor substrate having a field region and an active region; a device isolation layer on the field region including a conductive (e.g., polysilicon) layer and an insulating layer thereon; a sidewall spacer at sides of the device isolation layer; an ONO layer on the active region; a gate electrode on the ONO layer; source and drain regions at sides of the gate electrode in the active region; a passivation layer on the semiconductor substrate, having a contact hole in the drain region; and a drain electrode in the contact hole, connected with the drain region.

This application claims the benefit of the Korean Application No. P2004-31863 filed on May 6, 2004, which is hereby incorporated by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a flash memory device and a method for fabricating the same, and more particularly, to a flash memory device and a method for fabricating the same, which is suitable for improving integration in a SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) cell.

2. Discussion of the Related Art

A typical example of a nonvolatile memory device, in which data can be rewritable, is EEPROM (Electrically Erasable Programmable Read Only Memory). Generally, EEPROM devices use a floating gate type cell.

With rapid development of high-integration devices, the size of the floating gate type cell has generally decreased according to the related art. However, beyond a certain size, it is difficult to decrease the cell size since a relatively high voltage is generally used in programming and erasing modes, and it is difficult to obtain sufficient process margin for defining tunneling. For these (and other) reasons, various nonvolatile memory devices such as SONOS, FeRAM, SET and NROM have been studied actively as a substitute for the floating gate type cell. Among them, SONOS cell has attracted great attention as a nonvolatile memory device that can substitute for the floating gate type cell.

Hereinafter, a related art SONOS type nonvolatile memory device will be described with reference to the accompanying drawings.

FIG. 1is a layout of showing a unit cell of an SONOS type nonvolatile memory device according to the related art.FIG. 2Ais a cross sectional view along I–I′ ofFIG. 1.FIG. 2Bis a cross sectional view along II–II′ ofFIG. 1.FIG. 2Cis a cross sectional view of showing a pattern defect due to misalignment.

As shown inFIG. 1,FIG. 2AandFIG. 2B, the unit cell of the SONOS type nonvolatile memory device according to the related art includes a semiconductor substrate11, a device isolation layer12, an ONO layer13, and a gate electrode14. At this time, the device isolation layer12(an STI, or Shallow Trench Isolation, structure) is formed in the semiconductor substrate11, to divide the semiconductor substrate11into a field region and an active region. Also, the ONO layer13is formed by sequentially stacking a lower oxide layer13a, a nitride layer13band an upper oxide layer13cin order, wherein the lower oxide layer13ais used as a tunnel oxide layer, the nitride layer13bfunctions as a memory (storage) layer, and the upper oxide layer13cfunctions as a gate dielectric or blocking layer for preventing the loss of electric charges. Then, the gate electrode14is formed on the ONO layer13. In addition, source and drain regions15aand15bare formed at both sides of the gate electrode14in the active region of the semiconductor substrate11. Then, a drain contact hole16is formed in the drain region15b, for connection with an upper line.

In this case, the device isolation layer12is formed of an insulating layer in an STI (Shallow Trench Isolation) process. Recently, as dimensions in design rules for high integration semiconductor device decrease, the distance between the device isolation layers12becomes small. Accordingly, when the drain region15bis formed in the semiconductor substrate11between the device isolation layers12, a width of the drain region15bis also decreased, so that it is difficult to obtain a sufficient interval between the drain contact hole16and the device isolation layer12.

In case of misalignment when forming the drain contact hole16, as shown inFIG. 2C, the drain contact hole16may be formed above the device isolation layer12as well as above the drain region15b. That is, when forming the drain contact hole16, a portion of the semiconductor substrate11adjacent to the device isolation layer12may be etched, thereby generating junction leakage. Accordingly, the memory device may operate incorrectly or fail.

SUMMARY OF THE INVENTION

Accordingly, the present invention is directed to a flash memory device and a method for fabricating the same that substantially obviates one or more problems due to limitations and disadvantages of the related art.

An object of the present invention is to provide a flash memory device and a method for fabricating the same, in which it is possible to prevent mis-operation by reducing or preventing junction leakage in a drain contact hole, and to improve integration by decreasing a unit cell size in an SONOS type nonvolatile memory device.

To achieve these objects and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, a flash memory device includes a semiconductor substrate having a field region and an active region; a device isolation layer on the field region of the semiconductor substrate, wherein the device isolation layer comprises a conductive (e.g., polysilicon) layer with an insulating layer thereon; an insulating sidewall spacer at a side of the device isolation layer; an ONO layer on the active region of the semiconductor substrate; a gate electrode on the ONO layer; source and drain regions at sides of the gate electrode in the active region of the semiconductor substrate; a passivation layer on the semiconductor substrate, having a contact hole in the drain region; and a drain electrode in the contact hole, connected to the drain region.

In another aspect, a method for fabricating a flash memory device includes the steps of forming a device isolating layer having a first insulating layer, a conductive (e.g., polysilicon) layer and a second insulating layer on a field region of a semiconductor substrate; forming an insulating sidewall spacer at a side of the device isolation layer; forming an ONO layer on an active region of the semiconductor substrate, and forming a gate electrode on the ONO layer; forming source and drain regions by implanting impurity ions into the active region of the semiconductor substrate using the gate electrode as a mask; forming a passivation layer on an entire surface of the semiconductor substrate; and forming a contact hole in the passivation layer over the drain region.

DETAILED DESCRIPTION OF THE INVENTION

Hereinafter, a flash memory device and a method for fabricating the same according to the present invention will be described with reference to the accompanying drawings.

FIG. 3is a layout of showing a unit cell of an SONOS type nonvolatile memory device according to the present invention.FIG. 4Ais a cross sectional view along III–III′ ofFIG. 3.FIG. 4Bis a cross sectional view along IV–IV′ ofFIG. 3.

In the unit cell of the SONOS type nonvolatile memory device according to the present invention, as shown inFIG. 3,FIG. 4AandFIG. 4B, there are a semiconductor substrate31, a device isolation layer32, insulating sidewall spacers33, an ONO layer34, a gate electrode35, source and drain regions36aand36b, a passivation layer38, and a drain electrode37. The device isolation layer32divides the semiconductor substrate31into an active region and a field region. The device isolation layer32is in the field region of the semiconductor substrate31. Generally, the outer borders of device isolation layer32define the field region. In this case, the device isolation layer32is formed by sequentially stacking an oxide layer32a, a conductive (e.g., polysilicon) layer32b, an oxide layer32cand a nitride layer32din order. Also, the insulating sidewall spacers33are formed at the side of the device isolation layer32. Then, the ONO layer34is formed across the active region of the semiconductor substrate31. The ONO layer34comprises a lower oxide layer34a, a nitride layer34band an upper oxide layer34c. Herein, the lower oxide layer34agenerally functions as a tunnel oxide layer, the nitride layer34bfunctions as a memory (storage) layer, and the upper oxide layer34cfunctions as a blocking layer for preventing the loss of electric charges. After that, the gate electrode35is formed on the ONO layer34. The gate electrode35generally comprises a polysilicon layer (which may be [heavily] doped and/or which may further comprise a metal silicide layer thereon) that may be covered with an insulating layer (not shown). Then, the source and drain regions36aand36bare formed at both sides of the ONO layer34and the gate electrode35in the active region of the semiconductor substrate31. Also, a passivation layer38is formed on an entire surface of the semiconductor substrate31including the gate electrode35, and a contact hole is formed in the passivation layer38to expose a predetermine portion of the drain region36b. Accordingly, the drain electrode37in the contact hole is connected to the drain region36b. In this case, the contact hole for connection of the drain electrode37in the device isolation layer32is self aligned to the insulating sidewall spacers33above the drain region36b. Thus, the contact hole exposes the drain region36bof the semiconductor substrate31and part of the insulating sidewall spacer(s)33.

Although conductive layer32bgenerally comprises polysilicon (which, like gate electrode35, may be [heavily] doped and/or which may further comprise a metal silicide layer thereon), other conductors, such as aluminum, titanium, titanium nitride, tungsten, metal alloys thereof or other metals or conductive metal compounds may be employed. Also, when conductive layer32bgenerally comprises polysilicon, although not shown, an oxide layer may be formed at the side of the polysilicon layer32b. Furthermore, the conductive layer32bmay be connected with a ground terminal, which generally has the same structure as a ground gate in a general MOS transistor or ground plane in a general MOS integrated circuit.

As mentioned above, the contact hole is self-aligned to the insulating sidewall spacers33. As a result, it is not necessary to obtain or provide an interval or distance between the contact hole and the device isolation layer32. Also, as shown inFIG. 4A, the contact hole may expose part of the insulating sidewall spacer(s)33over the drain region36b.

A method for fabricating the aforementioned unit cell of the SONOS type nonvolatile memory device according to the present invention will be described as follows.

FIG. 5AandFIG. 5Bare cross sectional views of showing the process for fabricating the unit cell of the SONOS type nonvolatile memory device, along IV–IV ofFIG. 3, according to the present invention.

First, as shown inFIG. 5A, the oxide layer32a, the conductive (e.g., polysilicon) layer32b, the oxide layer32cand the nitride layer32dare sequentially stacked on the semiconductor substrate31, the semiconductor substrate31having an active region and a field region. Then, portions of the oxide layer32a, the polysilicon layer32b, the oxide layer32cand the nitride layer32dthat are over the active region of the semiconductor substrate31are selectively removed, thereby forming the device isolation layer32.

Subsequently, a well is formed by a doping process (e.g., ion implantation). Then, the polysilicon layer32bof the device isolation layer32may be oxidized, so that an oxide layer (not shown) may be formed at the side of the polysilicon layer32b.

Next, a spacer insulating material (e.g., a nitride layer) is formed on the entire surface of the semiconductor substrate31and then anisotropically etched, thereby forming the insulating sidewall spacers33at sides of the device isolation layer32.

Then, as shown inFIG. 5B, the ONO layer34is formed on the entire surface of the semiconductor substrate31. The ONO layer34generally comprises a lower oxide layer34a, a nitride layer34band an upper oxide layer34c. In this case, the lower oxide layer34afunctions as a tunnel oxide layer, the nitride layer34bfunctions as the memory (storage) layer, and the upper oxide layer34cfunctions as the blocking layer for preventing the loss of electric charges. Then, a gate material layer (e.g., comprising polysilicon, which may be [heavily] doped and/or silicided) is formed on the ONO layer34. After that, portions of the polysilicon layer and the ONO layer34are selectively removed to form the gate electrode35. Then, the gate electrode35may be oxidized before forming the source and drain regions.

Subsequently, impurity ions are implanted into the active region of the semiconductor substrate31using the gate electrode35as a mask, thereby forming the source and drain regions36aand36b, respectively. Then, the passivation layer38is formed on the entire surface of the semiconductor substrate31including the gate electrode35and the source and drain regions36aand36b, and a portion of the passivation layer38is selectively removed above the drain region36bto form the contact hole. At this time, the contact hole is formed in the device isolation layer32self aligned to the insulating layer sidewall spacers33.

After that, a conductive material is deposited on the entire surface of the semiconductor substrate31, and then is selectively removed, whereby the drain electrode37is electrically connected with the drain region36bin the contact hole.

After completing the flash memory device, the polysilicon layer32bof the device isolation layer32may be connected with a ground terminal.

As mentioned above, the flash memory device and the method for fabricating the same according to the present invention has the following advantages.

First, the contact hole for connection of the drain electrode is formed in the device isolation layer by self alignment. That is, when forming the contact hole, a predetermined portion of the device isolation layer is etched, exposing only the drain region36bof the semiconductor substrate therebelow, thereby reducing or preventing the junction leakage. Accordingly, it is possible to minimize or prevent mis-operation in the flash memory device.

Also, there is no requirement for maintaining a predetermined interval or distance between the drain electrode contact hole and the device isolation layer, so that it is possible to decrease the size of unit SONOS cell, thereby decreasing the entire chip size. Accordingly, it is possible to increase the number of chips or die in each wafer, thereby increasing the gross die per wafer, and thus, the integration of the high-integration flash memory device.