Semiconductor memory devices, methods for fabricating the same and electronic systems including the same

A semiconductor memory device may include a mold structure that includes mold insulation films and gate electrodes alternately stacked on a first substrate, a channel structure that penetrates the mold structure and intersects the gate electrodes, a block separation region that extends in a first direction parallel to an upper surface of the first substrate and cuts the mold structure, a first dam region and a second dam region spaced apart from each other, that each having a closed loop in a plan view and each cutting the mold structure, pad insulation films in the first and second dam regions that are alternately stacked with the mold insulation films and include a material different from the mold insulation films, and a through via which penetrates through the first substrate, the mold insulation films, and the pad insulation films, in the first dam region but not in the second dam region.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the benefit of priority under 35 U.S.C. § 119 from Korean Patent Application No. 10-2020-0174976 filed on Dec. 15, 2020, in the Korean Intellectual Property Office, with the contents of the above-identified application incorporated by reference herein in its entirety.

BACKGROUND

1. Technical Field

The present disclosure relates to semiconductor memory devices, methods for fabricating the same, and electronic systems including the semiconductor memory devices. More specifically, the present disclosure relates to semiconductor memory devices including a through via, methods for fabricating the same, and electronic systems including the semiconductor memory devices.

2. Description of the Related Art

In order to satisfy performance characteristics and low prices desired by consumers, there has been interest in increasing the degree of integration of semiconductor memory devices. This is in part because a degree of integration is an important factor in determining the price of the product, and as such increased density is particularly desirable.

For two-dimensional or planar semiconductor memory devices, the degree of integration is mainly determined by an area occupied by a unit memory cell, and is therefore greatly affected by the level of fine pattern forming technology. However, since the apparatuses required for miniaturization of patterns can be very expensive, the degree of integration of two-dimensional semiconductor memory devices is increasing, but is limited by cost and manufacturing factors. As a result, three-dimensional semiconductor memory devices including memory cells placed three-dimensionally have been proposed.

SUMMARY

Aspects of the present disclosure provide semiconductor memory devices in which product reliability is improved.

Aspects of the present disclosure also provide methods for fabricating semiconductor memory devices in which product reliability is improved.

Aspects of the present disclosure also provide electronic systems in which product reliability is improved.

According to some aspects of the present disclosure, there is provided a semiconductor memory device comprising a mold structure that includes mold insulation films and gate electrodes alternately stacked on a first substrate, a channel structure that penetrates through the mold structures and intersects the gate electrodes, a block separation region that extends in a first direction parallel to an upper surface of the first substrate and that cuts the mold structure, a first dam region that has a closed loop in a plane parallel to the upper surface of the first substrate and that cuts the mold structure, a second dam region that is spaced apart from the first dam region in the first direction, that has a closed loop in the plane parallel to the upper surface of the first substrate, and cuts the mold structure, pad insulation films in the first dam region and the second dam region that are alternately stacked with the mold insulation films and that include a material different from the mold insulation films, and a through via in the first dam region that penetrates through the first substrate, the mold insulation films, and the pad insulation films, wherein the through via is placed in the first dam region and is not placed in the second dam region.

According to some aspects of the present disclosure, there is provided a semiconductor memory device comprising a first substrate that includes a cell array region and an extension region arranged along a first direction, a mold structure including a mold insulation films and gate electrodes alternately stacked on an upper surface of the first substrate, a channel structure in the cell array region that penetrates through the mold structure and intersects the gate electrode, a first dam region in the extension region that has a closed loop in a plane parallel to the upper surface of the first substrate in the extension region, and that cuts the mold structure, a second dam region in the extension region that is spaced part from the first dam region in the first direction, that has a closed loop in the plane parallel to the upper surface of the first substrate, and that cuts the mold structure, pad insulation films in the first dam region and the second dam region that are alternately stacked with the mold insulation film and that include a material different from the mold insulation films, a second substrate including an upper surface that faces a lower surface of the first substrate, a peripheral circuit element on the upper surface of the second substrate, and a first through via in the first dam region that penetrates through the first substrate, the mold insulation films, and the pad insulation films, and connects a gate electrode of the gate electrodes with the peripheral circuit element.

According to some aspects of the present disclosure, there is provided a method for fabricating a semiconductor memory device, the method comprising forming a preliminary mold structure including mold insulation films and sacrificial films alternately stacked on a first substrate, forming a channel structure that penetrates the preliminary mold structure and intersects the sacrificial film, forming a block separation region that extends in a first direction parallel to an upper surface of the first substrate and cuts the preliminary mold structure, forming a first dam region that has a closed loop on a plane parallel to an upper surface of the first substrate, and that cuts the preliminary mold structure, forming a second dam region that is spaced apart from the first dam region in the first direction, that has a closed loop in the plane parallel to the upper surface of the first substrate, and that cuts the preliminary mold structure, replacing the sacrificial film outside the first dam region and the second dam region with a gate electrode, using the block separation region, and forming a through via in the first dam region that penetrates through the first substrate, the mold insulation films, and the sacrificial films.

According to another aspect of the present disclosure, there is provided an electronic system comprising a main board, a semiconductor memory device on the main board, and a controller electrically connected to the semiconductor memory device, on the main board, wherein the semiconductor memory device includes a mold structure that includes a mold insulation film and a gate electrode alternately stacked on a first substrate, a channel structure that penetrates the mold structure and that intersects the gate electrode, a block separation region that extends in a first direction parallel to an upper surface of the first substrate and cuts the mold structure, a first dam region that forms a closed loop in a plane parallel to the upper surface of the first substrate and cuts the mold structure, a second dam region that is spaced apart from the first dam region in the first direction, that forms a closed loop in the plane parallel to the upper surface of the first substrate, and that cuts the mold structure, pad insulation films in the first dam region and the second dam region that are alternately stacked with the mold insulation films and that include a material different from the mold insulation films, a decoder circuit connected to the controller, and a through via in the first dam region that penetrates through the first substrate, the mold insulation films, and the pad insulation films to connect the gate electrode of the gate electrodes with the decoder circuit, in the first dam region.

According to some aspect of the present disclosure, there is provided a semiconductor memory device comprising: a first substrate; a mold structure that includes a plurality of alternately stacked mold insulation films and gate electrodes; a channel structure that penetrates the mold structure and that intersects the gate electrodes; first and second block separation regions that extend in a first direction parallel to an upper surface of the first substrate and that cut the mold structure; first and second dam regions between the first and second block separation regions and spaced apart from each other, the first and second dam regions each cutting the mold structure and each having a closed loop when viewed in a plan view; pad insulation films in the first dam region and the second dam region, the pad insulation films alternately stacked with the mold insulation films and including a material different from the mold insulation films; and a through via in the first dam region that penetrates through the first substrate, the mold insulation films, and the pad insulation films. The second dam region may have a smaller perimeter in the plan view than the first dam region.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Hereinafter, a semiconductor memory device according to exemplary embodiments will be explained referring toFIGS.1to12.

FIG.1is an exemplary block diagram for explaining a semiconductor memory device according to some embodiments.

Referring toFIG.1, a semiconductor memory device10according to some embodiments may include a memory cell array20and a peripheral circuit30.

The memory cell array20may include a plurality of memory cell blocks BLK1to BLKn. Each of the memory cell blocks BLK1to BLKn may include a plurality of memory cells. The memory cell blocks BLK1to BLKn may be connected to the peripheral circuit30through at least one bit line BL, at least one word line WL, at least one string selection line SSL, and at least one ground selection line GSL.

Specifically, the memory cell blocks BLK1to BLKn may be connected to a row decoder33through the at least one word line WL, at least one string selection line SSL, and at least one ground selection line GSL. Further, the memory cell blocks BLK1to BLKn may be connected to a page buffer35through the at least one bit line BL.

The peripheral circuit30may receive an address ADDR, a command CMD and a control signal CTRL from a source (not shown) external to the semiconductor memory device10, and may transmit and receive data DATA to and from a device outside the semiconductor memory device10. The peripheral circuit30may include a control logic37, a row decoder33, and a page buffer35.

Although not shown inFIG.1, the peripheral circuit30may further include various sub-circuits, such as an I/O circuit, a voltage generation circuit configured to generate various voltages used in the operation of the semiconductor memory device10, and an error correction circuit configured to correct an error of the data DATA that is read from the memory cell array20.

The control logic37may be connected to the row decoder33, the I/O circuit, and the voltage generation circuit. The control logic37may control the overall operation of the semiconductor memory device10. The control logic37may generate various internal control signals used inside the semiconductor memory device10in response to a control signal CTRL. For example, the control logic37may adjust the voltage levels provided to the word line WL and the bit line BL when performing memory operations such as a program operation or an erase operation.

The row decoder33may select at least one of a plurality of memory cell blocks BLK1to BLKn in response to the address ADDR, and may select at least one word line WL, at least one string selection line SSL, and at least one ground selection line GSL of the selected memory cell blocks BLK1to BLKn. The row decoder33may transfer a voltage for performing a memory operation to the word lines WL of the selected memory cell blocks BLK1to BLKn.

The page buffer35may be connected to the memory cell array20through the at least one bit line BL. The page buffer35may operate as a writer driver or a sense amplifier. Specifically, at the time of program operation, the page buffer35may operate as a write driver to apply to at least one bit line BL a voltage corresponding to the data DATA to be stored in the memory cell array20. At the time of the read operation, the page buffer35may operate as a sense amplifier to sense the data DATA stored in the memory cell array20.

FIG.2is an exemplary circuit diagram for explaining the semiconductor memory device according to some embodiments.

Referring toFIG.2, the memory cell array (e.g.,20ofFIG.1) of the non-volatile memory device according to some embodiments may include a common source line CSL, a plurality of bit lines BL, and a plurality of cell strings CSTR.

The common source line CSL may extend in a first direction Y. In some embodiments, a plurality of common source lines CSL may be arranged two-dimensionally. For example, the plurality of common source lines CSL may be spaced apart from each other and each extend in the first direction Y. Electrically equal voltages may be applied to the common source lines CSL, or different voltages are applied thereto, and/or the common source lines CSL may be controlled separately.

The plurality of bit lines BL may be arranged two-dimensionally. For example, the bit lines BL may be spaced apart from each other and each extend in a second direction X that intersects the first direction Y. One or more of the plurality of cell strings CSTR may be connected in parallel to each bit line BL. The cell strings CSTR may be connected in common to the common source line CSL. That is, the plurality of cell strings CSTR may be placed between the bit lines BL and the common source line CSL.

Each cell string CSTR may include a ground selection transistor GST connected to the common source line CSL, a string selection transistor SST connected to the bit line BL, and a plurality of memory cell transistors MCT placed between the ground selection transistor GST and the string selection transistor SST. Each memory cell transistor MCT may include a data storage element. The ground selection transistor GST, the string selection transistor SST, and the memory cell transistors MCT may be connected in series.

The common source line CSL may be commonly connected to the sources of the ground selection transistor GST. Also, a ground selection line GSL, a plurality of word lines WL11to WL1n, WL21to WL2n, and a string selection line SSL may be placed between the common source line CSL and the bit line BL. The ground selection line GSL may be used as a gate electrode of the ground selection transistor GST, the word lines WL11to WL1n, WL21to WL2nmay be used as the gate electrodes of the memory cell transistors MCT, and the string selection line SSL may be used as the gate electrode of the string selection transistor SST.

In some embodiments, and as seen inFIG.2, an erasure control transistor ECT may be placed between the common source line CSL and the ground selection transistor GST. The common source line CSL may be commonly connected to the sources of the erasure control transistor ECT. Further, an erasure control line ECL may be placed between the common source line CSL and the ground selection line GSL. The erasure control line ECL may be used as a gate electrode of the erasure control transistor ECT. The erasure control transistors ECT may generate a gate induced drain leakage (GIDL) to perform the erasure operation of the memory cell array.

FIG.3is a layout diagram for explaining a semiconductor memory device according to some embodiments.FIG.4is a cross-sectional view taken along A-A ofFIG.3.FIG.5is an extension view for explaining a region R ofFIG.4.

Referring toFIGS.1to5, the semiconductor memory device according to some embodiments includes a first substrate100, mold structures MS1and MS2, a channel structure CH, a bit line BL, a block separation region WLC, a cell gate cutting region CAC, an extension gate cutting region CNC, a first dam region RD, a second dam region DD, a first pad structure PS1, a second pad structure PS2, a second substrate200, a peripheral circuit element PT, and a first through via THV.

The first substrate100may include, as non-limiting examples, a semiconductor substrate, such as a silicon substrate, a germanium substrate, or a silicon-germanium substrate. Alternatively, the first substrate100may include a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, or the like. In some embodiments, the first substrate100may include impurities. For example, the first substrate100may include n-type impurities (e.g., phosphorus (P), arsenic (As), etc.).

The first substrate100may include a cell array region CELL and an extension region EXT. The cell array region CELL and the extension region EXT may be cut by a plurality of block separation regions WLC to form a plurality of memory cell blocks (for example, BLK1to BLKn ofFIG.1). For example, the block separation region WLC may extend in the first direction Y parallel to an upper surface of the first substrate100to cut the cell array region CELL and the extension region EXT.

A memory cell array (e.g.,20ofFIG.1) including a plurality of memory cells may be formed in the cell array region CELL. For example, a channel structure CH, a bit line BL, gate electrodes ECL, GSL, WL11to WL1n, WL21to WL2n, and SSL, and the like, may be placed in the cell array region CELL, as explained herein.

The extension region EXT may be placed around the cell array region CELL. The gate electrodes ECL, GSL, WL11to WL1n, WL21to WL2n, and SSL, as explained herein, may be stacked in the extension region EXT in a stepped manner. In some embodiments, the cell array region CELL and the extension region EXT may be arranged in a direction along which the block separation region WLC extends. For example, the cell array region CELL and the extension region EXT may be arranged along the first direction Y.

The mold structures MS1and MS2may be formed on the first substrate100. For example, a first interlayer insulation film140that covers the first substrate100may be formed on the first substrate100. The mold structures MS1and MS2may be stacked on an upper surface of the first interlayer insulation film140.

The mold structures MS1and MS2may include a plurality of gate electrodes ECL, GSL, WL11to WL1n, WL21to WL2n, and SSL and a plurality of mold insulation films110that are alternately stacked on the first substrate100. In some embodiments, the mold structures MS1and MS2may include a first mold structure MS1and a second mold structure MS2that are sequentially stacked on the first substrate100.

The first mold structure MS1may be formed on the first substrate100. The first mold structure MS1may include a plurality of first gate electrodes ECL, GSL, and WL11to WL1nand a plurality of mold insulation films110that are alternately stacked on the first substrate100. For example, the first gate electrodes ECL, GSL, and WL11to WL1nand the mold insulation films110may each have a layered structure that extends in parallel to the upper surface of the first substrate100. The first gate electrodes ECL, GSL, and WL11to WL1nand the mold insulation films110may be stacked alternately along a third direction Z that intersects (e.g., is perpendicular to) the upper surface of the first substrate100. Adjacent gate electrodes in the third direction Z may be separated by one of the plurality of mold insulation films110.

In some embodiments, the first gate electrodes ECL, GSL, and WL11to WL1nmay include an erasure control line ECL, a ground selection line GSL, and a plurality of first word lines WL11to WL1nthat are sequentially stacked on the first substrate100. In some embodiments, the erasure control line ECL may be omitted.

The second mold structure MS2may be formed on the first mold structure MS1. The second mold structure MS2may include a plurality of second gate electrodes WL21to WL2n, and SSL and a plurality of mold insulation films110that are alternately stacked on the first mold structure MS1. For example, the second gate electrodes WL21to WL2n, and SSL and the mold insulation films110may have a layered structure that extends in parallel to the upper surface of the first substrate100. The second gate electrodes WL21to WL2n, and SSL and the mold insulation films110may be alternately stacked along the third direction Z.

In some embodiments, the second gate electrodes WL21to WL2n, and SSL may include a plurality of second word lines WL21to WL2nand a string selection line SSL that are sequentially stacked on the first mold structure MS1.

The first gate electrodes ECL, GSL, and WL11to WL1n, as well as the second gate electrodes WL21to WL2nand SSL may include a conductive material. For example, the first gate electrodes ECL, GSL, and WL11to WL1nand the second gate electrodes WL21to WL2n, and SSL may each include, as non-limiting examples, a metal such as tungsten (W), cobalt (Co), and nickel (Ni), or a semiconductor material, such as silicon.

The mold insulation films110may include an insulating material. As one non-limiting example, the mold insulation films110may include a silicon oxide film.

In some embodiments, a second interlayer insulation film142may be formed on the first substrate100. The second interlayer insulation film142may cover the mold structures MS1and MS2. The second interlayer insulation film142may include, as non-limiting examples, at least one of silicon oxide, silicon oxynitride, and/or a low dielectric constant (low-k) material having a lower dielectric constant than silicon oxide.

The channel structure CH may penetrate the mold structures MS1and MS2. The channel structure CH may intersect a plurality of gate electrodes ECL, GSL, WL11to WL1n, WL21to WL2n, and SSL. For example, the channel structure CH may have a pillar shape (e.g., a columnar shape) that extends in the third direction Z.

Although the channel structure CH is only shown as being formed inside the mold structures MS1and MS2of the cell array region CELL, this is only for convenience of explanation. For example, as seen inFIG.4, in order to reduce a stress applied to the mold structures MS1and MS2, a dummy channel structure DCH having a shape similar to that of the channel structure CH may be formed inside the mold structures MS1and MS2of the extension region EXT. The dummy channel structure DCH may penetrate through the second interlayer insulation film142and the mold structures MS1and MS2. As seen inFIG.5, the channel structure CH and/or the dummy channel structure DCH may include a semiconductor pattern130and an information storage film132.

The semiconductor pattern130may extend in the third direction Z to penetrate through the mold structures MS1and MS2and the layers of the mold structures MS1and MS2. The semiconductor pattern130may have a cup shape where one end (e.g., the end more proximate to the substrate100) is closed. Although the semiconductor pattern130is shown as a cup shape, this is only an example. For example, the semiconductor pattern130may have various shapes such as a cylindrical shape, a rectangular barrel shape, and a solid pillar shape.

The information storage film132may be interposed between the semiconductor pattern130and the respective gate electrodes ECL, GSL, WL11to WL1n, WL21to WL2n, and SSL. For example, the information storage film132may extend along the side surfaces of the semiconductor pattern130.

The information storage film132may include, as non-limiting examples, at least one of silicon oxide, silicon nitride, silicon oxynitride, and/or a high dielectric constant material having a higher dielectric constant than that of silicon oxide. The high dielectric constant material may include, as non-limiting examples, at least one of aluminum oxide, hafnium oxide, lanthanum oxide, tantalum oxide, titanium oxide, lanthanum hafnium oxide, lanthanum aluminum oxide, dysprosium scandium oxide, or a combination of these materials.

In some embodiments, the information storage film132may be formed by multi-films or a plurality of films. For example, as shown inFIG.5, the information storage film132may include a tunnel insulation film132a, a charge storage film132b, and a blocking insulation film132c, which are sequentially stacked on the semiconductor pattern130.

The tunnel insulation film132amay include, as non-limiting examples, a silicon oxide or a high dielectric constant material (e.g., aluminum oxide (Al2O3), and hafnium oxide (HfO2)) having a higher dielectric constant than that of silicon oxide. The charge storage film132bmay include, for example, silicon nitride. The blocking insulation film132cmay include, for example, a silicon oxide or a high dielectric constant material having a higher dielectric constant than that of silicon oxide (e.g., aluminum oxide (Al2O3), and hafnium oxide (HfO2)).

In some embodiments, the channel structure CH may further include a filling pattern134. The filling pattern134may be formed to fill the inside of the semiconductor pattern130(e.g., the cup-shaped semiconductor pattern130). The filling pattern134may include, as a non-limiting example, an insulating material such as silicon oxide.

As seen inFIG.4some embodiments, the channel structure CH may further include a channel pad136. The channel pad136may be formed to be connected to the upper part of the semiconductor pattern130. The channel pad136may include, as one non-limiting example, impurity-doped polysilicon.

In some embodiments, a plurality of channel structures CH may be arranged in a zigzag form. For example, as shown inFIG.3, a plurality of channel structures CH may be arranged to be offset from each other in the second direction X and the first direction Y. The plurality of channel structures CH arranged in the zigzag form may further improve the degree of integration of the semiconductor memory device.

In some embodiments, a source structure105may be formed on the first substrate100. The source structure105may be interposed between the first substrate100and the mold structures MS1and MS2. The source structure105may include, for example, impurity-doped polysilicon or metal.

The source structure105may be formed to be connected to the semiconductor pattern130of the channel structure CH. For example, as seen inFIG.5, the source structure105may penetrate the information storage film132, and the source structure105may be in contact with the semiconductor pattern130. In some embodiments, the channel structure CH may penetrate the source structure105. For example, the lower part of the channel structure CH may penetrate the source structure105and may be buried inside the first substrate100.

In some embodiments, a base insulation film102may be formed on the first substrate100. The base insulation film102may be interposed between the first substrate100and the source structure105. The base insulation film102may include, as non-limiting examples, at least one of silicon oxide, silicon oxynitride and/or a low dielectric constant (low-k) material having a lower dielectric constant than that of silicon oxide.

The bit line BL may be formed on the mold structures MS1and MS2. For example, the bit line BL may be formed on the second to fourth interlayer insulation films142,144, and146, which are sequentially stacked on the mold structures MS1and MS2.

The bit line BL may extend in the second direction X parallel to the upper surface of the first substrate100and may be connected to a plurality of channel structures CH. For example, a bit line contact170that penetrates the third and fourth interlayer insulation films144and146and is connected to each channel structure CH may be formed. The bit line BL may be electrically connected to a plurality of channel structures CH through the bit line contact170.

The block separation region WLC is formed in the cell array region CELL and the extension region EXT and may cut the gate electrodes ECL, GSL, WL11to WL1n, WL21to WL2n, and SSL. Also, the block separation region WLC may intersect the bit line BL. For example, a plurality of block separation regions WLC may be arranged in the cell array region CELL and the extension region EXT along the second direction X. Each block separation region WLC may extend in the first direction Y to cut the mold structures MS1and MS2.

As explained above, the block separation region WLC may cut the cell array region CELL and the extension region EXT to form a plurality of memory cell blocks BLK1to BLKn. For example, each block separation region WLC may extend in length in the first direction Y and may completely cut the mold structures MS1and MS2. The mold structures MS1and MS2that are cut by two adjacent block separation regions WLC may define one of the block regions BLK1to BLKn.

The cell gate cutting region CAC may be formed in the cell array region CELL and may cut the gate electrodes ECL, GSL, WL11to WL1n, WL21to WL2n, and SSL, and the mold insulation films110. Also, the cell gate cutting region CAC may intersect the bit line BL. For example, the plurality of cell gate cutting regions CAC may be in the cell array region CELL and spaced apart from each other in the second direction X. Each cell gate cutting region CAC may extend in the first direction Y to cut the mold structures MS1and MS2inside the cell array region CELL.

The cell gate cutting region CAC may form a plurality of sections I, II, and III inside one of the block regions BLK1to BLKn of the cell array region CELL. For example, as shown inFIG.3, two cell gate cutting regions CAC may be formed between two adjacent block separation regions WLC. As a result, three sections (hereinafter, first to third sections I, II, and III) may be formed between the two adjacent block separation regions WLC. The cell gate cutting regions CAC allow the first section I and the second section II to be separated and controlled separately, and the second section II and the third section III to be separated and controlled separately.

The extension gate cutting region CNC may be formed in the extension region EXT to cut the gate electrodes ECL, GSL, WL11to WL1n, WL21to WL2n, and SSL. Also, the extension gate cutting region CNC may intersect the bit line BL. A plurality of extension gate cutting regions CNC may be in the extension region EXT and spaced apart from each other in the second direction X. Each extension gate cutting region CNC may extend in the first direction Y to cut the mold structures MS1and MS2in the extension region EXT.

In some embodiments, at least a part of the extension gate cutting region CNC may be arranged to overlap the cell gate cutting region CAC in the first direction Y. For example, as shown inFIG.3, five extension gate cutting regions CNC may be formed between two adjacent block separation regions WLC. As an example, two of the five extension gate cutting regions CNC may overlap the two cell gate cutting regions CAC in the first direction Y.

The block separation region WLC, the cell gate cutting region CAC, and the extension gate cutting region CNC may each include a first material pattern150. The first material pattern150may be formed to fill the block separation region WLC, the cell gate cutting region CAC, and the extension gate cutting region CNC. The first material pattern150may include, as non-limiting examples, at least one of polysilicon, silicon oxide, silicon nitride, silicon oxynitride and/or a low dielectric constant (low-k) material having a lower dielectric constant than that of silicon oxide.

In some embodiments, the block separation region WLC, the cell gate cutting region CAC, and the extension gate cutting region CNC may be formed at the same level. As used herein, the expression “formed at the same level” may mean that the regions are formed by the same fabricating process. In some embodiments, the insulating materials that form the block separation region WLC, the cell gate cutting region CAC and the extension gate cutting region CNC may be identical to each other.

In some embodiments, a string separation structure SC may be formed inside the mold structures MS1and MS2of the cell array region CELL. The string separation structure SC may be interposed between two adjacent block separation regions WLC to cut the string selection line SSL of the mold structures MS1and MS2. A plurality of string separation structures SC may be arranged in the cell array region CELL along the second direction X. Each string separation structure SC may extend in the first direction Y to cut the string selection line SSL.

In some embodiments, the string separation structure SC may be interposed between the block separation region WLC and the cell gate cutting region CAC. For example, the string separation structure SC may be placed in each of the first to third sections I, II, and III. Accordingly, the first to third sections I, II, and III may provide two string selection lines SSL that are each electrically separated and controlled separately. As an example, six string selection lines SSL may be formed between two adjacent block separation regions WLC.

In some embodiments, at least a part of the extension gate cutting region CNC may be arranged to overlap the string separation structure SC in the first direction Y. For example, as shown inFIG.3, five extension gate cutting regions CNC may be formed between two adjacent block separation regions WLC. As an example, three of the five extension gate cutting regions CNC may overlap the three string separation structures SC in the first direction Y.

A first dam region RD and a second dam region DD may be formed in the mold structures MS1and MS2. The first dam region RD and the second dam region DD may each form a closed loop in a plane parallel to the upper surface of the first substrate100(for example, a plane extending in the first direction Y and the second direction X). For example, as shown inFIG.3, the first dam region RD and the second dam region DD may each form a rectangular closed loop, when viewed in a plan view. The first dam region RD and the second dam region DD may cut the mold structures MS1and MS2. For example, as shown inFIG.4, the first dam region RD and the second dam region DD may each extend in the third direction Z and penetrate the mold structures MS1and MS2.

In some embodiments, the first dam region RD and the second dam region DD may be formed inside the mold structures MS1and MS2of the extension region EXT. For example, the mold structures MS1and MS2may include a first pad gate electrode WLm stacked in a stepped manner in the extension region EXT. In the extension region EXT, at least a part of the first pad gate electrode WLm may be exposed from the gate electrodes (e.g., WL2n, SSL) stacked on the top thereof. The first dam region RD and the second dam region DD may be formed in the exposed region of the first pad gate electrode WLm.

However, the technical idea of the present disclosure is not limited thereto, and the first dam region RD and/or the second dam region DD may, of course, be formed inside the mold structures MS1, MS2of the cell array region CELL.

Although the first pad gate electrode WLm is only shown as being included in the second mold structure MS2, this is only an example, and the first pad gate electrode WLm may be included in the mold structure MS1.

The second dam region DD may be separated from the first dam region RD. In some embodiments, the second dam region DD may be separated from the first dam region RD in the first direction Y. A spaced distance D1between the first dam region RD and the second dam region DD may be, for example, about 2 μm to about 5 μm. As an example, the spaced distance D1between the first dam region RD and the second dam region DD may be about 3 μm to about 4 μm.

In some embodiments, one or more extension gate cutting regions CNC may be interposed between the first dam region RD and the second dam region DD. The one or more extension gate cutting regions CNC may be arranged in one or more rows. AlthoughFIG.3shows that only one row of extension gate cutting regions CNC arranged along the second direction X are interposed between the first dam region RD and the second dam region DD, this is only an example. In some embodiments, no extension gate cutting regions CNC are interposed between the first dam region RD and the second dam region DD.

In some embodiments, a part of the first dam region RD and/or a part of the second dam region DD may be arranged to overlap at least a part of the extension gate cutting regions CNC in the first direction Y. For example, as shown inFIG.3, the first dam region RD and the second dam region DD forming a rectangular closed loop may include two sides each extending in the first direction Y. As an example, the two first sides may overlap the two extension gate cutting regions CNC in the first direction Y.

In some embodiments, the first dam region RD and the second dam region DD may each be formed to extend over a distance that a plurality of extension gate cutting regions CNC are spaced or arranged. For example, as shown inFIG.3, the first dam region RD and the second dam region DD forming the rectangular closed loop may include two second sides each extending in the second direction X. As an example, the two second sides may be formed to extend a distance that the four extension gate cutting regions CNC are arranged along the second direction X.

Although the length of the first dam region RD in the second direction X and the length of the second dam region DD in the second direction X are shown as being the same, this is only an example. For example, the length of the first dam region RD in the second direction X may, be greater or smaller than the length of the second dam region DD in the second direction X.

In some embodiments, a first length L1of the first dam region RD in the first direction Y may be greater than a second length L2of the second dam region DD in the first direction Y. For example, the second length L2may be about 0.1 to about 0.9 times the first length L1. As an example, the second length L2may be about 0.3 to about 0.7 times the first length L1. In some embodiments, the first length L1may be about 2 μm to about 5 μm. As an example, the first length L1may be about 3 μm to about 4 μm. Accordingly, a perimeter (when viewed in a plan view) of the second dam region DD may be smaller than the perimeter of the first dam region RD.

In some embodiments, a dummy channel structure DCH may be interposed between the first dam region RD and the second dam region DD. AlthoughFIG.4shows only one dummy channel structure DCH interposed between the first dam region RD and the second dam region DD, this is only an example. In some embodiments, no dummy channel structures DCH are interposed between the first dam region RD and the second dam region DD.

The first dam region RD and the second dam region DD may each include second material patterns152,154, and156. The second material patterns152,154, and156may fill the first dam region RD and the second dam region DD. The second material patterns152,154, and156may include, as non-limiting examples, at least one of polysilicon, silicon oxide, silicon nitride, silicon oxynitride, and/or a low dielectric constant (low-k) material having a lower dielectric constant than that of silicon oxide.

In some embodiments, the second material patterns152,154, and156may be formed by multi-films or a plurality of films. For example, the second material patterns152,154, and156may include a first material film152, a second material film154, and a third material film156that are stacked sequentially. As an example, the first material film152may include a silicon oxide film, the second material film154may include a silicon nitride film, and the third material film156may include a polysilicon film.

The first pad structure PS1may be formed in the first dam region RD. The first dam region RD may define the first pad structure PS1in the mold structures MS1and MS2. For example, the first dam region RD may surround the side surfaces of the first pad structure PS1.

The second pad structure PS2may be formed in the second dam region DD. The second dam region DD may define a second pad structure PS2in the mold structures MS1and MS2. For example, the second dam region DD may surround the side surfaces of the second pad structure PS2.

The first pad structure PS1and the second pad structure PS2may each include a plurality of pad insulation films115and a plurality of mold insulation films110that are alternately stacked on the first substrate100. For example, each pad insulation film115and each mold insulation film110may have a layered structure that extend in parallel to the upper surface of the first substrate100. The pad insulation films115and the mold insulation films110may be alternately stacked along the third direction Z.

The pad insulation films115may be stacked at the same level as at least some of the gate electrodes ECL, GSL, WL11to WL1n, WL21to WL2n, and SSL. As used herein, the expression “stacked at the same level” may mean that the pad insulation films115are stacked at substantially the same height on the basis of the upper surface of the first substrate100. For example, as shown inFIG.4, the pad insulation films115may be stacked at the same level as the gate electrodes (for example, ECL, GSL, WL11to WL1n, and WL21to WLm) below the first pad gate electrode WLm. A first pad insulation film115may be stacked at the same level as a first gate electrode (e.g., gate electrode ECL), a second pad insulation film115may be stacked at the same level as a second gate electrode (e.g., gate electrode GSL), and so on.

In some embodiments, the height of the first pad structure PS1may be the same as the height of the second pad structure PS2from the upper surface of the first substrate100. As used herein, the meaning of the term “same” indicates not only an exact equality, but also small or minute differences that may occur due to process margins and the like. The uppermost pad insulation film115of the first pad structure PS1and the uppermost pad insulation film115of the second pad structure PS2may be stacked at the same level as the first pad gate electrode WLm.

The pad insulation films115may include, as non-limiting examples, at least one of polysilicon, silicon oxide, silicon nitride, silicon oxynitride, and/or low dielectric constant (low-k) material having a lower dielectric constant than that of silicon oxide.

The pad insulation films115may include a material different from the mold insulation films110. As an example, the mold insulation films110may include a silicon oxide film, and the pad insulation films115may include a silicon nitride film. Thus, the mold insulation films110and the pad insulation films115may have different etch selectivity from each other.

The pad insulation films115may also include a material different from the second material patterns152,154, and156, or the films thereof. As an example, the first material film152may include a silicon oxide film, and the pad insulation films115may include a silicon nitride film. Thus, the first material film152and the pad insulation films115may have different etch selectivity from each other.

The second substrate200may be placed under the first substrate100. For example, the upper surface of the second substrate200may face the lower surface of the first substrate100. The first substrate100may be formed on the second substrate200. A fifth interlayer insulation film240that covers the second substrate200may be formed on the second substrate200. The first substrate100may be stacked on the upper surface of the fifth interlayer insulation film240.

The second substrate200may include, as non-limiting examples, a semiconductor substrate, such as a silicon substrate, a germanium substrate, or a silicon-germanium substrate. Alternatively, the second substrate200may include a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, and/or the like.

The peripheral circuit element PT may be formed on the upper surface of the second substrate200and may be covered by the fifth interlayer insulation film240. The peripheral circuit element PT may form a peripheral circuit (for example,30ofFIG.1) that controls the operation of the semiconductor memory device. For example, the peripheral circuit element PT may include control logic (e.g.,37ofFIG.1), a row decoder (e.g.,33ofFIG.1), a page buffer (e.g.,35ofFIG.1), and the like.

The peripheral circuit element PT may include, but is not limited to, for example, a transistor. For example, the peripheral circuit element PT may include active elements such as transistors, and/or passive elements such as capacitors, resistors, and inductors.

At least one first through via THV may be placed inside the first dam region RD. The first through via THV may extend in the third direction Z to penetrate through the first substrate100and the first pad structure PS1. The first through via THV may sequentially penetrate through the fourth interlayer insulation film146, the third interlayer insulation film144, the second interlayer insulation film142, the first pad structure PS1, and the first substrate100.

First through vias THV may not be placed inside the second dam region DD. The second pad structure PS2may be a dummy pad structure in which the first through via THV is not formed.

In some embodiments, the first through via THV may penetrate through the first substrate100and may be connected to the peripheral circuit element PT. For example, a wiring structure PW connected to the peripheral circuit element PT may be formed inside the fifth interlayer insulation film240. The first through via THV may be connected to the wiring structure PW. As a result, the wiring structure PW may electrically connect the first through via THV and the peripheral circuit element PT.

In some embodiments, the first substrate100may include a substrate hole100tthat exposes the fifth interlayer insulation film240. The first interlayer insulation film140may fill the substrate hole100t. The first through via THV may be placed inside the substrate hole100t. As a result, the first through via THV may penetrate the first interlayer insulation film140and may be connected to the wiring structure PW.

In some embodiments, the first through via THV may be connected to the respective gate electrodes ECL, GSL, WL11to WL1n, WL21to WL2n, and SSL. For example, a gate contact162that penetrates through the second to fourth interlayer insulation films142,144, and146and is connected to each of the gate electrodes ECL, GSL, WL11to WL1n, WL21to WL2n, and SSL may be formed. Further, a connection wiring CL that connects the gate contact162and the first through via THV may be formed on the fourth interlayer insulation film146. The first through via THV may be electrically connected to each of the gate electrodes ECL, GSL, WL11to WL1n, WL21to WL2n, and SSL through the connection wiring CL and the gate contact162. As a result, the first through via THV may electrically connect the respective gate electrodes ECL, GSL, WL11to WL1n, WL21to WL2n, and SSL and the peripheral circuit element PT.

In some embodiments, the peripheral circuit element PT connected to the first through via THV may include a row decoder (33ofFIG.1). That is, the first through via THV may electrically connect the respective gate electrodes ECL, GSL, WL11to WL1n, WL21to WL2n, and SSL and the row decoder (33ofFIG.1).

A dam region (e.g., RD) may be provided in the mold structure to form a through via (e.g., THV) that penetrates the mold structure (e.g., MS1, MS2). However, the dam region may buckle due to the stress applied to the mold structure, which may become a cause of decrease in product reliability. For example, the interlayer insulation film (e.g.,142) that covers the mold structure may apply stress to the mold structure along the first direction Y, resulting in buckling of the dam region.

However, the memory device according to some embodiments includes a second dam region DD in which the first through via THV is not placed, and thus it may be possible to reduce stress applied to the dam region RD in which the first through via THV is placed. Specifically, as explained above, the second dam region DD may be spaced apart from the first dam region RD in the first direction Y. As a result, the stress applied to the mold structures MS1and MS2along the first direction Y may be dispersed to the second dam region DD, and stress applied to the first dam region RD may be reduced, and as such it may be possible to provide a semiconductor memory device in which the product reliability is improved.

FIG.6is a cross-sectional view for explaining a semiconductor memory device according to some embodiments. For reference,FIG.6is another cross-sectional view taken along A-A ofFIG.3. For convenience of explanation, repeated parts of contents explained above usingFIGS.1to5will be briefly explained or omitted.

Referring toFIG.6, the semiconductor memory device according to some embodiments includes an impurity region107.

The impurity region107may be formed in the first substrate100. The impurity region107may extend in the first direction Y, and provided as a common source line (e.g., CSL ofFIG.2) of the semiconductor memory device.

In some embodiments, the block separation region WLC may include a conductive material. For example, the block separation region WLC may include a conductive pattern, and a spacer film that separates the mold structures MS1and MS2from the conductive pattern. The block separation region WLC may include the conductive pattern may be connected to the impurity region107, and may be provided as a common source line (e.g., CSL ofFIG.2) of the semiconductor memory device.

In some embodiments, the source structure105ofFIG.4may be omitted.

FIG.7is a layout diagram for explaining a semiconductor memory device according to some embodiments.FIG.8is a cross-sectional view taken along B-B ofFIG.7. For convenience of explanation, repeated parts of contents explained above usingFIGS.1to5will be briefly explained or omitted.

Referring toFIGS.7and8, a semiconductor memory device according to some embodiments includes a second through via DTHV.

The second through via DTHV may be placed in the second dam region DD. The second through via DTHV that extends in the third direction Z and that may penetrate through the second pad structure PS2. For example, the second through via DTHV may sequentially penetrate through the fourth interlayer insulation film146, the third interlayer insulation film144, the second interlayer insulation film142, and the second pad structure PS2.

In some embodiments, the second through via DTHV may not be connected to the peripheral circuit element PT. The second through via DTHV may extend into the first substrate100but may not penetrate through the first substrate100. That is, the second through via DTHV may be a dummy through via that is not electrically connected to the peripheral circuit element PT.

In some embodiments, the second through via DTHV may not be connected to the respective gate electrodes ECL, GSL, WL11to WL1n, WL21to WL2n, and SSL. For example, the second through via DTHV may not be connected to the connection wiring CL.

FIG.9is a layout diagram for explaining a semiconductor memory device according to some embodiments.FIG.10is a cross-sectional view taken along C-C ofFIG.9. For convenience of explanation, repeated parts of contents explained above usingFIGS.1to5will be briefly explained or omitted.

Referring toFIGS.9and10, the height of the first pad structure PS1may be different from the height of the second pad structure PS2from the upper surface of the first substrate100.

For example, the mold structures MS1and MS2may include a first pad gate electrode WLm and a second pad gate electrode WL1that are stacked in a stepped manner in the extension region EXT. The first pad gate electrode WLm may be stacked on the second pad gate electrode WL1. In the extension region EXT, the second pad gate electrode WL1may be exposed from the gate electrodes (e.g., WLm to WL2n, and SSL) stacked thereon. The first dam region RD may be formed in the exposed region of the first pad gate electrode WLm, and the second dam region DD may be formed in the exposed region of the second pad gate electrode WL1.

As a result, a height of the first pad structure PS1may be higher than a height of the second pad structure PS2from the upper surface of the first substrate100. The uppermost pad insulation film115of the first pad structure PS1may be stacked at the same level as the first pad gate electrode WLm, and the uppermost pad insulation film115of the second pad structure PS2may be stacked at the same level as the second pad gate electrode WL1.

Although the drawing shows that the height of the first pad structure PS1is higher than the height of the second pad structure PS2from the upper surface of the first substrate100, this is only an example. As another example, the first dam region RD may be formed inside the exposed region of the second pad gate electrode WL1, and the second dam region DD be formed in the exposed region of the first pad gate electrode WLm. As such, the height of the first pad structure PS1may be smaller than the height of the second pad structure PS2from the upper surface of the first substrate100.

Although both the first pad gate electrode WLm and the second pad gate electrode WL1are shown as being included in the second mold structure MS2, this is only an example, and the first pad gate electrode WLm and/or the second pad gate electrode WL1may be included in the first mold structure MS1.

FIG.11is a layout diagram for explaining the semiconductor memory device according to some embodiments.FIG.12is a cross-sectional view taken along D-D ofFIG.11. For convenience of explanation, repeated parts of contents explained above usingFIGS.1to5will be briefly explained or omitted.

Referring toFIGS.11and12, the semiconductor memory device according to some embodiments may include a cross gate cutting region XC.

The cross gate cutting region XC is formed in the extension region EXT and may cut a plurality of gate electrodes ECL, GSL, WL11to WL1n, WL21to WL2n, and SSL. Also, the cross gate cutting region XC may intersect the extension gate cutting region CNC. For example, the cross gate cutting region XC may extend in the second direction X to cut the mold structures MS1and MS2in the extension region EXT. In some embodiments, a plurality of cross gate cutting regions XC may be arranged in the extension region EXT along the second direction X.

The cross gate cutting region XC may be spaced apart from the first dam region RD. In some embodiments, the cross gate cutting region XC may be spaced apart from the first dam region RD in the first direction Y. A spaced distance between the first dam region RD and the cross gate cutting region XC may be, for example, about 2 μm to about 5 μm. As an example, a spaced distance D1between the first dam region RD and the cross gate cutting region XC may be about 3 μm to about 4 μm.

Although the cross gate cutting region XC is shown as being interposed between the first dam region RD and the second dam region DD, this is only an example. In some embodiments, the second dam region DD may be interposed between the first dam region RD and the cross gate cutting region XC. In some embodiments, the first dam region RD may be interposed between the cross gate cutting region XC and the second dam region DD.

In some embodiments, the cross gate cutting region XC may include a first material pattern150. The first material pattern150may fill the cross gate cutting region XC. In some embodiments, the first pattern material150that fills the cross gate cutting region XC may be the same material that fills the block separation region WLC.

In some embodiments, the block separation region WLC, the cell gate cutting region CAC, the extension gate cutting region CNC, and the cross gate cutting region XC may be formed at the same level.

Hereinafter, operations of methods for fabricating a semiconductor memory device according to exemplary embodiments will be explained referring toFIGS.1to22.

FIGS.13to22are intermediate stage diagrams for explaining the method for fabricating the semiconductor memory device according to some embodiments. For convenience of explanation, repeated parts of contents explained above usingFIGS.1to12will be briefly explained or omitted.

Referring toFIGS.13and14, a first substrate100and a preliminary mold structure pMS may be formed on a second substrate200. For reference,FIG.14is a cross-sectional view taken along A-A ofFIG.13.

The first substrate100may be formed on the second substrate200. For example, a fifth interlayer insulation film240that covers the second substrate200may be formed on the second substrate200. The first substrate100may be stacked on the upper surface of the fifth interlayer insulation film240.

The preliminary mold structure pMS may be formed on the first substrate100. For example, a first interlayer insulation film140that covers the first substrate100may be formed on the first substrate100. The preliminary mold structure pMS may be stacked on the upper surface of the first interlayer insulation film140. The preliminary mold structure pMS may include a plurality of sacrificial films115pand a plurality of mold insulation films110that are alternately stacked on the first substrate100.

The sacrificial films115pand the mold insulation films110may have different etch selectivity from each other. As an example, the sacrificial films115pmay include a silicon nitride film, and the mold insulation films110may include a silicon oxide film.

In some embodiments, a string separation structure SC may be formed in the preliminary mold structure pMS of the cell array region CELL. The string separation structure SC extends in the first direction Y and may cut the uppermost sacrificial film115p.

The sacrificial films115pmay be stacked in the extension region EXT in a stepped manner. For example, the preliminary mold structure pMS of the extension region EXT may be patterned in a stepped manner.

Referring toFIGS.15and16, a channel structure CH is formed in the preliminary mold structure pMS. For reference,FIG.16is a cross-sectional view taken along A-A ofFIG.15.

The channel structure CH may penetrate through the preliminary mold structure pMS. The channel structure CH may intersect a plurality of sacrificial films115p. For example, the channel structure CH may have a pillar shape (e.g., a columnar shape) extending in the third direction Z.

In some embodiments, a second interlayer insulation film142may be formed on the first substrate100. The second interlayer insulation film142may cover the preliminary mold structure pMS. The second interlayer insulation film142may include, as non-limiting examples, at least one of silicon oxide, silicon oxynitride, and/or a low dielectric constant (low-k) material having a lower dielectric constant than that of silicon oxide.

In some embodiments, a dummy channel structure DCH having a shape similar to that of the channel structure CH may be formed in the preliminary mold structure pMS of the extension region EXT. The dummy channel structure DCH may penetrate through the second interlayer insulation film142and the preliminary mold structure pMS.

Referring toFIGS.17and18, the block separation region WLC, the cell gate cutting region CAC, the extension gate cutting region CNC, the first dam region RD, and the second dam region DD are formed in the preliminary mold structure pMS. For reference,FIG.18is a cross-sectional view taken along A-A ofFIG.17.

The block separation region WLC may extend in the first direction Y to cut (e.g., completely cut) the preliminary mold structure pMS in the cell array region CELL and the extension region EXT.

The cell gate cutting region CAC may extend in the first direction Y to cut the preliminary mold structure pMS in the cell array region CELL.

The extension gate cutting region CNC may extend in the first direction Y to cut the preliminary mold structure pMS in the extension region EXT.

The first dam region RD and the second dam region DD may each cut the preliminary mold structure pMS. In some embodiments, the first dam region RD and the second dam region DD may be formed in the preliminary mold structure pMS of the extension region EXT. The second dam region DD may be spaced apart from the first dam region RD in the first direction Y.

The first dam region RD and the second dam region DD may each form a closed loop in a plane parallel to the upper surface of the first substrate100(for example, a plane extending in the first direction Y and the second direction X). As a result, a first pad structure PS1isolated by the first dam region RD may be formed, and a second pad structure PS2isolated by the second dam region DD may be formed. The first pad structure PS1and the second pad structure PS2may include a plurality of sacrificial films115pand a plurality of mold insulation films110that are alternately stacked on the first substrate100.

In some embodiments, the block separation region WLC, the cell gate cutting region CAC, the extension gate cutting region CNC, the first dam region RD and the second dam region DD may each include second material patterns152,154, and156. The second material patterns152,154, and156may be formed to fill the block separation region WLC, the cell gate cutting region CAC, the extension gate cutting region CNC, the first dam region RD, and the second dam region DD.

The sacrificial film115pand the second material patterns152,154, and156may have different etch selectivity from each other. As an example, the sacrificial film115pmay include a silicon nitride film, and the first material film152may include a silicon oxide film.

In some embodiments, the block separation region WLC, the cell gate cutting region CAC, the extension gate cutting region CNC, the first dam region RD, and the second dam region DD may be formed at the same level. For example, the block separation region WLC, the cell gate cutting region CAC, the extension gate cutting region CNC, the first dam region RD and the second dam region DD that cut the preliminary mold structure may be formed at the same time and/or via a single process or operation.

Referring toFIG.19, the second material patterns152,154, and156that fills the block separation region WLC, the cell gate cutting region CAC and the extension gate cutting region CNC may be removed.

The second material patterns152,154, and156that fill the first dam region RD and the second dam region DD may not be removed. For example, a mask pattern, which may expose the block separation region WLC, the cell gate cutting region CAC and the extension gate cutting region CNC and may cover the first dam region RD and the second dam region DD, may be formed on the preliminary mold structure pMS. The mask pattern may selectively remove the second material patterns152,154, and156that fill the block separation region WLC, the cell gate cutting region CAC, and the extension gate cutting region CNC.

Referring toFIG.20, the sacrificial films115pexposed by the block separation region WLC, the cell gate cutting region CAC, and the extension gate cutting region CNC may be removed.

As described above, since the sacrificial films115pand the mold insulation films110may have different etch selectivity from each other, the sacrificial films115pmay be selectively removed. Also, as mentioned above, since the sacrificial films115pand the second material patterns152,154, and156may have different etch selectivity from each other, the sacrificial films115pof the first pad structure PS1may be protected by the first dam region RD, and the sacrificial films115pof the second pad structure PS2may be protected by the second dam region DD. That is, the sacrificial films115poutside the first dam region RD and the second dam region DD may be selectively removed.

As a result, the first pad structure PS1and the second pad structure PS2including the pad insulation film115and the mold insulation film110which are alternately stacked may be formed.

For example, the gate electrodes ECL, GSL, WL11to WL1n, WL21to WL2n, and SSL may be formed in regions in which parts of the sacrificial films115pare removed. That is, parts of the removed sacrificial films115pmay be replaced with the gate electrodes ECL, GSL, WL11to WL1n, WL21to WL2n, and SSL. As a result, the mold structures MS1and MS2may be formed that include the gate electrodes ECL, GSL, WL11to WL1n, WL21to WL2n, and SSL alternately stacked with the mold insulation films110.

Subsequently, a first material pattern150that fills the block separation region WLC, the cell gate cutting region CAC, and the extension gate cutting region CNC may be formed.

Subsequently, referring toFIGS.3and4, the gate contact162, the bit line contact170, the first through via THV, the bit line BL, and the connection wirings CL may be formed. Accordingly, a method for fabricating a semiconductor memory device in which product reliability is improved.

Hereinafter, an electronic system including the semiconductor memory device according to the exemplary embodiments will be explained referring toFIGS.1to12and23to25.

FIG.23is a schematic block diagram for explaining an electronic system according to some embodiments.FIG.24is a schematic perspective view for explaining the electronic system according to some embodiments.FIG.25is a schematic cross-sectional view taken along I-I′ ofFIG.24.

Referring toFIG.23, an electronic system1000according to some embodiments may include a semiconductor memory device1100and a controller1200that is electrically connected to the semiconductor memory device1100. The electronic system1000may be a storage device that includes one or a plurality of semiconductor memory devices1100, or may be an electronic device that includes the storage device. For example, the electronic system1000may be an SSD device (solid state drive device) including one or a plurality of semiconductor memory devices1100, a USB (Universal Serial Bus) device, a computing system, a medical device, and/or a communication device.

The semiconductor memory device1100may be a non-volatile memory device (for example, a NAND flash memory device), and may be, for example, the semiconductor memory device described above with respect toFIGS.1to12. The semiconductor memory device1100may include a first structure1100F, and a second structure1100S on the first structure1100F.

The first structure1100F may be a peripheral circuit structure that includes a decoder circuit1110(e.g., the row decoder33ofFIG.1), a page buffer1120(e.g., the page buffer35ofFIG.1), and a logic circuit1130(e.g., the control logic37ofFIG.1).

The second structure1100S may include the common source line CSL, the plurality of bit lines BL, and the plurality of cell strings CSTR explained above usingFIG.2. The cell strings CSTR may be connected to the decoder circuit1110through at least one word line WL, at least one string selection line SSL, and at least one ground selection line GSL. Further, the cell strings CSTR may be connected to the page buffer1120through the bit lines BL.

The common source line CSL and the cell strings CSTR may be electrically connected to the decoder circuit1110through first connection wirings1115that extend from the first structure1100F to the second structure1100S. In some embodiments, the first connection wiring1115may correspond to the first through via THV explained above referring toFIGS.1to12. That is, the first through via THV may electrically connect the respective gate electrodes ECL, GSL, WL, and SSL and the decoder circuit1110(for example, the row decoder33ofFIG.1).

In some embodiments, the bit lines BL may be electrically connected to the page buffer1120through second connection wirings1125that extend from the first structure1100F to the second structure1100S.

The semiconductor memory device1100may communicate with the controller1200through at least one I/O pad1101that is electrically connected to a logic circuit1130(for example, the control logic37ofFIG.1). The I/O pad1101may be electrically connected to the logic circuit1130through an I/O connection wiring1135that extends from the first structure1100F to the second structure1100S.

The controller1200may include a processor1210, a NAND controller1220, and a host interface1230. In some embodiments, the electronic system1000may include a plurality of semiconductor memory devices1100, and in this case, the controller1200may control the plurality of semiconductor memory devices1100.

The processor1210may control the overall operation of the electronic system1000including the controller1200. The processor1210may operate according to a predetermined firmware, and may control the NAND controller1220to access the semiconductor memory device1100. The NAND controller1220may include a NAND interface1221that processes communication with the semiconductor memory device1100. Control command for controlling the semiconductor memory device1100, data to be recorded in the memory cell transistors MCT of the semiconductor memory device1100, data to be read from the memory cell transistors MCT of the semiconductor memory device1100, and the like may be transmitted through the NAND interface1221. The host interface1230may provide a communication function between the electronic system1000and an external host. When receiving the control command from an external host through the host interface1230, the processor1210may control the semiconductor memory device1100in response to the control command.

Referring toFIGS.24and25, the electronic system according to some embodiments may include a main board2001, a main controller2002mounted on the main board2001, one or more semiconductor packages2003, and a DRAM (dynamic random-access memory)2004. The semiconductor package2003and the DRAM2004may be connected to the main controller2002by wiring patterns2005formed on the main board2001.

The main board2001may include a connector2006including a plurality of pins coupled to an external host. In the connector2006, the number and arrangement of the plurality of pins may vary depending on the communication interface between the electronic system2000and the external host. In some embodiments, the electronic system2000may communicate with an external host according to any one of interfaces such as M-Phy for USB, PCI-Express (Peripheral Component Interconnect Express), SATA (Serial Advanced Technology Attachment), and UFS (Universal Flash Storage). In some embodiments, the electronic system2000may be operated by power supplied from an external host through the connector2006. The electronic system2000may further include a PMIC (Power Management Integrated Circuit) that distributes the power supplied from the external host to the main controller2002and the semiconductor package2003.

The main controller2002may record data in the semiconductor package2003and/or read data from the semiconductor package2003, and may improve the operating speed of the electronic system2000.

The DRAM2004may be a buffer memory configured to alleviate a speed difference between the semiconductor package2003, which is a data storage area, and an external host. The DRAM2004included in the electronic system2000may also operate as a kind of cache memory, and may also provide a space for temporarily storing data in the control operation of the semiconductor package2003. When the DRAM2004is included in the electronic system2000, the main controller2002may further include a DRAM controller for controlling the DRAM2004, in addition to the NAND controller for controlling the semiconductor package2003.

The semiconductor package2003may include a first semiconductor package2003aand a second semiconductor package2003bthat are spaced apart from each other. The first semiconductor package2003aand the second semiconductor package2003bmay each be a semiconductor package that includes a plurality of semiconductor chips2200. The first semiconductor package2003aand the second semiconductor package2003bmay each include a package substrate2100, semiconductor chips2200on the package substrate2100, adhesive layers2300placed on the lower surfaces of each of the semiconductor chips2200, a connection structure2400that is configured to electrically connect the semiconductor chips2200and the package substrate2100, and a molding layer2500that covers the semiconductor chips2200and the connection structure2400on the package substrate2100.

The package substrate2100may be a printed circuit board that includes upper pads2130. Each semiconductor chip2200may include an I/O pad2210. The I/O pad2210may correspond to the I/O pad1101ofFIG.23.

Each of the semiconductor chips2200may include a first structure3100, and a second structure3200stacked on the first structure3100. Each of the semiconductor chips2200may include the semiconductor memory device explained above usingFIGS.1to12. As an example, the first structure3100may include the second substrate200and the fifth interlayer insulation film240explained above usingFIGS.3and4. In addition, and as an example, the second structure3200may include the first substrate100, the mold structures MS1and MS2, the channel structure CH, the bit line BL, the block separation region WLC, the cell gate cutting region CAC, the extension gate cutting region CNC, the first dam region RD, the second dam region DD, the first pad structure PS1, and the second pad structure PS2explained above usingFIGS.3and4.

In some embodiments, the connection structure2400may be a bonding wire that electrically connects the I/O pad2210and the upper pads2130. Therefore, in each of the first semiconductor package2003aand the second semiconductor package2003b, the semiconductor chips2200may be electrically connected to each other in a bonding wire manner, and may be electrically connected to the upper pads2130of the package substrate2100. In some embodiments, in each of the first semiconductor package2003aand the second semiconductor package2003b, the semiconductor chips2200may also be electrically connected to each other by a connection structure including a through silicon via (TSV) or other connection structure instead of the bonding wire type connection structure2400.

In some embodiments, the main controller2002and the semiconductor chips2200may also be included in a single package. In some embodiments, the main controller2002and the semiconductor chips2200may be mounted on a separate interposer board different from the main board2001, and the main controller2002and the semiconductor chips2200may also be connected to each other by the wiring formed on the interposer board.

In some embodiments, the package substrate2100may be a printed circuit board. The package substrate2100may include a package substrate body portion2120, upper pads2130placed on an upper surface of the package substrate body portion2120, lower pads2125placed on a lower surface of the package substrate body portion2120or exposed through the lower surface, and inner wirings2135that electrically connect the upper pads2130and the lower pads2125inside the package substrate body portion2120. The upper pads2130may be electrically connected to the connection structures2400. The lower pads2125may be connected to the wiring patterns2005of the main board2010of the electronic system2000through the conductive connections2800, as seen inFIG.24.

In concluding the detailed description, those skilled in the art will appreciate that many variations and modifications may be made to the preferred embodiments without substantially departing from the principles of the present inventive concept. Therefore, the disclosed exemplary embodiments of the disclosure are used in a generic and descriptive sense only and not for purposes of limitation.