Method of forming vertical field effect transistors with different threshold voltages and the resulting integrated circuit structure

An integrated circuit and method are disclosed. In the method, a stack of sacrificial layers is formed on a semiconductor layer such that a first portion of the stack has an extra sacrificial layer as compared to a second portion. First and second multi-layer fins are etched through the first and second portions and into the semiconductor layer. First and second vertical field effect transistors (VFETs) are formed using the fins. During VFET formation, multiple etch processes are performed to remove the sacrificial layers. The last of these etch processes is a selective isotropic etch process that removes the extra sacrificial layer and etches back first and second upper dielectric spacers on the first and second multi-layer fins. Due to the extra sacrificial layer, the first upper dielectric spacer will be taller than the second and the first VFET will have a higher threshold voltage than the second.

BACKGROUND

Field of the Invention

The present invention relates to integrated circuit (IC) structures with vertical field effect transistors (VFETs) having different threshold voltages (Vts) and, thereby different switching speeds. More particularly, the present invention relates to a method of forming multiple VFETs with different Vts on the same substrate and to the resulting IC structures.

Description of the Related Art

Integrated circuit (IC) design decisions are often driven by device scalability, device density, manufacturing efficiency and costs. For example, size scaling of planar field effect transistors (FETs) resulted in the development of planar FETs with relatively short channel lengths and, unfortunately, the smaller channel lengths resulted in a corresponding increase in short channel effects. In response, non-planar FET technologies (e.g., fin-type FET (FINFET) technologies) were developed. A FINFET is a non-planar FET that incorporates a semiconductor fin (i.e., a relatively tall and thin, elongated, rectangular-shaped, semiconductor body) and, within the semiconductor fin, a channel region positioned laterally between source/drain regions. A gate is positioned adjacent to the top surface and opposing sidewalls of the semiconductor fin at the channel region. Such a FINFET exhibits two-dimensional field effects as compared to the single-dimensional field effects exhibited by a planar FET and, thus, exhibits improved gate control over the channel. It should be noted that, because the semiconductor fin is so thin, any field effects exhibited at the top surface are insignificant (i.e., negligible). Recently, vertical devices and, particularly, vertical field effect transistors (VFETs) have been developed that allow for increased device density (i.e., a greater number of devices within a given area). While multiple essentially identical VFETs can produced on a substrate with minimal impact on manufacturing efficiency and costs, oftentimes IC designs require devices with different switching speeds (e.g., due to different threshold voltages (Vts)) and forming vertical VFETs with different switching speeds on the same substrate can be challenging.

SUMMARY

Disclosed herein is a method of forming an integrated circuit (IC) structure with multiple vertical field effect transistors (VFETs) having different threshold voltages (Vts) and, thereby different switching speeds.

Generally, the method includes forming a stack of sacrificial layers on a semiconductor layer. The stack can be formed such that a first portion of the stack on a first device region has an extra sacrificial layer as compared to a second portion of the stack on a second device region. First and second multi-layer fins can be etched in the first and second portions of the stack, respectively, and into the semiconductor layer. First and second vertical field effect transistors (VFETs) can be concurrently formed using the first and second multi-layer fins, respectively. During formation of the first and second VFETs, first and second upper dielectric spacers can be formed on the first and second multi-layer fins, respectively. Additionally, multiple etch processes can be performed to remove the sacrificial layers from the first and second multi-layer fins. These etch processes can include initial etch processes, which remove all of the sacrificial layers except for the extra sacrificial layer on the first multi-layer fin, and an isotropic etch process, which removes the extra sacrificial layer from the first multi-layer fin and also etches back the first upper dielectric spacer and the second upper dielectric spacer. However, due to the presence of the extra sacrificial layer in the first multi-layer fin, the second upper dielectric spacer is etched back to a greater degree than the first upper dielectric spacer. Specifically, wherein, during the isotropic etch process, the first upper dielectric spacer is partially protected by the extra sacrificial layer until the extra sacrificial layer is removed and, thus, the second upper dielectric spacer is etched back faster than the first upper dielectric spacer. As a result, the first upper dielectric spacer in the first VFET will be taller than the second upper dielectric spacer in the second VFET.

In one particular embodiment of the method, a semiconductor layer can be provided and a stack of sacrificial layers can be formed on the semiconductor layer. To form the stack of sacrificial layers, a first sacrificial layer can be formed on a first device region of the semiconductor layer. Then, a second sacrificial layer can be formed on a second device region of the semiconductor layer and further on the first sacrificial layer. Next, a third sacrificial layer over the second sacrificial layer and a fourth sacrificial layer can be formed over the third sacrificial layer. Thus, the stack of sacrificial layers will have a first portion on the first device region and a second portion, which is different from the first portion, on the second device region. Specifically, the first portion will have the first sacrificial layer (i.e., the extra sacrificial layer) and the second portion will be devoid of this layer. After the stack of sacrificial layers is formed, multi-layer fins can be etched into the different portions of the stack and the semiconductor layer. Specifically, a first multi-layer fin can be etched in the first portion of the stack of sacrificial layers and the semiconductor layer and a second multi-layer fin can be etched in the second portion of the stack of sacrificial layers and the semiconductor layer. Vertical field effect transistors (VFETs) can then be concurrently formed using the multi-layer fins. Specifically, a first VFET can be formed using the first multi-layer fin and a second VFET can be concurrently formed using the second multi-layer fin.

During formation of the first VFET and the second VFET, a first upper dielectric spacer can be formed above a first gate and positioned laterally adjacent to first sidewalls of the first multi-layer fin and a second upper dielectric spacer can be formed above a second gate and positioned laterally adjacent to second sidewalls of the second multi-layer fin. Then, multiple etch processes can be performed to remove the sacrificial layers from the first multi-layer fin and the second multi-layer fin, thereby creating a first semiconductor fin and a second semiconductor fin, respectively. Specifically, following removal of the sacrificial layers, only the portions of the first and second multi-layer fins that were etched into the semiconductor layer will remain such that the remaining portions can be simply described as first and second semiconductor fins, respectively. The multiple etch processes include initial etch processes, which remove all of the sacrificial layers except for the first sacrificial layer (i.e., the extra sacrificial layer) on the first multi-layer fin, and an isotropic etch process, which removes the first sacrificial layer (i.e., the extra sacrificial layer) from the first multi-layer fin and also etches back the first upper dielectric spacer and the second upper dielectric spacer. It should be noted that, due to the presence of the first sacrificial layer on the first multi-layer fin, the second upper dielectric spacer is etched back to a greater degree than the first upper dielectric spacer. Specifically, during the isotropic etch process, the first upper dielectric spacer is partially protected by the first sacrificial layer (i.e., extra sacrificial layer) until that first sacrificial layer is removed and, thus, the second upper dielectric spacer is etched back faster than the first upper dielectric spacer. As a result, in the IC structure, the first upper dielectric spacer will be above the first gate and positioned laterally adjacent to the first semiconductor fin and the second upper dielectric spacer will similarly be above the second gate and positioned laterally adjacent to the second semiconductor fin, but the first upper dielectric spacer will be taller than the second upper dielectric spacer.

In the method described above, as result of the first upper dielectric spacer in the first VFET being taller than the second upper dielectric spacer in the second VFET, spacing between a subsequently formed first upper source/drain region and a first channel region in the first semiconductor fin of the first VFET will be greater than spacing between a subsequently formed second upper source/drain region and a second channel region in the second semiconductor fin of the second VFET. This difference in spacing between the upper source/drain regions and the channel regions of the two VFETs causes the first Vt of the first VFET to be greater than the second Vt of the second VFET and, thereby causes the first switching speed of the first VFET to be slower than the second switching speed of the second VFET.

Also disclosed herein is an integrated circuit (IC) structure formed according to the disclosed method so as to have multiple vertical field effect transistors (VFETs) with different threshold voltages (Vts) and, thereby different switching speeds. Specifically, the IC structure can include a first VFET and a second VFET on a semiconductor substrate.

The first VFET can have a first lower source/drain region and a first upper source/drain region. A first semiconductor fin can extend essentially vertically from the first lower source/drain region to the first upper source/drain region. A first gate can laterally surround the first semiconductor fin at a first channel region and dielectric spacers can physically separate the the first gate from the first lower source/drain region and the first upper source/drain region. That is, a first lower dielectric spacer can be positioned laterally adjacent to the first semiconductor fin and stacked between the first lower source/drain region and the first gate. Additionally, a first upper dielectric spacer can be positioned laterally adjacent to the first semiconductor fin and can be stacked between the first gate and the first upper source/drain region.

Similarly, the second VFET can have a second lower source/drain region and a second upper source/drain region. A second semiconductor fin can extend essentially vertically from the second lower source/drain region to the second upper source/drain region. A second gate can laterally surround the second semiconductor fin at a second channel region and dielectric spacers can physically separate the the second gate from the second lower source/drain region and the second upper source/drain region. That is, a second lower dielectric spacer can be positioned laterally adjacent to the second semiconductor fin and stacked between the second lower source/drain region and the second gate. Additionally, a second upper dielectric spacer can be positioned laterally adjacent to the second semiconductor fin and can be stacked between the second gate and the second upper source/drain region.

Thus, the first VFET and the second VFET are almost identical in structure except that, due to the method used to form these VFETs, the first upper dielectric spacer of the first VFET is taller than the second upper dielectric spacer of the second VFET. As a result, spacing between the first upper source/drain region and the first channel region in the first semiconductor fin of the first VFET is greater than spacing between the second upper source/drain region and the second channel region in the second semiconductor fin of the second VFET. This difference in spacing between the channel regions and the upper source/drain regions of the two VFETs causes the first Vt of the first VFET to be greater than the second Vt of the second VFET and, thereby causes the first switching speed of the first VFET to be slower than the second switching speed of the second VFET.

DETAILED DESCRIPTION

As mentioned above, integrated circuit (IC) design decisions are often driven by device scalability, device density, manufacturing efficiency and costs. For example, size scaling of planar field effect transistors (FETs) resulted in the development of planar FETs with relatively short channel lengths and, unfortunately, the smaller channel lengths resulted in a corresponding increase in short channel effects. In response, non-planar FET technologies (e.g., fin-type FET (FINFET) technologies) were developed. A FINFET is a non-planar FET that incorporates a semiconductor fin (i.e., a relatively tall and thin, elongated, rectangular-shaped, semiconductor body) and, within the semiconductor fin, a channel region positioned laterally between source/drain regions. A gate is positioned adjacent to the top surface and opposing sidewalls of the semiconductor fin at the channel region. Such a FINFET exhibits two-dimensional field effects as compared to the single-dimensional field effects exhibited by a planar FET and, thus, exhibits improved gate control over the channel. It should be noted that, because the semiconductor fin is so thin, any field effects exhibited at the top surface are insignificant (i.e., negligible). Recently, vertical devices and, particularly, vertical field effect transistors (VFETs) have been developed that allow for increased device density (i.e., a greater number of devices within a given area). While multiple essentially identical VFETs can produced on a substrate with minimal impact on manufacturing efficiency and costs, oftentimes IC designs require devices with different switching speeds (e.g., due to different threshold voltages (Vts)) and forming vertical VFETs with different switching speeds on the same substrate can be challenging.

In view of the foregoing, disclosed herein is a method of forming an integrated circuit (IC) structure with multiple vertical field effect transistors (VFETs), including a first VFET and a second VFET, having the same type conductivity (e.g., both P-type VFETs or both N-type VFETs) but different threshold voltages (Vts) and, thereby different switching speeds. In the method, a stack of sacrificial layers can be formed on a semiconductor substrate such that a first portion of the stack has an extra sacrificial layer as compared to a second portion of the stack. First and second multi-layer fins can be etched through the first and second portions of the stack, respectively, and into the semiconductor substrate. First and second vertical field effect transistors (VFETs) can be concurrently formed using the first and second multi-layer fins, respectively. During formation of the first and second VFETs, first and second upper dielectric spacers can be formed on the first and second multi-layer fins, respectively. Additionally, multiple etch processes can be performed to remove the sacrificial layers from the first and second multi-layer fins. The last of these etch processes can be an isotropic etch process, which, not only removes the extra sacrificial layer from the first multi-layer fin, but also etches back the first upper dielectric spacer and the second upper dielectric spacer. However, due to the presence of the extra sacrificial layer in the first multi-layer fin, the second upper dielectric spacer is etched back to a greater degree than the first upper dielectric spacer. As a result, the first upper dielectric spacer in the first VFET will be taller than the second upper dielectric spacer in the second VFET such that spacing between a subsequently formed first upper source/drain region and a first channel region of the first VFET will be greater than spacing between a subsequently formed second upper source/drain region and a second channel region for the second VFET. This difference in spacing causes the first Vt of the first VFET to be greater than the second Vt of the second VFET and, thereby causes the first switching speed of the first VFET to be slower than the second switching speed of the second VFET.

More particularly, referring to the flow diagram ofFIG. 1, disclosed herein is a method of forming an integrated circuit (IC) structure.

The method includes providing a semiconductor layer101(2). For example, the semiconductor layer101can be a bulk semiconductor wafer, such as a bulk silicon wafer (seeFIG. 2). Alternatively, the semiconductor layer101can be a semiconductor layer of a semiconductor-on-insulator wafer (e.g., a silicon-on-insulator (SOI) or any other suitable semiconductor-on-insulator wafer). In this case, the semiconductor layer (e.g., the silicon layer) of the semiconductor-on-insulator wafer will be considered the semiconductor substrate upon which processing is performed, as discussed below. In any case, the semiconductor substrate can have areas designated for formation of a first device region160and a second device region140.

The semiconductor layer101can be undoped so that channel regions of the VFETs in the resulting structure are undoped, enabling higher mobility. However, optionally, the semiconductor layer101can be doped so as to have a first type conductivity at a relatively low conductivity level (e.g., P− conductivity in the case of N-type VFETs or N− conductivity in the case of P-type VFETs) and, thus, so that the first channel region of the first VFET and the second channel region of the second VFET in the resulting structure will also have the first type conductivity at the relatively low conductivity level.

Optionally, the method can include forming, at some predetermined depth below the top surface of the semiconductor substrate, a first lower source/drain region162for the first VFET in the first device region160and a second lower source/drain region142for the second VFET in the second device region140(4). Such lower source/drain regions can be formed, for example, by performing one or more masked dopant implantation process to form deep well regions within the different device regions below the top surface of the semiconductor layer. Alternatively, any other suitable technique could be performed to form such lower source/drain regions. For example, trenches can be formed within a semiconductor substrate in different device regions. The trenches could be filled with an in-situ doped semiconductor material to form the lower source/drain regions and the semiconductor layer101could subsequently be formed on the top surface of the semiconductor substrate over the lower source/drain region regions (not shown). In any case, the lower source/drain regions can be doped so as to have a second type conductivity at a relatively high conductivity level (e.g., N+ conductivity in the case of N-type VFETs or P+ conductivity in the case of P-type VFETs).

A stack190of sacrificial layers can be formed on the semiconductor layer101such that a first portion191of the stack190on the first device region160has an extra sacrificial layer as compared to a second portion192of the stack190on the second device region140and, thus, is taller than the second portion192(6, seeFIG. 3). That is, the height of the first portion191, as measured from the top surface of the semiconductor layer101will be greater than the height of the second portion192, as measured from the top surface of the semiconductor layer101.

For example, to form the stack190at process6, a first sacrificial layer102can be formed (e.g., deposited) so as to be immediately adjacent to and cover the top surface of the semiconductor layer101. The first sacrificial layer102can subsequently be lithographically patterned and etched so that it is removed from the top surface of the semiconductor layer101in the second device region140, but remains on the top surface of the semiconductor layer101in the first device region160. The first sacrificial layer102can be deposited so that it has a predetermined thickness of 2-10 nm (e.g., approximately 2 nm, approximately 3 nm, etc.). As discussed in greater detail below, this predetermined thickness will be approximately equal to the desired difference in spacing between the first channel region and the first upper source/drain region in the first VFET being formed. Next, a second sacrificial layer103can be formed (e.g., conformally deposited) so that it is immediately adjacent to and covers the semiconductor layer101in the second device region140and further so that it extends laterally onto and covers the first sacrificial layer102. Subsequently, a third sacrificial layer104can be formed (e.g., conformally deposited) over the second sacrificial layer103and a fourth sacrificial layer105can be formed (e.g., conformally deposited) over the third sacrificial layer104.

It should be noted that in the above described stack190, the first sacrificial layer102, the second sacrificial layer103and the third sacrificial layer104can all be made of different sacrificial materials so that these layers can be selectively etched away during subsequent processing. The fourth sacrificial layer105can further be made of a different sacrificial material than the sacrificial materials of the second sacrificial layer103and the third sacrificial layer104and, optionally, can be made of the same sacrificial material as the first sacrificial layer102.

For example, in one embodiment, the first sacrificial layer102can be a sacrificial silicon nitride layer; the second sacrificial layer103can be a sacrificial silicon dioxide layer; the third sacrificial layer104can be a sacrificial amorphous silicon layer; and the fourth sacrificial layer105can be an additional sacrificial silicon nitride layer. In any case, the first sacrificial layer102and the second sacrificial layer103can each be relatively thin as compared to the third sacrificial layer104and the fourth sacrificial layer105. Such a stack190of sacrificial layers will have a first portion191on the first device region160and a second portion192, which is different from the first portion191, on the second device region140. The first portion191will have one extra sacrificial layer (namely, the first sacrificial layer102) and the second portion192will be devoid of this layer. Thus, the first portion191of the stack190will be taller than the second portion192by an amount equal to the thickness of the first sacrificial layer102(e.g., by 2-10 nm).

After the stack190of sacrificial layers is formed at process6, multi-layer fins can be formed (e.g., lithographically patterned and etched) into the different portions191-192of the stack190and into the semiconductor layer101below (8). That is, the same lithographic patterning and etch processes can be used to essentially simultaneously form a first multi-layer fin161in the first device region160and a second multi-layer fin141in the second device region140. Specifically, the first multi-layer fin161can be etched into the first portion191of the stack190of sacrificial layers and further into at least the upper portion101′ of the semiconductor layer101in the first device region160and the second multi-layer fin141can be etched into the second portion192of the stack190of sacrificial layers and further into the upper portion101′ of the semiconductor layer101in the second device region140. In the case where the first lower source/drain region162and the second lower source/drain region142are already formed this etch process can be performed so as to expose the lower source/drain regions and, thereby such that the bottom of the first multi-layer fin161is immediately adjacent to the first lower source/drain region162and such that the bottom of the second multi-layer fin141is immediately adjacent to the second lower source/drain region142(as illustrated).

In any case, the layers of the first multi-layer fin161will include the upper portion101′ of the semiconductor layer, the first sacrificial layer102(i.e., the extra sacrificial layer), the second sacrificial layer103, the third sacrificial layer104and the fourth sacrificial layer105; whereas, the layers of the second multi-layer fin141will only include the upper portion101′ of the semiconductor layer, the second sacrificial layer103, the third sacrificial layer104and the fourth sacrificial layer105. Thus, due to the presence of the first sacrificial layer102in the first multi-layer fin161, the first multi-layer fin161will be taller than the second multi-layer fin141by an amount equal to the thickness of the first sacrificial layer102(e.g., by 2-10 nm).

Vertical field effect transistors (VFETs) can then be concurrently formed using these multi-layer fins (10)-(28).

Specifically, if lower source/drain regions for the VFETs were not previously formed at process4, a first lower source/drain region162can now be formed in the semiconductor layer101adjacent to the bottom of the first multi-layer fin161and a second lower source/drain region142can now be formed in the semiconductor layer101adjacent to the bottom of the second multi-layer fin141(10, seeFIG. 5). The lower source/drain regions162,142can be formed, for example, as dopant implant regions, doped epitaxial semiconductor regions, etc. Various different techniques for forming lower source/drain regions for VFETs are well known in the art and, thus, the details of these techniques have been omitted from this specification in order to allow the reader to focus on the salient aspects of the disclosed methods. In any case, the lower source/drain regions can be doped so as to have a second type conductivity at a relatively high conductivity level (e.g., N+ conductivity in the case of N-type VFETs or P+ conductivity in the case of P-type VFETs).

Next, a lower dielectric spacer layer107can be deposited over the partially completed structure and then recessed (12, seeFIG. 6). As a result, the lower dielectric spacer layer107will be positioned above and immediately adjacent to both the first lower source/drain region162and the second lower source/drain region142and will further be positioned laterally around and immediately adjacent to the first sidewalls of the first multi-layer fin161and the second sidewalls of the second multi-layer fin141. The lower dielectric spacer layer107can be made, for example, of silicon nitride.

A gate dielectric layer108can then be conformally deposited over the partially completed structure (i.e., onto the lower dielectric spacer layer107and over the first multi-layer fin161and the second multi-layer fin141) (14, seeFIG. 7). The gate dielectric layer108can be a silicon dioxide gate dielectric layer. Alternatively and preferably, the gate dielectric layer108can be a high-K gate dielectric layer. The high-K gate dielectric layer can be, for example, a dielectric material with a dielectric constant that is greater than the dielectric constant of silicon dioxide (i.e., greater than 3.9). Exemplary high-K dielectric materials include, but are not limited to, hafnium (HO-based dielectrics (e.g., hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, hafnium aluminum oxide, etc.) or other suitable high-k dielectrics (e.g., aluminum oxide, tantalum oxide, zirconium oxide, etc.). Techniques for conformally depositing such gate dielectric materials are well known in the art and, thus, the details have been omitted from this specification in order to allow the reader to focus on the salient aspects of the disclosed methods.

Next, at least one gate conductor layer109can be formed on the gate dielectric layer108and recessed so that the top surface of the gate conductor layer109is below the level of the bottom of the stack of sacrificial layers in each of the multi-layer fins (16, seeFIG. 8). The gate conductor layer109can be, for example, an in situ doped polysilicon gate conductor layer. Alternatively and preferably, the gate conductor layer109can include a conformal work function metal layer and a fill metal layer on the conformal work function metal layer. The metal material or metal alloy material of such the work function metal layer can be preselected in order to achieve the optimal gate conductor work function given the conductivity type of the FET. For example, the optimal gate conductor work function of N-type VFETs will be, for example, between 3.9 eV and about 4.2 eV. Exemplary metals (and metal alloys) having a work function within this range include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, and alloys thereof, such as, hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. The optimal gate conductor work function for a P-type VFETs will be, for example, between about 4.9 eV and about 5.2 eV. Exemplary metals (and metal alloys) having a work function within this range include, but are not limited to, ruthenium, palladium, platinum, cobalt, and nickel, as well as metal oxides (aluminum carbon oxide, aluminum titanium carbon oxide, etc.) and metal nitrides (e.g., titanium nitride, titanium silicon nitride, tantalum silicon nitride, titanium aluminum nitride, tantalum aluminum nitride, etc.). Exemplary fill metals include, but are not limited to, tungsten, aluminum and cobalt. It should be noted that, depending upon the selective etch process used to recess the gate conductor layer109, the gate dielectric layer108may also be recessed, as illustrated. Alternatively, the gate dielectric layer108may remain on the top surfaces and sidewalls of the multi-layer fins.

Upper dielectric spacers169,149can then be formed on the sidewalls of the exposed portions of the multi-layer fins161,141(18, seeFIG. 9). The upper dielectric spacers can be formed, for example, using conventional sidewall spacer formation techniques. That is, a relatively thin conformal upper dielectric spacer layer can be deposited over the partially completed structure. A directional etch process can then be performed in order to remove horizontal portions of the upper dielectric spacer layer from horizontal surfaces, leaving vertical portions of the upper dielectric spacer layer intact and thereby forming a first upper dielectric spacer169above the gate conductor layer109and positioned laterally immediately adjacent to the first sidewalls of the first multi-layer fin161and a second upper dielectric spacer149above the gate conductor layer109and positioned laterally immediately adjacent to the second sidewalls of the second multi-layer fin141. The upper dielectric spacer layer can be made, for example, of silicon nitride and, thus, the first upper dielectric spacer169and the second upper dielectric spacer149can be silicon nitride spacers.

Subsequently, a gate/lower dielectric spacer patterning process can be performed (20).

For example, conventional lithographic patterning and etch processes could be performed to pattern the gate and lower dielectric spacer at process20. That is, a blanket mask layer (e.g., an optical planarization layer (OPL)) can be deposited (e.g., using a spin-on process) so as to cover the partially completed structure. Optionally, the mask layer can further be etched back and additional OPL material can be re-deposited to improve uniformity. Then, an anti-reflective coating (ARC) can be formed on the top surface of the mask layer and a photoresist layer can be formed on the ARC. The photoresist layer can be patterned with desired gate/lower dielectric spacer shapes above first device region and the second device region. Directional etch processes can then be performed to transfer the image of these shapes through the ARC and into and through the mask layer, thereby forming a first mask167over and on opposing sides of the first multi-layer fin161and a second mask147over and on opposing sides of the second multi-layer fin141(seeFIG. 10). Using the first mask167and the second mask147, additional directional etch processes can be performed to etch through the gate conductor layer109, the gate dielectric layer108and the lower dielectric spacer layer107, thereby forming the following: for the first VFET, a first lower dielectric spacer168above and immediately adjacent to the first lower source/drain region162and laterally surrounding and immediately adjacent to the first sidewalls of the first multi-layer fin161and a first gate164(including portions of the gate dielectric layer108and gate conductor layer109) above and immediately adjacent to the first lower dielectric spacer168and laterally surrounding and immediately adjacent to the first sidewalls of the first multi-layer fin161at a first channel region163; and, for the second VFET, a second lower dielectric spacer148above and immediately adjacent to the second lower source/drain region142and laterally surrounding and immediately adjacent to the second sidewalls of the second multi-layer fin141and a second gate144(including portions of the gate dielectric layer108and gate conductor layer109) above and immediately adjacent to the second lower dielectric spacer148and laterally surrounding and immediately adjacent to the second sidewalls of the second multi-layer fin141at a second channel region143(seeFIG. 11). As shown inFIG. 11, the first and second lower dielectric spacers168,148will have essentially co-planar top surfaces and the first and second gates164,144on top of the first and second lower dielectric spacers will also have essentially co-planar top surfaces. Thus, the first gate164and the second gate144will have essentially equal gate lengths and, thereby essentially equal channel lengths. The first mask167and the second mask147can then be selectively removed.

Alternatively, if the upper dielectric spacers169and149were formed so as to be relatively thick, then lithographic patterning, as described above, could be avoided. Instead, the relatively thick upper dielectric spacers169and149could function as the first mask and the second mask used during the etching of the gate and lower dielectric spacers at process20.

Next, a blanket interlayer dielectric (ILD) layer112can be deposited onto the partially completed structure and polished (22, seeFIG. 12). The ILD layer112can be, for example, a silicon oxide layer or a layer of some other suitable ILD material (e.g., borophosphosilicate glass (BPS G), tetraethyl orthosilicate (TEOS), fluorinated tetraethyl orthosilicate (FTEOS), etc.). The polishing process (e.g., a chemical mechanical polishing (CMP) process) can be performed to planarize the top surface of the ILD layer112and further to expose the fourth sacrificial layer105within both the first multi-layer fin161and the second multi-layer fin141. Since, as mentioned above, the first multi-layer fin161and first upper dielectric spacer169are initially taller than the second multi-layer fin141and second upper dielectric spacer149, the polishing process used to expose the fourth sacrificial layer105within the second multi-layer fin141will thin the fourth sacrificial layer105within the first multi-layer fin161and reduce the height of the first upper dielectric spacer169so that the first and second upper dielectric spacers169,149will have approximately equal heights as measured from the top surfaces of the first and second gates164,144to the top surfaces of the first and second upper dielectric spacers169,149, respectively. Those skilled in the art will recognize that, due to the CMP or other incoming process non-uniformity, there may be some various in the heights of the first and second upper dielectric spacers169,149. Wafer to wafer or wafer center to wafer edge variations may also occur due to process non-uniformity.

Multiple etch processes can then be performed, which remove all of the sacrificial layers from the first multi-layer fin161and the second multi-layer fin141(24).

Specifically, a selective etch process can be used to selectively remove the fourth sacrificial layer105from both the first multi-layer fin161and the second multi-layer fin141(seeFIG. 13). If, as mentioned above, the fourth sacrificial layer105and the first and second upper dielectric spacers169,149are made of silicon nitride, the third sacrificial layer104is made of amorphous silicon and the ILD layer112is made of silicon dioxide, this selective etch process can be selective to silicon nitride over amorphous silicon and silicon dioxide and can also etch back the first and second upper dielectric spacers169,149. Etch processes suitable for selectively etching silicon nitride over silicon and silicon dioxide are well known in the art and, thus, the details of these processes have been omitted from this specification in order to allow the reader to focus on the salient aspects of the disclosed method.

An additional selective etch process can be used to selectively remove the third sacrificial layer104from both the first multi-layer fin161and the second multi-layer fin141(seeFIG. 14). If, as mentioned above, the third sacrificial layer104is made of amorphous silicon, the upper dielectric spacers169,149are made of silicon nitride, and the second sacrificial layer103and the ILD layer112are made of silicon dioxide, the additional selective etch process can be selective to amorphous silicon over silicon nitride and silicon dioxide. Exemplary selective etch processes that could be used include a hot ammonia (NH3) wet etch process or tetramethylammonium hydroxide (TMAH) wet process.

A selective isotropic etch process can then be used to selectively remove the second sacrificial layer103from both the first multi-layer fin161and the second multi-layer fin141(seeFIG. 15). If, as mentioned above, the second sacrificial layer103is made of silicon dioxide, the upper dielectric spacers169,149and the first sacrificial layer102are made of silicon nitride, and the semiconductor layer101is made of silicon, this selective isotropic etch process can be selective to silicon dioxide over silicon nitride and silicon. It should be noted that, if the ILD layer112were also made of silicon dioxide, exposed horizontal and vertical surfaces of the ILD layer112would also be etched back, as illustrated. One exemplary selective isotropic etch process that could be used is a diluted hydrofluoric acid (DHF) wet etch process.

Finally, the last of the multiple etch processes used to remove the sacrificial layers can be an additional selective isotropic etch process (seeFIG. 16). At this point, the only remaining sacrificial layer will be the first sacrificial layer102(i.e., the extra sacrificial layer) on the first multi-layer fin161. If, as mentioned above, the first sacrificial layer102and the upper dielectric spacers169,149are made of silicon nitride, the ILD layer112is made of silicon dioxide and the semiconductor layer101is made of silicon, this additional selective isotropic etch process can be selective to silicon nitride over silicon dioxide and silicon. As a result, this additional selective isotropic etch process will, not only remove the first sacrificial layer102(i.e., the extra sacrificial layer) from the first multi-layer fin161, but will also etch back exposed surfaces of the first upper dielectric spacer169and the second upper dielectric spacer149. However, due to the presence of the first sacrificial layer102(e.g., the extra sacrificial layer) on the first multi-layer fin161, the second upper dielectric spacer149will be etched back to a greater degree than the first upper dielectric spacer169. That is, this isotropic etch process, the first upper dielectric spacer169will be partially protected by the first sacrificial layer102(i.e., the extra sacrificial layer) until the first sacrificial layer102is removed and, thus, the second upper dielectric spacer149will be etched back faster than the first upper dielectric spacer169.

As a result, following this additional selective isotropic etch process, the first upper dielectric spacer169will be taller (as measured from the top surface of the first gate164to the top surface of the first upper dielectric spacer169) than the second upper dielectric spacer149(as measured from the top surface of the second gate144to the top surface of the second upper dielectric spacer149). That is, the first upper dielectric spacer169will have a first height (h1), the second upper dielectric spacer149will have a second height (h2), and the first height (h1) will be greater than the second height (h2). The difference in heights of the first upper dielectric spacer169and the second upper dielectric spacer149will essentially be equal to the thickness of the first sacrificial layer102such that it can be accurately controlled during processing. Thus, for example, if the first sacrificial layer102(e.g., the extra sacrificial layer) is deposited so as to have a thickness of approximately 2-5 nm, then the difference in heights of the first upper dielectric spacer169and the second upper dielectric spacer149following this additional selective isotropic etch process will also be approximately 2-5 nm. Etch processes suitable for selectively and isotropically etching silicon nitride over silicon and silicon dioxide are well known in the art and, thus, the details of these processes have been omitted from this specification in order to allow the reader to focus on the salient aspects of the disclosed method.

It should be noted that, following removal of all of the sacrificial layers from the first multi-layer fin161and the second multi-layer fin141at process24, only those portions of the first multi-layer fin161and second multi-layer fin141that were etched into upper portion101′ of the semiconductor layer101will remain. In other words, removing all of the sacrificial layers from the first multi-layer fin161and the second multi-layer fin141, effectively creates single layer semiconductor fins and, particularly, a first semiconductor fin165and a second semiconductor fin145. Additionally, it should be noted that because the final etch process of selectively and isotropically removes the first sacrificial layer102(i.e., the extra sacrificial layer) from the first multi-layer fin161and also etches back exposed surfaces of the first upper dielectric spacer169and the second upper dielectric spacer149without etching the semiconductor material below, the method eliminates any height differences in the remaining semiconductor fins165,145while ensuring that first and second upper dielectric spacers have the different heights, as described above. Thus, as illustrated, the top surfaces of the first semiconductor fin165and the second semiconductor fin145will be approximately level (i.e., co-planar). Additionally, the top surface of the first upper dielectric spacer169will be approximately level with the top surface of the first semiconductor fin165, but the top surface of the second upper dielectric spacer149will be below the level of the top surface of the second semiconductor fin145by approximately 2-5 nm. Thus, portions of the sidewalls of the second semiconductor fin145above the second upper dielectric spacer149are exposed.

After the multiple etch processes are performed, a first upper source/drain region166can be formed adjacent to the top of the first semiconductor fin165above the first upper dielectric spacer169to complete the first VFET160′ and a second upper source/drain region146can be formed adjacent to the top of the second semiconductor fin145above the second upper dielectric spacer149to complete the second VFET140′ (26, seeFIG. 17). The upper source/drain regions166,146can be concurrently formed by, for example, epitaxially depositing semiconductor material onto the exposed surfaces of the first and second semiconductor fins165,145above the first and second upper dielectric spacers169,149, respectively. That is, the epitaxial semiconductor material will be deposited onto the exposed top surface of the first semiconductor fin165and onto the exposed top surface and sidewalls of the second semiconductor fin145. The semiconductor material can be in situ doped during the epitaxial deposition process so that the upper source/drain regions166,146have the second type conductivity at a relatively high conductivity level (e.g., N+ conductivity in the case of N-type VFETs or P+ conductivity in the case of P-type VFETs). It should be noted that because of the difference in heights between the first and second upper dielectric spacers169,149and, thereby the different amount of exposed surfaces of the first and second semiconductor fins165,145upon which the epitaxial semiconductor material is deposited at process26, during a subsequently performed dopant activation anneal, there will be a greater amount of dopant diffusion from the second upper source/drain region146toward the second channel region143of the second VFET as compared to the amount of dopant diffusion from the first upper source/drain region166toward the first channel region163of the first VFET. As a result, a source/drain dopant diffusion area146′ in the second top end of the second semiconductor fin145will be larger than a source/drain dopant diffusion area166′ in the first top end of the first semiconductor fin165and, thus, the second upper source/drain region146(which includes the source/drain dopant diffusion area146′ within the second semiconductor fin145) will be closer to the second channel region143than the first upper source/drain region166(which includes the source/drain dopant diffusion area166′ within the first semiconductor fin165) is to first channel region163and the second VFET will have a lower threshold voltage than the first VFET.

Additional processing can subsequently be performed to complete the IC structure100(28). This additional processing can include, but is not limited to, performance of a polishing process (e.g., a CMP process) to planarize the top surface of the ILD layer112(seeFIG. 18), deposition of at least one additional ILD layer over the ILD layer112and upper source/drain regions166,146, formation of middle of the line (MOL) contacts to the upper and lower source/drain regions and the gates of the VFETs, performance of back end of the line (BEOL) processing, etc. Optionally, instead polishing the ILD layer112down to the top surfaces of the upper source/drain regions166,146, as illustrated, the MOL contacts to the upper source/drain regions can be formed within the existing openings in the ILD layer112above the upper source/drain regions.

In any case, in the method described above, as result of the first upper dielectric spacer169in the first VFET160′ being taller than the second upper dielectric spacer149in the second VFET140′, spacing between the first upper source/drain region166and the first channel region163in the first semiconductor fin165of the first VFET160′ will be greater than spacing between the second upper source/drain region146and the second channel region143in the second semiconductor fin of the second VFET140′. This difference in spacing between the the upper source/drain regions and the channel regions of the two VFETs causes the first Vt of the first VFET160′ to be greater than the second Vt of the second VFET140′, as discussed above, and, thereby causes the first switching speed of the first VFET160′ to be slower than the second switching speed of the second VFET140′.

Referring toFIG. 18, also disclosed herein is an integrated circuit (IC) structure100formed according to the method described above so as to have multiple vertical field effect transistors (VFETs), including a first VFET160′ and a second VFET140′, having the same type conductivity (e.g., both P-type VFETs or both N-type VFETs) but different threshold voltages (Vts) and, thereby different switching speeds.

Specifically, the IC structure100can include a first VFET160′ and a second VFET140′ on a semiconductor substrate101. The semiconductor substrate can be a bulk semiconductor substrate (e.g., a bulk silicon substrate), as illustrated. Alternatively, the semiconductor substrate can be a semiconductor layer of a semiconductor-on-insulator wafer (e.g., a silicon-on-insulator (SOI) wafer or any other suitable semiconductor-on-insulator wafer.

The first VFET160′ can have a first lower source/drain region162in the semiconductor substrate101. The first lower source/drain region162can be a dopant implant region. Alternatively, the first lower source/drain region162can be a doped epitaxial semiconductor region. In any case, the first source/drain regions162can be doped so as to have a second type conductivity at a relatively high conductivity level (e.g., N+ conductivity in the case of N-type VFETs or P+ conductivity in the case of P-type VFETs).

The first VFET160′ can further have a first semiconductor fin165with a first bottom end above and immediately adjacent to the first lower source/drain region162and a first top end opposite the first bottom end. The first semiconductor fin165can have a first channel region163between the first bottom end and the first top end. The first channel region163can be undoped for enhanced mobility. Alternatively, the first channel region163can be doped so as to have a first type conductivity at a relatively low conductivity level (e.g., P− conductivity in the case of N-type VFETs or N− conductivity in the case of P-type VFETs).

The first VFET160′ can further have a first lower dielectric spacer168(e.g., a first lower silicon nitride spacer) above and immediately adjacent to the first lower source/drain region162and laterally surrounding and immediately adjacent to first sidewalls of the first semiconductor fin165near the first bottom end.

The first VFET160′ can further have a first gate164above and immediately adjacent to the first lower dielectric spacer168and further laterally surrounding and immediately adjacent to the first sidewalls of the first semiconductor fin165at the first channel region163. The first gate164can include a gate dielectric layer (e.g., a silicon dioxide gate conductor layer or a high-K gate dielectric layer, as discussed in greater detail above with regard to the method) and a gate conductor layer (e.g., a doped polysilicon layer or a stack of gate conductor layers including a work function metal layer and a fill metal layer, as discussed in greater detail above with regard to the method) on the gate dielectric layer.

The first VFET160′ can further have a first upper dielectric spacer169(e.g., a first upper silicon nitride spacer) above and immediately adjacent to the first gate164and laterally surrounding and immediately adjacent to the first sidewalls of the first semiconductor fin165near the first top end. The first upper dielectric spacer169has a first height (h1). Top surfaces of the first upper dielectric spacer169and the first semiconductor fin165can be approximately level (i.e., co-planar).

The first VFET160′ can further have a first upper source/drain region166. The first upper source/drain region166can include in-situ doped epitaxial semiconductor material above and immediately adjacent to the first top end of the first semiconductor fin165and further extending laterally over and immediately adjacent to the first upper dielectric spacer169. The first upper source/drain region166can further include a first source/drain dopant diffusion area166′ within the first top end of the first semiconductor fin165. The first upper source/drain region166(including the in-situ doped epitaxial semiconductor material and the first upper source/drain dopant diffusion area166′) can have a second type conductivity at a relatively high conductivity level (e.g., N+ conductivity in the case of N-type VFETs or P+ conductivity in the case of P-type VFETs).

Thus, in the first VFET160′, the first semiconductor fin165extends essentially vertically from the first lower source/drain region162to the first upper source/drain region166. Additionally, first lower and upper dielectric spacers168,169physically separate the first gate164from the first lower and upper source/drain regions162,166, respectively. That is, the first lower dielectric spacer168is positioned laterally adjacent to the first semiconductor fin165and stacked between the first lower source/drain region162and the first gate164. Furthermore, the first upper dielectric spacer169is positioned laterally adjacent to the first semiconductor fin165and is stacked between the first gate164and the first upper source/drain region166.

Similarly, the second VFET140′ can have a second lower source/drain region142in the semiconductor substrate101. The second lower source/drain region142can be a dopant implant region. Alternatively, the second lower source/drain region142can be a doped epitaxial semiconductor region. In any case, the second lower source/drain regions142can be doped so as to have a second type conductivity at a relatively high conductivity level (e.g., N+ conductivity in the case of N-type VFETs or P+ conductivity in the case of P-type VFETs).

The second VFET140′ can further have a second semiconductor fin145with a second bottom end above and immediately adjacent to the second lower source/drain region142and a second top end opposite the second bottom end. Top surfaces of the second semiconductor fin145and the first semiconductor fin165can be approximately level (i.e., co-planar). Thus, the first semiconductor fin145and the second semiconductor fin165can have approximately equal heights as measured from the top surface of the substrate. The second semiconductor fin145can have a second channel region143between the second bottom end and the second top end. The second channel region143can be undoped for enhanced mobility. Alternatively, the second channel region143can be doped so as to have a second type conductivity at a relatively low conductivity level (e.g., P− conductivity in the case of N-type VFETs or N− conductivity in the case of P-type VFETs).

The second VFET140′ can further have a second lower dielectric spacer148(e.g., a second lower silicon nitride spacer) above and immediately adjacent to the second lower source/drain region142and laterally surrounding and immediately adjacent to second sidewalls of the second semiconductor fin145near the second bottom end.

The second VFET140′ can further have a second gate144above and immediately adjacent to the second lower dielectric spacer148and further laterally surrounding and immediately adjacent to the second sidewalls of the second semiconductor fin145at the second channel region143. The second gate144can include a gate dielectric layer (e.g., a silicon dioxide gate conductor layer or a high-K gate dielectric layer, as discussed in greater detail above with regard to the method) and a gate conductor layer (e.g., a doped polysilicon layer or a stack of gate conductor layers including a work function metal layer and a fill metal layer, as discussed in greater detail above with regard to the method) on the gate dielectric layer.

The second VFET140′ can further have a second upper dielectric spacer149(e.g., a second upper silicon nitride spacer) above and immediately adjacent to the second gate144and laterally surrounding and immediately adjacent to the second sidewalls of the second semiconductor fin145near the second top end. The second upper dielectric spacer149is shorter than the first upper dielectric spacer169. That is, the second upper dielectric spacer149has a second height (h2) that is less than the first height (h1) of the first upper dielectric spacer169.

The second VFET140′ can further have a second upper source/drain region146. The second upper source/drain region146can include in-situ doped epitaxial semiconductor material immediately adjacent to the second top end of the second semiconductor fin145and further extending laterally over and immediately adjacent to the second upper dielectric spacer149. Specifically, the in-situ doped epitaxial semiconductor material can be immediately adjacent to the top surface of the second semiconductor fin145and also immediately adjacent to portions of the second sidewalls of the second semiconductor fin145above the second upper dielectric spacer149. The second upper source/drain region146can further include a second source/drain dopant diffusion area146′ within the second top end of the second semiconductor fin145. The second upper source/drain region146(including the in-situ doped epitaxial semiconductor material and the second source/drain dopant diffusion area146′) can be doped so as to have a second type conductivity at a relatively high conductivity level (e.g., N+ conductivity in the case of N-type VFETs or P+ conductivity in the case of P-type VFETs).

Thus, in the second VFET140′, the second semiconductor fin145extends essentially vertically from the second lower source/drain region142to the second upper source/drain region146. Additionally, second lower and upper dielectric spacers148,149physically separate the second gate144from the second lower and upper source/drain regions142,146, respectively. That is, the second lower dielectric spacer148is positioned laterally adjacent to the second semiconductor fin145and stacked between the second lower source/drain region142and the second gate144. Furthermore, the second upper dielectric spacer149is positioned laterally adjacent to the second semiconductor fin145and is stacked between the second gate144and the second upper source/drain region146.

Additionally, as shown inFIG. 18, in this IC structure100, the first lower dielectric spacer168of the first VFET160′ and the second lower dielectric spacer148of the second VFET140′ will have essentially co-planar top surfaces. Furthermore, the first gate164on top of the first lower dielectric spacer168in the first VFET160′ and the second gate144on top of the second lower dielectric spacer148in the second VFET140′ will also have essentially co-planar top surfaces. Thus, the first gate164and the second gate144will have essentially equal gate lengths and, thereby essentially equal channel lengths.

As described above, the first VFET160′ and the second VFET140′ are almost identical in structure. However, due to the method used to form these VFETs, the first upper dielectric spacer169of the first VFET160′ is taller than the second upper dielectric spacer149of the second VFET140′. The difference in heights can be selectively controlled and can, for example, be between 2 and 10 nm (e.g., approximately 2-5 nm). In any case, due to the difference in heights between the first and second upper dielectric spacers169,149, the epitaxial semiconductor material of the first upper source/drain region166is grown immediately adjacent to the top surface only of the first semiconductor fin165, whereas the epitaxial semiconductor material of the second upper source/drain region146is grown immediately adjacent to the top surface and portions of the sidewalls of the second semiconductor fin145above the second upper dielectric spacer149. As a result, the second source/drain dopant diffusion area146′ in the second top end of the second semiconductor fin145is larger than the first source/drain dopant diffusion area166′ in the first top end of the first semiconductor fin165. Thus, the second upper source/drain region146(which includes in-situ doped epitaxial semiconductor material and the second source/drain dopant diffusion area146′ within the second semiconductor fin145) is closer to the second channel region143than the first upper source/drain region166(which includes the in-situ doped epitaxial semiconductor material and the first source/drain dopant diffusion area166′ within the first semiconductor fin165) is to first channel region163. This difference in spacing between the channel regions and the upper source/drain regions of the two VFETs causes the first Vt of the first VFET160′ to be greater than the second Vt of the second VFET140′ and, thereby causes the first switching speed of the first VFET160′ to be slower than the second switching speed of the second VFET140′.