THIN FILM TRANSISTOR, FABRICATION METHOD THEREOF, AND DISPLAY APPARATUS COMPRISING THE SAME

A thin film transistor includes an active layer including an oxide semiconductor layer, a metal layer disposed on the active layer and overlapping with at least a portion of the active layer, a gate electrode spaced apart from the active layer, and overlapping with at least a portion of the active layer, and a gate insulating film between the active layer and the gate electrode, wherein the active layer includes a channel portion, a first connection portion contacting one side of the channel portion, and a second connection portion contacting the other side of the channel portion, and wherein the metal layer includes a first metal layer contacting an upper surface of the first connection portion, and a second metal layer contacting an upper surface of the second connection portion, a fabrication method of the thin film transistor, and a display apparatus comprising the same.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the priorities of Korean Patent Application No. 10-2021-0117987 filed on Sep. 3, 2021 and Korean Patent Application No. 10-2021-0194776 filed on Dec. 31, 2021, which are hereby incorporated by reference in their entirety.

BACKGROUND

Field of the Disclosure

The present disclosure relates to a thin film transistor and a display apparatus comprising the same.

Description of the Background

According to a material constituting an active layer, a thin film transistor may be divided into an amorphous silicon thin film transistor using an active layer of amorphous silicon, a polycrystalline silicon thin film transistor using as an active layer of polycrystalline silicon, and an oxide semiconductor thin film transistor using as an active layer of oxide semiconductor.

According as the oxide semiconductor thin film transistor TFT have a large resistance change according to the content of oxygen, it facilitates obtaining the desired physical properties. Also, since the oxide constituting the active layer becomes a thin film at a relatively low temperature for a fabrication process of the oxide semiconductor thin film transistor, a manufacturing cost is low. The oxide semiconductor is transparent owing to the properties of the oxide, whereby it is favorable to a realization of a transparent display apparatus.

Preferably, a thin film transistor used as a driving device of a display apparatus has a large S-factor for a grayscale representation. Therefore, it necessarily requires a study for securing a large S-factor in a thin film transistor used as a driving device of a display apparatus.

SUMMARY

Accordingly, the present disclosure is to provide a thin film transistor capable of improving an S-factor, a display apparatus comprising the thin film transistor with the improved S-factor, and a fabrication method of the thin film transistor.

The present disclosure is also to provide a driving thin film transistor with improved S-factor by doping dopant in an active layer.

The present disclosure is also to provide a thin film transistor capable of reducing defect probability by forming a conductor portion of an active layer through an ion implantation process regardless of a process error of a gate electrode.

The present disclosure is also to provide a driving thin film transistor capable of preventing deterioration of the electrical characteristics through an active layer being conductive by hydrogen, and a display apparatus comprising the same.

Further, the present disclosure is to provide a display apparatus enabling a great grayscale representation by the use of driving thin film transistor having a large S-factor.

In an aspect of the present disclosure, a thin film transistor includes an active layer including an oxide semiconductor layer, a metal layer disposed on the active layer and overlapping with at least a portion of the active layer, a gate electrode provided on the active layer and spaced apart from the active layer, and overlapping with at least a portion of the active layer, and a gate insulating film between the active layer and the gate electrode, wherein the active layer includes a channel portion, a first connection portion contacting one side of the channel portion, and a second connection portion contacting the other side of the channel portion, and wherein the metal layer includes a first metal layer contacting an upper surface of the first connection portion, and a second metal layer contacting an upper surface of the second connection portion.

In another aspect of the present disclosure, a display apparatus comprising the above thin film transistor.

In another aspect of the present disclosure, a fabrication method of a thin film transistor includes forming a light shielding layer on a substrate, forming a buffer layer covering the light shielding layer, forming an active layer on the buffer layer, forming a metal layer on the active layer, patterning the active layer and the metal layer, forming a gate insulating film on the patterned active layer, forming a gate electrode on the gate insulating film, and implanting dopant to the patterned active layer.

DETAILED DESCRIPTION

The shapes, sizes, ratios, angles, and numbers disclosed in the drawings for describing aspects of the present disclosure are merely examples, and thus the present disclosure is not limited to the illustrated details. Like reference numerals refer to like elements throughout. In the following description, when the detailed description of the relevant known function or configuration is determined to unnecessarily obscure the important point of the present disclosure, the detailed description will be omitted.

In the case in which “comprise,” “have,” and “include” described in the present specification are used, another part may also be present unless “only” is used. The terms in a singular form may include plural forms unless noted to the contrary.

In construing an element, the element is construed as including an error region although there is no explicit description thereof.

In describing a positional relationship, for example, when the positional order is described as “on,” “above,” “below,” “beneath”, and “next,” the case of no contact therebetween may be included, unless “just” or “direct” is used. If it is mentioned that a first element is positioned “on” a second element, it does not mean that the first element is essentially positioned above the second element in the figure. The upper part and the lower part of an object concerned may be changed depending on the orientation of the object. Consequently, the case in which a first element is positioned “on” a second element includes the case in which the first element is positioned “below” the second element as well as the case in which the first element is positioned “above” the second element in the figure or in an actual configuration.

In describing a temporal relationship, for example, when the temporal order is described as “after,” “subsequent,” “next,” and “before,” a case which is not continuous may be included, unless “just” or “direct” is used.

It should be understood that the term “at least one” includes all combinations related with any one item. For example, “at least one among a first element, a second element and a third element” may include all combinations of two or more elements selected from the first, second and third elements as well as each element of the first, second and third elements.

In the drawings, the same or similar elements are denoted by the same reference numerals even though they are depicted in different drawings.

In the aspects of the present disclosure, a source electrode and a drain electrode are distinguished from each other, for convenience of explanation. However, the source electrode and the drain electrode are used interchangeably. Thus, the source electrode may be the drain electrode, and the drain electrode may be the source electrode. Also, the source electrode in any one aspect of the present disclosure may be the drain electrode in another aspect of the present disclosure, and the drain electrode in any one aspect of the present disclosure may be the source electrode in another aspect of the present disclosure.

In one or more aspects of the present disclosure, for convenience of explanation, a source region is distinguished from a source electrode, and a drain region is distinguished from a drain electrode. However, aspects of the present disclosure are not limited to this structure. For example, a source region may be a source electrode, and a drain region may be a drain electrode. Also, a source region may be a drain electrode, and a drain region may be a source electrode.

FIG.1is a plan view of a thin film transistor according to the aspect of the present disclosure, andFIG.2is a cross sectional view along I-I′ ofFIG.1.

Referring toFIGS.1and2, the thin film transistor100according to the aspect of the present disclosure may include a light shielding layer250on a substrate110, a buffer layer120on the light shielding layer250, an active layer130on the buffer layer120, a first metal layer145aoverlapping a first connection portion130aof the active layer130, a second metal layer145boverlapping a second connection portion130bof the active layer130, a gate insulating film140on the first metal layer145a,the second metal layer145band the active layer130, a gate electrode150on the gate insulating film140, and an interlayer insulating film160for covering the active layer130and the gate electrode150.

The substrate110may be a glass substrate, a curable or bendable thin film glass substrate, a plastic substrate, or a silicon wafer substrate. If using plastic for the substrate110, transparent plastic having flexibility, for example, polyimide may be used. If the substrate110is formed of polyimide, heat resistant polyimide capable of enduring a high temperature may be used in consideration of a high temperature deposition process on the substrate110.

Then, the light shielding layer250may be disposed on the substrate110. The light shielding layer250overlaps a channel portion130nof the active layer130.

The light shielding layer250may be made of a material having the light blocking characteristics or light reflection characteristics. The light shielding layers250may be formed in a single-layered structure or a multi-layered structure made of metal such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and silver (Ag), or an alloy thereof. However, it is not limited to these materials, and the light shielding layer250may be formed of various materials generally known to those in the art.

The light shielding layer250may include a first light shielding layer251, and a second light shielding layer252on the first light shielding layer251. The light shielding layer250blocks incident light provided from the external, to thereby protect the active layer130. The light shielding layer250may not be disposed on a whole surface of the substrate110, but may be disposed on at least a portion overlapping the thin film transistor100.

According to one aspect of the present disclosure, the light shielding layer250may include at least one of molybdenum (Mo) and titanium (Ti). Also, each of the first light shielding layer251and the second light shielding layer252may include at least one of molybdenum Mo and titanium Ti.

For example, the first light shielding layer251may include molybdenum Mo, and the second light shielding layer252may include titanium (Ti).

If the light shielding layer250includes titanium (Ti), it is possible to reduce or minimize an influence of hydrogen, which is diffused in an inorganic layer such as the buffer layer120and the gate insulating film140, on the electrical characteristics of the thin film transistor100.

The buffer layer120may be disposed on the light shielding layer250and the substrate110.

According to the aspect of the present disclosure, the buffer layer120may be formed of a multi-layer by stacking one or more inorganic films of a silicon oxide film (SiOx), a silicon nitride layer (SiN), and a silicon oxynitride layer (SiON). The buffer layer120protects the gate electrode150. Thus, other components of the thin film transistor100including the active layer130, which will be described later, may be disposed on the buffer layer120.

The active layer130may be disposed on the buffer layer120.

The active layer130may be disposed to overlap the light shielding layer250and the gate electrode150. The active layer130includes the channel portion130n,the first connection portion130a,and the second connection portion130b.The first connection portion130acontacts one side of the channel portion130n,and the second connection portion130bcontacts the other side of the channel portion130n.

The first connection portion130aand the second connection portion130bmay be formed by selective conduction of the active layer130. The first connection portion130aand the second connection portion130bmay be referred to as conductor portions.

For example, the first connection portion130aand the second connection portion130bmay be formed by implanting dopants by performing an ion implantation process using the gate electrode150spaced apart from the active layer130as a mask pattern. When the ion implantation process of the dopant is performed on the first connection portion130aand the second connection portion130bof the active layer130, the first connection portion130aand the second connection portion130bmay be formed by the selective conduction except for the channel portion130nmasked by the gate electrode150. According to one aspect of the present disclosure, the dopant for the conduction of the first connection portion130aand the second connection portion130bmay include at least one of boron (B), phosphorus (P), fluorine (F), and hydrogen (H).

The metal layers145aand145bmay be disposed on the active layer130. The metal layers145aand145bmay partially overlap at least a portion of the active layer130. The metal layers145aand145bmay include the first metal layer145acontacting an upper surface of the first connection portion130a,and the second metal layer145bcontacting an upper surface of the second connection portion130b.

In detail, the first metal layer145aand the second metal layer145bmay be disposed on the active layer130. More specifically, the first metal layer145amay overlap with the first connection portion130aof the active layer130, and the second metal layer145bmay overlap with the second connection portion130bof the active layer130. The first metal layer145aand the second metal layer145bmay include at least one of molybdenum (Mo) and titanium (Ti).

According to one aspect of the present disclosure, the first metal layer145aand the second metal layer145bmay include molybdenum (Mo) or molybdenum (Mo) alloy.

According to one aspect of the present disclosure, when the first metal layer145aand the second metal layer145binclude molybdenum (Mo), an S-factor of the thin film transistor100may be improved by an ion doping effect of molybdenum (Mo) in the channel portion130nof the active layer130, which is introduced during a process for forming the first metal layer145aand the second metal layer145b,whereby it may be favorable to a grayscale representation of the display apparatus including the thin film transistor100according to the present disclosure. Therefore, the thin film transistor according to the present disclosure may be implemented as a driving thin film transistor.

In detail, before the first metal layer145aand the second metal layer145bare configured to correspond to the first connection portion130aand the second connection portion130bof the active layer130, a metal material layer may be formed while being overlapping with the entire active layer130, and then patterned to form the first metal layer145aand the second metal layer145b.Accordingly, when the first metal layer145aand the second metal layer145bare formed to overlap the entire active layer130, that is, the first connection portion130a,the second connection portion130b,and the channel portion130nof the active layer130, and then patterned, molybdenum Mo included in at least a portion of the first metal layer145aand the second metal layer145bmay be ion-implanted to the channel portion130nof the active layer130, and the thin film transistor including the channel portion130nin which molybdenum Mo is ion-implanted may have the improved S-factor.

When the active layer130is composed of an IGZO-based oxide semiconductor, the thin film transistor including the active layer130of IGZO-based oxide semiconductor may have a relatively low S-factor. During the process of forming and patterning the first metal layer145aand the second metal layer145bon the active layer130including the IGZO-based oxide semiconductor, the channel portion130nof the active layer130may be impurity-doped with molybdenum Mo. The molybdenum Mo doped in the channel portion130nof the active layer130may have an effect which is similar to that of the molybdenum Mo ion implantation process, and the molybdenum Mo may function as a carrier acceptor component in the IGZO-based oxide semiconductor, so that it is possible to reduce carriers and a current change rate relative to a voltage, thereby improving the S-factor of the thin film transistor.

For example, the S-factor of the molybdenum Mo impurity-doped IGZO-based oxide semiconductor may be increased by a value of 2 to 3 times as compared to that of the IGZO-based oxide semiconductor which is not impurity-doped with the molybdenum Mo. For example, since the thin film transistor100of the present disclosure has the improved S-factor value, the thin film transistor100of the present disclosure may be applied to a driving thin film transistor.

According to the aspect of the present disclosure, the first connection portion130aof the active layer130may be a source region, and the second connection portion130bmay be a drain region. However, the aspect of the present disclosure is not limited thereto, and the first connection portion130amay be a drain region and the second connection portion130bmay be a source region.

According to one aspect of the present disclosure, the active layer130may include an oxide semiconductor material.

The active layer130may include, for example, one of IGZO (InGaZnO)-based active material, TO(SnO)-based active material, IGO(InGaO)-based active material, IGZTO(InGaZnSnO)-based active material, GZTO(GaZnSnO)-based active material, GZO(GaZnO)-based active material, ITZO(InSnZnO)-based active material, FIZO(FeInZnO)-based active material, and GO(GaO)-based active material. However, the aspect of the present disclosure is not limited to these materials, and the active layer130may be formed of various materials generally known to those in the art. Also, the active layer130may be formed in a single-layered structure, or a multi-layered structure such as a two-layered structure or a three-layered structure obtained by stacking materials vertically.

The gate insulating film140is disposed on the buffer layer120, the active layer130, the first metal layer145aand the second metal layer145b,is disposed between the gate electrode150and the active layer130, and is configured to protect the active layer130. The gate insulating film140may include a silicon nitride film (SiNx) or a silicon oxide film (SiOx), but not limited to these materials. The gate insulating film140may be formed in a single-layered structure or a multi-layered structure.

The gate electrode150is disposed on the gate insulating film140. The gate electrode150overlaps the channel portion130nof the active layer130.

The gate electrode150may include at least one of aluminum-based metal materials such as aluminum Al or aluminum alloys, silver-based metal materials such as silver Ag or silver alloys, copper-based metal materials such as copper (Cu), copper alloys, molybdenum-based metal materials such as molybdenum (Mo), molybdenum alloys, chromium (Cr), tantalum (Ta), neodymium (Nd), and titanium (Ti).

The gate electrode150may include a first gate electrode151and a second gate electrode152. The first gate electrode151is disposed on the gate insulating film140, and may overlap the channel portion130n.The second gate electrode152may be disposed on the first gate electrode151.

According to one aspect of the present disclosure, the gate electrode150may include titanium (Ti) or molybdenum (Mo). For example, the first gate electrode151may be formed of a material including molybdenum (Mo), and the second gate electrode152may be formed of a material including titanium (Ti).

The inorganic layer adjacent to the active layer130, for example, the buffer layer120and the gate insulating film140, may be prepared by a process in which a plurality of hydrogen exists. Accordingly, the buffer layer120and the gate insulating film140may be the hydrogen-rich inorganic layer. When the buffer layer120and the gate insulating film140are exposed to a predetermined temperature after the deposition of the buffer layer120and the gate insulating film140, hydrogen may be diffused from the buffer layer120and the gate insulating film140to the active layer130. Also, when the hydrogen is diffused into the active layer130, the active layer130becomes conductive to change the electrical characteristics such as mobility and resistance of the active layer130. Accordingly, the thin film transistor100may have the unintended change of the electrical characteristic due to the changed electrical characteristics of the active layer130.

Referring to the configuration of the gate electrode150and the light shielding layer250according to the present disclosure, a second light shielding layer252and a second gate electrode152may be prepared by a metal material including titanium. When the second light shielding layer252and the second gate electrode152are formed to include titanium, the second light shielding layer252and the second gate electrode152are formed to surround the channel portion130nof the active layer130or the active layer130at the upper and lower sides, thereby preventing the unintended change in the electrical characteristics of the thin film transistor by the diffusion of hydrogen to the channel portion130nof the active layer130.

Also, although the gate electrode150and the light shielding layer250are not connected to each other in the cross-sectional structure of the thin film transistor100ofFIG.2, the gate electrode150and the light shielding layer250are in contact with each other through a third contact hole CH3, as shown in the plan view ofFIG.1. The light shielding layer250may function as a lower gate electrode of the thin film transistor100through the contact structure of the gate electrode150and the light shielding layer250. Accordingly, the thin film transistor100according to the present disclosure may have a dual gate structure of the thin film transistor including the lower gate electrode made of the light shielding layer250in addition to the gate electrode150.

The interlayer insulating film160may be disposed on the gate electrode150and the gate insulating film140.

The interlayer insulating film160may include a silicon oxide (SiOx) film or a silicon nitride (SiNx) film, and may protect the thin film transistor. In order to contact the active layer130and a first electrode171and a second electrode172, a portion of the interlayer insulating film160corresponding to contact holes CH1and CH2may be removed.

The first electrode171and the second electrode172may be disposed on the interlayer insulating film160.

The first electrode171may serve as a source electrode, and the second electrode172may serve as a drain electrode. However, the aspects of the present disclosure are not limited thereto, and the first electrode171may serve as a drain electrode, and the second electrode172may serve as a source electrode. In addition, the first connection portion130aand the second connection portion130bserve as a source electrode and a drain electrode, respectively, and the first electrode171and the second electrode172may serve as a connection electrode between the devices.

The first electrode171and the second electrode172may be connected to the active layer130through first and second contact holes CH1and CH2, respectively. Specifically, the first electrode171may be electrically connected to the first connection portion130athrough the first contact hole CH1. More specifically, the first electrode171may be electrically connected to the first connection portion130aby contacting the first metal layer145athrough the first contact hole CH1.

The second electrode172may be spaced apart from the first electrode171and may be electrically connected to the second connection portion130bthrough the second contact hole CH2. More specifically, the second electrode172may be electrically connected to the second connection portion130bby contacting the second metal layer145bthrough the second contact hole CH2.

FIG.3is a cross sectional view of a thin film transistor according to another aspect of the present disclosure. Except that a light shielding layer250is not provided below an active layer130, a thin film transistor200shown inFIG.3is identical in structure to the thin film transistor100shown inFIGS.1and2. Accordingly, the same reference numerals are assigned to the same parts, and a duplicate description thereof will be omitted.

Referring toFIG.3, an active layer130including a channel portion130n,a first connection portion130a,and a second connection portion130b,and a gate electrode150in the thin film transistor200may have the same configuration and arrangement structure as those ofFIG.2.

Accordingly, in case of the thin film transistor200according to another aspect of the present disclosure, when a first metal layer145aand a second metal layer145binclude molybdenum Mo, an S-factor of the thin film transistor200may be improved by an ion doping effect of molybdenum Mo in the channel portion130nof the active layer130, which is introduced during a process for forming the first metal layer145aand the second metal layer145b,whereby it may be favorable to a grayscale representation of a display apparatus including the thin film transistor200according to the present disclosure. Therefore, the thin film transistor200according to the present disclosure may be implemented as a driving thin film transistor.

FIGS.4A to4Fillustrate a fabrication method of the thin film transistor according to one aspect of the present disclosure.

Referring toFIG.4A, the light shielding layer250is formed on the substrate110. Then, the buffer layer120may be formed on the substrate110and the light shielding layer250, to thereby cover the light shielding layer250.

Next, the active layer130and a metal material layer145are formed on the buffer layer120. The first metal layer145aand the second metal layer145bmay be formed by patterning the metal material layer145. According to one aspect of the present disclosure, the metal material layer145may include molybdenum (Mo). For example, the metal material layer145may include molybdenum (Mo) or molybdenum titanium alloy.

InFIG.4A, the channel portion of the active layer130is not formed. However, when the metal material layer145including molybdenum Mo is formed on the active layer130, molybdenum Mo is doped onto the surface of the active layer130, that, it shows a dopant doping effect. A dopant doping of molybdenum Mo may be applied to the channel portion130nof the active layer130defined in following fabrication steps. The molybdenum Mo may function as an acceptor component in the active layer130including the oxide semiconductor, so that the S-factor of the oxide semiconductor thin film transistor may be improved by the molybdenum Mo doped in the corresponding portion of the channel portion130nof the active layer130.

Referring toFIG.4B, in order to pattern the metal material layer145and the active layer130in the following step, a photoresist PR mask pattern may be formed on the metal material layer145. The photoresist PR mask pattern is formed by performing a full exposure process and a half exposure process. The portion where the full exposure process is performed may be the remaining area except for the portion of the photoresist PR mask pattern, and the portion where the half exposure process is performed may be the area corresponding to the center portion of the photoresist PR mask pattern. The photoresist PR portion obtained after the half exposure process may have the different thickness, and the thickness of the photoresist PR portion corresponding to the channel portion130nof the active layer130, which is set in the following fabrication method, may be relatively small.

Referring toFIG.4C, a predetermined portion of the active layer130and the metal material layer145, which is not covered by the photoresist PR, may be removed by a first wet etching process. The thickness of the remaining photoresist PR may be entirely reduced by performing a dry etching process. The dry etching process may be performed until all the photoresist PR pattern of the center portion is removed.

Referring toFIG.4D, a second wet etching process may be performed using the photoresist PR remaining inFIG.4Cas a mask, and the metal material layer145exposed by the photoresist PR may be patterned. As a result, it is possible to form the configuration of the first metal layer145a,the second metal layer145b,and the active layer130of the thin film transistor of the present disclosure. The first metal layer145aand the second metal layer145bare also referred to as metal layers145aand145b.

Referring toFIG.4E, the gate insulating film140covering the active layer130, the first metal layer145aand the second metal layer145bmay be formed, and the gate electrode150may be formed in a predetermined portion above the gate insulating film140. The gate electrode150may be formed in a double layer structure including the first gate electrode151and the second gate electrode152.

Referring toFIG.4E, the dopant may be implanted to the active layer130by the ion implantation.

During the ion implantation process, the gate electrode150may function as a mask of the ion implantation process. Thus, the dopant implanted by the ion implantation process may not be implanted to the channel portion130noverlapping the gate electrode150. The first connection portion130aand the second connection portion130b,which are not overlapping with the gate electrode150, may be formed through the ion implantation process. That is, the first connection portion130aand the second connection portion130bof the active layer130may be defined by the dopant implanted by the ion implantation process. For the ion implantation, the first metal layer145aand the second metal layer145bmay have a thickness of 300 Å or less.

Referring toFIG.4F, the interlayer insulating film160is disposed on the gate electrode150and the gate insulating film140. The first electrode171and the second electrode172are disposed on the interlayer insulating film160, and the first electrode171and the second electrode172are connected to the first metal layer145aand the second metal layer145bthrough the first and second contact holes CH1and CH2, respectively. As a result, the thin film transistor100according to the aspect of the present disclosure may be fabricated.

FIGS.5A to5Dexplain the formation of the connection portion of the active layer by process errors of the gate electrode of the present disclosure. InFIG.5A, “L0” is a predetermined length of the gate electrode, “L1” is a predetermined length of the first connection portion130a,and “L2” is a predetermined length of the second connection portion130b.FIGS.5A to5Dshow the structure obtained after the ion implantation process.

Referring toFIG.5A, the gate electrode150of the present disclosure has the same length as the predetermined length L0, and the first connection portion130ahas the same length as the predetermined length L1, and the second connection portion130bhas the same length as the predetermined length L2.

InFIG.5B, the gate electrode150deviates from a predetermined position, and the gate electrode150is biased toward the second connection portion130b.Referring toFIG.5B, the gate electrode150is biased toward the second connection portion130b.Thus, according as the length of the first connection portion130ais increased in the direction toward the channel portion130n,a first offset length Loff1is formed. Also, according as a portion of the second connection portion130boverlaps the gate electrode150, the length of the second connection portion130bis reduced by a second offset length Loff2. InFIG.5B, even if the gate electrode150is biased to one side in a horizontal direction due to an error, the thin film transistor of the present disclosure is normally formed with the first connection portion130aand the second connection portion130bwhich are conductive by the ion implantation.

FIG.5Cillustrates a case where the length of the gate electrode150is larger than a distance between the first metal layer145aand the second metal layer145b.The length of the gate electrode150may be larger than the distance between the first metal layer145aand the second metal layer145bdue to the process error. Alternatively, in order to apply the ion implantation process according to the aspect of the present disclosure, the length of the gate electrode150may be larger than the distance between the first metal layer145aand the second metal layer145b.

Referring toFIG.5C, the length of the channel portion130nof the active layer130may be increased by the sum of the first offset length Loff1and the second offset length Loff2in the “L0” corresponding to the predetermined length of the gate electrode. InFIG.5C, even though the length of the gate electrode150may be larger the distance between the first metal layer145aand the second metal layer145bby the process error or intentional purpose, the thin film transistor of the present disclosure may be normally formed with the first connection portion130aand the second connection portion130bwhich are conductive by the ion implantation.

FIG.5Dillustrates a case where the length of the gate electrode150is smaller than a distance between the first metal layer145aand the second metal layer145b.The length of the gate electrode150may be smaller than the distance between the first metal layer145aand the second metal layer145bdue to the process error. Alternatively, in order to apply the ion implantation process according to the aspect of the present disclosure, the length of the gate electrode150may be smaller than the distance between the first metal layer145aand the second metal layer145b.

Referring toFIG.5D, even though the length of the gate electrode150may be smaller the distance between the first metal layer145aand the second metal layer145bby the process error or intentional purpose, the thin film transistor of the present disclosure may be normally formed with the first connection portion130aand the second connection portion130bwhich are conductive by the ion implantation.

In the thin film transistor according to the present disclosure, the length of the gate electrode150may be changed variously as shown inFIGS.5A to5D. Also, even though a portion of the gate electrode150overlaps the predetermined length L1of the first connection portion130aor the predetermined length L2of the second connection portion130b,it is possible to stably form the first connection portion130aand the second connection portion130b.

FIG.6is a schematic diagram of a display apparatus500according to another aspect of the present disclosure.

As shown inFIG.6, a display apparatus500according to another aspect of the present disclosure includes a display panel310, a gate driver320, a data driver330, and a controller340.

Gate lines GL and data lines DL are disposed on the display panel310, and pixels P are disposed in respective crossing areas of the gate lines GL and the data lines DL. An image is displayed by driving the pixels P.

The controller340controls the gate driver320and the data driver330.

The controller340outputs a gate control signal GCS for controlling the gate driver320and a data control signal DCS for controlling the data driver330by using a signal supplied from an external system (not shown). Also, the controller340samples input video data input from the external system and rearranges the sampled input video data, and supplies the rearranged digital video data RGB to the data driver330.

The gate control signal GCS includes a gate start pulse GSP, a gate shift clock GSC, a gate output enable signal GOE, a start signal Vst, and a gate clock GCLK. Further, control signals for controlling a shift register may be included in the gate control signal GCS.

The data control signal DCS includes a source start pulse SSP, a source shift clock signal SSC, a source output enable signal SOE, and a polarity control signal POL.

The data driver330supplies a data voltage to the data lines DL of the display panel310. Specifically, the data driver330converts the video data RGB inputted from the controller340into an analog data voltage and supplies the data voltage to the data lines DL.

The gate driver320may include the shift register350.

The shift register350sequentially supplies gate pulses to the gate lines GL during one frame by the use of start signal and gate clock transmitted from the controller340. Herein, the one frame refers to a period in which one image is outputted through the display panel310. The gate pulse has a turn-on voltage capable of turning on a switching device (thin film transistor) disposed in the pixel P.

Also, during the remaining period of one frame, in which the gate pulse is not supplied, the shift register350supplies a gate-off signal capable of turning off the switching device to the gate line GL. Hereinafter, the gate pulse and the gate-off signal are totally referred to as a scan signal SS or Scan.

According to the aspect of the present disclosure, the gate driver320may be mounted on a base substrate110. As described above, a structure in which the gate driver320is directly mounted on the base substrate110is referred to as a gate-in-panel GIP structure.

FIG.7is a circuit diagram of one pixel P ofFIG.6,FIG.8is a plan view of the pixel P ofFIG.7, andFIG.9is a cross sectional view along line III-III′ ofFIG.8.

The circuit diagram ofFIG.7is an equivalent circuit diagram of a pixel P of a display apparatus500including an organic light emitting diode OLED. The pixel P includes a display device710, and a pixel driver PDC for driving the display device710.

According to another aspect of the present disclosure, the display apparatus500includes the pixel driver PDC and the display device710. The pixel driver PDC includes a first thin film transistor TR1and a second thin film transistor TR2. The first thin film transistor TR1may include the thin film transistors100and200described above.

According to another aspect of the present disclosure, the first thin film transistor TR1is a driving transistor, and the second thin film transistor TR2is a switching transistor.

The structure of the first thin film transistor shown inFIG.9may be the same as that of the thin film transistor shown inFIG.2.

The second thin film transistor TR2is connected to a gate line GL and a data line DL, and is turned on or off by a scan signal SS supplied through the gate line GL.

The data line DL provides a data voltage Vdata to the pixel driver PDC, and the second thin film transistor TR2controls the application of the data voltage Vdata.

A driving power line PL provides a driving voltage Vdd to the display device710, and the first thin film transistor TR1controls the driving voltage Vdd. The driving voltage Vdd is a pixel driving voltage for driving an organic light emitting diode OLED corresponding to the display device710.

When the second thin film transistor TR2is turned on by the scan signal SS applied through the gate line GL from a gate driver320, the data voltage Vdata supplied through the data line DL is supplied to a gate electrode of the first thin film transistor TR1connected to the display device710. The data voltage Vdata is charged to a storage capacitor C1formed between the gate electrode of the first thin film transistor TR1and a source electrode of the first thin film transistor TR1.

An amount of current supplied to the organic light emitting diode OLED corresponding to the display device710through the first thin film transistor TR1is controlled by the data voltage Vdata, whereby a grayscale of light emitted from the display device710may be controlled.

Referring toFIGS.8and9, the first thin film transistor TR1and the second thin film transistor TR2are disposed on a substrate110.

The substrate110may be a glass substrate, a curable or bendable thin film glass substrate, a plastic substrate, or a silicon wafer substrate. If using plastic for the substrate110, transparent plastic having flexibility, for example, polyimide may be used. If the substrate110is formed of polyimide, heat resistant polyimide capable of enduring a high temperature may be used in consideration of a high temperature deposition process on the substrate110.

Then, light shielding layers111and211may be disposed on the substrate110.

The light shielding layers111and211block the external light being incident from the outside, to thereby protect active layer130and the first and second thin film transistors TR1and TR2. The light shielding layers111and211may be made of a material having the light blocking characteristics or light reflection characteristics. The light shielding layers111and211may be disposed on at least a portion overlapping the thin film transistor.

In the configuration of the first thin film transistor TR1shown inFIGS.8and9, the light shielding layer111may contact the gate electrode G1through a contact hole. Thus, the light shielding layer111of the first thin film transistor TR1may function as a bottom gate electrode in the configuration of the first thin film transistor TR1.

A buffer layer120is disposed on the light shielding layer111and211and the substrate110.

The light shielding layer111of the first thin film transistor TR1may include at least one of aluminum-based metal materials such as aluminum (Al) or aluminum alloys, silver-based metal materials such as silver (Ag) or silver alloys, copper-based metal materials such as copper (Cu), copper alloys, molybdenum-based metal materials such as molybdenum (Mo), molybdenum alloys, chromium (Cr), tantalum (Ta), neodymium (Nd), and titanium (Ti). The light shielding layer111may have a multi-layered structure including at least two conductive layers having the different physical properties.

Each light shielding layer111and211may include a first light shielding layer251, and a second light shielding layer252on the first light shielding layer251.

The buffer layer120may be formed in a multi-layered structure by depositing at least one of a silicon oxide (SiOx) film, silicon nitride (SiN) film, and a silicon oxynitride (SiON) film. Other components of the thin film transistor including the gate electrode150, which will be described later, may be disposed on the buffer layer120.

The active layer A1of the first thin film transistor TR1and the active layer A2of the second thin film transistor TR2are disposed on the buffer layer120.

A gate insulating film140is disposed on the active layer A1of the first thin film transistor TR1, the active layer A2of the second thin film transistor TR2and the buffer layer120and is disposed between the active layer A1of the first thin film transistor TR1and the gate electrode G1and between the active layer A2of the second thin film transistor TR2and the gate electrode G2, to thereby protect the active layer A1of the first thin film transistor TR1and the active layer A2of the second thin film transistor TR2. The gate insulating film140may include a silicon nitride (SiNx) film or a silicon oxide (SiOx) film, but not limited thereto. The gate insulating film140may have a single-layered structure or a multi-layered structure.

A first capacitor electrode C11of a storage capacitor C1is disposed on the gate insulating film140. The first capacitor electrode C11may be connected to the first gate electrode G1of the first thin film transistor TR1. The first capacitor electrode C11may be integrated into the first gate electrode G1of the first thin film transistor TR1as one body.

The thin film transistor according to the aspect of the present disclosure may further include a hydrogen blocking layer HBL. As shown inFIGS.8and9, the hydrogen blocking layer HBL may be configured to be adjacent to the active layer A1of the first thin film transistor TR1. The hydrogen blocking layer HBL may be disposed on the gate insulating film140. Although not shown, the hydrogen blocking layer HBL may include a first hydrogen blocking layer, and a second hydrogen blocking layer on the first hydrogen blocking layer.

The hydrogen blocking layer HBL may have the same composition as that of the gate electrode G1and G2. The hydrogen blocking layer HBL may be formed of the same material as that of the gate electrode G1and G2, and may have the same stacked structure as that of the gate electrode G1and G2.

The gate electrode G1of the first thin film transistor TR1and the gate electrode G2of the second thin film transistor TR2are disposed on the gate insulating film140. The gate electrode G1of the first thin film transistor TR1and the gate electrode G2of the second thin film transistor TR2overlap the channel portions of the active layers Al and A2, respectively. The gate electrode G1of the first thin film transistor TR1and the gate electrode G2of the second thin film transistor TR2may be the same as the gate electrode150of the thin film transistor100illustrated inFIG.1.

The gate electrode G1of the first thin film transistor TR1and the gate electrode G2of the second thin film transistor TR2may include at least one of aluminum-based metal materials such as aluminum (A1), aluminum alloys, silver-based metal materials such as silver (Ag) or silver alloys, copper-based metal materials such as copper (Cu) or copper alloys, molybdenum-based metal materials such as molybdenum (Mo), molybdenum alloys, chromium (Cr), tantalum (Ta), neodymium (Nd), and titanium (Ti). The gate electrode G1of the first thin film transistor TR1and the gate electrode G2of the second thin film transistor TR2may have a multi-layered structure including at least two conductive layers having the different physical properties.

For example, each of the gate electrode G1of the first thin film transistor TR1and the gate electrode G2of the second thin film transistor TR2may include a first gate electrode151, and a second gate electrode152on the first gate electrode151.

An interlayer insulating film160is disposed on the gate electrode G1and G2and the gate insulating film140.

The interlayer insulating film160include a silicon oxide film SiOx or a silicon nitride film SiNx, and may protect the thin film transistor. In order to contact the active layer A1of the first thin film transistor TR1and the active layer A2of the second thin film transistor TR2to source and drain electrodes, respectively, a portion of the interlayer insulating film160corresponding to a contact hole may be removed. A source electrode S1and a drain electrode D1of the first thin film transistor TR1are disposed on the interlayer insulating film160, and a source electrode S2and a drain electrode D2of the second thin film transistor TR2are disposed on the interlayer insulating film160. A data line DL, a driving power line PL, and a second capacitor electrode C12of the storage capacitor C1may be disposed on the interlayer insulating film160.

A portion of the driving power line PL may extend and may be the drain electrode D1of the first thin film transistor TR1. The drain electrode D1of the first thin film transistor TR1is connected to the active layer A1through a first contact hole H1.

The first gate electrode G1of the first thin film transistor TR1and the light shielding layer111may be connected through a contact hole.

The source electrode S1of the first thin film transistor TR1is connected to the active layer A1through a second contact hole H2.

The source electrode S1of the first thin film transistor TR1and the second capacitor electrode C12are connected to each other. The source electrode S1of the first thin film transistor TR1and the second capacitor electrode C12may be integrally formed as one body.

A portion of the data line DL may extend and may be the source electrode S2of the second thin film transistor TR2. The source electrode S2of the second thin film transistor TR2may be connected to the active layer A2through a fifth contact hole H5.

The drain electrode D2of the second thin film transistor TR2may be connected to the active layer A2through a sixth contact hole H6, and may be connected to the first capacitor electrode C11through a fourth contact hole H4, and may be connected to the light shielding layer211through a seventh contact hole H7.

A planarization layer180is disposed on the source electrode S1and the first drain electrode D1of the first thin film transistor TR1, the source electrode S2and the second drain electrode D2of the second thin film transistor TR2, the data line DL, the driving power line PL, and the second capacitor electrode C12.

The planarization layer180is formed of an insulating layer and is configured to planarize upper portions of the first thin film transistor TR1and the second thin film transistor TR2, and to protect the first thin film transistor TR1and the second thin film transistor TR2.

A first pixel electrode711of the display device710is disposed on the planarization layer180. The first pixel electrode711contacts the second capacitor electrode C12through an eighth contact hole H8formed in the planarization layer180. As a result, the first pixel electrode711may be connected to the source electrode S1of the first thin film transistor TR1. The eighth contact hole H8connected to the first pixel electrode711formed in the planarization layer180may be formed in a non-opening portion of the display device710while being overlapping with a bank layer750.

The bank layer750is disposed at an edge of the first pixel electrode711. The bank layer750defines a light emission area of the display device710.

An organic light emitting layer712is disposed on the first pixel electrode711, and a second pixel electrode713is disposed on the organic light emitting layer712. Accordingly, the display device710is configured. The display device710shown inFIGS.8and9is an organic light emitting diode OLED. Accordingly, the display apparatus500according to another aspect of the present disclosure is an organic light emitting display apparatus.

FIG.10is a circuit diagram of any one pixel of a display apparatus according to another aspect of the present disclosure.

The pixel P of the display apparatus600shown inFIG.10includes an organic light emitting diode OLED corresponding to a display device710, and a pixel driver PDC for driving the display device710. The display device710is connected to the pixel driver PDC.

In the pixel P, there are signal lines DL, GL, PL, RL, and SCL to supply a signal to the pixel driver PDC.

A data voltage Vdata is supplied to a data line DL, a scan signal SS is supplied to a gate line GL, a driving voltage Vdd for driving the pixel is supplied to a driving power line PL, a reference voltage Vref is supplied to a reference line RL, and a sensing control signal SCS is supplied to a sensing control line SCL.

For example, the pixel driver PDC includes a second thin film transistor TR2(switching transistor) connected to the gate line GL and the data line DL, a first thin film transistor TR1(driving transistor) for controlling a level of current output to the display device710according to the data voltage Vdata transmitted through the second thin film transistor TR2, and a third thin film transistor TR3(reference transistor) for sensing the characteristics of the first thin film transistor TR1.

A storage capacitor C1is disposed between a gate electrode of the first thin film transistor TR1and the display device710.

The second thin film transistor TR2is turned on by the scan signal SS supplied to the gate line GL, and the turned-on second thin film transistor TR2transmits the data voltage Vdata supplied to the data line DL to the gate electrode of the first thin film transistor TR1.

The third thin film transistor TR3is connected to the reference line RL and a first node n1between the first thin film transistor TR1and the display device710, and is turned on or off by the sensing control signal SCS, and senses the characteristics of the first thin film transistor TR1corresponding to the driving transistor for a sensing period.

A second node n2connected to the gate electrode of the first thin film transistor TR1is connected to the second thin film transistor TR2. The storage capacitor C1is formed between the second node n2and the first node n1.

When the second thin film transistor TR2is turned on, the data voltage Vdata supplied through the data line DL is supplied to the gate electrode of the first thin film transistor TR1. The data voltage Vdata is charged to the first capacitor C1formed between the gate electrode and source electrode of the first thin film transistor TR1.

When the first thin film transistor TR1is turned on, the current is supplied to the display device710through the first thin film transistor TR1by the driving voltage Vdd for driving the pixel, whereby light is emitted from the display device710.

FIG.11is a circuit diagram of any one pixel of a display apparatus according to another aspect of the present disclosure.

The pixel P of the display apparatus700shown inFIG.11includes an organic light emitting diode OLED corresponding to a display device710, and a pixel driver PDC for driving the display device710. The display device710is connected to the pixel driver PDC.

The pixel driver PDC includes thin film transistors TR1, TR2, TR3, and TR4.

In the pixel P, there are signal lines DL, EL, GL, PL, SCL, and RL to supply a driving signal to the pixel driver PDC.

In comparison to the pixel P ofFIG.10, the pixel P ofFIG.11further includes an emission control line EL. An emission control signal EM is supplied to the emission control line EL.

Also, in comparison to the pixel driver PDC ofFIG.10, the pixel driver PDC ofFIG.11further includes a fourth thin film transistor TR4, which is a light emitting control transistor for controlling an emission time point of the first thin film transistor TR1.

A storage capacitor C1is disposed between a gate electrode of the first thin film transistor TR1and the display device710.

The second thin film transistor TR2is turned on by a scan signal SS supplied to a gate line GL, and transmits a data voltage Vdata supplied to a data line DL to the gate electrode of the first thin film transistor TR1.

The third thin film transistor TR3is connected to a reference line RL and is turned on or off by a sensing control signal SCS, and senses the characteristics of the first thin film transistor TR1corresponding to a driving transistor for a sensing period.

The fourth thin film transistor TR4transfers a driving voltage Vdd to the first thin film transistor TR1or blocks the driving voltage Vdd according to the emission control signal EM. When the fourth thin film transistor TR4is turned on, a current is supplied to the first thin film transistor TR1, whereby light is emitted from the display device710.

The pixel driver PDC according to another aspect of the present disclosure may be formed in various structures in addition to the above-described structures. For example, the pixel driver PDC may include five or more thin film transistors.

Accordingly, the thin film transistor according to one aspect of the present disclosure may improve the S-factor.

Also, in the thin film transistor according to one aspect of the present disclosure, the molybdenum Mo may be ion-implanted to the channel portion of the active layer for the process of forming the metal layer, and the molybdenum Mo ion-implanted to the channel portion of the active layer may function as the acceptor, whereby the carrier may be reduced in the active layer, and the S-factor may be improved, to thereby reduce the rate of change of the current to the voltage.

In addition, the thin film transistor according to one aspect of the present disclosure may minimize or prevent the hydrogen of the active layer from being conductive by the inorganic film positioned adjacent to the active layer.

It will be apparent to those skilled in the art that various substitutions, modifications, and variations are possible within the scope of the present disclosure without departing from the spirit and scope of the present disclosure. Therefore, the scope of the present disclosure is represented by the following claims, and all changes or modifications derived from the meaning, range and equivalent concept of the claims should be interpreted as being included in the scope of the present disclosure.