Transmission of probabilistically shaped amplitudes using partially anti-symmetric amplitude labels

A communication system in which a constellation employing partially anti-symmetric amplitude labels is used to transmit probabilistically shaped amplitudes such that said amplitudes are also used to determine the signs applied thereto for transmission. In an example embodiment, a data transmitter is configured to use a suitable logic function (e.g., an XOR function) to place the parity generated by an FEC code into a selected amplitude bit while using the partially anti-symmetric amplitude labels to avoid placing the parity into the sign bits of the transmitted constellation symbols. In some embodiments, the FEC code can be a low-density parity-check code. Some embodiments are compatible with layered FEC coding, e.g., employing an outer FEC code and an inner FEC code. In some embodiments, FEC coding may be optional. Some embodiments can advantageously be used in communication systems relying on DMT modulation, such as the systems providing DSL access over copper wiring.

BACKGROUND

Field

Various example embodiments relate to optical communication equipment and, more specifically but not exclusively, to methods and apparatus for transmitting and receiving communication signals using probabilistic signal shaping and optional forward error correction (FEC).

Description of the Related Art

Signal shaping can provide energy savings often referred to as the shaping gain. In a typical implementation of signal shaping, constellation symbols of relatively large energy are transmitted less frequently than constellation symbols of relatively small energy. For a linear communication channel, the shaping gain can theoretically approach 1.53 dB.

A representative systematic FEC code is used to convert an input bit sequence into an expanded bit sequence (FEC codeword) by appending to the input bit sequence a corresponding set of parity bits. Some well-performing FEC codes are low-density parity-check (LDPC) codes. LDPC codes are linear block codes that have parity check matrices with a relatively small number of nonzero elements in each row and column. An LDPC decoder may use soft information during decoding, which information can be generated by a soft information detector, e.g., relying on a soft-output algorithm, such as the Viterbi algorithm, the Bahl-Cocke-Jelinek-Raviv algorithm, or a belief-propagation algorithm.

Frequency-division multiplexing (FDM) is a method of transmitting data on multiple carrier frequencies that can be used in wireline, wireless, and optical communication channels. Different variants of FDM are used in various forms of wideband digital communications, digital television, audio broadcasting, digital subscriber line (DSL) or G.fast or G.mgfast Internet access, local area networks (LANs), home networks, 4G or 5G mobile-access networks, etc. Some variants of FDM, typically collectively referred to as discrete multi-tone (DMT) modulation, are used in wireline communication channels established over, e.g., plain old telephone service (POTS) copper wiring, coaxial cable, and/or power lines. Some FDM schemes use orthogonal frequency-division multiplexing (OFDM).

At least some communication systems can benefit from the use of various combinations and sub-combinations of signal shaping, forward error correction, and/or frequency-division multiplexing.

SUMMARY OF SOME SPECIFIC EMBODIMENTS

Disclosed herein are various embodiments of a communication system in which a constellation employing partially anti-symmetric amplitude labels is used to transmit probabilistically shaped amplitudes such that said amplitudes are also used to determine the signs applied thereto for transmission. In an example embodiment, a data transmitter is configured to use a suitable logic function (e.g., an XOR function) to place the parity generated by an FEC code into a selected amplitude bit while using the partially anti-symmetric amplitude labels to avoid placing the parity into the sign bits of the transmitted constellation symbols. In some embodiments, the FEC code can be a low-density parity-check code. Some embodiments are compatible with layered FEC coding, e.g., employing an outer FEC code and an inner FEC code. In some embodiments, FEC coding may be optional. Some embodiments can advantageously be used in communication systems relying on DMT modulation, such as the systems providing DSL or G.fast access over copper wiring.

Also disclosed are data receivers compatible with the disclosed data transmitters.

According to an example embodiment, provided is an apparatus comprising a data transmitter that comprises an electrical analog front end and a digital signal processor, the digital signal processor being configured to: redundancy-encode an input data stream to generate a constellation-symbol stream; and drive the analog front end to cause one or more modulated electrical carriers generated by the analog front end to carry constellation symbols of the constellation-symbol stream; and wherein the digital signal processor comprises: a demultiplexer configured to demultiplex the input data stream to generate a first sub-stream and a second sub-stream; a shaping encoder configured to generate a first encoded data stream and a second encoded data stream (by applying a shaping code to the first sub-stream; and a constellation mapper configured to: use the second encoded data stream to select constellation-symbol amplitudes for the constellation-symbol stream; and use the first encoded data stream and the second sub-stream to select at least some signs applied to the constellation-symbol amplitudes.

According to another example embodiment, provided is a apparatus comprising a data receiver that comprises an electrical analog front end and a digital signal processor, the digital signal processor being configured to process a stream of values representing one or more modulated carriers of a received electrical signal outputted by the electrical analog front end and corresponding to a stream of transmitted constellation symbols of a constellation, the digital signal processor being configured to redundancy-decode the stream of values to recover a source data stream redundancy-encoded in the stream of transmitted constellation symbols and carried by the one or more modulated electrical carriers; and wherein the digital signal processor comprises: a constellation demapper configured to generate a first data stream and a second data stream by mapping each of the stream of values onto the constellation, the first data stream carrying sign bits of binary labels of constellation symbols determined by the mapping, the second stream carrying amplitude bits of the binary labels of the constellation symbols determined by the mapping; and a shaping decoder configured to recover a first sub-stream of the source data stream by decoding a stream of bit-words generated using the first and second data streams, the decoding being performed using a shaping code.

DETAILED DESCRIPTION

Some embodiments disclosed herein may benefit from the use of one or more features disclosed in U.S. Pat. Nos. 10,091,046 and 10,200,231 and U.S. patent application Ser. No. 15/817,537, each of which is incorporated herein by reference in its entirety.

FIG. 1shows a block diagram of a DMT system100in which various embodiments can be practiced. System100comprises a distribution point unit (DPU)110and a plurality of customer-premise-equipment (CPE) units1501-150nconnected by way of subscriber lines1401-140nas indicated inFIG. 1. In some embodiments, DPU110may be located at a “central office” of the service provider (e.g., a telephone company). In some other embodiments, DPU110may be remotely deployed using one or more backhaul (e.g., optical) links to a location that is closer to subscriber premises than that of the central office, and the corresponding equipment can be physically placed in a street cabinet, on a pole, in the basement of a building, etc. CPE units1501-150nare typically located at different respective customer sites.

Each of subscriber lines1401-140ntypically comprises a respective “twisted-pair” cable configured to transmit signals corresponding to data services. In some embodiments, legacy signals, such as POTS or ISDN signals, may be frequency-multiplexed with a data-service signal transmitted over the twisted-pair cable. At DPU110, each of subscriber lines1401-140nis connected to a respective one of input/output (I/O) ports1381-138n. At the CPE side, each of subscriber lines1401-140nis similarly connected to a respective one of I/O ports1421-142n, each being an I/O port of a respective one of CPE units1501-150n.

In an example embodiment, DPU110comprises a plurality of transceivers (120i/130i), each internally connected to a respective one of I/O ports1381-138n, where i=1, 2, . . . , n. A transceiver (120i/130i) includes a respective transmitter120iand a respective receiver130i. A CPE unit150icomprises a transceiver (160i/170i) internally connected to I/O port142iof that CPE unit. A transceiver (160i/170i) includes a respective transmitter160iand a respective receiver170i. Transmitter160ican be functionally similar to transmitter120i. Receiver170ican be functionally similar to receiver130i. Example embodiments of transmitters120,160are described in more detail below in reference toFIGS. 2, 4, 7, 9, and 10. Example embodiments of receivers130,170are described in more detail below in reference toFIGS. 3, 6, 8, 11, and 12.

FIG. 2shows a block diagram of a transmitter200that can be used in system100(FIG. 1) according to an embodiment. Transmitter200comprises a digital signal processor (DSP)204, a digital-to-analog converter (DAC)230, and an analog front end (AFE)240. Different instances of transmitter200can be used to implement some or all of transmitters1201-120nand/or1601-160n(FIG. 1).

DSP204operates to carry out redundant data encoding and digital carrier multiplexing to generate a digital output signal222having encoded thereon an input data stream202. DAC230operates to convert digital signal222into an analog form to generate a corresponding analog electrical radio-frequency (RF) signal232. AFE240then converts signal232into a form suitable for transmission over a subscriber line140and applies a resulting modulated electrical signal242to a corresponding I/O port138or142.

In an example embodiment, DSP204comprises an electronic encoder210and an inverse fast-Fourier-transform (IFFT) module220. Electronic encoder210carries out redundant data encoding that includes, inter alia, probabilistic signal shaping, FEC encoding, and constellation and carrier mapping to generate constellation-symbol sequences2121-212K, each carrying constellation symbols intended for transmission using a different respective tone (carrier wave) of a different respective frequency. IFFT module220then uses an inverse Fourier transform, as known in the pertinent art, to perform digital carrier multiplexing, thereby converting sequences2121-212Kinto a corresponding time-domain digital signal222. Depending on the specific embodiment, the number K of tones used in transmitter200can be on the order of one hundred, one thousand, or even greater than one thousand.

Example embodiments of electronic encoder210are described in more detail below in reference toFIGS. 4, 7, 9, and 10.

AFE240can be a conventional transmitter AFE circuit. Example transmitter AFE circuits suitable for implementing AFE240are briefly reviewed, e.g., by N. Stojkovic in “ADSL Analog Front End,” AUTOMATIKA v. 47 (2006), no. 1-2, pp. 59-67, which is incorporated herein by reference in its entirety.

FIG. 3shows a block diagram of a receiver300that can be used in system100(FIG. 1) according to an embodiment. Receiver300comprises an AFE310, an analog-to-digital converter (ADC)320, and a DSP324. Different instances of receiver300can be used to implement some or all of receivers1301-130nand/or1701-170n(FIG. 1).

AFE310operates to convert a modulated electrical input signal302received through a corresponding I/O port138or142into a corresponding analog electrical RF signal312suitable for digitization in ADC320. The typical analog signal processing applied to input signal302in AFE310includes amplification and filtering. Example receiver AFE circuits suitable for implementing AFE310are briefly reviewed, e.g., in the above-cited paper by N. Stojkovic. In some embodiments, an AFE310and an AFE240belonging to the same transceiver or modem can share some circuit elements, such as a clocking system and an electrical hybrid.

ADC320operates to sample signal312at an appropriate sampling rate to generate a corresponding sequence322of digital samples (values).

In an example embodiment, DSP324comprises a fast-Fourier-transform (FFT) module330and an electronic decoder340. FFT module330uses a Fourier transform, as known in the pertinent art, to perform digital carrier de-multiplexing, thereby converting sequence322into the corresponding frequency-domain digital sequences3321-332K. Electronic decoder340then applies constellation and carrier demapping, error correction, and redundancy decoding to recover the data stream202encoded by the corresponding transmitter onto the output signal242that caused receiver300to receive input signal302(also seeFIG. 2). The recovered data stream202is then directed to external circuits by way of a digital output signal342.

Example embodiments of electronic decoder340are described in more detail below in reference toFIGS. 6, 8, 11, and 12.

ITU standardization has recently started working on the next-generation DSL standard, often referred-to as G.mgfast, as well as on the evolution of the G.hn standard for powerline communications. For both of these standards, new coding and modulation schemes are being considered. For example, for both standards, LDPC-coded modulation (LCM), also known as multi-layered coding, might be used as an FEC scheme capable of improving the performance compared to the current solutions.

Another modulation technique that can be used to further improve the performance is the “shaping” of the transmitted constellations, such as a quadrature amplitude modulation (QAM) constellation. For example, conventional communication systems use QAM constellations uniformly distributed on a square grid to transmit information. This distribution leads to a performance gap of at least 1.53 dB compared to the theoretical capacity for high signal-to-noise ratio (SNR) values. Probabilistic amplitude shaping (PAS) is a practical method that can be used to reduce or close this performance gap. For example, PAS can modify the probabilities with which constellation symbols are transmitted to have an approximately Gaussian-like distribution, such as an approximate Maxwell-Boltzmann distribution over the constellation grid. In comparison to other shaping schemes, PAS may be advantageous in that the amount of shaping can be tuned to match the capacity of a given channel, and that it can be combined with a suitable off-the-shelf LDPC code.

In the description that follows, we focus on the pulse-amplitude modulation (PAM) format. A 2m-PAM constellation has 2mdistinct constellation points distributed along a 1-dimensional line. Herein, we assume that the constellation points are arranged equidistantly with respect to each other and symmetrically around the origin (zero). Each of the constellation points can be labeled using an m-bit long unique binary label. The extension of the presented description to QAM-modulation is relatively straightforward. For example, two 2m-PAM symbols can be combined to construct a 22m-QAM symbol by modulating each of the two dimensions of the QAM symbol independently with a respective PAM symbol.

The different bits of the binary label can be assigned different respective “significance” in terms of the overall value of the binary label. For example, the assignment can be such that changing the value of a more significant bit from “1” to “0” leads, on average, to a constellation point that is farther away from the original constellation point compared to when the same is done for a less significant bit. Under this labeling scheme, the binary labels of different constellation points can be parsed into non-overlapping sets of least significant bits (LSBs) and most significant bits (MSBs) in a manner suitable for the encoding and mapping described herein below.

Some example embodiments disclosed herein may be viewed as being based on non-obvious modifications of certain encoders and/or decoders disclosed in the above-cited U.S. Pat. No. 10,091,046. More specifically, U.S. Pat. No. 10,091,046 discloses, inter alia, a PAS-LCM scheme, in which the (c−1) LSBs of the binary label are encoded together with the sign bit by an LDPC code, and the (m−c) MSBs (excluding the sign bit) of the binary label remain uncoded by the LDPC code. All parity bits generated by the LDPC code are placed in (a fraction of) the sign bits.

One feature of this PAS-LCM scheme is that the sign bits are protected by the LDPC code. However, relatively often, the sign bits do not need such protection, e.g., because they tend to be the most reliable bits of the transmitted binary label. In some situations, the latter characteristic may result in some loss in performance compared to that of a legacy LCM scheme.

An example embodiment disclosed herein below can address the above-indicated and possibly other related problems in the state of the art by (i) placing a parity-bit value into a selected LSB position of a PAS-encoded label to replace the original bit value therein and (ii) generating the sign-bit value by applying a suitable logic function (e.g., an XOR function) to said original bit value and said parity bit value. As a result, the above-indicated possible loss in performance can beneficially be mitigated or avoided altogether. Other possible performance benefits of example embodiments are described below in reference toFIG. 13.

FIG. 4shows a block diagram of a digital circuit400that can be used in transmitter200(FIG. 2) according to an embodiment. More specifically, circuit400can be a part of electronic encoder210and is configured to convert an input data stream402into an output stream452of constellation symbols, wherein constellation symbols of different amplitudes have different respective rates of occurrence due to the encoding applied by a shaping encoder410. In some embodiments, electronic encoder210may include two or more instances (nominal copies) of circuit400connected in parallel with one another.

Input data stream402may be configured to carry data transfer units (DTUs) or frames, each of which is a structured data block intended for transmission and, if necessary, retransmission as a whole unit. A typical DTU includes a DTU header, a payload portion, and a cyclic-redundancy-check (CRC) portion. In some embodiments, data stream402may not carry an entire DTU. For example, if multiple parallel circuits400are used, then each circuit400may be configured to process a respective part of a DTU, with different parts of the same DTU being processed by different respective instances of circuit400. A person of ordinary skill in the art will readily understand how to generate input data stream402using input data stream202(FIG. 2).

Output stream452is typically directed to a carrier mapper that operates to distribute the constellation symbols received from one or more circuits400among constellation-symbol sequences2121-212K. As already indicated above, each of constellation-symbol sequences2121-212Kis transmitted using a different respective frequency component of modulated electrical signal242(seeFIG. 2).

Circuit400includes a demultiplexer (DMUX)404that partitions input data stream402to generate data streams406and408. Data stream406is applied to shaping encoder410. Copies of data stream408are applied to an LDPC encoder420and a multiplexer (MUX)440, as indicated inFIG. 4. The relative bit rates of data streams406and408are determined by the rates of the codes used in shaping encoder410and LDPC encoder420and by the size(s) of the constellation(s) used in a constellation mapper450.

In an example embodiment, shaping encoder410is configured to carry out fixed-in/fixed-out (FIFO) probabilistic signal shaping under which a fixed-size block of input data406is converted into a fixed-size set of bit-words of an output sequence412. Typically, the statistical properties of input data406are similar to those of a random or pseudo-random data sequence. However, different bit-word values in output sequence412have different respective rates of occurrence dictated by the shaping code used by shaping encoder410. In different embodiments, the shaping code can be configured to cause output sequence412to have any selected distribution of bit-word values. Some examples of such distributions include, but are not limited to an approximate exponential distribution, an approximate Gaussian distribution, and an approximate Maxwell-Boltzmann distribution. A person of ordinary skill in the art will understand that the shaping code achieves a desired distribution of bit-word values by redundancy-encoding input data406.

In some embodiments, shaping encoder410may be configured to perform the above-mentioned FIFO conversion in a “streaming” fashion such that the ratio between the number of bits supplied by input data406and the number of bit-words in the corresponding output sequence412remains constant and does not depend on the size or binary contents of input data406after the shaping encoder has executed the pertinent initialization procedures. This feature is different from the corresponding feature of some other probabilistic-signal-shaping schemes in which either the size of the input data block or the size of the output set of bit-words, or both, may depend on the binary contents of the input data block. Different variants of such probabilistic-signal-shaping schemes are often referred-to in the relevant literature as variable-in/fixed-out (VIFO), fixed-in/variable-out (FIVO), and variable-in/variable-out (VIVO) schemes.

In some embodiments, shaping encoder410may be configured to generate output sequence412using a VIFO shaping code.

A person of ordinary skill in the art will appreciate that the shaping code used in shaping encoder410and the constellation used in constellation mapper450are designed and configured to be compatible with one another. Some of the parameters that are taken into account to ensure this compatibility include, but are not limited to the use of the same modulation order m and of compatible binary labels for the shaped amplitudes and the corresponding constellation points. An example of such compatibility, for m=3, is described in more detail below in reference toFIGS. 5A-5B.

A bit-word parser414operates to parse each bit-word of sequence412into shorter bit-words. For example, if the bit-word length in sequence412is (m−1) bits, then the (m−1−c) MSBs of each bit word are used to form the corresponding bit-words for a parsed sequence416, and the remaining LSBs of each bit word are used to form parsed sequences417and418. More specifically, the most significant bit of said LSBs is directed into sequence417, and the remaining (c−1) LSBs are directed into sequence418. Here, m denotes the number of bits encoded in each constellation symbol of the constellation used in constellation mapper450.

LDPC encoder420uses copies of data stream408and sequence418to form blocks of bits, to which the LDPC encoder applies the operative LDPC code to generate the corresponding blocks of parity bits. The blocks of parity bits are serialized to form a data stream422.

MUX440multiplexes data streams408and422to generate a corresponding data stream442. A buffer4304operates to appropriately align in time the data streams408and422prior to their application to MUX440. Two copies of data stream442are applied to an XOR gate432and constellation mapper450, respectively. XOR gate432also receives sequence417. A buffer4301operates to appropriately align in time the sequence417and data stream442prior to their application to XOR gate432. XOR gate432applies an XOR operation to each pair of bits from sequence417and data stream442, respectively, thereby generating an output data stream436, which is then directed to constellation mapper450. Constellation mapper450also receives sequences416and418, which are appropriately buffered in buffers4302and4303, respectively, to time-align them with other inputs (e.g.,436,442) received by the constellation mapper.

The above-indicated time alignments are performed, e.g., to account for different processing delays in different signal-processing paths between DMUX404and constellation mapper450. A person of ordinary skill in the art will understand that the majority of these delays are typically caused by the processing performed in shaping encoder410and LDPC encoder420.

Constellation mapper450uses the operative2m-PAM constellation to convert sequences416and418and data streams436and442into output stream452, wherein each constellation symbol encodes m bits. Shown inFIG. 4is an input interface448of constellation mapper450that pictorially indicates how a bit-word that is being mapped therein is constructed from the various inputs received by the constellation mapper. As shown, each bit-word has m bits denoted as follows:
(su1u2. . . uNuL′l1l2. . . lNl)  (3)
where s denotes the sign bit of the bit-word; u1, u2, . . . , uNudenote the NuMSBs of the bit-word (excluding the sign bit); L′, l1, l2, . . . , lNldenote the (Nl+1) LSBs of the bit-word; and L′ denotes the most significant bit of the (Nl+1) LSBs. The sign bit s is provided by the corresponding bit of data stream436. The bit-word (u1, u2, . . . , uNu) is provided by the corresponding bits of sequence416. The bit L′ is provided by the corresponding bit of data stream442. The bit-word (11, l2, . . . , lNl) is provided by the corresponding bits of sequence418.

Comparison of Eqs. (1) and (3) reveals the bit-word transformation performed by the circuitry located between parser414and constellation mapper450. More specifically, the unsigned amplitude label (u1u2. . . uNuL′ l1l2. . . lNl) of the bit-word shown in Eq. (3) is obtained by replacing the bit L of the unsigned amplitude label (u1u2. . . uNuL l1l2. . . lNl) of Eq. (1) by a respective bit L′ from stream442. The latter bit can be either a parity bit generated by LDPC encoder420or an information bit from data stream408. The sign bit s for the unsigned amplitude label is generated in accordance with Eq. (4):
s=LXORL′(4)
The signed amplitude label (s u1u2. . . uNuL′ l1l2. . . lNl) for constellation mapper450is then generated by pre-pending the signed bit s to the unsigned amplitude label (u1u2. . . uNuL′ l1l2. . . lNl).

In some embodiments, circuit400may be configured to fill the L′ bits using only parity bits422(for instance, if there is generated a proper sufficient number of such parity bits). In such embodiments, buffer4304and MUX440can be removed, and parity stream422can be used instead of data stream442. A person of ordinary skill in the art will understand that the number of parity bits generated by LDPC encoder420for stream422depends, inter alia, on the rate of the LDPC code used therein and the number Nl.

In some embodiments, the number Nucan be zero (i.e., Nu=0). In such embodiments, buffer4302can be removed, and sequence416may not be generated by bit-word parser414and may not be used by constellation mapper450.

In some embodiments, the number Nlcan be zero (i.e., Nl=0). In such embodiments, buffer4303can be removed, and sequence418may not be generated by bit-word parser414and may not be used by LDPC encoder420and constellation mapper450.

FIGS. 5A-5Bshow example labeling schemes that can be used in circuit400according to an embodiment. More specifically,FIG. 5Ashows a 2m-PAM constellation500used in constellation mapper450, with the corresponding binary labels shown next to each constellation point.FIG. 5Billustrates the relationship between the amplitude labels used in shaping encoder410and in constellation500. In this example, m=3; Nu=0; and Nl=1.

Referring toFIG. 5A, each binary label in constellation500is a three-bit bit-word. According to Eq. (3), the corresponding bit-word format is as follows:
(s L′l1)  (5)
Inspection of the binary labels in constellation500reveals that the values of the bit L′ are anti-symmetric with respect to the origin. In contrast, the values of the bit l1are symmetric with respect to the origin. As conventional, the values of the sign bit s are anti-symmetric with respect to the origin. A person of ordinary skill in the art will appreciate that these symmetries of the individual bits of the binary labels in constellation500can be used to implement an optimal LCM configuration.

A 2m-PAM constellation500′ shown inFIG. 5Bis the constellation used in shaping encoder410. According to Eq. (1), the unsigned amplitude labels in constellation500′ have the following format:
(Ll1)  (6)
Inspection of the binary labels in constellation500′ reveals that the values of the bit L are symmetric with respect to the origin. The values of the bit l1are also symmetric with respect to the origin and are the same as in constellation500(FIG. 5A). A person of ordinary skill in the art will appreciate that these symmetries of the individual bits of the binary labels in constellation500′ are typical for PAS encoding, wherein the corresponding mapping is implicitly symmetric around the origin, e.g., because no sign bits are generated by a PAS (shaping) encoder.

Note the difference in the symmetries of the two LSBs of the binary labels in constellations500and500′, as indicated inFIGS. 5A and 5B.

In effect, XOR gate432is used in circuit400to convert the labeling of constellation500′ into the labeling of constellation500, thereby making it optimal for the LCM encoding implemented therein. The two bit strings shown inFIG. 5Bbelow constellation500′ can be used to easily verify that such conversion indeed takes place. The first of those two bit strings shows the values of the bit L′ for each constellation point. These values are the same as inFIG. 5A(also see Eq. (5)). The second of those two bit strings shows the values of (s XOR L′) for each constellation point (again, see Eq. (5)). It is evident that the values in said second string are the same as the values of the bit L in constellation500′ (also see Eq. (6)), i.e., L=s XOR L′. It can easily be verified that the latter can equivalently be expressed as s=L XOR L′, which gives the explicit formula for the sign bit s.

FIG. 6shows a block diagram of a digital circuit600that can be used in receiver300(FIG. 3) according to an embodiment. More specifically, circuit600can be a part of electronic decoder340. In some embodiments, electronic decoder340may include two or more instances (nominal copies) of circuit600connected in parallel with one another.

Circuit600operates to recover data stream402(also seeFIG. 4) in response to receiving a corresponding input stream602of digital samples (values) from a carrier demapper of electronic decoder340. In an example embodiment, the carrier demapper generates input stream602by appropriately transferring thereto digital samples from one or more sequences3321-332Kgenerated by FFT module330of the corresponding receiver300, e.g., as described above in reference toFIG. 3.

Circuit600includes a soft information detector610configured to calculate log-likelihood ratios (LLRs) corresponding to the bits encoded by LDPC encoder420. This calculation can be performed as known in the pertinent art, e.g., using prior information608of the corresponding amplitude distributions. The LLRs corresponding to the L′ bits are directed to an LDPC decoder630by way of an LLR stream612. The LLRs corresponding to the encoded LSBs (11, l2, . . . , lNl) are similarly directed to LDPC decoder630by way of an LLR stream614.

LDPC decoder630operates to process the LLRs provided by LLR streams612and614to recover the corresponding codewords of the LDPC code used by LDPC encoder420. The bits representing the L′ bits are then extracted from each recovered LDPC codeword to reconstruct data stream442. The bits representing the encoded LSBs (l1, l2, . . . , lNl) are also extracted from each recovered LDPC codeword to reconstruct sequence418(also seeFIG. 4).

A bit puncher640operates to discard (punch out) from data stream442the bits corresponding to parity bit stream422, thereby reconstructing data stream408.

A constellation demapper650uses a delayed copy of input stream602and copies of data stream442and sequence418to reconstruct sequence416and data stream436(also seeFIG. 4). In some embodiments, the demapping performed by constellation demapper650may rely on some or all of prior information608. A buffer620is configured to delay input stream602to account for the processing delay introduced by soft information detector610and LDPC decoder630such that, in each time slot, the bits provided to constellation demapper650by data stream442and sequence418originate from the digital sample provided by input stream602.

In an example embodiment, constellation demapper650can be configured to implement an LCM demapping procedure described in the above-cited U.S. Pat. No. 10,091,046.

An XOR gate632applies an XOR operation to each pair of bits received by way of sequence418and data stream442, respectively, thereby recovering sequence417.

A concatenator660uses the recovered sequences416,417, and418to reconstruct sequence412. A person of ordinary skill in the art will understand that the operation performed by concatenator660is inverse to the operation performed by parser414(FIG. 4). The latter fact is also apparent from comparison of interfaces415(FIG. 4) and659(FIG. 6).

A shaping decoder670operates, using the same shaping code used in shaping encoder410, to convert bit-word sequence412back into data stream406.

A MUX680operates to properly multiplex the recovered data streams406and408to recover data stream402. A person of ordinary skill in the art will understand that the operation performed by MUX680is inverse to the operation performed by DMUX404(FIG. 4).

It should be noted that, due to the XOR-ing in a (receiver) circuit600of the decoded L′ and s bits to obtain the L bits, errors from the LDPC-protected L′ bits might propagate to the L bits. This implies that errors in the LDPC parity bits (422,FIG. 4; carried by the L′ bits) will lead to errors in the decoded L bit values, and thus to errors in the decoded unsigned amplitude values. The latter errors will further lead to decoding errors in shaping decoder670. This error-propagation behavior (wherein errors in the LDPC parity propagate to the amplitudes) is a distinct characteristic of the coding scheme implemented using circuits400and600. For example, such error propagation does not happen in “pure” LCM (without shaping) or in a PAS-LCM scheme in which parity is placed in the sign bits, e.g., because, in the latter two schemes, the parity is simply discarded after the hard demapping.

Many LDPC codes that are used in practice offer less protection for the parity bits, as their structure is typically such that the average degree of the parity bits is lower than the average degree of the information bits (which are encoded). As used herein, the term “degree of a bit” refers to the number of constraints the bit is subjected to by the LDPC code. As a consequence, at a low codeword error rate, erroneous received codewords may have errors only in parity bits. Such erroneous codewords may not lead to decoding errors in some conventional coding schemes, as the erroneous parity bits are simply discarded. However, in the coding scheme implemented using circuits400and600, such erroneous codewords may lead to error propagation to the amplitude bits (e.g., to the L bit).

Fortunately, such error propagation can be prevented in circuit600in a relatively straightforward manner, e.g., by configuring LDPC decoder630to apply an additional post-processing step, in which the decoded information bits are re-encoded using the operative LDPC code. The parity generated in this manner, rather than the decoded parity, may then be outputted by LDPC decoder630together with the decoded information bits to prevent the above-indicated error propagation. This post-processing step is optional and does not need to be used in all embodiments or applied to generate all parity bits. This post-processing step can also be used to generate only a part of the parity bits (e.g., the parity bits with a degree below a certain threshold).

In an alternative embodiment, this post-processing step can be implemented using a separate dedicated circuit component (not explicitly shown inFIG. 6). Said dedicated circuit component may be inserted, e.g., upstream from XOR gate632.

FIG. 7shows a block diagram of a digital circuit700that can be used in transmitter200(FIG. 2) according to another embodiment. Circuit700is a modification of circuit400(FIG. 4) in which an additional (outer) layer of FEC coding is used to protect sequences416,417, and418and data stream408, or a subset thereof. In the example shown inFIG. 7, the outer layer of FEC coding is implemented using a Reed-Solomon (RS) code. A person of ordinary skill in the art will understand that other implementations of the outer layer of FEC coding may use other suitable FEC codes.

The additional circuitry incorporated into circuit700(as compared with circuit400,FIG. 4) includes an RS encoder720, buffers4305and4306, and a MUX740. RS encoder720operates to generate a parity bit stream722by applying the operative RS code to blocks of bits formed using copies of sequences416,417, and418and data stream408(or a subset thereof). Bit stream722and data stream408are then multiplexed using MUX740to generate a corresponding data stream742. A copy of data stream742is applied to LDPC encoder420instead of the copy of data stream408(seeFIG. 4). The time delays imposed by buffers4301-4306are appropriately selected to account for different processing delays in different signal-processing paths between DMUX404and constellation mapper450.

In an example implementation, the code rate of the RS code used in RS encoder720can be higher than the code rate of the LDPC code used in LDPC encoder420. The same RS code can advantageously be used at the corresponding receiver (see, e.g.,FIG. 8) to correct errors (if any) in the decoded sequences416,417, and418and data stream408. These errors can be caused, e.g., by the non-stationary noise induced by narrowband RF interference on some tones.

FIG. 8shows a block diagram of a digital circuit800that can be used in receiver300(FIG. 3) according to an alternative embodiment. More specifically, circuit800is a modification of circuit600(FIG. 6), with the modifications being directed at making the decoding processing implemented in circuit800compatible with the encoding processing implemented in circuit700(FIG. 7).

The additional circuitry incorporated into circuit800(as compared with circuit600,FIG. 6) includes an RS decoder830and a bit puncher840. The inputs to RS decoder830are labeled using the “primed” reference numerals to indicate that the corresponding data sequences/streams may have errors in them, which errors can be corrected by the RS decoder. Bit puncher840operates to discard from the recovered data stream742the bits corresponding parity bit stream722, thereby reconstructing data stream408.

A person of ordinary skill in the art will understand, without any undue experimentation, how to modify circuit800to make it compatible with any one of the above-indicated alternative embodiments of circuit700.

FIG. 9shows a block diagram of a digital circuit900that can be used in transmitter200(FIG. 2) according to yet another embodiment. Circuit900is another modification of circuit400(FIG. 4) in which some LSBs of the transmitted constellation symbols are left unshaped by (e.g., are not generated using) shaping encoder410.

The additional circuitry incorporated into circuit900(as compared with circuit400,FIG. 4) includes a 3-way DMUX902, a buffer4305, a DMUX904, and a MUX940. The 3-way DMUX902replaces DMUX404(seeFIG. 4) and is configured to generate data streams406,408, and908by demultiplexing input data stream402. LDPC decoder420is modified to generate parity bit stream422based on three inputs instead of two, the additional input being a copy of data stream908. Constellation mapper450has a modified input interface948that enables generation of input bit-words based on five inputs instead of four, the additional input being a data stream918(also seeFIG. 4). As shown, each bit-word formed by input interface948has the following structure:
(su1u2. . . uNuL′l1l2. . . lNllNl+1lNl+2. . .1Nl+q)  (7)
where s denotes the sign bit of the bit-word; u1, u2, . . . , uNudenote the NuMSBs of the bit-word (excluding the sign bit); L′, l1, l2, . . . , lNl, . . . , lNl+qdenote the (Nl+1+q) LSBs of the bit-word; L′ denotes the most significant bit of the (Nl+1+q) LSBs; and q is a positive integer; and the numbers q, Nuand Nlare positive integers that satisfy Eq. (8):
Nu+Nl+q+2=m(8)
The sign bit s is provided by the corresponding bit of data stream436. The bit-word (u1, u2, . . . , uNu) is provided by the corresponding bits of sequence416. The bit L′ is provided by the corresponding bit of data stream442. The bit-word (11, l2, . . . , lNl) is provided by the corresponding bits of sequence418. The bit-word (1Nl+1lNl+2. . . lNl+q) is provided by the corresponding bits of data stream918.

DMUX904is configured to branch off a portion910of parity data stream422. The remaining portion906of parity data stream422is channeled by DMUX904, by way of MUX440, into data stream442. MUX940is configured to generate data stream918by multiplexing data streams908and910.

The time delays imposed by buffers4301-4305are appropriately selected to account for different processing delays in different signal-processing paths between DMUX902and constellation mapper450.

In this embodiment, the bits (lNl+1lNl+2. . . lNl+q) of each binary label of the operative constellation are not shaped by shaping encoder410, but are nevertheless protected by the operative LDPC code used in LDPC encoder420.

In some embodiments, circuit900can be modified such that LDPC encoder420is removed, and the parity bit stream422is neither generated nor transmitted. In such embodiments, data stream408is used instead of data stream442, and data stream908is used instead of data stream918(e.g., seeFIG. 10).

In some embodiments, the numbers Nland q can be set to Nl=0 and q=1. In such embodiments, DMUX904an MUX940can be removed.

FIG. 10explicitly shows a block diagram of digital circuit900according to an alternative embodiment, in which LDPC encoder420is absent (as indicated in the preceding paragraph). An important characteristic of this particular embodiment is the realization of anti-symmetric labeling (explained in reference toFIGS. 5A-5B) for the transmission of at least one of the shaped amplitude bits (e.g., L) without affecting the symmetric labeling inherent to the PAS coding (e.g., see500′,FIG. 5A). This particular embodiment of digital circuit900also demonstrates that placing parity into such anti-symmetric amplitude bits (e.g., L′) can be optional, as FEC parity is not being generated therein.

FIG. 11shows a block diagram of a digital circuit1100that can be used in receiver300(FIG. 3) according to yet another embodiment. More specifically, circuit1100can be a part of electronic decoder340. Circuit1100is a modification of circuit600(FIG. 6), with the modifications being directed at making the decoding processing implemented in circuit1100compatible with the encoding processing implemented in circuit900(FIG. 9).

The additional circuitry incorporated into circuit1100(as compared with circuit600,FIG. 6) includes a bit puncher1140. A three-input MUX1180replaces MUX680(seeFIG. 6). Soft detector610is modified to generate an additional LLR stream, which is labeled1102, said additional LLR stream carrying the LLRs corresponding to the LSBs (lNl+1lNl+2. . . lNl+q). LDPC decoder630is modified to additionally output data stream918(also seeFIG. 9). Constellation demapper is modified to recover sequences416,417, and418based on data streams418,918, and442received from LDPC decoder630. Bit puncher1140operates to discard from said data stream918the bits corresponding to bit stream910, thereby reconstructing data stream908(also seeFIG. 9). MUX1180operates to properly multiplex the received data streams406,908, and408to recover data stream402. A person of ordinary skill in the art will understand that the operation performed by MUX1180is inverse to the operation performed by DMUX902(FIG. 9).

FIG. 12shows a block diagram of a digital circuit1200that can be used in receiver300(FIG. 3) according to yet another embodiment. More specifically, circuit1200can be a part of electronic decoder340and is configured to perform the decoding processing that is compatible with the encoding processing implemented in the embodiment of circuit900shown inFIG. 10.

Circuit1200comprises a constellation demapper1250that maps digital samples of input stream602onto the operative constellation to determine the corresponding binary label. An output interface1248then appropriately parses the determined binary labels to recover data streams/sequences436,416,408,418, and908. XOR gate632recovers sequence417by applying an XOR operation to each pair of bits provided by data streams436and408. Concatenator660then reconstructs sequence412using sequences416,417, and418. Shaping decoder670operates to convert bit-word sequence412back into data stream406.

The time delays imposed by buffers620are appropriately selected to account for different processing delays in different signal-processing paths between constellation demapper1250and a MUX1280. MUX1180operates to multiplex the received data streams406,908, and408to recover data stream402.

FIG. 13graphically compares certain performance characteristics of several LCM schemes. To obtain the shown performance data, we used, for all of these schemes, a 12000-bit long LDPC code with a code rate 3/4, i.e., a code that generates one parity bit for every three information bits. The simulated block error rates of the different schemes are shown as a function of the SNR gap to capacity, which is defined as:
SNR gap to capacity [dB]=SNR[dB]−10 log10(2b_eff−1)  (9)
where b_eff is the effective amount of information that is being transmitted (i.e., with the coding and shaping overhead subtracted). The SNR gap to capacity allows comparing different schemes that transmit different respective amounts of effective information b_eff.

Curve1302graphically shows the simulated block error rate (for a block of 15000 bits) of the disclosed LSB-only LCM-PAS scheme with four coded bits per 28-QAM symbol (i.e., with two coded bits per 16-PAM symbol). The corresponding encoding at the transmitter can be performed, e.g., using circuit400(FIG. 4).

An LCM scheme without shaping and with four coded bits (curve1306) leads to a gap to capacity of about 2.77 dB at a block error rate of 10−4, which is a typical operating point for DSL. By applying the shaping encoding based on the LCM-PAS with six coded bits (curve1304), one can reduce the gap to about 2.1 dB (a gain of about 0.67 dB). The gain is limited compared to the potential shaping gain of 1.53 dB, because of the higher number of coded bits (i.e., six instead of four). For all practical purposes, one cannot use the LCM-PAS scheme with only four coded bits (curve1308), because then the uncoded bits do not have sufficient protection, leading to an unacceptably high block error rate. In contrast, with the LSB-only LCM-PAS scheme represented by curve1302, one can use four coded bits while still being able to obtain sufficient protection for the uncoded bits, leading to a gap to capacity of ˜1.58 dB, which is a shaping gain of ˜1.19 dB.

A possible benefit of the disclosed LSB s-only PAS-LCM technique is that one can apply the LDPC code to the lowest LSBs only, which are the bits that need the protection the most (because they are the least reliable). In contrast, under the comparable PAS-LCM technique, the corresponding encoder is also configured to protect sign bits, even though the sign bits are the most reliable (and hence may not need the protection). As a consequence, the LSB s-only scheme can be more efficient in terms of the information throughput and complexity, with the corresponding improvements being indicated by the relative position of curve1302. Note that some embodiments may be applied not only to LCM but to any suitable layered coded modulation scheme. For example, it can be used with Trellis-coded modulation, such as that used in legacy DSL.

Note also that some embodiments can be used in multi-carrier communication, such as DSL, in which the FEC codewords run over different tones that can possibly use different shaping codes and/or different modulation orders.

According to an example embodiment disclosed above, e.g., in the summary section and/or in reference to any one or any combination of some or all ofFIGS. 1-13, provided is an apparatus comprising a data transmitter (e.g.,200,FIG. 2) that comprises an electrical analog front (e.g.,240,FIG. 2) end and a digital signal processor (e.g.,204,FIG. 2), the digital signal processor being configured to: redundancy-encode an input data stream (e.g.,202,FIG. 2;402,FIGS. 4, 7, 9, 10) to generate a constellation-symbol stream (e.g.,452,FIGS. 4, 7, 9, 10); and drive the analog front end to cause one or more modulated electrical carriers generated by the analog front end to carry constellation symbols of the constellation-symbol stream; and wherein the digital signal processor comprises: a demultiplexer (e.g.,404,FIGS. 4, 7;902,FIGS. 9, 10) configured to demultiplex the input data stream to generate a first sub-stream (e.g.,406,FIGS. 4, 7, 9, 10) and a second sub-stream (e.g.,408,FIGS. 4, 7, 9, 10;908,FIGS. 9, 10); a shaping encoder (e.g.,410,FIGS. 4, 7, 9, 10) configured to generate a first encoded data stream (e.g.,417,FIGS. 4, 7, 9, 10) and a second encoded data stream (e.g.,416,FIGS. 4, 7, 9, 10) by applying a shaping code to the first sub-stream; and a constellation mapper (e.g.,450,FIGS. 4, 7, 9, 10) configured to: use the second encoded data stream to select constellation-symbol amplitudes for the constellation-symbol stream; and use the first encoded data stream and the second sub-stream to select at least some signs (e.g., s,FIGS. 4, 7, 9, 10) applied to the constellation-symbol amplitudes.

In some embodiments of the above apparatus, the digital signal processor further comprises a logic gate (e.g.,432,FIGS. 4, 7, 9, 10) having first and second inputs and an output, the first input being connected to receive the first encoded data stream, the second input being connected to receive a data stream (e.g.,408,FIG. 10;442,FIGS. 4, 7, 9) corresponding to the second sub-stream, the output being connected to the constellation mapper; and wherein the constellation mapper is configured to use bit values (e.g.,436,FIGS. 4, 7, 9, 10) received from the output to select the signs applied to the constellation-symbol amplitudes.

In some embodiments of any of the above apparatus, the logic gate comprises an XOR gate (e.g.,432,FIGS. 4, 7, 9, 10).

In some embodiments of any of the above apparatus, the apparatus further comprises an FEC encoder (e.g.,420,FIGS. 4, 7, 9) configured to generate a third encoded data stream (e.g.,422,FIGS. 4, 7, 9) by applying an FEC code to the second sub-stream; and wherein the constellation mapper is further configured to use the third encoded data stream (e.g., by way of442,FIGS. 4, 7, 9; and/or918,FIG. 9) to select the constellation-symbol amplitudes for the constellation-symbol stream.

In some embodiments of any of the above apparatus, the FEC encoder (e.g.,420,FIGS. 4, 7, 9) is configured to use a low-density parity-check (LDPC) code.

In some embodiments of any of the above apparatus, the shaping encoder is further configured to generate a fourth encoded data stream (e.g.,418,FIGS. 4, 7, 9) by applying the shaping code to the first sub-stream; and wherein the FEC encoder is further configured to generate the third encoded data stream by also applying the FEC code to the fourth encoded data stream.

In some embodiments of any of the above apparatus, the demultiplexer is further configured to demultiplex the input data stream to generate a third sub-stream (e.g.,408or908,FIG. 9); and wherein the FEC encoder is further configured to generate the third encoded data stream by also applying the FEC code to the third sub-stream.

In some embodiments of any of the above apparatus, the constellation mapper is further configured to use the third encoded data stream (e.g., by way of442,FIGS. 4, 7, 9) to select at least some of the signs applied to the constellation-symbol amplitudes.

In some embodiments of any of the above apparatus, the apparatus further comprises an FEC encoder (e.g.,420,FIGS. 4, 7, 9) configured to generate a third encoded data stream (e.g.,422,FIGS. 4, 7, 9) by applying an FEC code to the second sub-stream; and wherein the constellation mapper is further configured to use the third encoded data stream (e.g., by way of442,FIGS. 4, 7, 9) to select at least some of the signs applied to the constellation-symbol amplitudes.

In some embodiments of any of the above apparatus, the constellation mapper is configured to select a constellation-symbol amplitude using a bit-word (e.g., (u1u2. . . uNuL′), Eq. (7)) having a fixed number (e.g., Nu,FIG. 10) of bits supplied by the second encoded data stream and a single bit (e.g., L′,FIG. 10) supplied by the second sub-stream.

In some embodiments of any of the above apparatus, the constellation mapper is configured to perform constellation mapping using a set of binary labels in which different binary labels correspond to different respective constellation symbols (e.g.,500,FIG. 5A), each binary label (e.g., (s L′ l1), Eq. (5)) including a respective sign portion (e.g., s, Eq. (5)) and a respective amplitude portion (e.g., (L′ l1), Eq. (5)); and wherein the amplitude portion is such that, for any pair of constellation symbols that are symmetric with respect to a constellation origin, respective values of a particular bit of the amplitude portion include a binary zero and a binary one (e.g., L′,FIG. 5A).

In some embodiments of any of the above apparatus, the digital signal processor further comprises a carrier mapper (e.g.,210,FIG. 2) configured to generate a plurality of constellation-symbol sub-streams (e.g.,212,FIG. 2) by partitioning the constellation-symbol stream; and wherein the digital signal processor is configured to drive the analog front end to cause a plurality of the modulated electrical carriers generated by the analog front end to carry the plurality of said constellation-symbol sub-streams.

In some embodiments of any of the above apparatus, the apparatus further comprises a modem (e.g.,150,FIG. 1), the modem including the data transmitter.

In some embodiments of any of the above apparatus, the apparatus further comprises a service distribution unit (e.g.,110,FIG. 1), the service distribution unit including the data transmitter.

According to another example embodiment disclosed above, e.g., in the summary section and/or in reference to any one or any combination of some or all ofFIGS. 1-13, provided is an apparatus comprising a data receiver (e.g.,300,FIG. 3) that comprises an electrical analog front end (e.g.,310,FIG. 3) and a digital signal processor (e.g.,324,FIG. 3), the digital signal processor being configured to process a stream of values (e.g.,602,FIG. 6) representing one or more modulated carriers of a received electrical signal outputted by the electrical analog front end and corresponding to a stream of transmitted constellation symbols of a constellation (e.g.,500,FIG. 5A), the digital signal processor being configured to redundancy-decode the stream of values to recover a source data stream (e.g.,402,FIG. 6) redundancy-encoded in the stream of transmitted constellation symbols and carried by the one or more modulated electrical carriers; and wherein the digital signal processor comprises: a constellation demapper (e.g.,650,FIG. 6;1250,FIG. 12) configured to generate a first data stream (e.g.,436,FIGS. 6, 12) and a second data stream (e.g.,416,FIGS. 6, 12) by mapping each of the stream of values onto the constellation, the first data stream carrying sign bits of binary labels of constellation symbols determined by the mapping, the second stream carrying amplitude bits of the binary labels of the constellation symbols determined by the mapping; and a shaping decoder (e.g.,670,FIG. 6) configured to recover a first sub-stream (e.g.,406,FIG. 6) of the source data stream by decoding a stream (e.g.,412,FIG. 6) of bit-words (e.g., (u1u2. . . uNuL l1l2. . . lNl), Eq. (1);659,FIG. 6) generated using the first and second data streams, the decoding being performed using a shaping code.

In some embodiments of the above apparatus, the digital signal processor further comprises a logic gate (e.g.,632,FIG. 6) having first and second inputs and an output, the first input being connected to receive the first data stream, the second input being connected to receive a third data stream (e.g.,442,FIG. 6;408,FIG. 12), the third data stream being generated based on the stream of values; and wherein the stream of bit-words includes bit values (e.g.,417,FIG. 6) generated at the output of the logic gate.

In some embodiments of any of the above apparatus, the logic gate comprises an XOR gate (e.g.,632,FIG. 6).

In some embodiments of any of the above apparatus, the apparatus further comprises an FEC decoder (e.g.,610/630,FIG. 6) configured to recover a second sub-stream (e.g.,408,FIG. 6) of the source data stream by applying an FEC code to decode the stream of values; and wherein the constellation demapper is further configured to use an output (e.g.,442,418,FIG. 6) of the FEC decoder to perform the mapping.

In some embodiments of any of the above apparatus, the FEC decoder (e.g.,630,FIG. 6) is configured to use a low-density parity-check (LDPC) code.

In some embodiments of any of the above apparatus, the FEC decoder is configured to: discard parity bits recovered by decoding the stream of values; regenerate the parity bits by re-encoding information bits recovered by decoding the stream of values; and direct the regenerated parity bits to the constellation demapper.

In some embodiments of any of the above apparatus, the digital signal processor further comprises a logic gate (e.g.,632,FIG. 6) having first and second inputs and an output, the first input being connected to receive the first data stream, the second input being connected to receive a third data stream (e.g.,442,FIG. 6), the third data stream being generated by the FEC decoder by decoding the stream of values; and wherein the stream of bit-words includes bit values (e.g.,417,FIG. 6) generated at the output of the logic gate.

In some embodiments of any of the above apparatus, the apparatus further comprises a modem (e.g.,150,FIG. 1), the modem including the data receiver.

In some embodiments of any of the above apparatus, the apparatus further comprises a service distribution unit (e.g.,110,FIG. 1), the service distribution unit including the data receiver.

While this disclosure includes references to illustrative embodiments, this specification is not intended to be construed in a limiting sense. Various modifications of the described embodiments, as well as other embodiments within the scope of the disclosure, which are apparent to persons skilled in the art to which the disclosure pertains are deemed to lie within the principle and scope of the disclosure, e.g., as expressed in the following claims.

Some embodiments may be implemented as circuit-based processes, including possible implementation on a single integrated circuit.

Some embodiments can be embodied in the form of methods and apparatuses for practicing those methods. Some embodiments can also be embodied in the form of program code recorded in tangible media, such as magnetic recording media, optical recording media, solid state memory, floppy diskettes, CD-ROMs, hard drives, or any other non-transitory machine-readable storage medium, wherein, when the program code is loaded into and executed by a machine, such as a computer, the machine becomes an apparatus for practicing the patented invention(s). Some embodiments can also be embodied in the form of program code, for example, stored in a non-transitory machine-readable storage medium including being loaded into and/or executed by a machine, wherein, when the program code is loaded into and executed by a machine, such as a computer or a processor, the machine becomes an apparatus for practicing the patented invention(s). When implemented on a general-purpose processor, the program code segments combine with the processor to provide a unique device that operates analogously to specific logic circuits.

It will be further understood that various changes in the details, materials, and arrangements of the parts which have been described and illustrated in order to explain the nature of this disclosure may be made by those skilled in the art without departing from the scope of the disclosure, e.g., as expressed in the following claims.

Unless otherwise specified herein, the use of the ordinal adjectives “first,” “second,” “third,” etc., to refer to an object of a plurality of like objects merely indicates that different instances of such like objects are being referred to, and is not intended to imply that the like objects so referred-to have to be in a corresponding order or sequence, either temporally, spatially, in ranking, or in any other manner.

A person of ordinary skill in the art would readily recognize that steps of various above-described methods can be performed by programmed computers. Herein, some embodiments are intended to cover program storage devices, e.g., digital data storage media, which are machine or computer readable and encode machine-executable or computer-executable programs of instructions where said instructions perform some or all of the steps of methods described herein. The program storage devices may be, e.g., digital memories, magnetic storage media such as a magnetic disks or tapes, hard drives, or optically readable digital data storage media. The embodiments are also intended to cover computers programmed to perform said steps of methods described herein.