Integrated circuit having capacitors for smoothing a supply voltage

The integrated circuit is provided with capacitors for smoothing the supply voltage. The capacitors are disposed below the supply interconnects which supply the integrated circuit with the supply voltage. This enables the integrated circuit to be accommodated on a minimal area.

BACKGROUND OF THE INVENTION 
1. Field of the Invention 
The invention pertains to an integrated circuit with capacitors for 
smoothing the supply voltage. 
Integrated circuits are known in a multiplicity of embodiments and require 
no further explanation. Smoothing the supply voltage of integrated 
circuits by means of capacitors proves to be advantageous because it 
enables the integrated circuits to operate free from interference, and it 
means that they have reduced electromagnetic emission. Integrating the 
capacitors provided for smoothing into the integrated circuit makes 
particularly effective smoothing possible. On the other hand, capacitors 
provided in integrated circuits require a relatively large area on the 
chip containing the integrated circuit, and integrated circuits containing 
capacitors are therefore relatively large and hence also expensive, 
susceptible to faults and cumbersome. 
2. Summary of the Invention 
It is accordingly an object of the invention to provide an integrated 
circuit, which overcomes the above-mentioned disadvantages of the 
heretofore-known devices and methods of this general type and which can be 
accommodated on an area that is as small as possible. 
With the foregoing and other objects in view there is provided, in 
accordance with the invention, an integrated circuit, comprising: 
supply interconnects disposed on a substrate body for supplying the 
integrated circuit with a supply voltage; and 
a plurality of capacitors for smoothing the supply voltage carried on the 
supply interconnects, the capacitors being disposed below the supply 
interconnects. 
In other words, the invention is characterized by the positioning of the 
capacitors below the supply interconnects which are used to supply the 
integrated circuit with the supply voltage. 
As the regions below the supply interconnects in conventional integrated 
circuits have not been used at all to date, integrating the capacitors 
makes the integrated circuit no larger, or at the outside minimally 
larger, than it would be without the capacitor integration. 
The integrated circuit according to the invention can therefore be 
accommodated on a minimal area. 
The proximity of the capacitors to the supply interconnects carrying the 
supply voltage which is to be smoothed makes it possible, furthermore, for 
the electrical connections, which are necessary in order to arrange the 
capacitors such that they act between the two terminals of the supply 
voltage, to be extremely short. This, of course, means that the integrated 
circuit is simple in construction, easy to manufacture, and reliable in 
operation. 
In accordance with an added feature of the invention, the supply 
interconnects comprise a VDD supply interconnect for a VDD potential, and 
a VSS supply interconnect for a VSS potential, whereby the supply 
interconnects form a constituent part of a metal layer of the integrated 
circuit. 
In accordance with an additional feature of the invention, the plurality of 
capacitors are one or more capacitors below each the VDD supply 
interconnect and the VSS supply interconnect. 
In accordance with another feature of the invention, the capacitors are 
either disposed essentially below the VDD supply interconnect or 
essentially below the VSS supply interconnect. 
In accordance with a further feature of the invention, a polysilicon layer 
is disposed on the substrate body. The capacitors below the VDD supply 
interconnect are formed by interacting poly sections in the polysilicon 
layer and p.sup.+ -regions below the poly sections in the substrate body. 
The capacitors below the VSS supply interconnect are formed by interacting 
poly sections in the polysilicon layer and n.sup.+ -regions below the poly 
sections in the substrate body. The poly sections of the capacitors below 
the VDD supply interconnect are electrically connected to the VSS supply 
interconnect, and the p.sup.+ -regions are multiply connected to the VDD 
supply interconnect. The poly sections of the capacitors below the VSS 
supply interconnect are electrically connected to the VDD supply 
interconnect, and the n.sup.+ -regions are multiply connected to the VSS 
supply interconnect. 
In accordance with again a further feature of the invention, the poly 
sections are strips with finger-like projections. The projections of the 
poly sections of the capacitors below the VDD supply interconnect extend 
to below the VSS supply interconnect, and the finger-like projections of 
the poly sections of the capacitors below the VSS supply interconnect 
extending to below the VDD supply interconnect. 
In accordance with a concomitant feature of the invention, the intermediate 
spaces formed between mutually adjacent poly sections are used for 
connecting the p.sup.+ -regions to the VDD supply interconnect and for 
connecting the n.sup.+ -regions to the VSS supply interconnect. 
Other features which are considered as characteristic for the invention are 
set forth in the appended claims. 
Although the invention is illustrated and described herein as embodied in 
an integrated circuit, it is nevertheless not intended to be limited to 
the details shown, since various modifications and structural changes may 
be made therein without departing from the spirit of the invention and 
within the scope and range of equivalents of the claims. 
The construction and method of operation of the invention, however, 
together with additional objects and advantages thereof will be best 
understood from the following description of specific embodiments when 
read in connection with the accompanying drawings.

DESCRIPTION OF THE PREFERRED EMBODIMENTS 
Referring now to the figures of the drawing in detail and first, 
particularly, to FIG. 1 thereof, it is pointed out that all sectional 
hatching has been omitted for reasons of clarity. 
The integrated circuit of the best mode preferred embodiment is a CMOS 
circuit which comprises a substrate S (for example made of silicon), a 
polysilicon layer (poly layer) P arranged at a distance above the latter, 
and a metal layer M1 arranged at a distance above the poly layer P. Other 
layers may be provided as well, for example a poly2 layer, a metal2 layer, 
and the like. The intermediate spaces between the individual layers are 
filled in with an insulating material (for example silicon oxide) which is 
not indicated in more detail in the figures. 
The illustrated structures of the metal layer M1 are a VDD supply 
interconnect 1 and a VSS supply interconnect 2 which are used to carry the 
supply voltage (the VDD potential and the VSS potential in the example) to 
those points at which it is needed. As the designations themselves 
indicate, the VDD potential is applied to the integrated circuit via the 
VDD supply interconnect 1, and the VSS potential is applied to the 
integrated circuit via the VSS supply interconnect 2. 
The VDD supply interconnect 1 and the VSS supply interconnect 2 are 
connected to one another via capacitors for smoothing the supply voltage. 
As will be described in more detail below, the smoothing capacitors are 
arranged below the VDD supply interconnect 1 and/or the VSS supply 
interconnect 2 and are formed by the interaction of the polysilicon layer 
P and the substrate S. 
As shown by the illustration in FIG. 1, two capacitors are provided. One 
capacitor is drawn below the VDD supply interconnect 1 and the other 
capacitor is drawn below the VSS supply interconnect 2. 
The capacitor located below the VDD supply interconnect 1 is formed by a 
poly section 11 formed in the polysilicon layer, a p.sup.+ -region 21 
provided below the poly section 11 in the substrate S or an n-well 20 in 
the latter, and the insulating material situated in between; the capacitor 
located below the VSS supply interconnect 2 is formed by a poly section 12 
formed in the polysilicon layer, an n.sup.+ -region 31 provided below said 
poly section 12 in the substrate S or a p-well 30 in the latter, and the 
insulating material situated in between. 
From the capacitor located below the VDD supply interconnect 1, the poly 
section 11 is connected to the VSS supply interconnect 2 via a 
plated-through hole 41, and the p.sup.+ -region 21 is connected to the VDD 
supply interconnect 1 via a plated-through hole 42. The capacitor located 
below the VDD supply interconnect is therefore disposed and connected so 
that it acts between the VDD supply interconnect 1 and the VSS supply 
interconnect 2. 
From the capacitor located below the VSS supply interconnect 2, the poly 
section 12 is connected to the VDD supply interconnect 1 via a 
plated-through hole 51, and the n.sup.+ -region 31 is connected to the VSS 
supply interconnect 2 via a plated-through hole 52; the capacitor located 
below the VSS supply interconnect 2 is therefore likewise arranged so that 
it acts between the VDD supply interconnect 1 and the VSS supply 
interconnect 2, the capacitor located below the VDD supply interconnect 1 
and the capacitor located below the VSS supply interconnect 2 thereby 
being arranged electrically in parallel with one another. 
A multiplicity of plated-through holes 42 should be provided between the 
p.sup.+ -region 21 and the VDD supply interconnect 1, and a multiplicity 
of plated-through holes 52 should be provided between the n.sup.+ -region 
31 and the VSS supply interconnect 2, particularly if the capacitors have 
a relatively large area. Consequently, the real parts of the capacitor 
impedances can be kept low, which is of great importance, particularly for 
the radio-frequency response of the capacitors. It proves to be 
particularly advantageous if the resistance of a respective capacitor is 
produced in approximately equal portions by the p.sup.+ -region 21 and the 
poly section 11 or by the n.sup.+ -region 31 and the poly section 12. 
An n.sup.+ -region 22 connected to the VDD supply interconnect 1 via a 
plated-through hole 43 is provided adjacent to the p.sup.+ -region 21 
and--if present--likewise also inside the n-well 20. Similarly, a p.sup.+ 
-region 32 connected to the VSS supply interconnect 2 via a plated-through 
hole 53 is provided adjacent to the n.sup.+ -region 31 and--if 
present--likewise also inside the p-well 30. The plated-through holes 43 
and 53 are so-called substrate contacts whose function and manner of 
operation are known and require no further explanation. However, in the 
exemplary embodiment, the substrate contacts are provided "only" for 
reliability reasons as a precaution against circumstances which do not 
normally occur and/or for standardizing the manufacture of the wells. No 
changes, at any rate no serious changes, in the function and manner of 
operation of the respective capacitors need be expected if the substrate 
contacts are omitted, i.e. the n.sup.+ -region 22 and the plated-through 
hole 43 as well as the p.sup.+ -region 32 and the plated-through hole 53. 
As mentioned above, the illustration of the structure and arrangement of 
the capacitors in FIG. 1 is highly schematic. One possible practical 
implementation of such a configuration will now be explained with 
reference to FIG. 2. 
Mutually corresponding elements in FIGS. 1 and 2 are identified with the 
same reference symbols. 
The capacitors provided for smoothing the supply voltage (the "smoothing 
capacitors") are located essentially entirely below the supply 
interconnects 1 and 2. They are illustrated there as dotted areas. 
The numerous poly sections 11 and 12 that are illustrated as dashed areas 
in FIG. 2 are of strip-like design. The number of poly sections 11 and 12 
corresponds--at least in the exemplary embodiment--to the number of 
capacitors present. 
The poly sections 11 are arranged essentially entirely below the VDD supply 
interconnect 1. However, each of the poly sections 11 has a finger-like 
projection 11a which extends, beyond the region of the VDD supply 
interconnect 1, below the VSS supply interconnect 2 and is connected to 
the latter at that point by means of the through-plated hole 41 
illustrated as a black area. A similar situation applies to the poly 
sections 12: they are arranged essentially entirely below the VSS supply 
interconnect 2, but each of the poly sections 12 has a finger-like 
projection 12a which extends, beyond the region of the VSS supply 
interconnect 2, below the VDD supply interconnect 1 and is connected to 
the latter at this point by means of the through-plated hole 51. 
In order that the finger-like projections 11a and 12a are able to pass by 
one another with a sufficient spacing, the poly sections 11 and 12 are 
arranged offset relative to one another in their transverse direction. The 
mutual offset may be dispensed with, particularly if the poly sections 11 
and 12 are wider and/or the finger-like projections 11a and 12a are 
narrower than illustrated in FIG. 2. 
The p.sup.+ -region 21 (not shown in FIG. 2) located below each poly 
section 11 is designed with a larger area than the relevant poly section 
11 and is connected to the VDD supply interconnect 1 by means of a 
multiplicity of plated-through holes 42 arranged in a row. That row of 
plated-through holes is located in each case in the intermediate space 
between adjacent poly sections 11. It is not necessary for each poly 
section 11 to be assigned its own p.sup.+ -region 21. Instead, it is also 
possible to provide a single large p.sup.+ -region common to all poly 
sections 11. 
The same applies to the capacitors provided below the VSS supply 
interconnect 2: the n.sup.+ -region 31 (not shown in FIG. 2) located below 
each poly section 12 is designed with a larger area than the relevant poly 
section 12 and is connected to the VSS supply interconnect 2 by means of a 
multiplicity of plated-through holes 52 arranged in a row. That row of 
plated-through holes is located in each case in the intermediate space 
between adjacent poly sections 12. It is not necessary for each poly 
section 12 to be assigned its own n.sup.+ -region 31. Instead, it is also 
possible to provide a single large n.sup.+ -region common to all poly 
sections 12. 
Each capacitor has a substrate contact. This is the plated-through contact 
43 in the case of the capacitors located below the VDD supply interconnect 
1. In the case of the capacitors located below the VSS supply interconnect 
1 it is the plated-through hole 53. 
The arrangement of capacitors below the supply interconnects, which has not 
been practical in the past, proves to be advantageous in several respects: 
firstly because that space has not been used otherwise to date and the 
size of the integrated circuit is not increased by disposing the 
capacitors at that position, and secondly because the essential 
connections between the supply interconnects and the capacitors, wherever 
they may be provided, can thus be produced in a particularly simple and 
elegant manner. 
Although the topography illustrated in FIG. 2 is currently considered the 
best mode embodiment with the simplest and most efficient capacitor 
configuration, it should not be understood as restricting the invention. 
In principle, the capacitors may be arranged in any desired manner below 
the supply interconnects. 
In summary, it will be appreciated that the above-described integrated 
circuit can be accommodated very simply on a minimal area.