Active input/output expander of a memory sub-system

A read command to read a target memory die of a memory sub-system is received from a host system via a host-side interface of an active input/output (I/O) expander. The active I/O expander identifies a page address corresponding to the target memory die and decodes the read command to send to a memory stack associated with the page address corresponding to the target memory die. Read data is received via a memory-side interface of the active I/O expander from the memory stack including the target memory die. A signal conditioning operation is performed on the read data to generate conditioned read data. The active I/O expander sends, via the host-side interface, the conditioned read data to the host system.

TECHNICAL FIELD

Embodiments of the disclosure relate generally to memory sub-systems, and more specifically, relate to an active input/output expander of a memory sub-system.

BACKGROUND

A memory sub-system can be a storage system, such as a solid-state drive (SSD), or a hard disk drive (HDD). A memory sub-system can be a memory module, such as a dual in-line memory module (DIMM), a small outline DIMM (SO-DIMM), or a non-volatile dual in-line memory module (NVDIMM). A memory sub-system can include one or more memory components that store data. The memory components can be, for example, non-volatile memory components and volatile memory components. In general, a host system can utilize a memory sub-system to store data at the memory components and to retrieve data from the memory components.

DETAILED DESCRIPTION

Aspects of the present disclosure are directed to an active input/output (TO) expander of a memory sub-system. An example of a memory sub-system is a storage device that is coupled to a central processing unit (CPU) via a peripheral interconnect (e.g., an input/output bus, a storage area network). Examples of storage devices include a solid-state drive (SSD), a flash drive, a universal serial bus (USB) flash drive, and a hard disk drive (HDD). Another example of a memory sub-system is a memory module that is coupled to the CPU via a memory bus. Examples of memory modules include a dual in-line memory module (DIMM), a small outline DIMM (SO-DIMM), a non-volatile dual in-line memory module (NVDIMM), etc. In some embodiments, the memory sub-system can be a hybrid memory/storage sub-system. In general, a host system can utilize a memory sub-system that includes one or more memory components. The host system can provide data to be stored at the memory sub-system and can request data to be retrieved from the memory sub-system.

The memory sub-system can include an active IO expander to process commands (e.g., read, write, read status, get feature, etc.) from a host system corresponding to data stored in a high capacity storage area including multiple memory stacks each having multiple memory die. The active IO expander includes an interface to the host system (e.g., a host-side interface) that is compliant with Open NAND Flash Interface (ONFI) specifications (herein referred to as an “ONFI-compliant interface” or “ONFI interface”) to send and receive commands in accordance with the ONFI protocol. The active IO expander further includes an ONFI-compliant interface to the high capacity storage area including the multiple memory stacks (i.e., a memory-side interface). The active IO expander decodes ONFI commands processed via the host-side interface and the memory-side interface to program or write data to the memory stacks. The active I/O expander operates as a switch (e.g., a 1×2 or 1×4 switch) to select from multiple memory channels to perform addressing functions and communicate with the multiple memory stacks of the high capacity storage area in view of the read and write commands received from the host system.

Conventional memory sub-systems include storage areas that have a limited number of dies per each memory channel. Accordingly, conventional interfaces between a controller of the memory sub-system and the low capacity storage area are configured to support a lower media throughput in order to process commands corresponding to the limited number of dies associated with each memory channel. However, these configurations do not allow for additional memory die to be supported at sufficiently high data transmission rates. As such, as memory sub-system sizes expand with additional memory die, conventional interfaces are not able to support the increased number of memory die per transmission channel.

Aspects of the present disclosure address the above and other deficiencies by including an ONFI-compliant active I/O expander in a memory sub-system to enable an increased number of memory die (e.g., higher capacity) that can be supported by a controller channel, thereby enabling increased media throughput (e.g., greater than 1200 MT/s). The ONFI-compliant active IO expander can decode ONFI-protocol commands relating to writing data to the memory die and reading data from the memory die. The ONFI-compliant active IO expander can perform signal conditioning operations (e.g., buffering, re-timing, re-driving) on signals sent by the host-side controller to and from the memory die.

Advantages of the present disclosure include, but are not limited to, improved host-side and memory-side interfaces configured to support ONFI-compliant drive strength tuning, on-die termination (ODT), and calibrating (e.g., ZQ calibration). Furthermore, the ONFI-compliant active I/O expander enables a host system to connect to a larger number of memory dies at higher speeds and optimizes power and performance behavior of the memory sub-system.

FIG. 1illustrates an example computing environment100that includes a memory sub-system110in accordance with some embodiments of the present disclosure. The memory sub-system110can include media, such as memory components112A to112N. The memory components112A to112N can be volatile memory components, non-volatile memory components, or a combination of such. In some embodiments, the memory sub-system is a storage system. An example of a storage system is a SSD. In some embodiments, the memory sub-system110is a hybrid memory/storage sub-system. In general, the computing environment100can include a host system120that uses the memory sub-system110. For example, the host system120can write data to the memory sub-system110and read data from the memory sub-system110.

The host system120can be a computing device such as a desktop computer, laptop computer, network server, mobile device, or such computing device that includes a memory and a processing device. The host system120can include or be coupled to the memory sub-system110so that the host system120can read data from or write data to the memory sub-system110. The host system120can be coupled to the memory sub-system110via a physical host interface. As used herein, “coupled to” generally refers to a connection between components, which can be an indirect communicative connection or direct communicative connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical, optical, magnetic, etc. Examples of a physical host interface include, but are not limited to, a serial advanced technology attachment (SATA) interface, a peripheral component interconnect express (PCIe) interface, universal serial bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), etc. The physical host interface can be used to transmit data between the host system120and the memory sub-system110. The host system120can further utilize an NVM Express (NVMe) interface to access the memory components112A to112N when the memory sub-system110is coupled with the host system120by the PCIe interface. The physical host interface can provide an interface for passing control, address, data, and other signals between the memory sub-system110and the host system120.

The memory components112A to112N can include any combination of the different types of non-volatile memory components and/or volatile memory components. An example of non-volatile memory components includes a negative-and (NAND) type flash memory. Each of the memory components112A to112N can include one or more arrays of memory cells such as single level cells (SLCs) or multi-level cells (MLCs) (e.g., triple level cells (TLCs) or quad-level cells (QLCs)). In some embodiments, a particular memory component can include both an SLC portion and a MLC portion of memory cells. Each of the memory cells can store one or more bits of data (e.g., data blocks) used by the host system120. Although non-volatile memory components such as NAND type flash memory are described, the memory components112A to112N can be based on any other type of memory such as a volatile memory. In some embodiments, the memory components112A to112N can be, but are not limited to, random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), phase change memory (PCM), magneto random access memory (MRAM), negative-or (NOR) flash memory, electrically erasable programmable read-only memory (EEPROM), and a cross-point array of non-volatile memory cells. A cross-point array of non-volatile memory can perform bit storage based on a change of bulk resistance, in conjunction with a stackable cross-gridded data access array. Additionally, in contrast to many flash-based memories, cross-point non-volatile memory can perform a write in-place operation, where a non-volatile memory cell can be programmed without the non-volatile memory cell being previously erased. Furthermore, the memory cells of the memory components112A to112N can be grouped as memory pages or data blocks that can refer to a unit of the memory component used to store data.

The memory system controller115(hereinafter referred to as “controller”) can communicate with the memory components112A to112N to perform operations such as reading data, writing data, or erasing data at the memory components112A to112N and other such operations. The controller115can include hardware such as one or more integrated circuits and/or discrete components, a buffer memory, or a combination thereof. The controller115can be a microcontroller, special purpose logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor. The controller115can include a processor (processing device)117configured to execute instructions stored in local memory119. In the illustrated example, the local memory119of the controller115includes an embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines that control operation of the memory sub-system110, including handling communications between the memory sub-system110and the host system120. In some embodiments, the local memory119can include memory registers storing memory pointers, fetched data, etc. The local memory119can also include read-only memory (ROM) for storing micro-code. While the example memory sub-system110inFIG. 1has been illustrated as including the controller115, in another embodiment of the present disclosure, a memory sub-system110may not include a controller115, and may instead rely upon external control (e.g., provided by an external host, or by a processor or controller separate from the memory sub-system).

The memory sub-system110includes an ONFI-compliant active I/O expander113(also referred to as an ONFI-compliant active I/O expander) to process commands (e.g., read and write commands) from a host system relating to data stored in a high capacity storage area including multiple memory stacks having multiple memory die. The ONFI-compliant active I/O expander113includes a first host-side interface communicatively coupled to a host-side controller (also referred to as a host-side interface) that is compliant with ONFI specifications (herein referred to as an “ONFI-compliant”) to send and receive commands in accordance with the ONFI protocol. In an embodiment, the host-side interface can operate at a data transmission rate of between approximately 800 MT/s and approximately 2400 MT/s. The ONFI-compliant active I/O expander113also includes an interface to a high capacity storage area including multiple memory stacks, where each memory stack can include multiple memory die (also referred to as the “memory-side interface”). In an embodiment, the memory-side interface of the ONFI-compliant active I/O expander113is configured to operate as a demultiplexer or switch between multiple different memory stacks (e.g., a 1×2 switch, a 1×4 switch) operating at data transmission rates of between approximately 800 MT/s-2400 MT/s (e.g., depending on a data loading level and printed circuit board (PCB) trace length)

The active IO expander decodes ONFI commands processed via the host-side interface and the memory-side interface to program or write data to the memory stacks. The active I/O expander operates as a switch (e.g., a 1×2 or 1×4 switch) to select from multiple memory channels to communicate with the multiple memory stacks of the high capacity storage area in view of the read and write commands received from the host system. In an embodiment, the memory sub-system110includes multiple ONFI-compliant active I/O expanders113, where each of the multiple ONFI-compliant active I/O expanders113supports one or more sets of memory components (e.g., memory stacks including multiple memory die) in a 2×2 mode.

In an embodiment, the ONFI-compliant active I/O expander113provides a communication pathway between with the memory component112A-112N (e.g., memory die) and the host system120. In an embodiment, the ONFI-compliant active I/O expander113presents as the host system120(or controller115of the host system120) at the memory-side interface. In an embodiment, the ONFI-compliant active I/O expander113can have a volume address configuration to process commands from the host system120and uses volume select commands to select the memory component112A-112N that is the subject of the command (e.g., a read or write command). In another embodiment, the ONFI-compliant active I/O expander113includes a chip enable (CE) decoder to process commands from the host system120and uses CE decoding to select the memory component112A-112N that is the subject of the command.

Advantageously, the ONFI-compliant active I/O expander113performs one or more signal conditioning operations (e.g., buffering, retiming, redriving, etc.) on the signals and corresponding data communicated between the host system130and the memory components112A-112N. The ONFI-compliant active I/O expander113operates at ONFI-level speeds and enable parameter tuning (e.g., power management, drive strength (DS), on-die termination (ODT), calibration) to operate for multiple different memory configurations at increased speeds (e.g., in a range of 800 MT/s and 2400 MT/s), such as, for example an average operating speed of approximately 1200 MT/s. In an embodiment, this enable the ONFI-compliant active I/O expander113to deliver performance at optimized power levels.

FIG. 2illustrates an example ONFI-compliant active I/O expander213communicatively coupled to a controller215of a host system220and multiple memory components (e.g., multiple memory stacks280A-280D each having sets of multiple memory die (281A-281D). In an embodiment, each memory stack (e.g., memory stack280A) includes a die loading level of multiple memory die281(e.g., memory die281A), such as four, eight, sixteen, thirty-two, or sixty-four memory dies per each memory stack and corresponding ONFI channel (e.g., ONFI channel290A). The ONFI-compliant active I/O expander213manages signals between the host system220(e.g., via controller215) and the memory stacks280A-280D to execute various commands (e.g., read and write commands). As shown inFIG. 2, the ONFI-compliant active I/O expander213includes a host-side ONFI interface260to communicate with the controller215of the host system220via an ONFI channel218(e.g., a channel compliant with the ONFI protocol and specifications). In an example, the host-side ONFI interface260(e.g., an ONFI4 NV-DDR3 interface) is configured to process data at a rate in an approximate range of at least 800 MT/s to 1600 MT/s.FIG. 2illustrates an example 1×4 ONFI-compliant active I/O expander213, where the ONFI-compliant active I/O expander213communicates with four different memory stacks280A-280D via respective ONFI channels290A-290D.

As shown inFIG. 2, the ONFI-compliant active I/O expander213includes a memory-side ONFI interface270to communicate with the multiple memory stacks280A-280D and corresponding memory die281A-281D via a respective ONFI channel290A-290D. In an embodiment, the memory-side ONFI interface270is an 8-bit data/strobe interface. In an example, the memory-side ONFI interface260(e.g., an ONFI4 NV-DDR3 interface) is configured to process data at a rate in an approximate range of at least 800 MT/s to 1600 MT/s.

The ONFI-compliant active I/O expander213also includes a calibration module230, a signal conditioning module240, and an ONFI command decode module250to perform various operations and functions relating to the processing of signals between the controller215of the host system220and the memory stacks280A-280D. In an embodiment, the calibration module230configures or tunes one or more parameters of the host-side ONFI interface260and the memory-side ONFI interface270. For example, the calibration module230can tune drive strength (DS) and on-die termination (ODT) settings for the host-side ONFI interface260and the memory-side ONFI interface270. In an embodiment, the calibration module230can initiate a calibration process to change one or more values of the memory-side ONFI interface270to enable ONFI-compliant communications (e.g., a ZQ calibration process). In an embodiment, the calibration process can be initiated via the ONFI channel290A-290D corresponding to the memory stack280A-280D addressed in a read or write command to tune parameters in view of the target memory die. In an embodiment including multiple ONFI-compliant active I/O expanders (e.g., as shown inFIG. 6), in response to a command identifying a memory die of interest (e.g., a memory die that is subject to the command, also referred to as a “target memory die”), the calibration module230selects the ONFI-compliant active I/O expander associated with the corresponding memory stack280A-280D including the target memory die. In an embodiment, the calibration module230is a component of each ONFI-compliant active I/O expander213. For example, when there are multiple ONFI-compliant active I/O expander213each with a calibration module230, the process can be initiated in a broadcast fashion, via a host-side ONFI channel command, wherein each calibration module230operates on its respective memory side interface. In an embodiment, there are no communications or coordination between the multiple ONFI-compliant active I/O expanders213.

In an embodiment, the host-side ONFI interface260and the memory-side ONFI interface270settings (e.g., the DS and ODT settings) can be set to match a parasitic load on the traces and the interfaces of the active I/O expander.

The ONFI command decode module250receives, inspects, decodes and passes through a read command received from the host system220to a target memory die (e.g., the memory die that is the subject of the read command). In an embodiment, the ONFI command decode module250provides memory address information (e.g., memory page address information) associated with the current command (e.g., a destination page address for a write command or a page address to read the data for a read command).

In an embodiment, the signal conditioning module240conditions the signals transmitted between the host system220and the memory stacks280A-280D. In an embodiment, signals received from both the host-side ONFI interface260and the memory-side ONFI interface270are conditioned (or re-conditioned) in accordance with the ONFI specifications for transmission via the ONFI interfaces260,270and ONFI channels218,290A-290D. For example, the signal conditioning module240can buffer, retime, and re-drive the data to the controller215of the host system220and the memory stacks280A-280D.

FIG. 3is a flow diagram of an example method300to perform configuration of parameters and calibration of an ONFI-compliant active I/O expander of a memory sub-system in accordance with some embodiments of the present disclosure. The method300can be performed by processing logic that can include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the method300is performed by the ONFI-compliant active I/O expander113ofFIG. 1. Although shown in a particular sequence or order, unless otherwise specified, the order of the processes can be modified. Thus, the illustrated embodiments should be understood only as examples, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. Additionally, one or more processes can be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are possible.

At operation310, the processing device selects, in response to a command from a host system, an active I/O expander associated with a target memory die of a memory sub-system. In an embodiment, the target memory die is identified as a memory die of interest that is the subject of a command (e.g., a read command, a write command, etc.) from a host system. In an embodiment, the active I/O expander is selected from multiple active I/O expanders included within the memory sub-system, where each active I/O expander is connected to multiple memory stacks (e.g., multiple NAND packages), and where each of the multiple memory stacks includes multiple memory dies. An example of a memory sub-system including multiple active I/O expanders is shown inFIG. 6.

In operation320, the processing device configures a value setting (e.g., a register setting) associated with one or more parameters of at least one of a host-side ONFI interface and a memory-side ONFI interface of the active I/O expander to enable ONFI-compliant communications between the host system and the target memory die. In an embodiment, the one or more parameters can include a drive strength parameter and on-die termination (ODT) parameter. In an embodiment, resistor values can be selected to provide optimal slew rate and impedance matching to achieve the desired performance for the loading, without dissipating excess power. In an embodiment, this behavior can change from system to system, such that the tuning of these settings in firmware provides valuable control functionality. For example, the host-side interface can be configured to have a value setting of 37.5 Ohms or 50 Ohms for the drive strength parameter. In another example, the value setting of the ODT parameter for the memory-side interface can be 50 Ohms, 75 Ohms, 150 Ohms, etc.

In an embodiment, configuring the value setting of the one or more parameters enables operation of the ONFI-compliant active I/O expander in different memory configurations (e.g., different SSD configuration including memory die having single level cells (SLCs), multi-level cells (MLCs), triple level cells (TLCs) or quad-level cells (QLCs)). In an embodiment, configuring the one or more parameters allows the ONFI-compliant active I/O expander to be used with different printed circuit board (PCB) types and memory die loading levels (e.g., the number of memory die per channel or memory stack).

In operation330, the processing device initiates a calibration command to tune the one or more parameters of at least one of a host-side interface or a memory-side interface. In an embodiment, the calibration command is a ZQ calibration command. In an embodiment, the calibration procedure can track drift in the drive strength resistor values due to process, voltage or temperature variations. In an embodiment, incorporation of the calibration process in an ONFI-compliant active I/O expander allows for more accurate performance tracking. In an embodiment, the ZQ calibration (ZQCAL) command can manage process-voltage-temperature (PVT) variations in the one or more parameters (e.g., the drive strength and ODT values).

In an embodiment, operations320and330can be performed in parallel. In an embodiment, the value settings for the various parameters (e.g., DS, ODT, DS, ZQCAL) can be configured with an ONFI-compliant set field (SETF) feature with a dedicated address space that is not used by the memory stacks of the sub-system (e.g. the ONFI-compliant active I/O expander can decode the dedicated address and not forward any SETF commands in the address space to the memory stacks).

At operation410, the processing device receives, from a host system via a host-side interface of an active I/O expander, a read command to read data of a target memory die of a memory sub-system. In an embodiment, the read command is transmitted via an ONFI channel connecting the host-side interface with a controller of the host system. In an example, the ONFI channel and host-side interface operate in accordance with the ONFI protocol at a rate between 800 MT/s and 1600 MT/s.

In operation420, the processing device identifies a page address corresponding to the target memory die. In an embodiment, the page address can be determined by the flash translation layer (FTL) on the host-side controller. That in turn communicates with the appropriate ONFI channels flash controller which then dispatches the physical memory die page address to the correct ONFI channel. In an embodiment, the active I/O expander determines which of the multiple connected memory stacks includes the target memory die and identifies the corresponding page address.

In operation430, the processing device decodes the read command to send to a memory stack associated with the page address corresponding to the target memory die. In an embodiment, an ONFI command decode module of the active I/O expander (e.g., the ONFI Command Decode Module250ofFIG. 2) receives the read command from the host-side ONFI-compliant interface (e.g., host-side ONFI interface260ofFIG. 2), inspects the read command, and decodes the read command. In an embodiment, the read command format can be specified in the ONFI specifications (e.g., a Multi-Plane Read command can consists of two command cycles 00h-32h).

After decoding the read command, the decoded command is sent to the memory stack associated with the target memory die via the memory-side interface of the active I/O expander. In an embodiment, the read command is transmitted to the selected memory stack of the target memory die with the page address including the data to be read. In an embodiment, operation430can be performed for other commands associated with a memory stack, such as a read status command or a get feature command. The decoded read command is transmitted by a memory-side ONFI interface via an ONFI channel to the destination memory stack. In an example, the read command can be transmitted via the ONFI channel at a rate in a range of approximately 800 MT/s to approximately 1600 MT/s.

In operation440, the processing device receives, via a memory-side interface of the active I/O expander, read data from the memory stack including the target memory die. In an embodiment, the read data (i.e., the data read from the target memory die) is transmitted by the memory stack via an ONFI channel to the memory-side interface of the active I/O expander.

In operation450, the processing device performs a signal conditioning operation on the read data to generate conditioned read data. In an embodiment, the memory-side ONFI-compliant interface passes the read data to a signal condition module of the active I/O expander (e.g., signal conditioning module240ofFIG. 2) to perform the one or more signal conditioning operations. In an embodiment, the signal conditioning operation can include one or more of buffering and retiming the read data. In an embodiment, the buffering operation can include one or more I/O drivers configured to boost and reshape the slope of the signal as it leaves the active I/O expander. In an embodiment, the drive-strength and ODT settings help match this to the receiver. In an embodiment, the retiming operation can clock, latch and drive the signal out, helping clean up incoming jitter and further boosting performance. In an embodiment, the read data can be conditioned to satisfy applicable signal integrity (SI) and performance requirements (e.g., exit latency requirements, reliability requirements, etc.)

In operation460, the processing device sends, via the host-side interface of the active I/O expander, the conditioned read data to the host system. In an embodiment, the processing device transmits the conditioned read out to the controller of the host system via the host-side ONFI-compliant interface of the active I/O expander and the conditioned read data is sent via an ONFI-compliant channel at a data rate in a range of approximately 800 MT/s and approximately 1600 MT/s. In an example, the average data read of the conditioned read data sent to the host system is approximately 1200 MT/s.

FIG. 5is a flow diagram of an example method500for an ONFI-compliant active I/O expander of a memory-subsystem to manage a write command provided by a host system in accordance with some embodiments of the present disclosure. The method500can be performed by processing logic that can include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the method500is performed by the ONFI-compliant active I/O expander113ofFIG. 1. Although shown in a particular sequence or order, unless otherwise specified, the order of the processes can be modified. Thus, the illustrated embodiments should be understood only as examples, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. Additionally, one or more processes can be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are possible.

At operation510, the processing device receives, from a host system via a host-side interface of an active I/O expander, a write command to write data to a target memory die of a memory sub-system. In an embodiment, the write command is transmitted via an ONFI channel connecting the host-side interface with a controller of the host system. In an example, the ONFI channel and host-side interface operate in accordance with the ONFI protocol at a rate between 800 MT/s and 1600 MT/s.

In operation520, the processing device identifies a page address corresponding to the target memory die. In an embodiment, the active I/O expander determines which of the multiple connected memory stacks includes the target memory die and identifies the corresponding page address.

In operation530, the processing device decodes the write command to send to a memory stack associated with the page address corresponding to the target memory die. In an embodiment, an ONFI command decode module of the active I/O expander (e.g., the ONFI Command Decode Module250ofFIG. 2) receives the write command from the host-side ONFI interface (e.g., host-side ONFI interface260ofFIG. 2), inspects the write command, and decodes the write command. After decoding the write command, the decoded command is sent to the memory stack associated with the target memory die via the memory-side ONFI-compliant interface of the active I/O expander. In an embodiment, the write command is transmitted to the selected memory stack of the target memory die with the page address including the data to be programmed. The decoded write command is transmitted by a memory-side ONFI-compliant interface via an ONFI channel to the destination memory stack. In an example, the write command can be transmitted via the ONFI channel at a rate in a range of approximately 800 MT/s to approximately 1600 MT/s.

In operation540, the processing device receives, from the host system via the host-side interface of the active I/O expander, data to be written (also referred to as “write data”) to the target memory data. In an embodiment, the host system can provide the write data to the active I/O expander a short time duration following operation530. In an embodiment, the write data (i.e., the data to be written to the target memory die) is transmitted by the controller of the host system via an ONFI channel to the host-side interface of the active I/O expander.

In operation550, the processing device performs a signal conditioning operation on the write data to generate conditioned write data. In an embodiment, the memory-side interface passes the write data to a signal condition module of the active I/O expander (e.g., signal conditioning module240ofFIG. 2) to perform the one or more signal conditioning operations. In an embodiment, the signal conditioning operation can include one or more of buffering and retiming the write data.

In operation560, the processing device sends the conditioned write data to the target memory die. In an embodiment, the processing device transmits the conditioned write data out to the memory stack associated with the target memory die via the memory-side interface of the active I/O expander and the conditioned write data is sent via an ONFI-compliant channel at a data rate in a range of approximately 800 MT/s and approximately 1600 MT/s. In an example, the average data read of the conditioned read data sent to the host system is approximately 1200 MT/s.

In an embodiment, method300(ofFIG. 3) can be performed as a part of either method400(ofFIG. 4) or method500(ofFIG. 5). In an embodiment, operations310-330can be performed for a read command in connection with operations410-460. For example, operation410can be performed following execution of operations320or330(e.g., in the event operations320and330are performed in parallel). In an embodiment, operations310-330can be performed for a write command in connection with operations510-560. For example, operation510can be performed following execution of operations320or330(e.g., in the event operations320and330are performed in parallel).

FIG. 6illustrates a system having a 2×2 configuration where ONFI-compliant active I/O expander613A is connected to memory stack680A and memory stack680B, and ONFI-compliant active I/O expander613B is connected to memory stack680C and memory stack680D. Accordingly, in the example shown inFIG. 6, if a target memory die (e.g., the subject of a read command according toFIG. 4or a write command according toFIG. 5) is part of the memory die set681C, the processing device selects ONFI-compliant active I/O expander613B B to process the command and corresponding signals (e.g., as detailed above with respect to operation310ofFIG. 3).

The example computer system700includes a processing device702, a main memory704(e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory706(e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system718, which communicate with each other via a bus730.

The data storage system718can include a machine-readable storage medium724(also known as a computer-readable medium) on which is stored one or more sets of instructions726or software embodying any one or more of the methodologies or functions described herein. The instructions726can also reside, completely or at least partially, within the main memory704and/or within the processing device702during execution thereof by the computer system700, the main memory704and the processing device702also constituting machine-readable storage media. The machine-readable storage medium724, data storage system718, and/or main memory704can correspond to the memory sub-system110ofFIG. 1.