Motor driving apparatus

A motor driving apparatus includes a driving circuit that drives a motor based on a driving instruction signal at a first state of the first state and a second state which are binarized, a current feedback circuit including a latch circuit, and a controller that outputs the driving instruction signal and a current command signal. The latch circuit latches a third state of the third state and a fourth state which are binarized if a motor current value exceeds a current command value. When the driving instruction signal becomes the second state, the latch circuit releases the latching of the third state and outputs a signal of the fourth state. The controller outputs the driving instruction signal of the second state along with the current command signal so as to release the latching of the latch circuit when outputting the current command signal with the current command value changed.

The present application is based on Japanese patent application No. 2016-013032 filed on Jan. 27, 2016, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

Technical Field

The present invention relates to a motor driving apparatus.

Background Art

A power conversion apparatus that controls a current in a motor on the basis of a result of comparing a current command with a current feedback signal outputted from a current detector is known as an example of conventional technology (see Patent Document 1, for example).

CITATION LIST

Patent Literature

Patent Document 1: Japanese Unexamined Patent Application Publication No. 2008-206319A

SUMMARY OF INVENTION

Technical Problem

A current control apparatus is known in which, as an example of the above-described current control, the apparatus compares a current command value with a value of a current flowing in a motor and drives the motor intermittently with a constant current upon the current value exceeding the current command value. This current control apparatus includes a latch circuit. In this current control apparatus, a signal is switched from Lo to Hi upon the current value exceeding the current command value, and the latch circuit latches the signal of Hi state. There is a problem with this current control apparatus in that in the case where the current command value switches to another current command value without pause, the output of the latch circuit will not switch from Hi to Lo and will remain latched at Hi, so that current does not flow to the motor.

Accordingly, an object of the present invention is to provide a motor driving apparatus in which, even if a current command value has switched, a motor current based on the switched current command value can be supplied to a motor.

Solution to Problem

One aspect of the present invention provides a motor driving apparatus including a driving circuit that drives a motor on the basis of a driving instruction signal in a first state among first and second binary states, a current feedback circuit including a latch circuit, and a controller that outputs the driving instruction signal and a current command signal. The latch circuit latches a third state among third and fourth binary states in the case where a motor current value of a current flowing in the motor and a current command value based on the current command signal that is inputted are compared, and the motor current value exceeds the current command value. The latch circuit is released from a latch state in the third state and becomes the fourth state in the case where the driving instruction signal becomes the second state. The controller outputs the driving instruction signal in the second state along with the current command signal in the case of outputting the current command signal that changes the current command value.

Advantageous Effects of Invention

According to the present invention, even if the current command value has switched, the motor current based on the switched current command value can be supplied to the motor.

DESCRIPTION OF EMBODIMENT

Overview of Embodiment

A motor driving apparatus according to an embodiment is generally configured including a driving circuit that drives a motor on the basis of a driving instruction signal in a first state among first and second binary states, a current feedback circuit including a latch circuit, and a controller that outputs the driving instruction signal and a current command signal. The latch circuit latches a third state among third and fourth binary states in the case where a motor current value of a current flowing in the motor and a current command value based on the current command signal that is inputted are compared, and the motor current value exceeds the current command value. The latch circuit is released from a latch state in the third state and becomes the fourth state in the case where the driving instruction signal becomes the second state. The controller outputs the driving instruction signal in the second state along with the current command signal and releases a latch state of the latch circuit in the case of outputting the current command signal that changes the current command value.

With this motor driving apparatus, even if a current command signal that changes the current command value of the current command signal inputted previously is continuously inputted, the driving instruction signal in the second state is outputted so as to release the latch state of the latch circuit. Thus compared to a case where this configuration is not employed, the third state does not continue to be latched, and thus even if the current command value switches, a motor current based on the switched current command value can be supplied to the motor.

Embodiment

Overview of Motor Driving Apparatus1

FIG. 1is a block diagram illustrating an example of the motor driving apparatus according to the embodiment. InFIG. 1, arrows indicate the flows of primary signals.

A motor driving apparatus1is configured to supply a motor current IAbased on a current command signal S1to a motor9.

As illustrated inFIG. 1, the motor driving apparatus1is generally configured including a driving circuit2that drives the motor9on the basis of a driving instruction signal S1in a first state among first and second binary states, a current feedback circuit3including a latch circuit4, and a microcomputer5serving as a controller that outputs the driving instruction signal S1and a current command signal S2. The latch circuit4latches (holds) a third state among third and fourth binary states in the case where a motor current value Imof a current flowing in the motor9and a current command value I1based on the current command signal S2that is inputted are compared, and the motor current value Imexceeds the current command value I1. The latch circuit4is released from a latch state in the third state and becomes the fourth state in the case where the driving instruction signal S1becomes the second state. The microcomputer5serving as the controller outputs the driving instruction signal S1in the second state along with the current command signal S2and releases a latch state of the latch circuit4in the case of outputting the current command signal S2that changes the current command value I1.

The first state in the present embodiment is Hi. The second state is Lo. The third state is Hi. Finally, the fourth state is Lo. Upon the input of the driving instruction signal S1indicating Hi, a driving circuit100starts driving the motor9. The latch circuit4latches a Hi state in the case where the motor current value Imhas exceeded the current command value I1.

Configuration of Driving Circuit2

As illustrated inFIG. 1, the driving circuit2is generally configured including a gate circuit part20and a drive circuit part21, for example.

The gate circuit part20includes two AND circuits200. The gate circuit part20outputs, for example, a driving signal VCWand a driving signal VCCWon the basis of the driving instruction signal S1and a latch output signal S3outputted from the latch circuit4.

In the present embodiment, a rotating direction of the motor9is controlled, and thus the driving signal VCWor the driving signal VCCWis outputted from the corresponding AND circuit200as a logical product of the driving instruction signal S1and the latch output signal S3, a driving direction control signal SCW, or a driving direction control signal SCCW. The drive circuit part21is driven by the driving signal VCWor the driving signal VCCW, and a motor current IAgenerated by a power source22of the drive circuit part21is supplied to the motor9. Note that the driving direction control signal SCWis a signal causing the motor9to rotate forward. The driving direction control signal SCCWis a signal causing the motor9to rotate in reverse.

Configuration of Current Feedback Circuit3

The current feedback circuit3is generally configured including the latch circuit4, a comparator30, a low-pass filter (LPF)31and an LPF32, and a shunt resistor33.

The latch circuit4takes the driving instruction signal S1from the microcomputer5and a comparison output signal VCfrom the comparator30as inputs, and outputs the latch output signal S3on the basis of the driving instruction signal S1and the comparison output signal VCand latches the output state. The latch output signal S3is inputted into the microcomputer5and is inputted into the gate circuit part20via transistors (Tr)35.

The comparator30outputs the comparison output signal VCas a result of comparing the motor current value Imwith the current command value I1. The comparison output signal VCis inputted into the latch circuit4. The motor current value Imis inputted into a noninverting input terminal of the comparator30via the LPF31. The current command value I1is inputted into an inverting input terminal of the comparator30via the LPF32.

The shunt resistor33is connected to the drive circuit part21. The shunt resistor33is also connected to the comparator30via the LPF31. The current feedback circuit3includes the LPF31and the LPF32in order to reduce unstable operations caused by noise, voltage ripples, or the like.

Configuration of Microcomputer5

The microcomputer5includes, for example, a central processing unit (CPU), a random access memory (RAM) and a read only memory (ROM) that are semiconductor memories, and the like. The microcomputer5also includes internal means for generating a clock signal, and operates on the basis of this clock signal. The microcomputer5generates the driving instruction signal S1, the driving direction control signal SCW, the driving direction control signal SCCW, and the current command signal S2.

The driving instruction signal S1is a pulse width modulation (PWM) signal, and is outputted to the gate circuit part20and the latch circuit4. As described above, the driving direction control signal SCWand the driving direction control signal SCCWare signals that control the rotating direction of the motor9, and are outputted to the gate circuit part20.

The current command signal S2is a signal specifying the current command value I1, which is a target value for the motor current IAflowing into the motor9, and serves as a reference voltage by being inputted into the comparator30via the LPF32. By adjusting the current command signal S2, the microcomputer5controls the motor current value Imso as to adjust a rotation speed of the motor9.

An example of operations of the motor driving apparatus1according to the present embodiment will be described below with reference toFIG. 2.

Operation

FIG. 2is a schematic diagram illustrating waveforms of the signals and the like in the example of operations of the motor driving apparatus according to the embodiment.

In an ON period from time t1, the microcomputer5outputs the driving instruction signal S1at Hi (duty: 100%) in response to a driving instruction for the motor9from the exterior (a first driving instruction), and outputs one of the driving direction control signals based on the rotating direction of the motor9to the driving circuit2. In response to the driving instruction signal S1and the driving direction control signal, the gate circuit part20outputs a driving signal based on the driving direction to the drive circuit part21, and the motor current IAflows to the motor9. The motor current value Imof the motor current IAis inputted into the comparator30via the LPF31. As illustrated inFIG. 2, this ON period is a period lasting until the driving instruction signal S1switches from Hi to Lo.

At time t2, the comparator30outputs, to the latch circuit4, the comparison output signal VCindicating that the motor current value Imhas exceeded the current command value I1. In response to the driving instruction signal S1being Hi and the comparison output signal VC, being inputted, the latch circuit4switches the latch output signal S3from Lo to Hi.

After outputting the driving instruction signal S1, upon detecting an edge where the latch output signal S3switches from Lo to Hi for the first time at time t2, the microcomputer5changes the duty of the driving instruction signal S1from 100% to 80%, and an intermittent period starts. This intermittent period is a period, from time t3to time t6, lasting until the current command value I1specified by the first driving instruction switches to a new current command value I1specified by a second driving instruction.

At this time (time t3), the driving instruction signal S1has switched from Hi to Lo, and thus the latch state of the latch circuit4is cleared to switch the latch output signal S3from Hi to Lo.

Note that the microcomputer5ignores the latch output signal S3switching from Lo to Hi in the intermittent period, such as at time t4. In other words, the microcomputer5keeps the duty of the driving instruction signal S1at 80% in the intermittent period.

In the case where, in the intermittent period, the latch output signal S3has switched from Hi to Lo in a period where the driving instruction signal S1is Hi, the latch output signal S3switches from Hi to Lo in synchronization with the driving instruction signal S1switching from Hi to Lo, thus, the latch state is cleared (time t5). In this intermittent period, a motor current IAthat the motor current value Imis above and below the current command value I1flows to the motor9.

In the case where the current command value I1has been switched to a different current command value I1at time t6, and the microcomputer5holds the driving instruction signal S1at Hi, the latch output signal S3will remain at Hi without the latch state being cleared because the driving instruction signal S1has not switched from Hi to Lo.

To clear the latch state when the current command value I1switches, in a latch clear period from time t6to time t11, the microcomputer5according to the present embodiment switches the driving instruction signal S1from Hi to Lo so as to cause the latch state of the latch circuit4to be cleared. This latch clear period is an amount of time that is an integer multiple (no less than 2 times, for example) of the clock signal period, and as one example, is 100 ms. However, the latch clear period is not limited thereto. This latch clear period is changed in accordance with the specifications of the microcomputer5.

The same control as that carried out from time t1to t5described above is carried out from time t11to time t15, when the second driving instruction is in effect.

Effect of Embodiment

With the motor driving apparatus1according to the present embodiment, even if the current command value I1has switched, the motor current IAbased on the switched current command signal S1can be supplied to the motor9. Specifically, even if the current command value I1specified by the current command signal S2inputted previously is switched to a new current command value I1without pause, the motor driving apparatus1outputs the driving instruction signal S1with Lo level and releases the latch state of the latch circuit4. Thus compared to a case where this configuration is not employed, with the motor driving apparatus1, the latch circuit4does not continue to latch the Hi level, and thus even if the current command value I1has switched, the motor current IAbased on the switched current command value I1can be supplied to the motor9.

Parts of the motor driving apparatus1according to the embodiment and modification described above may, depending on the application, be realized by a program executed by a computer, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or the like.

Although an embodiment of the present invention has been described above, this embodiment is merely an example and the invention according to claims is not to be limited thereto. This novel embodiment may be implemented in various other forms, and various omissions, substitutions, changes, and the like can be made without departing from the spirit and scope of the present invention. In addition, all the combinations of the features described in this embodiment are not necessarily needed to solve the problem of the invention. Furthermore, this embodiment is included within the spirit and scope of the invention and also within the invention described in the claims and the scope of equivalents thereof.