Hysteresis comparator circuit for operation with a low voltage power supply

A hysteresis comparator circuit working with a low voltage supply and of a type which includes a composite structure incorporating first and second differential cells respectively comprised of an npn bipolar transistor pair with common emitters, on the one side, and a pair of pnp bipolar transistor pair with common emitters, on the other, such cells being coupled together through the bases of the respective transistors. The circuit includes at least one pair of variable current sources associated with each cell and tied operatively to the voltage value present on the comparator output; in addition, a voltage divider is connected between each interconnection of the bases of the transistors forming the cells.

DESCRIPTION 
1. Field of Application 
This invention relates to an integrated comparator circuit working with a 
low voltage supply and more particularly to hysteresis comparators. 
2. Prior Art 
As is well known, comparators circuits are used to compare two DC voltage 
values with each other, and to output two different set voltage values, 
according to whether an input signal Vin is higher or lower than a 
reference voltage Vr. Comparators are used extensively in integrated 
circuits, e.g., for controlling logic gates. 
On the other hand, for certain specific applications, the use of other 
hysteresis comparators is more appropriate. Hysteresis comparators 
distinguish themselves from the former type in that the switching between 
the two output logic values is brought about by different input voltages. 
Of course, such hysteresis comparators may also be implemented in 
integrated circuit form, and a typical example of a prior art integrated 
comparator is shown in FIG. 1 of the accompanying drawings. 
The comparator of FIG. 1 comprises a differential cell input stage which 
includes a first pair of bipolar transistors T1 and T2, of npn type, 
connected in a common emitter configuration. The collectors of such 
transistors are connected to a power supply line at a voltage Vcc=1 Volt, 
via respective resistors. The bases of these transistors are available to 
serve as circuit inputs, the one for the reference voltage Vr and the 
other for the input signal Vin for example. The emitters of transistors 
T.sub.1 and T.sub.2 are directly connected to a common terminal. A further 
transistor T.sub.3 connects the common terminal to the ground potential 
and operates substantially as a constant current generator. The base of 
transistor T.sub.3 receives a bias voltage V.sub.bias2. 
A second pair of bipolar transistors, of the pnp type, are associated with 
the input stage of the comparator. The bases of the transistors in this 
second pair are connected together and receive a bias voltage V.sub.bias1. 
The collectors of the first pair of npn transistors T1 and T2 are each 
connected to the corresponding emitter of the second pair of pnp 
transistors, respectively. 
The comparator output O is taken from the collector of one transistor in 
the second pair. 
The circuit of FIG. 1 exhibits a fairly small dynamic range in the common 
mode input voltage of about 0.9 Volts. The common mode voltage is the 
highest voltage that can be input without causing anomalous operation of 
the comparator. 
An improvement of the circuit in FIG. 1 is shown in FIG. 2, where an 
additional circuit portion is clearly discernible which is basically a 
follower arrangement and functions as a voltage level shifter. 
That circuit portion comprises a third pair of bipolar transistors, of the 
common base pnp type, which are connected between the supply Vcc and the 
signal inputs of the comparator. Each of these transistors is coupled to a 
resistor having one end connected to a corresponding base terminal of the 
first transistor pair in the input stage. 
Thus, the signal will not be applied to the differential stage directly, 
but supplied thereto through the follower. 
The voltage drop across each resistor will hold the bases of the first 
transistor pair in the input stage at a suitable voltage for proper 
operation of these transistors. 
However, according to the actual value of the common mode voltage at the 
inputs, a different variation of the voltage across the resistors may be 
required to keep the transistors operating correctly. 
For situations such as this, the prior art has proposed a third solution 
shown in FIG. 3. The circuit depicted in FIG. 3 is structurally similar to 
that shown in FIG. 1, except that a second input stage is provided here 
which comprises a pair of common-emitter pnp bipolar transistors. 
In essence, the last-mentioned solution provides a dual differential cell 
for the input circuit portion, which cell comprises a pair of npn 
bipolars, on the one side, and a pair of pnp bipolars, on the other. The 
two pairs are connected in parallel through the bases of their respective 
transistors. 
The first cell is driven by signals at a value close to the supply value 
Vcc, whereas the second cell operation is referenced to a signal ground 
value. However, with both transistor pairs in the "off" state, an 
indefinite condition occurs at the output O. 
SUMMARY OF THE INVENTION 
The underlying object of this invention is to provide a hysteresis 
comparator, working with a low voltage, which has such structural and 
functional features as to overcome the drawbacks of the solutions 
currently proposed in the prior art and affords expanded dynamic range of 
the common mode input voltage. 
According to principles of the present invention, the comparator comprises 
at least one pair of variable current sources associated with each 
differential cell and tied operatively to the comparator output voltage 
value. 
Based on this idea, the technical problem is solved by a comparator as 
described above and defined in the appended claims of claim 1. 
This invention is somewhat similar to the technical approach represented by 
the third of the solutions discussed hereinabove because it uses more than 
one differential cell, however, it has significant advantages not provided 
by this third solution. 
The features and advantages of a comparator according to the invention will 
become apparent from the following description of an embodiment thereof, 
given by way of example and not of limitation, with reference to the 
accompanying drawings.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
With reference to the drawing FIGS. 4 and 5, generally and schematically 
shown at 1 is a hysteresis comparator circuit embodying this invention. 
This comparator 1 comprises a first differential cell including a first 
pair of npn-type bipolar transistors T1 and T2 which have their respective 
emitters in common. Those emitters are also connected to a signal ground 
GND via a bias current source which comprises a transistor Tn on whose 
base a voltage Vb3 appears. 
The collectors C1, C2 of the transistors T1, T2 are connected, through 
respective resistors Rc1 and Rc2, to a power supply line 3 on which a 
relatively low voltage value Vcc of 1 Volt is present. 
The bases B1, B2 of the transistors T1, T2 are, in turn, connected to the 
line 3 through respective variable current sources A1, A2. Advantageously, 
such current sources are controlled by and tied operatively to the value 
of the voltage at the output O of the comparator. 
The circuit 1 further comprises a second differential cell 5 including a 
second transistor pair. T3 and T4. This second pair is formed by pnp-type 
bipolars being, in turn, interconnected with their respective emitters. 
Those emitters are also connected to the supply line 3 via a bias current 
source which comprises a transistor Tp at whose base a bias voltage Vb1 
appears. 
The collectors C3, C4 of the transistors T3, T4 are connected to ground at 
GND via respective resistors Rc3 and Rc4. 
The bases B3, B4 of the transistors T3, T4 are also connected to ground at 
GND, via respective variable current sources A3, A4. These current sources 
are also controlled by and tied operatively to the value of the voltage 
present at the comparator output O. 
The two differential cells 2 and 5 are coupled together through respective 
connections between the bases B1, B4 and the bases B2, B3 of the 
corresponding transistors. 
A voltage divider is connected between each of said base interconnections. 
Specifically, a first resistor pair R1, R4 are connected between the bases 
B1, B4, and a second resistor pair R2, R3 are connected between the bases 
B2 and B3. 
Preferably, the resistors R1, R2, R3 and R4 have equal values, as equal 
values have the currents I1, I2 and I3, I4, respectively. 
The point of interconnection of the first resistor pair R1, R4 is the 
inverting (IN-) input A of the comparator 1. 
On the other hand, the point of interconnection of the second resistor pair 
R2, R3 is the non-inverting (IN+) input B of the comparator 1. 
The structure of the circuit 1 is completed by a third pair of pnp-type 
bipolar transistors T9, T11 having corresponding emitters connected 
directly to the respective collectors C1, C2 of the first transistor pair 
T1, T2 in the cell 2. The transistors T9 and T11 have common-base and are 
supplied by a base voltage VB2. 
A fourth bipolar transistor pair T12, T13 of the npn type are provided in 
association with the second cell 5. Specifically, the transistors T12, T13 
which form this fourth pair have corresponding emitters connected directly 
to the respective collectors C3, C4 of the second transistor pair T3, T4 
in the cell 5. The transistors T12 and T13 have common-base, and the 
first, T12, of them has its base connected to the collector to thereby 
produce a diode configuration. 
The first transistor T9 in the third pair is connected to the first 
transistor T12 in the fourth pair through the connection between their 
respective collectors. Likewise, the second transistor T11 in the third 
pair is connected to the second transistor T13 in the fourth pair through 
the connection between the respective collectors thereof, and the output O 
from the comparator circuit 1 is actually taken from the common collector 
of transistors T11 and T13. 
This output O provides a voltage output value Vo. 
The operation of the circuit according to the invention will now be 
described. 
The composite, npn and pnp, structure of the cells 2 and 5 is connected to 
the signal inputs A and B, through the resistors R1, R2, R3, R4 and the 
variable current sources A1, A2, A3, A4, and provides a shift in logic 
level whose value is controlled by the state of the output O. 
The value of the output O also controls, as with any hysteresis 
comparators, the switching phase between the two (upper and lower) circuit 
thresholds. 
The current source A1 is suitably sized to ensure proper operation of the 
first transistor pair in the input stage, and hence an appropriate state 
of the output O. 
Assume that the signal voltage Vin(+) at the non-inverting input B is lower 
than Vin(-) at the inverting input A. For example, Vin(-) could be equal 
to the upper threshold Vth.sub.sup, and the shift level properly selected 
on the basis of that upper threshold. 
Under these conditions, the transistor T1 would operate in the active 
region until the input voltage Vin(+) attains the upper threshold 
Vth.sub.sup. 
When this threshold value is exceeded, the voltage Vin(+) will drive the 
comparator 1 to shift its output to the lower threshold value Vth.sub.inf. 
At this time, the variable source A1, being tied operatively to the output 
O, is forced to change its outgoing current value by activating the second 
cell 5 formed by the pnp transistor pair T3 and T4. 
This method of operation affords great freedom of selection of the two 
discrete threshold levels, thereby expanding the dynamic range of the 
common mode input voltage. 
One preferred alternative embodiment of the circuit 1 according to the 
invention is shown diagrammatically in FIG. 5. Of course, other circuit 
arrangements could implement the design similar to that of FIG. 4 besides 
the specific alternative shown in FIG. 5. The specific components shown in 
FIG. 5 could also be used in the embodiment of FIG. 4. 
As can be more clearly seen from FIG. 5, the variable sources A1 and A2 can 
include pnp bipolar transistors driven through their respective bases. The 
variable sources A3 and A4 can likewise include npn bipolar transistors. 
The output O of the circuit 1 corresponds to the base terminal of an npn 
transistor T14 having the emitter grounded and the collector connected to 
the supply Vcc via a current source I. 
The collector of this transistor T14 is connected to the base of an npn 
transistor T5 having the emitter grounded. The base of the transistor T5 
also assumes the logic value of inverted output O for the comparator 1. 
The collector of the transistor T5 is connected to the respective bases of 
a set of npn transistors T6, T7, T8 and T10 connected in parallel 
together, with their emitters grounded. The collectors of the transistors 
T6 and T7 are in common with those of the respective npn transistors 
incorporated to the current sources A3 and A4. The transistors T6, T7 and 
T8 may also be considered to be part of the variable current sources in 
some embodiments. 
The first, T6, in said transistor set has its collector connected to the 
collector of a further transistor T15, and through the latter, to the base 
terminals of the pnp transistors incorporated to the current sources A1 
and A2. A diode D1 connects that collector to the supply Vcc as well. 
In the embodiment of FIG. 5, the collector C1 and the collector C4 are 
linked to each other; however, the emitter of T9 is connected to the 
collector Cl and the emitter of T12 is connected to the collector C4 with 
transistors T9 and TI2 connected together. Correspondingly, transistors 
T11 and T13 are connected to collectors C2 and C3, respectively. The 
output is still taken from the common collector point between transistors 
T11 and T13, however, in the alternative embodiment of FIG. 5, this 
represents an output that is linked between the collectors C2 and C3. An 
inverted output is also provided in the embodiment of FIG. 5 as shown. 
The last-mentioned transistor, T15, which is also an npn bipolar type, has 
its base in common with those of the transistors incorporated to the 
current sources A3 and A4 and connected between a current source I' 
associated with the supply Vcc, and a diode D2 connected to ground. 
A similar structure comprising the series of a current source I" and a 
diode D3, is associated with the base of the transistor T10. The collector 
of the transistor T10 is connected to the non-inverting input B, whereto 
the upper voltage threshold value Vth.sub.sup is applied via a resistor 
R5. 
Assuming for the lower voltage threshold Vth.sub.inf a logic level shift 
above that required for the upper threshold, then the current source I' 
will continue to be correlated to this upper threshold value. 
Upon the output O attaining a "high" logic level, the corresponding 
inverted output O will be at a logic "low". Under this condition, the 
current I" is allowed to flow through the diode D3 and will be mirrored by 
the transistor T10 to generate hysteresis of the circuit. 
Through the transistors T6, T7 and T8, the shift in logic level is expanded 
as required tier the lower threshold Vth.sub.inf. 
Understandably, changes and modifications may be made unto the comparator 
circuit of this invention without departing from the invention, the scope 
of the invention being defined in the appended claims.