Connection control circuit and information storage apparatus

A connection control circuit having the function of controlling connection and disconnection of an information storage apparatus to and from a transmission line is constructed such that it uses a comparator to determine whether or not the level of operating clock signal output from a controller of the information storage apparatus is within a predetermined range, and if it is detected that the level of the operating clock signal departs from the predetermined range, the connection control circuit outputs a control signal to a by-pass circuit to disconnect the information storage apparatus from the transmission line loop. This enables the information storage apparatus to be disconnected from the loop even if the controller of the information storage apparatus does not function normally due to an abnormality of the clock or an abnormality of the power supply.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a fiber channel arbitrated loop (generally abbreviated to FC-LA) technology, and more particularly to a technology for avoiding system breakdown, when a component failure occurs in an information storage apparatus, such as a magnetic disk apparatus, on a FC-AL configuration, by disconnecting the relevant apparatus from the loop-like transmission path.

2. Description of the Related Art

FC-AL technology has been increasingly utilized for realizing a high speed interface between an information storage apparatus, such as a magnetic disk apparatus, or the like and a host computer. FC-AL technology is a technology which enables high speed data transfer to be carried out by serially transferring data without giving rise to any skew between different data.

In order for a reader to better understand problems associated with a system using conventional FC-AL technology, the construction of a system using conventional FC-AL technology will be described below with reference toFIG. 1that will be described in the section, “BRIEF DESCRIPTION OF THE DRAWINGS”.

InFIG. 1, a schematic view depicting the construction of a system using FC-AL technology is shown.

As shown inFIG. 1, a host computer2and a plurality of magnetic disk apparatuses3are connected to the transmission line loop1. The host computer is not limited to a single unit, and multiple units may be connected.

The host computer2and each of the magnetic disk apparatuses3are connected to the loop1via ports6. Each of the ports6is provided with a driver4and a receiver5. Each apparatus is connected in the form of a loop with its driver4connected to the receiver5of the port6of the apparatus in the following stage. Although, for the sake of simplicity, only one port is provided in each apparatus of the system shown in the Figure, a plurality of ports may be provided in an apparatus so as to form a plurality of loops.

Corresponding to each port, a by-pass circuit7is additionally provided. Depending on a control signal (loop enable signal) transmitted from a hard disk controller (HDC) (not shown) of the magnetic disk apparatus, each by-pass circuit7selects either the signal transferred from the apparatus in the preceding stage or a signal output from its own driver4as the signal to be sent out to the apparatus in the following stage. The loop enable signal is transmitted to the by-pass circuit7through a dedicated signal line8. When a failure occurs in a magnetic disk apparatus3, the HDC of the relevant magnetic disk apparatus3detects it and cancels the loop enable signal accordingly. In response to this cancellation of the loop enable signal, the by-pass circuit7selects the signal input from the apparatus in the preceding stage, and the magnetic disk apparatus3in which the failure occurs is thereby by-passed.

As has been described above, transmission of the control signal to the by-pass circuit7at the time of occurrence of a failure is performed by the HDC. However, when trouble occurs in a reference clock generator or a power supply, the HDC itself cannot function normally. In this case, the loop enable signal is not properly sent out so that the failed magnetic disk apparatus remains on the loop. In such a state, unexpected data are transferred to other magnetic disk apparatuses connected to the loop, leading to a breakdown of the loop.

SUMMARY OF THE INVENTION

It is a first object of the present invention to resolve the above described problem and to avoid the breakdown of the system due to an abnormality of any apparatus connected to the transmission line and to improve the reliability of the system.

It is a second object of the present invention to enable disconnection of the relevant apparatus from the transmission line, even when an abnormality occurs that cannot be monitored by a controller, such as an abnormality in the reference clock generator or an abnormality in the power supply.

The present invention provides a connection control circuit (that is, a loop control circuit) which comprises a comparator for comparing the level of an operating clock signal of a controller of an information storage apparatus with a threshold level and, based on a result of the comparison, generates a connection control signal for connection of the information storage apparatus to the transmission line.

Usually, when abnormality occurs in an information storage apparatus connected to the transmission line, the controller detects an abnormality and sends a control signal for disconnecting the relevant apparatus from the transmission line. However, when an abnormality such as non-output of a clock signal or departure from a normal frequency occurs, the controller of the information storage apparatus itself cannot function normally, and there is a possibility that the information storage apparatus cannot be disconnected from the transmission line.

Therefore, the present invention provides the above-described connection control circuit which, even if an abnormality occurs in the clock, is able to detect the abnormality, in place of the controller. When the abnormality occurs in the clock, the level of the clock signal deviates from a predetermined range, and the connection control circuit according to the present invention is able to detect this deviation and control the by-pass circuit to be operated accordingly. Thus, even if controller has become unable to operate normally, the failed information storage apparatus can be disconnected from the transmission line so that other apparatuses connected to the transmission line are not affected by the abnormality of the clock.

In the present invention, the abnormality of the clock can be detected as an abnormality of voltage level by converting the clock signal to a DC signal by means of a low-pass filter.

As described before, the cause of the abnormality of the clock includes a failure of the reference clock generator. When the reference clock generator fails, the clock has a frequency different from the normal frequency of the clock. Therefore, by adjusting the cut-off frequency of the low pass filter, the abnormality of the clock can be reliably detected.

Another cause of the abnormality of the clock may be a failure of the power supplied to the controller. When the power supply fails, the level of the clock signal may be lowered, or the clock signal may not be generated at all. Thus, by monitoring the clock, an abnormality of the power supply can be detected. Since the controller cannot operate normally in the event of failure of the power supply, the present invention is also useful when power supply fails. It should be noted that, in order to detect failure of the power supply to the controller, the source of power (power supply) to the comparator of the connection control circuit needs to be different from the power supply to the controller.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The construction and operation of preferred embodiments of the present invention will be described below with reference to the accompanying drawings (FIGS. 2to6).

FIG. 2is a view showing the schematic construction of a system using FC-AL in a connection control circuit according to an embodiment of the present invention.

InFIG. 2, a host computer2and a plurality of magnetic disk apparatuses3are connected to the loop11and loop12of transmission lines. The host computer2writes data into a magnetic disk (not shown in this Figure) contained in the magnetic disk apparatus3, or read out data recorded in a magnetic disk. Although, in the present embodiment, only one computer is connected to the loop, plural computers may be used.

The host computer2and each of the magnetic disk apparatuses3are provided with ports61and62. The port61is connected to the loop11and the port62is connected to the loop12. In the port6k, a driver4kand a receiver5kare provided (here, k denotes 1 or 2). The host computer2and each of the magnetic disk apparatuses3are connected in a loop-like form with its own driver4kbeing connected to the receiver5kof the port6kof the apparatus in the following stage. In the present embodiment, each apparatus is provided with two ports and two systems of loops are formed accordingly.

A by-pass circuit7kis additionally provided corresponding to each port6k. Each of the by-pass circuit7kselects, in response to a loop enable signal generated by a hard disk controller (HDC) (not shown in this Figure) of the magnetic disk apparatus3, either a signal sent from the apparatus in the preceding stage, or a signal output by its own driver, as a signal to be sent to the apparatus in the following stage.

The magnetic disk apparatus3has a dedicated terminal (not shown) for each system of loop for sending out a loop enable signal, and the loop enable signal sent out from the terminal is transmitted via a dedicated signal line8kto the by-pass circuit7k. When a fault occurs in a magnetic disk apparatus3, the HDC of the relevant magnetic disk apparatus3detects the fault and cancels the loop enable signal. In response to this, the by-pass circuit7kselects the signal sent from the apparatus in the preceding stage, and thereby by-passes the magnetic disk apparatus3in which the fault occurs and disconnects it from the loop1k.

FIG. 3is a perspective view showing the magnetic disk apparatus shown inFIG. 2with its cover removed, andFIG. 4is a perspective view showing the rear side of the magnetic disk apparatus.

In the base21of the magnetic disk apparatus3, there are contained a magnetic disk22for storing magnetic data, a spindle motor (SPM)23for rotary driving of the magnetic disk22, and an actuator25etc.

The actuator25is supported on a rotating axis on the base21, and has a magnetic head24mounted on one end thereof for writing data into the magnetic disk22or reading out data stored in the magnetic disk22, and has a coil (not shown) mounted on the other end thereof. The magnetic head24is driven on the magnetic disk22in the radial direction of the magnetic disk22.

On the base21, there is also provided a magnetic circuit27constructed of a permanent magnet and a yoke, and the above-described coil is disposed in the magnetic gap of the magnetic circuit27. A voice coil motor (VCM) for rotating the actuator25is composed of the magnetic circuit27and the coil.

As shown inFIG. 4, a printed circuit board27is mounted on the rear side of the base21. Chips such as a hard disk controller (HDC) and a read channel (RDC) and the like to be described later, and a connector28for interfacing with the host computer2, are mounted on the printed circuit board27. The interior of the base21and the printed circuit board27are electrically connected with each other, via an FPC (not shown).

The magnetic disk apparatus3is connected, via the above mentioned connector28, to a back panel (not shown), and sends and receives data to and from the host computer and other magnetic disk apparatus3via the loops11,12. The by-pass circuits71,72and the signal lines81,82are provided not on the magnetic disk apparatus3but on the back panel. Terminals for taking in and sending out data from and to the loop1k, and terminals for sending out a loop enable signal to the signal line8kare provided on the connector28. The magnetic disk apparatus3connected to the back panel is not restricted to a single unit, but may comprise plural units connected to the loop.

FIG. 5is a block diagram showing the components mounted on the printed circuit board.

On the printed circuit board27, there are mounted a micro-controller (MCU)30, a hard disk controller (HDC)31, a read channel (RDC)32, a servo-controller (SVC)33, a reference clock generator34, a read-only memory (ROM)36and the like, each constructed as a separate chip. Two or more of the MCU30, HDC31and RDC32may be combined into one chip.

The MCU30is constructed of a micro-processor (MPU). The MCU30executes the program stored in the ROM36, and recognizes the position information of the magnetic head24sent from the RDC32, to be described later, controls the driving current of the VCM or SPM23, and performs servo-control for the positioning of the magnetic head24.

The HDC31performs the control of interfacing with the host computer2(e.g., the control for sending out a command to or receiving data from the host computer2), and generates a control signal within the magnetic disk apparatus3for controlling the recording/reproducing format on the magnetic disk22. The HDC31also monitors the presence/absence of an abnormality in the magnetic disk apparatus3, and generates a loop enable signal for controlling connection/disconnection of the relevant magnetic disk apparatus3to and from the loop.

The RDC32comprises a modulation circuit for recording write-data sent from the host computer2to the magnetic disk22, and a demodulation circuit for reproducing read-data read out from the magnetic disk22and the servo signal.

The SVC33is composed of a power amplifier for supplying the driving current to the VCM, and a power amplifier for supplying the driving current to the SPM23, and supplies the driving current to SPM23and VCM in accordance with the instruction from the MCU30.

The reference clock generator34in the present embodiment is constructed of a quartz oscillator, and generates the reference clock. The frequency of the reference clock generated by the reference clock generator34is divided to 1/N of the frequency value in a frequency division circuit35, and provides the operation clock signal for the MCU30and the HDC31.

The read-only memory (ROM)36stores programs and the like which are to be executed by the MCU30and the HDC31.

The data buffer37temporarily stores data to be sent to the host computer2or data received from the host computer2.

The loop control circuit38that constitutes the connection control circuit of the present invention, detects the level of the clock signal output from the HDC36, and sends out the control signal depending on the detected level via the signal line8kto the by-pass circuit7k. When the level of the clock signal indicates abnormality, it sends out the control signal for disconnecting the magnetic disk apparatus3from the loop.

FIG. 6is a circuit diagram showing the loop control circuit according to an embodiment of the present invention.

The loop control circuit38of the present invention is, as shown inFIG. 5, provided on the print circuit board27as a unit separate from the HDC31. The loop control circuit38is largely composed of a low pass filter41for smoothing (to DC) of the clock signal output from the HDC31, a comparator42for comparing the smoothed output with a threshold voltage, and an AND circuit43that gives a logical product of loop enable1signal output from the HDC31and the output of the comparator42.

In a state in which the HDC31outputs a normal clock signal, the clock signal is output after passing through the low pass filter41as a DC signal having about half the level of the voltage of the power supply (that is, the first power supply)39. However, when the generator34fails, the clock signal may not be output from the HDC31or the clock signal having a frequency deviated from the normal value may be output, and as a result, a DC signal at a level indicating the occurrence of an abnormal event is output from the low pass filter41. Also, when the power supply39fails, the clock signal may not be output from the HDC31or the clock signal having a level deviated from the normal value may be output and, as a result, the DC output from the low pass filter41may exhibit a too high or too low level.

The comparator42has two voltage division points (a high level side voltage division point51and a low level side voltage division point52), in which the voltage of the power supply (that is, the second power supply)40is divided by a plurality of resistors44to46. The voltage at the high level side voltage division point51and output level of the low pass filter41is compared by a high level detection circuit53, and the voltage at the low level side voltage division point52and output level of the low pass filter41is compared by a low level detection circuit54. The comparator42outputs the signal at high level when output level of the filter41is between the voltage at the high level side voltage division point51and the voltage at the low level side voltage division point52, and outputs the signal at low level when output level of the filter41is either higher than the voltage at the high level side voltage division point51or lower than the voltage at the low level side voltage division point52.

The values of the voltage dividing resistance are set so that, when a normal clock signal is output from the HDC31, that is, when the level of the output signal from the low pass filter41is about half the voltage of the power supply39, the comparator42outputs the signal at high level. For example, if the voltage of the power supply is 3.3 V, half the value is 1.65 V, so that, allowing for a sufficient margin, the values of resistances44to46are chosen such that the voltage at high voltage division side is about 2.2 V and the voltage at low voltage division side is about 1.3 V.

In other words, when the clock output of the HDC31indicates an abnormality due to a trouble in the power supply39or the generator34, that is, when the output of the low pass filter is too high or too low, the comparator42outputs a signal at low level.

The AND circuit43gives a logical product of the output signal from the comparator42and loop enable1signal generated by the HDC31. The output signal from the AND circuit43is output as a loop enable2signal from the output terminal (not shown) provided in the connector28to the signal line8k, and transmitted to the by-pass circuit7k.

When trouble occurs in the generator34or the power supply39and the HDC31cannot function normally, the loop enable signal output from the HDC31is fixed either to a high level or to a low level. Conventionally, when the loop enable signal deviates to a low level, the loop enable signal is cancelled and the magnetic disk apparatus3can be disconnected from the loop. However, when the loop enable signal is fixed to a low level, the magnetic disk apparatus cannot be cancelled, and unexpected data may be transferred from the defective magnetic disk apparatus to other magnetic disk apparatuses connected to the loop, leading to breakdown of the loop.

In the present embodiment, on the other hand, when failure occurs in the generator34or the power supply39and the HDC31cannot function normally, an abnormality can be recognized from the clock signal output from the HDC31. As described before, when an abnormality is recognized in the clock signal, the comparator42outputs a low level signal so that, irrespective of whether loop enable1signal is fixed to a high level or to a low level, the AND circuit43outputs loop enable2signal at a low level to the signal line8k, and the magnetic disk apparatus can be disconnected from the loop.

When both generator34and the power supply39are normal and the HDC31outputs a normal clock signal, the loop enable1signal exhibits a high level. The output of the comparator is also at high level, as described before. As a result, the AND circuit43outputs the loop enable2signal at a high level. In this state, the magnetic disk apparatus3continues to be connected to the loop.

In the loop control circuit38as shown in the present embodiment, in order to be able to recognize an abnormality of the output clock signal from the HDC31caused by an abnormality of the power supply39, the power supply39for supplying power to the HDC31and the power supply40for supplying power to the comparator42are constructed as separate circuits. The output voltage is the same for both power supplies. If the two are constructed as the same and one power supply, failure of power supply to the HDC31means failure of power supply to the comparator42so that the comparator42no longer functions normally and an abnormality of the clock signal output from the HDC31cannot be detected.

As has been described in the foregoing, according to the preferred embodiments of the present invention, even if the controller itself of an information storage apparatus cannot function normally due to an abnormality of the reference clock or an abnormality of the power supply, a connection control circuit can recognize the abnormality and disconnect the information storage apparatus from the transmission line, and therefore, other apparatuses connected to the transmission line are not affected by the above-mentioned abnormality, and a system with high reliability can be thereby provided.