Semiconductor device with buried gate and method for fabricating the same

A semiconductor device includes buried gates formed over a substrate, storage node contact plugs which are formed over the substrate and include a pillar pattern and a line pattern disposed over the pillar pattern, and a bit line structure which is formed over the substrate and isolates adjacent ones of the storage node contact plugs from each other.

BACKGROUND OF THE INVENTION

Exemplary embodiments of the present invention relate to a technology for fabricating a semiconductor device, and more particularly, to a semiconductor device with buried gates (BG) and a method for fabricating the same.

As the size of semiconductor devices shrinks, compliance with diverse device characteristics and designing appropriate fabrication processes become more difficult. For example, in using 40 nm design rules, formation of structures of gates, bit lines, and contacts is reaching limits. Even if such small structures can be formed, desired device characteristics may not be obtained. To address such features, buried gate (BG) structures having gates buried in a substrate are used,

FIGS. 1A and 1Billustrate a conventional semiconductor device with buried gates.FIG. 1Ais a plan view, andFIG. 1Bis a cross-sectional view of the semiconductor device ofFIG. 1Aalong line A-A′.

Referring toFIGS. 1A and 1B, a plurality of buried gates are formed over a substrate11having active regions13defined by an isolation layer12, and landing plugs14are formed over the active regions13between the buried gates and the isolation layer12. Each buried gate includes a trench15formed over the substrate11, a gate insulation layer (not shown) on the surface of the trench15, a gate electrode16filling a portion of the trench15, and a gate sealing layer17filling the other portion of the trench15. An inter-layer dielectric layer18is formed over the substrate11where the buried gates are formed. Storage node contact plugs20and bit lines23are formed over the inter-layer dielectric layer18. Herein, a reference numeral ‘19’ denotes storage node contact holes, and a reference numeral ‘21’ denotes a damascene pattern. A reference numeral ‘22’ denotes bit line spacers, and a reference numeral ‘24’ denotes a bit line sealing layer.

According to the conventional technology, the storage node contact plugs20are formed after the bit lines23are formed. Here, using the conventional technology, the process margins of the process of forming the storage node contact plugs20may be decreased due to the presence of the bit lines23. To address such a feature, a method of forming the storage node contact plugs20first and then forming the bit lines23was suggested. In such a method, a short may easily occur between the storage node contact plugs20and the land plugs14under the bit lines23.

In addition, according to the conventional technology, the contact area between the landing plugs14and the storage node contact plugs20may be decreased since the storage node contact holes19are formed by etching the inter-layer dielectric layer18is etched at one step, for example, without consideration of the way that the formation of the storage node contact plugs20takes place, where the sidewalls of the storage node contact holes19are formed slanted due to etch characteristics.

SUMMARY OF THE INVENTION

An embodiment of the present invention is directed to a semiconductor device including buried gates which may increase the process margins of a storage node contact plug formation process, and a method for fabricating the same.

Another embodiment of the present invention is directed to a semiconductor device including buried gates which may prevent a short from being formed between storage node contact plugs and landing plugs under bit lines, and a method for fabricating the same.

Another embodiment of the present invention is directed to a semiconductor device including buried gates which may improve the contact margins of storage node contact plugs, and a method for fabricating the same.

In accordance with an embodiment of the present invention, a semiconductor device includes: buried gates formed over a substrate; storage node contact plugs which are formed over the substrate and include a pillar pattern and a line pattern disposed over the pillar pattern; and a bit line structure which is formed over the substrate and isolates adjacent ones of the storage node contact plugs from each other.

In accordance with another embodiment of the present invention, a method for fabricating a semiconductor device includes: forming a first layer over a substrate; forming a first pattern which exposes the substrate by selectively etching the first layer; forming a second layer to cover the substrate; forming a line-type second pattern coupled with the first pattern by selectively etching the second layer; forming a conductive layer to fill the first pattern and the second pattern; and forming contact plugs by selectively etching the conductive layer.

In accordance with yet another embodiment of the present invention, a method for fabricating a semiconductor device includes: forming buried gates over a substrate; forming a first layer over the substrate; forming a first pattern by selectively etching the first layer; forming a second layer over the substrate including the first pattern; forming a line-type second pattern coupled with the first pattern by selectively etching the second layer; forming a conductive layer that fills storage node contact holes including the first pattern and the second pattern; and forming storage node contact plugs by selectively etching the conductive layer, the second layer, and the first layer to form a damascene pattern simultaneously.

DESCRIPTION OF SPECIFIC EMBODIMENTS

Described hereafter is a method for fabricating a semiconductor device including buried gates that may improve process margins of a storage node contact plug forming process, prevent a short from being formed between landing plugs coupled with bit lines and storage node contact plugs, and increase the contact area between the landing plugs and the storage node contact plugs (that is, decrease the contact resistance).

FIG. 2is a plan view illustrating a semiconductor device including buried gates in accordance with an embodiment of the present invention.FIG. 3is a cross-sectional view of the semiconductor device ofFIG. 2along the lines A-A′ and B-B′.

Referring toFIGS. 2 and 3, the semiconductor device fabricated in accordance with the embodiment of the present invention includes buried gates68formed over a substrate61, storage node contact plugs70which penetrate an inter-layer dielectric layer69and include a pillar pattern70A and a line pattern70B over the pillar pattern70A, and a bit line structure75which is formed over the substrate61and electrically isolates adjacent storage node contact plugs70from each other, where the line pattern70are formed in at least two etching steps as described below and a slant in forming the line pattern for storage contact plugs is reduced. Each of the buried gates68formed over the substrate61includes a trench65simultaneously crossing an active region63and an isolation layer62, a gate insulation layer (not shown) formed on the surface of the trench65, a gate electrode66filling a portion of the trench65, and a gate sealing layer67filling the other portion of the trench65over the gate electrode66.

Landing plugs64defined by the buried gates68and the isolation layer62are formed over active regions63. The landing plugs64disposed on the edges of the active regions63are coupled with the storage node contact plugs70, and the landing plugs64disposed in the central portions of the active regions63are coupled with bit lines73.

The pillar pattern70A of each storage node contact plug70is disposed to correspond to the landing plug64of a predetermined region of each storage node contact plug70. The pillar pattern70A secures the contact area between the landing plugs64and the storage node contact plugs70and at the same time, simplifies a process for forming the storage node contact plugs70. Here, a short is prevented from being formed between the landing plugs64coupled with the bit lines73and the storage node contact plugs70.

The line pattern70B of each storage node contact plug70has a shape that it is extended in a direction parallel to the buried gates68between the buried gates68. More specifically, the line pattern70B covers a region of each storage node contact plug70, while being isolated by the bit line structure75. The line pattern70B serves to improve the process margins and stability of the storage node contact plugs70and at the same time to decrease the resistance of the storage node contact plugs70by increasing the volume of the storage node contact plugs70that penetrate the inter-layer dielectric layer69. Moreover, the line pattern70B serves to improve the contact margin between a storage node (not shown) and the storage node contact plugs70by maximizing/increasing the area of the storage node contact plugs70exposed on the surface of the inter-layer dielectric layer69.

The bit line structure75electrically disconnecting the adjacent storage node contact plugs70from each other includes a damascene pattern71penetrating the inter-layer dielectric layer69and extended in a direction that the damascene pattern71crosses the buried gates68, bit line spacers72formed on the sidewalls of the damascene pattern71, bit lines73filling a portion of the damascene pattern71, and a bit line sealing layer74filling the remaining portion of the damascene pattern71over the bit lines73.

Since the semiconductor device having the above-described structure includes the storage node contact plugs70, each of which is formed of the pillar pattern70A and the line pattern70B, it may prevent a short from being formed between the storage node contact plugs70and the landing plugs64under the bit lines73and prevent a decrease in the contact margin and increase in contact resistance and self-resistance of the storage node contact plugs70. The semiconductor device also has an advantage of increasing the process margins in the processes of forming the storage node contact plugs70and the bit line structure75, which processes will be described in detail later while describing a method for fabricating a semiconductor device in accordance with an embodiment of the present invention below.

FIGS. 4A to 4Kare cross-sectional views illustrating a method for fabricating a semiconductor device including buried gates in accordance with an embodiment of the present invention.FIGS. 5A and 5Dare plan views illustrating storage node contact holes in accordance with an embodiment of the present invention.

Referring toFIG. 4A, a first hard mask pattern32where a pad oxide layer32A and a hard mask polysilicon layer32B are sequentially stacked is formed over a substrate31having a cell region and a peripheral region. The first hard mask pattern32may be formed to have a thickness ranging from approximately 600 Å to approximately 1,500 Å in consideration of the depth of isolation trenches and the height of landing plugs to be formed subsequently.

Subsequently, an isolation layer33defining active regions34is formed by using the first hard mask pattern32as an etch barrier and etching the substrate31to thereby form isolation trenches and filling the isolation trenches with an insulating material.

Subsequently, grooves35exposing the active regions34are formed by selectively removing the first hard mask pattern32in the cell region. The grooves35provide the space where landing plugs are to be formed.

Referring toFIG. 4B, a conductive layer36for forming landing plugs is formed over the substrate31to fill the grooves35, and a planarization process is performed until the isolation layer33is exposed. The landing-plug-forming conductive layer36may be a polysilicon layer, and the planarization process may be a Chemical Mechanical Polishing (CMP) process.

Subsequently, a second hard mask pattern37is formed over the substrate31where the landing-plug-forming conductive layer36is already formed in order to form buried gates in the cell region. The second hard mask pattern37is patterned in the cell region and covers the peripheral region. The second hard mask pattern37may be a nitride layer.

Referring toFIG. 4C, line-type trenches38crossing the active regions34and the isolation layer33are formed by using the second hard mask pattern37as an etch barrier and etching the landing-plug-forming conductive layer36, the active regions34and the isolation layer33. After the line-type trenches38are formed, the landing-plug-forming conductive layer36becomes landing plugs36A. The landing plugs36A disposed on the edge of both sides of each active region34are coupled with storage node contact plugs through a subsequent process, and the landing plugs36A disposed in the central portion of each active region34are coupled with subsequently formed bit lines.

Subsequently, a gate insulation layer (not shown) is formed on the surface of the line-type trenches38. The gate insulation layer may be a silicon oxide (SiO2) layer formed through a thermal oxidation process.

Subsequently, a gate electrode39is formed to fill a portion of each line-type trench38. The gate electrode39may be a metallic layer including a metal layer, a metal oxide layer, a metal nitride layer, and a metal silicide layer.

Subsequently, a gate sealing layer40filling the other portion of each line-type trench38is formed over the gate electrode39. The gate sealing layer40may be a nitride layer.

A plurality of buried gates may be formed in the cell region of the substrate31through the above-described process, and the second hard mask pattern37formed in the peripheral region during the buried gates formation process may protect the peripheral region of the substrate31from being damaged or lost.

Referring toFIG. 4D, a first etch stop layer41(for example, an insulation layer) is formed over the substrate31. The first etch stop layer41protects the lower layers from being damaged undesirably while a damascene pattern formation process for forming bit lines and a storage node contact hole formation process are performed subsequently, and thus, first etch stop layer41provides an etch stop point.

Subsequently, a capping layer42is formed over the first etch stop layer41to cover the cell region and open the peripheral region. The capping layer42is a single layer selected from the group consisting of an oxide layer, a nitride layer, and an oxynitride layer, or a stacked layer where more than two of the foregoing layers are stacked.

Subsequently, the active regions34of the peripheral region are exposed by using the capping layer42as an etch barrier and removing the first etch stop layer41, the second hard mask pattern37and the first hard mask pattern32that are formed in the peripheral region. While the first hard mask pattern32is removed, a portion of the isolation layer33may be lost, and to facilitate a subsequent process, the surface of the active regions34and the surface of the isolation layer33in the peripheral region may be made to have the same height (for example, by etching).

Referring toFIG. 4E, peripheral gates46are formed in the peripheral region of the substrate31. The peripheral gates46may be a stacked structure where a peripheral gate insulation layer43, a peripheral gate electrode44, and a peripheral gate hard mask layer45are sequentially stacked. Here, all of the capping layer42of the cell region may be removed in the course of forming the peripheral gates46.

According to an example, the height of the peripheral gates46may be formed to be low to improve the stability of a subsequent process for forming an inter-layer dielectric layer. Here, the height of the peripheral gates46may be formed to be on the same plane as the upper surface of storage node contact plugs, which are to be formed in the cell region. For example, the peripheral gate hard mask layer45may have a thickness of approximately 300 Å to approximately 800 Å after the completion of the peripheral gates forming process. According to another example, the peripheral gate hard mask layer45may have a thickness of approximately 300 Å to approximately 2,500 Å as appropriate.

Subsequently, spacers47are formed on both sidewalls of each peripheral gate46. The spacers47may be formed of a nitride.

Subsequently, a sealing layer48of a desired thickness is formed along the surface of the structure including the peripheral gates46. The sealing layer48serves to protect the peripheral gates46during a subsequent process for forming storage node contact holes and may be formed to have a thickness ranging from approximately 50 Å to approximately 200 Å. The sealing layer48may be formed of a material having an etch selectivity with respect to the first etch stop layer41. For example, the sealing layer48may be an oxide layer.

Referring toFIG. 4F, a first pattern49exposing the landing plugs36A of a region where storage node contact plugs are to be formed is formed by selectively etching the sealing layer48of the cell region, the first etch stop layer41, the isolation layer33, and the gate sealing layer40. The first pattern49serves as a part of storage node contact holes, and the first pattern49is formed to expose the upper surface of the landing plugs36A disposed in the region where storage node contact plugs are to be formed as much as possible.

The first pattern49may be formed in a hole type (seeFIG. 5A) which exposes all the region where storage node contact plugs are to be formed, or it may be formed in a bar type (seeFIG. 5B) which simultaneously exposes an adjacent region and the region where storage node contact plugs are to be formed.

According to another example, the first pattern49may be formed in a shape which exposes all the landing plugs36A of the region except a region where bit lines are to be formed by forming a photoresist layer pattern cover the region where bit lines are to be formed over the sealing layer48, by using the photoresist layer pattern as an etch barrier and performing a blanket etch process. Here, the photoresist layer pattern may have a shape covering a region where bit lines are to be formed. It is more advantageous to form the first pattern49through the above-described method than to form the first pattern49in the hole type or the bar type because the pattern formation process may be simplified in the above-described method.

Herein, according to the embodiment of the present invention, since the first pattern49is formed by selectively etching the sealing layer48, the first etch stop layer41, the isolation layer33and the gate sealing layer40, the sidewalls of the first pattern49may be formed vertically, and the upper surface of the landing plugs36A in the region where storage node contact plugs are to be formed may be opened so as to provide a sufficient contact area. Also, since the process of forming the first pattern49may be simplified, the landing plugs36A to be coupled with bit lines may be prevented from being exposed due to causes such as misalignment occurring during a process for forming storage node contact holes. In other words, a short is prevented from being formed between storage node contact plugs and the landing plugs36A coupled with bit lines.

Referring toFIG. 4G, a second etch stop layer50(e.g., an insulation layer) is formed with a uniform thickness along the surface of the resulting structure including the first pattern49. The second etch stop layer50protects the lower structure from being damaged during a subsequent storage node contact hole formation process and operates as an etch stop. The second etch stop layer50may be formed to have a thickness ranging from approximately 50 Å to approximately 200 Å, and it may be formed of a material having an etch selectivity with respect to the sealing layer48. For example, the second etch stop layer50may be a nitride layer.

Subsequently, a first inter-layer dielectric layer51is formed over the substrate31including the first pattern49in such a manner that the first inter-layer dielectric layer51covers the peripheral gates46, and a planarization process is performed until the peripheral gate hard mask layer45is exposed. The first inter-layer dielectric layer51may be an oxide layer or it may be formed of boro-phospho silicate glass (BPSG) or a spin-on dielectric (SOD) substance, which has excellent flow characteristics. The planarization process may be Chemical Mechanical Polishing (CMP) process.

Subsequently, a second inter-layer dielectric layer52is formed over the first inter-layer dielectric layer51. The second inter-layer dielectric layer52provides the cell region with a sufficient height to allow formation of bit lines. The second inter-layer dielectric layer52may be formed of the same material as the first inter-layer dielectric layer51to facilitate a subsequent process. Also, the second inter-layer dielectric layer52may be formed of a material whose layer density is higher than that of the first inter-layer dielectric layer51to effectively prevent the profile of sidewalls from being deformed and to present a short from being formed between the sidewalls during the subsequent process for forming storage node contact holes and a subsequent process for forming a damascene pattern for bit lines. For example, the second inter-layer dielectric layer52may be an oxide layer, such as a High-Density Plasma (HDP) oxide layer or a tetra ethyl ortho silicate (TEOS) layer.

When the height of the peripheral gates46is low as described above, an inter-layer dielectric layer (51and52) may be formed through a series of processes of forming the first inter-layer dielectric layer51and then performing a planarization process to enhance the thickness stability of the first inter-layer dielectric layer51and through forming the second inter-layer dielectric layer52. When the height of the peripheral gates46is sufficiently high, the inter-layer dielectric layer (51and52) may be formed by performing the formation of a dielectric layer just once and performing a planarization process.

Referring toFIG. 4H, a line-type second pattern53which is extended in a direction parallel to buried gates and coupled with the first pattern49(for example, an outline of contact holes previously formed by second hard mask pattern37inFIG. 4Dbefore being removed during the formation of the first pattern) is formed by selectively etching the first inter-layer dielectric layer51and the second inter-layer dielectric layer52until the second etch stop layer50is exposed. As a result, storage node contact holes formed of the first pattern49and the second pattern53are formed (seeFIGS. 5C and 5D), where the second etch stop layer50will also be removed subsequently.

In forming the second pattern53as a line type by etching the first inter-layer dielectric layer51and the second inter-layer dielectric layer52, process margins and stability may be improved, where the space for storage node contact plugs70are formed in two etching steps (that is, one for the first pattern and one for the second pattern) and a slant in forming for storage node contact plugs70may be reduced.

Subsequently, the landing plugs36A of a region where storage node contact plugs are to be formed are exposed by selectively removing the second etch stop layer50that is exposed through the line-type second pattern53. The line-type second pattern53disposed in a region where bit lines are to be formed has an etch process stop at the first etch stop layer41. This is to protect the landing plugs36A disposed in the region where bit lines are to be formed from being damaged during the storage node contact hole formation process or to prevent a short from being formed between the landing plugs36A and storage node contact holes.

According to the embodiment of the present invention, sufficient contact area may be secured between the storage node contact plugs and the landing plugs36A due to the presence of the first pattern49even if the sidewalls of the line-type second pattern53may be slightly slanted due to the etch characteristics during the process of forming the line-type second pattern53.

Referring toFIG. 4I, a conductive layer54for storage node contact plugs filling the storage node contact holes, each of which is formed of the first pattern49and the line-type second pattern53, are formed. The storage node contact plug-forming conductive layer54may be a polysilicon layer.

Here, since the first etch stop layer41remains in the lower portion of the line-type second pattern53disposed in the region where bit lines are to be formed, a short may be prevented from being formed between the storage node contact-plug-forming conductive layer54and the landing plugs36A.

Referring toFIG. 43, the landing plugs36A are selectively exposed by selectively etching the storage node contact-plug-forming conductive layer54, the second inter-layer dielectric layer52, the first inter-layer dielectric layer51, the second etch stop layer50, the sealing layer48, the first etch stop layer41, the second hard mask pattern37, and the gate sealing layer40. Accordingly, line-type damascene pattern55extended in a direction crossing the direction that the buried gates are extended is formed. Here, portions of the line-type damascene pattern55form storage node contact plugs54A.

Referring toFIG. 4K, bit line spacers56are formed on the sidewalls of the line-type damascene pattern55. The bit line spacers56may be a single layer selected from the group consisting of an oxide layer, a nitride layer, and an oxynitride layer, or a stacked layer including more than two of the foregoing layers.

Meanwhile, an etching process is performed until the first etch stop layer41is exposed during the process of forming the line-type damascene pattern55, and the landing plugs36A under the second hard mask pattern37may be exposed by removing the sealing layer48and the second hard mask pattern37while forming the bit line spacers56at the same time.

Subsequently, bit lines57filling a portion of the line-type damascene pattern55are formed. The bit lines57may be formed of a metallic layer. Here, an ohmic contact layer (not shown) may be formed between the bit lines57and the landing plugs36A.

Subsequently, a bit line sealing layer58filling the other portion of the line-type damascene pattern55is formed over the bit lines57. The bit line sealing layer58may be a single layer selected from the group consisting of an oxide layer, a nitride layer, and an oxynitride layer, or a stacked layer including more than two of the foregoing layers.

The semiconductor device fabrication method in accordance with the embodiment of the present invention may improve the process margins of the storage node contact plugs54A formation process, prevent a short from being formed between the landing plugs36A coupled with the bit lines57and the storage node contact plugs54A, and secure a sufficient contact area between the landing plugs36A and the storage node contact plugs54A by forming the storage node contact holes from the first pattern49and the line-type second pattern53. In addition, the semiconductor device fabrication method in accordance with the embodiment of the present invention may increase the contact margin between storage nodes which are to be formed through a subsequent process and the storage node contact plugs54A.

According to the semiconductor device fabrication method in accordance with an embodiment of the present invention, a short between the landing plugs coupled with bit lines and storage node contact plugs may be prevented from being formed by dividing storage node contact holes into a first pattern and a second pattern and providing storage node contact plugs including a pillar pattern and a line pattern. Further, contact margins of the storage node contact plugs may be improved.