Semiconductor memory device having insulation patterns and cell gate patterns

Semiconductor memory devices and methods of forming semiconductor memory devices are provided. The methods may include forming insulation layers and cell gate layers that are alternately stacked on a substrate, forming an opening by successively patterning through the cell gate layers and the insulation layers, and forming selectively conductive barriers on sidewalls of the cell gate layers in the opening.

CROSS-REFERENCE TO RELATED APPLICATIONS

This U.S. nonprovisional patent application claims priority under 35 U.S.C. §119 of Korean Patent Application 10-2008-137864, filed on Dec. 31, 2008, the entire contents of which are hereby incorporated by reference.

BACKGROUND

Various embodiments relate to semiconductor devices and methods of forming the same, and, more particularly, to semiconductor memory devices and methods of forming the same.

In semiconductor devices, the semiconductor memory device can store digital data. As electronics industries and semiconductor industries advance, high integration of the semiconductor memory device is increasingly required. For instance, the development of mobile electronics equipment such as a laptop computer, a mobile phone, a digital camera, or MP3 player increasingly demands that the semiconductor memory device be capable of storing more data. In order to satisfy user demands, a more integrated semiconductor memory device is required.

Generally, high integration of the semiconductor memory device is achieved by decreasing a minimum line width of the fine patterns of fabricated devices. By decreasing two-dimensionally the minimum line width of the fine patterns, memory cells may be more highly integrated in a limited area. However, the ability to decrease the minimum line width is limited due to various factors (e.g., limitations of the photolithography process). Furthermore, the decrease in the line width of the fine patterns results in characteristic deterioration of the fine patterns and reliability deterioration. A semiconductor memory device that can overcome these problems is desired.

SUMMARY

Various embodiments are directed to a highly integrated semiconductor memory device and methods of forming the highly integrated semiconductor memory device.

Various embodiments are also directed to a highly integrated three-dimensional semiconductor memory device and methods of forming the highly integrated three-dimensional semiconductor memory device.

Various embodiments are also directed to a semiconductor memory device having improved reliability and methods of forming the semiconductor memory device.

Various embodiments of the present invention provide methods of forming a semiconductor memory device, including: forming insulation layers and cell gate layers that are alternately stacked on a substrate; forming an opening by successively patterning through the cell gate layers and the insulation layers; forming conductive barriers on sidewalls of the cell gate layers in the opening by carrying out a nitridation process; forming sequentially a blocking insulation layer, a charge storage layer, and a tunnel insulation layer on sidewalls of the insulation layers and sidewalls of the conductive barriers in the opening; and forming an active pattern extending upward from the substrate in the opening.

In some embodiments, the cell gate layers may contain metals, and the conductive barriers may contain metal nitrides.

In some embodiments, the methods may further include carrying out a metallization process on the cell gate layers exposed in the opening before carrying out the nitridation process. In this case, the cell gate layers may contain doped Group 4A elements, and metallized parts of the cell gate layers may be formed of Group 4A element-metal compounds.

In some embodiments, carrying out the metallization process may include: forming a metal layer coming in contact with the sidewalls of the cell gate layers exposed in the opening; reacting the metal layer to the cell gate layers; and removing an unreacted metal layer.

In some embodiments, the nitridation process may be carried out on the metallized parts of the cell gate layers, and the conductive barriers may contain Group 4A element-metal nitrides.

In some embodiments, the methods may further include forming undercut regions by recessing sideward the sidewalls of the cell gate layers in the opening as compared to the sidewalls of the insulation layers, before carrying out the nitridation process.

In some embodiments, each of the conductive barriers, at least part of the blocking insulation layer, and at least part of the charge storage layer may be formed in each undercut region.

In some embodiments, the methods may further include removing the charge storage layer outside at least the undercut region before forming the active pattern.

In some embodiments, the tunnel insulation layer may be formed after removing the charge storage layer outside the undercut region.

In some embodiments, the opening may form a hole, and the cell gate layers may be formed to have a planar surface.

In some embodiments, the opening may form a groove, and the cell gate layers may form a line extending in one direction in parallel with an upper surface of the substrate.

Other embodiments of the present invention provide a semiconductor memory device including: insulation patterns and cell gate patterns that are alternately stacked on a substrate; an active pattern disposed on the substrate and extending upward along sidewalls of the insulation patterns and sidewalls of the cell gate patterns; a charge storage layer interposed between the sidewall of the cell gate pattern and the active pattern; a blocking insulation layer interposed between the sidewall of the cell gate pattern and the charge storage layer; a tunnel insulation layer interposed between the charge storage layer and the active pattern; and a conductive barrier interposed between the blocking insulation layer and the sidewall of the cell gate pattern and containing nitrogen.

In other embodiments, the cell gate pattern may contain metals, and the conductive barrier may contain metal nitrides. In some cases, the cell gate pattern and the conductive barrier may contain the same metals.

In other embodiments, a part of at least the cell gate pattern coming in contact with the conductive barrier may contain Group 4A element-metal compounds, and the conductive barrier may contain Group 4A element-metal nitrides. In some cases, the Group 4A element-metal compounds and the conductive barrier may contain the same Group 4A elements and the same metals.

In other embodiments, the conductive barrier may be recessed sideward as compared to the sidewalls of the insulation patterns to define undercut regions. In some cases, the charge storage layers may be disposed in the undercut regions, respectively, and the charge storage layers disposed in adjacent undercut regions may be isolated from each other.

In other embodiments, the tunnel insulation layer may extend into successive undercut regions to be disposed between the charge storage layers that are isolated from each other and the active pattern.

In other embodiments, the active pattern may be disposed in a hole penetrating successively through the insulation patterns and the cell gate patterns, and the cell gate patterns may have a planar surface.

In other embodiments, the cell gate patterns may form lines extending along one direction in parallel with an upper surface of the substrate.

DETAILED DESCRIPTION OF EMBODIMENTS

Various embodiments of the present invention will be described below in more detail with reference to the accompanying drawings. The present invention may, however, be embodied in different forms and should not be constructed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the thicknesses of layers and/or regions may have been exaggerated for clarity. It will be understood that when a layer is referred to as being “on” another layer, it may be directly on the other layer or intervening layers may be present. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. Like numbers refer to like elements throughout the specification.

FIG. 1is a plan view illustrating a semiconductor memory device according to some embodiments of the present invention,FIG. 2Ais a cross-sectional view taken along a line I-I′ ofFIG. 1, andFIG. 2Bis a cross-sectional view taken along a line II-II′ ofFIG. 1.

Referring toFIGS. 1 and 2A, a semiconductor substrate100(“substrate”) may include a memory cell region A and a connection region B. Memory cells are disposed in the memory cell region B. The substrate100may further include a peripheral circuit region (not illustrated) in which peripheral circuits are disposed to operate the memory cells. Structures to connect the memory cells to the peripheral circuits may be disposed in the connection region B.

A well region102, which is doped with a first-conductive-type dopant, is disposed in the memory cell region A. A common source region104, which is doped with a second-conductive-type dopant, is disposed in the well region102. An upper surface of the common source region104may be the same height as that of the substrate100. The well region102may extend to the connection region B. Furthermore, the common source region104may also extend to the connection region B. The first-conductive-type dopant may be of inverse type to the second-conductive-type dopant. For example, the first-conductive-type dopant may be p-type dopant, while the second-conductive-type dopant may be n-type dopant. Conversely, the first-conductive-type dopant may be n-type dopant, while the second-conductive-type dopant may be p-type dopant.

A plurality of insulation patterns115and a plurality of cell gate patterns120may be alternately stacked on the substrate100of the memory cell region A. The cell gate patterns120may have a planar surface. A first selection gate pattern110is interposed between the lowest one of the cell gate patterns120and the substrate100. Like the cell gate patterns120, the first selection gate pattern110may also have a planar surface. The lowest one of the insulation patterns115is interposed between the lowest one of the cell gate patterns120and the first selection gate pattern110. A base insulation layer106is interposed between the first selection gate pattern110and the substrate100. A second selection gate pattern130is disposed on the uppermost one of the insulation patterns115. The second selection gate patterns130extend in parallel with each other along a first direction. The first direction is along an X-axis inFIG. 1. The second selection gate patterns130may be spaced apart from each other at regular intervals in a second direction vertical to the first direction (X-axis). The second direction is along a Y-axis inFIG. 1.

The flat-shaped cell gate patterns120and first selection gate pattern110may extend in a transverse direction, thereby being disposed on the substrate100of the connection region

B. Portions of the gate patterns120and110extending to the connection region B are defined as a connection pad (“CPD”). The CPD extending to the connection region B will be described in detail with reference toFIG. 2B.

Referring toFIGS. 1 and 2B, the insulation patterns115also may extend in the transverse direction, thereby being disposed on the connection region B. The insulation patterns115extending to the connection region B are interposed between the CPDs to make the CPDs insulated. As the height of the CPDs increases in the connection region B, the plane area of the CPDs may gradually be reduced. In addition, the CPDs may include overlapped regions. For this reason, the CPDs may be formed in a staircase structure. The CPD of the first selection gate pattern110has the largest plane area, while the CPD of the uppermost one of the cell gate patterns120has the smallest plane area. The CPDs may have a staircase structure that progresses upward in the second direction (Y-axis). That is, the CPDs may have a staircase structure that progresses upward along one side of the gate patterns110,120, and130. This can minimize the plane area of the connection region B.

If the CPDs have the staircase structure that progresses upward in the direction farther away from the gate patterns110,120and130, the plane area of the CPDs may increase. However, according to some embodiments of the present invention, the CPDs have the staircase structure that progresses upward along one side of the gate patterns110,120, and130, thereby minimizing the plane area of the connection region B.

Referring toFIGS. 1,2A, and2B, a first interlayer insulation layer135may be disposed on the entire surface of substrate100. The first interlayer insulation layer135covers the gate patterns110,120, and130. Moreover, the first interlayer insulation layer135covers the CPDs.

An opening140may penetrate the first interlayer insulation layer135, the second selection gate pattern130, the insulation patterns115, the cell gate patterns120, the first selection gate pattern110, and the base insulation layer106in succession, and an active pattern165may be disposed in the opening140. The active pattern165is disposed on the substrate100in the opening140to extend upwardly along sidewalls of the gate patterns110,120, and130and sidewalls of the insulation patterns115. The opening140may be a form of hole, as illustrate inFIG. 1. In the memory cell region, a plurality of openings140may two-dimensionally be arranged along rows and columns. A plurality of active patterns165is disposed in the plurality of openings140. As illustrated inFIG. 1, the opening140may have a square planar shape. Alternatively, the opening140may have various shapes, for example, planar circle, oval, and polygon.

Referring toFIGS. 2A and 2B, the active pattern165may be formed of Group 4A (or Group 14) elements of a periodic table. For instance, the active pattern165may be formed of silicon, germanium, or silicon-germanium. The active pattern165may have an undoped state or a doped state with the first-conductive-type dopant. The active pattern165may be a form of pipe whose inside is empty. The active pattern165adjacent to a bottom of the opening140may have a closed state, while the active pattern165adjacent to an upper end of the opening140may have an opened state. A filling insulation pattern170may fill the inside of the active pattern165. Alternatively, the active pattern165may be a form of pillar that fills the opening140. When the active pattern165is the form of pillar, the filling insulation pattern170may be omitted.

A drain region175, which is doped with a second-conductive-type dopant, is disposed at the upper end of the active pattern165. The lower surface of the drain region175may have a height close to the upper surface of the second selection gate pattern130. The lower end of the active pattern165comes in contact with the common source region104. Furthermore, the active pattern165may come in contact with the well region102in addition to the common source region104. The opening140extends downwardly to penetrate the common source region104, and the active pattern165also extends downwardly to come in contact with the well region102.

A charge storage layer157may be interposed between a sidewall of the cell gate pattern120in the opening140and the active pattern165. A blocking insulation layer155is interposed between the charge storage layer157and the sidewall of the cell gate pattern120, and a tunnel insulation layer160is interposed between the charge storage layer157and the active pattern165. The charge storage layer157may include insulating materials having traps capable of storing charges. For example, the charge storage layer157may include nitride, oxynitride, metal oxide (e.g., hafnium oxide and so on), and/or insulator including nano dots. The nano dots may include metals or Group 4A elements. The tunnel insulation layer160may include at least one selected from oxide, nitride, and oxynitride. The blocking insulation layer155may include the same insulation material as the tunnel insulation layer160or the insulation material having a higher dielectric constant than the tunnel insulation layer160. For example, the blocking insulation layer155may include a single-layered or multi-layered insulation metal oxide (e.g., aluminum oxide, hafnium oxide, or lanthanum oxide). Alternatively, the blocking insulation layer155may include oxide. When both of the blocking insulation layer155and the tunnel insulation layer160are formed of oxide, the blocking insulation layer155may be thicker than the tunnel insulation layer160. According to some embodiments of the present invention, the blocking insulation layer155may be thicker than the tunnel insulation layer160in effective oxide thickness (“EOT”). Here, the EOT is a value that estimates the thickness of dielectrics having a dielectric constant other than silicon dioxide (SiO2) in terms of silicon dioxide (SiO2). The EOT may be used in estimating the performance of new dielectrics having a different dielectric constant.

The blocking insulation layer155, the charge storage layer157, and the tunnel insulation layer160, which are interposed respectively between the first selection gate pattern110and the active pattern165, may be utilized as a first gate insulation layer of a first selection transistor. Likewise, the blocking insulation layer155, the charge storage layer157, and the tunnel insulation layer160, which are interposed respectively between the second selection gate pattern130and the active pattern165, may be utilized as a second gate insulation layer of a second selection transistor.

As illustrated inFIG. 2A, blocking insulation layers155may extend in parallel with each other, thereby being disposed between the plurality of gate patterns110and the active pattern165. Likewise, the charge storage layer157and the tunnel insulation layer160also extend in parallel with each other, thereby being disposed between the plurality of cell gate patterns120and the active pattern165.

A conductive barrier150may be interposed between the sidewall of the cell gate pattern120in the opening140and the blocking insulation layer155. The conductive barrier150prevents or inhibits the reaction and interaction between the cell gate pattern120and the blocking insulation layer155. The conductive barrier150may include conductive materials having a very low reactivity. For example, the conductive barrier150may include nitrogen. More specifically, the conductive barrier150may include conductive nitride. The cell gate pattern120may include conductive materials having a lower resistivity than the conductive barrier150. For example, the cell gate pattern120may include metal. When the cell gate pattern120includes metal, the conductive barrier150may include metal nitride. Also, the cell gate pattern120and the conductive barrier150may include the same metal. For instance, when the cell gate pattern120includes tungsten, the conductive barrier150may include tungsten nitride. Alternatively, when the cell gate pattern120includes titanium or tantalum, the conductive barrier150may include titanium nitride or tantalum nitride.

The conductive barrier150may be disposed over the sidewall of the cell gate pattern120in the opening140. For example, an interface between the conductive barrier150and the cell gate pattern120may be non-parallel with the upper surface of the substrate100. The interface may substantially be vertical to the upper surface of the substrate100. The conductive barriers150may be isolated from each other.

A first selective-conductive barrier151may be interposed between the sidewall of the first selection gate pattern110in the opening140and the first gate insulation layer155,157and160. The first selective-conductive barrier151may prevent or inhibit the reaction between the first selection gate pattern110and the first gate insulation layer155,157, and160. The first selective-conductive barrier151may include conductive materials having a very low reactivity. For example, the first selective-conductive barrier151may include conductive nitride containing nitrogen. When the first selection gate pattern110includes metal, the first selective-conductive barrier151may include metal nitride containing the same metal as the first selection gate pattern110. Likewise, a second selective-conductive barrier152may be interposed between the sidewall of the second selection gate pattern130in the opening140and the second gate insulation layer155,157and160. The second selective-conductive barrier152may prevent or inhibit a reaction between the second selection gate pattern130and the second gate insulation layer155,157, and160. The second selective-conductive barrier152may include conductive nitride containing nitrogen. When the second selection gate pattern130includes a metal, the second selective-conductive barrier152may include metal nitride containing the same metal as the second selection gate pattern130. The selective-conductive barriers151and152and the conductive barrier150are isolated from each other.

The first and second selection gate patterns110and130may include the same metal nitride as the cell gate pattern120. In this case, the conductive barrier150and the selective-conductive barriers151and152may include the same metal nitride. Alternatively, when the first and second selection gate patterns110and130include metals different from those of the cell gate pattern120, the first and second selective-conductive barriers151and152may include metals different from those of the conductive barrier150. Consequently, the first and second selective-conductive barriers151and152may be different in work function from the conductive barrier150.

A memory cell may include the cell gate pattern120, the conductive barrier150, the blocking insulation layer155, the charge storage layer157, and the tunnel insulation layer160. In addition, the memory cell may include a cell channel region. The cell channel region may include the sidewall of the active pattern165overlapped with the cell gate pattern120. The threshold voltage of the memory cell may be changed by the quantity of charges stored in the charge storage layer157. Using the change of threshold voltage, the memory cell may store data. The memory cell may store 1-bit or multi-bit data according to the quantity of charges stored in the charge storage layer157. The charges stored in the charge storage layer157may be isolated from one another by traps of the charge storage layer157and/or the blocking insulation layer155and the tunnel insulation layer160. Consequently, the memory cell may include nonvolatile characteristics that keep retaining data even though the power supply is interrupted. Therefore, the semiconductor memory device according to the embodiments of the present invention may be a nonvolatile memory device.

The first selection gate pattern110may be provided in a first selection transistor, and the second selection gate pattern130may be provided in a second selection transistor. The first selection transistor may include the first selection gate pattern110, the first selective-conductive barrier151, and the first gate insulation layer155,157and160; and the second selection transistor may include the second selection gate pattern130, the second selective-conductive barrier152, and the second gate insulation layer155,157and160. During the operation of the semiconductor memory device, inversion layers may be formed at the active pattern165between the gate patterns110,120, and130by the fringe field of the gate patterns110,120, and130. By the inversion layers, the selection transistors and the memory cells may be connected to each other in series.

As described above, according to some embodiments of the present invention, the first and second selective-conductive barriers151and152may be different in work function from the conductive barrier150of the cell gate pattern120. Owing to the difference of work function, both characteristics of the first and second selection transistors and characteristics of the memory cell can be optimized. For instance, when the selection transistors and the memory cell are an NMOS type, the work function of the first and second selective-conductive barriers151and152may be larger than that of the conductive barrier150. Consequently, the threshold voltage of the first and second selection transistors may be higher than that of an erased memory cell. This can minimize the amount of off-leakage current to improve reliability of the semiconductor memory device. Therefore, a semiconductor memory device having good characteristics can be provided by adjusting the work function of the selective-conductive barriers151and152and the conductive barrier150.

The first selection transistor, the plurality of memory cells, and the second selection transistor are upwardly stacked along the sidewall of the active pattern165. The first selection transistor, the plurality of memory cells, and the second selection transistor formed at the active pattern165are provided in a vertical-type cell string. A plurality of vertical-type cell strings is arranged on the substrate100of the memory cell region A in rows and columns.

A second interlayer insulation layer180may be disposed on the entire surface of the substrate100. Bit lines190are disposed on the second interlayer insulation layer180of the memory cell region A. The bit lines190intersect the second selection gate patterns130. That is, the bit lines190extend in parallel with each other along the second direction (Y-axis). The bit lines190are electrically connected to the drain regions175through bit line plugs185penetrating the second interlayer insulation layer180. One bit line190may be electrically connected to the plurality of drain regions175arranged in a column along the second direction (Y-axis). By the bit lines190and the second selection gate patterns130intersecting with each other, one of the active patterns165may be selected. Moreover, it may select one memory cell in the cell string of the selected active pattern165by selecting one of the cell gate patterns120.

Meanwhile, connection plugs187successively penetrate the second and first interlayer insulation layers180and135of the connection region B and are connected to the CPDs. According to some embodiments of the present invention, connection wirings192may be disposed on the second interlayer insulation layer180of the connection region B and connected to the connection plugs187. The connection wirings192extend to electrically connect with peripheral circuits of the peripheral circuit region.

The above-described semiconductor memory device may have a three-dimensional structure including the vertical-typed cell strings, thereby achieving high integration.

Furthermore, the conductive barrier150including nitrogen is disposed between the cell gate pattern120and the blocking insulation layer155. The conductive barrier150is disposed over the sidewall of the cell gate pattern120, thereby preventing or inhibiting the reaction between the cell gate pattern120and the blocking insulation layer155. For this reason, it can realize the semiconductor memory device having good reliability.

When the cell gate pattern including metal comes in contact with the blocking insulation layer, the metal of the cell gate pattern may be diffused into the blocking insulation layer. This makes the characteristics of the blocking insulation layer deteriorate to reduce the reliability of the semiconductor memory device. However, according to some embodiments of the present invention, since the conductive barrier150is disposed between the cell gate pattern120and the blocking insulation layer155, it may prevent or inhibit the reaction between the cell gate pattern120and the blocking insulation layer155to result in the semiconductor memory device having good reliability.

Next, some embodiments of the semiconductor memory device of the present invention will be described with reference toFIGS. 3A to 3C. These examples are similar to the semiconductor memory device described with reference toFIGS. 2A and 2B. Accordingly, with respect to the duplicated technical features, the description will be omitted hereinafter for brevity. The same reference numerals can be denoted to the same component as inFIGS. 2A and 2B.

FIG. 3Ais a cross-sectional view taken along the line I-I′ ofFIG. 1to explain some embodiments of the semiconductor memory device of the present invention.

Referring toFIG. 3A, cell gate patterns120may include Group 4A elements doped with dopants. For instance, the cell gate patterns120may include doped silicon, doped germanium, and/or doped silicon-germanium. The first and second selection gate patterns110and130may also include Group 4A elements doped with dopants. For example, the first and second selection gate patterns110and130may include doped silicon, doped germanium, and/or doped silicon-germanium.

A conductive barrier150amay be interposed between the cell gate pattern120and the blocking insulation layer155. A first selective-conductive barrier151amay be interposed between the first selection gate pattern110and the first gate insulation layer155,157and160, and a second selective-conductive barrier152amay be interposed between the second selection gate pattern130and the second gate insulation layer155,157and160. The conductive barriers151a,152a, and153amay include nitrogen.

Likewise, a portion147of the first selection gate pattern110adjacent to at least the first selective-conductive barrier151a may include Group 4A element-metal compounds, and the first selective conductive barrier151a may include Group 4A element-metal nitrides. A portion of the second selection gate pattern130adjacent to at least the second selective-conductive barrier152amay include Group 4A element-metal compounds, and the second selective conductive barrier152amay include Group 4A element-metal nitrides. The entirety of the first selection gate pattern110may be formed of Group 4A element-metal compounds. In addition, the entirety of the second selection gate pattern130may be formed of Group 4A element-metal compounds. The first and second selection gate patterns110and130may include the same metal as the cell gate pattern120. Likewise, the conductive barriers150a,151a, and152amay include the same metal. The first and second selection gate patterns110and130may include the same Group 4A elements as the cell gate pattern120. Also, the conductive barriers150a,151a, and152amay include the same Group 4A elements.

According to some embodiments of the present invention, as illustrated inFIG. 3A, the entirety of the second selection gate pattern130may be formed of Group 4A element-metal compounds, and the first selection gate pattern110and the cell gate pattern120may partially be formed of Group 4A element-metal compounds.

FIG. 3Bis a cross-sectional view taken along the line I-I′ ofFIG. 1to explain some embodiments of the semiconductor memory device of the present invention.

Referring toFIG. 3B, sidewalls of the cell gate patterns120formed in the opening140may be recessed sideward as compared to sidewalls of the insulation patterns115. For this reason, undercut regions143may be defined. The conductive barrier150may be disposed in the undercut region143and disposed on the recessed sidewall. The conductive barrier150may substantially cover over the recessed sidewall of the cell gate pattern120. Moreover, a blocking insulation layer155a, a charge storage layer157a, and a tunnel insulation layer160a, which are formed between the conductive barrier150and the active pattern165, may also be disposed in the undercut region143. The charge storage layers157amay be isolated from each other and disposed in the plurality of undercut regions143formed within the opening140. Likewise, the blocking insulation layers155amay be isolated from each other and disposed in the plurality of undercut regions143. Furthermore, the tunnel insulation layers160amay be isolated from each other and disposed in the plurality of undercut regions143. The blocking insulation layer155a, the charge storage layer157a, and the tunnel insulation layer160amay conformally be disposed along an inner side of the undercut region143. In such cases, the active pattern165may include a protrusion166extending in the undercut region143. The charge storage layer157amay be formed of the same materials as the charge storage layer157described with reference toFIG. 2AandFIG. 2B.

Sidewalls of the first and second selection gate patterns110and130formed in the opening140may be recessed sideward as compared to a sidewall of a base insulation layer106, sidewalls of insulation patterns115, and sidewalls of a first interlayer insulation layer135. For this reason, the undercut regions143may also be defined by sidewalls of the first and second selection gate patterns110and130. The first and second selective-conductive barriers151and152may be disposed in the undercut region143defined by sidewalls of the first and second selection gate patterns110and130. In addition, the first gate insulation layer155a,157aand160ainterposed between the first selective-conductive barrier151and the active pattern165may be disposed in the undercut region143. The second gate insulation layer155a,157aand160ainterposed between the second selective-conductive barrier152and the active pattern165may be disposed in the undercut region143. The first and second gate insulation layers155a,157aand160amay include the same materials as the blocking insulation layer155a, the charge storage layer157a, and the tunnel insulation layer160a. The first gate insulation layer155a,157aand160adisposed in the undercut region143may be isolated from the blocking insulation layer155a, the charge storage layer157a, and the tunnel insulation layer160adisposed in the above adjacent undercut region143. Likewise, the second gate insulation layer155a,157aand160adisposed in the undercut region143may be isolated from the blocking insulation layer155a, the charge storage layer157a, and the tunnel insulation layer160adisposed in the below adjacent undercut region143.

The modification example ofFIG. 3Aand the modification example ofFIG. 3Bmay be combined with each other. For example, the cell gate patterns120ofFIG. 3Bmay include doped Group 4A elements, and a portion of the cell gate patterns120adjacent to at least the conductive barrier150may include Group 4A element-metal compounds. In such cases, the conductive barrier150may include Group 4A element-metal nitrides. Likewise, the first and second selection gate patterns110and130ofFIG. 3Bmay include Group 4A elements. In such cases, portions of the selection gate patterns110and130adjacent to at least the selective-conductive barriers151and152may include Group 4A element-metal compounds, and the selective-conductive barriers151and152may include Group 4A element-metal nitrides.

FIG. 3Cis a cross-sectional view taken along the line I-I′ ofFIG. 1to explain further embodiments of the semiconductor memory device of the present invention.

Referring toFIG. 3C, the conductive barrier150, the blocking insulation layer155a, and the charge storage layer157amay be disposed in the undercut region143close to the cell gate pattern120. Like the modification example ofFIG. 3B, the blocking insulation layer155aand the charge storage layer157aare disposed in the undercut region143and may be isolated from the adjacent blocking insulation layer155aand charge storage layer156adisposed in the above and/or below adjacent undercut region143. The tunnel insulation layer160upwardly and/or downwardly extends to directly connect with the tunnel insulation layer160disposed in the adjacent undercut region143. That is, one tunnel insulation layer160extends into successive undercut regions and may be disposed between a plurality of charge storage layers157aisolated from each other and the active pattern165. In some embodiments, the charge storage layer157amay be formed of the same materials as the charge storage layer157described with reference toFIGS. 2A and 2B. Alternatively, the charge storage layer157amay be formed of Group 4A elements (e.g., silicon, germanium, or silicon-germanium) or conductors. The blocking insulation layer155aand the tunnel insulation layer160may be formed of the same materials as the blocking insulation layer155and the tunnel insulation layer160described with reference toFIGS. 2A and 2B.

As illustrated inFIG. 3C, the tunnel insulation layer160may extend so as to be interposed between the first and second selection gate patterns110and130and the active pattern165. The tunnel insulation layer160may be included in first and second gate insulation layers155a,157aand160a. Like some embodiments ofFIG. 3B, with respect to the gate patterns110,120, and130including Group 4A element-metal compounds and the conductive barriers150a,151a, and152aincluding Group 4A element-metal nitrides inFIG. 3A, it may be applicable to the semiconductor memory device ofFIG. 3C.

Methods of forming the semiconductor memory device according to some embodiments of the present invention will now be described with reference to drawings.

FIGS. 4A to 4Eare process cross-sectional views taken along the line I-I′ ofFIG. 1to explain methods of forming the semiconductor memory device according to some embodiments of the present invention; andFIGS. 5A to 5Care process cross-sectional views taken along the line II-II′ ofFIG. 1to explain methods of forming pads in a connection region of the semiconductor memory device according to some embodiments of the present invention.

Referring toFIGS. 1 and 4A, a well region102may be formed by injecting the first-conductive-type dopants into the substrate100of the memory cell region A. The well region102may also be formed in the connection region B. A common source region104is formed by injecting the second-conductive-type dopants into the well region102.

Subsequently, a base insulation layer106may be formed on the substrate100, and a first selection gate layer110may be formed on the base insulation layer106. The base insulation layer106may be, for example, an oxide layer, a nitride layer, and/or an oxynitride layer. Insulation layers115and cell gate layers110are alternately stacked on the first selection gate layer110. A second insulation layer130may be formed on the uppermost one of the insulation layers115. Before forming the base insulation layer106, transistors and/or resistors may be formed in a peripheral region (not shown) to configure peripheral circuits. Second selection patterns130may be formed in the memory cell region A by patterning the second selection gate layer130. The second selection gate patterns130may extend along one direction in parallel with each other. A first selection gate pattern110, alternately stacked insulation patterns115, and cell gate patterns120may be formed by successively patterning the cell gate layers120, the insulation layers115, and the first selection gate layer110. The cell gate patterns120, the insulation patterns115, and the first selection gate pattern110may be formed on the base insulation layer106of the memory cell region A and the connection region B.

After forming the second selection gate pattern130, the first selection gate pattern110and the cell gate patterns120may be formed. Alternatively, after forming the first selection gate pattern110and the cell gate patterns120, the second selection gate pattern130may be formed. The insulation patterns115may be formed of such as an oxide, a nitride, and/or an oxynitride. The cell gate patterns120may include metal. For example, the cell gate patterns120may be formed of tungsten, titanium, or tantalum. The first and second selection gate patterns110and130may include metals. The first and second selection gate patterns110and130may include the same metals as the cell gate patterns120. On the contrary, the first and second selection gate patterns110and130may include metals different from those of the cell gate patterns120.

Next, the CPDs of the connection region B may be formed. Methods of forming the CPDs will be described with reference toFIGS. 5A to 5C.

Referring toFIGS. 1,2B and5A, the CPDs to be formed in the connection region B may be divided into a first group and a second group. The number of layers of the first-group CPDs may be equal to that of the second-group CPDs. Alternatively, the number of layers of the first-group CPDs may be as small as 1 or as large as 1 as compared to that of the second-group CPDs. When the total number of layers to be formed in the connection region B is an even number, the number of layers of the first-group CPDs may be equal to that of the second-group CPDs. When the total number of layers to be formed in the connection region B is an odd number, the number of layers of the first-group CPDs may be unequal to that of the second-group CPDs. Alternatively, the number of layers of the first-group CPDs may be as small as 1 or as large as 1 as compared to that of the second-group CPDs.

For convenience of description,FIG. 2Billustrates five-layered CPDs. With five layers, the number of layers of the first-group CPDs may be designated as 2 and the number of layers of the second-group CPDs may be designated as 3. Naturally, it should be understood that the embodiments are not limited thereto. For example, the number of layers of the first-group CPDs may be designated as 3 and the number of layers of the second-group CPDs may be designated as 2.

A first photolithography process may be carried out to divide a first region10and a second region20in the connection region B. A first mask pattern133amay be formed by the first photolithography process to cover gate patterns110and120of the first region10divided in the connection region. Also, gate patterns110and120of the second region20may be exposed. The first-group CPDs may be formed in the first region10, while the second-group CPDs may be formed in the second region20. The first mask pattern133amay cover over the memory cell region A.

Using the first mask pattern133aas an etching mask, a first etching process may be carried out. The gate pattern120, which may be formed by the uppermost pad CPD of the second-group CPDs, may be exposed by the first etching process. A first patterning process may include the first photolithography process and the first etching process.

Referring toFIGS. 1,2B and5B, the first-group CPDs may be divided into two subgroups in the same manner as the methods of dividing the CPDs into the first group and the second group. Likewise, the second-group CPDs may be divided into two subgroups by the above-described division. Two groups in the first group may be defined as a first subgroup and a second subgroup, respectively, and two groups in the second group may be defined as a third subgroup and a fourth subgroup. In such embodiments of the present invention, the number of layers in the CPDs of the first, second, and third subgroups may be 1, and the number of layers in the CPDs of the fourth subgroup may be 2.

The number of layers of the first-subgroup CPDs may be equal to that of the second-subgroup CPDs. Alternatively, the number of layers of the first-subgroup CPDs may be as small as 1 or as large as 1 as compared to that of the second-subgroup CPDs. Likewise, the number of layers of the third-subgroup CPDs may be equal to that of the fourth-subgroup CPDs. Alternatively, the number of layers of the third-subgroup CPDs may be as small as 1 or as large as 1 as compared to that of fourth-subgroup CPDs.

Similarly, the first region10may be divided into two sub-regions11and12, and the second region20may be divided into two sub-regions30and40. That is, the first region10may be divided into a first sub-region11in which the first-subgroup CPDs are formed and a second sub-region12in which the second-subgroup CPDs are formed; and the second region20may be divided into a third sub-region30in which the third-subgroup CPDs are formed and a fourth sub-region40in which the fourth-subgroup CPDs are formed.

After carrying out the first patterning process, the first mask pattern133amay be removed. Sequentially, a second mask pattern133bmay be formed by carrying out a second photolithography process. The second mask pattern133bmay cover one sub-region of the first region10and one sub-region of the second region20. Also, gate patterns may be exposed, located in the other sub-region of the first region10and the other sub-region of the second region20. For example, the first and third sub-regions11and30may be covered with the second mask pattern133b, and the second and fourth sub-regions12and40may be exposed.

Using the second mask pattern133bas an etching mask, a second etching process may be carried out. The second etching process etches gate patterns located in the second sub-region12and the fourth sub-region40. Consequently, the first, second, third, and fourth-subgroup CPDs are formed with a single layer, respectively. A second patterning process may include the second photolithography process and the second etching process.

Referring toFIGS. 1 and 5C, the second mask pattern133bmay be removed. The number of layers of the fourth-subgroup CPDs may be 2. Accordingly, the fourth-subgroup CPDs may be divided into two subgroups once more. Likewise, the fourth sub-region40may be divided into two sub-regions41and42, each corresponding to two subgroups in the fourth subgroup. A third mask pattern133cmay be formed by carrying out a third photolithography process to cover one sub-region41in the fourth sub-region40. Also, gate patterns may be exposed, located at the other sub-region42in the fourth sub-region40. The third mask pattern133cmay cover the previously formed CPDs. Moreover, the third mask pattern133cmay cover the memory cell region A. A third etching process is carried out by using the third mask pattern133cas an etching mask. Consequently, two CPDs are formed in the fourth sub-region40. A third patterning process includes the third photolithography process and the third etching process.

As described above, after patterning it by dividing the connection region B into the first region10and the second region20, the first region10and the second region20may be divided into two sub-regions, respectively, thereby patterning one sub-region12in the first region10and one sub-region40in the second region20at the same time. Next, each of the four sub-regions11,12,30and40is divided into two smaller sub-regions, and two smaller sub-regions included in each of the four sub-regions11,12,30and40are simultaneously patterned. By repeatedly performing these manners, all of the CPDs may be formed in the connection region B by the number of patterning processes smaller than the total number of layers of the CPDs.

When the total number X of layers of the CPDs formed in the connection region B is 2n-1<X≦2n(n is a natural number), the number of patterning processes is ‘n’. For example, when the total number of layers of the CPDs is 32, the number of patterning processes is 5. That is, when the total number of layers of the CPDs is 32, all of the CPDs may be formed by performing the patterning processes five times. As an alternate example, when the total number X of layers of the CPDs is 64, it may form all 64-layered CPDs by performing the patterning processes six times.

Subsequently, referring toFIG. 4B, the first interlayer insulation layer135may be formed on the entire surface of the substrate100. The first interlayer insulation layer135covers the second selection gate patterns130and the CPDs (CPDs ofFIG. 2B). The first interlayer insulation layer135may be, for example, an oxide layer, a nitride layer, and/or an oxynitride layer.

The opening140may be formed by successively patterning the first interlayer insulation layer135, the second selection gate pattern130, the insulation patterns115, the cell gate patterns120, the first selection gate pattern110, and the base insulation layer106. The opening140may be a form of hole. The common source region104may be exposed in the opening140. The hole-shaped openings140may be formed on the substrate100of the memory cell region A so as to be spaced apart from each other in parallel with each other. The hole-shaped openings140may be two-dimensionally arranged along rows and columns.

Referring toFIG. 4C, a nitridation process may be carried out in the opening140. More specifically, the nitridation process is carried out on sidewalls of the cell gate patterns120exposed in the opening140. For this reason, conductive barriers150are formed on the sidewalls of the cell gate patterns120in the opening140. During the nitridation process, the sidewalls of the exposed cell gate patterns120react with the supplied nitrogen to form the conductive barriers150. At this time, conductive materials do not form on sidewalls of the insulation patterns115in the opening140. For this reason, the conductive barriers150are electrically isolated from each other. When the cell gate patterns120include metals, the conductive barriers150are formed of metal nitrides. For example, when the cell gate patterns120are formed of tungsten, titanium, or tantalum, the conductive barriers150may be formed of tungsten nitride, titanium nitride, or tantalum nitride. By the nitridation process, a first selective-conductive barrier151and a second selective-conductive barrier152are formed on sidewalls of the first and second selection gate patterns110and130exposed in the opening140, respectively.

The nitridation process may be isotropy. The nitridation process may use nitrogen-containing nitrogen source gas. The nitridation process may use thermally excited nitrogen, plasma-state nitrogen, and/or radical-state nitrogen, which are obtained from the nitrogen-containing nitrogen source gas. The thermally excited nitrogen, plasma-state nitrogen, and/or radical-state nitrogen may be generated inside a process chamber in which the nitridation process is carried out. When the plasma-state nitrogen is generated in the process chamber, a back bias may not be applied to an electrostatic chuck on which the substrate100is mounted. Alternatively, according to some embodiments of the present invention, the plasma-state nitrogen and the radical-state nitrogen are remotely generated at the outside of the process chamber and may be supplied to the inside of the process chamber by diffusion and/or convention. The nitrogen source gas may contain such as a nitrogen (N2) gas, an ammonia (NH3) gas, and/or a nitrogen trifluoride (NF3) gas. The present invention is not limited thereto. The nitrogen source gas may use another gases containing nitrogen.

The conductive barriers150,151, and152may be formed by the nitridation process, thereby being selectively formed on the exposed gate patterns110,120, and130. As a result, it can form the conductive barriers150isolated from each other and the first and second selective-conductive barriers151and152isolated from the conductive barriers150in the opening140. Furthermore, the conductive barriers150,151, and152may be formed over the sidewalls of the gate patterns110,120, and130by the nitridation process.

Before carrying out the nitridation process, the sidewalls of the gate patterns110,120, and130exposed in the opening140may be recessed sideward as compared to the sidewalls of the insulation patterns115. By the recess process, the state of an inner sidewall of the opening140can be controlled. For example, the sidewalls of the conductive barriers150,151, and152may be protruded into the opening140as compared to the sidewalls of the insulation patterns115. By carrying out the recess process before the nitridation process, the sidewalls of the conductive barriers150,151, and152may substantially coplanar with the sidewalls of the insulation patterns115.

Referring toFIG. 4D, the blocking insulation layer155, the charge insulation layer157, and the tunnel insulation layer160may be conformally formed on the entire surface of the substrate having the conductive barriers150,151, and152. For this reason, the blocking insulation layer155, the charge storage layer157, and the tunnel insulation layer160may be formed along the sidewalls of the opening140with a uniform thickness. The blocking insulation layer155, the charge storage layer157, and the tunnel insulation layer160may be formed by an ALD (atomic layer deposition) process.

Subsequently, removing the tunnel insulation layer160, the charge storage layer157, and the blocking insulation layer155formed on the bottom of the opening140may expose the common source region104. The tunnel insulation layer160, the charge storage layer157, and the blocking insulation layer155formed on the bottom of the opening140may be removed by anisotropically etching the entire surface. At this time, the tunnel insulation layer160, the charge storage layer157, and the blocking insulation layer155formed on the top of the opening140may also be removed.

By etching the exposed common source region104, the well region102may be exposed.

Referring subsequently toFIG. 4E, the active pattern165may be formed in the opening140. The active pattern165may include Group 4A elements. For instance, the active pattern165may be formed of silicon, germanium, or silicon-germanium. Methods of forming the active pattern165will now be described. An amorphous active layer may conformally be formed on the substrate100having the opening140. The amorphous active layer has good step coverage. The amorphous active layer comes in contact with the substrate100below the opening140, the well region102being formed thereon. A crystallization process may be carried out on the amorphous active layer. The amorphous active layer may be changed into a poly crystalline active layer by the crystallization process. Alternatively, the amorphous active layer come in contact with the mono crystalline substrate100may be changed into a mono crystalline active layer by the crystallization process. A filling insulation layer may be formed on the active layer to fill the opening140. The active pattern165and the filling insulation pattern170may be formed in the opening140by planarizing the active layer and the filling insulation layer until the first interlayer insulation layer is exposed. The crystallization process may be carried out before or after forming the filling insulation layer.

Alternatively, the active pattern165may also be formed by a selective epitaxial process using the substrate100exposed in the opening140as a seed layer. In such cases, the active pattern165may also be a form of pillar that fills the opening140. When the active pattern165is formed by the epitaxial process, the filling insulation layer may be omitted.

The following methods will be described with reference toFIGS. 1,2A and2B. The drain region175may be formed by supplying a second-conductive-type dopant to the upper end of the active pattern165, and the second interlayer insulation layer180may be formed to cover the entire surface of the substrate100. The bit line plugs185are formed, which penetrate the second interlayer insulation layer180. The bit line plugs185are connected to the drain region175. The connection plugs187are formed, which continuously penetrate the second and first interlayer insulation layers180and135of the connection region B. The connection plugs187and the bit line plugs185may be formed at the same time. The bit line190is formed on the second interlayer insulation layer180of the memory cell region A, thereby being connected to the bit line plugs185. The connection wirings192are formed on the second interlayer insulation layer180of the connection region B, thereby being connected to the connection plugs187. The bit line190and the connection wirings192may be formed at the same time. The plugs185and187may include, for example, tungsten, copper, or aluminum. The bit line190and the connection wirings192may include, for example, tungsten, copper, or aluminum.

Methods of forming the semiconductor memory device illustrated inFIG. 3Awill be described below. These methods may include the methods described with reference toFIGS. 4A and 4B, andFIGS. 5A to 5Cexcept that the gate patterns110,120, and130may include Group 4A doped with dopants.

FIGS. 6A to 6Care process cross-sectional views to explain methods of forming the semiconductor memory device illustrated inFIG. 3A.

Referring toFIGS. 4B and 6A, after forming the opening140, the undercut regions142may be formed by recessing sideward the sidewalls of the gate patterns110,120, and130exposed in the opening140as compared to the sidewalls of the insulation patterns115. The gate patterns110,120, and130may include doped Group 4A elements. For example, the gate patterns110,120, and130may include doped silicon, doped germanium, or doped silicon-germanium.

Referring toFIG. 6B, a metallization process may be carried out on the sidewalls of the gate patterns110,120, and130exposed in the opening140. The metallization process supplies metals into the exposed gate patterns110,120, and130to form at least a part of the gate patterns110,120, and130of metal compounds. By the metallization process, at least a part of the gate patterns110,120, and130may be formed of Group 4A element-metal compounds.

In some embodiments of the metallization process, a metal layer144may be formed on the substrate100to come in contact with the sidewalls of the gate patterns110,120, and130exposed in the opening140. The metal layer144may include cobalt, nickel, or titanium. At least a part of the gate patterns110,120, and130may be formed of the Group 4A element-metal compounds by reacting the metal layer144to the gate patterns110,120, and130. As illustrated inFIG. 6B, the overall second selection gate pattern130may be formed of the Group 4A element-metal compounds. The metal layer144and the gate patterns110,120, and130may be reacted to each other by a thermal process. The method of forming the metal layer144and the reaction process of the metal layer144and the gate patterns110,120, and130may be carried out by an in-situ method or an ex-site method. After finishing the reaction process, unreacted metal layer140is removed. Hereby, the metallization process may be finished.

Metallized parts (that is, parts formed of Group 4A element-metal compounds) of the gate patterns110,120, and130may be increased in volume. Consequently, portions of the undercut regions142may be filled with the metallized parts of the gate patterns110,120, and130.

Before forming the metal layer144, a buffer layer (not shown) may be disposed on the common source region104below the opening140. The buffer layer may be a part of the base insulation layer106. Specifically, in forming the opening140when carrying out the metallization process, the top of the base insulation layer120is removed and the bottom of the base insulation layer120remains. A part of the remained base insulation layer106may be used as a buffer layer. The buffer layer may prevent or inhibit the reaction between the metal layer144and the common source region104. After removing the metal layer144, the buffer layer may be removed.

During the metallization process, the metal layer144and the common source region104below the opening140may be reacted to each other. In such cases, the metallized part of the common source region104may remain. Conversely, the metallized part of the common source region104may be removed by an additional process. Moreover, the metallized part of the common source region104may be removed by the following methods for exposing the well region102.

Referring toFIG. 6C, the unreacted metal layer144may be removed, and then the metallized parts146and147of the gate patterns110,120, and130may be exposed. The conductive barriers150a,151a, and152aare formed by carrying out the nitridation process on the metallized parts146and147of the gate patterns110,120, and130. The nitridation process may be equal to the nitridation process described with reference toFIG. 4C. Due to the nitridation process, the conductive barriers150a,151a, and152amay be formed of Group 4A element-metal nitrides by supplying nitrogen to the metallized parts of the gate patterns110,120, and130. The metallized parts146and147of the gate patterns110,120, and130may have a low resistivity as compared to the conductive barriers150a,151a, and152a.

The conductive barriers150a,151a, and152amay fill the undercut region142. According to some embodiments of the present invention, the formation of the undercut region142may be omitted.

The following methods may be carried out in the same manner as described with reference toFIGS. 4D and 4E, andFIGS. 2A and 2B. The methods may thereby realize the semiconductor memory device ofFIG. 3A.

Next, methods of forming the semiconductor memory device illustrated inFIG. 3Bwill be described with reference to accompanying drawings.

These methods may include the ways described with reference toFIGS. 4A and 4B, andFIGS. 5A to 5C.

FIGS. 7A to 7Care process cross-sectional views to explain methods of forming the semiconductor memory device illustrated inFIG. 3B.

Referring toFIGS. 4B and 7A, after forming the opening140, the undercut regions143may be formed by recessing sideward the sidewalls of the gate patterns110,120, and130exposed in the opening140as compared to the sidewalls of the insulation patterns115. The depth of the undercut region143may be deeper than the undercut region142ofFIG. 6A. The depth of the undercut region143may be a horizontal distance between the recessed sidewalls of the cell gate pattern120and the sidewalls of the insulation pattern115.

Referring toFIG. 7B, the nitridation process is subsequently carried out on the substrate100to form the conductive barriers150,151, and152. The nitridation process is the same as described with reference toFIG. 4C. The conductive barriers150,151, and152are formed in the undercut regions143. Portions of the undercut regions143may be in an empty state. When the gate patterns110,120, and130contain metals, the nitridation process may directly be carried out on the recessed sidewalls of the gate patterns110,120, and130. Hereby, the conductive barriers150,151, and152may be formed of metal nitrides.

Alternatively, when the gate patterns110,120, and130contain doped Group 4A elements, the metallization process may be carried out on the recessed sidewalls of the gate patterns110,120, and130before carrying out the nitridation process. The metallization process may be equal to that described with reference toFIG. 6B. In such cases, by carrying out the metallization process and the nitridation process, the conductive barriers150,151, and152may be formed of Group 4A element-metal nitrides. Even in these cases, the conductive barriers150,151, and152may be formed in the undercut regions143, and portions of the undercut regions143may be in an empty state.

Subsequently, the blocking insulation layer155, the charge storage layer157, and the tunnel insulation layer160may be conformally formed on the substrate100in turns. At this time, parts of the blocking insulation layer155, the charge storage layer157, and the tunnel insulation layer160may be formed in the undercut region143. The blocking insulation layer155, the charge storage layer157, and the tunnel insulation layer160may be formed to have a substantially uniform thickness along an inner surface of the opening140and the undercut region143.

A sacrificial layer may be formed on the substrate100to fill the opening140and the undercut region143, and then the sacrificial layer may be planarized until the tunnel insulation layer160disposed on the upper surface of the first interlayer insulation layer135is exposed. Sacrificial patterns162may be formed by anisotropically etching the planarized sacrificial layer to fill the undercut region143.

Referring toFIG. 7C, by using the sacrificial patterns162as an etching mask, the tunnel insulation layer160, the charge storage layer157, and the blocking insulation layer155located outside the undercut regions143may be removed by the isotropic etching. Consequently, the blocking insulation layer155a, the charge storage layer157a, and the tunnel insulation layer160aremaining in the undercut region143are isolated from adjacent blocking insulation layer155a, charge storage layer157a, and tunnel insulation layer160adisposed in above and/or below adjacent undercut region143. Then, the sacrificial patterns162may be removed.

Alternatively, the tunnel insulation layer160, the charge storage layer157, and the blocking insulation layer155located outside the undercut regions143may also be removed by the anisotropic etching. In this case, the sacrificial patterns162may not be required.

The following methods may be carried out in the same manner as described with reference toFIG. 4E. Also, the active patterns165may be formed to have the protrusion166extending in the undercut region143. The methods can thus realize the semiconductor memory device ofFIG. 3B.

FIG. 8is a process cross-sectional view to explain methods of forming the semiconductor memory device illustrated inFIG. 3C. The methods of foaming the semiconductor memory device may include the methods described with reference toFIG. 3C.

Referring toFIG. 8, the nitridation process is carried out on the substrate100having the undercut regions143to form the conductive barriers150,151, and152. The method of forming the conductive barriers150,151, and152in the undercut regions143may be the same as described with reference toFIG. 7B.

Subsequently, the blocking insulation layer155and the charge storage layer157may be conformally formed on the substrate100. The blocking insulation layer155and the charge storage layer157may be formed to have a substantially uniform thickness along an inner surface of the opening140and the undercut region143.

The charge storage layer157and the blocking insulation layer155outside the undercut regions143may be removed. For this reason, the blocking insulation layer155aand the charge storage layer157aremaining in the undercut region143may be isolated from the adjacent blocking insulation layer155aand charge storage layer157adisposed in the above and/or below adjacent undercut region143. The charge storage layer157and the blocking insulation layer155may be removed by the anisotropic etching or the isotropic etching using the sacrificial patterns.

Subsequently, the tunnel insulation layer160may be conformally formed on the substrate100. Then, the tunnel insulation layer160formed on the bottom of the opening140may be removed. At this time, the tunnel insulation layer160may remain as it is, located on the sidewalls of the charge storage layer157aand the insulation patterns115in the opening140.

The following methods may be carried out in the same manner as described with reference toFIG. 4E. The methods can thus realize the semiconductor memory device ofFIG. 3C.

Various embodiments illustrate different cell gate patterns.

FIG. 9is a plan view illustrating a semiconductor memory device according to some embodiments of the present invention, andFIG. 10is a cross-sectional view taken along a line III-III′ ofFIG. 9.

Referring toFIGS. 9 and 10, a well region202, which is doped with a first-conductive-type dopant, is disposed in a substrate200, and a common source region204, which is doped with a second-conductive-type dopant, is disposed in the well region202. A plurality of device isolation patterns234extend along a first direction (X-axis) in parallel with one another. The device isolation patterns234are spaced apart from each other in a second direction (Y-axis) perpendicular to the first direction (X-axis). A pair of gate stacks205is disposed on the substrate200between a pair of adjacent device separation patterns234. The pair of gate stacks205extends along the first direction (X-axis) in parallel with each other. The pair of gate stacks205is spaced apart from each other along the second direction (Y-axis) to define an opening240. The opening240may be a form of groove extending in the first direction (X-axis). The pair of gate stacks205is symmetrical to each other on the basis of the opening240.

The gate stack205may include a base insulation layer206a, a first selection gate pattern210a, insulation patterns215a, cell gate patterns220a, a second selection gate pattern230a, and a capping insulation pattern232a. The first selection gate pattern210ais disposed on the base insulation pattern206a, and the insulation patterns215aand the cell gate patterns220aare alternately stacked on the first selection gate pattern210a. The second selection gate pattern230ais disposed on the uppermost one of the insulation patterns215a, and the capping insulation pattern232ais disposed on the second selection gate pattern230a. The cell gate pattern220amay form a line extending in the first direction (X-axis). The first and second selection gate patterns210aand230amay also form a line extending in the first direction (X-axis). The first interlayer insulation layer235may be disposed on the substrate200. The first interlayer insulation layer235covers the gate stacks205and the device isolation patterns234. The opening240extends upward to penetrate the first interlayer insulation layer235.

An active pattern265amay be disposed in the opening240. The active pattern265aextends upward along sidewalls (sidewalls of the gate patterns210a,220a, and230aand sidewalls of the insulation patterns206a,215a, and232a) of the gate stacks205. A pair of active patterns265ais spaced apart from each other to face each other. The pair of active patterns265amay extend upward along sidewalls of the pair of gate stacks205. The pair of active patterns265amay be disposed on both edges of an active plate264disposed on the bottom of the opening240. The pair of active patterns265amay be connected to both edges of the active plate264without a boundary. The active plate264may come in contact with the common source region204. In addition, the opening240extends downward to penetrate the common source region204, and the active plate264may come in contact with the well region202. For this reason, the active pattern265amay electrically be connected to the well region202in two directions. A drain region275doped with a second dopant may be disposed on an upper end of the active pattern265a. A pair of vertical-type cell strings includes the pair of active patterns265a. The pair of active patterns265aand the active plate264may be defined as one active pattern group. A plurality of active pattern groups is disposed in the opening240so as to be spaced apart from each other in the first direction (X-axis). A filling insulation pattern270amay be interposed between the pair of active patterns265a.

Meanwhile, the pair of active patterns265amay be substituted by one pillar-type active pattern. The pillar-type active pattern has a pair of lateral sides facing each other. The pair of lateral sides in the pillar-type active pattern extends upward along sidewalls of the pair of gate stacks205. In such cases, the filling insulation pattern270amay be omitted. The plurality of pillar-type active patterns may be disposed in the opening240so as to be spaced apart from each other in the first direction (X-axis).

Referring subsequently toFIGS. 9 and 10, the charge storage layer257is interposed between the cell gate pattern220aand the active pattern265a, and the blocking insulation layer255is interposed between the charge storage layer257and the cell gate pattern220a. The tunnel insulation layer260is interposed between the charge storage layer257and the active pattern265a. The blocking insulation layer255, the charge storage layer257, and the tunnel insulation layer260may be formed of the same materials as the blocking insulation layer155, the charge storage layer157, and the tunnel insulation layer160ofFIGS. 1,2A and2B.

A conductive barrier250may be interposed between the cell gate pattern220aand the blocking insulation layer255. The conductive barrier250contains nitrogen. When the cell gate pattern220acontains metals, the conductive barrier250may contain metal nitride. The cell gate pattern220aand the conductive barrier250may contain the same metals. The conductive barrier250may be a form of line extending in the first direction (X-axis).

Layers255,257, and260between the first selection gate pattern210aand the active pattern265amay be utilized as a first insulation layer of a first selection transistor, while layers255,257, and260between the second selection gate pattern230aand the active pattern265amay be utilized as a second insulation layer of a second selection transistor. A first selective-conductive barrier251is interposed between the first selection gate pattern210aand the first gate insulation layer255,257and260; and a second selective-conductive barrier252is interposed between the second selection gate pattern230aand the second gate insulation layer255,257and260. When the first and second selection gate patterns210aand230acontain metals, the first and second selective-conductive barriers251and252may contain metal nitrides. The conductive barriers250,251, and252may be formed of the same materials as the conductive barriers150,151, and152described with reference toFIGS. 1 and 2A.

A second interlayer insulation layer280may be disposed on the entire surface of the substrate200, and a bit line plug285may penetrate the second interlayer insulation layer280, thereby being connected to the drain region275. A bit line290is disposed on the second interlayer insulation layer280, thereby being connected to the bit line plug285. The bit line290goes across the gate patterns210a,220a, and230a. A plurality of bit lines290may extend in the second direction (Y-axis) in parallel with one another.

The blocking insulation layer255, the charge storage layer257, and the tunnel insulation layer260may continuously extend, thereby being interposed between the plurality of cell gate patterns220aand the active pattern265a.

FIG. 11Ais a cross-sectional view taken along the line III-III′ ofFIG. 9to explain examples of the semiconductor memory device according to some embodiments of the present invention.

Referring toFIG. 11A, as mentioned in above-described embodiments of the present invention, the gate patterns210,220a, and230amay contain Group 4A elements. In such cases, portions246,247, and248of the cell gate patterns210a,220a, and230aadjacent to at least the conductive barriers250a,251a, and252amay contain Group 4A element-metal compounds. At this time, the conductive barriers250a,251a, and252amay contain Group 4A element-metal nitrides. All of the gate patterns210a,220a, and230amay be formed of Group 4A element-metal compounds. The Group 4A element-metal compounds of the gate patterns210a,220a, and230amay be the same materials as those of the gate patterns110,120, and130inFIG. 3A. The conductive barrier250a,251a, and252amay be formed of the same materials as the conductive barriers150a,151a, and152aofFIG. 3A

FIG. 11Bis a cross-sectional view taken along the line III-III′ ofFIG. 9to explain other examples of the semiconductor memory device according to some embodiments of the present invention.

Referring toFIG. 11B, sidewalls of the gate patterns210a,220a, and230aformed in the opening140may be recessed sideward as compared to sidewalls of the insulation patterns206a,215a, and232a. For this reason, the undercut regions242may be defined. The conductive barriers250,251, and252are disposed in the undercut regions242. The blocking insulation layer255aand the charge storage layer257amay be disposed in the undercut region242. The blocking insulation layer255aand the charge storage layer257amay restrictively be disposed in the undercut region242. That is, the blocking insulation layer255aand the charge storage layer257adisposed in the undercut region242are isolated from the adjacent blocking insulation layer255aand charge storage layer257adisposed in the above and/or below adjacent undercut region242. The tunnel insulation layer260continuously extends, thereby being interposed between the charge storage layers257aand the active pattern265a, which are isolated from each other in the opening240. Alternatively, as illustrated inFIG. 3, the tunnel insulation layers260may be isolated from one another, which are disposed in the undercut regions242. The active pattern265amay include a protrusion266extending in the undercut region242. As the examples ofFIG. 3Aand the examples ofFIG. 3Bmay be combined with each other, so the examples ofFIG. 11Aand the examples ofFIG. 11Bmay be combined with each other.

Methods of forming the semiconductor memory device according to these embodiments of the present invention will now be described with reference to accompanying drawings.

FIGS. 12A to 12Care cross-sectional views taken along the line III-III′ ofFIG. 9to explain methods of forming the semiconductor memory device according to some embodiments of the present invention.

Referring toFIG. 12A, a well region202may be formed by injecting the first-conductive-type dopants into the substrate200, and a common source region204may be formed by injecting the second-conductive-type dopants into the well region202. A base insulation layer206, a first selection gate layer210, insulation layers215and cell gate layers220that are alternately stacked, a second selection gate layer230, and a capping insulation layer232are sequentially formed on the substrate200. A trench is formed by sequentially patterning the layers232,230,220,215,210, and106, and a device isolation pattern234is formed. As illustrated inFIG. 9, the device isolation patterns234may extend in one direction in parallel with one another. Consequently, the patterned capping insulation layer232, the second selection gate layer230, the insulation layers215, the cell gate layers220, the first selection gate layer210, and the base insulation layer206, which are located between the device isolation patterns234adjacent to each other, may be a form of line extending in one direction.

Referring toFIG. 12B, the first interlayer insulation layer235may be formed on the entire surface of the substrate200. The opening240is formed by patterning sequentially the patterned layers232,230,215,220,210, and206. The opening240may be a form of groove extending in one direction. For this reason, a pair of gate stacks205is formed at both sides of the opening240. The gate stacks205are configured of lines extending in one direction. The gate stacks205include a base insulation pattern206a, a first selection gate pattern210a, insulation patterns215aand cell gate patterns220athat are alternately stacked, a second selection gate patterns230a, and a capping insulation pattern232a. A portion of the base insulation layer206may remain below the opening240. The remaining portion of the base insulation layer206may be a buffer layer.

Referring toFIG. 12C, the conductive barriers250,251, and252may be formed by carrying out the nitridation process on sidewalls of the gate patterns210a,220a, and230aexposed at both sidewalls of the opening140. The nitridation process may be equal to that of the above-described embodiments of the present invention. Before carrying out the nitridation process, the sidewalls of the gate patterns210a,220a, and230amay be recessed sideward.

The blocking insulation layer255, the charge storage layer257, and the tunnel insulation layer260may conformally be formed on the substrate200having the conductive barriers250,251, and252. The tunnel insulation layer260, the charge storage layer257, and the blocking insulation layer255on the bottom of the opening240are removed. At this time, the layers255,257, and260on the sidewalls of the opening240remain.

The layers255,257, and260located on the upper surface of the first interlayer insulation layer235may be removed together with the layers255,257, and260on the bottom of the opening240. When a buffer layer is arranged below the opening240, the common source region204may be exposed by removing the buffer layer. The well region202may be exposed by etching the exposed common source region204.

The active plate264and the pair of active patterns265amay be formed in the opening240. The active plate264comes in contact with the common source region204and the well region202, and the pair of active patterns265aextends upward along the sidewalls of the pair of gate stacks205from both edges of the active plate264. The pair of active patterns265aand the active plate264may be formed of doped Group 4A elements (e.g., doped silicon, doped germanium, or doped silicon-germanium). Methods of forming the pair of active patterns265aand the active plate264will be described more fully with reference toFIGS. 13A to 13C.

FIGS. 13A to 13Care plan views to explain active patterns ofFIG. 12C.

Referring toFIGS. 12C and 13A, an amorphous active layer may conformally be formed on the substrate200having the exposed common source region204and the exposed well region202. The amorphous active layer has good step coverage. A crystallization process may be carried out on the amorphous active layer. The amorphous active layer may be changed into a poly crystalline or mono crystalline active layer by the crystallization process. The filling insulation layer is formed on the active layer to fill the opening140. The crystallization process may be carried out before or after forming the filling insulation layer.

As illustrated inFIG. 13A, a preliminary active pattern265and a preliminary filling insulation pattern270may be formed in the opening140by planarizing the active layer and the filling insulation layer until the first interlayer insulation layer is exposed.

Referring toFIG. 13B, a plurality of filling insulation patterns270amay be formed in the opening240by patterning the preliminary filling insulation pattern270. The preliminary filling insulation patterns270aare spaced apart from one another in one direction.

Referring toFIG. 13C, the preliminary active pattern265may be isotropically etched by using the filling insulation patterns270aas an etching mask. As a result, the preliminary active pattern265between the filling insulation patterns270is removed, thereby forming the pair of active patterns265aand the active plate264. The pair of active patterns265amay be a preliminary active pattern265remaining between the filling insulation pattern270aand the pair of gate stacks205, and the active plate264may be a preliminary active pattern265remaining between the filling insulation pattern270aand the substrate200. The upper surface of the pair of active patterns265amay be lower than that of the filling insulation pattern270a.

Referring subsequently toFIG. 12C, the drain region275ofFIG. 10may be formed by injecting the second-conductive-type dopants into the upper ends of the active pattern265a, and the second interlayer insulation layer280ofFIG. 10may be formed to cover the entire surface of the substrate200. The bit line plug285ofFIG. 10is formed, which penetrates the second interlayer insulation layer280, and the bit line290ofFIG. 10is formed on the second interlayer insulation layer280, thereby being connected to the bit line plug285. As a result, it may realize the semiconductor memory device ofFIG. 8andFIG. 10.

FIGS. 14A and 14Bare cross-sectional views to explain methods of forming the semiconductor memory device illustrated inFIG. 11A. The methods of forming the semiconductor memory device ofFIG. 11Amay include the ways described with reference toFIG. 12A.

Referring toFIGS. 12B and 14A, after forming the opening240, sidewalls of the gate patterns210a,220a, and230amay be exposed in the opening240. The gate patterns210a,220a, and230amay be formed of doped Ground 4A elements, for example, doped silicon, doped germanium, or doped silicon-germanium.

The metallization process may be carried out on the sidewalls of the gate patterns210a,220a, and230aexposed in the opening240. The metallization process may be the same as described with reference toFIG. 6B. That is, a metal layer is formed on the substrate200to come in contact with the sidewalls of the gate patterns210a,220a, and230aexposed in the opening240. The metal layer reacts to the gate patterns210a,220a, and230a. For this reason, at least the parts246,247, and248of the gate patterns210a,220a, and230amay be formed of Group 4A element-metal compounds. The method of forming the metal layer and the reaction process of the metal layer may be carried out by an in-situ method or an ex-site method. Unreacted metal layer is removed. The metal layer may be formed on the buffer layer below the opening240described with reference toFIG. 12. The buffer layer may prevent or inhibit the reaction between the metal layer and the common source region204.

Before carrying out the metallization process, the exposed sidewalls of the gate patterns210a,220a, and230amay be recessed sideward.

Referring toFIG. 14B, the metallized parts246,247, and248(that is, parts formed of Ground 4A element-metal compounds) of the gate patterns210a,220a, and230may be exposed by removing the unreacted metal layer. Then, the conductive barriers250a,251a, and252amay be formed by carrying out the nitridation process on the metallized parts246,247, and248. The conductive barriers250a,251a, and252amay be formed of Group 4A element-metal nitrides.

A process of forming the blocking insulation layer255and the following methods may be carried out in the same manner as described with reference toFIG. 12CandFIGS. 13A to 13C. The methods may thereby realize the semiconductor memory device illustrated inFIG. 11A.

FIGS. 15A and 15Bare cross-sectional views to explain methods of forming the semiconductor memory device illustrated inFIG. 11B. These methods may include the methods described with reference toFIGS. 12A and 12B.

Referring toFIGS. 12B and 15A, the undercut regions242may be formed by recessing sideward the gate patterns210a,220a, and230aexposed in the opening240. When the gate patterns210a,220a, and230acontain metals, the conductive barriers250,251, and252may be formed by carrying out the nitridation process on the recessed sidewalls of the gate patterns210a,220a, and230a. In such cases, the conductive barriers250,251, and252may be formed of metal nitrides. The nitridation process may be the same as the above-described embodiments of the present invention. The conductive barriers250,251, and252are formed in the undercut regions242.

When the gate patterns210a,220a, and230acontain doped Group 4A elements, the metallization process and the nitridation process may sequentially be carried out. In such cases, the conductive barriers250,251, and252may be formed of Group 4A element-metal nitrides.

The conductive barriers250,251, and252may fill a portion of the undercut regions242. That is, other portions of the undercut regions242may be in an empty state.

Referring toFIG. 15B, the blocking insulation layer and the charge storage layer may be conformally formed on the substrate200in turns. The blocking insulation layer and the charge storage layer may be formed to have a substantially uniform thickness along an inner surface of the opening240and the undercut region242. The blocking insulation layer and the charge storage layer located outside the undercut region242are removed. For this reason, the blocking insulation layer255aand the charge storage layer257aremaining in the undercut region242are isolated from adjacent blocking insulation layer255aand charge storage layer257adisposed above and/or below adjacent undercut region242. The blocking insulation layer and the charge storage layer located outside the undercut region242may be removed by the anisotropic etching. Alternatively, the blocking insulation layer and the charge storage layer located outside the undercut region242may also be removed by the isotropic etching that uses the sacrificial pattern162ofFIG. 7B. The blocking insulation layer255aand the charge storage layer257aformed restrictively in the undercut region242may be formed of the same materials as the blocking insulation layer155aand the charge storage layer157adescribed with reference toFIG. 3B.

Subsequently, the tunnel insulation layer260may be conformally formed on the substrate200, and the tunnel insulation layer260formed on the bottom of the opening240may be removed. At this time, the tunnel insulation layer260, which is located on the sidewalls of the insulation patterns215in the opening240, remains. Therefore, the continuously extending tunnel insulation layer260may be disposed on the inner sidewall of the opening240.

Alternatively, the tunnel insulation layer260may be formed before removing the blocking insulation layer and the charge storage layer outside the undercut region242, and all of the blocking insulation layer, the charge storage layer, and the tunnel insulation layer outside the undercut region242may also be removed.

A process of forming the active patterns265aand the following methods may be carried out in the same manner as described with reference toFIGS. 13A to 13CandFIG. 12C. The methods can thereby realize the semiconductor memory device described inFIG. 11B.

In the various embodiments of the present invention, corresponding components may be formed of the same materials.

According to the various embodiments of the present invention, the semiconductor memory devices may be embodied on various types of semiconductor packages. For example, the semiconductor memory devices according to the embodiments of the present invention may be packaged in such manners as Package on Package (PoP), Ball Grid Arrays (BGAs), Chip Scale Packages (CSPs), Plastic Leaded Chip Carrier (PLCC), Plastic Dual In-Line Package (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP), Small Outline (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package (WFP), Wafer-Level Processed Stack Package (WSP), and the like. According to the embodiments of the present invention, the package on which the semiconductor memory device is mounted may further include a controller controlling the semiconductor memory device and/or a logic device.

FIG. 16is a block diagram of an electronic system including semiconductor memory devices according to the embodiments of the present invention.

Referring toFIG. 16, the electronic system1100according to the embodiments of the present invention may include a controller1110, an input and output (I/O) device1120, a memory device1130, an interface1140, and a bus1150. The controller1110, the I/O device1120, the memory device1130, and the interface1140may be coupled to each other via the bus1150. The bus1150is a transfer pathway of data.

The controller1110may include at least one microprocessor, digital signal processor, and/or microcontroller, and at least one logic device that can execute functions similar to these. The I/O device1120may include a keypad, a keyboard, and a display device. The memory device1130may store data and/or instructions. The memory device1130may include at least one of the semiconductor memory devices disclosed in the various embodiments of the present invention. In addition, the memory device1130may further include other types of semiconductor memory devices (e.g., phase change memory device, magnetic memory device, DRAM (Dynamic Random Access Memory) device, and/or SRAM (Static Random Access Memory) device). The interface1140transmits data to a communication network or receives data from a communication network. The interface1140may have a wired or wireless form. For example, the interface1140may include an antenna or a wire/wireless transceiver. Although not illustrated inFIG. 16, the electric system1100and an operation memory for improving the operation of the controller1110may further include high-speed DRAM and/or SRAM

The electronic system1100is applicable to a mobile system, a personal computer, an industrial computer, or a system carrying out various functions. For example, the mobile system may be a personal digital assistant (PDA), a portable computer, a web tablet, a mobile phone, a wireless phone, a memory card, a digital music system, or electronic products for transmitting/receiving information in wireless environments.

FIG. 17is a block diagram a memory card including the semiconductor memory device according to some embodiments of the present invention.

Referring toFIG. 17, a memory card1200may include a memory device1210. The memory device1210may include a memory controller1220for controlling the data exchange between a host and the memory device1210.

The memory controller1220may include a CPU (Central Processing Unit)1222for controlling overall operations of the memory card. Furthermore, the memory controller1220may include an SRAM1221used as an operation memory of the CPU1222. In addition, the memory controller1220may further include a host interface1223and a memory interface1225. The host interface1223may be provided with a data exchange protocol between the memory card1200and the host. By the memory interface1225, the memory controller1220is connected with the memory device1210. Moreover, the memory controller1220may further include an Error Correction Code (ECC)1224. The ECC1224may detect and correct the errors of data read from the memory device1210. Even not illustrated inFIG. 17, the memory card1200may further include a ROM device that stores code data for interfacing with the host. The memory card1200may be used as a portable data storage card. Alternatively, the memory card1200may be embodied with a Solid State Disk (SSD) that can exchange with a hard disk of computer system.

As described above, according to various embodiments, the opening may be formed to penetrate the stacked cell gates, and the conductive barriers may be formed on the sidewalls of the cell gate layers by carrying out the nitridation process in the opening. Due to the nitridation process, the conductive barriers may selectively be formed on the sidewalls of the cell gate layers. In addition, the conductive barriers may be formed in the opening in a state of separation.