Isolated well contact in semiconductor devices

An integrated circuit and method has an isolated well with an improved isolated well contact. The well contact diffusion is isolated from a device diffusion of opposite conductivity type within the isolated well by an isolation transistor gate.

FIELD OF THE INVENTION

This invention relates to the field of integrated circuits. More particularly, this invention relates to electrical contact to isolated wells in semiconductor devices.

BACKGROUND

As semiconductor integrated circuits have scaled, both lateral and vertical dimensions have decreased. As the depth of isolated wells has decreased, the cross sectional area of the well under isolation such as shallow trench isolation (STI) has decreased resulting in increased resistance. To compensate retrograde well doping is used, where the doping at the bottom of the well is increased thus reducing the well resistance under the STI.

While retrograde well doping is sufficient for nominal voltages the well resistance under the STI may still be sufficiently high to cause a significant voltage drop when the well is under high bias and significant current is flowing between the well contact and a device such as a transistor formed in the isolated well. This drop in voltage negatively impacts the performance of the device.

A typical integrated circuit with a transistor formed in an isolated well is illustrated inFIG. 1. The transistor110is formed in the isolated well104in substrate102. Shallow trench isolation (STI) geometries108electrically isolate the well104from the substrate102by blocking silicide112from shorting the well contact diffusion146to the substrate contact diffusion156. STI geometries106electrically isolate the well contact diffusions146from the transistor source and drain diffusions154. Contact plugs116couple diffusions156,154, and146in the substrate102and well104to the first level of interconnect126.

The cross sectional area114of the well104under the STI geometry106is significantly smaller than the cross sectional area of the well adjacent to the STI geometry. This smaller cross sectional area114may cause current crowding when high bias is applied to the well104and significant current flows between a device diffusion154(such as a transistor) and the well contact diffusion146. This current crowding may cause a voltage drop which may negatively impact the performance of a device such as a transistor110.

SUMMARY

An integrated circuit containing an isolated well with an improved isolated well contact is described. The well contact diffusion is isolated from a device diffusion of opposite doping type within the isolated well by an isolation transistor gate. A process for forming an integrated circuit containing an isolated well with an improved isolated well contact is described. A process for simultaneously forming a device transistor within an isolated well and forming an improved isolated well contact is described.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

An embodiment integrated circuit with an improved isolated well contact that significantly reduces voltage drop when high bias is applied to the isolated well is illustrated inFIG. 2. Similar toFIG. 1, the transistor110is formed in an isolated well104of a second conductivity type (e.g., n-type) in substrate102of a first conductivity type (e.g., p-type). Transistor110includes a gate and source and drain regions154. Shallow trench isolation (STI) geometries108electrically isolate the well104from the substrate102by blocking silicide112from shorting the well contact diffusion146of the second conductivity type (e.g., n-type) to the substrate contact diffusion156of the first conductivity type (e.g., p-type). Contact plugs116couple diffusions156,154, and146in the substrate102and well104to the first level of interconnect126.

Instead of STI geometries106(FIG. 1) separating the isolated well contact diffusions146from the source and drain diffusions154of the transistor110, isolation transistor gates202and204are employed. The isolation transistor gates,202and204, block silicide112from shorting the well contact diffusions146, to the transistor source and drain diffusions154. The isolation transistor gates,202and204, may be left electrically floating (unconnected to any other device elements) or may be tied to a fixed voltage node such as a ground terminal or the well104potential.

For purposes of illustration, the isolation transistor gates,202and204, isolate the well contact diffusions146from the source and drain diffusions,154, of a MOS transistor. Optionally the isolation transistor gates,202and204, may isolate the well contact diffusions146from other types of devices formed in the isolated well104such as bipolar transistors, resistors, capacitors, memory cells, etc. Two well contact diffusions146are used for illustration but any number of well contact diffusions may be used.

As shown inFIG. 2, the cross sectional area214of the isolated well104under the isolation transistor gates,202and204is significantly larger than the cross sectional area114(FIG. 1) under the STI isolation. The increased cross sectional area214significantly reduces current crowding that causes the voltage drop when high bias is applied to the isolated well104and the device110draws significant current.

The major steps in an integrated circuit process flow that forms an integrated circuit with the improved isolated well contact is illustrated in the cross sections inFIGS. 3A-3G. This process flow provides an improved isolated well contact with no additional processing steps and no additional cost.

FIG. 3Ashows a partially processed integrated circuit in which an isolated well104is formed in a single crystal substrate102of opposite conductivity type. Shallow trench isolation (STI) geometries108prevent silicide from shorting the isolated well104to the substrate. For purposes of illustration an isolated n-type well104is formed in a p-type substrate102. An isolated p-type well formed in an n-type substrate could also be used.

Referring now toFIG. 3B, a transistor gate dielectric107is formed on the n-type well104and the substrate102and gate material109such as polysilicon is deposited on the transistor gate dielectric107. A transistor gate photoresist pattern with a transistor gate photo resist geometry111to form the gate of the transistor and with isolation transistor gate photo resist geometries113to form the isolation transistor gates202and204is formed on the gate material109.

The gate material109is etched using resist geometries111and113to form the gate of the transistor110and to form the isolation transistor gates202and204. The resist geometries111and113are then removed. The resulting gate of transistor110and isolation transistor gates202and204are shown inFIG. 3C.

InFIG. 3Da PMOS extension photo resist pattern130is formed on the integrated circuit and p-type dopant132is implanted to form the source and drain extensions134self-aligned to the gate of the PMOS transistor110.

Sidewall spacers140are formed on the gate of the PMOS transistor110and on isolation transistor gates,202and204, as shown inFIG. 3E. The sidewall spacers140may be formed of a dielectric material such as silicon dioxide and silicon nitride. A NMOS transistor source and drain (NSD) photo resist pattern142is formed on the integrated circuit and n-type dopant144is implanted to form the source and drains of NMOS transistors elsewhere in the circuit and to form contact diffusions146to the n-type well104. The NSD pattern partially covers the isolation transistor gates202and204and covers the source and drain extensions134adjacent to the gate of the PMOS transistor110. The NSD dopant is implanted to form well diffusions146self-aligned to the dielectric sidewall spacer140on the isolation transistor gates202and204.

InFIG. 3Fa PMOS source and drain (PSD) photo resist pattern150is formed on the integrated circuit and p-type dopant152is implanted self-aligned to the sidewall spacers140on the gate of the PMOS transistor110to form the PMOS transistor source and drain diffusions154. The p-type dopant152is also implanted into the p-type substrate102to form the p-type substrate contact diffusion156.

As illustrated inFIG. 3G, silicide112is formed in the usual manner on exposed silicon surfaces: on top of the gate of the PMOS transistor110, on top of the isolation transistor gates202and204, on top of the p-type substrate contact156, on top of the nwell104contact146, and on top of the PMOS transistor source and drain diffusions154. The isolation transistor gates block silicide112from shorting the transistor source and drain diffusions154to the nwell contact diffusions146.

Additional processing to form the premetal dielectric (PMD)120(FIG. 2), the contact plugs116, and the first level of interconnect126may be performed on the integrated circuit inFIG. 3Gto form the integrated circuit shown inFIG. 2. Additional processing may be performed on the integrated circuit inFIG. 2to add additional levels of dielectric and interconnect to complete the integrated circuit.

The embodiment improved isolated well contact provides a lower resistance path between the well contact and devices in the well. The lower resistance path reduces the voltage drop between the isolated well contact and devices formed in the well thus avoiding degraded device performance.