Nonvolatile programmable logic circuit

A nonvolatile programmable logic circuit using a ferroelectric memory performs a nonvolatile memory function and an operation function without additional memory devices, thereby reducing power consumption. Also, a nonvolatile ferroelectric memory is applied to a FPGA (Field Programmable Gate Array), thereby preventing leakage of internal data and reducing the area of a chip.

CROSS-REFERENCES TO RELATED APPLICATIONS

The present application claims priority to Korean patent application number 10-2003-0020767, filed on Apr. 2, 2003 and Korean patent application number 10-1999-0049972 (now U.S. Pat. No. 6,363,004). granted filing date Mar. 26, 2002, which is incorporated by reference in its entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to a program register using a nonvolatile memory device and a programmable logic circuit using the same, and more specifically, to a technology for storing data or performing an operation on the data without additional memory devices, thereby reducing the area of the circuit.

2. Description of the Prior Art

Generally, a ferroelectric random access memory (hereinafter, referred to as ‘FRAM’) has attracted considerable attention as next generation memory device because it has a data processing speed as fast as a Dynamic Random Access Memory DRAM and conserves data even after the power is turned off.

The FRAM having structures similar to the DRAM includes the capacitors made of a ferroelectric substance, so that it utilizes the characteristic of a high residual polarization of the ferroelectric substance in which data is not deleted even after an electric field is eliminated.

The technical contents on the above FRAM are disclosed in the Korean Patent Application No. 1999-49972 by the same inventor of the present invention. Therefore, the basic structure and the operation on the FRAM are not described herein.

A conventional programmable logic operation circuit for changing logic levels of input signals stores address information in storage means. However, since a SRAM (Static Random Access Memory) is used as the conventional programmable logic operation circuit, various information stored in latches is leaked in a power-off mode. Even when power is supplied to the system again, various data for operations of circuits are required to be reset.

SUMMARY OF THE INVENTION

Accordingly, it is an object of the present invention to provide a nonvolatile programmable logic circuit using a ferroelectric memory which disconnects power supply during a stand-by mode of the system to reduce power consumption.

It is another object of the present invention to provide a nonvolatile programmable logic circuit using a ferroelectric memory for storing data and performing an operation on the data without additional memory devices.

It is still another object of the present invention to provide a nonvolatile programmable logic circuit using a ferroelectric memory applied to a FPGA (Field Programmable Gate Array) to reduce the area of a chip.

In an embodiment, a nonvolatile programmable logic circuit comprises a plurality of CAMs (Content Addressable Memory), a first nonvolatile ferroelectric register and a switch meansr. The plurality of CAMs, connected in parallel to a match line, change a voltage level of a match line. The first nonvolatile ferroelectric register generates a first logic control signal depending on a programmed code in the nonvolatile ferroelectric capacitor. The switch means precharges the match line to a predetermined level in response to the first logic control signal.

In an embodiment, a nonvolatile programmable logic circuit comprises an inversion means, a nonvolatile ferroelectric register and an output control means. The inversion means selectively outputs one of a power voltage and a ground voltage in response to an input signal. The nonvolatile ferroelectric register generates a pair of logic control signals having an opposite phase from each other depending on a programmed code in a nonvolatile ferroelectric capacitor. The output control means outputs a signal outputted from the inversion means or floats an output terminal in response to the pair of logic control signals.

In an embodiment, a nonvolatile programmable logic circuit comprises a nonvolatile ferroelectric register, a logic combination means and an inversion means. The nonvolatile ferroelectric register generates a pair of logic control signals of opposite phases depending on a programmed code in a nonvolatile ferroelectric capacitor. The logic combination means logically combines the pair of logic control signals and the input signal. The inversion means outputs one of a power voltage and a ground voltage or floats an output terminal in response to an output signal from the logic combination means.

In an embodiment, a nonvolatile programmable logic circuit comprises a nonvolatile ferroelectric register and an inversion means. The nonvolatile ferroelectric register stores an input signal in a nonvolatile ferroelectric capacitor. The inversion means outputs one of a power voltage and a ground voltage or floats an output terminal in response to an output signal from the nonvolatile ferroelectric register.

In an embodiment, a nonvolatile programmable logic circuit comprises a nonvolatile ferroelectric register and a switch means. The nonvolatile ferroelectric register generates a logic control signal depending on a programmed code in a nonvolatile ferroelectric register. The switch means selectively connects an output terminal to a source in response to the logic control signal.

In an embodiment, a nonvolatile programmable logic circuit comprises a look-up table, a second nonvolatile ferroelectric register and a first transmission means. The look-up table selectively outputs first logic control signals outputted from a plurality of first nonvolatile ferroelectric registers in response to a logic input signal. The second nonvolatile ferroelectric register outputs a second logic control signal depending on a programmed code in a nonvolatile ferroelectric capacitor. The first transmission means selectively transmits an output signal from the look-up table in response to the second logic control signal.

In an embodiment, a nonvolatile programmable logic circuit comprises a latch means, a first nonvolatile ferroelectric register and a second nonvolatile ferroelectric register. The latch means selectively latches input data in response to a clock signal. The first nonvolatile ferroelectric register generates a first logic control signal to selectively transmit the clock signal depending on a programmed code in a nonvolatile ferroelectric capacitor. The second nonvolatile ferroelectric register generates a second logic control signal to reset the latch means depending on a programmed code in a nonvolatile ferroelectric capacitor.

In an embodiment, a nonvolatile programmable logic circuit comprises a flip-flop, a first nonvolatile ferroelectric register and a second nonvolatile ferroelectric register. The flip-flop selectively stores input data in response to a clock signal. The first nonvolatile ferroelectric register generates a first logic control signal to selectively transmit the clock signal depending on a programmed code in a nonvolatile ferroelectric capacitor. The second nonvolatile ferroelectric register generates a second logic control signal to reset the flip-flop depending on a programmed code in a nonvolatile ferroelectric capacitor.

In an embodiment, a nonvolatile programmable logic circuit comprises a program command processing block, a program register control block and a program register array block. The program command processing block sequentially outputs a plurality of command signals to code program commands in response to a write enable signal, a chip enable signal, an output enable signal and a reset signal. The program register control block outputs a write control signal and a cell plate signal using the plurality of command signals and a power-up detecting signal. The program register array block, including a plurality of nonvolatile ferroelectric registers each comprising a nonvolatile ferroelectric capacitor, programs the nonvolatile ferroelectric capacitor in response to the write control signal and the cell plate signal.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

A nonvolatile ferroelectric programmable logic circuit according to an embodiment of the present invention can be applied to various logic circuits such as a CAM (Content Addressable Memory), a CAM array, a buffer, a buffer array, an inversion means, a switch, a transmission switch, a pull-up/pull-down switch, a look-up table, a latch and a flip-flop.

FIG. 1is a block diagram illustrating a FeRAM register1applied to a pull-up operation of a match line connected to a plurality of CAMs according to an embodiment of the present invention.

In an embodiment, the nonvolatile programmable logic circuit comprises a FeRAM register1, a pull-up switch2and a plurality of CAMs3.

The plurality of CAMs3each connected to match lines ML constitute an array.

The FeRAM register1outputs a control signal RE to selectively control a switching operation of the pull-up switch2.

The pull-up switch2comprises a PMOS transistor P1. The PMOS transistor P1, connected between a power voltage and a match line ML, has a gate to receive the control signal RE. The PMOS transistor P1selectively precharges the match line ML in response to the control signal RE.

In an initial mode, the match line ML is precharged to a power voltage by the pull-up switch2. Then, when an output signal from one of the plurality of CAMs3becomes at a low level, a voltage level of the match line ML transits from a high to low level.

FIG. 2is a block diagram illustrating a CAM having an NMOS transistor structure using a FeRAM register according to an embodiment of the present invention.

In an embodiment, the CAM comprises a FeRAM register1and a pair of switching units4and5.

The FeRAM register1outputs control signals RE and REB for disabling the voltage level of the match line ML from a high to low level.

The first switching unit4comprises NMOS transistors N1and N2connected serially between the match line ML and the ground voltage. The NMOS transistor N1has a gate to receives a line control signal SB applied from a search bus. The NMOS transistor N2has a gate to receive the control signal RE applied from the FeRAM register1.

The second switching unit5comprises NMOS transistors N3and N4. The NMOS transistor N3has a gate to receive a line control signal /SB applied from the search bus. The NMOS transistor N4has a gate to receive the logic control signal REB applied from the FeRAM register1.

If the line control signal SB and the logic control signal RE are at a high level or the line control signal /SB and the logic control signal REB are at a high level, the voltage level of the match line ML transits to the ground voltage.

If the line control signal /SB and the logic control signal REB are enabled to a high level simultaneously, the NMOS transistors N3and N4are all turned on to connect the match line ML to the ground voltage. IF the line control signal SB and the logic control signal RE are enabled to a high level simultaneously, the NMOS transistors N1and N2are all turned on to connected to the match line ML to the ground voltage. As a result, the voltage level of the match line ML transits from a high to low level.

However, when the line control signal /SB has an opposite phase to the logic control signal REB, the match line ML is maintained at a high level. When the line control signal SB has an opposite phase to the logic control signal RE, the match line ML is maintained at a high level like in a precharge mode.

FIG. 3is a block diagram illustrating a FeRAM register1applied to a pull-down operation of a match line connected to a plurality of CAMs according to an embodiment of the present invention.

In an embodiment, the nonvolatile programmable logic circuit comprises a FeRAM register1, a pull-down switch6and a plurality of CAMs7.

The plurality of CAMs7each connected to match lines ML constitute an array.

The FeRAM register1outputs a control signal RE to selectively control a switching operation of the pull-down switch6.

The pull-down switch6comprises an NMOS transistor N5. The NMOS transistor N5, connected to the match line ML and a ground voltage, has a gate to receive the control signal RE. The NMOS transistor N5selectively pulls down the match line ML in response to the control signal RE.

In an initial state, the match line ML is pulled down to the ground voltage by the pull-down switch6. When an output signal from one of the plurality of CAMs7is at a high level, a voltage level of the match line ML transits from a low to high level.

FIG. 4is a block diagram illustrating a CAM having a PMOS transistor structure using a FeRAM register according to an embodiment of the present invention.

In an embodiment, the nonvolatile programmable logic circuit comprises a FeRAM register1and a pair of switching units8and9.

The FeRAM register1outputs control signals RE and REB for enabling a voltage level of the match line ML from a low to a high level.

The first switching unit8comprises PMOS transistor P2and P3connected in series between a power voltage terminal and the match line ML. The PMOS transistor P2has a gate to receive the logic control signal RE applied from the FeRAM register1. The PMOS transistor P3has a gate to receive a line control signal SB applied from a search bus.

The second switching unit9comprises PMOS transistors P4and P5connected serially between the power voltage terminal and the match line ML. The PMOS transistor P4has a gate to receive the logic control signal REB applied from the FeRAM register1. The PMOS transistor P5has a gate to receive a line control signal /SB applied from the search bus.

As a result, when the line control signal SB and the logic control signal RE are at a low level or the line control signal /SB and the logic control signal REB are at a low level, the voltage level of the match line ML transits to a power voltage.

If the line control signal /SB and the logic control signal REB are disabled to a low level simultaneously, the PMOS transistors P4and P5are all turned on to connect the match line to the power voltage. When the line control signal SB and the logic control signal RE are disabled to a low level simultaneously, the PMOS transistor P2and P3are all turned on to connect the match line ML to the power voltage. As a result, the voltage level of the match line ML transits from a low to high level.

When the line control signal /SB has an opposite phase to the logic control signal REB, the match line ML is maintained at a low level. When the line control signal SB has an opposite phase to the logic control signal RE, the match line ML is maintained at a low level in the precharge mode.

FIG. 5is a block diagram illustrating a nonvolatile programmable logic circuit comprising a tri-state buffer10using a FeRAM register1.

In an embodiment, the nonvolatile programmable logic circuit comprises a plurality of tri-state buffers10and a logic operation unit11.

The plurality of tri-state buffers10are connected to a first output line L1and a second output line L2, respectively.

An output signal Yi selected out of output signals Y0˜Yn from the plurality of tri-buffers10connected to the first output line L1is outputted into the first output line L1. An output signal Yi selected out of output signals Y0˜Yn from the plurality of tri-buffers10connected to the second output line L2is outputted into the second output line L2.

The logic operation unit11comprises an AND gate AND1for performing an AND operation on the output signals Yi applied from the first output line L1and the second output line L2.

FIG. 6is a circuit diagram illustrating an example of the tri-state buffer ofFIG. 5.

The tri-state buffer10comprises an inverter unit12and an output controller13.

The inverter unit12comprises a PMOS transistor P6and an NMOS transistor N6. The PMOS transistor P6, connected between the power voltage and the output controller13, has a gate to receive an input signal X. The NMOS transistor N6, connected between the output controller13and the ground voltage, has a gate to receive the input signal X.

The output controller13comprises the FeRAM register1and an output driving unit comprising a PMOS transistor P7and an NMOS transistor N7. The FeRAM register1outputs the control signal RE and REB having an opposite state from each other to control inversion of the buffer. The PMOS transistor P7and the NMOS transistor N7are connected in series between the PMOS transistor P6and the NMOS transistor N6. The PMOS transistor P7has a gate to the logic control signal REB, and the NMOS transistor N7has a gate to the logic control signal RE. An output signal Y is outputted from a common terminal of the PMOS transistor P7and the NMOS transistor N6.

When the control signal RE is at a high level and the logic control signal REB is at a low level, the NMOS transistor N7and the PMOS transistor P7are all turned on. As a result, an input signal X is inverted to have an opposite phase to an output signal Y.

On the other hand, when the control signal RE is at a low level and the logic control signal REB is at a high level, the NMOS transistor N7and the PMOS transistor P7are all turned off. As a result, a voltage level of the output signal Y is at a floating state regardless of that of the input signal X.

FIG. 7is a circuit diagram of another example of the tri-state buffer10ofFIG. 5.

The tri-state buffer10comprises an inverter unit14and an output controller15.

The inverter unit14comprises a PMOS transistor P8and an NMOS transistor N8. The PMOS transistor P8, connected between a power voltage and the output controller15, has a gate to receive the input signal X. The NMOS transistor N8, connected between the output controller15and the ground voltage, has a gate to receive the input signal X.

The output controller15comprises the FeRAM register1, an inverter IV1and a logic operation unit16. The FeRAM register1outputs the control signals RE and REB having an opposite phase from each other. The inverter IV1inverts a clock signal CLK.

The logic operation unit16comprises an NAND gate ND1and an NOR gate NOR1. The NAND gate ND1performs an NAND operation on the logic control signal REB and the clock signal CLK. The NOR gate NOR1performs an NOR operation on the logic control signal RE and an output signal from the inverter IV1.

The PMOS transistor P9and the NMOS transistor N9are connected in series between the PMOS transistor P8and the NMOS transistor N8. The PMOS transistor P9has a gate to receive an output signal from the NAND gate ND1. The NMOS transistor N9has a gate to receive an output signal from the NOR gate NOR1. The output signal Y is outputted from a common terminal of the PMOS transistor P9and the NMOS transistor N9.

When the logic control signal RE is at a low level, the logic control signal REB at a high level and the clock signal CLK at a low level, the NMOS transistor N9and the PMOS transistor P9are all turned off. As a result, the voltage level of the output signal Y is at a floating state.

When the logic control signal RE is at the low level, the logic control signal REB at the high level and the clock signal CLK at a high level, the NMOS transistor N9and the PMOS transistor P9are all turned on. As a result, the input signal X is inverted to have an opposite phase to that of the output signal Y.

The voltage level of the output signal Y can be periodically controlled by inverting or floating the voltage level of the input signal X in response to the clock signal CLK.

If the logic control signal RE is at a high level and the logic control signal REB is at a low level, the NMOS transistor N9and the PMOS transistor P9are all turned off regardless of the clock signal CLK. As a result, the voltage level of the output signal Y becomes floated.

FIG. 8is a circuit diagram of still another diagram of the tri-state buffer10ofFIG. 5.

The tri-state buffer10comprises an input controller17and an output driving unit18.

The input controller17comprises the FeRAM register1and a logic operation unit19. The FeRAM register1outputs the logic control signals RE and REB having an opposite phase from each other for inversion of an inverter. The logic operation unit19comprises an AND gate AND2and an OR gate OR1. The AND gate AND2performs an AND operation on the logic control signal REB and the input signal X. The OR gate OR1performs an OR operation on the logic control signal RE and the input signal X.

The output driving unit18comprises a PMOS transistor10and an NMOS transistor10. The PMOS transistor P10and the NMOS transistor N10are connected serially between the power voltage and the ground voltage. The PMOS transistor P10has a gate to receive an output signal from the AND gate AND2. The NMOS transistor N10has a gate to receive an output signal from the OR gate OR1.

When the logic control signal RE is at the high level and the logic control signal REB is at the low level, the voltage level of the output signal Y is floated regardless of that of the input signal X.

If the logic control signal RE is at the low level, the logic control signal REB at the low level and the input signal X at a high level, the NMOS transistor N10is turned on. AS a result, the input signal X is inverted, and the output signal Y transits to a low level.

On the other hand, when the logic control signal RE is at the low level, the logic control signal REB at the high level and the input signal X at a low level, the PMOS transistor P10is turned on. As a result, the input signal X is inverted, and the output signal Y transits to a high level.

FIG. 9is a circuit diagram of still another example of the tri-state buffer10ofFIG. 5for controlling logic of the inverter unit and storing values of input signals at the same time.

The tri-state buffer10ofFIG. 9comprises an input controller20and an output driving unit21.

The input controller20comprises inverters IV2and IV3, the FeRAM register1and a logic operation unit22. The inverter IV2inverts the clock signal CLK, and the inverter IV3inverts the input signal X. The FeRAM register1outputs the logic control signal RE for controlling the logic level of the output driving unit21.

The logic operation unit22comprises an AND gate AND3and an OR gate OR2. The AND gate AND3performs an AND operation on the clock signal CLK and the logic control signal RE. The OR gate OR2performs an OR operation on an output signal from the inverter IV2and the logic control signal RE.

The output driving unit21comprises a PMOS transistor P11and an NMOS transistor N11. The PMOS transistor P11and the NMOS transistor N11are connected in series between the power voltage and the ground voltage. The PMOS transistor P11has a gate to receive an output signal from the AND gate AND3. The NMOS transistor N11has a gate to receive an output signal from the OR gate OR2.

When the clock signal CLK is at the high level and the logic control signal RE is at the high level, the NMOS transistor N11is turned on. As a result, the input signal X is inverted, and the output signal Y transits to a low level.

If the clock signal CLK is at the low level, the PMOS transistor P11and the NMOS transistor N11are turned on regardless of the logic control signal RE. As a result, the voltage level of the output signal Y is floated.

On the other hand, if the clock signal CLK is at the high level and the logic control signal RE is at the low level, the PMOS transistor P11is turned on. As a result, the input signal X is inverted, and the output signal Y transits to a high level.

FIG. 10is a block diagram illustrating a transmission switch23for transmitting data between bus lines using a FeRAM register.

In an embodiment, a plurality of transmission switches23are connected between a plurality of row bus lines R0˜Rn and a plurality of column bus lines C0˜Cn crossed from each other.

Each transmission switch23comprises the FeRAM register1and an NMOS transistor N12. The FeRAM register1outputs the control signal RE for controlling the switching operation. The NMOS transistor N12, connected between the row bus line R and the column bus line C, has a gate to receive the logic control signal RE.

When the control signal RE is at the high level, the NMOS transistor N12is turned on to connect the row bus line R to the column bus line C. However, when the logic control signal RE is at the low level, the NMOS transistor N12is turned off to disconnect the row bus line R to the column bus line C.

FIG. 11is a circuit diagram illustrating another example of the transmission switch23ofFIG. 10.

The transmission switch23ofFIG. 11comprises a switch controller24and the NMOS transistor N12.

The switch controller24comprises the FeRAM register1and a logic operation unit25. The FeRAM register1outputs the control signal RE for controlling the switching operation. The logic operation unit25comprises an AND gate AND4for performing an AND operation on the control signal RE and the clock signal CLK.

If the clock signal CLK and the logic control signal RE are at the high level, the NMOS transistor N12is turned on to connect the row bus line R to the column bus line C.

However, when the clock signal CLK is at the low level and the logic control signal RE is at the high level, the NMOS transistor N12is turned off to disconnect the row bus line R to the column bus line C.

If the control signal RE is at the low level, the NMOS transistor is turned off regardless of the clock signal CLK.

FIG. 12is a block diagram illustrating the nonvolatile programmable logic circuit for selectively pulling up bus lines using a FeRAM register1.

The nonvolatile programmable logic circuit ofFIG. 12comprises a plurality of FeRAM registers1and a plurality of pull-up switches26. Each FeRAM register1outputs the control signal RE for controlling each pull-up switch26. The plurality of pull-up switches26are connected between the power voltage and a plurality of bus lines B0˜Bn. Each pull-up switch26comprises a PMOS transistor P12having a gate to receive the control signal RE.

When the control signal RE is at the low level, the pull-up switch26is turned on to pull up the bus line B to the power voltage. However, when the control signal RE is at the high level, the pull-up switch26is turned off.

FIG. 13is a block diagram illustrating the nonvolatile programmable logic circuit for selectively pulling down bus lines using a FeRAM register1.

The nonvolatile programmable logic circuit ofFIG. 13comprises a plurality of FeRAM registers1and a plurality of pull-down switches27. Each FeRAM register1outputs the control signal RE for controlling each pull-down switch27. The plurality of pull-down switches27are connected between the plurality of bus lines B0˜Bn and the ground voltage. Each pull-down switch27comprises an NMOS transistor N13having a gate to receive the control signal RE.

When the control signal RE is at the high level, the pull-down switch27is turned on to pull down the bus line B to the ground voltage. However, when the control signal RE is at the low level, the pull-down switch27is turned off.

FIG. 14is a block diagram illustrating the nonvolatile programmable logic circuit for controlling logic levels of a look-up table using a FeRAM register1.

The FeRAM register1outputs the control signal RE for controlling logic levels of the look-up table28. The loop-up table28performs an operation on the logic input signal X in response to the control signal RE, thereby controlling the output signal Y.

FIG. 15ais a circuit diagram illustrating the nonvolatile programmable logic circuit for controlling the 2-register input look-up table28ofFIG. 14.

The FeRAM register1outputs the logic control signal RE for controlling the transmission switch30. The transmission switch30comprises an NMOS transistor14. The NMOS transistor N14, connected between an output terminal of the logic output signal Y and a common drain of the NMOS transistors N15and N16, has a gate to receive the logic control signal RE.

The inverter IV4inverts the logic input signal X. The NMOS transistor N15outputs a logic control signal RE1into the transmission switch30in response to the logic input signal X. The NMOS transistor N16outputs a logic control signal RE2into the transmission switch30in response to the output signal from the inverter IV4.

The nonvolatile programmable logic circuit controls the value of the logic output signal Y through different operation processes depending on kinds of data stored in the FeRAM register array29.

For example, when the logic control signal RE is at the high level, the NMOS transistor N14is turned on to determine the value of the logic output signal Y in response to the logic control signals RE1and RE2.

When the logic control signals RE1and RE2are all at a low level, the voltage level of the logic output signal Y becomes at a low level. However, when the logic control signals RE1and RE2are all at a high level, the voltage level of the logic output signal Y becomes at a high level.

When the first logic control signal RE1is at the high level and the second logic control signal RE2is at the low level, the logic input signal X becomes the logic output signal Y. However, when the first logic control signal RE1is at the low level and the second logic control signal RE2is at the high level, the logic input signal X is inverted.

If the logic control signal RE is at the low level, the NMOS transistor N14is turned off. As a result, the voltage level of the output signal Y is floated regardless of the logic control signals RE1and RE2.

FIG. 15bis a circuit diagram illustrating the nonvolatile programmable logic circuit for controlling the 4-register input look-up table28ofFIG. 14.

The look-up table28performs an operation on logic input signals X0and X1in response to logic control signals RE1˜RE4to control the logic output signal Y.

The FeRAM register1outputs the logic control signal RE for controlling the transmission switch31. The transmission switch31comprises an NMOS transistor N17. The NMOS transistor N17, connected between an output terminal of the logic output signal Y and a common drain of the NMOS transistor N18and N19, has a gate to receive the logic control signal RE.

The inverter IV5inverts the first logic input signal X0. The NMOS transistor N18outputs the first logic control signal RE1and the second logic control signal RE2into the transmission switch31in response to the first logic input signal X0. The NMOS transistor N19outputs the third logic control signal RE3and the fourth logic control signal RE4in response to the output signal from the inverter IV5.

The inverter IV6inverts the second logic input signal X1. The NMOS transistor N20outputs the first logic control signal RE1in response to the second logic input signal X1. The NMOS transistor N21outputs the second logic control signal RE2in response to the output signal from the inverter IV6. The NMOS transistor N22outputs the third logic control signal RE3in response to the second logic input signal X1. The NMOS transistor N23outputs the fourth logic control signal RE4in response to the output signal from the inverter IV6.

The logic control operation according to an embodiment of the present invention is represented as follows:

When the logic control signal RE is at the high level, the NMOS transistor N17is turned on to determine the value of the logic output signal Y in response to the logic control signals RE1˜RE4.

When the fourth logic control signal RE4is at the high level and the rest logic control signals RE1˜RE3are at the low level, the logic output signal Y is an NOR operation result of the logic input signals X0and X1. When the first logic control signal RE1and the fourth logic control signal RE4are at the low level and the second logic control signal RE2and the third logic control signal RE3are at the high level, the logic output signal Y is an exclusive logic operation result of the logic input signals X0and X1.

When the first logic control signal RE1is at the low level, the rest logic control signals RE2˜RE4are at the high level, the logic output signal Y is an NAND operation result of the logic input signal X0and X1. When the first logic control signal RE1is at the high level and the rest logic control signals RE2˜RE4are at the low level, the logic output signal Y is an AND operation result of the logic input signals X0and X1. When the fourth logic control signal RE4is at the low level and the rest logic control signals RE1˜RE3are at the high level, the logic output signal Y is an OR operation result of the logic input signals X0and X1.

When the logic control signal RE is at the low level, the NMOS transistor N17is turned off to float the voltage level of the logic output signal regardless of the logic control signals RE1˜RE4.

FIG. 15cis a circuit diagram illustrating the nonvolatile programmable logic circuit for controlling the 8-register input look-up table28ofFIG. 14.

The look-up table28performs an operation on logic input signals X0, X1and X2in response to logic control signals RE1˜RE8to control the logic output signal.

The look-up table29comprises a FeRAM register array29, inverters IV7˜IV9, NMOS transistors N25˜N38, a FeRAM register1and a transmission switch32. The FeRAM register array29comprising eight FeRAM registers1outputs logic control signals RE1˜RE8to control logic of the look-up table28.

The FeRAM register1outputs a logic control signal RE0for controlling the transmission switch32. The transmission switch32comprises an NMOS transistor N24. The NMOS transistor N24, connected between an output terminal of the logic output signal Y and a common drain of the NMOS transistors N25and N26, has a gate to receive the logic control signal RE0.

The inverter IV7inverts the first logic input signal X0. The NMOS transistor N25outputs one of the logic control signals RE1˜RE4into the transmission switch32in response to the first logic input signal X0. The NMOS transistor N26outputs one of the logic control signals RE5˜RE8into the transmission switch32in response to the output signal from the inverter IV7.

The inverter IV8inverts the second logic input signal X1. The NMOS transistor N27outputs the first logic control signal RE1or the second logic control signal RE2into the NMOS transistor N25in response to the second logic input signal X1. The NMOS transistor N28outputs the third logic control signal RE3or the fourth logic control signal RE4into the NMOS transistor N25in response to the output signal from the inverter IV8.

The NMOS transistor N29outputs the fifth logic control signal RE5or the sixth logic control signal RE6into the NMOS transistor N26in response to the second logic input signal. The NMOS transistor N30outputs the seventh logic control signal RE7or the eighth logic control signal into the NMOS transistor N26into the NMOS transistor N26.

The inverter IV9inverts the third logic input signal X2.

The NMOS transistor N31outputs the first logic control signal RE1into the NMOS transistor N27in response to the third logic input signal X2. The NMOS transistor N32outputs the second logic control signal RE2into the NMOS transistor N27in response to the output signal from the inverter IV9. The NMOS transistor N33outputs the third logic control signal RE3into the NMOS transistor N28in response to the third logic input signal X2. The NMOS transistor N34outputs the fourth logic control signal RE4into the NMOS transistor N28in response to the output signal from the inverter IV9.

The NMOS transistor N35outputs the fifth logic control signal RE5into the NMOS transistor N29in response to the third input signal X2. The NMOS transistor N36outputs the sixth logic control signal RE6into the NMOS transistor N29in response to the output signal from the inverter IV9. The NMOS transistor N37outputs the seventh logic control signal RE7into the NMOS transistor N30in response to the third logic input signal X2. The NMOS transistor N38outputs the eighth logic control signal RE8into the NMOS transistor N30in response to the output signal from the inverter IV9.

The nonvolatile programmable logic circuit ofFIG. 15performs a logic operation on the logic input signals X0, X1and X2in response to the logic control signals RE1˜RE8to determine the value of the logic output signal Y.

If the logic control signal RE is at the low level, the NMOS transistor N24is turned off to float the voltage level of the logic output signal Y regardless of the logic control signals RE1˜RE8.

FIG. 16is a circuit diagram illustrating the nonvolatile programmable logic circuit for controlling logic levels of a D-latch using a FeRAM register1.

The nonvolatile programmable logic circuit ofFIG. 16comprises a latch controller33and a latch unit34.

The latch controller33comprises a FeRAM register1, an NAND gate ND2and an inverter IV10. The NAND gate ND2performs an NAND operation on the clock signal CLK and an output signal from the FeRAM register1. The inverter IV10inverts an output signal from the NAND gate ND2.

The latch unit34comprises inverters IV11and IV12, transmission gates T1and T2, an NAND operation ND3and a FeRAM register1. The inverter IV11inverts an input signal inputted through an input terminal d. The first transmission gate T1selectively transmits an output signal from the inverter IV11in response to an output signal applied from the latch controller33. The inverter IV12inverts an output signal from the first transmission gate T1and outputs the inverted signal into an output terminal q.

The NAND gate ND3performs an NAND operation on an output signal from the FeRAM register1to control a reset operation and an output signal from the inverter IV12. The second transmission gate T2selectively transmits an output signal from the NAND gate ND3in response to an output signal from the latch controller33.

In the embodiment ofFIG. 16, the clock signal CLK is selectively outputted in response to an output signal from the FeRAM register1of the latch controller33. When the output signal from the FeRAM register1is at a high level, the clock signal CLK is outputted into the latch unit34. However, when the output signal from the FeRAM register1is at a low level, the clock signal CLK is not outputted into the latch unit34.

The FeRAM register1of the latch unit34controls a reset operation of the latch unit34. When the output signal from the FeRAM register1is at the high level, a normal latch operation is performed. When the output signal from the FeRAM register1is at the low level, an output signal from the latch unit34is reset.

FIG. 17is a circuit diagram of another example of the nonvolatile programmable logic circuit ofFIG. 16.

The nonvolatile programmable logic circuit ofFIG. 17comprises a latch controller33and a latch unit35.

The latch controller33comprises a FeRAM register1, an NAND gate ND4and an inverter IV13. The NAND gate ND4performs an NAND operation on the clock signal CLK and an output signal from the FeRAM register1. The inverter IV13inverts an output signal from the NAND gate ND4.

The latch unit35comprises inverters IV14and IV15, transmission gates T3and T4and a FeRAM register1. The third transmission gate T3selectively transmits an output signal from the inverter IV14in response to an output signal applied from the latch controller33. The inverter IV15inverts a signal transmitted from the third transmission gate T3, and outputs the inverted signal into an output terminal q.

The signal transmitted from the third transmission gate T3is inputted into an inversion input terminal /D of the FeRAM register1. An output signal from the inverter IV15is inputted into a non-inversion input terminal D of the FeRAM register1. The fourth transmission gate T4selectively transmits the logic control signal REB in response to the output signal from the latch controller33.

In the embodiment ofFIG. 17, the clock signal CLK is selectively outputted in response to the output signal from the FeRAM register1of the latch controller33. When the output signal from the FeRAM register1is at a high level, the clock signal CLK is outputted into the latch unit35. However, when the output signal from the FeRAM register1is at a low level, the clock signal CLK is not outputted into the latch unit35.

The FeRAM register1of the latch unit35stores data inputted in the latch unit35. As a result, the data stored in the FeRAM register1can be restored when power is re-supplied after a power off mode.

FIG. 18is a circuit diagram of still another example of the nonvolatile programmable logic circuit ofFIG. 16.

The nonvolatile programmable logic circuit ofFIG. 18comprises a latch controller33, a operation unit36and a latch unit37.

The latch controller33comprises a FeRAM register1, an NAND gate ND5and an inverter IV16. The NAND gate ND5performs an NAND operation on the clock signal CLK and an output signal from the FeRAM register1. The inverter IV16inverts an output signal from the NAND gate ND5.

The operation unit36comprises an AND gate AND5for performing an AND operation on logic input signals X0and X1.

The latch unit37comprises transmission gates T5and T6, an inverter IV17and a FeRAM register1. The fifth transmission gate T5selectively transmits an output signal from the AND gate AND5in response to an output signal applied from the latch controller33. The inverter IV17inverts an output signal from the fifth transmission gate T5, and outputs the inverted signal into an output terminal q.

The signal transmitted from the fifth transmission gate T5is inputted into an inversion input terminal /D of the FeRAM register1. An output signal from the inverter IV17is inputted into a non-inversion input terminal D of the FeRAM register1. The sixth transmission gate T6selectively transmits the logic control signal REB in response to an output signal from the latch controller33.

In the embodiment ofFIG. 18, the clock signal CLK is selectively outputted in response to the output signal from the FeRAM register1of the latch controller33. When the output signal from the FeRAM register1is at a high level, the clock signal CLK is outputted into the latch unit37. However, when the output signal from the FeRAM register1is at a low level, the clock signal CLK is not outputted into the latch unit37.

The FeRAM register1of the latch unit37stores data inputted in the latch unit37. As a result, the data stored in the FeRAM register1can be restored when power is re-supplied after a power off mode.

FIG. 19is a circuit diagram illustrating the nonvolatile programmable logic circuit for controlling logic levels of a flip-flop using a FeRAM register1.

The nonvolatile programmable logic circuit ofFIG. 19comprises a logic controller38and a flip-flop unit39.

The logic controller38comprises a FeRAM register1, an NAND gate ND6and an inverter IV18. The NAND gate ND6performs an NAND operation on the clock signal CLK and an output signal from the FeRAM register1. The inverter IV18inverts an output signal from the NAND gate ND5.

The flip-flop unit39comprises inverters IV19˜IV22, transmission gates T7˜T10and two FeRAM registers1. The seventh transmission gate T7selectively transmits an output signal from the inverter IV19in response to an output signal applied from the logic controller38.

The signal transmitted from the seventh transmission gate T7is inputted into an inversion input terminal /D of the first FeRAM register1. An output signal from the inverter IV20is inputted into a non-inversion input terminal D of the first FeRAM register1. The eighth transmission gate T8selectively transmits the logic control signal REB in response to an output signal from the logic controller38.

The ninth transmission gate T9selectively transmits an output signal from the inverter IV20in response to an output signal applied from the logic controller38. The signal transmitted from the ninth transmission gate T9is inputted into an inversion input terminal /D of the second FeRAM register1. An output signal from the inverter IV21is inputted into a non-inversion input terminal D of the second FeRAM register1. The tenth transmission gate T10selectively transmits the logic control signal REB in response to an output signal from the logic controller38. The inverter IV22inverts an output signal from the inverter IV21, and outputs the inverted signal into an output terminal q.

In the embodiment ofFIG. 19, the clock signal CLK is inputted in response to the output signal from the FeRAM register1. When the output signal from the FeRAM register1is at a high level, the clock signal CLK is outputted into the flip-flop unit39. However, when the output signal from the FeRAM register1is at a low level, the clock signal CLK is not inputted into the flip-flop unit39.

The two FeRAM registers1of the flip-flop unit39store data inputted in the flip-flop unit39. As a result, the data stored in the FeRAM register1can be restored when power is re-supplied after a power-off mode.

FIG. 20is a circuit diagram illustrating another example ofFIG. 19.

The nonvolatile programmable logic circuit ofFIG. 20comprises a logic controller38, an operation unit40and a flip-flop unit41.

The logic controller38comprises a FeRAM register1, an NAND gate ND7and an inverter IV23. The NAND gate ND7performs an NAND operation on the clock signal CLK and an output signal from the FeRAM register1. The inverter IV23inverts an output signal from the NAND gate ND7.

The operation unit40comprises an AND gate AND6for performing an AND operation on logic input signals X0and X1.

The flip-flop unit41comprises inverters IV24˜IV26, transmission gate T11˜T14and two FeRAM register1. The 11thtransmission gate T11selectively transmits an output signal from the AND gate AND6in response to an output signal applied from the logic controller38. The signal transmitted from the 11thtransmission gate T11is inputted into an inversion input terminal /D of the FeRAM register1. An output signal from the inverter IV24is inputted into a non-inversion input terminal D of the FeRAM register1. The 12thtransmission gate T12selectively transmits the logic control signal REB in response to an output signal from the logic controller38.

The 13thtransmission gate T13selectively transmits an output signal from the inverter IV24in response to the output signal applied from the logic controller38. The signal transmitted from the 13thtransmission gate T13is inputted into an inversion input terminal /D of the first FeRAM register1. An output signal from the inverter IV25is inputted into a non-inversion input terminal D of the second FeRAM register1. The 14thtransmission gate T14selectively transmits the logic control signal REB in response to the output signal from the logic controller38. The inverter IV26inverts the output signal from the inverter IV25, and outputs the inverted signal into an output terminal q.

In the embodiment ofFIG. 20, an output signal from the operation unit40is inputted into the flip-flop unit41.

In the embodiment ofFIG. 20, the clock signal CLK is inputted in response to the output signal from the FeRAM register1. When the output signal from the FeRAM register1is at a high level, the clock signal CLK is outputted into the flip-flop unit41. However, when the output signal from the FeRAM register1is at a low level, the clock signal CLK is not inputted into the flip-flop unit41.

The two FeRAM registers1of the flip-flop unit41store data inputted in the flip-flop unit41. As a result, the data stored in the FeRAM register1can be restored when power is re-supplied after a power-off mode.

FIG. 21is a circuit diagram illustrating still another example ofFIG. 19.

The nonvolatile programmable logic circuit ofFIG. 21comprises a logic controller38and a flip-flop unit42.

The logic controller38comprises a FeRAM register1, an NAND gate ND8and an inverter IV27. The NAND gate ND8performs an NAND operation on the clock signal CLK and an output signal from the FeRAM register1. The inverter IV27inverts an output signal from the NAND gate ND8.

The 17thtransmission gate T17selectively transmits the output signal from the inverter IV29in response to the output signal applied from the logic controller38. The NAND gate ND10performs an NAND operation on the signal transmitted from the 17thtransmission gate T17and the output signal from the FeRAM register1. The 18thtransmission gate T18selectively transmits an output signal from the inverter IV30in response to the output signal from the logic controller38.

In the embodiment ofFIG. 21, the FeRAM register1of the flip-flop unit42controls a reset operation of the flip-flop unit42. If the output signal from the FeRAM register1is at a high level, a normal flip-flop operation is possible. If the output signal from the FeRAM register1is at a low level, the flip-flop unit42is reset.

FIG. 22is a block diagram illustrating a logic circuit for programming a FeRAM register1according to an embodiment of the present invention.

In an embodiment, the program logic circuit comprises comprises a program command processor43, a program register controller44, a reset circuit unit45and a program register array46.

The program command processor43codes program commands in response to a write enable signal WEB, the chip enable signal CEB, an output enable signal OEB and a reset signal RESET, and outputs a command signal CMD. The program register controller44logically combines the command signal CMD, a power-up detecting signal PUP and input data DQn, and outputs a write control signal ENW and a cell plate signal CPL.

In a power-up mode, the reset circuit unit45outputs the reset signal RESET into the program register controller44.

The program register array46programs externally inputted data Dm and /Dm in response to a pull-up enable signal ENP, a pull-down enable signal ENN, a write control signal ENW and a cell plate signal CPL, and outputs register control signals REm and REBm.

If the command signal CMD is generated from the program command processor43, the program register controller44changes or sets configuration data of a program in the program register array46.

The reset circuit unit45generates the reset signal RESET in the power-up mode, thereby activating the program register controller44. Control signals outputted from the program register controller44are to initialize nonvolatile data of the program register array46.

FIG. 23is a circuit diagram illustrating the program command processor43ofFIG. 22.

The program command processor43comprises a command controller47and a multiple command generator48.

The command controller47comprises a logic unit49, a flip-flop unit50and an over-toggle detector51.

The logic unit49comprises an NOR gate NOR2, an AND gates AND7and AND8and an inverter IV32. The NOR gate NOR2performs an NOR operation on the write enable signal WEB and the chip enable signal CEB. The AND gate AND7performs an AND operation on an output signal from the NOR gate NOR2and the output enable signal OEB. The inverter IV32inverts the reset signal RESET. The AND gate AND8performs an AND operation on the output signal from the NOR gate NOR2, an output signal from the inverter IV32and an output signal from the over-toggle detector51.

The flip-flop unit50comprises n flip-flops FF connected serially. The first flip-flop FF(1) has an input terminal d to receive the output signal from the NOR gate NOR2. Also, each flip-flop FF has an input terminal cp to receive an activation synchronizing signal outputted from the AND gate AND7, and a reset terminal R to receive a reset signal outputted from the AND gate AND8.

Here, the input terminal cp of the flip-flop FF receives the output enable signal OEB when the chip enable signal CEB and the write enable signal WEB are at a low level. The reset terminal R of the flip-flop FF receives a low level signal if one of the chip enable signal CEB and the write enable signal WEB becomes at a high level. In the power-up mode, the flip-flop FF is reset while the reset signal RESET is at a high level.

The over-toggle detector51comprises an NAND gate ND11for performing an NAND operation on the output signal from the node A and the output enable signal OEB. The over-toggle detector51resets the flip-flop unit50when the output enable signal OEB toggles over n times to cause over-toggle. Therefore, the number of toggle in the program command processor43is set to be different.

The multiple command generator48comprises a logic unit52and a flip-flop unit53.

The logic unit52comprises an NOR gate NOR3, AND gates AND9and AND10and an inverter IV33. The NOR gate NOR3performs an NOR operation on the write enable signal WEB and the chip enable signal CEB. The AND gate AND9performs an AND operation on an output signal from the NOR gate NOR3and the output enable signal OEB. The inverter IV33inverts the reset signal RESET. The AND gate AND10performs an AND operation on the output signal from the AND gate AND3and the output signal from the inverter IV33.

The flip-flop unit53comprises m flip-flops FF connected serially. The first flip-flop FF(n+1) has an input terminal d to receive an output signal from the flip-flop FF(n−1) of the command controller47. Through input terminals d and output terminals q serially connected each other, a high pulse outputted from the flip-flop FF(n+1) sequentially moves into the next flip-flop. As a result, the flip-flops FF sequentially output a plurality of command signal such as a 1st_CMD, a 2nd_CMD, . . . , a mth_CMD.

Each flip-flop has an input terminal cp to receive an activation synchronization signal outputted from the AND gate AND9, and a reset terminal R to receive a reset signal outputted from the AND gate AND10.

When the chip enable signal CEB and the write enable signal WEB are at a low level, the output enable signal OEB is inputted into the input terminal cp of each flip-flop FF. When one of the chip enable signal CEB or write enable signal WEB becomes at a high level, a low level signal is inputted into the reset terminal R of each flip-flop FF, and the flip-flop is reset. While the reset signal RESET is at a high level, the flip-flop FF is reset in the power-up mode.

The flip-flop FF comprises transmission gates T19˜T22, NAND gates ND12and ND13, and inverters IV34˜IV39. Here, the inverter IV34inverts an output signal from the input terminal cp, and the inverter IV35inverts an output signal from the inverter IV34.

The inverter IV36inverts the data inputted through the input terminal d.

The 19thtransmission gate T19selectively outputs an output signal from the inverter IV36depending on output signals E and F from the inverters IV34and IV35. The inverter IV39inverts an output signal from the 19thtransmission gate T19. The NAND gate ND12performs an NAND operation on output signal from the inverter IV37and the reset terminal R. The 20thtransmission gate T20selectively outputs an output signal from the NAND gate ND12depending on the output signals E and F from the inverters IV34and IV35.

The 21sttransmission gate T21selectively outputs an output signal from the inverter IV37depending on the output signals E and F from the inverters IV34and IV35. The NAND gate ND13performs an NAND operation on output signals from the 21sttransmission gate T21and the reset terminal R.

The inverter IV38inverts an output signal from the NAND gate ND13.

The 22ndtransmission gate T22selectively outputs an output signal from the inverter IV38depending on the output signals E and F from the inverters IV34and IV35. The inverter IV39inverts an output signal from the NAND gate ND13, and outputs the inverted signal into the output terminal q.

Data inputted from the input terminal d are transmitted by the transmission gates T19and T21whenever a control signal inputted through the input terminal cp toggles once. When a low level signal is inputted into the reset terminal R, a low level signal is outputted into the output terminal q to reset the flip-flop FF.

FIG. 25is a timing diagram illustrating the operation of the program command processor43ofFIG. 22.

In a command processing interval, the chip enable signal CEB and the write enable signal WEB are maintained at a low level. While the output enable signal OEB toggles n times, the command signal CMD is maintained at a low level.

Thereafter, if an programmable activation interval starts and the output enable signal OEB toggles n times, the command signal 1st_CMD outputted from the flip-flop FF(n+1) is enabled to a high level.

If the over-toggle detector51detects over-toggle after the nthtoggle, the output signal of the node A becomes at a low level. Here, since an output signal of the flip-flop FF(n−1) is inputted into the flip-flop FF(n+1), the multiple command generator48is not affected by the over-toggle detector51.

Next, if the (n+1)thtoggle occurs, the command signal 1st_CMD becomes at a low level, and the command signal 2nd_CMD outputted from the flip-flop FF(n+2) is enabled to a high level. When the number of toggles of the output signal OEB is regulated, the number of flip-flops FF connected serially is regulated.

FIG. 26is a circuit diagram illustrating the program register controller44ofFIG. 22.

The program register controller44comprises a delay unit54, an AND gate AND11, inverters IV43˜IV47, and NOR gates NOR4and NOR5. The AND gate AND11performs an AND operation on the command signal ith_CMD and input data DQi. The delay unit54which comprises the inverters IV40˜IV42connected in series delays an output signal from the AND gate AND11.

The NOR gate NOR4performs an NOR operation on output signals from the AND gate AND11and the delay unit54. The inverter IV43and IV44delay an output signal from the NOR gate NOR4to output the write control signal ENW.

The NOR gate NOR5performs an NOR operation on an output signal from the NOR gate NOR4and the power-up detecting signal PUP. The inverters IV45˜IV47invert and delay an output signal from the NOR gate NOR5to output the cell plate signal CPL.

Here, the power-up detecting signal PUP is to reset the register after data stored in the register are read in the initial reset mode.

If the input data DQi inputted through an input pad are toggled after the command signal 1st_CMD is activated to a high level, the write control signal ENW and the cell plate signal CPL having a pulse width for a delay time of the delay unit54.

FIG. 27is a circuit diagram illustrating the program register array46ofFIG. 22.

The program register array46comprises m FeRAM registers1.

The FeRAM register1comprises a pull-up switch P13, a pull-up driver55, a write enable controller56, a ferroelectric capacitor unit57, a pull-down driver58and a pull-down switch N43.

The pull-up switch P13, connected between the power voltage terminal VCC and the pull-up driver55, has a gate to receive the pull-up enable signal ENP. The pull-up driver55, connected between the pull-up switch P13and the write enable controller56, comprises PMOS transistors P14and P15connected with a latch structure between nodes CN1and CN2.

The write enable controller56comprises NMOS transistors N39and N40. The NMOS transistors N39, connected between a data input terminal /Di and the node CN1, has a gate to receive the write control signal ENW, and the NMOS transistor N40, connected between a data input terminal Di and the node CN2, has a gate to receive the write control signal ENW.

The ferroelectric capacitor unit57comprises nonvolatile ferroelectric capacitors FC1˜FC4. The nonvolatile ferroelectric capacitor FC1has one terminal connected to the node CN1and the other terminal to receive the cell plate signal CPL. The nonvolatile ferroelectric capacitor FC2has one terminal connected to the node CN2and the other terminal to receive the cell plate signal CPL. The nonvolatile ferroelectric capacitor FC3is connected between the node CN1and the ground voltage terminal, and the nonvolatile ferroelectric capacitor FC4is connected between the node CN2and the ground voltage terminal. Here, the nonvolatile ferroelectric capacitors FC3and FC4may be selectively added depending on loading level of the nodes CN1and CN2.

The pull-down driver58, connected between the ferroelectric capacitor unit57and the pull-down switch N43, comprises NMOS transistors N41and N42connected with a latch structure between the nodes CN1and CN2. The pull-down switch N43, connected between the pull-down driver58and the ground voltage VSS terminal, has a gate to receive the pull-down enable signal ENN. The program register array46outputs control signals REBi and REi through an output terminal.

FIG. 28is a timing diagram illustrating the operation of the FeRAM register array46ofFIG. 27in a power-up mode.

In an interval T1after the power-up mode, when power voltage VCC reaches a stabilized voltage level, the reset signal RESET becomes at a low level and the power-up detecting signal PUP is at a high level.

Then, the cell plate signal CPL transits to a high level as the power-up detecting signal PUP is at a high level. Here, charges stored in the nonvolatile ferroelectric capacitors FC1and FC2of the program register array46generate a voltage difference between the nodes CN1and CN2by capacitance load of the nonvolatile ferroelectric capacitors FC3and FC4.

In an interval T2, since the sufficient voltage difference between the nodes CN1and CN2is generated, the pull-down enable signal ENN is enabled to a high level, and the pull-up enable signal ENP is disabled to a low level. As a result, data of the nodes CN1and CN2are amplified.

Thereafter, in an interval T3, when data amplification of nodes CN1and CN2is completed, the power-up detecting signal PUP and the cell plate signal CPL transits to the low level again. As a result, the destroyed high data of the nonvolatile ferroelectric capacitor FC1or FC2are restored. Here, the write control signal ENW is maintained at the low level to prevent external data from being re-written.

FIG. 29is a timing diagram illustrating the operation of the FeRAM register array46ofFIG. 27.

When a predetermined time passes after the command signal 1st_CMD is activated to a high level, new data Di and /Di are inputted. When the input data DQi applied from the data input/output pad is disabled from a high to low level, the program cycle starts. As a result, the write control signal ENW to write new data in the register and the cell plate signal CPL transit to a high level. Here, the pull-down enable signal ENN is maintained at the high level, and the pull-up enable signal ENP is maintained at the low level.

If the command signal 1st_CMD having a high level is inputted into the program register controller44, signal input from the program command processor43is prevented. As a result, the program operation can be performed while no more control command is inputted.

As described above, a nonvolatile programmable logic circuit using a ferroelectric memory according to an embodiment of the present invention disconnects power supply during a stand-by mode of the system, thereby reduce power consumption. A nonvolatile register is used by program commands to change the configuration of circuits and parameters, which results in small quantity batch production with a mask set. Also, a nonvolatile ferroelectric memory is applied to a FPGA (Field Programmable Gate Array), thereby preventing leakage of internal data and reducing the area of a chip. Additionally, since a nonvolatile memory function and an operation function are performed with a nonvolatile ferroelectric memory, extra external memory devices are unnecessary.