Semiconductor devices including application processor connected to high-bandwidth memory and low-bandwidth memory, and channel interleaving method thereof

A memory system includes a high-bandwidth memory device, the high-bandwidth memory device having a relatively high operation bandwidth, the high-bandwidth memory device having a plurality of access channels. A low-bandwidth memory device has a relatively low operation bandwidth relative to the high-bandwidth memory device, the low-bandwidth memory device having one or more access channels. An interleaving unit performs a memory interleave operation among the plurality of access channels of the high-bandwidth memory device and an access channel of the one or more access channels of the low-bandwidth memory device.

BACKGROUND

The present inventive concepts herein relate to semiconductor devices, and more particularly, to semiconductor devices including a plurality of different types of memory devices having different bandwidths relative to one another, and to a channel interleaving method thereof.

Semiconductor devices can often times include an application processor (AP), which, in some cases, is embodied in a system on chip (SoC). For example, a mobile system may commonly include a modem and an application processor (AP) or a multimedia processor. Contemporary semiconductor-based electronic systems can require one or more memory devices to support processor operation.

Semiconductor devices can perform interleaving operations among multiple memory devices, i.e. two or more devices, for memory access. That is, a semiconductor device can alternately access two or more memory devices. When this operation is performed, the memory devices are typically of the same type, for example, both of the DRAM type of memory devices. In some cases, a semiconductor device can utilize different types of memory devices. For example, a first memory device can have a relatively high-speed data transmission rate but may be of relatively small memory size and a second memory device can have a relatively low-speed data transmission rate but may be of relatively large memory size.

SUMMARY

In an aspect, a memory system comprises: a high-bandwidth memory device, the high-bandwidth memory device having a relatively high operation bandwidth, the high-bandwidth memory device having a plurality of access channels; a low-bandwidth memory device, the low-bandwidth memory device having a relatively low operation bandwidth relative to the high-bandwidth memory device, the low-bandwidth memory device having one or more access channels; and an interleaving unit that performs a memory interleave operation among the plurality of access channels of the high-bandwidth memory device and an access channel of the one or more access channels of the low-bandwidth memory device.

In some embodiments, the interleaving unit comprises a memory controller in communication with the high-bandwidth memory device and the low-bandwidth memory device.

In some embodiments, the one or more access channels of the low-bandwidth memory device comprises a plurality of access channels and wherein the interleaving unit performs a memory interleave operation among the plurality of access channels of the high-bandwidth memory device and the plurality of access channels of the low-bandwidth memory device.

In some embodiments, the interleaving unit comprises a high-bandwidth channel interleaving unit that manages the memory interleave operation among the plurality of access channels of the high bandwidth memory device.

In some embodiments, the interleaving unit further comprises a low-bandwidth channel interleaving unit that manages the memory interleave operation among the plurality of access channels of only the low-bandwidth memory device.

In some embodiments, the memory system further comprises a router that selects a mode of operation of the memory system among at least one of: an interleave operation among the plurality of access channels of the high-bandwidth memory device; an interleave operation among multiple ones of the one or more access channels of the low-bandwidth memory device; and an interleave operation among the plurality of access channels of the high-bandwidth memory and the at least one of the one or more access channels of the low-bandwidth memory device.

In some embodiments, the memory system further comprises a multiplexer that selects the at least one of the one or more access channels of the low-bandwidth memory device for the interleave operation.

In some embodiments, the interleaving unit comprises; a high-bandwidth channel interleaving unit that manages the memory interleave operation among the plurality of access channels of the high bandwidth memory device; and a low-bandwidth channel interleaving unit that manages the memory interleave operation among the plurality of access channels of only the low-bandwidth memory device; and wherein the multiplexer receives a selection signal from at least one of the high-bandwidth channel interleaving unit, the low-bandwidth channel interleaving unit, and the router.

In some embodiments, the low-bandwidth memory device comprises multiple low-bandwidth memory devices, each low-bandwidth memory device having at least one access channel, and wherein the memory interleave operation is performed among the plurality of access channels of the high-bandwidth memory device and the at least one access channels of the multiple low-bandwidth memory devices.

In some embodiments, the high-bandwidth memory device comprises a Wide I/O memory device; and the low-bandwidth memory device comprises a Low-Power DDR (LPDDR) memory device.

In some embodiments, during a low-power mode of operation of the system, the interleaving unit performs a memory interleave operation only among the one or more access channels of the LPDDR memory device.

In some embodiments, the access channels of the high-bandwidth memory device and the low bandwidth memory device among which the interleave operation is performed comprise assigned segments of memory that have a same memory size and have a same access rate.

In some embodiments, the high-bandwidth memory device is fabricated on a first chip and wherein an application processor including the interleaving unit is fabricated on a second chip and wherein the first chip and the second chip are connected to one another using a through-silicon via connection arrangement.

In some embodiments, the first chip and second chip are mounted to a first printed circuit board and packaged collectively in a first chip package; the low-bandwidth memory device is fabricated on a third chip mounted to a printed circuit board, wherein the third chip is connected to the printed circuit board by a wiring arrangement, and wherein the third chip and second printed circuit board are packaged collectively in a second package; and the first chip package and second chip package are connected to each other by a wiring arrangement.

In an aspect, a system on a chip comprises a memory controller; a high-bandwidth memory device in communication with the memory controller, the high-bandwidth memory device having a relatively high operation bandwidth, the high-bandwidth memory device having a plurality of access channels, the high-bandwidth memory device comprising a WideIO type memory device; a low-bandwidth memory device in communication with the memory controller, the low-bandwidth memory device having a relatively low operation bandwidth, relative to the high-bandwidth memory device, the low-bandwidth memory device having one or more access channels, the low-bandwidth device comprising a Low-Power DDR type memory device; and an interleaving unit that performs a memory interleave operation among the plurality of access channels of the high-bandwidth memory device and an access channel of the one or more access channels of the low-bandwidth memory device.

In some embodiments, the system on a chip further comprises: a first chip on which the memory controller is fabricated; at least one second chip on which at least one corresponding high-bandwidth memory devices is fabricated; wherein the at least one second chip is stacked on the first chip.

In some embodiments, the at least one second chip is connected to the first chip using a through-silicon via connection arrangement.

In some embodiments, the at least one second chip on which at least one corresponding high-bandwidth memory devices is fabricated comprises multiple second chips including multiple high-bandwidth memory devices.

In some embodiments, the Low-Power DDR type memory device comprises at least one of a LPDDR1, LPDDR2, LPDDR3, LPDDR4, or LPDDR5 generation device.

In some embodiments, during a low-power mode of operation of the system, the interleaving unit performs a memory interleave operation only among the one or more access channels of the LPDDR memory device.

In some embodiments, the access channels of the high-bandwidth memory device and the low bandwidth memory device among which the interleave operation is performed comprise assigned segments of memory that have a same memory size and have a same access rate.

In another aspect, a channel interleaving unit for a memory system comprises: a high-bandwidth channel interleaver that performs a memory interleave operation among a plurality of access channels of a high-bandwidth memory device; a low-bandwidth channel interleaver that performs a memory interleave operation among a plurality of access channels of a low-bandwidth memory device; and a router that, in response to a memory access command, controls operation of the high-bandwidth channel interleaver and the low-bandwidth channel interleaver to initiate an interleave operation among the plurality of access channels of the high-bandwidth memory device and an access channel of the one or more access channels of the low-bandwidth memory device.

In some embodiments, the high-bandwidth memory device has a relatively high operation bandwidth, wherein the low-bandwidth memory device has a relatively low operation bandwidth, relative to the high-bandwidth memory device.

In some embodiments, the high-bandwidth memory device comprises a Wide I/O memory device; and wherein the low-bandwidth memory device comprises a Low-Power DDR (LPDDR) memory device.

In some embodiments, the router further selects a mode of operation of among at least one of: an interleave operation among the plurality of access channels of the high-bandwidth memory device; an interleave operation among multiple ones of the one or more access channels of the low-bandwidth memory device; and an interleave operation among the plurality of access channels of the high-bandwidth memory and the at least one of the one or more access channels of the low-bandwidth memory device.

In some embodiments, the channel interleaving unit further comprises a multiplexer that selects the at least one of the one or more access channels of the low-bandwidth memory device for the interleave operation.

In an aspect, a method of performing an interleaving operation in a memory system, comprises: partitioning a high-bandwidth memory device into a plurality of first segments, the first segments having a same access size and a same access rate, the high-bandwidth memory device having a relatively high operation bandwidth, the high-bandwidth memory device having a plurality of first access channels, each first access channel corresponding to one of the first segments; partitioning a low-bandwidth memory device into a plurality of second segments, the second segments having a same access size and a same access rate as each other, the low-bandwidth memory device having a relatively low operation bandwidth, relative to the high-bandwidth memory device; the low-bandwidth memory device having a plurality of second access channels, each second access channel corresponding to one of the second segments; and performing a memory interleave operation among the plurality of first access channels of the high-bandwidth memory device and at least one second access channel of the plurality of access channels of the low-bandwidth memory device.

In some embodiments, the high-bandwidth memory device comprises a Wide I/O memory device; and wherein the low-bandwidth memory device comprises a Low-Power DDR (LPDDR) memory device.

In some embodiments, the second segments have a same access size and a same access rate as those of the first segments,

In some embodiments, the low-bandwidth memory device has an available access size and wherein the combined access sizes of the second segments is less than the available access size.

In some embodiments, during a low-power mode of operation of the system, the interleave operation is performed only among the one or more access channels of the low-bandwidth memory device.

In some embodiments, during a low-power mode of operation of the system, the interleave operation is performed only among the one or more access channels of the high-bandwidth memory device.

In some embodiments, the interleave operation is performed among the plurality of first access channels of the high-bandwidth memory device and at least one second access channel of the plurality of access channels of the low-bandwidth memory device, during a high-power mode of operation of the system.

In an aspect, a method of performing an interleaving operation in a memory system including a high-bandwidth memory device and a low-bandwidth memory device, comprises: receiving a request for a memory access operation; determining whether an available memory region of the high-bandwidth memory is sufficient for processing the request; assigning a channel identification in response to the request; and if the available memory region of the high-bandwidth memory is insufficient for processing the request, performing a channel interleaving operation in response to the channel identification among a plurality of access channels of the high-bandwidth memory device and an access channel of one or more access channels of the low-bandwidth memory device.

In some embodiments, the memory access operation is a write operation

In some embodiments, the memory access operation is a read operation

In an aspect, a mobile device comprises: a memory system comprises: a high-bandwidth memory device, the high-bandwidth memory device having a relatively high operation bandwidth, the high-bandwidth memory device having a plurality of access channels; a low-bandwidth memory device, the low-bandwidth memory device having a relatively low operation bandwidth relative to the high-bandwidth memory device, the low-bandwidth memory device having one or more access channels; and an interleaving unit that performs a memory interleave operation among the plurality of access channels of the high-bandwidth memory device and an access channel of the one or more access channels of the low-bandwidth memory device. an input device at which a user provides user input to the memory system; and a display that provides information output by the memory system.

In some embodiments, the mobile device further comprises a mobile power source.

In some embodiments, the mobile device comprises a system-on-a-chip.

In an aspect, a system on chip (SoC) comprises: a high-bandwidth memory device having a plurality of access channels; a first low-bandwidth memory device having one or more access channels, the high-bandwidth memory device having a higher operation bandwidth than the first low-bandwidth memory device; and an interleaving unit configured to perform a memory interleave operation among the plurality of access channels of the high-bandwidth memory device and at least one of the one or more access channels of the first low-bandwidth memory device.

In some embodiments, the interleaving unit comprises a memory controller in communication with the high-bandwidth memory device and the first low-bandwidth memory device.

In some embodiments, the first low-bandwidth memory device comprises a plurality of access channels, and the interleaving unit performs a memory interleave operation among the plurality of access channels of the high-bandwidth memory device and the plurality of access channels of the first low-bandwidth memory device.

In some embodiments, the interleaving unit comprises a high-bandwidth channel interleaver configured to manage the memory interleave operation among the plurality of access channels of the high-bandwidth memory device and the at least one of the one or more access channels of the first low-bandwidth memory device.

In some embodiments, the interleaving unit further comprises a low-bandwidth channel interleaver configured to manage the memory interleave operation among the remaining access channels of the first low-bandwidth memory device other than the at least one access channel of the first low-bandwidth memory device managed by the high-bandwidth channel interleaver.

In some embodiments, the interleaving unit performs a mode of operation of the SoC among one of: an interleave operation among the plurality of access channels of the high-bandwidth memory device; an interleave operation among the one or more access channels of the first low-bandwidth memory device; and an interleave operation among the plurality of access channels of the high-bandwidth memory and the at least one of the one or more access channels of the first low-bandwidth memory device.

In some embodiments, the SoC further comprises a second low-bandwidth memory device, wherein the second low-bandwidth memory device includes one or more access channels, and the memory interleave operation is performed among the plurality of access channels of the high-bandwidth memory device, the at least one of one or more access channels of the first low-bandwidth memory device, and at least one of the one or more access channels of the second low-bandwidth memory device.

In some embodiments, the high-bandwidth memory device comprises a Wide I/O memory device; and the low-bandwidth memory device comprises a Low-Power DDR (LPDDR) memory device.

In some embodiments, during a low-power mode of operation of the SoC, the interleaving unit performs the memory interleave operation among the plurality of access channels of the Wide I/O memory device.

In some embodiments, during a high-power mode of operation of the SoC, the interleaving unit performs the memory interleave operation among the plurality of access channels of the Wide I/O memory device and the at least one of the one or more access channels of the LPDDR memory device.

In some embodiments, a bandwidth of the high-bandwidth memory device is evenly divided by the number of access channels of the high-bandwidth memory device, and the high-bandwidth memory device performs data communication via each access channel with the evenly divided bandwidth.

In some embodiments, a bandwidth of the low-bandwidth memory device is evenly divided by the number of access channels of the low-bandwidth memory device, and when the evenly divided bandwidth of the low-bandwidth memory device is less than the evenly divided bandwidth of the high-bandwidth memory device, the interleaving unit performs a portion of a memory access command using at least two access channels of the low-bandwidth memory device.

In some embodiments, the high-bandwidth memory device is fabricated on a first chip, an application processor including the interleaving unit is fabricated on a second chip, and the first chip and the second chip are connected to one another using a through-silicon via connection arrangement.

In some embodiments, the first chip and second chip are mounted to a first printed circuit board and packaged collectively in a first chip package, the low-bandwidth memory device is fabricated on a third chip mounted to a second printed circuit board, the third chip is connected to the second printed circuit board by a wiring arrangement, the third chip and the second printed circuit board are packaged collectively in a second package; and the first chip package and the second chip package are connected to each other by a wiring arrangement.

In an aspect, a system on chip (SoC) comprises: a memory controller; a high-bandwidth memory device in communication with the memory controller, the high-bandwidth memory device having a plurality of access channels, the high-bandwidth memory device comprising a Wide I/O type memory device; a low-bandwidth memory device in communication with the memory controller, the low-bandwidth memory device having one or more access channels, the low-bandwidth device comprising a Low-Power DDR type memory device, the high-bandwidth memory device having a higher operation bandwidth than the first low-bandwidth memory device; and an interleaving unit configured to perform a memory interleave operation among the plurality of access channels of the high-bandwidth memory device and at least one of the one or more access channels of the low-bandwidth memory device.

In some embodiments, the SoC further comprises: a first chip on which the memory controller is fabricated; and at least one second chip on which the high-bandwidth memory device is fabricated, wherein the at least one second chip is stacked on the first chip.

In some embodiments, the at least one second chip comprises a plurality of second chips, each of the plurality of second chips including one or more Wide I/O type memory devices.

In an aspect, a channel interleaving unit for a system on chip (SoC) comprises: a high-bandwidth channel interleaver configured to perform a memory interleave operation among a plurality of access channels of a high-bandwidth memory device and at least one of one or more access channels of a low-bandwidth memory device; a low-bandwidth channel interleaver configured to perform the memory interleave operation among at least one access channel of the low-bandwidth memory device; and a router configured to receive memory access commands and determine whether each of the memory access commands is transmitted to the high-bandwidth channel interleaver or to the low-bandwidth channel interleaver based on an address of each of the memory access commands.

In some embodiments, the channel interleaving unit further comprises a multiplexer configured to perform an arbitration among the memory access commands.

In some embodiments, the multiplexer performs the arbitration based on priority information.

In some embodiments, the priority information includes priority information of each of the memory access commands and status information of the channel interleaving unit, the status information including urgent information of the high-bandwidth channel interleaver, urgent information of the low-bandwidth channel interleaver and urgent information of the router, the urgent information being generated based on status of a buffer for storing the memory access commands.

In an aspect, a mobile device comprises: a system on chip (SoC) comprises: a high-bandwidth memory device having a plurality of access channels; a low-bandwidth memory device having one or more access channels, the high-bandwidth memory device having a higher operation bandwidth than the first low-bandwidth memory device; and an interleaving unit configured to perform a memory interleave operation among the plurality of access channels of the high-bandwidth memory device and at least one of the one or more access channels of the low-bandwidth memory device; an input device at which a user provides user input to the SoC; and a display configured to provide information output by the SoC.

DETAILED DESCRIPTION OF EMBODIMENTS

Semiconductor devices in accordance with embodiments of the inventive concepts can employ a portion of a low-bandwidth memory (for example, LPDDRx type memory) as a high-bandwidth region when a memory size of the high-bandwidth memory (for example, WideIO type memory) is insufficient by performing a channel interleaving operation on different types of two or more memories that have different bandwidths relative to one another. Hereinafter, a channel interleaving operation of a semiconductor device in accordance with embodiments of the inventive concepts will be described.

FIG. 1is a block diagram illustrating a semiconductor device in accordance with embodiments of the inventive concepts. Referring toFIG. 1, a semiconductor device100includes a high bandwidth memory device111, a low bandwidth memory device112and an application processor (AP)120.

InFIG. 1, the high bandwidth memory device111and the application processor120can, in some embodiments, be embodied in a system-on-a-chip (SoC) configuration. In other embodiments, the high bandwidth memory device111, the low bandwidth memory device112and the application processor120can together be embodied in a SoC configuration.

In some embodiments, the application processor120can include one or more of a memory controller130, a central processing unit (CPU)150, a multimedia processor160and a modem processor170for accessing the high bandwidth memory device111and the low bandwidth memory device112. One or more of the memory controller130, the central processing unit (CPU)150, the multimedia processor160and the modem processor170can be connected to, and communicate with, one another through a bus connection unit121.

In some embodiments, the high bandwidth memory device111is connected to the memory controller130through one or more channels, and in the present example embodiment, four channels CH1˜CH4. The low bandwidth memory device112is connected to the memory controller130through one or more channels, and in the present embodiment, two channels CHa and CHb. If it is assumed that one channel transmits data of 128 bits in width, the high bandwidth memory device111has a bandwidth that can transmit data of 512 bits and the low bandwidth memory device112has a bandwidth that can transmit data of 256 bits. High bandwidth memory devices and low bandwidth memory devices with other numbers of channels, and other data widths, are equally applicable to the principles of the present inventive concepts.

In the present exemplary embodiment, the memory controller130accesses the high bandwidth memory device111through the channels CH1˜CH4and accesses the low bandwidth memory device112through the channels CHa and CHb. In some embodiments, the central processing unit150controls an overall operation of the application processor120and can be configured to control the operation of peripheral devices like the high bandwidth memory device111and the low bandwidth memory device112including controlling the operations of read and write access from and to these devices111,112.

In some embodiments, the multimedia processor160is operable to process multimedia data and control a multimedia device such as a camera and/or a display. In some embodiments, the multimedia processor160is configured to access the high bandwidth memory device111and the low bandwidth memory device112that are connected to the application processor120using a channel interleaving operation as described herein. In this manner, the multimedia device can be controlled with access to the channels of the high bandwidth memory device111and the low bandwidth memory device112in a channel-interleaved arrangement.

In some embodiments, the modem processor170is configured to perform wireless communication with a base station or other communication devices. Like the multimedia processor160, in embodiments of the present inventive concepts, the modem processor170can access channels of the high bandwidth memory device111and the low bandwidth memory device112in a channel interleaving arrangement.

FIG. 2is a block diagram conceptually illustrating a channel interleaving operation of the semiconductor device illustrated herein, in accordance with embodiments of the present inventive concepts. In some embodiments, the memory controller130(refer toFIG. 1) receives a memory access address ADDR and performs a channel interleaving operation on the high bandwidth memory device111and the low bandwidth memory device112. In this manner, in some embodiments, the channel interleaving operation performs interleaving among at least one of high-bandwidth channels CH1˜CH4and at least one of the low-bandwidth channels CHa˜CHb. In some embodiments, the channel interleaving operation performs interleaving among at least two of high-bandwidth channels CH1˜CH4and at least one of the low-bandwidth channels CHa˜CHb. In some embodiments, the channel interleaving operation performs interleaving among at least two of high-bandwidth channels CH1˜CH4and at least two of the low-bandwidth channels CHa˜CHb. In some embodiments, the channel interleaving operation performs interleaving among all available channels CH1˜CHn of the high-bandwidth memory device and all available channels CHa˜CHx of the low-bandwidth channels memory device.

The memory controller130can write data to the high bandwidth memory device111or read data from the high bandwidth memory device111through the first through fourth channels CH1˜CH4. In general, the term “access” as used herein refers to writing data to the memory devices111,112, and/or reading data from the memory devices111,112In some embodiments, the memory controller130can access the first through fourth channels CH1˜CH4of the high bandwidth memory device111and at least a portion of channels of the low bandwidth memory device112. In the example embodiment ofFIG. 2, the memory controller130accesses all the channels CHa and CHb of the low bandwidth memory device112. However, as described herein, the memory controller130may optionally be configured to instead access a subset, part, or portion of the channels CHa and CHb of the low bandwidth memory device112.

By virtue of systems and method of the present inventive concepts, the memory controller130can extend the memory size of the high bandwidth memory device111, and/or can increase the bandwidth of the high bandwidth memory device111by utilizing at least a portion of channels of the low bandwidth memory device112through a channel interleaving operation. InFIG. 2, the memory controller130utilizes four channels of the high bandwidth memory device111and two channels of the low bandwidth memory device112to perform a channel interleaving operation among six channels of the devices,111,112.

In accordance with the inventive concepts, at least a portion of channels of the low bandwidth memory device112can be utilized by dividing a channel of the low bandwidth memory device112and/or by combining channels of the low-bandwidth memory device112to match the channel size of the high bandwidth memory device111. In this manner, a channel interleaving operation can be performed according to the additional memory size or a bandwidth needed by the high bandwidth memory device111. Accordingly, the semiconductor device100can extend a memory size of a bandwidth of the high bandwidth memory device111by utilizing at least a portion of the low bandwidth memory device112as a high bandwidth region through a channel interleaving operation.

FIG. 3is a schematic view illustrating an example of enlarging the memory size of a high bandwidth region of the semiconductor device illustrated inFIG. 1, in accordance with the present inventive concepts.

Referring toFIG. 3, in this example, the high bandwidth memory device111and the low bandwidth memory device112are each assumed to have a memory size of 2 GB respectively.

In the semiconductor device100, a high bandwidth region101can be extended to 3 GB by performing a channel interleaving operation. Accordingly, the remaining low bandwidth region102becomes 1 GB in size. InFIG. 3, an extension portion103is actually a portion of the low bandwidth memory device112but is used or borrowed for the high bandwidth region101of the overall system.

The semiconductor device100can use a part of extension region103, extended from the low bandwidth memory device112, as the high bandwidth region101by performing a channel interleaving operation between different kinds of memories having different bandwidths relative to one another. According to the inventive concepts, a high-bandwidth memory device with would otherwise be insufficient in size for a given application or operation can be extended by borrowing one or more segments from the low-bandwidth memory device while maintaining a high bandwidth operation characteristic of the high bandwidth memory device111.

FIG. 4is a block diagram illustrating another example of a channel interleaving operation of semiconductor devices in accordance with the present inventive concepts. Referring toFIG. 4, a semiconductor device200includes a WideIO memory device211(operating as a high-bandwidth memory device), an LPDDRx memory device212(operating as a low-bandwidth memory device), and an application processor220. InFIG. 4, the WideIO memory device211and the application processor can be embodied in a system-on-chip (SoC) configuration, as shown and described herein in connection withFIG. 18. In other embodiments, the WideIO memory211, the LPDDRx memory device212and the application processor220can be embodied in a system on chip (SoC) configuration, as shown and described herein in connection withFIG. 17.

In the present example, the WideIO memory device211can be considered a high bandwidth memory and the LPDDRx memory device212can be considered a low bandwidth memory. The WideIO memory device211and the LPDDRx memory device212commonly are used as a low power memory or a mobile memory in a mobile device such as a smart phone, a tablet PC, and other mobile devices.

Over time, the LPDDRx (low power double data rate) memory212has been manifested as LPDDR1, LPDDR2, LPDDR3, LPDDR4, etc. devices, according to adaptations in the related JEDEC standards. The LPDDR1 device was originally designed to reduce total power consumption of a DDR SDRAM and the supply voltage of the LPDDR1 was lowered from 2.5V to 1.8V, as compared with an SDRAM. The LPDDR1 family of devices reduces power consumption by reducing the number of times refresh operations are performed relative to temperature, since it was determined that LPDDR1 requires a lower memory refresh frequency when operating in a lower temperature. The LPDDR2 family of devices basically maintains the low power state similar to the LPDDR1 and further includes a function refresh operations can be performed only on a portion of memory columns, further reducing the impact of memory refresh on power consumption and device performance.

Mobile memory devices that have been developed following the LPDDR2 include the LPDDR3 (or LPDDR4) devices and the WideIO memory devices211. The LPDDR3 (or LPDDR4) provides a relative increase a data transmission speed over earlier generations by increasing the operation speed of a memory. For example, the LPDDR2 has a maximum operation frequency of 533 MHz, while the LPDDR3 has a maximum operation frequency of 800 MHz.

The WideIO memory devices211extend bandwidth and increase data transmission amount over the LPDDRx device family by greatly increasing the number of input/output terminals. The WideIO memory device211also reduces power consumption by reducing operation frequency. For example, in some embodiments, the WideIO memory device211is configured to exchange data through four channels, with each channel having a bandwidth of 128 bits. An operation frequency of each channel is 200 MHz, which corresponds roughly to half the operation frequency of the LPDDR2.

The WideIO memory device211offers a relatively low operation frequency but, at the same time, a relatively more data transmission. In view of the fact that a WideIO memory device211has a wide bandwidth of 512 bits, it has a relatively high speed of data transmission of 12.8 GBps (or 25.6 GBps) at a relatively low operation frequency of 200 MHz. This corresponds roughly to two times the data throughput in comparison with the LPDDR3, which has a data transmission speed of 6.4 GBps (or 12.8 GBps) at an operation frequency of 800 MHz.

Returning toFIG. 4, in some embodiments, the WideIO memory device211can be directly connected to the application processor220using a through silicon via (TSV) technology. That is, the WideIO memory device211can be stacked on the application processor220in the same chip package using TSV technology. Such a configuration offers reduced delay time, reduced power consumption and increased data throughput.

In some embodiments, the WideIO memory device211can be divided into four regions and an input/output pad of each bank can be located in a central region of a silicon die. An input/output pad supporting a bandwidth of 128 bits is located in each bank. An input/output pad of each bank can be connected to the application processor220through a channel CH1˜CH4.

In the present embodiment ofFIG. 4, the application processor220includes memory controllers231˜234,23a, and23b, a channel interleaving unit240, a central processing unit (CPU)250, a multimedia processor260and a modem processor270. One or more of the channel interleaving unit240, central processing unit (CPU)250, multimedia processor260and modem processor270can be connected to one another through a bus connection unit221.

In some embodiments, the application processor220includes the memory controllers231˜234,23a, and23bconfigured to access the WideIO memory device211and the LPDDRx memory device212. In some embodiments, the memory controllers231˜234,23a, and23bcan be connected to the WideIO memory device211or the LPDDRx memory device212through channels CH1˜CH4, CHa˜CHb.

In the present example embodiment, the first controller231is connected to the WideIO memory device211through a first channel CH1. The second through fourth memory controllers232˜234are similarly connected to the WideIO memory device211through second through fourth channels CH2˜CH4. Similarly, a memory controller23ais connected to the LPDDRx memory device212through a channel CHa. A memory controller23bis connected to the LPDDRx memory device212through a channel CHb.

If it is assumed that one channel transmits data of 128 bits, the WideIO memory device211has a bandwidth that can transmit data of 512 bits and the LPDDRx memory device212has a bandwidth that can transmit data of 256 bits. The application processor220can be configured to access portions of the WideIO memory device211and the LPDDRx memory device212through a channel interleaving operation.

The channel interleaving unit240operates to control a channel interleaving operation of the application processor220. Referring toFIG. 4, the channel interleaving unit240includes a high bandwidth channel interleaver241, a low bandwidth channel interleaver242and a router243.

The high bandwidth channel interleaver241performs a channel interleaving operation not only among channels of the WideIO memory device211, but rather among channels of both the WideIO memory device211and the LPDDRx memory device212. The low bandwidth channel interleaver242can perform a channel interleaving operation among the a channel CHa and the b channel CHb of the LPDDRx memory device212.

In an example scenario, the router243receives a request for a channel interleaving, for example, in the form of a memory access command, and designates one access to a high bandwidth region or a low bandwidth region. In the case where the router243designates access to the high bandwidth region, the high bandwidth channel interleaver241is selected, and in a case where the router243designates access to the low bandwidth region, the low bandwidth channel interleaver242is selected. In a case where the router243extends the high bandwidth region of the WideIO memory device211to the LPDDRx memory device212, the router243can extend the high-bandwidth region to include a path to the a channel CHa and the b channel CHb of the LPDDRx memory device212. In this manner, the router243can be configured to receive memory access commands and determine, in response to the commands, whether the memory access command is to be transmitted to the high-bandwidth channel interleaver241or the low-bandwidth channel interleaver242. In some embodiments, the determination can be made based on an address associated with each of the memory access commands.

The central processing unit250controls an overall operation of the application processor220and can optionally further control a channel interleaving operation among the WideIO memory device211and the LPDDRx memory device212. The multimedia processor260can optionally access the WideIO memory device211and the LPDDRx memory device212that are connected to the application processor220to process multimedia data and control a multimedia device (not illustrated) external the application processor220. The modem processor270is a processor for performing a wireless communication with a base station or other communication devices and can be configured to access the WideIO memory device211and the LPDDRx memory device212in a manner similar to the multimedia processor260.

Performance of an external device such as a multimedia device or a communication device connected to the application processor220to be used continues to increase As a result, a main region (for example, the WideIO memory device211) required by a mobile AP commonly needs to satisfy the requirements of high bandwidth data transmission and large memory size at the same time.

FIG. 5is a block diagram illustrating an example embodiment in which case the channel interleaving unit of the semiconductor device illustrated inFIG. 4further includes a multiplexer MUX. Referring toFIG. 5, in this embodiment, the channel interleaving unit240includes the high bandwidth channel interleaver241, the low bandwidth channel interleaver242, the router243and the multiplexer244.

The multiplexer244is constructed and arranged to receive a signal from the high bandwidth channel interleaver241and the low bandwidth channel interleaver242, and to select which of the channels of the interleavers241,242is applied to the a channel CHa and the b channel CHb of the LPDDRx memory device212. The multiplexer244can be configured to select none of the channels of the LPDDRx memory device212, to select all the channels of the LPDDRx memory device212or to select a portion of the channels of the LPDDRx memory device212for interleaving with the channels of the WideIO memory device. A select signal of the multiplexer244can be provided from the high bandwidth channel interleaver241, the low bandwidth channel interleaver242or the router243. The inventive concept can select and utilize the channels of the LPDDRx memory device212in an interleaving operation with the channels of the WideIO memory device, as described herein. In some embodiments, the multiplexer244is configured to perform an arbitration among the received memory access commands. In some embodiments, the multiplexer244performs the arbitration based on priority information. In some embodiments, the priority information includes priority information of each of the received memory access commands and status information of the channel interleaving unit240, the status information including urgent information of the high bandwidth channel interleaver241, urgent information of the low-bandwidth channel interleaver242and urgent information of the router243. In some embodiments, the urgent information being generated based on a status of a buffer for storing the memory access commands.

As described herein, the WideIO memory device211is suitable for transmitting data due to its relatively high bandwidth capabilities, however may be limited in its ability to increase in memory size. The semiconductor device200in accordance with the inventive concepts can supplement insufficiencies in memory size of the WideIO memory device211by utilizing the LPDDRx memory device212. The inventive concepts allow for this by providing systems and methods that perform a channel interleaving operation among channels of the WideIO memory device and the LPDDRx memory device to further extend the high bandwidth region of the device200

In some embodiments, during a low-power mode of operation of the SoC, the interleaving unit240performs the memory interleave operation among the plurality of access channels of the Wide I/O memory device. In some embodiments, during a high-power mode of operation of the SoC, the interleaving unit performs the memory interleave operation among the plurality of access channels of the Wide I/O memory device and the at least one of the one or more access channels of the LPDDR memory device.

FIGS. 6-11are schematic views for explaining a channel interleaving operation of the semiconductor device illustrated herein, in accordance with the inventive concepts.

Referring toFIG. 6, the WideIO memory device211is connected to the application processor220through the first through fourth channels CH1˜CH4and has a memory size of 1 GB and a data transmission speed of 25.6 GBps. The WideIO memory device211can be partitioned into chunk units. In some embodiments, a data size of a first chunk is 256 MB and first chunk data is transmitted through the first channel CH1at a speed of 6.4 GBps. Similarly, second through fourth chunk data are transmitted through the second through fourth channels CH2˜CH4respectively, each having a size of 256 MB and a speed of 6.4 GBps.

The LPDDRx memory device212is connected to the application processor220through the a channel CHa and the b channel CHb and has a memory size of 2 GB and a data transmission speed of 12.8 GBps. Like the WideIO memory device211, the LPDDRx memory device212can be partitioned into chunk units. A data size of a fifth chunk is 256 MB and fifth chunk data is transmitted through the a channel CHa at a speed of 6.4 GBps. Similarly, sixth chunk data has a data size of 256 MB and is transmitted through the b channel CHb at a speed of 6.4 GBps.

To further illustrate the inventive concepts, referring back to the embodiment ofFIGS. 1-4, for example, the CPU150, Multimedia Processor160, modem170, or the like, such devices referred to herein collectively as a “master”, can generate one or more requests to access the memory devices111,112. In an example embodiment, the master150,160,170can generate first and second access requests, each request including address information. In the event the address of the first request is assigned to a high-bandwidth region101of memory, a router243of the channel interleaving unit240can be configured to transmit the first request to the high bandwidth channel interleaver241. Accordingly, the first request is partitioned into 6 pieces by the high bandwidth channel interleaver241, which high bandwidth channel interleaver241, in turn, transmits 4 pieces to WideIO Memory211through memory controllers 1-4231-234and the other 2 pieces to LPDDRx Memory212through memory controller23a,23b. Assuming the address of the second request is assigned to a low-bandwidth region102of memory, the router243can be configured to transmit the request to the low-bandwidth channel interleaver242. As a result, the second request is divided into 2 pieces by the low-bandwidth channel interleaver242. The low-bandwidth channel interleaver242operates to transmit the 2 pieces of the second request to LPDDRx Memory212through the memory controller23a,23b.

Further to the present example, in the event a CPU150generates a first request that includes address information assigned to the high-bandwidth region, and Multimedia Processor160generates a second request that includes address information assigned to the low-bandwidth region at the same time as the first request, the router243will transmit the first request to the high-bandwidth channel interleaver241and the second request242to the low-bandwidth channel interleaver. Accordingly, the two pieces of the first request and the second request will result in a conflict in access to the LPDDRx Memory212. In such a case, the memory Controller23a,23bor MUX244can be configured to arbitrate the priority of the conflicting requests.

Referring toFIG. 7, in some embodiments, the SOC comprises an application processor220, a WideIO Memory211having a data transmission speed of 25.6 GBps and 4 channels, and a LPDDRx Memory212having a data transmission speed of 18 GBps and 6 channels. Each channel of WideIO memory211is allocated 6.4 GBps and each channel of LPDDRx memory212is allocated 3 GBps. In the present example, it is assumed that a high bandwidth request is to be divided into 5 pieces. In this case, piece 5 of the high bandwidth request is allocated to be serviced by 3 channels of LPDDRx memory212, because the piece 5 of the high-bandwidth request requires at least 6.4 GB/s bandwidth to meet the requirements of the channel data transmission rates of the other four pieces 1˜4 of the high-bandwidth request. The other 3 channels of the LPDDRx memory212can be reserved to service low-bandwidth requests. Accordingly, in the event the CPU250generates a first request that includes address information assigned to the high-bandwidth region and the Multimedia Processor260generates a second request that includes address information assigned to the low bandwidth region at the same time, the router243will transmit the first request to the high-bandwidth channel interleaver241and the second request to the low-bandwidth channel interleaver242(seeFIG. 5). Accordingly, the high-bandwidth channel interleaver241services the 1st, 2nd, 3rd, and 4th pieces of the high-bandwidth request through 4 channels of WideIO Memory211, and the low-bandwidth channel interleaver242services the 5th piece of the high-bandwidth request through 3 channels of LPDDRx memory212and services the low-bandwidth request through the other 3 channels of LPDDRx memory212.

Referring toFIG. 8, in some embodiments, the SOC comprises an application processor220, a WideIO Memory211having a data transmission speed of 25.6 GBps and 4 channels, and a LPDDRx Memory212having a data transmission speed of 12.8 GBps and 4 channels. Each channel of WideIO memory211is allocated 6.4 GBps and each channel of LPDDRx memory212is allocated 3.2 GBps. In the present example, it is assumed that a high bandwidth request is to be divided into 5 pieces. In this case, piece 5 of the high bandwidth request is allocated to be serviced by 2 channels of LPDDRx memory212, because the piece 5 of the high-bandwidth request requires at least 6.4 GB/s bandwidth to meet the requirements of the channel data transmission rates of the other four pieces 1-4 of the high-bandwidth request. The other 2 channels of the LPDDRx memory212can be reserved to service low-bandwidth requests. Accordingly, in the event the CPU250generates a first request that includes address information assigned to the high-bandwidth region and the Multimedia Processor260generates a second request that includes address information assigned to the low bandwidth region at the same time, the router243will transmit the first request to the high-bandwidth channel interleaver241and the second request to the low-bandwidth channel interleaver242(seeFIG. 5). Accordingly, the high-bandwidth channel interleaver241services the 1st, 2nd, 3rd, and 4th pieces of the high-bandwidth request through 4 channels of WideIO Memory211, and the low-bandwidth channel interleaver242services the 5th piece of the high-bandwidth request through 2 channels of LPDDRx memory212and services the low-bandwidth request through the other 2 channels of LPDDRx memory212.

Referring toFIG. 9, in some embodiments, the SOC comprises an application processor220, a WideIO Memory211having a data transmission speed of 25.6 GBps and 4 channels, and a LPDDRx Memory212having a data transmission speed of 6.4 GBps and 2 channels. Each channel of WideIO memory211is allocated 6.4 GBps and each channel of LPDDRx memory212is allocated 3.2 GBps. In the present example, it is assumed that a high bandwidth request is to be divided into 5 pieces. In this case, piece 5 of the high bandwidth request is allocated to be serviced by 2 channels of LPDDRx memory212, because the piece 5 of the high-bandwidth request requires at least 6.4 GB/s bandwidth to meet the requirements of the channel data transmission rates of the other four pieces 1-4 of the high-bandwidth request. Accordingly, in the event the CPU250generates a first request that includes address information assigned to the high-bandwidth region and the Multimedia Processor260generates a second request that includes address information assigned to the low bandwidth region at the same time, the router243will transmit the first request to the high-bandwidth channel interleaver241and the second request to the low-bandwidth channel interleaver242(seeFIG. 5). Accordingly, the high-bandwidth channel interleaver241services the 1st, 2nd, 3rd, and 4th pieces of the high-bandwidth request through 4 channels of WideIO Memory211, and the low-bandwidth channel interleaver242services the 5th piece of the high-bandwidth request through 2 channels of LPDDRx memory212. In this manner, the low-bandwidth channel interleaver first services the 5th piece of the high-bandwidth request through 2 channels of LPDDRx memory212and then services a low-bandwidth request through the through 2 channels of LPDDRx memory212.

Referring toFIG. 10, in this example, before the application processor220performs a channel interleaving operation, the WideIO memory device211had a memory size of 1 GB and a data transmission bandwidh of 25.6 GBps and the LPDDRx memory device212had a memory size of 2 GB and a data transmission bandwidth of 12.8 GBps. As illustrated inFIG. 10, prior to the interleaving operation, a high bandwidth region has a memory size of 1 GB corresponding to the WideIO memory211. A low bandwidth region has a memory size of 2 GB corresponding to the LPDDRx memory device212.

In accordance with the inventive concepts, the application processor220can assign a portion203(see hashed region) of the LPDDRx memory device212as a high bandwidth region by virtue of a channel interleaving operation in accordance with the inventive concepts. The portion203which belongs to the LPDDRx memory device212but is used as a high bandwidth region includes two chunk data portions (refer to the fifth and sixth chunks ofFIG. 6) and has a memory size of 0.5 GB and a data transmission bandwidth of 12.8 GBps. Referring toFIG. 10, during a channel interleaving operation, the high bandwidth region201has a memory size of 1.5 GB and a data transmission bandwidth of 38.4 GBps. The remaining low bandwidth region202has a memory size of 1.5 GB.

Referring toFIG. 11, in an exemplary embodiment, the memory size of the high bandwidth region201can be extended from 1 GB to 1.5 GB by incorporating a channel interleaving operation in accordance with the present inventive concepts. That is, the application processor220can, by initiating the interleaving operation, cause the high bandwidth region201to have a memory size of 1.5 GB and a data transmission bandwidth of 38.4 GBps using the first through fourth chunks (chunk1˜chunk4) of the WideIO memory device211and the fifth and sixth chunks (chunk5and chunk6) of the LPDDRx memory device212.

FIG. 12is a block diagram illustrating a semiconductor device in accordance with another embodiment of the inventive concepts. Referring toFIG. 12, a semiconductor device300includes a WideIO memory device311, a first LPDDRx memory device312, a second LPDDRx memory device313and an application processor320. In some embodiments, the WideIO memory device311and the application processor320can be embodied in a system on chip (SoC), for example, as shown in the embodiment ofFIG. 18.

In the present embodiment, the WideIO memory device311can be considered a high bandwidth memory device and the first and second LPDDRx memories312and313can be considered a low bandwidth memory device. The application processor320includes memory controllers331˜334,33aand33b, a channel interleaving unit340, a central processing unit (CPU)350, a multimedia processor360and a modem processor370. The central processing unit (CPU)350, the multimedia processor360and the modem processor370can be connected to one another through a bus connection unit321. The channel interleaving unit340includes a high bandwidth channel interleaver341, a low bandwidth channel interleaver342and a router343.

In the embodiments of the type depicted inFIGS. 4 and 5, the semiconductor device200is configured to supplement an insufficient memory size of the WideIO memory device211by employing a single LPDDRx memory device212having two channels CHa and CHb in an interleaving operation in accordance with the inventive concepts. In the semiconductor device300of the type illustrated inFIG. 12, an insufficient memory size of the WideIO memory311can be supplemented by including multiple LPDDRx memory devices312and313, that are separate from each other, or independent of each other. Although two LPDDRx memory devices312and313are shown, more than two devices312,313can be employed for this purpose. The inventive concepts of the embodiment ofFIG. 12can perform channel interleaving operation among the WideIO memory device311and the multiple LPDDRx memory devices312,313to extend the high bandwidth region of the semiconductor device300.

FIG. 13is a flow diagram for explaining a channel interleaving operation of a semiconductor device in accordance with an embodiment of the inventive concept. The channel interleaving operation illustrated inFIG. 13may be performed, for example, by the memory controller130ofFIG. 1or may be performed by the channel interleaving units240and340of the embodiments ofFIGS. 4, 5 and 12. Hereinafter, a channel interleaving operation as performed by the channel interleaving unit240of the embodimentFIG. 4will be described. However, the same principles apply to the other embodiments of the present inventive concepts.

In a step S110, the channel interleaving unit240of the application processor220receives a request for a channel interleaving operation. In a step S120, the channel interleaving unit240determines the requisite size of the high bandwidth region according to address information of the request. In other words, the channel interleaving unit240determines whether the high bandwidth region is to be maintained in the WideIO memory device211or whether the high bandwidth region will extend to the LPDDRx memory device212. In a step S130, a channel ID that will perform a channel interleaving operation is calculated. The channel ID that will perform a channel interleaving operation can be calculated with reference to a memory access address ADDR. In a step S140, a channel interleaving operation is performed based on the calculated channel ID.

In the semiconductor device in accordance with embodiments of the inventive concepts, an application processor performs a channel interleaving operation between different kinds of at least two memory devices (e.g., WideIO memory device, LPDDRx memory device) having different bandwidths relative to each other. As a result, in the case that a memory size of a high bandwidth memory device, for example WideIO memory, is insufficient, a portion of a low bandwidth memory device, for example, LPDDRx memory, can be re-assigned, or otherwise allocated, to the high bandwidth region of the system.

FIGS. 14 through 16are cross sectional views illustrating a structure of a semiconductor device in accordance with an embodiment of the inventive concept.

FIG. 14illustrates a semiconductor package whereby an application processor (AP) and a WideIO memory chip are die-to-die interconnected. In the semiconductor package illustrated inFIG. 14, the application processor (AP) and the WideIO memory chip are directly connected to each other for example using a through silicon via (TSV) technology. In this example, a package on package (PoP) method is not employed wherein the application processor (AP) and the WideIO memory chip are independently packaged, and then the packages are repackaged again and connected to each other. Referring toFIG. 14, in this embodiment, the application processor (AP) is formed on a printed circuit board (PCB), and then the application processor (AP) and the WideIO memory chip are connected to each other through TSV.

FIG. 15illustrates a package on package (PoP) configuration wherein an LPDDRx memory chip package is stacked on the semiconductor package illustrated inFIG. 14. Referring toFIG. 15, in the package on package (PoP) configuration, a second package (package2) is stacked on a first package (package1). The first package (package1) is the semiconductor package illustrated inFIG. 14and the second package (package2) is a semiconductor package including the LPDDRx memory chip applied to a printed circuit board (PCB). The resulting second package (package2) is connected to the printed circuit board (PCB) of the first package (package1) through a wire.

FIG. 16illustrates an example embodiment wherein the first and second packages illustrated inFIG. 15are each mounted on a printed circuit board respectively. Referring toFIG. 16, the first package connects the application processor (AP) and the WideIO memory chip to each other through a TSV arrangement and the second package connects the LPDDRx memory chip to a printed circuit board through a wire. The first package and the second package are electrically connected to each other using customary signal lines.

The semiconductor device in accordance with embodiments of the inventive concepts can be applied to various products. The semiconductor device in accordance with embodiments of the inventive concepts can be used in electronic devices such as a digital cameras, a camcorders, a mobile phones, smart phones, tablet PCs, electronic book technology, etc.

FIGS. 17 and 18are block diagrams illustrating a mobile device including a channel interleaving unit (CIU) in accordance with an embodiment of the inventive concept. Mobile devices1000and2000illustrated inFIGS. 17 and 18can be embodied, for example, in a wireless internet device such as a cellular phone, a smart phone, a tablet PC, etc.

Referring toFIG. 17, the mobile device1000includes a system on chip (SoC)1001. In some embodiments, the system on chip (SoC)1001can be manufactured in the form of the package on package (PoP) described inFIG. 15. The system on chip (SoC)1001includes an application processor1100including a channel interleaving unit1110, a WideIO memory device1200and an LPDDRx memory device1300. The channel interleaving unit1110in the application processor1100can perform a channel interleaving operation among channels of the WideIO memory device1200and the LPDDRx memory device1300.

A radio transceiver1400can transmit or receive radio signals through an antenna. The radio transceiver1400can convert radio signals received through an antenna into signals which the system on chip1001can process. The system on chip1001performs a data processing on signals output by the radio transceiver1400, and the system on chip1001can store the processed data in the WideIO memory1200and/or the LPDDRx memory1300, or display the processed data at a display1600.

The radio transceiver1400can convert signals output from the system on chip1001into radio signals to output the converted radio signals to an external location through an antenna.

An input device1500can input control signals for controlling an operation of the system on chip1001or data to be processed by the system on chip1001. The input device1500can be embodied by a pointing device such as a touch pad and a computer mouse, a keypad or a keyboard, or other suitable input devices such as voice recognition or movement recognition.

The system on chip1001can control an operation of the display1600so that data output from the WideIO memory device1200or the LPDDRx memory device1300, radio signals output from the radio transceiver1400, or data output from the input device1500is displayed through the display1600.

Referring toFIG. 18, the mobile device2000of this embodiment includes a system on chip2001, an LPDDRx memory2300, a radio transceiver2400, an input device2500and a display2600. The system on chip2001can be manufactured in the form of the semiconductor package described inFIG. 14. The system on chip2001includes an application processor2100including a channel interleaving unit2110and a WideIO memory2200. The channel interleaving unit2110in the application processor2100can perform a channel interleaving operation among channels of the WideIO memory device2200and the LPDDRx memory device2300.

FIGS. 19 and 20are block diagrams illustrating another application example of an electronic device including a channel interleaving unit (CIU) in accordance with embodiments of the inventive concepts. Referring toFIGS. 19 and 20, electronic devices3000and4000include system on chips3001and4001including channel interleaving units3110and4110respectively. The channel interleaving units3110and4110in the system on chips3001and4001can perform a channel interleaving operation between channels of the WideIO memory devices3200and4200and channels of the LPDDRx memory devices3300and4300respectively.

Image sensors3400and4400of the electronic devices3000and4000illustrated inFIGS. 19 and 20can convert optical images into digital signals. The system on chip3001and4001process the converted digital signals to generate data on the basis of a virtual address, convert the virtual address into a physical address and store data in a physical address of the WideIO memory devices3200and4200or the LPDDRx memory devices3300and4300. The data can be displayed through displays3500and4500under the control of the system on chips3001and4001.

The semiconductor device in accordance with the inventive concept can be mounted using various types of packages such as PoP (package on package), ball grid array (BGA), chip scale package (CSP), plastic leaded chip carrier (PLCC), plastic dual in-line package (PDIP), die in waffle pack, die in wafer form, chip on board (COB), ceramic dual in-line package (CERDIP), plastic metric quad flat pack (MQFP), thin quad flat pack (TQFP), small outline (SOIC), shrink small outline package (SSOP), thin small outline (TSOP), thin quad flatpack (TQFP), system in package (SIP), multi chip package (MCP), wafer-level fabricated package (WFP) and wafer-level processed stack package (WSP).

In accordance with embodiments of the present inventive concepts, in a case where a storage space of a high bandwidth memory, for example WideIO memory, is insufficient, a portion of a low bandwidth memory, for example LPDDRx memory, can be reassigned to be used as a high bandwidth region by performing a channel interleaving operation among channels of the high bandwidth and low bandwidth memory devices (e.g., WideIO memory device, LPDDRx memory device).