Methods of manufacturing transistors using dummy gate patterns

Example methods of manufacturing a transistor using a dummy gate pattern are disclosed. A local channel is formed by local channel implantation using the dummy gate pattern after a source and a drain are formed so that a short channel effect can be minimized and a reverse SCE can be reduced.

TECHNICAL FIELD

The present invention relates to transistors and, more particularly, methods of manufacturing transistors using dummy gate patterns.

BACKGROUND

Generally, as a level of integration of a semiconductor device increases, there are serious disturbing factors that occur during semiconductor device manufacturing. One of the disturbing factors is a divot of a shallow trench isolation (STI), which affects characteristics of a transistor having a narrow width. Another disturbing factor is a capability of a lithography at side wall of CoO.

DETAILED DESCRIPTION

FIGS. 1Ato1G are schematic diagrams illustrating the results of an example transistor manufacturing process.

Referring toFIG. 1A, a first oxide layer2, a first nitride layer3, a second oxide layer4, and a second nitride layer5are sequentially formed on a silicon substrate1. Next, a first photoresist layer6is selectively formed on the second nitride layer5. The first and the second oxide layer2and4, the first and the second nitride layer3and5and the silicon substrate1are etched away through an etching process, e.g., a dry etching, to thereby form a trench region7having a predetermined depth.

As shown inFIG. 1B, the first photoresist layer6is stripped away and then an insulation layer8, e.g., a third oxide layer, is deposited on the second nitride5and the trench region7. Next, the insulation layer8is planarized through a chemical mechanical polishing (CMP) process. At this time, the second nitride layer5acts as a stopper of the CMP process. A second photoresist layer is deposited on the planarized insulation layer8and then patterned. Next, portions of the first and the second oxide layer2and4and the first and the second nitride layer3and5are etched away based on the patterned second photoresist layer through a dry etching to thereby form a dummy gate pattern10at a gate region. Thereafter, a lightly doped drain (LDD)9is formed underneath both sides of the dummy gate pattern10in the substrate1and then the second nitride layer5is removed.

Referring toFIG. 1C, a third nitride layer11, i.e., a spacer is formed on each sidewall of the dummy gate pattern10. Thereafter, a source12aand a drain12bare formed at a source and a drain region of the substrate1, respectively, and then a fourth nitride layer13having a thickness of hundreds of angstrom is deposited on the first insulation layer8, the source and the drain12aand12b, the second oxide layer4and the spacer11. A second insulation layer14is formed on the fourth nitride layer13and then planarized through the CMP process. At this time, the fourth nitride layer13acts as the stopper of the CMP process so that a portion of the fourth nitride layer13deposited on the second oxide layer4may be exposed.

As shown inFIG. 1D, the exposed portion of the fourth nitride layer13is removed. The second oxide layer4is removed through an etching process so that the first nitride layer3may be exposed. In one example, an etching selectivity of the second oxide layer4to the second insulation layer14in this case is about equal to or greater than 20.

Next, the exposed first nitride layer3is etched back as shown in FIG.1E.

Referring toFIG. 1F, a local channel implantation15is performed into the substrate to thereby form a local channel region16at the gate region of the substrate1. By doing this, a lateral diffusion of the source/drain can be reduced and, therefore, a junction depth thereof can be reduced. Also, an edge junction of the gate can be shallower to thereby reduce a junction leakage of n+/p and p+/n and enhance a short channel effect (SCE).

Referring toFIG. 1G, the first oxide layer2in the gate region is removed and then a third insulation layer17is grown thereto. Next, a conducting material is filled up to the surface of the second insulation layer14so that a gate electrode18is formed in the gate; region. A fourth insulation layer19is deposited on the gate electrode18and the second insulation layer14and then planarized. Finally, a gate plug20a, a source plug20band a drain plug20care formed at the gate region, the source region and the drain region, respectively.

As described above, the local channel is formed by local channel implantation using the dummy gate pattern after the source and the drain are formed so that the SCE can be minimized and a reverse SCE can be reduced. In an alternative example, the first nitride layer3can be omitted.

Although certain example methods are disclosed herein, the scope of coverage of this patent is not limited thereto. On the contrary, this patent covers every apparatus, method and article of manufacture fairly falling within the scope of the appended claims either literally or under the doctrine of equivalents.