Solid-state image sensor and image reading device

A solid-state image sensor including: a first impurity region of a first conductivity type; a plurality of second impurity regions of a second conductivity type disposed in the first impurity region and arranged in a first direction; and a light shielding layer that overlaps the first impurity region and does not overlap the second impurity regions in a plan view, wherein the first impurity region has a first portion between adjacent ones of the second impurity regions, the light shielding layer has a second portion that overlaps the first portion in a plan view, and a length of the second portion in the first direction is smaller than a length of the first portion in the first direction.

The present application is based on, and claims priority from Japanese Patent Application Serial Number 2019-082688, filed on Apr. 24, 2019, and Japanese Patent Application Serial No. 2020-000689, filed on Jan. 7, 2020, the disclosures of which are hereby incorporated by reference herein in their entirety.

BACKGROUND

1. Technical Field

The present invention relates to a solid-state image sensor and an image reading device.

2. Related Art

Scanners that use a solid-state image sensor such as a CIS (Contact Image Sensor), as well as copy machines, multifunction printers, and the like that have a print function in addition to a scanner are being developed. A line sensor used in scanners is configured by arranging a plurality of solid-state image sensors, in which a plurality of pixels are arranged in one direction. For example, JP-A-2016-100509 discloses that an n-type diffusion layer constitutes a photodiode, and the photodiode constitutes a pixel.

JP-A-2016-100509 is an example of the related art.

Adjacent n-type diffusion layers are electrically separated by a p-type diffusion layer. A solid-state image sensor is designed such that an n-type diffusion layer is completely depleted and serves as a depletion layer, and the depletion layer also extends from a boundary between the n-type diffusion layer and the p-type diffusion layer toward the p-type diffusion layer. Carriers that have undergone photoelectric conversion can be accumulated in the depletion layer, and thus, if light incident on the depletion layer is blocked by a light shielding layer, the solid-state image sensor may become less sensitive.

SUMMARY

In an aspect, a solid-state image sensor according to the present disclosure includes:a first impurity region of a first conductivity type;a plurality of second impurity regions of a second conductivity type disposed in the first impurity region and arranged in a first direction; anda light shielding layer that overlaps the first impurity region and does not overlap the second impurity regions in a plan view,wherein the first impurity region has a first portion between adjacent ones of the second impurity regions,the light shielding layer has a second portion that overlaps the first portion in a plan view, anda length of the second portion in the first direction is smaller than a length of the first portion in the first direction.

In an aspect of the solid-state image sensor,the light shielding layer may be an interconnect layer electrically coupled to the first impurity region.

In an aspect of the solid-state image sensor,a ground potential may be applied to the light shielding layer.

In an aspect of the solid-state image sensor,in a plan view, a first distance between one of adjacent ones of the second impurity regions and the second portion may be equal to a second distance between another one of the adjacent ones of the second impurity regions and the second portion.

In an aspect of the solid-state image sensor,an impurity concentration in the second impurity regions may be 1×1015atom/cm3or more and 1×1017atom/cm3or less, andthe first distance and the second distance may be 0.4 μm.

In an aspect of the solid-state image sensor,the solid-state image sensor may further include depletion layers constituted by the second impurity regions and portions of the first impurity region,wherein the length of the second portion in the first direction may be smaller than or equal to a distance between adjacent ones of the depletion layers in the first direction.

In an aspect of the solid-state image sensor,the light shielding layer may have a third portion,in a plan view, the third portion may be located in a second direction with respect to the second impurity regions, the second direction being orthogonal to the first direction, andin a plan view, the third portion may be spaced apart from the second impurity regions.

In an aspect of the solid-state image sensor,the solid-state image sensor may further include another light shielding layer that overlaps the light shielding layer in a plan view,wherein the other light shielding layer may have a fourth portion that overlaps the first portion in a plan view, anda length of the fourth portion in the first direction may be smaller than the length of the first portion in the first direction.

In an aspect, an image reading device according to the present disclosure includes:a light source; andthe solid-state image sensor in an aspect that reads an image formed on a medium to be read, based on light that is light applied by the light source reflected off the medium to be read.

DESCRIPTION OF EXEMPLARY EMBODIMENTS

Hereinafter, preferable embodiments of the present disclosure will be described in detail with reference to the drawings. Note that the following embodiments are not intended to unjustly limit the content of the present disclosure described in the claims. Not all of the configurations described below are necessarily essential constituent elements for the present disclosure.

1. First Embodiment

First, a solid-state image sensor according to the first embodiment will be described with reference to the drawings.FIG.1is a plan view schematically showing a solid-state image sensor100according to the first embodiment.FIG.2is a cross-sectional view taken along a line II-II inFIG.1that schematically shows the solid-state image sensor100according to the first embodiment. Note thatFIGS.1and2show an X axis, a Y axis, and a Z axis as three axes that are orthogonal to each other.

As shown inFIGS.1and2, the solid-state image sensor100includes a semiconductor substrate10, a first impurity region20, second impurity regions30, pinning layers40, a first insulating layer50, a second insulating layer52, a third insulating layer54, a first light shielding layer60, and a second light shielding layer70. Note that, in the following description, the first insulating layer50, the second insulating layer52, and the third insulating layer54may also be referred to as insulating layers50,52, and54, and the first light shielding layer60and the second light shielding layer70may also be referred to as light shielding layers60and70. InFIG.1, the pinning layers40, the insulating layers50,52, and54, and the second light shielding layer70are omitted for convenience.

The semiconductor substrate10is a semiconductor substrate of a second conductivity type. The second conductivity type refers to n-type. The semiconductor substrate10is an n-type silicon substrate obtained by adding an impurity such as phosphorus to silicon. The impurity concentration in the semiconductor substrate10is about 5×1014atom/cm3, for example. The impurity concentration can be measured using a SIMS (Secondary Ion Mass Spectroscopy).

The first impurity region20is disposed on the semiconductor substrate10. The first impurity region20is an impurity region of a first conductivity type, which differs from the second conductivity type. The first conductivity type refers to p-type. The first impurity region20is a p-type impurity region obtained by adding an impurity such as boron to silicon. The impurity concentration in the first impurity region20is 1×1015atom/cm3or more and 1×1016atom/cm3or less, for example. A ground potential is applied to the first impurity region20. The ground potential is 0 V, for example.

The second impurity regions30are disposed in the first impurity region20. The depth of the second impurity regions30is smaller than the depth of the first impurity region20. The second impurity regions30are n-type impurity regions obtained by adding an impurity such as phosphorus to silicon. The impurity concentration in the second impurity regions30is higher than the impurity concentration in the semiconductor substrate10. The impurity concentration in the second impurity regions30is 1×1015atom/cm3or more and 1×1017atom/cm3or less, for example.

A plurality of second impurity regions30are disposed. The plurality of second impurity regions30are arranged at a predetermined pitch in a first direction. In the shown example, the first direction is an X-axis direction. The first impurity region20electrically separates the plurality of second impurity regions30from each other. Furthermore, the first impurity region20electrically separates the semiconductor substrate10and the second impurity regions30from each other.

The second impurity regions30and portions21of the first impurity region20that overlap the second impurity regions30in a plan view constitute pixels2. Each of the pixels2is constituted by a photodiode. The pixels2, upon being irradiated with light, generate carriers and accumulate these carriers. Note that “in a plan view” refers to viewing from a thickness direction of the semiconductor substrate10, and refers to viewing from the Z-axis direction in the shown example.

Amplifier circuits (not shown) are electrically coupled to the second impurity regions30. A plurality of amplifier circuits are provided corresponding to the plurality of second impurity regions30. The amplifier circuits read out voltages that correspond to the amounts of carriers accumulated in the pixels2, amplify the read voltages, and output the amplified read voltages as output signals. A scanner that includes the solid-state image sensor100generates an image based on the output signals output for the respective pixels2by the amplifier circuits.

The pinning layers40are disposed on the surfaces of the second impurity regions30. The pinning layers40are p-type impurity regions obtained by adding an impurity such as boron to silicon. The impurity concentration in the pinning layers40is 1×1017atom/cm3or more and 1×1019atom/cm3or less, for example. The pinning layers40are capable of reducing a dark current caused by carriers generated due to thermal excitation that does not depend on light, in the second impurity regions30. In the shown example, the shape of the pinning layers40is the same as the shape of the second impurity regions30in a plan view.

The first insulating layer50is disposed on the first impurity region20and the pinning layers40. The first insulating layer50is an inter-layer insulating layer. The first insulating layer50is a silicon oxide layer.

The first light shielding layer60is disposed on the first insulating layer50. The first light shielding layer60overlaps the first impurity region20but does not overlap the second impurity regions30in a plan view. The first light shielding layer60shields the first impurity region20from light. The first light shielding layer60is an interconnect layer that is electrically coupled to the first impurity region20. A ground potential is applied to the first light shielding layer60. The first light shielding layer60is an aluminum layer or a copper layer.

The first light shielding layer60has second portions62that overlap first portions22of the first impurity region20in a plan view. The first impurity region20has the first portions22located between adjacent second impurity regions30. The length W2of one second portion62in the X-axis direction is smaller than the length W1of one first portion22in the X-axis direction. The length W1is the length of one first portion22in the X-axis direction, and is the smallest length between two adjacent second impurity regions30. The length W2is the largest length of one second portion62in the X-axis direction. In the example shown inFIG.1, the shape of the first portions22and the shape of the second portions62are rectangular in a plan view. In a plan view, the center of each first portion22overlaps the center of the corresponding second portion62.

A distance D1is equal to a distance D2. The first distance D1is the smallest distance between one of two adjacent second impurity regions30and a corresponding second portion62in a plan view. The second distance D2is the smallest distance between the other one of two adjacent second impurity regions30and the corresponding second portion62in a plan view. The first distance D1and the second distance D2are 0.4 μm, for example.

The length W2of one second portion62of the first light shielding layer60is smaller than or equal to a distance D3between two adjacent depletion layers4in the X-axis direction. The distance D3is the smallest distance between two adjacent depletion layers4in the X-axis direction. The length W2may be equal to the distance D3, or may be smaller than the distance D3. The solid-state image sensor100includes the depletion layers4, which are constituted by the second impurity regions30and portions of the first impurity region20. The depletion layers4are formed as a result of the second impurity regions30and portions of the first impurity region20being depleted. As is also shown inFIG.2, the depletion layers4also extend from boundaries A between the first impurity region20and the second impurity regions30toward the first impurity region20. When the impurity concentration in the second impurity regions30is 1×1015atom/cm3or more and 1×1017atom/cm3or less, the depletion layers4extend from the boundaries A toward the first impurity region20by approximately 0.4 μm.

The first light shielding layer60has third portions64. The third portions64are located in a second direction with respect to the second impurity regions30in a plan view. The second direction is a direction orthogonal to the first direction, and is the Y-axis direction in the shown example. In the shown example, the third portions64are located in the +Y-axis direction and the −Y-axis direction with respect to the second impurity regions30. In a plan view, the third portions64are spaced apart from the second impurity regions30. In a plan view, the first impurity region20is located between the third portions64and the second impurity regions30.

The second insulating layer52is disposed on the first insulating layer50and the first light shielding layer60. The second insulating layer52is an inter-layer insulating layer. The second insulating layer52is a silicon oxide layer.

The second light shielding layer70is disposed on the second insulating layer52. The second light shielding layer70overlaps the first impurity region20, and does not overlap the second impurity regions30, in a plan view. The second light shielding layer70shields the first impurity region20from light. The second light shielding layer70is another light shielding layer that overlaps the first light shielding layer60in a plan view. In the shown example, the shape of the second light shielding layer70is the same as the shape of the first light shielding layer60in a plan view. The second light shielding layer70is an interconnect layer that is electrically coupled to the first impurity region20. A ground potential is applied to the second light shielding layer70. The second light shielding layer70is an aluminum layer or a copper layer, for example.

The second light shielding layer70has fourth portions72that overlap the first portions22of the first impurity region20in a plan view. The length W4of one fourth portion72in the X-axis direction is smaller than the length W1of one first portion22in the X-axis direction. The length W4is the largest length of one fourth portion72in the X-axis direction. In the shown example, the length W4of one fourth portion72is the same as the length W2of one second portion62.

The third insulating layer54is disposed on the second insulating layer52and the second light shielding layer70. The third insulating layer54is a passivation layer. The third insulating layer54is a silicon oxide layer or a silicon nitride layer, for example.

1.2. Method for Manufacturing Solid-State Image Sensor

Next, a method for manufacturing the solid-state image sensor100according to the first embodiment will be described with reference to the drawings.FIG.3is a cross-sectional view schematically showing a process of manufacturing the solid-state image sensor100according to the first embodiment.

As shown inFIG.3, the first impurity region20is formed in the semiconductor substrate10. The first impurity region20is formed by injecting boron into the semiconductor substrate10using an ion injection method, for example.

As shown inFIG.2, the second impurity regions30are formed in the first impurity region20. The second impurity regions30are formed by injecting phosphorus into the first impurity region20using an ion injection method, for example.

Next, the pinning layers40are formed in the second impurity regions30. The pinning layers40are formed by injecting boron into the second impurity regions30using an ion injection method, for example.

Next, the first insulating layer50is formed on the first impurity region20and the pinning layers40. The first insulating layer50is formed using a CVD (Chemical Vapor Deposition) method, for example. Next, for example, the upper surface of the first insulating layer50is polished and flattened by means of CMP (Chemical Mechanical Polishing), for example.

Next, the first light shielding layer60is formed on the first insulating layer50. The first light shielding layer60is formed by means of film deposition using a sputtering method, and patterning by means of photolithography and etching, for example.

Next, the second insulating layer52is formed on the first insulating layer50and the first light shielding layer60. The second insulating layer52is formed using a CVD method, for example. Next, for example, the upper surface of the second insulating layer52is polished and flattened by means of CMP.

Next, the second light shielding layer70is formed on the second insulating layer52. The second light shielding layer70is formed by means of film deposition using a sputtering method, and patterning by means of photolithography and etching, for example.

Next, the third insulating layer54is formed on the second insulating layer52and the second light shielding layer70. The third insulating layer54is formed using a CVD method, for example. Lastly, for example, the upper surface of the third insulating layer54may be polished and flattened by means of CMP.

The solid-state image sensor100can be manufactured through the above process.

The solid-state image sensor100has the following effects, for example.

In the solid-state image sensor100, the length W2of one second portion62of the first light shielding layer60in the X-axis direction is smaller than the length W1of one first portion22of the first impurity region20in the X-axis direction. Thus, in the solid-state image sensor100, portions4aof the depletion layers4that are constituted by the first impurity region20are also irradiated with light. Accordingly, the amount of carriers accumulated in the depletion layers4can be increased compared with the case where the length W2is the same as the length W1as shown inFIGS.4and5. This configuration enables the solid-state image sensor100to be highly sensitive. Accordingly, when the solid-state image sensor100is used in a scanner, the exposure time of the scanner can be shortened, and an increase in speed is achieved.

Note thatFIG.4is a plan view schematically showing a solid-state image sensor in which the length W2is equal to the length W1.FIG.5is a cross-sectional view taken along a line V-V inFIG.4that schematically shows the solid-state image sensor in which the length W2is equal to the length W1. InFIG.4, the pinning layers40, the insulating layers50,52, and54, and the second light shielding layer70are omitted for convenience.

Furthermore, the first light shielding layer60has the second portions62that overlap the first portions22in a plan view. Thus, adjacent second impurity regions30can be electrically separated from each other more reliably than in the case where the second portions are not provided. Accordingly, when the solid-state image sensor100is used in a scanner, the likelihood that crosstalk occurs, i.e. a color looks blurred in a scanned image can be reduced.

In the solid-state image sensor100, the first light shielding layer60is an interconnect layer that is electrically coupled to the first impurity region20. Thus, the structure of the solid-state image sensor100can be simplified compared with the case where a light shielding layer is provided separately from an interconnect layer.

In the solid-state image sensor100, a ground potential is applied to the first light shielding layer60. Accordingly, in the solid-state image sensor100, parasitic capacitance can be reduced compared with the case where a potential higher than the ground potential is applied to the first light shielding layer60.

In the solid-state image sensor100, in a plan view, the first distance D1between one of two adjacent second impurity regions30and a corresponding second portion62is equal to the second distance D2from the other one of the two adjacent second impurity regions30and the corresponding second portion62. Thus, in the solid-state image sensor100, the difference in the amount of accumulated carriers between a depletion layer4that has the one of the second impurity regions30and a depletion layer4that has the other one of the second impurity regions30can be reduced compared with the case where the first distance D1differs from the second distance D2. Accordingly, the difference in sensitivity between a pixel2that has the one of the second impurity regions30and a pixel2that has the other one of the second impurity regions30can be reduced.

In the solid-state image sensor100, the impurity concentration in the second impurity regions30is 1×1015atom/cm3or more and 1×1017atom/cm3or less, and the first distance D1and the second distance D2are 0.4 μm. When the impurity concentration in the second impurity regions30is 1×1015atom/cm3or more and 1×1017atom/cm3or less, the depletion layers4extend from the boundaries A toward the first impurity region20by approximately 0.4 μm. Thus, in the solid-state image sensor100, the portions4aof the depletion layers4are more reliably irradiated with light.

In the solid-state image sensor100, the length W2of one second portion62in the X-axis direction is smaller than or equal to the distance D3between two adjacent depletion layers4in the X-axis direction. Thus, in the solid-state image sensor100, the portions4aof the depletion layers4are more reliably irradiated with light.

In the solid-state image sensor100, the third portions64of the first light shielding layer60are located in the Y-axis direction with respect to the second impurity regions30in a plan view, and the third portions64are spaced apart from the second impurity regions30in a plan view. Thus, in the solid-state image sensor100, the depletion layers4, which are located in the Y-axis direction with respect to the second impurity regions30in a plan view, are irradiated with light.

In the solid-state image sensor100, the second light shielding layer70has fourth portions72that overlap the first portions22of the first impurity region20in a plan view, and the length W4of one fourth portion72in the X-axis direction is smaller than the length W1of one first portion22in the X-axis direction. Thus, in the solid-state image sensor100, the amount of carriers accumulated in the depletion layers4can be increased as in the first light shielding layer60, compared with the case where the length W4is the same as the length W1.

In the solid-state image sensor100, the first light shielding layer60has the second portions62as mentioned above. For this reason, when the second insulating layer52is polished by means of CMP, dishing is unlikely to occur, i.e. the second insulating layer52is unlikely to be excessively polished.

If the first light shielding layer60does not have the second portions62as shown inFIGS.6and7, dishing may occur, i.e. the second insulating layer52may be excessively polished at portions where the density of the first light shielding layer60is small, when the second light shielding layer52is polished by means of CMP. Consequently, when patterning is performed to form the second light shielding layer70, there may be cases where focusing fails during lithography and a defect occurs in the second light shielding layer70.

Note thatFIG.6is a plan view schematically showing a solid-state image sensor in which dishing may occur.FIG.7is a cross-sectional view taken along a line VII-VII inFIG.6that schematically shows the solid-state image sensor in which dishing may occur. InFIG.6, the pinning layers40, the insulating layers50,52, and54, and the second light blocking layer70are omitted for convenience.

Note that, in the above-described example, three insulating layers and two light shielding layers are included, but the number of insulating layers and the number of light shielding layers are not specifically limited. Although not shown in the diagrams, the solid-state image sensor100may alternatively include four insulating layers and three light shielding layers.

In the above-described example, the first conductivity type is p-type and the second conductivity type is n-type, but the first conductivity type may be n-type, and the second conductivity type may be p-type. That is to say, the semiconductor substrate10and the second impurity regions30may be of a p-type, and the first impurity region20and the pinning layers40may be of an n-type.

The solid-state image sensor100may be a CCD (Charge Coupled Device), or may be a CMOS (Complementary Metal Oxide Semiconductor) image sensor.

1.4.1. First Modification

Next, a solid-state image sensor110according to a first modification of the first embodiment will be described with reference to the drawings.FIG.8is a plan view schematically showing the solid-state image sensor110according to the first modification of the first embodiment. Note that, inFIG.8, the pinning layers40, the insulating layers50,52, and54, and the second light shielding layer70are omitted for convenience.

In the following description of the solid-state image sensor110according to the first modification of the first embodiment, members with the same functions as those of the constituent members of the solid-state image sensor100according to the above-described first embodiment are assigned the same reference numerals, and detailed description thereof is omitted. This also applies to a later-described solid-state image sensor according to a second modification of the first embodiment.

In the above-described solid-state image sensor100, in a plan view, the third portions64of the first light shielding layer60are spaced apart from the second impurity regions30, and the first impurity region20is located between the third portions64and the second impurity regions30, as shown inFIG.1.

In contrast, in the solid-state image sensor110, the first impurity region20is not located between the third portions64of the first light shielding layer60and the second impurity regions30, as shown inFIG.8. In the solid-state image sensor110, the third portions64overlap the depletion layers4that are located in the Y-axis direction with respect to the second impurity regions30in a plan view.

In the solid-state image sensor110, the length W2of one second portion62of the first light shielding layer60in the X-axis direction is smaller than the length W1of one first portion22of the first impurity region20in the X-axis. Accordingly, the amount of carriers accumulated in the depletion layers4can be increased, as with the solid-state image sensor100, compared with the case where the length W2is the same as the length W1. As shown inFIG.8, the length of one second impurity region30in the Y-axis direction is greater than the length in the X-axis direction. Thus, if the length W2is smaller than the length W1, the solid-state image sensor110can be configured to be highly sensitive even if the third portions64overlap the depletion layers4.

1.4.2. Second Modification

Next, a solid-state image sensor120according to the second modification of the first embodiment will be described with reference to the drawings.FIG.9is a plan view schematically showing the solid-state image sensor120according to the second modification of the first embodiment.FIG.10is a cross-sectional view taken along a line X-X inFIG.9that schematically shows the solid-state image sensor120according to the second modification of the first embodiment. Note that, inFIG.9, the pinning layers40and the insulating layers50,52, and54are omitted for convenience.

In the above-described solid-state image sensor100, the length W2of one second portion62of the first light shielding layer60in the X-axis direction is equal to the length W4of one fourth portion72of the second light shielding layer70in the X-axis direction, as shown inFIG.2.

In contrast, in the solid-state image sensor120, the length W4of one fourth portion72of the second light shielding layer70is smaller than the length W2of one second portion62of the first light shielding layer60, as shown inFIGS.9and10. Thus, in the solid-state image sensor120, light incident on the solid-state image sensor120obliquely relative to the Z axis is unlikely to be blocked by the fourth portions72, compared with the case where the length W2is the same as the length W4. This configuration can increase the amount of light incident on the pixels2, and can increase sensitivity.

2. Second Embodiment

Next, a solid-state image sensor200according to the second embodiment will be described with reference to the drawings.FIG.11is a plan view schematically showing the solid-state image sensor200according to the second embodiment.FIG.12is a cross-sectional view taken along a line XII-XII inFIG.11that schematically shows the solid-state image sensor200according to the second embodiment. Note that, inFIG.11, the pinning layers40, the insulating layers50,52, and54, and the second light shielding layer70are omitted for convenience.

In the following description of the solid-state image sensor200according to the second embodiment, members with the same functions as those of the constituent members of the solid-state image sensor100according to the above-described first embodiment are assigned the same reference numerals, and detailed description thereof is omitted.

The solid-state image sensor200differs from the above-described solid-state image sensor100in that the solid-state image sensor200includes third impurity regions80, as shown inFIGS.11and12. Furthermore, the solid-state image sensor200includes a fourth impurity region90and a LOCOS (Local Oxidation of Silicon) layer92.

The third impurity regions80are disposed in the first impurity region20. The depth of the third impurity regions80is smaller than the depth of the first impurity region20. In the shown example, the depth of the third impurity regions80is the same as the depth of the second impurity regions30. The plurality of second impurity regions30and the third impurity regions80are arranged in the X-axis direction. Of the plurality of second impurity regions30and the third impurity regions80that are arranged in the X-axis direction, the third impurity regions80are located at the ends. In the shown example, the third impurity regions80are disposed at one end and the other end, in the X-axis direction, of a line in which the second impurity regions30and the third impurity regions80are arranged.

The third impurity regions80do not constitute the pixels2. Thus, the amplifier circuits (not shown) are not electrically coupled to the third impurity regions80. Note that the first impurity region20need not be provided in the Y-axis direction of the third impurity regions80in a plan view.

The third impurity regions80are spaced apart from the second impurity regions30. The first impurity region20has portions24between the third impurity regions80and the second impurity regions30adjacent to the third impurity regions80. The length of one third impurity region80in the X-axis direction is smaller than the length of one second impurity region30in the X-axis direction.

The first light shielding layer60has portions66that overlap the portions24of the first impurity region20in a plan view. The length W5of one portion66in the X-axis direction is smaller than the length W6of one portion24in the X-axis direction. The length W5is equal to the length W2. The length W6is equal to the length W1.

The third impurity regions80are n-type impurity regions obtained by adding an impurity such as phosphorus to silicon. The impurity concentration in the third impurity regions80is greater than or equal to the impurity concentration in the second impurity regions30, and is smaller than the impurity concentration in the fourth impurity region90. The third impurity regions80are coupled to the fourth impurity region90. The pinning layers40are disposed on the surfaces of the third impurity regions80.

The fourth impurity region90is disposed on the semiconductor substrate10. The fourth impurity region90surrounds the first impurity region20in a plan view. The fourth impurity region90surrounds the second impurity regions30and the third impurity regions80in a plan view. In the shown example, the depth of the fourth impurity region90is smaller than the depth of the first impurity region20.

The fourth impurity region90is an n-type impurity region obtained by adding an impurity such as phosphorus to silicon. The fourth impurity region90is a high-concentration impurity region with an impurity concentration higher than the impurity concentration in the second impurity regions30. The impurity concentration in the fourth impurity region90is 1×1016atom/cm3or more and 1×1017atom/cm3or less, for example.

A power supply voltage VDD is applied to the fourth impurity region90. The power supply voltage VDD is 3.3 V, for example.

The LOCOS layer92is disposed on the fourth impurity region90. The LOCOS layer92is an element isolation insulating layer. Note that, although not shown in the diagrams, a semi-recessed LOCOS layer or an STI (shallow trench isolation) layer may be used in place of the LOCOS layer92.

2.2. Method for Manufacturing Solid-State Image Sensor

Next, a method for manufacturing the solid-state image sensor200according to the second embodiment will be described with reference to the drawings.

As shown inFIG.12, the LOCOS layer92is formed on the semiconductor substrate10. The LOCOS layer92is formed using a LOCOS method.

Next, the first impurity region20is formed on the semiconductor substrate10. The first impurity region20is formed by injecting boron into the semiconductor substrate10using an ion injection method, for example.

Next, the second impurity regions30and the third impurity regions80are formed on the first impurity region20. The second impurity regions30and the third impurity regions80are formed by injecting phosphorus into the first impurity region20using an ion injection method, for example. In the following description, the second impurity regions30and the third impurity regions80are also referred to as impurity regions30and80.

Next, the fourth impurity region90is formed on the semiconductor substrate10. The fourth impurity region90is formed by injecting phosphorus into the semiconductor substrate10using an ion injection method, for example.

Next, the pinning layers40are formed on the second impurity regions30and the third impurity regions80. The pinning layers40are formed by injecting boron into the impurity regions30and80using an ion injection method, for example.

The solid-state image sensor200can be manufactured through the above process.

Note that the order of the process of forming the impurity regions30and80and the process of forming the fourth impurity region90is not specifically limited. Also, the order of the process of forming the fourth impurity region90and the process of forming the pinning layers40is not specifically limited.

The solid-state image sensor200has the following effects, for example.

In the solid-state image sensor200, the difference in the amount of accumulated carriers between the pixels2located at the ends and the pixels2that are not located at the ends, of the plurality of pixels2arranged in the X-axis direction, can be reduced. The reason will be described below.

FIG.13is a diagram showing potential energy on a broken line B shown inFIG.12.FIG.14is a cross-sectional view schematically showing a solid-state image sensor that does not have the third impurity regions80.FIG.15is a diagram showing potential energy on a broken line B shown inFIG.14. Note that, inFIGS.13and15, carriers are indicated by black dots.

As shown inFIG.14, if the third impurity regions80are not disposed, the potential energy in the first impurity region20adjacent to the fourth impurity region90is affected by the 3.3 V applied to the fourth impurity region90and decreases, as shown inFIG.15. For this reason, it is highly probable that carriers generated in the first impurity region20between the pixels2located at the ends and the fourth impurity region90, namely carriers surrounded by the broken line, will fall down into the fourth impurity region90, rather than the pixels2located at the ends. Consequently, the amount of carriers accumulated in the pixels2located at the ends is smaller than the amount of carriers accumulated in pixels2that are not located at the ends. As a result, the pixels2located at the ends are less sensitive.

In contrast, in the solid-state image sensor200, the third impurity regions80can make the potential energy at the portions24between the second impurity regions30and the third impurity regions80the same as the potential energy at the first portions22between two adjacent second impurity regions30, as shown inFIG.13. Thus, the probability that carriers generated at the portions24, namely carriers surrounded by the broken line, will fall down into the pixels2can be approximated to the probability that carriers generated at the first portions22will fall down into the pixels2. Thus, the difference in the amount of accumulated carriers between the pixels2located at the ends and the pixels2that are not located at the ends can be reduced. As a result, the pixels2located at the ends are unlikely to become less sensitive, and the difference in sensitivity between the pixels2located at the ends and the pixels2that are not located at the ends can be reduced.

The phenomenon in which the sensitivity deteriorates is particularly an issue in CISs for high-resolution use in which the pitch between the pixels2is 10 μm or less, for example. This is because, the smaller the pitch between the pixels2is, the smaller the area of each pixel2is and the smaller the amount of accumulated carriers is, and thus, the amount of carriers that move from the pixels2located at the ends to the fourth impurity region90is not negligible with respect to the amount of carriers accumulated in the pixels2that are not located at the ends.

As mentioned above, in the solid-state image sensor200, the third impurity regions80function as electric-field relaxing regions that relax the voltage applied to the fourth impurity region90, and thus the sensitivity of the pixels2located at the ends is unlikely to deteriorate.

Furthermore, in the solid-state image sensor200, the length W5of one portion66of the first light shielding layer60in the X-axis direction is smaller than the length W6of one portion24of the first impurity region20in the X-axis direction. Thus, it is possible to reduce the likelihood that the depletion layers4that have the second impurity regions30that constitute the pixels2located at the ends are shielded from light by the portions66of the first light shielding layer60. Accordingly, the difference in sensitivity between the pixels2located at the ends and the pixels2that are not located at the ends can be reduced.

Next, a solid-state image sensor according to a modification of the second embodiment will be described with reference to the drawings.

In the following description, differences between the solid-state image sensor according to the modification of the second embodiment and the example of the solid-state image sensor200according to the above-described second embodiment will be described, and description of the same points will be omitted.

In the above-described solid-state image sensor200, the conductivity type of the semiconductor substrate10and the fourth impurity region90is the second conductivity type, namely an n-type.

In contrast, in the solid-state image sensor according to the modification of the second embodiment, the conductivity type of the semiconductor substrate10and the fourth impurity region90is the first conductivity type, namely a p-type.

In the solid-state image sensor according to the modification of the second embodiment, the impurity concentration in the first impurity region20is higher than the impurity concentration in the semiconductor substrate10. The fourth impurity region90is a high-concentration impurity region with an impurity concentration higher than the impurity concentration in the first impurity region20. A ground potential is applied to the first impurity region20and the fourth impurity region90.

In the solid-state image sensor according to the modification of the second embodiment, it is possible to reduce the difference in the amount of accumulated carriers between the pixels2located at the ends and the pixels2that are not located at the ends, of the plurality of pixels2arranged in the X-axis direction. The reason will be described below.

FIG.16is a diagram showing potential energy in the solid-state image sensor according to the modification of the second embodiment. Specifically,FIG.16is a diagram showing potential energy on the broken line B in the solid-state image sensor200shown inFIG.12when the conductivity type of the semiconductor substrate10and the fourth impurity region90is of the p-type.FIG.17is a diagram showing potential energy on the broken line B in the solid-state image sensor that does not have the third impurity regions80shown inFIG.14when the conductivity type of the semiconductor substrate10and the fourth impurity region90is of the p-type.

If the third impurity regions80are not provided, as shown inFIG.17, carriers generated in the fourth impurity region90, namely carriers surrounded by the broken line, are likely to gather in the pixels2located at the ends, and the amount of accumulated carriers differs between the pixels2located at the ends and the pixels2that are not located at the ends. As a result, the pixels2located at the ends are more sensitive, and a difference in sensitivity occurs between the pixels2located at the ends and the pixels2that are not located at the ends. In the shown example, the curve indicating the potential energy in the fourth impurity region90and the first impurity region20is flat for convenience. However, the impurity concentration in the fourth impurity region90is higher than the impurity concentration in the first impurity region20, and thus, in reality, the curve indicating potential energy inclines so as to move down from the fourth impurity region90toward the first impurity region20. Accordingly, carriers generated in the fourth impurity region90are likely to gather in the pixels2located at the ends.

In contrast, the solid-state image sensor according to the modification of the second embodiment has the third impurity regions80, and thus, carriers generated in the fourth impurity region90gather in the third impurity regions80, rather than the pixels2located at the ends, as shown inFIG.16. Thus, the difference in the amount of accumulated carriers between the pixels2located at the ends and the pixels2that are not located at the ends can be reduced. As a result, the pixels2located at the ends are unlikely to become less sensitive, and the difference in sensitivity between the pixels2located at the ends and the pixels2that are not located at the ends can be reduced.

Next, a multifunction machine400according to the third embodiment will be described with reference to the drawings.FIG.18is a perspective view schematically showing an appearance of the multifunction machine400according to the fourth embodiment.

As shown inFIG.18, the multifunction machine400includes a printer unit402, which is an image recording device, and a scanner unit403, which is an image reading device. Specifically, the multifunction machine400integrally includes the printer unit402, which is a machine body, and the scanner unit403, which is an upper unit provided at an upper portion of the printer unit402. Note that, in the following description, the front-rear direction inFIG.18is referred to as an X-axis direction, and the left-right direction is referred to as a Y-axis direction.

As shown inFIG.18, the printer unit402includes a conveyance portion (not shown) that feeds a sheet-type recording medium, namely print paper or cut paper, along a feeding path, a print portion (not shown) that is provided above the feeding path and performs print processing on the recording media using an inkjet method, a panel-form operation portion463provided in the front surface, a machine frame (not shown) on which the conveyance portion, the print portion, and the operation portion463are mounted, and a machine housing465that covers these members. The machine housing465is provided with a discharge port466from which a printed recording medium is discharged. Although not shown in the diagram, a USB (Universal Serial Bus) port and a power supply port are provided at a lower portion of the back surface. That is to say, the multifunction machine400can be connected to a computer or the like via the USB port.

The scanner unit403is pivotably supported by the printer unit402via a hinge portion404at a rear end portion, and covers an upper portion of the printer unit402in an openable and closable manner. That is to say, by pulling up the scanner unit403in a pivoting direction, an upper opening portion of the printer unit402is exposed, and the interior of the printer unit402is exposed via the upper opening portion. Conversely, the upper opening portion is closed with the scanner unit403by pulling down the scanner unit403in the pivoting direction and placing the scanner unit403on the printer unit402. Thus, for example, ink cartridges can be replaced and a paper jam can be resolved by opening the scanner unit403.

FIG.19is a perspective view schematically showing an internal structure of the scanner unit403. As shown inFIGS.18and19, the scanner unit403includes an upper frame411, which is a housing, an image reading portion412, which is accommodated in the upper frame411, an image sensor module420, and an upper lid413, which is pivotably supported by an upper portion of the upper frame411. As shown inFIG.19, the upper frame411includes a box-shaped lower case416, which accommodates the image reading portion412and the image sensor module420, and an upper case417, which covers a top surface of the lower case416. A document placement plate (not shown) that is made of glass, namely a document plate is widely installed over the upper case417, and a medium that is to be read, namely a document is placed thereon with a face to be read facing downward. Meanwhile, the lower case416is formed to have a shallow box shape that is open in its upper face.

FIG.20is an exploded perspective view schematically showing a configuration of an image sensor module420. In the example shown inFIG.20, the image sensor module420includes a case421, a light source422, a lens423, a module substrate424, and solid-state image sensors100for reading an image. The light source422, the lens423, and the solid-state image sensors100are accommodated between the case421and the module substrate424. The case421is provided with a slit. The light source422has R, G, and B light-emitting diodes (LEDs), and causes red LEDs, green LEDs, and blue LEDs to emit light in turn while rapidly switching therebetween. Light emitted by the light source422is applied to a medium to be read via the slit, and the light from the medium to be read is input to the lens423via the slit. The lens423guides the input light to the solid-state image sensor100.

The solid-state image sensors100read an image formed on the medium to be read, based on light that is light applied by the light source422reflected off the medium to be read. Specifically, in the solid-state image sensors100, carriers are accumulated in the pixels2in accordance with the incident light. The amplifier circuit that is electrically coupled to the pixels2reads out and amplifies voltages corresponding to the amounts of carriers accumulated in the pixels2, and outputs the amplified voltages as output signals. The scanner unit403generates an image based on the output signals that are output for the respective pixels2by the amplifier circuit.

FIG.21is a plan view schematically showing the solid-state image sensors100. As shown inFIG.21, a plurality of solid-state image sensors100are arranged on the module substrate424in the X-axis direction. The length of one solid-state image sensor100in the X-axis is 10 mm or more and 20 mm or less, for example.

Note that the solid-state image sensors100are applicable to both a color scanner and a monochrome scanner.

In the present disclosure, some of the configurations may be omitted within the scope where the characteristics and effects described in the present application are exhibited, and the embodiments and the modifications may be combined.

The present disclosure is not limited to the above-described embodiments, and more various modifications may be made. For example, the present disclosure includes substantially the same configurations as those described in the embodiments. “Substantially the same configurations” means configurations that have the same functionalities, methods, and results, or configurations that have the same objects and effects, for example. Also, the present disclosure includes a configuration in which portions thereof described in the embodiments that are not essential are replaced. Also, the present disclosure includes a configuration that exhibits the same effects as those described in the embodiments or a configuration that enables the same object to be achieved. Also, the present disclosure includes a configuration that is achieved by adding a known technique to the configurations described in the embodiments.