Bipolar junction device

The present disclosure provides embodiments of bipolar junction transistor (BJT) structures. A BJT according to the present disclosure includes a first epitaxial feature disposed over a well region, a second epitaxial feature disposed over the well region, a vertical stack of channel members each extending lengthwise between the first epitaxial feature and the second epitaxial feature, a gate structure wrapping around each of the vertical stack of channel members, a first electrode coupled to the well region, an emitter electrode disposed over and coupled to the first epitaxial feature, and a second electrode disposed over and coupled to the second epitaxial feature.

BACKGROUND

The electronics industry has experienced an ever-increasing demand for smaller and faster electronic devices which are simultaneously able to support a greater number of increasingly complex and sophisticated functions. Accordingly, there is a continuing trend in the semiconductor industry to manufacture low-cost, high-performance, and low-power integrated circuits (ICs). Thus far these goals have been achieved in large part by scaling down semiconductor IC dimensions (e.g., minimum feature size) and thereby improving production efficiency and lowering associated costs. However, such scaling has also introduced increased complexity to the semiconductor manufacturing process. Thus, the realization of continued advances in semiconductor ICs and devices calls for similar advances in semiconductor manufacturing processes and technology.

Multi-gate devices, such as fin field-effect transistors (FinFETs) and multi-bridge-channel (MBC) transistors (also known as gate-all-around (GAA) transistors, surrounding gate transistors (SGTs), nanowire transistors, or nanosheet transistors), have been introduced in an effort to improve gate control by increasing gate-channel coupling, reduce OFF-state current, and reduce short-channel effects (SCEs). The three-dimensional structure of the multi-gate devices allows them to be aggressively scaled while maintaining gate control and mitigating SCEs.

Current-controlled active devices, such as bipolar junction transistors (BJTs), may be integrated with voltage-controlled multi-gate devices to meet various design needs. Although conventional BJTs are generally adequate for their intended purposes, they are not satisfactory in all aspects.

DETAILED DESCRIPTION

The present disclosure generally relates to semiconductor devices. Particularly, the present disclosure relates to bipolar junction transistors fabricated along with multi-gate transistors.

Some example BJTs include three source/drain features formed over an active region and respectively coupled to an emitter electrode, a collector electrode, and a base electrode. The emitter electrode, collector electrode, and base electrode in these example BJTs are routed through front-side source/drain contacts. The present disclosure provides BJT structures that may be fabricated along with MBC transistors and include two source/drain features disposed over a doped well region. In various embodiments, the two source/drain features are coupled to front-side source/drain features and the doped well region is coupled to a backside power rail. The two front-side source/drain features and the backside power rail may serve as the emitter electrode, the collector electrode, and the base electrode of a BJT. As compared to BJTs that span across three source/drain features and have electrical routing on the front side, the BJTs spanning across two source/drain features and electrically routed on both sides have a smaller footprint and improved routing.

The various aspects of the present disclosure will now be described in more detail with reference to the figures. Among the figures,FIGS. 1 and 2illustrate a first device structure100-1;FIGS. 3 and 4illustrate a second device structure100-2;FIGS. 5 and 6illustrate a third device structure100-3;FIGS. 8 and 9illustrate a fourth device structure100-4;FIGS. 10 and 11illustrate a fifth device structure100-5; andFIGS. 12 and 13illustrate a sixth device structure100-6.FIG. 7illustrates an equivalent circuit diagram of the first device structure100-1, the second device structure100-2, and the third device structure100-3.FIG. 14illustrates an equivalent circuit diagram of the fourth device structure100-4, the fifth device structure100-5, and the sixth device structure100-6.FIG. 15illustrates a fragmentary top view of a semiconductor device400that includes a plurality of device structures connected in parallel. Throughout the present disclosure, like reference numerals denote like features. The X, Y, Z directions in the figures are perpendicular to one another and are used consistently.

FIG. 1illustrates a fragmentary cross-sectional view of a first device structure100-1viewed along the Y direction. In some embodiments represented inFIG. 1, the first device structure100-1has a structure similar to but not identical to a multi-bridge-channel (MBC) transistor that includes a plurality of bridge-like channel members (or channel structures). InFIG. 1, the first device structure100-1includes a plurality of channel members108extending along the X direction between a first p-type epitaxial feature116P-1and a second p-type epitaxial feature116P-2. Because the first p-type epitaxial feature116P-1and the second p-type epitaxial feature116P-2are fabricated along with MBC transistors, they may also be referred to as first and second p-type source/drain features116P-1and116P-2, respectively. The first device structure100-1includes a gate structure110that extends lengthwise along the Y direction. The gate structure110wraps around each of the plurality of channel members108. As shown inFIG. 1, the gate structure110includes a gate dielectric layer112and a gate electrode114. The gate structure110is isolated from the first and second p-type source/drain features116P-1and116P-2by a plurality of inner spacer features118. The plurality of inner spacer features118interleave the plurality of channel members108. A first source/drain contact120-1is disposed over and electrically coupled to the first p-type source/drain feature116P-1and a second source/drain contact120-2is disposed over and electrically coupled to the second p-type source/drain feature116P-2. In some implementations represented inFIG. 1, each of the first source/drain contact120-1and the second source/drain contact120-2includes a barrier layer122and a metal fill layer124.

In some embodiments, the channel members108may include a semiconductor material, such as silicon (Si), germanium (Ge), or silicon germanium (SiGe). In one embodiment, the channel members108are formed of silicon (Si). The gate dielectric layer112may include an interfacial layer and a high-k dielectric layer. In some embodiments, the interfacial layer may include a dielectric material such as silicon oxide layer. The high-k dielectric layer is formed of a high-k (dielectric constant greater than about 3.9) dielectric material that may include hafnium oxide, titanium oxide, hafnium zirconium oxide, tantalum oxide, hafnium silicon oxide, zirconium oxide, zirconium silicon oxide, combinations thereof, or other suitable materials. The gate electrode114may include one or more work function layers and a metal fill layer. The one or more work function layers may include n-type work function layers and p-type work function layers. Example n-type work function layers may be formed of aluminum, titanium aluminide, titanium aluminum carbide, tantalum silicon carbide, tantalum silicon aluminum, tantalum silicide, or hafnium carbide. Example p-type work function layers may be formed of titanium nitride, titanium silicon nitride, tantalum nitride, tungsten carbonitride, or molybdenum. The metal fill layer may be formed of a metal, such as tungsten (W), ruthenium (Ru), cobalt (Co) or copper (Cu). The first p-type epitaxial feature116P-1and the second p-type epitaxial feature116P-2may be a semiconductor material such as silicon germanium (SiGe) and is doped with a p-type dopant, such as boron (B).

The gate structure110, the first p-type epitaxial feature116P-1, the second p-type epitaxial feature116P-2, and the bottommost inner spacer features118are disposed on an n-type well region102N. In some implementations, the n-type well region102N is doped with an n-type dopant such as phosphorus (P) or arsenic (As) and has a first doping concentration (C1) between about 1×1018and about 1×1019atoms/cm2. The n-type well region102N is disposed over and electrically coupled to a backside conductive feature130. The backside conductive feature130may be referred to as a power rail or a backside power rail. In some embodiments illustrated inFIG. 1, the backside conductive feature130serves as or is electrically coupled to a first base electrode204. The first source/drain contact120-1serves as or is electrically coupled to a first emitter electrode202. The second source/drain contact120-2serves as or is electrically coupled to a first collector electrode206. To reduce contact resistance between the n-type well region102N and the backside conductive feature130, the first device structure100-1further includes a first epitaxial layer126-1and a silicide layer128. In some implementations, the first epitaxial layer126-1may include silicon (Si) and is epitaxially grown on the n-type well region. The silicide layer128interposes between the first epitaxial layer126-1and the backside conductive feature130. In some embodiments, the first epitaxial layer126-1is doped in-situ with an n-type dopant, such as phosphorus (P) or arsenic (As) and has a second doping concentration (C2) between about 1×1019and about 1×1020atoms/cm2. The second doping concentration (C2) is greater than the first doping concentration (C1) to reduce contact resistance. The silicide layer128may include titanium silicide (TiSi), nickel silicide (NiSi), cobalt silicide (CoSi), or titanium silicon nitride (TiSiN). The backside conductive feature130may be formed of tungsten (W), titanium (Ti), titanium nitride (TiN), ruthenium (Ru), cobalt (Co), nickel (Ni), or copper (Cu). In that sense, the backside conductive feature130is a metal line disposed below the first device structure100-1. Because the first device structure100-1is fabricated along with MBC transistors that serve core (i.e., logic) or memory functions, the dimensions of the backside conductive feature130, such as its length, thickness or width, are largely determined based on the designs of the MBC transistors. As will be described below, in some embodiments, isolation structures may be implemented to prevent shorting between an emitter and a base. An isolation structure may divide a backside conductive feature130into multiple segments.

Reference is now made toFIG. 2, which illustrates a fragmentary top view of the first device structure100-1. The n-type well region102N is doped region in a substrate102, which may be formed of a semiconductor material, such as silicon (Si). In some alternative embodiments, the substrate102may include other semiconductor materials, such as silicon germanium (SiGe) or germanium (Ge). A portion of the n-type well region102N may be patterned along with the plurality of channel members108to form a base portion or a semiconductor body disposed below the plurality of channel members108. Although not explicitly shown in the figures, the base portion formed of the n-type well region102N may be defined in an isolation feature. In some embodiments, the isolation feature may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric, combinations thereof, and/or other suitable materials. The isolation feature may also be referred to as a shallow trench isolation (STI) feature. With the substrate102flipped over, the first epitaxial layer126-1is epitaxially grown on the exposed surface of the n-type well region102N and the silicide layer128is formed over the first epitaxial layer126-1. After a planarization process, such as a CMP process, a dielectric layer is deposited over the STI feature and the silicide layer128. An opening is then formed in the dielectric layer by use of lithography processes and etch processes to expose the silicide layer128. Thereafter, the backside conductive feature130is deposited over the silicide layer128. The first epitaxial layer126-1, the silicide layer128, and the backside conductive feature130may substantially coincide around all edges along the Z direction. It can be seen fromFIGS. 1 and 2that the n-type well region102N extends lengthwise along the X direction and may be regarded as an elongated semiconductor body that is doped with an n-type dopant. The dielectric layer that surrounds the backside conductive feature130may be referred to as an interlayer dielectric (ILD) layer and may include materials such as tetraethylorthosilicate (TEOS) oxide, un-doped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and/or other suitable dielectric materials.

The first device structure100-1neither functions nor is electrically connected as an MBC transistor. As shown inFIG. 1, the gate structure110of the first device structure100-1is electrically floating and is not configured to turn on the channel members108. The first source/drain contact120-1may include or be resistively coupled to a first emitter electrode202. The second source/drain contact120-2may include or be resistively coupled to a first collector electrode206. The backside conductive feature130may include or be resistively coupled to a first base electrode204. When connected as such, the first device structure100-1may function as a P-N-P bipolar junction transistor (BJT)300-1, shown inFIG. 7. With reference toFIG. 1, a p-n junction of the P-N-P BJT300-1exists between the first p-type epitaxial feature116P-1and the n-type well region102N and an n-p junction of the P-N-P BJT300-1exists between the n-type well region102N and the second p-type epitaxial feature116P-2. It is noted that the n-type well region102N has a first minimum thickness T1measured from the silicide layer128along the Z direction. In some embodiments, the first minimum thickness (T1) may be between 50 nanometer (nm) and about 100 nm and, according to experiments, is sufficient to isolate the first p-type epitaxial feature116P-1from the silicide layer128to prevent shorting. The first minimum thickness T1is determined by the dielectric constant of the substrate102. Experimental results show that when the substrate102is formed of silicon with a dielectric constant of about 11.7, emitter-to-base short is more likely when the distance between the first p-type epitaxial feature116P-1(or the first n-type epitaxial feature116N-1) and the silicide layer128is less than 50 nm.

Reference is now made toFIG. 3, which illustrates a fragmentary cross-sectional view of a second device structure100-2. In the second device structure100-2, the n-type well region102N has a second minimum thickness T2between the silicide layer128and the first p-type epitaxial feature116P-1. When the second minimum thickness T2is between about 20 nm and about 50 nm, the first p-type epitaxial feature116P-1may be shorted to the silicide layer128, rendering the P-N-P BJT inoperative. To prevent the shorting between the first p-type epitaxial feature116P-1and the silicide layer128, the second device structure100-2includes an isolation structure132disposed directly below the first p-type epitaxial feature116P-1. The isolation structure132functions to prevent the silicide layer128(as well as the backside conductive feature130) from extending directly below the first p-type epitaxial feature116P-1and to increase spacing in between. The isolation structure132may include silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, or other suitable dielectric materials. As shown inFIGS. 3 and 4, besides the second minimum thickness T2and the isolation structure132, the second device structure100-2is similar to the first device structure100-1. With the isolation structure132in place, the first epitaxial layer126-1, the silicide layer128, and the backside conductive feature130may substantially coincide around all edges along the Z direction below the second p-type epitaxial feature116P-2. Detailed description of the second device structure100-2is therefore omitted for brevity.

Like the first device structure100-1, the second device structure100-2neither functions nor is electrically connected like an MBC transistor. As shown inFIG. 3, the gate structure110of the second device structure100-2is electrically floating and is not configured to turn on the channel members108. The first source/drain contact120-1may include or be resistively coupled to the first emitter electrode202. The second source/drain contact120-2may include or be resistively coupled to the first collector electrode206. The backside conductive feature130may include or be resistively coupled to the first base electrode204. When connected as such, the second device structure100-2may function as a P-N-P bipolar junction transistor (BJT)300-1, shown inFIG. 7. With reference toFIG. 3, a p-n junction of the P-N-P BJT300-1exists between the first p-type epitaxial feature116P-1and the n-type well region102N and an n-p junction of the P-N-P BJT300-1exists between the n-type well region102N and the second p-type epitaxial feature116P-2.

FIG. 5illustrates a fragmentary cross-sectional view of a third device structure100-3when viewed along the Y direction. As shown inFIG. 5, the third device structure100-3includes a plurality of channel members108extending along the X direction between a p-type epitaxial feature116P and an n-type epitaxial feature116N. Because the p-type epitaxial feature116P and the n-type epitaxial feature116N are fabricated along with MBC transistors, the p-type epitaxial feature116P may also be referred to as a p-type source/drain feature116P and the n-type epitaxial feature116N may also be referred to as an n-type source/drain feature116N. Like the first device structure100-1, the third device structure100-3includes a gate structure110that extends lengthwise along the Y direction. The gate structure110wraps around each of the plurality of channel members108. The gate structure110includes a gate dielectric layer112and a gate electrode114. The gate structure110is isolated from the p-type epitaxial feature116P and the n-type epitaxial feature116N by a plurality of inner spacer features118. The plurality of inner spacer features118interleave the plurality of channel members108. The third device structure100-3includes the first source/drain contact120-1disposed over and electrically coupled to the p-type epitaxial feature116P and a third source/drain contact120-3disposed over and electrically coupled to the n-type epitaxial feature116N. In some implementations represented inFIG. 5, each of the first source/drain contact120-1and the third source/drain contact120-3includes a barrier layer122and a metal fill layer124.

The channel members108, the gate dielectric layer112, gate electrode114, the inner spacer features118, the first source/drain contact120-1, and the third source/drain contact120-3of the third device structure100-3may be similar to those in the first device structure100-1shown inFIG. 1. Detailed descriptions of them are therefore omitted for brevity.

The gate structure110, the p-type epitaxial feature116P, the n-type epitaxial feature116N, and the bottommost inner spacer features118are disposed on an n-type well region102N. In some implementations, the n-type well region102N is doped with an n-type dopant such as phosphorus (P) or arsenide (As) and has a first doping concentration (C1) between about 1×1018and about 1×1019atoms/cm2. The n-type well region102N is disposed over and electrically coupled to a backside conductive feature130. The backside conductive feature130may be referred to as a power rail or backside power rail. In some embodiments illustrated inFIG. 5, the backside conductive feature130serves as or is electrically coupled to the first collector electrode206. The first source/drain contact120-1serves as or is electrically coupled to the first emitter electrode202. The third source/drain contact120-3serves as or is electrically coupled to the first base electrode204. In order to form a P-N-P BJT, the third device structure100-3further includes a rectifying Schottky junction below the n-type well region102N. The rectifying Schottky junction may also be referred to as a Schottky barrier junction or a Schottky barrier contact. In some instances shown inFIG. 5, the third device structure100-3includes a silicide layer128and the rectifying Schottky junction exists between the n-type well region102N and the silicide layer128. The silicide layer128may include titanium silicide (TiSi), nickel silicide (NiSi), cobalt silicide (CoSi), or titanium silicon nitride (TiSiN). The backside conductive feature130may be formed of tungsten (W), titanium (Ti), titanium nitride (TiN), ruthenium (Ru), cobalt (Co), nickel (Ni), or copper (Cu).

Reference is now made toFIG. 6, which illustrates a fragmentary top view of the third device structure100-3. The n-type well region102N is doped region in a substrate102, which may be formed of a semiconductor material, such as silicon (Si). In some alternative embodiments, the substrate102may include other semiconductor materials, such as silicon germanium (SiGe) or germanium (Ge). A portion of the n-type well region102N may be patterned along with the plurality of channel members108to form a base portion or a semiconductor body disposed below the plurality of channel members108. Although not explicitly shown in the figures, the base portion formed of the n-type well region102N may be defined in an isolation feature. In some embodiments, the isolation feature may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric, combinations thereof, and/or other suitable materials. The isolation feature may also be referred to as a shallow trench isolation (STI) feature. With the substrate102flipped over, the silicide layer128is formed on the exposed surface of the n-type well region102N. After a planarization process, such as a CMP process, an ILD layer is deposited over the isolation feature and the silicide layer128. An opening is then formed in the ILD layer by use of lithography processes and etch processes to expose the silicide layer128. Thereafter, the backside conductive feature130is deposited over the silicide layer128. It can be seen fromFIGS. 5 and 6that the n-type well region102N extends lengthwise along the X direction and may be regarded as an elongated semiconductor body that is doped with an n-type dopant. As shown inFIG. 6, the first epitaxial layer126-1, the silicide layer128, and the backside conductive feature130may substantially coincide around all edges along the Z direction. As the ILD layer has been described before, detailed description thereof will not be repeated here for brevity.

The third device structure100-3neither functions nor is electrically connected like an MBC transistor. As shown inFIG. 5, the gate structure110of the third device structure100-3is electrically floating and is not configured to turn on the channel members108. The first source/drain contact120-1may include or be resistively coupled to the first emitter electrode202. The third source/drain contacts120-3may include or be resistively coupled to the first base electrode204. The backside conductive feature130may include or be resistively coupled to the first collector electrode206. When connected as such, the third device structure100-3may function as a P-N-P bipolar junction transistor (BJT)300-1, shown inFIG. 7. With reference toFIG. 5, a p-n junction of the P-N-P BJT300-1exists between the p-type epitaxial feature116P and the n-type well region102N and an n-p junction of the P-N-P BJT300-1exists between the n-type well region102N and the Schottky junction between the n-type well region102N and the silicide layer128. The n-type epitaxial feature116N is coupled to the n-type well region102N by ohmic contact. It is noted that the n-type well region102N of the third device structure100-3has a first minimum thickness T1measured from the silicide layer128along the Z direction. In some embodiments, the first minimum thickness (T1) may be between 50 nm and about 100 nm and, according to experiments, is sufficient to isolate the p-type epitaxial feature116P from the silicide layer128to prevent shorting.

The present disclosure also provides embodiments of N-P-N BJT structures, such as the device structures shown inFIGS. 8-13.

FIG. 8illustrates a fragmentary cross-sectional view of a fourth device structure100-4viewed along the Y direction. The fourth device structure100-4includes a plurality of channel members108extending along the X direction between a first n-type epitaxial feature116N-1and a second n-type epitaxial feature116N-2. Because the first n-type epitaxial feature116N-1and the second n-type epitaxial feature116N-2are fabricated along with MBC transistors, they may also be referred to as first and second n-type source/drain features116N-1and116N-2, respectively. The fourth device structure100-4includes a gate structure110that extends lengthwise along the Y direction. The gate structure110wraps around each of the plurality of channel members108. As shown inFIG. 8, the gate structure110includes a gate dielectric layer112and a gate electrode114. The gate structure110is isolated from the first and second n-type source/drain features116N-1and116N-2by a plurality of inner spacer features118. The plurality of inner spacer features118interleave the plurality of channel members108. A fourth source/drain contact120-4is disposed over and electrically coupled to the first n-type source/drain feature116N-1and a fifth source/drain contact120-5is disposed over and electrically coupled to the second n-type source/drain feature116N-2. In some implementations represented inFIG. 8, each of the fourth source/drain contact120-4and the fifth source/drain contact120-5includes a barrier layer122and a metal fill layer124.

The channel members108, the gate dielectric layer112, the gate electrode114, the inner spacer features118, the metal filler layer124, and the barrier layer122in the fourth device structure100-4may be similar to counterparts in the first device structure100-1and detailed description of them are omitted for brevity. The first n-type epitaxial feature116N-1and the second n-type epitaxial feature116N-2may include a semiconductor material such as silicon and is doped with an n-type dopant, such as phosphorus (P) or arsenic (As).

The gate structure110, the first n-type epitaxial feature116N-1, the second n-type epitaxial feature116N-2, and the bottommost inner spacer features118are disposed on a p-type well region102P. In some implementations, the p-type well region102P is doped with a p-type dopant such as boron (B) and has a third doping concentration (C3) between about 1×1018and about 1×1019atoms/cm2. The p-type well region102P is disposed over and electrically coupled to a backside conductive feature130. The backside conductive feature130may be referred to as a power rail or a backside power rail. In some embodiments illustrated inFIG. 8, the backside conductive feature130serves as or is electrically coupled to a second base electrode214. The fourth source/drain contact120-4serves as or is electrically coupled to a second emitter electrode212. The fifth source/drain contact120-5serves as or is electrically coupled to a second collector electrode216. To reduce contact resistance between the p-type well region102P and the backside conductive feature130, the fourth device structure100-4further includes a second epitaxial layer126-2and a silicide layer128. In some implementations, the second epitaxial layer126-2may include silicon germanium (SiGe) and is epitaxially grown on the p-type well region102P. The silicide layer128interposes between the second epitaxial layer126-2and the backside conductive feature130. In some embodiments, the second epitaxial layer126-2is doped in-situ with a p-type dopant, such as boron (B), and has a fourth doping concentration (C4) between about 1×1019and about 1×1020atoms/cm2. The fourth doping concentration (C4) is greater than the third doping concentration (C3) to reduce contact resistance. The silicide layer128may include titanium silicide (TiSi), nickel silicide (NiSi), cobalt silicide (CoSi), or titanium silicon nitride (TiSiN). The backside conductive feature130may be formed of tungsten (W), titanium (Ti), titanium nitride (TiN), ruthenium (Ru), cobalt (Co), nickel (Ni), or copper (Cu).

Reference is now made toFIG. 9, which illustrates a fragmentary top view of the fourth device structure100-4. The p-type well region102P is doped region in a substrate102, which may be formed of a semiconductor material, such as silicon (Si). In some alternative embodiments, the substrate102may include other semiconductor materials, such as silicon germanium (SiGe) or germanium (Ge). A portion of the p-type well region102P may be patterned along with the plurality of channel members108to form a base portion or a semiconductor body disposed below the plurality of channel members108. Although not explicitly shown in the figures, the base portion formed of the p-type well region102P may be defined in an STI feature. With the substrate102flipped over, the second epitaxial layer126-2is epitaxially grown on the exposed surface of the p-type well region102P and the silicide layer128is formed on the second epitaxial layer126-2. After a planarization process, such as a CMP process, an ILD layer is deposited over the isolation feature and the silicide layer128. An opening is then formed in the ILD layer by use of lithography processes and etch processes to expose the silicide layer128. Thereafter, the backside conductive feature130is deposited over the silicide layer128. It can be seen fromFIGS. 8 and 9that the p-type well region102P extends lengthwise along the X direction and may be regarded as an elongated semiconductor body that is doped with a p-type dopant. As shown inFIG. 9, the second epitaxial layer126-2, the silicide layer128, and the backside conductive feature130may substantially coincide around all edges along the Z direction. As the ILD layer has been described before, detailed description thereof will not be repeated here for brevity.

The fourth device structure100-4neither functions nor is electrically connected like an MBC transistor. As shown inFIG. 8, the gate structure110of the fourth device structure100-4is electrically floating and is not configured to turn on the channel members108. The fourth source/drain contact120-4may include or be resistively coupled to the second emitter electrode212. The fifth source/drain contact120-5may include or be resistively coupled to the second collector electrode216. The backside conductive feature130may include or be resistively coupled to the second base electrode214. When connected as such, the fourth device structure100-4may function as an N-P-N bipolar junction transistor (BJT)300-2, shown inFIG. 14. With reference toFIG. 8, an n-p junction of the N-P-N BJT300-2exists between the first n-type epitaxial feature116N-1and the p-type well region102P and a p-n junction of the N-P-N BJT300-2exists between the p-type well region102P and the second n-type epitaxial feature116N-2. It is noted that the p-type well region102P has a first minimum thickness T1measured from the silicide layer128along the Z direction. In some embodiments, the first minimum thickness (T1) may be between 50 nm and about 100 nm and, according to experiments, is sufficient to isolate the first n-type epitaxial feature116N-1from the silicide layer128to prevent shorting.

Reference is now made toFIG. 10, which illustrates a fragmentary cross-sectional view of a fifth device structure100-5. In the fifth device structure100-5, the p-type well region102P has a second minimum thickness T2between the silicide layer128and the first n-type epitaxial feature116N-1. When the second minimum thickness T2is between about 20 nm and about 50 nm, the first n-type epitaxial feature116N-1may be shorted to the silicide layer128, rendering the N-P-N BJT inoperative. To prevent the shorting between the first n-type epitaxial feature116N-1and the silicide layer128, the fifth device structure100-5includes an isolation structure132disposed directly below the first n-type epitaxial feature116N-1. The isolation structure132functions to prevent the silicide layer128(as well as the backside conductive feature130) from extending directly below the first n-type epitaxial feature116N-1and to increase spacing in between. The isolation structure132may include silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, or other suitable dielectric materials. As shown inFIGS. 10 and 11, besides the second minimum thickness T2and the isolation structure132, the fifth device structure100-5is similar to the fourth device structure100-4. Referring toFIG. 11, with the isolation structure132in place, the second epitaxial layer126-2, the silicide layer128, and the backside conductive feature130may substantially coincide around all edges along the Z direction below the second n-type epitaxial feature116N-2. Detailed description of the fifth device structure100-5is therefore omitted for brevity.

Like the fourth device structure100-4, the fifth device structure100-5neither functions nor is electrically connected like an MBC transistor. As shown inFIG. 10, the gate structure110of the fifth device structure100-5is electrically floating and is not configured to turn on the channel members108. The fourth source/drain contact120-4may include or be resistively coupled to the second emitter electrode212. The fifth source/drain contact120-5may include or be resistively coupled to the second collector electrode216. The backside conductive feature130may include or be resistively coupled to the second base electrode214. When connected as such, the fifth device structure100-5may function as an N-P-N bipolar junction transistor (BJT)300-2, shown inFIG. 14. With reference toFIG. 10, an n-p junction of the N-P-N BJT300-2exists between the first n-type epitaxial feature116N-1and the p-type well region102P and a p-n junction of the N-P-N BJT300-2exists between the p-type well region102P and the second n-type epitaxial feature116N-2.

FIG. 12illustrates a fragmentary cross-sectional view of a sixth device structure100-6when viewed along the Y direction. As shown inFIG. 12, the sixth device structure100-6includes a plurality of channel members108extending along the X direction between an n-type epitaxial feature116N and a p-type epitaxial feature116P. Because the n-type epitaxial feature116N and the p-type epitaxial feature116P are fabricated along with MBC transistors, the n-type epitaxial feature116N may also be referred to as an n-type source/drain feature116N and the p-type epitaxial feature116P may also be referred to as a p-type source/drain feature116P. The sixth device structure100-6includes a gate structure110that extends lengthwise along the Y direction. The gate structure110wraps around each of the plurality of channel members108. The gate structure110includes a gate dielectric layer112and a gate electrode114. The gate structure110is isolated from the n-type epitaxial feature116N and the p-type epitaxial feature116P by a plurality of inner spacer features118. The plurality of inner spacer features118interleave the plurality of channel members108. The sixth device structure100-6includes the fourth source/drain contact120-4disposed over and electrically coupled to the n-type epitaxial feature116N and a sixth source/drain contact120-6disposed over and electrically coupled to the p-type epitaxial feature116P. In some implementations represented inFIG. 12, each of the fourth source/drain contact120-4and the sixth source/drain contact120-6includes a barrier layer122and a metal fill layer124.

The channel members108, the gate dielectric layer112, gate electrode114, the inner spacer features118, the fourth source/drain contact120-4, and the sixth source/drain contact120-6of the sixth device structure100-6may be similar to those of the fourth device structure100-4shown inFIG. 8. Detailed descriptions of them are therefore omitted for brevity.

The gate structure110, the n-type epitaxial feature116N, the p-type epitaxial feature116P, and the bottommost inner spacer features118are disposed on the p-type well region102P. In some implementations, the p-type well region102P is doped with a p-type dopant such as boron (B) and has a third doping concentration (C3) between about 1×1018and about 1×1019atoms/cm2. The p-type well region102P is disposed over and electrically coupled to a backside conductive feature130. In some embodiments illustrated inFIG. 12, the backside conductive feature130serves as or is electrically coupled to the second collector electrode216. The fourth source/drain contact120-4serves as or is electrically coupled to the second emitter electrode212. The sixth source/drain contact120-6serves as or is electrically coupled to the second base electrode214. In order to form an N-P-N BJT, the sixth device structure100-6further includes a rectifying Schottky junction below the p-type well region102P. The rectifying Schottky junction may also be referred to as a Schottky barrier junction or a Schottky barrier contact. In some instances shown inFIG. 12, the sixth device structure100-6includes a silicide layer128and the rectifying Schottky junction exists between the p-type well region102P and the silicide layer128. The silicide layer128may include titanium silicide (TiSi), nickel silicide (NiSi), cobalt silicide (CoSi), or titanium silicon nitride (TiSiN). The backside conductive feature130may be formed of tungsten (W), titanium (Ti), titanium nitride (TiN), ruthenium (Ru), cobalt (Co), nickel (Ni), or copper (Cu).

Reference is now made toFIG. 13, which illustrates a fragmentary top view of the sixth device structure100-6. The p-type well region102P is doped region in a substrate102, which may be formed of a semiconductor material, such as silicon (Si). In some alternative embodiments, the substrate102may include other semiconductor materials, such as silicon germanium (SiGe) or germanium (Ge). A portion of the p-type well region102P may be patterned along with the plurality of channel members108to form a base portion or a semiconductor body disposed below the plurality of channel members108. Although not explicitly shown in the figures, the base portion formed of the p-type well region102P may be defined in an STI feature. With the substrate102flipped over, the silicide layer128is formed on the exposed surface of the p-type well region102P. After a planarization process, an ILD layer is deposited over the STI feature and the silicide layer128. An opening is then formed in the ILD layer by use of lithography processes and etch processes to expose the silicide layer128. Thereafter, the backside conductive feature130is deposited over the silicide layer128. As shown inFIG. 13, the second epitaxial layer126-2, the silicide layer128, and the backside conductive feature130may substantially coincide around all edges along the Z direction.

The sixth device structure100-6neither functions nor is electrically connected like an MBC transistor. As shown inFIG. 12, the gate structure110of the sixth device structure100-6is electrically floating and is not configured to turn on the channel members108. The fourth source/drain contacts120-4may include or be resistively coupled to the second emitter electrode212. The sixth source/drain contacts120-6may include or be resistively coupled to the second base electrode214. The backside conductive feature130may include or be resistively coupled to the second collector electrode216. When connected as such, the sixth device structure100-6may function as an N-P-N bipolar junction transistor (BJT)300-2, shown inFIG. 14. With reference toFIG. 12, an n-p junction of the N-P-N BJT300-2exists between the n-type epitaxial feature116N and the p-type well region102P and a p-n junction of the N-P-N BJT300-2exists between the p-type well region102P and the Schottky junction between the p-type well region102P and the silicide layer128. The p-type epitaxial feature116P is coupled to the p-type well region102P by ohmic contact. It is noted that the p-type well region102P has a first minimum thickness T1measured from the silicide layer128along the Z direction. In some embodiments, the first minimum thickness (T1) may be between 50 nm and about 100 nm and, according to experiments, is sufficient to isolate the n-type epitaxial feature116N from the silicide layer128to prevent shorting.

Reference is now made toFIG. 15. A plurality of the first device structure100-1, the second device structure100-2, the third device structure100-3, the fourth device structure100-4, the fifth device structure100-5, and the sixth device structure100-6may be connected in parallel to function as one BJT. For ease of reference, the first device structure100-1, the second device structure100-2, the third device structure100-3, the fourth device structure100-4, the fifth device structure100-5, and the sixth device structure100-6may be collectively referred to a device100and illustrated as such inFIG. 15. Each of the first device structure100-1, the second device structure100-2, the third device structure100-3, the fourth device structure100-4, the fifth device structure100-5, and the sixth device structure100-6may serve as a repeating unit and be duplicated along the X direction and the Y direction in a semiconductor device400. As used herein, connection in parallel refers to connecting all emitter electrodes together, connecting all collector electrodes together, and connecting all base electrodes together. In some embodiments illustrated inFIG. 15, emitter electrodes of the repeating devices100may be coupled together by a first slot source/drain contact1201extending along the Y direction. Depending on the design of the device100, a second slot source/drain contact1202, which also extends along the Y direction, may be used to couple collector electrodes (for example, when the device100is the first device structure100-1, the second device structure100-2, the fourth device structure100-4, or the fifth device structure100-5) or base electrodes (for example, when the device100is the third device structure100-3or the sixth device structure100-6). In the depicted embodiments, common backside conductive features1301and1302, which may extend along the Y direction, may be implemented to couple together base electrodes (for example, when the device100is the first device structure100-1or the fourth device structure100-4) or collector electrodes (for example, when the device100is the third device structure100-3or the sixth device structure100-6). Repeating devices100arranged along the Y direction may share the same gate structure110, which is electrically floating. The isolation structure132in the second device structure100-2or the fifth device structure100-5may prevent a common backside conductive feature from extending along the X direction. Although not explicitly shown inFIG. 15, when the device100(as the repeating unit) is the second device structure100-2or the fifth device structure100-5, the common backside conductive feature may extend below and parallel to the second slot source/drain contact1202, rather than extending perpendicular to the second slot source/drain contact1202.

In one example aspect, the present disclosure provides a bipolar junction transistor (BJT) in accordance with some embodiments. The BJT includes a first epitaxial feature disposed over a well region, a second epitaxial feature disposed over the well region, a vertical stack of channel members each extending lengthwise between the first epitaxial feature and the second epitaxial feature, a gate structure wrapping around each of the vertical stack of channel members, a first electrode coupled to the well region, an emitter electrode disposed over and coupled to the first epitaxial feature, and a second electrode disposed over and coupled to the second epitaxial feature.

In some embodiments, the gate structure is electrically floating. In some implementations, the first epitaxial feature and the second epitaxial feature include silicon and an n-type dopant, the well region includes a p-type dopant and the first electrode includes a base electrode, and the second electrode includes a collector electrode. In some embodiments, the first epitaxial feature and the second epitaxial feature include silicon germanium and a p-type dopant, the well region includes an n-type dopant, the first electrode includes a base electrode, and the second electrode includes a collector electrode. In some instances, the first epitaxial feature includes silicon germanium and a p-type dopant, the second epitaxial feature includes silicon and an n-type dopant, the well region includes the n-type dopant, the first electrode includes a collector electrode, and the second electrode includes a base electrode. In some embodiments, the BJT may further include a silicide layer disposed between the well region and the first electrode. In some instances, the BJT may further include an epitaxial layer disposed between the silicide layer and the well region. In some implementations, the BJT may further include an isolation structure disposed below the first epitaxial feature. The isolation structure prevents the first electrode from extending directly below the first epitaxial feature. In some embodiments, the BJT may further include a plurality of inner spacer features interleaving the vertical stack of channel members.

Another one aspect of the present disclosure pertains to a semiconductor structure. The semiconductor structure includes a first epitaxial feature and a second epitaxial feature disposed over a first well region, a third epitaxial feature and a fourth epitaxial feature disposed over a second well region, a gate structure disposed between the first epitaxial feature and the second epitaxial feature and between the third epitaxial feature and the fourth epitaxial feature, a first electrode coupled to the first well region, a second electrode coupled to the second well region, a common emitter electrode disposed over and coupled to the first epitaxial feature and the third epitaxial feature, and a third electrode disposed over and coupled to the second epitaxial feature and the fourth epitaxial feature.

In some embodiments, the gate structure is electrically floating. In some implementations, the first epitaxial feature, the second epitaxial feature, the third epitaxial feature, and the fourth epitaxial feature include silicon and an n-type dopant, the first well region and the second well region include a p-type dopant, the first electrode and the second electrode are coupled to a base electrode, and the third electrode includes a collector electrode. In some implementations, the first epitaxial feature, the second epitaxial feature, the third epitaxial feature, and the fourth epitaxial feature include silicon germanium and a p-type dopant, the first well region and the second well region include an n-type dopant, the first electrode and the second electrode are coupled to a common base electrode, and the third electrode includes a common collector electrode. In some implementations, the first epitaxial feature and the third epitaxial feature include silicon germanium and a p-type dopant, the second epitaxial feature and the fourth epitaxial feature include silicon and an n-type dopant, the first well region and the second well region include the n-type dopant, the first electrode and the second electrode are coupled to a common collector electrode, and the third electrode includes a common base electrode. In some instances, the first electrode is disposed below the second epitaxial feature and the second electrode is disposed below the fourth epitaxial feature. In some embodiments, the semiconductor structure may further include an isolation structure disposed below the first epitaxial feature. The isolation structure prevents the first electrode from extending directly below the first epitaxial feature. The first well region includes a thickness between about 20 nanometer (nm) and about 50 nm below the first epitaxial feature.

Yet another aspect of the present disclosure pertains to a semiconductor device. The semiconductor device includes a first-type epitaxial feature and a second-type epitaxial feature disposed over a semiconductor body, a silicide layer disposed below and in contact with the semiconductor body, and a metal line disposed below and in contact with the silicide layer. The silicide layer and the semiconductor body include a Schottky junction. In some embodiments, the first-type epitaxial feature includes silicon germanium and a p-type dopant, the second-type epitaxial feature includes silicon and an n-type dopant, and the semiconductor body is doped with the n-type dopant. In some implementations, the first-type epitaxial feature includes silicon and an n-type dopant, the second-type epitaxial feature includes silicon germanium and a p-type dopant, and the semiconductor body is doped with the p-type dopant. In some instances, the semiconductor device may further include a vertical stack of channel members sandwiched between the first-type epitaxial feature and the second-type epitaxial feature, and a gate structure wrapping around each of the vertical stack of channel members. Each of the first-type epitaxial feature and the second-type epitaxial feature is spaced apart from the gate structure by a plurality of inner spacer features.