Liquid crystal display and method for operating the same

A liquid crystal display (LCD) and an operating method thereof are provided. The operating method includes the following steps. It is determined whether a first frame and a second frame following the first frame are dynamic frames. When the first frame and the second frame are dynamic frames, a timing controller of the LCD performs a polarity inversion on a polarity signal, so that the polarity signal corresponding to the first frame is the same as the polarity signal corresponding to the second frame. When the second frame is written into an LCD panel of the LCD, energy written into the LCD panel is reduced.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a display and a method for operating the same. Particularly, the invention relates to a liquid crystal display and a method for operating the same.

2. Description of Related Art

Along with quick development of photoelectric technology and semiconductor techn39712ology, flat panel displays such as liquid crystal displays (LCDs) are quickly developed in recent years. Since the LCD has advantages of low power consumption, no irradiation and high spatial usage rate, etc., it becomes a main stream in today's flat panel display market. Since an LCD panel does not emit light itself, a backlight module has to be configured at the back of the LCD panel for providing a planar light source required by the LCD panel. The LCD panel controls a rotation angle of liquid crystal to adjust light transmittance and reflectivity of the light source, so as to display images.

Generally, the rotation angle of the liquid crystal is determined by a voltage difference of two ends of the liquid crystal layer and a direction of an electric field. In order to avoid a liquid crystal polarization phenomenon, the LCD generally applies a driving method of polarity inversion, i.e. voltages of different polarities (for example, a positive polarity and a negative polarity) are used to alternatively drive the liquid crystal at different time. The polarity of the voltage applied on the liquid crystal is determined by the direction of the electric field applied on the liquid crystal. Assuming a voltage of a pixel electrode is greater than a common voltage, the liquid crystal is driven by the voltage of the positive polarity. Conversely, the liquid crystal is driven by the voltage of the negative polarity.

However, when the LCD panel displays dynamic frames, a gray value displayed by each pixel on the LCD panel is probably varied constantly. In case of gray value variation, the liquid crystal of the LCD panel may have the polarization phenomenon, i.e. the liquid crystal in the pixels may have remained DC voltages, which may cause motion blur of the LCD panel.

SUMMARY OF THE INVENTION

The invention is directed to a liquid crystal display (LCD) and a method for operating the same, in which a polarity signal inversion is performed to reduce a chance of generating motion blur on an LCD panel. Moreover, a frame flicking phenomenon caused by polarity signal inversion is suppressed.

The invention provides a method for operating a liquid crystal display (LCD), which includes the following steps. It is determined whether a first frame and a second frame following the first frame are dynamic frames. When the first frame and the second frame are the dynamic frames, a timing controller of the LCD performs a polarity inversion on a polarity signal to equalize the polarity signal corresponding to the first frame with the polarity signal corresponding to the second frame. When the second frame is written into an LCD panel of the LCD, energy written into the LCD panel is reduced.

In an embodiment of the invention, the step of reducing the energy written into the LCD panel includes shortening a pulse width of an output enable signal or a gate clock signal to shorten pulse widths of a plurality of scan signals output to the LCD panel.

In an embodiment of the invention, the method for operating the LCD further includes following steps. When a frame rate of the LCD is decreased to be smaller than a first frame rate threshold, the pulse width of the output enable signal or the gate clock signal is set to a first pulse width. When the frame rate of the LCD is increased to be greater than a second frame rate threshold, the pulse width of the output enable signal or the gate clock signal is set to a second pulse width, where the first frame rate threshold is greater than the second frame rate threshold, and the first pulse width is greater than the second pulse width.

In an embodiment of the invention, the method for operating the LCD further includes following steps. When a working temperature of the LCD is decreased to be smaller than a first temperature threshold, the pulse width of the output enable signal or the gate clock signal is set to a third pulse width. When the working temperature of the LCD is increased to be greater than a second temperature threshold, the pulse width of the output enable signal or the gate clock signal is set to a fourth pulse width, where the first temperature threshold is greater than the second temperature threshold, and the third pulse width is greater than the fourth pulse width.

In an embodiment of the invention, the step of reducing the energy written into the LCD panel includes delaying a latch signal to shorten output time of a plurality of pixel voltages output to the LCD panel.

In an embodiment of the invention, the method for operating the LCD further includes following steps. When a frame rate of the LCD is decreased to be smaller than a first frame rate threshold, a delay time of the latch signal is set to a first delay time. When the frame rate of the LCD is increased to be greater than a second frame rate threshold, the delay time of the latch signal is set to a second delay time, where the first frame rate threshold is greater than the second frame rate threshold, and the first delay time is greater than the second delay time.

In an embodiment of the invention, the method for operating the LCD further includes following steps. When a working temperature of the LCD is decreased to be smaller than a first temperature threshold, a delay time of the latch signal is set to a third delay time. When the working temperature of the LCD is increased to be greater than a second temperature threshold, the delay time of the latch signal is set to a fourth delay time, where the first temperature threshold is greater than the second temperature threshold, and the third delay time is smaller than the fourth delay time.

In an embodiment of the invention, the step of reducing the energy written into the LCD panel includes reducing gray values corresponding to a plurality of pixel voltages output to the LCD panel.

In an embodiment of the invention, the method for operating the LCD further includes following steps. When a frame rate of the LCD is decreased to be smaller than a first frame rate threshold, the gray values corresponding to the pixel voltages are decreased by a first gray value. When the frame rate of the LCD is increased to be greater than a second frame rate threshold, the gray values corresponding to the pixel voltages are decreased by a second gray value, where the first frame rate threshold is greater than the second frame rate threshold, and the first gray value is greater than the second gray value.

In an embodiment of the invention, the method for operating the LCD further includes following steps. When a working temperature of the LCD is decreased to be smaller than a first temperature threshold, the gray values corresponding to the pixel voltages are decreased by a third gray value. When the working temperature of the LCD is increased to be greater than a second temperature threshold, the gray values corresponding to the pixel voltages are decreased by a fourth gray value, where the first temperature threshold is greater than the second temperature threshold, and the third gray value is smaller than the fourth gray value.

In an embodiment of the invention, the method for operating the LCD further includes stopping performing the polarity inversion on the polarity signal when one of the first frame and the second frame is a static frame.

In an embodiment of the invention, the step of determining whether the first frame is the dynamic frame includes following steps. When the first frame and a plurality of consecutive previous frames are different, it is determined that the first frame is the dynamic frame. When two neighbouring frames of the first frame and the previous frames are the same, it is determined that the first frame is a static frame, where the first frame follows the previous frames.

The invention also provides a liquid crystal display (LCD) including an LCD panel, a gate driver, a source driver and a timing controller. The gate driver is coupled to the LCD panel for outputting a plurality of scan signals to the LCD panel. The source driver is coupled to the LCD panel for outputting a plurality of pixel voltages to the LCD panel. The timing controller is coupled to the gate driver and the source driver for receiving a first frame and a second frame following the first frame, and determining whether the first frame and the second frame are dynamic frames. When the first frame and the second frame are the dynamic frames, the timing controller performs a polarity inversion on a polarity signal output to the source driver to equalize the polarity signal corresponding to the first frame with the polarity signal corresponding to the second frame. When the second frame is written into the LCD panel, the timing controller adjusts output states of the scan signals or the pixel voltages to reduce energy written into the LCD panel.

In an embodiment of the invention, the timing controller shortens a pulse width of an output enable signal or a gate clock signal output to the gate driver to shorten pulse widths of the scan signals output to the LCD panel.

In an embodiment of the invention, when a frame rate of the LCD is decreased to be smaller than a first frame rate threshold, the timing controller sets the pulse width of the output enable signal or the gate clock signal to a first pulse width. When the frame rate of the LCD is increased to be greater than a second frame rate threshold, the timing controller sets the pulse width of the output enable signal or the gate clock signal to a second pulse width, where the first frame rate threshold is greater than the second frame rate threshold, and the first pulse width is greater than the second pulse width.

In an embodiment of the invention, when a working temperature of the LCD is decreased to be smaller than a first temperature threshold, the timing controller sets the pulse width of the output enable signal or the gate clock signal to a third pulse width. When the working temperature of the LCD is increased to be greater than a second temperature threshold, the timing controller sets the pulse width of the output enable signal or the gate clock signal to a fourth pulse width, where the first temperature threshold is greater than the second temperature threshold, and the third pulse width is greater than the fourth pulse width.

In an embodiment of the invention, the timing controller delays a latch signal output to the source driver to shorten output time of the pixel voltages output to the LCD panel.

In an embodiment of the invention, when a frame rate of the LCD is decreased to be smaller than a first frame rate threshold, the timing controller sets a delay time of the latch signal to a first delay time. When the frame rate of the LCD is increased to be greater than a second frame rate threshold, the timing controller sets the delay time of the latch signal to a second delay time, where the first frame rate threshold is greater than the second frame rate threshold, and the first delay time is greater than the second delay time.

In an embodiment of the invention, when a working temperature of the LCD is decreased to be smaller than a first temperature threshold, the timing controller sets a delay time of the latch signal to a third delay time. When the working temperature of the LCD is increased to be greater than a second temperature threshold, the timing controller sets the delay time of the latch signal to a fourth delay time, where the first temperature threshold is greater than the second temperature threshold, and the third delay time is smaller than the fourth delay time.

In an embodiment of the invention, the timing controller controls the source driver to reduce gray values corresponding to a plurality of pixel voltages output to the LCD panel.

In an embodiment of the invention, when a frame rate of the LCD is decreased to be smaller than a first frame rate threshold, the timing controller controls the source driver to decrease the gray values corresponding to the pixel voltages by a first gray value. When the frame rate of the LCD is increased to be greater than a second frame rate threshold, the timing controller controls the source driver to decrease the gray values corresponding to the pixel voltages by a second gray value, where the first frame rate threshold is greater than the second frame rate threshold, and the first gray value is greater than the second gray value.

In an embodiment of the invention, when a working temperature of the LCD is decreased to be smaller than a first temperature threshold, the timing controller controls the source driver to decrease the gray values corresponding to the pixel voltages by a third gray value. When the working temperature of the LCD is increased to be greater than a second temperature threshold, the timing controller controls the source driver to decrease the gray values corresponding to the pixel voltages by a fourth gray value, where the first temperature threshold is greater than the second temperature threshold, and the third gray value is smaller than the fourth gray value.

In an embodiment of the invention, when one of the first frame and the second frame is a static frame, the timing controller stops performing the polarity inversion on the polarity signal.

In an embodiment of the invention, when the first frame and a plurality of consecutive previous frames are different, the timing controller determines the first frame to be the dynamic frame. When two neighbouring frames of the first frame and the previous frames are the same, the timing controller determines the first frame to be a static frame, where the first frame follows the previous frames.

According to the above descriptions, in the LCD and the method for operating the same, when the first frame and the second frame are all dynamic frames, the timing controller performs the polarity inversion on the polarity signal to equalize the polarity signal corresponding to the first frame with the polarity signal corresponding to the second frame, so as to suppress polarization of liquid crystal of the LCD panel. Moreover, the timing controller adjusts the scan signals or the pixel voltages to reduce the energy of the second frame written into the LCD panel, and avoid a frame flicking phenomenon occurred when the LCD panel displays the brighter second frame.

DETAILED DESCRIPTION OF DISCLOSED EMBODIMENTS

FIG. 1is a system schematic diagram of a liquid crystal display (LCD) according to an embodiment of the invention. Referring toFIG. 1, in the present embodiment, the LCD100includes a timing controller110, a gate driver120, a source driver130, an LCD panel140and gamma voltage generator150. The timing controller110is coupled to the gate driver120, the source driver130and the gamma voltage generator150, and the gate driver120and the source driver130are respectively coupled to the LCD panel140. The gamma voltage generator150is used for generating a plurality of gamma voltages VG to the source driver130.

The timing controller110sequentially receives a plurality of consecutive previous frames PF, a first frame F1and a second frame F2, and outputs a plurality of display data DD, a latch signal TP and a polarity signal POL to the source driver130according to the previous frames PF, the first frame F1and the second frame F2, so as to control the source driver130to output a plurality of pixel voltages VP to the LCD panel140according to the received gamma voltages VG. Moreover, the timing controller110outputs a gate clock signal CPV and an output enable signal OE to the gate driver120for controlling the gate driver120to output a plurality of scan signals SC to the LCD panel140. The LCD panel140is driven by the scan signals SC to receive the pixel voltages VP, and displays images corresponding to the previous frames PF, the first frame F1or the second frame F2.

Moreover, the timing controller110determines whether the first frame F1and the second frame F2are dynamic frames. When the first frame F1and the second frame F2are all dynamic frames, the timing controller110can perform a polarity inversion on the polarity signal POL to equalize the polarity signal POL corresponding to the first frame F1with the polarity signal POL corresponding to the second frame F2, so as to reduce a chance that liquid crystal of the LCD panel140is polarized when the LCD panel140displays dynamic images. Conversely, when one of the first frame F1and the second frame F2is determined to be a static frame, the timing controller110stops performing the polarity inversion on the polarity signal POL.

In case that the polarity signal POL corresponding to the first frame F1is the same to the polarity signal POL corresponding to the second frame F2, each of pixels (not shown) of the LCD panel140has a same polarity charging phenomenon, i.e. polarities of the pixel voltage VP corresponding to each of the pixels in the first frame F1and the second frame F2are the same. In case of the same polarity charging, the second frame F2displayed by the LCD panel140is brighter, which may cause a frame flicking phenomenon. Therefore, when the second frame F2is written into the LCD panel140, the timing controller110adjusts output states of the scan signals SC or the pixel voltages VP to reduce energy written into the LCD panel140, so as to avoid the frame flicking phenomenon occurred when the LCD panel140displays the brighter second frame F2.

In the present embodiment, the gamma voltage generator150is controlled by the timing controller110to generate the gamma voltages VG. However, in other embodiments, the gamma voltage generator150can independently operate to generate the gamma voltages VG, and the invention is not limited thereto, i.e. the gamma voltage generator150is not necessarily coupled to the timing controller110.

FIG. 2is a timing schematic diagram of the polarity signal ofFIG. 1according to an embodiment of the invention. Referring toFIG. 1andFIG. 2, in the present embodiment, the timing controller110can determine whether the first frame F1is a dynamic frame according to the previous frames PF and the first frame F1. Further, when the previous frames PF and the first frame F1are different, the timing controller110determines the first frame F1to be the dynamic frame. Conversely, when two neighbouring frames of the first frame F1and the previous frames PF are the same, the timing controller110determines the first frame F1to be a static frame. In other words, when the timing controller110counts that N consecutive frames are different frames, it determines an Nth frame to be the dynamic frame. Conversely, the timing controller110determines the Nth frame to be the static frame, where N is a positive integer.

Similarly, whether the second frame F2is a dynamic frame can be determined according to the previous frames PF and the first frame F1. Moreover, in case that the first frame F1and the second frame F2are all dynamic frames, the timing controller110performs the polarity inversion on the polarity signal POL of the second frame F2to equalize the polarity signal POL corresponding to the first frame F1and the polarity signal POL corresponding to the second frame F2. In other words, when the timing controller110counts that the N consecutive frames are different frames, and an (N+1)th frame (corresponding to the second frame F2) is also different to the Nth frame (corresponding to the first frame F1), the timing controller110performs the polarity inversion on the polarity signal POL of the (N+1)th frame. Conversely, the timing controller110does not perform the polarity inversion on the polarity signal POL of the (N+1)th frame.

FIG. 3Ais a timing schematic diagram of output enable signals and scan signals ofFIG. 1according to an embodiment of the invention. Referring toFIG. 1andFIG. 3A, in the present embodiment, an output enable signal OE1and a scan signals SC1correspond to the first frame F1, and an output enable signal OE2and a scan signals SC2correspond to the second frame F2. According to the above descriptions, when the timing controller110performs the polarity inversion on the polarity signal POL of the second frame F2, the timing controller110adjusts the output states of the scan signals SC or the pixel voltages VP to reduce energy written into the LCD panel140.

In the present embodiment, a first method of reducing the energy written into the LCD panel140is to shorten pulse widths of the scan signals SC. Since the pulse widths of the scan signals SC determine a time for each of the pixels (not shown) of the LCD panel140receiving the pixel voltages VP, the pulse widths of the scan signals SC can determine a magnitude of energy received by the LCD panel140, i.e. the energy written into the LCD panel140can be reduced by shortening the pulse widths of the scan signals SC.

In the present embodiment, it is assumed that the pulse widths of the scan signals SC are controlled by pulse width of the output enable signal OE, as the pulse width of the output enable signal OE2output by the timing controller110in the second frame F2is smaller than the pulse width of the output enable signal OE1output in the first frame F1, the pulse widths of the scan signals SC2output by the gate driver120in the second frame F2is smaller than the pulse widths of the scan signals SC1output in the first frame F1, for example, the pulse widths of the scan signals SC2is 0.3 times of the pulse widths of the scan signals SC1. The pulse widths of the scan signal SC2can be determined according to a frame brightness difference of the first frame F1and the second frame F2, i.e. the greater the frame brightness difference is, the narrower the pulse width of each scan signal SC2is, and the smaller the frame brightness difference is, the wider the pulse width of each scan signal SC2is.

In another embodiment, the pulse widths of the scan signals SC can be controlled by a pulse width of the gate clock signal CPV, so that as the pulse width of the gate clock signal CPV output by the timing controller110in the second frame F2is smaller than the pulse width of the gate clock signal CPV output in the first frame F1, the pulse widths of the scan signals SC2output by the gate driver120in the second frame F2is smaller than the pulse widths of the scan signals SC1output in the first frame F1.

In another embodiment, the pulse widths of the scan signals SC can be simultaneously controlled by the pulse width of the output enable signal OE and the gate clock signal CPV, so that the pulse widths of the output enable signal OE2and the gate clock signal CPV output by the timing controller110in the second frame F2are both smaller than the pulse widths of the output enable signal OE1and the gate clock signal CPV output in the first frame F1.

Moreover, a frame rate of the LCD100is varied along with different regions, and the difference of the frame rates may influence a charging time of the LCD panel140, i.e. influence the pulse widths of the output enable signal OE and the gate clock signal CPV.FIG. 3Bis a schematic diagram of regulating the set of the LCD100according to an embodiment of the invention. Referring toFIG. 3B, generally, the frame rate of the LCD100is approximately 50 Hz or 60 Hz. Therefore, the pulse widths of the output enable signal OE2and the gate clock signal CPV output in the second frame F2can be adjusted to different pulse widths according to different frame rates, and a first frame rate threshold FA and a second frame rate threshold FB can be set to determine the adjusted pulse widths of the output enable signal OE2and the gate clock signal CPV. The first frame rate threshold FA is set to be greater than the second frame rate threshold FB, where the first frame rate threshold FA is, for example, 57 Hz, and the second frame rate threshold FB is, for example, 52 Hz. Moreover, the first frame rate threshold FA and the second frame rate threshold FB can be quite different to the frame rate to be determined, so as to avoid a boundary effect.

Further, when the frame rate of the LCD100is decreased to be smaller than the first frame rate threshold FA, the timing controller110sets the pulse width of the output enable signal OE2and/or the gate clock signal CPV output in the second frame F2to a larger pulse width (corresponding to a first pulse width P1). When the frame rate of the LCD100is increased to be greater than the second frame rate threshold FB, the timing controller110sets the pulse width of the output enable signal OE2and/or the gate clock signal CPV output in the second frame F2to a smaller pulse width (corresponding to a second pulse width P2).

Moreover, when the LCD100initially operates, a working temperature thereof is increased from a lower working temperature to a higher working temperature along with time, and the difference of the working temperatures may influence a rotation speed of the liquid crystal of the LCD panel140, i.e. influence a flicking degree caused by displaying of the second frame F2.FIG. 3Cis a schematic diagram of regulating the set of the LCD100according to another embodiment of the invention. Referring toFIG. 3C, generally, the working temperature of the LCD100is increased from the lower working temperature of an initial operation state to the higher working temperature of a normal operation state. Therefore, the pulse width of the output enable signal OE2and/or the gate clock signal CPV output in the second frame F2is adjusted to different pulse widths according to the lower working temperature and the higher working temperature of the LCD100, and a first temperature threshold TA and a second temperature threshold TB can be set to determine the pulse widths of the output enable signal OE2and the gate clock signal CPV. The first temperature threshold TA and the second temperature threshold TB are between the aforementioned lower working temperature and the higher working temperature, and the first temperature threshold TA is greater than the second temperature threshold TB. Moreover, the first temperature threshold TA and the second temperature threshold TB can be quite different to the working temperature to be determined, so as to avoid the boundary effect.

Further, when the working temperature of the LCD100is decreased to be smaller than the first temperature threshold TA, the timing controller110sets the pulse width of the output enable signal OE2and/or the gate clock signal CPV output in the second frame F2to a larger pulse width (corresponding to a third pulse width P3). When the working temperature of the LCD100is increased to be greater than the second temperature threshold TB, the timing controller110sets the pulse width of the output enable signal OE2and/or the gate clock signal CPV output in the second frame F2to a smaller pulse width (corresponding to a fourth pulse width P4).

Moreover, in some embodiments, the LCD100can set the pulse widths of the output enable signal OE2and the gate clock signal CPV output in the second frame F2according to both of the frame rate and the working temperature.

FIG. 4is a timing schematic diagram of the scan signals and the latch signals ofFIG. 1according to an embodiment of the invention. Referring toFIG. 1andFIG. 4, in the present embodiment, a latch signal TP1corresponds to the first frame F1, and a latch signal TP2corresponds to the second frame F2. According to the above descriptions, when the timing controller110performs the polarity inversion on the polarity signal POL corresponding to the second frame F2, the timing controller110adjusts the output states of the scan signals SC or the pixel voltages VP to reduce the energy written into the LCD panel140.

In the present embodiment, a second method of reducing the energy written into the LCD panel140is to delay the latch signal TP output to the source driver130. Since the source driver130is controlled by the latch signal TP to receive the display data DD, a timing of the latch signal TP influences the output time of the pixel voltages VP. Namely, by delaying the latch signal TP output to the source driver130, the output time of the pixel voltages VP can be shortened, so as to reduce the energy written into the LCD panel140. In other words, when the timing controller110writes the second frame F2into the LCD panel140, it delays the latch signal TP by a delay time D for outputting, for example, the delay time D between the latch signals TP1and TP2shown inFIG. 4. The delay time D can be determined according to the frame brightness difference of the first frame F1and the second frame F2, i.e. the greater the frame brightness difference is, the longer the delay time D is, and the smaller the frame brightness difference is, the shorter the delay time D is.

Moreover, since the difference of the frame rates influences the charging time of the LCD panel140, the first frame rate threshold and the second frame rate threshold can be set to determine the delay time D of the latch signal TP2. Further, when the frame rate of the LCD100is decreased to be smaller than the first frame rate threshold, the timing controller110sets the delay time D of the latch signal TP2output in the second frame F2to a larger delay time (corresponding to a first delay time). When the frame rate of the LCD100is increased to be greater than the second frame rate threshold, the timing controller110sets the delay time D of the latch signal TP2output in the second frame F2to a smaller delay time (corresponding to a second delay time).

Moreover, since the difference of the working temperatures of the LCD100may influence the rotation speed of the liquid crystal of the LCD panel140, the first temperature threshold and the second temperature threshold can be set to determine the delay time D of the latch signal TP2. Further, when the working temperature of the LCD100is decreased to be smaller than the first temperature threshold, the timing controller110sets the delay time D of the latch signal TP2output in the second frame F2to a smaller delay time (corresponding to a third delay time). When the working temperature of the LCD100is increased to be greater than the second frame rate threshold, the timing controller110sets the delay time D of the latch signal TP2output in the second frame F2to a larger delay time (corresponding to a fourth delay time).

Moreover, in some embodiments, the LCD100can set the delay time D of the latch signal TP2output in the second frame F2according to both of the frame rate and the working temperature.

Referring toFIG. 1, in the present embodiment, a third method of reducing the energy written into the LCD panel140is to reduce gray values corresponding to the pixel voltages VP output to the LCD panel140. Since the pixel voltages VP determine brightness (i.e. the gray values) displayed by the pixels (not shown) of the LCD panel140, the energy written into the LCD panel140can be reduced by reducing the gray values corresponding to the pixel voltages VP output to the LCD panel140.

According to the above descriptions, when the timing controller110writes the second frame F2into the LCD panel140, the timing controller110can reduce the gray value corresponding to the display data DD. Namely, assuming an original gray value corresponding to the display data DD is100, when the timing controller110writes the second frame F2into the LCD panel140, the timing controller110can reduce the gray value corresponding to the display data DD to99. Alternatively, when the timing controller110writes the second frame F2into the LCD panel140, the timing controller110can reduce a voltage level of the gamma voltage VG corresponding to each of the gray values. Namely, assuming the gamma voltage VG corresponding to the gray value100is 8 volts, when the timing controller110writes the second frame F2, the timing controller110can reduce the gamma voltage VG corresponding to the gray value100to 7.9 volts. An adjustment amplitude of the gray value corresponding to the display data DD and an adjustment amplitude of the gamma voltage VG corresponding to each of the gray values are determined by the frame brightness difference of the first frame F1and the second frame F2, i.e. the greater the frame brightness difference is, the greater the adjustment amplitude is, and the smaller the frame brightness difference is, the smaller the adjustment amplitude is.

Moreover, since the difference of the frame rates influences the charging time of the LCD panel140, the first frame rate threshold and the second frame rate threshold can be set to determine the reduced gray value of the display data DD and the reduced voltage of the gamma voltage VG. Further, when the frame rate of the LCD100is decreased to be smaller than the first frame rate threshold, the timing controller110sets a higher reduced gray value (corresponding to a first gray value) of the display data DD corresponding to the second frame F2or a higher reduced voltage of the gamma voltage VG, i.e. sets a higher reduced gray value (corresponding to the first gray value) of the pixel voltage VP. When the frame rate of the LCD100is increased to be greater than the second frame rate threshold, the timing controller110sets a lower reduced gray value of the display data DD corresponding to the second frame F2or a lower reduced voltage of the gamma voltage VG, i.e. sets a lower reduced gray value (corresponding to a second gray value) of the pixel voltage VP.

Moreover, since the difference of the working temperatures of the LCD100may influence the rotation speed of the liquid crystal of the LCD panel140, the first temperature threshold and the second temperature threshold can be set to determine the reduced gray value of the display data DD and the reduced voltage of the gamma voltage VG. Further, when the working temperature of the LCD100is decreased to be smaller than the first temperature threshold, the timing controller110sets a lower reduced gray value (corresponding to a third gray value) of the display data DD corresponding to the second frame F2or a lower reduced voltage of the gamma voltage VG. When the working temperature of the LCD100is increased to be greater than the second frame rate threshold, the timing controller110sets a higher reduced gray value (corresponding to a fourth gray value) of the display data DD corresponding to the second frame F2or a higher reduced voltage of the gamma voltage VG.

Moreover, in some embodiments, the LCD100can set the reduced gray value of the display data DD corresponding to the second frame F2or the reduced voltage of the gamma voltage VG according to both of the frame rate and the working temperature.

FIG. 5is a flowchart illustrating a method for operating an LCD according to an embodiment of the invention. Referring toFIG. 5, in the present embodiment, the method for operating the LCD includes following steps. It is determined whether a first frame and a second frame following the first frame are dynamic frames (step S510). When the first frame and the second frame are the dynamic frames, i.e. when a determination result of the step S510is “yes”, a timing controller of the LCD performs a polarity inversion on a polarity signal to equalize the polarity signal corresponding to the first frame with the polarity signal corresponding to the second frame (step S520). When the second frame is written into an LCD panel of the LCD, energy written into the LCD panel is reduced (step S530). When one of the first frame and the second frame is a static frame, i.e. when the determination result of the step S510is “no”, it is stopped performing the polarity inversion on the polarity signal. Details of the above steps can refer to related descriptions of the embodiments ofFIG. 1-FIG.4, which are not repeated.

In summary, in the LCD and the method for operating the same, when the first frame and the second frame are all dynamic frames, the timing controller performs the polarity inversion on the polarity signal to equalize the polarity signal corresponding to the first frame with the polarity signal corresponding to the second frame, so as to reduce a chance of liquid crystal polarization of the LCD panel. Now, the timing controller controls the source driver and/or the gate driver to reduce the energy written into the LCD panel, so as so avoid a frame flicking phenomenon occurred when the LCD panel displays the brighter second frame.