Inverter circuit and balanced input inverter circuit

A balanced input inverter circuit includes a first P-type MOS transistor including a gate terminal connected to an input, a source terminal connected to a first power source potential, and a drain terminal connected to an output, a first N-type MOS transistor including a gate terminal connected to the input, a drain terminal connected to the output, and a source terminal connected to a second power source potential, a first inverter circuit including an input terminal connected to an inverted input, and an output terminal connected to a back gate terminal of the first N-type MOS transistor, a first diode connected between the first power source potential and a first power source terminal of the first inverter circuit, a second inverter circuit including an input terminal connected to the inverted input, and an output terminal connected to a back gate terminal of the first P-type MOS transistor, and a second diode connected between the second power source potential and a second power source terminal of the second inverter circuit.

FIELD

The embodiments discussed herein are directed to an inverter circuit and a balanced input inverter circuit.

BACKGROUND

Recently, semiconductor products using a metal oxide semiconductor (MOS) transistor and the like are required to achieve a high speed operation and low power consumption at the same time. To achieve a high speed operation, it is preferable to increase a driving current of a transistor. However, when a power source voltage is increased to increase the driving current, the power consumption also increases, and this is against achieving low power consumption. Further, when a space taken by a transistor is enlarged to increase the driving current, the entire area of a circuit increases, and this makes it difficult to achieve downsizing of a semiconductor product.

On the other hand, to increase a driving current of a MOS transistor, it is effective to reduce a threshold voltage between a gate terminal and a source terminal. For this purpose, it is effective to adjust a back gate voltage as a voltage of a substrate of the MOS transistor, and reduce the threshold voltage by a substrate bias effect. For example, Japanese Patent No. 3039336 describes a technique of applying a voltage shifted from a power source as a back gate voltage of a MOS transistor, and reducing a threshold voltage when the MOS transistor is in an operating state.

In a circuit described in Japanese Patent No. 3039336, as depicted inFIG. 21, diodes30and40are provided between a power source potential and back gate terminals of transistors10and20, respectively. With this arrangement, in an operating state of the MOS transistor10, a forward current flows to the diode30, and a back gate voltage of the MOS transistor10is shifted from a power source voltage (a positive power source Vdd). Consequently, a threshold voltage of the MOS transistor10is reduced and a driving current increases. In an operating state of the MOS transistor20, a forward current flows to the diode40, and a back gate voltage of the MOS transistor20is shifted from a power source voltage (a negative power source Vss). Consequently, a threshold voltage of the MOS transistor20is reduced and a driving current increases.

However, to increase the driving current as described above, a leak current also increases along with the increase of the driving current. That is, when a space taken by a transistor is increased, an element size increases, and this can be a cause of the increase of the leak current.

The leak current also increases when a threshold voltage is reduced by shifting a back gate voltage. Specifically, when a relationship between a gate voltage VG and a current IDS between a drain terminal and a source terminal depicted inFIG. 22is referred to, for example, it is clear that when a back gate voltage indicated by a solid line inFIG. 22is low, a driving current is small and a leak current is also small. When a back gate voltage indicated by a broken line inFIG. 22is at a medium level, a driving current and a leak current are also at medium levels. When a back gate voltage indicated by a dashed line inFIG. 22is high, a driving current becomes large, but a leak current also becomes large. Particularly, inFIG. 22, because the current IDS is expressed in a logarithmic scale, it is clear that the increase of the leak current along with the increase of the back gate voltage is very large.

As described above, when the back gate voltage is fixedly shifted, a leak current increases as well as a driving current. Therefore, there is a certain limit to improve the driving capacity by reducing the threshold voltage. To dynamically control the back gate voltage, there can be considered a circuit configuration that applies a voltage equal to a gate input voltage of a MOS transistor to a back gate terminal. In this case, however, a forward voltage is generated between the source terminal and the back gate terminal and a current is also generated, and thus it is not realistic to apply the gate input voltage to the back gate terminal.

SUMMARY

According to one aspect of the invention, a balanced input inverter circuit includes: a first P-type MOS transistor including a gate terminal connected to an input, a source terminal connected to a first power source potential, and a drain terminal connected to an output; a first N-type MOS transistor including a gate terminal connected to the input, a drain terminal connected to the output, and a source terminal connected to a second power source potential; a first inverter circuit including an input terminal connected to an inverted input, and an output terminal connected to a back gate terminal of the first N-type MOS transistor; a first diode connected between the first power source potential and a first power source terminal of the first inverter circuit; a second inverter circuit including an input terminal connected to the inverted input, and an output terminal connected to a back gate terminal of the first P-type MOS transistor; and a second diode connected between the second power source potential and a second power source terminal of the second inverter circuit.

According to another aspect of the invention, an inverter circuit includes: a first transistor including a gate terminal connected to an input, a source terminal connected to a first power source potential, and a drain terminal connected to an output; a second transistor having a polarity different from that of the first transistor and including a gate terminal connected to the input, a drain terminal connected to the output, and a source terminal connected to a second power source potential; a first diode connected between a back gate terminal of the first transistor and a back gate terminal of the second transistor; a third transistor including a gate terminal connected to an inverted input, a source terminal connected to the first power source potential, a drain terminal connected to the back gate terminal of the first transistor, and a back gate terminal connected to the first power source potential; and a fourth transistor including a gate terminal connected to the inverted input, a drain terminal connected to a back gate terminal of the second transistor, a source terminal connected to the second power source potential, and a back gate terminal connected to the second power source potential.

According to still another aspect of the invention, an inverter circuit includes: a first transistor including a gate terminal connected to an input, a source terminal connected to a first power source potential, and a drain terminal connected to an output; a second transistor having a polarity different from that of the first transistor and including a gate terminal connected to the input, a drain terminal connected to the output, and a source terminal connected to a second power source potential; a first diode connected between a back gate terminal of the first transistor and a back gate terminal of the second transistor; a third transistor including a gate terminal connected to an inverted input, a source terminal connected to a third power source potential which is higher than the first power source potential, a drain terminal connected to the back gate terminal of the first transistor, and a back gate terminal connected to the third power source potential; and a fourth transistor including a gate terminal connected to the inverted input, a drain terminal connected to a back gate terminal of the second transistor, a source terminal connected to a fourth power source potential which is lower than the second power source potential, and a back gate terminal connected to the fourth power source potential.

DESCRIPTION OF EMBODIMENTS

Exemplary embodiments of the present invention will be explained below in detail with reference to the accompanying drawings.

[a] First Embodiment

FIG. 1is a circuit diagram of a configuration of an inverter circuit according to a first embodiment of the present invention. The inverter circuit depicted inFIG. 1includes a P-type MOS transistor (hereinafter, “P-type MOS”)101, an N-type MOS transistor (hereinafter, “N-type MOS”)102, a diode103, and a diode104.FIG. 2is a schematic diagram of a cross-sectional configuration of the inverter circuit depicted inFIG. 1.

In the P-type MOS101, a gate terminal (denoted as “G” inFIG. 2) is connected to an input terminal, a source terminal (denoted as “S” inFIG. 2) is connected to the positive power source potential Vdd, and a drain terminal (denoted as “D” inFIG. 2) is connected to an output terminal and to a drain terminal of the N-type MOS102. A back gate terminal of the P-type MOS101(denoted as “P-BG” inFIG. 2) is connected to an anode side (denoted as “A” inFIG. 2) of the diode103. The P-type MOS101becomes an operating state when an input voltage Vin applied to the gate terminal is L (low), and passes a current from the source terminal to the drain terminal, and sets an output voltage Vout from the output terminal to H (high).

In the N-type MOS102, a gate terminal is connected to the input terminal, a source terminal is connected to the negative power source potential Vss, and a drain terminal is connected to the output terminal and to the drain terminal of the P-type MOS101. A back gate terminal of the N-type MOS102is connected to a cathode side (denoted as “K” inFIG. 2) of the diode104. The N-type MOS102becomes an operating state when the input voltage Vin applied to the gate terminal is H (high), and passes a current from the drain terminal to the source terminal, and sets the output voltage Vout from the output terminal to L (low).

The diode103becomes an on-state when the P-type MOS101is in an operating state, and sets a voltage at an anode side to a voltage higher than the input voltage Vin. Therefore, based on the diode103, a back gate voltage of the P-type MOS101becomes lower than the source voltage, and an absolute value of the threshold voltage becomes small. As a result, when the P-type MOS101is in an operating state, a driving current can be increased. The diode103becomes an off-state when the P-type MOS101is in a non-operating state. Therefore, when the P-type MOS101is in a non-operating state, a leak current can be suppressed without reducing the absolute value of the threshold voltage.

The diode104becomes an on-state when the N-type MOS102is in an operating state, and sets a voltage at a cathode side to a voltage lower than the input voltage Vin. Therefore, based on the diode104, a back gate voltage of the N-type MOS102becomes higher than the source voltage, and an absolute value of the threshold voltage becomes small. As a result, when the N-type MOS102is in an operating state, a driving current can be increased. The diode104becomes an off-state when the N-type MOS102is in a non-operating state. Therefore, when the N-type MOS102is in a non-operating state, a leak current can be suppressed without reducing the absolute value of the threshold voltage.

FIG. 3is a schematic diagram for explaining an operation of the inverter circuit according to the first embodiment. InFIG. 3, the P-type MOS101is in an operating state.

When the P-type MOS101is in an operating state, that is, when the input voltage Vin is L (low), the diode103becomes an on-state, and the back gate voltage of the P-type MOS101becomes a voltage having a threshold voltage Vth (Dp) of the diode103added to the input voltage Vin. When the following equation (1) is satisfied, the absolute value of the threshold voltage of the P-type MOS101becomes small, and the driving current increases, without passing a current from the source terminal to the back gate terminal.
Vin+Vth(Dp)>Vdd−Vth(S−BG)  (1)

In the equation (1), as depicted inFIG. 3, Vth(S−BG) denotes a voltage between the source terminal and the back gate terminal.

Similarly, when the N-type MOS102is in an operating state, that is, when the input voltage Vin is H (high), the diode104becomes an on-state, and the back gate voltage of the N-type MOS102becomes equal to or smaller than a voltage having a threshold voltage Vth (Dn) of the diode104subtracted from the input voltage Vin. When the following equation (2) is satisfied, the absolute value of the threshold voltage of the N-type MOS102becomes small, and the driving current increases, without passing a current from the back gate terminal to the source terminal.
Vin−Vth(Dn)<Vth(S−BG)+Vss(2)

As explained above, according to the first embodiment, the diode103and the diode104shift the back gate voltages of the P-type MOS101and the N-type MOS102corresponding to the input voltages Vin. Therefore, the driving currents of the P-type MOS101and the N-type MOS102can be increased without generating a current between the source terminal and the back gate terminal.

[b] Second Embodiment

According to a second embodiment of the present invention, a MOS transistor is connected to a diode, whereby a back gate voltage of a MOS transistor in a non-operating state is controlled to stabilize the operation.

FIG. 4is a circuit diagram of a configuration of an inverter circuit according to the second embodiment. InFIG. 4, like parts as those inFIG. 1are denoted by like reference numerals and explanations thereof will not be repeated. The inverter circuit depicted inFIG. 4includes the P-type MOS101, the N-type MOS102, the diode103, the diode104, an N-type MOS201, and a P-type MOS202.

In the N-type MOS201, a gate terminal is connected to an input terminal, a source terminal is connected to a back gate terminal of the P-type MOS101, and a drain terminal is connected to the positive power source potential Vdd. A back gate terminal of the N-type MOS201is connected to the negative power source potential Vss. The N-type MOS201becomes an operating state when the input voltage Vin applied to the gate terminal is H (high), and passes a current from the drain terminal to the source terminal, and sets the back gate voltage of the P-type MOS101equal to Vdd. That is, when the P-type MOS101is in a non-operating state, the N-type MOS201sets the source voltage and back gate voltage of the P-type MOS101equal.

In the P-type MOS202, a gate terminal is connected to the input terminal, a source terminal is connected to a back gate terminal of the N-type MOS102, and a drain terminal is connected to the negative power source potential Vss. A back gate terminal of the P-type MOS202is connected to the positive power source potential Vdd. The P-type MOS202becomes an operating state when the input voltage Vin applied to the gate terminal is L (low), and passes a current from the source terminal to the drain terminal, and sets the back gate voltage of the N-type MOS102equal to Vss. That is, when the N-type MOS102is in a non-operating state, the P-type MOS202sets the source voltage and back gate voltage of the N-type MOS102equal.

In the second embodiment, the N-type MOS201and the P-type MOS202are added to the circuit of the first embodiment. In the circuit (FIG. 1) of the first embodiment, the diode103and the diode104are provided. With this arrangement, when the P-type MOS101and the N-type MOS102corresponding to these diodes are in an operating state, the driving current can be increased. However, in the first embodiment, when the P-type MOS101and the N-type MOS102are in a non-operating state, the back gate terminals of the respective MOS transistors become a floating state that power is not supplied, and the operation becomes unstable.

Therefore, in the second embodiment, the N-type MOS201and the P-type MOS202are connected to the diode103and the diode104, respectively. When the diode103is in an off-state, the N-type MOS201supplies positive power to the back gate terminal of the P-type MOS101. When the diode104is in an off-state, the P-type MOS202supplies negative power to the back gate terminal of the N-type MOS102.

With this arrangement, when the P-type MOS101and the N-type MOS102are in a non-operating state, the back gate voltage becomes equal to the source voltage, and the circuit operation becomes stable. Further, a threshold voltage in a non-operating state of the P-type MOS101and the N-type MOS102becomes large, and a leak current can be reduced to a state before the driving capacity is improved.

FIG. 5depicts a relationship between the input voltage Vin and an output current Iout output from the output terminal, for the inverter circuit (a solid line) according to the second embodiment and a conventional inverter circuit (a broken line). As depicted inFIG. 5, along with the increase of the input voltage Vin from 0 to 1, the output current Iout is reduced. In the inverter circuit expressed by the solid line inFIG. 5, an absolute value of the output current Iout is larger than that in the conventional inverter circuit expressed by the broken line inFIG. 5. That is, when the input voltage Vin is 0, for example, the output current Iout is in a positive value, and the output current Iout is larger in the inverter circuit according to the second embodiment expressed by the solid line. When the input voltage Vin is 1, the output current Iout is in a negative value, and the output current Iout in the inverter circuit according to the second embodiment expressed by the solid line is smaller. This indicates that the inverter circuit of the second embodiment can obtain a larger driving current than the conventional inverter circuit.

Various variations are considered for the inverter circuit according to the second embodiment. First, as depicted inFIG. 6, a differential-input-voltage Vin bar can be input instead of the input voltage Vin, to the gate terminals of the N-type MOS201and the P-type MOS202. InFIG. 6, because the differential-input-voltage Vin bar having the input voltage Vin inverted is applied to the gate terminals of the N-type MOS201and the P-type MOS202, a positional relationship between the N-type MOS201and the P-type MOS202can be reversed from that in the circuit configuration depicted inFIG. 4. As a result, in the circuit configuration depicted inFIG. 6, P-type MOS transistors (the P-type MOS101and the P-type MOS202) can be arranged at an upper part of the diagram, and N-type MOS transistors (the N-type MOS102and the N-type MOS201) can be arranged at a lower part of the diagram, thereby improving the usability of the circuit.

Next, as depicted inFIG. 7, the positive power source potential and the negative power source potential connected to the drain terminals of the N-type MOS201and the P-type MOS202can be set deeper than the positive power source potential Vdd and the negative power source potential Vss, respectively. That is, the positive power source potential connected to the drain terminal of the N-type MOS201can be set larger than the positive power source potential Vdd, and the negative power source potential connected to the drain terminal of the P-type MOS202can be set smaller than the negative power source potential Vss. With this arrangement, the threshold voltage when the P-type MOS101and the N-type MOS102are in a non-operating state can be larger, whereby the leak current can be suppressed more securely.

Further, as depicted inFIG. 8, the back gate voltages of the N-type MOS201and the P-type MOS202can be obtained from the back gate voltages of the P-type MOS101and the N-type MOS102, respectively. With this arrangement, a timing when the N-type MOS201and the P-type MOS202become an operating state can be changed, thereby controlling a timing of matching the source voltage and the back gate voltage of the P-type MOS101and the N-type MOS102.

FIG. 9depicts characteristics of the input voltage Vin and a back gate voltage Vbg in the P-type MOS101of the inverter circuit (FIG. 1) according to the first embodiment, and the inverter circuits (FIGS. 4,6,7, and8) according to the second embodiment. InFIG. 9, application of the input voltage Vin to the back gate terminal is expressed by a broken line. As is clear fromFIG. 9, in all inverter circuits depicted inFIGS. 1,4,6,7, and8, in a state that the input voltage Vin is low, the back gate voltage Vbg is larger than the input voltage Vin. That is, it is clear that in the P-type MOS101, when the input voltage Vin is L (low), the threshold voltage becomes high, and the driving voltage increases.

In a state that the input voltage Vin is small, characteristics of all inverter circuits do not belong to a back-gate leak region where a leak current to the back gate terminal is large, but belong to an intermediate region where a driving current is large and some current is leaked to the back gate terminal, or belong to an output-current increase region where a driving current is large. When the input voltage Vin becomes larger, it is clear that, in the characteristics of all inverter circuits, the back gate voltage becomes close to a constant value (1V), and the leak current becomes similar to that of the conventional inverter circuit. However, in the circuit depicted inFIG. 7, because the positive power source potential connected to the drain terminal of the N-type MOS201is set larger, the back gate voltage of the P-type MOS101becomes larger, and the leak current is further reduced than normal.

As explained above, according to the second embodiment, MOS transistors are provided between the back gate terminals of the P-type MOS101and the N-type MOS102and the positive power source and the negative power source, respectively. Therefore, when the P-type MOS101and the N-type MOS102are in a non-operating state, respectively, the source voltage and the back gate voltage match each other, and the operation of the inverter circuit can be stabilized.

According to a third embodiment of the present invention, a current flowing through a diode is led to a positive power source or a negative power source. With this arrangement, the current flowing through the diode is prevented from flowing to the input terminal.

In the inverter circuits according to the first and second embodiments, the cathode side of the diode103is connected to the input terminal. Therefore, when the diode103becomes an on-state, a current flows to the input terminal. Accordingly, this has a risk of putting a burden on a pre-stage circuit of the inverter circuit. In the third embodiment, a transistor functions as a diode, and a current flowing through the diode is not led to the input terminal, based on switching performed by MOS transistors.

FIG. 10is a circuit diagram of a configuration of an inverter circuit according to the third embodiment. InFIG. 10, like parts as those inFIGS. 1 and 4are denoted by like reference numerals and explanations thereof will not be repeated. The inverter circuit depicted inFIG. 10includes the P-type MOS101, the N-type MOS102, the N-type MOS201, the P-type MOS202, a diode301, an N-type MOS302, a P-type MOS303, and a diode304.

The diode301includes an N-type MOS. A gate terminal is connected to the positive power source potential Vdd. A source terminal is connected to a drain terminal of the N-type MOS302. A drain terminal is connected to the positive power source potential Vdd. A back gate terminal is connected to the negative power source potential Vss. The diode301works to set a voltage of a drain terminal of the N-type MOS302to a voltage lower than the positive power source potential Vdd. That is, the diode301has a function equivalent to that of the diodes104according to the first and second embodiments.

In the N-type MOS302, a gate terminal is connected to an input terminal. A source terminal is connected to the back gate terminal of the N-type MOS102. A drain terminal of the N-type MOS302is connected to the source terminal of the diode301. A back gate terminal of the N-type MOS302is connected to the negative power source potential Vss. Therefore, the N-type MOS302and the P-type MOS202have configurations similar to that of a buffer circuit that passes the input voltage Vin as it is.

The N-type MOS302becomes an operating state when the input voltage Vin is H (high), and functions as a switch that connects between the diode301and the back gate terminal of the N-type MOS102. On the other hand, the N-type MOS302becomes a non-operating state when the input voltage Vin is L (low). The diode301does not apply a voltage reduced from the positive power source potential Vdd to the back gate terminal of the N-type MOS102.

In the P-type MOS303, a gate terminal is connected to an input terminal. A source terminal of the P-type MOS303is connected to the back gate terminal of the P-type MOS101. A drain terminal is connected to a source terminal of the diode304. A back gate terminal of the P-type MOS303is connected to the positive power source potential Vdd. Therefore, the P-type MOS303and the N-type MOS201have configurations similar to that of a buffer circuit that passes the input voltage Vin as it is.

The P-type MOS303becomes an operating state when the input voltage Vin is L (low), and functions as a switch that connects between the diode304and the back gate terminal of the P-type MOS101. On the other hand, the P-type MOS303becomes a non-operating state when the input voltage Vin is H (high). The diode304does not apply a voltage increased from the negative power source potential Vss to the back gate terminal of the P-type MOS101.

The diode304includes a P-type MOS. A gate terminal is connected to the negative power source potential Vss. A source terminal is connected to the drain terminal of the P-type MOS303. A drain terminal is connected to the negative power source potential Vss. A back gate terminal is connected to the positive power source potential Vdd. The diode304works to set a voltage of the drain terminal of the P-type MOS303to a voltage higher than the negative power source potential Vss. That is, the diode304has a function equivalent to that of the diodes103according to the first and second embodiments.

In the third embodiment, based on switching performed using the N-type MOS302and the P-type MOS303, whether to apply voltages from the diode301and the diode304to the back gate terminals of the N-type MOS102and the P-type MOS101is switched. Further, it is also obviously possible to use an analog switch that operates in a similar manner to the N-type MOS302and the P-type MOS303. It is also possible to replace the N-type MOS201and the P-type MOS202with a circuit that performs switching.

It is also possible to use a toggle switch or the like that connects the back gate terminal of the P-type MOS101to any one of the N-type MOS201and the P-type MOS303by switching. Similarly, it is also possible to use a toggle switch that connects the back gate terminal of the N-type MOS102to any one of the P-type MOS202and the N-type MOS302by switching.

In the third embodiment, when the input voltage Vin is L (low), the P-type MOS101, the P-type MOS202, the P-type MOS303, and the diode304become an operating state. Because the diode304and the P-type MOS303become an operating state, the back gate voltage of the P-type MOS101becomes a voltage larger than the negative power source potential Vss by a threshold voltage of the diode304. Accordingly, a leak current from the source terminal of the P-type MOS101to the back gate terminal can be suppressed, and the driving current can be increased. Further, because the P-type MOS202becomes an operating state, the source voltage and the back gate voltage of the N-type MOS102match the negative power source potential Vss in a similar manner to that of the second embodiment, and the operation becomes stable.

On the other hand, when the input voltage Vin is H (high), the N-type MOS102, the N-type MOS201, the diode301, and the N-type MOS302become an operating state. Further, because the diode301and the N-type MOS302become an operating state, the back gate voltage of the N-type MOS102becomes a voltage smaller than the positive power source potential Vdd by a threshold voltage of the diode301. Accordingly, a leak current from the source terminal of the N-type MOS102to the back gate terminal can be suppressed, and the driving current can be increased. Because the N-type MOS201becomes an operating state, the source voltage and the back gate voltage of the P-type MOS101match the positive power source potential Vdd in a similar manner to that of the second embodiment, and the operation becomes stable.

In the inverter circuit according to the third embodiment, the input terminal is connected to only the gate terminals of the MOS transistors, and a current does not flow from the diode and the like into the input terminal. Therefore, the driving current is not wastefully consumed and a high speed operation can be performed.

Various variations are considered for the inverter circuit according to the third embodiment, in a similar manner to that of the second embodiment. Firstly, as depicted inFIG. 11, the differential-input-voltage Vin bar can be input instead of the input voltage Vin, to the gate terminals of the N-type MOS201and the P-type MOS202. InFIG. 11, because the differential-input-voltage Vin bar having the input voltage Vin inverted is applied to the gate terminals of the N-type MOS201and the P-type MOS202, a positional relationship between the N-type MOS201and the P-type MOS202can be reversed from that in the circuit configuration depicted inFIG. 10. Following this, the positional relationship among the diode301, the N-type MOS302, the P-type MOS303, and the diode304can be reversed. As a result, in the circuit configuration depicted inFIG. 11, P-type MOS transistors (the P-type MOS101, the P-type MOS202, the P-type MOS303, and the diode304) can be arranged at an upper part of the diagram, and N-type MOS transistors (the N-type MOS102, the N-type MOS201, the diode301, and the N-type MOS302) can be arranged at a lower part of the diagram, thereby improving the usability of the circuit.

Next, as depicted inFIG. 12, the positive power source potential and the negative power source potential connected to the drain terminals of the N-type MOS201and the P-type MOS202can be set deeper than the positive power source potential Vdd and the negative power source potential Vss, respectively. That is, the positive power source potential connected to the drain terminal of the N-type MOS201can be set larger than the positive power source potential Vdd, and the negative power source potential connected to the drain terminal of the P-type MOS202can be set smaller than the negative power source potential Vss. With this arrangement, the threshold voltage when the P-type MOS101and the N-type MOS102are in a non-operating state can be larger, whereby the leak current can be suppressed more securely.

As explained above, according to the third embodiment, the P-type MOS transistors and the N-type MOS transistors are used to provide a circuit configuration in which a current to adjust the back gate voltages of the P-type MOS101and the N-type MOS102does not flow into the input terminal. Therefore, the driving current is not wastefully consumed and a high speed operation can be performed.

Transistors having configurations as depicted inFIG. 13toFIG. 17can be also used for the diode301and the diode304according to the third embodiment. InFIG. 13toFIG. 17, an anode side of the diode is denoted by “A”, and a cathode side is denoted by “K”.FIG. 13depicts a PNP (Positive-Negative-Positive) transistor. When this transistor is used as the diode301, an emitter terminal becomes the anode side, and a base terminal becomes the cathode side. A collector terminal is connected to the negative power source potential Vss. Although illustrations are omitted, when an NPN (Negative-Positive-Negative) transistor is used as the diode304, a base terminal becomes the anode side, and an emitter terminal becomes the cathode side. The collector terminal is connected to the positive power source potential Vdd.

FIG. 14depicts a P-type MOS transistor, and this transistor is used as the diode304. In this case, a source terminal becomes the anode side. A gate terminal and a drain terminal are connected together at the cathode side. A back gate terminal of the P-type MOS transistor is connected to the positive power source potential Vdd.

FIG. 15depicts an N-type MOS transistor, and this transistor is used as the diode301. In this case, the gate terminal and the drain terminal are connected at the anode side. A source terminal becomes the cathode side, and a back gate terminal of the N-type MOS transistor is connected to the negative power source potential Vss.

FIG. 16depicts a P-type MOS junction transistor, and this transistor is used as the diode304. In this case, a back gate terminal of the P-type MOS junction transistor becomes the cathode side, and a drain terminal becomes the anode side. Similarly,FIG. 17depicts an N-type MOS junction transistor, and this transistor is used as the diode301. In this case, a back gate terminal of the N-type MOS junction transistor becomes the anode side, and a source terminal becomes the cathode side.

According to a fourth embodiment of the present invention, the arrangements of the MOS transistors functioning as a buffer circuit and a diode in the circuit in the third embodiment are replaced to have a large operation margin of the entire circuit.

FIG. 18is a circuit diagram of a configuration of an inverter circuit according to the fourth embodiment. InFIG. 18, like parts as those inFIGS. 1,4, and10are denoted by like reference numerals and explanations thereof will not be repeated. In the circuit depicted inFIG. 18, positions of the P-type MOS303and the diode304in the third embodiment depicted inFIG. 11are replaced with each other, and positions of the diode301and the N-type MOS302are replaced with each other. Other aspects are identical to those of the third embodiment, except that the operation margin becomes large based on the configuration of the circuit in the fourth embodiment.

InFIG. 18, the differential-input-voltage Vin bar is input to the gate terminals of the N-type MOS201and the P-type MOS202. However, the positional relationship between the N-type MOS and the P-type MOS can be reversed, and the input voltage Vin can be used, in a similar manner to that of the second and third embodiments. When the differential-input-voltage Vin bar is used, the N-type MOS transistor can be arranged at the negative power source potential Vss side, and the P-type MOS transistor can be arranged at the positive power source potential Vdd side in a similar manner to the third embodiment, thereby improving the usability of the circuit.

Further, as depicted inFIG. 19, a negative power source potential connected to the source terminal of the N-type MOS201can be set smaller than the negative power source potential Vss, and a positive power source potential connected to the source terminal of the P-type MOS202can be set larger than the positive power source potential Vdd. With this arrangement, a threshold voltage when the P-type MOS101and the N-type MOS102are in a non-operating state becomes larger, and a leak current can be more securely suppressed. InFIG. 19, the diode301and the diode304are denoted by circuit symbols of a diode instead of a MOS transistor.

Although illustrations are omitted, inFIG. 19, a negative power source potential connected to the source terminal of the N-type MOS302can be set smaller than the negative power source potential Vss, and a positive power source potential connected to the drain terminal of the P-type MOS303can be set larger than the positive power source potential Vdd. In this case, when the same negative power source potentials are connected to the source terminals of the N-type MOS201and the N-type MOS302, and also when the same positive power source potentials are connected to the drain terminals of the P-type MOS202and the P-type MOS303, the circuit configuration can be simplified.

According to a fifth embodiment of the present invention, one diode in the second embodiment is provided, thereby simplifying the circuit configuration.

FIG. 20is a circuit diagram of a configuration of an inverter circuit according to the fifth embodiment. InFIG. 20, like parts as those inFIGS. 1 and 4are denoted by like reference numerals and explanations thereof will not be repeated. The inverter circuit depicted inFIG. 20includes the P-type MOS101, the N-type MOS102, a diode401, the N-type MOS201, and the P-type MOS202.

When the P-type MOS101and the N-type MOS201are in an operating state, the diode401sets the back gate voltage of the P-type MOS101lower than the source voltage, and sets an absolute value of the threshold voltage small. When the N-type MOS102and the P-type MOS202are in an operating state, the diode401sets the back gate voltage of the N-type MOS102higher than the source voltage, and sets an absolute value of the threshold voltage small. As a result, a driving current can be increased when any one of the P-type MOS101and the N-type MOS102is in an operating state.

Also in the fifth embodiment, a leak current can be more securely suppressed by setting the positive power source potential and the negative power source potential connected by the P-type MOS202and the N-type MOS201to potentials deeper than Vdd and Vss, respectively. Further, instead of the differential-input-voltage Vin bar, the input voltage Vin can be directly applied to the gate terminals of the P-type MOS202and the N-type MOS201.

In the above embodiments, while driving currents of both the P-type MOS101and the N-type MOS102are increased, it is also possible to adjust a back gate voltage of only any one of the MOS transistors. Particularly, when the back gate voltage of only the P-type MOS transistor is adjusted, the entire driving current of the circuit can be effectively increased. In addition, the adjustment of a back gate voltage similar to the above can be used for various output driver circuits using MOS transistors as well as the inverter circuit.

According to one embodiment, the diode can shift the back gate voltage of a first transistor or a second transistor corresponding to the input voltage. Accordingly, the current between the source terminal and the back gate terminal can be suppressed, and a leak current can be suppressed while the driving current is increased.

According to one embodiment, corresponding diodes can shift the back gate voltages of a first transistor and a second transistor corresponding to the input voltages. Accordingly, the driving current of the entire circuit can be further increased.

According to one embodiment, an effect identical to that described above can be achieved by using a MOS transistor which can be easily integrated.

According to one embodiment, when a first transistor or a second transistor is in a non-operating state, the source voltage and the back gate voltage of the respective transistors can be set equal. Accordingly, the operation of the circuit can be stabilized.

According to one embodiment, the back gate voltage of the P-type MOS transistor can be set larger than the input voltage, and the back gate voltage of the N-type MOS transistor can be set smaller than the input voltage. Accordingly, a current between the source terminal and the back gate terminal can be securely suppressed.

According to one embodiment, a first diode and a second diode can adjust the back gate voltages of a first P-type MOS transistor and a first N-type MOS transistor. At the same time, there can be provided a circuit configuration in which the current flowing through the first diode and the second diode does not flow into the input. Accordingly, there is no waste in the driving current and a high speed operation can be performed.

According to one embodiment, a threshold voltage when a first P-type MOS transistor and a first N-type MOS transistor are in a non-operating state becomes larger. Accordingly, a leak current can be suppressed more securely.

According to one embodiment, when the MOS transistors are used for a first diode and a second diode, the N-type MOS transistor can be arranged at the negative power source potential Vss side, the P-type MOS transistor can be arranged at the positive power source potential Vdd side, and the P-type MOS transistors and the N-type MOS transistors of the same polarities can be arranged together. Accordingly, these MOS transistors can be operated based on the power source voltage, and the circuit can be used more conveniently.

According to one embodiment, various transistors can be used for a first diode and a second diode. Accordingly, an effect identical to that described above can be obtained in a flexible circuit configuration. Further, by flexibly using transistors having different threshold voltages, back gate voltages can be adjusted more minutely.

According to one embodiment, the back gate voltage of a first transistor or a second transistor can be shifted corresponding to the input voltage in a simple configuration of using only one diode. Accordingly, a current between the source terminal and the back gate terminal can be suppressed, and a leak current can be suppressed while increasing the driving current.

According to one embodiment, the driving current is increased, and a threshold voltage when a first P-type MOS transistor and a first N-type MOS transistor are in a non-operating state becomes larger. Accordingly, a leak current can be suppressed more securely.

According to one embodiment, a first diode and a second diode can adjust the back gate voltages of a first transistor and a second transistor. At the same time, there can be provided a circuit configuration in which the current flowing through the first diode and the second diode does not flow into the input. Accordingly, there is no waste in the driving current and a high speed operation can be performed.

According to one embodiment, the diode can shift the back gate voltage of a first transistor or a second transistor corresponding to the input voltage. Accordingly, the current between the source terminal and the back gate terminal can be suppressed, and a leak current can be suppressed while the driving current is increased.

According to the embodiments, a leak current can be suppressed while a driving current is increased.