System and method for responding to error detection

Systems and methods to respond to error detection are provided. A particular method may include issuing a first command to a first redrive device and a second command to a second redrive device. The method may also include reissuing the second command to the second redrive device in response to detecting a transmission error between a memory controller and the second redrive device. The method may further include storing at a first buffer first data that is received from the first redrive device in response to the first command. The method may include storing at a second buffer second data that is received from the second redrive device in response to the reissued second command. The method also may include merging the second data with the first data.

I. FIELD OF THE INVENTION

The present invention relates generally to data communication, and more specifically, to responding to error detection.

Successful storage and transmission of data may be impeded by errors in the data. A number of factors may cause data corruption. For example, a soft error may result from an unintentional bit flip caused by an alpha particle or noise. As another example, drift or skew due to temperature or voltage variations over time may create a hard error in the data.

Corrective action is usually initiated in response to a detection of the error. For instance, a memory controller may reissue a command after determining that a command was corrupted during transmission. In some instances, the memory controller may initiate a retrain of a link between the memory controller and a memory structure before reissuing the command to the memory structure via the link.

Corrective actions may limit the capability of the memory structure to perform some operations. For example, while retraining the link, the memory controller may be unable to use the link to transmit read and write commands to the memory structure. Reducing the amount of time that the memory controller performs corrective actions may increase the availability of the memory controller to perform normal operations. The increased availability translates into improved efficiency and reduced memory latency. It is therefore desirable to increase the ratio of time spent by the memory controller on normal operations versus corrective actions.

III. SUMMARY OF THE DISCLOSURE

In a particular embodiment, a method to respond to error detection is disclosed. The method includes issuing a first command to a first redrive device and a second command to a second redrive device. The method also includes reissuing the second command to the second redrive device in response to detecting a transmission error between a memory controller and the second redrive device. The method further includes storing at a first buffer first data that is received from the first redrive device in response to the first command. The method includes storing at a second buffer second data that is received from the second redrive device in response to the reissued second command. The method also includes merging the second data with the first data.

In another embodiment, a method to respond to error detection is disclosed. The method includes transmitting a constant pattern in response to initiation of a retrain of a link between a memory controller and a redrive device. The method also includes interrupting the transmission of the constant pattern after the constant pattern has been transmitted for a minimum duration to transmit a sequence of transitions. The method further includes resuming the transmission of the constant pattern after transmitting the sequence of transitions.

In another embodiment, a method to respond to error detection is disclosed. The method includes creating first scrub commands at a first scrub controller. The method also includes creating second scrub commands at a second scrub controller. The method further includes alternating issuance of the first scrub commands and the second scrub commands at a memory controller port.

These and other advantages and features that characterize the invention are set forth in the claims annexed hereto and forming a further part hereof. However, for a better understanding of the invention, and of the advantages and objectives attained through its use, reference should be made to the Drawings and to the accompanying descriptive matter in which there are described exemplary embodiments of the invention.

V. DETAILED DESCRIPTION

FIG. 1is a diagram of a first embodiment of a system to respond to error detection and is generally designated100. The system100includes a first redrive device104, a second redrive device106, and a memory controller102with a first buffer108and a second buffer110. The memory controller102and the first redrive device104may be connected via a first high speed link and the memory controller102and the second redrive device106are connected via a second high speed link. Each high speed link may refer to two unidirectional high speed links. For example, the memory controller102may transmit to the first redrive device104via a southbound link of the first high speed link and the first redrive device104may transmit to the memory controller102via a northbound link of the first high speed link.

Generally, the memory controller102may split a single command into two commands (e.g., a first command112and a second command114). The first command112may be transmitted to a first redrive device104, and the second command114may be transmitted to a second redrive device106. To complete the single command, both the first command112and the second command114may be executed. The memory controller102may receive good data (e.g., first data116) from the first redrive device104in response to transmission of the first command112and may detect a transmission error118between the memory controller102and the second redrive device106in response to transmission of the second command114. A response to the single command may not be complete without good data being received in response to both the first command112and the second command114. Instead of discarding the first data116and retransmitting both the first command112and the second command116, the memory controller102may store the good data (e.g., the first data116) received in response to the first command112. The memory controller102may reissue the second command114(e.g., reissued second command120) to the second redrive device106.

After receiving good data (second data122) in response to the reissued second command120, the memory controller may merge the first data116and the second data122to produce a synchronized complete data response to the single command. Reissuing only the second command114instead of both commands may prevent some errors. For instance, execution of the first command112may alter the data in a memory structure. Reissuance of the first command112may initiate the retrieval of the altered data in the memory structure instead of the initial data, as retrieved in the first data116.

Preservation of the first data116to merge with the second data122received in response to the reissued second command120may reduce the complexity of a corrective action that is performed. Reducing the complexity of the corrective action may reduce the amount of time dedicated to performing the corrective action and increase the amount of time that the memory controller is available to perform normal processes. Increasing the ratio of time spent performing normal processes to time spent performing corrective actions may improve the efficiency of the memory controller102and decrease memory latency.

The memory controller102may be configured to issue the first command112to the first redrive device104and the second command114to the second redrive device106. The memory controller102may be configured to reissue the second command (e.g., the reissued second command120) to the second redrive device106in response to detecting the transmission error118between the memory controller102and the second redrive device106. The memory controller102is configured to store at the first buffer108the first data116that is received from the first redrive device104in response to the first command112. The memory controller102may be configured to store at the second buffer110the second data122that is received from the second redrive device106in response to the reissued second command120. The memory controller102is configured to merge the second data122with the first data116.

The memory controller102may issue the first command112to the first redrive device104. The first redrive device104may decode and reformat the first command112to send to a first memory structure (not illustrated) connected to the first redrive device104. For example, after decoding and reformatting the first command112, the first redrive device104may transmit the first command112to the first memory structure.

In response to receiving the first command112from the first redrive device104, the first memory structure may transmit the first data116to the first redrive device104. The first redrive device104may reformat the first data116and transmit the reformatted first data116to the memory controller102via the northbound link of the first high speed link. In response to receiving the first data116, the memory controller102may store the first data116at the first buffer108. Storing the first data116at the first buffer108may allow the memory controller102to preserve good data while performing a corrective action in response to detection of the transmission error118between the memory controller102and the second redrive device106.

Detecting the transmission error118may include the second redrive device106detecting the transmission error118in the second command114received from the memory controller102. For instance, the second redrive device106may include logic that checks commands received from the memory controller102for cyclic redundancy checks (CRC) errors. The CRC checking may indicate that the second command114received from the memory controller102via the second southbound link contains a CRC error (e.g., the transmission error118).

After detecting the transmission error118, the second redrive device106may drop second subsequent commands in a second command stream received from the memory controller102and return an alert status frame150to the memory controller102. Dropping the second subsequent commands in the second command stream may include the second redrive device106not redriving the second command114or the second subsequent commands to a second memory structure (not illustrated).

The second redrive device106may return a stream of alert status frames to the memory controller102via a northbound link of the second high speed link in response to detection of the transmission error118. The memory controller102may use the received alert status frames to detect the transmission error118between the memory controller102and the second redrive device106. For example, the memory controller102may determine that the transmission error118occurred in a southbound link of the second high speed link. The determination may be based on the receipt of the alert status frame150via the northbound link of the second high speed link.

In response to detecting the transmission error118, the memory controller102may halt issuance of subsequent commands to both the first redrive device104and the second redrive device106to perform the corrective action on the link between the memory controller102and the second redrive device106. For instance, after receiving the alert status frame150, the memory controller102may issue a link reset of the second high speed link. The link reset may clear the second high speed link of the alert status frames. After the second high speed link is cleared, the second high speed link may be ready for reissuance of the second command stream. The memory controller102may reissue the second command (e.g., the reissued second command120) to the second redrive device106via the southbound link of the second high speed link.

The memory controller102may reissue the second command stream to the second redrive device106to allow the second redrive device106to redrive the second command stream to the second memory structure. For example, the memory controller102may reissue the second command stream from a point where the second redrive device106terminated the second command stream in response to detecting the transmission error118. The memory controller102may reissue the second command stream to the second redrive device106starting with the reissued second command120.

The second redrive device106may redrive the reissued second command120to the second memory structure. In response to receiving the reissued second command120, the second memory structure may retrieve the second data122and transmit the second data122to the second redrive device106. The second redrive device106may transmit the second data122to the memory controller102. The memory controller102may store the second data122in the second buffer110to merge with the first data116at the first buffer108. Rather than reissuing commands to both the redrive devices when the transmission error118is detected, storing the first data116allows the memory controller102to avoid errors that may be created by reissuing the first command112to the first redrive device104. For instance, execution of the first command112may have altered original data in a memory structure.

Reissuing the first command112may initiate retrieval of the altered data in the memory structure, instead of the original data that was retrieved as the first data116. Preservation of the first data116to merge with the second data122received in response to the reissued second command120may reduce the complexity of the corrective action that is performed. Reducing the complexity of the corrective action may, in turn, reduce the amount of time dedicated to performing the corrective action and increase the amount of time that the memory controller102is available to perform normal processes. Increasing the ratio of time spent performing normal processes to time spent performing corrective actions may improve the efficiency of the memory controller102and decrease memory latency.

Referring toFIG. 2, a diagram of another embodiment of a system to respond to error detection is illustrated and is generally designated200. The system200includes many elements found in the system100referred to inFIG. 1, where similar elements have the same reference number.

During operation, the memory controller102may issue the first command112to the first redrive device104. The first redrive device104may decode and reformat the first command112to send to a first memory structure (not illustrated). The first memory structure may be connected to the first redrive device104. For example, after decoding and reformatting the first command112, the first redrive device104may transmit the first command112to the first memory structure.

In response to receiving the first command112from the first redrive device104, the first memory structure may transmit the first data116to the first redrive device104. The first redrive device104may reformat the first data116and transmit the reformatted first data116to the memory controller102via the northbound link of the first high speed link. In response to receiving the first data116, the memory controller102may store the first data116at the first buffer108. Storing the first data116at the first buffer108may allow the memory controller102to preserve good data (i.e., the first data116) while performing a corrective action in response to detection of the transmission error118between the memory controller102and the second redrive device106.

Detecting the transmission error118may include the second redrive device106detecting the transmission error118in the second command114received from the memory controller102. For instance, the second redrive device106may include logic that checks commands received from the memory controller102for CRC errors. The CRC checking may indicate that the second command114received from the memory controller102via the second southbound link contains a CRC error (e.g., the transmission error118).

After detecting the transmission error118, the second redrive device106may drop second subsequent commands in a second command stream received from the memory controller102. The second redrive device106may further return an alert status frame to the memory controller102. Dropping the second subsequent commands in the second command stream may include the second redrive device106not redriving the second command114or the second subsequent commands to a second memory structure (not illustrated).

The second redrive device106may return a stream of alert status frames160to the memory controller102. The frames160may be returned via a northbound link of the second high speed link in response to detection of the transmission error118. The memory controller102may use the received alert status frames160to detect the transmission error118between the memory controller102and the second redrive device106. For example, the memory controller102may determine that the transmission error118occurred in a southbound link of the second high speed link. The determination may be based on a receipt of the alert status frame via the northbound link of the second high speed link.

In response to detecting the transmission error118, the memory controller102may halt issuance of subsequent commands to both the first redrive device104and the second redrive device106. The corrective action on the second high speed link between the memory controller102and the second redrive device106may be performed. For example, the memory controller102may issue a link reset of the second high speed link after receiving the alert status frames160. The link reset may clear the second high speed link of the alert status frames160. The second high speed link may further be ready for reissuance of the second command stream. The memory controller102may reissue the second command (e.g., the reissued second command120) to the second redrive device106via the southbound link of the second high speed link.

The memory controller102may reissue the second command stream to the second redrive device106to allow the second redrive device106to redrive the second command stream to the second memory structure. For instance, the memory controller102may reissue the second command stream from a point where the second redrive device106terminated the second command stream in response to detecting the transmission error118. The memory controller102may reissue the second command stream to the second redrive device106starting with the second command (e.g., the reissued second command120).

In a particular embodiment, the second redrive device106may redrive the reissued second command120to the second memory structure. In response to receiving the reissued second command120, the second memory structure may retrieve the second data122and transmit the second data122to the second redrive device106. The second redrive device106may transmit the second data122to the memory controller102. The memory controller102may store the second data122in the second buffer110to merge with the first data116at the first buffer108.

A second set of commands may be issued from the memory controller102to the redrive devices before the transmission error118is detected. For example, the memory controller102may issue a third command162to the first redrive device104after issuance of the first command112. The memory controller102may issue a fourth command166to the second redrive device106after issuance of the second command114. The memory controller102may receive third data164in response to the third command162. The third data164may be stored at the first buffer108. However, after receiving the alert status frames160from the second redrive device106, the memory controller102may reissue the fourth command (e.g., reissued fourth command170) to the second redrive device106. The memory controller102may receive fourth data172in response to the reissued fourth command170. The memory controller102may store the fourth data172at the second buffer110to merge with the third data164in the first buffer108. In a particular embodiment, the first buffer108includes several buffers. The first data116may be stored in one of the several buffers of the first buffer and the third data164may be stored in another one of the several buffers of the first buffer.

Rather than reissuing commands to both the redrive devices when the transmission error118is detected, storing the first data116and the third data164allows the memory controller102to avoid errors that may be created by reissuing the first command112and the third command162to the first redrive device104. For instance, execution of the first command112may have altered original data in a memory structure. Reissuance of the first command112may retrieve the altered data in the memory structure instead of the original data as retrieved in the first data116. Preservation of the first data116to merge with second data122received in response to the reissued second command120may reduce the complexity of the corrective action that is performed. Reducing the complexity of the corrective action may reduce the amount of time dedicated to performing the corrective action and increase the amount of time that the memory controller102is available to perform normal processes. Increasing the ratio of time spent performing normal processes to time spent performing corrective actions may improve the efficiency of the memory controller102and decrease memory latency.

FIG. 3is a flow diagram of a first embodiment of a method to respond to error detection and is generally designated300. In a particular embodiment, the method300is performed by any of the system ofFIGS. 1 and 2, or any combination thereof. The method300may include issuing a first command to a first redrive device and a second command to a second redrive device, at block302. For example, the memory controller102ofFIGS. 1 and 2may issue the first command112to the first redrive device104and the second command114to the second redrive device106. The method300may also include reissuing the second command to the second redrive device in response to detecting a transmission error between a memory controller and the second redrive device, at block304. For instance, the memory controller102ofFIGS. 1 and 2may reissue the second command120to the second redrive device106in response to detecting the transmission error between the memory controller102and the second redrive device106.

The method300may further include storing at a first buffer first data that is received from the first redrive device in response to the first command, at block306. For example, the memory controller102ofFIGS. 1 and 2may store at the first buffer108the first data116that is received from the first redrive device104in response to the first command112. The method300may include storing at a second buffer second data that is received from the second redrive device in response to the reissued second command, at block308. For instance, the memory controller102may store at the second buffer110the second data122that is received from the second redrive device106in response to the reissued second command120. The method300also includes merging the second data with the first data, at block310. For example, the memory controller102ofFIGS. 1 and 2may merge the second data122with the first data116.

FIG. 4is a diagram of another embodiment of a system to respond to error detection and is generally designated400. The system400includes a memory controller402and a redrive device404. The memory controller402and the redrive device404may be connected via a link406. The link406may include two unidirectional high speed links. For instance, the memory controller402may transmit to the redrive device404via a southbound link of the link406and the redrive device404may transmit to the memory controller402via a northbound link of the link406.

Generally, the memory controller402may transmit a signal pattern to a redrive device404to indicate that the memory controller402is initiating407a retrain of the link. To distinguish the transmission of the signal pattern indicating a link retrain action from a regular data transmission, the signal pattern may be a constant pattern without transitions. For example, the memory controller402may transmit for multiple cycles a signal equivalent to a digital constant of one. The signal would not include a transition to an equivalent of a digital constant of zero.

The memory controller402and the redrive device404may rely on transitions in the signal pattern to maintain alignment. Without receiving a transition during transmission of the constant pattern, the memory controller402and the redrive device404may be unable to maintain alignment. For instance, transmission of the constant pattern408may result in the memory controller402and the redrive device404losing alignment or becoming further misaligned. Further misalignment may result in an alignment locking algorithm performing more processes in a later stage to regain alignment.

Interrupting the transmission of the constant pattern409to transmit a sequence410of transitions412before resuming414the transmission of the constant pattern416may allow the memory controller402and the redrive device404to maintain alignment during the link retrain action. Alignment may be maintained when the number of transitions412transmitted satisfies a minimum acceptable transition density. Maintaining alignment during the link retrain action may allow the memory controller402and redrive device404to use a less efficient alignment locking algorithm at a later stage of the link retrain action. For example, an alignment locking algorithm may be selected that may perform relatively slowly, but that has reduced power, space and manufacturing requirements. The alignment locking algorithm may perform fewer processes to reconfirm alignment or resume alignment because the alignment was not lost. Reducing the number of processes that the alignment locking algorithm performs may reduce the overall latency of the link retrain action. Reducing the latency of the link retrain action may improve the overall efficiency of the memory controller402and reducing the size will cause it to cost less.

The memory controller402may be configured to transmit the constant pattern in response to initiation407of the retrain of the link between the memory controller402and the redrive device404. The memory controller402may be configured to interrupt409the transmission of the constant pattern408after the constant pattern has been transmitted for the minimum duration to transmit a sequence410of transitions412. The memory controller402may be configured to resume414the transmission of the constant pattern416after transmitting the sequence410of transitions412.

The memory controller402may issue a command stream to the redrive device404. For instance, the redrive device404may receive the command stream from the memory controller402via the southbound link of the link406. The redrive device404may decode and reformat the command stream to send to a memory structure (not illustrated) connected to the redrive device404. The memory structure may retrieve data in response to the command stream and may transmit the data to the redrive device404. The redrive device404may reformat the data and transmit the reformatted data to the memory controller402. For example, the redrive device404may transmit the data to the memory controller402via the northbound link of the link406after reformatting the data.

Communication on both the southbound link and the northbound link may be checked for errors. Error detection on the command stream received via the southbound link may be performed by the redrive device404. For instance, the redrive device404may include logic that performs CRC checking. The CRC checking may determine that a particular command in the command stream contains a single bit error (i.e., a transmission error). After detecting the transmission error, the redrive device404may drop all subsequent commands in the command stream and return an alert status frame to the memory controller402.

In a particular embodiment, the redrive device404returns a stream of alert status frames to the memory controller402via the northbound link in response to the transmission error. The memory controller402may use the received alert status frames to detect the transmission error between the memory controller402and the redrive device404. For example, the memory controller402may determine that the transmission error occurred in the southbound link of the link406based on the receipt of the alert status frame via the northbound link.

In response to detecting the transmission error, the memory controller402may perform a corrective action. For instance, after receiving the alert status frame, the memory controller402may issue a link reset of the link406. The link reset may clear the link406of the alert status frames. The link406may be ready for reissuance of the command stream. For example, the memory controller402may reissue the command stream to the redrive device404via the southbound link of the link406.

The link reset may be unsuccessful in clearing the link406of the alert status frames. The link406may not be ready to receive the reissued commands. For instance, the memory controller402may continue to receive alert status frames on the northbound link after performing the link reset. The memory controller402may initiate407a link retrain action. The link retrain action may include retraining the link406between the memory controller402and the redrive device404.

Retraining the link406may include the memory controller402notifying the redrive device404that the link is being retrained. Notifying the redrive device404that the memory controller402is initiating407the link retrain action may include transmitting the constant pattern408to the redrive device404. In a particular embodiment, the constant pattern is a ‘disable b’ signal that disables normal operations at the redrive device. For example, during transmission of the constant pattern408, the memory controller402may transmit a sequence of digital constants without transitions. The memory controller402may transmit all ones without a transition to zero. In response to receiving the signal pattern without a transition, the redrive device404may determine that the memory controller402is initiating407the link retrain action.

The constant pattern may be transmitted for a minimum duration to ensure that the redrive device404registers the transmission as an indication that the memory controller402is initiating407the link retrain action. The minimum duration may be based on a minimum number of unit intervals for the redrive device404to recognize the constant pattern. The unit interval may be the time for the memory controller402to transmit one transition on the link at line speed. For instance, the memory controller402may transmit the constant pattern for one hundred and forty-four unit intervals without a transition to indicate to the redrive device404that the memory controller402has initiated407the link retrain action.

The memory controller402may interrupt409the transmission of the constant pattern408after the constant pattern has been transmitted for the minimum duration by transmitting a sequence410of transitions412. Transmitting the sequence410of transitions412maintains alignment between the memory controller402and the redrive device404. The number of transitions412in the sequence410of transitions412may be based on a minimum bit transition density of the link406. The minimum bit transition density may indicate a minimum number of transitions412to maintain bit alignment between the memory controller402and the redrive device404. For example, the minimum number of transitions412necessary to maintain bit alignment may be eight transitions412. The memory controller402may transmit an alternating signal pattern equivalent to digital constants of ones and zeros before resuming the constant pattern of all ones.

After transmitting the sequence410of transitions412, the memory controller402may resume414transmission of the constant pattern416. Interrupting409the constant pattern408to issue the sequence410of transitions412may allow the memory controller402and the redrive device404to remain aligned. Maintaining alignment during the link retrain action may allow the memory controller402and redrive device404to use a less efficient alignment locking algorithm at a later stage of the link retrain action. For instance, an alignment locking algorithm may be selected that performs slow but uses less power and occupies less space. Although the alignment locking algorithm may perform relatively slowly, the alignment locking algorithm may perform fewer processes to regain alignment. Reducing the number of processes that the alignment locking algorithm performs may reduce the overall latency of the link retrain action. Reducing the latency of the link retrain action may improve the overall efficiency of the memory controller402.

FIG. 5is a flow diagram of a second embodiment of a method to respond to error detection and is generally designated500. In a particular embodiment, the method500is performed by the system ofFIG. 4. The method500includes transmitting a constant pattern in response to initiation of a retrain of a link between a memory controller and a redrive device, at block502. For example, the memory controller402ofFIG. 4transmits the constant pattern408in response to initiation407of the retrain of the link406between the memory controller402and the redrive device404. The method500also includes interrupting the transmission of the constant pattern after the constant pattern has been transmitted for a minimum duration to transmit a sequence of transitions, at block504. For instance, the memory controller402ofFIG. 4may interrupt409the transmission of the constant pattern408after the constant pattern has been transmitted for a minimum duration to transmit a sequence410of transitions412. The method500further includes resuming the transmission of the constant pattern after transmitting the sequence of transitions, at block506. For example, the memory controller402ofFIG. 4may resume414the transmission of the constant pattern416after transmitting the sequence410of transitions412.

FIG. 6is a diagram of a fifth embodiment of a system to respond to error detection and is generally designated600. The system600includes a redrive device604, a memory controller port602with command arbitration logic612, a first scrub controller608and a second scrub controller610. The memory controller port602and the redrive device604are connected via a link606. The link606may include two uni-directional links. For instance, the memory controller602may transmit to the redrive device604via a southbound link of the link606and the redrive device604may transmit to the memory controller602via a northbound link of the link606.

Generally, each scrub controller may create scrub commands to scrub a particular memory structure. For example, the first scrub controller608may create first scrub commands614directed to a first memory structure (not illustrated) and the second scrub controller610may create second scrub commands616directed to a second memory structure (not illustrated). The memory controller may alternate issuance of the scrub commands from each scrub controller. Alternating between each scrub controller may allow the memory controller port602to scrub multiple memory structures via a single link606.

The memory controller port602may be configured to create the first scrub commands614at the first scrub controller608. The memory controller port602may be configured to create the second scrub commands616at the second scrub controller610. The memory controller port602may be configured to alternate issuance of the first scrub commands614and the second scrub commands616at the memory controller port602.

The memory controller port602may use the scrub commands to detect and correct errors in data. For instance, the first scrub controller608may create a scrub read command (e.g., the first scrub command) that is issued from the memory controller port602. In response to issuance of the scrub read command, the memory controller port602may receive scrub read data. The memory controller port602may include logic that checks the scrub read data for error correction codes (ECC). For example, ECC checking may indicate that the scrub read data contains a single bit error. The memory controller port602may invoke redundant bit steering (RBS) to correct the error. After the error is corrected, the first scrub controller608may create a scrub write command that is issued from the memory controller port602. The scrub write command may write the corrected scrub read data in a memory address from which the scrub read data was previously retrieved.

The memory controller port602may alternate issuance of the first scrub commands614and the second scrub commands616. The command arbitration logic612alternates issuance of the first scrub commands614and the second scrub commands616. Alternating issuance of the scrub commands may include issuing the scrub commands in the following order: a first scrub command, a second scrub command, a first scrub command, and a second scrub command. Alternating between each scrub command may allow the memory controller port602to scrub multiple memory structures via a single link (e.g., the link606). For instance, the first scrub commands614may be directed to the first memory structure and the second scrub commands616may be directed to the second memory structure. The addresses in the first memory structure and the second memory structure may be scrubbed at the same time by the same memory controller port602.

Referring toFIG. 7, a diagram of another embodiment of a system to respond to error detection is illustrated and is generally designated700. The system700includes a redrive device604, a first memory structure730, and a second memory structure732. The system also includes a memory controller port602with command arbitration logic612, a first scrub controller608and a second scrub controller610. The memory controller port602and the redrive device604may be connected via a link606. The link606may include two unidirectional links. For example, the memory controller may transmit to the redrive device604via a southbound link of the link606and the redrive device604may transmit to the memory controller via a northbound link of the link606. The redrive device604may be connected to the first memory structure730via a first memory bus736and connected to the second memory structure732via a second memory bus738.

Generally, each scrub controller may create scrub commands to scrub a particular memory structure. For instance, the first scrub controller608may create first scrub commands614directed to the first memory structure730. The second scrub controller610may create second scrub commands616directed to the second memory structure732. The memory controller may alternate issuance of the scrub commands from each scrub controller to the redrive device604via the link606. The redrive device604may issue the first scrub commands614to the first memory structure730and the second scrub commands616to the second memory structure732. Alternating between each scrub controller may allow the memory controller port602to scrub multiple memory structures via a single link (e.g., the link606).

The memory controller port602may use the scrub commands to detect and correct errors in data. For example, the first scrub controller608may create a first scrub read command (e.g., the first scrub command) that is issued from the memory controller port602to the redrive device604. The redrive device604may format and decode the scrub read command to transmit to the first memory structure730. For instance, the redrive device604may change the scrub read command to a DDR address that is recognized by the first memory structure730. The redrive device604may transmit the formatted scrub read command to the first memory structure730via the first memory bus736.

In response to receiving the formatted scrub read command (e.g., the first scrub command), the first memory structure730may retrieve scrub read data (e.g., first data720) and transmit the scrub read data to the redrive device604via the first memory bus736. The first memory structure730may retrieve the scrub read data in a burst chop four mode (BC4) mode. Operating in BC4mode, the first memory structure730may retrieve four beats of data followed by four beats of gap. For example, the first memory structure730may transmit four beats of the scrub read data (e.g., the first data720) to the redrive device604followed by four beats of gap. The redrive device604may receive a first data stream that includes an alternating pattern of gaps and portions of the first data720.

The redrive device604may receive second scrub commands616from the memory controller via the link606. In a particular embodiment, the command arbitration logic612alternates issuance of the first scrub commands614and the second scrub commands616. The redrive device604may transmit the second commands to the second memory structure732over the second memory bus738. In response to the second scrub commands616, the second memory structure732may retrieve second data722and transmit the second data722to the redrive device604via the second memory bus738. Operating in BC4mode, the second memory structure732may transmit four beats of the second data722to the redrive device604followed by four beats of gap. The redrive device604may receive a second data stream that includes an alternating pattern of gaps and portions of the second data722.

The redrive device604may format and decode the first data720in the first data stream and the second data722in the second data stream. For instance, the redrive device604may change the first data720and the second data722into data that corresponds to addresses in the memory controller port602. After formatting the first data720and the second data722, the redrive device604may transmit the first data720and the second data722to the memory controller port602via the link606.

The redrive device604may alternate transmitting the first data720from the first data stream and transmitting the second data722from the second data stream. The redrive device604may transmit the first data stream and the second data stream without the gaps. The memory controller port602may receive an alternating pattern of the first data720and the second data722without gaps. The memory controller port602may direct the first data720to the first scrub controller608and the second data722to the second scrub controller610. Receiving data via the link606without the gaps may improve utilization of the link606.

The memory controller port602may include logic that checks data received via the link606for errors. For example, ECC checking may indicate that the scrub read data (e.g., the first data720) contains a single bit error. The memory controller port602may invoke RBS to correct the error. After the error is corrected, the first scrub controller608may issue a scrub write command (e.g., the first command) to the redrive device604. The redrive device604may format the scrub write command and transmit the scrub write command to the first memory structure730. The scrub write command may instruct the first memory structure730to overwrite data in the first memory structure730with the scrub read data corrected by RBS.

One of the second scrub commands616issued by the memory controller port602may be the scrub write command. The redrive device604may issue an alternating pattern of scrub write commands to both the first memory structure730and the second memory structure732. Alternating issuance of the first scrub commands614and the second scrub commands616may allow the memory controller port602to scrub both the first memory structure730and the second memory structure732via the single link606. Performing memory scrubbing on multiple memory structures improves the efficiency of the memory controller port602and reduces memory latency.

FIG. 8is a flow diagram of a third embodiment of a method to respond to error detection and is generally designated800. The method800is performed by any of the systems ofFIGS. 6 and 7, or any combination thereof. The method800includes creating first scrub commands at a first scrub controller, at block802. For instance, the first scrub controller608ofFIGS. 6 and 7may create the first scrub commands614. The method800also includes creating second scrub commands at a second scrub controller, at block804. For example, the second scrub controller610ofFIGS. 6 and 7may create the second scrub commands616. The method800further includes alternating issuance of the first scrub commands and the second scrub commands at a memory controller port, at block806. For instance, the memory controller port602ofFIGS. 6 and 7may alternate issuance of the first scrub commands614and the second scrub commands616.

Particular embodiments can take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment containing both hardware and software elements. The disclosed methods are implemented in software, which includes but is not limited to firmware, resident software, microcode, etc.