An optoelectronic device including first, second, and third three-dimensional light-emitting diodes having an axial configuration. Each light-emitting diode includes a semiconductor element and an active region resting on the semiconductor element. Each semiconductor element corresponds to a microwire, a nanowire, a nanometer- or micrometer-range conical or frustoconical element. The first, second, and third light-emitting diodes are configured to respectively emit first, second, and third radiations at first, second, and third wavelengths. The semiconductor elements of the first, second, and third light-emitting diodes respectively have first, second, and third diameters. The first diameter is smaller than the second diameter and the second diameter is smaller than the third diameter, the first wavelength being greater than the third wavelength and the second wavelength being greater than the first wavelength.

The present patent application claims the priority benefit of French patent application FR20/09895 which is herein incorporated by reference.

TECHNICAL BACKGROUND

The present invention generally concerns optoelectronic devices comprising three-dimensional semiconductor elements of nanowire or microwire type, and a method of manufacturing the same, and more particularly optoelectronic devices capable of displaying images, particularly a display screen or an image projection device.

PRIOR ART

A pixel of an image corresponds to the unit element of the image displayed or captured by the optoelectronic device. For the display of color images, the optoelectronic device generally comprises, for the display of each pixel of the image, at least three components, also called display sub-pixels, which each emit a light radiation substantially in a single color (for example, red, green, and blue). The superposition of the radiations emitted by the three display sub-pixels provides the observer with the colored sensation corresponding to the pixel of the displayed image. In this case, the assembly formed by the three display sub-pixels used for the display of a pixel of an image is called display pixel of the optoelectronic device.

There exist optoelectronic devices comprising three-dimensional semiconductor elements of nanowire or microwire type based on III-V compounds enabling to form so-called three-dimensional light-emitting diodes. A light-emitting diode comprises an active region which is the region of the light-emitting diode having most of the electromagnetic radiation supplied by the light-emitting diode emitted therefrom. A three-dimensional light-emitting diode may be formed in a so-called radial configuration, also called core/shell configuration, where the active region is formed at the periphery of the three-dimensional semiconductor element. It may also be formed in a so-called axial configuration, where the active region does not cover the periphery of the three-dimensional semiconductor element but essentially extends along a longitudinal epitaxial growth axis.

Three-dimensional light-emitting diodes in an axial configuration have an emission surface area smaller than that of light-emitting diodes in a radial configuration, but have the advantage of being made of a semiconductor material of better crystalline quality, thus providing a higher internal quantum efficiency, particularly due to a better relaxation of the stress at the interfaces between semiconductor layers.

It is known to cover a light-emitting diode with a photoluminescent material capable of converting the electromagnetic radiation emitted by the active area into an electromagnetic radiation at a different wavelength, particularly higher. However, such photoluminescent materials may have a high cost, have a low conversion efficiency, and have a performance which degrades over time.

It would thus be desirable to be able to form an optoelectronic device comprising light-emitting diodes configured to directly emit radiations in three different colors to obtain a color display without using photoluminescent materials.

Further, the industrial development of the method of manufacturing an active region of an axial-type three-dimensional light-emitting diode based on III-V compounds is a touchy operation. It is known to simultaneously form light-emitting diodes however emitting radiations in different colors by using semiconductor elements of different diameters, the wavelengths of the radiations emitted by the active areas particularly depending on the diameters of the semiconductor elements and on the distance between the semiconductor elements, the wavelength theoretically decreasing with the diameter of the semiconductor element. However, it may be difficult to form light-emitting diodes emitting in blue, which would correspond to semiconductor elements having too small a diameter to be compatible with manufacturing methods at an industrial scale.

SUMMARY

Thus, an object of an embodiment aims at least partly overcoming the disadvantages of the previously-described optoelectronic devices comprising light-emitting diodes.

Another object of an embodiment is for the active area of each light-emitting diode to comprise a stack of layers of semiconductor materials based on III-V compounds.

Another object of an embodiment is for the optoelectronic device to comprise light-emitting diodes configured to emit light radiations in three different colors without using photoluminescent materials.

Another object of an embodiment is for the optoelectronic device to comprise light-emitting diodes configured to emit light radiations in three different colors and which are manufactured simultaneously.

An embodiment provides an optoelectronic device comprising first, second, and third three-dimensional light-emitting diodes with an axial configuration, each light-emitting diode comprising a semiconductor element and an active region resting on the semiconductor element, each semiconductor element corresponding to a microwire, a nanowire, a nanometer- or micrometer-range conical element, or a nanometer- or micrometer-range frustoconical element, the first light-emitting diodes being configured to emit a first radiation at a first wavelength, the semiconductor elements of the first light-emitting diodes having a first diameter, the second light-emitting diodes being configured to emit a second radiation at a second wavelength, the semiconductor elements of the second light-emitting diodes having a second diameter, and the third light-emitting diodes being configured to emit a third radiation at a third wavelength, the semiconductor elements of the third light-emitting diodes having a third diameter, the first diameter being smaller than the second diameter and the second diameter being smaller than the third diameter, the first wavelength being greater than the third wavelength and the second wavelength being greater than the first wavelength.

According to an embodiment, the first diameter varies from 80 nm to 150 nm.

According to an embodiment, the second diameter varies from 200 nm to 350 nm.

According to an embodiment, the third diameter varies from 370 nm to 500 nm.

According to an embodiment, the first wavelength is in the range from 510 nm to 570 nm.

According to an embodiment, the second wavelength is in the range from 600 nm to 720 nm.

According to an embodiment, the third wavelength is in the range from 430 nm to 490 nm.

According to an embodiment, the device comprises a first optoelectronic circuit bonded to a second electronic circuit, the second electronic circuit comprising electrically-conductive pads, the first optoelectronic circuit comprising pixels and comprising, for each pixel:a first electrically-conductive layer;for each of the first, second, and third light-emitting diodes, said semiconductor element extending perpendicularly to the first electrically-conductive layer and in contact with the first electrically-conductive layer and the active region resting on the end of the semiconductor element opposite to the first electrically-conductive layer; andsecond, third, fourth, and fifth electrically-conductive layers electrically coupled to the electrically-conductive pads, the second electrically-conductive layer being coupled to the active regions of the first light-emitting diodes, the third electrically-conductive layer being coupled to the active regions of the second light-emitting diodes, the fourth electrically-conductive layer being coupled to the active regions of the third light-emitting diodes, and the fifth electrically-conductive layer being coupled TO the first electrically-conductive layer.

According to an embodiment, each active region comprises a single quantum well or multiple quantum wells.

According to an embodiment, the semiconductor elements and the active regions are made of III-V compounds.

According to an embodiment, the semiconductor elements of the first, second, and third light-emitting diodes are formed by MOCVD.

According to an embodiment, the active regions of the first, second, and third light-emitting diodes are formed by MBE.

According to an embodiment, the semiconductor elements of the first, second, and third light-emitting diodes rest on a substrate and are in contact with a material adapted to the epitaxial growth of the semiconductor elements of the first, second, and third light-emitting diodes.

According to an embodiment, the first, second, and third light-emitting diodes form a monolithic structure.

An embodiment also provides a method of manufacturing the optoelectronic device such as previously defined, comprising the successive steps of:simultaneously forming the semiconductor elements of the first, second, and third light-emitting diodes; andsimultaneously forming the active regions of the first, second, and third light-emitting diodes on the semiconductor elements of the first, second, and third light-emitting diodes.

According to an embodiment, the method comprises the successive steps of:simultaneously forming on a support the semiconductor elements of the first, second, and third light-emitting diodes and forming the active regions of the first, second, and third light-emitting diodes on the semiconductor elements of the first, second, and third light-emitting diodes;forming an electrically-insulating layer between the three-dimensional semiconductor elements of the first, second, and third light-emitting diodes; andremoving the support.

DESCRIPTION OF THE EMBODIMENTS

Like features have been designated by like references in the various figures. In particular, the structural and/or functional features that are common among the various embodiments may have the same references and may dispose identical structural, dimensional and material properties. For the sake of clarity, only the steps and elements that are useful for an understanding of the embodiments described herein have been illustrated and described in detail. En particulier, les moyens pour commander les diodes électroluminescentes d'un dispositif optoélectronique sont bien connus et ne seront pas décrits.

Unless specified otherwise, the expressions “around”, “approximately”, “substantially” and “in the order of” signify within 10%, and preferably within 5%. Further, unless specified otherwise, the expression “insulating” means “electrically insulating” and the expression “conductive” means “electrically conductive”. In the following description, the inner transmittance of a layer corresponds to the ratio of the intensity of the radiation coming out of the layer to the intensity of the radiation entering into the layer. The absorption of the layer is equal to the difference between 1 and the inner transmittance. In the following description, a layer is said to be transparent to a radiation when the absorption of the radiation through the layer is smaller than 60%. In the following description, a layer is said to be absorbing for a radiation when the absorption of the radiation in the layer is higher than 60%. When a radiation exhibits a generally “bell”-shaped spectrum, for example, of Gaussian shape, having a maximum, wavelength of the radiation, or central or main wavelength of the radiation, designates the wavelength at which the maximum of the spectrum is reached. In the following description, the refraction index of a material corresponds to the refraction index of the material for the wavelength range of the radiation emitted by the optoelectronic device. Unless specified otherwise, the refraction index is considered as substantially constant over the wavelength range of the useful radiation, for example, equal to the average of the refraction index over the wavelength range of the radiation emitted by the optoelectronic device.

The present application particularly concerns optoelectronic devices comprising light-emitting diodes comprising three-dimensional elements, for example, microwires, nanowires, nanometer- or micrometer-range conical elements, or nanometer- or micrometer-range frustoconical elements. In particular, a conical or frustoconical element may be a circular conical or frustoconical element or a pyramidal conical or frustoconical element. In the following description, embodiments are in particular described for electronic devices comprising microwires or nanowires. However, such embodiments may be implemented for three-dimensional elements other than microwires or nanowires, for example, conical or frustoconical three-dimensional elements.

The terms “microwire”, “nanowire”, “conical element”, or “frustoconical element” designate a three-dimensional structure having a shape elongated along a preferred direction, having at least two dimensions, called minor dimensions, in the range from 5 nm to 2.5 μm, preferably from 50 nm to 1 μm, more preferably from 30 nm to 300 nm, the third dimension, called major dimension, being greater than or equal to 1 time, preferably greater than or equal to 5 times, the largest minor dimension, for example, in the range from 1 μm to 5 μm.

In the following description, the term “wire” is used to designate a “microwire” or a “nanowire”. Preferably, the median line of the wire which runs through the centers of gravity of the cross-sections, in planes perpendicular to the preferred direction of the wire, is substantially rectilinear and is called “axis” of the wire hereafter. The wire diameter is here defined as being a quantity associated with the perimeter of the wire at the level of a cross-section. This may be the diameter of a disk having the same surface as the cross-section of the wire. The local diameter, also called diameter hereafter, is the wire diameter at the level of a given height thereof along the wire axis. The mean diameter is the mean, for example, arithmetic, of the local diameters along the wire or a portion thereof.

According to an embodiment, each axial-type light-emitting diode comprises a wire, as previously described, and an active region on the upper portion of the wire. The active region is the region from which most of the radiation supplied by the light-emitting diode is emitted. The active region may comprise confinement means. The active region may comprise a quantum well, two quantum wells, or a plurality of quantum wells, each quantum well being interposed between two barrier layers, the quantum well having a bandgap energy smaller than that of the barrier layers. The active region may comprise a quantum well or quantum wells made of a ternary compound which comprises the group-III and -V elements of the wire and an additional group-III element. The length of the radiation emitted by the active region depends on the incorporated proportion of additional group-III element. For example, the wires may be made of GaN and the quantum well(s) may be made of InGaN. The length of the radiation emitted by the active region accordingly depends on the incorporated proportion of In.

It is known that the proportion of the additional group-III element varies according to the wire diameter. However, documents mentioning such a variation up to now describe an increase in the proportion of the additional group-III element according to the wire diameter, and thus an increase in the wavelength of the radiation emitted by an axial-type light-emitting diode comprising such a wire.

The inventors have shown that there can be observed first, second, and third successive ranges of diameters with an increase in the wavelength of the radiation emitted by a light-emitting diode when the wire diameter increases over the first range of diameters, a decrease in the wavelength of the radiation emitted by a light-emitting diode when the wire diameter increases over the second range of diameters, and a stagnation of the wavelength of the radiation emitted by a light-emitting diode when the wire diameter increases over the third range of diameters.

These results have been advantageously obtained with wires formed by metal-organic chemical vapor deposition (MOCVD) and active regions typically formed by molecular beam epitaxy (MBE).

The previously-described method may be implemented to manufacture an optoelectronic device capable of displaying images, in particular a display screen or an image projection device. In particular, the previously-described method may be implemented to manufacture wires of different mean diameters, for example, first wires having a small mean diameter, second wires having an intermediate diameter, and third wires having a large mean diameter. The active regions formed on the first, second, and third wires will emit radiations at different wavelengths. In particular, the first wires having a small mean diameter will emit a radiation at a first central wavelength, the second wires having an intermediate mean diameter will emit a radiation at a second central wavelength, and the third wires having an intermediate mean diameter will emit a radiation at a third central wavelength, the second wavelength being greater than the first wavelength and the third wavelength being smaller than the first wavelength. A color display screen can then be manufactured.

The forming of the wires by MOCVD advantageously enables to obtain wires having less defects, in particular without defects, as compared with those capable of being obtained by MBE. The forming of the wires by MOCVD advantageously enables to obtain a fast growth of the wires. It further enables to easily obtain wires having diameters complying with the diameter-to-wavelength variation curve implemented according to the present invention. MBE methods advantageously enable to incorporate a greater proportion of the additional group-III element into the quantum wells as compared with the MOCVD method.

Further, the fact for the active region to be only formed on the upper portion of the wire, and not on the lateral sides of the wire advantageously enables to form the active region only on a c plane or semi-polar planes and not on m planes. This advantageously enables to incorporate a greater proportion of the additional group-III element into the quantum wells as compared with the case where the active region is grown on m planes.

FIG.1is a partial simplified cross-section view of an optoelectronic device10formed from wires such as previously described and capable of emitting an electromagnetic radiation. According to an embodiment, an optoelectronic device10comprising at least two integrated circuits12and14, also called chips, is provided. The first integrated circuit12comprises light-emitting diodes. The second integrated circuit14comprises electronic components, particularly transistors, used for the control of the light-emitting diodes of the first integrated circuit12. The first integrated circuit12is bonded to the second integrated circuit, for example, by molecular bonding or by a “flip-chip”-type bonding, particularly a ball or microtube “flip-chip” method. First integrated circuit12is called optoelectronic circuit or optoelectronic chip in the following description and second integrated circuit14is called control circuit or control chip in the following description.

Preferably, optoelectronic chip12only comprises light-emitting diodes and elements of connection of these light-emitting diodes and control chip14comprises all the electronic components necessary to control the light-emitting diodes of the optoelectronic chip. As a variant, optoelectronic chip12may also comprise other electronic components in addition to the light-emitting diodes.

FIG.1shows, in its left-hand portion, the elements of optoelectronic chip12for a display pixel, the structure being repeated for each display pixel, and, in its right-hand portion, elements adjacent to the display pixels and that may be common to a plurality of display pixels.

Optoelectronic chip12comprises, from bottom to top inFIG.1:an electrically-insulating layer16, at least partially transparent to the electromagnetic radiations emitted by the light-emitting diodes and which delimits a surface17;an electrically-conductive layer18, at least partially transparent to the electromagnetic radiations emitted by the light-emitting diodes;first wires20(three first wires being shown) of diameter D1, second wires22(three second wires being shown) of diameter D2, and third wires24(three third wires being shown) of diameter D3, the first, second, and third wires having axes parallel to one another and perpendicular to surface17, extending from conductive layer18and in contact with conductive layer18, diameter D1being smaller than diameter D2and diameter D2being smaller than diameter D3;a first head26at the end of each first wire20opposite to conductive layer18, a second head28at an end of each second wire22opposite to conductive layer18, and a third head30at an end of each third wire24opposite to conductive layer18;an electrically-insulating layer32made of a first electrically-insulating material between wires20,22,24having a thickness substantially equal to the sum of the height H, measured along the axis of the wires, of wire20,22,24and of the associated head26,28,30;an electrically-insulating layer34of a second electrically-insulating material, which may be different from the first insulating material or identical to the first insulating material, extending around first insulating layer32and of same thickness as insulating layer32;an opening36extending through insulating layer34across the entire thickness of insulating layer34;an electrically-conductive layer38extending in opening36and being in contact with conductive layer18;distinct electrically-conductive layers42,44,46,48, conductive layer42being in contact with first heads26, conductive layer44being in contact with second heads28, conductive layer46being in contact with third heads30, and conductive layer48being in contact with conductive layer38;an electrically-insulating layer50covering conductive layers42,44,46, and48and extending between conductive layers42,44,46, and48and delimiting a surface51, preferably substantially planar; andelectrically-conductive pads52,54,56,58capable of having a multilayer structure, extending through insulating layer50and flush with surface51, conductive pad52being in contact with conductive layer42, conductive pad54being in contact with conductive layer44, conductive pad56being in contact with conductive layer46, and conductive pad58being in contact with conductive layer48.

Control chip14particularly comprises on the side of optoelectronic chip12an electrically-insulating layer60delimiting a surface61, preferably substantially planar, and conductive pads62flush with surface61, conductive pads62being electrically coupled to conductive pads52,54,56,58. In the case where control chip14is bonded to optoelectronic chip12by molecular bonding, conductive pads62may be in contact with conductive pads52,54,56,58. In the case where control chip14is bonded to optoelectronic chip12by a “flip-chip”-type bond, solder balls or microtubes may be interposed between conductive pads62and conductive pads52,54,56,58.

The assembly formed by each wire20,22,24and the associated head26,28,30forms a wire-shaped elementary light-emitting diode in axial configuration.

FIG.2is a partial simplified cross-section view of a more detailed embodiment of the head26of a light-emitting diode. Heads28and30may have a similar structure.

Head26comprises, from bottom to top inFIG.2:possibly a semiconductor layer70, also called semiconductor cap, made of the same material as wire20and doped with a first conductivity type, for example, type N, covering the upper end72of wire20and having an upper surface74;an active region76covering the surface74of semiconductor layer70; anda semiconductor stack78covering active region76and comprising at least one semiconductor layer80, having a conductivity type opposite to that of wire20, covering active region76.

Each wire20,22,24and each semiconductor layer70,80are at least partly formed from at least one semiconductor material. According to an embodiment, the semiconductor material is selected from the group comprising III-V compounds, for example, a III-N compound. Examples of group-III elements comprise gallium (Ga), indium (In), or aluminum (Al). Examples of III-N compounds are GaN, AlN, InN, InGaN, AlGaN, or AlInGaN. Other group-V elements may also be used, for example, phosphorus or arsenic. Generally, the elements in the III-V compound may be combined with different molar fractions. The semiconductor material of wires20,22,24, and/or of semiconductor layers70,80may comprise a dopant, for example, silicon, ensuring an N-type doping of a III-N compound, or magnesium ensuring a P-type doping of a III-N compound.

Stack78may further comprise an electron-blocking layer82between active region76and semiconductor layer80, and a bonding layer84covering semiconductor layer80on the side opposite to active region76, bonding layer84being covered with conductive layer42. Bonding layer84may be made of the same semiconductor material as semiconductor layer80, with the same conductivity type as semiconductor layer80but with a greater dopant concentration. Bonding layer84enables to form an ohmic contact between semiconductor layer80and conductive pad42.

Active region76is the region from which most of the radiation supplied by the light-emitting diode is emitted. According to an example, active region76may comprise confinement means. Active region76may comprise at least one quantum well, comprising a layer of an additional semiconductor material having a bandgap energy smaller than that of semiconductor layer70and of semiconductor layer80, preferably interposed between two barrier layers, thus improving the confinement of charge carriers. The additional semiconductor material may comprise the III-V compound of doped semiconductor layer70,80having at least one additional element incorporated therein. As an example, in the case of wires20,22,24made of GaN, the additional material forming the quantum well is preferably InGaN. Active region76may be made of a single quantum well or of a plurality of quantum wells.

According to a preferred embodiment, each wire20,22,24is made of GaN. Semiconductor layer70may be made of GaN and be doped with the first conductivity type, for example, type N, in particular with silicon. The height of conductive layer70, measured along axis C, may be in the range from 10 nm to 1 μm, for example, in the range from 20 nm to 200 nm. Active region76may comprise a single or a plurality of quantum wells, for example, made of InGaN. Active region76may comprise a single quantum well which extends between semiconductor layers70,80. As a variant, it may comprise multiple quantum wells and it is then formed of an alternation along axis C of quantum wells86, for example, made of InGaN, and of barrier layers88, for example, made of GaN, three GaN layers88and two InGaN layers86being shown as an example inFIG.2. GaN layers88may for example be N- or P-type doped, or non-doped. The thickness of active region76, measured along axis C, may be in the range from 2 nm to 100 nm. Conductive layer80may be made of GaN and be doped with the second conductivity type opposite to the first type, for example, type P, in particular with magnesium. The thickness of semiconductor layer80may be in the range from 20 nm to 100 nm. When an electronic-blocking layer82is present, it may be made of GaN or of a ternary III-N compound, for example, AlGaN or AlInN, advantageously P-type doped. This enables to increase the radiative combination rate in active region76. The thickness of electron-blocking layer82may be in the range from 10 nm to 50 nm. Electron-blocking layer82may correspond to a superlattice of InAlGaN or of AlGaN and GaN layers, each layer for example having a 2-nm thickness.

Tests have been carried out. For the tests, wires20were made of GaN. Active regions76were each comprised of seven quantum wells made of InGaN separated by GaN layers. Wires20have been formed by MCVD and active regions76have been formed by MBE. The wavelength of the radiation emitted by active regions76has been measured, as well as the diameter of wires20.

FIG.3gathers the results of these tests. The axis of ordinates shows the central wavelength λ, expressed in nanometers, of the radiation emitted by active regions76, and the axis of abscissas shows the diameter D, expressed in nanometers, of wires20. The results of a first series of tests are shown inFIG.3by white circles and the results of a second series of tests are shown inFIG.3by black circles. Curve CT is the curve of variation of wavelength λ according to diameter D, obtained by a cubic spline regression from the values obtained at the first and second tests. Horizontal lines R, G, and B respectively correspond to colors red, green, and blue.

As a comparison, black diamonds show the results disclosed in Kishino et al.'s publication entitled “Monolithic integration of four-colour InGaN-based nanocolumn LEDs” (Elec Letters 28th May 2015 Vol 51 pages 852-854), and hexagons containing a cross show the results disclosed in Mi et al.'s publication entitled “Tunable, Full-Color Nanowire Light Emitting Diode Arrays Monolithically Integrated on Si and Sapphire” (Proc. of SPIE Vol. 9748+, 2016). The comparison results have been obtained with GaN wires and active regions with a single InGaN quantum well. Further, the wires and the active regions were formed by MBE for Mi et al. and Kishino et al.'s publications. For the comparison results, an increase in the wavelength of the emitted radiation with the wire diameter can be observed. It is known that the wavelength of the radiation emitted by the active region increases when the proportion of indium in the quantum well(s) increases. The comparison results thus imply for the proportion of indium in the single quantum well to increase when the wire diameter increases.

The forming of the wires by MOCVD has enabled to form wires of greater diameters than what is generally achieved by MBE, so that after the forming of the active regions by MBE, it has been unexpectedly observed that variation curve CT successively comprises a first rising portion C1, for which the wavelength of the emitted radiation increases with the diameter of the wire, a second falling portion C2, for which the wavelength of the emitted radiation decreases with the diameter of the wire, and a third substantially constant portion C3, for which the wavelength of the emitted radiation varies little with the wire diameter.

According to an embodiment, first rising portion C1is obtained for a wire diameter varying in a first range P1from approximately 50 nm to approximately 300 nm. The wavelength of the radiation emitted over the first rising portion increases from approximately 510 nm to approximately 675 nm. According to an embodiment, the second falling portion C2is obtained for a wire diameter varying in a second range P2from approximately 300 nm to approximately 375 nm. The wavelength of the radiation emitted over the second falling portion decreases from approximately 675 nm to approximately 475 nm. According to an embodiment, the third constant portion C3is obtained for a wire diameter in a third range P3from approximately 375 nm to approximately 550 nm. The wavelength of the radiation emitted over the third constant portion varies between approximately 460 nm and 490 nm. As shown inFIG.3, a light-emitting diode emitting in blue may be formed with a diameter in third range P3and light-emitting diodes emitting in green and in red may be formed with a diameter in first range P1. A light-emitting diode emitting in green may be formed with a diameter in second range P2. However, in practice, the variability of the wavelength obtained according to the diameter may be too high for an application at an industrial scale.

A display pixel has been formed by forming first light-emitting diodes with wires20of small diameter D1, second light-emitting diodes with wires22of intermediate diameter D2, and third light-emitting diodes with wires24of large diameter D3.

FIG.4shows an XY chromaticity diagram having the results of the first and second tests indicated thereon by black circles. By selecting, to form display sub-pixels, the light-emitting diodes for which the radiations correspond to circles DR, DG, and DB closest to the “apexes” of the chromaticity diagram, it is possible to display an image pixel, the color of which can be obtained by combination of the colors corresponding to circles DR, DG, and DB. For circle DR, the diameter was equal to approximately 200 nm-250 nm. For circle DG, the diameter was equal to approximately 100 nm-150 nm. For circle DB, the diameter was greater than or equal to approximately 370 nm. There appears that a large portion of the chromaticity diagram can be reached.

FIG.5shows curves CR, CG, and CBof light intensity I, expressed in arbitrary units (a.u.), according to the wavelength λ, expressed in nanometers (nm), of the radiation respectively emitted by the light-emitting diodes corresponding to circles DR, DG, and DB inFIG.4. As shown in this drawing, the spectrums of the radiations of these light-emitting diodes are relatively narrow.

FIG.6illustrates a possible explanation of the variation of the curve CT ofFIG.3.FIG.6very schematically shows three wires20,22,24, without showing the associated active regions76, semiconductor stacks78and conductive layers42,44, and46. The upper portion of each wire20,22,24may comprise a c plane (surface90perpendicular to axis C) and/or semi-polar planes (surface92inclined with respect to axis C). Active region76is likely to cover a c plane and/or semi-polar planes. The optical properties of the portion of active region76covering a c plane are not the same as those of the portion of active region76covering semi-polar planes. In particular, the maximum rate of incorporation of the additional element into the portion of active area76covering a c plane is greater than the maximum rate of incorporation of the additional element into the portion of active area76covering semi-polar planes. An explanation of the variation of the curve CT ofFIG.3would be the following: in the first range P1of diameters, the contribution, in the general radiation emitted by active region76, of the portion of active region76resting on a c plane is predominating over the contribution of the portion of active region76resting on semi-polar planes. Thereby, an increase in the wavelength of the general radiation with the wire diameter can be observed. In the second range P2of diameters, the significances of the contribution in the general radiation of the portion of active region76resting on a c plane and of the contribution in the general radiation of the portion of active region76resting on semi-polar planes are inverted and, since the incorporation of indium into the portion of active region76resting on semi-polar planes is decreased, the central wavelength of the general radiation drops. In the third range P3of diameters, the contribution of the portion of active region76resting on semi-polar planes in the general radiation emitted by active region76is predominating over the contribution of the portion of active region76resting on a c plane, which results in a stagnation of the central wavelength of the emitted radiation.

ConsideringFIG.1again, according to an embodiment, each display pixel of optoelectronic device10comprises at least three types of light-emitting diodes. According to an embodiment, the light-emitting diodes of the first type, for example comprising wires20and heads26, are adapted to emitting a first radiation at a first central wavelength. The light-emitting diodes of the second type, for example comprising wires22and heads28, are adapted to emitting a second radiation at a second central wavelength. The light-emitting diodes of the third type, for example comprising wires24and heads30, are adapted to emitting a third radiation at a third central wavelength. The first, second, and third central wavelengths are different.

According to an embodiment, the first wavelength corresponds to green light and is in the range from 510 nm to 550 nm. According to an embodiment, the first diameter D1varies from 80 nm to 150 nm. According to an embodiment, the second wavelength corresponds to red light and is in the range from 600 nm to 720 nm. According to an embodiment, the second diameter D2varies from 200 nm to 350 nm. According to an embodiment, the third wavelength corresponds to blue light and is within the range from 430 nm to 490 nm. According to an embodiment, the third diameter D3varies from 370 nm to 500 nm. Advantageously, as appears fromFIG.3, beyond a diameter equal to approximately 400 nm, the wavelength of the radiation emitted by active region76is little sensitive to the wire diameter.

According to an embodiment, each display pixel Pix comprises light-emitting diodes of a fourth type, the light-emitting diodes of the fourth type being adapted to emitting a fourth radiation at a fourth wavelength. The first, second, third, and fourth wavelengths may be different. According to an embodiment, the fourth wavelength corresponds to yellow light and is in the range from 570 nm to 600 nm, or to cyan and is in the range from 490 nm to 510 nm, or generally to any other color than the first, second, and third radiations.

According to an embodiment, for each display pixel, the elementary light-emitting diodes having wires of same diameter have a common electrode and, when a voltage is applied between conductive layer18and conductive layer42,44, or46, a light radiation is emitted by the active areas of these elementary light-emitting diodes.

In the present embodiment, the electromagnetic radiation emitted by each light-emitting diode escapes from optoelectronic device12through surface17. Preferably, each conductive layer42,44,46is reflective and advantageously enables to increase the proportion of the radiation emitted by the light-emitting diodes which escapes from optoelectronic device10through surface17.

Optoelectronic chip12and control chip14being stacked, the lateral bulk of optoelectronic device10is decreased. According to an embodiment, the lateral dimension of a display pixel, measured perpendicularly to the wire axes, is smaller than 5 μm, preferably smaller than 4 μm, for example, equal to approximately 3 μm. Further, optoelectronic chip12may have the same dimensions as control chip14. Thereby, the compactness of optoelectronic device10may advantageously be increased.

Conductive layer18is capable of biasing the active areas of heads26,28,30and of giving way to the electromagnetic radiation emitted by the light-emitting diodes. The material forming conductive layer18may be a transparent conductive material such as graphene or a transparent conductive oxide (TCO), particularly indium tin oxide (ITO), zinc oxide, doped or not with aluminum, or with gallium, or with boron, or silver nanowires. As an example, conductive layer18has a thickness in the range from 20 nm to 500 nm, preferably from 20 nm to 100 nm.

Conductive layer38, conductive layers42,44,46,48, and conductive pads52,54,56,58may be made of metal, for example, of aluminum, silver, platinum, nickel, copper, gold, or ruthenium, or of an alloy comprising at least two of these compounds, particularly the PdAgNiAu alloy or the PtAgNiAu alloy. Conductive layer38may have a thickness in the range from 100 nm to 3 μm. Conductive portions42,44,46,48may have a thickness in the range from 100 nm to 2 μm. The minimum lateral dimension, in a plane perpendicular to surface17, is in the range from 150 nm to 1 μm, for example, approximately 0.25 μm. Conductive pads52,54,56,58may have a thickness in the range from 0.5 μm to 2 μm.

Each of insulating layers16,32,34, and50is made of a material selected from the group comprising silicon oxide (SiO2), silicon nitride (SixNy, where x is approximately equal to 3 and y is approximately equal to 4, for example, Si3N4), silicon oxynitride (particularly of general formula SiOxNy, for example, Si2ON2), hafnium oxide (HfO2), titanium oxide (TiO2), or aluminum oxide (Al2O3). Layer34and/or layer32may further be made of an organic insulating material, for example, made of parylene or of benzocyclobutene (BCB). Insulating layer16may have a maximum thickness in the range from 100 nm to 5 μm. Insulating layers32and34may have a maximum thickness in the range from 0.5 μm to 2 μm. Insulating layer50may have a maximum thickness in the range from 0.5 μm to 2 μm.

Each wire20,22,24may have a semiconductor structure elongated along an axis substantially perpendicular to surface17. Each wire20,22,24may have a generally cylindrical shape with a cross-section that may have different shapes, such as, for example, an oval, circular, or polygonal shape, particularly triangular, rectangular, square, or hexagonal. The axes of two adjacent wires20,22,24may be distant by from 100 nm to 3 μm and preferably from 200 nm to 1.5 μm. The height of each wire20,22,24may be in the range from 150 nm to 10 μm, preferably from 200 nm to 1 μm, more preferably from 250 nm to 750 nm. The mean diameter of each wire20,22,24may be in the range from 50 nm to 10 μm, preferably from 100 nm to 2 μm, more preferably from 120 nm to 1 μm.

According to an embodiment, wires20,22,24are simultaneously formed by MOCVD from a seed layer. The growth conditions in the reactor are adapted to favor the preferential growth of each wire20,22,24along its axis C. This means that the growth speed of a wire along axis C is much greater, preferably by at least one order of magnitude, than the growth speed of the wire along a direction perpendicular to axis C. In an example, the method may comprise the injection into a reactor of a precursor of a group-III element and of a precursor of a group-V element. Examples of precursors of group-III elements are trimethylgallium (TMGa), triethylgallium (TEGa), trimethylindium (TMIn), or trimethylaluminum (TMAl). Examples of precursors of group-V elements are ammonia (NH3), tributylphosphate (TBP), arsine (AsH3), or dimethylhydrazine (UDMH). Some of the precursor gases may be generated by using a water mixer and a carrier gas.

According to an embodiment, the temperature in the reactor is in the range from 900° C. to 1,065° C., preferably in the range from 1,000° C. to 1,065° C., in particular1,050° C. According to an embodiment, the pressure in the reactor is in the range from 50 Torr (approximately 6.7 kPa) to 200 Torr (approximately 26.7 kPa), in particular 100 Torr (approximately 13.3 kPa). According to an embodiment, the flow rate of the precursor of the group-III element, for example, TEGa, is in the range from 500 sccm to 2,500 sccm, in particular, 1,155 sccm. According to an embodiment, the flow rate of the precursor of the group-V element, for example NH3, is in the range from 65 sccm to 260 sccm, in particular 130 sccm. According to an embodiment, the ratio of the flow rate of the precursor gas of the group-V element injected into the reactor to the flow rate of the precursor gas of the group-III element injected into the reactor, called V/III ratio, is in the range from 5 to 15. The carrier gases may include N2and H2. According to an embodiment, the percentage of hydrogen injected into the reactor is in the range from 3% to 15% by weight, in particular 5% by weight, with respect to the total mass of the carrier gases. The obtained growth speed of wire34may be in the range from 1 μm/h to 15 μm/h, in particular 5 μm/h.

A precursor for the dopant may be injected into the reactor. For example, when the dopant is Si, the precursor may be silane (SiH4). The flow rate of the precursor may be selected to target an average dopant concentration in the range from 5*1018to 5*1019atoms/cm3, in particular 1019atoms/cm3.

In another embodiment, semiconductor layer70, when present, is grown on each wire by MBE. According to an embodiment, for the MBE growth of semiconductor layer70, the temperature in the reactor is in the range from 800° C. to 900° C. According to an embodiment, the pressure in the reactor is in the range from 3*10−8Torr (approximately 4*10−3mPa) to 5*10−5Torr (approximately 6.7 mPa). According to an embodiment, a plasma is created with an RF power between 300 W and 600 W, for example, 360 W. According to an embodiment, the temperature of the solid source of the group-III element, for example, Ga, is in the range from 800° C. to 1,000° C., particularly 850° C. According to an embodiment, the flow rate of the precursor gas of the group-V element, for example, N2, is in the range from 0.5 sccm to 5 sccm, in particular 1.5 sccm.

A precursor for the dopant may be injected into the reactor. For example, when the dopant is Si, the precursor may be silane (SiH4). The flow rate of the precursor may be selected to target an average dopant concentration in the range from 5*1018to 2*1019atoms/cm3, in particular 1019atoms/cm3.

According to an embodiment, each layer of active region76is grown by MBE. In an embodiment, the MOCVD and MBE steps are carried out in different reactors. In an embodiment, the method may use for the MBE a solid/gaseous source precursor for the group-III element and for the group-V element. According to an embodiment, a solid source may be used when the group-III element is Ga and a gaseous or plasma precursor may be used when the group-V element is N. According to an embodiment, a beam of active nitrogen is supplied by a DC plasma source. In this source, excited neutral nitrogen molecules are formed in a region devoid of electric field and are accelerated towards the substrate by the pressure gradient with the vacuum chamber.

The forming of certain layers of active region76, in particular quantum wells86, may comprise injecting into the reactor a solid/gaseous precursor of an additional element. According to an embodiment, a solid source may be used when the additional group-III element is In, Ga, or Al. The speed of incorporation of the additional element into the active region76particularly depends on the lateral dimensions of active regions76, on the distance between wires20,22,24, and on the height of active regions76with respect to the support having wires20,22,24extending therefrom.

A dopant may be injected into the reactor. For example, when the dopant is made of Si, a solid source may be used. According to an embodiment, the temperature of the solid source of the dopant element is in the range from 1,000° C. to 1,200° C.

According to an embodiment, for the MBE growth of each barrier layer88, the temperature in the reactor is in the range from 570° C. to 640° C., in particular 620° C. According to an embodiment, the pressure in the reactor is in the range from 3*10−8Torr (approximately 4*10−3mPa) to 5*10−5Torr (approximately 6.7 mPa). According to an embodiment, a plasma is created with an RF power between 300 W and 600 W, for example, 360 W. According to an embodiment, the temperature of the solid source of the group-III element, for example, Ga, is in the range from 850° C. to 950° C., particularly 895° C. According to an embodiment, the flow rate of the precursor gas of the group-V element, for example, N2, is in the range from 0.5 sccm to 5 sccm, in particular 1.5 sccm.

According to an embodiment, for the MBE growth of each quantum well86, the temperature in the reactor is in the range from 570° C. to 640° C., in particular 620° C. According to an embodiment, the pressure in the reactor is in the range from 3*10−8Torr (approximately 4*10−3mPa) to 5*10−5Torr (approximately 6.7 mPa). According to an embodiment, a plasma is created with an RF power between 300 W and 600 W, for example, 360 W. According to an embodiment, the temperature of the solid source of the group-III element, for example, Ga, is in the range from 850° C. to 950° C., particularly 895° C. According to an embodiment, the temperature of the solid source of the additional element, for example, In, is in the range from 750° C. to 900° C., particularly 790° C. According to an embodiment, the flow rate of the precursor gas of the group-V element, for example, N2, is in the range from 0.5 sccm to 5 sccm, in particular 1.5 sccm.

According to an embodiment, each layer of semiconductor stack78is grown by MBE. According to an embodiment, semiconductor layer80is grown with substantially a c-plane orientation. According to an embodiment, for the MBE growth of electron-blocking layer82, the temperature in the reactor is in the range from 700° C. to 900° C., in particular 800° C. According to an embodiment, the pressure in the reactor is in the range from 3*10−8Torr (approximately 4*10−3mPa) to 5*10−5Torr (approximately 6.7 mPa). According to an embodiment, a plasma is created with an RF power between 300 W and 600 W, for example, 360 W. According to an embodiment, the temperature of the solid source of the group-III element, for example, Ga, is in the range from 850° C. to 950° C., particularly 905° C. According to an embodiment, the temperature of the solid source of the additional element, for example, Al, is in the range from 1,000° C. to 1,100° C., particularly 1,010° C. According to an embodiment, the flow rate of the precursor gas of the group-V element, for example, N2, is in the range from 0.5 sccm to 5 sccm, in particular 1.5 sccm. A dopant may be injected into the reactor. For example, when the dopant is Mg, a solid source may be used. According to an embodiment, the temperature of the solid source of the dopant element is in the range from 150° C. to 350° C., in particular 190° C.

FIGS.7A to7Nare partial simplified cross-section views of the structures obtained at successive steps of another embodiment of a method of manufacturing the optoelectronic device10shown inFIG.1.

FIG.7Ashows the structure obtained after the steps of:

forming a support100corresponding to the stacking, from bottom to top inFIG.7A, of a substrate101, of at least one nucleation layer, also called seed layer, two nucleation layers102and103being shown as an example inFIG.7A, of an electrically-insulating layer104, and of an electrically-insulating layer106on insulating layer104, insulating layers104,106being made of different materials;

forming first openings108in insulating layers104and106to expose portions of nucleation layer103at the desired locations of first wires20, the diameter of the first openings108substantially corresponding to the diameter of first wires20, second openings110in insulating layers104and106to expose portions of nucleation layer103at the desired locations of second wires22, the diameter of second openings110substantially corresponding to the diameter of the second wires22, and third openings112in insulating layers104and106to expose portions of nucleation layers103at the desired locations of third wires24, the diameter of third openings112substantially corresponding to the diameter of third wires24;simultaneously growing wires20,22,24by MOCVD from nucleation layer103in openings108,110,112;simultaneously growing heads26,28,30by MBE on wires20,22,24, each head26,28,30comprising active region76and semiconductor stack78.

As a variation, insulating layers104,106may be replaced with a single insulating layer.

Substrate101may correspond to a monoblock structure or may correspond to a layer covering a support made of another material. Substrate101is preferably a semiconductor substrate, for example, a substrate made of silicon, of germanium, of silicon carbide, of a III-V compound, such as GaN or GaAs, or a ZnO substrate, or a conductive substrate, for example, a substrate made of a metal or a metal alloy, particularly copper, titanium, molybdenum, a nickel-based alloy, and steel. Preferably, substrate101is a single-crystal silicon substrate. Preferably, it is a semiconductor substrate compatible with manufacturing methods implemented in microelectronics. Substrate101may correspond to a multilayer structure of silicon-on-insulator type, also called SOI. Substrate101may be heavily doped, lightly-doped, or non-doped.

Nucleation layers102,103are made of a material which favors the growth of wires20,22,24. The material forming each nucleation layer102,103may be a metal, a metal oxide, a nitride, a carbide, or a boride of a transition metal of column IV, V, or VI of the periodic table of elements or a combination of these compounds and preferably a nitride of a transition metal of column IV, V, or VI of the periodic table of elements, or a combination of these compounds. As an example, each seed layer102,103may be made of aluminum nitride (AlN), of aluminum oxide (Al2O3), of boron (B), of boron nitride (BN), of titanium (Ti), of titanium nitride (TiN), of tantalum (Ta), of tantalum nitride (TaN), of hafnium (Hf), of hafnium nitride (HfN), of niobium (Nb), of niobium nitride (NbN), of zirconium (Zr), of zirconium borate (ZrB2), of zirconium nitride (ZrN), of silicon carbide (SiC), of tantalum carbide nitride (TaCN), of magnesium nitride in MgxNyform, where x is approximately equal to 3 and y is approximately equal to 2, for example, magnesium nitride in Mg3N2form. Each nucleation layer102,103has, for example, a thickness in the range from 1 nm to 100 nm, preferably in the range from 10 nm to 30 nm.

Each of insulating layers104and106is made of a material selected from the group comprising silicon oxide (SiO2), silicon nitride (SixNy, where x is approximately equal to 3 and y is approximately equal to 4, for example, Si3N4), silicon oxynitride (particularly of general formula SiOxNy, for example, Si2ON2), hafnium oxide (HfO2), or aluminum oxide (Al2O3). According to an embodiment, insulating layer104is made of silicon oxide and insulating layer106is made of silicon nitride. The thickness of each insulating layer104,106is in the range from 10 nm to 100 nm, preferably from 20 nm to 60 nm, particularly equal to approximately 40 nm.

The growth method of wires20,22,24is the MOCVD method such as previously described. The height of each wire20,22,24at the end of the growth step may be in the range from 250 nm to 15 μm, preferably from 500 nm to 5 μm, more preferably from 1 μm to 3 μm. The height of the first wires20is different from the height of the second wires22and from the height of the third wires24. The height of wires20,22,24particularly depends on the wire diameter and on the distance between wires. According to an embodiment, the height of the first wires20is greater than the height of the second wires22and the height of the second wires22is greater than the height of the third wires24.

Each seed layer102,103and each insulating layer104,106may be deposited as an example by plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), sub-atmospheric chemical vapor deposition (SACVD), CVD, physical vapor deposition (PVD), or atomic layer deposition (ALD).

FIG.7Bshows the structure obtained after having deposited a dielectric layer113over all the wires20,22,24and over insulating layer106between wires20,22,24.

Dielectric layer113may be made of the same material as insulating layer106. According to an embodiment, the minimum thickness of layer113is greater than the sum of the height of the smallest wires20,22,24and of the height of the associated head26,28,30. Preferably, the minimum thickness of layer113is greater than the sum of the height of the largest wires20,22,24and of the height of the associated head26,28,30.

As an example, the thickness of dielectric layer113is in the range from 250 nm to 15 μm, preferably from 300 nm to 5 μm, for example, equal to approximately 2 μm. Insulating layer113may be formed by the same methods as those used to form insulating layers104,106.

FIG.7Cshows the structure obtained after having thinned and planarized insulating layer113and a portion of heads26,28,30to delimit a planar surface114at a height of insulating layer106for example in the range from 150 nm to 10 μm. The etching is for example a CMP (Chemical-Mechanical Planarization). The presence of insulating layer113between wires20,22,24enables to implement a CMP-type etch method, which would be difficult or even impossible if only the wires were present. After this step, all wire-head assemblies20-26,22-28,24-30have the same height. The etching of insulating layer113and of a portion of wires20,22,24may be carried out in a plurality of steps. As a variant, the step of thinning and of planarization of insulating layer83and of a portion of heads26,28,30may not be present when the wire-head assemblies20-26,22-28,24-30have substantially the same height.

FIG.7Dshows the structure obtained after having fully removed dielectric layer113to expose insulating layer106and wire-head assemblies20-26,22-28,24-30. Insulating layer106may then play the role of an etch stop layer during the etching of dielectric layer113. The removal of dielectric layer113may be performed by a wet etching. As a variation, the etching of dielectric layer113may be only partial, a residual layer being kept on insulating layer106.

FIG.7Eshows the structure obtained after the steps of:forming of insulating layer32;forming of insulating layer34; andetching or thinning insulating layer34across part of its thickness to delimit a substantially planar surface116.

Insulating layer32may be formed by conformal deposition, for example, by LPCVD. The method of forming insulating layer32is preferably carried out at a temperature lower than 700° C. to avoid damaging the active regions of the light-emitting diodes. Further, an LPCVD-type method enables to obtain a good filling between wires20,22,24. The deposited thickness of insulating layer32may be in the range from 100 nm to 1 μm, for example, approximately 500 nm. Insulating layer34may for example be formed by conformal deposition, for example, by PECVD. The deposited thickness of insulating layer34may be greater than or equal to 2 μm. The partial etching of insulating layer34may be performed by CMP. The stopping of the etching may be performed in insulating layer34, as shown inFIG.7E, or insulating layer32, but in any case before exposing heads26,28,30.

FIG.7Fshows the structure obtained after having etched insulating layers32,34, to expose the upper surfaces of heads26,28,30. The etching is for example an etching of reactive ion etching type (RIE) or an inductively coupled plasma etching (ICP). Since heads26,28,30may have different dimensions, some heads26,28,30may be more exposed than others. Heads26,28,30are not etched at this step. The etching is preferably an anisotropic etching. Portions, not shown, of layer32may be kept on the lateral walls of heads26,28,30. The layer located at the top of heads26,28,30plays the role of an etch stop layer. According to an embodiment, on forming of heads26,28,30, an additional layer is added at the top of heads26,28,30to play the role of an etch stop layer. It may be an AlN layer.

FIG.7Gshows the structure obtained after the following steps:when etch stop layers are present on heads26,28,30, removal of the etch stop layers;deposition of a metal layer on the structure shown inFIG.7E, for example, by cathode sputtering, for example having a 0.5-μm thickness;etching of the metal layer to delimit conductive layers42,44,46,48.

When the etch stop layers on heads26,28,30are made of AN, they may be removed by an etching of tetramethylammonium hydroxide type (TMAH). Before the forming of conductive layers42,44,46,48, separate metal portions may be formed over the entire structure. This may be performed by the deposition of a metal layer having a 1-nm thickness, for example, nickel or platinum, and a thermal anneal step, for example, at a 550° C. temperature, which results in the forming of the separate portions.

FIG.7Hshows the structure obtained after the steps of:depositing insulating layer50on the structure shown inFIG.7G; andforming conductive pads52,54,56,58, for example, made of copper.

FIG.7Ishows the structure obtained after having bonded control chip14to optoelectronic chip12. The bonding of control chip14to optoelectronic chip12may be performed by using inserts such as connection microballs, not shown. As a variation, the bonding of control chip14to the optoelectronic chip may be performed by direct bonding, without using inserts. The direction bonding may comprise a direct metal-to-metal bonding of metal areas, particularly the conductive pads62, of control chip14, and of metal areas, particularly the conductive pads52,54,56,58, of optoelectronic chip12, and a dielectric-to-dielectric bonding of dielectric areas, particularly the insulating layer50of control chip14, and of dielectric areas, particularly the insulating layer50, of optoelectronic chip12. The bonding of control chip14to optoelectronic chip12may be performed by a thermocompression method where optoelectronic chip12is pressed against control chip14with the application of a pressure and of a heating.

FIG.7Jshows the structure obtained after the steps of:removal of substrate101;removal of seed layers102,103;removal of insulating layers104and106;partial etching of insulating layer32, of insulating layer34, and of wires20,22,24to delimit a substantially planar surface118.

The removal of substrate101may be performed by grinding and/or wet etching. The removal of seed layers102,103, of insulating layer32, of insulating layer34, and of wires20,22,24may be performed by wet etching, dry etching, or by CMP. Insulating layer104or106may play the role of an etch stop layer during the etching of seed layer103.

FIG.7Kshows the structure obtained after having formed conductive layer18on surface118, for example, by depositing a TCO layer over the entire surface118, for example having a 50-nm thickness, and by etching this layer by photolithography techniques to only keep TCO layer18.

FIG.7Lshows the structure obtained after having etched opening36in insulating layer34across the entire thickness of insulating layer34to expose conductive layer48. This may be carried out by photolithography techniques.

FIG.7Mshows the structure obtained after having formed conductive layer38in opening36and on surface118in contact with conductive layer18. This may be performed by depositing a stack of conductive layers, for example, of type Ti/TiN/AlCu, over the entire structure on the side of surface118, and by etching this stack by photolithography techniques to only keep conductive layer38.

FIG.7Nshows the structure obtained after having formed, on conductive layer18, the insulating layer16delimiting surface17. It for example is a SiON layer deposited by PECVD with a 1-μm thickness.

An additional step of forming raised areas on surface17, also called texturing step, may be provided to increase the extraction of light.

The decrease in the wire height from the back side may be carried out by a CMP-type method, as previously described, or by any other dry etching or wet etching method. The obtained height of the wires, particularly made of GaN, may be selected to increase the extraction of light from the foot of the wire by optical interactions within the wire itself. Further, this height may be selected to favor the optical coupling between the different wires and thus to increase the collective emission of an assembly of wires.

Various embodiments and variants have been described. Those skilled in the art will understand that certain features of these various embodiments and variants may be combined, and other variants will occur to those skilled in the art. In particular, although, in the previously-described embodiments, the optoelectronic device comprises two chips bonded to each other, it is clear that the optoelectronic device may comprise a single chip, the electronic light-emitting diode control circuit being formed in integrated fashion with the light-emitting diodes. Finally, the practical implementation of the described embodiments and variations is within the abilities of those skilled in the art based on the functional indications given hereabove.