Structures and methods for determining TDDB reliability at reduced spacings using the structures

A structure for TDDB measurement, a method determining TDDB at reduced spacings. The structure includes an upper dielectric layer on a top surface of a lower dielectric layer, a bottom surface of the upper dielectric layer and the top surface of the lower dielectric layer defining an interface; a first wire formed in the lower dielectric layer; a second wire formed in the upper dielectric layer; and wherein a distance between the first wire and the second wire measured in a direction parallel to the interface is below the lithographic resolution limit of the fabrication technology.

TECHNICAL FIELD

The present invention relates to the field of time dependent dielectric breakdown (TDDB) of integrated circuit reliability; more specifically, it relates to structures and methods for determining TDDB reliability at reduced spacings using the structures.

BACKGROUND

As the dimensions of integrated circuit features decreases, determining TDDB behavior (which is critical to integrated circuit reliability, at wire-to-wire spacings below the minimum spacing allowed by the lithographical process used to define wires in a same wiring level) using current measurement structures and methods have become more unreliable. Accordingly, there exists a need in the art to mitigate the deficiencies and limitations described hereinabove.

BRIEF SUMMARY

A first aspect of the present invention is a structure, comprising: an upper dielectric layer on a top surface of a lower dielectric layer, a bottom surface of the upper dielectric layer and the top surface of the lower dielectric layer defining an interface; a first wire formed in the lower dielectric layer; a second wire formed in the upper dielectric layer; and wherein a distance between the first wire and the second wire measured in a direction parallel to the interface is below a minimum allowed wire-to-wire spacing in the lower dielectric layer.

A second aspect of the present invention is a method, comprising: providing two or more TDDB test structures, each TDDB test structure comprising: an upper dielectric layer on a top surface of a lower dielectric layer, a bottom surface of the upper dielectric layer and the top surface of the lower dielectric layer defining an interface; a first conductor formed in the lower dielectric layer; a second conductor formed in the upper dielectric layer; and wherein a distance between the first conductor and the second conductor measured in a direction parallel to the interface is below the resolution limit of the lithographical process used to define conductor-to conductor distanced in the lower dielectric layer; each of the two or more TDDB test structure having a different first conductor to second conductor distance; stressing the TDDB test structures at a preselected temperature with an electric field applied between the first and second conductors, measuring a leakage current between the first and second conductors, and recording a time for each TDDB test structure of the two or more TDDB test structures to exceed a preselected leakage current value; and extrapolating a time to fail of a TDDB test structure having a first conductor to second conductor distance that is less than the smallest distance of the different first conductor to second conductor distances.

These and other aspects of the invention are described below.

DETAILED DESCRIPTION

Time dependent dielectric breakdown is a breakdown that can occur along an interface (rather than through the bulk dielectric) of two dielectric layers between two conductors spaced apart. TDDB results in a TDDB leakage current. TDDB leakage current is an indicator of adjacent wire-to-wire leakage that can occur during or as a result of normal operation of the integrated circuit over its lifetime and is a reliability indicator.

Dmin is defined as the minimum allowed designed wire-to-wire spacing in the same wiring level and is the lithographic resolution limit of the fabricating technology. MinIns is defined as the minimum conductor-to-conductor (e.g., wire-to wire or wire-to-via) spacing in the same wiring level that can actually occur in a physical integrated circuit due to process variations.

The TDDB test structures of the embodiments of the present invention utilize vias or via bars of an upper wire in an upper dielectric layer placed within a horizontal distance of a lower wire in a lower and abutting dielectric layer, wherein the distance is below the lithographic resolution limit of the fabricating technology.

A damascene process is one in which wire trenches or via openings are formed in a dielectric layer, an electrical conductor of sufficient thickness to fill the trenches is formed in the trenches and on a top surface of the dielectric. The topographic dimensions of the trenches are defined by a lithographic/etch process. A chemical-mechanical-polish (CMP) process is performed to remove excess conductor and make the surface of the conductor co-planar with the surface of the dielectric layer to form damascene wires (or damascene vias). When only a trench and a wire (or a via opening and a via) is formed the process is called single-damascene.

A via first dual-damascene process is one in which via openings are formed through the entire thickness of a dielectric layer followed by formation of trenches part of the way through the dielectric layer in any given cross-sectional view. A trench first dual-damascene process is one in which trenches are formed part way through the thickness of a dielectric layer followed by formation of vias inside the trenches the rest of the way through the dielectric layer in any given cross-sectional view. All via openings are intersected by integral wire trenches above and by a wire trench below, but not all trenches need intersect a via opening. An electrical conductor of sufficient thickness to fill the trenches and via opening is formed on a top surface of the dielectric and a CMP process is performed to make the surface of the conductor in the trench co-planar with the surface of the dielectric layer to form dual-damascene wires and dual-damascene wires having integral dual-damascene vias.

When viewed from the top, a via has a width about equal to its length (e.g., a square). When viewed from the top, a via that has a length of at least about 1.5 times greater than its width (e.g., a rectangle) the via is called a via bar. The term via is defined as a via that has a width about equal to its length. The term via bar is defined as a via bar that has a length of at least about 1.5 times greater than its width. Those skilled in the art will recognize that the corners of vias and via bars may become rounded when formed. Vias may actually become circular when formed.

Vias may be partially landed on a wire in the abutting lower dielectric layer or un-landed (i.e., not landed) on any wire formed in the abutting lower dielectric layer. As opposed to a fully landed via where the entire bottom surface of the via touches a top surface of the lower wire, in a partially landed via a less than whole portion of the bottom surface of the via touches the top surface of the lower wire.

Integrated circuits comprise various devices, such as field effect transistors (FETs) formed in the substrate and wires formed in wiring levels above the substrate that interconnect the devices into circuits. There are multiple wiring levels, each comprised of a wire formed in an interlevel dielectric layer. The upper wires are connected to immediately lower adjacent wires by vias. Wiring levels are identified using the designation X where X is a positive integer from 1 to N. The wiring levels are identified from the wiring level closest to the substrate to the wiring level furthest from the substrate as 1 through N where 1 is the first or lowermost wiring level and N is the last or uppermost wiring level. Wires, vias and via bars are similarly designated. A wire in the X wiring level is designated as an MX wire. A via in the X wiring level is designated as a VX−1 via. A via bar in the X wiring level is designated as a VX−1 via bar. Note that there are no V0 vias or via bars. When a wire in an upper wiring level is designated MX, then a wire in an immediately lower wiring level is designated MX−1. Likewise, when a wire in a lower wiring level is designated MX, then a wire in an immediately higher wiring level is designated MX+1. For a first wiring level (X=1), the wire is M1 and there are no “V0” vias or via bars as generally the connection from M1 to devices below M1 is made through separately formed contacts in a contact layer designated CA. For a second wiring level (X=2), the wire is M2 and the vias or via bars are V1. For a third wiring level (X=3), the wire is M3 and the vias or via bars are V2. All wires described in the monitor structures described infra are either single-damascene wires (for X=1) or dual-damascene wires for X=2 or greater.

Similar structures in the various embodiments will use the same reference numbers in order to emphasize the similarities and differences between embodiments.

FIGS. 1A through 1Eillustrate a first TDDB test structure according to the present invention.FIG. 1Ais a top view,FIG. 1Bis a cross-sectional view through line1B-1B ofFIG. 1AandFIG. 1Cis a cross-sectional view through line1C-1C ofFIG. 1A. InFIG. 1A, a TDDB test structure100A includes a first MX wire105A, a second MX wire105B, a first MX+1 wire110A and a second MX+1 wire110B. First MX+1 wire110A includes multiple integrally formed VX vias115A that are in direct physical and electrical contact with first MX wire105A. Second MX+1 wire110B includes multiple integrally formed VX vias115B that are in direct physical and electrical contact with first MX wire105A. First MX wire105A has fingers111and112that are interdigitated with fingers116and117of second MX wire105B. Finger of116of second MX wire105B is spaced a distance Dmin from finger112of first MX wire105A. Finger of112of first MX wire105A is spaced distance Dmin from finger117of second MX wire105B. VX vias115A are not fully landed on first MX wire105A (they are offset towards the fingers of second MX wire105B) and are spaced a distance Dcrit from the adjacent finger of second MX wire105B. VX vias115B are not fully landed on first MX wire105A (they are offset towards the adjacent finger of second MX wire105B) and are spaced a distance Dcrit from the adjacent finger of second MX wire105B.

FromFIGS. 1B and 1C, it can be seen that MX wires105A and105B are formed in a lower dielectric layer120and MX+1 wire110A (also wire110B, not shown) and VX vias115A (also vias115B) are formed in an upper dielectric layer125. InFIG. 1C, a top surface127of second MX wire105B is coplanar with bottom surfaces128of VX vias115A. Dcrit is the distance between second MX wire105B and VX vias115A along the interface between lower dielectric layer120and upper dielectric layer125. The distance between second MX wire105B and VX vias115B (not shown inFIG. 1C) along the interface between lower dielectric layer120and upper dielectric layer125is also Dcrit.

The dielectric materials and electrical conductors of wires, vias and via bars of the TDDB structures are the same as the normal materials used in wiring the active devices.

Exemplary materials for lower dielectric layer120and upper dielectric layer125include but are not limited to silicon dioxide (SiO2), silicon nitride (Si3N4), silicon carbide (SiC), silicon oxy nitride (SiON), silicon oxy carbide (SiOC) plasma-enhanced silicon nitride (PSiNx) or NBLock (SiC(N,H)). Exemplary low K (dielectric constant) materials having a relative permittivity of about 4 or less, for lower dielectric layer120and upper dielectric layer125include but are not limited to hydrogen silsesquioxane polymer (HSQ), methyl silsesquioxane polymer (MSQ), polyphenylene oligomer, methyl doped silica or SiOx(CH3)yor SiCxOyHyor SiOCH, organosilicate glass (SiCOH), and porous SiCOH, fluorinated SiO2(FSG) and porous SiO2.

When dielectric layers120and125comprise multiple dielectric layers, the interface of interest is the interface between the uppermost dielectric layer of lower dielectric layer120and the lowermost dielectric layer of upper dielectric layer125as illustrated inFIG. 12, which is exemplary for all embodiments of the present invention. InFIG. 12, upper dielectric layer125A comprises a bottom dielectric layer132and a top dielectric layer133. The interface of interest is the interface between lower dielectric layer120and bottom dielectric layer132. Examples of materials for bottom dielectric layer132include, but are not limited to, Si3N4, SiC and SiC(N,H). Examples of materials for top dielectric layer133include nonporous SiO2and low K (dielectric constant) materials having a relative permittivity of about 4 or less, examples of which include but are not limited to HSQ, MSQ, polyphenylene oligomer, SiOx(CH3)y, SiCxOyHy, SiOCH, SiCOH, porous SiCOH, porous SiO2and FSG.

Examples of electrically conductive materials for wires, vias and via-bars of the embodiments of the present invention include aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), titanium nitride (TiN), tantalum (Ta) and tantalum nitride (TaN) and particularly wires (and the integral vias or via bars) comprising a copper core and a liner of TaN/Ta or TiN/Ti.

FIG. 1Dillustrates a variation ofFIG. 1Cwherein VX vias115A extend into lower dielectric layer120so top surface127of second MX wire105B is not coplanar with bottom surfaces128of VX vias115A. However, Dcrit is still measured along the interface between lower dielectric layer120and upper dielectric layer125.FIG. 1Eillustrates a variation of first and second MX+1 wires110A and110B. InFIGS. 1A and 1C, the widths of first MX+1 wire110A and VX vias115A are the same, while inFIG. 1Ethe width of first MX+1 wire110A is greater than the widths of VX vias115A. Dcrit is still measured along the interface between lower dielectric layer120and upper dielectric layer125.

Dmin and MinIns have been defined supra. For 22 nm technology, Dmin is about 40 nm and MinIns is about 12 nm and values that can be obtained for Dcrit range from about 40 nm to about 20 nm. In other words, Dcrit can range between about Dmin and about 0.5×Dmin or less. In order to estimate the TDDB behavior of an integrated circuit at MinIns, a series of measurement structures100A (and100B,100C,100D,100E and100F described infra) with values of Dcrit ranging from about Dmin to about 0.5×Dmin or less are fabricated. The structures are stressed, and the data extrapolated to MinIns. Also, there may be sets of measurement structures built in different pairs of adjacent wiring levels and Dmin and MinIns may vary from set to set.

FIGS. 2A through 2Eillustrate a second TDDB test structure according to the present invention.FIGS. 2A through 2Fare similar toFIGS. 1A through 1Eexcept vias115A and115B ofFIGS. 1A through 1Eare replaced with via bars130A and130B respectively.FIG. 2Ais a top view,FIG. 2Bis a cross-sectional view through line2B-2B ofFIG. 2AandFIG. 2Cis a cross-sectional view through line2C-2C ofFIG. 2A. InFIG. 2A, a TDDB test structure100B includes a first MX wire105A, a second MX wire105B, a first MX+1 wire110A and a second MX+1 wire110B. First MX+1 wire110A includes an integrally formed VX via bar130A that is in direct physical and electrical contact with first MX wire105A. Second MX+1 wire110B includes an integrally formed VX via bar130B that is in direct physical and electrical contact with first MX wire105A. First MX wire105A has fingers111and112that are interdigitated with fingers116and117of second MX wire105B. Finger of116of second MX wire105B is spaced a distance Dmin from finger112of first MX wire105A. Finger of112of first MX wire105A is spaced distance Dmin from finger117of second MX wire105B. VX via bar130A is not fully landed on first MX wire105A (it is offset towards the fingers of second MX wire105B) and is spaced a distance Dcrit from the adjacent finger of second MX wire105B. VX via bar130B is not fully landed on first MX wire105A (it is offset towards the adjacent finger of second MX wire105B) and are spaced distance Dcrit from the adjacent finger of second MX wire105B.

FromFIGS. 2B and 2C, it can be seen that MX wires105A and105B are formed in lower dielectric layer120and MX+1 wire110A (also wire110B, not shown) and VX via bar130A (also via bar130B) is formed in an upper dielectric layer125. InFIG. 2C, a top surface127of second MX wire105B is coplanar with a bottom surfaces128of VX via bar130A. Dcrit is the distance between second MX wire105B and VX via bar130A along the interface between lower dielectric layer120and upper dielectric layer125. The distance between second MX wire105B and VX via bar130B (not shown in FIG.2C) along the interface between lower dielectric layer120and upper dielectric layer125is also Dcrit.

FIG. 2Dillustrates a variation ofFIG. 2Cwherein VX via bar130A extends into lower dielectric layer120so top surface127of second MX wire105B is not coplanar with bottom surfaces128of VX via bar130A. However, Dcrit is still measured along the interface between lower dielectric layer120and upper dielectric layer125.FIG. 2Eillustrates a variation of first and second MX+1 wires110A and110B. InFIGS. 2A and 2C, the widths of first MX+1 wire110A and VX via bar130A are the same, while inFIG. 2Ethe width of first MX+1 wire110A is greater than the width of VX via bar130A. Dcrit is still measured along the interface between lower dielectric layer120and upper dielectric layer125.

FIGS. 3A through 3Eillustrate a third TDDB test structure according to the present invention.FIGS. 3A through 1Eare similar toFIGS. 1A through 1Eexcept MX wires105A and105B ofFIGS. 1A through 1Eare replaced with a single MX wire105, MX+1 wires110A and110B are replaced with a single MX+1 wire110, VX vias115A and115B are replaced by three sets of VX vias115and the VX vias115are un-landed.FIG. 3Ais a top view,FIG. 3Bis a cross-sectional view through line3B-3B ofFIG. 3AandFIG. 3Cis a cross-sectional view through line3C-3C ofFIG. 3A. InFIG. 3A, a TDDB test structure100C includes an MX wire105, an MX+1 wire110. MX+1 wire110includes multiple integrally formed VX vias115that are not in direct physical and electrical contact with any MX wire. MX wire105has fingers126and127that are interdigitated with fingers121,122and123of MX+1 wire110. Finger126of MX wire105is spaced a distance Dcrit from VX vias115of finger121of MX+1 wire110. Finger127of MX wire105is spaced a distance Dcrit from VX vias115of finger122of MX+1 wire110.

FromFIGS. 3B and 3C, it can be seen that MX wire105is formed in lower dielectric layer120and MX+1 wire110and VX vias115are formed in upper dielectric layer125. InFIG. 3C, a top surface133of MX wire105is coplanar with bottom surfaces134of VX vias115. Dcrit is the distance between MX wire105and VX vias115along the interface between lower dielectric layer120and upper dielectric layer125.

FIG. 3Eillustrates a variation ofFIG. 3Cwherein VX vias115extend into lower dielectric layer120so top surface133of MX wire105is not coplanar with bottom surfaces134of VX vias115. However, Dcrit is still measured along the interface between lower dielectric layer120and upper dielectric layer125.FIG. 3Eillustrates a variation of MX+1 wire110. InFIGS. 3A and 3C, the widths of MX+1 wire110and VX vias115are the same, while inFIG. 3Ethe width of MX+1 wire110is greater than the widths of VX vias115. Dcrit is still measured along the interface between lower dielectric layer120and upper dielectric layer125.

FIGS. 4A through 4Eillustrate a fourth TDDB test structure according to the present invention.FIGS. 4A through 4Eare similar toFIGS. 3A through 3Eexcept the three sets of MX vias115ofFIGS. 3A through 3Eare replaced with three VX via bars135and the VX via bars135are un-landed.FIG. 4Ais a top view,FIG. 4Bis a cross-sectional view through line4B-4B ofFIG. 4AandFIG. 4Cis a cross-sectional view through line4C-4C ofFIG. 4A. InFIG. 4A, a TDDB test structure100D includes MX wire105, MX+1 wire110. MX+1 wire110includes three integrally formed VX via bars135(one VX via bar on each of fingers121,122and123) that are not in direct physical and electrical contact with any MX wire. MX wire105has fingers126and127that are interdigitated with fingers121,122and123of MX+1 wire110. Finger126of MX wire105is spaced a distance Dcrit from VX via bar135of finger121of MX+1 wire110. Finger127of MX wire105is spaced a distance Dcrit from VX via bar135of finger122of MX+1 wire110.

FromFIGS. 4B and 4C, it can be seen that MX wire105is formed in lower dielectric layer120and MX+1 wire110and VX via bars135are formed in upper dielectric layer125. InFIG. 4C, a top surface133of MX wire105is coplanar with bottom surfaces136of VX via bars135. Dcrit is the distance between MX wire105and VX via bars135along the interface between lower dielectric layer120and upper dielectric layer125.

FIG. 4Dillustrates a variation ofFIG. 4Cwherein VX via bars135extend into lower dielectric layer120so top surface133of MX wire105is not coplanar with bottom surfaces136of VX via bars135. However, Dcrit is still measured along the interface between lower dielectric layer120and upper dielectric layer125.FIG. 4Eillustrates a variation of MX+1 wire110. InFIGS. 4A and 4C, the widths of MX+1 wire110and VX via bars135are the same, while inFIG. 4Ethe width of MX+1 wire110is greater than the widths of VX via bars135. Dcrit is still measured along the interface between lower dielectric layer120and upper dielectric layer125.

FIGS. 5A through 5Eillustrate a fifth TDDB test structure according to the present invention.FIG. 5Ais a top view,FIG. 5Bis a cross-sectional view through line5B-5B ofFIG. 5AandFIG. 5Cis a cross-sectional view through line5C-5C ofFIG. 5A. InFIG. 5A, a TDDB test structure100E includes a first serpentine MX wire140A, a second serpentine MX wire140B and a serpentine MX+1 wire145. MX+1 wire145includes a serpentine wire portion150and an integrally formed serpentine Via bar portion155that is partially landed on first MX wire140A along the entire length of VX via bar155. First MX wire140A is spaced distance Dmin from second MX wire140B along an entire length of second MX wire140B directly contacted by via bar portion155of MX+1 wire145. MX+1 wire145(including wire portion150and Via bar portion155) is offset toward second MX wire140B. The entire length of via bar portion155of MX+1 wire145is spaced a distance Dcrit from second MX wire140B.

FromFIGS. 5B and 5C, it can be seen that MX wire140A and140B are formed in lower dielectric layer120and MX+1 wire145(including wire portion150and via bar portion155) is formed in upper dielectric layer125. InFIG. 5C, a top surface157of second MX wire140B is coplanar with a bottom surface158of via bar portion155of MX+1 wire145. Dcrit is the distance between second MX wire140B and via bar portion155of MX+1 wire145along the interface between lower dielectric layer120and upper dielectric layer125. When dielectric layers120and125comprise multiple dielectric layers, the interface of interest is the interface between the uppermost dielectric layer of lower dielectric layer120and the lowermost dielectric layer of upper dielectric layer125.

FIG. 5Dillustrates a variation ofFIG. 5Cwherein Via bar portion155of MX+1 wire145extends into lower dielectric layer120so top surface157of second MX wire140B is not coplanar with bottom surface158of via bar portion155of MX+1 wire145. However, Dcrit is still measured along the interface between lower dielectric layer120and upper dielectric layer125.FIG. 5Eillustrates a variation of MX+1 wires145. InFIGS. 5A and 5C, the widths of wire portion150and via bar portion155of MX+1 wire145are the same, while inFIG. 5Ethe width of wire portion150is greater than the width of via bar portion155of MX+1 wire145. Dcrit is still measured along the interface between lower dielectric layer120and upper dielectric layer125.

FIGS. 6A through 6Eillustrate a sixth TDDB test structure according to the present invention.FIG. 6Ais a top view,FIG. 6Bis a cross-sectional view through line6B-6B ofFIG. 6AandFIG. 6Cis a cross-sectional view through line6C-6C ofFIG. 6A.FIGS. 6A through 6Eare similar toFIGS. 5A through 5Eexcept there is no first MX wire140A and consequently via bar portion155of MX+1 wire145is un-landed and second MX wire140A is now designated MX wire140. InFIG. 6A, a TDDB test structure100F includes serpentine MX wire140, and serpentine MX+1 wire145. MX+1 wire145includes serpentine wire portion150and integrally formed serpentine via bar portion155. MX+1 wire145(including wire portion150and Via bar portion155) is offset toward MX wire140. MX wire140is spaced distance Dcrit from via bar portion155of MX+1 wire145along the entire length of the via bar portion.

FromFIGS. 6B and 6C, it can be seen that MX wire140is formed in lower dielectric layer120and MX+1 wire145(including wire portion150and via bar portion155) is formed in upper dielectric layer125. InFIG. 6C, a top surface157of MX wire140is coplanar with a bottom surface158of via bar portion155of MX+1 wire145. Dcrit is the distance between MX wire140and via bar portion155of MX+1 wire145along the interface between lower dielectric layer120and upper dielectric layer125. When dielectric layers120and125comprise multiple dielectric layers, the interface of interest is the interface between the uppermost dielectric layer of lower dielectric layer120and the lowermost dielectric layer of upper dielectric layer125.

FIG. 6Dillustrates a variation ofFIG. 6Cwherein via bar portion155of MX+1 wire145extends into lower dielectric layer120so top surface157of MX wire140is not coplanar with bottom surface158of via bar portion155of MX+1 wire145. However, Dcrit is still measured along the interface between lower dielectric layer120and upper dielectric layer125.FIG. 6Eillustrates a variation of MX+1 wire145. InFIGS. 6A and 6C, the widths of wire portion150and via bar portion155of MX+1 wire145are the same, while inFIG. 6Ethe width of wire portion150is greater than the width of via bar portion155of MX+1 wire145. Dcrit is still measured along the interface between lower dielectric layer120and upper dielectric layer125.

FIGS. 7A and 7Billustrate placement of TDDB test structures according to embodiments of the present invention in integrated circuit chips. InFIG. 7A, an integrated circuit chip200A includes a functional circuit area205and a kerf area210where test and monitor structures are placed and which form the streets for singulating individual chips from a wafer. InFIG. 7A, a set of TDDB monitor regions215A,215B,215C, and215D are placed in kerf area210. Each of the TDDB monitor regions contains sets of two or more TDDB test structures according to the embodiments of the present invention wherein Dcrit is varied between about Dmin and about 0.5×Dmin or less. There may be one or more such sets corresponding to one or more wiring levels. This configuration is suitable for measurement only at wafer level since singulation will destroy the TDDB monitor regions215A,215B,215C, and215D.

FIG. 7Bis similar toFIG. 7Aexcept TDDB monitor regions215A,215B,215C, and215D are placed in functional circuit area205. This configuration is suitable for measurement at either wafer or module level.

FIG. 8illustrates an un-singulated wafer containing integrated circuit chips having TDDB test structures according to embodiments of the present invention. InFIG. 8, a wafer220contains an array225of integrated circuit chips200A or200B.

FIG. 9illustrates an integrated circuit chip having TDDB test structures according to embodiments of the present invention mounted to a module. InFIG. 9, an integrated circuit chip200B is physically mounted to a module (e.g., chip carrier)230. Integrated circuit chip200B is electrically connected to module230by wire bonds235. Module230includes connectors240for temporary connection of module230to a burn-in board or other test jig.

FIG. 10is a method of determining TDDB behavior using TDDB test structures according to embodiments of the present invention. Testing is performed in a stress chamber (if the test is performed at non-ambient temperature, otherwise a test jig can be used) connected to a computer. In step250, a set of TDDB test structures according to embodiments of the present invention are provided. The Dcrit of each of the TDDB structures is different, ranging between about Dmin (or more) and about 0.5×Dmin (or less) but greater than MinIns. In step255, the stress conditions are applied to the set of TDDB test structures. In one example, the stress is performed at a preselected temperature (which may be above ambient room temperature, at ambient room temperature or below ambient room temperature) while an electric field is applied to each TDDB test structure. In one example, the stress is performed at a preselected temperature (which may be above ambient room temperature, at ambient room temperature or below ambient room temperature) while an electric field of between about 2 MV/cm and about 7 MV/cm is applied to each TDDB test structure. In one example, the stress is performed at between about 100° C. and about 300° C. while an electric field of between about 2 MV/cm and about 7 MV/cm is applied to each TDDB test structure. In step260, the leakage current in each TDDB test structure of the set of TDDB test structures is monitored. In step265, it is determined if any TDDB test structure fails (e.g., a current leakage limit is exceeded). If there is a fail, the fail time is recorded (the leakage current may also be recorded) and the method proceeds to step275. In step275, it is determined if there is still a TDDB test structure that has not failed. If there is another TDDB test structure that has not failed, the method loops back to step260, otherwise the method proceeds to step280.

Returning to step265, if there is no fail, the method proceeds to step270. In step270it is determined if the length of time of the stress test has exceeded a preset time limit. If preset time limit has not been exceeded, the method proceeds to step275, otherwise to step280. It should be understood that steps265and270are performed periodically while step260is performed. Step270is optional and testing could proceed until all TDDB test structures of the set of TDDB test structures have failed and step265would connect directly to step275. In step280, the stress test is complete and the time to fail at MinIns is extrapolated from the time of fail of the TDDB test structures. There is no direct measurement of the time to fail for a structure at MinIns because it is not possible to build such a structure. Remember Dmin>Dcrit>MinIns. The extrapolation may be done by curve fitting or a computer model may be used.

FIG. 11is chart illustrating step280ofFIG. 10.FIG. 11should be considered exemplary. TheFIG. 11chart is a simulation of a plot of time to fail in seconds versus conductor-to-conductor distance along the dielectric layers interface in nm. The curve was generated using a square root electric field (SQRT E) model with 65 (nm/V)0.5field acceleration running on a computer. In this example, Dmin is 40 nm. Dcrit is 20 nm and MinIns is 12 nm. Values for time to fail for 20 nm and higher would be inputs to the model from actual measurements. Values for time to fail below 20 nm would be generated by the model.

Thus, the embodiments of the present invention provide structures and methods for determining TDDB reliability at reduced spacings using the structures.