Semiconductor device and process for fabricating the same

A thin stacked semiconductor device has a plurality of circuits that are laminated and formed sequentially in a specified pattern to form a multilayer wiring part. At the stage for forming the multilayer wiring part, a filling electrode is formed on the semiconductor substrate such that the surface is covered with an insulating film, a post electrode is formed on specified wiring at the multilayer wiring part, a first insulating layer is formed on one surface of the semiconductor substrate, the surface of the first insulating layer is removed by a specified thickness to expose the post electrode, and the other surface of the semiconductor substrate is ground to expose the filling electrode and to form a through-type electrode, A second insulating layer is formed on one surface of the semiconductor substrate while exposing the forward end of the through-type electrode, and bump electrodes are formed on both electrodes.

TECHNICAL FIELD

The present invention relates to a semiconductor device for allowing thin forming and high-speed operation and a process for fabricating the same, and in particular to technology effectively applicable to manufacturing technology of laminating a plurality of semiconductor devices sequentially to form a stacked semiconductor device.

BACKGROUND ART

Accompanied by trend toward multifunction and compactness of various electronic apparatuses, semiconductor devices incorporated in an electronic apparatus leads to such a structure with a lot of built-in circuit elements even with compactness. As a method of improving integration density of a semiconductor device (integrated circuit device), three-dimensional stacked semiconductor device is known.

For example, such a structure of planning intensive integration with LSI chips having through-type electrodes over a plurality of stages stacked and secured on an interposer is proposed (for example, Patent Document 1 and Non-Patent Document 1).

A three-dimensional device with first to third semiconductor substrates stacked to form an integrated circuit is known. In this three-dimensional device, an SOI substrate is used in the third semiconductor device (for example, Patent Document 2).

As technology necessary for manufacturing a three-dimensional stacked LSI, there is technology of forming through-type electrodes in a semiconductor substrate. The current process of forming through-type electrodes in a silicon (Si) wafer still requires a lot of steps (for example, Non-Patent Document 2).

[Non-Patent Document 1]: The Institute of Electrical Engineers of Japan, Research Reports of Materials Research Society, VOL. EFM-02-6, No. 1-8, P. 31-35

DISCLOSURE OF THE INVENTION

Problems to be Solved by the Invention

Conventional three-dimensional stacked semiconductor devices have problems as described below.

(1) In a multilayer structure of laminating LSI chips (for example, three chips and more), mainly an individual interposer is frequently provided to implement lamination with that interposer. In this case, an individual flip-chip technique is frequently adopted from a point of view of characteristics. Flip-chip mounting will get costly. In addition, since an interposer is interposed individually, the inter-chip connection path is lengthened, characteristics are deteriorated as well.

(2) Connection with bonding wire to replace a flip chip is applicable to around three layers or four layers. However, increase in the number of wires will require addition to the number of steps. Due to wires, the connection path will be lengthened and increase in impedance will lead to deterioration in characteristics (high speed operation). Moreover, due to problems in handling, thin bear chips have a limitation for forming them thinly in its entirety.

(3) In order to increase the yield factor of a finished product, a final test must be carried out with a bear chip prior to mounting (lamination), but the final test with the bear chip and the final test with so-called KGD (Known Good Die) are extremely costly due to difficulty in handling at the moment.

(4) Lamination in a plurality of sites on a chip is limited to two steps at best, and even in this case, the connection path will be lengthened to be apt to influence characteristics.

System in Package (SiP) is overwhelmingly less costly in development and shorter in development period compared with System on Chip (SoC) and is technology to playing a role in sophisticated semiconductors in the future. SiP is used in cellular phones and digital cameras and the like, but further intensive integration is being demanded. Therefore, demand for four-layer or five-layer lamination is expected to arise in the near future, and moreover, combination thereof is assumed to demand flexibility.

An object of the present invention is to provide a stacked semiconductor device capable of allowing short connection path between semiconductor devices and excellent in characteristics.

Another object of the present invention is to provide a thin stacked semiconductor device allowing a various types of semiconductor devices respectively different in configuration to be laminated over a plurality of steps.

An object of the present invention is to provide a process for fabricating a semiconductor device that enables a well productive and highly reliable thin stacked semiconductor device to be fabricated inexpensively.

An object of the present invention is to provide a process of fabricating a stacked semiconductor device in which electronic parts including various types of semiconductor devices different in configuration can be easily laminated over a plurality of steps.

An object of the present invention is to provide a semiconductor device that allows a connection path to its outside to get short and size thereof to get thin and fabrication to get inexpensive.

The above described as well as other objects and novel characteristics of the present invention will become apparent with reference to descriptions as well as attached drawings hereof.

Means for solving the Problems

Summary of representative inventions among those disclosed herein will be briefly described as follows.

(1) A stacked semiconductor device of the present invention has a first semiconductor device having outside electrode terminals on its lower surface, a second semiconductor device electrically connected with the above described first semiconductor device through joints and secured on the above described first semiconductor device and a third semiconductor device sequentially stacked and secured between the above described first semiconductor device and second semiconductor device through joints, wherein

the above described first semiconductor device has:

a semiconductor substrate;

a multilayer wiring part including a plurality of circuit elements formed at a first main surface side of the above described semiconductor substrate and wiring connected with the above described circuit elements;

a first insulating layer for covering the above described multilayer wiring part;

a second insulating layer for covering a second main surface to become an opposite face against the first main surface of the above described semiconductor substrate;

a plurality of post electrodes formed on respective specified wiring of the above described multilayer wiring part to be exposed in a surface of the above described first insulating layer; and

a plurality of through-type electrodes provided to pierce through the above described semiconductor substrate and the above described second insulating layer from specified depth of the above described multilayer wiring part, brought into contact to the above described semiconductor substrate through insulating film and connected with specified wiring of the above described multilayer wiring part respectively, and

the above described second semiconductor device has:

a semiconductor substrate;

a multilayer wiring part including a plurality of circuit elements formed at a first main surface side of the above described semiconductor substrate and wiring connected with the above described circuit elements;

a first insulating layer for covering the above described multilayer wiring part;

a second insulating layer for covering a second main surface to become an opposite face against the first main surface of the above described semiconductor substrate;

at least post electrodes formed on respective specified wiring of the above described multilayer wiring part to be exposed in a surface of the above described first insulating layer or

a plurality of through-type electrodes provided to pierce through the above described semiconductor substrate and the above described second insulating layer from specified depth of the above described multilayer wiring part, brought into contact to the above described semiconductor substrate through insulating film and connected with specified wiring of the above described multilayer wiring part respectively, and

the above described third semiconductor device has:

a semiconductor substrate;

multilayer wiring part including a plurality of circuit elements formed at a first main surface side of the above described semiconductor substrate and wiring connected with the above described circuit elements;

a first insulating layer for covering the above described multilayer wiring part;

a second insulating layer for covering a second main surface to become an opposite face against the first main surface of the above described semiconductor substrate;

a plurality of post electrodes formed on respective specified wiring of the above described multilayer wiring part to be exposed in a surface of the above described first insulating layer;

a plurality of through-type electrodes provided to pierce through the above described semiconductor substrate and the above described second insulating layer from specified depth of the above described multilayer wiring part, brought into contact to the above described semiconductor substrate through insulating film and connected with specified wiring of the above described multilayer wiring part respectively, and

in the above described first semiconductor device, the above described post electrodes or the above described through-type electrodes come in the lower surface and the post electrodes or the through-type electrodes in the lower surface is provided with the above described outside electrode terminals;

the above described through-type electrodes or the above described post electrodes in the lower surface of the above described third semiconductor device are electrically connected with the above described post electrodes or the above described through-type electrodes in the upper surface of the above described first semiconductor device through the above described joints;

the above described post electrodes or the above described through-type electrodes in the lower surface of the above described second semiconductor device are electrically connected onto the above described post electrodes or the above described through-type electrodes in the upper surface of the above described third semiconductor device through the above described through-type electrodes.

Such a stacked semiconductor device has,

(a) a step of aligning, disposing and forming product forming part in plurality inclusive of specified circuit elements on a first main surface of a semiconductor substrate;

(b) a step of forming a multilayer wiring part by laminating and forming sequentially in a specified pattern wiring and insulating layers being connected electrically with the above described circuit elements;

(c) a step of forming, at a stage for forming the above described multilayer wiring part, a plurality of holes toward a second main surface to become an opposite face against the above described first main surface of the above described semiconductor substrate from specified depth of the above described multilayer wiring part having insulating film on their surfaces and of forming filling electrodes to fill those holes with conductive substance and be electrically connected with specified wiring of the above described multilayer wiring part;

(d) a step of forming post electrodes on respectively specified wiring of the above described multilayer wiring part;

(e) a step of forming, on the first main surface of the above described semiconductor substrate, a first insulating layer to cover the above described post electrodes;

(f) a step of removing the surface of the above described first insulating layer by specified thickness to expose the above described post electrodes;

(g) a step of removing the second main surface of the above described semiconductor substrate from its surface by specified thickness to expose the above described filling electrodes to form through-type electrodes;

(h) a step of removing by etching the second main surface of the above described semiconductor substrate by specified thickness to cause the above described through-type electrodes to protrude by specified length;

(i) a step of forming the second insulating layer of specified thickness on the second main surface of the above described semiconductor substrate in a state of exposing forward ends of the above described through-type electrodes; and

(j) a step of cutting the above described semiconductor substrate inclusive of the above described first and second insulating layers in a lattice pattern to divide the above described product forming part; and has

(k) a step of forming protruding electrodes at specified exposed ends among the above described through-type electrodes and the above described post electrodes after the above described step (i) or after the above described step (j), wherein

through the above described step (a) to step (k), the above described first semiconductor device and third semiconductor device are formed;

through selection of the above described step (a) to step (k), the second semiconductor device having only the above described through-type electrodes or only the above described post electrodes on the lower surface is formed;

next, disposing the above described first semiconductor device so that the above described through-type electrodes or the above described post electrodes come to the lower surface, the above described electrodes on the lower surface are regarded as the above described outside electrode terminals, and thereafter, the above described through-type electrodes or the above described post electrodes in the lower surface of the above described semiconductor device are overlapped and connected to the above described through-type electrodes or the above described post electrodes in the upper surface of the above described first semiconductor device by causing the above described protruding electrodes to undergo temporal heat processing, and

next, the above described through-type electrodes or the above described post electrodes in the lower surface of the above described second semiconductor device are overlapped and connected to the above described through-type electrodes or the above described post electrodes in the upper surface of the above described third semiconductor device by causing the above described protruding electrodes to undergo temporal heat processing to fabricate a stacked semiconductor device.

The above described second semiconductor device having only the above described through-type electrodes is formed through:

a step of aligning, disposing and forming product forming part in plurality inclusive of specified circuit elements on a first main surface of the above described semiconductor substrate;

a step of forming a multilayer wiring part by laminating and forming sequentially in a specified pattern wiring and insulating layers being connected electrically with the above described circuit elements;

a step of forming, at a stage for forming the above described multilayer wiring part, a plurality of holes toward a second main surface to become an opposite face against the above described first main surface of the above described semiconductor substrate from specified depth of the above described multilayer wiring part having insulating film on their surfaces and of forming filling electrodes to fill those holes with conductive substance and be electrically connected with specified wiring of the above described multilayer wiring part;

a step of forming a first insulating layer on the first main surface of the above described semiconductor substrate;

a step of removing the second main surface of the above described semiconductor substrate from its surface by specified thickness to expose the above described filling electrodes to form through-type electrodes;

a step of removing by etching the second main surface of the above described semiconductor substrate by specified thickness to cause the above described through-type electrodes to protrude by specified length;

a step of forming the second insulating layer of specified thickness on the second main surface of the above described semiconductor substrate to expose forward ends of the above described through-type electrodes;

a step of cutting the above described semiconductor substrate inclusive of the above described first and second insulating layers in a lattice pattern to divide the above described product forming part; and

a step of forming protruding electrodes at exposed portions of the above described through-type electrodes before or after the above described dividing step.

The above described second semiconductor device having only the above described post electrodes is formed through:

a step of aligning, disposing and forming product forming part in plurality inclusive of specified circuit elements on a first main surface of a semiconductor substrate;

a step of forming a multilayer wiring part by laminating and forming sequentially in a specified pattern wiring and insulating layers being connected electrically with the above described circuit elements;

a step of forming post electrodes on respectively specified wiring of the above described multilayer wiring part;

a step of forming, on the first main surface of the above described semiconductor substrate, a first insulating layer to cover the above described post electrodes;

a step of removing the surface of the above described first insulating layer by specified thickness to expose the above described post electrodes;

a step of removing the second main surface of the above described semiconductor substrate from its surface by specified thickness to make the above described semiconductor substrate thin;

a step of forming the second insulating layer of specified thickness on the second main surface of the above described semiconductor substrate;

a step of cutting the above described semiconductor substrate inclusive of the above described first and second insulating layers in a lattice pattern to divide the above described product forming part; and

a step of forming protruding electrodes at exposed portions of the above described post electrodes before or after the above described dividing step.

(2) The above described configuration (1) is characterized in that a plurality of second semiconductor devices smaller than the above described first semiconductor device are disposed and secured in parallel on the above described first semiconductor device.

ADVANTAGES OF THE INVENTION

Effects derived by representative inventions among those disclosed herein will be briefly described as follows.

According to means in the item (1), (a) the first, the third and the second semiconductor devices, in fabrication thereof, the first insulating layers are formed at the first main surface sides of the semiconductor substrates and thereafter the second main surfaces of the semiconductor substrates undergo thickness removal by a specified amount, but since the above described first insulating layers act as strength member, the semiconductor substrates can be made thin to a level of around 5 to 50 μm. In addition, since thickness of the insulating layers can also be made thin to a level of around 20 to 100 μm, in such a state that thickness of the protruding electrodes is not considered, respective semiconductor devices can be made to have thickness of, for example, around 40 to 100 μm so that thinning of the stacked semiconductor device can be attained. If a value of the lower limit is taken for thickness of the semiconductor substrates and insulating layers, further thinning can be planned.

(b) In the first, the third and the second semiconductor devices, in connecting the semiconductor device at the lower stage side with the semiconductor device at the upper stage side, connection is carried out in utilization of post electrodes to become columnar provided by piercing through the first insulating layer and through-type electrodes to become columnar provided by piercing through the semiconductor substrate, and therefore, the current pathway will get short to make reduction in inductance attainable and to make electrical property of the stacked semiconductor device good. The post electrodes and through-type electrodes provided in the first insulating layer and semiconductor substrate are short with length thereof being around 5 to 50 μm, and will become sufficiently short compared with length of not less than several hundred micrometers of a bonding wire by means of wire connection. Thereby, high speed operation of the stacked semiconductor device will become feasible.

(c) There is a constraint that the through-type electrodes provided in the semiconductor substrate is formed in a region apart from the region where circuit elements are formed, and nevertheless the disposing locations for wiring regions and the like can be selected comparatively freely. The disposing location for the post electrodes connected with specified wiring of the multilayer wiring part can be determined comparatively freely by deploying wiring. Therefore, by selecting locations to provide the through-type electrodes and the post electrodes, improvement in integration density in the two-dimensional direction can be planned.

(d) The stacked semiconductor device of the present invention will become capable of electrically connecting the semiconductor device at the lower stage side with the semiconductor device at the upper stage side without using any interposer. Consequently, reduction in the number of assembling parts items can be planned and thinning of the stacked semiconductor device can be planned. Use of interposer will lengthen connecting path (current pathway) between semiconductor chips or between semiconductor devices, but no use of interposer will enable the current pathway to get short so that improvement in electrical property can be planned.

(e) In fabricating the stacked semiconductor device of the present invention, the first, the third and the second semiconductor devices are fabricated in use of the semiconductor wafers in fabrication thereof, which together with insulating layers are cut at the final stage to fabricate the first, the third and the second semiconductor devices. Accordingly, since required processing other than stacking and securing the first, the third and the second semiconductor devices is carried out on a wafer level, handling performance is good throughout the steps and wasteful work will get less. Consequently, reduction in production costs can be planned.

(2) According to the above described structure (1), a plurality of second semiconductor devices smaller than the above described first semiconductor device are disposed and secured in parallel on the above described first semiconductor device, and therefore further improvement in integration can be planned.

DESCRIPTION OF SYMBOLS

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiments of the present invention will be described in detail below with reference to drawings. The like reference characters and numerals designate the parts having the same functions throughout the figures for describing embodiments of the present invention and repeated descriptions thereof will be omitted.

FIG. 1toFIG. 20relate to a stacked semiconductor device being Embodiment 1 of the present invention.FIG. 1toFIG. 3relate to structures of the stacked semiconductor device,FIG. 4toFIG. 19relate to fabrication of the stacked semiconductor device andFIG. 20is a drawing showing a state of mounting the stacked semiconductor device.

A stacked semiconductor device1fabricated subject to a process of fabricating the present invention consists of, as shown inFIG. 2, a rectangular first semiconductor device2to become a lower stage, a middle stage third semiconductor device4stacked and secured on the upper surface of this first semiconductor device2and an upper stage second semiconductor device3stacked and secured on the upper surface of this third semiconductor device4. In the stacked semiconductor device1of Embodiment 1, the first, the second and the third semiconductor devices2,3and4have the same planar sizes and are stacked in a corresponding fashion.FIG. 3is a drawing showing a bottom view of the stacked semiconductor device1which has external electrode terminals5formed with protruding electrodes provided on the lower surface of the first semiconductor device.

In the first, the second and the third semiconductor devices2,3and4, respective semiconductor devices are different in presence or absence of through-type electrodes and post electrodes at the stacked and secured surface side and in presence or absence of joints for bringing the through-type electrodes and the post electrodes into connection, and therefore names of respective parts are the corresponding names while symbols for the first semiconductor device2are provided with “a” at the end of numerals, symbols for the second semiconductor device3are provided with “b” at the end of numerals and symbols for the third semiconductor device4are provided with “c” at the end of numerals for description. The protruding electrodes (bump electrodes) provided at exposed ends of the through-type electrode and the post electrode undergo temporal heating processing to form the above described joints.

The first semiconductor device2has a rectangular semiconductor substrate6a. The semiconductor substrate6ais, for example, made of silicon (Si) and a multilayer wiring part7ais formed on a first main surface (a surface where circuits such as IC and the like are formed, or the upper surface inFIG. 1) side thereof and the multilayer wiring part7ais provided with a first insulating layer8amade of insulating resin thereon. The insulating layer is generally formed of resin, for example, insulating resin such as polyimide resin, epoxy resin and the like, to be used for fabricating a semiconductor device. The semiconductor substrate6ahas thickness of, for example, around 20 μm. The semiconductor substrate6amay have thickness of around 6 to 50 μm. The insulating layer will become strength member when to fabricate a semiconductor device and is comparatively thick to have, for example, thickness of around 50 μm. The insulating layer may have thickness of around 20 to 100 μm.

There provided are post electrodes9amade of columnar copper (Cu) piercing through the first insulating layer8ato be electrically connected to specified wiring of the multilayer wiring part7a. The post electrodes9aare exposed on the surface of the first insulating layer8a. The exposed portions of the post electrodes9aare provided with protruding electrodes10a. The protruding electrodes10aare bump electrodes made of, for example, solder balls, gold balls, copper balls subject to plating with gold on their surfaces and the like.

On the first main surface of the semiconductor substrate6aactive elements such as transistors, diodes and the like in various types of structures and passive elements such as resistance elements, capacitor elements, inductor elements and the like are formed in accordance with necessity. The post electrodes9ahave diameter of around 10 μm and thickness of 50 μm. The post electrodes9amay have diameter of around 10 to 50 μm and thickness of around 20 to 100 μm. The protruding electrodes10aare formed of balls having diameter of, for example, around 60 μm in size prior to connection and have thickness of around 40 μm. Balls having diameter of around 40 to 80 μm may be used to form the protruding electrodes10a.

The second main surface (the bottom surface inFIG. 1) to become the rear side of the above described first main surface of the semiconductor substrate6ais provided with a second insulating layer11amade of insulating resin. The second insulating layer11ais formed of, for example, polyimide resin. The second insulating layer11ahas thickness of, for example, around several micrometers to 10 μm that will at least secure electrical insulation. The embodiment hereof has thickness of around 5 μm.

Through-type electrodes12aare provided to pierce through the semiconductor substrate6aas well as the second insulating layer11afrom specified depth of the multilayer wiring part7a. Those through-type electrodes12aare electrically connected to specified wiring of the multilayer wiring part7a. The through-type electrodes12aare formed of columnar copper plating. The through-type electrodes12ahave diameter of, for example, around 10 μm. The through-type electrodes12amay have diameter of around several micrometers to 30 μm. The through-type electrodes12a, as to be described below, contacts the semiconductor substrate6athrough insulating film that comes between the semiconductor substrate6aand the circumference surface of the through-type electrodes12aso that they are electrically independent from the semiconductor substrate6a.

The through-type electrodes12aare exposed on the surface of the second insulating layer11a. The exposed portions of those through-type electrodes12aare provided with protruding electrodes13a. The protruding electrodes13aare ball bump electrodes made of, for example, gold balls, copper balls subject to plating with gold on their surfaces, solder balls and the like. The protruding electrodes13aare also balls in size similar to protruding electrodes10a. The protruding electrodes may be formed by plating or printing (screen printing). In that case, the protruding electrodes may have thickness of around 10 μm.

The stacked semiconductor device1of Embodiment 1 is structured so that, in any of the first, second and third semiconductor devices2,3,4, the first insulating layers8a,8b,8ccome to the top and semiconductor substrates6a,6b,6ccome to the bottom.

The middle stage third semiconductor device4is different from the first semiconductor device2in the pattern of the post electrodes9cand through-type electrodes12c, but is structured substantially the same as the first semiconductor device2in the other portions. The third semiconductor device4is not provided with any protruding electrode. The reason thereof is to use, for connection, protruding electrodes of semiconductor device of the counter party to be stacked when to be stacked and secured. However, such a process may be adopted that protruding electrodes are provided in the post electrodes9cand the through-type electrodes12cso that the protruding electrodes are connected each other for carrying out stacking and securing.

The third semiconductor device4in the middle stage is provided with a multilayer wiring part7cand a first insulating layer8con the first main surface (upper surface) of a semiconductor substrate6cand the second main surface is provided with an insulating layer11c. The first insulating layer8cis provided with a plurality of post electrodes9cto be electrically connected to specified wiring of the multilayer wiring part7c. And there are a plurality of through-type electrodes12cpiercing through the second insulating layer11cfrom the semiconductor substrate6cto be electrically connected to specified wiring of the multilayer wiring part7c. Those through-type electrodes12chave insulating surface on their circumference and are insulated and separated from the semiconductor substrate6c.

The through-type electrodes12con the lower surface side of the third semiconductor device4in the middle stage and the post electrodes9aon the upper surface side of the first semiconductor device2in the lower stage are respectively facing each other and are electrically connected through the protruding electrodes10a. The protruding electrodes10awill undergo temporal heat processing to become joints so as to connect the connecting portions. That connection will cause the third semiconductor device4to be stacked and secured on the first semiconductor device2.

The second semiconductor device3in the upper stage is structured like the first semiconductor device2except that the upper surface is not provided with any post electrode. That is, the second semiconductor device3is structured to have a multilayer wiring part7bas well as a first insulating layer8bon a first main surface (upper surface) of a semiconductor substrate6band a second insulating layer11bon a second main surface. Through-type electrodes12bare provided to pierce through the semiconductor substrate6band the second insulating layer11b. The through-type electrodes12bare electrically connected to specified wiring of the multilayer wiring part7b. The exposed portions of those through-type electrodes12bon the surface of the second insulating layer11bare provided with protruding electrodes13b.

The through-type electrodes12bon the bottom surface side of the third semiconductor device3in the upper stage and the post electrodes9con the upper surface side of the third semiconductor device4in the middle stage are respectively facing each other and are electrically connected through the protruding electrodes13b. That connection will cause the second semiconductor device3to be stacked and secured on the third semiconductor device4.

The protruding electrodes10abringing the first semiconductor device2and the third semiconductor device4into connection will become joints and the protruding electrodes13bbringing the third semiconductor device4and the second semiconductor device3into connection will become joints. When the protruding electrodes are formed of balls in diameter of around 60 μm, the protruding electrodes having thickness of around 40 μm can be formed. When the above described joints are formed of protruding electrodes, the joints will have thickness of around 20 μm. In the case where protruding electrodes are formed in post electrodes and through-type electrodes, it is advisable that desired plating film is formed in advance onto a surface where through-type electrodes and protruding electrodes are exposed when it is difficult to form the protruding electrode directly.

Respective semiconductor devices can be caused to have thicknesses of around 40 to 100 μm by respectively selecting specified sizes from the size range shown in the embodiment, and therefore, the stacked semiconductor device1stacked and secured in three stages will have thickness of around 200 to 380 μm in case of ball bump electrodes and, in case of protruding electrodes by means of printing, of around 150 to 330 μm that is extremely thin. Height of that stacked semiconductor device1will vary in accordance with size (thickness) of the ball bump electrodes and the protruding electrodes by means of printing.

In the stacked semiconductor device1fabricated by stacking and securing, the protruding electrodes13aprovided at the bottom surface of the semiconductor substrate6awill become outside electrode terminals5. In case of using the first semiconductor device2to dispose the first insulating layer8aat the bottom surface, the protruding electrodes10awill become the outside electrode terminals5.

Next, a process for fabricating the stacked semiconductor device1of Embodiment 1 hereof will be described.FIG. 4is a flow chart showing a process for fabricating the stacked semiconductor device1. That flow chart constitutes respective flowcharts respectively consisting of stages from a step11(S11) to a step21(S21) to fabricate a first semiconductor device2in the bottom stage, a third semiconductor device4in the middle stage and a second semiconductor device3in the upper stage and a stage of a step S22to stack and secure the semiconductor devices in the bottom stage, the middle stage and the upper stage.

The first semiconductor device2in the lower stage is formed through respective steps of forming circuit elements onto a semiconductor substrate (Step S11), forming filling electrodes as well as electrode pads at a stage of forming multilayer wiring part (Step S12), forming post electrodes (Step S13), forming a first insulating layer (to embed post electrodes: Step S14), removing surface of the first insulating layer (to expose post electrodes: Step S15), removing the substrate surface (to form through-type electrodes: Step S16), etching the substrate surface (to protrude through-type electrodes: Step S17), forming a second insulating layer (to expose the through-type electrode: Step S18), forming protruding electrodes (through-type electrodes and post electrodes: Step S19), separation (into individual pieces: Step S20) and performing a characteristics test (Step S21).

The third semiconductor device4in the middle stage is fabricated through the same stages as in the stages for fabricating the above described first semiconductor device2in the lower stage, and however the through-type electrodes12cprovided to the lower side are formed in a pattern to face the post electrodes9aon the upper surface of the first semiconductor device2in the lower stage.

Since no post electrode is formed in the second semiconductor device3in the upper stage, the stage of Step S13will become unnecessary. Since no post electrode is provided, a first insulating layer is formed in Step S14while the surface of the first insulating layer is removed in Step S15and consideration on post electrodes will be no longer required.

The first, third and second semiconductors2,4and3formed in the stage of Step S21are sequentially stacked in the stacking and securing stage (Step S22) and are stacked and secured through, for example, a reflow oven to fabricate the stacked semiconductor device1shown inFIG. 1toFIG. 3.

Any semiconductor device of the stacked semiconductor device1in Embodiment 1 is a semiconductor device in use of a silicon substrate. However, semiconductor devices in use of compound semiconductor such as GaAs, InP or the like and semiconductor devices in use of silicon substrates may be brought into combination. In such a case, circuit elements suitable for material are formed in the semiconductor portions.

Next, fabrication of the first semiconductor device2in the lower stage will be described.FIG. 5is a schematic sectional view showing filling electrodes having been formed in a semiconductor substrate (silicon substrate) with ICs and the like having been already formed in fabricating the stacked semiconductor device1.

In fabricating a semiconductor device, a wide area semiconductor wafer is prepared and thereafter unit circuits inclusive of specified circuit elements are formed on the first main surface of that wafer. Those unit circuits are formed on the first main surface of that wafer while being aligned and disposed in a lattice. Thereafter, subject to respective processes, lastly cut and separated in a checked fashion, a great number of semiconductor elements (semiconductor chips) are formed. That rectangular shape region (portion) to form that unit circuit will be referred to as product forming part herein. Between a product forming part and a product forming part, there positioned is a scribe line to undergo dividing or a dicing region to undergo cutting. Lastly, cutting takes place in that dicing region. InFIG. 5and forward, only a single product forming part will be shown. Accordingly, as far as there is no problem, a major part of names will be taken from names used in a state of a finished product for descriptions.

As shown inFIG. 5, after a semiconductor substrate6ahaving thickness of several hundreds micrometers is prepared, circuits (circuit elements) are formed on a first main surface of that semiconductor substrate6a(Step S11). A multilayer wiring part7ais formed on the first main surface of the semiconductor substrate6a. At the stage for forming that multilayer wiring part7a, holes are formed on the first main surface of the semiconductor substrate6a. Thereafter, the surface of the hole undergo oxidization and subsequently a plating film is filled and formed inside the hole. By filling with that plating film, filling electrodes12are formed. The holes have, for example, diameter of around several micrometers to 30 μm and depths of around 5 to 50 μm. In the embodiments, they have, for example, diameter of around 10 μm and a depth of 30 μm. In this embodiment, at the point of time when a semiconductor device is formed, the semiconductor substrate6ais made thin to make the first semiconductor device2thin. Therefore, in case of enhancing the thin structure further, the above described holes may be made further shallower so as to make processing the holes easier. The plating film is formed of, for example, copper. The process for forming the filling electrodes12may be the other process. For example, such a process may be employed for forming the filling electrodes12that subjects to filling the interior of the holes with electrically conductive particles sprayed in an ink jet system and thereafter undergoing hardening by means of heat processing. For example, tungsten, titanium, nickel, aluminum or alloy thereof may be used for filling with CVD (chemical vapor depositing).

FIG. 6is an enlarged schematic sectional view of a part of a semiconductor substrate showing the lower layer portion of the above described filling electrode and multilayer wiring part. A semiconductor6ais a substrate of a first electrically conductive type, and a first well21of a second electrically conductive type and a second well22of the first electrically conductive type are formed in a surface layer portion on the first main surface side. In the first well21, a source region23, a drain region24and an insulating gate film25are formed and a gate electrode26is formed on the insulating gate film25to form a field effective transistor (FET). Electrodes27and28are formed on the surfaces of the first and the second wells22respectively. A thick oxide film29is selectively provided on the first main surface of the semiconductor substrate6a.

FIG. 7is an enlarged schematic sectional view of a part of the above described filling electrode, multilayer wiring part and the like. As shown inFIG. 7, on the first main surface of the semiconductor substrate6a, the insulating layers30and the wiring layers (wiring)31are alternately laminated and formed in a specified pattern to form a multilayer wiring part7a. The wiring layer in the uppermost layer forms an electrode pad32. A part of that electrode pad32is exposed. Post electrodes9awill be formed in the exposed portions. Therefore, the exposed portions become holes having diameter of around 10 μm.FIG. 6shows the insulating layer30and wiring layers (wiring)31in the lowest layer of the multilayer wiring part7a.

At the stage for forming the multilayer wiring part7a, the above described filling electrode12is formed in the semiconductor substrate6a. In the embodiment, at the stage for having formed the circuit elements and formed the thick oxide film29, the above described hole33is formed on the first main surface side of the semiconductor substrate6awith photolithography technology and photo etching for normal use. Thereafter, oxidation processing is carried out to form an insulating film34on the surface of the hole33. Moreover, copper plating is carried out to fill the hole33with a copper plating film to form the filling electrode12. For example, the filling electrode12will have diameter of around 10 μm and a depth of around 30 μm. Thereby, the filling electrode and the electrode pad are formed (Step S12). The filling electrode12will be electrically insulated due to contact with the semiconductor substrate6athrough the insulating film34.

The above described filling electrode12may be formed by spraying electrically conductive liquid in an inkjet system to embed the hole33. In that case, after spaying, the filled electrically conductive liquid undergoes hardening processing (baking). The other metal, for example, tungsten, titanium, nickel, aluminum or alloy thereof may be used for filling with CVD (chemical vapor depositing) so as to form a CVD film.

As described above, since the insulating film34is interposed between the filling electrode12and the semiconductor substrate6a, the filling electrode12will be electrically separated (independent) from the semiconductor substrate6a.

At the time when the insulating layers30and the wiring layers (wiring)31are alternately laminated and formed sequentially in a specified pattern to form a multilayer wiring part7aon the first main surface of the semiconductor substrate6a, the filling electrode12is electrically connected with specified wiring of the multilayer wiring part7a.

Next, as shown inFIG. 8, specified positions on the first main surface of the semiconductor substrate6aundergo plating to form a plurality of columnar post electrodes9a(Step S13). As for those post electrodes9a, likewise the above described filling electrodes12, copper, tungsten, titanium, nickel, aluminum or alloy thereof may be used to form a CVD film.

Next, a first insulating layer8ais formed on the first main surface of the semiconductor substrate6a(Step S14). The post electrodes9aare covered with the first insulating layer8a. Insulating organic resin such as epoxy resin, polyimide resin and the like is used for the first insulating layer8a. The first insulating layer8ais formed with, for example, transfer molding or squeegee printing.

FIG. 9is an exemplary enlarged schematic sectional view of a part of a semiconductor substrate with the above described post electrode and first insulating layer having been formed thereon. A post electrode9ais formed on the upper surface of the electrode pad32and the post electrode9ais covered with the first insulating layer8a.FIG. 9depicts the post electrode9ato be formed thinner than the electrode pad32by a large margin. This assumes direct use of a process for fabricating an IC and the like having an electrode pad to be connected with wires. In order to connect an IC and the like with electrically conductive wires, the electrode pad is shaped rectangular with a side having length of around 80 to 100 μm. Therefore, in the embodiment, the post electrode9ais provided on that electrode pad32. Use of the electrode pad32by means of an established IC process as wiring portion for forming the post electrode9ais also one technique. But, the present invention will not be limited thereto, but the post electrode9amay be formed in a wiring portion with small area.

FIG. 10andFIG. 11are examples (variations) with the post electrode9aformed on the electrode pad32to have nearly the same diameter as the electrode pad32.

The structure ofFIG. 10is an example where the filling electrode12has been formed at a comparatively early stage for forming the multilayer wiring part7a. After having formed the first layer and the second layer of insulating layers30on the first surface side of the semiconductor substrate6a, the hole33is formed in those two layers of the insulating layer30and semiconductor substrate6aand subsequently the hole33is filled with a plating film to form the filling electrode12.

The structure inFIG. 11is an example of a filling electrode12that has been formed at a stage of a comparatively later period for forming the multilayer wiring part7a. After having formed a first layer to a fourth layer of insulating layers30on the first surface side of the semiconductor substrate6a, a hole33is formed in those four layers of the insulating layer30and the semiconductor substrate6a, and subsequently the hole33is filled with a plating film to form a filling electrode12.

As shown inFIG. 7,FIG. 10andFIG. 11, the hole33can be formed in a freely selective fashion at a desired stage for forming the multilayer wiring part7aso as to enable electrical connection with specified wiring (wiring layer31) of the multilayer wiring part7a. Since structures inFIG. 7andFIG. 9are already described in detail inFIG. 9andFIG. 10, a part of symbols will be omitted.

Next, as shown inFIG. 12, the surface of the first insulating layer8ais removed by a specified thickness (Step S15). For example, the surface of the first insulating layer8ais ground so as to expose the forward end of the post electrode9a. If the quantity of grinding gets larger, the thickness of the post electrode9agets shorter and the thickness of the first insulating layer8agets thinner as well. In the present embodiment, after making the semiconductor substrate6athin to be described later, since the first insulating layer8ais used as a strength member for supporting the semiconductor substrate6a, the thickness of the first insulating layer8a, for example, is set to around 50 μm. In the case where there is no problem in handling the semiconductor substrate6ain terms of strength, the first insulating layer8amay be made further thinner. This will lead to thinning of the first semiconductor device2and thinning of the stacked semiconductor device1.

Next, as shown inFIG. 13, the second main surface of the semiconductor substrate6ais ground so as to expose the forward ends of the filling electrodes12and to form the through-type electrodes12and with the filling electrodes12(Step S16). Thereby, the semiconductor substrate6awill have thickness of around 25 μm. Even if the semiconductor substrate6agets thin like this, the first insulating layer8ais thick and thereby the semiconductor substrate6acan prevent damages such as cracking at the time of handling or breakage from taking place.

Next, as shown inFIG. 14, the second main surface side of the semiconductor substrate6aundergoes etching for a specified thickness. Etching is carried out with wet etching with etching solution of a hydrofluoric acid system and the through-type electrodes12ado not undergo etching. Thereby, the forward ends of the through-type electrodes12awill be protruded by around 5 μm from the semiconductor substrate6ahaving thickness of around 20 μm.

Next, as shown inFIG. 15, a second insulating layer11ais formed on the silicon surface at the second main surface side of the semiconductor substrate6a. At that time, the second insulating layer11ais formed so as to expose the forward ends of the through-type electrodes12a(Step S18). The second insulating layer11amay be formed with, for example, spinner application, and squeegee printing or film-type substance is pasted by heat processing and pasted with insulating adhesive for forming. Thickness of the second insulating layer11ais set to thickness that enables electrical insulation to be planned at least. In forming this second insulating layer11a, it can be formed by applying insulating material that is hydrophobic to through-type electrodes12abeing Cu and is hydrophilic to Si. That is, providing the second insulating layer11aso as to reach approximate height of protrusion of the through-type electrodes12a, the forward ends of the through-type electrodes12aare exposed from the second insulating layer11a.

Next, as shown inFIG. 16, protruding electrodes10aand13aare formed at the forward ends of the post electrodes9ato be exposed on the front side of the second insulating layer11aand the forward end of the through-type electrodes12ato be exposed on the second main surface side of the semiconductor substrate6a(Step S19). The protruding electrodes10aand13aare bump electrodes made of, for example, solder balls, gold balls, copper balls having undergone gold plating on their surfaces and the like or by screen printing and heating. When it is difficult to form protruding electrodes directly to the post electrodes and the through-type electrodes, it is advisable to form a plating film on the exposed surfaces of the post electrodes and the through-type electrodes in advance for making connection well.

Next, the semiconductor wafer is divided in a checked fashion to form individual pieces (Step S20). The drawing has been described not in a state of a semiconductor wafer but in a state of a single product forming part. Therefore, the first semiconductor device2that has been divided and formed will have sectional structure shown inFIG. 16as well. In embodiments, the bump electrodes have been formed and thereafter undergone processing to form individual pieces but the bump electrodes may be formed after processing to form individual pieces.

InFIG. 16, the semiconductor substrate6ais disposed to the upper surface side and the first insulating layer8ais disposed to the lower surface side, and, inFIG. 17, the semiconductor substrate6ais disposed to the lower surface side and the first insulating layer is disposed to the upper surface side. The first semiconductor device2is used as a semiconductor device disposed at the lowest stage at the time of stacking and securing, but in the case where the protruding electrodes10aare used as shown inFIG. 16as outside electrode terminals at that time, or as shown inFIG. 17, the protruding electrodes13awill be used as outside electrode terminals.

Next, after forming an individual chip, that is, the first semiconductor device2, a normal test (electrical property test) is carried out. At that time, as shown inFIG. 18, respective chips (first semiconductor devices2) are housed in housing depressions41provided in a matrix state on the upper surface of the tray40. Since the upper surface and the rear surface of the first semiconductor device2are respectively covered with insulating material, the test can be carried out simultaneously as well as in parallel with a probe test. Products having been found to be defective are excluded. InFIG. 18, the protruding electrodes13aof the first semiconductor devices2are displayed schematically. Use of such a tray40allows arrangement of products in an array state to make collective testing possible and to make handling of the products easier to improve test efficiency.

In general, in fabricating a semiconductor device, an electrical property test of products (circuits) of respective product forming parts of the semiconductor wafer is performed in a state of a semiconductor wafer. That is, a probe nail is brought into contact with an electrode exposed in respective product forming parts of a semiconductor wafer to perform an electrical property test, and also in the present embodiment, a same probe test may be performed prior to dividing processing so as to perform measurement and a test on quality of products (circuits) of respective product forming parts. The first semiconductor device2is fabricated by the above described process.

The third semiconductor device4stacked and secured on the first semiconductor device2is fabricated by the same steps as in the first semiconductor device2, that is, respective steps of Step S11to Step S21shown inFIG. 4. At that time, the third semiconductor device4can be used in a state as shown inFIG. 16orFIG. 17, that is, so that the protruding electrodes10aare located on the lower surface or the protruding electrodes13aare located on the lower surface. Selection thereof is free, but it is necessary to form the protruding electrodes10aor the protruding electrodes13aon the lower surface of the third semiconductor device4so as to be connectable to the protruding electrodes10aor the protruding electrodes13aon the upper surface of the first semiconductor device2. Since the third semiconductor device to become the middle stage is provided with the bump electrodes engaged in connection in the first semiconductor device2at the lower stage side and the second semiconductor device3at the upper stage side, the bump electrodes do not have to be provided with intentionally. Therefore, the third semiconductor device4may be stacked and secured as shown in the middle stage inFIG. 19in such a state that no bump electrode is provided. Moreover, the third semiconductor device4at the middle stage may be provided with the protruding electrodes either on the upper surface or on the lower surface. In that case, the semiconductor device does not have to be provided in advance with protruding electrodes intentionally on its surface that faces the surface provided with protruding electrodes, and the protruding electrodes provided in the third semiconductor device4at the middle stage act as joints.

The second semiconductor device3stacked and secured on the upper surface of the third semiconductor device4is structured to form either the through-type electrodes12aor the post electrodes9ain fabricating the above described first semiconductor device2. That is, since it will come to the uppermost stage, no outside electrode terminal is necessary on its upper surface.

In Embodiment 1 hereof, as shown inFIG. 4, the second semiconductor device3will be described with an example without forming any post electrode but with forming through-type electrodes12a. In fabricating the second semiconductor device3, circuit element forming onto the semiconductor substrate (Step S11) is the same but only filling electrodes at the stage for forming a multilayer wiring part are formed in Step S12. Thereafter the step goes forward to Step S14. In this Step S14, only first insulating layer8ais formed. Since no post electrode is present in Step S15, relationship with post electrodes does not have to be considered, but thickness of the first insulating layer8ais secured. Subsequent Step S16, Step S17and Step S18will be the same processing. In Step S19, protruding electrodes13bare formed only at the forward ends of the through-type electrodes12a. Subject to division in Step S20and a property test in Step S21, the second semiconductor device3shown in the uppermost stage inFIG. 19is formed.

FIG. 19is a drawing where three types of semiconductor devices (the first semiconductor device2, the third semiconductor device4and the second semiconductor device3) having been formed in Embodiment 1 are shown in an order of lamination and in a separated fashion. Those three parties of the semiconductor devices2,4and3are aligned so that the connecting portions overlap and the protruding electrodes undergo heating and melting temporally through the furnace body and are joined. As for connection in the connecting portions, heat may be locally applied to the connecting portions so as to carry out connection. In Embodiment 1, the connecting portions between the first semiconductor device2and the third semiconductor device4are protruding electrodes10aand the through-type electrodes12cwhile the connecting portions between the third semiconductor device4and the second semiconductor device3are the post electrodes9cand the protruding electrodes13b. They form a joint. Thus stacked and secured, the stacked semiconductor device1shown inFIG. 1toFIG. 3can be fabricated. The protruding electrodes13aon the lower surface of the first semiconductor device2at the lowest stage will become outside electrode terminals5(seeFIG. 1).

FIG. 20is a schematic sectional view showing amounting state of the stacked semiconductor device1fabricated with the process for fabricating the stacked semiconductor device of Embodiment 1 hereof. The stacked semiconductor device1is mounted on the upper surface of a daughter board45made of a multilayer wiring substrate. The daughter board45has a plurality of bump electrodes46on its lower surface and on its upper surface there formed is a land which is are not shown in the drawing, though. The disposing pattern of the outside electrode terminals5of the stacked semiconductor device1corresponds to the disposing pattern of the above described land. Accordingly, reflow of the outside electrode terminals5enables the stacked semiconductor device1to be mounted onto the daughter board45.

In Embodiment 1 hereof, fabrication technologies on the stacked semiconductor device1have been described, and in consideration as a single product, the first semiconductor device2and the third semiconductor device4can be shipped respectively as a single product. According to the present invention, those semiconductor devices2and4are characterized by causing the through-type electrodes and the post electrodes to become electrodes respectively to protrude from the upper and lower surfaces of the semiconductor devices.

Embodiment 1 hereof gives rise to following effects.

(1) In fabricating the stacked semiconductor device1formed by stacking and securing the first, second and third semiconductor devices2,3and4, the first insulating layers8a,8band8care formed at the first main surface sides of the semiconductor substrates6a,6band6cof the respective semiconductor devices2,3and4and thereafter the second main surfaces of the semiconductor substrates6a,6band6cundergo thickness removal by a specified amount, but since the above described first insulating layers8a,8band8cact as strength members, the semiconductor substrates6a,6band6ccan be made thin to a level of around 5 to 50 μm. Thicknesses of the insulating layers8a,8band8ccan also be made thin to a level of around 20 to 100 μm. Therefore, in the stacked semiconductor device1stacked and secured, the bump electrodes will have heights (thicknesses) of around 200 to 380 μm so that the protruding electrodes by means of printing can be made thin to have heights (thicknesses) of around 150 to 330 μm. Therefore, thinning of the semiconductor devices (integrated circuit devices: three-dimensional integrated circuit devices) of the multilayer stacked structure can be planned.

(2) In the first, the third and the second stacked semiconductor devices, in connecting the semiconductor device at the lower stage side with the semiconductor device at the upper stage side, connection is carried out in utilization of post electrodes to become columnar provided by piercing through the first insulating layer and through-type electrodes to become columnar provided by piercing through the semiconductor substrate, and therefore, the current pathway will get short to make reduction in inductance attainable and to make electrical property of the stacked semiconductor device1good. The post electrodes and through-type electrodes provided in the first insulating layer and semiconductor substrate are short with length (thickness) thereof being around 20 to 100 μm or 5 to 50 μm, and will become sufficiently short compared with length of not less than several hundred micrometers of a bonding wire by means of wire connection. Thereby, high speed operation of the stacked semiconductor device1will become feasible.

(3) There is a constraint that the through-type electrodes provided in the semiconductor substrate is formed in a region apart from the region where circuit elements are formed, and nevertheless disposing locations for wiring regions and the like can be selected comparatively freely. The disposing location for the post electrodes connected with specified wiring of the multilayer wiring part can be determined comparatively freely by deploying wiring. Therefore, selecting locations to provide the through-type electrodes and the post electrodes, improvement in integration density in the two-dimensional direction can be planned.

(4) The stacked semiconductor device1of Embodiment 1 hereof will become capable of electrically connecting the semiconductor device at the lower stage side with the semiconductor device at the upper stage side without using any interposer. Consequently, reduction in the number of assembling parts items can be planned and thinning of the stacked semiconductor device can be planned. Use of interposer will lengthen connecting path (current pathway) between semiconductor chips or between semiconductor devices, but no use of interposer will enable the current pathway to get short so that improvement in electrical property can be planned.

(5) In fabricating the stacked semiconductor device1of Embodiment 1 hereof, the first, the third and the second semiconductor devices2,4, and3are fabricated in use of the semiconductor substrates6a,6cand6b, and the semiconductor substrates6a,6cand6btogether with the insulating layers are cut at the final stage to fabricate the first, the third and the second semiconductor devices2,4and3. Accordingly, since required processing other than stacking and securing the first, the third and the second semiconductor devices2,4and3is carried out on a wafer level, handling performance is good throughout the steps and wasteful work will get less. Consequently, reduction in production costs can be planned.

(6) In fabricating the stacked semiconductor device1of Embodiment 1 hereof, at the stage before the three semiconductor devices2,4and3are stacked and secured, all processing is implemented on a wafer level, and therefore, the process is simplified so as to increase productivity and reduction in fabrication costs of the stacked semiconductor device1can be attained.

(7) According to the process for fabricating the stacked semiconductor device of Embodiment 1 hereof, just planning correspondence of the connecting portions of the semiconductor devices to be vertically overlapped enables the semiconductor devices to be stacked into further abundance of layers, and therefore the stacked semiconductor device1undergoing further sophisticated integration can be fabricated.

(8) In the stacked semiconductor device1of Embodiment 1 hereof, in the structure thereof, as in the above described article (7), except a constraint of planning correspondence of the connecting portions of the semiconductor devices to be vertically overlapped, the circuits formed in respective semiconductor devices can be designed freely. That is, taking the above described constraint as one of designing tools, the stacked semiconductor device1can be designed as if it were one chip. In the current designing tools, only such a designing tool is present in assumption of one chip LSI (corresponding to each semiconductor device of Embodiment 1 hereof).

Under the circumstances, in designing System in Package, simulating what kind of circuit is appropriate for each semiconductor device subject to determination based on performance, costs, simplicity of the test and the like and allocating respective semiconductor devices based on that simulation outcome, the stacked semiconductor device1excellent in electric property and high speed operation performance can be fabricated in compact, thin and inexpensive fashion.

(9) The first semiconductor device2and the third semiconductor device4being single product are structured to cause the through-type electrodes and the post electrodes, that will become electrodes respectively, to protrude from the upper and the lower surface of the semiconductor devices. Due to the above described articles (1) to (3) and articles (5) to (6) deriving from this characteristic and due to simplification of the process, thinning, high speed operation and improvement in density of integration in the two-dimensional direction can be planned even for the single semiconductor device, and reduction in cost for fabrication thereof can be planned due to fabrication in a state of a wafer.

FIG. 21is a schematic sectional view of a stacked semiconductor device being Embodiment 2 of the present invention. Embodiment 2 hereof is configured, in the stacked semiconductor device1of Embodiment 1, to fill a gap between the first semiconductor device2and the third semiconductor device4as well as a gap between the third semiconductor device4and the second semiconductor device3with insulating resin to form underfill layers50and51. With those underfill layers50and51, the gaps are filled and therefore short defects due to incorporation of foreign substance and the like can be prevented. Polyimide resin, for example, as insulating resin is caused to fill the gaps in a vacuum atmosphere and thereafter is hardened subject to bake processing.

FIG. 22(a) andFIG. 22(b) show schematic sectional views of a stacked semiconductor device1of a two-stage stacked and secured type being Embodiment 3 of the present invention. In both ofFIG. 22(a) andFIG. 22(b), the semiconductor substrates6aand6bdisposed upper and the first insulating layers8aand8bdisposed lower have been stacked and secured. In any of them, the protruding electrodes10aon the lower surface of the first semiconductor device2will become outside electrode terminals5. The protruding electrodes13aon the upper surface of the first semiconductor device2will become joints so that the second semiconductor device3is stacked and secured. That is, the protruding electrodes13aattached to the through-type electrodes12aat the upper surface side of the first semiconductor device2are structured to be connected to the post electrodes9bin the lower surface of the second semiconductor device3.

InFIG. 22(a), the second semiconductor device3is structured so that no electrode is exposed at its upper surface side, that is, is structured so that the semiconductor substrate6bis provided with no through-type electrode12b.

In contrast, inFIG. 22(b), the semiconductor substrate6bat the upper surface side of the second semiconductor device3is provided with through-type electrodes12b. The through-type electrodes12bare structured to have diameter of the same level as the through-type electrode12bin case of Embodiment 1 and thick through-type electrodes12bshown at the both end sides in the drawing. The thick through-type electrodes12bhave diameter of the same level as the electrode pad as described with reference toFIG. 10, and, for example, can be connected with wires. That is, they can be connected with the pads of a daughter board with electrically conductive wires.

In contrast, a plurality of thin through-type electrodes12bas those in Embodiment 1 are configured, for example, to be connected to one end of the electrode plate55connected to the ground of the daughter board. According to the present embodiment, due to a structure to expose the through-type electrodes12bin the upper surface of the second semiconductor device3at the upper stage, the degree of allowance for circuit designing (implementation designing) inclusive of the daughter board increases.

In the present embodiment, active elements (active parts) such as chip resistors, chip capacitors, chip inductor and the like may be mounted at the upper surface side of the second semiconductor device3. Electrodes of respective active elements are electrically connected with the through-type electrodes12b. Such configuration will increase the integration level.

FIG. 23andFIG. 24are drawings related to a process for fabricating stacked semiconductor device being Embodiment 4 of the present invention. In Embodiment 4 hereof, substantially likewise the case of Embodiment 1, the stacked semiconductor device1is fabricated through stages of Step S11to Step S22, but the first semiconductor device2is connected with the third semiconductor device4with inter-metal joint by means of ultrasonic oscillation without using any protruding electrode. Therefore, a portion thereof is different in fabrication.

As shown inFIG. 23(a), in fabricating the first semiconductor device2, after the post electrodes9aprovided at the first main surface side of the semiconductor substrate6aare covered with the first insulating layer8a, primary hardening processing to implement processing of hardening resin insufficiently is implemented at the time of hardening processing (cure) of the first insulating layer8a.

Next, as shown inFIG. 23(b), the surface of the first insulating layer8ais ground by specified thickness and is removed so as to expose the post electrode9a.

As shown inFIG. 23(c), such secondary hardening processing (cure) that the first insulating layer8aaccompanies hardening contraction is implemented to expose forward ends of the post electrodes9aon the surface of the first insulating layer8a. For example, length of protrusion is around 10 μm. That protrusion length is length required for implementing inter-metal joint by means of ultrasonic oscillation effectively.

Next, the first semiconductor device2, the third semiconductor device4and the second semiconductor device3undergo positioning and are stacked.FIG. 24(a) shows an order of lamination, and is a drawing in which the first semiconductor device2is positioned in the lowest layer, the third semiconductor device4is positioned thereabove, and the second semiconductor device3is positioned apart thereon.

There, nothing is shown in particular in the drawing, but the third semiconductor device4undergoes positioning and is disposed on the first semiconductor device2, and the post electrodes9amade of Cu on the upper surface of the first semiconductor device2are rubbed to the through-type electrodes12cmade of Cu on the lower surface of the third semiconductor device4by relatively applying ultrasonic oscillation so that rubbed surfaces between the post electrodes9aand through-type electrodes12care connected by inter-metal joint (metal joint). Thereafter, the second semiconductor device3is stacked and secured on the third semiconductor device4by the same process as in Embodiment 1 to fabricate the stacked semiconductor device1as shown inFIG. 24(b).

In this example, the gap between the first semiconductor device2and the third semiconductor device4is filled with an insulating underfill layer50and the gap between the third semiconductor device4and the second semiconductor device3is filled with an insulating underfill layer51.

The present embodiment is characterized in that, when the first semiconductor device2and the third semiconductor device4are stacked and secured, no protruding electrode is used, and therefore further thinning processing can be planned.

FIG. 25(a) andFIG. 25(b) show sectional views of respective steps showing a part of a process for fabricating a stacked semiconductor device being Embodiment 5 of the present invention. Embodiment 5 hereof is an example of stacking and securing with metal joint likewise Embodiment 4. In this example, after the third semiconductor device4is stacked and secured onto the first semiconductor device2by metal joint, the third semiconductor device4is stacked and secured onto the third semiconductor device4by metal joint. In the present embodiment, likewise Embodiment 4, at the time of fabricating the first semiconductor device2and the third semiconductor device4, the forward ends of the post electrodes9aand9cof the first semiconductor device2and the third semiconductor device4are caused to protrude from the surface of the first insulating layers8aand8cby around 10 μm.

FIG. 25(a) shows an order of lamination, and is a drawing in which the first semiconductor device2is positioned in the lowest layer, the third semiconductor device4is positioned thereabove, and the second semiconductor device3is positioned apart thereon.

There, nothing is shown in particular in the drawing, but the third semiconductor device4undergoes positioning and is disposed on the first semiconductor device2, and the post electrodes9amade of Cu on the upper surface of the first semiconductor device2are rubbed to the through-type electrodes12cmade of Cu on the lower surface of the third semiconductor device4by relatively applying ultrasonic oscillation so that rubbed surfaces between the post electrodes9aand through-type electrodes12care connected by inter-metal joint (metal joint).

Next, likewise, nothing is shown in particular in the drawing, but the second semiconductor device3undergoes positioning and is disposed on the third semiconductor device4, and the post electrodes9cmade of Cu on the upper surface of the third semiconductor device4are rubbed to the through-type electrodes12bmade of Cu on the lower surface of the second semiconductor device3by relatively applying ultrasonic oscillation so that rubbed surfaces between the post electrodes9cand through-type electrodes12bare connected by inter-metal joint (metal joint).

In this example, the gap between the first semiconductor device2and the third semiconductor device4is filled with an insulating underfill layer50and the gap between the third semiconductor device4and the second semiconductor device is filled with an insulating underfill layer51.

The present embodiment is characterized in that, when the first semiconductor device2and the third semiconductor device4are stacked and secured and the third semiconductor device4and the second semiconductor device3are stacked and secured, no protruding electrode is used, and therefore further thinning processing can be planned.

FIG. 26is a schematic sectional view of a state showing the stacked semiconductor device according to Embodiment 6 of the present invention having been mounted in a daughter board. In Embodiment 6 hereof, the first semiconductor device2, the second semiconductor device3and the third semiconductor device4of the stacked semiconductor device1are stacked and secured in such a state that any of the semiconductor substrates6a,6band6cis located at the upper surface side and the first insulating layers8a,8band8care located at the lower surface side. And the first semiconductor device2is mounted onto the daughter board45by connecting the protruding electrodes10aof the first semiconductor device2with lands not shown in the drawing of the daughter board45.

FIG. 27is a schematic sectional view of a state showing the stacked semiconductor device according to Embodiment 7 of the present invention having been mounted in a daughter board. The present embodiment is a mixed type with the first semiconductor device2and the second semiconductor device3of the stacked semiconductor device1being stacked and secured in such a state that the semiconductor substrates6aand6bare located at the upper surface side and the first insulating layers8aand8bare located at the lower surface side, and for the third semiconductor device4, being stacked and secured in such a state that the semiconductor substrate6cis located at the lower surface side and the first insulating layer8cis located at the upper surface side. And the first semiconductor device2is mounted onto the daughter board45by connecting the protruding electrodes10aof the first semiconductor device2with lands not shown in the drawing of the daughter board45.

FIG. 28is a schematic sectional view of a state showing the stacked semiconductor device according to Embodiment 8 of the present invention having been mounted on a daughter board. Embodiment 8 hereof is structured so that a plurality of semiconductor devices4A and4B being the middle stage third semiconductor devices4smaller than the first semiconductor device2are disposed and secured in parallel on the first semiconductor device2, and semiconductor devices3A and3B to become the second semiconductor devices3are stacked and secured respectively on those semiconductor devices4A and4B. That is, in Embodiment 8 hereof, a great number of middle stage third semiconductor devices4are disposed in parallel in plurality on the first semiconductor device2with the largest area, and, moreover, the upper stage second semiconductor devices3are stacked and secured respectively on those third semiconductor devices4. The middle stage third semiconductor device may consist of a plurality of stages to be stacked and secured between the lower stage first semiconductor device and the upper stage second semiconductor device so as to further improve integration level.

In Embodiment 8 hereof, among the above described first to third semiconductor devices, the above described semiconductor substrate of one semiconductor device is a silicon substrate and the above described semiconductor substrate of another semiconductor device is a compound semiconductor substrate. And circuit elements suitable for respective semiconductor substrates are formed. For example, the semiconductor substrate6aof the first semiconductor device2is a silicon substrate and the semiconductor substrate6cA of the semiconductor device3A is a compound semiconductor (for example, a GaAs substrate). The semiconductors at the middle stage and the upper stage, almost all the symbols will be omitted. However, in necessity for descriptions, the middle stage third semiconductor devices4A and4B will be provided with A or B at the ends for depiction. The upper stage second semiconductor devices3A and3B will be provided with A or B at the ends for depiction.

In Embodiment 8, semiconductor devices are designated for all parts to be incorporated in the stacked semiconductor device1, but the other electronic parts may be stacked and secured. For example, chip parts such as resistors, capacitors and the like, MEMS (Micro electro Mechanical System), biochips and the like may be stacked and secured. Silicon substrates as semiconductor substrates and compound semiconductor substrates as semiconductor substrate may be present more in number.

According to Embodiment 8 hereof, further intensive integration is attained.

FIG. 29is a schematic sectional view of a state showing the stacked semiconductor device according to Embodiment 9 of the present invention having been mounted on a daughter board. Embodiment 9 hereof is an example in which, in Embodiment 8, a metal plate60is sandwiched between the first semiconductor device2and the semiconductor device4B thereabove and a metal plate70is sandwiched between the semiconductor device4B and the semiconductor device3B. Circuitwise, for example, the metal plate70is configured to be given the ground potential and the metal plate60is configured to be given the power supply potential (reference potential) such as Vcc and the like.

That is, the metal plate60having insulating holes61is present between the first semiconductor device2and the semiconductor device4B. In the portion of the insulating holes61, the through-type electrodes12aon the upper surface of the first semiconductor device2are electrically connected with the post electrodes9cB on the lower surface of the semiconductor device4B through the protruding electrodes13aand the protruding electrodes10cB in a state without contacting the metal plate60.

The through-type electrodes12aof the first semiconductor device2and the semiconductor device4B to face the metal plate60are electrically connected with the post electrodes9cB on the lower surface of the semiconductor device4B through the protruding electrodes13aand the protruding electrodes10cB. Since inter position of the metal plate60lengthens the distance between the through-type electrodes12aand the post electrodes9cB, the protruding electrodes13aand the protruding electrodes10cB used for connection in the portion of the insulating holes61are made larger than the protruding electrodes13aand the protruding electrodes10cB connected to the metal plate60.

In addition, the metal plate70having insulating holes71is present between the semiconductor device4B and the semiconductor device3B as well. In the portion of the insulating holes71, the through-type electrodes12bB on the upper surface of the semiconductor device4B are electrically connected with the post electrodes9bB on the lower surface of the semiconductor device3B through the protruding electrodes13cB and the protruding electrodes10bB in a state without contacting the metal plate70. The through-type electrodes12cB of the semiconductor device4B and the post electrodes9bB of the semiconductor device3B to face the metal plate70are brought into electrical connection through the protruding electrodes13cB and the protruding electrodes10bB. Since interposition of the metal plate70lengthens the distance between the through-type electrodes12cB and the post electrodes9bB, the protruding electrodes13cB and the protruding electrodes10bB used for connection in the portion of the insulating holes71are made larger than the protruding electrodes13cB and the protruding electrodes10bB connected to the metal plate70.

The gap between the first semiconductor device2and the semiconductor device4B is filled with an underfill layer80and the gap between the semiconductor device4B and the semiconductor device3B is filled with an underfill layer81.

According to Embodiment 9 hereof, presence of the metal plate70given the ground potential and the metal plate60given the power supply potential (reference potential) such as Vcc and the like stabilizes the power supply as well as the ground of the stacked semiconductor device1, and consequently stabilizes operations and can derive good electrical property.

So far, the invention attained by the present inventor has been described in particular based on embodiments, and nevertheless the present invention will not be limited to the above described embodiments, but it goes without saying that various changes can be made without departing the gist thereof. In the embodiments, the post electrodes have been formed with plating but may be formed with stud bumps. Stud bumping is a system of connecting a gold wire with an electrode pad with a thermo compression method (ball bonding method) to form a nail head, and thereafter cutting the wire in the base portion of that nail head to form protruding electrodes which are stacked in many stages.

INDUSTRIAL APPLICABILITY

As described above, the stacked semiconductor device related to the present invention can be used as a thin three-dimensional integrated circuit device suitable for high speed operation. In addition, the stacked semiconductor device related to the present invention allows allocation of respective semiconductor devices in the stacked semiconductor device subject to simulation based on determination on performance, costs, simplicity of the test and the like in designing System in Package. Therefore, according to the present invention, the stacked semiconductor device being excellent in electric property and high speed operation performance and to become compact and thin and inexpensive can be provided.