Wafer level chip scale package system

A wafer level chip scale package system is provided including placing a first integrated circuit over a semiconductor wafer having a second integrated circuit; connecting a second electrical interconnect between the first integrated circuit and the second integrated circuit; forming a stress relieving encapsulant on the outer perimeter of the second integrated circuit for covering the second electrical interconnect; and singulating a chip scale package, from the semiconductor wafer, through the stress relieving encapsulant and the semiconductor wafer.

TECHNICAL FIELD

The present invention relates generally to integrated circuit packaging, and more particularly to a system for wafer level manufacturing of stackable integrated circuit packages.

BACKGROUND ART

Today the drive for miniaturization is exemplified by the cellular telephone industry. A few years ago large phones that allowed you to stay in touch were widely accepted. Today a cellular telephone must fit easily in the palm of your hand, even for a small woman or a child. The phone is also not for just keeping in touch. It has wireless internet access, a camera with video recording, embedded games and the ability to store the number for every person that you have ever dialed accompanied by their picture. In order to achieve this level of function packed into a very small space, package technology has made dramatic changes to enable the innovation.

Chip-on-board and board-on-chip (BOC) techniques are used to attach semiconductor dies to an interposer or other carrier substrate such as a printed circuit board (PCB). Attachment can be achieved through flip chip attachment, wire bonding, or tape automated bonding (“TAB”). Flip chip attachment typically utilizes ball grid array (BGA) technology. The BGA component (die) includes conductive external contacts, typically in the form of solder balls or bumps, arranged in a grid pattern on the active surface of the die, which permit the die to be flip chip mounted to an interposer or other carrier substrate (e.g., PCB).

In a flip chip attachment, the balls of the BGA component are aligned with terminals on the carrier substrate, and connected by reflowing the solder balls. The solder balls can be replaced with a conductive polymer that is cured. A dielectric under-fill is then interjected between the flip chip die and the surface of the carrier substance to embed the solder balls and mechanically couple the BGA component to the carrier substrate.

Wire bonding and TAB attachment generally involve attaching a die by its backside to the surface of a carrier substrate with an appropriate adhesive (e.g., epoxy) or tape. With wire bonding, bond wires are attached to each bond pad on the die and bonded to a corresponding terminal pad on the carrier substrate (e.g., interposer). With TAB, ends of metal leads carried on a flexible insulating tape such as a polyimide, are attached to the bond pads on the die and to the terminal pads on the carrier substrate. A dielectric (e.g., silicon or epoxy) is generally used to cover the bond wires or metal tape leads to prevent damage.

High performance, low cost, increased miniaturization of components, and greater packaging density of integrated circuits have long been goals of the computer industry. One method of increasing integrated circuit density while reducing package size and height is to stack dies vertically. Different approaches to packaging have been pursued to provide stacked die devices.

One such example of a stacked die to lower wire bond loop height is to mount a flip chip die on a chip-on-board (“FC-on-chip”). The package includes a flip chip die mounted via solder bumps with the active surface facing down onto the active surface of a bottom die (chip-on-board), which in turn, is mounted with an adhesive tape or paste onto an interposer substrate. Bonding wires connect the bond pads on the bottom die to lead or trace ends on the interposer. The interposer could include solder balls for mounting the encapsulated package (component) onto a substrate, e.g., motherboard or PCB.

Flip chip attachment has provided improved electrical performance and allowed greater packaging density. However, developments in ball grid array technology have produced arrays in which the balls are made smaller and with tighter pitch. As the balls become smaller and are set closer together, it poses problems for the mutual alignment of the conductive bumps on the flip chip die with the bond pads on the bottom die, requiring a metal reroute or redistribution layer (RDL) disposed as an intermediate layer on the surface of the bottom die. The RDL effects an electrical interconnection (redistribution) between the bond pads on the flip chip die to the bond pads on the bottom die for die attachment and wire bonding to the substrate.

Fabricating an FC-on-chip can also lead to high costs and process difficulties. For Example, a flip chip mounting device is required to accurately align the top die to the bottom die. Another drawback is that damage can occur to the active surface of the bottom die during an under-filling process onto the active surface, and a molding filler can fail to flow into voids between the dies if the gap is too small.

Thus, a need still remains for a wafer level chip scale package. In view of the enormous demand for smaller and more intelligent electronic devices, it is increasingly critical that answers be found to these problems. In view of the ever-increasing commercial competitive pressures, along with growing consumer expectations and the diminishing opportunities for meaningful product differentiation in the marketplace, it is critical that answers be found for these problems. Additionally, the need to save costs, improve efficiencies and performance, and meet competitive pressures, adds an even greater urgency to the critical necessity for finding answers to these problems.

Solutions to these problems have long been sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.

DISCLOSURE OF THE INVENTION

The present invention provides a wafer level chip scale package system including placing a first integrated circuit over a semiconductor wafer having a second integrated circuit; connecting a second electrical interconnect between the first integrated circuit and the second integrated circuit; forming a stress relieving encapsulant on the outer perimeter of the second integrated circuit for covering the second electrical interconnect; and singulating a chip scale package, from the semiconductor wafer, through the stress relieving encapsulant and the semiconductor wafer.

BEST MODE FOR CARRYING OUT THE INVENTION

In the following description, numerous specific details are given to provide a thorough understanding of the invention. However, it will be apparent that the invention may be practiced without these specific details. In order to avoid obscuring the present invention, some well-known circuits, system configurations, and process steps are not disclosed in detail. Likewise, the drawings showing embodiments of the system are semi-diagrammatic and not to scale and, particularly, some of the dimensions are for the clarity of presentation and are shown greatly exaggerated in the drawing FIGs. Where multiple embodiments are disclosed and described, having some features in common, for clarity and ease of illustration, description, and comprehension thereof, similar and like features one to another will ordinarily be described with like reference numerals.

For expository purposes, the term “horizontal” as used herein is defined as a plane parallel to the plane or surface of the semiconductor wafer, regardless of its orientation. The term “vertical” refers to a direction perpendicular to the horizontal as just defined. Terms, such as “above”, “below”, “bottom”, “top”, “side” (as in “sidewall”), “higher”, “lower”, “upper”, “over”, and “under”, are defined with respect to the horizontal plane. The term “on” means there is direct contact among elements. The term “system” means the method and the apparatus of the present invention. The term “processing” as used herein includes stamping, forging, patterning, exposure, development, etching, cleaning, sawing, and/or removal of the material or laser trimming as required in forming a described structure.

Referring now toFIG. 1, therein is shown a cross-sectional view of a wafer level chip scale package system100, in an embodiment of the present invention. The cross-sectional view of the wafer level chip scale package system100depicts a first integrated circuit102with an adhesive104, such as a die attach material, attached to a component side106of a package substrate108. A first wire bond pad110, on the component side106of the package substrate108, is coupled to the first integrated circuit102by a first electrical interconnect112, such as a bond wire. A molded cap114, such as an epoxy molding compound, encapsulates the first integrated circuit102, the first electrical interconnect112and the component side106of the package substrate108. A system side116of the package substrate108has a contact pad118for electrical connection of a system interconnect120, such as a solder ball, solder column, or stud bump. A second wire bond pad122is formed on the system side116of the package substrate108for further connection. The combination forms a base package124.

The base package124is adhesively bonded, in an inverted position, directly to an active surface126of a second integrated circuit128by the adhesive104. The base package124may be positioned on the active surface126of the second integrated circuit128by a pick and place machine (not shown). The position of the base package124is controlled in order to keep all of the connection paths as short as possible. A second electrical interconnect130, such as a bond wire, electrically connects the second integrated circuit128to the second wire bond pad122on the system side116of the package substrate108. A stress relieving encapsulant132, such as an under-fill material, encloses the second wire bond pad122, the second electrical interconnect130, and the active surface126of the second integrated circuit128.

It has been discovered that the wafer level chip scale package system100may provide a better overall yield than other processes because the base package can be completely tested prior to assembly on the wafer tested die. The subsequent assembly and singulation processes are well known and in high volume production.

Referring now toFIG. 2, therein is shown a cross-sectional view of a wafer level chip scale package system200in an alternative embodiment of the present invention. The cross-sectional view of the wafer level chip scale package system200depicts the first integrated circuit102with the adhesive104, such as a die attach material, attached to a system side202of a package substrate204. The first wire bond pad110, on the system side202of the package substrate204, is coupled to the first integrated circuit102by the first electrical interconnect112, such as a bond wire. The molded cap114, such as an epoxy molding compound, encapsulates the first integrated circuit102, the first electrical interconnect112and a portion of the system side202of the package substrate204. The contact pad118is positioned between the molded cap114and the second wire bond pad122. The system interconnect120is coupled to the contact pad118forming a base package206. The adhesive104, such as a die attach material, is attached to a backside208of the package substrate204.

The base package206is mounted on the active surface126of the second integrated circuit128. The second electrical interconnect130may be coupled between the active surface126of the second integrated circuit128and the second wire bond pad122forming an electrical connection between the second integrated circuit128, the first integrated circuit102, the system interconnect128, or a combination thereof. The stress relieving encapsulant132, such as an under-fill material, protects the second electrical interconnect130and the active surface126of the second integrated circuit128.

Referring now toFIG. 3, therein is shown the system side202view of the base package206as shown inFIG. 2. The system side202view of the base package206depicts the package substrate204having the molded cap114positioned in the center of the system side202. A row of the second wire bond pad122extends around the periphery of the package substrate204. A single row of the system interconnect120is positioned between the molded cap114and the row of the second wire bond pad122.

This geometry is an example only and it is understood that the geometry of the base package206may differ. A smaller version of the molded cap114would allow room for a double row of the system interconnects, as an example. The number and position of the rows of the second wire bond pad122is also for the example, as any number of the second wire bond pad122that meet the physical design limitations of the package substrate204technology would be possible. The pitch and position of the system interconnect120are also limited only by the tolerances of the assembly.

Referring now toFIG. 4, therein is shown a bottom view of the base package124as shown inFIG. 1. The bottom view of the base package124depicts the package substrate108having the system side116with an array of the system interconnect120. A row of the second wire bond pad122extends around the periphery of the package substrate108. The number and spacing of the system interconnect120and the second wire bond pad122is by way of example only and no limitation is implied by the drawing.

Referring now toFIG. 5, therein is shown a bottom view of a base package500as shown inFIG. 1with an alternative ball pattern. The bottom view of the base package500depicts the package substrate108having the system side116with an array of the system interconnect120. A row of the second wire bond pad122extends around the periphery of the package substrate108. The number and spacing of the system interconnect120and the second wire bond pad122is by way of example only and no limitation is implied by the drawing. The areas that are missing the system interconnect120may be for allowing a clearance around some structure on the printed circuit board (not shown) or a low profile discrete component that is placed on the printed circuit board (not shown).

Referring now toFIG. 6, therein is shown a bottom view of a base package600as shown inFIG. 1with another alternative ball pattern. The bottom view of the base package600depicts the package substrate108having the system side116with an array of the system interconnect120. A row of the second wire bond pad122extends around the periphery of the package substrate108. The number and spacing of the system interconnect120and the second wire bond pad122are by way of example only and no limitation is implied by the drawing.

A first pattern602of the system interconnect120may have a higher density of the system interconnect120than a second pattern604. The first pattern602and the second pattern604may be of any size, pitch, and configuration. In this example the first pattern602may be used to voltages or low frequency signals, while the second pattern604may be used for higher frequency signals that might create a cross-talk problem if they were in a closer proximity to each other.

Referring now toFIG. 7, therein is shown a bottom view of a base package700as shown inFIG. 1with yet another alternative ball pattern. The bottom view of the base package700depicts the package substrate108having the system side116with an array of the system interconnect120. A row of the second wire bond pad122extends around the periphery of the package substrate108. The number and spacing of the system interconnect120and the second wire bond pad122is by way of example only and no limitation is implied by the drawing.

A core pattern702of the system interconnect120may be used for connecting the first integrated circuit102ofFIG. 1to a printed circuit board (not shown). The outer ring of the system interconnect120may be used for connecting the second integrated circuit128ofFIG. 1which is not yet coupled to the base package700. The number and position of the system interconnect120may be changed to meet the requirements of the application.

Referring now toFIG. 8, therein is shown a cross-sectional view of the base package124in a wafer mount phase of manufacturing. The cross-sectional view of the base package124depicts a semiconductor wafer802, having a wafer bond pad804coupled to the second integrated circuit128ofFIG. 1formed thereon. The adhesive104, such as a die attach material, placed over the second integrated circuit is attached to the molded cap114of the base package124.

The base package124and the adhesive104are precisely placed to allow a wire bonding machine (not shown) to have access to the wafer bond pad804and the second wire bond pad122. The placement of the base package124and the adhesive may be performed by a robotic device (not shown).

Referring now toFIG. 9, therein is shown a cross-sectional view of the base package206in a wafer mount phase of manufacturing. The cross-sectional view of the base package206depicts a pick and place machine902positioning the base package206with the adhesive104attached. The pick and place machine902is normally used to position integrated circuit packages (not shown) on a printed circuit board (not shown). The pick and place machine902may be optically aligned and capable of very fine position adjustments in a volume manufacturing environment.

The base package206and the adhesive may be precisely positioned and attached to the semiconductor wafer802, such that the base package206is centered between the wafer bond pad804formed on each side of the second integrated circuit128ofFIG. 1. Each of the tested locations on the semiconductor wafer802may have the base package206and the adhesive104applied during the operation. In this way potentially the semiconductor wafer802may be entirely covered with the base package206and the adhesive104in preparation for the next phase of manufacturing.

Referring now toFIG. 10, therein is shown a cross-sectional view of the base package124ofFIG. 1in a wire bonding phase of manufacturing. The cross-sectional view of the base package124depicts the semiconductor wafer802having the base package124adhered to locations across the semiconductor wafer802. The second electrical interconnect130, such as a bond wire, is applied to the wafer bond pad804and the second wire bond pad122. The operation completes the coupling between the second integrated circuit128, ofFIG. 1having the wafer bond pad804and the base package124having the second wire bond pad122.

Referring now toFIG. 11, therein is shown a cross-sectional view of the base package206ofFIG. 2in a wire bonding phase of manufacturing. The cross-sectional view of the base package206depicts the semiconductor wafer802having the base package206adhered to locations across the semiconductor wafer802. The second electrical interconnect130, such as a bond wire, is applied to the wafer bond pad804and the second wire bond pad122. The operation completes the coupling between the second integrated circuit128, ofFIG. 1having the wafer bond pad804and the base package206having the second wire bond pad122.

Referring now toFIG. 12, therein is shown a top view of the wafer level chip scale package system200ofFIG. 2in a package molding phase of manufacturing. The top view of the wafer level chip scale package system200depicts the semiconductor wafer802having the base package206mounted over the active surface126of the semiconductor wafer802.

A dam material1202is formed around the edge of the semiconductor wafer and over the edge of the base package206. The dam material forms a reservoir1204that may be filled with the stress relieving encapsulant132. The stress relieving encapsulant is poured over the active surface126of the semiconductor wafer802and the electrical interconnects130ofFIG. 1. A section-line13-13depicts the view forFIG. 13.

Referring now toFIG. 13, therein is shown a cross-sectional view of the wafer level chip scale package system200ofFIG. 12along the section line13-13. The cross-sectional view of the wafer level chip scale package system200depicts the semiconductor wafer802having the wafer bond pad804the base package206is mounted over the semiconductor wafer802on the adhesive104. The dam material1202forms the reservoir1204for the stress relieving encapsulant132. The stress relieving encapsulant132, such as an under-fill material, is formed on the second electrical interconnect130and the active surface126of the semiconductor wafer802. The stress relieving encapsulant132protects the second electrical interconnect130.

Referring now toFIG. 14, therein is shown a cross-sectional view of the wafer level chip scale package system200ofFIG. 12in a singulation phase of manufacturing. The cross-sectional view of the wafer level chip scale package system200depicts the semiconductor wafer802mounted in a dicing frame1402and held by a dicing tape1404. A singulation saw1406may be used to singulate a chip scale package1408. The singulation saw1406is used to cleave the section of the semiconductor wafer802covered by the stress relieving encapsulant132. When the dicing tape1404is released the chip scale package1408is realized. The system interconnect120allows electrical connection to the next level system, such as a printed circuit board. The use of the singulation saw1406and dicing tape1404is for example and it is understood that the singulation process may include other singulation tools, such as a laser scribe or a diamond edge scribe.

Referring now toFIG. 15, therein is shown a cross-sectional view of the wafer level chip scale package system100in a package on package structure1500with a wire bond BGA package. The cross-sectional view of the wafer level chip scale package system100in the package on package structure1500depicts a third integrated circuit1502, such as a wire bond integrated circuit, on a layer of the adhesive104that is on a stacking substrate1504. The stacking substrate1504has a stacking contact1506on a component side1508and a system contact1510on a system side1512. The third integrated circuit1502is coupled to the stacking substrate1504by the second electrical interconnect130, such as a bond wire.

The molded cap114, such as an epoxy molding compound molded into a cap, is on the third integrated circuit1502, the second electrical interconnect130, and a portion of the component side1508of the stacking substrate1504. The system interconnect120is coupled to the system contact1510on the system side1512of the stacking substrate1504. The wafer level chip scale package system100is coupled to the stacking contact1506completing the structure.

The package on package structure1500can very efficiently couple three or more of the integrated circuits in a space the size of the second integrated circuit128. This configuration is an example only and it is understood that the stacking substrate1504may support more than the third integrated circuit1502.

Referring now toFIG. 16, therein is shown a cross-sectional view of the wafer level chip scale package system100in a package on package structure1600with a flip chip BGA package. The cross-sectional view of the wafer level chip scale package system100in the package on package structure1600depicts a third integrated circuit1602, such as a flip chip integrated circuit, on a stacking substrate1604. The stacking substrate1604has a stacking contact1606on a component side1608and a system contact1610on a system side1612.

The third integrated circuit1602is coupled to the stacking substrate1604by an interconnect1614, such as a solder ball, solder column, or stud bump. An adhesive material1616, such as an under-fill material, is used to protect the interconnect1614. The system interconnect120is coupled to the system contact1610on the system side1612of the stacking substrate1604. The wafer level chip scale package system100is coupled to the stacking contact1606completing the structure.

The package on package structure1600can very efficiently couple three or more of the integrated circuits in a space the size of the second integrated circuit128. This configuration is an example only and it is understood that the stacking substrate1604may support more than the third integrated circuit1602.

Referring now toFIG. 17, therein is shown a cross-sectional view of the wafer level chip scale package system200in a package on package structure1700with an inverted wire bond BGA package. The a cross-sectional view of the wafer level chip scale package system200in the package on package structure1700depicts a third integrated circuit1702, such as a wire bond integrated circuit, on a layer of the adhesive104that is on a stacking substrate1704. The stacking substrate1704has a stacking contact1706on a top side1708and a system contact1710on a system side1712. The third integrated circuit1702is coupled to the system side1712of the stacking substrate1704by the second electrical interconnect130, such as a bond wire.

The molded cap114, such as an epoxy molding compound molded into a cap, is on the third integrated circuit1702, the second electrical interconnect130, and a portion of the system side1712of the stacking substrate1704. The system interconnect120is coupled to the system contact1710on the system side1712of the stacking substrate1704. The wafer level chip scale package system200is coupled to the stacking contact1706completing the structure.

The package on package structure1700can very efficiently couple three or more of the integrated circuits in a space the size of the second integrated circuit128. This configuration is an example only and it is understood that the stacking substrate1704may support more than the third integrated circuit1702.

Referring now toFIG. 18, therein is shown a cross-sectional view of the wafer level chip scale package system200in a package on package structure1800with an inverted flip chip BGA package. The cross-sectional view of the wafer level chip scale package system200in the package on package structure1800depicts a third integrated circuit1802, such as a flip chip integrated circuit, on a stacking substrate1804. The stacking substrate1804has a stacking contact1806on a component side1808and a system contact1810on a system side1812.

The third integrated circuit1802is coupled to the system side1812of the stacking substrate1804by an interconnect1814, such as a solder ball, solder column, or stud bump. An adhesive material1816, such as an under-fill material, is used to protect the interconnect1814. The system interconnect120is coupled to the system contact1810on the system side1812of the stacking substrate1804. The wafer level chip scale package system200is coupled to the stacking contact1806completing the structure.

The package on package structure1800can very efficiently couple three or more of the integrated circuits in a space the size of the second integrated circuit128. This configuration is an example only and it is understood that the stacking substrate1804may support more than the third integrated circuit1802.

Referring now toFIG. 19, therein is shown a flow chart of a wafer level chip scale package system1900for manufacturing the wafer level chip scale package system100in an embodiment of the present invention. The system1900includes placing a first integrated circuit on a semiconductor wafer having a second integrated circuit in a block1902; connecting a second electrical interconnect between the first integrated circuit and the second integrated circuit in a block1904; forming a stress relieving encapsulant on the outer perimeter of the second integrated circuit for covering the second electrical interconnect in a block1906; and singulating a chip scale package, from the semiconductor wafer, through the stress relieving encapsulant and the semiconductor wafer in a block1908.

Thus, it has been discovered that the wafer level chip scale package system of the present invention furnishes important and heretofore unknown and unavailable solutions, capabilities, and functional aspects for multi-chip integrated circuit packaging. The resulting processes and configurations are straightforward, cost-effective, uncomplicated, highly versatile and effective, can be surprisingly and unobviously implemented by adapting known technologies, and are thus readily suited for efficiently and economically manufacturing integrated circuit devices fully compatible with conventional manufacturing processes and technologies. The resulting processes and configurations are straightforward, cost-effective, uncomplicated, highly versatile, accurate, sensitive, and effective, and can be implemented by adapting known components for ready, efficient, and economical manufacturing, application, and utilization.