Semiconductor integrated circuit design tool, computer implemented method for designing semiconductor integrated circuit, and method for manufacturing semiconductor integrated circuit

A semiconductor integrated circuit design tool includes a reference data defining module configured to define design data of one of a plurality of transistors implementing the semiconductor integrated circuit as reference data, a simulator configured to simulate each effective channel length of the transistors, based on the design data and a reference channel length based on the reference data, and an adjuster configured to adjust gate lengths of gate electrodes of the transistors to reduce a difference between the effective channel length and the reference channel length.

This application is based upon and claims the benefit of priority from prior Japanese Patent Application P2004-235528 filed on Aug. 12, 2004; the entire contents of which are incorporated by reference herein.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to design process for a semiconductor integrated circuit and in particular to a semiconductor integrated circuit design tool, a computer implemented method for designing a semiconductor integrated circuit, and a method for manufacturing a semiconductor integrated circuit.

2. Description of the Related Art

In a manufacturing process of a semiconductor integrated circuit, unifying electrical characteristics of a plurality of transistors is a crucial factor to improve the defect rate. To unify the electrical characteristics of insulated gate transistors such as the MOS transistors, variability of gate electrode lengths caused by the optical proximity effect (OPE) and the loading effect should be eliminated. In Japanese Patent Laid-Open Publication No. Hei 10-200109, a method to reduce such variability of the gate electrode lengths by disposing dummy patterns around the gate electrode pattern in a photomask is proposed.

However, even though the variability of the gate electrode lengths is reduced at the mask level, the effective channel lengths of the transistors may vary dependent on the surface area of the impurity region formed by the ion implantation process, since such effective channel lengths depend on the diffusion of the dopants by the annealing process. Such effective channel length variability leads the electrical characteristics per unit channel length to unevenness. When the number of the doped dopants and the number of point defects in the impurity regions are varied dependent on the surface area of the impurity regions, such effective channel length variability generates. In addition, when the decay time of the point defects are affected by the volume restriction of the impurity region surrounded by a trench isolation region, the diffusion of the doped dopants by the annealing process becomes uneven in the semiconductor substrate.

SUMMARY OF THE INVENTION

An aspect of present invention inheres in a semiconductor integrated circuit design tool according to an embodiment of the present invention. The tool includes a reference data defining module configured to define design data of one of a plurality of transistors implementing the semiconductor integrated circuit as reference data. A simulator is configured to simulate each effective channel length of the transistors based on the design data and a reference channel length based on the reference data. An adjuster is configured to adjust gate lengths of gate electrodes of the transistors to reduce a difference between the effective channel length and the reference channel length.

Another aspect of the present invention inheres in a computer implemented method for designing semiconductor integrated circuit according to the embodiment of the present invention. The method includes defining design data of one of transistors implementing the semiconductor integrated circuit as reference data, simulating each effective channel length of the transistors based on the design data and a reference channel length based on the reference data, and adjusting gate lengths of gate electrodes of the transistors to reduce a difference between the effective channel length and the reference channel length.

Yet another aspect of the present invention inheres in a method for manufacturing the semiconductor integrated circuit according to the embodiment of the present invention. The method includes forming a gate insulator on a semiconductor substrate, depositing a conductive layer on the gate insulator, coating a resist film on the conductive layer, and projecting an image of a photomask onto the resist film to form etching masks on the conductive layer. The photomask has patterns of gate electrodes of which gate lengths are adjusted to reduce a difference between effective channel lengths of transistors implementing the semiconductor integrated circuit, based on designed lengths and designed surface areas of diffusion regions of the transistors. The method also includes etching the conductive layer by using the etching masks to form the gate electrodes, doping dopants into the semiconductor substrate using the gate electrodes as a doping mask, and annealing the semiconductor substrate to activate the dopants to form the diffusion regions in the semiconductor substrate.

DETAILED DESCRIPTION OF THE INVENTION

With reference toFIG. 1, a semiconductor integrated circuit design tool in accordance with an embodiment of the present invention includes a central processing unit (CPU)100and a simulator201connected to the CPU100. The CPU100includes a reference data defining module102and an adjuster400. The reference data defining module102is configured to define design data of one of the plurality of transistors implementing the semiconductor integrated circuit as reference data. The simulator201is configured to simulate each effective channel length of the transistors based on the plurality of design data. Also, the simulator201is configured to simulate a reference channel length based on the reference data. The adjuster400is configured to adjust the gate lengths of the gate electrodes of the transistors to reduce a significant difference between the effective channel length and the reference channel length.

The semiconductor integrated circuit design tool further includes a design data memory305, a mask data memory306, a process recipe memory307, a simulator201, a verification tool251, an input unit301, an output unit302, a program memory303, and a temporary memory304. The CPU100further includes a data interface111an area calculator101, and an optical proximity correction module120.

Here, the design data memory305stores the plurality of design data of the semiconductor integrated circuits containing the transistors. Examples of the plurality of design data of transistors stored in the design data memory305are shown inFIGS. 2 and 4. InFIG. 2, the design data of a first n-channel transistor includes a gate electrode32, a first n+diffusion region12, and a second n+diffusion region22. The gate electrode32is interposed between the first and the second n+diffusion regions12and22. The first and second n+diffusion regions12and22are surrounded by a trench isolation region60. Also, an insulating sidewall spacer61is disposed on the sidewalls of the gate electrode32. InFIG. 4, the design data of a second n-channel transistor includes a gate electrode34A, a first n+diffusion region14A, and a second n+diffusion region24A. The gate electrode34A is interposed between the first and second n+diffusion regions14A and24A. The first and second n+diffusion regions14A and24A are surrounded by a trench isolation region62. An insulating sidewall spacer63is disposed on the sidewalls of the gate electrode34A.

The gate length “a” of the gate electrode32included in the first n-channel transistor shown inFIG. 2is equal to the gate length “a” of the gate electrode34A included in the second n-channel transistor shown inFIG. 4. Also, each gate width “e” of the first and second n+ diffusion regions12and22shown inFIG. 2, in the direction parallel to the longitudinal direction of the gate electrodes32, is equal to each gate width “e” of the first and second n+diffusion regions14A and24A shown inFIG. 4. However, each length “d2” of the first and second n+diffusion regions14A and24A in a gate length direction shown inFIG. 4is longer than each length “d1” of the first and second n+diffusion regions12and22shown inFIG. 2.

With reference again toFIG. 1, the data interface111is configured to fetch the plurality of design data of the plurality of transistors from the design data memory305. The area calculator101is configured to calculate surface areas of the diffusion regions in the transistors by using the design data fetched by the data interface111. For example, the surface area of each of the first and second n+diffusion regions12and22in the first n-channel transistor shown inFIG. 2is “d1*e”, and the surface area of each of the first and second n+ diffusion regions14A and24A in the second n-channel transistor shown inFIG. 4is “d2*e”.

The reference data defining module102shown inFIG. 1classifies the plurality of design data by the length of the diffusion region in the gate length direction. Further, the reference data defining module102defines the design data of the transistor of which the length of the diffusion region in the gate length direction is the shortest as the reference data. For example, if the design data of the first n-channel transistor shown inFIG. 2and the design data of the second n-channel transistor shown inFIG. 4are stored in the design data memory305, the reference data defining module102defines the design data of the first n-channel transistor shown inFIG. 2as the reference data since the length “d1” is shorter than the length “d2”.

The process recipe memory307shown inFIG. 1stores process recipes used for manufacturing each of the plurality of transistors. The process recipes contain conditions for an ion implantation process for forming the diffusion regions of the transistors such as acceleration energy “Eac” and dose. The process recipes also contain conditions for an annealing process that is carried out after the ion implantation process.

The simulator201simulates the structure of the manufactured transistor by using process analysis methods, such as implantation models based on the Monte Carlo method and diffusion models based on the dynamic Monte Carlo method by using the design data of the transistors stored in the design data memory305and the process recipes stored in the process recipe memory307.

FIG. 3is a sectional view taken on line III—III inFIG. 2.FIG. 3shows the structure of the first n-channel transistor simulated by the simulator201shown inFIG. 1. Such structure shown inFIG. 3is simulated based on the conditions for the ion implantation and the subsequent annealing processes for manufacturing the first n-channel transistor stored in the process recipe memory307and the design data of the first n-channel transistor shown inFIG. 2.

FIG. 5is a sectional view taken on line V—V inFIG. 4.FIG. 5shows the structure of the second n-channel transistor simulated by the simulator201shown inFIG. 1. Such structure shown inFIG. 5is simulated based on the conditions for the ion implantation and the subsequent annealing processes for manufacturing the second n-channel transistor stored in the process recipe memory307and the design data of the second n-channel transistor shown inFIG. 4.

The first n-channel transistor shown inFIG. 3includes a semiconductor substrate70, the trench isolation region60provided in the semiconductor substrate70, a p-well82provided in the semiconductor substrate70in the region surrounded by the trench isolation region60, a gate insulator64disposed on the p-well82, the gate electrode32disposed on the gate insulator64, the insulating sidewall spacer61disposed on the sidewall of the gate electrode32, and the first and second n+diffusion regions12and22self aligned in the p-well82by the gate electrode32.

The second n-channel transistor shown inFIG. 5includes the semiconductor substrate70, the trench isolation region62provided in the semiconductor substrate70, a p-well84provided in the semiconductor substrate70in the region surrounded by the trench isolation region62, a gate insulator66A disposed on the p-well84, the gate electrode34A disposed on the gate insulator66A, the insulating sidewall spacer63disposed on the sidewalls of the gate electrode34A, and the first and second n+diffusion regions14A and24A self aligned in the p-well84by the gate electrode34A.

As shown inFIGS. 3 and 5, the gate length “a” of the gate electrodes32included in the first n-channel transistor is equal to the gate length “a” of the gate electrodes34A included in the second n-channel transistors at the mask level. However, the surface area of the p-well82in the first n-channel transistor shown inFIG. 3, to which n-type dopants such as phosphorus (P+) and arsenic (As+) are doped, is smaller than the surface area of the p-well84in the second n-channel transistor shown inFIG. 5. Therefore, the total number of the n-type dopants doped into the p-well82shown inFIG. 3and the number of point defects in the p-well82are smaller than the total number of the n-type dopants doped into the p-well84shown inFIG. 5and the number of the point defects in the p-well84, respectively.

Accordingly, the diffusion of the n-type dopants in the p-well82of the first n-channel transistor shown inFIG. 3is reduced as compared to the diffusion of the n-type dopants in the p-well84of the second n-channel transistor shown inFIG. 5. So, in the case where the effective channel length of the second n-channel transistor is “b”, the effective channel length of the first n-channel transistor is longer by “(Δb)/2” on each side of the gate electrode32in comparison with the effective channel length “b”. Therefore, the effective channel length of the first n-channel transistor is “b+Δb”. As a result, from the point of view of the electrical characteristics of the first and second n-channel transistors, the difference between the threshold voltages of the first and second n-channel transistors is generated as shown inFIG. 6. Consequently, the first and second n-channel transistors have different characteristic in the short channel effect and the leakage current, for example.

With reference again toFIG. 1, the adjuster400compares the reference channel length and each of the effective channel lengths. Such reference channel length is simulated by the simulator201based on the reference data, the conditions for the ion implantation process, and the conditions for the annealing process. Also, each of the effective channel lengths is simulated by the simulator201based on each of the plurality of design data, the conditions for the ion implantation process, and the conditions for the annealing process. In addition, the adjuster400judges that there is a significant difference if the difference between the reference channel length and each of the channel lengths is 5% or more, for example. Further, the adjuster400adjusts the gate lengths of the gate electrode patterns included in the design data of this transistors to reduce the significant difference. For example, the adjuster400increases the gate length by 5% to 10%. Also, the adjuster400transfers the adjusted design data to the simulator201. The adjuster400determines whether or not a significant difference between the effective channel length of the transistor of which the structure is simulated by the simulator201based on the adjusted design data and the reference channel length still exists. If a significant difference still exists, the adjustments of the gate length are further repeated.

FIG. 7shows the design data of the second n-channel transistor adjusted by the adjuster400. The adjusted design data of the second n-channel transistor has a gate electrode34B, a first n+diffusion region14B and a second n+diffusion region24B. The gate electrode34B is interposed between the first and second n+diffusion region14B and24B. The first and second n+diffusion regions14B and24B are surrounded by the trench isolation62. The insulating sidewall spacer63is disposed on the sidewalls of the gate electrode34B. Here, the gate length of the gate electrode34A shown inFIG. 4is increased in the directions of the first and second n+ diffusion regions14A and24A by “(Δa)/2” for each direction through the adjustment. As a result, the gate electrode34B has the gate length of “a+Δa” as shown inFIG. 7. Meanwhile, each of the first and second n+diffusion regions14B and24B has the length of “d2−(Δa)/2”.

FIG. 8is a sectional view taken on line VIII—VIII inFIG. 7.FIG. 8shows the adjusted structure of the second n-channel transistor simulated by the simulator201shown inFIG. 1based on the adjusted design data, the conditions for the ion implantation, and the conditions for the annealing process. Here, the adjusted second n-channel transistor includes the semiconductor substrate70, the trench isolation region62provided in the semiconductor substrate70, the p-well84provided in the semiconductor substrate70in the region surrounded by the trench isolation region62, a gate insulator66B disposed on the p-well84, the gate electrode34B disposed on the gate insulator66B, the insulating sidewall spacer63disposed on the sidewalls of the gate electrode34B, and the first and second n+diffusion regions14B and24B self aligned in the p-well84by the gate electrode34B.

It should be noted that the effective channel length of the adjusted second n-channel transistor is increased toward the trench isolation region62by “(Δb)/2” on each side due to the increased gate length “a+Δa” of the gate electrode34B. Therefore, a significant difference between the effective channel length of the adjusted second n-channel transistor and the effective channel length of the first n-channel transistor as the reference channel length shown inFIG. 3is reduced. Accordingly, the threshold voltage of the adjusted second n-channel transistor is almost equal to the threshold voltage of the first n-channel transistor as shown inFIG. 9.

With reference again toFIG. 1, the verification tool251is configured to predict the projected image of a mask pattern on a wafer. Such mask pattern contains a pattern corresponding to the gate electrode adjusted by the adjuster400. The verification tool251verifies the optical proximity effect that generates when an image of the photomask is projected onto the wafer.

The optical proximity correction module120is configured to apply the optical proximity correction (OPC) to the design data of the gate electrode based on the result from the verification tool251. When the verification tool251predicts that the length of the projected image of gate electrode in the design data234A shown inFIG. 10is decreased in the gate length direction by “(Δo)/2” on each side, for example, the optical proximity correction module120increases the length of the gate electrode in the design data234B by “(Δo)/2” on each side as shown inFIG. 11. The mask data memory306shown inFIG. 1stores the design data corrected by the optical proximity correction module120.

A keyboard, a mouse, a flexible drive, a CD-ROM drive, a DVD-ROM drive, and a MO drive may be used for the input unit301. An LCD, an LED, and a network connector such as the LAN port may be used for the output unit302. The program memory303stores a program instructing the CPU100to transfer data with apparatuses connected to the CPU100. The temporary memory304stores temporary data calculated during operation by the CPU100.

With reference toFIG. 12, a computer implemented method for designing the semiconductor integrated circuit according to the embodiment of the present invention is described.

In step S101, the data interface111shown inFIG. 1fetches the plurality of design data of the plurality of transistors from the design data memory305. Transferring the design data of the transistors from the input unit111to the data interface111is an alternative. In step S102, the area calculator101calculates the surface areas of the diffusion regions of the respective transistors by using the design data fetched by the data interface111. Thereafter, the area calculator101stores the calculated surface areas in the temporary memory304.

In step S103, the reference data defining module102fetches the plurality of design data from the design data memory305. Then, the reference data defining module102defines the design data of the transistor of which the length of the diffusion region in the gate length direction is the shortest as the reference data. Thereafter, the reference data defining module102stores the reference data in the temporary memory304.

In step S104, the adjuster400transfers the plurality of the design data of the plurality of the transistors fetched by the data interface111in step S101to the simulator201. The simulator201simulates each effective channel length of the plurality of the transistors manufactured using the ion implantation and the annealing based on the length of the diffusion region in the gate length direction and the surface area of the diffusion region stored in the temporary memory304.

In step S105, the adjuster400judges whether a significant difference between the reference channel length simulated by the simulator201based on the reference data and each of the effective channel lengths simulated by the simulator201based on the design data of the transistors exists or not. When the adjuster400judges a significant difference exists, step S106is a next procedure.

In step S106, the adjuster400adjusts gate lengths of the gate electrodes contained in the design data of the transistors to reduce a significant difference. The adjuster400stores the adjusted design data of the gate electrode in the temporary memory304. When the adjuster400judges a significant difference does not exist, step S107is a next procedure.

In step S107, the verification tool251verifies the change of the line width of the gate electrode generated by the OPE. If the change of the line width is significant, the optical proximity correction module120corrects the design data of the gate electrode. Thereafter, the optical proximity correction module120stores the corrected design data in the mask data memory306.

As described above, the semiconductor integrated circuit design tool shown inFIG. 1and the computer implemented method for designing the semiconductor integrated circuit shown inFIG. 12adjust the gate length of the gate electrode based on each surface area and each length of the diffusion regions in the gate length direction contained in the design data of the plurality of the transistors. Therefore, the semiconductor integrated circuit design tool and the computer implemented method for designing the semiconductor integrated circuit according to the embodiment of the present invention make it possible to unify the effective channel lengths of the plurality of the transistors in the semiconductor integrated circuit. Consequently, the plurality of the transistors of which electrical characteristics per unit channel length such as the threshold voltage, and the leakage current are unified are provided. Accordingly, there is no need to allow for the dispersion of the manufactured transistors when the transistors are designed, which makes it possible to shrink the size of the semiconductor integrated circuit and accelerate the manufacturing process for the semiconductor integrated circuit.

With reference toFIG. 13andFIG. 14which is a sectional view taken on line XIV—XIV inFIG. 13, the semiconductor integrated circuit in accordance with the embodiment of the present invention has a semiconductor substrate1, and an n-channel transistor Q1provided in the semiconductor substrate1, an n-channel transistor Q2provided in the semiconductor substrate1, a trench isolation region5surrounding the n-channel transistor Q1and Q2. The length of the diffusion region in the gate length direction of the n-channel transistor Q1is different from the length of the diffusion region in the gate length direction of the n-channel transistor Q2.

The n-channel transistor Q1has a p-well6provided in the semiconductor substrate1, a gate insulator23disposed on the p-well6, a gate electrode75disposed on the gate insulator23, and the source and drain regions3and4self aligned in the p-well6by the gate electrode75.

The n-channel transistor Q2has a p-well16provided in the semiconductor substrate1, a gate insulator123disposed on the p-well16, a gate electrode76disposed on the gate insulator123, and the source and drain regions13and214self aligned in the p-well16by the gate electrode76.

As shown inFIG. 13, each of the source region3and the drain region4in the n-channel transistor Q1has the gate width “W”. Each of the source region13and the drain region214in the n-channel transistor Q2also has the gate width “W”. However, the length of the n-channel transistor Q1in the gate length direction is “L1”. On the contrary, the length of the n-channel transistor Q2in the gate length direction is “L2” Here, “L2” is twice as long as “L1”. In addition, the gate electrode75in the n-channel transistor Q1has the gate length “A”. On the contrary, the gate electrode76in the n-channel transistor Q2has the gate length “A+ΔA”. Therefore, the gate length of the gate electrode76is longer by “(ΔA)/2” on each side in comparison with the gate length of the gate electrode75. Since the gate length of the gate electrode76is adjusted, the effective channel length “B” of the n-channel transistor Q1is equal to the effective channel length “B” of the n-channel transistor Q2as shown inFIG. 14. Accordingly, there is no significant difference between the electrical characteristics per unit channel length of the n-channel transistor Q1and the n-channel transistor Q2.

With reference toFIGS. 15–20, a method for manufacturing the semiconductor integrated circuit shown inFIGS. 13 and 14according to the embodiment of the present invention is described.

In step S201, the mask pattern for manufacturing the semiconductor integrated circuit is prepared. The mask pattern contains the gate electrode patterns of which gate lengths are adjusted by the method shown inFIG. 12. Thereafter, a photomask having the mask pattern is manufactured. In step S202, the trench isolation region5is formed in the semiconductor substrate1as shown inFIG. 16. Then, the p-well6and the p-well16are formed in the semiconductor substrate1. The p-well6and the p-well16are surrounded by the trench isolation region5.

In step S203, as shown inFIG. 17, the gate insulator23on the p-well6and the gate insulator123on the p-well16are grown by thermal oxidation, respectively. Thereafter, a polycrystalline silicon layer55as a conductive layer is deposited on the semiconductor substrate1by the Chemical Vapor Deposition (CVD) process.

In step S204, a resist film is coated on the polycrystalline silicon layer55. Subsequently, the resist film is exposed to light through the photomask prepared in step S201. InFIG. 18, the resist film is discriminately dissolved by the develop process and chemical etching masks90and91are formed on the polycrystalline silicon layer55. Here, the length of the chemical etching mask90in the gate length direction is “A”. The length of the chemical etching mask91in the gate length direction is “A+ΔA”. The length of the chemical etching mask91is longer than the length of the chemical etching mask90by “(ΔA)/2” for each direction.

In step S205, as shown inFIG. 19, the polycrystalline silicon layer55wherever the resist film is removed is discriminately etched by use of the optical lithography and the reactive ion etching (RIE) process. Consequently, the gate electrodes75,75are formed. Here, the gate length of the gate electrode75formed on the p-well6is “A”. On the contrary, the gate length of the gate electrode76formed on the p-well16is “A+ΔA”. The gate length of the gate electrode76is longer than the gate length of the gate electrode75by “(ΔA)/2” for each direction.

In step S206, as shown inFIG. 20, a resist film43is coated on the semiconductor substrate1. Thereafter, openings143and144are delineated in the resist film43by use of the lithography process. Then, the p-well6and the p-well16exposed by the openings143and144are selectively doped with N-type dopants such as phosphorus (P+) and arsenic (As+) using the gate electrodes75and76as the doping mask. Then, resist film43is removed by the ash process. In step S207the annealing process is employed to activate and diffuse the doped dopants in the p-wells6and16. Consequently, the semiconductor integrated circuit shown inFIGS. 13 and 14is obtained.

As described above, the method for manufacturing the semiconductor integrated circuit in accordance with the embodiment of the present invention makes it possible to unify the effective channel lengths of the transistors even though the transistors have different lengths of the diffusion regions in the gate length direction. In an earlier method, the OPC method is employed to unify the gate lengths of the gate electrodes in the semiconductor integrated circuits. However, it is difficult to unify the effective channel lengths of the transistors of which lengths of the diffusion regions in the gate length direction are different from each other. On the contrary, the method for manufacturing the semiconductor integrated circuit in accordance with the embodiment makes it possible to unify the effective channel lengths of the transistors even though the plurality of transistors have different lengths of the diffusion regions in the gate length direction. Therefore, it is possible to unify the electrical characteristics per the unit channel length of the transistors.

Although an invention has been described above by reference to the embodiment of the present invention, the present invention is not limited to the embodiment described above. Modifications and variations of the embodiment described above will occur to those skilled in the art, in the light of the above teachings. For example, in the embodiment described above, the tool shown inFIG. 1and the method shown inFIG. 12are employed to adjust the gate length of the gate electrode34A in the second n-channel transistor, where the single gate electrode34A is disposed as shown inFIG. 4. However, the tool and the method according to the embodiment are also useful in adjusting the design data of the transistor having a plurality of gate electrodes40A,41,42A shown inFIG. 21.

The design data of the transistor shown inFIG. 21contains the parallel gate electrodes40A,41,42A, a first n+diffusion region10A adjacent to the gate electrode40A, a second n+diffusion region11between the gate electrodes40A and41, a third n+diffusion region212between the gate electrodes41and42A, and a fourth n+diffusion region213A adjacent to the gate electrode42A. Each gate length of the gate electrodes40A,41,42A is “L” at the mask level. Each length of the first and the fourth n+diffusion regions10A and213A in the gate length direction is “d4”. Each length of the second and the third n+diffusion regions11and212in the gate length direction is “d3” that is shorter than “d4”.

In this case, the simulator201shown inFIG. 1simulates the each effective channel length for the gate electrodes40A,41,42A after the doped dopants are activated and diffused in the first to fourth n+diffusion regions10A,11,212, and213A based on the design data shown inFIG. 21. When the simulator201simulates the effective channel lengths, the simulator201incorporates the design where one edge of the first n+diffusion region10A is in contact with the trench isolation and another edge of the first n+diffusion region10A is in contact with the gate electrode40A in the gate length direction as the restriction factor of the diffusion. Also, the simulator201incorporates the design where one edge of the second n+diffusion region11is in contact with the gate electrode40A and another edge of the second n+diffusion region11is in contact with the gate electrode41in the gate length direction as the restriction factor of the diffusion. As for the third n+diffusion region212, the simulator201incorporates the design where one edge is in contact with the gate electrode41and another edge is in contact with the gate electrode42A in the gate length direction as the restriction factor of the diffusion. As for the fourth n+diffusion region213A, the simulator201incorporates the design where one edge is in contact with the gate electrode42A and another edge is in contact with the trench isolation region in the gate length direction as the restriction factor of the diffusion.

If the simulator201simulates that each effective channel length for the gate electrode40A and42A is shorter than the effective channel length for the gate electrode41, for example, the adjuster400shown inFIG. 1adjusts the design data as shown inFIG. 22. The adjusted design data for the transistor contains gate electrodes40B,41,42B, a first n+diffusion region10B, a second n+diffusion region11, a third n+diffusion region212, and a fourth n+diffusion region213B. Here, each of the gate electrodes40B and42B is increased by “L+Δl” and each length of the first and fourth n+diffusion regions10B and213B in the gate length direction is decreased from “d4” to “d4−Δl” based on the simulated effective channel length. Therefore, the transistor manufactured by using the adjusted design data shows no significant difference in the effective channel length for each of the gate electrodes40A,41,42. As described above, the present invention includes many variations of embodiments. Therefore, the scope of the invention is defined with reference to the following claims.