MULTIPLE OPERATION FUSED ADDITION AND SUBTRACTION INSTRUCTION SET

An embodiment of an apparatus comprises decode circuitry to decode a single instruction, the single instruction to include respective fields for one or more source operands, one or more destination operands, and an opcode, the opcode to indicate execution circuitry is to perform a fused addition and subtraction operation, and execution circuitry to execute the decoded instruction according to the opcode to retrieve data from one or more locations indicated by the one or more source operands, to perform the fused addition and subtraction operation indicated by the opcode on three or more arguments indicated by the retrieved data to produce one or more results. Other embodiments are disclosed and claimed.

BACKGROUND

1. Technical Field

This disclosure generally relates to processor technology, and more particularly to instruction set technology.

2. Background Art

Some implementations of homomorphic encryption (HE) rely heavily on polynomial arithmetic over a finite field. Two of the biggest performance bottlenecks in HE primitives and applications are polynomial modular multiplication and the forward and inverse number-theoretic transform (NTT). INTEL Homomorphic Encryption Acceleration Library (INTEL HEXL) is a C++ library which provides optimized implementations of polynomial arithmetic for INTEL processors. INTEL HEXL utilizes an Advanced Vector Extensions 512 (INTEL AVX512) instruction set to provide implementations of the NTT and modular multiplication.

DETAILED DESCRIPTION

The technologies discussed herein variously provide techniques and mechanisms for multiple operation fused addition and subtraction. The technologies described herein may be implemented in one or more electronic devices. Non-limiting examples of electronic devices that may utilize the technologies described herein include any kind of mobile device and/or stationary device, such as cameras, cell phones, computer terminals, desktop computers, electronic readers, facsimile machines, kiosks, laptop computers, netbook computers, notebook computers, internet devices, payment terminals, personal digital assistants, media players and/or recorders, servers (e.g., blade server, rack mount server, combinations thereof, etc.), set-top boxes, smart phones, tablet personal computers, ultra-mobile personal computers, wired telephones, combinations thereof, and the like. More generally, the technologies described herein may be employed in any of a variety of electronic devices including integrated circuitry which is operable to provide a multiple operation fused addition and subtraction.

It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein.

As used throughout this description, and in the claims, a list of items joined by the term “at least one of” or “one or more of” can mean any combination of the listed terms. For example, the phrase “at least one of A, B or C” can mean A; B; C; A and B; A and C; B and C; or A, B and C. It is pointed out that those elements of a figure having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

In addition, the various elements of combinatorial logic and sequential logic discussed in the present disclosure may pertain both to physical structures (such as AND gates, OR gates, or XOR gates), or to synthesized or otherwise optimized collections of devices implementing the logical structures that are Boolean equivalents of the logic under discussion.

For an addition operation, the arguments or inputs of the operation may be referred to as addends and the result or output of the operation may be referred to as a sum (e.g., sum=addend+addend). For a subtraction operation, the first argument or input of the operation may be referred to as a minuend, the second argument of input of the operation may be referred to as a subtrahend, and the result or output of the operation may be referred to as a difference (e.g., difference=minuend−subtrahend). A conventional processor instruction for an addition or subtraction operation involves two inputs and one output. Many applications involve calculations with multiple additions and/or subtractions. A problem is that at the instruction level such calculations that must be broken down into multiple two-input operations, which incurs penalties in terms of instruction decode and processing overhead. Some embodiments overcome one or more of the foregoing problems.

Some embodiments provide technology for a multi-operation fused addition and subtraction instruction. As used herein, a fused operation may refer to a fusion of multiple operations, generally in response to a single request or instruction.

With reference toFIG.1, an embodiment of an apparatus100may include a processor111to perform arithmetic operations that include at least addition operations and subtraction operations, and circuitry113coupled to the processor111to cause the processor111to perform a fused addition and subtraction operation on three or more source inputs in response to a single processor instruction to produce one or more results. For example, each of the source inputs may include one or more input arguments for a subsequent addition or subtraction operation, and the single processor instruction may indicate various groupings of the arguments, add/sub operations between various arguments, add/sub operations between the various groupings of the arguments, various orders of the add/sub operations, etc. For example, the various inputs and indications may be included in the instruction itself (e.g., through the opcode, explicit fields of the instruction, pre-determined or implicit inputs/indications, etc.), or the instruction may explicitly or implicitly point to the information that identifies the various inputs and indications. Similarly, destination locations for the one or more results may be explicit operands of the single processor instruction or may be implicit locations (e.g., pre-determined registers or memory locations).

In some embodiments, the single processor instruction may indicate two or more sets of the three or more source inputs for the fused addition and subtraction operation (e.g., set A=[first source input, second source input], set B=[third source input], set C=[fourth source input, fifth source input, sixth source input], and so on). For example, the single processor instruction may indicate one of an addition operation and a subtraction operation to be performed between arguments within each set of the two or more sets that includes two or more source inputs (e.g., set A=[first source input+/−second source input], set C=[fourth source input+/−fifth source input+/−sixth source input], etc.), and/or the single processor instruction may also indicate one of an addition operation and a subtraction operation to be performed between each set of the two or more sets (e.g., set A+/−set B+/−set C, and so on).

In some embodiments, in response to the single processor instruction, the circuitry113may be further configured to cause the processor111to perform a first operation indicated by the single processor instruction to one of add and subtract respective first and second arguments of first and second input sources indicated by the single processor instruction to produce an intermediate value, and to perform a second operation indicated by the single processor instruction to one of add and subtract the intermediate value and a third argument of a third input source indicated by the single processor instruction to produce a result of the one or more results. For example, further in response to the single processor instruction, the circuitry113may also be configured to cause the processor111to store the result of the second operation in a location indicated by the single processor instruction. In some embodiments, the single processor instruction may include a mask operand that indicates whether the first operation is an addition operation or a subtraction operation and whether the second operation is an addition operation or a subtraction operation.

In some embodiments, in response to the single processor instruction, the circuitry113may be further configured to cause the processor111to provide an overflow indication to the processor if the intermediate value is larger than a threshold value, and/or to provide an underflow indication to the processor if the intermediate value is less than zero. In some embodiments, one or more of the three or more input sources may include a scalar argument (e.g., that is used for one or more fused add/sub operations).

Embodiments of the processor111, and/or the circuitry113, may be incorporated in or integrated with a processor such as those described herein including, for example, the core990(FIG.8B), the cores1102A-N (FIGS.10,14), the processor1210(FIG.11), the co-processor1245(FIG.11), the processor1370(FIGS.12-13), the processor/coprocessor1380(FIGS.12-13), the coprocessor1338(FIGS.12-13), the coprocessor1520(FIG.14), and/or the processors1614,1616(FIG.15).

With reference toFIG.2, an embodiment of an accelerator220may include hardware circuitry223to perform arithmetic operations that include at least a fused addition and subtraction operation on three or more source inputs in response to a single instruction to produce one or more results. For example, each of the source inputs may be a vector that includes one or more input arguments per vector for a subsequent addition or subtraction operation, and the single instruction may indicate various groupings of the arguments, add/sub operations between various arguments, add/sub operations between the various groupings of the arguments, various orders of the add/sub operations, etc. For example, the various inputs and indications may be included in the instruction itself (e.g., through an opcode, explicit fields of the instruction, pre-determined or implicit inputs/indications, etc.), or the instruction may explicitly or implicitly point to the information that identifies the various inputs and indications. Similarly, destination locations for the one or more results may be explicit operands of the single instruction or may be implicit locations (e.g., pre-determined registers or memory locations). The hardware circuitry223have a wide processing width, have a highly parallel architecture, and/or may otherwise be specially configured to accelerate the multi-operation fused addition and subtraction.

FIG.3illustrates an embodiment of hardware300to process instructions such as multi-operation fused add-subtract (MOFAS) instructions (e.g., MOFAS_AA, MOFAS_AS, MOFAS_SA, MOFAS_SS, MOFAS_MM, etc.). As illustrated, storage343stores one or more MOFAS instructions341to be executed. Decoder circuitry345may be configured to decode a single instruction, the single instruction to include respective fields for one or more source operands, one or more destination operands, and an opcode, the opcode to indicate execution circuitry is to perform a fused addition and subtraction operation.

One of the MOFAS instructions341is received by decoder circuitry345. For example, the decoder circuitry345receives this instruction from fetch logic/circuitry. The instruction includes fields for an opcode, one or more source(s), and one or more destination(s). In some embodiments, the source(s) and destination(s) are registers, and in other embodiments one or more are memory locations. In some embodiments, the opcode details which MOFAS operation is to be performed.

The decoder circuitry345decodes the instruction into one or more operations. In some embodiments, this decoding includes generating a plurality of micro-operations to be performed by execution circuitry (such as execution circuitry349). The decoder circuitry345also decodes instruction prefixes.

In some embodiments, register renaming, register allocation, and/or scheduling circuitry347provides functionality for one or more of: 1) renaming logical operand values to physical operand values (e.g., a register alias table in some embodiments), 3) allocating status bits and flags to the decoded instruction, and 3) scheduling the decoded instruction for execution on execution circuitry out of an instruction pool (e.g., using a reservation station in some embodiments).

Registers (register file) and/or memory348store data as operands of the instruction to be operated on by execution circuitry349. Exemplary register types include packed data registers, general purpose registers, and floating point registers.

Execution circuitry349executes the decoded instruction. Exemplary detailed execution circuitry is shown inFIG.8B, etc. The execution of the decoded instruction causes the execution circuitry349to execute the decoded instruction according to the opcode. For some MOFAS instructions, for example, the execution of the decoded instruction causes the execution circuitry349to retrieve data from one or more locations indicated by the one or more source operands, to perform the fused addition and subtraction operation indicated by the opcode on three or more arguments indicated by the retrieved data to produce one or more results, and to store the one or more results in one or more locations indicated by the one or more destination operands. For example, one or more of the three or more arguments may be a scalar argument.

In some embodiments, the execution of the decoded instruction causes the execution circuitry349to perform a first operation to one of add and subtract first and second arguments of the three or more arguments to produce an intermediate value, where the first operation is indicated by one or more of the decoded instruction and the retrieved data, and to perform a second operation to one of add and subtract the intermediate value and a third argument of the three or more arguments to produce one of the one or more results, where the second operation is indicated by one or more of the decoded instruction and the retrieved data. For example, the retrieved data may include mask information, and the execution of the decoded instruction causes the execution circuitry349to determine whether the first operation is an addition operation or a subtraction operation based on the mask information, and to determine whether the second operation is an addition operation or a subtraction operation based on the mask information. In some embodiments, the execution of the decoded instruction causes the execution circuitry349to provide an overflow indication if the intermediate value is larger than a threshold value, and/or to provide an underflow indication if the intermediate value is less than zero.

In some embodiments, retirement/write back circuitry353architecturally commits the destination register into the registers or memory348and retires the instruction.

Instead of mask, in some embodiments the opcode itself may determine the add/sub operations to be performed on the input sources. Instead of fields, in some embodiments, all inputs and outputs for the instruction may be intrinsic. For example, information (e.g., data structures, flags, masks, registers, etc.) may be pre-prepared in advance for the performance of the instruction and the fused add-sub operation may performed on that information upon execution of the instruction. The various locations of the information needed for the fused add-sub operation may be pre-determined or otherwise known at the time the instruction is executed, or one or more MSR(s) may point to the location(s) of the needed information. Some instructions may provide a single result for single fused add-sub operation. Some instructions may provide a set of results for a set of fused add-sub operations (e.g., where the input sources and/or output results correspond to a list, an array, a vector, a multi-dimension array, a matrix, etc.). The size of the set (e.g., a number of arguments in the list, vector, matrix, etc.) may be fixed or variable, and may be explicitly included as a field of the instruction or implicitly determined (e.g., based on a size of allocated memory for the input/output source(s)).

Non-limiting example MOFAS instructions for scalar operations and description thereof are listed in Table 1 below.

TABLE 1InstructionDescriptionMOFAS_AAFused addition of three or more scalar operandsMOFAS_ASFused addition on first two scalar operands to produceintermediate result and subtraction of third scalaroperand from intermediate resultMOFAS_SAFused subtraction of second scalar operand from firstscalar operand to produce intermediate result andaddition of third scalar operand to intermediate resultMOFAS_SSFused subtraction of second scalar operand from firstscalar operand to produce intermediate result andsubtraction of third scalar operand from intermediateresultMOFAS_MMFused add/sub per bit 0 of mask with first scalaroperand as addend/minuend and second scalar operandas addend/subtrahend to produce intermediate result andadd/sub operation per bit 1 of mask with intermediateresult as addend/minuend and third scalar operand asaddend/subtrahend

Non-limiting example MOFAS instructions for vector operations and description thereof are listed in Table 2 below.

TABLE 2InstructionDescriptionVMOFAS_AAFused addition of three or more vector operandsVMOFAS_ASFused addition on first two vector operands to produceintermediate result and subtraction of third vectoroperand from intermediate resultVMOFAS_SAFused subtraction of second vector operand from firstvector operand to produce intermediate result andaddition of third vector operand to intermediate resultVMOFAS_SSFused subtraction of second vector operand from firstvector operand to produce intermediate result andsubtraction of third vector operand from intermediateresultVMOFAS_MMFused add/sub per bit 0 of mask with first vectoroperand as addend/minuend and second operand vectoras addend/subtrahend to produce intermediate resultand add/sub operation per bit 1 of mask withintermediate result as addend/minuend and third vectoroperand as addend/subtrahend

Non-limiting example MOFAS instructions for mixed vector and scalar operations and description thereof are listed in Table 3 below.

TABLE 3InstructionDescriptionVVSMOFAS_AAFused addition of first two vector operands withthird scalar operandVVSMOFAS_ASFused addition on first two vector operands toproduce intermediate result and subtraction of thirdscalar operand from intermediate resultVVSMOFAS_SAFused subtraction of second vector operand fromfirst vector operand to produce intermediate resultand addition of third scalar operand to intermediateresultVVSMOFAS_SSFused subtraction of second vector operand fromfirst vector operand to produce intermediate resultand subtraction of third scalar operand fromintermediate resultVVSMOFAS_MMFused add/sub per bit 0 of mask with first vectoroperand as addend/minuend and second vectoroperand as addend/subtrahend to produceintermediate result and add/sub operation per bit1 of mask with intermediate result as addend/minuend and third scalar operand as addend/subtrahend

A format for an embodiment of a MOFAS instruction where one or more mask(s) are utilized to configure one or more add-sub operations between arguments is MOFAS_MNEMONIC DSTREG(S), SRCREG(S), MASK(S). In some embodiments, MOFAS_MNEMONIC is the opcode mnemonic of the instruction. DSTREG(S) is one or more fields for the destination operand(s) to indicate the result registers, or to indicate one or more memory locations that store the respective results (e.g., or pointers thereto). SRCREG(S) is one or more field(s) for an input source operand to indicate one or more registers for the operation or one or more memory locations that store the respective input sources (e.g., or pointers thereto). MASK(S) is one or more field(s) for a source operand to indicate one or more registers for the operation or one or more memory locations that store the respective masks (e.g., or pointers thereto).

In one example, a MOFAS instruction with the format <VVSMOFAS_MMUQ dst1, src1, src2, src3, mask1> may be executed to cause a processor to add/sub unsigned quadword vector elements from src1 and src2 according to a lower-order bit of two-bit element mask1 and store the unsigned quadword result in an intermediate value, and then to add/sub the intermediate value and an unsigned quadword scalar element from src3 according to an upper-order bit of two-bit element mask1 and store the unsigned quadword result in dst1.

In another example, a MOFAS instruction with the format <VMOFAS_MMBSSD dst1, src1, src2, src3, mask1> may be executed to cause a processor to add/sub signed byte vector elements from src1 and src2 according to a lower-order bit of two-bit element mask1 and store the dword result in an intermediate value, and then to add/sub the intermediate value and signed byte vector elements from src3 according to an upper-order bit of two-bit element mask1 and store the dword result in dst1.

In another example, a MOFAS instruction with the format <VMOFAS_MMBUUD result_ptr, input1_ptr, input2_ptr, input3_ptr, mask_ptr> may be executed to cause a processor to add/sub unsigned byte vector elements pointed to by input1_ptr with corresponding unsigned vector elements pointed to by input2_ptr according to a mask pointed to by mask_ptr and store the intermediate dword results in two or more locations pointed to by tmp_ptr, and then to add/sub unsigned byte vector elements pointed to by tmp_ptr with unsigned corresponding vector elements pointed to by input3_ptr according to the mask pointed to by mask_ptr and store the final dword results in two or more locations pointed to by result_ptr. For example, the respective pointers may point to respective memory locations that store respective data structures that indicate the various operation information and respective register/memory locations for each input source and/or result destination. Those skilled in the art will appreciate that a wide variety of other instruction formats may be utilized where execution of a single instruction may cause a processor to perform respective fused add/sub operations on three or more arguments in response to the single instruction.

FIGS.4A to4Billustrate an embodiment of method430performed by a processor to process MOFAS instructions. For example, a processor core as shown inFIG.8B, a pipeline as detailed below, etc. performs this method.

At431, an instruction is fetched. For example, a MOFAS instruction is fetched. The MOFAS instruction includes a single instruction having fields for an opcode, one or more destination operands, and one or more source operands. In some embodiments, the instruction further includes a field for a writemask. In some embodiments, the instruction is fetched from an instruction cache. The source operand(s) and destination operand(s) are packed data. The opcode of the MOFAS instruction indicates which fused add/sub operation (e.g., MOFAS_AA, MOFAS_AS, MOFAS_SA, MOFAS_SS, MOFAS_MM etc.) to perform.

The fetched instruction is decoded according to the opcode at433. For example, the fetched MOFAS instruction is decoded by decode circuitry such as that detailed herein.

Data values associated with the source operands of the decoded instruction are retrieved and execution of the decoded instruction is scheduled at435. For example, when one or more of the source operands are memory operands, the data from the indicated memory location is retrieved.

The decoded instruction is executed by execution circuitry (hardware) such as that detailed herein. For the MOFAS instruction, at437, the execution will cause execution circuitry to perform a fused addition and subtraction operation indicated by the opcode on three or more arguments indicated by the retrieved data to produce one or more results, and to store the one or more results in one or more locations indicated by the one or more destination operands at438.

In some embodiments, the instruction is committed or retired at439.

In some embodiments, the execution of the decoded MOFAS instruction will further cause execution circuitry to perform a first operation to one of add and subtract first and second arguments of the three or more arguments to produce an intermediate value at441, where the first operation is indicated by one or more of the decoded instruction and the retrieved data, and to perform a second operation to one of add and subtract the intermediate value and a third argument of the three or more arguments to produce one of the one or more results at443, where the second operation is indicated by one or more of the decoded instruction and the retrieved data. For example, the execution of the decoded MOFAS instruction may further cause execution circuitry to determine whether the first operation is an addition operation or a subtraction operation based on mask information included in the retrieved data at445, and to determine whether the second operation is an addition operation or a subtraction operation based on the mask information at447. The execution of the decoded MOFAS instruction may also cause execution circuitry to provide an overflow indication if the intermediate value is larger than a threshold value at451, and/or to provide an underflow indication if the intermediate value is less than zero at453. For example, one or more of the three or more arguments may be a scalar argument at455.

FIGS.5A to5Billustrate an embodiment of method550performed by a processor to process a MOFAS instruction using emulation or binary translation. For example, a processor core as shown inFIG.8B, a pipeline as detailed below, etc. performs this method.

At551, an instruction is fetched. For example, a MOFAS instruction is fetched. The MOFAS instruction includes a single instruction having fields for an opcode, one or more destination operands, and one or more source operands. In some embodiments, the instruction further includes a field for a writemask. In some embodiments, the instruction is fetched from an instruction cache. The source operand(s) and destination operand(s) are packed data. The opcode of the MOFAS instruction indicates which fused add/sub operation (e.g., MOFAS_AA, MOFAS_AS, MOFAS_SA, MOFAS_SS, MOFAS_MM, etc.) to perform.

The fetched instruction of the first instruction set is translated into one or more instructions of a second instruction set at552.

The one or more translated instructions of the second instruction set are decoded at553. In some embodiments, the translation and decoding are merged.

Data values associated with the source operands of the decoded instruction(s) are retrieved and execution of the decoded instruction(s) is scheduled at555. For example, when one or more of the source operands are memory operands, the data from the indicated memory location is retrieved.

The decoded instruction is executed by execution circuitry (hardware) such as that detailed herein. For the MOFAS instruction, at557, the execution will cause execution circuitry to perform a fused addition and subtraction operation indicated by the opcode on three or more arguments indicated by the retrieved data to produce one or more results, and to store the one or more results in one or more locations indicated by the one or more destination operands at558.

In some embodiments, the instruction is committed or retired at559.

In some embodiments, the execution of the decoded MOFAS instruction will further cause execution circuitry to perform a first operation to one of add and subtract first and second arguments of the three or more arguments to produce an intermediate value at561, where the first operation is indicated by one or more of the decoded instruction and the retrieved data, and to perform a second operation to one of add and subtract the intermediate value and a third argument of the three or more arguments to produce one of the one or more results at563, where the second operation is indicated by one or more of the decoded instruction and the retrieved data. For example, the execution of the decoded MOFAS instruction may further cause execution circuitry to determine whether the first operation is an addition operation or a subtraction operation based on mask information included in the retrieved data at565, and to determine whether the second operation is an addition operation or a subtraction operation based on the mask information at567. The execution of the decoded MOFAS instruction may also cause execution circuitry to provide an overflow indication if the intermediate value is larger than a threshold value at571, and/or to provide an underflow indication if the intermediate value is less than zero at573. For example, one or more of the three or more arguments may be a scalar argument at575.

Some embodiments may provide three-operand fused add/subtract instructions that may be particularly useful for various encryption technologies. Privacy-preserving machine learning (PPML) enables learning from data while keeping the data private. PPML techniques include INTEL Software Guard Extensions (SGX), federated learning, secure multi-party computation, and homomorphic encryption (HE). HE is a form of encryption that enables computation on the encrypted data.

Polynomial multiplication in the finite field Zq[X]/(X{circumflex over ( )}N+1) (that is, polynomials of degree at most N−1 whose coefficients are integers mod q), or similar fields, may be a bottleneck in many HE applications. The negacyclic number-theoretic-transform (NTT), both the forward transform and the inverse transform, may be used to speed up multiplication. Multiplying two polynomials f(x)*g(x) in this field is may be computed as InvNTT(FwdNTT(f)⊙FwdNTT(g)), where ⊙ indicates element-wise vector-vector modular multiplication.

In some encryption schemes, the NTT is used to speed up polynomial multiplication over a polynomial ring. Polynomial multiplication may also be a bottleneck in these cryptography workloads. The core of the NTT computation includes modular integer arithmetic, in particular modular addition and multiplication. While numerous techniques have been developed to improve or optimize the NTT, a problem is that the NTT computation remains a bottleneck for many applications. Some embodiments address this problem.

Some embodiments provide a MOFAS instruction set for vector fused add-subtract of unsigned quadwords, nominally referred to as VFADDSUBUQ, to improve or optimize an inverse NTT. Embodiments of a VFADDSUBUQ instruction causes a suitably configured processor or accelerator to perform a fused three-operand addition-addition, addition-subtraction, subtraction-addition, or subtraction-subtraction operation (e.g., where at least two of the operands are vectors). Advantageously, embodiments of the VFADDSUBUQ instruction may be utilized to significantly improve the performance of a forward NTT, and/or an inverse NTT.

Embodiments of a multi-operand add instruction may also be beneficial for other cryptography algorithms. For example, the National Security Agency designed a secure hash algorithm 2 (SHA-2) with a family of hash functions, one of which is 256 bits (SHA-256). The SHA-256 cryptographic hash function is utilized by numerous cryptography and other applications, such as block chain and crypto currencies.

The logical and rotate operations can be processed on multiple execution ports and some efficiency may be provided by instructions like TERNLOG that perform three-operand Boolean functions. The above-noted calculations of “temp1” with four addition operations (five addends), and “a” with two addition operations (three addends), are a significant part of the processing. Embodiments of a multi-operation fused add-sub instruction, such as a VFADDSUBUQ instruction, may be used to perform multi-operand addition for all of the arguments of “temp1” (e.g., a five-operand fused add-sub operation) and “a” (e.g., a three-operand fused add-sub operation) to accelerate those calculations.

In one example, a MOFAS instruction with the format <VFADDSUBUQ src1, src2, src3, mask1, dst1> may be executed to cause a processor to vector add/sub unsigned quadword vector elements from src1 and src2 according to a lower-order bit of two-bit element mask1 and store the result as an intermediate value, and then to add/sub the intermediate value and unsigned quadword vector elements from src3 according to an upper-order bit of two-bit element mask1 and store the unsigned quadword result in dst1, where src1, src2, and src3 are vector arguments, and dst1 is a vector result.

With reference toFIG.6, an embodiment of a method630for the VFADDSUBUQ instruction may include, for each packed unsigned N-bit integer in src1 and src2 (at632, where num_arg is the size of the vector), add (at636) or subtract (at638) according to the 1st bit of the mask1 (at634), to form an (N+1)-bit intermediate result (tmp, at636or638). For each corresponding packed N-bit integer in src3, add to (at642) or subtract from (at644), according to the 2nd bit of the mask1 (at640), the intermediate result (tmp) and store the result in dst1 (at642or644).

In some embodiments, one or more of the operands of the VFADDSUBUQ instruction may be implicit. In some embodiments, one or more of the operands of the VFADDSUBUQ instruction may be pointers. For a single instruction multiple data (SIMD) architecture, different versions of the VFADDSUBUQ instruction may be provided for different register widths (e.g., VFADDSUBUQ128, VFADDSUBUQ256, VFADDSUBUQ512, etc.). Embodiments of the VFADDSUBUQ instructions may also be instantiated for several bit-widths N (e.g., N=32 and/or N=64 may be beneficial for HE applications).

A non-limiting example for a SIMD architecture with a number of bit lanes (NumBitLanes) with each bit lane having a bit width of N includes the following pseudo-code for the VFADDSUBUQ instruction:

In embodiments of fused add-sub operations, the intermediate values may add up to a larger number than can be fully represented by the bit width of the input sources. In some embodiments, enough bits are provided for all anticipated sums of the intermediate value such that the intermediate bits are not dropped (e.g., supporting infinitely precise intermediate results). In the foregoing example pseudo-code, for example, the summations may involve up to two extra bits for the intermediate summation result and the subtraction may underflow. In the foregoing example pseudo-code, the overflow bits are ignored and only the lower N bits of tmp[(N−1):0] are stored into the result.

A variant of the VFADDSUBUQ instruction includes an embodiment of a VSFADDSUBUQ instruction that has a single 64-bit integer for the third source. For example, an embodiment of a VSFADDSUBUQ instruction may be utilized in applications such as the NTT, where the same modulus may be re-used many times.

In one example, a MOFAS instruction with the format <VSFADDSUBUQ src1, src2, src3, mask1, dst1> may be executed to cause a processor to add/sub unsigned quadword vector elements from src1 and src2 according to a lower-order bit of two-bit element mask1 and store the result as an intermediate value, and then to add/sub the intermediate value and the 64-bit integer value of src3 according to an upper-order bit of two-bit element mask1 and store the unsigned quadword result in dst1, where src1 and src2 are vector arguments, src3 is a scalar argument, and dst1 is a vector result.

With reference toFIG.7, an embodiment of a method730for the VSFADDSUBUQ instruction may include, for each packed unsigned N-bit integer in src1 and src2 (at732, where num_arg is the size of the vector), add (at736) or subtract (at738) according to the 0th bit of the mask1 (at734), to form an (N+1)-bit intermediate result (tmp, at736or738). Next, according to the 1st bit of the mask1 (at740), add src3 to (at742) or subtract src3 from (at744), the intermediate result (tmp) and store the result in dst1 (at742or744).

In some embodiments, one or more of the operands of the VSFADDSUBUQ instruction may be implicit. In some embodiments, one or more of the operands of the VSFADDSUBUQ instruction may be pointers. For a SIMD architecture, different versions of the VSFADDSUBUQ instruction may be provided for different register widths (e.g., VSFADDSUBUQ128, VSFADDSUBUQ256, VSFADDSUBUQ512, etc.). Embodiments of the VSFADDSUBUQ instructions may also be instantiated for several bit-widths N (e.g., N=32 and/or N=64 may be beneficial for HE applications).

A non-limiting example for a SIMD architecture with a number of bit lanes (NumBitLanes) with each bit lane having a bit width of N includes the following pseudo-code for the VSFADDSUBUQ instruction:

As with the VFADDSUBUQ instruction, although the intermediate result may be up to N+2 bits, the final result stores only the lower N bits of “tmp” into the result. Embodiments of the VSFADDSUBUQ instruction may be used to accelerate an AVX512-IFMA radix-4 forward NTT butterfly. For example, embodiments of code that implements an AVX512-IFMA radix-4 forward NTT butterfly may utilize significantly fewer assembly instructions by utilizing an embodiment of a VSFADDSUBUQ instruction (e.g., about 10% fewer instructions). Embodiments of an AVX512-IFMA52 radix-2 forward NTT as well as the AVX512-IFMA52 radix-2 inverse NTT may also be improved. Other applications may also be improved or optimized by utilizing embodiments of the MOFAS instructions described herein.

Examples of Extensions and Other MOFAS Instructions

As noted above, embodiments of a VSFADDSUBUQ may support a variety of forms, including a 128-bit, 256-bit, and 512-bit form, as well as a formulation with a scalar third non-mask input argument. In some embodiments, the packed integers may further be of different bit widths. For example, VSFADDSUBUQ may operate on packed 32-bit integers, or packed 64-bit integers.

In some embodiments, a MOFAS instruction may operate on signed integers only, which may be useful in cases where elements of Z_q={integers mod q} are represented using the range [−q/2, q/2). For comparison, an unsigned integer embodiment may be useful when Z_q is represented using the range [0,q).

In some embodiments, a MOFAS instruction such as VSFADDSUBUQ may return an error flag or set an overflow flag if an intermediate addition is larger than or equal to the input bit-width (i.e., if either of the top two bits of “tmp” in the foregoing pseudo code are non-zero). Similarly, in some embodiments, a MOFAS instruction such as VSFADDSUBUQ may return an error flag or set an underflow flag if an intermediate subtraction results in a negative value.

In some embodiments, an order of operands of a MOFAS instruction such as VSFADDSUBUQ may have a scalar second non-mask argument or scalar first non-mask argument, rather than a scalar third non-mask argument, for situations where such operand ordering may be a more intuitive argument order.

In some embodiments, as noted above, a MOFAS instructions such as VSFADDSUBUQ may include additional non-mask arguments to create a fused 4-or-more-operand add/subtract. In this case, the 3rd and higher bits of the mask may be used to determine whether to add or to subtract the fourth and higher non-scalar operand(s).

Those skilled in the art will appreciate that a wide variety of devices may benefit from the foregoing embodiments. The following exemplary core architectures, processors, and computer architectures are non-limiting examples of devices that may beneficially incorporate embodiments of the technology described herein.

Exemplary Core Architectures

In-Order and Out-of-Order Core Block Diagram

InFIG.8A, a processor pipeline900includes a fetch stage902, a length decode stage904, a decode stage906, an allocation stage908, a renaming stage910, a scheduling (also known as a dispatch or issue) stage912, a register read/memory read stage914, an execute stage916, a write back/memory write stage918, an exception handling stage922, and a commit stage924.

FIG.8Bshows processor core990including a front end unit930coupled to an execution engine unit950, and both are coupled to a memory unit970. The core990may be a reduced instruction set computing (RISC) core, a complex instruction set computing (CISC) core, a very long instruction word (VLIW) core, or a hybrid or alternative core type. As yet another option, the core990may be a special-purpose core, such as, for example, a network or communication core, compression engine, coprocessor core, general purpose computing graphics processing unit (GPGPU) core, graphics core, or the like.

The front end unit930includes a branch prediction unit932coupled to an instruction cache unit934, which is coupled to an instruction translation lookaside buffer (TLB)936, which is coupled to an instruction fetch unit938, which is coupled to a decode unit940. The decode unit940(or decoder) may decode instructions, and generate as an output one or more micro-operations, micro-code entry points, microinstructions, other instructions, or other control signals, which are decoded from, or which otherwise reflect, or are derived from, the original instructions. The decode unit940may be implemented using various different mechanisms. Examples of suitable mechanisms include, but are not limited to, look-up tables, hardware implementations, programmable logic arrays (PLAs), microcode read only memories (ROMs), etc. In one embodiment, the core990includes a microcode ROM or other medium that stores microcode for certain macroinstructions (e.g., in decode unit940or otherwise within the front end unit930). The decode unit940is coupled to a rename/allocator unit952in the execution engine unit950.

The execution engine unit950includes the rename/allocator unit952coupled to a retirement unit954and a set of one or more scheduler unit(s)956. The scheduler unit(s)956represents any number of different schedulers, including reservations stations, central instruction window, etc. The scheduler unit(s)956is coupled to the physical register file(s) unit(s)958. Each of the physical register file(s) units958represents one or more physical register files, different ones of which store one or more different data types, such as scalar integer, scalar floating point, packed integer, packed floating point, vector integer, vector floating point, status (e.g., an instruction pointer that is the address of the next instruction to be executed), etc. In one embodiment, the physical register file(s) unit958comprises a vector registers unit, a write mask registers unit, and a scalar registers unit. These register units may provide architectural vector registers, vector mask registers, and general purpose registers. The physical register file(s) unit(s)958is overlapped by the retirement unit954to illustrate various ways in which register renaming and out-of-order execution may be implemented (e.g., using a reorder buffer(s) and a retirement register file(s); using a future file(s), a history buffer(s), and a retirement register file(s); using a register maps and a pool of registers; etc.). The retirement unit954and the physical register file(s) unit(s)958are coupled to the execution cluster(s)960. The execution cluster(s)960includes a set of one or more execution units962and a set of one or more memory access units964. The execution units962may perform various operations (e.g., shifts, addition, subtraction, multiplication) and on various types of data (e.g., scalar floating point, packed integer, packed floating point, vector integer, vector floating point). While some embodiments may include a number of execution units dedicated to specific functions or sets of functions, other embodiments may include only one execution unit or multiple execution units that all perform all functions. The scheduler unit(s)956, physical register file(s) unit(s)958, and execution cluster(s)960are shown as being possibly plural because certain embodiments create separate pipelines for certain types of data/operations (e.g., a scalar integer pipeline, a scalar floating point/packed integer/packed floating point/vector integer/vector floating point pipeline, and/or a memory access pipeline that each have their own scheduler unit, physical register file(s) unit, and/or execution cluster—and in the case of a separate memory access pipeline, certain embodiments are implemented in which only the execution cluster of this pipeline has the memory access unit(s)964). It should also be understood that where separate pipelines are used, one or more of these pipelines may be out-of-order issue/execution and the rest in-order.

The set of memory access units964is coupled to the memory unit970, which includes a data TLB unit972coupled to a data cache unit974coupled to a level 2 (L2) cache unit976. In one exemplary embodiment, the memory access units964may include a load unit, a store address unit, and a store data unit, each of which is coupled to the data TLB unit972in the memory unit970. The instruction cache unit934is further coupled to a level 2 (L2) cache unit976in the memory unit970. The L2 cache unit976is coupled to one or more other levels of cache and eventually to a main memory.

By way of example, the exemplary register renaming, out-of-order issue/execution core architecture may implement the pipeline900as follows: 1) the instruction fetch938performs the fetch and length decoding stages902and904; 2) the decode unit940performs the decode stage906; 3) the rename/allocator unit952performs the allocation stage908and renaming stage910; 4) the scheduler unit(s)956performs the schedule stage912; 5) the physical register file(s) unit(s)958and the memory unit970perform the register read/memory read stage914; the execution cluster960perform the execute stage916; 6) the memory unit970and the physical register file(s) unit(s)958perform the write back/memory write stage918; 7) various units may be involved in the exception handling stage922; and 8) the retirement unit954and the physical register file(s) unit(s)958perform the commit stage924.

Specific Exemplary In-Order Core Architecture

FIG.9Ais a block diagram of a single processor core, along with its connection to the on-die interconnect network1002and with its local subset of the Level 2 (L2) cache1004, according to embodiments of the invention. In one embodiment, an instruction decoder1000supports the x86 instruction set with a packed data instruction set extension. An L1 cache1006allows low-latency accesses to cache memory into the scalar and vector units. While in one embodiment (to simplify the design), a scalar unit1008and a vector unit1010use separate register sets (respectively, scalar registers1012and vector registers1014) and data transferred between them is written to memory and then read back in from a level 1 (L1) cache1006, alternative embodiments of the invention may use a different approach (e.g., use a single register set or include a communication path that allow data to be transferred between the two register files without being written and read back).

FIG.9Bis an expanded view of part of the processor core inFIG.9Aaccording to embodiments of the invention.FIG.9Bincludes an L1 data cache1006A part of the L1 cache1006, as well as more detail regarding the vector unit1010and the vector registers1014. Specifically, the vector unit1010is a 16-wide vector processing unit (VPU) (see the 16-wide ALU1028), which executes one or more of integer, single-precision float, and double-precision float instructions. The VPU supports swizzling the register inputs with swizzle unit1020, numeric conversion with numeric convert units1022A-B, and replication with replication unit1024on the memory input. Write mask registers1026allow predicating resulting vector writes.

FIG.10is a block diagram of a processor1100that may have more than one core, may have an integrated memory controller, and may have integrated graphics according to embodiments of the invention. The solid lined boxes inFIG.10illustrate a processor1100with a single core1102A, a system agent1110, a set of one or more bus controller units1116, while the optional addition of the dashed lined boxes illustrates an alternative processor1100with multiple cores1102A-N, a set of one or more integrated memory controller unit(s)1114in the system agent unit1110, and special purpose logic1108.

The memory hierarchy includes one or more levels of respective caches1104A-N within the cores1102A-N, a set or one or more shared cache units1106, and external memory (not shown) coupled to the set of integrated memory controller units1114. The set of shared cache units1106may include one or more mid-level caches, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, a last level cache (LLC), and/or combinations thereof. While in one embodiment a ring based interconnect unit1112interconnects the integrated graphics logic1108, the set of shared cache units1106, and the system agent unit1110/integrated memory controller unit(s)1114, alternative embodiments may use any number of well-known techniques for interconnecting such units. In one embodiment, coherency is maintained between one or more cache units1106and cores1102-A-N.

In some embodiments, one or more of the cores1102A-N are capable of multi-threading. The system agent1110includes those components coordinating and operating cores1102A-N. The system agent unit1110may include for example a power control unit (PCU) and a display unit. The PCU may be or include logic and components needed for regulating the power state of the cores1102A-N and the integrated graphics logic1108. The display unit is for driving one or more externally connected displays.

Exemplary Computer Architectures

Referring now toFIG.11, shown is a block diagram of a system1200in accordance with one embodiment of the present invention. The system1200may include one or more processors1210,1215, which are coupled to a controller hub1220. In one embodiment the controller hub1220includes a graphics memory controller hub (GMCH)1290and an Input/Output Hub (IOH)1250(which may be on separate chips); the GMCH1290includes memory and graphics controllers to which are coupled memory1240and a coprocessor1245; the IOH1250couples input/output (I/O) devices1260to the GMCH1290. Alternatively, one or both of the memory and graphics controllers are integrated within the processor (as described herein), the memory1240and the coprocessor1245are coupled directly to the processor1210, and the controller hub1220in a single chip with the IOH1250.

The optional nature of additional processors1215is denoted inFIG.11with broken lines. Each processor1210,1215may include one or more of the processing cores described herein and may be some version of the processor1100.

The memory1240may be, for example, dynamic random access memory (DRAM), phase change memory (PCM), or a combination of the two. For at least one embodiment, the controller hub1220communicates with the processor(s)1210,1215via a multi-drop bus, such as a frontside bus (FSB), point-to-point interface such as QuickPath Interconnect (QPI), or similar connection1295.

In one embodiment, the coprocessor1245is a special-purpose processor, such as, for example, a high-throughput MIC processor, a network or communication processor, compression engine, graphics processor, GPGPU, embedded processor, or the like. In one embodiment, controller hub1220may include an integrated graphics accelerator.

There can be a variety of differences between the physical resources1210,1215in terms of a spectrum of metrics of merit including architectural, microarchitectural, thermal, power consumption characteristics, and the like.

In one embodiment, the processor1210executes instructions that control data processing operations of a general type. Embedded within the instructions may be coprocessor instructions. The processor1210recognizes these coprocessor instructions as being of a type that should be executed by the attached coprocessor1245. Accordingly, the processor1210issues these coprocessor instructions (or control signals representing coprocessor instructions) on a coprocessor bus or other interconnect, to coprocessor1245. Coprocessor(s)1245accept and execute the received coprocessor instructions.

Referring now toFIG.12, shown is a block diagram of a first more specific exemplary system1300in accordance with an embodiment of the present invention. As shown inFIG.12, multiprocessor system1300is a point-to-point interconnect system, and includes a first processor1370and a second processor1380coupled via a point-to-point interconnect1350. Each of processors1370and1380may be some version of the processor1100. In one embodiment of the invention, processors1370and1380are respectively processors1210and1215, while coprocessor1338is coprocessor1245. In another embodiment, processors1370and1380are respectively processor1210coprocessor1245.

Processors1370and1380are shown including integrated memory controller (IMC) units1372and1382, respectively. Processor1370also includes as part of its bus controller units point-to-point (P-P) interfaces1376and1378; similarly, second processor1380includes P-P interfaces1386and1388. Processors1370,1380may exchange information via a point-to-point (P-P) interface1350using P-P interface circuits1378,1388. As shown inFIG.12, IMCs1372and1382couple the processors to respective memories, namely a memory1332and a memory1334, which may be portions of main memory locally attached to the respective processors.

Processors1370,1380may each exchange information with a chipset1390via individual P-P interfaces1352,1354using point to point interface circuits1376,1394,1386,1398. Chipset1390may optionally exchange information with the coprocessor1338via a high-performance interface1339and an interface1392. In one embodiment, the coprocessor1338is a special-purpose processor, such as, for example, a high-throughput MIC processor, a network or communication processor, compression engine, graphics processor, GPGPU, embedded processor, or the like.

Chipset1390may be coupled to a first bus1316via an interface1396. In one embodiment, first bus1316may be a Peripheral Component Interconnect (PCI) bus, or a bus such as a PCI Express bus or another third generation I/O interconnect bus, although the scope of the present invention is not so limited.

As shown inFIG.12, various I/O devices1314may be coupled to first bus1316, along with a bus bridge1318which couples first bus1316to a second bus1320. In one embodiment, one or more additional processor(s)1315, such as coprocessors, high-throughput MIC processors, GPGPU's, accelerators (such as, e.g., graphics accelerators or digital signal processing (DSP) units), field programmable gate arrays, or any other processor, are coupled to first bus1316. In one embodiment, second bus1320may be a low pin count (LPC) bus. Various devices may be coupled to a second bus1320including, for example, a keyboard and/or mouse1322, communication devices1327and a storage unit1328such as a disk drive or other mass storage device which may include instructions/code and data1330, in one embodiment. Further, an audio I/O1324may be coupled to the second bus1320. Note that other architectures are possible. For example, instead of the point-to-point architecture ofFIG.12, a system may implement a multi-drop bus or other such architecture.

Referring now toFIG.13, shown is a block diagram of a second more specific exemplary system1400in accordance with an embodiment of the present invention Like elements inFIGS.12and13bear like reference numerals, and certain aspects ofFIG.12have been omitted fromFIG.13in order to avoid obscuring other aspects ofFIG.13.

FIG.13illustrates that the processors1370,1380may include integrated memory and I/O control logic (“CL”)1472and1482, respectively. Thus, the CL1472,1482include integrated memory controller units and include I/O control logic.FIG.13illustrates that not only are the memories1332,1334coupled to the CL1472,1482, but also that I/O devices1414are also coupled to the control logic1472,1482. Legacy I/O devices1415are coupled to the chipset1390.

Referring now toFIG.14, shown is a block diagram of a SoC1500in accordance with an embodiment of the present invention. Similar elements inFIG.10bear like reference numerals. Also, dashed lined boxes are optional features on more advanced SoCs. InFIG.14, an interconnect unit(s)1502is coupled to: an application processor1510which includes a set of one or more cores1102A-N and shared cache unit(s)1106; a system agent unit1110; a bus controller unit(s)1116; an integrated memory controller unit(s)1114; a set or one or more coprocessors1520which may include integrated graphics logic, an image processor, an audio processor, and a video processor; an static random access memory (SRAM) unit1530; a direct memory access (DMA) unit1532; and a display unit1540for coupling to one or more external displays. In one embodiment, the coprocessor(s)1520include a special-purpose processor, such as, for example, a network or communication processor, compression engine, GPGPU, a high-throughput MIC processor, embedded processor, or the like.

FIG.15is a block diagram contrasting the use of a software instruction converter to convert binary instructions in a source instruction set to binary instructions in a target instruction set according to embodiments of the invention. In the illustrated embodiment, the instruction converter is a software instruction converter, although alternatively the instruction converter may be implemented in software, firmware, hardware, or various combinations thereof.FIG.15shows a program in a high level language1602may be compiled using an x86 compiler1604to generate x86 binary code1606that may be natively executed by a processor with at least one x86 instruction set core1616. The processor with at least one x86 instruction set core1616represents any processor that can perform substantially the same functions as an Intel processor with at least one x86 instruction set core by compatibly executing or otherwise processing (1) a substantial portion of the instruction set of the Intel x86 instruction set core or (2) object code versions of applications or other software targeted to run on an Intel processor with at least one x86 instruction set core, in order to achieve substantially the same result as an Intel processor with at least one x86 instruction set core. The x86 compiler1604represents a compiler that is operable to generate x86 binary code1606(e.g., object code) that can, with or without additional linkage processing, be executed on the processor with at least one x86 instruction set core1616. Similarly,FIG.15shows the program in the high level language1602may be compiled using an alternative instruction set compiler1608to generate alternative instruction set binary code1610that may be natively executed by a processor without at least one x86 instruction set core1614(e.g., a processor with cores that execute the MIPS instruction set of MIPS Technologies of Sunnyvale, CA and/or that execute the ARM instruction set of ARM Holdings of Sunnyvale, CA). The instruction converter1612is used to convert the x86 binary code1606into code that may be natively executed by the processor without an x86 instruction set core1614. This converted code is not likely to be the same as the alternative instruction set binary code1610because an instruction converter capable of this is difficult to make; however, the converted code will accomplish the general operation and be made up of instructions from the alternative instruction set. Thus, the instruction converter1612represents software, firmware, hardware, or a combination thereof that, through emulation, simulation or any other process, allows a processor or other electronic device that does not have an x86 instruction set processor or core to execute the x86 binary code1606.

Additional Notes and Examples

Example 1 includes an apparatus, comprising a processor to perform arithmetic operations that include at least addition operations and subtraction operations, and circuitry coupled to the processor to cause the processor to perform a fused addition and subtraction operation on three or more source inputs in response to a single processor instruction to produce one or more results.

Example 2 includes the apparatus of Example 1, wherein the single processor instruction indicates two or more sets of the three or more source inputs for the fused addition and subtraction operation.

Example 3 includes the apparatus of Example 2, wherein the single processor instruction indicates one of an addition operation and a subtraction operation to be performed between arguments within each set of the two or more sets that includes two or more source inputs, and wherein the single processor instruction indicates one of an addition operation and a subtraction operation to be performed between each set of the two or more sets.

Example 4 includes the apparatus of any of Examples 1 to 3, wherein, in response to the single processor instruction, the circuitry is further to cause the processor to perform a first operation indicated by the single processor instruction to one of add and subtract respective first and second arguments of first and second input sources indicated by the single processor instruction to produce an intermediate value, and perform a second operation indicated by the single processor instruction to one of add and subtract the intermediate value and a third argument of a third input source indicated by the single processor instruction to produce a result of the one or more results.

Example 5 includes the apparatus of Example 4, wherein, in response to the single processor instruction, the circuitry is further to cause the processor to store the result of the second operation in a location indicated by the single processor instruction.

Example 6 includes the apparatus of any of Examples 4 to 5, wherein the single processor instruction includes a mask operand that indicates whether the first operation is an addition operation or a subtraction operation and whether the second operation is an addition operation or a subtraction operation.

Example 7 includes the apparatus of any of Examples 4 to 6, wherein, in response to the single processor instruction, the circuitry is further to cause the processor to provide an overflow indication to the processor if the intermediate value is larger than a threshold value.

Example 8 includes the apparatus of any of Examples 4 to 7, wherein, in response to the single processor instruction, the circuitry is further to cause the processor to provide an underflow indication to the processor if the intermediate value is less than zero.

Example 9 includes the apparatus of any of Examples 1 to 8, wherein one or more of the three or more input sources includes a scalar argument.

Example 10 includes an apparatus comprising decode circuitry to decode a single instruction, the single instruction to include respective fields for one or more source operands, one or more destination operands, and an opcode, the opcode to indicate execution circuitry is to perform a fused addition and subtraction operation, and execution circuitry to execute the decoded instruction according to the opcode to retrieve data from one or more locations indicated by the one or more source operands, to perform the fused addition and subtraction operation indicated by the opcode on three or more arguments indicated by the retrieved data to produce one or more results.

Example 11 includes the apparatus of Example 10, wherein the execution circuitry is further to execute the decoded instruction according to the opcode to store the one or more results in one or more locations indicated by the one or more destination operands.

Example 12 includes the apparatus of any of Examples 10 to 11, wherein the execution circuitry is further to execute the decoded instruction according to the opcode to perform a first operation to one of add and subtract first and second arguments of the three or more arguments to produce an intermediate value, wherein the first operation is indicated by one or more of the decoded instruction and the retrieved data, and perform a second operation to one of add and subtract the intermediate value and a third argument of the three or more arguments to produce one of the one or more results, wherein the second operation is indicated by one or more of the decoded instruction and the retrieved data.

Example 13 includes the apparatus of Example 12, wherein the retrieved data includes mask information, and wherein the execution circuitry is further to execute the decoded instruction according to the opcode to determine whether the first operation is an addition operation or a subtraction operation based on the mask information, and determine whether the second operation is an addition operation or a subtraction operation based on the mask information.

Example 14 includes the apparatus of any of Examples 12 to 13, wherein the execution circuitry is further to execute the decoded instruction according to the opcode to provide an overflow indication if the intermediate value is larger than a threshold value.

Example 15 includes the apparatus of any of Examples 12 to 14, wherein the execution circuitry is further to execute the decoded instruction according to the opcode to provide an underflow indication if the intermediate value is less than zero.

Example 16 includes the apparatus of any of Examples 10 to 15, wherein one or more of the three or more arguments is a scalar argument.

Example 17 includes a method, comprising fetching a single instruction having fields for an opcode, one or more destination operands, and one or more source operands, decoding the single instruction according to the opcode, retrieving data associated with the one or more source operands, scheduling execution of the instruction, and executing the decoded instruction to perform a fused addition and subtraction operation indicated by the opcode on three or more arguments indicated by the retrieved data to produce one or more results.

Example 18 includes the method of Example 17, further comprising storing the one or more results in one or more locations indicated by the one or more destination operands.

Example 19 includes the method of any of Examples 17 to 18, further comprising performing a first operation to one of add and subtract first and second arguments of the three or more arguments to produce an intermediate value, wherein the first operation is indicated by one or more of the decoded instruction and the retrieved data, and performing a second operation to one of add and subtract the intermediate value and a third argument of the three or more arguments to produce one of the one or more results, wherein the second operation is indicated by one or more of the decoded instruction and the retrieved data.

Example 20 includes the method of Example 19, further comprising determining whether the first operation is an addition operation or a subtraction operation based on mask information included in the retrieved data, and determining whether the second operation is an addition operation or a subtraction operation based on the mask information.

Example 21 includes the method of any of Examples 19 to 20, further comprising providing an overflow indication if the intermediate value is larger than a threshold value.

Example 22 includes the method of any of Examples 19 to 21, further comprising providing an underflow indication if the intermediate value is less than zero.

Example 23 includes the method of any of Examples 17 to 22, wherein one or more of the three or more arguments is a scalar argument.

Example 24 includes an apparatus, comprising means for fetching a single instruction having fields for an opcode, one or more destination operands, and one or more source operands, means for decoding the single instruction according to the opcode, means for retrieving data associated with the one or more source operands, means for scheduling execution of the instruction, and means for executing the decoded instruction to perform a fused addition and subtraction operation indicated by the opcode on three or more arguments indicated by the retrieved data to produce one or more results.

Example 25 includes the apparatus of Example 24, further comprising means for storing the one or more results in one or more locations indicated by the one or more destination operands.

Example 26 includes the apparatus of any of Examples 24 to 25, further comprising means for performing a first operation to one of add and subtract first and second arguments of the three or more arguments to produce an intermediate value, wherein the first operation is indicated by one or more of the decoded instruction and the retrieved data, and means for performing a second operation to one of add and subtract the intermediate value and a third argument of the three or more arguments to produce one of the one or more results, wherein the second operation is indicated by one or more of the decoded instruction and the retrieved data.

Example 27 includes the apparatus of Example 26, further comprising means for determining whether the first operation is an addition operation or a subtraction operation based on mask information included in the retrieved data, and means for determining whether the second operation is an addition operation or a subtraction operation based on the mask information.

Example 28 includes the apparatus of any of Examples 26 to 27, further comprising means for providing an overflow indication if the intermediate value is larger than a threshold value.

Example 29 includes the apparatus of any of Examples 26 to 28, further comprising means for providing an underflow indication if the intermediate value is less than zero.

Example 30 includes the apparatus of any of Examples 24 to 29, wherein one or more of the three or more arguments is a scalar argument.

Example 31 includes at least one non-transitory one machine readable medium comprising a plurality of instructions that, in response to being executed on a computing device, cause the computing device to fetch a single instruction having fields for an opcode, one or more destination operands, and one or more source operands, decode the single instruction according to the opcode, retrieve data associated with the one or more source operands, schedule execution of the instruction, and execute the decoded instruction to perform a fused addition and subtraction operation indicated by the opcode on three or more arguments indicated by the retrieved data to produce one or more results.

Example 32 includes the at least one non-transitory one machine readable medium of Example 31, comprising a plurality of further instructions that, in response to being executed on the computing device, cause the computing device to store the one or more results in one or more locations indicated by the one or more destination operands.

Example 33 includes the at least one non-transitory one machine readable medium of any of Examples 31 to 32, comprising a plurality of further instructions that, in response to being executed on the computing device, cause the computing device to perform a first operation to one of add and subtract first and second arguments of the three or more arguments to produce an intermediate value, wherein the first operation is indicated by one or more of the decoded instruction and the retrieved data, and perform a second operation to one of add and subtract the intermediate value and a third argument of the three or more arguments to produce one of the one or more results, wherein the second operation is indicated by one or more of the decoded instruction and the retrieved data.

Example 34 includes the at least one non-transitory one machine readable medium of Example 33, comprising a plurality of further instructions that, in response to being executed on the computing device, cause the computing device to determine whether the first operation is an addition operation or a subtraction operation based on mask information included in the retrieved data, and determine whether the second operation is an addition operation or a subtraction operation based on the mask information.

Example 35 includes the at least one non-transitory one machine readable medium of any of Examples 33 to 34, comprising a plurality of further instructions that, in response to being executed on the computing device, cause the computing device to provide an overflow indication if the intermediate value is larger than a threshold value.

Example 36 includes the at least one non-transitory one machine readable medium of any of Examples 33 to 35, comprising a plurality of further instructions that, in response to being executed on the computing device, cause the computing device to provide an underflow indication if the intermediate value is less than zero.

Example 37 includes the at least one non-transitory one machine readable medium of any of Examples 31 to 36, wherein one or more of the three or more arguments is a scalar argument.