Method of forming source and drain regions utilizing dual capping layers and split thermal processes

Source and drain regions are formed in a first-type semiconductor device. Then, a high tensile stress capping layer is formed over the source and drain regions. A thermal process is then performed to re-crystallize the source and drain regions and to introduce tensile strain into the source and drain regions of the first-type semiconductor device. Afterwards, source and drain regions are formed in a second-type semiconductor device. Then, a high compressive stress capping layer is formed over the source and drain regions of the second-type semiconductor device. A thermal process is performed to re-crystallize the source and drain regions and to introduce compressive strain into the source and drain regions of the second-type semiconductor device.

FIELD

This invention relates generally to semiconductor fabrication.

BACKGROUND

Currently, a polysilicon (“poly”) cap layer with high tensile stress is utilized to improve the performance of NMOS semiconductor devices. The poly cap layer is deposited over the NMOS device after a source and drain ion implantation and prior to a source and drain anneal. As the source and drain are annealed, the re-crystallization retains the stress of the poly cap layer formed over the source and drain. The tensile strain introduced into the source and drain improves charge carrier mobility in the NMOS device.

Typically, the poly cap layer is also formed over other semiconductor devices contained in the wafer, such as PMOS devices. The source and drain of both the PMOS and NMOS devices are subjected to an anneal, simultaneously, in order to re-crystallize the silicon of both the PMOS and NMOS devices. However, the high tensile stress of the poly cap layer does not improve the performance of the PMOS device. In fact, the PMOS device's performance may be degraded by the presence of the poly cap layer during the source and drain anneal. As such, processes are needed that allow tensile stain to be introduced into an NMOS device without adversely affecting a PMOS device.

SUMMARY OF THE INVENTION

An embodiment of the present disclosure is directed to a method of fabricating a semiconductor device. The method includes forming a source region and a drain region in at least one NMOS semiconductor region; forming a tensile stress capping layer over the at least one NMOS semiconductor region and at least one PMOS semiconductor region; performing a thermal process to re-crystallize the source region and drain region of the NMOS semiconductor region and to introduce tensile strain to the source region and drain region of the NMOS semiconductor region; and forming a source region and drain region in the at least one PMOS semiconductor region.

Another embodiment is directed to a method of fabricating a semiconductor device. The method includes forming a source region and a drain region in at least one PMOS semiconductor region; forming a compressive stress capping layer over the at least one PMOS semiconductor region and at least one NMOS semiconductor region; performing a thermal process to re-crystallize the source region and drain region of the PMOS semiconductor region and to introduce compressive strain to the source region and drain region of the PMOS semiconductor region; and forming a source region and drain region in the at least one NMOS semiconductor region.

Another embodiment is directed to a method of fabricating a semiconductor device. The method includes forming a source region and a drain region in at least one a first-type semiconductor region; forming a tensile stress capping layer over the at least one first-type semiconductor region and at least one second-type semiconductor region; performing a thermal process to re-crystallize the source region and drain region of the first-type semiconductor region and to introduce tensile strain to the source region and drain region of the first-type semiconductor region; and forming a source region and drain region in the at least one second-type semiconductor region.

Another embodiment of the present disclosure is directed to a method of fabricating a semiconductor device. The method includes forming a source region and a drain region in at least one NMOS semiconductor region; forming a tensile stress capping layer over the at least one NMOS semiconductor region and at least one PMOS semiconductor region; performing a thermal process to re-crystallize the source region and drain region of the NMOS semiconductor region and to introduce tensile strain to the source region and drain region of the NMOS semiconductor region; removing portions of the tensile stress capping layer to form sidewalls on at least one NMOS gate of the at least one NMOS semiconductor region and at least one PMOS gate of the at least one PMOS semiconductor region; and forming a source region and drain region in the at least one PMOS semiconductor region.

Another embodiment is directed to a method of fabricating a semiconductor device. The method includes forming a source region and a drain region in at least one PMOS semiconductor region; forming a compressive stress capping layer over the at least one PMOS semiconductor region and at least one NMOS semiconductor region; performing a thermal process to re-crystallize the source region and drain region of the PMOS semiconductor region and to introduce compressive strain to the source region and drain region of the PMOS semiconductor region; removing portions of the compressive stress capping layer to form sidewalls on at least one NMOS gate of the at least one NMOS semiconductor region and at least one PMOS gate of the at least one PMOS semiconductor region; and forming a source region and drain region in the at least one NMOS semiconductor region.

Another embodiment is directed to a method of fabricating a semiconductor device. The method includes forming a source region and a drain region in at least one first-type semiconductor region; forming a tensile stress capping layer over the at least one first-type semiconductor region and at least one second-type semiconductor region; performing a thermal process to re-crystallize the source region and drain region of the first-type semiconductor region and to introduce tensile strain to the source region and drain region of the first-type semiconductor region; removing portions of the tensile stress capping layer to form sidewalls on at least one gate of the at least one first-type semiconductor region and at least one gate of the at least one second-type semiconductor region; and forming a source region and drain region in the at least one second-type semiconductor region.

Additional embodiments of the disclosure will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the present disclosure. The embodiments of the disclosure will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims.

DESCRIPTION OF THE EMBODIMENTS

Embodiments of the present disclosure are directed to a method of forming source and drain regions utilizing dual capping layers and split thermal processes. In the method, source and drain regions are formed in a first-type semiconductor device. Then, a high tensile stress capping layer is formed over the source and drain regions. A thermal process is then performed to re-crystallize the source and drain regions and to introduce tensile strain into the source and drain regions of the first-type semiconductor device.

Afterwards, source and drain regions are formed in a second-type semiconductor device. Then, a high compressive stress capping layer is formed over the source and drain regions of the second-type semiconductor device. A thermal process is performed to re-crystallize the source and drain regions and to introduce compressive strain into the source and drain regions of the second-type semiconductor device. Additionally, the capping layers can be utilized to form sidewalls on gates of the first-type and second-type semiconductor devices.

By utilizing separate capping layers and thermal processes, different-type semiconductor devices can be individually optimized without adversely affecting the devices during processing.

Reference will now be made in detail to the exemplary embodiments of the present disclosure, an example of which is illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.

In the following description, reference is made to the accompanying drawings that form a part thereof and in which is shown by way of illustration specific exemplary embodiments which may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the embodiments and it is to be understood that other embodiments may be utilized and that changes may be made without departing from the scope of the invention. The following description is, therefore, merely exemplary.

FIG. 1is a flow diagram illustrating a method100for forming source and drain regions in different-type semiconductor regions. Method100begins with forming source and drain regions in a first-type semiconductor region (stage102). The source and drain regions may be formed by implanting ions in the first-type semiconductor region. As such, amorphization occurs in a gate and the source and drain regions. The first-type semiconductor region can be any type of partially completed, well-known semiconductor device that was formed using any type of well-known technique. For example, first-type semiconductor region can be a MOSFET, such as an NMOS, PMOS, or other suitable semiconductor device. The first-type semiconductor region can include conventional features such as a gate with sidewalls formed over a well region.

The source and drain region can be formed by an ion implantation. The ion implantation causes amorphization in the gate and source and drain region. The ion implantation may be performed using any suitable techniques available in semiconductor processing for ion implantation. For example, boron or other suitable P-type dopant may be implanted during the ion implantation process to form the source region and the drain region. Likewise, arsenic, phosphorous, antimony, or other suitable N-type dopant may be implanted.

Next, a tensile stress capping layer is formed over the first-type semiconductor region and a second-type semiconductor region (stage104). The tensile stress capping layer can be any type of suitable tensile stress layer. For example, the tensile stress capping layer can be one or more nitride layers, one or more oxide layers, combination thereof and the like.

The second-type semiconductor region can be any type of partially completed, well-known semiconductor device that was formed using any type of well-known technique, but different than the first-type semiconductor device. For example, the second-type semiconductor region can be a MOSFET, such as an NMOS, PMOS, or other suitable semiconductor device. The second-type semiconductor region can include conventional features such as a gate with sidewalls formed over a well region. During forming the source and drain regions for the first-type semiconductor region, the second-type semiconductor region is masked to prevent the formation of source and drain regions in the second-type semiconductor device.

After forming the tensile stress capping layer, a thermal process is performed (stage106). The thermal process re-crystallizes the source and drain regions of the first-type semiconductor region. Additionally, the thermal process transfers the tensile stress of the capping layer and introduces tensile strain into the source and drain regions of the first-type semiconductor region.

The thermal process can be any type of suitable process available in semiconductor processing to re-crystallize source and drain regions of the first-type semiconductor region. The thermal process can be an anneal performed at a temperature in a range from approximately 750° C. to approximately 1300° C. for a time period in a range from milliseconds to approximately 5 hours.

After the thermal process, the tensile stress capping layer is removed. Then, source and drain regions are formed in the second-type semiconductor region (stage108). The source and drain region can be formed by an ion implantation. The ion implantation causes amorphization in the gate and source and drain region. The ion implantation may be performed using any suitable techniques available in semiconductor processing for ion implantation. For example, boron or other suitable P-type dopant may be implanted during the ion implantation process to form the source region and the drain region. Likewise, arsenic, phosphorous, antimony, or other suitable N-type dopant may be implanted.

During formation of the source and drain region of the second-type semiconductor region, the first-type semiconductor region is masked to prevent the formation of source and drain regions in the first-type semiconductor region.

Then, a compressive stress capping layer is formed over the second-type semiconductor region and the first-type semiconductor region (stage110). The compressive stress capping layer can be any type of suitable compressive stress layer. For example, the compressive stress capping layer can be one or more nitride layers, one or more oxide layers, combination thereof, and the like.

After forming the compressive stress capping layer, a thermal process is performed (stage112). The thermal process re-crystallizes the source and drain regions of the second-type semiconductor region. Additionally, the thermal process transfers the compressive stress of the capping layer and introduces compressive strain into the source and drain regions of the second-type semiconductor region.

The thermal process can be any type of suitable process available in semiconductor processing to re-crystallizes source and drain regions of the second-type semiconductor region. The thermal process can be an anneal performed at a temperature in a range from approximately 750° C. to approximately 1300° C. for a time period in a range from milliseconds to approximately 5 hours.

Afterwards, the compressive stress capping layer is removed (stage114). Then, further processing can be preformed on the first-type and the second-type semiconductor regions. By utilizing separate capping layers and separate thermal processes for the different-type semiconductor regions, each device can be optimized without adversely affecting the other type region.

FIGS. 2A-2Hare diagrams illustrating an exemplary method for forming source and drain regions for an NMOS and PMOS semiconductor regions. According to embodiments of the present disclosure, dual capping layers and split anneal processes are utilized to form the source and drain regions.

FIG. 2Ashows a partially completed semiconductor device200including a partially completed NMOS semiconductor device and PMOS semiconductor device. As illustrated, device200includes a substrate202, an NMOS region204, and a PMOS region206. Substrate202may be formed from any suitable semiconductor material, such as silicon. For example, substrate202may be a silicon wafer, a silicon wafer with previously embedded devices, an epitaxial layer grown on a wafer, a semiconductor on insulation (“SOI”) system, or other suitable substrates having any suitable crystal orientation.

NMOS region204and PMOS region206can include various components of a partially completed semiconductor device such as a NMOS transistor and PMOS transistor, respectively. As illustrated, NMOS region204can include a P-well208. PMOS region206can include an N-well210. P-well208and N-well210can be formed utilizing any type of suitable technique used in semiconductor processing, such as doping.

NMOS region204and PMOS region206can be separated by an isolation feature212. Isolation feature212can be formed of any suitable isolation structure such as shallow trench isolation (STI) regions, field oxide regions (LOCOS), and the like.

NMOS region204can include a gate214formed over P-well208. Gate214can be formed of any well-known suitable materials by any suitable well-known techniques. For example, gate214can be formed using any suitable growth and/or deposition techniques using semiconductor processing and can be formed from any suitable material, such as polysilicon.

NMOS region204can include n-type extension regions218. Extension regions218can be formed utilizing any suitable well-known techniques. For example, PMOS region206can be covered with a mask material and n-type dopants can be implanted in NMOS region204.

Gate214can include sidewalls216formed on the side of gate214. Sidewalls216can be formed of any well-known suitable materials by any suitable well-known techniques. For example, sidewalls216can be formed using any suitable growth and/or deposition techniques using semiconductor processing and can be formed from any suitable dielectric materials, such as oxide, nitride, a combination of oxide and nitride, or other suitable materials.FIG. 2Aillustrates gate214with a pair of sidewalls216but one skilled in the art will realize that gate214can include additional sidewalls. Additionally, a gate oxide can be formed between gate214and substrate202.

PMOS region206can include a gate220formed over N-well210. Gate220can be formed of any well-known suitable materials by any suitable well-known techniques. For example, gate220can be formed using any suitable growth and/or deposition techniques using semiconductor processing and can be formed from any suitable material, such as polysilicon.

PMOS region206can include p-type extension regions224. Extension regions224can be formed utilizing any suitable well-known techniques. For example, NMOS region204can be covered with a mask material and p-type dopants can be implanted in PMOS region206.

Gate220can include sidewalls222formed on the side of gate220. Sidewalls222can be formed of any well-known suitable materials by any suitable well-known techniques. For example, sidewalls222can be formed using any suitable growth and/or deposition techniques using semiconductor processing and can be formed from any suitable dielectric materials, such as oxide, nitride, a combination of oxide and nitride, or other suitable materials.FIG. 2Aillustrates gate220with a pair of sidewalls222but one skilled in the art will realize that gate220can include additional sidewalls. Additionally, a gate oxide can be formed between gate220and substrate202.

As illustrated inFIG. 2B, according to embodiments of the present disclosure, source and drain regions230are formed in NMOS region204. Source and drain regions230can be formed in P-well208using any suitable techniques used in semiconductor processing, such as ion implantation.

Source and drain regions230can be formed by forming a resist mask226over PMOS region206. Resist mask226can be formed over the entire substrate202and a portion may be removed to expose NMOS region204. Resist mask226can be formed of any suitable material to block implantation of ions in PMOS region206.

An ion implantation228is performed to form source and drain regions230. For example, arsenic, phosphorous, antimony, or other suitable n-type dopants can be implanted in P-well208during ion implantation228to form source and drain regions230. Additionally, during ion implantation, a doped region232may be formed at the top of gate214.

As illustrated inFIG. 2C, after forming source and drain regions242, resist mask226is removed. Resist mask226can be removed utilizing any type of suitable technique available in semiconductor processing. For example, resist mask226can be removed utilizing an etch, an O2ashing, combination thereof, and the like.

Then, a capping layer234is formed over NMOS region204and PMOS region206. Capping layer234can be a high tensile stress layer in order to introduce tensile strain into source and drain regions230. Capping layer234can be any type of suitable tensile stress layer. For example, capping layer234can be one or more nitride layers, one or more oxide layers, combination thereof, and the like.

Capping layer234can be formed utilizing any type of well-known suitable technique available in semiconductor processing. For example, capping layer234can be formed using any suitable deposition techniques, such as chemical vapor deposition (CVD).

As illustrated inFIG. 2D, after forming capping layer234, device200is subjected to a thermal process236. Thermal process236re-crystallizes source and drain regions230and doped region232, damaged during ion implantation228. According to embodiments of the present disclosure, thermal process236transfers the tensile stress of capping layer234to source and drain region230and doped region232and introduces tensile stain into source and drain region230and doped region232. Additionally, since PMOS region206does not include an amorphized gate, source and drain regions, PMOS region206is unaffected by the thermal process.

Thermal process236can be any type of suitable process available in semiconductor processing to re-crystallizes source and drain regions230and doped region232. For example, thermal process236can be an anneal performed at a temperature in a range from approximately 750° C. to approximately 1300° C. for a time period in a range from milliseconds to approximately 5 hours.

As illustrated inFIG. 2E, after thermal process236, capping layer234is removed from device200. Capping layer234can be removed utilizing any type of suitable technique available in semiconductor processing. For example, capping layer234can be removed utilizing an etch, chemical mechanical polish, combination thereof, and the like.

Then, source and drain regions242are formed in PMOS region206. Source and drain regions242can be formed in N-well210using any suitable techniques available in semiconductor processing, such as ion implantation. Source and drain regions242can be formed by forming a resist mask238over NMOS region204. Resist mask238can be formed over the entire substrate202and a portion may be removed to expose PMOS region206. Resist mask238can be formed of any suitable material to block implantation of ions in NMOS region204.

An ion implantation240is performed to form source and drain regions242. For example, boron or other suitable P-type dopants can be implanted in N-well210during ion implantation240to form source and drain regions242. Additionally, during ion implantation, a doped region244may be formed at the top of gate220.

As illustrated inFIG. 2F, after forming source and drain regions242, resist mask238is removed. Resist mask238can be removed utilizing any type of suitable technique available in semiconductor processing. For example, resist mask238can be removed utilizing an etch, an O2ashing, combination thereof and the like.

Then, a capping layer246is formed over NMOS region204and PMOS region206. Accordingly to embodiments of the present disclosure, capping layer246can be a high compressive stress layer in order to introduce compressive strain into source and drain regions242. Capping layer246can be any type of suitable compressive stress layer. For example, capping layer246can be one or more nitride layers, one or more oxide layers, combination thereof and the like.

Capping layer246can be formed utilizing any type of suitable technique available in semiconductor processing. For example, capping layer246can be formed using any deposition techniques, such as CVD.

As illustrated inFIG. 2G, after forming capping layer246, device200is subjected to a thermal process248. Thermal process248re-crystallizes source and drain regions242and doped region244, damaged during ion implantation240. According to embodiments of the present disclose, thermal process248transfers the compressive stress of capping layer246to source and drain region242and doped region244and introduces compressive stain into source and drain region242and doped region244. Additionally, NMOS region204is unaffected by thermal process248since source and drain regions230have been re-crystallized.

Thermal process248can be any type of suitable process available in semiconductor processing to re-crystallizes source and drain regions242and doped region244. For example, thermal process248can be an anneal performed at a temperature in a range from approximately 750° C. to approximately 1300° C. for a time period in a range from milliseconds to approximately 5 hours.

Afterwards, as illustrated inFIG. 2H, capping layer246is removed from device200. Capping layer246can be removed utilizing any type of suitable technique available in semiconductor processing. For example, capping layer246can be removed utilizing an etch, chemical mechanical polish, combination thereof, and the like. After formation of source and drain regions230and242further semiconductor processing can be performed to complete device200.

In embodiments of the present disclosure described above, device200includes an NMOS region and a PMOS region. One skilled in the art will realize that device200may include multiple NMOS regions, multiple PMOS regions, and other semiconductor features. As such, the method described above can be performed on the multiple NMOS regions and PMOS regions.

In the method described above, processing to re-crystallize doped region232and source and drain region230of NMOS region204is performed first. According to another embodiment of the present disclosure, processing to re-crystallize doped region244source and drain regions242can be performed prior to processing the NMOS device. In this embodiment, the stages illustrated inFIGS. 2E-2Gcan be performed prior to the stages illustrated inFIGS. 2B-2D.

In the method described above, both a capping layer234and a capping layer246are utilized. According to another embodiment of the present disclosure, only one capping layer can be utilized. In this embodiment, the method would be as illustrated inFIGS. 2A-2Hwith capping layer234and a capping layer246being omitted.

According to another embodiment of the present disclosure, either capping layer234or capping layer246can be utilized as a resist mask in forming source and drain regions.FIG. 2Iis a diagram illustrating using capping layer234as a resist mask in forming source and drain regions242.

In this embodiment, a resist mask can be used to pattern capping layer234or capping layer246in order to selectively remove capping layer234or capping layer246from PMOS region206or NMOS region204. As illustrated inFIG. 2I, after thermal process236FIG2D, a portion of capping layer234can be removed to expose PMOS region206. The portion of capping layer246can be removed utilizing any type of suitable technique available in semiconductor processing. For example, capping layer246can be patterned and removed utilizing an etch, such as an reactive ion etch. The remaining portion252of capping layer234would function during implantation250shown inFIG. 2Ias implant mask238functions during implantation240shown in FIG2E.

In addition, if processing on PMOS region206is performed first, a portion of capping layer246can be removed. As such, resist mask226can be omitted and the remaining portion of capping layer246can function as resist mask226in forming source and drain regions230.

According to another embodiment of the present disclosure, a capping layer used to transfer tensile or compressive stress can be used to form sidewalls on gates of PMOS and NMOS devices.FIGS. 3A-3Iare diagrams illustrating an exemplary method for forming source and drain regions for an NMOS and PMOS semiconductor regions consistent with embodiments of the present disclosure.

FIG. 3Ashows a partially completed semiconductor device300including a partially completed NMOS semiconductor device and PMOS semiconductor device. As illustrated, device300includes a substrate302, an NMOS region304, and a PMOS region306. Substrate302may be formed from any suitable semiconductor material, such as silicon. For example, substrate302may be a silicon wafer, a silicon wafer with previously embedded devices, an epitaxial layer grown on a wafer, a SOI system, or other suitable substrates having any suitable crystal orientation.

NMOS region304and PMOS region306can include various components of a partially completed semiconductor device such as a NMOS transistor and PMOS transistor, respectively. As illustrated, NMOS region304can include a P-well308. PMOS region306can include an N-well310. P-well308and N-well310can be formed utilizing any type of suitable technique used in semiconductor processing, such as doping.

NMOS region304and PMOS region306can be separated by an isolation feature312. Isolation feature312can be formed of any suitable isolation structure such as STI regions, LOCOS, and the like.

NMOS region304can include a gate314formed over P-well308. Gate314can be formed of any well-known suitable materials by any suitable well-known techniques. For example, gate314can be formed using any suitable growth and/or deposition techniques using semiconductor processing and can be formed from any suitable material, such as polysilicon.

PMOS region306can include a gate316formed over N-well310. Gate316can be formed of any well-known suitable materials by any suitable well-known techniques. For example, gate316can be formed using any suitable growth and/or deposition techniques using semiconductor processing and can be formed from any suitable material, such as polysilicon.

As illustrated inFIG. 3B, according to embodiments of the present disclosure, source and drain regions318are formed in NMOS region304. Source and drain regions318can be formed in P-well308using any suitable techniques used in semiconductor processing, such as ion implantation320.

Source and drain regions318can be formed by forming a resist mask322over PMOS region306. Resist mask322can be formed over the entire substrate302and a portion may be removed to expose NMOS region304. Resist mask322can be formed of any suitable material to block implantation of ions in PMOS region306.

An ion implantation320is performed to form source and drain regions318. For example, arsenic, phosphorous, antimony, or other suitable n-type dopants can be implanted in P-well308during ion implantation320to form source and drain regions318. Additionally, during ion implantation, a doped region324can be formed at the top of gate314. Ion implantation320causes the silicon of P-well308and gate314to amorphize.

As illustrated inFIG. 3C, after forming source and drain regions318, resist mask322is removed. Resist mask322can be removed utilizing any type of suitable technique available in semiconductor processing. For example, resist mask322can be removed utilizing an etch, an O2ashing, combination thereof, and the like.

Then, a capping layer326is formed over NMOS region304and PMOS region306. Capping layer326can be a high tensile stress layer in order to introduce tensile strain into source and drain regions318and doped region324. Capping layer326can be any type of suitable tensile stress layer. For example, capping layer326can be one or more nitride layers, one or more oxide layers, combination thereof, and the like.

Capping layer326can be formed utilizing any type of well-known suitable technique available in semiconductor processing. For example, capping layer326can be formed using any suitable deposition techniques, such as CVD.

As illustrated inFIG. 3D, after forming capping layer326, device300is subjected to a thermal process328. Thermal process328re-crystallizes source and drain regions318and doped region324, damaged during ion implantation320. According to embodiments of the present disclose, thermal process328transfers the tensile stress of capping layer326to source and drain region318and doped region324and introduces tensile stain into source and drain region318and doped region324. Additionally, since PMOS region306does not include an amorphized gate, source and drain regions, PMOS region306is unaffected by the thermal process.

Thermal process328can be any type of suitable process available in semiconductor processing to re-crystallizes source and drain regions318and doped region324. For example, thermal process328can be an anneal performed at a temperature in a range from approximately 750° C. to approximately 1300° C. for a time period in a range from milliseconds to approximately 5 hours.

As illustrated inFIG. 3E, according to embodiments of the present disclosure, after thermal process328, portions of capping layer326are removed. Portions of capping layer326are removed to form sidewalls330on gate314and gate316. Capping layer326can be removed utilizing any type of suitable technique available in semiconductor processing. For example, capping layer234can be removed utilizing an etch332, such as a dry etch.

Then, as illustrated inFIG. 3F, source and drain regions334are formed in PMOS region306. Source and drain regions334can be formed in N-well310using any suitable techniques available in semiconductor processing, such an ion implantation336. Source and drain regions334can be formed by forming a resist mask338over NMOS region304. Resist mask338can be formed over the entire substrate302and a portion may be removed to expose PMOS region306. Resist mask338can be formed of any suitable material to block implantation of ions in NMOS region304.

An ion implantation336is performed to form source and drain region334. For example, boron or other suitable P-type dopants can be implanted in N-well310during ion implantation336to form source and drain regions334. Additionally, during ion implantation, a doped region340may be formed at the top of gate316.

As illustrated inFIG. 3G, after forming source and drain regions334, resist mask338is removed. Resist mask338can be removed utilizing any type of suitable technique available in semiconductor processing. For example, resist mask338can be removed utilizing an etch, an O2ashing, combination thereof, and the like.

Then, a capping layer342is formed over NMOS region304and PMOS region306. Accordingly to embodiments of the present disclosure, capping layer342can be a high compressive stress layer in order to introduce compressive strain into source and drain regions334and doped region340. Capping layer342can be any type of suitable compressive stress layer. For example, capping layer342can be one or more nitride layers, one or more oxide layers, combination thereof, and the like.

Capping layer342can be formed utilizing any type of suitable technique available in semiconductor processing. For example, capping layer342can be formed using any suitable deposition techniques, such as CVD.

As illustrated inFIG. 3H, after forming capping layer342, device300is subjected to a thermal process344. Thermal process344re-crystallizes source and drain regions334and doped region340, damaged during ion implantation336. According to embodiments of the present disclose, thermal process344transfers the compressive stress of capping layer342to source and drain region334and doped region340and introduces compressive stain into source and drain region334and doped region340. Additionally, NMOS region304is unaffected by thermal process344since source and drain regions318and doped region324have been re-crystallized.

Thermal process344can be any type of suitable process available in semiconductor processing to re-crystallizes source and drain regions334and doped region340. For example, thermal process344can be an anneal performed at a temperature in a range from approximately 750° C. to approximately 1300° C. for a time period in a range from milliseconds to approximately 5 hours.

Afterwards, as illustrated inFIG. 3I, capping layer342is removed from device300. Capping layer342can be removed utilizing any type of suitable technique available in semiconductor processing. For example, capping layer342can be removed utilizing an etch, chemical mechanical polish, combination thereof, and the like. After formation of source and drain regions318and334further semiconductor processing can be performed to complete device300.

In embodiments of the present disclosure described above, device300includes an NMOS region and a PMOS region. One skilled in the art will realize that device300may include multiple NMOS regions, multiple PMOS regions, and other semiconductor features. As such, the method described above can be performed on the multiple NMOS regions and PMOS regions.

In the method described above, processing to form and to re-crystallize doped region324and source and drain region318of NMOS region304is performed first. According to another embodiment of the present disclosure, the source and drain regions of the PMOS region may be formed first, prior to processing the NMOS region. In this embodiment, processing to form and re-crystallize doped region340and source and drain regions334can be performed prior to processing the NMOS device. In this embodiment, the stages illustrated inFIGS. 3F-31can be performed prior to the stages illustrated inFIGS. 3B-3Ewith capping layer342being utilized to from sidewalls330.

In the method described above, both a capping layer326and a capping layer342are utilized. According to another embodiment of the present disclosure, only one capping layer can be utilized. In this embodiment, the method would be as illustrated inFIGS. 3A-3Iwith capping layer326and a capping layer342being omitted.