Selective page calibration based on hierarchical page mapping

A computer-implemented method, according to one embodiment, includes: detecting that a calibration of a first page group has been triggered, and evaluating a hierarchical page mapping to determine whether the first page group correlates to one or more other page groups in non-volatile memory. In response to determining that the first page group does correlate to one or more other page groups in the non-volatile memory, a determination is made as to whether to promote at least one of the one or more other page groups for calibration. In response to determining to promote at least one of the one or more other page groups for calibration, the first page group and the at least one of the one or more other page groups are calibrated. Moreover, each of the page groups includes one or more pages in non-volatile memory.

BACKGROUND

The present invention relates to non-volatile memory such as NAND Flash memory, and more particularly, this invention relates to selectively calibrating pages in non-volatile memory based on hierarchical page mapping.

Using Flash memory as an example, the performance characteristics of conventional NAND Flash-based solid state drives (SSDs) are fundamentally different from those of traditional hard disk drives (HDDs). Data in conventional SSDs is typically organized in pages of 4, 8, or 16 KB sizes. Moreover, page read operations in SSDs are typically one order of magnitude faster than write operations and latency neither depends on the current nor the previous location of operations.

The raw bit error rate (RBER) of a Flash memory block will typically increase over time due to additional program and erase cycling, charge leakage from retention, and additional charge placed in the cells by read operations (i.e., read disturb errors). Typically, a Flash memory block is retired when any page in the block exhibits a code word that reaches a page retirement error count limit. This limit is typically set to be achieved in conjunction with an appropriate error correction code (ECC), with the RBER for a Flash memory block being set to be similar to the RBER in traditional hard disk drives, e.g., at around 10−15, but may be more or less.

Read voltage shifting, also known as block calibration, has been shown to be a key contributor to enhance endurance and retention, particularly for enterprise-level Flash memory systems using modern three-dimensional (3-D) triple-level-cell (TLC) or quad-level-cell (QLC) NAND Flash memory. Previous attempts to maintain efficient memory performance typically included inspecting the read voltages for each block of memory in a sweeping fashion or by a read voltage shifting algorithm that tracks and corrects the read voltages depending on how the threshold voltage distributions have changed as a result of cycling or retention or other disturbing effects. Moreover, upon identifying a block which was a calibration candidate, these previous attempts would perform block-level calibrations in which all pages in the identified block would be calibrated. It follows that these previous attempts involved inspecting each block in memory individually. Furthermore, although a block of memory is identified as being a candidate for calibration, typically not all pages in the block benefit from the calibration.

SUMMARY

A computer-implemented method, according to one embodiment, includes: detecting that a calibration of a first page group has been triggered, and evaluating a hierarchical page mapping to determine whether the first page group correlates to one or more other page groups in non-volatile memory. In response to determining that the first page group does correlate to one or more other page groups in the non-volatile memory, a determination is made as to whether to promote at least one of the one or more other page groups for calibration. In response to determining to promote at least one of the one or more other page groups for calibration, the first page group and the at least one of the one or more other page groups are calibrated. Moreover, each of the page groups includes one or more pages in non-volatile memory.

A computer-implemented method, according to another embodiment, includes: detecting that a bit error count of a first page group has triggered a calibration of the first page group, and calibrating the first page group. A determination is made as to whether an updated bit error count of the calibrated first page group is above a threshold. In response to determining that the updated bit error count of the calibrated first page group is above the threshold, a hierarchical page mapping is evaluated to determine whether the first page group correlates to one or more other page groups in non-volatile memory. In response to determining that the first page group does correlate to one or more other page groups in the non-volatile memory, at least one of the one or more other page groups is calibrated. Moreover, each of the page groups includes one or more pages in non-volatile memory.

A computer program product, according to yet another embodiment, includes a computer readable storage medium having program instructions embodied therewith. The computer readable storage medium is not a transitory signal per se. Moreover, the program instructions readable and/or executable by a processor to cause the processor to perform a method which includes: detecting, by the processor, that a calibration of a first page group has been triggered; and evaluating, by the processor, a hierarchical page mapping to determine whether the first page group correlates to one or more other page groups in non-volatile memory. In response to determining that the first page group does correlate to one or more other page groups in the non-volatile memory, a determination is made, by the processor, as to whether to promote at least one of the one or more other page groups for calibration. In response to determining to promote at least one of the one or more other page groups for calibration, the first page group and the at least one of the one or more other page groups are calibrated by the processor. Moreover, each of the page groups includes one or more pages in non-volatile memory.

DETAILED DESCRIPTION

The following description discloses several preferred embodiments of data storage systems, as well as operation and/or component parts thereof. It should be appreciated that various embodiments herein can be implemented with a wide range of memory mediums, including for example non-volatile random access memory (NVRAM) technologies such as NAND Flash memory, NOR Flash memory, phase-change memory (PCM), magnetoresistive RAM (MRAM) and resistive RAM (RRAM). To provide a context, and solely to assist the reader, various embodiments may be described with reference to a type of non-volatile memory. This has been done by way of example only, and should not be deemed limiting on the invention defined in the claims.

In one general embodiment, a computer-implemented method includes: detecting that a calibration of a first page group has been triggered, and evaluating a hierarchical page mapping to determine whether the first page group correlates to one or more other page groups in non-volatile memory. In response to determining that the first page group does correlate to one or more other page groups in the non-volatile memory, a determination is made as to whether to promote at least one of the one or more other page groups for calibration. In response to determining to promote at least one of the one or more other page groups for calibration, the first page group and the at least one of the one or more other page groups are calibrated. Moreover, each of the page groups includes one or more pages in non-volatile memory.

In another general embodiment, a computer-implemented method includes: detecting that a bit error count of a first page group has triggered a calibration of the first page group, and calibrating the first page group. A determination is made as to whether an updated bit error count of the calibrated first page group is above a threshold. In response to determining that the updated bit error count of the calibrated first page group is above the threshold, a hierarchical page mapping is evaluated to determine whether the first page group correlates to one or more other page groups in non-volatile memory. In response to determining that the first page group does correlate to one or more other page groups in the non-volatile memory, at least one of the one or more other page groups is calibrated. Moreover, each of the page groups includes one or more pages in non-volatile memory.

In yet another general embodiment, a computer program product includes a computer readable storage medium having program instructions embodied therewith. The computer readable storage medium is not a transitory signal per se. Moreover, the program instructions readable and/or executable by a processor to cause the processor to perform a method which includes: detecting, by the processor, that a calibration of a first page group has been triggered; and evaluating, by the processor, a hierarchical page mapping to determine whether the first page group correlates to one or more other page groups in non-volatile memory. In response to determining that the first page group does correlate to one or more other page groups in the non-volatile memory, a determination is made, by the processor, as to whether to promote at least one of the one or more other page groups for calibration. In response to determining to promote at least one of the one or more other page groups for calibration, the first page group and the at least one of the one or more other page groups are calibrated by the processor. Moreover, each of the page groups includes one or more pages in non-volatile memory.

FIG. 1illustrates a memory card100, in accordance with one embodiment. It should be noted that although memory card100is depicted as an exemplary non-volatile data storage card in the present embodiment, various other types of non-volatile data storage cards may be used in a data storage system according to alternate embodiments. It follows that the architecture and/or components of memory card100are in no way intended to limit the invention, but rather have been presented as a non-limiting example.

Moreover, as an option, the present memory card100may be implemented in conjunction with features from any other embodiment listed herein, such as those described with reference to the other FIGS. However, such memory card100and others presented herein may be used in various applications and/or in permutations which may or may not be specifically described in the illustrative embodiments listed herein. Further, the memory card100presented herein may be used in any desired environment.

With continued reference toFIG. 1, memory card100includes a gateway102, a general purpose processor (GPP)112(such as an ASIC, FPGA, CPU, etc.) connected to a GPP memory114(which may comprise RAM, ROM, battery-backed DRAM, phase-change memory PC-RAM, MRAM, STT-MRAM, etc., or a combination thereof), and a number of memory controllers108, which include Flash controllers in the present example. Each memory controller108is connected to a plurality of NVRAM memory modules104(which may comprise NAND Flash or other non-volatile memory type(s) such as those listed above) via channels106.

According to various embodiments, one or more of the controllers108may be or include one or more processors, and/or any logic for controlling any subsystem of the memory card100. For example, the controllers108typically control the functions of NVRAM memory modules104such as, data writing, data recirculation, data reading, etc. The controllers108may operate using logic known in the art, as well as any logic disclosed herein, and thus may be considered as a processor for any of the descriptions of non-volatile memory included herein, in various embodiments.

Moreover, the controller108may be configured and/or programmable to perform or control some or all of the methodology presented herein. Thus, the controller108may be considered to be configured to perform various operations by way of logic programmed into one or more chips, modules, and/or blocks; software, firmware, and/or other instructions being available to one or more processors; etc., and combinations thereof.

Referring still toFIG. 1, each memory controller108is also connected to a controller memory110which preferably includes a cache which replicates a non-volatile memory structure according to the various embodiments described herein. However, depending on the desired embodiment, the controller memory110may be battery-backed DRAM, phase-change memory PC-RAM, MRAM, STT-MRAM, etc., or a combination thereof.

As previously mentioned, memory card100may be implemented in various types of data storage systems, depending on the desired embodiment.FIG. 2illustrates a data storage system architecture200according to an exemplary embodiment which is in no way intended to limit the invention. Moreover, it should be noted that the data storage system220ofFIG. 2may include various components found in the embodiment ofFIG. 1.

Looking toFIG. 2, the data storage system220comprises a number of interface cards202configured to communicate via I/O interconnections204to one or more processor systems201. The data storage system220may also comprise one or more RAID controllers206configured to control data storage in a plurality of non-volatile data storage cards208. The non-volatile data storage cards208may comprise NVRAM, Flash memory cards, RAM, ROM, and/or some other known type of non-volatile memory.

The I/O interconnections204may include any known communication protocols, such as Fiber Channel (FC), FC over Ethernet (FCoE), Infiniband, Internet Small Computer System Interface (iSCSI), Transport Control Protocol/Internet Protocol (TCP/IP), Peripheral Component Interconnect Express (PCIe), etc., and/or any combination thereof.

The RAID controller(s)206in the data storage system220may perform a parity scheme similar to that employed by RAID-5, RAID-10, or some other suitable parity scheme, as would be understood by one of skill in the art upon reading the present descriptions.

Each processor system201comprises one or more processors210(such as CPUs, microprocessors, etc.), local data storage211(e.g., such as RAM1114ofFIG. 11, ROM1116ofFIG. 11, etc.), and an I/O adapter218configured to communicate with the data storage system220.

Referring again toFIG. 1, memory controllers108and/or other controllers described herein (e.g., RAID controllers206ofFIG. 2) may be able to perform various functions on stored data, depending on the desired embodiment. Specifically, memory controllers may include logic configured to perform any one or more of the following functions, which are in no way intended to be an exclusive list. In other words, depending on the desired embodiment, logic of a storage system may be configured to perform additional or alternative functions, as would be appreciated by one skilled in the art upon reading the present description.

Garbage Collection

Garbage collection in the context of SSD memory controllers of the present description may include the process of identifying blocks of data to be reclaimed for future usage and relocating all pages that are still valid therein. Moreover, depending on the specific controller and/or the respective garbage collection unit of operation, LEBs may be identified for being reclaimed and/or relocated. Typically, one LEB corresponds to one block stripe, but alternative implementations may consider a fixed number of block stripes building a LEB as well.

A physical “block” represents a minimal unit that may be erased on non-volatile memory, e.g., such as NAND Flash memory, and thereby prepared for writing data thereto. However, a typical garbage collection unit of operation is often a multiple of the physical blocks of non-volatile memory, and is also referred to herein as a LEB. This is due to the fact that typically RAID-like parity information is added in LEBs. Therefore, in case of a page or block failure data can only be rebuilt when all blocks in the LEB are still holding data. Accordingly, the individual blocks from the garbage collection unit can only be erased either individually or in a single unit once all still valid data from all blocks in the LEB has been relocated successfully to new locations. Hence, the full garbage collection units are garbage-collected as a single unit. Moreover, the size of the LEB directly affects the garbage collection induced write amplification. The larger the LEB, the more likely it becomes that unrelated data are stored together in the LEB, and therefore more of the LEB data may have to be relocated upon garbage collection selection.

Frequently, blocks from different dies and/or flash channels are grouped together, such that blocks from the same group can be read or written in parallel, thereby increasing overall bandwidth. It is also possible to combine the previous two methods, and to compose RAID stripes using blocks from different flash channels that can be accessed in parallel.

It should also be noted that an LEB may include any multiple of the physical memory block, which is a unit of physical erasure. Moreover, the organization of memory blocks into LEBs not only allows for adding RAID-like parity protection schemes among memory blocks from different memory chips, memory planes and/or channels but also allows for significantly enhancing performance through higher parallelism. For instance, multiple non-volatile memory blocks may be grouped together in a RAID stripe. As will be appreciated by one skilled in the art upon reading the present description, RAID schemes generally improve reliability and reduce the probability of data loss.

According to an exemplary embodiment, which is in no way intended to limit the invention, memory controllers (e.g., see108ofFIG. 1) may internally perform a garbage collection. As previously mentioned, the garbage collection may include selecting a LEB to be relocated, after which all data that is still valid on the selected LEB may be relocated (e.g., moved). After the still valid data has been relocated, the LEB may be erased and thereafter, used for storing new data. The amount of data relocated from the garbage collected LEB determines the write amplification. Moreover, an efficient way to reduce the write amplification includes implementing heat segregation.

Heat Segregation

In the present context, the “write heat” of data refers to the rate (e.g., frequency) at which the data is updated (e.g., rewritten with new data). Memory blocks that are considered “hot” tend to have a frequent updated rate, while memory blocks that are considered “cold” have an update rate slower than hot blocks.

Tracking the write heat of a logical page may involve, for instance, allocating a certain number of bits in the LPT mapping entry for the page to keep track of how many write operations the page has seen in a certain time period or window. Typically, host write operations increase the write heat whereas internal relocation writes decrease the write heat. The actual increments and/or decrements to the write heat may be deterministic or probabilistic.

Similarly, read heat may be tracked with a certain number of additional bits in the LPT for each logical page. To reduce meta-data, read heat can also be tracked at a physical block level where separate counters per block for straddling and non-straddling reads can be maintained. However, it should be noted that the number of read requests to and/or read operations performed on a memory block may not come into play for heat segregation when determining the heat of the memory block for some embodiments. For example, if data is frequently read from a particular memory block, the high read frequency does not necessarily mean that memory block will also have a high update rate. Rather, a high frequency of read operations performed on a given memory block may denote an importance, value, etc. of the data stored in the memory block.

By grouping memory blocks of the same and/or similar write heat values, heat segregation may be achieved. In particular, heat segregating methods may group hot memory pages together in certain memory blocks while cold memory pages are grouped together in separate memory blocks. Thus, a heat segregated LEB tends to be occupied by either hot or cold data.

The merit of heat segregation is two-fold. First, performing a garbage collection process on a hot memory block will prevent triggering the relocation of cold data as well. In the absence of heat segregation, updates to hot data, which are performed frequently, also results in the undesirable relocations of all cold data collocated on the same LEB as the hot data being relocated. Therefore, the write amplification incurred by performing garbage collection is much lower for embodiments implementing heat segregation.

Secondly, the relative heat of data can be utilized for wear leveling purposes. For example, hot data may be placed in healthier (e.g., younger) memory blocks, while cold data may be placed on less healthy (e.g., older) memory blocks relative to those healthier memory blocks. Thus, the rate at which relatively older blocks are exposed to wear is effectively slowed, thereby improving the overall endurance of a given data storage system implementing heat segregation.

Write Allocation

Write allocation includes placing data of write operations into free locations of open LEBs. As soon as all pages in a LEB have been written, the LEB is closed and placed in a pool holding occupied LEBs. Typically, LEBs in the occupied pool become eligible for garbage collection. The number of open LEBs is normally limited and any LEB being closed may be replaced, either immediately or after some delay, with a fresh LEB that is being opened.

During performance, garbage collection may take place concurrently with user write operations. For example, as a user (e.g., a host) writes data to a device, the device controller may continuously perform garbage collection on LEBs with invalid data to make space for the new incoming data pages. As mentioned above, the LEBs having the garbage collection being performed thereon will often have some pages that are still valid at the time of the garbage collection operation; thus, these pages are preferably relocated (e.g., written) to a new LEB.

Again, the foregoing functions are in no way intended to limit the capabilities of any of the storage systems described and/or suggested herein. Rather, the aforementioned functions are presented by way of example, and depending on the desired embodiment, logic of a storage system may be configured to perform additional or alternative functions, as would be appreciated by one skilled in the art upon reading the present description.

Referring now toFIG. 3, a system300is illustrated in accordance with one embodiment. As an option, the present system300may be implemented in conjunction with features from any other embodiment listed herein, such as those described with reference to the other FIGS. However, such system300and others presented herein may be used in various applications and/or in permutations which may or may not be specifically described in the illustrative embodiments listed herein. Further, the system300presented herein may be used in any desired environment, e.g., in combination with a controller.

As illustrated, system300includes a write cache302which is coupled to several other components, including garbage collector304. As previously mentioned, garbage collector304may be used to free LEB units by relocating valid data and providing non-volatile memory blocks to be erased for later reuse. Thus, the garbage collector304may reclaim blocks of consecutive physical space, depending on the desired embodiment. According to an exemplary embodiment, block erase units may be used to keep track of and/or complete the erase of non-volatile memory blocks handed over by the garbage collector304.

Write cache302is also coupled to free block manager306which may keep track of free non-volatile memory blocks after they have been erased. Moreover, as would be appreciated by one of ordinary skill in the art upon reading the present description, the free block manager306may build free stripes of non-volatile memory blocks from different lanes (e.g., block-stripes) using the erased free non-volatile memory blocks.

Referring still toFIG. 3, write cache302is coupled to LPT manager308and memory I/O unit310. The LPT manager308maintains the logical-to-physical mappings of logical addresses to physical pages in memory. According to an example, which is in no way intended to limit the invention, the LPT manager308may maintain the logical-to-physical mappings of 4 KiB logical addresses. The memory I/O unit310communicates with the memory chips in order to perform low level operations, e.g., such as reading one or more non-volatile memory pages, writing a non-volatile memory page, erasing a non-volatile memory block, etc.

To better understand the distinction between block-stripes and page-stripes as used herein,FIG. 4Ais a conceptual diagram400, in accordance with one embodiment. LEBs are built from block stripes and typically a single block stripe is used to build a LEB. However, alternative embodiments may use multiple block stripes to form an LEB. As an option, the present conceptual diagram400may be implemented in conjunction with features from any other embodiment listed herein, such as those described with reference to the other FIGS. However, such conceptual diagram400and others presented herein may be used in various applications and/or in permutations which may or may not be specifically described in the illustrative embodiments listed herein. Further, the controller conceptual diagram400presented herein may be used in any desired environment. Thus, the exemplary non-volatile memory controller conceptual diagram400ofFIG. 4Amay be implemented in a cache architecture. However, depending on the desired embodiment, the conceptual diagram400ofFIG. 4Amay be implemented in defining the organization of data stored in non-volatile memory. Accordingly, both implementations are described in turn below.

Looking now toFIG. 4A, the conceptual diagram400includes a set of M+1 aggregated planes labeled “Plane 0” through “Plane M”. An aggregated plane consists of all physical planes with the same plane index on different channels. It should be noted that aggregated planes are also referred to herein simply as planes.

When implemented with data stored in non-volatile memory, each physical plane on a channel may include a large set of blocks, e.g., typically in the order of 1024, 2048 or more. Moreover, one or more physical planes may also include several additional blocks which may be used as replacement blocks for bad blocks (e.g., blocks performing poorly, blocks having undesirable characteristics, etc.).

In each plane of non-volatile memory, a single block from each channel forms a respective block-stripe. It follows that a number of block-stripes supported by a given embodiment of non-volatile memory may be determined by the number of blocks per plane and the number of planes.

In the exploded view of Plane 0, the conceptual diagram400further illustrates a single block-stripe (Block-stripe 0) out of the set of block-stripes supported in the remainder of the planes. Block-stripe 0 of plane 0 is shown as including 11 blocks, one block from each channel labeled “Channel 0” through “Channel 10”. It should be noted that the association of blocks to block-stripe can change over time as block-stripes are typically dissolved after they have been garbage collected. Erased blocks may be placed in free block pools, whereby new block-stripes are assembled from blocks in the free block pools when write allocation requests fresh block-stripes. For example, looking to conceptual diagram400, Block 10 from Channel 0 and Block 41 from Channel 4 are currently associated with the illustrated Block-stripe 0 of Plane 0. Furthermore, the illustrated Block-stripe 0 holds N+1 page-stripes and each block therefore holds N+1 pages labeled “Page 0” through “Page N”.

Cache Architecture

Referring still toFIG. 4A, each block of pages illustrated in the exploded view of aggregated Plane 0 may constitute a unique block from one channel when implemented in a cache architecture. Similarly, each channel contributes a single, individual block which form a block-stripe. For example, looking to conceptual diagram400, Block 10 from Channel 0 includes all pages (Page 0 through Page N) therein, while Block 41 from Channel 4 corresponds to all pages therein, and so on.

In the context of a memory controller, e.g., which may be capable of implementing RAID at the channel level, a block-stripe is made up of multiple blocks which amount to a stripe of blocks. Looking still toFIG. 4A, the multiple blocks of aggregated Plane 0 constitute Block-stripe 0. While all blocks in a block-stripe typically belong to the same aggregated plane, in some embodiments one or more blocks of a block-stripe may belong to different physical planes. It follows that each aggregated plane may include one or more block-stripe. Thus, according to an illustrative embodiment, Block 0 through Block 10 from different physical planes may constitute a block-stripe.

Regardless of whether the conceptual diagram400ofFIG. 4Ais implemented with non-volatile memory and/or a cache architecture, in different embodiments, the number of pages in each block and/or the number of channels in each plane may vary depending on the desired embodiment. According to an exemplary embodiment, which is in no way intended to limit the invention, a block may include 1024 pages, but could include more or less in various embodiments. Analogously, the number of channels per plane and/or the number of planes may vary depending on the desired embodiment.

Referring still toFIG. 4A, all pages in a block-stripe with the same page index denote a page-stripe. For example, Page-stripe 0 includes the first page (Page 0) of each channel in Block-stripe 0 of Plane 0. Similarly, Page-stripe N includes the last page (Page N) of each channel in Block-stripe 0 of Plane 0.

The general storage architecture illustrated in the conceptual diagram400ofFIG. 4Ais also implemented by using 3-D memory structures in some approaches. For instance,FIG. 4Bdepicts a representational view of a 3-D non-volatile memory structure450, in accordance with one embodiment. As an option, the present structure450may be implemented in conjunction with features from any other embodiment listed herein, such as those described with reference to the other FIGS., such asFIG. 4A. However, such structure450and others presented herein may be used in various applications and/or in permutations which may or may not be specifically described in the illustrative embodiments listed herein. Further, the structure450presented herein may be used in any desired environment. ThusFIG. 4B(and the other FIGS.) may be deemed to include any possible permutation.

As shown, each layer452of the 3-D non-volatile memory structure450extends along both the x-axis and the y-axis. Each of these layers452include a plurality of storage components (not shown), such as voltage supply lines, sensor stacks, transistors, etc., which are used to implement the non-volatile memory devices of the general storage architecture illustrated in the conceptual diagram400ofFIG. 4A, e.g., as would be appreciated by one skilled in the art after reading the present description. Moreover, the various layers452are arranged in a stacked fashion along the z-axis in order to increase storage density and efficiency, e.g., by implementing shared wordlines. Cells from different bitlines along a wordline (typically in the x or y dimension ofFIG. 4B) are logically combined to form pages: In TLC, each wordline in a block contains 3 physical pages (i.e., a lower page, an upper page, and an extra page) and a wordline typically belongs to one particular layer in the z dimension (perpendicular to the x-y plane). For a particular block, which is formed from a grid of cells connected by wordlines and bitlines, the number of wordlines residing on the same layer is typically small. Therefore, a block can be formed from wordlines of all layers452. Moreover, wordlines as well as pages in the same block may reside on different layers452.

Again, due to cycling, retention, read disturb, program disturb, etc., or other mechanisms that may be specific to the NAND storage technology (e.g., floating gate or charge trap), process technology (e.g., 2-D or 3-D), scaling node, etc., or other specific design factors, the programmed threshold voltage distributions in memory may change with writing and erasing data (cycling), reading data (read disturb), time (retention), etc., in a slow or fast manner. In other words, bit error rates for Flash memory blocks increase with time and use. As memory blocks are used, each program/erase (P/E) cycle performed on the blocks causes damage, which in turn increases the corresponding bit error rate.

Moreover, although increases in bit error rates due to retention and/or read disturbances are not permanent in the sense that the memory blocks affected are not being irreversibly damaged, these unfavorable declines in performance are only remedied when the memory blocks are erased or re-calibrated. Thus, block calibration, also known as read voltage shifting, is an important aspect of enhancing endurance and retention for storage systems, e.g., particularly enterprise-level Flash systems. This block calibration corresponds to the read voltages and refers to algorithms that are able to track the changes of the threshold voltages. Moreover, adjustments to the read voltages are applied during a read command accordingly. It follows that the threshold voltage represents the voltage required to turn on the transistor of a given Flash memory cell and its value depends on the amount of charge stored during programming. However, the read voltage is a bias voltage, the value of which is typically between the threshold voltage of two adjacent logical states, e.g., as is explained in further detail below inFIG. 5.

Referring momentarily toFIG. 5, a graph500illustrating the threshold voltage shifting phenomenon is illustrated in accordance with an example. The x-axis of the graph500represents the programmed threshold voltage VTH, while the y-axis represents the corresponding cell count of a TLC NAND memory block. In TLC NAND, each memory cell stores 3 bits of information, therefore, the VTH distributions correspond to 8 possible discrete levels (E, L1, . . . , L7). The solid distributions502indicate the VTH levels after programming. The vertical solid lines504indicate the read voltages (rL1, . . . , rL7) that are optimal for the VTH distributions502. The dashed distributions506indicate a negative shift of the VTH levels due to charge loss over time. Because of this negative shift to lower voltages, the read voltages504are no longer optimal. Indeed, a negative offset must be applied to the read voltages in order to account for the changes of the VTH distributions from502to506. The vertical dashed lines508indicate the read voltages (rL1, . . . , rL7) that are optimal during retention for the VTH distributions in506. In general, each of the 8 levels (E, L1, . . . , L7) shown in the figure may have a different VTH shifts and thus, each of the 7 read voltages (rL1, . . . , rL7) may have a different optimal shift.

Accordingly, the read voltage shift values are preferably determined shortly after a block has been written to and/or periodically thereafter. The threshold voltage can be considered an index of the memory state, as determined by measuring the source-drain current when a control gate bias is applied to the memory cell. Typically, upon a read operation, a read voltage between adjacent nominal threshold voltages is used to determine the memory cell state. As the threshold voltage value of the memory cell changes (as explained above), the read voltage applied during a read operation is preferably shifted using a read voltage shift value to obtain optimal readout conditions and minimize bit error rates. Subsequently, the optimal read voltage shift values may be updated periodically, e.g., in a background health check.

Previous attempts to maintain efficient memory BER performance typically included inspecting the read voltages for each block of memory in a sweeping fashion or by a read voltage shifting algorithm that tracks and corrects the read voltages depending on how the threshold voltage distributions have changed as a result of cycling or retention or other disturbing effects. Moreover, upon identifying a block which was a calibration candidate, these previous attempts would perform block-level calibrations in which all pages in the identified block would be calibrated. It follows that these previous attempts involved inspecting each block in memory individually. Furthermore, although a block of memory is identified as being a candidate for calibration, typically not all pages in the block benefit from the calibration. Accordingly, these previous attempts suffered from significant inefficiencies not only in the process of identifying portions of memory which were in need of calibration, but also in performing the calibration process itself, as numerous pages would often be unnecessarily calibrated. Moreover, in modern 3-D TLC and QLC NAND flash, the number of pages in a block and the number of blocks in a package have been substantially increased with respect to previous generation 2-D NAND Flash. As a result, it may take longer before a particular page or block is inspected during the regular background process. Accordingly, these previous attempts suffered from high RBER triggering events of higher probability due to the longer times before the corresponding pages or blocks are inspected.

These inefficiencies were realized mainly as a result of a discovery made regarding a bit error rate correlation which exists between various pages in memory. For instance, referring momentarily toFIG. 6, a graph600which illustrates the bit error rate for various pages in a 3D TLC block is illustrated in accordance with an exemplary embodiment, which is in no way intended to limit the invention. As shown, multiple levels of bit error rate correlation exist across different pages in the memory block. For instance, the lower pages have in general lower BER than the upper pages which have in general lower BER than the extra pages. It follows that pages of different types, but which are in the same block of memory have different bit error rate characteristics. Moreover, pages of the same type and in the same layer have similar bit error rate characteristics. Further, there exist pages of the same type in adjacent layers that have similar characteristics, e.g., the pages of same type in layers “m” and “m+1” or in layers “k” and “k+1”. However, there also exists layers where the pages of the same type have different bit error rate characteristics, e.g., the pages of same type in layers “m” and “k”.

It follows that these various correlations between the bit error rate characteristics of different portions of memory are utilized in some of the embodiments presented herein. For instance, by establishing a process which applies the different levels of bit error rate correlation to the calibration process, the calibration of a particular page group can also trigger the calibration of specific portions of memory which are correlated thereto. Thus, a number of the embodiments included herein are able to increase the efficiency by which memory is maintained, particularly with respect to the threshold voltage shift phenomenon, e.g., as will be described in further detail below.

Referring now toFIG. 7A, a flowchart of a method700is shown according to one embodiment. The method700may be performed in accordance with the present invention in any of the environments depicted inFIGS. 1-6, among others, in various embodiments. Of course, more or less operations than those specifically described inFIG. 7Amay be included in method700, as would be understood by one of skill in the art upon reading the present descriptions.

Each of the steps of the method700may be performed by any suitable component of the operating environment. For example, in various embodiments, the method700may be partially or entirely performed by a controller, a processor, a computer, etc., or some other device having one or more processors therein. Thus, in some embodiments, method700may be a computer-implemented method. It should also be noted that the terms computer, processor and controller may be used interchangeably with regards to any of the embodiments herein, such components being considered equivalents in the many various permutations of the present invention.

As shown inFIG. 7A, operation702of method700includes performing a read scrub operation which monitors the status of the various pages in non-volatile memory by reading the given page and measuring the resulting bit error rate. The read scrub operation is preferably performed in the background such that it does not hinder the performance of ongoing data access and/or modification operations. Moreover, in some approaches the read scrub operation inspects the threshold voltage of each page or block in a sequential manner, an interleaved manner, or any other manner depending on how often or how fast the pages, the page groups, or the blocks benefit from inspection. Upon inspecting all portions of memory, the read scrub operation returns to inspect each of the portions of memory again in a repeating, cyclical manner such that a status of the memory is continuously being evaluated.

While the general progression of the read scrub operation is similar to that implemented in the aforementioned previous attempts, the manner by which the memory is calibrated as a result of detecting a portion of memory due for calibration differs significantly from the previous shortcomings, e.g., as will soon become apparent. Moreover, these improvements are achievable for various types of memory, including but not limited to two-dimensional (2-D) or 3-D NAND Flash memory (e.g., as seen inFIG. 4B), non-volatile memory implementing TLCs, non-volatile memory implementing quad-level cells (QLCs), etc.

Operation704includes detecting that a calibration of a first page group has been triggered. In other words, operation704includes detecting a first page group that is due for calibration. With respect to the present description, a “page group” is intended to refer to a grouping of one or more pages in non-volatile memory (e.g., NAND Flash) for which a bit error rate correlation exists therebetween. Thus, each of the pages included in a given page group have the same or substantially similar bit error rate characteristics over a given amount of time, use, etc., and therefore will also have the same or substantially similar read voltages. The pages which are included in a given page group may belong to the same to the same layer in a 3-D NAND Flash. In principle, the pages in the same group belong to the same block, however other approaches of grouping pages that belong to different blocks can be envisioned without deviating from the scope of the current application. Again, multiple levels of bit error rate correlation exist across different page types and different blocks of memory, e.g., as described with respect toFIG. 6above.

In some approaches, the calibration of a given page group is triggered by a bit error rate of the given page group. For instance, determining that the bit error rate of a page group is too high may indicate that a threshold voltage distribution change has occurred. Thus, the detection in operation704may be made in response to measuring the number of errors incurred by reading any or a subset or all pages of the page group. It follows that the detection is made in response to performing a probe (e.g., test) read operation which attempts to determine whether the threshold voltage has deviated from an anticipated value by means of the returned bit error count.

Furthermore, decision706includes determining whether the first page group correlates to one or more other page groups in non-volatile memory by evaluating a hierarchical page group mapping. As described above, multiple levels of bit error rate correlation exist across different page types and different blocks of memory. For instance, pages that are in adjacent (e.g., neighboring) wordlines and/or which are of the same type (e.g., lower page, extra page, upper page, top page, etc.) will generally have similar characteristics which are different than the characteristics of other pages in different wordlines and/or which are of a different type. Thus, the hierarchical mapping is based on the principle that a bit error rate correlation exists between particular levels of memory which extends between pages, page groups, super-groups, layers, blocks, etc.

These correlations are thereby used in preferred approaches to develop a hierarchical page group mapping which identifies functional relationships between various portions of memory. Moreover, these relationships serve as valuable information in maintaining efficient BER performance of the memory as a whole, e.g., as would be appreciated by one skilled in the art after reading the present description. Accordingly, the page groups having a bit error rate correlation with a page group designated for calibration are referred to herein as a “super-group of page groups”. Said another way, a super-group of page groups includes those page groups having a bit error rate correlation with a page group designated for calibration. Similarly, a given page group may have a bit error rate correlation with a super-group of layers, a super-group of blocks, etc. Also note that a super-group of page groups may include a part of a block, or an entire block depending on the approach.

However, the relationships represented in a hierarchical page group mapping are developed using other criteria and/or dependencies in some approaches. For example, apart from correlations based on similar BER characteristics, hierarchical mappings may be based on super groups of pages which are defined based on having similar cycling history, retention history, etc.

Furthermore, in some approaches the hierarchical page group mapping is static in the sense that relationships which exist between page groups and/or the specific pages included therein remain constant over time and throughout use. In such approaches, the hierarchical page group mapping may be based on a bit error rate correlation which exists between the pages in the non-volatile memory as determined using characteristic data of the non-volatile memory gathered during manufacture of the non-volatile memory and/or the product testing phase before being released for actual use.

However, the bit error rate correlation which exists between the pages in the non-volatile memory may change over time and with use. For example, different ones of the pages in a given page group can experience varied write cycles and therefore different wear rates. Accordingly, in other approaches the hierarchical page group mapping is updated over time (e.g., during actual use) based on such changes to the bit error rate correlation between the page groups in the non-volatile memory and/or the specific pages included therein. These updates to the hierarchical page group mapping may be performed periodically, in response to receiving a user request to do so, in response to a predetermined condition being met, etc.

With continued reference toFIG. 7A, method700proceeds to decision708in response to determining that the first page group does correlate to one or more other page groups in the non-volatile memory. There, decision708includes determining whether to promote at least one of the one or more other page groups for calibration. The determination made in decision708depends on various factors in different approaches. For instance, in some approaches the determination made in decision708is based on a bit error rate of the first page group detected in operation704. Referring momentarily toFIG. 7B, exemplary sub-processes of determining whether to promote at least one of the one or more other page groups for calibration are illustrated in accordance with one embodiment, one or more of which may be used to perform decision708ofFIG. 7A. However, it should be noted that the sub-processes ofFIG. 7Bare illustrated in accordance with one embodiment which is in no way intended to limit the invention.

As shown, the flowchart includes determining whether a bit error rate of the first page group is above a threshold. See decision750. Determining that the bit error rate for a given page group is sufficiently high (undesirable) is a good indicator that page groups having bit error rate correlations with the given page group also have undesirably high bit error rates. Thus, the bit error rate of a given page group allows for other portions of memory which would greatly benefit from a calibration operation to be identified.

Depending on the approach, the threshold may be predetermined, set by a user, calculated based on current conditions and/or memory performance, etc. Moreover, it should be noted that “above a threshold” is in no way intended to limit the invention. Rather than determining whether a value is above a threshold, equivalent determinations may be made, e.g., as to whether a value is within a predetermined range, whether a value is outside a predetermined range, whether an absolute value is above a threshold, whether a value is below a threshold, etc., depending on the desired approach.

With continued reference toFIG. 7B, the flowchart proceeds to sub-operation752in response to determining that the bit error rate of the first page group is above the threshold. There, sub-operation752includes promoting at least one of the one or more other page groups for calibration. A number of the one or more other page groups which are promoted for calibration is based at least in part on the bit error rate of the first page group in some approaches. As alluded to above, the bit error rate of the first page group serves as an indicator on how each of the page groups correlated thereto are performing as well, e.g., at least to some extent. Thus, situations in which the first page group has a higher bit error rate results in a greater number of page groups being promoted for calibration, at least with respect to situations in which the first page group has a relatively lower bit error rate.

From sub-operation752, the flowchart returns to operation710ofFIG. 7A. However, returning to decision750, the flowchart proceeds to operation712ofFIG. 7Ain response to determining that the bit error rate of the first page group is not above the threshold, e.g., as will be described in further detail below.

Again, the determination made in decision708ofFIG. 7Adepends on various factors in different approaches. For instance, in other approaches the determination made in decision708is based on the results of performing probe read operations. Referring momentarily toFIG. 7C, exemplary sub-processes of determining whether to promote at least one of the one or more other page groups for calibration are illustrated in accordance with one embodiment, one or more of which may be used to perform decision708ofFIG. 7A. However, it should be noted that the sub-processes ofFIG. 7Care illustrated in accordance with one embodiment which is in no way intended to limit the invention.

As shown, the flowchart includes performing a probe read on each of the one or more other page groups which are candidates of being promoted for calibration. See sub-operation760. A probe read performed on a given page group allows for the one or more pages included therein to be tested in terms of read performance with respect to the given threshold voltage used thereby. In other words, operation760allows for each of the candidate page groups to be evaluated before actually performing a calibration thereof, thereby conserving system resources and focusing management efforts on portions of memory which would actually benefit therefrom.

Furthermore, decision762includes determining whether a bit error rate resulting from each of the probe reads performed is above a threshold. In some approaches, this threshold may be the same as that use in decision750ofFIG. 7B. However, in other approaches, this threshold may vary depending on the particular page group being evaluated, user preference, a level of correlation with the page group which originally triggered the calibration process in operation704, etc.

The flowchart further proceeds to sub-operation764for each of the page groups determined as having a bit error rate (resulting from the respective probe read) which is above the threshold. There, sub-operation764includes promoting each of the one or more other page groups having a bit error rate resulting from the respective probe read which is above the threshold. In other words, sub-operation764includes selecting certain page groups having sufficiently high bit error rates for calibration. Accordingly, the page groups which are promoted may be added to a calibration queue, marked for calibration (e.g., using a special flag), etc., depending on the approach.

From sub-operation764, the flowchart returns to operation710ofFIG. 7A. However, returning to decision762, the flowchart proceeds to operation712ofFIG. 7Ain response to determining that none of the bit error rates resulting from the probe reads performed are above a threshold, e.g., as will be described in further detail below.

Again, the flowchart ofFIG. 7Cis preferably performed for each page included in the page group being evaluated for calibration. Accordingly, in preferred approaches the sub-processes included therein are repeated in an iterative fashion for each of the pages included in a page group. Another approach is to randomly select one page or a subset of pages of the page group and measure the bit error rate for only that page or the subset of pages. This approach reduces the amount of probe reads.

Returning now toFIG. 7A, method700proceeds to operation710from decision708in response to determining to promote at least one of the one or more other page groups for calibration, e.g., as shown. There, operation710includes calibrating the first page group as well as the at least one of the one or more other page groups. In other words, operation710includes calibrating the page group which was originally detected in operation704as well as each of the additional page groups identified and promoted as a result of performing decision708and the various sub-processes included therein. As mentioned above, the number of the one or more other page groups which are ultimately promoted for calibration along with the originally detected page group is based at least in part on the bit error rate of the first page group in some approaches. Thus, the total number of page groups calibrated in operation710corresponds to on the bit error rate of the initial page group in some approaches.

Returning to decision706, method700proceeds to operation712in response to determining that the first page group does not correlate to any other page groups in non-volatile memory. As mentioned above, this determination is made by evaluating a hierarchical page group mapping. Similarly, method700proceeds from decision708to operation712in response to determining to not promote any of the one or more other page groups for calibration. Looking back toFIGS. 7B-7C, this determination is made based on results of probe read operations, bit error rates, etc., depending on the approach.

Referring again toFIG. 7A, operation712includes calibrating the first page group. In other words, only the page group which was originally detected in operation704is calibrated in operation712. Moreover, method700progresses from operation712as well as operation710to operation714, whereby method700ends. However, it should be noted that although method700ends upon reaching operation714in some approaches, any one or more of the processes included in method700may be repeated in order to process additional page groups identified as being due from a calibration.

Accordingly, the various processes included in method700are able to evaluate the various pages in non-volatile memory and perform calibration operations on certain ones thereof in a manner which is more efficiently than previously achievable. For instance, by maintaining a hierarchical page group mapping, multiple page groups which have similar bit error rate characteristics can be identified and calibrated together when desirable. As a result, numerous pages which span across various layers, blocks, etc. of the memory can be identified and calibrated without having to systematically search for each of the pages individually as performed in previous attempts. Moreover, the granularity by which these calibrations are performed is much finer than previously achievable. Thus, unnecessary calibrations are avoided and system resources such as processing power, computational throughput, etc. are preserved. It follows that various ones of the approaches included herein are able to achieve a level of efficiency in the management and performance of memory which is orders of magnitude greater than achievable by conventional products.

While the approaches included in method700generally evaluated whether to promote additional page groups prior to performing any calibration operations, determinations as to whether to promote additional page groups may be made following an initial calibration operation in other approaches. For example, referring now toFIG. 8, another method800is illustrated in accordance with one embodiment. It should also be noted that various ones of the processes included in method800are similar to those presented above in method700. Accordingly, any of the approaches presented above with respect toFIGS. 7A-7Cmay be implemented in conjunction withFIG. 8, e.g., as would be appreciated by one skilled in the art after reading the present description. Moreover, the method800may be performed in accordance with the present invention in any of the environments depicted inFIGS. 1-6, among others, in various embodiments. Of course, more or less operations than those specifically described inFIG. 8may be included in method800, as would be understood by one of skill in the art upon reading the present descriptions.

Each of the steps of the method800may be performed by any suitable component of the operating environment. For example, in various embodiments, the method800may be partially or entirely performed by a controller, a processor, a computer, etc., or some other device having one or more processors therein. Thus, in some embodiments, method800may be a computer-implemented method. It should also be noted that the terms computer, processor and controller may be used interchangeably with regards to any of the embodiments herein, such components being considered equivalents in the many various permutations of the present invention.

As shown inFIG. 8, operation802of method800includes performing a read scrub operation which monitors the status of the various pages in non-volatile memory by reading the given page and measuring the resulting bit error rate. Moreover, operation804includes detecting that a bit error count of a first page group has triggered a calibration of the first page group. As mentioned above, the bit error rate of a given page group triggers a calibration of that page group in response to exceeding a threshold in some approaches. By exceeding the threshold, the bit error rate provides an indication that the read voltage for the corresponding pages is no longer accurate and thereby causing an increased number of errors in accessing data stored in the memory.

Proceeding to operation806, here method800includes calibrating the first page group. The process of calibrating the first page group may implement any of the approaches described herein. Moreover, other calibration processes which would be apparent to one skilled in the art after reading the present description can be implemented, e.g., depending on the desired approach.

Decision808further includes determining whether an updated bit error count of the calibrated first page group is above a threshold. As described above, calibrating a given page of memory involves determining how much the threshold voltage thereof has shifted, and adjusting read settings accordingly. Thus, the bit error rate for a given page after being calibrated is typically lower than the bit error rate prior to the calibration. However, it is desirable in some approaches to inspect the updated bit error count of a page group after being calibrated, e.g., to ensure the calibration operation was performed successfully and that desirable read performance will be achieved moving forward. It should also be noted that “above a threshold” is again in no way intended to limit the invention. Rather than determining whether a value is above a threshold, equivalent determinations may be made, e.g., as to whether a value is within a predetermined range, whether a value is outside a predetermined range, whether an absolute value is above a threshold, whether a value is below a threshold, etc., depending on the desired approach.

In response to determining that the updated bit error count of the calibrated first page group exceeds the threshold, method800proceeds to decision810. There, decision810includes determining whether the first page group correlates to one or more other page groups in non-volatile memory by evaluating a hierarchical page group mapping. Again, determining that the bit error rate for a given page group is sufficiently high (undesirable) is a good indicator that page groups having bit error rate correlations with the given page group also have undesirably high bit error rates. Thus, the bit error rate of a given page group allows for other portions of memory which would greatly benefit from a calibration operation to be identified.

Again, multiple levels of bit error rate correlation exist across different page types and different blocks of memory. For instance, pages that are in adjacent (e.g., neighboring) wordlines and/or which are of the same type (e.g., lower page, extra page, etc.) will generally have similar characteristics which are different than the characteristics of other pages in different wordlines and/or which are of a different type. Thus, the hierarchical mapping is based on the principle that a bit error rate correlation exists between particular levels of memory which extends between pages, page groups, super-groups, layers, blocks, etc.

As previously mentioned, these correlations are thereby used in preferred approaches to develop a hierarchical page group mapping which identifies functional relationships between various portions of memory. These relationships also serve as valuable information in maintaining efficient BER performance of the memory as a whole, e.g., as would be appreciated by one skilled in the art after reading the present description. In some approaches the hierarchical page group mapping is static in the sense that relationships which exist between page groups and/or the specific pages included therein remain constant over time and throughout use, e.g., according to any of the approaches included herein. However, in other approaches the hierarchical page group mapping is updated over time (e.g., during actual use) based on such changes to the bit error rate correlation between the page groups in the non-volatile memory and/or the specific pages included therein, e.g., according to any of the approaches included herein.

In response to determining that the first page group does correlate to one or more other page groups in the non-volatile memory, operation812is performed which includes calibrating at least one of the one or more other page groups. As mentioned above, a number of the one or more other page groups which are calibrated is based at least in part on the bit error rate and/or the updated bit error rate of the first page group with respect to the thresholds, respectively.

The flowchart proceeds from operation812to operation814, whereby method800may end. Method800is also shown as progressing to operation814from decision808in response to determining that an updated bit error count of the calibrated first page group is not above a threshold. Similarly, method800proceeds directly to operation814from decision810in response to determining that the first page group does not correlate to any other page groups in non-volatile memory. However, it should be noted that although method800may end upon reaching operation814, any one or more of the processes included in method800may be repeated in order to process additional page groups identified as being due from a calibration.

Again, the various processes included in method800are able to evaluate the various pages in non-volatile memory and perform calibration operations on certain ones thereof in a manner which is more efficiently than previously achievable. For instance, by maintaining a hierarchical page group mapping, multiple page groups which have similar bit error rate characteristics can be identified and calibrated together when desirable, despite the fact that the various page groups may be located across different layers, blocks, etc. of the memory. As a result, numerous pages which span across the memory can be identified and calibrated without having to systematically search for each of the pages individually as performed in previous attempts. Moreover, the granularity by which these calibrations are performed is much finer than previously achievable. Thus, unnecessary calibrations are avoided and system resources such as processing power, computational throughput, etc. are preserved. It follows that various ones of the approaches included herein are able to achieve a level of efficiency in the management and performance of memory which is orders of magnitude greater than achievable by conventional products.

According to an in-use example of a 3-D TLC NAND Flash, which is in no way intended to limit the invention, assume page group “j” with an upper page in layer “k” of block “b” triggers a calibration. Because the bit error rate of an upper page is typically less than the bit error rate of an extra page, it is likely that page group “i” of block “b” having the shared extra pages would also benefit from a calibration. Moreover, because page groups “i” and “j” both belong to layer “k”, it is likely that the same type of groups (e.g., those having upper pages and those having extra pages) in the adjacent layers “k−1”, “k+1” of block “b” would benefit from a calibration operation also. Further still, the approaches included herein are able to determine that because page group “j” in block “b” triggered the calibration in the first place, it is likely that blocks “b+1” and “b+2” (e.g., which were written together with block “b” and have seen the same number and/or frequency of program erase cycles and/or read cycles) would benefit from a calibration operation as well.

It follows that, given the different levels of bit error rate correlation, the approaches included herein establish a process which, depending on whether a particular page group triggers calibration, promotes one or more page groups, one or more layers, one or more blocks, etc., for calibration. In other words, portions of memory are queued for calibration given a hierarchical mapping between the triggering page group and the other page groups, layers, blocks, etc. Also note that the page groups may include a part of a block, or an entire block depending on the approach.

Looking now toFIG. 9, a representational view of non-volatile memory900is illustrated in accordance with another in-use example of a 3-D TLC NAND Flash, which again is in no way intended to limit the invention. In the present example, the act of reading page “i+6” triggers a calibration of the page and of page group “x”, shown as PG(X), that page “i+6” belongs to. According to a hierarchical page group mapping, a dependency exists between page “i+6” and page groups “x”, “x+1”, and “x+2”. More specifically, page group “x” contains, in this example, four pages of the same type, i.e., lower pages (LP), that belong to four adjacent word lines, i.e., “j”, “j+1”, “j+2, “j+3, and pages groups “x+1” and “x+2” contain the corresponding shared upper pages (UP) and extra pages (XP), respectively. Accordingly, page groups “x”, “x+1”, and “x+2” may be considered as being a super-group of page groups which are correlated to page “i+6”. It follows that page “i+6” as well as page groups “x”, “x+1”, and “x+2” are each calibrated as a result of the identified bit error rate correlation which exists therebetween.

While the super-group of page groups is located on a same layer as page “i+6” in the present approach, the page groups in a given super-group is located on different layers in other approaches. For instance, reading page “i+11” also triggers a calibration of the page and of page group “x+2”, shown as PG(X+2), that page “i+11” belongs to. The hierarchical page group mapping identifies that a bit error rate correlation exists between page “i+11” and page groups “x−1”, and “x+2”. Accordingly, page groups “x−1”, and “x+2” may be considered as being a super-group of page groups which are located on adjacent layers in memory, but which are also correlated to page “i+11”. Accordingly, multiple levels of bit error rate correlation exist across the different page types (e.g., lower page, upper page, extra page, top page, etc.).

The approaches included herein focus on the calibration (e.g., normal or snap) on a page group basis while proactively promote page groups for calibration that have similar characteristics and use history (e.g., cycling, retention, etc.) with the page group that triggered calibration.

FIG. 10illustrates a network architecture1000, in accordance with one embodiment. As shown inFIG. 10, a plurality of remote networks1002are provided including a first remote network1004and a second remote network1006. A gateway1001may be coupled between the remote networks1002and a proximate network1008. In the context of the present network architecture1000, the networks1004,1006may each take any form including, but not limited to a LAN, a WAN such as the Internet, public switched telephone network (PSTN), internal telephone network, etc.

In use, the gateway1001serves as an entrance point from the remote networks1002to the proximate network1008. As such, the gateway1001may function as a router, which is capable of directing a given packet of data that arrives at the gateway1001, and a switch, which furnishes the actual path in and out of the gateway1001for a given packet.

Further included is at least one data server1014coupled to the proximate network1008, and which is accessible from the remote networks1002via the gateway1001. It should be noted that the data server(s)1014may include any type of computing device/groupware. Coupled to each data server1014is a plurality of user devices1016. Such user devices1016may include a desktop computer, laptop computer, handheld computer, printer, and/or any other type of logic-containing device. It should be noted that a user device1011may also be directly coupled to any of the networks, in some embodiments.

A peripheral1020or series of peripherals1020, e.g., facsimile machines, printers, scanners, hard disk drives, networked and/or local data storage units or systems, etc., may be coupled to one or more of the networks1004,1006,1008. It should be noted that databases and/or additional components may be utilized with, or integrated into, any type of network element coupled to the networks1004,1006,1008. In the context of the present description, a network element may refer to any component of a network.

According to some embodiments, methods and systems described herein may be implemented with and/or on virtual systems and/or systems which emulate one or more other systems, such as a UNIX system which virtually hosts a MICROSOFT WINDOWS environment, etc. This virtualization and/or emulation may be enhanced through the use of VMWARE software, in some embodiments.

FIG. 11shows a representative hardware environment associated with a user device1016and/or server1014ofFIG. 10, in accordance with one embodiment.FIG. 11illustrates a typical hardware configuration of a processor system1100having a central processing unit1110, such as a microprocessor, and a number of other units interconnected via a system bus1112, according to one embodiment. In some embodiments, central processing unit1110may include any of the approaches described above with reference to the one or more processors210ofFIG. 2.

The processor system1100shown inFIG. 11includes a Random Access Memory (RAM)1114, Read Only Memory (ROM)1116, and an I/O adapter1118. According to some embodiments, which are in no way intended to limit the invention, I/O adapter1118may include any of the approaches described above with reference to I/O adapter218ofFIG. 2. Referring still to processor system1100ofFIG. 11, the aforementioned components1114,1116,1118may be used for connecting peripheral devices such as storage subsystem1120to the bus1112. In some embodiments, storage subsystem1120may include a similar and/or the same configuration as data storage system220ofFIG. 2. According to an example, which is in no way intended to limit the invention, storage subsystem1120may include non-volatile data storage cards, e.g., having NVRAM memory cards, RAM, ROM, and/or some other known type of non-volatile memory, in addition to RAID controllers as illustrated inFIG. 2.

With continued reference toFIG. 11, a user interface adapter1122for connecting a keyboard1124, a mouse1126, a speaker1128, a microphone1132, and/or other user interface devices such as a touch screen, a digital camera (not shown), etc., to the bus1112.

Processor system1100further includes a communication adapter1134which connects the processor system1100to a communication network1135(e.g., a data processing network) and a display adapter1136which connects the bus1112to a display device1138.

Moreover,FIG. 12illustrates a storage system1200which implements high level (e.g., SSD) storage tiers in combination with lower level (e.g., magnetic tape) storage tiers, according to one embodiment. Note that some of the elements shown inFIG. 12may be implemented as hardware and/or software, according to various embodiments. The storage system1200may include a storage system manager1212for communicating with a plurality of media on at least one higher storage tier1202and at least one lower storage tier1206. However, in other approaches, a storage system manager1212may communicate with a plurality of media on at least one higher storage tier1202, but no lower storage tier. The higher storage tier(s)1202preferably may include one or more random access and/or direct access media1204, such as hard disks, nonvolatile memory (NVM), NVRAM), solid state memory in SSDs, flash memory, SSD arrays, flash memory arrays, etc., and/or others noted herein or known in the art. According to illustrative examples,FIGS. 3-4show exemplary architectures of SSD systems which may be used as a higher storage tier1202depending on the desired embodiment.

Referring still toFIG. 12, the lower storage tier(s)1206preferably includes one or more lower performing storage media1208, including sequential access media such as magnetic tape in tape drives and/or optical media, slower accessing HDDs, slower accessing SSDs, etc., and/or others noted herein or known in the art. One or more additional storage tiers1216may include any combination of storage memory media as desired by a designer of the system1200. Thus, the one or more additional storage tiers1216may, in some approaches, include a SSD system architecture similar or the same as those illustrated inFIGS. 1-2. Also, any of the higher storage tiers1202and/or the lower storage tiers1206may include any combination of storage devices and/or storage media.

The storage system manager1212may communicate with the storage media1204,1208on the higher storage tier(s)1202and lower storage tier(s)1206through a network1210, such as a storage area network (SAN), as shown inFIG. 12, or some other suitable network type. The storage system manager1212may also communicate with one or more host systems (not shown) through a host interface1214, which may or may not be a part of the storage system manager1212. The storage system manager1212and/or any other component of the storage system1200may be implemented in hardware and/or software, and may make use of a processor (not shown) for executing commands of a type known in the art, such as a central processing unit (CPU), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc. Of course, any arrangement of a storage system may be used, as will be apparent to those of skill in the art upon reading the present description.

In more embodiments, the storage system1200may include any number of data storage tiers, and may include the same or different storage memory media within each storage tier. For example, each data storage tier may include the same type of storage memory media, such as HDDs, SSDs, sequential access media (tape in tape drives, optical disk in optical disk drives, etc.), direct access media (CD-ROM, DVD-ROM, etc.), or any combination of media storage types. In one such configuration, a higher storage tier1202, may include a majority of SSD storage media for storing data in a higher performing storage environment, and remaining storage tiers, including lower storage tier1206and additional storage tiers1216may include any combination of SSDs, HDDs, tape drives, etc., for storing data in a lower performing storage environment. In this way, more frequently accessed data, data having a higher priority, data needing to be accessed more quickly, etc., may be stored to the higher storage tier1202, while data not having one of these attributes may be stored to the additional storage tiers1216, including lower storage tier1206. Of course, one of skill in the art, upon reading the present descriptions, may devise many other combinations of storage media types to implement into different storage schemes, according to the embodiments presented herein.

According to some embodiments, the storage system (such as1200) may include logic configured to receive a request to open a data set, logic configured to determine if the requested data set is stored to a lower storage tier1206of a tiered data storage system1200in multiple associated portions, logic configured to move each associated portion of the requested data set to a higher storage tier1202of the tiered data storage system1200, and logic configured to assemble the requested data set on the higher storage tier1202of the tiered data storage system1200from the associated portions.