METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR STRUCTURE

A method of manufacturing a semiconductor structure and a semiconductor structure are disclosed. The method of manufacturing a semiconductor structure includes: providing a substrate; forming a multilayer film stack on the substrate; forming a supporter at a top of the multilayer film stack; and etching the multilayer film stack to form a plurality of gate structures arranged at intervals along a first direction, where the supporter penetrates a top of each of the plurality of gate structures and extends along the first direction.

TECHNICAL FIELD

The present disclosure relates to, but is not limited to, a method of manufacturing a semiconductor structure and a semiconductor structure.

BACKGROUND

With the advancement of technology, dynamic random access memory (DRAM) is developing in the direction of high speed, high integration density and low power consumption. The structure size of the DRAM device is getting smaller. Especially, in the process of manufacturing semiconductor devices with a low line width, the material, shape, size and electrical properties of a gate structure need to meet higher requirements.

The current manufacturing process usually requires multiple wet cleaning processes to obtain the required gate structure, and the gate structure is prone to peeling during the cleaning process, which affects the electrical properties of the gate structure.

SUMMARY

A first aspect of the present disclosure provides a method of manufacturing a semiconductor structure. The method of manufacturing a semiconductor structure includes:providing a substrate;forming a multilayer film stack on the substrate;forming a supporter at a top of the multilayer film stack; andetching the multilayer film stack to form a plurality of gate structures arranged at intervals along a first direction, the supporter penetrating a top of each of the plurality of gate structures and extending along the first direction.

A second aspect of the present disclosure provides a semiconductor structure, where the semiconductor structure includes:a substrate;a plurality of gate structures, located on the substrate and arranged at intervals along a first direction; anda supporter, penetrating a top of each of the plurality of gate structures and extending along the first direction.

DETAILED DESCRIPTION

To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the following clearly and completely describes the technical solutions in the embodiments of the present disclosure with reference to the accompanying drawings in the embodiments of the present disclosure. Apparently, the described embodiments are some but not all of the embodiments of the present disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of the present disclosure without creative efforts should fall within the protection scope of the present disclosure. It should be noted that the embodiments in the present disclosure and features in the embodiments may be combined with each other in a non-conflicting manner.

As the dynamic random access memory (DRAM) develops in the direction of high speed, high integration density and low power consumption, the structure size of the DRAM device is getting smaller. Especially, in the process of manufacturing semiconductor devices with a low line width, the material, shape, size and electrical properties of a gate structure need to meet higher requirements.

FIG.1shows a semiconductor structure in the related art. The semiconductor structure includes a substrate1and a plurality of gate structures2arranged on the substrate1. The current manufacturing process usually requires multiple wet cleaning processes to obtain the required gate structure2. During the cleaning process, due to the small critical dimension of the gate structure2and the large height of the gate structure2(vertically upward perpendicular to the substrate), the gate structure2is peeled off from the substrate1after repeated cleaning, which affects the electrical performance of the gate structure2.

An exemplary embodiment of the present disclosure provides a method of manufacturing a semiconductor structure.FIG.2is a flowchart of a method of manufacturing a semiconductor structure according to an exemplary embodiment of the present disclosure.FIG.3toFIG.13are schematic diagrams of the method of manufacturing a semiconductor structure at various stages. The method of manufacturing a semiconductor structure is described below with reference toFIG.3toFIG.13.

The semiconductor structure is not limited in this embodiment. The semiconductor structure is described below by using a DRAM as an example, but this embodiment is not limited thereto. Alternatively, the semiconductor structure in this embodiment may further be another structure.

As shown inFIG.2, an exemplary embodiment of the present disclosure provides a method of manufacturing a semiconductor structure. The method includes the following steps:

Step S100: Provide a substrate.

As shown inFIG.3, a material of the substrate1may be silica (Si), germanium (Ge), silicon-germanium (GeSi), or silicon carbide (SiC); or may be silicon on insulator (SOI) or germanium on insulator (GOI); or may further be another material, for example, a III-V compound such as gallium arsenide. The substrate1is configured to support elements provided thereon.

The substrate1may be doped with certain impurity ions as required, and the impurity ions may be N-type impurity ions or P-type impurity ions. In some embodiments, the doping includes well region doping and source drain region doping. In this embodiment, a plurality of transistors may be formed in the substrate1. If the plurality of transistors are used as a part of the DRAM memory, specifically, as shown inFIG.3, a plurality of active areas11arranged at intervals are provided in the substrate1, and adjacent active areas11are isolated from each other by a shallow trench isolation region12. The active area11includes a channel region, and a source region and a drain region that are located on two sides of the channel region. The source region and the drain region are formed by a source drain doping process.

Step S200: Form a multilayer film stack on the substrate.

In this example, as shown inFIG.3, a multilayer film stack2′ may be formed on the substrate1through a deposition process, such as atomic layer deposition (ALD) or chemical vapor deposition (CVD). In this embodiment, the multilayer film stack2′ may be configured to form the gate structures2in post-processing.

In some embodiments, before the multilayer film stack2′ is formed, wet cleaning is performed on the substrate1, thereby removing impurities on the surface of the substrate1, to provide good interface performance and process foundation for subsequent processes, thus helping improve the quality of the semiconductor structure.

Step S300: Form a supporter at a top of the multilayer film stack.

In this step, referring toFIG.9, the supporter3may be formed on the multilayer film stack2′ through a deposition process. The deposition process has been explained, and details are not described herein again. This embodiment shows a semiconductor structure provided with two supporters3. It is to be understood that, only one supporter3may be provided, and the one supporter3extends along the first direction (direction X shown inFIG.9). More supporters3may be provided, where the plurality of supporters3are arranged along a second direction (direction Y shown inFIG.9), and each supporter3extends along the first direction.

In an example, referring toFIG.4toFIG.6, the support material layer3′ may be formed on the multilayer film stack2′ first. Then, a part of the support material layer3′ is removed through lithography, etching, or other processes, and the retained part of the support material layer3′ forms the supporter3.

In an example, referring toFIG.11toFIG.13, a part of the multilayer film stack2′ may be removed through lithography, etching, or other processes first, and then the supporter3is formed through a deposition process in the region in which the multilayer film stack2′ is removed.

Step S400: Etch the multilayer film stack to form a plurality of gate structures arranged at intervals along a first direction, the supporter penetrating a top of each of the plurality of gate structures and extending along the first direction.

In this step, as shown inFIG.8andFIG.9, the multilayer film stack2′ may be etched through an etching process, to form a plurality of gate structures2arranged at intervals along the first direction (direction X inFIG.9), where the supporter3penetrates the top of each of the plurality of gate structures2and extends along the first direction.

Referring toFIG.8andFIG.9, this embodiment shows an example in which a plurality of gate structures2are formed and every two gate structures2form an annular gate group. That is, a mask layer (not shown in the figure) with a block pattern is formed, and the multilayer film stack2′ covered by the block pattern of the mask layer is protected in the etching process and is thus retained; the multilayer film stack2′ not covered by the block pattern of the mask layer is removed by etching, to finally form an annular gate group. The formation of the annular gate group does not constitute limitation on the present disclosure. It may be understood that, the shape of the gate structure2is related to the preset pattern on the mask layer. When the preset pattern on the mask layer is a plurality of strips arranged at intervals, the formed gate structure2is strip-shaped.

In an example, as shown inFIG.9, a material of the supporter3and a material of the multilayer film stack2′ have different etch selectivities, such that in the same etching environment, only a part of the multilayer film stack2′ is removed while the supporter3is retained, to form the supporter3penetrating the plurality of gate structures2.

In this embodiment, a supporter3is first formed on a multilayer film stack2′, and then the multilayer film stack2′ is etched to form a plurality of gate structures2arranged at intervals along a first direction, where the supporter3extends along the first direction and penetrates a top of each of the plurality of gate structures2. A depth-to-width ratio of the gate structure2can be effectively improved by setting the supporter3, thereby improving the electrical performance of the semiconductor structure. The supporter3reliably supports and connects the plurality of gate structures2, thereby effectively avoiding peeling of the gate structure2during processes such as cleaning, to ensure the product yield.

In an exemplary embodiment, step S200may specifically include the following steps:

Step S210: Form a gate dielectric material layer to cover a top surface of the substrate.

In this step, as shown inFIG.3, the gate dielectric material layer21′ may be formed on the top surface of the substrate1through a deposition process. The deposition process has been explained in the foregoing embodiment, and details are not described herein again. In this step, a material of the gate dielectric material layer21′ may be silicon dioxide (SiO2). In other embodiments, the material of the gate dielectric material layer21′ may be at least one of silicon oxynitride (SiON) and silicon nitride (SiN). One or more gate dielectric material layers21′ may be provided. When a plurality of gate dielectric material layers21′ are provided, the gate dielectric material layers21′ may be made of a same material or different materials.

Step S220: Form a gate conductive material layer to cover a top surface of the gate dielectric material layer.

In this step, as shown inFIG.3, the gate conductive material layer22′ may be formed through a deposition process. The gate conductive material layer22′ may be a multilayer film stack including a semiconductor conductive layer and a metal layer. A material of the semiconductor conductive layer may be polysilicon. A material of the metal layer may be tungsten (W). In other embodiments, the gate conductive material layer22′ may also be a single-layer structure only including a metal layer. The material of the metal layer may further be at least one of copper (Cu), gold (Au), and silver (Ag).

Step S220may specifically include the following steps:

Step S221: Form a first conductive material layer to cover the top surface of the gate dielectric material layer.

In this step, referring toFIG.3, the first conductive material layer221′ is the semiconductor material layer in the foregoing embodiment, and details are not described herein again.

Step S222: Form a barrier material layer to cover a top surface of the first conductive material layer221′.

In this step, the barrier material layer222′ is configured to prevent inter-diffusion between the metal layer and the semiconductor conductive layer. The barrier material layer222′ may be formed through a deposition process. A material of the barrier material layer222′ may be titanium nitride (TiN).

Step S223: Form a second conductive material layer to cover the barrier material layer.

In this step, referring toFIG.3, the second conductive material layer223′ is the metal layer in the foregoing embodiment, and details are not described herein again.

Step S230: Form an insulation material cap layer to cover a top surface of the gate conductive material layer.

In this step, as shown inFIG.3, the insulation material cap layer23′ may be formed through a deposition process. In this embodiment, a material of the insulation material cap layer23′ is silicon nitride (SiN). In other embodiments, the insulation material cap layer23′ may also be made of silicon oxynitride (SiON) or other insulation materials. One or more insulation material cap layers23′ may be provided. When a plurality of insulation material cap layers23′ are provided, the insulation material cap layers23′ may be made of a same material or different materials.

Referring toFIG.2, the gate dielectric material layer21′, the gate conductive material layer22′ and the insulation material cap layer23′ jointly constitute the multilayer film stack2′.

In an embodiment, after the multilayer film stack2′ is formed, step S310may be performed, to form the supporter3at the top of the multilayer film stack2′.

Referring toFIG.4toFIG.6, step S310includes the following steps:

Step S311: Form a support material layer on the insulation material cap layer.

In this step, as shown inFIG.4, the support material layer3′ may be formed on the insulation material layer through a deposition process. It needs to be ensured that the support material layer3′ and the multilayer film stack2′ have a specific etch selectivity. The etch selectivity between the support material layer3′ and the multilayer film stack2′ is less than 1:10. For example, when the material of the multilayer film stack2′ is the material in the foregoing embodiment, the material of the support material layer3′ may be silicon carbonitride (SiCN).

Step S312: Form a first mask layer on the support material layer.

In this step, as shown inFIG.5, the first mask layer5amay be formed on the support material layer3′ through a deposition process. A material of the first mask layer5amay be silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), or titanium nitride (TiN).

Step S313: Form a patterned first photoresist layer on the first mask layer, where the patterned first photoresist layer includes a first preset pattern extending along the first direction.

In this step, as shown inFIG.5, the patterned first photoresist layer6amay be formed on the first mask layer5athrough a deposition process. The patterned first photoresist layer6aincludes a first preset pattern extending along the first direction, and the first preset pattern may be strip-shaped, to form a strip-shaped supporter3in post-processing. A material of the first photoresist layer6amay be silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), or titanium nitride (TiN).

Step S314: Pattern the first mask layer based on the first photoresist layer, to transfer the first preset pattern to the first mask layer.

In this step, as shown inFIG.5, downward (the direction opposite to direction Z shown inFIG.9) etching may be performed by using an etching process. The first mask layer5acovered by the first photoresist layer6awill not be removed by etching, and the exposed surface of the first mask layer5ais removed by etching.

Step S315: Etch the support material layer by using the patterned first mask layer as a mask, to obtain the supporter.

In this step, as shown inFIG.6, the first preset pattern on the first mask layer5amay be transferred to the support material layer3′ through an etching process, to remove a partial structure of the support material layer3′, and the retained part of the support material layer3′ forms the supporter3. In another embodiment (this embodiment is not shown in the drawings), a photoresist layer having a first preset pattern may be formed on the support material layer3′. The first preset pattern in the photoresist layer may be transferred to the support material layer3′ through dry etching, to remove a partial structure of the support material layer3′.

After a partial structure of the support material layer3′ is removed through an etching process, the mask is removed through an ashing process, and impurities in the removed region of the support material layer3′ are removed through wet etching, to provide good interface performance and process foundation for subsequent processes, thus helping improve the quality of the formed semiconductor.

In an embodiment, after the multilayer film stack2′ is formed, step S320may also be performed, to form the supporter3at the top of the multilayer film stack2′.

Referring toFIG.11toFIG.13, step S320includes the following steps:

Step S321: Form a second mask layer on the multilayer film stack.

In this step, referring toFIG.11, the second mask layer5bmay be formed on the multilayer film stack2′ through a deposition process. The implementation manner and optional materials of the second mask layer5bare the same as those of the first mask layer5ain step S312, and details are not described herein again.

Step S322: Form a patterned second photoresist layer on the second mask layer, where the patterned second photoresist layer includes a second preset pattern extending along the first direction.

In this step, referring toFIG.11, the patterned second photoresist layer6bmay be formed on the second mask layer5bthrough a deposition process, where the patterned second photoresist layer6bincludes the second preset pattern extending along the first direction. The implementation manner and optional materials of the second photoresist layer6bare the same as those of the first photoresist layer6a, and details are not described herein again.

Step S323: Pattern the second mask layer based on the second photoresist layer, to transfer the second preset pattern to the second mask layer.

In this step, as shown inFIG.11, the second mask layer5bnot covered by the second photoresist layer6bmay be etched through an etching process, to transfer the second preset pattern on the second photoresist layer6bto the second mask layer5b.

Step S324: Etch the insulation material cap layer by using the patterned second mask layer as a mask to obtain a first trench.

In this step, as shown inFIG.12, the second preset pattern on the second mask layer5bmay be transferred to the insulation material cap layer23′ through an etching process, thereby removing a partial structure of the insulation material cap layer23′, and the first trench231′ is formed in the removed region of the insulation material cap layer23′. In another embodiment (this embodiment is not shown in the drawings), a photoresist layer having a second preset pattern may be formed on the insulation material cap layer23′. The second preset pattern in the photoresist layer may be transferred to the insulation material cap layer23′ through dry etching, to remove a partial structure on the insulation material cap layer23′, thereby forming the first trench231′.

Step S325: Fill the first trench with a support material layer to form the supporter.

In this step, as shown inFIG.13, a support material deposited and filled in the first trench231′ through a deposition process. The support material filling the first trench231′ forms the supporter3.

In an example, the support material may be deposited on the upper surface of the insulation material cap layer23′. After the deposition, the support material may be removed through chemical mechanical polishing (CMP), to expose the covered surface of the insulation material cap layer23′, ensuring that the support material only exists in the first trench231′, and the support material in the first trench231′ forms the supporter3.

In an example, a mask having a preset pattern may be disposed on the insulation material cap layer23′, where the mask exposes the first trench231′, thereby depositing the support material in the first trench231′.

In an exemplary embodiment, as shown inFIG.7toFIG.9, step S400in the foregoing embodiment specifically includes the following steps:

Step S410: Form a third mask layer on the supporter and the multilayer film stack.

In this step, as shown inFIG.8, the third mask layer5cmay be formed on the supporter3and the multilayer film stack2′ through a deposition process. The implementation manner of the third mask layer5cis the same as that of the first mask layer5aand the second mask layer5bin the foregoing embodiment, and details are not described herein again.

Step S420: Form a patterned third photoresist layer on the third mask layer, where the patterned third photoresist layer includes third preset patterns arranged at intervals along the first direction.

In this step, as shown inFIG.8, the patterned third photoresist layer6cmay be formed on the third mask layer5cthrough a deposition process, where the patterned third photoresist layer6cincludes the third preset patterns arranged at intervals along the first direction. The implementation manner of the third photoresist layer6cis the same as those of the first photoresist layer6aand the second photoresist layer6b, and details are not described herein again.

FIG.8shows a third photoresist layer6chaving block-shaped third preset patterns, to form block-shaped gate structures2in subsequent processes. In other embodiments, third preset patterns in other shapes such as strip shapes may be formed, thereby forming strip-shaped gate structures2.

Step S430: Pattern the third mask layer based on the third photoresist layer, to transfer the third preset patterns to the third mask layer.

In this step, as shown inFIG.8, the third mask layer5cnot covered by the third photoresist layer6cmay be etched by using an etching process, to transfer the third preset patterns on the third photoresist layer6cto the third mask layer5c.

Step S440: Etch the multilayer film stack by using the patterned third mask layer as a mask, to obtain the plurality of gate structures arranged at intervals along the first direction, and retain the supporter at the top of each of the gate structures.

In this step, as shown inFIG.9, the third preset patterns on the third mask layer5cmay be transferred to the multilayer film stack2′ through an etching process, thereby removing a partial structure in the multilayer film stack2′, such that the retained multilayer film stack2′ forms the gate structures2.

An etch selectivity between the supporter3and the multilayer film stack2′ is less than 1:10, such that in the etching process, the multilayer film stack2′ not covered by the third mask layer5cis removed by etching, and the supporter3has an inert reaction with an etching gas, thereby being retained.

In the etching process, during downward (an opposite direction of direction X shown inFIG.9) etching of the etching gas, the etching gas diffuses to a certain extent in the horizontal direction (a plane in which direction X and direction Y are located inFIG.9). By setting a width of the supporter3in the second direction (direction Y shown inFIG.9) to 2 nm to 10 nm, the etching gas can only remove the multilayer film stack2′ right below the supporter3.

In first exemplary embodiments, in the method of manufacturing a semiconductor structure provided by the embodiments of the present disclosure, after the supporter3is formed and before the multilayer film stack2′ is etched, the method further includes the following steps:

Step S330: Form a supplementary material layer on the multilayer film stack.

In this step, as shown inFIG.6andFIG.7, the supplementary material layer4′ may be formed through a deposition process. A material of the supplementary material layer4′ may be any one or more from the group consisting of hafnium oxide (HfO2), aluminum oxide (Al2O3), and silicon dioxide (SiO2). The supplementary material layer4′ is formed, such that the supplementary material layer4′ wraps side surfaces of the supporter3, thereby improving the connection strength between the supporter3and the gate structure2.

After the supplementary material is formed, the method may further include the following step:

Step S331: Planarize the supplementary material layer.

In this step, as shown inFIG.7, the supplementary material layer4′ is planarized to ensure the flatness of the upper-layer structure. The supplementary material layer4′ is planarized through chemical mechanical polishing (CMP).

An embodiment of the present disclosure further provides a semiconductor structure. As shown inFIG.9andFIG.10, the semiconductor structure includes a substrate1, a plurality of gate structures2, and a supporter3. A material of the substrate1may be silicon (Si), germanium (Ge), silicon-germanium (GeSi), or silicon carbide (SiC); or may be silicon on insulator (SOI) or germanium on insulator (GOI); or may further be another material, for example, a III-V compound such as gallium arsenide. The substrate1is configured to support elements provided thereon. The substrate1may be doped with certain impurity ions as required, and the impurity ions may be N-type impurity ions or P-type impurity ions. In some embodiments, the doping includes well region doping and source drain region doping. In this embodiment, a plurality of transistors may be formed in the substrate1. If the plurality of transistors are used as a part of the DRAM memory, a plurality of active areas11arranged at intervals are provided in the substrate1, and adjacent active areas11are isolated from each other by a shallow trench isolation region12. The active area11includes a channel region, and a source region and a drain region that are located on two sides of the channel region. The source region and the drain region are formed through source drain doping.

As shown inFIG.9andFIG.10, the plurality of gate structures2are located on the substrate1, and are arranged at intervals along a first direction. One shallow trench isolation region12is provided between two adjacent gate structures2.FIG.9shows a semiconductor structure with four gate structures2. Every two gate structures form a gate group, and the two gate structures forming the gate group forms a ring, so as to form an annular gate. It may be understood that, more gate structures2may be arranged in the first direction, and thus the plurality of gate structures2may form 3, 4, 5, or 6 gate groups.

As shown inFIG.9andFIG.10, the gate structure2includes a gate dielectric layer21, a gate conductive layer22, and an insulation cap layer23. Referring toFIG.9andFIG.10, the gate dielectric layer21is located on the substrate1and covers the top surface of the substrate1. A material of the gate dielectric layer21may be at least one from the group consisting of silicon oxide (SiO2), silicon oxynitride (SiON), and silicon nitride (SiN). Referring toFIG.9toFIG.10, the gate conductive layer22is located on the gate dielectric layer21and covers the top surface of the gate dielectric layer21. The gate conductive layer22specifically includes a first conductive layer221, a barrier layer222, and a second conductive layer223. The first conductive layer221is located on the gate dielectric layer21, the barrier layer222is located on the first conductive layer221, and the second conductive layer223is located on the barrier layer222. A material of the first conductive layer221may be polysilicon; a material of the barrier layer222may be titanium nitride (TiN); a material of the second conductive layer223may be at least one from the group consisting of tungsten (W), copper (Cu), gold (Au), and silver (Ag).

As shown inFIG.9andFIG.10, the supporter3penetrates a top of each of the plurality of gate structures2, and extends along the first direction (direction X shown inFIG.9). The supporter3penetrates a top of the insulation cap layer23of the gate structure2. A material of the gate structure2may be silicon carbonitride (SiCN). The gate structure2has a width of 2 nm to 10 nm in a second direction (direction Y shown inFIG.9). By setting the width of the gate structure2within the above range, sufficient support strength can be implemented, and in the process of etching the multilayer film stack2′, the multilayer film stack2′ below the supporter3can be removed by etching. It may be understood that, in the process of etching the multilayer film stack2′ downward (the direction opposite to direction Z shown inFIG.9), an etching gas diffuses in a certain range in the horizontal direction (a plane in which direction X and direction Y are located inFIG.9), thereby removing the multilayer film stack2′ below the supporter3.

It should be noted that, a material of the multilayer film stack2′ is different from that of the supporter3. An etch selectivity between the supporter3and the multilayer film stack2′ is less than 1:10, such that only the multilayer film stack2′ is removed by etching in the process of etching the multilayer film stack2′, while the supporter3can be retained.

In this embodiment, the supporter3is provided on the plurality of gate structures2, and the supporter3penetrates the top of each of the plurality of gate structures2. An extension direction of the supporter3is the same as the arrangement direction of the gate structures2, which improves the depth-to-width ratio of the gate structure2, thereby improving the electrical performance of the semiconductor device. Moreover, the supporter3avoids peeling of the gate structure2in the subsequent multiple cleaning processes.

In an exemplary embodiment, as shown inFIG.9, the semiconductor structure further includes a supplementary layer4. The supplementary layer4is located on the insulation cap layer23, and the supporter3penetrates the supplementary layer4. In an example, referring to step S310in the foregoing embodiment, the supplementary layer4is formed after formation of the supporter3. Optional materials of the supplementary layer4are the same as those of the insulation cap layer23, and details are not described herein again.

The embodiments or implementations of this specification are described in a progressive manner, and each embodiment focuses on differences from other embodiments. The same or similar parts between the embodiments may refer to each other.

In the description of this specification, the description with reference to terms such as “an embodiment”, “an exemplary embodiment”, “some implementations”, “a schematic implementation”, and “an example” means that the specific feature, structure, material, or characteristic described in combination with the implementation(s) or example(s) is included in at least one implementation or example of the present disclosure.

In this specification, the schematic expression of the above terms does not necessarily refer to the same implementation or example. Moreover, the described specific feature, structure, material or characteristic may be combined in an appropriate manner in any one or more implementations or examples.

It should be noted that in the description of the present disclosure, the terms such as “center”, “top”, “bottom”, “left”, “right”, “vertical”, “horizontal”, “inner” and “outer” indicate the orientation or position relationships based on the accompanying drawings. These terms are merely intended to facilitate description of the present disclosure and simplify the description, rather than to indicate or imply that the mentioned apparatus or element must have a specific orientation and must be constructed and operated in a specific orientation. Therefore, these terms should not be construed as a limitation to the present disclosure.

It can be understood that the terms such as “first” and “second” used in the present disclosure can be used to describe various structures, but these structures are not limited by these terms. Instead, these terms are merely intended to distinguish one structure from another.

The same elements in one or more accompanying drawings are denoted by similar reference numerals. For the sake of clarity, various parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown. For the sake of brevity, a structure obtained by implementing a plurality of steps may be shown in one figure. In order to understand the present disclosure more clearly, many specific details of the present disclosure, such as the structure, material, size, processing process, and technology of the device, are described below. However, as those skilled in the art can understand, the present disclosure may not be implemented according to these specific details.

Finally, it should be noted that the above embodiments are merely intended to explain the technical solutions of the present disclosure, rather than to limit the present disclosure. Although the present disclosure is described in detail with reference to the above embodiments, those skilled in the art should understand that they may still modify the technical solutions described in the above embodiments, or make equivalent substitutions of some or all of the technical features recorded therein, without deviating the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present disclosure.

INDUSTRIAL APPLICABILITY

In the method of manufacturing a semiconductor structure and the semiconductor structure provided by the embodiments of the present disclosure, a depth-to-width ratio of a gate structure can be effectively improved by setting a supporter, thereby improving the electrical performance of the semiconductor structure. The supporter reliably supports and connects the plurality of gate structures, thereby effectively avoiding peeling of the gate structure during processes such as cleaning, to ensure the product yield.