Nonvolatile memory system

A nonvolatile (NV) memory system includes a memory control module that encodes data to provide encoded logical data structures. The system also includes NV memory that includes X arrays that include physical data structures that differ in size from the encoded logical data structures. The memory control module writes/reads from the NV memory according to the encoded logical data structures. X is an integer greater than or equal to 1.

FIELD

The present disclosure relates to memory systems and, more particularly, to systems and methods for storing data in nonvolatile (NV) memory.

BACKGROUND

Referring now toFIGS. 1,2A and2B, nonvolatile (NV) semiconductor memory10may include flash memory, static random access memory (SRAM), nitride read only memory (NROM), phase change memory, magnetic RAM, multi-state memory, etc. The NV semiconductor memory10may include one or more arrays16that may each be arranged on one or more memory chips. The arrays16may include data structures, such as blocks and pages. The arrays16may therefore be arranged as B blocks18-1,18-2, . . . , and18-B (collectively referred to as blocks18).

InFIG. 2A, each block18includes P pages20-1,20-2, . . . , and20-P (collectively referred to as pages20). InFIG. 2B, each page20may include a plurality of memory cells that are associated with a data portion24and may include other memory cells that are associated with an overhead data portion26such as error correcting code (ECC) data or other (O) overhead data.

Referring now toFIG. 2C, a memory drive may include one or more arrays16-1,16-2, . . . , and16-C (collectively referred to as arrays16) and each include blocks18. Usually, the control module addresses the memory drive according to a hardwired physical block size. Pages20in the blocks18may also have a hardwired physical page size and may therefore be referred to as physical pages. The number of memory cells in the data and overhead portions of the pages20may also be hardwired.

For example only, a NAND flash array may include 2048 blocks for a total of 2 Gigabytes (GB) of memory. Each block may include 128 kilobytes (KB) in 64 pages. Each page20may include 2112 bytes. Of the 2112 bytes, 2048 bytes may be associated with the data portion and 64 bytes may be associated with the overhead portion. Each memory cell may store a bit.

The memory control module erases pages20and blocks18according to predetermined erase blocks29-1,29-2, . . . , and29-R (collectively referred to as erase blocks29). The memory control module generally requires data in an entire erase block to be erased simultaneously.

A host device may initiate a read operation and provide data files to the memory control module that are arranged in multiples of allocation units (AUs) of predefined size that fit in a physical block. AUs correspond to the smallest logical amount of memory space that can be allocated by the control module to store a file and may therefore be referred to as logical pages. Groupings of logical pages may be referred to as logical blocks.

When a write command is issued, data is sent in multiples of logical block size to the memory control module. The memory control module allocates the exact number of physical pages20to accommodate the logical pages. Even when ECC is used on logical page data, the number of parity bits are kept within the number of spare bits per overhead portion of a respective physical page. Therefore, one (ECC) coded logical page fits in an integer number of physical pages, and one coded logical block fits within an integer number of physical blocks.

SUMMARY

A nonvolatile (NV) memory system includes a memory control module that encodes data to provide encoded logical data structures. The system also includes NV memory that includes X arrays that include physical data structures that differ in size from the encoded logical data structures. The memory control module writes/reads from the NV memory according to the encoded logical data structures. X is an integer greater than or equal to 1.

In other features, the memory control module sends and receives the data in logical data structures. The logical data structures comprise at least one of logical pages and logical blocks. The physical data structures comprise at least one of physical pages and physical blocks in the NV memory. The memory control module includes an encoder module that selects one of N error correction code (ECC) rates where N>1. The encoder module performs encoding according to at least one of a Reed Solomon scheme, a Bose-Chaudhuri-Hocquenghem (BCH) scheme, a Low Density Parity Check (LDPC) scheme, a Gray code scheme, and a combination of two or more of the BCH scheme, the LDPC scheme, and the Gray code scheme.

In other features, the memory control module includes a decoder module that decodes the encoded logical data structures during a read operation from the NV memory. The memory control module writes to the X arrays in parallel when X>1. The memory control module writes a first portion of a first of the encoded logical data structures to a first of the X arrays while writing a second portion of the first of the encoded logical data structures to a second of the X arrays. The memory control module writes a first portion of a second of the encoded logical data structures to the second of the arrays while writing the first and second portions of the first of the encoded logical data structures.

In other features, the memory control module allocates buffers within the X arrays for each of the encoded logical data structures. The allocation is conducted so that portions of the encoded logical data structures that do not fit into the physical data structures are stored in the buffers. Each of the X arrays corresponds to one or more memory chips. The memory control module selectively determines an amount of data to erase in the NV memory based on a size of the encoded logical data. The amount of data includes data within a predetermined number of cells within all of the X arrays.

In other features, the system includes a memory drive that includes the memory control module and the NV memory. The system further includes the host device that communicates with the memory drive according to the logical data structures. The NV memory includes at least one of flash memory, static random access memory (SRAM), nitride read only memory (NROM), phase change memory, magnetic RAM and multi-state memory. The physical data structures differ in size from the encoded logical data structures so that a size of the physical data structures and a size of the encoded logical data structures do not have an integer relationship.

In other features, a method for operating a nonvolatile (NV) memory system includes encoding data to provide encoded logical data structures. The method also includes writing/reading from NV memory according to the encoded logical data structures. The NV memory includes X arrays that include physical data structures that differ in size from the encoded logical data structures. X is an integer greater than or equal to 1.

In other features, the method includes sending and receiving the data external to the NV memory system in logical data structures. The logical data structures comprise at least one of logical pages and logical blocks. The physical data structures comprise at least one of physical pages and physical blocks in the NV memory. The method also includes selecting one of N error correction code (ECC) rates where N>1. The method also includes encoding the data according to at least one of a Reed Solomon scheme, a Bose-Chaudhuri-Hocquenghem (BCH) scheme, a Low Density Parity Check (LDPC) scheme, a Gray code scheme, and a combination of two or more of the BCH scheme, the LDPC scheme, and the Gray code scheme.

In other features, the method includes decoding the encoded logical data structures during a read operation from the NV memory. The method also includes writing to the X arrays in parallel when X>1. The method also includes writing a first portion of a first of the encoded logical data structures to a first of the X arrays while writing a second portion of the first of the encoded logical data structures to a second of the X arrays. The method also includes writing a first portion of a second of the encoded logical data structures to the second of the arrays while writing the first and second portions of the first of the encoded logical data structures.

In other features, the method includes allocating buffers within the X arrays for each of the encoded logical data structures. The allocation is conducted so that portions of the encoded logical data structures that do not fit into the physical data structures are stored in the buffers. Each of the X arrays corresponds to one or more memory chips. The method also includes determining an amount of data to erase in the NV memory based on a size of the encoded logical data. The amount of data includes data within a predetermined number of cells within all of the X arrays.

In other features, the NV memory includes at least one of flash memory, static random access memory (SRAM), nitride read only memory (NROM), phase change memory, magnetic RAM and multi-state memory. The physical data structures differ in size from the encoded logical data structures so that a size of the physical data structures and a size of the encoded logical data structures do not have an integer relationship.

In other features, a nonvolatile (NV) memory system includes memory control means for encoding data to provide encoded logical data structures. The system also includes NV means for storing data that includes X arrays that include physical data structures that differ in size from the encoded logical data structures. The memory control means writes/reads from the NV means according to the encoded logical data structures. X is an integer greater than or equal to 1.

In other features, the memory control means sends and receives the data in logical data structures. The logical data structures comprise at least one of logical pages and logical blocks. The physical data structures comprise at least one of physical pages and physical blocks in the NV means. The memory control means includes encoder means for selecting one of N error correction code (ECC) rates, where N>1. The encoder means performs encoding according to at least one of a Reed Solomon scheme, a Bose-Chaudhuri-Hocquenghem (BCH) scheme, a Low Density Parity Check (LDPC) scheme, a Gray code scheme, and a combination of two or more of the BCH scheme, the LDPC scheme, and the Gray code scheme.

In other features, the memory control means includes decoder means for decoding the encoded logical data structures during a read operation from the NV means. The memory control means writes to the X arrays in parallel when X>1. The memory control means writes a first portion of a first of the encoded logical data structures to a first of the X arrays while writing a second portion of the first of the encoded logical data structures to a second of the X arrays. The memory control means writes a first portion of a second of the encoded logical data structures to the second of the arrays while writing the first and second portions of the first of the encoded logical data structures.

In other features, the memory control means allocates buffers within the X arrays for each of the encoded logical data structures so that portions of the encoded logical data structures that do not fit into the physical data structures are stored in the buffers. Each of the X arrays corresponds to one or more memory chips. The memory control means selectively determines an amount of data to erase in the NV means based on a size of the encoded logical data. The amount of data includes data within a predetermined number of cells within all of the X arrays.

In other features, the system includes memory drive means for storing data that includes the memory control means and the NV means. The system further includes the host device that communicates with the memory drive means according to the logical data structures. The NV means includes at least one of flash memory, static random access memory (SRAM), nitride read only memory (NROM), phase change memory, magnetic RAM and multi-state memory. The physical data structures differ in size from the encoded logical data structures so that a size of the physical data structures and a size of the encoded logical data structures do not have an integer relationship.

In still other features, the systems and methods described above are implemented by a computer program executed by one or more processors. The computer program can reside on a computer readable medium such as but not limited to memory, non-volatile data storage, and/or other suitable tangible storage mediums. The computer program operates a nonvolatile (NV) memory system and includes encoding data to provide encoded logical data structures. The computer program also includes writing/reading from NV memory according to the encoded logical data structures. The NV memory includes X arrays that include physical data structures that differ in size from the encoded logical data structures. X is an integer greater than or equal to 1.

In other features, the computer program includes sending and receiving the data external to the NV memory system in logical data structures. The logical data structures comprise at least one of logical pages and logical blocks. The physical data structures comprise at least one of physical pages and physical blocks in the NV memory. The computer program also includes selecting one of N error correction code (ECC) rates where N>1. The computer program also includes encoding the data according to at least one of a Reed Solomon scheme, a Bose-Chaudhuri-Hocquenghem (BCH) scheme, a Low Density Parity Check (LDPC) scheme, a Gray code scheme, and a combination of two or more of the BCH scheme, the LDPC scheme, and the Gray code scheme.

In other features, the computer program includes decoding the encoded logical data structures during a read operation from the NV memory. The computer program also includes writing to the X arrays in parallel when X>1. The computer program also includes writing a first portion of a first of the encoded logical data structures to a first of the X arrays while writing a second portion of the first of the encoded logical data structures to a second of the X arrays. The computer program also includes writing a first portion of a second of the encoded logical data structures to the second of the arrays while writing the first and second portions of the first of the encoded logical data structures.

In other features, the computer program includes allocating buffers within the X arrays for each of the encoded logical data structures so that portions of the encoded logical data structures that do not fit into the physical data structures are stored in the buffers. Each of the X arrays corresponds to one or more memory chips. The computer program also includes determining an amount of data to erase in the NV memory based on a size of the encoded logical data. The amount of data includes data within a predetermined number of cells within all of the X arrays.

In other features, the NV memory includes at least one of flash memory, static random access memory (SRAM), nitride read only memory (NROM), phase change memory, magnetic RAM and multi-state memory. The physical data structures differ in size from the encoded logical data structures so that a size of the physical data structures and a size of the encoded logical data structures do not have an integer relationship.

DETAILED DESCRIPTION

Previously, a host device interfaced with a memory control module according to logical data structures, such as logical pages or blocks of logical pages, that were restricted to a predetermined size. The memory control module encoded the data, and either one coded logical page contained an integer number of physical pages within memory, or a physical page within memory contained an integer number of coded logical pages.

In other words, there previously was an integer relationship between the logical page and physical page, although the relationship was not necessarily 1:1. For example, a logical page could be 0.5 kilobytes (KB) while a physical page could be 2 KB, or the logical page could be 4 KB while the physical page could be 2 KB. In either case, the logical page either completely fit in one physical page or was evenly distributed into several physical pages.

In the present disclosure, the memory control module may instead modify coded logical block (CLB) size and/or physical block size so that they are no longer integer multiples of each other. The CLBs may thus be spread among multiple arrays, which may be included on one or more memory chips. During a read operation, the memory control module may reformat data from the memory into groupings that conform to logical data structures of a host device interface. The host device may receive the data according to the logical data structures.

For example, a logical page can be 4.4 KB while a hard-wired physical page is 2 KB. In this case, the logical page may be unevenly distributed into, for example, 3 physical pages. The first two pages contain 2 KB each, while the last physical page contains 0.4 KB of the logical page. Also, the last physical page may contain a first portion of the next logical page.

Referring now toFIG. 3A, a memory system66for a nonvolatile (NV) semiconductor memory68, such as multilevel flash memory, is illustrated. InFIG. 3A, a host device70communicates with a solid state NV memory drive69that includes a memory control module72and the NV memory68. The memory control module72may communicate with the memory68via write and read path modules73,75that erase, write to and read from erase blocks80-1,80-2, . . . , and80-A (collectively referred to as erase blocks80).

The NV memory68may include one or more arrays78-1,78-2, . . . , and78-X (collectively referred to as array78) of memory cells that may each correspond to one or more memory chips. The array78may be arranged according to physical memory blocks of predetermined size that include physical pages of predetermined size. The memory control module72may receive data in logical blocks and/or logical pages from the host device70and generate a physical format for the data that differs from the hard-wired physical format of the NV memory68. The generated physical format is modified from the physical format and may therefore be referred to as a modified physical format. In other words, the memory control module72may write data according to coded logical block size and not physical block size.

The memory control module72may reformat physical blocks, physical pages and erase blocks80to, for example, increase error correction code (ECC) rates for the data. Different ECC rates may be used to maintain integrity of the data. ECC rates may be represented by fractional numbers and may indicate the portion of the total amount of data that is not part of the ECC. In other words, if the code rate is k/n, for every k bits of useful information, the coder generates n bits of data, of which n-k are redundant.

For example, a rate of 0.9 ECC may be used. If user data is 4 KB per read/write operation, then the CLB size may be 4.4 KB, which is 4.4*8/6=5.87 physical pages (if each cell contains 3 bits, and each physical page contains 2048 (2K) cells, then physical page size may be 6 KB). Therefore, the CLB size may be larger than the physical block size, and CLB size may not be an integer multiple of the physical block size. Therefore, the memory control module72writes to the memory68based on the CLB size rather than the physical block size. As another example, if the ECC rate is 0.85, then CLB size may equal 4.7 KB, which is 6.27 physical pages. The present disclosure may support multiple (for example, rate 0.9 and rate 0.85) ECC codes and select from the different ECC code rates for a particular field.

Referring now toFIG. 3B, the write path module73is illustrated. The write path module73may include an ECC encoder module93that encodes received data with an overhead portion. The ECC encoder module93may include a cyclic redundancy (CRC) module (not shown) that generates CRC bits based on user data. The ECC encoder module93may include other encoding modules, such as a Reed Solomon encoder module or a Bose-Chaudhuri-Hocquenghem (BCH)/Low Density Parity Check (LDPC) encoder module. The write path module73may also include a write format module100that generates the modified block and/or page format for the memory68.

Referring now toFIG. 3C, a read path module75is illustrated. The read path module75includes a read format module104that reads data from the memory68based on the modified block and/or page format. The read path module75also includes an ECC decoder module106that decodes the read-back signals that were encoded by the ECC encoder module93. The ECC decoder module may include, for example, a LDPC module, a Gray Code decoder module, a BCH decoder module, a Reed-Solomon decoder and/or a CRC decoder.

Referring now toFIG. 3D, the write and read format modules100,104may employ column and row select modules (not shown) to select memory cells within the NV memory68. The write format module100may also include a rate selection module105that selects a rate for the ECC encoder module93. Alternatively, an external rate selection module may select the ECC rate. During a write operation, a logical block size module108of the write format module100receives ECC encoded logical blocks of data and determines a size of the CLBs.

A physical format module110allocates a portion of the memory68based on the size of the CLBs. The allocated portion may be referred to as a modified physical block of data and may include any number of memory cells, such as a particular cell, a row of cells, a column of cells, a block of cells, a page of cells, erase blocks, etc. The physical format module110may erase data in an erase block that may or may not correspond to a predetermined erase block80of the NV memory68. At least a portion of the erase block80is allocated for the modified physical block. The physical format module110writes to cells within the modified physical block of the NV memory68. The physical format module110may also include memory (not shown) that stores a memory map based on modified blocks of data.

The read format module104may include a read module120that reads back data from the NV memory68according to the modified physical block as provided by the physical format module110. During a read operation, the read module120selects read target cells, which may include any number of memory cells, such as a particular cell, a row of cells, a column of cells, a block of cells, a page of cells, etc. Once the read target cells are selected, the read module120reads the read target cells. A logical block size module122may then reapportion the data (before or after decoding) according to the original logical blocks/pages as when the data was sent to the memory control module72.

Referring now toFIG. 4, a modified memory map is shown for write/read operations. Arrays78are divided by erase blocks80. The memory control module72writes CLBs200-1,200-2, . . . , and200-N (collectively referred to as CLBs200) across the arrays78regardless of the original physical size of data structures in the arrays78. For example, the first CLB200-1fills the memory cells in a physical page of array78-1and also fills memory cells within part of a physical page within array78-2.

The memory control module72may write to some or all of the arrays78in parallel. For example, when the memory control module72writes three CLBs (CLB1, CLB2, CLB3), after encoding, the memory control module72may send a first part260of CLB1to the first array78-1, and simultaneously send a second part262of CLB1with a first part264of the CLB2to the second array78-2, etc.

Conventional NV memory drives use a page/erase block structure to store data. For example, a physical page may contain 2 KB of data plus an overhead area if each memory cell contains 1 bit of data. If each memory cell contains 3 bits of data, then the physical page size may be 6 KB. An erase block contains an integer number of physical pages. Typical size for erase block may range from 128 KB to 512 KB. Data in the erase block may be erased simultaneously.

In the present disclosure, the memory control module72may define logical page size to be, for example, 4 KB, so that write/read commands transfer a multiple of 4 KB of data between the memory control module72and the host device70. Meanwhile, the memory control module72may define a physical block size to be, for example, 4.4 KB. The additional 0.4 KB of the modified physical block may correspond to an additional 0.4 KB of ECC added to the original 4 KB. In other words, logical page size (for example 4 KB) may be an integer multiple of physical page size (for example 4 KB) but differs from modified physical page size (for example 4.4 KB). Likewise, if the memory control module72defines logical block size as 4 KB, where logical block size is an integer multiple of physical block size (for example 4 KB), modified physical block size may be set to, for example, 4.4 KB, which is not an integer multiple of physical block size.

Referring now toFIGS. 5-6, simplified memory arrays78are provided to illustrate two exemplary methods for writing to the NV memory68. The simplified memory arrays78include CLBs that are illustrated as integers (1-7). The first method, as inFIG. 5, includes spreading CLBs200across multiple arrays78. Each of the CLBs200includes a portion209-1,209-2, . . . , and209-N that overlaps two or more physical blocks in two or more arrays78. The second method ofFIG. 6includes setting each CLB200in a single array. For parallel writing according to the second method, the memory control module72may define a buffer210-1,210-2, . . . , and210-N in each array78to store a part of each of the CLBs200that exceeds (i.e. overflows) the physical blocks.

Referring now toFIG. 7an exemplary method300for writing to and reading from memory is illustrated. Logic starts in step302. In step304, the memory control module72receives logical pages of data. In step306, the memory control module72encodes the data. The encoding may be selectively based on a desired integrity for the data and/or may be predetermined. In step308, if the CLBs match the physical blocks in memory, and control goes to step312. In step312, the memory control module72writes/reads from the memory and then decodes the data in step314.

If in step308the CLBs differ from the physical blocks, the memory control module72modifies the physical blocks and/or pages in step316. For example, if CLB size is 5.2 KB and physical block or page size is 4 KB, the memory control module72may request the memory drive to allocate enough space for the 5.2 KB CLB size for each write operation. The allocated memory space may be referred to as modified physical blocks or pages that would then, for example, include 5.2 KB. In step320, the memory control module72writes/reads according to the modified physical blocks and/or pages.

The host device70may still transfer data using logical blocks/pages as the smallest unit, but the memory control module72may now accommodate high rate ECCs to the data before sending it to the memory drive. The present disclosure may also decrease write/read time by bypassing physical blocks and/or pages and by writing to multiple memory arrays simultaneously.

Referring now toFIGS. 8A-8G, various exemplary implementations incorporating the teachings of the present disclosure are shown.

Referring now toFIG. 8A, the teachings of the disclosure can be implemented in NV memory of a hard disk drive (HDD)400. The HDD400includes a hard disk assembly (HDA)401and an HDD printed circuit board (PCB)402. The HDA401may include a magnetic medium403, such as one or more platters that store data, and a read/write device404. The read/write device404may be arranged on an actuator arm405and may read and write data on the magnetic medium403. Additionally, the HDA401includes a spindle motor406that rotates the magnetic medium403and a voice-coil motor (VCM)407that actuates the actuator arm405. A preamplifier device408amplifies signals generated by the read/write device404during read operations and provides signals to the read/write device404during write operations.

The HDD PCB402includes a read/write channel module (hereinafter, “read channel”)409, a hard disk controller (HDC) module410, a buffer411, the NV memory412, a processor413, and a spindle/VCM driver module414. The read channel409processes data received from and transmitted to the preamplifier device408. The HDC module410controls components of the HDA401and communicates with an external device (not shown) via an I/O interface415. The external device may include a computer, a multimedia device, a mobile computing device, etc. The I/O interface415may include wireline and/or wireless communication links.

The HDC module410may receive data from the HDA401, the read channel409, the buffer411, NV memory412, the processor413, the spindle/VCM driver module414, and/or the I/O interface415. The processor413may process the data, including encoding, decoding, filtering, and/or formatting. The processed data may be output to the HDA401, the read channel409, the buffer411, NV memory412, the processor413, the spindle/VCM driver module414, and/or the I/O interface415.

The HDC module410may use the buffer411and/or NV memory412to store data related to the control and operation of the HDD400. The buffer411may include DRAM, SDRAM, etc. NV memory412may include any suitable type of semiconductor or solid-state memory, such as flash memory (including NAND and NOR flash memory), phase change memory, magnetic RAM, and multi-state memory, in which each memory cell has more than two states. The spindle/VCM driver module414controls the spindle motor406and the VCM407. The HDD PCB402includes a power supply416that provides power to the components of the HDD400.

Referring now toFIG. 8B, the teachings of the disclosure can be implemented in NV memory of a DVD drive418or of a CD drive (not shown). The DVD drive418includes a DVD PCB419and a DVD assembly (DVDA)420. The DVD PCB419includes a DVD control module421, a buffer422, the NV memory423, a processor424, a spindle/FM (feed motor) driver module425, an analog front-end module426, a write strategy module427, and a DSP module428.

The DVD control module421controls components of the DVDA420and communicates with an external device (not shown) via an I/O interface429. The external device may include a computer, a multimedia device, a mobile computing device, etc. The I/O interface429may include wireline and/or wireless communication links.

The DVD control module421may receive data from the buffer422, NV memory423, the processor424, the spindle/FM driver module425, the analog front-end module426, the write strategy module427, the DSP module428, and/or the I/O interface429. The processor424may process the data, including encoding, decoding, filtering, and/or formatting. The DSP module428performs signal processing, such as video and/or audio coding/decoding. The processed data may be output to the buffer422, NV memory423, the processor424, the spindle/FM driver module425, the analog front-end module426, the write strategy module427, the DSP module428, and/or the I/O interface429.

The DVD control module421may use the buffer422and/or NV memory423to store data related to the control and operation of the DVD drive418. The buffer422may include DRAM, SDRAM, etc. NV memory423may include any suitable type of semiconductor or solid-state memory, such as flash memory (including NAND and NOR flash memory), phase change memory, magnetic RAM, and multi-state memory, in which each memory cell has more than two states. The DVD PCB419includes a power supply430that provides power to the components of the DVD drive418.

The DVDA420may include a preamplifier device431, a laser driver432, and an optical device433, which may be an optical read/write (ORW) device or an optical read-only (OR) device. A spindle motor434rotates an optical storage medium435, and a feed motor436actuates the optical device433relative to the optical storage medium435.

When reading data from the optical storage medium435, the laser driver provides a read power to the optical device433. The optical device433detects data from the optical storage medium435, and transmits the data to the preamplifier device431. The analog front-end module426receives data from the preamplifier device431and performs such functions as filtering and A/D conversion. To write to the optical storage medium435, the write strategy module427transmits power level and timing data to the laser driver432. The laser driver432controls the optical device433to write data to the optical storage medium435.

Referring now toFIG. 8C, the teachings of the disclosure can be implemented in NV memory of a high definition television (HDTV)437. The HDTV437includes an HDTV control module438, a display439, a power supply440, the memory441, a storage device442, a network interface443, and an external interface445. If the network interface443includes a wireless local area network interface, an antenna (not shown) may be included.

The HDTV437can receive input signals from the network interface443and/or the external interface445, which can send and receive data via cable, broadband Internet, and/or satellite. The HDTV control module438may process the input signals, including encoding, decoding, filtering, and/or formatting, and generate output signals. The output signals may be communicated to one or more of the display439, memory441, the storage device442, the network interface443, and the external interface445.

Memory441may include random access memory (RAM) and/or NV memory. NV memory may include any suitable type of semiconductor or solid-state memory, such as flash memory (including NAND and NOR flash memory), phase change memory, magnetic RAM, and multi-state memory, in which each memory cell has more than two states. The storage device442may include an optical storage drive, such as a DVD drive, and/or a hard disk drive (HDD). The HDTV control module438communicates externally via the network interface443and/or the external interface445. The power supply440provides power to the components of the HDTV437.

Referring now toFIG. 5D, the teachings of the disclosure may be implemented in NV memory of a vehicle446. The vehicle446may include a vehicle control system447, a power supply448, the memory449, a storage device450, and a network interface452. If the network interface452includes a wireless local area network interface, an antenna (not shown) may be included. The vehicle control system447may be a powertrain control system, a body control system, an entertainment control system, an anti-lock braking system (ABS), a navigation system, a telematics system, a lane departure system, an adaptive cruise control system, etc.

The vehicle control system447may communicate with one or more sensors454and generate one or more output signals456. The sensors454may include temperature sensors, acceleration sensors, pressure sensors, rotational sensors, airflow sensors, etc. The output signals456may control engine operating parameters, transmission operating parameters, suspension parameters, etc.

The power supply448provides power to the components of the vehicle446. The vehicle control system447may store data in memory449and/or the storage device450. Memory449may include random access memory (RAM) and/or NV memory. NV memory may include any suitable type of semiconductor or solid-state memory, such as flash memory (including NAND and NOR flash memory), phase change memory, magnetic RAM, and multi-state memory, in which each memory cell has more than two states. The storage device450may include an optical storage drive, such as a DVD drive, and/or a hard disk drive (HDD). The vehicle control system447may communicate externally using the network interface452.

Referring now toFIG. 8E, the teachings of the disclosure can be implemented in NV memory of a cellular phone458. The cellular phone458includes a phone control module460, a power supply462, the memory464, a storage device466, and a cellular network interface467. The cellular phone458may include a network interface468, a microphone470, an audio output472such as a speaker and/or output jack, a display474, and a user input device476such as a keypad and/or pointing device. If the network interface468includes a wireless local area network interface, an antenna (not shown) may be included.

The phone control module460may receive input signals from the cellular network interface467, the network interface468, the microphone470, and/or the user input device476. The phone control module460may process signals, including encoding, decoding, filtering, and/or formatting, and generate output signals. The output signals may be communicated to one or more of memory464, the storage device466, the cellular network interface467, the network interface468, and the audio output472.

Memory464may include random access memory (RAM) and/or NV memory. NV memory may include any suitable type of semiconductor or solid-state memory, such as flash memory (including NAND and NOR flash memory), phase change memory, magnetic RAM, and multi-state memory, in which each memory cell has more than two states. The storage device466may include an optical storage drive, such as a DVD drive, and/or a hard disk drive (HDD). The power supply462provides power to the components of the cellular phone458.

Referring now toFIG. 8F, the teachings of the disclosure can be implemented in NV memory of a set top box478. The set top box478includes a set top control module480, a display481, a power supply482, the memory483, a storage device484, and a network interface485. If the network interface485includes a wireless local area network interface, an antenna (not shown) may be included.

The set top control module480may receive input signals from the network interface485and an external interface487, which can send and receive data via cable, broadband Internet, and/or satellite. The set top control module480may process signals, including encoding, decoding, filtering, and/or formatting, and generate output signals. The output signals may include audio and/or video signals in standard and/or high definition formats. The output signals may be communicated to the network interface485and/or to the display481. The display481may include a television, a projector, and/or a monitor.

The power supply482provides power to the components of the set top box478. Memory483may include random access memory (RAM) and/or NV memory. NV memory may include any suitable type of semiconductor or solid-state memory, such as flash memory (including NAND and NOR flash memory), phase change memory, magnetic RAM, and multi-state memory, in which each memory cell has more than two states. The storage device484may include an optical storage drive, such as a DVD drive, and/or a hard disk drive (HDD).

Referring now toFIG. 8G, the teachings of the disclosure can be implemented in NV memory of a mobile device489. The mobile device489may include a mobile device control module490, a power supply491, the memory492, a storage device493, a network interface494, and an external interface499. If the network interface494includes a wireless local area network interface, an antenna (not shown) may be included.

The mobile device control module490may receive input signals from the network interface494and/or the external interface499. The external interface499may include USB, infrared, and/or Ethernet. The input signals may include compressed audio and/or video, and may be compliant with the MP3 format. Additionally, the mobile device control module490may receive input from a user input496such as a keypad, touchpad, or individual buttons. The mobile device control module490may process input signals, including encoding, decoding, filtering, and/or formatting, and generate output signals.

The mobile device control module490may output audio signals to an audio output497and video signals to a display498. The audio output497may include a speaker and/or an output jack. The display498may present a graphical user interface, which may include menus, icons, etc. The power supply491provides power to the components of the mobile device489. Memory492may include random access memory (RAM) and/or NV memory.

NV memory may include any suitable type of semiconductor or solid-state memory, such as flash memory (including NAND and NOR flash memory), phase change memory, magnetic RAM, and multi-state memory, in which each memory cell has more than two states. The storage device493may include an optical storage drive, such as a DVD drive, and/or a hard disk drive (HDD). The mobile device may include a personal digital assistant, a media player, a laptop computer, a gaming console, or other mobile computing device.