POWER DESIGN ARCHITECTURE

A power design architecture including a power supply circuit, a power wiring, at least one chip, a power ring, and a first reference conductor is provided. The power wiring is connected to the power supply circuit. The power ring is disposed around the chip and electrically connected to the chip and the power wiring. The first reference conductor is electrically connected to the chip. Low self-impedance is maintained at any position of the power ring.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefit of Taiwanese application no.111139712, filed on Oct. 19, 2022. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.

TECHNICAL FIELD

The disclosure relates to a circuit architecture, and relates to a power design architecture.

BACKGROUND

The most common method to ensure power integrity (PI) is to add a decoupling capacitor, and this method is particularly suitable for solving the problem of voltage drop. In a load circuit, a local capacitor absorbs a transient supply current and helps meet the transient charge demand. However, the following problems arise. First, the number of passive capacitive components disposed increases; second, because the number of passive capacitive components disposed increases, an area required for placing passive capacitive components also increases; and third, there are different frequency settings under heterogeneous IC integration operation. The above-mentioned problems all cause troubles in the placement of decoupling capacitors.

Therefore, how to achieve the effect of low self-impedance without affecting the number of passive capacitive components is a technology that needs to be developed urgently.

SUMMARY

A power design architecture according to an embodiment of the disclosure includes a power supply circuit, a power wiring, at least one chip, a power ring, and a first reference conductor. The power wiring is connected to the power supply circuit. The power ring is disposed around the chip and is electrically connected to the chip and the power wiring. The first reference conductor is electrically connected to the chip. Low self-impedance is maintained at any position of the power ring.

In an embodiment of the disclosure, the power design architecture further includes a first substrate, and the power wiring, the chip, the power ring, and the first reference conductor are all disposed on the first substrate. The first substrate is a dielectric plate.

In an embodiment of the disclosure, the power design architecture further includes a second reference conductor disposed on the same side of the first substrate as the chip and the power ring.

In an embodiment of the disclosure, the power design architecture further includes a second substrate and a second reference conductor. The second substrate is disposed between the first reference conductor and the second reference conductor, and the power ring is disposed in the second substrate.

DETAILED DESCRIPTION OF DISCLOSED EMBODIMENTS

A power design architecture according to an embodiment of the disclosure includes a power supply circuit, a power wiring, a chip, a power ring, and a reference conductor. The power wiring and the reference conductor, and the power ring and the reference conductor respectively form a first power transmission wiring and a second power transmission wiring. The disclosure provides a power design architecture capable of lowering self-impedance. After electrical lengths and characteristic impedance of the first power transmission wiring and the second power transmission wiring are properly designed, the effect of maintaining low self-impedance is achieved at any position of the power ring, thereby suppressing the generation of voltage noise. In addition, since the power ring is around the chip, the power ring can supply power at any position. The power design architecture of the disclosure will be further described below.

First Embodiment

FIG.1Ais a top view of a power design architecture according to the first embodiment of the disclosure, andFIG.1Bis a side view of the power design architecture ofFIG.1A. InFIG.1A, the first substrate is omitted and not shown. Referring toFIG.1AandFIG.1Bat the same time, the power design architecture1of the embodiment includes a first substrate11, a power supply circuit12, a power wiring13, at least one chip14, a power ring15, and a first reference conductor16.

The first substrate11is a dielectric plate, and the first substrate11has a first side11aand a second side11bwhich are opposite to each other. The power wiring13, the chip14, and the power ring15are disposed on the first side11aof the first substrate11, and the first reference conductor16is disposed on the second side11bof the first substrate11.

The power wiring13disposed on the first side11aof the first substrate11is connected between the power supply circuit12and the power ring15, the power ring15is disposed around the chip14, and the power ring15is electrically connected to the chip14and the power wiring13. In the embodiment, the power ring15is a closed ring which is disposed around an outer side of the chip14, and the chip14is electrically connected to the power ring15through one of methods such as wire bonding, metal wiring, bumps or solder balls, but is not limited thereto. Other possible electrical connection methods are also applicable. In the embodiment, the first substrate11is provided with a via11cto electrically connect the chip14and the first reference conductor16by methods such as through-silicon via (TSV) or conductive post.

FIG.2A,FIG.2BandFIG.2Care possible implementations in which the power ring is a closed ring. Referring toFIG.2A,FIG.2B, andFIG.2Cat the same time, the shape of the power ring15which is a closed ring can be a quadrangle, a polygon, or a quadrangle with rounded corners, but is not limited to the shape shown in the drawings of the embodiment. The quadrangle is not limited to a square shown inFIG.2A, but also includes a rectangle. In addition, the polygon is not limited to an octagon shown inFIG.2B, but may also be a quadrilateral, a pentagon, a hexagon, etc. In addition, the shape of the closed ring is not limited to the shapes shown inFIG.2A,FIG.2B, andFIG.2C, but may also be circular or elliptical. It can be seen that the shape of the closed ring may be selected according to actual requirements of the arrangement and placement of the chips.

Based on the above, the first substrate11is provided with at least one via11cpenetrating the first side11aand the second side11b, and the first reference conductor16disposed on the second side11bof the first substrate11passes through the via11cto be electrically connected to the chip14. In the embodiment, an orthographic projection range of a portion of the power wiring13, the power ring15, and the chip14falls within an orthographic projection range of the first reference conductor16.

The above-mentioned power wiring13and the power ring15forms the first power transmission wiring, and the first reference conductor16is the second power transmission wiring. It is designed so that a length of the power wiring13is ¼ wavelength, and a length of the power ring15is an odd multiple of ½ wavelength.

Through the above-mentioned disposition, it can be seen that the power design architecture1of the embodiment can achieve the effect of low self-impedance at any position of the power ring15without using a bypass capacitor, thereby suppressing the voltage disturbance noise on a wiring, which is generated from the current drawn by the operation of the chip14. In addition, since the power ring15is disposed around the chip14, it is possible to supply power to any power pin of the chip14at any position of the power ring15nearby.

Second Embodiment

FIG.3Ais a top view of a power design architecture according to the second embodiment of the disclosure, andFIG.3Bis a side view of the power design architecture ofFIG.3A. InFIG.3A, the first substrate is omitted and not shown. Referring toFIG.3AandFIG.3Bat the same time, the embodiment is substantially the same as the aforementioned first embodiment, except that, compared with the first embodiment, the embodiment further includes a second reference conductor27. The second reference conductor27is positioned between the power ring15and the chip14.

In the embodiment, the second reference conductor27is disposed on the same side (that is, the first side11a) of the first substrate11as the chip14and the power ring15. Similarly, the chip14is electrically connected to the second reference conductor27and the power ring15by wire bonding. In addition, the second reference conductor27is electrically connected to the first reference conductor16through the via11c. Also, the second reference conductor27is a closed ring between the power ring15and the chip14.

Third Embodiment

FIG.4Ais a top view of a power design architecture according to the third embodiment of the disclosure, andFIG.4Bis a side view of the power design architecture ofFIG.4A. InFIG.4A, the first substrate is omitted and not shown. Referring toFIG.4AandFIG.4Bat the same time, the embodiment is substantially the same as the aforementioned second embodiment, except that the shape and the disposed position of the second reference conductor37of the embodiment are different from the shape and the disposed position of the second reference conductor27of the second embodiment.

The second reference conductor37in the embodiment is a C-shaped ring, and the power ring15is positioned between the second reference conductor37and the chip14.

Fourth Embodiment

FIG.5Ais a top view of a power design architecture according to the fourth embodiment of the disclosure, andFIG.5Bis a side view of the power design architecture ofFIG.5A. InFIG.5A, the first substrate is omitted and not shown. Referring toFIG.5AandFIG.5Bat the same time, in the fourth embodiment of the disclosure, the power design architecture4further includes a second substrate48and a second reference conductor47. The second substrate48is disposed between the first reference conductor16and the second reference conductor47, and the power ring15is disposed in the second substrate48.

The hierarchical disposition order from top to bottom is the chip14, the first substrate11, the first reference conductor16, the second substrate48, and the second reference conductor47. The power ring15is positioned in the second substrate48, and the chip14is electrically connected to the first reference conductor16, the power ring15, and the second reference conductor47through the plurality of vias11c.

Fifth Embodiment

The embodiment is substantially the same as the aforementioned first embodiment, except that the first reference conductor56of the embodiment is disposed on the same side of the first substrate11as the chip14and the power ring15.

FIG.6Ais a top view of a power design architecture according to the fifth embodiment of the disclosure, andFIG.6Bis a side view of the power design architecture ofFIG.6A. Referring toFIG.6AandFIG.6Bat the same time, in the embodiment, the first reference conductor56of the power design architecture5is disposed on the same side (that is, the first side11a) of the first substrate11as the chip14and the power ring15.

The above-mentioned first reference conductor56is a closed ring between the power ring15and the chip14, and the first reference conductor56is connected to a transmission wiring30on the second side11bof the first substrate11through the via11c.

Sixth Embodiment

The embodiment is substantially the same as the aforementioned fifth embodiment, except that the shape of the first reference conductor66of the embodiment is different from the shape of the first reference conductor56of the fifth embodiment.

FIG.7Ais a top view of a power design architecture according to the sixth embodiment of the disclosure, andFIG.7Bis a side view of the power design architecture ofFIG.7A. Referring toFIG.7AandFIG.7Bat the same time, in the embodiment, the first reference conductor66is a C-shaped ring, an opening of the C-shaped ring faces the power wiring13, and the power ring15is positioned between the chip14and the first reference conductor66.

Similarly, the first reference conductor66is connected to the transmission wiring30on the second side11bof the first substrate11through the via11c.

Seventh Embodiment

The embodiment is substantially the same as the aforementioned first embodiment, except that an orthographic projection range of the chip14and an orthographic projection range of the first reference conductor76in the embodiment do not overlap each other, and the first reference conductor76is connected to the transmission wiring30disposed on the second side11bof the first substrate11.

FIG.8Ais a top view of a power design architecture according to the seventh embodiment of the disclosure, andFIG.8Bis a side view of the power design architecture of FIG.8A. Referring toFIG.8AandFIG.8Bat the same time, in the embodiment, the first reference conductor76is a closed ring, and since the chip14and the first reference conductor76are positioned on different sides of the first substrate11, the chip14is electrically connected to the first reference conductor76through the via11cand the transmission wiring30.

Although the disposed position of the first reference conductor76shown inFIG.8Bis positioned between the chip14and the power ring15, it is not limited thereto. In an embodiment not illustrated here, the power ring15may also be disposed between the first reference conductor76and the chip14; that is, the first reference conductor76can also be disposed outermost.

Eighth Embodiment

The embodiment is substantially the same as the aforementioned first embodiment, except that, in the embodiment, there are a plurality of the power rings15, and each power ring15corresponds to a different frequency.

FIG.9Ais a top view of a power design architecture according to the eighth embodiment of the disclosure, andFIG.9Bis a side view of the power design architecture ofFIG.9A. InFIG.9A, the first substrate is omitted and not shown. Referring toFIG.9AandFIG.9Bat the same time, in the embodiment, the power rings15are disposed in plural. The plurality of power rings151,152, and153are all disposed on the first side11aof the first substrate11, and the power rings151,152, and153are electrically connected in series with each other. Although the embodiment illustrates three power rings as an example, the actual number of power rings is not limited thereto, and can be changed according to requirements.

Ninth Embodiment

The embodiment is substantially the same as the aforementioned eighth embodiment, except that, in the embodiment, some of the power rings15are disposed on the first side11aof the first substrate11, and some of the power rings15are disposed on the second side11bof the first substrate11.

FIG.10Ais a top view of a power design architecture according to the ninth embodiment of the disclosure, andFIG.10Bis a side view of the power design architecture ofFIG.10A. InFIG.10A, the first substrate is omitted and not shown. Referring toFIG.10AandFIG.10Bat the same time, in the embodiment, the chip14and some of the power rings15are disposed on the first side11aof the first substrate11, and some of the power rings15are disposed on the second side11bof the first substrate11. Each power ring15corresponds to a different frequency. The plurality of power rings15are electrically connected to each other by wires (not shown).

Tenth Embodiment

The embodiment is substantially the same as the aforementioned first embodiment, except that there are multiple chips14, and the number of power rings15corresponds to the number of chips14, and each chip14is correspondingly surrounded by one power ring15.

FIG.11is a schematic view of a power design architecture according to the tenth embodiment of the disclosure. InFIG.11, the first substrate is omitted and not shown. Referring toFIG.11, in the embodiment, each power ring15can provide different or the same operating frequency for different chips14to operate.

In the embodiment, the number of chips14provided is more than one. Similarly, although the above-mentioned other embodiments illustrate one chip as an example, the disclosure is not limited thereto. According to actual needs, a power ring can also be provided with a plurality of chips inside, and the disposition of other related components can be changed as required.

To sum up, in the power design architecture of the disclosure, by improving the connection path between the power supply and the chip in the package or the circuit board, the power supply can supply power to any power pin of the chip from any direction nearby. Moreover, without using bypass capacitors, low self-impedance is maintained at any position of the power ring, thereby suppressing the voltage disturbance on a wiring, which is generated from the current drawn by the operation of the chip.