System and method for performing scan test

A system for performing a scan test on an integrated circuit such as a System on a Chip (SoC) that may be packaged in different package types and with different features enabled includes a bypass-signal generator and a first scan-bypass circuit. The bypass-signal generator generates a first bypass signal based on chip package information. The first bypass signal indicates whether a first scan chain associated with a first non-common circuit block of the SoC is to be bypassed. The first scan chain is bypassed in response to the first bypass signal. By enabling partial scan testing based on package information, unintentional yield loss caused by a full scan test determining an SoC is faulty can be avoided.

BACKGROUND OF THE INVENTION

The present invention relates generally to scan testing and memory built-in self test (BIST) of integrated circuits and, more particularly, to a system and method for performing a scan test and a memory BIST test on integrated circuits using a scan bypass and a BIST bypass.

In recent years there have been tremendous advancements in the fields of semiconductor devices and electronic circuit integration. Currently, a single system-on-chip (SoC) with multiple package types or options is available. In small package embodiments, certain functional intellectual property (IP) blocks may be masked out depending on the selected package type. The masked out IP blocks may include combinational logic blocks and memory blocks.

FIG. 1is a schematic diagram illustrating scan testing using scan chain design and memory testing using BIST controllers in system that includes both scan and BIST test systems. That is, scan testing is performed on an integrated circuit (IC)10having a plurality of scan chains12using an automatic test equipment14(ATE), which employs a deterministic automatic test pattern generation (ATPG). The IC10also may have a plurality of BIST controllers15for testing memory modules (not shown) using the ATE14. The ATE14inputs compressed scan test patterns to the IC10. The IC10includes a decompressor16that receives and decompresses the scan test patterns and provides the decompressed test patterns to the scan chains 0-N12such that all of the flip-flops of the IC10, including those of unused functional circuit blocks, are tested for faults. The scan test response from the scan chains12are output to a compressor18, which compresses the scan test response and then provides the compressed scan test response to the ATE14where it is compared with expected scan responses to determine whether the IC10has any faults. Similarly, memory test patterns are generated and provided to the BIST controllers 0-M15for testing memory blocks of the IC10.

If any faults exist and are detected in the masked-out blocks, the IC10will be discarded. However, the IC10may still be operable for other package types in which the masked-out blocks are not necessary for functional operation. Thus, the full scan and full memory BIST tests may result in unintentional yield loss. It would be advantageous to be able to prevent unintentional yield loss due to faults only in the masked-out blocks.

DETAILED DESCRIPTION OF THE INVENTION

In one embodiment, the present invention provides a system for performing a scan test that includes a bypass-signal generator and a first scan bypass circuit. The bypass-signal generator generates a first bypass signal based on chip package information. The first bypass signal indicates whether a first scan chain associated with a first non-common IP block of the chip is to be bypassed during the scan test. The first scan bypass circuit bypasses the first scan chain in response to the first bypass signal.

In another embodiment, the present invention provides a system for performing a memory BIST test that includes a bypass-signal generator and a first BIST bypass circuit. The bypass-signal generator generates a first bypass signal based on chip package information. The first bypass signal indicates whether a first BIST controller associated with a first non-common memory block of the chip is to be bypassed during the memory BIST test. The first BIST bypass circuit bypasses the first BIST controller in response to the first bypass signal.

In an embodiment of the present invention, the system also includes a first scan-clock gating circuit that gates a scan clock for the first scan chain in response to the first bypass signal. In another embodiment of the present invention, the system further includes a first BIST-clock gating circuit that gates a BIST clock for the first BIST controller in response to the first bypass signal.

In another embodiment, the present invention provides a method for performing a scan test that includes generating a first bypass signal based on chip package information. The first bypass signal indicates whether a first scan chain associated with a first non-common IP block of the chip is to be bypassed, and bypassing the first scan chain in response to the first bypass signal.

In another embodiment, the present invention provides a method for performing a BIST test that includes generating a first bypass signal based on chip package information. The first bypass signal indicates whether a first BIST controller associated with a first non-common memory block of the chip is to be bypassed, and bypassing the first BIST controller in response to the first bypass signal.

In an embodiment of the present invention, the method includes gating a scan clock for the first scan chain in response to the first bypass signal. In another embodiment of the present invention, the method includes gating a BIST clock for the first BIST controller in response to the first bypass signal.

The present invention is advantageous in reducing yield loss unintentionally occurred in testing of circuit IPs and memory modules that are not to be used in a particular chip package configuration and also in reducing power consumption during testing.

Present electronic technology allows an integrated circuit (IC) such as a SoC to be packaged in any of a variety of package options. The package options may be a multi-chip package or a single-chip package. According to the present invention, the IC or SoC is package-aware and programmable. It should be noted that the terms SoC, chip, die, and IC are used interchangeably in the specification. The terminology used in the specification is only used for clearly illustrating and describing the embodiments of the present invention, but not for limiting the essence of the present invention.

An integrated circuit such as a SoC that may be packaged in various packages, for example 116 pin BGA vs. 144 pin BGA, includes common IP blocks and non-common IP blocks. The common IP blocks are those that are used by the SoC even though assembled in different packages, while the non-common IP blocks are those only used in one or more certain ones of the package types. An IP block may be a functional circuit block, a memory block, or a combination of a functional circuit block and memory block. When performing a scan test on the SoC of a selected package type, if all the scan chains, including those of any unused functional circuit blocks, are scanned, scanning the unused functional circuit blocks causes unnecessary power consumption and takes additional time. Similarly, when performing a BIST test on a SoC of a selected package type, if all the BIST controllers are tested, testing the unused memory blocks causes unnecessary power and time consumption. More importantly, if defects are found only in the unused IP blocks, the SoC may still be operable for some package types. For example, for a chip supporting four (4) package options, such as a 121-pin BGA, 144-pin BGA, 196-pin BGA, and 256-pin BGA, the Test and Debug block, i.e., JTAG, is a common IP block, while the double data rate-synchronous dynamic random access memory (DDR-SDRAM), liquid crystal display controller (LCDC), NAND flash controller (NFC), floating point processing unit (FPU), USB2OTG, etc., are non-common IP blocks.

If the chip is to be assembled into a 144-pin BGA package the non-common IP blocks DDR, LCDC, NFC and USB2OTG may be non-functional blocks and these non-functional blocks can use up about 25% of the total sea of gate (SOG) count of the chip. Thus, if time, cost and effort to discover defects in these blocks during the scan test are saved, approximately 25% of the scan test yield may be improved. Therefore, performing a full scan test and a full memory BIST test on a SoC with multiple package options may introduce an unintentional yield loss.

Embodiments of the present invention solve the above technical problem. The present invention uses chip package information stored in a register on the chip to automatically bypass scan chains for functional circuit blocks and memory BIST controllers for memory blocks that will non-functional or non-operational for that certain package, and thus yield recovery is possible. Further, as described in more detail below, in one embodiment, the present invention uses the chip package information to automatically gate the scan clocks and BIST clocks to those unused IP blocks to decrease the power dissipation during scan test and memory BIST.

One embodiment of the present invention provides a system for performing a scan test. The system comprises a bypass-signal generator and a first scan bypass circuit. The bypass-signal generator generates a first bypass signal based on chip package information, the first bypass signal indicating whether a first scan chain associated with a first non-common IP block of the chip is to be bypassed. The first scan bypass circuit bypasses the first scan chain in response to the first bypass signal. In an embodiment of the present invention, the system further comprises a second scan bypass circuit. The bypass-signal generator further generates a second bypass signal based on the package information, the second bypass signal indicating whether a second scan chain associated with a second non-common IP block is to be bypassed. The second scan bypass circuit bypasses the second scan chain in response to the second bypass signal.

According to one embodiment of the present invention, the system for performing a scan test further has a first scan-clock gate circuit gating a scan clock for the first scan chain in response to the first bypass signal. According to another embodiment of the present invention, the system further comprises a second scan-clock gate circuit gating a scan clock for the second scan chain in response to the second bypass signal.

In an embodiment of the present invention, the bypass-signal generator includes a lookup table of the chip receiving the package information. In another embodiment of the present invention, the first scan bypass circuit includes a first 2-to-1 multiplexer and the second scan bypass circuit includes a second 2-to-1 multiplexer. The first bypass signal and second bypass signal are provided to the first 2-to-1 multiplexer and second 2-to-1 multiplexer as a selection signal respectively. In a further embodiment of the present invention, the system further includes an input receiving an enable signal to allow the system to perform the scan bypass test.

In addition, one embodiment of the present invention provides a method for performing a scan test, which comprises generating a first bypass signal based on package information of the chip, the first bypass signal indicating whether a first scan chain associated with a first non-common IP block of the chip is to be bypassed, and bypassing the first scan chain in response to the first bypass signal. In one embodiment of the present invention, the method further comprises generating a second bypass signal based on the package information, the second bypass signal indicating whether a second scan chain associated with a second non-common IP block of the chip is to be bypassed, and bypassing the second scan chain in response to the second bypass signal

According to an embodiment of the present invention, the method for performing a scan test further includes gating a scan clock for the first scan chain in response to the first bypass signal. In another embodiment of the present invention, the method further comprises gating a scan clock for the second scan chain in response to the second bypass signal.

In an embodiment of the present invention, the first and second bypass signals are generated by a lookup table of the chip. Bypassing the first scan chain is performed by a first 2-to-1 multiplexer and bypassing the second scan chain is performed by a second 2-to-1 multiplexer. The first bypass signal and second bypass signal are provided to the first 2-to-1 multiplexer and second 2-to-1 multiplexer as a selection signal respectively. In another embodiment of the present invention, the method further comprises receiving an enable signal to perform the scan bypass test.

In another embodiment, the present invention provides a system for performing a memory BIST test that includes a bypass-signal generator and a first BIST bypass circuit. The bypass-signal generator generates a first bypass signal based on chip package information. The first bypass signal indicates whether a first BIST controller associated with a first non-common memory block of the chip is to be bypassed during BIST test. The first BIST bypass circuit bypasses the first BIST controller in response to the first bypass signal. In an embodiment of the present invention, the system further comprises a second BIST bypass circuit. The bypass-signal generator further generates a second bypass signal based on the package information, the second bypass signal indicating whether a second BIST controller associated with a second non-common memory block is to be bypassed. The second BIST bypass circuit bypasses the second BIST controller in response to the second bypass signal.

According to one embodiment of the present invention, the system for performing a BIST test further has a first BIST-clock gate circuit gating a BIST clock for the first BIST controller in response to the first bypass signal. According to another embodiment of the present invention, the system further comprises a second BIST-clock gate circuit gating a BIST clock for the second BIST controller in response to the second bypass signal.

Referring now toFIG. 2, a schematic block diagram illustrating a system20for performing scan test and memory BIST on an IC or SoC22in accordance with an embodiment of the present invention is shown. The system20includes an ATE14that generates and transmits test patterns to the IC22, and receives test responses from the IC22, as is known in the art. The IC22may include a decompressor16for decompressing compressed scan data in and a compressor18for compressing scan test data prior to transmitting the scan test data to the ATE14.

According to the present invention, the IC22also includes a bypass-signal generator24, a plurality of scan-bypass circuits26(only one is shown), a plurality of BIST-bypass circuits27(only one is shown), a plurality of scan chains28, a plurality of BIST controllers29(only the one associated with the BIST-bypass circuit27is shown), a plurality of test clock gating circuits30(only one associated with scan chain A and BIST controller A is shown), additional scan chains32, and additional BIST controllers33.

For the scan testing, the scan data from the ATE14preferably comprises compressed scan data, as is known in the art, which is received by the decompressor16. For the BIST, however, the BIST data from the ATE14depends less on compression/decompression and so can be directly fed to and received from the BIST controller29and additional BIST controllers33. The compressed scan data then is decompressed and input to the scan chains32of the various functional circuit blocks (i.e., the common and non-common functional circuit blocks for a selected package type) to check for faults, as is known in the art. For example, in this embodiment of the present invention, the additional scan chains32and additional BIST controllers33are associated with common IP blocks, while the scan chain A28and BIST controller A29are associated with a non-common IP block A (i.e., functional circuit block A and memory A). Thereafter, corresponding scan-out patterns are received by the compressor18, which compresses the scan out patterns and provides the compressed response to the ATE14where the compressed data is compared with expected scan responses to determine whether the IC22has any faults. On the other hand, the BIST output data may be compared directly with expected responses by the ATE14without going through compression and decompression processes.

However, regarding the scan chains associated with the non-common functional circuit blocks, such as the scan chain A28, a decompressed scan test pattern is provided to the scan-bypass circuit26based on a first bypass signal generated by the bypass-signal generator24. Similarly, the BIST controllers associated with the non-common memory blocks, such as the BIST controller A29, receive a test pattern from the ATE14and provide the test pattern to the BIST-bypass circuit27based on a second bypass signal generated by the bypass-signal generator24. The bypass-signal generator24generates a plurality of bypass signals for the non-common IP blocks based on chip package information stored in the IC22, if the IC22permits scan-bypass and BIST-bypass, which can programmed into the IC22. As an alternative to storing the chip package information in a register in the IC22, the chip package information could be transmitted to the bypass-signal generator24from outside of the IC22. Preferably the bypass-signal generator24also receives an enable signal from an input pin of the IC22to enable generation of bypass signals.

Each bypass signal indicates whether a scan chain and/or BIST controller associated with a non-common IP block is to be bypassed. For a certain selected package type of the IC22, if a non-common IP block is not used, the associated bypass signal indicates that the non-common IP block is to be bypassed (not tested); otherwise, the associated bypass signal indicates that the non-common IP block is not to be bypassed, and therefore, the non-common IP block undergoes scan test and/or BIST.

In a scan bypass test, the plurality of scan-bypass circuits26bypass the associated scan chains in response to the bypass signals generated by the bypass-signal generator24. For example, for the scan chain A28, if the first bypass signal indicates that the non-common functional circuit block A is to be bypassed, the scan-bypass circuit26bypasses the scan chain A28so that the response of scan chain A will not be compared. Thus any defect in non-common functional circuit block A that could be detected by scan testing will be ignored; otherwise, the scan-bypass circuit26does not cause the scan chain A28bypassed. Alternatively, the scan-bypass circuit A26can simply pass the uncompressed scan data back to the compressor18without rippling the scan data through any of the latches so that there will not be a miscompare indicating a fault.

Similarly, in a memory BIST test, if a non-common memory block is to be bypassed (not tested because it is non-functional), the bypass signal generator24generates the second bypass enable signal and provides it to the BIST bypass circuit A27. Once enabled, the BIST bypass circuit A27bypasses the associated BIST controllers such that such BIST data is not used to test that memory block so there will not later be a miscompare and therefore, the unused memory block will not be determined as faulty. For example, for the BIST controller A29, if the second bypass signal indicates that a non-common memory block A is to be bypassed, the BIST bypass circuit27bypasses the BIST controller A29so that the corresponding memories will not be tested for faults; otherwise, the BIST bypass circuit27does not cause the BIST controller A29to be bypassed.

In addition, to avoid unnecessary power consumption by the bypassed scan chains, the test clock gating circuit30gates the scan clocks for the bypassed scan chains and BIST clocks for the bypassed BIST controllers in response to the bypass signals. That is, the scan clocks for the scan chains to be bypassed and the BIST clocks for the BIST controllers to be bypassed are disabled so that the latches and gates in the bypassed IP blocks are not toggled.

FIG. 3is a schematic diagram showing a logic structure of the bypass-signal generator24, an exemplary scan-bypass circuit26, an exemplary BIST bypass circuit27, and an exemplary test clock gating circuit30in accordance with an embodiment of the present invention. The same or similar logic structures can be applied to other scan-bypass circuits26, other BIST-bypassed circuits27, and other test clock gating circuits30for scan chains and/or BIST controllers associated with non-common IP blocks in the IC22.

Referring now toFIG. 3, in one embodiment of the present invention, the bypass-signal generator24includes a lookup table (LUT)34. The LUT34, in response to received chip package information and a bypass-enable signal, generates a plurality of bypass signals (A-A, B-B, C-C . . . N-N) for the plurality of scan chains associated with the non-common functional circuit blocks and the plurality of BIST controllers associated with the non-common memory blocks. For example, if the system20sets the bypass-enable signal to a true state, the bypass-signal generator24generates a bypass signal A-A for IP block A, a bypass signal B-B for IP block B, and so on, based on the chip package type information. Each bypass signal has a true or false state to indicate whether the associated scan chain and/or BIST controllers are to be bypassed. An embodiment of the true or false state of the lookup table (LUT)34is shown inFIG. 4which will be described later in more details.

The plurality of bypass signals is input to a corresponding plurality of scan-bypass circuits26and to a corresponding plurality of BIST-bypass circuits27. For the scan test, according to one embodiment of the present invention, each scan-bypass circuit26includes a multiplexer36, e.g., a 2-to-1 multiplexer. A bypass signal is used as a selection signal of the multiplexer36. For each non-common functional circuit block, the decompressed scan test pattern received from the decompressor16is provided to one input of the corresponding multiplexer36and to the scan input of its associated scan chain. The scan output of the scan chain is provided to another input of the multiplexer36. Therefore, the scan-bypass circuit26can selectively output the scan-out test pattern in response to the bypass signal, which may be the decompressed scan input, that is, the scan chain is to be bypassed; or the scanned output of the scan chain, that is, the pattern is rippled through the scan chain and not bypassed.

According to one embodiment of the present invention, for the selected chip package, if the package information indicates that a non-common IP block is not used, the bypass signal associated with the non-common functional circuit block is true. Taking the non-common IP block A shown inFIG. 3for example, its associated bypass signal A-A is provided to the 2-to-1 multiplexer36to serve as a selection signal. The corresponding decompressed scan-input A is provided to a first input of the 2-to-1 multiplexer36and to the scan input of the scan chain A28. The scan-out A output from the scan chain A28is provided to a second input of the 2-to-1 multiplexer36. When the bypass signal A-A is true, the scan-bypass circuit26outputs the decompressed scan-input A. That is, the system20bypasses the scan chain A28. When the bypass signal A-A is false, the scan-bypass circuit26outputs the scanned test pattern A of the scan chain A28. That is, the system20scans the scan chain A, rather than bypassing it.

In another embodiment of the present invention, for a BIST, bypassing the BIST controller is performed by a pair of OR gate35and AND gate37through an inverter39, wherein the bypass signal is coupled to the respective input of the pair of OR gate and AND gate as a selection signal. Each of the plurality of memory BIST controller A29has two outputs of “A BIST-done” and “A BIST-fail”. Asserting “A BIST-done” to a logic high (or true) state and “A BIST-fail” to a logic low (or false) state by the BIST controller A29indicates the corresponding memory module is in a good condition. When the bypass signal A-A is true, the output of the inverter39is false, and the pair of OR gate and AND gate outputs the same values on “BIST-out A” bypassing the BIST controller A29. That is the BIST controller is in don't-care condition regardless whether the memory has problem or not.

In an embodiment of the present invention, the plurality of bypass signals is input to the test clock gating circuits30to shut down the scan clocks of those bypassed scan chains and/or the BIST clocks of those bypassed BIST controllers. According to one embodiment of the present invention, each test clock gating circuit30includes a NAND gate or an integrated clock gating cell (not shown). The test clock gating circuit30receives a scan clock signal, a BIST clock signal and an associated bypass signal from the bypass-signal generator24, which is used as a gated enable signal. The outputs of the test clock gating circuit are the gated/or ungated scan clocks and/or BIST clocks in response to the bypass signal.

Taking the non-common IP block A shown inFIG. 3for example, the bypass signal A-A is provided to the test clock gating circuit30to serve as an gating enable signal. When the bypass signal A-A is true, the scan clock and BIST clock from test clock gating circuit30will be gated. The test clock gating circuit A30outputs gated scan clock A for scan chain A and gated BIST clock A for BIST controller A. When the bypass signal A-A is false, the scan clock and BIST clock from the test clock gating circuit30will not be gated. The test clock gating circuit A30outputs ungated scan clock A for scan chain A and ungated BIST clock A for BIST controller A.

FIG. 4is a truth table illustrating a logic decoding table40to determine values of bypass signals in response to package information according to an embodiment of the present invention. As shown inFIG. 4, each bypass signal has a true (a high logic state or “1”) or false (a low logic state or “0”) state to indicate whether the associated scan chain and/or BIST controller is to be bypassed. In one embodiment, the package information can be encoded by four digits of binary numbers with each digit having two logic states—true or false. In one particular package requirement where all IP blocks are used, the package information is encoded with all false or zero (0000), as indicated in the decoding table40, indicating none of the IP blocks will be bypassed. In another particular package requirement where IP block C-C are not used, the package information is encoded with 0001 indicating the decoding logic will set the bypass signal C-C to true and other bypass signals remain at zeros, that is, the scan chain C and/or BIST controller C is to be bypassed. In yet another particular package requirement where all the non-common IP blocks are not used, the package information is encoded with all true or ones (1111), as shown in the last row of the decoding table40, indicating all the non-common circuit IP blocks will be bypassed. In other package requirements where a certain number of the non-common circuit IP blocks are not used, a decoding logic can be constructed to generate a true (or “1”) state in the corresponding outputs of the bypass signal locations.

FIG. 5is a flow chart illustrating a method for performing a scan test and/or a memory BIST in accordance with an embodiment of the present invention. Though the flow chart is explained below in conjunction withFIGS. 2,3and4, the method for performing the scan test and/or a memory BIST may be implemented by computer software in other embodiments. Furthermore, the sequence of steps is not limited by the number of the steps. Accordingly, the flow chart is only used to clearly illustrate and describe the embodiments of the present invention, but does not limit the essence of the present invention.

Referring toFIG. 5, at step50, the IC or SoC22with multiple package options is reset so as to enter a test mode. Note, as previously discussed, each package option may be a multi-chip package or a single-chip package. The common IP blocks of the IC22are scanned and BIST tested in a current test mode, however, the non-common IP blocks are scanned using a scan bypass test and/or a BIST bypass test as follows.

At step52, a plurality of bypass signals are generated by the bypass-signal generator24(e.g., using the LUT34), and each bypass signal is sent to an associated one of the plurality of scan chains and/or the plurality of BIST controllers based on received chip package information and the bypass-enable signal. That is, for a first scan chain and/or BIST controller, e.g. scan chain A and BIST controller A associated with a first non-common IP block, e.g., IP block A, a first bypass signal, e.g., bypass signal A-A is generated, for a second scan chain and/or BIST controller, e.g., scan chain B and BIST controller B associated with a second non-common IP block, e.g., IP block B, a second bypass signal e.g., bypass signal B-B is produced, and so on. For the selected chip package type, if the package information indicates a non-common IP block is not used, the bypass signal for the non-common IP block is set at a first state, for example, true; otherwise, the bypass signal is set at a second state, false.

Continuing with step52, in an embodiment of the present invention, the method further includes providing the plurality of bypass signals from the bypass-signal generator24as input to the plurality of scan-clock and BIST-clock gating circuits30to shut down the scan clocks and BIST clocks for those scan chains and BIST controllers that are bypassed. For example, the first bypass signal A-A is provided to the first scan-clock gating circuit A30to act as an gating enable signal. When the bypass signal A-A is true, the scan clock of the non-common IP block A is gated in test clock gating circuit30. When the bypass signal A-A is false, the scan clock pass through the test clock gating circuit30, i.e. the scan clock of the non-common IP block A is not gated. The operation to shut down the BIST clocks of the unused non-common BIST controllers is essentially the same as that shutting down the scan clocks.

At step54, compressed scan test patterns from the ATE14are decompressed by the decompressor16, and the decompressed scan test patterns associated with the non-common functional circuit blocks are output to the scan-bypass circuit26, while those associated with the common functional circuit blocks are output to their respective scan chains32(e.g., chain 0 and chain 1). In addition, the BIST test patterns from the ATE14associated with non-common memory blocks are directly sent to the BIST-bypass circuit26for BIST bypass test, while those associated with the common memory blocks are output to their respective BIST controllers.

At step56, the scan-bypass test is performed by the plurality of scan-bypass circuits26and BIST bypass test of the non-common IP blocks is performed by the plurality of BIST-bypass circuit27based on the received bypass signals. Specifically, each bypass signal is used as a selection signal of the associated scan-bypass circuit26and BIST-bypass circuit27of one non-common IP block. For example, the first bypass signal is provided to a first scan-bypass circuit26(e.g., a 2-to-1 multiplexer36) to serve as a selection signal, the second bypass signal is provided to a second scan-bypass circuit26to serve as a selection signal for another 2-1 multiplexer36, and so on. Regarding the scan chain A28inFIG. 3, when the bypass signal A-A is true, the decompressed scan test pattern A is output by the scan-bypass circuit A26, that is, the scan chain A is to be bypassed. When the bypass signal A-A is false, the scan output of the scan chain A28is output by the scan-bypass circuit A26. That is, the scan chain A is scanned, rather than bypassed. For BIST bypass test, when the bypass signal A-A is true, the BIST-done signal output from BIST bypass circuit27will be always high and the BIST-fail output will be always zero. That is, the BIST controller A will be bypassed or not checked. When the bypass signal A-A is false, BIST controller A will be tested as normal, rather than bypassed.

At step58, the compressor18compresses all of the scan-out test patterns shifted from the common functional circuit blocks and non-common functional circuit blocks and then outputs the compressed scan-out test patterns to the ATE14. Similarly, the BIST controllers29,33will output BIST test results patterns to the ATE14. In other embodiments, the BIST test patterns and test responses can be decompressed/compressed in a way similar to the scan test patterns.

By using the package information to automatically bypass the scan chains and/or the BIST controllers for the non-common IP blocks that are not used in a certain package, the present invention can achieve a yield recovery. In addition, the present invention uses the package information to automatically gate the scan clocks and BIST clocks of the unused IP blocks and reduces power dissipation during the scan test.

While various embodiments of the present invention have been illustrated and described, it will be clear that the present invention is not limited to these embodiments. Numerous modifications, changes, variations, substitutions, and equivalents will be apparent to those skilled in the art, without departing from the spirit and scope of the present invention, as described in the claims.