Re-based integrated photonic and electronic layered structures

Systems and methods describe growing RE-based integrated photonic and electronic layered structures on a single substrate. The layered structure comprises a substrate, an epi-twist rare earth oxide layer over a first region of the substrate, and a rare earth pnictide layer over a second region of the substrate, wherein the first region and the second region are non-overlapping.

BACKGROUND OF THE INVENTION

Photonic devices are components for creating, manipulating and/or detecting light. A photonic device can include a laser diode, a light-emitting diode, solar and photovoltaic cells, displays and/or optical amplifiers. Conventionally, photonic devices and electronic devices are formed separately, and may be combined into a circuit if needed. The separate individual manufacturing processes can be costly, and the resulting photonic devices and electronic devices may each consume separate circuit areas.

In addition, for semiconductor manufacturing, lattice match between different layers of different materials can often be an issue, as lattice mismatch between layers can sometimes lead to increased strains among the layered structure. Traditionally, SrTiO3-buffered Si of an orientation of <100> is traditionally used as a starting template for barium (Ba) based perovskite materials, but lattice mismatch often occurs, which impairs the performance of the semiconductor layers. Recently rare earth oxide (REO) bulk substrates of a crystal orientation of <110> are used as a good option for the epitaxy of Ba-based perovskite materials, because the REO substrate is usually lattice matched with Ba-based perovskite. A bulk single crystal lattice matched REO substrate, however, usually has a limited size, e.g., up to 32 mm in diameter, which highly restricts the size of perovskite that can be deposited over the lattice matched REO substrate as well.

SUMMARY

Systems and methods describe growing RE-based integrated photonic and electronic layered structures on a single substrate. The layered structure comprises a substrate, an epi-twist rare earth oxide layer over a first region of the substrate, and a rare earth pnictide layer over a second region of the substrate, wherein the first region and the second region are non-overlapping.

In some embodiments, the substrate is a silicon substrate having a crystal orientation of (100), wherein the epi-twist rare earth oxide layer has a crystal orientation of (110), and wherein the rare earth pnictide layer has a crystal orientation of (100). In some embodiments, the layered structure further comprises an interface layer over a third region of the substrate, wherein the third region is separate from the first region and the second region, wherein the interface layer is composed of silicon dioxide or a wafer bonding material, a silicon layer over the interface layer.

In some embodiments, the silicon layer has a crystal orientation of (111), and the layered structure further comprises a rare earth oxide layer having a crystal orientation of (111) over the silicon layer.

In some embodiments, the silicon layer has a crystal orientation of (100), and the layered structure further comprises another rare earth pnictide having a crystal orientation of (100) over the silicon layer. In some embodiments, the substrate is a silicon substrate having a crystal orientation of (111), and the layered structure further comprises a stack of an interface layer and a silicon layer having a crystal orientation of (100) over the interface layer, wherein the stack covers the first region and the second region, and is between the substrate, and the epi-twist rare earth oxide layer and the rare earth pnictide layer, and a rare earth oxide layer having a crystal orientation of (111) over a third region of the substrate that is separate from the first region or the second region.

In some embodiments, either of the substrate and the silicon layer includes a porous silicon portion. In some embodiments, either of the substrate and the silicon layer comprises a first portion of a first electrical doping type, and a second portion of a second electrical doping type, and wherein the first portion and the second portion of different electrical doping types are generated by adding an additional silicon epitaxial layer to the substrate or the silicon layer to change electrical doping of the substrate or the silicon layer.

In some embodiments, the substrate is a germanium substrate having a crystal orientation of (100). In some embodiments, the substrate is a silicon substrate having a crystal orientation of (100), and the layered structure further comprises an interface layer over a third region of the substrate, wherein the third region is separate from the first region and the second region, and a germanium layer having a crystal orientation of (100) over the interface layer. In some embodiments, locations of the epi-twist rare earth oxide layer, the rare earth pnictide layer and the rare earth oxide layer are interchangeable. In some embodiments, another stack of another interface layer and another silicon layer, wherein the other stack is directly over the silicon layer and aligns with one of the first region and the second region, and wherein one of the epi-twist rare earth oxide layer, the rare earth pnictide layer and the rare earth oxide layer is over the other silicon layer.

In some embodiments, the layered structure further comprises a combination of devices selected from a group of III-V devices, III-N devices, oxide photonic devices, electronic devices and radio frequency devices, over an upper surface of one or more of the epi-twist rare earth oxide layer, the rare earth pnictide layer and the rare earth oxide layer. In some embodiments, the combination of devices further comprises one or more of: a perovskite oxide, a BaTiO3based modulator, an InP based emitter, a III-N High-electron-mobility transistor, a polar, non-polar or semi-polar III-N device, an epitaxial metal, and a ScxAl1-xN filter. In some embodiments, the substrate is a p-type silicon substrate having a portion of n-type silicon that aligns with the first region at an upper surface of the substrate, and the layered structure further comprises an InP based emitter over the rare earth pnictide layer, and wherein the epi-twist rare earth oxide layer is composed of Gd1-yEryO3, and wherein Er atoms at the epi-twist rare earth oxide layer are configured to convert a first wave length of light waves emitted from the InP based emitter to a second wave length that is detectable by the portion of n-type silicon.

In some embodiments, the substrate comprises a first porous portion underneath and aligning with the n-type silicon portion, wherein the first porous portion forms a first distributed Bragg reflector that passes the second wave length, and a second porous portion underneath and aligning with the first porous portion, wherein the second porous portion forms a second distributed Bragg reflector that passes the first wave length.

In some embodiments, the layered structure further comprises a photonic device over the epi-twist rare earth oxide layer, and an electronic device over the rare earth pnictide layer. In some embodiments, the photonic device is a stack of a first epitaxial metal, a modulator, and a second epitaxial metal over the modulator, and the electronic device is a III-V electronic field effect transistor.

In some aspects, a layered structure, comprises a substrate, an epi-twist rare earth oxide layer over the substrate, a stack of a first epitaxial metal, a layer forming a modulated optical path, and a second epitaxial metal over the layer, wherein the stack is over a first region on the epi-twist rare earth oxide layer, and a waveguide over a second region on the epi-twist rare earth oxide layer.

In some embodiments, the layered structure further comprises cladding material wrapping at least one side of the epi-twist rare earth oxide layer, the stack and the waveguide, wherein a first refractive index corresponding to the layer forming the modulated optical path or the wave guide is greater than a second refractive index corresponding to the cladding material.

DETAILED DESCRIPTION

Embodiments described herein provide a layered structure that allows mixed photonic and electronic device to be integrated on the same platform. For example, the layered structure uses a mixture of rare earth oxide (REO) and rare earth pnictide on a silicon-on-insulator (SOI) substrate formed by a silicon layer of <111> over another silicon layer of <100>, and the SOI wafers containing the two orientations are used to generate discrete photonic/electronic structures that are spatially separated on the wafer. In this way, mixed photonic and electronic devices can be integrated into the structure sharing a common epitaxial platform.

Embodiments described herein also provide an epitwist crystalline rare earth oxide (cREO) based template grown on a silicon wafer, for growing perovskites. Traditionally, perovskites may be grown on a silicon <100> substrate with a SrTiO3 buffer, but the STO buffer may not be lattice matched with the perovskite. Or the perovskite may be grown on an REO substrate in the form of (M1M2)2O3cut in a <110> orientation where M1, M2 are rare earths chosen to lattice match to a specific perovskite oxide, but the REO substrate is usually restricted in size. To provide a stable and lattice-matched buffer for perovskite growth on a silicon substrate, epitwist technology can be used to result in a cREO layer on a Si substrate of <100>, and the cREO layer is grown in a <110> direction. Using the cREO layer on Si <100> in a <110> direction can reduce the mismatch problem for perovskite growth.

FIG. 1provides an example of layered structure100illustrating mixed photonic and electronic structures that share a common epitaxial platform, according to an exemplary embodiment described herein. Structure100includes a silicon substrate102of an orientation of <100>, over which two non-overlapping layered stacks are grown at different regions. For example, at a first region, an epi-twist rare earth oxide (REO) <110> layer104is grown over the Si substrate102.

At a second region which is non-overlapping with the first region on the silicon substrate102, a rare earth (RE) pnictide layer <100>106may be grown. The epi-twist REO layer104and RE-pnictide layer106may be used as a base to build various devices on the on-overlapping regions respectively. In some embodiments, the second region may be spatially separated from the first region. Or alternatively, the second region may border the first region.

FIG. 2provides an example of layered structure200illustrating another non-overlapping device layer on the substrate described inFIG. 1, according to an exemplary embodiment described herein. Layered structure200depicted inFIG. 2is similar to layered structure100ofFIG. 1, except that layered structure200has an additional non-overlapping layered stack at a third region of the silicon substrate102. In some embodiments, at the third region of the substrate102, an SOI substrate is formed on the silicon substrate102. In some embodiments, the SOI substrate, is grown over an insulator layer202. In such embodiments, the insulator layer202may be composed of silicon oxide (SiO2). A silicon layer204having an orientation <111> may be grown over the layer202. In some embodiments, the insulator layer202may be p-type Si, which can be used as an optical/wave guide. In some embodiments, a portion of the silicon substrate102and/or the silicon layer204may be converted to porous silicon portion(s) and may thus form a porous-Si-to-porous-Si bond. In some embodiments, the porous portions from the silicon layer102of <100> and the silicon layer204of <111> may contribute to form a single porous silicon wafer202. In this way, a silicon wafer that is composed of Si <111>-porous Si—Si <100> can be formed. This silicon wafer may be used to grow epaxial layers discussed throughout the application. A cREO layer206is grown over the silicon layer204. The growth of three non-overlapping device layers at different regions of the silicon substrate102is for exemplary purposes only. In some implementations, any number of non-overlapping layers at a number of non-overlapping regions may be grown over the silicon substrate102. For example, in some embodiments, less than three non-overlapping layered structures may be grown over silicon substrate102, and in some other embodiments, more than three non-overlapping layered structures may be grown over the silicon substrate102.

FIG. 3provides an example of layered structure300illustrating non-overlapping device layers on the substrate described inFIG. 1, according to an exemplary embodiment described herein. Layered structure300is similar to layered structure200, except that in layered structure300, the silicon layer304grown over the insulator layer202may have an orientation of <100> instead of <111> as depicted inFIG. 2. A second RE-pnictide layer304may be grown over the silicon layer302. The second RE-pnictide layer304may be similar or different from the RE-pnictide layer106originally present on the silicon substrate102.

FIG. 4provides an example of layered structure400illustrating non-overlapping device layers on a substrate, according to an exemplary embodiment described herein. Structure400includes a silicon substrate102of an orientation of <111> instead of the <100> orientation as depicted inFIGS. 1-3. In layered structure400, over the silicon substrate402, two non-overlapping layered stacks are grown at different regions. For example, at a first region, a cREO layer406having an orientation of <111> is grown over the substrate402.

At a second region which is non-overlapping with the first region on the silicon substrate102, the insulator layer202(as described inFIGS. 2-3) is grown over the substrate402. As described inFIG. 3, silicon layer302having orientation of <100> may be grown over the insulator layer202. The surface of the silicon layer302may further be divided into multiple non-overlapping regions. At a first non-overlapping layer of the silicon layer302, a RE-pnictide layer304may be grown over the silicon layer302. Similarly, at a second non-overlapping region of the silicon layer302, an epi-twist REO layer404may be grown. The combination of layers302,304and406is similar to the layered structure100as described in106.

FIG. 5provides an example of layered structure500illustrating non-overlapping device layers on the substrate described inFIG. 1, according to an exemplary embodiment described herein. Layered structure500is similar to the layered structure200described inFIG. 2, except that silicon layer204is modified using porous silicon process to enhance the electric or acoustic application of the device. InFIG. 5, the modification of a portion of the silicon layer204results in the porous silicon layer502between the silicon layer204and the cREO layer206. The modification of silicon layer204may be similar or different from the modification of insulator layer202performed. The insulator layer202is described in further detail inFIG. 2.

Silicon substrate102of layered structure500ofFIG. 5may also include alternating layers of silicon and porous silicon layers504within the silicon substrate102. These layers504, while within the substrate, may be aligned with any of the three non-overlapping regions over which any of the three-layered structures are grown.

FIG. 6provides an example of layered structure600illustrating non-overlapping device layers on a substrate, according to an exemplary embodiment described herein. Layered structure600is similar to layered structure500except that layer structure600does not include the alternating silicon and porous silicon layers504. In layered structure600, the electrical doping concentration of each of silicon layers102and204may be modified using additional silicon. In some embodiments, additional silicon may be used to modify the electrical doping of silicon substrate102to a p-type substrate. N-type silicon layer604having orientation <111> may be inserted in the substrate102. In some embodiments, the electrical concentration of the silicon substrate102and n-type silicon layer604may be reversed. Similar to silicon substrate102, silicon layer of200may be converted to a p-type layer using additional silicon. N-type silicon layer602may be grown over the modified p-type silicon layer204. In some embodiments, the electrical doping of silicon layers204and602may be revered, and a p-type silicon layer may be grown over an n-type silicon layer.

FIG. 7provides an example of layered structures illustrating non-overlapping device layers on a substrate, according to an exemplary embodiment described herein. Layered structure702inFIG. 7is similar to the layered structure300ofFIG. 3, except that in layered structure700, the silicon substrate102ofFIG. 3is replaced with a germanium substrate706that has an orientation of <100>. The change in the substrate may lead to a change in the composition of the insulator layer202grown in a first region of the germanium substrate706. In some embodiments, insulator layer202may be composed of porous Si, or Ge, or a combination of porous Si and Ge. In some embodiments, the insulator layer202may be composed of SiO2as described inFIG. 2. Silicon layer302having orientation <100> may be grown over the insulator layer202. The silicon layer302may act as a base over which an epi-twist REO layer404over the silicon layer302. Layered structure702allows for a silicon layer302over a germanium substrate706. In a second non-overlapping region of the germanium substrate706, a RE-pnictide layer106may be grown as shown inFIG. 1.

Layered structure704is also similar to the layered structure300ofFIG. 3, except that the silicon layer302in layered structure300is replaced with a germanium layer708with an orientation of <100>. In this embodiment, a germanium layer may be grown over a silicon substrate, which allows for a variety of substrates to grow electronic and acoustic devices.

FIG. 8provides an example of layered structures illustrating non-overlapping device layers on a substrate, according to an exemplary embodiment described herein.FIG. 8allows for growth of two substrate layers (silicon, or germanium of different orientations) over a substrate layer. In some embodiments, there is a RE alloy available for discrete epitaxial integration on any of Si<100>, Si<111>, or Ge<100>. Layered structure800described in FIG. is similar to the layered structure200ofFIG. 2except that the layered structure800includes an additional non-overlapping region on silicon layer204at which a second insulator layer802is grown. The process of growing an insulator layer802is described in detail inFIG. 2. Silicon layer804is grown over insulator layer802, and epi-twist REO layer806is epitaxially grown over silicon layer804.

FIG. 9provides an example of layered structures illustrating non-overlapping device layers on a substrate, according to an exemplary embodiment described herein.FIG. 9builds on layered structure200ofFIG. 2. The surface layers cREO206, epi-twist REO layer104, and RE-pnictide layer106of layered structure200may be used as a base to grow different photonic or electronic device layers902composed of III-V alloys, III-N alloys, and various other oxides. In some embodiments, different device layers902may be grown over different non-overlapping structures of layered structure900. In such embodiments, multiple electronic and photonic devices may be simultaneously grown over silicon substrate102.

FIGS. 10A-Bprovides an example diagrams1000a-billustrating different examples of growing spatially separated stacks including perovskite materials and photonic devices, respectively, on the silicon substrate according to an embodiment described herein. For example, as shown inFIG. 10A, over the silicon substrate102of <100>, a first stack1002of epitwist REO layer1010of <110> and a perovskite layer1012, can be grown at a first region on the silicon substrate102. In some embodiments, the epitwist cREO layer1010may be composed of Sm1-yScyO3(0≤y≤1). In some embodiments, the perovskite material1012may include a BaTiO3-based modulator.

In some embodiments, the stack of substrate102, epitwist REO layer1010and the perovskite layer1012may be formed as an independent layered structure. In this way, the perovskite layer1012may be grown over the REO layer1010with lattice match.

In some embodiments, a second stack1004of a rare earth pnictide layer1014and a photonic device1016integrated on top of the rare earth pnictide layer1014can be grown at a second region on the silicon substrate102. In some embodiments, the rare earth pnictide layer1014may be composed of GdN1-xAsx(0≤x≤1). In some embodiments, the photonic device may include a group III-V layer, e.g., InP-based emitter1016. In some embodiments, a group IV layer, e.g., SiGeSn210, may be grown over the rare earth pnictide layer206within the second stack.

The structures shown in diagram1000illustrates a dual orientation rare-earth based buffer (e.g.,1010and1014) for integration of other layers and/or devices. Both materials above the rare earth buffers are lattice matched to the respective rare earth buffer, e.g., the BaTiO3-based modulator1012is lattice matched with the epitwist cREO layer1010, and the InP-based emitter1016is lattice matched with the RE pnictide1014.

FIG. 10Bprovides an example block diagram1000billustrating different examples of integrating an epitaxial metal electrode into the structures described inFIG. 10A, respectively, on the silicon substrate, according to an embodiment described herein. As shown at1011which is similar to the first stack of layers1002inFIG. 10A, a first epitaxial metal (e.g., having an orientation of <221>)1032is grown between the epitwist cREO layer1010and the BaTiO3-based modulator1012. A second epitaxial metal layer1034can be grown over the BaTiO3-based modulator1012within the first stack1011. A vertical modulator at the first stack311may be formed, as electro optic effect in the BaTiO3-based modulator1012can be strongly directional so as to align the metal electrodes1032and1034. An example of lower epitaxial metal1032may be Mo. In some embodiments, the top metal layer1034may be a different metal from the metal layer1032, and may not be epitaxial (e.g., at1036).

FIG. 11provides an example diagram1100illustrating different examples of growing spatially separated stacks including photonic devices, respectively, on the silicon substrate according to an embodiment described herein. Layered structure1110ofFIG. 11builds on the layered structure200ofFIG. 2. Layered structure1110grows a polar III-N layer1102over the cREO layer206of layered structure200. In some embodiments, polar III-N layer1102may be a III-N HEMT1106. Additionally, layered structure1110ofFIG. 11grows a non-polar or semi-polar III-N structure over the epi-twist REO layer104. In some embodiments, non-polar or semi-polar III-N layers may be a III-N photonic device1108built on a silicon substrate102.

In some embodiments, layer1102may be composed of SiGeSn having a crystal orientation of 111.

In some embodiments, instead of growing Epi-twist REO at104and the III-N photonic device1104/1108on top of the epi-twist REO, a stack of a RE pnictide layer and a III-V layer over the RE pnictide layer may be grown over the silicon substrate102at the region of104.

FIG. 12provides an example diagram1200illustrating different examples of growing spatially separated stacks of different photonic devices, respectively, on the silicon substrate according to an embodiment described herein. Layered structure1200builds on the layered structure100ofFIG. 1. Layered structure100had RE-pnictide layer106at a first region of the silicon substrate102and epi-twist REO layer104at a second non-overlapping region of the silicon substrate102. A III-V photonic device layer1202is grown over the RE-pnictide layer106to create a first photonic device1206on the silicon substrate102. A III-N photonic device layer1204is grown over epi-twist REO layer104to generate a second photonic device over the silicon substrate102.

FIG. 13provides an example diagrams illustrating different examples of growing epitaxial metal layers on separated stacks of different devices, respectively, on the silicon substrate according to an embodiment described herein. Layered structure1302ofFIG. 13builds on the layered structure200ofFIG. 2. An epitaxial metal layer1306is grown over cREO layer206of layered structure200ofFIG. 2. In layered structure1304, the epitaxial metal layer1308is grown over epi-twist REO layer104of layered structure200ofFIG. 2.

FIG. 14provides an example block diagram1400illustrating different examples of integrating an III-N device layer into the structures described inFIG. 13, respectively, on the silicon substrate, according to an embodiment described herein. As shown at layered structure1400which is similar to the first stack of layers inFIG. 13, a III-N layer of the form ScxAl1-xN is grown over the epitaxial metal layer1306off layered structure1400ofFIG. 14.

FIG. 15Aprovide example block diagram1500aillustrating different examples of integrating an epitaxial metal electrode into the structures described inFIG. 10A, respectively, on the silicon substrate, according to an embodiment described herein. As shown at1500awhich is similar to the first stack of layers1002inFIG. 10, a first epitaxial metal (e.g., having an orientation of <221>)1502is grown between the epitwist cREO layer1010and the BaTiO3-based modulator1012.

FIG. 15Bprovides an example block diagram1500billustrating selective processing on a silicon wafer using epitaxy to produce spatial integration of various photonic and/or electronic devices, according to an embodiment described herein. As shown at diagram1500b, various combinations of photonics and electronics using epitaxy can be grown on different epitwist cREO layers with lattice matched. For example, on the silicon wafer102, a first stack1511containing epitwist cREO and the BaTiO3-based modulator and a second stack1512containing a rare earth pnictide layer and an InP-based emitter can be grown at spatially separated regions. In addition, the rare earth pnictide layer can be grown at different regions for integration of different photonics such as emitters, detectors, and/or the like, and different electronics such as FETs, bipolar devices, and/or the like. For example, stack1502shows a rare earth pnictide layer grown at a third region on the Si substrate102, and a III-V photonic device1506grown over the rare earth pnictide layer. For another example, stack1504shows a rare earth pnictide layer grown at a fourth region on the Si substrate102, and a III-V electronic device1508grown over the rare earth pnictide layer.

FIG. 16provides an example block diagram1600illustrating optical properties of the spatially integrated structure based on a silicon substrate similar to that described inFIG. 10, according to an embodiment described herein. In some embodiments, at a first region of porous silicon substrate1602, a RE-pnictide layer106is grown over the porous silicon substrate1602. In some embodiments, the RE-pnictide layer may be composed of GdN1-x1Asx1. A layer of InP based emitter1202is grown over the RE pnictide layer106. At a second region of the porous silicon substrate1602, an additional epitwist cREO layer of <110>1614may be grown. For example, the epitwist cREO1614may be composed of Gd1-yEryO3(0≤y≤1). The porous silicon substrate1602may be added with a PIN diode such that the p-type silicon portion having an orientation of <100>, and the N-type silicon1618portion may be aligned with the cREO layer1614.

The cREO layer1614, which incorporates Er, may be used for upconversion of lights emitted from the InP-based emitter. For example, the light1604at a first wavelength1606of 1550 nm may be converted by the Er atoms1610within the epitwist cREO layer1614to a visible wavelength1612. In this way, the light at the second wavelength1612can be detected by the silicon diode.

FIG. 17provides an example block diagram1700illustrating using porous silicon as the substrate to grow an epitwist cREO layer for perovskites, according to an embodiment described herein. Diagram1700shows a porous silicon substrate102of <100>, whereas a portion of the substrate is modified to be porous. The porous silicon portion may be selected to have different porosities. For example, a first porosity of the porous portion1704may be selected to pass through a first wavelength, and a second porosity of the porous portion1702may be selected to pass through a second wavelength. Thus, when lights at the first wavelength is converted to the second wavelength via upconversion at the epiwist cREO1614, e.g., as illustrated atFIG. 16, the converted light at the second wavelength can pass through the porous portion1702but may be reflected at the porous portion904. Lights at the first wavelength or the second wavelength can be harvested at the cREO layer1614as the two wavelengths may be reflected back into the cREO1614or the PIN diode (e.g., the n-type silicon1618).

The Si-based porous portions1702and1704may be aligned with the n-types silicon414within the silicon wafer. The porous portion1702and1704may form a distributed bragg reflector (DBR). In various embodiments, the regions of porous silicon portions1702and1704may be placed beneath any element grown on the substrate. Further integration and implementation of a porous Si DBR can be found in commonly-owned and U.S. provisional application no. 62/618,985, filed Jan. 18, 2018, which is hereby expressly incorporated by reference in its entirety.

FIGS. 18A-Cprovide example block diagrams illustrating an integration of a modulator and one or more waveguide(s) into an REO buffer, according to an embodiment described herein. InFIG. 18A, diagram1800ashows a cross-section view of the plan view1804at the cross-section “X.” In diagram1820, a first stack of a first epitaxial metal1806, a modulated optical path1808and a second metal layer1810may be grown at a first region on top of the REO layer104, that is gown over a silicon substrate102. A waveguide1812may be grown at a spatially separated second region on top of the REO layer104. A cladding material1802may be used to wrap around and fill in the space between the first stack and the second stack. Specifically, the refractive index of either the first stack or the second stack is selected to be greater than the cladding refractive index of the cladding material1802. The refractive index of the REO (110)104may be smaller than the core refractive index of the waveguide1812. The structure shown at1820is formed on the silicon substrate of <100>, which allows integration with Si electronics.

At diagram1804which illustrates the plan view of the layered structure1800, lights may pass through the waveguide1812, whereas lights are split into two beams to pass through modulated optical path1808. A first beam of light may enter the modulated optical path1808to be modulated into a first modulated beam of light1814. A second beam of light may enter the optical path1816. In some embodiments, to be modulated into a second modulated beam of light1816. The two modulated beams of light1814and1816may be mixed to form a combined beam of light1818. The cross-section view at “X” of diagram1804may be similar to diagram1820.

Diagram1800cinFIG. 18Cshows another example of integration of photonic and electronic devices onto the REO layer104on a single wafer. For example, selective areas on the single wafer of the REO layer104can be used for electronics and photonics device epitaxy. Photonic devices such as modulators, detectors, waveguides, splitters etc. may be integrated into the stack of1806,1808and1810. Electronic devices such as an electronic FET1822may be integrated into the same REO layer104.

FIG. 19provides an example block diagram illustrating an integration of electronic and photonic devices on a silicon substrate, according to an embodiment described herein. As shown inFIG. 18A, photonic devices1902may be grown at a first region of the silicon substrate102. Similarly, electronic devices1904may be grown at a second region of the silicon substrate102. The photonic devices may be composed of epi-twist REO layer104, epitaxial metal layer1806over the epi-twist REO layer104, a modulated optical path1808over the epitaxial metal layer1806, and metal layer1810over the modulated optical path1808. Similarly, at a second non-overlapping region of silicon substrate102, a RE-pnictide layer106may be grown over the silicon substrate102. The RE-pnictide layer106may be used as a base to grow III-V electronic devices1906. In this way, the silicon substrate102is able to grow both photonic devices1902and electronic devices1904simultaneously.

FIG. 20provides an example diagram2000showing a mixed electronic/RF structure with an epitaxial metal layer, according to an embodiment. In the structure2000, a layer2004composed of AlxSc1-xN (0≤x≤1), e.g., as an Al(Sc)N-based radio-frequency filter, is grown over the REO layer within the first stack, and GaAs2006is grown over the rare earth pnictide layer within the second stack. Within the first stack, the REO layer having an orientation of <111> acts as buffer where an additional epitaxial metal layer2002and the AlxSc1-xN layer2004can be grown over the <111> Silicon portion of the SOI substrate. Within the second stack, the rare earth pnictide may act as a buffer for the GaAs layer2006and any subsequent III-V power amplifier epitaxially grown over the GaAs layer2006.

FIG. 21provides an example diagram2100showing optical interactions between the formed two stacks within the two regions on the silicon substrate in a layered structure similar to those illustrated inFIG. 20, according to an embodiment. Specifically, as shown inFIG. 21, light2103emitted from the III-V layer within the second stack may reach the REO layer within the first stack, which in turn passes through the light to the silicon layer having an orientation of <111>. At the REO layer2120, upconversion may be used to convert the light to a detectable wavelength for the Si diode at the SOI substrate. For example, at the REO layer2102, the rare earth element may absorb light2103at a specific wavelength and remit the light2106at a shorter wavelength. An example option of the rare earth element may be Er, which interacts with lights at the wavelength of 1550 nm and then produces a light at wavelength ranging from 980 to 530 nm. The Si <111> layer (e.g., similar to106inFIG. 1) contains the p-n junctions2104-2105that can act as a diode, and respond to the remitted light2106at a shorter wavelength.

FIGS. 22-24provide example layout diagram showing different applications of the layered structure similar to those illustrated inFIGS. 1-21 and 23-27, according to an embodiment. Diagram2200inFIG. 22shows a PIC chip layout at a transceiver. For example, photonic devices such as lasers2208, electronic devices such as tap monitors2210, an electron-absorption modulator (EAM)2212, an multi-mode interface (MMI)2213and/or the like may be integrated into the same epitaxial platform in a similar way as shown inFIGS. 1-21. As the photonic devices and electronic devices share the same epitaxial platform, the size or dimension of the circuit chip may be small, e.g., with a 1.5×2.5 mm chip area for four lasers multiplexed into one fiber.

Diagram2300inFIG. 23and diagram2400inFIG. 24show alternative embodiments of a cross-section layout for building the circuit layout2200shown inFIG. 22, including repetitions of structures similar to that shown inFIG. 1. For example, diagram2300shows a cross-section view of the circuit chip2200at a position “X”2202, where the (four) lasers2208may be integrated into the (four) regions of III-V alloys2304,2308,2312and2316. The for-surface mount portion2318(e.g., corresponding to2213inFIG. 22) may be an island of oxide that allows a component to be placed on the PIC, and may be electrically isolated from neighboring elements. For example, the for-surface mount portion2318may include a layer of epi metal for connectivity. The SOI portion2320(e.g., corresponding to2201inFIG. 22) may be a region designed for upstream processing, e.g., by using porous process to optically isolate/guide the adjacent laser by converting Si to p-type Si.

For another example, diagram2400shows a cross-section view of the circuit chip2200at a position “Z”2206, where a laser (e.g.,2208) can be integrated into the III-V region2404, and an EAM (e.g.,2212) may be integrated into the SiGeSn layer2406, respectively. A waveguide (not shown inFIG. 22) can be inserted at2408using the silicon layer of <111>.

FIGS. 25-26provide example processes2500-2600to form the example structures1000ashown inFIG. 10A, according to an embodiment. Process2500may start at step2502with an SOI substrate. For example, the SOI substrate may include the first silicon substrate102of <100>, an insulator layer202composed of SiO2and a second silicon layer204of <111>, as discussed inFIG. 2. At step2504, a mask2512is formed at a region on top of the SOI substrate. At step2506, an REO layer2514can be grown on the SOI substrate at a region that is not masked by the mask2512. At step2508, a photonic device (e.g., SiGeSn) may be integrated into the structure by growing over the REO layer2514. At step2510, the mask2512may be removed to expose the previously masked available region on the SOI substrate.

Continuing on with process2600inFIG. 26, at step2602, another mask2610that is used to protect the formed first stack including the photonic device of step2510from additional processing steps and to separate the first stack from a second stack to be formed on the SOI substrate. At step2604, the SOI substrate is modified in a way such that the insulator layer and the second silicon layer on top of the insulator layer are removed by well-etching techniques to align with the region defined by the mask2610. In this way, an available region on the original silicon substrate102is exposed. At step2606, the insulator layer and the second silicon layer are further resized such that the mask2610is extended to form a shield that separates the formed first stack of the insulator layer, the second silicon layer, the REO layer and the photonic device from growth of other layers on the other side of the mask2610. Thus, at the exposed available region that is separated by the mask2610on the original silicon substrate102, a rare earth pnictide layer2614is grown, and the III-V layer2612is grown over the rare earth pnictide layer2614. At step2608, the mask2610is removed, and two stacks of layered structures similar to that illustrated inFIG. 10Aare formed on the silicon substrate102.

It is worth noting that inFIGS. 25-26, two stacks of layers are formed from the silicon substrate102and/or the SOI substrate including102,104and106. However, multiple stacks, or multiple repetitions of the stacks of layers can be formed in a similar way (e.g., by repeating processes2500-2600) to form a common epitaxial platform for photonic devices and electronic devices, e.g., as shown in the cross-section views900-1000of a circuit layout inFIGS. 22-23.

FIG. 27provides example diagrams2702and2706that show different ways to grow different layers on the silicon substrate during the process illustrated inFIGS. 25-26, according to an embodiment. In some embodiments, prior to manufacture of the SOI wafer at step2502inFIG. 25, part of the first silicon substrate102inFIG. 25, may be modified to form a porous portion2704via a porous silicon process such that the porous portion2704aligns with and interacts with the device grown upon the substrate, e.g., the rare earth pnictide and the InP on top of the porous portion2704. In another example, prior to the deposition of any rare earth-based material at step2506inFIG. 25, part of the second silicon wafer204may be modified to form a porous portion2708via the porous silicon process such that the porous portion2708aligns with and interacts with the device grown upon the silicon layer, e.g., the REO layer and the photonic device.

As described herein, a layer means a substantially-uniform thickness of a material covering a surface. A layer can be either continuous or discontinuous (i.e., having gaps between regions of the material). For example, a layer can completely or partially cover a surface, or be segmented into discrete regions, which collectively define the layer (i.e., regions formed using selective-area epitaxy).

Monolithically-integrated means formed on the surface of the substrate, typically by depositing layers disposed on the surface.

Disposed on means “exists on” an underlying material or layer. This layer may comprise intermediate layers, such as transitional layers, necessary to ensure a suitable surface. For example, if a material is described to be “disposed on a substrate,” this can mean either (1) the material is in intimate contact with the substrate; or (2) the material is in contact with one or more transitional layers that reside on the substrate.

Single-crystal means a crystalline structure that comprises substantially only one type of unit-cell. A single-crystal layer, however, may exhibit some crystalline defects such as stacking faults, dislocations, or other commonly occurring crystalline defects.

Single-domain means a crystalline structure that comprises substantially only one structure of unit-cell and substantially only one orientation of that unit cell. In other words, a single-domain crystal exhibits no twinning or anti-phase domains.

Single-phase means a crystalline structure that is both single-crystal and single-domain.

Substrate means the material on which deposited layers are formed. Exemplary substrates include, without limitation: bulk silicon wafers, in which a wafer comprises a homogeneous thickness of single-crystal silicon; composite wafers, such as a silicon-on-insulator wafer that comprises a layer of silicon that is disposed on a layer of silicon dioxide that is disposed on a bulk silicon handle wafer; or any other material that serves as base layer upon which, or in which, devices are formed. Examples of such other materials that are suitable, as a function of the application, for use as substrate layers and bulk substrates include, without limitation, germanium, alumina, gallium-arsenide, indium-phosphide, silica, silicon dioxide, borosilicate glass, pyrex, and sapphire. A substrate may have a single bulk wafer, or multiple sub-layers. Specifically, a silicon substrate may include multiple non-continuous porous portions. The multiple non-continuous porous portions may have different densities and may be horizontally distributed or vertically layered.

Miscut Substrate means a substrate which comprises a surface crystal structure that is oriented at an angle to that associated with the crystal structure of the substrate. For example, a 6° miscut <100> silicon wafer comprises a <100> silicon wafer that has been cut at an angle to the <100> crystal orientation by 6° toward another major crystalline orientation, such as <110>. Typically, but not necessarily, the miscut will be up to about 20°. Unless specifically noted, the phrase “miscut substrate” includes miscut wafers having any major crystal orientation. That is, a <111> wafer miscut toward the <011> direction, a <100> wafer miscut toward the <110> direction, and a <011> wafer miscut toward the <001> direction.

Semiconductor refers to any solid substance that has a conductivity between that of an insulator and that of most metals. An example semiconductor layer is composed of silicon. The semiconductor layer may include a single bulk wafer, or multiple sub-layers. Specifically, a silicon semiconductor layer may include multiple non-continuous porous portions. The multiple non-continuous porous portions may have different densities and may be horizontally distributed or vertically layered.

Semiconductor-on-Insulator means a composition that comprises a single-crystal semiconductor layer, a single-phase dielectric layer, and a substrate, wherein the dielectric layer is interposed between the semiconductor layer and the substrate. This structure is reminiscent of prior-art silicon-on-insulator (“SOI”) compositions, which typically include a single-crystal silicon substrate, a non-single-phase dielectric layer (e.g., amorphous silicon dioxide, etc.) and a single-crystal silicon semiconductor layer. Several important distinctions between prior-art SOI wafers and the inventive semiconductor-on-insulator compositions are that:

Semiconductor-on-insulator compositions include a dielectric layer that has a single-phase morphology, whereas SOI wafers do not. In fact, the insulator layer of typical SOI wafers is not even single crystal.

A first layer described and/or depicted herein as “configured on,” “on” or “over” a second layer can be immediately adjacent to the second layer, or one or more intervening layers can be between the first and second layers. A first layer that is described and/or depicted herein as “directly on” or “directly over” a second layer or a substrate is immediately adjacent to the second layer or substrate with no intervening layer present, other than possibly an intervening alloy layer that may form due to mixing of the first layer with the second layer or substrate. In addition, a first layer that is described and/or depicted herein as being “on,” “over,” “directly on,” or “directly over” a second layer or substrate may cover the entire second layer or substrate, or a portion of the second layer or substrate.

A substrate is placed on a substrate holder during layer growth, and so a top surface or an upper surface is the surface of the substrate or layer furthest from the substrate holder, while a bottom surface or a lower surface is the surface of the substrate or layer nearest to the substrate holder. Any of the structures depicted and described herein can be part of larger structures with additional layers above and/or below those depicted. For clarity, the figures herein can omit these additional layers, although these additional layers can be part of the structures disclosed. In addition, the structures depicted can be repeated in units, even if this repetition is not depicted in the figures.

From the above description it is manifest that various techniques may be used for implementing the concepts described herein without departing from the scope of the disclosure. The described embodiments are to be considered in all respects as illustrative and not restrictive. It should also be understood that the techniques and structures described herein are not limited to the particular examples described herein, but can be implemented in other examples without departing from the scope of the disclosure. Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results.