Bootstrap circuit

A bootstrap circuit particularly suitable for low voltage applications and use with semiconductor memories is disclosed.

BACKGROUND OF THE INVENTION 
1. Field of the Invention 
The present invention relates to a bootstrap circuit particularly suitable 
for a low voltage driven bootstrap circuit to be used with a voltage 
booster for a semiconductor memory such as DRAM and a flash memory. 
2. Description of the Related Art 
A charge pump circuit is used as a voltage booster for a semiconductor 
memory such as DRAM and a flash memory. The voltage booster is required to 
generate a desired high and stable potential in a predetermined time. In 
order to boost a voltage at high speed, a charge pump circuit has been 
used to which an input clock having a voltage higher than a power source 
voltage V.sub.DD is supplied. 
A conventional bootstrap circuit has a structure such as shown in FIG. 1. 
The operation of this bootstrap circuit will be described with reference 
to FIGS. 2A to 2D. FIGS. 2A to 2D show waveforms of potentials changing 
with time at an input terminal IN, a node N.sub.121, a node N.sub.122, and 
a node N.sub.123 (output terminal OUT), respectively of the circuit shown 
in FIG. 1. 
As the potential at the input terminal IN rises as shown in FIG. 2A from 
the ground potential V.sub.SS to the power source voltage V.sub.DD during 
the time period from time t.sub.1 to time t.sub.2, the potential at the 
node N.sub.123 connected via an N-channel enhancement MOS transistor 
M.sub.121 to the input terminal IN starts rising from the ground potential 
V.sub.SS as shown in FIG. 2D. The transistor M.sub.121 is in an on-state 
with the power source voltage V.sub.DD being applied to its gate. On the 
other hand, the potential at the node N.sub.122 connected via an inverter 
IV.sub.121 to the input terminal IN starts gradually lowering from the 
power source voltage V.sub.DD toward the ground potential V.sub.SS by the 
function of a capacitor C.sub.122 as shown in FIG. 2C. At this time, 
however, the potential at the node N.sub.121 remains to be the ground 
potential V.sub.SS as shown in FIG. 2B because an N-channel enhancement 
MOS transistor M.sub.123 with its gate being connected to the node 
N.sub.122 is in an on-state. 
After the potential at the node N.sub.122 continues lowering and becomes 
lower than the threshold voltage of the transistor M.sub.123, the 
transistor M.sub.123 changes from the on-state to the off-state. On the 
other hand, after the potential at the node N.sub.123 continues rising and 
becomes higher than the threshold voltage of an N-channel enhancement 
transistor M.sub.122 with its gate connected to the node N.sub.123, the 
transistor M.sub.122 changes from the off-state to the on-state. As a 
result, the potential at the node N.sub.121 starts rising from the ground 
potential V.sub.SS to the power source voltage V.sub.DD (at time t.sub.3 
shown in FIGS. 2B). 
As the potential at the node N.sub.121 starts rising, the potential at the 
node N.sub.123 further rises by the amount corresponding to a rise of the 
potential at the node N.sub.121 because of the function of the capacitor 
C.sub.121. With the feedback function of the capacitor C.sub.121, the 
potential at the node N.sub.123 (i.e., output terminal OUT) rises higher 
than the power source voltage V.sub.DD (at time t.sub.4 shown in FIG. 2D). 
At the time when the potential at the node N.sub.123 becomes the power 
source voltage V.sub.DD, a potential difference between the gate and 
source/drain of the transistor M.sub.121 is small. Therefore, regardless 
of the higher potential at the node N.sub.123 than the power source 
voltage V.sub.DD, current will not flow from the node N.sub.123 to the 
input terminal IN. 
Next, as the potential at the input terminal IN lowers as shown in FIG. 2A 
from V.sub.DD to V.sub.SS during the time period from time t.sub.5 to time 
t.sub.7, the potential at the node N.sub.122 connected via the inverter 
IV.sub.121 to the input terminal IN starts rising as shown in FIG. 2C. 
When the potential at the node N.sub.122 exceeds the threshold voltage of 
the transistor M.sub.123 (at time t.sub.6), the transistor M.sub.123 
changes from the off-state to the on-state and the potential at the node 
N.sub.121 starts lowering as shown in FIG. 2B. As a result, the potential 
at the node N.sub.123 also starts lowering as shown in FIG. 2D. When the 
potential at the node N.sub.123 becomes lower than the threshold voltage 
of the transistor M.sub.123, the transistor M.sub.122 changes from the 
on-state to the off-state and the node N.sub.121 is disconnected from the 
power source terminal. On the other hand, as the potential at the input 
terminal IN lowers and the potential at the node N.sub.123 lowers, the 
transistor M.sub.121 with its gate to which the power source voltage 
V.sub.DD is applied changes from the on-state to the off-state, and 
current flows from the node N.sub.123 to the input terminal IN so that the 
potential at the node N.sub.123 becomes the ground potential V.sub.SS (at 
time t.sub.8 show in FIG. 2D). Then, at time t.sub.9 the potentials at 
both the nodes N.sub.121 and N.sub.122 become the ground potential 
V.sub.SS (refer to FIGS. 2B and 2C). 
With the above operations, a pulse signal having a larger voltage than the 
power source voltage V.sub.DD is obtained at the output terminal OUT, and 
the pulse signal can be used as a clock input to a charge pump circuit. 
Although the conventional bootstrap circuit described above can obtain a 
pulse signal having a higher voltage than the power source voltage 
V.sub.DD, the boost of the output voltage is not still sufficient. 
Specifically, as the potential at the node N.sub.121 of the circuit shown 
in FIG. 1 rises to the power source voltage V.sub.DD, the output voltage 
should rise to 2 V.sub.DD in an ideal case. However, in an actual case, it 
rises only to 2 V.sub.DD -V.sub.th because of the threshold voltage 
V.sub.th of the transistor M.sub.121 which functions as a switching 
transistor (refer to FIG. 2D). 
Further, in the conventional bootstrap circuit, it is relatively difficult 
for the transistor M.sub.122 to turn on because it is an N-channel 
transistor. The conventional bootstrap circuit is therefore associated 
with a problem that linearity of the rise of the output pulse is 
insufficient. If the bootstrap circuit is driven at a low power source 
voltage, particularly at about 1 V, the transistor M.sub.122 does not turn 
on in some cases. 
Still further, in the conventional bootstrap circuit, the voltage fall at 
the node N.sub.123 upon the fall of the output pulse is achieved by 
flowing current via the transistor M.sub.121 to the input terminal IN. A 
voltage fall at the node N.sub.123 is therefore relatively slow. This 
results in a problem of a long fall time of the output pulse. 
SUMMARY OF THE INVENTION 
It is an object of the present invention to provide a bootstrap circuit 
having a voltage boost ability higher than conventional, providing a 
reliable operation even at a low power source voltage, and being able to 
shorten a fall time of the output pulse. 
According to one aspect of the present invention, there is provided a 
bootstrap circuit comprising: 
a first enhancement N-channel MOS transistor having a drain connected to an 
input terminal of the bootstrap circuit and a source connected to an 
output terminal of the bootstrap circuit; 
a first enhancement P-channel MOS transistor having a gate connected via a 
first inverter to the source of the first enhancement N-channel MOS 
transistor and a drain connected to a power source terminal; 
a first capacitor having one terminal connected to a source of the first 
enhancement P-channel MOS transistor and the other terminal connected to 
the source of the first enhancement N-channel MOS transistor; 
a second enhancement N-channel MOS transistor having a drain connected to 
the source of the first enhancement P-channel MOS transistor, a source 
connected to a ground terminal, and a gate connected via a second inverter 
to the input terminal; 
a second capacitor having one terminal connected to an input terminal of 
the second inverter and the other terminal connected to the ground 
terminal; and 
gate potential controlling means for controlling a gate potential of the 
first enhancement N-channel MOS transistor so as to raise the gate 
potential to a power source potential or higher during a predetermined 
time period immediately after an input signal applied to the input 
terminal rises and to maintain the gate potential to be substantially the 
same as the power source potential during a time period other than the 
predetermined time period. 
The gate potential controlling means may comprise: 
a third capacitor having one terminal connected to the input terminal and 
the other terminal connected to a gate of the first enhancement N-channel 
MOS transistor; 
a second enhancement P-channel MOS transistor having a gate connected to 
the input terminal, a drain connected to the power source terminal, and a 
source connected to the gate of the first enhancement N-channel MOS 
transistor; 
a third enhancement P-channel MOS transistor having a drain connected to 
the power source terminal and a source connected to the gate of the first 
enhancement N-channel MOS transistor; and 
a delay circuit connected between the input terminal and a gate of the 
third enhancement P-channel MOS transistor, the delay circuit determining 
the predetermined time period during which the gate potential of the first 
enhancement N-channel MOS transistor is raised. 
The bootstrap circuit may further include a third N-channel MOS transistor 
having a drain connected to the source of the first enhancement N-channel 
MOS transistor, a source connected to the ground terminal, and a gate 
connected via a third inverter to the input terminal. 
An output terminal of the third inverter may be connected via a fourth 
inverter to the input terminal of the second inverter, and an output 
terminal of the second inverter may be connected to a gate of the third 
enhancement P-channel MOS transistor. 
A fourth P-channel MOS transistor included in the fourth inverter and the 
second capacitor may control the predetermined time period during which 
the gate potential of the first enhancement N-channel MOS transistor is 
raised. 
According to the present invention, the gate potential of the first 
N-channel MOS transistor used as the switching transistor of the bootstrap 
circuit is raised to a power source voltage or higher during a 
predetermined time period immediately after the input signal rises. 
Accordingly, the influence of the threshold voltage of the transistor can 
be eliminated and an output voltage generally two times as high as the 
power source voltage can be obtained. 
Therefore, a relatively high output voltage can be obtained even at a low 
power source voltage. By using this output as an input pulse to a charge 
pump circuit, a voltage boost speed of the charge pump circuit can be 
improved. 
The first enhancement P-channel MOS transistor is used as the MOS 
transistor constituting the feedback section. Accordingly, this transistor 
is easy to turn on while ensuring a reliable operation even at a low power 
source voltage. 
Furthermore, provision of the third N-channel MOS transistor between the 
output terminal and the ground terminal allows a voltage fall at the 
output terminal to be performed in a short time. Accordingly, an output 
signal having a short fall time can be obtained, improving an operation 
speed of the bootstrap circuit.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
As shown in FIG. 3, in a bootstrap circuit according to an embodiment of 
the present invention, an input terminal IN is connected to the drain of 
an enhancement N-channel MOS transistor M.sub.11, to the gate of an 
enhancement P-channel MOS transistor M.sub.12, to one terminal of a 
capacitor C.sub.12, and to the input terminal of an inverter IV.sub.11. 
The source of the transistor M.sub.11 is connected to a node N.sub.16. 
This node N.sub.16 is connected to an output terminal OUT, the input 
terminal of an inverter IV.sub.14, to one end of a capacitor C.sub.13, and 
to the drain of an enhancement N-channel MOS transistor M.sub.16. The 
drain of the transistor M.sub.12 is connected to a power source terminal 
TV.sub.DD, and the source thereof is connected via a node N.sub.17 to the 
gate of the transistor M.sub.11. The node N.sub.17 is connected to the 
other terminal of the capacitor C.sub.12 and to the source of an 
enhancement P-channel MOS transistor M.sub.13. Also connected to the nodes 
N.sub.17 are the substrate terminals of the transistors M.sub.12 and 
M.sub.13. The drain of the transistor M.sub.13 is connected to the power 
source terminal TV.sub.DD. 
The output terminal of the inverter IV.sub.14 is connected via a node 
N.sub.15 to the gate of an enhancement P-channel MOS transistor M.sub.14. 
The drain and substrate terminal of the transistor M.sub.14 are connected 
to the power source terminal TV.sub.DD, and the source thereof is 
connected to a node N.sub.14. The node N.sub.14 is connected to the other 
terminal of the capacitor C.sub.13 and to the drain of an enhancement 
N-channel MOS transistor M.sub.15. The source of the transistor M.sub.15 
is connected to a ground terminal TV.sub.SS. 
The output terminal of the inverter IV.sub.11 is connected via a node 
N.sub.11 to the input terminal of an inverter IV.sub.12. The node N.sub.11 
is also connected to the gate of the transistor M.sub.16. The source of 
the transistor M.sub.16 is connected to the ground terminal TV.sub.SS. The 
output terminal of the inverter IV.sub.12 is connected via a node N.sub.12 
to the input terminal of an inverter IV.sub.13. The node N.sub.12 is 
connected to one terminal of a capacitor C.sub.11 the other terminal of 
which is connected to the ground terminal TV.sub.SS. The output terminal 
of the inverter IV.sub.13 is connected via a node N.sub.13 to the gate of 
the transistor M.sub.13 and to the gate of the transistor M.sub.15. 
Next, the operation of the bootstrap circuit of this embodiment constructed 
as above will be described with reference to FIGS. 4A to 4F. FIGS. 4A to 
4F show waveforms of potentials changing with time at the input terminal 
IN, output terminal OUT (node N.sub.16), and nodes N.sub.17, N.sub.14, 
N.sub.11, and N.sub.13, respectively of the circuit shown in FIG. 3. Being 
different from FIGS. 2A to 2D, FIGS. 4A to 4F mainly illustrate a low 
level part of an input signal. A power source voltage V.sub.DD is 1 volt. 
While the input signal takes a low level (ground voltage V.sub.SS ), the 
P-channel transistor M.sub.12 is in an on-state. Therefore, the power 
source voltage V.sub.DD is being applied to the gate of the N-channel 
transistor M.sub.11 which maintains the on-state. Since the potential at 
the node N.sub.11 is at a high level (power source voltage V.sub.DD ), the 
N-channel transistor M.sub.16 is in the on-state. Therefore, the potential 
at the node N.sub.16 is at the low level (ground voltage V.sub.SS ). Since 
the potential at the node N.sub.15 is at the high level (power source 
voltage V.sub.DD), the P-channel transistor M.sub.14 is in an off-state so 
that the node N.sub.14 is disconnected from the power source terminal 
TV.sub.DD. Since the potential at the node N.sub.13 is at the high level 
(power source voltage V.sub.DD), the P-channel transistor M.sub.13 is in 
the off-state, the N-channel transistor M.sub.15 is in the on-state, and 
the potential at the node N.sub.14 is at the low level (ground voltage 
V.sub.SS). 
Next, as the potential at the input terminal IN rises at time t.sub.5 as 
shown in FIG. 4A from the ground voltage V.sub.SS to the power source 
voltage V.sub.DD, the potential at the node N.sub.11 connected via the 
inverter IV.sub.11 to the input terminal IN starts lowering from the power 
source voltage V.sub.DD to the ground voltage V.sub.SS (at time t.sub.6 
shown in FIG. 4E). As a result, the N-channel transistor M.sub.16 changes 
from the on-state to the off-state and the potential at the node N.sub.16 
connected via the transistor M.sub.11 to the input terminal IN starts 
rising (refer to FIG. 4B). On the other hand, as the potential at the 
input terminal IN rises from the ground voltage V.sub.SS to the power 
source voltage V.sub.DD, the P-channel transistor M.sub.12 changes from 
the on-state to the off-state and the potential at the node N.sub.17 
starts rising (at time t.sub.6 shown in FIG. 4C) because of the function 
of charges stored in the capacitor C.sub.12. 
In some short time after the potential at the input terminal IN reaches the 
power source voltage V.sub.DD, the potential at the node N.sub.17 takes a 
peak value (at time t.sub.8 shown in FIG. 4C). Because of this potential 
rise at the node N.sub.17, i.e., at the gate of the N-channel transistor 
M.sub.11, the potential at the node N.sub.16 rises near to the power 
source voltage V.sub.DD (refer to FIG. 4B). If the gate potential of the 
transistor M.sub.11 were fixed to the power source voltage V.sub.DD as in 
the conventional circuit, the potential at the node N.sub.16 at this time 
rises only to V.sub.DD -V.sub.th (V.sub.th is the threshold voltage of the 
transistor M.sub.11). However, in this embodiment, since the gate 
potential of the transistor M.sub.11 is raised to the power source voltage 
V.sub.DD or higher, the potential at the node N.sub.16 rises near to the 
power source voltage V.sub.DD. In this case, if the gate potential of the 
transistor M.sub.11 is raised to V.sub.DD +V.sub.th or higher, the 
potential at the node N.sub.16 reaches the power source voltage V.sub.DD. 
Thereafter, during the time period from time t.sub.9 to time t.sub.10, the 
potential at the node N.sub.13 lowers from the power source voltage 
V.sub.DD to the ground voltage V.sub.SS (refer to FIG. 4F). A time 
difference or delay time between the time t.sub.9 when the potential at 
the node N.sub.13 starts lowering and the time t.sub.5 when the potential 
at the input terminal IN starts rising, results from the function of the 
inverters IV.sub.11, IV.sub.12, IV.sub.13 and capacitor C.sub.11. In this 
embodiment, this delay time is mainly controlled by a resistance R.sub.c 
of a P-channel transistor (not shown) used in the inverter IV.sub.12 and a 
capacitance C.sub.s of the capacitor C.sub.11. 
As the potential at the node N.sub.13 lowers, the P-channel transistor 
M.sub.13 changes from the off-state to the on-state and the potential at 
the node N.sub.17 lowers to the power source voltage V.sub.DD (during the 
time period from time t.sub.9 to time t.sub.11 shown in FIG. 4C). In an 
actual case, the potential at the node N.sub.17 starts lowering earlier 
than time T.sub.9 in an actual case because of leak current. As the gate 
potential of the N-channel transistor lowers, the transistor M.sub.11 
changes from the on-state to the off-state and the node N.sub.16 is 
disconnected from the input terminal IN. 
As the potential at the node N.sub.13 lowers, the N-channel transistor 
M.sub.15 changes from the on-state to the off-state and the node N.sub.14 
is disconnected from the ground terminal TV.sub.SS. By this time, since 
the potential at the node N.sub.16 has risen to about the power source 
voltage V.sub.DD (refer to FIG. 4B), the potential at the node N.sub.15 
connected via the inverter IV.sub.14 to the node N.sub.16 has lowered to 
about the ground voltage V.sub.SS. Therefore, the P-channel transistor 
M.sub.14 is in the on-state and the node N.sub.14 is connected to the 
power source terminal TV.sub.DD. Then, the potential at the node N.sub.14 
starts rising from the ground voltage V.sub.SS to the power source voltage 
V.sub.DD (refer to FIG. 4D). By the feedback operation of the capacitor 
C.sub.13, the potential at the node N.sub.16, i.e., at the output terminal 
OUT, is raised over the power source voltage V.sub.DD (refer to FIG. 4B). 
In this embodiment, since the potential at the node N.sub.16 is near at 
the power source voltage V.sub.DD and the transistor M.sub.11 is in the 
off-state when the feedback operation starts, the potential at the output 
terminal OUT is raised nearly to the voltage of 2 V.sub.DD (at time 
t.sub.12 shown in FIG. 4B). 
Also in this embodiment, the transistor relevant to the feedback operation 
is constituted by the P-channel transistor M.sub.14, the reliable 
operation of the P-channel transistor M.sub.14 is ensured even at a low 
power source voltage of, for example, about 1 V. 
Next, like the time period from time t.sub.1 to time t.sub.2, as the 
potential at the input terminal IN starts lowering from the power source 
voltage V.sub.DD to the ground voltage V.sub.SS, the potential at the node 
N.sub.11 starts rising from the ground voltage V.sub.SS to the power 
source voltage V.sub.DD (refer to FIG. 4E) and the N-channel transistor 
M.sub.16 changes from the off-state to the on-state. Therefore, the node 
N.sub.16 is connected to the ground terminal TV.sub.SS and the potential 
at the output terminal OUT lowers quickly (during the time period from 
time t.sub.1 to time t.sub.4 shown in FIG. 4B). As the potentials at the 
input terminal IN and node N.sub.16 lower, also the N-channel transistor 
M.sub.11 with the power source voltage V.sub.DD being applied to its gate 
changes from the off-state to the on-state, and so the node N.sub.16 is 
connected to the input terminal IN. 
As the potential at the node N.sub.13 starts rising from the ground voltage 
V.sub.SS to the power source voltage V.sub.DD (at time t.sub.3 shown in 
FIG. 4F), the N-channel transistor M.sub.15 changes from the off-state to 
the on-state. Therefore, the node N.sub.14 is connected to the ground 
terminal TV.sub.SS and the potential at the node N.sub.14 lowers from the 
power source voltage V.sub.DD to the ground voltage V.sub.SS (during the 
time period from time t.sub.3 to time t.sub.4 shown in FIG. 4D). As the 
potential at the node N.sub.15 rises, the P-channel transistor M.sub.14 
changes from the on-state to the off-state and the node N.sub.14 is 
disconnected from the power source terminal TV.sub.DD. 
As the potential at the input terminal IN lowers, the P-channel transistor 
M.sub.12 changes from the off-state to the on-state, whereas as the 
potential at the node N.sub.13 rises, the P-channel transistor M.sub.13 
changes from the on-state to the off-state. 
With the above-described operations, an output pulse having a voltage of 
approximately 2 V.sub.DD boosted from the power source voltage V.sub.DD 
can be obtained. 
The input signal pulse used in this embodiment has the fall edge steeper 
than the rise edge. It is therefore uncertain whether the potential at the 
node N.sub.16 (output terminal OUT) can be lowered more rapidly than the 
conventional circuit. However, it is to be noted at least that the voltage 
fall at the node N.sub.16 is more rapid than when the transistor M.sub.16 
is not used. 
The present invention has been described in connection with the preferred 
embodiment. The present invention is not intended to be limited only to 
this embodiment. For example, in the above embodiment, although the delay 
circuit for controlling the gate potential of the N-channel transistor 
M.sub.11 is mainly constituted by the inverter IN.sub.12 (P-channel 
transistor used therein) and the capacitor C.sub.11, a transistor gate 
circuit may be used for the delay circuit.