Control method of flash memory controller and associated flash memory controller and electronic device

The present invention provides a control method of a flash memory controller, wherein the flash memory controller is configured to access a flash memory module, the flash memory module includes a plurality of planes, and each plane includes a plurality of blocks; and the control method includes the steps of: after the flash memory controller is powered on, reading a first code bank from a specific block of the plurality of blocks; storing the first code bank into a buffer memory; executing the first code bank to manage the flash memory module; when the flash memory controller starts a code bank swapping operation, trying to read a second code bank from a super block; if the second code bank is read successfully, storing the second code bank into the buffer memory to replace the first code bank; and executing the second code bank to manage the flash memory module.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a flash memory controller.

2. Description of the Prior Art

In a conventional flash memory system, a code bank comprising an in-system programming (ISP) code is generally stored in a specific block of a flash memory module. When a flash memory controller is powered on, the flash memory controller will read the ISP code from the specific block and store the ISP code into a buffer within the flash memory controller, for subsequent use. However, the buffer capacity is limited, and a size of the ISP code will become larger as firmware of the flash memory controller is updated, so the ISP code may be divided into several code banks, and the buffer within the flash memory controller stores only one code bank. When the ISP code is divided into several code banks, each code bank will only comprise part of functions, and the flash memory controller may need to load the required code bank from the flash memory module to replace the current code bank stored in the buffer. Therefore, because the flash memory controller swaps the code banks based on the required functions to be used, the specific block storing the code banks will be read many times, causing read disturbance and affecting data quality.

SUMMARY OF THE INVENTION

It is therefore an objective of the present invention to provide a method for managing code banks, which can increase the robustness of the code banks and increase the speed of swapping code banks, to solve the above-mentioned problems.

According to one embodiment of the present invention, a control method of a flash memory controller is disclosed, wherein the flash memory controller is configured to access a flash memory module, the flash memory module comprises a plurality of planes, each plane comprises a plurality of blocks, and each block comprises a plurality of pages; and the control method comprises the steps of: after the flash memory controller is powered on, reading a first code bank from a specific block of the plurality of blocks; storing the first code bank into a buffer memory; executing the first code bank to manage the flash memory module; when the flash memory controller starts a code bank swapping operation, trying to read a second code bank from a super block, wherein the super block comprises a plurality of blocks respectively located in at least two planes; if the second code bank is read successfully, storing the second code bank into the buffer memory to replace the first code bank; and executing the second code bank to manage the flash memory module.

According to another one embodiment of the present invention, a flash memory controller is disclosed, wherein the flash memory controller is configured to access a flash memory module, the flash memory module comprises a plurality of planes, each plane comprises a plurality of blocks, and each block comprises a plurality of pages. The flash memory controller comprises a read only memory and a microprocessor, wherein the read only memory stores a program code, and the microprocessor is configured to execute the program code to control the access of the flash memory module. The microprocessor is configured to perform the steps of: after the flash memory controller is powered on, reading a first code bank from a specific block of the plurality of blocks; storing the first code bank into a buffer memory; executing the first code bank to manage the flash memory module; when the flash memory controller starts a code bank swapping operation, trying to read a second code bank from a super block, wherein the super block comprises a plurality of blocks respectively located in at least two planes; if the second code bank is read successfully, storing the second code bank into the buffer memory to replace the first code bank; and executing the second code bank to manage the flash memory module.

According to another one embodiment of the present invention, an electronic device comprising a flash memory module and a flash memory controller is disclosed. The flash memory module comprises a plurality of planes, each plane comprises a plurality of blocks, and each block comprises a plurality of pages. The flash memory controller is configured to perform the steps of: after the flash memory controller is powered on, reading a first code bank from a specific block of the plurality of blocks; storing the first code bank into a buffer memory; executing the first code bank to manage the flash memory module; when the flash memory controller starts a code bank swapping operation, trying to read a second code bank from a super block, wherein the super block comprises a plurality of blocks respectively located in at least two planes; if the second code bank is read successfully, storing the second code bank into the buffer memory to replace the first code bank; and executing the second code bank to manage the flash memory module.

DETAILED DESCRIPTION

FIG.1is a diagram illustrating an electronic device100according to an embodiment of the present invention. The electronic device100includes a flash memory module120and a flash memory controller110. The flash memory controller110is configured to access the flash memory module120. According to the present embodiment, the flash memory controller110includes a microprocessor112, a read only memory (ROM)112M, a control logic114, a buffer memory116and an interface logic118. The read only memory112M is configured to store a code112C, and the microprocessor112is configured to execute the code112C to control access of the flash memory module120. The control logic114includes an encoder132and a decoder134, wherein the encoder132is configured to encode data which is written in the flash memory module120to generate a corresponding check code (also known as an error correction code (ECC)), and the decoder134is configured to decode data read from the flash memory module120.

In a general situation, the flash memory module120includes a plurality of flash memory chips, and each flash memory chip includes a plurality of blocks. The flash memory controller110performs a block-based erase operation upon the flash memory module120. In addition, a block can record a specific number of pages, wherein the flash memory controller110performs a page-based write operation upon the flash memory module120. In the present embodiment, the flash memory module120is a 3D NAND-type flash memory module, but it's not a limitation of the present invention.

Specifically, through the microprocessor112executing the code112C, the flash memory controller110may use its own internal components to perform many control operations. For example, the flash memory controller110uses the control logic114to control access of the flash memory module120(especially access of at least one block or at least one page), uses the buffer memory116to perform a required buffering operation, and uses the interface logic118to communicate with a host device130. The buffer memory116is implemented by a random access memory (RAM). For example, the buffer memory116may be a static RAM (SRAM), but the present invention is not limited thereto.

In one embodiment, the electronic device100may be a portable memory device such as a memory card which conforms to one of the SD/MMC, CF, MS and XD specifications, and the host device130is another electronic device able to be connected to the electronic device100, such as a cellphone, a laptop, a desktop computer, etc. In another embodiment, the electronic device100may be a solid state drive (SSD) or an embedded memory device which conforms to the universal flash storage (UFS) specification or embedded Multi Media Card (EMMC) specification, and can be arranged in a cellphone, a laptop or a desktop computer. At this time, the host device130can be a processor of the cellphone, a processor of the laptop or a processor of the desktop computer.

FIG.2is a diagram illustrating a block200of the flash memory module120according to an embodiment of the present invention, wherein the flash memory module120is a 3D NAND-type flash memory module. As shown inFIG.2, the block200includes a plurality of memory cells, such as floating gate transistors202shown inFIG.2or other charge trapping components. A 3D NAND-type flash memory structure is formed through a plurality of bit lines (only BL1-BL3are shown inFIG.2) and a plurality of word lines (e.g., WL0-WL2, WL4-WL6and following word lines shown inFIG.2). Taking a top plane inFIG.2as an example, all floating gate transistors on the word line WL0form at least one page, all floating gate transistors on the word line WL1format least another one page, and so on. In addition, the definition between the word line WL0and the page (logic page) may vary depending on a writing method of the flash memory. In detail, when data are stored using a single-level cell (SLC) means, all floating gate transistors on the word line WL0correspond to only one logic page; when data are stored using a multi-level cell (MLC) means, all floating gate transistors on the word line WL0correspond to two logic pages; when data are stored using a TLC means, all floating gate transistors on the word line WL0correspond to three logic pages; and when data are stored using a QLC means, all floating gate transistors on the word line WL0correspond to four logic pages. The 3D NAND-type flash memory structure and the relationship between word lines and pages are obvious to those skilled in the art. For simplification, no further illustration is provided.

In addition, the flash memory module120stores an ISP code, and the ISP code serves as a firmware code for the flash memory controller110to load and execute. Specifically, when the electronic device100is powered on, the microprocessor112within the flash memory controller110will read the code112C within the ROM112M to initialize the electronic device100and perform some basic operations. After the code112C is executed, the flash memory controller110reads part of the ISP code from a specific block within the flash memory module120, then the flash memory controller110executes the ISP code to control and manage the flash memory module120. As described in the prior art, the ISP code may be divided into several code banks, and flash memory controller110loads only part of the code banks due to the limited size of the buffer memory116(for example, the buffer memory116is 128 KB, two 64 KB code banks or four 32 KB code banks can be stored in the buffer memory116), so the flash memory controller needs to swap the code bank based on the required functions to be used, thereby the specific block storing the code banks will be read frequently, causing read disturbance and affecting data quality. To solve this problem, the embodiment provides an arrangement of the code banks and a method of loading the code banks, to increase the robustness of the code banks and increase the speed of swapping code banks.

Specifically,FIG.3shows the code banks stored in the flash memory module120according to one embodiment of the present invention. As shown inFIG.3, the flash memory controller120comprises a plurality of flash memory chips310_1-310_N, and each of the flash memory chips310_1-310_N may be divided into several planes such as two planes or four planes. In this embodiment, each flash memory chip has two planes, that is, the flash memory chips310_1has two planes312_1and314_1, and the flash memory chips310_N has two planes312_N and314_N. In addition, each plane has many blocks, and the block B0of the plane312_1serves as the specific block to store the ISP code (code banks), and the flash memory controller110configures part of the other blocks belonging to different planes in the flash memory module120into a super block to facilitate the management of data access. Specifically, the block B0of the plane312_1serving as the specific block does not belong to any super block, that is the flash memory controller110reads the block B0by using one-plane-read operations. The flash memory controller110configures blocks B1of all planes312_1,314_1, . . . ,312_N and314_N as a super block350, and configures blocks B2of all planes312_1,314_1, . . . ,312_N and314_N as a super block360, and so on. The super block350/360comprises many physical blocks, and the flash memory controller110treats the super block350/360as a normal block when accessing the super block350/360. For example, the super block350/360itself is an erasing unit, that is, although many blocks B1/B2of the super block350/360can be erased separately, the flash memory controller110must erase all the blocks B1/B2together. In addition, the super block is a logical block set by the flash memory controller110to facilitate management of the storage space, and is not a physical block. In addition, the flash memory controller110can read the super block350/360by using multi-plane-read operations.

In one embodiment, the super block350/360supports the garbage collection mechanism, that is the flash memory controller110can determine if performing the garbage collection operation upon the super block350/360according to some information such as data quality of the super block350/360or a read count of the super block350/360; however, the block B0does not support the garbage collection mechanism, that is the flash memory controller110does not add the block B0into a garbage collection queue. In one embodiment, the super block350/360has redundant array of independent disks (RAID) mechanism, that is if the flash memory controller110fails to read one block of super block350, the flash memory controller110can read the other blocks of super block350to recover data of the one block; however, because the block B0does not belong to any super block, the flash memory controller110cannot use the RAID mechanism to recover the data of the block B0if the block B0cannot be read.

In addition, one or more super blocks may be used to store the management information such as logical address to physical address mapping tables, physical address to logical address mapping tables and other tables, and the super block configured to store these tables is named as a meta block. In the following description, the super block350serves as the meta block. In this embodiment, the flash memory controller110can copy the ISP code in the block B0to the super block350, that is the flash memory controller110can use the single-plane-read operation to read the ISP code from the block B0, and the flash memory controller110can also use the multi-plane-read operation to read the ISP code from the super block350.

FIG.4shows the ISP code stored in the block B0according to one embodiment of the present invention. As shown inFIG.4, it is assumed that the ISP code is divided into two code banks, a first code bank is stored in pages P0-P3(i.e., CB11-CB14), and a second code bank is stored in pages P4-P7(i.e., CB21-CB24).FIG.5shows the ISP code copied from the block B0to the super block350according to one embodiment of the present invention. As shown inFIG.5, CB11-CB14are written into pages P0of the blocks B1of the planes312_1,314_1,312_2and314_2, respectively, wherein the pages P0of the planes form a super page510; and CB21-CB24are written into pages P1of the blocks B1of the planes312_1,314_1,312_2and314_2, respectively, wherein the pages P1of the planes form a super page520. The super page510/520comprises many physical pages, and the flash memory controller110treats the super page510/520as a normal page when accessing the super page510/520. For example, super page510/520itself is a writing unit. In addition, the super page is a logical page set by the flash memory controller110to facilitate management of the storage space, and is not a physical page.

In one embodiment, the super page510/520may further have a parity page if the decoder134supports the RAID mechanism. For example, the super page510may have five pages, wherein the five pages comprise CB11-CB14and a parity page.

FIG.6is a flowchart of a control method of the flash memory controller110and the flash memory module120according to one embodiment of the present invention. In Step600, the flow starts, and the electronic device100is powered on, and the microprocessor112loads the code112C from the ROM112M. In Step602, the microprocessor112executes the code112C to read one of the code banks from the block B0, and stores the code bank into the buffer memory116. For example, the microprocessor112may read the pages P0-P3of the block B0to obtain the first code bank CB11-CB14, and stores the first code bank CB11-CB14into the buffer memory116. At this time, the other code banks such as the second code bank CB21-CB24are not loaded due to the limited size of the buffer memory116. In Step604, the initialization procedure has been completed, and the microprocessor112can execute the first code bank CB11-CB14(firmware) to manage the flash memory module120.

In Step606, the microprocessor112determines if swapping the code bank, if yes, the flow enters Step608; and if not, the flow stays in Step606. Specifically, because the functions of the first code bank and the second code bank are not the same, if the microprocessor112needs to perform the operation corresponding to the second code bank, the microprocessor112needs to load the second code bank from the flash memory module120to replace the first code bank temporarily stored in the buffer memory116.

In Step608, the microprocessor112refers to a meta pointer to determine if the super block350(i.e., the meta block) has the second code bank that is to be swapped, if yes, the flow enters Step616; and if not, the flow enters Step610.

In Step610, the microprocessor112reads the pages P4-P7of the block B0to obtain the second code bank CB21-CB24, and stores the second code bank CB21-CB24into the buffer memory116. At this time, the first code bank CB11-CB14is removed from the buffer memory116.

In Step612, the microprocessor112reads the code banks from the block B0, and writes the code banks into the super block350. In Step614, the code bank swapping operation completed, and the flow goes back to Step606to determine if swapping the code banks.

In Step616, the microprocessor616tries to read the second code bank CB21-CB24from the super page520of the super block350. In Step618, the microprocessor112determines if the second code bank CB21-CB24is successfully read from the super block350, if yes, the flow enters Step620; and if not, the flow enters Step610.

In Step620, the microprocessor112determines if the data stored in the super page520is unstable, if yes, the flow enters Step612; and if not, the flow enters Step614. Specifically, the microprocessor112can determine if the data stored in the super page520is unstable based on a decoding step or a bit error count. For example, if the decoder134cannot use a hard decode to decode the data read from the super page520to obtain the second code bank CB21-CB24, the microprocessor112can determine that the data stored in the super page520is unstable. In another example, if the bit error count of the data read from the super page520is greater than a threshold, the microprocessor112can determine that the data stored in the super page520is unstable.

In the embodiment shown inFIG.6, because the block B0is only read during initialization procedure and when the code banks cannot be read from the super block350, the read count of the block B0can be greatly reduced, and the read disturbance of the block B0can be improved. In addition, because the flash memory controller110can manage the super block350by using garbage collection mechanism, read reclaim mechanism, read retry mechanism, RAID decoding mechanism, it is rare for the block B0to be unreadable. Furthermore, because the first/second code bank is sequentially stored in the block B0while the first/second code bank is stored in the super page510in parallel, the speed of reading the first/second code bank from the super page510/520is about four times faster than the speed of reading the first/second code bank from the block B0, that is the embodiment can increase the speed of swapping the code banks.

In one embodiment, regarding Step618, if the decoder134fails to use a default read mechanism to read the second code bank CB21-CB24from the super block350, the microprocessor112and the decoder134enter an error handling mechanism to determine if the second code bank CB21-CB24can be successfully read from the super block350, and the decoder134refers to a setting to determine if using the hard decoding method, the soft decoding method, and/or the RAID decoding method to retry the decoding steps. In this embodiment, the hard decoding method may be a Bose-Chaudhuri-Hocquenghem (BCH) decoding method or a low-density parity-check (LDPC) decoding method, the soft decoding method may be LDPC decoding method for decoding readout information obtained by using predetermined read voltages and adjusted read voltages. Specifically, refer toFIG.7, which shows the error handling mechanism according to one embodiment of the present invention. In Step700, the flow starts and enters the error handling mechanism. In Step702, the microprocessor112determines if the setting indicates skipping the hard decoding method, if yes, the flow enters Step706; and if not, the flow enters Step704. In Step704, the decoder134uses the hard decoding method to decode the data read from the super block350, and the decoder134determines if the data can be successfully decoded, if yes, the flow enters Step716; and if not, the flow enters Step706.

In Step706, the microprocessor112determines if the setting indicates skipping the soft decoding method, if yes, the flow enters Step710; and if not, the flow enters Step708. In Step708, the decoder134uses the soft decoding method to decode the data read from the super block350, and the decoder134determines if the data can be successfully decoded, if yes, the flow enters Step716; and if not, the flow enters Step710.

In Step710, the microprocessor112determines if the setting indicates skipping the RAID decoding method, if yes, the flow enters Step714; and if not, the flow enters Step712. In Step712, the decoder134uses the RAID decoding method to decode the data read from the super block350, and the decoder134determines if the data can be successfully decoded, if yes, the flow enters Step716; and if not, the flow enters Step714.

In Step714, the microprocessor112determines that the code bank cannot be successfully read from the super block350, and a code bank fail flag is set for the microprocessor112to read the code banks from the block B0, and to write the code banks into the super block350.

In Step716, the microprocessor112determines that the code bank can be successfully read from the super block350, and a code bank risky flag is set for the microprocessor112to determine if the code bank stored in the super block350is unstable.

In one embodiment, because the soft decoding method needs to use additional voltages to read the memory cells, and the RAID decoding method needs to read parity page in other planes, the setting may skip these two decoding methods to increase the speed of swapping the code banks. In one embodiment, the hard decoding method may also be skipped to further improve the speed.

Briefly summarized, in the embodiments of the present invention, by arranging the code banks in the specific block and the super block, and using the code banks stored in the super block for the code bank swapping operation, the read count of the specific block can be greatly reduced, and the read disturbance of the specific block can be improved. In addition, because the code banks are sequentially stored in the specific block while the code banks are stored in the super blocks in parallel, the speed of reading the code banks from the super block is faster than the speed of reading the code banks from the specific block, that is the speed of swapping the code banks is increased.