Reducing effects of parasitic transistors in thyristor-based memory using local thinning or implanting

Method and apparatus for an integrated circuit having memory including thyristor-based memory cells is described. A pair of the thyristor-based memory cells are commonly coupled via a bitline region, where a parasitic bipolar junction transistor is defined therebetween responsive to the bitline region being common. In another implementation, the pair of the thyristor-based memory cells are commonly coupled via the anode region, where a parasitic bipolar junction transistor is defined therebetween responsive to the anode region being common. The common bitline or anode region, respectively, has a locally thinned region to inhibit charge transfer between the pair via the parasitic bipolar junction transistor. Moreover, a method for forming a field-effect transistor on a silicon-on-insulator wafer is described, where charge transfer facilitated by a parasitic bipolar transistor is reduced responsive to an increase in dopants at least proximate to an insulator layer.

FIELD OF THE INVENTION

One or more aspects of the present disclosure relate generally to semiconductor devices and, more particularly, to integrated circuits with thyristor-based memory cells.

BACKGROUND OF THE INVENTION

Conventionally, semiconductor memories such as static random access memory (“SRAM”) and dynamic random access memory (“DRAM”) are in widespread use. DRAM is very common due to its high density with a cell size typically between 6F2and 8F2, where F is a minimum feature size. However, DRAM is relatively slow, having an access time commonly near 20 nanoseconds (“ns”). Though SRAM access time is typically an order of magnitude faster than DRAM, an SRAM cell is commonly made of four transistors and two resistors or of six transistors, leading to a cell size of approximately 60F2to 100F2.

SRAM memory designs based on a negative differential resistance cell, such as a thyristor-based memory cell, have been introduced to minimize the size of a conventional SRAM memory. A thyristor-based memory may be effective in stand-alone and embedded memory applications. Examples of thyristor-based memory cells are described in additional detail in U.S. Pat. Nos. 6,767,770 B1, 6,686,612 B1, 6,690,039 B1, 6,815,734 B1, and 6,818,482 B1.

Unfortunately, parasitic transistors, whether existing internally to a thyristor-based memory cell (“intra-cell parasitic transistors”) or created by thyristor-based memory cells connected together in an array (“inter-cell parasitic transistors”) may negatively impact performance. For example, an inter-cell parasitic transistor may facilitate charge to be transferred from one thyristor-based memory cell to another commonly coupled thereto. Charge from one thyristor-based memory cell injected into an adjacent thyristor-based memory cell may make the adjacent memory cell less stable or may make both memory cells less stable. Moreover, an intra-cell parasitic transistor may undesirably impact stability or operability of a thyristor-based memory cell by facilitating unwanted charge transport within such cell.

Accordingly, it would be desirable and useful to provide means to reduce one or more effects of parasitic transistors associated with one or more thyristor-based memory cells of a thyristor-based memory array.

SUMMARY OF THE INVENTION

An aspect of the invention is an integrated circuit having memory, including thyristor-based memory cells, where each of the thyristor-based memory cells includes a thyristor-based storage element and an access transistor. The thyristor-based storage element includes an anode region and a cathode region. A pair of the thyristor-based memory cells are commonly coupled via a bitline region associated with the access transistor. The pair of the thyristor-based memory cells define a parasitic bipolar junction transistor therebetween responsive to the bitline region being common. The bitline region has a locally thinned region to inhibit charge transfer between the pair via the parasitic bipolar junction transistor.

Another aspect of the invention is an integrated circuit having memory, including thyristor-based memory cells, where each of the thyristor-based memory cells includes a thyristor-based storage element and an access transistor. The thyristor-based storage element includes an anode region and a cathode region. A pair of the thyristor-based memory cells are commonly coupled via the anode region. The pair of the thyristor-based memory cells define a parasitic bipolar junction transistor therebetween responsive to the anode region being common. The anode region has a locally thinned region to inhibit charge transfer between the pair via the parasitic bipolar junction transistor.

Yet another aspect of the invention is a method for forming a field-effect transistor on a silicon-on-insulator wafer, including: forming source/drain regions of the field-effect transistor responsive to a first implant, the first implant targeted to a first depth within a silicon layer of the silicon-on-insulator wafer; the source/drain regions disposed on opposite sides of a body region of the field-effect transistor, where the field-effect transistor defines a parasitic bipolar transistor; and implanting the source/drain regions responsive to a second implant targeted to a second depth greater than the first depth, where the second implant is configured to increase dopants at least proximate to an insulator layer of the silicon-on-insulator wafer. Charge transfer facilitated by the parasitic bipolar transistor is reduced responsive to the increase in dopants at least proximate to the insulator layer.

Still yet another aspect of the inventions is a method for forming a field-effect transistor on a silicon-on-insulator wafer. Source/drain regions of the field-effect transistor are formed responsive to a single implant targeted to a depth within a bottom half of a silicon layer of the silicon-on-insulator wafer. The source/drain regions are disposed on opposite sides of a body region of the field-effect transistor. The field-effect transistor is adjacent to at least one of another field-effect transistor or a thyristor-based storage element to form a parasitic bipolar transistor. Charge transfer facilitated by the parasitic bipolar transistor is reduced responsive to the increase in dopants at least proximate to an insulator layer of the silicon-on-insulator wafer.

DETAILED DESCRIPTION OF THE DRAWINGS

One or more aspects of the invention may be applicable to a variety of different types of semiconductor devices, and may be particularly suited for silicon-on-insulator (“SOI”) devices, such as thyristor-based memory devices, and for enhancing the ability to form such devices. While the present disclosure is not necessarily limited to such devices, various aspects of the invention may be appreciated through a description of various examples using this context.

FIG. 1Ais a cross-sectional view depicting an exemplary embodiment of a thyristor-based memory cell array (“memory array”)100. Memory array100may be formed on a semiconductor wafer155. In this example, semiconductor wafer155is an SOI wafer, as some parasitic transistors described elsewhere herein are associated with use of SOI wafers. However, it should be appreciated that memory array100may be formed on a bulk semiconductor wafer, such as a bulk silicon wafer, and thus those parasitic transistors generally associated with SOI wafers may be avoided. Moreover, it should be understood that semiconductors other than silicon may be used.

SOI wafer155includes a substrate124on which a buried oxide (“BOx”) layer131is formed. Substrate124is omitted in subsequent figures herein to avoid unnecessary detail. Over BOx layer131is formed silicon layer141. Silicon layer141may have n-type or p-type dopants. In the example described herein, silicon layer141is a p-type layer, although an n-type layer may be used. More particularly, in the example described herein, silicon layer141is has a p− dopant concentration, though other doping concentrations may be used.

In the cross-sectional view ofFIG. 1A, thyristor-based memory cells (“memory cells”)150and160, generally indicated by associated dashed boxes, are illustratively shown as having a common reference voltage line contact109. Notably, formation of some spacers, silicides, and other known details regarding memory cells150and160are omitted for purposes of clarity.

Reference voltage line contact109may be for coupling memory cells150and160to a reference voltage source. Reference voltage line contact109is coupled to anodic region101, which is common to both of memory cells150and160. Region101is referred to as an “anodic” region or anode herein, as current is sourced via region101for a memory cell, such as memory cell150for example. In this example, anode101is a p-type region having a p+ dopant concentration formed in silicon layer141. As memory cells150and160are similarly constructed, only one is described in detail herein to avoid unnecessary repetition.

Memory cell150includes a thyristor-based storage element (“storage element”)170. Storage element170is coupled to an access device, such as a field effect transistor (“access transistor”)171. Storage element170may be coupled to access transistor171at a common region, namely, region104. Region104is referred to as a “cathodic” region or cathode, as current passing through storage element170may be output via cathode104. In this embodiment, cathode104may be an n-type region having an n+ dopant concentration formed in silicon layer141. Cathode104may be referred to as a source/drain node of access transistor171.

Storage element170includes base regions102and103. In this example, base region102is an n-type base region (“n-base”)102, and base region103is a p-type base region (“p-base”)103.

In addition to source/drain region104, access transistor171includes source/drain region106and transistor body region105. In this exemplary embodiment, source/drain region106is an n-type region having an n+ dopant concentration formed in silicon layer141, and transistor body region105is a p-type region having a p dopant concentration formed in silicon layer141. Accordingly, transistor body region105may be referred to herein as p-well105. Source/drain region106may be coupled to a bitline, as described elsewhere herein, of memory array100, and accordingly may be referred to herein as bitline region106.

One or more dielectric layers may be formed over a top surface of silicon layer141to provide gate dielectrics107A and107B. Notably, gate dielectrics107A and107B may be the same or different. Formed over gate dielectric107B and generally above n-base102and partially over gate110is a dielectric offset spacer111.

Formed above gate dielectrics107A and107B are wordlines. For memory array100, included are two types of wordlines, namely WL2sfor directly accessing storage elements170thereof and WL1sfor directly accessing access transistors171thereof. WL1sare formed over gate dielectric107A and WL2sare formed over gate dielectric107B. At locations along such WL1sand WL2s, below which are p-wells105and p-bases103, respectively, defined gates are formed above gate dielectrics107A and107B, respective. Thus, continuing the example of memory cell150, disposed above gate dielectric107A in access transistor171is a gate108formed of a portion of a WL1, and disposed above gate dielectric107B in storage element170is a gate110formed of a portion of a WL2. Gate108is referred to herein as an access gate as it is associated with an access device, such as access transistor171, for accessing a memory cell, and gate110is referred to herein as a control gate as it is associated with controlled access to a storage element170for writing a logic 1 or a logic 0 to a memory cell.

Because memory cells150and160share reference line contact109and thus anode101, a parasitic bipolar junction transistor (“BJT”)125is formed, as is illustratively shown inFIG. 1Aby heavy dashed lines. Parasitic BJT125is formed of n-base102of memory cell160, anode101common to both memory cells150and160, and n-base102of memory cell150. Accordingly, parasitic BJT125is an inter-cell parasitic transistor. Transport of charge from one memory cell to another, such as from memory cell150to memory cell160, is undesirably facilitated by parasitic BJT125. Thus, data state in one memory cell, such as memory cell150or160, may be influenced by data state in the other memory cell, such as memory cell160or150. Accordingly, charge may be transferred in either direction via BJT125as between common anode memory cells.

As is known with respect to formation of field effect transistors (“FETs”) using SOI wafers, each FET may include a co-existing BJT. So, for each access transistor171being an FET, there is a corresponding, co-existing parasitic BJT126. BJT126is formed of source/drain104, p-well105, and bitline region106of access transistor171.

Having parasitic BJT126in parallel with access transistor171may cause charge to be injected from memory cell150to a neighboring memory cell commonly coupled via bitline region106, as illustratively shown in the cross-sectional view depicted inFIG. 1B.

FIG. 1Bis a cross-sectional view depicting an exemplary embodiment of memory array100having memory cells150and180commonly coupled via bitline region106. A common bitline contact119is coupled to bitline region106. Memory cell180is formed as previously described with reference to memory cell150, and thus such description is not repeated.

In the example ofFIG. 1B, parasitic BJT126may undesirably facilitate injection of charge from memory cell150into p-well105of memory cell180via common bitline region106. This injected charge may undesirably go into or through cathode104of memory cell180. Accordingly, such injection of charge may undesirably impact data stored in a common bitline-neighboring memory cell. Furthermore, parasitic BJT126may undesirably facilitate injection of holes into p-well105of access device171. Injection of holes into a p-well105of a bitline-neighboring memory cell or of a memory cell in which such parasitic BJT126is located may increase sub-threshold voltage leakage current of NMOS access transistor171. This increase in sub-threshold voltage leakage may undesirably impact data stored in a bitline-neighboring memory cell, such as memory cell180with respect to memory cell150for example, or the memory cell in which such parasitic BJT126is located, such as memory cell150for example.

Furthermore, by sharing a common bitline region106, memory cells150and180form a parasitic BJT127. Parasitic BJT127is formed of p-wells105of adjacent access transistors171and common bitline region106. BJT127may undesirably facilitate charge transport from one memory cell to another memory cell coupled to the same bitline. For example, data state in memory cell150may be undesirably influenced by data state in memory cell180owing to charge transport facilitated via parasitic BJT127.

With simultaneous reference toFIGS. 1A and 1B, another parasitic BJT128is described. Parasitic BJT128results from a thyristor-based memory cell, such as any of memory cells150,160, and180, with an access transistor171coupled to a storage element170via a common cathode104. Parasitic BJT128is formed of p-well105, common cathode104, and p-base region103of a memory cell. Parasitic BJT128may undesirably facilitate charge transport from p-base region103through cathode104to p-well105of access transistor171, which may undesirably impact a data state stored in the memory cell associated with such parasitic BJT128. In other words, parasitic BJT128may undesirably facilitate charge leakage from the memory cell in which such parasitic BJT128is located. Furthermore, charge may be injected in the opposite direction, i.e., into the memory cell, as undesirably facilitated by the parasitic BJT128located therein. For example, charge injected from common bitline region106into p-well105may be further injected as facilitated by parasitic BJT128into p− base region103. Such injection of charge may undesirably impact a stored data state in the memory cell in which BJT128is located. A junction between region105and106may be forward biased, and thus electrons may be injected into region106. These electrons may thus be injected into the memory cell through bipolar transistor128.

For purposes of clarity, parasitic BJTs125,126,127, and128may be respectively referred to herein as anode BJT125, FET BJT126, bitline BJT127, and storage node BJT128. It should be understood that anode BJT125and bitline BJT127are inter-cell parasitic BJTs, owing to a common contact region as between memory cells. FET BJT126and storage node BJT128are formed in a thyristor-based memory cell, such as memory cell150, and as such are referred to as intra-cell parasitic BJTs.

For purposes of clarity, it shall be assumed that memory cells150,160, and180are formed in part as described below with known processing steps being omitted for purposes of clarity. Moreover, it should be understood that processing as described below may be implemented in whole or in part, and some embodiments are alternatives of other embodiments. Thus, memory cells150,160, and180may be formed with one or more of the processing technologies described below to reduce or eliminate unwanted affects of one or more parasitic BJTs125,126,127, and128.

It should be understood that collector current, namely injected current, for a BJT is proportional to the inverse of the amount of dopants present. In other words, the dominant current path is the more lightly doped portion. Thus, by increasing the amount of dopants in a region, or targeted portion thereof, such injected current may be reduced.

InFIG. 2A, there is shown a cross-sectional view depicting an exemplary embodiment of a deep n+ region implant for memory array100. As illustratively shown, p-wells105, gate dielectrics107A and107B, offset spacers111, gates110, gates108, extension regions156, “zero” spacers123, and sidewall spacers129have been already been formed as is known. Notably, only one bitline region106is illustratively shown inFIG. 2A, as only a portion of memory array100is shown for purposes of clarity. However, though reference to a bitline region106is made, it should be understood to include multiple bitline regions. Regions102,104, and106are formed responsive to implants into silicon layer141extending from top surface140to bottom surface142of silicon layer141.

In the example ofFIG. 2A, a mask143is used to mask off n-base regions102, leaving top surface140of silicon layer141exposed with respect to location of cathodes104and bitline region106. Implant152may follow immediately after implant151. One of implants151and152is to provide a deeper implant than the other. For purposes of clarity by way of example and not limitation, it shall be assumed that implant152is a deeper implant than implant151. Implants151and152may each be of an n-type material to create at least initially an n concentration in regions104and106. Implant151is used to at least initially form n-base cathodes104and bitline region106. Implant152is used in regions104and106to increase dopant concentration at least proximate to bottom surface142of silicon layer141, such as generally at locations154for example.

Alternatively, an n+ concentration implant151may be provided to memory array100. Implant151may be followed implant152, again where one of implants151and152is deeper than the other. For purposes of clarity by way of example and not limitation, it shall be assumed that implant152is deeper than implant151. Implants151and152provide regions104and106with an n+ concentration. Thus, it should be appreciated that n-base regions102, which are masked for implants151and152, may be formed with an n concentration and bitline region106and cathodes104may have an n+ concentration for this exemplary embodiment. Notably, anode regions101ofFIGS. 1A and 1Bmay be subsequently formed as is known.

FIG. 2Bis a graphical diagram depicting exemplary implant profiles for implants associated withFIG. 2A. Along depth of implant axis137D, as associated with thickness137of silicon layer141, locations of a top surface140and a bottom surface142are graphically indicated. Location of a peak concentration as indicated with dopant concentration axis138of implant profiles for implants151and152is within thickness137of silicon layer141. Implant151provide a Gaussian distribution approximately centered to or just below the center of thickness of silicon layer141ofFIG. 2A. The implantation profile of implant152is shown with a dashed line to delineate its profile from the profile of implant151. As graphically indicated, though both implantation profiles generally have a Gaussian distribution, the implantation profile associated with implant152has its peak closer to bottom surface142than the implantation profile of implant151.

Notably, it should be appreciated that doping is generally not uniform through the thickness of a silicon layer, but is more generally along the lines of a Gaussian distribution. Charge transport is generally most effective through the lightest doped regions. Accordingly, without the addition of an implant152, there would be a light distribution of n-type ions in near proximity to top surface140and bottom surface142of silicon layer141. At or near top surface140of silicon layer141, a low n-type concentration provides means for facilitating charge transfer in this region for operation of memory array100. With respect to the lighter distribution in near proximity to bottom surface142of silicon layer141, however, such a lightly doped path would facilitate charge transfer of parasitic BJTs mentioned elsewhere herein. Accordingly, by adding implant152, this concentration of n-type dopants in near proximity to bottom surface142is increased, which results in a reduction in charge transport along or near bottom surface142of silicon layer141. Referring back toFIGS. 1A and 1B, it should be appreciated that each of parasitic BJTs125,126,127, and128is effectively inhibited from parasitic charge transfer owing to the addition of implant152.

Notably, though implant152may be added to have more n-type ions concentrated at or in near proximity to bottom surface142of silicon layer141for bitline region106, implant152may be omitted, as implant150may be sufficient to inhibit charge transfer of parasitic BJTs126and127.

Notably, at or near the mid-point of thickness137of silicon layer141, n-type concentration is high owing to implant151, and thus charge transfer is inhibited in this region. At or near top surface140of silicon layer141, n-type concentration remains low owing to implant151being targeted more toward the middle thickness of silicon layer141. As described above, such low concentration facilitates charge transfer in this region for operation of memory array100.

For an approximately 80 to 100 nanometer (“nm”), thickness137of silicon layer141, Table 1 below provides example materials, approximate dosages ranges, where for example 1-8 E15means a range of approximately 1×1015to 8×1015at/cm2, and approximate energy levels for implants for the embodiment described with reference toFIG. 2A.

Notably, dopants that diffuse more readily in silicon than arsenic, such as phosphorus or another dopant from the same column in the Periodic Table of Elements, may be used. Alternatively, or in addition to one or more of the embodiments described with respect toFIG. 2A, a silicon layer141thinning etch153, as illustratively shown inFIG. 3A, may be used to reduce the effect of one or more of parasitic BJTs125through128. Moreover, rather than having implant151followed by implant152, a single implant151may be used. For an implementation of a single implant151, arsenic may be implanted with a dosage range of approximately 1×1015to 8×1015at/cm2for an energy in a range of approximately 40 to 80 keV for targeting to approximately the bottom half of silicon layer141.

FIG. 3Ais a cross-sectional view depicting an exemplary embodiment of a silicon layer141thinning etch153of memory array100. A known anisotropic dry or wet etch of silicon, or oxidation and wet etching, may be used for etch153. Etch153may be used to thin only bitline region106, or it may be used to thin regions101,104, and106as illustratively shown inFIG. 3A. Notably, thinning etch153may etch, though slightly, spacers111,123, and129, but will more readily etch polysilicon gates108and110and exposed regions of silicon layer141, namely anode regions101, cathodes104, and bitline region106. Regions101,104, and106, as well as gates108and110, may be thinned responsive to silicon etch153for this example.

Subsequent silicidation of regions101,104, and106as well as polysilicon gates108and110may be used to restore height removed via thinning etch153, as generally indicated inFIG. 3B.FIG. 3Bis a cross-sectional view depicting memory array100ofFIG. 3Awith silicide regions160. Silicide regions160may be conventionally formed salicides (“salicide regions”) responsive to annealing deposited metal on exposed portions of regions101,104, and106, as well as gates108and110.

By thinning silicon layer141in regions101,104, and106, recombination of charge flowing near salicide regions160associated with regions101,104, and106is impacted. Thus, locally thinned and partially salicided regions101,104, and106facilitate minority carrier movement, namely of holes in n-type regions104and106and of electrons in p-type regions101in this example, to be proximate to salicides. In other words, the region between bottom surface142and the bottom of salicide regions160is narrowed by locally thinning silicon layer141in regions101,104, and106. Because minority carriers in these locally thinned regions are transported closer to salicide regions160, charge recombination is more likely, which means charge injection facilitated by parasitic BJTs125through128described elsewhere herein is reduced. For a silicon layer141of approximately 100 nm, silicon layer141may be thinned down to approximately 50 to 80 nm for subsequent silicidation.

FIGS. 4A and 4Bare cross-sectional views depicting an alternative embodiment of the embodiment illustratively shown with reference toFIGS. 3A and 3B. InFIG. 4A, after local thinning of silicon layer141in regions101,104, and106, as illustratively shown inFIG. 3A, a mask157is formed over memory array100. Mask157leaves exposed locally thinned bitline region106and covers, among other things, regions101and104, as well as gates108and110. Mask157is for a patterned etch158of bitline region106. A known dry or wet etch, which is generally an anisotropic etch, may be used for etch158. Etch158is for further local thinning of bitline region106. Thus, for example, portion199, as generally indicated by a dashed circle, of bitline region106has a thinner profile than portion189, also generally indicated by a dashed circle, of anode region101.

FIG. 4Bis the cross-sectional view ofFIG. 4Aafter forming salicide regions160. Notably, because regions160may be formed as self-aligned silicides, they may be referred to as salicide regions160. Because a salicide region160formed from silicon of bitline region106extends to BOx layer131, charge flowing through bitline region106is more likely to be recombined. In other words, minority carriers, the flow of which is facilitated by parasitic BJTs126and127ofFIG. 1B, pass through salicide region160of bitline region106in this embodiment. For a silicon layer141of approximately 100 nm, silicon layer141may be thinned down to approximately 25 to 60 nm for subsequent silicidation of bitline region106. Notably, only one bitline region106and one corresponding salicide region160formed therein are illustratively shown inFIG. 4B, as only a portion of memory array100is shown for purposes of clarity. However, memory array100should be understood to include multiple bitline regions and multiple salicide regions160formed therein in this embodiment.

FIG. 5is a cross-sectional view depicting an exemplary embodiment of a threshold voltage (Vt) adjustment implant159of memory array100for forming shallow implant regions165. More particularly, a Vt-adjust implant mask163is formed to cover region103and to cover substantial portions of104and106. Notably, regions101,102,104and106, which are formed in silicon layer141, have not yet been formed at this point in time. However, to indicate a relationship between location of implant mask163and regions104and106, approximate locations of regions104and106are indicated in dashed-lines. Notably, by substantially masking regions104and106, counter-doping from implant159, such as an implant of boron, is significantly reduced with respect to bitline region106and cathodes104. For example, implant159may be boron implanted into approximately 100 nm thick silicon with a dosage in a range of approximately 5E11 to 1E14 at/cm2with implant energy of less than approximately 40 keV.

FIG. 6is a cross-sectional view depicting an exemplary embodiment of memory array100with a heavy ion implant169. Heavy ion implant169is to create a damaged region167in silicon layer141. Damaged region167, which is formed dividing bitline contact region106, is exposed and other portions of memory array100are protected by mask157. Notably, edges of mask157may be located above gates108for lateral control of the profile of damage region167versus the lateral profile of the junction between regions105and106. Additionally, opening up mask157edges to be above gates108may provide additional control for forming damage or recombination region167. Accordingly, each bitline region106may have a damaged region167. Damaged region167may be formed before or after a source/drain anneal, but is formed before silicidation of bitline region106. While not wishing to be bound by theory, it is believed that damaged region167creates electron trap levels.

Notably, implant169may be perpendicular to top surface140of silicon layer141or may be done at another angle with respect to top surface140up to approximately a 45 degree angle. By creating damaged region167, the likelihood of a conductive path, such as from p-well105of one memory cell to a p-well105of an adjacent memory cell is substantially reduced, and thus the effect of parasitic BJT127ofFIG. 1Bis substantially reduced. Heavy ion implant169may be done with any of a variety of known heavy ions having a mass greater than or equal to the atomic mass of silicon, or of at least approximately 28 atomic mass units, such as heavy ions from column IVa or VIIIa of the Periodic Table of the Elements, or a cluster or compound of such ions, including xenon or germanium.

Alternatively to the embodiment ofFIG. 6, an isolation region177may be formed as illustratively shown inFIG. 7A.FIG. 7Ais cross-sectional view depicting an exemplary embodiment of memory array100having shallow trench isolation (“STI”) region177. STI region177effectively divides bitline region106. However, in this embodiment, separate bitline regions106are formed for each shared bitline contact171of bitline adjacent thyristor-based memory cells750. Thus, each bitline region106is formed after the formation of an associated STI region177. Bitline contact171may be a defined shape to facilitate contact lithography. For example, bitline contact171may be formed using a rectangularly shaped contact to effectively provide a rectangularly shaped plug. Contact formation uniformity may be facilitated. Accordingly, there may be one such bitline contact171for each pair of memory cells.

In order to share a metal line172for providing a bitline to adjacent memory cells, a bitline contact171may be formed partially over salicide regions160of each bitline region106of bitline-adjacent memory cells750. In this configuration, adjacent memory cells may share a bitline metal line172. Contact171may be formed of a metal, and STI region177may be conventionally formed. Notably, by creating an STI or other isolation region177, charge transport through the base of parasitic BJT127ofFIG. 1Bmay be eliminated. Moreover, parasitic BJT127ofFIG. 1Bmay be eliminated.

Alternatively to a local interconnect bitline contact171, a pair of bitline contacts174may be implemented as illustratively shown inFIG. 7B.FIG. 7Bis a cross-sectional view depicting an exemplary embodiment of memory array100with bitline contacts174on either side of an STI region177. Respective bitline contacts174are formed for individual coupling to salicide regions160of each bitline region106. Thus, each bitline region106separated by an STI region177may have respective salicide regions160to which respective contacts174may be coupled. An inter-layer dielectric173may be deposited, including between contacts174, in a conventional manner. Metal line172may be formed to be in contact with contacts174, in effect forming a bridge over STI region177. Though not shown to scale, it should be appreciated that a smaller STI region177may be used by having separate contacts174as opposed to one local interconnect bitline contact171for each pair of bitline-adjacent memory cells750as illustratively shown inFIG. 7A.

Though contacts171and174ofFIGS. 7A and 7Bhave been described in terms of bitline contacts, it should be understood that such contacts may be used as anode contacts, as respectively illustratively shown in the cross-sectional views ofFIGS. 7C and 7D, or as storage node contacts, as illustratively shown in the cross-sectional views ofFIGS. 7E and 7F.

FIG. 7Cis cross-sectional view depicting an exemplary embodiment of memory array100with separate anode regions101on either side of an STI region177. STI region177effectively divides an anode region101. However, in this embodiment, separate anode regions101are formed for each shared anode contact181of anode-adjacent thyristor-based memory cells850. Thus, each anode region101is formed after the formation of an associated STI region177.

In order to share a metal line182for providing a reference voltage to anode-adjacent memory cells, an anode contact181may be formed over salicide regions160of each anode region101of anode-adjacent memory cells850. In this configuration, adjacent memory cells may share an anode metal line182. Contact181may be formed of a metal, and STI region177may be conventionally formed. Notably, by creating an STI or other isolation region177, charge transport through the base of parasitic BJT125ofFIG. 1Amay be eliminated. Moreover, parasitic BJT125ofFIG. 1Amay be eliminated.

Alternatively to a local interconnect anode contact181, a pair of anode contacts184may be implemented as illustratively shown inFIG. 7D.FIG. 7Dis a cross-sectional view depicting an exemplary embodiment of memory array100with anode contacts184on either side of an STI region177. Respective anode contacts184are formed for individual coupling to salicide regions160of each anode region101. Thus, each anode region101separated by an STI region177may have respective salicide regions160to which respective contacts184may be coupled. An inter-layer dielectric173may be deposited, including between contacts184, in a conventional manner. Metal line182may be formed to be in contact with contacts184, in effect forming a bridge over STI region177. A smaller STI region177may be used by having separate contacts184as opposed to one local interconnect anode contact181for each pair of anode-adjacent memory cells850as illustratively shown inFIG. 7C.

FIG. 7Eis cross-sectional view depicting an exemplary embodiment of a thyristor-based memory cell950with separate cathodes104on either side of an STI region177. STI region177effectively divides a cathode104. However, in this embodiment, separate cathodes104are formed for each shared storage node contact191of a memory cell950for coupling an access transistor952to a thyristor-based storage element951. Thus, each cathode104is formed after the formation of an associated STI region177. Notably, cathode104of access transistor952may be considered a source/drain region, and cathode104of thyristor-based storage element951may be considered a cathode region.

Storage node contact191may be formed partially over salicide regions160of each cathode104. Contact191may be formed of a metal, and STI region177may be conventionally formed. Notably, by creating an STI or other isolation region177, charge transport through the base of parasitic BJT128ofFIG. 1Amay be eliminated. Moreover, parasitic BJT128ofFIG. 1Amay be eliminated.

Alternatively to a local interconnect storage node contact191, a pair of storage node contacts194may be implemented as illustratively shown inFIG. 7F.FIG. 7Fis a cross-sectional view depicting an exemplary embodiment of memory cell950with storage node contacts194on either side of an STI region177. Respective storage node contacts194are formed for individual coupling to salicide regions160of each cathode104. Thus, each cathode104separated by an STI region177may have respective salicide regions160to which respective contacts194may be coupled. An inter-layer dielectric173may be deposited, including between contacts194, in a conventional manner. A storage node line192may be coupled to storage node contacts194for electrical continuity therebetween. A smaller STI region177may be used by having separate contacts194as opposed to one local interconnect storage node contact191as illustratively shown inFIG. 7E.