Method for forming multi-level contacts

A method of forming a plurality of contact holes 70 in a semiconductor wafer uses a single step. The semiconductor wafer includes a dielectric layer 69 overlying a silicon substrate 51, a silicon nitride layer 67a, and a silicon oxynitride layer 63c. First, a photoresist 68 layer is developed on the dielectric layer. Prior to forming the dielectric layer, the silicon oxynitride layer is formed overlying a first conductive layer, and the silicon nitride layer is formed overlying a second conductive layer. Second, an etching step is performed to etch through the silicon oxynitride layer, the silicon nitride layer, a portion of the dielectric layer above the silicon oxynitride layer, and the silicon nitride layer to expose the silicon substrate 51, the first conductive layer 63a, and the second conductive layer 67c. The etching recipe includes a first chemistry and a second chemistry. The first chemistry includes C.sub.2 F.sub.6, C.sub.4 F.sub.8, CH.sub.3 F, and Ar. The second chemistry is chosen from a group including O.sub.2, CO.sub.2, CO and any combination thereof. Thus, a plurality of contact holes is formed above the silicon substrate, the first conductive layer and the second conductive layer.

BACKGROUND OF THE INVENTION 
1. Field of the Invention 
This invention relates to a method for forming multi-level contacts, and 
especially relates to a method for forming multi-level contacts in large 
scale integration semiconductor devices. 
2. Description of the Prior Art 
With the advent of Ultra Large Scale Integrated (ULSI) DRAM devices, the 
size of the memory cells becomes smaller and smaller such that the area 
available for a single memory cell becomes very small. The manufacture of 
a DRAM memory cell includes the fabrication of a transistor, a capacitor 
and contacts to periphery circuits. To shrink the area of the devices in 
the DRAM cell is thus the most important issue for the designer of the 
DRAM cell. The stacked capacitor is widely used in DRAM memory cells of 
small size, because the stacked capacitor occupies relatively small area. 
Additionally, as the step height of the stacked capacitor is large for the 
large-scale integration semiconductor device, multi-level contacts in the 
periphery circuit are widely used. Also, the self align contact technology 
must be used in fabricating ULSI devices. When there is no need to use the 
technology of self align contact, the spacer and the cap of the gate 
electrode can be formed of TEOS (Tetra Ethyl Ortho Silicate) oxide. As 
shown in FIG. 1, a plurality of multi-level contact holes is to be formed 
in the semiconductor device mentioned above. 
A silicon substrate 9 is provided for the semiconductor device mentioned 
above. A plate poly layer 10 is connected to a capacitor 11 of the 
semiconductor device, and a bit line 13 includes a first tungsten silicide 
layer 13a and a first poly silicon layer 13b. A word line 17 includes an 
oxide cap 17a, an oxide spacer 17b, a second tungsten silicide layer 17c, 
and a second poly silicon layer 17d. The bit line 13 and the word line 17 
are used to address a semiconductor device. The plurality of multi-level 
contact holes 18 is formed penetrating a BPSG layer 19, using a developed 
photoresist layer 20 as a mask. Because the integration of the 
semiconductor device mentioned above is not high, it is not necessary to 
utilize a self-aligned contact technology or an anti-reflection layer. 
Thus the multi-level contact holes can be formed in an etching step using 
a fluorine-containing gas as a etchant, such as CCI.sub.2 F.sub.2 or 
CF.sub.4. 
When the large scale integration semiconductor device is to be fabricated, 
an anti-reflection layer must be used to increase the cell density and 
improve the photo proximity effect. Typically, an inorganic 
anti-reflection layer composed of silicon nitride (Si.sub.3 N.sub.4) or 
silicon oxynitride (SiON) is used. In addition, the technology of self 
align contact is used to increase critical dimension (CD) control when 
fabricating the large scale integration semiconductor device. So the 
material used to form the spacer and the cap of the gate electrode is 
changed to silicon nitride (Si.sub.3 N.sub.4). 
The cross sectional view of the large scale integration semiconductor 
device is shown in FIG. 2. A silicon substrate 29 is provided for the 
large scale semiconductor device mentioned above. A plate poly layer 30 is 
connected to a capacitor 31 of the large scale integration semiconductor 
device, and a bit line 33 includes a first tungsten silicide layer 33a, a 
first poly silicon layer 33b, and a silicon oxynitride layer 33c. The 
silicon oxynitride layer 33c on the first tungsten silicide layer 33a is 
an anti-reflection layer. A word line 37 includes a silicon nitride layer 
37a, a silicon nitride spacer 37b, a second tungsten silicide layer 37c, 
and a second polysilicon layer 37d. The bit line 33 and the word line 37 
are used to address the large scale integration semiconductor device. 
Subsequently, to form multi-level contacts, a photoresist layer 38 is 
developed on a BPSG layer 39. 
When the traditional fluorine containing gas is used to form the 
multi-level contact hole, it tends to result in either an etch-stop 
or/polymer regrowth on both the silicon nitride layer 37a and the silicon 
oxynitride layer 33c. In addition, silicon loss in the plate poly layer 30 
and the silicon substrate 29 can be serious. As shown in FIG. 3, 
multi-level contact holes 40 are formed in the BPSG layer 39. But as 
mentioned above, when etching the silicon nitride layer 37a and the 
silicon oxynitride layer 33c, the etch-stop or the polymer regrowth 
problems can result. Thus the first tungsten silicide layer 33a and the 
second tungsten silicide layer 37c are not exposed after the etching step. 
Moreover, there is a tendency to over etch the plate poly layer 30 and the 
silicon substrate 29 when the traditional fluorine-containing gas is used 
to form the multi-level contact hole to expose the first tungsten silicide 
layer 33a and the second tungsten silicide layer 37c. The cross sectional 
view of the semiconductor device processed with the etching step mentioned 
above is shown in FIG. 3, in which the semiconductor device is defective 
because of an open circuit or short circuit in the semiconductor device. 
Because it is very difficult to use the traditional recipe to form 
multi-level contact holes of different depth, the yield of the 
semiconductor device of high integration is low. As the integration of 
semiconductor gets higher, the multi-level contact becomes more important, 
and the etching step becomes more critical. 
SUMMARY OF THE INVENTION 
To implement a large scale integration semiconductor device, a method 
forming a plurality of contact holes in a semiconductor wafer using 
self-aligned contact technology within an etching step is disclosed 
herein. The semiconductor wafer includes a dielectric layer overlying a 
silicon substrate, a silicon nitride layer, and a silicon oxynitride 
layer. The method includes the following steps. First, a photoresist layer 
is developed on the dielectric layer. Prior to forming the dielectric 
layer, the silicon oxynitride layer is formed overlying a first conductive 
layer, and the silicon nitride layer is formed overlying a second 
conductive layer. 
Second, an etching step is performed to etch through the silicon oxynitride 
layer, the silicon nitride layer, a portion of the dielectric layer above 
the silicon oxynitride layer, and the silicon nitride layer to expose the 
silicon substrate, the first conductive layer, and the second conductive 
layer. The etching recipe includes a first chemistry and a second 
chemistry. The first chemistry includes C.sub.2 F.sub.6, C.sub.4 F.sub.8, 
CH.sub.3 F, and Ar. The second chemistry is chosen from a group including 
O.sub.2, CO.sub.2, CO, and any combination thereof. Thus a plurality of 
contact holes is formed above the silicon substrate, the first conductive 
layer, and the second conductive layer. The flow rate of the second 
chemistry is about 1-10 percent of that of the first chemistry.

BRIEF DESCRIPTION OF THE DRAWINGS 
The above features of the present invention will be more clearly understood 
from consideration of the following descriptions in connection with 
accompanying drawings in which: 
FIG. 1 illustrates the cross sectional view of a semiconductor device 
without self align contact technology; 
FIG. 2 illustrates the cross sectional view a large scale integration 
semiconductor device with self-aligned contact technology; 
FIG. 3 illustrates the cross sectional view of a large scale integration 
semiconductor device using self-aligned contact technology with 
multi-level contact holes in the prior art; and 
FIG. 4 illustrates the cross sectional view of a large scale integration 
semiconductor device using self-aligned contact technology with 
multi-level contact holes in the present invention. 
DESCRIPTION OF THE PREFERRED EMBODIMENT 
Etch-stop or polymer regrowth can result on the silicon nitride layer 37a, 
and the silicon oxynitride layer 33c, when the traditional 
fluorine-containing gas is used to form the multi-level contact hole. 
Further more, there can be serious silicon loss in the plate poly layer 30 
and the silicon substrate 29. So, as the integration of a semiconductor 
device increases, the traditional recipe used to form the multi-level 
contact hole can not meet the needs of the etching process. Thus the 
present invention provides a recipe to form the multi-level contact hole 
of different depth, and the yield of the semiconductor device can be 
greatly improved. 
To penetrate the silicon nitride layer 37a and the silicon oxynitride layer 
33c (FIG. 3), and to prevent the over etching of the plate poly payer 30 
and the silicon substrate 29 when forming the multi-level contact holes 40 
in an etching step, the present invention provides a recipe. The recipe 
provided in the preferred embodiment of the present invention can produce 
a polymer on the surface when etching the poly-silicon. Also, the recipe 
can etch through the silicon nitride layer 37a and the silicon oxynitride 
layer 33c without producing the etch-stop or the polymer regrowth when 
simultaneously etching the plate poly layer 30 and the silicon substrate 
29. 
To implement a large scale integration semiconductor device, an 
anti-reflection layer a self-aligned contact is utilized, and a 
multi-level contact is formed in the semiconductor device to implement the 
interconnection. Referring to FIG. 4, a silicon substrate 51 is provided 
for the large integration scale semiconductor device mentioned above. A 
plate poly layer 60 is connected to a capacitor 61 of the large scale 
integration semiconductor device, and a bit line 63 includes a first 
conductive layer 63a, a first polysilicon layer 63b, and a silicon 
oxynitride layer 63c. The first conductive layer 63a in the preferred 
embodiment of the present invention is formed of tungsten silicide. The 
silicon oxynitride layer 63c on the first conductive layer 63a is an 
anti-reflection layer. 
A word line 67 includes a silicon nitride layer 67a, a nitride spacer 67b, 
a second conductive layer 67c, and a second polysilicon layer 67d. The 
second conductive layer 67c in the preferred embodiment of the present 
invention is formed of tungsten silicide. In addition, the first 
conduction layer 63a and the second conductive layer 67c can be chosen 
from the group consisting of: WSi, TiSi, CoSi. The bit line 63 and the 
word line 67 are used to address the large scale integration semiconductor 
device. Subsequently, to form multi-level contacts, a photoresist layer 68 
is developed on a dielectric layer 69. The dielectric layer 69 is formed 
of BPSG. When the recipe according to the preferred embodiment is used to 
form multi-level contact holes 70, there is neither the etch-step nor 
polymer regrowth problem on the silicon nitride layer 67a and the silicon 
oxynitride layer 63c. Instead, the etching step using the recipe in the 
preferred embodiment of the present invention can penetrate the silicon 
nitride layer 67a and the silicon oxynitride layer 63c to expose the first 
conductive layer 63a and the second conductive layer 67c. 
In addition, a polymer is produced when etching the silicon in the plate 
poly layer 60 and the silicon substrate 51. So there is no serious silicon 
overetching in the plate poly layer 60 and the silicon substrate 51. Thus, 
multi-level contact holes 70 of different depth are formed in the etching 
step. A cross sectional view of the resulting semiconductor wafer is shown 
in FIG. 4. To form the multi-level contact plug, the polymer in the 
multi-level contact holes 70 is removed in situ in another etching step, 
followed by filling polysilicon in the multi-level contact holes 70. 
Because the polymer in the multi-level contact holes 70 acts as a mask when 
etching the polysilicon in the plate poly layer 60 and the silicon 
substrate 51, the over etching is prevented. The recipe used in the 
preferred embodiment according to the present invention includes a first 
chemistry including C.sub.2 F.sub.6, C.sub.4 F.sub.8, CH.sub.3 F and Ar. 
In addition, the recipe used in the preferred embodiment of the present 
invention includes a second chemistry that is not used in the traditional 
recipe. The second chemistry includes CO.sub.2, CO, O.sub.2 or the 
combination thereof. The flow rate of C.sub.2 F.sub.6, C.sub.4 F.sub.8, 
CH.sub.3 F and Ar are about 0-10 sccm, 13-25 sccm, 10-30 sccm, and 60-200 
sccm respectively. 
Particularly, the flow rate of the second chemistry is about 1-10 percent 
of that of the first chemistry. The recipe in the present invention can 
prevent etch-stop on the silicon nitride layer or the silicon oxynitride 
layer while maintaining high selectivity to the underlying conductive 
layers, such as silicon substrate, doped polycrystalline silicon, and 
material silicide. The power used to process the recipe is about 1600-2400 
Watts in source power, and about 1000-1500 Watts in bias power. Thus the 
multi-level contacts can be formed in the large scale integration 
semiconductor device without etch-stop on the silicon nitride layer or the 
silicon oxynitride layer while maintaining high selectivity to silicon 
substrate, doped polycrystalline silicon, or material silicide. 
Although specific embodiments have been illustrated and described it will 
be obvious to those skilled in the art that various modification may be 
made without departing from the spirit which is intended to be limited 
solely by the appended claims.