Testing with high speed pulse generator

An integrated circuit, where a hard macro is resident within the integrated circuit. The hard macro receives a clock signal at a frequency that is below the operational frequency of the integrated circuit, and produces a clock signal having a frequency that is at least equal to the operational frequency of the integrated circuit. The hard macro has a first input that receives a first signal from the tester. A second input receives a second signal from the tester, offset by substantially ninety degrees from the phase of the first signal. A speed select input receives a signal, where the signal is selectively set at one of a logical high indicating a first multiplier to be applied in the hard macro, and a logical low indicating a second multiplier to be applied in the hard macro. A clock multiplication circuit receives the first signal, selectively receives the second signal, and receives the speed select signal, and produces the clock signal. The clock signal is a multiple of the tester frequency that is dependent at least in part upon the setting of the speed select signal and the tester frequency. An input receives the clock signal from the hard macro and provides the clock signal to the integrated circuit during testing.

FIELD

This invention relates to the field of integrated circuit fabrication. More particularly, this invention relates to testing of integrated circuits.

BACKGROUND

It is becoming more critical for high speed memory to be tested at actual application frequencies, or as close as the automated test equipment can facilitate. The challenge is that most automated test equipment in use, particularly the lower cost testers, cannot provide a high enough clock speed to test such memories. Such testers top out at about two hundred megahertz, which is not sufficient to properly run the needed tests. A higher speed solution is needed to perform the desired tests.

One solution is to purchase new testers that can support test frequencies well beyond the current speed limitations. However, the enormous capital expenditure that would be required for this solution is not practical for most manufacturers.

What is needed, therefore, is a system that overcomes problems such as those described above, at least in part.

SUMMARY

The above and other needs are met by an integrated circuit having an operational frequency, where a hard macro is resident on a monolithic substrate with the integrated circuit. The hard macro receives a reference clock signal from a tester that is external from the substrate at a tester frequency that is below the operational frequency of the integrated circuit, and produces a multiplied clock signal having a second frequency that is at least equal to the operational frequency of the integrated circuit. The hard macro has a first reference clock input that receives a first reference clock signal from the tester at the tester frequency and a first phase. A second reference clock input receives a second reference clock signal from the tester at the tester frequency and a second phase. The second phase is offset by substantially ninety degrees from the first phase of the first reference clock signal.

A speed select input receives a speed select signal, where the speed select signal is selectively set at one of two states, a logical high indicating a first multiplier to be applied in the hard macro, and a logical low indicating a second multiplier to be applied in the hard macro. A clock multiplication circuit receives the first reference clock signal, selectively receives the second reference clock signal, and receives the speed select signal, and produces the multiplied clock signal at a multiplied clock output. The multiplied clock signal has the second frequency, which is a multiple of the tester frequency that is dependent at least in part upon the setting of the speed select signal and the tester frequency. An input receives the multiplied clock signal from the hard macro and provides the multiplied clock signal to portions of the integrated circuit during testing of the integrated circuit.

In this manner, the logic to generate the high-speed clock is implemented on the actual device to be tested. One feature of this invention is its ability to provide a multiplied clock frequency for built in self testing, which multiplied frequency is under the control of the tester, through the provided reference signals. The more common approach of using an on-chip PLL to provide the clock multiplication cannot easily be controlled with respect to shutting down the on-chip multiplied clock, which is a critical component of post-manufacturing device analysis and failure analysis.

According to another aspect of the invention there is provided a method of testing an integrated circuit at an operational frequency of the integrated circuit. The integrated circuit is connected to a tester, and the tester is set to provide a clock frequency to the integrated circuit, where the clock frequency is less than the operational frequency of the integrated circuit. The clock frequency is received with a hard macro within the integrated circuit, and increased with the hard macro to a multiplied frequency that is substantially at least as high as the operational frequency of the integrated circuit. The multiplied frequency is provided to the integrated circuit, which is tested at the multiplied frequency.

In one embodiment, a speed select signal is provided to the hard macro, and the clock frequency is increased to the multiplied frequency, which is dependent at least in part on the speed select signal and the clock frequency. The step of receiving the clock frequency preferable includes receiving a first clock signal and a second clock signal, each having the clock frequency, where a phase of the first clock signal is offset by substantially ninety degrees from a phase of the second clock signal.

DETAILED DESCRIPTION

With reference now toFIG. 1, there is depicted a clock speed increasing circuit10according to a preferred embodiment of the present invention. The circuit10is created as a built-in self test hard macro within the integrated circuit to be tested, such as by being created on the same monolithic substrate and at the same time as the integrated circuit. The circuit10receives one or more clock signals from the offboard tester, as described in more detail below, and increases the frequency of the clock signals to create a new, higher speed clock signal that is used as the testing frequency for the integrated circuit, such as a high speed memory circuit.

This allows for clock doubling on-chip relative to a single reference clock provided by the tester, or clock quadrupling on-chip relative to two reference clocks provided by the tester. The circuit10is intended to be implemented as a hard macro within an integrated circuit technology library in order to ensure that its performance is consistent from one device to another, independent of layout and routing differences between unique designs.

The circuit10preferably consists of a digital logic block consisting of four inputs, first reference clock12, reset14, speed select16, and second reference clock18, and one output doubled/quadrupled clock26, as depicted inFIG. 1. These inputs and output are described in more detail below.

The reset signal14is preferably used to initialize the clock multiplier circuit10at the beginning of the test block to be run on the tester. A logical zero is preferably used to force the reset condition, followed by a logical one for the duration of the test block. The speed select signal16is preferably used to set the clock multiplier to a factor of either two or four, where a logical zero preferably denotes a multiplier of two, and a logical one preferably denotes a multiplier of four.

When a multiplication factor of two is desired, preferably the only reference clock input that is used is the first reference clock12. This is preferably a two hundred megahertz maximum signal from the tester, or whatever else the maximum frequency is of the tester being used. The signal12is preferably supplied with a fifty percent duty cycle, such that both the rising and falling edges of the reference clock12generate an on-chip clock pulse pair, or a multiplication factor of two relative to the tester's operational frequency, as depicted in the timing diagram ofFIG. 4.

When a multiplication factor of four is desired, preferably both of the reference clock inputs, the first reference clock12and the second reference clock18, are used. These two reference clocks are preferably supplied such that the second clock18is substantially ninety degrees out of phase relative to the first reference clock12. Both clocks12and18preferably have a fifty percent duty cycle, and the rising and falling edges of both generate an on-chip clock sequence of four pulses, or a multiplication factor of four relative to the tester's operational frequency, again as depicted in the timing diagram ofFIG. 4.

The pulse generators20aand20bdepicted inFIG. 1are circuits that preferably generate a narrow pulse referenced to both the rising and falling edge of the reference clock signals12and18provided to the circuit10. The pulse generators20could be designed in a variety of different embodiments as determined by a circuit designer.FIGS. 2 and 3represent possible implementations of the pulse generator circuit20.

FIG. 2depicts one embodiment of the pulse generator circuit20that takes a single input clock signal, such as either one of the first reference clock12or the second reference clock18, and generates two clock out pulses40for each input clock signal. The upper flip-flop is preferably a rising-edge-triggered circuit, and the lower flip-flow is preferably a falling-edge-triggered circuit. The two flip-flop outputs are logically OR'd at gate24to create the clock out signal40with a multiplication factor of two. OR'ing two such circuits20together as shown inFIG. 1creates the multiplication factor of four. It is appreciated that other circuits could accomplish this same multiplication of the input clock signal.

FIG. 3depicts one embodiment of the delay circuits38depicted inFIG. 2. The speed select signal16preferably selects either a 625 picosecond or 1,250 picosecond delay as appropriate for a multiplication factor of either two or four, respectively. It is appreciated that other circuits could create the desired delays as described herein.

FIG. 4depicts is a timing diagram of the operation of the circuit in a mode with a multiplication factor of four. A mode of a multiplication factor of two preferably operates in the same fashion, except that the speed select signal16is low, disabling the second reference clock18and causing the delay inFIG. 3to generate a 1,250 picosecond pulse instead of a 625 picosecond pulse.

The factor of two or factor of four clock signal26is preferably routed off-chip in one test mode, such that the operation of the circuit10can be calibrated relative to the tester before testing the integrated circuit to be tested. The high-speed clock26generated on the chip can thus be optimized relative to the reference clock or clocks from the tester. The tester-provided signals12and18will typically not have a perfect fifty percent duty cycle as programmed from within the test program for the device under test. Thus, a calibration routine allows the rising and falling edges of the reference clocks12and18from the tester to be set to optimize the frequency of the on-chip multiplied clock26with respect to any jitter created by a non-fifty percent duty cycle reference.