Setting information storage circuit and integrated circuit chip including the same

A setting information storage circuit includes first decoders configured to generate first input enable signals, respectively, in response to selection codes and a first set signal, first register sets configured to correspond to the first decoders, respectively, and to receive setting data when first input enable signals generated from the first decoders corresponding to the first register sets, respectively, are enabled, and store the received setting data, a second decoders configured to generate a second input enable signals, respectively, in response to the selection codes and a second set signal, and a second register sets configured to correspond to the second decoders, respectively, and to receive the setting data when second input enable signals generated from the second decoders corresponding to the second register sets, respectively, are enabled, and store the received setting data.

BACKGROUND

Exemplary embodiments of the present invention relate to setting information storage circuits for storing setting information for various settings within an integrated circuit chip.

2. Description of the Related Art

An integrated circuit chip requires various settings for a normal operation after the chip is fabricated. For example, only when settings for voltage levels used in an integrated circuit chip and settings for delay values of a delay circuit included in the integrated circuit chip are correctly performed, the integrated circuit chip may operate in an optimal environment. Furthermore, a variety of environments necessary for a test are set, and the test for an integrated circuit chip is performed. As described above, most of integrated circuit chips include a variety of setting circuits for setting operation mode, the voltage levels, and delay values.

FIG. 1is a diagram illustrating a setting circuit included within a conventional integrated circuit chip.

Referring toFIG. 1, the integrated circuit chip includes a selection code transfer bus101, a setting data transfer bus102, a set signal transfer line103, a reset signal transfer line104, a plurality of decoders110_0to110_N, a plurality of register sets120_0to120_N, and a plurality of internal circuits130_0to130_N.

The selection code transfer bus101transfers external selection codes SEL<0:A> received from a source other than the integrated circuit chip. The selection codes SEL<0:A> designate that external setting data DATA<0:B> received from a source other than the integrated circuit chip to be stored in one of the plurality of register sets120_0to120_N. The setting data transfer bus102transfers the external setting data DATA<0:B>. The setting data DATA<0:B> is stored in a register set that is selected in response to the selection codes SEL<0:A>. The set signal transfer line103transfers an external set signal SET received from a source other than the integrated circuit chip. Furthermore, the reset signal transfer line104transfers an external reset signal RST received from a source other than the integrated circuit chip. The set signal SET includes timing information that designates a time at which setting data starts being inputted to a register set selected in response to the selection codes SEL<0:A>. The reset signal RST includes timing information that designates a time at which the setting data DATA<0:B> starts being inputted to a register set selected in response to the selection codes SEL<0:A>.

The decoders110_0to110_N generate input enable signals EN_0to EN_N in response to the selection codes SEL<0:A>, the set signal SET, and the reset signal RST. If the selection codes SEL<0:A> has a corresponding value to one of the decoders110_0to110_N, one of the decoders110_0to110N enables the respective input enable signals EN_0to EN_N in response to the enabling of the set signal SET and disable the respective input enable signals EN_0to EN_N in response to the enabling of the reset signal RST. For example, assuming that the number of decoders110_0to110_N is 8 (that is, N=7) and the selection codes SEL<0:A> have 3 bits (that is, A=2), if the selection codes SEL<0:2> have a value of ‘000’, the decoder110_0enables the input enable signal EN_0in response to the enabling of the set signal SET and disables the input enable signal EN_0in response to the enabling of the reset signal RST. Furthermore, if the selection codes SEL<0:2> have a value of ‘010’, the decoder110_2enables the input enable signal EN_2in response to the enabling of the set signal SET and disables the input enable signal EN_2in response to the enabling of the reset signal RST.

The register sets120_0to120_N receive and store the setting data DATA<0:B> loaded onto the setting data transfer bus102while the respective input enable signals EN_0to EN_N are enabled. For example, while the input enable signal EN_1is enabled, the setting data DATA<0:B>, which is loaded onto the setting data transfer bus102, is stored in the register set120_1. While the input enable signal EN_3is enabled, the setting data DATA<0:B>, which is loaded onto the setting data transfer bus102, is stored in the register set120_3.

The internal circuits130_0to130_N perform setting necessary for respective operations by using setting data stored in respective register sets. For example, if the internal circuit130_0is a circuit for setting the operation mode of the integrated circuit chip, the internal circuit130_0may set the operation mode of the integrated circuit chip in mode A or mode B by using setting data stored in the register set120_0. Furthermore, if the internal circuit130_1is a circuit for generating an internal voltage used in the integrated circuit chip, the internal circuit130_1may set the level of the internal voltage by using setting data stored in the register set120_1. Furthermore, if the internal circuit130_2is a delay circuit for delaying a specific signal, the internal circuit130_2may set a delay value by using setting data stored in the register set120_2.

The setting method used in the above-described integrated circuit chip is performed in such a manner that a setting item is selected in response to the selection codes SEL<0:A>, and setting information DATA<0:B> is inputted to the selected setting item. Accordingly, the number of items that may be set varies depending on the number of bits of the selection codes SEL<0:A>. In order to increase the number of items that may be set in this setting method, the number of bits of the selection codes SEL<0:A> has to be increased. If the number of bits of the selection codes SEL<0:A> is increased, however, there are concerns in that an area of the selection code transfer bus101must be increased and the design of the decoders110_0to110_N must be changed. In particular, in the case of an integrated circuit chip in which the number of bits of the selection codes SEL<0:A> is determined in accordance with standards, such as JEDEC and IEEE, there is a concern in that an increase in the number of bits of the selection codes SEL<0:A> may violate the standards. Accordingly, there is a need for technology that can increase the number of items that may be set without increasing the number of bits of the selection codes SEL<0:A> and changing the design of the decoder110_0to110_N.

SUMMARY

Exemplary embodiments of the present invention are directed to providing technology that may increase the number of settings that may be set without increasing the number of bits of selection codes or changing the construction of decoders.

In accordance with an embodiment of the present invention, a setting information storage circuit includes a plurality of first decoders configured to generate a plurality of first input enable signals, respectively, in response to selection codes and a first set signal, a plurality of first register sets configured to correspond to the plurality of first decoders, respectively, and to receive setting data when the first input enable signals generated from the first decoders corresponding to the first register sets, respectively, are enabled, and to store the received setting data, a plurality of second decoders configured to generate a plurality of second input enable signals, respectively, in response to the selection codes and a second set signal, and a plurality of second register sets configured to correspond to the plurality of second decoders, respectively, and to receive the setting data when the second input enable signals generated from the second decoders corresponding to the plurality of second register sets, respectively, are enabled, and to store the received setting data.

In accordance with another embodiment of the present invention, an integrated circuit chip includes a selection code transfer bus configured to transfer selection codes, a setting data transfer bus configured to transfer setting data, a first line configured to transfer a first set signal, a second line configured to transfer a second set signal, a plurality of first decoders configured to generate a plurality of first input enable signals, respectively, in response to the selection codes and a first set signal, a plurality of first register sets configured to correspond to the plurality of first decoders, respectively, and to receive the setting data when the first input enable signals generated from the first decoders corresponding to the first register sets, respectively, are enabled, and to store the received setting data, a plurality of second decoders configured to generate a plurality of second input enable signals, respectively, in response to the selection codes and the second set signal, and a plurality of second register sets configured to correspond to the plurality of second decoders, respectively, and to receive the setting data when the second input enable signals generated from the plurality of second decoders corresponding to the second register sets, respectively, are enabled, and to store the received setting data.

DETAILED DESCRIPTION

FIG. 2illustrates a block diagram of an integrated circuit chip including a setting information storage circuit in accordance with one embodiment of the present invention.

Referring toFIG. 2, the integrated circuit includes a reception circuit200, a selection code transfer bus201, a setting data transfer bus202, a first set signal transfer line203, a second set signal transfer line204, a reset signal transfer line205, a plurality of first decoders210_0to210_N, a plurality of second decoders220_0to220_N, a plurality of first register sets230_0to230_N, a plurality of second register sets240_0to240_N, a plurality of first internal circuits250_0to250_N, and a plurality of second internal circuits260_0to260_N.

The reception circuit200receives selection codes SEL<0:A>, setting data DATA<0:B>, a first set signal SET1, a second set signal SET2, and a reset signal RST, all of which are externally received from a source other than the integrated circuit chip.

The selection code transfer bus201transfers the external selection codes SEL<0:A> received from a source other than the integrated circuit chip. The selection codes SEL<0:A> designate that the external setting data DATA<0:B> received from a source other than the integrated circuit chip has to be stored in which one of the register sets230_0to230_N and240_0to240_N. The selection codes SEL<0:A> are shared by all the decoders210_0to210_N and220_0to220_N within the integrated circuit, and thus, the selection code transfer bus201is connected to all the decoders210_0to210_N and220_0to220_N.

The setting data transfer bus202transfers the external setting data DATA<0:B> received from a source other than the integrated circuit chip. The setting data DATA<0:B> is stored in a register set selected in response to the selection codes SEL<0:A> and the set signals SET1and SET2. All the register sets230_0to230_N and240_0to240_N within the integrated circuit chip receive the setting data DATA<0:B> through the setting data transfer bus202and store the received setting data DATA<0:B>, and thus, the setting data transfer bus202is connected to all the register sets230_0to230_N and240_0to240_N.

The first set signal transfer line203transfers the first set signal SET1, which is received from a source other than the integrated circuit chip, as a set signal used in the first decoders210_0to210_N. In an exemplary embodiment, the first set signal SET1is used in the first decoders210_0to210_N, but is not used in the second decoders220_0to220_N. Thus, the first set signal transfer line203is connected to the first decoders210_0to210_N only. The second set signal transfer line204transfers the second set signal SET2, received from a source other than the integrated circuit chip, as a set signal used in the second decoders220_0to220_N. The second set signal transfer line204is connected to the second decoders2200to220_N.

The reset signal transfer line205transfers the reset signal RST, received from a source other than the integrated circuit chip, to the first decoders210_0to210_N and the second decoders220_0to220_N. The reset signal transfer line205is connected to all the decoders210_0to210_N and220_0to220_N within the integrated circuit chip.

The plurality of first decoders210_0to210_N generate first input enable signals EN1_0to EN1_N, respectively, in response to the selection codes SEL<0:A>, the first set signal SET1, and the reset signal RST. If the selection codes SEL<0:A> has a corresponding value, the first decoders210_0to210_N enable the first input enable signals EN1_0to EN1_N, respectively, in response to the enabling of the first set signal SET1and disable the first input enable signals EN1_0to EN1_N, respectively, in response to the enabling of the reset signal RST. For example, assuming that the number of first decoders210_0to210_N is 8 (that is, N=7) and the selection codes SEL<0:A> have 3 bits (that is, A=2), if the selection codes SEL<0:2> have a value of ‘000’, the decoder210_0enables the first input enable signal EN1_0in response to the enabling of the first set signal SET1and disables the first input enable signal EN1_0in response to the enabling of the reset signal RST. Furthermore, if the selection codes SEL<0:2> have a value of ‘010’, the first decoder210_2enables the first input enable signal EN1_2in response to the enabling of the first set signal SET1and disables the first input enable signal EN1_2in response to the enabling of the reset signal RST.

The plurality of first register sets230_0to230_N receive the setting data DATA<0:B> loaded onto the setting data transfer bus202while the first input enable signals EN1_0to EN1_N corresponding to the first register sets230_0to230_N, respectively, are enabled and stores the received setting data DATA<0:B>. For example, while the first input enable signal EN1_1is enabled, the setting data DATA<0:B>, which is loaded onto the setting data transfer bus202, is stored in the first register set230_1. While the first input enable signal EN1_3is enabled, the setting data DATA<0:B>, which is loaded onto the setting data transfer bus202, is stored in the first register set230_3.

The plurality of second decoders220_0˜220_N generate second input enable signals EN2_0˜EN2_N, respectively, in response to the selection codes SEL<0:A>, the second set signal SET2, and the reset signal RST. If the selection codes SEL<0:A> have a corresponding value, the second decoders220_0to220_N enable the second input enable signals EN2_0to EN2_N in response to the enabling of the second set signal SET2and disable the second input enable signals EN2_0to EN2_N in response to the enabling of the reset signal RST. For example, assuming that the number of second decoders220_0to220_N is 8 (that is, N=7) and the selection codes SEL<0:A> have 3 bits (that is, A=2), if the selection codes SEL<0:2> have a value of ‘000’, the decoder210_0enables the second input enable signal EN2_0in response to the enabling of the second set signal SET2and disables the second input enable signal EN2_0in response to the enabling of the reset signal RST. Furthermore, if the selection codes SEL<0:2> have a value of ‘010’, the second decoder220_2enables the second input enable signal EN2_2in response to the enabling of the second set signal SET2and disables the second input enable signal EN2_2in response to the enabling of the reset signal RST.

The plurality of second register sets240_0to240_N receives the setting data DATA<0:B> loaded onto the setting data transfer bus202while the second input enable signals EN2_0to EN2_N corresponding to the second register sets240_0to240_N, respectively, are enabled. For example, while the second input enable signal EN2_1is enabled, the setting data DATA<0:B>, which is loaded onto the setting data transfer bus202, is stored in the second register set240_1. While the second input enable signal EN2_3is enabled, the setting data DATA<0:B>, which is loaded onto the setting data transfer bus202, is stored in the second register set240_3.

The first internal circuits250_0to250_N and the second internal circuits260_0to260_N perform settings necessary for respective operations using setting data stored in the respective register sets230_0to230_N and240_0to240_N. For example, if the internal circuit250_0is a circuit for setting the operation mode of the integrated circuit chip, the internal circuit250_0may set the operation mode of the integrated circuit chip in mode A or mode B using setting data stored in the first register set230_0. Furthermore, if the internal circuit260_1is a circuit for generating an internal voltage used in the integrated circuit chip, the internal circuit260_1may set the level of the internal voltage using setting data stored in the second register set240_1. Furthermore, if the internal circuit250_2is a delay circuit for delaying a specific signal, the internal circuit250_2may set a delay value by using setting data stored in the register set230_2.

In accordance with the present invention, the number of items that may be set in the integrated circuit chip, that is, the number of register sets230_0to230_N and240_0to240_N, may be increased by increasing the number of set signals SET1and SET2without increasing the number of bits of the selection codes SEL<0:A>. The first set signal SET1is transferred to the first decoders210_0to210_N, and the second set signal SET2is transferred to the second decoders220_0to220_N. As a result, an area of the first and the second set signal transfer lines203and204that are necessary to transfer the first and the second set signals SET1and SET2because of the increased number of set signals SET1and SET2may not be increased. Furthermore, since the number of bits of the selection codes SEL<0:A> remains intact as in the prior art, a change of the design of the decoders210_0to210_N and220_0to220_N, and an increase in the area of each decoder due to an increase in the number of bits of a signal to be decoded may be prevented.

FIG. 3illustrates a detailed circuit diagram in accordance with an embodiment of the first decoder210_1ofFIG. 2.FIG. 3illustrates the first decoder210_1when the number of bits of the selection codes SEL<0:N> is 6 bits (hereinafter referred to as SEL<0:5>) and a value of the selection codes SEL<0:5> corresponding to the first decoder210_1is ‘000001’.

Referring toFIG. 3, the first decoder210_1includes an enable controller310and an SR latch320.

The enable controller310enables an enable control signal CONTROL to ‘0’ when the selection codes SEL<0:5> has a value of ‘000001’, and the first set signal SET1is enabled to ‘1’. The enable controller310may include an inverter311, NOR gates312and313, and a NAND gate314as shown inFIG. 3.

The SR latch320enables the first input enable signal EN1_1to ‘1’ when the enable control signal CONTROL is enabled to ‘0’ and disables the first input enable signal EN1_1to ‘0’ when the reset signal RST is enabled to ‘1’ (that is, the output signal of an inverter321becomes ‘0’).

Each of the first decoders other than the first decoder210_1, which are first decoders210_0and210_2to210_N, may have a similar construction as the first decoder210_1shown inFIG. 3. In the case of the first decoders210_0and210_2to210_N, the number and positions of inverters in front of the NOR gates312and313may have to be changed depending on a corresponding value of the selection codes SEL<0:5>. Furthermore, the second decoders220_0to220_N may have the same design as the first decoders210_0to210_N, except that the second set signal SET2is received instead of the first set signal SET1.

FIG. 4illustrates a detailed circuit diagram in accordance with an embodiment of the first register set230_1ofFIG. 2.

Referring toFIG. 4, the first register set230_1includes pass gates410_0to410_B and latches420_0to420_B. Each of the latches420_0to420_B has the same number of bits (B+1) of the setting data DATA<0:B>.

The pass gates410_0to410_B are turned on when the first input enable signal EN1_1is enabled to ‘1’. When the pass gates410_0to410_B are turned on, the latches420_0to420_B receive the setting data DATA<0:B>, which is loaded onto the setting data transfer bus202, and receive the received setting data DATA<0:B>.

Each of the first register sets230_0and230_2to230_N and the second register sets240_0to240_N may have the same construction as the first register set230_1ofFIG. 4, except that each of the input enable signals EN1_0, EN1_2to EN1_N, and EN2_0to EN2_N is received.

FIG. 5illustrates a block diagram of an integrated circuit chip including a setting information storage circuit in accordance with another embodiment of the present invention.

The embodiment ofFIG. 5further includes an encoding circuit510in the embodiment ofFIG. 4. Codes and signals for setting the integrated circuit chip may be directly received from a source other than the integrated circuit chip as in the embodiment ofFIG. 4, but may be internally generated by encoding signals INPUTS externally received through a reception circuit200. The encoding circuit510generates codes and signals SEL<0:A>, DATA<0:B>, SET1, SET2, and RST for setting the integrated circuit chip by using the signals INPUTS received from the outside of the integrated circuit chip. That is, the encoding circuit510may generate the codes and signals SEL<0:A>, DATA<0:B>, SET1, SET2, and RST by changing a format of the external signals INPUTS. For example, in a memory device, such as DRAM, signals for setting the memory device may be received through a command channel and an address channel, and the codes and signals SEL<0:A>, DATA<0:B>, SET1, SET2, and RST for setting within the memory device are generated by using the received signals.

In accordance with yet another embodiment (not shown), an e-fuse array circuit and nonvolatile memory, such as flash memory, are included in an integrated circuit chip, and the codes and signals SEL<0:A>, DATA<0:B>, SET1, SET2, and RST for setting the integrated circuit chip may be generated by using information stored in the nonvolatile memory.

That is, the codes and signals SEL<0:A>, DATA<0:B>, SET1, SET2, and RST for setting the integrated circuit chip may be directly received from a source other than the integrated circuit chip (for example,FIG. 4), may be internally generated within the integrated circuit chip by using external signals (for example,FIG. 5), or may be internally generated within the integrated circuit by using information stored in the integrated circuit chip.

In accordance with the present invention, the number of items that can be set may be increased by increasing the number of set signals. Accordingly, the number of bits of selection codes and the construction of a decoder may not have to be changed, because the concerns raised by an increase in the area of a circuit and a change of the design may be alleviated.