Integrated circuit wafer dicing method

An integrated circuit wafer dicing method is provided. The method includes forming a plurality of integrated circuits and a plurality of test-keys on a wafer substrate, wherein the plurality of test-keys are disposed between the adjacent integrated circuits; forming a patterned protective film on the wafer to cover the plurality of integrated circuits and expose the plurality of test-keys; etching the plurality of test-keys by using the patterned protective film as a mask; and dicing an area between the plurality of integrated circuits to form a plurality of discrete integrated circuit dies.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention generally relates to an integrated circuit wafer dicing method, wherein a plurality of integrated circuit dies are formed from an integrated circuit wafer by the integrated circuit wafer dicing method.

2. Description of the Prior Art

A wafer is a substrate for manufacturing integrated circuits. Using integrated circuit fabrication technology, through a series of complicated chemical, physical, and optical processes, a fabricated integrated circuit wafer can include thousands or hundreds of integrated circuit dies. After being tested, cut, and packaged, these dies can be formed into various integrated circuit products having different functions.

FIG. 1shows a conventional integrated circuit wafer900and an enlarge view of the area80;FIG. 2shows a cross-sectional view of the area80ofFIG. 1indicated by PP. As shown inFIGS. 1 and 2, the conventional integrated circuit wafer900includes a wafer substrate100, a plurality of integrated circuits300, and a plurality of test-keys400. In a conventional wafer dicing process, an external force K is applied by a cutter to the integrated circuit wafer900along a path between two adjacent integrated circuits300. Because the cutter is directly applied onto the integrated circuit wafer900, cracks and damages of the integrated circuit wafer900will be produced due to the dicing stress. On the other hand, the test-keys400are distributed between the integrated circuits300, i.e. on the dicing path. Therefore, the yield rate will be decreased due to metal ashes generated from the cutting of test-keys during the dicing process. Therefore, it is desired to improve the conventional dicing method.

SUMMARY

It is an object of the present invention to provide an integrated circuit wafer which can be separated into multiple integrated circuit dies with improved yield rate.

The method includes forming a plurality of integrated circuits and a plurality of test-keys on a wafer substrate, wherein the test-keys are respectively disposed between the adjacent integrated circuits; forming a patterned protective layer on the integrated circuits, wherein the patterned protective layer covers the integrated circuits and exposes the test-keys; etching to remove the test-keys by using the patterned protective layer as a mask; and dicing an area between the adjacent integrated circuits to form a plurality of discrete integrated circuit dies. The plurality of test-keys are used for wafer acceptance test. The plurality of test-keys include a transistor, a capacitor, a resistor, an n-type semiconductor, a p-type semiconductor, a p-n-type semiconductor, a metal wire component, or a combination thereof.

The patterned protective layer is a patterned photoresist layer. The step of forming the patterned protective layer includes: covering the wafer substrate with a photoresist layer; exposing the photoresist layer by using a photomask; and developing the exposed photoresist layer to form the patterned protective layer. The step of etching can be dry etching or wet etching. The etching step further includes forming a plurality of grooves at the locations of the test-keys, wherein the dicing step further includes dicing along the grooves. The integrated circuits are disposed on the wafer substrate in matrix.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

As shown inFIG. 3, the integrated circuit wafer dicing method of the present invention includes the following steps.

Step1010, the step of forming a plurality of integrated circuits and a plurality of test-keys on a wafer substrate is performed, wherein the test-keys are respectively disposed between the adjacent integrated circuits. More particularly, as shown inFIGS. 1 and 2which is a cross sectional view of area80ofFIG. 1indicated by PP, the integrated circuits300and the test-keys400are formed on the wafer substrate100by semiconductor processing steps such as deposition, photolithography, etching, thermal processes, etc. The locations where the integrated circuits300and the test-keys400are formed can be controlled by the patterns of a mask. The integrated circuits300are disposed on the wafer substrate100in matrix. More particularly, as shown inFIG. 1, a unit square represents one integrated circuit300on the wafer substrate100, wherein the integrated circuits300are aligned and arranged in matrix for manufacturing and dicing. However, the shape and the arrangement of the integrated circuits300are not limited to the above embodiment. For example, the integrated circuits300can have rectangular or any suitable geometric shape and arranged in any manner as appropriate.

The test-keys400are respectively formed between adjacent integrated circuits300. More particularly, the test-keys400are disposed on a dicing path, wherein the dicing path is defined as a path for dicing the wafer substrate100to form a plurality of discrete dies of integrated circuits300. The plurality of test-keys400are used for wafer acceptance test. More particularly, the acceptance of the wafer substrate100, i.e. the quality of the wafer substrate100, can be obtained by carrying out electrical tests onto the plurality of test-keys400distributed on the wafer substrate100before dicing the wafer substrate100. The plurality of test-keys400may include transistors, capacitors, resistors, n-type semiconductors, p-type semiconductors, p-n-type semiconductors, metal wire components, etc. Moreover, the test-keys400can include a combination of devices described above.

Step1030, the step of forming a patterned protective layer on the integrated circuits is performed, wherein the patterned protective layer covers the integrated circuits and exposes the test-keys. More particularly, the patterned protective layer is a patterned photoresist layer. The step of forming the patterned protective layer includes: covering the wafer substrate with a photoresist layer; exposing the photoresist layer by using a photomask; and developing the exposed photoresist layer to form the patterned protective layer. More particularly, the step of forming the patterned protective layer includes: covering the wafer substrate100with the photoresist layer500as shown inFIG. 4A; exposing the photoresist layer500by using the photomask666as shown inFIG. 4B; and developing the exposed photoresist layer500to form a developed photoresist layer500as shown inFIG. 5, wherein the developed photoresist layer500is the patterned protective layer. The photoresist layer500shown inFIG. 4Ais preferably a blanket layer covering the entire wafer substrate100including the integrated circuits300and the test-keys400by spin coating. The patterned protective layer shown inFIG. 5covers the integrated circuits300and exposes the test-keys400.

Step1050, the step of etching to remove the test-keys by using the patterned protective layer as a mask is performed. More particularly, the test-keys400shown inFIG. 5is etched through by a dry plasma etching process or a wet chemical etching process to form an integrated circuit wafer900shown inFIG. 6A.

Step1070, the step of dicing an area between the adjacent integrated circuits to form a plurality of integrated circuit dies is performed. More particularly, as shown inFIG. 6A, an external force F is applied to an area between the two adjacent integrated circuits300to separate the wafer substrate100into a plurality of discrete integrated circuit dies. The external force F can be applied by a cutting tool. Since the test-keys (shown inFIG. 5) are removed in step1050, the present invention can solve the problem of yield rate decreasing caused by metal ashes, wherein the metal ashes are produced from cutting and damaging the test-key during dicing in the prior art.

In another embodiment, step1050further includes forming a plurality of grooves at the locations of the test-keys, wherein the dicing step further comprising dicing along the grooves. More particularly, by controlling the conditions of etching process such as the time of etching or the concentration of etching solutions, the grooves600shown inFIG. 6Bcan further be formed by etching during the removal of the test-keys400. Since the thickness of the wafer substrate100is thinner at the location of the grooves600, step1070can further include dicing along the grooves for more swimmingly.

As shown inFIG. 7, taking a different point of view, the integrated circuit wafer dicing method of the present invention includes the following steps.

Step2010, the step of providing a wafer substrate containing a plurality of integrated circuits is performed, wherein the adjacent integrated circuits are separated by a dicing path, wherein a metal layer is disposed at the dicing path. The metal layer is preferably but not limited to a test-key.

Step2030, the step of forming a patterned protective layer on the integrated circuits is performed, wherein the patterned protective layer covers the integrated circuits and exposes the dicing path. In the preferred embodiment, the patterned protective layer is formed by using a photoresist layer. The patterned protective layer exposes the test-keys.

Step2050, the step of etching to remove the metal layer at the dicing path by using the patterned protective layer as a mask is performed. In the preferred embodiment, the test-keys are etched to be removed.

Step2070, the step of dicing the wafer substrate along the dicing path to form a plurality of discrete integrated circuit dies is performed.

In the preferred embodiment, the method further includes step2060, the step of removing the patterned protective layer, after step2050. More particularly, the patterned protective layer is removed by etching before step2070.