Circuit arrangement for the timed control of semiconductor switches

In a circuit arrangement for the timed control of semiconductor switches (1-4) to each of which a freerunning diode (D1-D4) is connected in parallel and which are arranged in branches of a bridge, an ohmic-inductive load (5) of low loss power which lies in the diagonals of the bridge is to be acted on by a controlled average current value. For this purpose two semiconductor switches (for instance 1, 4) lying diagonally opposite each other in the bridge are closed in a current-application phase while in the following freerunning phase a freerunning current flows through the load. For the reduction of the loss power, at the start of the freerunning phase only one (1) of the two diagonally opposite semiconductors (1,4) is opened and a semiconductor switch (3) which lies in the bridge alongside the conductive semiconductor switch (4) is then closed. Before the start of a current-application phase which follows this, the semiconductor switch (3) which lies in the bridge alongside the closed semiconductor switch (4) is opened before the opened semiconductor switch ( 1) of the two diagonally opposite semiconductor switches (1,4) is closed again.

FIELD AND BACKGROUND OF THE INVENTION 
The present invention relates to a circuit arrangement for the timed 
control of semiconductor switches. 
In particular, the invention relates to a circuit arrangement for the timed 
control of semiconductor switches, in parallel with each of which there is 
a freerunning diode, and which are arranged in branches of a bridge in the 
diagonals of which there is an ohmic-inductive load, in particular a dc 
motor, two semiconductor switches which lie diagonally opposite each other 
in the bridge and are closed during a current-application phase, and a 
freerunning current flowing through the load in the freerunning phase. 
In known circuit arrangements of the aforementioned type, the control of, 
in each case, two semiconductor switches lying diagonally opposite each 
other in the bridge in the same direction is effected by one control 
signal so that both semiconductor switches are closed simultaneously at 
the start of a current-application phase so that during that phase the 
amount of current in the load increases, and in the following freerunning 
phase they are placed simultaneously into the non-conductive state. During 
the freerunning phase the current in the load decreases and flows back via 
freerunning diodes into a source of voltage, for instance an automobile 
battery, which feeds the circuit arrangement. The average current which is 
established in the load, i.e. the consuming device, results in this case 
from the pulse duty factor of the controlled semiconductor switches, i.e. 
the ratio of the connect time to the disconnect time, and the time 
constants of the ohmic-inductive load as well as other load parameters. 
Depending on which pair of the semiconductor switches that lie diagonally 
opposite each other in the bridge is controlled in timed fashion while the 
other pair of semiconductor switches in each case is blocked, the current 
flows in positive or negative direction in the load. In this known circuit 
arrangement, therefore, the freerunning diodes conduct the entire current 
flowing through the load in the freerunning phase (freerunning current). 
The freerunning current, however, produces a relatively large voltage drop 
in the freerunning diodes and thus a high loss power. 
SUMMARY OF THE INVENTION 
It is an object of the present invention so to improve a circuit 
arrangement of the aforementioned type that the loss power is reduced. 
According to the invention, at the start of a freerunning phase only one 
(1) of the two diagonally opposite semiconductor switches (1, 4) is opened 
and thereupon a semiconductor switch (3) lying in the bridge alongside the 
conductive semiconductor switch (4) is closed and before the start of a 
then following current-application phase the semiconductor switch (3) 
lying in the bridge alongside the conductive semiconductor switch (4) is 
opened before the opened semiconductor switch (1) of the two diagonally 
opposite semiconductor switches (1, 4) is again closed. 
The invention is based on the principle that two semiconductor switches 
lying diagonally opposite each other in the bridge are no longer 
controlled simultaneously in the same direction so that they conduct or 
block simultaneously while in each case the other two semiconductor 
switches lying diagonally in the bridge are blocked. Rather, in accordance 
with the invention, the four semiconductor switches of the bridge are 
controlled separately and individually by control circuits the 
construction of which is defined by the function described hereinafter. In 
particular, the four semiconductor switches arranged in the bridge include 
four control circuits in order to exert a different control function for 
each semiconductor switch. The four control signals which control the 
individual semiconductor switches are produced by the control circuits can 
be determined by a common desired-value signal and possibly a common 
fed-back actual-value signal. The desired-value signal and the 
actual-value signal can, for instance, be desired and actual average 
current values in the load which lies in the bridge formed with the four 
semiconductor switches. If a dc motor of a servo-drive serves as load, 
then the desired value and the actual value can also be formed by a 
desired position value of the servo-drive and the actual position value 
thereof. A position control with underlying current regulation is also 
realizable. 
The essence of the invention resides therein that the freerunning current 
is no longer conducted only through the freerunning diodes but through a 
pre-established semiconductor switch in the bridge, which switch lies in 
parallel to one of the two semiconductor switches lying diagonally 
opposite each other in the bridge and which are closed during the 
current-application phase within a different branch of the bridge while 
the said semiconductor switch to which it lies in parallel remains closed 
in the conductive state also in the freerunning phase. Due to this, the 
freerunning current flows essentially via these two closed semiconductor 
switches on which thus only slight voltage drops occur. The loss power is 
correspondingly small. The energy which is fed to the load from the 
voltage source can thereby be used more effectively. In the event that a 
dc motor serves as load, its torque will drop only slightly in the 
freerunning phase. The merely slight freerunning voltage which is induced 
on the load is furthermore advantageous. 
The control circuit for the semiconductor switch which predominantly takes 
over the freerunning current provides assurance that said switch only 
conducts when the semiconductor switch lying in series with it in the 
bridge circuit is blocked, so that a high longitudinal current is 
prevented over these semiconductor switches which lie in series. The 
control circuit for the timed semiconductor switch of the two switches 
lying diagonally opposite each other in the bridge is again such that, 
before a following current-application phase, the semiconductor switch 
which had taken over the freerunning current together with the diode lying 
in parallel to it is first blocked. The control circuit for the second of 
the two semiconductor switches which lie diagonally opposite each other in 
the bridge and which conduct the load current in the current-application 
phase need simply effect a continuous conduction of this semiconductor 
switch during the given direction of the current in the load. The last of 
the four semiconductor switches in the bridge has such a control circuit 
that it remains at all times open for this direction of the current in the 
load. 
The control circuit for the semiconductor switch in the bridge branch which 
lies alongside the bridge branch with the conductive semiconductor switch 
of the semiconductor switches lying diagonally opposite each other in the 
bridge which conduct the current through the load in the 
current-application phase is to particular advantage developed in the 
manner that, in the freerunning phase, the semiconductor switch (3) which 
lies in the bridge alongside the conductive semiconductor switch (4) is 
closed when the freerunning diode (D3) thereof has taken over the 
freerunning current, whereby the semiconductor switch is closed during the 
freerunning phase is only controlled into this condition when the 
freerunning diode lying parallel to it has taken over the freerunning 
current. 
In this way, assurance is had that the semiconductor switch lying in series 
with this semiconductor switch in the bridge is blocked and longitudinal 
current is prevented over both semiconductor switches. 
In order to control the above-mentioned control circuit and further control 
circuits, one for each semiconductor switch, there is advantageously 
provided a monitoring circuit (13) which monitors the voltage on the load 
(5) and the switch states of the semiconductor switches (1-4) and controls 
in each case one control circuit (7-10) for each semiconductor switch, 
whereby the monitoring circuit prevents, as a whole, longitudinal 
currents, i.e. the currents which act on the source of voltage but do not 
flow over the load and which can endanger also the semiconductor switches 
conducting them. 
Instead of this monitoring of the switch states of the semiconductors by 
means of the monitoring circuit, a waiting time generator (33) can be 
provided for producing fixed waiting times, each of which controls a 
control circuit (7-12) for each semiconductor switch, whereby the 
monitoring circuit also upon the switching from a current-flow phase to a 
freerunning phase and vice versa prevents longitudinal currents through 
two bridge branches which lie in series. The waiting times can be produced 
in the waiting time generator by counters, monostable multivibrators or 
matching functions which are produced, for instance, by a 
resistorcapacitor combination. Instead of fixed waiting times, variable 
waiting times can also be provided, for example times which are dependent 
on the supply voltage and/or the amount of the load current. 
For the timed operation of the semiconductor switches in the bridge with a 
pulse duty factor which corresponds, in particular, to the difference 
between a desired-value signal and an actual-value signal, the control 
circuits are controlled by a pulse-length modulator (14). 
If a reversal of current direction from positively counted to negatively 
counted current is desired in the load, which also can be determined by 
the difference between desired-value signal and actual-value signal, the 
control circuits for the semiconductor switches in the bridge are widened 
wherein for the controlled current-direction reversal in the load during a 
freerunning phase the semiconductor switch (4) which is still closed of 
the two diagonally opposite semiconductor switches (1-4) is opened while 
the semiconductor switch (3) which lies in the bridge alongside of said 
semiconductor switch (4) remains closed and thereupon the semiconductor 
switch (2) which lies diagonally opposite said last-mentioned 
semiconductor switch (3) is closed; and for the controlled 
current-direction reversal in the load during the current-application 
phase there is first of all opened that one (1) of the two diagonally 
opposite semiconductor switches (1, 4) which was timed-switched before the 
reversal of the direction of current and thereupon the semiconductor 
switch (3) lying in the bridge alongside the conductive semiconductor 
switch (4) of the two diagonally opposite semiconductor switches is 
closed, whereupon the semiconductor switch of the two diagonally opposite 
semiconductor switches (1-4) which is still closed is opened while the 
semiconductor switch (3) lying in the bridge alongside of said 
semiconductor switch (4) remains closed, and thereupon the semiconductor 
switch (2) lying diagonally opposite said last-mentioned semiconductor 
switch (3) is closed. 
With respect to the first above-mentioned construction, in this connection 
the features of the control circuit for the controlled reversal of 
direction of current in the load during a freerunning phase are provided. 
With respect to the second above-mentioned construction, the extensions 
which are to be effected for the controlled current-direction reversal 
during the flow phase is obtained. If the current-direction reversal is to 
take place the semiconductor switches are thus first of all to be brought 
from the current-application phase into the freerunning phase. The 
reversing of the four control circuits for the semiconductor switches in 
the bridge is controlled by a common current-direction reversal circuit. 
According to a feature of the invention, current-direction reversal circuit 
(12) in each case controls a control circuit for each semiconductor 
switch. 
As semiconductor switches (1-4) in the bridge there are preferably used 
MOSFET transistors, each having an integrated freerunning diode. 
Other variations of semiconductor switches in the bridge which are suitable 
depending on the purpose of use are as follows: 
Each of the semiconductor switches (3, 4) comprises two interconnected NPN 
bipolar transistors (36, 37) with an additional freerunning diode (D3; 
D4). 
Also, two semiconductor switches (3; 4) lying alongside of each other in 
the bridge are MOSFET semiconductors and two other semiconductor switches 
(1; 2) lying alongside each other in the bridge are bipolar transistors.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
In FIGS. 1 and 2, 1-4 are semiconductor switches which are arranged in a 
bridge circuit. An ohmic-conductive load 5 is present in one of the 
diagonals of the bridge. The bridge is fed by a source of voltage 6 of 
polarity +U shown in FIG. 1. A freerunning diode D1-D4 is connected 
directly in parallel to each of the controlled switches 1-4. 
Each of the four semiconductor switches is controlled by a control circuit, 
not shown in FIGS. 1 and 2, but which can be noted in FIGS. 3-5. The 
control circuits are provided therein with the reference numbers 7-10. The 
construction and the control function of each control circuit can be noted 
from the following description of the switch states of the semiconductor 
switches 1-4 in FIGS. 1 and 2. 
In FIG. 1 it is assumed that for a given direction of flow--arrow 11--in 
the load 5, the semiconductor switches 1 and 4 are closed during a 
current-application phase. There results an interruptable course of the 
current from the voltage source via the semiconductor switch 1, and load 
5, and the semiconductor switch 4 back to the source of voltage. 
The flow of current from the voltage source is interrupted in the manner 
that the semiconductor switch 1 is blocked while the semiconductor switch 
4 remains closed. In this way the freerunning phase commences during which 
the current continues to flow, while fading away, through the 
ohmic-conductive load 5, corresponding to the dot-dash course of the 
current further over the conducting semiconductor switch 4 and initially 
over the freerunning diode D3. When the control circuit 9 in FIG. 3 has 
reported that the semiconductor switch 1 blocks and the freerunning diode 
D3 has taken on freerunning current, the semiconductor switch 3 is brought 
into the conductive state. It thus takes over a substantial part of the 
current flowing through the load 5. 
When the load 5 is again to be fed current from the voltage source 6, the 
semiconductor switch 3 is first of all opened by the control circuit 9. 
When the control circuit 7 for the semiconductor switch 1 has reported 
that this process is complete, the semiconductor switch 1 is again closed. 
The timed switching operation described can start over again. 
The semiconductor switch 4 remains at all times closed during the entire 
timed control for the current direction 11, its control circuit 10 being 
designed for this. 
If a reversal of the direction of current to a direction opposite the arrow 
11 in FIG. 1 is to take place in the load, which is determined by a 
current-direction reversal circuit 12 in FIGS. 3 to 5, then the 
corresponding control functions take place as follows during the 
freerunning phase in which the semiconductor switches 3 and 4 are closed: 
First of all, the semiconductor switch 4 is opened. The current then flows 
in the load further over the semiconductor switch 3 and over the 
freerunning diode D2 back into the battery. As soon as it has been 
recognized that the semiconductor switch 4 is open, which can be effected 
with a monitoring unit 13--see FIG. 3--the semiconductor switch 2 is 
closed by its control circuit 8. The current in the load flows further, 
dying away against the voltage of the source of voltage until it has 
dropped to zero (end of the freerunning phase) and then again increases in 
the desired reverse direction (new current-application phase). 
The semiconductor switch 3 remains closed during the entire time that 
current is to flow through the load in the direction opposite the arrow 
11. 
From the dot-dash course of the current in FIG. 2 it can be seen how the 
current flows in the freerunning phase when a current-direction reversal 
command is given in it by the current-direction reversal circuit 12 and 
the semiconductor switch 4 is already open. 
If the command for the reversal of the direction of current is given during 
the current-application phase when the semiconductor switches 1 and 4 are 
closed, the semiconductor switch 1 is first of all opened and the 
semiconductor switch 3 then closed, as described above for the transition 
from the current-flow phase to the freerunning phase. In the freerunning 
phase which is then thus present, the further control of the semiconductor 
switches takes place in the manner also described above, as though the 
command for the reversal of the direction of flow had occurred originally 
in the freerunning phase. 
FIG. 3 shows that an input signal, representing, for instance, a control 
deviation of a control variable which is to be regulated with the load 5, 
or a current control signal for the load 5 acts on a pulse-length 
modulator 14 and on the current-direction reversal circuit 12. The 
pulse-length modulator produces from the analog input signal a timed 
output signal which lies on a bus line 14a. The current-direction reversal 
circuit produces, at given limit values of the input signal, 
current-direction reversal commands on the bus line 15. An output of 
monitoring unit 13 is connected to another bus line 16. All bus lines are 
connected to inputs of four control circuits 7-10 for the four 
semiconductor switches 1-4. In FIGS. 3-5 it is indicated that the 
freerunning diodes D1-D4 are integrated in the semiconductor switches 1-4 
when the latter are developed in MOSFET technique. It is particularly 
suitable if the semiconductor switches 3 and 4 are N-Channel MOSFETs which 
are acted on by positive control voltages. The semiconductor switches 1 and 
2 can also be MOSFETs, or else bipolar or other semiconductor switches. 
With the monitoring unit 13, the potentials or voltages of the switch paths 
of the semiconductor switches 1-4 are monitored as well as the voltage on 
the load 5. For this the monitoring lines 16a-19 are used. Additional 
monitoring lines 21 and 22 report the control voltages for the 
semiconductor switches 4 and 3 back to the monitoring unit. 
The circuit arrangement of FIG. 4 differs from that of FIG. 3 first of all 
by the fact that, as input signal, there is used a desired current value 
which is fed into the pulse-length modulator 14 and the current-direction 
reversal circuit 12. Furthermore, by an actual-value line 22 a current 
actual-value is fed into the pulse-length modulator and the 
current-direction reversal circuit. Within the pulse length modulator and 
the current-direction reversal circuit the difference between desired 
value and actual value is formed and a corresponding 
pulse-length-modulated output variable or a current-direction command is 
formed. 
In order to form the actual current value, currents can be detected in the 
load 5, in all the semiconductor switches 1-4 and in the feed lines to the 
voltage source, which are not provided with reference numbers, as shown in 
detail by current detection lines 23-29. The current detection lines 23-29 
are brought--shown combined with a strand 30--to a current-detection 
circuit arrangement 32. 
Furthermore, in FIG. 4 the bus line 16, instead of being connected to the 
(voltage) monitoring unit 13 in FIG. 3, is connected to a waiting-time 
generator 33 with which the waiting times are produced upon the switching 
of the semiconductor switches so that no undesired switch states occur 
which cause, in particular, longitudinal currents in the bridge circuit. 
As a whole, with the circuit arrangement of FIG. 4 a current is established 
in the load 5 which is equal to the desired value set. 
The circuit arrangement of FIG. 5 differs from that of FIG. 4 by the fact 
that there is used as load a dc servomotor of a position-regulating device 
which is equipped with a position-feedback. The dc servomotor is designated 
34. A position feedback line is designated 35. It leads to a position 
actual-value detection device 31 which, in its turn, produces on the 
actual-value line 22 an actual-value signal which corresponds to the 
position set with the dc servomotor. The actual value is fed, similarly to 
a position desired value, again into the pulse-length modulator 14 and the 
current-direction reversal circuit 12. The circuit shown in FIG. 5 
otherwise acts in the same way as that of FIG. 4, in which connection, 
however, in this case the position predetermined by the position desired 
value is set by the dc servomotor 34. 
In FIG. 6, the semiconductor switch of the bridge which is designated 
generally as 3 is shown in further detail. It comprises two NPN bipolar 
transistors 36, 37 in accordance with FIG. 6, with the freerunning diode 
D3. The NPN bipolar transistors 36, 37 are, via in each case a resistor 38 
and 39 respectively, at a potential of the voltage source and are 
controlled via the series resistors 40 and 41 respectively as explained in 
connection with FIGS. 1 and 2. In FIG. 7, U.sub.1, U.sub.2, U.sub.3, 
U.sub.4 show the variation with time of the voltages which correspond to 
the currents in the semiconductor switches 1, 2, 3, 4 in FIG. 1. The 
voltages U.sub.1 -U.sub.4 are produced by transformation from the currents 
which flow in the branches of the bridge circuit. The transformers are 
indicated without reference numbers in FIG. 3. To the voltage courses 
U.sub.1 -U.sub.4 there corresponds an input signal which, in accordance 
with FIG. 3, acts on the pulse-length modulator 14 and the 
current-direction reversal circuit 12. The output voltage of the 
pulse-length modulator is designated U.sub.PWM in FIG. 7 and the output 
voltage of the current-direction reversal circuit 12 is indicated as 
U.sub.out12. A positive direction of current corresponding to the arrow 11 
in FIG. 1 is to correspond to the output voltage U.sub.out12 in FIG. 7. As 
already described in connection with FIG. 1, for this direction of current 
the semiconductor switches 1 are closed as from the time t.sub.1, which is 
indicated by a high voltage level U.sub.1 , while the semiconductor switch 
3 is opened, which is indicated by a low voltage level U.sub.3. The 
semiconductor switch 2 is continuously blocked--see lower level U.sub.2 
--while the semiconductor switch 4 conducts continuously--see high level 
U.sub.4. If, in accordance with the voltage signal U.sub.PWM, the clock 
ratio which is dependent on the input signal, the current flow from the 
voltage source 6 is interrupted at the time t.sub.2, the current drops and 
thus the voltage U.sub.1 drops in the branch in which the semiconductor 
switch 1 is located. In this freerunning phase which commences at the time 
t.sub.2, the switch 3 is initially not yet made conductive; see the low 
remaining voltage level U.sub.3. Only at the end of the freerunning phase 
at time t.sub.3 when it is reported that the current through the 
semiconductor switch U.sub.1 has entirely faded away is the semiconductor 
switch 3 made conductive; see the rising level of U.sub.3 as from t.sub.3. 
In this connection, the semiconductor switch 4 remains closed as always 
during this direction of flow; see high level U.sub.4, and the 
semiconductor switch 2 remains open; see low level U.sub.2. 
In FIG. 7 it is further indicated how a shorter high level of the pulse 
U.sub.PWM up to t.sub.5 than the time difference t.sub.1 minus t.sub.2 
corresponds to a decreasing input signal as from the time t.sub.4. The 
turn-on time of the switch 1 is correspondingly shortened, see the voltage 
U.sub.1, as is the disconnect time or blocking time of the switch 3, see 
the voltage U.sub.3, which, however, rises again after a further 
freerunning phase from t.sub.5 to t.sub.6. 
In FIG. 7 the time difference t.sub.4 minus t.sub.1 corresponds to the 
period or repetition time of the pulse U.sub.PWM which is given off by the 
pulse-length modulator and which, in contradistinction to the pulse duty 
factor or the connecting time of the pulse, is constant independently of 
the input signal. 
The said pulse duty factor is referred to there also as pulse pause ratio. 
A preferred embodiment of the pulse-length modulator 14 of FIG. 5 is shown 
diagrammatically in FIG. 8. The pulse-length modulator comprises a 
sawtooth generator 42 with integrator which gives off a sawtooth output 
voltage on a line 43. The line 43 is connected to one input each of a 
comparator 44 and 45 respectively. A second input each of the two 
comparators is connected to the output of a function generator 46 and 47 
respectively. The function generator 46 transforms a positive input 
voltage into a proportional output voltage if the input voltage is 
positive and does not produce an output voltage when the input voltage is 
negative. The function generator 47 does not produce any output voltage 
when the input voltage is positive and produces an output voltage 
proportional to the input voltage with reverse sign when the input voltage 
is negative. Both comparators are fed with the input signal U.sub.in via 
addition members 48, 49 into which an additional offset signal can be fed 
for displacement of the input voltage. The offset signal serves for the 
zeropoint displacement of the bend of the characteristic curve in the 
function members. When the offset signal is zero, the function generator 
46 gives off, in the event of input signals greater than zero, an output 
signal which is compared in the comparator with the sawtooth signal on the 
line 43. Conversely, in the case of an input signal less than zero the 
comparator 45 is acted on by the function generator 47 and gives off an 
output signal. The output signals of the two comparators are designated 
U.sub.PWM1 and U.sub.PWM2. They pass into the bus line 14a in FIG. 5. It 
is pointed out that for an understanding of the circuit arrangement in 
FIG. 5 and of the time functions of the switch states in FIG. 7, an output 
signal U.sub.PWM of the pulse-length modulator which can correspond, for 
instance, to U.sub.PWM in FIG. 8 is sufficient. 
A preferred embodiment of the current-direction reversal circuit comprises 
two function generators 49, 50 which are fed parallel to each other with 
the input signal U.sub.in and on the outputs of which the output voltages 
U.sub.out1 and U.sub.out2 are produced. The characteristic curves of the 
function generators are shown in the blocks. The function generator 49 
gives off a constant output voltage U.sub.out1 only in the case of a 
positive input voltage while the function generator 50 gives off an output 
voltage U.sub.out2 in the event of a negative input signal. These signals 
U.sub.out1 and U.sub.out2 are fed into the bus line 15 in FIG. 3. It is 
pointed out that for an understanding of the functions of the entire 
circuit arrangement for the clock control of semiconductor switches one 
output signal U.sub.out is sufficient, for which reason only one output 
signal U.sub.out12 is shown in the time graph of FIG. 7. 
In FIG. 10, on the other hand, the output signals U.sub.out1 and U.sub.out2 
are shown as a function of an input signal U.sub.in in the event of an 
offset voltage of zero. 
FIG. 11 shows an example of a current-detection circuit which converts the 
currents in the branches of the bridge circuit and in other lines 
connected with the bridge circuit into a proportional voltage, for 
instance the voltages U.sub.1, U.sub.2, U.sub.3, U.sub.4. Each 
current-detection circuit consists of a measurement resistor, for 
instance, 51 on which a voltage U drops as a function of a current I. 
FIG. 12 shows a monitoring unit for all semiconductor switches. The 
monitoring unit comprises four comparators 51-54 each of which is preset 
to a desired value and the outputs of which lead to the bus line 16. 
Inputs of the comparators 53, 54 are connected to the lines 20, 21 at the 
control inputs of the semiconductor switches 4 and 3. Further monitorings 
take place via the lines 17 and 19 on the load 5 by means of the 
comparators 51 and 52. 
The function of the monitoring unit will be explained below with reference 
to FIG. 13 in which time graphs of the signals U.sub.1 -U.sub.4, 
U.sub.PWM1, U.sub.PWM2, U.sub.out1, U.sub.out2 a.sub.n d the load voltages 
with respect to ground potential are shown, namely, on the one hand, as the 
load voltage on the line 19 and, on the other hand, as the load voltage on 
the line 17 with respect to ground potential. FIG. 13 concerns a given 
direction of current through the load, in this case positive. FIG. 13 
shows the variations with time furthermore even more accurately than they 
are shown in FIG. 7. The starting point is the time t.sub.2 at which the 
output signal U.sub.PWM1 of the pulse-length modulator drops to a lower 
level and directly blocks the semiconductor switch 1. When the voltage 
signal U.sub.1 on the semiconductor switch 1 becomes smaller, the voltage 
on the load resistance U.sub.load on line 19 with respect to ground 
potential also drops. If in this connection the voltage on the line 19 
reaches a preset threshold value at the time t.sub.3, this signals the end 
of the freerunning phase between t.sub.2 and t.sub.3 and the semiconductor 
switch 3 is made conductive, which is signaled by the rising potential 
U.sub.3. At the time t.sub.4 the output signal U.sub.PWM1 of the 
pulse-length modulator, on the other hand, gives the command to block the 
semiconductor switch 3 which, at the time t.sub.5, reaches a predetermined 
level, which again causes a switching-on of the semiconductor switch 1; see 
rising signal level U.sub.1 on the last-mentioned semiconductor switch. 
FIG. 14 shows, in manner similar to this the variations with time of the 
signals when a negative current direction through the load 5 is caused by 
the output voltages U.sub.out1 and U.sub.out2 of the current-direction 
reversal circuit 12. In this case, the disconnecting of one of the 
semiconductor switches 2 and 4 is determined directly by the output signal 
U.sub.PWM2 of the pulse-length modulator while the connecting of these 
semiconductor switches takes place with time delay when the monitoring 
unit signals that the voltage condition has been reached. 
In FIG. 15 there is shown an embodiment of a waiting-time generator 33 of 
FIG. 5 which causes the turning on of given semiconductor switches of the 
bridge circuit, not as a function of a monitored voltage condition but of 
a fixed predetermined waiting time .tau.1 or .tau.2. The delay .tau.1 
takes place between the positive ascending flank of an output signal 
U.sub.PWM1 or U.sub.PWM2 of the pulse-length modulator and the 
semiconductor switch which is to be connected to this signal while the 
delay .tau.2 takes place between the rear flank of the signal U.sub.PWM1 
or U.sub.PWM2 and the semiconductor switch which is to be made conductive 
by this. The delay times .tau.1 and .tau.2 are entered as examples in the 
right-hand upper part of FIG. 14. 
In FIG. 15 there is shown an embodiment of a waiting-time generator with 
which the time delays .tau.1 and .tau.2 are produced. It consists 
essentially of two monostable flip-flops with trigger input 55 and 56 
which from a flank at the input produce a pulse of the length 1 or 2. The 
monostable flipflops are controlled, as shown in FIG. 15, via OR-members 
57, 58 by the outputs U.sub.PWM1 or U.sub.PWM2 of the pulse-length 
modulator. The OR-member 57 is so connected that it permits the passage of 
the front flank of U.sub.PWM1 in order to produce the delay time .tau.1 
with the monostable flipflop 55. The OR-member 58, on the other hand, has 
inverting inputs so that the rear flank is passed as trigger signal for 
the production of .tau.2. 
FIGS. 16-19 show examples of the control circuits which are to be viewed in 
combination with the monitoring unit of FIG. 12. The functions of the 
control circuits result directly from the generally known symbols; in 
addition, the signal diagrams in FIGS. 13 and 14 can be utilized: 
The control circuit 9 in FIG. 3 consists of an AND-member 59 with inverting 
inputs as well as a subsequent OR-member 60. With the OR-member 59 there is 
effected the clocking of the switch 3 which is made conductive when the 
output signal U.sub.PWM1 of the pulse-length modulator is low and the 
signal voltage on the line 19 of the monitoring unit 13, see FIG. 12, is 
less than the predetermined threshold. The semiconductor switch 3, on the 
other hand, is continuously connected via the OR-member 60 directly when 
the output voltage U.sub.out2 of the current-direction reversal circuit 12 
is high for negative directions of current. 
The control circuit 7 in FIG. 3 for the semiconductor switch 1 is shown in 
FIG. 17. It consists of an AND-member 61 with an inverting input which 
lies at the output of the comparator 54 in FIG. 12. The outer input is fed 
with U.sub.PWM1. Similar to the control circuit in FIG. 16, the control 
circuit 10 of FIG. 3 is shown in FIG. 18 with the AND-member 62 with 
inverting inputs as well as the following OR-member 63. The AND-member is 
fed here with the signal U.sub.PWM2 and from the comparator 51. The one 
input of the OR-member, on the other hand, receives the signal U.sub.out1 
of the current-direction reversal circuit and continuously switches the 
semiconductor switch 4 when the output signal U.sub.out1 of the 
current-direction reversal circuit 12 gives off a signal with high level. 
The control circuit 8 of FIG. 3 shown in FIG. 19 corresponds, in its turn, 
to the control circuit according to FIG. 17, with the exception that in 
this case an AND-member 64 having an inverting input is connected to the 
output of the comparator 53 while the other noninverting input is acted on 
by the signal U.sub.PWM2.