Display panel, methods of fabricating and repairing the same

The present application discloses a display panel including an array substrate and an opposing substrate facing the array substrate; a data line layer having a plurality of data lines on the array substrate; a passivation layer on a side of the data line layer proximal to the opposing substrate; a sealant layer on a side of the passivation layer distal to the data line layer, sealing the array substrate and the opposing substrate together; the display panel having a first area enclosed by the sealant layer and a second area outside of the first area and the sealant layer; the plurality of data lines extending from the first area into the second area; and a common electrode layer on a side of the sealant layer distal to the passivation layer. The common electrode layer includes a portion having a plurality of connections, and a plurality of slits spaced apart from each other by the plurality of connections; the plurality of slits and the plurality of connections extending from the first area into the second area, each of the plurality of connections is between two adjacent slits; each of the plurality of connections has a first portion in the first area and a second portion in the second area.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a national stage application under 35 U.S.C. § 371 of International Application No. PCT/CN2016/094093 filed Aug. 9, 2016, the contents of which are incorporated by reference in the entirety.

TECHNICAL FIELD

The present invention relates to a display panel, and methods of fabricating and repairing the same.

BACKGROUND

Liquid crystal display devices have found a wide range of applications in display technology field. Typically, liquid crystal display devices include an array substrate and a opposing substrate (e.g., a color filter substrate) packaged together. The array substrate and the opposing substrate are fabricated separately, then assembled to produce a display panel.

SUMMARY

In one aspect, the present disclosure provides a display panel comprising an array substrate and an opposing substrate facing the array substrate; a data line layer comprising a plurality of data lines on the array substrate; a passivation layer on a side of the data line layer proximal to the opposing substrate; a sealant layer on a side of the passivation layer distal to the data line layer, sealing the array substrate and the opposing substrate together; the display panel comprising a first area enclosed, by the sealant layer and a second area outside of the first area and the sealant layer, the plurality of data lines extending from the first area into the second area; and a common electrode layer on a side of the sealant layer distal to the passivation layer.

Optionally, the common electrode layer comprises a portion having a plurality of connections, and a plurality of slits spaced apart from each other by the plurality of connections; the plurality of slits and the plurality of connections extending from the first area into the second area, each of the plurality of connections is between two adjacent slits; each of the plurality of connections has a first portion in the first area and a second portion in the second area.

Optionally, each of the plurality of connections is configured to be insulated from the common electrode layer when cut at both the first portion and the second portion.

Optionally, the display panel further comprises a common electrode signal line layer on the array substrate; the sealant layer comprises a plurality of conductive components; and the common electrode layer on the opposing substrate and the common electrode signal layer on the array substrate are electrically connected by the plurality of conductive components.

Optionally, the display panel further comprises an insulating layer on a side of the common electrode signal line layer proximal to the sealant layer; and a conductive layer on a side of the insulating layer distal to the common electrode signal line layer; the conductive layer being electrically connected to the common electrode signal line layer through a via extending through the insulating layer; the common electrode layer on the opposing substrate and the conductive layer on the array substrate are electrically connected by the plurality of conductive components.

Optionally, the plurality of conductive components are a plurality of gold balls.

Optionally, the plurality of data lines extending from the first area into the second area through an area substantially corresponding to the portion of the common electrode layer having the plurality of slits and the plurality of connections in plan view of the display panel.

Optionally, each of the plurality of connections corresponds to each of the plurality of data lines; a projection of each of the plurality of connections on the array substrate overlaps that of each of the plurality of data lines in plan view of the display panel.

Optionally, the common electrode layer further includes at least one insulated island in the portion having the plurality of connections and the plurality of slits; the plurality of slits being spaced apart from each other by the plurality of connections and the at least one insulated island, each of the at least one insulated island being between two slits adjacent thereto, extending from the first area into the second area; and each of the at least one insulated island is insulated from the rest of the common electrode layer by the two slits adjacent thereto, a first gap in the first area, and a second gap in the second area; the two slits adjacent thereto, the first gap and the second gap surrounding a complete periphery of each of the at least one insulated island.

Optionally, the opposing substrate is a color filter substrate.

In another aspect, the present invention provides a display apparatus comprising a display panel described herein.

In another aspect, the present invention provides a method of repairing an electrical short circuit between a data line and a common electrode layer in the display panel described herein, comprising identifying the data line involved in the electrical short circuit; identifying a connection in the display panel from an area corresponding to the data, line in plan view of the display panel; and insulating the connection from the common electrode layer by disconnecting the connection from the common electrode layer at both the first portion and the second portion.

Optionally, the step of insulating the connection from the common electrode layer is performed by laser cutting the connection at both the first portion and the second portion.

In another aspect, the present invention provides a method of fabricating a display panel, comprising forming an opposing substrate on a first base substrate; the step of forming the opposing substrate comprising forming a common electrode layer on the first base substrate; forming an array substrate on a second base substrate; the step of forming the array substrate comprises forming a data line layer comprising a plurality of data lines on the second base substrate; and forming a passivation layer on a side of the date line layer distal to the second base substrate; and sealing the opposing substrate and the array substrate by a sealant layer thereby forming the display panel comprising a first area enclosed by the sealant layer and a second area outside of the first area and the sealant layer.

Optionally, the step of forming the common electrode layer comprises forming plurality of connections, and a plurality of slits spaced apart by the plurality of connections in a portion of the common electrode layer; the plurality of slits and the plurality of connections extending from the first area into the second area, each of the plurality of connections is between two adjacent slits; and each of the plurality of connections is formed to have a first portion in the first area and a second portion in the second area.

Optionally, the step of forming the array substrate further comprises forming a common electrode signal line layer on the second base substrate; and the step of sealing the opposing substrate and the array substrate by die sealant layer comprises forming a sealant layer comprising a plurality of conductive components; and the method further comprising electrically connecting the common electrode layer and the common electrode signal line layer by the plurality of conductive components in the sealant layer.

Optionally, the step of forming the array substrate further comprises forming an insulating layer on a side of the common electrode signal line layer proximal to the sealant layer; forming a conductive layer on a side of the insulating layer distal to the common electrode signal line layer; forming a via extending through the insulating layer; electrically connecting the conductive layer and the common electrode signal line layer through the via; and electrically connecting the common electrode layer and the conductive layer by the plurality of conductive components.

Optionally, the plurality of conductive components are a plurality of gold balls.

Optionally, the data line layer is formed so that the plurality of data lines extending from the first area into the second area through an area substantially corresponding to the portion of the common electrode layer having the plurality of slits and the plurality of connections in plan view of the display panel.

Optionally, the data line layer and the common electrode layer are so formed that each of the plurality of connections corresponds to each of the plurality of data lines; a projection of each of the plurality of connections overlaps a projection of each of the plurality of data lines in plan view of the display panel.

DETAILED DESCRIPTION

In some conventional, display panels, the common electrode layer is disposed in the opposing, substrate and the common electrode signal line is disposed in the array substrate. Conventional display panels use a sealant layer made of a mixture of resin and gold balls for electrically connecting the common electrode layer in the opposing substrate and the common electrode signal line in the array substrate. In conventional display panels, the data line layer and the gold balls in the sealant layer are insulated merely by a thin passivation layer. Typically, the passivation layer has a thickness in the range of approximately 2000 Å to approximately 9000 Å, and thus is prone to physical damages and electrostatic breakdown, leading to an electrical short circuit between the common electrode layer and the data line (D-C short).

In one aspect, the present disclosure is directed to a novel display panel, methods of fabricating and repairing the same that substantially obviates one or more of the problems due to limitations and disadvantages of the related art. In some embodiments, the present display panel includes an array substrate and an opposing substrate facing the array substrate; a data line layer having a plurality of data lines on the array substrate; a passivation layer on a side of the data line layer proximal to the opposing, substrate; a sealant layer on a side of the passivation layer distal to the data line layer, sealing the array substrate and the opposing substrate together the display panel having: a first area enclosed by the sealant layer and a second area outside of the first area and the sealant layer; the plurality of data lines extending from the first area into the second area; and a common electrode layer on a side of the sealant layer distal to the passivation layer. The common electrode layer in the present display panel includes a portion having a plurality of connections, and a plurality of slits spaced apart from each other by the plurality of connections. Optionally, the plurality of slits and the plurality of connections extend from the first area into the second area. Each of the plurality of connections is between two adjacent slits. Each of the plurality of connections has a first portion in the first area and a second portion in the second area.

FIG. 1is a diagram illustrating the structure of a display panel in some embodiments. Referring toFIG. 1, the display panel in the embodiment includes an array substrate AS and an opposing substrate PS facing the array substrate AS. The line101inFIG. 1indicates an edge of the array substrate AS, and the line102indicates an edge of the opposing substrate PS. The display panel includes a display area104and a peripheral area outside of the display area. On one side of the display panel, various signal lines are connected to a printed circuit board (not shown inFIG. 1) in a fan-out area103, which is a part of the peripheral area of the display panel.

The display panel further includes a sealant layer105for sealing the array substrate AS and the opposing substrate PS together to form a cell. The sealant layer105divides the display panel into two areas, i.e., a first area A enclosed by the sealant layer105and a second area B outside of the first area A and the sealant layer105(see, also, areas “A” and “B” inFIG. 1).

Referring toFIG. 1, the display panel further includes a data line layer having a plurality of data lines106. The plurality of data lines106extend from the display area104of the display panel into the peripheral area of the display panel. After the plurality of data lines106exit the display area104, they enter into the first area A enclosed by the sealant layer105. The plurality of data lines106extend from the first area A into the second area B, crossing over an interface area (see area “I” inFIG. 4) corresponding to the sealant layer105. In plan view of the display panel, the plurality of data lines104crosses over a projection of the sealant layer105on the array substrate.

In some embodiments, the common electrode signal for the common electrode layer in the opposing substrate is provided by the common electrode signal line layer disposed in the array substrate. For example, the display panel may include a common electrode layer in the opposing substrate electrically connected to a common electrode signal line layer in the array substrate. Various embodiments may be practiced to electrically connect the common electrode layer in the opposing substrate to the common electrode signal line layer in the array substrate. Optionally, the common electrode layer in the opposing substrate is electrically connected to the common electrode signal line layer in the array substrate through the sealant layer in the peripheral area. For example, they may be connected in an area X as shown inFIG. 1.

FIG. 2is a diagram illustrating the structure of a display panel in some embodiments. Referring toFIG. 2, the opposing substrate PS in the display panel includes a first base substrate208, a black matrix layer207on the first base substrate208, and a common electrode layer206on a side of the black matrix layer distal to the first base substrate208. Me array substrate AS in the display panel includes a second base substrate201, a common electrode signal line layer300on the second base substrate201, an insulating layer301on a side of the common electrode signal line layer300distal to the second base substrate201, and a conductive layer302on a side of the insulating layer301distal to the common electrode signal line layer300. The insulating layer301includes a via303, and the conductive layer302is electrically connected to the common electrode signal line layer300through the via303extending through the insulating layer301.

Referring toFIG. 2, the display panel further includes a sealant layer105between the array substrate AS and the opposing substrate PS, sealing the array substrate AS and the opposing substrate PS together into a cell. The sealant layer105includes a plurality of conductive components209. The common electrode layer206in the opposing substrate PS may be electrically connected to the common electrode signal line layer300in the array substrate AS through the conductive components209in the sealant layer105. Optionally, the common electrode layer296is electrically connected to the common electrode signal line layer300through the conductive component209and the conductive layer302extending through the via303in the insulating layer301. In some embodiments, the common electrode layer206is an integral layer extending throughout the opposing substrate PS.

Examples of conductive components209include, hut are not limited to, metal balls such as gold balls or nickel balls. Various embodiments may be practiced to make the conductive components209. In some examples, the conductive components209are made of elastic resin particles coated with metals such as gold or nickel. Optionally, the conductive components209have a size in the range of approximately 1 μm to approximately 500 μm.

Referring toFIG. 1, the common electrode layer206in the embodiment includes a slit area SA having a plurality of connections C, and a plurality of slits S spaced apart from each, other by the plurality of connections C. Each of plurality of connections C is arranged between two adjacent slits S. As shown inFIG. 1, the plurality of slits S and the plurality of connections C extend from the first area A into the second area. B. i.e., the plurality of slits S and the plurality of connections C in plan view of the display panel cross over a projection of the sealant layer105on the array substrate. A projection of the sealant layer105on the slit S divides the slit S into a first portion in the first area A and a second portion in the second area B. A projection of the sealant layer105on the connection C divides the connection C into a first portion in the first area A and a second portion in the second area B. Thus, each of the plurality of connections C has a first side in the first area A and a second side in the second area B.

FIGS. 3A-3Bare diagrams illustrating the structure of a connection and two adjacent slits in some embodiments.FIG. 3Ashows a connection C sandwiched by two adjacent slits S in a common electrode layer206. As shown inFIG. 3A, a projection of the sealant layer105on the connection C divides the connection C into a fast portion C1in the first area A and a second portion C2in the second area B. The connection C may be cut from both sides to be insulated from the rest of the common electrode layer206.FIG. 3Bshows an insulated island after the connection C being cut at both the first portion C1in the first area A and the second portion C2in the second area B.

Referring toFIG. 1, the display panel in the embodiment includes a plurality of connections C and a plurality of slits S in the slit area SA. The slit area SA corresponds to an area where the plurality of data line106extending from the first area A into the second area B. In some embodiments, each connection C corresponds to one or more data line106, e.g., a projection of each connection C on the array substrate AS overlaps with that of one or more data line106in plan view of the display panel. Optionally, each connection C corresponds to a single data line106, e.g., a projection of each connection C on the array substrate AS overlaps with that of a single data line106in plan view of the display panel. Optionally, the plurality of data lines106are arranged so that a projection of substantially all data lines106on the array substrate AS overlaps with that of substantially all connection C in plan view of the display panel.

Referring toFIG. 1, the plurality of data lines106exiting from the slit area SA are connected to a plurality of gate line-data line bridges107(G-D bridges) in the fan-out area103, and in turn connected to a plurality of bonding pads108for bonding with a printed circuit board.

FIG. 4shows a cross-sectional view along the A-A′ direction of the display and ofFIG. 1. Referring toFIG. 4, the display panel in the embodiment includes an array substrate AS, an opposing substrate PS facing the array substrate AS, and a sealant layer105sealing the array substrate AS and the opposing substrate PS together in a cell. The opposing substrate PS inFIG. 4includes a first base substrate208, a black matrix layer207on the first base substrate208, and a common electrode layer206on a side of the black matrix layer207distal to the first base substrate208. In the first area A, the array substrate AS includes a second base substrate201, a gate insulating layer203on the second base substrate201, a data line layer106on a side of the gate insulating layer203distal to the second base substrate201, and a passivation layer204on a side of the data line layer106distal to the gate insulating layer203. The sealant layer105is on a side of the passivation layer204distal to the data line layer106, and on a side of the common electrode layer206distal to the black matrix layer207, the sealant layer105is sandwiched between the common electrode layer206and the passivation layer204in the interface area I.

Various appropriate materials may be used to make the passivation layer204. Examples of appropriate materials include, but are not limited to, silicon nitride (SiNx), silicon oxide (SiOx), and silicon oxide nitride (SiOxNy). Optionally the passivation layer204has a thickness in the range of approximately 2000 Å to approximately 9000 Å.

Referring toFIG. 4, the data line106extends from the first area A and the interface area I into the second area B. In the second area B, the array substrate AS includes a G-D bridge107and a bonding pad108. The G-D bridge107includes a gate line layer202on the second base substrate201, a gate insulating layer203on a side of the gate line layer202distal to the second base substrate201, a data line layer106on a side of the gate insulating layer106distal to the gate line layer202, a passivation layer204on a side of the data line layer106distal to the gate insulating layer203, and a conductive layer205on a side of the passivation layer204distal to the data line layer106. The conductive layer205is electrically connected to the data line layer106through a via extending through the passivation layer204.

The bonding pad108inFIG. 4includes a gate line layer202on the second base substrate201, a gate insulating layer203on a side of the gate line layer202distal to the second base substrate201, a passivation layer204on a side of the gate insulating layer203distal to the gate line layer202, and a conductive layer205on a side of the passivation layer204distal to the gate insulating layer203. The conductive layer205is electrically connected to the gate line layer202through a via extending through the passivation layer204and the gate insulating layer203.

FIG. 5shows a cross-sectional view along the B-B′ direction of the display panel ofFIG. 1. Referring toFIG. 5, the display panel in the embodiment includes an array substrate AS, an opposing substrate PS facing the array substrate AS, and a sealant layer105sealing the array substrate AS and the opposing substrate PS together in a cell. The opposing substrate PS inFIG. 5includes a first base substrate208, a black matrix layer207on the first base substrate208, and a common electrode layer206on aside of the black matrix layer207distal to the first base substrate208. The common electrode layer206includes a plurality of connections C, and a plurality of slits S spaced apart from each other by the plurality of connections C. Each of plurality of connections C is arranged between two adjacent slits S.

The array substrate AS inFIG. 5includes a second base substrate201, a gate line layer202on the second base substrate201, a gate insulating layer203on a side of the gate line layer202distal to the second base substrate201, a data line layer106on a side of the gate insulating layer203distal to the second base substrate201, and a passivation layer204on a side of the data line layer106distal to the gate insulating layer203.

The sealant layer105inFIG. 5is on a side of the passivation layer204distal to the data line layer106, and on a side of the common electrode layer206distal to the black matrix layer207, i.e., the sealant layer105is sandwiched between the common electrode layer206and the passivation layer204. The sealant layer105includes a plurality of conductive components209.

As shown inFIGS. 4 and 5, the data line layer106and the conductive component209are insulated by the passivation layer204. Typically, the passivation layer204has a thickness in the range of approximately 2000 Å to approximately 9000 Å. The passivation layer204is prone to physical damages, e.g., those resulting from the conductive component209being pressed against the passivation layer204. Moreover, the passivation layer204is also prone to electrostatic breakdown. For example, the electrostatic breakdown voltage for a passivation layer204having a thickness in the range of approximately 2000 Å to approximately 9000 Å is typically in the range of 100 V to 300 V, whereas electrostatic voltage in a display panel may be as high as 2000 Å. Therefore, one issue associated with the conventional display panel is the electrical short circuit occurred between a data line106and a common electrode layer206.

In another aspect, the present disclosure provides a method of repairing an electrical short circuit between the data line and the common electrode layer that substantially obviates the problems due to limitations and disadvantages of the conventional display panel.FIGS. 6A-6Billustrate a process of repairing an electrical short circuit between a data line and a common electrode layer in a display panel. In some embodiments. Referring toFIG. 6A, the portion of the common electrode layer206in contact with the conductive component209is a connection C as shown inFIG. 3A. As discussed above in connection withFIG. 3A, the connection. C includes a first portion C1in the first area. A and a second portion. C2in the second area B. The conductive component209inFIG. 6Ais in contact with the passivation layer204. As shown inFIG. 6A, the contacting portion of the passivation layer204is damaged, resulting in an electrical short circuit between the data line106and the common electrode layer206.

Referring toFIG. 6B, the portion of the common electrode layer206(corresponding to the connection C inFIG. 3A) in contact with the conductive component209is cut at both sides (e.g., a first side in the first area A and a second side in the second area B). After the portion of the common electrode layer206is cut, it is insulated from the rest of the common electrode layer206. The cut portion corresponds to the insulated island inFIG. 3Bafter the connection CFIG. 3Abeing cut at both the first portion C1in the first area A and the second portion C2in the second area B. Once the portion is insulated from the rest of the common electrode layer206, the electrical short circuit is removed.

In some embodiments, the step of insulating the connection from the common electrode layer is performed by laser cutting the connection at both the first side and the second side. Various alternative embodiments may be practiced to perform the step of insulating.

Accordingly, the present disclosure in another aspect provides a display panel repaired by a repairing method described herein throughout. In some embodiments, the display panel includes an array substrate and an opposing substrate facing the array substrate; a data line layer having a plurality of data lines on the array substrate; a passivation layer on a side of the data line layer proximal to the opposing substrate; a sealant layer on a side of the passivation layer distal to the data line layer, sealing the array substrate and the opposing substrate together; the display panel having a first area enclosed by the sealant layer and a second area outside of the first area and the sealant layer; the plurality of data lines extending from the first area into the second area; and a common electrode layer an a side of the sealant layer distal to the passivation layer. The common electrode layer in the repaired display panel includes a portion having a plurality of connections, at least one insulated island, and a plurality of slits spaced apart from each other by the plurality of connections and the at least one insulated island. Optionally, the plurality of slits, the plurality of connections, and the at least one insulated island extend from the first area into the second area. Each of the plurality of connections is between two adjacent slits. Each of the at least one insulated island is between two adjacent slits. Each of the plurality of connections has a first portion in the first area and a second portion in the second area. Each of the at least one insulated island has a first portion in the first area and a second portion in the second area. Each of the at least one insulated island is insulated from the rest of the common electrode layer by two adjacent slits, a first gap in the first area, and a second gap in the second area. The two adjacent slits, the first gap and the second gap surround a complete periphery of the insulated island.

In another aspect, the present disclosure provides a method of fabricating a display panel, in some embodiments, the method includes forming an opposing substrate on a first base substrate; forming an array substrate on a second base substrate; and sealing the opposing substrate and the array substrate by a sealant layer thereby forming the display panel having a first area enclosed by the sealant layer and a second area outside of the first area and the sealant layer.

In some embodiments, the step of forming the opposing substrate includes forming a common electrode layer on the first base substrate. Optionally, the step of forming the opposing substrate further includes forming a black matrix layer on the first base substrate. The common electrode layer is then formed on a side of the black matrix layer distal to the first base substrate.

In some embodiments, the step of forming the common electrode layer includes forming a slit area in the common electrode layer. The slit area so formed includes a plurality of connections, and a plurality of slits spaced apart by the plurality of connections. The plurality of slits and the plurality of connections extend from the first area into the second area. Each of the plurality of connections is disposed between two adjacent slits. Each of the plurality of connections is formed to have a first side in the first area and a second side in the second area.

In some embodiments, the step of sealing the opposing substrate and the array substrate by the sealant layer includes forming a sealant layer comprising a plurality of conductive components. Optionally, the method further includes electrically connecting the common electrode layer and the common electrode signal line layer by the plurality of conductive components in the sealant layer.

The conductive components may be made of various appropriate materials. Examples of conductive components include, but are not limited to, metal balls such as gold balls or nickel balls. In some examples, the conductive components are made of elastic resin particles coated with metals such as gold or nickel. Optionally, the conductive components have a size in the range of approximately 1 μm to approximately 500 μm.

In some embodiments, the step of forming the array substrate includes forming a data line layer having a plurality of data lines on the second base substrate; and forming a passivation layer on a side of the date line layer distal to the second base substrate. Optionally, the step of forming the array substrate further includes forming a common electrode signal line layer on the second base substrate. Optionally, the step of forming the array substrate further includes forming an insulating layer on a side of the common electrode signal line layer proximal to the sealant layer; forming a conductive layer on a side of the insulating layer distal to the common electrode signal line layer forming a via extending through the insulating layer; electrically connecting the conductive layer and the common electrode signal line layer through the via; and electrically connecting the common electrode layer and the conductive layer by the plurality of conductive components.

Optionally, the data line layer is formed so that the plurality of data lines extending front the first area into the second area through an area substantially corresponding to the slit area in plan view of the display panel.

Optionally, the data line layer and the common electrode layer are so formed that each of the plurality of connections corresponds to one or more data line. Optionally, a projection of each of the plurality of connections overlaps a projection of one or more data line in plan view of the display panel. Optionally, the data line layer and the common electrode layer are so formed that each of the plurality of connections corresponds to a single data line. Optionally, a projection of each of the plurality of connections overlaps a projection of a single data line plan view of the display panel. Optionally, a projection of substantially all data lines on the array substrate overlaps with that of substantially all connection in plan view of the display panel.

In some embodiments, the display panel is of an advanced super dimensional switching (ADS) type, an in-plane switching (IPS) type, a twist nematic (TN) type, or a vertical align (VA) type. Optionally, the display panel is a TN-type display panel.

In another aspect, the present disclosure provides a novel opposing substrate. In some embodiments, the opposing substrate includes a base substrate and a common electrode layer on the base substrate having a portion in a peripheral area of the opposing substrate, the portion including a plurality of connections, and a plurality of slits spaced apart from each other by the plurality of connections. Each of the plurality of connections is arranged between two adjacent slits. Optionally, the opposing substrate further includes a black matrix layer between the base substrate and the common electrode layer, e.g., on a side of the common electrode layer proximal to the base substrate.

As used herein the term “peripheral area” refers to an area of a display substrate (e.g., an opposing substrate or an array substrate) in a display panel where various circuits and wires are provided to transmit signals to the display substrate. To increase the transparency of the display apparatus, non-transparent or opaque components of the display apparatus (e.g., battery, printed circuit board, metal frame), can be disposed in the peripheral area rather than in the display areas. As used herein, the term “display area” refers to an area of a display substrate (e.g., an opposing substrate or an array substrate) in a display panel where image is actually displayed. Optionally, the display area may include both a subpixel region and an inter-subpixel region. A subpixel region refers to alight emission region of a subpixel, such as a region corresponding to a pixel electrode in a liquid crystal display or a region corresponding to a light emissive layer in an organic light emitting display. An inter-subpixel region refers to a region between adjacent subpixel regions, such as a region corresponding to a black matrix in a liquid crystal display or a region corresponding a pixel definition layer in an organic light emitting display. Optionally, the inter-subpixel region is a region between adjacent subpixel regions in a same pixel. Optionally, the inter-subpixel region is a region between two adjacent subpixel regions from two adjacent pixels.

In another aspect, the present disclosure provides a display apparatus having a display substrate described herein or fabricated by a method described herein. Examples of appropriate display apparatuses include, but are not limited to, a liquid crystal display panel, an electronic paper, an organic light emitting display panel, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital album, a OPS, etc.