Image sensor and method of fabricating the same

An image sensor includes a substrate including a plurality of pixel regions, and a deep isolation pattern in the substrate between the pixel regions. The deep isolation pattern includes a semiconductor pattern penetrating at least a portion of the substrate, and a dielectric pattern disposed between the substrate and the semiconductor pattern. The dielectric pattern includes a first part disposed adjacent to the semiconductor pattern, and a second part disposed between the substrate and the first part. The semiconductor pattern includes a first semiconductor pattern and a second semiconductor pattern. The first semiconductor pattern is disposed between the dielectric pattern and the second semiconductor pattern. The first part of the dielectric pattern includes a material different from a material of the second part of the dielectric pattern. A thickness of the first part of the dielectric pattern is less than a thickness of the second part of the dielectric pattern.

CROSS-REFERENCE TO RELATED APPLICATIONS

This U.S. nonprovisional application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2020-0112900, filed on Sep. 4, 2020 in the Korean Intellectual Property Office, the disclosure of which is hereby incorporated by reference in its entirety.

TECHNICAL FIELD

Embodiments of the present inventive concept relate to an image sensor and a method of fabricating the same, and more particularly, to a complementary metal oxide semiconductor (CMOS) image sensor and a method of fabricating the same.

DISCUSSION OF RELATED ART

An image sensor is a semiconductor device that transforms optical images into electrical signals. Recent advances in computer and communication industries have led to strong demands in high performances image sensors in various consumer electronic devices such as, for example, digital cameras, camcorders, personal communication systems (PCSs), game devices, security cameras, medical micro cameras, etc. An image sensor may be classified as a charge coupled device (CCD) type or a complementary metal oxide semiconductor (CMOS) type. A CMOS type image sensor may be referred to as a CMOS image sensor (CIS). A CIS has a plurality of two-dimensionally arranged pixels, each of which includes a photodiode. The photodiode serves to transform an incident light into an electrical signal. The pixels may be defined by a deep isolation pattern disposed therebetween.

SUMMARY

Embodiments of the present inventive concept provide an image sensor having a reduced number of defects, and a method of fabricating the same.

Embodiments of the present inventive concept provide a highly-integrated image sensor, and a method of fabricating the same.

According to embodiments of the present inventive concept, an image sensor includes a substrate including a plurality of pixel regions, and a deep isolation pattern in the substrate between the pixel regions. The deep isolation pattern includes a semiconductor pattern penetrating at least a portion of the substrate, and a dielectric pattern disposed between the substrate and the semiconductor pattern. The dielectric pattern includes a first part disposed adjacent to the semiconductor pattern, and a second part disposed between the substrate and the first part. The semiconductor pattern includes a first semiconductor pattern and a second semiconductor pattern. The first semiconductor pattern is disposed between the dielectric pattern and the second semiconductor pattern. The first part of the dielectric pattern includes a material different from a material of the second part of the dielectric pattern. A thickness of the first part of the dielectric pattern is less than a thickness of the second part of the dielectric pattern.

According to embodiments of the present inventive concept, an image sensor includes a substrate that includes a plurality of pixel regions, and a deep isolation pattern disposed in the substrate between the plurality of pixel regions. The deep isolation pattern includes a semiconductor pattern disposed between the plurality of pixel regions, a buried dielectric pattern disposed on the semiconductor pattern, and a dielectric pattern disposed between the semiconductor pattern and each of the plurality of pixel regions, the dielectric pattern extending onto a lateral surface of the buried dielectric pattern. The dielectric pattern includes a first part disposed adjacent to a lateral surface of the semiconductor pattern and the lateral surface of the buried dielectric pattern, and a second part disposed between the first part of the dielectric pattern and each of the plurality of pixel regions. The first part of the dielectric pattern includes a material different from a material of the second part of the dielectric pattern, and a thickness of the first part of the dielectric pattern is less than a thickness of the second part of the dielectric pattern.

According to embodiments of the present inventive concept, a method of fabricating an image sensor includes forming, in a substrate, a trench that defines a plurality of pixel regions, forming, on the substrate, a dielectric layer that fills a portion of the trench, nitriding a surface of the dielectric layer by performing a nitridation process, and forming a semiconductor pattern that fills the trench. The nitridation process causes the dielectric layer to separate into a first part and a second part that include different materials from each other. The first part of the dielectric layer includes one or more of a nitride and an oxynitride.

DETAILED DESCRIPTION

Embodiments of the present inventive concept will be described more fully hereinafter with reference to the accompanying drawings. Like reference numerals may refer to like elements throughout the accompanying drawings.

Herein, when elements are described as being substantially coplanar with one another, it is to be understood that elements are exactly coplanar with one another, or almost coplanar with one another (e.g., within a measurement error), as would be understood by a person having ordinary skill in the art. Further, when one value is described as being about the same as or about equal to another value, it is to be understood that the values are equal to each other to within a measurement error, or if measurably unequal, are close enough in value to be functionally equal to each other as would be understood by a person having ordinary skill in the art. It will be further understood that when two components or directions are described as extending substantially parallel or perpendicular to each other, the two components or directions extend exactly parallel or perpendicular to each other, or extend approximately parallel or perpendicular to each other as would be understood by a person having ordinary skill in the art (e.g., within a measurement error). Other uses of the terms “substantially” and “about” should be interpreted in a like fashion.

It will be understood that when a component such as a film, a region, a layer, or an element, is referred to as being “on”, “connected to”, “coupled to”, or “adjacent to” another component, it can be directly on, connected, coupled, or adjacent to the other component, or intervening components may be present. It will also be understood that when a component is referred to as being “between” two components, it can be the only component between the two components, or one or more intervening components may also be present. It will also be understood that when a component is referred to as “covering” another component, it can be the only component covering the other component, or one or more intervening components may also be covering the other component. Other words used to describe the relationships between components should be interpreted in a like fashion.

FIG.1illustrates a block diagram showing an image sensor according to embodiments of the present inventive concept.

Referring toFIG.1, an image sensor may include an active pixel sensor array1, a row decoder2(also referred to as a row decoder circuit), a row driver3(also referred to as a row driver circuit), a column decoder4(also referred to as a column decoder circuit), a timing generator5(also referred to as a timing generator circuit), a correlated double sampler (CDS)6(also referred to as a CDS circuit), an analog-to-digital converter (ADC)7(also referred to as an ADC circuit), and an input/output (I/O) buffer8(also referred to as an I/O buffer circuit).

The active pixel sensor array1may include a plurality of two-dimensionally arranged pixels, each of which is configured to convert optical signals into electrical signals. The active pixel sensor array1may be driven by a plurality of driving signals such as, for example, a pixel select signal, a reset signal, and a charge transfer signal received from the row driver3. In addition, the correlated double sampler6may be provided with the electrical signals that are converted by the active pixel sensor array1.

The row driver3may provide the active pixel sensor array1with several driving signals for driving the plurality of pixels in accordance with a decoded result obtained from the row decoder2. In a case in which the plurality of pixels is arranged in a matrix shape, the driving signals may be provided for respective rows.

The timing generator5may provide timing and control signals to the row decoder2and the column decoder4.

The correlated double sampler6may receive the electrical signals generated from the active pixel sensor array1, and may hold and sample the received electrical signals. The correlated double sampler6may perform a double sampling operation to sample a specific noise level and a signal level of the electrical signal, and then output a difference level corresponding to a difference between the noise and signal levels.

The analog-to-digital converter7may convert analog signals, which correspond to the difference level received from the correlated double sampler6, into digital signals, and then output the converted digital signals.

The input/output buffer8may latch the digital signals and then sequentially output the latched digital signals to an image signal processing unit in response to the decoded result obtained from the column decoder4.

FIG.2illustrates a circuit diagram showing an active pixel sensor array of an image sensor according to embodiments of the present inventive concept.

Referring toFIGS.1and2, the active pixel sensor array1may include a plurality of pixels PX, which may be arranged in a matrix shape. Each of the pixels PX may include a transfer transistor TX and logic transistors RX, SX, and DX. The logic transistors RX, SX, and DX may include a reset transistor RX, a select transistor SX, and a drive transistor DX. The transfer transistor TX, the reset transistor RX, and the select transistor SX may respectively include a transfer gate TG, a reset gate RG, and a select gate SG. Each of the pixels PX may further include a photoelectric conversion element PD and a floating diffusion region FD.

The photoelectric conversion element PD may create and accumulate photo-charges in proportion to an amount of externally incident light. The photoelectric conversion element PD may be, for example, a photodiode including a P-type impurity region and an N-type impurity region. The transfer transistor TX may transfer charges generated in the photoelectric conversion element PD into the floating diffusion region FD. The floating diffusion region FD may accumulatively store the charges generated and transferred from the photoelectric conversion element PD. The drive transistor DX may be controlled by an amount of photo-charges accumulated in the floating diffusion region FD.

The reset transistor RX may periodically reset the charges accumulated in the floating diffusion region FD. The reset transistor RX may have a drain electrode connected to the floating diffusion region FD and a source electrode connected to a power voltage VDD. When the reset transistor RX is turned on, the floating diffusion region FD may be supplied with the power voltage VDDconnected to the source electrode of the reset transistor RX. Accordingly, when the reset transistor RX is turned on, the charges accumulated in the floating diffusion region FD may be exhausted, and thus, the floating diffusion region FD may be reset.

The drive transistor DX may serve as a source follower buffer amplifier. The drive transistor DX may amplify a variation in electrical potential of the floating diffusion region HD and may output the amplified electrical potential to an output line VOUT.

The select transistor SX may select each row of the pixels P to be read out. When the select transistor SX is turned on, the power voltage VDDmay be applied to a drain electrode of the drive transistor DX.

FIG.2depicts, by way of example, a unit pixel PX that includes one photoelectric conversion element PD and four transistors TX, RX, DX, and SX. However, the image sensor according to embodiments of the present inventive concept is not limited thereto. For example, according to embodiments of the inventive concept, neighboring pixels PX may share the reset transistor RX, the drive transistor DX, or the select transistor SX. Thus, according to embodiments, integration of the image sensor may be increased.

FIG.3illustrates a plan view showing an image sensor according to embodiments of the present inventive concept.FIG.4illustrates a cross-sectional view taken along line I-I′ ofFIG.3according to embodiments of the present inventive concept.FIG.5Aillustrates an enlarged view showing section A ofFIG.4according to embodiments of the present inventive concept.FIG.5Billustrates a graph showing how nitrogen concentration changes in a dielectric pattern ofFIG.5Aaccording to embodiments of the present inventive concept.

Referring toFIGS.3and4, an image sensor may include a photoelectric conversion layer10, a wiring layer20, and an optical transmittance layer30. The photoelectric conversion layer10may be disposed between the wiring layer20and the optical transmittance layer30.

The photoelectric conversion layer10may include, for example, a substrate100, which may include a plurality of pixel regions PXR. The substrate100may be a semiconductor substrate such as, for example, a silicon substrate, a germanium substrate, a silicon-germanium substrate, a II-VI group compound semiconductor substrate, or a III-V group compound semiconductor substrate, or a silicon-on-insulator (SOI) substrate. The substrate100may have a first surface100aand a second surface100bthat are opposite to each other. The plurality of pixel regions PXR may be two-dimensionally arranged along a first direction D1and a second direction D2that are substantially parallel to the second surface100bof the substrate100. The first direction D1and the second direction D2may intersect each other.

The photoelectric conversion layer10may further include a deep isolation pattern150disposed in the substrate100between the plurality of pixel regions PXR. When viewed in a plan view, the deep isolation pattern150may have a grid structure that surrounds each of the plurality of pixel regions PXR. The deep isolation pattern150may penetrate at least a portion of the substrate100along a third direction D3substantially perpendicular to the second surface100bof the substrate100. According to embodiments, the deep isolation pattern150may extend from the first surface100atoward the second surface100bof the substrate100, and may have a bottom surface150B substantially coplanar with the second surface100bof the substrate100. For example, the bottom surface150B of the deep isolation pattern150and the second surface100bof the substrate100may be located at substantially the same level. For example, according to embodiments, the deep isolation pattern150may fully extend through the substrate100from the first surface100aof the substrate100to the second surface100bof the substrate100. The deep isolation pattern150may prevent or reduce cross-talk between neighboring pixel regions PXR.

Referring toFIGS.4and5A, the deep isolation pattern150may include a semiconductor pattern SP that penetrates at least a portion of the substrate100, and a dielectric pattern IP disposed between the semiconductor pattern SP and the substrate100. The semiconductor pattern SP may be disposed between the plurality of pixel regions PXR, and the dielectric pattern IP may be interposed between the semiconductor pattern SP and each of the plurality of pixel regions PXR. According to embodiments, the semiconductor pattern SP and the dielectric pattern IP may have bottom surfaces, each of which may correspond to the bottom surface150B of the deep isolation pattern150, and each of which may be substantially coplanar with the second surface100bof the substrate100. According to embodiments, the deep isolation pattern150may further include a buried dielectric pattern159on the semiconductor pattern SP. The dielectric pattern IP may extend from a lateral surface of the semiconductor pattern SP toward a lateral surface of the buried dielectric pattern159.

The semiconductor pattern SP may include a first semiconductor pattern155adjacent to the dielectric pattern IP and a second semiconductor pattern157disposed on the dielectric pattern IP across the first semiconductor pattern155. The second semiconductor pattern157may cover an uppermost surface of the first semiconductor pattern155and may contact the dielectric pattern IP. The buried dielectric pattern159may be disposed on the second semiconductor pattern157. The second semiconductor pattern157may extend between the first semiconductor pattern155and the buried dielectric pattern159, thereby contacting the dielectric pattern IP. Each of the first and second semiconductor patterns155and157may include a semiconductor material doped with impurities. The impurities may have, for example, P-type or N-type conductivity. For example, each of the first and second semiconductor patterns155and157may include polycrystalline silicon doped with boron.

The dielectric pattern IP may include a first part153adjacent (e.g., directly adjacent) to the semiconductor pattern SP and a second part151adjacent (e.g., directly adjacent) to the substrate100. The first part153of the dielectric pattern IP may be adjacent (e.g., directly adjacent) to the lateral surface of the semiconductor pattern SP and the lateral surface of the buried dielectric pattern159. The second part151of the dielectric pattern IP may be separated across the first part153from the lateral surface of the semiconductor pattern SP and the lateral surface of the buried dielectric pattern159, and may be adjacent (e.g., directly adjacent) to each of the plurality of pixel regions PXR. The first semiconductor pattern155may be adjacent (e.g., directly adjacent) to the first part153of the dielectric pattern IP. The second semiconductor pattern157may cover the uppermost surface of the first semiconductor pattern155and may contact the first part153of the dielectric pattern IP. The buried dielectric pattern159may contact the first part153of the dielectric pattern IP. For example, according to embodiments, the first part153of the dielectric pattern IP may be disposed adjacent to the semiconductor pattern SP, and the second part151of the dielectric pattern IP may be disposed between the substrate100and the first part153of the dielectric pattern IP. Further, the first semiconductor pattern155may be disposed between the dielectric pattern IP and the second semiconductor pattern157.

The first part153of the dielectric pattern IP may include a different material from that of the second part151of the dielectric pattern IP. For example, according to embodiments, the first part153of the dielectric pattern IP may include one or more of a nitride and an oxynitride, and the second part151of the dielectric pattern IP may include an oxide. For example, according to embodiments, the first part153of the dielectric pattern IP may include one or more of silicon nitride and silicon oxynitride, and the second part151of the dielectric pattern IP may include silicon oxide. According to embodiments, the first part153and the second part151do not include a same material. According to embodiments, the first part153of the dielectric pattern IP may include a nitrogen element, and the second part151of the dielectric pattern IP does not include a nitrogen element (e.g., the second part151of the dielectric pattern IP is free of a nitrogen element).

The dielectric pattern IP may have a thickness in a direction (e.g., the second direction D2) substantially parallel to the second surface100bof the substrate100. The second part151of the dielectric pattern IP may have a thickness151T that is measured in the second direction D2from an inner lateral surface of the substrate100, and the first part153of the dielectric pattern IP may have a thickness153T that is measured in the second direction D2from a boundary between the first part153and the second part151. The thickness153T of the first part153of the dielectric pattern IP may be less than the thickness151T of the second part151of the dielectric pattern IP. A total thickness151T and153T of the dielectric pattern IP may range from about 30 Å to about 350 Å. The thickness153T of the first part153of the dielectric pattern IP may be, for example, about 2% to about 10% of the total thickness151T and153T of the dielectric pattern IP. For example, the total thickness151T and153T of the dielectric pattern IP may be about 180 Å, and the thickness153T of the first part153of the dielectric pattern IP may be about 10 Å.

Referring toFIGS.5A and5B, the first part153of the dielectric pattern IP may have a first lateral surface S1adjacent to the semiconductor pattern SP and a second lateral surface S2adjacent to the second part151of the dielectric pattern IP. The semiconductor pattern SP and the buried dielectric pattern159may contact the first lateral surface S1of the first part153of the dielectric pattern IP. The first part153of the dielectric pattern IP may have a nitrogen concentration that decreases in a direction from the first lateral surface S1toward the second lateral surface S2. The nitrogen concentration in the first part153of the dielectric pattern IP may be at its highest value at a region adjacent to (or in contact with) the first lateral surface S1.

Referring back toFIGS.3and4, each of the plurality of pixel regions PXR may include a photoelectric conversion region110and a doped region120that extends along a lateral surface of the deep isolation pattern150. The doped region120may be disposed between the photoelectric conversion region110and the deep isolation pattern150.

The substrate100may have a first conductivity type, and the photoelectric conversion region110may be an area doped with impurities having a second conductivity type different from the first conductivity type. For example, the first conductivity type and the second conductivity type may be a P-type and an N-type conductivity type, respectively. In this case, the impurities having the second conductivity type may include N-type impurities, such as one or more of, for example, phosphorus, arsenic, bismuth, and antimony. The photoelectric conversion region110and the substrate100may form a PN junction to constitute a photodiode. The doped region120may be an area doped with impurities having the first conductivity type. The doped region120may prevent the photoelectric conversion region110from receiving electrons that have been trapped in dangling bonds that may be present on a lateral surface of each of the plurality of pixel regions PXR, or may reduce the receiving of such electrons, and thus, the dark current of the image sensor may be improved, and the formation of a white spot(s) may be prevented or reduced. The impurities having the first conductivity type may include P-type impurities, such as, for example, boron. According to embodiments, the semiconductor pattern SP of the deep isolation pattern150may include a semiconductor material doped with impurities having the first conductivity type (e.g., P-type).

A shallow isolation pattern103may be disposed adjacent to the first surface100aof the substrate100. Each of the plurality of pixel regions PXR may include active regions ACT defined by the shallow isolation pattern103. The shallow isolation pattern103may include one or more of, for example, a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer.

Referring back toFIGS.4and5A, the deep isolation pattern150may penetrate the shallow isolation pattern103and may penetrate and extend into the substrate100. The buried dielectric pattern159of the deep isolation pattern150may be disposed in the shallow isolation pattern103. The buried dielectric pattern159may penetrate the shallow isolation pattern103and may contact the semiconductor pattern SP. The dielectric pattern IP of the deep isolation pattern150may extend between the shallow isolation pattern103and the buried dielectric pattern159. The first part153of the dielectric pattern IP may be adjacent to (or in contact with) the buried dielectric pattern159, and the second part151of the dielectric pattern IP may be adjacent to (or in contact with) the shallow isolation pattern103.

The shallow isolation pattern103may be disposed in a first trench TR1that extends into the substrate100from the first surface100aof the substrate100. The deep isolation pattern150may be disposed in a second trench TR2that penetrates the shallow isolation pattern103and extends toward the second surface100bof the substrate100. Each of the first and second trenches TR1and TR2may have a width in a direction (e.g., the second direction D2) substantially parallel to the second surface100bof the substrate100. A width of a bottom surface TR1_B of the first trench TR1may be greater than a width of an upper portion of the second trench TR2. The dielectric pattern IP of the deep isolation pattern150may partially cover the bottom surface TR1_B of the first trench TR1.

Referring back toFIGS.3and4, the transfer transistors TX and the logic transistors RX, SX, and DX ofFIG.2may be disposed on the first surface100aof the substrate100. Each of the transistors TX, RX, SX, and DX may be disposed on the active region ACT that corresponds to the pixel region PXR.

The transfer transistor TX may include a transfer gate TG and a floating diffusion region FD on a corresponding active region ACT. A lower portion of the transfer gate TG may be inserted into the substrate100, and an upper portion of the transfer gate TG may protrude upwardly from the first surface100aof the substrate100. A gate dielectric layer GI may be interposed between the transfer gate TG and the substrate100. The floating diffusion region FD may be disposed on a corresponding active region ACT on one side of the transfer gate TG. The floating diffusion region FD may be an area doped with impurities having the second conductivity type (e.g., N-type).

The drive transistor DX may include a drive gate SFG on a corresponding active region ACT, and the select transistor SX may include a select gate SG on a corresponding active region ACT. The reset transistor RX may include a reset gate RG on a corresponding active region ACT. An additional gate dielectric layer GI may be interposed between the substrate100and each of the drive, select, and reset gates SFG, SG, and RG.

The wiring layer20may be disposed on the first surface100aof the substrate100. The wiring layer20may include a first interlayer dielectric layer210, a second interlayer dielectric layer220, and a third interlayer dielectric layer230that are sequentially stacked on the first surface100aof the substrate100. The wiring layer20may further include contact plugs BCP in the first interlayer dielectric layer210, first wiring patterns222in the second interlayer dielectric layer220, and second wiring patterns232in the third interlayer dielectric layer230. The first interlayer dielectric layer210may be disposed on the first surface100aof the substrate100and may cover the transistors TX, RX, SX, and DX, and the contact plugs BCP may be connected to terminals of the transistors TX, RX, SX, and DX. The contact plugs BCP may be connected to corresponding ones of the first wiring patterns222, and the first wiring patterns222may be connected to corresponding ones of the second wiring patterns232. The first and second wiring patterns222and232may be electrically connected through the contact plugs BCP to the transistors TX, RX, SX, and DX. Each of the first, second, and third interlayer dielectric layers210,220, and230may include a dielectric material, and the contact plugs BCP, the first wiring patterns222, and the second wiring patterns232may include a conductive material.

The optical transmittance layer30may be disposed on the second surface100bof the substrate100. The optical transmittance layer30may include a color filter array320and a micro-lens array330on the second surface100bof the substrate100. The color filter array320may be disposed between the micro-lens array330and the second surface100bof the substrate100. The optical transmittance layer30may focus and filter externally incident light, and the photoelectric conversion layer10may be provided with the focused and filtered light.

The color filter array320may include a plurality of color filters that is correspondingly disposed on the plurality of pixel regions PXR. The micro-lens array330may include a plurality of micro-lenses that is correspondingly disposed on the plurality of color filters of the color filter array320. Each of the plurality of micro-lenses of the micro-lens array330may vertically overlap (e.g., in the third direction D3) the photoelectric conversion region110of a corresponding pixel region PXR.

An antireflection layer310may be interposed between the color filter array320and the second surface100bof the substrate100. The antireflection layer310may prevent or reduce light reflection such that the photoelectric conversion region110may readily receive light incident onto the second surface100bof the substrate100. A first dielectric layer312may be interposed between the antireflection layer310and the color filter array320, and a second dielectric layer322may be interposed between the color filter array320and the micro-lens array330. A grid315may be interposed between the first dielectric layer312and the color filter array320. The grid315may vertically overlap the deep isolation pattern150. The grid315may allow the photoelectric conversion region110to receive light incident onto the second surface100bof the substrate100. The grid315may include, for example, metal. The color filter array320may extend between neighboring grids315and may contact the first dielectric layer312.

FIGS.6to13illustrate cross-sectional views taken along line I-I′ ofFIG.3, showing a method of fabricating an image sensor according to embodiments of the present inventive concept. For brevity of description, a repetitive explanation of technical aspects and elements of the image sensor described with reference toFIGS.1to5Bmay be omitted.

Referring toFIGS.3and6, the substrate100may be provided which has the first surface100aand the second surface100bthat are opposite to each other. The substrate100may have a first conductivity type (e.g., P-type). The first trench TR1may be formed adjacent to the first surface100aof the substrate100. The formation of the first trench TR1may include forming a first mask pattern M1on the first surface100aof the substrate100, and etching the substrate100by using the first mask pattern M1as an etching mask. The first trench TR1may define the active regions ACT in the substrate100.

Referring toFIGS.3and7, an isolation layer103rmay be formed on the first surface100aof the substrate100. The isolation layer103rmay cover the first mask pattern M1and may fill the first trench TR1. The isolation layer103rmay include, for example, one or more of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer.

The second trench TR2may be formed in the substrate100. The formation of the second trench TR2may include forming, on the isolation layer103r, a second mask pattern that defines a region where the second trench TR2will be formed, and etching the isolation layer103rand the substrate100by using the second mask pattern as an etching mask. The second trench TR2may have a bottom surface TR2_B at a level higher than that of the second surface100bof the substrate100. In this description, the level of the bottom surface TR2_B of the second trench TR2may be a distance measured in the third direction D3from the second surface100bof the substrate100. The second trench TR2may define the plurality of pixel regions PXR in the substrate100. Each of the plurality of pixel regions PXR may include the active regions ACT defined by the first trench TR1.

Referring toFIGS.3and8, a portion of the isolation layer103r, which is exposed to the second trench TR2, may be recessed. Therefore, an upper portion of the second trench TR2may be expanded, and a portion of the bottom surface TR1_B of the first trench TR1may be exposed by the second trench TR2. For example, a wet etching process may be performed to partially recess the isolation layer103r.

Referring toFIGS.3and9, the doped region120may be formed in the substrate100exposed to the second trench TR2. The formation of the doped region120may include, for example, implanting impurities having a first conductivity type (e.g., P-type) into the substrate100exposed to the second trench TR2.

A dielectric layer IPr may be formed on the isolation layer103rand may conformally cover an inner surface of the second trench TR2. The dielectric layer IPr may partially cover the bottom surface TR1_B of the first trench TR1, the bottom surface TR1_B being exposed to the second trench TR2. The dielectric layer IPr may include, for example, an oxide (e.g., silicon oxide).

Referring toFIGS.3and10, a nitridation process may be performed to nitride a surface of the dielectric layer IPr. The nitridation process may include, for example, using ion implantation or plasma treatment to implant nitrogen elements into the surface of the dielectric layer IPr. The nitridation process may cause the dielectric layer IPr to separate into the first part153and the second part151that include different materials from each other. The first part153of the dielectric layer IPr may include, for example, one or more of a nitride and an oxynitride, and the second part151of the dielectric layer IPr may include, for example, an oxide. For example, the first part153of the dielectric layer IPr may include one or more of silicon nitride and silicon oxynitride, and the second part151of the dielectric layer IPr may include silicon oxide. According to embodiments, the first part153of the dielectric layer IPr may include a nitrogen element, and the second part151of the dielectric layer IPr does not include a nitrogen element (e.g., is free of a nitrogen element). As described with reference toFIG.5A, the first part153of the dielectric layer IPr may be formed to have a thickness less than that of the second part151of the dielectric layer IPr. In addition, because the nitridation process is performed by using ion implantation or plasma treatment, as described with reference toFIG.5B, the first part153of the dielectric layer IPr may have a nitrogen concentration that decreases in a direction from a surface S1of the first part153toward the second part151.

Referring toFIGS.3and11, the first semiconductor pattern155may be formed to fill a portion of the second trench TR2. The formation of the first semiconductor pattern155may include, for example, forming, on the dielectric layer IPr, a first semiconductor layer that fills a portion of the second trench TR2, and performing an anisotropic etching process on the first semiconductor layer. The anisotropic etching process may remove the first semiconductor layer from an upper portion of the second trench TR2, thereby exposing the dielectric layer IPr. The first semiconductor pattern155may be locally formed in a lower portion of the second trench TR2that extends into the substrate100. The formation of the first semiconductor pattern155may further include implanting impurities having the first conductivity type (e.g., P-type) into the first semiconductor pattern155. After the formation of the first semiconductor pattern155, a cleaning process may be performed to remove etch byproducts resulting from the anisotropic etching process.

The impurities having the first conductivity type doped into the first semiconductor pattern155may diffuse into the dielectric layer IPr in a subsequent annealing process. In this case, the impurities diffused into the dielectric layer IPr may serve as trap sites, and thus, may contribute to white spots in the image sensor. Moreover, during the cleaning process, the exposed dielectric layer IPr may be partially removed from an upper portion of the second trench TR2, and as a result, a reduction in thickness of the dielectric layer IPr may occur. Such a reduction in thickness of the dielectric layer IPr may induce an increase in electric field applied to the dielectric layer IPr, thereby accelerating formation of the white spots.

According to embodiments of the present inventive concept, the nitrided first part153of the dielectric layer IPr may prevent the impurities having the first conductivity type from diffusing from the first semiconductor pattern155into the second part151of the dielectric layer IPr, or may reduce the diffusion of such impurities. Accordingly, formation of electron trap sites in the dielectric layer IPr may be suppressed. Furthermore, the nitrided first part153may prevent the dielectric layer IPr from undergoing a reduction in thickness in an upper portion of the second trench TR2during the cleaning process, or may reduce such a reduction in thickness. As a result, the image sensor may prevent or reduce the occurrence of a white spot(s).

Referring toFIGS.3and12, the second semiconductor pattern157may be formed to fill a lower portion of the second trench TR2. The formation of the second semiconductor pattern157may include, for example, forming, on the dielectric layer IPr, a second semiconductor layer that fills the second trench TR2, and performing an etch-back process on the second semiconductor layer. The etch-back process may continue until the second semiconductor layer remains locally in a lower portion of the second trench TR2. The second semiconductor pattern157may cover an uppermost surface of the first semiconductor pattern155, and may contact the dielectric layer IPr (or the first part153of the dielectric layer IPr). After the formation of the second semiconductor pattern157, an annealing process may be performed on the substrate100. Therefore, the first conductivity impurities may diffuse into the second semiconductor pattern157from the first semiconductor pattern155. The first semiconductor pattern155and the second semiconductor pattern157may be collectively referred to as a semiconductor pattern SP.

Referring toFIGS.3and13, the buried dielectric pattern159may be formed to fill an upper portion of the second trench TR2. The formation of the buried dielectric pattern159may include, for example, forming, on the substrate100in which the semiconductor pattern SP is formed, a buried dielectric layer that fills a remaining portion of the second trench TR2, and performing a planarization process on the buried dielectric layer, the dielectric layer IPr, and the isolation layer103runtil the first surface100aof the substrate100is exposed. The planarization process may remove the first mask pattern M1. The planarization process may convert the buried dielectric layer, the dielectric layer IPr, and the isolation layer103rinto the buried dielectric pattern159, the dielectric pattern IP, and the shallow isolation pattern103. The buried dielectric pattern159, the dielectric pattern IP, and the semiconductor pattern SP may be collectively referred to as the deep isolation pattern150. The deep isolation pattern150may be interposed between the plurality of pixel regions PXR.

According to embodiments of the present inventive concept, the first part153of the dielectric pattern IP may be formed by implanting nitrogen elements into a surface of the dielectric layer IPr. Compared to a case where an additional dielectric layer is deposited on the dielectric layer IPr, this may facilitate a reduction in size (e.g., a reduction in the width in the second direction D2) of the deep isolation pattern150, and accordingly, an increase in the integration of the plurality of pixel regions PXR may be achieved.

The photoelectric conversion region110may be formed in each of the plurality of pixel regions PXR. The formation of the photoelectric conversion region110may include, for example, implanting the substrate100with impurities having a second conductivity type (e.g., N-type) different from the first conductivity type (e.g., P-type).

A thinning process may be performed on the second surface100bof the substrate100, and the thinning process may partially remove the substrate100and the deep isolation pattern150. The thinning process may include, for example, grinding or polishing the second surface100bof the substrate100, and anisotropically and/or isotropically etching the second surface100bof the substrate100. The thinning process may remove a lower portion of the deep isolation pattern150, and the bottom surface150B of the deep isolation pattern150may be substantially coplanar with the second surface100bof the substrate100.

Transistors TX, RX, SX, and DX may be formed on the first surface100aof the substrate100and on each pixel region PXR. The formation of the transfer transistor TX may include, for example, implanting a corresponding active region ACT with impurities to form a floating diffusion region FD, and forming a transfer gate TG on the corresponding active region ACT. The formation of the drive, select, and reset transistors DX, SX, and RX may include implanting a corresponding active region ACT with impurities to form an impurity region, and forming, on the corresponding active region ACT, a corresponding one of driver, select, and reset gates SFG, SG, and RG.

The process described above may form the photoelectric conversion layer10. The wiring layer20may be formed on the first surface100aof the substrate100. For example, the first interlayer dielectric layer210may be formed on the first surface100aof the substrate100, and may cover the transistors TX, RX, SX, and DX. The contact plugs BCP may be formed in the first interlayer dielectric layer210, and may be connected to terminals of the transistors TX, RX, SX, and DX. The second interlayer dielectric layer220and the third interlayer dielectric layer230may be sequentially formed on the first interlayer dielectric layer210. The first wiring patterns222and the second wiring patterns232may be formed in the second interlayer dielectric layer220and the third interlayer dielectric layer230, respectively. The first and second wiring patterns222and232may be electrically connected through the contact plugs BCP to the transistors TX, RX, SX, and DX.

Referring back toFIGS.3and4, the optical transmittance layer30may be formed on the second surface100bof the substrate100. For example, the antireflection layer310and the first dielectric layer312may be sequentially formed on the second surface100bof the substrate100. The grid315may be formed on the first dielectric layer312, and may vertically overlap the deep isolation pattern150. The formation of the grid315may include, for example, depositing a metal layer on the first dielectric layer312, and patterning the metal layer. The color filter array320may be formed on the first dielectric layer312and may cover the grid315. The color filter array320may include a plurality of color filters, and the plurality of color filters of the color filter array320may be correspondingly disposed on the plurality of pixel regions PXR. The second dielectric layer322may be formed on the color filter array320, and the micro-lens array330may be formed on the second dielectric layer322. The micro-lens array330may include a plurality of micro-lenses that are correspondingly disposed on the plurality of color filters of the color filter array320. Each of the plurality of micro-lenses of the micro-lens array330may be disposed to vertically overlap (e.g., in the third direction D3) the photoelectric conversion region110of a corresponding pixel region PXR.

FIG.14illustrates a cross-sectional view showing an image sensor according to embodiments of the present inventive concept. For brevity, a further description of elements and technical aspects previously described may be omitted, and the following description will focus on differences from the image sensor described with reference toFIGS.1to5B.

Referring toFIG.14, the photoelectric conversion layer10may include a substrate100that includes a plurality of pixel regions PXR, and may also include a deep isolation pattern150disposed in the substrate100between the plurality of pixel regions PXR. According to embodiments, the deep isolation pattern150may extend from a second surface100bof the substrate100toward a first surface100aof the substrate100, and may have a bottom surface150B at a higher level than that of the first surface100aof the substrate100. In this description, the level of the bottom surface150B of the substrate100may be a distance measured from the first surface100aof the substrate100and measured in a direction (e.g., the third direction D3) substantially perpendicular to the first surface100aof the substrate100.

The deep isolation pattern150may include a semiconductor pattern SP that penetrates a portion of the substrate100, and may also include a dielectric pattern IP interposed between the semiconductor pattern SP and the substrate100. The semiconductor pattern SP may be disposed between the plurality of pixel regions PXR, and the dielectric pattern IP may be interposed between the semiconductor pattern SP and each of the plurality of pixel regions PXR. According to embodiments, the dielectric pattern IP may be interposed between each of the plurality of pixel regions PXR and a lateral surface of the semiconductor pattern SP, and may extend between the substrate100and a bottom surface of the semiconductor pattern SP. The dielectric pattern IP may have a bottom surface that corresponds to a bottom surface150B of the deep isolation pattern150and is located at a higher level than that of the first surface100aof the substrate100.

According to embodiments, the uppermost surfaces of the dielectric pattern IP and the semiconductor pattern SP may be substantially coplanar with the second surface100bof the substrate100. For example, the uppermost surfaces of the dielectric pattern IP and the semiconductor pattern SP may be located at substantially the same level as that of the second surface100bof the substrate100. In this description, the level may be a distance measured from the first surface100aof the substrate100and measured in a direction (e.g., the third direction D3) substantially perpendicular to the first surface100aof the substrate100. According to embodiments, differently from that shown, the deep isolation pattern150may further include the buried dielectric pattern159described with reference toFIG.4, and the buried dielectric pattern IP may extend from the lateral surface of the semiconductor pattern SP onto a lateral surface of the buried dielectric pattern159.

The semiconductor pattern SP may include a first semiconductor pattern155adjacent to the dielectric pattern IP and a second semiconductor pattern157disposed on the dielectric pattern IP across the first semiconductor pattern155. The second semiconductor pattern157may cover an uppermost surface of the first semiconductor pattern155and may contact the dielectric pattern IP. The dielectric pattern IP may include a first part153adjacent to the semiconductor pattern SP and a second part151adjacent to the substrate100. According to embodiments, the first part153of the dielectric pattern IP may be adjacent to the lateral and bottom surfaces of the semiconductor pattern SP, and the second part151of the dielectric pattern IP may be spaced apart from the lateral and bottom surfaces of the semiconductor pattern SP across the first part153of the dielectric pattern IP.

Each of the plurality of pixel regions PXR may include a photoelectric conversion region110and a doped region120that extends along a lateral surface of the deep isolation pattern150. The doped region120may be disposed between the photoelectric conversion region110and the deep isolation pattern150. According to embodiments, the doped region120may extend along the bottom surface150B of the deep isolation pattern150.

A shallow isolation pattern103may be disposed adjacent to the first surface100aof the substrate100. According to embodiments, the deep isolation pattern150(or the bottom surface150B thereof) may be spaced apart from the shallow isolation pattern103.

The transfer transistor TX and the logic transistors RX, SX, and DX ofFIG.3may be disposed on the first surface100aof the substrate100. A wiring layer20may be disposed on the first surface100aof the substrate100, and an optical transmittance layer30may be disposed on the second surface100bof the substrate100. Except for the differences described above, an image sensor according to an embodiment described with reference toFIG.14may be substantially the same as the image sensor according to an embodiment described with reference toFIGS.1to5B.

FIG.15illustrates a cross-sectional view showing an image sensor according to embodiments of the present inventive concept. For brevity, a further description of elements and technical aspects previously described may be omitted, and the following description will focus on differences from the image sensor described with reference toFIGS.1to5B.

Referring toFIG.15, the photoelectric conversion layer10may include a substrate100that includes a plurality of pixel regions PXR, and may also include deep isolation patterns150disposed in the substrate100between the plurality of pixel regions PXR. Each of the deep isolation patterns150may include a semiconductor pattern SP that penetrates at least a portion of the substrate100, a dielectric pattern IP interposed between the semiconductor pattern SP and the substrate100, and a buried dielectric pattern159on the semiconductor pattern SP. Each of the deep isolation patterns150may be substantially the same as the deep isolation pattern150described with reference toFIGS.1to5B.

First and second shallow isolation patterns103and105may be disposed adjacent to the first surface100aof the substrate100. Each of the plurality of pixel regions PXR may include active regions ACT defined by the first shallow isolation pattern103, and the second shallow isolation pattern105may be disposed in a corresponding active region ACT. Each of the deep isolation patterns150may penetrate the first shallow isolation pattern103and may penetrate and extend into the substrate100. For example, the buried dielectric pattern159of each of the deep isolation patterns150may be disposed in the first shallow isolation pattern103. The buried dielectric pattern159may penetrate the first shallow isolation pattern103and may contact the semiconductor pattern SP. The dielectric pattern IP of each of the deep isolation patterns150may extend between the first shallow isolation pattern103and the buried dielectric pattern159.

The transfer transistor TX and the logic transistors RX, SX, and DX ofFIG.3may be disposed on the first surface100aof the substrate100. The transfer transistor TX may include a transfer gate TG and a first floating diffusion region FD1on a corresponding active region ACT. The first floating diffusion region FD1may be disposed in the corresponding active region ACT on one side of the transfer gate TG. A second floating diffusion region FD2may be disposed in the corresponding active region ACT, and the second shallow isolation pattern105may be interposed between the first floating diffusion region FD1and the second floating diffusion region FD2. The first and second floating diffusion regions FD1and FD2may be regions doped with impurities having a second conductivity type (e.g., N-type) different from a first conductivity type of the substrate100.

A wiring layer20may be disposed on the first surface100aof the substrate100. The wiring layer20may include a first interlayer dielectric layer210, a second interlayer dielectric layer220, and a third interlayer dielectric layer230that are sequentially stacked on the first surface100aof the substrate100. The wiring layer20may further include first and second contact plugs BCP1and BCP2in the first interlayer dielectric layer210, first wiring patterns222in the second interlayer dielectric layer220, and second wiring patterns232in the third interlayer dielectric layer230. The first contact plugs BCP1may be connected to terminals of the transistors TX, RX, SX, and DX. The semiconductor pattern SP of one deep isolation pattern150may be electrically connected to the second floating diffusion region FD2through the second contact plug BCP2and the first wiring pattern222. The semiconductor pattern SP of another deep isolation pattern150may be electrically separated (or insulated) from the semiconductor pattern SP of one deep isolation patterns150.

Each of the plurality of pixel regions PXR may include a first photoelectric conversion region110a. The first photoelectric conversion region110amay be a region doped with impurities having the second conductivity type (e.g., N-type) different from the first conductivity type of the substrate100. The first photoelectric conversion region110aand the substrate100may form a PN junction to constitute a photodiode.

An optical transmittance layer30may be disposed on the second surface100bof the substrate100. The optical transmittance layer30may include a color filter array320and a micro-lens array330on the second surface100bof the substrate100. The color filter array320may be disposed between the micro-lens array330and the second surface100bof the substrate100. The color filter array320may include a plurality of color filters that are correspondingly disposed on the plurality of pixel regions PXR, and the micro-lens array330may include a plurality of micro-lenses that are correspondingly disposed on the plurality of color filters of the color filter array320.

A first dielectric layer312may be disposed between the color filter array320and the second surface100bof the substrate100. Light-shield patterns314amay be disposed on the first dielectric layer312between the plurality of color filters of the color filter array320. Low-refraction patterns314bmay be disposed between the plurality of color filters of the color filter array320, and may be disposed on corresponding light-shield patterns314a. A third dielectric layer316may be interposed between each of the light-shield patterns314aand each of the low-refraction patterns314b. The third dielectric layer316may extend between the micro-lens array330and each of the plurality of color filters of the color filter array320.

Pixel electrodes350may be correspondingly disposed on the plurality of pixel regions PXR. The pixel electrodes350may be correspondingly disposed on the plurality of color filters of the color filter array320, and the third dielectric layer316may be interposed between the pixel electrodes350and the color filters of the color filter array320. Electrode separation patterns354may be disposed between the pixel electrodes350. A fourth dielectric layer318may be disposed between the third dielectric layer316and the pixel electrodes350, and may extend between the electrode separation patterns354and the low-refraction patterns314b.

A second photoelectric conversion layer110bmay be disposed between the pixel electrodes350and the electrode separation patterns354, and a common electrode356may be disposed on the second photoelectric conversion layer110b. The second photoelectric conversion layer110bmay be disposed between the common electrode356and the pixel electrodes350and between the common electrode356and the electrode separation patterns354. The color filter array320and the micro-lens array330may be provided therebetween with the pixel electrodes350, the electrode separation patterns354, the second photoelectric conversion layer110b, and the common electrode356. The second photoelectric conversion layer110bmay be, for example, an organic photoelectric conversion layer. The second photoelectric conversion layer110bmay include a P-type organic semiconductor material and an N-type organic semiconductor material, which may form a PN junction. Alternatively, the second photoelectric conversion layer110bmay include quantum-dots or chalcogenide. The pixel electrodes350and the common electrode356may include, for example, one or more of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and an organic transparent conductive material.

Each of the pixel electrodes350may be electrically connected to the semiconductor pattern SP of one deep isolation pattern150through a via plug340. The via plug340may be connected to the semiconductor pattern SP of one deep isolation pattern150, and may be connected to a corresponding one of the pixel electrodes350after penetrating the first dielectric layer312, a corresponding light-shield pattern314a, the third dielectric layer316, a corresponding low-refraction pattern314b, and the fourth dielectric layer318. A via barrier layer342may be between the via plug340and each of the first dielectric layer312, the corresponding light-shield pattern314a, the third dielectric layer316, the corresponding low-refraction pattern314b, and the fourth dielectric layer318. The semiconductor pattern SP of one deep isolation pattern150may be electrically connected to the second floating diffusion region FD2through the second contact plug BCP2and the first wiring pattern222.

A second dielectric layer322may be interposed between the common electrode356and the micro-lens array330. The first, second, third, and fourth dielectric layers312,316,318, and322and the electrode separation patterns354may include, for example, one or more of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer.

Except for the differences described above, an image sensor according to an embodiment described with reference toFIG.15may be substantially the same as the image sensor according to an embodiment described with reference toFIGS.1to5B.

FIG.16illustrates a plan view showing an image sensor according to embodiments of the present inventive concept.FIG.17illustrates a cross-sectional view taken along line II-IP ofFIG.16. For brevity, a further description of elements and technical aspects previously described may be omitted, and the following description will focus on differences from the image sensor described with reference toFIGS.1to5B.

Referring toFIGS.16and17, an image sensor may include a substrate100including a pixel array region AR, an optical black region OB, and a pad region PR, a wiring layer20on a first surface100aof the substrate100, a base substrate40on the wiring layer20, and an optical transmittance layer30on a second surface100bof the substrate100. The wiring layer20may be disposed between the base substrate40and the first surface100aof the substrate100. The wiring layer20may include an upper wiring layer21adjacent to the first surface100aof the substrate100, and may also include a lower wiring layer23between the upper wiring layer21and the base substrate40. The pixel array region AR may include a plurality of pixel regions PXR and a deep isolation pattern150disposed between the plurality of pixel regions PXR. The pixel array region AR may be substantially the same as the pixel array region AR described with reference toFIGS.1to5B,14, and15. For example, the deep isolation pattern150may be substantially the same as one of the deep isolation patterns150described with reference toFIGS.1to5B,14, and15.

A first connection structure50, a first contact81, and a bulk color filter90may be disposed on the optical black region OB of the substrate100. The first connection structure50may include a first light-shield pattern51, a first separation pattern53, and a first capping pattern55. The first light-shield pattern51may be disposed on the second surface100bof the substrate100. The first light-shield pattern51may cover the first dielectric layer312, and may conformally cover an inner wall of one of third and fourth trenches TR3and TR4. The first light-shield pattern51may penetrate the photoelectric conversion layer10and the upper wiring layer21. The first light-shield pattern51may be connected to the semiconductor pattern SP of the deep isolation pattern150included in the photoelectric conversion layer10, and may be connected to wiring lines in the upper and lower wiring layers21and23. Therefore, the first connection structure50may electrically connect the photoelectric conversion layer10to the wiring layer20. The first light-shield pattern51may include a metallic material (e.g., tungsten). The first light-shield pattern51may block light incident onto the optical black region OB.

The first contact81may fill a remaining portion the third trench TR3. The first contact81may include a metallic material (e.g., aluminum). The first contact81may be connected to the semiconductor pattern SP of the deep isolation pattern150. A bias may be applied through the first contact81to the semiconductor pattern SP. The first separation pattern53may fill a remaining portion of the fourth trench TR4. The first separation pattern53may penetrate the photoelectric conversion layer10and a portion of the wiring layer20. The first separation pattern53may include a dielectric material. The first capping pattern55may be disposed on the first separation pattern53. The first capping pattern55may include the same material as that of the buried dielectric pattern159shown inFIG.4.

The bulk color filter90may be disposed on the first connection structure50and the first contact81. The bulk color filter90may cover the first connection structure50and the first contact81. A first passivation layer71may lie on and encapsulate the bulk color filter90.

An additional photoelectric conversion region110′ and a dummy region111may each be provided in a corresponding pixel region PXR of the optical black region OB. The additional photoelectric conversion region110′ may be a region doped with impurities having a conductivity type (e.g., N-type) different from a first conductivity type of the substrate100. According to embodiments, the additional photoelectric conversion region110′ may have a structure similar to that of the photoelectric conversion regions110in the plurality of pixel regions PXR of the pixel array region AR, but does not perform the same operation (e.g., reception of light and generation of electrical signals) as that of the photoelectric conversion regions110. According to embodiments, the dummy region111is not doped with impurities.

A second connection structure60, a second contact83, and a second passivation layer73may be disposed in the pad region PR of the substrate100. The second connection structure60may include a second light-shield pattern61, a second separation pattern63, and a second capping pattern65.

The second light-shield pattern61may be disposed on the second surface100bof the substrate100. The second light-shield pattern61may cover the first dielectric layer312, and may conformally cover an inner wall of each of fifth and sixth trenches TR5and TR6. The second light-shield pattern61may penetrate the photoelectric conversion layer10and the upper wiring layer21. The second light-shield pattern61may be connected to wiring lines in the lower wiring layer23. Therefore, the second connection structure60may electrically connect the photoelectric conversion layer10to the wiring layer20. The second light-shield pattern61may include a metallic material (e.g., tungsten). The second light-shield pattern61may block light incident onto the pad region PR.

The second contact83may fill a remaining portion of the fifth trench TR5. The second contact83may include a metallic material (e.g., aluminum). The second contact83may serve as an electrical connection path between the image sensor and an external device. The second separation pattern63may fill a remaining portion of the sixth trench TR6. The second separation pattern63may penetrate the photoelectric conversion layer10and a portion of the wiring layer20. The second separation pattern63may include a dielectric material. The second capping pattern65may be disposed on the second separation pattern63. The second capping pattern65may include the same material as that of the buried dielectric pattern159shown inFIG.4. The second passivation layer73may cover the second connection structure60.

A current applied through the second contact83may flow through the second light-shield pattern61, wiring lines in the wiring layer20, and the first light-shield pattern51to the semiconductor pattern SP of the deep isolation pattern150. Electrical signals generated from the photoelectric conversion regions110in the plurality of pixel regions PXR of the pixel array region AR may be externally transferred through wiring lines in the wiring layer20, the second light-shield pattern61, and the second contact83.

According to embodiments of the present inventive concept, a nitrided first part of a dielectric pattern included in a deep isolation pattern may prevent impurities from diffusing from a semiconductor pattern into a second part of the dielectric pattern, or may reduce such diffusion. Accordingly, the formation of electron trap sites in the dielectric pattern may be suppressed. In addition, the first part may suppress a reduction in thickness of the dielectric pattern during a cleaning process. As a result, an image sensor in which the occurrence of a white spot(s) is prevented or reduced may be provided.

Furthermore, the first part of the dielectric pattern may be formed by performing a nitridation process on a surface of a dielectric layer. Compared to a case in which an additional dielectric layer is deposited, this process may facilitate a reduction in size of the deep isolation pattern, and a highly-integrated image sensor may be provided.