POWER SEMICONDUCTOR DEVICES INCLUDING MULTIPLE GATE BOND PADS

Power semiconductor devices comprise a silicon carbide based semiconductor layer structure including an active region defined therein and a gate bond pad that is on the semiconductor layer structure and vertically overlaps the active region.

FIELD OF THE INVENTION

The present invention relates to power semiconductor devices and, more particularly, to power semiconductor devices including multiple gate bond pads.

BACKGROUND

A wide variety of power semiconductor devices are known in the art including, for example, power Metal Oxide Semiconductor Field Effect Transistors (“MOSFETs”), Insulated Gate Bipolar Transistors (“IGBTs”) and various other devices. These power semiconductor devices are often fabricated from wide bandgap semiconductor materials such as silicon carbide or gallium nitride based materials. Herein, the term “wide bandgap semiconductor” encompasses any semiconductor having a bandgap of at least 1.4 eV. Power semiconductor devices are designed to selectively block or pass large voltages and/or currents. For example, in the blocking state, a power semiconductor device may be designed to sustain hundreds or thousands of volts of electric potential.

Power semiconductor devices such as a power MOSFET can have a lateral structure or a vertical structure. A power MOSFET having a lateral structure has both the source region and the drain region of the MOSFET on the same major surface (i.e., upper or lower) of a semiconductor layer structure of the device. In contrast, a power MOSFET having a vertical structure has its source region on one major surface of the semiconductor layer structure and its drain region on the other (opposed) major surface thereof. Vertical device structures are typically used in very high power applications, as the vertical structure allows for a thick semiconductor drift layer that can support high current densities and block high voltages. Herein, the term “semiconductor layer structure” refers to a structure that includes one or more semiconductor layers such as semiconductor substrates and/or semiconductor epitaxial layers.

A conventional vertical silicon carbide power MOSFET includes a silicon carbide drift region that is formed on a silicon carbide substrate, such as a silicon carbide wafer. The MOSFET has an active region, as well as one or more inactive regions such as a termination region that may surround the active region and/or a gate bond pad region. The active region acts as a main junction for blocking voltage during reverse bias operation and providing current flow during forward bias operation. The power MOSFET typically has a unit cell structure, meaning that the active region includes a large number of individual “unit cell” MOSFETs that are electrically connected in parallel to function as a single power MOSFET. In high power applications, such a device may include thousands or tens of thousands of unit cells. It is generally desirable to maximize the total active area of the power MOSFET, since total active area is directly proportional to current carrying capacity.

Many power semiconductor devices, such as power MOSFETs and IGBTs, have gate structures. These devices can be turned on and off by applying different bias voltages to the gate structures thereof. The gate structure has a distributed gate resistance, which is a function of the length of the electrical path from the gate bond pad (or other gate terminal) to the gate finger of each individual unit cell and the sheet resistance of the materials forming the gate structure. The gate structure may comprise, for example, the gate bond pad, a plurality of gate fingers in the active region of the device, a gate pad, one or more gate buses that extend between the gate pad and the gate fingers.

SUMMARY

Pursuant to embodiments of the present invention, semiconductor devices are provided that comprise a silicon carbide based semiconductor layer structure including an active region defined therein, and a gate bond pad that is on the semiconductor layer structure and vertically overlaps the active region.

In some embodiments, more than half the gate bond pad vertically overlaps the active region.

In some embodiments, the semiconductor devices may also comprise a plurality of source regions in the active region, and a source contact that is electrically connected to the plurality of source regions, wherein the source contact extends underneath the gate bond pad.

The semiconductor devices may further comprise a gate bus that is electrically connected to the gate bond pad, and a dielectric layer that covers the gate bus and the source contact. Further, the semiconductor devices may comprise a source bond pad that is on the source contact and is electrically connected to the source contact through one or more first conductive vias that extend through the dielectric layer and/or a conductive gate connector that is underneath the gate bond pad and is electrically connected to the gate bond pad through a second conductive via that extends through the dielectric layer. Additionally, the semiconductor devices may comprise a gate resistor that electrically connects the conductive gate connector to the gate bus and/or a field oxide layer that is interposed between the conductive gate connector and the semiconductor layer structure.

In some embodiments, the semiconductor devices may also comprise a field oxide layer that is interposed between the gate bus and the semiconductor layer structure.

In some embodiments, the gate bond pad comprises a first gate bond pad, and the semiconductor device further comprises a second gate bond pad that is spaced apart from the first gate bond pad, and the second gate bond pad is on the semiconductor layer structure and vertically overlaps the active region.

The first gate bond pad is adjacent a first side of the semiconductor layer structure, and the second gate bond pad is adjacent a second side of the semiconductor layer structure. The first side is opposite the second side when the semiconductor device is viewed from above. In some embodiments, the first gate bond pad and the second gate bond pad are each positioned about midway between a third side of the semiconductor layer structure and a fourth side of the semiconductor layer structure, and where the fourth side is opposite the third side when the semiconductor device is viewed from above

In some embodiments, the semiconductor devices may further comprise a third gate bond pad that is positioned between the first gate bond pad and the second gate bond pad.

In some embodiments, the semiconductor devices may further comprise a third gate bond pad and a fourth gate bond pad. The first, second, third and fourth gate bond pads are positioned above respective first, second, third and fourth corner regions of the semiconductor layer structure.

In some embodiments, the semiconductor devices may further comprise a plurality of source regions in the active region, a source contact that is electrically connected to the plurality of source regions, and a gate bus that is electrically connected to the gate bond pad. The gate bus comprises a gate bus connector that vertically overlaps the source contact.

In some embodiments, the semiconductor devices may further comprise a gate electrode extending on the semiconductor layer structure. The gate bus further comprises a conductive gate bus plug that protrudes from the gate bus connector of the gate bus toward the semiconductor layer structure and contacts the gate electrode.

In some embodiments, the gate bus connector comprises a first gate bus connector, and the gate bus further comprises a second gate bus connector. The first gate bus connector extends longitudinally in a first horizontal direction that is parallel to an upper surface of the semiconductor layer structure, and the second gate bus connector protrudes from the first gate bus connector and extends longitudinally in a second horizontal direction that is parallel to the upper surface of the semiconductor layer structure and is different from the first horizontal direction.

The semiconductor devices may further comprise first and second gate electrodes that are on the semiconductor layer structure and extend longitudinally in the first horizontal direction, The gate bus further comprises a first conductive gate bus plug and a second conductive gate bus plug, the first conductive gate bus plug protrudes from the first gate bus connector toward the first gate electrode and contacts the first gate electrode, and the second conductive gate bus plug extends from the second gate bus connector toward the second gate electrode and contacts the second gate electrode. Additionally, the semiconductor devices may comprise first and second field oxide layers, wherein the first and second conductive gate bus plugs vertically overlaps the first and second field oxide layers, respectively.

In some embodiments, the semiconductor devices may also comprise a gate electrode that is on the semiconductor layer structure and extends longitudinally in a first horizontal direction that is parallel to an upper surface of the semiconductor layer structure, and a gate resistor that is electrically connected to the gate bond pad and extends from the gate electrode in a second horizontal direction that is parallel to the upper surface of the semiconductor layer structure and is different from the first horizontal direction.

The semiconductor devices may further comprise a conductive gate connector that is underneath the gate bond pad, is electrically connected to the gate bond pad and contacts the gate resistor.

The gate bond pad comprises a first gate bond pad, and the semiconductor device further comprises a second gate bond pad that is on the semiconductor layer structure, vertically overlaps the active region and is spaced apart from the first gate bond pad in a first horizontal direction that is parallel to an upper surface of the semiconductor layer structure, a first gate resistor that is electrically connected to the first gate bond pad and extends longitudinally in a second horizontal direction that is parallel to the upper surface of the semiconductor layer structure and is different from the first horizontal direction, and a second gate resistor that is electrically connected to the second gate bond pad and extends longitudinally in the second horizontal direction.

The semiconductor devices may further comprise a first conductive gate connector that is underneath the first gate bond pad, is electrically connected to the first gate bond pad and contacts the first gate resistor, and a second conductive gate connector that is underneath the second gate bond pad, is electrically connected to the second gate bond pad and contacts the second gate resistor.

Pursuant to embodiments of the present invention, semiconductor devices are provided that comprise a silicon carbide based semiconductor layer structure, a source bond pad on the semiconductor layer structure, and a plurality of gate bond pads that are on the semiconductor layer structure and are spaced apart from each other.

In some embodiments, the plurality of gate bond pads comprise a first gate bond pad that is adjacent a first side of the semiconductor layer structure and a second gate bond pad that is adjacent a second side of the semiconductor layer structure, and where the second side is opposite the first side

In some embodiments, the first gate bond pad and the second gate bond pad are each positioned about midway between a third side of the semiconductor layer structure and a fourth side of the semiconductor layer structure, where the fourth side is opposite the third side when the semiconductor device is viewed from above.

In some embodiments, the semiconductor devices may also comprise a third gate bond pad that is positioned between the first gate bond pad and the second gate bond pad. The third gate bond pad is positioned above a center of the upper surface of the semiconductor layer structure.

In some embodiments, the semiconductor devices may also comprise a third gate bond pad and a fourth gate bond pad, wherein the first, second, third and fourth gate bond pads are positioned above respective first, second, third and fourth corner regions of the upper surface of the semiconductor layer structure.

In some embodiments, the semiconductor devices may also comprise a gate bus that is electrically connected to the plurality of gate bond pads, and a dielectric layer that covers the gate bus.

In some embodiments, the semiconductor devices may also comprise a plurality of gate bond pads that vertically overlap the plurality of conductive gate connectors, respectively, and a plurality of conductive vias that extend through the dielectric layer, wherein each of the plurality of conductive vias electrically connects a respective one of the plurality of conductive gate connectors to a respective one of the plurality of gate bond pads.

The semiconductor devices may further comprise a plurality of gate bond pads that vertically overlap the plurality of conductive gate connectors, respectively, and a plurality of conductive vias that extend through the dielectric layer, wherein each of the plurality of conductive vias electrically connects a respective one of the plurality of conductive gate connectors to a respective one of the plurality of gate bond pads.

The semiconductor devices may further comprise a plurality of gate bond pads that vertically overlap the plurality of conductive gate connectors, respectively, and a plurality of conductive vias that extend through the dielectric layer, wherein each of the plurality of conductive vias electrically connects a respective one of the plurality of conductive gate connectors to a respective one of the plurality of gate bond pads.

The semiconductor devices may further comprise a plurality of gate resistors, wherein each of the plurality of gate resistor electrically connects a respective one of the plurality of conductive gate connectors to the gate bus.

The semiconductor devices may further comprise a plurality of field oxide layers, wherein each of the plurality of field oxide layers is interposed between the semiconductor layer structure and a respective one of the plurality of conductive gate connectors.

In some embodiments, the semiconductor devices may also comprise a plurality of field oxide layers that is interposed between a respective one of the plurality of gate bond pads and the semiconductor layer structure.

In some embodiments, the semiconductor devices may further comprise a plurality of source regions in the semiconductor layer structure, a source contact that is electrically connected to the plurality of source regions, and a gate bus that is electrically connected to the plurality of gate bond pads. The gate bus comprises a gate bus connector that vertically overlaps the source contact.

The semiconductor devices may further comprise a gate electrode extending on the semiconductor layer structure, wherein the gate bus further comprises a conductive gate bus plug that protrudes from the gate bus connector toward the semiconductor layer structure and contacts the gate electrode.

In some embodiments, the gate bus connector comprises a first gate bus connector, and the gate bus further comprises a second gate bus connector, and the first gate bus connector extends longitudinally in a first horizontal direction that is parallel to an upper surface of the semiconductor layer structure, and the second gate bus connector protrudes from the first gate bus connector and extends longitudinally in a second horizontal direction that is parallel to the upper surface of the semiconductor layer structure and is different from the first horizontal direction.

In some embodiments, the semiconductor devices may further comprise first and second gate electrodes that are on the semiconductor layer structure and extend longitudinally in the first horizontal direction, wherein the gate bus further comprises a first conductive gate bus plug and a second conductive gate bus plug, the first conductive gate bus plug protrudes from the first gate bus connector toward the first gate electrode and contacts the first gate electrode, and the second conductive gate bus plug extends from the second gate bus connector toward the second gate electrode and contacts the second gate electrode. Further, the semiconductor devices may comprise first and second field oxide layers, wherein the first and second conductive gate bus plugs vertically overlaps the first and second field oxide layers, respectively.

In some embodiments, the semiconductor devices may further comprise a plurality of source regions in the semiconductor layer structure, and a source contact that is electrically connected to the plurality of source regions, wherein at least one of the plurality of gate bond pads vertically overlaps the source contact.

Pursuant to embodiments of the present invention, semiconductor devices are provided that comprise a silicon carbide based semiconductor layer structure including an active region defined therein, a plurality of source regions in the active region, a source contact that is electrically connected to the plurality of source regions, a plurality of gate electrodes on the semiconductor layer structure, and a gate bus that is electrically connected to the plurality of gate electrodes. The gate bus comprises a gate bus connector that vertically overlaps the source contact.

In some embodiments, the semiconductor devices may further comprise a dielectric layer that is interposed between the source contact and the gate bus connector. The gate bus may further comprises a conductive gate bus plug that is in the dielectric layer, protrudes from the gate bus connector toward the semiconductor layer structure and contacts one of the plurality of gate electrodes. The conductive gate bus plug is above a center of an upper surface of the semiconductor layer structure. Further, the semiconductor devices may comprise a field oxide layer, wherein the conductive gate bus plug vertically overlaps the field oxide layer.

In some embodiments, the gate bus connector comprises a first gate bus connector, and the gate bus further comprises a second gate bus connector, and the first gate bus connector extends longitudinally in a first horizontal direction that is parallel to an upper surface of the semiconductor layer structure, and the second gate bus connector protrudes from the first gate bus connector and extends longitudinally in a second horizontal direction that is parallel to the upper surface of the semiconductor layer structure and is different from the first horizontal direction.

In some embodiments, the plurality of gate electrodes comprises first and second gate electrodes that are on the semiconductor layer structure and are spaced apart from each other in the second horizontal direction. The gate bus further comprises a first conductive gate bus plug and a second conductive gate bus plug, the first conductive gate bus plug protrudes from the first gate bus connector toward the first gate electrode and contacts the first gate electrode, and the second conductive gate bus plug extends from the second gate bus connector toward the second gate electrode and contacts the second gate electrode.

The semiconductor devices may further comprise first and second field oxide layers, wherein the first and second conductive gate bus plugs vertically overlaps the first and second field oxide layers, respectively.

In some embodiments, the semiconductor devices may further comprise a gate bond pad that is on the semiconductor layer structure and is electrically connected to the gate bus. The gate bond pad vertically overlaps the active region.

The semiconductor devices may further comprise a conductive gate connector, wherein the gate bond pad vertically overlaps the conductive gate connector, and a conductive via that is interposed between the gate bond pad and the conductive gate connector and contacts both the gate bond pad and the conductive gate connector.

The semiconductor devices may further comprise a gate resistor, wherein the gate resistor electrically connects the conductive gate connector to the gate bus.

The semiconductor devices may further comprise a field oxide layer, wherein the field oxide layer is interposed between the semiconductor layer structure and the conductive gate connector.

In some embodiments, the plurality of gate electrodes comprises a first gate electrode, and the gate bus further comprises a conductive gate bus plug. The conductive gate bus plug is electrically connected to the gate bus connector and the first gate electrode, and an upper surface of the gate bus connector is higher than an upper surface of the conductive gate bus plug. The conductive gate bus plug contacts the first gate electrode.

Pursuant to embodiments of the present invention, semiconductor devices are provided that comprise providing a silicon carbide based semiconductor layer structure that includes an active region defined therein and a plurality of source regions in the active region, forming a plurality of gate structures on the semiconductor layer structure, wherein each of the plurality of gate structures comprises a gate electrode and a gate capping layer on the gate electrode, forming a source contact on the plurality of source regions, wherein the source contact is electrically connected to the plurality of source regions, forming a conductive gate connector on a first of the plurality of gate structures, the conductive gate connector electrically connected to the gate electrode of the first of the plurality of gate structures, forming a dielectric layer on the source contact and the conductive gate connector, and forming a source bond pad and a gate bond pad on the dielectric layer, wherein the source bond pad is electrically connected to the source contact, and the gate bond pad is electrically connected to the conductive gate connector.

In some embodiments, the methods may further comprise forming a first conducive via and a second conductive via in the dielectric layer before forming the source bond pad and the gate bond pad. The first conducive via is interposed between the source bond pad and the source contact and contacts both the source bond pad and the source contact, and the second conductive via is interposed between the gate bond pad and the conductive gate connector and contacts both the gate bond pad and the conductive gate connector.

In some embodiments, the methods may further comprise forming a field oxide layer on the semiconductor layer structure before forming the plurality of gate structures. The conductive gate connector vertically overlaps the field oxide layer.

In some embodiments, forming the source contact and the conductive gate connector comprises forming a first metal layer on the plurality of source regions and the plurality of gate structures, and patterning the first metal layer thereby forming the source contact and the conductive gate connector that comprise first and second portions of the first metal layer, respectively.

In some embodiments, patterning the first metal layer further forms a gate bus that comprises a third portion of the first metal layer and is electrically connected to the conductive gate connector.

In some embodiments, the gate bus comprises a conductive gate bus plug, and the method further comprises forming a second metal layer on the dielectric layer, and patterning the second metal layer thereby forming a gate bus connector of the gate bus that comprises a portion of the second metal layer, contacts the conductive gate bus of the gate bus and vertically overlaps the source contact.

In some embodiments, the gate bus connector comprises a first gate bus connector extending a first horizontal direction that is parallel to an upper surface of the semiconductor layer structure, and patterning the second metal layer further forms a second gate bus connector of the gate bus that protrudes from the first gate bus connector and extend in a second horizontal direction that is parallel to the upper surface of the semiconductor layer structure and is different from the first horizontal direction.

In some embodiments, forming the source bond pad and the gate bond pad comprises forming a second metal layer on the dielectric layer, and patterning the second metal layer thereby forming the source bond pad and the gate bond pad that comprise first and second portions of the second metal layer, respectively.

DETAILED DESCRIPTION

It is generally desirable to increase switching speed and reduce power consumption of a power semiconductor device. According to embodiments of the present invention, a power semiconductor device includes multiple gate bond pads to facilitate more efficient propagation of the gate voltage to all regions of the device, which allows faster and more power-efficient switching of the device.

It is also generally desirable to maximize the total area of an active region of a power semiconductor device, since this total area is directly proportional to current carrying capacity. Further, increasing the total area of an active region allows for an increase in current carrying capacity for a given size. Alternatively, increasing the total area of an active region allows for a decrease in size of the device without sacrificing current carrying capacity. In conventional power semiconductor devices, no active area is allowed underneath a gate bond pad, and thus the number of gate bond pads cannot be increased without degrading the current carrying capacity. According to embodiments of the present invention, a power semiconductor device includes gate bond pads, some or all of which include at least a portion vertically overlapping an active region, such that the number of gate bond pads can be increased without significantly reducing the total area of the active region. Herein, a first element (e.g., a gate bond pad) of a semiconductor device “vertically overlaps” a second element (e.g., an active region) of the semiconductor device if an axis that is perpendicular to a major surface of a semiconductor layer structure of the semiconductor device passes through both the first and second elements.

Further, it is generally desirable to reduce gate bus resistance for high speed operation of a power semiconductor device. Gate bus resistance can be reduced by using a wide gate bus but that reduces the total area of an active region, as an area underneath a conventional gate bus cannot be used as an active region. According to embodiments of the present invention, a second metal gate bus is provided above the gate bus and is electrically connected to the gate bus. Accordingly, the composite resistance of the second metal gate bus and the gate bus can be reduced without a wide gate bus.

According to embodiments of the present invention, a semiconductor device may include a silicon carbide based semiconductor layer structure including an active region defined therein and a gate bond pad that is on the semiconductor layer structure and vertically overlapping the active region.

According to embodiments of the present invention, a semiconductor device may include a silicon carbide based semiconductor layer structure, a source bond pad on the semiconductor layer structure, and a plurality of gate bond pads that are on the semiconductor layer structure and are spaced apart from each other.

According to embodiments of the present invention, a semiconductor device may include a silicon carbide based semiconductor layer structure including an active region defined therein, a plurality of source regions in the active region, a source contact that is electrically connected to the source regions, a plurality of gate electrodes on the semiconductor layer structure, and a gate bus that is electrically connected to the gate electrodes. The gate bus may include a gate bus connector that vertically overlaps the source contact.

According to embodiments of the present invention, a method of forming a semiconductor device may include providing a silicon carbide based semiconductor layer structure that includes an active region defined therein and a plurality of source regions in the active region and forming a plurality of gate structures on the semiconductor layer structure. Each of the gate structures may include a gate electrode and a gate capping layer on the gate electrode. The method may also include forming a source contact on the source regions, forming a conductive gate connector on a first of the gate structures, forming a dielectric layer on the source contact and the conductive gate connector, and forming a source bond pad and a gate bond pad on the dielectric layer. The source contact is electrically connected to the source regions, and the conductive gate connector is electrically connected to the gate electrode of the first of the gate structures. The source bond pad is electrically connected to the source contact, and the gate bond pad is electrically connected to the conductive gate connector.

FIGS.1,2and5are plan views of MOSFETs that include a single metal layer according to embodiments of the present invention.FIG.1Ais a cross-sectional view of the MOSFET taken along the line Z-Z inFIG.1.FIGS.3,4,6,7,8and9are cross-sectional views of the MOSFETs inFIGS.1,2and5according to embodiments of the present invention. Specifically,FIG.3is a cross-sectional view taken along the line A-A inFIG.1or the line A′-A′ inFIG.2, andFIG.4is a cross-sectional view taken along the line B-B inFIG.1or the line B′-B′ inFIG.2.FIG.6is a cross-sectional view taken along the line A″-A″ inFIG.5, andFIG.7is a cross-sectional view taken along the line B″-B″ inFIG.5.FIG.8is a cross-sectional view taken along the C-C inFIG.1, the line C′-C′ inFIG.2or the line C″-C″ inFIG.5, andFIG.9is a cross-sectional view taken along the line D-D inFIG.1, the line D′-D′ inFIG.2or the line D″-D″ inFIG.5. The lines A-A, A′-A′, A″-A″, C-C, C′-C′ and C″-C″ pass through a gate electrode (e.g., a gate electrode134inFIG.3), and the lines B-B, B′-B′, B″-B″, D-D, D′-D′ and D″-D″ pass through a source region (e.g., a source region128inFIG.4).

Referring toFIGS.1and1A, the MOSFET1100may include a silicon carbide based semiconductor layer structure120(also referred to as a semiconductor layer structure) including an active region defined therein. An active region of a MOSFET device is a region in which current is conducted when the MOSFET device is in a conduction mode.

The active region may include a plurality of unit cell transistors. The semiconductor layer structure120may be a wide bandgap semiconductor layer structure120(i.e., a semiconductor layer structure120formed of wide bandgap semiconductor materials). The semiconductor layer structure120may include a substrate122, a drift region124, and a well region126. The substrate122may be an n-type silicon carbide semiconductor substrate such as, for example, a single crystal 4H silicon carbide semiconductor substrate that is heavily-doped (e.g., between 1×1018atoms/cm3and 1×1021atoms/cm3) with n-type impurities. The drift region124may be a lightly-doped n-type (n-) silicon carbide drift region provided on an upper surface of the substrate122. The well regions126may be moderately-doped p-type regions formed in upper portions of the n-type drift region124. The semiconductor layer structure120may also include source regions128. The source regions128may be heavily-doped (n+) n-type silicon carbide source regions. The source regions128may be spaced apart from each other in a second direction D2.

The MOSFET1100may also include gate structures160that may be spaced apart from each other in the second direction D2. The gate structures160and the source regions128may be arranged alternately along the second direction D2 as illustrated inFIG.1A. Each of the gate structures160may include a gate insulator132, a gate electrode134, and a gate capping layer150on the gate electrode134. The gate capping layer150may electrically isolate the gate electrode134from other conductive elements. For simplicity of illustration, the gate insulator132may not be shown in various cross-sectional views.

Further, the MOSFET1100may include a source bond pad20on top of the semiconductor layer structure120and multiple gate bond pads10that are on top of the semiconductor layer structure120and are spaced apart from each other. In the MOSFET1100, the source bond pad20may contact the source regions128and may also be referred to as a source contact. A region underneath the source contact20may be an active region of the MOSFET1100.

The MOSFET1100may include four gate bond pads10(i.e., a first gate bond pad, a second gate bond pad, a third gate bond pad and a fourth gate bond pad) that are positioned above respective first, second, third and fourth corner regions of an upper surface (e.g.,120U inFIG.3) of the semiconductor layer structure120.

Referring toFIGS.3,4,8and9, each of the gate electrode134and the source region128may may extend longitudinally in a first direction D1. The first direction D1 may be different from the second direction D2. The semiconductor layer structure120may include an upper surface120U on which the gate electrode134is provided and a lower surface120L that is opposite the upper surface120U. The first direction D1 and the second direction D2 both may be parallel to the upper surface120U of the semiconductor layer structure120and may be first and second horizontal directions, respectively. In some embodiments, the first direction D1 may be perpendicular to the second direction D2. A third direction D3 may be perpendicular to the upper surface120U of the semiconductor layer structure120and may be a vertical direction.

The MOSFET1100may include field oxide layers140. Each of the field oxide layers140may be interposed between the semiconductor layer structure120and a respective one of the gate bond pads10. A gate resistor134R that extends from the gate electrode134may optionally be provided on the field oxide layer140. The gate resistor134R may be interposed between the gate bond pad10and the field oxide layer140. In some embodiments, the gate bond pad10may contact the gate resistor134R such that the gate bond pad10may be electrically connected to the gate resistor134R.

The MOSFET1100may also include a gate bus30that may be electrically connected to the gate bond pads10through the gate resistors134R. In some embodiments, the gate bus30may contact the gate resistor134R such that the gate bus30may be electrically connected to the gate resistor134R. In some embodiments, the field oxide layer140may be interposed between the gate resistor134R and the semiconductor layer structure120.

Further, the MOSFET1100may include a source bond pad20that may be electrically connected to the source regions128. The source bond pad20may contact the source regions128as illustrated inFIG.4. The source bond pad20may vertically overlap the gate electrodes134as illustrated inFIG.1A. The source bond pad20may be electrically isolated from the gate electrode134by the gate capping layer150that is interposed between the source bond pad20and the gate electrode134. A dielectric layer40(e.g., an inter-metal dielectric layer) may be provided for electrical isolation between conductive elements (e.g., the gate bond pad10, the source bond pad20, and the gate bus30). The gate bus30may continuously extend along an outline of the source bond pad20as represented with a dashed line inFIG.1, or may comprise multiple discontinuous segments.

In some embodiments, the gate bond pad10, the source bond pad20and/or the gate bus30may be formed concurrently by the same processes. For example, a conductive layer (e.g., a metal layer) may be formed on the gate structures160and then the conductive layer may be patterned to form the gate bond pad10, the source bond pad20and/or the gate bus30. Accordingly, the gate bond pad10, the source bond pad20and/or the gate bus30may include respective portions of the conductive layer. In some embodiments, upper surfaces of the gate bond pad10and the source bond pad20may be coplanar with each other as illustrated inFIGS.3and4.

Referring toFIGS.8and9, in the area where the gate bond pads10are not provided, the gate resistor134R may be omitted, and the gate bus30may contact the gate electrode134and the field oxide layer140.

Referring toFIGS.2and5, a MOSFET1200inFIG.2and a MOSFET1300are similar to the MOSFET1100inFIG.1with a primary difference being that each of the MOSFETs1200and1300includes different numbers of gate bond pads10at different locations.

Referring toFIGS.2and5, each of the MOSFETs1200and1300may include a first gate bond pad10that is adjacent a first side of the semiconductor layer structure120and a second gate bond pad10that is adjacent a second side of the semiconductor layer structure120. The first side may be opposite the second side. In some embodiments, the first and second gate bond pads10may each be positioned about midway between a third side of the semiconductor layer structure120and a fourth side of the semiconductor layer structure120, where the fourth side is opposite the third side when the MOSFET is viewed from above as illustrated inFIGS.2and5.

The MOSFET1300may further include a third gate bond pad10between the first and second gate bond pads10. In some embodiments, the third gate bond pad10may be positioned above a center of the upper surface120U of the semiconductor layer structure120as illustrated inFIG.5.

FIGS.6and7are cross-section views of the MOSFET1300taken along the lines A″-A″ and B″-B″ inFIG.5. The cross-section views of the MOSFET1300illustrated inFIGS.6and7are similar to the cross-sectional views illustrated inFIGS.3and4with primary differences being that a field oxide layer140, a gate resistor134R and a gate bus30are additionally provided adjacent the third gate bond pad10that is positioned about midway between opposing sides of the upper surface120U of the semiconductor layer structure120, and portions of the source bond pad20are provided on opposing sides of the third gate bond pad10. The field oxide layer140and the gate resistor134R may be provided between the third gate bond pad10and the semiconductor layer structure120, and the gate bus30may be provided on the gate resistor134R and the field oxide layer. In some embodiment, the gate bus30may enclose the third gate bond pad10when the MOSFET is viewed from above.

FIGS.10,11and16are plan views of MOSFETs that include double metal layers according to embodiments of the present invention.FIGS.12,13,14,15,17,18,19and20are cross-sectional views of the MOSFETs illustrated inFIGS.10,11and16according to embodiments of the present invention. Specifically,FIG.12is a cross-sectional view taken along the line E-E inFIG.10or the line E′-E′ inFIG.11,FIG.13is a cross-sectional view taken along the line F-F inFIG.10or the line F′-F′ inFIG.11,FIG.14is a cross-sectional view taken along the line G-G inFIG.10or the line G′-G′ inFIG.11, andFIG.15is a cross-sectional view taken along the line H-H inFIG.10or the line H′-H′ inFIG.11.FIG.17is a cross-sectional view taken along the line E″-E″ inFIG.16, andFIG.18is a cross-sectional view taken along the line F″-F″ inFIG.16.FIG.19is a cross-sectional view taken along the I-I inFIG.10, the line I′-I′ inFIG.11or the line I″-I″ inFIG.16, andFIG.20is a cross-sectional view taken along the J-J inFIG.10, the line J′-J′ inFIG.11or the line J″-J″ inFIG.16. The lines E-E, E′-E′, E″-E″, G-G, G′-G′, I-I, I′-I′, and I″-I″ pass through a gate electrode (e.g., a gate electrode134inFIG.12), and the lines F-F, F′-F′, F″-F″, H-H, H′-H′, J-J, J′-J′, and J″-J″ pass through a source region (e.g., a source region128inFIG.13).

Referring toFIGS.10,12through15,19and20, the MOSFET2100may include a semiconductor layer structure120including an active region defined therein and a gate bond pad that is on top of the semiconductor layer structure120and vertically overlaps the active region. The MOSFET2100may also include double metal layers including a lower metal layer (also referred to as a first metallization layer) and an upper metal layer (also referred to as a second metallization layer). The lower metal layer may include, for example, a source contact220and a gate bus230, and the upper metal layer may include, for example, a gate bond pad410and a source bond pad420. A dielectric layer340(also referred to as a second dielectric layer) may be provided on the lower metal layer. The dielectric layer340may cover the source contact220and the gate bus230. A portion of the semiconductor layer structure120underneath the source contact220may be the active region.

The source contact220is electrically connected to the source regions128and may be provided on the upper surface120U of the semiconductor layer structure120. The source contact220may extend underneath the gate bond pad410, and the gate bond pad410may vertically overlap the source contact220.

The source contact220and the gate bond pad410are provided at different levels from an upper surface120U of the semiconductor layer structure120, and the gate bond pad410may vertically overlap an active region. In some embodiments, more than half the gate bond pad410may vertically overlap the active region.

The gate bond pad410and the source bond pad420may be provided at the same height from the upper surface120U of the semiconductor layer structure120. A passivation layer430may be provided to electrically isolate the gate bond pad410and the source bond pad420.

A conductive gate connector210electrically connected to a gate resistor134R may be provided on the gate resistor134R. The conductive gate connector210may contact the gate resistor134R. A gate bus230electrically connected to the conductive gate connector210may be provided on the gate resistor134R. The gate bus230may contact the gate resistor134R and may be electrically connected to the conductive gate connector210through the gate resistor134R. A field oxide layer140may be interposed between the semiconductor layer structure120and the gate resistor134R and between the semiconductor layer structure120and the conductive gate connector210. The portions of the source regions128underneath the field oxide layer140may have the opposite conductivity type (e.g., p-type) than the remainder of the source regions128(which may be n-type) to form a p-type guard ring. The gate bond pad410may vertically overlap the conductive gate connector210, the gate resistor134R and the field oxide layer140. The MOSFET2100may include multiple conductive gate connectors210, multiple gate resistors134R and multiple field oxide layer140.

The dielectric layer340may electrically isolate conductive elements (e.g., the conductive gate connector210, the source contact220and the gate bus230) from each other. The MOSFET2100may further include a first conductive via310and a second conductive via320that are provided in the dielectric layer340. In some embodiments, the first conductive via310and the second conductive via320may extend through the dielectric layer340. The first conductive via310may electrically connect the gate bond pad410to the conductive gate connector210. In some embodiments, the first conductive via310may contact the gate bond pad410and the conductive gate connector210. The second conductive via320may electrically connect the source bond pad420to the source contact220. In some embodiments, the second conductive via320may contact the source bond pad420and the source contact220.

Referring toFIGS.14and15, the field oxide layer140may have a narrow width in the area where the conductive gate connector210and the gate resistor134R are not provided. Accordingly, a portion of the source contact220may be provided outside of the gate bus230, and a portion of the semiconductor layer structure120below that portion of the source contact220can be used as an active region.

In some embodiments, the conductive gate connector210, the source contact220and/or the gate bus230may be formed concurrently by the same processes. For example, a first conductive layer (e.g., a first metal layer) may be formed on the gate structures and then the first conductive layer may be patterned to form the conductive gate connector210, the source contact220and/or the gate bus230. Accordingly, the conductive gate connector210, the source contact220and/or the gate bus230may include respective portions of the first conductive layer.

In some embodiments, the gate bond pad410and the source bond pad420may be formed concurrently by the same processes. For example, a second conductive layer (e.g., a second metal layer) may be formed on the dielectric layer340and then the second conductive layer may be patterned to form the gate bond pad410and the source bond pad420. Accordingly, the gate bond pad410and the source bond pad420may include respective portions of the second conductive layer. In some embodiments, top surfaces of the gate bond pad410and the source bond pad420may be coplanar with each other, and the gate bond pad410and the source bond pad420may have the same thicknesses in the third direction D3.

Referring toFIGS.19and20, in the area where the gate bond pads410are not provided, the gate resistor134R may be omitted, and the gate bus230may contact the gate electrode134and the field oxide layer140.

Referring toFIGS.10and12, the MOSFET2100may include four gate bond pads410(i.e., a first gate bond pad, a second gate bond pad, a third gate bond pad and a fourth gate bond pad) that are positioned above respective first, second, third and fourth corner regions of the upper surface120U of the semiconductor layer structure120.

The MOSFET2200inFIG.11and the MOSFET2300inFIG.16are similar to the MOSFET2100inFIG.10with a primary difference being that the MOSFETs2200and2300include different numbers of gate bond pads410at different locations.

Referring toFIGS.11and16, the each of the MOSFETs2200and2300may include a first gate bond pad410that is adjacent a first side of the semiconductor layer structure120and a second gate bond pad410that is adjacent a second side of the semiconductor layer structure120. The first side may be opposite the second side. In some embodiments, the first and second gate bond pads410may each positioned about midway between a third side of the semiconductor layer structure120and a fourth side of the semiconductor layer structure120, where the fourth side is opposite the third side when the semiconductor device is viewed from above as illustrated inFIGS.11and16.

The MOSFET2300may further include a third gate bond pad410between the first and second gate bond pads410. In some embodiments, the third gate bond pad410may be positioned above a center of the upper surface120U of the semiconductor layer structure120as illustrated inFIG.16.

FIGS.17and18are cross-section views of the MOSFET2300taken along the lines E″-E″ and F″-F″ inFIG.16. The cross-section views of the MOSFET2300illustrated inFIGS.17and18are similar to the cross-sectional views illustrated inFIGS.12and13with primary differences being that a field oxide layer140, a gate resistor134R and a gate bus230are additionally provided adjacent the third gate bond pad410that is positioned about midway between opposing sides of the upper surface120U of the semiconductor layer structure120, and portions of the source contact220are provided on opposing sides of the field oxide layer140. The field oxide layer140and the gate resistor134R may be interposed between the third gate bond pad410and the semiconductor layer structure120, and the gate bus230may be provided on the gate resistor134R. In some embodiment, the gate bus230may enclose the third gate bond pad410when the MOSFET is viewed from above. The gate bond pads410may vertically overlap the active region of the semiconductor layer structure120, which is below the source contact220.

FIGS.21and22are plan views of MOSFETs according to further embodiments of the present invention.FIGS.23,24,25and26are cross-sectional views of the MOSFETs inFIGS.21and22according to embodiments of the present invention. Specifically,FIG.23is a cross-sectional view taken along the line K-K inFIG.21or the line K′- K′ inFIG.22,FIG.24is a cross-sectional view taken along the line L-L inFIG.21or the line L′-L′ inFIG.22,FIG.25is a cross-sectional view taken along the line M-M inFIG.21or the line M′-M′ inFIG.22, andFIG.26is a cross-sectional view taken along the line N-N inFIG.21or the line N′-N′ inFIG.22. The lines K-K, K′- K′, M-M and M′-M′ pass through a gate electrode (e.g., a gate electrode134inFIG.23), and the lines L-L, L′-L′, N-N and N′-N′ pass through a source region (e.g., a source region128inFIG.24).

Referring toFIGS.21through26, the MOSFETs2400and2500inFIGS.21and22are similar to the MOSFET2200inFIG.11with a primary difference being that a first gate bus connector230L1, a second gate bus connector230L2, and a conductive gate bus plug230P or230P′ are additionally provided. The first and second gate bus connectors230L1,230L2are conductive structures that electrically connect the gate bus230to the conductive gate bus plugs230P/230P'plugs. As shown inFIGS.21-23, the first and second gate bus connectors230L1,230L2may be implemented as metal segments that extend above the source contact220._The first and second gate bus connectors230L1and230L2, the conductive gate bus plug230P or230P′ and the gate bus230may be all electrically connected to each other and may collectively form a gate bus structure. The gate bus structure may include portions disposed at different height from the upper surface120U of the semiconductor layer structure120. For example, the first and second gate bus connectors230L1and230L2may be provided at a level higher than a level at which the gate bus230is provided.

The first gate bus connector230L1may extend longitudinally in the first direction D1 and may be on top of one or more portions of the gate bus230. The second gate bus connector230L2may extend longitudinally in the second direction D2 and may also be on top of one or more portions of the gate bus230. The gate bus230and the first and second gate bus connectors230L1and230L2may be provided at a level lower than a level at which the gate bond pad410is provided. Accordingly, the gate bond pad410may vertically overlap the gate bus230and the first and second gate bus connectors230L1and230L2.

Each of the first and second gate bus connectors230L1and230L2may vertically overlap the source contact220. The source contact220may be electrically connected to multiple source regions128in the active region. In some embodiments, the first gate bus connector230L1may traverse a portion of the source contact220as illustrated inFIGS.21and22. The dielectric layer340may be interposed between the source contact220and the first and second gate bus connectors230L1and230L2.

The conductive gate bus plug230P may protrude from the first and second gate bus connectors230L1and230L2toward the gate electrode134and may contact the first gate electrode134. In some embodiments, the conductive gate bus plug230P may have a linear shape and may extend longitudinally in the second direction D2 as illustrated inFIG.21. In some embodiments, the conductive gate bus plug230P′ may include multiple conductive gate bus plugs230P′ that are spaced apart from each other in the second direction D2 as illustrated inFIG.22. The conductive gate bus plugs230P′ may contact respective gate electrodes134. The conductive gate bus plug230P and230P′ may be provided in the dielectric layer340. The first and second gate bus connectors230L1and230L2may be at a level different from a level at which the conductive gate bus plug230P and230P′ are provided. The conductive gate bus plug230P and230P′ may be at a level lower than a level of the first and second gate bus connectors230L1and230L2. In some embodiments, upper surfaces of the first and second gate bus connectors230L1and230L2may be higher than upper surfaces of the conductive gate bus plug230P and230P′.

Referring toFIGS.23and24, the field oxide layer140may be provided between the semiconductor layer structure120and the conductive gate bus plug230P or230P′, and the conductive gate bus plug230P or230P′ may vertically overlap the field oxide layer140. The conductive gate bus plug230P may contact multiple gate electrodes134. The conductive gate bus plugs230P′ may contact respective multiple gate electrodes134.

Referring toFIGS.25and26, the second gate bus connector230L2may vertically overlap the conductive gate bus plug230P or at least one of the conductive gate bus plugs230P′.

Referring toFIGS.21and22, each of the MOSFETs2400and2500may include a first gate bond pad410that is adjacent a first side of the semiconductor layer structure120and a second gate bond pad410that is adjacent a second side of the semiconductor layer structure120. The first side may be opposite the second side. The first and second gate bond pads410may each positioned about midway between a third side of the semiconductor layer structure120and a fourth side of the semiconductor layer structure120, where the fourth side is opposite the third side when the semiconductor device is viewed from above as illustrated inFIGS.21and22.

FIG.27is a plan view of a MOSFET2600including double metal layers and lumped gate resistors136according to embodiments of the present invention.FIGS.28,29,30and31are cross-sectional views of the MOSFET2600inFIG.27according to embodiments of the present invention. Specifically,FIG.28is a cross-sectional view taken along the line O-O inFIG.27,FIG.29is a cross-sectional view taken along the line P-P inFIG.27,FIG.30is a cross-sectional view taken along the line Q-Q inFIG.27, andFIG.31is a cross-sectional view taken along the line R-R inFIG.27. The lines O-O and Q-Q pass through a gate electrode (e.g., a gate electrode134inFIG.28), and the lines P-P and R-R pass through a source region (e.g., a source region128inFIG.29).

The MOSFET2600inFIG.27is similar to the MOSFET2300inFIG.16with a primary difference being that lumped gate resistors136are provided under the gate bond pads410, respectively. Referring toFIGS.27through31, the MOSFET2600may include lumped gate resistors136, each of which includes a first portion extending longitudinally in the first direction D1 and a second portion extending longitudinally in the second direction D2. The second portion of the lumped gate resistor136may extend from one of gate electrodes134in the second direction D2.

The MOSFET2600may include two lumped gate resistors136(i.e., first and second lumped gate resistors) that are spaced apart from each other in the first direction D1. The first and second lumped gate resistors136may be above first and second sides of the semiconductor layer structure120, respectively. The first side may be opposite the second side.

The first and second lumped gate resistors136may be underneath first and second gate bond pads410, respectively, and may be electrically connected to the first and second gate bond pads410, respectively. Each of the first and second lumped gate resistors136may be electrically connected to the first or second gate bond pads410through the conductive gate connector210and the first conductive via310. The conductive gate connector210and the first conductive via310, which are electrically connected to the first gate bond pad410and the first lumped gate resistor136, may be underneath the first gate bond pad410. The conductive gate connector210and the first conductive via310, which are electrically connected to the second gate bond pad410and the second lumped gate resistor136, may be underneath the second gate bond pad410. The conductive gate connector210underneath the first gate bond pad410may contact the first lumped gate resistor136, and the conductive gate connector210underneath the second gate bond pad410may contact the second lumped gate resistor136.

FIG.32is a flow chart of a method of forming a MOSFET including double metal layers according to some embodiments of the present invention.FIGS.33A,33B,34A,34B,35A,35B36A and 36B are cross-sectional views illustrating a method of forming a MOSFET including double metal layers according to embodiments of the present invention. Specifically,FIGS.33A,34A,35A and36Aare cross-sectional views taken along the line E-E inFIG.10, andFIGS.33B,34B,35B and36Bare cross-sectional views taken along the line F-F inFIG.10.

Referring toFIGS.1A,32,33A and33B, the method may include providing a silicon carbide based semiconductor layer structure120(Block3100). The semiconductor layer structure120may include an active region defined therein and a plurality of source regions128in the active region. A field oxide layer140may be formed on an upper surface120U of the semiconductor layer structure120.

Referring toFIGS.1A,32,33A and33B, a plurality of gate structures160, each of which includes a gate electrode134, a gate insulating layer (not shown, but interposed between the gate electrode and the semiconductor layer structure as is well known in the art), and a gate capping layer150on the gate electrode134, may be formed on the semiconductor layer structure120(Block3200). The gate electrode134may be formed along a surface of the field oxide layer140and a portion of the gate electrode134formed on the field oxide layer140may be used as a gate resistor134R.

Referring toFIGS.1A,32,34A and34B, a source contact220, a conductive gate connector210and a gate bus230may be formed (Block3300). The conductive gate connector210and the gate bus230may be formed, for example, by forming a sacrificial layer on the gate resistor134R and forming openings in the sacrificial layer, and then filling the openings with a conductive material to form the conductive gate connector210and the gate bus230. The source contact220may be formed on the plurality of source regions128in the active region and may be electrically connected to the plurality of source regions128. In some embodiments, the source contact220may contact the plurality of source regions128. The conductive gate connector210may be formed on one of the gate electrodes134and may be electrically connected thereto. In some embodiments, the conductive gate connector210may contact the one of the gate electrodes134. The conductive gate connector210may be formed to vertically overlap the field oxide layer140.

The source contact220and the conductive gate connector210may be formed through multiple unit processes. For example, a first metal layer may be formed on the plurality of source regions128and the plurality of gate structures160and then the first metal layer may be patterned to form the source contact220and the conductive gate connector210. Accordingly, the source contact220and the conductive gate connector210may include first and second portions of the first metal layer, respectively. The first metal layer may be patterned by performing an etch process using an etch mask layer (e.g., a photoresist layer) that is formed on the first metal layer. In some embodiments, a gate bus230including a third portion of the first metal layer may be formed concurrently with the source contact220and the conductive gate connector210.

Referring toFIGS.1A,32,35A and35B, a dielectric layer340may be formed on the source contact220and the conductive gate connector210(Block3400). The dielectric layer340may cover the source contact220and the conductive gate connector210. A first conductive via310and a second conductive via320may be formed in the dielectric layer340. The first conductive via310may vertically overlap the conductive gate connector210and may be electrically connected thereto. The second conductive via320may vertically overlap the source contact220and may be electrically connected thereto. In some embodiments, multiple second conductive vias320may be formed to vertically overlap the source contact220.

Referring toFIGS.1A,32,36A and36B, a source bond pad420and a gate bond pad410may be formed on the dielectric layer340(Block3500). The source bond pad420may be electrically connected to the source contact220through the second conductive via320, and the gate bond pad410may be electrically connected to the conductive gate connector210through the first conductive via310. The first conducive via310may be interposed between the gate bond pad410and the conductive gate connector210, and the second conductive via320may be interposed between the source bond pad420and the source contact220.

The source bond pad420and the gate bond pad410may be formed through multiple unit processes. For example, a second metal layer may be formed on the dielectric layer340and then the second metal layer may be patterned to form the source bond pad420and the gate bond pad410. Accordingly, the source bond pad420and the gate bond pad410may include first and second portions of the second metal layer, respectively. The second metal layer may be patterned by performing an etch process using an etch mask layer that is formed on the second metal layer. A passivation layer430may be formed between the source bond pad420and the gate bond pad410for electrical isolation therebetween.

In some embodiments, the method may also include, before the source bond pad420and the gate bond pad410are formed, forming a linear portion (e.g., the first and second gate bus connectors230L1and230L2inFIG.21) that is electrically connected to the gate bus230. The linear portion may be formed on the dielectric layer340. The liner portion and the gate bus230may collectively form a gate bus structure. The linear portion may be formed through multiple unit processes. For example, a third metal layer may be formed on the dielectric layer340and then the third metal layer may be patterned to form the linear portion. The third metal layer may be patterned by performing an etch process using an etch mask layer that is formed on the third metal layer.

While embodiments of the present invention are discussed above with respect to semiconductor devices that have channels that extend laterally underneath gate electrodes that extend on a top surface of the semiconductor layer structure, it will be appreciated that embodiments of the present invention are not limited thereto. For example, in other embodiments, the semiconductor devices may have gate electrodes that extend in trenches that are formed within the semiconductor layer structure.FIG.1Bis a cross-sectional view of an alternative version of the MOSFETs inFIGS.1,2and5, where the MOSFET is implemented to have trench gate electrodes. As shown inFIG.1B, the design of the MOSFET ofFIG.1Bis similar to the design of the MOSFET ofFIG.1A. However, in the MOSFET ofFIG.1B, trenches121are formed in the semiconductor layer structure120, and the gate insulators132are formed along the sidewalls and bottom surfaces of the trenches121. Heavily-doped p-type (p+) deep shielding patterns127A may be formed underneath at least a portion of the bottom of each trench121to protect the gate insulators from high electric fields during reverse blocking operation. P-type deep shielding connection patterns127B may electrically connect the deep shielding patterns to the p-type well regions126. As otherwise the MOSFETFIG.1Bmay be generally identical to the MOSFET ofFIG.1A, further description thereof will be omitted. It will be appreciated that any of the MOSFETs or IGBTs according to embodiments of the present invention may have the trench gate electrode design shown inFIG.1B.

The invention has been described above with reference to the accompanying drawings, in which embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. It will be understood that when an element or layer is referred to as being “on”, “connected to” or “coupled to” another element or layer, it can be directly on, connected or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly connected to” or “directly coupled to” another element or layer, there are no intervening elements or layers present. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. Like numbers refer to like elements throughout, except where expressly noted.

It will be understood that although the terms first and second are used herein to describe various regions, layers and/or elements, these regions, layers and/or elements should not be limited by these terms. These terms are only used to distinguish one region, layer or element from another region, layer or element. Thus, a first region, layer or element discussed below could be termed a second region, layer or element, and similarly, a second region, layer or element may be termed a first region, layer or element without departing from the scope of the present invention.

It will be understood that the embodiments disclosed herein can be combined. Thus, features that are pictured and/or described with respect to a first embodiment may likewise be included in a second embodiment, and vice versa.

While the above embodiments are described with reference to particular figures, it is to be understood that some embodiments of the present invention may include additional and/or intervening layers, structures, or elements, and/or particular layers, structures, or elements may be deleted. Although a few exemplary embodiments of this invention have been described, those skilled in the art will readily appreciate that many modifications are possible in the exemplary embodiments without materially departing from the novel teachings and advantages of this invention. Accordingly, all such modifications are intended to be included within the scope of this invention as defined in the claims. Therefore, it is to be understood that the foregoing is illustrative of the present invention and is not to be construed as limited to the specific embodiments disclosed, and that modifications to the disclosed embodiments, as well as other embodiments, are intended to be included within the scope of the appended claims. The invention is defined by the following claims, with equivalents of the claims to be included therein.