Power integrated circuit

A power integrated circuit including a substrate of semiconductor material having a first conductivity type on which is formed a first epitaxial layer of the same conductivity type. In a first portion of the first epitaxial layer are formed first and second diffused regions having respectively first and second conductivity type. The first and the second diffused regions are isolated from a power stage included partially in a second portion of the first epitaxial layer by an annular region having the second conductivity type. Over the first epitaxial layer is formed a second epitaxial layer having the first conductivity type in which are extended the first and the second diffused regions to permit forming a control circuitry for the power stage.

BACKGROUND OF THE INVENTION 
1. Field of the Invention 
The present invention relates to a power integrated circuit and to a 
related manufacturing process. 
2. Description of the Related Art 
In conventional power integrated circuit technologies, in which the power 
stage is preferably of the vertical DMOS type of structure, some 
limitations are present when these technologies are used in high-frequency 
applications or when the substrate includes high-voltage (e.g. 
&gt;300V/.mu.sec) transients. These limitations are due to the presence of 
high junction capacitances between the substrate and diffused and isolated 
regions having respectively an N-type and a P-type conductivity and 
including the control circuitry of the power stage. The dimensions of 
these junction capacitances are proportional to the dimensions of the 
diffused and isolated regions. When there are abrupt changes in the 
voltage present on the substrate these junction capacitances transmit 
disturbances to the control circuitry of the power stage and compromise 
its operation. It would therefore be necessary either to reduce 
drastically the dimensions of the control circuitry or provide in the 
substrate a low resistance through which conveying to a ground terminal a 
large part of the current injected capacitively from the substrate to the 
control circuitry. 
A known technical solution for solving these problems is described in 
European Patent Applications 95830060.0 and 94830229.4, both of the same 
applicant. 
The first patent application describes a process for providing a power 
integrated circuit including a semiconductor substrate in which is 
diffused a region having an N-type conductivity. The diffused region is 
isolated from the substrate by an implanted buried region having a P-type 
conductivity. Specifically, the buried region is formed implanting 
high-energy boron. Normally the buried region has a thickness of 
approximately 1 .mu.m and a distance from the integrated circuit surface 
dependent upon the implantation energy. For example, if the implantation 
energy used is around 900 kev the buried region will be at a depth of 
approximately 1.5 .mu.m. To connect the buried region with the integrated 
circuit surface there is formed through an implantation and a successive 
diffusion a deep region having a P-type conductivity. The deep region 
includes two structurally independent regions which contact laterally the 
buried region. The buried region and the deep region form an annular 
region including the diffused region. The annular region isolates the 
diffused region from the rest of the integrated circuit. In this solution 
the thickness of the diffused region is on the order of 1 .mu.m depending 
also on the doping of the region. But this thickness is insufficient if 
the diffused region must also include the control circuitry of the power 
stage. 
The second patent application describes a process for providing a power 
integrated circuit including a control circuitry incorporated in first and 
second diffused regions having respectively an N-type conductivity and a 
P-type conductivity. Again in this case the first and second diffused 
regions are isolated from the rest of the integrated circuit through an 
annular region including a buried region, implanted with high energy, and 
a deep region. When the implantation of the buried region is performed at 
900 kev the depth at which the buried region is located does not exceed 2 
.mu.m. Considering that the thickness of the buried region is 
approximately 1 .mu.m the residual thickness towards the surface of the 
integrated circuit is approximately 1 .mu.m. This thickness is 
insufficient for providing the control circuitry of the power stage. 
Indeed, the thermal cycles necessary for forming the power stage cause 
rising of the buried region to the surface. This shortcoming could be 
avoided implanting the buried region at much higher energy but the entire 
process would be much costlier. 
SUMMARY OF THE INVENTION 
It is an object of the present invention to provide a power integrated 
circuit and a related manufacturing process which would have better 
breakdown voltage for equal manufacturing cost or which for equal 
breakdown voltage would have smaller manufacturing cost. 
The solution idea underlying the present invention is to grow on the power 
integrated circuit surface an epitaxial layer to increase the thickness of 
the P-type and N-type diffused regions including the control circuitry of 
the power stage. 
The preferred embodiment of the invention is implemented in a power 
integrated circuit including a substrate of semiconductor material having 
a first conductivity type on which is formed a first epitaxial layer of 
the same conductivity type. In a first portion of the first epitaxial 
layer are formed first and second diffused regions having respectively 
first and second conductivity type. The first and the second diffused 
regions are isolated from a power stage included partially in a second 
portion of the first epitaxial layer by an annular region having the 
second conductivity type. Over the first epitaxial layer is formed a 
second epitaxial layer having the first conductivity type in which are 
extended the first and the second diffused regions to permit forming a 
control circuitry for the power stage. 
The features and advantages of the integrated circuit and related 
maufacturing process according to the present invention will become 
apparent from the following description of an embodiment thereof, given by 
way of example and not limitation, with reference to the accompanying 
drawings.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
The figures of the accompanying drawings generally and schematically 
illustrate a power integrated circuit and a related manufacturing process 
in accordance with the invention. 
For convenience of explanation a preferred embodiment of the inventive 
power integrated circuit is now described with reference to its 
manufacturing process. 
As shown in FIG. 1 the power integrated circuit 40 includes a semiconductor 
material substrate 1, e.g. silicon, having a first conductivity type, in 
particular N.sup.+ -type. On the substrate 1 is grown a first epitaxial 
layer 2 having the same conductivity type of the substrate and in 
particular N.sup.- -type. 
With reference to FIG. 2, on the surface of the power integrated circuit 40 
is deposited a first mask provided by known techniques. In exposed 
portions of the first epitaxial layer 2 are implanted and successive 
diffused a diffused region 3 having the first conductivity type, in 
particular N-type, and a diffused region 4 having a second conductivity 
type, in particular P-type. Successively in other exposed portions of the 
first epitaxial layer 2 are implanted and succesive diffused deep regions 
5 and 6 having the second conductivity type, in particular P.sup.+ -type. 
The deep regions 5 and 6 include each two structurally independent regions 
designated respectively 5', 5" and 6', 6". Simultaneously there is 
provided another diffusion of the diffused regions 3 and 4. As will be 
understood by those skilled in the art, the deep region 5 is preferably 
annular in topology. The term "annular" is used herein to mean a closed 
region and preferably is generally rectangular or opposed to circular. The 
deep region 6 is also preferably annular viewed from the top surface of 
the device. 
As shown in FIG. 3 a second mask is deposited to form opposite the diffused 
regions 3 and 4 a buried region 7. The buried region 7 is obtained by an 
high-energy implantation, e.g. 900 kev, of ions of a dopant having the 
second conductivity type, e.g. boron. The buried region 7 has a depth 
dependent on the implantation energy, e.g. at 900 kev the buried region is 
at a depth of approximately 1.5 .mu.m. In addition the buried region 7 is 
limited laterally by the deep region 5 with which it forms an annular 
isolation region 43 enclosing the diffused regions 3 and 4. 
With reference to FIG. 4, after removal of the second mask is grown on the 
first epitaxial layer 2 a second epitaxial layer 8 having the first 
conductivity type and in particular N--type and a thickness of a few 
.mu.m, e.g. 2 .mu.m. The diffused regions 3 and 4 and the deep regions 5 
and 6, during the successive diffusion heat treatments to which will be 
subjected the integrated circuit 40 will diffuse partially in the second 
epitaxial layer 8 increasing their thickness. 
As shown in FIG. 5, on the surface of the integrated circuit 40 is grown a 
thin oxide layer 9. Successively there are deposited polycrystalline 
silicon layers designated with 10, 11 and 12. 
With reference to FIG. 6, there are then formed through an implantation and 
successive diffusion heat treatment diffused regions 13 and 14 having the 
second conductivity type. The diffused regions 13 and 14 include each two 
structurally independent regions respectively designated with 13', 13" and 
14',14". In particular the diffused region 13 performs the contact of the 
annular isolation region 43 with the surface of the integrated circuit 
enclosing and isolating completely the diffused regions 3 and 4 from the 
rest of the integrated circuit 40. 
As shown in FIG. 7 and in FIG. 8 one then proceeds with implantation and 
successive diffusion of diffused regions 15, 16, 17 and 18 having the 
first conductivity type, and in particular N.sup.+ -type, and diffused 
regions 19 and 20 having the second conductivity type. The manufacturing 
process of the integrated circuit 40 then proceeds in the conventional 
manner with the deposit of a passivating material layer 21, with the 
opening of the contacts and with the deposit of metallizations 22, 23, 24, 
25, 26 and 27. 
With reference to FIG. 9, the diffused regions 15 and 19 form a source 
region of a signal P-channel MOS transistor 45 which is included in the 
diffused region 3. The signal transistor 45 also includes a gate region 
formed by the polycrystalline silicon layer 10 and a drain region formed 
by the diffused region 20. In addition the diffused regions 16 and 17 form 
respectively a source region and a drain region of a signal N-channel MOS 
transistor 46 which is provided in the diffused region 4. The signal 
transistor 46 also includes a gate region formed by the polycrystalline 
silicon layer 11. 
Again with reference to FIG. 9, the diffused region 14 forms body regions 
of a power transistor 44 having a vertical DMOS type of structure. The 
power transistor 44 also includes a source region formed by the diffused 
region 18 and a drain region included in the substrate 1 and in the first 
epitaxial layer 2. The power transistor 44 also includes a gate region 
formed by the polycrystalline silicon layer 12. In addition, the 
metallization 22 provides the contact of the annular isolation region 43 
and of the diffused region 13 with a ground terminal GND at which is also 
connected the source region of the signal transistor 45. 
As shown in FIG. 10, without change the manufacturing process steps of the 
integrated circuit 40 it's possible to replace the power transistor 44 
with a power bipolar transistor 47 having vertical current flow. 
Specifically, the power bipolar transistor 47 includes a collector region 
included in the substrate 1 and in the first epitaxial layer 2, an emitter 
region 30 and a base region including a buried region 31, a diffused 
region 28 and a diffused region 29. The emitter region 30 is formed during 
the performance of the diffused regions 15, 16 and 17, while the buried 
region 31 is formed during the performance of the buried region 7. The 
diffused regions 28 and 29 are formed respectively during the performance 
of the diffused regions 4 and 13. 
As shown in FIG. 11 the power bipolar transistor 47 can also be provided 
with omission of the buried region 31 or omission either of the buried 
region 31 or the diffused region 28 as shown in FIG. 12. 
In conclusion the introduction of the second epitaxial layer 8 causes the 
diffused regions 3 and 4 to exhibit a thickness such as to allow greater 
breakdown voltage of the signal transistors 45 e 46 for equal implantation 
energy of the buried region 7. In addition for equal breakdown voltage of 
the above mentioned transistors the buried region 7 can be implanted with 
a lower energy thus reducing process costs.