Semiconductor device

According to one embodiment, a semiconductor device includes a first element region. The first element region includes first, second, and third semiconductor regions, and first, and second conductive layers. The first semiconductor region includes first, second, and third partial regions. A second direction from the first partial region toward the first conductive layer crosses a first direction from the second partial region toward the first partial region. The third partial region is between the second partial region and the second conductive layer in the second direction. The second semiconductor region includes a first semiconductor portion. The first semiconductor portion is between the first partial region and the first conductive layer in the second direction. At least a portion of the third semiconductor region is between the first partial region and the first semiconductor portion in the second direction.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2020-041890, filed on Mar. 11, 2020; the entire contents of which are incorporated herein by reference.

FIELD

Embodiments of the invention generally relate to a semiconductor device.

BACKGROUND

For example, it is desirable for the characteristic fluctuation of a semiconductor device such as a transistor or the like to be small.

DETAILED DESCRIPTION

According to one embodiment, a semiconductor device includes a first element region. The first element region includes a first semiconductor region, a second semiconductor region, a third semiconductor region, a first conductive layer, and a second conductive layer. The first semiconductor region includes a first partial region, a second partial region, and a third partial region, and is of a first conductivity type. A second direction from the first partial region toward the first conductive layer crosses a first direction from the second partial region toward the first partial region. The third partial region is between the second partial region and the second conductive layer in the second direction. The second conductive layer has a Schottky contact with the third partial region. The second semiconductor region includes a first semiconductor portion, and is of a second conductivity type. The first semiconductor portion is between the first partial region and the first conductive layer in the second direction. The third semiconductor region is of the first conductivity type. At least a portion of the third semiconductor region is between the first partial region and the first semiconductor portion in the second direction. A concentration of an impurity of the first conductivity type in the third semiconductor region is greater than a concentration of the impurity of the first conductivity type in the first partial region.

In the specification and drawings, components similar to those described previously in an antecedent drawing are marked with like reference numerals, and a detailed description is omitted as appropriate.

First Embodiment

FIG. 1is a schematic cross-sectional view illustrating a semiconductor device according to a first embodiment.

As shown inFIG. 1, the semiconductor device110according to the embodiment includes a first element region E1. The semiconductor device110may include a second element region, which is described below. The second element region is, for example, a cell region. As described below, at least a portion of the first element region E1is provided outside the second element region. The first element region E1is, for example, a terminal region.

The first element region E1includes a first semiconductor region11, a second semiconductor region12, a third semiconductor region13, a first conductive layer31, and a second conductive layer32.

The first semiconductor region11includes a first partial region11a, a second partial region11b, and a third partial region11c. The first semiconductor region11is of a first conductivity type. A first direction from the second partial region11btoward the first partial region11acrosses a second direction from the second partial region11btoward the third partial region11c.

The first direction is taken as an X-axis direction. One direction perpendicular to the X-axis direction is taken as a Z-axis direction. A direction perpendicular to the X-axis direction and the Z-axis direction is taken as a Y-axis direction. The second direction is, for example, the Z-axis direction.

The second direction (the Z-axis direction) from the first partial region11atoward the first conductive layer31crosses the first direction from the second partial region11btoward the first partial region11a.

The third partial region11cis between the second partial region11band the second conductive layer32in the second direction (the Z-axis direction). For example, the direction from the second conductive layer32toward the first conductive layer31is along the first direction (the X-axis direction). The second conductive layer32has a Schottky contact with the third partial region11c. For example, a Schottky barrier diode D1is formed of the third partial region11cand the second conductive layer32.

The second semiconductor region12includes a first semiconductor portion12a. The second semiconductor region12is of a second conductivity type. The first semiconductor portion12ais between the first partial region11aand the first conductive layer31in the second direction (the Z-axis direction).

The first conductive layer31is electrically connected to the second semiconductor region12. For example, a parasitic p-n diode D2is formed of the first conductive layer31, the second semiconductor region12, and the first partial region11aof the first semiconductor region11.

The third semiconductor region13is of the first conductivity type.

For example, the first conductivity type is an n-type, and the second conductivity type is a p-type. In the embodiment, the first conductivity type may be the p-type, and the second conductivity type may be the n-type. Hereinbelow, the first conductivity type is taken to be the n-type, and the second conductivity type is taken to be the p-type.

At least a portion of the third semiconductor region13is between the first partial region11aand the first semiconductor portion12ain the second direction (the Z-axis direction). The third semiconductor region13is connected to the third partial region11c. For example, it is possible for a current to flow between the third semiconductor region13and the third partial region11c.

For example, the concentration of an impurity of the first conductivity type in the third semiconductor region13is greater than the concentration of the impurity of the first conductivity type in the first partial region11a. For example, the concentration of the impurity of the first conductivity type in the third semiconductor region13is greater than the concentration of the impurity of the first conductivity type in the second partial region11b. For example, the concentration of the impurity of the first conductivity type in the third semiconductor region13is greater than the concentration of the impurity of the first conductivity type in the third partial region11c.

For example, because the third semiconductor region13is provided, the parasitic p-n diode D2formed of the first partial region11aand the second semiconductor region12does not switch on easily. The position in the X-axis direction where the parasitic p-n diode D2switches on is far from the position in the X-axis direction of the Schottky barrier diode D1.

By such a configuration, for example, the electron current that is injected from the second conductive layer32toward the third partial region11cand the hole current that is injected from the first conductive layer31toward the second semiconductor region12are spatially separated. Recombination of the electrons and the holes is suppressed thereby. By suppressing the recombination, the expansion of defects inside the semiconductor can be suppressed. For example, the formation of defects inside the semiconductor can be suppressed. The characteristic fluctuation of the semiconductor device can be suppressed thereby. For example, the breakdown of the semiconductor device can be suppressed. According to the embodiment, a semiconductor device can be provided in which the characteristic fluctuation can be small. For example, high reliability is obtained.

The first semiconductor region11, the second semiconductor region12, and the third semiconductor region13include, for example, SiC. When the semiconductor region includes SiC, recombination causes enlargement of stacking faults, and characteristic degradation easily occurs. The characteristic degradation includes, for example, the degradation of an on-voltage Vf of the diode. The characteristic degradation includes, for example, the degradation of an on-resistance Ron of a MOSFET. The characteristic degradation includes, for example, the degradation of a threshold voltage Vth of the MOSFET. When the semiconductor region includes SiC, the recombination is suppressed by providing the third semiconductor region13described above; therefore, the characteristic fluctuation can be effectively reduced. For example, high reliability is obtained.

As shown inFIG. 1, the semiconductor device110may include a first electrode51and a second electrode52. The direction from the first electrode51toward the second electrode52is along the second direction (the Z-axis direction). In the example, at least a portion of the first semiconductor region11is between the first electrode51and the second electrode52. The first conductive layer31and the second conductive layer32are between the first semiconductor region11and the second electrode52. The first conductive layer31and the second conductive layer32are electrically connected to the second electrode52. For example, the second conductive layer32contacts the second semiconductor region12.

As described below, when the cell region includes a transistor or the like, for example, the first electrode51corresponds to a drain electrode, and the second electrode52corresponds to a source electrode.

In the example as shown inFIG. 1, the first element region E1further includes a fourth semiconductor region14. The fourth semiconductor region14is of the second conductivity type (e.g., the p-type). The fourth semiconductor region14is provided between the first semiconductor portion12aand the first conductive layer31in the second direction (the Z-axis direction). The concentration of an impurity of the second conductivity type in the fourth semiconductor region14is greater than the concentration of the impurity of the second conductivity type in the second semiconductor region12(e.g., the first semiconductor portion12a).

In one example, the first conductive layer31has an ohmic contact with the fourth semiconductor region14.

In the example, the first element region E1further includes a first compound region41a. The first compound region41ais provided between the fourth semiconductor region14and the first conductive layer31. The first conductive layer31is electrically connected to the fourth semiconductor region14via the first compound region41a. The first compound region41aincludes, for example, a silicide. The first compound region41aincludes, for example, a silicide including nickel (e.g., NiSi2). A good electrical connection is obtained by providing the first compound region41a.

As shown inFIG. 1, the first semiconductor region11may further include a fourth partial region11d. The first partial region11ais between the second partial region11band the fourth partial region11din the first direction (the X-axis direction). The direction from the fourth partial region11dtoward a portion of the third semiconductor region13is along the second direction (the Z-axis direction). For example, the third semiconductor region13is longer than the first conductive layer31along the X-axis direction. Thereby, for example, the electron current and the hole current can be effectively separated spatially.

As shown inFIG. 1, the second semiconductor region12may further include a second semiconductor portion12b. The second semiconductor portion12bis between the third partial region11cand the fourth semiconductor region14in the first direction (the X-axis direction). For example, the first semiconductor region11further includes a fifth partial region11e. The fifth partial region11eis between the second partial region11band the first partial region11ain the first direction (the X-axis direction). A portion of the third semiconductor region13is between the fifth partial region11eand the second semiconductor portion12bin the second direction (the Z-axis direction). A stable connection with the third partial region11cis obtained by such a third semiconductor region13.

As shown inFIG. 1, the first element region E1may further include a third conductive layer33, a second-conductivity-type (e.g., p-type) fifth semiconductor region15, and a first-conductivity-type (e.g., n-type) sixth semiconductor region16.

The first semiconductor region11further includes a sixth partial region11f. The second partial region11bis between the sixth partial region11fand the first partial region11ain the first direction (the X-axis direction). The fifth semiconductor region15includes a third semiconductor portion15c. At least a portion of the sixth partial region11fis between the sixth partial region11fand the third semiconductor portion15cin the second direction (the Z-axis direction). The sixth semiconductor region16is connected to the third partial region11c. The concentration of the impurity of the first conductivity type in the sixth semiconductor region16is greater than the concentration of the impurity of the first conductivity type in the third partial region11c.

For example, another parasitic p-n diode D2is formed of the sixth partial region11f, the fifth semiconductor region15, and the third conductive layer33. By providing the sixth semiconductor region16, for example, the electron current that is injected from the second conductive layer32toward the third partial region11cand the hole current that is injected from the third conductive layer33toward the fifth semiconductor region15are spatially separated. The recombination of the electrons and the holes is suppressed thereby. By suppressing the recombination, the defects in the semiconductor region can be suppressed. The fluctuation of the characteristics of the semiconductor device can be suppressed thereby. According to the embodiment, a semiconductor device can be provided in which the characteristic fluctuation can be reduced. For example, high reliability is obtained.

In one example, the distance along the first direction (the X-axis direction) between the third semiconductor region13and the sixth semiconductor region16is less than the length along the first direction of the second conductive layer32.

As shown inFIG. 1, the first element region E1may further include a seventh semiconductor region17of the second conductivity type. The seventh semiconductor region17is provided between the third semiconductor portion15cand the third conductive layer33in the second direction (the Z-axis direction). The concentration of the impurity of the second conductivity type in the seventh semiconductor region17is greater than the concentration of the impurity of the second conductivity type in the fifth semiconductor region15(e.g., the third semiconductor portion15c).

As shown inFIG. 1, the first element region E1may further include a second compound region41b. The second compound region41bincludes, for example, a silicide (e.g., NiSi2, etc.). The second compound region41bis provided between the seventh semiconductor region17and the third conductive layer33. The third conductive layer33is electrically connected to the seventh semiconductor region17via the second compound region41b.

As shown inFIG. 1, the first semiconductor region11may further include a seventh partial region11g. The sixth partial region11fis provided between the seventh partial region11gand the second partial region11bin the first direction (the X-axis direction). The first semiconductor region11may further include an eighth partial region11h. The eighth partial region11his provided between the sixth partial region11fand the second partial region11bin the first direction (the X-axis direction).

The fifth semiconductor region15may include a fourth semiconductor portion15d. The fourth semiconductor portion15dis provided between the seventh semiconductor region17and the third partial region11cin the X-axis direction. The fourth semiconductor portion15dis provided between the eighth partial region11hand the fourth semiconductor portion15din the Z-axis direction. A portion of the sixth semiconductor region16is between the seventh partial region11gand the fifth semiconductor region15in the second direction (the Z-axis direction).

As shown inFIG. 1, the first element region E1may include an eighth semiconductor region18. For example, the eighth semiconductor region18is of the first conductivity type. The eighth semiconductor region18may be, for example, a substrate. The eighth semiconductor region18may be, for example, a SiC substrate.

For example, the first semiconductor region11may be formed by epitaxial growth on the eighth semiconductor region18. For example, the second to seventh semiconductor regions12to17described above are formed by introducing impurities into portions of the first semiconductor region11.

When these semiconductor regions include SiC, for example, the n-type impurity includes at least one selected from the group consisting of N, P, and As. For example, the p-type impurity includes at least one selected from the group consisting of B, Al, and Ga.

The concentration of the impurity of the first conductivity type in the first semiconductor region11is, for example, not less than 1.1×1015/cm3and not more than 5×1016/cm3.

The concentrations of the impurity of the second conductivity type in the second and fifth semiconductor regions12and15are, for example, not less than 5×1018/cm3and not more than 1×1019/cm3.

The concentrations of the impurity of the first conductivity type in the third and sixth semiconductor regions13and16are, for example, not less than 5×1015/cm3and not more than 5×1017/cm3. It is favorable for the concentrations of the impurity of the first conductivity type in the third and sixth semiconductor regions13and16to be, for example, not less than 6×1016/cm3and not more than 2×1017/cm3.

The concentrations of the impurity of the second conductivity type in the fourth and seventh semiconductor regions14and17are, for example, not less than 1×1019/cm3and not more than 1×1021/cm3.

The concentration of the impurity of the first conductivity type in the eighth semiconductor region18is, for example, not less than 1×1018/cm3and not more than 1×1020/cm3. An example of profiles of the impurities in the semiconductor regions recited above are described below.

At least a portion of the first semiconductor region11is, for example, an n−-region. The third partial region11cis, for example, an n−-region. The second semiconductor region12and the fifth semiconductor region15are, for example, p−-regions. The third semiconductor region13and the sixth semiconductor region16are, for example, n+-regions. The fourth semiconductor region14and the seventh semiconductor region17are, for example, p+-regions.

The first conductive layer31, the second conductive layer32, and the third conductive layer33include at least one selected from the group consisting of Ti, Ni, Mo, and polysilicon.

As shown inFIG. 1, the first element region E1may include an insulating member60. For example, the insulating member60is provided between the second electrode52and the various semiconductor regions described above. The insulating member60includes, for example, silicon oxide (e.g., SiO2, etc.).

FIGS. 2A and 2Bare schematic views illustrating the semiconductor device according to the first embodiment.

As shown inFIGS. 2A and 2B, the semiconductor device110further includes a second element region E2(a cell region) in addition to the first element region E1. The second element region E2includes at least one of a transistor Tr1or a diode D3. At least a portion of the first element region E1is provided outside the second element region E2. The configuration illustrated inFIG. 1is provided in the first element region E1. The shape of a gate electrode (an interconnect GP) is illustrated inFIG. 2A. The diode D3is, for example, a Schottky barrier diode in the second element region E2(the cell region). The parasitic p-n diode of the transistor Tr1(e.g., a MOS transistor) in the second element region E2is clamped by the diode D3(the Schottky barrier diode). The unintended injection of charge (e.g., holes) due to the parasitic p-n diode is suppressed thereby.

On the other hand, when the third semiconductor region13and the sixth semiconductor region16described above are not provided in the first element region E1(the terminal region), the parasitic p-n diode D2of the first element region E1easily switches to the on-state. Therefore, the distance between the electron current from the Schottky barrier diode D1and the hole current from the parasitic p-n diode D2is short. Therefore, recombination easily occurs.

The third semiconductor region13and the sixth semiconductor region16are provided in the embodiment. The distance between the electron current from the Schottky barrier diode D1and the hole current from the parasitic p-n diode D2is increased thereby. The recombination is effectively suppressed thereby.

FIG. 3is a schematic cross-sectional view illustrating characteristics of the semiconductor device according to the first embodiment.

As shown inFIG. 3, electrons Ec flow from the second conductive layer32toward the first semiconductor region11. Because the third semiconductor region13is provided in the embodiment, the electrons Ec flow from the third partial region11ctoward the third semiconductor region13. The flow of the electrons Ec (the electron current) spreads along the X-axis direction (along the X-Y plane). The parasitic p-n diode D2does not easily switch on in the region through which the electrons Ec flow along the X-axis direction. Therefore, holes Hc from the first conductive layer31do not easily enter the region through which the electrons Ec flow along the X-axis direction. The holes Hc flow in a distant region in the X-axis direction when viewed from the second conductive layer32.

The density of the electrons Ec is high directly under the second conductive layer32and low away from the second conductive layer32. The density of the electrons is low in the region through which the holes Hc flow. The recombination of the electrons and the holes is suppressed thereby.

FIG. 4is a schematic cross-sectional view illustrating the semiconductor device according to the first embodiment.

In the semiconductor device110according to the embodiment as shown inFIG. 4, the fourth semiconductor region14includes a first end e1and a second end e2. The direction from the first end e1toward the second end e2is along the first direction (the X-axis direction). The position in the first direction (the X-axis direction) of the first end e1is between the position in the first direction (the X-axis direction) of the third partial region11cand the position in the first direction (the X-axis direction) of the second end e2. For example, the position in the first direction (the X-axis direction) of the first end e1is between the position in the first direction (the X-axis direction) of the second end e2and the position in the first direction (the X-axis direction) of a boundary bf1between the third partial region11cand the second semiconductor region12.

The third semiconductor region13includes a third end e3and a fourth end e4. The direction from the third end e3toward the fourth end e4is along the first direction (the X-axis direction). The position of the fourth end e4may match the position of the outer edge of the second semiconductor region12. The position of the fourth end e4may match the position of the outer edge of the first element region E1. The position in the first direction (the X-axis direction) of the first end e1is between the position in the first direction of the third end e3and the position in the first direction of the fourth end e4.

For example, the position in the first direction of the boundary bf1described above is between the position in the first direction of the third end e3and the position in the first direction of the first end e1. The position in the first direction of the boundary bf1may match the position in the first direction of the third end e3.

The position in the first direction (the X-axis direction) of the second end e2is between the position in the first direction of the first end e1and the position in the first direction of the fourth end e4. The distance in the first direction between the position in the first direction of the second end e2and the position in the first direction (the X-axis direction) of the boundary bf1between the third partial region11cand the second semiconductor region12is taken as a first distance d1. The distance in the first direction between the position in the first direction of the second end e2and the position in the first direction of the fourth end e4is taken as a second distance d2. The second distance d2corresponds to the length of the region through which the third semiconductor region13extends along the X-axis direction when viewed from the fourth semiconductor region14.

In the embodiment, it is favorable for the second distance d2to be greater than the first distance d1. Thereby, the position at which the holes Hc are substantially injected can be farther from the position at which the density of the electrons Ec is high.

In the embodiment, for example, the second distance d2may be not less than 2 times the first distance d1. The second distance d2may be not less than 3 times the first distance d1. The second distance d2may be not less than 5 times the first distance d1. The second distance d2may be not less than 10 times the first distance d1.

In one example according to the embodiment, the second distance d2is, for example, 5 μm or more. The second distance d2may be, for example, 10 μm or less.

As shown inFIG. 4, the length along the second direction (the Z-axis direction) of the third semiconductor region13is taken as a thickness t13. The thickness t13is, for example, not less than 0.1 μm and not more than 2 μm. The thickness t13may be, for example, not less than 0.2 μm and not more than 2 μm. For example, the thickness t13is not less than 0.001 times and not more than 1 times the second distance d2.

In one example, the thickness t13along the second direction of the third semiconductor region13is not less than 0.1 times and not more than 5 times a thickness t12along the second direction of the first semiconductor portion12a.

The distance along the first direction (the X-axis direction) between the first conductive layer31and the second conductive layer32is taken as a third distance d3. The third distance d3is, for example, not less than 0.5 μm and not more than 2 μm. By setting the third distance d3to be 0.5 μm or more, for example, the manufacturing is easier. By setting the first distance d1to be 2 μm or less, it is easier to downsize the semiconductor device.

As shown inFIG. 4, the boundary between the second partial region11band the third partial region11cis taken as a first boundary b1. The boundary between the first partial region11aand the third semiconductor region13is taken as a second boundary b2. The boundary between the third semiconductor region13and the second semiconductor region12is taken as a third boundary b3. For example, the first boundary b1corresponds to the lower end of the third partial region11c. For example, the second boundary b2corresponds to the lower end of the third semiconductor region13. For example, the third boundary b3corresponds to the lower end of the second semiconductor region12.

For example, the position in the second direction (the Z-axis direction) of the first boundary b1is between the position in the second direction of the second boundary b2and the position in the second direction of the third boundary b3. Thereby, for example, the current that flows in the third semiconductor region13from the third partial region11cis more than the current flowing in the second partial region11bfrom the third partial region11c. For example, the difference between the potential of the third semiconductor region13and the potential of the second semiconductor region12is small. For example, the parasitic p-n diode D2can be clamped farther in the X-axis direction.

FIG. 5is a graph illustrating characteristics of semiconductor devices.

The horizontal axis ofFIG. 5is a drain voltage Vd. The vertical axis ofFIG. 5is a drain current Id. InFIG. 5, the measurement results of a characteristic of a semiconductor device119of a first reference example are illustrated in addition to the measurement results of a characteristic of the semiconductor device110according to the embodiment. A Schottky diode is not provided in the semiconductor device119. Otherwise, the configuration of the semiconductor device119is similar to the configuration of the semiconductor device110.

As shown inFIG. 5, for the same drain voltage Vd, the absolute value of the drain current Id of the semiconductor device110is small compared to the semiconductor device119. It is considered that this is caused by the current based on the parasitic p-n diode D2of the first element region E1in the semiconductor device110being small compared to that of the semiconductor device119.

FIG. 6is a graph illustrating characteristics of semiconductor devices.

As shown inFIG. 6, a peak p1and a peak p2are observed for the semiconductor device119. The peak p1is caused by the parasitic p-n diode D2of the first element region E1. The peak p2is caused by the diode D3of the second element region E2. As shown inFIG. 6, these peaks are not observed for the semiconductor device110. Light emissions that correspond to the peaks described above are observed for the semiconductor device119. Light emission is not observed for the semiconductor device110.

FIG. 7is a schematic view illustrating the semiconductor device according to the embodiment.

FIG. 7illustrates profiles of the concentrations of the impurities in the semiconductor region of the semiconductor device110.FIG. 7corresponds to profiles along line segment X1-X2ofFIG. 1. The horizontal axis ofFIG. 7is a position pZ in the Z-axis direction. The vertical axis is a concentration C1of the impurity of the first conductivity type and a concentration C2of the impurity of the second conductivity type. As shown inFIG. 7, the third semiconductor region13includes the impurity of the first conductivity type and the impurity of the second conductivity type. The concentration C2of the impurity of the second conductivity type includes a “mountain skirt” at the position of the third semiconductor region13.

As shown inFIG. 7, the second semiconductor region12may include a region12p, a region12q, and a region12r. The region12qis between the third semiconductor region13and the region12r. The region12pis between the third semiconductor region13and the region12q. The region12ris, for example, a front-surface region. The region12qis, for example, an intermediate region. The region12pis a deep region. The impurity concentration of the second conductivity type in the region12ris, for example, not less than 1×1015/cm3and not more than 1×1018/cm3. For example, the threshold voltage is appropriately adjusted by such a concentration. The impurity concentration of the second conductivity type in the region12qis, for example, not less than 1×1017/cm3and not more than 1×1018/cm3. For example, punch-through can be suppressed by such a concentration. The impurity concentration of the second conductivity type in the region12pis, for example, not less than 1×1016/cm3and not more than 1×1017/cm3. For example, a high breakdown voltage is obtained by such a concentration.

In the embodiment, for example, the positions in the Z-axis direction of the fourth and seventh semiconductor regions14and17may correspond to the position in the Z-axis direction of the region12q.

Simulation results that relate to characteristics of the semiconductor device for first to sixth conditions CC1to CC6described below are shown in these figures. For the first condition CC1, a Schottky barrier diode is not provided in the terminal region. For the second to sixth conditions CC2to CC6, a Schottky barrier diode is provided in the terminal region. For the second condition CC2, the third semiconductor region13is not provided in the configuration illustrated inFIG. 1.

The third to sixth conditions CC3to CC6have the configuration illustrated inFIG. 1. The thickness t13of the third semiconductor region13is taken to be the full width at half maximum of the peak of the impurity of the first conductivity type of the third semiconductor region13. For the third condition CC3, the peak of the impurity concentration of the first conductivity type in the third semiconductor region13is 6×1016/cm3, and the thickness t13is 0.1 μm. For the fourth condition CC4, the peak of the impurity concentration of the first conductivity type in the third semiconductor region13is 1.2×1016/cm3, and the thickness t13is 0.1 μm. For the fifth condition CC5, the peak of the impurity concentration of the first conductivity type in the third semiconductor region13is 1.2×1017/cm3, and the thickness t13is 0.15 μm. For the sixth condition CC6, the peak of the impurity concentration of the first conductivity type in the third semiconductor region13is 1.2×1017/cm3, and the thickness t13is 0.2 μm.

The vertical axis ofFIG. 8Ais the drain current Id. The vertical axis ofFIG. 8Bis a current ISBD flowing in the Schottky barrier diode. The vertical axis ofFIG. 9Ais a hole current Ih flowing from the first conductive layer31. The vertical axis ofFIG. 9Bis an electron current Ie flowing from the first conductive layer31. The drain voltage is 4 V for these characteristics.

As shown inFIG. 8A, the drain current Id was large for the third to sixth conditions CC3to CC6. As shown inFIG. 8B, the current ISBD was large for the third to sixth conditions CC3to CC6. As shown inFIG. 9A, the hole current Ih was small for the third to sixth conditions CC3to CC6. As shown inFIG. 9B, the electron current Ie was small for the third condition CC3. The electron current Ie substantially was not generated for the fourth to sixth conditions CC4to CC6.

The vertical axis ofFIG. 10is an integral IR of the SRH (Shockley-Read-Hall) recombination in the drift region. As shown inFIG. 10, the integral IR in the first element region E1of the SRH recombination was small for the third to sixth conditions CC3to CC6. This trend increases when the peak of the impurity concentration of the first conductivity type in the third semiconductor region13is high or when the thickness t13is thick.

In the embodiment, for example, information that relates to the concentration of the impurity is obtained by SIMS analysis (Secondary Ion Mass Spectrometry), etc. For example, the end of a semiconductor region may be taken to be the position at which the concentration of ½ of the peak of the impurity concentration is obtained. For example, the width of the semiconductor region may be taken to be the full width at half maximum for the concentration of the impurity.

According to the embodiments, a semiconductor device can be provided in which the characteristic fluctuation can be reduced.

Hereinabove, exemplary embodiments of the invention are described with reference to specific examples. However, the embodiments of the invention are not limited to these specific examples. For example, one skilled in the art may similarly practice the invention by appropriately selecting specific configurations of components included in semiconductor devices such as semiconductor regions, conductive layers, compound regions, electrodes, insulating members, etc., from known art. Such practice is included in the scope of the invention to the extent that similar effects thereto are obtained.

Moreover, all semiconductor devices practicable by an appropriate design modification by one skilled in the art based on the semiconductor devices described above as embodiments of the invention also are within the scope of the invention to the extent that the spirit of the invention is included.