Input buffer circuit

When an input terminal, which is connected to an input transistor, is opened, a transistor having an emitter connected to the input transistor conducts to supply constant current to a constant current source which is connected to the emitter of the input transistor. Therefore, load current of a reference circuit connected to the constant current source is not changed even if the input terminal is opened. As the result, current values of all constant current sources receiving voltage from the reference circuit are not changed so that the internal circuit of a semiconductor integrated circuit device can be stably operated.

BACKGROUND OF THE INVENTION 
1. Field of the Invention 
The present invention relates to an improvement in an input stage of a 
semiconductor integrated circuit apparatus employing emitter-coupled logic 
(hereinafter referred to as ECL). 
2. Description of the Background Art 
FIG. 1 is a circuit diagram showing a conventional ECL circuit. A buffer 
circuit 1 is formed by a transistor Q.sub.1 and a constant current source 
circuit 2. The transistor Q.sub.1 is an emitter follower buffer NPN 
transistor. The transistor Q.sub.1 has a base connected to an input 
terminal 3, a collector connected to a first power supply line 4 and an 
emitter connected to the constant current source circuit 2. The transistor 
Q.sub.1 derives a signal which is responsive to an input signal received 
in the input terminal 3 at its emitter. The constant current source 
circuit 2 is a constant current load for supplying constant current to the 
transistor Q.sub.1. The constant current source circuit 2 is formed by a 
transistor Q.sub.2 and a resistor R.sub.1. The transistor Q.sub.2 is an 
NPN transistor, which has a base connected to a reference voltage input 
terminal 5, a collector connected to the emitter of the transistor Q.sub.1 
and an emitter connected to a second power supply line 6 through the 
resistor R.sub.1. 
An ECL differential pair 7 is formed by transistors Q.sub.3 and Q.sub.4. 
The transistors Q.sub.3 and Q.sub.4 are prepared by NPN transistors, 
emitters of which are commonly connected with each other. The transistor 
Q.sub.3 has a base connected to the emitter of the transistor Q.sub.1 and 
a collector connected to the first power supply line 4 through the 
resistor R.sub.2 as well as to an output terminal 8. The transistor 
Q.sub.4 has a base connected to a logic comparison reference voltage input 
terminal 9 and a collector connected to the first power supply line 4. The 
logic comparison reference voltage input terminal 9 is set at a potential 
value evaluated by adding the base-to-emitter potential of the transistor 
Q.sub.1 to an intermediate potential between a high-level signal and a 
low-level signal supplied to the input terminal 3. The transistor Q.sub.3 
is made conductive/nonconductive depending on whether or not a signal 
level supplied to its base is higher than the potential of the logic 
comparison reference voltage input terminal 9, so that a high-level or 
low-level signal is outputted from the output terminal 8. 
A constant current source circuit 10 is adapted to supply constant current 
to the ECL differential pair 7, and is formed by a transistor Q.sub.5 and 
a resistor R.sub.3. The transistor Q.sub.5 is prepared by an NPN 
transistor, which has a base connected to the base of the transistor 
Q.sub.2, a collector connected to the emitter common junction of the 
transistors Q.sub.3 and Q.sub.4 and an emitter connected to the second 
power supply line 6 through a resistor R.sub.7. 
Operation of the circuit in the aforementioned structure will now be 
described. When the input terminal 3 receives a high-level signal, the 
transistor Q.sub.3 of the ECL differential pair 7 is supplied in its base 
with a high-level signal which is higher than the potential at the logic 
comparison reference voltage input terminal 9 through the buffer 
transistor Q.sub.1, whereby the transistor Q.sub.3 enters a conducting 
state and the transistor Q.sub.4 enters a nonconducting state. Current 
flows to the resistor R.sub.2 to cause voltage drop, and hence a low-level 
signal is outputted from the output terminal 8. 
When the input terminal 3 receives a low-level signal, on the other hand, 
the transistor Q.sub.3 of the ECL differential pair 7 is supplied in its 
base with a low-level signal which is lower than the potential at the 
logic comparison reference voltage input terminal 9 through the buffer 
transistor Q.sub.1, whereby the transistor Q.sub.3 enters a nonconducting 
state and the transistor Q.sub.4 enters a conducting state. Since no 
current flows to the resistor R.sub.2 to cause no voltage drop in this 
case, a high-level signal is outputted from the output terminal 8. 
As hereinabove described, the transistor Q.sub.1 is regularly in a 
conducting state when a high-level or low-level signal is received in the 
input terminal 3, to level-shift the potential of the high-level or 
low-level signal by its base-to-emitter voltage to derive the same at the 
emitter. In such a normal operation state, current to the constant current 
source circuit 2 is supplied from the first power supply line 4. Assuming 
that the constant current supplied to the constant current source circuit 
2 is represented by I.sub.0 and the grounded emitter current amplification 
factor of the transistor Q.sub.2 is 100, current of I.sub.0 /100 is 
supplied to the base of the transistor Q.sub.2 from a reference circuit 
(not shown). 
FIG. 2 is a circuit diagram showing another conventional ECL circuit, 
wherein the constant current source circuit 2 shown in FIG. 1 is formed by 
a current mirror circuit. The constant current source circuit 2 comprises 
a transistor Q.sub.2, a resistor R.sub.3 and a diode D.sub.1. The diode 
D.sub.1 is equivalent to a transistor whose base and collector are 
interconnected with each other. The transistor Q.sub.2 has a base 
connected to a reference voltage input terminal 5 through the resistor 
R.sub.3 as well as to a second power supply line 6 through the diode 
D.sub.1 and an emitter connected to the second power supply line 6. This 
structure is so designed that a reference circuit (not shown), which is 
connected to the reference voltage input terminal 5, has reference voltage 
of V.sub.REF and supplies reference current of I.sub.01 {I.sub.01 
=(V.sub.REF -V.sub.F(D1) /R.sub.3 }. V.sub.F(D1) shows a voltage drop of 
diode D.sub.1. 
In the conventional semiconductor integrated circuit device having the 
aforementioned structure, the transistor Q.sub.1 enters a nonconducting 
state when the input terminal 3 is opened, whereby the constant current 
I.sub.0 to the constant current source circuit 2 cannot be supplied from 
the first power supply line 4. Thus, no collector current flows in the 
transistor Q.sub.2. Therefore, the transistor Q.sub.2 operates as a diode 
formed by the base and the emitter. Thus, load current of the reference 
circuit, which is base current of the transistor Q.sub.2 in the circuit 
shown in FIG. 1, is increased from I.sub.0 /100 to I.sub.0, whereby output 
voltage of the reference circuit is changed. In the circuit shown in FIG. 
2, on the other hand, the current I.sub.01 flowing in the diode D.sub.1 is 
divided by the diode D.sub.1 and the transistor Q.sub.2, to cause change 
in the anode potential of the diode D.sub.1, which is reference voltage of 
the constant current circuit 10. Consequently, all of the constant current 
sources receiving these reference voltages are changed in current value, 
to cause deviation in potential of an internal circuit when the 
semiconductor integrated circuit device is used under the condition that 
the input terminal 3 is opened. 
SUMMARY OF THE INVENTION 
The present invention provides an input buffer circuit for buffering an 
input signal to a desired circuit, wherein the input buffer circuit and 
the desired circuit are formed as a semiconductor integrated circuit 
device. The inventive input buffer circuit comprises first and second 
power sources; a buffer transistor having a base which is supplied with 
the input signal, a first electrode connected to the first power source 
and a second electrode from which a signal responsive to the input signal 
is derived to be supplied to the desired circuit; a first constant current 
source connected between the second electrode of the buffer transistor and 
the second power source as a current load; a third power source connected 
to the first constant current source as a reference for defining a current 
flowing in the first constant current source; and a clamp circuit for 
clamping a potential of the second electrode of the buffer transistor or a 
control electrode or the base of the buffer transistor at a predetermined 
potential level. 
Accordingly, it is an object of the present invention to provide an input 
buffer circuit employed for a semiconductor integrated circuit device, 
which causes no change in value of current flowing to a constant current 
source even if the input buffer circuit is used under condition that its 
input terminal is opened, so that an internal circuit is subjected to no 
potential deviation to perform stable operation. 
These and other objects, features, aspects and advantages of the present 
invention will become more apparent from the following detailed 
description of the present invention when taken in conjunction with the 
accompanying drawings.

DESCRIPTION OF THE PREFERRED EMBODIMENTS 
FIG. 3 is a circuit diagram showing an embodiment of an input buffer 
circuit according to the present invention. The circuit is formed as a 
semiconductor integrated circuit device. This embodiment is different from 
the conventional ECL circuit of FIG. 1 in such a point that a clamp 
circuit 11 is connected to an emitter of a transistor Q.sub.1, for 
clamping the emitter potential of the transistor Q.sub.1 at a 
predetermined potential level. The clamp circuit 11 is formed by a 
transistor Q.sub.6 and a constant voltage source 12. The transistor 
Q.sub.6 is a clamp NPN transistor, which has a base connected to the 
constant voltage source 12, a collector connected to a first power supply 
line 4 and an emitter connected to the emitter of the transistor Q.sub.1 
respectively. An output potential of the clamp circuit 11, i.e., the 
emitter potential of the transistor Q.sub.6 is set at a level lower than a 
low-level signal which may be received in an input terminal 3, to exert no 
influence on output. 
Operation of the circuit is the aforementioned structure will now be 
described. When a high-level or low-level signal is inputted in the input 
terminal 3, only the transistor Q.sub.1 conducts while the transistor 
Q.sub.6 enters a nonconducting state since the transistors Q.sub.1 and 
Q.sub.6 form an ECL differential pair. Thus, the operation in this case is 
similar to that of the conventional ECL circuit shown in FIG. 1. 
When the input terminal 3 is opened, the transistor Q.sub.1 is made 
nonconductive while the transistor Q.sub.6 is made conductive, whereby the 
emitter potential of the transistor Q.sub.1 is clamped at the output 
potential of the clamp circuit 11. Therefore, constant current I.sub.0 to 
a constant current source circuit 2 is supplied through the transistor 
Q.sub.6. Thus, assuming that the grounded emitter current amplification 
factor of a transistor Q.sub.2 is 100, current of I.sub.0 /100 is supplied 
to the base of the transistor Q.sub.2 from a reference circuit (not shown) 
which is connected to a reference voltage input terminal 5, similarly to 
the case of inputting a high-level or low-level signal in the input 
terminal 3, even if the input terminal 3 is opened. Thus, base current of 
the transistor Q.sub.2, which is load current of the reference circuit, is 
not changed even if the semiconductor integrated circuit device is used 
under the condition that the input terminal 3 is opened. Therefore, 
reference voltage inputted in the reference voltage input terminal 5 is 
not changed but remains constant, whereby current values of all constant 
current source circuits, including a constant current source circuit 10, 
to which the reference voltage is applied, remain constant. As the result, 
the semiconductor integrated circuit device can be stably operated with no 
regard to the state of connection of the input terminal 3. 
Also when the constant current source circuit 2 shown in FIG. 3 is 
implemented by a current mirror circuit (FIG. 12) which is similar to that 
shown in FIG. 2, the emitter voltage of the transistor Q.sub.1 is clamped 
at the output voltage of the clamp circuit 11 if the input terminal 3 is 
opened. Thus, the base potential of the transistor Q.sub.2 is not changed 
since the current I.sub.0 flows in the transistor Q.sub.2 even if the 
input terminal 3 is opened. As the result, the current value of the 
constant current source 10, receiving the anode potential of the diode 
D.sub.1 as reference voltage, is not changed and remains constant, whereby 
the semiconductor integrated circuit device can be stably operated with no 
regard to the state of connection of the input terminal 3. 
FIG. 4 is a circuit diagram showing exemplary structure of the constant 
voltage source 12 in the above embodiment. Referring to FIG. 4, the 
constant voltage source 12 is formed by a constant current source circuit 
consisting of a resistor R.sub.4 and a transistor Q.sub.7, and a resistor 
R.sub.5. The transistor Q.sub.7 has a base connected to a reference 
voltage input terminal 5, an emitter connected to a second power supply 
line 6 through the resistor R.sub.4 and a collector connected to the base 
of the transistor Q.sub.6 as well as to a first power supply line 4 
through the resistor R.sub.5. In this case, current flowing in the 
resistor R.sub.5 can be made constant by the constant current source 
circuit formed by the reference voltage input terminal 5, the transistor 
Q.sub.7 and the resistor R.sub.4. Thus, a voltage drop at the resistor 
R.sub.5 can be made constant and the base voltage of the transistor 
Q.sub.6 can be maintained constant, to attain an effect similar to that of 
the above embodiment. Further, the resistor R.sub.5 may be replaced by a 
diode series circuit or a series circuit of a diode and a resistor. 
FIG. 5 is a circuit diagram showing still another embodiment of the present 
invention. While the clamp circuit 11 is formed by the transistor Q.sub.6 
and the constant voltage source 12 in each of the embodiments shown in 
FIGS. 3 and 4, a clamp circuit 11 is formed by a diode series circuit in 
the embodiment shown in FIG. 5. In this diode series circuit, an anode is 
connected to a first power supply line and a cathode is connected to an 
emitter of a transistor Q.sub.1. When an input terminal 3 is opened, the 
diode series circuit is turned on so that emitter voltage of the 
transistor Q.sub.1 can be clamped at a predetermined potential level by a 
voltage drop of the diodes, to thereby attain an effect similar to those 
of the aforementioned embodiments. The diode series circuit may be 
replaced by a series circuit of a diode and a resistor. 
Although the clamp circuit 11 is connected to the emitter of the transistor 
Q.sub.1 so that the constant current I.sub.0 flows in the constant current 
circuit 2 with no regard to the input state of the input terminal 3 in 
each of the aforementioned embodiments, a similar effect can also be 
attained by connecting a clamp circuit 11 to the base of a transistor 
Q.sub.1, as shown in FIG. 6. In this case, the potential of a constant 
voltage source 12 is set at a level lower than a low level of an input 
signal, to exert no influence on output when a high-level or low-level 
signal is received in the input terminal 3. When the input terminal 3 is 
opened, the base potential of the transistor Q.sub.1 is clamped at the 
output potential of the clamp circuit 11. Therefore, the transistor 
Q.sub.1 maintains its conducting state and constant current I.sub.0 to a 
constant current source circuit 2 is supplied from a first power supply 
line 4, to attain an effect similar to those of the aforementioned 
embodiments. 
The constant voltage source 12 in FIG. 6 may be formed by resistors R.sub.4 
and R.sub.5 and a transistor Q.sub.7, as shown in FIG. 7, in a similar 
manner to that shown in FIG. 4. Further, the clamp circuit 11 in FIG. 6 
may be formed by a diode series circuit, as shown in FIG. 8, in a similar 
manner to that shown in FIG. 5. 
Although the present invention has been described and illustrated in 
detail, it is clearly understood that the same is by way of illustration 
and example only and is not to be taken by way of limitation, the spirit 
and scope of the present invention being limited only by the terms of the 
appended claims.