Resistive random access memory and fabrication method thereof

A resistive random access memory (RRAM) unit includes at least one bit line extending along a first direction, at least one word line disposed on a substrate and extending along a second direction so as to intersect the bit line, a hard mask layer on the word line to isolate the word line from the bit line, a first memory cell on a sidewall of the word line, and a second memory cell on the other sidewall of the word line.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to the field of semiconductor memory devices. More particularly, the present invention relates to an improved resistive random access memory (RRAM) device, which utilizes spacer-type resistance layer and top electrode and has a cell size of 2F2. A method of fabricating such RRAM device is also disclosed.

2. Description of the Prior Art

Resistive switching random access memory or RRAM devices have certain beneficial characteristics over other types of memory devices, such as low power consumption, high speed, excellent bit resolution, high degree of scaling of miniaturization, non-volatile, and low cost, and therefore have become a promising next-generation non-volatile memory to replace flash memory.

RRAM may be characterized by a resistor or a resistance layer disposed between a top electrode and a bottom electrode of a storage node, which may be fabricated in a semiconductor pillar structure and stacked with a diode. The resistor may have a current-voltage characteristic which may be varied according to an applied voltage. Once the current-voltage characteristic is varied, the varied current-voltage characteristic of the resistor may be maintained until a reset voltage is applied to the resistor. RRAM devices store data by varying the resistance of the resistor between a high resistance state (HRS) and a low resistance state (LRS), arguably due to the formation/collapse of conduction filaments in the resistance layer. Data may be written to a selected RRAM device by applying a predetermined voltage, at a predetermined polarity, for a predetermined duration. To ensure the stability when operating the RRAM device, it is believed that maintaining a certain amount of the conduction filaments is essential.

It is also believed that, when the RRAM device is operated, the quantity of conduction filaments is proportional to the contact area between the resistance layer and the electrode. As the size of the memory cell shrinks, however, the variation or deviation of the quantity of conduction filaments created during the operation of the RRAM device becomes critical and may significantly influence the device reliability. Accordingly, there is a need in this industry to provide an improved RRAM structure and fabrication method thereof to solve the above-mentioned problems or shortcomings.

SUMMARY OF THE INVENTION

To achieve the above-described purposes, a resistive random access memory (RRAM) device on a substrate is provided according to one embodiment. The RRAM device includes at least one bit line extending along a first direction; at least one word line extending along a second direction and intersecting the bit line; a hard mask layer on the word line to electrically isolate the word line from the bit line; a first memory cell disposed on one sidewall of the word line, the first memory cell comprising a first spacer-type resistance layer, a first top electrode, and a first diode coupled to the first top electrode; and a second memory cell disposed on the other sidewall of the word line, the second memory cell comprising a second spacer-type resistance layer, a second top electrode, and a second diode coupled to the second top electrode.

According to another embodiment, a method of fabricating a resistive random access memory (RRAM) device is disclosed. A plurality of word lines extending along a first direction are formed on a substrate with a recess between the word lines. A spacer-type resistance layer and a top electrode layer are formed on a sidewall of each of the word lines. A photoresist stripe pattern extending along a second direction is then formed on the substrate. The first direction is perpendicular to the second direction. An etching process is performed to remove the top electrode layer and the spacer-type resistance layer not covered by the photoresist stripe pattern to form a plurality of top electrodes. A diode is formed on each of the top electrodes.

DETAILED DESCRIPTION

Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments may be embodied in many different forms and should not be construed as being limited to the example embodiments set forth herein. Example embodiments are provided so that this disclosure will be thorough, and will fully convey the scope to those who are skilled in the art. In some example embodiments, well-known processes, well-known device structures, and well-known technologies are not described in detail to avoid the unclear interpretation of the example embodiments. Throughout the specification, like reference numerals in the drawings denote like elements.

Please refer toFIG. 1andFIG. 2.FIG. 1is a schematic diagram showing a portion of a resistive random access memory (RRAM) array in accordance with one embodiment of this invention.FIG. 2is a schematic, cross-sectional diagram taken along line I-I′ inFIG. 1. As shown inFIG. 1andFIG. 2, the RRAM array1comprises a plurality of bit lines104, for example, BL0˜BL3, extending along a first direction such as the reference x-axis, and a plurality of word lines102, for example, WL0˜WL2, extending along a second direction such as the reference y-axis. The first direction may be perpendicular to the second direction. The word lines102intersect the bit lines104and a memory cell unit10is provided at each cross point.

According to the embodiment of this invention, the word lines102, which extend along the second direction, are formed on a surface of a base layer or substrate101with a pitch of 2F, where F is the minimum feature size or line width. According to the embodiment of this invention, the word lines102may comprise metal such as titanium nitride (TiN), but not limited thereto. A hard mask layer103such as silicon nitride may be provided on each of the word lines102. The hard mask layer103insulates the word lines102from the overlying bit lines104extending along the first direction.

According to the embodiment of this invention, the memory cell unit10at each cross point of the word lines102and bit lines104comprises two memory cells110aand110b, which are formed on two opposite sidewalls of the word line102such as WL1. For example, the memory cell110acomprises a spacer-type resistance layer120aand a spacer-type top electrode130aon the left side of WL1, and the memory cell110bcomprises a spacer-type resistance layer120band a spacer-type top electrode130bon the right side of WL1, thereby forming a dual spacer configuration on either sidewall of the word line. The word line102acts as a bottom electrode of each memory cell. Therefore, a minimum cell size of 2F2can be achieved.

According to the embodiment of this invention, the spacer-type resistance layers120aand120bare both in direct contact with the word line102. The top electrodes130aand130bare in direct contact with the resistance layers120aand120brespectively. It is noteworthy that the spacer-type resistance layers120aand120bmust cover the entire sidewall surface and may slightly extend upward to cover a portion of the hard mask layer103. This avoids the direct contact between the top electrode130a,130band the word line102.

InFIG. 1, according to the embodiment of this invention, the exemplary spacer-type resistance layer120a,120bis continuous and extends along the second direction on either sidewall of the word line102. The top electrode130a,130bis non-continuous and segmented. However, it is to be understood that the spacer-type resistance layer120a,120bmay be non-continuous and segmented in another embodiment.

According to the embodiment of this invention, the spacer-type resistance layer120a,120bmay comprise hafnium dioxide (HfO2), but not limited thereto. It is to be understood that the spacer-type resistance layer120a,120bmay comprise other resistance change materials such as ZrO2, TiO2, CuxO, or Al2O3among others. According to the embodiment of this invention, the top electrodes130aand130bmay comprise TiN, but not limited thereto. When choosing the suitable material for the top electrodes130aand130b, the proper metal work function may be taken into account so as to form NP diode and PN diode on two opposite sides of the word line102.

As shown inFIG. 2, according to the embodiment of this invention, the memory cell110afurther comprises an NP diode140athat is electrically coupled to the top electrode130a, and the memory cell110bfurther comprises a PN diode140bthat is electrically coupled to the top electrode130b. According to the embodiment of this invention, NP diode140aand PN diode140bmay be a metal-tunnel oxide diode, metal diode or metal oxide diode.

By way of example,FIG. 16andFIG. 17show exemplary RRAM structure with metal diode and metal oxide diode respectively. As shown inFIG. 16, a boron-aluminum (B—Al) metal442ais formed on the left side of WL1, while on the right side of WL1, a phosphorus-aluminum (P—Al) metal442bis formed. As shown inFIG. 17, composite metal oxide including titanium oxide (TiO)542aand nickel oxide (NiO)541ais formed on the left side of WL1thereby forming an NP metal oxide diode, while composite metal oxide including nickel oxide (NiO)542band titanium oxide (TiO)541bis formed on the right side of WL1thereby forming a PN metal oxide diode.

InFIG. 2, a metal-tunnel oxide diode structure is shown. The NP diode140acomprises a tunnel oxide layer141covering the top electrode130a, and a platinum (Pt) layer142a. The PN diode140bcomprises the tunnel oxide layer141covering the top electrode130b, and a hafnium (Hf) layer142b. The tunnel oxide layer141, the Pt layer142aand the Hf layer142bconformally covers the recess between the word lines102, and cover a portion of the substrate101. According to the embodiment of this invention, the tunnel oxide layer141may have a thickness of about 6 nm, but not limited thereto. A contact layer170such as tungsten (W) is provided on the Pt layer142aand the Hf layer142b. The contact layer170fills the recess between the word lines102and is electrically connected to the bit line104such as BL0. Going into detail, an N electrode (Pt layer) of the NP diode140ais coupled to the bit line104through the contact layer170, and a P electrode (Hf layer) of the PN diode140bis coupled to the bit line104through the contact layer170.

FIG. 3is an exemplary circuit diagram of the RRAM array according to the embodiment of this invention. By way of example, inFIG. 3, the memory cell unit10comprises two memory cells110aand110b, which are electrically coupled to the bit line104such as BL0(indicated by dashed line) through the NP diode140aand PN diode140brespectively. On the other hand, the spacer-type resistance layers120aand120bof the memory cells110aand110brespectively are directly connected to the word line102such as WL1. It can be seen fromFIG. 3that the NP diode140aand the PN diode140bcoupled to each bit line104are arranged in an inverted configuration. However, it is to be understood that in other cases the two diodes may be unidirectional and is not arranged in such inverted configuration.

FIG. 4is a perspective view of the memory cell unit10. The present invention features a minimum memory cell size of 2F2by forming two memory cells110aand110bon two opposite sidewalls of the word line102. With the scaling of the memory cell unit10due to the improvement of the semiconductor fabrication techniques, an effective surface area A (A=F×Z) can be still maintained by adjusting the thickness Z of the word line102. As previously described, when the RRAM device is operated, the quantity of conduction filaments is proportional to the contact area A between the resistance layer and the electrode. By adjusting the thickness Z of the word line102, the influence of the variation of the conduction filaments can be eliminated or alleviated, thereby solving the reliability issue.

FIG. 5AandFIG. 5Bdepict exemplary methods for operating the RRAM array inFIG. 3. By way of example, as shown inFIG. 5A, to write the right side memory cell110b′ of the memory cell unit10′ at the cross point of the word line WL0and the bit line BL2, a 1.5V voltage is applied to WL0, a 0V voltage is applied to BL2, such that the PN diode140b′ is forward biased to conduct current, while the NP diode140a′ is not in a conducted state. A 0.7V voltage is applied to other word lines. A 0.7V voltage is applied to other bit lines. As shown inFIG. 5B, to write the left side memory cell110a′ of the memory cell unit10′ at the cross point of the word line WL0and the bit line BL2, a 0V voltage is applied to WL0, a 1.5V voltage is applied to BL2, such that the NP diode140a′ is forward biased to conduct current, while the PN diode140b′ is not in a conducted state. Likewise, a 0.7V voltage is applied to other word lines. A 0.7V voltage is applied to other bit lines. It is to be understood that the above voltages are exemplary and are provided only for the purpose of illustration.

A detail description of the fabrication process for forming the RRAM device will now be provided below in accompany withFIG. 6toFIG. 15.

As shown inFIG. 6, a substrate101is provided. The substrate101may be a semiconductor substrate or a substrate having thereon an inter-metal dielectric film. For example, the substrate101may be a substrate having thereon an inter-metal dielectric film and a peripheral circuit has been fabricated in a front end process and covered by the inter-metal dielectric film. The RRAM device is fabricated directly on the inter-metal dielectric film. A word line material layer102′ and a hard mask material layer103′ are deposited on the substrate101. A photoresist dense line pattern210with a pitch of 2F and L (line width):S (space)=1:1 is then provided on the hard mask material layer103′.

As shown inFIG. 7, an etching process is carried out to trim and modify the thickness of the photoresist dense line pattern210such that the line width L is reduced and the space S is increased. As shown inFIG. 8andFIG. 8A, a dry etching process is performed to remove the hard mask material layer103′ and the word line material layer102′ not covered by modified the photoresist dense line pattern210, thereby forming a plurality of word lines102such as WL0˜WL2. The modified the photoresist dense line pattern210is then stripped. The hard mask layer103is remained on the word lines102.

As shown inFIG. 9, subsequently, a spacer-type resistance layer120a,120band top electrode130a,130bare formed on either sidewall of the word line102and hard mask layer103. To form the spacer-type resistance layer120a,120band top electrode130a,130b, a deposition method and self-aligned anisotropic etching process may be used, which are well-known in the art and the details are therefore omitted. The spacer-type resistance layer120a,120bmay comprise HfO2, ZrO2, TiO2, CuxO, Al2O3or the like. The top electrode130a,130bmay comprise TiN, but not limited thereto.

As shown inFIG. 10, a photoresist pattern220is formed on the substrate101. The photoresist pattern220is stripe pattern extending along the reference x-axis, which intersects the word lines102and defines the position of the memory cells. As shown inFIG. 11, using the photoresist pattern220as an etch hard mask, a dry etching process is performed to remove the top electrode130a,130bnot covered by the photoresist pattern220to thereby define the memory cells110aand110bon two opposite sidewalls of the word line102. At this point, the spacer-type resistance layer120a,120bmay remain continuous, not segmented, and extends along the reference y-axis.

Subsequently, the diode elements are fabricated. As shown inFIG. 12andFIG. 12A, for example, the recess between the word lines102is filled with a dielectric layer302. A photoresist pattern230is then formed. The photoresist pattern230has a plurality of openings230athat reveal odd columns of the dielectric layer302embedded in the recesses between the word lines102. The exposed dielectric layer302is then removed through the openings230a. Thereafter, a tunnel oxide layer141is formed in the recesses.

As shown inFIG. 13, a Pt layer142aand contact layer170such as a tungsten layer are filled into the odd-column recesses between the word lines102. A planarization process such as a chemical mechanical polishing (CMP) process may be performed to remove excess Pt layer142aand contact layer170.

As shown inFIG. 14, the steps as described inFIG. 12,FIG. 12AandFIG. 13are repeated to form the tunnel oxide layer141, Hf layer142band contact layer170in the even-column recesses between the word lines102. The excess Hf layer142band contact layer170are then removed using planarization process such as a CMP process. As shown inFIG. 15, a plurality of bit lines104are formed and the Pt layer142aand Hf layer142bare electrically connected to the bit line104through the contact layer170.

According to the above-described embodiment, Pt layer142aand Hf layer142bare formed respectively on the left sidewall and light sidewall, thereby forming two diodes arranged in an inverted configuration. Therefore, the two memory cells on two opposite sidewalls of the word line can be operated independently. However, it is understood that in other embodiments the sidewalls of the word line may be covered with the same metal material to form two identical diodes, for example, two NP diodes or two PN diodes. In this case, the two memory cells on two sidewalls of the word line will be operated concurrently.