Bit-width minimization scheme for wireless communication

A technique for generating a reduced bit-width in a signal generated by a first-type modulator in a communication apparatus that includes two distinct modulators. In particular, the communication apparatus includes a first modulator adapted to generate a first modulated signal quantified to a first bit-width, a second modulator adapted to generate a second modulated signal quantified to a second bit-width that is less than the first bit-width, and a device to generate a third modulated signal comprising a combination of the first and second modulated signals. In an exemplary implementation, the first modulator includes an OFDMA modulator, the second modulator includes a CDMA, and the combining device includes an IFFT. Additionally, an apparatus for processing a communication signal includes a tasklist cache memory having a tasklist, a processor adapted to provide a task to the tasklist, and a communication module adapted to fetch the task from the tasklist, and process the communication signal based on the retrieved task.

BACKGROUND

A MIMO system supports a time division duplex (TDD) and frequency division duplex (FDD) systems. In a TDD system, the forward and reverse link transmissions are on the same frequency region so that the reciprocity principle allows the estimation of the forward link channel from the reverse link channel. This enables the access point to extract transmit beamforming gain on the forward link when multiple antennas are available at the access point.

DESCRIPTION

Single carrier frequency division multiple access (SC-FDMA), which utilizes single carrier modulation and frequency domain equalization is a technique. SC-FDMA has similar performance and essentially the same overall complexity as those of OFDMA system. SC-FDMA signal has lower peak-to-average power ratio (PAPR) because of its inherent single carrier structure. SC-FDMA has drawn great attention, especially in the uplink communications where lower PAPR greatly benefits the mobile terminal in terms of transmit power efficiency. It is currently a working assumption for uplink multiple access scheme in 3GPP Long Term Evolution (LTE), or Evolved UTRA.

Referring toFIG. 1, a multiple access wireless communication system according to one embodiment is illustrated. A access point100(AP) includes multiple antenna groups, one including104and106, another including108and110, and an additional including112and114. InFIG. 1, only two antennas are shown for each antenna group, however, more or fewer antennas may be utilized for each antenna group. Access terminal116(AT) is in communication with antennas112and114, where antennas112and114transmit information to access terminal116over forward link120and receive information from access terminal116over reverse link118. Access terminal122is in communication with antennas106and108, where antennas106and108transmit information to access terminal122over forward link126and receive information from access terminal122over reverse link124. In a FDD system, communication links118,120,124and126may use different frequency for communication. For example, forward link120may use a different frequency then that used by reverse link118.

Each group of antennas and/or the area in which they are designed to communicate is often referred to as a sector of the access point. In the embodiment, antenna groups each are designed to communicate to access terminals in a sector of the areas covered by access point100.

In communication over forward links120and126, the transmitting antennas of access point100utilize beamforming in order to improve the signal-to-noise ratio of forward links for the different access terminals116and124. Also, an access point using beamforming to transmit to access terminals scattered randomly through its coverage causes less interference to access terminals in neighboring cells than an access point transmitting through a single antenna to all its access terminals.

An access point may be a fixed station used for communicating with the terminals and may also be referred to as an access point, a Node B, or some other terminology. An access terminal may also be called an access terminal, user equipment (UE), a wireless communication device, terminal, or some other terminology.

FIG. 2is a block diagram of an embodiment of a transmitter system210(also known as the access point) and a receiver system250(also known as access terminal) in a MIMO system200. At the transmitter system210, traffic data for a number of data streams is provided from a data source212to a transmit (TX) data processor214.

At transmitter system210, the modulated signals from receiver system250are received by antennas224, conditioned by receivers222, demodulated by a demodulator240, and processed by a RX data processor242to extract the reverse link message transmitted by the receiver system250. Processor230then determines which pre-coding matrix to use for determining the beam forming weights then processes the extracted message.

In modern communication systems, under the UMB standard as one of several possible examples, there has been the requirement of transmitting a CDMA segment with the OFDMA transmission. The composite waveform from both the CDMA and the OFDMA segments generally go through an IFFT transformation before getting up-sampled and transmitted over the air. This composite waveform at the IFFT input generally has a large dynamic range and hence requires a certain bit-width for signal representation. The understanding of related approaches is that a fixed allocation of a 16 bit width per CDMA and per OFDMA is to be used.

However, in evaluation of the CDMA portion of the composite waveform, it has been found that the dynamic range of the CDMA portion is smaller than the dynamic range of the OFDMA segment. Also, it has been found that the relative strengths of the CDMA and OFDMA waveforms are known at the transmitter. Taking these two observations into consideration, an overall composite waveform with a reduced bit-width CDMA segment can be generated.

Specifically, based on studies performed, the overall dynamic range for the composite waveform has been evaluated to be approximately 63 dB. This translates to approximately 12 bits (11 bits for range and 1 bit for sign) at the IFFT input. Given a possible Gaussian probability distribution function for the time-domain waveform, additional bits are added, resulting in an overall bit length of approximately 14 bits.

It is apparent, therefore, that 14 bits are less than the 16 bits/CDMA+16 bits/ODFMA described above. Because of the reduced bit width it is possible to use less bits in hardware (e.g., cheaper hardware and/or faster hardware), resulting in improved cost and/or performance efficiencies. It should be noted, however, that though 14 bits has been found to be appropriate for the studies performed, more or less bits may be used, depending on the type of study performed, as well as design and performance objectives. For example, though a reduced bit computation was based on the overall dynamic range of the composite waveform, it is possible to modify the disclosed process to arrive at a reduced bit width by allocating reduced bits only to the CDMA portion of the composite signal. It is noted that the bit-width for the CDMA portion of the signal is usually less than the bit-width for the OFDMA portion of the signal. Also, conceivably any loss in resolution or quantization caused by the use of reduced bits may be isolated to the CDMA portion of the signal or vice versa, to the OFDMA portion of the signal, as according to design preference. Thereby, by determining the sensitivity of the signal waveform to degradation of the CDMA or OFDMA due to the reduced bit allocation, adjustments may be made to the bit width or to the portion of the signal that it is applied to.

FIG. 3is a block diagram300of a transmit data path and the respective bit widths for an exemplary reduced bit scheme. The transmit data path is shown with a modulator block302, an IFFT block350, and associated blocks360, with a DAC block370. The modulator block302contains OFDMA related blocks and CDMA related blocks.

The OFDMA related blocks are the interleaver random access memory (IRAM) data channel (DCH)304, a Symbol Mapper & Data Scrambler306, a dedicated pilot channel (DPICH) Pilot Generator308, a Cell/Sector Scrambler310, and an Applying Power Gain block312. The IRAM (DCH)304codes and interleaves traffic data. The Symbol Mapper & Data Scrambler306generates symbols from the coded and interleaved bits received from the IRAM (DCH)306, and performs a predetermined scrambling of the symbols. The DPICH pilot generation308generates symbols for the pilot channel. The Cell/Sector scrambler310performs a predetermined scrambling of the pilot symbols. And, the Applying Power Gain combines and amplifies the symbols from the Symbol Mapper & Data Scrambler306and Cell/Sector Scrambler310. It shall be understood that the OFDMA portion may be configured differently.

As can be seen from the outputs of the Symbol Mapper & Data Scrambler306and the Cell/Sector Scrambler310, the bit width is designated S1.7, where “S” represents a signed value, the “1” represents the number for integer values, and “7” represents the number for decimal values. The Applying Power Gain312applies a gain factor having a bit width of S7.4 to the outputs of the Symbol Mapper & Data Scrambler306and the Cell/Sector Scrambler310. Therefore, S7.4 represents 12 bits (1 for sign, 7 for integer, and 4 for decimal). The output of the Applying Power Gain block312is shown having 14 bits (S7.6). As stated above, it is noted that the bit-width for the CDMA portion of the signal is usually less than the bit-width for the OFDMA portion of the signal.

The CDMA related blocks contain a plurality of reverse link control channels RLCC #N316to RLCC #1318blocks having 2 bits (S1.0) coupled to the Applying Power Gain block320. The applied power signals are added by the Adder322and then a Fast Fourier Transfer (FFT) is performed by the FFT block324. It shall be understood that the CDMA portion may be configured differently.

The bit width after the FFT block324is designated as 10 (S3.6). The outputs of the CDMA related blocks and the OFDMA related blocks are inputs to the IFFT block350to generate a value represented by 14 bits (S7.6). It is noted that the IFFT block350is illustrated as having 4096 points. Of course, less or more points may be used, if desired. From the IFFT block350, the signal proceeds through various other devices/processes where it is upsampled/interporlated resulting in a bit width of 12 (S7.4) The resulting bit-width represented signal is then converted into an analog signal via the 12-bit DAC370for further operation or transmission.

More specifically, the associated blocks360includes a transmitter (Tx) automatic gain control (AGC)360-1to boost the power of the output of the IFFT350to a predetermined level. The associated blocks360also includes a cyclic prefix (CP) insertion and window360-2to add a cyclic prefix and windowing to the output of the TX AGC360-1to reduce intersymbol interference and smooth the output waveform. The associated blocks360further includes an overlap & add360-3to further smooth the output waveform. The associated blocks360further includes a time and frequency correction360-4to perform correction of the time and frequency of the output waveform. The associated blocks360further includes an upsampler/interpolator to upconvert the signal to a higher frequency (e.g., from 40 MHz to 160 MHz). It shall be understood that the associated blocks360may be configured differently. The output of the associated blocks360is coupled to a digital-to-analog converter (DAC), which converts the output signal into an analog signal for transmission.

It should be understood that while the above example provided definitive bit width assignment values during the various stages of the data path, these assignment values may be adjusted according to the design chosen, the hardware used, the performance objectives desired, etc. Therefore, the values determined inFIG. 3, though applicable to the system shown, may accordingly be changed.

Although in the above example, the system300has been described with reference to setting the respective bit-widths of CDMA and OFDMA signals and combining the signals, it shall be understood that the system300is applicable to setting the bit-widths of two or more distinct modulation signals, and combining the two or more distinct modulations signals.

FIG. 4is a block diagram of another exemplary communication system400in accordance with another embodiment of the invention. In summary, the communication system400implements a unique technique for providing tasks to communication hardware (HW) for execution thereof. In particular, a processor writes tasks for the communication hardware (HW) to a tasklist cache memory (TCM). The communication hardware (HW), in turn, fetches the tasks from the tasklist cache memory (TCM), and then executes the tasks based on one or more timing parameters. Thus, instead of the processor having direct access to the communication hardware (HW), the processor instructs the communication hardwave (HW) via the cache memory. This improves processor performance and efficiency.

More specifically, the communication system400comprises a processor402, a tasklist cache memory (TCM)404including one or more tasklists406-1,406-2, etc., a processor bus408, a TCM bus410, and communication hardware (HW)411. The communication hardware (HW)411, in turn, comprises a processor bus interface412, a TCM bus interface414, a real time clock (RTC)416, and one or more communication modules430-1,430-2, etc. The RTC416, in turn, comprises an RTC counter422, one or more reference value storing units418-1to418-N, and one or more comparators (CMP)420-1to420-N.

Each communication module (430-1,430-2) comprises a task manager (431-1,432-2), a task FIFO (434-1,434-2), a hardware block (436-1,436-2), a processor interface (438-1,438-2), one or more registers (440-1,440-2), a push direct memory access (DMA) (442-1,442-2), a memory arbiter (444-1,444-2), and a static random access memory (446-1,446-2). The hardware block (436-1,436-2) may be any device of a communication system, such as those described with reference toFIGS. 2-3.

A summary of the operation is now provided. The processor402writes tasks for the communication modules430-1and430-2in respective tasklists406-1and406-2of the tasklist cache memory (TCM)404. If any of these tasks requires execution by a certain time, the processor402also writes the timing information to one or more of the reference value storing units418-1to418-N of the RTC416via the processor bus408and the processor bus interface412. The communication modules430-1and430-2fetches the tasks from the respective tasklists406-1and406-2of the tasklist cache memory (TCM)404via the TCM bus410and TCM bus interface414.

In particular, the task manager (432-1,432-2) of each communication module (430-1,430-2) performs the fetching of the tasks. Once the task manager (432-1,432-2) fetches the tasks, it provides it sequentially to the task FIFO (434-1,434-2). The hardware block (436-1,436-2), in turn, fetches the tasks from the TASK FIFO (434-1,434-2), populates the registers (440-1,440-2) according to the tasks, and executes the tasks. If the processor402needs to be notified of the completion of a task, the hardware block (436-1,436-2) sends an interrupt to the processor402via the processor interface (438-1,438-2), the processor bus interface412, and the processor bus408. If the hardware block (436-1,436-2) generates data, the data may be sent to the SRAM (446-1,446-2) for storage via the memory arbiter (444-1,444-2). If the processor402needs to obtain access to the data, the data may be pushed to the tasklist cache memory (TCM)404by the push DMA (442-1,442-2) via the TCM bus interface414and TCM bus410. If necessary, the processor402may also obtain access to the register (440-1,440-2) and/or communicate directly with the hardware block (436-1,436-2) via the processor bus408, processor bus interface412, and processor interface (438-1,438-2). The following describes particular methods implemented in the communication system400.

FIG. 5is a flow diagram of an exemplary method500of providing tasks for communication hardware (HW) in accordance with another embodiment of the invention. According to the method500, the processor402starts by performing an initialization procedure by disabling the hardware blocks (436-1,436-2, etc.) (block502). The processor402continues the initialization procedure by allocating memory for the one or more tasklists406-1,406-2, etc., in the tasklist cache memory (TCM)404(block504).

Then, according to the initialization procedure, the processor402initializes the respective start and end addresses TL_START_ADDR and TL_END_ADDR and the respective write and read pointers TL_WR_PTR and TL_RD_PTR of the tasklists406-1,406-2(block506). As an example, the processor402initializes the start address TL_START_ADDR at the top or beginning of the corresponding tasklist. The processor402initializes the end address TL_END_ADDR at the bottom or end of the corresponding tasklist. The processor402also initializes the write and read pointers TL_WR_PTR and TL_RD_PTR at the top or beginning of the corresponding tasklist. The processor402then completes the initialization procedure by enabling the hardware blocks (block508). The processor402then writes a task into the corresponding address of the tasklist indicated by the write pointer TL_WR_PTR (block510). The processor402then advances the write pointer TL_WR_PTR to the next address of the tasklist (block512). The processor402then repeats the operations of blocks510and512to add additional tasks for the corresponding communication module.

FIG. 6is a flow diagram of an exemplary method600of obtaining tasks for communication hardware (HW) in accordance with another embodiment of the invention. According to the method600, the task manager (432-1,432-2) of the corresponding communication module (430-1,430-2) determines whether the write pointer TL_WR_PTR points to the same address of the task list (406-1,406-2) to which the read pointer TL_RD_PTR points (block602). If the task manager (432-1,432-2) determines that the read and write pointers are pointing to the same address, the task manager continues to make the same determination in block602. If the task manager (432-1,432-2) determines that the read and write pointers are not pointing to the same address, the task manager then determines whether the corresponding task FIFO (434-1,434-2) is full (block604). If the task manager (432-1,432-2) determines that the task FIFO is full, the task manager continues to make the same determination in block604.

If the task manager (432-1,432-2) determines that the task FIFO is not full, the task manager fetches a task from the corresponding tasklist (406-1,406-2) (block606). The task manager (432-1,432-2) then pushes the task into the corresponding task FIFO (434-1,434-2) (block608). The task manager (432-1,432-2) then advances the corresponding read pointer TL_RD_PTR to the next address of the corresponding tasklist (406-1,406-2). The task manager (432-1,432-2) then returns back to operation specified in block602, and repeats the process for the next task.

FIG. 7is a flow diagram of an exemplary method700of executing tasks by hardware block in accordance with another embodiment of the invention. According to the method700, the hardware block (436-1,436-2) fetches a task from the corresponding task FIFO (434-1,434-2) (block702). The hardware block (436-1,436-2) then determines the timing status of the task execution (block704). For example, the retrieved task could be executed immediately, or based on the RTC416, or based on an event that occurred in the corresponding hardware block (436-1,436-2), or based on a software event running on the processor402. The hardware block (436-1,436-2) then executes the task according to the timing status (block706).

After completing the task, the hardware block (436-1,436-2) determines whether the processor402is to be notified of the completion of the task (block708). If the hardware block (436-1,436-2) determines that the processor402is to be notified, the hardware block sends a notification (e.g., an interrupt) to the processor402via the corresponding processor interface (438-1,438-2), processor bus interface412, and processor bus408(block712). The hardware block (436-1,436-2) then determines whether the processor402needs to receive the data generated by executing the task (block710). If the hardware block (436-1,436-2) determines that the processor402needs the task data, the hardware block sends the data to the processor402via the corresponding push DMA (442-1,442-2, the TCM bus interface414, TCM bus410, and the tasklist cache memory (TCM)404(block714), and then continues to block702to fetch another task from the task FIFO. If the hardware block (436-1,436-2) determines that the processor402does not need the task data, the hardware block continues to block702to fetch another task from the task FIFO.

Those of skill in the art would understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, changes in energy states, or any combination thereof.