Method for designing minimal cost, timing correct hardware during circuit synthesis

A method of considering circuit timing requirements during the circuit design process, comprising receiving a clock cycle-time constraint; receiving delay characteristics of hardware resources from a macrocell library; receiving an operation, an alternative clock cycle associated with said operation and an alternative hardware resource associated with said operation; and determining validity of the received alternative with respect to timing constraints using a hardware structural representation of the program graph.

FIELD OF THE INVENTION

The present invention is directed to digital circuit synthesis, and, in particular, to improving the quality of digital circuits produced by high-level synthesis by incorporating timing analysis considerations.

BACKGROUND

The combination of continuing advances in technology and reduced production costs have led to a proliferation of electronic devices that incorporate or use advanced digital circuits. These electronic devices include both traditional electronic devices such as desktop computers, laptop computers, hand-held computing devices, such as Personal Digital Assistants (PDAs) and hand-held computers, as well as non-traditional devices such as cellular telephones, printers, digital cameras, facsimile machines, and household and business appliances. The digital circuits included in these electronic devices may be used to provide the basic functionality of the electronic devices or may be used to provide additional, desirable features.

For each of these electronic devices it is desirable to reduce the overall cost of the device. This reduction in cost may be accomplished by reducing the cost of the digital circuits incorporated into the device. The cost of the digital circuits may be reduced by reducing the amount of silicon used to fabricate each digital circuit. However, it is important that the digital circuit still meet the appropriate functional and performance requirements. Performance requirements are expressed as a combination of several metrics: throughput (number of tasks executed per clock cycle), latency (number of clock cycles to complete a single task), and clock speed.

Given a functional and performance requirement, synthesis approaches typically try to design a digital circuit with the required functionality that has minimal cost and still meets the performance requirements.FIG. 1is a block diagram of a typical process for the high-level synthesis of digital circuits. As illustrated, the design process takes as input functional specification101of the application and desired performance requirement102and performs a number of steps including: analysis, transformations and optimizations step103, storage determination step104, functional unit allocation step105, operation scheduling and resource binding step106, and hardware synthesis step107. The structural Register-Transfer-Level (RTL) description of the circuit is then produced as output108.

The functional specification input101is a high level specification that expresses the behavior of the application. It is usually an executable program in a language that the high-level synthesis process understands. If it is a textual document, then the equivalent executable code may need to be written for the purposes of synthesis. The performance requirement102represents the throughput, latency, clock speed, etc. required of the synthesized digital circuit.

The program is analyzed and transformed in step103to expose opportunities for meeting the desired performance and for cost reduction. This includes techniques to exploit parallelism at the task-level, interation-level, and instruction-level, and other traditional compiler optimizations like common sub-expression elimination, dead code elimination, etc.

In step104, storage is determined for the variables in the program. Data structures contained in the program may be mapped to global memory while others may be mapped to local memory or possibly to internal registers.

In step105, functional units are allocated for the operations in the transformed and optimized program. Program operations may include, but are not limited to, additions, subtractions, multiplication, division, etc. A functional unit (FU) refers to components such as adders, multipliers, load-store units and similar components. Each of these functional units is capable of executing one or more type of operations. Allocating functional units entails the process of allocating a minimal-cost set of hardware components that can execute the operations in the program graph and meet the required performance. For example, given a program with additions, subtractions, multiplications, memory loads, and memory stores, step105may allocate two multiply-adders, three subtractors, and one load-store functional unit.

Operation scheduling and resource binding are performed in step106. Operation scheduling involves assigning the start of each operation to a specific clock cycle. For example, an add operation may be assigned to start executing on clock cycle number23. Resource binding entails selecting, for each operation, a specific functional unit to be used for its execution. For example, in allocating functional units step105, a determination may have been made that two adders, ADDER1and ADDER2, are required to be included in the circuit design. In resource binding step106, a particular addition operation may be bound to ADDER1, i.e., it is assigned to execute on ADDER1.

Typically, unscheduled operations (operations that have not been associated with a clock cycle and a functional unit) are addressed in some order that is either pre-assigned or is dynamically determined during scheduling. Once an unscheduled operation is selected, several alternatives are considered for scheduling and binding this operation. An alternative refers to a specific clock cycle and functional unit that this operation can be scheduled and bound on. The alternatives for an unscheduled operation are derived by determining the available clock cycles and functional units to execute this operation. For example, if there are three possible clock cycles and two possible adder functional units for an operation that requires an adder, there would be six alternatives to be analyzed for scheduling the operation. The scheduler/binder may also undo some prior decisions due to dependency and/or resource-conflict issues. For one example of a scheduling and binding algorithm, see B. R. Rau, “ITERATIVE MODULO SCHEDULING,” International Journal of Parallel Processing, vol. 24, pp. 3-64, 1996, the disclosure of “A” which is hereby incorporated by reference herein. This document is also available as HP Labs Tech. Report HPL-94-115 from Hewlett-Packard Co.

Hardware synthesis step107occurs after completion of operation scheduling and resource binding step106. Hardware synthesis includes the processes of allocating the registers to hold data values and connecting the hardware functional units to each other and from/to allocated storage elements. These interconnections are based on the data flow of the program and the scheduling & binding decisions taken in previous steps.

Finally, the structural description of the circuit is produced as output109. This RTL circuit description can then be taken through subsequent logic synthesis and place & route steps to produce the final circuit.

The high-level synthesis process may include other steps not shown in FIG.1. Also, the high-level synthesis process of performing analysis, transformations and optimizations, storage determination, functional unit allocation, operation scheduling and resource binding, and hardware synthesis maybe performed serially in the sequence shown inFIG. 1, or serially in a different sequence, or several of these steps may be combined and performed in parallel. One example of high-level synthesis currently available that performs several steps of the overall process is PICO-NPA. Refer to FIG.13and Section 5 of U.S. patent application Ser. No. 09/378,298, filed Aug. 20, 1999, entitled “PROGRAMMATIC SYNTHESIS OF PROCESSOR ELEMENT ARRAYS”, the disclosure of which is hereby incorporated by reference herein.

As mentioned above, the overall objective of the operation scheduling and resource binding step is to associate a specific clock cycle and functional unit to each operation in the program, such that the specified performance requirements are met and the cost of the hardware is minimized. In addition to meeting latency and throughput performance requirements, it is important to ensure that the resulting hardware meets the timing constraints imposed on the circuit paths due to the specified clock frequency. Circuit paths are combinational paths from a primary input to a latch/register, or from a latch/register to another latch/register, or from a latch/register to a primary output, or from a primary input to a primary output.

SUMMARY OF THE INVENTION

The present invention is directed to a method of considering circuit timing requirements during the circuit design process, comprising receiving a clock cycle-time constraint; receiving delay characteristics of hardware resources from a macrocell library; receiving an operation, an alternative clock cycle associated with said operation and an alternative hardware resource associated with said operation; and determining validity of the received alternative with respect to timing constraints using a hardware structural representation of the program graph.

DETAILED DESCRIPTION

FIG. 2shows a flow diagram of the mechanism to enable scheduling and binding to produce hardware that meets the given clock frequency requirement. The present invention, timing tracker205, works in conjunction with scheduler/binder201to achieve this objective. Scheduler/binder201provides as input202to timing tracker205, the following: an operation; an alternative, including an alternative clock cycle and an alternative functional unit, expressed as an ordered pair: <clock cycle, functional unit>.

Timing tracker205also receives a clock period specification203and has access to macrocell library204. Macrocell library204contains the delay for all hardware resources (functional units, registers, multiplexers and other logic-switching elements). The delay associated with each of these macrocells is pre-characterized by Δini, Δouti, Δthrui,j, Δinirefers to the longest combination path delay from the primary input i of the macrocell to a latch inside the macrocell and is a function of the transition time at the primary input. If there is no such path (for instance, for a combinational macrocell) then Δiniis irrelevant. Δoutirefers to the longest combinational path delay from a latch inside the macrocell to the primary output i of the macrocell, and is a function of the capacitive load on the primary output. If there is no such path (for instance, for a combinational macrocell) then Δoutiis irrelevant. Δthrui,jrefers to the longest combinational path delay from the primary input i of the macrocell to the primary output j of the macrocell and is a function of the primary input transition time and the primary output capacitive load. If there is no such path (for instance, for a sequential macrocell) then Δthrui,jis irrelevant. These macrocell delays, Δini, Δouti, and Δthrui,jmay also be functions of macrocell-specific parameters such as width. Furthermore, they correspond to specific hardware implementation of the macrocell, for example, the fastest implementation, the smallest implementation, etc., the choice of which may be controlled externally.

Timing tracker205uses an internal representation of the partial hardware structure as it is being defined during scheduling and binding. The structural representation of the hardware (box206) may be fine-grained wherein data flow between FUs is bound to registers and the corresponding interconnect is synthesized, or may be coarse-grained wherein data flows are modeled as virtual links between producing and consuming FUs. An example of coarse-grained structural representation is shown inFIG. 3, where the data flow from FU1to FU3is modeled as wire301, register302, and wire303, and the data flow from FU1to FU6is modeled as wire304. The level of detail included in the structural representation of the digital circuit may be controlled externally. Timing tracker205works with all such possible structural representations.

At each scheduling/binding step, timing tracker205receives new values for input202. Timing tracker205performs analysis to determine whether scheduling and binding the operation as given by the alternative will meet the clock frequency requirement in the context of prior scheduling and binding decisions. Step207identifies all scheduled operations that may cause flow dependency conflicts if the operation given in input202were to be placed on the alternative given in input202. Placement of an operation on a given alternative means that the operation will be scheduled to execute at the clock cycle corresponding to the alternative and will execute on the FU corresponding to the alternative. A flow dependency conflict is caused when an operation produces data after this data is consumed by another operation.

In step208, a directive is issued to the hardware structural representation module206to compute the hardware structure based on: the previously made scheduling and binding decisions, input202, and any flow dependence conflicting operations that were identified in step207. The structural representation may be built from scratch every time timing tracker205receives new values for input202, or the structure may be kept persistent during the scheduling/binding process and incrementally updated every time step208is invoked, i.e., every time the validity determination is performed. The timing tracker works with all such possibilities for maintaining the structural representation. In the embodiment where updating to the hardware structure is done incrementally, the hardware structural representation is updated with the additional data flow relationships that would be introduced by scheduling this operation at the clock cycle given by the alternative and on the FU given by the alternative.

FIG. 3illustrates updating to the internal hardware structure representation when the timing tracker receives an input202(FIG. 2) that specifies that an operation, for example OP1, is to be validated on a specified alternative, for example, <clock cycle=17, functional unit=FU1>. Here, as a result of updating the internal hardware structure representation, wires304,306and307(as shown in bold) are added to model the data flow relationships that get bound as a result of scheduling OP1at clock cycle17on functional unit FU1.

In step209, timing analysis is performed on the computed structural representation. If the structural representation is coarse-grained (i.e., the storage and interconnect are not modeled exactly), then, in order to perform the timing analysis, parameters that are needed by the macrocell delay functions (Δini, Δouti, and Δthrui,j) may need to be approximated. These parameters include fan-ins, fan-out capacitances, and widths. Fan-in refers to the number of inputs for each switching logic element required to steer the data values from an FU or register to another register or FU (for e.g., the number of inputs to a multiplexer). Fan-out capacitance refers to the load capacitance on all FU, register and logic element outputs. These approximations may be made prior to scheduling and binding, based on the expected values for these parameters, or they can be made during scheduling and binding, in which case, these values are recomputed every time the structure is updated. Each of these scenarios are within the scope of the present invention. These parameters are then used to derive the exact delay values for all hardware resources in the hardware structure using the Δini, Δouti, Δthrui,jfunctions associated with each resource in the macrocell library. The timing analysis is performed on the hardware structure based on these delay values.

The timing analysis step209may be performed on the entire hardware structure, or incrementally, i.e., only on the portion of the hardware structure where timing is affected as a result of the structure update. For example, inFIG. 3, as a result of the structure update described above, the portion of the hardware structure whose timing is affected is shown as within region305. Region305includes any hardware resource whose fan-in, fan-out capacitance, or width has changed due to the structure update, and all hardware resources along any circuit path whose timing changes as a result. The present invention covers timing analysis step209performed both non-incrementally and incrementally. Timing analysis, in this context, refers to the process of checking that every circuit path meets the timing constraint. It will be understood that any timing analysis algorithm may be used, such as, for example, the timing analysis disclosed in U.S. patent application Ser. No. 10/266,830 entitled “SYSTEM FOR AND METHOD OF CLOCK CYCLE-TIME ANALYSIS USING MODE-SLICING MECHANISM”, filed concurrently herewith and incorporated by reference herein in its entirety.

Referring back toFIG. 2, in step210, if the timing constraints have been satisfied in step209, a true signal is generated at step211to scheduler/binder201. Otherwise, a false signal is generated at step212and transmitted to scheduler/binder201. In one embodiment of the present invention a Boolean flag is set to true (step211) or false (step212) as a result of the timing constraint satisfaction check performed at step210. In either event, in step213, a directive is issued to the hardware structural representation module206to restore the hardware structural representation to the state it had when the timing tracker205was invoked for a new input202. The timing tracker now returns control back to the scheduler and binder201.

Another embodiment of the present invention may be used to minimize the cost of a digital circuit while meeting the timing constraints imposed by the clock frequency.FIG. 4is a flow diagram of the mechanism for selecting minimal cost alternatives in the digital circuit that satisfy the timing constraints for an electronic device to be designed. WhileFIG. 2describes a method and a system for validating operation/alternative selections for timing correctness, this embodiment of the present invention also reduces overall circuit cost. Scheduler/binder401is similar in nature to scheduler/binder201ofFIG. 2with the difference that scheduler/binder401interfaces with a cost-performance tracker403to reduce the overall digital circuit cost by minimizing the amount of silicon used. Cost-performance tracker403, works in conjunction with scheduler/binder401to achieve this objective.

Scheduler/binder401provides as input202to cost-performance tracker403, the following: an operation, and an alternative including an alternative clock cycle and an alternative functional unit.

Cost-performance tracker module403also receives a clock period specification203and has access to macrocell library402. Macrocell library402contains area-delay characteristics for all hardware resources (functional units, registers, multiplexers and other logic-switching elements). In this embodiment the macrocells in the macrocell library represent a set of hardware implementations with different areas and delays. Essentially, the macrocells in this embodiment do not correspond to specific hardware implementations as in the previously described embodiment, but instead correspond to a family of hardware implementations. In this embodiment, the delay for any chosen implementation depends on the area of the chosen implementation, in addition to the other parameters, such as widths, input transition times and capacitive output loads. Similarly, the area for any chosen implementation depends on the delay of the chosen implementation. Areas, in this context, are proportional to the amount of silicon included in the hardware resource and is therefore associated with the cost of the hardware resource.

As the amount of silicon in the hardware resource is increased, the delay is decreased but the cost of the hardware resource is increased. For example, as the delay of an adder is decreased, the silicon area increases and the associated cost is also increased. These area-delay characteristics are typically represented as area delay trade-off curves. The trade-off curves could be expressed in several ways, as a list of area-delay values (tuples), or as a closed-form formula. The present invention is capable of working with any of these representations. Also, for a macrocell with internal latches (e.g., pipelined FUs), there will be a different area-delay curve for each possible micro-architectural choice for that macrocell (e.g. ripple-carry vs. carry-lookahead vs. carry-select for an adder).

FIG. 5shows two examples of (i) macrocell501and its area-delay characteristics represented as area-delay curves505,506and507and (ii) macrocell508and its area-delay characteristics represented as area-delay curve510. Here, “Ain”502refers to the area of that portion of the macrocell that consists of all combinational logic from the macrocell inputs up to the set of pipelining registers first encountered within the macrocell starting from its inputs. The corresponding area-delay curve is shown by505. “Aout”504refers to the area of that portion of the macrocell which consists of the set of pipelining registers first encountered within the macrocell starting going backwards from its outputs, and all combinational logic between these registers and the macrocell outputs. The corresponding area-delay curve is shown by507. “Apipe”503refers to the area of that portion of the macrocell which consists of the first and all intermediate set of pipelining registers, and all intervening combinational logic. The corresponding area-delay curve is shown by506. For the example of a combinational macrocell508, “A”509refers to the total area. The corresponding area-delay curve is shown by510.

Returning toFIG. 4, at each scheduling/binding step, cost-performance tracker403receives new values for input202. Cost-performance tracker403performs analysis to determine a comparative cost of the hardware resulting from scheduling and binding the operation as given by the alternative in the context of prior scheduling and binding decisions, while still meeting the clock frequency requirement. Upon receiving new values for input202, steps207followed by step208are performed. These steps have already been described in the context of FIG.2.

Next, step404determines the minimal relative cost of the computed hardware structural representation such that the specified clock period input203is satisfied. This determination can be done in several ways.

In one embodiment of step404, this is posed as a numerical optimization problem:
min ΣA
such that ∀p, ΣpΔ≦T

where “min ΣA” means minimize the sum of the areas of all components, and “∀p, ΣpΔ≦T” means for every circuit path p (“∀p”) the path delay, i.e., the sum of the delays of all components along that path p (“ΣpΔ”), is less than or equal to the input clock period203(“≦T”). This numerical optimization problem is non-linear because of the non-linear nature of the macrocell area-delay characteristics.

In another embodiment of step404, time-budgeting can be used to partition the clock cycle time amongst the registers, the interconnects and the FUs along each circuit path. In this manner the delay constraints on each individual hardware resource are obtained and analyzed to ensure that timing considerations are satisfied. The area-delay characteristics are used to determine the minimum area implementation for each hardware resource such that the delay constraints for the hardware resource are satisfied.

Additionally, choices concerning variations among micro-architectural choices for each FU macrocell are also included as part of the analysis. For example, a pipelined FU macrocell may have two different micro-architectural implementations, e.g., arch1and arch2, represented by representative area-delay trade-off curves601-603ofFIG. 6. Aminimal area implementation such that the delay constraints (Δini, cycle time, Δouti,) are met is
min(Ain,arch1+Apipe,arch1+Aout,arch1, Ain,arch2+Apipe,arch2+Aout,arch2).

Similar to step209, step404may be performed for all hardware resources in the hardware structure, or may be done only for the portion of the hardware structure where timing is affected as a result of the structure update step208. The present invention covers step404performed both non-incrementally and incrementally.

Subsequently, in step213, a directive is issued to the hardware structural representation module206to restore the hardware structural representation to the state it had when the cost-performance tracker403was invoked for a new input202. The cost-performance tracker now returns control back to the scheduler and binder401.

The second described embodiment ensures the selection of alternatives for operations that are both minimal cost and are timing correct. This enables the objective of minimizing the silicon area while utilizing the entire specified clock period for computation. This approach is superior to previous approaches in that the minimum cost hardware is derived accurately and used to guide alternative selections at each step of the design process.