HIGH-DENSITY MICROBUMP ARRAYS WITH ENHANCED ADHESION AND METHODS OF FORMING THE SAME

A semiconductor die may include metal interconnect structures located within interconnect-level dielectric material layers, bonding pads located on a topmost interconnect-level dielectric material layer, a dielectric passivation layer located on the topmost interconnect-level dielectric material layer, and metal bump structures extending through the dielectric passivation layer and located on the bonding pads. Each of the metal bump structures comprises a contoured bottom surface including a bottommost surface segment in contact with a top surface of a respective one of the bonding pads, a tapered surface segment in contact with a tapered sidewall of a respective opening through the dielectric passivation layer, and an annular surface segment that overlies the dielectric passivation layer and having an inner periphery that is laterally offset inward from an outer periphery by a lateral offset distance that is at least 8% of a width of a respective underlying one of the bonding pads.

BACKGROUND

Micrometal bump structures are used to provide high-density electrical connection between a semiconductor die and an interposer, between a pair of semiconductor dies, and/or between a semiconductor die and a packaging substrate.

DETAILED DESCRIPTION

The present disclosure is directed to semiconductor devices, and particularly to a semiconductor die including stress-resistant bonding structures and method of forming the same, the various aspects of which are now described in detail.

Generally, the various embodiment methods and structures disclosed herein may be used to provide a semiconductor die including a high-density array of microbumps. According to an aspect of the present disclosure, adhesion between the microbumps and underlying structures may be enhanced by increasing contact areas between the microbumps and a dielectric passivation layer. The microbumps may comprise contoured bottom surfaces including annular surface segments that increase adhesion to an underlying material layer, which may comprise the dielectric passivation layer and/or a capping dielectric material layer. The various aspects of the methods and structures of embodiments of the present disclosure are now described with reference to the accompanying drawings.

FIG.1is a vertical cross-sectional view of an exemplary structure after formation of complementary metal-oxide-semiconductor (CMOS) transistors, metal interconnect structures embedded in dielectric material layers, and a connection-via-level dielectric layer according to an embodiment of the present disclosure. The exemplary structure includes complementary metal-oxide-semiconductor (CMOS) transistors and metal interconnect structures formed in dielectric material layers. Specifically, the exemplary structure includes a semiconductor substrate9, which may be a semiconductor substrate such as a commercially available silicon wafer. Shallow trench isolation structures720including a dielectric material such as silicon oxide may be formed in an upper portion of the semiconductor substrate9. Suitable doped semiconductor wells, such as p-type wells and n-type wells, may be formed within each area that may be laterally enclosed by a portion of the shallow trench isolation structures720. Field effect transistors may be formed over the top surface of the semiconductor substrate9. For example, each field effect transistor may include a source region732, a drain region738, a semiconductor channel735that includes a surface portion of the semiconductor substrate9extending between the source region732and the drain region738, and a gate structure750. Each gate structure750may include a gate dielectric752, a gate electrode754, a gate cap dielectric758, and a dielectric gate spacer756. A source-side metal-semiconductor alloy region742may be formed on each source region732, and a drain-side metal-semiconductor alloy region748may be formed on each drain region738. While planar field effect transistors are illustrated in the drawings, embodiments are expressly contemplated herein in which the field effect transistors may additionally or alternatively include fin field effect transistors (FinFET), gate-all-around field effect (GAA FET) transistors, or any other type of field effect transistors (FETs).

The devices formed on the top surface of the semiconductor substrate9may include field effect transistors701such as complementary metal-oxide-semiconductor (CMOS) transistors. Additional semiconductor devices (such as resistors, diodes, capacitors, etc.) may be formed on the semiconductor substrate9.

Various metal interconnect structures (which are also referred to as first metal interconnect structures) embedded in dielectric material layers (which are also referred to as first dielectric material layers) may be subsequently formed over the semiconductor substrate9and the devices (such as field effect transistors). The dielectric material layers may include, for example, a contact-level dielectric material layer601, a first metal-line-level dielectric material layer610, a second line-and-via-level dielectric material layer620, a third line-and-via-level dielectric material layer630, and a fourth line-and-via-level dielectric material layer640. The metal interconnect structures may include device contact via structures612formed in the contact-level dielectric material layer601and contact a respective component of the field effect transistors701, first metal line structures618formed in the first metal-line-level dielectric material layer610, first metal via structures622formed in a lower portion of the second line-and-via-level dielectric material layer620, second metal line structures628formed in an upper portion of the second line-and-via-level dielectric material layer620, second metal via structures632formed in a lower portion of the third line-and-via-level dielectric material layer630, third metal line structures638formed in an upper portion of the third line-and-via-level dielectric material layer630, third metal via structures642formed in a lower portion of the fourth line-and-via-level dielectric material layer640, and fourth metal line structures648formed in an upper portion of the fourth line-and-via-level dielectric material layer640.

Each of the dielectric material layers (601,610,620,630,640) may include a dielectric material such as undoped silicate glass, a doped silicate glass, organosilicate glass, amorphous fluorinated carbon, porous variants thereof, or combinations thereof. Each of the metal interconnect structures (612,618,622,628,632,638,642,648) may include at least one conductive material, which may be a combination of a metallic liner layer (such as a metallic nitride or a metallic carbide) and a metallic fill material. Each metallic liner layer may include TiN, TaN, WN, TiC, TaC, and WC, and each metallic fill material portion may include W, Cu, Al, Co, Ru, Mo, Ta, Ti, alloys thereof, and/or combinations thereof. Other suitable metallic fill materials within the contemplated scope of disclosure may also be used. In one embodiment, the first metal via structures622and the second metal line structures628may be formed as integrated line and via structures by a dual damascene process, the second metal via structures632and the third metal line structures638may be formed as integrated line and via structures, and/or the third metal via structures642and the fourth metal line structures648may be formed as integrated line and via structures. While the present disclosure is described using an embodiment in which an array of memory cells formed over the fourth line-and-via-level dielectric material layer640, embodiments are expressly contemplated herein in which the array of memory cells may be formed at a different metal interconnect level.

The dielectric material layers (601,610,620,630,640) may be located at a lower level relative to an array of memory cells to be subsequently formed. As such, the dielectric material layers (601,610,620,630,640) are herein referred to as lower-level dielectric layers, i.e., dielectric material layer located at a lower level relative to the array of memory cells to be subsequently formed. The metal interconnect structures (612,618,622,628,632,638,642,648) are herein referred to lower-level metal interconnect structures. A subset of the metal interconnect structures (612,618,622,628,632,638,642,648) includes lower-level metal lines (such as the fourth metal line structures648) that are embedded in the lower-level dielectric layers and having top surfaces within a horizontal plane including a topmost surface of the lower-level dielectric layers. Generally, the total number of metal line levels within the lower-level dielectric layers (601,610,620,630,640) may be in a range from1to10.

FIGS.2A-2Jare sequential vertical cross-sectional view of a portion of a first configuration of the exemplary structure during formation of bonding pads, a dielectric passivation layer, a capping dielectric material layer, metal bump structures, and solder material portions according to an embodiment of the present disclosure.

Referring toFIG.2A, additional metal interconnect levels may be used to provide stress-absorption structures such as multi-via support structures (648,656). Each multi-via support structure (648,656) may be designed to distribute a mechanical stress transmitted from an overlying connection via structure to be subsequently formed over an area larger than the area of the overlying connection via structure. For example, each multi-via support structure (648,656) may include a bottom metallic plate (which may be, for example, a fourth metal line structures648), and an integrated plate and via assembly656that may be formed in a dielectric material layer such as a fifth line-and-via-level dielectric material layer650. The integrated plate and via assembly656may include a top metallic plate and a plurality of metallic via structures that are adjoined to the top metallic plate and contacting a top surface of the bottom metallic plate. The integrated plate and via assemblies656may be formed by patterning an array of via cavities through the fifth line-and-via-level dielectric material layer650over each area of the bottom metallic plates, by depositing at least one metallic material in the array of via cavities and over the fifth line-and-via-level dielectric material layer650, and by patterning the at least one metallic material. Each integrated plate and via assembly656may have a planar top surface, i.e., a top surface located entirely within a horizontal plane.

Referring toFIG.2B, another dielectric material layer, which is herein referred to as a topmost interconnect-level dielectric material layer660, may be deposited over the fifth line-and-via-level dielectric material layer650and fifth metal interconnect structures (which include the integrated plate and via assemblies656). The topmost interconnect-level dielectric material layer660may also be referred to as a first topmost interconnect-level dielectric material layer. The topmost interconnect-level dielectric material layer660may include any material that may be used for the underlying interconnect-level dielectric material layers. The thickness of the topmost interconnect-level dielectric material layer660may be in a range from 2 microns to 20 microns, although lesser and greater thicknesses may also be used.

A connection via cavity may be formed over each of the integrated plate and via assemblies656through the topmost interconnect-level dielectric material layer660, for example, by applying and patterning a photoresist layer and by transferring the pattern in the photoresist layer through the topmost interconnect-level dielectric material layer660by performing an etch process such as a reactive ion etch process. A top surface of an integrated plate and via assembly656may be physically exposed at the bottom of each connection via cavity. The maximum lateral dimension of each connection via cavity, such as a diameter of an upper periphery of each connection via cavity, may greater than twice the thickness of a metallic material layer to be subsequently deposited thereupon. For example, the maximum lateral dimension of each connection via cavity may be in a range from 1 microns to 20 microns, such as from 2 microns to 15 microns, although lesser and greater maximum lateral dimensions may also be used.

At least one metallic material such as Cu, Mo, Co, Ru, W, TiN, TaN, WN, or a combination or a stack thereof may be deposited in the connection via cavities and over the top surface of the topmost interconnect-level dielectric material layer660, for example, by physical vapor deposition. The at least one metallic material may be patterned, for example, by applying a photoresist layer over the at least one metallic material and by transferring the pattern in the photoresist layer through the at least one metallic material. Patterned portions of the at least one metallic material comprise bonding pads68that contact a respective one of the multi-via support structures (648,656). The bonding pads68are also referred to as first bonding pads.

Each bonding pad68may comprise a connection via portion located within a respective connection via cavity below a horizontal plane including a top surface of the topmost interconnect-level dielectric material layer660and a pad plate portion that contacts a horizontal top surface of the topmost interconnect-level dielectric material layer660and located above the horizontal plane including the top surface of the topmost interconnect-level dielectric material layer660. Each connection via portion of the bonding pads68vertically extends through the topmost interconnect-level dielectric material layer660, and each pad plate portion of the bonding pads68overlies the topmost interconnect-level dielectric material layer660.

The maximum lateral dimension between parallel facing pairs of sidewall segments of each bonding pad68is herein referred to as a pad width PW. The pad width PW of each bonding pad68may be in a range from 2 micron to 40 microns, such as from 3 microns to 20 microns, although lesser and greater pad widths PW may also be used. Optionally, pad-level metal structures69may be formed, which may comprise metal interconnect structures (such as metal lines) and/or inductor structures. In one embodiment, the bonding pads68may comprise, and/or may consist essentially of, copper. The thickness of the bonding pads68may be in a range from 2 microns to 10 microns, although lesser and greater thicknesses may also be used. The bonding pads68may have a horizontal cross-sectional shape of a rectangle, a circle, or a rounded rectangle. Generally, the bonding pads68may be located on the topmost interconnect-level dielectric material layer660, and may be electrically connected to a respective one of the metal interconnect structures that are embedded within the interconnect-level dielectric material layers (610,620,630,640,650,660).

Referring toFIG.2C, a dielectric passivation layer72may be formed directly on, and over, the topmost interconnect-level dielectric material layer660and the bonding pads68. The dielectric passivation layer72comprises, and/or consists essentially of, a dielectric passivation material blocking diffusion of hydrogen and moisture. In one embodiment, the dielectric passivation material of the dielectric passivation layer72may be selected from silicon nitride and silicon carbide nitride. In one embodiment, the dielectric passivation layer72may be formed by a conformal deposition process such as a chemical vapor deposition process. The thickness of the dielectric passivation layer72may be in a range from 100 nm to 1,000 nm, such as from 200 nm to 500 nm, although lesser and greater thicknesses may also be used.

In one embodiment, the dielectric passivation layer72comprises a horizontally-extending segment721contacting the topmost interconnect-level dielectric material layer660, vertically-extending segments722contacting sidewalls of the bonding pads68, and capping segments723contacting top surfaces of the bonding pads68. Each capping segment723may contact an entirety of the top surface of a respective underlying bonding pad68. Outer sidewalls of the vertically-extending segments722of the dielectric passivation layer72may be physically exposed.

Referring toFIG.2D, a capping dielectric material layer74may be formed over the dielectric passivation layer72, for example, by deposition of a capping dielectric material and subsequent planarization of the capping dielectric material. The planarization of the capping dielectric material may be performed by a recess etch process or by a chemical mechanical polishing process. In one embodiment, an entirety of the top surface of the capping dielectric material layer74may be formed within a horizontal plane. The vertical distance between the topmost surfaces (such as the top surfaces of the capping segments723) of the dielectric passivation layer72and the top surface of the capping dielectric material layer74may be in a range from 100 nm to 2 microns, such as from 200 nm to 1.5 micron and/or from 300 nm to 1 micron, although lesser and greater vertical distances may also be used. In one embodiment, the ratio of the vertical distance between the topmost surfaces of the dielectric passivation layer72and the top surface of the capping dielectric material layer74to the thickness of the dielectric passivation layer72may be greater than 1.0, and may be in a range from 1.0 to 3.0.

In one embodiment, the capping dielectric material layer74may comprise an additional dielectric passivation material blocking diffusion of hydrogen and moisture. In one embodiment, the additional dielectric passivation material of the capping dielectric material layer74may be selected from silicon nitride and silicon carbide nitride. In one embodiment, the additional dielectric passivation material of the capping dielectric material layer74may be different from the dielectric passivation material of the dielectric passivation layer72. In one embodiment, the dielectric passivation layer72comprises silicon nitride, and the capping dielectric material layer74comprises silicon carbide nitride. In another embodiment, the dielectric passivation layer72comprises silicon carbide nitride, and the capping dielectric material layer74comprises silicon nitride.

Referring toFIG.2E, a photoresist layer77may be applied over the capping dielectric material layer74, and may be lithographically patterned to form openings therein. In one embodiment, the bonding pads68may be formed as a two-dimensional periodic array of bonding pads68such as a rectangular periodic array or a hexagonal periodic array. In this case, the openings in the photoresist layer77may have the same two-dimensional periodicity as the underlying two-dimensional array of bonding pads68. In one embodiment, the shape of each opening through the photoresist layer77may be circular, and may have a diameter that is less than the pad width PW of the bonding pads68. In one embodiment, the area of each opening through the photoresist layer77may be located entirely within the area of an underlying bonding pad68in a plan view (such as a top-down view). In one embodiment, the entirety of the periphery of each opening through the photoresist layer77may be laterally offset inward from the sidewalls of the underlying bonding pad68. In one embodiment, the ratio of the diameter of an opening in the photoresist layer77to the pad width PW of an underlying bonding pad68to may be in a range from 0.5 to 0.80, although lesser and greater ratios may also be used.

An anisotropic etch process may be performed to transfer the pattern of the openings in the photoresist layer77through the underlying portions of the capping dielectric material layer74and the dielectric passivation layer72. Openings having tapered surfaces may be formed through the capping dielectric material layer74and the dielectric passivation layer72. Generally, the taper angle of the tapered sidewalls of the capping dielectric material layer74and the taper angle of the tapered sidewalls of the dielectric passivation layer72may be the same or different. The taper angle (as measured from a vertical direction) of the tapered sidewalls of the capping dielectric material layer74may be in a range from 30 degrees to 75 degrees, such as from 40 degrees to 65 degrees, although lesser and greater taper angles may also be used. The taper angle (as measured from a vertical direction) of the tapered sidewalls of the dielectric passivation layer72may be in a range from 35 degrees to 80 degrees, such as from 45 degrees to 70 degrees, although lesser and greater taper angles may also be used. In one embodiment, the taper angle of the tapered sidewalls of the dielectric passivation layer72may be greater than the taper angle of the tapered sidewalls of the capping dielectric material layer74.

A planar top surface portion of each bonding pad68may be physically exposed after the anisotropic etch process. In one embodiment, each physically exposed planar top surface portion of the bonding pads68may have a circular shape with a diameter, which is herein referred to as a bottom pad opening width BPOW. The ratio of the bottom pad opening width BPOW to the pad width PW may be in a range from 0.3 to 0.7, such as from 0.35 to 0.65, although lesser and grater ratios may also be used.

Referring toFIG.2E, a selective etch process may be optionally performed to recess physically exposed surfaces of the capping dielectric material layer74selective to the dielectric passivation layer72. The recess distance of the capping dielectric material layer74may be in a range from 1 nm to 100 nm, such as from 3 nm to 50 nm, although lesser and greater recess distances may be used. The selective etch process may comprise an isotropic etch process or an anisotropic etch process. In an alternative embodiment, the selective etch process may be performed after the anisotropic etch process ofFIG.2Dprior to removal of the patterned photoresist layer77.

Referring toFIG.2F, A top periphery of each tapered opening through the capping dielectric material layer74may be circular, and may have a lateral dimension (i.e., a diameter) that is herein referred to as a top pad opening width TPOW. The ratio of the top pad opening width TPOW to the bottom pad opening width BPOW may be in a range from 1.13 to 1.30, such as from 1.16 to 1,24, although lesser and greater ratios may also be used. The photoresist layer77may be removed, for example, by ashing.

A top periphery of each tapered opening through the dielectric passivation layer72may be circular, and may have a lateral dimension (i.e., a diameter) that is herein referred to as an intermediate pad opening width IPOW. A bottom periphery of each tapered opening through the dielectric passivation layer72may be circular, and may have a lateral dimension (i.e., a diameter) that is herein referred to as a bottom pad opening width BPOW. A lateral offset Δ may be present between a bottom periphery of a tapered opening through the capping dielectric material layer74and the top periphery of an underlying tapered opening through the dielectric passivation layer72. The A lateral offset Δ may be the same as the recess distance of the selective etch process, and may be in a range from 1 nm to 100 nm, such as from 3 nm to 50 nm, although lesser and greater recess distances may be used.

Referring toFIG.2G, a continuous metallic seed layer802L may be deposited over, and directly on, the physically exposed surfaces of the dielectric passivation layer72, the capping dielectric material layer74, and the bonding pads68. The continuous metallic seed layer802L includes a continuous metallic seed material such as Ti, Ta, W, TiN, TaN, or WN. In one embodiment, the continuous metallic seed layer802L may be deposited by physical deposition process. The continuous metallic seed layer802L may be deposited in the openings through the capping segments723of the dielectric passivation layer72and on physically exposed surfaces of the bonding pads68. The thickness of the continuous metallic seed layer802L may be in a range from 30 nm to 300 nm, although lesser and greater thicknesses may also be used.

Referring toFIG.2H, a photoresist layer87may be formed over the continuous metallic seed layer802L, and may be lithographically patterned to form openings over each of the openings through the capping dielectric material layer74. The thickness of the photoresist layer87may be greater than the height of the copper pillar structures to be subsequently formed. For example, the thickness of the photoresist layer87as measured over the top surface of the capping dielectric material layer74may be in a range from 2 micron to 30 microns, such as from 3 microns to 20 microns, although lesser and greater thicknesses may also be used. In one embodiment, openings in the photoresist layer87may have a respective shape of a circular cylindrical pillar having a diameter, which is herein referred to as a bump width BW. In one embodiment, each opening in the photoresist layer87may have a respective periphery that is located entirely within the area of an underlying bonding pad PW.

Referring toFIG.21, copper pillar structures804may be formed within the openings in the photoresist layer87directly on physically exposed metallic surfaces of the continuous metallic seed layer802L, for example, by electroplating. Each electroplate material portion located within a respective opening in the photoresist layer87constitutes a copper pillar structure804. Each copper pillar structure804may have a diameter of the bump width BW. The ratio of the pad width PW to the bump width BW may be in a range from 1.01 to 1.60, although lesser and greater ratios may also be used. The copper pillar structures804may have the same two-dimensional periodicity as the bonding pads68. The ratio of the pad width PW to the periodicity of the two-dimensional array of bonding pads68in any direction of periodicity may be in a range from 0.20 to 0.50, although lesser and greater ratios may also be used.

The lateral offset distance between the sidewall of a copper pillar structure804and a vertical plane including a most proximal portion of a top periphery of a tapered sidewall of an underlying opening through the capping dielectric material layer74is herein referred to as a first lateral offset distance ENA. In one embodiment, the ratio of the first lateral offset distance ENA to the pad width PW is greater than 0.08, and may be in a range from 0.08 to 0.20, such as from 0.11 to 0.16. According to an aspect of the present disclosure, selection of the ratio of the first lateral offset distance ENA to the pad width PW within the range from 0.08 to 0.20 enhances adhesion of the metal bump structures to be formed to the dielectric passivation layer72and the capping dielectric material layer74.

The lateral offset distance between the sidewall of a copper pillar structure804and a vertical plane including a most proximal sidewall of an underlying bonding pad68is herein referred to as a second lateral offset distance ENB. In one embodiment, the ratio of the second lateral offset distance ENB to the pad width PW is greater than 0.07, and may be in a range from 0.07 to 0.18, such as from 0.10 to 0.15. According to an aspect of the present disclosure, selection of the ratio of the second lateral offset distance ENB to the pad width PW within the range from 0.07 to 0.18 enhances adhesion of the metal bump structures to be formed to the dielectric passivation layer72and the capping dielectric material layer74.

Referring toFIG.2J, the photoresist layer87may be removed selective to the copper pillar structures804and the continuous metallic seed layer802L, for example, by ashing. An etch process may be performed to etch physically exposed portions of the continuous metallic seed layer802L. The etch process may comprise an anisotropic etch process or an isotropic etch process. Each patterned portion of the continuous metallic seed layer802L comprises a metallic seed layer802. Each contiguous combination of a metallic seed layer802and a copper pillar structure804constitutes a metal bump structure80.

Referring toFIGS.2K,2L, and3, a solder material portion130may be attached to the top surface of each of the metal bump structures80. In one embodiment, each of the metal bump structures80may be located entirely within an area of the respective underlying one of the bonding pads68in a plan view along a direction that is perpendicular to a top surface of the topmost interconnect-level dielectric material layer660.

Generally, metal bump structures80may be formed on the first bonding pads68through the dielectric passivation layer72, Each of the first metal bump structures80comprises a contoured bottom surface including a bottommost surface segment BSS in contact with a top surface of a respective one of the bonding pads68, a first tapered surface segment TSS1in contact with a tapered sidewall of a respective opening through the dielectric passivation layer72, and a first annular surface segment ASS1that overlies the dielectric passivation layer72and having an inner periphery that is laterally offset inward from an outer periphery by a first lateral offset distance ENA that is at least 8% of a width, i.e., the pad width PW, of a respective underlying one of the first bonding pads68. In one embodiment, the diameter of the inner periphery of the first annular surface segment ASS1may be the same as the top pad opening width TPOW. In one embodiment, the outer periphery of the first annular surface segment ASS1may be the same as the bottom periphery of a cylindrical sidewall of the metal bump structure80.

In one embodiment, a capping dielectric material layer74may overlie the dielectric passivation layer72, and each of the metal bump structures80comprises an additional tapered surface segment, i.e., a second tapered sidewall segment TSS2, in contact with a tapered sidewall of a respective opening through the capping dielectric material layer74.

In some embodiments, the capping dielectric material layer74comprises a horizontal top surface that extends over areas that are not covered by the metal bump structures, and a cylindrical surfaces segment of the capping dielectric material layer74extends between a bottom periphery of each of the metal bump structures80and a respective periphery of the horizontal top surface of the capping dielectric material layer74.

In one embodiment, the first annular surface segment ASS1of each of the metal bump structures80contacts a respective annular surface segment of the capping dielectric material layer74, and each of the metal bump structures80comprises an additional annular surface segment (i.e., a second annular surface segment ASS2) in contact with a respective annular surface segment of a top surface of a capping segment723of the dielectric passivation layer72that overlies a respective one of the bonding pads68.

Referring toFIG.4, a first semiconductor die700is illustrated, which includes the first configuration of the exemplary structure illustrated inFIG.3. An interconnect-containing structure200is provided, which has an array of second metal bump structures280on a mating surface thereof. The array of second metal bump structures280on the interconnect-containing structure200may have a mirror image pattern of the array of first metal bump structures80on the first semiconductor die700.

Generally, the interconnect-containing structure200may comprise any structure that includes metal interconnect structures embedded within dielectric material layers. For example, the interconnect-containing structure200may comprise a second semiconductor die, an interposer, or a packaging substrate. The metal interconnect structures may comprise conventional metal interconnect structures formed in silicon oxide-based dielectric material layers as used in back-end-of-line (BEOL) semiconductor processing steps, or redistribution structures embedded within polymer layers. The first metal bump structures80of the first semiconductor die700may be bonded to the second metal bump structures280of the interconnect-containing structure200through the solder material portions130.

Referring toFIGS.5A and5B, an underfill material portion90may be applied into the gap between the first semiconductor die700and the interconnect-containing structure200. The underfill material portion90may comprise any dielectric underfill material known in the art. The underfill material portion90may contact the solder material portions130, the first metal bump structures80of the first semiconductor die700, and the second metal bump structures280of the interconnect-containing structure200. In one embodiment, the underfill material portion90may contact the horizontal top surface and vertical sidewalls (such as cylindrical surface segments) of the capping dielectric material layer74.

In one embodiment, the first configuration of the exemplary structure may comprise first metal interconnect structures located within first interconnect-level dielectric material layers (610,620,630,640,650,660); first bonding pads68located on a topmost first interconnect-level dielectric material layer660and electrically connected to a respective one of the first metal interconnect structures; a dielectric passivation layer72located on the topmost first interconnect-level dielectric material layer660and the first bonding pads68; and first metal bump structures80extending through the dielectric passivation layer72and located on the first bonding pads68. Each of the first metal bump structures80comprises a contoured bottom surface including a bottommost surface segment in contact with a top surface of a respective one of the bonding pads68, and an annular surface segment that overlies, and is vertically spaced from, the dielectric passivation layer72and having an inner periphery that is laterally offset inward from an outer periphery by a lateral offset distance that is at least 8% of a width of a respective underlying one of the first bonding pads68.

FIGS.6A-6Eare sequential vertical cross-sectional view of a portion of a second configuration of the exemplary structure during formation of bonding pads, a dielectric passivation layer, metal bump structures, and solder material portions according to an embodiment of the present disclosure.

Referring toFIG.6A, the second configuration of the exemplary structure may be the same as the first configuration of the exemplary structure illustrated inFIG.2C.

Referring toFIG.6B, a photoresist layer77may be applied over the dielectric passivation layer72, and may be lithographically patterned to form openings therein. In one embodiment, the bonding pads68may be formed as a two-dimensional periodic array of bonding pads68such as a rectangular periodic array or a hexagonal periodic array. In this case, the openings in the photoresist layer77may have the same two-dimensional periodicity as the underlying two-dimensional array of bonding pads68. In one embodiment, the shape of each opening through the photoresist layer77may be circular, and may have a diameter that is less than the pad width PW of the bonding pads68. In one embodiment, the area of each opening through the photoresist layer77may be located entirely within the area of an underlying bonding pad68in a plan view (such as a top-down view). In one embodiment, the entirety of the periphery of each opening through the photoresist layer77may be laterally offset inward from the sidewalls of the underlying bonding pad68. In one embodiment, the ratio of the diameter of an opening in the photoresist layer77to the pad width PW of an underlying bonding pad68to may be in a range from 0.5 to 0.80, although lesser and greater ratios may also be used.

An anisotropic etch process may be performed to transfer the pattern of the openings in the photoresist layer77through the underlying portions of the dielectric passivation layer72. Openings having tapered surfaces are formed through the dielectric passivation layer72. The taper angle (as measured from a vertical direction) of the tapered sidewalls of the dielectric passivation layer72may be in a range from 35 degrees to 80 degrees, such as from 45 degrees to 70 degrees, although lesser and greater taper angles may also be used.

A planar top surface portion of each bonding pad68may be physically exposed after the anisotropic etch process. In one embodiment, each physically exposed planar top surface portion of the bonding pads68may have a circular shape with a diameter, which is herein referred to as a bottom pad opening width BPOW. The ratio of the bottom pad opening width BPOW to the pad width PW may be in a range from 0.3 to 0.7, such as from 0.35 to 0.65, although lesser and grater ratios may also be used. The top periphery of a tapered surface of each opening through the dielectric passivation layer72may have a circular shape having a diameter, which is herein referred to as a top pad opening width TPOW. The ratio of the top pad opening width TPOW to the bottom pad opening width TPOW may be in a range from 1.13 to 1.30, such as from 1.16 to 1.24, although lesser and greater ratios may also be used. The photoresist layer77may be removed, for example, by ashing.

Referring toFIG.6C, the processing steps ofFIGS.2F and2Gmay be performed to form a continuous metallic seed layer802L and a copper layer804L. The thickness and the material composition of each of the continuous metallic seed layer802L and the copper layer804L may be the same as in the first configuration of the exemplary structure.

Referring toFIG.6D, the processing steps ofFIG.2Hmay be performed to pattern the copper layer804L into copper pillar structures804. Each copper pillar structure804may have a diameter of the bump width BW. The ratio of the pad width PW to the bump width BW may be in a range from 1.01 to 1.60, although lesser and greater ratios may also be used. The copper pillar structures804may have the same two-dimensional periodicity as the bonding pads68. The ratio of the pad width PW to the periodicity of the two-dimensional array of bonding pads68in any direction of periodicity may be in a range from 0.20 to 0.50, although lesser and greater ratios may also be used.

The lateral offset distance between the sidewall of a copper pillar structure804and a vertical plane including a most proximal portion of a top periphery of a tapered sidewall of an underlying opening through the dielectric passivation layer72is herein referred to as a first lateral offset distance ENA. In one embodiment, the ratio of the first lateral offset distance ENA to the pad width PW is greater than 0.08, and may be in a range from 0.08 to 0.20, such as from 0.11 to 0.16. According to an aspect of the present disclosure, selection of the ratio of the first lateral offset distance ENA to the pad width PW within the range from 0.08 to 0.20 enhances adhesion of the metal bump structures to be formed to the dielectric passivation layer72.

The lateral offset distance between the sidewall of a copper pillar structure804and a vertical plane including a most proximal sidewall of an underlying bonding pad68is herein referred to as a second lateral offset distance ENB. In one embodiment, the ratio of the second lateral offset distance ENB to the pad width PW is greater than 0.07, and may be in a range from 0.07 to 0.18, such as from 0.10 to 0.15. According to an aspect of the present disclosure, selection of the ratio of the second lateral offset distance ENB to the pad width PW within the range from 0.07 to 0.18 enhances adhesion of the metal bump structures to be formed to the dielectric passivation layer72and the capping dielectric material layer74.

Referring toFIG.6E, the processing steps ofFIGS.2J,2K,2L, and3may be performed to form metal bump structures80. In one embodiment, each of the metal bump structures80may be located entirely within an area of the respective underlying one of the bonding pads68in a plan view along a direction that is perpendicular to a top surface of the topmost interconnect-level dielectric material layer660.

Generally, metal bump structures80may be formed on the first bonding pads68through the dielectric passivation layer72, Each of the first metal bump structures80comprises a contoured bottom surface including a bottommost surface segment BSS in contact with a top surface of a respective one of the bonding pads68, a first tapered surface segment TSS1in contact with a tapered sidewall of a respective opening through the dielectric passivation layer72, and a first annular surface segment ASS1that overlies the dielectric passivation layer72and having an inner periphery that is laterally offset inward from an outer periphery by a first lateral offset distance ENA that is at least 8% of a width, i.e., the pad width PW, of a respective underlying one of the first bonding pads68. In one embodiment, the diameter of the inner periphery of the first annular surface segment ASS1may be the same as the top pad opening width TPOW. In one embodiment, the outer periphery of the first annular surface segment ASS1may be the same as the bottom periphery of a cylindrical sidewall of the metal bump structure80. In one embodiment, the first annular surface segment ASS1of each of the metal bump structures80contacts a respective annular surface segment of the dielectric passivation layer72.

Referring toFIG.7, the processing steps ofFIGS.4,5A, and5Bmay be performed to form a bonded structure including a first semiconductor die700and an interconnect-containing structure200. Specifically, an underfill material portion90may be applied into the gap between the first semiconductor die700and the interconnect-containing structure200. The underfill material portion90may comprise any dielectric underfill material known in the art. The underfill material portion90may contact the solder material portions130, the first metal bump structures80of the first semiconductor die700, and the second metal bump structures280of the interconnect-containing structure200. In one embodiment, the underfill material portion90may contact the horizontal top surface of the dielectric passivation layer72.

In one embodiment, the second configuration of the exemplary structure may comprise first metal interconnect structures located within first interconnect-level dielectric material layers (610,620,630,640,650,660); first bonding pads68located on a topmost first interconnect-level dielectric material layer660and electrically connected to a respective one of the first metal interconnect structures; a dielectric passivation layer72located on the topmost first interconnect-level dielectric material layer660and the first bonding pads68; and first metal bump structures80extending through the dielectric passivation layer72and located on the first bonding pads68. Each of the first metal bump structures80comprises a contoured bottom surface including a bottommost surface segment in contact with a top surface of a respective one of the bonding pads68, and an annular surface segment that overlies, and directly contacts, the dielectric passivation layer72and having an inner periphery that is laterally offset inward from an outer periphery by a lateral offset distance that is at least 8% of a width of a respective underlying one of the first bonding pads68.

FIGS.8A-8Iare sequential vertical cross-sectional view of a portion of a third configuration of the exemplary structure during formation of bonding pads, a dielectric passivation layer, a capping dielectric material layer, metal bump structures, and solder material portions according to an embodiment of the present disclosure.

Referring toFIG.8A, the third configuration of the exemplary structure may be derived from the first configuration of the exemplary structure illustrated inFIG.2Cby forming a capping dielectric material layer174over the dielectric passivation layer72. According to an aspect of the present disclosure, the capping dielectric material layer174includes a polymer material such as polyimide. In one embodiment, the polymer material of the capping dielectric material layer174may be deposited by spin coating to provide a planar horizontal top surface. The vertical distance between the topmost surfaces (such as the top surfaces of the capping segments723) of the dielectric passivation layer72and the top surface of the capping dielectric material layer174may be in a range from 100 nm to 2 microns, such as from 200 nm to 1.5 micron and/or from 300 nm to 1 micron, although lesser and greater vertical distances may also be used. In one embodiment, the ratio of the vertical distance between the topmost surfaces of the dielectric passivation layer72and the top surface of the capping dielectric material layer174to the thickness of the dielectric passivation layer72may be greater than 1.0, and may be in a range from 1.0 to 3.0.

Referring toFIG.8B, a photoresist layer77may be applied over the capping dielectric material layer174, and may be lithographically patterned to form openings therein. In one embodiment, the bonding pads68may be formed as a two-dimensional periodic array of bonding pads68such as a rectangular periodic array or a hexagonal periodic array. In this case, the openings in the photoresist layer77may have the same two-dimensional periodicity as the underlying two-dimensional array of bonding pads68. In one embodiment, the shape of each opening through the photoresist layer77may be circular, and may have a diameter that is less than the pad width PW of the bonding pads68. In one embodiment, the area of each opening through the photoresist layer77may be located entirety within the area of an underlying bonding pad68in a plan view (such as a top-down view). In one embodiment, the entirety of the periphery of each opening through the photoresist layer77may be laterally offset inward from the sidewalls of the underlying bonding pad68. In one embodiment, the ratio of the diameter of an opening in the photoresist layer77to the pad width PW of an underlying bonding pad68to may be in a range from 0.5 to 0.80, although lesser and greater ratios may also be used.

An anisotropic etch process may be performed to transfer the pattern of the openings in the photoresist layer77through the underlying portions of the capping dielectric material layer174. Openings having tapered surfaces are formed through the capping dielectric material layer174and the dielectric passivation layer72.

In an alternative embodiment, the capping dielectric material layer174may comprise a photosensitive polymer material that may be patterned by lithographic exposure and development. In this case, the capping dielectric material layer174may be patterned without use of the photoresist layer77.

Referring toFIG.8C, the photoresist layer77may be removed selective to the capping dielectric material layer174, for example, by ashing or by dissolution in a solvent. An anneal process may be performed to cure the polymer material of the capping dielectric material layer174. Shrinkage of the polymer material of the capping dielectric material layer174causes formation of tapered surfaces around openings through the capping dielectric material layer174. The taper angle (as measured from a vertical direction) of the tapered sidewalls of the capping dielectric material layer174may be in a range from 30 degrees to 75 degrees, such as from 40 degrees to 65 degrees, although lesser and greater taper angles may also be used. In one embodiment, each physically exposed planar top surface portion of the dielectric passivation layer72may have a circular shape with a diameter.

Referring toFIG.8D, an anisotropic etch process may be performed to etch portions of the dielectric passivation layer72that are not masked by the capping dielectric material layer174. A planar top surface portion of each bonding pad68may be physically exposed after the anisotropic etch process. In one embodiment, each physically exposed planar top surface portion of the bonding pads68may have a circular shape with a diameter, which is herein referred to as a bottom pad opening width BPOW. The ratio of the bottom pad opening width BPOW to the pad width PW may be in a range from 0.3 to 0.7, such as from 0.35 to 0.65, although lesser and grater ratios may also be used.

A selective etch process may be optionally performed to recess physically exposed surfaces of the capping dielectric material layer174selective to the dielectric passivation layer72. The recess distance of the capping dielectric material layer174may be in a range from 1 nm to 100 nm, such as from 3 nm to 50 nm, although lesser and greater recess distances may be used. The selective etch process may comprise an isotropic etch process or an anisotropic etch process.

A top periphery of each tapered opening through the capping dielectric material layer174may be circular, and may have a lateral dimension (i.e., a diameter) that is herein referred to as a top pad opening width TPOW. The ratio of the top pad opening width TPOW to the bottom pad opening width BPOW may be in a range from 1.13 to 1.30, such as from 1.16 to 1.24, although lesser and greater ratios may also be used.

Generally, the taper angle of the tapered sidewalls of the capping dielectric material layer174and the taper angle of the tapered sidewalls of the dielectric passivation layer72may be the same or different. The taper angle (as measured from a vertical direction) of the tapered sidewalls of the capping dielectric material layer174may be in a range from 30 degrees to 75 degrees, such as from 40 degrees to 65 degrees, although lesser and greater taper angles may also be used. The taper angle (as measured from a vertical direction) of the tapered sidewalls of the dielectric passivation layer72may be in a range from 35 degrees to 80 degrees, such as from 45 degrees to 70 degrees, although lesser and greater taper angles may also be used. In one embodiment, the taper angle of the tapered sidewalls of the dielectric passivation layer72may be greater than the taper angle of the tapered sidewalls of the capping dielectric material layer174.

A top periphery of each tapered opening through the dielectric passivation layer72may be circular, and may have a lateral dimension (i.e., a diameter) that is herein referred to as an intermediate pad opening width IPOW. A lateral offset Δ may be present between a bottom periphery of a tapered opening through the capping dielectric material layer174and the top periphery of an underlying tapered opening through the dielectric passivation layer72. The A lateral offset Δ may be the same as the recess distance of the selective etch process, and may be in a range from 1 nm to 100 nm, such as from 3 nm to 50 nm, although lesser and greater recess distances may be used.

Referring toFIG.8E, a continuous metallic seed layer802L may be deposited over, and directly on, the physically exposed surfaces of the dielectric passivation layer72, the capping dielectric material layer174, and the bonding pads68. The continuous metallic seed layer802L includes a continuous metallic seed material such as Ti, Ta, W, TiN, TaN, or WN. In one embodiment, the continuous metallic seed layer802L may be deposited by physical deposition process. The continuous metallic seed layer802L may be deposited in the openings through the capping segments723of the dielectric passivation layer72and on physically exposed surfaces of the bonding pads68. The thickness of the continuous metallic seed layer802L may be in a range from 30 nm to 300 nm, although lesser and greater thicknesses may also be used.

Referring toFIG.8F, a photoresist layer87may be formed over the continuous metallic seed layer802L, and may be lithographically patterned to form openings over each of the openings through the capping dielectric material layer174. The thickness of the photoresist layer87may be greater than the height of the copper pillar structures to be subsequently formed. For example, the thickness of the photoresist layer87as measured over the top surface of the capping dielectric material layer174may be in a range from 2 micron to 30 microns, such as from 3 microns to 2020 microns, although lesser and greater thicknesses may also be used. In one embodiment, openings in the photoresist layer87may have a respective shape of a circular cylindrical pillar having a diameter, which is herein referred to as a bump width BW. In one embodiment, each opening in the photoresist layer87may have a respective periphery that is located entirely within the area of an underlying bonding pad PW.

Referring toFIG.8G, copper pillar structures804can be formed within the openings in the photoresist layer87directly on physically exposed metallic surfaces of the continuous metallic seed layer802L, for example, by electroplating. Each electroplate material portion located within a respective opening in the photoresist layer87constitutes a copper pillar structure804. Each copper pillar structure804may have a diameter of the bump width BW. The ratio of the pad width PW to the bump width BW may be in a range from 1.01 to 1.60, although lesser and greater ratios may also be used. The copper pillar structures804may have the same two-dimensional periodicity as the bonding pads68. The ratio of the pad width PW to the periodicity of the two-dimensional array of bonding pads68in any direction of periodicity may be in a range from 0.20 to 0.50, although lesser and greater ratios may also be used.

The lateral offset distance between the sidewall of a copper pillar structure804and a vertical plane including a most proximal portion of a top periphery of a tapered sidewall of an underlying opening through the capping dielectric material layer174is herein referred to as a first lateral offset distance ENA. In one embodiment, the ratio of the first lateral offset distance ENA to the pad width PW is greater than 0.08, and may be in a range from 0.08 to 0.20, such as from 0.11 to 0.16. According to an aspect of the present disclosure, selection of the ratio of the first lateral offset distance ENA to the pad width PW within the range from 0.08 to 0.20 enhances adhesion of the metal bump structures to be formed to the dielectric passivation layer72and the capping dielectric material layer174.

The lateral offset distance between the sidewall of a copper pillar structure804and a vertical plane including a most proximal sidewall of an underlying bonding pad68is herein referred to as a second lateral offset distance ENB. In one embodiment, the ratio of the second lateral offset distance ENB to the pad width PW is greater than 0.07, and may be in a range from 0.07 to 0.18, such as from 0.10 to 0.15. According to an aspect of the present disclosure, selection of the ratio of the second lateral offset distance ENB to the pad width PW within the range from 0.07 to 0.18 enhances adhesion of the metal bump structures to be formed to the dielectric passivation layer72and the capping dielectric material layer174.

Referring toFIG.8H, the photoresist layer87may be removed selective to the copper pillar structures804and the continuous metallic seed layer802L, for example, by ashing. An etch process may be performed to etch physically exposed portions of the continuous metallic seed layer802L. The etch process may comprise an anisotropic etch process or an isotropic etch process. Each patterned portion of the continuous metallic seed layer802L comprises a metallic seed layer802. Each contiguous combination of a metallic seed layer802and a copper pillar structure804constitutes a metal bump structure80.

Referring toFIG.8I, a solder material portion130may be attached to the top surface of each of the metal bump structures80. In one embodiment, each of the metal bump structures80may be located entirely within an area of the respective underlying one of the bonding pads68in a plan view along a direction that is perpendicular to a top surface of the topmost interconnect-level dielectric material layer660.

Generally, metal bump structures80may be formed on the first bonding pads68through the dielectric passivation layer72, Each of the first metal bump structures80comprises a contoured bottom surface including a bottommost surface segment BSS in contact with a top surface of a respective one of the bonding pads68, a first tapered surface segment TSS1in contact with a tapered sidewall of a respective opening through the dielectric passivation layer72, and a first annular surface segment ASS1that overlies the dielectric passivation layer72and having an inner periphery that is laterally offset inward from an outer periphery by a first lateral offset distance ENA that is at least 8% of a width, i.e., the pad width PW, of a respective underlying one of the first bonding pads68. In one embodiment, the diameter of the inner periphery of the first annular surface segment ASS1may be the same as the top pad opening width TPOW. In one embodiment, the outer periphery of the first annular surface segment ASS1may be the same as the bottom periphery of a cylindrical sidewall of the metal bump structure80.

In one embodiment, a capping dielectric material layer174may overlie the dielectric passivation layer72, and each of the metal bump structures80comprises an additional tapered surface segment, i.e., a second tapered sidewall segment TSS2, in contact with a tapered sidewall of a respective opening through the capping dielectric material layer174.

In some embodiments, the capping dielectric material layer174comprises a horizontal top surface that extends over areas that are not covered by the metal bump structures, and a cylindrical surfaces segment of the capping dielectric material layer174extends between a bottom periphery of each of the metal bump structures80and a respective periphery of the horizontal top surface of the capping dielectric material layer174.

In one embodiment, the first annular surface segment ASS1of each of the metal bump structures80contacts a respective annular surface segment of the capping dielectric material layer174, and each of the metal bump structures80comprises an additional annular surface segment (i.e., a second annular surface segment ASS2) in contact with a respective annular surface segment of a top surface of a capping segment723of the dielectric passivation layer72that overlies a respective one of the bonding pads68.

Referring toFIG.9, a first semiconductor die700is illustrated, which includes the third configuration of the exemplary structure illustrated inFIG.8I. An interconnect-containing structure200is provided, which has an array of second metal bump structures280on a mating surface thereof. The array of second metal bump structures280on the interconnect-containing structure200may have a mirror image pattern of the array of first metal bump structures80on the first semiconductor die700.

Generally, the interconnect-containing structure200may comprise any structure that includes metal interconnect structures embedded within dielectric material layers. For example, the interconnect-containing structure200may comprise a second semiconductor die, an interposer, or a packaging substrate. The metal interconnect structures may comprise conventional metal interconnect structures formed in silicon oxide-based dielectric material layers as used in back-end-of-line (BEOL) semiconductor processing steps, or redistribution structures embedded within polymer layers. The first metal bump structures80of the first semiconductor die700may be bonded to the second metal bump structures280of the interconnect-containing structure200through the solder material portions130.

An underfill material portion90may be applied into the gap between the first semiconductor die700and the interconnect-containing structure200. The underfill material portion90may comprise any dielectric underfill material known in the art. The underfill material portion90may contact the solder material portions130, the first metal bump structures80of the first semiconductor die700, and the second metal bump structures280of the interconnect-containing structure200. In one embodiment, the underfill material portion90may contact the horizontal top surface and vertical sidewalls (such as cylindrical surface segments) of the capping dielectric material layer174.

In one embodiment, the third configuration of the exemplary structure may comprise first metal interconnect structures located within first interconnect-level dielectric material layers (610,620,630,640,650,660); first bonding pads68located on a topmost first interconnect-level dielectric material layer660and electrically connected to a respective one of the first metal interconnect structures; a dielectric passivation layer72located on the topmost first interconnect-level dielectric material layer660and the first bonding pads68; and first metal bump structures80extending through the dielectric passivation layer72and located on the first bonding pads68. Each of the first metal bump structures80comprises a contoured bottom surface including a bottommost surface segment in contact with a top surface of a respective one of the bonding pads68, and an annular surface segment that overlies, and is vertically spaced from, the dielectric passivation layer72and having an inner periphery that is laterally offset inward from an outer periphery by a lateral offset distance that is at least 8% of a width of a respective underlying one of the first bonding pads68. In one embodiment, the capping dielectric material comprises a polymer material.

Referring toFIG.10, a flowchart illustrates steps for forming a semiconductor structure according to an embodiment of the present disclosure.

Referring to step1010andFIGS.1and2A, first metal interconnect structures are formed within first interconnect-level dielectric material layers (610,620,630,640,650,660) of a first semiconductor die.

Referring to step1020andFIGS.2B,6A, and8A, first bonding pads68are formed on a topmost first interconnect-level dielectric material layer660. The first bonding pads68are electrically connected to a respective one of the first metal interconnect structures.

Referring to step1030andFIGS.2C,6A, and8A, a dielectric passivation layer72may be formed over the topmost first interconnect-level dielectric material layer660and the first bonding pads68.

Referring to step1040andFIGS.2D-2L,3,4,5A,5B,6B-6E,7,8A-8I, and9, forming first metal bump structures80may be formed on the first bonding pads68through the dielectric passivation layer72. Each of the first metal bump structures80comprises a contoured bottom surface including a bottommost surface segment BSS in contact with a top surface of a respective one of the bonding pads68, and an annular surface segment ASS1that overlies the dielectric passivation layer72and having an inner periphery that is laterally offset inward from an outer periphery by a lateral offset distance that is at least 8% of a width of a respective underlying one of the first bonding pads.

Referring to all drawings and according to various embodiments of the present disclosure, a semiconductor structure may include a semiconductor die700, wherein the semiconductor die700includes: metal interconnect structures located within interconnect-level dielectric material layers (610,620,630,640,650,660); bonding pads68located on a topmost interconnect-level dielectric material layer660and electrically connected to a respective one of the metal interconnect structures; a dielectric passivation layer72located on the topmost interconnect-level dielectric material layer660, wherein the dielectric passivation layer72comprises a dielectric passivation material blocking diffusion of hydrogen and moisture; and metal bump structures80extending through the dielectric passivation layer72and located on the bonding pads68, wherein each of the metal bump structures80comprises a contoured bottom surface including a bottommost surface segment BSS in contact with a top surface of a respective one of the bonding pads68, a tapered surface segment TSS1in contact with a tapered sidewall of a respective opening through the dielectric passivation layer72, and an annular surface segment ASS1that overlies the dielectric passivation layer72and having an inner periphery that is laterally offset inward from an outer periphery by a lateral offset distance that is at least 8% of a width PW of a respective underlying one of the bonding pads68.

In one embodiments, the dielectric passivation layer may include a horizontally-extending segment contacting the topmost interconnect-level dielectric material layer, vertically-extending segments contacting sidewalls of the bonding pads, and capping segments contacting an annular peripheral portion of a top surface of each of the bonding pads. In one embodiment, the semiconductor structure may further include a capping dielectric material layer overlying the dielectric passivation layer, wherein each of the metal bump structures comprises an additional tapered surface segment in contact with a tapered sidewall of a respective opening through the capping dielectric material layer. In one embodiment, the capping dielectric material layer may include an additional dielectric passivation material. In one embodiment, each of the dielectric passivation material and the additional dielectric passivation material may be selected from silicon nitride and silicon carbide nitride. In one embodiment, the capping dielectric material may include a polymer material. In one embodiment, the capping dielectric material layer may include a horizontal top surface that extends over areas that are not covered by the metal bump structures. In one embodiment, the annular surface segment of each of the metal bump structures may contact a respective annular surface segment of the capping dielectric material layer; and each of the metal bump structures may include an additional annular surface segment in contact with a respective annular surface segment of a top surface of a capping segment of the dielectric passivation layer that overlies a respective one of the bonding pads. In one embodiment, the annular surface segment of each of the metal bump structures may contact a respective annular surface segment of the dielectric passivation layer. In one embodiment, each of the metal bump structures may be located entirely within an area of the respective underlying one of the bonding pads in a plan view along a direction that is perpendicular to a top surface of the topmost interconnect-level dielectric material layer. In one embodiment, the semiconductor structure may also include an interconnect-containing structure that may include additional metal bump structures and selected from a second semiconductor die, an interposer, or a packaging substrate, wherein the metal bump structures of the semiconductor die is bonded to the additional metal bump structures of the interconnect-containing structure through solder material portions. In one embodiment, the semiconductor structure may also include an underfill material portion contacting the solder material portions, the metal bump structures of the semiconductor die, and the additional metal bump structures of the interconnect-containing structure.

Referring toFIGS.1-10and according to various embodiments of the present disclosure, a semiconductor structure may include a first semiconductor die700and an interconnect-containing structure200, wherein the first semiconductor die700includes: first metal interconnect structures located within first interconnect-level dielectric material layers (610,620,630,640,650,660); first bonding pads68located on a topmost first interconnect-level dielectric material layer660and electrically connected to a respective one of the first metal interconnect structures; a dielectric passivation layer72located on the topmost first interconnect-level dielectric material layer660and the first bonding pads68; and first metal bump structures80extending through the dielectric passivation layer72and located on the first bonding pads68, wherein: each of the first metal bump structures80comprises a contoured bottom surface including a bottommost surface segment BSS in contact with a top surface of a respective one of the bonding pads68, and an annular surface segment ASS1that overlies the dielectric passivation layer72and having an inner periphery that is laterally offset inward from an outer periphery by a lateral offset distance that is at least 8% of a width PW of a respective underlying one of the first bonding pads68; the interconnect-containing structure200comprises second metal bump structures280and is selected from a second semiconductor die, an interposer, or a packaging substrate; and the first metal bump structures80are bonded to the second metal bump structures280through solder material portions130.

In one embodiment, the semiconductor structure may also include a capping dielectric material layer contacting the dielectric passivation layer and the contoured bottom surfaces of the first metal bump structures, wherein each of the metal bump structures comprises an additional tapered surface segment in contact with a tapered sidewall of a respective opening through the capping dielectric material layer, and wherein an underfill material portion contacts the capping dielectric material layer. In one embodiment, the semiconductor structure may also include an underfill material portion contacting a horizontal surface and vertical sidewalls of the dielectric passivation layer.

The metal bump structures80of the present disclosure use a large ratio of the first lateral offset distance ENA to the pad width PW that is at least 0.08 and uses a small ratio of the top pad opening width TPOW to the bottom pad opening width BPOW that is less than 1.30. This feature provides the benefit of suppressing delamination of the metal bump structures80from the dielectric passivation layer72and the capping dielectric material layer (74,174) during manufacture of a semiconductor die700, during formation of a bonded assembly, and during subsequent usage of the bonded assembly. In some embodiments, the bump configuration may reduce or prevent the interfacial delamination between UBM structures and underlying polymer material portions after a chip package reliability test and/or during operation of the chip package.

Typically, prior art packaging structures are prone to generation of a high density of delamination at the interfaces between UBM structures and polymer material portions due to small dimensions of openings in the polymer material portions. The probability of delamination between the UBM structures and the underlying polymer material portions is the highest in an annular edge region adjacent to the periphery of a wafer1110as illustrated inFIG.11. Thus, a subset of the semiconductor dies1120including corner portions located within the annular edge region tends to have high failure rates during a reliability test or during usage due to delamination of the UBM structures. The various embodiments of the present disclosure provides configurations in which the adhesion between the UBM structures and underlying dielectric material portions is enhanced, and thus, delamination of the UBM structures is reduced. The adhesion may be enhanced through an increase in the top pad opening width TPOW relative to the lateral dimensions of the bonding pads68, through reduction of the thickness of the capping dielectric material layer74(which may comprise a polymer material), through a reduction in the ratio of the top pad opening with TPOW to the bottom pad opening width BPOW, and/or additional features of the present disclosure as described above.

The various embodiments of the present disclosure enable manufacture of advanced chap package structures including highly scaled semiconductor devices such as 5 nm semiconductor devices or 3 nm semiconductor devices. Simulations show that mechanical stress at the interface between the metal bump structures80and the dielectric passivation layer72and/or the capping dielectric material layer (74,174) may decrease by about 30% compared to prior art devices.

While the present disclosure is described using embodiments in which the dielectric passivation layer72and/or the capping dielectric material layer (74,174) are formed in the first semiconductor die700, it is understood that a mirror image structure may be formed within the interconnect-containing structure200of the present disclosure. Specifically, the interconnect-containing structure200may comprise a dielectric passivation layer72and/or a capping dielectric material layer (74,174), and the second metal bump structures280of the interconnect-containing structure200may comprise the same features as the first metal bump structures80of the first semiconductor die700.