Wide range charge balancing capacitive-to-digital converter

A capacitive-to-digital converter is provided which includes: sensor, offset and reference capacitors, an integrator circuit and a demodulation circuit. The sensor capacitor is switched according to a first clock and the offset capacitor according to a second clock, which has a higher switching frequency. The reference capacitor is switched according to a return signal from the converter's output. The integrator circuit includes an integrator capacitor, and has first and second nodes, with the sensor, offset and reference capacitors each being switched to the first and second nodes based on the respective first clock, second clock or return signal. The demodulation circuit receives and converts output of the integrator circuit into a digital output. The higher frequency clocking of the offset capacitor allows for a reduction in capacitance of the offset, reference or integrator capacitor, and the multiclocking of the converter allows for use of a multireferencing to the sensor capacitor.

BACKGROUND

The present invention relates in general to a wide range capacitive-to-digital charge balancing converter based on complementary metal-oxide-semiconductor (CMOS) devices for accurate capacitance-to-digital conversion of a capacitive sensor signal.

Capacitive sensor signal-conditioning integrated circuits, such as the cLite™ capacitive sensor signal conditioner (or cLite™ ASSP (Application Specific Standard Product)) available from Zentrum Mikroelektronik Dresden (ZMD) AG of Dresden Germany, comprise a capacitive-to-digital converter and are able to convert a capacitance within a selectable range (for example, 2-260 pF in the case of the cLite™ signal conditioner) to a corresponding digital value. Advantageously, the cLite™ signal conditioner currently provides a 14-bit resolution and very high accuracy over wide ranges of capacitances and temperatures, and can be used as input for microcontrollers or other switch applications.

Capacitive sensors are widely used in many MEMS sensing elements, such as pressure sensors for hydraulic control systems, humidity sensors and liquid level gauges. Such sensors do not touch or make direct contact with the system or device being sensed, and thus the sensors are advantageous for industrial linear and angular position sensors and contactless potentiometers, even under harsh or explosive environmental conditions.

For a capacitive-to-digital converter (CDC) covering a wide range, such as the cLite™ capacitive sensor and signal conditioner noted above, on-chip offset, reference and integrator capacitors must conventionally collectively be as large as or larger than the sensor capacitor. This can be impractical and costly depending on the desired implementation.

BRIEF SUMMARY

In one aspect, the shortcomings of the prior art are overcome and additional advantages are provided through the provision of a charge balancing capacitive-to-digital converter comprising a sensor capacitor, an offset capacitor, a reference capacitor, an integrator circuit, and a demodulation circuit. The sensor capacitor is switched according to a first clock signal of a first clock schedule, and the offset capacitor is switched according to a second clock signal of a second clock schedule, wherein the second clock schedule is of higher frequency than the first clock schedule. The reference capacitor is provided for charge balancing and is switched according to a return signal from an output of the charge balancing capacitive-to-digital converter. The integrated circuit comprises an integrator capacitor, and has a first input node and a second input node. The sensor capacitor, offset capacitor and reference capacitor are each switched to the first input node or the second input node based on the respective first clock schedule, second clock schedule or return signal. The demodulation circuit receives and converts output of the integrator circuit into a clocked digital output, wherein the second clock schedule being of higher frequency than the first clock schedule allows a reduction in capacitance of at least one of the offset capacitor, reference capacitor or integrator capacitor.

Advantageously, provided herein is a wide range capacitive-to-digital charge balancing converter with high resolution and low manufacturing cost. This is accomplished, in one embodiment, by employing both a multi-clocking and a multi-referencing approach.

DETAILED DESCRIPTION

FIG. 1shows an example of a charge balancing capacitive-to-digital converter100. Converter100has as a main input CSENSORwhose output node is connected over a first switch110ato the negative IntNode of an operational amplifier (or integrator)150and over a second switch110bto the positive input of operational amplifier150. As shown, the first switch is clocked with a clock signal CLK and the second switch with the inverted CLK. The output node of operational amplifier150is bridged with the IntNode thereof by an integrator capacitor CINTand is connected via a demodulator160to an input of an AND gate170, which outputs a signal ZOUT (Z). The other input of AND gate170, as well as the other input of demodulator160, is connected to receive clock signal CLK (N).

The input of CSENSORis connected to REFP over a first switch112a, which is clocked by CLK, and to REFN over a second switch112b, clocked by inverted CLK. The difference between REFP and REFN is the reference voltage110. Capacitances COFFand CREFare coupled in parallel with CSENSOR. These capacitances are switched ON or OFF by respective switches114a,114band116a,116bwhich are clocked by CLK and inverted CLK, in the case of COFF, and by a return signal171from the output ZOUT (Z) of converter200, in the case of CREF.

The operating principal is
N*CSENSOR*VREF−N*COFF*VREF−Z*CREF*VREF=0
where VREF=(REFP−REFN).

The capacitor CSENSOR, which is the sensor capacitance, adds charge to IntNode every clock cycle CLK(N), while the capacitance COFF, which is the on-chip offset capacitance, subtracts charge from IntNode every clock cycle CLK (N).

CREFis the on-chip reference capacitance, and it subtracts charge from IntNode every clock cycle that it is enabled by ZOUT (Z).

ZOUT (Z) enables CREFwhen needed to balance the net charge, and the ratio of Z/N is:
Z/N=(CSENSOR−COFF)/CREF

A charge balancing C/D converter such as depicted inFIG. 1shows very low sensitivity to circuit components, but does have limitations.

On-chip capacitors (COFF, CREF, and CINT) thus conventionally have to collectively be greater than or equal to CSENSOR. This imposes a limitation on the size of CSENSOR.

FIG. 2illustrates an enhanced capacitive-to-digital charge balancing converter, generally denoted200, in accordance with aspects of the present invention. Converter200advantageously employs multi-clocking and multi-referencing, as described below.

As illustrated inFIG. 2, capacitances CSENSOR, COFFand CREFare connected to the negative input (i.e. IntNode) of operational amplifier (or integrator)250, or alternatively, to the positive input of operational amplifier250via separate switches210a,210b,211a,211b.

Specifically, switch210aconnects/disconnects the output signal of capacitance CSENSORwith IntNode, and is clocked by a first clocking signal Clk_S, while switch210bconnects/disconnects the output signal of capacitance CSENSORwith the positive input of operational amplifier250, and is clocked by the inverted first clocking signal Clk_S.

The offset and reference capacitances (COFFand CREF) are coupled via switches211a,211balternatively to the negative input IntNode or the positive input of operational amplifier250using a second clocking signal CLK, and inverted second clocking signal CLK, as shown.

The input of CSENSORis connected with REFP over a first switch212a, which is clocked by first clocking signal CLK_S, and with REFN over a second switch212b, which is clocked by an inverted CLK_S. Thus, reference voltage210(VREF) equals REFP−REFN.

The inputs of COFFand CREFare connected/disconnect alternatively to ground (GND) or VDD so that the voltage over the capacitances COFFand CREFalternates from GND to VDD depending on the setting of the switches214a,214b,216a,216bon the input side. Switches214a,214bon the input side of COFFare clocked with the second clocking signal CLK and inverted CLK, respectively, while switches216a,216bon the input side of CREFare clocked with return signal271from the output (ZOUT (Z)) of converter200.

As shown, the output node of operational amplifier250is bridged with the IntNode thereof via an integrator capacitor CINTand is connected via a demodulator260with an input of an AND gate270, which outputs signal ZOUT (Z). The other input of AND gate270is connected to receive second clock signal CLK (N), while the clock input to demodulator260receives first clock signal CLK_S (N/MULTF). Multclocking is accomplished by configuring the first clocking schedule of the first clocking signal to be a factor (MULTF) lower than the second clocking schedule of the second clocking signal. The second clocking schedule for clocking signal CLK can be written as CLK (N), where N is the number of clocks per unit of time. Thus, the first clocking schedule for clocking signal CLK_S can be written as CLK_S (N/MULTF), where N/MULTFis the number clocks of CLK_S, per same unit of time.

FIG. 2shows an example in which the second to first clock signals (CLK, CLK_S) are in a 2:1 mode, but (by way of example) clocking in a 1:1, 4:1 or 8:1 mode is also possible. Details of these modes are shown inFIG. 4, which is described further below.

FIG. 3illustrates an example of 2:1 (CLK:CLK_S) clocking mode, where CREFand COFF(shown inFIG. 2) each receives two clock pulses to transfer enough charge to balance the charge added by a single clocking of CSENSOR. In order to keep CINTreasonably small, the reference voltage (REFP−REFN) to CSENSORis reduced (e.g., [REFP-REFN]=⅝ VDD−⅜ VDD).

InFIG. 4a reference input voltage selector400is shown receiving a multi-clocking select signal (MULTICLKSEL[1:0]), and providing a VREF210(REFP−REFN) to the charge balancing C/D converter ofFIG. 2. This clocking device would be connected to the respective inputs REFP and REFN of converter shown inFIG. 2. As depicted, reference input voltage selector400is clocked by clock signal MULTICKLSEL[1:0], which is determined (for example) by comparing the second clock schedule of the second clock signal CLK to the first clock schedule of the first clock signal CLK_S.

The reference voltage selector has two signal generators420a,420b, generating two output signals as input for a reference buffer block430, which outputs REFP and REFN.

A shown, the inputs to the signal generators are connected to respective nodes of a voltage divider comprising series connected resistors410a-410i, which generate the desired ratios.

Advantageously, REFP and REFN scale with the multi-clock selection in such a way that when higher clocking ratios are used, a smaller quantity (REFP−REFN) is used.

As the quantity (REFP−REFN) reduces, less charge is added/subtracted by CSENSOR& CREF. This allows CINTto remain reasonable in size.

Note that CINTcould be kept small by always using [REFP, REFN]=[17:32, 15/32], but by using such a small reference voltage when measuring small sensor capacitances (e.g., 2 pF) the noise floor would rise, which means kT/C noise, for instance, would rise.