Method for the formation of transistors PDSO1 and FDSO1 on a same substrate

The present invention relates to a method for forming an electronic device intended to accommodate at least one fully depleted transistor of the FDSOI type and at least one partially depleted transistor of the PDSOI type, from a stack of layers (10) comprising at least one insulating layer (100) topped with at least one active layer (200) made of a semiconductor material, the method comprising at least one step of dry etching and one step of height adjustment between at least two etched elements.

TECHNICAL FIELD OF THE INVENTION

The present invention relates to the field of micro-electronics and more particularly the field of partially depleted transistors and fully depleted transistors mounted on the same semiconductor wafer.

PRIOR ART

In the field of integrated circuits formed from elaborate substrates of the semiconductor-on-insulator type, also referred to by their acronym SOI forSemiconductor On Insulator, two types of transistors are generally used: partially depleted transistors, also referred to by their acronym PDSOI, forPartially Depleted Semiconductor On Insulator, and fully depleted transistors, also referred to by their acronym FDSOI, forFully Depleted Semiconductor On Insulator.

An elaborate substrate is characterised by the presence of a thin surface layer of single-crystal semiconductor, like single-crystal silicon, for instance, supported by a continuous insulating oxide layer, for instance silicon oxide, also called buried oxide, or BOX, the acronym forBuried Oxide Layer. The solidity and mechanical strength of the assembly are provided by a layer supporting the BOX and which is the body of the SOI substrate, often calledbulkto indicate that the original substrate is generally made of a solid semiconductor material, silicon, for instance, Such structure has many advantages for making MOS transistors, the acronym forMetal-Oxide-semiconductor. More particularly, it enables a drastic reduction of stray capacities because of the presence of the continuous insulating layer.

Both FDSOI and PDSOI transistor types meet specific needs in the field of analog and digital electronics, and specifically in the field of radio-frequency electronics.

Electronic devices comprising FDSOI transistors and PDSOI transistors on the same electronic chips are also known from the prior art.

The prior art provides several solutions for forming such type of electronic devices. However some solutions are relatively complex and expensive to be implemented for reproducibly obtaining, on the same chip, high-performance transistors. A need thus exists for a simpler production and reduced production costs for such electronic devices.

SUMMARY OF THE INVENTION

The present invention relates to a method for forming an electronic device intended to accommodate at least one fully depleted transistor (FDSOI) and at least one partially depleted transistor (PDSOI), from a stack of layers comprising at least one insulating layer topped with at least one active layer made of a semiconductor material, with the method comprising at least the following steps:Forming at least one shallow trench through the thickness of the active layer so as to define, in said active layer, on either side of the shallow trench, at least one first active region whereon at least one partially depleted transistor (PDSOI) is intended to be formed and at least one second active region whereon at least one fully depleted transistor (FDSOI) is intended to be formed;Forming, above the at least one first active region and on a part of the shallow trench, a masking layer, without covering the at least one second active region and without covering a part of the shallow trench;Simultaneously etching, using dry etching, so as to form etched areas:a portion of the thickness of the active layer of the at least one second active region so as to form at least one second thinned active region and to obtain, in the at least one second thinned active region, a smaller thickness of the active layer than in the at least one first active region;at least a part of the thickness of the not covered part of the shallow trench so as to form an etched part of the shallow trench,and the whole masking layer;Adjusting, after the step of dry etching, the height of the surface of the at least one second thinned active region to the height of the surface of said one etched part of the shallow trench.

The present invention makes it possible to form, on the same semiconductor substrate, preferably of the SOI type, a plurality of partially depleted transistors of the PDSOI type and fully depleted transistors of the FDSOI type in a minimum number of steps, i.e. by implementing economical steps in terms of process time savings and as regards the chemistry currently used in the prior art. As a matter of fact, the present invention takes advantage of a synergy of these steps in order to optimize the utility of each one of these, while minimising the number thereof.

Such synergy relies on two steps, i.e. a step of dry etching and a step of forming a sacrificial oxide layer: dry etching makes it possible to simultaneously etch a plurality of different layers and of materials and the sacrificial oxide layer makes it possible to improve the performances of the FDSOI transistor while facilitating the formation of the source and drain areas caused by a screening effect during the subsequent steps of ion implantation.

Dry etching is a step making it possible to quickly and easily thinning one region of the active layer while thinning a portion of the shallow trenches surrounding said thinned region of the active layer.

Advantageously, such step of dry etching makes it possible to remove the masking layer, also called hard mask, of the PDSOI areas as well as to thin one region of the active layer and one portion of the shallow trenches. In order to be able to simultaneously etch three materials having a different nature, so that the desired thinned thickness corresponds to the complete etching of one of the three materials, preferably the masking layer selecting the nature and the structure thereof is a critical point, as is the selection of the dry etching.

Advantageously, one oxide, preferably silicon oxide, obtained by low pressure chemical vapor deposition, also called a LPCVD oxide, i.e. the acronym forLow-Pressure Chemical Vapor Depositionand one oxide, preferably silicon oxide, obtained by chemical vapor deposition executed at a sub-atmospheric pressure, also called a PECVD oxide, i.e. the acronym forPlasma-enhanced Chemical Vapor Depositionhave cleverly been so selected as to meet such requirement. The PECVD oxide forms the insulating trenches whereas the LPCVD oxide forms the masking layer. Thus, one single step of etching thus makes it possible to etch three different materials under the desired thinning and removing conditions.

However, such step of dry etching leads to the forming of micro-trenches at the junction between the thinned region of the active layer and the etched parts of the shallow trenches. Such micro-trenches directly result from the nature of the dry etching at the interface between two different materials and cause the subsequent forming of rails made of polycrystalline material in the subsequent steps of the formation of the FDSOI transistors. Such phenomenon calledMicrotrenching, is well known to the persons skilled in the art and would have dissuaded these persons to use dry etching to thin the active layer as well as a part of the shallow trenches.

As a matter of fact, it may seem that such micro-trenches suggest that the performances of the FDSOI transistors will be affected. However, when developing the present invention, the effects of such micro-trenches on the transistors performances could be controlled. Surprisingly, the step of adjusting the height of the surface of the at least one second thinned active region to the height of the surface of said etched part of the shallow trench makes it possible to control the structure of such micro-trenches, so that these do not affect the performances of the FDSOI transistors.

As regards the use of a sacrificial oxide layer, it provides at least three distinct functions in synergy with the issue of reducing the production costs and with the preceding step of dry etching.

As a matter of fact, such sacrificial oxide layer makes it possible, on the one hand, to improve the surface condition of the thinned active layer by eliminating the surface defects from the thinned region of the active layer induced by the dry etching, and on the other hand, to adjust the height of such thinned region of the active layer to the height of the surface of the etched part of the insulating trench, so as to eliminate the nuisance of the micro-trenches and optimise the performances of the FDSOI transistor, while preserving easily executable steps to obtain such transistor.

The present invention also relates to an electronic device intended to accommodate at least one fully depleted transistor of the FDSOI type and at least one partially depleted transistor of the PDSOI type, produced with the method according to the present invention.

The drawings attached are given as examples and are not limiting to the invention. Such drawings are schematic representations and are not necessarily to scale with a practical application. Particularly, the relative thickness of the various layers and substrates are not a representation of reality.

DETAILED DESCRIPTION OF THE INVENTION

PDSOI transistor or more generally PDSOI device mean a device produced in an area, the thickness of which is greater than the maximum depletion layer Wd_max.

FDSOI transistor or more generally FDSOI device mean, a device produced in an area, the thickness of which is smaller than the maximum depletion layer Wd_max.

The thickness of such maximum depletion layer Wd_maxis given by the equation:
Wd_max=(2εsiε02φF/qNA)1/2
where:εs: relative dielectric constant of silicon;ε0: capacitivity of free space;φF=(kT/q) In(NA/ni)−;k: Boltzmann constant;T: temperature;nl: silicon carrier intrinsic concentration;q: elementary electric charge;NA: concentration of impurities.

Everything at ambient temperature (300K) gives φF=0.0259 In(NA/1.5×1010)

In the following description,PDSOI areameans an area of the substrate intended to receive at least one PDSOI transistor and comprising an active layer and a part of the shallow trenches located on either side of the considered active layer.FDSOI areameans an area of the substrate intended to receive at least one FDSOI transistor and comprising an active layer and a part of the shallow trenches located on either side of the considered active layer.PDSOI active regionmeans one region of the substrate comprising an active layer intended for forming at least one PDSOI transistor.FDSOI active regionmeans one region of the substrate comprising an active layer intended for forming at least one FDSOI transistor.PECVD oxidemeans one oxide formed by plasma-enhanced chemical vapor deposition.LPCVD oxidemeans one oxide formed by sub-atmospheric chemical vapor phase deposition.

It should be noted that, within the scope of the present invention:wafer,substrateorchipor the equivalents thereof refer to one device advantageously comprising one or more semiconductor layer(s) and so configured as to receive the formation of semiconductor structures like transistors for instance.

It should be noted that, within the scope of the present invention:SOI Substrate, or the equivalents thereof refer to a substrate characterised by the presence of a single-crystal semiconductor surface layer, like single-crystal silicon, for instance, supported by a continuous insulating oxide layer, for instance silicon oxide, also called buried oxide, or BOX, the acronym forburied oxide layer. The solidity and mechanical strength of the assembly are provided by a supporting layer, for instance made of silicon.

It should be specified that, within the scope of the present invention,over,on the top oforunderlyingor the equivalents thereof do not necessarily meanin contact with. Then, for instance, depositing a first layer on a second layer, does not necessarily mean that both layers are in direct contact with one another, but means that the first layer at least partially covers the second layer and is either in direct contact therewith, or spaced therefrom by another layer or another element.

In the following description, thickness is generally measured in directions perpendicular to the plane of the lower face of the layer to be etched or of a substrate whereon the lower layer has been deposited. Thus, thickness is thus generally measured along a vertical direction in the figures shown.

In the following description, thesame heightor the equivalents thereof, mean that two different surfaces are located in the same plane, parallel to the substrate, i.e. relative to the figures of the not restrictive example, that two different surfaces are located in the same horizontal plane.

In the following description,levelling,height adjustingor the equivalents thereof, mean modifying the height of a layer so that the surface thereof is located in the same plane as the surface of another layer, typically in the same horizontal plane relative to the figures in the not restrictive example.

Within the scope of the present invention, an organic or organo-mineral material which can be formed mechanically or by being exposed to an electron beam, a photon beam or an X-ray beam, is called a resin.

In the following description,etchingmeans the partial or total removal of a given material.

In the following description,wet etchingmeans an etching technique which requires using wet chemistry, i.e. baths, generally.

In the following description,dry etchingmeans an etching technique in a non wet medium, and preferably using plasma.

Compliantmeans layer geometry having, within production tolerances, a constant thickness, in spite of the changes in the direction of layers, for instance on vertical sides of some structures.

Stepdoes not necessarily means that the actions executed during one step are simultaneous or immediately successive. Some actions of one first step can be followed by actions of a different step, and other actions of the first step can be resumed afterwards. Thus, “steps” does not necessary mean unit actions which can be separated in time and in the sequence of the process phases.

Structureof a material, means the distribution in space of the elementary components thereof, as regards crystallography. Two layers of the same material can thus have the same nature but different crystal structures.

Natureof a material, means the chemical composition and/or the crystal structure thereof. Two layers can thus have the same chemical composition but a different nature as regards crystallography.

Prior to giving a detailed description of the various embodiments of the invention, optional characteristics which may be used in association or alternately with the above characteristics are enumerated hereunder:Advantageously, the shallow trench110comprises at least one oxide formed by plasma-enhanced chemical vapor deposition, which is called a PECVD oxide in the following description.Advantageously, the masking layer330comprises at least one oxide formed by sub-atmospheric chemical vapor phase deposition, which is called a LPCVD oxide in the following description.Advantageously, the PECVD oxide is a silicon oxide.Advantageously, the LPCVD oxide is a silicon oxideThe conditions selected for the deposition and the nature of the PECVD and LPCVD oxides determine the respective etching rates thereof during the step of dry etching400. According to one embodiment of the present invention; the conditions for forming and etching these two oxides are so configured that the total etching time of the LPCVD oxide corresponds to the etching of the desired thickness of the PECVD oxide.Advantageously, the dry etching400, the oxide110formed by plasma-enhanced chemical vapor deposition and the oxide330formed by sub-atmospheric chemical vapor phase deposition are configured, specifically the thickness of such oxides and/or the etching selectivity thereof, so that the time required for forming the at least one etched portion of the shallow trench112corresponds to the time required for etching the whole thickness of the masking layer330.Advantageously, the step of adjusting the height of the surface221aof the at least one second thinned active region220ato the height of the surface113of said etched part of the shallow trench112comprises at least the following steps:oxidation of at least one portion of the second thinned active region220aso as to form a sacrificial oxide layer225;at least partial removal of the sacrificial oxide layer225so as to form a residual sacrificial oxide layer230and so that the surface231of the residual sacrificial oxide layer230is at the same height as the surface113of the not covered part of the etched shallow trench112.Advantageously, the sacrificial oxide layer225is formed by a step of oxidation on at least a part of the thickness of the at least one second thinned active region220a.According to one embodiment, the sacrificial oxide layer225has a thickness preferably ranging from 2 nm to 20 nm, advantageously from 5 nm to 15 nm, and preferably equal to 7.5 nm,Advantageously, the sacrificial oxide layer225has a thickness preferably ranging from 6 nm to 8 nm, and advantageously equal to 5 nm,Advantageously, the residual sacrificial oxide layer230has a thickness preferably ranging from 0 nm to 10 nm, advantageously from 2 nm to 7 nm, and preferably equal to 5 nm,Advantageously, the dry etching400is a plasma etching.Advantageously, said plasma is a high density plasma.Advantageously, the parameters for the plasma dry etching are:1stphase (also called breakthrough phase)Source power TCP 500 W;Pressure: 4 mT;Helium pressure (He) at the wafer backside (He Cooling) 8T;CF4 50 sccm (Standard Cubic Centimeter per Minute), as measured under standard temperature and pressure conditions;Bias 50 W;2ndphase (also called silicon etching)Source power TCP 600 W;Pressure: 25 mT;Helium pressure at the wafer backside (He Cooling) 8T;C12 125 sccm O2 19 sccm;Bias 400 W;3rdphase (also called final cleaning)Source power TCP 1200 W;Pressure: 10 mT;Helium pressure at the wafer backside (He Cooling) 8T;Argon (Ar) 120 sccm/O2 12 sccm/CF4 60 sccm;Bias 0 W.Advantageously, the active region200has an initial thickness preferably ranging from 100 nm to 200 nm, advantageously from 125 nm to 180 nm, and preferably equal to 140 nm,Advantageously, the first active region210has a thickness preferably ranging from 100 nm to 200 nm, advantageously from 125 nm to 180 nm, and preferably equal to 140 nm,Advantageously, the at least one second thinned active region220ahas a thickness preferably ranging from 25 nm to 100 nm, advantageously from 50 nm to 85 nm, and preferably equal to 70 nm,Advantageously, the step of dry etching400is followed by a step of wet cleaning the surfaces of said etched areas.Advantageously, the step of wet cleaning the surface of said etched areas is so configured as to eliminate residual materials resulting from the step of dry etching400.Advantageously, the residual materials are oxides of the semiconductor material.Advantageously, the shallow trench110contacts the insulating layer100.Advantageously, the step of forming the masking layer330above the at least one first active region210and on at least a part of the shallow trench110follows the forming of an intermediate oxide layer310on said first active region210.Advantageously, the step of forming the intermediate oxide layer310on the first active region210is followed by the forming of a nitride layer320above the intermediate oxide layer310, so that the masking layer330at least partially contacts said nitride layer320.According to one embodiment, the insulating layer100has a thickness ranging from 50 nm to 1,000 nm, advantageously from 200 nm to 600 nm and preferably equal to 400 nm.Advantageously, the intermediate oxide layer310has a thickness ranging from 1 nm to 10 nm, preferably from 2 nm to 7 nm, and preferably equal to 5 nm,Advantageously, the nitride layer320has a thickness ranging from 10 nm to 150 nm, and preferably ranging from 50 nm to 100 nm, and preferably equal to 70 nm,According to one embodiment, the thickness of the STIs110ranges from 100 nm to 200 nm, advantageously from 125 nm to 180 nm, and preferably equal to 140 nm,Advantageously, the thickness of the masking layer330ranges from 20 nm to 100 nm, preferably from 35 nm to 65 nm, and advantageously equal to 42.5 nm,Advantageously, the conditions for forming such PECVD oxide are as follows:1stphase:O22200 sccm,SiH440 sccm,H21,200 sccmHigh frequency power (13.56 MHz) 0 WLow frequency power (250 kHz) 3,000 W2ndphase:O277 sccm,SiH440 sccm,H21,200 sccmHigh frequency power (13.56 MHz) 2,450 WLow frequency power (250 kHz) 2,750 W3rdphase:O2104 sccm,SiH455 sccm,H21,200 sccmHigh frequency power (13.56 MHz) 3,000 WLow frequency power (250 kHz) 2,750 WAdvantageously, the conditions for forming such masking layer330using LPCVD are as follows: Temperature 650° C., pressure 250 mTorr, TEOS rate 100 CC/minute.Advantageously, the step of wet cleaning is executed using hydrofluoric acid of the DHF/SC1/SC2 type and comprises the following parameters:DHF18 SC1 SC2 on FSINH4OH 170 cc/mn Hot DI Water 1,700 cc/mn 88 secSC1: H2O2 200 cc/mn NH4OH 125 cc/mn Hot DI Water 1,500 cc/mn 45 secNH4OH 40 cc/mn Hot DI Water 1,600 cc/mn 180 secSC2: HCL 40 cc/mn H202=200 cc/m, Hot DI Water 1,600 cc/mn

One exemplary embodiment of the present invention will now be explained in greater details while referring to the figures.

The present invention provides a method for producing PDSOI transistors and FDSOI transistors on the same SOI substrate10. Such a substrate10comprises a thin surface layer made of a single-crystal semiconductor, advantageously single-crystal silicon, also called an active layer200. Such active layer200is supported by an insulating layer100. Such active layer200is also supported by a supporting layer, not shown.

According to one embodiment, the result of which is shown inFIG. 1, from such SOI substrate, an intermediate oxide layer310is formed on the whole surface of the substrate. Such intermediate oxide layer310preferably comprises silicon oxide.

According to one embodiment, one nitride layer320is deposited onto the whole intermediate oxide layer310. Such nitride layer320is advantageously formed using LPCVD. According to one embodiment, the chemical composition of such nitride layer is Si3N4.

Once both layers310and320are formed, a series of steps of lithography makes it possible to form so-called STIs, the acronym forShallow trench isolation110illustrated inFIG. 1.

Very advantageously; such STIs110are formed from one PECVD oxide, and preferably one PECVD silicon oxide.

Preferably, The STIs contact the BOX100as shown inFIG. 1.

The persons skilled in the art know several techniques for forming STIs. In the present invention. the criterion of the oxide nature is extremely important. As a matter of fact, such oxide is preferably a PECVD silicon oxide.

One process which can be considered for forming such STIs100is based on the utilization of conventional lithography techniques, so as to form trenches in the substrate10. Such trenches are then filled with an oxide, advantageously one PECVD silicon oxide.

On either side of such STIs110, regions of the active layer200are defined. A first active region210is called a PDSOI active region since it is intended to form PDSOI transistors700. A second active region220is called a FDSOI active region since it is intended to form FDSOI transistors600.

Once such regions210and220are defined by forming the STIs110, a masking layer330is deposited, preferably in a compliant deposition, so as to obtain the layer330illustrated inFIG. 1.

Very advantageously; the masking layer330comprises one LPCVD oxide, and preferably one LPCVD silicon oxide. Such masking layer330can also be called ahard mask D.

Once the masking layer330is formed, a substrate as shown inFIG. 1is obtained.

Two areas are then defined, as illustrated inFIG. 2:one PDSOI area201comprising one PDSOI active region210, i.e. an active layer210intended to form at least one PDSOI transistor700, and comprising a portion of the STIs110positioned on either side of the active layer210.one FDSOI area202comprising one FDSOI active region220, i.e. an active layer220intended to form at least one FDSOI transistor600, and comprising a portion of the STIs110positioned on either side of the active layer220.

FIG. 2also shows the deposition of a protective layer340above the PDSOI areas. advantageously comprising resin. Such protective layer340is advantageously deposited onto at least one part of the surface331of the masking layer330.

In a preferred embodiment, the protective layer340is deposited so as to cover a portion of the STIs110, preferably about 50% of the surface thereof. It is opened using one of the numerous known lithography processes, for instance photolithography, in case of a photoresist.

FIG. 3illustrates a step of etching the FDSOI areas so as to remove the masking layer330, the nitride layer320and the intermediate oxide layer310. Such step of etching is preferably chemical using fluorocarbon chemistry, for instance. Such preferably wet etching results in exposing the surface221of the FDSOI active region220, as well as at least a portion of the surface of the STIs110.

FIG. 4illustrates the step of dry etching400so configured as to thin the FDSOI area202, and more particularly the active layer220and at least a portion of the STIs110, the portion not covered with the masking layer330.

Advantageously, the step of removing the protective layer340is executed prior to the step of dry etching400. Such removal is advantageously obtained using oxygen plasma. Such removal is preferably followed by wet cleaning so as to eliminate any residue from the protective layer340.

In addition. the native oxide present on the surface of the substrate may advantageously be cleaned using carbon tetrafluoride. Such cleaning then prepares the surfaces of the FDSOI202area during the step of dry etching400.

The step of dry etching400, using plasma, preferably high density plasma, aims at thinning the FDSOI area. Such high density plasma is advantageously based on chlorine- and oxygen-based chemistry.

According to one embodiment, dry etching400using high density plasma is so configured as to reach an etching rate of the order of 1 nm per second for the materials considered, and preferably for the active layer220, advantageously made of single-crystal silicon.

Preferably, such dry etching400is subject to an etched thickness measure feedback loop, advantageously by interferometry. Thus etching is performed in multiple successive etching operations separated by an interferometric measurement of the consumed thickness of the materials considered and preferably of the active layer220.

Advantageously, such dry etching400is so configured as to thin the active layer220of the FDSOI region.

Preferably, such dry etching400is so configured as to thin a portion of the STIs110, i.e. a portion of the FDSOI region.

Preferably, such dry etching400is so configured as to totally remove the masking layer330, advantageously from the whole substrate10.

Very cleverly, such dry etching400is so configured as to simultaneously thin two materials having a different nature and remove a third material. Such dry etching400is configured so that the time required for totally removing the masking layer330corresponds to the etching time required for the desired thinning of the portions of the STIs110and the active layer220.

One of the advantages of such step of dry etching400is the possibility of reaching an optimum thickness of the thinned active layer220aof the order of 75 nm for forming FDSOI transistors600.

Such step of dry etching400is particularly innovative since it is executed in a single step, and the active layer220is so thinned as to reach the desired thickness for forming the FDSOI transistors600, the masking layer330is removed from the PDSOI regions and one portion of the STIs110, surrounding the active layers220, is also thinned.

Such step of dry etching400makes it possible not to use multiple chemical etching which is not economical both as regards process costs and time.

The materials used in such step of dry etching400have been specifically selected and formed in order to meet the conditions for the relative etching rates, in order to reach the result shown inFIG. 5.

FIG. 5shows the result of the dry etching400disclosed above. The thinned active layer220aand the etched portions of the STIs112have been formed at the same time as the total removal of the masking layer330.

As a result of such dry etching400, a residual oxide layer410has been formed on all the etched surfaces, for instance on the whole substrate10. This is a residue from the step of dry etching400.

The formation of cavities120can also be noted. Such cavities are called micro-trenches120, because of their geometry, at the vertical interfaces between the active layer220aand the etched parts of the STIs112.

Such micro-trenching120is well known to the persons skilled in the art, and it is traditionally seen at the vertical interfaces between two materials having a different nature when simultaneously etching both materials. This phenomenon is one of the reasons which might turn the persons skilled in the art away from the present invention. As a matter of fact, such structural discontinuity firstly seems to be a defect affecting the performances of the FDSOI transistors600.

However, when developing the present invention, it could rather surprisingly be noted that such structural defects120, i.e. the micro-trenches120, can be reduced, so that they do not affect the performances of the FDSOI transistors600.

As a matter of fact, the shallow trenches120are reduced by adjusting the various chemical etching methods. The depth of the shallow trenches120is thus reduced in the FDSOI transistors areas and prevents, after the etching of the gate polysilicon, the presence of polysilicon filaments, which may be the source of stray connections between the different polysilicon lines of the FDSOI transistors.

As disclosed hereafter, such shallow trenches120are filled with polycrystalline materials during the subsequent steps of forming the FDSOI transistors600and mainly the gates of said FDSOI transistors600.

A step of wet cleaning, illustrated inFIG. 6follows the dry etching400. Such wet cleaning is so configured as to remove the residual oxide layer410from all the considered surfaces.

For instance, such wet cleaning can use preferably diluted hydrofluoric acid.

Such wet cleaning is so configured as to expose at least one among the following surfaces:the surface321of the nitride layer320;the surface221aof the thinned active layer220a;the surface of the trenches120.the surface of the STIs110.

FIGS. 7 and 8illustrate the step of adjusting the height of the surface221aof the thinned active layer220ato the height of the surface113of the etched portion of the STIs112. Adjusting the height then makes it possible, among other things, to reduce the geometry of the shallow trenches120, so that they do not affect the performances of the FDSOI transistors.

Advantageously, the shallow trenches120are reduced by adjusting the various chemical etching methods. The depth of the shallow trenches is thus reduced in the FDSOI transistors areas and prevents, after the etching of the gate polysilicon, the presence of polysilicon filaments, which may be the source of stray connections between the different polysilicon lines of the FDSOI transistors.

Such adjustment in height comprises at least two steps: forming a sacrificial oxide layer225and removing at least one portion of such sacrificial oxide layer225.

The formation and the partial removing of a sacrificial oxide layer225act in synergy with the previous step of dry etching400so as to reduce the production costs of the electronic devices.

First, such sacrificial oxide layer225makes it possible to improve the surface condition of the thinned active layer220a, i.e. to structurally clean the surface221a. As a matter of fact, the surface221aresults from dry etching which may damage the surface221aas regards crystallography on a very low thickness, of the order of a few nanometers for example. The partial removing of such sacrificial oxide layer225then makes it possible to remove the damaged portion of the surface221awhile leaving a residual sacrificial oxide layer230only, the surface231of which no longer shows any structural damage.

Then, the partial removing of such sacrificial oxide layer225makes it possible to level the surface231of the residual sacrificial oxide layer230with the height of the surfaces113of the etched portions of the STIs112. Such levelling then eliminates the limiting effects of the shallow trenches120on the performances of the FDSOI transistors600.

Eventually, the residual sacrificial oxide layer230acts as a screen to the ion implantations subsequently executed for forming the source areas610,710and drain areas620,720. Such screen provides a better homogeneity in the implantation by preventing any channelling effect and also limiting the structural damages resulting from the ion implantations.

Thus, one single step of height adjustment makes it possible to restore a surface structure with no defects, to eliminate the drawbacks resulting from the formation of the micro-trenches120and to enable future ion implantations.

FIG. 9illustrates a step of removing the nitride layer320at the PDSOI areas so as to expose the surface311of the intermediate oxide layer310. Such removal can be a wet operation, for instance, so as not to damage the surface231.

FIG. 10shows the step of ion implantation500for forming source and drain areas.

Advantageously, such step of ion implantation500may comprise two sub-steps corresponding to a first ion implantation of the PDSOI areas followed by a second ion implantation of the FDSOI areas. This makes it possible to have several degrees of freedom in selecting doses and elements to be implanted in order to meet the various requirements as regards the characteristics of the PDSOI700and FDSOI transistors600.

Such step of ion implantation500advantageously benefits from the presence of the intermediate oxide layer310the PDSOI areas and the residual sacrificial oxide layer231at the FDSOI areas so as to ensure a very homogeneous implantation and to limit the structural defects in the ion implantation. The intermediate oxide layers310at the PDSOI areas and the residual sacrificial oxide layer231at the FDSOI areas then act as screens to optimise the formation of the sources and the drains.

FIG. 11shows, according to a preferred embodiment, a FDSOI600transistor formed above the thinned FDSOI active region220aand two PDSOI transistors700, shown in halves inFIG. 11, and formed above the PDSOI210active regions.

InFIG. 11each transistor is schematically shown. Each transistor comprises at least one source area (610,710) and one drain area (620,720), raised in this example, with a gate (630,730) preferably comprising a plurality of layers and potentially spacers electrically insulating the sides of each gate (630,730) of the source (610,710) and drain areas (620,720).

FIG. 11shows the position of the PDSOI transistors700and the FDSOI transistors600relative to the PDSOI201areas and to the FDSOI202areas, according to one embodiment of the present invention.

The present invention relates to a method for producing an electronic device adapted to form PDSOI and FDSOI transistors on the same silicon wafer. The present invention comprises steps which have been studied, developed and optimized so as to have a mutual synergy so as to reduce production costs for such a device while not affecting the performances of electronic devices of this type.

Thus, some pluralities have multiple effects for reducing the total number of required steps.

The invention is not limited to the embodiments described above but applies to all the embodiments covered by the scope of the claims.

REFERENCES

10. Stack of layers, SOI substrate100. Insulating layer, BOX, silicon oxide110. Shallow Trench Isolation or STI111. Part of the shallow trenches covered with the masking layer112. Etched part of the shallow trenches113. Surface of the etched part of the shallow trenches120. Cavities, Micro-trenches200. Active layer;201. PDSOI area202. FDSOI area210. First active region, PDSOI active region, active layer220. Second active region, FDSOI active region, active layer220a. Second thinned active region, thinned FDSOI active region, thinned active layer221. Surface of the second active region221a. Surface of the second thinned active region225. Sacrificial oxide layer226. Surface of the sacrificial oxide layer230. Residual sacrificial oxide layer231. Surface of the residual sacrificial oxide layer310. Intermediate oxide layer311. Surface of the intermediate oxide layer320. Nitride layer321. Surface of the nitride layer330. Masking layer331. Surface of the masking layer340. Protective layer, resin400. Dry etching;500. Ion implantation;600. Fully depleted transistor FDSOI transistor610. Source area620. Drain area630. Gate700. Partially depleted transistor PDSOI transistor710. Source area720. Drain area730. Gate