Strained silicon germanium fin with block source/drain epitaxy and improved overlay capacitance

A semiconductor structure is provided including a strained silicon germanium alloy fin that can be employed as a channel material for a FinFET device and having a gate spacer including a lower portion that fills in a undercut region that lies adjacent to the strained silicon germanium alloy fin and beneath raised source/drain (S/D) structures and silicon pedestal structures that can provide improved overlay capacitance.

BACKGROUND

The present application relates to a semiconductor structure and a method of forming the same. More particularly, the present application relates to a semiconductor structure including a strained silicon germanium alloy fin that can be employed as a channel material for a FinFET device and having improved overlay capacitance. The present application also provides a method for forming such a semiconductor structure.

For more than three decades, the continued miniaturization of metal oxide semiconductor field effect transistors (MOSFETs) has driven the worldwide semiconductor industry. Various showstoppers to continued scaling have been predicated for decades, but a history of innovation has sustained Moore's Law in spite of many challenges. However, there are growing signs today that metal oxide semiconductor transistors are beginning to reach their traditional scaling limits. Since it has become increasingly difficult to improve MOSFETs and therefore complementary metal oxide semiconductor (CMOS) performance through continued scaling, further methods for improving performance in addition to scaling have become critical.

The use of non-planar semiconductor devices such as, for example, semiconductor fin field effect transistors (FinFETs) is the next step in the evolution of complementary metal oxide semiconductor (CMOS) devices. Semiconductor fin field effect transistors (FETs) can achieve higher drive currents with increasingly smaller dimensions as compared to conventional planar FETs.

In order to extend FinFET devices beyond the current technology node, there is a need to boost the performance by using high mobility channel materials such as, for example, strained silicon germanium (SiGe). In current SiGe FinFETs, the SiGe fins suffer from strain relaxation do to cutting the SiGe fins to a desired length. In such instances, the strain relaxes, especially at the end portions of the SiGe fins. Short SiGe fins are even more prone to the effect of strain relaxation. There is thus a need for providing a structure and method to maintain strain in SiGe fins.

SUMMARY

A semiconductor structure is provided including a strained silicon germanium alloy fin that can be employed as a channel material for a FinFET device and having a gate spacer including a lower portion that fills in a undercut region that lies adjacent to the strained silicon germanium alloy fin and beneath raised source/drain (S/D) structures and silicon pedestal structures that can provide improved overlay capacitance.

In one aspect of the present application, a semiconductor structure is provided. In one embodiment of the present application, the semiconductor structure of the present application includes a functional gate structure straddling over a first portion of at least one strained silicon germanium alloy fin. A source region is located on one side of the functional gate structure and comprises, a first end portion of the at least one strained silicon germanium alloy fin, and silicon pedestal structures located on opposing sidewalls of the first end portion of the at least one strained silicon germanium alloy fin. A drain region is located on another side of the functional gate structure and comprises a second end portion of the at least one strained silicon germanium alloy fin, and silicon pedestal structures located on opposing sidewalls of the second end portion of the at least one strained silicon germanium alloy fin. A raised source/drain (S/D) structure is present over each of the silicon pedestal structures, and the first and second end portions of the silicon germanium alloy fins, wherein each of the raised silicon raised source/drain (S/D) structures has a sidewall surface that overhangs a sidewall surface of each silicon pedestal structure. A gate spacer is located on opposing sidewalls of the functional gate structure and separates the functional gate structure from the source region and the drain region, wherein the gate spacer has a first region that is located on the at least one strained silicon germanium alloy fin, and the gate spacer has second regions that are present adjacent the at least one strained silicon germanium alloy fin and that have an upper portion and a lower portion, the lower portion of the gate spacer fills an undercut region beneath the overhang.

In another aspect of the present application, a method of forming a semiconductor structure is provided. In one embodiment of the present application, the method of the present application includes forming a structure containing at least one silicon germanium alloy fin having silicon pedestals located on opposing sidewalls of the at least one silicon germanium alloy fin. A sacrificial gate structure and a dielectric spacer are formed over a first portion of the at least one silicon germanium alloy fin and a first portion of each silicon pedestal. Next, a raised source/drain (S/D) structure and an interlevel dielectric layer are formed sequentially on exposed portions of the at least one silicon germanium alloy fin and the silicon pedestals not covered by the sacrificial gate structure and the dielectric spacer. The sacrificial gate structure is then removed to expose at least the first portion of the silicon pedestals. The first portion of each silicon pedestal is removed, while maintaining a silicon pedestal portion beneath the raised source/drain structure and the interlevel dielectric layer. A sidewall of each silicon pedestal portion is then etched into to provide silicon pedestal structures, wherein the raised source/drain structure and the interlevel dielectric layer overhang each silicon pedestal structure. A gate spacer is then formed, wherein the gate spacer has a first region that is located on the first portion of the at least one strained silicon germanium alloy fin, and the gate spacer has second regions that are present adjacent the first portion of the at least one strained silicon germanium alloy fin that have an upper portion and a lower portion, the lower portion of the gate spacer fills an undercut region beneath the overhang.

DETAILED DESCRIPTION

Referring first toFIG. 1, there is illustrated an exemplary semiconductor structure including a plurality of silicon pedestals10P extending upwards from a surface of a substrate10B, wherein a first hard mask cap12P is located on each silicon pedestal10P that can be employed in accordance with an embodiment of the present application. Each silicon pedestal10P is separated by a gap14having a width w1; w1may be referred to herein as first width. Width, w1, of each gap14provides the width of each strained silicon germanium alloy fin to be subsequently formed. In one embodiment, width, w1, of each gap14is from 4 nm to 30 nm. Other widths that are lesser than, or greater than, the aforementioned width range can also be used as width, w1, of each gap14.

The exemplary semiconductor structure shown inFIG. 1can be formed by first providing one of a bulk silicon substrate (i.e., a semiconductor substrate entirely composed of silicon), a multilayered semiconductor substrate in which the uppermost portion of the multilayered semiconductor substrate is composed of silicon, or a silicon-on-insulator (SOI) substrate in which the topmost layer of the SOI substrate is composed of silicon. The silicon present in any of the instances is single crystalline and may have any of the well known crystal orientations. For example, the crystal orientation of the bulk semiconductor substrate may be {100}, {110} or {111}.

Next, a first hard mask layer is formed on one of the above mentioned substrates. The first hard mask layer that is present on the surface of one of the above mentioned substrates is a contiguous hard mask material that covers the entirety of the substrate. The first hard mask layer that is employed in the present application may include an oxide, a nitride and/or an oxynitride. In one embodiment, the hard mask material that can be used in providing the first hard mask layer can be comprised of silicon dioxide. In another embodiment, the hard mask material that can be used in providing the first hard mask layer can be comprised of silicon nitride. In yet another embodiment, the hard mask material that can be used in providing the first hard mask layer can be a stack comprised of, in any order, silicon dioxide and silicon nitride.

In some embodiments, the hard mask material that can be used in providing the first hard mask layer can be formed by a deposition process such as, for example, chemical vapor deposition (CVD) or plasma enhanced chemical vapor deposition (PECVD). In other embodiments, the hard mask material that can be used in providing the first hard mask layer can be formed by a thermal process such as, for example, thermal oxidation and/or thermal nitridation. In yet other embodiments, the hard mask material that can be used in providing the first hard mask layer can be formed by a combination of a deposition process and a thermal process. The thickness of the hard mask material that can be used in providing the first hard mask layer can range from 10 nm to 40 nm. Other thicknesses that are lesser than, or greater than, the aforementioned thickness range may also be employed as the thickness of the first hard mask layer.

After providing the hard mask layer on one of the above mentioned substrates, the hard mask layer and the upper silicon layer or silicon portion of the substrate is patterned. In one embodiment of the present application, the patterning may include lithography and etching. Lithography includes forming a photoresist material (not shown) atop a material or material stack to be patterned. The photoresist material may include a positive-tone photoresist composition, a negative-tone photoresist composition or a hybrid-tone photoresist composition. The photoresist material may be formed by a deposition process such as, for example, spin-on coating. After forming the photoresist material, the deposited photoresist material is subjected to a pattern of irradiation. Next, the exposed photoresist material is developed utilizing a conventional resist developer. This provides a patterned photoresist atop a portion of the material or material stack to be patterned. The pattern provided by the patterned photoresist material is thereafter transferred into the underlying material layer or material layers utilizing at least one pattern transfer etching process. Typically, the at least one pattern transfer etching process is an anisotropic etch. In one embodiment, a dry etching process such as, for example, reactive ion etching can be used. In another embodiment, a chemical etchant can be used. In still a further embodiment, a combination of dry etching and wet etching can be used. In one embodiment of the present application, the etch stops on a sub-surface of a bulk semiconductor substrate.

In one embodiment of the present application, the substrate10B is a remaining portion of a bulk silicon substrate. In another embodiment and when an SOI substrate is employed, the substrate10B may include, from bottom to top, a handle substrate (e.g., a semiconductor material such as silicon), an insulator layer (e.g., a buried oxide) and a thin lower portion of a topmost silicon layer. In yet a further embodiment of the present and when a multilayered semiconductor substrate is employed, the remaining portion of the substrate10B may include remaining semiconductor layers of the multilayered semiconductor substrate.

Each silicon pedestal10P that is formed can have height from 30 nm to 120 nm, and a width from 20 nm to 120 nm. Other heights and widths that are lesser than, or greater than, the aforementioned ranges may also be employed in the present application. As is shown, the sidewall surfaces of each first hard mask cap12P are vertically aligned with the sidewall surfaces of one of the underlying silicon pedestals10P.

Referring now toFIG. 2, there is illustrated the exemplary semiconductor structure ofFIG. 1after forming a dopant region11within an upper semiconductor material portion of the substrate10B. In some embodiments of the present application, the step of forming the dopant region11within the upper semiconductor material portion of substrate10B may be omitted.

In one embodiment, the upper semiconductor material portion in which the dopant region11can be formed is composed of silicon or one of the semiconductor materials that provides the multilayered semiconductor substrate. The dopant region11can be formed utilizing ion implantation, followed by an activation anneal.

The dopant region11may contain a p-type dopant or an n-type dopant. The term “p-type” refers to the addition of impurities to an intrinsic semiconductor that creates deficiencies of valence electrons. Examples of p-type dopants, i.e., impurities, include, but are not limited to, boron, aluminum, gallium and indium. “N-type” refers to the addition of impurities that contributes free electrons to an intrinsic semiconductor. Examples of n-type dopants, i.e., impurities, include, but are not limited to, antimony, arsenic and phosphorous. In one embodiment of the present application, the concentration of dopant within dopant region11can range from 1×1018atoms/cm3to 1×1021atoms/cm3, although dopant concentrations greater than 1×1021atoms/cm3or less than 1×1018atoms/cm3are also conceived. In one embodiment, the dopant region11may be uniform (i.e., have a uniform distribution of dopants throughout the entire region). In another embodiment, the dopant region11may be graded. In such an embodiment, the dopant concentration may decrease downwards from the substrate10B/silicon pedestal10P interface. The dopant region11is oppositely doped to the later formed source/drain region so as to act as a punch through stop layer. The depth of dopant region11may range from 30 nm to 70 nm below the topmost surface of substrate10B.

Referring now toFIG. 3, there is illustrated the exemplary semiconductor structure ofFIG. 2after epitaxally growing a strained silicon germanium alloy fin16P within each gap14located between each silicon pedestal10P. Each strained silicon germanium alloy fin16P has a bottommost surface that directly contacts a topmost semiconductor material portion of substrate10B. Each strained silicon germanium alloy fin16P has a topmost surface that is less than the topmost surface of each silicon pedestal10P. Thus, each strained silicon germanium alloy fin16P has a height that is less than a height of each silicon pedestal10P. In one example, each strained silicon germanium alloy fin16P has a height from 10 nm to 80 nm. Each strained silicon germanium alloy fin16P completely fills one of the gaps14. Hence, each strained silicon germanium alloy fin16P has the width, w1, mentioned above for gap14. In accordance with the present, each strained silicon germanium alloy fin16P contains a silicon pedestal10P located on opposing sidewalls thereof. The strained silicon germanium alloy fins16P and the silicon pedestal10P have a same length at this point of the present application.

Each strained silicon germanium alloy fin16P may have a germanium content from 20 atomic percent germanium to 60 atomic percent germanium. Other germanium contents that are lesser than, or greater than the aforementioned range may also be employed in the present application.

As mentioned above, each strained silicon germanium alloy fin16P is formed by an epitaxial growth (or deposition) process. The terms “epitaxially growing and/or depositing” and “epitaxially grown and/or deposited” mean the growth of a semiconductor material on a deposition surface of a semiconductor material, in which the semiconductor material being grown has the same crystalline characteristics as the semiconductor material of the deposition surface. In an epitaxial deposition process, the chemical reactants provided by the source gases are controlled and the system parameters are set so that the depositing atoms arrive at the deposition surface of the semiconductor substrate with sufficient energy to move around on the surface and orient themselves to the crystal arrangement of the atoms of the deposition surface. Therefore, an epitaxial semiconductor material has the same crystalline characteristics as the deposition surface on which it is formed. Since an epitaxial growth process is used in providing each strained silicon germanium alloy fin16P, each strained silicon germanium alloy fin16P has an epitaxial relationship with the upper semiconductor material portion of substrate10B.

Examples of various epitaxial growth process apparatuses that can be employed in the present application include, e.g., rapid thermal chemical vapor deposition (RTCVD), low-energy plasma deposition (LEPD), ultra-high vacuum chemical vapor deposition (UHVCVD), atmospheric pressure chemical vapor deposition (APCVD) and molecular beam epitaxy (MBE). The temperature for epitaxial deposition typically ranges from 550° C. to 900° C. Although higher temperature typically results in faster deposition, the faster deposition may result in crystal defects and film cracking. The epitaxial growth of each strained silicon germanium alloy fin16P can be performed utilizing any well known precursor gas or gas mixture. Carrier gases like hydrogen, nitrogen, helium and argon can be used.

Referring now toFIG. 4, there is illustrated the exemplary semiconductor structure ofFIG. 3after removing each first hard mask cap12P from the silicon pedestals10P. Each first hard mask cap12P can be removed utilizing an etching process that is selective in removing the first hard mask material relative to the strained silicon germanium alloy fins16P and the silicon pedestals10P. In one embodiment of the present application, a reactive ion etch can be used to remove each of the first hard mask caps12P from atop each of the silicon pedestals10P. After removing the first hard mask caps12P, a topmost surface of each silicon pedestal10P is exposed.

Referring now toFIG. 5, there is illustrated the exemplary semiconductor structure ofFIG. 4after forming a second hard mask cap18P on each strained silicon germanium alloy fin16P. Each second hard mask cap18P can be formed utilizing one of the hard mask materials mentioned above for the first hard mask layer that provided each first hard mask cap12P. Each second hard mask cap18P can be formed by first providing a second hard mask layer utilizing one of the techniques mentioned above in forming the first hard mask layer. After providing the second hard mask layer, a planarization process such as, for example, chemical mechanical polishing, can be used to provide each second hard mask cap18P. Each second hard mask cap18P has a bottommost surface that directly contacts a topmost surface of a strained silicon germanium alloy fin16P. Each second hard mask cap18P that is formed has a topmost surface that is coplanar with a topmost surface of each silicon pedestal10P. Also, the width of each second hard mask cap18P is equal to the w1mentioned above for gap14.

Referring now toFIG. 6, there is illustrated the exemplary semiconductor structure ofFIG. 5after forming a sacrificial gate structure20and a dielectric spacer22. As is shown the dielectric spacer22surrounds the sacrificial gate structure20. Although a single sacrificial gate structure20and a single dielectric spacer22are described and illustrated, a plurality of sacrificial gate structures and a plurality of dielectric spacers can be formed. The sacrificial gate structure20and dielectric spacer22cover a first portion (i.e., channel region) of each strained silicon germanium alloy fin16P and each silicon pedestal10P, while leaving end portions of each strained silicon germanium alloy fin16P and end portions of each silicon pedestal10P exposed for further processing. The ends portions of the strained silicon germanium alloy fins18P and each silicon pedestal10P are located in the S/D regions of the exemplary semiconductor structure of the present application.

The sacrificial gate structure20may include a single sacrificial material layer or a stack of two or more sacrificial materials (i.e., at least one sacrificial material portion). In one embodiment, the at least one sacrificial material portion comprises, from bottom to top, a sacrificial gate dielectric portion, a sacrificial gate portion and a sacrificial dielectric cap portion. In some embodiments, the sacrificial gate dielectric portion and/or the sacrificial dielectric cap portion can be omitted and only a sacrificial gate portion is formed. The at least one sacrificial material portion can be formed by forming a blanket layer (or layers) of a material (or various materials) and then patterning the material (or various materials) by lithography and an etch. In one embodiment, the at least one sacrificial material portion can be formed by first depositing a blanket layer of a sacrificial gate dielectric material. The sacrificial gate dielectric material can be an oxide, nitride, and/or oxynitride. In one example, the sacrificial gate dielectric material can be a high k material having a dielectric constant greater than silicon dioxide. In some embodiments, a multilayered dielectric structure comprising different dielectric materials, e.g., silicon dioxide, and a high k dielectric can be formed and used as the sacrificial gate portion. The sacrificial gate dielectric material can be formed by any deposition technique including, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), sputtering, or atomic layer deposition.

After forming the blanket layer of sacrificial gate dielectric material, a blanket layer of a sacrificial gate material can be formed on the blanket layer of sacrificial gate dielectric material. The sacrificial gate material can include any material including, for example, polysilicon, amorphous silicon, an elemental metal (e.g., tungsten, titanium, tantalum, aluminum, nickel, ruthenium, palladium and platinum), an alloy of at least two elemental metals or multilayered combinations thereof. The sacrificial gate material can be formed utilizing a deposition process including, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), sputtering, atomic layer deposition (ALD) or other like deposition processes.

After forming the blanket layer of sacrificial gate material, a blanket layer of a sacrificial gate cap material can be formed. The sacrificial gate cap material may include a hard mask material such as, for example, silicon dioxide and/or silicon nitride. The sacrificial gate cap material can be formed by any suitable deposition process such as, for example, chemical vapor deposition or plasma enhanced chemical vapor deposition.

After providing the above mentioned sacrificial material stack (or any subset of said sacrificial materials), lithography and etching can be used to pattern the sacrificial material stack (or any subset of said sacrificial materials) and to provide the sacrificial gate structure20. The remaining portions of the sacrificial gate dielectric material constitute a sacrificial gate dielectric portion, the remaining portions of the sacrificial gate material constitute a sacrificial gate portion, and the remaining portions of the sacrificial dielectric cap material constitute a sacrificial dielectric cap portion.

After providing the sacrificial gate structure20, a dielectric spacer22can be formed on exposed sidewall surfaces of the sacrificial gate structure20. Dielectric spacer22can be formed by first providing a dielectric spacer material and then etching the dielectric spacer material. Examples of dielectric spacer materials that may be employed in the present application include dielectric oxides, dielectric nitrides and/or dielectric oxynitrides. In one embodiment, the dielectric spacer material used in providing dielectric spacer22is composed of silicon dioxide or silicon nitride. The dielectric spacer material may be provided by a deposition process including, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), or physical vapor deposition (PVP). The etch used to provide the dielectric spacer may comprise a dry etching process such as, for example, reactive ion etching.

Referring now toFIG. 7, there is illustrated the exemplary semiconductor structure ofFIG. 6after removing exposed portions of each second hard mask18P not covered by the sacrificial gate structure20and the dielectric spacer22, and forming a raised source/drain (S/D) structure24on exposed portions of each silicon pedestal10P and each strained silicon germanium alloy fin16P and one opposing sides of the sacrificial gate structure20. As is known to those skilled in the art, the raised source/drain (S/D) structure24formed on one side of the sacrificial gate structure is within a source region of the exemplary semiconductor structure, while the raised source/drain (S/D) structure24formed on the other side of the sacrificial gate structure is within a drain region of the exemplary semiconductor structure.

Each raised source/drain (S/D) structure24that is formed includes a semiconductor material having semiconductor properties and either a-type dopant or an n-type dopant, as defined above. The semiconductor material that provides each raised source/drain (S/D) structure24may include silicon (Si), germanium (Ge), silicon germanium alloys (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), III-V compound semiconductors and/or II-VI compound semiconductors. III-V compound semiconductors are materials that include at least one element from Group III of the Periodic Table of Elements and at least one element from Group V of the Periodic Table of Elements. II-VI compound semiconductors are materials that include at least one element from Group II of the Periodic Table of Elements and at least one element from Group VI of the Periodic Table of Elements. In one embodiment, each raised source/drain (S/D) structure24is entirely composed of silicon or a silicon germanium alloy.

Each raised source/drain (S/D) structure24can be formed utilizing an epitaxial growth process, as defined above. In one embodiment, the dopant that is present within each raised source/drain (S/D) structure24may be present within the precursor gas that provides each raised source/drain (S/D) structure24. In another embodiment, the dopant that is present within each raised source/drain (S/D) structure24can be introduced into an intrinsic epitaxially deposited semiconductor material by utilizing one of ion implantation or gas phase doping. The dopant concentration within each raised source/drain (S/D) structure24can range from 1×1020atoms/cm3to 1×1021atoms/cm3, although dopant concentrations greater than 1×1021atoms/cm3or less than 1×1020atoms/cm3are also conceived. The dopant can be uniformly distributed with each raised source/drain structure24or the dopant can be present as a gradient in each raised source/drain (S/D) structure24. In some embodiments of the present application, each raised source/drain (S/D) structure24is grown up-ward from 100-crystal planes.

Although not evident from the top down view, each raised source/drain (S/D) structure24that is formed has a topmost surface that is located beneath a topmost surface of the sacrificial gate structure20and the dielectric spacer22.

Referring now toFIG. 8, there is illustrated the exemplary semiconductor structure ofFIG. 7after forming an interlayer dielectric (ILD) layer26on each raised S/D structure24. Although not evident from the top down view, each ILD layer26that is formed has a topmost surface that is coplanar with a topmost surface of the sacrificial gate structure20and the dielectric spacer22.

Each ILD layer26may be composed of silicon dioxide, undoped silicate glass (USG), fluorosilicate glass (FSG), borophosphosilicate glass (BPSG), a spin-on low-k dielectric layer, a chemical vapor deposition (CVD) low-k dielectric layer or any combination thereof. The term “low-k” as used throughout the present application denotes a dielectric material that has a dielectric constant of less than silicon dioxide. In another embodiment, a self-planarizing material such as a spin-on glass (SOG) or a spin-on low-k dielectric material such as SiLK™ can be used as ILD layer26. The use of a self-planarizing dielectric material as the ILD layer26may avoid the need to perform a subsequent planarizing step.

In one embodiment, the ILD layer26can be formed utilizing a deposition process including, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), evaporation or spin-on coating. In some embodiments, particularly when non-self-planarizing dielectric materials are used as the ILD layer26, a planarization process or an etch back process follows the deposition of the dielectric material that provides the ILD layer26.

Referring now toFIGS. 9A-9C, there are shown various views of the exemplary semiconductor structure ofFIG. 8after removing the sacrificial gate structure20; in the drawings the portion of the dielectric spacer22that extends beyond the outermost silicon pedestals10P is not shown for clarity. The sacrificial gate structure20may be removed utilizing an etching process such as, for example, reactive ion etching. A single etch or multiple etch processes may be used in removing the sacrificial gate structure20. A cavity is provided that exposes a topmost surface of each silicon pedestal10P (See, for example,FIGS. 9A and 9C) and a topmost surface of each second hard mask18P (See, for example,FIGS. 9A-9B).

Referring now toFIGS. 10A-10C, there are shown various views ofFIGS. 9A-9Cafter removing each exposed silicon pedestal10P not covered by the ILD layer26and the dielectric spacer22. Hence, each silicon pedestal10P is cut into silicon pedestal portions10L,10R. One of the silicon pedestal portions (e.g.,10L) can be present in the source region of the exemplary semiconductor structure, while the other of the silicon pedestal portions (e.g.,10R) can be present in the drain region of the exemplary semiconductor structure. Within the cavity mentioned above, an extended cavity28is formed that exposes a topmost semiconductor material portion of substrate10B. The removal (i.e., cutting) of the exposed silicon pedestals10P not covered by the ILD layer26and the dielectric spacer22may be performed utilizing an etching process such as, for example, a reactive ion etch. The strained silicon germanium alloy fins16P that are present in the cavity formed by removing the sacrificial gate structure20are not removed since they are protected by the second hard mask cap18P as shown inFIGS. 10A-10B. Strain within the strained silicon germanium alloy fins16P is maintained in the present application.

At this point of the present application and as is shown inFIG. 10C, the dielectric spacer22has an outermost edge (i.e., sidewall surface) that is vertical aligned with an outermost edge (i.e., sidewall surface) of each silicon pedestal portion (10L,10R).

Referring now toFIGS. 11A-11C, there are illustrated various views of the exemplary semiconductor structure ofFIGS. 10A-10Cafter etching into a sidewall of each remaining silicon pedestal10P (i.e., each silicon pedestal portion10L,10R) located beneath the dielectric spacer22. InFIG. 11A, the arrows show the direction of the etching. After etching, portions of each silicon pedestal portion10L,10R remain beneath the ILD layer26in both the source region and the drain region. The remaining portions of the silicon pedestal portions10L,10R can be referred to herein as silicon pedestal structures10L′,10R′. As is shown, inFIG. 11C, portions of the raised source/drain (S/D) structure24and the ILD layer26now overhang the underlying silicon pedestal structure10L′,10R′. As is shown inFIG. 11C, an undercut region29is now formed. The etching used to provide the exemplary semiconductor structure shown inFIGS. 11A-11Ccomprises a directional etch. In one example, the directional etch may include TMAH (tetramethylammonium hydroxide) as an etchant. In some embodiments, the etch may include an anisotropic selective silicon reaction ion etch. The undercut region29may have a width, w2from 2 nm to 20 nm. The width, w2, of undercut region29is measured from an outermost sidewall of the raised source/drain structure24to the outermost sidewall of silicon pedestal structures10L′,10R′ within the extended cavity28.

Referring now toFIGS. 12A-12C, there are illustrated various views of the exemplary semiconductor structure ofFIGS. 11A-11Cafter removing the dielectric spacer22and each second hard mask cap18P not covered by the ILD layer26. The removal of the second hard mask caps18P exposes topmost surfaces of each strained silicon germanium fin16P within the cavity that was formed after removing the sacrificial gate structure, while the removal of the dielectric spacer22exposes sidewall surfaces of the ILD layer26and the raised source/drain (S/D) structure24within the source region and the drain region of the exemplary semiconductor structure.

In some embodiments of the present application and when the dielectric spacer22and each second hard mask cap18P comprise a same material a single etch may be used. In one embodiment, the etch is an anisotropic etch such as a reactive ion etch. In other embodiments of the present application and when the dielectric spacer22and each second hard mask cap18P comprise different materials, two separate etching processing may be used to remove the dielectric spacer22and each second hard mask cap18P. In such an embodiment, the order of removal may vary and is not critical to the present application. As is shown inFIG. 12C, the raised source/drain (S/D) structures24and the overlying ILD layer26have sidewalls that overhang the sidewalls of the silicon pedestal structures10L′,10R′.

Referring now toFIGS. 13A-13C, there is shown the exemplary semiconductor structure ofFIGS. 12A-12Cafter forming a gate spacer30. The gate spacer30has first regions, R1, that are located on each strained silicon germanium alloy fin16P. See, for example,FIG. 13B. The gate stack30also has second regions, R2, that are present adjacent each strained silicon germanium alloy fin16P that have an upper portion30A and a lower portion30B. See, for example,FIG. 13C. In some embodiments of the present application, the first regions, R1, of the gate spacer30, and the second regions, R2, of the gate spacer30including the upper portion30A and lower portion30B have a same thickness. This is shown inFIG. 13Cby the dotted line within gate spacer30located in the second regions, R2. In another embodiment of the present application, the first regions, R1, of the gate spacer30and the upper portion30A of the gate spacer30in the second regions, R2, have a first thickness, and the lower portion30B of the gate spacer30in the second region, R2, has a second thickness that is greater than the first thickness. In either embodiment, the lower portion30B of the gate spacer30has a sidewall surface that directly contacts an exposed sidewall surface of the silicon pedestal structures10R′,10L′. The lower portion30B the gate spacer30thus fills in the undercut region29mentioned above. As is further shown, the upper portion30A of gate spacer30has a sidewall surface in which one portion thereof directly contacts a sidewall surface of the ILD layer26, while another portion of the upper portion30A of the gate spacer30directly contacts a sidewall surface of the raised source/drain (S/D) structure24. Within the first region, R1, the gate spacer30has a bottommost surface that is coplanar with a bottommost surface of each raised source/drain (S/D) structure24. In the second regions, R2, the lower portion30B of the gate spacer30has a bottommost surface that is coplanar with a bottommost surface of each silicon pedestal structure10L′,10R′.

In some embodiments of the present application, the gate spacer30may include a dielectric oxide, dielectric nitride and/or dielectric oxynitride. In one embodiment, the gate spacer30is composed of silicon dioxide or silicon nitride. In other embodiments of the present application, the gate spacer30comprises a dielectric material having a dielectric constant that is less than the dielectric constant of silicon dioxide. In one example, the gate spacer30having a dielectric constant less than silicon dioxide may include a material that includes atoms of Si, O, C and H with N being optionally present.

The gate spacer30may be provided by a deposition process, followed by etching. The deposition used to provide the gate spacer30may include, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), or physical vapor deposition (PVP). The etch used to provide the gate spacer30may comprise a dry etching process such as, for example, reactive ion etching.

Referring now toFIGS. 14A-14C, there are illustrated various views of the exemplary semiconductor structure ofFIGS. 13A-13Cafter forming a functional gate structure. By “functional gate structure” it is meant a permanent gate structure used to control output current (i.e., flow of carriers in the channel) of a semiconducting device through electrical or magnetic fields. Although not evidence from the top down view shown inFIG. 14A, the functional gate structure has a topmost surface that is coplanar with a topmost surface of the ILD26and the gate spacer30; See,FIGS. 14B and 14C. The functional gate structure may include a gate dielectric portion32and a gate conductor portion34; the topmost surface of each of the gate dielectric portion32and the gate conductor portion34may be coplanar with a topmost surface of the ILD layer26. In the present application, the functional gate structure including the gate dielectric portion32and the gate conductor portion34within the cavity mentioned above straddle the exposed portions of the strained silicon germanium alloy fins16P. Thus, and within the cavity mentioned above that is formed by removing the sacrificial gate structure20, the exposed strained silicon germanium alloy fins16P represent channel regions of the FinFET structure that includes the functional gate structure.

The gate dielectric portion32may include a gate dielectric material. The gate dielectric material that provides the gate dielectric portion32can be an oxide, nitride, and/or oxynitride. In one example, each gate dielectric material that provides the gate dielectric portion32can be a high-k material having a dielectric constant greater than silicon dioxide. Exemplary high-k dielectrics include, but are not limited to, HfO2, ZrO2, La2O3, Al2O3, TiO2, SrTiO3, LaAlO3, Y2O3, HfOxNy, ZrOxNy, La2OxNy, Al2OxNy, TiOxNy, SrTiOxNy, LaAlOxNy, Y2OxNy, SiON, SiNx, a silicate thereof, and an alloy thereof. Each value of x is independently from 0.5 to 3 and each value of y is independently from 0 to 2. In some embodiments, a multilayered gate dielectric structure comprising different gate dielectric materials, e.g., silicon dioxide, and a high-k gate dielectric, can be formed and used as the gate dielectric portion32. In some embodiments, the gate dielectric portion32of each functional gate structure comprises a same gate dielectric material. In another embodiment, at least one of the gate dielectric portions32of at least one of the functional gate structures comprises a different gate dielectric material than the other gate dielectric portions32of the other functional gate structures.

The gate dielectric material used in providing the gate dielectric portion32can be formed by any deposition process including, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), sputtering, or atomic layer deposition. In some embodiments, block mask technology can be used to provide a different gate dielectric material to different functional gate structures. In one embodiment of the present application, the gate dielectric material used in providing the gate dielectric portion32can have a thickness in a range from 1 nm to 10 nm. Other thicknesses that are lesser than, or greater than, the aforementioned thickness range can also be employed for the gate dielectric material that may provide the gate dielectric portion32.

The gate conductor portion34can include a gate conductor material. The gate conductor material used in providing the gate conductor portion34can include any conductive material including, for example, doped polysilicon, an elemental metal (e.g., tungsten, titanium, tantalum, aluminum, nickel, ruthenium, palladium and platinum), an alloy of at least two elemental metals, an elemental metal nitride (e.g., tungsten nitride, aluminum nitride, and titanium nitride), an elemental metal silicide (e.g., tungsten silicide, nickel silicide, and titanium silicide) or multilayered combinations thereof. In one embodiment, the gate conductor portion34may comprise an nFET gate metal. In another embodiment, the gate conductor portion34may comprise a pFET gate metal. In some embodiments, at least one of the gate conductor portions34of at least one of the functional gate structures comprises a different gate conductor material than the other gate conductor portions of the other functional gate structures.

The gate conductor material used in providing the gate conductor portion34can be formed utilizing a deposition process including, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), sputtering, atomic layer deposition (ALD) or other like deposition processes. In some embodiments, block mask technology can be used to provide a different gate conductor material to different functional gate structures. When a metal silicide is formed, a conventional silicidation process is employed. In one embodiment, the gate conductor material used in providing the gate conductor portion34can have a thickness from 50 nm to 200 nm. Other thicknesses that are lesser than, or greater than, the aforementioned thickness range can also be employed for the gate conductor material used in providing the gate conductor portion34.

The functional gate structure (32,34) can be formed by providing a functional gate material stack of the gate dielectric material, and the gate conductor material. A planarization process may follow the formation of the functional gate material stack.

Notably,FIGS. 14A-14Cillustrate a semiconductor structure in accordance with the present application. The semiconductor structure of the present application includes a functional gate structure (32,34) straddling over a first portion of at least one strained silicon germanium alloy fin16P. A source region100is located on one side of the functional gate structure (32,34) and comprises, a first end portion of the at least one strained silicon germanium alloy fin16P, and silicon pedestal structures (e.g.,10L′) located on opposing sidewalls of the first end portion of the at least one strained silicon germanium alloy fin16P. A drain region102is located on another side of the functional gate structure (32,34) and comprises a second end portion of the at least one strained silicon germanium alloy fin16P, and silicon pedestal structures (e.g.,10R′) located on opposing sidewalls of the second end portion of the at least one strained silicon germanium alloy fin16P. A raised source/drain (S/D) structure24is present over each of the silicon pedestal structures10L′,10R′ and the first and second end portions of the silicon germanium alloy fins16P, wherein each of the raised silicon raised source/drain (S/D) structures24has a sidewall surface that overhangs a sidewall surface of the silicon pedestal structure10L,10R′. A gate spacer30is located on opposing sidewalls of the functional gate structure (32,34) and separates the functional gate structure (32,34) from the source region100and the drain region102, wherein the gate spacer30has a first region, R1, that is located on the at least one strained silicon germanium alloy fin16P, and the gate spacer30has second regions, R2, that are present adjacent the at least one strained silicon germanium alloy fin16P that have an upper portion30A and a lower portion30B, the lower portion30B of gate spacer30fills an undercut region29beneath the overhang.

Referring now toFIGS. 15A-15C, there are illustrated through different views, and in another embodiment of the present application, the exemplary semiconductor structure ofFIGS. 10A-10Cafter etching into a sidewall of each remaining silicon pedestal portion10L,10R located beneath the dielectric spacer22, and forming a gate spacer40.

After etching, portions of each silicon pedestal portion10L,10R remain beneath the ILD layer26in both the source region and the drain region. The remaining portions of the silicon pedestal portions10L,10R can be referred to herein as silicon pedestal structures10L′,10R′.

As is shown, inFIG. 15C, portions of the raised source/drain (S/D) structure24and the ILD layer26overhang the underlying silicon pedestal structure10L′,10R′. The etching used to provide the exemplary semiconductor structure shown inFIGS. 15A-15Ccomprises a directional etch as mentioned above.

After etching, gate spacer40is formed. Gate spacer40may comprise one of the spacer materials mentioned above for gate spacer30. Gate spacer40may be formed utilizing the technique mentioned above in forming gate spacer30. The gate spacer40has first regions, R1, that are located on each strained silicon germanium alloy fin16P. See, for example,FIG. 15B. The gate stack40also has second regions, R2, that are present adjacent each strained silicon germanium alloy fin16P that have an upper portion40A and a lower portion40B. See, for example,FIG. 15C. In some embodiments of the present application, the first regions, R1, of the gate spacer40, and the second regions, R2, of the gate spacer40including the upper portion40A and lower portion40B have a same thickness. In another embodiment of the present application the first regions, R1, of the gate spacer40and the upper portion40A of the gate spacer40in the second regions, R2, have a first thickness, and the lower portion40B of the gate spacer40in the second region, R2, has a second thickness that is greater than the first thickness. In either embodiment, the lower portion40B of the gate spacer40has a sidewall surface that directly contacts an exposed sidewall surface of the silicon pedestal structures10R′,10L′. The lower portion40B the gate spacer40thus fills in the undercut region29mentioned above. As is further shown, the upper portion40A of gate spacer40has a sidewall surface directly contacting the dielectric spacer22that is present on a sidewall surface of the ILD layer26and a sidewall surface of the raised source/drain (S/D) structure24. Within the first region, R1, the gate spacer40has a bottommost surface that is coplanar with a bottommost surface of each raised source/drain (S/D) structure24. In the second regions, R2, the lower portion40B of the gate spacer has a bottommost surface that is coplanar with a bottommost surface of each silicon pedestal structure10L′,10R′.

Referring now toFIGS. 16A-16C, there are illustrated various views of the exemplary semiconductor structure ofFIGS. 15A-15Cafter forming a functional gate structure. The functional gate structure of this embodiment of the present is the same as that described above in the previous embodiment shown inFIGS. 14A-14C. The functional gate structure includes a gate dielectric portion32, as described above, and a gate conductor portion34, as also described above.

Notably,FIGS. 16A-16Cillustrated another exemplary semiconductor structure of the present application which is similar to the one depicted inFIGS. 14A-14Cexcept that gate spacer is now labeled as element40and the dielectric spacer22remains.