NAND memory with virtual channel

A string of nonvolatile memory cells are connected together by source/drain regions that include an inversion layer created by fixed charge in an overlying layer. Control gates extend between floating gates so that two control gates couple to a floating gate. A fixed charge layer may be formed by plasma nitridation.

BACKGROUND OF THE INVENTION

This invention relates to nonvolatile memories and methods of forming nonvolatile memories. In particular, this application relates to nonvolatile memory arrays in which a series of floating gate memory cells are electrically connected in series.

Nonvolatile memory systems are used in various applications. Some nonvolatile memory systems are embedded in a larger system such as a personal computer. Other nonvolatile memory systems are removably connected to a host system and may be interchanged between different host systems. Examples of such removable memory systems include memory cards and USB flash drives. Electronic circuit cards, including non-volatile memory cards, have been commercially implemented according to a number of well-known standards. Memory cards are used with personal computers, cellular telephones, personal digital assistants (PDAs), digital still cameras, digital movie cameras, portable audio players and other host electronic devices for the storage of large amounts of data. Such cards usually contain a re-programmable non-volatile semiconductor memory cell array along with a controller that controls and supports operation of the memory cell array and interfaces with a host to which the card is connected. Several of the same type of card may be interchanged in a host card slot designed to accept that type of card. However, the development of the many electronic card standards has created different types of cards that are incompatible with each other in various degrees. A card made according to one standard is usually not useable with a host designed to operate with a card of another standard. Memory card standards include PC Card, CompactFlash™ card (CF™ card), SmartMedia™ card, MultiMediaCard (MMC™), Secure Digital (SD) card, a miniSD™ card, Subscriber Identity Module (SIM), Memory Stick™, Memory Stick Duo card and microSD/TransFlash™ memory module standards. There are several USB flash drive products commercially available from SanDisk Corporation under its trademark “Cruzer®.” USB flash drives are typically larger and shaped differently than the memory cards described above.

Different types of memory array architecture are used in nonvolatile memory systems. In one type of architecture, a NAND array, a series of strings of more than two memory cells, such as 16 or 32, are connected along with one or more select transistors between individual bit lines and a reference potential to form columns of cells. Word lines extend across cells within a large number of these columns. An individual cell within a column is read and verified during programming by causing the remaining cells in the string to be over driven so that the current flowing through a string is dependent upon the level of charge stored in the addressed cell.

SUMMARY OF THE INVENTION

A nonvolatile memory array according to an embodiment of the present invention comprises: a plurality of floating gate memory cells connected in series, the plurality of floating gate memory cells electrically connected by source/drain regions, a source/drain region including an inversion layer created by a fixed charge within a fixed charge layer portion that extends over the source/drain region, control gates extending between floating gates such that a control gate overlies the fixed charge layer portion.

An nonvolatile memory array according to another embodiment comprises: a plurality of memory cells connected in series to form a NAND string, each of the plurality of memory cells having a floating gate; a plurality of control gates, each of the plurality of control gates extending between adjacent floating gates; a plurality of source/drain regions that electrically connect the plurality of memory cells in series, each of the plurality of source/drain regions underlying one of the plurality of control gates; and a plurality of fixed charge layer portions, each of the plurality of fixed charge layer portions extending over one of the plurality of source/drain regions, each of the plurality of fixed charge layer portions holding a fixed electrical charge.

A method of forming a nonvolatile memory array according to an embodiment of the present invention comprises: forming a plurality of floating gates overlying a substrate surface; forming a plurality of fixed charge layer portions overlying the substrate surface, the plurality of fixed charge layer portions interspersed between the plurality of floating gates, each of the plurality of fixed charge layer portions formed having fixed electrical charge; and forming a plurality of control gates overlying the plurality of fixed charge layer portions.

A method of forming a nonvolatile memory array according to another embodiment comprises: forming a gate dielectric layer over a substrate surface; subsequently forming a plurality of floating gates overlying the gate dielectric layer; subsequently forming a plurality of fixed charge layer portions, individual fixed charge layer portions overlying the substrate surface between floating gates; forming an interlayer dielectric layer over the plurality of floating gates; and forming a plurality of control gates between floating gates.

DETAILED DESCRIPTION OF ILLUSTRATED EMBODIMENTS

FIG. 1shows a cross section of a NAND flash memory string100that has control gates81-84extending on both sides of floating gates33-35(this type of array is sometimes referred to as ENAND). Examples of such strings and methods of forming them are described in U.S. Pat. No. 6,888,755. In string100ofFIG. 1a floating gate is coupled to two control gates, one on either side of the control gate (e.g. floating gate34is coupled to control gates82and83). This is in contrast to a common memory design where a control gate overlies a floating gate so that each floating gate is coupled to only one control gate. A memory string such as that ofFIG. 1may be formed as part of a memory array having many strings. Neighboring strings may be isolated from each other by Shallow Trench Isolation (STI) structures, or other means (not shown inFIG. 1). In some cases, individual stings may have 8, 16, 32 or more memory cells connected together in series. Select gates45,51are provided at either end of string100and are connected to select lines80,85to allow string100to be connected to circuits used for accessing the memory cells of string100. Floating gates33-35are separated from substrate77by a gate dielectric (tunnel oxide) layer91overlying substrate surface79.

In string100ofFIG. 1, source/drain regions57,62,67,72,105,106are provided in substrate77on either side of floating gates. Source/drain regions57,62,67,72,105,106are shared by neighboring memory cells and provide an electrically conductive pathway between memory cells so that the memory cells in string100may be connected in series. Source/drain regions57,62,67,72,105,106ofFIG. 1are formed by implantation using floating gates33-35and select gates45,51to provide a mask so that source/drain regions57,62,67,72,105,106are self-aligned to floating gates33-35and select gates45,51. Control gates81-84are then formed by depositing a conductive layer (e.g. doped polysilicon) and removing the conductive material where it overlies floating gates33-35and select gates45,51so that conductive material remains between floating gates33-35. Thus, control gates81-84may be considered to be self-aligned to floating gates33-35. Control gates81-84are separated from floating gates33-35by an interlayer dielectric layer103. Control gates81-84extend in the direction perpendicular to the cross section shown and control gates of neighboring strings are connected together as word lines. Thus, a word line is a conductive element that extends through multiple strings and forms control gates where it couples to floating gates of individual strings. A control gate may couple to the underlying substrate to form a transistor where it overlies a source/drain region. By biasing a control gate a source/drain region may be made more conductive or less conductive. Thus, the source/drain region in a memory of this type (having a control gate close to the substrate, not just overlying the floating gate) may be considered as the channel of a transistor that has the control gate as its gate. In some cases, control gate bias may be sufficient to create an inversion layer that acts as a conductive source/drain region without requiring a source/drain implant.

When an architecture such as that ofFIG. 1is scaled to small dimensions (e.g. gate length less than 45 nanometers) certain device characteristics may be negatively impacted. Problems encountered as a result of diminished channel length may be referred to as “short channel effects.” Short channel effects may be caused by implanted dopant in a source/drain region reducing the effective gate length and causing variation in effective gate length. This problem may be mitigated by reducing the amount of dopant implanted. However, less dopant results in higher resistivity and thus higher source/drain resistance, which is generally undesirable. Reduction in post implant anneal thermal cycle may also help to mitigate the problem, but does not generally eliminate short channel effects.

FIG. 2shows a cross section of a NAND string200according to an embodiment of the present invention in which source/drain regions202-205are not formed by implanting dopants, but by causing an inversion layer to be formed in substrate208. An inversion layer is formed near a semiconductor surface when an electrical charge is in close proximity, the electrical charge drawing charge carriers to the surface where they form a conductive layer. Such an electrical charge may cause a flat band voltage shift and inverts the surface. A fixed interface charge may induce enough band bending to invert the surface to form a conduction channel. InFIG. 2, fixed charge layer portions210-213(having positive charge) are present on both sides of floating gates216-218. Each of fixed charge layer portions210-213contains a fixed amount of positive electrical charge. The positively charged fixed charge layer portions210-213cause negatively charged electrons to be drawn to portions of substrate208underlying the fixed charge layer portions210-213. There, the electrons form an inversion layer (source/drain regions202-205) within the P-well (P-doped portion of substrate208). An inversion layer formed in this manner will form a conduction channel between two floating gates. Since the conduction channel is formed without a metallurgical junction, the floating gate transistor will not experience short channel effects from the source/drain regions as may be experienced when dopants are implanted to form source/drain regions. As inFIG. 1, control gates220-223overlie source/drain regions202-205and source/drain regions202-205act as channels of transistors having control gates220-223as their gates. Unlike the example ofFIG. 1, here such channels are not formed by dopant that is implanted in a substrate. Instead a channel is formed by charge carriers in an inversion layer caused by fixed charge. Such a channel may be referred to as a “virtual channel.”

While the example ofFIG. 2shows positively charged fixed charge layer portions210-213(and hence negative charge in the inversion layer of source/drain regions202-205), in other examples negatively-charged fixed charge layer portions may be provided causing positive charge carriers to form an inversion layer in an N-doped portion of a substrate.

While the example ofFIG. 2shows source/drain regions202-205being formed without source/drain implants, in other examples source/drain regions may be formed by a combination of implantation and an inversion layer. In this manner a lower implant dose may be used without resulting in an excessively high source/drain resistance. In general, the resistance of a source/drain region depends on any dopant in the region, any electrical field caused by fixed charge as described above and any electrical field caused by biasing an overlying control gate.

Fixed charge layers may be formed in a variety of ways using a variety of materials. Materials may include Hf-rich Hafnium oxide, Zr-rich Zirconium oxide, Silicon nitride, nitrided Silicon dioxide or some combination of these or other materials. Fixed charge layers may be formed by plasma deposition, plasma nitrification, plasma oxidation, chemical vapor deposition, atomic layer deposition, rapid thermal processing, ion implantation or other techniques. A fixed charge layer may contain charge as-deposited or may have charge added after deposition (such as by plasma processing). In some cases, a fixed charge layer has charge as-deposited and subsequently has additional charge added. In one example, nitridation of a Silicon dioxide surface results in a nidrided Silicon dioxide that contains positive charge. A fixed charge layer may result where surface states are created on a substrate by a process such as a plasma deposition process.

A fixed charge layer may be patterned in some manner so that fixed charge layer portions remain only where an inversion layer is to be formed. Alternatively, a fixed charge layer may be deposited as a blanket layer over a substrate having floating gates already formed. Where the fixed charge layer is on or close to the substrate surface (between floating gates) fixed charge layer portions cause inversion layer portions to be formed at these locations. Where such a fixed charge layer overlies a floating gate it has little effect and may be left in place. In this way, inversion layer portions are formed in the substrate in a manner that is self-aligned to the floating gates, since they are only formed where the fixed charge layer is in close proximity to the substrate surface. In some cases, a fixed charge layer may be deposited directly on a substrate surface, while in other cases a layer of Silicon dioxide or other material may lie between the substrate surface and the fixed charge layer.

FIGS. 3-8show the formation of a NAND memory string300having control gates between floating gates and having a virtual channel according to an embodiment of the present invention.FIG. 3shows a cross section of NAND string300at an intermediate stage in a fabrication process. A substrate330has a surface332covered by a dielectric layer334(in this case Silicon dioxide). Dielectric layer334may be formed by oxidation, chemical vapor deposition or in some other manner. Floating gates336-339are located on dielectric layer334so that dielectric layer334forms a gate dielectric (tunnel oxide) layer to allow electron tunneling from substrate330into the floating gates336-339under certain conditions. Gate dielectric layer334also extends across substrate surface332between floating gates336-339. Floating gates336-339are covered by hardmask elements342-345(Silicon nitride in this example). Hardmask elements342-345are used to define floating gates336-339during an etch process. Hardmask elements342-345may be formed by lithographic patterning to have a width equal to the minimum feature size of the patterning process or may be formed using sidewall spacers or other techniques so that they have a width that is less than the minimum feature size of the lithographic process used. Short channel effects may be especially bad where such techniques are used to form floating gate memory cells with very short channels. To form a memory string such as that ofFIG. 1, source/drain implants would generally be performed at this point. However, in this process an alternative technique is used. Exemplary processes that may be used to fabricate a memory array up to the point shown inFIG. 3are described in U.S. Pat. No. 6,888,755.

FIG. 4shows NAND string300ofFIG. 3after a plasma nitridation process is performed. The plasma nitridation process results in nitridation of exposed surfaces of the dielectric layer334and floating gates336-339. The plasma nitridation process may be performed using conventional plasma deposition equipment such as a Dual Plasma Nitride (DPN) chamber from Applied Materials, a Slot Plane Antenna (SPA) chamber from Tokyo Electron Limited (TEL), Modified Magnetron Typed (MMT) system from Hitachi Kokusai Electric or other plasma processing equipment. In one example a MMT system performs a nitridation process using the following conditions: Temperature=350 degrees Centigrade; Pressure=50 Pascals; Gas=Nitrogen (N2); RF Power=250 Watts. The result of the nitridation is that a nitrided layer450is formed. Portions450a-cof nitrided layer450between floating gates336-339may include Silicon nitride and nitrided Silicon dioxide. Nitrided Silicon dioxide may also be formed over floating gates336-339. Positively charged species are incorporated into nitrided surfaces. Generally, the charge incorporated into nitrided surfaces in this manner is not free to move because the nitrided surface is not electrically conductive, so the charge remains fixed in place. Thus, a nitrided surface formed in this way may be considered a fixed charge layer. Portions450a-cof the fixed charge layer450that extend between floating gates336-339are on or close to substrate surface332(some Silicon dioxide of dielectric layer334may remain under fixed charge layer portions450a-c, or all Silicon dioxide may be nitrided). The presence of electrical charge affects the portions of the substrate330underlying fixed charge layer portions450a-cas discussed later. It may be desirable to locate fixed charge as close to the substrate as possible (without actually being in the substrate) and process conditions may be selected accordingly. This may provide a stronger channel inversion and hence a more conductive source/drain region.

Subsequent to forming fixed charge layer450, one or more dielectric materials are deposited over memory string300to form an interlayer dielectric layer556(a dielectric layer separating floating gates and control gates—also referred to as “interpoly dielectric” though materials other than polysilicon may be used for these layers in some cases). In the example ofFIG. 5the interlayer dielectric layer556is formed of three layers: a Silicon dioxide layer, then a Silicon nitride layer, then another Silicon dioxide layer forming an Oxide-Nitride-Oxide (ONO) stack. In other examples the interlayer dielectric may be formed of a single material or from a different combination of materials. An interlayer dielectric layer may be formed using a process that provides a low thermal cycle so that the fixed charge layer is not subject to high temperatures that might affect it. For example Atomic Layer Deposition (ALD), TEL SPA, or Applied Materials' In Situ Steam Generation (ISSG) system may be used.

Subsequent to forming interlayer dielectric layer556, a conductive material is deposited to form a conductive layer660as shown inFIG. 6. In the present example, conductive layer660is formed of doped polysilicon. Conductive layer660is deposited as a blanket layer that extends between floating gates336-339to fill the spaces between neighboring floating gates. Conductive layer660also extends over floating gates336-339when it is deposited, as shown inFIG. 6. Subsequently, portions of conductive layer660that overlie the floating gates336-339are removed.

FIG. 7shows string300after removal of excess conductive material to leave separate portions660a-eof conductive material between floating gates336-339. Conductive material may be removed by etch back, Chemical Mechanical Polishing (CMP) or other techniques. The resulting separate portions660a-eof conductive material form control gates extending in a direction perpendicular to the cross section shown. Control gates of neighboring strings are connected together to form word lines that may serve many strings. A floating gate may be accessed through control gates on both sides, typically by using both control gates together.

FIG. 8illustrates how string300ofFIG. 7operates as a string of memory cells connected in series. In particular, as previously discussed, fixed charge layer portions450a-care formed over substrate surface332between floating gates336-339and fixed charge layer portions4520a-ccause inversion layer portions to be formed in underlying portions of substrate330, these inversion layer portions forming source/drain regions880-882. The memory cells thus formed are connected in series by the source/drain regions880-882.

FIG. 9shows a NAND string900according to an alternative embodiment of the present invention in which floating gates902-905have an inverted-T shape. Such inverted-T shaped floating gates may be formed by a process such as that described in U.S. Pat. No. 7,026,684. As with the previous example, subsequent to formation of floating gates902-905, a fixed charge layer908is formed over string900so that fixed charge layer portions create inversion layer portions where the fixed charge layer is on or close to substrate910(i.e. between floating gates902-905). A fixed charge layer may be used in this manner with floating gates of other shapes also. In some cases such a fixed charge layer eliminates the need for source/drain implants, while in other cases the fixed charge layer may be used in combination with source/drain implants.

All patents, patent applications, articles, books, specifications, other publications, documents and things referenced herein are hereby incorporated herein by this reference in their entirety for all purposes. To the extent of any inconsistency or conflict in the definition or use of a term between any of the incorporated publications, documents or things and the text of the present document, the definition or use of the term in the present document shall prevail.

Although the various aspects of the present invention have been described with respect to certain preferred embodiments, it is understood that the invention is entitled to protection within the full scope of the appended claims.