Semiconductor arrangement and method of making

A semiconductor arrangement is provided. The semiconductor arrangement includes a first dielectric layer over a substrate, a metal layer over the first dielectric layer, a first conductive structure passing through the metal layer and the first dielectric layer, a second conductive structure passing through the metal layer and the first dielectric layer, and a third conductive structure coupling the first conductive structure to the second conductive structure, and overlying a first portion of the metal layer between the first conductive structure and the second conductive structure, wherein an interface exists between the metal layer and at least one of the first conductive structure or the second conductive structure.

BACKGROUND

Semiconductor arrangements are used in a multitude of electronic devices, such as mobile phones, laptops, desktops, tablets, watches, gaming systems, and various other industrial, commercial, and consumer electronics. Semiconductor arrangements generally comprise semiconductor portions and wiring portions formed inside the semiconductor portions.

DETAILED DESCRIPTION

Some embodiments relate to a semiconductor arrangement. In accordance with some embodiments, the semiconductor arrangement includes an etch stop layer (ESL) over a substrate, a first dielectric layer over the ESL, a metal layer over the first dielectric layer, and a first conductive structure passing through the metal layer, the first dielectric layer, and the ESL. In some embodiments, the semiconductor arrangement includes a second conductive structure passing through the metal layer, the first dielectric layer, and the ESL. In some embodiments, the semiconductor arrangement includes a third conductive structure coupling the first conductive structure to the second conductive structure. In some embodiments, a first portion of the metal layer is between the first conductive structure and the second conductive structure. In some embodiments, the third conductive structure overlies the first portion of the metal layer.

According to some embodiments, the semiconductor arrangement includes a second dielectric layer overlying the third conductive structure. According to some embodiments, the second dielectric layer overlies the first dielectric layer. In some embodiments, a sidewall of the second dielectric layer is adjacent a sidewall of the third conductive structure and a sidewall of the metal layer. In some embodiments, the third conductive structure overlies a second portion of the metal layer that is not between the first conductive structure and the second conductive structure.

According to some embodiments, the first dielectric layer includes a low-k dielectric material having a dielectric constant of about 1.8 to about 5. According to some embodiments, the metal layer protects at least the first dielectric layer during one or more etching processes, such as by having a different etch selectivity to one or more etchants as compared to other layers, features, etc. According to some embodiments, one or more characteristics, such as lattice structure, dielectric constant value, etc., of the first dielectric layer experience little to no change from the one or more etching processes due to the protection afforded by the metal layer. According to some embodiments, sidewalls, corners, edges, etc. of the first dielectric layer experience little to no rounding, non-linearity, etc. from the one or more etching processes due to the protection afforded by the metal layer.

According to some embodiments, the metal layer is patterned to generate a patterned metal layer. According to some embodiments, the patterned metal layer serves as a mask to pattern at least the first dielectric layer, such as by having a different etch selectivity to one or more etchants as compared to other layers, features, etc. According to some embodiments, the patterned metal layer protects at least portions of the first dielectric layer underlying the patterned metal layer during one or more etching processes. According to some embodiments, one or more characteristics, such as lattice structure, dielectric constant value, etc., of the portions of the first dielectric layer experience little to no change from the one or more etching processes due to the protection afforded by the patterned metal layer. According to some embodiments, sidewalls, corners, edges, etc. of the portions of first dielectric layer experience little to no rounding, non-linearity, etc. from the one or more etching processes due to the protection afforded by the patterned metal layer.

According to some embodiments, sidewalls, corners, edges, etc. of the first dielectric layer that define one or more openings, trenches, etc. in the first dielectric layer as a result of one or more etching processes performed with the patterned metal layer in place experience little to no rounding, non-linearity, etc. According to some embodiments, one or more openings, trenches, etc. defined in the first dielectric layer with the patterned metal layer in place are at least one of narrower or deeper than such openings, trenches, etc. formed without the patterned metal layer in place. According to some embodiments, one or more openings, trenches, etc. defined in the first dielectric layer with the patterned metal layer in place have a different, such as lower or higher, aspect ratio than such openings, trenches, etc. formed without the patterned metal layer in place. According to some embodiments, one or more features, structures, elements, etc. formed in the one or more openings, trenches, etc. have little to no rounding, non-linearity, etc. due to the ‘true’ nature of the sidewalls, corners, edges, etc. of the first dielectric layer that define the one or more openings, trenches, etc. According to some embodiments, one or more features, structures, elements, etc. formed in the one or more openings, trenches, etc. have a different, such as lower or higher, aspect ratio than such features, structures, elements, etc. formed in one or more openings, trenches, etc. that are formed without the patterned metal layer in place.

Referring toFIGS. 1A, 1B, and 10, the semiconductor arrangement100includes an etch stop layer (ESL)104, a first dielectric layer106over the ESL104, and a metal layer108over the first dielectric layer106, according to some embodiments. In some embodiments, the ESL104is formed over a substrate102. In some embodiments, the substrate102includes at least one of an epitaxial layer, a silicon-on-insulator (SOI) structure, a wafer, or a die formed from a wafer. In some embodiments, the substrate102includes at least one of silicon or other suitable materials.

In some embodiments, the semiconductor arrangement100is patterned, such as etched. In some embodiments, the patterning of the semiconductor arrangement100is so performed that a plurality of vertical structures110is formed over the metal layer108. In some embodiments, at least one of the vertical structures includes a hard mask (HM)112and a second dielectric layer114. In some embodiments, the pattering stops at the metal layer108and the underlying layers, such as the first dielectric layer106, the ESL104and the substrate102, are not patterned. In some embodiments, the patterning process includes an etching process. In some embodiments, at least one of HF, a chlorine compound, or other suitable etchants are used to pattern the semiconductor arrangement100. In some embodiments, a selectivity of the metal layer108to an etchant is different than a selectivity of the HM112and the second dielectric layer114to the etchant so that the HM112and the second dielectric layer114are etched but the metal layer108is not etched.

In some embodiments, the ESL104includes at least one of SiC, SiO2, SiOC, SiCN, SiOCN, AlON, AlO, or other suitable materials. In some embodiments, the ESL104is formed by at least one of physical vapor deposition (PVD), sputtering, chemical vapor deposition (CVD), low pressure CVD (LPCVD), atomic layer chemical vapor deposition (ALCVD), ultrahigh vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), spin on, or other suitable techniques. In some embodiments, the ESL104is formed at a temperature of about 150 degrees Celsius to about 400 degrees Celsius. In some embodiments, the ESL104has a thickness of about 10 Angstroms to about 1000 Angstroms.

According to some embodiments, the first dielectric layer106includes a low-k dielectric material. In some embodiments, the first dielectric layer106has a dielectric constant of about 1.8 to about 5. In some embodiments, the first dielectric layer106includes at least one of SiC, SiO2, SiOC, SiN, SiCN, SiON, SiOCN, or other suitable materials. In some embodiments, the first dielectric layer106is formed by at least one of PVD, sputtering, CVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin on, or other suitable techniques. In some embodiments, the first dielectric layer106is formed at a temperature of about 50 degrees Celsius to about 400 degrees Celsius. In some embodiments, the first dielectric layer106has a thickness of about 30 Angstroms to about 800 Angstroms.

In some embodiment, the metal layer108includes a metal. In some embodiments, the metal layer108is not metal per se. According to some embodiments, the metal layer108includes a metallic compound. In some embodiments, the metal layer108includes at least one of Ta, TaN, TiN Cu, Co, Ru, Mo, Ir, W, or other suitable materials. According to some embodiments, the metal layer108acts as a barrier layer to protect the first dielectric layer106from degradation, patterning, etc. during one or more processing operations, such as etching, of the semiconductor arrangement100. In some embodiments, the metal layer108is formed by at least one of PVD, sputtering, CVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin on, or other suitable techniques. In some embodiments, the metal layer108is formed at a temperature of about 150 degrees Celsius to about 400 degrees Celsius. In some embodiments, the metal layer108has a thickness of about 10 Angstroms to about 1000 Angstroms.

In some embodiments, the HM112includes at least one of TiN, TiO, W, WC, HfO, ZrO, ZrTiO, or other suitable materials. In some embodiments, the HM112is formed by at least one of PVD, sputtering, CVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin on, or other suitable techniques. In some embodiments, the HM112is formed at a temperature of about 50 degrees Celsius to about 400 degrees Celsius. In some embodiments, the HM112has a thickness of about 30 Angstroms to about 500 Angstroms.

In some embodiments, the second dielectric layer114includes at least one of SiC, SiO2, SiOC, SiN, SiCN, SiON, SiOCN, or other suitable materials. In some embodiments, the second dielectric layer114is formed by at least one of PVD, sputtering, CVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin on, or other suitable techniques. In some embodiments, the second dielectric layer114is formed at a temperature of about 50 degrees Celsius to about 400 degrees Celsius. In some embodiments, the second dielectric layer114has a thickness of about 30 Angstroms to about 800 Angstroms.

In some embodiments, the first dielectric layer106and the second dielectric layer114are formed in a same manner. In some embodiments, the first dielectric layer106and the second dielectric layer114are formed in different manners. In some embodiments, the first dielectric layer106and the second dielectric layer114have a same material composition. In some embodiments, the first dielectric layer106and the second dielectric layer114do not have a same material composition.

Referring toFIGS. 2A, 2B, and 2C, a barrier layer (BL)202is formed over the metal layer108, the HM112, and the second dielectric layer114, including sidewalls of the HM112and sidewalls of the second dielectric layer114, according to some embodiments. In some embodiments, the BL202includes at least one of oxide, nitride, or other suitable materials. In some embodiments, the BL202is formed by at least one of PVD, sputtering, CVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin on, or other suitable techniques. In some embodiments, the second dielectric layer114has a thickness of about 300 Angstroms to about 2000 Angstroms.

In some embodiments, a protective metal layer (ML)204is formed over the BL202. In some embodiment, the ML204includes a metal. In some embodiments, the ML204is not metal per se. According to some embodiments, the ML204includes a metallic compound. According to some embodiments, the ML204includes metal nitride or other suitable materials. In some embodiments, the ML204is formed by at least one of PVD, sputtering, CVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin on, or other suitable techniques. In some embodiments, the ML204is formed at a temperature of about 150 degrees Celsius to about 400 degrees Celsius. In some embodiments, the metal layer108has a thickness of about 10 Angstroms to about 1000 Angstroms.

In some embodiments, a photoresist layer (PR)206is formed over the ML204. In some embodiments, the PR206includes a light sensitive material where properties, such as solubility, of the PR206are affected by light. The PR206is either a negative photoresist or a positive photoresist. With respect to the negative photoresist, regions of the negative photoresist become insoluble when illuminated by a light source, such that application of a solvent to the negative photoresist during a subsequent development stage removes non-illuminated regions of the negative photoresist. A pattern formed in the negative photoresist is thus a negative of a pattern defined by opaque regions of a template between the light source and the negative photoresist. In the positive photoresist, illuminated regions of the positive photoresist become soluble and are removed via application of the solvent during development. Thus, a pattern formed in the positive photoresist is a positive image of opaque regions of the template between the light source and the positive photoresist. According to some embodiments, an etchant has a selectivity such that the etchant removes or etches away the layer under the photoresist at a greater rate than the etchant removes or etches away the photoresist. Accordingly, an opening in the photoresist allows the etchant to form a corresponding opening in the layer under the photoresist, and thereby transfer a pattern in the photoresist to the layer under the photoresist. The pattern in the layer under the photoresist is filled with one or more materials to form one or more elements, features, etc. and the patterned photoresist is stripped or washed away at least one of before or after the pattern in the layer under the photoresist is filled with the one or more materials. In some embodiments, the PR206is formed by at least one of PVD, sputtering, CVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin on, or other suitable techniques. In some embodiments, the PR206has a thickness of about 10 Angstroms to about 1000 Angstroms. In some embodiments, one or more openings302are formed in the PR206. In some embodiments, the openings302expose a top surface of the ML204.

Referring toFIGS. 3A, 3B, and 3C, in some embodiments, the openings302are deepened by removing some of the ML204and BL202. In some embodiments, the removal process is so performed that a top surface of the metal layer108is exposed. In some embodiments, removal of at least one of the ML204or the BL202includes at least one of etching or wet clean. According to some embodiments, an etchant is used that removes or etches away at least one of the ML204or the BL202at a greater rate than the etchant removes or etches away at least one of the PR206or the metal layer108. In some embodiments, removal of at least one of the ML204or the BL202includes at least one of inductively coupled plasma (ICP), capacitively coupled plasma (CCP), ion beam etching (IBE), a remote plasma method, or other suitable techniques. In some embodiments, removal of at least one of the ML204or the BL202uses at least one of CH4, CH3F, CH2F2, CH F3, C4F8, C4F6, CF4, H2, HBr, CO, CO2, O2, BCl3, Cl2, He, N2, Ne, Ar, CH3OH, C2H5OH, or other suitable material as a source of plasma. According to some embodiments, removal of at least one of the ML204or the BL202is performed at a pressure of about 0.2 mT to about 120 mT. According to some embodiments, removal of at least one of the ML204or the BL202is performed at a temperature of about 0° C. to about 100° C. According to some embodiments, removal of at least one of the ML204or the BL202is performed using a power of about 50 W to about 3000 W. According to some embodiments, removal of at least one of the ML204or the BL202is performed using a bias of about 0V to about 1200V.

Referring toFIGS. 4A, 4B, and 4C, in some embodiments, the openings302are deepened by patterning or removing some of the metal layer108, thereby generating a patterned metal layer. In some embodiments, the removal process is so performed that a top surface of the first dielectric layer106is exposed. In some embodiments, removal of the metal layer108includes at least one of etching or wet clean. According to some embodiments, an etchant is used that removes or etches away the metal layer108at a greater rate than the etchant removes or etches away at least one of the BL202or the first dielectric layer106. In some embodiments, removal of the metal layer108includes at least one of ICP, CCP, IBE, a remote plasma method, or other suitable techniques. In some embodiments, removal of the metal layer108uses at least one of CH4, CH3F, CH2F2, CH F3, C4F8, C4F6, CF4, H2, HBr, CO, CO2, O2, BCl3, Cl2, He, N2, Ne, Ar, CH3OH, C2H5OH, or other suitable material as a source of plasma. According to some embodiments, removal of the metal layer108is performed at a pressure of about 0.2 mT to about 120 mT. According to some embodiments, removal of the metal layer108is performed at a temperature of about 0° C. to about 100° C. According to some embodiments, removal of the metal layer108is performed using a power of about 50 W to about 3000 W. According to some embodiments, removal of the metal layer108is performed using a bias of about 0V to about 1200V.

In some embodiments, remaining portions of the PR206and ML204are removed. In some embodiments, remaining portions of at least one of the PR206or the ML204are removed as some of the metal layer108is removed to deepen the openings302. In some embodiments, remaining portions of at least one of the PR206or the ML204are removed by a different process than the process that removes some of the metal layer108to deepen the openings302. In some embodiments, remaining portions of at least one of the PR206or the ML204are removed by at least one of stripping, wet clean, chemical mechanical polishing (CMP), or other suitable techniques, alone or in combination with the process that removes some of the metal layer108to deepen the openings302.

Referring toFIGS. 5A, 5B, and 5C, in some embodiments, the openings302are deepened by patterning or removing some of the first dielectric layer106, thereby generating a patterned first dielectric layer. In some embodiments, the removal process is so performed that a top surface of the ESL104is exposed. In some embodiments, removal of the first dielectric layer106includes at least one of etching or wet clean. According to some embodiments, an etchant is used that removes or etches away the first dielectric layer106at a greater rate than the etchant removes or etches away at least one of the BL202or the ESL104. In some embodiments, removal of the first dielectric layer106includes at least one of ICP, CCP, IBE, a remote plasma method, or other suitable techniques. In some embodiments, removal of the first dielectric layer106uses at least one of CH4, CH3F, CH2F2, CHF3, C4F8, C4F6, CF4, H2, HBr, CO, CO2, O2, BCl3, Cl2, He, N2, Ne, Ar, CH3OH, C2H5OH, or other suitable material as a source of plasma. According to some embodiments, removal of the first dielectric layer106is performed at a pressure of about 0.2 mT to about 120 mT. According to some embodiments, removal of the first dielectric layer106is performed at a temperature of about 0° C. to about 100° C. According to some embodiments, removal of the first dielectric layer106is performed using a power of about 50 W to about 3000 W. According to some embodiments, removal of the first dielectric layer106is performed using a bias of about 0V to about 1200V.

According to some embodiments, at least two of removal of some of the ML204, removal of some of the BL202, removal of some of the metal layer108, or removal of some of the first dielectric layer106to deepen the openings302are accomplished by a single, same, continuous, etc. process, such as an etching process. According to some embodiments, at least two of removal of some of the ML204, removal of some of the BL202, removal of some of the metal layer108, or removal of some of the first dielectric layer106to deepen the openings302are not accomplished by a single, same, continuous, etc. process, such as an etching process.

Referring toFIGS. 6A, 6B, and 6C, in some embodiments, the BL202is removed. In some embodiments, removal of the BL202includes at least one of etching or wet clean. According to some embodiments, an etchant is used that removes or etches away the BL202at a greater rate than the etchant removes or etches away at least one of the second dielectric layer114, the HM112, the metal layer108, the first dielectric layer106, or the ESL104. In some embodiments, removal of the first dielectric layer106includes at least one of ICP, CCP, IBE, a remote plasma method, or other suitable techniques. In some embodiments, removal of the BL202uses at least one of CH4, CH3F, CH2F2, CHF3, C4F8, C4F6, CF4, H2, HBr, CO, CO2, O2, BCl3, Cl2, He, N2, Ne, Ar, CH3OH, C2H5OH, or other suitable material as a source of plasma. According to some embodiments, removal of the BL202is performed at a pressure of about 0.2 mT to about 120 mT. According to some embodiments, removal of the BL202is performed at a temperature of about 0° C. to about 100° C. According to some embodiments, removal of the BL202is performed using a power of about 50 W to about 3000 W. According to some embodiments, removal of the BL202is performed using a bias of about 0V to about 1200V. According to some embodiments, removal of the BL202occurs during at least one of removal of some of the ML204, removal of some of the BL202, removal of some of the metal layer108, or removal of some of the first dielectric layer106to deepen the openings302.

Referring toFIGS. 7A, 7B, and 7C, in some embodiments, the openings302are deepened by patterning or removing some of the ESL104, thereby generating a patterned ESL. In some embodiments, the removal process is so performed that a top surface of the substrate102is exposed. In some embodiments, removal of the ESL104includes at least one of etching or wet clean. According to some embodiments, an etchant is used that removes or etches away the ESL104at a greater rate than the etchant removes or etches away at least one of the second dielectric layer114, the HM112, the metal layer108, the first dielectric layer106, or the substrate102. In some embodiments, removal of the ESL104includes at least one of ICP, CCP, IBE, a remote plasma method, or other suitable techniques. In some embodiments, removal of the ESL104uses at least one of CH4, CH3F, CH2F2, CHF3, C4F8, C4F6, CF4, H2, HBr, CO, CO2, O2, BCl3, Cl2, He, N2, Ne, Ar, CH3OH, C2H5OH, or other suitable material as a source of plasma. According to some embodiments, removal of the ESL104is performed at a pressure of about 0.2 mT to about 120 mT. According to some embodiments, removal of the ESL104is performed at a temperature of about 0° C. to about 100° C. According to some embodiments, removal of the ESL104is performed using a power of about 50 W to about 3000 W. According to some embodiments, removal of the ESL104is performed using a bias of about 0V to about 1200V.

Referring toFIGS. 8A, 8B, and 8C, in some embodiments, a conductive layer802is formed. According to some embodiments, the conductive layer802fills the openings302. In some embodiments, a height of the conductive layer802is greater than a height of the plurality of vertical structures110. In some embodiment, the conductive layer802includes a metal. In some embodiments, the conductive layer802is not metal per se. According to some embodiments, the conductive layer802includes a metallic compound. In some embodiments, the conductive layer802includes at least one of Ta, TaN, TiN Cu, Co, Ru, Mo, Ir, W, or other suitable materials. According to some embodiments, the conductive layer802has a same material composition as the metal layer108. According to some embodiments, the conductive layer802does not have a same material composition as the metal layer108. Given that the conductive layer802is formed after the metal layer108, an interface exists between the conductive layer802and the metal layer108. In some embodiments, the conductive layer802is formed by at least one of PVD, sputtering, CVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin on, or other suitable techniques.

Referring toFIGS. 9A, 9B, and 9C, in some embodiments, excess conductive layer802is removed. According to some embodiments, the top surfaces of the plurality of vertical structures110are exposed after removal of the excess conductive layer802. In some embodiments, the excess conductive layer802is removed by at least one of CMP or other suitable techniques.

Referring toFIGS. 10A, 10B, and 100, in some embodiments, the vertical structures110, comprising the second dielectric layer114and the HM112, and portions of the metal layer108underlying the vertical structures110are removed. In some embodiments, the removal process is so performed that a top surface of the first dielectric layer106is exposed. In some embodiments, removal of at least one of the vertical structures110or the portions of the metal layer108underlying the vertical structures110includes at least one of etching or wet clean. According to some embodiments, an etchant is used that removes or etches away at least one of the vertical structures110or the portions of the metal layer108underlying the vertical structures110at a greater rate than the etchant removes or etches away at least one of the first dielectric layer106or the conductive layer802. In some embodiments, removal of at least one of the vertical structures110or the portions of the metal layer108underlying the vertical structures110includes at least one of ICP, CCP, IBE, a remote plasma method, or other suitable techniques. In some embodiments, removal of at least one of the vertical structures110or the portions of the metal layer108underlying the vertical structures110uses at least one of CH4, CH3F, CH2F2, CHF3, C4F8, C4F6, CF4, H2, HBr, CO, CO2, O2, BCl3, Cl2, He, N2, Ne, Ar, CH3OH, C2H5OH, or other suitable material as a source of plasma. According to some embodiments, removal of at least one of the vertical structures110or the portions of the metal layer108underlying the vertical structures110is performed at a pressure of about 0.2 mT to about 120 mT. According to some embodiments, removal of at least one of the vertical structures110or the portions of the metal layer108underlying the vertical structures110is performed at a temperature of about 0° C. to about 100° C. According to some embodiments, removal of at least one of the vertical structures110or the portions of the metal layer108underlying the vertical structures110is performed using a power of about 50 W to about 3000 W. According to some embodiments, removal of at least one of the vertical structures110or the portions of the metal layer108underlying the vertical structures110is performed using a bias of about 0V to about 1200V. According to some embodiments, a mask is formed over the conductive layer802to protect the conductive layer802and structures, features, elements, etc. underlying the conductive layer802when the vertical structures110and the portions of the metal layer108underlying the vertical structures110are removed.

Referring toFIGS. 11A, 11B, and 11C, a third dielectric layer1102is formed over first dielectric layer106, the conductive layer802, and the metal layer108, including sidewalls of the conductive layer802and the metal layer108, according to some embodiments. In some embodiments, a height of the third dielectric layer1102is greater than a height of the conductive layer802. According to some embodiments, the third dielectric layer1102includes a low-k dielectric material. In some embodiments, the third dielectric layer1102has a dielectric constant of about 1.8 to about 5. In some embodiments, the third dielectric layer1102includes at least one of SiC, SiO2, SiOC, SiN, SiCN, SiON, SiOCN, or other suitable materials. In some embodiments, the third dielectric layer1102is formed by at least one of PVD, sputtering, CVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin on, or other suitable techniques. In some embodiments, the third dielectric layer1102is formed at a temperature of about 50 degrees Celsius to about 400 degrees Celsius. In some embodiments, the first dielectric layer106has a thickness of about 1000 Angstroms to about 3000 Angstroms.

In some embodiments, the third dielectric layer1102is formed in a same manner as at least one of the first dielectric layer106or the second dielectric layer114. In some embodiments, the third dielectric layer1102is not formed in a same manner as at least one of the first dielectric layer106or the second dielectric layer114. In some embodiments, the third dielectric layer1102has a same material composition as at least one of the first dielectric layer106or the second dielectric layer114. In some embodiments, the third dielectric layer1102does not have a same material composition as at least one of the first dielectric layer106or the second dielectric layer114.

According to some embodiments, at least one of the one or more layers, features, structures, elements, etc. disclosed herein are in direct contact with another of the one or more layers, features, structures, elements, etc. disclosed herein. According to some embodiments, at least one of the one or more layers, features, structures, elements, etc. disclosed herein are not in direct contact with another of the one or more layers, features, structures, elements, etc. disclosed herein, such as where one or more intervening, separating, etc. layers, features, structures, elements, etc. exist.

According to some embodiments, a first portion802aof the conductive layer802constitutes a first conductive structure passing through the metal layer108, the first dielectric layer106, and the ESL104. According to some embodiments, a second portion802bof the conductive layer802constitutes a second conductive structure passing through the metal layer108, the first dielectric layer106, and the ESL104. Given that the conductive layer802is formed after the metal layer108, an interface exists between the metal layer108and at least one of the first conductive structure or the second conductive structure. According to some embodiments, a third portion802cof the conductive layer802constitutes a third conductive structure that couples the first conductive structure to the second conductive structure. According to some embodiments, the third conductive structure overlies a first portion108aof the metal layer108between the first conductive structure and the second conductive structure. According to some embodiments, the third conductive structure overlies a second portion108bof the metal layer108adjacent the first conductive structure but not between the first conductive structure and the second conductive structure. According to some embodiments, the third conductive structure overlies a third portion108cof the metal layer108adjacent the second conductive structure but not between the first conductive structure and the second conductive structure. According to some embodiments at least one of the first conductive structure or the second conductive structure has a height of about 5 nm to about 3000 nm. According to some embodiments at least one of the first conductive structure or the second conductive structure has a width of about 50 nm to about 300 nm.

According to some embodiments, at least due to the protection afforded by the metal layer108, one or more characteristics, such as lattice structure, dielectric constant value, etc., of the first dielectric layer106experience little to no change from one or more fabrication processes, such as etching. According to some embodiments, at least due to the protection afforded by the metal layer108, sidewalls, corners, edges, etc. of the first dielectric layer experience little to no rounding, non-linearity, etc. from one or more fabrication processes, such as etching.

According to some embodiments, at least due to the protection afforded by the metal layer108, one or more features, structures, elements, etc., such as at least one of the first conductive structure or the second conductive structure, formed in one or more openings, trenches, etc. in the first dielectric layer106have little to no rounding, non-linearity, etc. due to the ‘true’ nature of the sidewalls, corners, edges, etc. of the first dielectric layer106that define the one or more openings, trenches, etc.

According to some embodiments, a method for forming a semiconductor arrangement includes forming a metal layer over a first dielectric layer, patterning the metal layer to generate a patterned metal layer, patterning the first dielectric layer using the patterned metal layer to generate a patterned first dielectric layer, wherein a first opening is defined in the patterned metal layer and the patterned first dielectric layer, forming a first conductive structure in the first opening, and forming a second dielectric layer over the first conductive structure, the patterned metal layer, and the patterned first dielectric layer, wherein a sidewall of a portion of the second dielectric layer overlying a first portion of the patterned first dielectric layer is adjacent a sidewall of a first portion of the patterned metal layer overlying a second portion of the patterned first dielectric layer.

According to some embodiments, a semiconductor arrangement includes a first dielectric layer over a substrate, a metal layer over the first dielectric layer, a first conductive structure passing through the metal layer and the first dielectric layer, a second conductive structure passing through the metal layer and the first dielectric layer, and a third conductive structure coupling the first conductive structure to the second conductive structure, and overlying a first portion of the metal layer between the first conductive structure and the second conductive structure, wherein an interface exists between the metal layer and at least one of the first conductive structure or the second conductive structure.

According to some embodiments, a method for forming a semiconductor arrangement includes forming a metal layer over an etch stop layer (ESL), patterning the metal layer to generate a patterned metal layer, and patterning the ESL using the patterned metal layer to generate a patterned ESL.

It will be appreciated that layers, features, elements, etc. depicted herein are illustrated with particular dimensions relative to one another, such as structural dimensions or orientations, for example, for purposes of simplicity and ease of understanding and that actual dimensions of the same differ substantially from that illustrated herein, in some embodiments. Additionally, a variety of techniques exist for forming the layers, regions, features, elements, etc. mentioned herein, such as at least one of etching techniques, planarization techniques, implanting techniques, doping techniques, spin-on techniques, sputtering techniques, growth techniques, or deposition techniques such as chemical vapor deposition (CVD), for example.