Method of fabricating thin film transistor by crystallization through metal layer forming source and drain electrodes

A method of fabricating a thin film transistor includes patterning the amorphous semiconductor layer to form an amorphous semiconductor layer pattern, forming a gate electrode corresponding to the amorphous semiconductor layer pattern on a gate insulating layer, forming an interlayer insulating layer on the entire surface of the substrate, forming a first contact hole partially exposing the amorphous semiconductor layer pattern, forming a second contact hole partially exposing the gate electrode, and forming a metal layer on the entire surface of the substrate. The method also includes applying an electrical field to the metal layer such that a semiconductor layer is formed by crystallization of the amorphous semiconductor layer pattern, and patterning the metal layer to form source and drain electrodes that are insulated from the gate electrode and that are electrically connected with the semiconductor layer through the first contact hole.

BACKGROUND OF THE INVENTION

1. Field of the Invention

Embodiments of the present invention relate to a thin film transistor, a method of fabricating the same, and an organic light emitting diode display device including the same. More particularly, embodiments of the present invention relate to a thin film transistor (TFT) that can prevent generated Joule heat from generating an arc during a conventional crystallization process.

2. Description of the Related Art

Annealing methods used during a crystallization process generally include a furnace annealing method using a heat furnace, a rapid thermal annealing (RTA) method using radiant heat, e.g., a halogen lamp, a laser annealing method using a laser, and an annealing method using Joule heating. Among available annealing methods, an appropriate annealing method for the crystallization process is determined based on characteristics of material and process contemplated. Some of the factors to be considered in the selection of an appropriate annealing method are a range of an annealing temperature, uniformity of the annealing temperature, a heating rate, a cooling rate, purchase price, and maintenance cost. However, a selection of annealing method becomes very limited when high temperature annealing or high rate annealing only in a local region of a material is needed.

The laser annealing method can rapidly anneal a surface of a material. Despite this advantage, the laser annealing method has only limited applicability, since it can only be used to anneal particular materials. When scanned linear laser beams overlap to anneal a large-sized device, non-uniformity in intensity of the laser beam and in irradiation level of the laser beam may occur. Also, the laser annealing method requires very expensive equipment, as well as incurring high maintenance cost.

The RTA method is widely applied to a semiconductor fabrication process. However, with current technology, RTA methods can be applied only to a 300 mm silicon wafer, so it is difficult to uniformly anneal a substrate larger than 300 mm. Moreover, this method has a maximum heating rate of about 400° C./sec, and thus cannot be applied to a process requiring a higher heating rate than 400° C./sec.

Thus, research has been widely conducted on annealing methods to solve these problems and to eliminate processing limitations. A rapid annealing method, which applies an electrical field to a conductive layer and generates Joule heat, can rapidly anneal a selected material by transferring high heat. The rapid annealing method has much higher heating rate than that of the conventional RTA method. However, such a rapid annealing method cannot prevent physical defects of substrates from an arc generated during the Joule heating.

SUMMARY OF THE INVENTION

Embodiments of the present invention are therefore directed to a TFT, a method of fabricating the same, and an organic light emitting diode (OLED) display device using the same, which substantially overcome one or more of the disadvantages of the related art.

It is therefore a feature of an embodiment of the present invention to provide a TFT having a semiconductor layer crystallized by application of an electric field using a metal layer capable of preventing an arc formation during the crystallization of an amorphous layer, as the result of heat transfer from the metal layer.

It is therefore another feature of an embodiment of the present invention to provide a method of fabricating a TFT exhibiting above features and OLED display device including the TFT.

At least one of the above features and other advantages of the present invention may be realized by providing a TFT, including a substrate, a buffer layer on the substrate, a semiconductor layer on the buffer layer, a gate insulating layer on the semiconductor layer, a gate electrode on the gate insulating layer, an interlayer insulating layer on the entire surface of the substrate having the gate electrode, and having a first contact hole and a second contact hole, and source and drain electrodes on the interlayer insulating layer, insulated from the gate electrode, and having a portion connected with the semiconductor layer through the first contact hole.

It is therefore another feature of an embodiment of the present invention to provide the TFT including a metal layer forming source and drain electrodes further includes a metal layer pattern that disposes on the gate electrode.

It is therefore another feature of an embodiment of the present invention to provide the TFT having the first and the second contact holes in where the first contact hole is spaced apart from the second hole. The first contact hole partially exposes the semiconductor layer. The second contact hole partially exposes the gate electrode and is disposed in a region corresponding to a channel region of the semiconductor layer.

At least one of the above features and other advantages of the present invention may be realized by providing a method of fabricating the TFT including preparing a substrate, forming a buffer layer on the substrate, forming an amorphous semiconductor layer on the buffer layer, patterning the amorphous semiconductor layer to form a semiconductor layer pattern, forming a gate insulating layer on the semiconductor layer pattern, forming a gate electrode corresponding to the semiconductor layer pattern on the gate insulating layer, forming an interlayer insulating layer on the entire surface of the substrate, forming a first contact hole partially exposing the semiconductor layer, and a second contact hole partially exposing the gate electrode on the interlayer insulating layer, forming a metal layer on the entire surface of the substrate, applying an electrical field to the metal layer, and forming a semiconductor layer by crystallization of the semiconductor layer pattern and patterning the metal layer for source and drain electrodes to form source and drain electrodes insulated from the gate electrode and electrically connected with the semiconductor layer through the first contact hole.

It is therefore another feature of an embodiment of the present invention to provide the method of fabricating the TFT in where crystallization is performed while the metal layer is in contact with the gate electrode through the second contact hole.

It is therefore another feature of an embodiment of the present invention to provide the method of fabricating the TFT in where the electrical field of about 100 V/cm2to about 10,000 V/cm2is applied to the metal layer.

It is therefore another feature of an embodiment of the present invention to provide the method of fabricating the TFT in where the metal layer is formed to prevent exposure of the interlayer insulating layer. The voltage is applied to the metal layer.

It is therefore another feature of an embodiment of the present invention to provide the method of fabricating the TFT forming the first and second contact holes in where the first contact hole is formed to be spaced apart from the second contact hole. The second contact hole is formed to correspond to a channel region of the semiconductor layer.

Above feature and other advantages of the present invention may be realized by providing an OLED display device including a substrate, a buffer layer on the substrate, a semiconductor layer on the buffer layer, a gate insulating layer on the semiconductor layer, a gate electrode on the gate insulating layer; an interlayer insulating layer on the entire surface of the substrate having the gate electrode, and having a first contact hole and a second contact hole, source and drain electrodes on the interlayer insulating layer, insulated from the gate electrode, and having a portion connected with the semiconductor layer through the first contact hole, a passivation layer on the entire surface of the substrate, and a first electrode, an organic layer, and a second electrode, which are on the passivation layer and electrically connected with the source and drain electrodes.

It is therefore another feature of an embodiment of the present invention to provide the OLED display device including a metal layer forming source and drain electrodes further includes a metal layer pattern that disposes on the gate electrode.

It is therefore another feature of an embodiment of the present invention to provide the OLED display device including the first and the second contact holes in where the first contact hole is spaced apart from the second contact hole. The first contact hole partially exposes the semiconductor layer. The second contact hole partially exposes the gate electrode. In addition, the second contact hole is disposed in a region corresponding to a channel region of the semiconductor layer.

DETAILED DESCRIPTION OF THE INVENTION

Korean Patent Application No. 10-2008-0064001, filed on Jul. 2, 2008, in the Korean Intellectual Property Office, and entitled: “Thin Film Transistor, Method of Fabricating the Same, and Organic Light Emitting Diode Display Device Including the Same,” is incorporated by reference herein in its entirety.

FIGS. 1A to 1Dillustrate cross-sectional views of a TFT according to a first exemplary embodiment of the present invention.

Referring toFIG. 1A, a substrate100is provided. The substrate100may be formed of glass or plastic. A buffer layer110may be on the substrate100. The buffer layer110may prevent or reduce out-diffusion of moisture or impurities from the substrate100and/or may control a heat transfer rate during crystallization to facilitate the crystallization of an amorphous silicon layer. The buffer layer110may be, e.g., a silicon oxide layer, a silicon nitride layer, or a combination thereof.

Subsequently, an amorphous semiconductor layer120′, e.g., amorphous silicon, is formed on the substrate100and then patterned, thereby forming a semiconductor layer pattern120a(shown inFIG. 1B) to be used as a semiconductor layer120(shown inFIG. 1C).

Then, referring toFIG. 1B, a gate insulating layer130may be provided on the entire surface of the substrate100including the semiconductor layer pattern120a. The gate insulating layer130may be a silicon oxide layer, a silicon nitride layer, or a combination thereof.

A gate electrode140may be formed on the gate insulating layer130to correspond to the semiconductor layer pattern120a. The gate electrode140may be formed of a single layer, e.g., aluminum (Al), an Al alloy such as aluminum-neodymium (Al—Nd), etc., or a multi layer formed by stacking, e.g., an aluminum (Al) alloy on chromium (Cr) or molybdenum (Mo) alloy.

Referring toFIG. 1C, an interlayer insulating layer150may be formed on the entire surface of the substrate. The interlayer insulating layer150may be a silicon oxide layer, a silicon nitride layer, or a combination thereof.

After forming the interlayer insulating layer150, first and second contact holes160aand160bmay be formed. The first contact hole160amay be formed by partially etching the gate insulating layer130and the interlayer insulating layer150to partially expose the semiconductor layer pattern120a. The second contact hole160bmay be formed by partially etching the interlayer insulating layer150on the gate electrode140to partially expose the gate electrode.

A metal layer160may be formed on the entire surface of the substrate100. When the metal layer160is heated by application of an electrical field, heat generated from the metal layer160is transferred to the underlying semiconductor layer pattern120a, which is then crystallized into the semiconductor layer120, e.g., polycrystalline silicon.

The metal layer160is connected to the semiconductor layer120through the first contact hole160a, preventing formation of an arc during the crystallization and reducing defects thereof. Also, the metal layer160may be connected to the gate electrode140through the second contact hole160b, transferring heat generated from the metal layer160to the underlying semiconductor layer120through the gate electrode140, facilitating crystallization.

Here, for preferable crystallization, an electrical field of about 100 V per unit area (cm2) to about 10,000 V per unit area (cm2) may be applied for about 1 μs to about 1 sec. An electrical field of less than about 100 V per unit area (cm2) cannot generate sufficient Joule heat for crystallization, while an electrical field of more than 10,000 V per unit area (cm2) can generate a local arc. Further, when an electrical field is applied for less than 1 μs, crystallization may not be facilitated due to insufficient Joule heat, while when an electrical field is applied for more than 1 sec, the substrate may be bent or may form a defect along an edge due to heat transfer during crystallization.

Referring toFIG. 1D, after the semiconductor layer120is formed, the metal layer160may be patterned to form source and drain electrodes160sand160d. Here, a metal layer pattern160cmay remain in the second contact hole160bon the gate electrode140. Accordingly, the TFT according to an Exemplary embodiment 1 is completed.

The metal layer160is generally formed to a thickness suitable for the source and drain electrodes160sand160d, e.g., about 50 nm to about 200 nm. When the thickness of the metal layer160is less than about 50 nm, the metal layer160on the gate electrode140may not be uniform, so that heat cannot be uniformly transferred to the amorphous silicon layer, resulting in non-uniform crystallization. When the thickness of the metal layer160is greater than about 200 nm, the gate electrode140may no longer be suitable for thin film device. Thus, when the metal layer160has a thickness of about 200 nm or less, but exceeding 50 nm, uniform crystallization may be realized, while allowing the gate electrode to properly operate as an electrode suitable for the thin film device.

The metal layer160may be formed of one or more of molybdenum (Mo), chromium (Cr), tungsten (W), MoW, aluminum (Al), Al—Nd, titanium (Ti), titanium nitride (TiN), copper (Cu), a Mo alloy, an Al alloy and a Cu alloy.

Exemplary embodiment 2 is almost same as Exemplary embodiment 1 except for formation of a second contact hole. Thus, descriptions thereof may not be repeated.

Referring toFIG. 2A, by the same method described with references toFIGS. 1A and 1Bin Exemplary embodiment 1, the substrate100, the buffer layer110, the semiconductor layer pattern120a, e.g., amorphous silicon pattern, the gate insulating layer130, and the gate electrode140are formed. Then, an interlayer insulating layer150may be formed on the entire surface of the substrate100.

Next, the first contact hole160aand a second contact hole160b′ may be formed by etching. The gate insulating layer130and the interlayer insulating layer150may be partially etched, thereby forming the first contact hole160aand partially exposing the semiconductor layer pattern120athrough the first contact hole160a. The second contact hole160b′ may be formed by partially etching the interlayer insulating layer150, which further results in partially exposing the gate electrode140.

A region of the gate electrode140exposed through the second contact hole160b′ corresponds to a channel region120cof the semiconductor layer120(shown inFIG. 2B) to be formed later. When the second contact hole160b′ is formed as described above, a contact area between the metal layer160and the gate electrode140is formed above the channel region120cof the semiconductor layer120(shown inFIG. 2B). Such placement of the contact area results in effective heat transfer to the channel region, and crystallization of the channel region.

After the metal layer160is formed on the entire surface of the substrate100, the semiconductor layer pattern120ais crystallized into the semiconductor layer120by the same method as described in Exemplary embodiment 1.

Referring toFIG. 2B, the metal layer160is patterned by the same method as described in Exemplary embodiment 1, thereby forming source and drain electrodes160sand160d. Here, a metal layer pattern160c′ may remain on the gate electrode140in the second contact hole160b′. Accordingly, the TFT according to Exemplary embodiment 2 is completed.

FIG. 3illustrates a cross-sectional view of an OLED display device having a TFT according to an embodiment. The TFT is the same as that described in Exemplary embodiment 1.

Referring toFIG. 3, a passivation layer210may be formed on the entire surface of the substrate100including the TFT according to the exemplary embodiment described inFIG. 1D. The passivation layer210may be formed of an inorganic material, e.g., silicon oxide, silicon nitride, and silicate on glass, an organic material, e.g., polyimide, benzocyclobutene series resin and acrylate, or a combination thereof.

The passivation layer210may be etched to form a via hole exposing the source electrode160sor drain electrode160d. A first electrode220connected to one of the source and drain electrodes160sand160dthrough the via hole may be formed. The first electrode220may be an anode or a cathode. When the first electrode220is an anode, it may be formed of a transparent conductive layer, e.g., an ITO, IZO, or ITZO layer. When the first electrode220is a cathode, it may be formed of magnesium (Mg), calcium (Ca), aluminum (Al), silver (Ag), barium (Ba), or an alloy thereof.

Next, a pixel defining layer230may be formed on the passivation layer210and on the first electrode220. The pixel defining layer may include an opening partially exposing surface of the first electrode220and an organic layer240including an emission layer, formed on the exposed portion of the first electrode220. The organic layer240may further include at least one or more of a hole injection layer, a hole transport layer, a hole blocking layer, an electron blocking layer, an electrode injection layer, and an electron transport layer. As would be understood by a person of ordinary skill in the art, the organic layer240is a conductive layer. Then, a second electrode250may be formed on the pixel defining layer230and on the organic layer240. Accordingly, the OLED display device according to an exemplary embodiment is completed.

By forming the electrode on the amorphous semiconductor before crystallization, an occurrence of an arc caused by Joule heat during the crystallization may be prevented. Thus, defects can be reduced, and production yield can be improved.