A display apparatus includes a light-emitting diode disposed on a substrate, the light-emitting diode including a first electrode arranged in a display area, a second electrode disposed on the first electrode, and an emission layer disposed between the first electrode and the second electrode, and a main common voltage line arranged in a non-display area outside the display area, the main common voltage line electrically connected to the second electrode, the main common voltage line including an inner edge adjacent to the display area and an outer edge opposite to the inner edge, and a pattern including bars arranged in a direction from the inner edge to the outer edge.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application claims priority to Korean Patent Application No. 10-2021-0194548 under 35 U.S.C. §119, filed on December 31, 2021, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference.

1. Technical Field

The embodiments relate to a display apparatus.

2. Description of the Related Art

A display apparatus such as an organic light-emitting display apparatus includes transistors arranged in a display area to control luminance of light-emitting diodes. The transistors control light-emitting diodes to emit light of a selected color by using a data signal, a driving voltage, and a common voltage, which are transferred to the transistors.

One of the electrodes of the light-emitting diodes may receive a selected voltage via a transistor, and the other electrode may receive a voltage through an auxiliary wire.

SUMMARY

As the number of processes for manufacturing a display apparatus increases, it is necessary to precisely control the location of layers included in the display apparatus. When the layer or layers are misaligned, the quality of the display apparatus may be degraded, or defects may be generated. The embodiments provide a display apparatus having a structure for tracking locations of some layers of the display apparatus. However, the above objective is an example, and the scope of the embodiments of the disclosure is not limited by the above objective.

According to one or more embodiments, a display apparatus may include a light-emitting diode disposed on a substrate, the light-emitting diode including: a first electrode arranged in a display area, a second electrode on the first electrode, and an emission layer between the first electrode and the second electrode, and a main common voltage line arranged in a non-display area outside the display area, the main common voltage line electrically connected to the second electrode, the main common voltage line including an inner edge adjacent to the display area, an outer edge opposite to the inner edge, and a pattern including bars arranged in a direction from the inner edge to the outer edge.

The emission layer may overlap an entire area of the display area in a plan view. An edge of the emission layer may overlap the pattern in the non-display area in a plan view.

The main common voltage line may include an additional pattern that is spaced apart from the pattern. The second electrode may overlap the entire area of the display area in a plan view. An edge of the second electrode may overlap the additional pattern in the non-display area in a plan view.

The edge of the emission layer may be disposed between the edge of the second electrode and the display area.

The main common voltage line may include an additional pattern that is spaced apart from the pattern. The additional pattern may include bars arranged in a direction from the inner edge to the outer edge.

The main common voltage line may include a hole between neighboring ones among the bars of the pattern.

An interval between the neighboring ones among the bars of the pattern may be constant.

The main common voltage line and the first electrode may include a same material.

The main common voltage line may include exhaust holes arranged around the pattern, the exhaust holes overlapping in a plan view an organic insulating layer disposed below the main common voltage line.

The display apparatus may further include a bank layer overlapping an edge of the first electrode in a plan view, the bank layer including a light-emission opening overlapping the first electrode in a plan view. The bank layer may extend over the main common voltage line and may overlap the pattern in a plan view.

In the embodiments, a display apparatus may include light-emission areas disposed on a substrate and arranged in a display area, an encapsulation layer disposed on the light-emission areas, a color conversion-transmission layer disposed on the encapsulation layer, the color conversion-transmission layer including a color conversion portion that converts a color of light emitted from a light emitting area among the light-emission areas and a transmission portion that transmits light emitted from another light-emission area among the light-emission areas, and at least one pattern arranged in a non-display area outside the display area. The at least one pattern may include bars arranged in a first direction.

The display apparatus may further include first electrodes spaced apart from each other in the display area, the first electrodes respectively corresponding to the light-emission areas, an emission layer disposed on the first electrodes, and a second electrode disposed on the emission layer. At least one of the emission layer and the second electrode may overlap an entire area of the display area in a plan view. At least one an edge of the emission layer and an edge of the second electrode may overlap the at least one pattern in the non-display area in a plan view.

Each of the emission layer and the second electrode may overlap the entire area of the display area in a plan view. The edge of the emission layer and the edge of the second electrode may be disposed in the non-display area. The edge of the emission layer may be disposed between the edge of the second electrode and the display area.

The at least one pattern may include a first pattern and a second pattern. The first pattern and the second pattern may be spaced apart from each other. The edge of the emission layer may overlap the first pattern in a plan view. The edge of the second electrode may overlap the second pattern in a plan view.

The display apparatus may further include a bank layer overlapping an edge of each of the first electrodes and overlapping the at least one pattern in a plan view, the bank layer including light-emission openings respectively overlapping the first electrodes in a plan view.

The display apparatus may further include a main common voltage line arranged in the non-display area, the main common voltage line electrically connected to the second electrode. The at least one pattern corresponds to a portion of the main common voltage line.

The main common voltage line and the first electrodes may include a same material.

The main common voltage line may include a hole between neighboring ones among the bars of the at least one pattern.

An interval between the neighboring ones among the bars of the at least one pattern may be constant.

The main common voltage line may include exhaust holes arranged around the at least one pattern, the exhaust holes overlapping, in a plan view, an organic insulating layer disposed below the main common voltage line.

DETAILED DESCRIPTION OF THE EMBODIMENTS

As the disclosure allows for various changes and numerous embodiments, embodiments will be illustrated in the drawings and described in detail in the written description. The effects and features of the disclosure, and ways to achieve them will become apparent by referring to embodiments that will be described later in detail with reference to the drawings. However, the disclosure is not limited to the following embodiments but may be embodied in various forms.

Hereinafter, embodiments of the disclosure will be described in detail with reference to the accompanying drawings, and in the description with reference to the drawings, like reference numerals refer to like elements and redundant descriptions thereof will be omitted.

In the embodiments below, it will be understood when various elements such as a layer, a film, an area, or a plate is referred to as being “on” or “above” another element, it can be directly on or above the other element, or an intervening element may also be present. Also, in the drawings, for convenience of description, sizes of elements may be exaggerated or contracted. For example, since sizes and thicknesses of elements in the drawings are arbitrarily illustrated for convenience of explanation, the following embodiments are not limited thereto.

In the embodiments below, an x-axis, a y-axis, and a z-axis are not limited to three axes on a rectangular coordinates system but may be construed as including these axes. For example, an-x axis, a y-axis, and a z-axis may be at right angles or may also indicate different directions from one another, which are not at right angles.

FIG.1is a schematic perspective view illustrating a display apparatus according to an embodiment.

Referring toFIG.1, a display apparatus DV may include a display area DA and a non-display area NDA outside the display area DA. The display apparatus DV may provide an image through an array of sub-pixels arranged two-dimensionally on an x-y plane. The sub-pixels may include a first sub-pixel, a second sub-pixel, and a third sub-pixel; hereinafter, for convenience of description, the first sub-pixel is described as a red sub-pixel Pr, the second sub-pixel is described as a green sub-pixel Pg, and the third sub-pixel is described as a blue sub-pixel Pb.

The red sub-pixel Pr, the green sub-pixel Pg, and the blue sub-pixel Pb may be areas from which red, green, and blue light may be emitted, respectively, and the display apparatus DV may provide an image by using light emitted from these sub-pixels.

The non-display area NDA may be an area from which no image is provided, and may entirely surround the display area DA. In the non-display area NDA, a driver or a main voltage line for providing an electrical signal or power to sub-pixel circuits may be arranged. A pad, which is an area to which an electronic element or a printed circuit board may be electrically connected, may be included in the non-display area NDA.

The display area DA may have a polygonal shape including a quadrangle, as illustrated inFIG.1. For example, the display area DA may have a rectangular shape having a longer width than a length or a rectangular shape having a shorter width than a length, or a square shape. In other examples, the display area DA may have various shapes such as an oval or a circle.

FIG.2is a schematic cross-sectional view illustrating sub-pixels of a display apparatus according to an embodiment.

Referring toFIG.2, the display apparatus DV may include a circuit layer200on a substrate100(e.g., in a z-direction). The circuit layer200may include first to third sub-pixel circuits PC1, PC2, and PC3, and the first to third sub-pixel circuits PC1, PC2, and PC3may be electrically connected to first to third light-emitting diodes LED1, LED2, and LED3of a light-emitting diode layer300, respectively.

The first to third light-emitting diodes LED1, LED2, and LED3may include an organic light-emitting diode including an organic material. According to an embodiment, the first to third light-emitting diodes LED1, LED2, and LED3may include an inorganic light-emitting diode including an inorganic material. The inorganic light-emitting diode may include a PN junction diode including inorganic semiconductor-based materials. When a voltage is applied to the PN junction diode in a forward direction, holes and electrons are injected, and energy generated by recombination of the holes and electrons may be converted into light energy to emit light of a selected color. The inorganic light-emitting diode may have a width of several to several hundred micrometers or several to several hundred nanometers. In some embodiments, a light-emitting diode LED may include a light-emitting diode including quantum dots. As described above, an emission layer of the light-emitting diode LED may include an organic material, an inorganic material, quantum dots, an organic material and quantum dots, or an inorganic material and quantum dots.

The first to third light-emitting diodes LED1, LED2, and LED3may emit light of the same color. For example, light (e.g., blue light Lb) emitted from the first to third light-emitting diodes LED1, LED2, and LED3may pass through an encapsulation layer400on the light-emitting diode layer300and pass through the color conversion-transmission layer500.

The color conversion-transmission layer500may include optical portions that convert a color of light (e.g., blue light Lb) emitted from the light-emitting diode layer300or that transmit the light without converting it. For example, the color conversion-transmission layer500may include color conversion portions that convert light (e.g., the blue light Lb) emitted from the light-emitting diode layer300into light of another color, and a transmission portion that transmits the light emitted from the light-emitting diode layer300without converting the color of the light. The color conversion-transmission layer500may include a first color conversion portion510corresponding to the red sub-pixel Pr, a second color conversion portion520corresponding to the green sub-pixel Pg, and a transmission portion530corresponding to the blue sub-pixel Pb. The first color conversion portion510may convert the blue light Lb into red light Lr, and the second color conversion portion520may convert the blue light Lb into green light Lg. The transmission portion530may transmit the blue light Lb without converting it.

A color layer600may be disposed on the color conversion-transmission layer500. The color layer600may include first to third color filters610,620, and630having different colors. For example, the first color filter610may include a red color filter, the second color filter620may include a green color filter, and the third color filter630may include a blue color filter.

Color purity of light, on which color conversion is performed and which is transmitted by the color conversion-transmission layer500may be improved as the light passes through the first to third color filters610,620, and630. The color layer600may prevent or minimize external light (e.g., light incident from the outside of the display apparatus DV toward the display apparatus DV), which is reflected and viewed by a user.

A light-transmissive base layer700may be included on the color layer600. The light-transmissive base layer700may include glass or a light-transmissive organic material. For example, the light-transmissive base layer700may include a light-transmissive organic material such as an acrylic resin.

In an embodiment, when fabricating the display apparatus DV, the light-transmissive base layer700may be used as a substrate, and the color layer600and the color conversion-transmission layer500may be formed on the light-transmissive base layer700. The light-transmissive base layer700, the color layer600, and the color conversion-transmission layer500may be integrated with the other layers of the display apparatus DV such that the color conversion-transmission layer500faces the encapsulation layer400.

In other examples, the color conversion-transmission layer500and the color layer600may be sequentially formed on the encapsulation layer400, and the light-transmissive base layer700may be directly applied on the color layer600and cured. In an embodiment, an optical film, such as an anti-reflection (AR) film, may be disposed on the light-transmissive base layer700.

The display apparatus DV described above may be included in an electronic device displaying a moving picture or a still image, such as a television, a billboard, a screen for movie theaters, a monitor, a tablet personal computer (PC), or a notebook computer.

FIG.3illustrates respective optical portions of the color conversion-transmission layer500ofFIG.2.

Referring toFIG.3, the first color conversion portion510may convert the incident blue light Lb into red light Lr. As illustrated inFIG.3, the first color conversion portion510may include a first photosensitive polymer1151and first quantum dots1152and first scattering particles1153dispersed in the first photosensitive polymer1151.

The first quantum dots1152may be excited by blue light Lb to isotropically emit red light Lr which has a longer wavelength than blue light Lb. The first photosensitive polymer1151may include an organic material that is light-transmissive. The first scattering particles1153may scatter blue light Lb that is not absorbed into the first quantum dots1152and thus excite more first quantum dots1152, thereby increasing the color conversion efficiency. The first scattering particles1153may include, for example, titanium oxide (TiO2) or metal particles. The first quantum dots1152may be selected from a Group II-VI compound, a Group III-V compound, a Group IV-VI compound, a Group IV element, a Group IV compound, and combinations thereof.

The second color conversion portion520may convert incident blue light Lb into green light Lg. As illustrated inFIG.3, the second color conversion portion520may include a second photosensitive polymer1161and second quantum dots1162and second scattering particles1163dispersed in the second photosensitive polymer1161.

The second quantum dots1162may be excited by blue light Lb to isotropically emit green light Lg having a longer wavelength than blue light Lb. The second photosensitive polymer1161may include an organic material that is light-transmissive.

The second scattering particles1163may scatter blue light Lb that is not absorbed into the second quantum dots1162, and thus excite more second quantum dots1162, thereby increasing the color conversion efficiency. The second scattering particles1163may include, for example, titanium oxide (TiO2) or metal particles. The second quantum dots1162may be selected from a Group II-VI compound, a Group III-V compound, a Group IV-VI compound, a Group IV element, a Group IV compound, and combinations thereof.

In some embodiments, the first quantum dots1152and the second quantum dots1162may include a same material. The size of the first quantum dots1152may be greater than the size of the second quantum dots1162.

The transmission portion530may transmit the incident blue light Lb without converting the blue light Lb. As illustrated inFIG.3, the transmission portion530may include a third photosensitive polymer1171in which third scattering particles1173are dispersed. The third photosensitive polymer1171may include, for example, an organic material that is light-transmissive, such as a silicone resin or an epoxy resin, and may be the same material as the first and second photosensitive polymers1151and1161. The third scattering particles1173may scatter and emit the blue light Lb, and the first, second, and third scattering particles1153,1163, and1173may include a same material.

FIG.4is a schematic diagram of an equivalent circuit illustrating a light-emitting diode included in a display apparatus according to an embodiment and a sub-pixel circuit electrically connected to the light-emitting diode. A sub-pixel circuit PC illustrated inFIG.4may correspond to the first to third sub-pixel circuits PC1, PC2, and PC3described above with reference toFIG.2, and the light-emitting diode LED ofFIG.4may correspond to the first to third light-emitting diodes LED1, LED2, and LED3described above with reference toFIG.2.

Referring toFIG.4, a first electrode (e.g., an anode) of a light-emitting diode, for example, the light-emitting diode LED, may be electrically connected to the sub-pixel circuit PC, and a second electrode of the light-emitting diode LED (e.g., cathode) may be electrically connected to a main common voltage line to be described later with reference toFIG.5, to receive a common voltage ELVSS. The light-emitting diode LED may emit light with a luminance corresponding to the amount of current supplied from the sub-pixel circuit PC.

The light-emitting diode LED ofFIG.4may correspond to one of the first to third light-emitting diodes LED1, LED2, and LED3illustrated inFIG.2, and the sub-pixel circuit PC ofFIG.4may correspond to one of the first to third sub-pixel circuits PC1, PC2, and PC3illustrated inFIG.2.

The sub-pixel circuit PC may control the amount of current flowing from a driving voltage ELVDD to the common voltage ELVSS via the light-emitting diode LED in response to a data signal. The sub-pixel circuit PC may include a first transistor M1, a second transistor M2, a third transistor M3, and a storage capacitor Cst.

Each of the first transistor M1, the second transistor M2, and the third transistor M3may include an oxide semiconductor transistor including a semiconductor layer including an oxide semiconductor, or a silicon semiconductor including a semiconductor layer including polysilicon. According to the type of transistor, a first electrode may include one of a source electrode and a drain electrode, and a second electrode may include the other one of the source electrode and the drain electrode.

A first electrode of the first transistor M1may be electrically connected to a driving voltage line PL that supplies the driving voltage ELVDD, and a second electrode thereof may be electrically connected to the first electrode of the light-emitting diode LED. A gate electrode of the first transistor M1may be electrically connected to a first node N1. The first transistor M1may control, in response to a voltage of the first node N1, the amount of current flowing through the light-emitting diode LED from the driving voltage ELVDD.

The second transistor M2may include a switching transistor. A first electrode of the second transistor M2may be electrically connected to a data line DL, and a second electrode thereof may be electrically connected to the first node N1. A gate electrode of the second transistor M2may be electrically connected to the scan line SL. When a scan signal is supplied to a scan line SL, the second transistor M2may be turned on to electrically connect the data line DL to the first node N1.

The third transistor M3may include an initialization transistor and/or a sensing transistor. A first electrode of the third transistor M3may be electrically connected to a second node N2, and a second electrode thereof may be electrically connected to a sensing line ISL. A gate electrode of the third transistor M3may be electrically connected to a control line CL.

A storage capacitor Cst may be electrically connected between the first node N1and the second node N2. For example, a first capacitor electrode of the storage capacitor Cst may be electrically connected to the gate electrode of the first transistor M1, and a second capacitor electrode of the storage capacitor Cst may be connected to the first electrode of the light-emitting diode LED.

While the first transistor M1, the second transistor M2, and the third transistor M3are illustrated as NMOSs (n-type metal oxide semiconductors) inFIG.4, the disclosure is not limited thereto. For example, at least one of the first transistor M1, the second transistor M2, and the third transistor M3may include a PMOS (p-type metal oxide semiconductor).

While three transistors are illustrated inFIG.4, the disclosure is not limited thereto. The sub-pixel circuit PC may include four or more transistors.

FIG.5is a schematic plan view illustrating a display apparatus according to an embodiment.

As illustrated inFIG.5, a second electrode330of the light-emitting diode LED described above inFIG.4(the cathode of the light-emitting diode electrically connected to the line which supplies the common voltage ELVSS)) may overlap the entire display area DA. Multiple light-emitting diodes may be arranged in the display area DA, where the second electrode330may be shared by the light-emitting diodes as a common electrode.

An emission layer320of the light-emitting diode LED described above with reference toFIG.4may overlap the entire display area DA in a plan view, in a similar manger as the second electrode330. The emission layer320emitting light of a selected color (e.g., blue) may be shared by the light-emitting diodes as a common layer.

A main common voltage line110may be arranged in the non-display area NDA outside the display area DA. For example, the main common voltage line110may entirely surround the display area DA, in the non-display area NDA. The main common voltage line110may be electrically connected to a pad PAD through a connection line C-L. The pad PAD may be electrically connected to an electronic device or a printed circuit board (not shown).

The second electrode330of the light-emitting diodes may be electrically connected to the main common voltage line110in the non-display area NDA. For example, the second electrode330of the light-emitting diodes may directly contact a portion of the main common voltage line110in the non-display area NDA.

Auxiliary wires112extending from the main common voltage line110may be arranged in the display area DA. The auxiliary wires112may be arranged parallel to each other in the display area DA. When the display area DA has a relatively large area, a voltage drop of the second electrode330may occur in portions of the display area DA. For example, a voltage drop may occur in a central portion of the second electrode330located relatively far from the main common voltage line110, due to the resistance of the second electrode330itself. The voltage drop may deteriorate the display quality. However, according to an embodiment, the auxiliary wires112electrically connected to the main common voltage line110may extend across the display area DA, and as the auxiliary wires112may be electrically connected to the second electrode330in the display area DA, a voltage drop may be prevented.

FIG.6is an enlarged schematic plan view of portion VI ofFIG.5, andFIG.7is a schematic cross-sectional view taken along line A-A′ and line B-B′ ofFIG.6. InFIG.7, for convenience of description, the color conversion-transmission layer500, the color layer600, and the light-transmissive base layer700described above with reference toFIG.2are omitted. For example,FIG.7illustrates a stacked structure corresponding to the circuit layer200, the light-emitting diode layer300, and the encapsulation layer400on the substrate100.

Referring to the display area DA ofFIG.6, light-emission areas, for example, first to third light-emission areas EA1, EA2, and EA3, may be arranged in the display area DA. The first to third light-emission areas EA1, EA2, and EA3may emit light of the same color. For example, blue light emitted from each of the first to third light-emission areas EA1, EA2, and EA3may pass through the color conversion-transmission layer500as described above with reference toFIG.2and be converted into red light or green light or may pass through without color conversion to be viewed by a user.

Light-emitting diodes emitting blue light may be arranged in the first to third light-emission areas EA1, EA2, and EA3.FIG.7illustrates a first light-emitting diode LED1that may be arranged in the first light-emission area EA1. WhileFIG.7illustrates the first light-emitting diode LED1in the first light-emission area EA1, the second and third light-emitting diodes LED2and LED3(refer toFIG.2) arranged in the second light-emission area EA2and the third light-emission area EA3may also have the same structure as the first light-emitting diode LED1of the first light-emission area EA1.

Referring to the cross-section taken along line A-A′ inFIG.7, the circuit layer200may be disposed on the substrate100, and the light-emitting diode layer300including the light-emitting diode LED may be disposed on the circuit layer200, and the light-emitting diode layer300may be sealed by the encapsulation layer400.

The substrate100may include a glass material or a polymer resin, and the substrate100including a polymer resin may be flexible. For example, the shape of a display apparatus including the substrate100, which may be a flexible substrate, may be modified to be a curved, bendable, rollable, or foldable shape.

A buffer layer201may be disposed on the substrate100and prevent penetration of impurities from the substrate100into the transistor TR. The buffer layer201may include an inorganic insulating material such as silicon oxide, silicon nitride, and/or silicon oxynitride.

A semiconductor layer210of the transistor TR is disposed on the buffer layer201. The semiconductor layer210may include an oxide semiconductor. The oxide semiconductor may include indium gallium zinc oxide (IGZO), zinc tin oxide (ZTO), indium zinc oxide (IZO), or the like. In other examples, the semiconductor layer210may include polysilicon, amorphous silicon, or an organic semiconductor. The semiconductor layer210may include a channel region overlapping a gate electrode220in a plan view, and conductive regions may be disposed on both sides of the channel region and are doped with impurities or made conductive. One of the conductive regions may correspond to a source region and the other conductive region may correspond to a drain region.

The gate electrode220may overlap the channel region of the semiconductor layer210in a plan view, with a gate insulating layer203disposed therebetween. The gate electrode220may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), and the like, and may have a multi-layer or single-layer structure including such materials. The gate insulating layer203may include an inorganic insulating material such as silicon oxide, silicon nitride, and/or silicon oxynitride.

A source electrode230and a drain electrode240may be disposed on an interlayer insulating layer205, and may be electrically connected to the conductive regions of the semiconductor layer210. The interlayer insulating layer205may include an inorganic insulating material such as silicon oxide, silicon nitride, and/or silicon oxynitride.

The storage capacitor Cst may include at least two capacitor electrodes. In an embodiment,FIG.7illustrates the storage capacitor Cst including a first capacitor electrode250and a second capacitor electrode260, wherein the second capacitor electrode260includes first and second sub-capacitor electrodes261and262disposed on different layers from each other. The first and second sub-capacitor electrodes261and262may each overlap the first capacitor electrode250. WhileFIG.7illustrates that the second capacitor electrode260includes the first and second sub-capacitor electrodes261and262, in other examples, one of the first and second sub-capacitor electrodes261and262may be omitted.

An inorganic protective layer207may be formed on the transistor TR and the storage capacitor Cst. The inorganic protective layer207may include an inorganic insulating material such as silicon oxide, silicon nitride, and/or silicon oxynitride.

An organic insulating layer209may include an organic insulating material such as acrylic, benzocyclobutene (BCB), polyimide, or hexamethyldisiloxane (HMDSO).

The first light-emitting diode LED1may include a first electrode310, the emission layer320, and the second electrode330.

The first electrode310may include a transparent conductive material such as indium tin oxide (ITO), IZO, zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO) or aluminum zinc oxide (AZO). In other examples, the first electrode310may include a reflective layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a compound thereof. In other examples, the first electrode310may have a structure in which layers including ITO, IZO, ZnO or In2O3are above or below the reflective layer. For example, the first electrode310may have a three-layer structure in which an ITO layer, a silver (Ag) layer, and an ITO layer are stacked.

A bank layer BNL may be disposed on the first electrode310and may cover edges of the first electrode310. The bank layer BNL may include an opening BOP (hereinafter referred to as a “light-emission opening”) overlapping a portion of the first electrode310, and the light-emission opening BOP may expose a portion of the first electrode310. The light-emission opening BOP may define the first light emission area EA1of the first light-emitting diode LED1. For example, a width of the light-emission opening BOP may correspond to a width of the first light-emission area EA1. The bank layer BNL may include an organic material.

The emission layer320may overlap the first electrode310through the light-emission opening BOP. Although not illustrated, functional layer(s) may be disposed below and/or above the emission layer320. The functional layer(s) may include a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and/or an electron injection layer (EIL). As described with reference toFIG.5, the emission layer320may be formed to entirely cover the display area DA, and like the emission layer320, the functional layer(s) may also be arranged between the first electrode310and the second electrode330such that the functional layer(s) completely covers the display area DA.

The second electrode330may include a conductive material having a low work function. For example, the second electrode330may include a (semi)transparent layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or an alloy thereof. In other examples, the second electrode330may further include a layer such as ITO, IZO, ZnO or In2O3on the (semi)transparent layer.

The encapsulation layer400may be disposed on the second electrode330. The encapsulation layer400may include at least one inorganic encapsulation layer and at least one organic encapsulation layer.FIG.7illustrates the encapsulation layer400including a first inorganic encapsulation layer410, an organic encapsulation layer420, and a second inorganic encapsulation layer430.

The first inorganic encapsulation layer410may include an inorganic insulating material such as silicon oxide, silicon nitride, and/or silicon oxynitride. According to necessity, a capping layer including an organic insulating material and/or an inorganic insulating material, and a LiF layer may be between the first inorganic encapsulation layer410and the second electrode330.

As the first inorganic encapsulation layer410is formed along a structure therebelow, an upper surface thereof is not flat. The organic encapsulation layer420covers the first inorganic encapsulation layer410, and unlike the first inorganic encapsulation layer410, an upper surface of the organic encapsulation layer420located in the display area DA may be approximately flat. In detail, a portion of the organic encapsulation layer420corresponding to the display area DA may have a substantially flat upper surface, and the organic encapsulation layer420may have a gentle slope in the non-display area NDA.

The organic encapsulation layer420may be formed by applying a monomer and then curing the monomer. Partition walls may be arranged in the non-display area NDA to control the flow of the monomer.FIG.7illustrates first to fourth partition walls PW1, PW2, PW3, and PW4.

The first to fourth partition walls PW1, PW2, PW3, and PW4may be arranged outside the display area DA. The main common voltage line110may be disposed between the display area DA and the first to fourth partition walls PW1, PW2, PW3, and PW4. The first to fourth partition walls PW1, PW2, PW3, and PW4may include an organic insulating material. One of the first to fourth partition walls PW1, PW2, PW3, and PW4, for example, the fourth partition wall PW4arranged in an outermost portion, may support a mask used in a process of forming the emission layer320and/or the second electrode330.

The organic encapsulation layer420may include one or more materials selected from polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate, and hexamethyldisiloxane. The second inorganic encapsulation layer430may cover the organic encapsulation layer420and may include an inorganic insulating material such as silicon oxide, silicon nitride, and/or silicon oxynitride. The second inorganic encapsulation layer430may directly contact the first inorganic encapsulation layer410on some partition walls, for example, the third partition wall PW3and the fourth partition wall PW4.

As illustrated inFIG.6, the first electrodes310are spaced apart from each other and respectively arranged in the first to third light emission areas EA1, EA2, and EA3, whereas the emission layer320and the second electrode330may be deposited using a mask that may have an opening larger in area than the area of the display area DA. Accordingly, each of the emission layer320and the second electrode330may overlap the entire area of the display area DA, as described above with reference toFIG.5.

Each of the emission layer320and the second electrode330may have an area larger than that of the display area DA, and outer portions of the emission layer320and the second electrode330, which do not overlap the display area DA, may be located in the non-display area NDA.FIGS.6and7illustrate that an edge320E of the emission layer320and an edge330E of the second electrode330are disposed in the non-display area NDA.

The emission layer320may have a smaller area than the second electrode330. Accordingly, as illustrated inFIGS.6and7, the edge320E of the emission layer320may be disposed closer to the display area DA than the edge330E of the second electrode330. The edge320E of the emission layer320may be disposed between the edge330E of the second electrode330and the display area DA.

Referring to the cross-sections ofFIGS.6and7taken along line B-B′, the second electrode330may extend to the non-display area NDA and overlap a portion of the main common voltage line110. The main common voltage line110may be arranged on the same layer as the first electrode310of the light-emitting diode LED, for example, on the organic insulating layer209. The main common voltage line110may include the same material as the first electrode310of the light-emitting diode LED.

The main common voltage line110may include exhaust holes h that are two-dimensionally arranged along an x-direction and a y-direction, as shown inFIG.6. The exhaust holes h may provide a path for discharging gas included in the organic insulating layer209disposed below the main common voltage line110. When heat is applied to the organic insulating layer209during a manufacturing process of the display apparatus, the material included in the organic insulating layer209may be vaporized and discharged to the outside through the exhaust holes h. Accordingly, degradation in quality of light that is emitted from a light-emitting diode caused by gas generated from the organic insulating layer209and moves toward the display area DA due to lack of the exhaust holes h may be prevented.

The outer portion of the second electrode330disposed in the non-display area NDA may directly contact a portion of the main common voltage line110while overlapping the main common voltage line110. For example, the outer portion of the second electrode330may directly contact a portion of the main common voltage line110corresponding to a portion between the neighboring exhaust holes h, as illustrated inFIG.7. The exhaust holes h may be covered by a material corresponding to the bank layer BNL. The bank layer BNL includes an opening BNL-OP disposed between the adjacent exhaust holes h, and the outer portion of the second electrode330may directly contact the main common voltage line110through the opening BNL-OP of the bank layer BNL.

The main common voltage line110may include at least one pattern1100.FIG.6illustrates that the main common voltage line110includes patterns1100spaced apart from each other. For example, a pattern1100may be arranged adjacent to an inner edge of the main common voltage line110(an edge110E1which is close to the display area DA), and another pattern1100may be arranged adjacent to an outer edge of the main common voltage line110(an edge110E2that is relatively far from the display area DA and is disposed near the first partition wall PW1). For example, adjacent patterns1100may be arranged to be spaced apart from each other, without overlapping each other in a diagonal direction ob that is oblique to the x-direction and the y-direction.

The patterns1100may include a position tracking pattern or monitoring pattern for monitoring a position of the edge320E of the emission layer320and/or the edge330E of the second electrode330, which are located in the non-display area NDA. One of the patterns1100may be used to monitor or track the position of the edge320E of the emission layer320, and the other patterns1100may be used to monitor or track the position of the edge330E of the second electrode330. The patterns1100may be covered with the bank layer BNL as illustrated inFIG.7.

The patterns1100may include bars spaced apart by a selected interval. Hereinafter, the patterns1100are described with reference toFIGS.8A to8C.

FIG.8Ais an schematic excerpt plan view of the pattern1100ofFIG.6and its surroundings, andFIG.8Bis a schematic excerpt plan view illustrating the pattern1100ofFIG.8A, andFIG.8Cis a schematic plan view illustrating a pattern1100′ according to another embodiment.

Referring toFIG.8A, the pattern1100may be defined by first to fourth holes110H1,110H2,110H3, and110H4arranged in the main common voltage line110. A size (or width) of the first to fourth holes110H1,110H2,110H3, and110H4defining the pattern1100may each be larger than a size (or width) of the exhaust holes h arranged around the pattern1100.

The first hole110H1and the second hole110H2may be spaced apart from each other in a first direction (e.g., the x-direction), and may each have a length in a second direction (e.g., the y-direction). The third holes110H3and the fourth holes110H4may be arranged between the first hole110H1and the second hole110H2. The third holes110H3may be spaced apart from each other in the same direction between the first hole110H1and the second hole110H2(e.g., the first direction or a direction from the first hole110H1to the second hole110H2, x-direction). Similarly, the fourth holes110H4may be spaced apart from each other in the same direction between the first hole110H1and the second hole110H2(e.g., in the first direction or the direction from the first hole110H1to the second hole110H2, x-direction). One of the third holes110H3and one of the fourth holes110H4may be arranged along the second direction (e.g., the y-direction). Each of the third holes110H3and the fourth holes110H4may have a length along the second direction (e.g., the y-direction), and a length of each of the third holes110H3and the fourth hole110H4may be less than the length of the first hole110H1or the second hole110H2.

The pattern1100may include bars1112,1113,1114,1115, and1116arranged in a direction from the inner edge110E1to the outer edge110E2of the main common voltage line110described inFIG.6and as illustrated inFIG.8B(or in a direction away from the display area DA in an x-direction). The bars1112,1113,1114,1115, and1116may be arranged between the first hole110H1and the second hole110H2.FIG.8Billustrates five bars1112,1113,1114,1115, and1116for convenience of description, but the number of bars may be less than or equal to four or more than six.

At least a portion of each of the bars1112,1113,1114,1115, and1116may be spaced apart (or separated) from at least a portion of a neighboring (or adjacent) bar. A hole may be disposed between adjacent bars among the bars1112,1113,1114,1115, and1116. In an embodiment,FIG.8Billustrates that the third holes110H3and/or the fourth holes110H4are disposed between adjacent bars1112,1113,1114,1115, and1116. Portions of each of the bars1112,1113,1114,1115, and1116may be spaced apart from portions of another adjacent bar, with the third holes110H3and/or the fourth holes110H4included therebetween.

An interval (or a separation distance Ad) between two adjacent bars may have a constant value. The separation distance Ad may correspond to a width of the third holes110H3and/or the fourth holes110H4in the first direction. Each of the bars1112,1113,1114,1115, and1116may have the same width in the first direction. When the separation distance Ad has a constant value and each of the bars1112,1113,1114,1115, and1116has the same width, a distance between the center of a bar and the center of an adjacent bar (hereinafter referred to as a central distance AL) may be constant.

In some embodiments, the bars1112,1113,1114,1115, and1116having the constant central distance AL may be used as a ruler, and the pattern1100may be used to determine a position or alignment of the emission layer320and/or the second electrode330. For example, as described above with reference toFIG.6, by checking which of the bars among the bars1112,1113,1114,1115, and1116are overlapped by the edge320E of the emission layer320and/or the edge330E of the second electrode330, the position or alignment of the emission layer320and/or the second electrode330may be identified.

In some embodiments, a portion of each of the bars1112,1113,1114,1115, and1116may be connected to a portion of a neighboring bar. A portion of each of the bars1112to1116may be integral with each other. Referring toFIG.8B, a portion (e.g., a central portion) of a bar (hereinafter, referred to as “first bar”)1112disposed on a leftmost side may be connected to a portion (e.g., a central portion) of an adjacent bar(hereinafter, referred to as “ second bar”)1113via a first connection portion1111a.A portion of the second bar1113(e.g., a central portion) may be connected to a portion (e.g., a central portion) of another adjacent bar(hereinafter, referred to as “third bar”)1114via a second connection portion1111b.A portion of the third bar1114(e.g., a central portion) may be connected to a portion (e.g., a central portion) of another bar(hereinafter, referred to as “fourth bar”)1115via the third connection portion1111c.A portion (e.g., a central portion) of the fourth bar1115may be connected to a portion of another bar (hereinafter, referred to as “fifth bar”)1116(e.g., a central portion) via the fourth connection portion1111d.

The first to fourth holes110H1,110H2,110H3, and110H4described with reference toFIGS.8A and8Bmay be entirely covered (or overlapped) by the bank layer BNL in a plan view, as described inFIG.7. The pattern1100may be entirely covered by the bank layer BNL (refer toFIG.7). For example, the bars1112,1113,1114,1115, and1116and the first to fourth connection portions1111a,1111b,1111cand1111dof the pattern1100may be entirely covered by the bank layer BNL (refer toFIG.7).

FIG.8Billustrates that the central portions of each of the bars1112,1113,1114,1115, and1116are connected to each other, but the disclosure is not limited thereto. In other examples, an end of each of the bars1112,1113,1114,1115, and1116may be connected to each other.

Referring toFIG.8C, an end of each of the bars1112,1113,1114,1115, and1116may be connected to each other by the first to fourth connection portions1111a,1111b,1111cand1111d,and the pattern1100may have a comb-like shape.

The third holes110H3may be disposed between adjacent bars among the bars1112,1113,1114,1115, and1116. Unlike the third holes110H3that are spaced apart from each other between the first and second holes110H1and110H2in the first direction (e.g., the x-direction), a fourth hole110H4′ may be elongated between the first hole110H1and the second hole110H2in the first direction (e.g., the x direction).

Even in a pattern1100′ illustrated inFIG.8C, an interval (or a separation distance Ad) between two adjacent bars may have a constant value, and a central distance AL between the centers of any two adjacent bars may also have a constant value.

The patterns1100and1100′ described with reference toFIGS.6to8Care not located only in portion VI illustrated inFIG.5. As illustrated inFIG.5, they may be arranged along the longitudinal direction of the main common voltage line110having a substantially rectangular frame shape. For example, at least one of the patterns1100and1100′ may also be arranged in an upper portion, a lower portion, a left portion, and a right portion of the main common voltage line110having a shape of a quadrangular frame.

According to the embodiment as described above, positions of intermediate layers and/or a second electrode constituting the display apparatus may be accurately controlled without adding additional processes. However, the scope of the disclosure is not limited to these effects.