Method for forming an interfacial layer on a semiconductor using hydrogen plasma

Techniques include a method of forming an interfacial passivation layer between a first semiconductor material (such as germanium) and a high-k gate dielectric. Such techniques include using a hydrogen-based plasma formed using a slotted-plane antenna plasma processing system. Such a plasma treatment can be executed with substrate temperatures less than 380 degrees Celsius, and even down to about 200 degrees Celsius or below.

BACKGROUND OF THE INVENTION

Techniques herein relate to semiconductor fabrication, and more particularly, to forming protection layers.

Field Effect Transistors (FETs) are widely used in the electronics industry with varied processing applications including switching, amplification, filtering, and so forth. Metal Oxide Field Effect Transistors (MOSFETs) are a common type of FET device used in microelectronics. Transistor structures typically include a metal or polysilicon gate contact energized to create an electric field within a semiconductor channel, which allows current to conduct between source and drain regions.

Semiconductor fabrication techniques commonly use high-k dielectric materials for the gate dielectric layer along with metals other than polysilicon for the gate electrode. Such devices may be referred to as high-k/metal gate transistors. Interfacial layers or passivation layers can form between these layers. Depending on materials used, an interfacial layer can be beneficial or detrimental. Sometimes the formation of a given interfacial layer is unintended, while other times it is designed.

SUMMARY

Silicon has been the primary semiconductor material used in microelectronics. Expanding beyond use of silicon in semiconductor fabrication is helping to enable smaller and faster transistors. For example, using germanium (Ge) as a semiconductor material in microelectronics is becoming an important technology as integrated circuits shrink in size. Using germanium is beneficial because the mobility of electrons and holes of Ge semiconductors can be two-four times higher than that of silicon.

In an example fabrication technique, a gate insulator material is deposited over Ge and then this gate insulator material needs to be processed. Such processing conventionally involves one or more high temperature exposures either for dopant activation or annealing. Such high-temperature processes, however, can lead to diffusion of germanium and/or surface damage. To prevent diffusion, a protection layer or passivation layer can be formed between the germanium and the gate insulator. It is desirable to have this protection layer formed after depositing the gate insulator, and to form this protection layer at a low temperature to prevent thermal diffusion.

Conventionally thermal processing, however, is performed in furnaces, which can result in undesirable shrinking of materials. Such conventional protection layers that are formed in a furnace are typical processed using a formed gas anneal (FGA) process at a relatively high temperature in an environment of approximately 98% nitrogen and 2% hydrogen. Conventional techniques additionally include depositing a top electrode, such as platinum, on a substrate stack and using this electrode as a catalyst to help form a thin layer of germanium oxide. This catalyst electrode then needs to be removed from the stack, which increases cost and fabrication time.

Techniques disclosed herein include a method of forming an interfacial passivation layer between a first semiconductor material (such as germanium) and a high-k gate dielectric. Such techniques include using a hydrogen-based plasma formed using a slotted-plane antenna plasma processing system. Such a plasma treatment can be executed with substrate temperatures less than 380 degrees Celsius, and even down to about 200 degrees Celsius or below.

One embodiment includes a method of forming an interfacial passivation layer on a semiconductor layer of a substrate. This method includes depositing an insulation layer on a semiconductor layer of a substrate. The insulation layer can have a dielectric constant value greater than approximately 5. The substrate is disposed on a substrate holder in a plasma processing system. The plasma processing system has a slotted plane antenna that creates plasma via surface wave transmission of electromagnetic radiation. Then a process gas mixture is flowed into the plasma processing system. An interfacial passivation layer is then formed between the semiconductor layer and the insulation layer by forming a plasma from the process gas mixture such that the insulation layer is exposed to the plasma. During this plasma exposure, the substrate and/or plasma are maintained at a temperature less than about 380 degrees Celsius.

DETAILED DESCRIPTION

Techniques herein include methods for using a slotted plane antenna plasma processing system for treating high dielectric constant (high-k) materials for application with germanium, with III-V compounds, and with other related materials.

Referring toFIG. 1A, techniques include receiving a substrate including a semiconductor layer120(such as a germanium layer) and an insulation layer130deposited on the semiconductor layer120. The insulation layer130can include a high-k material (gate insulator) such as aluminum oxide. Position below the semiconductor layer can one or more underlying layers105and110, which can be selected from varied materials depending on a particular fabrication scheme. Underlying layer110can be, for example, titanium, and underlying layer105can be, for example, aluminum.

The substrate is positioned in a plasma chamber that uses a slotted-plane antenna to generate plasma. By way of a non-limiting example, a process gas mixture of Argon (600 sccm), H2 (18 sccm), and O2 (1.5 sccm) is flowed into a process chamber at a pressure of about 1-20 Torr with 1000-3000 watts of radio frequency power used to create plasma. Note that gas mixture ratios can be varied. The state temperature can be between about 200-380 degrees Celsius. Oxygen can be added to prevent an upper electrode of the process chamber from being damaged. Such upper electrodes can have silicon dioxide surface. By forming hydrogen radicals in the plasma, a metal electrode on the substrate is not needed to catalyze the formation of the thin protection layer. Hydrogen radicals are generated through the discharge, thus techniques herein do not require a metal layer as a catalyst, thereby accelerating the process. In other embodiments, however, a catalyst can still be used. Plasma can be formed in conditions that prevent sputtering of the high-k insulator layer. The plasma formed can promote or create a GeO2 bonding at the interface between, for example, Germanium and an aluminum oxide (Al2O3) capping layer. Using such a hydrogen plasma can decrease the interface trap density (Dit). Accordingly, as illustrated inFIG. 1B, interfacial layer121can be formed as a result of such a plasma treatment process.

The plasma chamber can be a slot plane antenna and/or processing system that generates plasma via surface wave transmission. With such a plasma processing system, plasma densities can be achieved greater than 1012 (cm−3), with low electron temperature, such as less than 1.5 eV, as well as having a low process temperature of less than 400 degrees Celsius. Alternatively, electron cyclotron resonance (ECR) oxygen plasma can be used.

In one example flow, a process can begin with deionized water cleaning for about 5 minutes of the substrate inFIG. 1A(prior to depositing layer130). Cleaning can be followed by water pre-pulsing of about 50 cycles at 270 C. Al2O3 can then be deposited via atomic layer deposition of about 6 nanometers, with 100 cycles at about 270 C. Next a plasma treatment step can be executed using flowing a process gas mixture of argon, H2, and O2, to form an interfacial passivation or protection layer121. After plasma treatment, an upper metal (Pt, Ti/Al) or electrode layer (if used) can be evaporated. Note that such techniques are substantially unaffected by a particular type of gate metal material.

One example embodiment includes a method of forming an interfacial passivation layer on a semiconductor layer of a substrate. The method can include depositing an insulation layer on a semiconductor layer of a substrate. The insulation layer (a gate insulator of a field effect transistor) has a dielectric constant value greater than approximately 5. The substrate is then disposed a substrate holder in a plasma processing system, such as a wafer holder or chuck. The plasma processing system has a slotted plane antenna that creates plasma via surface wave transmission of electromagnetic radiation. A process gas mixture is flow into the plasma processing system. An interfacial passivation layer is then formed between the semiconductor layer and the insulation layer by forming plasma from the process gas mixture (for example, above the substrate) such that the insulation layer is exposed to the plasma. This plasma exposure process is executed with the substrate and/or plasma being maintained at a temperature less than about 380 degrees Celsius.

Example process gas mixtures can comprises a hydrogen gas including H2. The process gas mixture can also comprises an oxygen gas, such as O2. In some embodiments, a ratio of hydrogen gas to oxygen gas is greater than about ten to one. The process gas mixture can also include a noble gas or other carrier gas. In some embodiments the oxygen gas comprises less than about five percent of the process gas mixture.

The insulation layer can be selected from various materials including aluminum oxide, hafnium oxide (HfO2), zirconium oxide (ZrO2), titanium oxide (TiO2), etc. The semiconductor layer can be a channel of a field effect transistor. The semiconductor layer can include germanium or doped germanium, or a III-V compound. The created interfacial passivation layer can comprise germanium oxide.

Plasma processing can be executed using a plasma processing system such as a slotted plane antenna system that creates plasma via surface wave transmission of microwaves generated from radio frequency power. Plasma processing systems are known.FIG. 2is a simplified schematic diagram of an example plasma processing system200. As seen inFIG. 2, the plasma processing system200comprises a gas supply system235coupled to the processing chamber110and configured to introduce a process gas to process space215. The process gas may comprise mixtures of gasses as described above. The plasma processing system200can be used for etching or heating or other treatments by adjusting system parameters,

Furthermore, the plasma processing system200includes a pumping system280coupled to the processing chamber210, and configured to evacuate the processing chamber210, as well as control the pressure within the processing chamber210. Optionally, the plasma processing system200further includes a control system290coupled to the processing chamber210, the substrate holder220, the plasma source230, the gas supply system235, and the pumping system280. The control system290can be configured to execute a process recipe for performing at least one of an etch process and a deposition process in the plasma processing system200. The plasma processing system200may be configured to process substrates of various sizes.

The processing chamber210is configured to facilitate the generation of plasma in process space215, and generate process chemistry in process space215adjacent a surface of the substrate225. Once plasma is formed in the process space215, heated electrons can collide with molecules in the process gas causing dissociation and the formation of reactive radicals for treating a substrate.

Referring now toFIG. 3, a schematic representation of a SWP source230is provided according to an embodiment. The SWP source230comprises an electromagnetic (EM) wave launcher232configured to couple EM energy in a desired EM wave mode to a plasma by generating a surface wave on a plasma surface260of the EM wave launcher232adjacent plasma. Furthermore, the SWP source230comprises a power coupling system290coupled to the EM wave launcher232, and configured to provide the EM energy to the EM wave launcher232for forming the plasma.

The EM wave launcher232includes a microwave launcher configured to radiate microwave power into process space215(seeFIG. 2). The EM wave launcher232is coupled to the power coupling system290via coaxial feed238through which microwave energy is transferred. The power coupling system290includes a microwave source292, such as a 2.45 GHz microwave power source. Microwave energy generated by the microwave source292is guided through a waveguide294to an isolator296for absorbing microwave energy reflected back to the microwave source292. Thereafter, the microwave energy is converted to a coaxial TEM (transverse electromagnetic) mode via a coaxial converter298. A tuner may be employed for impedance matching, and improved power transfer. The microwave energy is coupled to the EM wave launcher232via the coaxial feed238, wherein another mode change occurs from the TEM mode in the coaxial feed238to a TM (transverse magnetic) mode.

Referring now toFIGS. 4 and 5, a schematic cross-sectional view and a bottom view, respectively, of EM wave launcher232are provided according to an embodiment. The EM wave launcher232comprises the coaxial feed238having an inner conductor240, an outer conductor242, and insulator241, and a slot antenna246having a plurality of slots248coupled between the inner conductor240and the outer conductor242as shown inFIG. 4. The plurality of slots248permits the coupling of EM energy from a first region above the slot antenna246to a second region below the slot antenna246. The EM wave launcher232may further comprise a slow wave plate244, and a resonator plate250.

The number, geometry, size, and distribution of the slots248are all factors that can contribute to the spatial uniformity of the plasma formed in process space115(seeFIG. 1). Thus, the design of the slot antenna246may be used to control the spatial uniformity of the plasma in process space115.

As shown inFIG. 4, the EM wave launcher232may comprise a fluid channel256that is configured to flow a temperature control fluid for temperature control of the EM wave launcher232. Although not shown, the EM wave launcher232may further be configured to introduce a process gas through the plasma surface260to the plasma.

Referring still toFIG. 4, the EM wave launcher232may be coupled to an upper chamber portion of a plasma processing system, wherein a vacuum seal can be formed between an upper chamber wall252and the EM wave launcher232using a sealing device254. The sealing device254can include an elastomer O-ring.

The EM wave launcher232is fabricated with a first recess configuration262formed in the plasma surface260and a second recess configuration264formed in the plasma surface260according to one embodiment.

The resonator plate250comprises a dielectric plate having a plate diameter and a plate thickness. Therein, the plasma surface260on resonator plate250comprises a planar surface266within which the first recess configuration262and the second recess configuration264are formed. Alternatively, the resonator plate250comprises an arbitrary geometry. Therein, the plasma surface260may comprise a non-planar surface within which the first recess configuration and the second recess configuration are formed (not shown). For example, the non-planar surface may be concave, or convex, or a combination thereof.

Additional details regarding the design of plasma processing systems that can be used with method herein can be found in U.S. Pat. No. 8,415,884, entitled “Stable surface wave plasma source,” the content of which is herein incorporated by reference in its entirety.