Image sensor

An image sensor including a semiconductor substrate having a first surface and a second surface, and a pixel region having a photoelectric conversion region; a first conductive pattern in a first trench defining the pixel region and extending from the first surface toward the second surface; a second conductive pattern in a second trench shallower than the first trench and defined between a plurality of active patterns on the first surface of the pixel region; a transfer transistor and a plurality of logic transistors on the active patterns; and a conductive line on the second surface and electrically connected to the first conductive pattern.

CROSS-REFERENCE TO RELATED APPLICATION

A claim of priority under 35 U. S. C. § 119 is made to Korean Patent Application No. 10-2019-0002080 filed on Jan. 8, 2019 in the Korean Intellectual Property Office, the entirety of which is hereby incorporated by reference.

BACKGROUND

The present inventive concepts relate to image sensors, and more particularly to complementary metal oxide semiconductor (CMOS) image sensors.

Image sensor convert photonic images into electrical signals. Recent advances in computer and communication industries have led to increased demand for high performance image sensors in various consumer electronic devices such as digital cameras, camcorders, personal communication systems (PCSs), game consoles, security cameras, and medical micro-cameras, for example.

Image sensors may be classified into charged coupled device (CCD) type and CMOS image sensor type. CMOS image sensors are typically easy to operate and small-sized as corresponding signal processing circuitry may be integrated into a single chip. Also, CMOS image sensors require relatively small power consumption, which is useful in battery-powered applications. In addition, since processing technology of CMOS image sensors is compatible with CMOS processing technology, the cost of fabrication of CMOS image sensors is comparatively low. Accordingly, CMOS image sensors have been increasingly used as a result of advances in technology and the increased demand for high resolution applications.

SUMMARY

Embodiments of the inventive concepts provide an image sensor with enhanced dark current characteristics.

Embodiments of the inventive concepts provide an image sensor including a semiconductor substrate having a first surface and a second surface, the semiconductor substrate including a pixel region having a photoelectric conversion region; a first conductive pattern in a first trench, the first trench defining the pixel region and extending from the first surface toward the second surface; a second conductive pattern in a second trench, the second trench being shallower than the first trench and defined between a plurality of active patterns on the first surface in the pixel region; a transfer transistor and a plurality of logic transistors on the active patterns; and a conductive line on the second surface and electrically connected to the first conductive pattern.

Embodiments of the inventive concepts further provide an image sensor including a semiconductor substrate having a first surface and a second surface, the semiconductor substrate including a pixel region having a photoelectric conversion region; a first device isolation structure having a grid structure surrounding the pixel region, the first device isolation structure including a first conductive pattern; a second device isolation structure in the pixel region, the second device isolation structure including a second conductive pattern; and a conductive line on the second surface and electrically connected to the first conductive pattern. Top surfaces of the first and second device isolation structures are coplanar with the first surface. A distance between a bottom surface of the first device isolation structure and the second surface is less than a distance between a bottom surface of the second device isolation structure and the second surface.

Embodiments of the inventive concepts still further provide an image sensor including a semiconductor substrate having a first surface and a second surface, the semiconductor substrate including a pixel region having a photoelectric conversion region; a first device isolation structure having a grid structure surrounding the pixel region, the first device isolation structure including a first conductive pattern and a first dielectric pattern on the first conductive pattern; and a second device isolation structure in the pixel region. The second device isolation structure includes a second conductive pattern and a second dielectric pattern on the second conductive pattern. Top surfaces of the first dielectric pattern and the second dielectric pattern are coplanar with the first surface. A distance between a top surface of the second conductive pattern and the first surface is less than a distance between a top surface of the first conductive pattern and the first surface.

Embodiments of the inventive concepts also provide an image sensor including a semiconductor substrate having a first surface and a second surface opposite the first surface, the semiconductor substrate including a pixel region having a photoelectric conversion region; a first device isolation structure surrounding the pixel region, the first device isolation structure including a first conductive pattern and a first dielectric pattern on the first conductive pattern; a second device isolation structure in the pixel region, the second device isolation structure including a second conductive pattern and a second dielectric pattern on the second conductive pattern; and a conductive line on the second surface and electrically connected to the first conductive pattern.

DETAILED DESCRIPTION

Example embodiments of the inventive concepts will now be described more fully with reference to the accompanying drawings.

It should be understood that the accompanying figures are intended to illustrate general characteristics of methods, structure and/or materials utilized in certain example embodiments and to supplement the written description hereinafter provided. These drawings are not however to scale and may not precisely reflect the precise structural or performance characteristics of any given embodiment, and should not be interpreted as defining or limiting the range of values or properties encompassed by example embodiments. For example, the relative thicknesses and positioning of molecules, layers, regions and/or structural elements may be reduced or exaggerated for clarity. The use of similar or identical reference numbers in the various drawings is intended to indicate the presence of a similar or identical element or feature.

FIG. 1illustrates a block diagram showing an image sensor according to embodiments of the inventive concepts.

Referring toFIG. 1, image sensor1000includes an active pixel sensor array1, a row decoder2, a row driver3, a column decoder4, a timing generator5, a correlated double sampler (CDS)6, an analog-to-digital converter (ADC)7, and an input/output (I/O) buffer8.

The active pixel sensor array1may include a plurality of two-dimensionally arranged unit pixels, each of which is configured to convert optical signals into electrical signals. The active pixel sensor array1may be driven by a plurality of driving signals such as a pixel selection signal, a reset signal, and a charge transfer signal from the row driver3. The correlated double sampler6is provided with the converted electrical signals.

The row driver3provides the active pixel sensor array1with several of the driving signals for driving several unit pixels in accordance with a decoded result obtained from the row decoder2. In the case that the unit pixels are arranged in a matrix shape, the driving signals may be provided for respective rows.

The timing generator5provides timing and control signals to the row decoder2and the column decoder4.

The correlated double sampler6receives the electrical signals generated from the active pixel sensor array1, and holds and samples the received electrical signals. The correlated double sampler6may perform a double sampling operation to sample a specific noise level and a signal level of the electrical signal, and outputs a difference level corresponding to a difference between the noise and signal levels.

The analog-to-digital converter7converts analog signals, which correspond to the difference level received from the correlated double sampler6, into digital signals, and output the converted digital signals.

The input/output buffer8latches the digital signals and then sequentially outputs the latched digital signals to an image signal processing unit (not shown) in response to the decoded result obtained from the column decoder4.

FIG. 2illustrates a circuit diagram showing an active pixel sensor array of an image sensor according to embodiments of the inventive concepts.

Referring toFIGS. 1 and 2, sensor array1includes a plurality of unit pixels PX, which may be arranged in a matrix shape. Each of the unit pixels PX may include a transfer transistor TX and logic transistors RX, SX, and DX. In this case, the logic transistors RX, SX, and DX ofFIG. 2include a reset transistor RX, a select transistor SX, and a drive transistor DX. The transfer transistor TX includes a transfer gate TG, the select transistor SX includes a select gate SG and the reset transistor RX includes a reset gate RG. Each of the unit pixels PX further includes a photoelectric conversion device PD and a floating diffusion region FD.

The photoelectric conversion device PD may create and accumulate photo-charges in proportion to an amount of externally incident light. The photoelectric conversion device PD may for example include a photodiode, phototransistor, a photogate, a pinned photodiode, or a combination thereof. The transfer transistor TX may transfer charges generated in the photoelectric conversion device PD into the floating diffusion region FD. The floating diffusion region FD may accumulatively store the charges generated and transferred from the photoelectric conversion device PD. The drive transistor DX is controlled by an amount of photo-charges accumulated in the floating diffusion region FD.

The reset transistor RX may periodically reset the charges accumulated in the floating diffusion region FD. The reset transistor RX includes a drain electrode connected to the floating diffusion region FD and a source electrode connected to a power voltage VDD. When the reset transistor RX is turned on, the floating diffusion region FD is supplied with the power voltage VDDconnected to the source electrode of the reset transistor RX. Accordingly, when the reset transistor RX is turned on, the charges accumulated in the floating diffusion region FD may be exhausted and thus the floating diffusion region FD may be reset.

The drive transistor DX may serve as a source follower buffer amplifier. The drive transistor DX amplifies a variation in electrical potential of the floating diffusion region FD and outputs the amplified electrical potential to an output line VOUT.

The select transistor SX may select each row of the unit pixels PX to be readout. When the select transistor SX is turned on, the power voltage VDDis applied to a drain electrode of the drive transistor DX.

FIG. 3illustrates a plan view of an image sensor according to embodiments of the inventive concepts.FIGS. 4A and 4Billustrate cross-sectional views respectively taken along lines I-I′ and II-II′ ofFIG. 3.

Referring toFIGS. 3, 4A, and 4B, an image sensor according to some embodiments of the inventive concepts includes a photoelectric conversion layer10, a connection line layer20, and an optical transmittance layer30. When viewed in cross-section, the photoelectric conversion layer10is disposed between the connection line layer20and the optical transmittance layer30. The photoelectric conversion layer10may include a semiconductor substrate100and photoelectric conversion regions110provided in the semiconductor substrate100. The photoelectric conversion regions110convert externally incident light into electrical signals.

The semiconductor substrate100has a first surface (or a front surface)100aand a second surface (or a rear surface)100bthat face each other. The connection line layer20is disposed on the first surface100aof the semiconductor substrate100, and the optical transmittance layer30is disposed on the second surface100bof the semiconductor substrate100.

The semiconductor substrate100may be a substrate in which an epitaxial layer is formed on a bulk silicon substrate having a first conductive type (e.g., p-type) the same as that of the epitaxial layer. The bulk silicon substrate may be removed in fabricating an image sensor, and thus the semiconductor substrate100may include only the p-type epitaxial layer. As another example, the semiconductor substrate100may be a bulk semiconductor substrate having a well of the first conductive type. As still another example, the semiconductor substrate100may include various substrates, such as for example an n-type epitaxial layer, a bulk silicon substrate, and a silicon-on-insulator (SOI) substrate.

The semiconductor substrate100includes a plurality of pixel regions PR defined by a first device isolation structure101. The pixel regions PR may correspond to the unit pixels PX ofFIGS. 1 and 2. The pixel regions PR may be arranged in a matrix shape along first and second directions D1and D2intersecting each other. The first device isolation structure101prevents photo-charges generated from light incident onto each pixel region PR from randomly drifting into neighboring pixel regions PR. For example, the first device isolation structure101may suppress cross-talk phenomenon between the pixel regions PR.

When viewed in plan, the first device isolation structure101may have a grid structure. When viewed in plan, the first device isolation structure101may completely surround each of the pixel regions PR. For example, the first device isolation structure101may include first segments that extend in the second direction D2and are spaced apart from each other in the first direction D1, and also second segments that extend in the first direction D1and are spaced apart from each other in the second direction D2. A pair of first segments and a pair of second segments define the pixel region PR. For example, the pixel region PR is surrounded by a pair of first segments and a pair of second segments.

The first device isolation structure101extends along a third direction D3from the first surface100atoward the second surface100bof the semiconductor substrate100. The first device isolation structure101may penetrate the semiconductor substrate100. For example, the first device isolation structure101may have a depth substantially the same as a vertical thickness of the semiconductor substrate100. The first device isolation structure101may have a width that gradually decreases as approaching the second surface100bfrom the first surface100aof the semiconductor substrate100.

The photoelectric conversion regions110are disposed in corresponding pixel regions PR. The photoelectric conversion regions110may be impurity regions doped with impurities of a second conductive type (e.g., n-type) opposite to that of the semiconductor substrate100. For example, the photoelectric conversion regions110may be adjacent to the second surface100bof the semiconductor substrate100. The photoelectric conversion regions110may be disposed closer to the second surface100bthan to the first surface100a.

Each of the photoelectric conversion regions110includes a first region adjacent to the first surface100aand a second region adjacent to the second surface100b. Impurity concentration of the first and second regions of the photoelectric conversion regions110may be different. Thus, a potential slope may exist between the first and second surfaces100aand100bof the photoelectric conversion regions110of the semiconductor substrate100.

The semiconductor substrate100and the photoelectric conversion regions110together form photodiodes. For example, a photodiode may be constituted by a p-n junction between the semiconductor substrate100of the first conductive type and a photoelectric conversion region110of the second conductive type. The photoelectric conversion regions110constituting photodiodes may generate and accumulate photo-charges in proportion to intensity of incident light.

The semiconductor substrate100includes a second device isolation structure103provided on first surface100athat defines first active patterns ACT1, second active patterns ACT2, and third active patterns ACT3. Each of the pixel regions PR includes the first active pattern ACT1, the second active pattern ACT2, and the third active pattern ACT3. The first active pattern ACT1, the second active pattern ACT2, and the third active pattern ACT3are spaced apart from each other. The first active pattern ACT1, the second active pattern ACT2, and the third active pattern ACT3may have different size with respect to each other. The first active pattern ACT1as shown inFIG. 3is disposed between the second active pattern ACT2and the third active pattern ACT3.

When viewed in plan, the first active pattern ACT1is disposed on a central area of the pixel region PR. The first active pattern ACT1may have an L-shaped planar shape. When viewed in plan, each of the second and third active patterns ACT2and ACT3are disposed on an edge area of the pixel region PR. Each of the second and third active patterns ACT2and ACT3may have a linear shape extending in the second direction D2. It should be understood that the planar shapes of the first, second, and third active patterns ACT1, ACT2, and ACT3are not limited to that shown inFIG. 3, but may be variously changed in other embodiments of the inventive concepts.

The second device isolation structure103may have a width that gradually decreases approaching the second surface100bfrom the first surface100aof the semiconductor substrate100. The second device isolation structure103may have a bottom surface vertically spaced apart from the photoelectric conversion regions110. The second device isolation structure103may have a depth less than that of the first device isolation structure101. The first device isolation structure101may overlap a portion of the second device isolation structure103.

Transfer transistors TX and logic transistors RX, SX, and DX identical or similar to those described with reference toFIG. 2are provided on the first surface100aof semiconductor substrate100. The transfer transistor TX is provided on the first active pattern ACT1of each of the pixel regions PR. The transfer transistor TX may be electrically connected to the photoelectric conversion region110.

The transfer transistor TX includes a transfer gate TG and a floating diffusion region FD on the first active pattern ACT1. The transfer gate TG may include a lower segment inserted into the semiconductor substrate100, and also an upper segment connected to the lower segment and protruding above the first surface100aof the semiconductor substrate100. A gate dielectric layer GI is interposed between the transfer gate TG and the semiconductor substrate100. The floating diffusion region FD is placed in the first active pattern ACT1on a side of the transfer gate TG. The floating diffusion region FD has the second conductive type (e.g., n-type) opposite to that of the semiconductor substrate100.

The drive transistor DX and the select transistor SX are provided on the second active pattern ACT2of each of the pixel regions PR. The drive transistor DX and the select transistor SX respectively include a drive gate SFG and a select gate SG on the second active pattern ACT2. The reset transistor RX as provided on the third active pattern ACT3of each of the pixel regions PR. The reset transistor RX includes a reset gate RG on the third active pattern ACT3.

The gate dielectric layer GI is interposed between the semiconductor substrate100and each of the drive, select, and reset gates SFG, SG, and RG. Impurity regions DR may be provided on an upper portion of each of the second and third active patterns ACT2and ACT3on opposite sides of each of the drive, select, and reset gates SFG, SG, and RG. For example, the impurity regions DR may have the second conductive type (e.g., n-type) opposite to that of the semiconductor substrate100.

The connection line layer20may include first, second, and third interlayer dielectric layers221,222and223, and also include first and second connection lines212and213. The first interlayer dielectric layer221is provided on (over) the first surface100aof the semiconductor substrate100as covering the transfer transistors TX and the logic transistors RX, SX, and DX. The first and second connection lines212and213may be disposed in the respective second and third interlayer dielectric layers222and223stacked on the first interlayer dielectric layer221.

The first and second connection lines212and213may be electrically connected to the transfer transistors TX and the logic transistors RX, SX, and DX through first contacts CT1penetrating the first interlayer dielectric layer221. In certain embodiments, the first and second connection lines212and213may be arranged regardless of an arrangement of the photoelectric conversion regions110. When viewed in plan, the first and second connection lines212and213may cross over the photoelectric conversion regions110.

The optical transmittance layer30includes color filters303and micro-lenses307. The optical transmittance layer30focuses and filters externally incident light, so that the photoelectric conversion layer10may be provided with the focused and filtered light.

For example, the color filters303and the micro-lenses307may be provided on the second surface100bof the semiconductor substrate100. The color filters303may be disposed on corresponding pixel regions PR. The micro-lenses307may be disposed on corresponding color filters303. A first planarized layer301may be disposed between the color filters303and the second surface100bof the semiconductor substrate100, and a second planarized layer305may be disposed between the color filters303and the micro-lenses307.

The color filters303may include primary-color filters. For example, the color filters303may include respective green-colored, red-colored, and blue-colored filters. The color filters303may be arranged in Bayer pattern format. As another example, the color filters303may include different colored filters such as respective cyan, magenta, or yellow colored filters.

The micro-lenses307may have convex shape to focus incident light onto the pixel regions PR. When viewed in plan, the micro-lenses307may overlap corresponding photoelectric conversion regions110.

The first device isolation structure101and the second device isolation structure103will be described in detail hereinafter. A first trench TR1is provided to define the pixel regions PR. The first trench TR1penetrates the semiconductor substrate100. When viewed in plan, the first trench TR1may have a grid structure. The first device isolation structure101may fill the first trench TR1.

The first device isolation structure101includes a first conductive pattern SP1, a first dielectric pattern IP1, and a second dielectric pattern IP2. The first dielectric pattern IP1covers an inner sidewall of the first trench TR1. The first conductive pattern SP1and the second dielectric pattern IP2may fill the first trench TR1. The second dielectric pattern IP2may fill an upper portion of the first trench TR1, and the first conductive pattern SP1may fill a remaining portion of the first trench TR1other than the upper portion.

The second dielectric pattern IP2may be adjacent to the first surface100a, and have a top surface coplanar with the first surface100a. The first conductive pattern SP1may be adjacent to the second surface100b, and have a bottom surface coplanar with the second surface100b.

The first dielectric pattern IP1is interposed between the first conductive pattern SP1and the semiconductor substrate100. The first dielectric pattern IP1separates the first conductive pattern SP1from the semiconductor substrate100. The first dielectric pattern IP1insulates the first conductive pattern SP1from the semiconductor substrate100. For example, the first conductive pattern SP1may include n-type doped polysilicon or p-type doped polysilicon. Each of the first and second dielectric patterns IP1and IP2may for example include a silicon oxide layer, a silicon oxynitride layer, or a silicon nitride layer.

A conductive line CL may be provided on an area around the second surface100bof the semiconductor substrate100. The conductive line CL may be electrically connected to the first conductive pattern SP1of the first device isolation structure101. For example, the conductive line CL may be in direct contact with the bottom surface of the first conductive pattern SP1.

A negative voltage may be applied to the conductive line CL. For example, the conductive line CL may be electrically connected to a charge pump, and supplied with a negative voltage from the charge pump. The negative voltage may be applied as a constant voltage.

The first conductive pattern SP1may be supplied with the negative voltage through the conductive line CL. When the first conductive pattern SP1is supplied with the negative voltage, positive charges generated from the pixel region PR may thus be eliminated by the first conductive pattern SP1surrounding the pixel region PR. As a result, dark current characteristics of the image sensor may be improved.

A second trench TR2is provided to define the first, second, and third active patterns ACT1, ACT2, and ACT3of the pixel region PR. The second trench TR2may extend from the first surface100atoward the second surface100b. The second trench TR2may be shallower than the first trench TR1. The second device isolation structure103may fill the second trench TR2. A bottom surface of the first device isolation structure101may be positioned closer to the second surface100bthan a bottom surface of the second device isolation structure103is positioned. That is, a distance between the bottom surface of the first device isolation structure101and the second surface100bmay be less than a distance between the bottom surface of the second device isolation structure103and the second surface100b.

The second device isolation structure103includes a second conductive pattern SP2, a third dielectric pattern IP3, and a fourth dielectric pattern IP4. The third dielectric pattern IP3covers an inner sidewall and a bottom surface of the second trench TR2. The second conductive pattern SP2and the fourth dielectric pattern IP4may fill the second trench TR2. The fourth dielectric pattern IP4may fill an upper portion of the second trench TR2, and the second conductive pattern SP2may fill a lower portion of the second trench TR2other than the upper portion.

The fourth dielectric pattern IP4may be adjacent to the first surface100a, and have a top surface coplanar with the first surface100a. The top surface of the fourth dielectric pattern IP4may be coplanar with the top surfaces of the first and second dielectric patterns IP1and IP2of the first device isolation structure101.

The third dielectric pattern IP3is interposed between the second conductive pattern SP2and the semiconductor substrate100. The third dielectric pattern IP3separates the second conductive pattern SP2from the semiconductor substrate100. The third dielectric pattern IP3insulates the second conductive pattern SP2from the semiconductor substrate100.

The first dielectric pattern IP1of the first device isolation structure101separates the second conductive pattern SP2of the second device isolation structure103from the first conductive pattern SP1of the first device isolation structure101. The first dielectric pattern IP1insulates the second conductive pattern SP2from the first conductive pattern SP1. Because the second conductive pattern SP2is not electrically connected to the first conductive pattern SP1, even if a negative voltage is applied to the first conductive pattern SP1, negative voltage is not applied from the first conductive pattern SP1to the second conductive pattern SP2.

The second conductive pattern SP2may include, for example, n-type doped polysilicon or p-type doped polysilicon. Each of the third and fourth dielectric patterns IP3and IP4may for example include a silicon oxide layer, a silicon oxynitride layer, or a silicon nitride layer.

The second conductive pattern SP2and the first conductive pattern SP1may have their top surfaces at different levels. The top surface of the second conductive pattern SP2may be located at a higher level than that of the top surface of the first conductive pattern SP1. The top surface of the second conductive pattern SP2may be closer to the first surface100athan the top surface of the first conductive pattern SP1is to the first surface100aof the semiconductor substrate100. That is, a distance between the top surface of the second conductive pattern SP2and the first surface100amay be less than a distance between the top surface of the first conductive pattern SP1and the first surface100a.

At least one second contact CT2may be provided to penetrate the first interlayer dielectric layer221and the fourth dielectric pattern IP4to have electrical connection with the second conductive pattern SP2. At least one first connection line212may be electrically connected through the at least one second contact CT2to the second conductive pattern SP2. The second conductive pattern SP2may be supplied with a negative voltage through the at least one first connection line212and the at least one second contact CT2. For example, similar to the conductive line CL, the at least one first connection line212may be electrically connected to a charge pump. With the second conductive pattern SP2supplied with the negative voltage, positive charges generated from the pixel region PR may be eliminated not only by the first conductive pattern SP1but also by the second conductive pattern SP2. As a result, dark current characteristics of the image sensor may be further improved.

FIGS. 5, 7, and 9illustrate plan views of a method of fabricating an image sensor according to embodiments of the inventive concepts.FIGS. 6A, 8A, and 10Aillustrate cross-sectional views taken along line I-I′ ofFIGS. 5, 7, and 9, respectively.FIGS. 6B, 8B, and 10Billustrate cross-sectional views taken along line II-II′ ofFIGS. 5, 7, and 9, respectively.

Referring toFIGS. 5, 6A, and 6B, a semiconductor substrate100is provided as having a first surface100aand a second surface100bfacing each other. The semiconductor substrate100may be doped with impurities to have a first conductive type (e.g., p-type).

A second device isolation structure103is formed on the first surface100aof the semiconductor substrate100. For example, the first surface100aof the semiconductor substrate100may be patterned to form a second trench TR2defining first, second, and third active patterns ACT1, ACT2, and ACT3. By formation of the second trench TR2, the semiconductor substrate100is recessed at first surface100aat positions other than the first, second, and third active patterns ACT1, ACT2, and ACT3.

A third dielectric pattern IP3is formed to partially fill the second trench TR2. The formation of the third dielectric pattern IP3may include conformally forming a first dielectric layer on the first surface100aof the semiconductor substrate100. The third dielectric pattern IP3may cover an inner sidewall and a bottom surface of the second trench TR2. The first dielectric layer may include, for example, a silicon oxide layer, a silicon oxynitride layer, or a silicon nitride layer.

A second conductive pattern SP2is formed on the third dielectric pattern IP3. The formation of the second conductive pattern SP2may include forming a first conductive layer filling the second trench TR2and performing an etch-back process on the first conductive layer. The second conductive pattern SP2thus fills a lower portion of the second trench TR2. The second conductive pattern SP2may have a top surface lower than top surfaces of the first, second, and third active patterns ACT1, ACT2, and ACT3. The first conductive layer may include, for example, n-type doped polysilicon or p-type doped polysilicon.

A fourth dielectric pattern IP4is formed on the second conductive pattern SP2. The formation of the fourth dielectric pattern IP4may include forming a second dielectric layer filling an upper portion of the second trench TR2. The second dielectric layer may include, for example, a silicon oxide layer, a silicon oxynitride layer, or a silicon nitride layer. The first dielectric layer and the second dielectric layer may undergo a planarization process that is performed until the top surfaces of the first, second, and third active patterns ACT1, ACT2, and ACT3are exposed. Thus, the first dielectric layer and the second dielectric layer may be respectively formed into the third dielectric pattern IP3and the fourth dielectric pattern IP4. The second device isolation structure103may be constituted by the second conductive pattern SP2, the third dielectric pattern IP3, and the fourth dielectric pattern IP4that are formed in the second trench TR2.

Referring toFIGS. 7, 8A, and 8B, a first device isolation structure101is formed on the first surface100aof the semiconductor substrate100. For example, the first surface100aof the semiconductor substrate100may be patterned to form a first trench TR1defining pixel regions PR. The pixel regions PR may be two-dimensionally arranged in a first direction D1and a second direction D2that intersect each other. By formation of the first trench TR1, the second device isolation structure103is partially etched. The first trench TR1is formed to penetrate a portion of the second device isolation structure103. When viewed in plan, the first trench TR1may be formed as a grid structure.

The first trench TR1extends from the first surface100atoward the second surface100b. For example, the first trench TR1may have a width that gradually decreases approaching the second surface100bfrom the first surface100a. The first trench TR1is deeper than the second trench TR2filled with the second device isolation structure103. The first trench TR1has a bottom surface vertically spaced apart from the second surface100b.

A first dielectric pattern IP1is formed to partially fill the first trench TR1. The formation of the first dielectric pattern IP1may include conformally forming a third dielectric layer on the first surface100aof the semiconductor substrate100. The first dielectric pattern IP1may cover an inner sidewall and the bottom surface of the first trench TR1. The third dielectric layer may include, for example, a silicon oxide layer, a silicon oxynitride layer, or a silicon nitride layer.

A first conductive pattern SP1is formed on the first dielectric pattern IP1. The formation of the first conductive pattern SP1may include forming a second conductive layer filling the first trench TR1and performing an etch-back process on the second conductive layer. The first conductive pattern SP1thus fills a lower portion of the first trench TR1. For example, the first conductive pattern SP1may fill a remaining portion of the first trench TR1other than an upper portion of the first trench TR1. The first conductive pattern SP1has a top surface lower than top surfaces of the first, second, and third active patterns ACT1, ACT2, and ACT3. The top surface of the first conductive pattern SP1may be lower than that of the second conductive pattern SP2. The second conductive layer may include, for example, n-type doped polysilicon or p-type doped polysilicon.

A second dielectric pattern IP2is formed on the first conductive pattern SP1. The formation of the second dielectric pattern IP2may include forming a fourth dielectric layer filling an upper portion of the first trench TR1. The fourth dielectric layer may include, for example, a silicon oxide layer, a silicon oxynitride layer, or a silicon nitride layer. The third dielectric layer and the fourth dielectric layer may undergo a planarization process that is performed until the top surfaces of the first, second, and third active patterns ACT1, ACT2, and ACT3are exposed, and thus may be respectively formed into the first dielectric pattern IP1and the second dielectric pattern IP2. The first device isolation structure101may be constituted by the first conductive pattern SP1, the first dielectric pattern IP1, and the second dielectric pattern IP2that are formed in the first trench TR1.

Referring toFIGS. 9, 10A, and 10B, on each of the pixel regions PR, a transfer transistor TX is formed on the first active pattern ACT1, a drive transistor DX and a select transistor SX are formed on the second active pattern ACT2, and a reset transistor RX is formed on the third active pattern ACT3.

For example, the formation of the transfer transistor TX may include implanting the first active pattern ACT1with impurities to form a floating diffusion region FD, and forming a transfer gate TG on the first active pattern ACT1. The formation of the drive transistor DX and the select transistor SX may include implanting the second active pattern ACT2with impurities to form an impurity region DR, and forming a drive gate SFG and a select gate SG on the second active pattern ACT2. The formation of the reset transistor RX may include implanting the third active pattern ACT3with impurities to form an impurity region DR, and forming a reset gate RG on the third active pattern ACT3.

A first interlayer dielectric layer221is formed on the first surface100aof the semiconductor substrate100. The first interlayer dielectric layer221may be formed to cover the transfer transistors TX and the logic transistors RX, SX, and DX formed on the first surface100aof the semiconductor substrate100.

Second and third interlayer dielectric layers222and223are sequentially formed on the first interlayer dielectric layer221. First and second connection lines212and213may be respectively formed in the second and third interlayer dielectric layers222and223. First contacts CT1may be formed to electrically connect the first and second connection lines212and213to the transfer transistors TX and the logic transistors RX, SX, and DX. At least one second contact CT2may be formed to electrically connect at least one first connection line212to the second conductive pattern SP2.

Referring back toFIGS. 3, 4A, and 4B, a planarization process is performed on the second surface100bof the semiconductor substrate100until the first conductive pattern SP1of the first device isolation structure101is exposed. The semiconductor substrate100may thus have reduced thickness. The first device isolation structure101may thus have a depth the same as a thickness of the semiconductor substrate100.

The pixel regions PR are implanted with impurities to form photoelectric conversion regions110on corresponding pixel regions PR. The photoelectric conversion regions110may have a second conductive type (e.g., n-type) different from the first conductive type (e.g., p-type).

A first planarized layer301may be formed on the second surface100bof the semiconductor substrate100. A conductive line CL is formed on an area around the second surface100bof the semiconductor substrate100. The conductive line CL is electrically connected to the first conductive pattern SP1of the first device isolation structure101.

Color filters303may be formed on the first planarized layer301. The color filters303may be formed on corresponding pixel regions PR. A second planarized layer305may be formed on the color filters303. Micro-lenses307may be formed on the second planarized layer305. The micro-lenses307may be formed on corresponding color filters303.

FIG. 11illustrates a plan view of an image sensor according to embodiments of the inventive concepts.FIGS. 12A and 12Billustrate cross-sectional views respectively taken along lines I-I′ and II-II′ ofFIG. 11. Regarding the embodiments ofFIGS. 11, 12A and 12B, detailed description of technical features repetitive to technical features described above with reference toFIGS. 3, 4A, and 4Bwill be omitted, and differences between the embodiments ofFIGS. 11, 12A and 12BandFIGS. 3, 4A and 4Bwill be described in detail.

Referring toFIGS. 11, 12A, and 12B, a third device isolation structure105is additionally provided on the first and second device isolation structures101and103. The third device isolation structure105may have a top surface coplanar with the first surface100aof the semiconductor substrate100.

Upper portions of the first and second device isolation structures101and103are recessed to define a third trench TR3. The third trench TR3is spaced apart from the first, second, and third active patterns ACT1, ACT2, and ACT3. The third trench TR3may have a depth less than that of the first trench TR1. The depth of the third trench TR3may be less than a depth of the second trench TR2. The third device isolation structure105may fill the third trench TR3. The third trench TR3may be at a portion of the second trench TR2. Accordingly, the third device isolation structure105may fill a portion of the second trench TR2.

The third device isolation structure105includes a third conductive pattern SP3and a fifth dielectric pattern IP5on the third conductive pattern SP3. The fifth dielectric pattern IP5may be adjacent to the first surface100a, and have a top surface coplanar with the first surface100a. For example, the fifth dielectric pattern IP5, the second dielectric pattern IP2, and the fourth dielectric pattern IP4may have top surfaces coplanar with each other.

The third conductive pattern SP3may include, for example, n-type doped polysilicon or p-type doped polysilicon. The fifth dielectric pattern IP5may include for example a silicon oxide layer, a silicon oxynitride layer, or a silicon nitride layer. In contrast to and different from the second device isolation structure103described with reference to ofFIGS. 3, 4A, and 4B, the second device isolation structure103according to the present embodiment ofFIGS. 11, 12A and 12Bdoes not include the second conductive pattern SP2. For example, according to the present embodiment, the second device isolation structure103includes the third dielectric pattern IP3and the fourth dielectric pattern IP4.

The third device isolation structure105has a first segment P1on the first device isolation structure101and a second segment P2on the second device isolation structure103. The first segment P1may be provided on a boundary between neighboring pixel regions PR. The first segment P1may be provided on the first device isolation structure101defining the boundary between the pixel regions PR. The first segment P1may vertically overlap the first device isolation structure101. When viewed in plan, the first segment P1may have a linear shape extending in the first direction D1.

The second segment P2is provided in the pixel region PR. The second segment P2may be provided on the second device isolation structure103in the pixel region PR. The second segment P2may vertically overlap at least a portion of the second device isolation structure103. When viewed in plan, the second segment P2may horizontally extend from the first segment P1onto the pixel region PR. The second segment P2may be positioned between the first, second, and third active patterns ACT1, ACT2, and ACT3.

The first segment P1may have a bottom surface in contact with the top surface of the first conductive pattern SP1of the first device isolation structure101. The third conductive pattern SP3of the first segment P1may be in contact with the first conductive pattern SP1of the first device isolation structure101. The second segment P2may have a bottom surface in contact with the third dielectric pattern IP3on the bottom surface of the second trench TR2. The third conductive pattern SP3of the second segment P2may be in contact with the third dielectric pattern IP3of the second device isolation structure103.

The third conductive pattern SP3of the first segment P1may be electrically connected to the first conductive pattern SP1of the first device isolation structure101. Because the third conductive pattern SP3of the second segment P2horizontally extends from the third conductive pattern SP3of the first segment P1, the third conductive pattern SP3of the second segment P2may also be electrically connected to the first conductive pattern SP1. The third dielectric pattern IP3of the second device isolation structure103may insulate the third conductive pattern SP3of the second segment P2from the semiconductor substrate100.

The first conductive pattern SP1of the first device isolation structure101may be supplied with a negative voltage through the conductive line CL. Because the third conductive pattern SP3is electrically connected to the first conductive pattern SP1, the third conductive pattern SP3may also be supplied with the negative voltage. The second device isolation structure103may be provided thereon with the third conductive pattern SP3on the pixel region PR. Accordingly, with the third conductive pattern SP3supplied with the negative voltage, positive charges generated around the second device isolation structure103may be eliminated by the third conductive pattern SP3.

FIGS. 13, 15, and 17illustrate plan views showing a method of fabricating an image sensor according to embodiments of the inventive concepts.FIGS. 14A, 16A, and 18Aillustrate cross-sectional views taken along line I-I′ ofFIGS. 13, 15, and 17, respectively.FIGS. 14B, 16B, and 18Billustrate cross-sectional views taken along line II-II′ ofFIGS. 13, 15, and 17, respectively. Regarding the embodiments ofFIGS. 13 to 18B, detailed description of technical features repetitive to technical features described with reference toFIGS. 5 to 10Bwill be omitted, and differences between the embodiments ofFIGS. 13 to 18BandFIGS. 5 to 10Bwill be described in detail.

Referring toFIGS. 13, 14A, and 14B, a second device isolation structure103is formed on the first surface100aof the semiconductor substrate100. For example, a third dielectric pattern IP3may be formed to partially fill a second trench TR2. A fourth dielectric pattern IP4may be formed on the third dielectric pattern IP3. In contrast to and different from the second device isolation structure103described with reference to ofFIGS. 5, 6A, and 6B, the second device isolation structure103according to the present embodiment does not include second conductive pattern SP2.

Referring toFIGS. 15, 16A, and 16B, a first device isolation structure101is formed on the first surface100aof the semiconductor substrate100. The formation of the first device isolation structure101may include forming a first dielectric pattern IP1, a first conductive pattern SP1, and a second dielectric pattern IP2in a first trench TR1. The formation of the first device isolation structure101according to the present embodiment may be substantially the same as that of the first device isolation structure101described with reference toFIGS. 7, 8A, and 8B.

Referring toFIGS. 17, 18A, and 18B, a third device isolation structure105is formed on the first surface100aof the semiconductor substrate100. For example, upper portions of the first and second device isolation structures101and103may be patterned to form a third trench TR3. The third trench TR3may penetrate the second dielectric pattern IP2of the first device isolation structure101and expose a top surface of the first conductive pattern SP1. The third trench TR3may expose the third dielectric pattern IP3of the second device isolation structure103. In the present embodiment, the third dielectric pattern IP3may include a silicon nitride layer, and thus may serve as an etch stopper when an etching process is performed to form the third trench TR3.

A third conductive pattern SP3is formed to partially fill the third trench TR3. The formation of the third conductive pattern SP3may include forming a third conductive layer filling the third trench TR3and performing an etch-back process on the third conductive layer. The third conductive pattern SP3may fill a lower portion of the third trench TR3. The third conductive pattern SP3may be formed to contact the top surface of the first conductive pattern SP1. The third conductive layer may include, for example, n-type doped polysilicon or p-type doped polysilicon.

A fifth dielectric pattern IP5is formed on the third conductive pattern SP3. The formation of the fifth dielectric pattern IP3may include forming a fifth dielectric layer filling an upper portion of the third trench TR3. The fifth dielectric layer may include, for example, a silicon oxide layer, a silicon oxynitride layer, or a silicon nitride layer. A planarization process may be performed on the fifth dielectric layer until the top surfaces of the first, second, and third active patterns ACT1, ACT2, and ACT3are exposed, which results in the formation of the fifth dielectric pattern IP5. The third device isolation structure105may be constituted by the third conductive pattern SP3and the fifth dielectric pattern IP5that are formed in the third trench TR3.

Subsequently, on each of the pixel regions PR, a transfer transistor TX is formed on the first active pattern ACT1, a drive transistor DX and a select transistor SX are formed on the second active pattern ACT2, and a reset transistor RX is formed on the third active pattern ACT3.

First, second, and third interlayer dielectric layers221,222, and223and first and second connection lines212and213may be formed on the first surface100aof the semiconductor substrate100. First contacts CT1may be formed to electrically connect the first and second connection lines212and213to the transfer transistors TX and the logic transistors RX, SX, and DX. In contrast to and different from the embodiments described with reference toFIGS. 9, 10A, and 10B, a second contact CT2is not formed.

Referring back toFIGS. 11, 12A, and 12B, the second surface100bof the semiconductor substrate100may undergo a planarization process to expose the first conductive pattern SP1of the first device isolation structure101. The pixel regions PR may be implanted with impurities to form photoelectric conversion regions110on corresponding pixel regions PR. Color filters303may be formed on corresponding pixel regions PR. Micro-lenses307may be formed on corresponding color filters303.

According to the inventive concepts, an image sensor may be configured to apply a negative voltage to a first conductive pattern in a first trench, and to a second conductive pattern in a second trench shallower than the first trench. As a result, positive charges generated from a pixel region may be eliminated and dark current characteristics improved.

Although the inventive concepts have been described in connection with some example embodiments illustrated in the accompanying drawings, it should be understood to those skilled in the art that various changes and modifications may be made without departing from the technical spirit and essential feature of the present inventive concepts. It should be apparent to those skilled in the art that various substitutions, modifications, and changes may be made to the described example embodiments without departing from the scope and spirit of the present inventive concepts.