Direct digital synthesizer, reference frequency generating device, and sine wave outputting method

A DDS achieved in size and cost reductions by removing a ROM for storing a table and the like and suppressing an operation amount is provided. A DDS includes an NCO, a DAC, and a BPF. The NCO outputs a sawtooth wave. The DAC converts either one of the sawtooth wave outputted from the NCO and a triangle wave signal converted by a waveform converting circuit based on the sawtooth wave, from a digital signal into an analog signal. The BPF receives the signal converted into the analog signal by the DAC and extracts a sine wave at a predetermined frequency from the inputted signal, by allowing a signal at a frequency within a fixed range to pass therethrough.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a U.S. National stage of International Application No. PCT/JP2012/081948 filed on Dec. 10, 2012. This application claims priority to Japanese Patent Application No. 2011-277498 filed on Dec. 19, 2011. The entire disclosure of Japanese Patent Application No. 2011-277498 is hereby incorporated herein by reference.

BACKGROUND

1. Field of the Invention

The present invention mainly relates to a direct digital synthesizer, which can output a sine wave at a predetermined frequency.

2. Background Information

Conventionally, as described inFIG. 8(a), DDSs (Direct Digital Synthesizers) each including an NCO (Numerically Controlled Oscillator), a ROM, and an LPF (Low-pass Filter), have been known.

The NCO outputs a sawtooth wave at a predetermined frequency. The ROM stores, as a table, output values (a phase of the sawtooth wave) from the NCO and an amplitude (displacement) of a sine wave which is set corresponding to the output values. By performing a conversion based on this table, the sawtooth wave can be converted into the sine wave. Then, this sine wave is outputted after a high frequency element thereof is removed by an LPF.

JP2005-045674A (Patent Document 1) includes an integration circuit having a similar configuration to the NCO, a multiplication circuit, and an error correcting unit. The multiplication circuit performs predetermined operation on a sawtooth wave, which is to be outputted from the multiplication circuit, to convert this sawtooth wave into a parabolic signal. The error correcting unit corrects the parabolic signal obtained from the multiplication circuit, based on an ideal sine waveform stored in a storage in advance. Thus, a sine wave can be formed.

SUMMARY

However, in a case where the DDS having the configuration illustrated inFIG. 8(a) uses an NCO with high resolution, the DDS needs to store multiple relations between the phase of the sawtooth wave and the displacement of the sine wave in order to sufficiently exert the performance of the NCO. In this case, a ROM with a large storing capacity is required, and therefore, the size of the ROM increases, which prevents downsizing of the device.

Moreover, the DDS disclosed in Patent Document 1 does not need to store the table described above; however, in order to output sine waves at a plurality of frequencies, it needs to store a plurality of ideal sine waveforms (or obtain them by operation). Therefore, it can be considered that this DDS will need a large ROM or the operation amount will increase. Moreover, in a case where an NCO with high resolution is used, the operation amount when converting the sawtooth wave into the parabolic signal increases, and therefore, using such an NCO may be CPU intensive.

The present invention is made in view of the above situations and it aims to provide a DDS achieved in size and cost reductions by removing a ROM for storing a table and the like and suppressing an operation amount.

Problems to be solved by the present invention are described above, and means for solving the problems and effects thereof will be described below.

According to a first aspect of the present invention, a direct digital synthesizer having the following configuration is provided. That is, the direct digital synthesizer includes a numerically controlled oscillator, a DAC, and a band-pass filter. The numerically controlled oscillator outputs a sawtooth wave. The DAC converts either one of the sawtooth wave outputted from the numerically controlled oscillator and a signal obtained based on the sawtooth wave, from a digital signal into an analog signal. The band-pass filter receives the signal converted into the analog signal by the DAC and extracts a sine wave at a predetermined frequency from the inputted signal, by allowing a signal at a frequency within a fixed range to pass therethrough.

Thus, the sine wave can be outputted without providing a ROM for storing the table, which has been used in the conventional DDS, and while suppressing an operation amount. Therefore, the DDS can be reduced in size, as well as the manufacturing cost. Moreover, by using different band-pass filters with different frequency bands (passing bands) to pass therethrough, not only the sine wave at the same frequency as the sawtooth wave, but also sine waves at various frequencies can be outputted.

The direct digital synthesizer described above preferably includes a waveform converting unit configured to convert the sawtooth wave outputted from the numerically controlled oscillator into a triangle wave.

Thus, since the triangle wave and the sine wave have similar waveforms, when the sine wave at the same frequency as the triangle wave is outputted, the sine wave can be outputted by effectively utilizing a triangle wave to serve as the base (without greatly dropping the signal intensity).

With the direct digital synthesizer described above, the waveform converting unit preferably includes a circuit configured to perform operation of an exclusive disjunction on a half cycle of the sawtooth wave to invert the sawtooth wave of the half cycle.

Thus, the sawtooth wave can be converted into the triangle wave with the simple configuration.

The direct digital synthesizer described above is preferably configured as follows. That is, the band-pass filter includes a plurality of band-pass filters aligned in parallel, the plurality of band-pass filters including a first band-pass filter and a second band-pass filter. Frequencies of the signals outputted from the first band-pass filter and the second band-pass filter are different from each other.

Thus, a plurality of signals at different frequencies can be generated simultaneously. Therefore, the direct digital synthesizer can flexibly respond to a change in a specification of an equipment to be connected thereto, a change in the number of the equipments, and the like.

According to a second aspect of the present invention, a reference frequency generating device having the following configuration is provided. That is, this reference frequency generating device includes the direct digital synthesizer of described above, and a phase comparing unit. The phase comparing unit compares phases of either one of the signal generated by the numerically controlled oscillator and a signal based thereon, and a reference signal, and outputs the comparison result. Moreover, the numerically controlled oscillator outputs the sawtooth wave based on the comparison result. At least one of the signal outputted from the band-pass filter and a signal based thereon is a reference frequency signal.

Since a PLL circuit is formed as above, the NCO can output the sawtooth wave synchronized with the reference signal. Therefore, a highly accurate reference frequency signal can be outputted.

The reference frequency generating device described above is preferably configured as follows. That is, the reference frequency generating device includes a subsequent phase synchronization circuit configured to use either one of the sine wave outputted from the band-pass filter and a signal based on this sine wave as the reference signal. The subsequent phase synchronization circuit includes a voltage controlled oscillator configured to output a signal synchronized with either one of the sine wave outputted from the band-pass filter and the signal based on this sine wave. The signal outputted from the voltage controlled oscillator is the reference frequency signal.

Thus, the PLL circuit (subsequent phase synchronization circuit) with the analog signal obtained after jitter which appears in a digital signal is removed is formed. Therefore, a stable reference frequency signal can be outputted.

According to a third aspect of the present invention, the following sine wave outputting method is provided. That is, this sine wave outputting method includes causing a numerically controlled oscillator to generate a sawtooth wave, converting either one of the sawtooth wave outputted from the numerically controlled oscillator and a signal obtained based on the sawtooth wave, from a digital signal into an analog signal, and extracting a sine wave at a predetermined frequency from the signal converted into the analog signal in the converting, by applying a band-pass filter configured to allow a signal at a frequency within a fixed range to pass therethrough.

Thus, by using different band-pass filters with different frequency bands (passing bands) to pass therethrough, not only the sine wave at the same frequency as the sawtooth wave, but also sine waves at various frequencies can be outputted. Moreover, the sine wave can be outputted without providing a ROM for storing the table, which has been used in the conventional DDS. Therefore, the DDS can be reduced in size, as well as the manufacturing cost.

DETAILED DESCRIPTION OF EMBODIMENTS

Next, an embodiment of the present invention is described.FIG. 1is a block diagram schematically illustrating a reference frequency generating device10according to the one embodiment of the present invention. The reference frequency generating device10is for providing a reference frequency signal to user-side equipment to which the reference frequency generating device is to be connected. Examples of targets to be supplied the reference frequency signal from the reference frequency generating device10include a base station of mobile phones, a transmitter station of terrestrial digital broadcasting, a WiMAX (Worldwide Interoperability for Microwave Access) communication facility, and the like.

The reference frequency generating device10of this embodiment includes a GPS receiver21, a PLL (Phase Locked Loop) circuit31, and a DDS (Direct Digital Synthesizer)32.

The GPS receiver21is connected with a GPS antenna11installed outside the reference frequency generating device10. The GPS receiver21performs positioning based on positioning signals received by this GPS antenna11to generate a reference signal (a pulse signal generated once every second). This reference signal is suitably corrected so as to accurately synchronize with one second of universal time coordinated (UTC).

Next, the PLL circuit31is described. As illustrated inFIG. 1, the PLL circuit31includes a phase comparator (phase comparing unit)22, a loop filter23, an NCO (numerically controlled oscillator)24, and a frequency divider25. This PLL circuit31compares phases of the reference signal outputted from the GPS receiver21and a signal obtained by dividing the frequency of a signal outputted from the NCO24, and adjusts the frequency of the signal outputted from the NCO24based on the comparison result. Hereinafter, the respective components configuring the PLL circuit31are described in detail.

The phase comparator22receives the reference signal and the signal obtained by dividing the frequency of the signal outputted from the NCO24. The phase comparator22compares the phases of these signals to obtain a phase difference therebetween, and outputs a signal (phase difference signal) based on the phase difference. This phase difference signal is outputted to the loop filter23.

The loop filter23is configured as a low-pass filter for cutting off a high frequency element and removing noise of the phase difference signal inputted from the phase comparator22. The phase difference signal after the cutoff of the high frequency element and the removal of the noise by the loop filter23is outputted to the NCO24.

The NCO24is a digitally controlled oscillator for outputting a signal to serve as a base of the reference frequency signal. The NCO24includes a register and an adder which are not illustrated. The NCO24outputs a signal of which an output value gradually increases and returns back to 0 at a predetermined cycle (sawtooth wave, seeFIG. 6(a) described later, for example) by the adder and the register. Note that, in the description hereinafter, the output value of the NCO24may be called particularly “a phase of the sawtooth wave,” focusing on a periodic change thereof.

Moreover, the phase difference signal is inputted to the NCO24from the loop filter23. Based on this phase difference signal, the NCO24generates the sawtooth wave so as to eliminate the phase difference between the reference signal and the signal obtained by dividing the frequency of the signal to be outputted from the NCO24. The sawtooth wave is outputted to a later-described waveform converting circuit (waveform converting unit)26provided in the DDS32, and the frequency divider25.

The frequency divider25divides the frequency of the signal outputted from the NCO24to convert it from a high frequency into a low frequency, and outputs the obtained signal (phase comparison signal) to the phase comparator22. For example, when the reference frequency signal is 10 MHz, the frequency divider25divides the frequency of this signal of 10 MHz at a frequency division ratio of 1/10,000,000 to generate the phase comparison signal of 1 Hz. Then this phase comparison signal is outputted as a timing signal from an output terminal to an external user-side system, as well as to the phase comparator22.

With the configuration described above, a loop of the PLL circuit31is formed. For example, a case is considered where the timing for the adder of the NCO24to perform integration is changed due to an aging variation, a temperature change in the surroundings and a supply voltage, etc. In this case, the phase of the sawtooth wave outputted from the NCO varies and a stable reference frequency signal cannot be outputted. However, the PLL circuit31digital-controls the NCO24based on an accurate 1PPS signal inputted from the GPS receiver21so that the variation of the phase of the sawtooth wave is eliminated. Therefore, even in the case where the timing for the adder to perform the integration is changed as described above, the accuracy of the reference frequency to be outputted from the reference frequency generating device10can be kept high.

Next, the DDS32is described. As illustrated inFIG. 1, the DDS32includes the NCO24, the waveform converting circuit26, a DAC (Digital to Analog Converter)27, and a BPF (Band-pass Filter)28. Note that, the NCO24is equipment that serves as a component of both of the PLL circuit31and the DDS32.

The waveform converting circuit26is a circuit for converting the sawtooth wave into a triangle wave by inverting a later-half cycle of the sawtooth wave generated by the NCO24. Hereinafter, this waveform converting circuit26is described in detail with reference toFIG. 2.FIG. 2shows views for describing how the sawtooth wave is converted into the triangle wave. Note that, to simplify the description, in the example ofFIG. 2, one cycle of the sawtooth wave is expressed with eight steps of output values; however normally, the sawtooth wave is expressed with a larger number of steps of data.

In the column of “before converted” in the table illustrated inFIG. 2(a), the change of the phase of the sawtooth wave outputted from the NCO24is described with three-bit binary digits. As illustrated in this table, it can be understood that the sawtooth wave indicates a waveform where the output value increases by one at a time (see the left-side chart inFIG. 2(b)). The waveform converting circuit26is a logic circuit which takes an exclusive disjunction of the later-half portion (d5to d8) of this sawtooth wave with “111.” By taking the exclusive disjunction, as described in the column of “after converted” on the right side inFIG. 2(a), the bits of the output values of the later-half portion are inverted.

As described above, a triangle wave of which the output value gradually increases in the earlier-half portion (d1to d4) and gradually reduces in the later-half portion (d5to d8) can be obtained (see the right-side chart inFIG. 2(b)). Note that, the waveform converting circuit26is not essential in the present invention, and a configuration in which the sawtooth wave outputted from the NCO24is directly outputted to the DAC27may be adopted. The triangle wave outputted from the waveform converting circuit26is outputted to the DAC27.

The DAC27converts the triangle wave inputted from the waveform converting circuit26, from a digital signal into an analog signal. The triangle wave converted into the analog signal by the DAC27is outputted to the BPF28.

The BPF28is a filter having a configuration that only allows signals in a predetermined frequency band (passing band) to pass therethrough but does not allow signals with other frequencies to pass therethrough. Moreover, a triangle wave is known to be a wave formed by superimposing a certain sine wave with odd overtones thereof. On the other hand, the sawtooth wave is known to be a wave formed by superimposing a certain sine wave with even and odd overtones thereof. Therefore, by applying the BPF28to either one of the triangle wave and the sawtooth wave inputted from the DAC27, a sine wave at a frequency around the passing band can be extracted. The sine wave at the predetermined frequency extracted by the BPF28is supplied to external equipment as the reference frequency signal via an output terminal.

Note that, by changing the BPF28, as illustrated in the charts ofFIG. 3, a sine wave at the same frequency as the sawtooth wave can be extracted (FIG. 3(a)), a sine wave at twice the frequency of the sawtooth wave can be extracted (FIG. 3(b)), and a sine wave at four-times the frequency of the sawtooth wave can be extracted (FIG. 3(c)). Similarly for the triangle wave, by changing the BPF28, a sine wave at the odd overtones can be extracted. As described above, by using the DDS of the present invention, the sine wave to which an integral multiple of the frequency of either one of the sawtooth wave and the triangle wave is set can be extracted.

As described above, the DDS32of this embodiment includes the NCO24, the DAC27, and the BPF28. The NCO24outputs the sawtooth wave (sawtooth wave generating process). The DAC27converts, from the digital signal into the analog signal, either one of the sawtooth wave outputted from the NCO24and the triangle wave signal converted by the waveform converting circuit26based on the sawtooth wave (analog converting process). The BPF28is inputted with the signal converted into the analog signal by the DAC27, and among the inputted signals, by allowing the signal at the frequency within a fixed range to pass therethrough, extracts the sine wave at the predetermined frequency (sine wave extracting process).

Thus, the sine wave can be outputted without providing a ROM for storing the table, which has been used in the conventional DDS, and while suppressing an operation amount. Therefore, the DDS can be reduced in size, and the manufacturing cost can be reduced. Moreover, by using different BPFs28at different frequency bands (passing bands) to pass therethrough, not only the sine wave at the same frequency as the sawtooth wave, but also sine waves at various frequencies can be outputted.

Next, a first modification is described with reference toFIG. 4.FIG. 4is a block diagram illustrating a configuration of a reference frequency generating device10according to the first modification. Note that, in the descriptions of the first modification, a second modification described later and the like, the same reference numerals are denoted in the drawings for the same or similar members to those in the embodiment described above, and the descriptions thereof may be omitted. Moreover, in the following modifications, differently to the above embodiment, a configuration in which the waveform converting circuit26is not provided is adopted (FIG. 8(c)); however, the configuration in which the waveform converting circuit26is provided (FIG. 8(b)), the same configuration to the above embodiment may be adopted as well.

A DDS33of the reference frequency generating device10of this modification has a configuration in which a plurality of BPFs28are aligned in parallel. Further, each BPF28has a different frequency band of the signal to pass therethrough. Therefore, in this DDS33, the frequency of the sine wave outputted from each BPF28can be different from each other.

With this configuration, a plurality of reference frequency signals at different frequencies can be generated simultaneously. Therefore, the reference frequency generating device10which can flexibly respond to a change in the specification of the equipment to be connected thereto, a change of the equipment itself, a change in the number of the equipments, and the like can be achieved.

Next, the second modification is described with reference toFIGS. 5 and 6.FIG. 5is a block diagram illustrating a configuration of a reference frequency generating device10according to the second modification.FIG. 6shows charts illustrating a difference between the digital signal and the analog signal.

The reference frequency generating device10of the second modification, in addition to the configuration of the above embodiment, includes a subsequent PLL circuit40using the sine wave outputted from the BPF28. This subsequent PLL circuit40includes a phase comparator42, a loop filter43, and a VCO (Voltage Controlled Oscillator)44.

The phase comparator42and the loop filter43have substantially similar configurations to the phase comparator22and the loop filter23described above. Moreover, the VCO44is an oscillator which can change the frequency to be outputted, depending on a voltage level to be applied externally.

In the second modification, as illustrated inFIG. 5, the sine wave outputted from the BPF28is outputted outside as a first reference frequency signal, as well as outputted to the phase comparator42. The phase comparator42compares the phases of the signal outputted from this BPF and the signal outputted from the VCO44and outputs the comparison result to the loop filter43.

The loop filter43converts the signals indicating the comparison result into a controlled voltage signal by averaging the voltage levels of the signals in terms of time. This controlled voltage signal is outputted to the VCO44.

The VCO44generates a signal at a frequency based on this controlled voltage signal. This signal is outputted outside as a second reference frequency signal, as well as outputted to the phase comparator42and the frequency divider25.

The phase comparator42uses the signal outputted from the VCO44to perform the phase comparison described above. The frequency divider25, similarly to the above embodiment, generates the phase comparison signal of 1 Hz by dividing the frequency of the signal outputted from the VCO44.

As above, in the second modification, the phase comparison using the digital signal outputted from the NCO24is not performed. In the second modification, the phase comparison using the analog signal outputted from the BPF28is performed by the phase comparator42, and the phase comparison using the signal obtained by dividing the frequency of the analog signal outputted from the VCO44is performed by the phase comparator22. By performing the phase comparisons using the analog signals, influence of jitter which is typical with a digital signal is eliminated, and therefore, highly accurate phase comparisons can be performed.

Hereinafter, the jitter which appears with a digital signal is described. Since the sawtooth wave generated by the NCO24is a digital signal, the waveform thereof is not exactly smooth. As illustrated inFIG. 6(a), the sawtooth wave has a stepwise waveform. Therefore, for example, the output value at the center of a first cycle of the sawtooth wave, and the output value at the center of a second cycle thereof may not indicate the same value and be different by one step. Such a variation of the signal is jitter. By the influence of this jitter, the accuracy of the synchronization control performed by the PLL circuit31slightly degrades.

On the other hand, with the signal outputted from the BPF28, since the stepwise sine wave is complemented by the DAC27to become an analog signal, as illustrated inFIG. 6(b), it has a smoothly curved waveform. Therefore, jitter which is typical with the digital signal described above does not occur. Therefore, by forming the subsequent PLL circuit40using the sine wave outputted from this BPF28, it can be prevented that the accuracy of the synchronization control degrades. This is similar with the signal outputted from the VCO44, which is an analog signal samely.

Next, a third modification is described with reference toFIG. 7.FIG. 7is a block diagram illustrating a configuration of a reference frequency generating device10according to the third modification.

In the third modification, a configuration in which a subsequent PLL circuit50is formed similarly to the second modification is adopted, and in the configuration, the sine wave outputted from the BPF28is outputted to the subsequent PLL circuit50after the frequency thereof is divided. Note that, the signal outputted from the BPF28may be outputted as the reference frequency signal as in the second modification, or may be not outputted as in the third modification.

The subsequent PLL circuit50includes a phase comparator52, a loop filter53, a VCO54, and a frequency divider55. Note that, since the respective components configuring the subsequent PLL circuit50have substantially the same configurations as the components with the same names described above, the descriptions thereof are omitted.

The phase comparator52compares the phases of the signal obtained by dividing the frequency of the signal outputted from the BPF28and the signal obtained by dividing the frequency of the signal outputted from the VCO54, and outputs the comparison result to the loop filter53.

The loop filter53converts the signal indicating the comparison result into a controlled voltage signal and outputs it to the VCO54.

The VCO54generates a signal at a frequency based on this controlled voltage signal. This signal is outputted outside as a reference frequency signal, as well as outputted to the frequency divider55.

The frequency divider55divides the frequency of the signal outputted from the VCO54and outputs the frequency-divided signal as a timing signal from an output terminal to external equipment, as well as to the phase comparator52. Note that, also in the third modification, since the subsequent PLL circuit50performs the phase comparison using the analog signal, the degradation in accuracy due to the jitter which is typical with the digital signal can be prevented.

Although the preferred embodiment and the modifications of the present invention are described above, the above configurations may be modified as follows.

The above embodiment and modifications have the configurations in which the reference signal is generated based on the signals from the GPS satellites; however, as long as it is a configuration using GNSS (Global Navigation Satellite System), the configuration may suitably be changed. For example, the configuration may be changed to what in which the reference signal is generated based on the signals from GLONASS satellites or GALILEO satellites. Further, a configuration in which the reference signal from an external device is acquired may be adopted.

The configuration may be changed to what in which the GPS receiver is disposed outside the reference frequency generating device10and the 1PPS signal (reference signal) is inputted externally. Moreover, the configuration may be changed to what in which the GPS receiver supplies a signal other than 1 Hz, such as PP2S instead of 1PPS, as the reference signal to the reference frequency generating device10.

The waveform converting circuit is not limited to the configuration described above using the exclusive disjunction, and may be achieved by a circuit with an arbitrary configuration. Moreover, a configuration may be adopted, in which a plurality of waveform converting circuits are provided, and a triangle wave for two cycles is obtained from a triangle wave for one cycle by inverting a portion of the triangle wave described above (central two portions when divided into four portions).

The respective components provided to the reference frequency generating device10, instead of being configured as hardware, may be comprised of software.