Analog interface structures and methods for digital displays

Structures and methods are provided for generating a digital display signal from an analog signal that is limited to 2N discrete analog levels and from a synchronization signal that defines spatial order for the digital display signal. These structures and methods accurately synchronize digitizers to the analog signal and they follow from a recognition that enhanced digitizer resolution will generate code patterns which easily distinguish between correct and incorrect sampling of the analog signals. Accordingly, the digitizers quantize the analog samples into an M-bit digital display signal wherein M exceeds N.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to digital displays and, more particularly, to interfaces that adapt analog display signals to digital displays.

2. Description of the Related Art

The cathode ray tube (CRT) has been the standard computer-display monitor for many years. Because CRTs have generally responded to analog display signals, there currently exists an extremely large installed base of computers (more than a billion) that incorporate digital-to-analog converters (DACs) configured to generate CRT analog display signals.

Recently, digital display devices (e.g., flat-panel displays, liquid crystal displays, projectors, digital television displays and near-to-eye displays) have become increasingly popular. Although it is anticipated that all-digital interfaces will eventually become the standard interface for these displays, analog interfaces must be available for the near future because of the large existing installation base of computers.

In response to the need for both analog and digital interfaces, an open industry group known as the Digital-Display Working Group (DDWG) has developed a digital-visual interface (DVI) specification which establishes analog and digital interface standards. In particular, these standards reference the Video Electronics Standards Association (VESA) specifications for the implementation of analog interfaces.

Analog-to-digital converters (ADCs) are typically used to adapt the analog display signals to a flat-panel display. The ADCs generally include high-speed samplers that provide analog samples which the ADCs then quantize into the desired digital display signals.

In order to assure accurate analog samples, the sample clock that actuates the samplers must be extremely stable (i.e., have low jitter) and be driven with extremely accurate clock signals. For example, a 640×480 pixel display with a typical refresh rate has a pixel processing period on the order of 40 nanoseconds but a large 1280×1024pixel display reduces the pixel processing period to 8–9 nanoseconds. Because rise and fall times and ringing further reduce the time that each pixel's analog state is valid, it is not surprising that control of ADC samplers has been a persistent problem in analog interface structures.

BRIEF SUMMARY OF THE INVENTION

The present invention is directed to structures and methods for generating an accurate digital display signal from an analog signal. They are realized with the recognition that digitizing an analog signal, which is limited to 2Ndiscrete analog levels, with M-bit digitizers, wherein M exceeds N, will generate code patterns that easily distinguish between correct and incorrect sampling of the analog signals.

DETAILED DESCRIPTION OF THE INVENTION

FIGS. 1 through 6illustrate structures and methods for generating a digital display signal from an analog signal that is limited to 2Ndiscrete analog levels and from a synchronization signal that defines spatial order for the digital display signal. These structures and methods accurately synchronize digitizers with the analog signal and they follow from a recognition that enhanced digitizer resolution will generate code patterns which easily distinguish between correct and incorrect sampling of the analog signals.

In particular,FIG. 1illustrates structure embodiments18of the present invention for coupling display signals from a pc graphics card20to a digital display system30. The graphics card20includes a graphics processor22, memory23and a signal converter24. The signal converter comprises a set of digital-to-analog converters (DACs)26and a sync signal generator28.

In operation of the graphics card20, the graphics processor22renders data from a computer's central processing unit (not shown) into a graphics-oriented format which it stores in the memory23. The DACs26are sometimes referred to as RAMDACs because they then convert elements of the stored formatted data directly from the memory23into analog display signals that each contain analog information (coded, for example, in 256 analog levels) sufficient to generate one of the red, green and blue components that form an analog image (e.g., on a CRT).

The sync signal generator28also responds to elements of the stored formatted data by generating synchronization signals that define spatial order for the analog display signals (i.e., the spatial order of display pixels). For example, these synchronization signals typically comprise a horizontal synchronization signal (hsync) that indicates the beginning of each display line and a vertical synchronization signal (vsync) that indicates the beginning of each frame of horizontal lines.

The digital display system30includes an analog interface32, a graphics controller34and a digital display36which may be, for example, a liquid crystal display panel. In operation, the analog interface receives the red, green and blue analog display signals and their corresponding synchronization signals from the pc graphics card20and converts them to digital display signals and a corresponding clock signal. In particular, the graphics controller34receives these signals from the analog interface and formats them into forms suitable for display of the LCD data on the digital display36.

In transit to the analog interface32, the phase relationship between the synchronization signals and the red, green and blue analog display signals is lost and this relationship must be reconstructed in the analog interface.FIG. 2illustrates an analog interface embodiment40which is particularly suited for the purpose of generating digital display signals that accurately recover this synchronization as they adapt the analog display signals to Digital display36ofFIG. 1.

In particular, the analog interface40includes, for each of red, green and blue analog display signals56, an analog-to-digital converter (ADC)42coupled between a clamp41and a data formatter43. It further includes a phase-locked loop (PLL)44, a pixel clock synthesizer46, a clock controller50and an associated memory48, a clamp generator52and an offset and gain adjuster54.

The PLL44provides a reference signal (REF) which it phase locks to the hsync signal that comes from the sync signal generator (28inFIG. 1). It is intended that graphics will be displayed on the digital display (36inFIG. 1) in a predetermined number of pixels (e.g., 1280) that are spaced across a predetermined number of lines (e.g., 1024) that form one complete graphics frame (the VSYNC signal ofFIG. 1is not shown in other figures as it is not relevant to the description).

Accordingly, the PLL includes a divider45that divides the reference signal so that it can be phase locked to the hsync signal. For example, if only the number of line pixels is considered and if the number is 1280, the divider45would be commanded to have a divisor of 1280 so that the ratio of the reference signal's frequency to the hsync signal's frequency would also be 1280. In practice, each line generally includes a blanking signal which must also be considered. In at least one exemplary super extended graphics array (SXGA) display, the divisor would be increased to something on the order of 1350 to accommodate the blanking signal. In another example, the video electronics standard association (VESA) defines a “reduced blanking” timing which permits more active pixels to be transmitted to a digital display at a given pixel frequency.

The pixel clock synthesizer46introduces a phase shift (e.g., a delay) to position the reference signal and thereby form a sample clock which drives wide-band samplers47in each of the ADCs42. In response to the red, green and blue analog display signals56and to the sample clock, the samplers provide analog samples which are then quantized by the converter portions of the ADCs42. Finally, the data formatters43convert the quantized signals into formats compatible with the graphics controller34.

In order to set the black level of the ADCs properly, the clamp generator provides information as to the location of the “back porch” which is located between each hsync signal and the first pixel of the line. At this point, the clamp generator52commands the clamps41to establish a predetermined clamp level (e.g., 0 volts) for each ADC. The offset and gain adjuster54can be used in a conventional manner to set the offset and gain of each ADC which essentially sets the brightness and contrast of the red, green and blue pixels on the digital display (36inFIG. 1).

As mentioned above, the phase relationship between the synchronization signals and the red, green and blue analog display signals is lost in transit to the analog interface40and must be reconstructed. As also mentioned above, the processing period for each pixel can be extremely limited (e.g., on the order of 8–9 nanoseconds) and the time extent of reliable pixel information is further limited by spurious signal parameters such as rise and fall times and ringing. Accordingly, setting the sample clock so that the samplers provide accurate analog samples to the converter sections of the ADCs42is a demanding task.

The invention recognizes that this task can be effectively accomplished by providing ADCs (42inFIG. 2) whose conversion resolution substantially exceeds the resolution of the DACs (26inFIG. 1) that generated the analog display signals. For example, if the DACs have a resolution of 8 bits, the ADCs may be configured with a resolution of 10 bits.

Thus, each DAC will provide 256 levels of analog signals but the ADCs will provide 1024 digital codes. This enhanced resolution is utilized by the clock controller50which monitors digital codes generated by at least one of the ADCs42and provides a frequency control signal to the divider45of the PLL44and a phase control signal to the pixel clock synthesizer46. The monitoring is facilitated by the clock controller's memory48which effectively forms “code bins” for storing a count of recent occurrences of the digital codes generated by one of the ADCs42. For 10-bit ADCs, an exemplary memory could be configured with 1024 locations that are each sufficient (e.g., 16 bits) to store a count of its respective digital code.

The operation of the high-resolution ADCs42, the PLL44, the pixel clock synthesizer46, the memory48and the clock controller50can be examined with reference toFIG. 3which illustrates transfer functions of the DACs26ofFIG. 1and the ADCs42ofFIG. 2and toFIGS. 4A–4Cwhich are expanded views of the area4ofFIG. 3. Although the following description is directed to adaptation of a selected one of the red, green and blue analog display signals ofFIGS. 1 and 2, its concepts apply to all.

The graph60ofFIG. 4A, for example, shows 8-bit digital codes along the vertical graph axis that are provided to a DAC26ofFIG. 1by the memory23. The heavy horizontal bars62indicate the corresponding analog signals (with reference to exemplary analog amplitudes in millivolts along the horizontal graph axis) that are generated by any of the DACs26. For example, the 8-bit digital code 0---01 corresponds to a converted analog signal of 16 millivolts.

The graph60also shows a stepped plot64which indicates the transfer function of any of the ADCs42ofFIG. 2in response to an analog signal along the graph's horizontal axis and the resulting ten-bit codes which are shown along the graph's vertical axis. The stepped plot64is centered on a broken line65which represents an analog-to-digital conversion which has no offset or gain errors (i.e., the offset and gain adjuster54ofFIG. 2has perfectly adjusted the ADCs).

In an exemplary use of the stepped transfer function64, the horizontal bar62A shows that an 8-bit digital code 0---01 into a DAC (26inFIG. 1) corresponds to an analog signal of 16 millivolts and the vertical line66intersects the transfer function64to illustrate that an input analog signal of 16 millivolts corresponds to a 10-bit digital code 0---0100 from any of the ADCs (42inFIG. 2). Similarly, the horizontal bar62B shows that an 8-bit digital code 0---10 corresponds to an analog signal of 32 millivolts and the vertical line68intersects the transfer function64to illustrate that an input analog signal of 32 millivolts corresponds to a 10-bit digital code 0---1000 from any of the ADCs.

FIG. 3illustrates the complete graph60from which a portion4has been expanded and shown inFIG. 4A. Some bits in the digital codes ofFIG. 4Ahave not been shown to conserve drawing space. An arrow67indicates the complete code for an exemplary one of the digital codes.

The 256 analog levels of the analog display signals of the 8-bit DACs26ofFIG. 1correspond to the digital data received from the memory23. The graph80ofFIG. 5Aillustrates an exemplary portion82of one of these analog display signals that defines various ones of these analog levels84which are connected by ramp segments86. The ramp segments are shown as straight lines for illustrative purposes but represent the portion of the analog display signal used up by spurious signal parameters (e.g., rise and fall times and ringing). The ramp segments substantially reduce the temporal extent of the analog levels84and, accordingly, the sample clock ofFIG. 2must be positioned with significant accuracy.

Arrows87inFIG. 5Aindicate pulses of a sample clock that is positioned so that the samplers47ofFIG. 2provide accurate analog signals to their respective ADCs42. With this sampling accuracy, the ADCs42will only generate those 10-bit digital codes ofFIG. 4Athat correspond to the horizontal bars62. Over some exemplary time span, the code bins in the memory48will therefore show various code counts that correspond to the horizontal bars62but none that correspond to the other 10-bit digital codes ofFIG. 4A.

InFIG. 4A, horizontal lines terminated by circles symbolize the code counts88in the memory48ofFIG. 2with the length of the line indicative of the number of codes in each code bin. The lengths are exemplary (as they correspond to the content of each image stored in the memory23ofFIG. 1) and are only intended to indicate that over an exemplary time span, generated digital codes will correspond to the horizontal bars62. The graph60ofFIG. 4Aindicates that the current phase control and frequency control signals from the clock controller50ofFIG. 2are proper—that is, the sample clock pulses (87inFIG. 5A) are correctly positioned to generate analog samples.

In contrast toFIG. 5A, the graph90ofFIG. 5Billustrates a situation in which the clock pulses87are positioned midway between the analog levels84so that the samplers (47inFIG. 2) sample the ramp segments86. Attention is directed to the clock pulse arrow87A and to a series of analog levels94that may occur just after this clock pulse (the particular levels will correspond to the data in the memory23ofFIG. 1). Although each of the analog levels94correspond to one of the horizontal bars62ofFIG. 4A, their respective ramp segments define various analog levels at the time of the clock pulse arrow87A that, in general, do not.

The analog samples provided by the samplers (47inFIG. 2) will no longer correspond to the end of one of the horizontal bars62ofFIG. 4Abut, rather, will be distributed along the horizontal axis ofFIG. 4B. These analog samples will then be quantized in accordance with the transfer function64ofFIG. 4Band, over an exemplary time span, be distributed among all of the 10-bit digital display signals of the vertical axis ofFIG. 4B.

This process is specifically shown in the graph100ofFIG. 4Bwhich is similar toFIG. 4A(with like elements indicated by like reference numbers) but does not show the horizontal bars62. Code counts98(in the code bins of the memory48ofFIG. 2) are now shown that, in general, correspond to all of the 10-bit digital display signals. Again, the actual code counts will vary with the data in the memory23ofFIG. 1.

The correct and incorrect timing of the sample clock pulses87inFIGS. 5A and 5Bthus respectively produce the code count arrangements ofFIGS. 4A and 4Bthat are easily distinguished because one (inFIG. 4A) corresponds only to the 8-bit digital signals along the vertical axis and the other (inFIG. 4B) corresponds to the 10-bit digital signals along the vertical axis. The difference in resolution thus provides code patterns which are easily distinguished. The clock controller50ofFIG. 2is configured to examine the code counts collected in its associated memory48and adjust the sample clock of the clock synthesizer46to obtain the code-count pattern ofFIG. 4Awhich has an absence of those 10-bit digital signals that do not correspond to one of the horizontal bars62.

In operation, the clock controller50adjusts the phase control signal that it sends to the pixel clock synthesizer46to enable phase shifts of the sample clock which will alter the code counts in the memory48. This process is continued until the clock controller50senses that the code counts correspond to the horizontal bars62ofFIG. 4A. The pixel clock synthesizer can be realized with any of various structures that provide selectable phase shifts. An exemplary synthesizer is a conventional delay-locked loop.

The graph60ofFIG. 4Ahas been idealized to facilitate the initial description of the analog interface40ofFIG. 2. Accordingly, the graph60ignores “real-life” effects (e.g., gain, offset and linearity errors in the ADCs42and general system noise) that will degrade the code counts88ofFIG. 4A. The result of these real-life effects is shown in the graph110ofFIG. 4Cwhich is similar toFIG. 4Awith like elements indicated by like reference numbers. In contrast, however,FIG. 4Cindicates that the code counts88ofFIG. 4Aare supplemented by code counts112that correspond to the other code counts98ofFIG. 4B. Correct timing of the sample clock pulses (as shown inFIG. 5A) will cause these latter code counts to be reduced. In practice, code counts that generally define an envelope114will be a clear indication of correct timing.

As described above, the reference signal from the PLL44should have a frequency that corresponds to the number of pixels that are to be displayed in each row on the digital display (36inFIG. 1) wherein this number is appropriately modified to account for any blanking signal. Accordingly, the divider45of the PLL44should be set to provide a divisor equal to the ratio of this frequency to the hsync signal's frequency. If the divider has, instead, a divisor that is off by one (either lower or higher), the clock pulse arrows87ofFIG. 5Awill cycle once between an accurate setting and an inaccurate setting during each horizontal row of pixels in the display of the digital display (36ofFIG. 1). If the divisor is off by n, then n such cycles will occur.

The clock controller50is configured to detect the cycles by examining the code bins of the memory48and, in response, to change the frequency control signal to cause an appropriate correction in the divider45. Although a divisor error of +1 will generate a code bin pattern substantially similar to that of a divisor error of −1, the clock controller can obtain the correct count by incrementing the count one way and then reversing the increment if that produces more cycles rather than reducing cycles. Once the frequency control signal has been adjusted to properly set the frequency of the reference signal, the phase control signal can then be set as previously described.

The processes described above are summarized in the flow chart120ofFIG. 6which is directed to a method of generating a digital display signal from an analog signal that is limited to 2Ndiscrete analog levels and from a synchronization signal that defines spatial order for the digital display signal. In a first process step122, N-bit analog display signals are provided (e.g., by the pc graphics card20ofFIG. 1) and a sample clock is provided (e.g., by the PLL44ofFIG. 2). As stated in process step124, the analog signal is sampled, in response to the sample clock, to provide analog samples. This step may be accomplished with the samplers47ofFIG. 2.

These analog samples are quantized in process step126to provide an M-bit digital display signal wherein M exceeds N. This step may be accomplished with the ADCs42ofFIG. 2. Finally, at least one of the frequency and phase of the sample clock is adjusted in process step128to substantially restrict the codes of the M-bit digital display signal to 2Ndifferent codes. This step may be accomplished with the clock controller50ofFIG. 2and its corresponding memory48.

Structures and methods have been provided to synchronize digitizers with incoming analog display signals. This has been accomplished with by described observation of signals from ADCs whose conversion resolution substantially exceeds the resolution of the DACs that generated the analog display signals. Although the invention has been illustrated with an ADC resolution that exceeds the DAC resolution by two bits, embodiments include structures and methods in which the an ADC resolution exceeds the DAC resolution by at least one bit.

The clock controller50ofFIG. 2can be realized with various conventional structures, e.g., at least one of an array of gates, an appropriately-programmed digital processor or a combination thereof.

The structures and methods of the invention have been described with reference to a synchronization signal that comprises the hsync signal ofFIGS. 1 and 2. Different pc graphics cards may provide different synchronization signals but these can be accommodated within corresponding embodiments of the invention.