QUANTUM DEVICE

A quantum device includes a chip including a superconducting circuit, a first wiring substrate, a second wiring substrate, first connection portions connecting the chip and a wiring layer on a first surface of the first wiring substrate and second connection portions connecting the second wiring substrate and a wiring layer on a second surface of the first wiring substrate, wherein one or more second connection portions arranged in a first row as viewed from the edge of the first substrate are provided at positions corresponding respectively to one or more of the first connection portions arranged in a first row as viewed from the edge and are arranged closer to the edge than the first connection portions arranged in the first row.

FIELD

Cross Reference to Related Applications

This application is based upon and claims the benefit of the priority of Japanese patent application No. 2022-046286, filed on Mar. 23, 2022, the disclosure of which is incorporated herein in its entirety by reference thereto.

This invention relates to a quantum device provided with a superconducting circuit.

BACKGROUND

A quantum chip provided with a superconducting circuit such as a superconducting quantum bit (qubit) and a coupler is formed on a substrate (e.g., silicon substrate) using a semiconductor micro-fabrication process. For pitch narrowing of connection terminals (electrodes) and wiring miniaturization of the quantum chip, the quantum chip is connected to a first wiring substrate (interposer) which performs pitch conversion and wiring routing.

With an increase in the number of connection terminals due to an increase in the number of qubits included in the quantum chip, a connection terminal arranged on a surface facing the quantum chip is connected via a through via to a connection terminal arranged on an opposite side surface of the quantum chip, a signal is transmitted and received from the connection terminal provided on the opposite side surface. In the first wiring substrate (interposer), wiring is formed on a silicon substrate, which is similar to the substrate of a quantum chip. The quantum chip is flip-chip mounted on the first wiring substrate (interposer), with a circuit surface on which qubits are formed, faced down.

In the first wiring substrate (interposer), such a configuration in which a dielectric other than a silicon is placed and a material other than a superconducting material is exposed on a first surface facing the circuit surface of the quantum chip is usually not adopted to prevent degradation of a qubit's transmission characteristic. Therefore, a wiring accommodation ratio of the first wiring substrate (interposer) cannot be increased.

In order to increase a wiring accommodation ratio, for example, a configuration is used in which a plurality of wiring substrates are stacked. In this case, connection terminals on a surface of the first wiring substrate (interposer), opposite to a surface facing to a quantum chip, are directly connected to connection terminals on a first surface of a second wiring substrate (also called a package substrate), facing to the first wiring substrate, where connection to external circuit(s) is made from the connection terminals on a second surface of the second wiring substrate which is opposite to the first surface. As the second wiring substrate, a resin-based multilayer substrate may be used.

In a three-dimensional mounting package composed of a plurality of wiring substrates, where the package includes a quantum chip and an interposer, as a substrate such as the interposer becomes thinner, warping or other deformation of the substrate impairs connection reliability. The warping of the substrate is also caused by a thermal stress due to a difference (mismatch) in coefficients of thermal expansion (coefficient of linear expansion) between materials subjected to thermal history.

Underfill is used to increase a mounting strength (mechanical strength) of a wiring substrate on which a semiconductor chip is flip-chip mounted. An underfill material (e.g., epoxy resin, urethane resin, silicon resin, polyester resin, acrylic resin, etc.) is filled in a gap between the semiconductor chip and the first wiring substrate (interposer) and a gap between the first wiring substrate (interposer) and the second wiring substrate, for stress relaxation (Patent Literature (PTL) 1). However, it is known that circuit characteristics deteriorate in several to several tens of GHz (Gigahertz) band, for example, due to an effect of an underfill material which is an insulating adhesive material used to fix and seal the second wiring substrate and first wiring substrate (interposer). In addition, as described above, an underfill material is not used in the superconducting quantum circuit to avoid characteristic degradation (loss) due to a dielectric. Furthermore, in terms of thermal shrinkage, an underfill material is not used in consideration of occurrence of a warping and/or a stress strain thereof.[PTL 1] International Publication No. WO2020/122014

SUMMARY

It is an object of the present disclosure to provide a quantum device enabled to suppress deformation or the like of a wiring substrate to improve connection reliability.

According to the present disclosure, a quantum device includes:

a chip including a substrate and a wiring layer made of superconducting material on the substrate;

a first wiring substrate including a first substrate, a first wiring layer including a plurality of wirings formed on a first surface of the first substrate, a second wiring layer formed on a second surface opposite the first surface of the first substrate; and a plurality of through vias penetrating the first substrate and electrically connecting the plurality of wirings on the first wiring layer and a plurality of wirings on the second wiring layer;

a second wiring substrate including a second substrate, and a third wiring layer formed on a first surface of the second substrate;

a plurality of first connection portions that electrically connect a plurality of wirings on the wiring layer of the chip and the plurality of wirings of the first wiring layer on the first surface of the first wiring substrate arranged opposed to the chip; and

a plurality of second connection portions that electrically connect the plurality of wirings of the second wiring layer on the second surface of the first wiring substrate and the plurality of wirings of the third wiring layer on the first surface of the second wiring substrate arranged opposed to the second surface of the first wiring substrate.

In the first wiring substrate, the plurality of the second connection portions on the second surface arranged in a first row as viewed from an edge of the first substrate, include one or more second connection portions provided at positions that correspond respectively to one or more of the first connection portions on the first surface arranged in a first row as viewed from the edge of the first substrate and that are closer to the edge than the first connection portions on the first surface arranged in the first row.

According to the present disclosure, it is possible to provide a quantum device that suppresses deformation or the like. of a wiring substrate to improves connection reliability. Still other features and advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description in conjunction with the accompanying drawings where only exemplary embodiments of the invention are shown and described, simply by way of illustration of the best mode contemplated of carrying out this invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawing and description are to be regarded as illustrative in nature, and not as restrictive.

EXAMPLE EMBODIMENTS

In a three-dimensionally mounted quantum device package provided with a plurality of wiring substrates in which a quantum chip and an interposer are included, as the substrate such as the interposer becomes thinner, a warping and/or other deformation of the substrate may deteriorate connection reliability.

Underfill cannot be used in a quantum device. Therefore, a new measure (structure or architecture) is desired to be introduced to suppress a warping and/or other deformation of a substrate due to thermal shrinkage and other factors in a three-dimensionally mounted quantum device package. According to the present disclosure, a quantum device is enabled to suppress deformation or the like. of a wiring substrate to improves connection reliability.

The following describes example embodiments of the present disclosure.FIG.1illustrates a quantum device1in one of example embodiments. As illustrated inFIG.1, the quantum device1is provided with a quantum chip10, a first wiring substrate (interposer substrate)20, and a second wiring substrate30.

The quantum chip10includes a wiring layer, not illustrated in which a superconducting quantum circuit is formed, on a first surface (circuit surface) of a substrate11. The quantum chip10is flip-chip mounted on the first wiring substrate20with the first surface faced down. As a non-limiting example, the quantum chip10may include a qubit using Josephson junctions (e.g., a Josephson parametric oscillator) as a superconducting quantum circuit.

A wiring on the first surface (circuit surface) of the substrate11of the quantum chip10and a wiring on a wiring layer on a first surface of the first wiring substrate20facing the quantum chip10is directly connected (bonded) with a first connection portion41. The first connection portion41is preferably made with a bump electrode (metal bump).

A substrate21of the first wiring substrate20is preferably made of the same material as the substrate11of the quantum chip10, in consideration of a linear expansion coefficient and so on.

In a case where the substrate11of the quantum chip10is a silicon substrate, for example, the substrate21of the first wiring substrate20preferably is made of silicon. In this case, the first wiring substrate20is also called a silicon interposer substrate. A wiring layer12of the substrate11of the quantum chip10is manufactured by a semiconductor process (semiconductor micro-fabrication process). The wiring layer of the first wiring substrate20(silicon interposer substrate) may also be manufactured by the semiconductor process. In this case, a through via (Through Silicon Via: TSV), which connects a first wiring layer and a second wiring layer of the first wiring substrate penetrating the substrate11, is also manufactured by the semiconductor process, where the first wiring layer is the wiring layer on the surface of the first wiring substrate20facing the quantum chip and the second wiring layer is a wiring layer on an opposite side of the first wiring layer.

The first connection portion (bump electrode)41may be manufactured by a semiconductor process (metal film deposition and pattern formation). The first connection portion (bump electrode)41may be made of a normal conductor such as copper (Cu) or an insulator (SiO2, silicon nitride film, silicon oxynitride film, etc.) surface-coated with a superconducting film.

The second wiring substrate30is directly connected to a wiring on a back surface of the first wiring substrate20(a second surface opposite to the first surface facing the quantum chip10) with a second connection portion42. The second connection portion42is preferably made with a bump electrode (metal bump).

The second wiring substrate30is suitably configured to have a size (area) and thickness each larger than that of the first wiring substrate20, for pitch conversion, wiring routing, etc., though not limited thereto. The second wiring substrate30may be configured with a multilayer silicon interposer substrate with insulation and conductor layers alternatingly provided on both sides of a core material, a resin-based multilayer substrate, a ceramic substrate, a tape substrate or the like. The second wiring substrate30is also called a package substrate or an interposer substrate (second interposer substrate). The second surface of the second wiring substrate30, opposite to the first surface facing the first wiring substrate20, may be provided with a connection terminal(s) to connect to a wiring on the first surface with a through via etc.

According to the present example embodiment, in the first wiring substrate20, on a surface (second surface) of an opposite side of a surface (first surface) facing the quantum chip10, among the plurality of second connection portions (bump electrodes)42arranged in a first row on the second surface as viewed from an edge of the substrate21, one or more second connection portions (bump electrodes)42are arranged at one or more positions on the second surface which correspond to one or more of the first connection portions (bump electrodes)41arranged in a first row on the first surface as viewed from an edge of the substrate21, respectively, and which are closer to the edge than the corresponding one or more positions of the first connection portions (bump electrodes)41arranged in the first row on the first surface. The configuration of the plurality of the second connection portions (bump electrodes)42in the first row as viewed from the edge of the substrate21is not limited to one in which the second connection portions are aligned and arranged in the same line along the X-axis or Y-axis direction ofFIG.1on the second surface of the substrate21. The configuration of the second connection portions (bump electrodes)42may include one in which the second connection portions are not aligned on the same line, but each of the second connection portions is positioned first (closest to the edge) as viewed from the edge of the substrate21. The same may be said to the first connection portions (bump electrodes)41arranged in the first row on the first surface as viewed from the edge of the substrate21.

As illustrated inFIG.1, there is no encapsulant (insulating adhesive material) such as an underfill material between the quantum chip10and the first wiring substrate20and between the first wiring substrate20and the second wiring substrate30. In a vacuum-evacuated refrigerator, a gap between the quantum chip10and the first wiring substrate20and a gap between the first wiring substrate20and the second wiring substrate30are each in a vacuum.

Only for the sake of simplicity of the drawing, inFIG.1, a height of the first connection portion (bump electrode)41is illustrated as larger than a thickness of the quantum chip10and the first wiring substrate20. As a non-limiting example, the thickness of the quantum chip10(silicon chip) and that of the first wiring substrate20(silicon interposer substrate) are about 30 to several hundred μm (micrometer) (30 μm or more), for example, and the height of the first connection portion (bump electrode)41is, for example, about 1 to several 10 μm (1 μm or more).

InFIG.1, the number of the first wiring substrate20mounted on the second wiring substrate30is one, but a plural number of the first wiring substrates20may, as a matter of course, be mounted on the second wiring substrate30.

FIG.2illustrates a schematic side end view of the quantum device1illustrated inFIG.1, viewed from an x-axis direction. A wiring layer12formed on the substrate11of the quantum chip10is made of a superconducting material, such as Niobium (Nb). The superconducting material is not limited to niobium (Nb). Niobium nitride, aluminum (Al), indium (In), lead (Pb), tin (Sn), rhenium (Re), palladium (Pd), titanium (Ti), tantalum (Ta), tantalum nitride, or an alloy including at least any one of those aforementioned. The first connection portion41and the second connection portion42, each of which is configured by a bump electrode (metal bump), will be referred to as a first bump electrode41and a second bump electrode42, respectively in the following.

The wiring layer12formed on the first surface of the substrate11of the quantum chip10may include a non-linear element such as Josephson junction and an inductor (L) in a LC resonant circuit of a superconducting quantum circuit.

A first wiring layer22on a first surface of the first wiring substrate20facing the first surface (the wiring layer12) of the quantum chip10may be made of a superconducting material. A part of the superconducting quantum circuit of the quantum chip10may also be formed in the first wiring layer22of the first wiring substrate20. For example, a capacitor (C) of the LC resonant circuit of the superconducting quantum circuit may include a first electrode and a second electrode, where the first electrode is formed on the wiring layer12of the quantum chip10, and the second electrode facing the first electrode may be formed on the first wiring layer22of the first wiring substrate20.

The first bump electrode41may be fabricated on the first wiring layer22when manufacturing the first wiring substrate20. In this case, the first bump electrode41may be bonded to a pad (connection terminal) of the wiring layer12of the quantum chip10by direct bonding through surface activation, ultrasonically bonding, or solder (superconducting solder) bonding. Alternatively, thermal compression bonding (TCB) or the like may be applied. Bonding of the first bump electrode41is preferably carried out before bonding of the second bump electrode42.

Alternatively, the first bump electrode41may be fabricated on the wiring layer12when manufacturing the quantum chip10. In this case, the first bump electrode41may be bonded to a pad in the first wiring layer22of the first wiring substrate20by direct bonding through surface activation, ultrasonically bonded, or solder (superconducting solder) bonding. Alternatively, thermal compression bonding or the like may be applied.

A diameter (crimp diameter) of the first bump electrodes41may be about several μm to several 10 μm, for example, 5 μm to 10 μm. A distance between centers of the first bump electrodes41(bump pitch) is also approximately equal to or greater than the diameter of the first bump electrode41.

A second wiring layer23on the second surface of the first wiring substrate20facing the second wiring substrate30, is connected to the first bump electrode41by a through via (not shown). InFIG.2, the second wiring layer23is illustrated as a wiring layer extending from one end to another end of the substrate21. The second wiring layer23includes via pads, a planner chape thereof being a circle or rectangle) of the through vias (not shown). The second wiring layer23may be made of a superconducting material or a non-superconducting material. For example, the second wiring layer23may have a surface coated with gold (Au), platinum (Pt), palladium (Pd), or the like.

The second wiring substrate30may be a multilayer substrate. A third wiring layer32of the second wiring substrate30facing the first wiring substrate20may be made of a non-superconducting material. A diameter of the second bump electrode42may be, for example, about 50 μm to 100 μm. The second bump electrode42may be formed on the second wiring layer23of the first wiring substrate20. In this case, the second bump electrodes40are bonded on a wiring pad of the third wiring layer32of the second wiring substrate30by, for example, surface activation, ultrasonic waves, solder, or crimping.

A fourth wiring layer33of the second wiring substrate30may be made of a non-superconducting material. Of the fourth wiring layer33, a signal wiring (e.g., readout line, control line, etc.) may be taken out from the refrigerator and connected, for example, to a measurement device installed in a room temperature area. The measurement device includes for example, a readout circuit or a current control circuit that supplies current to generate a magnetic flux to penetrate through the SQUID (superconducting quantum interference device) loop of a qubit.

In the substrate21of the first wiring substrate20, one or more second bump electrodes42arranged in the first row (or the first one) as viewed from an edge of the second surface where the second wiring layer23is formed, are arranged corresponding to one or more first bump electrodes41arranged in the first row (or the first one) as viewed from an edge of the first surface where the first wiring layer22is formed. The one or more second bump electrodes42are arranged at positions each closer to the edge than that of each of the one or more corresponding first bump electrodes41.

FIG.3Ais a schematic plan view of the first wiring layer22of the first wiring substrate20illustrated inFIG.2.FIG.3Aschematically illustrates a part of area bumps where the first bump electrodes41are arranged in an area-array on a surface of the quantum chip10to be mounted by the flip-chip method. The first bump electrodes41, which are connected to pads around the periphery of the quantum chip10, are schematically illustrated on the first wiring layer22of the first wiring substrate20. The second bump electrodes42(illustrated as a gray circle with a dashed line border) on the second wiring layer23(seeFIG.2) are arranged in the first row as viewed from an edge of the second surface where the second wiring layer23and are located at an outer peripheral side as compared with corresponding ones of the first bump electrodes41which are arranged in the first row as viewed from an edge of the first surface where the first wiring layer22is formed. InFIG.3A, only the second bump electrodes42arranged on the most outer side of the second wiring layer23are illustrated and other second bump electrodes42(not shown) may be arranged inside the corresponding first bump electrodes41. A placement pattern of the first bump electrodes41inside the periphery is arbitrary, and for this reason they are omitted inFIG.3A.

FIG.3Billustrates a positioning of the first bump electrodes41and the second bump electrodes42.FIG.3Bschematically illustrates the positioning of one first bump electrode41and one second bump electrode42in the lower left corner (corner) of the first wiring layer22inFIG.3A. As illustrated inFIG.3B, a distance d1is, for example, 0.2 times greater than a distance d2(d1>=0.2×d2). The distance d1is a distance between the outermost positions of the second bump electrode42and the first bump electrode41when the second bump electrode42is projected on the same plane on which the first bump electrode41is located. The distance d2is a distance between the center position of the first bump electrode41and the outermost position of the first bump electrode41. In the example illustrated inFIG.3B, the first bump electrode41is of a cylindrical form (with a cross section being a circle), and d2is the radius of the first bump electrode41. Preferably, d1>=(⅓)×d2, or d1>=0.4×d2.

In the substrate21of the first wiring substrate20, a plurality of second bump electrodes42, each of which is arranged in the first row as viewed from each of the four sides (edges) of the second surface where the second wiring layer23is formed, are arranged at positions closer to the end side than corresponding one of a plurality of first bump electrodes41arranged in the first row as viewed from each of the four sides (edges) of the first surface where the first wiring layer22is formed. With this configuration, the first connection portions41are arranged within a deformation suppression region defined by the second connection portions42that connect the first wiring substrate20and the second wiring substrate30. Thus, deformation such as warping of the first wiring substrate20due to cooling to a cryogenic temperature can be suppressed. That is, according to the present example embodiment, in a configuration where there is not provided any underfill material or the like between the quantum chip10and the first wiring substrate20and between the first wiring substrate20and the second wiring substrate30, it is possible to suppress deformation of the first wiring substrate and avoid a breakage of each connection portion, thereby improving a connection reliability between the first wiring substrate20and the second wiring substrate30.

FIGS.4A to4Care schematic plan views of the first wiring layer22of the first wiring substrate20illustrated inFIG.2.FIGS.4A to4Cexamples of variations in the arrangement of the second bump electrodes42illustrated inFIG.3. In the example illustrated inFIG.4A, in the substrate21of the first wiring substrate20, each second bump electrode42A (gray circle with dashed line border) located in the first position as viewed from an edge of each of four corners of the second surface where the second wiring layer23is formed, is arranged closer to the edge of each of the four corners than each corresponding one of the first bump electrodes41A located in the first position as viewed from the edge of each of the four corners of the first surface of the where the first wiring layer22is formed.

In the example illustrated inFIG.4B, in the substrate21of the first wiring substrate20, the second bump electrodes42A and at least one second bump electrode out of second bump electrodes42B and42C neighboring to the second bump electrode42A are respectively arranged closer to the edge side than the corresponding first bump electrode41A and at least one first bump electrode out of the first bump electrodes41B and41C neighboring to the first bump electrode41A. The second bump electrode42A is positioned first as viewed from an edge of each of four corners of the second surface where the second wiring layer23is formed, and the first bump electrode41A is positioned first as viewed from an edge of each of the four corners of the first surface where the first wiring layer22is formed.

In the example illustrated inFIG.4C, in the substrate21of the first wiring substrate20, the second bump electrodes42A arranged at a corner, and at least one second bump electrode out of second bump electrodes42D,42E, and42F each arranged in a center portion of a side between the two opposing corners are arranged closer to the edge side than the corresponding first bump electrode41A arranged at the corner, and at least one first bump electrode out of first bump electrodes41D,41E, and41F each arranged in a center portion of a side between the two opposing corners, respectively. The second bump electrode42A is positioned first as viewed from an edge of each of four corners of the second surface where the second wiring layer23is formed, and the first bump electrodes41is positioned first as viewed from the edge of each of the four corners of the first surface where the first wiring layer22is formed.

For each corner, a length of all of a plurality of the second bump electrodes42each positioned closer to an end side than a corresponding one of the first bump electrodes41, which is given by (a diameter of the second bump electrode42+a pitch between the second bump electrodes42)×(the number of the second bump electrode42positioned closer to the end side than the first bump electrodes41) may be about ⅓ or less, or ⅕ or less, of a length of all of the second bump electrodes42arranged along each side of the second surface where the second wiring layer23is formed.

Also, on each side of the second surface where the second wiring layer23, a length of all of a plurality of the second bump electrodes42arranged in the center portion of the side and arranged closer to the end side than the first bump electrodes41, which is given by (a diameter of the second bump electrode42+a pitch between the second bump electrodes42)×(the number of the second bump electrode42in the center portion of the side and arranged closer to the end side than the first bump electrodes41) may be about ⅓ or less, or ⅕ or less, of a length of all of the second bump electrodes42arranged on one side.

FIG.5Aillustrate schematically a cross section of the first wiring substrate20illustrated inFIG.2. A wiring (pad) of the first wiring layer22on the first surface of the first wiring substrate20and a wiring (pad) of the second wiring layer23on the second surface are connected by a through via (through-substrate via)24formed in the substrate21.

When the substrate21is a silicon substrate, the through via24is also called TSV (through-silicon via) penetrating the silicon die (silicon wafer). The through via24is formed by drilling a hole in the wafer and filling a conductive material in the hole to form a through electrode. The conductive material filled in an inner wall of the hole of the through vias24can be either a superconducting material or a non-superconducting material (Cu, Ni, Au, Pt, etc.). The through via24may be formed on a first surface (front surface) of the wafer before the first wiring layer22is formed (via first), or formed from the first surface or a second surface (back surface) of the wafer after the first wiring layer22is formed (via last).

InFIG.5A, dashed circles on both sides of the substrate11represent a substrate configuration such that exposure of anything other than a superconducting material on a first surface of the substrate11of the quantum chip10(exposure of the first surface of the substrate11) may be avoided as much as possible. That is, a wiring pattern of the first wiring layer22covers up to an end portion (edge) of the substrate21. On the first surface of the substrate11, in the wiring pattern of the first wiring layer22includes a ground pattern (plane) arranged to surround both sides of a signal line waveguide. Therefore, the first surface of substrate11is configured such that a wide area (region) thereof is not exposed.

In order to reduce warpage of the substrate21, the first and second surfaces are provided with the same number of wiring layers (first and second wiring layers22and23) thereon. If warpage can be controlled by a layout and thickness of the wiring layers, the wiring layer23facing to the second wiring substrate30may be configured as multiple layers.

In an example illustrated inFIG.5A, in first wiring substrate20, the second wiring layer23includes a via pad of the through via24, i.e., a pad electrode (connection terminal) directly below the through via24.

Regarding the second connection portions (second bump electrode)42, for example, as illustrated inFIG.5B, in the first wiring substrate20, a second connection portion (second bump electrode)42a, which is located at the outermost periphery of the second connection portions42connected to the wiring of the wiring layer31of the second wiring substrate30may be shifted outward from a position of a first connection portion (first bump electrode)41a, which is connected via a through via24a. In this case, a planar shape of a via pad23a(wiring) directly below the through via24amay have a shape that extends outward from a center of the through via24a, and a positioning of the first and second connection portions (first and second bumps)41and42may have a positioning relationship as illustrated inFIG.3B. Alternatively, the outermost second connection portion (second bump electrode)42amay be configured such that a position of the first connection portion (first bump electrode)41awhich is located in a center of the via pad23aof the through via24aand connected via the through via24a, is located inside the outermost positioned second connection portion (second bump electrode).

In a case where in the first wiring substrate20, a connection is made with the wiring of the wiring layer32of the second wiring substrate30, and the second connection portion (second bump electrode)42connecting to the first surface of the connection portion (first bump electrode)41via the through via24is connected directly under the through via24, a signal connection is made at a shortest distance, though not limited thereto. For example, as illustrated inFIG.5C, on the second surface of the substrate21of the first wiring substrate20, a via pad23bof a through via24bmay be wire routed to a pad electrode (connection terminal)23c, and the second connection portion (second bump electrode)42blocated at the outermost periphery of the second connection portions (second bump electrodes)42may be bonded to the pad electrode23c. The via pad23bis located inside, extending inward, from an edge of the substrate21. The pad electrode23cis located at the outermost position separated from the position of the through via24b. In this case, the second connection portion (second bump electrode)42bis located outside of an outermost first connection portion (first bump electrode)41a. A wiring routing and a pad electrode may be formed by patterning the through via24with a process such as forming it from the second surface of the substrate21.

FIG.6schematically illustrates a cross section of the second wiring substrate30illustrated inFIG.2. As illustrated inFIG.6, the second wiring substrate30is configured as a 6-layer multilayer substrate with a configuration, in which, a conductor324, an insulation layer313, a conductor322, an insulation layer312, and a conductor of the third wiring layer32are stacked on a first surface of a core material311, the third wiring layer32and the conductor322are connected with a via321, the conductor322and the conductor324are connected with a via323, a conductor334, an insulation layer314, a conductor332, an insulation layer315, a conductor of a fourth wiring layer33are stacked on a second surface opposite to the first surface of the core material311, the conductor of the fourth wiring layer33and the conductor332are connected with a via331, the conductor332and the conductor334are connected with a via333, and the conductor324, the conductor334are connected with a through via316penetrating the core material311. The core material311is made of a silicon substrate to have the same linear thermal expansion coefficient as the substrate11of the quantum chip10. and the substrate21of the first wiring substrate20. In this case, the through via316is configured with a TSV. Configurations of a wiring layer and an insulation layer on both sides of the core material311is the same to suppress warpage of the substrate. Conductors to be built up may be, for example, copper (Cu) or aluminum, etc. Silicon oxide, silicon nitride, silicon oxynitride, polyimide resin, acrylic resin, epoxy resin, fluorine resin (Poly Tetra Fluoro Etylene (PTFE)), or the like may be used as insulation layers.

FIG.7AtoFIG.7Cschematically illustrate a comparative example and an example embodiment.FIG.7Aschematically illustrate a configuration of the comparative example. In the first wiring substrate20, regarding the first bump electrode41that connect to the quantum chip10, there are first bump electrodes41, which are located outside of the deformation suppression region defined as an inside region encircled by the second bump electrodes42arranged closest to the edge (outmost) of the substrate21.

Since the quantum chip10and the substrates11and21of the first wiring substrate20are each made of a silicon substrate, coefficients of linear thermal expansion of the quantum chip10and the substrates11and21of the first wiring substrate20are the same when cooled to the cryogenic temperature. In the substrate21of the first wiring substrate20, in a region inside the second bump electrodes42(deformation suppression region) arranged outmost, deformation with large curvature is suppressed due to a constraining force from the second bump electrode42.

On the other hand, in an area outside the deformation suppression region in the substrate21of the first wiring substrate20, ranging from the second bump electrodes42arranged closest to the edge (outmost) of the substrate21to the edge of the substrate21is an unbounded free end, in which unlike inside the deformation suppression region, a large curvature deformation (warpage) may occur, as shown schematically inFIG.7B. An amount of substrate warpage is known to depend on Young's modulus (modulus of longitudinal elasticity) E of a substrate material, Poisson's ratio v, substrate thickness (inversely proportional to the square of the substrate thickness), substrate length (proportional to the square of the length), linear expansion coefficient (difference thereof), temperature change, etc.

An amount of deformation (warpage) due to a change in temperature from room temperature to cryogenic temperature becomes more remarkable as the substrate21of the first wiring substrate20becomes thinner, which may result in a connection failure or other faults in the second bump electrodes42. In an example illustrated inFIG.7B, an area extending from the first bump electrodes41closest to the end (outmost) of the substrate11of the quantum chip10to an edge of the substrate11is an unbounded area (free end) in which warpage due to thermal contraction and other factors may cause the outermost first bump electrode41to tilt, resulting in a connection failure and other faults due to stripping of the junction portion (electrode peeling) and other problems.FIG.7Bschematically illustrates a large curvature warpage of the unbounded free end of the first wiring substrate20, while a warpage of the second wiring substrate30is not shown. This is because the warpage of the second wiring substrate30varies depending on thickness, size, material, etc.

When the second bump electrode42closest to the edge (outmost) of the substrate21of the first wiring substrate20is a ground bump, since many ground bumps are provided, the warpage of the unbounded free end of the first wiring substrate20will not necessarily incur a failure. The second bump electrode42, as a ground bump, connects a planer ground pattern (plane) in the second wiring layer23of the second wiring substrate20and a planer ground pattern (plane) in the third wiring layer33of the third wiring substrate30. However, in the case of a bump for signal transmission (signal bump), the warpage of the unbounded free end of the first wiring substrate20directly leads to signal characteristic degradation and failure such as wiring breakage.

FIG.7Cschematically illustrates a configuration of the present example embodiment, corresponding toFIG.7A. In the first wiring substrate20, regarding the first bump electrode41that connects to the quantum chip10, the first bump electrode41is located inside of the deformation suppression region defined inside the second bump electrodes42closest to an edge (outmost) of the substrate21. A length of the unbounded free area (end) extending from the second bump electrode42closest to an edge (outmost) of the substrate21to the edge of the substrate21is shorter than that inFIG.7A.

By shortening the length (predetermined length) of the area (free edge) where not bounded by the second bump electrodes42, deformation with a large curvature during heat shrinkage is suppressed. A predetermined length can be obtained by thermal stress analysis, etc. Similarly, for quantum chip10, by shortening the length of unbounded free edge from the first bump electrodes41at the most end portion side (outside) of the substrate11of the quantum chip10to the end portion of the substrate11as much as possible, deformation with a large curvature during heat shrinkage is suppressed. Even when the second bump electrode42at the most end portion side (outside) of the substrate21of the first wiring substrate20is a bump for signal transmission (signal bump), deformation such as warping of the substrate21is suppressed to ensure connection reliability and avoid deterioration of signal characteristics.

It is to be noted that it is possible to modify or adjust the example embodiments or examples within the whole disclosure of the present invention (including the Claims) and based on the basic technical concept thereof. Further, it is possible to variously combine or select a wide variety of the disclosed elements (including the individual elements of the individual claims, the individual elements of the individual examples and the individual elements of the individual figures) within the scope of the Claims of the present invention. That is, it is self-explanatory that the present invention includes any types of variations and modifications to be done by a skilled person according to the whole disclosure including the Claims, and the technical concept of the present invention.