BACK INTERFACE FOR RACK SHELF

An apparatus is described. The apparatus includes a rack shelf back interface. The rack shelf back interface has first and second flanges to mount to a rack’s rear facing rack mounts. The rack shelf back interface has a power connector610 on an inside of a back face of the rack shelf interface, the power connector to mate with a corresponding power connector on an electronic system that is to be installed in the rack shelf. The rack shelf back interface has an alignment feature on the inside of the back face of the rack shelf interface to ensure that the power connector properly mates with the corresponding power connector.

BACKGROUND

System design engineers face challenges, especially with respect to high performance data center computing, as both computers and networks continue to pack higher and higher levels of performance into smaller and smaller packages. Creative packaging solutions are therefore being designed to keep pace with such aggressively designed systems.

DETAILED DESCRIPTION

FIGS.1athrough1fdepict various views of rack mounted electronic systems.FIG.1adepicts the skeletal structure of a rack100for housing electronic systems. As observed inFIG.1a, the rack100includes an arrangement of slide rails101, front facing mounts102and back facing mounts103.

When installing an electronic system104, referring toFIG.1b, a technician slides the system104on the corresponding rails101of a particular one of the rack’s “shelves” (rails can be implemented as, e.g., static “L” brackets, actual rollers, etc.). After the technician has slid the system104a sufficient distance along the rails101, flanges105on the front face of the system will meet the front facing mounts.

Referring toFIG.1c, the flanges105and front facing mounts102have aligned holes through which thumb screws are threaded by the technician thereby mounting the front face of the electronic system104_1to the rack’s front facing mounts102. In the case of the rack specified by the Open-Compute Project, the system104slides along the rails101until some feature of the system104meets the back facing mounts103. The system104is then mounted to the front facing mounts102(See, e.g., “Open Compute Project, Open Rack Standard V2.1” published by Open Compute.org).

The technician then walks behind the rack. For most electronic systems, the mounting of the system104to the front facing mounts102in combination with support provided by the rails101, and/or other flooring, is sufficient to mechanically secure the system to the rack100. Nevertheless, at least in some cases, referring toFIG.1d, the technician mounts rear flanges106to the sides of the system104that corner with the back facing mounts103.

Each rear flange106is then mounted to its corresponding back facing mount103to secure the back of the system104to the rack. In many instances, the length of the system104is longer than the distance between the front and back facing mounts102,103such that the back face104_2of the system104extends beyond the back facing mounts103as depicted inFIG.1d.

As depicted inFIG.1e, the technician then plugs power chords, networking cables, and any liquid cooling fluidic conduits107to the back of the system104_1. Here, the chords, cables, and conduits107emanate from the back of the shelf so that the technician can readily plug them into the back of the system104_1after the system has been guided along the shelf’s rails and mounted to the front and back facing mounts102,103.

A problem is that the technician has to walk behind the rack in order mount the rear flanges106and plug the power chords, network cables, and fluidic conduits107to the back of the system104_1. Here, the electronic systems104that are mounted into a rack are typically designed to blow their hot exhaust air through the back of the system104_1. Thus, in cases where a number of systems are already plugged into and operating from within the rack, including additional systems that are operating within neighboring racks, the region behind the rack where the technician is standing can be uncomfortable because of its high temperature.

Generally, referring toFIG.1f, multiple racks having respective equipment mounted therein are aligned in rows with their respective backs facing each other and their respective fronts pointed away from each another. Often, walls108separate the front of the racks from the back of the racks so cool air can flow into the systems through the front of the racks and hot exhaust air can be collected from the back of the racks and vented.

Additionally, a large amount space is reserved behind the racks in order to accommodate the technician’s performing of the aforementioned installation tasks (mounting of rear flanges and plugging in of the power, networking, and fluidic conduits). This space corresponds to increased floor space for the overall data center implementation, which, in turn, drives up data center implementation costs.

FIGS.2athrough2gdepict an improved approach in which the back of the rack shelves are fitted with a common back interface210, e.g., as part of a rack’s initial configuration prior to installation of electronic systems within the rack. As will be described in more detail further below, as part of installing a back interface210for a particular shelf, the power chords, network cables, and fluidic conduits that have been routed in the rack for that shelf are plugged into that shelf’s back interface.

Upon the back interfaces being installed with their respective chord/cables/conduit connections along their respective shelfs, the rack is then positioned, e.g., along a row of racks. Importantly, with the back interfaces being installed in the rack, a technician need not walk behind the rack to install an electronic system into any particular shelf. Rather, the technician simply walks to the front of the rack, slides an electronic system along the rails of a particular one of the rack’s shelves and mounts the electronic system to the front facing mounts.

Here, as the electronic system is near the end of being slid along the shelf’s rails, the back of the electronic system mechanically engages with the back interface210which, in turn, mechanically couples the shelf’s power chords, network cables, and fluidic conduits to the back of the electronic system. Additionally, the back interface210can also provide some form of flooring that the underside of the back of the system rests upon for additional mechanical support.

In short, a shelf’s back interface210automatically couples the power chord, network cable, and cooling fluid conduit connections to the back of an electronic system while that system is being installed in the shelf.

FIG.2ashows a first angled view of a back interface210according to one embodiment. As observed inFIG.2a, the back interface210has the general shape of a cavity of some depth211. As the electronic system is being slid along the shelf rails, the back of the system enters the cavity211until the system’s power/network/fluidic connections are flush against the corresponding connections213,215on the inside of the cavity.

The particular back interface210embodiment ofFIG.2aincludes a left back face212having a first fluidic connection213that is coupled to a “hot” out-take fluidic conduit214. The hot out-take fluidic conduit214receives warmed fluid from the electronic system and directs it further within the rack’s hot egress fluidic conduits for subsequent cooling by, e.g., data center liquid cooling equipment. Additionally, the left back face212includes a first power connection215that is coupled to a first power chord216.

Similar connections exist inside a right back face217but are not visible inFIG.2aowing to the angle ofFIG.2a’s perspective. The fluidic conduit associated with the right back face’s fluidic connection is a “cold” intake fluidic conduit218that supplies cooled fluid to the electronic system. A second power connection that is coupled to a second power chord219is also present on the inside of the right back face217.

For ease of drawing, the back interface210ofFIG.2adoes not include a network cable interface on either of the back faces212,217but one or more such interfaces could readily be added/included.

The back interface210ofFIG.2aalso includes flanges221that are used to mount the back interface210to the rear facing rack mounts103during installation of the back interface210to the rack (prior to installation of the electronic system).

The particular back interface210embodiment ofFIG.2aalso include a floor222that mechanically integrates the left and right sides and back faces into a single, cohesive unit. Moreover, the floor222provides mechanical support for the rear of the electronic system. Here, the flanges221of the back interface210consume the rack’s rear facing mounts103at the expense of flanges106as depicted inFIG.1d. That is, the back interface210mounts to the rear facing mounts103rather than the electronic system. Nevertheless, the back of the electronic system can receive mechanical support by resting on floor222.

The particular embodiment ofFIG.2aalso includes a guide post (“pin”)223that emanates toward the electronic system from the inside of the left back face212. Another such pin can also exist on the inside of the right back face217but is not visible inFIG.2a.

Referring toFIG.2b, which depicts a side view, the back of the electronic system224has a corresponding hole225to receive guide pin223. During installation of the electronic system, when the electronic system is sliding on the shelf’s rails toward the inside face(s) of the back interface226, the guide pin223will enter the corresponding hole225at the back of the electronic system224.

The opening of the hole225at the back face of the electronic system224is large and the tip of the guide pin223is narrow so that there is plenty of tolerance to ensure the pin223will enter the hole225when the back face of the system224reaches the tip of the pin223. As the system continues to be pushed towards the back face226of the interface, however, as depicted inFIG.2c, the width of the hole225narrows and the width of the pin expands to bring the system’s connectors into precise alignment with their corresponding connections at the back interface once the pin223is fully inserted in the hole225as depicted inFIG.2d.

The precise alignment results in an axis227of precise alignment from which the locations of the connectors on both the electronic system and the inside face of the back interface can be defined in reference to.

Specifically,FIG.2eshows a direct view of the back face of the electronic system or the back interface. In the embodiment ofFIG.2dthere are two hole and pin arrangements resulting in a pair of axes of precision227_1,227_2. The leftwise axis of precision227_1is used to define the respective locations of leftwise connectors231,232. Specifically, the position of connector231is defined as +x1, +y1 and the position of connector232is +x2, -y2. Similarly, from rightwise axis227_2, the position of connector233is defined as -x3, +y3 and the position of connector234is -x4, -y4.

Importantly, the location of each of the connectors231,232,233,234defines the location of a pair of corresponding connectors: a first on the back face of the electronic system and a second on the inside of the back face of the back interface. By designing both the electronic system and the back interface to have identical coordinate locations relative to a same axis of precision for each pair of corresponding connectors, the connectors will successfully mate as each system connector presses into the corresponding interface connector during installation of the system.

FIG.2fshows a view of the back interface210ofFIG.2alooking directly into the cavity211. Here, the aforementioned the left side fluidic212and power213connectors on the left inner back face212are visible as are corresponding connectors on the right back face217.FIG.2gshows a direct rear view, whileFIG.2hshows an angled rear view, of the back interface210ofFIGS.2aand2e.

FIGS.3athrough3cshow views of the back interface embodiment210ofFIG.2amounted to a rack.FIG.3ashows an angled view looking into the back of a rack. Here, the right back face217of the back interface is visible while the left back face212is hidden behind the frame of the rack’s rear door. Notably, the right back face217is on the same side of the back interface210as the right back face217ofFIG.2a. However, becauseFIG.2ashows a front side view the interface210, while,FIG.3ashows a rear view of the interface, the right back face217appears on the left inFIG.3a.

FIG.3adepicts (a top corner of) the right side flange221mounted to one of the rear facing mounts103of the rack as well as the floor222of the back interface210. Notably, one of the rails101associated with the particular rack shelf that the back side interface210is mounted to and the rail’s relationship with the right back face217are also depicted.

FIG.3aalso shows the cold intake conduit218emanating from the rear of the right back face217and connecting into the rack’s conduit lines. Likewise,FIG.3ashows the right side power chord218emanating from the rear of the right back face217and connecting into the rack’s power bus.

FIG.3bshows the same view asFIG.3abut with the electronic system having been installed into the rack and the back side interface.

FIG.3cshows a top down view of the inside of the rack. Here, the back side interface is shown with both power chords and both fluidic conduits emanating from the interface and connecting to the rack. As depicted, both of the interface’s flanges are mounted to the rack’s rear facing mounts. The rails101of the particular shelf that the interface is associated with are also depicted.

FIGS.4athrough4cexplore different standard industry specification possibilities for different sized electronic systems and their corresponding standard back interfaces.

However, referring briefly back toFIG.1a, a typical rack100has front facing mounts102that are spaced a set distance apart150. Generally, the width of any/all electronic systems that are to be mounted to the rack100cannot exceed the spacing150between front facing mounts102(but narrower, e.g., “half width” components that mount to only one front facing mount can exist).

One example are systems and racks that conform to the International Electrotechnical Commission (IEC) Specification 60297 (entitled, “Mechanical structures for electronic equipment - Dimensions of mechanical structures of the 482.6 mm (19 in) series”). This particular standard sets a distance150of 19 inches between front facing mounts102. Other distances are possible (such as 23 inches).

The various electronic systems that can be installed into the rack100can have varying heights. According to current industry practice, referring now toFIG.1b, a system height151of 1U vertically along the front facing mounts102corresponds to 1.75″. The respective height151of various systems that can mount to the front facing mounts102are usually specified in units of U (e.g., 1U, 2U, 3U, etc.).

Thus, once an electronic system is designed to fit into a particular rack, the width of the system should stay within the distance150between the front facing mounts (e.g., 19″ or 23″) and the height151of the system can be specified in units of U.

Importantly, the depth of the electronic system can vary and different standardized back interfaces can be defined that establish different system depths and corresponding back interface cavities in increments.

FIGS.4athrough4cshow side views of different systems404_1,404_2,404_3having different depths that result in different extensions of the systems404_1,404_2,404_3beyond a rack’s rear facing mount103. The depth of a system is how far the system extends into the rack upon being mounted to the front side mounts102.

For example, a unit distance along the depth axis of can be established (e.g., Z = 2″). A system having a depth of OZ, as depicted inFIG.4a, corresponds to a system whose back face aligns with the rear facing mount103. The appropriate standardized back interface410_1for a OZ system likewise positions the connectors to align with the rear facing mounts103. In the OZ case, it is possible to implement the standard back interface410_1as left and right plates that mount to the read facing mounts103with little or no floor.

By contrast, referring toFIG.4b, a system404_2having a depth of 1Z corresponds to a system404_2whose back face resides 2Z behind the rear facing mounts103. The appropriate standardized back interface410_2for a 1Z system therefore positions the connectors to be 1Z behind the rear facing mounts103. Likewise, referring toFIG.4c, a system404_3having a depth of 2Z corresponds to a system404_3whose back face resides 2Z behind the rear facing mounts103. The appropriate standardized back interface410_3for a 2Z system404_3therefore positions the connectors to be 2Z behind the rear facing mounts103.

As discussed above with respect toFIG.2e, the positions of the connectors can also be standardized, e.g., relative to the position of the interface guide pin and the corresponding system hole and resulting axis of precision.

A set of mechanical specifications can therefore be developed for both electronic systems and corresponding standard back interfaces that define: 1) the manner and location of one or more holes and guide pins that define one or more axes of precision; 2) system/interface connector pairs defined by connector type (e.g., specific chord, cable or conduit) and location relative to an axis of precision; and, 3) system depth and corresponding back interface cavity depth defined in specified increments of Z (where Z can be any predefined distance, e.g., 1.5″, 2.0″, 2.5″, etc.). Multiple, different mechanical specifications/standards can therefore be defined where each unique specification/standard defines a unique set of the three above parameters.

Note that the back interface can be manufactured to include any of the power chords, network cables or fluidic conduits as integrated components of the interface (e.g., chords/cables/conduits “hang” off the back of the back interface). Alternatively, any of the power chords/cable/conduits can be assumed to be provided by the rack and the back interface has connectors at the outer back face to receive any such chords/cables/conduits.

Note that the guide pin and hole system described above with respect toFIGS.2b,2c, and2dare more generally mechanical alignment features. Other mechanical alignment features are possible. For example, a guide pin can be mounted at the back of the electronic system and the hole to receive the pin can be integrated on the inside of the back face of the back interface. In another embodiment the back interface has a floor that supports the system from the bottom, a ceiling to prevent the system from substantially moving upward/downward, and sides to substantially prevent side-to-side motion. With sufficient mechanical precision/tolerance of these features, enough guidance can be provided to the system during installation for successful mating between corresponding connectors of the system and the back interface.

Note that the connectors on the back of the electronic system and the corresponding connectors on the inside of the back face of the back interface can be referred to as “power connectors”, “network connectors” and “fluid connectors” and the like because these connectors mate without a chord/cable/conduit existing between the system/interface connection.

In various embodiments, referring back toFIG.2a, the back interface additionally includes a support ceiling230that sits above the inserted shelf to prevent upward/downward movement of the shelf during a shock or vibration event.

The teachings above can be applied to the cooling apparatus500ofFIG.5.FIG.5depicts a general cooling apparatus500whose features can be found in many different kinds of semiconductor chip cooling systems. As observed inFIG.5, one or more semiconductor chips within a package502(such as memory chips) are mounted to an electronic circuit board501(such as a DIMM). A cold plate503is thermally coupled with the package502(e.g., by being placed on the package502with a thermally conductive material (“thermal interface material”) between them) so that the cold plate503receives heat generated by the one or more semiconductor chips (the cold plate503can also be referred to as a vapor chamber in the case of two phase cooling systems).

Liquid coolant is within the cold plate503. If the system also employs air cooling (optional), a heat sink504can be thermally coupled to the cold plate503. Warmed liquid coolant and/or vapor505leaves the cold plate503to be cooled by one or more items of cooling equipment (e.g., heat exchanger(s), radiator(s), condenser(s), refrigeration unit(s), etc.) and pumped by one or more items of pumping equipment (e.g., dynamic (e.g., centrifugal), positive displacement (e.g., rotary, reciprocating, etc.))506. Cooled liquid507then enters the cold plate503and the process repeats.

Here, one or more semiconductor chips within a system that plugs into a rack shelf as described above with respect toFIGS.2a-h,3a-c, and4a-ccan be cooled with liquid cooling as described immediately above with respect toFIG.5. Here, cooled liquid can enter the system and be distributed to the respective cold plates in the system. The warmed fluid is then collected within the system so that it can collectively flow out of the system’s hot out-take fluidic conduit.

With respect to the cooling equipment and pumping equipment506, cooling activity can precede pumping activity, pumping activity can precede cooling activity, or multiple stages of one or both of pumping and cooling can be intermixed (e.g., in order of flow: a first cooling stage, a first pumping stage, a second cooling stage, a second pumping stage, etc.) and/or other combinations of cooling activity and pumping activity can take place.

Moreover, the intake of any equipment of the cooling equipment and pumping equipment506can be supplied by the cold plate of one semiconductor chip package or the respective cold plate(s) of multiple semiconductor chip packages.

In the case of the later (intake received from cold plate(s) of multiple semiconductor chip packages), the semiconductor chip packages can be components on a same electronic circuit board or multiple electronic circuit boards. In the case of the later (multiple electronic circuit boards), the multiple electronic circuit boards can be components of a same electronic system (e.g., different boards in a same server computer) or different electronic systems (e.g., electronic circuit boards from different server computers). In essence, the general depiction ofFIG.5describes compact cooling systems (e.g., a cooling system contained within a single electronic system), expansive cooling systems (e.g., cooling systems that cool the components of any of a rack, multiple racks, a data center, etc.) and cooling systems in between.

AlthoughFIG.5shows the cold plate503in direct contact with a semiconductor chip package, in other embodiments one or more intervening structure(s) can exist along the thermal path between the cold plate and the semiconductor chip package.

The following discussion concerningFIGS.6,7, and8are directed to systems, data centers and rack implementations, generally. As such,FIG.6generally describes possible features of an electronic system that can be installed into a rack shelf having a back interface as described at length above.FIG.7describes possible features of a data center having racks of electronic equipment with back interfaces as described above.FIG.8describes possible features of a rack having a back interface as described above.

FIG.6depicts an example system. System600includes processor610, which provides processing, operation management, and execution of instructions for system600. Processor610can include any type of microprocessor, central processing unit (CPU), graphics processing unit (GPU), processing core, or other processing hardware to provide processing for system600, or a combination of processors. Processor610controls the overall operation of system600, and can be or include, one or more programmable general-purpose or special-purpose microprocessors, digital signal processors (DSPs), programmable controllers, application specific integrated circuits (ASICs), programmable logic devices (PLDs), or the like, or a combination of such devices.

Certain systems also perform networking functions (e.g., packet header processing functions such as, to name a few, next nodal hop lookup, priority/flow lookup with corresponding queue entry, etc.), as a side function, or, as a point of emphasis (e.g., a networking switch or router). Such systems can include one or more network processors to perform such networking functions (e.g., in a pipelined fashion or otherwise).

In one example, system600includes interface612coupled to processor610, which can represent a higher speed interface or a high throughput interface for system components that needs higher bandwidth connections, such as memory subsystem620or graphics interface components640, or accelerators642. Interface612represents an interface circuit, which can be a standalone component or integrated onto a processor die. Where present, graphics interface640interfaces to graphics components for providing a visual display to a user of system600. In one example, graphics interface640can drive a high definition (HD) display that provides an output to a user. High definition can refer to a display having a pixel density of approximately100PPI (pixels per inch) or greater and can include formats such as full HD (e.g., 1080p), retina displays, 4K (ultra-high definition or UHD), or others. In one example, the display can include a touchscreen display. In one example, graphics interface640generates a display based on data stored in memory630or based on operations executed by processor610or both. In one example, graphics interface640generates a display based on data stored in memory630or based on operations executed by processor610or both.

Memory subsystem620represents the main memory of system600and provides storage for code to be executed by processor610, or data values to be used in executing a routine. Memory subsystem620can include one or more memory devices630such as read-only memory (ROM), flash memory, volatile memory, or a combination of such devices. Memory630stores and hosts, among other things, operating system (OS)632to provide a software platform for execution of instructions in system600. Additionally, applications634can execute on the software platform of OS632from memory630. Applications634represent programs that have their own operational logic to perform execution of one or more functions. Processes636represent agents or routines that provide auxiliary functions to OS632or one or more applications634or a combination. OS632, applications634, and processes636provide software functionality to provide functions for system600. In one example, memory subsystem620includes memory controller622, which is a memory controller to generate and issue commands to memory630. It will be understood that memory controller622could be a physical part of processor610or a physical part of interface612. For example, memory controller622can be an integrated memory controller, integrated onto a circuit with processor610. In some examples, a system on chip (SOC or SoC) combines into one SoC package one or more of: processors, graphics, memory, memory controller, and Input/Output (I/O) control logic circuitry.

In various implementations, memory resources can be “pooled”. For example, the memory resources of memory modules installed on multiple cards, blades, systems, etc. (e.g., that are inserted into one or more racks) are made available as additional main memory capacity to CPUs and/or servers that need and/or request it. In such implementations, the primary purpose of the cards/blades/systems is to provide such additional main memory capacity. The cards/blades/systems are reachable to the CPUs/servers that use the memory resources through some kind of network infrastructure such as CXL, CAPI, etc.

While not specifically illustrated, it will be understood that system600can include one or more buses or bus systems between devices, such as a memory bus, a graphics bus, interface buses, or others. Buses or other signal lines can communicatively or electrically couple components together, or both communicatively and electrically couple the components. Buses can include physical communication lines, point-to-point connections, bridges, adapters, controllers, or other circuitry or a combination. Buses can include, for example, one or more of a system bus, a Peripheral Component Interconnect express (PCIe) bus, a HyperTransport or industry standard architecture (ISA) bus, a small computer system interface (SCSI) bus, Remote Direct Memory Access (RDMA), Internet Small Computer Systems Interface (iSCSI), NVM express (NVMe), Coherent Accelerator Interface (CXL), Coherent Accelerator Processor Interface (CAPI), Cache Coherent Interconnect for Accelerators (CClX), Open Coherent Accelerator Processor (Open CAPI) or other specification developed by the Gen-z consortium, a universal serial bus (USB), or an Institute of Electrical and Electronics Engineers (IEEE) standard 1394 bus.

In one example, system600includes interface614, which can be coupled to interface612. In one example, interface614represents an interface circuit, which can include standalone components and integrated circuitry. In one example, multiple user interface components or peripheral components, or both, couple to interface614. Network interface650provides system600the ability to communicate with remote devices (e.g., servers or other computing devices) over one or more networks. Network interface650can include an Ethernet adapter, wireless interconnection components, cellular network interconnection components, USB (universal serial bus), or other wired or wireless standards-based or proprietary interfaces. Network interface650can transmit data to a remote device, which can include sending data stored in memory. Network interface650can receive data from a remote device, which can include storing received data into memory. Various embodiments can be used in connection with network interface650, processor610, and memory subsystem620.

In one example, system600includes one or more input/output (I/O) interface(s)660. I/O interface660can include one or more interface components through which a user interacts with system600(e.g., audio, alphanumeric, tactile/touch, or other interfacing). Peripheral interface670can include any hardware interface not specifically mentioned above. Peripherals refer generally to devices that connect dependently to system600. A dependent connection is one where system600provides the software platform or hardware platform or both on which operation executes, and with which a user interacts.

In one example, system600includes storage subsystem680to store data in a nonvolatile manner. In one example, in certain system implementations, at least certain components of storage680can overlap with components of memory subsystem620. Storage subsystem680includes storage device(s)684, which can be or include any conventional medium for storing large amounts of data in a nonvolatile manner, such as one or more magnetic, solid state, or optical based disks, or a combination. Storage684holds code or instructions and data in a persistent state (e.g., the value is retained despite interruption of power to system600). Storage684can be generically considered to be a “memory,” although memory630is typically the executing or operating memory to provide instructions to processor610. Whereas storage684is nonvolatile, memory630can include volatile memory (e.g., the value or state of the data is indeterminate if power is interrupted to system600). In one example, storage subsystem680includes controller682to interface with storage684. In one example controller682is a physical part of interface614or processor610or can include circuits in both processor610and interface614.

In an example, system600can be implemented as a disaggregated computing system. For example, the system600can be implemented with interconnected compute sleds of processors, memories, storages, network interfaces, and other components. High speed interconnects can be used such as PCIe, Ethernet, or optical interconnects (or a combination thereof). For example, the sleds can be designed according to any specifications promulgated by the Open Compute Project (OCP) or other disaggregated computing effort, which strives to modularize main architectural computer components into rack-pluggable components (e.g., a rack pluggable processing component, a rack pluggable memory component, a rack pluggable storage component, a rack pluggable accelerator component, etc.).

Although a computer is largely described by the above discussion ofFIG.6, other types of systems to which the above described invention can be applied and are also partially or wholly described byFIG.6are communication systems such as routers, switches, and base stations.

FIG.7depicts an example of a data center. Various embodiments can be used in or with the data center ofFIG.7. As shown inFIG.7, data center700may include an optical fabric712. Optical fabric712may generally include a combination of optical signaling media (such as optical cabling) and optical switching infrastructure via which any particular sled in data center700can send signals to (and receive signals from) the other sleds in data center700. However, optical, wireless, and/or electrical signals can be transmitted using fabric712. The signaling connectivity that optical fabric712provides to any given sled may include connectivity both to other sleds in a same rack and sleds in other racks.

Data center700includes four racks702A to702D and racks702A to702D house respective pairs of sleds704A-1and704A-2,704B-1and704B-2,704C-1and704C-2, and704D-1and704D-2. Thus, in this example, data center700includes a total of eight sleds. Optical fabric712can provide sled signaling connectivity with one or more of the seven other sleds. For example, via optical fabric712, sled704A-1in rack702A may possess signaling connectivity with sled704A-2in rack702A, as well as the six other sleds704B-1,704B-2,704C-1,704C-2,704D-1, and704D-2that are distributed among the other racks702B,702C, and702D of data center700. The embodiments are not limited to this example. For example, fabric712can provide optical and/or electrical signaling.

FIG.8depicts an environment800that includes multiple computing racks802, each including a Top of Rack (ToR) switch804, a pod manager806, and a plurality of pooled system drawers. Generally, the pooled system drawers may include pooled compute drawers and pooled storage drawers to, e.g., effect a disaggregated computing system. Optionally, the pooled system drawers may also include pooled memory drawers and pooled Input/Output (I/O) drawers. In the illustrated embodiment the pooled system drawers include an INTEL®XEON®pooled computer drawer808, and INTEL®ATOM™ pooled compute drawer810, a pooled storage drawer812, a pooled memory drawer814, and a pooled I/O drawer816. Each of the pooled system drawers is connected to ToR switch804via a high-speed link818, such as a 40 Gigabit/second (Gb/s) or 100 Gb/s Ethernet link or a 100+ Gb/s Silicon Photonics (SiPh) optical link. In one embodiment high-speed link818comprises a 600 Gb/s SiPh optical link.

Again, the drawers can be designed according to any specifications promulgated by the Open Compute Project (OCP) or other disaggregated computing effort, which strives to modularize main architectural computer components into rack-pluggable components (e.g., a rack pluggable processing component, a rack pluggable memory component, a rack pluggable storage component, a rack pluggable accelerator component, etc.).

Multiple of the computing racks800may be interconnected via their ToR switches804(e.g., to a pod-level switch or data center switch), as illustrated by connections to a network820. In some embodiments, groups of computing racks802are managed as separate pods via pod manager(s)806. In one embodiment, a single pod manager is used to manage all of the racks in the pod. Alternatively, distributed pod managers may be used for pod management operations. RSD environment800further includes a management interface822that is used to manage various aspects of the RSD environment. This includes managing rack configuration, with corresponding parameters stored as rack configuration data824.

Any of the systems, data centers or racks discussed above, apart from being integrated in a typical data center, can also be implemented in other environments such as within a bay station, or other micro-data center, e.g., at the edge of a network.

Some examples may be implemented using or as an article of manufacture or at least one computer-readable medium. A computer-readable medium may include a non-transitory storage medium to store program code. In some examples, the non-transitory storage medium may include one or more types of computer-readable storage media capable of storing electronic data, including volatile memory or non-volatile memory, removable or non-removable memory, erasable or non-erasable memory, writeable or re-writeable memory, and so forth. In some examples, the program code implements various software elements, such as software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, API, instruction sets, computing code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof.

To the extent any of the teachings above can be embodied in a semiconductor chip, a description of a circuit design of the semiconductor chip for eventual targeting toward a semiconductor manufacturing process can take the form of various formats such as a (e.g., VHDL or Verilog) register transfer level (RTL) circuit description, a gate level circuit description, a transistor level circuit description or mask description or various combinations thereof. Such circuit descriptions, sometimes referred to as “IP Cores”, are commonly embodied on one or more computer readable storage media (such as one or more CD-ROMs or other type of storage technology) and provided to and/or otherwise processed by and/or for a circuit design synthesis tool and/or mask generation tool. Such circuit descriptions may also be embedded with program code to be processed by a computer that implements the circuit design synthesis tool and/or mask generation tool.