Coefficient tap leakage for fractionally-spaced equalizers

A quadrature amplitude modulated (QAM) data signal transmitted at T symbols per second is sampled in a data receiver at a rate of 2/T samples per second and applied to a transversal-type equalizer structure (25, 46, 34, 35) having taps spaced at T/2 second intervals. A demodulated equalized signal (a.sub.j, b.sub.j), generated once every T seconds, is quantized to form a decision (a.sub.j *, b.sub.j *) as to the value of the original modulating data symbol. An error signal (e.sub.j, e.sub.j) is formed in response to the pre- and post-quantized values of the demodulated equalized signal. Tap coefficients (c.sub.i (j), c.sub.i (j)) used in generating the equalized signals are updated in response to (a) a correction term which is a function of the error signal and (b) a predetermined tap leakage term which has a constant magnitude. The introduction of the tap leakage term maintains the coefficient values at minimum levels.

BACKGROUND OF THE INVENTION 
The present invention relates to automatic equalizers which compensate for 
the distorting effects of band-limited channels on transmitted data 
signals. 
Automatic equalizers are necessary for accurate reception of high-speed 
data signals transmitted over band-limited channels with unknown 
transmission characteristics. The equalizer is generally in the form of a 
transversal filter in which successive samples of the incoming data signal 
are multiplied by respective tap coefficients. The resulting products are 
added together to generate an "equalized" signal which is then demodulated 
and/or quantized to recover the transmitted data. In addition, an error 
signal is formed equal to the difference between the equalized signal and 
a reference signal which represents the transmitted data symbol. The value 
of the symbol that was transmitted may be known at the receiver, a priori 
as is the case in many equalizer start-up arrangements. Alternatively, as 
in the so-called adaptive type of automatic equalizer, the reference 
signal is derived from the decision made in the receiver (on the basis of 
the equalized signal value) as to what data symbol was transmitted. In 
either case, the error signal is used to update the tap coefficient values 
in such a way as to minimize a measure of the distortion--primarily 
intersymbol interference--introduced by the channel. The most commonly 
used error-directed coefficient updating algorithm is the so-called 
mean-squared error algorithm, which adjusts the tap coefficients so as to 
minimize the average of the value of the square of the error signal. 
Most commercial data receivers, e.g., data modems, incorporate a 
synchronous, or baud, equalizer in which the received data signal is 
sampled at a rate equal to the symbol rate. It is, however, possible to 
use a so-called fractionally-spaced equalizer in which the received signal 
is sampled at a higher rate. Data decisions, i.e., quantizations of the 
equalized samples, are still made at the symbol rate. However, the fact 
that equalization is carried out using a finer sampling interval provides 
the fractionally-spaced equalizer with significant advantages over its 
more conventional cousin. Most notable among these is insensitivity to 
channel delay distortion, including sampling phase errors. 
There is, however, at least one significant problem unique to the 
fractionally-spaced equalizer. In a synchronous equalizer, one set of tap 
coefficients is clearly optimum, i.e., provides the smallest mean-squared 
error. By contrast, many sets of coefficient values provide approximately 
the same mean-squared error in the fractionally-spaced equalizer. As a 
consequence of this property, the presence of small biases in the 
coefficient updating processing hardware--such as biases associated with 
signal value roundoff--can cause at least some of the coefficient values 
to drift to very large levels, or "blow-up", even though the mean-squared 
error remains at, or close to, its minimum value. The registers used to 
store the coefficients or other signals computed during normal equalizer 
operation can then overflow, causing severe degradation, or total 
collapse, of the system response. 
The prior art--exemplified by G. Ungerboeck, "Fractional Tap-Spacing 
Equalizers and Consequences for Clock Recovery for Data Modems," IEEE 
Trans. on Communications, Vol. COM-24, No. 8, August 1976, pp. 
856-864--suggests that the problem of coefficient value blow-up can be 
controlled by introducing one of two alternative auxiliary terms into the 
conventional updating algorithm. The auxiliary term may be, for example, a 
predetermined small fraction of the current value of the coefficient being 
updated. This implements a so-called tap leakage approach. Alternatively, 
a spectral zero-forcing approach is suggested. Here the auxiliary term is 
a predetermined small fraction of an alternating-sign sum of the current 
values of all the coefficients. 
Having presented these approaches for controlling coefficient blow-up, the 
Ungerboeck article further reports that in a computer simulation of a 
fractionally-spaced equalizer, blow-up actually never occurred, at least 
when sufficient precision was used in the computations. 
SUMMARY OF THE INVENTION 
We have discovered that the blow-up of tap coefficients in 
fractionally-spaced equalizers is a more serious problem than has been 
heretofore recognized. Computer studies, such as reported in the prior 
art, typically simulate only several seconds of equalizer operation. We 
have found, however, that in an actual implementation, depending on the 
nature of the bias which causes the blow-up, it can take as much as 
forty-five minutes for the above-mentioned register overflow to occur. 
Moreover, we have discovered that the techniques proposed in the prior art 
to deal with the coefficient blow-up, although perhaps effective in 
dealing with that problem, are not wholly satisfactory from other 
standpoints. For example, it is desirable in any transversal filter type 
of automatic equalizer to have as many of the coefficient values at or as 
close to zero as possible. This means that the numerical computations 
associated with coefficient updating will involve the manipulation and 
storage of smaller numbers than would otherwise be the case. This, in 
turn, minimizes the complexity and expense of the computational hardware. 
In addition, keeping as many of the coefficient values at or as close to 
zero as possible best conditions the system to withstand the effects of, 
and to recover from, phase hits and other transmission disturbances. The 
prior art approaches for dealing with coefficient blow-up, while providing 
an upper limit for the coefficient values, allow a large number of the 
coefficients to assume values which are not at or close to zero. Thus, 
system performance suffers. 
The present invention provides a technique which not only prevents the 
blow-up of fractionally-spaced equalizer coefficients, but also minimizes 
their values. As in the prior art, a tap leakage term is introduced into 
the coefficient updating algorithm. Our invention differs from the prior 
art, however, in that the magnitude of the tap leakage term is independent 
of any coefficient value. In an illustrative embodiment, for example, the 
tap leakage term has a constant magnitude, its sign being such as to drive 
the magnitude of the coefficient then being updated in the direction of 
zero. 
The efficacy of the present invention is a result of its "never-quit" 
approach; no matter how small any coefficient gets, the full value of the 
tap leakage term enters the updating computation. This approach is 
efficacious because it is directed to what we have discovered to be the 
cause of the coefficient blow-up problem-bias in the arithmetic 
operations. The prior art approaches, by contrast, by providing a 
correction term magnitude which is a function of coefficient magnitude, 
are directed only to the symptom, i.e., large coefficient values. The 
problem with such an approach is that the tap leakage or spectral 
zero-forcing terms used in the prior art may become so small that, due to 
roundoff inherent in the digital circuitry implementing the equalizer, no 
change from the value specified by the error-directed part of the updating 
algorithm is made. This opens the door for other coefficient magnitudes, 
theretofore at or close to zero, to begin to creep upward.

DETAILED DESCRIPTION 
The present invention is illustrated herein in the context of a 
quadrature-amplitude modulated (QAM) digital data transmission system. 
Four paralleled information bits are illustratively transmitted during 
each symbol interval of duration T=1/2400 sec. The symbol rate is thus 
2400 baud, yielding a binary data transmission rate of 9600 bits per 
second. During each symbol interval, the four bits to be transmitted are 
encoded into two data signals, each of which can take on one of the four 
values {+1, -1, +3, -3}. These two data signals, after baseband filtering, 
amplitude-modulate respective 1800-Hz carrier waves which are in 
quadrature relation, i.e., 90.degree. out-of-phase with respect to one 
another. The modulated signals are added together and transmitted over a 
bandlimited data (e.g., voiceband telephone) channel. 
FIG. 1 is a simplified block diagram of a fractionally-spaced 
equalizer/demodulator for use in a receiver for the above-described type 
of QAM signals. The tap coefficients used in the fractionally-spaced 
equalizer are updated in accordance with the tap leakage technique of the 
present invention. 
More particularly, the received QAM passband signal on line 10 (which has 
been previously passed through a bandpass filter (not shown) is passed 
through a phase splitter 11. The latter generates two replicas of the 
received analog signal, one lagging the other by 90.degree.. The signals, 
which are a Hilbert Transform pair, are passed to A/D converter 12. 
In general, the above-described advantages provided by a 
fractionally-spaced equalizer are realized when the sample rate is at 
least (1+.alpha.)/T, where .alpha.=(2Tf.sub.co -), f.sub.co being the 
highest spectral component about the carrier frequency (i.e., the highest 
component in the modulating (baseband) signal) having at least a 
predetermined energy. The parameter .alpha. is referred to as the 
fractional excess bandwidth. A/D converter 12, in particular, 
illustratively operates at 2/T=4800 times per second, i.e., twice the 
symbol rate, to generate two passband, i.e., modulated, signal samples 
R.sub.j and R.sub.j ' during the j.sup.th receiver symbol interval. (An 
alternative way of generating R.sub.j and R.sub.j ' is to first sample and 
digitize the received signal at a rate greater than twice its highest 
frequency component and then pass the resulting signal through a digital 
phase-splitter.) 
QAM signals are conveniently expressed and processed as complex numbers, 
each having a real and imaginary component. The real and imaginary 
components of the samples formed by A/D converter 12 are provided in 
serial form as separate ten-bit digital signals, or words, on respective 
output leads 14 and 15. (Each of the other signal leads in FIG. 1 
similarly carries it signals in serial form.) Notationally, the real and 
imaginary components of sample R.sub.j are represented as r.sub.j and 
r.sub.j. Those of sample R.sub.j ' are represented as r.sub.j ' and 
r.sub.j '. 
Samples R.sub.j and R.sub.j ', which are spaced T/2 seconds apart, are 
equalized using two synchronous equalizer units 25 and 26. Each of these 
units is adapted to operate on a complex sample stream in which the 
samples are spaced T seconds apart. Double-throw switch 16 applies 
components r.sub.j and r.sub.j to equalizer unit 25 and components r.sub.j 
' and r.sub.j ' to equalizer unit 26. Separate data streams, each 
containing samples spaced T seconds apart, are thus presented to each 
equalizer unit. A delay unit 23 is interposed between switch 16 and 
equalizer unit 25 so that r.sub.j and r.sub.j are applied to equalizer 
unit 25 at the same time that r.sub.j ' and r.sub.j ' are applied to 
equalizer unit 26. This advantageously allows equalizer units 25 and 26 to 
be controlled by the same clocking and timing signals. 
The output signal Q.sub.j of equalizer unit 25, described more fully below, 
is comprised of real and imaginary components q.sub.j and q.sub.j which 
appear as ten-bit words on leads 43 and 44. Similarly, the output signal 
Q.sub.j ' of equalizer unit 26 is comprised of real and imaginary 
components q.sub.j ' and q.sub.j ', which appear on leads 45 and 46. 
Components q.sub.j and q.sub.j ' are added together in an adder 45 while 
components q.sub.j and q.sub.j ' are added together in an adder 35. The 
outputs of adders 34 and 35 are the real and imaginary components z.sub.j 
and z.sub.j of a modulated equalized signal Z.sub.j associated with a 
particular transmitted symbol. (Signal Z.sub.j could have been 
equivalently generated using a single equalizer unit having taps spaced at 
T/2 second intervals.) 
Signal Z.sub.j is demodulated to baseband by demodulator 27. The 
demodulated output of demodulator 27 is equalized signal A.sub.j, which 
has real and imaginary components a.sub.j and b.sub.j, provided as ten-bit 
words on leads 38 and 39, respectively. The demodulation process performed 
by demodulator 27 is expressed in complex notation as 
EQU A.sub.j =Z.sub.j e.sup.-j.theta..sbsp.j.sup.* 
where j=.sqroot.-1 and .theta..sub.j * is an estimate of the current 
carrier phase. In terms of real and imaginary components, the demodulation 
process is expressed as 
EQU a.sub.j =z.sub.j cos (.theta..sub.j *)+z.sub.j sin (.theta..sub.j *) 
b.sub.j =z.sub.j cos (.theta..sub.j *)-z.sub.j sin (.theta..sub.j *). 
For purposes of generating a.sub.j and b.sub.j in accordance with the above 
expressions, demodulator 27 receives nine-bit digital representations of 
sin (.theta..sub.j *) and cos (.theta..sub.j *) on output leads 52 and 53 
of carrier source 51. 
Components a.sub.j and b.sub.j are quantized in I (in-phase) decision 
circuit 41 and Q (quadrature-phase) decision circuit 42, respectively. The 
resulting outputs on leads 56 and 57 are decisions a.sub.j * and b.sub.j * 
as to the value of the data symbol with which equalized signal Z.sub.j is 
associated. Decisions a.sub.j * and b.sub.j * can be thought of as the 
real and imaginary components of a complex decision A.sub.j *. 
Decision circuits 41 and 42 also provide, on leads 61 and 62, the real and 
imaginary components, .delta..sub.j and .DELTA..sub.j, of a complex 
baseband error signal .DELTA..sub.j associated with the data symbol in 
question. The value of signal .DELTA..sub.j is equal to the difference 
between the value of equalized signal A.sub.j and the value of the 
transmitted symbol. During the equalizer start-up period, in which a 
predetermined data stream is transmitted (to facilitate the determination 
of an initial set of coefficient values), the value of the transmitted 
symbols are known a priori. Thereafter, the equalizer/demodulator operates 
adaptively, with value of the transmitted symbol being taken to be (the 
assemdly correct) decision A.sub.j *. 
Assuming operation in the latter mode, baseband error signal .DELTA..sub.j 
is equal to the quantity (A.sub.j -A.sub.j *). In particular, 
.delta..sub.j =(a.sub.j -a.sub.j *) and .delta..sub.j =(b.sub.j -b.sub.j 
*), with .delta..sub.j and .delta..sub.j being expressed as respective 
twelve-bit words. Error signal .DELTA..sub.j is remodulated in error 
remodulator 37 to yield a remodulated, or passband, error signal E.sub.j 
given by 
EQU E.sub.j =.DELTA..sub.j e.sup.+j.theta..sbsp.j.sup.* 
The real and imaginary components of E.sub.j, e.sub.j and e.sub.j, are 
generated by remodulator 37 in accordance with 
EQU e.sub.j =.delta..sub.j cos (.theta..sub.j *)-.delta..sub.j sin 
(.theta..sub.j *) 
EQU e.sub.j =.delta..sub.j sin (.theta..sub.j *)+.delta..sub.j cos 
(.theta..sub.j *) 
To this end, remodulator 37, like modulator 27, receives sin (.theta..sub.j 
*) and cos (.theta..sub.j *) from carrier source 51. Components e.sub.j 
and e.sub.j are extended to equalizer units 25 and 26 on a time-shared 
basis on lead 58 for purposes of coefficient updating, as described below. 
(An alternative way of generating error signal E.sub.j would be to 
remodulate complex decision A.sub.j * and substract it from modulated 
equalized signal Z.sub.j. In either case, the value of E.sub.j is the 
same, it being equal to the difference, modulated at the carrier 
frequency, between the pre- and post-quantized values of equalized signal 
A.sub.j.) 
FIG. 2 is a simplified block diagram of equalizer unit 25. The structure of 
equalizer unit 26 is illustratively identical to that of equalizer unit 25 
and thus need not be described in detail. 
As shown in FIG. 2, the r.sub.j components of sample R.sub.j are received 
by equalizer unit 25 on the lead 19 and stored in r.sub.j store 113. The 
r.sub.j components, received on lead 20, are stored in r.sub.j store 114. 
Stores 113 and 114 illustratively include respective first-in/first-out 
(FIFO) recirculating memories, each storage location of which represents a 
transversal equalizer tap position. Each store has (2 N+1) storage 
locations, N being a selected integer, so that during the j.sup.th 
receiver symbol interval, stores 113 and 114 hold the components of a 
plurality of (2 N+1) samples R.sub.j through R.sub.j-2 N associated with 
the j.sup.th interval. Associated with the i.sup.th equalizer tap 
position, i=(O,1 . . . 2 N), is a complex coefficient C.sub.i (j), which 
has a particular value associated with the j.sup.th receiver symbol 
interval. (In this embodiment, as described below, that value is partially 
updated during the interval.) The real and imaginary components c.sub.i 
(j) and c.sub.i (j) of C.sub.i (j) are each represented as a 
twenty-four-bit word. The c.sub.i (j)'s are initially held in c.sub.i 
coefficient store 119. The c.sub.i (j)'s are initially held in c.sub.i 
coefficient store 120. Stores 119 and 120 also illustratively include FIFO 
memories. 
During the j.sup.th receiver symbol interval, equalizer unit 25 generates 
signal Q.sub.j in accordance with 
##EQU1## 
Expressed in terms of real and imaginary components, 
##EQU2## 
Real component q.sub.j is generated first. In particular, the (2 
N+1)r.sub.j-i components are sequentially read out of store 113 into one 
input of multiplier 123. As the bits of each r.sub.j-i component are 
applied serially to one multiplier input, the bits of the corresponding 
coefficient component, c.sub.i (j), are serially read out of store 119 and 
applied to the other multiplier input. At the same time, each of the (2 
N+1) r.sub.j-i components is read out of store 114 and multiplied in 
multiplier 124 by the corresponding coefficient component, c.sub.i (j), 
read out of store 120. Each product formed in multipliers 123 and 124 is 
hereinafter referred to as a "tap product." 
Only the twelve highest-order bits of each twenty-four-bit word 
representing each c.sub.i (j) and c.sub.i (j) coefficient component are 
used in generating tap products; the other twelve bits are carried along 
for purposes of smoothing out the updating process. The tap products 
c.sub.i (j)r.sub.j-i and c.sub.i (j)r.sub.j-i appearing on leads 138 and 
139, respectively, are summed in passband accumulator 127, passband 
accumulator 128 being inactive at this time. 
The same values of coefficient components c.sub.i (j) and c.sub.i (j) used 
to generate signal component q.sub.j, as just described, could also be 
used in generating signal component q.sub.j. The coefficient component 
values would then be updated in preparation for the next symbol interval. 
In the present illustrative embodiment, however, the coefficient values 
used to form q.sub.j are partially updated before q.sub.j is formed, the 
remainder of the updating being performed thereafter. This approach 
advantageously reduces the total amount of signal processing time needed 
during each symbol interval. 
A detailed explanation of the coefficient updating process appears 
hereinbelow. For purposes of describing FIG. 2, however, it suffices to 
say that each c.sub.i (j) component, in addition to being read from store 
119 into multiplier 123 for tap product generation, is also read into 
coefficient update unit 122, where it is partially updated. The partially 
updated c.sub.i (j)'s pass from update unit 122 to store 120 via lead 118. 
Each c.sub.i (j) component, similarly, is not only read from store store 
into multiplier 124, but also into coefficient update unit 121. The 
partially updated c.sub.i (j)'s pass from update uunit 121 into store 119 
via lead 117. Thus, after component q.sub.j has been generated and stored 
in accumulator 127, the c.sub.i (j) and c.sub.i (j) coefficient 
components, partially updated, are resident in stores 120 and 119, 
respectively. 
Component q.sub.j is now generated in much the same way as component 
q.sub.j was. The tap products c.sub.i (j)r.sub.j-i and c.sub.i 
(j)r.sub.j-i are generated on leads 138 and 139, respectively, and are 
combined together in passband accumulator 128 (accumulator 127 now being 
inactive). The c.sub.i (j)'s and c.sub.i (j)'s pass through update units 
121 and 122 where the second step of the coefficient updating process is 
performed. The c.sub.i (j)'s, now fully updated, return to store 119. The 
fully updated c.sub.i (j)'s are similarly returned to store 120. 
The updating of coefficients C.sub.i (j) will now be described in detail. 
Conventionally, adaptive equalizer coefficients are updated by additively 
combining (i.e., adding or subtracting) an updating, or correction, term 
therewith. This procedure can be represented, in general, as 
##EQU3## 
where .alpha. is a predetermined positive, fractional constant and F(j) is 
the correction term. (More generally, .alpha. could be a function of j.) 
In accordance with the present invention, a "tap leakage" term is 
introduced into the conventional coefficient updating expression, that 
term also being additively combined with the coefficient being updated. In 
contradistinction to prior art tap leakage arrangements, the present tap 
leakage term has a magnitude which is independent of any coefficient 
value. In the present illustrative embodiment, more particularly, the tap 
leakage term has a constant magnitude .alpha..mu., where .mu. is a 
predetermined positive constant. The sign of the tap leakage term for the 
updating of a particular coefficient is such as to drive the magnitude of 
that coefficient in the direction of zero--positive for negative 
coefficients and negative for positive coefficients. The conventional 
coefficient updating rule is thus modified in accordance with the 
invention to be 
EQU C.sub.i (j+1)=C.sub.i (j)-.alpha.F(j)-.alpha..mu.sgn [C.sub.i (j)], 
where the value of the function sgn [x] is either +1 or -1, depending on 
the sign of x. 
The value of .mu. is arrived at empirically. It should be sufficiently 
large to maintain the coefficient values at acceptable levels. It should 
not, however, be so large as to severely degrade equalizer performance. 
The so-called mean-squared error algorithm is used in the present 
embodiment to determine the value of F(j) and, typically, F(j) would be a 
function of E.sub.j. In this embodiment, however, coefficient updating 
begins before signal E.sub.j has been formed. Accordingly, error signal 
E.sub.j-1, which was formed during the previous, (j-1).sup.st, symbol 
interval, is used instead, yielding an F(j) given by E.sub.j-1 
R.sub.j-i-1. The complete mean-squared error/tap leakage updating rule is 
then 
EQU C.sub.i (j+1)=C.sub.i (j)-.alpha.E.sub.j-1 R.sub.j-i-1 
-.alpha..mu.sgn[C.sub.i (j)]. 
This is expressed in terms of real and imaginary components as 
EQU c.sub.i (j+1)=c.sub.i (j)-.alpha.e.sub.j-1 r.sub.j-i-1 
+.alpha.ej-1r.sub.j-i-1 -.alpha..mu.sgn[c.sub.i (j)]. (3) 
EQU c.sub.i (j+1)=c.sub.i (j)-.alpha.e.sub.j-1 r.sub.j-i-1 -.alpha.e.sub.j-1 
r.sub.j-i-1 -.alpha..mu.sgn[c.sub.i (j)]. (4) 
As previously noted, the structure of equalizer unit 26 is illustratively 
identical to that of equalizer unit 25. Thus, the output Q.sub.j ' of 
equalizer unit 26 can be expressed in terms of a second set of complex 
coefficients C.sub.i '(j) as 
##EQU4## 
so that 
##EQU5## 
Thus, also, the updating relation for the C.sub.j '(j)'s is C.sub.i 
'(j+1)=C.sub.i '(j)-.alpha.F'(j)-.alpha..mu.sgn[C.sub.i '(j)], where, 
illustratively, F'(j)=E.sub.j-1 R.sub.j '.sub.-i-1. 
Attention is now redirected to FIG. 2. Since the coefficient updating is a 
function of error values, coefficient update units 121 and 122 each 
receive the remodulated error components which appear on lead 58, as 
previously described. Coefficient updating is also a function of sample 
values. To this end, update unit 122 receives sample components from store 
113 via lead 115, while update unit 121 receives sample components from 
store 114 via lead 116. Concomitant with the generation of signal 
component q.sub.j, in particular, update unit 122 subtracts 
.alpha.e.sub.j-1 r.sub.j-i-l and .alpha..mu.sgn[c.sub.i (j)] from the 
c.sub.i (j)'s while update unit 121 subtracts .alpha.e.sub.j-1 r.sub.j-i-1 
from the c.sub.i (j)'s. Concomitant with the subsequent generation of 
q.sub.j, update unit 122 subtracts .alpha.e.sub.j-1 r.sub.j-i-1 and 
.alpha..mu.sgn[c.sub.i (j)] from the c.sub.i (j)'s. Update unit 121 at 
this time adds .alpha.e.sub.j-1 r.sub.j-i-1 to the c.sub.i (j)'s. The 
c.sub.i (j) and c.sub.i (j) components of coefficients C.sub.i (j) are 
thus fully updated in accordance with Eqs. (3) and (4). 
Attention is now directed to FIG. 3 which shows additional details of 
r.sub.j store 113, c.sub.i coefficient store 119 and coefficient update 
unit 122. Store 113, to which store 114 (FIG. 2) is similar, includes data 
selector 101, input and output hold registers 103 and 106, and FIFO memory 
104. Store 119, to which store 120 is similar, includes input and output 
hold registers 151 and 156 and FIFO memory 153. Update unit 122 includes 
MSE circuit 170 which, in combination with a similar circuit in update 
unit 121, provides conventional mean-squared error updating. Update unit 
122 further includes tap leakage circuit 180, which generates the tap 
leakage term of the present invention. 
The operation of the circuitry of FIG. 3 to provide coefficient component 
updating will now be described. Assume, by way of example, that 
coefficient multiplication and updating during the current receiver symbol 
interval have been in progress for a short while so that several of the 
c.sub.i (j)'s resident in store 119 at the start of the symbol interval 
have already been multiplied by a sample component in multiplier 123 and 
partially updated in update unit 122. At this point, load pulse is 
provided on lead 158, which extends from the receiver's timing and clock 
circuit 190. This load pulse causes the next c.sub.i (j) in the queue of 
memory 153 to be loaded in parallel form into register 156. The load pulse 
also causes the c.sub.i (j) most recently updated in update unit 121, 
which is now stored in register 151, to be entered at the end of the queue 
within memory 153. 
A sequence of twenty-four shift pulses is now provided from circuit 190 on 
lead 159. These pulses cause the bits of the coefficient component c.sub.i 
(j) held in register 156 to be shifted out to update unit 122 via lead 
112. At this time, sample component r.sub.j-i-1 is resident in output hold 
register 106 of store 113. The above-mentioned shift pulses on lead 159 
cause the bits of that sample component to be shifted to MSE update 
circuit 170 via lead 115 in synchronism with the bits of coefficient 
component c.sub.i (j) on lead 112. (Multiplier 123 is inactive at this 
time and ignores the signals on leads 112 and 115.) The bits of 
remodulated error component e.sub.j-l, now resident in remodulator 37 
(FIG. 1), are serially fed into MSE circuit 170 via lead 58 in synchronism 
with the coefficient and sample components. The value of .alpha. is 
permanently stored in circuit 170. The latter is thus provided with all 
the signals needed to subtract .alpha.e.sub.j-l r.sub.j-i-l from each 
incoming c.sub.i (j) per Eq. (3), concomitant with the formation of signal 
component q.sub.j. A circuit similar to circuit 170, comprising the whole 
of update unit 121 (FIG. 2), subtracts .alpha.e.sub.j-l r.sub.j-i-l from 
each c.sub.i (j), per Eq. (4). 
There is negligible delay in MSE circuit 170, the output bits thereof being 
extended, lowest-order bit first, to tap leakage circuit 180 via lead 
172--again in synchronism with the shift pulses on lead 159. MSE circuit 
170 is readily realized with standard arithmetic circuitry. It thus need 
not be described in further detail. 
Coefficient components c.sub.i (j) and c.sub.i (j) are illustratively 
represented in two's complement notation, with the highest-order bit being 
the sign bit--"0" for positive and "1" for negative. Reducing the 
magnitude of a coefficient component by .alpha..mu. in accordance with the 
invention means subtracting that amount from the binary word which 
represents that component if the latter has a positive value and adding 
that amount to the binary word if the component has a negative value. In 
the present illustrative embodiment, the magnitude .alpha..mu. is equal to 
the value represented by the least significant coefficient component bit. 
Thus, implementation of the invention requires tap leakage circuit 180 to 
add or subtract a binary "1" from each coefficient component received from 
MSE circuit 170, depending on the sign of the component. 
The procedure followed in tap leakage circuit 180 to subtract (add) a 
binary "1" from an incoming coefficient component is as follows: As long 
as the incoming bits are "0" ("1"), they are inverted to "1" ("0"). The 
lowest order "1" ("0") in the word is inverted to "0" ("1"). All other 
bits are unchanged. 
Turning now to the operation of tap leakage circuit 180, it will be 
appreciated from the foregoing that the lowest-order coefficient component 
bit is always to be inverted. To this end, the above-mentioned load pulse 
on lead 158 provides the further function of clearing to "0" a one-bit 
delay 186 in tap leakage circuit 180, delay 186 being clocked from the 
pulses on shift lead 159. Inverter 188 provides on lead 192 an inverted 
version of the output of delay 186. Lead 192 is connected to one input of 
exclusive-OR gate 191. The incoming coefficient component bits on lead 172 
are applied to the other input of gate 191. Lead 192 initially carries a 
"1", so that, as desired, the lowest-order bit on lead 172 is inverted in 
gate 191. The output of gate 191 is provided on lead 118. 
The load pulse on lead 158 provides the further function of clocking the 
coefficient component sign bit, which first appears on output lead 161 of 
memory 153, into D-type sign flip-flop 181 of circuit 180. Assume that the 
sign bit is "0", indicating a positive coefficient component from which a 
binary "1" is to be subtracted. The output of flip-flop 181 is extended to 
one input of exclusive-OR gate 183 on lead 182. Since that lead carries a 
"0" throughout the updating of the coefficient component at hand, the 
output of exclusive-OR gate 183 on lead 184 is equal to the value of the 
current coefficient component bit on lead 172. 
Thus, if the lowest-order coefficient component bit on lead 172 is "1", a 
"1" will appear at the output of delay 186 when the second bit appears on 
lead 172, that "1" having been previously passed to lead 193 by OR gate 
185. Lead 192 thus carries a "0" and, as desired, the second bit passes 
through gate 191 uninverted. Moreover, since the output of delay 186 feeds 
back into its own input via lead 187 and OR gate 185, lead 192 continues 
to carry a "0" and all subsequent coefficient component bits similarly 
pass uninverted through gate 191. 
If, on the other hand, the lowest-order bit on lead 172 is "0", the output 
of delay 186 will be "0" when the second bit appears on lead 172. That 
bit, therefore, is also inverted in gate 191, as desired. Moreover, as 
long as the bits on lead 172 continue to be "0", they are similarly 
inverted by gate 191, as is the first "1" which appears on lead 172. 
Thereafter, however, lead 192 will again carry a "0" and, as before, all 
subsequent bits will pass through gate 191 uninverted. 
Circuit 180 operates in a complementary fashion to that described above to 
add a "1" to the words on lead 172 which represent negative coefficient 
components. 
Larger values of .alpha..mu. can be implemented with a structure similar to 
circuit 180 by allowing k bits on lead 172 to pass through gate 191 
undisturbed, while holding delay 186 in the "0" state. The value of 
.alpha..mu. thus realized is equal to the value of the least significant 
coefficient component bit multiplied by 2.sup.k. 
As with MSE circuit 170, there is negligible delay in tap leakage circuit 
180. Thus, overall, the bits of the partially updated c.sub.i (j)'s appear 
on output lead 118 of update unit 22 in synchronism with the bits coming 
in on lead 112. Coefficient update unit 121 operates similarly. Thus, the 
bits of a partially updated c.sub.i (j) appear on lead 117 in synchronism 
with the shift pulses on lead 159. These bits are gated into register 151 
of coefficient store 119 via twenty-four shift pulses provided from 
circuit 190 on lead 157. 
The bits of component r.sub.j-i-1 are still present at the output of memory 
104. These are extended in parallel form to one of the multibit data 
inputs of data selector 101 of store 113 via lead bundle 102. The present 
logic state of selection lead 108, which extends from circuit 190, 
indicates to selector 101 that the signal on lead bundle 102 is to be 
applied to the input of memory 104. That signal is now recirculated into 
memory 104 by a load pulse received from circuit 190 on lead 109. The load 
pulse also causes the next sample component in the memory queue, component 
r.sub.j-i, to be loaded into hold register 106. 
Another sequence of twenty-four shift pulses now appears on lead 159. The 
value that component c.sub.i (j) had prior to being partially updated, as 
just described, is still resident in hold register 156. Thus, the pulses 
on lead 159 cause the bits of c.sub.i (j) and r.sub.j-i to be serially 
shifted onto leads 112 and 115 from registers 156 and 106 in order for 
multiplier 123 to form the tap product c.sub.i (j)r.sub.j-i. (Coefficient 
update unit 122 is inactive at this time and ignores the signals on leads 
112 and 115.) 
Another load pulse now appears on lead 158, the whole process repeating for 
each successive c.sub.i (j)--and in update unit 121, each c.sub.i 
(j)--unit all of the tap products comprising q.sub.j have been formed and 
all the coefficient components partially updated. 
The remainder of the coefficient updating, which occurs concomitantly with 
the formation of q.sub.j, proceeds similarly, with MSE circuit 170 (and 
the corresponding circuit in update unit 121) repetitively receiving error 
component e.sub.j-1 along with each c.sub.i (j) and r.sub.j-i-1 (or 
c.sub.i (j) and r.sub.j-i-1 in the case of update unit 121) to generate 
the coefficient correction terms. Once q.sub.j has been formed and the 
coefficient components fully updated, the logic state of selection lead 
108 changes. Thereafter, in an early portion of the next, (j+1).sup.st, 
receiver symbol interval, memory 104 is pulsed via lead 109 once more. 
This operation causes the just-generated sample component, r.sub.j+1, 
previously shifted into hold register 103 from output lead 19 of delay 23 
(FIG. 1) to be read into the queue of memory 104. This newest sample 
component supplants the oldest sample component, which would have 
otherwise been recirculated into the memory from lead bundle 102. 
The present invention is illustrated herein in the context of a QAM data 
system. It will be appreciated, however, that the present tap leakage 
technique for fractionally-spaced equalizers is equally applicable to 
systems using other modulation techniques and, indeed, to baseband 
fractionally-spaced equalizers, as well. It is also applicable to other 
receiver structures, such as those in which the received signal is 
demodulated first and then equalized at baseband. Finally, there may be 
applications in which the present tap leakage technique is efficacious for 
baud, as well as fractionally-spaced, equalizers. 
Thus, although a specific application of the invention and specific 
circuitry embodying same are shown and described herein, various other 
arrangements embodying the principles of the invention may be devised by 
those skilled in the art without departing from their spirit and scope.