SMALLER MODULE BY STACKING

A module is described. The module includes two dies which are stacked over a top insulating layer of a PCB. When both dies are be connected to the PCB through a copper pillar, the top die has a taller interconnect and the bottom die has a shorter interconnect. To further reduce a height of the module, the bottom die and/or the top die may be placed into a cavity of the PCB and a bulk silicon layer of the top die may be grinded away.

TECHNICAL FIELD

The present invention generally relates to methods, systems and apparatuses for integrated circuit (IC) packages including a substrate having interconnection layers.

BACKGROUND

There is steady demand for the solid-state modules inside electronic products, such as cellular telephones, personal communication devices and portable computers, to be physically smaller. Limiting factors that affect the size and height of such a solid-state module include printed circuit boards (PCBs) and various components mounted to either or both sides of the PCBs, incorporated in the module package.

Module size reduction in the x and y directions (e.g., where x and y directions correspond to a width and a length of a module) is a driving factor in module design. The dies and passive components are mounted on a PCB top surface next to each other, resulting in a module with a given size (in x and y). The placement of the dies and passive components on the PCB top surface may thus become a bottleneck for reducing the overall module size reduction (in x and y directions).

For example, flip-chip dies, filters, and surface mount technology (SMT) components may be connected to a top surface of a PCB, in which case the height of the tallest SMT component must be accommodated by the overall height of the module containing the PCB. High Q inductors, in particular, tend to be taller than other electronic components mounted to a PCB, creating a barrier against overall module height reduction (in a z direction, where z corresponds to a height of a module).

In view of the above, one or more embodiments of the present disclosure provide a module with die stacking to reduce a size in the x and y directions, and to reduce the module height in the z direction at the same time.

SUMMARY

A module is disclosed, in accordance with one or more illustrative embodiments. In some embodiments, the module includes a printed circuit board (PCB) including a plurality of metal layers. In some embodiments, a first metal layer of the plurality of metal layers is disposed on a top insulating layer of the PCB. In some embodiments, the module includes a first die electrically and/or mechanically coupled to the PCB by a first flip-chip mounting. In some embodiments, the PCB defines a cavity with a second metal layer of the plurality of metal layers disposed on a bottom surface of the cavity. In some embodiments, the module includes a second die electrically and/or mechanically coupled to the bottom surface of the PCB cavity by a second flip-chip mounting. In some embodiments, at least a portion of the second die is disposed between the first die and the PCB such that the first die is stacked over the second die. In some embodiments, the first die is separated from the second die by a gap. In some embodiments, a height of the first flip-chip mounting is taller than a height of the second flip-chip mounting. In some embodiments, at least two opposing ends of the first die extend beyond the second die.

In some embodiments, the first flip-chip mounting mechanically supports the at least two opposing ends of the first die. In some embodiments, the module can may include one or more component electrically coupled to the first metal layer. In some embodiments, the module includes a molding compound formed over the component, the second die, and the top insulating layer of the PCB.

In some embodiments, the first die may be flip-chip mounted to the second metal layer of the plurality of metal layers at the bottom surface of the cavity. In some embodiments, the cavity may be formed through one or more intermediary metal layers, to further increase the depth of the cavity thus reducing the standoff height of the die stack above the PCB surface. In some embodiments, the flip-chip mounting may include solder bumps and/or copper pillars on the surface of the cavity and/or the top insulating layer of the PCB.

In some embodiments, the first die and the second die may be flip-chip mounted to the first metal layer on the top insulating layer of the PCB.

In some embodiments, the module may include an interposer. The interposer may be coupled between the top insulating layer of the PCB and one or more of the first die and the second die. Both the first die and the second die may be flip-chip mounted to the interposer. In some embodiments, the module may include a second molding compound. The second molding compound may enclose the flip-chip mounting of the second die. In some embodiments, the second molding compound includes conductive vias through all or a portion for the flip-chip mounting of the first die. In some embodiments, the second molding compound encloses the second die.

In some embodiments, the molding compound is over the first die. In some embodiments, the molding compound is around the first die, such that a top surface of the first die is exposed. A top surface of the SMT component may be disposed below the first die when the molding compound is not over the top surface of the first die. The top surface of the first die may be exposed by grinding the molding compound thereby reducing the height of the module. In some embodiments, the interposer may be coupled between the bottom surface of the PCB cavity and both of the first die and the second die.

In some embodiments, the flip-chip mounting of the first die includes copper pillars. In some embodiments, the flip-chip mounting of the second die includes nickel bumps. The copper pillars may be taller than the nickel bumps.

In some embodiments, the module includes a third die in addition to the first die and the second die. Similar to the second die, the third die may be disposed between the first die and the PCB.

In some embodiments, the second die includes a bank of silicon capacitors or an integrated passive device.

In some embodiments, the PCB includes a bottom insulating layer disposed opposite to the top insulating layer. The module may include ball grid array (BGA) balls coupled to the bottom surface.

A module is disclosed, in accordance with one or more illustrative embodiments. In some embodiments, the module includes a printed circuit board (PCB) including a plurality of metal layers. In some embodiments, the PCB defines a cavity. In some embodiments, a first metal layer of the plurality of metal layers is disposed on a top insulating layer of the PCB. In some embodiments, the module includes a first die electrically coupled to the first layer of the PCB by a first wire-bond. In some embodiments, the module includes a second die electrically and/or mechanically coupled to the bottom surface of a PCB cavity by a flip-chip mounting. In some embodiments, at least a portion of the second die is disposed between the first die and the PCB such that the first die is stacked over the second die. In some embodiments, the backside of the first die is attached to the backside of the second die by a first die attach film. In some embodiments, the first die is mechanically supported by the die attach film. In some embodiments, the module may include one or more components electrically coupled to the first metal layer. In some embodiments, the module includes a molding compound formed over the component, the second die, and the top insulating layer of the PCB.

In some embodiments, the second die is electrically coupled to the first metal layer by a wire-bond. The second die may be attached to the bottom surface of a PCB cavity by a second die attach film which mechanically supports the second die. The backside of the first die may then be attached to the face of the second die by the first die attach film. At least one end of the second die may extend beyond the first die for forming the second wire-bond.

A module is disclosed, in accordance with one or more illustrative embodiments. In some embodiments, the module includes a printed circuit board (PCB) including a plurality of metal layers. In some embodiments, a first metal layer of the plurality of metal layers is disposed on a top insulating layer of the PCB. In some embodiments, the module includes a first die electrically coupled to the PCB by a first flip-chip mounting between the first die and the first metal layer. In some embodiments, the module includes a second die electrically coupled to the first die by a second flip-chip mounting between a face of the second die and a face of the first die. In some embodiments, at least a portion of the second die is disposed between the first die and the PCB such that the first die is stacked over the second die. In some embodiments, a height of the first flip-chip mounting is taller than a height of the second flip-chip mounting. In some embodiments, the module may include one or more component electrically coupled to the first metal layer. In some embodiments, the module includes a molding compound formed over the component, the second die, and the top surface of the PCB.

In some embodiments, the molding compound is over the first die. In some embodiments, the molding compound is around the first die. A top surface of the SMT component may be disposed below a top surface of the first die. The top surface of the first die may then be exposed such that the molding compound is not over the top surface of the first die for reducing a height of the module. The top surface of the first die may be exposed by grinding the molding compound. In some embodiments, the first die may be flip-chip mounted to the bottom surface of the PCB cavity.

DETAILED DESCRIPTION OF THE INVENTION

It is noted herein “coupled” may mean one or more of communicatively coupled, electrically coupled, and/or physically coupled for the purposes of the present disclosure. As used herein, coupled may refer to a direct or indirect coupling. An indirect coupling may refer to a connection via another function element. A direct coupling may refer to a connection without intermediary functional elements. It is noted herein that by being “coupled between”, it may be understood to be relative to movement or flow of a signal between two or more components, and may additionally include intervening components therein. An electrical coupling or electrical connection may refer to the ability of electrical energy to flow between components. The terms electrical coupling and electrical connection may be used interchangeably. A mechanical coupling or mechanical attachment may refer to a physical support of components. The terms mechanical coupling and mechanical attachment may be used interchangeably. In some instances, the mechanical attachment is provided to support the component while a molding compound is formed over, around, and/or under the component. Once the molding compound is set, the molding compound in combination with the mechanical attachment may provide a desired level of a rigidity to the component.

Reference will now be made in detail to the subject matter disclosed, which is illustrated in the accompanying drawings. Embodiments of the present disclosure are generally directed to stacking dies or other components on the top surface of the PCB for floorplan optimization. A smaller package size in the x and y directions may be achieved by stacking the dies. The stacked dies may also be placed into a cavity of the PCB to further reduce the package height. As used herein, stacking may refer to placing a die above another die relative to a printed circuit board.

U.S. Pat. No. 10,827,617, titled “Printed circuit board with cavity”, naming Dingyou Zhang, Nitesh Kumbhat, Li Sun, Sarah Haney, and Chang Kyu Choi as inventors, is incorporated herein by reference in the entirety.

Referring generally toFIGS.1A-2L, a module100is described, in accordance with one or more embodiments of the present disclosure. The module100may generally include a first die which is stacked above a second die on a printed circuit board, an interposer, or inside a substrate cavity, such that at least a portion of the second die is disposed between the first die and the PCB. An overall area of the floorplan of the PCB may be reduced when the dies are stacked over the top side of the PCB in the vertical direction. By arranging the module100as described herein, the size of the module100in the x and y directions may be reduced by up to 30 percent. In some instances, stacking the die in the vertical direction may increase the height of the module. For instance, the height of the module may be increased depending upon the relative height of the stacked dies and one or more surface mount technology (SMT) components. Embodiments of the present disclosure are also directed to minimizing the increase in height due to the die stacking. The overall height may thus remain the same or also be reduced. With the structure of the module100, electrical performance may also be improved as a result of the potential shortened critical path length between functional dies. Improving the electrical performance may lead to reduced resistive-capacitive (RC) delay. Thermal performance may also be improved by stacking one flip chip die, which acts as a thermal spreader, on top of another thermal sensitive die. Thermal performance may also be improved by reducing a thermal path when placing a thermal sensitive die inside a substrate cavity.

In embodiments, the module100may be also be referred to as a radio frequency (RF) front-end module (FEM). The module100may be molded and EMI shielded for RF applications. The module100may be used in a number of radio frequency (RF) applications, such as, but not limited to, a radio frequency (RF) module of a mobile phone or another communication device. In such RF applications, designs of the module100may be sensitive to size and cost requirements. The module100may further include one or more filters, amplifiers, oscillators, and the like. In some instances, the RF front end is placed onto the motherboard of a communication device. The RF front end may be placed on the motherboard for filtering or amplifying a signal of the communication device. It is further contemplated that the module100may include applications other than as an RF module or an RF front end.

The module100may include one or more components, such as, but not limited to, a printed circuit board (PCB)102, a die104, a die106, a surface-mounted technology (SMT)108, a die110, ball-grid array (BGA)112, and/or a molding compound113. The overall height for the module100may be determined by the PCB102thickness, the BGA112height, the die104thickness, the die106thickness, among other factors. The module100may also include interconnects118, solder joints120, interconnects122, solder joints124, cavity126, wire bonds128, wire bonds130, die attach film132, die attach film134, interposers136, molding compound113, and/or intermediary molding compound138.

The PCB102may include pads for coupling the die104and the die106. For example, the metal layers114of the PCB102may be patterned to have solder bumps landed on a top surface of the PCB102and/or in the cavity126. The solder bumps may be melted and wetted to the metal layers of the PCB during reflow, followed by cooling to form a solid joint with one or more of the interconnects118or the interconnects122.

As used herein, a top surface of the PCB102may generally refer to a top insulating layer of the PCB. For example, see the top insulating layer depicted inFIG.1D. Although not labelled, the exemplary configurations depicted inFIGS.1A-1Nmay similarly include the top insulating layer150. The top insulating layer150may also be referred to as a substrate layer. The top insulating layer150may generally include a low conductivity to electricity. The top insulating layer150may be formed by any electrically insulating material compatible with fabrication of printed circuit boards, such as, but not limited to, a resin material (e.g., epoxy (e.g., FR-4)), and the like. The top insulating layer150may include a metal layer (e.g., metal layer114a) disposed on the top insulating layer150. The metal layer disposed on the top insulating layer150may also be referred to as a trace. The metal layer may be formed from any electrically conductive material compatible with fabrication of printed circuit boards, such as, but not limited to, copper, gold, silver, aluminum, and the like. The metal layer may generally be fabricated by any printed circuit board fabrication process. The printed circuit board102may also include multiple layers of the metal layers and/or multiple layers of the insulating layers, such that the printed circuit board102may be considered a multilayer PCB. In embodiments, the PCB defines a cavity which may include a surface. As used herein, a surface of the cavity may similarly refer to an insulating layer of the PCB102which is lower than the top insulating layer.

The PCB102may be double-sided, including pads for coupling a die to a top surface of the PCB102and a bottom surface of the PCB102. The PCB102may be a multilayer PCB including metal layers114separated by insulating layers. For example, the PCB102is depicted as including nine of the metal layers, although this is not intended to be limiting. The metal layers114may be formed of any electrically conductive material compatible with fabrication of printed circuit boards. For example, the material may include, but is not limited to, copper (Cu), gold (Au), silver (Ag) and/or aluminum (AI). The insulating layers may be formed of any electrically insulating material compatible with fabrication of printed circuit boards, such as prepreg material and/or resin-based dielectric material, for example. The metal layers114may be patterned to include circuitry between metal patterns (e.g., pads, trace, etc.) on the top surface of the PCB, metal patterns on the bottom surface of the PCB, and the BGA112. For example, a top metal layer may connect to the die104or the die106by one or more copper pillars, solder bumps, wire bonds, and/or die attach films. By way of another example, a second metal layer may connect to the die104or the die106by one or more copper pillars, solder bumps, wire bonds, and/or die attach films, where the PCB includes a cavity. As used herein, cavity may refer to a hole cutout from a surface of the PCB through to one or more lower metal layers. The PCB may additionally include the vias116, and the like. The vias116may provide interconnects between the metal layers114. The vias116and the metal layers114may then provide routings between one or more of the die104, the die106, the SMT108, the die110, and/or the BGA112. As may be understood, the various vias116and the metal layers114depicted are not intended to be limiting and are merely illustrative.

The die106may generally be disposed between the die104and the top surface of the printed circuit board (PCB)102. In this regard, the die104may be stacked above the die106. Stacking the die104above the die106may be advantageous in reducing the size of the module100in the x and y directions.

The die104and the die106may be referred to herein as a die, although this is not intended to be limiting. For example, the die104and the die106may include, but are not limited to, CMOS die, a silicon on insulator (SOI) die, an integrated passive device (IPD) die, a filter die, a bank of silicon capacitors, a discrete passive component, and the like. As used herein, passive may refer to an inductor, a resistor, a capacitor, and the like. The die may be selected from any of the above to achieve a desired functionality. A die thickness may be between 100 micrometers and 150 micrometers. The die106may generally be stacked over the die104. The module100may further include the SMT108on the top surface of the PCB102. The SMT108may include an inductor. The inductor may be taller than the die104and/or the die106. For example, the inductor may include a component height (in the z-direction) of about 220 micrometers up to 320 micrometers, typically 250 micrometers for example. By stacking the die106on the die104, the module100may advantageously use space above the die106which would otherwise be filled with molding compound, due to the height requirements of the SMT.

The PCB102may additionally include one or more of the die110attached to the bottom surface of the PCB102. In this regard, the PCB102may be referred to as a double-sided PCB. In the depicted embodiment, the module100is a ball grid array (BGA) component. For example, the module100may include an array of solder balls, indicated by representative solder ball. The array of solder balls may be attached to a bottom surface of the PCB102. The BGA112serves as the input/output (I/O) for the module100, such as for communicating signals to and from a motherboard of a cell phone to the module100. Alternatively, the module100may be a land grid array (LGA) component (which does not include the array of solder balls), or various other types of components, without departing from the scope of the present teachings.

The module100also includes the molding compound113. The molding compound113may be formed of a reinforced or non-reinforced epoxy resin, an epoxy molding compound (EMC), and the like. The molding compound113may be applied using any process compatible with fabrication of semiconductor devices. For example, the molding compound113may be applied by one or more of as injection molding, transfer molding, and/or compression molding. The molding compound113generally protects the electronic components (e.g., the PCB102, the die104, the die106, the SMT108, etc.). The molding compound113may also provide additional structural support to the module100. The molding compound113may also hermetically seal the electronic components and other circuitry within the module100. The hermetic seal may protect against environmental elements, such as temperature and moisture. The molding compound113may be formed over the SMT108, the die106, and the top surface of the PCB102. In some instances, the molding compound113is also formed over the die104. In other instances, the molding compound113is formed around a portion of the die104, with a top surface of the die104being exposed.

Optionally, grinding may be performed reduce a height of the die104. In some instances, the top die may extend above a surface-mounted technology (SMT)108component. The overall height for this module is then limited based on the top die. By grinding a portion of the die, the module height may be reduced. For example, the die104may be exposed where the die104is flip chip mounted to the PCB such that the back of the die104is exposed at the top surface of the module. Additionally, the top surface of the die104may be exposed where the SMT108is disposed below the top surface of the die104such that the top surface of the die104may be exposed by grinding the molding compound113without grinding the SMT108. Grinding the molding compound113to expose the top surface of the die104may be advantageous in reducing the overall height of the module100, as compared to a module which has not been grinded down below the top surface of the die104. The grinding may be performed for height management to reduce the overall height of the module. Where the module is grinded to expose the die, the grinding may include grinding a portion of the die. For example, a silicon bulk found on the back side of the die104may be grinded away. The grinding may remove between 30 to 45 micrometers. This is based on the die thickness before grinding, so that the die thickness after grinding will be reduced to a range of 130 micrometers to 205 micrometers. The benefit of grinding the die104is that a thicker die may be easier to pick and place onto the PCB102prior to grinding while also including a reduced height after grinding.

To be exposed may mean that the surface is not covered by the molding compound113, but may or may not be covered by an EMI shield. For example, after the components are placed, the molding compound113may be over-molded, followed by grinding to a given height, followed by EMI shielding. The EMI shielding is not depicted herein.

The module100may include a marking (not depicted), such as a laser marking or ink marking. The laser marking may include letters, numbers, or characters visually indicating the series marking with a lot, date, assembly side, or machine-readable barcode and the like. The laser marking may be included on the molding surface area. The laser marking may have a certain depth. For example, a laser marking depth may be 40 micrometers. If the laser marking is performed on the molding surface, for example, there may be a minimum height requirement under that molding surface. A clearance must be maintained from the top surface for the marking depth. In embodiments, the laser marking may also be performed on top surface of the die104which is exposed. By laser marking the die104, the minimum clearance requirement from the die surface may be shallower than the minimum clearance requirement from the molding surface when marking on the molding surface area. In this regard, the laser marking may be included in the silicon bulk of the die104. Including the laser marking in the silicon bulk helps reduce the overall height of the module. In embodiments, marking on die104may be done by ink marking. In this regard, there may be no height clearance requirement for marking.

Although not depicted, the module100may include an external shield formed over the molding compound113. The external shield may provide additional protection from environmental stress, as well as electromagnetic shielding from external sources. The external shield may be formed of a conductive material (e.g., metal). For example, the material may include, but is not limited to, stainless steel, copper (Cu), silver (Ag), gold (Au), and/or aluminum (AI). By way of another example, the material may include a combination of conductive and non-conductive materials, without departing from the present teachings.

In embodiments, the module100include one or more interconnects118(e.g., copper pillars) and one or more solder joints120. The interconnects118may be formed of a copper material in a pillar shape and the solder joint120may be formed of a solder joint. The interconnect118together with the solder joint120may be referred to as a copper pillar structure and/or as a flip-chip mounting for the die104. The height of the flip-chip mounting may be determined by measuring the height of the interconnect118together with the height of the solder joint120. The interconnect118and solder joint120together may also be referred to herein as a taller pillar structure. In embodiments, the module100includes one or more wire bonds128. The interconnects118, solder joints120, and/or the wire bonds128may generally provide an electrical connection for the die104. The interconnects118and the solder joints120may provide a mechanical attachment for the die104. In some instances, the interconnects118and the solder joints120provide both a mechanical attachment and an electrical connection. In some instances, the interconnects118and the solder joints120serve as mechanical attachment but carry no electrical signals.

In embodiments, the module100includes one or more interconnects122and one or more solder joints124. The interconnects122may be formed of a copper material in a pillar shape. The interconnect122together with the solder joint124may be referred to as a copper pillar structure. The interconnect122and the solder joint124together may also be referred to herein as a shorter pillar structure and/or as a flip-chip mounting for the die106. Similarly, the height of the flip-chip mounting may be determined by measuring the height of the interconnect122together with the height of the solder joint124. In embodiments, the module100includes interconnects122and one or more solder joints124. The interconnect122may be a under bump metallization (UBM) mainly formed of a nickel material, such that the interconnect122and solder joint124together may be referred to as a nickel bump. The interconnect122and the solder joint124together may also be referred to herein as a shorter bump structure. In embodiments, the module100includes one or more wire bonds130. The interconnects122, solder joints124, and/or the wire bonds130may generally provide an electrical connection for the die106. The interconnect122and the solder joints124may provide a mechanical attachment for the die106. In some instances, the interconnects122and the solder joints124provide both a mechanical attachment and an electrical connection. In some instances, the interconnects122and the solder joints124serve as mechanical attachment but carry no electrical signals.

The relative heights of the flip-chip mounting for the die104and the flip-chip mounting for the die106are now described. In some embodiments, the flip-chip mounting for the die104may be taller than the flip-chip mounting for the die106. The height for the flip-chip mounting may be determined relative to a respective mounting surface. Here, the respective mounting surface may refer to a specific metal layer to which the die104and/or the die106are flip-chip mounted. Providing the die104with a taller flip-chip mounting may allow the die104to be disposed over the die106. In some embodiments, the flip-chip mounting for the die104may be taller than the flip-chip mounting for the die106when the die104is flip-chip mounted to a higher metal layer than the die106. For example,FIG.1Adepicts the die104flip-chip mounted to the metal layer114aof the PCB102by the interconnect118and the solder joint120.FIG.1Afurther depicts the die106flip-chip mounted to the metal layer114b(e.g., PCB pad140) of the PCB102by the interconnect118and the solder joint120. The interconnect118and the solder joint120have a first height, when measured from the metal layer114a. The interconnect122and the solder joint124have a second height, when measured from the metal layer114b. As depicted, the first height is taller than the second height. Thus, the die104may be disposed over the die106due to the relative heights of the flip-chip mountings.

The interconnect118and solder joint120together and the interconnect122and solder joint124together may be substantially similar in function. The various interconnects and solder joints may provide an electrical or mechanical connection between the dies and the PCB102. One difference between the interconnect118and solder joint120together and the interconnect122and solder joint124together is that the total height of the interconnect122and solder joint124together is significantly shorter than the total height of the interconnect118and solder joint120together. For example, the interconnect118may be a copper pillar with a height between 50 and 100 micrometers and the solder joint120may be a solder joint with a height around 20 micrometers. By way of another example, the interconnect122may be a nickel UBM with a height of 3 micrometers, and the solder joint124may be a solder joints with a height around 15 micrometers. By way of another example, the interconnect122may be a copper pillar with a height of 10 micrometers and the solder joint124may be a solder joint with a height around 15 micrometers. In some instances, PCB pad140thickness under the solder joint124may be thinner than PCB pad142thickness under the solder joint120, such as 5 micrometers thinner, for example. The smaller pad thickness may be induced by etching during the PCB cavity formation process, or the like. The smaller pad thickness may be advantageous for further reducing the standoff height of the die106.

The use of the nickel bump may be advantageous in achieving a bump size which is sufficiently small for reducing the standoff height of the die106. Reducing the standoff height may be particularly advantageous where the die104is stacked above the die106. The solder bumps may be wetted to pads of the PCB102. As may be understood, the pads may be formed by selective plating or etching the metal layers during fabrication of the PCB102. Other techniques for fabricating the metal layers to form the pads including other selective additive processes and etching processes may be incorporated without departing from the scope of the present teachings, as would be apparent to one skilled in the art.

The die104and the die106may each be rectangular. By being rectangular, each die includes two opposing ends. The opposing ends may also be referred to herein as opposing sides, lateral sides, and the like. In embodiments, the opposing ends of the die104may or may not extend beyond the opposing ends of the die104. Where the opposing ends of the die104extend beyond the opposing ends of the die106, the die104may be considered to be wider than the die106. For example, the die104include an end146aand an end146b. The end146amay oppose the end146b(e.g., opposing ends146). The die106may include an end148aand an end148b. The end148amay oppose the end148b(e.g., opposing ends148). As depicted inFIG.1A, the opposing ends146of the die104may extend beyond the opposing ends148of the die106. Similarly, the die104may be narrower than the die106. The opposing ends146may not extend beyond the opposing ends148when the die104is narrower than the die106(e.g., seeFIG.1EorFIG.2E). The die104may also be wider than the die106while also not including the opposing ends146which extend beyond the opposing ends148(e.g., seeFIG.1D or2F).

In embodiments, each of the opposing ends for each die is supported by the pillars. By being supported by the pillars, the die may be mechanically supported and may stand on the PCB stably. Furthermore, each of the two ends are not intended to be limited to a single pillar, but may include a number of pillars per each opposing end. It is further contemplated the dies may be supported on more than two ends, although this is not intended to be limiting. In embodiments, the die may be supported by the die attach films and then electrically connected by the wire bonding.

When assembling the stacked dies, the PCB102may be loaded into an assembly machine and held in place by a vacuum chuck. A pick and place machine may then place the dies and other components onto the surface of the PCB. When the module100includes the stacked dies, the pick and place machine may place the lowest die first and then place the upper die. In this regard, the pick and place machine require a specific sequencing of placement to achieve the stacked configuration. The distance between the outer most pad under the solder joint124of the die106and its neighboring pad under the solder joint120of the die104may be selected based on PCB manufacturing tolerance and/or placement accuracy tolerance.

In embodiments, the die104and the die106may be separated by a gap144. The gap144may comprise an EMC molding material or an underfill material. Such material may be important for improving a reliability of the module. The gap144may generally include any dimension, such as, but not limited to, 35 micrometers. For example, the die104is depicted as being separated from the106by the gap144inFIGS.1A-1C,1F-1H, and1K-1N.

In embodiments, the die104may be attached to the backside of the die106using die attach film. The die attach film may be an adhesive film having a thickness of between 5 micrometers and 10 micrometers.

In embodiments, the PCB102may define a cavity126. The cavity126may be formed in the top side of a PCB102such that the top surface is not flat across the entire PCB102. As may be understood, the cavity126may be formed from the PCB102by any suitable process, such as etching, laser ablation, or using patternable photosensitive materials. The depth of the cavity126may be selected based on a distance to the metal layers114below the top surface. For example, the depth of the cavity126may be selected to expose the second metal layer114b. Exposing the metal layer114bmay be referred to as one-layer cavity depth. Higher layer cavity depths are contemplated but are not depicted herein, such as two-layer cavity depths and three-layer cavity depths. When the standoff height of the die104is a limiting factor with respect to the size of the module100, the die106may be mechanically attached within the cavity126. The die106may be mechanically attached within the cavity126by the interconnect122and the solder joint124or the die attach film134. Attaching the die106within the cavity126lowers the standoff height of the die106, as compared to attaching the die106on the top surface of the PCB102. Where the die104is stacked above the die106and the die106is mechanically attached within the cavity126, the standoff height of the die104may also be reduced. Reducing the standoff height of the die104may be beneficial in reducing the overall height of the module100. In embodiments, the die104may also be attached within the cavity126by the interconnect118and solder joint120, although this is not intended to be limiting. The die104may be attached to the top surface of the PCB102by the interconnect118while the die106is attached within the cavity126, for achieving the reduced module height. The die104may be attached to the top surface of the die106by the die attach film132while the die106is attached within the cavity126, for achieving the reduced module height. The reduction in height of the module100may correspond to the cavity depth, which may be about 37 micrometers, for example. It is further contemplated the cavity depth may be up to 50 micrometer or more.

In embodiments, the module100may include an interposer136. As used herein, interposer may refer to an electrical interface between one or more components. The interposer136may include metal layers and insulating layers (not depicted). The metal layers of the interposer136may provide routing among the PCB102, the die104, and the die106. The interposer136may be beneficial in increasing the I/O density for routing purposes. For example, the interposer136may have a finer line width and space, as compared to the PCB102. The interposer136may be fabricated by redistribution layer (RDL) process, wafer level back-end-of-line process, and the like. Although the module100is described as including the interposer136, this is not intended to be limiting.

Each of the die104and the die106may include a face. As used herein, a face may refer to a surface of a die. A face may include electrical interconnects for electrically coupling by pillars, bumps or wire bonds. Each of the die104and the die106may also include a back which is oppositely disposed to the face. The face of the dies may generally include an electrical connection between the dies and one or more components of the module100. In some instances, the face or the back may include a mechanical attachment between the dies and one or more components of the module100. The die104is thus electrically connected and mechanically attached to one or more components of the module100. In some instances, the die104is electrically connected and mechanically attached to a first component, such as the top surface of the PCB102, the cavity126, the interposer136. In some instances, the die104is electrically connected to a first component, such as the die106, and electrically connected and mechanically attached to a second component, such as the top surface of the PCB102. Similar to the die104, the die106is electrically connected and/or mechanically attached to one or more components of the module100. In some instances, the die106is electrically connected and mechanically attached to a first component, such as the top surface of the PCB102, the bottom surface of the cavity126, the interposer136, or the die104. In some instances, the die106is mechanically attached to a first component, such as the metal layer114binside the cavity126, and electrically connected to a second component, such as the metal layer114aas the top surface of the PCB102.

A number of permutations for the electrical connections and mechanical attachments of the die104and the die106are now described. As may be understood, the various depictions of the permutations are not intended to be limiting and are merely provided for illustration.

In embodiments, the die104may be electrically connected and mechanically attached to the metal layers114by a flip-chip mounting. The module100may include one or more interconnects118and one or more solder joints120. The interconnect118and the solder joints120may electrically connect and mechanically attach the die104to the one or more of the metal layers114of the PCB102. Such arrangement may also be referred to herein as a flip-chip mounting between the die104and the PCB102. The die104may be flip-chip mounted to the metal layer114aon the top surface of the PCB or the metal layer114bbelow the metal layer114a(i.e., within the cavity126). For example,FIG.1A,FIG.1C, andFIGS.1F-1Idepict a flip-chip mounting between the die104and the metal layer114adisposed on the top surface of the PCB102. By way of another example,FIG.1Bdepicts a flip-chip mounting between the die104and the metal layer114bdisposed in the cavity126of the PCB102. As used herein, “flip-chip mounting” may refer to connecting a face of a die to another component by one or more interconnects, copper pillars, and/or one or more solder joints.

In embodiments, the die104may be electrically connected to the metal layers114by wire bonding and mechanically attached to the die106. The module100may include the wire-bonds128and the die attach film132. The wire-bonds128may electrically connect the die104onto the metal layer114aof the top surface of the PCB102. The die attach film132may mechanically attach the die104to the die106. For example,FIGS.1D-1Edepict the wire-bonds128and die attach film132as described.

In embodiments, the die104may be electrically connected and mechanically attached to the interposer136. The module100may include the interconnect118electrically connecting and mechanically attaching the die104to the interposer136. The interconnects118may be pre-existing pillars which are formed on the interposer136prior to molding to form the connection to the die104. The die104may be attached to the surface of the second molding compound138through a solder or flux printing process. The interconnect118may be formed by through mold vias. The interconnects118may be connected onto pads of the interposer136. The interposer136may then be electrically connected and mechanically attached to the metal layer114of the PCB and interconnect the die104to the PCB102. For example,FIGS.1K-1Ndepict the die104connected to the interposer136as described.

In embodiments, the die106may be electrically connected and mechanically attached to the metal layers114by a flip-chip mounting. The module100may include one or more interconnects122(e.g., pillars or UBM) and one or more solder joints124. The interconnects122and the solder joint124may electrically connect and mechanically attach the die106to the one or more of the metal layers114of the PCB102. Such arrangement may also be referred to herein as a flip-chip mounting between the die106and the PCB102. The die106may be flip-chip mounted to the metal layer114aon the top surface of the PCB or the metal layer114bbelow the metal layer114a(i.e., within the cavity126). For example,FIGS.1F-1Gdepict a flip-chip mounting between the die106and the metal layer114adisposed on the top surface of the PCB102. By way of another example,FIGS.1A-1Ddepicts a flip-chip mounting between the die106and the metal layer114bdisposed in the cavity126of the PCB102.

In embodiments, the die106may be electrically connected to the metal layers114by wire bonding and mechanically attached to the PCB102by a die attach film. The module100may include one or more wire-bonds130and a die attach film134. The wire-bonds130may electrically connect the die104to the metal layer114aon the top surface of the PCB102. The die attach film134may mechanically attach the die104to the top surface of the PCB102or mechanically attach the die106within the cavity126. For example,FIG.1E, depicts the die attach film134mechanically attaching the die106within the cavity126with the wire bonds130electrically connecting to the metal layer114aof the top surface of the PCB. In this example, the ends148of the die106extend beyond the ends146of the die104for receiving the wire bonds130. In some embodiments, the die104includes one or more of the ends148which extend beyond the die104for receiving the wire bonds130.

In embodiments, the die106may be electrically connected and mechanically attached to the die104. The die106may be electrically connected and mechanically attached to the die104by a flip-chip mounting. The module100may include the interconnects122(e.g., pillar or UBM) and the solder joint124between the die104and the die106. In this configuration, the die104may include mechanical support and electrical interconnects (e.g., signal paths) between the die106and the PCB102. The die104may then act as an interconnect to the PCB102for the die106. For example,FIGS.1H-1Jdepict the flip-chip mounting between the die106and the die104. The flip-chip mounting between the die106and the die104may also be referred to as a face-to-face connection, in which the face of the die106is oriented towards the face of the die104. Providing the face-to-face connection may provide a beneficial electrical performance for functions, because the electrical path between the die104and the die106is shorter.

In embodiments, the die106may be electrically connected and mechanically attached to the interposer136. The die106may be electrically connected and mechanically attached to the interposer136by the interconnect122(e.g., pillar or UBM) and the solder joints124. The interposer136may then be electrically connected and mechanically attached to the metal layer114of the PCB and interconnect the die106to the PCB102. For example,FIGS.1K-1Ndepict the die106connected to the interposer136as described.

One or more exemplary configurations of the module100are now described. As may be understood, the various numerical ranges of the exemplary ranges are not intended to be limiting and are merely provided for illustration.

Referring now in particular toFIG.1A, an exemplary module100ais described. The exemplary module100aincludes die stacking with the die106coupled within the cavity126of the PCB. The die106is flip-chip mounted into the cavity126. The die104is then flip-chip mounted onto the top surface of the PCB102. The solder joints120and the solder joints124may then be formed at the same time by reflow at once along with other dies and components placed on PCB top surface (i.e., the SMT108), thereby not introducing additional reflow steps nor extra assembly cost. The die104is connected by the interconnects118along with solder joints120and the die106is connected by the interconnects122along with solder joints124. To realize this configuration, the total height of interconnect122and solder joint124are shorter than the total height of interconnect118and solder joint120. For example, interconnect122and solder joint124together may be shorter copper pillars or nickel bumps and interconnect118and solder joint120together may be taller copper pillars. The die104and the die106may be fully or partially overlapped (seeFIGS.2A-2D, for example). The die106may include multiple dies, bank of Si capacitors, IPD, or any combination therein. A shorter bump structure (for example, 3 micrometers of nickel and 15 micrometer of plated solder) along with 70 micrometer bump diameter and 110 micrometer bump pitch may be used for the interconnects122and solder joints124of the die106. A taller bump structure (for example, 80 micrometers of copper and 20 micrometers of plated solder) along with 70 micrometers bump diameter and 110 micrometer bump pitch may be used for the interconnects118and solder joints120of the die104. A depth for the cavity126may be around 37 micrometers. A distance between the outer most pad of the die106and its neighboring pad of the die104may be 155 micrometers or greater. A thickness for the die106may vary from 50 micrometers to 105 micrometers. A thickness for the die104may vary from 100 micrometers to 155 micrometers. The die104and the die106may include an airgap in between. The airgap may be filled with underfill or molding during one or more fabrication steps to form the gap144. The airgap may be around 35 micrometers, making it feasible for stacking the die104on the die106. The clearance between the top surface of the die104and the top surface of the molding compound may be around 30 micrometers.

Referring now in particular toFIG.1B, an exemplary module100bis described. The exemplary module100bincludes die stacking with the die104and the die106coupled within the cavity126. Notably, the die104of the exemplary module is coupled within the cavity126. For example, the die106is flip-chip mounted into the cavity126. The die104is then flip-chip mounted into the cavity126. The solder joint120and the solder joint124may then be formed at the same time through one reflow step along with other dies and components placed on PCB top surface (i.e., the SMT108), thereby not introducing additional reflow steps and extra assembly cost. The die104and the die106may be fully or partially overlapped (seeFIGS.2A-2D, for example). The die106may include multiple dies, bank of Si capacitors, IPD, or any combination therein. A shorter bump structure (for example, 3 micrometers of nickel and 15 micrometers of plated solder) along with 70 micrometers bump diameter and 110 micrometer bump pitch may be used for the interconnects122(e.g., pillars or UBM) and solder joints124of the die106. A taller bump structure (for example, 80 micrometers of copper and 20 micrometers of plated solder) along with 70 micrometers bump diameter and 110 micrometer bump pitch may be used for the interconnects118and solder joints120of the die104. A depth for the cavity126may be around 37 micrometers. A distance between the outer most pad of the die106and its neighboring pad of the die104may be 155 micrometers or greater. A thickness for the die106may vary from 50 micrometers to 105 micrometers. A thickness for the die104may vary from 100 micrometers to 155 micrometers. The die104and the die106may include an airgap in between which may be filled with underfill or molding. The airgap may be around 35 micrometers, making it feasible for stacking the die104on the die106. The clearance between the top surface of the die104and the top surface of the molding compound may be around 30 micrometers.

Referring now in particular toFIG.1C, an exemplary module100cis described. The exemplary module100cincludes die stacking with the die106coupled within the cavity126and a top surface of the die104exposed. The top surface of the die104is exposed and not covered by the molding compound113. The die106is flip-chip mounted into the cavity126. The die104is then flip-chip mounted onto the top surface of the PCB102. The solder joint120and the solder joint124may then be formed at the same time by one step reflow along with other dies and components placed on PCB top surface (i.e., the SMT108), thereby not introducing extra assembly cost. A one step reflow may refer to where all of the various joints are reflowed in a single step. The molding compound113may then be over molded and grinded to expose the die104. As used herein, over molding may refer to molding above a desired height. The over molding may then be ground to the desired height by the grinding. The die104and the die106may be fully or partially overlapped (seeFIGS.2A-2D, for example). The die106may include multiple dies, bank of Si capacitors, IPD, or any combination therein. A shorter bump structure (for example, 3 micrometers of nickel and 15 micrometers of plated solder) along with 70 micrometers bump diameter and 110 micrometer bump pitch may be used for the interconnect122(e.g., pillars or UBMs) and solder joints124of the die106. A taller bump structure (for example, 80 micrometers of copper and 20 micrometers of plated solder) along with 70 micrometers bump diameter and 110 micrometer bump pitch may be used for the interconnects118and solder joints120of the die104. A depth for the cavity126may be around 37 micrometers. A distance between the outer most pad of the die106and its neighboring pad of the die104may be 155 micrometers or greater. A thickness for the die106may vary from 50 micrometers to 105 micrometers. A thickness for the die104may vary from 160 micrometers to 250 micrometers before grinding, and may vary from 130 micrometers to 205 micrometers after grinding. The die104and the die106may include an airgap in between which may be filled with underfill or molding. The airgap may be around 35 micrometers, making it feasible for stacking the die104on the die106. The backside of the die104is exposed by grinding, which helps further reduce the height of the module100. In embodiments, the top surface of the die104may include a laser marking or ink marking.

Referring now in particular toFIG.1D, an exemplary module100dis described. The exemplary module100dincludes die stacking with interconnect122(e.g., pillars or UBMs) and solder joints124connecting the die106within the cavity126and wire bonds128connecting the die104with the PCB102. The die106is flip-chip mounted into the cavity126. The PCB102and the die106are then reflowed. The die104is then attached onto the die106using the die attach film132. The die104is then connected to the PCB102by the wire bonds128. The die106is thus electrically connected through the interconnect122and solder joints124while the die104is connected through the wire bonds128. Thus, the die104is stacked over the die106, the die104is connected to the PCB102by the wire bonds128, the die104is mechanically attached to the die106by the die attach film132, and the die106is connected inside cavity126of the PCB102by the interconnect122and solder joint124. The die104may be smaller than, bigger than, or of equal size to the die106(seeFIGS.2A,2H, for example). The die104may be multiple dies, bank of Si capacitors, IPD, or any combination therein. The die104and the die106may overlap as much as possible for the sake of module size reduction as well as ease in the wire bonding process. A shorter bump structure (for example, 3 micrometers of nickel and 15 micrometers of plated solder) along with 70 micrometers bump diameter and 110 micrometer bump pitch may be used for the interconnect122and the solder joints124sof the die106. A depth for the cavity126may be around 37 micrometers. A distance between the outer most pad of the die106and the outermost bond pad of the die104may be 170 micrometers or greater (from pad edge to pad edge). A thickness for the die106may vary from 50 micrometers to 150 micrometers. A thickness for the die104may vary from 50 micrometers to 100 micrometers. The clearance between the top surface of the die104and the top surface of the molding compound may be around 85 micrometers.

Referring now in particular toFIG.1E, an exemplary module100eis described. The exemplary module100eincludes die stacking with wire bonds130connecting the die106with the PCB102and wire bonds128connecting the die104with the PCB102. The exemplary module100eincludes the wire bonds130and the die attach film134. The die106is attached to metal layer114binside the substrate cavity126using the die attach film134. The die104is then attached onto the die106using the die attach film132. The die104and the die106are then connected to the metal layer114aon the top surface of PCB102by the wire bonds128and the wire bonds130. Thus, the die104is electrically connected to the PCB102by the wire bonds128, the die104is attached to the die106by the die attach film132, the die106is electrically connected to the PCB102by the wire bonds130, and the die106is attached to metal layer114bwithin the cavity126of the PCB102by the die attach film134. The die106is not fully covered by the die104(seeFIGS.2E-2G, for example) so that the wire bonds may be formed. The die104may be multiple dies, bank of Si capacitors, IPD, or any combination therein. A depth for the cavity126may be around 37 micrometers. A thickness for the die106may vary from 50 micrometers to 150 micrometers. A thickness for the die104may vary from 50 micrometers to 100 micrometers. The clearance between the top surface of the die104and the top surface of the molding compound113may be around 85 micrometers.

Referring now in particular toFIG.1F, an exemplary module100fis described. The exemplary module100fmay include die stacking on a top surface of the PCB102. The exemplary module100fincludes the interconnects122and solder joints124which are connected to the metal layer114a. The die106is flip-chip mounted onto the top surface of the PCB102. The die104is then flip-chip mounted onto the top surface of the PCB102. The solder joint120and the solder joint124may then be formed through one step reflow at the same time along with other dies and components placed on PCB top surface (i.e., the SMT108), thereby not introducing extra assembly cost. The die104and the die106may be fully or partially overlapped (seeFIGS.2A-2D, for example). The die106may include multiple dies, bank of Si capacitors, IPD, or any combination therein. A shorter interconnect structure (for example, 3 micrometers of nickel and 15 micrometers of plated solder) along with 70 micrometer bump diameter and 120 micrometer bump pitch may be used for the interconnect122and the solder joints124of the die106. An even taller interconnect structure (for example, 100 micrometers of copper and 20 micrometers of plated solder) along with 70 micrometer bump diameter and 120 micrometer bump pitch may be used for the interconnects118and the solder joints120of the die104. A distance between the edge of the die106and its neighboring pad of the die104may be 80 micrometers or greater. A thickness for the die106may vary from 50 micrometers to 70 micrometers. A thickness for the die104may vary from 120 micrometers to 155 micrometers. The airgap between the die104and the die106before underfill or molding may be around 35 micrometers, making it feasible for die stacking. The clearance between the top surface of the die104and the top surface of the molding compound113may be around 30 micrometers.

Referring now in particular toFIG.1G, an exemplary module100gis described. The exemplary module100gmay include die stacking on the top surface of the PCB102with the top surface of the die104exposed. The die106is flip-chip mounted onto the top surface of the PCB102. The die104is then flip-chip mounted onto the top surface of the PCB102. The solder joints120and the solder joints124may then be formed through one step reflow at the same time along with other dies and components placed on PCB top surface (i.e., the SMT108), thereby not introducing extra assembly cost. The molding compound113may then be over molded and grinded to expose the top surface of the die104. The die104and die106may be fully or partially overlapped (seeFIGS.2A-2D, for example). The die106may be multiple dies, bank of Si capacitors, IPD, or any combination therein. A shorter interconnect structure (for example, 3 micrometers of nickel and 15 micrometers of plated solder) along with 70 micrometer bump diameter and 120 micrometer bump pitch may be used for the interconnect122and the solder joints124of die106. An even taller interconnect structure (for example, 100 micrometers of copper and 20 micrometers of plated solder) along with 70 micrometer bump diameter and 120 micrometer bump pitch may be used for the interconnects118and the solder joints120of die104. A distance between the edge of the die106and its neighboring pad of the die104may be 80 micrometers or greater. A thickness for the die106may vary from 50 micrometers to 70 micrometers. A thickness for the die104may vary from 140 micrometers to 250 micrometers before mold grinding and from 110 micrometer to 185 micrometers after grinding. The airgap between the die104and the die106before underfill or molding may be around 35 micrometers, making it feasible for die stacking. The backside of the die104is exposed by grinding the molding compound113, which helps further reduce the height of the module100. In embodiments, the top surface of the die104may include a laser marking or ink marking.

Referring now in particular toFIG.1H, an exemplary module100his described. The exemplary module100hmay include die stacking in a face-to-face configuration. The die106is flip-chip mounted to the face side of the die104and reflowed to form a diced die stack. The diced die stack may then be flip-chip mounted onto the top surface of the PCB by the interconnect118and solder joint120and reflowed. Thus, the die106is connected to the die104by the interconnect122solder joint124in a face-to-face configuration and the die104is connected to the PCB102by the interconnect118and solder joint120. The die104and die106may be fully or partially overlapped (seeFIGS.2A-2D, for example). The die106may be multiple dies, bank of Si capacitors, IPD, or any therein. A shorter interconnect structure (for example, 3 micrometers of nickel and 15 micrometers of plated solder) along with 70 micrometer bump diameter and 120 micrometer bump pitch may be used for the interconnect122(e.g., UBM) and the solder joints124of the die106. An even taller interconnect structure (for example, 100 micrometers of copper and 20 micrometers of plated solder) along with 70 micrometer bump diameter and 120 micrometer bump pitch may be used for the interconnects118and the solder joints120of the die104. A distance between the edge of the die106and its neighboring pad of the die104may be 80 micrometers or greater. A thickness for the die106may vary from 50 micrometers to 70 micrometers. A thickness for the die104may vary from 120 micrometers to 155 micrometers. The airgap between the die106and the top surface of the PCB before underfill or molding may be around 35 micrometers, making it feasible for die stacking. The clearance between the top surface of the die104and the top surface of the molding compound113may be around 30 micrometers.

Referring now in particular toFIG.1I, an exemplary module100iis described. The exemplary module100imay include die stacking in a face-to-face configuration with a top surface of the die104exposed. The die106is flip-chip mounted to the die104and reflowed to form a diced die stack. The diced die stack is then flip-chip mounted onto the top surface of the PCB102surface by the interconnects118and reflowed. The molding compound113is then over molded and grinded to expose the top surface of the die104. The die104and the die106may be fully or partially overlapped (seeFIGS.2A-2D, for example). The die106may be multiple dies, bank of Si capacitors, IPD, or any combination therein. A shorter interconnect structure (for example, 3 micrometers of nickel and 15 micrometers of plated solder) along with 70 micrometer bump diameter and 120 micrometer bump pitch may be used for the interconnect122and the solder joints124of the die106. An even taller interconnect structure (for example, 100 micrometers of copper and 20 micrometers of plated solder) along with 70 micrometer bump diameter and 120 micrometer bump pitch may be used for the interconnects118and the solder joints120of the die104. A distance between the edge of the die106and its neighboring pad of the die104may be 80 micrometers or greater. A thickness for the die106may vary from 50 micrometers to 70 micrometers. A thickness for the die104may vary from 110 micrometer to 185 micrometers after grinding. The airgap between die106and PCB top surface before underfill or molding may be around 35 micrometers, making it feasible for die stacking. The backside of the die104is exposed by grinding the molding compound113, which helps further reduce the height of the module100. In embodiments, the top surface of the die104may include a laser marking or ink marking.

Referring now in particular toFIG.1J, an exemplary module100jis described. The exemplary module100jmay include die stacking in a face-to-face configuration with (not depicted inFIG.1J) or without a top surface of the die104exposed inside a PCB cavity. The die106is flip-chip mounted to the die104and reflowed to form a diced die stack. The diced die stack is then flip-chip mounted to the metal layer114bwithin the cavity126by the interconnects118and reflowed. The molding compound is 113 is then over molded and grinded to expose or not expose the top surface of the die104. The die104and the die106may be fully or partially overlapped (seeFIGS.2A-2D, for example). The die106may be multiple dies, bank of Si capacitors, IPD, or any combination therein.

Referring now in particular toFIG.1K, an exemplary module100kis described. The exemplary module100kmay include die stacking on the interposer136. The die106is flip-chip mounted to the interposer136followed by reflow, molding to form the intermediary molding compound138, and grinding. The die104is then flip-chip mounted to the stack including interposer136and the die106. Thus, the die104and the die106may be stacked over the interposer136. The interposer136may then be mounted to the top surface of the PCB102. The die104and die106may be fully or partially overlapped and the interposer136may fully overlap the die104and the die106(seeFIGS.21-2L, for example). Both of the interconnect118and the interconnect122are fully enclosed by the intermediary molding compound138. The die106may be multiple dies, bank of Si capacitors, IPD, or a combination of any of them. The interconnects118may be pre-existing copper pillars which are formed on interposer136before molding. The connection between the die104and the stacking including the interposer136and the die106may be formed by a solder or flux printing process followed by reflow. The taller interconnect structure (for example, 100 micrometers of copper and 20 micrometers of plated solder) along with 70 micrometer bump diameter and 120 micrometer bump pitch may be used for the interconnects118and the solder joints120of the die104. Alternatively, the interconnects118may be through mold vias (TMV) filled with conductive metals (e.g., plated copper, tungsten, etc.) after the intermediary EMC is formed, grinded, and drilled. A shorter interconnect structure (for example, 3 micrometer of nickel and 15 micrometers of plated solder) along with 70 micrometer bump diameter and 120 micrometer bump pitch may be used for the interconnect122and the solder joints124of the die106. The thickness for the interposer136may vary from 30 micrometers to 100 micrometers. The die106thickness may vary from 45 micrometers to 155 micrometers. The die104thickness may vary from 50 micrometers to 160 micrometers. The distance between the edge of the die106and its neighboring pad of the die104may be 80 micrometers or greater. The airgap between the die106and the die104before underfill or molding may be around 10 to 20 micrometers. The clearance between the top surface of the die104and the top surface of the molding compound113may be 30 micrometers.

Referring now in particular toFIG.1L, an exemplary module100lis described. The exemplary module100lmay include die stacking on the interposer136with the top surface of the die104exposed. The die106is flip-chip mounted to the interposer136followed by reflow, molding of the intermediary molding compound138, and grinding. The die104is then flip-chip mounted to the stack including interposer136and the die106. The interposer136is then mounted to the top surface of the PCB102. The molding compound113is then over molded and grinded to expose the top surface of the die104. The die104and die106may be fully or partially overlapped and the interposer136may fully overlap the die104and the die106(seeFIGS.21-2L, for example). Both of the interconnect118and the interconnect122are fully enclosed by the intermediary molding compound138. The die106may be multiple dies, bank of Si capacitors, IPD, or any combination therein. The interconnects118may be pre-existing copper pillars which are formed on the interposer136before molding. The connection between the die104and the stack including the interposer136and the die106may be formed by a solder or flux printing process followed by reflow. The taller interconnect structure (for example, 100 micrometers of copper and 20 micrometers of plated solder) along with 70 micrometer bump diameter and 120 micrometer bump pitch may be used for the interconnects118and the solder joints120of the die104. Alternatively, the interconnects118may be through mold vias filled with metals (e.g., plated copper, tungsten, etc.) after the intermediary EMC is formed, grinded, and drilled. A shorter interconnect structure (for example, 3 micrometers of nickel and 15 micrometers of plated solder) along with 70 micrometer bump diameter and 120 micrometer bump pitch may be used for the interconnect122and the solder joints124of the die106. The thickness for the interposer136may vary from 30 micrometers to 100 micrometers. The die106thickness may vary from 45 micrometers to 155 micrometers. The die104thickness may vary from 80 micrometers to 190 micrometers. The distance between the edge of the die106and its neighboring pad of the die104may be 80 micrometers or greater. The airgap between the die106and the die104before underfill or molding may be around 10 to 20 micrometers. The backside of the die104is exposed by grinding the molding compound113, which helps further reduce the height of the module100. In embodiments, the top surface of the die104may include a laser marking or ink marking.

Referring now in particular toFIG.1M, an exemplary module100mis described. The exemplary module100mmay include die stacking on the interposer136with the top surface of the die104exposed. The die106is flip-chip mounted to the interposer136followed by reflow, molding of the intermediary molding compound138, and grinding. The die104is then flip-chip mounted to the stack including the interposer136and the die106. The interposer136is then mounted to the metal layer114bin the cavity126. The molding compound113is then over molded and grinded to expose the top surface of the die104. Alternatively, the molding compound113may grinded less, such that the top surface of the die104is not exposed (not depicted inFIG.1M).

Referring now in particular toFIG.1N, an exemplary module100nis described. As an alternative process flow to the exemplary module100k, the die106may be flip-chip mounted to the interposer136, followed by the die104being flip-chip mounted to the interposer, followed by reflow and molding of the intermediary molding compound138. In this regard, the intermediary molding compound138may encompass the die104, the die106, and the top surface of the interposer136. The interposer136may then be mounted to the top surface of the PCB102.

Referring generally again toFIGS.1A-2L.

The module may also include an under-bump metallization (UBM) layer. The UBM layer serves as an adhesion layer and a barrier layer between the die and the copper pillars or between the die and the nickel bumps. The UBM layer may be titanium, titanium tungsten, tantalum, and the like.

As used herein, directional terms such as “top,” “bottom,” “over,” “under,” “upper,” “upward,” “lower,” “down,” and “downward” are intended to provide relative positions for purposes of description, and are not intended to designate an absolute frame of reference. Various modifications to the described embodiments will be apparent to those with skill in the art, and the general principles defined herein may be applied to other embodiments.

It is understood that the specific order or hierarchy of steps in the methods, operations, and/or functionality disclosed are examples of exemplary approaches. Based upon design preferences, it is understood that the specific order or hierarchy of steps in the methods, operations, and/or functionality can be rearranged while remaining within the scope of the inventive concepts disclosed herein. The accompanying claims may present elements of the various steps in a sample order, and are not necessarily meant to be limited to the specific order or hierarchy presented. It is to be understood that embodiments of the methods according to the inventive concepts disclosed herein may include one or more of the steps described herein. Further, such steps may be carried out in any desired order and two or more of the steps may be carried out simultaneously with one another. Two or more of the steps disclosed herein may be combined in a single step, and in some embodiments, one or more of the steps may be carried out as two or more sub-steps. Further, other steps or sub-steps may be carried in addition to, or as substitutes to one or more of the steps disclosed herein.