Array substrate, manufacturing method thereof, flexible display panel and display device

The present disclosure provides an array substrate, a manufacturing method thereof, a flexible display panel, and a display device, all for achieving a frame-free full-screen flexible display product. The array substrate provided in the present disclosure comprises a flexible base substrate, a thin film transistor on a first surface of the flexible base substrate, and a wiring terminal for transmitting a signal to an electrode of the thin film transistor on a second surface of the flexible base substrate opposite to the first surface. The electrode of the thin film transistor is electrically connected to the wiring terminal through a via hole penetrating the flexible base substrate.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority to Chinese Patent Application No. 201710433423.6, filed on Jun. 9, 2017, the entirety of which is incorporated herein by reference.

BACKGROUND

The present disclosure relates to the technical field of displays, and particularly to an array substrate, a manufacturing method thereof, a flexible display panel, and a display device.

The field of display technology is developing rapidly. With the continuous increase in demand for various display products such as notebooks, smartphones, televisions, tablet computers, smart watches, fitness wristbands and the like, more novel display products will emerge in future.

At present, most flexible display panels have frames, and wiring terminals (for example, for binding PAD) are usually disposed on the outer periphery of the display area of the flexible display panel. Frame-free full-screen display products allow better viewing experiences of users, and are likely to drive new consumer markets. On this basis, there exists an urgent technical need to achieve a frame-free full-screen flexible display product.

SUMMARY

Embodiments of the present disclosure provide an array substrate, a manufacturing method thereof, a flexible display panel and a display device, for achieving a frame-free full-screen flexible display product.

Embodiments of the present disclosure provide an array substrate comprising: a flexible base substrate, a thin film transistor on a first surface of the flexible base substrate, and a wiring terminal for transmitting a signal to an electrode of the thin film transistor, on a second surface of the flexible base substrate opposite to the first surface, wherein the electrode of the thin film transistor is electrically connected to the wiring terminal through a via hole penetrating the flexible base substrate.

In an embodiment, the array substrate further comprises a signal wire on the first surface or the second surface of the flexible base substrate; wherein the wiring terminal is connected to the electrode of the thin film transistor through the signal wire.

In an embodiment, the signal wire comprises a plurality of gate electrode signal wires and a plurality of data signal wires insulated from each other.

In an embodiment, the signal wire is disposed on the first surface of the flexible base substrate, a plurality of wiring terminals are provided, and a first insulating layer is disposed between the gate electrode signal wires and the flexible base substrate, wherein each gate electrode signal wire is connected to each wiring terminal in one to one correspondence through a via hole penetrating the first insulating layer and the flexible base substrate.

In an embodiment, a second insulating layer is disposed between the data signal wires and the flexible base substrate, and each data signal wire is connected to each wiring terminal in one to one correspondence through a via hole penetrating the second insulating layer and the flexible base substrate.

In an embodiment, the gate electrode signal wires are disposed in the same layer as that of a gate electrode, and the data signal wires are disposed in the same layer as that of source/drain electrodes.

In an embodiment, the gate electrode is positioned between the source/drain electrodes and the flexible base substrate, and an active layer is disposed between the gate electrode and the flexible base substrate; the first insulating layer comprises: a buffer layer between the active layer and the flexible base substrate, and a gate insulating layer between the gate electrode and the active layer, and the second insulating layer comprises: the buffer layer, the gate insulating layer, and an interlayer dielectric layer between the source/drain electrodes and the gate electrode.

In an embodiment, the gate electrode is positioned between the source/drain electrodes and the flexible base substrate, and an active layer is disposed between the gate electrode and the source/drain electrodes; the first insulating layer comprises a buffer layer between the gate electrode and the flexible base substrate, and the second insulating layer comprises the buffer layer, and a gate insulating layer between the gate electrode and the active layer.

In an embodiment, the source/drain electrodes are positioned between the gate electrode and the flexible base substrate, and an active layer is disposed between the source/drain electrodes and the flexible base substrate; the second insulating layer comprises a buffer layer between the active layer and the flexible base substrate, and the first insulating layer comprises the buffer layer, and a gate insulating layer between the gate electrode and the source/drain electrodes.

Embodiments of the present disclosure further provide a flexible display panel comprising: the array substrate provided in any embodiment of the present disclosure, and a flexible circuit board or integrated circuit on the second surface of the flexible base substrate; wherein the flexible circuit board or integrated circuit is electrically connected to an electrode of the thin film transistor through the wiring terminal.

Embodiments of the present disclosure further provide a display device comprising the flexible display panel provided in any embodiment of the present disclosure.

Embodiments of the present disclosure further provide a manufacturing method of an array substrate, comprising: forming a wiring terminal for transmitting a signal to an electrode of a thin film transistor, on a rigid substrate; forming a flexible base substrate on the rigid substrate with the wiring terminal formed thereon; and forming a thin film transistor on the flexible base substrate, wherein an electrode of the thin film transistor is electrically connected to the wiring terminal through a via hole penetrating the flexible base substrate.

In an embodiment, after forming the wiring terminal and before forming the flexible base substrate, the method further comprises forming a signal wire on the rigid substrate with the wiring terminal formed thereon; or after forming the flexible base substrate, the method further comprises forming a signal wire on the flexible base substrate, wherein the wiring terminal is to be connected to an electrode of the thin film transistor through the signal wire.

In an embodiment, the signal wire comprises a plurality of gate electrode signal wires and a plurality of data signal wires insulated from each other; a plurality of wiring terminals are provided; and forming the plurality of gate electrode signal wires on the flexible base substrate comprises: forming a first insulating layer on the flexible base substrate; forming a via hole at a position on the first insulating layer and the flexible base substrate corresponding to each of the wiring terminals to be connected to the gate electrode signal wires; and forming a plurality of gate electrode signal wires on the first insulating layer with the via hole formed thereon, wherein each gate electrode signal wire is connected to each wiring terminal in one to one correspondence through a via hole penetrating the first insulating layer and the flexible base substrate.

In an embodiment, forming a plurality of data signal wires on the flexible base substrate comprises: forming a second insulating layer on the flexible base substrate; forming a via hole at a position on the second insulating layer and the flexible base substrate corresponding to each of the wiring terminals to be connected to the data signal wires; and forming a plurality of data signal wires on the second insulating layer with the via hole formed thereon, wherein each data signal wire is connected to each wiring terminal in one to one correspondence through a via hole penetrating the second insulating layer and the flexible base substrate.

DETAILED DESCRIPTION

Embodiments of the present disclosure provide an array substrate, a manufacturing method thereof, a flexible display panel, and a display device for achieving a frame-free full-screen flexible display product.

The technical solutions in embodiments of the present disclosure will be described in detail below in combination with the drawings of the embodiments of the present disclosure. The embodiments described in detail herein constitute only a part of, not all of the embodiments contemplated in view of the present disclosure. All of other embodiments obtained by those skilled in the art based on the embodiments of the present disclosure, without inventive efforts, fall within the protection scope of the present invention.

It should be noted that that the drawings are not necessarily to scale. For example, the thickness and shape of each layer in the drawings of the present disclosure does not indicate a real proportion, and is only intended to schematically illustrate the present disclosure.

Referring toFIG. 1, an embodiment of the present disclosure provides an array substrate comprising: a flexible base substrate11, a thin film transistor15(as indicated by the dashed box inFIG. 1) and a signal wire12disposed on a first surface of the flexible base substrate11, and a wiring terminal13for transmitting a signal to an electrode of the thin film transistor15disposed on a second surface of the flexible base substrate11opposite to the first surface, wherein one end of the signal wire12is connected to the electrode of the thin film transistor15, and the other end is connected to the wiring terminal13through a via hole14penetrating the flexible base substrate11.

Here, the signal wire12may comprise a plurality of gate electrode signal wires121and a plurality of data signal wires122insulated from each other.

The signal wire12, for example, may also comprise a clock signal wire, and this is not limited in the embodiments of the present disclosure.

If an insulating layer is further disposed between the signal wire12and the flexible base substrate11, the signal wire12is connected to the wiring terminal13through a via hole penetrating the insulating layer and the flexible base substrate11.

As shown inFIG. 1, the thin film transistor15comprises an active layer151, a gate insulating layer (GI)152, a gate electrode153, an interlayer dielectric layer (ILD)154and source/drain electrodes155sequentially stacked on the flexible base substrate11.

As shown inFIG. 1, a plurality of wiring terminals13are provided, and a first insulating layer is disposed between the gate electrode signal wire121and the flexible base substrate11, and each gate electrode signal wire121is connected to one wiring terminal13through a via hole141penetrating the first insulating layer and the flexible base substrate11.

As shown inFIG. 1, a second insulating layer is disposed between the data signal wire122and the flexible base substrate11, and each data signal wire122is connected to one wiring terminal13through a via hole142penetrating the second insulating layer and the flexible base substrate11.

In a particular embodiment, as shown inFIG. 1, the gate electrode signal wire121is disposed in the same layer as that of the gate electrode153, and the data signal wire122is disposed in the same layer as that of the source/drain electrodes155.

In a particular embodiment, as shown inFIG. 1, a buffer layer (Buffer)16is disposed between the active layer151and the flexible base substrate11; the first insulating layer comprises the buffer layer16and the gate insulating layer152; and the second insulating layer comprises the buffer layer16, the gate insulating layer152and the interlayer dielectric layer154.

Further, the signal wire12may also be disposed on the second surface of the flexible base substrate11. In this case, one end of the signal wire12is connected to the wiring terminal13, and the other end is connected to an electrode of the thin film transistor15through the via hole14disposed in the flexible base substrate11.

Referring toFIG. 2, an embodiment of the present disclosure further provides an array substrate, which is similar to the array substrate as shown inFIG. 1. The same portions are not reiterated here, and only different portions are described below.

In the array substrate as shown inFIG. 2, the thin film transistor15(as indicated by the dashed box inFIG. 2) comprises a gate electrode153, a gate insulating layer152, an active layer151and source/drain electrodes155sequentially stacked on the flexible base substrate11.

In a particular embodiment, as shown inFIG. 2, a buffer layer16is disposed between the gate electrode153and the flexible base substrate11; the first insulating layer comprises the buffer layer16; and the second insulating layer comprises the buffer layer16and the gate insulating layer152.

Of course, it is possible that no buffer layer16is disposed between the gate electrode153and the flexible base substrate11. In this case, there is no first insulating layer between the gate electrode signal wire121and the flexible base substrate11, that is, the gate electrode signal wire121is connected to the wiring terminal13only through a via hole disposed in the flexible base substrate11, and this is not limited in the embodiments of the present disclosure.

Referring toFIG. 3, an embodiment of the present disclosure further provides an array substrate, which is similar to the array substrate as shown inFIG. 1. The same portions are not reiterated here, and only different portions are described below.

In the array substrate as shown inFIG. 3, the thin film transistor15(as indicated by the dashed box inFIG. 3) comprises an active layer151, source/drain electrodes155, a gate insulating layer152and a gate electrode153sequentially stacked on the flexible base substrate11.

In a particular embodiment, as shown inFIG. 3, a buffer layer16is disposed between the active layer151and the flexible base substrate11; the second insulating layer comprises the buffer layer16; and the first insulating layer comprises the buffer layer16and the gate insulating layer152.

Base on the same concept, as shown inFIG. 4, an embodiment of the present disclosure further provides a manufacturing method of an array substrate, comprising the following steps:

S101: Forming a wiring terminal for transmitting a signal to an electrode of a thin film transistor on a rigid substrate; wherein the rigid substrate may be a glass substrate, a quartz substrate, a rock crystal substrate, or the like.

The material of the wiring terminal may be, for example, a metal material such as molybdenum (Mo), aluminum (Al), copper (Cu) and the like.

Forming the wiring terminal on the rigid substrate may comprise: forming a metal layer on the rigid substrate by sputtering; and patterning the metal layer to form the wiring terminal.

S102: Forming a flexible base substrate on the rigid substrate with the wiring terminal formed thereon; wherein, the flexible base substrate may be a transparent organic insulating substrate composed of one selected from the group consisting of polyethersulfone (PES), polyacrylate (PAR), polyetherimide (PEI), polyethelene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyallylate, polyimide resin (PI), polycarbonate (PC), cellulose triacetate (TAC), cellulose acetate propionate (CAP), acrylate and a combination thereof.

S103: Forming a thin film transistor on the flexible base substrate, wherein an electrode of the thin film transistor is electrically connected to the wiring terminal through a via hole penetrating the flexible base substrate.

In a particular embodiment, after forming the wiring terminal and before forming the flexible base substrate, the method may further comprise: forming a signal wire on the rigid substrate with the wiring terminal formed thereon; wherein the wiring terminal is to be connected to an electrode of the thin film transistor through the signal wire.

In another particular embodiment, after forming the flexible base substrate, the method may further comprise: forming a signal wire on the flexible base substrate; wherein the wiring terminal is to be connected to an electrode of the thin film transistor through the signal wire.

Here, the signal wire may comprise a plurality of gate electrode signal wires and a plurality of data signal wires insulated from each other, and a plurality of wiring terminals may be provided.

In a particular embodiment, forming a plurality of gate electrode signal wires on the flexible base substrate may particularly comprise: forming a first insulating layer on the flexible base substrate; forming a via hole at a position on the first insulating layer and the flexible base substrate corresponding to each of the wiring terminals to be connected to the gate electrode signal wires; and forming a plurality of gate electrode signal wires on the first insulating layer with the via hole formed thereon, wherein each gate electrode signal wire is connected to each wiring terminal in one to one correspondence through a via hole penetrating the first insulating layer and the flexible base substrate.

In a particular embodiment, forming a plurality of data signal wires on the flexible base substrate may particularly comprise: forming a second insulating layer on the flexible base substrate; forming a via hole at a position on the second insulating layer and the flexible base substrate corresponding to each of the wiring terminals to be connected to the data signal wires; and forming a plurality of data signal wires on the second insulating layer with the via hole formed thereon, wherein each data signal wire is connected to each wiring terminal in one to one correspondence through a via hole penetrating the second insulating layer and the flexible base substrate.

It should be noted that if the data signal wire is above the gate electrode signal wire, then the second insulating layer=the first insulating layer+a third insulating layer between the gate electrode signal wire and the data signal wire. In the process of manufacturing the array substrate, forming the plurality of gate electrode signal wires and the plurality of data signal wires insulated from each other on the flexible base substrate may particularly comprise: forming a first insulating layer on the flexible base substrate; on the first insulating layer and the flexible base substrate, forming a via hole at a position corresponding to each of the wiring terminals to be connected to the gate electrode signal wires, and forming a via hole at a position corresponding to each of the wiring terminals to be connected to the data signal wires; forming a plurality of gate electrode signal wires on the first insulating layer with the via hole formed thereon; forming a third insulating layer on the flexible base substrate with the plurality of gate electrode signal wires formed thereon; forming a via hole at a position on the third insulating layer corresponding to each of the wiring terminals to be connected to the data signal wires; and forming a plurality of data signal wires on the third insulating layer with the via hole formed thereon.

Here, the third insulating layer may be, for example, a gate insulating layer, an interlayer dielectric layer or the like.

In an embodiment, the area occupied by the via hole pattern of the third insulating layer is not less than the area occupied by the via hole pattern of the first insulating layer.

Forming the plurality of gate electrode signal wires and the plurality of data signal wires insulated from each other on the flexible base substrate may further comprise: forming a first insulating layer on the flexible base substrate; forming a via hole at a position on the first insulating layer and the flexible base substrate corresponding to each of the wiring terminals to be connected to the gate electrode signal wires; and forming a plurality of gate electrode signal wires on the first insulating layer with the via hole formed thereon; forming a third insulating layer on the flexible base substrate with the plurality of gate electrode signal wires formed thereon; forming a via hole at a position on the third insulating layer, the first insulating layer and the flexible base substrate corresponding to each of the wiring terminals to be connected to the data signal wires; and forming a plurality of data signal wires on the third insulating layer with the via hole formed thereon.

Similarly, if the gate electrode signal wire is above the data signal wire, then the first insulating layer=the second insulating layer+a third insulating layer between the gate electrode signal wire and the data signal wire. In the process of manufacturing the array substrate, forming the plurality of gate electrode signal wires and the plurality of data signal wires insulated from each other on the flexible base substrate may particularly comprise: forming a second insulating layer on the flexible base substrate; on the second insulating layer and the flexible base substrate, forming a via hole at a position corresponding to each of the wiring terminals to be connected to the gate electrode signal wires, and forming a via hole at a position corresponding to each of the wiring terminals to be connected to the data signal wires; forming a plurality of data signal wires on the second insulating layer with the via hole formed thereon; forming a third insulating layer on the flexible base substrate with the plurality of gate electrode signal wires formed thereon; forming a via hole at a position on the third insulating layer corresponding to each of the wiring terminals to be connected to the gate electrode signal wires; and forming a plurality of gate electrode signal wires on the third insulating layer with the via hole formed thereon.

In an embodiment, the area occupied by the via hole pattern of the third insulating layer is not less than the area occupied by the via hole pattern of the second insulating layer.

Forming the plurality of gate electrode signal wires and the plurality of data signal wires insulated from each other on the flexible base substrate may further comprise: forming a second insulating layer on the flexible base substrate; forming a via hole at a position on the second insulating layer and the flexible base substrate corresponding to each of the wiring terminals to be connected to the data signal wires; and forming a plurality of data signal wires on the second insulating layer with the via hole formed thereon; forming a third insulating layer on the flexible base substrate with the plurality of gate electrode signal wires formed thereon; forming a via hole at a position on the third insulating layer, the second insulating layer and the flexible base substrate corresponding to each of the wiring terminals to be connected to the gate electrode signal wires; and forming a plurality of gate electrode signal wires on the third insulating layer with the via hole formed thereon.

The manufacturing process of an array substrate provided in an embodiment of the present disclosure will be described in detail below with reference toFIG. 5(a)˜FIG. 5(g), by taking an array substrate shown inFIG. 1as an example.

Step I: Referring toFIG. 5(a), forming a wiring terminal502for transmitting a signal to an electrode of a thin film transistor on a glass substrate501. For example, a metal film layer may be deposited on the glass substrate501by using a magnetron sputtering process; the material of the metal film layer may be Mo, Al, Cu or the like; and the metal film layer is patterned with a wet etching method using photoresist to form the wiring terminal502.

Step II: Referring toFIG. 5(b), forming a flexible base substrate503on the glass substrate501with the wiring terminal502formed thereon; wherein, the material of the flexible base substrate503is PI. For example, the flexible base substrate503is formed by spin coating a PI film layer on the glass substrate501with the wiring terminal502formed thereon.

Step III: Referring toFIG. 5(c), forming a buffer layer504, an active layer505, and a gate insulating layer506sequentially on the flexible base substrate503. For example, a silicon nitride (SiNx) layer and a silicon oxide (SiOx) layer are sequentially deposited as the buffer layer504on the flexible base substrate503with a plasma enhanced chemical vapor deposition (PECVD) method; an amorphous silicon (A-Si) layer is formed on the SiOxlayer, and the amorphous silicon, after being dehydrogenated by high temperature annealing, is subjected to crystallization treatment with an excimer laser crystallization (ELA) method, and then a poly-silicon (P-Si) pattern, as the active layer505, is formed with a dry etching process using photoresist; the poly-silicon active layer505is subjected to a threshold voltage heavy doping (Vth Doping) with an ion injection process; and a silicon nitride (SiNx) layer and a silicon oxide (SiOx) layer are sequentially deposited as the gate insulating layer506on the active layer505with a PECVD method.

Step IV: Referring toFIG. 5(d), forming a via hole at a position on the gate insulating layer506, the buffer layer504and the flexible base substrate503corresponding to each of the wiring terminals502. For example, the gate insulating layer506, the buffer layer504and the flexible base substrate503are patterned with a dry etching method using photoresist, to form the via hole at a position corresponding to each of the wiring terminals502.

Step V: Referring toFIG. 5(e), forming a plurality of gate electrode signal wires507, a gate electrode508and an interlayer dielectric layer509sequentially on the gate insulating layer506with the via hole formed thereon; wherein, each gate electrode signal wire507is connected to one wiring terminal502through a via hole penetrating the gate insulating layer506, the buffer layer504and the flexible base substrate503. For example, a Mo metal layer may be deposited with a magnetron sputtering process on the gate insulating layer506with the via hole formed thereon, and patterned with a wet etching method using photoresist to form the plurality of gate electrode signal wires507and the gate electrode508; the poly-silicon active layer505is subjected to source/drain heavy doping (S/D Doping) with an ion injection process; and a silicon nitride (SiNx) layer and a silicon oxide (SiOx) layer are sequentially deposited as the interlayer dielectric layer509on the plurality of gate electrode signal wires507and the gate electrode508with a PECVD method.

Step VI: Referring toFIG. 5(f), for the interlayer dielectric layer509, forming a via hole at a position corresponding to each of the wiring terminals502to be connected to the data signal wires; and for the interlayer dielectric layer509and the gate insulating layer506, forming a via hole for connecting the active layer505and the source/drain electrodes. For example, the interlayer dielectric layer509is patterned with exposing and dry etching methods, to form a via hole at a position corresponding to each of the wiring terminals502to be connected to the data signal wires; and the interlayer dielectric layer509and the gate insulating layer506are patterned with exposing and dry etching methods to form a via hole for connecting the active layer505and the source/drain electrodes.

Step VII: Referring toFIG. 5(g), forming a plurality of data signal wires510and source/drain electrodes511on the interlayer dielectric layer509with the via hole formed thereon; wherein, each data signal wire510is connected to one wiring terminal502through a via hole penetrating the interlayer dielectric layer509, the gate insulating layer506, the buffer layer504and the flexible base substrate503. The source/drain electrodes511and the active layer505are connected through the via hole therebetween. For example, a Ti metal layer, an Al metal layer, and a Ti metal layer may be sequentially deposited with a magnetron sputtering process on the interlayer dielectric layer509with the via hole formed thereon, and patterned with a dry etching method using photoresist to form the plurality of data signal wires510and the source/drain electrodes511.

Step VIII: Peeling off the glass substrate501, wherein the array substrate after peeling is as shown inFIG. 5(h).

Based on the same concept, referring toFIG. 6, an embodiment of the present disclosure further provides a flexible display panel comprising: an array substrate61provided in any embodiment of the present disclosure, and a flexible circuit board62disposed on a second surface of a flexible base substrate611of the array substrate61; wherein the flexible circuit board62is connected to a signal wire613of the array substrate61through a wiring terminal612of the array substrate61, and the signal wire613is connected to an electrode of a thin film transistor of the array substrate61. Here, the flexible circuit board62may be replaced with an integrated circuit.

In a particular embodiment, as shown inFIG. 6, the above flexible display panel may further comprise: a planarization layer (PLN)63disposed on a thin film transistor614of the array substrate61and an organic light emitting diode64. Here, the organic light emitting diode64may be replaced with a quantum dot light emitting diode.

Based on the same concept, an embodiment of the present disclosure further provides a display device comprising the flexible display panel provided in any embodiment of the present disclosure. The display device may be any product or component having a displaying function such as mobile phone, tablet computer, television, display, notebook, digital photo frame, navigator and the like.

In summary, the embodiments of the present disclosure provide an array substrate, a manufacturing method thereof, a flexible display panel and a display device. The array substrate comprises a flexible base substrate, a thin film transistor disposed on a first surface of the flexible base substrate, and a wiring terminal for transmitting a signal to an electrode of the thin film transistor disposed on a second surface of the flexible base substrate opposite to the first surface, wherein the electrode of the thin film transistor is electrically connected to the wiring terminal through a via hole penetrating the flexible base substrate. Since the wiring terminal is disposed on the back surface of the flexible base substrate, there is no need to reserve a space for disposing the wiring terminal on the outer periphery of the display area of the flexible display panel comprising the array substrate, said wiring terminal being used to connect the flexible circuit board or integrated circuit with the electrode of the thin film transistor. Thus, a frame-free full-screen flexible display product can be achieved.

Obviously, modifications and variations on the present disclosure can be made by those skilled in the art without departing from the spirit and scope of the present invention. As such, if these modifications and variations fall within the scopes of the claims of the present application or equivalent technologies thereof, the present invention is intended to encompass these modifications and variations.