Automatic gain control circuit for a modem receiver

An automatic gain control method and apparatus for modem receivers. The automatic gain control circuit includes a programmable loop gain for scaling a digital signal Y to a first prescribed level during a first mode of operation and to a second prescribed level during a second mode of operation; and filters and converters for converting the scaled signal Y into an analog gain control signal for input to the analog AGC. The gain control circuit and method of operation provides control over the parameters of the programmable loop gain such that during start-up initialization the signal Y is scaled to the first prescribed value and during steady state operation the signal Y is scaled to the second prescribed value. This is accomplished by changing the gain parameter of the programmable loop gain.

FIELD OF THE INVENTION
 This invention relates to the field of automatic gain control (AGC)
 circuits, and more particularly, for AGC circuits of modem receivers.
 BACKGROUND OF THE INVENTION
 In communication systems a modem is used to convert (modulate) digital
 signals generated by a computer into analog signals suitable for
 transmission over telephone lines. Another modem, located at the receiving
 end of the transmission, converts (demodulates) the analog signals back
 into digital form. The transmission speed of digital subscriber loop (DSL)
 modems has exhibited a remarkable increase in recent years, and as the
 increase of the transmission speed progresses, it becomes increasingly
 necessary to reduce the occurrence of errors in data communication arising
 from disturbances of the circuit to as few as possible.
 In addition, due to the large range of different twisted pair loops over
 which high speed modems operate and the varying amount of interference,
 the received signal at the analog-to-digital converter input (in the
 demodulation section of a modem) can present a dynamic range of over 70
 dB.
 An automatic gain control circuit is provided in the demodulation section
 of a modem to monitor the input signal level and to provide the
 appropriate gain to bring the signal to a desired level.
 Traditional AGC circuits in modem receivers working over the necessary full
 dynamic range present significant differences in performance, convergence
 times, and gain variability at different regions of operation.
 Consequently, there is a need for a AGC circuit in an modem receiver that
 provides gain tracking for a large range of twisted pair loops with over
 70 dB range (for example), various signal bandwidths, and in the presence
 of radio frequency (RF) and other asynchronous digital subscriber line
 (ADSL) interference. Further, the AGC circuit must improve gain ripple
 after convergence to minimize its noise contribution to the system.
 SUMMARY OF THE INVENTION
 An object of the present invention is to provide an automatic gain control
 circuit for a modem receiver that improves gain tracking for a large range
 of twisted pair loops.
 Another object of the present invention is to provide an automatic gain
 control circuit for a modem receiver that improves gain ripple after modem
 convergence to minimize noise contribution.
 In accordance with an aspect of the present invention there is provided an
 automatic gain control circuit for a modem receiver, said receiver having
 an analog automatic gain control (AGC) amplifier to attenuate an input
 signal X prior to being digitized to a signal Y by an analog-to-digital
 converter, said automatic gain control circuit comprising: a programmable
 loop gain for scaling the signal Y to a first prescribed level during a
 first mode of operation and to a second prescribed level during a second
 mode of operation; and means for converting the scaled signal Y into an
 analog gain control signal for input to the analog AGC.
 In accordance with another aspect of the present invention there is
 provided an automatic gain control circuit for a modem receiver, said
 receiver having an analog automatic gain control (AGC) amplifier to
 attenuate an input signal X prior to being digitized to a signal Y by an
 analog-to-digital converter, said automatic gain control circuit
 comprising: (a) means for obtaining an AGC signal from the signal Y; (b)
 means for subtracting the AGC signal from a prescribed reference signal to
 form a delta signal; (c) scaling means for reducing the delta signal by a
 prescribed value; (d) an integrator for integrating the scaled delta
 signal to form an AGC level control signal; and (e) conversion means for
 converting the AGC level control signal to an analog AGC control signal
 for the analog AGC amplifier to attenuate the input signal X.
 In accordance with another aspect of the present invention there is
 provided an a method of attenuating an input signal X in an automatic gain
 control circuit of a modem receiver, said receiver having an analog
 automatic gain control (AGC) amplifier to attenuate the input signal X
 prior to being digitized to a signal Y by an analog-to-digital converter,
 the method comprising the steps of: (a) scaling the signal Y to a first
 prescribed level during a first mode of operation and to a second
 prescribed level during a second mode of operation; and (b) converting the
 scaled signal Y into an analog gain control signal for input to the analog
 AGC.

DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION
 A portion of a receiver 10 of a modem is illustrated in FIG. 1. An input
 signal X is processed through analog filters 12 to condition the input
 signal X. The analog filters 12 reject and attenuate unwanted signals,
 such as other ADSL signals, feed-through signals from a transmitter
 through hybrid four-to-two wire interfaces, RF interference (e.g. from AM
 broadcasts), out-of-band noises, and the like.
 The filtered input signal X is then processed through an analog automatic
 gain control (AGC) amplifier 14 to control the gain of the input signal X.
 After processing through the analog AGC 14 the signal is digitized by an
 analog-to-digital converter 16 to produce a digital signal Y.
 The digital signal Y is processed by an AGC control signal circuit 24 to
 produce an analog control signal G, that is provided to the analog AGC 14
 to dictate the amount of attenuation/gain required to bring the level of
 the input signal X to a desired level. Typically, it is desirable for the
 input signal X to be brought to near the full scale of the ADC 16, so that
 a majority of the ADC dynamic range can be exploited.
 Due to the range of different telecommunications environments in which
 modems operate and the varying amounts of possible interference, the
 strength of the input signal X can vary considerably. To regulate the
 signal strength at the input to the ADC 16 the present invention provides
 the AGC control signal circuit 24 to provide the control signal G.sub.c to
 the analog AGC 14 to modulate the gain of the input signal X. Three
 different implementations 24a, 24b, and 24c of the AGC control signal
 circuit 24 are described in detail below in conjunction with FIGS. 2 to 4.
 An AGC control signal circuit 24a according to a first embodiment of the
 present invention is illustrated in FIG. 2. An absolute value filter 30
 receives as input the digital signal Y to produce an output signal Vabs,
 which in the present embodiment is also a Vagc signal.
 The Vagc signal is subtracted from a reference/threshold Vref signal to
 obtain a delta signal (delta=Vref-Vagc). The delta signal is processed by
 a programmable loop gain (PLG) 32 characterised by the following scaling
 factor equation:
EQU 2.sup.-k.sup..sub.1
 where k.sub.1 represents a gain factor.
 The loop gain 32 scales down the delta signal by a prescribed value to
 produce a signal x for use by an integrator (INT) 34. For example, for a
 16QAM system the gain k.sub.1 of scaling factor defined by Eq. 1 varies
 over a range of k.sub.1 =15 to 18. The values of 2.sup.-k.sup..sub.1 are
 approximately inversely proportional of time constants of the AGC loop
 circuit (characterised by analog AGC 14, ADC 16 and control circuit 24).
 Therefore, for large k.sub.1 the AGC loop circuit is slow and is less
 noisy in steady state.
 The scaled delta signal is used as a stimulus for the integrator 34. The
 INT 34 takes the form of an up/down counter with variable step size and is
 characterised by the following equation:
EQU a(n)=b(n)+a(n-1)
 where a represents input to the integrator, b represents output from the
 integrator (AGC level control signal), and n is a sample number (i.e.
 time).
 The programmable loop gain 32 and the integrator 34 incorporate two main
 operating modes that can be programmably modified by the values of the
 controlling parameter k.sub.1. For example, during initialization/start-up
 operation the PLG 32 has high gain 2.sup.-k.sup..sub.1 (i.e. small
 k.sub.1), and during steady state operation the gain 2.sup.-k.sup..sub.1
 is reduced (i.e. increase k.sub.1) to minimize steady state noise
 introduced to the demodulator 10. In summary, the programmable loop gain
 32 can be configured to provide fast acquisition time (with large gain
 ripple), and then after convergence, switch to a slow mode with small
 steady state gain ripple. The PLG 32 also supports a wide dynamic range.
 The output of the integrator 34 is an agc level control signal that is
 converted into a single bit control signal by a sigma-delta modulator 36
 known in the art. The 1-bit sigma-delta digital signal is output from the
 modulator 36 at a multiple of the ADC sampling rate and passed through an
 analog reconstruction filter 38 to produce the control signal G.sub.c. The
 control signal G.sub.c is used by the analog AGC 12 to control the gain of
 the input signal X as described above.
 An AGC control signal circuit 24b according to a second embodiment of the
 present invention is illustrated in FIG. 3. In circuit 24b the Vabs signal
 is obtained taking the absolute value of the digital signal Y. The Vabs
 signal is processed by a leaky peak detector 50 to obtain a Vlpk signal
 which is then multiplexed with the Vabs signal by a multiplexer (MUX) 52
 to obtain the Vagc signal. Therefore, the output from the MUX 52 (the Vagc
 signal) is either the Vabs signal, if the leaky peak detector 50 is
 bypassed, or the Vlpk signal. The Vagc signal that is then processed as
 discussed in conjunction with circuit 24a of FIG. 2 to produce the control
 signal G.sub.c for the analog AGC 14.
 The peak detector 50 is used to detect a peak Px of the Vabs signal. The
 peak detector 50 incorporates a leak to ensure that a selected peak value
 tracks the level of the Vabs signal so that an originally estimated peak
 does not remain fixed at the same level. The detector 50 also reduces
 rapid fluctuations in the Vabs signal. The leaky peak calculation is
 characterised by the following equation:
EQU Vlpk=Px-2.sup.-k Px,
 where Px is a selected peak and 2.sup.-k is a leakage factor and is
 programmable over a range of k=4 to k=8.
 The range of k allows control over leak speed (i.e. how quickly the
 detector 50 "forgets" the previous peak). The term "leak" refers to
 tracking the true peak of the Vabs signal, then allowing the peak to
 slowly reduce in time provided the following samples are smaller than the
 previous peak, otherwise a new peak will be declared and leaked.
 An AGC control signal circuit 24c according to a third embodiment of the
 present invention is illustrated in FIG. 4. The circuit 24c introduces a
 low pass filter 54 and a multiplexer 56 to the circuit 24b of FIG. 3. The
 low pass filter 54 is characterised by the following equation:
 ##EQU1##
 where k.sub.2 represents the pole of the filter and Z.sup.-1 represents a
 phase shift
 In the circuit 24c the Vabs signal is processed by the leaky peak detector
 50 to obtain the Vlpk signal which is then multiplexed with the Vabs
 signal by the multiplexer 52 to obtain a Vlpkm signal (i.e. Vlpkm is
 either Vabs or Vlpk).
 The peak detector 50 is used to detect a peak x of the Vabs signal. The
 peak detector 50 incorporates a leak to ensure that the selected peak
 values track the agc level control signal, as discussed in conjunction
 with circuit 24b .
 The Vlpkm signal is integrated by the low pass filter 54 to produce a Vlpf
 output signal that is multiplexed with the Vlpkm signal by the multiplexer
 56 to produce the Vagc signal (i.e. Vagc is either (a) Vabs if detector 50
 and LPF 54 are both bypassed, (b) Vlpk if Vabs is processed through
 detector 50, and LPF 54 is bypassed, or (c) Vlpf is Vabs processed through
 both the detector 50 and the LPF 54). The Vagc signal is then processed,
 as discussed in conjunction with circuit 24a of FIG. 2, to produce the
 control signal CS for the analog AGC 14.
 In summary, the agc control signal circuits 24a-c provide the following
 features:
 (a) multiple settings for the gain (by changing k.sub.1) of the
 programmable loop gain 32 are supported that change for
 initialization/start-up and converged states to allow for faster initial
 acquisition/convergence with higher gains and low steady-state ripple with
 small gains.
 (b) the addition of a leaky peak detector 50 (circuit 24b) provides the
 possibility of adjusting the signal level with respect to its peak rather
 than to its absolute average value.
 (c) the addition of a low pass filter 54 with the leaky peak detector 50
 (circuit 24c) provides an improved estimate of the signal level with
 respect to a threshold.