In described examples, each node between adjacent capacitive elements of a stack of series-coupled capacitive elements is biased during a reset mode, where each of the capacitive elements includes piezoelectric material. A strain-induced voltage is generated across each of the capacitive elements. Each of the strain-induced voltages is combined to generate a piezoelectric-responsive output signal during a sensing mode at a time different from the time of the reset mode.

BACKGROUND

Vibration sensors can include piezoelectric-based materials. Such materials can include piezoelectric ceramics, such as lead zirconate titanate (PZT). Piezoelectric devices can include a piezoelectric sensor coupled to an analog front end (AFE) for signal conditioning, such that the piezoelectric devices can monitor or otherwise respond to relatively small signals generated by the piezoelectric sensor. However, the electrical signals generated by the piezoelectric sensor can be generated in response to a variety of environmental stimuli, such as vibration or other forces or environmental effects affecting electrical characteristics of the piezoelectric sensors. The response of the piezoelectric sensor to the varying stimuli can obscure smaller signals generated by the piezoelectric sensor in response to a particular environmental stimulus.

SUMMARY

In described examples, each node between adjacent capacitive elements of a stack of series-coupled capacitive elements is biased during a reset mode, where each of the capacitive elements includes piezoelectric material. A strain-induced voltage is generated across each of the capacitive elements. Each of the strain-induced voltages is combined to generate a piezoelectric-responsive output signal during a sensing mode at a time different from the time of the reset mode.

DETAILED DESCRIPTION

Piezoelectric sensors (e.g., piezo sensors) are sensitive to strain effects (e.g., piezo-electric effects) as well as to temperature changes (e.g., pyro-electric effects). As described herein, the portion of a sensor signal due to changes in strain is relatively fast changing and includes relatively small strain-related signal levels. (The term “portion” can mean an entire portion or a portion that is less than the entire portion.) In contrast, the portion of a sensor signal due to changes in temperature is relatively slow changing and includes relatively large temperature-related signal levels. For example, the piezo sensor signal changes due to changes in operating temperature can be orders of magnitude greater than the piezo sensor signal changes due to changes in strain (e.g., due to vibration).

To detect motion, example piezoelectric devices described hereinbelow can measure the portion of piezo sensor signals due to strain changes by suppressing the effects of the piezo sensor signal caused by temperature changes. “Stacking” (e.g., arranging and/or being coupled in series) several piezo sensor elements in a serial chain can boost portions of the sensor signal that are produced in response to changes in strain on the piezoelectric devices. To help suppress the temperature response (e.g., which otherwise can obscure the relatively smaller strain-induced electrical responses), each sensor element can be reset to a nominal voltage at periodic intervals. Periodically resetting (e.g., periodically biasing to a common voltage) each of the sensor elements shortens the time window over which pyroelectric responses can occur. The periodic reset function can effectively function in a similar manner (e.g., function as) a high pass filter, which can effectively remove the relatively slow-changing portions of the piezo sensor signal that result from temperature drifting over longer periods of time.

Some example piezo devices described hereinbelow can include piezo sensor embedded in a silicon substrate. Embedding the piezo sensor on silicon can allow the stacking of the sensor elements to boost the signal response, and yet maintain individual control of each of the sensor elements, such that portions of the piezo sensor signal that result from changes in temperature can be suppressed. As described herein, an automatic reset (e.g., periodic reset) of each sensor element of an embedded piezoelectric sensor facilitates the detection of a change in motion (e.g., over longer periods of time) by reducing the portions of the piezo sensor signal that result from changes in temperature.

In various apparatus and methods of example piezo devices described hereinbelow, a system of an example piezo device can: 1) select a “wake” or a “sleep” operating mode for a microcontroller unit (MCU) in response to a respective detected change in motion or a determination of lack of a change in motion; 2) select a “wake” or a “sleep” operating mode for a microcontroller unit (MCU) in response to a strain sensor sensing a respective detected change in motion or sensing a lack of a change in motion; 3) select a “wake” or a “sleep” operating mode for a microcontroller unit (MCU) in response to a piezo-electric based strain sensor for sensing a respective detected change in motion or for determining a lack of change in motion piezo-electric based strain sensor; and/or 4) select a “wake” or a “sleep” operating mode for a microcontroller unit (MCU) in response to an integrated (e.g., integrated on a common substrate) PZT piezo-electric based strain sensor for sensing a respective detected change in motion or for determining a lack of a change in motion.

FIG. 1is a block diagram of an example piezoelectric sensor100in a differential configuration. For example, the sensor100can be generally described as including three stages: a first stage, such as a pre-conditioning circuit120; a second stage, such as a stack of piezoelectric sensor elements (e.g., piezoelectric capacitive elements), shown collectively as piezoelectric capacitor stack130; and a third stage, such as a sensor output circuit140. Each of the stages as described herein can be implemented as a single integrated circuit in which the stages and other elements are mutually integrated into a monolithic structure, such as a single integrated circuit substrate. A piezoelectric sensing element can be referred to as a “capacitive element” (or sometimes “capacitor”) because of its capacitive behavior when coupled to an electrical circuit.

The example pre-conditioning circuit120includes an initialization finite state machine (INIT FSM)122. The INIT FSM122can include logic gates, memory, and/or a controller or other processor. The INIT FSM122achieves FSM state transitions (e.g., as sequentially ordered operations) for selectively asserting a number 2n+1 “poling” (e.g., for polarizing) signals S0through S2nfor polarizing (e.g., repolarizing) capacitor elements (e.g., elements C0through C2n) of the stack130. Each of the poling signals S0through S2n(e.g., when asserted) is operable to polarize (e.g., including a partially polarize) a respective capacitor element in stack130. Accordingly, the INIT FSM122is operable to configure the sensor100in various operational modes (and is not limited only to “initialization” functions).

In an example, the INIT FSM122receives four input signals: 1) a clock signal CLK; 2) a reset signal FSM_RST; 3) a negative polarization signal INIT0; and 4) a positive polarization initialization signal INIT1. The INIT FSM122also includes a number of output signals, such as the poling signals S0through S2n. Each of the poling signals S0through S2nis coupled as an input to a respective buffer of buffer bank124, and each paralleled output of the buffer bank124is coupled as an input to a respective switch (e.g., low leakage switch) in switch bank126. Each respective switch of switch bank126can be instantiated as at least one transistor as described hereinbelow with reference toFIG. 2.

The INIT FSM122also generates output control signals, such as an enable signal and a busy signal, for controlling the stack130. The enable signal EN (and its complement, EN) is generated for controlling (e.g., individually or collectively) each of the low leakage switches in the switch bank126, as described hereinbelow. The reset circuit110is responsive to the enable signal EN to assert enable signals E1, E2, and E3(ofFIG. 2) in various modes, such as: a polarization mode (e.g., described hereinbelow with respect toFIG. 3); a sensing (e.g., active) mode (e.g., described hereinbelow with respect toFIG. 4); and a sensor reset mode (e.g., described hereinbelow with respect toFIG. 5). The BUSY output signal is asserted to indicate that the INIT FSM122is in an active state (e.g., is not in an idle state).

The stack130includes a chain of number 2n of serially-coupled capacitors, C0through C2n. For example, an upper electrode of capacitor C0is coupled to a lower electrode of capacitor C1(not explicitly shown), an upper electrode of capacitor C1is coupled to a lower electrode of capacitor C2(not explicitly shown), and so forth on through to where an upper electrode of capacitor Cn−2(not explicitly shown) is coupled to a lower electrode of capacitor Cn−1. The upper electrode of capacitor Cn−1is coupled to a lower electrode of capacitor Cn+1, and so forth on through to where an upper electrode of capacitor C2n−1(not explicitly shown) is coupled to a lower electrode of capacitor C2n.

In various examples, the value of n can be selected in accordance with the examples described herein, and can be selected from a range, such as 5≤n≤32. Also, the number of capacitors in the stack130can be one less than the total number of buffers in the buffer bank124(and can be one less than the total number of the low leakage switches LLS in the switch bank126).

In various examples, each capacitor in stack130is a ferroelectric capacitor (FeCap).

Also, in various examples, the capacitors of the stack130are formed on a single semiconductor device, in which the lower electrode of each capacitor is in a same first fabrication layer, each capacitor ferroelectric layer is in a same second fabrication layer, and the upper electrode of each capacitor is in a same third fabrication layer, wherein each upper electrode is coupled (e.g., electrically coupled through a “via” that extends vertically between fabrication layers) to a next capacitor lower electrode (e.g., and so on until the upper electrode of the end capacitor is encountered). Accordingly, environmental factors, such as processing, temperature, and physical stresses, are more uniformly applied across the capacitors of the stack130, which can provide greater accuracy in the piezoelectric response achieved by stack130when applying the techniques and circuits described herein.

The end terminals (e.g., outputs or output nodes) of terminal capacitive elements of the stack130are switchably coupled to respective inputs (e.g., input terminals) of the differential amplifier142. For example, the lower electrode of capacitor C0is switchably coupled (as well as the output of low leakage switch LLS0described hereinabove) through a first (e.g., lower) stack switch SLSto a noninverting terminal of the amplifier142, whereas the upper electrode of capacitor C2nis coupled (as well as the output of low leakage switch LLSndescribed hereinabove) through a second (e.g., upper) stack switch SUSto the inverting terminal of the amplifier142. For example, the first stack includes at least three capacitive elements coupled in series, and the second stack includes at least three capacitive elements coupled in series. Additionally, the center tap of the stack130is switchably coupled to the reference voltage (e.g., nominal voltage) VREF via a third (e.g., center) stack switch SREF(reference switch), described hereinbelow. Each of the stack switches SLS, SUSand SREFis controlled by ĒN: that is, when ĒN is asserted, each such switch closes (such as during a sensing mode); and when ĒN is de-asserted, each such switch opens (such as during a polarization mode). (Additionally, a sensor reset mode is described hereinbelow with at least respect toFIG. 5.)

The sensor output circuit140includes the amplifier142(which can optionally include multiple amplification stages for greater gains). The amplifier is signal amplification circuitry for differentially generating an output signal in response to first and second input terminals. The amplifier142is powered by two rail voltages (which are not shown, but are inherent to active circuitry), which can be referred to as VDD(e.g., where VDDis the high-side voltage) and VSS(e.g., where VSScan be the low-side voltage, or simply, ground). The voltage reference VREF is a voltage that is between (e.g., halfway between) the rail voltages of amplifier142. The output node of the amplifier142VOUTis the piezoelectric sensor signal.

As described herein, the sensor100includes three modes: a polarization mode, a sensing mode and a sensor reset mode. In various examples, each of the three modes is performed within a time (e.g., time period) that is different from the time within another of the other two modes is performed.

In a first mode (e.g., the polarization mode), the pre-conditioning circuit120co-aligns the ferroelectric polarization of capacitors C0through C2nin a same direction (e.g., direction of polarity) by applying the same voltage across each individual capacitor element. The resulting aligned polarity enhances the constructive addition of sensitivity of each capacitor, for example, which improves a signal-to-noise (SNR) response. Operation in the first mode (e.g., the polarization mode) can be executed as a part of the manufacturing process of sensor100: for example, the polarization mode can be initiated by the manufacturer and before the release of the device to a user/consumer and before deployment to the field.

Additionally, the operation in the polarization mode can be initiated after deployment, such that a subsequent reconditioning of the polarization in the stack130can be achieved in the field. Accordingly, the sensor100can be freshly repolarized to align the polarization of the capacitor elements of stack130in a same direction, which offsets depolarization that can occur due to influences of time, normal or abnormal operation, and environmental effects. Operation in the polarization mode can be repeated (e.g., in response to an analysis of the piezo sensor signal by a processor), such that the SNR of the piezo sensor signal can be periodically improved (e.g., by repeatedly offsetting the degradation of the polarization of the capacitor elements of stack130that can occur over time). Operation of the sensor100in the polarization mode is described hereinbelow with respect toFIG. 2andFIG. 3.

In a second mode (e.g., the piezoelectric sensing mode), the sensor100is arranged to respond to (e.g., sense) environmental stimuli by measuring the effect of such stimuli upon the piezoelectric material of stack130. For example, the environmental stimuli produce various responses in the piezo sensor signal VOUT. The piezo sensor signal VOUTincludes indications of changes in at least one condition of the environmental stimuli imposed on the piezoelectric material.

Piezoelectric sensors operating in the piezoelectric sensing mode can be used in various applications. Examples of such applications include detecting the change of strain, pressure, stress, acceleration, temperature (using the pyroelectric behavior of the sensing material), or force, where the such changes are imposed on the stack130and converted by amplifier142into the piezo sensor signal VOUT.

As described herein, operating in the piezoelectric sensing mode to generate the piezo sensor signal VOUTcan be initiated after completing operation in the polarization mode. Operating in the piezoelectric sensing mode can be initiated after completing a pre-conditioning by the manufacturer of sensor100, or, after completing one of the repeated reconditioning operations to repolarize the capacitor elements of the stack130. Operation of the sensor100in the piezoelectric sensing mode is described herein below with respect toFIG. 2andFIG. 4.

In a third mode (e.g., the sensor reset mode), the sensor100is reset to a nominal voltage (e.g., VREF) at periodic intervals. The sensor100can be reset in the reset mode to a nominal voltage by the pre-conditioning circuit120being arranged to periodically bias each of the nodes between adjacent capacitive elements of a first and second stack of the capacitive elements. For example, the sensor100can be automatically reset at periodic intervals (e.g., defined intervals as determined by a timer function of the INIT FSM122). In one example, the sensor100is automatically reset at periodic intervals to reduce temperature-induced effects on the output of the piezo sensor signal VOUT. In another example, a high-pass filter (not shown) can be coupled to the output(s) of each sensor element of the stack130. In another example, a processor can be arranged to analyze the sensor100response (e.g., piezo sensor signal VOUT) and separate the signal components of the piezo sensor signal VOUTby digitizing and performing post-processing signal analysis on the piezo sensor signal VOUT. In other examples, various combinations of the periodic resetting of the capacitor elements of the stack130, the high-pass filtering, and the post-processing analysis can be used to increase the discrimination of the strain-induced portions of the piezo sensor signal VOUT.

FIG. 2is a schematic diagram of an example switch circuit200for each low leakage switch LLS0through LLS2nofFIG. 1. Each such switch circuit200is formed so as to minimize leakage from the respective capacitor stack node through the switch circuit200while operating in a sensing mode. In the sensing mode, any relatively small change in charge across the stack130generated by capacitors Cxand/or Cx+1(e.g., within the stack130) is conserved (e.g., which can improve the SNR of the sensed output voltage VOUT). Accordingly, the generated voltages are isolated from being coupled by any leakage path to the poling circuitry or voltage references, such that the capacitors Cxand/or Cx+1are isolated during the sensing mode.

Switch circuit200includes a node ND1coupled between capacitors Cxand Cx+1(e.g., of any two adjacent capacitors of stack130) and a drain (e.g., output) of a transistor Q1, which is an isolated (e.g., P-well isolated) NMOS transistor. The gate of transistor Q1is coupled to the E2signal, the source (e.g., input) of transistor Q1is coupled to a node ND2, and the backgate of transistor Q1is coupled to a node ND3. The node ND2is further coupled to the drain of a transistor Q2, the gate of transistor Q2is coupled to the E1signal, and the source of transistor Q2is coupled to an output of a respective buffer BUF, described hereinabove with respect toFIG. 1. Node ND2is further coupled to a source of a transistor Q3, which includes a gate coupled to E3and a drain coupled to VREF. Node ND3is further coupled to a source of a transistor Q4, which includes a gate coupled to E3and a drain coupled to VREF. The node ND3is also coupled to a source of a transistor Q5, which includes a gate coupled to E1and a drain coupled to ground. The node ND3is connected to the isolated p-well of Q1and is arranged to control the back biasing voltage.

The operation of the switch circuit200is described hereinbelow with respect toFIG. 3,FIG. 4, andFIG. 5. The polarization mode is described hereinbelow with respect toFIG. 3. The sensor active mode is described hereinbelow with respect toFIG. 4. The sensor reset mode is described hereinbelow with respect toFIG. 5.

FIG. 3is a schematic diagram of an example switch circuit300arranged in a polarization mode. In the polarization mode the switch circuit300is arranged to selectively couple a polarization voltage to each of the nodes between adjacent capacitive elements of the first (or second) stack of the adjacent capacitive elements in a polarization mode. In the polarization mode, the signals E1and E2(as shown inFIG. 2) are asserted, which selectively closes transistors Q1, Q2, and Q5of the switch circuit300; whereas the signal E3is not asserted, such that the transistors Q3and Q4of the switch circuit300are open and not enabled. Accordingly, the buffer BUF is coupled to drive a poling signal Sxalong the source/drain (e.g., input/output) paths of transistors Q2and Q1to the respective node in stack130. Also during the polarization mode, the source of transistor Q5couples the p-well of transistor Q1to a ground potential, which enhances the transconductance of transistor Q1.

FIG. 4is a schematic diagram of an example switch circuit400arranged in a sensing mode. In the sensing mode, the signal E3(as shown inFIG. 2) is asserted, which selectively closes transistors Q3and Q4of the switch circuit300; whereas the signals E1and E2are not asserted, such that the transistors Q1, Q2, and Q5of the switch circuit400are open and not enabled. Accordingly, the source of the transistor Q1is decoupled from poling signal Sxgenerated by the respective buffer BUF. Instead, the transistor Q3couples the source of the transistor Q1to VREF, and the transistor Q4couples the backgate of the transistor Q1to VREF. Driving the source and backgate of the transistor Q1to the same potential (e.g., VREF) helps eliminate potential leakage paths from the capacitor sensor of stack130through transistor Q1because the multiple nodes being driven to the same potential VREF does not induce current flow (e.g., leakage). Accordingly, the switch400is a low-leakage switch that is configured to isolate the serial-coupled capacitors of the stack130from any poling signal or circuitry associated therewith. Isolating the serial-coupled capacitors of the stack130helps isolate the charge on each of the stack130capacitors against leakage, which in turn conserves charge for generating a more robust piezo sensor signal VOUT.

FIG. 5is a schematic diagram of an example switch circuit500arranged in a sensor reset mode. In the sensor reset mode, the signals E2and E3(as shown inFIG. 2) are asserted, which selectively closes transistors Q1, Q3, and Q4of the switch circuit500; whereas the signal E1is not asserted, such that the transistors Q2and Q5of the switch circuit500are open and not enabled. Accordingly, the source of the transistor Q1is decoupled from poling signal Sxgenerated by the respective buffer BUF. Instead, the transistor Q3couples the source of the transistor Q1to VREF, and the transistor Q4couples the backgate of the transistor Q1to VREF (e.g., Q4is arranged to bias the backgate of Q1). In the sensor reset mode, the transistor Q1is arranged to conduct, which couples the potential VREF at the source of the transistor Q1to a respective node (e.g., node ND1) between adjacent capacitors (e.g., two different capacitors electrically coupled via a common node) capacitors of the stack130. Transistor Q1is arranged to couple the potential VREF at the source of the transistor Q1to each of the nodes (e.g., node ND1) between adjacent capacitors of the stack130equalizes the charge of each of the stack130capacitors. Coupling the potential VREF at the source of the transistor Q1to each of the nodes resets the piezo sensor signal VOUT(e.g., resets with respect to voltages generated in response to pyroelectric effects). As described herein, periodically resetting the charges of each of the stack130capacitors helps reduce the effects (e.g., larger effects) of temperature drift upon the piezo sensor signal VOUT.

FIG. 6is a schematic diagram of an example wake-on-motion piezoelectric sensing system600. The system600includes the first oscillator651, and a second oscillator652. For example, the first oscillator651generates a first clock signal (not shown) having relatively long period (e.g., 1 ms), whereas the second oscillator652generates the second clock symbol (not shown) having a relatively short period (e.g., 0.025 ms). The first and second clock signals can be used to clock the pole (e.g., polarization) FSM653and the analog front end (AFE) FSM660. The first clock signal can be used to initiate the start of a sensor sample sequence (e.g., at a sampling frequency), whereas the second clock signal can be used to initiate (and/or coordinate) various events that follow the start of a particular operational mode (e.g., a sample-and-hold mode, a compare mode, or a sensor reset mode).

To begin operation of the system600, the pole FSM can be activated by control signals (e.g., INIT0or INIT1) to (re-)polarize the first capacitor stack671and a second capacitor stack672(which are coupled respectively to the non-inverting and the inverting inputs of the low noise amplifier673). The repolarized first and second capacitor stacks can be reset (as described herein above) in response to a sensor reset640signal, which normalizes the bias voltage (e.g., to VREF670) on each node between individual capacitors of the first and second capacitor stacks671and672. Normalizing the bias voltages initializes the first and second capacitor stacks671and672for operation in a sensing mode.

While components680are operating in a sleep mode, the first and second capacitor stacks671and672can be electrically isolated to accumulate changes in charge due to environmental effects. The accumulated changes in charge can be sensed to determine whether a strain stress induced due to movement of the system600has occurred, and if so, perform a wake-on-motion operation. The periodic sensing can be initiated in response to the first clock signal (e.g., output by OSC1651).

The changes in charge of the first and second capacitor stacks671and672can be sampled by coupling the outputs of the first and second capacitor stacks671and672to opposing inputs of the low noise amplifier (LNA)673. The net (e.g., combined) charge of the first and second capacitor stacks671and672can be measured by closing the stack switches SLS, SUSand SREFdescribed hereinabove with respect toFIG. 1during the sample period611(e.g., determined by Sample signal610) and the hold period621(e.g., determined by Hold signal620). The LNA673can be trimmed during calibration such that the offset of the LNA673is centered around the VREF potential. In an example system600, the LNA673includes a gain of around 400 percent.

The output of the LNA673(e.g., which can be the same as the piezoelectric sensor signal VOUT) is coupled to the input of the programmable gain amplifier (PGA)674. The output of the PGA674is coupled to measurement circuitry679, which can include the comparator (CMP)677, the digital-to-analog converter (DAC)676; and the gain of the mixer675. In other examples, the measurement circuitry679can include an analog-to-digital converter (ADC, not shown) coupled to a processor arranged to log (e.g., store in memory) and/or compare digital samples of the output of the PGA674.

The gain of the PGA674can be determined in response to: the rail voltages of the CMP677; one or two thresholds (e.g., upper and lower thresholds) generated by the DAC676; and the gain of the mixer675.

During time period631(e.g., determined by Compare signal630), the differential output of the first and second capacitors stack671and672are effectively compared against a first threshold. For example, the DAC676can be programmed with a first threshold (e.g., lower threshold) to determine (e.g., by operation of CMP677) whether the differential output of the first and second capacitors stack671and672has fallen below VREF by at least the first threshold. In a similar manner, the DAC676can be programmed with a second threshold (e.g., upper threshold) during a time period632to determine whether the differential output of the first and second capacitors stack671and672has risen above VREF by at least the second threshold. In one example, the first and second thresholds are voltages spaced equally around the voltage VREF coupled to the inverting input of the CMP677.

If the CMP677indicates a comparison result of either (1) the differential output of the first and second capacitors stack671and672has fallen below VREF by at least the first threshold or (2) the differential output of the first and second capacitors stack671and672has risen above VREF by at least the second threshold, the CMP677asserts an activation signal (e.g., the wake-on-movement interrupt request, WOM IRQ), which is coupled to activate components680previously in a sleep mode state. The AFE FSM660can control the sequencing of the first and second thresholds for the comparisons.

The components680can be in a housing separate from a housing including the strain sensors (e.g., the individual capacitors of the first and second capacitor stacks671and672). (The term “housing” can mean a package or a sealed subassembly/assembly, which can include control circuitry and sensors in a local environment that is sealed from an outside environment.) The components680to-be-activated can include components such as system processor681and system memory/peripherals682that are in a state of reduced operational power consumption during a sleep mode.

After sensing (e.g., in a sensing mode) the first and second capacitor stacks are reset during time period641(e.g., for operating in a reset sensor mode) indicated by the sensor reset640signal. The reset normalizes the bias voltage on each node between individual capacitors of the first and second capacitor stacks671and672(e.g., such that the charge on each capacitor is equalized). As described herein, the resetting of the capacitor stacks (e.g.,671and672) after operating in the sensing mode, limits (or otherwise shortens) a time period during which accumulated thermal “creep” or drift could otherwise induce a sufficiently strong combined output of the first and second capacitors stack671and672, such that a false WOM IRQ (wake-on-motion interrupt request) is asserted. For example, the time period during which accumulated thermal “creep” (e.g., changes in temperature) could otherwise occur is limited to time period601(which is, in the example, less than 1 ms). The length of the time period601can be adjusted to control the high pass frequency cutoff point of the piezoelectric sensor signal: for example, shortening the length of the time period601increases the high (e.g., higher) frequency content of the piezoelectric sensor signal (which reduces the amount of the lower frequency temperature-induced information in the piezoelectric sensor signal).

After a period of relative inactivity (e.g., during the first portion of time period, in which power can be conserved by circuitry operating in a sleep mode), another polarization/sensing/reset cycle can be performed (the polarization mode is optional, and can be initiated over longer periods than illustrated). For example, the first and second capacitor stacks671and672are coupled to opposing inputs of the LNA673by closing the stack switches SLS, SUSand SREFduring the sample period612(e.g., determined by Sample signal610) and the hold period622. During time period633, the combined output of the first and second capacitors stack671and672are effectively compared against the first threshold. During time period634, the combined output of the first and second capacitors stack671and672are effectively compared against the second threshold. Accordingly the combined output signal of the first and second capacitors stack671and672is “thresholded” by comparing the combined output signal of the first and second capacitors stack671and672against at least one threshold (e.g., where a system event—such as a wake event—can be generated in response to a comparison of the combined output signal against a threshold).

After the sensing period (e.g., during time periods633, and634), the first and second capacitor stacks671and672can be reset (as described hereinabove) during time period642. Resetting the first and second capacitor stacks671and672renormalizes the bias voltage of each node between adjacent capacitors of the first and second capacitor stacks671and672(which in turn truncates the time period available for changes in temperature to affect the sensing voltages generated by the first and second capacitor stacks671and672). Accordingly, temperature change-induced voltages of the first and second capacitor stacks671and672can be reduced in response to periodically biasing each node between adjacent capacitive elements of the first and second capacitor stacks671and672during successive reset node periods.

In a similar manner, the sensing voltages of the first and second capacitor stacks671and672can be periodically sampled (e.g., when the system processor681and system memory/peripherals682are in a wake mode) to determine a lack of motion. In response to the determined lack of motion, the measurement circuitry679can assert a deactivation signal, such that the system processor681and system memory/peripherals682can be placed in a sleep mode (e.g., to conserve power when not actively being used by a user).

FIG. 7is a waveform diagram of responses to temperature change in a first test scenario700of an example piezoelectric sensing system. The test scenario700includes an example piezoelectric sensor signal waveform710generated in response to real-world measurements of an example piezoelectric sensor (such as example sensor100) periodically operating in a reset sensor mode, such as described hereinabove with respect toFIG. 6.

For example, the waveform710can be generated as the output of the LNA673, where the waveform710includes a voltage level of around 300 mV when no stimulus (e.g., change in strain or temperature) is applied. At around 1600 ms into the test scenario, the example piezoelectric sensor is subjected to a relatively sudden change (e.g., impulse) in temperature, which results in a response731that includes a rise in temperature of greater than 4 degrees C. in around 400 ms, as well as a gradual decrease in temperature thereafter (as shown by temperature waveform730).

The response711(shown in waveform712) of the example piezoelectric sensor to the applied temperature impulse is limited in response to the periodic reset of the example piezoelectric sensor. For example, the temperature response of the example piezoelectric sensor as amplified by the LNA673is around 35 mV peak-to-peak (e.g., where the reset of the example piezoelectric sensor is periodically applied at intervals of 50 ms).

In contrast, the waveform720is an example piezoelectric sensor signal waveform generated by example piezoelectric sensor (such as example sensor100) that is not periodically reset (e.g., operated without normalizing each of the nodes between adjacent capacitors of the first and second capacitor stacks671and672). For example, the temperature response721of the example piezoelectric sensor as amplified by the LNA673(e.g., without piezoelectric sensor reset) is around 165 mV peak-to-peak. Further, the piezoelectric sensor (e.g., without reset) recovers over a period of thousands of milliseconds (e.g., several seconds). Accordingly, the reset of the example piezoelectric sensor lessens the impact of temperature upon the example piezoelectric sensor in extent (e.g., voltage swing) and time (e.g., limited to the period between successive reset operations).

FIG. 8is a waveform diagram of responses to temperature change in a second test scenario800of an example piezoelectric sensing system. The test scenario800includes an example piezoelectric sensor signal waveform810generated in response to real-world measurements of an example piezoelectric sensor (such as example sensor100) periodically operating in a reset sensor mode, such as described hereinabove with respect toFIG. 6.

For example, the waveform810can be generated as the output of the LNA673, where the waveform810includes a voltage level of around 300 mV when no stimulus (e.g., change in strain or temperature) is applied. At around 1 second into the test scenario, the example piezoelectric sensor is subjected to a (e.g., gradual) rise831in temperature of around 10 degrees C. per second for around 2 seconds thereafter (as shown by temperature waveform830).

The response811of the example piezoelectric sensor to the applied temperature impulse is limited in response to (e.g., as a result of) the periodic reset of the example piezoelectric sensor. For example, the temperature response (to the rise831) of the example piezoelectric sensor as amplified by the LNA673is around 120 mV peak-to-peak (e.g., where the reset of the example piezoelectric sensor returns the voltage output from a low peak back to the original peak during each reset).

In contrast, the waveform820is an example piezoelectric sensor signal waveform generated by example piezoelectric sensor (such as example sensor100) that is not periodically reset (e.g., operated without normalizing each of the nodes between adjacent capacitors of the first and second capacitor stacks671and672). For example, the temperature response of the example piezoelectric sensor as amplified by the LNA673(e.g., without piezoelectric sensor reset) falls from the nominal voltage of 300 mV and “rails out” (e.g., by falling to a low limit defined by the lower voltage rail of the LNA673). The “railing out” effect limits the effective dynamic range of the LNA673, such that (for example) responses to changes in strain by the piezoelectric sensor (e.g., operating without reset) could not (and, hence, would not) be detected by the comparator. Accordingly, the reset of the example piezoelectric sensor increases the sensitivity of the example piezoelectric sensor (and associated circuitry) over wider ranges of temperature excursions.

In described examples, a pre-conditioning circuit (e.g., state machine) pre-conditions (e.g., biases) the sensor material (e.g., piezoelectric) so as to maximize and stabilize sensitivity over time and temperature. Additionally, the self-biasing of the amplifier minimizes leakage to extend low frequency performance range (as compared against relatively complicated charge amplifier circuits). Further, the described examples can be arranged on a single semiconductor (e.g., silicon) integrated circuit chip, which provides provide a full solution on a single substrate.

Various described examples include an integrated silicon device that includes a piezoelectric-based sensor array, sensor pre-condition, ultra-low leakage switches and signal amplification for strain-change detection, as a single silicon solution that can replace a sensor (which can be formed monolithically or assembled using discrete components) and AFE signal chain. Accordingly, various described examples can also facilitate reduced power consumption and help avoid off-chip and input/output related parasitics. Some of the various described examples include the ability to re-condition (e.g., repolarize) sensing material (e.g., PZT) to compensate for various effects, including the passage of time and changes in temperature.