Decoding system and physical layout for analog neural memory in deep learning artificial neural network

Various embodiments of word line decoders, control gate decoders, bit line decoders, low voltage row decoders, and high voltage row decoders and various types of physical layout designs for non-volatile flash memory arrays in an analog neural system are disclosed. Shared and segmented embodiments of high voltage row decoders are disclosed.

FIELD OF THE INVENTION

Improved decoding systems and physical layouts are disclosed for analog neural memory systems that utilize non-volatile memory cells.

BACKGROUND OF THE INVENTION

Artificial neural networks mimic biological neural networks (the central nervous systems of animals, in particular the brain) and are used to estimate or approximate functions that can depend on a large number of inputs and are generally unknown. Artificial neural networks generally include layers of interconnected “neurons” which exchange messages between each other.

FIG. 1illustrates an artificial neural network, where the circles represent the inputs or layers of neurons. The connections (called synapses) are represented by arrows, and have numeric weights that can be tuned based on experience. This makes neural networks adaptive to inputs and capable of learning. Typically, neural networks include a layer of multiple inputs. There are typically one or more intermediate layers of neurons, and an output layer of neurons that provide the output of the neural network. The neurons at each level individually or collectively make a decision based on the received data from the synapses.

One of the major challenges in the development of artificial neural networks for high-performance information processing is a lack of adequate hardware technology. Indeed, practical neural networks rely on a very large number of synapses, enabling high connectivity between neurons, i.e. a very high computational parallelism. In principle, such complexity can be achieved with digital supercomputers or specialized graphics processing unit clusters. However, in addition to high cost, these approaches also suffer from mediocre energy efficiency as compared to biological networks, which consume much less energy primarily because they perform low-precision analog computation. CMOS analog circuits have been used for artificial neural networks, but most CMOS-implemented synapses have been too bulky given the high number of neurons and synapses required.

Applicant previously disclosed an artificial (analog) neural network that utilizes one or more non-volatile memory arrays as the synapses in U.S. patent application Ser. No. 15/594,439, published as US Patent Publication No. 2017/0337466, which is incorporated by reference. The non-volatile memory arrays operate as an analog neural memory. The neural network device includes a first plurality of synapses configured to receive a first plurality of inputs and to generate therefrom a first plurality of outputs, and a first plurality of neurons configured to receive the first plurality of outputs. The first plurality of synapses includes a plurality of memory cells, wherein each of the memory cells includes spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate disposed over and insulated from a first portion of the channel region and a non-floating gate disposed over and insulated from a second portion of the channel region. Each of the plurality of memory cells is configured to store a weight value corresponding to a number of electrons on the floating gate. The plurality of memory cells is configured to multiply the first plurality of inputs by the stored weight values to generate the first plurality of outputs.

Each non-volatile memory cells used in the analog neural memory system must be erased and programmed to hold a very specific and precise amount of charge, i.e., the number of electrons, in the floating gate. For example, each floating gate must hold one of N different values, where N is the number of different weights that can be indicated by each cell. Examples of N include 16, 32, 64, 128, and 256.

One challenge in vector by matrix multiplication (VMM) systems is the ability to select a specific cell or groups of cells, or in some cases an entire array of cells, for erase, programming, and read operations. A related challenge is to improve, the use of physical space within a semiconductor die without losing functionality.

What is needed are improved decoding systems and physical layouts for analog neural memory systems that utilize non-volatile memory cells.

SUMMARY OF THE INVENTION

Improved decoding systems and physical layouts are disclosed for analog neural memory systems that utilize non-volatile memory cells.

DETAILED DESCRIPTION OF THE INVENTION

The artificial neural networks of the present invention utilize a combination of CMOS technology and non-volatile memory arrays.

Non-Volatile Memory Cells

Digital non-volatile memories are well known. For example, U.S. Pat. No. 5,029,130 (“the '130 patent”), which is incorporated herein by reference, discloses an array of split gate non-volatile memory cells, which are a type of flash memory cells. Such a memory cell210is shown inFIG. 2. Each memory cell210includes source region14and drain region16formed in semiconductor substrate12, with channel region18there between. Floating gate20is formed over and insulated from (and controls the conductivity of) a first portion of the channel region18, and over a portion of the source region14. Word line terminal22(which is typically coupled to a word line) has a first portion that is disposed over and insulated from (and controls the conductivity of) a second portion of the channel region18, and a second portion that extends up and over the floating gate20. The floating gate20and word line terminal22are insulated from the substrate12by a gate oxide. Bitline terminal24is coupled to drain region16.

Memory cell210is erased (where electrons are removed from the floating gate) by placing a high positive voltage on the word line terminal22, which causes electrons on the floating gate20to tunnel through the intermediate insulation from the floating gate20to the word line terminal22via Fowler-Nordheim tunneling.

Memory cell210is programmed (where electrons are placed on the floating gate) by placing a positive voltage on the word line terminal22, and a positive voltage on the source region14. Electron current will flow from the source region14(source line terminal) towards the drain region16. The electrons will accelerate and become heated when they reach the gap between the word line terminal22and the floating gate20. Some of the heated electrons will be injected through the gate oxide onto the floating gate20due to the attractive electrostatic force from the floating gate20.

Memory cell210is read by placing positive read voltages on the drain region16and word line terminal22(which turns on the portion of the channel region18under the word line terminal). If the floating gate20is positively charged (i.e. erased of electrons), then the portion of the channel region18under the floating gate20is turned on as well, and current will flow across the channel region18, which is sensed as the erased or “1” state. If the floating gate20is negatively charged (i.e. programmed with electrons), then the portion of the channel region under the floating gate20is mostly or entirely turned off, and current will not flow (or there will be little flow) across the channel region18, which is sensed as the programmed or “0” state.

Table No. 1 depicts typical voltage ranges that can be applied to the terminals of memory cell110for performing read, erase, and program operations:

TABLE NO. 1Operation of Flash Memory Cell 210 of FIG. 2WLBLSLRead 10.5-3V0.1-2V0VRead 20.5-3V0-2V2-0.1VErase~11-13V0V0VProgram1-2V1-3μA9-10V
“Read 1” is a read mode in which the cell current is output on the bit line. “Read 2” is a read mode in which the cell current is output on the source line terminal.

FIG. 3shows memory cell310, which is similar to memory cell210ofFIG. 2with the addition of control gate (CG) terminal28. Control gate terminal28is biased at a high voltage, e.g., 10V, in programming, low or negative in erase, e.g., 0 v/−8V, low or mid range in read, e.g., 0 v/2.5V. Other terminals are biased similarly to that ofFIG. 2.

FIG. 4depicts four-gate memory cell410comprising source region14, drain region16, floating gate20over a first portion of channel region18, a select gate22(typically coupled to a word line, WL) over a second portion of the channel region18, a control gate28over the floating gate20, and an erase gate30over the source region14. This configuration is described in U.S. Pat. No. 6,747,310, which is incorporated herein by reference for all purposes. Here, all gates are non-floating gates except floating gate20, meaning that they are electrically connected or connectable to a voltage source. Programming is performed by heated electrons from the channel region18injecting themselves onto the floating gate20. Erasing is performed by electrons tunneling from the floating gate20to the erase gate30.

Table No. 2 depicts typical voltage ranges that can be applied to the terminals of memory cell310for performing read, erase, and program operations:

TABLE NO. 2Operation of Flash Memory Cell 410 of FIG. 4WL/SGBLCGEGSLRead 10.5-2V0.1-2V0-2.6V0-2.6V0VRead 20.5-2V0-2V0-2.6V0-2.6V2-0.0VErase−0.5 V/0 V0V0 V/−8 V8-12V0VProgram1V1μA8-11V4.5-9V4.5-5V
“Read 1” is a read mode in which the cell current is output on the bit line. “Read 2” is a read mode in which the cell current is output on the source line terminal.

FIG. 5shows memory cell510, which is similar to memory cell410ofFIG. 4except that memory cell510does not contain an erase gate EG terminal. An erase is performed by biasing the substrate18to a high voltage and biasing the control gate CG terminal28to a low or negative voltage. Alternatively, an erase is performed by biasing word line terminal22to a positive voltage and biasing control gate terminal28to a negative voltage. Programming and reading is similar to that ofFIG. 4.

FIG. 6depicts a three-gate memory cell610, which is another type of flash memory cell. Memory cell610is identical to the memory cell410ofFIG. 4except that memory cell610does not have a separate control gate terminal. The erase operation (whereby erasing occurs through use of the erase gate terminal) and read operation are similar to that of theFIG. 4except there is no control gate bias applied. The programming operation also is done without the control gate bias, and as a result, a higher voltage must be applied on the source line terminal during a program operation to compensate for a lack of control gate bias.

Table No. 3 depicts typical voltage ranges that can be applied to the terminals of memory cell610for performing read, erase, and program operations:

TABLE NO. 3Operation of Flash Memory Cell 610 of FIG. 6WL/SGBLEGSLRead 10.5-2.2V0.1-2V0-2.6V0VRead 20.5-2.2V0-2V0-2.6V2-0.1VErase−0.5 V/0 V0V11.5V0VProgram1V2-3μA4.5V7-9V
“Read 1” is a read mode in which the cell current is output on the bit line. “Read 2” is a read mode in which the cell current is output on the source line terminal.

FIG. 7depicts stacked gate memory cell710, which is another type of flash memory cell. Memory cell710is similar to memory cell210ofFIG. 2, except that floating gate20extends over the entire channel region18, and control gate terminal22(which here will be coupled to a word line) extends over floating gate20, separated by an insulating layer (not shown). The erase, programming, and read operations operate in a similar manner to that described previously for memory cell210.

Table No. 4 depicts typical voltage ranges that can be applied to the terminals of memory cell710and substrate12for performing read, erase, and program operations:

“Read 1” is a read mode in which the cell current is output on the bit line. “Read 2” is a read mode in which the cell current is output on the source line terminal. Optionally, in arrays comprising rows and columns of memory cells210,310,410,510,610, or710, source lines can be coupled to one row of memory cells or to two adjacent rows of memory cells. That is, source line terminals can be shared by adjacent rows of memory cells.

In order to utilize the memory arrays comprising one of the types of non-volatile memory cells described above in an artificial neural network, two modifications are made. First, the lines are configured so that each memory cell can be individually programmed, erased, and read without adversely affecting the memory state of other memory cells in the array, as further explained below. Second, continuous (analog) programming of the memory cells is provided.

Specifically, the memory state (i.e. charge on the floating gate) of each memory cell in the array can be continuously changed from a fully erased state to a fully programmed state, independently and with minimal disturbance of other memory cells. In another embodiment, the memory state (i.e., charge on the floating gate) of each memory cell in the array can be continuously changed from a fully programmed state to a fully erased state, and vice-versa, independently and with minimal disturbance of other memory cells. This means the cell storage is analog or at the very least can store one of many discrete values (such as 16 or 64 different values), which allows for very precise and individual tuning of all the cells in the memory array, and which makes the memory array ideal for storing and making fine tuning adjustments to the synapsis weights of the neural network.

The methods and means described herein may apply to other non-volatile memory technologies such as SONOS (silicon-oxide-nitride-oxide-silicon, charge trap in nitride), MONOS (metal-oxide-nitride-oxide-silicon, metal charge trap in nitride), ReRAM (resistive ram), PCM (phase change memory), MRAM (magnetic ram), FeRAM (ferroelectric ram), OTP (bi-level or multi-level one time programmable), and CeRAM (correlated electron ram), without limitation. The methods and means described herein may apply to volatile memory technologies used for neural network such as SRAM, DRAM, and volatile synapse cell, without limitation.

Neural Networks Employing Non-Volatile Memory Cell Arrays

FIG. 8conceptually illustrates a non-limiting example of a neural network utilizing a non-volatile memory array of the present embodiments. This example uses the non-volatile memory array neural network for a facial recognition application, but any other appropriate application could be implemented using a non-volatile memory array based neural network.

S0is the input layer, which for this example is a 32×32 pixel RGB image with 5 bit precision (i.e. three 32×32 pixel arrays, one for each color R, G and B, each pixel being 5 bit precision). The synapses CB1going from input layer S0to layer C1apply different sets of weights in some instances and shared weights in other instances, and scan the input image with 3×3 pixel overlapping filters (kernel), shifting the filter by 1 pixel (or more than 1 pixel as dictated by the model). Specifically, values for 9 pixels in a 3×3 portion of the image (i.e., referred to as a filter or kernel) are provided to the synapses CB1, where these 9 input values are multiplied by the appropriate weights and, after summing the outputs of that multiplication, a single output value is determined and provided by a first synapse of CB1for generating a pixel of one of the layers of feature map C1. The 3×3 filter is then shifted one pixel to the right within input layer S0(i.e., adding the column of three pixels on the right, and dropping the column of three pixels on the left), whereby the 9 pixel values in this newly positioned filter are provided to the synapses CB1, where they are multiplied by the same weights and a second single output value is determined by the associated synapse. This process is continued until the 3×3 filter scans across the entire 32×32 pixel image of input layer S0, for all three colors and for all bits (precision values). The process is then repeated using different sets of weights to generate a different feature map of C1, until all the features maps of layer C1have been calculated.

In layer C1, in the present example, there are 16 feature maps, with 30×30 pixels each. Each pixel is a new feature pixel extracted from multiplying the inputs and kernel, and therefore each feature map is a two dimensional array, and thus in this example layer C1constitutes 16 layers of two dimensional arrays (keeping in mind that the layers and arrays referenced herein are logical relationships, not necessarily physical relationships—i.e., the arrays are not necessarily oriented in physical two dimensional arrays). Each of the 16 feature maps in layer C1is generated by one of sixteen different sets of synapse weights applied to the filter scans. The C1feature maps could all be directed to different aspects of the same image feature, such as boundary identification. For example, the first map (generated using a first weight set, shared for all scans used to generate this first map) could identify circular edges, the second map (generated using a second weight set different from the first weight set) could identify rectangular edges, or the aspect ratio of certain features, and so on.

An activation function P1(pooling) is applied before going from layer C1to layer S1, which pools values from consecutive, non-overlapping 2×2 regions in each feature map. The purpose of the pooling function is to average out the nearby location (or a max function can also be used), to reduce the dependence of the edge location for example and to reduce the data size before going to the next stage. At layer S1, there are 16 15×15 feature maps (i.e., sixteen different arrays of 15×15 pixels each). The synapses CB2going from layer S1to layer C2scan maps in S1with 4×4 filters, with a filter shift of 1 pixel. At layer C2, there are 22 12×12 feature maps. An activation function P2(pooling) is applied before going from layer C2to layer S2, which pools values from consecutive non-overlapping 2×2 regions in each feature map. At layer S2, there are 22 6×6 feature maps. An activation function (pooling) is applied at the synapses CB3going from layer S2to layer C3, where every neuron in layer C3connects to every map in layer S2via a respective synapse of CB3. At layer C3, there are 64 neurons. The synapses CB4going from layer C3to the output layer S3fully connects C3to S3, i.e. every neuron in layer C3is connected to every neuron in layer S3. The output at S3includes 10 neurons, where the highest output neuron determines the class. This output could, for example, be indicative of an identification or classification of the contents of the original image.

Each layer of synapses is implemented using an array, or a portion of an array, of non-volatile memory cells.

FIG. 9is a block diagram of a system that can be used for that purpose. Vector-by-matrix multiplication (VMM) system32includes non-volatile memory cells and is utilized as the synapses (such as CB1, CB2, CB3, and CB4inFIG. 6) between one layer and the next layer. Specifically, VMM system32includes VMM array33comprising non-volatile memory cells arranged in rows and columns, erase gate and word line gate decoder34, control gate decoder35, bit line decoder36and source line decoder37, which decode the respective inputs for the non-volatile memory cell array33. Input to VMM array33can be from the erase gate and wordline gate decoder34or from the control gate decoder35. Source line decoder37in this example also decodes the output of VMM array33. Alternatively, bit line decoder36can decode the output of VMM array33.

VMM array33serves two purposes. First, it stores the weights that will be used by the VMM system32. Second, VMM array33effectively multiplies the inputs by the weights stored in VMM array33and adds them up per output line (source line or bit line) to produce the output, which will be the input to the next layer or input to the final layer. By performing the multiplication and addition function, VMM array33negates the need for separate multiplication and addition logic circuits and is also power efficient due to its in-situ memory computation.

The output of VMM array33is supplied to a differential summer (such as a summing op-amp or a summing current mirror)38, which sums up the outputs of VMM array33to create a single value for that convolution. The differential summer38is arranged to perform summation of both positive weight and negative weight inputs to output the single value.

The summed up output values of differential summer38are then supplied to an activation function circuit39, which rectifies the output. The activation function circuit39may provide sigmoid, tan h, ReLU functions, or any other non-linear function. The rectified output values of activation function circuit39become an element of a feature map of the next layer (e.g. C1inFIG. 8), and are then applied to the next synapse to produce the next feature map layer or final layer. Therefore, in this example, VMM array33constitutes a plurality of synapses (which receive their inputs from the prior layer of neurons or from an input layer such as an image database), and summer38and activation function circuit39constitute a plurality of neurons.

The input to VMM system32inFIG. 9(WLx, EGx, CGx, and optionally BLx and SLx) can be analog level, binary level, digital pulses (in which case a pulses-to-analog converter PAC may be needed to convert pulses to the appropriate input analog level) or digital bits (in which case a DAC is provided to convert digital bits to appropriate input analog level) and the output can be analog level, binary level, digital pulses, or digital bits (in which case an output ADC is provided to convert output analog level into digital bits).

FIG. 10is a block diagram depicting the usage of numerous layers of VMM systems32, here labeled as VMM systems32a,32b,32c,32d, and32e. As shown inFIG. 10, the input, denoted Inputx, is converted from digital to analog by a digital-to-analog converter31, and provided to input VMM system32a. The converted analog inputs could be voltage or current. The input D/A conversion for the first layer could be done by using a function or a LUT (look up table) that maps the inputs Inputx to appropriate analog levels for the matrix multiplier of input VMM system32a. The input conversion could also be done by an analog to analog (A/A) converter to convert an external analog input to a mapped analog input to the input VMM system32a. The input conversion could also be done by a digital-to-digital pules (D/P) converter to convert an external digital input to a mapped digital pulse or pulses to the input VMM system32a.

The output generated by input VMM system32ais provided as an input to the next VMM system (hidden level1)32b, which in turn generates an output that is provided as an input to the next VMM system (hidden level2)32c, and so on. The various layers of VMM system32function as different layers of synapses and neurons of a convolutional neural network (CNN). Each VMM system32a,32b,32c,32d, and32ecan be a stand-alone, physical non-volatile memory array, or multiple VMM systems could utilize different portions of the same physical non-volatile memory array, or multiple VMM systems could utilize overlapping portions of the same physical non-volatile memory system. Each VMM system32a,32b,32c,32d, and32ecan also be time multiplexed for various portion of its array or neurons. The example shown inFIG. 10contains five layers (32a,32b,32c,32d,32e): one input layer (32a), two hidden layers (32b,32c), and two fully connected layers (32d,32e). One of ordinary skill in the art will appreciate that this is merely exemplary and that a system instead could comprise more than two hidden layers and more than two fully connected layers.

FIG. 11depicts neuron VMM array1100, which is particularly suited for memory cells310as shown inFIG. 3, and is utilized as the synapses and parts of neurons between an input layer and the next layer. VMM array1100comprises memory array1101of non-volatile memory cells and reference array1102(at the top of the array) of non-volatile reference memory cells. Alternatively, another reference array can be placed at the bottom.

In VMM array1100, control gate lines, such as control gate line1103, run in a vertical direction (hence reference array1102in the row direction is orthogonal to control gate line1103), and erase gate lines, such as erase gate line1104, run in a horizontal direction. Here, the inputs to VMM array1100are provided on the control gate lines (CG0, CG1, CG2, CG3), and the output of VMM array1100emerges on the source lines (SL0, SL1). In one embodiment, only even rows are used, and in another embodiment, only odd rows are used. The current placed on each source line (SL0, SL1, respectively) performs a summing function of all the currents from the memory cells connected to that particular source line.

As described herein for neural networks, the non-volatile memory cells of VMM array1100, i.e. the flash memory of VMM array1100, are preferably configured to operate in a sub-threshold region.

The non-volatile reference memory cells and the non-volatile memory cells described herein are biased in weak inversion:
Ids=Io*e(Vg-Vth)/nVt=w*Io*e(Vg)/nVt,
wherew=e(−Vth)/nVt
where Ids is the drain to source current; Vg is gate voltage on the memory cell; Vth is threshold voltage of the memory cell; Vt is thermal voltage=k*T/q with k being the Boltzmann constant, T the temperature in Kelvin, and q the electronic charge; n is a slope factor=1+(Cdep/Cox) with Cdep=capacitance of the depletion layer, and Cox capacitance of the gate oxide layer; Jo is the memory cell current at gate voltage equal to threshold voltage, Jo is proportional to (Wt/L)*u*Cox*(n−1)*Vt2where u is carrier mobility and Wt and L are width and length, respectively, of the memory cell.

For an I-to-V log converter using a memory cell (such as a reference memory cell or a peripheral memory cell) or a transistor to convert input current Ids, into an input voltage, Vg:
Vg=n*Vt*log[Ids/wp*Io]
Here, wp is w of a reference or peripheral memory cell.

For a memory array used as a vector matrix multiplier VMM array, the output current is:
Iout=wa*Io*e(Vg)/nVt, namely
Iout=(wa/wp)*Iin=W*Iin
W=e(Vthp-Vtha)/nVt
Iin=wp*Io*e(Vg)/nVt
Here, wa=w of each memory cell in the memory array.

A wordline or control gate can be used as the input for the memory cell for the input voltage.

Alternatively, the non-volatile memory cells of VMM arrays described herein can be configured to operate in the linear region:
Ids=beta*(Vgs−Vth)*Vds; beta=u*Cox*Wt/L,
Wα(Vgs−Vth),
meaning weight W in linear region is proportional to (Vgs−Vth)

A wordline or control gate or bitline or sourceline can be used as the input for the memory cell operated in the linear region. The bitline or sourceline can be used as the output for the memory cell.

For an I-to-V linear converter, a memory cell (such as a reference memory cell or a peripheral memory cell) or a transistor operating in the linear region or a resistor can be used to linearly convert an input/output current into an input/output voltage.

Alternatively, the flash memory cells of VMM arrays described herein can be configured to operate in the saturation region:
Ids=½*beta*(Vgs−Vth)2; beta=u*Cox*Wt/L
Wα(Vgs−Vth)2, meaning weightWis proportional to (Vgs−Vth)2

A wordline, control gate, or erase gate can be used as the input for the memory cell operated in the saturation region. The bitline or sourceline can be used as the output for the output neuron.

Alternatively, the memory cells of VMM arrays described herein can be used in all regions or a combination thereof (sub threshold, linear, or saturation).

Other embodiments for VMM array32ofFIG. 9are described in U.S. patent application Ser. No. 15/826,345, which is incorporated by reference herein. As described in that application, a sourceline or a bitline can be used as the neuron output (current summation output).

FIG. 12depicts neuron VMM array1200, which is particularly suited for memory cells210as shown inFIG. 2, and is utilized as the synapses between an input layer and the next layer. VMM array1200comprises a memory array1203of non-volatile memory cells, reference array1201of first non-volatile reference memory cells, and reference array1202of second non-volatile reference memory cells. Reference arrays1201and1202, arranged in the column direction of the array, serve to convert current inputs flowing into terminals BLR0, BLR1, BLR2, and BLR3into voltage inputs WL0, WL1, WL2, and WL3. In effect, the first and second non-volatile reference memory cells are diode-connected through multiplexors1214(only partially depicted) with current inputs flowing into them. The reference cells are tuned (e.g., programmed) to target reference levels. The target reference levels are provided by a reference mini-array matrix (not shown).

Memory array1203serves two purposes. First, it stores the weights that will be used by the VMM array1200on respective memory cells thereof. Second, memory array1203effectively multiplies the inputs (i.e. current inputs provided in terminals BLR0, BLR1, BLR2, and BLR3, which reference arrays1201and1202convert into the input voltages to supply to wordlines WL0, WL1, WL2, and WL3) by the weights stored in the memory array1203and then adds all the results (memory cell currents) to produce the output on the respective bit lines (BL0-BLN), which will be the input to the next layer or input to the final layer. By performing the multiplication and addition function, memory array1203negates the need for separate multiplication and addition logic circuits and is also power efficient. Here, the voltage inputs are provided on the word lines WL0, WL1, WL2, and WL3, and the output emerges on the respective bit lines BL0-BLN during a read (inference) operation. The current placed on each of the bit lines BL0-BLN performs a summing function of the currents from all non-volatile memory cells connected to that particular bitline.

Table No. 5 depicts operating voltages for VMM array1200. The columns in the table indicate the voltages placed on word lines for selected cells, word lines for unselected cells, bit lines for selected cells, bit lines for unselected cells, source lines for selected cells, and source lines for unselected cells, where FLT indicates floating, i.e. no voltage is imposed. The rows indicate the operations of read, erase, and program.

FIG. 13depicts neuron VMM array1300, which is particularly suited for memory cells210as shown inFIG. 2, and is utilized as the synapses and parts of neurons between an input layer and the next layer. VMM array1300comprises a memory array1303of non-volatile memory cells, reference array1301of first non-volatile reference memory cells, and reference array1302of second non-volatile reference memory cells. Reference arrays1301and1302run in row direction of the VMM array1300. VMM array is similar to VMM1000except that in VMM array1300, the word lines run in the vertical direction. Here, the inputs are provided on the word lines (WLA0, WLB0, WLA1, WLB2, WLA2, WLB2, WLA3, WLB3), and the output emerges on the source line (SL0, SL1) during a read operation. The current placed on each source line performs a summing function of all the currents from the memory cells connected to that particular source line.

Table No. 6 depicts operating voltages for VMM array1300. The columns in the table indicate the voltages placed on word lines for selected cells, word lines for unselected cells, bit lines for selected cells, bit lines for unselected cells, source lines for selected cells, and source lines for unselected cells. The rows indicate the operations of read, erase, and program.

FIG. 14depicts neuron VMM array1400, which is particularly suited for memory cells310as shown inFIG. 3, and is utilized as the synapses and parts of neurons between an input layer and the next layer. VMM array1400comprises a memory array1403of non-volatile memory cells, reference array1401of first non-volatile reference memory cells, and reference array1402of second non-volatile reference memory cells. Reference arrays1401and1402serve to convert current inputs flowing into terminals BLR0, BLR1, BLR2, and BLR3into voltage inputs CG0, CG1, CG2, and CG3. In effect, the first and second non-volatile reference memory cells are diode-connected through multiplexors1412(only partially shown) with current inputs flowing into them through BLR0, BLR1, BLR2, and BLR3. Multiplexors1412each include a respective multiplexor1405and a cascoding transistor1404to ensure a constant voltage on the bitline (such as BLR0) of each of the first and second non-volatile reference memory cells during a read operation. The reference cells are tuned to target reference levels.

Memory array1403serves two purposes. First, it stores the weights that will be used by the VMM array1400. Second, memory array1403effectively multiplies the inputs (current inputs provided to terminals BLR0, BLR1, BLR2, and BLR3, for which reference arrays1401and1402convert these current inputs into the input voltages to supply to the control gates (CG0, CG1, CG2, and CG3) by the weights stored in the memory array and then add all the results (cell currents) to produce the output, which appears on BL0-BLN, and will be the input to the next layer or input to the final layer. By performing the multiplication and addition function, the memory array negates the need for separate multiplication and addition logic circuits and is also power efficient. Here, the inputs are provided on the control gate lines (CG0, CG1, CG2, and CG3), and the output emerges on the bitlines (BL0-BLN) during a read operation. The current placed on each bitline performs a summing function of all the currents from the memory cells connected to that particular bitline.

VMM array1400implements uni-directional tuning for non-volatile memory cells in memory array1403. That is, each non-volatile memory cell is erased and then partially programmed until the desired charge on the floating gate is reached. This can be performed, for example, using the precision programming techniques described below. If too much charge is placed on the floating gate (such that the wrong value is stored in the cell), the cell must be erased and the sequence of partial programming operations must start over. As shown, two rows sharing the same erase gate (such as EG0or EG1) need to be erased together (which is known as a page erase), and thereafter, each cell is partially programmed until the desired charge on the floating gate is reached.

Table No. 7 depicts operating voltages for VMM array1400. The columns in the table indicate the voltages placed on word lines for selected cells, word lines for unselected cells, bit lines for selected cells, bit lines for unselected cells, control gates for selected cells, control gates for unselected cells in the same sector as the selected cells, control gates for unselected cells in a different sector than the selected cells, erase gates for selected cells, erase gates for unselected cells, source lines for selected cells, and source lines for unselected cells. The rows indicate the operations of read, erase, and program.

FIG. 15depicts neuron VMM array1500, which is particularly suited for memory cells310as shown inFIG. 3, and is utilized as the synapses and parts of neurons between an input layer and the next layer. VMM array1500comprises a memory array1503of non-volatile memory cells, reference array1501or first non-volatile reference memory cells, and reference array1502of second non-volatile reference memory cells. EG lines EGR0, EG0, EG1and EGR1are run vertically while CG lines CG0, CG1, CG2and CG3and SL lines WL0, WL1, WL2and WL3are run horizontally. VMM array1500is similar to VMM array1400, except that VMM array1500implements bi-directional tuning, where each individual cell can be completely erased, partially programmed, and partially erased as needed to reach the desired amount of charge on the floating gate due to the use of separate EG lines. As shown, reference arrays1501and1502convert input current in the terminal BLR0, BLR1, BLR2, and BLR3into control gate voltages CG0, CG1, CG2, and CG3(through the action of diode-connected reference cells through multiplexors1514) to be applied to the memory cells in the row direction. The current output (neuron) is in the bitlines BL0-BLN, where each bit line sums all currents from the non-volatile memory cells connected to that particular bitline.

Table No. 8 depicts operating voltages for VMM array1500. The columns in the table indicate the voltages placed on word lines for selected cells, word lines for unselected cells, bit lines for selected cells, bit lines for unselected cells, control gates for selected cells, control gates for unselected cells in the same sector as the selected cells, control gates for unselected cells in a different sector than the selected cells, erase gates for selected cells, erase gates for unselected cells, source lines for selected cells, and source lines for unselected cells. The rows indicate the operations of read, erase, and program.

FIG. 24depicts neuron VMM array2400, which is particularly suited for memory cells210as shown inFIG. 2, and is utilized as the synapses and parts of neurons between an input layer and the next layer. In VMM array2400, the inputs INPUT0. . . , INPUTNare received on bit lines BL0, . . . BLN, respectively, and the outputs OUTPUT1, OUTPUT2, OUTPUT3, and OUTPUT4are generated on source lines SL0, SL1, SL2, and SL3, respectively.

FIG. 25depicts neuron VMM array2500, which is particularly suited for memory cells210as shown inFIG. 2, and is utilized as the synapses and parts of neurons between an input layer and the next layer. In this example, the inputs INPUT0, INPUT1, INPUT2, and INPUT3are received on source lines SL0, SL1, SL2, and SL3, respectively, and the outputs OUTPUT0, . . . OUTPUTNare generated on bit lines BL0, . . . , BLN.

FIG. 26depicts neuron VMM array2600, which is particularly suited for memory cells210as shown inFIG. 2, and is utilized as the synapses and parts of neurons between an input layer and the next layer. In this example, the inputs INPUT0, . . . , INPUTMare received on word lines WL0, . . . , WLM, respectively, and the outputs OUTPUT0, . . . OUTPUTNare generated on bit lines BL0, . . . , BLN.

FIG. 27depicts neuron VMM array2700, which is particularly suited for memory cells310as shown inFIG. 3, and is utilized as the synapses and parts of neurons between an input layer and the next layer. In this example, the inputs INPUT0, . . . , INPUTMare received on word lines WL0, . . . , WLM, respectively, and the outputs OUTPUT0, . . . OUTPUTNare generated on bit lines BL0, . . . , BLN.

FIG. 28depicts neuron VMM array2800, which is particularly suited for memory cells410as shown inFIG. 4, and is utilized as the synapses and parts of neurons between an input layer and the next layer. In this example, the inputs INPUT0, . . . , INPUTnare received on vertical control gate lines CG0, . . . , CGN, respectively, and the outputs OUTPUT1and OUTPUT2are generated on source lines SL0and SL1.

FIG. 29depicts neuron VMM array2900, which is particularly suited for memory cells410as shown inFIG. 4, and is utilized as the synapses and parts of neurons between an input layer and the next layer. In this example, the inputs INPUT0, . . . , INPUTNare received on the gates of bit line control gates2901-1,2901-2, . . . ,2901-(N−1), and2901-N, respectively, which are coupled to bit lines BL0, . . . , BLN, respectively. Exemplary outputs OUTPUT1and OUTPUT2are generated on source lines SL0and SL1.

FIG. 30depicts neuron VMM array3000, which is particularly suited for memory cells310as shown inFIG. 3, memory cells510as shown inFIG. 5, and memory cells710as shown inFIG. 7, and is utilized as the synapses and parts of neurons between an input layer and the next layer. In this example, the inputs INPUT0, . . . , INPUTMare received on word lines WL0, . . . , WLM, and the outputs OUTPUT0, . . . , OUTPUTNare generated on bit lines BL0, . . . , BLN, respectively.

FIG. 31depicts neuron VMM array3100, which is particularly suited for memory cells310as shown inFIG. 3, memory cells510as shown inFIG. 5, and memory cells710as shown inFIG. 7, and is utilized as the synapses and parts of neurons between an input layer and the next layer. In this example, the inputs INPUT0, . . . , INPUTMare received on control gate lines CG0, . . . , CGM. Outputs OUTPUT0, . . . , OUTPUTNare generated on vertical source lines SL0, . . . , SLN, respectively, where each source line SLiis coupled to the source lines of all memory cells in column i.

FIG. 32depicts neuron VMM array3200, which is particularly suited for memory cells310as shown inFIG. 3, memory cells510as shown inFIG. 5, and memory cells710as shown inFIG. 7, and is utilized as the synapses and parts of neurons between an input layer and the next layer. In this example, the inputs INPUT0, . . . , INPUTMare received on control gate lines CG0, . . . , CGM. Outputs OUTPUT0, . . . , OUTPUTNare generated on vertical bit lines BL0, . . . , BLN, respectively, where each bit line BLiis coupled to the bit lines of all memory cells in column i.

Long Short-Term Memory

The prior art includes a concept known as long short-term memory (LSTM). LSTM units often are used in neural networks. LSTM allows a neural network to remember information over predetermined arbitrary time intervals and to use that information in subsequent operations. A conventional LSTM unit comprises a cell, an input gate, an output gate, and a forget gate. The three gates regulate the flow of information into and out of the cell and the time interval that the information is remembered in the LSTM. VMMs are particularly useful in LSTM units.

FIG. 16depicts an exemplary LSTM1600. LSTM1600in this example comprises cells1601,1602,1603, and1604. Cell1601receives input vector x0and generates output vector h0and cell state vector c0. Cell1602receives input vector x1, the output vector (hidden state) h0from cell1601and cell state c0from cell1601and generates output vector h1and cell state vector c1. Cell1603receives input vector x2, the output vector (hidden state) h1from cell1602, and cell state c1from cell1602and generates output vector h2and cell state vector c2. Cell1604receives input vector x3, the output vector (hidden state) h2from cell1603, and cell state c2from cell1603and generates output vector h3. Additional cells can be used, and an LSTM with four cells is merely an example.

FIG. 17depicts an exemplary implementation of an LSTM cell1700, which can be used for cells1601,1602,1603, and1604inFIG. 16. LSTM cell1700receives input vector x(t), cell state vector c(t−1) from a preceding cell, and output vector h(t−1) from a preceding cell, and generates cell state vector c(t) and output vector h(t).

LSTM cell1700comprises sigmoid function devices1701,1702, and1703, each of which applies a number between 0 and 1 to control how much of each component in the input vector is allowed through to the output vector. LSTM cell1700also comprises tan h devices1704and1705to apply a hyperbolic tangent function to an input vector, multiplier devices1706,1707, and1708to multiply two vectors together, and addition device1709to add two vectors together. Output vector h(t) can be provided to the next LSTM cell in the system, or it can be accessed for other purposes.

FIG. 18depicts an LSTM cell1800, which is an example of an implementation of LSTM cell1700. For the reader's convenience, the same numbering from LSTM cell1700is used in LSTM cell1800. Sigmoid function devices1701,1702, and1703and tan h device1704each comprise multiple VMM arrays1801and activation circuit blocks1802. Thus, it can be seen that VMM arrays are particular useful in LSTM cells used in certain neural network systems. The multiplier devices1706,1707, and1708and the addition device1709are implemented in a digital manner or in an analog manner. The activation function blocks1802can be implemented in a digital manner or in an analog manner.

An alternative to LSTM cell1800(and another example of an implementation of LSTM cell1700) is shown inFIG. 19. InFIG. 19, sigmoid function devices1701,1702, and1703and tan h device1704share the same physical hardware (VMM arrays1901and activation function block1902) in a time-multiplexed fashion. LSTM cell1900also comprises multiplier device1903to multiply two vectors together, addition device1908to add two vectors together, tan h device1705(which comprises activation circuit block1902), register1907to store the value i(t) when i(t) is output from sigmoid function block1902, register1904to store the value f(t)*c(t−1) when that value is output from multiplier device1903through multiplexor1910, register1905to store the value i(t)*u(t) when that value is output from multiplier device1903through multiplexor1910, and register1906to store the value o(t)*c˜(t) when that value is output from multiplier device1903through multiplexor1910, and multiplexor1909.

Whereas LSTM cell1800contains multiple sets of VMM arrays1801and respective activation function blocks1802, LSTM cell1900contains only one set of VMM arrays1901and activation function block1902, which are used to represent multiple layers in the embodiment of LSTM cell1900. LSTM cell1900will require less space than LSTM1800, as LSTM cell1900will require ¼ as much space for VMMs and activation function blocks compared to LSTM cell1800.

It can be further appreciated that LSTM units will typically comprise multiple VMM arrays, each of which requires functionality provided by certain circuit blocks outside of the VMM arrays, such as a summer and activation circuit block and high voltage generation blocks. Providing separate circuit blocks for each VMM array would require a significant amount of space within the semiconductor device and would be somewhat inefficient.

Gated Recurrent Units

An analog VMM implementation can be utilized for a GRU (gated recurrent unit) system. GRUs are a gating mechanism in recurrent neural networks. GRUs are similar to LSTMs, except that GRU cells generally contain fewer components than an LSTM cell.

FIG. 20depicts an exemplary GRU2000. GRU2000in this example comprises cells2001,2002,2003, and2004. Cell2001receives input vector x0and generates output vector h0. Cell2002receives input vector x1the output vector h0from cell2001and generates output vector h1. Cell2003receives input vector x2and the output vector (hidden state) h1from cell2002and generates output vector h2. Cell2004receives input vector x3and the output vector (hidden state) h2from cell2003and generates output vector h3. Additional cells can be used, and an GRU with four cells is merely an example.

FIG. 21depicts an exemplary implementation of a GRU cell2100, which can be used for cells2001,2002,2003, and2004ofFIG. 20. GRU cell2100receives input vector x(t) and output vector h(t−1) from a preceding GRU cell and generates output vector h(t GRU cell2100comprises sigmoid function devices2101and2102, each of which applies a number between 0 and 1 to components from output vector h(t−1) and input vector x(t). GRU cell2100also comprises a tan h device2103to apply a hyperbolic tangent function to an input vector, a plurality of multiplier devices2104,2105, and2106to multiply two vectors together, an addition device2107to add two vectors together, and a complementary device2108to subtract an input from 1 to generate an output.

FIG. 22depicts a GRU cell2200, which is an example of an implementation of GRU cell2100. For the reader's convenience, the same numbering from GRU cell2100is used in GRU cell2200. As can be seen inFIG. 22, sigmoid function devices2101and2102, and tan h device2103each comprise multiple VMM arrays2201and activation function blocks2202. Thus, it can be seen that VMM arrays are of particular use in GRU cells used in certain neural network systems. The multiplier devices2104,2105,2106, the addition device2107, and the complementary device2108are implemented in a digital manner or in an analog manner. The activation function blocks2202can be implemented in a digital manner or in an analog manner.

An alternative to GRU cell2200(and another example of an implementation of GRU cell2300) is shown inFIG. 23. InFIG. 23, GRU cell2300utilizes VMM arrays2301and activation function block2302, which when configured as a sigmoid function applies a number between 0 and 1 to control how much of each component in the input vector is allowed through to the output vector. InFIG. 23, sigmoid function devices2101and2102and tan h device2103share the same physical hardware (VMM arrays2301and activation function block2302) in a time-multiplexed fashion. GRU cell2300also comprises multiplier device2303to multiply two vectors together, addition device2305to add two vectors together, complementary device2309to subtract an input from 1 to generate an output, multiplexor2304, register2306to hold the value h(t−1)*r(t) when that value is output from multiplier device2303through multiplexor2304, register2307to hold the value h(t−1)*z(t) when that value is output from multiplier device2303through multiplexor2304, and register2308to hold the value h{circumflex over ( )}(t)*(1−z(t)) when that value is output from multiplier device2303through multiplexor2304.

Whereas GRU cell2200contains multiple sets of VMM arrays2201and activation function blocks2202, GRU cell2300contains only one set of VMM arrays2301and activation function block2302, which are used to represent multiple layers in the embodiment of GRU cell2300. GRU cell2300will require less space than RU cell2200, as GRU cell2300will require ⅓ as much space for VMMs and activation function blocks compared to GRU cell2200.

It can be further appreciated that GRU systems will typically comprise multiple VMM arrays, each of which requires functionality provided by certain circuit blocks outside of the VMM arrays, such as a summer and activation circuit block and high voltage generation blocks. Providing separate circuit blocks for each VMM array would require a significant amount of space within the semiconductor device and would be somewhat inefficient.

The input to the VMM arrays can be an analog level, a binary level, or digital bits (in this case a DAC is needed to convert digital bits to appropriate input analog level) and the output can be an analog level, a binary level, or digital bits (in this case an output ADC is needed to convert output analog level into digital bits).

For each memory cell in a VMM array, each weight W can be implemented by a single memory cell or by a differential cell or by two blend memory cells (average of 2 cells). In the differential cell case, two memory cells are needed to implement a weight W as a differential weight (W=W+−W−). In the two blend memory cells, two memory cells are needed to implement a weight W as an average of two cells.

Decoding Systems and Physical Layout Embodiments for VMM Arrays

FIGS. 33-51disclose various decoding systems and physical layouts for VMM arrays that can be used with any of the memory cell types described previously with respect toFIGS. 2-7, or with other non-volatile memory cells.

FIG. 33depicts VMM system3300. VMM system3300comprises VMM array3301(which can be based on any of the VMM array designs discussed previously, such as VMM array1000,1100,1200,1300,1400,1500,2400,2500,2600,2700,2800,2900,3000,3100, and3200or other VMM designs), low voltage row decoder3302, high voltage row decoder3303, column decoder3304, column driver3305, control logic3306, bias circuit3307, neuron output circuit block3308, input VMM circuit block3309, algorithm controller3310, high voltage generator block3311, analog circuit block3315, and control logic3316.

Input circuit block3309serves as interface from an external input to the input terminals of the memory array3301. Input circuit block3309can comprise a DAC (Digital-to-Analog Converter), DPC (Digital-to-Pulse Converter), APC (Analog-to-Pulse Converter), IVC (Current-to-Voltage Converter), AAC (Analog-to-Analog Converter such as voltage to voltage scaler), or FAC (Frequency-to-Analog Converter), without limitation. Neuron output block3308serves as an interface from the memory array output to an external interface (not shown). Neuron output block3308can comprise an ADC (Analog-to-Digital Converter), APC (Analog-to-Pulse Converter), DPC (Digital-to-Pulse Converter), IVC (Current-to-Voltage Converter), or IFC (Current-to-Frequency Converter), without limitation. Neuron output block3308may include activation functions, normalization circuitry, and/or re-scaling circuitry, without limitation.

Low voltage row decoder3302provides a bias voltage for read and program operations and provides a decoding signal for high voltage row decoder3303. High voltage row decoder3303provides a high voltage bias signal for program and erase operations.

Algorithm controller3310provides a controlling function for bit lines during program, verify, and erase operations.

High voltage generator block3311comprises charge pump3312, charge pump regulator3313, and high voltage generation circuitry3314that provides the multiple voltages needed for the various program, erase, program verify, and read operations.

FIG. 34depicts VMM system3400, which is particularly suited for use with memory cells of the type depicted inFIG. 4as memory cell410. VMM system3400comprises VMM arrays3401,3402,3402, and3404(each which can be based on any of the VMM array designs discussed previously, such as VMM array1000,1100,1200,1300,1400,1500,2400,2500,2600,2700,2800,2900,3000and31000, or other VMM array designs); low voltage row decoders3405,3406,3407, and3408; shared high voltage row decoder3409; word lines or word input lines3411,3412,3413, and3414; bit lines3421,3422,3423, and3424; control gate lines3432, source lines3434, and erase gate lines3434. The shared high voltage row decoder3409provides the control gate line3432, source lines3434, and erase gate lines3434. In this arrangement, word lines3411,3412,3413, and3414and bit lines3421,3422,3423, and3424are parallel to one another. In one embodiment the wordlines and bitlines are arranged in the vertical direction. Control gate lines3432, source line lines3434, and erase gate lines3436are parallel to one another and are arranged in the horizontal direction, and therefore are perpendicular to word lines or word input lines3411,3412,3413, and3414and bit lines3421,3422,3423, and3424.

In VMM system3400, VMM arrays3401,3402,3403, and3404share control gate lines3432, source line lines3434, erase gate lines3436, and high voltage row decoder3409. However, each of the arrays has its own low voltage row decoder, such that low voltage row decoder3405is used with VMM array3401; low voltage row decoder3406is used with VMM array3402; low voltage row decoder3407is used with VMM array3403; and low voltage row decoder3408is used with VMM array3404. Advantageous to this arrangement is the fact that word lines3411,3412,3413, and3414are arranged in the vertical direction, such that word lines3411can be routed solely to VMM array3401, word lines3412can be routed solely to VMM array3402, word lines3413can be routed solely to VMM array3403, and word lines3414can be routed solely to VMM array3404. This would be very inefficient using a conventional layout where word lines are arranged in the horizontal direction for multiple VMM arrays sharing the same high voltage decoder and same high voltage decoding lines

FIG. 35depicts VMM system3500, which is particularly suited for use with memory cells of the type depicted inFIG. 4as memory cell410. VMM system3500is similar to VMM system3300ofFIG. 33except that VMM system3500contains separate word lines and low voltage row decoders for read operations and programming operations.

VMM system3500comprises VMM arrays3501,3502,3503, and3504(each which can be based on any of the VMM design discussed previously, such as VMM array1000,1100,1200,1300,1400,1500,2400,2500,2600,2700,2800,2900,3000,3100, and3200or other VMM array designs); low voltage read row decoders3505,3506,3507, and3508; shared low voltage program row decoder3530; shared high voltage row decoder3509; read word lines or word input lines3511,3512,3513, and3514; program pre-decoding row line3515; bit lines3521,3522,3523, and3524; control gate lines3532, source lines3533, and erase gate lines3535. The shared high voltage row decoder3509provides the control gate lines3532, source line3533, and erase gate lines3535. In this layout, read word lines or word input lines3511,3512,3513, and3514, program pre-decoding row line3515, and bit lines3521,3522,3523, and3524are parallel to one another and are arranged in the vertical direction. Control gate lines3532, source lines3533, and erase gate lines3535are parallel to one another and are arranged in the horizontal direction, and therefore are perpendicular to read word lines or word input lines3511,3512,3513, and3514, program pre-decoding row line3515, and bit lines3521,3522,3523, and3524. In this VMM system3500, the low voltage program row decoder3530is shared across multiple VMM arrays.

In VMM system3500, VMM arrays3501,3502,3503, and3504share control gate lines3532, source lines3533, erase gate lines3535, and high voltage row decoder3509. However, each of the VMM arrays has its own low voltage read row decoder, such that low voltage read row decoder3505is used with VMM array3501; low voltage read row decoder3506is used with VMM array3502; low voltage read row decoder3507is used with VMM array3503; and low voltage read row decoder3508is used with VMM array3504. Advantageous to this layout is the fact that read word lines or word input lines3511,3512,3513, and3514are arranged in the vertical direction, such that word lines3511can be routed solely to VMM array3501, word lines3512can be routed solely to VMM array3502, word lines3513can be routed solely to VMM array3503, and word lines3514can be routed solely to VMM array3504. This would be very inefficient using a conventional layout where word lines are arranged in the horizontal direction for multiple arrays sharing the same high voltage decoder and same high voltage decoding lines. Notably, program pre-decoding row line3515can be connected to any of VMM arrays3501,3502,3503, and3504through low voltage program row decoder3530such that cells in one or more of those VMM arrays can be programmed at a time.

FIG. 36depicts additional detail regarding certain aspects of VMM system3500, particularly, detail regarding the low voltage row decoders3505,3506,3507and3508, exemplified as low voltage row decoder3600. Low voltage read row decoder3600comprises a plurality of switches, such as the exemplary switches shown, to selectively couple word lines with rows of cells in VMM arrays3601,3602,3603, and3604, respectively. Low voltage program decoder3630comprises exemplary NAND gates3631and3632, PMOS transistors3633and3635and NMOS transistors3636and3636, configured as shown. NAND gates3631and3632receive program pre-decoding row lines XPs3615as inputs. During program operation, switches Sp (which can be CMOS multiplexors or another type of switch) in the low voltage read row decoders3605,3605,3606, and3608are closed, and thus the program wordline Wlp0-nare coupled to the word-lines in the array to apply voltages for programming. During a read operation, read word lines or word input lines3611,3612,3613, and3614are selectively coupled to apply voltages to word line terminals of rows within one or more of arrays3601,3602,3603, and3604using the Sr switches (being closed) (which can be CMOS multiplexors or another type of switch) within low voltage read row decoders3605,3606,3607, and3608.

FIG. 37depicts VMM system3700, which is particularly suited for use with memory cells of the type depicted inFIG. 4as memory cell410. VMM system3700comprises VMM arrays3701,3702,3702, and3704(each which can be based on any of the VMM design discussed previously, such as VMM array1000,1100,1200,1300,1400,1500,2400,2500,2600,2700,2800,2900,3000and3100, or other VMM array designs); low voltage row decoders3705,3706,3707, and3708; local high voltage row decoders3709and3710; global high voltage row decoder3730; word lines3711,3712,3713, and3714; bit lines3721,3722,3723, and3724; high voltage and/or low voltage (HV/LV) pre-decoding lines3732, source lines3733, and erase gate lines3734. The shared global high voltage row decoder3730provides the HV/LV pre-decoding lines3732, source line lines3733, and erase gate lines3734. In this layout, word-lines3711,3712,3713, and3714and bit lines3721,3722,3723, and3724are parallel to one another and are arranged in the vertical direction. HV/LV pre-decoding lines3732, source line lines3733, and erase gate lines3734are parallel to one another and are arranged in the horizontal direction, and therefore are perpendicular to word lines3711,3712,3713, and3714and bit lines3721,3722,3723, and3724. The HV/LV pre-decoding lines3732are input to the local high voltage decoders3709and3710. The local high voltage decoders3709outputs the local control gate lines for the VMM array3701and3702. The local high voltage decoders3710outputs the local control gate lines for the VMM array3703and3704. In another embodiment, the local high voltage decoders3709and3710can provide the local source lines for the VMM array3701/3702and VMM array3703/3704respectively. In another embodiment, the local high voltage decoders3709and3710can provide the local erase gate lines for the VMM array3701/3702and VMM array3703/3704respectively.

Here, local high voltage row decoder3709is shared by VMM arrays3701and3702and local high voltage row decoder3710is shared by VMM arrays3703and3704. Global high voltage decoder3730routes high voltage and low voltage pre-decoding signals to a local high voltage row decoder, such as local high voltage row decoders3709and3710. Thus, the high voltage decoding function is split between global high voltage row decoder3730and the local high voltage decoders such as local high voltage decoders3709and3710.

In VMM system3700, VMM arrays3701,3702,3703, and3704share HV/LV pre-decoding lines3732, source lines3733, erase gate lines3734, and global high voltage row decoder3730. However, each of the VMM arrays has its own low voltage row decoder, such that low voltage row decoder3705is used with VMM array3701; low voltage row decoder3706is used with VMM array3702; low voltage row decoder3707is used with VMM array3703; and low voltage row decoder3708is used with VMM array3704. Advantageous to this layout is the fact that word lines3711,3712,3713, and3714are arranged in the vertical direction, such that word lines3711can be routed solely to VMM array3701, word lines3712can be routed solely to VMM array3702, word lines3713can be routed solely to VMM array3703, and word lines3714can be routed solely to VMM array3704. This would be very inefficient using a conventional layout where word lines are arranged in the horizontal direction for multiple arrays sharing a single high voltage decoder.

FIG. 38depicts VMM system3800, which is particularly suited for use with memory cells of the type depicted inFIG. 4as memory cell410. VMM system3800comprises VMM arrays3801,3802,3802, and3804(each which can be based on any of the VMM design discussed previously, such as VMM array1000,1100,1200,1300,1400,1500,2400,2500,2600,2700,2800,2900,3000,3100, and3200or other VMM array designs); low voltage row decoders3805,3806,3807, and3808; local high voltage row decoders3809and3810; global high voltage row decoder3830; bit lines3821,3822,3823, and3824; control gate lines or control gate input lines3811and3812, HV/LV pre-decoding lines3833, source lines3834, and erase gate lines3835. The shared global high voltage row decoder3830provides the HV/LV pre-decoding line3833, source line lines3834, and erase gate lines3835. The local high voltage decoders3809and3810couples the control gate input CGs3811and3812to local control gates of the VMM arrays3801,3802and3803,3804respectively. The low voltage row decoders3805,3806,3807and3808provide local (horizontal) word-lines to the arrays3801,3802,3803,3804respectively. In this layout, control gate lines3811and3812and bit lines3821,3822,3823, and3824are parallel to one another and are arranged in the vertical direction. Source lines3834and erase gate lines3835are parallel to one another and are arranged in the horizontal direction, and therefore are perpendicular to control gate lines3811and3812and bit lines3821,3822,3823, and3824.

As in VMM system3700ofFIG. 37, local high voltage row decoder3809is shared by VMM arrays3801and3802and local high voltage row decoder3810is shared by VMM arrays3803and3804. Global high voltage decoder3830routes signals to a local high voltage row decoder, such as local high voltage row decoders3809and3810. Thus, the high voltage decoding function is split between global high voltage row decoder3830and the local high voltage decoders such as local high voltage decoders3809and3810(that can provide local source line lines and/or local erase gate lines).

In VMM system3800, VMM arrays3801,3802,3803, and3804share HV/LV pre-decoding lines3833, source line lines3834, erase gate lines3835, and global high voltage row decoder3830. However, each of the VMM arrays has its own low voltage row decoder, such that low voltage row decoder3805is used with VMM array3801; low voltage row decoder3806is used with VMM array3802; low voltage row decoder3807is used with VMM array3803; and low voltage row decoder3808is used with VMM array3804. Advantageous to this layout is the fact that control gate lines3811and3812, which may be read lines or input lines, are arranged in the vertical direction, such that control gate lines3811can be routed solely to VMM arrays3801and3802and control gate lines3812can be routed solely to VMM arrays3803and3804. This would not be possible using a conventional layout where word lines are arranged in the horizontal direction.

FIG. 39depicts VMM system3900, which is particularly suited for use with memory cells of the type depicted inFIG. 3as memory cell310,FIG. 4as memory cell410,FIG. 5as memory cell510, orFIG. 7as memory cell710. VMM system3900comprises VMM arrays3901and3902(each which can be based on any of the VMM design discussed previously, such as VMM array1000,1100,1200,1300,1400,1500,2400,2500,2600,2700,2800,2900,3000,3100, and3200or other VMM array designs); low voltage row decoders3903(used with arrays3901and3902); local high voltage row decoder3905, global high voltage row decoder3904; control gate lines3908and3909; and bit lines3906and3907. In this layout, control gate lines3908are used solely by VMM array3901, and control gate lines3909are used solely by VMM array3902. Low voltage row decoding line3910is used as decoding input to the global high voltage row decoder3904. Global high voltage row decoding line3911is used as decoding input to the local high voltage decoder3905.

Local high voltage row decoder3905is shared by VMM arrays3901and3902. Global high voltage decoder3904routes signals to a local high voltage row decoder of multiple VMM systems, such as local high voltage row decoder3905of VMM system3900. Thus, the high voltage decoding function is split between global high voltage row decoder3904and the local high voltage decoders such as local high voltage decoder3905as described above.

In VMM system3900, VMM arrays3901and3902share word lines (not shown), source gate lines if present (not shown), erase gate lines if present (not shown), and global high voltage row decoder3904. Here, VMM arrays3901and3902share low voltage row decoder3903. Advantageous to this layout is the fact that VMM arrays3901and3902do not share control gate lines, which enable each array to be independently accessed using control gate lines3908and3909, respectively.

FIG. 51depicts VMM system5100, which is particularly suited for use with memory cells of the type depicted inFIG. 4as memory cell410. VMM system5100comprises VMM arrays5101,5102,5103, and5104(each which can be based on any of the VMM array designs discussed previously, such as VMM array1000,1100,1200,1300,1400,1510,2400,2510,2600,2700,2800,2900,3000,3100, and3200or other VMM array designs); high voltage decoder5130; routing blocks5151and5152; input word lines5111and5112, bit lines5121,5122,5123, and5124; control gate lines5132, source lines5133, and erase gate lines5134. The high voltage decoder5130provides control gate lines5132, source lines5133, and erase gate lines5134. The routing blocks5151,5152is where the input wordlines5111and5112, respectively, which are received vertically, are routed to horizontal-running wordlines of VMM arrays5101-5104. Alternatively, the routing blocks5151,5152may route the control gate input lines5132which are received vertically to horizontal-running control gate lines5132of the VMM arrays.

FIG. 40depicts low voltage row decoder4000, which comprises NAND gate4001, PMOS transistor4002, and NMOS transistor4003. NAND gate4001receives row address signals4004. PMOS transistor4002is coupled to vertical wordline inputs4005. The output is on horizontal word lines4006, which is one of many word lines, which couple to respective VMM arrays. In this example, there are 16 word lines total, and there will therefore be 16 instantiations of row decoder4000, each outputting one of the 16 word lines. Thus, based on the received row address signal, one word line, such as word line4006, will output a respective signal, such as a voltage, and the other word lines will be set to ground.

FIG. 41depicts combined co-select/deselect word line and control gate decoder4100, which comprises a low voltage row decoder as inFIG. 40, here comprising NAND gate4101, PMOS transistor4102, NMOS transistor4103, row address signals4104, vertical input wordline lines4105, and horizontal word output line4106which couples to wordlines of VMM arrays. Combined word line and control gate decoder4100further comprises inverter4107, switches4108and4112, and isolation transistor4109, and receives control gate input4110CGIN0and outputs control gate line4111CG0. The wordline output4106WL0and control gate output CG04111are selected or de-selected at the same times by decoding logic (not shown) controlling NAND gate4101.

FIG. 42depicts bit line decoder4200, which operates on VMM arrays4201and4202. Bit line decoder4200comprises column multiplexor4203(for selecting one or more bit lines for program and verify, where a verify operation is used to confirm the cell current reaches a certain target during a tuning operation (program or erase operation), and sense amplifiers4204(for performing a read operation on one or more bit lines). As shown, local bitline mux4201band4202bmuxes local array bitlines to global bitlines4220xto be coupled to the column multiplexor4203. The sense amplifier comprises an ADC or other device. Thus, the bit line decoder4200is shared across multiple arrays.

FIG. 43depicts VMM system4300, which comprises VMM arrays4301,4302,4303, and4304; low voltage row decoders4305and4307; local high voltage row decoders4306and4308, global high voltage row decoder4309, digital bus inputs QIN[7:0]4311and4312(which here are inputs to a VMM array), and bit lines4321,4322,4323, and4324. Each low voltage row decoder, such as low voltage row decoder4305, comprises a circuit block row decoder4335for each word line, such as exemplary data input block4331(which might consist of 8 latches or registers) and block4332(which might comprise data-to-voltage converter circuits or data-to-pulse converter circuits), which outputs signal4333on a word line. Thus, the input to this low voltage row decoder is a digital bus QIN [7:0] with appropriate control logic. For each circuit block row decoder4335, the digital input QIN [7:0]4311and4312are latched appropriately such as by synchronous clocking means and method (such as by a serial to parallel clocking interface).

FIG. 44depicts a neural network array input-output bus multiplexor4400, which receives outputs from a VMM array (such as from an ADC) and provides those outputs in groups in multiplexed fashion to the input blocks of other VMM arrays (such as DAC or DPC). In the example shown, the inputs to input-output bus multiplexor4400comprise 2048 bits (256 sets, NEU0. . . NEU255, of 8 bits each) and input-output bus multiplexor4400provides those bits in 64 different groups of 32 bits per group, where it multiplexes between the different groups, such as by using time-division multiplexing (where it provides 1 group of 32 bits at any given time). Control logic4401generates control signals4402to controls input-output bus multiplexor4400.

FIGS. 45A and 45Bdepict exemplary layouts of VMM arrays where the word lines are laid out in a horizontal manner (FIG. 45A) versus in a vertical manner (FIG. 45B, such as inFIG. 34 or 35).

FIG. 46depicts an exemplary layout of VMM array where the word lines are laid out in a vertical manner (such as inFIG. 34 or 35). However, in this layout, two word lines (such as word lines4601and4602) can occupy the same column, but access different rows in the array (due to the gap between them).

FIG. 47depicts VMM high voltage decode circuits, comprising word line decoder circuit4701, source line decoder circuit4704, and high voltage level shifter4708, which are appropriate for use with memory cells of the type shown inFIG. 2.

Word line decoder circuit4701comprises PMOS select transistor4702(controlled by signal HVO_B) and NMOS de-select transistor4703(controlled by signal HVO_B) configured as shown.

Source line decoder circuit4704comprises NMOS monitor transistors4705(controlled by signal HVO), driving transistor4706(controlled by signal HVO), and de-select transistor4707(controlled by signal HVO_B), configured as shown.

High voltage level shifter4708receives enable signal EN and outputs high voltage signal HV and its complement HVO_B.

FIG. 48depicts VMM high voltage decode circuits, comprising erase gate decoder circuit4801, control gate decoder circuit4804, source line decoder circuit4807, and high voltage level shifter4811, which are appropriate for use with memory cells of the type shown inFIG. 3.

Erase gate decoder circuit4801and control gate decoder circuit4804use the same design as word line decoder circuit4701inFIG. 47.

Source line decoder circuit4807uses the same design as source line decoder circuit4704inFIG. 47.

High voltage level shifter4811uses the same design as high voltage level shifter4708inFIG. 47.

FIG. 49depicts word line driver4900. Word line driver4900selects a word line (such as exemplary word lines WL0, WL1, WL2, and WL3shown here) and provides a bias voltage to that word line. Each word line is attached to a select isolation transistor, such as select transistor4901, that is controlled by control line4902. The select transistors, such as select transistor4901, isolate the high voltage used during an erase operation (e.g., 8-12V) from word line decoding transistors, which can be implemented with IO transistors that operate at a low voltage (e.g., 1.8V, 3.3V). Here, during any operation, control line4902is activated and all select transistors similar to select transistor4901are turned on. Exemplary bias transistor4903(part of a wordline decoding circuit) selectively couples a word line to a first bias voltage (such as 3V) and exemplary bias transistor4904(part of the wordline decoding circuit) selectively couples a word line to a second bias voltage (lower than the first bias voltage, including ground, a bias in between ground and the first bias voltage, or a negative voltage bias to reduce leakage from un-used memory rows). During an ANN (analog neural network) read operation, all used word lines will be selected and tied to the first bias voltage. All un-used wordlines are tied to the second bias voltage. During other operations such as program operation, only one word line will be selected and the other word lines will be tied to the second bias voltage, which can be a negative bias (e.g., −0.3 to −0.5V or more) to reduce array leakage.

Bias transistors4903and4904are coupled to the outputs of stage4906of shift register4905. Shift register4905enables each row to be controlled independently, in accordance with the input data pattern (which is loaded in the beginning of an ANN operation)

FIG. 50depicts word line driver5000. Word line driver5000is similar to word line driver4900, except that each select transistor is further coupled to a capacitor, such as capacitor5001. Capacitor5001can provide a pre-charge or bias to the word line at the beginning of an operation, enabled by transistor5002to sample the voltage on line5003. Capacitor5001acts to sample and hold (S/H) the input voltage for each wordline. Transistors5004and5005are off during the ANN operation (array current summer and activation function) of the VMM array, meaning that the voltage on the S/H capacitor5001will serve as a (floating) voltage source for the respective wordline. Alternatively, capacitor5001can be provided by the word line (or as a control gate capacitance if the input is on a control gate) capacitance from the VMM array.

It should be noted that, as used herein, the terms “over” and “on” both inclusively include “directly on” (no intermediate materials, elements or space disposed therebetween) and “indirectly on” (intermediate materials, elements or space disposed therebetween). Likewise, the term “adjacent” includes “directly adjacent” (no intermediate materials, elements or space disposed therebetween) and “indirectly adjacent” (intermediate materials, elements or space disposed there between), “mounted to” includes “directly mounted to” (no intermediate materials, elements or space disposed there between) and “indirectly mounted to” (intermediate materials, elements or spaced disposed there between), and “electrically coupled” includes “directly electrically coupled to” (no intermediate materials or elements there between that electrically connect the elements together) and “indirectly electrically coupled to” (intermediate materials or elements there between that electrically connect the elements together). For example, forming an element “over a substrate” can include forming the element directly on the substrate with no intermediate materials/elements therebetween, as well as forming the element indirectly on the substrate with one or more intermediate materials/elements there between.