Stack-type semiconductor package

According to example embodiments, a stack-type semiconductor package includes a lower semiconductor package, an upper semiconductor package, connection pads, and a metal layer pattern. The lower semiconductor package includes a lower semiconductor chip on a top surface of a lower package substrate, lower lands on the lower package substrate, and an encapsulant on the top surface of the lower package substrate. The encapsulant defines via holes that expose the lower lands. The upper semiconductor package is on the encapsulant. Upper solder balls are connected to a bottom surface of the upper semiconductor package. The connection pads are on the via holes and the encapsulant. The connection pads electrically connect the lower semiconductor package to the upper semiconductor package. The metal layer pattern is between the lower package substrate and the upper semiconductor package. The metal layer pattern surrounds the connection pads and is isolated from the connection pads.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2013-0115475, filed on Sep. 27, 2013, the disclosure of which is hereby incorporated by reference in its entirety.

BACKGROUND

Example embodiments of inventive concepts relate to a stack-type semiconductor package, a method of fabricating the stack-type semiconductor package, a semiconductor module, an electronic circuit board, and/or an electronic system including the stack-type semiconductor package.

2. Description of Related Art

To improve the integration density of semiconductor devices and downscale electronic circuit systems, a package stack structure has been proposed.

SUMMARY

Example embodiments of inventive concepts relate to a stack-type semiconductor package capable of embodying a fine ball pitch.

Example embodiments of inventive concepts relate to a stack-type semiconductor package having high reliability.

In accordance with example embodiments of inventive concepts, a stack-type semiconductor package includes a lower semiconductor package, an upper semiconductor package, connection pads electrically connecting the lower semiconductor package and the upper semiconductor package, and a metal layer pattern. The lower semiconductor package includes a lower package substrate, a lower semiconductor chip on a top surface of the lower package substrate, lower solder balls on the top surface of the lower package substrate in a vicinity of the lower semiconductor chip, and an encapsulant on the top surface of the lower package substrate. The encapsulant defines via holes that expose the lower solder balls. The upper semiconductor package is on the encapsulant. The upper semiconductor package includes upper solder balls connected to a bottom surface of the upper semiconductor package. The connection pads are on the via holes and the encapsulant. The connection pads electrically connect the lower semiconductor package to the upper semiconductor package. The metal layer pattern is between the lower package substrate and the upper semiconductor package. The metal layer pattern surrounds the connection pads and is isolated from the connection pads.

In example embodiments, a same metal layer may define the metal layer pattern and the connection pads.

In example embodiments, the connection pads may be electrically connected to the lower solder balls through the via holes, and the connection pads may be electrically connected to the upper solder balls on the encapsulant.

In example embodiments, each one of the connection pads may conformally cover both sidewalls of a corresponding one of the via holes, exposed surfaces of a corresponding one of the lower solder balls, and the encapsulant.

In example embodiments, each one of the connection pads may fill a corresponding one of the via holes.

In example embodiments, in a plan view, each of the connection pads has an area covering a corresponding one of the lower solder balls and a corresponding one of the upper solder balls.

In example embodiments, the stack-type semiconductor package may further include redistribution patterns electrically connected to the upper solder balls and the connection pads. The redistribution patterns and the connection pads may be defined from a same metal layer.

In example embodiments, the redistribution patterns may be on a top surface of the lower semiconductor chip.

In example embodiments, the upper solder balls may be on the lower semiconductor chip.

In accordance with example embodiments of inventive concepts, a stack-type semiconductor package includes a lower semiconductor package, an upper semiconductor package, connection pads, and a metal layer pattern. The lower semiconductor package includes a lower package substrate, lower lands on the lower package substrate, a lower semiconductor chip on a top surface of the lower package substrate, and an encapsulant on the top surface of the lower package substrate. The encapsulant defines via holes that expose the lower lands. The upper semiconductor package is on the encapsulant and includes upper solder balls connected to a bottom surface of the upper semiconductor package. The connection pads are on the via holes and the encapsulant. The connection pads electrically connect the lower semiconductor package to the upper semiconductor package. The metal layer pattern is between the lower package substrate and the upper semiconductor package. The metal layer pattern surrounds the connection pads and is isolated from the connection pads.

In example embodiments, the connection pads may be electrically connected to the lower lands through the via holes, and the connection pads may be electrically connected to the upper solder balls on the encapsulant.

In example embodiments, a same metal layer may define the metal layer pattern and the connection pads.

In example embodiments, in a plan view, each of the connection pads may have an area covering an exposed surface of a corresponding one of the lower lands and a corresponding one of the upper solder balls.

In example embodiments, the stack-type semiconductor package may further include redistribution patterns. The redistribution patterns may electrically connect the upper solder balls to the connection pads. A same metal layer may define the redistribution patterns and the connection pads.

In example embodiments, the redistribution patterns may be on a top surface of the lower semiconductor chip, and the upper solder balls may be on the lower semiconductor chip.

According to example embodiments, a stack-type semiconductor package may include a lower package substrate, lower lands on the lower package substrate and surrounding a portion of the substrate, a lower semiconductor chip on the portion of the lower package substrate, an encapsulant on the lower package substrate, a metal layer pattern on the encapsulant and over at least part of the portion of the lower package substrate, and upper package substrate on the lower package substrate, and connection pads electrically isolated from the metal layer pattern. The encapsulant surrounds the lower semiconductor chip and defines via holes that expose the lower land. The upper semiconductor package includes upper solder balls connected to a bottom surface of the upper semiconductor package. The connection pads are electrically connected through the via holes to the lower lands, respectively, and the connection pads are electrically connected to the upper solder balls, respectively.

In example embodiments, lower solder balls may be in the via holes between the connection pads and the lower lands. Each one of the upper solder balls may be electrically connected to a corresponding one of the lower lands through a corresponding one of the connection pads and a corresponding one of the lower solder balls.

In example embodiments, a metal redistribution pattern may be on the lower semiconductor chip. The upper solder balls may be on the metal redistribution pattern and electrically connected to the metal redistribution pattern. The metal redistribution may be surrounded by the metal layer pattern and electrically isolated from the metal layer pattern. The metal redistribution pattern may electric connected each one of the upper solder balls to a corresponding one of the connection pads.

In example embodiments, each one of the connection pads may be directly connected to a corresponding one of the lower lands.

In example embodiments, a same metal layer on a top surface of the encapsulant may define the metal layer pattern and the connection pads.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

Spatially relative terms, such as “top end”, “bottom end”, “top surface”, “bottom surface”, “upper”, and “lower” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary term “below” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

FIG. 1is a cross-sectional view of a stack-type semiconductor package500aaccording to example embodiments of inventive concepts,FIG. 2is a plan view of a lower package substrate ofFIG. 1, andFIG. 3is an enlarged view of portion A ofFIG. 2.

Referring toFIGS. 1, 2, and 3, the stack-type semiconductor package500aaccording to example embodiments of inventive concepts may include a lower semiconductor package100aand an upper semiconductor package200a.

The stack-type semiconductor package500amay have a package-on-package (POP) structure in which the upper semiconductor package200ais stacked on the lower semiconductor package100a. The lower semiconductor package100aand the upper semiconductor package200amay be packages, each of which has finished a packaging process and an electrical test.

The lower semiconductor package100amay include a lower package substrate105and a lower semiconductor chip110mounted on the lower package substrate105.

The lower package substrate105may be a substrate on which a plurality of lower lines are formed. The lower package substrate105may include a rigid printed circuit board (rigid PCB), a flexible PCB, or a rigid-flexible PCB. A rigid-flexible PCB may include a rigid area and a flexible area, and the flexible area may be connected to the rigid area. A rigid-flexible PCB may be used in electronic devices such as notebook computers, PDAs, and wearable devices, but example embodiments are not limited thereto. The lower package substrate105may include a lower core layer102and lower solder resist layers104aand104b. The plurality of lower lines may be formed in the lower core layer102constituting the lower package substrate105. A ground voltage and a power supply voltage may be applied to the plurality of lower lines.

First lower lands106may be formed on a top surface105aof the lower package substrate105and electrically insulated from one another by the first lower solder resist layer104a. Second lower lands108may be formed on a bottom surface105bof the lower package substrate105and electrically insulated from one another by the second lower solder resist layer104b. The first lower lands106may be electrically connected to the second lower lands108by the lower lines. The first and second lower lands106and108may each include at least one metal such as copper (Cu), nickel (Ni), gold (Au), and combinations thereof, or a solder material. A material of the first lower lands106may be the same as or different than a material of the second lower lands108.

External connection members114may be formed on the second lower lands108to electrically connect the stack-type semiconductor package500to a semiconductor module board or a system board. The external connection members114may include a solder material, such as solder balls, solder bumps, or a solder paste, or include a spherical metal, a mesa-shaped metal, or a pin-shaped metal. The external connection members114may be arranged as a grid type to embody a ball grid array (BGA) package.

The lower semiconductor chip110may include a logic device, such as a microprocessor (MP), a microcontroller (MC), or an application processor (AP). The lower semiconductor chip110may be a system-on chip (SOC) in which different kinds of semiconductor devices are disposed in a single semiconductor chip.

The lower semiconductor chip110may be connected to the lower package substrate105using a flip-chip technique. For example, the lower semiconductor chip110may be a flip-chip package (FCP) in which an active surface110aincluding chip pads is disposed opposite the top surface105aof the lower package substrate105, and directly connected onto the lower package substrate105using conductive chip bumps112adhered to the chip pads. The chip pads formed on the active region110aof the lower semiconductor chip110may be electrically connected to the first lower lands106by the chip bumps112and the lower lines. The chip bumps112may include a solder material or at least one metal, such as gold (Au), silver (Ag), platinum (Pt), aluminum (Al), copper (Cu), or nickel (Ni) and combinations thereof. When each of the chip bumps112is a solder bump, each of the chip bumps112may maintain a ball shape due to a surface tension effect. In comparison, when each of the chip bumps112is a metal bump, each of the chip bumps112may be formed as a mesa type.

The lower semiconductor package100amay include lower solder balls115formed on the first lower lands106of the lower package substrate105, and a lower encapsulant116formed on the entire surface of the lower package substrate105and having via holes118exposing the lower solder balls115.

The lower solder balls115may be formed in the same arrangement as the first lower lands106. The lower solder balls115may be formed at a lower level than top surfaces of the via holes118.

The lower encapsulant116may be formed to surround the lower semiconductor chip110and the chip bumps112to protect an electrical connection between the lower semiconductor chip110and the lower package substrate105. Also, the lower encapsulant116may reduce stress applied to the top surface105aof the lower package substrate105. A top surface110bdisposed opposite to the active surface110aof the lower semiconductor chip110may not be covered with the lower encapsulant116. The lower encapsulant116may expose the top surface110bof the lower semiconductor chip110and reduce the entire height of the stack-type semiconductor package500a. The lower encapsulant116may include an epoxy resin or an epoxy mold compound (EMC), but example embodiments are not limited thereto. When necessary, the lower encapsulant116may be formed on the bottom surface105bof the lower package substrate105and protect the second lower solder resist layer104band stably support the external connection members114.

The upper semiconductor package200amay be vertically stacked on the lower semiconductor package100aand include an upper package substrate205and at least one of upper semiconductor chips210and212mounted on the upper package substrate205. The upper semiconductor package200amay be a multi-chip package (MCP) in which a plurality of semiconductor chips are vertically stacked on each other. Alternatively, the upper semiconductor package200amay have a structure in which a plurality of semiconductor chips are vertically stacked on a plurality of semiconductor chips disposed at a level.

The upper package substrate205may be a substrate including a plurality of upper lines, which may include a rigid PCB, a flexible PCB, or a rigid-flexible PCB. The upper package substrate205may include an upper core layer202and upper solder resist layers204aand204b. The plurality of upper lines may be formed in the upper core layer202constituting the upper package substrate205. A ground voltage and a power supply voltage may be applied to the plurality of upper lines.

First upper lands206may be formed on a top surface205aof the upper package substrate205and electrically insulated from one another by a first upper solder resist layer204a. Second upper lands208may be formed on a bottom surface205bof the upper package substrate205and electrically insulated from one another by a second upper solder resist layer204b. The first upper lands206may be connected to the second upper lands208aby the upper lines. The first and second upper lands206and208may include a solder material or at least one metal, such as copper, nickel, or gold and a combination thereof. Only one first upper land206at each end of the upper package substrate205is illustrated inFIG. 1for brevity, but example embodiments are not limited thereto. Each end of the upper package substrate205may include a plurality of first upper lands206.

The upper semiconductor chips210and212may include memory devices. The upper semiconductor chips210and212may be connected to the upper package substrate205using a wire bonding technique or a flip-chip technique. For example, chips pads formed on active surfaces of the upper semiconductor chips210and212may be connected to the first upper lands206of the upper package substrate205by wires214. AlthoughFIG. 1illustrates that the upper semiconductor chips210and212are connected to the upper package substrate205using a wire bonding technique, the upper semiconductor chips210and212alternatively may be directly connected to the upper package substrate205using a flip-chip technique.

The upper semiconductor package200amay further include an upper encapsulant216, which may be formed on the entire surface of the upper package substrate205and protect the active surfaces of the upper semiconductor chips210and212and the wires214. The upper encapsulant214may include an epoxy resin or an EMC, but example embodiments are not limited thereto.

The lower semiconductor package100aof the stack-type semiconductor package500aaccording to example embodiments of inventive concepts may include connection pads120aformed on the via holes118and the lower encapsulant116.

The connection pads120amay be conformally formed on both sidewalls of the via holes118, exposed surfaces of the lower solder balls115, and the lower encapsulant116. From a plan view ofFIG. 3, each of the connection pads120amay be formed to have an area covering the lower solder ball115and an upper solder ball220. Each of the connection pads120amay be in direct contact with the lower solder ball115of the lower package substrate105through the via hole115, and in direct contact with the upper solder ball220of the upper package substrate205on the lower encapsulant116. Thus, each of the connection pads120amay serve as an electrical path between the lower semiconductor package100aand the upper semiconductor package200a. The upper solder balls220may be laterally spaced apart from the lower solder balls115by a desired (and/or alternative predetermined) distance in consideration of solder reflow during a solder joint process for bonding the upper solder balls220with the connection pads120a.

Even if the size of the lower solder balls115is reduced to embody a fine ball pitch, since the upper solder balls220are in direct contact with the connection pads120a, the upper solder balls220may be electrically connected to the lower solder balls115by the connection pads120a. Accordingly, a stack-type semiconductor package having a fine ball pitch of about 0.2 mm or less may be embodied.

The lower semiconductor package100aof the stack-type semiconductor package500aaccording to example embodiments of inventive concepts may include a metal layer pattern120bformed on the entire surface of the lower package substrate105.

The metal layer pattern120bmay be formed in the same layer as the connection pads120a, and isolated from the connection pads120aas shown inFIG. 3. The connection pads120aand the metal layer pattern120bmay include a metal layer120deposited on the entire surface of the lower package substrate105. The metal layer120may include at least one metal such as copper, nickel, aluminum, gold, silver, or an alloy thereof.

Since the metal layer pattern120bfunctions as a heat sink configured to externally effectively dissipate a large amount of heat generated during the driving of the lower semiconductor chip110, the metal layer pattern120bmay increase heat radiation efficiency of the stack-type semiconductor package500aand limit (and/or prevent) operational errors due to overheating. Also, since the metal layer pattern120bfunctions as an electromagnetic interference (EMI) shield layer, the reliability and/or durability of the stack-type semiconductor package500amay be improved.

Hereinafter, stack-type semiconductor packages according to example embodiments of inventive concepts will be described. Here, the differences compared to the semiconductor package according to example embodiments inFIGS. 1-3will chiefly be described.

FIG. 4is a cross-sectional view of a stack-type semiconductor package500baccording to example embodiments of inventive concepts, andFIG. 5is a plan view of a lower package substrate shown inFIG. 4.

Referring toFIGS. 4 and 5, the stack-type semiconductor package500baccording to example embodiments of inventive concepts may have the same structure and effects as the stack-type semiconductor package500ashown inFIG. 1except that connection pads120aare formed to fill via holes118.

From a plan view ofFIG. 5, each of the connection pads120amay be formed to have an area covering the lower solder ball115and an upper solder ball220.

FIG. 6is a cross-sectional view of a stack-type semiconductor package500caccording to example embodiments of inventive concepts, andFIG. 7is a plan view of a portion of a lower package substrate ofFIG. 6.

Referring toFIGS. 6 and 7, the stack-type semiconductor package500caccording to example embodiments of inventive concepts may include a lower semiconductor package100cand an upper semiconductor package200c. The lower semiconductor package100cmay include a lower package substrate105, a lower semiconductor chip110formed on a top surface105aof the lower package substrate105, lower solder balls115formed on the top surface105aof the lower package substrate105in the vicinity of the lower semiconductor chip110, and a lower encapsulant116formed on the top surface105aof the lower package substrate105and having via holes118exposing the lower solder balls115. The upper semiconductor package200cmay be disposed on the lower encapsulant116and have upper solder balls220disposed on a bottom surface205bof an upper package substrate205.

The stack-type semiconductor package500cmay include connection pads120aformed on the via holes118and the lower encapsulant116and configured to electrically connect the lower semiconductor package100cand the upper semiconductor package200c, and a metal layer pattern120bformed on the entire surface of the lower package substrate105and isolated from the connection pads120a.

The stack-type semiconductor package500cmay include redistribution patterns120cformed in the same metal layer120as the connection pads120aand configured to electrically connect the upper solder balls220and the connection pads120a.

As shown inFIG. 7, each of the redistribution patterns120cmay be connected to the connection pad120aand serve to electrically extend the connection pad120aalong the redistribution pattern120c.

The redistribution patterns120cmay be formed on a top surface110bof the lower semiconductor chip110. In this case, the upper solder balls220may be disposed over the lower semiconductor chip110, and be widely disposed on a bottom surface205bof the upper package substrate205. Accordingly, a degree of freedom of design for the upper solder balls220may be increased.

FIG. 8is a cross-sectional view of a stack-type semiconductor package500daccording to example embodiments of inventive concepts.

Referring toFIG. 8, the stack-type semiconductor package500daccording to example embodiments of inventive concepts may have the same structure and effects as the stack-type semiconductor package500cshown inFIG. 6except that connection pads120aare formed to fill via holes118.

FIG. 9is a cross-sectional view of a stack-type semiconductor package500eaccording to example embodiments of inventive concepts, andFIG. 10is a plan view of a portion of a lower package substrate ofFIG. 9.

Referring toFIGS. 9 and 10, the stack-type semiconductor package500eaccording to example embodiments of inventive concepts may include a lower semiconductor package100eand an upper semiconductor package200e. The lower semiconductor package100emay include a lower package substrate105having a top surface105aon which first lower lands106are formed, a lower semiconductor chip110mounted on a top surface105aof the lower package substrate105, and a lower encapsulant116formed on the top surface105aof the lower package substrate105and having via holes118exposing the first lower lands106. The upper semiconductor package200emay be disposed on the lower encapsulant116and have upper solder balls220disposed on a bottom surface205bof an upper package substrate205. The stack-type semiconductor package500emay include connection pads120aformed on the via holes118and the lower encapsulant116and configured to electrically connect the lower semiconductor package100eand the upper semiconductor package200eand a metal layer pattern120bformed on the entire surface of the lower package substrate105.

The connection pads120amay be conformally formed on both sidewalls of the via holes118, exposed surfaces of the first lower lands106, and the lower encapsulant116. From a plan view ofFIG. 10, each of the connection pads120amay be formed to have an area covering an exposed region of the first lower land106and the upper solder ball220.

Each of the connection pads120amay be in direct contact with the first lower land106of the lower package substrate105through the via hole115, and in direct contact with an upper solder ball220of the upper package substrate205on the lower encapsulant116. Thus, each of the connection pads120amay serve as an electrical path between the lower semiconductor package100eand the upper semiconductor package200e.

The metal layer pattern120bmay be formed in the same layer as the connection pads120a, and isolated from the connection pads120aas shown inFIG. 10. The metal layer pattern120bmay function as both a heat sink and an EMI shield layer.

FIG. 11is a cross-sectional view of a stack-type semiconductor package500faccording to example embodiments of inventive concepts.

Referring toFIG. 11, the stack-type semiconductor package500faccording to example embodiments of inventive concepts may have the same structure and effects as the stack-type semiconductor package500eshown inFIG. 9except that connection pads120aare formed to fill via holes118.

FIG. 12is a cross-sectional view of a stack-type semiconductor package according to example embodiments of inventive concepts.FIG. 13is a plan view of a portion of a lower package substrate ofFIG. 12.

Referring toFIGS. 12 and 13, the stack-type semiconductor package500gaccording to example embodiments of inventive concepts may include a lower semiconductor package100gand an upper semiconductor package200g. The lower semiconductor package100gmay include a lower package substrate105having a top surface105aon which first lower lands106are formed, a lower semiconductor chip110mounted on a top surface105aof the lower package substrate105, and a lower encapsulant116formed on the top surface105aof the lower package substrate105and having via holes118exposing the first lower lands106. The upper semiconductor package200gmay be disposed on the lower encapsulant116and have upper solder balls220formed on a bottom surface205bof an upper package substrate205.

The stack-type semiconductor package500gmay include connection pads120aformed on the via holes118and the lower encapsulant116and configured to electrically connect the lower semiconductor package100gand the upper semiconductor package200g, a metal layer pattern120bformed on the entire surface of the lower package substrate105and isolated from the connection pads120a, and redistribution patterns120cconfigured to electrically connect the upper solder balls220and the connection pads120a.

The connection pads120a, the metal layer pattern120b, and the redistribution patterns120cmay be formed in the same metal layer120.

As shown inFIG. 13, each of the redistribution patterns120cmay be connected to the connection pad120aand electrically extend the connection pad120aalong the redistribution pattern120c.

The redistribution patterns120may be formed on a top surface110bof the lower semiconductor chip110. In this case, since the upper solder balls220may be disposed over the lower semiconductor chip110, the upper solder balls220may be widely disposed on the bottom surface205bof the upper package substrate205.

FIG. 14is a cross-sectional view of a stack-type semiconductor package500haccording to example embodiments of inventive concepts.

Referring toFIG. 14, the stack-type semiconductor package500haccording to example embodiments of inventive concepts may have the same structure and effects as the stack-type semiconductor package500gshown inFIG. 12except that connection pads120aare formed to fill via holes118.

Hereinafter, a method of fabricating a stack-type semiconductor package according to example embodiments of inventive concepts will be described with reference toFIGS. 15A through 26.

FIGS. 15A through 19Bare cross-sectional views and plan views illustrating a method of fabricating a stack-type semiconductor package according to example embodiments of inventive concepts.FIGS. 15B, 16B, 17B, 18B, and 19Bare plan views of a portion of a lower package substrate.

Referring toFIGS. 15A and 15B, a lower package substrate105including a lower core layer102, lower solder resist layers104aand104b, and first and second lower lands106and108may be prepared.

The lower package substrate105may be a substrate including a plurality of lower lines, which may include a rigid PCB, a flexible PCB, or a rigid-flexible PCB. The plurality of lower lines may be formed in the lower core layer102constituting the lower package substrate105.

The first lower lands106formed on a top surface105aof the lower package substrate105may be electrically insulated from one another by the first lower solder resist layer104a. The second lower lands108formed on a bottom surface105bof the lower package substrate105may be electrically insulated from one another by the second lower solder resist layer104b. The first lower lands106may be electrically connected to the second lower lands108by the lower lines. The first and second lower lands106and108may include copper, nickel, gold, or a solder material.

A lower semiconductor chip110may be mounted on the lower package substrate105using a flip-chip technique. For example, the lower semiconductor chip110may be disposed such that an active surface110ahaving chip pads faces a top surface105aof the lower package substrate105. Thereafter, the lower semiconductor chip110may be directly connected onto the lower package substrate105using chip bumps112adhered to the chip pads. The chip pads formed on the active surface110aof the lower semiconductor chip110may be electrically connected to the first lower lands106of the first lower package substrate100by the chip bumps112and the plurality of lower lines.

The lower semiconductor chip110may include a logic semiconductor device, such as an MP, an MC, or an AP. The lower semiconductor chip110may be an SOC in which different kinds of semiconductor devices are included in one semiconductor chip. The chip bump112may include gold (Au), silver (Ag), platinum (Pt), aluminum (Al), copper (Cu), or a solder material.

Lower solder balls115may be formed on the first lower lands106of the lower package substrate105. The lower solder balls115may be formed in the same arrangement as the first lower lands106. A lower encapsulant116may be formed on the lower package substrate105having the lower solder balls115to expose a top surface100bof the lower semiconductor chip110. The lower encapsulant116may protect electrical connection between the lower semiconductor chip110and the lower package substrate105and be formed to surround the lower semiconductor chip110and the chip bumps112. Also, the lower encapsulant116may reduce stress applied to the top surface105aof the lower package substrate105. The lower encapsulant116may include an epoxy resin or an EMC.

Referring toFIGS. 16A and 16B, the lower encapsulant116may be selectively removed using a laser drilling process to form via holes118exposing the surfaces of the lower solder balls115.

The via holes118may be formed to expose a top surface and/or side surface of the lower solder ball115or a portion of the surface of the first lower solder resist layer104a. The lower solder ball115may be formed at a lower level than a top surface of the via hole118.

Referring toFIGS. 17A and 17B, a metal layer120may be deposited on the entire surface of the lower package substrate105having the via holes118using, for example, a sputtering process. The metal layer120may include copper, nickel, aluminum, gold, silver, or an alloy thereof. The metal layer120may be conformally formed on both sidewalls of the via holes118, exposed surfaces of the lower solder balls115, and the lower encapsulant116.

Referring toFIGS. 18A and 18B, the metal layer120may be patterned using a laser cutting technique. As a result, connection pads120amay be formed on the via holes118and the lower encapsulant116, and a metal layer pattern120bmay be formed on the entire surface of the lower package substrate105and isolated from the connection pads120a.

Each of the connection pads120amay be electrically connected to the lower solder ball115through the via hole118. The metal layer pattern120bmay function as both a heat sink and an EMI shield layer.

A backend process may be performed on the lower package substrate105having the connection pads120aand the metal layer pattern120b. The backend process may include a process of cutting the lower package substrate105into respective unit semiconductor chips and a process of forming the external connection members114on a bottom surface105bof the lower package substrate105. The external connection members114may be formed in the same arrangement as the second lower lands108. The external connection members114may include a solder material, such as solder balls, solder bumps, or a solder paste, or a spherical metal, a mesa-shaped metal, or a pin-shaped metal. The external connection members114may be arranged as a grid type to embody a BGA package.

Thus, the lower semiconductor package100aincluding the lower package substrate105, the lower semiconductor chip110, the lower solder balls115, the lower encapsulant116, the connection pads120a, the metal layer pattern120b, and the external connection members114may be completed. Since the lower semiconductor package100ais formed using a laser drilling process, the lower semiconductor package100amay be referred to as a laser drill package (LDP).

Referring toFIGS. 19A and 19B, an upper semiconductor package200amay be prepared.

The upper semiconductor package200amay include an upper package substrate205, which may have an upper core layer202, an upper solder resist layers204aand204b, and first and second upper lands206and208.

A plurality of upper semiconductor chips210and212may be mounted on a top surface205aof the upper package substrate205by interposing an adhesive layer, such as a die-attach film (DAF) therebetween. Each of the upper semiconductor chips210and212may include a memory device. The upper semiconductor chips210and212may be electrically connected to first upper lands206of the upper package substrate205by wires214. The wires214may include gold, silver, platinum, aluminum, copper, nickel, cobalt, chromium, or titanium.

An upper encapsulant216may be formed on the upper package substrate205to protect active surfaces of the upper semiconductor chips210and212and the wires214. The upper encapsulant216may include an epoxy resin or an EMC. Upper solder balls220may be formed on the second upper lands208disposed on a bottom surface205bof the upper package substrate205. The upper solder balls220may be laterally spaced apart from the lower solder balls115of the lower semiconductor package100aby a desired (and/or alternative predetermined) distance in consideration of solder reflow during a subsequent solder joint process.

The upper semiconductor package200amay be vertically stacked on the lower semiconductor package100a, and a solder joint process may be performed to bond the upper solder balls220of the upper semiconductor package200awith the connection pads120aof the lower semiconductor package100a. By connecting the upper solder balls220with the connection pads120ausing the solder joint process, the upper semiconductor package200amay be electrically connected to the lower semiconductor package100a.

As shown inFIG. 19B, each of the connection pads120amay be connected to the lower solder balls115through the via hole118, and be connected to the upper solder ball220on the lower encapsulant116. Thus, each of the connection pads120amay serve as an electrical path between the lower semiconductor package100aand the upper semiconductor package200a.

Hereinafter, a method of fabricating a stack-type semiconductor package according to example embodiments of inventive concepts will be described. Here, the same descriptions as in the previous embodiments will be omitted, and only modifications will chiefly be described.

FIGS. 20A and 20Bare cross-sectional views illustrating a method of fabricating a stack-type semiconductor package according to example embodiments of inventive concepts.

Referring toFIG. 20A, the processes described with reference toFIGS. 15A and 16Amay be performed on a lower package substrate105to form a lower semiconductor chip110, lower solder balls115, a lower encapsulant116, and via holes118through the lower encapsulant116to expose the surfaces of the lower solder balls115.

A metal layer120may be deposited on the entire surface of the lower package substrate105using, for example, a sputtering process. The metal layer120may be formed on the lower encapsulant116to a desired (and/or alternative predetermined) thickness to fill the via holes118.

Referring toFIG. 20B, the metal layer120may be patterned using a laser cutting technique to form connection pads120aand a metal layer pattern120b.

The connection pads120amay be formed on the via holes118and the lower encapsulant116and connected to the lower solder balls115through the via holes118. The metal layer pattern120bmay be formed on the entire surface of the lower package substrate105and isolated from the connection pads120a. The metal layer pattern120bmay function as both a heat sink and an EMI shield layer.

External connection members114may be formed on a bottom surface105bof the lower package substrate105having the connection pads120aand the metal layer pattern120bto complete a lower semiconductor package100b. Thereafter, the processes described with reference toFIG. 19Amay be performed. Thus, an upper semiconductor package200bmay be vertically stacked on the lower semiconductor package100b, and the upper solder balls220of the upper semiconductor package200bmay be bonded to the connection pads120ato electrically connect the lower semiconductor package100bwith the upper semiconductor package200b.

FIG. 21is a cross-sectional view illustrating a method of fabricating a stack-type semiconductor package according to example embodiments of inventive concepts.

Referring toFIG. 21, the processes described with reference toFIGS. 15A through 17Amay be performed. Thus, a lower semiconductor chip110, lower solder balls115, a lower encapsulant116, via holes118, and a metal layer120may be formed on a lower package substrate105.

The metal layer120may be conformally formed on both sidewalls of the via holes118, exposed surfaces of the lower solder balls115, and the lower encapsulant116.

The metal layer120may be patterned using a laser cutting technique to form connection pads120a, a metal layer pattern120b, and redistribution patterns120c. The connection pads120amay be connected to the lower solder balls115through the via holes118. The metal layer pattern120bmay be isolated from the connection pads120a. Also, the redistribution patterns120cmay be connected to the connection pads120a.

Each of the connection pads120amay electrically extend along the corresponding redistribution pattern120c. The redistribution patterns120cmay be formed on the top surface110bof the lower semiconductor chip110.

External connection members114may be formed on a bottom surface of the lower package substrate105to complete a lower semiconductor package100c. Thereafter, the processes described with reference toFIG. 19Amay be performed. Thus, an upper semiconductor package200chaving upper solder balls220disposed over the lower semiconductor chip110may be vertically stacked on the lower semiconductor package100c. A solder joint process may be performed to bond the upper solder balls220onto the redistribution patterns120cso that the upper solder balls220can be electrically connected to connection pads120aby the redistribution patterns120c. By electrically connecting the upper solder balls220to the lower solder balls115using the connection pads120a, the lower semiconductor package100cmay be electrically connected to the upper semiconductor package200c.

FIG. 22is a cross-sectional view illustrating a method of fabricating a stack-type semiconductor package according to example embodiments of inventive concepts.

Referring toFIG. 22, the processes described with reference toFIGS. 15A through 17Amay be performed, thereby forming a lower semiconductor chip110, lower solder balls115, a lower encapsulant116, via holes118, and a metal layer120on a lower package substrate105.

The metal layer120may be formed to a desired (and/or alternative predetermined) thickness on the lower encapsulant116to fill the via holes118.

The metal layer120may be patterned using a laser cutting technique to form connection pads120a, a metal layer pattern120b, and redistribution patterns120c. The connection pads120amay be connected to the lower solder balls115through the via holes118. The metal layer pattern120bmay be isolated from the connection pads120a. The redistribution patterns120cmay be connected to the connection pad120a. The metal layer pattern120bmay be formed on the entire surface of the lower package substrate105, and the redistribution patterns120cmay be formed on a top surface110bof the lower semiconductor chip110.

External connection members114may be formed on a bottom surface105bof the lower package substrate105to complete a lower semiconductor package100d. Thereafter, the processes described with reference toFIG. 19Amay be performed. Thus, an upper semiconductor package (refer to200dinFIG. 8) having upper solder balls220disposed over the lower semiconductor chip110may be vertically stacked on the lower semiconductor package100d. Afterwards, the upper solder balls220may be bonded onto the redistribution patterns120cso that the lower semiconductor package100dcan be electrically connected to the upper semiconductor package200d.

FIGS. 23A through 23Care cross-sectional views illustrating a method of fabricating a stack-type semiconductor package according to example embodiments of inventive concepts.

Referring toFIG. 23A, a lower package substrate105including a lower core layer102, lower solder resist layers104aand104b, and first and second lower lands106and108may be prepared.

The first lower lands106formed on a top surface105aof the lower package substrate105may be electrically insulated from one another by the first lower solder resist layer104a. The second lower lands108formed on a bottom surface105bof the lower package substrate105may be electrically insulated from one another by the second lower solder resist layer104b. The first lower lands106may be electrically connected to the second lower lands108by the lower lines.

A lower semiconductor chip110may be mounted on the lower package substrate105using a flip-chip technique. Chip pads formed on an active surface110aof the lower semiconductor chip110may be electrically connected to the first lower lands106of the first lower package substrate100by chip bumps112and a plurality of lower lines.

A lower encapsulant116may be formed on the lower package substrate105on which the lower semiconductor chip110is mounted, to expose a top surface110bof the lower semiconductor chip110. Thereafter, the lower encapsulant116may be selectively removed using a laser drilling process to form via holes118exposing portions of the surfaces of the first lower lands106.

Referring toFIG. 23B, a metal layer120may be deposited using, for example, a sputtering process on the entire surface of the lower package substrate105having the via holes118. The metal layer120may be conformally formed on both sidewalls of the via holes118, exposed surfaces of the first lower lands106, and the lower encapsulant116.

Referring toFIG. 23C, the metal layer120may be patterned using a laser cutting technique to form connection pads120aand a metal layer pattern120b.

The connection pads120amay be formed on the via holes118and the lower encapsulant116, and be connected to the first lower lands106through the via holes118. The metal layer pattern120bmay be formed on the entire surface of the lower package substrate105and isolated from the connection pads120a.

External connection members114may be formed on the bottom surface105bof the lower package substrate105to complete a lower semiconductor package100e.

Thereafter, the processes described with reference toFIG. 19Amay be performed. Thus, an upper semiconductor package (refer to200einFIG. 9) may be vertically stacked on the lower semiconductor package100e. Thereafter, upper solder balls220of the upper semiconductor package200emay be bonded to the connection pads120ausing a solder joint process so that the lower semiconductor package100ecan be electrically connected to the upper semiconductor package200e.

The connection pads120amay be connected to first lower lands106of the lower semiconductor package100ethrough the via holes115, and be connected to the upper solder balls220of the upper semiconductor package200eon the lower encapsulant116. Thus, each of the connection pads120amay serve as an electrical path between the lower semiconductor package100eand the upper semiconductor package200e.

FIGS. 24A and 24Bare cross-sectional views illustrating a method of fabricating a stack-type semiconductor package according to example embodiments of inventive concepts.

Referring toFIG. 24A, the processes described with reference toFIG. 23Amay be performed. Thus, a lower semiconductor chip110and a lower encapsulant116may be formed on a lower package substrate105having a top surface105aon which first lower lands106are formed. Via holes118may be formed through the lower encapsulant116to expose the first lower lands106.

A metal layer120may be deposited using, for example, a sputtering process on the entire surface of the lower package substrate105. The metal layer120may be formed to a desired (and/or alternative predetermined) thickness on the lower encapsulant116to fill the via holes118.

Referring toFIG. 24B, the metal layer120may be patterned using a laser cutting technique to form connection pads120aand a metal layer pattern120b. The connection pads120amay be connected to the first lower lands106through the via holes118. The metal layer pattern120bmay be isolated from the connection pads120a.

External connection members114may be formed on a bottom surface105of the lower package substrate105to complete a lower semiconductor package100f. Thereafter, the processes described with reference toFIG. 19Amay be performed. Thus, an upper semiconductor package (refer to200finFIG. 11) may be vertically stacked on the lower semiconductor package100f. Thereafter, the connection pads120amay be bonded to upper solder balls220so that the lower semiconductor package100fcan be electrically connected to the upper semiconductor package200f.

FIG. 25is a cross-sectional view illustrating a method of fabricating a stack-type semiconductor package according to example embodiments of inventive concepts.

Referring toFIG. 25, the processes described with reference toFIGS. 23A and 23Bmay be performed. Thus, a lower semiconductor chip110, a lower encapsulant116, via holes118, and a metal layer120may be formed on a lower package substrate105having a top surface105aon which first lower lands106are formed. The via holes118may expose portions of the surfaces of the first lower lands106.

The metal layer120may be conformally formed on both sidewalls of the via holes118, exposed surfaces of the first lower lands106, and the lower encapsulant116.

The metal layer120may be patterned using a laser cutting technique, thereby forming connection pads120a, a metal layer pattern120b, and redistribution patterns120c. The connection pads120amay be formed on the via holes118and the lower encapsulant116, and connected to the first lower lands106through the via holes118. The metal layer pattern120bmay be formed on the entire surface of the lower package substrate105and isolated from the connection pads120a. The redistribution patterns120cmay be connected to the connection pad120aand formed on a top surface of the lower semiconductor chip110. Each of the connection pads120amay electrically extend along the corresponding redistribution pattern120c.

External connection members114may be formed on a bottom surface105bof the lower package substrate105to complete a lower semiconductor package100g. Thereafter, the processes described with reference toFIG. 19Amay be performed. Thus, an upper semiconductor package (refer to200ginFIG. 12) having upper solder balls220disposed over the lower semiconductor chip110may be vertically stacked on the lower semiconductor package100g.

The upper solder balls220may be bonded onto the redistribution patterns120cusing a solder joint process so that the upper solder balls220can be electrically connected to connection pads120aby redistribution patterns120c. The upper solder balls220may be electrically connected to the lower solder balls115by the connection pads120aso that the lower semiconductor package100gcan be electrically connected to the upper semiconductor package200g.

FIG. 26is a cross-sectional view illustrating a method of fabricating a stack-type semiconductor package according to example embodiments of inventive concepts.

Referring toFIG. 26, the processes described with reference toFIGS. 23A and 23Bmay be performed. Thus, a lower semiconductor chip110, a lower encapsulant116, via holes118, and a metal layer120may be formed on a lower package substrate105having a top surface105aon which first lower lands106are formed. The via holes118may expose portions of the surfaces of the first lower lands106.

The metal layer120may be formed to a desired (and/or alternative predetermined) thickness on the lower encapsulant116to fill the via holes118.

The metal layer120may be patterned using a laser cutting technique to form connection pads120a, a metal layer pattern120b, and redistribution patterns120c. The connection pads120amay be connected to the first lower lands106through the via holes118. The metal layer pattern120bmay be isolated from the connection pads120a. The redistribution patterns120cmay electrically extend the connection pads120a.

External connection members114may be formed on a bottom surface105bof the lower package substrate105to complete a lower semiconductor package100g. Thereafter, the processes described with reference toFIG. 19Amay be performed. Thus, an upper semiconductor package (refer to200hinFIG. 14) having upper solder balls220disposed over the lower semiconductor chip110may be vertically stacked on the lower semiconductor package100h. Also, the upper solder balls220may be bonded onto the redistribution patterns120cso that the lower semiconductor package100hcan be electrically connected to the upper semiconductor package200hby the connection pads120aand the redistribution patterns120c.

FIG. 27is a cross-sectional view of a stack-type semiconductor package according to example embodiments of inventive concepts.

Referring toFIG. 27, a stack-type semiconductor package500iaccording to example embodiments may be the same as the stack-type semiconductor package500fdescribed previously with reference toFIG. 11, except for the structure of the connection pads120a. As shown inFIG. 27, the stack-type semiconductor package500imay include plugs170filling the via holes118. The plugs170may include a conductive material such as a metal or metal alloy. The connection pads120amay be formed on the plugs170. An upper surface of the plugs170may be level with an upper surface of the lower encapsulant116. A material of the plugs170may be different than a material of at least one of the connection pads120aand the lower lands106.

FIG. 28is a cross-sectional view of a stack-type semiconductor package according to example embodiments of inventive concepts.

Referring toFIG. 28, a stack-type semiconductor package500jaccording to example embodiments may be the same as the stack-type semiconductor package500hdescribed previously with reference toFIG. 14, except for the structure of the connection pads120a. As shown inFIG. 28, the stack-type semiconductor package500jmay include plugs170filling the via holes118. The connection pads120amay be formed on the plugs170.

FIG. 29is a schematic diagram of a semiconductor module including a stack-type semiconductor package according to example embodiments of inventive concepts.

Referring toFIG. 29, a semiconductor module1100on which a package stack structure is mounted, according to example embodiments of inventive concepts, may include a module substrate1110, a plurality of semiconductor devices or stack-type semiconductor packages1120disposed on the module substrate1110, and module contact terminals1130formed in a row on one edge of the module substrate1110and electrically connected to the semiconductor devices or stack-type semiconductor packages1120, respectively. The stack-type semiconductor packages1120may be one of the above-described stack-type semiconductor packages according to example embodiments, described with reference toFIGS. 1-14 and 27-28.

The module substrate1110may be a printed circuit board (PCB). Both surfaces of the module substrate1110may be used. In other words, the semiconductor devices or stack-type semiconductor packages1120may be disposed on both front and rear surfaces of the module substrate1110.

The semiconductor module1100may further include an additional controller or chipset configured to control the semiconductor devices or stack-type semiconductor packages1120.

The module contact terminals1130may be formed of a metal and have oxidation resistance. The module contact terminals1130may be variously set according to standard protocols of the semiconductor module1110.

FIG. 30is a schematic block diagram of an electronic circuit board1200including a stack-type semiconductor package according to example embodiments of inventive concepts.

Referring toFIG. 30, the electronic circuit board1200according to example embodiments of inventive concepts may include a microprocessor (MP)1220disposed on a circuit board1210, a main storage circuit1230and a supplementary storage circuit1240configured to communicate with the MP1220, an input signal processing circuit1250configured to transmit commands to the MP1220, an output signal processing circuit1260configured to receive commands from the MP1220, and a communication signal processing circuit1270configured to transmit and receive electric signals to and from other circuit boards. InFIG. 30, arrows may be referred to as paths through which signals may be transmitted.

The MP1220may receive and process various electric signals, output processing results, and control other components of the electronic circuit board1200. The MP1220may be interpreted as, for example, a central processing unit (CPU) and/or a main control unit (MCU).

The main storage circuit1230may temporarily store data always or frequently required by the MP1220or data to be processed or already processed data. Since the main storage circuit1230needs a high response speed, the main storage circuit1230may include a semiconductor memory device. More specifically, the main storage circuit1230may be a semiconductor memory device called a cache or include a static random access memory (SRAM), a dynamic RAM (DRAM), a resistive RAM (RRAM), applied semiconductor memory devices thereof (e.g., an utilized RAM, a ferroelectric RAM (FRAM), a fast-cycle RAM, a phase-changeable RAM (PRAM), and a magnetic RAM (MRAM)) and other semiconductor memory devices. The semiconductor device may be included in one of the above-described stack-type semiconductor packages according to example embodiments of inventive concepts, described with reference toFIGS. 1-14 and 27-28. Also, the main storage circuit1230may include a volatile or nonvolatile random access memory device. In example embodiments, the main storage circuit1230may include a semiconductor module1100having stack-type semiconductor packages according to example embodiments of inventive concepts.

The supplementary storage circuit1240may be a mass storage device, which may be a nonvolatile semiconductor memory, such as a flash memory, or a hard disc drive (HDD) using a magnetic field. Alternatively, the supplementary storage circuit1240may be a compact disc drive (CDD) using light. The supplementary storage circuit1240may be used to store a larger amount of data at lower speed as compared with the main storage circuit1230. The supplementary storage circuit1240may include a semiconductor module1100having stack-type semiconductor packages according to example embodiments of inventive concepts.

The input signal processing circuit1250may change an external command into an electric signal or transmit an external electric signal to the MP1220. The external command or electric signal may be an operation command, an electric signal to be processed, or data to be stored. The input signal processing circuit1250may be a terminal signal processing circuit configured to process signals transmitted from, for example, a keyboard, a mouse, a touch pad, an image recognition apparatus, or various sensors, an image signal processing circuit configured to process an image signal input by a scanner or a camera, various sensors, or an input signal interface. The input signal processing circuit1250may include a semiconductor module1100having stack-type semiconductor packages according to example embodiments of inventive concepts.

The output signal processing circuit1260may be a component configured to externally transmit an electric signal processed by the MP1220. For instance, the output signal processing circuit1260may be a graphic card, an image processor, an optical converter, a beam panel card, or a multifunctional interface circuit. The output signal processing circuit1260may include a semiconductor module1100having stack-type semiconductor packages according to example embodiments of inventive concepts.

The communication circuit1270may be a component configured to directly transmit and receive electric signals to and from another electronic system or another circuit substrate without passing through the input signal processing circuit1250or the output signal processing circuit1260. For example, the communication circuit1270may be a modem, a local area network (LAN) card, or various interface circuits of a personal computer (PC) system. The communication circuit1270may include a semiconductor module1100having stack-type semiconductor packages according to example embodiments of inventive concepts.

FIG. 31is a schematic block diagram of an electronic system1300including a semiconductor module having stack-type semiconductor packages according to example embodiments of inventive concepts.

Referring toFIG. 31, the electronic system1300according to example embodiments of inventive concepts may include a control unit1310, an input unit1320, an output unit1330, and a storage unit1340and further include a communication unit1350and/or another operation unit1360.

The control unit1310may generally control the electronic system1300and respective units. The control unit1310may be interpreted as a CPU and/or an MCU and include the electronic circuit board1200according to example embodiments of inventive concepts. Also, the control unit1310may include a semiconductor module1100having stack-type semiconductor packages according to example embodiments of inventive concepts.

The input unit1320may transmit electrical command signals to the control unit1310. The input unit1320may be an image recognition unit, such as a keyboard, a keypad, a mouse, a touch pad, or a scanner, or various input sensors. The input unit1320may include a semiconductor module1100having stack-type semiconductor packages according to example embodiments of inventive concepts.

The output unit1330may receive electric command signals from the control unit1310and output processing results of the electronic system1300. The output unit1330may be a monitor, a printer, a beam radiator, or various mechanical apparatuses. The output unit1330may include a semiconductor module1100having stack-type semiconductor packages according to example embodiments of inventive concepts.

The storage unit1340may be a component configured to temporarily or permanently store electric signals already processed or to be processed by the control unit1310. The storage unit1340may be physically and electrically connected or combined with the control unit1310. The storage unit1340may be a semiconductor memory, a magnetic storage device such as a hard disk, an optical storage device such as a compact disc (CD), or a server having other data storage functions. Furthermore, the storage unit1340may include a semiconductor module1100having stack-type semiconductor packages according to example embodiments of inventive concepts.

The communication unit1350may receive electric command signals from the control unit1310and transmit and receive electric signals to and from another electronic system. The communication unit1350may be a modem, a wired transceiving device such as a LAN card, a wireless transceiving device such as a wireless broadband (WiBro) interface, or an infrared (IR) port. In addition, the communication unit1350may include a semiconductor module1100having stack-type semiconductor packages according to example embodiments of inventive concepts.

The operation unit1360may perform physical or mechanical operations in response to commands of the control unit1310. For example, the operation unit1360may be a component configured to perform mechanical operations, such as a plotter, an indicator, or an up/down operator. The electronic system1300according to example embodiments of inventive concepts may be a computer, a network server, a networking printer or scanner, a wireless controller, a mobile communication terminal, an exchanger, or an electronic product capable of other programmed operations.

According to example embodiments of inventive concepts, connection pads configured to electrically connect a lower semiconductor package and an upper semiconductor package can be formed on a top surface of a lower encapsulant formed on a lower package substrate.

Each of the connection pads can be electrically connected to a lower solder ball of the lower package substrate through a via hole formed in the lower encapsulant, and be electrically connected to an upper solder ball of the upper package substrate on the lower encapsulant. Since each of the connection pads serves as an electrical path between the upper semiconductor package and a lower semiconductor package, a stack-type semiconductor package having a fine ball pitch can be embodied.

A metal layer pattern formed on the entire surface of the lower package substrate apart from the connection pads can function as a heat sink configured to dissipate heat generated by a lower semiconductor chip. Thus, a stack-type semiconductor package having excellent heat radiation characteristics can be embodied. Furthermore, since the metal layer pattern can function as an EMI shield layer, the reliability and durability of the stack-type semiconductor package can be improved.

The foregoing is illustrative of embodiments and is not to be construed as limiting thereof.