Frequency and load balance compensated, gate firing phase shift delay line

An apparatus for an alpha trim adjustment includes a phase delay circuit that creates a phase delay for a gate signal for a switching cycle. The gate signal is for a phase of a three-phase, phase shifted alternating current (“AC”) input of a multi-pulse motor drive powering a direct current (“DC”) motor. The apparatus includes an alpha trim circuit that modifies the phase delay with an alpha trim adjustment to create an adjusted phase delay for the switching cycle, a delay application circuit that applies the adjusted phase delay to the gate signal.

BACKGROUND INFORMATION

The subject matter disclosed herein relates to motor controllers and more specifically applies to multi-pulse motor controllers for direct current (“DC”) motors.

BRIEF DESCRIPTION

An apparatus with an alpha trim adjustment includes a phase delay circuit that creates a phase delay for a gate signal for a switching cycle. The gate signal is for a switch of a phase of a three-phase, phase shifted alternating current (“AC”) input of a multi-pulse motor drive powering a direct current (“DC”) motor. The apparatus includes an alpha trim circuit that modifies the phase delay with an alpha trim adjustment to create an adjusted phase delay for the switching cycle, a delay application circuit that applies the adjusted phase delay to the gate signal.

Another apparatus with an alpha trim adjustment includes a first delay circuit that delays a gate signal by 30 degrees plus a first alpha trim adjustment for a first switching cycle. The gate signal is for a phase of a three-phase, phase shifted AC input of a multi-pulse motor drive powering a DC motor. The apparatus includes a second delay circuit that delays the gate signal by 30 degrees plus a second alpha trim adjustment for another switching cycle and a setup switch that changes between a first position that connects the first delay circuit while disconnected from the second delay circuit and a second position that connects the second delay circuit while disconnected from the first delay circuit. The apparatus includes a setup switch controller that changes the setup switch between the first position and the second position during a non-switching period between switching cycles. The apparatus includes an average current circuit that measures current from two or more phases feeding a 0-degree rectifier of the multi-pulse motor drive and that measures current from two or more phases feeding a 30-degree rectifier of the multi-pulse motor drive and that averages the currents from the phases of feeding the 0-degree rectifier and averages the currents from the phases feeding the 30-degree rectifier. The apparatus includes an alpha trim circuit that adjusts the second alpha trim adjustment while the setup switch is in the first position and that sets the first alpha trim adjustment while the setup switch is in the second position in response to an amplitude difference between the average current from the 0-degree rectifier and the average current from the 30-degree rectifier.

A multi-pulse motor controller with an alpha trim adjustment includes a 0-degree rectifier with a plurality of drive switches each driven by a gate signal. The 0-degree rectifier is fed by non-phase-shifted phases of a power source. The multi-pulse motor controller includes a 30-degree rectifier includes a plurality of drive switches each driven by a gate signal, the 30-degree rectifier fed by phase-shifted phases of a power source. Outputs of the 0-degree rectifier and the 30-degree rectifier feed a DC motor. Each drive switch of the 30-degree rectifier includes a first delay circuit that delays a gate signal by 30 degrees plus a first alpha trim adjustment for a first switching cycle, a second delay circuit that delays the gate signal by 30 degrees plus a second alpha trim adjustment for another switching cycle, and a setup switch that changes between a first position that connects the first delay circuit while disconnecting the second delay circuit and a second position that connects the second delay circuit while disconnecting the first delay circuit. The multi-pulse motor drive includes a setup switch controller that changes the setup switch of a drive switch between the first position and the second position during a non-switching period between switching cycles of the drive switch, and an alpha trim circuit that, for each drive switch, adjusts the second alpha trim adjustment while the setup switch of the drive switch is in the first position and that sets the first alpha trim adjustment while the setup switch for the drive switch is in the second position.

DETAILED DESCRIPTION

Many of the functional units described in this specification have been labeled as circuits, in order to more particularly emphasize their implementation independence. For example, a circuit may be implemented as a hardware circuit comprising custom VLSI circuits or gate arrays, off-the-shelf semiconductors such as logic chips, transistors, or other discrete components. A circuit may also be implemented in programmable hardware devices such as field programmable gate arrays, programmable array logic, programmable logic devices or the like.

More specific examples of the computer readable storage medium may include but are not limited to a portable computer diskette, a hard disk, a random access memory (“RAM”), a read-only memory (“ROM”), an erasable programmable read-only memory (“EPROM” or Flash memory), a portable compact disc read-only memory (“CD-ROM”), a digital versatile disc (“DVD”), an optical storage device, a magnetic storage device, a holographic storage medium, a micromechanical storage device, or any suitable combination of the foregoing. In the context of this document, a computer readable storage medium may be any tangible medium that can contain, and/or store program code for use by and/or in connection with an instruction execution system, apparatus, or device.

The computer readable medium may also be a computer readable signal medium. A computer readable signal medium may include a propagated data signal with program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated signal may take any of a variety of forms, including, but not limited to, electrical, electro-magnetic, magnetic, optical, or any suitable combination thereof. A computer readable signal medium may be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport program code for use by or in connection with an instruction execution system, apparatus, or device. Program code embodied on a computer readable signal medium may be transmitted using any appropriate medium, including but not limited to wire-line, optical fiber, Radio Frequency (“RF”), or the like, or any suitable combination of the foregoing

An apparatus with an alpha trim adjustment includes a phase delay circuit that creates a phase delay for a gate signal for a switching cycle. The gate signal is for a switch of a phase of a three-phase, phase shifted alternating current (“AC”) input of a multi-pulse motor drive powering a direct current (“DC”) motor. The apparatus includes an alpha trim circuit that modifies the phase delay with an alpha trim adjustment to create an adjusted phase delay for the switching cycle, a delay application circuit that applies the adjusted phase delay to the gate signal.

In some embodiments, the switching cycle is a first switching cycle and further comprising another switching cycle and, for each gate signal, the phase delay circuit includes a first delay circuit that includes the phase delay modified by a first alpha trim adjustment from the alpha trim circuit, and a second delay circuit that comprises the phase delay modified by a second alpha trim adjustment from the alpha trim circuit. The delay application circuit includes a setup switch that changes between a first position that connects the first delay circuit while disconnected from the second delay circuit and a second position that connects the second delay circuit while disconnected from the first delay circuit, and a setup switch controller that changes the setup switch between the first position and the second position during a non-switching period between switching cycles.

In other embodiments, the first delay circuit and the second delay circuit each include a plurality of clock-driven delay components arrangeable in series where each delay component provides a fixed amount of delay relative to a period of a clock signal and a number of delay components connected in series provides a delay of the period of the clock signal multiplied by the number of delay components connected in series. In other embodiments, the alpha trim circuit connects and disconnects delay components of the first and second delay circuits to a number of delay components in the first and second delay circuits connected in series to provide a phase delay. In other embodiments, the apparatus includes a frequency adjustment circuit that connects and disconnects delay components to maintain the phase delay in response to variations in a fundamental frequency of a power source providing power to the multi-pulse motor drive.

In some embodiments, the setup switch controller include a drive switch detection circuit that asserts a switch-on signal in response to detecting a switching cycle where the setup switch controller changes the setup switch between the first position and the second position during a period when the switch-on signal is not asserted. In other embodiments, the multi-pulse motor drive includes a 0-degree rectifier and a 30-degree rectifier. The 0-degree rectifier and the 30-degree rectifier each include a forward set of drive switches for driving the DC motor current in a forward direction and a negative set of drive switches for driving the DC motor current in a reverse direction and the switch-on signal is used by a lockout signal that turns off switching in the 0-degree rectifier and the 30-degree rectifier during a transition between forward and reverse driving of the DC motor.

In some embodiments, the alpha trim adjustment adds delay to or subtracts delay from the phase delay. In other embodiments, the alpha trim circuit adjusts the alpha trim adjustment in response to an amplitude difference between current from a 0-degree rectifier of the multi-pulse motor drive and current from a 30-degree rectifier of the multi-pulse motor drive. In other embodiments, the alpha trim circuit includes a comparator that compares current from a 0-degree rectifier of the multi-pulse motor drive and current from a 30-degree rectifier of the multi-pulse motor drive, an alpha pulse circuit increases the alpha trim adjustment in response to an output from the comparator indicative of the current from the 30-degree rectifier being higher than the current from the 0-degree rectifier; and decreases the alpha trim adjustment in response to an output from the comparator indicative of the current from the 30-degree rectifier being lower than the current from the 0-degree rectifier. In other embodiments, the apparatus includes an alpha pulse rate limiter that controls the alpha pulse circuit to limit a rate of increase and decrease of the alpha trim adjustment.

In other embodiments, the apparatus includes an average current circuit that measures current from two or more phases feeding a 0-degree rectifier of the multi-pulse motor drive and that measures current from two or more phases feeding a 30-degree rectifier of the multi-pulse motor drive and that averages the currents from the phases of feeding the 0-degree rectifier to provide a first input to the comparator and averages the currents from the phases feeding the 30-degree rectifier to provide a second input to the comparator. In other embodiments, the comparator provides a digital output to the alpha pulse circuit and the alpha pulse circuit provides an increase output with a digital pulse on an increase alpha trim line and provides a decrease output comprising a digital pulse on a decrease alpha trim line. In other embodiments, the alpha trim circuit includes an up/down counter that maintains a current alpha trim adjustment and increases the current alpha trim adjustment in response to a digital pulse on an increase alpha trim line and decreases the current alpha trim adjustment in response to a digital pulse on a decrease alpha trim line.

In some embodiments, the multi-pulse motor drive includes a phase delay circuit for each drive switch of a 30-degree rectifier of the multi-pulse motor drive. In other embodiments, the multi-pulse motor drive includes a 0-degree rectifier and a 30-degree rectifier. The 0-degree rectifier and the 30-degree rectifier each include a forward set of drive switches for driving the DC motor current in a forward direction and a negative set of drive switches for driving the DC motor current in a reverse direction where each drive switch of the 30-degree rectifier includes a phase delay circuit and the alpha trim circuit modifies the phase delay for each drive switch.

Another apparatus with an alpha trim adjustment includes a first delay circuit that delays a gate signal by 30 degrees plus a first alpha trim adjustment for a first switching cycle. The gate signal is for a phase of a three-phase, phase shifted AC input of a multi-pulse motor drive powering a DC motor. The apparatus includes a second delay circuit that delays the gate signal by 30 degrees plus a second alpha trim adjustment for another switching cycle and a setup switch that changes between a first position that connects the first delay circuit while disconnected from the second delay circuit and a second position that connects the second delay circuit while disconnected from the first delay circuit. The apparatus includes a setup switch controller that changes the setup switch between the first position and the second position during a non-switching period between switching cycles. The apparatus includes an average current circuit that measures current from two or more phases feeding a 0-degree rectifier of the multi-pulse motor drive and that measures current from two or more phases feeding a 30-degree rectifier of the multi-pulse motor drive and that averages the currents from the phases of feeding the 0-degree rectifier and averages the currents from the phases feeding the 30-degree rectifier. The apparatus includes an alpha trim circuit that adjusts the second alpha trim adjustment while the setup switch is in the first position and that sets the first alpha trim adjustment while the setup switch is in the second position in response to an amplitude difference between the average current from the 0-degree rectifier and the average current from the 30-degree rectifier.

In some embodiments, the first delay circuit and the second delay circuit each includes a plurality of clock-driven delay components arrangeable in series where each delay component provides a fixed amount of delay relative to a period of a clock signal and a number of delay components connected in series provides a delay of the period of the clock signal multiplied by the number of delay components connected in series, and where the alpha trim circuit connects and disconnects delay components of the first and second delay circuits to a number of delay components in the first and second delay circuits connected in series to provide a phase delay. In other embodiments, the setup switch controller includes a drive switch detection circuit that asserts a switch-on signal in response to detecting a switching cycle, where the setup switch controller changes the setup switch between the first position and the second position during a period when the switch-on signal is not asserted.

A multi-pulse motor controller with an alpha trim adjustment includes a 0-degree rectifier with a plurality of drive switches each driven by a gate signal. The 0-degree rectifier is fed by non-phase-shifted phases of a power source. The multi-pulse motor controller includes a 30-degree rectifier includes a plurality of drive switches each driven by a gate signal, the 30-degree rectifier fed by phase-shifted phases of a power source. Outputs of the 0-degree rectifier and the 30-degree rectifier feed a DC motor. Each drive switch of the 30-degree rectifier includes a first delay circuit that delays a gate signal by 30 degrees plus a first alpha trim adjustment for a first switching cycle, a second delay circuit that delays the gate signal by 30 degrees plus a second alpha trim adjustment for another switching cycle, and a setup switch that changes between a first position that connects the first delay circuit while disconnecting the second delay circuit and a second position that connects the second delay circuit while disconnecting the first delay circuit. The multi-pulse motor drive includes a setup switch controller that changes the setup switch of a drive switch between the first position and the second position during a non-switching period between switching cycles of the drive switch, and an alpha trim circuit that, for each drive switch, adjusts the second alpha trim adjustment while the setup switch of the drive switch is in the first position and that sets the first alpha trim adjustment while the setup switch for the drive switch is in the second position.

FIG. 1is a schematic block diagram100of one embodiment of a 12-pulse motor drive powering a direct current (“DC”) motor102and one embodiment of control circuits. It is typical for motor drives to be fed from a 3-phase alternating current (“AC”) source104. Typical 3-phase motor drives use a rectifier circuit, such as a full-bridge rectifier to convert 3-phase AC voltage to DC voltage useful for driving a DC motor, a non-motor load, such as an electro-plating operation, or for a DC bus, which may be used for conversion to an AC waveform with a variable frequency for driving an AC motor. A problem with 3-phase motor drives is that many topologies generate harmonics that waste power and require oversized equipment to handle the harmonic currents. In addition, harmonic currents drawn by 3-phase drives can cause problems for utilities providing the 3-phase power. A variety of methods are used to reduce harmonics, which often involve additional components, such as inductors, capacitors, etc. As motor sizes increase, component sizes increase, including components for mitigating harmonics.

Multi-pulse motor drives, such as a 12-pulse motor drive, offer a way to reduce harmonics. A typical 12-pulse motor drive includes a delta-delta-wye transformer106(e.g. “transformer106”) where the primary is delta-connected. The transformer106has two secondaries where one secondary is delta-connected and the other secondary is wye-connected, which has a 30-degree phase shift from the delta-connected secondary. The 12-pulse motor drive includes at least two rectifiers; a 0-degree rectifier108for the delta-connected secondary and a 30-degree rectifier112for the wye-connected secondary.

The 12-pulse motor drive may also include two 0-degree rectifiers108,110for the delta-connected secondary, where a forward 0-degree rectifier108is for driving current of the DC motor102in a forward direction the other reverse 0-degree rectifier110is for driving current of the DC motor102in a reverse direction. For the wye-connected secondary, a forward 30-degree rectifier112is for driving current of the DC motor102in the forward direction and the other reverse 30-degree rectifier114is for driving current of the DC motor102in the reverse direction. Pulses generated by the 0-degree rectifiers108,110are offset from pulses generated by the 30-degree rectifiers112,114, which increases efficiency and reduces harmonics and power losses.

In some embodiments, the 12-pulse motor drive includes an inductor circuit116that helps to reduce harmonics. Arrows in the inductor circuit116and in the line from the inductor circuit116to the DC motor102indicate current flow for a forward motor direction.

The 12-pulse motor drive includes a regulator118that determines if the DC motor102needs more power or less power to maintain a certain speed for a particular load, to increase speed, to decrease speed, to react to a load change, etc. The regulator118typically adjusts a turn-on time of switches F1-F6of the rectifiers108-114to adjust a DC voltage level feeding the DC motor102. In some embodiments, the regulator118is a PowerFlex® DC Stand-Alone Regulator by Allen-Bradley®. The switches F1-F6may be of any known thyristor devices, such as an SCR, for example. The switches F1-F6are typically switched with respect to a zero-crossing of a sinusoidal waveform of each phase feeding the rectifiers108-114.

While a 12-pulse motor drive is depicted inFIG. 1, other multi-pulse motor drives may be used for embodiments described herein. For example, the multi-pulse motor drive may be 6-pulse motor drive, an 18-pulse motor drive, a 24-pulse motor drive, and the like. While a 12-pulse motor drive creates a set of 0-degree lines and a set of 30-degree delay lines, where drive signals are delayed 30 degrees for the 30-degree delay lines, other multi-pulse motor drives include other delays, such as 15 degrees, 20 degrees, 40 degrees, 45 degrees, etc. In other embodiments, the multi-pulse motor drive is used for series connected motor drives. For example, the series connected motor drives may be multi-pulse where rectifiers are connected in series. A multi-pulse series connected motor drive may include differing numbers of rectifiers with different phase delays, such as 15 degrees, 20 degrees, 40 degrees, 45 degrees, etc. Multi-pulse series connected motor drives typically need to balance control voltage instead of current so that output voltages of rectifier are used as an input signal instead of current from a current transformer112. As used herein, a multi-pulse motor drive includes both series and parallel motor drives of various pulses.

A fundamental frequency of the AC source104is typically 50 hertz (“Hz”) or 60 Hz, but other fundamental frequencies may be used. The regulator118, in one example, may delay turn on of the switches F1-F6for 35 degrees from the previous zero crossing of a sinusoidal waveform. The 35 degree delay, in one embodiment, may be called a firing angle. Where voltage to the DC motor102is to be increased, the regulator118may reduce the firing angle, for example to 30-degrees, so that power is connected through the rectifiers (e.g.108,112) to the DC motor102for a longer period than for the 35-degree firing angle. Alternatively, where voltage to the DC motor102is to be decreased, the regulator118may further delay switching so the firing angle is 40 degrees so that power is connected through the rectifiers (e.g.108,112) to the DC motor102for a shorter period of time. Note that other switching schemes and switches may also be used, such as symmetric voltage cancellation (“SVC”) control, asymmetric voltage cancellation (“AVC”) control, fixed conduction angle with variable voltage control, fixed conduction angle control, and the like. Any switching technique may be used that is compatible with a multi-pulse motor controller.

The regulator118typically provides gate signals to a gate drive circuit120for the 0-degree rectifiers108,110and through a delay circuit122to a gate drive circuit124for the 30-degree rectifiers (e.g.112,114). In an alternate embodiment, the gate drive circuit120provides gate signals to the phase delay circuit122. In a typical 12-pulse motor drive, the delay circuit122provides a 30-degree delay from the firing of the switches F1-F6by the regulator118. As used herein, a 0-degree signal fed to the 0-degree rectifiers108,110is referenced from the firing angle. Likewise, a 30-degree signal fed to the 30-degree rectifiers112,114is delayed from the firing angle by 30-degrees. Note that a 30-degree delay is dependent on the fundamental frequency of the AC source104.

A 60 Hz fundamental frequency has a period of 16.67 microseconds (“mS”) so that a 30-degree delay will be 1.39 mS. A 50 Hz fundamental frequency has a period of 20 mS so that a 30-degree delay will be 1.67 mS. While utilities routinely supply 60 Hz in some countries and 50 Hz in other countries, an actual fundamental frequency may vary from 50 Hz or 60 Hz. In addition, some power sources may have a greater variation of the fundamental frequency. In some embodiments, the phase delay circuit122includes a frequency sensing circuit to detect an actual fundamental frequency at the 12-pulse motor drive. The phase delay circuit122uses the measured frequency to determine the 30-degree delay that is to ensure that the time delay equates to 30 degrees of the fundamental frequency of the AC voltage source104.

In addition to variations in fundamental frequency, voltage amplitude may vary between phases of the AC source104. The transformer106is typically not perfect and the phase shift between the secondary windings may not be exactly 30 degrees. Transients, unequal phase loading, etc. may also cause variation between phase voltages and may cause variations to the phase shift between secondary windings of the transformer106. The discrepancies in phase shift, phase imbalances, etc. may cause the 0-degree rectifiers108,110to produce pulses with an amplitude different than the 30-degree rectifiers112,114, which causes unequal loading, unequal wear, increased harmonics, etc. To remedy discrepancies between rectifiers108-114, an alpha trim circuit provides an adjustment to the 30-degree delay, which results in an ability to equalize pulses of the 0-degree rectifiers108,110compared to the 30-degree rectifiers112,114. The alpha trim circuit is described below. While the 12-pulse motor drive ofFIG. 1includes 0-degree rectifiers108,110and 30-degree rectifiers112,114, other motor drive topology may have more or less rectifiers.

FIG. 2is a schematic block diagram200of one embodiment of controls for a multi-pulse motor drive with an alpha trim adjustment. The depicted embodiment is for a 12-pulse motor drive. Other multi-pulse motor drives may also include an alpha trim adjustment. In the diagram200, the 0-degree rectifiers108,110and the 30-degree rectifiers112,114are displayed in a simplified diagram. On a 12-pulse motor drive, typically current is measured and sent to the regulator118. In the depicted embodiment, current transformers202measure current from two phases of the incoming power lines for the 0-degree rectifiers108,110and the 30-degree rectifiers112,114and are summed (not shown) and a signal is fed to a current to voltage converter204to derive a voltage signal for an alpha trim circuit206. In other embodiments, three current transformers202are used where a current transformer202is used for each phase.

In the embodiment, the gate drive circuit120driving switches F1-F6on the 0-degree rectifiers108,110also sends a signal to a phase delay circuit122that creates a phase delay that is a 30-degree delay for a gate signal for a switching cycle of a 12-pulse motor drive. The switching cycle is a period where switches F1-F6for the 30-degree rectifiers112,114are commanded closed. The alpha trim circuit206modifies the 30-degree delay with an alpha trim adjustment to create an adjusted 30-degree delay for the switching cycle. For example, the alpha trim adjustment adds delay to or subtracts delay from the 30-degree delay. In one example, the alpha trim circuit206adds or subtracts up to 10 degrees from the 30-degree delay. In some instances, the alpha trim circuit206adjusts the alpha trim adjustment in response to an amplitude difference between current from the 0-degree rectifiers108,110of the 12-pulse motor drive and current from the 30-degree rectifiers112,114of the 12-pulse motor drive.

The alpha trim circuit206uses the voltage signals proportional to current from the rectifiers108-114to determine an amount of alpha trim adjustment. In some embodiments, the alpha trim circuit206compares the two current signals and produces a positive or negative alpha trim adjustment based in response to the comparison being positive or negative. For other multi-pulse motor drives, signals from additional rectifiers may be compared to signals from the 0-degree rectifiers108,110or to another reference, such as an average current level. Beneficially, the alpha trim circuit206equalizes voltage/current pulses produced by the 0-degree rectifiers108,110and the 30-degree rectifiers112,114for equal power sharing between the rectifiers108-114.

In the embodiment depicted inFIG. 2, the 12-pulse motor drive includes a delay application circuit208that applies the adjusted 30-degree delay to the gate signal of the 30-degree rectifiers112,114. The 30-degree delay modified by the alpha trim adjustment may be called a modified 30-degree delay. The modified 30-degree delay is referenced from the firing angle. In some embodiments, the 12-pulse motor drive includes a phase delay circuit122for each drive switch of a 30-degree rectifier of the 12-pulse motor drive and the alpha trim circuit206modifies the 30-degree delay for each drive switch F1-F6.

FIG. 3is a schematic block diagram300of another embodiment of controls for a multi-pulse motor drive with an alpha trim adjustment. In the diagram300, the rectifiers108-114, current transformers202, current to voltage converters204, regulator118and gate drive circuit120are substantially similar to those described above.

In the embodiment depicted inFIG. 2, the phase delay circuit122includes a first delay circuit302and a second delay circuit304. In the embodiment, the first delay circuit302includes the 30-degree delay modified by a first alpha trim adjustment from the alpha trim circuit206and the second delay circuit304includes the 30-degree delay modified by a second alpha trim adjustment from the alpha trim circuit206. In the embodiment, the switching cycle is a first switching cycle and another switching cycle is different from the first switching cycle.

The delay application circuit208includes a setup switch306that changes between a first position that connects the first delay circuit302while disconnected from the second delay circuit304and a second position that connects the second delay circuit304while disconnected from the first delay circuit302. In the embodiment, the delay application circuit208also includes a setup switch controller308that changes the setup switch306between the first position and the second position during a non-switching period between switching cycles. The delay application circuit208may also include other elements for driving switches of the 30-degree rectifiers112,114.

Having a first delay circuit302and a second delay circuit304allows the second delay circuit304to be setup while the first delay circuit302is active and vise-versa. A gate drive signal from the gate drive circuit120triggers execution of a first modified 30-degree delay of the first delay circuit302, which is the 30-degree delay modified by the first alpha trim adjustment, when the setup switch306is in the first position. At the end of the first modified 30-degree delay, the drive switch connected to the first delay circuit302through the setup switch306in the first position turns, creating a first switching cycle, on based on a drive signal that propagates through the first delay circuit302. While the first delay circuit302is active, the alpha trim circuit206adjusts the 30-degree delay of the second delay circuit304. The setup switch controller308then changes the setup switch306from the first position to the second position during a non-switching period between switching cycles.

While the setup switch306is in the second position, the second delay circuit304is active and a gate drive signal from the gate drive circuit120triggers a second modified 30-degree delay, which is the 30-degree delay modified by the second alpha trim adjustment. At the end of the second modified 30-degree delay, the gate drive signal moves through the setup switch306in the second position and to a switch (e.g. F2) of the 30-degree rectifiers112,114creating a second switching period. While the setup switch is in the second position, the alpha trim circuit206adjusts the 30-degree delay of the first delay circuit302using the first alpha trim adjustment in anticipation of the setup switch306moving again to the first position.

Note that the first alpha trim adjustment and the second alpha trim adjustment may be the same or may be different as the alpha trim circuit206may change an amount of alpha trim adjustment while one of the delay circuits302,304is active. Also note that, in some embodiments, when the first delay circuit302is active the alpha trim circuit206does not adjust the first alpha trim adjustment and when the second delay circuit304is active the alpha trim circuit206does not adjust the second alpha trim adjustment.

In some embodiments, the multi-pulse motor drive includes a lockout circuit310that tracks switching cycles and locks out changing between forward rectifiers108,112and reverse rectifiers110,114for a period of time to avoid triggering switches F1-F6of the rectifiers108,112and reverse rectifiers110,114at the same time. In some embodiments, the lockout circuit310includes edge detection circuitry for detecting when a switching cycle is starting and/or ending, which may be used by the setup switch controller308to determine a period of non-switching for changing the setup switch306between the first position and second position. In other embodiments, the setup switch controller308includes circuits independent of any lockout circuit310for determining a non-switching period.

In some embodiments, the 12-pulse motor drive includes a 30-degree delay calculation circuit312that uses a measurement of actual line frequency of power feeding the 12-pulse motor drive to calculate an amount of delay for the 30-degree delay. The 30-degree delay may then be fed into the first delay circuit302and second delay circuit304. In some embodiments, the 30-degree delay calculation circuit312adjusts the 30-degree delay in response to a change in line frequency. In other embodiments, 30-degree delay calculation circuit312adjusts the 30-degree delay in the first delay circuit302when not active and in the second delay circuit304when not active.

FIG. 4is a schematic block diagram400of a more detailed embodiment of controls for a multi-pulse motor drive with an alpha trim adjustment. In the diagram400, the rectifiers108-114, current transformers202, current to voltage converters204, regulator118and gate drive circuit120are substantially similar to those described above. In addition, the diagram400also depicts a bridge rectifier402for the 0-degree rectifiers108,110and the 30-degree rectifiers112,114, which averages the current signals from the current transformers202. The bridge rectifiers402, in one embodiment, are full bridge rectifiers that convert the current signals to a DC signal that represents current. The current to voltage converters204then send the current signals on to the regulator118but also create a signal where +/−1 ampere (“A”) is represented by +/−10 volts (“V”) for the alpha trim circuit206. In other embodiments, the current to voltage converters204also send a +/−10 V signal to the regulator118. In other embodiments, other circuit designs are used to derive a signal representative of current in the rectifiers108-114.

In the diagram400, the gate drive circuit120to drive the switches F1-F6of the 0-degree rectifiers108,110is represented by first gate amplifier404, which includes a gate input, forward input (“FWD in”), reverse input (“REV in”), forward output (“FWD”), reverse output (“REV”) and alpha trim. A similar second gate amplifier406to drive the switches F1-F6of the 30-degree rectifiers112,114includes the same inputs, outputs and alpha trim. The gate input receives a gate drive signal from the regulator118, which includes a firing angle and the gate drive signal has a 0-degree reference that is correlated to the firing angle. The first gate amplifier404outputs two forward output signals. One forward output signal drives a switch (e.g. F1) in the forward 0-degree rectifier108and one forward output signal is sent to the forward input of the second gate amplifier406as a forward input signal420. Likewise, the first gate amplifier404outputs two reverse output signals. One reverse output signal drives a switch (e.g. F1) in the reverse 0-degree rectifier110and one reverse output signal is sent to the reverse input of the second gate amplifier406as a reverse input signal422. The alpha trim is not used for the first gate amplifier404.

The alpha trim circuit206depicted inFIGS. 2 and 3is represented by the ControlLogix® circuit408and the alpha trim418inFIG. 4. The ControlLogix circuit408is a control device made by Allen-Bradley®, but other embodiments include a different device. The ControlLogix circuit408includes two analog-to-digital converters410,412that convert the signals from the current to voltage converters204of the 0-degree rectifiers108,110and the 30-degree rectifiers112,114to digital signals, which are fed to a comparator414, which feeds an alpha pulse circuit416. The alpha pulse circuit416has an increase output (“INC”) and a decrease output (“DEC”) connected to the alpha trim418of the second gate amplifier406.

When the signal from the 30-degree rectifiers112,114compared to the signal from the 0-degree rectifiers108,110calls for an increase in the alpha trim adjustment, the alpha pulse circuit416sends out pulses on the increase alpha trim line424at a prescribed rate. In one embodiment, the ControLogix circuit408includes an alpha pulse rate limiter (not shown) that controls the alpha pulse circuit to limit a rate of increase and decrease of the alpha trim adjustment. Each pulse, in some embodiments, increases the alpha trim adjustment by a certain amount. For example, each pulse from the increase alpha trim line424may increase the alpha trim adjustment by 0.1 degrees.

Other embodiments include a different increment for the increase alpha trim line424. Likewise, when the signal from the 30-degree rectifiers112,114compared to the signal from the 0-degree rectifiers108,110calls for a decrease in the alpha trim adjustment, the alpha pulse circuit416sends out pulses on the decrease alpha trim line426at a prescribed rate dictated by the alpha pulse rate limiter. Other embodiments include an analog comparator feeding the alpha trim418, which includes analog-to-digital circuits and/or other circuits to change the alpha trim adjustment.

Each pulse, in some embodiments, decreases the alpha trim adjustment by a certain amount. For example, each pulse from the decrease alpha trim line426may decrease the alpha trim adjustment by 0.1 degrees. Other embodiments include a different increment for the increase alpha trim line424and the decrease alpha trim line426. In addition, the alpha pulse rate limiter controls the rate of pulses on the increase alpha trim line424and the decrease alpha trim line426, depending on a desired rate of increase/decrease for the alpha trim adjustment.

The second gate amplifier406adjusts the forward input signal420and the reverse input signal422, which result in a modified forward output and a modified reverse output from the second gate amplifier406to the 30-degree rectifiers112,114. The 30-degree delay, in some embodiments, is calculated in the second gate amplifier406, which receives a line frequency signal (not shown) to calculate the 30-degree delay. The alpha trim adjustment modifies the 30-degree delay and a modified 30-degree delay is added to the forward input signal420and the reverse input signal422. Where the phase delay differs from 30 degrees, for example, 15 degrees, 20 degrees, 40 degrees, 45 degrees, etc., the second gate amplifier406includes a switch, a dial, or other mechanism to set the base phase delay and the second gate amplifier406calculates the phase delay based on the setting for the phase delay.

FIG. 5is a schematic block diagram500of an embodiment of a portion of controls for a multi-pulse motor drive with an alpha trim adjustment. The ControlLogix circuit408ofFIG. 4is depicted along with internal components of the alpha trim418of the second gate amplifier406ofFIG. 4. The forward input signal420and the reverse input signal422are fed to a lockout circuit502, which includes a forward crossover circuit504and a reverse crossover circuit506. The lockout circuit502, in one embodiment, produces a lockout signal508that prevents gate drive signals being sent to the 0-degree rectifiers108,110and to the 30-degree rectifiers112,114as depicted inFIG. 5, or for other rectifiers for multi-pulse motor drives with a different number of pulses. In some embodiments, the forward crossover circuit504includes circuitry to detect a start and/or a finish of a series of gate drive signal pulses making up a switching period, which are used by the setup switches510,512to determine a non-switching period. Other embodiments include other circuits different than from the lockout circuit502to determine a non-switching period.

The forward input signal420, in some embodiments, are 6 forward signals for switches F1-F6of the forward 30-degree rectifier112. The forward input signals420, depicted as a single line, are fed to a delay514, which is a small delay intended to allow the forward crossover circuit504to operate. In other embodiments, other means are used to allow the forward crossover circuit504to operate. The delay514is depicted as one device but may be multiple devices with one device per drive signal. The output of the delay514is fed to AND gates516, which are combined with the lockout signal508to control lockout of the forward 30-degree rectifier112. Likewise, the reverse input signal422, in some embodiments, are 6 reverse signals for switches F1-F6of the reverse 30-degree rectifier114. The reverse input signals422, depicted as a single line, are fed to a delay518, which is a small delay intended to allow the reverse crossover circuit506to operate. In other embodiments, other means are used to allow the reverse crossover circuit506to operate. The delay518is depicted as one device but may be multiple devices with one device per drive signal. The output of the delay518is fed to AND gates520, which are combined with the lockout signal508to control lockout of the reverse 30-degree rectifier114.

In the depicted embodiment ofFIG. 5, there is a forward first delay circuit522and a forward second delay circuit524for the forward delay lines526that delay a gate drive signal to the forward 30-degree rectifier112. There is also a reverse first delay circuit528and a reverse second delay circuit530for the reverse delay lines532that delay a gate drive signal to the reverse 30-degree rectifier114. The forward first delay circuit522and the reverse first delay circuit528are one embodiment of the first delay circuit302of the diagram300ofFIG. 3and the forward second delay circuit524and the reverse second delay circuit530are one embodiment of the second delay circuit304of the diagram300ofFIG. 3.

In the depicted embodiment, the first delay circuits522,528and the second delay circuits524,530each include a plurality of clock-driven delay components arrangeable in series. Each delay component provides a fixed amount of delay relative to a period of a clock signal and a number of delay components connected in series provides a delay of the period of the clock signal multiplied by the number of delay components connected in series. For example, the delay components may be D flip-flops. In another embodiment, the delay element includes NAND gates arranged to output what is on an input line after a clock signal. One of skill in the art will recognize other ways to construct a memory element where an input signal is clocked to an output after application of a clock signal. For example, an adjustable counter may function to provide a delay.

The ControlLogix circuit408is connected to a pulse counter534, which may be an up/down counter, maintains a current alpha trim adjustment and increases the current alpha trim adjustment in response to a digital pulse on the increase alpha trim line424and decreases the current alpha trim adjustment in response to a digital pulse on the decrease alpha trim line426. An output of the pulse counter534, in some embodiments, is connected to an input of an alpha trim calculation circuit536that calculates a number of delay elements corresponding to a current alpha trim adjustment, which may vary based on a current line frequency and a clock period. The alpha trim calculation circuit536adjusts the number of required delay elements based on a line frequency measurement and a period of the clock. The alpha trim calculation circuit536is depicted feeding an alpha trim537, which feeds an alpha trim adjustment to the forward delay lines526and reverse delay lines532. The alpha trim537is depicted for convenience, but one of skill in the art understands that the alpha trim calculation circuit536may feed the forward delay lines526and reverse delay lines532directly.

A frequency adjustment circuit538receives a measurement of a current line frequency and determines a number of delay elements for the 30-degree delay and feeds the number of delay elements for the 30-degree delay to a frequency adjustment540feeding the forward delay lines526and reverse delay lines532. The frequency adjustment540is depicted for convenience and one of skill in the art will recognize that other embodiments may include a frequency adjustment circuit538that feeds the number of delay elements for the 30-degree delay directly to forward delay lines526and reverse delay lines532. A clock542also feeds the forward delay lines526and reverse delay lines532as well as the alpha trim calculation circuit536.

A drive delay circuit544is included in some embodiments and feeds the forward delay lines526and reverse delay lines532and sets an amount of delay based on topology of the motor drive. In some embodiments, the drive delay circuit544includes a mode switch that sets an amount of phase delay. Where the motor drive is a 12-pulse motor drive, the drive delay circuit544sets the delay to 30 degrees. Other motor drives may require a different delay. For example, a 24-pulse motor drive may require a 15-degree delay, 30-degree delay and a 45-degree delay, an 18-pulse motor drive may require a 20-degree delay and a 40-degree delay, etc. where a gate amplifier404,406is used for each rectifier section. For the embodiments described herein, the drive delay circuit544is set to 30 degrees.

In one embodiment, the line frequency is 60 Hz, which has a period of 16.667 mS, which represents 360 degrees, or 46.296 microseconds (“μS”) per degree. If the alpha trim adjustment can be +/−10 degrees added to a 30-degree delay, the range of the alpha trim adjustment plus the 30-degree delay is 40 degrees to 20 degrees. A range of delays would be the 30-degree delay would be 1.3889 mS+/−462.96 μS. A longest delay would be 1.3889 mS+462.96 μS=1.8519 mS. If the clock is a 4 mega Hertz (“MHz”) clock, the period is 0.25 μS so that 1.8519 mS/0.25 μS=7407 delay elements. Where there are 12 active lines (6 forward, 6 reverse) in the forward first delay circuits522and reverse first delay circuits528and 12 setup lines (6 forward, 6, reverse) in the forward second delay circuits524and reverse second delay circuits530, there are24total delay circuits522,524,528,530, so at 60 Hz with a 4 MHz clock and at an alpha trim of +10 degrees, a total of 177,778 delay elements would be required. This results in 185.19 counts per degree of resolution.

A worst case scenario, in terms of largest number of delay elements, could be calculated from the minimum acceptable frequency and highest alpha trim adjustment. For example, where a power source fundamental frequency is 50 Hz+/−10 Hz, a minimum frequency is 40 Hz, with a period of 25 mS, or 69.444 μS per degree. For a 45-degree delay and an alpha trim adjustment of +/−10 degrees, a +10 degree alpha trim adjustment would result in a delay of 55 degrees, or 3.819 mS. Again, using a 4 MHz clock, this results in 15,278 delay elements for 24 lines or 366,667 delay elements. This results in 277.78 counts per degree of resolution. Thus, where an alpha trim418of a second gate amplifier406has an FPGA or similar device with a particular number of delay device, the extremes of possible line frequencies, a clock rate, and a desired per degree minimum resolution can be used to select an FPGA and clock frequency to meet desired requirements.

While the delay circuits522,524,528,530are depicted with discrete delay elements, other logic, circuits, etc. may be used to create a 30-degree delay adjusted by an alpha trim adjustment. One of skill in the art will recognize other ways to create a gate drive signal delay based on a 30-degree delay and an alpha trim adjustment.