Method of manufacturing a semiconductor device having an even coating thickness using electro-less plating, and related device

A method of manufacturing a semiconductor device includes forming a diffusion barrier layer on a substrate, and forming at least two features on the substrate such that the diffusion barrier layer is respectively disposed between each feature and the substrate and contacts the at least two features. A first impurity region of the substrate contains impurities of a first type, a second impurity region of the substrate contains impurities of a second type, different from the first type, a first feature of the at least two features is in the first impurity region, and a second feature of the at least two features is in the second impurity region, such that the second feature is electrically isolated from first feature by the different impurity regions.

BACKGROUND OF THE INVENTION

1. Field of the Invention

Embodiments relate to a method of manufacturing a semiconductor device and, more particularly, to a method of manufacturing a semiconductor device having an even coating thickness using electro-less plating, and a device made thereby.

2. Description of the Related Art

Generally, electroplating and electro-less plating may be used to deposit a material layer, e.g., a conductive layer, on a substrate. Electroplating typically involves exposing a target substrate to a metal-containing solution, in which metal ions are dissolved in acid, and driving a reduction reaction using an applied electric potential so as to convert the metal ions to a metal layer on the substrate. For example, the substrate may be immersed in the metal-containing solution while being connected as a cathode of the electrical circuit. The cathode may be connected to a first pole of a power source, and an anode connected to an opposite pole of the power source may be immersed in the solution to complete an electrical circuit.

Unlike conventional electroplating, electro-less plating does not depend on the application of an external electrical potential to drive the plating process. Electro-less plating may be a desirable alternative to electroplating, because the relatively simple electro-less plating process may require less equipment and lower costs as compared to electroplating. Further, electro-less plating may be employed to form a metal layer on sidewalls and a top portion of a bump, whereas electroplating may form a metal layer only on the top portion of the bump.

It is commonly understood that even non-conductive substrates may be plated using electro-less plating, i.e., conductivity of the substrate is not required. However, where finely-patterned features are to be plated using electro-less plating, a difference in electrical potential between similar features formed on the substrate may result in those features being unevenly plated. Thus, in the fabrication of a semiconductor device having finely-patterned features such as, e.g., bumps, wiring patterns, etc., variations in plating thickness may occur when using an electro-less plating process, and the variations in plating thickness may reduce the reliability of the semiconductor device.

SUMMARY OF THE INVENTION

Embodiments are therefore directed to a method of manufacturing a semiconductor device having an even coating thickness using electro-less plating, and a related device, which substantially overcome one or more of the problems due to the limitations and disadvantages of the related art.

Embodiments therefore provide a method of electro-less plating suitable for plating features that are located in regions of a substrate that contain impurities of differing types.

Embodiments also provide a device including features having an outer conductive layer, the features being located in regions of a substrate that contain impurities of differing types.

At least one of the above and other advantages may be realized by providing a method of manufacturing a semiconductor device, including forming a diffusion barrier layer on a substrate, and forming at least two features on the substrate such that the diffusion barrier layer is respectively disposed between each feature and the substrate and contacts the at least two features. A first impurity region of the substrate may contain impurities of a first type, a second impurity region of the substrate may contain impurities of a second type, different from the first type, a first feature of the at least two features may be in the first impurity region, and a second feature of the at least two features may be in the second impurity region, such that the second feature is electrically isolated from first feature by the different impurity regions.

The diffusion barrier layer may provide an electrical path between the at least two features, and the method may further include electro-less plating an outer conductive layer on the at least two features while the at least two features are connected by the electrical path, and, after the electro-less plating, processing the diffusion barrier layer so as to interrupt the electrical path. Processing the diffusion barrier layer so as to interrupt the electrical path may include removing the diffusion barrier layer from a region surrounding at least one of the at least two features. After interrupting the electrical path, the diffusion barrier layer may extend laterally to an outer edge of the conductive layer and is exposed by the conductive layer.

The conductive layer may be plated on a surface of the features that includes one or more of copper or nickel, the conductive layer may include one or more of nickel, gold, palladium, tin, or indium, and the diffusion barrier layer may include one or more of titanium, chromium, or aluminum. The conductive layer may include a palladium layer on the surface of each feature, a nickel layer on each palladium layer, and at least one gold layer on each palladium layer.

The method may further include, after forming the diffusion barrier layer and before the electro-less plating, forming a seed layer on the substrate, selectively forming the at least two features on the seed layer, and selectively removing the seed layer from a region between the at least two features. The at least two features may be formed by electroplating or electro-less plating. Forming the at least two features may include forming a seed layer on the substrate, forming a photoresist pattern on the substrate, the photoresist pattern having openings corresponding to the at least two features, the openings exposing the seed layer, depositing a material in the openings in the photoresist pattern using electroplating, planarizing the deposited material to form the at least two features, removing the photoresist pattern, and removing portions of the seed layer exposed on the substrate adjacent to the at least two features. The seed layer may be conductive.

A portion of the diffusion barrier layer that provides the electrical path may be exposed during the electro-less plating. The method may further include, before the electro-less plating, subjecting the exposed portion of the diffusion barrier layer that provides the electrical path to an oxygen plasma surface treatment.

At least one of the above and other advantages may also be realized by providing a semiconductor device, including a substrate, at least two features on the substrate, each including an outer conductive layer, and a diffusion barrier layer respectively disposed between each feature and the substrate, wherein a first impurity region of the substrate contains impurities of a first type, a second impurity region of the substrate contains impurities of a second type, different from the first type, a first feature of the at least two features is in the first impurity region, a second feature of the at least two features is in the second impurity region, such that the second feature is electrically isolated from first feature by the different impurity regions, and each respective diffusion barrier layer may extend laterally to an outer edge of the corresponding conductive layer and may be exposed by the corresponding conductive layer.

The conductive layer may contact a top surface of the diffusion barrier layer. Each feature may include a core material having a different composition from the conductive layer. The core material may include one or more of copper or nickel. The conductive layer may include one or more of nickel, gold, palladium, tin, or indium. The diffusion barrier layer may include one or more of titanium, chromium, or aluminum. The diffusion barrier layer may include one or more of a titanium-nitrogen compound or a titanium-tungsten compound.

The at least two features may be bumps that are configured to provide electrical signals between the semiconductor device and a second substrate. The at least two features may be wiring lines.

At least one of the above and other advantages may also be realized by providing a display device, including a display and a display driver integrated circuit coupled to the display, wherein the display is configured to reproduce an image in response to signals provided by the display driver integrated circuit, and the display driver integrated circuit includes a substrate, at least two features on the substrate, each including an outer conductive layer, and a diffusion barrier layer respectively disposed between each feature and the substrate, wherein a first impurity region of the substrate contains impurities of a first type, a second impurity region of the substrate contains impurities of a second type, different from the first type, a first feature of the at least two features is in the first impurity region, a second feature of the at least two features is in the second impurity region, such that the second feature is electrically isolated from first feature by the different impurity regions, and each respective diffusion barrier layer may extend laterally to an outer edge of the corresponding conductive layer and may be exposed by the corresponding conductive layer.

At least one of the above and other advantages may also be realized by providing a method of manufacturing a semiconductor device, including forming a diffusion barrier layer on a substrate, forming at least two features on the substrate such that the diffusion barrier layer is respectively disposed between each feature and the substrate, the diffusion barrier layer electrically connecting the at least two features, electro-less plating an outer conductive layer on the at least two features while the at least two features are electrically connected by the diffusion barrier layer, and selectively removing the diffusion barrier layer so as to interrupt the electrical connection.

At least one of the above and other advantages may also be realized by providing a semiconductor device, including a substrate, a first feature and a second feature on the substrate, a first diffusion barrier between the substrate and the first feature, a first conductive layer on the first feature, a second diffusion barrier between the substrate and the second feature, and a second conductive layer on the second feature, wherein the first conductive layer contacts a top surface of the first diffusion barrier, and the second conductive layer contacts a top surface of the second diffusion barrier.

DETAILED DESCRIPTION OF THE INVENTION

Korean Patent Application No. 10-2007-0038981, filed on Apr. 20, 2007, in the Korean Intellectual Property Office, and entitled: “Method for a semiconductor device manufacturing having an even coating thickness in electro-less plating,” is incorporated by reference herein in its entirety.

Embodiments will now be described more fully hereinafter with reference to the accompanying drawings; however, they should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

In the figures, the dimensions of layers and regions may be exaggerated for clarity of illustration. It will also be understood that when a layer or element is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Further, it will be understood that when a layer is referred to as being “under” another layer, it can be directly under, and one or more intervening layers may also be present. In addition, it will also be understood that when a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. Where an element is described as being connected to a second element, the element may be directly connected to second element, or may be indirectly connected to second element via one or more other elements. Further, where an element is described as being connected to a second element, it will be understood that the elements may be electrically connected, e.g., in the case of transistors, capacitors, power supplies, nodes, etc. In the figures, the dimensions of regions may be exaggerated and elements may be omitted for clarity of illustration. Like reference numerals refer to like elements throughout.

FIG. 1illustrates a schematic of an electro-less plating operation. Referring toFIG. 1, a semiconductor device100being manufactured may include a substrate102, e.g., a semiconductor substrate, having features116, e.g., bumps116A and116B. The features116may be conductors that are provided for passing signals, e.g., control signals, data, power, ground, etc. into and out of the semiconductor device100. The features116may be, e.g., bumps on a device bonding pad. In an implementation the features116may be, e.g., a signal terminal bump116A and a ground bump116B.

The semiconductor device100may also include device bonding pads106respectively corresponding to the bumps116A,116B. A well region124, e.g., a doped impurity region, may isolate the bumps116A from the substrate102. In an implementation, the substrate102may be doped with an n-type impurity and the well region124may be doped with a p-type impurity.

The semiconductor device100may also include a diffusion barrier layer108disposed between the bumps116A and the bumps116B. The diffusion barrier layer108may electrically connect one or more bumps116A to one or more bumps116B.

The diffusion barrier layer108may serve to normalize a voltage potential between a bump116A, which is isolated by the well region124, and a bump116B, which is not isolated by the well region124. The diffusion barrier layer108may reduce or eliminate a voltage potential between the bumps116A and116B during electro-less plating. For example, where the bump116A is a signal bump and the bump116B is a ground bump, the voltage potential may be normalized by allowing electrons to move from the ground bump116B toward the signal bump116A through the diffusion barrier layer108.

In view of the electron flow through the diffusion barrier layer108, each of the bumps116A and116B may have an equal or substantially equal supply of electrons, which may enable an electro-less plating reaction to occur equally at the surface of each of the bumps116A and116B, such that equal amounts of material, e.g., metal, are deposited on each of the bumps116A and116B. Accordingly, the electro-less plating process may yield a plated layer having a substantially uniform thickness with respect to the bumps116A and116B, which may improve the reliability of the semiconductor device100as compared to an electro-less plating process performed when a voltage potential between the bumps116A and116B is not normalized.

More particularly, in the absence of an electrical connection connecting the bump116A to the bump116B, the bump116A may not be at a same electrical potential as the bump116B. In particular, the well region124may isolate the bump116A from the substrate102, such that a flow of electrons between the substrate and the bump116A is different from a flow of electrons between the substrate102and the bump116B. This may result in variations in electro-less plating conditions between the bump116A and the bump116B. For example, electro-less plating may be less effective for the bump116A than for the bump116B, which is not isolated from the substrate.

FIGS. 2A-2Iillustrate stages in a method of manufacturing a semiconductor device according to a first embodiment, including stages before and after the electro-less plating stage illustrated inFIG. 1. In the description that follows, the fabrication of only one bump of the bumps116A and116B will be described. However, it will be appreciated that fabrication of the other of the bumps116A and116B may proceed in similar fashion. Accordingly, details of the fabrication of the other of the bumps116A and116B will not be repeated.

Referring toFIG. 2A, the substrate102may have the device bonding pad106thereon. The bonding pad106may be in region of the substrate102that is isolated by an impurity well such as the well124described above, or may be in a region of the substrate102that is not isolated. As shown inFIG. 2A, a passivation layer104may be formed on the substrate102. The passivation layer104may partially cover the bonding pad106.

Referring toFIG. 2B, the diffusion barrier layer108may be formed on the passivation layer104. The diffusion barrier layer108may include one or more of titanium, chromium, or aluminum. In an implementation, the diffusion barrier layer108may include one or more of a titanium-nitrogen compound or a titanium-tungsten compound. The diffusion barrier layer108may have a thickness of about 3000 Å. A seed layer110may be formed on the diffusion barrier layer108. The seed layer110may include copper and may have a thickness of about 2000 Å. The seed layer110may act as a seed metal layer for forming a feature116, e.g., a bump, on the bonding pad106in a subsequent operation. For example, the seed layer110may include Ni or a Ni—Cu alloy, and the feature116to be formed later may also include Ni or a Ni—Cu alloy, respectively. In an implementation (not shown), in a case where a titanium layer is used as the diffusion barrier layer108, the seed layer110may include a titanium nitride layer and a copper layer on top of the titanium nitride layer.

Referring toFIG. 2C, a photoresist layer114may be formed on the substrate and patterned to define a region in which the feature116is to be formed. The photoresist layer114may be applied and patterned using well-known techniques, the details of which will not be repeated here. The patterned photoresist layer114may expose an area overlying the bonding pad106.

Referring toFIG. 2D, the feature116may be formed in the area defined by the patterned photoresist layer114. The feature116may be formed using, e.g., electroplating or electro-less plating. The feature116may be nickel, copper, a copper-nickel alloy, etc. The feature116may be formed to a height less than that of the photoresist layer114, or may be formed to a height greater than that of the photoresist layer114(not shown). In either case, a planarization process may be performed to planarize the upper surface of the feature116, as shown inFIG. 2E. Subsequently, the photoresist layer114may be removed, as shown inFIG. 2F.

Referring toFIG. 2G, portions of the seed layer110that are exposed after removing the photoresist layer114may be removed to expose the underlying diffusion barrier layer108, e.g., using an etch process. The etch process may selectively remove the seed layer110with respect to the diffusion barrier layer108, such that the diffusion barrier layer108remains. Selectively removing the seed layer110may leave a portion110aof the seed layer between the diffusion barrier layer108and the overlying feature116.

In another implementation, as described above, the seed layer110may include a titanium layer, and the diffusion barrier layer108may include a titanium nitride layer and a copper layer on top of the titanium nitride layer. In this case, the copper top layer may be removed to expose the titanium nitride layer, and electro-less plating (described below) may be performed in this configuration. However, if electro-less plating deposits material on the titanium nitride layer, the titanium nitride layer may also be removed, and electro-less plating may be performed with the titanium layer exposed.

The diffusion barrier layer108may electrically connect the feature116to an adjacent feature116. For example, referring again toFIG. 1, the diffusion barrier layer108may electrically connect the bump116A that is disposed in the well124region of the substrate102to the bump116B that is disposed outside the well124region.

In an implementation, the exposed region of the diffusion barrier layer108may be subjected to a surface treatment in order to reduce or eliminate the deposition of material thereon during a subsequent electro-less plating operation. For example, the exposed region of the diffusion barrier layer108may be subjected to an oxygen plasma treatment, e.g., for a duration of about 60 seconds, which may impart insulating characteristics to the exposed surface. The oxygen plasma treatment may increase the sheet resistance of the surface of the diffusion barrier layer108by about 0.5% to about 5%. Table 1 below shows effects of example oxygen plasma de-scum treatments on sheet resistivity of a 3,000 Å thick titanium diffusion barrier layer:

Referring toFIG. 2H, a conductive layer122may be formed on the surface of the feature116. The conductive layer122may be formed using electro-less plating. The electro-less plating may uniformly form the conductive layer122on the feature116as well as on one or more features116that are electrically interconnected by the diffusion barrier layer108. Thus, in the case of, e.g., the bumps116A and116B shown inFIG. 1, the electro-less plating may form the conductive layer122to a substantially uniform thickness on the bump116A that is disposed in a well124region of the substrate102, as well as on the bump116B that is disposed outside the well124region.

The conductive layer122may include one or more layers of differing materials, or may be a single layer. For example, the conductive layer122may include a double layer of nickel and gold, a single layer or multiple layers of gold, multiple layers including nickel, multiple layers including palladium, a single or multiple layers including tin, tin alloys, indium, etc. In an implementation, the conductive layer122may include a nickel layer118and a gold layer120formed on the nickel layer118. In another implementation, the conductive layer122may include a palladium layer126, a nickel layer118, a first gold layer120B and a second gold layer120A, as shown inFIG. 2I.

For example, the conductive layer122may include the palladium layer126as the bottommost activation layer, the nickel layer118, having a thickness of, e.g., about 0.4 μm, the first gold layer120B, having a thickness of, e.g., about 0.1 μm, formed by a substitution reaction process, and the second gold layer120A, having a thickness of, e.g., about 0.3 μm to about 0.4 μm, formed by a reduction reaction process. In detail, a precleaning operation may be performed, after which the palladium layer126may be formed using, e.g., a catalyst treatment. Subsequently, a nickel layer118, which may serve as a diffusion barrier layer, may be formed using, e.g., NiP plating at a temperature of about 75° C. to about 90° C. The first and second gold layers120B and120A may be formed using a gold substitution reaction and a gold reduction reaction at a temperature of about 65° C. to about 85° C., respectively. After each operation, a cleaning may be performed using deionized water. Where a tin layer is included in the conductive layer122, the tin may be deposited using electro-less plating at about 60° C. after a precleaning operation that includes cleaning with deionized water followed by soft etching using potassium persulfate, K2S2O8. The hardness of the feature116may be adjusted using a heat treatment operation, e.g., heating to a temperature of about 250° C.

After forming the conductive layer122, exposed portions of the diffusion barrier layer108may be removed, leaving a portion108aof the barrier layer between the passivation layer104and the overlying portion110aof the seed layer. Since the exposed portions of diffusion barrier layer108are removed after the conductive layer122is formed, the conductive layer122may cover the feature116and may extend along sides of the feature116to contact a top surface of the diffusion barrier layer108, as shown inFIG. 2I. In an implementation, the conductive layer122may directly contact the diffusion barrier layer108, and may directly contact the remaining portion108aof the diffusion barrier layer after the selective removal of the exposed portions. The selective removal of the exposed portions of the diffusion barrier layer108may leave the remaining portion108ahaving a lateral extent that is substantially aligned with the outer periphery of the conductive layer122. The portion110aof the seed layer may be completely encapsulated by the surrounding conductive layer122, the overlying feature116, and the underlying portion108aof the diffusion barrier layer. Removing the exposed portions of the diffusion barrier layer108may interrupt the electrical path between the features116. Thus, the diffusion barrier layer108may act as a diffusion barrier as well as provide the electrical path during electro-less plating, and the remaining portion108amay remain after the electrical path is interrupted, so as to serve as a diffusion barrier in resultant device.

A second embodiment will now be described in connection withFIGS. 3A,3B, and4A-4G. In this embodiment, the feature116described above may be implemented as a wiring pattern, e.g., a redistribution pattern210, on a semiconductor device200.FIG. 3Aillustrates a plan view of an example semiconductor device according to the second embodiment.FIG. 3Billustrates a sectional view of the semiconductor device ofFIG. 3A, taken along a line A-A ofFIG. 3A. Referring toFIG. 3A, the redistribution pattern210may redistribute bonding regions such that, for example, peripheral bonding pads206are connected to respective redistributed bonding pads212, which may be formed in an interior region of the semiconductor device200.

Referring toFIG. 3B, the bonding pad206may be disposed on a substrate202. A passivation layer204may be disposed on the substrate202and may partially cover the bonding pad206. A first dielectric layer208may be disposed on the substrate202so as to cover the passivation layer204and expose a region overlying the bonding pad206. The redistribution pattern210may be disposed in contact with the bonding pad206in the region exposed by the passivation layer204, and may extend along a surface of the the first dielectric layer208towards the region where the redistributed bonding pad212is located. A second dielectric layer228may cover the first dielectric layer208and the redistribution pattern210, and may have an opening exposing a region of the redistribution pattern210to form the redistributed bonding pad212. A solder ball214, a bump, etc., may be disposed on the redistributed bonding pad212and may provide electrical contact with an adjacent substrate such as a printed circuit board, etc., (not shown).

The redistribution pattern210may be formed in similar fashion to the features116described above. In particular, an electro-less plating operation may be performed while multiple redistribution patterns210are electrically connected by a diffusion barrier216, which is described in detail below. The electrical connection provided by the diffusion barrier216may allow the electrical potential of redistribution patterns210connected thereby to be normalized, which may improve the uniformity of a conductive layer formed on the redistribution patterns210.

FIGS. 4A-4Gillustrate cross-sectional views of stages in a method of manufacturing the semiconductor device200described above in connection withFIG. 3A, taken along a line B-B ofFIG. 3A. Referring toFIG. 4A, the passivation layer204may be formed on the substrate202. The passivation layer204may be patterned to expose a portion of the bonding pad206(seeFIGS. 3A and 3B). The first dielectric layer208may be formed on the substrate202and may cover the passivation layer204. The first dielectric layer208may be patterned to expose the bonding pad206.

The diffusion barrier layer216may be formed on the first dielectric layer208and on the exposed portion of the bonding pad206, and a seed layer218may be formed on the diffusion barrier layer216. In an implementation, the diffusion barrier layer216may include Ti, Cr, Al, TiN, and/or TiW, and the seed layer218may include Cu, Ni, and/or Cu—Ni alloy. In another implementation, the diffusion barrier216and the seed layer218may include a three-layer structure of Ti/TiN/Cu.

Referring toFIG. 4B, a photoresist layer222may be formed on the seed layer218. The photoresist layer222may be patterned to form an opening that exposes a portion of the seed layer218that overlies the bonding pad206, and which defines a channel in which the redistribution pattern210is to be formed.

Referring toFIG. 4C, forming the redistribution pattern210(seeFIGS. 3A and 3B) may include electroplating or electro-less plating a material in the opening in the photoresist layer222to form a core pattern224for the redistribution pattern210. The core pattern224may include, e.g., Cu, Ni, or Cu—Ni alloy, and may be formed by electroplating or electro-less plating. In an implementation, copper may be plated in the opening to a thickness of, e.g., about 3 μm to about 5 μm. The thickness of the plated material may be greater or smaller than that of the photoresist layer222, and the plated material and photoresist layer222may be planarized in the same manner as described above in connection withFIG. 2E. The remaining photoresist layer222may then be removed, as shown inFIG. 4D.

Referring toFIG. 4E, portions of the seed layer218that are exposed as a result of the removal of the photoresist layer222may be selectively removed from around the core pattern224, e.g., using an etch process, such that the core pattern224and the remaining portion218aof the seed layer are substantially coextensive. As described above in connection with the first embodiment, the removal of the seed layer218may be selective with respect to the underlying diffusion barrier layer216, such that the diffusion barrier layer216remains and provides an electrical path between multiple core patterns224at this stage in the exemplary redistribution pattern forming process. Accordingly, a subsequent operation of electro-less plating an outer layer on the core patterns224may be performed while the core patterns224are electrically connected. Thus, the electro-less plating may be used to produce redistribution patterns210that have an outer layer plated thereon that has a substantially uniform thickness.

In an implementation, the surface of the diffusion barrier layer216may be subjected to an oxygen plasma treatment before performing electro-less plating, which may increase the sheet resistance of the diffusion barrier layer216by, e.g., about 0.5% to about 5%.

Referring toFIG. 4F, an outer conductive layer226may be plated on the core pattern224using electro-less plating. The outer conductive layer226may have a thickness of, e.g., about 1 μm to about 3 μm. As illustrated inFIG. 4F, the outer conductive layer226may cover the top and sides of the core pattern224, such that the core pattern224is not exposed in the redistribution pattern210. This may be particularly advantageous in the case of, e.g., a copper core pattern224, since the outer conductive layer226may prevent oxidation of the core pattern224and may prevent the copper from diffusing into adjacent material layers.

The conductive layer226may include one or more layers of differing materials, or may be a single layer. For example, the conductive layer226may include a double layer of nickel and gold, a single layer or multiple layers of gold, multiple layers including nickel, multiple layers including palladium, a single or multiple layers including tin, tin alloys, indium, etc. In an implementation, the conductive layer226may include a nickel layer and a gold layer formed on the nickel layer. In another implementation, the conductive layer226may include a palladium layer, a nickel layer, a first gold layer and a second gold layer, in a similar configuration to that described above in connection withFIG. 2I.

For example, the conductive layer226may include the palladium layer as the bottommost activation layer, the nickel layer having a thickness of, e.g., about 0.4 μm, the first gold layer having a thickness of, e.g., about 0.1 μm, formed by a substitution reaction process, and the second gold layer having a thickness of, e.g., about 0.3 μm to about 0.4 μm, formed by a reduction reaction process. In detail, a precleaning operation may be performed, after which the palladium layer may be formed using, e.g., a catalyst treatment. Subsequently, a nickel layer, which may serve as a diffusion barrier layer, may be formed using, e.g., NiP plating at a temperature of about 75° C. to about 90° C. The first and second gold layers may be formed using a gold substitution reaction and a gold reduction reaction at a temperature of about 65° C. to about 85° C., respectively. After each operation, a cleaning may be performed using deionized water. Where a tin layer is included in the conductive layer226, the tin may be deposited using electro-less plating at about 60° C. after a precleaning operation that includes cleaning with deionized water followed by soft etching using potassium persulfate, K2S2O8. The hardness of the feature may be adjusted using a heat treatment operation, e.g., heating to a temperature of about 250° C.

After the electro-less plating, exposed portions of the diffusion barrier layer216may be selectively removed, leaving a portion216aof the diffusion barrier layer between the first dielectric layer208and the overlying portion218aof the seed layer. Thus, in similar fashion to the first embodiment described above in connection withFIGS. 2A-2I, the conductive layer226may cover the copper core pattern224and may extend along sides of the copper core pattern224to contact a top surface of the diffusion barrier layer216. The conductive layer226may directly contact the diffusion barrier layer216, and may directly contact the remaining portion216aof the diffusion barrier layer after the selective removal of the exposed portions. The selective removal of the exposed portions of the diffusion barrier layer216may leave the remaining portion216ahaving a lateral extent that is substantially aligned with the outer periphery of the conductive layer226. The portion218aof the seed layer may be completely encapsulated by the surrounding conductive layer226, the overlying copper core pattern224, and the underlying portion216aof the diffusion barrier layer. Removing the exposed portions of the diffusion barrier layer216may interrupt the electrical path between copper core patterns224. Thus, the diffusion barrier216may act as a diffusion barrier as well as provide the electrical path during electro-less plating, and the remaining portion216amay remain after the electrical path is interrupted, so as to serve as a diffusion barrier in the resultant device.

Referring toFIG. 4G, a second dielectric layer228may be formed on the substrate202. The second dielectric layer228may be patterned to expose a top portion of the outer conductive layer226of the redistribution pattern210, the exposed portion corresponding to a location of the redistributed bonding pad212(see alsoFIG. 3B). The solder ball214, a bump, etc., may be disposed on the redistributed bonding pad212to enable an electrical connection to an adjacent substrate or element.

FIG. 5illustrates an example memory card system700, e.g., a multi-media card (MMC) or a secure digital (SD) card, according to a third embodiment. Referring toFIG. 5, the card700may include a controller710and a memory720. The memory720may be, e.g., a flash memory, a PRAM, a DRAM, etc. An interface may be provided for exchanging data and commands (instructions) between the controller710and the memory720). Another interface, e.g., a standard MMC or SD interface, may be provided for exchanging information with another device (not shown). The memory720, the controller710, and the interface therebetween may be packaged together as a multi-chip package (MCP).

FIG. 6illustrates an example electronic system800according to a fourth embodiment. Referring toFIG. 6, the system800may include a processor810, a memory820, at least one I/O (input/output) device830, and at least one bus840. The system800may be, e.g., a mobile phone, an MP3 device, a navigation system, a solid state disk (SSD), a household appliance, etc. The memory820, the processor810, the I/O device830, and the bus840may be packaged together as an MCP. In an implementation, one, some, or all of the components (memory820, the processor810and the I/O device840) may be packaged together, e.g., being vertically stacked together as an MCP.

FIG. 7illustrates an example display device900according to a fifth embodiment. The display device900may include a display901and a display driver integrated circuit902coupled to the display, e.g., coupled using an anisotropic conductive film903. The display901may be configured to reproduce an image in response to signals provided by the display driver integrated circuit902. The display driver integrated circuit902may include a substrate, e.g., a semiconductor substrate, having at least two features916thereon. The features916on the substrate may be features as described above having an outer conductive layer and a diffusion barrier layer respectively disposed between each feature and the substrate. A first impurity region of the substrate may contain impurities of a first type, and a second impurity region of the substrate may contain impurities of a second type, different from the first type. A first feature of the at least two features may be in the first impurity region, and a second feature of the at least two features may be in the second impurity region, such that the second feature is electrically isolated from first feature by the different impurity regions. Each respective diffusion barrier layer may extend laterally to an outer edge of the corresponding conductive layer and may be exposed by the corresponding conductive layer.

Exemplary embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. Thus, although specific embodiments have been described above whereby a bump and a redistribution pattern may be plated using an electro-less plating method, the method may be similarly applied to other features. Moreover, the method may be applied to a device in which the features, e.g., bumps or wiring patterns, are not isolated by different impurity regions. For example, embodiments may provide a device, e.g., a display driver integrated circuit in a display device, and a method of manufacturing the same, in which a diffusion barrier layer is formed on a substrate, at least two features are formed on the substrate such that the diffusion barrier layer is respectively disposed between each feature and the substrate, the diffusion barrier layer electrically connecting the at least two features, an outer conductive layer is electro-less plated on the at least two features while the at least two features are electrically connected by the diffusion barrier layer, and the diffusion barrier layer is selectively removed so as to interrupt the electrical connection. The outer conductive layer may contact a top surface of the diffusion barrier layer, the method may include, before forming the at least two features, forming a seed layer on the diffusion barrier layer in regions corresponding to the at least two features, and a portion of the seed layer corresponding to one of the features may be encapsulated by the outer conductive layer, the feature, and the diffusion barrier layer.

Accordingly, it will be understood by those of ordinary skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the following claims.