Error Detection in Communications over Serial Peripheral Interfaces

A memory device and a host system configured to transmit, using serial peripheral interfaces, an item (e.g., a command, an address, or a data item) followed by a cyclic redundancy check value of the item using operations same as transmission of one or more bits of the item. If the received cyclic redundancy check value does not match with the cyclic redundancy check value computed from the received item, an interrupt signal can be transmitted via a control line of a serial peripheral interface bus to request re-transmission of the item. When the host system detects a transmission error in receiving data from the memory device the serial peripheral interface bus, the host system can terminate the read command and re-transmit the read command.

TECHNICAL FIELD

At least some embodiments disclosed herein relate to memory systems in general, and more particularly, but not limited to memory systems communicating via Serial Peripheral Interfaces.

BACKGROUND

DETAILED DESCRIPTION

At least some aspects of the present disclosure are directed to error detection in communications through serial peripheral interfaces.

Memory devices implemented using NOR memory cells have been used recently in automotive systems as boot devices. NOR memory cells are reliable and fast (e.g., in comparison with NAND memory cells). A boot loader, firmware, and/or software (e.g., operating system, applications) can be stored in a NOR memory device as a boot device accessible, through a serial peripheral interface (SPI) bus, by a computing device in an automotive vehicle. However, a conventional serial peripheral interface (SPI) protocol for a computer bus does not have an error detection mechanism. When errors resulting from transmission over a conventional serial peripheral interface (SPI) bus are not detected, the reliability and safety of a vehicle using such a boot device can be reduced.

At least some aspects of the present disclosure address the above and other deficiencies by implementing an error detection mechanism in a serial peripheral interface (SPI) protocol. Using the error detection mechanism, errors introduced in communication on a conventional serial peripheral interface (SPI) bus can be detected to improve reliability and safety, such as the reliability and safety of an automotive vehicle configured to use an SPI NOR memory device as a boot device to store mission critical data.

For example, the error detection mechanism can be implemented using a technique of cyclic redundancy check (CRC). CRC data can be generated for commands, addresses, and/or data items transmitted over serial peripheral interface (SPI) buses. The CRC data can be transmitted over the serial peripheral interface (SPI) buses following the transmission of the respective commands, addresses, and/or data items. A memory device, or a host system, as a recipient can determine whether there is an error in the transmission by comparing the received CRC data with the CRC data generated from the received command, address or data item. When there is a mismatch between the computed CRC data and the received CRC data, a transmission error is detected.

When a memory device detects an error in a received command, address, or data item using the corresponding CRC data, the memory device can be configured to set an error bit in a status register and/or toggle an interrupt line of the bus to request re-transmission of the command, address, or data item.

During a read operation, when a host detects an error in a data item received from the memory device using the corresponding CRC data of the data item, the host can stop the current read operation and request the read again.

By detecting communication errors in serial peripheral interface (SPI) buses and requesting re-transmission of the received commands, addresses, and data items having transmission errors, the reliability and safety of automotive vehicles configured to use SPI NOR memory devices as boot devices are improved.

FIG.1illustrates an example computing system having a memory device in accordance with some embodiments of the present disclosure.

InFIG.1, a computing system has a memory device103and a host system101connected via a serial peripheral interface (SPI) bus having data lines107and control lines109. Optionally, the host system101is further connected to additional memory devices105via connections123, such as a serial peripheral interface (SPI) bus, a peripheral component interconnect express (PCIe) bus, a universal serial bus (USB) bus, or another bus.

For example, the memory device103can be configured as a boot device with content119stored in NOR memory cells117. The content119can include instructions executable in the host system101as a boot loader, firmware/software, an operating system, an application, etc., and input data for the instructions. Optionally, a portion of output generated from the execution of the instructions can be stored into the memory cells117.

For example, the computing system can be configured on an automotive vehicle to control certain operations of the vehicle.

For example, the host system101can include a vehicle control unit127configured to provide such services as reading sensors, motor control, torque coordination, operation and gearshift strategies, voltage coordination, charging control, on board diagnosis, monitoring, thermal management, etc.

For example, the host system101can include a control unit129of Advanced Driver Assistance System (ADAS) to fuse sensor data from cameras, lidar, radar, inertial measurement unites (IMUs), and/or map data, for perception and decision making.

For example, the content119stored in the memory cells117of the memory device103can include a boot loader, firmware, software, operating systems, application, etc., of the vehicle control unit127, the ADAS (Advanced Driver Assistance System) control unit (129), and/or the host system101.

InFIG.1, the memory device103and the host system101are connected via a serial peripheral interface (SPI) bus having data lines107and control lines109. Each of the lines has a signal connection usable to transmit a signal between from a pin of the serial peripheral interface (SPI)111of the memory device103and a corresponding pin of the serial peripheral interface (SPI)121of the host system101.

For example, the control lines109can include a line to transmit a clock signal, a line to transmit an interrupt signal, etc.

For example, the data lines107can include a predetermined number of lines to transmit signals representative of bits of a command, address, or data item according to the clock signal. Each of the data line107can transmit a signal independent of other lines; and the data lines107or a subset of the data lines107can be used as a group to transmit the bits of a command, address or data item one bit at a time through each line.

The memory device103has a cyclic redundancy check (CRC) module115configured to compute CRC data for a data item to be transmitted via the data lines107serial peripheral interface (SPI) bus to the host system101. The cyclic redundancy check (CRC) module115of the memory device is further configured to check a command, address, and/or data item received via the serial peripheral interface (SPI) bus from the host system101using corresponding CRC data received from the host system101via the data lines107for the command, address and/or data item.

When the memory device103detects an error in a received command, address, or data item, the cyclic redundancy check module115sets an error bit in the status register113and/or toggle a pin connected to the control lines109. For example, an interrupt pin can be pulled to a low voltage level to request re-transmission of the most recently transmitted command, address, or data item.

Similarly, the host system101has a cyclic redundancy check (CRC) module125configured to compute CRC data for a command, address, and/or a data item to be transmitted via the data lines107of serial peripheral interface (SPI) bus to the memory device103. The cyclic redundancy check (CRC) module125of the host system101is further configured to detect errors in a data item received in the serial peripheral interface (SPI)121using corresponding CRC data received from the memory device103via the data lines107for the data item.

When the host system101detects an error in a received data item, the host system101can terminate the current read operation and restart the previous read operation that has produced the erroneous data item received over the data lines107.

In general, a piece of CRC data of a data item can be computed from the data item using a predetermined formula. The data item can be transmitted with the CRC data for the recipient to determine whether there is an error in the receive data item by checking whether a corresponding CRC data computed from the received data item agrees with the received CRC data. If there is a mismatch, an error is detected in the received data item and the received CRC data.

For example, to protect the transmission of a n+1 bit data item, a 7-bit CRC value (CRC7) can be computed using a predetermined number x, a generator polynomial G(x)=x7+x3+1, and a function M(x)=(first bit)·xn+(second bit)·xn-1+ . . . +(last bit)·x0. The CRC7 can be computed as CRC [6:0]=Remainder[(M(x)·x7)/G(x)].

For example, to protect the transmission of a n+1 bit data item, a 16-bit CRC value (CRC16) can be computed using a predetermined number x, a generator polynomial G(x)=x16+x12+x5+1, and a function M(x)=(first bit)·xn+(second bit)·xn-1+ . . . +(last bit)·x0. The CRC16 can be computed as CRC [15:0]=Remainder[(M(x)·x16)/G(x)].

For example, CRC7 and/or CRC16 can be used in the data lines107of the serial peripheral interface (SPI) bus connected between the memory device103and the host system101to provide an error detection mechanism.

For example, the operations for transmitting the last bit of a command, address, or data item on a data line can be repeated in the next one or more cycles to transmit the CRC data of the corresponding command, address, or data item. A data lines107or a subset of the data lines107(e.g., 4 or 8 lines) can be used together to transmit the bits of a command, address, or data item, and its CRC data as illustrate dinFIG.2toFIG.9.

FIG.2toFIG.9illustrate transmission of cyclic redundancy check data for error detection in command, address, and data transmitted via a serial peripheral interface according to one embodiment.

FIG.2illustrates a clock signal151transmitted on a clock line among the control lines109of a serial peripheral interface (SPI) bus.

A waveform131illustrates the signals configured to transmit bits of a command and its CRC data over a group of four data lines107of a serial peripheral interface (SPI) bus.

According to a serial peripheral interface (SPI) protocol, a bit of a command from a host system101to a memory device103is transmitted over a data line107using one clock cycle in the clock signal151. A two clock cycle period141from time145to time147can be used to transmit an 8-bit command using four data lines107.

The operations of the last clock cycle between time153and time147can be repeated to extend the transmission of the command in the period141by two clock cycles to time149, as if the time periods141and143were used to transmit a 16-bit command. The time period143between the time147and time149can be used to transmit the CRC7 of the command two-bit per line in the same way as the transmitting the last bit per line for the command between time153and time147.

Upon receiving from the host system101the command in the time period141and the CRC data of the command in the time period143, the cyclic redundancy check module115of the memory device103can check the received command against the receive CRC data to determine if there is an error in the received command and the received CRC data. If there is an error, the memory device103as a recipient can set an error bit in the status register113and/or immediately assert an interrupt signal via an interrupt line among the control lines109to request the host system101as a sender to repeat the transmission of the signals provided in the time periods141and143.

Thus, the likelihood of the memory device103executes an erroneous command due to transmission error over a serial peripheral interface (SPI) bus is reduced or eliminated.

InFIG.3, after the transmission of a command and its CRC data in the time periods141and143(e.g., in a way as inFIG.2), the host system101of the memory device103can transmit an address in time period165between time149and time161, as illustrated by the waveform132.

According to a serial peripheral interface (SPI) protocol, the host system101can transmit, between time149and161, two bits of the address on each data line. One of the two bits transmitted during a clock cycle can be configured for sensing/detection at a rising edge of the clock signal151; and the other bit can be configured for sensing/detection at a falling edge of the clock signal151. Thus, the transmitting and receiving operations for each bit of the address in time period165are generally different from the transmitting and receiving operations for each bit of the command in time period141.

For example, when four bit lines are used to transmit the address in the time period165of three cycles, a 24-bit address can be transmitted from the host system101to the memory device103.

After time161, the operations in the last clock cycle between time155and161can be repeated to extend the transmission of the address by a time period167of one clock cycle, as if the time periods165and167were used to transmit a 32-bit address.

The time period167between the time161and time163can be used provide the CRC7 of the address transmitted in the time period165. The CRC7 of the address can be transmitted two-bit per line in one clock cycle in the same way as the transmitting the last two bits per line for the address between time155and time161.

Upon receiving the address in time period165and the CRC data of the address in time period167, the memory device103can check the received address against the receive CRC data to determine if there is an error in the received command and its CRC data. If there is an error, the memory device103can the memory device103as a recipient can set an error bit in the status register113and/or immediately assert an interrupt signal via an interrupt line among the control lines109to request the host system101as a sender to repeat the transmission of the signals provided in the time periods165and167.

Thus, the likelihood of the memory device103executes a command to operate at an erroneous address due to transmission errors over a serial peripheral interface (SPI) bus is reduced or eliminated.

After the communication of a write command and an address from the host system101to the memory device103, the host system101can transmit, via the data lines107of the serial peripheral interface (SPI) bus, a data item to be written into the memory device103for a write command.

After the communication of a read command and an address from the host system101to the memory device103, the memory device103can transmit, via the data lines107of the serial peripheral interface (SPI) bus, a data item retrieved from the memory device103in response to the read command.

The transmission of data for read and write commands are illustrated inFIG.4andFIG.5, after the transmission of a command and an address as inFIG.3.

InFIG.4, data is transmitted one byte at a time over data lines107. Similar to the transmission of addresses inFIG.3, data items can be transmitted on data lines107two bits per clock cycle. During a first clock cycle in a time period181between time185and time187, a byte is transmitted over four data lines107(e.g., from the memory device103to the host system101in response to a read command, or from the host system101to the device103following a write command). After the time period181, the operations during the last clock cycle between time157to187can be repeated for a clock cycle in the time period183, as if in an attempt to transmit a two-byte data time. During the time period183from time187to time189, the CRC7 of the byte transmitted in the time period181is transmitted, as illustrated by the waveform133.

If an error in the byte of data and its CRC data transmitted respectively in the time periods181and183is detected, the recipient can assert the interrupt signal to request the re-transmission of the byte and its CRC data.

If no error is detected, the next byte can be transmitted in the next clock cycle following the time period183of transmitting the CRC data.

InFIG.5, data is transmitted one block at a time over data lines107. For example, the data block can have a size of 512 bytes. Similar to the transmission of addresses inFIG.3, data items can be transmitted on data lines107two bits per clock cycle during a time period191to transmit the data block. After the time period191of transmitting a block of data, the operations for the transmission and reception in the last clock cycle between the time period159and197can be repeated for two clock cycles as illustrated by the waveform134to transmit the CRC16 of the data block transmitted in the time period191.

If an error in the block of data and its CRC data transmitted respectively in the time periods191and193is detected, the recipient can assert the interrupt signal to request the re-transmission of the block and its CRC data.

If no error is detected, the next block can be transmitted in the next time period195following the time period193of transmitting the CRC data from time197to time199.

FIG.2toFIG.5illustrate the transmission of commands, addresses and data items with CRC data over a group of four data lines107if a serial peripheral interface (SPI) bus.FIG.6toFIG.9illustrate the transmission of commands, addresses and data items with CRC data over a group of eight data lines107if a serial peripheral interface (SPI) bus.

InFIG.6, a waveform135shows the transmission of a 8-bit command in a time period141of one clock cycle followed by a time period143of one clock cycle for the transmission of the CRC7 of the command.

InFIG.7, a waveform136shows the transmission of a 24-bit address in a time period165of one and a half of clock cycles followed by a time period143of a half clock cycle for the transmission of the CRC7 of the address.

InFIG.8, a waveform137shows the transmission of a byte of a data item during the time period181of a half clock cycle followed by another half clock cycle arranged to transmit the CRC7 of the byte. Subsequently, another clock cycle is used to transmit a next byte in the first half and its CRC7 in the next half.

INFIG.9, a waveform138shows the transmission of a block of a data item during the time period181, which is followed by a time period193of one clock cycle for the transmission of CRC16 of the block transmitted in the time period181. A next block can be transmitted in a time period following the time period193of the CRC16.

FIG.10shows a method to detect errors in communications over a serial peripheral interface according to one embodiment.

For example, the method ofFIG.10can be used by the host system101and/or the memory device103ofFIG.1in communication over a serial peripheral interface bus according toFIG.2toFIG.9.

At block201, a host system101communicates to a memory device103a clock signal151over a first control line109of a serial peripheral interface bus connected between the memory device103and the host system101.

At block203, the memory device103and the host system101communicate an item over a plurality of data lines107of the serial peripheral interface bus during a first time period (e.g.,141,165,181, or191) of one or more clock cycles identified using the clock signal151.

At block205, the memory device103or the host system101computes a cyclic redundancy check value of the item for transmission of the item over the plurality of data lines107of the serial peripheral interface bus.

At block207, the memory device103and the host system101communicate the cyclic redundancy check value over the plurality of data lines107during a second time period (e.g.,143,167,183, or193) of one or more clock cycles identified using the clock signal151.

For example, the cyclic redundancy check value can be transmitted immediately following the transmission of the last bit of the item in a data line107, such that the second time period is configured to follow the first time period without a time gap longer than a quarter of a clock cycle. For example, the communications of bits of the cyclic redundancy check value can be transmitted in a same way as transmission of bits of the item. For example, the transmission of an 8-bit command and its CRC7 value can be transmitted in a same way of transmitting a 16-bit command. For example, the transmission of an 24-bit address and its CRC7 value can be transmitted in a same way of transmitting a 32-bit address. For example, the transmission of an 8-bit data item and its CRC7 value can be transmitted in a same way of transmitting a 16-bit address. For example, the transmission of an 512-byte data item and its CRC16 value can be transmitted in a same way of transmitting a 514-byte data item. Such an arrangement minimizes changes to be implemented to support error detection via Cyclic Redundancy Check (CRC).

For example, the item can be a 8-bit command. The 8-bit command can be is transmitted via four data lines107in the serial peripheral interface bus over two first clock cycles in the first time period141(e.g., as inFIG.2), or via eight data lines107in the serial peripheral interface bus over one first clock cycle in the first time period141(e.g., as inFIG.6). The cyclic redundancy check value (e.g., CRC7) of the 8-bit command can be transmitted via the four data lines over two second clock cycles in the second time period143(e.g., as inFIG.2), or via the eight data lines over one second clock cycle in the second time period143(e.g., as inFIG.6). After the transmission of the 8-bit command, a 24-bit address and a cyclic redundancy check value computed from the 24-bit address can be communicated, e.g., over the four data lines in four clock cycles following the two second clock cycles (e.g., as inFIG.3), or over the eight data lines in two clock cycles following the one second clock cycle (e.g., as inFIG.7).

For example, the item can be is 24-bit address. The address and the cyclic redundancy check value can be transmitted via four data lines in the serial peripheral interface bus over four clock cycles in the first time period165and the second time period167(e.g., inFIG.3). Alternatively, the address and the cyclic redundancy check value can be transmitted via eight lines in the serial peripheral interface bus over two clock cycles in the first time period165and the second time period167(e.g., as inFIG.7).

For example, the item can be an 8-bit data item to be written to the memory cells117via the command at the address, or retrieved from the memory cells117after execution the command the address. The 8-bit data item and the cyclic redundancy check value can be transmitted via four data lines in the serial peripheral interface bus over two clock cycles in the first time period181and the second time period183(e.g., as inFIG.4). Alternatively, the 8-bit data item and the cyclic redundancy check value can be transmitted via eight data lines in the serial peripheral interface bus over one clock cycle in the first time period181and the second time period183(e.g., as inFIG.8).

For example, the item can be a 512 byte data block. After the data block is transmitted in the serial peripheral interface bus in the first time period191, the cyclic redundancy check value can be transmitted via four data lines over two clock cycles in the second time period193(e.g., as inFIG.5), or via eight data lines over one clock cycle in the second time period193(e.g., as inFIG.9).

At block209, the memory device103or the host system101, as a recipient, determines whether a communication error has occurred in transmission of the item and the cyclic redundancy check value over the serial peripheral interface bus.

For example, to determine whether a communication error has occurred, the recipient can compute a cyclic redundancy check value computed from the item received via the serial peripheral interface bus, and compare the computed cyclic redundancy check value and the cyclic redundancy check value received via the serial peripheral interface bus. If there is a mismatch, a communication error is detected.

For example, when the memory device103determines that there is a communication error in a command, an address or a data item received from the host system101, the memory device103can assert an interrupt signal in a second control line109of the serial peripheral interface bus. The interrupt signal can cause the host system101to re-transmit the item (e.g., command, address or data item to be written into memory cells117of the memory device) and the cyclic redundancy check value of the item. Alternatively, or in combination, the memory device can set an error bit in a status register113in the memory device103in response to a determination that a communication error has occurred in transmission of the item and the cyclic redundancy check value over the serial peripheral interface bus. The error status can be reported to the host system101for error handling.

For example, when the host system101determines that there is a communication error in a data item retrieved from the memory device103(e.g., during execution of a read command), the host system101can terminate execution of a current command and re-transmit the current command to the memory device for execution.

In some embodiment, a computing system includes a host system101and a memory sub-system containing the memory device103and/or the memory devices105.

The memory sub-system can include media, such as one or more volatile memory devices (e.g.,105), one or more non-volatile memory devices (e.g.,103), or a combination of such.

The computing system can be a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., airplane, drone, train, automobile, or other conveyance), an Internet of Things (IoT) enabled device, an embedded computer (e.g., one included in a vehicle, industrial equipment, or a networked commercial device), or such a computing device that includes memory and a processing device.

For example, the host system101can include a processor chipset (e.g., processing device) and a software stack executed by the processor chipset. The processor chipset can include one or more cores, one or more caches, a memory controller (e.g., NVDIMM controller), and a storage protocol controller (e.g., PCIe controller, SATA controller). The host system101uses the memory sub-system, for example, to write data to the memory sub-system and read data from the memory sub-system.

The host system101can be coupled to the memory sub-system via a physical host interface. Examples of a physical host interface include, but are not limited to, a serial advanced technology attachment (SATA) interface, a peripheral component interconnect express (PCIe) interface, a universal serial bus (USB) interface, a Fibre Channel, a Serial Attached SCSI (SAS) interface, a double data rate (DDR) memory bus interface, a Small Computer System Interface (SCSI), a dual in-line memory module (DIMM) interface (e.g., DIMM socket interface that supports Double Data Rate (DDR)), an Open NAND Flash Interface (ONFI), a Double Data Rate (DDR) interface, a Low Power Double Data Rate (LPDDR) interface, a serial peripheral interface, or any other interface. The physical host interface can be used to transmit data between the host system101and the memory sub-system. The host system101can further utilize an NVM Express (NVMe) interface to access components (e.g., memory devices103) when the memory sub-system is coupled with the host system101by the PCIe interface. The physical host interface can provide an interface for passing control, address, data, and other signals between the memory sub-system and the host system101. In general, the host system101can access multiple memory sub-systems via a same communication connection, multiple separate communication connections, and/or a combination of communication connections.

The processing device of the host system101can be, for example, a microprocessor, a central processing unit (CPU), a processing core of a processor, an execution unit, etc. In some instances, the memory controller in the host system101can be control the communications over a bus coupled between the host system101and the memory sub-system. In general, the memory controller can send commands or requests to the memory sub-system for desired access to memory devices103and/or105. The memory controller can further include interface circuitry to communicate with the memory sub-system. The interface circuitry can convert responses received from memory sub-system into information for the host system101.

The memory controller of the host system101can communicate with a controller of the memory sub-system to perform operations such as reading data, writing data, or erasing data at the memory devices103and/or105and other such operations. In some instances, the memory controller is integrated within the same package of the processing device of the host system101. In other instances, the memory controller is separate from the package of the processing device of the host system. The memory controller and/or the processing device of the host system101can include hardware such as one or more integrated circuits (ICs) and/or discrete components, a buffer memory, a cache memory, or a combination thereof. The memory controller and/or the processing device of the host system101can be a microcontroller, special purpose logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or another suitable processor.

The memory devices103and105can include any combination of the different types of non-volatile memory components and/or volatile memory components. The volatile memory devices (e.g., memory device105) can be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

A memory sub-system can have a controller configured to communicate with the memory devices103and105to perform operations such as reading data, writing data, or erasing data at the memory devices103and105and other such operations (e.g., in response to commands scheduled on a command bus by the memory controller of the host system101). The controller of the memory sub-system can include hardware such as one or more integrated circuits (ICs) and/or discrete components, a buffer memory, or a combination thereof. The hardware can include digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The controller of the memory sub-system can be a microcontroller, special purpose logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or another suitable processor.

The controller of the memory sub-system can include a processing device or processor configured to execute instructions stored in a local memory. In an example, the local memory of the memory sub-system includes an embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines that control operation of the memory sub-system, including handling communications between the memory sub-system and the host system101.

In some embodiments, the local memory of the memory sub-system can include memory registers storing memory pointers, fetched data, etc. The local memory can also include read-only memory (ROM) for storing micro-code. In one example, a memory sub-system a controller; and in another example, a memory sub-system does not include a controller, and can instead rely upon external control (e.g., provided by an external host, or by a processor or controller separate from the memory sub-system).

The memory sub-system can also include additional circuitry or components that are not illustrated. In some embodiments, the memory sub-system can include a cache or buffer (e.g., DRAM) and address circuitry (e.g., a row decoder and a column decoder) that can receive an address from the controller of the memory sub-system and decode the address to access the memory devices103.

In some embodiments, the memory devices103include local media controllers that operate in conjunction with memory sub-system controller to execute operations on one or more memory cells of the memory devices103. An external controller (e.g., memory sub-system controller) can externally manage the memory device103(e.g., perform media management operations on the memory device103). In some embodiments, a memory device103is a managed memory device, which is a raw memory device combined with a local controller for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.