Semiconductor device with pump circuit

In the present semiconductor device a positive, driving pump circuit is driven by an external power supply potential EXVDD (for example of 1.8V) to generate a positive voltage VPC (for example of 2.4V). A negative pump circuit for internal operation is driven by the positive voltage VPC to generate a negative voltage VNA (for example of −9.2V) required in an erasure or similar internal operation for a word line. The negative pump circuit for internal operation can have a smaller number of stages of pump and hence consume a smaller area than when the circuit is driven by the external power supply voltage EXVDD (for example of 1.8V) as conventional.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to semiconductor devices and particularly to semiconductor devices including a charge pump circuit and a clock driver.

2. Description of the Background Art

In flash memory, a non-volatile memory capable of electrical erasure and rewriting, word and bit lines are set to different potential depending on each mode of operation. For example, a word line in a read is set to 5.5V and in a programming operation is set to 9.7V, and in data erasure is set to −9.2V. A bit line in a read is set to 0.7V and in a programming operation is set to 5.1V. Furthermore, a well potential in a read is set to 0V and in a programming operation is set to −0.9V. Accordingly to generate from a single external power supply voltage (for example of 1.8V) a voltage required in each mode of operation a variety of pump circuits are provided.

A proposed, conventional pump circuit generating a negative voltage resets a constituent P channel MOS transistor's gate electrode in potential when the pump circuit is inactive. The second and succeeding pump operations can also be performed without reduced rates of generating the negative voltage (see Japanese Patent Laying-Open No. 2002-032987 for example).

Furthermore, there is also another conventional pump circuit proposed to share a pump module operating in standby and active cycles. This can eliminate the necessity of separate circuits for the standby and active cycles, respectively, and a reduced circuit area can be achieved (see Japanese Patent Laying-Open No. 07-111093 for example).

In recent years there is a demand for a semiconductor device having a further reduced area. Conventional semiconductor devices, however, have not yet achieved a sufficiently reduced pump circuit area.

SUMMARY OF THE INVENTION

Accordingly the present invention mainly contemplates a semiconductor device having a small area.

The present invention provides a semiconductor device including: a first charge pump circuit driven by a first type of clock signal corresponding to a first amplitude voltage to generate a prescribed potential; an amplitude conversion circuit converting the first amplitude voltage of the first type of clock signal to a second amplitude voltage to output a second type of clock signal, the second amplitude voltage being larger than the first amplitude voltage and corresponding to the prescribed potential; and a second charge pump circuit driven by the second type of clock signal. The second charge pump can have a reduced number of pump stages and the semiconductor device can be reduced in area.

The present invention in another aspect provides a semiconductor device including: a first charge pump circuit pumping in an active time when the semiconductor device has an internal circuit in operation; a second charge pump circuit having an output node connected to the first charge pump circuit's output node and pumping in a standby time when the semiconductor device has the internal circuit on standby; and a third charge pump circuit having an input node connected to the first and second charge pump circuits' output node and pumping in the active and standby times. As the third charge pump circuit can be shared in the active and standby times, the semiconductor device can be reduced in area.

The present invention in still another aspect provides a semiconductor device including a clock driver and provided with: a first clock driver circuit having a first inverter with a first transistor of a first conductance and a second transistor of a second conductance connected in series between a power supply potential node and a reference potential node to transmit the clock signal when a power supply potential is associated with a specification of a first level; and a second clock driver circuit having a second inverter with a third transistor of the first conductance and a fourth transistor of the second conductance having a gate insulation film smaller in thickness than that of the first and second transistors and connected in series between the power supply potential node and the reference potential node to transmit the clock signal when a power supply potential is associated with a specification of a second level lower than the first level. When the power supply potential is the first level the third and fourth transistors each have gate and drain electrodes connected to a source electrode and when the power supply potential is the second level the third and fourth transistors have their gate electrodes connected in common to an input node of the second inverter and the third and fourth transistors have their drain electrodes connected in common to an output node of the second inverter. As the first and third transistors can be provided within a single well region the semiconductor device can be reduced in area.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

With reference toFIG. 1, a semiconductor integrated circuit device includes a clock generation circuit1, reference potential generation circuits2,4, a divider circuit portion3, a positive pump circuit for normal operation11, positive pump circuits for internal operation12,13, a positive, driving pump circuit14, negative pump circuits for internal operation15–17, input terminals21,22, external application select circuits23–28, reset circuits29–33, select circuits34–37, a write circuit38, a word line driver39, a well driver40, a source driver41and a memory portion42.

The positive pump circuit for normal operation11, the positive pump circuits for internal operation12,13, and positive, driving pump circuit14are driven by a single, external power supply potential EXVDD (for example of 1.8V). The negative pump circuits for internal operation15–17are driven by a potential VPC (for example of 2.4V) provided from positive, driving pump circuit14.

Clock generation circuit1generates a clock signal CLK required for each pump circuit. Reference potential generation circuit2generates a reference potential VREF required for each pump circuit. Divider circuit portion3divides clock signal CLK output from clock generation circuit1to output a clock signal CLKD. Reference potential generation circuit4generates a reference potential VREFS required for the positive pump circuit for normal operation11.

The positive pump circuit for normal operation11receives reference potential VREFS to generate a positive potential VPP (for example of 5.5V) required for example in a read or similar, normal operation for a word line. The positive pump circuit for internal operation12receives clock signal CLKD and reference potential VREF to generate a positive potential VPB (for example of 5.1V) required for example in a programming or similar internal operation for a bit line. The positive pump circuit for internal operation13receives clock signal CLK and reference potential VREF to generate a positive potential VPW (for example of 9.7V) required for example in a programming or similar internal operation for a word line.

Positive, driving pump circuit14receives clock signal CLK and reference potential VREF to generate and provide positive potential VPC (for example of 2.4V) to the negative pump circuits for internal operation15–17. The negative pump circuit for internal operation15receives clock signal CLK and reference potential VREF to generate a negative potential VNA (for example of −9.2V) required for example in an erasure or similar internal operation for a word line. The negative pump circuit for internal operation16receives clock signal CLK and reference potential VREF to generate a negative potential VNB (for example of −0.5V) required for example in a programming or similar internal operation for word line driver39. The negative pump circuit for internal operation17receives clock signal CLK and reference potential VREF to generate a negative potential VNC (for example of −0.9V) required for example in a programming or similar internal operation for the well.

Input terminals21and22receive an external potential VEX. External application select circuit23selects and outputs one of external potential VEX received from input terminal21and potential VPP received from the positive pump circuit for normal operation11. External application select circuit24selects and outputs one of external potential VEX received from input terminal21and potential VPB received from the positive pump circuit for internal operation12. External application select circuit25selects and outputs one of external potential VEX received from input terminal21and potential VPW received from the positive pump circuit for internal operation13. External application select circuit26selects and outputs one of external potential VEX received from input terminal22and potential VNA received from the negative pump circuit for internal operation15. External application select circuit27selects and outputs one of external potential VEX received from input terminal22and potential VNB received from the negative pump circuit for internal operation16. External application select circuit28selects and outputs one of external potential VEX received from input terminal22and potential VNC received from the negative pump circuit for internal operation17.

Reset circuit29performs a reset operation providing a potential output from external application select circuit23to an output node of external application select circuit24when the positive pump circuit for internal operation12is inactive. Reset circuit30performs a reset operation providing a potential output from external application select circuit23to an output node of external application select circuit25when the positive pump circuit for internal operation13is inactive. Reset circuit31performs a reset operation resetting an output node of external application select circuit26to a ground potential (0V) when the negative pump circuit for internal operation15is inactive. Reset circuit32performs a reset operation resetting an output node of external application select circuit27to a ground potential (0V) when the negative pump circuit for internal operation16is inactive. Reset circuit33performs a reset operation resetting an output node of external application select circuit28to a ground potential (0V) when the negative pump circuit for internal operation17is inactive.

Select circuit34selects one of potentials output from external application select circuits23and25and the ground potential (0V) and provides the selected potential to word driver39. Select circuit35selects one of the potentials output from external application select circuits23and25and the ground potential (0V) and provides the selected potential to well driver40and source driver41. Select circuit36selects one of potentials output from external application select circuits26and27and the ground potential (0V) to provide the selected potential to word driver39. Select circuit37selects one of potentials output from external application select circuits26and28and the ground potential (0V) to provide the selected potential to well and source drivers40and41.

Write circuit38receives a potential output from external application select circuit24and provides to bit line BL of memory portion42a prescribed potential corresponding to a mode of operation. Word line driver39receives potentials output from select circuits34and36and provides to word line WL of memory portion42a prescribed potential corresponding to a mode of operation. Well driver40receives potentials output from select circuits35and37and provides to a well of memory portion42a prescribed potential corresponding to a mode of operation. Source driver41receives potentials output from select circuits35and37and provides to source line SL of memory portion42a prescribed potential corresponding to a mode of operation. Memory portion42includes a plurality of memory cells to store data.

For example in a read operation the positive pump circuit for normal operation11provides potential VPP (for example of 5.5V) which is in turn provided via external application select circuit23, select circuit34and word line driver39to memory portion42on word line WL. The memory portion42well receives the ground potential (0V) from select circuit37via well driver40. Furthermore, the memory portion42source line SL receives the ground potential (0V) from select circuit37via source driver41.

In a programming operation the positive pump circuit for internal operation13provides potential VPW (for example of 9.7V) which is in turn provided via external application select circuit25, select circuit34and word line driver39to memory portion42on word line WL. Furthermore, the positive pump circuit for internal operation12provides potential VPB (for example of 5.1 V) which is in turn provided via external application select circuit24and write circuit38to memory portion42on bit line BL. Furthermore, the negative pump circuit for internal operation17provides potential VNC (for example of −0.9V) which is in turn provided via external application select circuit28, select circuit37and well driver40to memory portion42at the well. Furthermore, the memory portion42source line SL receives the ground potential (0V) from select circuit35.

In an erasure operation the negative pump circuit for internal operation15provides potential VNA (for example of −9.2V) which is in turn provided via external application select circuit26, select circuit36and word line driver39to memory portion42on word line WL. The memory portion42well receives potential VPW (for example of 7.5V) from the positive pump circuit for internal operation13via external application select circuit25, select circuit35and well driver40. Furthermore, the memory portion42source line SL receives potential VPW (for example of 7.5V) from the positive pump circuit for internal operation13via external application select circuit25, select circuit35and source driver41. Note that the positive pump circuit for internal operation13outputs potential VPW, which has a level switched in accordance with a state of operation (for example in a programming operation it is set to 9.7V and in an erasure operation it is set to 7.5V).

With reference toFIG. 2, divider circuit portion3includes a divider circuit59and a select circuit60. The positive pump circuit for internal operation12includes an inverter51, a detection circuit52, clock drivers53and54, charge pumps55and56, and AND circuits57and58. The positive pump circuit for internal operation13includes an inverter61, a detection circuit62, clock drivers63and64, charge pumps65and66, and AND circuits67and68.

Divider circuit59for an enable signal EN1having the high level of an activation level divides (or reduces in frequency) clock signal CLK received from clock generation circuit1to generate a clock signal CLK1. For enable signal EN1having the low level of an inactivation level, divider circuit59exactly outputs clock signal CLK as a clock signal CLK2. Select circuit60for enable signal EN1having the high level of the activation level selects clock signal CLK1received from divider circuit59and outputs the signal as clock signal CLKD. For enable signal EN1having the low level of the inactivation level, select circuit60selects clock signal CLK2output from divider circuit59and outputs the signal as clock signal CLKD. Inverter51inverts clock signal CLKD in logic level for output. Inverter61inverts clock signal CLK in logic level for output.

With reference toFIG. 3, detection circuit52includes resistors71and72, a comparison circuit73, and a constant current source74. Potential VBP, provided from output node N1, is divided by resistors71and72in voltage and provided as a divided voltage potential VPBD to a negative input terminal of comparison circuit73. Comparison circuit73has a positive input terminal receiving reference potential VREF, a potential corresponding to a target level of potential VPB. Constant current source74is connected between a ground terminal of comparison circuit83and a line of a ground potential GND.

Comparison circuit73compares divided voltage potential VPBD with reference potential VREF and if divided potential VPBD is lower than reference potential VREF comparison circuit73outputs a detection signal PEB set high and if divided voltage potential VPBD is higher than reference potential VREF comparison circuit73outputs detection signal PEB set low. Thus detection circuit52operates in accordance with reference potential VREF provided from reference potential generation circuit2and potential VPB provided from output node N1to output detection signal PEB to AND circuits57and58.

Again with reference toFIG. 2detection circuit62is similar in configuration and operation to theFIG. 3detection circuit52, operating in accordance with reference potential VREF provided from reference potential generation circuit2and potential VPW provided from output node N2to output a detection signal PEW to AND circuits67and68.

AND circuits57and58receive an enable signal EN2externally and detection signal PEB from detection circuit52. AND circuit57outputs a signal provided to clock driver53. AND circuit58outputs a signal provided to clock driver54. AND circuit67receives an enable signal EN3externally and detection signal PEW from detection circuit62. AND circuit67outputs a signal provided to clock driver63. AND circuit68receives an enable signal EN4externally and detection signal PEW from detection circuit62. AND circuit68outputs a signal provided to clock driver64.

Clock driver53is activated in response a signal of the high level output from AND circuit57to amplify clock signal CLKD received from divider circuit portion3in current to generate a 4-phase clock signal φA1–φA4and provides the signal to charge pump55. When AND circuit57outputs a signal of the low level clock driver53is inactivated and does not transmit clock signal CLKD received from divider circuit portion3.

With reference toFIG. 4, the clock driver53unit circuit includes switch circuits81–84, P channel MOS transistor groups85and87, and N channel MOS transistor groups86and88.

Switch circuits81–84are controlled by an external select signal SEL. When external power supply potential EXVDD is low (e.g., 1.8V) select signal SEL is set low. When external power supply potential EXVDD is high (e.g., 3.0V) select signal SEL is set high. Switch circuit81operates for select signal SEL having the low level to connect a line of ground potential GND and a node N12. For select signal SEL having the high level, switch circuit81connects nodes N11and N12. Switch circuit82operates for select signal SEL having the low level to disconnect output nodes N14and N18from each other. For select signal SEL having the high level, switch circuit82connects output nodes N14and N18. Switch circuit83operates for select signal SEL having the low level to connect nodes N11and N15. For select signal SEL having the low level, switch circuit83connects a line of ground potential GND and node N15. Switch circuit84operates for select signal SEL having the low level to connect output nodes N17and N18. For select signal SEL having the high level, switch circuit84disconnects output nodes N17and N18from each other.

P channel MOS transistor group85includes P channel MOS transistors91and92and a plurality of P channel MOS transistors101. N channel MOS transistor group86includes N channel MOS transistors93and94and a plurality of N channel MOS transistors102. P and N channel MOS transistors101and102are equal in number.

P channel MOS transistors91and92are each connected between a line of external power supply potential EXVDD and a node N13. N channel MOS transistors93and94are connected in series between node N13and a line of ground potential GND. P and N channel MOS transistors91and94have their respective gates both connected to node N12. P and N channel MOS transistors92and93have their respective gates both receiving a signal output from AND circuit57. P and N channel MOS transistors101and102are connected in series between a line of external power supply potential EXVDD and a line of ground potential GND. P and N channel MOS transistors101and102form a plurality of pairs configuring inverters, respectively. These inverters are connected in series between node N13and output node N14.

P channel MOS transistor group87includes P channel MOS transistors95and96and a plurality of P channel MOS transistors103. N channel MOS transistor group88includes N channel MOS transistors97and98and a plurality of N channel MOS transistors104. P and N channel MOS transistors103and104are equal in number.

P channel MOS transistors95and96are each connected between a line of external power supply potential EXVDD and a node N16. N channel MOS transistors97and98are connected in series between node N16and a line of ground potential GND. P and N channel MOS transistors95and98have their respective gates both connected to node N15. P and N channel MOS transistors96and97have their respective gates both receiving a signal output from AND circuit57. P and N channel MOS transistors103and104are connected in series between a line of external power supply potential EXVDD and a line of ground potential GND. P and N channel MOS transistors103and104form a plurality of pairs configuring inverters, respectively. These inverters are connected in series between node N16and output node N17.

Note that P channel MOS transistors91,92,101and N channel MOS transistors93,94,102have a thick oxide film and they are suitable for high external power supply potential EXVDD (for example of 3V). P channel MOS transistors95,96,103and N channel MOS transistors97,98,104have a thin oxide film and they are suitable for low external power supply potential EXVDD (for example of 1.8V). Thus transistor groups85and86configured of transistors having a thick oxide film and transistor groups87and88configured of transistors having a thin oxide film are provided and selectively used depending on the external power supply potential EXVDD level.

More specifically, if external power supply potential EXVDD is high (e.g., 3V), select signal SEL is set high and clock signal CLKD is transmitted via inverters of a plurality of stages configured of P and N channel MOS transistor groups85and86, respectively, and output at output node N18as clock signal φA1. If external power supply potential EXVDD is low (e.g., 1.8V) select signal SEL is set low and clock signal CLKD is transmitted via inverters of a plurality of stages configured of P and N channel MOS transistor groups87and88, respectively, and output at output node N18as clock signal φA1.

FIG. 5is a circuit diagram more specifically showing a configuration of P and N channel MOS transistor groups87and88shown inFIG. 4. With reference to the figure, P channel MOS transistors95,96,93have their respective gates provided with switch circuits105,107,112. P channel MOS transistors95,96,103have their respective drains provided with switch circuits106,108,113. N channel MOS transistors97,104have their respective drains provided with switch circuits109,114. N channel MOS transistors97,98,104have their respective gates provided with switch circuits110,111,115. Switch circuits105–115are controlled by select signal SEL.

When select signal SEL has the low level (or external power supply potential EXVDD is low) switch circuit105connects node N15and the P channel MOS transistor95gate. Switch circuit106connects the P channel MOS transistor95drain and node N16. Switch circuit107connects the AND circuit57output node and the P channel MOS transistor96gate. Switch circuit108connects the P channel MOS transistor96drain and node N16. Switch circuit109connects node N16and the N channel MOS transistor97drain. Switch circuit110connects the AND circuit57output node and the N channel MOS transistor97gate. Switch circuit111connects node N15and the N channel MOS transistor98gate. As such, if AND circuit57outputs a signal of the high level, P channel MOS transistor96turns off and N channel MOS transistor97turns on, and a clock signal transmitted to node N15has its logic level inverted and thus provided to node N16. If AND circuit57outputs a signal of the low level, P channel MOS transistor96turns on and N channel MOS transistor97turns off, and node N16is fixed high and a clock signal transmitted to node N15is not transmitted to node N16.

If select signal SEL has the high level (or external power supply potential EXVDD is high) switch circuit105connects a line of external power supply potential EXVDD and the P channel MOS transistor95gate. Switch circuit106connects the P channel MOS transistor95drain and a line of external power supply potential EXVDD. Switch circuit107connects a line of external power supply potential EXVDD and the P channel MOS transistor96gate. Switch circuit108connects the P channel MOS transistor96drain and a line of external power supply potential EXVDD. Switch circuit109connects a line of ground potential GND and the N channel MOS transistor97drain. Switch circuit110connects a line of ground potential GND and the N channel MOS transistor97gate. Switch circuit111connects a line of ground potential GND and the N channel MOS transistor98gate.

Thus P channel MOS transistors95,96have their sources, drains and gates all connected to line of external power supply potential EXVDD. Furthermore, the N channel MOS transistor97drain and gate and the N channel MOS transistor98source and gate are both connected to line of ground potential GND. P channel MOS transistors95,96and N channel MOS transistors97and98are turned off to prevent high external power supply potential EXVDD from impairing MOS transistor.

Furthermore, if select signal SEL has the high level (or external power supply potential EXVDD is low) switch circuit112connects node N16and the P channel MOS transistor103gate. Switch circuit113connects the P channel MOS transistor103drain and a node N21. Switch circuit114connects node N21and the N channel MOS transistor104drain. Switch circuit115connects node N16and the N channel MOS transistor104gate. Thus a clock signal transmitted to node N16is inverted in logic level and thus provided to node N21.

If select signal SEL has the high level (or external power supply potential EXVDD is high) select circuit112connects a line of external power supply potential EXVDD and the P channel MOS transistor103gate. Switch circuit113connects the N channel MOS transistor103drain and a line of external power supply potential EXVDD. Switch circuit114connects a line of ground potential GND and the N channel MOS transistor104drain. Switch circuit115connects a line of ground potential GND and the N channel MOS transistor104gate.

Thus P channel MOS transistor103has its source, drain and gate all connected to line of external power supply potential EXVDD. Furthermore N channel MOS transistor104has its source, drain and gate all connected to line of ground potential GND. As such, P and N channel MOS transistors103and104are turned off to prevent high external power supply potential EXVDD from impairing MOS transistors.

Thus P and N channel MOS transistor groups87and88include MOS transistors switched to prevent high external power supply potential EXVDD from being applied to and thus impairing MOS transistors.

Note that while switch circuits81–84and105–115have been described as switch circuits switched by select signal SEL, switch circuits81–84and105–115may alternatively be switch circuits having an aluminum (Al) interconnect path switched by changing a mask.

FIG. 6is a layout for illustrating an arrangement of P channel MOS transistor groups85,87and N channel MOS transistor groups86,88shown inFIG. 4. In the figure, an N well region121is connected to a line of external power supply potential EXVDD and a P well region122is connected to a line of ground potential GND.

N well region121has PMOS regions123,124arranged therein. PMOS region123has arranged therein P channel MOS transistors91,92and the plurality of P channel MOS transistors101shown inFIG. 4. PMOS region124has arranged therein P channel MOS transistors95,96and the plurality of P channel MOS transistors103shown inFIG. 4.

P well region122underlies MOS regions125,126. NMOS region125has arranged therein N channel MOS transistors93,94and the plurality of N channel MOS transistors102shown inFIG. 4. NMOS region126has arranged therein N channel MOS transistors97,98and the plurality of N channel MOS transistors104shown inFIG. 4.

For conventional clock drivers, N well region121is separated in two and PMOS regions123and124are arranged on separate N well regions, since P and N channel MOS transistor groups87and88are not provided with switch circuits105–115. In that case when external power supply potential EXVDD is high node N15is set low and P channel MOS transistor95turns on. P channel MOS transistor95, with a thin oxide film, receives high external power supply potential EXVDD, and transistor may be impaired. Accordingly, the N well region having PMOS region123arranged therein and that having PMOS region124arranged therein are separated. This allows the N well region with PMOS region123to receive a high external power supply potential EXVDDH and that with PMOS region124to receive a low internal power supply potential EXVDDL. This configuration, however, requires a space at a boundary of the two N well regions and hence an increased layout area for the clock driver.

Accordingly in the present embodiment P and N channel MOS transistor groups87and88are provided with switch circuits105–115and PMOS regions123and124are arranged on a single N well region121. The clock driver's layout area can thus be reduced.

Note that theFIG. 6layout shows an arrangement of a transistor of a unit circuit of clock driver53shown inFIG. 4, and clock driver53is provided with a plurality of such unit circuits. For example if charge pump55has a 10-stage configuration, the number of unit circuits is twice that of the stages of pump portions, i.e., 20 unit circuits are provided. As such in the present embodiment a clock driver can be provided with unit circuits each having a reduced layout area and as a result the clock driver's entire layout area can significantly be reduced.

With reference again toFIG. 2clock drivers53,63,64are similar in configuration and operation to clock driver53. Clock driver54is activated for a signal of the high level output from AND circuit58to amplify a clock signal output from inverter51in current to generate a 4-phase clock signal /φA1–/φA4and provide the signal to charge pump56. If AND circuit58outputs a signal of the low level, clock driver54is inactivated and does not transmit a clock signal output from inverter51. Clock driver63is activated for a signal of the high level output from AND circuit67to amplify clock signal CLK received from clock generation circuit1in current to generate a 4-phase clock signal φB1–/φB4and provide the signal to charge pump65. If AND circuit67outputs a signal of the low level, clock driver63is inactivated and does not transmit clock signal CLK received from clock generation circuit1. Clock driver64is activated for a signal of the high level output form AND circuit68to amplify a clock signal output from inverter61in current to generate 4-phase clock signal /φB1–/φB4and provide the signal to charge pump66. If AND circuit68outputs a signal of the low level, clock driver64is inactivated and does not transmit a clock signal output from inverter61.

Charge pump55is driven by clock signal φA1–φA4output from clock driver53to generate and provide potential VPB to output node N1. Charge pump56is driven by clock signal /φA1–/φA4output from clock driver54to generate and provide potential VPB to output node N1. Charge pump65is driven by clock signal φB1–φB4output from clock driver63to generate and provide potential VPW to output node N2. Charge pump66is driven by clock signal /φB1–φB4output from clock driver64to generate and provide potential VPW to output node N2.

Charge pump65will more specifically be described in configuration and operation. With reference toFIG. 7, charge pump65includes N channel MOS transistors131–151and capacitors161–180.

N channel MOS transistors131–140are connected in series between a line of external power supply potential EXVDD and a node N51. N channel MOS transistors131–140have their gates connected to nodes N31–N40, respectively. N channel MOS transistors141–150are connected between nodes N41–N50and nodes N31–N40, respectively. N channel MOS transistors141–150have their gates connected to nodes N42–N51, respectively. N channel MOS transistor51has its drain and gate connected to node N51to configure a diode. N channel MOS transistor151has a source outputting potential VPW.

The odd numbered capacitors161–169have their respective one electrodes receiving clock signal φB2from clock driver63and their respective other electrodes connected to the odd numbered nodes N31–N39. The even numbered capacitors162–170have their respective one electrodes receiving clock signal φB4from clock driver63and their respective other electrodes connected to the even numbered nodes N32–N40. The odd numbered capacitors171–179have their respective one electrodes receiving clock signal φB3from clock driver63and their respective other electrodes connected to the even-numbered nodes N42–N50. The even numbered capacitors172–180have their respective one electrodes receiving clock signal φB1from clock driver63and have their respective other electrodes connected to the odd numbered nodes N43–N51. Charge pump65thus has a 10-stage pump configuration.

FIG. 8is a circuit diagram showing a configuration for resetting a potential of nodes N31–N40of theFIG. 7charge pump65. With reference to the figure, charge pump65further includes an inverter181, P channel MOS transistors182,183, and N channel MOS transistors184,185,191–200.

P and N channel MOS transistors182and184are connected in series between a line of potential VPP (or a potential output from the positive pump circuit for normal operation11) and a line of ground potential GND. P channel MOS transistor182has its gate connected to output a node N62. N channel MOS transistor184has its gate receiving a reset signal RS externally via inverter181. P and N channel MOS transistors183and185are connected in series between a line of potential VPP (a potential output from the positive pump circuit for normal operation11) and a line of ground potential GND. P channel MOS transistor183has its gate connected to a node N61. N channel MOS transistor185has a gate receiving external reset signal RS.

N channel MOS transistors191–200are connected between nodes N31–N40shown inFIG. 7, respectively, and a line of external power supply potential EXVDD. N channel MOS transistors191–200have their gates connected in common to output node N61.

FIG. 9is timing plots for illustrating an operation of charge pump65. With reference to the figure, clocks signals φB1–φB4are signals provided from clock driver63.

With reference to the timing plots a pump portion of the 10th stage shown inFIG. 7operates as will be described hereinafter. From time t0through time t1clock signals φB1, φB2are set high, node N49has its electric charge transferred to node N50, and node N50is charged to a high potential. At time t1clock signal φB2is pulled low and in response N channel MOS transistor139turns off and nodes N49and N50are electrically disconnected. Then at time t2clock signal φB3is pulled high and in response node N50increases in potential. As clock signal φB1has the high level and N channel MOS transistor150has responsively been turned on, node N50has its electric charge transferred to node N40, and node N40is charged to a high potential. At time t3clock signal φB1is pulled low and in response N channel MOS transistor150turns off and nodes N50and N44are electrically disconnected. Then at time t4clock signal φB4is pulled high and in response N channel MOS transistor140turns on, when the node N40potential having been charged to the high potential further increases and N channel MOS transistor140thus has its transferring ability increased, and node N50has its electric charge transferred to node N51without being affected by a threshold voltage of N channel MOS transistor140. The first to ninth stages' pump portions similarly operate and nodes N41–N51sequentially increase in potential.

If the diode configuring N channel MOS transistor151has a threshold voltage Vt then the node N51potential, i.e., the 10th stage's pump portion outputs a potential VPW+Vth. As such, if an i-th stage's pump portion outputs a potential Vi then the following expression:
Vj=EXVDD+i(VPW+Vth−EXVDD)/10  (1)
is established.

Nodes N31–N40each associated with a stage's pump portion are set higher in potential than potential Vi output from the stage's pump portion. Let us consider that the positive pump circuit for internal operation13performs a pumping operation once stopped and thereafter resumed for the sake of illustration. More specifically, with reference toFIG. 1, external application select circuit23selects and outputs potential VPP (for example of 5.5V) output from the positive pump circuit for normal operation11and external application select circuit25selects and outputs potential VPW (for example of 9.7V) output from the positive pump circuit for internal operation13, and in that condition the positive pump circuit13operation is stopped and reset circuit30provides an output node of external application select circuit24with potential VPP (for example of 5.5V) output from external application select circuit23. Subsequently, the positive pump circuit13operation is resumed to again generate potential VPW (for example of 9.7V).

In that case, with reference toFIG. 7, charge pump65outputs a potential reset from VPW (for example of 9.7V) to VPP (for example of 5.5V). Node N51has been set at a high potential (for example of 5.5V+Vth). As there still remains high potential at node N40, N channel MOS transistor140turns on, and node N50is brought to the same high potential as node N51(for example of 5.5V+Vth). N channel MOS transistor150is turned on receiving the high potential of node N51at its gate. As such, when charge pump65outputs a potential reset from VPW (for example of 9.7V) to VPP (for example of 5.5V) the node N40potential decreases due to coupling. At node N40, however, there still remains a high potential of external power supply potential EXVDD (for example 1.8V) or more. The ninth stage's pump portion is similar to the tenth stage's pump portion, and node N49is brought to the same high potential as node N50and at node N39there still remains a high potential of external power supply potential EXVDD (for example 1.8V) or more. Initial stages' pump portions do not have high potential applied thereto, and when the charge pump65output potential is reset from VPW (for example of 9.7V) to VPP (for example of 5.5V) the nodes N31, B32, . . . potential decrease due to coupling to be lower than external power supply potential EXVDD (for example of 1.8V).

If in this condition the positive pump circuit13operation is resumed to again generate positive potential VPW (for example of 9.7V) the ninth and tenth pump portions' nodes N39and N40still have a potential higher than external power supply potential EXVDD (for example of 1.8V), and N channel MOS transistors139,140are turned on and there is not rectification effect. In other words, succeeding stages' pump portions cannot pump and the charge pump65pumping ability drops. To prevent such disadvantage, theFIG. 8circuit is provided.

With reference toFIG. 8, reset signal RS is set high and low when the positive pump circuit for internal operation13operates and does not operate, respectively. When reset signal RS has the high level, N channel MOS transistor184turns off and N channel MOS transistor185turns on. In response, output node N62is set low and P channel MOS transistor182turns on. As such, node N61is set high and P channel MOS transistor183turns off, when in response to output node N62having been set low N channel MOS transistors191–200turn off.

When reset signal RS has the low level, N channel MOS transistor184turns on and N channel MOS transistor185turns off. In response, node N61is set low and P channel MOS transistor183turns on. As such, output node N62is set high and P channel MOS transistor182turns off, when in response to output node N62having been set high N channel MOS transistors191–200turn on. As such, nodes N31–N40are reset in potential to external power supply potential EXVDD (for example of 1.8V). As such, if the positive pump circuit13operation is resumed to again generate positive potential VPW (for example of 9.7V), with the ninth and tenth pump portions' nodes N39and N40without a potential higher than external power supply potential EXVDD (for example of 1.8V), the N channel MOS transistors139,140rectification effect has been recovered. In other words, succeeding pump portions' failure to pump can be resolved and charge pump65can be prevented from having an impaired pumping ability.

Then with reference again toFIG. 1the positive pump circuits for internal operation12and13are operated to control the memory portion42bit and word lines BL and WL in potential, as will be described hereinafter.FIG. 10is a timing plot for illustrating how the memory portion42bit and word lines BL and WL vary in potential. With reference to the figure, in a normal operation period a read or similar normal operation is performed. In an internal operation period a programming or similar internal operation is performed. In a preparation period a preparation is made for transitioning from a normal operation state to an internal operation state.

With reference toFIGS. 1,2and10in a normal operation period prior to time t10the positive pump circuit for normal operation11generates positive potential VPP (for example of 5.5V). External application select circuit23selects and outputs potential VPP provided from the positive pump circuit for normal operation11. Select circuit34selects potential VPP output from external application select circuit23and provides the potential to word line driver39. The memory portion42word line WL has its potential brought by word line driver39to VPP. The positive pump circuits for internal operation12,13have been inactivated. Reset circuit29provides an output node of external application select circuit24with potential VPP output from external application select circuit23minus transistor threshold voltage Vth, i.e., a potential VPP−Vth. The memory portion42bit line BL has its potential brought by write circuit38to potential VPP−Vth.

At time t10enable signals EN1–EN4are set to the high level of the activation level. In response to enable signal EN1having been set to the high level of the activation level divider circuit portion3divides clock signal CLK output from clock generation circuit1to output clock signal CLKD. Furthermore in response to enable signals EN2–EN4having been set to the high level of the activation level the positive pump circuits for internal operation12,13are activated. External application select circuit24selects and outputs a potential output from the positive pump circuit for internal operation12. External application select circuit25selects and outputs to write circuit38a potential output from the positive pump circuit for internal operation13. Reset circuits29and30do not perform a reset operation as the positive pump circuits for internal operation12,13are activated. Select circuit34selects a potential output from external application select circuit25and provides the potential to word line driver39. The memory portion42word line WL is provided with the potential output from the positive pump circuit for internal operation13. Furthermore the memory portion42bit line BL is provided with the potential output from the positive pump circuit for internal operation12. From time t10through time t11a preparation is made for transitioning from a normal operation period to an internal operation period.

At time t11the word line WL potential is set by the positive pump circuit for internal operation13to a prescribed potential VPW (for example of 9.7V) and the bit line BL potential is set by the positive pump circuit for internal operation12to a prescribed potential VPB (for example of 5.1V). Furthermore at time t11enable signals EN1and EN4are set to the low level of the inactivation level. In response to enable signal EN1having been set to the low level of the inactivation level divider circuit portion3outputs clock signal CLK, received from clock generation circuit1, as clock signal CLKD, rather than dividing clock signal CLK. This allows an increased drive ability of the positive pump circuit for internal operation12. Furthermore in response to enable signal EN4having been set to the low level of the inactivation level the positive pump circuit for internal operation13clock driver64is inactivated and the positive pump circuit for internal operation13has its drive ability halved.

At time t12enable signals EN2and EN3are set to the low level of the inactivation level. In response the positive pump circuits for internal operation12,13are inactivated. Furthermore select circuit34selects potential VPP output from external application select circuit23and provides the potential to word line driver39. The memory portion42word line WL has its potential brought by word line driver39VPP. Reset circuit29provides the output node of external application select circuit24with potential VPP output from external application select circuit23minus transistor threshold voltage Vth, i.e., a potential VPP−Vth. The memory portion42bit line BL has its potential brought by write circuit38to potential VPP−Vth.

Thus at time t11the positive pump circuits for internal operation12,13has a drive ability switched. After word line WL is raised to the prescribed potential VPW (for example 9.7V) its current consumption is reduced. As such, before time t11the positive pump circuit for internal operation1clock drivers63and64and charge pumps65and66are activated and after t11clock driver63and charge pump65alone are activated. Furthermore, after bit line BL is raised to the prescribed potential VPB (for example of 5.1V) the bit line requires a large write current. Accordingly before time t11divider circuit portion3divides clock signal CLK and by clock signal CLKD of a low frequency the bit line BL potential is gradually raised to the prescribed potential VPB (for example of 5.5V). The clock signal CLKD frequency is reduced to prevent the bit line BL potential from being higher than the prescribed potential VPB. After time t11, clock signal CLK is not divided, and by clock signal CLKD of high frequency the bit line BL potential is held at VPB. As such, a pumping operation is appropriately controlled in accordance with state and the word line WL potential is prevented from rippling. Furthermore, the bit line BL write current's peak value is reduced.

Note that with reference toFIG. 2the positive pump circuit for internal operation12is provided with inverter51in order to provide clock drivers53and54with complementary clock signals. Two charge pumps55and56thus alternately, continuously generate voltage. The positive pump circuit for internal operation13is also similarly provided with inverter61and two charge pumps65and66alternately, continuously generate voltage. As such, pump circuits for internal operation12and13output potentials VPB, VPW with limited ripple.

While the positive pump circuits for internal operation12,13each is provided with two pairs of a clock driver and a charge pump for the sake of illustration, the circuit may be provided with any number of pairs of a clock driver and a charge pump. Different numbers of such pairs allow the pump circuit to have different drive ability.

With reference toFIG. 11the positive pump circuit for normal operation11includes a detection circuit for active time201, a detection circuit for standby202, a clock generation circuit203, a clock driver204and a charge pump205.

The detection circuit for active time201and the detection circuit for standby202are similar in configuration and operation to theFIG. 3detection circuit52. It should be noted, however, that the detection circuit for active time201receives a switch signal /SW set to the low level of the activation level in an active time consuming a large amount of current (or in a state of operation with an internal circuit in operation) and set to the high level of the inactivation level in a standby time consuming a small amount of current (or in a standby state with the internal circuit not in operation).

The detection circuit for active time201operates for switch signal /SW having the low level of the activation level to output to clock generation circuit203a detection signal PEAC based on reference potential VREFS provided from reference potential generation circuit4and potential VPP provided from an output node N71. More specifically, potential VPP having been divided by an internal resistor is compared with reference potential VREFS and if potential VPP is lower than a target level detection signal PEAC is set high. If potential VPP is higher than the target level detection signal PEAC is set low. Furthermore if switch signal /SW has the high level of the inactivation level detection signal PEAC is set high.

The detection circuit for standby202outputs to clock generation circuit203a detection signal PEST based on reference potential VREFS provided from reference potential generation circuit4and potential VPP provided from output node N71. More specifically, potential VPP having been divided by internal resistor is compared with reference potential VREFS and if potential VPP is lower than a target level a detection signal PEST output is set high. If potential VPP is higher than the target level detection signal PEST output is set low.

From detection signals PEAC and PEST output from the detection circuits for active time and standby201and202, respectively, clock generation circuit203generates a clock signal for active time CLKAC, a clock signal for standby CLKST, and a common clock signal CLKAS. For switch signal /SW having the high level, clock generation circuit203operates in response to detection signal PEAC output from detection circuit201to generate clock signal CLKAC and common clock signal CLKAS. For switch signal /SW having the high level, clock generation circuit203operates in response to detection signal PEST output from detection circuit202to generate clock signal CLKST and common clock signal CLKAS.

Clock driver204is similar in configuration and operation to clock drivers53,54,63,64shown inFIG. 2. Clock driver204for switch signal /SW having the low level operates in response to clock signals CLKAC, CLKAS provided from clock generation circuit203to generate 4-phase clock signals φAC1–φAC4and φAS1–φAS4. For switch signals /SW having the high level, clock driver204operates in response to clock signals CLKST, CLKAS output from clock generation circuit203to generate 4-phase clock signals φST4and φAS1–φAS4.

FIG. 12is a circuit diagram showing a configuration of charge pump205, as compared withFIG. 7. TheFIG. 12charge pump205differs from theFIG. 7charge pump65in that: ten stages of pump portions are reduced to seven stages thereof; capacitors171–174are replaced with capacitors211–214; N channel MOS transistors215,216and a capacitor217are additionally introduced; and clock signals φB1–φB4are replaced with clock signals φAC1–φAC4, φAS1–φAS4and φST4.

N channel MOS transistor215is connected between a line of external power supply potential EXVDD and a node N44. N channel MOS transistor215has its gate connected to a node N81. N channel MOS transistor216is connected between a line of external power supply potential EXVDD and node N81. N channel MOS transistor216has its gate connected to node N44. Capacitor214has one electrode receiving clock signal φST4from clock driver204and the other electrode connected to node N81.

Capacitors161,163each have one electrode receiving clock signal φAC4. Capacitor162has one electrode receiving clock signal φAC2. Capacitor211has one electrode receiving clock signal φAC1. Capacitor212has one electrode receiving clock signal φAC3.

Capacitors164,166each have one electrode receiving clock signal φAS2. Capacitors165,167each have one electrode receiving clock signal φAS4. Capacitors213,175each have one electrode receiving clock signal φAS1. Capacitors214,216each have one electrode receiving clock signal φAS3. N channel MOS transistor137has a source outputting potential VPP.

FIG. 13is timing plots for illustrating an operation of the positive pump circuit for normal operation11. In the figure at time t20an active state is switched to a standby state.

A period prior to time t20switch signal /SW is set to the low level of the activation level. In response, clock generation circuit203operates in response to detection signal PEAC of the high level provided from detection circuit201to generate clock signal CLKAC for active state and common clock signal CLKAS. Clock driver204operates in response to clock signals CLKAC, CLKAS to generate clock signal φAC1–φAC4, φAS1–φAS4. Clock signal φST4is set low.

Charge pump205is driven by clock signals φAC1–φAC4, φAS1–φAS4to allow seven stages' pump portions to pump to generate potential VPP. This pumping operation will not specifically be described as it is similar to that of charge pump65shown inFIG. 7.

At time t20switch signal /SW is pulled to the high level of the inactivation level. In response, clock generation circuit203operates in response to detection signal PEST of the high level provided from detection circuit202to generate clock signal CLKST for standby and common clock signal CLKAS. Clock driver204operates in response to clock signals CLKST, CLKAS to generate clock signals φST4, φAS1–φAS4. Clock signals φAC1–φAC4are set low.

Charge pump205is driven by clock signals φST4, φAS1–φAS4to allow five stages' pump portions to pump to generate potential VPP. Thus in an active state the seven stages' pump portions pump and in a standby state five stages' pump portions pump. The number of stages of pump portions operated in the standby state is smaller than that of stages of pump portions operated in the active state. Thus in the standby state the pump circuit consumes a small current.

Conventionally a charge pump for active time and that for standby are separately provided. This results in the semiconductor integrated circuit device, having a major portion in area consumed by a charge pump, requiring an increased layout area for the charge pump. In the present embodiment a charge pump has a pump portion partially (or latter four stages' pump portions) shared as those for active time and standby and between active and standby states the number of stages of pump portions that pump is switched. The charge pump's layout area can thus be reduced.

FIG. 14is a schematic cross section of a configuration of capacitor175shown inFIG. 12. In the figure, capacitor175includes a P substrate221, an N well222, N+regions223,224and a gate (G)225.

P substrate221has a surface with N well222formed thereon. On N well222, N+regions223,224are formed. Over N well22, gate225is formed of a second polysilicon PS2. N+regions223,224receive a potential VSD and gate225receives a potential VG.

Capacitor175thus configured has a thick oxide film formed between N well222and gate225and is suitable when high potentials VSD, VG are applied. Capacitor175has a small capacitance per unit area. Capacitor176has the same configuration as capacitor175. As capacitors175,176corresponding to the fifth and sixth stages' pump portions receive high voltage, capacitors175,176are adapted to have a thick oxide film to withstand high voltage.

FIG. 15is a schematic cross section of a configuration of capacitor211shown inFIG. 12. In the figure, capacitor211includes a P substrate231, an N well232, N+regions233,234, a floating gate (FG)235, and a control gate (CG)236.

P substrate231has a surface with N well232formed thereon. On N well232, N+regions233and234are formed. Over N well232, floating gate235is formed of a first polysilicon PS1. Floating gate235underlies control gate236formed of the second polysilicon. N+regions233,234and control gate236receive a potential VCG and floating gate235receives a potential VFG.

Capacitor211thus configured has a thin oxide film formed between N well232and floating gate235and is suitable when low potential VCG is applied. Capacitor211has a large capacitance per unit area. Capacitors212–214have the same configuration as capacitor211. Thus capacitors211–214corresponding to the first to fourth stages' pump portions do not have high potential applied thereto, and a capacitor having a thick oxide film to withstand high voltage is not required and capacitors211–214having a thin oxide film are used. A smaller layout area of the pump circuit can be achieved than when a highly voltage withstanding capacitor alone is used as conventional.

With reference again toFIG. 1positive, driving pump circuit14is similar in configuration to the positive pump circuits for internal operation12,13and driven by clock signal CLK provided from clock generation circuit1and reference potential VREF provides from reference potential generation circuit2to generate a positive potential VPC (for example of 2.4V).

The negative pump circuits for internal operation15–17, as well as theFIG. 2positive pump circuits for internal operation12,13, include a detection circuit, a clock driver and a charge pump. The negative pump circuit for internal operation15detection circuit and clock driver are similar in configuration and operation to theFIG. 2positive pump circuits for internal operation12and13detection circuits and clock drivers. The negative pump circuit for internal operation15charge pump is, however, different in configuration and operation from theFIG. 2positive pump circuits for internal operation12,13charge pumps.

With reference toFIG. 16the negative pump circuit for internal operation15charge pump includes a level shifter241, diodes251–260, and capacitors261–270.

The negative pump circuit for internal operation15clock driver generates complementary clock signals φNA and /φNA as based on clock signal CLK provided from clock generation circuit1. Level shifter241is driven by potential VPC (for example of 2.4V) provided from positive, driving pump circuit14. Level shifter241converts the clock signal φNA, /φNA voltage level from the external power supply potential EXVDD (for example of 1.8V) level to the potential VPC (for example of 2.4V) level for output.

Diodes251–260are connected in series between an output node N91and a line of ground potential GND. The odd numbered capacitors261–269have their respective one electrodes connected to the odd numbered nodes N91–N99and their respective other electrodes receiving clock signal /φNA from level shifter241. The even numbered capacitors262–270have their respective ones electrodes connected to the even numbered nodes N92–N100and their respective other electrodes receiving clock signal φNA from level shifter241. Output node N91outputs a potential VNA (for example of −9.2V). The diode's threshold voltage will be represented by Vdio.

When clock signal φNA is set high (VPC) diode260conducts and the node N100potential is brought to the ground potential (0V) plus the diode260threshold voltage Vdio, i.e., a potential Vdio. Subsequently, clock signal φNA is set low (0V) and in response the node N100potential drops to Vdio−VPC. As clock signal /φNA has been set high (VPC), diode259conducts and the node N99potential attains the node N100potential plus the diode259threshold voltage Vdio, i.e., a potential 2Vdio−VPC. Subsequently, clock signal /φNA is pulled low (0V) and in response the node N99potential drops to 2(Vdio−VPC).

Thus nodes N100–N91drops in potential by Vdio−VPC and the output node N91potential VNA attains10(Vdio−VPC). For example if diode threshold voltage Vdio is 1.5V and positive, driving pump circuit14provides potential VPC of 2.4V then potential VNA=10(1.5−2.4)=−9V.

Conventional semiconductor integrated circuit devices are not provided with positive, driving pump circuit14, and the negative pump circuit for internal operation15is driven by external power supply potential EXVDD (for example of 1.8V). In that case, clock signal φNA, /φNA has a level in voltage of external power supply potential EXVDD (for example of 1.4V), and potential VNA generated will be 10(Vdio−EXVDD). For example, if diode threshold voltage Vdio is 1.5V and external power supply potential EXVDD is 1.8V then potential VNA=10(1.5−1.8)=−3V. Accordingly to generate potential VNA of −9V the number of diodes needs to be tripled, i.e., 30 diodes are required, which invites an increased layout area of the pump circuit.

In the present embodiment, by contrast, positive, driving pump circuit14is provided and the negative pump circuit for internal operation15is driven with potential VPC (for example of 2.4V). A reduced number of stages of pump is required and a reduced area of the negative pump circuit for internal operation15is achieved.

Note that while the positive pump circuit for normal operation11and the positive pump circuits for internal operation12,13employ N channel MOS transistor for a charge pump, the negative pump circuit for internal operation15employs a polysilicon diode. For an N channel MOS transistor, a triple N well configuration can separate a backgate. As such, backgate potential can be set as desired. For a P channel MOS transistor, however, some fabrication process would force a backgate to be fixed at a P substrate's potential (or ground potential GND). As such, if a deep negative potential VNA (for example of −9.2V) is generated, the P channel MOS transistor's source and drain and the P substrate would have a difference in potential exceeding a junction withstand voltage. (This is referred to as backgate effect.) Accordingly the P channel MOS transistor is not used and a polysilicon diode is instead used as a rectifier.

With reference toFIG. 17, the negative pump circuit for internal operation16charge pump includes a level shifter271, P channel MOS transistors281–285and capacitors291–294.

The negative pump circuit for internal operation16clock driver generates 4-phase clock signals φNB1–/φNB4as based on clock signal CLK provided from clock generation circuit1. Level shifter271is driven by potential VPC (for example of 2.4V) provided from positive, driving pump circuit14. Level shifter241converts the clock signal φNB2, /φNB4voltage level from the external power supply potential EXVDD (for example of 1.8V) level to the potential VPC (for example of 2.4V) level for output.

P channel MOS transistors281,282are connected in series between a line of ground potential GND and a node N105. P channel MOS transistors281,282have their respective gates connected to nodes N101, N102, respectively. P channel MOS transistors283,284are connected between nodes N103, N104and nodes N201, N102, respectively. P channel MOS transistors283,284have their respective gates connected to nodes N104, N105, respectively. P channel MOS transistor285has its drain and gate connected to node N105to configure a diode. P channel MOS transistors281–285have their backgates each connected to a line of ground potential GND. P channel MOS transistor285has a source outputting potential VNB (−0.5V).

Capacitor291has one electrode receiving clock signal φNB2from level shifter271and the other electrode connected to node N101. Capacitor292has one electrode receiving clock signal φNB4from level shifter271and the other electrode connected to node N102. Capacitor293has one electrode receiving clock signal φNB3from a clock driver and the other electrode connected to node N104. Capacitor294has one electrode receiving clock signal φNB1from clock driver and the other electrode connected to node N105.

The negative pump circuit for internal operation16is similar in operation to charge pump65of the positive pump circuit for internal operation13shown inFIG. 17. It should be noted, however, that an N channel MOS transistor is replaced with a P channel MOS transistor and node N103is connected to a line of ground potential GND, and accordingly nodes N104, N105are lower in potential than 0V. Consequently, the pumping operation generates negative potential VNB (for example of −0.5V). A smaller number of stages of pump is required than when positive, driving pump circuit14is not provided as conventional, and a smaller area of the negative pump circuit for internal operation16is achieved.

With reference again toFIG. 1the negative pump circuit17charge pump is similar in configuration and operation to the negative pump circuit16charge pump. Note that a programming operation is defined to be shorter in period than an erasure operation, and the negative pump circuit for internal operation17generating negative potential VNC (for example of −0.9V) required in the programming operation for a well is required to have a large driving ability. A polysilicon diode has a small current driving ability per unit area. As such, for a pump circuit generating a shallow negative potential VNC (for example of −0.9V) allowing a junction withstand voltage to be negligible, a P channel MOS transistor is better used as the rectifier as the pump circuit's layout area can be reduced. Note that the P channel MOS transistor's P substrate has a potential of a level of ground potential GND and due to the backgate effect the P channel MOS transistor's threshold voltage is slightly increased. In the present embodiment, however, positive, driving pump circuit14is provided and the negative pump circuit for internal operation17is driven by potential VPC (for example of 2.4V) provided from positive, driving pump circuit14so that the P channel MOS transistor's threshold voltage slightly increased does not negatively affect on operation.

Furthermore, although positive, driving pump circuit14contributes to an increased area therefor, a reduced area associated with the negative pump circuits for internal operation15–17is larger in degree than the increased area for positive, driving pump circuit14. As a result, the semiconductor integrated circuit device is generally reduced in area. Note that the negative pump circuits for internal operation15–17do not operate simultaneously, and a single, positive, driving pump circuit14can be shared.

With reference toFIG. 18, external application select circuit25includes inverters331and333–336, a buffer circuit332, P channel MOS transistors341–348and458–359, and N channel MOS transistors361–367.

P channel MOS transistors341,342and N channel MOS transistor361are connected in series between input terminal21and a line of ground potential GND. P channel MOS transistor341has its gate connected to a node N122and P channel MOS transistor341has its gate receiving potential VPP (for example of 5.5V). N channel MOS transistor361has its gate receiving a select signal SELR via inverter331. P channel MOS transistors343,344and N channel MOS transistor362are connected in series between input terminal21and a line of ground potential GND. P channel MOS transistor343has its gate connected to a node N121and P channel MOS transistor344has its gate receiving potential VPP (for example of 5.5V). N channel MOS transistor362has its gate receiving select signal SELR via inverters333,331. P channel MOS transistors345,346and N channel MOS transistor363are connected in series between input terminal21and a line of ground potential GND. P and N channel MOS transistors345and363, respectively, have their gates connected to node N121. P channel MOS transistor346has its gate receiving potential VPP (for example of 5.5V). P channel MOS transistors347,348and N channel MOS transistor364are connected in series between input terminal21and a line of ground potential GND. P channel MOS transistor347has its gate connected to a node N123and P channel MOS transistor348has its gate receiving potential VPP (for example of 5.5V). N channel MOS transistor364has its gate receiving select signal SELR via inverter334.

Buffer circuit332is driven by potential VPP (for example of 5.5V) and outputs select signal SELR having a level in voltage converted from the external power supply potential EXVDD (for example 1.8V) level to the potential VPP (for example of 5.5V) level, i.e., a signal SELS. Inverter336is driven by a potential of an output node N128and has an input terminal receiving select signal SELR via inverter331and an output terminal connected to P channel MOS transistor359at the gate. P channel MOS transistor359is connected between an output node of the positive pump circuit for internal operation13and output node N128.

P channel MOS transistors351,352are connected in series between output node N128and an node N124. P channel MOS transistor351has its gate connected to a node N125and P channel MOS transistor352has its gate receiving signal SELS output from buffer circuit332. P channel MOS transistors353,354and N channel MOS transistor365are connected in series between output node N128and a line of ground potential GND. P and N channel MOS transistors353and365, respectively, have their gates connected to a node N127. P channel MOS transistor354has its gate receiving signal SELS output from buffer circuit332. P channel MOS transistors355,356and N channel MOS transistor366are connected in series between output node N128and a line of ground potential GND. P channel MOS transistor355has its gate connected to node N127and P channel MOS transistor356has its gate receiving signal SELS output from buffer circuit332. N channel MOS transistor366has its gate receiving select signal SELR via inverters335,331. P channel MOS transistors357,358and N channel MOS transistor367are connected in series between output node N128and a line of ground potential GND. P channel MOS transistor357has its gate connected to a node N126and P channel MOS transistor358has its gate receiving signal SELS output from buffer circuit332. N channel MOS transistor367has its gate receiving select signal SELR via inverter331.

FIG. 19is a simplified circuit block diagram corresponding to theFIG. 18external application select circuit25. An application of theFIG. 19circuit configuration is theFIG. 18external application select circuit25. InFIG. 19, select signals SELP, SELQ are signals having a potential amplitude in a range from 0V to external power supply potential EXVDD (for example of 1.8V). A select circuit371for select signal SELP having the high level selects potential VPP (for example of 5.5V) received from the positive pump circuit for normal operation11via reset circuit30and for select signal SELP having the low level selects an external potential VEX (for example of 10V) provided from input terminal21and outputs the selected potential as VP. An inverter372is driven by potential VPP (for example of 5.5V) provided from the positive pump circuit for normal operation11. Inverter372inverts the logic level of select signal SELP and also converts the voltage level from the external power supply potential EXVDD (for example of 1.8V) level to the potential VPP (for example of 5.5V) level for output.

P channel MOS transistors381,382are connected in series between an output node of select circuit371and a node N131. P channel MOS transistor381has its gate connected to an output node N132. P channel MOS transistor382has its gate connected to an output node of inverter372. P channel MOS transistors383,384are connected in series between the output node of select circuit371and node N132. P channel MOS transistor383has its gate connected to node N131. P channel MOS transistor384has its gate connected to the output node of inverter372. P channel MOS transistors382,384are provided to reduce a difference in potential between the P channel MOS transistors381,383source and drain to prevent P channel MOS transistors381,383from degradation.

N channel MOS transistor385is connected between node N131and a line of ground potential GND. N channel MOS transistor385has its gate receiving select signal SELQ. N channel MOS transistor386is connected between output node N132and a line of ground potential GND. N channel MOS transistor386has its gate receiving select signal SELQ via inverter373.

FIG. 20is timing plots for illustrating an operation of theFIG. 19circuit. At time t30, select circuit371operates in response to select signal SELP of the high level to select and output potential VPP. Furthermore, in response to select signal SELQ having been pulled high, N channel MOS transistor385turns on and N channel MOS transistor386turns off. In response, node N131is pulled low and P channel MOS transistor383turns on. Inverter372receives select signal SELP of the high level and outputs a signal of the low level (0V). P channel MOS transistors382,384turn on in response to a signal of the low level provided from inverter372. Node NA is brought to the P channel MOS transistor382gate voltage level (0V) plus the P channel MOS transistor382threshold voltage Vth, i.e., a potential Vth, and output node N132is set high (VPP). P channel MOS transistor381turns off.

At time t31, select signal SELQ is pulled low. In response, N channel MOS transistor385turns off and N channel MOS transistor386turns on. This pulls output node N132low (0V) and turns on P channel MOS transistor381. In response, nodes NA, N131are pulled high (VPP). P channel MOS transistor383turns off.

At time t32, select signal SELP is pulled low. In response, select circuit371selects and outputs potential VEX. This increases node NA in potential to VEX.

At time t33, select signal SELQ is pulled high. In response, N channel MOS transistor385turns on and N channel MOS transistor386turns off. This pulls node N131low and turns on P channel MOS transistor383. P channel MOS transistor384has its gate receiving potential VPP (for example of 5.5V) and its drain receiving potential VEX (for example of 10V), and the transistor thus turns on. In response, output node N132is pulled high (VEX). This turns off P channel MOS transistor381and brings the node NA potential to a potential of the high level (VPP) provided from inverter372plus the P channel MOS transistor382threshold voltage Vth, i.e., a voltage VPP+Vth.

At time t34, select signal SELQ is pulled low. In response, N channel MOS transistor385turns off and N channel MOS transistor386turns on. This pulls output node N132low (0V) and turns on P channel MOS transistor381. In response, node NA is pulled high (VEX). P channel MOS transistor382has its gate receiving potential VPP (for example of 5.5V) and its drain receiving potential VEX (for example of 10V), and the transistor thus turns on. This sets node N131high and turns off P channel MOS transistor383.

Conventional external application select circuits are not provided with inverter372and the P channel MOS transistors382,384gates receive external power supply potential EXVDD (for example 1.8V). In that case at a time immediately before time t34, at which P channel MOS transistor381turns on, there is a large difference in potential between the P channel MOS transistor381source (or the output node of select circuit371) and drain (or node NA). More specifically at time t33select signal SELQ is pulled high and in response N channel MOS transistor385turns on and N channel MOS transistor386turns off This pulls node N131low and turns on P channel MOS transistor383. P channel MOS transistor384has its gate receiving potential EXVDD (for example 1.8V) and has its drain receiving potential VEX (for example of 10V), and the transistor thus turns on. In response, output node N132is pulled high (VEX). This turns off P channel MOS transistor381and brings the node NA potential to the P channel MOS transistor382gate voltage level (EXVDD) plus the P channel MOS transistor382threshold voltage Vth, i.e., a potential EXVDD+Vth. At time t34select signal SELQ is pulled low and in response N channel MOS transistor386turns on and N channel MOS transistor385turns off. This pulls output node N132low and turns on P channel MOS transistor381.

As such at the time immediately before time t34, at which P channel MOS transistor381turns on, the P channel MOS transistor381source (or the output node of select circuit371) and drain (or node NA) will have therebetween a difference in potential of VEX−(EXVDD+Vth). For example if external power supply potential EXVDD is 1.8V and external potential VEX is 10V the P channel MOS transistor381source (or the output node of select circuit371) and drain (or node NA) have therebetween a difference in potential of 8.2−Vth. Thus at a time immediately before P channel MOS transistor381turns on the transistor's source (or the output node of select circuit371) and drain (or node NA) have therebetween a difference in potential exceeding a voltage withstanding level, resulting in a degraded P channel MOS transistor in some cases.

In the present embodiment, by contrast, P channel MOS transistors382,384have their gates receiving a signal output from inverter372driven by potential VPP (for example of 5.5V). This allows a difference in potential of VEX−(EXVDD+Vth) between the P channel MOS transistor381source (or the output node of select circuit371) and drain (or node NA) at a time immediately before time t34, at which P channel MOS transistor381turns on, as shown inFIG. 20. For example if potential VPP is 5.5V and external potential VEX is 10V the P channel MOS transistor381source (the output node of select circuit371) and drain (or node NA) have therebetween a difference in potential of 4.5V−Vth. As such at a time immediately before P channel MOS transistor381turns on the P channel MOS transistor381source (or the output node of select circuit371) and drain (or node NA) have therebetween a reduced difference in potential. Thus at a time immediately before a P channel MOS transistor turns on the P channel MOS transistor's source and drain have a difference in potential limited to be lower than a voltage withstanding level to prevent P channel MOS transistor from degradation.

With reference again toFIG. 18external application select circuit25operates as will be described hereinafter. With reference toFIG. 21, external application select circuit25at a main portion321, in particular, operates as will be described hereinafter. Note that the external application select circuit25output potential is not switched directly from potential VPW (from the positive pump circuit for internal operation13) to external potential VEX (from input terminal21) but once brought to potential VPP (from the positive pump circuit for normal operation11), since when the positive pump circuit for internal operation13is inactivated, reset circuit30provides the external application select circuit23output potential (VPP) to an output node of external application select circuit25. Hereinafter the external application select circuit25output potential is switched between potential VPP and external potential VEX in an operation, in particular, as will be described hereinafter.

In a period prior to time t40, in response to select signal SELR of the low level (0V) N channel MOS transistor366turns off and N channel MOS transistor367turns on. This sets node N127low and turns on P channel MOS transistor355. Buffer circuit332operates in response to select signal SELR of the low level to output signal SELS of the low level. P channel MOS transistor356turns on in response to signal SELS of the low level. This sets node N126high and turns off P channel MOS transistor357. Potential VPP (for example of 5.5V) from reset circuit30is transmitted via P channel MOS transistor355to node NB and the node NB potential is brought to VPP. Note that at that time, external VEX provided from input terminal21is not transmitted to output node N128, and output node N128is receiving potential VPP from reset circuit30.

At time t40, select signal SELR is pulled high (EXVDD). In response, N channel MOS transistor366turns on and N channel MOS transistor367turns off. This sets node N126low and turns on P channel MOS transistor357. Buffer circuit332operates in response to select signal SELR of the high level (EXVDD) to output signal SELS of the high level (VPP). P channel MOS transistor358has its gate receiving potential VPP (for example of 5.5V) and its drain receiving potential VEX (for example 10V), and the transistor thus turns on. This pulls node N127high and turns off P channel MOS transistor355. The node NB potential is brought to potential VPP (for example of 5.5V) received by P channel MOS transistor356at the gate plus the P channel MOS transistor356threshold voltage Vth, i.e., a potential VPB+Vth. Output node N128receives external potential VEX from input terminal21.

At time t41, select signal SELR is pulled low (0V). In response, N channel MOS transistor367turns on and N channel MOS transistor366turns off. This pulls node N127low and turns on P channel MOS transistor355. Buffer circuit332operates in response to select signal SELR of the low level (0V) to output select signal SELS of the low level (0V). P channel MOS transistor356has its gate receiving select signal SELS of the low level (0V) and its drain receiving potential VPP+Vth, and the transistor thus turns on. This pulls node N126high and turns off P channel MOS transistor357. The node NB potential is brought to VPP. Note that external potential VEX provided from input terminal21is not transmitted to output node N128, and output node N128is receiving potential VPP from reset circuit30.

Conventionally, P channel MOS transistors342,344,346,348,352,354,356,358have their gates connected to line of external power supply potential EXVDD (for example 1.8V). In that case from time t40through time t41the node NB potential is brought to potential EXVDD (for example of 1.8V) received by P channel MOS transistor356at the gate plus the P channel MOS transistor356threshold voltage Vth, i.e., a potential EXVDD+Vth.

At time t41, select signal SELR is pulled low (0V). In response, N channel MOS transistor367turns on and N channel MOS transistor366turns off. This pulls node N127low and turns on P channel MOS transistor355.

As such at the time immediately before time t41, at which P channel MOS transistor355turns on, the P channel MOS transistor355source (or output node N128) and drain (or node NB) will have therebetween a difference in potential of VEX−(EXVDD+Vth). For example if external power supply potential EXVDD is 1.8V and potential VEX is 10V the P channel MOS transistor355source (or output node N128) and drain (or node NB) have therebetween a difference in potential of 8.2−Vth. Thus at a time immediately before P channel MOS transistor355turns on the transistor's source (or output node N128) and drain (or node NB) have therebetween a difference in potential exceeding a voltage withstanding level, resulting in a degraded P channel MOS transistor in some cases. This is influenced by reduction in voltage of external power supply voltage EXVDD.

Accordingly in the present embodiment P channel MOS transistors342,344,346,348have their gates receiving potential VPP (for example of 5.5V) from the positive pump circuit for normal operation11and P channel MOS transistors352,354,356,358have their gates receiving a signal output from buffer circuit322driven by potential VPP (for example of 5.5V). Thus, potential VPP (for example of 5.5V) higher than external power supply potential EXVDD (for example 1.8V) and constantly generated from the positive pump circuit for normal operation11is utilized. It should be noted, however, that when the output node N128potential is brought to VPP, P channel MOS transistors352,354,356,358need to have their gates brought in potential to be lower than VPP. Accordingly, select signal SELR is employed to switch a level in voltage of a signal output from buffer circuit332.

Thus, as shown inFIG. 21, at a time immediately before time t41, at which P channel MOS transistor355turns on, the P channel MOS transistor355source (or output node N128) and drain (or node NB) have therebetween a difference in potential of VEX−(VPP+Vth). For example if potential VPP is 5.5V and external potential VEX is 10V the P channel MOS transistor355source and drain have therebetween a difference in potential of 4.5V−Vth. As such at a time immediately before P channel MOS transistor355turns on the P channel MOS transistor355source (or output node N128) and drain (or node NB) have therebetween a reduced difference in potential. Thus at a time immediately before a P channel MOS transistor turns on the P channel MOS transistor's source and drain have a difference in potential limited to be lower than a voltage withstanding level to prevent P channel MOS transistor from degradation.

Note that with reference again toFIG. 1, external application select circuits23,24,26–28are similar in configuration and operation to external application select circuit25. As such, a similar effect can also be obtained for external application select circuits23,24,26–28.

Hereinafter first to fourth exemplary variations of the embodiment will be described. The first exemplary variation is shown inFIG. 22, in which theFIG. 19inverter372is replaced with an inverter391. InFIG. 22, inverter391has a power supply terminal receiving potential VPP (for example of 5.5V) and a ground terminal receiving potential EXVDD (for example of 1.8V). Inverter391for select signal SELP having the high level (EXVDD) outputs a signal of the low level (EXVDD) and for select signal SELP having the low level (0V) outputs a signal of the high level (VPP).

TheFIG. 22circuit is similar in operation to theFIG. 19circuit except that, with reference to theFIG. 20timing plots, the node NA potential is brought to a potential EXVDD+Vth in a period from time t30through time t31.

Thus in the first exemplary variation at a time immediately before P channel MOS transistor381turns on the P channel MOS transistor381source (or the output node of select circuit371) and drain (or node NA) have therebetween a reduced difference in potential. Thus at a time immediately before a P channel MOS transistor turns on the P channel MOS transistor's source and drain have a difference in potential limited to be lower than a voltage withstanding level to prevent P channel MOS transistor from degradation.

Note that by applying theFIG. 22circuit configuration to theFIG. 1external application select circuits23–28, external application select circuits23–28can be prevented from having an impaired P channel MOS transistor.

The second exemplary variation is shown inFIG. 23, in which theFIG. 22Pchannel MOS transistors382,384are removed and N channel MOS transistors401,42are additionally introduced. With reference toFIG. 22, N channel MOS transistor401is connected between node NA and the N channel MOS transistor385drain. N channel MOS transistor402is connected between output node132and the N channel MOS transistor386drain. N channel MOS transistors401,402have their gates receiving a signal output from inverter391.

Thus in the second exemplary variation at a time immediately before N channel MOS transistors385,386turn on the transistors' source and drain have therebetween a reduced difference in potential. Thus at a time immediately before an N channel MOS transistor turns on the transistor's source and drain has a difference in potential limited to be lower than a voltage withstanding level to prevent N channel MOS transistor from degradation.

Note that by applying theFIG. 23circuit configuration to theFIG. 1external application select circuits23–28, external application select circuits23–28can be prevented from having an impaired N channel MOS transistor.

The third exemplary variation is shown inFIG. 24, in which theFIG. 23inverter391and N channel MOS transistors401,402are additionally introduced in theFIG. 19circuit. Thus in the third exemplary variation at a time immediately before P channel MOS transistors381,383turn on the transistors' source and drain have therebetween a reduced difference in potential. Thus at a time immediately before a P channel MOS transistor turns on the transistor's source and drain have a difference in potential limited to be lower than a voltage withstanding level to prevent P channel MOS transistor from degradation.

Furthermore at a time immediately before N channel MOS transistors385,386turn on the transistors' source and drain have therebetween a reduced difference in potential. Thus at a time immediately before an N channel MOS transistor turns on the transistor's source and drain have a difference in potential limited to be lower than a voltage withstanding level to prevent N channel MOS transistor from degradation.

Note that by applying theFIG. 23circuit configuration to theFIG. 1external application select circuits23–28, external application select circuits23–28can be prevented from having impaired P and N channel MOS transistors.

The fourth exemplary variation is shown inFIG. 25, in which theFIG. 24inverter371is removed. With reference toFIG. 25, P channel MOS transistors382,384and N channel MOS transistors401,402have their gates all receiving signal output from inverter391.

Thus in the fourth exemplary variation at a time immediately before P channel MOS transistors381,383turn on the transistors' source and drain have therebetween a reduced difference in potential. Thus at a time immediately before a P channel MOS transistor turns on the transistor's source and drain have a difference in potential limited to be lower than a voltage withstanding level to prevent P channel MOS transistor from degradation.

Furthermore at a time immediately before N channel MOS transistors385,386turn on the transistors' source and drain have therebetween a reduced difference in potential. Thus at a time immediately before an N channel MOS transistor turns on the transistor's source and drain have a difference in potential limited to be lower than a voltage withstanding level to prevent N channel MOS transistor from degradation.

Note that by applying theFIG. 23circuit configuration to theFIG. 1external application select circuits23–28, external application select circuits23–28can be prevented from having impaired P and N channel MOS transistors.