Thin film transistor array substrate and display panel

The invention provides a thin film transistor (TFT) array substrate and a display panel. The TFT array substrate is disposed with multiple pixels arranged in an array. Each pixel includes first through third sub-pixels sequentially arranged along a first direction. The first through third sub-pixels are connected to a same scan line. The TFT array substrate further is disposed with first through third data lines sequentially arranged along the first direction. The first through third data lines respectively are for driving the first through third sub-pixels. The first sub-pixel includes first and second areas, the second sub-pixel includes third and fourth areas, and the third sub-pixel includes fifth and sixth areas, arranged along a second direction. A voltage difference between a sub-pixel electrode in the sixth area and a common electrode is different from a voltage difference between a sub-pixel electrode in the fifth area and the common electrode.

CROSS REFERENCE TO RELATED APPLICATION

This application claims the priority of Chinese Patent Application No. 201410854643.2, entitled “Thin Film Transistor Array Substrate and Display Panel”, filed on Dec. 31, 2014, the disclosure of which is incorporated herein by reference in its entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to the field of display technology, and particularly to a thin film transistor array substrate and a display panel.

2. Description of Related Art

The liquid crystal display (LCD) is a commonly used electronic device, and because of its low power consumption, small size, light weight and other characteristics, it is quite popular for users. Current liquid crystal displays mainly are thin film transistor (TFT) liquid crystal displays. With the development of flat panel display technology, the demand for liquid crystal display with wide viewing angle has been proposed. However, the conventional wide viewing angle liquid crystal display panel usually produces the color shift problem when being observed in large viewing angle. Therefore, in the prior art, the liquid crystal display panel when being observed in large viewing angle would produce technical problems such as color shift.

SUMMARY OF THE INVENTION

The invention provides a thin film transistor array substrate. The thin film transistor array substrate is disposed with a plurality of pixels arranged in an array. Each of the plurality of pixels includes a first sub-pixel, a second sub-pixel and a third sub-pixel sequentially arranged along a first direction, the first sub-pixel, the second sub-pixel and the third sub-pixel are connected to a same scan line. The thin film transistor array substrate further is disposed with a first data line, a second data line and a third data line sequentially arranged along the first direction, the first data line is configured for driving the first sub-pixel, the second data line is configured for driving the second sub-pixel, the third data line is configured for driving the third sub-pixel. The first sub-pixel includes a first area and a second area arranged along a second direction. The second sub-pixel includes a third area and a fourth area arranged along the second direction. The third sub-pixel includes a fifth area and a sixth area arranged along the second direction. A voltage difference between a sub-pixel electrode in the sixth area and a common electrode is different from a voltage difference between a sub-pixel electrode in the fifth area and the common electrode.

In an embodiment, the first area has a first thin film transistor disposed therein, the second area has a second thin film transistor disposed therein, the third area has a third thin film transistor disposed therein, the fourth area has a fourth thin film transistor disposed therein, the fifth area has a fifth thin film transistor disposed therein, the sixth area has a sixth thin film transistor and a seventh thin film transistor disposed therein; gates of the first thin film transistor, the second thin film transistor, the third thin film transistor, the fourth thin film transistor, the fifth thin film transistor, the sixth thin film transistor and the seventh thin film transistor are connected to the same scan line, drains of the first thin film transistor and the second thin film transistor are connected to the first data line, a source of the first thin film transistor sequentially connects a first main sub-pixel electrode and a first capacitor to the common electrode, a source of the second thin film transistor sequentially connects a first subsidiary sub-pixel electrode and a second capacitor to the common electrode, drains of the third thin film transistor and fourth thin film transistor are connected to the second data line, a source of the third thin film transistor sequentially connects a second main sub-pixel electrode and a third capacitor to the common electrode, a source of the fourth thin film transistor sequentially connects a second subsidiary sub-pixel electrode and a fourth capacitor to the common electrode, drains of the fifth thin film transistor and the sixth thin film transistor are connected to the third data line, a source of the fifth thin film transistor sequentially connects a third main sub-pixel electrode and a fifth capacitor to the common electrode, a source of the sixth thin film transistor sequentially connects a third subsidiary sub-pixel electrode and a sixth capacitor to the common electrode, a drain of the seventh thin film transistor is connected to the third subsidiary sub-pixel electrode, and a source of the seventh thin film transistor is connected to the common electrode.

In an embodiment, a voltage difference between a sub-pixel electrode in the fourth area and the common electrode is different from a voltage difference between a sub-pixel electrode in the third area and the common electrode.

In an embodiment, the four area has an eighth thin film transistor disposed therein, a gate of the eighth thin film transistor is connected to the scan line, a drain of the eighth thin film transistor is connected to a second subsidiary sub-pixel electrode, and a source of the eighth thin film transistor is connected to the common electrode.

In an embodiment, the thin film transistor array substrate further is disposed with a fourth data line, the third data line is configured for driving the fifth area of the third sub-pixel, the fourth data line is configured for the sixth area of the third sub-pixel, a driving voltage applied onto the third data line is different from a driving voltage applied onto the fourth data line.

In an embodiment, the first area has a first thin film transistor disposed therein, the second area has a second thin film transistor disposed therein, the third area has a third thin film transistor disposed therein, the fourth area has a fourth thin film transistor disposed therein, the fifth area has a fifth thin film transistor disposed therein, and the sixth area has a sixth thin film transistor disposed therein; gates of the first thin film transistor, the second thin film transistor, the third thin film transistor, the fourth thin film transistor, the fifth thin film transistor and the sixth thin film transistor are connected to the same scan line, drains of the first thin film transistor and the second thin film transistor are connected to the first data line, a source of the first thin film transistor sequentially connects a first main sub-pixel electrode and a first capacitor to the common electrode, a source of the second thin film transistor sequentially connects a first subsidiary sub-pixel electrode and a second capacitor to the common electrode; drains of the third thin film transistor and the fourth thin film transistor are connected to the second data line, a source of the third thin film transistor sequentially connects a second main sub-pixel electrode and a third capacitor to the common electrode, a source of the fourth thin film transistor sequentially connects a second subsidiary sub-pixel electrode and a fourth capacitor to the common electrode; a drain of the fifth thin film transistor is connected to the third data line, a source of the fifth thin film transistor sequentially connects a third main sub-pixel electrode and a fifth capacitor to the common electrode, a drain of the sixth thin film transistor is connected to the fourth data line, a source of the sixth thin film transistor sequentially connects a third subsidiary sub-pixel electrode and a sixth capacitor to the common electrode.

In an embodiment, the thin film transistor array substrate further is disposed with a fifth data line, the second data line is configured for driving the third area of the second sub-pixel, the fifth data line is configured for driving the fourth area of the second sub-pixel, a driving voltage applied onto the second data line is different from a driving voltage applied onto the fifth data line.

In an embodiment, the first area has a first thin film transistor disposed therein, the second area has a second thin film transistor disposed therein, the third area has a third thin film transistor disposed therein, the fourth area has a fourth thin film transistor disposed therein, the fifth area has a fifth thin film transistor disposed therein, and the sixth area has a sixth thin film transistor disposed therein; gates of the first thin film transistor, the second thin film transistor, the third thin film transistor, the fourth thin film transistor, the fifth thin film transistor and the sixth thin film transistor are connected to the same scan line, drains of the first thin film transistor and the second thin film transistor are connected to the first data line, a source of the first thin film transistor sequentially connects a first main sub-pixel electrode and a first capacitor to the common electrode, a source of the second thin film transistor sequentially connects a first subsidiary sub-pixel electrode and a second capacitor to the common electrode; a source of the third thin film transistor sequentially connects a second main sub-pixel electrode and a third capacitor to the common electrode, a drain of the third thin film transistor is connected to the second data line, a source of the fourth thin film transistor sequentially connects a second subsidiary sub-pixel electrode and a fourth capacitor to the common electrode, a drain of the fourth thin film transistor is connected to the fifth data line; a drain of the fifth thin film transistor is connected to the third data line, a source of the fifth thin film transistor sequentially connects a third main sub-pixel electrode and a fifth capacitor to the common electrode, a drain of the sixth thin film transistor is connected to the fourth data line, and a source of the sixth thin film transistor sequentially connects a third subsidiary sub-pixel electrode and a sixth capacitor to the common electrode.

In an embodiment, the first sub-pixel is a red sub-pixel, the second sub-pixel is a green sub-pixel, and the third sub-pixel is a blue sub-pixel.

The invention further provides a display panel. The display panel includes any one of the thin film transistor array substrates associated with the above various embodiments.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

In the following, with reference to accompanying drawings of embodiments of the invention, technical solutions in the embodiments of the invention will be clearly and completely described. Apparently, the embodiments of the invention described below only are a part of embodiments of the invention, but not all embodiments. Based on the described embodiments of the invention, all other embodiments obtained by ordinary skill in the art without creative effort belong to the scope of protection of the invention.

Please refer toFIG. 1andFIG. 2,FIG. 1is a schematic view of a thin film transistor array substrate according to a first preferred embodiment of the invention, andFIG. 2is a structural schematic view of a pixel in the thin film transistor array substrate according to the first preferred embodiment of the invention. The thin film transistor array substrate10is disposed with a plurality of pixels100arranged in an array. Each pixel100includes a first sub-pixel110, a second sub-pixel120and a third sub-pixel130arranged along a first direction. The first sub-pixel110, the second sub-pixel120and the third sub-pixel130are connected to a same scan line GL. The thin film transistor array substrate10further is disposed with a first data line D1, a second data line D2and a third data line D3sequentially arranged along the first direction. The first data line D1is configured (i.e., structured and arranged) for driving the first sub-pixel110, the second data line D2is configured for driving the second sub-pixel120, and the third data line D3is configured for driving the third sub-pixel130. The first sub-pixel110includes a first area111and a second area112arranged along a second direction, the second sub-pixel120includes a third area121and a fourth area122arranged along the second direction, the third sub-pixel130includes a fifth area131and a sixth area132arranged along the second direction. A voltage difference between a sub-pixel electrode in the sixth area132and a common electrode is different from a voltage difference between a sub-pixel electrode in the fifth area131and the common electrode. In this embodiment, the first direction is the horizontal direction, and the second direction is the vertical direction.

The first area111has a first thin film transistor Q1disposed therein, the second area112has a second thin film transistor Q2disposed therein, the third area121has a third thin film transistor Q3disposed therein, the fourth area122has a fourth thin film transistor Q4disposed therein, the fifth area131has a fifth thin film transistor Q5disposed therein, the sixth area132has a sixth thin film transistor Q6and a seventh thin film transistor Q7disposed therein. The first thin film transistor Q1, the second thin film transistor Q2, the third thin film transistor Q3, the fourth thin film transistor Q4, the fifth thin film transistor Q5, the sixth thin film transistor Q6and the seventh thin film transistor Q7each include a gate, a source and a drain. The first area111, the second area112, the third area121, the fourth area122, the fifth area131and the sixth area132each are corresponding to one sub-pixel electrode disposed therein. For the convenience of description, the corresponding sub-pixel electrode in the first area111is named as first main sub-pixel electrode113, the corresponding sub-pixel electrode in the second area112is named as first subsidiary sub-pixel electrode114, the corresponding sub-pixel electrode in the third area121is named as second main sub-pixel electrode123, the corresponding sub-pixel electrode in the fourth area122is named as second subsidiary sub-pixel electrode124, the corresponding sub-pixel electrode in the fifth area131is named as third main sub-pixel electrode133, and the corresponding sub-pixel electrode in the sixth area132is named as third subsidiary sub-pixel electrode134. It should be understood to those skilled in the art that, the names of the corresponding sub-pixel electrodes of the above various areas only are to distinguish the sub-pixels in different areas and for the convenience of description, and thus actually have no distinction of main and subsidiary.

The gates of the first thin film transistor Q1, the second thin film transistor Q2, the third thin film transistor Q3, the fourth thin film transistor Q4, the fifth thin film transistor Q5, the sixth thin film transistor Q6and the seventh thin film transistor Q7are connected to the same scan line GL. The drains of the first thin film transistor Q1and the second thin film transistor Q2are connected to the first data line D1, the source of the first thin film transistor Q1sequentially connects the first main sub-pixel electrode113and a first capacitor C1to a common electrode Cm (denoted by the triangle Δ inFIG. 2), the source of the second thin film transistor Q2sequentially connects the first subsidiary sub-pixel electrode114and a second capacitor C2to the common electrode Cm. The drains of the third thin film transistor Q3and the fourth thin film transistor Q4are connected to the second data line D2, the source of the third thin film transistor Q3sequentially connects the second main sub-pixel electrode123and a third capacitor C3to the common electrode Cm, and the source of the fourth thin film transistor Q4sequentially connects the second subsidiary sub-pixel electrode124and a fourth capacitor C4to the common electrode Cm. The drains of the fifth thin film transistor Q5and the sixth thin film transistor Q6are connected to the third data line D3, the source of the fifth thin film transistor Q5sequentially connects the third main sub-pixel electrodes133and a fifth capacitor C5to the common electrode Cm, and the source of the sixth thin film transistor Q6sequentially connects the third subsidiary sub-pixel electrode134and a sixth capacitor C6to the common electrode Cm. The drain of the seventh thin film transistor Q7is connected to the third subsidiary sub-pixel electrode134, and the source of the seventh thin film transistor Q7is connected to the common electrode Cm.

In this embodiment, since the fifth thin film transistor Q5of the fifth area131and sixth thin film transistor Q6of the sixth area132both are connected to the third data line D3, the source of the fifth thin film transistor Q5sequentially connects the third main sub-pixel electrode133and the fifth capacitor C5to the common electrode Cm, the source of the sixth thin film transistor Q6sequentially connects the third subsidiary sub-pixel electrode134and the sixth capacitor C6to the common electrode Cm, the drain of the seventh thin film transistor Q7is connected to the third subsidiary sub-pixel electrode134, and the source of the seventh thin film transistor Q7is connected to the common electrode Cm. That is, because the thin film transistor has a certain resistance, by the voltage-dividing effect of the seventh thin film transistor Q7, a voltage applied onto the third subsidiary sub-pixel electrode134in the sixth area132is different from a voltage applied onto the third main sub-pixel electrode133in the fifth area131. In this embodiment, the voltage applied onto the third subsidiary sub-pixel electrode134in the sixth area132is smaller than the voltage applied onto the third main sub-pixel electrode133in the fifth area131

In this embodiment, a voltage difference between the sub-pixel electrode of the sixth area132and the common electrode is different from a voltage difference between the sub-pixel electrode of the fifth area131and the common electrode, and therefore, the voltage applied onto the sub-pixel electrode of the sixth area132is different from the voltage applied onto the sub-pixel electrode of the fifth area131. In other words, the voltage applied onto the third main sub-pixel electrode133is different from the voltage applied onto the third subsidiary sub-pixel electrode134, so that the color shift occurred when the thin film transistor array substrate10is driving a liquid crystal layer can be improved. In another aspect, in this embodiment, in the three sub-pixels of one pixel100, only in the third sub-pixel130, the voltage applied onto the third subsidiary sub-pixel electrode134corresponding to the sixth area132is different from the voltage applied onto the third main sub-pixel electrode133corresponding to the fifth area131, compared with the prior art, which can reduce the drawback of liquid crystal molecules in the liquid crystal layer being not fully/completely rotated, so that the loss of light passing through the liquid crystal layer can be reduced. Accordingly, compared with the prior art, the thin film transistor array substrate10in this embodiment when driving the liquid crystal layer can improve the large viewing angle color shift and increase the transmittance of light passing through the liquid crystal layer.

In this embodiment, the first sub-pixel110is a red sub-pixel, the second sub-pixel120is a green sub-pixel, and the third sub-pixel130is a blue sub-pixel. Since the human eye is most sensitive to a variation of the blue sub-pixel, less sensitive to a variation of the green sub-pixel and least sensitive to a variation of the red sub-pixel. Therefore, the voltage difference between the sub-pixel electrode in the sixth area132corresponding to the third sub-pixel130and the common electrode is set to be different from the voltage difference between the sub-pixel electrode in the fifth area131and the common electrode, which can greatly improve the large viewing angle color shift and minimize the loss of transmittance.

Please refer toFIG. 3andFIG. 4,FIG. 3is a schematic view of a thin film transistor array substrate according to a second preferred embodiment of the invention, andFIG. 4is a structural schematic view of a pixel in the thin film transistor array substrate according to the second preferred embodiment of the invention. In this embodiment, the thin film transistor array substrate20is disposed with a plurality of pixels200arranged in an array. Each pixel200includes a first sub-pixel210, a second sub-pixel220and a third sub-pixel230arranged along a first direction. The first sub-pixel210, the second sub-pixel220and the third sub-pixel230are connected to a same scan line GL. The thin film transistor array substrate20further is disposed with a first data line D1, a second data line D2and a third data line D3sequentially arranged along the first direction. The first data line D1is configured for driving the first sub-pixel210, the second data line D2is configured for driving the second sub-pixel220, and the third data line D3is configured for driving the third sub-pixel230. The first sub-pixel210includes a first area211and a second area212arranged along a second direction, the second sub-pixel220includes a third area221and a fourth area222arranged along the second direction, the third sub-pixel230includes a fifth area231and a sixth area232arranged along the second direction. A voltage difference between a sub-pixel electrode in the sixth area232and a common electrode is different from a voltage difference between a sub-pixel electrode in the fifth area231and the common electrode. In this embodiment, the first direction is the horizontal direction, and the second direction is the vertical direction.

The first area211has a first thin film transistor Q1disposed therein, the second area212has a second thin film transistor Q2disposed therein, the third area221has a third thin film transistor Q3disposed therein, the fourth area222has a third thin film transistor Q4and an eighth thin film transistor Q8disposed therein, the fifth area231has a fifth thin film transistor Q5disposed therein, the sixth area232has a sixth thin film transistor Q6and a seventh thin film transistor Q7disposed therein. The first thin film transistor Q1, the second thin film transistor Q2, the third thin film transistor Q3, the fourth thin film transistor Q4, the fifth thin film transistor Q5, the sixth thin film transistor Q6, the seventh thin film transistor Q7and the eighth thin film transistor Q8each include a gate, a source and a drain. The first area211, the second area212, the third area221, the fourth area222, the fifth area231and the sixth area232each are corresponding to one sub-pixel electrode, for the convenience of description, the corresponding sub-pixel electrode in the first area211is named as first main sub-pixel electrode213, the corresponding sub-pixel electrode in the second area212is named as first subsidiary sub-pixel electrode214, the corresponding sub-pixel electrode in the third area221is named as second main sub-pixel electrode223, the corresponding sub-pixel electrode in the fourth area222is named as second subsidiary sub-pixel electrode224, the corresponding sub-pixel electrode in the fifth area231is named as third main sub-pixel electrode233, and the corresponding sub-pixel electrode in the sixth area232is named as third subsidiary sub-pixel electrode234. It should be understood to those skilled in the art that, the names of the corresponding sub-pixel electrodes of the above various areas only are to distinguish the sub-pixels in different areas and for the convenience of description, and thus actually have no distinction of main and subsidiary.

The gates of the first thin film transistor Q1, the second thin film transistor Q2, the third thin film transistor Q3, the fourth thin film transistor Q4, the fifth thin film transistor Q5, the sixth thin film transistor Q6, the seventh thin film transistor Q7and the eighth thin film transistor Q8are connected to the same scan line GL. The drains of the first thin film transistor Q1and the second thin film transistor Q2are connected to the first data line D1, the source of the first thin film transistor Q1sequentially connects the first main sub-pixel electrode213and a first capacitor C1to the common electrode Cm (denoted by the triangle Δ inFIG. 4), the source of the second thin film transistor Q2sequentially connects the first subsidiary sub-pixel electrode214and a second capacitor C2to the common electrode Cm. The drains of the third thin film transistor Q3and the fourth thin film transistor Q4are connected to the second data line D2, the source of the third thin film transistor Q3sequentially connects the second main sub-pixel electrode223and a third capacitor C3to the common electrode Cm, the source of the fourth thin film transistor Q4sequentially connects the second subsidiary sub-pixel electrode224and a fourth capacitor C4to the common electrode Cm. The drain of the eighth thin film transistor Q8is connected to the second subsidiary sub-pixel electrode224, and the source of the eighth thin film transistor Q8is connected to the common electrode Cm. The drains of the fifth thin film transistor Q5and the sixth thin film transistor Q6are connected to the third data line D3, the source of the fifth thin film transistor Q5sequentially connects the third main sub-pixel electrode233and a fifth capacitor C5to the common electrode Cm, the source of the sixth thin film transistor Q6sequentially connects the third subsidiary sub-pixel electrode234and a sixth capacitor C6to the common electrode Cm. The drain of the seventh thin film transistor Q7is connected to the third subsidiary sub-pixel electrode234, and the source of the seventh thin film transistor Q7is connected to the common electrode Cm.

In this embodiment, since the drains of the fifth thin film transistor Q5of the fifth area231and the sixth thin film transistor Q6of the sixth area232both are connected to the third data line D3, the source of the fifth thin film transistor Q5sequentially connects the third main sub-pixel electrode233and the fifth capacitor C5to the common electrode Cm, the source of the sixth thin film transistor Q6sequentially connects the third subsidiary sub-pixel electrode234and the sixth capacitor C6to the common electrode Cm, the drain of the seventh thin film transistor Q7is connected to the third subsidiary sub-pixel electrode234, and the source of the seventh thin film transistor Q7is connected to the common electrode Cm. That is, since the thin film transistor has a certain resistance, by the voltage-dividing effect of the seventh thin film transistor Q7, a voltage applied onto the third subsidiary sub-pixel electrode234in the sixth area232is different from a voltage applied onto the third main sub-pixel electrode233in the fifth area231. In this embodiment, the voltage applied onto the third subsidiary sub-pixel electrode234in the sixth area232is smaller than the voltage applied onto the third main sub-pixel electrode233in the fifth area231. Likewise, by the voltage-dividing effect of the eighth thin film transistor Q8, a voltage applied onto the second subsidiary sub-pixel electrode224in the fourth area222is different from a voltage applied onto the second main sub-pixel electrode223in the third area221. In this embodiment, the voltage applied onto the second subsidiary sub-pixel electrode224in the fourth area222is smaller than the voltage applied onto the second main sub-pixel electrode223in the third area221.

In this embodiment, a voltage difference between the sub-pixel electrode of the sixth area232and the common electrode is different from a voltage difference between the sub-pixel electrode of the fifth area231and the common electrode, and therefore, the voltage applied onto the sub-pixel electrode of the sixth area232is different from the voltage applied onto the sub-pixel electrode of the fifth area231. In other words, the voltage applied onto the third main sub-pixel electrode233is different from the voltage applied onto the third subsidiary sub-pixel electrode234, which can improve the color shift when the thin film transistor array substrate20is driving a liquid crystal layer. Likewise, in this embodiment, the voltage applied onto the second main sub-pixel electrode223is different from the voltage applied onto the second subsidiary sub-pixel electrode224, which can further improve the color shift when the thin film transistor array substrate20is driving the liquid crystal layer. In another aspect, in this embodiment, in the third sub-pixel230of one pixel200, the voltage applied onto the third subsidiary sub-pixel electrode234corresponding to the sixth area232is different from the voltage applied onto the third main sub-pixel electrode233corresponding to the fifth area231; in the second sub-pixel220, the voltage applied onto the second subsidiary sub-pixel electrode224corresponding to the fourth area222is different from the voltage applied onto the second main sub-pixel electrode221corresponding to the third area221; compared with the prior art, this embodiment can reduce the drawback of liquid crystal molecules in the liquid crystal layer being not fully/completely rotated, so that the loss of light passing through the liquid crystal layer can be reduced. Accordingly, compared with the prior art, the thin film transistor array substrate20in this embodiment when driving the liquid crystal layer can improve the large viewing angle color shift and increase the transmittance of light passing through the liquid crystal layer.

Similarly, in this embodiment, the first sub-pixel210is a red sub-pixel, the second sub-pixel220is a green sub-pixel, and the third sub-pixel230is a blue sub-pixel.

Please refer toFIG. 5andFIG. 6,FIG. 5is a schematic view of a thin film transistor array substrate according to a third preferred embodiment of the invention, andFIG. 6is a structural schematic view of a pixel in the thin film transistor array substrate according to the third preferred embodiment of the invention. The thin film transistor array substrate30is disposed with a plurality of pixels300arranged in an array. Each pixel300includes a first sub-pixel310, the second sub-pixel320and a third sub-pixel330arranged along a first direction. The first sub-pixel310, the second sub-pixel320and the third sub-pixel330are connected to a same scan line GL. The thin film transistor array substrate30further is disposed with a first data line D1, a second data line D2, a third data line D3and a fourth data line D4sequentially arranged along the first direction. The first data line D1is configured for driving the first sub-pixel310, the second data line D2is configured for driving the second sub-pixel320, the third data line D3is configured for driving the third sub-pixel330, and the fourth data line D4is configured for driving the third sub-pixel330. The first sub-pixel310includes a first area311and a second area312arranged along a second direction, the second sub-pixel320includes a third area321and a fourth area322arranged along the second direction, the third sub-pixel330includes a fifth area331and a sixth area332arranged along the second direction. A voltage difference between a sub-pixel electrode in the sixth area332and a common electrode is different from a voltage difference between a sub-pixel electrode in the fifth area331and the common electrode. In this embodiment, the first direction is the horizontal direction, and the second direction is the vertical direction. The third data line D3is for driving the fifth area331of the third sub-pixel330, the fourth data line D4is for driving the sixth area332of the third sub-pixel330, a driving voltage applied onto the third data line D3is different from a driving voltage applied onto the fourth data line D4. In this embodiment, by using the third data line D3and the fourth data line D4to respectively drive the fifth area331and the sixth area332of the third sub-pixel330, and the voltages applied onto the third data line D3and the fourth data line D4being different from each other, it is achieved that the voltage difference between the sub-pixel electrode in the sixth area332and the common electrode is different from the voltage difference between the sub-pixel electrode in the fifth area331and the common electrode.

The first area311has a first thin film transistor Q1disposed therein, the second area312has a second thin film transistor Q2disposed therein, the third area321has a third thin film transistor Q3disposed therein, the fourth area322has a fourth thin film transistor Q4disposed therein, the fifth area331has a fifth thin film transistor Q5disposed therein and the sixth area332has a sixth thin film transistor Q6disposed therein. The first thin film transistor Q1, the second thin film transistor Q2, the third thin film transistor Q3, the fourth thin film transistor Q4, the fifth thin film transistor Q5and the sixth thin film transistor Q6each include a gate, a source and a drain. The first area311, the second area312, the third area321, the fourth area322, the fifth area331and the sixth area332each are corresponding to one sub-pixel electrode, for the convenience of description, the corresponding sub-pixel electrode in the first area311is named as first main sub-pixel electrode313, the corresponding sub-pixel electrode in the second area312is named as first subsidiary sub-pixel electrode314, the corresponding sub-pixel electrode in the third area321is named as second main sub-pixel electrode323, the corresponding sub-pixel electrode in the fourth area322is named as second subsidiary sub-pixel electrode324, the corresponding sub-pixel electrode in the fifth area331is named as third main sub-pixel electrode333, and the corresponding sub-pixel electrode in the sixth area332is named as third subsidiary sub-pixel electrode334. It should be understood to those skilled in the art that, the names of the corresponding sub-pixel electrodes of the above various areas only are to distinguish the sub-pixels in different areas and for the convenience of description, and thus actually have no distinction of main and subsidiary.

The gates of the first thin film transistor Q1, the second thin film transistor Q2, the third thin film transistor Q3, the fourth thin film transistor Q4, the fifth thin film transistor Q5and the sixth thin film transistor Q6are connected to the same scan line GL. The drains of the first thin film transistor Q1and the second thin film transistor Q2are connected to the first data line D1, the source of the first thin film transistor Q1sequentially connects the first main sub-pixel electrode313and a first capacitor C1to the common electrode Cm (denoted by the triangle Δ inFIG. 6), the source of the second thin film transistor Q2sequentially connects the first subsidiary sub-pixel electrode314and a second capacitor C2to the common electrode Cm. The drains of the third thin film transistor Q3and the fourth thin film transistor Q4are connected to the second data line D2, the source of the third thin film transistor Q3sequentially connects the second main sub-pixel electrode323and a third capacitor C3to the common electrode Cm, the source of the fourth thin film transistor Q4sequentially connects the second subsidiary sub-pixel electrode324and a fourth capacitor C4to the common electrode Cm. The drain of the fifth thin film transistor Q5is connected to the third data line D3, the source of the fifth thin film transistor Q5sequentially connects the third main sub-pixel electrode333and a fifth capacitor C5to the common electrode Cm. The drain of the sixth thin film transistor Q6is connected to the fourth data line D4, the source of the sixth thin film transistor Q6sequentially connects the third subsidiary sub-pixel electrode334and a sixth capacitor C6to the common electrode Cm.

In this embodiment, by using the third data line D3and the fourth data line D4to respectively drive the fifth area331and the sixth area332of the third sub-pixel330, and the voltages applied onto the third data line D3and the fourth data line D4being different from each other, it is achieved that the voltage difference between the sub-pixel electrode in the sixth area332and the common electrode is different from the voltage difference between the sub-pixel electrode in the fifth area331and the common electrode. In other words, the voltage applied onto the third main sub-pixel electrode333is different from the voltage applied onto the third subsidiary sub-pixel electrode334, which can improve the color shift when the thin film transistor array substrate30is driving a liquid crystal layer. In another aspect, in this embodiment, in the three sub-pixels of one pixel300, only in the third sub-pixel330, the voltage applied onto the third subsidiary sub-pixel electrode334corresponding to the sixth area332is different from the voltage applied onto the third main sub-pixel electrode333corresponding to the fifth area331, compared with the prior art, this embodiment can reduce the drawback of liquid crystal molecules in the liquid crystal layer being not fully/completely rotated, so that the loss of light passing through the liquid crystal layer can be reduced. Accordingly, compared with the prior art, the thin film transistor array substrate30in this embodiment during the driving the liquid crystal layer can improve the large viewing angle color shift and increase the transmittance of light passing through the liquid crystal layer.

In this embodiment, the first sub-pixel310is a red sub-pixel, the second sub-pixel320is a green sub-pixel, and the third sub-pixel330is a blue sub-pixel.

Please refer toFIG. 7andFIG. 8,FIG. 7is a schematic view of a thin film transistor array substrate according to a fourth preferred embodiment of the invention, andFIG. 8is a structural schematic view of a pixel in the thin film transistor array substrate according to the fourth preferred embodiment of the invention. The thin film transistor array substrate40is disposed with a plurality of pixels400arranged in an array. Each pixel400includes a first sub-pixel410, a second sub-pixel420and a third sub-pixel430arranged along a first direction. The first sub-pixel410, the second sub-pixel420and the third sub-pixel430are connected to a same scan line GL. The thin film transistor array substrate40further is disposed with a first data line D1, a second data line D2, a fifth data line D5, a third data line D3and a fourth data line D4sequentially arranged along the first direction. The first data line D1is configured for driving the first sub-pixel410, the second data line D2is configured for driving the second sub-pixel420, the third data line D3is configured for driving the third sub-pixel430, the fourth data line D4is configured for driving the third sub-pixel430, and the fifth data line D5is configured for driving the second sub-pixel420. The first sub-pixel410includes a first area411and a second area412arranged along a second direction, the second sub-pixel420includes a third area421and a fourth area422arranged along the second direction, the third sub-pixel430includes a fifth area431and a sixth area432arranged along the second direction. A voltage difference between a sub-pixel electrode in the sixth area432and a common electrode is different from a voltage difference between a sub-pixel electrode in the fifth area431and the common electrode. In this embodiment, the first direction is the horizontal direction, and the second direction is the vertical direction. The third data line D3is for driving the fifth area431of the third sub-pixel430, the fourth data line D4is for driving the sixth area432of the third sub-pixel430, a driving voltage applied onto the third data line D3is different from a driving voltage applied onto the fourth data line D4. The second data line D2is for driving the third area421of the second sub-pixel420, the fifth data line D5is for driving the fourth area422of the second sub-pixel420, a driving voltage applied onto the second data line D2is different from a driving voltage applied onto the fifth data line D5. In this embodiment, by making the driving voltage applied onto the third data line D3be different from the driving voltage applied onto the fourth data line D4, it is achieved that the voltage applied onto the sub-pixel electrode in the fifth area431is different from the voltage applied onto the sub-pixel electrode in the sixth area432. By making the driving voltage applied onto the second data line D2be different from the driving voltage applied onto the fifth data line D5, it is achieved that the voltage applied onto the sub-pixel electrode in the third area421is different from the voltage applied onto the sub-pixel electrode in the fourth area422.

The first area411has a first thin film transistor Q1disposed therein, the second area412has a second thin film transistor Q2disposed therein, the third area421has a third thin film transistor Q3disposed therein, the fourth area422has a fourth thin film transistor Q4disposed therein, the fifth area431has a fifth thin film transistor Q5disposed therein, and the sixth area432has a sixth thin film transistor Q6disposed therein. The first thin film transistor Q1, the second thin film transistor Q2, the third thin film transistor Q3, the fourth thin film transistor Q4, the fifth thin film transistor Q5and the sixth thin film transistor Q6each include a gate, a source and a drain. The first area411, the second area412, the third area421, the fourth area422, the fifth area431and the sixth area432each are corresponding to one sub-pixel electrode, for the convenience of description, the corresponding sub-pixel electrode in the first area411is named as first main sub-pixel electrode413, the corresponding sub-pixel electrode in the second area412is named as first subsidiary sub-pixel electrode414, the corresponding sub-pixel electrode in the third area421is named as second main sub-pixel electrode423, the corresponding sub-pixel electrode in the fourth area422is named as second subsidiary sub-pixel electrode424, the corresponding sub-pixel electrode in the fifth area431is named as third main sub-pixel electrode433, and the corresponding sub-pixel electrode in the sixth area432is named as third subsidiary sub-pixel electrode434. It should be understood to those skilled in the art that, the names of the corresponding sub-pixel electrodes of the above various areas only are to distinguish the sub-pixels in different areas and for the convenience of description, and thus actually have no distinction of main and subsidiary.

The gates of the first thin film transistor Q1, the second thin film transistor Q2, the third thin film transistor Q3, the fourth thin film transistor Q4, the fifth thin film transistor Q5and the sixth thin film transistor Q6are connected to the same scan line GL. The drains of the first thin film transistor Q1and the second thin film transistor Q2are connected to the first data line D1, the source of the first thin film transistor Q1sequentially connects the first main sub-pixel electrode413and a capacitor C1to the common electrode Cm (denoted by the triangle Δ inFIG. 8), the source of the second thin film transistor Q2sequentially connects the first subsidiary sub-pixel electrode414and a second capacitor C2to the common electrode Cm. The drain of the third thin film transistor Q3is connected to the second data line D2, the source of the third thin film transistor Q3sequentially connects the second main sub-pixel electrode423and a third capacitor C3to the common electrode Cm, the drain of the fourth thin film transistor Q4is connected to the fifth data line D5, the source of the fourth thin film transistor Q4sequentially connects the second subsidiary sub-pixel electrode424and a fourth capacitor C4to the common electrode Cm. The drain of the fifth thin film transistor Q5is connected the third data line D3, the source of the fifth thin film transistor Q5sequentially connects the third main sub-pixel electrode433and a fifth capacitor C5to the common electrode Cm. The drain of the sixth thin film transistor Q6is connected to the fourth data line D4, the source of the sixth thin film transistor Q6sequentially connects the third subsidiary sub-pixel electrode434and a sixth capacitor C6to the common electrode Cm.

In this embodiment, by using the third data line D3and the fourth data line D4to respectively drive the fifth area431and the sixth area432of the third sub-pixel430, the voltages applied onto the third data line D3and the fourth data line D4being different from each other, it is achieved that a voltage difference between the sub-pixel electrode in the sixth area432and the common electrode is different from a voltage difference between the sub-pixel electrode in the fifth area431and the common electrode. In other words, the voltage applied onto the third main sub-pixel electrode433is different from the voltage applied onto the third subsidiary sub-pixel electrode434, which can improve the color shift when the thin film transistor array substrate40driving a liquid crystal layer. Likewise, by using the second data line D2and the fifth data line D5to respectively drive the third area421and the fourth area422of the second sub-pixel420, voltages applied onto the second data line D2and the fifth data line D5being different from each other, it is achieved that a voltage difference between the sub-pixel electrode in the third area421and the common electrode is different from a voltage difference between the sub-pixel electrode in the fourth area422and the common electrode. Compared with the prior art, this embodiment can reduce the drawback of liquid crystal molecules in the liquid crystal layer being not fully/completely rotated, so that the loss of light passing through the liquid crystal layer is reduced. Accordingly, compared with the prior art, the thin film transistor array substrate in this embodiment during driving the liquid crystal layer can improve the large viewing angle color shift and increase the transmittance of light passing through the liquid crystal layer.

In this embodiment, the first sub-pixel410is a red sub-pixel, the second sub-pixel420is a green sub-pixel, and the third sub-pixel430is a blue sub-pixel.

The invention further includes a display panel, in various preferred embodiments of the display panel, the display panel includes any one of the thin film transistor array substrates associated withFIGS. 1 through 8and thus will be not repeated herein.