Resistive memory device and method of manufacturing the same

A resistive memory device capable of improving an integration density is provided. The resistive memory device includes a semiconductor substrate, a plurality of resistive memory cells configured to be stacked on the semiconductor substrate and insulated from one another, where each of the plurality of resistive memory cells includes a switching transistor and a resistive device layer electrically connected to the switching transistor, a common source line electrically connected to the plurality of stacked resistive memory cells, and a bit line electrically connected to the plurality of stacked resistive memory cells and being insulated from the common source line.

CROSS-REFERENCES TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. 119(a) to Korean application number 10-2011-0135699, filed on Dec. 15, 2011, in the Korean Patent Office, which is incorporated by reference in its entirety as if set forth in full.

BACKGROUND OF THE INVENTION

1. Technical Field

Exemplary embodiments of the present invention relate to a semiconductor integrated circuit device and a method of manufacturing the same, and more particularly, to a stack type resistive memory device and a method of manufacturing the same.

2. Related Art

With rapid development of a mobile and digital information communication industry and an appliance industry, existing electron charge control-based devices are reaching their physical limits. Thus, different types of memory devices are being developed. For example, next-generation memory devices with large capacity, high speed, and low power consumption are desirable in order to increase the memory capacity of various devices.

Currently, resistive memory devices useable as a memory medium have been suggested as the next-generation memory devices. Exemplary resistive memory devices are phase-change memory devices, resistive memory devices, and magnetoresistive memory devices.

Each of the resistive memory devices is basically constituted of a switching device and a resistive device and stores data “0” or “1” according to a state of the resistive device.

Here, it is desirable to increase an integration density of the resistive memory devices and thus increase the memory capacity within a confined space.

SUMMARY

According to an exemplary embodiment, a resistive memory device includes a semiconductor substrate; a plurality of resistive memory cells configured to be stacked on the semiconductor substrate and insulated from one another, wherein each of the plurality of resistive memory cells includes a switching transistor and a resistive device layer electrically connected to the switching transistor; a common source line electrically connected to the plurality of stacked resistive memory cells; and a bit line electrically connected to the plurality of stacked resistive memory cells and being insulated from the common source line.

According to another exemplary embodiment, a resistive memory device includes a semiconductor substrate; a pair of first resistive memory cells formed on the semiconductor substrate; a first interlayer insulating layer formed on the pair of first resistive memory cells; a pair of second resistive memory cells formed on the first interlayer insulating layer at positions above the pair of first resistive memory cells; a common source line electrically connected to the first and second resistive memory cells; and a bit line electrically connected to the first and second resistive memory cells. Each of the first and second resistive memory cells includes a switching transistor and a resistive device layer connected to the switching transistor.

According to still another exemplary embodiment, a method of manufacturing a resistive memory device is provided. The method includes forming a first active layer on a semiconductor substrate; forming a first switching transistor and a resistive device layer in the first active layer; forming a first interlayer insulating layer on a structure including the first active layer; forming a second active layer on the first interlayer insulating layer; forming a second switching transistor and a resistive device layer in the second active layer; forming a common source line to be in contact with source regions of the first and second switching transistors; forming a second interlayer insulating layer on a structure including the common source line; forming a bit line contact unit to be in contact with the resistive device layers; and forming a bit line on the second interlayer insulating layer to be connected to the bit line contact unit.

These and other features, aspects, and embodiments are described below in the section entitled “DESCRIPTION OF EXEMPLARY EMBODIMENT”.

DESCRIPTION OF EXEMPLARY EMBODIMENT

Hereinafter, exemplary embodiments will be described in greater detail with reference to the accompanying drawings.

Exemplary embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of exemplary embodiments (and intermediate structures). As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, exemplary embodiments should not be construed as limited to the particular shapes of regions illustrated herein but may be to include deviations in shapes that result, for example, from manufacturing. In the drawings, lengths and sizes of layers and regions may be exaggerated for clarity. Like reference numerals in the drawings denote like elements. It is also understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other or substrate, or intervening layers may also be present.

As shown inFIG. 1, a resistive memory device10according to an exemplary embodiment includes a first memory cell mc1including a first switch transistor SW1and a first resistive device R1and a second memory cell mc2including a second switching transistor SW2and a second resistive device R2, where the first and second memory cells mc1and mc2are stacked with an insulating layer130interposed therebetween.

The first and second switching transistors SW1and SW2may be MOS transistors and the first and second resistive devices R1and R2(170) are formed to be electrically connected to junction regions of the first and second switching transistors SW1and SW2, for example, drain regions125band150b.

The stacked first and second resistive devices R1and R2may be commonly connected to the a bit line180by a bit line contact unit175which extends perpendicularly to a surface of a semiconductor substrate100. Sources regions125aand150aof the stacked first and second switching transistors SW1and SW2are electrically connected to a source common line160which extends perpendicular to the surface of the semiconductor substrate100.

The reference numerals105,130,155and165denote interlayer insulating layers, and the reference numerals120and145denote gate electrode layers. In addition, the reference numerals g1and g2denote gate electrode structures including gate insulating layers.

The resistive memory device according to the exemplary embodiment has a structure in which the memory cells mc1and mc2are stacked so that a plurality of memory cells can be integrated in a confined area.

Although it will be described in detail later, in the exemplary embodiment, the gate electrodes g1and g2of the first and second switching transistors SW1and SW2are formed to surround upper surfaces and lateral surfaces of the first active layers110and135having line shapes. Thereby, effective channel lengths of the first and second switching transistors SW1and SW2become longer to improve a current driving characteristic.

FIGS. 2 to 9are cross-sectional views illustrating a method of manufacturing a stack type resistive memory device according to an exemplary embodiment andFIGS. 10 to 15are plan views illustrating a method of manufacturing a stack type resistive memory device according to an exemplary embodiment.

Referring toFIGS. 2 and 10, an insulating layer105is formed on a semiconductor substrate100. A first active layer110having a line shape is formed on the insulating layer105. Here, a linewidth of the first active layer110determines a width of the switching transistor (SW1ofFIG. 1), where the first active layer110may include a conductive material including silicon (Si) (for example, a doped polysilicon layer).

Referring toFIGS. 3 and 11, a first gate insulating layer115and a first gate electrode layer120are sequentially stacked on the first active layer110and patterned to form a first gate electrode g1so that the first gate electrode layer120and the first gate insulating layer115cross the first active layer110. In the plan view ofFIG. 11, although the first gate electrode g1crosses the first active layer110, as shown inFIG. 16, the first gate electrode g1may be formed to surround three surfaces of the first active layer110. Therefore, an effective channel length of the switching transistor can be increased.

Although a plurality of first gate electrodes g1may be formed on the first active layer110, in the exemplary embodiment, for illustration purposes, only a pair of gate electrodes g1is described.

The first gate insulating layer115may be a silicon oxide layer or a metal oxide layer. The first gate electrode layer may include any one selected from the group consisting of a metal layer such as tungsten (W), copper (Cu), titanium (Ti), molybdenum (Mo) and tantalum (Ta), a metal nitride layer such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), molybdenum nitride (MoN), niobium nitride (NbN), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), titanium boron nitride (TiBN), zirconium silicon nitride (ZrSiN), tungsten silicon nitride (WSiN), tungsten boron nitride (WBN), zirconium aluminum nitride (ZrAlN), molybdenum silicon nitride (MoSiN), molybdenum aluminum nitride (MoAlN), tantalum silicon nitride (TaSiN) and tantalum aluminum nitride (TaAlN), a metal silicide layer such as titanium silicide (TiSi), an heterometal layer such as titanium tungsten (TiW), and a metal oxynitride layer such as a titanium oxynitride (TiON), tungsten oxynitride (WON), and tantalum oxynitride (TaON).

Referring toFIG. 4, impurities are implanted in the first active layer110at both sides of each first gate electrode g1to form first junction layers125. Here, among the first junction regions125, a first junction region125arranged between the first gate electrodes g1may be a drain region125bof a MOS transistor as described later and a junction region125arranged at the opposite side of each of the first gate electrodes g1may be a source region125aof the MOS transistor. Therefore, the first switching transistor SW1is formed. Next, a first interlayer insulating layer130is formed on a resultant structure of the semiconductor substrate100.

Referring toFIGS. 5 and 12, a second active layer135is formed on the first interlayer insulating layer130, and a second gate insulating layer140and a second gate electrode layer145are sequentially stacked. The second gate electrode layer145may include the same material as the first gate electrode layer120. The second gate electrode layer145and the second gate insulating layer140are patterned to form a second gate electrode g2so that the second gate electrode g2is arranged at a position corresponding to the first gate electrode g1. Like the first gate electrode g1, the second gate electrode g2may be formed to surround an upper surface and lateral surfaces of the second active layer135. In addition, a plurality of second gate electrodes g2may be formed on the second active layer135. Impurities are implanted into the second active layer135using the second gate electrode g2as a mask to form second junction regions150. Similarly, among the second junction regions150, a second junction region150arranged between the second gate electrodes g2may be a drain region150bof a MOS transistor as described later and a second junction region150arranged at the opposite side of each of the gate electrodes g2may be source regions150aof the MOS transistor. Therefore, a second switching transistor SW2is formed on the second active layer135. Subsequently, a second interlayer insulating layer155is formed on a resultant structure of the semiconductor substrate100.

Referring toFIGS. 6 and 13, a common source line160is formed to be electrically connected to the first and second junction regions125and150arranged at the outer sides of the first and second gate electrodes g1and g2, that is, the source regions125aand150a. More specifically, the second interlayer insulating layer155, the second active layer135, the first interlayer insulating layer130, the first active layer110, the insulating layer105, and the semiconductor substrate100are etched to expose the first and second junction regions125and150corresponding to the source regions125aand150a, thereby forming a contact hole (not shown). The first and second source regions125aand150aare exposed through a sidewall of the first contact hole and a conductive material fills the first contact hole, thereby forming the common source line160being in contact with the first and second source regions125aand150a. The common source line160may include any one of materials constituting the first gate electrode120.

Referring toFIG. 7, a third interlayer insulating layer165is formed on a resultant structure of the semiconductor substrate100in which the common source line160is formed. Next, the third interlayer insulating layer165, the second interlayer insulating layer155, the second junction region150, the first interlayer insulating layer130, and the first junction region125are etched to separate junction regions125and150between the gate electrodes g1and g2, which are arranged to be adjacent to one another on the same layer, that is, into the drain regions125band150bfor switching transistors, thereby forming a second contact hole H1. By the formation of the second contact hole H1, the drain regions125band150bmay be separated into the drain regions of the switching transistors and exposed through a sidewall of the second contact hole H1.

After the second contact hole H1is formed, an additional overetching process is performed to pull back the drain regions125band150btoward the gate electrodes g1and g2by a predetermined length. The pull-back process may be performed by a selective anisotropic etching method and a groove H2exposing the drain regions125band150bis formed in a predetermined portion of a sidewall of the second contact hole H1by the pull-back process.

Referring toFIGS. 8 and 14, a resistive device layer170buries the groove H2. The resistive device layer170may include any one selected from the group consisting of a praseodymium calcium manganese oxide (PCMO) layer which is a material for a resistive to random access memory (ReRAM), a chalcogenide layer which is a material for a phase-change random access memory (PCRAM), a magnetic layer which is a material for a magnetic random access memory (MRAM), a magnetization switching device layer which is a material for a spin-transfer torque MRAM (STTMRAM), and a polymer layer which is a material for a polymer random access memory (PoRAM). Thereby, a plurality of unit memory cells are formed in each layer and each of the plurality of unit memory cells is constituted of the switching transistor SW1and SW2and the resistive device layer170connected to the switching transistor SW1and SW2. Next, a conductive layer buries the second contact hole H1to form a bit line contact unit175which is in contact with the resistive device layer170. The bit line contact unit175may have a plug shape and include any one of the materials constituting the first gate electrode120.

Referring toFIGS. 1 and 15, a bit line180electrically connected to the bit line contact unit175is formed on the third interlayer insulating layer165. The bit line180may be formed to overlap the first and second active layers110and135and be arranged in a perpendicular direction to the gate electrodes g1and g2.

The resistive memory device according to the exemplary embodiment is configured to stack the memory cells mc1and mc2, each of which is constituted of the switching transistor SW1and SW2and the resistive layer170. Therefore, a high integration memory device can be manufactured by stacking the plurality of cells without being restricted by a critical dimension (CD).

In addition, in the exemplary embodiment, the gate electrodes g1and g2of the switching transistors SW1and SW2are formed to surround the three surfaces of the active layers110and135. Therefore, the effective channel lengths are increased so that current characteristics of the switching transistors can be improved and the fabrication process can be simple.

FIGS. 17 to 20are cross-sectional views illustrating resistive memory devices according to other exemplary embodiments. Referring toFIG. 17, switching transistors SW1and SW2may include n-channel MOS transistors. That is, source regions126aand151aand drain regions126band151bmay include n type impurities and may be formed in first and second active layers110and135as n type high concentration impurity regions.

In addition, referring toFIG. 18, resistive device layers171may be formed between source regions125aand150aand a common source line160. More specifically, after a process of forming a contact hole for forming the common source line160is performed, a pull-back process is performed on the source regions125aand150ato form a groove (not shown) in which the resistive device layer171is to be formed. Next, the resistive device layer171is formed in the groove and the common source line160is formed in the contact hole.

Referring toFIG. 19, a bit line185is arranged on one side of switching transistors SW1and SW2to be in contact with source regions125aand150aof the switching transistors SW1and SW2and a common source line160is formed to be electrically connected to drain regions125band150bof the switching transistors SW1and SW2. That is, the locations of the bit line185and the common source line160are switched from those inFIGS. 1,17, and18. Here, a plug160ais a conductive plug which connects the drain regions125band150bof the switching transistors SW1and SW2to the common source line160. The conductive plug160aextends perpendicular to a surface of a semiconductor substrate100so that a sidewall of the conductive plug160ais in contact with the drain regions125band150b.

Referring toFIG. 20, silicide layers190are formed on source regions125aand150aand drain regions125band150b, respectively, to increase current characteristics of switching transistors SW1and SW2.

FIGS. 21 and 22are cross-sectional views of phase-change memory devices according to other exemplary embodiments.

When the structure of the exemplary embodiment of the present invention is applied to a phase-change memory device, as shown inFIG. 21, a phase-change material layer210and an upper electrode220may be formed in a position in which the bit line contact unit175is formed in the above-described exemplary embodiments, that is, in the second contact hole H1and a heating electrode230may be formed in the region in which the resistive device layer170is formed in the above-described exemplary embodiments, that is, the groove H2.

The phase-change material layer210is formed to cover an inner surface of the second contact hole H1and the upper electrode220is formed to fill the second contact hole H1of which the inner surface is surrounded by the phase-change material layer210.

The heating electrode230may be formed on a sidewall s1and a bottom s2of the groove H2to reduce a contact area with the phase-change material layer210. For example, the heating electrode230may have an “L”-character shape and the groove H2of the heating electrode230may be buried with an insulating material layer240. By reducing the contact area between the heating electrode230and the phase-change material layer210, a reset current characteristic of the phase-change memory device may be improved.

According to another example, as shown inFIG. 22, a heating electrode235may be formed only on an upper surface of a groove H3. That is, the groove H3may be mostly filled with an insulating material layer240and the heating electrode235may be formed on the insulating material layer within the groove H3.

According to the exemplary embodiments, a plurality of memory cells can be integrated in a confined space by stacking resistive memory cells. Therefore, an integration density can be improved. In addition, MOS transistors are used as the switching transistors of the resistive memory cells and thus a current density can be increased.