Resistor loaded inverter structures

A method of forming an electrical device is provided that includes a semiconductor device and a passive resistor both integrated in a same vertically orientated epitaxially grown semiconductor material. The vertically orientated epitaxially grown semiconductor material is formed from a semiconductor surface of a supporting substrate. The vertically orientated epitaxially grown semiconductor material includes a resistive portion and a semiconductor portion, in which the sidewalls of the resistive portion are aligned with the sidewalls of the semiconductor portion. A semiconductor device is formed on the semiconductor portion of the vertically orientated epitaxially grown semiconductor material. A passive resistor is present in the resistive portion of the vertically orientated epitaxially grown semiconductor material, the resistive portion having a higher resistance than the semiconductor portion.

BACKGROUND

Technical Field

The present invention generally relates to passive electrical devices, and more particularly to integrating passive electrical devices with transistor type electrical devices.

Description of the Related Art

A resistor is an electrical component that limits or regulates the flow of electrical current in an electronic circuit. Resistors can also be used to provide a specific voltage for an active device such as a transistor. All other factors being equal, in a direct-current (DC) circuit, the current through a resistor is inversely proportional to its resistance, and directly proportional to the voltage across it. This is the well-known Ohm's Law.

SUMMARY

In one embodiment, a metal oxide semiconductor field effect transistor and resistor loaded inverter is provided that includes a fin structure vertically orientated on a supporting substrate, in which the fin structure includes a resistive portion and a semiconductor portion. In some embodiments, a transistor including a channel region is present in the semiconductor portion of the fin structure and a gate all around (GAA) gate structure is present on the channel region. The gate all around gate structure includes a gate dielectric directly on the channel region of the semiconductor portion of the fin structure and a gate electrode directly on the gate dielectric. A passive resistor is provided in the resistive portion of the fin structure.

In another embodiment, a junction field effect transistor and resistor loaded inverter is provided that includes a fin structure vertically orientated on a supporting substrate, in which the fin structure includes a resistive portion and a semiconductor portion. In some embodiments, a transistor including a channel region is present in the semiconductor portion of the fin structure and a gate all around (GAA) gate structure is present on the channel region. The gate all around gate structure includes a gate electrode directly on the channel region of the semiconductor portion of the fin structure. A passive resistor is provided in the resistive portion of the fin structure.

In another aspect of the present disclosure, a method of forming an inverter is provided that includes a semiconductor device and a passive resistor both integrated in a same vertically orientated epitaxially grown semiconductor material. The vertically orientated epitaxially grown semiconductor material is formed from a semiconductor surface of a supporting substrate. The vertically orientated epitaxially grown semiconductor material includes a resistive portion and a semiconductor portion, in which the sidewalls of the resistive portion are aligned with the sidewalls of the semiconductor portion. A semiconductor device is formed on the semiconductor portion of the vertically orientated epitaxially grown semiconductor material. The semiconductor device includes a gate structure present on a channel region portion of the semiconductor portion of the vertically orientated epitaxially grown semiconductor material, and source and drain regions on opposing sides of the channel region portion. A passive resistor is present in the resistive portion of the vertically orientated epitaxially grown semiconductor material, the resistive portion having a higher resistance than the semiconductor portion.

DETAILED DESCRIPTION

Detailed embodiments of the claimed structures and methods are disclosed herein; however, it is to be understood that the disclosed embodiments are merely illustrative of the claimed structures and methods that may be embodied in various forms. In addition, each of the examples given in connection with the various embodiments is intended to be illustrative, and not restrictive. Further, the figures are not necessarily to scale, some features may be exaggerated to show details of particular components. Therefore, specific structural and functional details disclosed herein are not to be interpreted as limiting, but merely as a representative basis for teaching one skilled in the art to variously employ the methods and structures of the present disclosure. For purposes of the description hereinafter, the terms “upper”, “lower”, “right”, “left”, “vertical”, “horizontal”, “top”, “bottom”, and derivatives thereof shall relate to the embodiments of the disclosure, as it is oriented in the drawing figures. The terms “positioned on” means that a first element, such as a first structure, is present on a second element, such as a second structure, wherein intervening elements, such as an interface structure, e.g. interface layer, may be present between the first element and the second element. The term “direct contact” means that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediary conducting, insulating or semiconductor layers at the interface of the two elements.

In the embodiments described herein, the transistors are field effect transistors (FETs). As used herein a “field effect transistor” is a transistor in which output current, i.e., source-drain current, is controlled by the voltage applied to the gate. A field effect transistor has three terminals, i.e., gate, source and drain. A “gate structure” means a structure used to control output current (i.e., flow of carriers in the channel) of a semiconducting device through electrical fields. As used herein, the term “drain” means a doped region in semiconductor device located at the end of the channel, in which carriers are flowing out of the transistor through the drain. As used herein, the term “source” is a doped region in the semiconductor device, in which majority carriers are flowing into the channel from the source. The field effect transistors of the present disclosure have a vertically orientated channel region that can be present within a fin structure. As used herein, a “fin structure” refers to a semiconductor material, which is employed as the body of a semiconductor device, in which the gate structure is positioned around the fin structure such that charge flows up or down the channel of the fin structure A FinFET is a semiconductor device that positions the channel region of the semiconductor device in a fin structure. As used herein, the term “channel” is the region adjacent to the gate structure and between the source and drain of a semiconductor device that becomes conductive when the semiconductor device is turned on. The source and drain regions of the fin structure are the portions of the fin structure that are on opposing sides of the channel region of the fin structure. A “vertical” FinFET semiconductor device has the drain, fin channel, and source device components arranged perpendicular to the plane of the substrate surface, which is referred to as a vertical stack.

In comparison to active resistors, e.g., diode connected transistors, passive resistors can have a higher temperature stability, higher linearity (i.e., higher bias stability) and lower noise. In some embodiments, passive resistors may be integrated into applications, such as biasing the high gain amplifiers or analog computation units, where small variations in bias may significantly drift the output. One issue associated with monolithic integration of passive resistors is their large area consumption. This is because the passive resistance values are larger or much larger than that of the ON resistance of the transistors, but the material used for the passive resistors is either metal or highly doped semiconductor to minimize temperature sensitivity and thermal noise.

The methods and structures of the present disclosure provide monolithic integration of a vertical passive resistor with vertical active elements, e.g., transistors. This approach substantially reduces area consumption. The resistance value of a passive resistor is given by R=ρL/A, where p is the resistivity of the material, L is the length of the resistor in the direction of current flow, and A the cross sectional area of the resistor perpendicular to current flow. The vertical structure allows L, i.e., the height of the resistor structure) to be arbitrarily large, while A (i.e., the footprint of the resistor/transistor pair) to be small. Both a large L value, and a small A value simultaneously favoring a large R.

The methods and structures of the present disclosure are vertically orientated designs that provide space savings compared to planar, i.e., horizontally, orientated devices. The methods and structures provided herein can produce vertically orientated four terminal devices. It is noted that the resistive portion of the vertically orientated epitaxially grown semiconductor material may have a height, i.e., length, that can be adjusted according to the resistive needs of the device. Therefore, the height depicted in the supplied figures are illustrative of only one embodiments, and are not intended to limit the present disclosure. As will be described in further detail below, the epitaxial growth of the material for the resistive portion of the device allows for one of ordinary skill in the art to adjust the resistive region to tune the desired resistance, i.e., control the dopant species, dopant concentration, doping level, epitaxial thickness and/or size. The methods and structures of the present disclosure are now described with greater detail with reference toFIGS. 1-21.

FIG. 1depicts one embodiment of a transistor and resistor loaded inverter that includes a passive resistor, integrated with a metal oxide semiconductor field effect transistor (MOSFET) having a vertical orientation, in which the body10of the passive resistor is positioned between the channel region20of the vertically orientated MOSFET and a supporting substrate5.

FIGS. 1-3andFIGS. 10-12illustrate some embodiments of a MOSFET and a resistor that can be used in an inverter circuit. In some embodiments, an inverter circuit outputs a voltage representing the opposite logic-level to its input. Its function can be to invert the input signal applied. If the applied input is low then the output becomes high and vice versa. Inverters can be constructed using a single NMOS transistor or a single PMOS transistor coupled with a resistor. Since this ‘resistive-drain’ approach uses only a single type of transistor, it can be fabricated at low cost. However, because current flows through the resistor in one of the two states, the resistive-drain configuration is disadvantaged for power consumption and processing speed. The inverter depicted inFIGS. 1-3is one example of a PMOS transistor being coupled with a resistor. The inverter depicted inFIGS. 10-12is one example of an NMOS transistor coupled with a resistor. In a MOSFET inverter circuits, a load resistor R and MOS transistor connected in series between supply voltage (VDD) and ground. If Vin is less than the threshold voltage of MOS transistor, the transistor is off.

FIG. 1depicts one embodiment of a body10of a passive resistor monolithically integrated with a channel region20of a metal oxide semiconductor field effect transistor (MOSFET) having a vertical orientation, in which the resistor is positioned between the channel of the MOSFET and the supporting substrate5. The term “monolithically” denotes that the body10of the resistor and the channel region20of the MOSFET are composed of the same semiconductor material. Because the body10of the resistor and the channel region20of the MOSFET are provided by the same epitaxially formed semiconductor material, the sidewalls of the body10of the resistor and the channel region20of the MOSFET are aligned. Further, the body10of the resistor and the channel region20of the MOSFET are stacked, i.e., vertically stacked.

Referring toFIG. 1, the electrical device that provides the inverter structure includes a supporting substrate5. The supporting substrate5is typically composed of a semiconductor material, such as a type IV semiconductor, e.g., silicon, and/or a type III-V semiconductor, e.g., gallium arsenide (GaAs). A counter doped region6is present atop the supporting substrate5. In the embodiment that is depicted inFIG. 1, a heavily doped source region layer7(GROUND (for the inverter) is present on the counter doped region6. In some embodiments, both the counter doped layer6and the heavily doped source region layer7can be epitaxially formed semiconductor materials, which can be type IV semiconductors, such as silicon (Si), germanium (Ge), and/or silicon germanium (SiGe), or can be type IIIV semiconductors, such as gallium arsenide (GaAs). The counter doped region6can function as an isolation layer, electrically isolating the supporting substrate5from the heavily doped source layer7. Therefore, the counter doped layer6and the heavily doped source region layer7are doped to opposite conductivity types. The MOSFET depicted inFIGS. 1 and 2is a p-type MOSFET. Therefore, the heavily doped source region layer7is doped to a p-type conductivity. As the counter doped region6has an opposite conductivity type as the heavily doped source region layer7, the counter doped region6is doped to an n-type conductivity.

The heavily doped source region layer7can provide both the source region of the MOSFET and an electrode for the passive resistor.

The body10of the passive resistor is present in direct contact, i.e., epitaxial relationship, with the heavily doped source region layer7, and is monolithically integrated with a channel region20of the metal oxide semiconductor field effect transistor (MOSFET) having a vertical orientation. This is provided by epitaxial growth of both the body10of the passive resistor and the channel region20in the same fin geometry opening using the heavily doped source region layer7as the epitaxial growth surface. The body10of the passive resistor and the channel region20may be composed of a type IV semiconductor, such as silicon, germanium or silicon germanium, and/or a type III-V semiconductor material, such as gallium arsenide (GaAs).

The dimensions, material composition, dopant type and dopant concentration of the resistor body10is selected to provide the resistance properties of the passive resistor for the inverter. For example, the body10of the passive resistor has a greater resistance than the channel portion20of the monolithically integrated structure.

The resistance value of the body10for the passive resistor is given by R=ρL/A, where p is the resistivity of the material, L is the length of the resistor in the direction of current flow, and A the cross sectional area of the resistor perpendicular to current flow. The vertical structure allows L, i.e., the height of the resistor structure) to be arbitrarily large, while A (i.e., the footprint of the resistor/transistor pair) to be small. Both a large L value, and a small A value simultaneously favoring a large R. The length L1of the body10of the passive resistor can be increased to increase the resistance of the passive resistor. This can be a function of the length of the epitaxial growth process for forming the body10of the passive resistor.

The body10of the passive resistor, i.e., length L1of the body of the passive resistor, can extend through a material stack of dielectric materials that can be on the order of three separate dielectric layers. For example, in the embodiment that is depicted inFIG. 1, a first resistor body level spacer8is present on the heaving doped source region layer7, an resistor body level dielectric layer9is present on the first resistor body level spacer8, and a second resistor body level spacer11is present on the resistor body level dielectric layer9. Each of these dielectric layers may be composed of a nitride, oxide or oxynitride material, as well as other dielectric materials employed in semiconductor devices.

Still referring toFIG. 1, a doped epitaxial semiconductor material having source doping25is present at the interface of the body10of the passive resistor, and the channel region20of the MOSFET. The doped epitaxial semiconductor material having source doping25may be doped to an n-type or p-type conductivity, and may be composed of a type IV semiconductor material, e.g., silicon, or a type III-V semiconductor material, e.g., gallium arsenide (GaAs). The geometry of the doped epitaxial semiconductor material having the source doping25may be facetted having sidewalls coming to an apex in a diamond like shape. The doped epitaxial semiconductor material having the source doping25may provide a source region for the MOSFET, as well as provide a terminal for the passive resistor that includes the resistor body10.

Referring toFIGS. 1 and 2, the doped epitaxial semiconductor material having the source doping25is in connection with an electrically conductive line14to an output via41to provide an output for the inverter device. The electrically conductive line14and the output via41may each be composed of a metal. The metal used for each of the electrically conductive line14and the output via41may be provided by copper, aluminum, silver, gold, platinum, tungsten, tantalum and combinations thereof.

The electrically conductive line14that is in direct contact with the doped epitaxial semiconductor material having the source doping25is present atop the second resistor body level dielectric spacer11and is separated from the gate structure by a lower gate sidewall spacer13. The lower gate sidewall spacer13is composed of a dielectric material, such as silicon nitride.

The gate structure15for the MOSFET may include a gate dielectric17that is present directly on the channel region20of the MOSFET. The gate dielectric17may be a high-k dielectric material. One example of a high-k material for the gate dielectric17is hafnium oxide (HfO2). The gate structure15also includes a gate electrode16, which may be an electrically conductive material, such as a doped semiconductor material, such as n-type polysilicon. In some embodiments, a work function adjusting layer18, such as an n-type or p-type work function adjusting layer, is present between the gate electrode16and the gate dielectric17. The gate structure15is contacted by a gate contact via42. The gate contact via42is composed of an electrically conductive material, such as a doped semiconductor or a metal, and provides the input for the inverter. The gate structure15may be a gate all around (GAA) gate structure that is present around an entirety of the channel region20portion of the monolithic epitaxially formed structure (having a FIN geometry)

An epitaxially formed drain region30is present on the end of the channel region20that is opposite the end of the channel region20that is in closest proximity to the resistor body10of the passive resistor. The epitaxially formed drain region30may be composed of a type IV semiconductor, such as silicon, silicon germanium and/or germanium, or the epitaxially formed drain region may be composed of a type III-V semiconductor, such as gallium arsenide (GaAs). The epitaxially formed drain region30may be doped to an n-type or p-type conductivity. In the embodiment depicted inFIGS. 1-3, the epitaxially formed drain region30is doped to a p-type conductivity. The geometry of the epitaxial formed drain region30may be facetted having sidewalls coming to an apex in a diamond like shape.

The epitaxially formed drain region30may be separated from the gate structure15by an upper gate sidewalls spacer23, which can be composed of a dielectric, such as an oxide, e.g., silicon oxide, and/or a nitride, such as silicon nitride. Sidewall spacers28that are also composed of a dielectric material may be present on sidewalls of the epitaxially formed drain region30. The epitaxially formed drain region30is contacted by the drain contact via43. The drain contact via43is composed of an electrically conductive material, such as a doped semiconductor or a metal, and provides for contact of the inverter to the positive power supply (VDD).

An interlevel dielectric layer40may encapsulate a majority of the inverter, in which the drain contact via43, the gate contact via42and the output via41extend through the interlevel dielectric layer40. The contact identified by reference number46can be an alternate output for the inverter.

The structures described above with reference toFIGS. 1-3are now described in more detail with reference toFIGS. 4-9, which illustrate one embodiment of a method for forming an inverter including a MOSFET having a vertically orientated channel20monolithically integrated with the body10of a passive resistor.

FIG. 4depicts one embodiment of material stack that provides an initial structure for use in a method for forming an inverter structure, as depicted inFIGS. 1-3. In some embodiments, the initial material stack includes a supporting substrate5, a counter doped layer6, and a heaving doped source region layer7that is present atop the counter doped layer. The counter doped layer6may be formed on the upper surface of the supporting substrate5by ion implantation or by epitaxial growth in combination with in situ doping or ion implantation. The counter doped layer6may have a thickness ranging from 5 nm to 50 nm. The material layer for providing the heaving doped source region layer7may also be formed using ion implantation or epitaxial growth in combination with ion implantation or in situ doping. The thickness for the material layer for the heaving doped source region layer7typically ranges from about 10 nm to about 100 nm.

Still referring toFIG. 4, a dielectric stack is present atop the aforementioned structure that corresponds to the level in which the body10of the passive resistor is to be formed. The dielectric stack includes a first resistor body level spacer8that is present atop the heavily doped source region layer7, a resistor body level dielectric layer9present on the first resistor body level spacer8, and a second resistor body level spacer11is present on the resistor body level dielectric layer9. Each of these dielectric layers may be composed of a nitride, oxide or oxynitride material, as well as other dielectric materials employed in semiconductor devices. The composition of these dielectric layers can be selected to provide for selective etching between the layers and the adjacent layers to the dielectric stack. The thickness of the resistor body level dielectric layer9is selected to provide the length L1of the body10for the passive resistor. Each of the first resistor body level spacer8, the resistor body level dielectric layer9, and the second resistor body level spacer11may be deposited using a chemical vapor deposition process, such as plasma enhanced chemical vapor deposition (PECVD).

A sacrificial electrical contact layer21, which may also be referred to as a dummy electrical contact layer, is present on the second resistor body level spacer11. The sacrificial electrical contact layer21may be composed of any material that can be removed selectively to the second resistor body level spacer11, and the overlying lower gate sidewall spacer layer13. In some embodiments, the sacrificial electrical contact layer21may be composed of a silicon containing material, such as amorphous silicon (α-Si). The sacrificial electrical contact layer21may be formed using a deposition process, such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), metal organic chemical vapor deposition (MOCVD), room temperature chemical vapor deposition (RTCVD), high density plasma chemical vapor deposition (HDPCVD) and combinations thereof.

Still referring toFIG. 4, a first dielectric spacer layer that provides the lower gate sidewall spacer13(also referred to as bottom gate sidewall spacer) of the vertical transistor device is formed on the upper surface of the sacrificial electrical contact layer21. The first dielectric spacer layer may be formed using a deposition process, such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), metal organic chemical vapor deposition (MOCVD), room temperature chemical vapor deposition (RTCVD), high density plasma chemical vapor deposition (HDPCVD) and combinations thereof. The first dielectric spacer layer that provides the lower gate sidewall spacer13may be composed of any dielectric material, and in some instances may be composed of silicon oxide or silicon nitride. In some embodiments, the lower gate sidewall spacer13can be composed of a low-k material. As used herein, the term “low-k” denotes a dielectric material having a dielectric constant equal to the dielectric constant of silicon oxide (SiO2) or less. Examples of materials suitable for the low-k dielectric material include diamond like carbon (DLC), organosilicate glass (OSG), fluorine doped silicon dioxide, carbon doped silicon dioxide, carbon doped silicon nitride, porous silicon dioxide, porous carbon doped silicon dioxide, boron doped silicon nitride, spin-on organic polymeric dielectrics (e.g., SILK™), spin-on silicone based polymeric dielectric (e.g., hydrogen silsesquioxane (HSQ) and methylsilsesquioxane (MSQ), and combinations thereof. The thickness of the lower gate sidewall spacer13may range from 5 nm to 20 nm.

A sacrificial gate structure layer22, which may also be referred to as a dummy gate layer, is present on the dielectric layer that provides the lower gate sidewall spacer13. The sacrificial gate structure layer22may be composed of any material that can be removed selectively to the lower gate sidewall spacer13. In some embodiments, the sacrificial gate structure layer22may be composed of a silicon containing material, such as amorphous silicon (α-Si). The sacrificial gate structure layer60may be formed using a deposition process, such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), metal organic chemical vapor deposition (MOCVD), room temperature chemical vapor deposition (RTCVD), high density plasma chemical vapor deposition (HDPCVD) and combinations thereof.

A second dielectric spacer layer that provides the upper gate sidewall spacer23(also referred to as top gate sidewall spacer) of the vertical transistor device is formed on the sacrificial gate structure layer23. The upper gate sidewall spacer23is similar to the lower gate sidewall spacer13. Therefore, the above description of the composition, thickness and method of forming the first dielectric spacer layer is suitable for describing forming the second dielectric spacer layer. For example, the second dielectric spacer layer may be composed of silicon oxide or silicon nitride.

A cap dielectric layer24is formed on the second dielectric spacer layer that provides the upper gate sidewall spacer23. The cap dielectric layer24in some examples may be composed of an oxide, such as silicon oxide. The selection of the composition of the cap dielectric layer24and the second dielectric spacer layer that provides the upper gate sidewall spacer23can be selected to provide that the cap dielectric layer24can be removed by an etch process that is selective to the upper gate sidewall spacer23. The upper gate sidewall spacer23protects the sacrificial gate structure layer22from being etched by the process steps that remove the cap dielectric layer24.

FIG. 5depicts forming a trench, i.e., fin structure opening, through the material stack depicted inFIG. 4to expose a surface of a heavily doped epitaxial source layer7, in which the heavily doped source layer7provides a surface for epitaxial growth of a fin structure geometry epitaxial material that provides the body10of the passive resistor and the channel of the MOSFET.

The trench opening, i.e., fin structure opening, can be formed using deposition, photolithography and etch processes. First, an etch mask is formed atop the material stack including the sacrificial gate layer22, and the resistor body level dielectric layer9, having openings exposing the portions of the material stack, in which the trench opening, i.e., fin structure openings, are formed. Specifically, a etch mask can be produced by applying a photoresist to the surface to be etched; exposing the photoresist to a pattern of radiation; and then developing the pattern into the photoresist utilizing conventional resist developer to produce the etch mask. Once the patterning of the photoresist is completed, the sections covered of the material stack covered by the etch mask are protected while the exposed regions are removed using an etching process that removes the unprotected regions. In some embodiments, the etch process may be an anisotropic etch that removes the exposed portions of the dielectric cap layer24, the second dielectric spacer layer that provides the upper gate sidewall spacer23, the sacrificial gate layer22, the first dielectric spacer layer that provides the lower gate sidewall spacer13, the sacrificial electrical contact layer21, the first resistor body level spacer8, the resistor body level dielectric layer9, and the second resistor body level spacer11to expose a surface of the heavily doped source layer7. For example, the etch process for forming the fin structure openings can be a reactive ion etch process.

Still referring toFIG. 5, following the formation of the fin structure openings, a thermal oxidation process forms a dielectric surface3of the sidewall surface of the sacrificial gate layer22, and forms a dielectric surface on the sidewall surface of the sacrificial electrical contact layer21, which are exposed within the trench openings, i.e., fin openings. In the embodiments in which the sacrificial gate layer22is composed of a silicon containing material, the dielectric surface3may be composed of an oxide, such as silicon oxide.

FIG. 6depicts one embodiment of epitaxially forming a fin structure in the opening formed inFIG. 5, in which the epitaxial fin structure provides for a monolithic structure provides both the body10for the passive resistor and the channel20for the MOSFET. The fin structures are formed filling the fin structure openings using an epitaxial deposition process that employs the electrically conductive surface region20at the base of the fin structure openings as an epitaxial deposition growth surface. The epitaxial semiconductor material that provides the fin structures does not form on dielectric surfaces, such as the dielectric cap layer24or the dielectric surface3,4of the sacrificial gate layer22, or the dielectric surface on the sacrificial electrical contact layer21.

The terms “epitaxial growth and/or deposition” and “epitaxially formed and/or grown,” mean the growth of a semiconductor material (crystalline material) on a deposition surface of another semiconductor material (crystalline material), in which the semiconductor material being grown (crystalline over layer) has substantially the same crystalline characteristics as the semiconductor material of the deposition surface (seed material). In an epitaxial deposition process, the chemical reactants provided by the source gases are controlled, and the system parameters are set so that the depositing atoms arrive at the deposition surface of the semiconductor substrate with sufficient energy to move about on the surface such that the depositing atoms orient themselves to the crystal arrangement of the atoms of the deposition surface. Therefore, an epitaxially grown semiconductor material has substantially the same crystalline characteristics as the deposition surface on which the epitaxially grown material is formed. The epitaxial deposition process may employ the deposition chamber of a chemical vapor deposition type apparatus, such as a RPCVD apparatus.

The epitaxially formed fin structures can be a type IV semiconductor containing material layer. In some embodiments, the gas source for the deposition of an epitaxially formed in situ doped n-type semiconductor material may include silicon (Si) deposited from silane, disilane, trisilane, tetrasilane, hexachlorodisilane, tetrachlorosilane, dichlorosilane, trichlorosilane, and combinations thereof. In other examples, when the in situ doped n-type semiconductor material15includes germanium, a germanium gas source may be selected from the group consisting of germane, digermane, halogermane, dichlorogermane, trichlorogermane, tetrachlorogermane and combinations thereof. The temperature for epitaxial silicon germanium deposition typically ranges from 450° C. to 900° C. Although higher temperature typically results in faster deposition, the faster deposition may result in crystal defects and film cracking.

The composition, dopant and dopant concentration of the first portion of the epitaxial growth period may be selected to provide the resistive properties of the body10of the passive resistor. The composition, dopant and the dopant concentration of the second portion of the epitaxial growth period may be selected to provide the semiconductor properties for the channel region20of the MOSFET. Both the body portion10of the passive resistor and the channel region20of the MOSFET may be epitaxially grown in the trench opening using the same epitaxial deposition chamber for both portions of the epitaxial growth process for forming the fin structure. Therefore, the epitaxial fin structure provides for a monolithic structure provides both the body10for the passive resistor and the channel20for the MOSFET.

FIG. 7depicts forming an epitaxial drain region30. In some embodiments, forming the process flow for forming the epitaxial drain region30may begin with recessing the fin structure. The fin structure may be recessed using an etch that is selective to the cap dielectric layer24. Etching the epitaxially formed fin structures forms a recess in the upper portions of the trench opening, i.e., fin structure opening. The recess is filled with a deposited dielectric material to provide the dielectric cap29. In some embodiments, the dielectric cap29may be composed of a nitride, such as silicon nitride, that is deposited using chemical vapor deposition (CVD), such as plasma enhanced chemical vapor deposition (PECVD).

Following formation of the dielectric cap29, the cap dielectric layer24may be removed. The cap dielectric layer24may be removed by an etch process, such as a dry etch process, e.g., reactive ion etching, or wet etch, e.g., chemical etching, in which the etch process may be selective to the upper gate sidewall spacer layer23. Because the epitaxial fin structure is only recessed to a portion of the thickness of the cap dielectric layer24, removing the cap dielectric layer24exposes a sidewall portion of the fin structure that provides the drain region portion of the epitaxially formed fin structure for the MOSFET.

Still referring toFIG. 7, the drain region30may be epitaxially formed on the exposed sidewall of the fin structure. The epitaxial deposition process for forming the drain region30is similar to the epitaxial deposition process that provides the fin structure of epitaxial semiconductor material that provides the body10of the passive resistor and the channel20of the MOSFET. For example, the drain region30may be composed of a type IV semiconductor such as silicon. Therefore, the above process conditions for forming the fin structures is equally applicable for forming at least one embodiment of a drain region30. It is noted that the epitaxial deposition process does not form epitaxial material on surfaces that are not composed of semiconductor material, such as the dielectric surfaces of the upper gate sidewall spacer layer23, and the dielectric surfaces of the dielectric cap29. In the embodiment that is depicted inFIG. 7, the epitaxial semiconductor material that provides the drain region30may have a diamond like geometry.

The epitaxial semiconductor material that provides the drain regions30is doped to an n-type or p-type conductivity. The n-type or p-type dopant may be formed using in situ doping or ion implantation. By “in-situ” it is meant that the dopant that dictates the conductivity type of the semiconductor material is introduced during the process step, e.g., epitaxial deposition, which forms the semiconductor material. In the embodiments described with reference toFIGS. 1-9, the drain region30can be doped to a p-type conductivity. A p-type dopant, such as borane and diborane gas, may be employed to in situ dope the drain region30.

FIG. 8depicts forming a gate structure for the MOSFET of the inverter. In some embodiments, the process flow for forming the gate structure may begin with forming an encapsulating sidewall spacers28around the drain region30; etching portions of the upper gate sidewall spacer layer23, and sacrificial gate layer22with an anisotropic etch that is selective to the lower gate sidewall spacer layer13; employing an isotropic etch to expose the sidewall surfaces of the channel region portion20of the fin structure; and forming a gate dielectric layer17on the exposed sidewall surfaces of the channel region portion20of the fin structure.

The encapsulating sidewall spacers28are formed on the exposed upper sidewalls of the drain region30using deposition process, such as plasma enhanced chemical vapor deposition (PECVD), following by an anisotropic etchback process, such as reactive ion etch. The encapsulating sidewall spacers28may also extend along sidewalls of the dielectric fin cap29, and have an upper surface that is coplanar with the upper surface of the dielectric fin cap29.

Following formation of the encapsulating spacers28, an anisotropic etch process, such as reactive ion etch (RIE), removes the portions of the upper gate sidewall spacer layer23, and the sacrificial gate structure layer22that are not directly underlying the encapsulating sidewall spacers28. The etch process at this stage of the process flow may be selective to the encapsulating spacers28, and the dielectric fin cap29. The remaining portion of the sacrifice gate structure layer22that is underlying the encapsulating spacers28may then be removed by an isotropic etch, such as a plasma etch or wet chemical etch, which may be selective to the dielectric surface3of the sidewall surface of the sacrificial gate layer22. Thereafter, the remaining dielectric surface3may be removed by an etch that is selective to the fin structures, which may also be an isotropic etch. Following the isotropic etch, the sidewalls of the fin structures that provide the channel region20of the MOSFET may be exposed.

Referring toFIG. 8, the gate dielectric17may then be formed on the exposed surfaces of the channel portion20of the fin structure. In some embodiments the gate dielectric17may be composed of a high-k gate dielectric. As used herein, “high-k” denotes a dielectric material featuring a dielectric constant (k) higher than the dielectric constant of SiO2at room temperature. For example, the gate dielectric17may be composed of a high-k oxide such as, for example, HfO2, ZrO2, Al2O3, TiO2, La2O3, SrTiO3, LaAlO3, Y2O3and mixtures thereof. The gate dielectric17may be deposited using chemical vapor deposition methods, such as plasma enhanced chemical vapor deposition (PECVD). In other embodiments, the gate dielectric17may be deposited using atomic layer deposition (ALD).

FIG. 8further depicts forming a metal work function adjusting layer18on the gate dielectric layer17. The metal work function adjusting layer18may be deposited by CVD, e.g., plasma enhanced chemical vapor deposition (PECVD). In other examples, the metal work function adjusting layer18may be deposited using physical vapor deposition, such as sputtering. In yet further examples, the metal work function adjusting layer18may be deposited using plating, electroplating, electroless deposition, and combinations thereof.

After the deposition of the metal work function adjusting layer18, an anisotropic etch process, such as reactive ion etch (RIE), removes the portions of the metal work function adjusting layer and the gate dielectric layer17that are not protected by the overlying encapsulating sidewall spacers28and the dielectric fin cap29.

FIG. 8also depicts forming a gate electrode16on the stack of the remaining portions of the work function adjusting metal layer18and the gate dielectric17. The gate electrode16may be formed directly on the metal work function adjusting layer17and may be composed of a metal selected from tungsten (W), tungsten nitride (WN) or combinations thereof. The material layer for the gate electrode16may be deposited by CVD, e.g., plasma enhanced chemical vapor deposition (PECVD); and/or deposited using physical vapor deposition, e.g., sputtering. In another embodiment, the material layer for the gate electrode16may be deposited using plating, electroplating, electroless deposition, and combinations thereof. Following deposition, the material layer for the gate electrode16may be recessed by an etch process, such as reactive ion etch (RIE), to provide the desired height for the gate electrode16. Once the gate electrode height is set, the gate electrode16may be patterned to provide its final geometry by employing photolithography and etch processing.

Referring toFIG. 8, after patterning the gate structure15to its final geometry, an interlevel dielectric layer40may be formed. The interlevel dielectric layer40may be deposited using chemical vapor deposition, deposition from solution, spin on deposition and combinations thereof. Following deposition, a planarization process may be applied to the upper surface of the interlevel dielectric layer40.

FIG. 9depicts one embodiment of forming an epitaxial semiconductor material25having the source type doping on the fin structure between the portion of the fin structure that provides the body10of the passive resistor and the portion of the fin structure that provides the channel20of the MOSFET. Forming the epitaxial semiconductor material25having the source type doping may begin with forming a via through the interlevel dielectric layer40exposing a portion of the sacrificial electrical contact layer21. The via opening may be formed using photolithography and etch processes. For example, a photoresist mask may be formed exposing the portion of the dielectric material layers in which the via opening is to be formed, wherein following formation of the photoresist mask, the via opening may be etched into the interlevel dielectric40using an etch process, such as reactive ion etch. The via opening formed at this stage may provide the via opening for the subsequently formed output via contact41.

Following the formation of the aforementioned via opening to the sacrificial electrical contact layer21, the sacrificial electrical contact layer21can be removed by an etch that is selected to the fin structure. The etch process is isotropic, and is applied to the sacrificial electrical contact layer21through the via. The etch process may be provided by plasma etching. Following removal of the sacrificial electrical contact layer21, the sidewall of the portion of the fin structure between the body portion10for the passive resistor, and the channel portion20for the MOSFET is exposed, and provides an epitaxial deposition surface. The epitaxial deposition process then forms the epitaxial semiconductor material25having the source type doping on the exposed portion of the fin structure that provides the epitaxial deposition surface.

The epitaxial deposition process for forming the epitaxial semiconductor material25having the source type doping is similar to the epitaxial deposition process that provides the drain region30, as well as the epitaxial deposition process that provides the fin structure of epitaxial semiconductor material that provides the body10of the passive resistor and the channel20of the MOSFET. For example, the epitaxial semiconductor material25having the source type doping may be composed of a type IV semiconductor such as silicon. Therefore, the above process conditions for forming the fin structures is equally applicable for forming at least one embodiment of an epitaxial semiconductor material25having the source type doping. In the embodiment that is depicted inFIG. 9, the epitaxial semiconductor material that provides the epitaxial semiconductor material25having the source type doping may have a diamond like geometry. The deposition gasses reach the epitaxial deposition surface by introduction through the via opening and traveling along the space created by removing the sacrificial electrical contact layer21

The epitaxial semiconductor material25having the source type doping is doped to an n-type or p-type conductivity. The n-type or p-type dopant may be formed using in situ doping. In the embodiments described with reference toFIGS. 1-9, the epitaxial semiconductor material25having the source type doping can be doped to a p-type conductivity. A p-type dopant, such as borane and diborane gas, may be employed to in situ dope the epitaxial semiconductor material25having the source type doping.

Following the formation of the epitaxial semiconductor material25having the source type doping, an electrically conductive material, such as a metal, e.g., copper, aluminum, titanium, tungsten, platinum, etc, is deposited filling the via opening and the space provided by removing the sacrificial electrical contact layer21. The electrically conductive material filling this space can provide the electrically conductive line14to the output via contact41that provides an output for the inverter device. The electrically conductive material may be deposited into the via opening using physical vapor deposition (PVD). Examples of PVD processes suitable for depositing the electrically conductive material include plating, electroplating, electroless plating, sputtering and combinations thereof.

In some embodiment, forming the output via contact41is part of a process sequence that also includes forming the gate contact via42and the drain contact via43. Both the gate conductive via42and the drain contact via43are composed of electrically conductive materials, such as metals, and are formed using photolithography, etching and deposition process steps. It is noted that the above process sequence only describes one embodiment of a process flow for forming the inverter that is depicted inFIGS. 1-3, and that other process flows including steps not described above may be applicable to the methods disclosed herein.

FIGS. 10-12depict an inverter including a passive electrical device, e.g., a passive resistor, integrated with a metal oxide semiconductor field effect transistor (MOSFET) having a vertical orientation, in which the body10of passive resistor is positioned atop the channel20of the vertically orientated MOSFET. In the embodiment that is depicted inFIGS. 10-12, the channel20of the vertically orientated MOSFET positioned between the body10of the passive resistor and a supporting substrate5.FIG. 12is a circuit diagram of the inverter depicted inFIGS. 10 and 11. In some embodiments of the inverter depicted inFIGS. 10-12, the vertically orientated MOSFET is an n-type MOSFET having source and drain regions doped to an n-type conductivity.

The inverter depicted inFIGS. 1-3is similar to the inverter that is depicted inFIGS. 10-12. Therefore, the structures having reference numbers inFIGS. 10-12that have the same reference numbers as structures depicted inFIGS. 1-3(also including the method described with reference toFIGS. 4-9) are equivalent to those same designated structures. Therefore, the description of the structures inFIGS. 1-9having the same references numbers as the structures labeled inFIGS. 10-13provide one embodiment of the description of the structures depicted inFIGS. 10-13.

In the embodiment that is depicted inFIG. 9, a heavily doped source region layer7(GROUND (for the inverter) is present on a counter doped region6that is overlying a supporting substrate5. The MOSFET depicted inFIGS. 10-13is an n-type MOSFET. Therefore, the heavily doped source region layer7is doped to an n-type conductivity. As the counter doped region6has an opposite conductivity type as the heavily doped source region layer7, the counter doped region6is doped to an p-type conductivity. The heavily doped source region layer7can provide both the source region of the MOSFET (as inFIG. 10) and an electrode for the passive resistor (as inFIG. 1).

In the embodiment depicted inFIGS. 10-12, the channel20of the MOSFET having a vertical orientation is present in direct contact with the heavily doped source region layer7, and is monolithically integrated with a body portion10of the passive resistor. This is provided by epitaxial growth of both the channel region20of the vertical MOSFET and the body10of the passive resistor in the same fin geometry opening using the heavily doped source region layer7as the epitaxial growth surface. The body10of the passive resistor and the channel region20may be composed of a type IV semiconductor, such as silicon, germanium or silicon germanium, and/or a type III-V semiconductor material, such as gallium arsenide (GaAs). Similar to the embodiments described with referenced toFIGS. 1-9, the dimensions, material composition, dopant type and dopant concentration of the resistor body10is selected to provide the resistance properties of the passive resistor for the inverter. For example, the body10of the passive resistor has a greater resistance that the channel portion20of the monolithically integrated structure.

A gate structure15is present about the channel portion20of the fin structure. The gate structure15has been described above with reference toFIGS. 1-9.

Still referring toFIG. 10, a doped epitaxial semiconductor material having drain doping30ais present at the interface of the channel region of the MOSFET, and the body10of the passive resistor. The doped epitaxial semiconductor material having drain doping25may be doped to an n-type or p-type conductivity, and may be composed of a type IV semiconductor material, e.g., silicon, or a type III-V semiconductor material, e.g., gallium arsenide (GaAs). The geometry of the doped epitaxial semiconductor material having the drain doping30amay be facetted having sidewalls coming to an apex in a diamond like shape. The doped epitaxial semiconductor material having the drain doping30amay provide a drain region for the MOSFET, as well as provide a terminal for the passive resistor that includes the resistor body10. In the embodiment depicted inFIGS. 10-12, the doped epitaxial semiconductor material having the drain doping30ais doped to an n-type conductivity.

Referring toFIGS. 10 and 11, the doped epitaxial semiconductor material having the drain doping30amay be contacted by a metal portion of a segmented line14. The metal used for the segmented line14may be provided by copper, aluminum, silver, gold, platinum, tungsten, tantalum and combinations thereof.

The body10of the passive resistor is present atop the doped epitaxial semiconductor material having the drain doping30a. Similar, to the embodiment described with reference toFIGS. 1-3, the resistance value of the body10for the passive resistor is given by R=ρL/A, where p is the resistivity of the material, L is the length of the resistor in the direction of current flow, and A the cross sectional area of the resistor perpendicular to current flow. The vertical structure allows L, i.e., the height of the resistor structure) to be arbitrarily large, while A (i.e., the footprint of the resistor/transistor pair) to be small. Both a large L value, and a small A value simultaneously favoring a large R. The length L1of the body10of the passive resistor can be increased to increase the resistance of the passive resistor. This can be a function of the length of the epitaxial growth process for forming the body10of the passive resistor.

An epitaxially formed drain region35is present on the end of the body portion10that is opposite the end of the boy portion10for the passive resistor that is in closest proximity to the channel region20of the MOSFET. The epitaxially formed drain region35may be composed of a type IV semiconductor, such as silicon, silicon germanium and/or germanium, or the epitaxially formed drain region may be composed of a type III-V semiconductor, such as gallium arsenide (GaAs). The epitaxially formed drain region35may be doped to an n-type or p-type conductivity. In the embodiment depicted inFIGS. 10-12, the epitaxially formed drain region35is doped to an n-type conductivity. The geometry of the epitaxial formed drain region35may be facetted having sidewalls coming to an apex in a diamond like shape. In the embodiment depicted inFIGS. 10-12, the drain region is n-type.

Referring toFIGS. 10-12, a drain contact via45is in direct contact with the epitaxial formed drain region35. The drain contact via45can be composed of an electrically conductive material, such as a doped semiconductor or a metal, and provides for contact of the inverter to the positive power supply (VDD). The inverter also includes a gate contact44that is in direct contact with the gates structure15, in which the gate contact44provides the input to the inverter. A source contact (GRND)46is also present.

The structures described above with reference toFIGS. 10-12are now described in more detail with reference toFIGS. 13-17.

FIG. 13depicts one embodiment of material stack that provides an initial structure for use in a method for forming an inverter structure, as depicted inFIGS. 10-12. In some embodiments, the initial material stack includes a supporting substrate5, a counter doped layer6, and a heaving doped source region layer7that is present atop the counter doped layer. Each of these layers have been described above. For example, each of these structures designated by the same reference numbers have been described above with reference toFIG. 4. Therefore, the description for these material layers provided with reference toFIG. 4is suitable for describing the material layers having the same reference numbers inFIG. 13with the exception that the heavily doped source region layer7depicted inFIG. 4is a p-type doped layer, and the heavily doped source region layer7depicted inFIG. 13is an n-type doped layer.

Still referring toFIG. 13, a stack of material layer for forming a gate structure is present atop the heavily doped source layer7. The stack for forming the gate structure including a lower gate sidewall spacer31present atop the heavily doped source layer7, a sacrificial gate layer32present on the lower gate sidewall spacer31, and a upper gate sidewall spacer33present atop the sacrificial gate layer32. The lower gate sidewall spacer31that is depicted inFIG. 13is similar to the first dielectric layer that provides the lower gate sidewall spacer13depicted inFIG. 4. Therefore, the description of the first dielectric layer that provides the lower gate sidewall spacer depicted inFIG. 4provides the description of at least one embodiment of the lower gate sidewall spacer depicted inFIG. 13. The sacrificial gate layer32that is depicted inFIG. 13is similar to the sacrificial gate layer22depicted inFIG. 4. Therefore, the description of the sacrificial gate layer22depicted inFIG. 4is suitable for describing one embodiment of the sacrificial gate layer32that is depicted inFIG. 13. The upper gate sidewall spacer33depicted inFIG. 13is similar to the second dielectric layer that provides the upper gate sidewall spacer23depicted inFIG. 4. Therefore, the description of the second dielectric layer that provides the upper gate sidewall spacer depicted inFIG. 4provides the description of at least one embodiment of the upper gate sidewall spacer depicted inFIG. 13.

A sacrificial electrical contact layer34, which may also be referred to as a dummy electrical contact layer, is present on the upper gate sidewall spacer33. The sacrificial electrical contact layer34depicted inFIG. 13is similar to the sacrificial electrical contact layer21depicted inFIG. 4. Therefore, the description of the sacrificial electrical contact layer21depicted inFIG. 4provides the description of at least one embodiment of the sacrificial electrical contact layer34depicted inFIG. 13.

Still referring toFIG. 13, a dielectric stack is present atop the aforementioned structure that corresponds to the level in which the body10of the passive resistor is to be formed. The dielectric stack includes a first resistor body level spacer8athat is present atop the sacrificial electrical contact layer34, a resistor body level dielectric layer9apresent on the first resistor body level spacer8a, and a second resistor body level spacer11ais present on the resistor body level dielectric layer9a. A description of each of the aforementioned layers is provided by the description of the resistor body level spacer8, the resistor body level dielectric layer9, and the second resistor body level spacer11inFIG. 4.

A cap dielectric layer24is formed on the second resistor body level spacer11a. The cap dielectric layer that is depicted inFIG. 13is similar to the cap dielectric layer that is depicted inFIG. 4.

FIG. 14depicts one embodiment of forming a trench through the material stack depicted inFIG. 13to expose a surface of a heavily doped epitaxial source layer7, and epitaxially forming a fin structure in the opening, in which the heavily doped source layer7provides a surface for epitaxial growth. The epitaxial formed fin structure includes a first portion, i.e., including the channel portion20, for the MOSFET that is formed first on the heavily doped epitaxial source layer followed by a second portion of the fin structure, i.e., including the body portion10, for the passive resistor. In some embodiments, dielectric surfaces3,4may be formed on the exposed semiconductor surfaces of the trench sidewalls prior to the epitaxial growth process. The methods for forming the trench and the epitaxial growth process for forming the fin structure depicted inFIG. 14are similar to the trench forming and epitaxial growth process that has been described above with reference toFIGS. 5 and 6. Therefore, with adjustments made to form the channel region portion20prior to the body portion, the methods for trench forming and epitaxial growth that are described with reference toFIGS. 5 and 6are suitable for description with reference toFIG. 14.

FIG. 15depicts forming an epitaxial semiconductor material30ahaving the drain doping between the section of the fin structure that provides the channel region20of the MOSFET and the section of the fin structure that provides the body10of the passive resistor. The epitaxial semiconductor material30ahaving the drain doping depicted inFIG. 15may be doped to an n-type conductivity. In some embodiments, the process sequence depicted inFIG. 15includes forming a via opening to the sacrificial electrical contact line34, removing the sacrificial electrical contact line34using an etchant that exposes the sidewall of the epitaxial fin structure, and epitaxially forming the epitaxial semiconductor material30ahaving the drain doping on the exposed sidewall of the fin structure. A similar process sequence has been described with reference toFIG. 9, which can provide the details for at least one method of forming the epitaxial semiconductor material30athat is depicted inFIG. 15. After forming the epitaxial semiconductor material30ahaving the source type doping, the metal layer identified by reference number14can be deposited in the space that is produced by removing the sacrificial electrical contact line34.

FIG. 16depicts one embodiment of forming an epitaxial drain region35. The epitaxial drain region depicted inFIG. 16may be doped to an n-type conductivity. The epitaxial drain region35that is depicted inFIG. 16is similar to the epitaxial drain region30that is depcited inFIG. 7. Therefore, the process sequence depicted inFIG. 7provides one embodiment of a method for forming the epitaxial drain region35that is depicted inFIG. 16. For example, forming the epitaxial drain region35may include a process sequence that includes recessing the epitaxial fin structure, forming a dielectric cap29aatop the recessed surface of the epitaxial fin structure, removing the cap dielectric layer24to expose sidewalls of the epitaxial fin structure; and forming the epitaxial drain region35on the sidewalls of the epitaxial fin structure using an epitaxial deposition process in combination with an in situ doping process.

FIG. 17depicts patterning the structure depicted inFIG. 16as a step of a process flow for forming the gate structure15for the MOSFET of the inverter, as depicted inFIGS. 10-12. The process flow for forming the gate structure15may begin with forming encapsulating sidewalls spacers28athat are formed on the sidewalls of the epitaxial drain region35. The encapsulating sidewall spacers having reference number28ahave been described above by the encapsulating sidewall spacers having reference number28inFIG. 8. Following the formation of the encapsulating sidewall spacers28a, an anisotropic etch process, such as reactive ion etch (RIE), employing the encapsulating sidewall spacers28aand the dielectric cap29aas an etch mask, remove the exposed portions of the dielectric stack11a,9a,8acorresponding to the body10of the passive resistor, removed the exposed portion of the upper gate sidewall spacer33and remove the exposed portions of the sacrificial gate layer32. Due to the anisotropic nature of the aforementioned etch sequence, a remaining portion of the sacrificial gate layer32′ remains underlying the encapsulating sidewall spacers28a. The remaining portion of the sacrificial gate layer32′ and the dielectric surface3on the channel portion20of the fin structure may then be removed using an isotropic etch.

Referring toFIGS. 10-12, the gate structure15including the gate dielectric17, the metal work function adjusting layer18, and the gate electrode16may then be formed on the channel portion20of the fin structure. Further details on forming the gate structure15have been described above in the gate structure forming sequence that is described with reference to FIGS.1-3. Following forming the gate structure15, an interlevel dielectric40is deposited followed by the formation of the gate contact44and the drain contact45.

It is noted that the MOSFET devices depicted inFIGS. 1-17are not the only vertical semiconductor devices suitable for use with the methods and structures described herein. For example, the JFET devices may also be integrated with passive resistors in inverter structures as depicted inFIGS. 18-21. A junction field effect transistor (JFET) does not include a gate dielectric layer in the gate structure of the device, which is a component of the gate structure to a metal oxide semiconductor field effect transistor (MOSFET). JFETs are voltage-controlled in that they do not need a biasing current. Electric charge flows through a semiconducting channel between source and drain terminals. By applying a reverse bias voltage to a gate terminal, the channel is “pinched”, so that the electric current is impeded or switched off completely. A JFET is usually on when there is no potential difference between its gate and source terminals. If a potential difference of the proper polarity is applied between its gate and source terminals, the JFET will be more resistive to current flow, which means less current would flow in the channel between the source and drain terminals. Thus, JFETs are sometimes referred to as depletion-mode devices.

FIGS. 18 and 19depict one embodiment of an inverter including a passive electrical device, e.g., a passive resistor, integrated with a junction field effect transistor (JFET) having a vertical orientation, in which the body10of the passive resistor is positioned between the channel20of the vertically orientated JFET and a supporting substrate5. The inverter depicted inFIGS. 18 and 19is similar to the inverter depicted inFIGS. 1-3with the exception that a gate structure to the JFET device does not include a gate dielectric, and the gate structure to the MOSFET device does include a gate dielectric.

Therefore, the structures having reference numbers inFIGS. 18 and 19that have the same reference numbers as structures depicted inFIGS. 1-3are equivalent to those same designated structures. Therefore, the description of the structures inFIGS. 1-9having the same references numbers as the structures labeled inFIGS. 18 and 19provide one embodiment of the description of the structures depicted inFIGS. 18 and 19.

The gate structure of the JFET device depicted inFIGS. 18 and 19may include an epitaxially formed doped semiconductor, as depicted by reference number70. The JFET gate structure70may be composed of silicon (Si), but other type IV and/or type III-IV semiconductor materials may be equally applicable for the JFET gate structure70. In some examples, the JFET gate structure70is doped to an n-type conductivity.

It is noted that the inverters depicted inFIGS. 18 and 19can be formed using a method similar to the method described with reference toFIGS. 1-9with the exception of the description of forming the gate structure. Instead of forming a gate structure including a gate dielectric17, work function adjusting layer18and a gate electrode16, the gate structure for the JFET is an epitaxial semiconductor that is epitaxially formed and insitu doped, e.g., n-type doped, on the exposed channel region20of the semiconductor fin structure.

FIGS. 20 and 21depict one embodiment of an inverter including a passive electrical device, e.g., a passive resistor, integrated with a junction field effect transistor (JFET) having a vertical orientation, in which the body10of the passive resistor is positioned atop the channel region20of the vertically orientated JFET, the channel region20of the vertically orientated JFET is positioned between the body10of the passive resistor and a supporting substrate5.

The inverter depicted inFIGS. 20 and 21is similar to the inverter depicted inFIGS. 10-12with the exception that a gate structure to the JFET device does not include a gate dielectric, and the gate structure to the MOSFET device does include a gate dielectric. Therefore, the structures having reference numbers inFIGS. 20 and 21that have the same reference numbers as structures depicted inFIGS. 10-12are equivalent to those same designated structures. Therefore, the description of the structures inFIGS. 10-17having the same references numbers as the structures labeled inFIGS. 20 and 21provide one embodiment of the description of the structures depicted inFIGS. 20 and 21.

The gate structure of the JFET device depicted inFIGS. 20 and 21may include an epitaxially formed doped semiconductor, as depicted by reference number70. The JFET gate structure70may be composed of silicon (Si), but other type IV and/or type III-IV semiconductor materials may be equally applicable for the JFET gate structure70. In some examples, the JFET gate structure70is doped to an n-type conductivity.

It is noted that the inverters depicted inFIGS. 20 and 21can be formed using a method similar to the method described with reference toFIGS. 10-17with the exception of the description of forming the gate structure. Instead of forming a gate structure including a gate dielectric17, work function adjusting layer18and a gate electrode16, the gate structure for the JFET is an epitaxial semiconductor that is epitaxially formed and insitu doped, e.g., n-type doped, on the exposed channel region20of the semiconductor fin structure.