IMAGING DEVICE AND ELECTRONIC DEVICE

Provided are an imaging device and an electronic device capable of suppressing deterioration in characteristic. An imaging device is provided with an N-type first semiconductor region, a P-type second semiconductor region in contact with one surface of the first semiconductor region, a light absorbing region provided on a side opposite to the first semiconductor region across the second semiconductor region, and an anode electrode provided at a position facing the second semiconductor region across the light absorbing region. The anode electrode includes a P-type semiconductor having a refractive index of 1.8 or larger and an optical bandgap of 1.9 eV or larger.

TECHNICAL FIELD

The present disclosure relates to an imaging device and an electronic device.

BACKGROUND ART

An imaging device using an avalanche photodiode is disclosed (refer to Patent Document 1).

CITATION LIST

Patent Document

SUMMARY OF THE INVENTION

Problems to be Solved by the Invention

An imaging device using an avalanche photodiode includes an N-type semiconductor region, a P-type semiconductor region provided closer to a light incident surface than this N-type semiconductor region, a light absorbing region (photoelectric conversion region) provided closer to the light incident surface than the P-type semiconductor region, and an anode electrode in contact with the light absorbing region. An avalanche amplification region is formed on a PN junction surface between the N-type semiconductor region and the P-type semiconductor region described above. Electrons generated by photoelectric conversion in the light absorbing region propagate to the avalanche amplification region and are subjected to avalanche amplification.

The anode electrode is formed by multistage ion implantation of P-type impurities at high acceleration into a semiconductor in a region adjacent to the light absorbing region (for example, an inter-pixel isolation region). In the ion implantation, since an implantation amount of impurities tends to vary in a depth direction of the implantation, it is difficult to form the anode electrode at a uniform impurity concentration. When the impurity concentration of the anode electrode is non-uniform, a resistance value of the anode electrode varies, and a characteristic of the imaging device might be deteriorated.

The present disclosure has been made in view of such circumstances, and an object thereof is to provide an imaging device and an electronic device capable of suppressing deterioration in characteristic.

Solutions to Problems

An imaging device according to an aspect of the present disclosure is provided with an N-type first semiconductor region, a P-type second semiconductor region in contact with one surface of the first semiconductor region, a light absorbing region provided on a side opposite to the first semiconductor region across the second semiconductor region, and an anode electrode provided at a position facing the second semiconductor region across the light absorbing region. The anode electrode includes a P-type semiconductor having a refractive index of 1.8 or larger and an optical bandgap of 1.9 eV or larger.

With this arrangement, as the P-type semiconductor, for example, P-type amorphous silicon carbide (a-SiC), P-type polysilicon carbide (poly-SiC), P-type amorphous silicon nitride (a-SiN), or P-type polysilicon nitride (poly-SiN) may be used. Since these films may be formed by a chemical vapor deposition (CVD) method while being doped with P-type impurities such as boron (B) in situ, a P-type impurity concentration in the film may be made uniform or substantially uniform. Therefore, the imaging device may suppress variation in electric resistance of the anode electrode, so that this may suppress deterioration in characteristic (for example, variation in sensitivity among a plurality of pixels) due to this variation.

An electronic device according to an aspect of the present disclosure is provided with a light source that emits light of a wavelength band set in advance, and an imaging device that photoelectrically converts the light and outputs a signal. The imaging device is provided with an N-type first semiconductor region, a P-type second semiconductor region in contact with one surface of the first semiconductor region, a light absorbing region provided on a side opposite to the first semiconductor region across the second semiconductor region, and an anode electrode provided at a position facing the second semiconductor region across the light absorbing region. The anode electrode includes a P-type semiconductor having a refractive index of 1.8 or larger and an optical bandgap of 1.9 eV or larger.

With this arrangement, since the electronic device is provided with the above-described imaging device, so that this may suppress deterioration in characteristic due to variations in electric resistance of the anode electrode.

MODE FOR CARRYING OUT THE INVENTION

Hereinafter, an embodiment of the present disclosure is described with reference to the drawings. In the illustration of the drawings referred to in the following description, the same or similar portions are denoted by the same or similar reference signs. It should be noted that the drawings are schematic, and a relationship between a thickness and a planar dimension, a ratio of the thicknesses between layers, and the like are different from actual ones. Therefore, specific thicknesses and dimensions should be determined in consideration of the following description. Furthermore, it goes without saying that dimensional relationships and ratios are partly different between the drawings.

Definition of directions such as upward and downward directions in the following description is merely the definition for convenience of description, and does not limit the technical idea of the present disclosure. For example, it goes without saying that if a target is observed while being rotated by 90°, the upward and downward directions are converted into rightward and leftward directions, and if the target is observed while being rotated by 180°, the upward and downward directions are inverted.

In the following description, the direction is sometimes described using terms such as an X-axis direction, a Y-axis direction, and a Z-axis direction. For example, the X-axis direction and the Y-axis direction are directions parallel to a back surface10bof a semiconductor substrate10. The Z-axis direction is a direction perpendicular to the back surface10bof the semiconductor substrate10. The Z-axis direction is a thickness direction of the semiconductor substrate10, and is also a thickness direction of a sensor substrate1including the semiconductor substrate10. The X-axis direction, the Y-axis direction, and the Z-axis direction are orthogonal to each other.

In the following description, + or − is sometimes added as for P or N indicating a conductivity type of a semiconductor. A semiconductor region to which + or − is added means that an impurity concentration thereof is relatively higher or lower than that of the semiconductor region to which + or − is not added. However, even in the semiconductor regions to which the same P and P (or N and N) are added, it does not mean that the impurity concentrations of the semiconductor regions are exactly the same.

First Embodiment

FIG.1is a cross-sectional view schematically depicting a configuration example of an imaging device100according to a first embodiment of the present disclosure. The imaging device100depicted inFIG.1is, for example, a back-illuminated solid-state imaging device. As depicted inFIG.1, the imaging device100includes a sensor substrate1and a logic substrate3joined to a front surface1a(inFIG.1, a lower surface) side of the sensor substrate1. Light to be detected by the sensor substrate1is, for example, infrared light, and a wavelength band thereof is of 900 nm or longer and 1100 nm or shorter.

The sensor substrate1includes a semiconductor substrate10, a plurality of pixels50provided on the semiconductor substrate10, a light-shielding electrode70(an example of a “light-shielding pixel isolation unit” of the present disclosure) provided on the semiconductor substrate10, and a microlens80(an example of a “lens body” of the present disclosure) provided on a back surface10b(inFIG.1, an upper surface) side of the semiconductor substrate10. The plurality of pixels50is arranged side by side in a direction parallel to the back surface10bof the semiconductor substrate10(for example, in an X-axis direction and a Y-axis direction). The pixel50is, for example, an avalanche photodiode, a single photon avalanche diode (SPAD) as an example. The light-shielding electrode70is arranged in a region between adjacent pixels among the plurality of pixels50. The light-shielding electrode70shields light between one pixel50and another pixel50adjacent to each other and isolates them from each other.

The semiconductor substrate10is, for example, a single-crystal silicon (Si) substrate. Alternatively, the semiconductor substrate10may be a single-crystal Si layer. The single-crystal Si layer may be obtained by, for example, forming a Si layer on a single-crystal support substrate not depicted by an epitaxial growth method and isolating the support substrate from the formed Si layer. The semiconductor substrate10is provided with an N-type first semiconductor region11, a P-type second semiconductor region12, a P−-type third semiconductor region13, a P−−-type fourth semiconductor region14, a P−-type fifth semiconductor region15, a P+-type sixth semiconductor region16, an N+-type seventh semiconductor region17, and a P+-type eighth semiconductor region18.

The P-type second semiconductor region12is arranged on one surface11b(inFIG.1, an upper surface) of the N-type first semiconductor region11. The P-type second semiconductor region12is in contact with one surface11bof the N-type first semiconductor region11. A portion in which the first semiconductor region11and the second semiconductor region12are in contact with each other is a PN junction of the SPAD.

The P−-type third semiconductor region13is arranged on the P-type second semiconductor region12, and the P−−-type fourth semiconductor region14is arranged on the P−-type third semiconductor region13. The P−-type third semiconductor region13and the P−−-type fourth semiconductor region14are an example of a “light absorbing region” of the present disclosure. The P−-type third semiconductor region13is arranged so as to cover the N-type first semiconductor region11and the P-type second semiconductor region12from a light irradiation surface (for example, a back surface) side, and is in contact with each of the first semiconductor region11and the second semiconductor region12. Furthermore, the P−−-type fourth semiconductor region14is arranged so as to cover the P−-type third semiconductor region13from the light irradiation surface side, and is in contact with the third semiconductor region13.

P−P—The P−-type fifth semiconductor region15and the P+-type sixth semiconductor region16are arranged on the other surface11a(inFIG.1, a lower surface) side of the first semiconductor region11. The P−-type fifth semiconductor region15is in contact with the other surface11aof the N-type first semiconductor region11. The P+-type sixth semiconductor region16faces a front surface10a(inFIG.1, a lower surface) of the semiconductor substrate10. The fifth semiconductor region15is arranged between the first semiconductor region11and the sixth semiconductor region16. The N+-type seventh semiconductor region17is provided on the other surface11aside of the first semiconductor region11and is in contact with the front surface10a(inFIG.1, the lower surface) of the semiconductor substrate10.

A magnitude relationship of an N-type impurity concentration between the first semiconductor region11and the seventh semiconductor region17, and a P-type impurity concentration in each of the second semiconductor region12, the third semiconductor region13, the fourth semiconductor region14, the fifth semiconductor region15, and the sixth semiconductor region16is as indicated by a superscript of + or − as described above. That is, the N-type impurity concentration is higher in the N+-type seventh semiconductor region17than in the N-type first semiconductor region11. The P-type impurity concentration is lower in the P−-type third semiconductor region13than in the P-type second semiconductor region, and the P-type impurity concentration is lower in the P−−-type fourth semiconductor region14than in the P−-type third semiconductor region13.

Note that, the P−−-type fourth semiconductor region14may be an intrinsic semiconductor region (of i-type). Furthermore, the third semiconductor region13and the fourth semiconductor region14may include one semiconductor region a conductivity type of which is the P-type or P−-type. That is, the “light absorbing region” of the present disclosure may include one semiconductor region the conductivity type of which is the P-type or P−-type.

Furthermore, the sensor substrate1includes an anode electrode21and a first insulating film23(an example of an “insulating film” of the present disclosure) and a second insulating film25provided on a side opposite to the light absorbing region across the anode electrode21. In the semiconductor substrate10, a trench H1is formed from the back surface10bto the front surface10aside in a region between the adjacent pixels. The anode electrode21is provided continuously from the back surface10bof the semiconductor substrate10to an inner side surface and a bottom surface of the trench H1.

For example, the anode electrode21includes a first site211arranged on the back surface10bof the semiconductor substrate10and a second site212arranged in the trench H1. The first site211is in contact with the P−−-type fourth semiconductor region14in a Z-axis direction. The second site212faces the second semiconductor region12in the X-axis direction and the Y-axis direction intersecting with (for example, orthogonal to) the Z-axis direction, and is in contact with the P−−-type fourth semiconductor region14. The second site212is in contact with the P−−-type fourth semiconductor region14on the inner side surface of the trench H1, and is in contact with the P+-type eighth semiconductor region18on the bottom surface of the trench H1.

The anode electrode21includes a P-type semiconductor having a refractive index of 1.8 or larger and an optical bandgap of 1.9 eV or larger. As such P-type semiconductor, P-type amorphous silicon carbide (a-SiC), P-type polysilicon carbide (poly-SiC), P-type amorphous silicon nitride (a-SiN), or P-type polysilicon nitride (poly-SiN) are exemplified. Furthermore, boron (B) is exemplified as the P-type impurities contained in the anode electrode21. In order to lower resistivity of the anode electrode21, a boron concentration in the anode electrode21(or a boron concentration in a-SiN) is preferably 1×1018cm−3or longer.

Since the anode electrode21includes the P-type semiconductor, this also serves as a hole accumulation layer. The hole accumulation layer may cause electrons present at an interface between this hole accumulation layer and another layer (for example, the fourth semiconductor region14or the first insulating film23) to disappear by recombination, and may suppress a dark current caused by the electrons present at the interface.

The first insulating film23is provided continuously from the back surface10bof the semiconductor substrate10to the inner side surface and the bottom surface of the trench H1so as to cover the anode electrode21. The first insulating film23is in contact with the anode electrode21. The light-shielding electrode70is arranged in the trench H1covered with the anode electrode21and the first insulating film23, and is in contact with the first insulating film23. The light-shielding electrode70is connected to, for example, a wire having the same potential as that of the anode electrode21. The second insulating film25is provided on the back surface10bside of the semiconductor substrate10, and covers the first insulating film23and the light-shielding electrode70. The microlens80is provided on a side opposite to the light absorbing region across the first insulating film23in a thickness direction of the light absorbing region (for example, in the Z-axis direction). For example, the microlens80is provided on the second insulating film25. In the imaging device100, a side on which the microlens80is provided is a light incident surface side.

The first insulating film23preferably includes a material having a refractive index smaller than that of the P-type semiconductor (for example, a P-type a-SiC film, a P-type poly-SiC film, a P-type a-SiN film, or a P-type poly-SiN film) forming the anode electrode21. For example, the first insulating film23includes an aluminum oxide film (Al2O3film), a silicon oxide film (SiO2film), or a hafnium oxide film (HfO2film). While a refractive index n of the P-type a-SiC film is about 2.6, the refractive index n of the Al2O3film is about 1.76, the refractive index n of the SiO2film is about 1.46, and the refractive index of the HfO2film is about 1.9. Since the magnitude relationship of the refractive index is defined between the first insulating film23and the anode electrode21in this manner, it is possible to suppress reflection of the incident light on the sensor substrate1at the interface between the first insulating film23and the anode electrode21.

Note that, in a case where the first insulating film23includes the Al2O3film or the HfO2film, the first insulating film23also serves as a negative fixed charge film. The negative fixed charge film may trap electrons present at an interface between this negative fixed charge film and another layer (for example, the anode electrode21or the second insulating film), and may suppress a dark current caused by the electrons present at the interface. Since the Al2O3film and the HfO2film have a stronger function as the negative fixed charge film than that of the SiO2film, it is more preferable to use the Al2O3film or the HfO2film for the first insulating film23. Therefore, the function as the hole accumulation layer of the anode electrode21may be further reinforced.

The second insulating film25preferably includes a material having the same refractive index as that of the first insulating film23or a material having a smaller refractive index than that of the first insulating film23. For example, the second insulating film25includes a SiO2film. This makes it possible to suppress the reflection of the incident light on the sensor substrate1at the interface between the second insulating film25and the first insulating film23.

The N-type first semiconductor region11, the P-type second semiconductor region12, the P−-type third semiconductor region13, the P−−-type fourth semiconductor region14, the P−-type fifth semiconductor region15, the P+-type sixth semiconductor region16, the N+-type seventh semiconductor region17, the P+-type eighth semiconductor region18, the anode electrode21, the first insulating film23, the second insulating film25, and the microlens80are arranged in each of the plurality of pixels50.

The P−-type third semiconductor region13and the P−−-type (or i-type) fourth semiconductor region14serve as the light absorbing region (photoelectric conversion region) of the SPAD. The P+-type sixth semiconductor region16serves as a region for ohmic connection of the P-type fifth semiconductor region15to a contact electrode CGND to be described later. The P+-type eighth semiconductor region18serves as a region for ohmic connection of the anode electrode21to a contact electrode CA to be described later. The N-type first semiconductor region11serves as a cathode. The N+-type seventh semiconductor region17serves as a region for ohmic connection of the N-type first semiconductor region11to a contact electrode CK to be described later.

When a voltage for electron amplification is applied between the first semiconductor region11(that is, the cathode) and the anode electrode21, electrons generated in the light absorbing region by photoelectric conversion are accelerated toward the P-type second semiconductor region12, and are subjected to avalanche amplification at the PN junction. The voltage for electron amplification is, for example, a voltage higher than a breakdown voltage of the PN junction between the N-type first semiconductor region11and the P-type second semiconductor region12. Therefore, the electrons generated in the light absorbing region of the SPAD increase by many times at the PN junction. Therefore, the sensor substrate1may detect, for example, one photon for each pixel50.

Furthermore, the sensor substrate1includes the contact electrodes CA, CK, and CGND provided on the front surface10aside of the semiconductor substrate10, a plurality of wiring layers ML11and ML12, and an interlayer insulating film19covering the front surface10aof the semiconductor substrate10. One end of the contact electrode CA is in contact with the anode electrode21, and the other end thereof is in contact with the wiring layer ML11having a first potential (for example, a negative potential). One end of the contact electrode CK is in contact with the seventh semiconductor region17, and the other end thereof is in contact with the wiring layer ML11having a second potential (for example, a positive potential) higher than the first potential. One end of the contact electrode CGND is in contact with the sixth semiconductor region16, and the other end thereof is in contact with the wiring layer ML11having a reference potential (for example, a ground potential (0 V)). The contact electrodes CA, CK, and CGND include metal such as aluminum (Al) or tungsten (W), for example. The wiring layers ML11and ML12include metal such as copper (Cu), for example.

The logic substrate3includes a semiconductor substrate30, an N-channel MOS transistor TrN provided on a front surface30a(inFIG.1, an upper surface) side of the semiconductor substrate30, a P-channel MOS transistor TrP provided on the front surface30aside of the semiconductor substrate30, a plurality of wiring layers ML31, ML32, and ML33provided on the front surface30aside of the semiconductor substrate30, a contact electrode CE connecting the MOS transistors TrN and TrP to the wiring layer ML31, and an interlayer insulating film39covering the front surface30aof the semiconductor substrate30. Furthermore, although not depicted, the logic substrate3includes an insulating isolation layer provided on the semiconductor substrate30. The insulating isolation layer electrically isolates an element such as the MOS transistor TrN from another element.

The MOS transistors TrN and TrP, the wiring layers ML31, ML32, and ML33, and the like provided in the logic substrate3form a bias circuit that applies a voltage between the first semiconductor region11(cathode) of the SPAD and the anode electrode21, an arithmetic circuit that performs arithmetic processing on the basis of a signal output from the SPAD, and the like.

In the sensor substrate1, the wiring layer ML12located on a side the closest to the surface is exposed from the interlayer insulating film19. In the logic substrate3, the wiring layer ML33located on a side the closest to the surface is exposed from the interlayer insulating film39. Each of the wiring layers ML12and ML33may be referred to as a pad electrode. The wiring layers ML12and ML33are provided at positions facing each other in the Z-axis direction, and are joined to each other (for example, Cu—Cu junction). Therefore, the sensor substrate1and the logic substrate3are joined to be integrated with each other, and it is possible to transmit and receive signals and apply a bias between the sensor substrate1and the logic substrate3.

FIG.2is a graph depicting a result of simulation of a relationship between a film thickness H of the P-type amorphous silicon carbide (a-SiC) film used for the anode electrode21and reflectance of infrared light on the incident surface side of the sensor substrate1in the sensor substrate1according to the first embodiment of the present disclosure. InFIG.2, the film thickness H of the P-type a-SiC film is plotted along the abscissa, and reflectance (%) is plotted along the ordinate.FIG.3is a diagram depicting a configuration on the incident surface side of the sensor substrate1set when the simulation ofFIG.2is performed. As depicted inFIG.3, in this simulation, a stacked body obtained by stacking a P-type a-SiC film (film thickness of H nm), an Al2O3film (film thickness of 15 nm), and a SiO2film (film thickness of 50 nm) in this order on a Si substrate was made the configuration on the incident surface side of the sensor substrate1. Light is incident on the Si substrate from the SiO2film. Furthermore, a wavelength of the infrared light in this simulation was set to 905 nm.

As is understood fromFIG.2, in a case where the light to be detected by the sensor substrate1is the infrared light, the film thickness of the P-type a-SiC film used for the anode electrode21is preferably 50 nm or more and 130 nm or less, more preferably 70 nm or more and 110 nm or less, and still more preferably about 90 nm. When the film thickness of the P-type a-SiC film used for the anode electrode21is within the above-described range, the reflectance of the infrared light on the incident surface side of the sensor substrate1may be kept low.

FIG.4is a graph depicting a result of simulation of a relationship between a wavelength of the incident light and transmittance of the incident light to the Si substrate in the sensor substrate1according to the first embodiment of the present disclosure. InFIG.4, the wavelength of the incident light is plotted along the abscissa, and the transmittance (%) to the Si substrate is plotted along the ordinate.FIG.5is a diagram depicting the configuration on the incident surface side of the sensor substrate1set when the simulation ofFIG.4is performed. As depicted inFIG.5, in this simulation, a stacked body obtained by stacking a P-type a-SiC film (film thickness of 90 nm), an insulating film (film thickness of 15 nm), and a SiO2film (film thickness of 50 nm) in this order on a Si substrate was made the configuration on the incident surface side of the sensor substrate1. Light is incident on the Si substrate from the SiO2film. Furthermore, in this simulation, two types of films, which are the Al2O3film and the SiO2film, were set as depicted inFIG.4as the insulating film depicted inFIG.5. In a case where the insulating film depicted inFIG.5is the SiO2film, the stacked body depicted inFIG.5has the configuration in which the SiO2film having a thickness of 65 nm (=15 nm+50 nm) is stacked on the SiC film.

As is understood fromFIG.4, when the wavelength of the incident light is 900 nm or longer and 1100 nm or shorter, the transmittance of the incident light to the Si substrate is 96% or larger. It may be said that the a-SiC film, the insulating film, and the SiO2film covering the Si substrate have high transmittance with respect to the incident light of the above-described wavelength. Furthermore, the transmittance of the insulating film between the a-SiC film and the SiO2film is slightly higher in a case where a film type is the Al2O3film than in a case where the film type is the SiO2film. This difference in transmittance is substantially zero in a case where the wavelength of the incident light is 900 nm, and becomes slightly larger when the wavelength of the incident light becomes longer than 900 nm. The difference in transmittance is slight.

Next, an example of a method of manufacturing the imaging device100according to the first embodiment of the present disclosure is described. The imaging device100is manufactured using various types of devices such as a film forming device (including a CVD device, a thermal oxidation furnace, a sputtering device, and a resist applying device), an exposure device, an ion implantation device, an annealing device, an etching device, a chemical mechanical polishing (CMP) device, and a bonding device. Hereinafter, these devices are collectively referred to as manufacturing devices.

FIGS.6A to6Gare cross-sectional schematic diagrams depicting the method of manufacturing the imaging device100according to the first embodiment of the present disclosure step by step. InFIG.6A, the manufacturing device separately manufactures a sensor substrate1′ and the logic substrate3using a CMOS process. For example, the manufacturing device forms the N-type first semiconductor region11, the P-type second semiconductor region12, the P−-type third semiconductor region13, the P−−-type fourth semiconductor region14, the P−-type fifth semiconductor region15, the P+-type sixth semiconductor region16, the N+-type seventh semiconductor region17, and the P+-type eighth semiconductor region18in the semiconductor substrate10by sequentially performing ion implantation of the P-type impurities and N-type impurities from the front surface10aside of the semiconductor substrate10into the semiconductor substrate10and performing thermal diffusion. Next, the manufacturing device forms the contact electrodes CA, CK, and CGND, the plurality of wiring layers ML11and ML12, and the interlayer insulating film19. The interlayer insulating film19is formed in a plurality of times so as to be interposed between the wiring layers ML11and ML12. Therefore, the sensor substrate1′ is manufactured.

Furthermore, the manufacturing device forms the insulating isolation layer not depicted, the N-channel MOS transistor TrN, and the P-channel MOS transistor TrP on the semiconductor substrate30, and thereafter forms the contact electrode CE, the plurality of wiring layers ML31, ML32, and ML33, and the interlayer insulating film39. The interlayer insulating film39is formed in a plurality of layers so as to be interposed between the wiring layers ML31, ML32, and ML33. Therefore, the logic substrate3is manufactured.

Next, the manufacturing device allows a surface of the sensor substrate1′ and a surface of the logic substrate3to face each other to be joined. At this step, the wiring layer M12of the sensor substrate1′ and the wiring layer ML33of the logic substrate3are joined by Cu—Cu junction, and the interlayer insulating film19of the sensor substrate1′ and the interlayer insulating film39of the logic substrate3are put into close contact to be joined. Therefore, the sensor substrate1′ and the logic substrate3are integrated with each other. Next, the manufacturing device grinds the back surface10bside of the semiconductor substrate10to set a thickness of the semiconductor substrate10to a value set in advance.

Next, as depicted inFIG.6B, the manufacturing device forms a resist pattern RP1on the back surface10b(inFIG.6B, an upper surface) of the semiconductor substrate10. The resist pattern RP1has a shape that opens on a region between the pixels50and covers other regions. Next, the manufacturing device performs etching on the semiconductor substrate10using the resist pattern RP1as a mask. This etching is performed by, for example, reactive ion etching (RIE). Therefore, the trench H1is formed in the region between the pixels50in the semiconductor substrate10. Thereafter, the manufacturing device removes the resist pattern RP1.

Next, as depicted inFIG.6C, the manufacturing device forms the anode electrode21on the back surface10bof the semiconductor substrate10using the CVD method and the like. The anode electrode21is formed continuously from the back surface10bof the semiconductor substrate10to the inner side surface and the bottom surface of the trench H1. For example, the anode electrode21is, for example, the P-type a-SiC film, the P-type poly-SiC film, the P-type a-SiN film, or the P-type poly-SiN film, with the film thickness of 90 nm.

The P-type a-SiC film or the P-type poly-SiC film may be formed by a plasma CVD method using silane (SiH4), methane (CH4), diborane (B2H6), and hydrogen (H2) as raw material gases. The P-type a-SiN film or the P-type poly-SiN film may be formed by a plasma CVD method using silane (SiH4), ammonium (NH3), diborane (B2H6), and hydrogen (H2) as raw material gases. Diborane (B2H6) is used as a doping gas of P-type impurities when the a-SiC film or a-SiN film is formed. When a B2H6gas flow rate increases, the P-type impurity concentration in the film increases and resistivity of the film decreases. Furthermore, when a H2gas flow rate increases, a poly film (polycrystalline film) is easily formed.

For example, the P-type a-SiC film is deposited by the plasma CVD method under conditions of the gas flow rate of SiH4=10 sccm, CH4=20 sccm, H2=30 sccm, and B2H6/H2=80 sccm (2600 ppm), a pressure in a chamber of 1 Torr, substrate temperature of 240° C., and RF power of 50 W. Note that, each condition of the gas flow rate, the pressure, the temperature, and the RF Power described above is merely an example, and these values may be appropriately changed by the CVD device.

The P-type a-SiC may be formed by a low-temperature process at about 240° C. Therefore, when the anode electrode21is formed, a thermal history loaded on the already formed N-type semiconductor region, P-type semiconductor region, and wiring layer may be kept small, and thermal diffusion of impurities and melting of the wiring layer may be suppressed. Therefore, it is possible to suppress fluctuation in characteristic due to the thermal history in the P-type semiconductor region, the N-type semiconductor region, and the wiring layer.

Next, as depicted inFIG.6D, the manufacturing device forms the first insulating film23on the back surface10bside of the semiconductor substrate10using the CVD method, the PVD method or the like. The anode electrode21is covered with the first insulating film23. Next, as depicted inFIG.6E, the manufacturing device forms a metal film70′ having a light-shielding property on the back surface10bside of the semiconductor substrate10using the CVD method, a sputtering method, or the like, and fills the trench H1. The metal film70′ is tungsten (W), for example. Next, as depicted inFIG.6F, the manufacturing device forms a resist pattern RP2on the metal film70′. The resist pattern RP2has a shape that covers the region between the adjacent pixels50and exposes other regions, for example. Next, the manufacturing device performs etching on the metal film70′ using the resist pattern RP2as a mask. Therefore, as depicted inFIG.6G, the light-shielding electrode70includes the metal film70′. Thereafter, the manufacturing device removes the resist pattern RP2.

Next, the manufacturing device forms the second insulating film25on the back surface10bside of the semiconductor substrate10using the CVD method, the PVD method, and the like. A thickness of the second insulating film25is, for example, 50 nm. Next, the manufacturing device attaches the microlens80(refer toFIG.1) on the second insulating film25. Through the above-described steps, the imaging device100depicted inFIG.1is completed.

Effect of First Embodiment

As described above, the imaging device100according to the first embodiment of the present disclosure includes the N-type first semiconductor region11, the P-type second semiconductor region12in contact with one surface11bof the first semiconductor region11, the light absorbing region (the third semiconductor region13and the fourth semiconductor region14) provided on the side opposite to the first semiconductor region11across the second semiconductor region12, and the anode electrode21provided at the position facing the second semiconductor region12across the light absorbing region. The anode electrode21includes the P-type semiconductor having the refractive index of 1.8 or larger and the optical bandgap of 1.9 eV or larger.

With this arrangement, as the P-type semiconductor, for example, P-type amorphous silicon carbide (a-SiC), P-type polysilicon carbide (poly-SiC), P-type amorphous silicon nitride (a-SiN), or P-type polysilicon nitride (poly-SiN) may be used. Since these films may be formed by a chemical vapor deposition (CVD) method while being doped with P-type impurities such as boron (B) in situ, the P-type impurity concentration in the film may be made uniform or substantially uniform, and the composition and crystal structure of the film may be easily homogenized. Therefore, the imaging device100may suppress variation in electric resistance (for example, resistivity) of the anode electrode21, so that this may suppress deterioration in characteristic (for example, variation in sensitivity among a plurality of pixels) due to this variation.

Furthermore, the P-type a-SiC is a wide gap material (for example, Eg=1.9 eV or larger and 2.1 eV or shorter) and hardly absorbs infrared light. The P-type poly-SiC, P-type a-SiN, or P-type poly-SiN is also a wide gap material and hardly absorbs infrared light. Therefore, the light absorbing region may be made thick. Photoelectric conversion efficiency of the pixel50may be enhanced as the light absorbing region is thicker, so that the sensitivity of the pixel50may be improved.

Furthermore, by forming the anode electrode21by the CVD method, it is easy to form the second site212of the anode electrode21to have a narrow electrode width and to be deeper in the Z-axis direction as compared with a case where multistage ion implantation is performed at high acceleration. Since it is easy to form the anode electrode21deep in the Z-axis direction, the light absorbing region of the semiconductor substrate10may be made thick. The photoelectric conversion efficiency of the pixel50may be enhanced as the light absorbing region is thicker, so that the sensitivity of the pixel50may be further improved.

Furthermore, the P-type impurities such as boron (B) contained in the anode electrode21are doped in situ at the time of film formation. Therefore, an annealing step for activating the P-type impurities is unnecessary as compared with a case of performing the ion implantation of the P-type impurities, so that the number of manufacturing steps may be reduced and the step may be simplified.

Furthermore, the anode electrode21is formed at a back surface processing step after forming the wiring layers ML11, ML12, and ML31to ML33and bonding the semiconductor substrates10and30to each other as described above. A thermal history when forming the N-type semiconductor region and the P-type semiconductor region, a thermal history when forming the wiring layers ML11, ML12, and ML31to ML33, and a thermal history when joining the semiconductor substrates10and30are not loaded on the anode electrode21. Therefore, it is possible to suppress fluctuation in characteristic due to the thermal history as for the anode electrode21.

FIG.7is a cross-sectional view schematically depicting a configuration of a sensor substrate1A according to a variation of the first embodiment of the present disclosure. As depicted inFIG.7, the sensor substrate1A includes a color filter CF between a second insulating film25and a microlens80. The color filter CF includes, for example, a red filter CF-R, a green filter CF-G, and a blue filter CF-B. Any one of the red filter CF-R, the green filter CF-G, and the blue filter CF-B is arranged in each of a plurality of pixels50.

With such a configuration, for example, P-type a-SiC, P-type poly-SiC, P-type a-SiN, or P-type poly-SiN may be used as an anode electrode21. They may be formed by a CVD method, and a P-type impurity concentration in the film may be made uniform or substantially uniform. Therefore, an imaging device including the sensor substrate1A has an effect similar to that of the first embodiment described above. Furthermore, since the sensor substrate1A includes the color filter CF, the imaging device including the sensor substrate1A may output a color image signal.

Second Embodiment

FIG.8is a cross-sectional view schematically depicting a configuration example of a sensor substrate1B according to a second embodiment of the present disclosure. The sensor substrate1B depicted inFIG.8includes a plurality of pixels250. Each of the plurality of pixels250is, for example, an avalanche photodiode. As depicted inFIG.8, the pixel250includes an N-type first semiconductor region201, a P-type second semiconductor region202provided below the N-type first semiconductor region201, and a well layer203. The N-type first semiconductor region201and the P-type second semiconductor region202are provided in the well 203 layer.

The well layer203may be a P-type semiconductor region. Furthermore, the well layer203may be, for example, a low-concentration semiconductor region having a P-type impurity concentration of smaller than 1×1015cm−3. Therefore, the well layer203may be easily depleted, and detection efficiency referred to as photon detection efficiency (PDE) may be improved.

The N-type first semiconductor region201includes, for example, N-type silicon (Si). The P-type second semiconductor region202includes, for example, P-type silicon (Si). A portion in which the N-type first semiconductor region201and the P-type second semiconductor region202are in contact with each other is a PN junction of the avalanche photodiode. A carrier generated by light incident on the sensor substrate1B is subjected to avalanche amplification at the PN junction described above. The P-type second semiconductor region202is preferably depleted, whereby the PDE may be improved.

The N-type first semiconductor region201serves as, for example, a cathode and is connected to a circuit via a contact electrode204. An anode electrode205is provided continuously between the N-type first semiconductor region201and an isolation region208, between the well layer203and the isolation region208, and below the well layer203(a back surface side of the pixel250). The anode electrode205is connected to a bias circuit via a contact electrode206.

The anode electrode205includes, similarly to the anode electrode21described in the first embodiment, for example, P-type amorphous silicon carbide (a-SiC), P-type polysilicon carbide (poly-SiC), P-type amorphous silicon nitride (a-SiN), or P-type polysilicon nitride (poly-SiN).

The sensor substrate1B may be applied to a back-illuminated imaging device or a front-illuminated imaging device. In a case where the sensor substrate1B is applied to the back-illuminated imaging device, a lens body such as a microlens is stacked under the well layer203(on a side opposite to a side on which the N-type first semiconductor region201is formed).

Furthermore, in a case where the sensor substrate1B is applied to the back-illuminated imaging device, a lens body such as a microlens is stacked on an upper surface (a surface on which the N-type first semiconductor region201is formed) side of the well layer203via a logic substrate3B (refer toFIG.10below) or the like.

The isolation region208is a region for isolating the adjacent pixels250from each other, and includes, for example, a silicon oxide film. The isolation region208may be formed so as to penetrate from the upper surface side to a lower surface side of the well layer203as depicted inFIG.8, or may be formed so as to penetrate only a part from the upper surface side to the lower surface side of the well layer203.

FIG.9is a plan view schematically depicting a configuration example of an imaging device100B according to the second embodiment of the present disclosure.FIG.10is a cross-sectional view depicting a configuration example of the imaging device100B according to the second embodiment of the present disclosure.FIG.10depicts a cross section of the plan view depicted inFIG.9taken along line X9-X′9. As depicted inFIGS.9and10, the plurality of pixels250is arranged in an array in a pixel region A1provided on the sensor substrate1B.

The logic substrate3B is connected to the lower surface (a surface opposite to a light incident surface) of the sensor substrate1B on which the plurality of pixels250is arranged. In the logic substrate3B, a circuit that processes a signal from the pixel250and supplies power to the pixel250is formed.

A peripheral region A2is arranged outside the pixel region A1. Moreover, a pad region A3is arranged outside the peripheral region A2. As depicted inFIG.10, the pad region A3is a hole in a vertical direction extending from an upper end of the sensor substrate1B to the inside of a wiring layer311, and pad openings313, which are holes for wiring to electrode pads312, are formed so as to be aligned in a straight line.

The electrode pad312for wiring is provided at a bottom of the pad opening313. The electrode pad312is used, for example, when being connected to a wire in the wiring layer311or connected to another external device (chip or the like). Furthermore, a wiring layer close to a bonding surface between the sensor substrate1B and the logic substrate3B may also serve as the electrode pad312.

The wiring layer311formed in the sensor substrate1B and the wiring layer formed in the logic substrate3B each includes an insulating film and a plurality of wires, and the plurality of wires and the electrode pads312are formed using metal such as copper (Cu) or aluminum (Al), for example. The wires formed in the pixel region A1and the peripheral region A2are also formed using a similar material.

The peripheral region A2is provided between the pixel region A1and the pad region A3. The peripheral region A2includes a ring-shaped N-type semiconductor region321surrounding the pixel region A1in plan view and a ring-shaped P-type semiconductor region322surrounding the pixel region A1outside the N-type semiconductor region321in plan view. A side surface on an outer peripheral side of the N-type semiconductor region321is in contact with a side surface on an inner peripheral side of the P-type semiconductor region322. Furthermore, the P-type semiconductor region322is connected to the wiring layer324via the contact electrode325, and the wiring layer324is connected to ground (GND).

In the example depicted inFIG.10, in the pixel region A1, the sensor substrate1B and the logic substrate3B are electrically connected to each other in such a manner that a part of the wiring layer located the closest to a bonding surface side out of the wiring layers formed on the bonding surface side of the sensor substrate1B and of the logic substrate3B are directly joined to each other.

In the N-type semiconductor region321, for example, two trenches323are formed. The trenches323are provided to physically isolate the pixel region A1from the peripheral region A2.FIG.10depicts a case where the two trenches323are formed, but the number of trenches323formed may be one or three or larger.

In the pixel region A1, a high voltage is applied between the first semiconductor region201(cathode) and the anode electrode205in the plurality of pixels250. Furthermore, the peripheral region A2is grounded to GND. In the isolation region between the pixel region A1and the peripheral region A2, a high electric field region is generated due to application of a high voltage to the anode electrode205, and breakdown might occur. In order to avoid the breakdown, it is conceivable to expand the isolation region between the pixel region A1and the peripheral region A2, but the sensor substrate1B becomes large by expanding the isolation region.

In the second embodiment of the present disclosure, the trench323is formed in order to suppress the occurrence of breakdown in the isolation region between the pixel region A1and the peripheral region A2. The breakdown may be suppressed by the trench323without expanding the isolation region.

As described above, the sensor substrate1B according to the second embodiment of the present disclosure includes the N-type first semiconductor region201, the P-type second semiconductor region202in contact with one surface of the first semiconductor region201, the well layer203(an example of a “light absorbing region” in the present disclosure) provided on a side opposite to the first semiconductor region201across the second semiconductor region202, and the anode electrode205provided at a position facing the second semiconductor region12across the well layer203. The anode electrode205includes a P-type semiconductor (for example, P-type a-SiC, P-type poly-SiC, P-type a-SiN, or P-type poly-SiN) having a refractive index of 1.8 or larger and an optical bandgap of 1.9 eV or larger.

With this, the anode electrode205may be formed by a CVD method, and the P-type impurity concentration in the film may be made uniform or substantially uniform. Therefore, the imaging device including the sensor substrate1B has an effect similar to that of the first embodiment described above.

Note that, the configurations of the peripheral region A2and the pad region A3depicted inFIGS.10and11are also applicable to the first embodiment. For example, inFIGS.10and11, the pixel250may be replaced with the pixel50depicted inFIG.1or7.

Third Embodiment

FIG.11is a block diagram depicting a configuration example of a ranging device200according to a third embodiment of the present disclosure. As depicted inFIG.11, a ranging device200(an example of an “electronic device” of the present disclosure) includes a distance image sensor401and a light source device411(an example of a “light source” of the present disclosure). The light source device411emits light of a wavelength band set in advance (for example, infrared light).

The distance image sensor401includes an optical system402, a sensor chip403, an image processing circuit404, a monitor405, and a memory406. Then, the distance image sensor401may obtain a distance image according to a distance to a subject420by receiving light (modulated light or pulsed light) projected from the light source device411toward the subject420and reflected on a surface of the subject420.

The optical system402including one or a plurality of lenses guides image light from the subject420(incident light) to a sensor chip403to form an image on a light-receiving surface (sensor unit) of the sensor chip403.

The sensor chip403photoelectrically converts infrared light and outputs a signal. For example, a light reception signal (APD OUT) is output from the sensor chip403. A distance signal indicating a distance acquired from the output light reception signal is supplied to the image processing circuit404. Note that, the imaging device100of the first embodiment or the imaging device100B of the second embodiment described above is applied as the sensor chip403.

The image processing circuit404performs image processing of constructing the distance image on the basis of the distance signal supplied from the sensor chip403, and the distance image (image data) obtained by the image processing is supplied to and displayed on the monitor405, or supplied to and stored (recorded) in the memory406.

In the distance image sensor401configured in this manner, an imaging characteristic may be improved by applying the above-described imaging devices100and100B, and for example, a more accurate distance image may be obtained.

Other Embodiment

As described above, the present disclosure is described according to the embodiments and variations thereof, but it should not be understood that the description and drawings forming a part of this disclosure limit the present disclosure. Various alternative embodiments, examples, and operation techniques will be apparent to those skilled in the art from this disclosure. For example, in the embodiment of the present disclosure, light to be detected is not limited to infrared light. The light to be detected may be, for example, visible light having a wavelength band of 400 nm or longer and 650 nm or shorter. As described above, it is a matter of course that the present technology includes various embodiments and the like not described herein. At least one of various omissions, substitutions, and changes of the components may be made without departing from the gist of the above-described embodiments and variations. Furthermore, the effect described in this specification is illustrative only; the effect is not limited thereto and there may also be another effect.

Application Example to Endoscopic Surgery System

The technology according to an embodiment of the present disclosure (present technology) is applicable to various products. For example, the technology according to an embodiment of the present disclosure may be applied to an endoscopic surgery system.

FIG.13is a block diagram depicting an example of a functional configuration of the camera head11102and the CCU11201depicted inFIG.12.

An example of the endoscopic surgery system to which the technology according to an embodiment of the present disclosure can be applied is described above. The technology according to an embodiment of the present disclosure can be applied to the endoscope11100, (the image pickup unit11402of) the camera head11102, (the image processing unit11412of) the CCU11201, and the like, for example, out of the configurations described above. Specifically, the imaging device100depicted inFIG.1, the imaging device100B depicted inFIG.9, or the sensor substrate1depicted inFIG.1, the sensor substrate1A depicted inFIG.7, and the sensor substrate1B depicted inFIG.8can be applied to the image pickup unit10402. By applying the technology according to an embodiment of the present disclosure to the endoscope11100, the image pickup unit11402of the camera head11102, the image processing unit11412of the CCU11201, and the like, for example, variation in sensitivity between a plurality of pixels is reduced, and a clearer surgical region image can be obtained, so that the operator can reliably confirm the surgical region.

Note that, the endoscopic surgery system is herein described as an example, but in addition to this, the technology according to an embodiment of the present disclosure may also be applied to a microscopic surgery system and the like, for example.

Application Example to Mobile Body

The technology according to an embodiment of the present disclosure (present technology) is applicable to various products. For example, the technology according to an embodiment of the present disclosure may also be implemented as a device mounted on any type of mobile body such as an automobile, an electric automobile, a hybrid electric automobile, a motorcycle, a bicycle, a personal mobility, an airplane, a drone, a ship, and a robot.

FIG.15is a diagram depicting an example of the installation position of the imaging section12031.

An example of the vehicle control system to which the technology according to an embodiment of the present disclosure can be applied is described above. The technology according to an embodiment of the present disclosure can be applied to the imaging section12031and the like out of the configurations described above. Specifically, the imaging device100depicted inFIG.1, the imaging device100B depicted inFIG.9, or the sensor substrate1depicted inFIG.1, the sensor substrate1A depicted inFIG.7, and the sensor substrate1B depicted inFIG.8can be applied to the imaging section12031. By applying the technology according to an embodiment of the present disclosure, for example, variation in sensitivity between a plurality of pixels is reduced, and a more easily viewable taken image may be obtained, so that driver's fatigue may be reduced.

Note that, the present disclosure may also have the following configuration.

An imaging device provided with:an N-type first semiconductor region;a P-type second semiconductor region in contact with one surface of the first semiconductor region;a light absorbing region provided on a side opposite to the first semiconductor region across the second semiconductor region; andan anode electrode provided at a position facing the second semiconductor region across the light absorbing region, in whichthe anode electrode includes a P-type semiconductor having a refractive index of 1.8 or larger and an optical bandgap of 1.9 eV or larger.

The imaging device according to (1) described above, in whichthe anode electrode includes:a first site facing the second semiconductor region in a thickness direction of the light absorbing region; anda second site facing the second semiconductor region in a direction intersecting the thickness direction of the light absorbing region.

The imaging device according to (1) or (2) described above, in which the anode electrode includes P-type amorphous silicon carbide, P-type polysilicon carbide, P-type amorphous silicon nitride, or P-type polysilicon nitride.

The imaging device according to any one of (1) to (3) described above, in which a boron concentration in the anode electrode is 1×1018cm−3or larger.

The imaging device according to any one of (1) to (4) described above, further provided with: an insulating film provided on a side opposite to the light absorbing region across the anode electrode, the insulating film having a refractive index lower than the refractive index of the anode electrode.

The imaging device according to (5) described above, in which the insulating film is an aluminum oxide film, a silicon oxide film, or a hafnium oxide film.

The imaging device according to (5) or (6) described above, further provided with: a lens body provided on a side opposite to the light absorbing region across the insulating film in a thickness direction of the light absorbing region.

The imaging device according to any one of (1) to (7) described above, in which a voltage for electron amplification is applied between the anode electrode and the first semiconductor region.

The imaging device according to any one of (1) to (8) described above, provided with:a semiconductor substrate;a plurality of pixels provided on the semiconductor substrate; anda light-shielding pixel isolation unit that is provided on the semiconductor substrate and isolates adjacent pixels among the plurality of pixels from each other, in whichthe first semiconductor region, the second semiconductor region, the light absorbing region, and the anode electrode are arranged in each of the plurality of pixels.

An electronic device provided with:a light source that emits light of a wavelength band set in advance; andan imaging device that photoelectrically converts the light and outputs a signal, in whichthe imaging device is provided with:an N-type first semiconductor region;a P-type second semiconductor region in contact with one surface of the first semiconductor region;a light absorbing region provided on a side opposite to the first semiconductor region across the second semiconductor region; andan anode electrode provided at a position facing the second semiconductor region across the light absorbing region, andthe anode electrode includes a P-type semiconductor having a refractive index of 1.8 or larger and an optical bandgap of 1.9 eV or larger.

REFERENCE SIGNS LIST