Gain adjustment for programmable gain amplifiers

A programmable gain amplifier (PGA) circuit includes a gain adjust circuit and a gain select circuit that are both coupled to an output of an amplifier. The gain select circuit completes feedback to the amplifier while the gain adjust circuit is arranged to boost or cut the gain of the gain selection circuit. The gain adjust circuit can be arranged as a trim adjustment to the overall gain of the PGA circuit, where a different trim adjustment can be mapped to each gain setting such as from a look-up table. In other example implementations, the PGA circuit can periodically switch between multiple gain settings using a modulation scheme such that the overall gain is blended between the various gain settings according to a duty cycle, pulse-width, or delta-sigma modulation, with a time averaging effect on the overall gain of the PGA circuit.

FIELD OF THE INVENTION

The present disclosure generally relates to electronic circuits. More particularly, the present disclosure relates to a technique for adjusting the gain associated with a programmable gain amplifier.

BACKGROUND

Many electronic systems employ programmable gain amplifiers as a basic analog building block. An example of a conventional programmable gain amplifier (800) is illustrated inFIG. 8. Programmable gain amplifier800includes an operational amplifier (AMP), three resistors (R81-R83), and two switches (S81-S82). The operational amplifier includes a non-inverting input terminal (INP), an inverting input terminal (INM), and an output terminal (AOUT). Switch S81is connected between AOUT and node N81. Switch S82is connected between AOUT and node N82. Resistor R81is connected between node N81and INM. Resistor R82is connected between node N82and INM. Resistor R83is connected between INM and a circuit ground (GND).

In operation, operational amplifier AMP is configured to receive an input signal (e.g., IN) at the non-inverting input (INP), and provide an output signal (e.g. OUT) at the output terminal (AOUT) that is related to the input signal according to a gain scaling factor (X). The gain scaling factor (X) is determined by the impedance in the feedback path between the output (OUT) and the inverting input (INM).

Switches S81and S82are arranged to change the selection of the feedback components (resistors R81and R82) to adjust the gain scaling factor (X). The selected feedback component is resistor R81when switch S81is closed, while the selected feedback component is resistor R82when switch S82is closed. The relationship between the input signal (IN) and the output signal (OUT) is determined by the feedback components and the switches as follows: OUT=IN * (1+X), where X is determined by the feedback components. In one example, X=R81/R83when switch S1is closed and switch S2is open. In another example, X=R82/R83when switch S2is closed and switch S1is open.

DETAILED DESCRIPTION

Throughout the specification and claims, the following terms take at least the meanings explicitly associated herein, unless the context clearly dictates otherwise. The meanings identified below are not intended to limit the terms, but merely provide illustrative examples for use of the terms. The meaning of “a,” “an,” and “the” may include reference to both the singular and the plural. The meaning of “in” may include “in” and “on.” The term “connected” may mean a direct electrical, electromagnetic, mechanical, logical, or other connection between the items connected, without any electrical, mechanical, logical or other intermediary therebetween. The term “coupled” can mean a direct connection between items, an indirect connection through one or more intermediaries, or communication between items in a manner that may not constitute a connection. The term “circuit” can mean a single component or a plurality of components, active and/or passive, discrete or integrated, that are coupled together to provide a desired function. The term “signal” can mean at least one current, voltage, charge, data, or other such identifiable quantity.

Briefly stated, the present disclosure generally relates to an apparatus and method for trimming gain adjustments in a programmable gain amplifier (PGA). An example PGA circuit includes a gain adjust circuit and a gain select circuit that are both coupled to an output of an amplifier. The gain select circuit completes feedback to the amplifier while the gain adjust circuit is arranged to boost or cut the gain of the gain selection circuit. The gain adjust circuit can be arranged as a trim adjustment to the overall gain of the PGA circuit, where a different trim adjustment can be mapped to each gain setting such as from a look-up table. In other example implementations, the PGA circuit can periodically switch between multiple gain settings using a modulation scheme such that the overall gain is blended between the various gain settings according to a duty cycle or other modulation technique such as pulse-width, delta-sigma, etc. In still a further implementation, the modulation scheme can be arranged to utilize a time averaging effect on the overall gain of the PGA circuit.

Overview

Monolithic amplifiers are often used in applications that require precision signal gain. These amplifiers routinely employ resistive feedback voltage divider elements, such as thin film resistors to control the overall signal gain. Although steps are taken to get accurate feedback ratios, resistor mismatches can result in significant overall amplifier gain error. Examples of conditions that disturb resistor ratios include both processing related differences as well as operating condition related differences. Example processing differences include processing gradients and variations in: sheet resistance (sheet rho), doping concentrations, parasitic capacitances, parasitic resistances, parasitic inductances, and parasitic leakages, to name a few. Example operating condition related differences include: temperature differences between resistors (thermal gradients), and operating voltage differences between resistors (voltage coefficient effects), to name a few.

Continuous laser trim of thin film resistance has been used in the past to correct for gain errors resulting from resistor mismatches. However, a variety of manufacturing costs such as test time, test equipment, laser trimming equipment, and other manufacturing costs can make such trimming techniques cost prohibitive for many markets. The process of trimming micro-electronic circuits (ICs) can also result in disturbances in the circuits that limit the accuracy of trimming, or extend the times necessary to perform trimming (again increasing costs).

Other manufacturing stresses can occur that reduce the accuracy of trimming. Laser trimming is typically performed on a semiconductor wafer prior to dicing the wafer into pieces called die. Example semiconductor processing steps include, dicing the wafer, attaching the die in a package with an epoxy, or perhaps a eutectic attachment, bonding the pads on the die to a lead-frame, forming and sealing the package, as well as others. Each of these semiconductor processing steps can produce die stresses (e.g., surface tension, sheering, bending, micro-cracking, etc.) that can change the overall values of the feedback elements and therefore directly affect post wafer trim gain accuracy.

The present disclosure contemplates each of the above described problems, as well as others, and provides a means for trimming and/or adjusting the gain in a programmable amplifier circuit with a digital means. The digital means can include a means for adjusting a gain trim for a selected gain setting when the gain setting is selected for the programmable gain amplifier. The gain trim can be used to boost or cut the gain according to a predetermined amount such that the desired overall gain is achieved. The digital means can be comprised of circuits that are adapted to adjust the overall gain of the programmable gain amplifier in response to one or more digital control signals. Each digital control signal can be provided by any number of input means such as, for example, from a pin or pad associated with the wafer, from a decoder logic circuit that receives a digital signal (or signals) and generates another digital signal (or signals), and from an analog-to-digital converter that receives an analog input signal and generates one or more digital control signals. The application of digital gain adjustment and trimming increases the number of opportunities for accurate signal amplification, including in-circuit calibration methods.

Trimmed Gain Amplifier

FIG. 1Ais a schematic diagram illustrating an example programmable gain amplifier circuit (100) that is arranged according to at least one aspect of the present disclosure. Programmable gain amplifier circuit100includes a gain adjust circuit (X1), a gain select circuit (X2), an operational amplifier (AMP, X3), a resistor (RSPAN, X4), a control circuit (X5), and an optional look-up table (X6). In some implementations resistor X4can be replaced with a wire, effectively a resistance of 0 ohms.

The operational amplifier (X3) includes a non-inverting input terminal (INP), an inverting input terminal (INM), and an output terminal (AOUT). The gain adjust circuit (X1) is coupled between AOUT and a reference terminal (REF). The gain select circuit is also coupled between AOUT and the reference terminal (REF). The resistor (X4) is coupled between a first tap-point terminal in the gain adjust circuit (X1) and a second tap point terminal in the gain select circuit (X2). The control circuit is arranged to receive input signals (e.g., GAIN ADJ, CALIBRATE, etc.) and provide a first control signal (GAIN TRIM SETTING) to the gain adjust circuit (X1) and a second control signal (GAIN SELECT) to the gain select circuit (X2). Optionally, the control circuit (X5) is arranged to interact with the look-up table (X6) to store and/or retrieve previously determined values associated with the first and second control signals.

The reference terminal (REF) is configured to couple a reference voltage (e.g., VREF) to the programmable gain amplifier circuit (100). The reference voltage can be any appropriate ground reference voltage (GND) such as, for example, 0V, a high power supply voltage (e.g., VDD), a low power supply voltage (e.g., VSS), a mid-supply voltage (e.g., [VDD−VSS]/2), etc.

The gain adjust circuit (X1) is configured similar to a potentiometer, where the wiper position corresponds to a variable tap point that is coupled to one side of resistor X4. The total resistance associated with the gain adjust circuit (X1) is the sum of two resistance values corresponding to RBOOST and RCUT. The specific resistance values associated with RBOOST and RCUT are variable in response to the first control signal (GAIN TRIM SETTING) such that a desired tap-point can be achieved analogous to adjusting the wiper position on a potentiometer. The gain adjust circuit (X1) is arranged to respond to the first control signal (GAIN TRIM SETTING), which can be implemented as one or more digital control signals.

The gain select circuit (X2) is also configured similar to a potentiometer, where a fixed tap point in the potentiometer is coupled to the other side of resistor X4, and where a variable tap-point in the potentiometer is coupled to the inverting input terminal (INM) of the operational amplifier circuit (X3). The variable tap-point is similar to a wiper position on a potentiometer. The total resistance associated with the gain select circuit (X2) is the sum of two resistance values corresponding to RA and RF. The specific resistance values associated with RA and RF are variable in response to the second control signal (GAIN SELECT) such that a variable tap-point can be achieved analogous to adjusting the wiper position on a potentiometer. The gain select circuit (X2) is arranged to respond to the second control signal (GAIN TRIM SETTING), which can be implemented as one or more digital control signals.

An input signal (IN) is coupled to the non-inverting input terminal (INP) of the operational amplifier (X3). The output signal (OUT) for the programmable gain amplifier circuit (100) corresponds to the output of the operation amplifier (AOUT). The gain select circuit (X2) is operated similar to the feedback circuit in a non-inverting amplifier, where the inverting input terminal (INM) is operated as the feedback point (FB) between two resistors (RA and RF). The gain select circuit (X2) adjusts the values associated with the two resistors (RA and RF) in response to the second control signal (GAIN SELECT) to achieve a desired gain setting for the programmable amplifier circuit (100). The desired gain is determined by the equation: OUT=IN*(1+RF/RA).

The gain adjust circuit (X1) is arranged to cooperate with the gain select circuit (X2) to modify the overall gain of the programmable gain amplifier circuit (100) from the selected gain setting (i.e., Gain=1+RF/RA) by boosting or cutting the gain by a desired amount. The resistance values associated with the gain select circuit (X2) are approximately in parallel with the resistance values of the gain adjust circuit (X1). The amount of boosting and cutting in the ideal gain is determined by the resistance values RBOOST and RCUT. When the wiper position is moved in the CUT direction, resistance RCUT decreases in value resistance while RBOOST simultaneously increases in value. When the wiper position is moved in the BOOST direction, RBOOST decreases in value as RCUT increases in value. RBOOST is effectively in parallel with RA such that a lower resistance value for RBOOST decreases the effective resistance value for RA. It is thus seen that a decreasing effective value for RA results in an increase in gain for the programmable gain amplifier circuit (100). Similarly, an increase in the effective value for RA results in a decrease in gain for the programmable gain amplifier circuit (100).

The control circuit (X5) is arranged to vary the control signals to the gain adjust circuit (X1) and the gain select circuit (X2) when a desired gain setting is selected by a user (e.g., via signal GAIN ADJ). When the desired gain setting is selected, the wiper position for the gain setting is selected via the first control signal (GAIN SELECT). A gain adjustment is also made via the second control signal (GAIN TRIM SETTING) so that the overall gain of the programmable gain amplifier circuit (100) is boosted or cut to achieve an accurate overall gain. Each gain setting can have a different predetermined trim amount that corresponds to a paired set of control signals for GAIN SELECT and GAIN TRIM SETTING. The trim amounts can be determined during a calibration sequence as will be discussed later with respect toFIG. 7. The control circuit (X5) can be arranged to operate in a calibration mode such as when the programmable gain amplifier circuit (100) is being tested and in a non-calibration mode when the programmable gain amplifier (100) is being operated by a user.

Adjustments associated with the trimming of the overall gain of the programmable gain amplifier circuit (100) can be stored in a look-up table (X6) such as a fuse map, a dynamic memory, a flash memory, a read only memory (ROM), or some other storage means that can be utilized to store values for later retrieval. The range associated with the trimming adjustments to the selected gain are in part dependent upon the values associated with RSPAN, RBOOST, and RCUT. In one example, the selected gain can be boosted by 10% or cut by 10%. In another example, the selected gain can be boosted by 10% or cut by 5%. Other amounts are also contemplated such that a desired range of gain adjustments are achieved. The trimming between gain settings can be further understood after review of the various circuits and methods described below.

FIG. 1Bis a schematic diagram illustrating another example programmable gain amplifier circuit (110) that is arranged according to at least one aspect of the present disclosure. Programmable gain amplifier circuit110includes a gain adjust circuit (X10), a gain select circuit (X2), an operational amplifier (AMP, X3), and a resistor (RSPAN, X4). InFIG. 1B, the gain adjust circuit (X1) fromFIG. 1Ais replaced with another gain adjust circuit (X10) that operates according to the same principals previously described. Additional control circuits and the optional look-up table are not shown, but contemplated as previously described.

The gain adjust circuit (X10) is again arranged to cooperate with the gain select circuit (X2) to modify the overall gain of the programmable gain amplifier circuit (110) from the selected gain setting (i.e., Gain=1+RF/RA) by boosting or cutting the gain by a desired amount. The resistance values associated with the gain select circuit (X2) are approximately in parallel with the resistance values of the gain adjust circuit (X10). ForFIG. 1B, the amount of boosting and cutting in the ideal gain is again determined by the effective resistance values for RBOOST and RCUT. However, the effective resistance values for RBOOST and RCUT are determined by three variable resistance circuits (X11, X12and X13).

The gain select circuit (X10) is again coupled between the output terminal (AOUT) and the reference terminal (REF), where node N1corresponds to the reference terminal (REF) and node N2corresponds to the output terminal (AOUT). Variable resistance circuits X11and X12are series coupled between nodes N1and N2as illustrated. Variable resistance circuits X11and X12include adjustable wiper positions that are coupled to nodes N4and N5, respectively. Variable resistance circuit X13is coupled between nodes N4and N5, and includes an adjustable wiper position that is coupled to node N3. Node N3corresponds to the resistor (RSPAN, X4) that couples the gain select circuit (X10) to the gain select circuit (X2).

In operation, variable resistance circuits X11-X13are arranged to provide the effective resistance values for RBOOST and RCUT such as illustrated inFIG. 1A. The resistance looking into node N3with respect to node N1corresponds to the effective resistance value for RBOOST, while the resistance looking into node N3with respect to node N2corresponds to the effective resistance value for RCUT. To reflect the relationship betweenFIGS. 1A and 1B, variable resistance circuit X11is labeled as RBOOST′ and variable resistance circuit X12is labeled as RCUT.

When the wiper position for variable resistance circuit X12is moved in the CUT′ direction, the effective resistance value for RCUT decreases, while RBOOST simultaneously increases in value. When the wiper position for variable resistance circuit X11is moved in the BOOST′ direction, the effective resistance value for RBOOST decreases as the effective resistance value for RCUT increases. The wiper position for variable resistance circuit X13can also be moved towards RCUT′ or RBOOST′ to similarly adjust the effective resistance values for RCUT and RBOOST.

The effective resistance value of RBOOST is again in a parallel configuration with respect to resistance RA, while the effective resistance value of RCUT is again in a parallel configuration with respect to resistance RF. A decreasing effective value for RA again results in an increase in gain, while an increasing effective value for RA results in a decrease in gain for the programmable gain amplifier circuit (110). A decreasing effective value for RF again results in an decreased in gain, while an increasing effective value for RF results in an increased in gain for the programmable gain amplifier circuit (110).

FIG. 1Cis a graph (120) illustrating gain error effects for example programmable gain amplifier circuits, such as that described inFIG. 1B.

Gain error inFIG. 1Cis determined as the difference between the desired gain setting and the actual gain setting that is achieved in a manufactured circuit. In some examples, the gain error can be reduced by increasing the effective gain setting from the gain adjust circuit (e.g., X1or X10), while in other examples the gain error can be reduced by decreasing the effective gain setting. Moreover, the slope of the gain error can also be changed by varying the settings for the gain adjust circuit (e.g., X10).

As illustrated inFIG. 1B, variable resistance circuit X11includes at least three example wiper positions (A1, A2and A3), while variable resistance circuit X12is includes at least another three wiper positions (B1, B2and B3). The effective resistance between nodes N1and N4are lowest at wiper position A3, higher at wiper position A2, and highest at wiper position A1. The effective resistance between nodes N5and N2are lowest at wiper position B1, higher at wiper position B2, and highest at wiper position B3.

ForFIG. 1C, the gain adjustment settings of gain adjust circuit X10ofFIG. 1Bhas wiper settings corresponding to position pairs A3, B3; A2, B1; and A1, B2. The gain error for wiper position pair A3, B3has a slope corresponding to m1. For this example, a decrease in overall gain error occurs when wiper position pair A1, B2is selected, where the overall slope remains approximately at m1. Changing from wiper position pair A1, B2to wiper position pair A2, B1results in a decrease in the overall slope from m1to m2, as illustrated. As illustrated byFIGS. 1B and 1C, moving the wiper position settings closer to the common node between variable resistance circuits X11and X12results in a decrease in overall gain adjustment range as is reflected by the gain error slope decreasing. Similarly, moving the wiper positions further apart from the common node results in an increase in overall gain adjustment range as is reflected by the gain error slope increasing. Moving the wiper positions together towards node N1tends to move the overall gain adjustment towards boost while maintaining a similar slope.

Digitally Adjusted Resistor Circuits

FIG. 2is a schematic diagram illustrating an example adjustable resistor topology (200) in another example programmable gain amplifier circuit that is arranged according to at least one aspect of the present disclosure. Adjustable resistor topology200includes an array of N-series coupled resistors (RS1-RSN) and a multiplexer circuit (MUX, X21). An example latch circuit (X22), look-up table (X23) and control circuit (X24) are also illustrated inFIG. 2.

Resistors RS1-RSN are series coupled between REF and OUT. Resistor RS1is coupled between REF and node P1. Resistor RS2is coupled between node P1and node P2. Resistor RSN-1is coupled between node PN-2and node PN-1. Resistor RSN is coupled between node PN-1and PN, where PN is coupled to OUT. Nodes P1through PN are coupled to multiplexer circuit X21. The multiplexer circuit (X21) is responsive to a control signal (e.g., GAIN TRIM SETTING) to couple one of nodes P1through PN to resistor RSPAN. The multiplexer circuit (X21) is arranged to cooperate with the array of resistors (RS1-RSN) to provide the necessary functions for a digitally controlled potentiometer.

The multiplexer circuit (X21) is illustrated as an array of controlled switches (S1-SN), where each switch is arranged to couple a respective one of nodes P1through PN to resistor RSPAN. The array of switches is intended to provide an example of the function provided by the multiplexer. Such functions may be provided by transistors, transmission gates, logic circuits, and other circuits that are arranged to provide a multiplexer functionality without departing from the spirit of the present disclosure.

Any number of resistors and switches can be utilized to achieve a desired number of tap points and a desired range of adjustability. The values associated with the resistors can be selected to achieve a desired granularity. In one example, equal valued resistors are selected. In another example, each resistor is related to a preceding resistor according to a binary scaling (e.g., 1×, 2×, 4×, etc.). In still another example, each resistor is related to a preceding resistor according to a linear scaling factor. In yet another example, each resistor is related to a preceding resistor according to a logarithmic scaling factor. Other arbitrarily assigned values can also be selected as may be desired.

In one example, the multiplexer circuit is controlled by a GAIN TRIM SETTING control signal that is provided by latch X22. Latch22can be set or cleared via control signals from the control circuits (X24). When the set signal is asserted, latch22stores a value (LUT Setting) that is provided by look-up table X23, which is also controlled by the control circuit (X24) such as via signals READ, WRITE, ADDR, DATA and EN.

An example look-up table (X24) can be implemented as a programmable read only memory, or some other programmable storage means. Each address (ADDR) can be associated with a particular gain setting for the programmable gain amplifier circuit. When an ADDR is used to access the look-up table (e.g., asserting the READ and EN signals when ADDR is ready), a look-up table setting value is retrieved for the associated gain setting. In some implementations, values can be stored in the look-up table (X23) using DATA to store the value associated with ADDR when the WRITE signal and EN signal are asserted. The described example is intended as a non-limiting example of a look-up table, and many other examples are contemplated such as read-only memory (ROM), random access memory (RAM), flash memory, programmable logic array (PLA), to name a few.

An example control circuit (X24) can be adapted to receive input signals (e.g., IN1, IN2, etc.) from one or more pads associated with an integrated circuit. The pads may be accessed using wafer probing techniques, using pins associated with the packaged integrated circuit, or via some other mechanism. Signals (e.g., D1, D2, etc.) received by control circuit X24are processed to provide the necessary control signals for testing gain/trim settings, storing calibration data, and for operating the programmable gain amplifier circuit. A mode control functional block can be utilized to identify and select an operating mode for the programmable gain amplifier circuit. Example modes include a test mode where the user can manually select gain and trim values, a store mode where the user can store settings associated with a trim value for a gain setting, and an operational mode where the user can program the gain of the programmable gain amplifier circuit using previously stored calibration trim values. An address register can be used to provide values for accessing the look-up table (X3). A data register can be used to provide values for storing in the look-up table (X3). When the testing mode is enabled, the control circuit can be used to select each trim setting for a respective gain setting in the programmable gain amplifier circuit.

FIG. 3Ais a schematic diagram illustrating another example adjustable resistor topology (300) in still another example programmable gain amplifier circuit that is arranged according to at least one aspect of the present disclosure. Adjustable resistor topology300includes an array of N-parallel configured resistors (RP1-RPN) and a multiplexer/selector circuit. An example register circuit (X31) is illustrated for a latching means that stores the gain trim setting control signal inFIG. 2.

Resistors RP1-RPN are arranged in a parallel configuration, where each resistor includes a first terminal that is coupled in common to resistor RSPAN. The multiplexer/selector circuit is coupled to a second terminal for each resistor at nodes P1-PN. The multiplexer/selector circuit is arranged to selectively couple each resistor to one of two nodes, one node corresponding to REF and the other node corresponding to OUT.

The multiplexer/selector circuit is illustrated as switching circuits S1-SN, where each switching circuit is associated with a respective one of resistors RP1-RPN. Each switching circuit is illustrated as a two-position switch, however the circuits are intended as a functional illustration that can be implemented as transistors, transmission gates, digital logic, and any other circuits configured to provide the desired functionality. The switching circuits are responsive to the control signal (e.g., GAIN TRIM SETTING) to independently couple each node (P1through PN) to either REF or OUT. The multiplexer/selector circuit is arranged to cooperate with the array of resistors (RS1-RSN) to provide the necessary functions for a digitally controlled potentiometer.

Any number of resistors and switches can be utilized to achieve a desired number of adjustments with a desired range. The values associated with the resistors can be selected to achieve a desired granularity. In one example, equal valued resistors are selected. In another example, each resistor is related to a preceding resistor according to a binary scaling (e.g., 1×, 2×, 4×, etc.). In still another example, each resistor is related to a preceding resistor according to a linear scaling factor. In yet another example, each resistor is related to a preceding resistor according to a logarithmic scaling factor. Other arbitrarily assigned values can also be selected as may be desired.

FIG. 3Bis a schematic diagram illustrating still another example adjustable resistor topology (310) in another example programmable gain amplifier circuit that is arranged according to at least one aspect of the present disclosure. Adjustable resistor topology310is an R-2R resistor ladder circuit, including four selectable nodes (P1-P4) that are selected by a multiplexer/selector circuit. An example register circuit (X31) is again illustrated for a latching means that stores the gain trim setting control signal.

Similar toFIG. 3A, the multiplexer/selector circuit is arranged to selectively couple each selectable node (P1-P4) from the resistor ladder circuit to one of two nodes, one node (N1) corresponding to REF and the other node (N2) corresponding to OUT. The multiplexer/selector circuit is illustrated as switching circuits S1-SN, where each switching circuit is associated with a respective one of resistors in the resistor ladder circuit. The switching circuits are responsive to the control signal (e.g., GAIN TRIM SETTING) to independently couple each node (P1through PN) to either REF or OUT.

The R-2R resistor ladder circuit includes a node (N3) that is coupled in common to resistor RSPAN. A resistor of value 2R is coupled between each pair of the following node pairs: N3, P4; N33, P3; N32, P2; N31, P1; N30, N1; and N30, N2. A resistor of value R is coupled between each pair of the following node pairs: N3, N33; N33, N32; N32, N31; and N31, N30. Although illustrated as a four bit R-2R ladder, any other number of bits of resolution can be utilized as will be understood to one of skill in the art.

The R-2R ladder circuit is arranged to selectively switch points P1-P4between nodes N1and N2in response to the gain trim setting signal. The effective resistance looking into node N30corresponds to the parallel combination of 2R and 2R, notated as 2R∥2R, which is equivalent to a value of R. The effective resistance looking into node N31corresponds to the combination of value R in series with the resistance looking into node N30, notated as R+RN30, which is equivalent to a value of 2R. This process continues up to the resistance looking into node N3, which is again equivalent to a value of 2R.

Each of the figures described can be combined to provide a desired functionality. Additional examples are also contemplated to provide any number of possibilities, including additional mode control circuits, serial control signals, parallel control signals, internally accessed trim tables, externally accessed trim tables, to name a few.

FIG. 4is a schematic diagram illustrating yet another example adjustable resistor topology (400) in yet another example programmable gain amplifier circuit that is arranged according to at least one aspect of the present disclosure. Resistor topology400includes a fine gain adjustment circuit (X41), a coarse gain adjustment circuit (X42), a gain select circuit (X43), three resistors (X44-X46), and an operational amplifier circuit (X47). In some implementations resistors X44and/or X45can be replaced by wire, effectively having a resistance of 0 ohms. In some other implementations resistor X46is combined with the gain select circuit (X43) such as illustrated inFIG. 1AorFIG. 1B.

The operational amplifier (X47) includes a non-inverting input terminal (INP), an inverting input terminal (INM), and an output terminal (AOUT). The coarse gain adjust circuit (X42) and the fine gain adjust circuit (X41) are coupled between AOUT and a reference terminal (REF). The gain select circuit is also coupled between AOUT (via resistor X46) and the reference terminal (REF). Resistor X44is coupled between a first fine adjust tap-point terminal in the fine gain adjust circuit (X41) and the tap point between the gain select circuit (X42) and resistor X46. Resistor X45is coupled between a coarse adjust tap-point terminal in the coarse gain adjust circuit (X42) and the tap point between the gain select circuit (X42) and resistor X46.

The reference terminal (REF) is configured to couple a reference voltage (e.g., VREF) to the programmable gain amplifier circuit (100). The reference voltage can be any appropriate ground reference voltage (GND) such as, for example, 0V, a high power supply voltage (e.g., VDD), a low power supply voltage (e.g., VSS), a mid-supply voltage (e.g., [VDD−VSS]/2), etc.

The example illustrated inFIG. 4is substantially similar to the examples ofFIGS. 1A and 1B, with the modification of the gain adjustment circuit to include coarse and fine adjustment means. The gain select circuit (X43) is again configured similar to a potentiometer, where a variable tap-point in the potentiometer is coupled to the inverting input terminal (INM) of the operational amplifier circuit (X47) to provide a feedback signal (FB). An input signal (IN) is again coupled to the non-inverting input terminal (INP) of the operational amplifier (X47).

The fine gain adjust circuit (X41), coarse gain adjust circuit (X42), and the gain select circuit (X43) are all configured to operate as digitally controlled potentiometers similar to those previously discussed. The wiper of the fine adjust circuit (X41) is adjusted in response to a first control signal (FINE GAIN TRIM SELECT), while the wiper of the coarse gain adjust circuit (X42) and the wiper of the gain select circuit (X43) are adjusted in response to second and third control signals (COARSE GAIN TRIM SELECT, GAIN SELECT). In one example, the fine gain adjust circuit (X41) is implemented as an array of series configured resistors while the coarse gain adjust circuit (X43) is implemented as an array of parallel configured resistors. Other examples are also contemplated where all of the adjustable resistor circuits may be different topologies from one another or the same topologies as one another.

Modulated Gain Adjustment

FIG. 5Ais a schematic diagram illustrating another example programmable gain amplifier circuit (500) that employs a modulation topology according to at least one aspect of the present disclosure. Programmable gain amplifier circuit500includes a first and second gain setting network (X51, X52), a switching circuit (SW, X53), a control logic circuit (X54), an optional look-up table (X55), an optional sensor circuit (X56), an optional resistor (R), and an operational amplifier circuit (X59). The sensor circuits can be of any variety of sensors such as, but not limited to, a temperature sensor (X57), a voltage sensor (X58), etc.

The operational amplifier circuit (X59) includes a non-inverting input terminal (INP), an inverting input terminal (INM), and an output terminal (AOUT). The first gain setting network (X51) is coupled between a first terminal of the switching circuit (X53) and the output terminal (AOUT) of the operational amplifier (X59). The second gain setting network (X52) is coupled between a second terminal of the switching circuit (X53) and the output AOUT) of the operational amplifier (X59). The switching circuit (X53) also includes a third terminal that is coupled to the inverting input (INM) of the operational amplifier through optional resistor R.

In operation, the switching circuit is arranged to couple one of the first and second terminals to the third terminal of the switching circuit (X53). When the first terminal is coupled to the third terminal, the overall gain of the programmable gain amplifier circuit (500) corresponds to the gain setting that is provided by the first gain setting network (X51). When the second terminal is coupled to the third terminal, the overall gain of the programmable gain amplifier circuit (500) corresponds to the gain setting that is provided by the second gain setting network (X52). The control logic circuit (X54) is arranged to provide a gain control signal to the switching circuit such that a desired blend is achieved between the gain from the first gain setting network (X51) and the gain from the second gain setting network (X52). By modulating the pulse width (or the average pulse density such as in the case of time averaged over-sampling modulation schemes such as sigma-delta modulation) associated with the gain control signal any desired blend between the gains can be achieved. The optional look-up table can again be used to retrieve values associated with a trimmed gain. For this example, the trimmed values correspond to a duty cycle setting.

In one example, a first gain setting network (X51) is arranged to provide a gain of 1.5 and a second gain setting network (X52) is arranged to provide a gain of 2.5. When the duty cycle is set to 0%, the overall gain is simply 1.5. Similarly, when the duty cycle is set to 100%, the overall gain is simply 2.5. However, when the duty cycle is set to 50%, the overall gain of the programmable gain amplifier circuit (500) corresponds to 2.0. By varying the duty cycle between 0% and 100%, the gain can be effectively adjusted between 1.5 and 2.5. A wide range of adjustments can be made without any additional circuit modifications simply by varying the duty cycle of the modulation between the first and second gain settings.

In some examples, the control logic circuit can be arranged to evaluate operating conditions associated with the circuit such as by monitoring voltages, currents, operating temperatures, etc. provided from a sensor circuit (X56). Various changes to the modulation can be made by the control logic circuit (X54) based on the dynamically measured operating conditions. In this way, the gain of the programmable gain amplifier circuit (500) can be carefully controlled. In some instances, it may be desirable to change to the modulation technique when one of the monitored operating conditions changes beyond a predetermined threshold.

FIG. 5Bis a schematic diagram illustrating still another example programmable gain amplifier circuit (510) that employs a modulation topology according to at least one aspect of the present disclosure. Programmable gain amplifier circuit510includes a first and second gain setting circuit (X51B, X52B), and an operational amplifier circuit (X59), arranged similar toFIG. 5A. Each gain setting circuit includes a switching circuit (SW, X53), an optional resistor (RA, RB), and two gain setting networks (X51B, X52B).

The first gain setting circuit (X51B) includes gain setting networks1and2, with corresponding gain values of G1and G2, respectively. The second gain setting circuit (X52B) includes gain setting networks3and4, with corresponding gain values of G3and G4respectively. Each gain setting network is selectively coupled between nodes INM and AOUT via their respective switching circuit (X53) and optional resistor (R) in response to the gain control signal(s).

In operation, the switching circuits are arranged to selectively couple one or more of the gain setting networks in the feedback loop of the operational amplifier circuit (X59), in a substantially similar manner as that described forFIG. 5A. The pulse width associated with the gain control signal(s) can again achieve any desired blend between the available gains (G1-G4). Also, each gain setting network can be arranged to have a desired frequency dependant gain as may be desired to achieve a frequency compensated gain adjustment.

In one example, gains G1and G3are selected together to achieve a gain error adjustment of −1.0%, gains G1and G4are selected together to achieve a gain error adjustment of −0.5%, gains G2and G3are selected together to achieve a gain error adjustment of +0.5%, and gains G2and G4are selected together to achieve a gain error adjustment of +1.0%.

FIG. 5Cis a schematic diagram illustrating yet still another example programmable gain amplifier circuit (520) that employs a modulation topology according to at least one aspect of the present disclosure. Programmable gain amplifier circuit520includes a four gain setting networks (N1-N4), an operational amplifier circuit (X59), a switching circuit (SW, X53C), and an optional resistor (R).

The first gain setting network (N1) has gain value of G1, while the second third and fourth gain setting networks (N2-N3) have corresponding gain value of G2, G3and G4, respectively. Each gain setting network is selectively coupled between nodes INM and AOUT via the switching circuit (X53C) and optional resistor (R) in response to the gain control signal. Each gain setting (G1-G4) can optionally have a different frequency dependant gain characteristic.

In operation, the switching circuit (X53C) is arranged to selectively couple one of the gain setting networks (N1-N4) in the feedback loop of the operational amplifier circuit (X59), in a substantially similar manner as that described forFIG. 5A. The pulse width associated with the gain control signal can again achieve any desired blend between the available gains (G1-G4). For example, gain setting network N1is selected at time t1, gain setting network N2is selected at time t2, gain setting network N3is selected at time t3, and gain setting network N4is selected at time t4.

Desired gain settings can be achieved by varying the amount of time that each gain setting is active/inactive over a period (e.g., T) where the gain setting pattern repeats. In one example, times t1, t2, t3and t4are spaced apart in time with equal active times for each selecting gain setting so that the overall gain corresponds to the average of G1, G2, G3and G4. In other example, only gain settings G1and G3are utilized for equal times so that the overall gain is the average of G1and G3. In still another example, each gain setting is utilized for a different amount of time so that each gain setting is applied for a non-equal percentage of the total period between repeated gain settings. Over-sampled time averaged modulation schemes such as delta-sigma modulation can be used as well.

FIG. 6Ais a schematic diagram illustrating still another example programmable gain amplifier circuit (600) that employs still another modulation topology according to at least one aspect of the present disclosure. Programmable gain amplifier circuit600includes an operational amplifier circuit (X61), a digitally controlled potentiometer (X62), a switching circuit (X63), a first capacitor circuit (C1, X64), a second capacitor circuit (C2, X65), an optional resistor circuit (R, X66), and a control circuit (X67). The control circuit (X67) includes functional blocks for a modulator (X68) and a control logic (X69).

The operational amplifier circuit (X61) includes a non-inverting input terminal (INP), an inverting input terminal (INM), and an output terminal (AOUT). The digitally controlled potentiometer (X62) is coupled between the output terminal (AOUT) of the operational amplifier circuit (X61) and a reference potential (REF), and also includes a fixed tap-point and a variable tap-point. The fixed tap-point is coupled to first terminals of the capacitor circuits (X64, X65) and the optional resistor circuit (R). The second terminal of the first capacitor circuit (X64) is coupled to the reference potential (REF), while the second terminal of the second capacitor circuit (X65) is coupled to the output terminal (AOUT) of the operational amplifier circuit (X61). A first terminal of the switching circuit (X63) is coupled to the reference potential (REF). A second terminal of the switching circuit (X63) is coupled to the output (AOUT) of the operational amplifier circuit (X61). The switching circuit (X63) also includes a third terminal that is coupled to the second terminal of the optional resistor circuit (R).

In operation, the switching circuit (X63) is arranged to couple one of the first and second terminals to the third terminal of the switching circuit (X63). When the first terminal is coupled to the third terminal, the overall gain of the programmable gain amplifier circuit (600) corresponds to a first gain setting. When the second terminal is coupled to the third terminal, the overall gain of the programmable gain amplifier circuit (600) corresponds to a second gain setting. The control logic circuit (X67) is arranged to provide a gain select control signal to adjust the feedback provided by the digitally controlled potentiometer circuit (X62). The control logic circuit (X67) is further arranged to provide a gain trim control signal to adjust the pulse width associated with modulating the switching circuit (X63). The operational features provide for a time averaged gain that is smoothed by the capacitors.

FIG. 6Bis a schematic diagram illustrating another example programmable gain amplifier circuit (610) that employs a similar modulation topology to that described forFIG. 6A. Similar to programmable gain amplifier circuit600fromFIG. 6A, programmable gain amplifier circuit610includes an operational amplifier circuit (X61), a digitally controlled potentiometer (X62), a switching circuit (X63), a first capacitor circuit (C1, X64), a second capacitor circuit (C2, X65), and an optional resistor circuit (R, X66).

Programmable gain amplifier circuit610further includes an adjustable resistor circuit (X68B, RC2), and an optional resistor (X67B, RC1). Adjustable resistor circuit X68B is coupled between nodes N1and N2, which corresponds to the reference potential (REF) and the output of the operational amplifier (X61), respectively. A wiper terminal for the adjustable resistor circuit (X68B) is coupled to node N3, which corresponds to the common node between capacitors C1and C2, via optional resistor RC1(X67B).

The operation of adjustable switching circuit (X63) is the same as that previously described forFIG. 6A. However, the adjustable resistor circuit (X68B) is arranged to operate as a coarse gain adjustment circuit that changes the overall gain of the digitally controlled potentiometer (X62) similar to that previously described, for example, byFIGS. 1A and 1B. The operational features again provide for a time averaged gain that is smoothed by the capacitors (C1and C2).

FIG. 6Cis a schematic diagram illustrating another example programmable gain amplifier circuit (620) that employs a similar modulation topology to that described forFIGS. 6A and 6B. Similar to programmable gain amplifier circuit600, programmable gain amplifier circuit620includes an operational amplifier circuit (X61), a digitally controlled potentiometer (X62), a switching circuit (X63), a first capacitor circuit (C1, X64), a second capacitor circuit (C2, X65), an optional resistor circuit (R1, X66), and a control circuit (X67).

Programmable gain amplifier circuit610further includes a second switching circuit (X68C), and a resistor (X67C, R2). Switching circuit X68includes contact terminals that are coupled to nodes N1, N2and node N3via resistor R2. Node N1corresponds to the reference potential (REF), while node N2corresponds to the output of the operational amplifier (X61). Node N3corresponds to the common node between capacitors C1and C2.

The operation of adjustable switching circuit (X63) is the same as that previously described forFIGS. 6A and 6B. However, switching circuit (X68C) is arranged to operate with resistor R2as a coarse gain adjustment circuit that changes the overall gain of the digitally controlled potentiometer (X62) similar to that previously described, for example, byFIGS. 1A and 1B. The operational features again provide for a time averaged gain that is smoothed by the capacitors (C1and C2). Resistors R1and R2can be of different values so that the amount of adjustment provided by switching operations are different for the two switching circuits (X63and X68C)

As will be appreciated by those of skill in the art having read the present disclosure, the modulation of the switching circuits (X53, X53C, X63, and X68C) fromFIGS. 5A,5B,5C,6A,6B and6C can be provided in a manner that is similar to delta-sigma modulation techniques or other time averaged modulation schemes to provide a wide range of gain trimming features for the programmable gain amplifier circuit (600).

The programmable gain amplifier circuits (600,610and620) ofFIGS. 6A,6B and6C may also include the optional sensor circuit (X56) fromFIG. 5A, where the sensor circuit can again include any variety of sensors such as, but not limited to, a temperature sensor (X57), a voltage sensor (X58), etc. For such as example implementation, the control logic circuit can be arranged to evaluate various operating conditions associated with the circuit (e.g., monitoring voltages, currents, operating temperatures, etc.) and effecting various changes to the modulation based on the dynamically measured operating conditions. In this way, the gain of the programmable gain amplifier circuits (600,610and620) can be carefully controlled. In some instances, it may be desirable to change the modulation technique when one of the monitored operating conditions changes beyond a predetermined threshold.

Gain Selection/Trimming Flow

FIG. 7is a flow chart (700) for identifying and/or setting gain adjustments in a programmable gain amplifier circuit that is arranged according to at least one aspect of the present disclosure. The programmable gain amplifier circuit corresponds to a circuit such as those described inFIGS. 1-6above, as well as others that are similarly arranged.

The described system/circuit is arranged to evaluate the current operating mode at decision block705. When the current operating mode corresponds to a test mode, the process flows from block705to block710where the system cycles to the next available gain settings (e.g., gain setting1, gain setting2, etc.) to test the accuracy of each gain setting. After the next gain setting is selected, the system process flows to block715where the next available trim setting (e.g., gain trim setting1, gain trim setting2, etc.) is selected. Processing continues to block720where the gain error associated with the current gain/trim settings is evaluated. At decision block725the system determines if more trim settings are to be evaluated. When additional trim settings are to be evaluated, processing continues back to block715. Otherwise processing flows to block730where the trim setting with a minimal gain error is identified for the gain setting. At block735the identified trim setting is stored or logged. At decision block740the system determines if additional gain settings are to be tested. When additional gain settings are to be tested, processing continues to block710. Otherwise processing of the test mode is concluded at block795.

The identified “best” available trim settings can be stored as values in a trim map or look-up table (LUT) such as those previously described. The trim map can be implemented on the same die as the programmable gain amplifier circuit (e.g., a fuse link table, a non-volatile memory array, or some other mapping mechanism), on a separate die in a multi-chip module, or in a separate micro-electronic circuit that is arranged to communicate the look-up table information to the programmable gain amplifier circuit.

When the test mode is inactive, processing flows from decision block705to decision block745where the selected mode is evaluated to determine if a gain adjustment (or normal operating) mode is active. When the gain adjustment mode is active, processing continues from decision block745to block745where the trim map is accessed. Continuing to block760a trim setting is selected based on the trim map. Proceeding to block765the gain and trim settings are used to generate the appropriate control signals and/or latched into a latch means such as a register. Processing concludes at block795.

When the test mode is inactive and the adjust gain mode is inactive, processing flows from decision block745to block750where additional modes can be processed. In one example, the circuits are operated in a “program gain/trim mode”, where the trim map is loaded from a separate set of values that can be provided by an externally provided table (e.g., ROM, EPROM, EEPROM, LUT, NVM, etc.). In another example, the circuits are operated in a “run mode”, where the gain and trim settings cannot be changed. In still another example the circuits are operated in a “program gain mode”, where the trim map and gain settings are selected to adjust the trim setting and amplifier gain similar to that described forFIG. 7. Other modes are also contemplated and considered within the scope of the present disclosure. For implementations where only test mode and adjust gain/normal operating mode are available, decision block745and processing block750can be eliminated.

Although the invention has been described herein by way of various example embodiments, variations in the structures, features, and methodological steps described herein may be made without departing from the spirit and scope of the invention. For example, the positioning of the various components may be varied. Individual components and arrangements of components may be substituted as known to the art. Since many embodiments of the invention can be made without departing from the spirit and scope of the invention, the invention resides in the claims hereinafter appended.