Circuit board layout

A circuit board having a method therefor comprises a first circuit board layer comprising a first surface having disposed thereon a first plurality of lands arranged in three rows and comprising at least one group of the lands, wherein each group of the lands comprises first and second ones of the lands arranged in a first one of the rows, third, fourth, and fifth ones of the lands arranged in a second one of the rows, and sixth and seventh ones of the lands arranged in a third one of the rows, wherein the second one of the rows is adjacent to, and lies between, the first one of the rows and the third one of the rows; and respective traces extending from the first, second, third, fourth, fifth, and sixth ones of the lands between the sixth and seventh ones of the lands.

BACKGROUND

The present invention relates generally to circuit boards. More particularly, the present invention relates to circuit board layout.

Modern integrated circuits have attained a complexity that requires a large number of terminals for connection to other devices. To reduce the package size of such integrated circuits, the terminals are generally arranged in multiple rows on the underside of the package, for example in what is referred to as a “ball grid array” (BGA). These terminals, referred to as “balls,” are then connected to contacts called “lands” on the surface of the circuit boards. Connections called “traces” connect the lands to other devices or terminals on the circuit board.

To reduce package footprint, the balls on the integrated circuit package are generally placed as close together as possible, as are the lands on the circuit board.

FIG. 1shows a top circuit board layer100for a prior art circuit board comprising three rows108A-C of lands102. As can be seen inFIG. 1, lands102are generally so close together that only one trace104can pass between adjacent lands102. In fact, as can be seen in the arrangement ofFIG. 1, there is no room for traces104to be connected to the lands102in the third row108C. Instead, a second circuit board layer is required. The lands102in the third (and higher) rows must be connected to vias, which penetrate circuit board layer100to connect to traces on other circuit board layers.

A similar limitation occurs for internal layers of prior art circuit boards.FIG. 2shows an internal circuit board layer200of a prior art circuit board comprising three rows208A-C of vias206. As can be seen inFIG. 2, vias206are also generally so close together that only one trace104can pass between adjacent vias206. In fact, as can be seen in the arrangement ofFIG. 2, there is no room for traces104to be connected to the vias206in the third row208C. Instead, a further circuit board layer is required. The vias206in the third (and higher) rows penetrate circuit board layer200to connect to traces on other internal circuit board layers.

As can be seen inFIGS. 1 and 2, a device having many rows of balls requires several circuit board layers. In addition, power and ground plane layers are required for each circuit board layer. These many layers increase the complexity and cost of the circuit boards.

SUMMARY

In general, in one aspect, the invention features a circuit board comprising: a first circuit board layer comprising a first surface having disposed thereon a first plurality of lands arranged in three rows and comprising at least one group of the lands, wherein each group of the lands comprises first and second ones of the lands arranged in a first one of the rows, third, fourth, and fifth ones of the lands arranged in a second one of the rows, and sixth and seventh ones of the lands arranged in a third one of the rows, wherein the second one of the rows is adjacent to, and lies between, the first one of the rows and the third one of the rows; and respective traces extending from the first, second, third, fourth, fifth, and sixth ones of the lands between the sixth and seventh ones of the lands.

In some embodiments, each of the groups of the lands further comprises: a first column of the lands comprising the third and sixth ones of the lands; a second column of the lands comprising the first and fourth ones of the lands; and a third column of the lands comprising the second, fifth and seventh ones of the lands; wherein the second column of the lands is adjacent to, and lies between, the first and third columns of the lands. Some embodiments comprise a second circuit board layer comprising a second surface having disposed thereon a plurality of vias arranged in three rows and comprising at least one group of the vias, wherein each group of the vias comprises first and second ones of the vias arranged in a first one of the rows, third, fourth, and fifth ones of the vias arranged in a second one of the rows, and sixth and seventh ones of the vias arranged in a third one of the rows, wherein the second one of the rows is adjacent to, and lies between, the first one of the rows and the third one of the rows; and respective traces extending from the first, second, third, fourth, fifth, and sixth ones of the vias between the sixth and seventh ones of the vias. In some embodiments, each of the groups of the vias further comprises: a first column of the vias comprising the third and sixth ones of the vias; a second column of the vias comprising the first and fourth ones of the vias; and a third column of the vias comprising the second, fifth and seventh ones of the vias; wherein the second column of the vias is adjacent to, and lies between, the first and third columns of the vias. In some embodiments, the lands disposed upon the first surface of the first circuit board layer further comprise: a second plurality of lands arranged in three rows; wherein each of the vias is electrically coupled to one of the second plurality of lands.

In general, in one aspect, the invention features a circuit board comprising: first circuit board layer means for supporting comprising a first surface having disposed thereon first plurality of first means for electrically contacting arranged in three rows and comprising at least one group of the first means for electrically contacting, wherein each group of the first means for electrically contacting comprises first and second ones of the first means for electrically contacting arranged in a first one of the rows, third, fourth, and fifth ones of the first means for electrically contacting arranged in a second one of the rows, and sixth and seventh ones of the first means for electrically contacting arranged in a third one of the rows, wherein the second one of the rows is adjacent to, and lies between, the first one of the rows and the third one of the rows; and respective means for electrically connecting extending from the first, second, third, fourth, fifth, and sixth ones of the first means for electrically contacting between the sixth and seventh ones of the first means for electrically contacting. In some embodiments, each of the groups of the first means for electrically contacting further comprises: a first column of the first means for electrically contacting comprising the third and sixth ones of the first means for electrically contacting; a second column of the first means for electrically contacting comprising the first and fourth ones of the first means for electrically contacting; and a third column of the first means for electrically contacting comprising the second, fifth and seventh ones of the first means for electrically contacting; wherein the second column of the first means for electrically contacting is adjacent to, and lies between, the first and third columns of the first means for electrically contacting. Some embodiments comprise second circuit board layer means for supporting comprising a second surface having disposed thereon a plurality of second means for electrically contacting arranged in three rows and comprising at least one group of the second means for electrically contacting, wherein each of the second means for electrically contacting penetrates the second circuit board layer means, and wherein each group of the second means for electrically contacting comprises first and second ones of the second means for electrically contacting arranged in a first one of the rows, third, fourth, and fifth ones of the second means for electrically contacting arranged in a second one of the rows, and sixth and seventh ones of the second means for electrically contacting arranged in a third one of the rows, wherein the second one of the rows is adjacent to, and lies between, the first one of the rows and the third one of the rows; and respective means for electrically connecting extending from the first, second, third, fourth, fifth, and sixth ones of the second means for electrically contacting between the sixth and seventh ones of the second means for electrically contacting. In some embodiments, each of the groups of the second means for electrically contacting further comprises: a first column of the second means for electrically contacting comprising the third and sixth ones of the second means for electrically contacting; a second column of the second means for electrically contacting comprising the first and fourth ones of the second means for electrically contacting; and a third column of the second means for electrically contacting comprising the second, fifth and seventh ones of the second means for electrically contacting; wherein the second column of the second means for electrically contacting is adjacent to, and lies between, the first and third columns of the second means for electrically contacting. In some embodiments, the first means for electrically contacting disposed upon the first surface of the first circuit board layer further comprise: a second plurality of first means for electrically contacting arranged in three rows; wherein each of the second means for electrically contacting is electrically coupled to one of the second plurality of first means for electrically contacting.

In general, in one aspect, the invention features method comprising: providing a first circuit board layer comprising a first surface; disposing, upon the first surface of the first circuit board layer, a plurality of lands arranged in three rows and comprising at least one group of the lands, wherein each group of the lands comprises first and second ones of the lands arranged in a first one of the rows, third, fourth, and fifth ones of the lands arranged in a second one of the rows, and sixth and seventh ones of the lands arranged in a third one of the rows, wherein the second one of the rows is adjacent to, and lies between, the first one of the rows and the third one of the rows; and respective traces extending from the first, second, third, fourth, fifth, and sixth ones of the lands between the sixth and seventh ones of the lands.

In some embodiments, each of the groups of the lands further comprises: a first column of the lands comprising the third and sixth ones of the lands; a second column of the lands comprising the first and fourth ones of the lands; and a third column of the lands comprising the second, fifth and seventh ones of the lands; wherein the second column of the lands is adjacent to, and lies between, the first and third columns of the lands. Some embodiments comprise providing a second circuit board layer comprising a second surface; disposing, upon the second surface of the second circuit board layer, a plurality of vias arranged in three rows and comprising at least one group of the vias, wherein each group of the vias comprises first and second ones of the vias arranged in a first one of the rows, third, fourth, and fifth ones of the vias arranged in a second one of the rows, and sixth and seventh ones of the vias arranged in a third one of the rows, wherein the second one of the rows is adjacent to, and lies between, the first one of the rows and the third one of the rows; and respective traces extending from the first, second, third, fourth, fifth, and sixth ones of the vias between the sixth and seventh ones of the vias. In some embodiments, each of the groups of the vias further comprises: a first column of the vias comprising the third and sixth ones of the vias; a second column of the vias comprising the first and fourth ones of the vias; and a third column of the vias comprising the second, fifth and seventh ones of the vias; wherein the second column of the vias is adjacent to, and lies between, the first and third columns of the vias. In some embodiments, the lands disposed upon the first surface of the first circuit board layer further comprise: a second plurality of lands arranged in three rows; wherein each of the vias is electrically coupled to one of the second plurality of lands.

In general, in one aspect, the invention features a multi-layer circuit board comprising: a first circuit board layer comprising a first surface having disposed thereon a plurality of lands, and respective first traces extending from the lands; and a second circuit board layer comprising a second surface having disposed thereon a plurality of vias arranged in three rows and comprising at least one group of the vias, wherein each group of the vias comprises first and second ones of the vias arranged in a first one of the rows, third, fourth, and fifth ones of the vias arranged in a second one of the rows, and sixth and seventh ones of the vias arranged in a third one of the rows, wherein the second one of the rows is adjacent to, and lies between, the first one of the rows and the third one of the rows, and respective second traces extending from the first, second, third, fourth, fifth, and sixth ones of the vias between the sixth and seventh ones of the vias.

In some embodiments, each of the groups of the vias further comprises: a first column of the vias comprising the third and sixth ones of the vias; a second column of the vias comprising the first and fourth ones of the vias; and a third column of the vias comprising the second, fifth and seventh ones of the vias; wherein the second column of the vias is adjacent to, and lies between, the first and third columns of the vias. In some embodiments, at least one of the lands is electrically coupled to at least one of the vias.

In general, in one aspect, the invention features multi-layer circuit board comprising: first circuit board layer means for supporting comprising a first surface having disposed thereon a plurality of first means for electrically contacting, and respective first means for electrically connecting extending from the first means for electrically contacting; and a second circuit board layer comprising a second surface having disposed thereon a plurality of second means for electrically contacting arranged in three rows and comprising at least one group of the second means for electrically contacting, wherein each group of the second means for electrically contacting comprises first and second ones of the second means for electrically contacting arranged in a first one of the rows, third, fourth, and fifth ones of the second means for electrically contacting arranged in a second one of the rows, and sixth and seventh ones of the second means for electrically contacting arranged in a third one of the rows, wherein the second one of the rows is adjacent to, and lies between, the first one of the rows and the third one of the rows, and respective second means for electrically connecting extending from the first, second, third, fourth, fifth, and sixth ones of the second means for electrically contacting between the sixth and seventh ones of the second means for electrically contacting.

In some embodiments, each of the groups of the second means for electrically contacting further comprises: a first column of the second means for electrically contacting comprising the third and sixth ones of the second means for electrically contacting; a second column of the second means for electrically contacting comprising the first and fourth ones of the second means for electrically contacting; and a third column of the second means for electrically contacting comprising the second, fifth and seventh ones of the second means for electrically contacting; wherein the second column of the second means for electrically contacting is adjacent to, and lies between, the first and third columns of the second means for electrically contacting. In some embodiments, at least one of the first means for electrically contacting is electrically coupled to at least one of the second means for electrically contacting.

In general, in one aspect, the invention features a method comprising: providing a first circuit board layer comprising a first surface; disposing, upon the first surface of the first circuit board layer, a plurality of lands, and respective first traces extending from the lands; providing a second circuit board layer comprising a second surface; disposing, upon the second surface of the second circuit board layer, a plurality of vias arranged in three rows and comprising at least one group of the vias, wherein each group of the vias comprises first and second ones of the vias arranged in a first one of the rows, third, fourth, and fifth ones of the vias arranged in a second one of the rows, and sixth and seventh ones of the vias arranged in a third one of the rows, wherein the second one of the rows is adjacent to, and lies between, the first one of the rows and the third one of the rows, and respective second traces extending from the first, second, third, fourth, fifth, and sixth ones of the vias between the sixth and seventh ones of the vias; and electrically coupling at least one of the lands to at least one of the vias.

In some embodiments, each of the groups of the vias further comprises: a first column of the vias comprising the third and sixth ones of the vias; a second column of the vias comprising the first and fourth ones of the vias; and a third column of the vias comprising the second, fifth and seventh ones of the vias; wherein the second column of the vias is adjacent to, and lies between, the first and third columns of the vias.

The leading digit(s) of each reference numeral used in this specification indicates the number of the drawing in which the reference numeral first appears.

DETAILED DESCRIPTION

Embodiments of the present invention provide circuit boards having land and/or via arrangements that reduce the number of circuit board layers compared to prior art arrangements. According to embodiments of the present invention, certain lands (and vias) are omitted from certain rows to accommodate traces from other rows, thereby permitting a higher number of rows of lands (and vias) to be used on each circuit board layer.

FIGS. 3A-Cshow three circuit board layers300A-C, respectively, for a multi-layer circuit board300according to embodiments of the present invention. Circuit board layers300A-C comprise lands302, traces304, and vias306. Each circuit board layer300A-C is capable of supporting traces304for three rows of lands302(for top layer300A) or three rows of vias306(for internal layers300B-C). Multi-layer circuit board300ofFIG. 3has seven rows308A-G of lands302, and uses only three circuit board layers300A-C for traces304. Of course, other embodiments may provide other numbers of layers, as will be apparent to one skilled in the relevant arts based on the disclosure and teachings provided herein.

In some embodiments, for a 1 mm BGA package pitch, each land302has a diameter of approximately 20 mils, each via306has a diameter of approximately 23 mils, the distance between the centers of two adjacent lands302or vias306in a row or column is approximately 20 mils, the width of each trace304is approximately 5 mils, and the minimum distance between traces304is approximately 5 mils. Of course, other embodiments may provide other dimensions, as will be apparent to one skilled in the relevant arts based on the disclosure and teachings provided herein.

Referring toFIG. 3A, top layer300A includes seven rows308A-G of lands, which of course will accommodate an integrated circuit package having seven rows of balls. Lands302in the outermost three rows308A-C generally have traces304disposed upon top layer300A, although some of the lands302in rows308A-C can be connected to vias instead, as shown inFIG. 3A.

Lands in the remaining four rows308D-G are generally connected to vias306, which can be connected to traces in inner layers300B-C. According to embodiments of the present invention, each layer300A-C can support traces for three rows308of lands302(or vias306). Therefore, referring toFIG. 3B, vias306in rows308D-F are generally connected to traces304on inner layer300B. Similarly, referring toFIG. 3C, vias306in row308G are generally connected to traces304on inner layer300C.

Each layer300A-C of circuit board300includes one or more groups310of lands302(or vias306) arranged to have an omitted land302(or via306) to allow room for traces304from other lands302(or vias306) in the group.FIG. 4shows one such group310A from top layer300A of circuit board300.

Group310A includes eight lands302A-H (marked simply as A-H inFIG. 4) arranged in three adjacent rows and three adjacent columns, although land302H is not required. Lands302A-B are arranged in the innermost row, lands302C-E are arranged in the middle row, and lands302F-G are arranged in the outermost row. In embodiments of the present invention, a land302is omitted between the lands302F and302G in the outermost row, thereby creating space for traces304from the other lands302A-E to pass between lands302F and302G.

FIG. 5shows a corresponding group310B of vias306from inner layer300B of circuit board300. Group310B includes eight vias306A-H (marked simply as A-H inFIG. 5) arranged in three adjacent rows and three adjacent columns, although via306H is not required. Vias306A-B are arranged in the innermost row, vias306C-E are arranged in the middle row, and vias306F-G are arranged in the outermost row. In embodiments of the present invention, a via306is omitted between the vias306F and306G in the outermost row, thereby creating space for traces304from the other vias306A-E to pass between vias306F and306G.

FIG. 6shows a process600for fabricating one or more layers of a multi-layer circuit board such as multi-layer circuit board300ofFIG. 3according to embodiments of the present invention. Although in the described embodiments, the elements of process600are presented in one arrangement, other embodiments may feature other arrangements, as will be apparent to one skilled in the relevant arts based on the disclosure and teachings provided herein. For example, the top layer of the circuit board can be fabricated according to conventional techniques, while one or more inner layers are fabricated according to embodiments of the present invention.

Process600provides a top circuit board layer300A (step602). Process600disposes, upon the surface of the circuit board layer, a plurality of lands302including one or more groups310A of the lands302arranged as shown inFIG. 4(step604) and respective traces arranged as shown inFIG. 4(step606).

If no inner layers are needed (step608), process600is done (step610). But if one or more inner layers are needed (step608), process600provides one or more further inner circuit board layers (step612). For example, referring toFIG. 3B, process600provides a first inner circuit board layer300B. Process600disposes, upon the surface of first inner circuit board layer300B, a plurality of vias306including one or more groups310B of the vias306arranged as shown inFIG. 5(step614) and respective traces304arranged as shown inFIG. 5(step616).

If no additional rows of contacts are needed (step618), for example because fewer than seven rows of contacts are needed, process600is done (step620), with only two circuit board layers providing six rows of contacts. But if an additional (seventh) row of contacts is needed, referring toFIG. 3C, process600provides a second inner circuit board layer300C (step622). Process600disposes, upon the surface of second inner circuit board layer300C, a plurality of vias306(step624) and respective traces304(step626), for example arranged as shown inFIG. 3C. Then process600is done (step628).

A number of implementations of the invention have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the invention. For example, while the arrangement of lands302shown inFIG. 4is ideal for the top layer in a multi-layer circuit board, the arrangement can also be used for the only layer in a single-layer circuit board. Accordingly, other implementations are within the scope of the following claims.