Semiconductor device

The first and second intrinsic semiconductor layers of thickness d are formed on a P type semiconductor substrate, keeping a prescribed interval therebetween, whereby a groove of depth d may be made between these layers. A dielectric layer is formed in such a way that it may cover a base and sides of the groove and a surface of the intrinsic semiconductor layer. On this surface, a gate electrode formed of polysilicon exists. Diffusion regions of a source and a drain of depths X.sub.sj and X.sub.dj are formed, in the neighborhood of groove sides, in the first and second intrinsic semiconductor layers (X.sub.sj, X.sub.dj d), resulting in an MOS transistor.

BACKGROUND OF THE INVENTION 
This invention relates to a semiconductor device such as an MOS transistor 
which shortens the essential channel length by forming a groove. 
A tendency toward an integration of high density, and toward a high speed 
operation of MOS IC, necessitates a considerable miniaturization of the 
individual MOS transistors forming the IC. 
The shortening of so-called channel length between regions of source and 
drain of MOS transistors is desirable in order to reduce the volume of the 
MOS transistor and the electrostatic capacity of the gate portion, thus 
increasing the operation speed. When the channel length L between the 
source and drain regions is sufficiently large in comparison with 
diffusion depths X.sub.j of the source and drain regions and the breadth 
of depletion layer, an equipotential line becomes approximately parallel 
to the substrate surfaces, and the operation of the MOS transistor is 
stable, not depending upon the channel length L or the diffusion depth of 
X.sub.j ; however, when a channel length becomes equal or less than 5.mu. 
and extends to the diffusion depths X.sub.j of the source and drain 
regions and to the breadth of the depletion layer, the equipotential lines 
in the channel becomes distorted and its distribution depends upon the 
depth X.sub.j of diffusion of the source and drain regions and the breadth 
of depletion layer. In consequence, a threshold value of voltage Vth 
allowing the source and drain regions to conduct by means of applying 
voltage Vth to the gate electrode, decreases with a reduction of the 
channel length and a small scatter of the channel length causes a big 
dispersion of the threshold voltage Vth. 
Even more so, the said equipotential line ends up by depending upon the 
diffusion depths X.sub.j of the source and drain regions and the voltage 
applied to the drain, and it is liable to produce a punch through between 
the source and drain regions, due to the effect of short channel. In order 
to deal with this kind of problem, diffusion depths X.sub.j of the source 
and drain regions may be minimized. However, the manufacture of an MOS 
transistor with small X.sub.j causes other problems, such as difficulties 
of heat treatment and penetration, the drop of the breakdown voltage at a 
p-n junction in the neighborhood of a semiconductor substrate and the 
increase of sheet or surface resistances of diffusion area of the source 
and drain. 
Instability and difficulty of such operation characteristics are big 
obstacles in the manufacture of IC of higher integrality. 
SUMMARY OF THE INVENTION 
Therefore, the first object of this invention is to provide a semiconductor 
device composed in such a way as to have a high density and high 
integrality but tends to prevent trouble arising from a short channel 
effect. 
The second object of the invention is to provide an MOS transistor of 
smaller size and of higher stability by composing it in such a way that a 
channel portion is limited to only the bottom of a groove. 
The third object of the invention aims at an MOS transistor composed in 
such a way that problems resulting from the structure of a source portion 
of the MOS transistor may be solved without creating conventional problems 
due to a short channel effect.

DETAILED DESCRIPTION OF THE INVENTION 
In FIG. 1, two intrinsic semiconductor layers 12 and 13 of thickness d, 
being separated from each other by a distance L, are placed on a P type 
semiconductor substrate 11, which results in a groove 14 having a depth d 
and a breadth L between the intrinsic semiconductor layers 12 and 13. 
n.sup.+ diffusion regions 15 and 16 are formed in the semiconductor layers 
12 and 13 respectively used as a source diffusion region of depth X.sub.sj 
and a drain diffusion region of depth x.sub.dj. 
Here, the depths X.sub.sj and X.sub.dj respectively of the source and drain 
regions 15 and 16 are formed so as to be less than the depth d of the 
groove 14. 
A film of SiO.sub.2 17 as a dielectric layer of substantially uniform 
thickness is formed on a part of the surfaces of the intrinsic 
semiconductor layers 12 and 13 coming in contact with the bottom and sides 
of the groove 14. On a surface of the SiO.sub.2 film 17, there exists a 
gate electrode 18 made of polysilicon. 
On the said diffusion regions of source and drains 15, 16, a source 
electrode 19 and a drain electrode 20 are formed by a conventional wiring 
technique and thus an MOS transistor is completed. 
In FIG. 1, S, G and D represent respectively terminals of a source, a gate 
and a drain. Next, one example of manufacturing process of the MOS 
transistor in FIG. 1 is explained by referring to FIG. 2A to FIG. 2F. As 
shown in FIG. 2A, an intrinsic semiconductor layer 21 of thickness of 
about 1.2.mu. is formed by an ion implantation process on the surface of a 
P type semiconductor layer 11. The semiconductor layer 21 may be made with 
an epitaxial growth method. A concentration of impurity of the 
semiconductor layer 11 is about 5.times.10.sup.15 /cm.sup.3. In the 
process of FIG. 2B, silicon oxide layers 22a and 22b and Si.sub.3 N.sub.4 
layers 22a and 23b are formed at appointed places of the source and drain 
separated from each other by a distance 2.mu. on the intrinsic 
semiconductor layer 21. Moreover, p.sup.+ regions 24 a and 24b of impurity 
concentration of about 10.sup.18 /cm.sup.3 are made in the semiconductor 
layer 21. 
Next, in the process of FIG. 2C, SiO.sub.2 layers 25a, 25b and 26, depth 
about 2.0.mu., are formed on the P.sup.+ regions 24 a, and 24b by heat 
treating the element of FIG. 2B in an oxidizing atmosphere. Following 
this, in the process of FIG. 2D, after forming resist films 26a and 26b 
only on the SiO.sub.2 layers 25a and 25b, the SiO.sub.2 layer 26 is 
removed by etching, and a groove 27 of breadth about 2.mu. and of depth 
about 1.2.mu. is formed on the P type semiconductor substrate 11. 
Since the thickness of the intrinsic semiconductor layers 21 and 21a is 
about 1.2.mu., the surface of the semiconductor substrate 11 is just 
exposed on the bottom of the groove 27. Next, in the process of FIG. 2E, 
the resist films 26a and 26b are removed, and then a SiO.sub.2 layer 28 of 
thickness about 0.1.mu. as a whole is formed, on which a gate electrode 29 
of over all length about 3.5.mu., made of polysilicon is formed. At last, 
in the process of FIG. 2F, the source 15 and drain 16 regions are formed, 
whose diffusion depths X.sub.sj and X.sub.dj from the surfaces of the 
intrinsic semiconductor layers 21 and 21a are respectively about 0.5.mu.. 
In the process of FIG. 2F, the source and drain regions 15, 16 are formed 
in such a manner that an n type impurity is diffused into the intrinsic 
semiconductor layers 21 and 21a at the portion where the SiO.sub.2 film 28 
is removed. The concentration of the n type impurity is about 10.sup.19 
/cm.sup.3. 
Hereafter, following a conventional production process, setting of 
electrode and passivation, the manufacturing process of the MOS transistor 
is completed, Moreover, in this example, first of all, the intrinsic 
semiconductor layer 21 was formed on the semiconductor substrate 11, but 
it may be possible to shift a period of formation of the intrinsic 
semiconductor layer 21 to the stage of processes of FIG. 2B and FIG. 2C by 
making use of an ion implantation method, and it is also possible to apply 
a choiced epitaxial growth process for production. 
FIG. 3 shows a schematic drawing of a distribution of depletion layer at a 
time of operation of the MOS transistor shown in FIG. 1. In FIG. 3, since 
the intrinsic semiconductor layers 12, 12a, 13 and 13a exist between the 
diffusion region of the source 15 and drain 16 and the P type 
semiconductor substrate 11, a part of the depletion layer 30 constituted 
in the substrate 11 under the areas of the source 15 and drain and 16 will 
have a very narrow breadth and, being interdependent on the effect of this 
special structure forms a channel 31 at the bottom of the groove 14. The 
depletion layer 30, due to the location of the source and drain 15 and 16 
proves to be effective to prevent the creation of a short channel effect. 
Moreover, since thickness variations of the depletion layer just under the 
drain region 16 in respect to a variation of drain voltage are smaller 
than is the case when an intrinsic semiconductor layer is not provided 
between the substrate 11 and the drain region 16, this embodiment proves 
to be effective to decrease the short channel effects of dependence on a 
drain voltage for a value of the threshold voltage Vth. In the structure 
of FIG. 3, the channel 31 encloses the groove 14 and it looks as if it has 
a large length of channel, but in actuality the channel 31 is not so 
large. Since an inversion layer is formed at the semiconductor dielectric 
boundary, the threshold voltage Vth to be applied to the gate presents a 
much smaller value in the case of using intrinsic semiconductor layers 12 
and 13 than in the case of only using the P type substrate 11 portion. 
Accordingly, the intrinsic semiconductor layer-portions 12a, 13a are 
formed, respectively, with sufficiently thick inversion layers with 
respect to the gate voltage permitting the formation of an inversion layer 
at the P type portion 31 right below the groove 14. For this reason, the 
effective channel portion wherein the current is to be controlled by the 
gate voltage is limited only to the portion 31 of the P type substrate 
surface right below the gate. 
Another merit of providing the intrinsic semiconductor layers (12, 12a) and 
(13, 13a) between the P type substrate 11 and the drain region 16, 
respectively, is that such provision enables an increase in the breakdown 
voltage at the p-n junctions between the P type substrate 11 and the n 
type source region 15 and between the P type substrate 11 and the drain 
region 16. Especially, a decline of the breakdown voltage when reducing 
the depths X.sub.sj and X.sub.dj of diffusion regions 15 and 16 can be 
well avoided. 
In relation to this, without bringing upon a decline of breakdown voltage 
of said p-n junction, it is possible to elevate a concentration of 
impurity of the P type substrate 11. 
This fact is linked with a reduction of the breadth of the depletion layer 
and shows that a whole body of MOS transistor may be miniaturized, without 
introducing the short channel effect. 
Furthermore, by means of holding an intrinsic semiconductor layer, that is, 
a semiconductor layer of high resistance 12 and 13 between the regions of 
source and drain 15 and 16 and the substrate 11, the electrostatic 
capacity at the p-n junction can be reduced. 
This is useful for speeding up of the whole IC composed of MOS transistors. 
Several embodiments of the invention can be considered, besides the said 
embodiments. They are explained in referring to FIG. 4 to FIG. 12. Same 
reference numerals are applied to the same parts as FIG. 1 and FIG. 3. 
First of all, in the embodiments of FIG. 1 and FIG. 3, the case of 
X.sub.sj =X.sub.dj is considered, and it is a matter of course to obtain a 
smaller effect in case of X.sub.sj .noteq.X.sub.dj. 
In the structure of the device shown in FIG. 3, the intrinsic semiconductor 
layers 12a and 13a are provided in neighborhood of the both sides of 
groove 14, but as shown in FIG. 4, a similar effectiveness can be 
obtained, even for structures having no said portions 12a nor 13a, only 
with the intrinsic semiconductor layers 12 and 13 of uniform thickness. 
Moreover, as shown in FIG. 5, a similar effect has been obtained by holding 
n.sup.- layers 12b and 13b of very low concentration of impurity between 
the regions of source and drain and the P type substrate 11 in place of 
the intrinsic semiconductor layers 12 and 13. Needless to say, a similar 
enforcement can be carried out by making use of P layers 12C and 13c, as 
shown in FIG. 6, in place of n.sup.- layers 12b and 13b. In each said 
embodiment, an MOS transistor of n channel has been described, but a whole 
similar operation can be carried out in case of an MOS transistor of P 
channel. FIG. 7, FIG. 8 and FIG. 9 show each embodiment in this case, 
namely, the embodiment of FIG. 7 consists of semiconductor layers 12c and 
13c of P type between the substrate of n type 11n and the regions of 
source and drain of P.sup.+ type 15p and 16p. The embodiment of FIG. 8 
consists of semiconductor layers of n.sup.- type 12b and 13b between the 
substrate of n type 11n and the regions of source and drain 15p and 16p. 
The embodiment of FIG. 9 is formed by holding the intrinsic semiconductor 
layers 12 and 13 between the substrate of n type 11n and the regions of 
source and drain of P.sup.+ type 15p and 16p. Every embodiment is an MOS 
transistor of P channel and its operation is similar to the case of the 
said embodiments. The embodiment of FIG. 10 is surrounded by the intrinsic 
semiconductor layers 12 and 13 round the regions of source and drain of 
n.sup.+ type and other compositions; operations are similar to those of 
the embodiment of FIG. 3. 
The embodiment of FIG. 11 shows the case of high resistive layer of P.sup.- 
type 13c at the drain side thicker than the layer at source side 12c and 
the source region 15 is formed thicker than the drain region 16. The 
embodiment of FIG. 12 is provided with a high resistive layer 13c of 
p.sup.- type only at the side of drain and the region of source 15 is 
formed so as to be directly adjacent to the P type substrate. 
Similar effectiveness can be obtained with the embodiments of FIG. 11 and 
FIG. 12. 
In FIG. 13, a groove 14 is formed with depth d on the surface of the P type 
substrate 11, and a dielectric layer 17 is made so as to cover an inner 
surface of groove 14 and a gate electrode 18 made of polysilicon is 
provided on a dielectric layer 17. The region of source 15 with a depth 
X.sub.sj and that of drain 16 with a depth X.sub.dj are formed by 
diffusing impurity of n type from the surface of the substrate 11 of the 
side of the groove 14. Upon them, a source electrode 19 and a drain 
electrode 20 are established. At this time, a depth of drain region 
X.sub.sj is formed so as to be represented by the formula 
##EQU1## 
There is no doubt that the depth of the groove 14 is made sufficiently 
large as to prevent the value from becoming negative. 
Where 
.epsilon.=dielectric coefficient of silicon 
N=concentration of impurity in silicon 
.phi..sub.F =fermi level 
V.sub.S =built-in electric field 
q=elementary charge 
V.sub.SUB =substrate voltage As shown in FIG. 13, a distance between a 
bottom face of P type substrate 11 and a bottom face of a source region 15 
is represented by X.sub.dj, and a distance between a bottom face of P type 
substrate 11 and a bottom face of a groove 14 is given by X.sub.d2. We 
have 
EQU X.sub.sj +X.sub.d1 .ltoreq.d+X.sub.d2 (2) 
The depth X.sub.sj of diffusion of the source region 15 is given by the 
formula (3). 
EQU X.sub.sj .ltoreq.d-X.sub.d1 +X.sub.d2 (3) 
It is well known that 
##EQU2## 
Substitution of (4) and (5) formula with (3), result in 
##EQU3## 
In FIG. 13, the formation of the source and drain 15 and 16 may be made by 
a diffusion, ion implantation and any other methods and a groove may be 
formed by a chosen epitaxial process, besides the etching process. A 
manufacturing process of the device shown in FIG. 13 is explained in 
referring to the FIG. 14 to FIG. 19. In the process of FIG. 14, a 
substrate 11 of p.sup.- type of concentration of impurity about 10.sup.15 
/cm.sup.3 is prepared. 
In the process of FIG. 15, oxide film layers 31a, 31b, and Si.sub.3 N.sub.4 
layers 32a and 32b are formed at prearranged positions of the source and 
drain, mutually separated by 2.mu. on the substrate 11, and on their 
outsides, P.sup.+ layers 30a and 30b of concentration about 10.sup.18 
/cm.sup.3 for a field use are established. Moreover, after forming 
SiO.sub.2 layers 33a, 33b and 34 of depth about 2.0.mu., by oxidation, in 
the process of FIG. 16, apply resists 35a and 35b in the process of FIG. 
17 and remove SiO.sub.2 layer 34 and thereby on the surface of the 
semiconductor substrate a groove of depth about 1.2.mu. is made. Remove 
resists 35a and 35b and form a SiO.sub.2 layer 17 of thickness about 
0.1.mu. in the process of FIG. 18. In the next process of FIG. 19, a gate 
electrode 18 of length 3.5.mu. consisting of polysilicon is formed on the 
layer of SiO.sub.2 layer 17. 
An impurity concentration of about 10.sup.19 /cm.sup.3 is obtained by 
diffusing impurities of n type at portion where part of oxide layers of 
SiO.sub.2 33a, 33b and 17 are removed, and a source region 15 and a drain 
region 16 are made in such a way that diffusing depth X.sub.sj from the 
surface of each region is approximately equal to 1.0.mu.. 
Hereafter, according to a conventional production process, prevention of 
deterioration is carried out by attachment of electrodes and a coating of 
PS.sub.i glass, and MOS transistors to be used under condition of 
V.sub.SUB =OV are formed. 
Schematic drawings of equipotential lines for the operation of an MOS 
transistor whose structure is given in FIG. 13, are shown in FIG. 20 and 
FIG. 21. 
In FIG. 20, equipotential lines from a channel portion just under the 
groove 14 up to a portion right under the source 15 become parallel to the 
surface by regulating a depth of diffusion X.sub.sj of the source region 
15. When a diffusion of the source 15 is deeper, equipotential lines near 
to the source 15 are lowered and become convex upward in the neighborhood 
of the groove 14 and a value of threshold voltage to be applied to the 
gate 18 becomes smaller resulting in the creation of a short channel 
effect. On the other hand, when a diffusion of the source 15 is shallower, 
a distribution of equipotential lines becomes like FIG. 21. At the source 
region 15, equipotential lines are drawn upward in opposite direction to 
the aforesaid. 
Owing to this fact, a curve becomes convex downward at a source portion 36 
near the groove 14. 
A value of threshold voltage at this portion becomes greater than that of 
other portion of channel and it is hard to form a reversed layer. In order 
to make act switches by controlling current from the source region 15 to 
the drain region 16, a formation of a reversed layer at a starting portion 
of a channel plays an important role, so that it is obviously possible to 
obtain an element of a short channel showing the same stable value of 
threshold voltage as a transistor of a long channel by excluding a 
variation of values of threshold voltage due to a bending of an 
equipotential line near by the source region 15. Moreover, this structure 
prevents otherwise easy breakdowns between the source 15 and drain 16. It 
is not necessary to minimize too much X.sub.dj and X.sub.sj, according to 
the embodiment, so technical difficulties such as heat treatment and 
penetration can be avoided and inconveniences such as an increase of 
surface resistances of the source and drain regions and a drop of 
break-down voltage etc. can be prevented. The embodiment shown in FIG. 13 
is treated for the case of X.sub.sj =X.sub.dj. 
The value of X.sub.dj may be established in such a way that it can prevent 
a threshold voltage from lowering, equipotential lines go straight on, and 
X.sub.dj is kept within a suitable range of values. MOS transistors of P 
channel can be composed in the same way as the above-mentioned MOS 
transistors of n channel. In the said embodiment, that is, the device of 
FIG. 13, a face constituting a channel of a bottom of the groove 14 and a 
face composing a channel of a side of the groove 14 become different 
crystal planes, respectively, for example, a (100) plane and a (111) 
plane. 
A difference of electric characteristics between both faces may induce 
influences as harmful as a variation of values of threshold voltage, etc. 
Embodiments mentioned below give small sized and high stable MOS 
transistors whose channel portions are limited only at the bottoms of the 
grooves. 
FIG. 22 to FIG. 24 show respectively a top view and cross sectional views 
of a MOS transistor based on the above-mentioned ideas. Parts similar to 
those of the embodiments above-mentioned have the same reference numerals. 
An insulating layer of heavy thickness for field use 40 is formed so as to 
enclose the MOS transistor composed of a source region 15, drain region 
16, a gate insulating layer 17 and a gate electrode 18. 
Hereupon, the deepest portion 41 of the boundary surface between the 
insulating layer for field use 40 and semiconductor substrate 11 is 
located more deeply than the face 42 forming the channel under the gate. 
The device shown in FIG. 22 to FIG. 24 as embodiment is manufactured 
through the process shown in FIGS. 25 to 31. 
First of all, a laminate film is composed of SiO.sub.2 layer 50 and 
Si.sub.3 N.sub.4 layer 51 applied on a surface of Si substrate 11 of P 
type with concentration of impurity about 10.sup.15 /cm.sup.3. 
Next, at the process of FIG. 26, this laminate film is removed at an 
appointed portion a formation of an insulating layer, and a P.sup.+ type 
layer 52a and 52b having concentration of impurity of about 10.sup.18 
/cm.sup.3 is formed by diffusion. 
Moreover, at the process of FIG. 27, after oxidizing the surface of the 
substrate 11 and forming the oxide layer 53a and 53b of thickness about 
1.5.mu. at the field area, remove the gate portion of the said laminate 
film 50 and 51 by etching. 
Next, at the process of FIG. 28 form an oxide layer 54 with thickness about 
2.mu. at the gate portion by oxidizing as a whole, and then inject 
phosphorus, for example, through the laminate film by ion implantation 
method, in order to make a source region of n.sup.+ type 15 and a drain 
region 16 of thickness about 0.8 .mu.m with concentration of impurity 
about 10.sup.19 /cm.sup.3. 
Thereafter, leave oxide layers 53a and 53b in the area of field as they 
are, and remove an oxide layer 54 at the gate region and the laminate 
films 50 and 51 above the source and drain regions 15 and 16. Next, in the 
process of the FIG. 29, the groove 14 of width about 2.mu. and depth about 
1.2.mu. is formed by etching of oxide layer 54. 
Thereafter, a gate oxide layer 17 of thickness about 0.1.mu. is formed in 
the process shown in FIG. 30, by a conventional manufacturing process of 
polycrystal silicon gate MOS transistors. 
In succession, through the process shown in FIG. 31, provide a gate 
electrode of polycrystal silicon, and after patterning, cover the whole 
surface with the oxide layer 55 by chemical vapor deposition process and 
open a contact hole and then evaporate A1 and form contact electrodes 56 
and 57 of the source and drain regions by patterning, and also, form 
contact electrodes of the gate (not indicated by figure), outside of 
transistor domain to complete the work. 
In the MOS transistor thus fabricated, the interface between the oxide film 
40 in a field area (FIGS. 22 to 24) and the substrate 11 is made so as to 
be situated under the channel 42 of the bottom of the groove 14; 
therefore, the channel is made only at the bottom of the groove 14, as 
shown clearly in FIG. 24, and not at the side of the channel. This permits 
formation of an MOS transistor having a sufficiently small width of 
channel. The MOS transistor as a practical embodiment is suitable for a 
transistor of a static RAM, for example, which requires a sufficiently 
small conductance in view of electric power consumption. Since the channel 
is formed on the crystal face, for example, the face (100) which exists at 
the bottom of the groove 14, other faces, having different electric 
characteristics and threshold values, are not involved; therefore, the 
characteristic of the MOS transistor is kept in good condition. Because of 
making the oxide layer of the field portion 40 sufficiently thick, 
protection of a field portion from a reversal is a big merit. 
According to the structure of the MOS transistor shown in this practical 
embodiment, a P-N junction between the source 15 and drain 16 of n type 
and the substrate of P type intersects the interface between the 
semiconductor substrate and oxide layer at an angle nearby a right angle, 
so a voltage-proof of breakdown can be obtained at the p-n junction and an 
instability of a value of threshold voltage due to a short channel effect 
can be avoided. 
In the practical embodiment of FIGS. 22 to 24, the p-n junction is made so 
as to be above the interface between the semiconductor of the gate domain 
and insulator, but even if it is made to be little under the interface, a 
sufficient effectiveness may be obtained, under a condition that an 
interface between a base plate in a domain of a surrounding field and an 
insulating layer is made to occupy a subordinate position in comparison 
with a channel portion. The same embodiment shows the case of MOS 
transistor of P channel. 
As the FIG. 32, a same composition can be obtained by using a Si substrate 
of n type, and moreover, this structure is applicable to constituent 
elements of an MOS transistor of Bucket Brigade Device (BBD) and is able 
to control a variation of a value of threshold voltage due to a short 
channel effect. 
This structure improves also the efficiency of electric charge transfer and 
is useful for an improvement of the break down voltage. 
Moreover, as shown in FIG. 33, even if the structure is composed so as to 
make lie a portion of the substrate 11 among the source region 15, a drain 
region 16 and a groove 14 of channel portion, without making it be 
adjacent to them, a sufficient effect may be obtained.