(N+1) input flip-flop packing with logic in FPGA architectures

A logic module and flip-flop includes input multiplexers having data inputs coupled to routing resources. A clock multiplexer has inputs coupled to clock resources, and an output. An input-select multiplexer has a first input coupled to the output of an input multiplexer. A flip-flop has a clock input coupled to the output of the clock multiplexer, and a data output coupled to an input of the input-select multiplexer. A logic module has data inputs coupled to the output of the input select multiplexers. A flip-flop multiplexer is coupled to the data input of the flip-flop, and has inputs input coupled to the output of the first input multiplexer, the data output of the logic module, and a third input coupled to routing resources.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to user-programmable circuits. More particularly, the present invention relates to field programmable gate array (FPGA) integrated circuits and to arrangements for flip-flop and logic circuits in FPGA architectures.

2. The Prior Art

Modern FPGA functionality is provided by logic modules and flip-flops. Logic modules can be n-input look-up-tables (n-LUTs) or any other kind of function generators with n inputs, where (n>1). The flip-flops can be simple D type flip-flops, or they can have additional functionality such as CLEAR, RESET, LOAD, and ENABLE. These additional functions (with the exception of ENABLE) can be synchronous with the clock (CLK) or asynchronous (or both.)

Logic modules and flip-flops are often grouped into clusters that may typically vary in size from four to more than twenty. The clustering provides no additional functionality; it is done for routing convenience. In addition to the functionality provided by the logic modules and flip-flops, the FPGAs may include other types of functional blocks such as multipliers, RAMs, FIFOs, etc.

The most common arrangement of logic modules and flip-flops is shown inFIG. 1. In this kind of arrangement, the Y output of a logic module10directly drives the D input of the flip-flop12. The A, B, C, and D data inputs of the logic module12are each driven by a multiplexer; multiplexer14drives data input A, multiplexer16drives data input B, multiplexer18drives data input C, multiplexer20drives data input D. Each of multiplexers14,16,18, and20have a plurality of data inputs that are driven from routing tracks as is known in the art. Multiplexer22allows the Q output of flip-flop12to be used as an additional input to the D data input of logic module10. The CLK input of flip-flop12is driven by the output of multiplexer24, which allows selection between the various clock resources at its data inputs.

The arrangement shown inFIG. 1has been used in earlier anti-fuse based FPGA products designed and marketed by Actel Corporation of Mountain View Calif. This is an economical in arrangement in terms of routing fabric usage, but it is also the most limited in terms of flexibly packing logic functions and flip-flops together. Unless the flip-flop is packed with the logic that drives it, the logic block functionality must be used as a feed through buffer and is thus wasted. In typical FPGA designs, this limitation causes a large number of isolated flip-flops to be present that are not packed together with logic modules.

The packing limitations of the arrangement shown inFIG. 1can be improved significantly by allowing configurable connections between logic modules and the flip-flops, as shown inFIG. 2. An additional multiplexer26permits selection of the source of the D input to the flip-flop12between the Y output of the logic module10and the output of multiplexer20that drives the D input to the logic module10.

The arrangement shown inFIG. 2is very commonly used in various products by FPGA vendors. As will be appreciated by persons of ordinary skill in the art, the logic module10in the arrangement ofFIG. 2is no longer wasted if the D-input of the flip-flop12is not driven from within that module. On average, this improves the packing efficiency by packing 20% more flip-flops with logic modules. However, even this arrangement has limitations when the logic module10does not drive the flip-flop12. The total number of combined data inputs to the logic module10and to the flip-flop12must be “n”, the same as the maximum number of inputs to the logic module. This either means that the logic module is used in a limited role by computing a logic function of (n−1) inputs, or that one of the inputs of the logic module must be driven from the Q-output of the flip-flop.

Even though the arrangement shown inFIG. 2improves the packing density, the improvement comes with a small performance penalty due to the delay through the flip-flop multiplexer26between the logic module10and the flip-flop12. This is typically a small delay that is well worth the increase in packing density, as long as the multiplexer26remains a single-level multiplexer.

BRIEF DESCRIPTION

According to one aspect of the present invention, a logic module and flip-flop arrangement includes a first input multiplexer having a plurality of data inputs coupled to routing resources, and an output. Second through nth input multiplexers, each have a plurality of data inputs coupled to routing resources, and an output. A clock multiplexer has a plurality of inputs coupled to clock resources, and an output. An input-select multiplexer has a plurality of inputs and an output, a first input of the data select multiplexer is coupled to the output of the first input multiplexer. A flip-flop has a clock input coupled to the output of the clock multiplexer, a data output coupled to a second input of the input-select multiplexer, and a data input. A logic module has a plurality of data inputs and an output, one data input of the logic module coupled to the output of the input select multiplexer, the other data inputs of the logic module are each coupled to the output of a different one of the second through nth input multiplexers. A flip-flop multiplexer having an output coupled to the data input of the flip-flop, a first input coupled to the output of the first input multiplexer, a second input coupled to the data output of the logic module, and a third input coupled to routing resources.

According to another aspect of the present invention, the flip-flop multiplexer includes fourth and fifth inputs coupled to routing resources.

According to another aspect of the present invention, the logic module further includes a sum output, a carry-in input and a carry-out output, and the flip-flop multiplexer further includes a sixth input coupled to the sum output of the logic module.

DETAILED DESCRIPTION

The present invention addresses the limitations of prior-art architectures by enlarging the routing multiplexer in between the logic module and the flip-flop, and accepting one or more inputs from routing resources.

Referring now toFIG. 3, the A, B, C, and D data inputs of the logic module12are each driven by a multiplexer; multiplexer14drives data input A, multiplexer16drives data input B, multiplexer18drives data input C, multiplexer20drives data input D. Each of multiplexers14,16,18, and20have a plurality of data inputs that are driven from routing tracks as is known in the art. Input-select multiplexer22allows the Q output of flip-flop12to be used as an additional input to the D data input of logic module10. The CLK input of flip-flop12is driven by the output of multiplexer24, which allows selection between the various clock resources at its data inputs. Flip-flop/routing multiplexer28permits selection of the source of the D input to the flip-flop12between the Y output of the logic module10and the output of multiplexer20that drives the D input to the logic module10. The illustrative embodiment ofFIG. 3also provides a routing input directly to the flip-flop12on line30, by-passing the logic module10. Logic module10and flip flop12form a packed pair.

It has been verified that a single routing input to the flip-flop can increase the packing density by about 2.5%. The density can be increased even more by providing additional inputs to multiplexer28as shown in the illustrative embodiment ofFIG. 4. Additional inputs30,32, and34are provided directly to the flip-flop through flip-flop/routing multiplexer28, by-passing the logic module10.

The present invention may be used in connection with both clustered and non-clustered routing architectures. When used in clustered architectures, for cluster sizes ranging from eight to sixteen, having three inputs from the routing resources directly to flip-flop12that bypass logic module10as shown inFIG. 4results in a more than 5.5% density increase in clusters. For cluster sizes as large as 24, the benefit exceeds 7%. Similar improvements should be seen for non-clustered architectures.

It has been found that providing more than three inputs, however, results in diminishing returns in terms of packing density increase, except for large cluster sizes (with 18 or more logic modules and flip-flops) and special types of FPGA designs that are unusually register rich. Besides, the larger the multiplexer between the logic module and the flip-flop becomes, the slower the multiplexer gets (even if it stays as a single level multiplexer), and it is not desirable to grow it by allowing for more than three inputs for general purpose FPGAs. For FPGAs specifically targeted for high register applications, however, this can be done.

Referring now toFIG. 5, a block diagram illustrates that the present invention applies equally well for FPGAs where the logic module is combined with an arithmetic unit with a fast carry chain. In the illustrative embodiment ofFIG. 5, the logic module10can be used to perform ordinary logic functions, or in an arithmetic mode, where it is provided with a second functionally distinct “S” output. The outputs Y and S can be recombined inside the logic module, or they can both be made available to the first level of routing resources. In the latter case, the multiplexer in between the logic module and the flip-flop will have to be enlarged by one more input as shown inFIG. 5.

The present invention performs well with only a few additional inputs to the multiplexer28between the logic module10and the flip-flop12. Flip-flop/routing multiplexer28is in general much smaller than any of the multiplexers14,16,18, and20that furnish the inputs to the logic module10. This is explained by the way in which flip-flops are commonly used in logic designs programmed into FPGAs. It has been discovered that the most common mode of flip-flop usage is to drive the flip-flop from a logic module without fanout, or to drive a logic module by the flip-flop without fanout. These two cases combined account for nearly 70% of all flip-flop usage in FPGA designs. In fact these two cases can be handled very efficiently by the prior-art arrangement ofFIG. 1. The prior-art arrangement ofFIG. 2adds additional packing capability, where 90% of the flip-flops are packed with a logic module (again except for very register rich designs).

The present invention as illustratively shown inFIGS. 3,4, and5increases the packing density to more than 95% with only three additional inputs to the flip-flop/routing multiplexer28in between the logic module10and the flip-flop12. In exchange for this density increase of more than 5%, the area cost of the invention is about 0.3% of the core FPGA fabric area in a typical implementation, which makes it very attractive.