Trench metal oxide semiconductor field effect transistor with multiple trenched source-body contacts for reducing gate charge

A trench MOSFET with multiple trenched source-body contacts is disclosed for reducing gate charge by applying multiple trenched source-body contacts in unit cell. Furthermore, source regions are only formed along channel regions near the gate trenches, not between adjacent trenched source-body contacts for UIS (Unclamped Inductance Switching) current enhancement.

FIELD OF THE INVENTION

This invention relates generally to the cell structure and device configuration of power semiconductor devices. More particularly, this invention relates to a novel and improved cell structure and device configuration of a trench metal oxide semiconductor field effect transistor (MOSFET, the same hereinafter) with multiple trenched source-body contacts.

BACKGROUND OF THE INVENTION

FIG. 1Ashows a conventional trench MOSFET100of prior art, wherein a single trenched source-body contact101is penetrating through an n+ source region102and extending into a P body region103between two adjacent trenched gates104in an active area, wherein the n+ source region102is formed in an upper portion of the P body region103. For trench MOSFET like the trench MOSFET100with voltage rating below 100V (Low Voltage), channel resistance Rch accounts for about 10% and 30% of total Rds at Vgs=10V and at Vgs=4.5V respectively for a 30V N-channel device. It can be seen that the channel resistance Rchplays an important role in on-resistance, especially at Vgs=4.5V. Therefore, the smaller pitch of the device, the lower Rds. So far, the minimum 1.0 um pitch is achieved by using 0.18 um and tungsten plug technologies for a cell density around 500 M/in2. However, for voltage rating beyond 100V (Middle and High Voltages), applications of the middle and high voltage devices are more at Vgs=10V. The Rchis less than 10% of Rds. For trench MOSFETs having device structure as shown inFIG. 1A, no much improvement in Rdsbut significant increase in gate charge with higher cell density.

Another prior art U.S. Pat. No. 8,049,273 discloses a device structure110having multiple trenched source-body contacts111in unit cells for improving the peak induced voltage in switching converter, as shown inFIG. 1B. However, n+ source regions112are disposed not only along channel regions but also among the multiple trenched source-body contacts111, causing poor avalanche capability issue because two additional parasitic n+/P/N+ bipolar transistors exist in the device structure110.

Therefore, there is still a need in the art of the semiconductor power device, particularly for trench MOSFET design and fabrication, to provide a novel cell structure, device configuration that would resolve these difficulties and design limitations.

SUMMARY OF THE INVENTION

The present invention provides a trench MOSFET with multiple trenched source-body contacts for reducing gate charge. According to the present invention, the multiple trenched source-body contacts are formed in unit cell and filled with tungsten plugs for a wide mesa between two adjacent gate trenches in an active area, furthermore, source regions are only formed along channel regions near the gate trenches, not between adjacent trenched source-body contacts for UIS (Unclamped Inductance Switching) current enhancement.

In one aspect, the present invention features a trench MOSFET comprising: a substrate of a first conductivity type; an epitaxial layer of the first conductivity type onto the substrate, wherein the epitaxial layer has a lower doping concentration than the substrate; a plurality of gate trenches starting from a top surface of the epitaxial layer and extending downward into the epitaxial layer; a plurality of body regions of a second conductivity type between two adjacent gate trenches; a plurality of source regions of the first conductivity type in an upper portion of the body regions in an active area; and multiple trenched source-body contacts each filled with a contact metal plug, penetrating through the source regions and extending into the body regions, wherein the source regions are only formed along channel regions near the gate trenches in the active area, not between two adjacent trenched source-body contacts.

In another aspect, the present invention features a trench MOSFET further comprising a plurality of body contact doped regions of the second conductivity type within the body regions and surrounding at least bottoms of the multiple trenched source-body contacts, wherein the body contact doped regions have a higher doping concentration than the body regions.

In another aspect, the present invention features a trench MOSFET wherein the gate trenches can be implemented to have single gate structure comprising a single electrode padded by a gate oxide layer, wherein the gate oxide layer has a thickness along sidewalls equal to or greater than bottom of the single electrode.

In another aspect, the present invention features a trench MOSFET wherein the gate trenches can be implemented to have single gate structure comprising a single electrode padded by a gate oxide layer, wherein the gate insulation layer has a greater thickness along bottom than along sidewalls of the single electrode.

In another aspect, the present invention features a trench MOSFET wherein the gate trenches can be implemented to have terrace gate structure comprising a single electrode padded by a gate oxide layer, wherein the single electrode further extends beyond the top surface of the epitaxial layer, and the gate oxide layer has a greater thickness along bottom than along sidewalls of the single electrode. Alternatively, the gate oxide layer has a thickness along sidewalls equal to or greater than bottom of the single electrode.

In another aspect, the present invention features a trench MOSFET wherein the gate trenches can be implemented to have dual electrodes structure comprising a shielded electrode in a lower portion connected to a source metal, and a gate electrode in an upper portion of the gate trench, wherein the shielded electrode and the gate electrode are insulated from the epitaxial layer and insulated from each other.

Preferred embodiments include one or more of the following features: the contact metal plug is a tungsten metal layer padded by a barrier metal layer of Ti/TiN or Co/TiN or Ta/TiN; the trench MOSFET further comprises multiple trenched body contacts filled with the contact metal plugs and extending into the body regions.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Please refer toFIG. 2for a preferred embodiment of this invention wherein an N-channel trench MOSFET200is formed in an N− epitaxial layer201onto an N+ substrate202coated with a back metal of Ti/Ni/Ag on a rear side as a drain metal203. A plurality of gate trenches204are formed starting from a top surface of the N− epitaxial layer201and extending downward into the N− epitaxial layer201, each of the gate trenches204is formed having single gate structure comprising a single electrode205padded by a gate oxide layer206, wherein the gate oxide layer206has a thickness along sidewalls equal to along bottom of the single electrode205. Alternative, the gate oxide layer206has a thickness along sidewalls greater than the bottom of the single electrode205. The single electrode205can be implemented by using doped poly-silicon layer. A plurality of P body regions207are formed in an upper portion of the N− epitaxial layer201between two adjacent gate trenches204. Two trenched source-body contacts208-1and208-2filled with contact metal plugs209-1and209-2are penetrating through a contact interlayer210and extending into the P body region207in an active area, wherein the contact metal plugs209-1and209-2are tungsten metal layer padded by a barrier metal layer of Ti/TiN or Co/TiN or Ta/TiN. Specially, n+ source regions211are only formed along channel regions near a top surface of the N− epitaxial layer201in the active area, not between two adjacent trenched source-body contacts208-1and208-2for UIS current enhancement. A trenched body contact214is filled with the contact metal plug215which is as same as the contact metal plugs209-1and209-2and extending into the P body region207adjacent edge of the active area. A plurality of p+ body contact doped regions212are formed within the P body regions207surrounding at least bottoms of the trenched source-body contacts208-1and208-2and the trenched body contact214to reduce the contact resistance between the P body region207and the contact metal plugs209-1,209-2and215. A trenched gate contact216filled with the contact metal plug218which is as same as the contact metal plugs209-1and209-2connects a single electrode205′ in a gate trench204′ in a trenched gate contact area to a gate metal217for gate connection, wherein the single electrode205′ has a greater width than the single electrode205in the active area.

FIG. 3shows a cross-sectional view of another trench MOSFET300according to the present invention. The trench MOSFET300has a similar structure to the trench MOSFET200inFIG. 2except that, inFIG. 3, the trench MOSFET300further comprises an additional trenched body contact301between the trenched source-body contacts308-1and308-2, similarly, n+ source regions311only formed along channel regions near the gate trenches304, not among the trenched source-body contacts308-1,308-2and301for UIS current enhancement. Accordingly, the P+ body contact doped regions312are formed within the P body regions307surrounding at least bottoms of all the trenched contacts to reduce the contact resistance between the P body regions307and the contact metal plugs.

FIG. 4shows a cross-sectional view of another trench MOSFET400according to the present invention. The trench MOSFET400has a similar structure to the trench MOSFET200inFIG. 2except that, inFIG. 4, all the gate trenches404are formed having single gate structure comprising a single electrode405padded by a gate oxide layer406, wherein the gate oxide layer406has a greater thickness along bottom than along sidewalls of the single electrode405.

FIG. 5shows a cross-sectional view of another trench MOSFET500according to the present invention. The trench MOSFET500has a similar structure to the trench MOSFET200inFIG. 2except that, inFIG. 5, all the gate trenches504are formed having terrace gate structure comprising a single electrode505padded by a gate oxide layer506, wherein the single electrode505further extends beyond the top surface of the epitaxial layer501, and the gate oxide layer506has a greater thickness along bottom than along sidewalls of the single electrode505. Alternatively, the gate oxide layer has a thickness along sidewalls equal to or greater than bottom of the single electrode.

FIG. 6shows a cross-sectional view of another trench MOSFET600according to the present invention. The trench MOSFET600has a similar structure to the trench MOSFET200inFIG. 2except that, inFIG. 6, the gate trenches604are formed having dual electrodes structure comprising a shielded electrode (S, as illustrated inFIG. 6)605in a lower portion and a gate electrode (G, as illustrated inFIG. 6)606in an upper portion of the gate trench604, wherein sidewalls and bottom of the shielded electrode605are surrounded by a gate insulation layer607, sidewalls of the gate electrode606are surrounded by a gate oxide layer608, wherein the shielded electrode605and the gate electrode606are insulated from each other by an inter-insulation layer609. The trench MOSFET600further comprises a shielded gate trench610only filled with the shielded electrode605which is connected to a source metal611of the trench MOSFET600via a trenched shielded electrode contact612filled with a contact metal plug.