SOLID-STATE IMAGING DEVICE

According to one embodiment, a solid-state imaging device is provided which comprises a photoelectric conversion element, a floating diffusion, a first capacitor, a first terminal, a second capacitor, a comparator, and a second terminal. The first capacitor is connected at one terminal to the floating diffusion. The first terminal is connected to the other terminal of the first capacitor, and a reference voltage of which the voltage value falls to a predetermined minimum and then rises to a predetermined maximum, is inputted to the first terminal. The second capacitor is connected at one terminal to the floating diffusion. The comparator has the other terminal of the second capacitor connected to its input and compares the potential on the floating diffusion and a threshold. The second terminal is connected to the output of the comparator, and the comparing result of the comparator is outputted via the second terminal.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2015-013748, filed on Jan. 27, 2015; the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to a solid-state imaging device.

BACKGROUND

There are conventionally known solid-state imaging devices wherein a pixel chip where a plurality of pixel cells that photoelectrically convert incident light into signal charge are arranged and a circuit chip that simultaneously reads pixel signals from all the pixel cells placed in the pixel chip are stacked.

Among those solid-state imaging devices, there is one which comprises an amplifying element to amplify the pixel signal in each pixel cell and a constant current source to supply current to each pixel cell to make the amplifying element operate as a source follower.

This solid-state imaging device needs to supply current from the constant current source to all the pixel cells when simultaneously driving all the pixel cells placed in the pixel chip and thus consumes large electric power.

DETAILED DESCRIPTION

According to the present embodiment, a solid-state imaging device is provided which comprises a photoelectric conversion element, a floating diffusion, a first capacitor, a first terminal, a second capacitor, a comparator, and a second terminal. The photoelectric conversion element converts incident light into signal charge. The floating diffusion holds the signal charge transferred from the photoelectric conversion element. The first capacitor is connected at one terminal to the floating diffusion. The first terminal is connected to the other terminal of the first capacitor, and a reference voltage of which the voltage value falls to a predetermined minimum and then rises to a predetermined maximum, is inputted to the first terminal. The second capacitor is connected at one terminal to the floating diffusion. The comparator has the other terminal of the second capacitor connected to its input and compares the potential on the floating diffusion and a threshold. The second terminal is connected to the output of the comparator, and the comparing result of the comparator is outputted via the second terminal.

The solid-state imaging device according to an embodiment will be described in detail below with reference to the accompanying drawings. The present invention is not limited to this embodiment.

FIG. 1is a schematic perspective view of a solid-state imaging device1according to the embodiment, andFIG. 2is a schematic cross-sectional view of the solid-state imaging device1according to the embodiment. As shown inFIG. 1, the solid-state imaging device1comprises a pixel chip10and a circuit chip11stacked one over the other.

The pixel chip10comprises a pixel array13wherein multiple pixel cells12corresponding to the pixels of a picked-up image are arranged in a two-dimensional array (matrix) along a horizontal direction (row direction) and a vertical direction (column direction), and so on. The circuit chip11comprises a logic circuit that reads a pixel signal of the picked-up image from each pixel cell12and that performs a variety of signal processing on the read pixel signals, and so on.

Further, as shown inFIG. 2, the solid-state imaging device1comprises connection units2that electrically connect the pixel chip10and the circuit chip11and an insulating adhesive member3that sticks the pixel chip10and the circuit chip11together. The connection unit2comprises an output terminal20provided on the side opposite to the light-incident side of the pixel chip10, an input terminal21provided on the side opposite the pixel chip10of the circuit chip11, and a bump22that electrically connects these terminals.

Each pixel cell12placed in the pixel chip10photoelectrically converts incident light to output a pixel signal corresponding to signal charge obtained by photoelectrical conversion to the circuit chip11via the connection unit2.

This solid-state imaging device1simultaneously drives all the pixel cells12placed in the pixel chip10to simultaneously output the pixel signals of the pixel cells12to the circuit chip11via the connection units2.

A solid-state imaging device having a usual pixel chip and circuit chip stacked comprises an amplifying element to amplify the pixel signal in each pixel cell placed in the pixel chip and a constant current source to supply current to each pixel cell to make the amplifying element operate as a source follower.

This solid-state imaging device supplies current from the constant current source to all the pixel cells when simultaneously driving all the pixel cells placed in the pixel chip and thus consumes large electric power.

Hence, as to the solid-state imaging device1according to the embodiment, by implementing tactics in the circuit configuration of each pixel cell12, power consumption when all the pixel cells12are simultaneously driven is reduced.

The circuit configuration and operation of the pixel cell12according to the embodiment that enables a reduction in power consumption will be described specifically with reference toFIGS. 3 and 4. Since each pixel cell12of the solid-state imaging device1has the same circuit configuration, one pixel cell12will be described here.

FIG. 3is an illustrative diagram showing an example circuit configuration of the pixel cell12according to the embodiment. As shown inFIG. 3, the pixel chip10comprises the pixel cell12, and the circuit chip11comprises an inverter A1, a switch SW1, and a second terminal T2. The dotted line inFIG. 3indicates the boundary between the pixel chip10and the circuit chip11, and the pixel chip10is shown to be on one side of the dotted line while the circuit chip11is on the other side of the dotted line.

As shown inFIG. 3, the pixel cell12comprises a photodiode PD, a transfer transistor TRS, and a reset transistor RST. Further, the pixel cell12comprises a floating diffusion FD, a first capacitor C1, and a second capacitor C2.

The photodiode PD is connected at the cathode to ground and at the anode to the source of the transfer transistor TRS. The transfer transistor TRS is connected at the drain to the floating diffusion FD. The reset transistor RST is connected at the source to the floating diffusion FD and at the drain to a power supply voltage line VDD.

The floating diffusion FD is connected to one terminal N1aof the first capacitor C1and one terminal N2aof the second capacitor C2. The other terminal Nib of the first capacitor C1is connected to a first terminal T1. A reference voltage VREF generated by a reference voltage generating circuit (not shown) is inputted to the first terminal T1. The reference voltage VREF is in the form of, e.g., a ramp wave whose voltage value increases or decreases over time.

The other terminal N2bof the second capacitor C2is connected to the input terminal N3aof the inverter A1. The switch SW1is connected in parallel with the inverter A1. The output terminal N3bof the inverter A1is connected to a second terminal T2. In this embodiment, the second capacitor C2, inverter A1, and switch SW1form a chopper comparator4. Further, in this embodiment, the inverter A1and switch SW1from among the constituents of the chopper comparator4are provided on the circuit chip11.

The transfer transistor TRS transfers signal charge photoelectrically converted into by the photodiode PD to the floating diffusion FD when a transfer signal READ is inputted to its transfer gate. The reset transistor RST resets the potential on the floating diffusion FD to the potential of the power supply voltage when a reset signal RESET is inputted to its gate.

When the reference voltage VREF inputted via the first terminal T1is applied to the first capacitor C1, the potential on the floating diffusion FD changes in tune with the reference voltage VREF. The chopper comparator4holds the potential on the floating diffusion FD reset by the reset transistor RST as a threshold and performs comparing operation based on this threshold and the changing potential on the floating diffusion FD. The chopper comparator4outputs a pixel signal VSIG that is the comparing result via the second terminal T2.

Next, the operation of the above pixel cell12will be described in detail according to the timing chart shown inFIG. 4.FIG. 4is a timing chart showing timings of the operation of the pixel cell12according to the embodiment. The solid-state imaging device1picks up an image according to a so-called global shutter method, by which all the pixels are exposed simultaneously, to store signal charge in the photodiodes PD by this exposure.

Here, assume that after at time t1the reset transistor RST is turned off, at time t2the switch SW1is turned off and that thereafter at time t5the transfer transistor TRS is turned on. Further assume that at time t8the reset transistor RST and the switch SW1are turned on. Note that the timing chart shown inFIG. 4is illustrative.

First, as shown inFIG. 4, when the reset signal RESET falls at time t1, the potential on the floating diffusion FD falls from the potential of the power supply voltage by an amount corresponding to reset noise. In this embodiment, the power supply voltage is, for example, 3.4 V.

Then when at time t2the switch SW1is turned off, the floating diffusion FD returns to the potential of the power supply voltage by zero offset operation. The chopper comparator4holds a potential that is the same as the potential of the power supply voltage as a reference potential R because of zero offset operation.

Then the potential on the floating diffusion FD changes in tune with the reference voltage VREF because the reference voltage VREF inputted via the first terminal T1is applied to the first capacitor C1. This reference voltage VREF is a voltage whose maximum and minimum are preset such that the changing potential on the floating diffusion FD intersects with the reference potential R.

Then as the reference voltage VREF falls to the minimum, the potential on the floating diffusion FD falls by an amount corresponding to the voltage of the minimum. Then when the reference voltage VREF starts rising at time t3, the potential on the floating diffusion FD rises in tune with it. Accordingly the chopper comparator4determines whether to continue or stop updating the count value at a clock (CLOCK) since time t3. Then the chopper comparator4performs comparison based on the changing potential on the floating diffusion FD held on the one terminal N2aof the second capacitor C2and the reference potential R held on the other terminal N2bof the second capacitor C2. Here, the reference voltage VREF rises from a state where the signal level is low to a high state during first period W1from time t3to time t4. That is, the reference voltage VREF takes the minimum voltage value at time t3in the first period W1and the maximum voltage value at time t4. In this embodiment, the count of clocks is performed by the reference voltage generating circuit (not shown), and the clock count value is held in a memory unit described later. That is, the chopper comparator4determines whether to continue or stop updating the count value in the memory unit.

Then the chopper comparator4repeatedly determines to make it continue updating the count value at a clock until the potential on the floating diffusion FD reaches the same potential as the reference potential R as shown inFIG. 4. In this example, at a count of five, the potential on the floating diffusion FD reaches the same potential as the reference potential R.

When the potential on the floating diffusion FD reaches the reference potential R, the chopper comparator4determines to stop it updating the count value at a clock. The count number in this first period W1is a criterion for determination whether signal charge is stored in the photodiodes PD. After reaching the reference potential R, the potential on the floating diffusion FD rises to the maximum at time t4in tune with the reference voltage VREF.

Then in the pixel cell12, when the transfer signal READ rises at time t5, the transfer signal READ is inputted to the transfer gate of the transfer transistor TRS. Then in the pixel cell12, if signal charge is stored in the photodiode PD, signal charge in the photodiode PD is transferred to the floating diffusion FD.

Thus, as shown inFIG. 4, the potential on the floating diffusion FD falls by an amount corresponding to the amount of signal charge stored in the photodiode PD and becomes stable. Then as the reference voltage VREF falls to the minimum again, the potential on the floating diffusion FD falls by an amount corresponding to the voltage of the minimum because the reference voltage VREF inputted via the first terminal T1is applied to the first capacitor C1.

As the reference voltage VREF starts rising at time t6, the potential on the floating diffusion FD rises in tune with it. Accordingly the chopper comparator4determines whether to continue or stop updating the count value at a clock since time t6. Then the chopper comparator4performs comparison based on the changing potential on the floating diffusion FD held on the one terminal N2aof the second capacitor C2and the reference potential R held on the other terminal N2bof the second capacitor C2. Here, the reference voltage VREF rises from a state where the signal level is low to a high state during second period W2from time t6to time t7. That is, the reference voltage VREF takes the minimum voltage value at time t6in the second period W2and the maximum voltage value at time t7.

Further, the gradient at which the reference voltage VREF rises is the same during the first period W1and second period W2. In the pixel cell12, the second period W2is set longer in time length than the first period W1so that the potential on the floating diffusion FD, which has fallen by an amount corresponding to the amount of signal charge, intersects with the reference potential R. Thus, the voltage value of the reference voltage VREF is greater at time t7than at time t4.

Then the chopper comparator4repeatedly determines to make it continue updating the count value at a clock until the potential on the floating diffusion FD reaches the same potential as the reference potential R as shown inFIG. 4. In this example, at a count of 19, the potential on the floating diffusion FD reaches the same potential as the reference potential R.

When the potential on the floating diffusion FD reaches the reference potential R, the chopper comparator4determines to stop it updating the count value at a clock. After reaching the reference potential R, the potential on the floating diffusion FD rises to the maximum at time t7in tune with the reference voltage VREF.

Then in the pixel cell12, when the reset signal RESET rises at time t8, the reset signal RESET is inputted to the gate of the reset transistor RST, so that the potential on the floating diffusion FD is reset to the potential of the power supply voltage. When the switch SW1is turned on at time t8simultaneously, the potential on the second capacitor C2is reset. Then signal charge stored in the photodiode PD by the next exposure is transferred according to the same procedure as above.

In contrast, in the pixel cell12, as shown inFIG. 4, if signal charge is not stored in the photodiode PD, when the transfer signal READ rises at time t5, the potential on the floating diffusion FD does not fall but stays stable in tune with the reference voltage VREF because the voltage value thereof is stable.

Then as the reference voltage VREF falls to the minimum, the potential on the floating diffusion FD falls by an amount corresponding to the voltage of the minimum. As the reference voltage VREF starts rising at time t6, the potential on the floating diffusion FD rises in tune with it. Accordingly the chopper comparator4determines whether to continue or stop updating the count value at a clock since time t6. Then the chopper comparator4repeatedly determines to make it continue updating the count value at a clock until the potential on the floating diffusion FD reaches the same potential as the reference potential R. In this example, at a count of five, the potential on the floating diffusion FD reaches the same potential as the reference potential R. This count number is the same as the count number taken in the first period W1. Thus, the solid-state imaging device1determines that signal charge was not stored in the photodiode PD on the ground that the count number taken in the second period W2coincides with the count number taken in the first period W1.

In the circuit chip11, the pixel signal VSIG of one bit per one count that is the comparing result of the chopper comparator4is sequentially outputted via the second terminal T2connected to the other terminal N3bof the inverter A1.

The pixel cell12according to the above embodiment comprises the photodiode PD that converts incident light into signal charge and the floating diffusion FD that holds signal charge transferred from the photodiode PD. The pixel cell12further comprises the first capacitor C1whose one terminal N1ais connected to the floating diffusion FD and the second capacitor C2whose one terminal N2ais connected to the floating diffusion FD. Further the pixel cell12comprises the first terminal T1connected to the other terminal N1bof the first capacitor C1and to which the reference voltage VREF is inputted. The second capacitor C2is a constituent of the chopper comparator4.

Thus, in this pixel cell12, the reference voltage VREF is applied to the first capacitor C1, and the potential on the floating diffusion FD changes in tune with the reference voltage VREF. Further, the pixel cell12has the chopper comparator4perform comparison based on the changing potential on the floating diffusion FD held on the one terminal N2aof the second capacitor C2and the reference potential R held on the other terminal N2bof the second capacitor C2.

That is, this pixel cell12does not amplify the potential on the floating diffusion FD by source follower operation to AD convert the amplified current but makes the potential on the floating diffusion FD attuned to the reference voltage VREF and compares that potential with the reference potential R, thereby performing AD conversion. Hence, the pixel cell12does not need a constant current source to read by a source follower, so that it can be driven with less power.

Thus, the power consumption of the solid-state imaging device1according to the above embodiment when all the pixel cell12arranged in the pixel chip10are driven simultaneously can be reduced. The power consumption of this solid-state imaging device1can be reduced also in the case where the pixel array13is divided into multiple areas and where multiple pixel cells12in each area are driven simultaneously.

Next, the operation of storing the clock count value into the memory unit will be described with reference toFIG. 5.FIG. 5is an illustrative diagram showing an example circuit configuration of a logic circuit provided on the circuit chip11according to the embodiment. The same reference numerals as inFIG. 3are used to denote constituents having the same functions as those shown inFIG. 3, with description thereof being omitted. The dotted line inFIG. 5indicates the boundary between the pixel chip10and the circuit chip11, and the pixel chip10is shown to be on one side of the dotted line while the circuit chip11is on the other side of the dotted line.

As shown inFIG. 5, the circuit chip11comprises the inverter A1and switch SW1that are constituents of the chopper comparator4, the second terminal T2, a chopper comparator4athat amplifies the pixel signal VSIG outputted via the second terminal T2, and a third terminal T3. The chopper comparator4ahas the same configuration as the chopper comparator4in this embodiment and comprises an inverter A2, a switch SW2, and a third capacitor C3.

Further the circuit chip11comprises the memory unit5connected to the third terminal T3. The memory unit5comprises a plurality of SRAMs (Static Random Access Memories)14, a signal line15, and a plurality of bus lines16. Although in this embodiment the SRAMs14are used in the memory unit5, not being limited to this, a DRAM (Dynamic Random Access Memory), FRAM (registered trademark) (Ferroelectric Random Access Memory), or the like can be used instead of the SRAM14.

The SRAM14is a line memory to hold for each bus line16. The signal line15connects the third terminal T3and the SRAMs14. The signal line15is a write enable signal line of the SRAMs14for controlling whether to continue or stop updating the count value in count operation. The bus lines16connect to the bit input terminals of each SRAM14. The count value of N bits (N is a natural number), which is updated per one count, is inputted onto the bus lines16in count operation, and the count value of N bits held in the SRAM14is outputted in read operation.

In the solid-state imaging device1, the count value of N bits at the time at which the potential on the floating diffusion FD reaches the reference potential R is stored into each memory unit5. In this embodiment, as shown inFIG. 5, the solid-state imaging device1comprises eight SRAMs14in each memory unit5, which store the count value of 8 bits. Specifically, if the clock count number at the time at which the potential on the floating diffusion FD reaches the reference potential R is 63, the solid-state imaging device1stores a count value of 00011111 into the memory unit5. If the clock count number at the time at which the potential on the floating diffusion FD reaches the reference potential R is 255, the solid-state imaging device1stores a count value of 11111111 into the memory unit5.

The solid-state imaging device1according to the above embodiment comprises a plurality of the memory units5on the circuit chip11respectively corresponding to the pixel cells12. Each memory unit5stores the count value of N bits at the time at which the potential on the floating diffusion FD reaches the reference potential R.

Thus, because the solid-state imaging device1need not secure a placement area for the memory unit5on the pixel chip10, the image pickup area on the pixel chip10can be expanded, so that more pixel cells12are arranged on the pixel chip10.

Although the solid-state imaging device1according to the above embodiment has the configuration where the chopper comparator4athat amplifies the pixel signal VSIG outputted from the inverter A1is provided between the second terminal T2and the third terminal T3, the invention is not limited to this configuration.

For example, in the solid-state imaging device1, the memory unit5may be connected to the second terminal T2so as to output the pixel signal VSIG directly from the inverter A1via the second terminal T2without using the chopper comparator4athat amplifies the pixel signal VSIG. Or in the solid-state imaging device1, an additional chopper comparator may be provided at the stage subsequent to the chopper comparator4ato further amplify the pixel signal VSIG to output via the third terminal T3.

Although the solid-state imaging device1according to the above embodiment has the configuration where the second capacitor C2, a constituent of the chopper comparator4, is provided on the pixel chip10, the invention is not limited to this configuration. For example, the solid-state imaging device1may be configured such that the second capacitor C2, a constituent of the chopper comparator4, is provided on the circuit chip11. In this case, the pixel cell12comprises the photodiode PD, transfer transistor TRS, reset transistor RST, floating diffusion FD, and first capacitor C1. As the first capacitor C1, second capacitor C2, and third capacitor C3, for example, MOS (Metal Oxide Semiconductor) capacitance elements or MIM (Metal Insulator Metal) capacitance elements are used.

Further, the solid-state imaging device1may be configured such that the connection unit2electrically connecting the pixel chip10and the circuit chip11functions as a fourth capacitor C4. This fourth capacitor C4is a constituent of the chopper comparator4. That is, the fourth capacitor C4corresponds to the second capacitor C2of the above chopper comparator4. In this case, an MIM capacitance element is used as the fourth capacitor C4.

Here, the configuration where the connection unit2functions as the fourth capacitor C4, an MIM capacitance element, will be described with reference toFIG. 6.FIG. 6is an illustrative diagram for explaining the configuration of the fourth capacitor C4according to the embodiment. The same reference numerals as inFIGS. 2 and 3are used to denote constituents having the same functions as those shown inFIGS. 2 and 3, with description thereof being omitted.

As shown inFIG. 6, the connection unit2comprises an insulating member23instead of the conductive bump22so as to function as the fourth capacitor C4, an MIM capacitance element. Thus, the connection unit2has a structure in which the insulating member23is sandwiched between the output terminal20and input terminal21made of metal, that is, an MIM structure. Hence, the connection unit2functions as an MIM capacitance element.

In the solid-state imaging device1according to the above embodiment, because the connection unit2connecting the pixel chip10and the circuit chip11functions as the fourth capacitor C4that is a constituent of the chopper comparator4, the size of the pixel chip10and the circuit chip11can be reduced.

Next, the specific structure of each pixel cell12placed on the pixel chip10will be described with reference toFIGS. 7A to 10. Because each pixel cell12has the same structure, one pixel cell12will be described here. The same reference numerals as inFIG. 3are used to denote constituents having the same functions as those shown inFIG. 3, with description thereof being omitted.

FIGS. 7A and 7Bare illustrative diagrams showing another configuration of the pixel cell12according to the embodiment. Specifically,FIG. 7Ais an illustrative diagram showing the circuit configuration of the pixel cell12where MOS capacitance elements are used according to the embodiment.FIG. 7Bis an illustrative diagram showing schematically the placement in the pixel cell12shown inFIG. 7Ain top plan view.

As shown inFIG. 7A, the pixel cell12comprises the first capacitor C1that is a MOS capacitance element and the second capacitor C2that is a MOS capacitance element. The pixel cell12is connected via the first terminal T1to a reference signal line6over which the reference voltage VREF is transmitted. InFIG. 7A, the connection relation between the photodiode PD, floating diffusion FD, transfer transistor TRS, reset transistor RST, first capacitor C1, and second capacitor C2is the same as the connection relation in the pixel cell12shown in FIG.

As shown inFIG. 7B, the pixel cell12comprises the photodiode PD (a photoelectric conversion element) and the floating diffusion FD that are electrically element-separated. The transfer gate TG of the transfer transistor TRS is placed over part of a semiconductor layer7between the photodiode PD and the floating diffusion FD. The gate RG of the reset transistor RST is placed over part of the semiconductor layer7next to the floating diffusion FD.

Further, the gate electrode G1of the first capacitor C1that is a MOS capacitance element and the gate electrode G2of the second capacitor C2that is a MOS capacitance element are placed over an area of the semiconductor layer7adjacent to the photodiode PD. The gate electrode G1is located between a source region80aand drain region80bformed in the semiconductor layer7. The gate electrode G2is located between a source region81aand drain region81bformed in the semiconductor layer7. Further, the reference signal line6is placed over an area of the semiconductor layer7adjacent to the photodiode PD and the first capacitor C1that are in a line.

The gate electrodes G1and G2are electrically connected by a metal line L1. The source region80aand the drain region80bare electrically connected by a metal line L2. The source region80aand the reference signal line6are electrically connected by a metal line L3. The source region81aand the drain region81bare electrically connected by a metal line L4. The floating diffusion FD and the metal line L1are electrically connected by a metal line L5.

As such, in the case of using MOS capacitance elements, the pixel cell12has the photodiode PD, floating diffusion FD, transfer gate TG, gate RG, and gate electrodes G1, G2placed in and over the semiconductor layer7.

In the solid-state imaging device1according to the above embodiment, because the first capacitor C1and second capacitor C2that the pixel cell12comprises are MOS capacitance elements, the capacitors can be easily mounted on the semiconductor layer7, so that the size of the pixel cell12can be reduced.

FIGS. 8A and 8Bare illustrative diagrams showing another configuration of the pixel cell12according to the embodiment. Specifically,FIG. 8Ais an illustrative diagram showing the circuit configuration of the pixel cell12where MIM capacitance elements are used according to the embodiment.FIG. 8Bis an illustrative diagram showing schematically the placement in the pixel cell12shown inFIG. 8Ain top plan view. The same reference numerals as inFIGS. 7A and 7Bare used to denote constituents having the same functions as those shown inFIGS. 7A and 7B, with description thereof being omitted.

As shown inFIG. 8A, the pixel cell12comprises the first capacitor C1that is an MIM capacitance element and the second capacitor C2that is an MIM capacitance element. The pixel cell12is connected via the first terminal T1to the reference signal line6over which the reference voltage VREF is transmitted. InFIG. 8A, the connection relation between the photodiode PD, floating diffusion FD, transfer transistor TRS, reset transistor RST, first capacitor C1, and second capacitor C2is the same as the connection relation in the pixel cell12shown inFIG. 3.

As shown inFIG. 8B, in the pixel cell12, one common lower-side electrode60is placed extending along a width direction of the pixel cell12over an area of the semiconductor layer7adjacent to the photodiode PD. The upper-side electrode61aof the first capacitor C1and the upper-side electrode61bof the second capacitor C2are placed over the common lower-side electrode60. Insulators (not shown) are placed between the upper-side electrodes61a,61band the common lower-side electrode60.

The upper-side electrode61aand the reference signal line6are electrically connected by a metal line L6. The floating diffusion FD and the common lower-side electrode60are electrically connected by a metal line L7.

As such, in the case of using MIM capacitance elements, the pixel cell12has the photodiode PD, floating diffusion FD, transfer gate TG, gate RG, common lower-side electrode60, and upper-side electrodes61a,61bplaced in and over the semiconductor layer7.

In the solid-state imaging device1according to the above embodiment, because the first capacitor C1and second capacitor C2that the pixel cell12comprises are MIM capacitance elements, the parasitic capacitance of the capacitors can be reduced, so that the operation speed can be improved.

FIGS. 9A and 9Bare illustrative diagrams showing another configuration of the pixel cell12according to the embodiment. Specifically,FIG. 9Ais an illustrative diagram showing the circuit configuration of the pixel cell12where a MOS capacitance element and an MIM capacitance element are used according to the embodiment.FIG. 9Bis an illustrative diagram showing schematically the placement in the pixel cell12shown inFIG. 9Ain top plan view. The same reference numerals as inFIGS. 7A, 7B, 8A, and 8Bare used to denote constituents having the same functions as those shown inFIGS. 7A, 7B, 8A, and 8B, with description thereof being omitted.

As shown inFIG. 9A, the pixel cell12comprises the first capacitor C1that is a MOS capacitance element and the second capacitor C2that is an MIM capacitance element. The pixel cell12is connected via the first terminal T1to the reference signal line6over which the reference voltage VREF is transmitted. InFIG. 9A, the connection relation between the photodiode PD, floating diffusion FD, transfer transistor TRS, reset transistor RST, first capacitor C1, and second capacitor C2is the same as the connection relation in the pixel cell12shown inFIG. 3.

As shown inFIG. 9B, in the pixel cell12, the gate electrode G1of the first capacitor C1that is a MOS capacitance element and a lower-side electrode60aare placed in a line along a width direction over an area of the semiconductor layer7adjacent to the photodiode PD. The gate electrode G1is located between the source region80aand the drain region80bformed in the semiconductor layer7. The upper-side electrode61bof the second capacitor C2, an MIM capacitance element, is placed over the lower-side electrode60a. An insulator (not shown) is placed between the upper-side electrode61band the lower-side electrode60a.

The gate electrode G1and the lower-side electrode60aare electrically connected by a metal line L8. The floating diffusion FD and the lower-side electrode60aare electrically connected by a metal line L9.

The placement in the semiconductor layer7of the pixel cell12schematically shown inFIGS. 9A and 9Bwill be described.FIG. 10is an illustrative diagram showing schematically example placement in the pixel cell12shown inFIGS. 9A and 9B. The same reference numerals as inFIGS. 9A and 9Bare used to denote constituents having the same functions as those shown inFIGS. 9A and 9B, with description thereof being omitted.

As shown inFIG. 10, the pixel cell12comprises the photodiode PD, the floating diffusion FD, the source region80a, the drain region80b, a channel forming region82, and a dark current suppressing region72in the semiconductor layer7.

The photodiode PD is formed by a PN junction between a P-type Si layer70and an N-type Si region71formed at a predetermined depth in the P-type Si layer70. The floating diffusion FD, the source region80a, and the drain region80bare formed by ion implanting an N-type impurity of a high concentration into the surface layer of the P-type Si layer70. The channel forming region82is formed by ion implanting an N-type impurity into part of the P-type Si layer70between the source region80aand the drain region80b. The dark current suppressing region72is formed by ion implanting a P-type impurity of a high concentration into part of the surface layer of the P-type Si layer70above the photodiode PD.

The transfer gate TG of the transfer transistor TRS located between the photodiode PD and the floating diffusion FD is formed over the surface of the semiconductor layer7. Further, the gate electrode G1of the first capacitor C1located over the channel forming region82, and the upper-side electrode61bof the second capacitor C2located above the gate electrode G1are formed over the surface of the semiconductor layer7.

As such, in the case of using a MOS capacitance element and an MIM capacitance element, the pixel cell12has the photodiode PD, floating diffusion FD, transfer gate TG, reset gate RG, gate electrode G1, lower-side electrode60a, and upper-side electrode61bplaced in and over the semiconductor layer7.

In the solid-state imaging device1according to the above embodiment, because the first capacitor C1and second capacitor C2that the pixel cell12comprises are a MOS capacitance element and an MIM capacitance element, a reduction in the size of the pixel cell12and an improvement in the operation speed can be achieved simultaneously.