Light emitting element device including light emitting thyristor and optical print head including the light emitting element device

A light emitting element device includes: a light emitting thyristor having a layered structure including a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type different from the first conductivity type, a third semiconductor layer of the first conductivity type, and a fourth semiconductor layer of the second conductivity type that are layered in this order; and a gate electrode for supplying gate current to the light emitting thyristor. The light emitting thyristor includes an etching stop layer disposed on a surface of the third semiconductor layer or included in the third semiconductor layer, the etching stop layer being a semiconductor layer having an etching rate lower than an etching rate of a semiconductor layer adjacent to the etching stop layer.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a light emitting element device including a light emitting thyristor, and an optical print head including light emitting element devices.

2. Description of the Related Art

Optical print heads including a light emitting thyristor array (or light emitting element array) including multiple light emitting thyristors (or light emitting elements) are proposed as optical print heads (or exposure devices) of electrophotographic image forming apparatuses (see, for example, Japanese Patent Application Publication No. 2015-109417, in particular, FIG. 4 and paragraphs 0036 to 0060). Japanese Patent Application Publication No. 2015-109417 discloses a light emitting thyristor having an npnp layered structure in which a p-type anode layer (or first semiconductor layer), an n-type gate layer (or second semiconductor layer), a p-type gate layer (or third semiconductor layer), and an n-type cathode layer (or fourth semiconductor layer) are layered, a gate electrode being formed on the p-type gate layer (or third semiconductor layer). The n-type gate layer (or second semiconductor layer) has a band gap smaller than that of each of the p-type anode layer (or first semiconductor layer) and n-type cathode layer (or fourth semiconductor layer), and the p-type gate layer (or third semiconductor layer) has a band gap smaller than that of the n-type gate layer (or second semiconductor layer), so that the p-type gate layer (or third semiconductor layer) is a light emitting layer.

In the above layered structure, the surface on which the gate electrode is disposed is formed by wet etching the p-type gate layer. Thus, the p-type gate layer needs to have a sufficiently large thickness (or a thickness including an etching margin) in consideration of variation in etching rate of the wet etching. However, increase in thickness of the p-type gate layer, which is a light emitting layer, increases light absorption by the p-type gate layer itself, thus reducing light extraction efficiency. Further, increase in thickness of the p-type gate layer, which is a base layer of the upper npn structure (or npn transistor) of the light emitting thyristor, reduces the current gain of the npn transistor, thus deteriorating the switching characteristics of the light emitting thyristor.

SUMMARY OF THE INVENTION

An aspect of the present invention is intended to provide a light emitting element device having high light extraction efficiency and good switching characteristics, and an optical print head including such a light emitting element device.

According to an aspect of the present invention, there is provided a light emitting element device including: a light emitting thyristor having a layered structure including a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type different from the first conductivity type, a third semiconductor layer of the first conductivity type, and a fourth semiconductor layer of the second conductivity type that are layered in this order; and a gate electrode for supplying gate current to the light emitting thyristor, wherein the light emitting thyristor includes an etching stop layer disposed on a surface of the third semiconductor layer or included in the third semiconductor layer, the etching stop layer being a semiconductor layer having an etching rate lower than an etching rate of a semiconductor layer adjacent to the etching stop layer.

According to another aspect of the present invention, there is provided an optical print head including: a light emitting element array including a plurality of light emitting element portions; and a lens array that focuses light emitted from the light emitting element array, wherein each of the plurality of light emitting element portions is the above light emitting element device.

DETAILED DESCRIPTION OF THE INVENTION

Embodiments of the present invention will now be described with reference to the attached drawings.

<1> First Embodiment

<1-1> Light Emitting Element Array

FIG. 1is a plan view schematically illustrating a configuration of a light emitting element array (or light emitting thyristor array)100including multiple light emitting element devices (or light emitting element portions)1according to a first embodiment of the present invention. The light emitting element array100is mounted on an optical print head as an exposure device in an electrophotographic image forming apparatus. As illustrated inFIG. 1, the light emitting element array100includes, for example, a chip-on-board (COB) substrate110, a semiconductor substrate120as a substrate mounted on the COB substrate110, and multiple light emitting thyristors16as multiple light emitting elements mounted on the semiconductor substrate120. The semiconductor substrate120and the multiple light emitting thyristors16as the multiple light emitting elements form a light emitting element array chip (or light emitting thyristor array chip). A light emitting thyristor array head as the optical print head will be described in a ninth embodiment described later.

The semiconductor substrate120is, for example, a silicon (Si) substrate, and includes a drive circuit121that is an integrated circuit that drives the light emitting thyristors16. The drive circuit121may be provided on the semiconductor substrate120or COB substrate110as an integrated circuit chip.

The light emitting element devices1are formed by bonding or attaching light emitting thyristor portions (which may also be referred to as light emitting element devices)10including the light emitting thyristors16onto the semiconductor substrate120. The light emitting thyristor portions10including the light emitting thyristors16are each formed on a production substrate (e.g., a production substrate150inFIG. 3Adescribed later), for example. The light emitting thyristor portions10(e.g., epitaxial films as thin films having a semiconductor layered structure formed by epitaxial growth) are each separated or peeled off from the production substrate and then bonded onto a major surface of the semiconductor substrate120.

The light emitting element array100also includes wirings17that electrically connect the light emitting element devices1to the drive circuit121. The wirings17are wiring layers or wires formed of conductive material. When the wirings17are formed by forming wiring layers on surfaces of the light emitting element devices1, before the wiring layers are formed, insulation layers are formed on regions of the light emitting thyristor portions10outside electrodes of the light emitting thyristor portions10and regions of the semiconductor substrate120outside electrodes on the semiconductor substrate120. The configuration ofFIG. 1is merely an example, and the configuration of the light emitting element array is not limited to that illustrated inFIG. 1.

<1-2> Light Emitting Element Device

FIG. 2is a sectional view schematically illustrating a configuration of one of the light emitting element devices1according to the first embodiment (or a cross-section taken along line II-II inFIG. 1). As illustrated inFIGS. 1 and 2, the light emitting element device1according to the first embodiment includes a part of the semiconductor substrate120as a substrate, and the light emitting thyristor portion10that is provided on the part of the semiconductor substrate120and driven by the drive circuit121.

As illustrated inFIG. 2, the light emitting thyristor16has a layered structure (or layered portion) including a p-type anode layer11as a first semiconductor layer of a first conductivity type, an n-type gate layer12as a second semiconductor layer of a second conductivity type different from the first conductivity type, a p-type gate layer13as a third semiconductor layer of the first conductivity type, an etching stop layer15, and an n-type cathode layer14as a fourth semiconductor layer of the second conductivity type that are layered in this order. The etching stop layer15is disposed on a surface of the p-type gate layer13as the third semiconductor layer on the n-type cathode layer14side. The etching stop layer15is a semiconductor layer having an etching rate lower than that of the semiconductor layer (inFIG. 2, the n-type cathode layer14) adjacent to and above the etching stop layer15. In this example, the etching stop layer15has an etching rate lower than that of each of the semiconductor layers (inFIG. 2, the p-type gate layer13and n-type cathode layer14) adjacent to the etching stop layer15.

In the first embodiment, the p-type anode layer11is a p-type aluminum gallium arsenide (AlGaAs) layer; the n-type gate layer12is an n-type AlGaAs layer; the p-type gate layer13is a p-type AlGaAs layer; the n-type cathode layer14is an n-type AlGaAs layer. In these layers, carbon (C) or zinc (Zn) is used as the p-type impurity or dopant, and silicon (Si) is used as the n-type impurity or dopant. The composition ratio of Al in the p-type anode layer (or p-type AlGaAs layer)11and the composition ratio of Al in the n-type cathode layer (or n-type AlGaAs layer)14are higher than the composition ratio of Al in the n-type gate layer (or n-type AlGaAs layer)12. Also, the composition ratio of Al in the n-type gate layer (or n-type AlGaAs layer)12is higher than the composition ratio of Al in the p-type gate layer (or p-type AlGaAs layer)13. In these layers, the higher the composition ratio of Al, the greater the band gap.

The etching stop layer15is, for example, a p-type indium gallium phosphide (InGaP) layer. The etching stop layer15has a thickness less than that of each of the semiconductor layers (inFIG. 2, the p-type gate layer13and n-type cathode layer14) adjacent to the etching stop layer15. The thickness of the etching stop layer15is preferably in the range of about 10 to 50 nm.

As illustrated inFIG. 2, the light emitting element device1includes an anode electrode91disposed on the p-type anode layer11, a cathode electrode92disposed on the n-type cathode layer14, and a gate electrode93disposed on the etching stop layer15and electrically connected to the p-type gate layer13via the etching stop layer15.

In the light emitting element device1according to the first embodiment, the drive circuit121(FIG. 1) supplies a signal (or gate current) to the gate electrode93of the light emitting thyristor16to establish an on state between the p-type anode layer11and the n-type cathode layer14, and supplies an anode signal (or cathode signal) to the anode electrode91(or cathode electrode92), thereby causing current to flow between the p-type anode layer11and the n-type cathode layer14to cause the p-type gate layer13of the light emitting thyristor16to emit light. The drive circuit121also makes the anode signal (or cathode signal) less than or equal to a predetermined level to establish an off state between the p-type anode layer11and the n-type cathode layer14.

<1-3> Manufacturing Process of Light Emitting Element Device

FIGS. 3A to 3Fare sectional views schematically illustrating a manufacturing process of the light emitting element device1illustrated inFIG. 2. The light emitting thyristor portion10of the light emitting element device1is produced on the production substrate150different from the semiconductor substrate120illustrated inFIG. 2.

Next, as illustrated inFIG. 3B, the n-type cathode layer14is partially etched by wet etching using, for example, a mixture of phosphoric acid, hydrogen peroxide solution, and water, or other etchants. The etching rate of InGaP by the mixture is about one hundredth of the etching rate of AlGaAs by the mixture. Thus, the wet etching inFIG. 3Bstops at the etching stop layer15formed of InGaP. The upper surface of the etching stop layer15formed of InGaP includes a region on which the gate electrode93(FIG. 3D) is to be formed.

Next, as illustrated inFIG. 3C, the etching stop layer15is partially removed by using, for example, hydrochloric acid so that the p-type gate layer13is partially exposed; then, by wet etching using a mixture that is the same as the above-described mixture, the p-type gate layer13and n-type gate layer12are partially removed, and a part of the p-type anode layer11is etched, so that a region on which the anode electrode91(FIG. 3D) is to be formed is formed.

Next, as illustrated inFIG. 3D, the anode electrode91is formed on the p-type anode layer11, the cathode electrode92is formed on the n-type cathode layer14, and the gate electrode93is formed on the etching stop layer15, so that the light emitting thyristor portion10including the light emitting thyristor16is formed. The light emitting thyristor16, which is, for example, an epitaxial film, can be separated from the production substrate150by etching the separation layer151and can be attached or bonded onto another substrate.

Next, as illustrated inFIG. 3E, the light emitting thyristor portion10is separated from the production substrate150by, for example, removing (or dissolving) the separation layer151while holding (e.g., by attraction or suction) the light emitting thyristor portion10by a holding device.

Next, as illustrated inFIG. 3F, the separated light emitting thyristor portion10is transferred onto the semiconductor substrate120and bonded to a predetermined position on the semiconductor substrate120. The above process is repeatedly performed, so that the multiple light emitting thyristor portions10are formed on the semiconductor substrate120. After that, for each of the multiple light emitting thyristor portions10, the anode electrode91, cathode electrode92, and gate electrode93are electrically connected to electrode portions of the drive circuit121by the wirings17or the like. As above, the light emitting element array chip (or light emitting thyristor array chip) including the light emitting element devices (or light emitting element portions)1illustrated inFIGS. 1 and 2is formed.

FIG. 4is a sectional view illustrating an etching process of a comparative light emitting thyristor having no etching stop layer. The comparative light emitting thyristor includes a p-type anode layer11c, an n-type gate layer12c, a p-type gate layer13c, and an n-type cathode layer14c. The n-type cathode layer14candp-type gate layer13care etched as indicated by arrow A. As illustrated inFIG. 4, etching in the etching process of the comparative light emitting thyristor (or semiconductor layered structure) having no etching stop layer stops at a position in the p-type gate layer13c. Thus, in the comparative light emitting thyristor having no etching stop layer, the p-type gate layer13cneeds to have a large thickness Tp including an etching margin M.

On the other hand, in the first embodiment, the etching in the etching process illustrated inFIG. 3Bstops at the etching stop layer15above the p-type gate layer13. Thus, the thickness T13(FIG. 2) of the p-type gate layer13need not include an etching margin, and can be minimized. As such, it is possible to reduce the thickness T13(FIG. 2) of the p-type gate layer13, thereby improving the light extraction efficiency from the light emitting element device1and the switching characteristics of the light emitting element device1.

Further, in the first embodiment, the gate electrode93is in contact with the p-type InGaP layer (or etching stop layer15) containing no Al. Thus, surface oxidation of the gate electrode93is less likely to occur. This can reduce the contact resistance as compared with a case where the gate electrode93is disposed on an AlGaAs layer.

<2> Second Embodiment

<2-1> Light Emitting Element Device

FIG. 5is a sectional view schematically illustrating a configuration of a light emitting element device2according to a second embodiment of the present invention. InFIG. 5, elements that are the same as or correspond to those illustrated inFIG. 2are given the same reference characters. The light emitting element device2according to the second embodiment differs from the light emitting element device1according to the first embodiment in that an etching stop layer25is an n-type InGaP layer instead of a p-type InGaP layer, and the gate electrode93is formed on the p-type gate layer13. Except for these differences, the light emitting element device2according to the second embodiment is the same as the light emitting element device1according to the first embodiment.

The light emitting element device2includes a light emitting thyristor portion (which may also be referred to as a light emitting element device)20including a light emitting thyristor26, and a part of the semiconductor substrate120on which the light emitting thyristor portion20is provided.

<2-2> Manufacturing Process of Light Emitting Element Device

FIGS. 6A to 6Fare sectional views schematically illustrating a manufacturing process of the light emitting element device2illustrated inFIG. 5. InFIGS. 6A to 6F, elements that are the same as or correspond to those illustrated inFIGS. 3A to 3Fare given the same reference characters. The light emitting thyristor portion20of the light emitting element device2is produced on the production substrate150different from the semiconductor substrate120illustrated inFIG. 5.

First, as illustrated inFIG. 6A, a layered structure consisting of the p-type anode layer (or p-type AlGaAs layer)11, n-type gate layer (or n-type AlGaAs layer)12, p-type gate layer (or p-type AlGaAs layer)13, etching stop layer (or n-type InGaP layer)25, and n-type cathode layer (or n-type AlGaAs layer)14is formed on the p-type AlAs layer (or separation layer)151provided on the production substrate150. The etching stop layer25is a semiconductor layer having an etching rate lower than that of the semiconductor layer (inFIG. 5, the n-type cathode layer14) adjacent to and above the etching stop layer25. In this example, the etching stop layer25has an etching rate lower than that of each of the semiconductor layers (inFIG. 5, the p-type gate layer13and n-type cathode layer14) adjacent to the etching stop layer25.

Next, as illustrated inFIG. 6B, the n-type cathode layer14is partially etched by wet etching using, for example, a mixture of phosphoric acid, hydrogen peroxide solution, and water, or other etchants. This etching stops at the etching stop layer25formed of InGaP. Then, as illustrated inFIG. 6B, the etching stop layer25is partially removed by using, for example, hydrochloric acid so that the p-type gate layer13is partially exposed. The exposed region of the upper surface of the p-type gate layer13includes a region on which the gate electrode93(FIG. 6D) is to be formed.

Next, as illustrated inFIG. 6C, by wet etching using a mixture that is the same as the above-described mixture, the p-type gate layer13and n-type gate layer12are partially removed, and a part of the p-type anode layer11is etched, so that a region on which the anode electrode91is to be formed is formed.

Next, as illustrated inFIG. 6D, the anode electrode91is formed on the p-type anode layer11, the cathode electrode92is formed on the n-type cathode layer14, and the gate electrode93is formed on the p-type gate layer13, so that the light emitting thyristor portion20including the light emitting thyristor26is formed. The light emitting thyristor26, which is, for example, an epitaxial film, can be separated from the production substrate150by etching the separation layer151and can be attached or bonded onto another substrate.

The subsequent processes illustrated inFIGS. 6E and 6Fare the same as those illustrated inFIGS. 3E and 3F.

As described above, in the light emitting element device2according to the second embodiment, the etching in the etching process illustrated inFIG. 6Bstops at the etching stop layer25above the p-type gate layer13. Thus, the thickness of the p-type gate layer13can be minimized. As such, it is possible to reduce the thickness of the p-type gate layer13, thereby improving the light extraction efficiency from the light emitting element device2and the switching characteristics of the light emitting element device2.

Further, since the etching stop layer25is an n-type InGaP layer containing no Al, the etching stop layer25is less likely to be affected by residual oxygen in the p-type gate layer13. Further, since the etching stop layer25is an n-type InGaP layer containing no Al, it is possible to reduce effects of surface recombination or a donor trap, such as a DX center, thereby improving the electrical characteristics of the light emitting element device2.

<3-1> Light Emitting Element Device

FIG. 7is a sectional view schematically illustrating a configuration of a light emitting element device3according to a third embodiment of the present invention. InFIG. 7, elements that are the same as or correspond to those illustrated inFIGS. 2 and 5are given the same reference characters. The light emitting element device3according to the third embodiment differs from the light emitting element device2according to the second embodiment in that an etching stop layer35has a layered structure including a p-type InGaP layer351and an n-type InGaP layer352. The etching stop layer35is a semiconductor layer having an etching rate lower than that of the semiconductor layer (inFIG. 7, the n-type cathode layer14) adjacent to and above the etching stop layer35. In this example, the etching stop layer35has an etching rate lower than that of each of the semiconductor layers (inFIG. 7, the p-type gate layer13and n-type cathode layer14) adjacent to the etching stop layer35. Except for this difference, the light emitting element device3according to the third embodiment is the same as the light emitting element device2according to the second embodiment.

<3-2> Manufacturing Process of Light Emitting Element Device

A manufacturing process of the light emitting element device3is the same as the manufacturing process of the light emitting element device2illustrated inFIGS. 6A to 6F, except that the layered structure including the p-type InGaP layer351and an n-type InGaP layer352is formed as the etching stop layer35.

In the light emitting element device3according to the third embodiment, as in the second embodiment, the thickness of the p-type gate layer13can be minimized. This can improve the light extraction efficiency from the light emitting element device3and the switching characteristics of the light emitting element device3.

Further, in the light emitting element device3according to the third embodiment, in addition to the advantages of the light emitting element device2according to the second embodiment, the following advantage can be obtained. The interface between the cathode layer and the gate layer is formed by a homojunction of InGaP. This can reduce effects of an energy barrier due to band gap discontinuity.

The etching stop layer15in the first embodiment may also be an etching stop layer having a layered structure including a p-type InGaP layer and an n-type InGaP layer.

<4-1> Light Emitting Element Device

FIG. 8is a sectional view schematically illustrating a configuration of a light emitting element device4according to a fourth embodiment of the present invention. InFIG. 8, elements that are the same as or correspond to those illustrated inFIGS. 2, 5, and 7are given the same reference characters. The light emitting element device4according to the fourth embodiment differs from the light emitting element device2according to the second embodiment in that an etching stop layer45is formed on a surface of the p-type gate layer13on the n-type gate layer12side (between the p-type gate layer13and the n-type gate layer12), and the gate electrode93is formed on a surface of the n-type gate layer12. Except for these differences, the light emitting element device4according to the fourth embodiment is the same as the light emitting element device2according to the second embodiment.

The light emitting element device4includes a light emitting thyristor portion (which may also be referred to as a light emitting element device)40including a light emitting thyristor46, and a part of the semiconductor substrate120on which the light emitting thyristor portion40is provided.

<4-2> Manufacturing Process of Light Emitting Element Device

FIGS. 9A to 9Fare sectional views schematically illustrating a manufacturing process of the light emitting element device4illustrated inFIG. 8. InFIGS. 9A to 9F, elements that are the same as or correspond to those illustrated inFIGS. 6A to 6Fare given the same reference characters. The light emitting thyristor portion40of the light emitting element device4is produced on the production substrate150different from the semiconductor substrate120illustrated inFIG. 8.

Next, as illustrated inFIG. 9B, the n-type cathode layer14and p-type gate layer13are partially etched by wet etching using, for example, a mixture of phosphoric acid, hydrogen peroxide solution, and water, or other etchants. This etching stops at the etching stop layer45formed of InGaP. Then, as illustrated inFIG. 9B, the etching stop layer45is partially removed by using, for example, hydrochloric acid so that the n-type gate layer12is partially exposed. The exposed region of the upper surface of the n-type gate layer12includes a region on which the gate electrode93(FIG. 9D) is to be formed.

Next, as illustrated inFIG. 9C, by wet etching using a mixture that is the same as the above-described mixture, the n-type gate layer12is partially removed, and a part of the p-type anode layer11is etched, so that a region on which the anode electrode91is to be formed is formed.

Next, as illustrated inFIG. 9D, the anode electrode91is formed on the p-type anode layer11, the cathode electrode92is formed on the n-type cathode layer14, and the gate electrode93is formed on the n-type gate layer12, so that the light emitting thyristor portion40including the light emitting thyristor46is formed. The light emitting thyristor46, which is, for example, an epitaxial film, can be separated from the production substrate150by etching the separation layer151and can be attached or bonded onto another substrate.

The subsequent processes illustrated inFIGS. 9E and 9Fare the same as those illustrated inFIGS. 3E and 3F, andFIGS. 6E and 6F.

As described above, in the light emitting element device4according to the fourth embodiment, the etching stop layer45is formed between the p-type gate layer13and the n-type gate layer12, and the gate electrode93is formed on the n-type gate layer12, as illustrated inFIG. 8. Thus, the etching in the etching process stops at the etching stop layer45above the n-type gate layer12. Thus, the thickness of the p-type gate layer13can be minimized. As such, it is possible to reduce the thickness of the p-type gate layer13, thereby improving the light extraction efficiency from the light emitting element device4and the switching characteristics of the light emitting element device4.

In the light emitting element device4according to the fourth embodiment, the etching stop layer (or n-type InGaP layer)45is formed between the p-type gate layer13and the n-type gate layer12. This forms a heterojunction having a barrier at the interface, preventing carrier transport. However, when current flows through the light emitting element device4, the pn junction between the p-type gate layer13and the n-type gate layer12is a depletion layer region, and thus the barrier at the interface does not affect characteristics of the light emitting element device4. Thus, the light emitting element device4according to the fourth embodiment can have improved switching characteristics.

The etching stop layer45in the fourth embodiment may be an etching stop layer having a layered structure including an n-type InGaP layer and a p-type InGaP layer.

<5-1> Light Emitting Element Device

FIG. 10is a sectional view schematically illustrating a configuration of a light emitting element device5according to a fifth embodiment of the present invention. InFIG. 10, elements that are the same as or correspond to those illustrated inFIGS. 2 and 5are given the same reference characters. The light emitting element device5according to the fifth embodiment differs from the light emitting element device2according to the second embodiment in that a third semiconductor layer53includes a first layer531, a second layer532adjacent to a surface of the first layer531on the fourth semiconductor layer14side, and a third layer533adjacent to a surface of the second layer532on the fourth semiconductor layer14side, and the second layer532is an etching stop layer. For example, the first layer531is a p-type AlGaAs layer, the second layer532is a p-type InGaP layer, and the third layer533is a p-type AlGaAs layer. Except for this difference, the light emitting element device5according to the fifth embodiment is the same as the light emitting element device2according to the second embodiment.

The light emitting element device5includes a light emitting thyristor portion (which may also be referred to as a light emitting element device)50including a light emitting thyristor56, and a part of the semiconductor substrate120on which the light emitting thyristor portion50is provided.

<5-2> Manufacturing Process of Light Emitting Element Device

FIGS. 11A to 11Fare sectional views schematically illustrating a manufacturing process of the light emitting element device5illustrated inFIG. 10. InFIGS. 11A to 11F, elements that are the same as or correspond to those illustrated inFIGS. 6A to 6Fare given the same reference characters. The light emitting thyristor portion50of the light emitting element device5is produced on the production substrate150different from the semiconductor substrate120illustrated inFIG. 10.

First, as illustrated inFIG. 11A, a layered structure consisting of the p-type anode layer (or p-type AlGaAs layer)11, the n-type gate layer (or n-type AlGaAs layer)12, the first layer (or p-type AlGaAs layer)531of the p-type gate layer53, the second layer (or p-type InGaP layer)532, which is an etching stop layer, the third layer (or p-type AlGaAs layer)533of the p-type gate layer53, and the n-type cathode layer (or n-type AlGaAs layer)14is formed on the p-type AlAs layer (or separation layer)151provided on the production substrate150. The second layer532, which is an etching stop layer, is a semiconductor layer having an etching rate lower than that of the semiconductor layer (inFIG. 10, the third layer533) adjacent to and above the second layer532. In this example, the second layer532has an etching rate lower than that of each of the semiconductor layers (inFIG. 10, the first layer531and third layer533of the p-type gate layer53) adjacent to the second layer532.

Next, as illustrated inFIG. 11B, the n-type cathode layer14and third layer533are partially etched by wet etching using, for example, a mixture of phosphoric acid, hydrogen peroxide solution, and water, or other etchants. This etching stops at the second layer532, which is an etching stop layer, formed of InGaP. Then, as illustrated inFIG. 11B, the second layer532, which is an etching stop layer, is partially removed by using, for example, hydrochloric acid so that the first layer531of the p-type gate layer53is partially exposed. The exposed region of the upper surface of the first layer531of the p-type gate layer53is a region on which the gate electrode93(FIG. 11D) is to be formed.

Next, as illustrated inFIG. 11C, by wet etching using a mixture that is the same as the above-described mixture, the first layer531of the p-type gate layer53and n-type gate layer12are partially removed, and a part of the p-type anode layer11is etched, so that a region on which the anode electrode91is to be formed is formed.

Next, as illustrated inFIG. 11D, the anode electrode91is formed on the p-type anode layer11, the cathode electrode92is formed on the n-type cathode layer14, and the gate electrode93is formed on the first layer531of the p-type gate layer53, so that the light emitting thyristor portion50including the light emitting thyristor56is formed. The light emitting thyristor56, which is, for example, an epitaxial film, can be separated from the production substrate150by etching the separation layer151and can be attached or bonded onto another substrate.

The subsequent processes illustrated inFIGS. 11E and 11Fare the same as those illustrated inFIGS. 3E and 3F.

As described above, in the light emitting element device5according to the fifth embodiment, the etching in the etching process illustrated inFIG. 11Bstops at the second layer (or etching stop layer)532in the p-type gate layer53. Thus, the thickness of the p-type gate layer53can be minimized. As such, it is possible to reduce the thickness of the p-type gate layer53, thereby improving the light extraction efficiency from the light emitting element device5and the switching characteristics of the light emitting element device5.

Further, in the light emitting element device5according to the fifth embodiment, the second layer532, which is an etching stop layer, is a semiconductor layer formed in the p-type gate layer53and having the same conductivity type as the first layer531and third layer533. Thus, it is possible to reduce effects of energy barrier due to a pn junction, thereby improving the switching characteristics.

<6-1> Light Emitting Element Device

FIG. 12is a sectional view schematically illustrating a configuration of a light emitting element device6according to a sixth embodiment of the present invention. InFIG. 12, elements that are the same as or correspond to those illustrated inFIG. 10(or the fifth embodiment) are given the same reference characters. The light emitting element device6according to the sixth embodiment differs from the light emitting element device5according to the fifth embodiment in that it includes, in addition to the etching stop layer (also referred to as the first etching stop layer)532, another etching stop layer (also referred to as the second etching stop layer), which is a second layer612described later, in a p-type anode layer61. Except for this difference, the light emitting element device6according to the sixth embodiment is the same as the light emitting element device5according to the fifth embodiment.

The light emitting element device6includes a light emitting thyristor portion (which may also be referred to as a light emitting element device)60including a light emitting thyristor66, and a part of the semiconductor substrate120on which the light emitting thyristor portion60is provided.

<6-2> Manufacturing Process of Light Emitting Element Device

FIGS. 13A to 13Fare sectional views schematically illustrating a manufacturing process of the light emitting element device6illustrated inFIG. 12. InFIGS. 13A to 13F, elements that are the same as or correspond to those illustrated inFIGS. 11A to 11Fare given the same reference characters. The light emitting thyristor portion60of the light emitting element device6is produced on the production substrate150different from the semiconductor substrate120illustrated inFIG. 12.

First, as illustrated inFIG. 13A, a layered structure consisting of a first layer (or p-type AlGaAs layer)611of the p-type anode layer61, the second layer (or p-type InGaP layer)612, which is the second etching stop layer, of the p-type anode layer61, a third layer (or p-type AlGaAs layer)613of the p-type anode layer61, the n-type gate layer (or n-type AlGaAs layer)12, the first layer (or p-type AlGaAs layer)531of the p-type gate layer53, the second layer (or p-type InGaP layer)532, which is the first etching stop layer, the third layer (or p-type AlGaAs layer)533of the p-type gate layer53, and the n-type cathode layer (or n-type AlGaAs layer)14is formed on the p-type AlAs layer (or separation layer)151provided on the production substrate150. The second layer532, which is the first etching stop layer, is a semiconductor layer having an etching rate lower than that of the semiconductor layer (inFIG. 12, the third layer533) adjacent to and above the second layer532. In this example, the second layer532has an etching rate lower than that of each of the semiconductor layers (inFIG. 12, the first layer531and third layer533of the p-type gate layer53) adjacent to the second layer532. The second layer612, which is the second etching stop layer, is a semiconductor layer having an etching rate lower than that of the semiconductor layer (inFIG. 12, the third layer613) adjacent to and above the second layer612. In this example, the second layer612has an etching rate lower than that of each of the semiconductor layers (inFIG. 12, the first layer611and third layer613of the p-type anode layer61) adjacent to the second layer612.

Next, as illustrated inFIG. 13B, the n-type cathode layer14and third layer533are partially etched by wet etching using, for example, a mixture of phosphoric acid, hydrogen peroxide solution, and water, or other etchants. This etching stops at the second layer532, which is the first etching stop layer, formed of InGaP. Then, as illustrated inFIG. 13B, the second layer532is partially removed by using, for example, hydrochloric acid so that the first layer531of the p-type gate layer53is partially exposed. The exposed region of the upper surface of the first layer531of the p-type gate layer53includes a region on which the gate electrode93(FIG. 13D) is to be formed.

Next, as illustrated inFIG. 13C, by wet etching using a mixture that is the same as the above-described mixture, the first layer531of the p-type gate layer53, the n-type gate layer12, and the third layer613of the p-type anode layer61are partially etched. This etching stops at the second layer612, which is the second etching stop layer, formed of InGaP. Then, as illustrated inFIG. 13C, the second layer612is partially removed by using, for example, hydrochloric acid so that the first layer611of the p-type anode layer61is partially exposed. The exposed region of the upper surface of the first layer611of the p-type anode layer61includes a region on which the anode electrode91(FIG. 13D) is to be formed.

Next, as illustrated inFIG. 13D, the anode electrode91is formed on the first layer611of the p-type anode layer61, the cathode electrode92is formed on the n-type cathode layer14, and the gate electrode93is formed on the first layer531of the p-type gate layer53, so that the light emitting thyristor portion60including the light emitting thyristor66is formed. The light emitting thyristor66, which is, for example, an epitaxial film, can be separated from the production substrate150by etching the separation layer151and can be attached or bonded onto another substrate.

The subsequent processes illustrated inFIGS. 13E and 13Fare the same as those illustrated inFIGS. 11E and 11F.

As described above, in the light emitting element device6according to the sixth embodiment, the etching in the etching process illustrated inFIG. 13Bstops at the second layer (or first etching stop layer)532in the p-type gate layer53. Thus, the thickness of the p-type gate layer53can be minimized. As such, it is possible to reduce the thickness of the p-type gate layer53, thereby improving the light extraction efficiency from the light emitting element device6and the switching characteristics of the light emitting element device6.

Further, in the light emitting element device6according to the sixth embodiment, the second layer532, which is an etching stop layer, is a semiconductor layer formed in the p-type gate layer53and having the same conductivity type as the first layer531and third layer533. Thus, it is possible to reduce effects of energy barrier due to a pn junction, thereby improving the switching characteristics.

Further, in the light emitting element device6according to the sixth embodiment, the etching in the etching process illustrated inFIG. 13Cstops at the second layer (or second etching stop layer)612in the p-type anode layer61. Thus, the thickness of the p-type anode layer61can be minimized. As such, it is possible to reduce the thickness of the p-type anode layer61, thereby improving the light extraction efficiency from the light emitting element device6when back surface reflection is used (or when a light reflecting surface made of, for example, metal is disposed on a surface of the substrate120), and improving the switching characteristics of the light emitting element device6.

<7-1> Light Emitting Element Device

FIG. 14is a sectional view schematically illustrating a configuration of a light emitting element device7according to a seventh embodiment of the present invention. InFIG. 14, elements that are the same as or correspond to those illustrated inFIG. 10(or the fifth embodiment) are given the same reference characters. The light emitting element device7according to the seventh embodiment differs from the light emitting element device5according to the fifth embodiment in the following two points.

Firstly, in the seventh embodiment, the fourth semiconductor layer (or n-type cathode layer)14of the second conductivity type, the third semiconductor layer (or p-type gate layer)73of the first conductivity type, the second semiconductor layer (or n-type gate layer)12of the second conductivity type, and the first semiconductor layer (or p-type anode layer)11of the first conductivity type are layered in this order on the semiconductor substrate120.

Secondly, the third semiconductor layer (or p-type gate layer)73includes a third layer733, a second layer732adjacent to a surface of the third layer733on the second semiconductor layer12side, and a first layer731adjacent to a surface of the second layer732on the second semiconductor layer12side; the second layer732is an etching stop layer. For example, the third layer733is a p-type AlGaAs layer, the second layer732is a p-type InGaP layer and serves as an etching stop layer, and the first layer731is a p-type AlGaAs layer. The gate electrode93is provided on the third layer733.

Except for these differences, the light emitting element device7according to the seventh embodiment is the same as the light emitting element device5according to the fifth embodiment.

The light emitting element device7includes a light emitting thyristor portion (which may also be referred to as a light emitting element device)70including a light emitting thyristor76, and a part of the semiconductor substrate120on which the light emitting thyristor portion70is provided.

<7-2> Manufacturing Process of Light Emitting Element Device

The light emitting element device7is produced as follows, for example. First, the light emitting thyristor76is formed on an n-type AlAs layer (or separation layer) on a production substrate. The light emitting thyristor76has a layered structure consisting of the n-type cathode layer (or n-type AlGaAs layer)14, the third layer (or p-type AlGaAs layer)733of the p-type gate layer73, the second layer (or p-type InGaP layer)732, which is an etching stop layer, the first layer (or p-type AlGaAs layer)731of the p-type gate layer73, the n-type gate layer (or n-type AlGaAs layer)12, and the p-type anode layer (or p-type AlGaAs layer)15. The second layer732, which is an etching stop layer, is a semiconductor layer having an etching rate lower than that of the semiconductor layer (inFIG. 14, the first layer731) adjacent to and above the second layer732. In this example, the second layer732has an etching rate lower than that of each of the semiconductor layers (inFIG. 14, the first layer731and third layer733of the p-type gate layer73) adjacent to the second layer732.

Next, by wet etching, the third layer733of the p-type gate layer73is partially exposed, so that a region on which the gate electrode93is to be formed is formed.

Next, by wet etching, the third layer733of the p-type gate layer73and a part of the n-type cathode layer14are etched, so that a region on which the cathode electrode92is to be formed is formed.

Next, the anode electrode91is formed on the p-type anode layer11, the cathode electrode92is formed on the n-type cathode layer14, and the gate electrode93is formed on the third layer733of the p-type gate layer73, so that the light emitting thyristor portion70including the light emitting thyristor76is formed. The light emitting thyristor76, which is, for example, an epitaxial film, can be separated from the production substrate and can be attached or bonded onto another substrate.

Next, the light emitting thyristor portion70is separated from the production substrate and bonded onto the semiconductor substrate120.

As described above, in the light emitting element device7according to the seventh embodiment, the etching in the etching process stops at the second layer732, which is an etching stop layer, in the p-type gate layer73. Thus, the thickness of the p-type gate layer73can be minimized. As such, it is possible to reduce the thickness of the p-type gate layer73, thereby improving the light extraction efficiency from the light emitting element device7and the switching characteristics of the light emitting element device7.

Further, in the light emitting element device7according to the seventh embodiment, the second layer732, which is an etching stop layer, is a semiconductor layer formed in the p-type gate layer73and having the same conductivity type as the first layer731and third layer733. Thus, it is possible to reduce effects of energy barrier due to a pn junction, thereby improving the switching characteristics.

<8-1> Light Emitting Element Device

FIG. 15is a sectional view schematically illustrating a configuration of a light emitting element device8according to an eighth embodiment of the present invention. InFIG. 15, elements that are the same as or correspond to those illustrated inFIG. 12(or the sixth embodiment) are given the same reference characters. The light emitting element device8according to the eighth embodiment differs from the light emitting element device6according to the sixth embodiment in the following three points.

Firstly, in the eighth embodiment, a fourth semiconductor layer (or n-type cathode layer)84of the second conductivity type, a third semiconductor layer (or p-type gate layer)83of the first conductivity type, the second semiconductor layer (or n-type gate layer)12of the second conductivity type, and the first semiconductor layer (or p-type anode layer)11of the first conductivity type are layered in this order on the semiconductor substrate120.

Secondly, the third semiconductor layer (or p-type gate layer)83includes a third layer833, a second layer832adjacent to a surface of the third layer833on the second semiconductor layer12side, and a first layer831adjacent to a surface of the second layer832on the second semiconductor layer12side; the second layer832is an etching stop layer (or first etching stop layer). For example, the third layer833is a p-type AlGaAs layer, the second layer832is a p-type InGaP layer and serves as an etching stop layer, and the first layer831is a p-type AlGaAs layer. The gate electrode93is provided on the third layer833.

Thirdly, the fourth semiconductor layer (or n-type cathode layer)84includes a third layer843, a second layer842adjacent to a surface of the third layer843on the second semiconductor layer12side, and a first layer841adjacent to a surface of the second layer842on the second semiconductor layer12side; the second layer842is another etching stop layer (or second etching stop layer). For example, the third layer843is an n-type AlGaAs layer, the second layer842is an n-type InGaP layer, and the first layer841is an n-type AlGaAs layer. The cathode electrode92is provided on the third layer843.

Except for these differences, the light emitting element device8according to the eighth embodiment is the same as the light emitting element device6according to the sixth embodiment.

The light emitting element device8includes a light emitting thyristor portion (which may also be referred to as a light emitting element device)80including a light emitting thyristor86, and a part of the semiconductor substrate120on which the light emitting thyristor portion80is provided.

<8-2> Manufacturing Process of Light Emitting Element Device

The light emitting element device8is produced as follows, for example. First, the light emitting thyristor86is formed on an n-type AlAs layer (or separation layer) on a production substrate. The light emitting thyristor86has a layered structure consisting of the third layer (or n-type AlGaAs layer)843of the n-type cathode layer (or n-type AlGaAs layer)84, the second layer (or n-type InGaP layer)842, which is the second etching stop layer, the first layer (or n-type AlGaAs layer)841of the n-type cathode layer84, the third layer (or p-type AlGaAs layer)833of the p-type gate layer83, the second layer (or p-type InGaP layer)832, which is the first etching stop layer, the first layer (or p-type AlGaAs layer)831of the p-type gate layer83, the n-type gate layer (or n-type AlGaAs layer)12, and the p-type anode layer (or p-type AlGaAs layer)11. The second layer832, which is the first etching stop layer, is a semiconductor layer having an etching rate lower than that of the semiconductor layer (inFIG. 15, the first layer831) adjacent to and above the second layer832. In this example, the second layer832has an etching rate lower than that of each of the semiconductor layers (inFIG. 15, the first layer831and third layer833of the p-type gate layer83) adjacent to the second layer832. The second layer842, which is the second etching stop layer, is a semiconductor layer having an etching rate lower than that of the semiconductor layer (inFIG. 15, the first layer841) adjacent to and above the second layer842. In this example, the second layer842has an etching rate lower than that of each of the semiconductor layers (inFIG. 15, the first layer841and third layer843of the n-type cathode layer84) adjacent to the second layer842.

Next, by wet etching, the third layer833of the p-type gate layer83is partially exposed, so that a region on which the gate electrode93is to be formed is formed.

Next, by wet etching, the third layer833of the p-type gate layer83and the first layer841of the n-type cathode layer84are partially etched, so that a region on which the cathode electrode92is to be formed is formed.

Next, the anode electrode91is formed on the p-type anode layer11, the cathode electrode92is formed on the third layer843of the n-type cathode layer84, and the gate electrode93is formed on the third layer833of the p-type gate layer83, so that the light emitting thyristor portion80including the light emitting thyristor86is formed. The light emitting thyristor86, which is, for example, an epitaxial film, can be separated from the production substrate and can be attached or bonded onto another substrate.

Next, the light emitting thyristor portion80is separated from the production substrate and bonded onto the semiconductor substrate120.

As described above, in the light emitting element device8according to the eighth embodiment, the etching in the first etching process stops at the second layer832, which is an etching stop layer, in the p-type gate layer83. Thus, the thickness of the p-type gate layer83can be minimized. As such, it is possible to reduce the thickness of the p-type gate layer83, thereby improving the light extraction efficiency from the light emitting element device8and the switching characteristics of the light emitting element device8.

Further, in the light emitting element device8according to the eighth embodiment, the second layer832, which is an etching stop layer, is a semiconductor layer formed in the p-type gate layer83and having the same conductivity type as the first layer831and third layer833. Thus, it is possible to reduce effects of energy barrier due to a pn junction, thereby improving the switching characteristics.

Further, in the light emitting element device8according to the eighth embodiment, the etching in the second etching process stops at the second layer842, which is an etching stop layer, in the n-type cathode layer84. Thus, the thickness of the third layer843of the n-type cathode layer84can be minimized. As such, it is possible to reduce the thickness of the third layer843of the n-type cathode layer84, thereby improving the light extraction efficiency from the light emitting element device8when back surface reflection is used (or when a light reflecting surface made of, for example, metal is disposed on a surface of the substrate120), and improving the switching characteristics of the light emitting element device8.

FIG. 16is a sectional view schematically illustrating a configuration of an optical print head200according to a ninth embodiment of the present invention. The optical print head200is an exposure device of an electrophotographic printer as an electrophotographic image forming apparatus. As illustrated inFIG. 16, the optical print head200includes a base member201, the COB substrate110(also illustrated inFIG. 1), a light emitting thyristor array chip203(including the semiconductor substrate120and light emitting thyristor portions10illustrated inFIG. 1, for example) as a light emitting element array chip, a lens array204as an erecting equal magnification imaging lens, a lens holder205, and a clamper206. The base member201is a member to which the COB substrate110is fixed. The base member201has, in its sides, openings202through which the clamper206fixes the COB substrate110and lens holder205to the base member201. The lens holder205is formed by, for example, injection molding of organic polymeric material or the like. The COB substrate110is a substrate on which the light emitting thyristor array chip203is mounted. The light emitting thyristor array chip203includes a substrate (e.g., the semiconductor substrate120inFIG. 1) including a drive circuit, and a light emitting thyristor array provided on the substrate (or light emitting thyristors bonded to the substrate). The lens array204is an optical lens group that focuses light emitted from the light emitting thyristor array (or light emitting element array) of the light emitting thyristor array chip203on a photosensitive drum as an image carrier to form an image. The arrow B inFIG. 16indicates light emitted from the lens array204. The lens holder205holds the lens array204at a predetermined position of the base member110. The clamper206is a spring member that clamps and holds the base member201, COB substrate110, and lens holder205through the openings202in the base member201and openings207in the lens holder205.

In the ninth embodiment, each of the light emitting element portions constituting the light emitting element array of the optical print head200is the light emitting element device according to any one of the first to eighth embodiments.

In the optical print head200, the drive circuit causes the light emitting thyristor array to selectively emit light based on print data, and the lens array204focuses the emitted light onto a uniformly charged surface of the photosensitive drum, so that an electrostatic latent image is formed on the photosensitive drum. Then, through a development process, a transfer process, and a fixing process, an image consisting of developer is formed (or printed) on a print medium (e.g., a sheet of paper).

As described above, the optical print head200according to the ninth embodiment has improved efficiency of extraction of light from the light emitting element devices including the light emitting thyristors. This can reduce electric power necessary for exposure of the photosensitive drum.

In the first to eighth embodiments, the first conductivity type is p-type and the second conductivity type is n-type, but the first conductivity type may be n-type and the second conductivity type may be p-type.

In the first to eighth embodiments, the second semiconductor layer preferably has a band gap smaller than that of each of the first semiconductor layer and fourth semiconductor layer.

In the first to fifth embodiments, the etching stop layer preferably has an impurity density lower than that of the semiconductor layer adjacent to and above the etching stop layer; the etching stop layer preferably has an impurity density lower than that of the semiconductor layer adjacent to and below the etching stop layer; the etching stop layer preferably has an impurity density lower than that of each of the semiconductor layers adjacent to the etching stop layer. The phrase “above the etching stop layer” refers to being situated on the opposite side of the semiconductor substrate120with respect to the etching stop layer. The phrase “below the etching stop layer” refers to being situated on the semiconductor substrate120side of the etching stop layer. The same applies to the first etching stop layer and second etching stop layer in the sixth to eighth embodiments.

In the first to fifth embodiments, the etching stop layer preferably has a thickness in the range of 10 nm to 50 nm. The same applies to the first etching stop layer and second etching stop layer in the sixth to eighth embodiments.

The present invention is not limited to the embodiments described above; it can be practiced in various other aspects without departing from the invention scope.