Low-1/F-noise local oscillator for non-overlapping differential I/Q signals

The present invention relates to a circuit arrangement (300) for generating non-overlapping and immune-to-1/f-noise signals as has been described. A break-before-make (BBM) circuit ensures that the differential I/Q signals (LO—0, LO—90, LO—180, LO—270), driving the transistors (M11, M12, M21, M22) of mixers (16A, 16B) in an RF receiver (200), are non-over-lapping for having at any time only one of these transistors turned on. The duty cycle of each driving signal is measured, and the difference (Δ) in the duty cycle corresponding to two subsequent LO phases is determined through a respective differential amplifier (38A-38D). Each differential amplifier is configured to have a current output (LT—0, LT—90, LT—180, LT—270), which is then fed back to the input of the input buffer (30A-30D) corresponding to the first LO phase in order to adjust its logic threshold (LT) level and make the difference (Δ) equal to zero. Thereby, the combined action of the BBM circuit and the feedback loops results in four non-overlapping differential I/Q signals (LO—0, LO—90, LO—180, LO—270) with constant and mutually equal duty cycles, and fixed and well-defined relative positions.

FIELD OF THE INVENTION

The present invention relates to the field of communications, and more particularly to local oscillator signals.

BACKGROUND OF THE INVENTION

FIG. 1depicts a conventional direct conversion or homodyne radio-frequency (RF) receiver100, which may also be heterodyne and preferably low-IF heterodyne.

The antenna10converts the radio-frequency electromagnetic (EM) waves into an RF signal, which is first filtered by an RF band-pass filter (BPF)12. The filtered signal is then amplified by a low-noise amplifier (LNA)14in order to increase the strength of the RF signal and reduce the noise Figure of the RF receiver100. The LNA-amplified signal is next input into a frequency converter represented by the dashed line for being down-converted to baseband, using mixers16A,16B and orthogonal signals, i.e. in-phase (I) and quadrature (Q) signals, generated by a so-called local oscillator (LO)18and a 90-degree phase shifter (not represented). Each mixer16A,16B multiplies the LNA-amplified signal at its RF input with a periodic signal provided at its LO input by the LO18, which is tuned to the carrier frequency of the desired RF signal. Each frequency-down-converted signal, also called intermediate-frequency (IF) signal, obtained at each IF output of mixers16A,16B is respectively filtered by a low-pass IF filter20A,20B before being amplified by a respective gain-controlled IF amplifier22A,22B. Usually, an IF filter20A,20B and its respective IF amplifier22A,22B are combined into a single building block as represented by the dashed lines. Each IF-amplified analog signal is then converted into a digital signal by a respective analog-to-digital converter (ADC)24A,24B, and the digital signal is afterwards demodulated by the digital baseband (BB) processor26.

Several types of mixers can be used. However, when the mixers16A,16B are unbalanced or single balanced rather than double balanced, the CMOS frequency divider generating the I/Q LO signals produces a lot of 1/f-noise at the mixers outputs, and this is particularly harmful in case of a zero-IF or near-zero-IF receiver. The problem originates from the fact that the LO-signal generator comprises MOS transistors, which components are known to be 1/f-noisy. This causes relatively-slow random fluctuations of the duty cycle and pulse position of the I/Q LO signals generated by the CMOS frequency divider and then amplified by LO buffers. Indeed, a small fraction of the differential I/Q LO signals ends up at the RF input of the mixers16A,16B, due to crosstalk via parasitic capacitances around the mixer transistors. Ideally, the fundamental content of these signals exactly cancels out. However, in case of fluctuations and/or static differences in duty cycle and pulse position, a small residual part will be left at the RF input of the mixers16A,16B, and will be mixed down to the IF (self mixing). A static mutual deviation in duty cycle and pulse position would result in a DC component at the IF output of the mixers16A,16B. However, the deviations are not static but change over time due to the 1/f-noise, such that the IF signal is polluted by 1/f-noise.

SUMMARY OF THE INVENTION

It is therefore an object of the present invention to provide a low-1/f-noise local oscillator capable to generate non-overlapping differential I/Q signals.

This object is achieved by a circuit arrangement as claimed in claim1, a local oscillator as claimed in claim6, a radio receiver as claimed in claim7, a method as claimed in claim8, a computer program as claimed in claim10, and an integrated circuit as claimed in claims11and12.

In accordance with the present invention, there is provided a circuit arrangement for generating non-overlapping signals immune to 1/f-noise, the circuit arrangement comprising:a break-before-make circuit for generating non-overlapping signals, each of the non-overlapping signals having a subsequent phase and a duty cycle;a plurality of detectors for respectively measuring the duty cycle;a plurality of differential amplifiers for respectively determining a difference in the duty cycle corresponding to two subsequent phases and providing in output a result of the comparison;a plurality of buffers for making the difference equal to zero based on the result corresponding to the first phase amongst the two subsequent phases.

Thereby, the feedback loop made up of the association of a detector and a differential amplifier that feeds back its output to a respective buffer allows to have signals with constant and mutually equal duty cycles. Moreover, a well-defined and mutually equal non-overlap delay can be introduced by the break-before-make circuit, such that the combined action of the break-before-make circuit and the feedback loop allows to have non-overlapping signals not only with constant and mutually equal duty cycles, but also with fixed and well-defined relative positions.

Moreover, each buffer can have a logic threshold that is adjusted based on the result output by the respective differential amplifier and corresponding to the first phase amongst the two subsequent phases. Thereby, the switching instants of the buffer can change, such that the duty cycle of the output signal of the respective buffer can also be adjusted.

Furthermore, the result output by the respective differential amplifier can be in the form of a current. Thereby, a voltage across the output resistance of the stage or gate driving the respective buffer can be built up.

Additionally, the break-before-make circuit can comprise a plurality of NAND-gates, each NAND-gate corresponding to a phase of the subsequent phase. Thereby, the well-defined and mutually equal non-overlap delay can be the gate delay of each NAND-gate.

Also, each detector can be a low-pass filter. Thereby, the measured or detected duty cycle can be a low-frequency signal.

The present invention further extends to a local oscillator for generating driving signals, the local oscillator comprising the preceding circuit arrangement.

The present invention further extends to a radio receiver comprising at least a plurality of mixers, the mixers being driven by the driving signals generated by the preceding local oscillator.

In accordance with the present invention, there is provided a method of generating non-overlapping signals immune to 1/f-noise, the method comprising the steps of:generating non-overlapping signals, each of the non-overlapping signals having a subsequent phase and a duty cycle;measuring the duty cycle, respectively;determining a difference in the duty cycle corresponding to two subsequent phases, respectively;providing in output a result of the comparison;making the difference equal to zero based on the result corresponding to the first phase amongst the two subsequent phases.

Additionally, the step of making the difference equal to zero can comprise adjusting a logic threshold based on the result output by the respective differential amplifier and corresponding to the first phase amongst the two subsequent phases.

The steps of the previous methods can be carried out by a computer program including program code means, when the computer program is carried out on a computer.

The present invention further extends to an integrated circuit comprising either the preceding circuit arrangement (300) or the preceding local oscillator (18).

DETAILED DESCRIPTION OF EMBODIMENTS

Both mixers16A,16B together form a half-complex mixer, which mixes a complex balanced LO signal with a real unbalanced RF signal. The first mixer16A is a in-phase mixer, which comprises a switch cell SWC1coupled to a trans-impedance amplifier TIS1and provides the in-phase component IFI of the IF signal. The second mixer16B is a quadrature mixer, which comprises a switch cell SWC2coupled to a trans-impedance amplifier TIS2and provides the quadrature component IFQ of the IF signal. Each trans-impedance amplifier TIS1, TIS2has a non-inverting input “+” and an inverting input “−”. The switch cells SWC1and SWC2respectively comprise at least a pair of transistors (M11, M12) and (M21, M22), which may be gate-controlled switching devices, such as field effect transistors (FETs) for example. The pair of transistors (M11, M12) is directly driven by a pair of respective in-phase (I) signals, i.e. a non-inverting in-phase signal LO_0and an inverting in-phase signal LO_180, each having a respective phase of 0° and 180°. The pair of transistors (M21, M22) is directly driven by a pair of respective quadrature (Q) signals, i.e. a non-inverting quadrature signal LO_90and an inverting quadrature signal LO_270, each having a respective phase of 90° and 270°. The duty cycle of these differential I/Q signals LO_0, LO_90, LO_180, LO_270will be chosen such that they do not overlap. In other terms, the switching sequence of the transistors M11-M22will be determined in such a manner that, at any time, only one transistor, e.g. M11, will be turned on, the others, i.e. M12, M21, M22, being turned off, since two or more transistors turned on at the same time would result in serious noise boosting of the trans-impedance amplifiers TIS1, TIS2. Thus, the duty cycle of each differential I/Q signal LO_0, LO_90, LO_180, LO_270should not exceed 25%.

FIG. 3discloses the fundamental (or first-harmonic) amplitude A of a 1Vpp-amplitude binary signal versus its duty cycle dc according to the relation A=(2/π)*sin(π*dc).

Thence, it can be observed that the slope of the curve is quite steep around 25%-duty cycle, such that duty cycle variations due to 1/f-noise will lead to substantial amplitude variations. These uncorrelated amplitude variations of the four differential I/Q signals LO_0, LO_90, LO_180, LO_270will result in a non-perfect cancellation of the four crosstalk signals at the RF input of the mixers16A,16B. To the contrary, these duty cycle variations are almost absent in case the duty cycle is around 50%, since the tangent line to the curve at that value is roughly horizontal. Nevertheless, such a non-perfect cancellation when the duty cycle is around 50% can still occur, in the case of pulse-position variations.

However, by comparison with signals having a 50%-duty cycle, the signals having a 25%-duty cycle have the advantage that they can be used in I/Q receivers without LNA. In presence of LNA, they have also the advantage that this LNA only needs to have one current output, whereas two current outputs are needed in the case of signals with a 50%-duty cycle for avoiding any trans-impedance amplifier noise boosting.

FIG. 4illustrates a circuit arrangement300for generating non-overlapping differential I/Q signals LO_0, LO_90, LO_180, LO_270, according to an embodiment of the present invention.

Such a circuit arrangement300comprises input buffers30A-30D, a break-before-make (BBM) circuit, output buffers34A-34D, duty cycle detectors36A-36D and differential amplifiers38A-38D. Each input buffer30A-30D is input by a respective differential I/Q LO signal LOI+, LOQ+, LOI−, LOQ−, each having a respective phase of 0°, 90°, 180° and 270° and a duty cycle less than 25% if non-overlapping and slightly greater than 25% if slightly overlapping (the preferred case), and can include a chain of tapered buffers or inverters, such as CMOS-inverters for example. Each output buffer34A-34D can include a chain of tapered inverters and allows to directly drive a respective transistor M11-M22such as depicted inFIG. 2, by outputting, at the corresponding LO input of the mixers16A,16B, a respective driving signal, namely a respective differential I/Q signal LO_0, LO_90, LO_180, LO_270. The BBM circuit has four inputs, each respectively supplied by an input signal in_0, in_90, in_180, in_270and coupled to the output of the respective input buffers30A-30D, and four outputs, each respectively providing an output signal out_0, out_90, out_180, out_270and coupled to the input of the respective output buffers34A-34D. It comprises as many NAND-gates as there are differential LO I/Q signals LOI+, LOQ+, LOI−, LOQ−, namely four NAND-gates32A-32D. Moreover, since it exists an a priori information about the differential LO I/Q signals LOI+, LOQ+, LOI−, LOQ−, 2-input NAND-gates can be used rather than 4-input NAND-gates as it is required in the case of a full-blown generic BBM circuit. By comparison, the use of 2-input NAND-gates32A-32D has the advantage to render the BBM circuit less complex and faster. The duty cycle of each differential I/Q signal LO_0, LO_90, LO_180, LO_270is determined using a respective duty cycle detector36A-36D, such as a first-order low-pass filter for example, which converts the detected duty cycle into a low-frequency signal, which is then provided to a respective differential amplifier38A,38B,38C,38D. To do so, each duty cycle detector36A-36D has its input connected to the output of a respective output buffer34A-34D, namely connected to a respective LO input of the mixers16A,16B, and its output commonly connected to the input of a pair of subsequent differential amplifiers38A-38B,38B-38C,38C-38D,38D-38A, in such a manner that, when a difference Δ in the duty cycle corresponding to two subsequent LO phases, namely 270° and 0°, 0° and 90°, 90° and 180° or 180° and 270°, is detected, this difference Δ is determined through the respective differential amplifier38A-38D. Each differential amplifier38A-38D is configured to have a current output LT_0, LT_90, LT_180, LT_270, which is then fed back to the input of the input buffer30A-30D corresponding to the first LO phase in order to adjust its logic threshold (LT) level and make the difference Δ equal to zero. Indeed, the output current of the differential amplifiers38A-38D builds up a voltage across the output resistance of the stage or gate driving the respective input buffer30A-30D. As depicted inFIG. 5wherein the input voltage Vin of a buffer has non-zero rise and fall times, this built-up voltage leads to an offset, from {circle around (1)} to {circle around (2)}, of its input voltage Vin downwards by a certain amount, without shifting its LT level. From another view, this can also be construed as shifting, from {circle around (1)} to {circle around (2)}, its LT level upwards by the same previous amount, without offsetting its input voltage Vin. In both cases, offsetting the input voltage Vin alone or shifting the LT level alone results in changing the switching instants t′ and t″ from {circle around (1)} to {circle around (2)}, such that the duty cycle of the differential LO I/Q signals LOI+, LOQ+, LOI−, LOQ− can be adjusted. Thus, the input signals in_0, in_90, in_180, in_270of the BBM circuit can have a duty-cycle value adjusted with respect to the differential LO I/Q signals LOI+, LOQ+, LOI−, LOQ−.

It is to be noted that the connection between the output of the differential amplifiers38A-38D and the corresponding input buffers30A-30D may also be made through a series resistor in order to reduce capacitive loading. Furthermore, in case the input buffers30A-30D are formed of a chain of tapered buffers or inverters, the current output will be preferably connected to the most-left input of the chain in order to maximize the effect of the respective differential amplifiers38A-38D by increasing the over-all loop-gain this way, which in turn is suitable for a large 1/f-noise suppression and static timing-error correction.

For clarity reasons, the input and output buffers30A-30D,34A-34D are assumed to be delay-less, since their gate delay is not essential for the operation of the BBM circuit, such that the differential I/Q signals LO_0, LO_90, LO_180, LO_270directly driving the respective transistors M11-M22ofFIG. 2exhibit the same but inverted waveforms as the output signals out_0, out_90, out_180, out_270of the BBM circuit. The symbol tdrepresents the gate delay of each NAND-gate32A-32D, and w represents the pulse width, namely the product of duty cycle and period, of each differential I/Q signal LO_0, LO_90, LO_180, LO_270.

As can be seen fromFIG. 6, the gate delay tdalso determines the exact gap between the trailing edge of an differential I/Q signal LO_0, LO_90, LO_180, LO_270corresponding to a given LO phase and the leading edge LO_0, LO_90, LO_180, LO_270of the differential I/Q signal corresponding to the next LO phase. Indeed, the gate delay tddetermines the time interval of non-overlap of the differential I/Q signals LO_0, LO_90, LO_180, LO_270, in case the input signals in_0, in_90, in_180, in_270are overlapping by an amount equal to or greater than the gate delay td. When the input signals in_0, in_90, in_180, in_270do not overlap or overlap by an amount lower than the gate delay td, the BBM circuit does not modify the differential I/Q signals LO_0, LO_90, LO_180, LO_270apart from adding some delay imposed by itself.

Furthermore, it can be observed that as long as the input signals in_0, in_90, in_180, in_270are overlapping, only the positions of their trailing edges affect the differential I/Q signals LO_0, LO_90, LO_180, LO_270, the positions of their leading edges being irrelevant. If, for example, the trailing edge of the input signal in_90is shifted towards the right by acting on the LT level of the input buffer30B, then the trailing edge of the differential I/Q signal LO_90will be also shifted towards the right, thus increasing its duty cycle. In turn, the shifted position of this trailing edge will shift towards the right the leading edge of the differential I/Q signal LO_180, thus decreasing its duty cycle. It is the reason why, in this example, the differential amplifier38C that determines the duty cycle difference A corresponding to the pair of LO phases 90° and 180° regulates through its output the input buffer30B corresponding to the LO phase 90°, namely corresponding to the first LO phase amongst the two issued from the pair. This particular example applies more generally to the other subsequent LO phases (270°, 0°), (0°, 90°), (180°, 270°). Indeed, changing the LT level of the input buffers30A-30D in the circuit arrangement300ofFIG. 4allows guaranteeing that the pulse width w, and therefore the duty cycle, of each differential I/Q signal LO_0, LO_90, LO_180, LO_270is constant and mutually equal. Moreover, in conjunction with the BBM circuit that provides, through its NAND-gates32A-32D, a well-defined and mutually equal non-overlap delay td, the circuit arrangement300contributes to guarantee that the relative quadrature position of the differential I/Q signals LO_0, LO_90, LO_180, LO_270is also well defined and fixed, for example when signals in_0, in_90, in_180, in_270are overlapping and are applied at the inputs of the BBM circuit. In fact, it can be seen fromFIG. 6that the distance between corresponding edges of two subsequent differential I/Q signals, i.e. between LO_0and LO_90, LO_90and LO_180, LO_180and LO_270, LO_270and LO_0, is equal to (w+td), such that if T represents the LO period, then T=4*(w+td) and the pulse width w can be defined as mutually equal to (T/4−td).

Thus, the association of a duty cycle detector36A-36D with a differential amplifier38A-38D configured to have a current output LT_0, LT_90, LT_180, LT_270that is fed back to the input of a respective input buffer30A-30D constitutes a feedback loop for each LO phase 0°, 90°, 180°, 270°, and the combined action of the BBM circuit and each feedback loop results in four non-overlapping output signals out_0, out_90, out_180, out_270with constant and mutually equal duty cycles, and fixed and well-defined relative positions. As mentioned above, the four non-overlapping differential I/Q signals LO_0, LO_90, LO_180, LO_270also exhibit the same but inverted waveforms as these output signals out_0, out_90, out_180, out_270, namely they have also constant and mutually equal duty cycles, and fixed and well-defined relative positions. Thereby, the circuit arrangement300when applied as local oscillator can provide IF signals immune to pollution with 1/f-noise and without any DC component.

The embodiment of the present invention has been described in the case of a single RF receiver pipe. In another embodiment, a plurality of RF receiver pipes can be used, the selection being carried out, for example, by a NAND-gate located at the input of each input buffer30A-30D.

In summary, a circuit arrangement300for generating non-overlapping and immune-to-1/f-noise signals has been described. A break-before-make (BBM) circuit ensures that the differential I/Q signals LO_0, LO_90, LO_180, LO_270, driving the transistors M11, M12, M21, M22of mixers16A,16B in an RF receiver200, are non-overlapping for having at any time only one of these transistors turned on. The duty cycle of each driving signal is measured, and the difference Δ in the duty cycle corresponding to two subsequent LO phases is determined through a respective differential amplifier38A-38D. Each differential amplifier is configured to have a current output LT_0, LT_90, LT_180, LT_270, which is then fed back to the input of the input buffer30A-30D corresponding to the first LO phase in order to adjust its logic threshold (LT) level and make the difference Δ equal to zero. Thereby, the combined action of the BBM circuit and the feedback loops results in four non-overlapping differential I/Q signals LO_0, LO_90, LO_180, LO_270with constant and mutually equal duty cycles, and fixed and well-defined relative positions.

Finally, any reference signs in the claims should not be construed as limiting the scope.