Display device and manufacturing method thereof

A display device according to an exemplary embodiment of the present invention includes: a substrate; a plurality of transistors formed on the substrate; and a light-emitting device connected to the plurality of transistors, wherein the transistor includes a gate electrode, the plurality of transistors include a first transistor and a second transistor of which lateral wall slope angles of the gate electrode are different from each other, and the first transistor further includes a doping control member formed on a lateral wall of the gate electrode.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2015-0121092 filed on Aug. 27, 2015 in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety.

TECHNICAL FIELD

The present invention relates to a display device and a manufacturing method thereof.

DISCUSSION OF RELATED ART

In general, as a display device, one such as a liquid crystal display (LCD), an organic light emitting device (organic light emitting diode display, OLED display), and the like are used.

The organic light emitting diode display includes two electrodes and an organic light emitting layer positioned therebetween. Electrons injected from a cathode that is an electrode and holes injected from an anode that is another electrode are combined to each other in the organic light emitting layer to form excitons. Light is emitted when the excitons discharge energy.

SUMMARY

According to an exemplary embodiment of the present invention, a display device is provided as follows. The display device includes a pixel driving circuit and a light-emitting device connected to the pixel driving circuit. The pixel driving circuit includes a first transistor having a first gate electrode and a second transistor having a second gate electrode. A lateral wall slope angle of the first gate electrode is different from a lateral wall slope angle of the second gate electrode. The first transistor further includes a doping control member formed on a lateral wall of the first gate electrode.

According to an exemplary embodiment of the present invention, a method of manufacturing a display device is provided as follows. Transistors including a gate electrode are formed on a substrate. A light-emitting device connected to the transistors is formed. The forming of the transistors includes forming a first gate electrode and a second gate electrode having different lateral wall slope angles on a substrate, forming an insulating layer covering the first gate electrode and the second gate electrode and etching the insulating layer to form a doping control member on a lateral wall of the first gate electrode.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

Exemplary embodiments of the present invention will be described below in detail with reference to the accompanying drawings. However, the present invention may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. In the drawings, the thickness of layers and regions may be exaggerated for clarity. It will also be understood that when an element is referred to as being “on” another element or substrate, it may be directly on the other element or substrate, or intervening layers may also be present. It will also be understood that when an element is referred to as being “coupled to” or “connected to” another element, it may be directly coupled to or connected to the other element, or intervening elements may also be present. Like reference numerals may refer to the like elements throughout the specification and drawings.

Further, since sizes and thicknesses of constituent members shown in the accompanying drawings are arbitrarily given for better understanding and ease of description, the present invention is not limited thereto. In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. In the drawings, for better understanding and ease of description, the thicknesses of some layers and areas are exaggerated.

Also, the present invention is not limited to a number of transistors and capacitors shown in accompanying drawings, and in the display device, each pixel may be provided with a plurality of transistors and at least one capacitor, and may be formed to have various structures by further forming additional wires or omitting existing wires. In this case, the pixel is a minimum unit for displaying an image, and the display device displays the image through the plurality of pixels.

Further, in the specification, the phrase “on a plane” means viewing the object portion from the top, and the phrase “on a cross-section” means viewing a cross-section of which the object portion is vertically cut from the side.

Now, a display device according to an exemplary embodiment of the present invention will be described with reference to accompanying drawings.

FIG. 1is a circuit diagram of one pixel of a display device according to an exemplary embodiment of the present invention.

As illustrated inFIG. 1, a unit pixel PX of the organic light emitting diode display according to an exemplary embodiment of the present invention includes a pixel driving circuit, and an organic light emitting diode OLED connected to the pixel driving circuit. The pixel driving circuit includes a plurality of signal lines151,152,153,158,171,172, and192, a plurality of transistors T1, T2, T3, T4, T5, T6, and T7connected to the plurality of signal lines, and a storage capacitor Cst. In an exemplary embodiment, the unit pixel PX is repeatedly arranged to form a display area. In this case, the signal lines151,152,153,158,171,172and192are also repeatedly connected to the transistors T1through T7. The transistors T1, T2, T3, T4, T5, T6, and T7include a first transistor group TA in which the reliability such as the leakage current is the important factor, and a second transistor group TB in which charge mobility related to the reaction speed is the important factor. The first transistor group TA includes a driving transistor T1, a compensation transistor T3, and an initialization transistor T4. The second transistor group TB includes a switching transistor T2, an operation control transistor T5, a light emission control transistor T6, and a bypass transistor T7.

The signal lines151,152,153,158,171,172, and192may include a scan line151, a previous scan line152, a light emission control line153, a bypass control line158, a data line171, a driving voltage line172, and an initialization voltage line192.

The scan line151transmits a scan signal Sn, the previous scan line152transmit a previous scan signal Sn−1 to the initialization transistor T4, the light emission control line153transmits a light emission control signal EM to the operation control transistor T5and the light emission control transistor T6, and the bypass control line158transmits a bypass signal BP to the bypass transistor T7.

The data line171crosses the scan line151, transmitting a data signal Dm. The driving voltage line172is substantially parallel to the data line171and transmits a driving voltage ELVDD. The initialization voltage line192transmits an initialization voltage Vint which is applied to the driving transistor T1through the initialization transistor T4.

The scan line151, the previous scan line152, the light emission control line153, the bypass control line158, the data line171, the driving voltage line172, and the initialization voltage line192are connected to the pixel PX.

A gate electrode G1of the driving transistor T1is connected to a first electrode Cst1of the storage capacitor Cst, a source electrode S1of the driving transistor T1is connected to the driving voltage line172via the operation control transistor T5, and a drain electrode D1of the driving transistor T1is electrically connected to an anode of the organic light emitting diode OLED via the emission control transistor T6. The driving transistor T1receives the data signal Dm according to a switching operation of the switching transistor T2to supply a driving current Id to the organic light emitting diode OLED.

A gate electrode G2of the switching transistor T2is connected to the scan line151, a source electrode S2of the switching transistor T2is connected to the data line171, and a drain electrode D2of the switching transistor T2is connected to the source electrode S1of the driving transistor T1. The drain electrode D2is also connected to the driving voltage line172via the operation control transistor T5. The switching transistor T2is turned on according to the scan signal Sn received through the scan line151to perform a switching operation transferring the data signal Dm transferred to the data line171to the source electrode S1of the driving transistor T1.

A gate electrode G3of the compensation transistor T3is connected to the scan line121, a source electrode S3of the compensation transistor T3is connected to the drain electrode D1of the driving transistor T1and connected to the anode of the organic light emitting diode OLED via the emission control transistor T6, and a drain electrode D3of the compensation transistor T3is connected to the first electrode Cst1of the storage capacitor Cst, the drain electrode D4of the initialization transistor T4, and the gate electrode C1of the driving transistor T1. The compensation transistor T3is turned on according to the scan signal Sn received through the scan line151so that the driving transistor T1is diode-connected by connecting the gate electrode G1and the drain electrode D1via the compensation transistor T3.

A gate electrode G4of the initialization transistor T4is connected to a previous scan line152, a source electrode S4of the initialization transistor T4is connected to the initialization voltage line192, and a drain electrode D4of the initialization transistor T4is connected to the first electrode Cst1of the storage capacitor Cst, the drain electrode D3of the compensation transistor T3, and the gate electrode C1of the driving transistor T1. The initialization transistor T4is turned on according to the previous scan signal Sn−1 received through the previous scan line152to transfer the initialization voltage Vint to the gate electrode G1of the driving transistor T1so that a voltage of the gate electrode G1of the driving transistor T1is initialized using the initialization voltage Vint. For example, in response to the previous scan signal Sn−1 applied before application of the scan signal Sn, the gate electrode G1is applied by the initialization voltage Vint via the initialization transistor T4. In this case, the compensation transistor T3and the initialization transistor T4are formed of a dual gate structure transistor to reduce a leakage current through the transistors T3and T4.

A gate electrode G5of the operation control transistor T5is connected to the emission control line153, a source electrode S5of the operation control transistor T5is connected to the driving voltage line172, and a drain electrode D5of the operation control transistor T5is connected to the source electrode S1of the driving transistor T1and the drain electrode S2of the switching transistor T2.

A gate electrode G6of the emission control transistor T6is connected to the emission control line153, a source electrode S6of the emission control transistor T6is connected to the drain electrode D1of the driving transistor T1and the source electrode S3of the compensation transistor T3, and a drain electrode D6of the emission control transistor T6is connected to the anode of the organic light emitting diode OLED. The operation control transistor T5and the first emission control transistor T6are substantially simultaneously turned on according to the emission control signal EM transmitted to the light emission control line153such that the driving voltage ELVDD is compensated through the diode-connected driving transistor T1and is transmitted to the organic light emitting diode OLED.

A gate electrode G7of the bypass transistor T7is connected to the bypass control line158, a source electrode S7of the bypass transistor T7is connected to the drain electrode D6of the light emission control transistor T6and the anode of the organic light emitting diode OLED, and a drain electrode D7of the bypass transistor T7is connected to the initialization voltage line192and the source electrode S4of the initialization transistor T4.

A second electrode Cst2of the storage capacitor Cst is connected to the driving voltage line172. A cathode of the organic light emitting diode OLED is connected to a common voltage line741transferring a common voltage ELVSS.

The unit pixel PX includes seven transistors T1to T7and one capacitor Cst, but the present invention is not limited thereto, and the number of transistors and the number of capacitors may change in an exemplary embodiment.

Next, the detailed structure of a transistor of the first transistor group and a transistor of the second transistor group of the display device shown inFIG. 1will be described with reference toFIG. 2andFIG. 3.

FIG. 2shows layouts of the driving transistor T1and the switching transistor T2ofFIG. 1according to an exemplary embodiment of the present invention.FIG. 3are cross-sectional views taken along lines III-III and III′-III′ ofFIG. 2. The driving transistor T1is shown as a representative example of the first transistor group TA, and the switching transistor T2is shown as a representative example of the second transistor group TB.

As shown inFIGS. 2 and 3, semiconductor members13A and13B are formed on a substrate110. The first semiconductor member13A and the second semiconductor member13B are spaced apart from each other. The first semiconductor members13A and13B may be collectively referred to as a semiconductor member130. The first semiconductor member13A includes a first channel131A, a lightly doped drain LDD, a first source electrode136A, and a first drain electrode137A. The first source electrode136A and the first drain electrode137A are formed on respective sides of the first channel131A. The lightly doped drain LDD is formed between the first channel131A and the first source electrode136A and between the first channel131A and the first drain electrode137A. The second semiconductor member13B includes a second channel131B, a second source electrode136B, and a second drain electrode137B. The second source electrode136B and the second drain electrode137B are formed on respective sides of the second channel131B. A lightly doped drain LDD as formed in the first semiconductor member13A is not formed in the second semiconductor member13B.

A gate insulating layer140covering the first semiconductor member13A and the second semiconductor member13B is formed the substrate110. A first gate electrode15A is protruded from a first scan line15to overlap a first semiconductor member13A and a second gate electrode15B is protruded from a second scan line16to overlap a second semiconductor member13B. The first and the second gate electrodes15A and15B are formed on the gate insulating layer140. The first gate electrode15A is formed on a first channel131A, and the second gate electrode15B is formed on a second channel131B. A lateral wall of the first gate electrode15A is inclined, and a first lateral wall slope angle θ1of the lateral wall of the first gate electrode15A with respect to the surface of the substrate110may range from about 70 degrees to about 90 degrees. The lateral wall of the second gate electrode15B is inclined and a second lateral wall slope angle θ2may be less than about 70 degrees. A doping control member SP is formed on each lateral wall of the first gate electrode15A. The doping control members SP are not separately formed on each lateral wall of the second gate electrode15B. As described above, since a doping control member SP is formed on each lateral wall of the first gate electrode15A of the first lateral wall slope angle θ1, the lightly doped drains LDD are formed underneath the doping control members SP. However, since the doping control members SP is not formed on the lateral walls of the second gate electrode15B having the second lateral wall slope angle θ2that is lower than the first lateral wall slope angle θ1, the lightly doped drain LDD is not formed.

The first transistor T1includes the first semiconductor member13A including the first channel131A, the first source electrode136A, and the first drain electrode137A and the first gate electrode15A. The second transistor T2includes the second semiconductor member13B including the second channel131B, the second source electrode136B, and the second drain electrode137B and the second gate electrode15B.

A residual insulating layer SPR is formed on the lateral wall of the first scan line15and on the lateral wall of the second scan line16except for the second gate electrode15B.

A manufacturing method of the display device according to an exemplary embodiment of the present invention will be described with reference toFIGS. 4, 5, 6, and 7.

FIG. 4shows layouts showing a manufacturing method of a display device according to an exemplary embodiment of the present invention,FIG. 5shows cross-sectional views taken along lines V-V and V′-V′ ofFIG. 4,FIG. 6shows layouts showing a following step ofFIG. 4, andFIG. 7shows cross-sectional views taken along lines VII-VII and VII′-VII′ ofFIG. 6.

Firstly, as shown inFIGS. 4 and 5, a first semiconductor member13A and a second semiconductor member13B are formed on a substrate110. A gate insulating layer140covering the semiconductor members13A and13B is formed. A gate metal layer150is formed on the gate insulating layer140. A photosensitive film is formed on the gate metal layer150. The photosensitive film may be a negative photosensitive film of which an exposed portion remains after a developing process.

The photosensitive film is exposed and developed by using a partial exposure mask1000to form a first photosensitive film member PR1and a second photosensitive film member PR2. In this case, a full opening1001of the partial exposure mask1000is positioned on the first semiconductor member13A and a partial opening1002having a slit part SL of the partial exposure mask1000is positioned on the second semiconductor member13B. Accordingly, through the exposure and developing process to the photosensitive film, the first photosensitive film member PR1exposed by the full opening1001is formed, and the second photosensitive film member PR2exposed by the partial opening1002is formed. However, the second photosensitive film member PR2of the position corresponding to the slit part SL of the partial opening1002is only partially removed. Accordingly, the lateral wall of the first photosensitive film member PR1has a steep slope, and the lateral wall of the second photosensitive film member PR2has a step shape. The partial opening1002of the partial exposure mask1000has the slit part, but the present invention is not limited thereto, and the partial exposure mask in which the partial opening is formed of a half tone may be used.

Next, as shown inFIGS. 6 and 7, the gate metal layer150is etched by using the first photosensitive film member PR1and the second photosensitive film member PR2as an etching mask to form a first gate electrode15A and a second gate electrode15B. In this case, since the lateral wall of the first photosensitive film member PR1has the steep slope, the lateral wall of the first gate electrode15A also has a steep slope. However, the lateral wall of the second photosensitive film member PR2has the step shape, and the lateral wall of the second gate electrode15B has a slope less than the steep slope. The first lateral wall slope angle θ1of the first gate electrode15A may range between about 70 degrees and about 90 degrees. The second lateral wall slope angle θ2of the second gate electrode15B may be less than about 70 degrees. When the first lateral wall slope angle θ1is less than about 70 degrees or is larger than about 90 degrees, the doping control members SP need not be formed.

Also, an insulating layer SPL covering the first gate electrode15A and the second gate electrode15B is formed on the gate insulating layer140.

Next, as shown inFIGS. 2 and 3, the insulating layer SPL is patterned by being etched by a dry etching method to form the doping control member SP. For example, the insulating layer SPL positioned on the lateral wall of the first gate electrode15A having the steep slope remains to be the doping control member SP, and the insulating layer SPL positioned on the lateral wall of the second gate electrode15B is removed. Also, by performing a doping process, a lightly doped drain LDD may be formed underneath the doping control member SP. For example, a portion of the first semiconductor member13A underneath the doping control member SP is converted to the lightly doped drain LDD by the doping process. In an exemplary embodiment, a first channel131A is also formed underneath the first gate electrode15A in the doping process. For example, a portion of the first semiconductor member13A underneath the first gate electrode15A is converted to the first channel131A. In an exemplary embodiment, the lightly doped drain LDD and the first channel131A are formed at the same time using the same doping process. Since the ion is partially doped in the first semiconductor member13A at the position corresponding to the control members SP, the lightly doped drain LDD is formed. A first source electrode136A and a first drain electrode137A are formed in the first semiconductor member13A at the position where the doping of the ion is not prevented. As described above, the first channel131A, the lightly doped drain LDD, the first source electrode136A, and the first drain electrode137A are formed to form the first transistor T1along with the first gate electrode15A.

Since the ion is doped in the second semiconductor member13B of the position corresponding to the second gate electrode15B, the doped second semiconductor member13B is converted to a second channel131B under a second gate electrode15B. A second source electrode136B and a second drain electrode137B are formed in the second semiconductor member13B at the position where the doping of the ion is not prevented. As described above, the second channel131B, the second source electrode136B, and the second drain electrode137B are formed to form the second transistor along with the second gate electrode15B.

As described above, by forming the first gate electrode15A and the second gate electrode15B having the different lateral wall slope angles from each other, the doping control members SP may be formed only on the first gate electrode15A having the large lateral wall slope angle. Accordingly, without the additional mask, the lightly doped drain LDD is formed in the first transistor T1formed with the doping control members SP and a lightly doped drain such as the lightly dope drain LDD of the first transistor T1is prevented from being formed in the second transistor T2. Accordingly, the manufacturing process is simplified and the manufacturing cost is reduced.

In the above, the display device having the first transistor T1and the second transistor T2is described. The first (driving) transistor T1is representative of the first transistor group TA including the compensation transistor T3and the initialization transistor T4, and thus the other transistors of the first transistor group TA may be similarly formed as described above with reference to the driving transistor T1. The second transistor (switching) T2is representative of the second transistor group TB including the operation control transistor T5, the light emission control transistor T6, and the bypass transistor T7, and thus the other transistors of the second transistor group TA may be similarly formed as described above with reference to the second transistor.

Next, the detailed structure of the display device shown inFIG. 1will be described with reference toFIGS. 8, 9, 10, and 11.

FIG. 8is a layout of the unit pixel PX ofFIG. 1according to an exemplary embodiment of the present invention,FIG. 9is a detailed layout view ofFIG. 8,FIG. 10is a cross-sectional view taken along a line X-X ofFIG. 9, andFIG. 11is a cross-sectional view taken along lines XI-XI and XI′-XI′ ofFIG. 9.

Hereinafter, a detailed planar structure of the display device according to the exemplary embodiment of the present invention will be described in detail with reference toFIGS. 8 and 9, and a detailed cross-sectional structure will be described in detail with reference toFIGS. 10 and 11.

As shown inFIGS. 8 and 9, the unit pixel PX according to an exemplary embodiment of the present invention includes a scan line151, a previous scan line152, and a light emission control line153respectively applying a scan signal Sn, a previous scan signal Sn−1, and a light emission control signal EM and formed in a row direction. In an exemplary embodiment, the bypass signal BP and the previous scan signal Sn−1 may be supplied in a time-multiplexing manner to the same signal line152. In an exemplary embodiment, the previous scan signal Sn−1 may also serve as the bypass signal BP. The bypass signal BP may be transmitted through the previous scan line152.

The unit pixel PX also includes a data line171, a driving voltage line172crossing the scan line151, the previous scan line152, and the light emission control line153to apply a data signal Dm and a driving voltage ELVDD, respectively.

The initialization voltage Vint is transmitted from the initialization voltage line192through the initialization transistor T4to the compensation transistor T3. The initialization voltage line192is formed to a straight portion192aand an oblique portion192bwhich are alternately connected to each other. The straight portion192ais disposed parallel to the scan line151, and the oblique portion192bextends at a predetermined angle with respect to the straight portion192a.

Also, the driving transistor T1, the switching transistor T2, the compensation transistor T3, the initialization transistor T4, the operation control transistor T5, the light emission control transistor T6, the bypass transistor T7, the storage capacitor Cst, and the organic light emitting diode (OLED) are formed in the pixel PX. The first transistor group TA includes the driving transistor T1, the compensation transistor T3, and the initialization transistor T4. The second transistor TB includes the switching transistor T2, the operation control transistor T5, the light emission control transistor T6, and the bypass transistor T7.

The organic light emitting diode (OLED) is formed of a pixel electrode191, an organic emission layer370, and a common electrode270. In this case, the compensation transistor T3and the initialization transistor T4are formed of dual gate transistors to prevent a leakage current.

Each channel of the driving transistor T1, the switching transistor T2, the compensation transistor T3, the initialization transistor T4, the operation control transistor T5, the light emission control transistor T6, and the bypass transistor T7is formed inside one connected semiconductor member130which may be bent in various shapes. The semiconductor member130may be formed of polysilicon or an oxide semiconductor material. The oxide semiconductor material may include one of oxides based on titanium (Ti), hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), germanium (Ge), zinc (Zn), gallium (Ga), tin (Sn), or indium (In), or zinc oxide (ZnO), indium-gallium-zinc oxide (InGaZnO4), indium zinc oxide (In—Zn—O), zinc-tin oxide (Zn—Sn—O), indium gallium oxide (In—Ga—O), indium-tin oxide (In—Sn—O), indium-zirconium oxide (In—Zr—O), indium-zirconium-zinc oxide (In—Zr—Zn—O), indium-zirconium-tin oxide (In—Zr—Sn—O), indium-zirconium-gallium oxide (In—Zr—Ga—O), indium-aluminum oxide (In—Al—O), indium-zinc-aluminum oxide (In—Zn—Al—O), indium-tin-aluminum oxide (In—Sn—Al—O), indium-aluminum-gallium oxide (In—Al—Ga—O), indium-tantalum oxide (In—Ta—O), indium-tantalum-zinc oxide (In—Ta—Zn—O), indium-tantalum-tin oxide (In—Ta—Sn—O), indium-tantalum-gallium oxide (In—Ta—Ga—O), indium-germanium oxide (In—Ge—O), indium-germanium-zinc oxide (In—Ge—Zn—O), indium-germanium-tin oxide (In—Ge—Sn—O), indium-germanium gallium oxide (In—Ge—Ga—O), titanium-indium-zinc oxide (Ti—In—Zn—O), or hafnium-indium-zinc oxide (Hf—In—Zn—O) which are complex oxides thereof. In the case where the semiconductor member130is formed of an oxide semiconductor material, an passivation layer for protecting the oxide semiconductor material which is vulnerable to an external environment such as a high temperature may be formed.

The semiconductor member130includes a channel which is channel-doped with an N-type impurity or a P-type impurity, and a source doping region and a drain doping region which are formed at respective sides of the channel and have a higher doping concentration than that of the doping impurity which is doped in the channel. The source doping region and the drain doping region may be referred to as the source electrode and the drain electrode, respectively. The source electrode and the drain electrode may be formed in the semiconductor member130by a doping process. The doping process may be controlled to be performed in the corresponding regions of the semiconductor member130to form the source electrode and the drain electrode. Further, the region between the source electrodes and the drain electrodes of different transistors in the semiconductor member130are doped, and thus the source electrodes may be electrically connected to the drain electrodes.

As illustrated inFIG. 9, the channel131includes a driving channel131awhich is formed in the driving transistor T1, a switching channel131bwhich is formed in the switching transistor T2, a compensation channel131cwhich is formed in the compensation transistor T3, an initialization channel131dwhich is formed in the initialization transistor T4, an operation control channel131ewhich is formed in the operation control transistor T5, a light emission channel131fwhich is formed in the light emission control transistor T6, and a bypass channel131gwhich is formed in the bypass transistor T7.

The driving transistor T1includes the driving channel131a, a driving gate electrode155a, a driving source electrode136a, and a driving drain electrode137a. The driving channel131amay be curved and may have a meandering shape or a zigzag shape. As such, the driving channel131ais formed in the curved shape, and a narrow space thereof may be extendedly formed along the driving channel131a. Therefore, a driving range of the driving gate-source voltage Vgs between the driving gate electrode155aand the driving source electrode136aincreases by forming the driving channel131ato be long. Since the driving range of the driving gate-source voltage Vgs increases, it is possible to more delicately control a gray of light emitted from the organic light emitting diode (OLED) by changing a magnitude of the driving gate-source voltage Vgs, thereby increasing a resolution of the organic light emitting diode display and improving display quality. The shape of the driving channel131ais variously changed, and thus various exemplary embodiments such as ‘reverse S’, ‘S’, ‘M’, ‘W’, and the like may be possible.

The driving gate electrode155aoverlaps the driving channel131a, and the driving source electrode136aand the driving drain electrode137aare formed on respective sides of the driving channel131a. The lightly doped drain LDD is formed between the driving channel131aand the driving source electrode136a, and the lightly doped drain LDD is also formed between the driving channel131aand the driving drain electrode137a. The driving gate electrode155ais connected to a driving connecting member174through a contact hole61.

The switching transistor T2includes the switching channel131b, a switching gate electrode155b, a switching source electrode136b, and a switching drain electrode137b. The switching gate electrode155bwhich is a part of the scan line151overlaps the switching channel131b, and the switching source electrode136band the switching drain electrode137bare formed to be adjacent to sides of the switching channel131b, respectively. The switching source electrode136bis connected to the data line171through a contact hole62.

The compensation transistor T3includes the compensation channel131c, a compensation gate electrode155c, a compensation source electrode136c, and a compensation drain electrode137c. The compensation gate electrode155cthat is a part of the scan line151is formed of a dual gate to prevent a leakage current, and overlaps the compensation channel131c. The compensation source electrode136cand the compensation drain electrode137care formed to be adjacent to sides of the compensation channel131c, respectively.

The lightly doped drain LDD is formed between the compensation channel131cand the compensation source electrode136c, and the lightly doped drain LDD is also formed between the compensation channel131cand the compensation drain electrode137c. The compensation drain electrode137cis connected to a driving connection member174through a contact hole63.

The initialization transistor T4includes the initialization channel131d, an initialization gate electrode155d, an initialization source electrode136d, and an initialization drain electrode137d. The initialization gate electrode155dthat is a part of the previous scan line152is formed as two to prevent the leakage current, and overlaps the initialization channel131d. The initialization source electrode136dand the initialization drain electrode137dare formed to be adjacent to sides of the initialization channel131d, respectively.

The lightly doped drain LDD is formed between the initialization channel131dand the initialization source electrode136d, and the lightly doped drain LDD is also formed between the initialization channel131dand the initialization drain electrode137d. The initialization source electrode136dis connected to a second data connecting member175through a contact hole64.

The operation control transistor T5includes the operation control channel131e, an operation control gate electrode155e, an operation control source electrode136e, and an operation control drain electrode137e. The operation control gate electrode155ethat is a part of the light emission control line153overlaps the operation control channel131e, and the operation control source electrode136eand the operation control drain electrode137eare formed to be adjacent to respective sides of the operation control channel131e. The operation control source electrode136eis connected to a part that extends from the driving voltage line172through a contact hole65.

The light emission control transistor T6includes the light emission control channel131f, a light emission control gate electrode155f, a light emission control source electrode136f, and a light emission control drain electrode137f. The light emission control gate electrode155fthat is a part of the light emission control line153overlaps the light emission control channel131f, and the light emission control source electrode136fand the light emission control drain electrode137fare formed to be adjacent to sides of the light emission control channel131f, respectively. The light emission control drain electrode137fis connected to a third data connecting member179through a contact hole66.

The bypass transistor T7includes the bypass channel131g, a bypass gate electrode155g, a bypass source electrode136g, and a bypass drain electrode137g. The bypass gate electrode155gthat is a part of the previous gate line152overlaps the bypass channel131g, and the bypass source electrode136gand the bypass drain electrode137gare formed to be adjacent to sides of the bypass channel131g, respectively.

The bypass source electrode136gis connected directly to the light emission control drain electrode137f, and the bypass drain electrode137gis connected directly to the initialization source electrode136d.

One end of the driving channel131aof the driving transistor T1is connected to the switching drain electrode137band the operation control drain electrode137e, and the other end of the driving channel131ais connected to the compensation source electrode136cand the light emission control source electrode136f.

The storage capacitor Cst includes a first storage electrode155aand a second storage electrode156disposed via a second gate insulating layer142interposed therebetween. The first storage electrode155acorresponds to the driving gate electrode155a, and the second storage electrode156as a part extended from a storage line157has the wider area than the driving gate electrode155aand covers the entire driving gate electrode155a.

Here, the second gate insulating layer142may be formed of a dielectric material, and the storage capacitance is determined by the charge charged in the storage capacitor Cst and the voltage between two storage electrodes155aand156. As such, the driving gate electrode155ais used as the first storage electrode155a, and as a result, it is possible to ensure a space in which the storage capacitor Cst may be formed within a space narrowed by the driving channel131ahaving a large area in the pixel.

The first storage electrode155awhich is the driving gate electrode155ais connected to one end of the driving connection member174through the driving contact hole61and a storage opening51. The storage opening51is an opening formed in the second storage electrode156. Accordingly, the contact hole61connecting one end of the driving connection member174and the driving gate electrode155ais formed inside the storage opening51. The driving connection member174is formed to be parallel to and at the same layer as the data line171, and the other end of the driving connection member174is connected to the compensation drain electrode137cof the compensation transistor T3and the initialization drain electrode137dof the initialization transistor T4through the contact hole63. Accordingly, the driving connection member174connects the driving gate electrode155a, and the compensation drain electrode137cof the compensation transistor T3and the initialization drain electrode137dof the initialization transistor T4, to each other.

The second storage electrode156is connected to the driving voltage line172through a contact hole69. Accordingly, the storage capacitor Cst stores a storage capacitance corresponding to a voltage difference between the driving voltage ELVDD transferred to the second storage electrode156through the driving voltage line172and the gate voltage Vg of the driving gate electrode155a.

The pixel connecting member179is connected to the pixel electrode191through a contact hole81, and the initialization connecting member175is connected to the initialization voltage line192through a contact hole82.

Hereinafter, cross-sectional structures of the display device according to the exemplary embodiment of the present invention will be described in detail according to a lamination order with reference toFIGS. 10 and 11.

In this case, since a lamination structure of the operation control transistor T5is mostly the same as that of the light emission control transistor T6, a detailed description thereof will be omitted.

A buffer layer120may be formed on a substrate110. The substrate110may be formed of an insulating material such as glass, crystal, ceramic, or plastic, and the buffer layer120serves to block impurities from the substrate110during a crystallization process for forming a polycrystalline semiconductor. The buffer layer120may reduce defects due to the impurities in the polycrystalline semiconductor and reduce stress applied to the substrate110.

The semiconductor member130including a channel131including the driving channel131a, the switching channel131b, the compensation channel131c, the initialization channel131d, the operation control channel131e, the light emission control channel131f, and the bypass channel131gis formed on the buffer layer120. A driving source electrode136aand a driving drain electrode137aare formed on respective sides of the driving channel131ain the semiconductor member130, and a switching source electrode136band a switching drain electrode1371) are formed on respective sides of the switching channel131b. The compensation source electrode136cand the compensation drain electrode137care formed at respective sides of the compensation channel131c, and the initialization source electrode136dand the initialization drain electrode137dare formed at respective sides of the initialization channel131d. The operation control source electrode136eand the operation control drain electrode137eare formed at respective sides of the operation control channel131e, and the emission control source electrode136fand the emission control drain electrode137fare formed at respective sides of the emission control channel131f. The bypass source electrode136gand the bypass drain electrode137gare formed at respective sides of the bypass channel131g.

In this case, the lightly doped drain LDD is formed between the driving channel131aand the driving source electrode136a, and the lightly doped drain LDD is also formed between the driving channel131aand the driving drain electrode137a. The lightly doped drain LDD is formed between the compensation channel131cand the compensation source electrode136c, and the lightly doped drain LDD is also formed between the compensation channel131cand the compensation drain electrode137c. The lightly doped drain LDD is formed between the initialization channel131dand the initialization source electrode136d, and the lightly doped drain LDD is also formed between the initialization channel131dand the initialization drain electrode137d.

The lightly doped drain LDD may mitigate the sudden electric field change of the driving drain electrode137a, the compensation drain electrode137c, and the initialization drain electrode137dto reduce the leakage current. Accordingly, the reliability of the driving transistor T1, the compensation transistor T3, and the initialization transistor T4may be increased.

A first gate insulating layer141covering the semiconductor member130is formed thereon. On the first gate insulating layer141, a first gate metal line (151,152,153, and155a) including a switching gate electrode155b, a scan line151including a compensation gate electrode155c, a previous scan line152including an initialization gate electrode155dand a bypass gate electrode155g, a light emission control line153including an operation control gate electrode155eand a light emission control gate electrode155f, a bypass control line158, and a driving gate electrode (a first storage electrode)155ais formed.

The first lateral wall slope angle θ1of the driving gate electrode155amay be more than about 70 degrees to less than about 90 degrees. A doping control member SP is formed on each lateral wall of the driving gate electrode155a. The doping control members SP are formed at the position corresponding to the lightly doped drain LDD to form the lightly doped drain LDD in the semiconductor member.

The second lateral wall slope angle θ2of the switching gate electrode155bmay be less than about 70 degrees. Accordingly, the doping control members SP are not formed on the lateral walls of the switching gate electrode155b.

The first lateral wall slope angle θ1of the compensation gate electrode155cmay be more than about 70 degrees to less than about 90 degrees. A doping control member SP is formed on each lateral wall of the compensation gate electrode155c.

The first lateral wall slope angle θ1of the initialization gate electrode155dmay range between about 70 degrees and about 90 degrees. A doping control member SP is formed on each lateral wall of the initialization gate electrode155d.

The second lateral wall slope angle θ2of the operation control gate electrode155emay be less than about 70 degrees, the second lateral wall slope angle θ2of the light emission control gate electrode155fmay be about 70 degrees, and the second lateral wall slope angle θ2of the bypass gate electrode155gmay be less than about 70 degrees. Accordingly, the doping control members SP are not all formed on both lateral walls of the operation control gate electrode155e, both lateral walls of the light emission control gate electrode155f, and both lateral walls of the bypass gate electrode155g.

A second gate insulating layer142covering the first gate metal line (151,152,153, and155a) and the first gate insulating layer141is formed thereon. The first gate insulating layer141and the second gate insulating layer142may be formed of silicon nitride (SiNx) or silicon oxide (SiOx).

A second gate metal line (157and156) including a storage line157parallel to the scan line151and the second storage electrode156as an expansion of the storage line157is formed on the second gate insulating layer142.

The second storage electrode156is wider than the first storage electrode155afunctioning as the driving gate electrode such that the second storage electrode156completely covers the driving gate electrode155a.

A gate metal line (151,152,153,155a,156, and157) including the first gate metal line (151,152,153,155a) and the second gate metal line (156and157) may be formed as a multilayer in which metal layers stacked on each other are made of copper (Cu), a copper alloy, aluminum (Al), an aluminum alloy, molybdenum (Mo), or a molybdenum alloy.

An interlayer insulating layer160is formed on the second gate insulating layer142and the second gate metal line (157and156). The interlayer insulating layer160may be formed of a silicon nitride (SiNx) or a silicon oxide (SiOx).

The interlayer insulating layer160has contact holes61,62,63,64,65,66, and69. On the interlayer insulating layer160, a data metal line (171,172,174,175, and179) including a data line171, a driving voltage line172, a driving connecting member174, an initialization connecting member175, and a pixel connecting member179is formed. The data metal line (171,172,174,175, and179) may be formed as a multilayer including metal layers including copper (Cu), a copper alloy, aluminum (Al), an aluminum alloy, molybdenum (Mo), or a molybdenum alloy, and for example, may be formed as a triple layer of titanium/aluminum/titanium (Ti/Al/Ti), a triple layer of molybdenum/aluminum/molybdenum (Mo/Al/Mo), or a triple layer of molybdenum/copper/molybdenum (Mo/Cu/Mo).

The data line171is connected to the switching source electrode136bthrough the contact hole62formed in the first gate insulating layer141, the second gate insulating layer142, and the interlayer insulating layer160, one end of the driving connecting member174is connected to the first storage electrode155athrough the contact hole61formed in the second gate insulating layer142and the interlayer insulating layer160, and the other end of the driving connecting member174is connected to the compensation drain electrode137cand the initialization drain electrode137dthrough the contact hole63formed in the first gate insulating layer141, the second gate insulating layer142, and the interlayer insulating layer160.

The initialization connecting member175parallel to the data line171is connected to the initialization source electrode136dthrough the contact hole64formed in the first gate insulating layer141, the second gate insulating layer142, and the interlayer insulating layer160. Also, the pixel connecting member179is connected to the light emission control drain electrode137fthrough the contact hole66formed in the first gate insulating layer141, the second gate insulating layer142, and the interlayer insulating layer160.

A passivation layer180covering the data metal line (171,172,174,175, and179) and the interlayer insulating layer160is formed thereon. The passivation layer180covers the data metal line (171,172,174,175, and179) to be flattened such that the pixel electrode191may be formed on the passivation layer180without a step. The passivation layer180may be formed of a stacked layer of an organic material such as a polyacrylate resin, a polyimide resin, or the like, or a stacked layer of an organic material and an inorganic material.

The pixel electrode191and the initialization voltage line192are formed on the passivation layer180. The pixel connecting member179is connected to the pixel electrode191through the contact hole81formed in the passivation layer180, and the initialization connecting member175is connected to the initialization voltage line192through the contact hole82formed in the passivation layer180.

A pixel definition layer (PDL)350covering the passivation layer180, the initialization voltage line192, and the edge of the pixel electrode191is formed thereon, and the pixel definition layer350has a pixel opening351exposing the pixel electrode191. The pixel definition layer350may be made of organic materials such as a polyacrylate resin, a polyimide resin, and the like, and silica-based organic materials.

An organic emission layer370is formed on the pixel electrode191exposed through the pixel opening351, and a common electrode270is formed on the organic emission layer370. The common electrode270is also formed on the pixel definition layer350over the plurality of pixels PX. As such, the organic light emitting diode (OLD) including the pixel electrode191, the organic emission layer370, and the common electrode270is formed.

Here, the pixel electrode191is an anode which is a hole injection electrode, and the common electrode270is a cathode which is an electron injection electrode. However, the exemplary embodiment according to the present invention is not limited thereto, and the pixel electrode191may be the cathode and the common electrode270may be the anode according to a driving method of the display device. Holes and electrons are injected into the organic emission layer370from the pixel electrode191and the common electrode270, respectively, and excitons acquired by combining the injected holes and electrons fall from an excitation state to a ground state, thereby emitting light.

The organic emission layer370is made of a low-molecular organic material or a high-molecular organic material such as poly(3,4-ethylenedioxythiophene) (PEDOT). Further, the organic emission layer370may be formed with multiple layers including at least one of an emission layer, a hole injection layer (HIL), a hole transporting layer (HTL), an electron transporting layer (ETL), and an electron injection layer (EIL). When the organic emission layer370includes all of the layers, the hole injection layer is disposed on the pixel electrode191which is the positive electrode, and the hole transporting layer, the light emission layer, the electron transporting layer, and the electron injection layer are sequentially laminated thereon.

The organic emission layer370may include a red organic emission layer emitting red light, a green organic emission layer emitting green light, and a blue organic emission layer emitting blue light, and the red organic emission layer, the green organic emission layer, and the blue organic emission layer are formed at a red pixel, a green pixel, and a blue pixel, respectively, to implement color images.

Further, in the organic emission layer370, all of the red organic emission layer, the green organic emission layer, and the blue organic emission layer are laminated together on the red pixel, the green pixel, and the blue pixel, and a red color filter, a green color filter, and a blue color filter are formed for each pixel to implement the color images. As another example, a white organic emission layer emitting white light is formed on all of the red pixel, the green pixel, and the blue pixel, and the red color filter, the green color filter, and the blue color filter are formed for each pixel to implement the color images. When the color images are implemented by using the white organic emission layer and the color filters, a deposition mask for depositing the red organic emission layer, the green organic emission layer, and the blue organic emission layer on individual pixels, that is, the red pixel, the green pixel, and the blue pixel, respectively, may not be used.

The white organic emission layer described in an exemplary embodiment may be formed by one organic emission layer, and includes a configuration that may emit white light by laminating a plurality of organic emission layers. In an exemplary embodiment, the white organic emission layer may include a configuration that enables the white light to be emitted by combining at least one yellow organic emission layer and at least one blue organic emission layer, a configuration that enables the white light to be emitted by combining at least one cyan organic emission layer and at least one red organic emission layer, a configuration that enables the white light to be emitted by combining at least one magenta organic emission layer and at least one green organic emission layer, and the like.

An encapsulation member (not shown) protecting the organic light emitting diode OLD may be formed on the common electrode270, and the encapsulation member may be sealed to the substrate110by a sealant and may be formed of various materials such as glass, quartz, ceramic, plastic, and a metal. A thin film encapsulation layer may be formed on the common electrode270by depositing the inorganic layer and the organic layer without the usage of the sealant.

A manufacturing method of the display device according to an exemplary embodiment of the present invention will now be described in detail with reference toFIGS. 12, 13, 14, and 15.

FIG. 12is a cross-sectional view showing one step of a manufacturing method of a display device according to an exemplary embodiment of the present invention as a cross-sectional view taken along line X-X of the display device ofFIG. 9,FIG. 13is a cross-sectional view showing the same step asFIG. 12as a cross-sectional view of the display device ofFIG. 9taken along lines XI-XI and XI′-XI′,FIG. 14is a cross-sectional view of a following step ofFIG. 12as a cross-sectional view taken along line X-X of the display device ofFIG. 9, andFIG. 15is a cross-sectional view of the same step asFIG. 14as a cross-sectional view of the display device ofFIG. 9taken along lines XI-XI and XI′-XI′.

First, as illustrated inFIGS. 12 and 13, the buffer layer120is formed on the substrate110. The buffer layer120may be formed of a single layer of a silicon nitride or a laminate layer of a silicon nitride and a silicon oxide, and is deposited on an entire surface of the substrate110by a method such as plasma enhanced chemical vapor deposition (PECVD). In addition, the semiconductor layer131is formed on the buffer layer120. The semiconductor layer131may be formed of polysilicon or an oxide semiconductor, and the polysilicon may be formed by a method of forming an amorphous silicon layer and then crystallizing the layer. Various crystallizing methods may be applied. For example, the amorphous silicon layer may be crystallized by using heat, a laser, Joule heat, an electric field, a catalyst metal, or the like. In this case, the semiconductor layer is in an intrinsic semiconductor state in which an impurity is not doped. Further, the semiconductor layer is patterned into the semiconductor member130having the form illustrated inFIG. 7by performing a photolithography process using a first mask on the semiconductor layer. In this case, the semiconductor member130is not doped, so that the semiconductor member130is not divided into the channel, the source electrode, and the drain electrode configuring each transistor. Further, the semiconductor130is made to be in an impurity semiconductor state by performing channel doping with a low doping concentration on the semiconductor130.

Further, the first gate insulating layer141covering the buffer layer120and the semiconductor layer130is formed thereon. The first gate insulating layer141is formed by depositing silicon nitride (SiNx) or silicon oxide (SiOx) on a front surface thereof by a method of plasma enhanced chemical vapor deposition (PECVD) and the like. In addition, a first gate metal layer is formed on the first gate insulating layer141. The first gate metal layer may be formed of a multilayer in which metal layers are formed of copper (Cu), a copper alloy, aluminum (Al), an aluminum alloy, molybdenum (Mo), or a molybdenum alloy and are stacked on each other. In addition, the first gate metal layer is patterned by a photolithography process using a second mask. As a result, the first gate metal line (151,152,153, and155a) including the scan line151, the previous scan line152, the light emission control line153, and the first storage electrode155aof the driving gate electrode is formed. In this case, since the second mask is a partial exposure mask, the lateral wall of the switching gate electrode155bthat is the part of the scan line151may be formed to be smooth. Also, the lateral wall of the bypass gate electrode155gthat is the part of the previous scan line152may be formed to be smooth, and the lateral wall of the operation control gate electrode155eand the light emission control gate electrode155fthat are the part of the light emission control line153may be formed to be smooth. The second lateral wall slope angle θ2of the switching gate electrode155bmay be formed to be less than about 70 degrees, and the second lateral wall slope angle θ2of the operation control gate electrode155e, the second lateral wall slope angle θ2of the light emission control gate electrode155f, and the second lateral wall slope angle θ2of the bypass gate electrode155gmay be formed to be about 70 degrees.

In contrast, the lateral wall of the driving gate electrode155a, the lateral wall of the compensation gate electrode155c, and the lateral wall of the initialization gate electrode155dare formed to have the relatively steep slope.

The first lateral wall slope angle θ1of the driving gate electrode155a, the first lateral wall slope angle θ1of the compensation gate electrode155c, and the first lateral wall slope angle θ1of the initialization gate electrode155dmay be formed to be more than about 70 degrees to less than about 90 degrees.

Also, the insulating layer SPL covering the first gate metal line (151,152,153,155a) is formed.

Next, as shown inFIGS. 14 and 15, the insulating layer SPL is wholly etched by the dry etching method. Accordingly, the insulating layer SPL positioned on the lateral wall of the first gate electrode15A including the driving gate electrode155a, the compensation gate electrode155c, and the initialization gate electrode155dhaving the steep slope remains to be the doping control member SP. The insulating layer SPL positioned on the lateral wall of the second gate electrode15B including the switching gate electrode155b, the operation control gate electrode155e, the light emission control gate electrode155f, and the bypass gate electrode155ghaving the smooth slope is removed.

Further, source and drain doping to have a higher doping concentration than that of the channel doping is performed on the semiconductor member130. Exposed areas of the semiconductor member130are source and drain doped except for the parts hidden by the switching gate electrode155b, the compensation gate electrode155c, the initialization gate electrode155d, the operation control gate electrode155e, the light emission control gate electrode. As a result, the source electrode and the drain electrode of each transistor are formed. The channel131of each transistor is formed in the area of the semiconductor130which is hidden and is not doped. That is, the driving channel131a, the switching channel131b, the compensation channel131c, the initialization channel131d, the operation control channel131e, the light emission control channel131f, and the bypass channel131gare simultaneously formed. Also, the lightly doped drain LDD is formed in the semiconductor member of the position corresponding to the doping control members SP is formed.

As described above, by only forming the doping control members SP and the lightly doped drain LDD in the first transistor including the first gate electrode15A, the lightly doped drain LDD may be selectively formed. As such, without the addition of the separate mask, the lightly doped drain LDD is formed in the first transistor and the lightly doped drain LDD may not be formed in the second transistor. Accordingly, the manufacturing process is simplified and the manufacturing cost is reduced.

Next, as shown inFIGS. 10 and 11, the second gate insulating layer142covering the first gate insulating layer141and the first gate metal line (151,152,153, and155a) is formed thereon. The second gate insulating layer142is formed by depositing silicon nitride (SiNx) or silicon oxide (SiOx) on a front surface thereof by a method of plasma enhanced chemical vapor deposition (PECVD) and the like.

Also, the second gate metal layer is formed on the second gate insulating layer142. The second gate metal layer may be formed in a multilayer in which metal layers are made of copper (Cu), a copper alloy, aluminum (Al), an aluminum alloy, molybdenum (Mo), or a molybdenum alloy and are stacked on each other. The second gate metal layer is etched by the photolithography process by using a third mask. As a result, the second gate metal line (157and156) including the storage line157and the second storage electrode156is formed.

Also, the interlayer insulating layer covering the second gate insulating layer142and the second gate metal line (157and156) is formed thereof. Also, the plurality of contact holes61,62,63,64,65,66, and69are simultaneously formed by simultaneously pattering the first gate insulating layer141, the second gate insulating layer142, and the interlayer insulating layer160by a photolithography process using a fourth mask.

Next, a data metal layer is formed on the interlayer insulating layer160. The data metal layer may be formed of a multilayer in which a metal layer including any one of copper, a copper alloy, aluminum, an aluminum alloy, molybdenum, and a molybdenum alloy is stacked. For example, the data metal layer may be formed of triple layers of titanium/aluminum/titanium (Ti/Al/Ti), molybdenum/aluminum/molybdenum (Mo/Al/Mo), or molybdenum/copper/molybdenum (Mo/Cu/Mo).

The data metal layer is patterned by a photolithography process using a fifth mask. Accordingly, a data metal line (171,172,174, and179) including the data line171, the driving voltage line172, the driving connecting member174, and the pixel connecting member179is formed on the interlayer insulating layer160.

Also, the passivation layer180covering the interlayer insulating layer160and the data metal line (171,172,174, and179) is formed and a contact hole81is formed in the passivation layer180by the photolithography process using a sixth mask. Further, a pixel electrode layer is formed on the passivation layer180and is etched by the photolithography process using a seventh mask. Accordingly, the pixel electrode191connected to the pixel connecting member179through the contact hole81is formed on the passivation layer180. Then, the pixel definition layer350covering the pixel electrode191is formed on the protective layer180, and the pixel opening351for exposing a portion of the pixel electrode191is formed in the pixel definition layer350by using an eighth mask. Then, the organic light emission layer370is formed on the pixel electrode191exposed through the pixel opening351of the pixel definition layer350. Also, the common electrode270is formed on the organic emission layer370to complete the organic light emitting diode (OLED). The common electrode270is formed over the entire area including an upper portion of the pixel definition layer350, so that a separate mask is not used.