Substrate mounting table

There is provided a substrate mounting table for use in a plasma-based processing apparatus that performs a plasma-based process on a substrate inside a processing container, which includes a substrate mounting portion having a front surface subjected to a mirroring treatment and on which the substrate is mounted, and an edge portion located around the substrate mounting portion and treated to have an uneven shape.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2017-224738, filed on Nov. 22, 2017, the entire contents of which are incorporated herein by reference.

TECHNICAL FIELD

The present disclosure relates to a substrate mounting table.

BACKGROUND

In manufacturing a semiconductor device, there are sonic cases where a plasma-based process such as a film-forming process, an etching process or the like is performed on a substrate. In such a plasma-based process, for example, inside a processing container in which a pair of parallel flat plate electrodes (upper electrode and lower electrode) are arranged, plasma of a processing gas is generated by mounting a substrate on a stage functioning as the lower electrode and applying high frequency power to one of the electrodes to form a high frequency electric field between the electrodes.

As the stage, a configuration in which a roughened portion having a surface roughness Ra of 2 μm or more and 6 μm or less is formed on a surface on which a substrate is mounted, and a configuration in which a surface is smoothly formed are known.

However, in the configuration in which a roughened portion is formed on a surface on which a substrate is mounted, the substrate electrically floats from the stage so that a potential difference between the substrate and the stage is generated. As a result, arc discharge (arcing) may occur when a high voltage is applied between the upper electrode and the lower electrode. On the other hand, in the configuration in which a surface is smoothly formed, when the plasma-based process is repeatedly performed, reaction products may adhere and accumulate on a portion of the surface of the stage where the substrate is not mounted. As a result, the accumulated reaction products may peel off, which causes particles.

SUMMARY

Some embodiments of the present disclosure provide a substrate mounting table capable of suppressing generation of arcing and particles.

According to one embodiment of the present disclosure, there is provided a substrate mounting table for use in a plasma-based processing apparatus that performs a plasma-based process on a substrate inside a processing container, including: a substrate mounting portion having a front surface subjected to a mirroring treatment and on which the substrate is mounted; and an edge portion located around the substrate mounting portion and treated to have an uneven shape.

DETAILED DESCRIPTION

Hereinafter, modes for carrying out the present disclosure will be described with reference to the drawings. Through the specification and the figures, the same or similar elements and parts are denoted by the same reference numerals, and explanation thereof will not be repeated. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it will be apparent to one of ordinary skill in the art that the present disclosure may be practiced without these specific details. In other instances, well-known methods, procedures, systems, and components have not been described in detail so as not to unnecessarily obscure aspects of the various embodiments.

An example of a plasma-based processing apparatus to which a stage according to an embodiment of the present disclosure can be applied will be described below.FIG. 1is a view showing the overall configuration of the plasma-based processing apparatus according to an embodiment of the present disclosure.

As shown inFIG. 1, the plasma-based processing apparatus1is an apparatus that performs a process of forming a titanium (Ti) film on a semiconductor wafer (hereinafter referred to as “wafer W”) as a substrate, by a plasma CVD method. The plasma-based processing apparatus1includes a substantially cylindrical airtight processing container2. An exhaust chamber21is installed in the central portion of a bottom wall of the processing container2.

The exhaust chamber21has a substantially cylindrical shape that protrudes downward. An exhaust path22is connected to the exhaust chamber21, for example, in a lateral surface of the exhaust chamber21.

An exhaust part24is coupled to the exhaust path22via a pressure regulating part23. The pressure regulating part23includes a pressure regulating valve such as a butterfly valve. The exhaust path22is configured so as to depressurize the interior of the processing container2by the exhaust part24. A transfer port25is formed in a lateral surface of the processing container2. The transfer port25is configured to be opened and closed by a gate valve26. The wafer W is transferred between the processing container2and a transfer chamber (not shown) via the transfer port25.

A stage3which is a substrate mounting table for holding the wafer W in a substantially horizontal posture, is installed inside the processing container2. The stage3is formed in a substantially circular shape in a plan view, and is supported by a support member31. A circular recess32for mounting the wafer W having a diameter of, e.g., 300 mm thereon is formed in the surface of the stage3. The recess32has an inner diameter slightly larger (for example, by about 1 mm to 4 mm) than the diameter of the wafer W. The depth of the recess32is substantially the same as the thickness of the wafer W, for example. The stage3is made of, for example, a ceramic material such as aluminum nitride (AlN). Further, the stage3may be formed of a metal material such as nickel (Ni). Instead of the recess32, a guide ring for guiding the wafer W may be installed in a peripheral edge portion of the surface of the stage3.

For example, a grounded lower electrode33is buried in the stage3. A heating mechanism34is buried under the lower electrode33. The heating mechanism34heats the wafer W mounted on the stage3to a set temperature (for example, a temperature of 350 to 700 degrees C.) with power fed from a power supply (not shown) based on a control signal provided from a control part100. In a case where the stage3is entirely made of metal, since the entire stage3functions as a lower electrode, it is not necessary to bury the lower electrode33in the stage3. The stage3is provided with a plurality of lift pins41(for example, three lift pins) for holding and moving up/down the wafer W mounted on the stage3. The lift pins41may be made of, for example, ceramics such as alumina (Al2O3), quartz or the like. Lower ends of the lift pins41are attached to a support plate42. The support plate42is coupled to an elevating mechanism44installed outside the processing container2via an elevating shaft43.

For example, the elevating mechanism44is installed below the exhaust chamber21. A bellows45is installed between the elevating mechanism44and an opening211formed in a lower surface of the exhaust chamber21. The elevating shaft43passes through the opening211. The support plate42may have a shape capable of moving up and down without interfering with the support member31of the stage3. The lift pins41are configured to be moved up and down between above the surface of the stage3and below the surface of the stage3by means of the elevating mechanism44.

A gas supply part5is installed in a ceiling wall27of the processing container2with an insulating member28interposed between the gas supply part5and the ceiling wall27. The gas supply part5constitutes an upper electrode and faces the lower electrode33. A high frequency power supply51is coupled to the gas supply part5via a matching device511. By supplying high frequency power from the high frequency power supply51to the upper electrode (the gas supply part5), a high frequency electric field is generated between the upper electrode (the gas supply part5) and the lower electrode33. The gas supply part5includes a hollow gas supply chamber52. For example, a plurality of holes53, for dispersedly supplying a processing gas into the processing container2therethrough, is evenly formed in a lower surface of the gas supply chamber52. A heating mechanism54is buried above the gas supply chamber52in the gas supply part5. The heating mechanism54is heated to a set temperature with power fed from a power supply (not shown) based on a control signal provided from the control part100.

A gas supply path6is formed in the gas supply chamber52. The gas supply path6is in communication with the gas supply chamber52. A gas source61, a gas source62and a gas source63are coupled to the upstream side of the gas supply path6via a gas line L61, a gas line L62and a gas line L63, respectively. In one embodiment, the gas source61is a supply source of an inert gas such as an Ar gas, a N2gas or the like. The gas source62is a supply source of a reaction gas such as a H2gas, an NH3gas or the like. The gas source62may also be used as a supply source of an inert gas (an Ar gas, a N2gas or the like) for purging. The gas source63is a supply source of a reaction gas such as a TiCl4gas or the like. The gas source63may also be used as a supply source of an inert gas (an Ar gas, a N2gas or the like) for purging. The gas line L61and the gas line L62are connected to each other between a valve V1in the gas line L61and the gas supply path6, and between a valve V2in the gas line L62and the gas supply path6.

The gas source61is coupled to the gas supply path6via the gas line L61. In the gas line L61, a pressure regulating valve V5, a valve V4, a pressure boosting part TK and the valve V1are disposed in this order from the side of the gas source61. The pressure boosting part TK is interposed between the valve V1and the valve V4in the gas line L61. The valve V4is interposed between the pressure regulating valve V5and the pressure boosting part TK. The pressure boosting part TK includes a gas storage tank TKT. With the valve V1closed and the valve V4opened, the gas storage tank TKT of the pressure boosting part TK is configured to store a gas supplied from the gas source61via the gas line L61and the valve V4and to boost an internal gas pressure of the gas storage tank TKT. The pressure boosting part TK includes a pressure gauge TKP. The pressure gauge TKP measures the internal gas pressure of the gas storage tank TKT included in the pressure boosting part TK and transmits the measurement result to the control part100. The valve V1is interposed between the pressure boosting part TK and the gas supply path6.

The gas source62is coupled to the gas supply path6via the gas line L62. In the gas line L62, a valve V6, a mass flow controller MF1and the valve V2are disposed in this order from the side of the gas source62.

The gas source63is coupled to the gas supply path6via the gas line L63. In the gas line L63, a valve V7, a mass flow controller MF2and a valve V3are disposed in this order from the side of the gas source63.

The plasma-based processing apparatus1includes the control part100and a storage part101. The control part100includes a CPU, a RAM, a ROM and the like (all not shown) and controls the overall operation of the plasma-based processing apparatus1, for example, by causing the CPU to execute a computer program stored in the ROM or the storage part101. Specifically, the control part100executes a plasma-based process or the like on the wafer W by causing the CPU to execute a control program stored in the storage part101to control the operation of each component of the plasma-based processing apparatus1.

The stage3, according to the embodiment of the present disclosure, will be described. The stage3, according to the embodiment of the present disclosure, for example, functions as a mounting table for mounting thereon the wafer W when performing a predetermined plasma-based process on the wafer W inside the processing container2of the above-described plasma-based processing apparatus1.FIG. 2is a schematic sectional view of the stage3according to the embodiment of the present disclosure.

The stage3includes a substrate mounting portion35, an edge portion36, a tapered portion37and a bank portion38. The substrate mounting portion35, the edge portion36, the tapered portion37and the bank portion38are formed in this order from the center portion of the stage3toward the outer peripheral portion thereof.

The substrate mounting portion35is formed at the central portion of the bottom surface of the recess32. The substrate mounting portion35may have substantially the same shape as the wafer W and may have, for example, a circular shape having a diameter of 298 mm to 300 mm. A surface of the substrate mounting portion35has been subjected to a minoring treatment to become a mirror surface. This mirror surface means that the arithmetic average roughness (hereinafter referred to as “surface roughness Ra”) defined in JISB0601: 2013 is 0.4 μm or less. Since the substrate mounting portion35has been subjected to the mirroring treatment, a distance between the front surface of the stage3and the back surface of the wafer W is narrowed. As a result, it is possible to prevent the arc discharge (arcing) from occurring between the front surface of the stage3and the back surface of the water W.

The edge portion36is formed around the substrate mounting portion35so as to surround the substrate mounting portion35. The edge portion36may have, for example, an annular shape. The inner diameter of the edge portion36may be substantially the same as the diameter of the wafer W and may be, for example, 298 mm to 300 mm. The outer diameter of the edge portion36may be slightly larger than the diameter of the wafer W and may be, for example, 301 mm to 303 mm. The edge portion36is treated to have an uneven shape of a larger surface roughness Ra than the substrate mounting portion35. Since the edge portion36is treated to have an uneven shape, a frictional force generated between the front surface of the edge portion36and the back surface of the wafer W is larger than that generated between the front surface of the substrate mounting portion35and the back surface of the wafer W. This restricts the movement of the wafer W from the substrate mounting portion35to the edge portion36. Thus, a positional deviation of the wafer W relative to the stage3can be suppressed. Further, since the edge portion36is treated to have an uneven shape, the adhesion of a film formed on the edge portion36by the plasma-based process to the stage3is improved. Therefore, the film formed on the edge portion36is prevented from being peeled off. As a result, it is possible to suppress generation of particles due to the peeling-off of the film. The surface roughness Ra of the edge portion36may fall within a range of 1 μm to 10 μm, in particular, from the viewpoint of suppressing the peeling-off of the film formed on the edge portion36.

The tapered portion37is formed on an inner surface of the recess32. In other words, the tapered portion37is formed around the edge portion36so as to surround the edge portion36. The tapered portion37prevents the wafer W from jumping out from the recess32. The tapered portion37is formed between the bottom surface of the recess32and the bank portion38. The tapered portion37is treated to have an uneven shape of a larger surface roughness Ra than the substrate mounting portion35. Since the tapered portion37is treated to have an uneven shape, the adhesion of a film formed on the tapered portion37by the plasma-based process to the stage3is improved. Therefore, the film formed on the tapered portion37is prevented from being peeled off. As a result, it is possible to suppress generation of particles due to the peeling-off of the film. The surface roughness Ra of the tapered portion37may be smaller than the surface roughness Ra of the edge portion36and may be, for example, 2 μm, from the viewpoint of easy surface treatment.

The bank portion38is formed around the tapered portion37so as to surround the tapered portion37. In other words, the bank portion38is formed on a peripheral portion of the recess32. For example, the bank portion38is substantially flush with the front surface of the wafer W mounted on the substrate mounting portion35. The bank portion38is treated to have an uneven shape of a surface roughness Ra larger than the substrate mounting portion35. Since the bank portion38is treated to have an uneven shape, the adhesion of a film formed on the bank portion38by the plasma-based process to the stage3is improved. Therefore, the film formed on the bank portion38is prevented from being peeled off. As a result, it is possible to suppress generation of particles due to the peeling-off of the film. The surface roughness Ra of the bank portion38may be the same as the surface roughness Ra of the edge portion36and may be, for example, 1 μm to 10 μm, from the viewpoint of easy surface treatment.

The effects achieved when using the stage3according to the embodiment of the present disclosure will be described. In the following description, stages3all made of Ni are used.

First, the plasma-based processing apparatus1including the stage3according to an example in which the substrate mounting portion35, the edge portion36, the tapered portion37and the bank portion38respectively have the surface roughness Ra of 0.02 μm (mirror surface), 10 μm, 2 μm and 10 μm was used to perform the plasma-based process on a wafer W. In addition, a plasma-based processing apparatus including a stage according to a comparative example in which the substrate mounting portion35, the edge portion36, the tapered portion37and the bank portion38respectively have the surface roughness Ra of 10 μm, 10 μm, 0.4 μm and 10 μm is used to perform the plasma-based process on a wafer W. Conditions of the plasma-based process according to the example and the comparative example are as follows.

Flow rate of Ar gas: 100 to 10,000 mL/min (sccm)

High frequency power: 10 to 3,000 W and 100 kHz to 100 MHz

FIG. 3is a view for explaining a relationship between a stage shape and an arcing occurrence number. The upper left ofFIG. 3shows a schematic shape of the stage3according to the example and the lower left ofFIG. 3shows the number of occurrences of arcing between the front surface of the stage3and the back surface of the wafer W after performing the plasma-based process on the wafer W mounted on the stage3according to the example. The upper right ofFIG. 3shows a schematic shape of the stage according to the comparative example and the lower right ofFIG. 3shows the position of occurrence and the number of occurrences of arcing between the front surface of the stage and the back surface of the wafer W after performing the plasma-based process on the wafer W mounted on the stage according to the comparative example. In the lower left and the lower right ofFIG. 3, “No. 1”, “No. 6”, “No. 13”, “No. 18” and “No. 24” represent results of 1st, 6th, 13th, 18th and 24th Runs of 25 Runs of the wafer W subjected to the plasma-based process, respectively. In the lower right ofFIG. 3, each plot shows the position of occurrence of arcing.

As shown in the lower left ofFIG. 3, in the case of using the stage3according to the example, no arcing occurs between the front surface of the stage3and the back surface of the wafer W in all the wafers W. On the other hand, as shown in the lower right ofFIG. 3, in the case of using the stage according to the comparative example, arcing occurs between the front surface of the stage and the back surface of the wafer W in most of the wafers W. Specifically, in the wafer W of “No. 1”, “No. 6”, “No. 13”, “No. 18” and “No. 24”, arcing occurs at 6, 24, 1, 0 and 11 spots, respectively.

As described above, by using the stage3according to the example, it is confirmed that the occurrence of arcing between the front surface of the stage3and the back surface of the wafers W can be suppressed as compared with the case of using the stage according to the comparative example.

Next, the plasma-based processing apparatus1including the stage3according to an example in which the substrate mounting portion35, the edge portion36, the tapered portion37and the bank portion38respectively have the surface roughness Ra of 0.02 μm, 10 μm, 2 μm and 10 μm was used to perform the plasma-based process on a wafer W. In addition, a plasma-based processing apparatus including a stage according to a comparative example in which the substrate mounting portion35, the edge portion36, the tapered portion37and the bank portion38respectively have the surface roughness Ra of 10 μm, 10 μm, 0.4 μm and 10 μm was used to perform the plasma-based process on a wafer W. Conditions of the plasma-based process according to the example and the comparative example are similar to those described in the above.

FIG. 4is a view for explaining a relationship between a stage shape and particles. The upper left ofFIG. 4shows a schematic shape of the stage3according to the example and the lower left ofFIG. 4shows a distribution of particles adhering to the front surface of the wafer W after performing the plasma-based process on the wafer W mounted on the stage3according to the example. The upper right ofFIG. 4shows a schematic shape of the stage according to the comparative example and the lower right ofFIG. 4shows a distribution of particles adhering to the front surface of the water W after performing the plasma-based process on the wafer W mounted on the stage according to the comparative example. In the lower left and the lower right ofFIG. 4, each plot shows particles adhering to the front surface of the wafer W.

As shown in the lower left ofFIG. 4, in the case of using the stage3according to the example, five particles adhered to the front surface of the wafer W. On the other hand, as shown in the lower right ofFIG. 4, in the case of using the stage according to the comparative example, a large number of particles adhered to the front surface of the wafer W.

As described above, by using the stage3according to the example, it is confirmed that particles adhering to the front surface of the wafer W which has been subjected to the plasma-based process can be reduced compared with the case of using the stage according to the comparative example.

Next, the plasma-based processing apparatus1including the stage3according to an example in which the substrate mounting portion35, the edge portion36, the tapered portion37and the bank portion38respectively have the surface roughness Ra of 0.02 μm, 10 μm, 2 μm and 10 μm was used to perform the plasma-based process on a wafer W. In addition, a plasma-based processing apparatus including a stage according to a comparative example in which the substrate mounting portion35, the edge portion36, the tapered portion37and the bank portion38respectively have the surface roughness Ra of 0.02 μm, 0.02 μm, 0.4 μm and 10 μm was used to perform the plasma-based process on a wafer W. Conditions of the plasma-based process according to the example and the comparative example are similar to those described in the above.

FIG. 5is a view for explaining a relationship between a stage shape and a wafer positional deviation amount. The upper left ofFIG. 5shows a schematic shape of the stage3according to the example and the lower left ofFIG. 5shows a positional deviation amount of the wafer W relative to the stage3according to the example. The upper right ofFIG. 5shows a schematic shape of the stage according to the comparative example and the lower right ofFIG. 5shows a positional deviation amount of the wafer W relative to the stage according to the comparative example. In the lower left and the lower right ofFIG. 5, the abscissa and the ordinate represent a deviation amount (μm) in the X direction and a deviation amount (μm) in the Y direction from the center of the stage in the plane of the stage, respectively. In addition, in the lower left and the lower right ofFIG. 5, each plot shows a movement amount (deviation amount) of a position after each of a plurality of wafers W was subjected to the plasma-based process relative to a position before each of the plurality of wafers W is subjected to the plasma-based process.

As shown inFIG. 5, by using the stage3according to the example, it is confirmed that the positional deviation of the wafer W relative to the stage3can be suppressed as compared with the case of using the stage of the comparative example.

As described above, the stage3according to the embodiment of the present disclosure includes the substrate mounting portion35subjected to a mirroring treatment surface on which the wafer W is mounted. As a result, the distance between the front surface of the stage3and the back surface of the water W is narrowed. It is therefore possible to prevent arcing from occurring between the front surface of the stage3and the back surface of the wafer W.

Further, the stage3includes the edge portion36which is located around the substrate mounting portion35and is treated to have an uneven shape. As a result, the adhesion of a film formed on the edge portion36by the plasma-based process to the stage3is improved. Therefore, it is possible to suppress the film formed on the edge portion36from being peeled off and adhering as particles to the front surface of the wafer W.

According to the present disclosure in some embodiments, it is possible to provide a substrate mounting table capable of suppressing generation of arcing and particles.