Power management for peripheral component interconnect

A new peripheral component interconnect express (PCIe) link state can enhance power saving capabilities of a PCIe link operating in a flow control unit (FLIT) mode. A device can operate a data link with a host in a FLIT mode using fixed-sized packets, the data link being in a partial width link state (PLS) in which a first set of lanes of the data link are in an electrical idle state and a second set of lanes of the data link are in an active state available for data traffic with the host. The device can transition one or more lines of the second set of lanes from the PLS to a partial width standby link state (PSLS) in which the one or more lines of the second set of lanes are in a standby state that has lower power consumption than the active state.

TECHNICAL FIELD

The technology discussed below relates generally to peripheral component interconnect express (PCIe) devices, and more particularly, to techniques for managing link power consumption of PCIe devices.

INTRODUCTION

High-speed interfaces are frequently used between circuits and components of mobile wireless devices and other complex systems. For example, certain devices may include processing, communications, storage, and/or display devices that interact with one another through one or more high-speed interfaces. Some of these devices, including synchronous dynamic random-access memory (SDRAM), may be capable of providing or consuming data and control information at processor clock rates. Other devices, e.g., display controllers, may use variable amounts of data at relatively low video refresh rates.

The peripheral component interconnect express (PCIe) standard is a high-speed interface that supports a high-speed data link capable of transmitting data at multiple gigabits per second. The PCIe interface also has multiple standby modes for when a link is inactive. PCIe can provide lower latency and higher data transfer rates compared to parallel buses. PCIe can be used for communication between a wide range of different devices. Typically, one device, e.g., a processor or hub, acts as a host, that communicates with multiple devices, referred to as endpoints, through PCIe links (data links) The peripheral devices or components may include graphics adapter cards, network interface cards (NICs), storage accelerator devices, mass storage devices, Input/Output (I/O) interfaces, and other high-performance peripherals.

A connection between any two PCIe devices is referred to as a link A PCIe link is built around a duplex, serial (1-bit), differential, point-to-point connection referred to as a lane. With PCIe, data is transferred over two signal pairs: two lines (wires, circuit board traces, etc.) for transmitting and two lines for receiving. The transmitting and receiving pairs are separate differential pairs for a total of four data lines per lane. The link encompasses a set of lanes, and each lane is capable of sending and receiving data packets simultaneously between the host and the endpoint. A PCIe link, as currently defined, can scale from one to 32 separate lanes. Usual deployments have 1, 2, 4, 8, 12, 16, or 32 lanes, which may be labeled as x1, x2, x4, x8, x12, x16, or x32, respectively, where the number is effectively the number of lanes. In one example, a PCIe x1 implementation has four lines to connect one wire-pair lane in each direction while a PCIe x16 implementation has 16 times that amount for 16 lanes or 64 lines.

There are various link power management states such as L0, L0s, and L1 that a PCIe physical link can enter and exit in response to state power management activities. These link power management states allow PCIe devices to use power more efficiently depending on the traffic condition or state of the PCIe link.

BRIEF SUMMARY

The following presents a summary of one or more implementations in order to provide a basic understanding of such implementations. This summary is not an extensive overview of all contemplated implementations and is intended to neither identify key or critical elements of all implementations nor delineate the scope of any or all implementations. Its sole purpose is to present some concepts of one or more implementations in a simplified form as a prelude to the more detailed description that is presented later.

In one example, a method of operating an endpoint for data communication is disclosed. The method includes operating a data link with a host in a flow control unit (FLIT) mode using fixed-sized packets, the data link being in a partial width link state (PLS) in which a first set of lanes of the data link are in an electrical idle state and a second set of lanes of the data link are in an active state available for data traffic with the host. The method further includes transitioning one or more lines of the data link second set of lanes from the PLS to a partial width standby link state (PSLS) in which the one or more lines of the second set of lanes are in a standby state that has lower power consumption than the active state.

In one example, an endpoint for a peripheral component interconnect express (PCIe) link is provided. The endpoint includes an interface circuit configured to provide an interface with the PCIe link connected with a host. The endpoint further includes a controller configured to operate the PCIe link in a flow control unit (FLIT) mode using fixed-sized packets. The PCIe link is in a partial width link state (PLS) in which a first set of lanes of the PCIe link are in an electrical idle state and a second set of lanes of the PCIe link are in an active state available for data traffic with host. The controller is further configured to transition one or more lines of the second set of lanes PCIe link from the PLS to a partial width standby link state (PSLS) in which the one or more of the second set of lanes are in a standby state that has lower power consumption than the active state.

In one example, a host for a peripheral component interconnect express (PCIe) link is provided. The host includes an interface circuit configured to provide an interface with the PCIe link connected with an endpoint. The host further includes a controller configured to operate the PCIe link in a flow control unit (FLIT) mode using fixed-sized packets. The PCIe link is in a partial width link state (PLS) in which a first set of lanes of the PCIe link are in an electrical idle state and a second set of lanes of the PCIe link are in an active state available for data traffic with the endpoint. The controller is further configured to transition one or more lines of the second set of lanes PCIe link from the PLS to a partial width standby link state (PSLS) in which the one or more of the second set of lanes are in a standby state that has lower power consumption than the active state.

To the accomplishment of the foregoing and related ends, the one or more implementations include the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative aspects of the one or more implementations. These aspects are indicative, however, of but a few of the various ways in which the principles of various implementations may be employed and the described implementations are intended to include all such aspects and their equivalents.

DETAILED DESCRIPTION

The recent peripheral component interconnect express (PCIe) specification (e.g., PCIe 6.0) can use Flow Control Unit (FLIT) encoding to improve the latency and efficiency of a PCIe link. When a PCIe link is in a FLIT mode, error correction operates on fixed-sized packets (flits). At the physical layer of a PCIe link, units of data transfer are flits. Further, PCIe 6.0 introduces a partial width link state (L0p) that is available in FLIT mode. In L0p, some lanes (i.e., partial width) may be in an electrical idle mode. When a lane is electrically idle, the corresponding line driver can be set in a static or high impedance state, and the differential voltage of the lane can be fixed (e.g., 0 volt). In some aspects, the standby link state L0s is not available in FLIT mode. Therefore, the L1 state becomes the power-saving state with the least resume latency (e.g., in order of 64 us) for L0p. In FLIT mode, the transition to a power-saving state L1 from L0p is based on triggering of an L1 state inactivity timer. However, for unidirectional transfers (i.e., only receive (RX) or only transmit (TX) lines are engaged), both the TX as well as RX lines are kept in the active L0p state because both devices connected by a PCIe link (e.g., a host and an endpoint) need to transition to L1. Since L0s is not available in FLIT mode, no power can be saved by transitioning the transmitter (e.g., a host or endpoint) alone to a low power state, without any negotiation or handshake sequence that is needed to transition the device to the other available low power state (e.g., L1).

In an exemplary handshake sequence, the physical layer (PHY) of a PCIe device (e.g., an endpoint) can detect a certain idle time period (e.g., based on a PCIe inactivity timer) on a PCIe link. The idle time period can be implementation specific (e.g., 7 microseconds (tis) to 10 μs). Then, the device blocks new outbound PCIe transactions (e.g., PCIe traffic) to the system (e.g., host). The PCIe device can keep sending a PM_Active_State_Request_L1 data link layer packet (DLLP) to the system side until the device receives a PM_Request_ACK from the system side. When the system receives the PM_Active_State_Request_L1 DLLP, the system blocks new transactions to the device, and keeps sending the PM_Request_ACK until the system receives an electrical idle ordered set. When the device receives the PM_Request_ACK, the device sends an electrical idle ordered set, and puts the device's transmitter into an electrical idle state. When the system receives the electrical idle ordered set, the system puts its transmitter into electrical idle. At this point, the PCIe link is in the L1 state. Either the system or device can initiate an exit from the L1 state.

Aspects of the disclosure provide techniques for implementing a new PCIe link state to enhance power saving capabilities of a PCIe link in FLIT mode. The techniques enable a host and an endpoint to enter the new link state (referred to as L0ps in this disclosure) independently from L0p in FLIT mode. In some aspects, a PCIe link in L0p state can quickly enter (e.g., based on an L0ps inactivity timer) and recover from the L0ps state without going through a recovery state. In some aspects, a lane can enter the L0ps state after receiving an electrical idle ordered set (EIOS) for the PCIe lane. In some aspects, when a lane exits from the L0ps state back to the L0p state, the lane re-establishes bit lock, symbol lock, or block alignment, and performs lane-to-lane de-skew. While the lanes of a multi-lane PCIe link can transmit data symbols simultaneously, lane-to-lane skew occurs when the data symbols of different lanes arrive at the receiver at different times The arrival time difference is referred to as lane-to-lane skew. For example, a device exiting L0ps can de-skew the lane by sending exit patterns on the idle lanes to train and de-skew them. As one example, an exit pattern can include an electrical idle exit ordered set (EIEOS) and a fast training sequence (FTS).

In some aspects, a TX and RX line pair on a PCIe lane can switch to the L0ps state independently (e.g., not simultaneously). In some aspects, the TX line and RX line can be in the L0ps state independently based on separate inactivity timeouts, without any handshaking between the host and endpoint.

FIG.1is a block diagram of an exemplary computing architecture using PCIe interfaces. The computing architecture100operates using multiple high-speed PCIe interface serial links A PCIe interface may be characterized as an apparatus comprising a point-to-point topology, where separate serial links connect each device to a host, which can be referred to as a root complex104. In the computing architecture100, the root complex104couples a processor102to memory devices, e.g., the memory subsystem108, and a PCIe switch circuit106. In some instances, the PCIe switch circuit106includes cascaded switch devices. One or more PCIe endpoint devices110may be coupled directly to the root complex104, while other PCIe endpoint devices112-1,112-2, . . .112-N may be coupled to the root complex104through the PCIe switch circuit106. The root complex104may be coupled to the processor102using a proprietary local bus interface or a standards defined local bus interface. The root complex104may control configuration and data transactions through the PCIe interfaces and may generate transaction requests for the processor102. In some examples, the root complex104is implemented in the same Integrated Circuit (IC) device that includes the processor102. The root complex104can support multiple PCIe ports.

The root complex104may control communication between the processor102and the memory subsystem108which is one example of an endpoint. The root complex104(host) also controls communication between the processor102and other PCIe endpoint devices110,112-1,112-2, . . .112-N. The PCIe interface may support full-duplex communication between any two endpoints, with no inherent limitation on concurrent access across multiple endpoints. Data packets may carry information through any PCIe link In a multi-lane PCIe link, packet data may be striped across multiple lanes. The number of lanes in the multi-lane link may be negotiated during device initialization and may be different for different endpoints.

When one or both traffic directions of the lanes of the PCIe links are being underutilized by low bandwidth applications that could be adequately served by fewer lanes, then the root complex104and endpoint may operate the link with more or fewer transmit lines and receive lines in one or both directions. In some aspects, a host (e.g., root complex104) and an endpoint can operate in FLIT mode and change between partial width link states (e.g., L0p and L0ps) based on the traffic condition of the link.

In some aspects, the computing architecture100may be implemented based on the PCIe M.2 Specification. The M.2 form factor can be used for mobile adapters. The M.2 enables expansion, contraction, and higher integration of functions onto a single form factor module solution. For example, any of the PCIe endpoints described above relation toFIG.1can be implemented as an M.2 adapter, and the root complex104can be implemented as an M.2 platform.

FIG.2is a block diagram of an exemplary PCIe system in which aspects of the present disclosure may be implemented. The system205includes a host system210and an endpoint device system250, which may be the same as the host and endpoints ofFIG.1. For example, the host system210may be a PCIe M.2 platform, and the endpoint device system250may be an M.2 adapter. The host system210may be integrated on a first chip (e.g., system on a chip or SoC), and the endpoint device system250may be integrated on a second chip. Alternatively, the host system and/or endpoint device system may be integrated in first and second packages, e.g., SiP, first and second system boards with multiple chips, or in other hardware or any combination. In this example, the host system210and the endpoint device system250are coupled by a PCIe link285.

The host system210includes one or more host clients214. Each of the one or more host clients214may be implemented on a processor executing software that performs the functions of the host clients214discussed herein. For the example of more than one host client, the host clients may be implemented on the same processor or different processors. The host system210also includes a host controller212, which may perform root complex functions. The host controller212may be implemented on a processor executing software that performs the functions of the host controller212discussed herein.

The host system210includes a PCIe interface circuit216, a system bus interface215, and a host system memory240. The system bus interface215may interface the one or more host clients214with the host controller212, and interface each of the one or more host clients214and the host controller212with the PCIe interface circuit216and the host system memory240. The PCIe interface circuit216provides the host system210with an interface to the PCIe link285. In this regard, the PCIe interface circuit216is configured to transmit data (e.g., from the host clients214) to the endpoint device system250over the PCIe link285and receive data from the endpoint device system250via the PCIe link285. The PCIe interface circuit216includes a PCIe controller218, a physical interface for PCI Express (PIPE) interface220, a physical (PHY) transmit (TX) block222, a clock generator224, and a PHY receive (RX) block226. The PIPE interface220provides a parallel interface between the PCIe controller218and the PHY TX block222and the PHY RX block226. The PCIe controller218(which may be implemented in hardware) may be configured to perform transaction layer, data link layer, and control flow functions specified in the PCIe specification, as described further below.

The host system210also includes an oscillator (e.g., crystal oscillator or “XO”)230configured to generate a reference clock signal232. The reference clock signal232may have a frequency of 19.2 MHz in one example, but is not limited to such frequency. The reference clock signal232is input to the clock generator224which generates multiple clock signals based on the reference clock signal232. In this regard, the clock generator224may include a phase locked loop (PLL) or multiple PLLs, in which each PLL generates a respective one of the multiple clock signals by multiplying up the frequency of the reference clock signal232.

The endpoint device system250includes one or more device clients254. Each device client254may be implemented on a processor executing software that performs the functions of the device client254discussed herein. For the example of more than one device client254, the device clients254may be implemented on the same processor or different processors. The endpoint device system250also includes a device controller252. The device controller252may be configured to receive bandwidth request(s) from one or more device clients, and determine whether to change the number of transmit lines or the number of receive lines based on bandwidth requests. The device controller252may be implemented on a processor executing software that performs the functions of the device controller.

The endpoint device system250includes a PCIe interface circuit260, a system bus interface256, and endpoint system memory274. The system bus interface256may interface the one or more device clients254with the device controller252, and interface each of the one or more device clients254and device controllers252with the PCIe interface circuit260and the endpoint system memory274. The PCIe interface circuit260provides the endpoint device system250with an interface to the PCIe link285. In this regard, the PCIe interface circuit260is configured to transmit data (e.g., from the device client254) to the host system210(also referred to as the host device) over the PCIe link285and receive data from the host system210via the PCIe link285. The PCIe interface circuit260includes a PCIe controller262, a PIPE interface264, a PHY TX block266, a PHY RX block270, and a clock generator268. The PIPE interface264provides a parallel interface between the PCIe controller262and the PHY TX block266and the PHY RX block270. The PCIe controller262(which may be implemented in hardware) may be configured to perform transaction layer, data link layer, and control flow functions.

The host system memory240and the endpoint system memory274at the endpoint may be configured to contain registers for the status of each transmit line and receive line of the PCIe link285. The transmit lines may be configured as differential transmit line pairs and the receive lines may be configured as differential receive line pairs.

The endpoint device system250also includes an oscillator (e.g., crystal oscillator)272configured to generate a stable reference clock signal273for the endpoint system memory274. In the example inFIG.2, the clock generator224at the host system210is configured to generate a stable reference clock signal273, which is forwarded to the endpoint device system250via a differential clock line288by the PHY RX block226. At the endpoint device system250, the PHY RX block270receives the endpoint (EP) reference clock signal on the differential clock line288, and forwards the EP reference clock signal to the clock generator268. The EP reference clock signal may have a frequency of 100 MHz, but is not limited to such frequency. The clock generator268can be configured to generate multiple clock signals based on the EP reference clock signal from the differential clock line288, as discussed further below. In this regard, the clock generator268may include multiple phase-locked loops (PLLs), in which each PLL generates a respective one of the multiple clock signals by multiplying up the frequency of the EP reference clock signal.

The system205also includes a power management integrated circuit (PMIC)290coupled to a power supply292e.g., mains voltage, a battery, or other power source. The PMIC290is configured to convert the voltage of the power supply292into multiple supply voltages (e.g., using switch regulators, linear regulators, or any combination thereof). In this example, the PMIC290generates voltages242for the oscillator230, voltages244for the PCIe controller218, and voltages246for the PHY TX block222, the PHY RX block226, and the clock generator224. The voltages242,244, and246may be programmable, in which the PMIC290is configured to set the voltage levels (corners) of the voltages242,244, and246according to instructions (e.g., from the host controller212).

The PMIC290also generates a voltage280for the oscillator272, a voltage278for the PCIe controller262, and a voltage276for the PHY TX block266, the PHY RX block270, and the clock generator268. The voltages280,278, and276may be programmable, in which the PMIC290is configured to set the voltage levels (corners) of the voltages280,278, and276according to instructions (e.g., from the device controller252). The PMIC290may be implemented on one or more chips. Although the PMIC290is shown as one PMIC inFIG.2, it is to be appreciated that the PMIC290may be implemented by two or more PMICs. For example, the PMIC290may include a first PMIC for generating voltages242,244, and246and a second PMIC for generating voltages280,278, and276. In this example, the first and second PMICs may both be coupled to the same power supply292or to different power supplies.

In operation, the PCIe interface circuit216on the host system210may transmit data from the one or more host clients214to the endpoint device system250via the PCIe link285. The data from the one or more host clients214may be directed to the PCIe interface circuit216according to a PCIe map set up by the host controller212during initial configuration, sometimes referred to as Link Initialization, when the host controller negotiates bandwidth for the link. At the PCIe interface circuit216, the PCIe controller218may perform transaction layer and data link layer functions on the data e.g., packetizing the data, generating error correction codes to be transmitted with the data, etc.

The PCIe controller218outputs the processed data to the PHY TX block222via the PIPE interface220. The processed data includes the data from the one or more host clients214as well as overhead data (e.g., packet header, error correction code, etc.). In one example, the clock generator224may generate a clock234for an appropriate data rate or transfer rate based on the reference clock signal232, and input the clock234to the PCIe controller218to time operations of the PCIe controller218. In this example, the PIPE interface220may include a 22-bit parallel bus that transfers 22-bits of data to the PHY TX block in parallel for each cycle of the clock234. At 250 MHz this translates to a transfer rate of approximately 8 GT/s.

The PHY TX block222serializes the parallel data from the PCIe controller218and drives the PCIe link285with the serialized data. In this regard, the PHY TX block222may include one or more serializers and one or more drivers. The clock generator224may generate a high-frequency clock for the one or more serializers based on the reference clock signal232.

At the endpoint device system250, the PHY RX block270receives the serialized data via the PCIe link285, and deserializes the received data into parallel data. In this regard, the PHY RX block270may include one or more receivers and one or more deserializers. The clock generator268may generate a high-frequency clock for the one or more deserializers based on the EP reference clock signal. The PHY RX block270transfers the deserialized data to the PCIe controller262via the PIPE interface264. The PCIe controller262may recover the data from the one or more host clients214from the deserialized data and forward the recovered data to the one or more device clients254.

On the endpoint device system250, the PCIe interface circuit260may transmit data from the one or more device clients254to the host system memory240via the PCIe link285. In this regard, the PCIe controller262at the PCIe interface circuit260may perform transaction layer and data link layer functions on the data e.g., packetizing the data, generating error correction codes to be transmitted with the data, etc. The PCIe controller262outputs the processed data to the PHY TX block266via the PIPE interface264. The processed data includes the data from the one or more device clients254as well as overhead data (e.g., packet header, error correction code, etc.). In one example, the clock generator268may generate a clock based on the EP reference clock through a differential clock line288, and input the clock to the PCIe controller262to control time operations of the PCIe controller262.

The PHY TX block266serializes the parallel data from the PCIe controller262and drives the PCIe link285with the serialized data. In this regard, the PHY TX block266may include one or more serializers and one or more drivers. The clock generator268may generate a high-frequency clock for the one or more serializers based on the EP reference clock signal.

At the host system210, the PHY RX block226receives the serialized data via the PCIe link285, and deserializes the received data into parallel data. In this regard, the PHY RX block226may include one or more receivers and one or more deserializers. The clock generator224may generate a high-frequency clock for the one or more deserializers based on the reference clock signal232. The PHY RX block226transfers the deserialized data to the PCIe controller218via the PIPE interface220. The PCIe controller218may recover the data from the one or more device clients254from the deserialized data and forward the recovered data to the one or more host clients214.

In some aspects, the host system210and endpoint system250can operate the PCIe link285in FLIT mode and switch the link285between a partial width link state (e.g., L0p) and a standby state (e.g., L0ps) in FLIT mode without going through a recovery state.

FIG.3is a diagram of exemplary lanes in a link385that may be used in the system ofFIG.1andFIG.2. For example, the link385may be implemented as the PCIe link285ofFIG.2. In this example, the link385includes multiple lanes310-1to310-n, in which each lane includes a respective first differential line pair312-1to312-nfor sending data from the host system210to the endpoint device system250, and a respective second differential line pair315-1to315-nfor sending data from the endpoint device system to the host system210. From the perspective of the host system, the first lane310-1is dual simplex, with a first differential line pair312-1as transmit lines and a second differential line pair315-1as receive lines. From the perspective of the endpoint device system, the first lane310-1has receive lines and transmit lines. The first differential line pairs312-1to312-nand the second differential line pairs315-1to315-nmay be implemented with metal traces on a substrate (e.g., printed circuit board), in which the host system may be integrated on a first chip mounted on the substrate, and the endpoint device is integrated on a second chip mounted on the substrate. Alternatively, the link may be implemented through an adapter card slot (e.g., PCIe M.2 slot), a cable, or a combination of different media. The link may also include an optical portion in which the PCIe packets are encapsulated within a different system. In this example, when data is sent from the host system to the endpoint device system across multiple lanes, the PHY TX block222may include logic for partitioning the data among the lanes. Similarly, when data is sent from the endpoint device system to the host system210across multiple lanes, the PHY TX block266may include logic for partitioning the data among the lanes.

The PHY TX block222of the host system210shown inFIG.2may be implemented to include a transmit driver320-1to320-nto drive each first differential line pair312-1to312-nto transmit data, and the PHY RX block270of the endpoint device system250shown inFIG.2may be implemented to include a receiver340-1to340-n(e.g., amplifier) to receive data from each second differential line pair312-1to312-n. Each transmit driver320-1to320-nis configured to drive the respective differential line pair312-1to312-nwith data, and each receiver340-1to340-nis configured to receive data from the respective first differential line pair312-1to312-n. Also, inFIG.2, the PHY TX block266of the endpoint device system250may include a transmit driver345-1to345-nfor each second differential line pair315-1to315-n, and the PHY RX block226of the host system210may include a receiver325-1to325-n(e.g., amplifier) for each second differential line pair315-1to315-n. Each transmit driver345-1to345-nis configured to drive the respective second differential line pair315-1to315-nwith data, and each receiver325-1to325-nis configured to receive data from the respective second differential line pair315-1to315-n.

In certain aspects, the width of the link385can be scalable to match the capabilities of the host system and the endpoint. The link may use one lane310-1for an x1 link, two lanes,310-1,310-2for an x2 link, or more lanes for wider links up to n lanes from310-1to310-n. Currently, links (x1, x2, x4, x8, x16, and x32) are defined for 1, 2, 4, 8, 16, and 32 lanes, although a different number of lanes may be used to suit particular implementations.

In one example, the host system210may include a power switch circuit350configured to individually control power to the transmit drivers320-1to320-nand the receivers325-1to325-nfrom the PMIC290. Therefore, in this example, the number of drivers and receivers that are powered on scales with the width of the link385. Similarly, the endpoint device system250as was shown inFIG.2may include a power switch circuit360configured to individually control power to the transmit drivers345-1to345-nand the receivers340-1to340-nfrom the PMIC290. In this way, the host system can set a number of the plurality of drivers to be selectively powered by the power switch circuit to change a number of active transmit lines and/or receive lines based on the number of lines that are powered (active) or electrically idle. With differential signaling, the lines can be set as active or standby in pairs. In some aspects, the transmit lines and receive lines of a differential pair can be independently set as active or standby.

ASPM States

FIG.4is a diagram400illustrating the operation of a power management state machine in accordance with some aspects disclosed herein. In some aspects, a PCIe system (e.g., system205) can manage power using the Active State Power Management (ASPM) protocol. The ASPM protocol is a power management mechanism for PCIe devices to reduce power usage based on link activity detected over the PCIe link between a host (e.g., the root complex) and an endpoint PCIe device. The state diagram400shows some PCIe link states that are consistent with the Link Training and Status state machine (LTSSM) as defined for PCIe, and other link states may be omitted for brevity. In this example, the link can operate in an L0 state404(i.e., active link operation state) where data can be transferred over a PCIe link in both directions. In L0, a PCIe device (e.g., a host or an endpoint) may be active and responsive to PCIe transactions, and/or may request or initiate a PCIe transaction.FIG.4also shows a standby state L1406that is defined in the PCIe specification. As shown, the L1 state406is accessible through a connection to the L0 state404. An ASPM state change may be initiated when conditions on a link dictate or suggest that a transition between states is appropriate. Both communication partners (e.g., a host and an endpoint) of the link may initiate power state change requests when conditions are right (e.g., idle or low data traffic).

When the link is idle (e.g., for a short time interval between data bursts or no data traffic for a time interval greater than a predetermined threshold), the link may be taken from the L0 state to a standby state L0s408, which is accessible only through the L0 state. In PCIe, L0s408is a power saving state accessible from L0. The link can also change to the L1 state406, which is a standby state with a higher exit latency than the L0s state402such that it takes a longer time to go back to L0 from L1 than from L0s. However, L1 can provide more power saving than L0s. In some aspects, the link can return from L1 to L0 through a recovery state410. In the recovery state, devices (e.g., a host and an endpoint) using the link can exchange training sequences to negotiate various link parameters, including for example lane polarity, link/lane numbers, equalization parameters, data rate, and so on. The exit latency of L0s and L1 refers to the time it takes for the device to go back to the L0 state. When a device (e.g., a host or endpoint) enters L0s, the transmitting device can send an electrical idle ordered set (EIOS) to the receiving device, then turn off power to its transmitter. When a device returns from L0s to L0, the device can transmit a specific number of small ordered sets known as Fast Training Sequences (FTS) in the PCIe specification such that the receiver can regain receiver lock and is able to receive traffic on the link.

In L0s, data may be transferred in both directions or one direction only, so that two devices (e.g., host and endpoint) connected by a link can each independently set their transmitters to idle. In some aspects, the L0s state can serve as a low latency standby state. Power saving techniques available during L0s can include, but are not limited to, powering down at least a portion of transceiver circuitry as well as the clock gating of at least the link layer logic. In L0s, device discovery and bus configuration processes may be implemented before the link transitions422from L0s to L0.

In L1, no data is being transferred through the link so that portions of the PCIe transceiver logic and/or PHY circuit can be turned off or disabled to achieve higher power savings than achievable in L0s. For example, a PCIe device can shut down most of the link transceiver circuitry and/or the PLL. The PCIe device can also use apply clock gating (i.e., reduce the clock rate) to most PCIe architecture logic. The L1 state is a primary standby state with higher latency and power saving than L0s. The L1 state may be entered through a transition424from L0 when a PCIe device determines that there are no outstanding PCIe requests or pending transactions or traffic. In some examples, power consumption in L1 may be reduced by disabling or idling transceivers in PCIe bus interfaces, disabling, gating, or slowing clocks used by the PCI device, and disabling PLL circuits used to generate clocks used to receive data. A PCIe device may make the transition424to L1 through the operation of a hardware controller or some combination of operating system and hardware control circuits.

In some aspects, the ASPM protocol can determine whether to transition to L0s or L1 based on a finite time interval or a threshold defined as the L0s/L1 entry latency. For example, whenever the PCIe link is inactive for the given L0s or L1 entry latency duration, a PCIe controller may request a link partner to enter a lower-power or standby link state (L0s or L1) in order to save power. In some instances, the L0s entry latency duration and L1 entry latency duration can be chosen based on overall system parameters, activity, and/or pending operations. The ASPM state machine may initiate a transition to a low power state (e.g., L0s or L1) after an observed link inactivity time. The particular entry latency duration may be adapted to suit different system architectures and device characteristics. In some aspects, the packet latency between data read/write requests in a PCIe interface can vary in some implementations, between e.g., 1 μs and 40 μs. In general, L0s entry latency is shorter than L1 entry latency.

FLIT Mode

In some aspects, a PCIe link can operate in FLIT mode that can improve the latency and efficiency of the PCIe link by performing error correction on fixed-sized packets (flits). A partial width link state L0p430is available in FLIT mode. In L0p, some lanes of a link may be in an electrical idle (EI) state while other lanes remain available for transferring PCIe traffic. By idling some lanes during low throughput data traffic scenarios, the L0p state can reduce power consumption while active data communication can continue through the link.

In L0p, a link may have a partial width. In some cases, each direction of the link can have different widths. Therefore, flits can be sent at different widths over the link. The link can exit to other link states, such as a low power link state (e.g., L1) based on certain received and sent messages or other events. In FLIT mode, however, the standby state L0s is not available according to the current PCIe specification. In that case, the transition to the power-saving state (e.g., L1) from L0p needs to wait until the L1 state inactivity timer is triggered.

L0ps State in FLIT Mode

In some aspects, a new partial width standby link state432(L0ps) is available when the link is in FLIT mode. When the link is in FLIT mode, L0ps provides a low-power standby state that has lower latency than L1. In L0p, when any RX line or TX line of the link becomes idle or inactive (e.g., for a short time interval between data bursts or a predetermined threshold), the idle RX/TX line(s) can change from L0p to the new standby state L0ps which is accessible only from L0p when FLIT mode is enabled. The RX line and TX line of a lane can enter the L0ps state independently. In some aspects, there is a separate L0p/L0ps transition state diagram for each line such that the RX line and TX line of a lane can switch between the L0p and L0ps states independently.

In some aspects, L0ps is a low power state that allows a PCIe link to quickly enter and recover from without going through recovery. The lines of a PCIe link can enter and exit the L0ps state independently. For example, a line transmitter (e.g., drivers320-1to320-n) and a line receiver (e.g., receivers340-1to340-n) can stop or lower its clock rate (e.g., using dynamic clock gating) to reduce power consumption when the RX/TX line is in L0ps. In some aspects, a PCIe device controls its transmitter to enter L0ps and transmit an ordered set (e.g., EIOS), and a receiver enters L0ps after receiving the ordered set from the transmitter. In some aspects, a device (e.g., endpoint) can transition the data link from L0p to L0ps without obtaining permission from a PCIe host. In contrast, a transition to L1 involves the device (e.g., endpoint) first requesting permission from an upstream device (e.g., a host) to enter the deeper power conservation L1 state. Upon acknowledgment, both devices can turn off their transmitters and enter electrical idle in the L1 state.

FIG.5is a diagram of a PCIe link between a host502and an endpoint504according to some aspects. The link506includes multiple duplex traffic lanes that may have the same physical structure as described in relation toFIG.3but are generalized to show four lanes in an exemplary x4 configuration. For example, the link506can include four lanes511,512,513,514, although more or fewer lanes may be used. Each lane includes two transmit (TX) lines (TX signal lines) as a differential line pair and two receive (RX) lines (RX signal lines) as a differential line pair. In this example, the link506has four lines per lane. InFIG.5, TX lines carry traffic in the direction from the host502to the endpoint504, and RX lines carry traffic in the direction from the endpoint504to the host502. Based on the example inFIG.3, the PHY TX block222shown inFIG.2may be implemented to include a transmit driver for each differential pair of TX lines, and the PHY RX block270shown inFIG.2may be implemented to include a receiver for each differential pair of RX lines.

In L0p, the width of the link506can be changed by controlling the number of lanes511,512,513,514that are active and/or idle without interrupting the data flow (i.e., always keeping at least one lane active while changing link width). The host502or the endpoint504may change the link width by configuring the number of traffic lanes that are powered to transmit and receive data through the link L0p is a partial width state in which some lanes (e.g., lanes511and512) can be active and some lanes (e.g., lanes513and514) can be electrically idle (E.I.). In L0p, the active lanes511and512can be used to transmit and/or receive traffic, and the E.I. lanes are not used (idle). If both TX traffic and/or RX traffic are low or if there is no traffic activity over the active lanes, then one or more RX and/or TX lines may be put in the L0ps state (standby state) to reduce the power consumption of the link.

FIG.6is a diagram illustrating an example of a PCIe link operating in FLIT mode between a host602and an endpoint604according to some aspects. The host602and endpoint604may be the same as the host502and endpoint504inFIG.5. The link606may have four lanes611,612,613,614similar to the PCIe link506described above inFIG.5. In one example, lanes611and612may be active lanes in the L0p state, and lanes613and614are electrically idle (E.I.). Due to low or no RX activity, RX lines620of lane611and RX lines622of lane612can change to the L0ps state to reduce link power consumption. In this case, the TX lines624of lane611and TX lines626of lane612remain in the L0p state for PCIe traffic. In some aspects, the transmitter (e.g., host602/endpoint604) may use an inactivity timer or threshold for determining the timing to change a line to the L0ps state due to low traffic or inactivity. In one aspect, when the inactivity timer expires or is triggered, the transmitter (e.g., endpoint604) can transmit an EIOS on the corresponding lane and enter L0ps, and the receiver (e.g., host602) can enter L0ps after receiving the EIOS on the corresponding lane. The RX and TX lines of the same lane can enter L0ps independently based on different inactivity timers (e.g., RX inactivity timer and TX inactivity timer). Similarly, the RX and TX lines can go back to the L0p state independently.

FIG.7is a diagram illustrating another example of a PCIe link operating in FLIT mode between a host702and an endpoint704according to some aspects. The host702and endpoint704may be the same as the hosts and endpoints inFIGS.5and6. The link706between the host702and endpoint704may have four lanes711,712,713, and714. In one example, lanes711and712may be active lanes in the L0p state, and lanes713and714are electrically idle (E.I.). Due to low or no TX traffic, TX lines720of lanes711and TX lines722of lane712can be put in the L0ps state to reduce link power consumption. The RX lines724of lane711and RX lines726of lane712remain in the L0p state for PCIe traffic. In some aspects, a transmitter (e.g., host702/endpoint704) may use an inactivity timer or threshold for determining the timing to change a line to the L0ps state due to low traffic or inactivity. When the inactivity timer expires or is triggered, the transmitter (e.g., host702or endpoint704) can transmit an EIOS on the corresponding lane and enters L0ps, and the receiver (e.g., endpoint704) can enter L0ps after receiving the EIOS on the corresponding lane. The RX and TX lines of the same lane can enter L0ps independently. The RX and TX lines of the same lane can enter L0ps independently based on different inactivity timers (e.g., RX inactivity timer and TX inactivity timer).

The new L0ps state described above can provide power savings for a PCIe link in FLIT mode (e.g., in L0p state) even when TX or RX line alone is idle. Because the line can go to L0ps without handshaking (unlike a transition to L1) between the host and endpoint, the overhead of a handshake sequence can be avoided. Therefore, the transition between L0ps and L0p states can provide significant overhead power saving over a period of time. Further, the L0ps state power saving can scale with increased link width. In comparison to L1, the L0ps state can provide lower latency (e.g., exit latency) because the transition from L0ps to L0p does not need to go through a recovery state that involves exchanging training sequences to negotiate various link parameters, including for example lane polarity, link/lane numbers, equalization parameters, data rate, and so on.

PCIe Capability Structure

In some aspects, the configuration and control of PCI devices (e.g., hosts and endpoints) can be performed using a set of registers referred to as configuration space in the PCIe specification. PCIe devices can have an extended configuration space providing additional registers.FIG.8is a diagram illustrating an exemplary PCIe configuration space (e.g., Device 3 Extended Capability Structure) according to some aspects. The Device 3 Extended Capability Structure800can be configured to support the implementation of the new standby state L0ps described above in relation toFIGS.4-7. The Device 3 Extended Capability Structure800can include a PCIe extended capability header802, a device capabilities 3 register804, a device control 3 register806, and a device status 3 register808.

FIG.9is a diagram illustrating a device capabilities 3 register900and a device control 3 register901according to some aspects. The device capabilities 3 register900and device control 3 register901may be the same as those included in the Device 3 Extended Capability Structure800ofFIG.8. The device capabilities 3 register can have 32 bits in which some bits902(e.g., bits 0-9) are configured for various functions according to the current PCIe specification. For example, bit 3 can indicate whether or not L0p is supported by a receiver, bits 4-6 can indicate the port L0p exit latency, and bits 7-9 can indicate the retimer L0p exit latency. The device capabilities 3 register also has reserved bits904(e.g., bits 10-31) that can be used to implement new features such as the new L0ps state described above in relation toFIGS.4-7. In one example, bit 10 can be used to indicate whether L0ps is supported or not, and bits 11-12 can provide the L0ps exit latency value. L0ps exit latency specifies the latency to exit the L0ps state (e.g., go back to L0p).

The device control 3 register901can have 32 bits in which some bits906(e.g., bits 0-6) are configured for various functions in the current PCIe specification. For example, bit 3 can indicate whether L0p state is enabled or not. The device control 3 register also has reserved bits908(e.g., bits 7-31) that can be used to implement new features such as the L0ps state described above in relation toFIGS.4-7. In one example, bit 7 can be used to indicate whether L0ps is enabled or not (e.g., 1 for enabled, 0 for disabled).

FIG.10is a block diagram of a link interface processing circuit. The processing circuit1004is an apparatus that may be a part of a host or an endpoint. It is coupled to a link1002, e.g., a PCIe link, with multiple duplex lanes similar to those described in relation toFIGS.5-7. The link1002can be coupled at an opposite end to another PCIe device (e.g., an endpoint or a host). Data and control information communicated as packets through the link1002are coupled to a link interface1020(e.g., PCIe interface) which provides a PHY level interface to the link1002and converts baseband signals to packets. The data and control packets are sent through the link interface1020through a bus1010to other components of the processing circuit1004. The link interface1020has a direct connection to interface configuration circuitry1018for configuration and control settings for the operation of the link1002.

The processing circuit1004further includes a memory1021that can be used for storing data and information used by the processor during various operations. The processing circuit1004further includes timer circuitry1012that is coupled to the bus1010. The timer circuitry1012can be configured for various timing-related functions, for example, timing for latency, inactivity, acknowledgment, and transition between PCIe states (e.g., L0, L0p, L0ps, L1, L2, and L3). The timer circuitry1012can access a computer-readable storage medium1008to access code for managing timers1032. In some aspects, the storage medium is a non-transitory computer-readable medium. The timer circuitry1012may also access registers maintained in the storage medium1008(and/or memory1021) that contain receive (RX) traffic timing thresholds1034and transmit (TX) traffic timing thresholds1036, which can be used to determine transition timing between PCIe link states.

The processing circuit1004can further include power management circuitry1014that manages power to each line/lane of the link1002and to other components of the processing circuit1004. The power management circuitry1014has access through the bus1010to code for managing PCIe power1040and to transmit line state registers1042and receive line state registers1044. These registers may be used to store a state for each transmit line and each receive line, or for a transmit side of a link and a receive side of the link. The state may be determined using the code for managing timers1032, the code for managing PCIe power1040, or in another way.

The processing circuit1004can further include link traffic monitor circuitry1016that monitors the transmit and receive traffic activity on the link1002. For example, link the traffic monitor circuitry1016can monitor traffic activity and traffic inactivity in order to determine the current link state and transition between link states. The link traffic monitor circuitry1016has access to code for monitoring link traffic1050in the storage medium1008and also to registers to store results and to obtain traffic activity thresholds. Transmit traffic activity thresholds1052and receive traffic activity thresholds1054can be used for monitoring transmit traffic activity and receive traffic activity, respectively.

The power management circuitry1014may manage power of the transmit lines and power of the receive lines in accordance with the transmit traffic activity and the receive traffic activity. The interface configuration circuitry1018may modify the configuration in response to the power management circuitry1014. For example, the interface configuration circuitry1018can change the link state (e.g., L0, L0p, L0ps) of the link1002.

The interface configuration circuitry1018is coupled to the bus1010as are the link traffic monitor circuitry1016, power management circuitry1014, and the timer circuitry1012so that each of these blocks may communicate with each other, with the storage medium1008and to a processor1006. The processor1006can control the operation of the other components and instigates instances of each component or its function as appropriate to the operation of the processing circuit1004. The interface configuration circuitry1018also has access to code for configuring the PCIe interface1060. On executing this code, the interface configuration circuitry1018can read and write values from a variety of configuration registers. For example, these registers include TX control, status, and capabilities registers1062and RX control, status, and capabilities registers1064. These registers may be accessed and read at the start of link initialization and then updated with the result of the initialization. The registers may also be modified in response to power management and bandwidth negotiations or to change the status of one or more transmit lines or receive lines of the link1002.

In some aspects, the interface configuration circuitry1018and link interface1020can configure the link1002to use the L0p and L0ps link states in FLIT mode as described above. In some aspects, the link1002in L0p state can quickly enter (e.g., based on an L0ps inactivity timer, for example, maintained by the timer1012) and recover from the L0ps state without going through a recovery state. In some aspects, the interface configuration circuitry1018and link interface1020can transmit or receive an electrical idle ordered set (EIOS) via the link1002. The EIOS can cause the link to enter L0ps. In some aspects, when a lane of the link1002switches from L0ps back to L0p, the interface configuration circuitry1018and link interface1020can re-establish bit lock, symbol lock, or block alignment, and perform lane-to-lane de-skew. In one example, the interface configuration circuitry1018and link interface1020can de-skew the lane by sending exit patterns on the idle lanes to train and de-skew them. As one example, an exit pattern can include an electrical idle exit ordered set (EIEOS) and a fast training sequence (FTS).

The processing circuit1004may initialize the link1002, manage the power, link state, and change the number of active lines of the link1002. In operation, bandwidth requests may also be received from the host or endpoint. Bandwidth requests may cause a bandwidth negotiation followed by a change in values set to control, status, and capabilities registers. The number of active lines may then be changed in response to transmit traffic activity and receive traffic activity. The link traffic monitor circuitry1016also can monitor TX traffic activity for the transmit lines of the link1002and monitors RX traffic activity for the receive lines of the link1002. The TX traffic activity and RX traffic activity are evaluated to determine a change of the number of active lines. The power management circuitry1014may change the link state of one or more TX or RX lines. The state change may then be recorded in TX line state registers1042and RX line state registers1044. The evaluation may be performed in different ways. In some examples, the TX traffic activity is compared to one or more thresholds in TX traffic threshold registers1052and the RX traffic activity is compared to one or more thresholds in RX traffic threshold registers1054at the link traffic monitor circuitry1016. A message may then be sent to the connected device (e.g., the host or endpoint) through the link1002.

Upon changing the number of active lines or link state, the power management circuitry1014may change the voltage levels of one or more of the voltages276,278, and280by instructing the PMIC290to set the voltage levels of one or more of the voltages supplied by the PMIC290as shown inFIG.2. The power management circuitry1014may also connect or disconnect power to drivers and receivers of affected lines in accordance with a new number of active lines. As an example, if the number of active lines is decreased, then the power management circuitry1014may power down the drivers in the PHY TX block222and/or the receivers in the PHY RX block226corresponding to the lines in the link1002that are being deactivated because of the change. The power management circuitry1014may power down selected drivers and/or receivers by sending instructions to a power switch circuit to turn off the selected drivers and/or receivers. So a power according to the negotiated bandwidth is managed by supplying one or more voltages to the interface circuit of the link and by setting the levels of the one or more voltages.

FIG.11illustrates a flow diagram of a method1100for link state management of a link, e.g., a PCIe link, according to aspects of the present disclosure. In certain aspects, the method1100provides techniques for link state management of a PCIe link operating in FLIT mode. As described herein the link can be a PCIe link, however, the method may be adapted to suit other data links with transmit lines and receive lines that operate in various link states. In some aspects, the method1100can be implemented at any of the hosts or endpoints described in.

At1102, the method includes a process of operating a PCIe link (a data link with a host or endpoint) in a flow control unit (FLIT) mode using fixed-sized packets. The PCIe link is in a partial width link state (PLS) in which a first set of lanes of the PCIe link are in an electrical idle state and a second set of lanes of the PCIe link are in an active state available for carrying PCIe traffic to/from a host or endpoint. In some aspects, PLS can correspond to the L0p state of a PCIe link in FLIT mode as described herein. For example, the PCIe link may be the same as the link506,606, or706, with some lanes (e.g., lanes513,514,613,614,713, or714) in the electrical idle state as in L0p. In one aspect, the interface configuration circuitry1018and PCIe interface1020can provide a means to operate the PCIe link in PLS using the FLIT mode.

At1104, the method includes a process of transitioning one or more lines (e.g., Rx line(s) and/or Tx line(s)) of the second set of lanes from the PLS to a partial width standby link state (PSLS) in which the one or more lines of the second set of lanes are in a standby state that has lower power consumption than the active state. In some aspects, PSLS corresponds to the L0ps state of the PCIe link in FLIT mode. As described above inFIGS.4-9, L0ps provides a lower power standby state from L0p when the link is in FLIT mode in which the other standby state L0s is not available. In one aspect, the interface configuration circuitry1018and PCIe interface1020can provide a means to transition the PCIe link between PLS and PSLS.

The following provides an overview of examples of the present disclosure.

a method of operating an endpoint for data communication, comprising: operating a data link with a host in a flow control unit (FLIT) mode using fixed-sized packets, the data link being in a partial width link state (PLS) in which a first set of lanes of the data link are in an electrical idle state and a second set of lanes of the data link are in an active state available for data traffic with the host; and transitioning one or more lines of the second set of lanes from the PLS to a partial width standby link state (PSLS) in which the one or more lines of the second set of lanes are in a standby state that has lower power consumption than the active state.

the method of example 1, further comprising: transitioning the one or more lines of the second set of lanes from the PSLS back to the PLS without going through a recovery state.

the method of example 1, further comprising: receiving, from the host, an electrical idle ordered set via the data link; and transitioning the one or more lines of the second set of lanes from the PLS to the PSLS in response to the electrical idle ordered set.

the method of example 1, further comprising transitioning the one or more lines of the second set of lanes from the PSLS to the PLS, comprising at least one of: establishing with the host at least one of bit lock, symbol lock, or block alignment of the data link; or de-skewing lane-to-lane skew of the data link.

the method of example 1, 2, 3, or 4, wherein the one or more lines of the second set of lanes comprises a transmit signal line for transmitting a signal to the host and a receive signal line for receiving a signal from the host, and wherein the transitioning the one or more lines of the second set of lanes from the PLS to the PSLS comprises at least one of: transitioning the transmit signal line to the PSLS independent of the receive signal line; or transitioning the receive signal line to the PSLS independent of the transmit signal line.

the method of example 5, wherein the transitioning the one or more lines of the second set of lanes from the PLS to the PSLS comprises: transitioning the transmit signal line to the PSLS based on a first inactivity timer; and transitioning the receive signal line to the PSLS based on a second inactivity timer that is independent of the first inactivity timer.

the method of example 5, further comprising: transitioning the one or more lines of the second set of lanes from the PLS to the PSLS without obtaining permission from the host.

the method of example 1, 2, 3, or 4, wherein the PLS comprises a peripheral component interconnect express (PCIe) L0p state configured to operate the data link in the FLIT mode using fixed-sized packets, and the PSLS comprises a PCIe L0ps state configured to operate the data link in the FLIT mode.

an endpoint for a peripheral component interconnect express (PCIe) link comprising: an interface circuit configured to provide an interface with the PCIe link connected with a host; and a controller configured to: operate the PCIe link in a flow control unit (FLIT) mode using fixed-sized packets, the PCIe link being in a partial width link state (PLS) in which a first set of lanes of the PCIe link are in an electrical idle state and a second set of lanes of the PCIe link are in an active state available for data traffic with host; and transitioning one or more lines of the second set of lanes from the PLS to a partial width standby link state (PSLS) in which the one or more of the second set of lanes are in a standby state that has lower power consumption than the active state.

the endpoint of example 9, wherein the controller is further configured to: transition the one or more lines of the second set of lanes from the PSLS back to the PLS without going through a recovery state.

the endpoint of example 9, wherein the controller is further configured to: receive, from the host, an electrical idle ordered set via the PCIe link; and transition the one or more lines of the second set of lanes from the PLS to the PSLS in response to the electrical idle ordered set.

the endpoint of example 9, wherein, to transition the one or more lines of the second set of lanes from the PSLS to the PLS, wherein the controller is further configured to: establish with the host at least one of bit lock, symbol lock, or block alignment of the PCIe link; or de-skew lane-to-lane skew of the PCIe link.

the endpoint of example 9, 10, 11, or 12, wherein the one or more lines of the second set of lanes comprises a transmit signal line for transmitting a signal to the host and a receive signal line for receiving a signal from the host, and wherein, to transition the one or more lines of the second set of lanes PCIe link from the PLS to the PSLS, the controller is further configured to at least one of: transition the transmit signal line to the PSLS independent of the receive signal line; or transition the receive signal line to the PSLS independent of the transmit signal line.

the endpoint of example 13, wherein, to transition the one or more lines of the second set of lanes from the PLS to the PSLS, the controller is further configured to: transition the transmit signal line to the PSLS based on a first inactivity timer; and transition the receive signal line to the PSLS based on a second inactivity timer that is independent of the first inactivity timer.

the endpoint of example 13, wherein the controller is further configured to: transition the one or more lines of the second set of lanes from the PLS to the PSLS without obtaining permission from the host.

the endpoint of example 9, 10, 11, or 12, wherein the PLS comprises a PCIe L0p state configured to operate the PCIe link in the FLIT mode using fixed-sized packets, and the PSLS comprises a PCIe L0ps state configured to operate the PCIe link in the FLIT mode.

a host for a peripheral component interconnect express (PCIe) link, comprising: an interface circuit configured to provide an interface with the PCIe link connected with an endpoint; and a controller configured to: operate the PCIe link in a flow control unit (FLIT) mode using fixed-sized packets, the PCIe link being in a partial width link state (PLS) in which a first set of lanes of the PCIe link are in an electrical idle state and a second set of lanes of the PCIe link are in an active state available for data traffic with the endpoint; and transition one or more lines of the second set of lanes from the PLS to a partial width standby link state (PSLS) in which the one or more of the second set of lanes are in a standby state that has lower power consumption than the active state.

the host of example 17, wherein, to transition the one or more lines of the second set of lanes from the PSLS to the PLS, wherein the controller is further configured to, at least one of: establish with the endpoint at least one of bit lock, symbol lock, or block alignment of the PCIe link; or de-skew lane-to-lane skew of the PCIe link.

the host of example 17 or 18, wherein the one or more lines of the second set of lanes comprises a transmit signal line for transmitting a signal to the endpoint and a receive signal line for receiving a signal from the endpoint, and wherein, to transition the one or more lines of the second set of lanes from the PLS to the PSLS, the controller is further configured to at least one of: transition the transmit signal line to the PSLS independent of the receive signal line; or transition the receive signal line to the PSLS independent of the transmit signal line.

the host of example 19, wherein, to transition the one or more lines of the second set of lanes from the PLS to the PSLS, the controller is further configured to: transition the transmit signal line to the PSLS based on a first inactivity timer; and transition the receive signal line to the PSLS based on a second inactivity timer that is independent of the first inactivity timer.

It is to be appreciated that the present disclosure is not limited to the exemplary terms used above to describe aspects of the present disclosure. For example, bandwidth may also be referred to as throughput, data rate or another term.

Although aspects of the present disclosure are discussed above using the example of the PCIe standard, it is to be appreciated that present disclosure is not limited to this example, and may be used with other standards.

The host clients214, the host controller212, the device controller252and the device clients254discussed above may each be implemented with a controller or processor configured to perform the functions described herein by executing software including code for performing the functions. The software may be stored on a non-transitory computer-readable storage medium, e.g., a RAM, a ROM, an EEPROM, an optical disk, and/or a magnetic disk, shows as host system memory240, endpoint system memory274, or as another memory.

Any reference to an element herein using a designation e.g. “first,” “second,” and so forth does not generally limit the quantity or order of those elements. Rather, these designations are used herein as a convenient way of distinguishing between two or more elements or instances of an element. Thus, a reference to first and second elements does not mean that only two elements can be employed, or that the first element must precede the second element.

Within the present disclosure, the word “exemplary” is used to mean “serving as an example, instance, or illustration.” Any implementation or aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects of the disclosure. Likewise, the term “aspects” does not require that all aspects of the disclosure include the discussed feature, advantage, or mode of operation. The term “coupled” is used herein to refer to the direct or indirect electrical or other communicative coupling between two structures. Also, the term “approximately” means within ten percent of the stated value.