High speed SAR ADC

High speed, high dynamic range SAR ADC method and architecture. The SAR DAC comparison method can make fewer comparisons with less charge/fewer capacitors. The architecture makes use of a modified top plate switching (TPS) DAC technique and therefore achieves very high-speed operation. The present disclosure proffers a unique SAR ADC method of input and reference capacitor DAC switching. This benefits in higher dynamic range, no external decoupling capacitory requirement, wide common mode range and overall faster operation due to the absence of mini-ADC.

CROSS-REFERENCE TO RELATED APPLICATIONS

This Application is related to U.S. application Ser. No. 17/558,610 filed Dec. 22, 2021, entitled “ALGORITHM FOR HIGH SPEED SAR ADC,” which is hereby incorporated herein in its entirety.

FIELD OF THE DISCLOSURE

This document pertains generally, but not by way of limitation, to integrated circuits, and more particularly, to analog-to-digital converter circuits and systems.

BACKGROUND

Analog signals and/or values can be produced in various kinds of circuit elements, such as signal generators, sensors, and antennas. However, there can be many instances where having digital signals or values can be beneficial, such as for a processing or storing of the signals or values. To utilize the benefits of having a digital signal or value when an analog signal or value has been produced, analog-to-digital converters (ADCs) have been developed to convert the analog signal or value into a digital signal or value.

A signal may be a time-based sequence of values. A digital value may be represented by a code. A name of a code (for example, CODE1) may refer to a digital value represented by the code. Some (but not all) digital values may be represented by codes using binary-weighted encoding. A resolution of a digital value or code expressed in terms of a number of bits may refer to a binary-weighted encoding, regardless of how it may be encoded.

In many electronics applications, analog input values are converted to digital output values (for example, for further digital processing or storage). For instance, in precision measurement systems, electronics are provided with one or more sensors to make measurements, and these sensors may generate analog values. The analog values may be provided as an input to an ADC to generate digital output values for further processing or storage.

ADCs can be found in many places such as broadband communication systems, automated test equipment, audio systems, vehicles, factory automation systems, etc. ADCs can translate analog electrical values representing real-world phenomena, e.g., light, sound, temperature, flow, or pressure. Designing an ADC is a non-trivial task because each application may have different needs in speed, performance, power, cost and size. As the applications needing ADCs grow, the need for accurate and reliable conversion performance also grows.

It is a general object of the present invention to provide a successive approximation A/D converter that substantially obviates one or more problems caused by the limitations and disadvantages of the related art.

There is a demonstrated need in the art for a wider common mode range for both reference and input and a reference buffer which is easier to design. There is also a demonstrated need to remove the mini-ADCs which are present in many systems. The inventors of the present disclosure have recognized that an impediment to low power and higher speeds. As such, the inventors contemplate a new comparison algorithm.

This overview is intended to provide an overview of subject matter of the present patent application. It is not intended to provide an exclusive or exhaustive explanation of the invention. Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with some aspects of the present invention as set forth in the remainder of the present application with reference to the drawings.

SUMMARY OF THE DISCLOSURE

High speed, high dynamic range SAR ADC method and architecture. The SAR DAC comparison method can make fewer comparisons with less charge/fewer capacitors. The architecture makes use of a modified top plate switching (TPS) DAC technique and therefore achieves very high-speed operation. The present disclosure proffers a unique SAR ADC method of input and reference capacitor DAC switching.

This benefits in removing the requirement for a mini-ADC for the same input swings. Therefore, this achieves better input bandwidth/redundancy usage compared to mini-ADC type architectures.

This also benefits in higher dynamic range for lower level input. The switching scheme results in lower reference caps for lower inputs thereby achieving lower input referred noise gain of residual amplifier (RA) and lower attenuation for ADC comparator inputs. The inventor of the present disclosure has recognized a 6 dB SNR improvement over traditional T/H based ADCs. This also make T/H based architecture more attractive for wide common mode range implementation as there is no need for two parallel mini-ADCs. This achieves lower complexity and consequently lower area and less power consumption. As such, the speed of the state-of-the-art architectures are maintained (and even exploited) without any reduction to SNR due to attenuation of reference caps, in addition to intention attenuation of caps of the DAC top plate to control voltage swing.

The present disclosure utilizes an ADC architecture which has symmetrical reference and input paths. This can be generalized to make a state-of-the-art “digitizer” that outputs the ratio of two inputs. So, instead of converting two inputs (using sim sampling ADC) and taking their ratio digitally, the generic form of this architecture could give that result using half the circuit layout area. The generic form of one or more embodiments has the ability to convert inputs greater than reference for overranging inputs.

Since the conversion happens entirely internal to the ADC block and no external signals like reference used during, it makes for a good candidate for embedded SAR which could run with no external decoupling capacitor. Also, the benefits in that the DAC resistances can be better controlled and easier for DAC design to make for very fast settling by matching the time constants in each DAC element.

Another advantage of the present disclosure is an inbuilt and on-demand redundancy. A redundancy can be implemented without affecting the attenuation inputs due to extra capacitors in the conversion DAC for inputs inside the [0, VREF] range. The existing DAC capacitors can be manipulated to generate voltage levels needed for redundancy implementation without needing additional caps tied to REF/GND on the conversion DAC. Extra redundant cap can be included with more segments in the reference DAC than required to attend to overranging. This can be added if the input is outside the rails, and therefore the SNR hit due to redundancy cap attenuation is only for inputs greater than full scale or less than negative full scale.

To achieve these and other advantages in accordance with the purpose of the invention, the disclosure provides a successive approximation A/D converter and algorithm thereof, which includes a sample-hold amplifier circuit configured to sample and hold an input analog voltage to produce at an output node an internal analog voltage proportional to the input analog voltage with a voltage gain being smaller than 1, a switched capacitor D/A converter coupled to the output node of the sample-hold amplifier circuit and including a plurality of capacitors for storing electric charge responsive to the internal analog voltage, the switched capacitor D/A converter configured to switch couplings of the capacitors in response to a control signal to produce at an output node a comparison analog voltage responsive to the internal analog voltage and the control signal, a comparator coupled to the output node of the switched capacitor D/A converter to produce at an output node a comparison result signal responsive to the comparison analog voltage, and a control circuit coupled to the output node of the comparator to supply the control signal responsive to the comparison result signal to the switched capacitor D/A converter.

The drawings show exemplary SAR circuits and configurations. Variations of these circuits, for example, changing the positions of, adding, or removing certain elements from the circuits are not beyond the scope of the present invention. The illustrated circuits, configurations, and complementary devices are intended to be complementary to the support found in the detailed description.

DETAILED DESCRIPTION

SAR analog-to-digital converters utilize a binary weighted capacitor array which is operable to operate in a tracking or sample mode wherein an input voltage is sampled onto one plate of a plurality of capacitors in the array. After sampling, the SAR converter is placed in a convert mode. In the convert mode, the plates of the capacitors that were connected to the input voltage are selectively connected between ground and a reference voltage. A comparator connected to the other plate of the capacitors is operable to compare the voltage on that plate with the threshold voltage in accordance with a conventional SAR search algorithm.

The following description and drawings set forth certain illustrative implementations of the disclosure in detail, which are indicative of several exemplary ways in which the various principles of the disclosure may be carried out. The illustrative examples, however, are not exhaustive of the many possible embodiments of the disclosure. Other objects, advantages and novel features of the disclosure are set forth in the proceeding in view of the drawings where applicable.

In many electronics applications, an analog input signal is converted to a digital output signal (e.g., for further digital signal processing). For instance, in measurement systems, electronics are provided with one or more sensors to make measurements, and these sensors can generate an analog signal. The analog signal can then be provided to an analog-to-digital converter (ADC) circuit as input to generate a digital output signal for further processing. In another instance, in a mobile device receiver, an antenna can generate an analog signal based on the electromagnetic waves carrying information/signals in the air. The analog signal generated by the antenna can then be provided as input to an ADC to generate a digital output signal for further processing.

Embodiments generally relate to electronic circuit designs, and more specifically to improvements in architectural arrangements which enable enhanced performance and/or features for sampling receivers, and specifically to direct conversion sampling receivers which include a successive approximation analog-to-digital converter (SAR-ADC) to enhance quality of sampling receivers, where the SAR-ADC incorporates a charge redistribution digital-to-analog converter (DAC) and where filtering is implemented in the radio frequency (RF) domain by at least reusing a capacitor arrays which form all or part of the DAC within the SAR ADC.

FIGS.1A-Ddepict exemplary successive approximation ADCs, in accordance with some embodiments of the disclosure provided herein.FIGS.1A-Dalso show an exemplary 2-bit process, the method of which can easily scaled up for higher resolution, as one skilled in the art can appreciate. Turning toFIG.1A, SAR-ADC100comprises reference inputs110, reference charging switches150, reference caps130, bridge switches155, comparator170, controller180, input bridge switches165, input caps140, input charging switches160, and inputs120.

Comparator170is a heuristic depiction of a comparator. A comparator is a device that compares two voltages or currents and outputs a digital signal indicating which is larger. A comparator consists of a specialized high-gain differential amplifier. They are commonly used in devices that measure and digitize analog signals, such as successive-approximation ADCs, as well as relaxation oscillators. A successive-approximation ADC is a type of analog-to-digital converter that converts a continuous analog waveform into a discrete digital representation using a binary search through all possible quantization levels before finally converging upon a digital output for each conversion.

The successive-approximation analog-to-digital converter circuit typically consists of four chief subcircuits. A sample-and-hold circuit to acquire the input voltage Vin. An analog voltage comparator that compares Vin to the output of the internal DAC and outputs the result of the comparison to the successive-approximation register (SAR). A successive-approximation register subcircuit designed to supply an approximate digital code of Vin to the internal DAC. An internal reference DAC that, for comparison with Vref, supplies the comparator with an analog voltage equal to the digital code output of the SARin.

Commonly in the art, the successive approximation register is initialized so that the most significant bit (MSB) is equal to a digital 1. This code is fed into the DAC, which then supplies the analog equivalent of this digital code (Vref/2) into the comparator circuit for comparison with the sampled input voltage. If this analog voltage exceeds Vin, then the comparator causes the SAR to reset this bit; otherwise, the bit is left as 1. Then the next bit is set to 1 and the same test is done, continuing this binary search until every bit in the SAR has been tested. The resulting code is the digital approximation of the sampled input voltage and is finally output by the SAR at the end of the conversion (EOC).

Contrary to traditional SAR-ADCs, the present disclosure gives rise to implementing the systems and methods found in U.S. application Ser. No. 17/558,610 filed Nov. 12, 2020, entitled “ALGORITHM FOR HIGH SPEED SAR ADC,” which is hereby incorporated herein in its entirety. As such, the embodiments disclosed herein are best viewed in the context of those algorithms.

Turing back,FIG.1Aillustrates the sampling of the input and reference voltages in a 2-bit SAR example. In practice input and ref voltages are acquired at the same time from inputs120and ref inputs110, respectively. On the ref side, reference charging switches150and ref bridge switches155are closed to allow ref inputs110to charge ref caps130. On the input sampling side, input charging switches160and input bridge switches165are closed to allow inputs120to charge input caps140.

In one embodiment, the controller180is a digital circuit controls the timing and switching of the switches. However, any suitable integrated circuit or device is not beyond the scope of the present invention. For example, the controller and/or other circuits of the FIGURES may be implemented as stand-alone modules (e.g., a device with associated components and circuitry configured to perform a specific application or function) or implemented as plug-in modules into application specific hardware of electronic devices. Note that particular embodiments of the present disclosure may be readily included in a system on chip (SOC) package, either in part, or in whole. An SOC represents an IC that integrates components of a computer or other electronic system into a single chip. It may contain digital, analog, mixed-signal, and often radio frequency functions: all of which may be provided on a single chip substrate. Other embodiments may include a multi-chip-module (MCM), with a plurality of separate ICs located within a single electronic package and configured to interact closely with each other through the electronic package. In various other embodiments, the clocking and filtering functionalities may be implemented in one or more silicon cores in Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs), and other semiconductor chips.

Turing toFIG.1B, SAR-ADC100comprises reference inputs110, reference charging switches150, reference caps130, ref bridge switches155, ref balance switches185, comparator170, controller180, input bridge switches165, input caps140, input charging switches160, input balance switches195, and inputs120. The present switching generates the necessary voltages on each cell, the details of which are now discussed.

As can be appreciated by one skilled in the art, ref balance switches185and input balance switches195are closed; reference charging switches150and input charging switches160are opened; and ref bridge switches155and input bridge switches165are opened. This provides the proper charging of the top plates while isolating from input and reference voltages.

Turing toFIG.1C, SAR-ADC100comprises reference inputs110, reference charging switches150, reference caps130, ref bridge switches155, ref balance switches185, comparator170, controller180, input bridge switches165, input caps140, input charging switches160, input balance switches195, and inputs120. According to some embodiments, the first step is to check the polarity of the sampled input. This results in the identification of the sign bit during a sign bit trial.

As can be appreciated by one skilled in the art, a single input cell135is for the sign bit trial. The two outer switches of input cell135are closed which creates a conductive path to the comparator170. Conversely, the inner cross switches can also be used with the notion that the operator knows of the opposite polarity. This result is the sign bit. Typically, the sign bit is a 1 or 0 in binary, which is used to denote positive/negative or forward/reverse bias, etc. However, any numbering or identification system is not beyond the scope of the present disclosure. For edification purposed, it is assumed that sign bit is 1.

Turing toFIG.1D, SAR-ADC100comprises reference inputs110, reference charging switches150, reference caps130, ref bridge switches155, ref balance switches185, comparator170, controller180, input bridge switches165, input caps140, input charging switches160, input balance switches195, and inputs120. According to some embodiments, the next step is to perform most significant bit (MSB) trial.

With the algorithm disclosed in U.S. application Ser. No. 17/558,610 filed Nov. 12, 2020, entitled “ALGORITHM FOR HIGH SPEED SAR ADC,” in mind, two input cells145are now compared to a single reference cell125. The switching choices—either straight or crossed—within the cell is determined by the sign bit. As can be appreciated by one skilled in the art, each subsequent switching choice for both the input and reference cells is based on the previous trial.

FIGS.2A-Billustrate exemplary novel successive approximation ADCs, in accordance with some embodiments of the disclosure provided herein. SAR-ADC200comprises reference inputs, sample input210, input cell210, comparator balance switches230, comparator235, and reference cell240. In one or more embodiments, input cell210comprises input charging switches205, M capacitors, input balance switch215, input bridging switches220, and input network switches225. Reference cell240comprises ref charging switches255, M capacitors, ref balance switch260, ref bridging switches250, and ref network switches245.

As can be appreciated by one skilled in the art, SAR-ADC inFIG.2Arepresents an idle or beginning state before acquisition and sampling. In some embodiments, input cells and reference cells, e.g.,210,240, are abstractions. They represent a collection of capacitors with corresponding switching networks, as necessary. Their capacitive value, collectively, is denoted by their respective notion and is explained as follows. Let's say the unit cap is C. And the resolution of the converter is N bits. The architecture involves splitting the total input and reference sampling capacitor into M equal parts, where M=2{circumflex over ( )}N. As one skilled in the art can appreciate, the charge compared at the comparison will different when comparing the same number of reference and input cells unless the input voltage equals the reference voltage.

Turning toFIG.2B, SAR-ADC200comprises reference inputs, sample input210, input cell210, comparator balance switches230, comparator235, and reference cell240. In one or more embodiments, input cell210comprises input charging switches205, M capacitors, input balance switch215, input bridging switches220, and input network switches225. Reference cell240comprises ref charging switches255, M capacitors, ref balance switch260, ref bridging switches250, and ref network switches245.

In practice, input charging switches205, ref charging switches255, comparator balance switches230, input bridging switches220, and reference bridging switches are all closed during the acquisition phase, as depicted inFIG.2B. This allows the capacitors to charge and nullify any remaining charge which may be present at the electrodes at the comparator235. The subsequent comparison algorithm will now be discussed in association with following figures.

FIG.3depicts an exemplary schematic of a successive approximation ADC, in accordance with others embodiments of the disclosure provided herein. SAR-ADC300comprises reference inputs390, input cell310, comparator balance switches330, comparator335, and reference cell385, input cell370and reference cell380. In one or more embodiments, input cell310comprises input charging switches, 2-unit capacitors, input balance switch315. In some embodiments, reference cell385comprises ref charging switches, 1-unit capacitors, ref balance switch360.

As previously discussed, a 4-bit converter will have N=4 and M=2{circumflex over ( )}4=16-unit capacitors. So, in the present embodiment, if the unit cell cap is equal to C, then the total input/reference cap is M*C. In practice, the bit trials begin with none of the reference cells tied to the comparator335input and only one input cell310tied to comparator335input. This is called as the sign bit trial. Based on this result, the manner in which the reference cells be connected will be changed. Thereafter each trial the total number of input cells will be ‘doubled’ and the number of reference cells connected to the comparator is based on the bit trial results so far.

In one or more embodiments, input cell370comprises input charging switches, M−2-unit capacitors, input balance switch365. In some embodiments, reference cell380comprises ref charging switches, M−1-unit capacitors, ref balance switch375. The circuitry configuration ofFIG.3represents the first trial after the sign bit trial, i.e., the most significant bit. It is noted that input cell370and ref cell380do not play a part in the trial and that they are abstractions representing the remain capacitors which are not used in the present trial.

Pursuant to the algorithm, 2 input cells are compared to 1 ref cell. The result of which determines the number of ref cells in the next trial which will now be discussed in greater detail. Input and ref charging switches are open while balance switches315,360are closed. Meanwhile switches from input cell310and ref cell385permit conductivity to the inputs of comparator335.

FIG.4depicts an exemplary schematic of a successive approximation ADC, in accordance with others embodiments of the disclosure provided herein. SAR-ADC400comprises reference inputs490, input cell410, comparator balance switches430, comparator435, and reference cell485, input cell470and reference cell480. In one or more embodiments, input cell410comprises input charging switches, 4-unit capacitors, input balance switch415. In some embodiments, reference cell485comprises ref charging switches, 3-unit capacitors, ref balance switch460.

As discussed, each trial the total number of input cells will be doubled and the number of reference cells connected to the comparator is based on the bit trial results so far. So,FIG.4shows the second bit trial after sign and MSB trials, therefore the input cap connected to comparator is equal to 1×2×2=4C. And the reference cap is, 2(because MSB trial resulted in 1)+1(current trial)=3C. The capacitors in input cell470and ref cell480are not yet part of the bit trial circuitry.

In one or more embodiments, input cell470comprises input charging switches, M−4-unit capacitors, input balance switch465. In some embodiments, reference cell480comprises ref charging switches, M−3-unit capacitors, ref balance switch475. The circuitry configuration ofFIG.4represents the second trial after the sign bit trial, i.e., the second most significant bit. It is noted that input cell470and ref cell480do not play a part in the trial and that they are abstractions representing the remain capacitors which are not used in the present trial.

Pursuant to the algorithm, 4 input cells are compared to 3 ref cells. The result of which determines the number of ref cells in the next trial which will now be discussed in greater detail. Input and ref charging switches are open while balance switches415,460remain closed. Meanwhile switches from input cell410and ref cell485permit conductivity to the inputs of comparator435.

FIG.5depicts an exemplary schematic of a successive approximation ADC, in accordance with others embodiments of the disclosure provided herein. SAR-ADC500comprises reference inputs590, input cell510, comparator balance switches530, comparator535, and reference cell585, input cell450and reference cell580. In one or more embodiments, input cell510comprises input charging switches, 8-unit capacitors, input balance switch515. In some embodiments, reference cell585comprises ref charging switches, 7-unit capacitors, ref balance switch560.

As discussed, each trial the total number of input cells will be doubled and the number of reference cells connected to the comparator is based on the bit trial results so far. So,FIG.5shows the third bit trial after sign and MSB trials, therefore the input cap connected to comparator is equal to 1×2×2×2=8C. And the reference cell585cap is 7, because MSB trial resulted in 1)+1(previous trial)+1(current trial)=7C. The capacitors in input cell570and ref cell580are not yet part of the bit trial circuitry.

In one or more embodiments, input cell570comprises input charging switches, M−8-unit capacitors, input balance switch565. In some embodiments, reference cell580comprises ref charging switches, M−7-unit capacitors, ref balance switch575. The circuitry configuration ofFIG.5represents the third trial after the sign bit trial, i.e., the third most significant bit. It is noted that input cell570and ref cell580do not play a part in the trial and that they are abstractions representing the remain capacitors which are not used in the present trial.

Pursuant to the algorithm, 8 input cells are compared to 7 ref cells. The result of which determines the number of ref cells in the next trial which will now be discussed in greater detail. Input and ref charging switches are open while balance switches515,560remain closed. Meanwhile switches from input cell510and ref cell585permit conductivity to the inputs of comparator535.

FIG.6depicts an exemplary schematic of a successive approximation ADC600, in accordance with others embodiments of the disclosure provided herein. SAR-ADC600comprises reference inputs690, input cell610, comparator balance switches630, comparator635, and reference cell685, input cell650and reference cell680. In one or more embodiments, input cell610comprises input charging switches, 8-unit capacitors, input balance switch615. In some embodiments, reference cell685comprises ref charging switches, 7-unit capacitors, ref balance switch660.

FIG.6illustrates the generalized implementation of an N-bit ADC where the number of reference cells connected to the comparator input, REFCELLS, after the kth bit trial after sign bit is given by the below equation.
REFCELLS=Σik2k,bMSB-i+1

The circuitry configuration ofFIG.6represents the k trial after the sign bit trial. It is noted that input cell670and ref cell680do not play a part in the trial and that they are abstractions representing the remain capacitors which are not used in the present trial.

Pursuant to the algorithm, 2kinput cells are compared to ref cells, the number of which is dependent on the previous trials. The result of which determines the number of ref cells in the next trial. Input and ref charging switches are open while balance switches615,660remain closed. Meanwhile switches from input cell610and ref cell685permit conductivity to the inputs of comparator635.

The SAR algorithm, without the above-mentioned redundancy, for an N bit A/D conversion can succinctly be described as follows:Step 1: Sample input and reference quantities [input=INP, reference=REF]Step 2: Split input and reference to M equal parts. where M=2{circumflex over ( )}N.set INP_CELL=INP/M, set REF_CELL=REF/M,set output array b [1: N]=0; i=1; X=0; Y=0.Step 3: set b[i]=1; X=(2{circumflex over ( )}i); Y=1+Σ{b[i]. (2{circumflex over ( )}i)} for i=1 to NStep 4: if (X.INP_CELL>=Y.REF_CELL) then b[i]=1 else b[i]=0.Step 5: if (i>=N) goto Step 6. else i=(i+1) and goto Step 3.Step 6: Stop. b [1: N] gives the digital output.

FIG.7illustrate an exemplary novel successive approximation ADC operating in differential mode, in accordance with some embodiments of the disclosure provided herein. SAR-ADC700comprises reference inputs, sample input710, input cell710, comparator balance switches730, comparator735, and reference cell740. In one or more embodiments, input cell710comprises input charging switches705, M capacitors, input balance switch715, input bridging switches720, and input network switches725. Reference cell740comprises ref charging switches755, M capacitors, ref balance switch760, ref bridging switches750, ref network switches745, and ref differential switches745.

As can be appreciated by one skilled in the art, SAR-ADC inFIG.7represents an idle or beginning state before acquisition and sampling. In some embodiments, input cells and reference cells, e.g.,710,740, are abstractions. They represent a collection of capacitors with corresponding switching networks, as necessary. Their capacitive value, collectively, is denoted by their respective notion and is explained as follows. Let's say the unit cap is C. And the resolution of the converter is N bits. The architecture involves splitting the total input and reference sampling capacitor into M equal parts, where M=2{circumflex over ( )}N. As one skilled in the art can appreciate, the charge compared at the comparison will different when comparing the same number of reference and input cells unless the input voltage equals the reference voltage.

In one or more embodiments, ref differential switches are used to cancel existing charge and/or negating voltage potential on the inputs to comparator735. As one skilled in the art can appreciate, an object is to reduce comparator swings. Each trial iteration not only identifies the next significant bit but to strives to mitigate the charge differential. To this end, inputs810opposite polarities can be observed inFIG.8.

FIG.8illustrate an exemplary novel successive approximation ADC operating in differential mode, in accordance with some embodiments of the disclosure provided herein. SAR-ADC800comprises reference inputs, sample input810, input cell810, comparator balance switches830, comparator835, and reference cell840. In one or more embodiments, input cell810comprises input charging switches805, M capacitors, input balance switch815, input bridging switches820, and input network switches825. Reference cell840comprises ref charging switches855, M capacitors, ref balance switch860, ref bridging switches850, ref network switches845, and ref differential switches845.

In practice, input charging switches805, ref charging switches855, comparator balance switches830, input bridging switches820, and reference bridging switches are all closed during the acquisition phase, as depicted inFIG.8. This allows the capacitors to charge and nullify any remaining charge which may be present at the electrodes at the comparator835. The subsequent comparison algorithm will now be discussed in association with following figures.

The present embodiments eliminate the need for large attenuation caps needed to reduce voltage swings at comparator inputs. The results in a comparator noise gain of 1+REFCELLS/M which increase linearly with input. For example, the comparative noise gain is ˜1 for inputs near zero swing and ˜2 for inputs near full swing. In contrast, the comparative noise gain is 1+M−1/M for a more traditional SAR ADC.

FIG.9depicts an exemplary schematic of a successive approximation ADC in differential mode, in accordance with others embodiments of the disclosure provided herein. SAR-ADC900comprises reference inputs990, input cell910, comparator balance switches930, comparator935, and reference cell985, input cell970and reference cell980. In one or more embodiments, input cell910comprises input charging switches, 1-unit capacitors, input balance switch915. In some embodiments, reference cell985comprises ref charging switches, M unit capacitors, ref balance switch960, and ref differential switches995.

As previously discussed, a 4-bit converter will have N=4 and M=2{circumflex over ( )}4=16-unit capacitors. So, in the present embodiment, if the unit cell cap is equal to C, then the total input/reference cap is M*C. In practice, the bit trials begin with none of the reference cells tied to the comparator935input and only one input cell910tied to comparator935input. This is called as the sign bit trial. Based on this result, the manner in which the reference cells be connected will be changed. Thereafter each trial the total number of input cells will be ‘doubled’ and the number of reference cells connected to the comparator is based on the bit trial results so far.

In one or more embodiments, input cell970comprises input charging switches, M−1-unit capacitors, input balance switch965. In some embodiments, reference cell985comprises ref charging switches, M unit capacitors, ref balance switch960. The circuitry configuration ofFIG.9represents the sign bit trial. As stated, the first trial is just to check polarity on the input. It is noted that input cell970and ref cell985do not play a part in the trial and that they are abstractions representing the remain capacitors which are not used in the present trial.

FIG.10depicts an exemplary schematic of a successive approximation ADC in differential mode, in accordance with others embodiments of the disclosure provided herein. SAR-ADC1000comprises reference inputs1090, input cell1010, comparator balance switches1030, comparator1035, and reference cell1085, input cell1070and reference cell1080. In one or more embodiments, input cell1010comprises input charging switches, 2-unit capacitors, input balance switch1015. In some embodiments, reference cell1085comprises ref charging switches, 1-unit capacitors, ref balance switch1060, and differential switches.

As discussed, each trial the total number of input cells will be doubled and the number of reference cells connected to the comparator is based on the bit trial results so far. So,FIG.10shows the first bit trial (MSB) after sign trial. Accordingly, the input cell1010connected to comparator is equal to 1×2=2C. And the reference cap is 1C. The capacitors in input cell1070and ref cell1080are not yet part of the bit trial circuitry.

In one or more embodiments, input cell1070comprises input charging switches, M−2-unit capacitors, input balance switch1065. In some embodiments, reference cell1080comprises ref charging switches, M−1-unit capacitors, ref balance switch1075. The circuitry configuration ofFIG.10represents the first trial after the sign bit trial, i.e., the most significant bit.

Pursuant to the algorithm, 2 input cells are compared to 1 ref cell. The result of which determines the number of ref cells in the next trial, as previously described. Input and ref charging switches are open while balance switches1015,1060remain closed. Meanwhile switches from input cell1010and ref cell1085permit conductivity to the inputs of comparator435.

FIG.11depicts an exemplary schematic of a successive approximation ADC in differential mode, in accordance with others embodiments of the disclosure provided herein. SAR-ADC1100comprises reference inputs1190, input cell1110, comparator balance switches1130, comparator1135, and reference cell1185, input cell1150and reference cell1180. In one or more embodiments, input cell1110comprises input charging switches, 4-unit capacitors, input balance switch1115. In some embodiments, reference cell1185comprises ref charging switches, 1-unit capacitors, ref balance switch1160.

As discussed, each trial the total number of input cells will be doubled and the number of reference cells connected to the comparator is based on the bit trial results so far. So,FIG.11shows the third bit trial after sign and MSB trials, therefore the input cap connected to comparator is equal to 1×2×2×2=8C. And the reference cell585cap is 1, because MSB trial resulted in 0)+0(previous trial)+1(current trial)=1C. The capacitors in input cell1170and ref cell1180are not yet part of the bit trial circuitry.

In one or more embodiments, input cell1170comprises input charging switches, M−4-unit capacitors, input balance switch1165. In some embodiments, reference cell1180comprises ref charging switches, M−1-unit capacitors, ref balance switch575. The circuitry configuration ofFIG.11represents the second trial after the sign bit trial, i.e., the second most significant bit. Pursuant to the algorithm, 4 input cells are compared to 1 ref cell. The result of which determines the number of ref cells in the next trial. Input and ref charging switches are open while balance switches1115,1160remain closed. Meanwhile switches from input cell1110and ref cell1185permit conductivity to the inputs of comparator1135.

FIG.12depicts an exemplary schematic of a successive approximation ADC600in differential mode, in accordance with others embodiments of the disclosure provided herein. SAR-ADC1200comprises reference inputs1290, input cell1210, comparator balance switches1230, comparator1235, and reference cell1285, input cell1250and reference cell1280. In one or more embodiments, input cell1210comprises input charging switches, M unit capacitors, input balance switch1215. In some embodiments, reference cell1285comprises ref charging switches, 1-unit capacitors, ref balance switch1260.

The circuitry configuration ofFIG.12represents the least significant bit (LSB) trial. In the present example, it is noted that the previous trials resulted in 0. That is, MSB-2 Trial, MSB, MSB-1=0. Pursuant to the algorithm, all M input cells are compared to 1 ref cells, the number of which is dependent on the previous trials. Input and ref charging switches are open while balance switches1215,1260remain closed. Meanwhile switches from input cell1210and ref cell1285permit conductivity to the inputs of comparator1235. It is noted that M−1-unit capacitors of ref cell1280remain unused in the trials.

FIG.13depicts an exemplary schematic of a successive approximation ADC1300, in accordance with others embodiments of the disclosure provided herein. In some embodiments, SAR ADC1300integrates existing elements, such as, Sub DAC1310which may use similar switching scheme as described for main DAC1340and1350earlier, CC capacitor bank1320, feedback capacitors (CFB)1330, and residue amplifier (RA)13601360into its architecture. Nominally, the present disclosure obviates these elements, as one skilled in the art can appreciate. However, the present embodiment exemplifies the present disclosures versatility into existing architectures while still retaining many benefits. Specifically, top and bottom plate blocks1340,1350are in electrical communication with comparator1335, RA1360, and disposed between CC1320and CFB1320.

In several embodiments, top plate capacitor attenuation is dependent on output code. All previous architectures give 6 dB signal loss at dac top plate node for input sampling capacitor equal to reference sampling capacitor or 2× noise gain for comparator/RA at ADC input, in contrast to the present architectures. For the present architecture, the noise gain scales with input from 1 (normal) to 2 as input goes from 0 to full-scale. The present disclosure provides for lower cap attenuation for smaller inputs. That is, smaller Inputs gets lower Noise Gain→High Dynamic Range. Another advantage is that the architecture is symmetric and Interchangeable INP and REF paths.

This enables redundancy to be applied only when it is needed as well. In traditional SAR implementations the redundant capacitors need to be proportionately large as the redundancy range that it provides and this redundant capacitor is present at the comparator input irrespective of whether there is a settling error or not. Adding capacitors to the comparator input which are not sampling the analog input acts as attenuation capacitors that reduces the signal swing and therefore the signal to noise ratio of the ADC. The new SAR algorithm enables an efficient use of redundancy that is added only when needed and the magnitude of redundancy capacitor is independent of the redundancy range that it provides.

Select Examples

Example 1 provides a method for performing SAR DAC comparison in a SAR ADC comprising dividing an input signal into a plurality of a predetermined number of input cells dividing a reference signal into a plurality of the predetermined number of reference cells, and adding 2N−1input cells to an input sum adding 2Nreference cells to a reference sum, comparing the input sum to the reference sum.

Example 2 provides a method for performing SAR DAC comparison in a SAR ADC according to any of the preceding and/or proceeding examples, and if the input sum is less than the reference sum, subtracting the 2N reference cells from the reference sum.

Example 3 provides a method for performing SAR DAC comparison in a SAR ADC according to any of the preceding and/or proceeding examples further comprising incrementing N.

Example 4 provides a method for performing SAR DAC comparison in a SAR ADC according to any of the preceding and/or proceeding examples further comprising iterating through N until 2N−1 equals or exceeds the predetermined number of input cells.

Example 5 provides a method for performing SAR DAC comparison in a SAR ADC according to any of the preceding and/or proceeding examples, wherein N is a normal number.

Example 6 provides a method for performing SAR DAC comparison in a SAR ADC according to any of the preceding and/or proceeding examples, wherein N in as integer beginning with 1.

Example 7 provides a method for performing SAR DAC comparison in a SAR ADC according to any of the preceding and/or proceeding examples, wherein the input signal represents a voltage.

Example 8 provides a method for performing SAR DAC comparison in a SAR ADC according to any of the preceding and/or proceeding examples, wherein the input signal represents a charge.

Example 9 provides a method for performing SAR DAC comparison in a SAR ADC according to any of the preceding and/or proceeding examples, wherein the reference signal represents a voltage.

Example 10 provides a method for performing SAR DAC comparison in a SAR ADC according to any of the preceding and/or proceeding examples, wherein the reference signal represents a charge.

Example 11 provides a method for performing SAR DAC comparison in a SAR ADC according to any of the preceding and/or proceeding examples, wherein reference sum is an input to a comparator.

Example 12 provides a method for performing SAR DAC comparison in a SAR ADC according to any of the preceding and/or proceeding examples, wherein input sum is an input to a comparator.

Example 13 provides a method for performing SAR DAC comparison in a SAR ADC according to any of the preceding and/or proceeding examples further comprising producing a binary result from the comparison.

Example 14 provides a method for performing SAR DAC comparison in a SAR ADC according to any of the preceding and/or proceeding examples further comprising producing an N-bit number resulting from the comparison.

Example 15 provides a method for performing SAR DAC comparison in a SAR ADC according to any of the preceding and/or proceeding examples, wherein the N-bit number represents a digital sample of the input signal.

Example 16 provides a method for performing SAR DAC comparison in a SAR ADC according to any of the preceding and/or proceeding examples, wherein the input cells are divided equally.

Example 17 provides a method for performing SAR DAC comparison in a SAR ADC according to any of the preceding and/or proceeding examples, wherein the reference cells are divided equally.

Example 18 provides for a SAR DAC in a SAR ADC comprising a plurality of input capacitors configured to equally divide an input signal, a plurality of reference capacitors configured to equally divide a reference signal, and a comparator having a reference lead and input lead.

Example 19 provides a SAR DAC in a SAR ADC according to any of the preceding and/or proceeding examples further comprising a controller configured to electrically connect 2N−1input capacitors to the input lead, electrically connect 2Nreference capacitors to the reference lead, evaluate a comparison of the input lead to the reference lead, increment N, if the input lead is less than the reference lead, disconnect the 2Nreference capacitor from the reference lead; and iterate through N until 2N−1equals or exceeds the number of input capacitors.

Example 20 provides a SAR DAC in a SAR ADC according to any of the preceding and/or proceeding examples, wherein the input signal represents at least one of a voltage, current, and charge.

Example 21 provides a SAR DAC in a SAR ADC according to any of the preceding and/or proceeding examples, wherein the reference signal represents at least one of a voltage, current, and charge.

Example 22 provides a SAR DAC in a SAR ADC according to any of the preceding and/or proceeding examples, wherein the controller is configured to produce an N-bit number resulting from the comparison.

Example 23 provides a SAR DAC in a SAR ADC according to any of the preceding and/or proceeding examples, wherein the N-bit number represents a digital sample of the input signal.

Example 24 provides for an apparatus for performing SAR DAC comparison in a SAR ADC comprising a means for dividing an input signal into a plurality of a predetermined number of input cells, a means for dividing a reference signal into a plurality of the predetermined number of reference cells, a means for adding 2N−1 input cells to an input sum, a means for adding 2N reference cells to a reference sum, a means for comparing the input sum to the reference sum and if the input sum is less than the reference sum, subtracting the 2N reference cells from the reference sum, a means for incrementing N, and a means for iterating through N until 2N−1 equals or exceeds the predetermined number of input cells.

The above description of illustrated embodiments, including what is described in the Abstract, is not intended to be exhaustive or limiting as to the precise forms disclosed. While specific implementations of, and examples for, various embodiments or concepts are described herein for illustrative purposes, various equivalent modifications may be possible, as those skilled in the relevant art will recognize. These modifications may be made in light of the above detailed description, the Abstract, the Figures, or the claims.

Having thus described several aspects and embodiments of the technology of this application, it is to be appreciated that various alterations, modifications, and improvements will readily occur to those of ordinary skill in the art. Such alterations, modifications, and improvements are intended to be within the spirit and scope of the technology described in the application. For example, those of ordinary skill in the art will readily envision a variety of other means and/or structures for performing the function and/or obtaining the results and/or one or more of the advantages described herein, and each of such variations and/or modifications is deemed to be within the scope of the embodiments described herein.

Those skilled in the art will recognize or be able to ascertain using no more than routine experimentation, many equivalents to the specific embodiments described herein. It is, therefore, to be understood that the foregoing embodiments are presented by way of example only and that, within the scope of the appended claims and equivalents thereto, inventive embodiments may be practiced otherwise than as specifically described. In addition, any combination of two or more features, systems, articles, materials, kits, and/or methods described herein, if such features, systems, articles, materials, kits, and/or methods are not mutually inconsistent, is included within the scope of the present disclosure.

The foregoing outlines features of one or more embodiments of the subject matter disclosed herein. These embodiments are provided to enable a person having ordinary skill in the art (PHOSITA) to better understand various aspects of the present disclosure. Certain well-understood terms, as well as underlying technologies and/or standards may be referenced without being described in detail. It is anticipated that the PHOSITA will possess or have access to background knowledge or information in those technologies and standards sufficient to practice the teachings of the present disclosure.

The PHOSITA will appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes, structures, or variations for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. The PHOSITA will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

The above-described embodiments may be implemented in any of numerous ways. One or more aspects and embodiments of the present application involving the performance of processes or methods may utilize program instructions executable by a device (e.g., a computer, a processor, or other device) to perform, or control performance of, the processes or methods.

In this respect, various inventive concepts may be embodied as a computer readable storage medium (or multiple computer readable storage media) (e.g., a computer memory, one or more floppy discs, compact discs, optical discs, magnetic tapes, flash memories, circuit configurations in Field Programmable Gate Arrays or other semiconductor devices, or other tangible computer storage medium) encoded with one or more programs that, when executed on one or more computers or other processors, perform methods that implement one or more of the various embodiments described above.

The computer readable medium or media may be transportable, such that the program or programs stored thereon may be loaded onto one or more different computers or other processors to implement various ones of the aspects described above. In some embodiments, computer readable media may be non-transitory media.

Note that the activities discussed above with reference to the FIGURES which are applicable to any integrated circuit that involves signal processing (for example, gesture signal processing, video signal processing, audio signal processing, analog-to-digital conversion, digital-to-analog conversion), particularly those that can execute specialized software programs or algorithms, some of which may be associated with processing digitized real-time data.

In some cases, the teachings of the present disclosure may be encoded into one or more tangible, non-transitory computer-readable mediums having stored thereon executable instructions that, when executed, instruct a programmable device (such as a processor or DSP) to perform the methods or functions disclosed herein. In cases where the teachings herein are embodied at least partly in a hardware device (such as an ASIC, IP block, or SoC), a non-transitory medium could include a hardware device hardware-programmed with logic to perform the methods or functions disclosed herein. The teachings could also be practiced in the form of Register Transfer Level (RTL) or other hardware description language such as VHDL or Verilog, which can be used to program a fabrication process to produce the hardware elements disclosed.

In example implementations, at least some portions of the processing activities outlined herein may also be implemented in software. In some embodiments, one or more of these features may be implemented in hardware provided external to the elements of the disclosed figures, or consolidated in any appropriate manner to achieve the intended functionality. The various components may include software (or reciprocating software) that can coordinate in order to achieve the operations as outlined herein. In still other embodiments, these elements may include any suitable algorithms, hardware, software, components, modules, interfaces, or objects that facilitate the operations thereof.

Any suitably-configured processor component can execute any type of instructions associated with the data to achieve the operations detailed herein. Any processor disclosed herein could transform an element or an article (for example, data) from one state or thing to another state or thing. In another example, some activities outlined herein may be implemented with fixed logic or programmable logic (for example, software and/or computer instructions executed by a processor) and the elements identified herein could be some type of a programmable processor, programmable digital logic (for example, an FPGA, an erasable programmable read only memory (EPROM), an electrically erasable programmable read only memory (EEPROM)), an ASIC that includes digital logic, software, code, electronic instructions, flash memory, optical disks, CD-ROMs, DVD ROMs, magnetic or optical cards, other types of machine-readable mediums suitable for storing electronic instructions, or any suitable combination thereof.

In operation, processors may store information in any suitable type of non-transitory storage medium (for example, random access memory (RAM), read only memory (ROM), FPGA, EPROM, electrically erasable programmable ROM (EEPROM), etc.), software, hardware, or in any other suitable component, device, element, or object where appropriate and based on particular needs. Further, the information being tracked, sent, received, or stored in a processor could be provided in any database, register, table, cache, queue, control list, or storage structure, based on particular needs and implementations, all of which could be referenced in any suitable timeframe.

Any of the memory items discussed herein should be construed as being encompassed within the broad term ‘memory.’ Similarly, any of the potential processing elements, modules, and machines described herein should be construed as being encompassed within the broad term ‘microprocessor’ or ‘processor.’ Furthermore, in various embodiments, the processors, memories, network cards, buses, storage devices, related peripherals, and other hardware elements described herein may be realized by a processor, memory, and other related devices configured by software or firmware to emulate or virtualize the functions of those hardware elements.

Also, a computer may have one or more input and output devices. These devices can be used, among other things, to present a user interface. Examples of output devices that may be used to provide a user interface include printers or display screens for visual presentation of output and speakers or other sound generating devices for audible presentation of output. Examples of input devices that may be used for a user interface include keyboards, and pointing devices, such as mice, touch pads, and digitizing tablets. As another example, a computer may receive input information through speech recognition or in other audible formats.

When implemented in software, the software code may be executed on any suitable processor or collection of processors, whether provided in a single computer or distributed among multiple computers.

Computer program logic implementing all or part of the functionality described herein is embodied in various forms, including, but in no way limited to, a source code form, a computer executable form, a hardware description form, and various intermediate forms (for example, mask works, or forms generated by an assembler, compiler, linker, or locator). In an example, source code includes a series of computer program instructions implemented in various programming languages, such as an object code, an assembly language, or a high-level language such as OpenCL, RTL, Verilog, VHDL, Fortran, C, C++, JAVA, or HTML for use with various operating systems or operating environments. The source code may define and use various data structures and communication messages. The source code may be in a computer executable form (e.g., via an interpreter), or the source code may be converted (e.g., via a translator, assembler, or compiler) into a computer executable form.

In some embodiments, any number of electrical circuits of the FIGURES may be implemented on a board of an associated electronic device. The board can be a general circuit board that can hold various components of the internal electronic system of the electronic device and, further, provide connectors for other peripherals. More specifically, the board can provide the electrical connections by which the other components of the system can communicate electrically. Any suitable processors (inclusive of digital signal processors, microprocessors, supporting chipsets, etc.), memory elements, etc. can be suitably coupled to the board based on particular configuration needs, processing demands, computer designs, etc.

Other components such as external storage, additional sensors, controllers for audio/video display, and peripheral devices may be attached to the board as plug-in cards, via cables, or integrated into the board itself. In another example embodiment, the electrical circuits of the FIGURES may be implemented as standalone modules (e.g., a device with associated components and circuitry configured to perform a specific application or function) or implemented as plug-in modules into application-specific hardware of electronic devices.

Note that with the numerous examples provided herein, interaction may be described in terms of two, three, four, or more electrical components. However, this has been done for purposes of clarity and example only. It should be appreciated that the system can be consolidated in any suitable manner. Along similar design alternatives, any of the illustrated components, modules, and elements of the FIGURES may be combined in various possible configurations, all of which are clearly within the broad scope of this disclosure.

In certain cases, it may be easier to describe one or more of the functionalities of a given set of flows by only referencing a limited number of electrical elements. It should be appreciated that the electrical circuits of the FIGURES and its teachings are readily scalable and can accommodate a large number of components, as well as more complicated/sophisticated arrangements and configurations. Accordingly, the examples provided should not limit the scope or inhibit the broad teachings of the electrical circuits as potentially applied to a myriad of other architectures.

Interpretation of Terms

Elements other than those specifically identified by the “and/or” clause may optionally be present, whether related or unrelated to those elements specifically identified. Thus, as a non-limiting example, a reference to “A and/or B”, when used in conjunction with open-ended language such as “comprising” may refer, in one embodiment, to A only (optionally including elements other than B); in another embodiment, to B only (optionally including elements other than A); in yet another embodiment, to both A and B (optionally including other elements); etc.

Thus, as a non-limiting example, “at least one of A and B” (or, equivalently, “at least one of A or B,” or, equivalently “at least one of A and/or B”) may refer, in one embodiment, to at least one, optionally including more than one, A, with no B present (and optionally including elements other than B); in another embodiment, to at least one, optionally including more than one, B, with no A present (and optionally including elements other than A); in yet another embodiment, to at least one, optionally including more than one, A, and at least one, optionally including more than one, B (and optionally including other elements); etc.

As used herein, the term “between” is to be inclusive unless indicated otherwise. For example, “between A and B” includes A and B unless indicated otherwise.

Numerous other changes, substitutions, variations, alterations, and modifications may be ascertained to one skilled in the art and it is intended that the present disclosure encompass all such changes, substitutions, variations, alterations, and modifications as falling within the scope of the appended claims.

In order to assist the United States Patent and Trademark Office (USPTO) and, additionally, any readers of any patent issued on this application in interpreting the claims appended hereto, Applicant wishes to note that the Applicant: (a) does not intend any of the appended claims to invoke 35 U.S.C. § 112(f) as it exists on the date of the filing hereof unless the words “means for” or “steps for” are specifically used in the particular claims; and (b) does not intend, by any statement in the disclosure, to limit this disclosure in any way that is not otherwise reflected in the appended claims.

The present invention should therefore not be considered limited to the particular embodiments described above. Various modifications, equivalent processes, as well as numerous structures to which the present invention may be applicable, will be readily apparent to those skilled in the art to which the present invention is directed upon review of the present disclosure.