Driver circuit

A driver circuit is provided for preventing generation of a pass-through current in a CMOS output unit even if a power supply voltage VDD supplied from a low voltage power supply drops below a recommended operating power supply voltage. The driver circuit includes a level shift unit having PMOS transistors and NMOS transistors, and a CMOS output unit having a PMOS transistor and an NMOS transistor. The source, drain and gate of one PMOS transistor are respectively connected to a high voltage power supply, a first contact and a second contact. The source, drain and gate of a second PMOS transistor are respectively connected to a high voltage power supply, the second contact and the first contact. The source of one NMOS transistor is grounded, the drain thereof is connected to the first contact, and the gate thereof receives a low voltage signal. The source of a second NMOS transistor is grounded, the drain thereof is connected to the second contact, and the gate thereof receives a low voltage signal. In this driver circuit, the driving current of the one PMOS transistor is higher than the driving current of the one NMOS transistor.

BACKGROUND OF THE INVENTION

(1) Field of the Invention

The present invention relates to a driver circuit for driving a plasma display panel (PDP) or the like.

(2) Description of the Related Art

As shown inFIG. 1, a conventional PDP driver includes a level shift unit25, a CMOS output unit26and a low voltage control unit21.

The level shift unit25includes a PMOS transistor17and a PMOS transistor16. The sources of the transistors17and16are both connected to a high voltage power supply terminal22, the drains thereof are respectively connected to a contact IN5and a contact IN4, and the gate of one transistor is connected to the drain of the other transistor crosswise. The level shift unit25further includes an NMOS transistor20and an NMOS transistor19. The gates of these transistors20and19are respectively connected to one of a contact IN1and IN2of the low voltage control unit21, the drains thereof are respectively connected to the contact IN5and the contact IN4, and the sources thereof are both grounded.

The CMOS output unit26includes an NMOS transistor18and a PMOS transistor15. The gate of the NMOS transistor18is connected to a contact IN3of the low voltage control unit21, the drain thereof is connected to an output terminal24, and the source thereof is grounded, while the source of the PMOS transistor is connected to the high voltage power supply terminal22, the gate thereof is connected to the contact IN4, and the drain thereof is connected to the output terminal24.

The low voltage control unit21is connected to a low voltage power supply terminal27. An output load34is a capacitive load like a plasma display panel.

FIG. 2shows the waveforms of the input and output signals of the low voltage control unit21in the conventional PDP driver and the signals at the contacts IN4, IN5and the output terminal24.

Next, the operation of the conventional PDP driver is described below. It is assumed here that the signal IN inputted to the low voltage control unit21switches from High (VDD level in this case) to Low (GND level in this case). In this case, the NMOS transistor20is turned on by the signal IN1inputted from the low voltage control unit21and the potential of the contact IN5drops to the ground potential (GND), which turns on the PMOS transistor16. At the same time as the turn-on of the PMOS transistor16, the NMOS transistor16is turned off by the signal IN2inputted from the low voltage control unit21, and as a result, the potential of the contact IN4rises to the potential level of the high voltage power supply (VDDH), which turns off the PMOS transistor15. Furthermore, the NMOS transistor18is turned on by the signal IN3inputted from the low voltage control unit21, which causes the potential of the output terminal24to drop to the ground potential (GND).

Reversely, when the IN signal switches from High to Low, the NMOS transistor19is turned on by the signal IN2inputted from the low voltage control unit21. At the same time as the turn-on of the NMOS transistor19, the NMOS transistor20is turned off, the PMOS transistor17is turned on and the PMOS transistor16is turned off by the signal IN1. At that time, the potential of the contact IN4drops to the ground potential (GND), which turns on the PMOS transistor15. As a result, the potential of the output terminal24rises to the potential level of the high voltage power supply (VDDH), and the NMOS transistor18is turned off by the signal IN3.

In this case, the driving capability of each transistor in the level shift unit25is determined as follows.

The PMOS transistor16and the NMOS transistor19of which drains are connected to the CMOS output unit26have heavier driving load than the PMOS transistor17and the NMOS transistor20which are placed at the front side in the level shift unit25because the PMOS transistor16and the NMOS transistor19drive the CMOS output unit26. Therefore, the PMOS transistor16and the NMOS transistor19need to have higher driving capability than the PMOS transistor17and the NMOS transistor20(See Examined Japanese Patent Application Publication No. 6-91442).

When the potentials of IN4and IN5in the level shift unit25switch from High (VDDH level in this case) to Low (GND level in this case) and vice versa, namely from Low to High, pass-through current flows transiently through the PMOS transistor17and the NMOS transistor20and through the PMOS transistor16and the NMOS transistor19, respectively. In order to reduce this pass-through current, the potentials of IN4and IN5must be immediately switched to the potentials of stable values. Therefore, the NMOS transistors20and19need to have higher driving capabilities than the PMOS transistors17and16(See Laid-Open Patent Application Publication No. 2000-164730).

As described above, in the conventional PDP driver, the pass-through current hardly flows through the level shift unit25and the CMOS output unit26if the power supply voltage VDD supplied from the low voltage power supply to the low voltage power supply terminal27is within a range of recommended operating power supply voltages, that is, within a range of power supply voltages which ensure the normal operation of the circuit, and therefore the desired operation is achieved.

However, the power supply voltage VDD supplied from the low voltage power supply to the low voltage power supply terminal27may be maintained around the medium potential VLo that is lower than the rated value because the low voltage power supply is not started up or shut down immediately when the power is turned on or off. For example, in the case where the rated value of the power supply voltage VDD is 5V, when the power is turned on, the power supply voltage VDD supplied from the low voltage power supply to the low voltage power supply terminal27is sometimes maintained around the medium potential VLo of 2V during the transition in which the voltage VDD is turned off. In this case where the power supply voltage VDD which has been supplied from the low voltage power supply to the low voltage power supply terminal27becomes lower than the recommended operating power supply voltage and the High levels of IN1, IN2and IN3drop, the circuit operates differently from the above-mentioned desired operation.

As shown inFIG. 3, when an input voltage IN switches from High (VLo level in this case) to Low (GND level in this case), the input voltage IN1of the level shift unit25turns into High, so that the NMOS transistor20is turned on and the PMOS transistor16is turned on. On the contrary, the input voltage IN2of the level shift unit25turns into Low, so that the NMOS transistor19is turned off and the PMOS transistor17is turned off. If the power supply voltage VDD drops, it becomes impossible to secure the input voltage IN1that is sufficiently larger than the threshold voltage (VT) of the NMOS transistor20. Therefore, the potential of the contact IN5cannot switch to Low instantaneously and there is a period of time t0during which the potential of the contact IN5stays at the medium potential1(VDDL level in this case).

On the other hand, the driving capability of the PMOS transistor16is lower than that of the NMOS transistor19. In addition, since the potential of the contact IN5is not Low but stays at the medium potential1(VDDL level) during the period t0, the PMOS transistor16is in an incomplete ON state and thus its driving current is reduced. Therefore, the PMOS transistor16which is in the incomplete ON state cannot supply the current sufficiently larger than the current driven by the NMOS transistor19which is in an incomplete OFF state, and thus the PMOS transistor16cannot be turned on instantaneously. As a result, the potential of the contact IN4does not rise from Low (GND level in this case) to High (VDDH level in this case) immediately and there is a period of time t0during which it stays at the medium potential2(VDDM level in this case).

During this period t0, the PMOS transistor15of the CMOS output unit26cannot be turned off completely due to the potential at the contact IN4, and the NMOS transistor18of the CMOS output unit26is in an ON state by the input signal from IN3. As a result, both the PMOS transistor15and the NMOS transistor18of the CMOS output unit26are turned on, and therefore the potential of the output terminal24does not drop completely to the ground potential but stays at the medium potential (VoutM level in this case). Therefore, a large amount of pass-through current flows from the high voltage power supply (VDDH) side to the ground potential (GND) side of the CMOS output unit26. This pass-through current causes a breakdown of the PDP driver and the image deterioration of the plasma display panel.

This problem is very serious particularly when the power supplied to the PDP driver is turned off. As shown inFIG. 4, after the power is turned off, the voltage of the low voltage power supply VDD declines with a small time constant (namely, fast), while the voltage of the high voltage power supply VDDH declines with a large time constant (namely, slowly), according to the amount of load put on the high voltage power supply VDDH and the low voltage power supply VDD, respectively. Therefore, the gate voltage of the NMOS transistor20declines fast while the high voltage is being supplied from the high voltage power supply VDDH to the CMOS output unit26, and the PMOS transistor15is not turned off completely, which results in a flow of pass-through current in the CMOS output unit26.

SUMMARY OF THE INVENTION

The present invention has been conceived in view of the above problem, and an object of the present invention is to provide a driver circuit for preventing the flow of pass-through current through the CMOS output unit even if the power supply voltage supplied from the low voltage power supply becomes lower than the recommended operating power supply voltage.

In order to solve the above problem and achieve the above object, the driver circuit according to the present invention includes: (a) a level shift unit including a first P-channel metal-oxide semiconductor (PMOS) transistor, a second PMOS transistor, a first N-channel metal-oxide semiconductor (NMOS) transistor and a second NMOS transistor, wherein a source, a drain and a gate of the first PMOS transistor are respectively connected to a high voltage power supply, a first contact and a second contact, a source, a drain and a gate of the second PMOS transistor are respectively connected to the high voltage power supply, the second contact and the first contact, a source of the first NMOS transistor is grounded, a drain of the first NMOS transistor is connected to the first contact, and a gate of the first NMOS transistor receives a first signal, and a source of the second NMOS transistor is grounded, a drain of the second NMOS transistor is connected to the second contact, and a gate of the second NMOS transistor receives a second signal; (b) a low voltage control unit, which is connected to a low voltage power supply, operable to output, according to an input signal, the first signal to the gate of the first NMOS transistor and the second signal to the gate of the second NMOS transistor; and (c) a push-pull output unit operable to perform a switching operation based on a signal at the first contact of the level shift unit and a third signal outputted from the low voltage control unit, wherein a driving current of the first PMOS transistor is higher than a driving current of the first NMOS transistor.

As described above, in the driver circuit according to the present invention, the driving current of the first PMOS transistor is larger than the driving current of the first NMOS transistor. Therefore, it is possible to prevent the generation of pass-through current in the CMOS output unit even if the power supply voltage VDD becomes lower than the recommended operating power supply voltage.

It should be noted that the driving current of a MOS transistor is a drain current that flows when the MOS transistor is on. As specific methods for determining the value of this driving current, there are a method for designing a MOS transistor so that the driving capability (mutual conductance) of the MOS transistor itself becomes an appropriate value, a method for connecting a resistive element that limits the drain current flow through the MOS transistor, as a load on the MOS transistor, and the like.

The above-mentioned push-pull output unit is a transistor output circuit in which two transistors are connected in series between the power supply and the ground, and also refers to a totem-pole circuit, a CMOS circuit or the like.

As described above, it becomes possible, according to the present invention, to provide a driver circuit for preventing the generation of pass-through current in the CMOS output unit even if the power supply voltage becomes lower than the recommended operating power supply voltage.

Particularly, since the pass-through current does not flow through the CMOS output unit in the case where the driver circuit of the present invention is applied to a PDP driver, so it becomes possible to prevent the breakdown of the PDP driver and image deterioration of the plasma display. Therefore, the reliability of the PDP driver and the plasma display can be improved.

As further information about technical background to this application, the disclosures of Japanese Patent Application No. 2004-249733 filed on Aug. 30, 2004 and Japanese Patent Application No. 2005-237952 filed on Aug. 18, 2005, including specifications, drawings and claims, are incorporated herein by reference in their entirety.

DESCRIPTION OF THE PREFERRED EMBODIMENT(S)

The best mode for carrying out the present invention is described below with reference to the diagrams.

First Embodiment

First, a structure of a PDP driver in the first embodiment is described with reference toFIG. 5.

FIG. 5is a structure diagram of the PDP driver in the first embodiment. The PDP driver in the first embodiment, which is one example of the driver circuit of the present invention, includes a level shift unit13, a CMOS output unit14, and a low voltage control unit7.

The level shift unit13includes a PMOS transistor3and a PMOS transistor2. The sources of these transistors3and2are both connected to a high voltage power supply terminal9, the drains thereof are respectively connected to the contact IN5and the contact IN4, and the gate of one transistor is connected to the drain of the other transistor crosswise. The level shift unit13further includes an NMOS transistor6and an NMOS transistor5. The gates of these transistors6and5are respectively connected to one of the contact IN1or IN2of the low voltage control unit7, the drains thereof are respectively connected to the contact IN5and the contact IN4, and the sources thereof are both grounded.

The CMOS output unit14is one example of a push-pull output unit which performs switching operations based on the signal at the contact IN4of the level shift unit13and the signal IN3outputted from the low voltage control unit7. The CMOS output unit14includes an NMOS transistor4and a PMOS transistor1. The gate of the NMOS transistor4is connected to the contact IN3of the low voltage control unit7, the drain thereof is connected to the output terminal12, and the source thereof is connected to the ground potential terminal11. The source of the PMOS transistor1is connected to the high voltage power supply terminal9, the gate thereof is connected to the contact IN4, and the drain thereof is connected to the output terminal12.

The low voltage control unit7is connected to the low voltage power supply terminal10. The output load34indicates a capacitive load like a plasma display panel.

Here, the driving capabilities of the PMOS transistor2, the PMOS transistor3, the NMOS transistor5and the NMOS transistor6in the level shift unit13are set in the following order. To be more specific, the driving capabilities of the PMOS transistor3, the NMOS transistor6, the NMOS transistor5and the PMOS transistor2increase, in that order from lowest to highest. The driving capability of a transistor is determined by the length of the side of a source region52facing a drain region53, that is, the length of a gate width54, as shown in the plan view of the structure of a MOS transistor inFIG. 6. For example, by setting the gate width of each transistor in the level shift unit13in the above order of the PMOS transistor3narrowest, the NMOS transistor6, the NMOS transistor5and the PMOS transistor2widest, the driving capabilities are set in the above order. It should be noted that a driving capability denotes a mutual conductance of a transistor, gm=ID/VGS, that is the property indicating an amount of current ID relative to the input voltage VGS between the gate and source. The driving capability can also be changed by changing the gate length55shown inFIG. 6.

Next, the operation of the PDP driver in the first embodiment is described with reference toFIG. 7.

Since the operation of the PDP driver in the present embodiment is same as that of the conventional PDP driver in the case where the power supply voltage VDD supplied from the low voltage power supply is within a range of recommended operating power supply voltages, the description thereof is not repeated here. A description is given below of the operation of the PDP driver in the present embodiment in the case where the power supply voltage VDD becomes VLo that is lower than the recommended operating power supply voltage because the low voltage power supply is not started up or shut down immediately when the power supply is turned on or off.

FIG. 7is a diagram showing the waveforms of the input and output signals at the low voltage control unit7and the signals at the contacts IN4and IN5and the output terminal12in the case where the power supply voltage VDD becomes VLo that is lower than the recommended operating power supply voltage.

When the input voltage IN switches from High (VLo level in this case) to Low (GND level in this case), the signal IN1outputted from the low voltage control unit7is switched to High, so that the NMOS transistor6is turned on and the PMOS transistor3is turned off. On the other hand, the signal IN2outputted from the low voltage control unit7is switched to Low, so that the NMOS transistor5is turned off and the PMOS transistor2is turned on. At this time, the driving capability of the NMOS transistor6is higher than the driving capability of the PMOS transistor3, but sufficient threshold voltage (VT) cannot be secured at the NMOS transistor6because the input voltage of IN1has dropped. Therefore, if the driving capability of the PMOS transistor2is lower than the driving capability of the NMOS transistor5as is the case of the conventional driver, the potential of the contact IN5is not changed to Low instantaneously but is maintained at the medium potential1as shown inFIG. 3(VDDL level in this case).

However, in the first embodiment, the driving capability of the PMOS transistor2is higher than that of the NMOS transistor5. Therefore, even if the potential at the contact IN5is maintained at the medium potential1and the PMOS transistor2is in an incomplete ON state, the PMOS transistor2can supply the current sufficiently larger than the current driven by the NMOS transistor5which is in an incomplete OFF state, and thus the PMOS transistor2can be turned on instantaneously. As a result, the potential at the contact IN4rises to High (VDDH level in this case) immediately, so that the PMOS transistor3is turned off and the potential at the contact IN4changes to Low (GND level in this case) immediately. Therefore, there is no period of time t0during which the potential stays at the medium potential1or2as shown inFIG. 3.

Accordingly, when IN switches from High to Low, the potential at the contact IN4switches to High (VDDH level) instantaneously, and therefore the PMOS transistor1in the CMOS output unit14is completely turned off instantaneously. Also, the NMOS transistor4in the CMOS output unit14is turned on according to the signal inputted from IN3, and therefore the potential at the output terminal12completely drops to ground potential (GND). As a result, no pass-through current flows through the CMOS output unit14.

Accordingly, it becomes possible to prevent the breakdown of the PDP driver and the image deterioration of the plasma display panel (output load34) and thus improve the reliability of the PDP driver and the plasma display panel.

As described above, the driving capabilities of respective transistors in the level shift unit13, that is, the PMOS transistor3, the NMOS transistor6, the NMOS transistor5and the PMOS transistor2, increase in that order from lowest to highest. Therefore, even if the power supply voltage VDD drops to VLo that is lower than the recommended operating power supply voltage, each transistor in the level shift unit13and the CMOS output unit14is switched from ON to OFF or from OFF to ON instantaneously upon switching of the input voltage IN from High to Low. In other words, both the PMOS transistor1and the NMOS transistor4are never switched on at the same time in the CMOS output unit14. As a result, no pass-through current flows through the CMOS output unit14, and therefore it becomes possible to prevent the breakdown of the PDP driver and the image deterioration of the plasma display panel (output load34).

It should be noted that the case where the input voltage IN is switched from High to Low has been described in the above first embodiment. The same is true in the case where IN is switched from Low to High. Since the driving capability of each transistor in the level shift unit13is also set as mentioned above in this case, each transistor is switched from ON to OFF or from OFF to ON instantaneously even if the voltage from the low voltage power supply drops to VLo. Therefore, no pass-through current flows through the CMOS output unit14, and therefore it becomes possible to prevent the breakdown of the PDP driver and the image deterioration of the plasma display panel (output load34).

Second Embodiment

A structure of a PDP driver in the second embodiment is described with reference toFIG. 8.

FIG. 8is a structure diagram of the PDP driver in the second embodiment. The PDP driver in the second embodiment has the same structure as the PDP driver in the first embodiment except that the former includes a power supply voltage detection circuit8.

The power supply voltage detection circuit8is connected to the low voltage power supply terminal10and the low voltage control unit7.FIG. 9shows the details of the power supply voltage detection circuit8. The power supply voltage detection circuit8compares, using a hysteresis converter30, a voltage of a reference voltage source33with a voltage obtained by dividing a voltage of the low voltage power supply terminal10using a resistor31and a resistor32. The power supply voltage detection circuit8outputs a control signal to the output terminal29based on the comparison result obtained from the hysteresis converter30.

FIG. 10is a timing chart showing the operation of the power supply voltage detection circuit8. The power supply voltage detection circuit8outputs a control signal which changes from Low to High and from High to Low according to the change in the power supply voltage VDD of the low voltage power supply terminal10. To be more specific, the control signal stays at Low level during a period in which the power supply voltage VDD changes from the ground voltage to a predetermined potential (VTON potential), and switches to High level when the power supply voltage VDD exceeds the VTON potential because it continues to rise. The control signal stays at High level during a period in which the power supply voltage VDD reaches and stays at the rated value and then begins to drop from the rated value below the VTON potential, and switches to Low level when the power supply voltage VDD drops to the VTOFF potential that is lower than VTON potential.

FIG. 11is a structure diagram of the low voltage control unit7. In the low voltage control unit7, a switch (SW)44selects a conversion circuit43when the control signal which is inputted to a signal detection circuit41from the power supply voltage detection circuit8turns into High level. The conversion circuit43converts an input signal IN as is the case with the first embodiment. The signals IN1, IN2and IN3from the conversion circuit43are outputted to the gates of the NMOS transistor6, the NMOS transistor5and the NMOS transistor4, which results in the same operations as those in the first embodiment.

On the other hand, when the voltage from the low voltage power supply drops and the control signal which is inputted to the signal detection circuit41from the power supply voltage detection circuit8turns into Low level, the switch (SW)44selects a fixed signal output circuit42. The fixed signal output circuit42outputs the signal IN1of High level (VDD level, for example), the signal IN2of Low level (GND level) and the signal IN3of Low level (GND level), regardless of the input signal IN.

When the signal IN1turns into High level, the NMOS transistor6is turned on and the potential at the contact IN5drops to the ground potential (GND), and thus the PMOS transistor2is turned on. As a result, the potential at the contact IN4is raised to the potential at the high voltage power supply (VDDH) and the PMOS transistor1is turned off. According to the signal IN3of Low level, the NMOS transistor4is turned off. The NMOS transistor5is also turned off according to the signal IN2of Low level. As a result, the PMOS transistor1and the NMOS transistor4are turned off, and therefore no pass-through current is generated in the CMOS output unit14.

The threshold voltage (VT) of a MOS transistor may fluctuate due to variations in manufacturing processes. In such a case, if the voltage at the low voltage power supply terminal10significantly drops, it becomes impossible to meet the prerequisite that the driving capability of the PMOS transistor2is higher than that of the NMOS transistor5. Therefore, the PMOS transistor2cannot supply the current sufficiently larger than the current driven by the NMOS transistor5.

However, if the voltage at the low voltage power supply terminal10significantly drops, the power supply voltage detection circuit8outputs the control signal of Low level, while the low voltage control unit7outputs the signal IN1of High level, the signal IN2of Low level and the signal IN3of Low level. Therefore, as described above, the PMOS transistor1and the NMOS transistor4are turned off. As a result, it becomes possible to prevent the generation of the pass-through current in the CMOS output unit14even if the PMOS transistor2cannot supply the current sufficiently larger than the current driven by the NMOS transistor5, as described above.

It should be noted that the PDP driver in the second embodiment not only includes the power supply voltage detection circuit8in addition to the elements of the PDP driver in the first embodiment, but also includes the low voltage control unit7which outputs the signal IN1of High level, the signal IN2of Low level and the signal IN3of Low level when the power supply voltage detection circuit8outputs the control signal of High level. However, the power supply voltage detection circuit8may be provided not only in the PDP driver in the first embodiment but also in the conventional PDP driver. In this case, the low voltage control unit21is designed in advance so as to output the signal IN1of High level, the signal IN2of Low level and the signal IN3of Low level when the control signal of High level is inputted from the power supply voltage detection circuit8. By doing so, it becomes possible to prevent the generation of the pass-through current in the CMOS output unit26by the operations of the power supply voltage detection circuit8and the low voltage control unit21, irrespective of the relationship of the driving capabilities of the NMOS transistor19, the NMOS transistor20, the PMOS transistor16and the PMOS transistor17in the level shift unit25, even if the power supply voltage VDD drops below the recommended operating power supply voltage. As a result, it becomes possible to easily design the driving capabilities of respective PMOS and NMOS transistors in the level shift units13and25.

Third Embodiment

A structure of a PDP driver in the third embodiment is described with reference toFIG. 12.

FIG. 12is a structure diagram of the PDP driver in the third embodiment. The PDP driver in the third embodiment has the same structure as the PDP driver in the first embodiment except for a level shift unit113.

The level shift unit113of the present embodiment corresponds to the circuit in which the PMOS transistor3in the level shift unit13of the first embodiment is substituted by a PMOS transistor103and a PMOS transistor103awhich are connected in series.

The PMOS transistor103is, for example, a PMOS transistor having the driving capability equivalent to that of the NMOS transistor6that is the other half of a complementary pair.

The PMOS transistor103ais one example of a resistive element. The source of the PMOS transistor103ais connected to the high voltage power supply VDDH, the drain thereof is connected to the source of the PMOS transistor103, and the gate thereof is connected to the gate of the PMOS transistor103. When a signal of Low level is inputted into the gates of these PMOS transistors103and103a, both of them are turned on and thus the ON-resistance between the drain and the source of the PMOS transistor103afunction as a load resistor of the PMOS transistor103.

The circuit that is a combination of these PMOS transistor103and PMOS transistor103aperforms the same function as the PMOS transistor3in the first embodiment. In other words, in the present embodiment, the driving capability of the PMOS transistor103itself is equivalent to that of the NMOS transistor6that is the other half of the complementary pair. However, since the PMOS transistor103ais connected as a load resistor for this PMOS transistor103, the driving current (drain current that flows when the PMOS transistor103is ON) of the PMOS transistor103is limited. As a result, the driving current that flows through the PMOS transistor103aand the PMOS transistor103is lower than the current that flows through the NMOS transistor6.

Based on the above fact, the PDP driver in the present embodiment produces the same effects as those in the first embodiment. To be more specific, since the driving current of the NMOS transistor6is higher than that of the PMOS transistor3, the ON state of the NMOS transistor6is securely maintained when the signal IN1is High even if the voltage of the low voltage power supply drops as does it immediately after the power is turned off. Furthermore, since the driving current of the PMOS transistor2is higher than that of the NMOS transistor5, the ON state of the PMOS transistor2is securely maintained, and as a result, the high voltage VDDH is supplied to the gate of the PMOS transistor1in the CMOS output unit14, the OFF state of the PMOS transistor1is securely maintained, and therefore the flow of the pass-through current through the CMOS output unit14is avoided.

It should be noted that in the present embodiment, the gate of the PMOS transistor103ais connected to the gate of the PMOS transistor103, but the present invention is not limited to such connection. All that is required of the PMOS transistor103ais function as a load resistor. The gate of the PMOS transistor103ajust has to be connected to a predetermined Low potential (for example, GND or the like).

Like the level shift unit113ashown inFIG. 13, the PMOS transistor103ain the present embodiment may be substituted by a resistor110having the same resistance value, which allows suppression of the drain current that flows through the PMOS transistor103.

Fourth Embodiment

Next, a structure of a PDP driver in the fourth embodiment is described with reference toFIG. 14.

FIG. 14is a structure diagram of the PDP driver in the fourth embodiment. The PDP driver in the fourth embodiment has the same structure as the PDP driver in the third embodiment except for a level shift unit114.

The level shift unit114of the present embodiment corresponds to the circuit in which the NMOS transistor6in the level shift unit113of the third embodiment is substituted by an NMOS transistor106and an NMOS transistor106a.

The NMOS transistor106is, for example, an NMOS transistor having the driving capability equivalent to that of the NMOS transistor5which is placed in the subsequent stage.

The NMOS transistor106ais one example of a resistive element. The source of the NMOS transistor106ais connected to the low voltage power supply VDD, the drain thereof is connected to the source of the NMOS transistor106, and the gate thereof is connected to the gate of the NMOS transistor106. When a signal of High level is inputted into the gates of these NMOS transistors106and106a, both of them are turned on and thus the ON-resistance components between the drain and the source of the NMOS transistor106afunction as a load resistor of the NMOS transistor106.

The circuit that is a combination of these NMOS transistor106and NMOS transistor106aperforms the same function as the NMOS transistor6in the third embodiment. In other words, in the present embodiment, the driving capability of the NMOS transistor106itself is equivalent to that of the NMOS transistor5that is placed in the subsequent stage. However, since the NMOS transistor106ais connected as a resistive element for this NMOS transistor106, the driving current (drain current that flows when the NMOS transistor106is ON) of the NMOS transistor106is limited. As a result, the driving current that flows through the NMOS transistor106and the NMOS transistor106ais lower than the current that flows through the NMOS transistor5.

It should be noted that the PMOS transistor103aand the NMOS transistor106aare designed so that the relationship between the driving currents of the PMOS transistor103and the NMOS transistor106becomes equal to that in the third embodiment. In other words, the driving current of the NMOS transistor106is higher than that of the PMOS transistor103.

Based on the above, the PDP driver in the present embodiment produces the same effects as those in the first embodiment. To be more specific, since the driving current of the NMOS transistor106is higher than that of the PMOS transistor103, the ON state of the NMOS transistor106is securely maintained when the signal IN1is High even if the voltage of the low voltage power supply drops as does it immediately after the power is turned off. Furthermore, since the driving current of the PMOS transistor2is higher than that of the NMOS transistor5, the ON state of the PMOS transistor2is securely maintained, and as a result, the high voltage VDDH is supplied to the gate of the PMOS transistor1in the CMOS output unit14, the OFF state of the PMOS transistor1is securely maintained, and therefore the flow of the pass-through current through the CMOS output unit14is avoided.

It should be noted that in the present embodiment, the gate of the PMOS transistor106ais connected to the gate of the NMOS transistor106, but the present invention is not limited to such connection. All that is required of the NMOS transistor106ais function as a load resistor. The gate of the NMOS transistor106ajust has to be connected to a predetermined high potential (for example, CDD or the like).

Like the level shift unit114ashown inFIG. 15, the NMOS transistor106ain the present embodiment may be substituted by a resistor111having the same resistance value, which allows suppression of the drain current that flows through the NMOS transistor106.

Although the driver circuit of the present invention has been described in detail based on the above first to fourth embodiments, those skilled in the art will readily appreciate that many modifications are possible in these exemplary embodiments without materially departing from the novel teachings and advantages of this invention. Accordingly, all such modifications are intended to be included within the scope of this invention.

For example, the PMOS transistor3of the first embodiment is substituted by the PMOS transistor103and the PMOS transistor103ain the third embodiment, and the NMOS transistor6is additionally substituted by the NMOS transistor106and the NMOS transistor106ain the fourth embodiment. However, the present invention is not limited to such substitutions of these transistors. The PMOS transistor2and the NMOS transistor5may also be substituted in the same manner. Furthermore, the four MOS transistors in the level shift unit may be substituted by a combination of any of these MOS transistors and a resistor. In short, each MOS transistor may be implemented singly or in combination with a resistive element (a MOS transistor or a resistor), as long as respective MOS transistors are designed so that the driving capabilities of the PMOS transistor3, the NMOS transistor6, the NMOS transistor5and the PMOS transistor2increase in that order, from lowest to highest.

Furthermore, the above first to fourth embodiments have been described taking as an example the case of using the push-pull output unit (CMOS output unit14) in which the PMOS transistor1and the NMOS transistor4are connected in series between the high voltage power supply (VDDH) and the ground potential (GND). However, the present invention is not limited to this case, and may be implemented using a push-pull output unit in which two transistors of the same type (for example, NMOS transistors, PMOS transistors, bipolar transistors, or IGBTs (insulated gate bipolar transistors)) are connected in series and the polarity of one of the control signals of the transistor on the side of the high voltage power supply (VDDH) and the transistor on the side of the ground potential (GND) is reversed.

INDUSTRIAL APPLICABILITY

The driver circuit according to the present invention is useful as a driver circuit for outputting a high voltage driving signal, and in particular, as a PDP driver or the like for driving a plasma display panel.