Method and system for supporting peripheral component interconnect (PCI) peer-to-peer access across a PCI host bridge supporting multiple PCI buses

A method and system for supporting multiple Peripheral Component Interconnect (PCI) local buses through a single PCI host bridge having multiple PCI interfaces within a data-processing system are disclosed. In accordance with the method and system of the present invention, a processor and a system memory are connected to a system bus. First and second PCI local buses are connected to the system bus through a PCI host bridge. The first and second PCI local buses have sets of in-line electronic switches, dividing the PCI local buses into PCI local bus segments supporting a plurality of PCI peripheral component slots for connecting PCI devices. The sets of in-line electronic switches are open and closed in accordance with bus control logic within the PCI host bridge allowing up to fourteen or more PCI peripheral component slots for connecting up to fourteen PCI devices to have access through a single PCI host bridge to the system bus. An internal PCI-to-PCI bridge is provided to allow a PCI device to share data with another PCI device as peer-to-peer devices across the first and second PCI local bus segments.

BACKGROUND OF THE INVENTION
 1. Technical Field
 The present invention relates in general to a method and system for data
 processing and, in particular, to a method and system for handling
 multiple Peripheral Component Interconnect (PCI) local bus accesses within
 a computer system. Still more particularly, the present invention relates
 to a method and system for handling PCI peer-to-peer access across
 multiple PCI local buses across a PCI host bridge supporting multiple PCI
 Buses within a computer system.
 2. Description of the Related Art
 A computer system typically includes several types of buses, such as a
 system bus, local buses, and peripheral buses. Various electronic circuit
 devices and components are connected with each other via these buses such
 that intercommunication may be possible among all of these devices and
 components.
 In general, a central processing unit (CPU) is attached to a system bus,
 over which the CPU communicates directly with a system memory that is also
 attached to the system bus. In addition, a local bus may be used for
 connecting certain highly integrated peripheral components rather than the
 slower standard expansion bus. One such local bus is known as the
 Peripheral Component Interconnect (PCI) bus. Under the PCI local bus
 standard, peripheral components can directly connect to a PCI local bus
 without the need for glue logic, the "profusion of chips needed to match
 the signals between different integrated circuits." Thus, PCI provides a
 bus standard on which high-performance peripheral devices, such as
 graphics devices and hard disk drives, can be coupled to the CPU, thereby
 permitting these high-performance peripheral devices to avoid the general
 access latency and the bandwidth constraints that are associated with an
 expansion bus. An expansion bus such as an Industry Standard Architecture
 (ISA) bus, is for connecting various peripheral devices to the computer
 system. These peripheral devices typically include input/output (I/O)
 devices such as a keyboard, floppy drives, and printers.
 Additionally, under the PCI local bus standard for 33 MHz operation, only
 four peripheral component connector slots may be attached to the PCI bus
 due to loading constraints on the bus. In order to overcome this technical
 constraint, designers may add a second or more PCI local buses that give
 the end user of a computer system the advantage of adding on four more
 slots per bus. However, a PCI host bridge is required for transferring
 information from the PCI bus to the system bus. Therefore, with the
 addition of more than one PCI local buses, designers have had to add on
 multiple PCI host bridges and/or PCI-to-PCI bridges for supporting the
 multiple PCI buses and a method for handling PCI peer-to-peer access
 across the multiple PCI host bridges thereby increasing the cost and
 complexity of the system.
 Therefore, it is desirable in a PCI-based system requiring multiple PCI
 host bridges and/or PCI-to-PCI bridges supporting multiple PCI buses, that
 a single PCI host bridge support multiple PCI buses thus minimizing the
 number of required bridges. Furthermore, it is desirable to have a single
 PCI host bridge operating at 33 MHz that has the capability of supporting
 more than four peripheral component slots having PCI devices connected
 thereto. Additionally, it is desirable to support PCI peer-to-peer access
 across a PCI bus operating at 33 MHz within a data-processing system. The
 subject invention herein solves all these problems in a new and unique
 manner which has not been part of the art previously.
 SUMMARY OF THE INVENTION
 In view of the foregoing, it is therefore an object of the present
 invention to provide an improved method and system for data processing.
 It is another object of the present invention to provide an improved method
 and system for handling PCI peer-to-peer accesses within a data-processing
 system.
 It is yet another object of the present invention to provide an improved
 method and system for supporting PCI peer-to-peer access across more than
 four PCI peripheral component slots connecting PCI devices per each PCI
 bus operating at 33 MHz within a data-processing system.
 In accordance with the method and system of the present invention, a
 processor and a system memory are connected to a system bus. First and
 second PCI local buses are connected to the system bus through a PCI host
 bridge. The first and second PCI local buses have sets of in-line
 electronic switches, dividing the PCI local buses into PCI local bus
 segments supporting a plurality of PCI peripheral component slots for
 connecting PCI devices. The sets of in-line electronic switches are open
 and closed in accordance with bus control logic within the PCI host bridge
 allowing up to fourteen or more PCI peripheral component slots for
 connecting up to fourteen PCI devices to have access through a single PCI
 host bridge to the system bus. A PCI-to-PCI bridge function is provided to
 allow a PCI device to share data with another PCI device as peer-to-peer
 devices across the first and second PCI local buses.
 All objects, features, and advantages of the present invention will become
 apparent in the following detailed written description.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENT
 The present invention may be applicable in a variety of computers under a
 number of different operating systems. The computer may be, for example, a
 personal computer, a mini-computer, or a mainframe computer. For the
 purpose of illustration, a preferred embodiment of the present invention,
 as described below, is implemented on a mini-computer, such as the RS/6000
 (series manufactured by International Business Machines Corporation).
 Referring now to the drawings wherein like reference numerals refer to like
 and corresponding parts throughout, and in particular to FIG. 1, there is
 depicted a block diagram of a typical computer system 10 having a PCI
 local bus architecture, which may utilize a preferred embodiment of the
 present invention. As shown in FIG. 1, a processor 12, cache memory 14,
 memory controller 16, and a Dynamic Random Access Memory (DRAM) 18 are all
 connected to a system bus 20 of a computer system 10. Processor 12, cache
 memory 14, memory controller 16, and DRAM 18 are also coupled to a PCI
 local bus 22 of computer system 10 through a PCI host bridge 24. PCI host
 bridge 24 provides a low latency path through which processor 12 may
 directly access PCI devices mapped anywhere within bus memory and/or I/O
 address spaces. PCI host bridge 24 also provides a high bandwidth path for
 allowing a PCI device to directly access DRAM 18. By way of example, but
 not of limitation, the PCI host bridge 24 may include various functions
 such as data buffering/posting and arbitration.
 Referring once again to FIG. 1, also attaching to PCI local bus 22 may be
 other devices such as a local-area network (LAN) interface 26, a small
 computer system interface (SCSI) 28 and an expansion bus interface 30. LAN
 interface 26 is for connecting computer system 10 to a local-area network
 32 such as to an Ethernet or Token-Ring. SCSI interface 28 is utilized to
 control high-speed SCSI disk drives 34. Expansion bus interface 30 couples
 any other expansion buses 36 such as an ISA bus, EISA bus, and/or
 MicroChannel Architecture (MCA) bus to the PCI local bus 22. Typically,
 various peripheral devices for performing certain basic I/O functions 46
 are attached to one of expansion buses 36.
 In general, PCI local bus 22 due to loading effects on the bus supports up
 to four add-in board connectors without requiring any expansion
 capability, such as adding a second PCI local bus not shown. Audio adapter
 board 38, motions video adapter board 40, and graphics adapter board 42
 connected to a monitor 44 are examples of some devices that may be
 attached to PCI local bus 22 via add-in board connectors as shown in FIG.
 1.
 With reference now to FIG. 2, there is illustrated a prior art
 configuration having separate PCI local buses under separate PCI host
 bridges. As shown, processor(s) 48 and a system memory 50 are coupled for
 communication over a system bus 20. By way of example but, not of
 limitation, system bus 20 provides a 32-bit memory address space and a
 16-bit I/O address space. A PCI host bridge 52 enables communications
 between bus agents coupled to system bus 20 and bus agents coupled to a
 PCI local bus A 56. Further, a PCI-to-ISA bridge 60 enables communications
 between bus agents (ISA device 64) coupled to an ISA bus 62 (ISA bus 62 is
 an expansion bus) and system memory 50. PCI-to-ISA bridge 60 also enables
 communications between processor(s) 48 and bus agents (ISA device 64)
 coupled to the ISA bus 62.
 Referring once again to FIG. 2, PCI devices 66, 68 and 70 are bus agents
 coupled for communication over PCI local bus A 56. In addition, PCI host
 bridge 52 and PCI-to-ISA bridge 60 are coupled as bus agents for
 communication over PCI local bus 56. PCI host bridge 52 and PCI-to-ISA
 bridge 60 have the capability to be initiators and targets for access
 cycles over PCI local bus 56. Turning once again to FIG. 2, in addition to
 PCI host bridge 52, a second PCI host bridge 54 is also attached to system
 bus 20. Similar to PCI host bridge 52, PCI host bridge 54 enables
 communications between bus agents coupled to system bus 20 and bus agents
 coupled to a second PCI local bus B 58. Attaching to PCI local bus B 58
 are PCI devices, such as PCI device 72 and PCI device 74.
 Referring now to FIG. 3, there is illustrated a block diagram of a PCI host
 bridge 76 in accordance with the preferred embodiment of the present
 invention. As shown, PCI host bridge 76 may support a plurality of PCI
 local buses, namely, PCI local bus A 56 and PCI local bus B 58. As shown
 in FIG. 3, two sets of in-line electronic switches are provided for each
 PCI bus thereby providing bus segments for allowing more than four PCI
 devices to be utilized on a given bus. These sets of in-line electronic
 switches additionally provide the total switching mechanism for all of the
 appropriate PCI signals associated with PCI buses for isolation on the
 buses as will be more fully described below.
 Referring once again to FIG. 3, two sets of in-line electronic switches
 SW-B1 86 and SW-B2 88 are inserted along PCI local bus B 58 creating PCI
 local bus segments B1 90 and B2 92, respectively. In accordance with the
 PCI specification, the bus loading design requirements for the PCI local
 bus B 58 are normally ten loads for a maximum frequency of up to 33 MHz at
 33 MHz of operation. Attaching a PCI slot to the PCI bus B 58 presents
 itself as two loads. As shown in FIG. 3, local bus segments B1 90 and B2
 92, respectively, each have attached four peripheral component slots 112
 and 114 for a total of eight loads on each bus segment. The host bridge 76
 adds one load and open switches on the other bus segment, PCI local bus A
 56, as will be more fully described below, add one more additional load,
 for a total of ten loads on each local bus segment B1 90 and B2 92,
 respectively.
 As shown in FIG. 3, the PCI local bus segments B1 90 and B2 92 each support
 four PCI peripheral component slots 112 and 114 (add-in board connectors)
 for receiving PCI devices, not shown. It should be understood that in
 order to meet the ten load requirement that at any one time only one set
 of switches may be closed on PCI local bus B 58 producing a total of ten
 loads. Therefore, the opening and closing of switches SW-B1 86 and SW-B2
 88 effectively isolate the PCI local bus B 58 from the local effects of
 the segments and the four added peripheral component slots behind the open
 switches allows eight slots to be utilized on PCI local bus B 58, thereby
 eliminating the need for the second PCI host bridge 54 shown in FIG. 2.
 Turning once again to FIG. 3, two sets of in-line electronic switches SW-A1
 78 and SW-A2 80 are inserted along PCI local bus A 56 creating PCI local
 bus segments A1 82 and A2 84, respectively. As noted above, the bus
 loading design requirements for the PCI local bus A 56 are normally ten
 loads for a maximum frequency of up to 33 MHz at 33 MHz of operation. Once
 again, attaching a PCI slot to the PCI bus A 56 presents itself as two
 loads. As shown in FIG. 3, local bus segments A1 82 and A2 84
 respectively, each have attached three peripheral component slots 96 and
 98 for a total of six loads on each bus. The host bridge 76 adds one load
 and open switches SW-B1 86 and SW-B2 88 on PCI local bus B 58 add one more
 additional load, for a total of eight loads on each PCI local bus segments
 A1 82 and A2 84, respectively. As discussed above, open switches SW-A1 78
 and SW-A2 80 adds an additional load on PCI local bus B 58. The three
 peripheral component slots 96 and 98 on each side of PCI local bus
 segments A1 82 and A2 84 when either switch SW-A1 78 and SW-A2 80 is
 closed presents six loads and is restricted to one less slot on each bus
 segment to allow for the added trace length of wire that may be required
 pass the slots in PCI local bus B 58 (which adds an approximately
 equivalent additional load to that bus segment).
 As shown in FIG. 3, the PCI local bus segments A1 82 and A2 84 each support
 three PCI peripheral component slots 96 and 98 (add-in board connectors)
 for receiving PCI devices, not shown, while accounting for the additional
 load presented by the extra wiring required to bypass the slots in PCI
 local bus B 58. It should be understood that in order to meet the ten load
 requirement that at any one time only one set of switches may be closed on
 PCI local bus A 56. Therefore, the opening and closing of switches SW-A1
 78 and SW-A2 80 effectively isolate the PCI local bus A 56 from the local
 effects of the segments and the three added peripheral component slots
 behind the open switches allows six slots to be utilized on PCI local bus
 A 56. Although not shown, it should be understood that PCI local bus A 56
 without PCI local bus B 58 could also support eight device slots.
 Additionally, a single pull double throw switch may also replace the two
 sets of in-line electronic switches. With this configuration, fourteen
 peripheral component slots are supported by each PCI host bridge.
 Referring once again to FIG. 3, The PCI host bridge 76 includes bus control
 logic 94 having an address decode 100, range registers 101 and an arbiter
 control 102 for controlling the sequence of turning "on" an "off" the
 switches SW-A1 78, SW-A2 80, SW-B1 86 and SW-B2 88, respectively, during
 bus operation. As mentioned before, when using either PCI local bus A 56
 or bus B 58, only one set of switches, SW-A1 78 and SW-A2 80 or SW-B1 86
 and SW-B2 88 are closed at a time, depending on where a master and where a
 target is during bus operation on either bus A 56 or bus B 58.
 By way of example, but not of limitation, the bus control logic 94 for bus
 A 56 will be described. The arbiter 102 for bus A 56 determines where the
 winning master is on the bus 56. If the current controlling master is say
 on bus segment A1 82, then the switch SW-A1 78 is closed and switch SW-A2
 80 is open when that master gains control of bus segment A1. If the
 operation is DMA (Direct Memory Access) to system memory 50 through the
 system bus 20, then the target is the host bridge 76. If the next winning
 arbiter is on segment A2 84, the grant line (GNT#) is removed from the
 master on segment A1 82, and when its latency timer expires, it gets off
 the bus 56 resulting in a idle cycle on the bus 56. When the bus 56 goes
 idle, switch SW-A1 78 is open, and SW-A2 80 is closed, and the GNT# is
 activated to the winning master waiting on segment A2 84. When the winning
 master in segment A2 84 sees its GNT# line active on the bus 56 it begins
 its Direct Memory Access (DMA) to system memory 50. It should be noted
 that the request line (REQ#) and GNT# lines (not shown) are not bused, and
 therefore not switched by the in-line switches SW-A1 78 and SW-A2 80.
 Although not described, it should be recognized that the equivalent bus
 control logic 94 discussed above is also provided for the in-line
 electronic switches SW-B1 86 and SW-B2 88 inserted along PCI local bus B
 58.
 Continuing from above and referring once again to FIG. 3, if the winning
 arbiter 102 is the PCI host bridge 76 for PCI local bus A 56, the address
 decode 100 and address range registers 101 in the bus controller 94 (for
 bus A) located in the PCI host bridge 76 is used to find the target the
 PCI host bridge 76 wants to access. This address decode 100 and address
 range registers 101 functions are handled in parallel with the arbitration
 102 described above. Once a target is located, then the PCI host bridge 76
 will know which set of in-line switches SW-A1 78 and SW-A2 80 need to be
 closed to connect the PCI host bridge 76 to the correct target. If the
 next target is on the same bus segment as the current controlling master,
 the switch states will not change until bus control is granted to the next
 controlling master. The address decode 100 is done to locate the target
 when the PCI host bridge 76 arbitrates for the PCI local bus A 56, in case
 the bridge wins the arbitration. When the current controlling master is on
 segment A1 82, the winning arbiter 102 is the PCI host bridge 76, and the
 target is on segment A2 84, the GNT# is removed from the master on segment
 A1 82, and when its latency timer expires, it gets off the PCI local bus
 56 resulting in an idle cycle on the PCI local bus 56. When the PCI local
 bus 56 goes idle, switch SW-A1 78 is open and switch SW-A2 80 is closed
 and the PCI host bridge 76 now begins its access to the target on PCI
 local bus segment A2 84. Although not described, it should be recognized
 that the equivalent bus control logic 94 discussed above is also provided
 for the set of in-line electronic switches SW-B1 86 and SW-B2 88 inserted
 along PCI local bus B 58.
 Turning once again to FIG. 3, for local bus segments A1 82 and A2 84 there
 are attached pull-up resistors 104 and 110 located on the slot 96 and 98
 sides of the switches 78 and 80. Similarly, for local bus segments B1 90
 and B2 92 there are attached pull-up resistors 106 and 108 located on the
 slot 112 and 114 sides of the switches 86 and 88. Additionally, more than
 two bus segments per PCI bus may be separated by set of in-line switches
 as long as the total bus loading requirements and timing budgets are met
 for a given frequency of operation. Also, more than two PCI buses can be
 provided by a single PCI host bridge as long as there are enough pins on
 the chip and the buses can be physically wired.
 Referring now to FIG. 4, there is illustrated a block diagram for providing
 peer-to-peer support for PCI devices on PCI local bus A1 56 by adding an
 internal enhanced PCI-to-PCI (P2P) bridge 116 capability including PCI
 Interfaces B and A 120 and 124, respectively and input/output buffers 122
 and 126 to the PCI host bridge 76 in accordance with the preferred
 embodiment of the present invention. Referring once again to FIG. 4, the
 P2P bridge capability 116 operates with PCI local bus segment A1 82, A2
 84, B1 90 and B2 92 to provide a P2P functionality to handle peer-to-peer
 between these bus segments. P2P bridge operations are known in the art and
 therefore not discussed in detail herein, except for the added P2P bridge
 capability described in the preferred embodiment.
 The following describes a new capability of a P2P bridge allowing the P2P
 bridge in conjunction with the PCI host bridge 76, address decode 100 and
 range registers 101 to accept a transaction as a target and then later to
 place the same transaction as a master out on the same PCI interface based
 on the location of the target. By way of example, but not of limitation,
 when a current controlling master is on PCI local bus segment A1 82,
 switches SW-A1 78 is closed and SW-A2 80 is opened thereby connecting
 local bus segment A1 82 to PCI host bridge 76, the transaction from the
 master is placed into input/output buffer 126 through PCI-Interface 124.
 The PCI host bridge 76 and the P2P bridge 116 (acting as potential
 targets) decode 100 the address of the transaction. When the address is a
 location in system memory, the PCI host bridge 76 responds as the target
 and forwards the information in the input/output buffer 126 via a separate
 transaction to the system via a system interface 118. When the address is
 for a device on PCI local bus segment A2 84, the P2P bridge 116 responds
 as the target and terminates the transaction as a delayed transaction or
 posts the transaction when the transaction is a memory write. The P2P
 bridge 116 then arbitrates for the local bus A 56. When the PCI interface
 124 is granted access to the PCI local bus A 56, the switch control logic
 closes switch SW-A2 80 and opens switch SW-A1 78 connecting PCI local bus
 segment A2 84 to PCI local bus A 56 so that the PCI Interface 124 of the
 P2P bridge 116 can complete the transaction in input/output buffers 126 to
 the PCI device connected at PCI slot 98. It should be noted that the same
 sequence of events occurs on bus segments A1 82 and A2 84 when the
 controlling master is on segment A2 84 and the target is on segment A1 82.
 Similarly, the same sequence of events occurs for local bus B 58, with
 devices on segment B1 90 and segment B2 92 using the PCI host bridge 76
 and the enhanced P2P bridge 116 in association with PCI-Interface B 120
 and input/output buffer 122.
 When the current controlling master is on PCI local bus segment A2 84,
 switches SW-A1 80 is closed and SW-A2 78 is opened thereby connecting
 local bus segment A2 84 to PCI host bridge 76, the transaction from the
 master is placed into input/output buffer 126 through PCI-Interface 124.
 Once again, the PCI host bridge 76 and the P2P bridge 116 (acting as
 potential targets) decode 100 the address of the transaction. When the
 address is a location in system memory, the PCI host bridge 76 responds as
 the target and forwards the information in the input/output buffer 126 via
 another transaction to the system via the system interface 118. When the
 address is for a device on PCI local bus segment B2 92, the P2P bridge 116
 responds as the target and terminates the transaction as a delayed
 transaction or posts the transaction when the transaction is a memory
 write. The P2P bridge 116 then arbitrates for the local bus B 58. When the
 PCI interface 120 is granted access to the PCI local bus B 92, the switch
 control logic closes switch SW-B2 88 and opens switch SW-B1 86 connecting
 PCI local bus segment B2 92 to PCI local bus B 58 so that the PCI
 Interface 120 of the P2P bridge 116 can complete the transaction in
 input/output buffers 126 to the PCI device connected at PCI slot 114.
 Similarly, the same sequence of events occurs when a controlling master is
 on local bus B 58 and the target is in one of the slots on local bus A 56.
 By way of example, but not of limitation, when both the controlling master
 and the target are on the same PCI bus segment A1 82 performing
 peer-to-peer operations, SW-A1 78 can be opened and PCI bus segments A2 84
 and A1 82 can be operated as a separate logical buses with the arbiter 102
 granting the bus segment A1 82 to either a master or segments A1 82 or to
 the PCI host bridge 76 via PCI-interface 124. Similarly, PCI bus segments
 B1 90 and B2 92 can be operated as separate logical buses when
 peer-to-peer operations are occurring on the same PCI bus segment, with
 the in-line switches providing the isolation. This functional capability
 adds greater bandwidth to the PCI I/O subsystem.
 While the invention has been particularly shown and described with
 reference to a preferred embodiment, it will be understood by those
 skilled in the art that various changes in form and detail may be made
 therein without departing from the spirit and scope of the invention.