Scan driver including stage circuit for reducing leakage current

A stage circuit includes a first driver, a second driver, a first output unit, a second output unit and a controller. The first driver controls voltages of first and second nodes, according to a first power source, a third power source, a start signal or a carry signal of a previous stage input to a first input terminal, and a clock signal supplied to a second input terminal. The second driver controls voltages of third and fourth nodes, according to voltages of the first power source, the third power source, the first input terminal and the first and second nodes. The first output unit outputs a carry signal to a first output terminal, according to voltages of the first power source, the second input terminal and the third and fourth nodes. The second output unit outputs a scan signal to a second output terminal, according to voltages of the second power source, the second input terminal and the third and fourth nodes. The controller is electrically coupled to the first output terminal and the second driver.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to and the benefit of Korean Patent Application No. 10-2013-0095210, filed on Aug. 12, 2013, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference in their entirety.

BACKGROUND

Embodiments of the present invention relate to a stage circuit and a scan driver using the same.

2. Description of the Related Art

With the recent developments in information technologies, the importance of a display device that is a medium for presenting information has been increasing. Accordingly, flat panel display devices (FPD devices) such as liquid crystal display (LCD) devices, organic light emitting diode (OLED) display devices and plasma display panel (PDP) devices are being increasingly used.

Among these FPD devices, the OLED display device displays images using organic light emitting diodes (OLED) that emit light through recombination of electrons and holes. The organic light emitting display device has a fast response speed and is driven with low power consumption.

SUMMARY

Embodiments provide a stage circuit and a scan driver using the same, which can improve the reliability of driving an OLED display device.

According to an embodiment of the present invention, there is provided a stage circuit, including: a first driver configured to control voltages of first and second nodes, according to a first power source, a third power source, a start signal or a carry signal of a previous stage input to a first input terminal, and a clock signal supplied to a second input terminal; a second driver configured to control voltages of third and fourth nodes, according to voltages of the first power source, the third power source, the first input terminal and the first and second nodes; a first output unit configured to output a carry signal to a first output terminal, according to voltages of the first power source, the second input terminal and the third and fourth nodes; a second output unit configured to output a scan signal to a second output terminal, according to voltages of the second power source, the second input terminal and the third and fourth nodes; and a controller electrically coupled to the first output terminal and the second driver.

The first driver, the second driver, the first output unit, the second output unit and the controller may be configured with N-type transistors.

The first and second power sources may have a gate-off voltage, and the third power source may have a gate-on voltage.

The second power source may have a voltage higher than that of the first power source.

The second output unit may include a first transistor coupled between the second input terminal and the second output terminal, the first transistor having a gate electrode coupled to the third node; and a second transistor coupled between the second output terminal and the second power source, the second transistor having a gate electrode coupled to the fourth node.

The first output unit may include a third transistor coupled between the second input terminal and the first output terminal, the third transistor having a gate electrode coupled to the third node; a fourth transistor coupled between the first output terminal and the first power source, the fourth transistor having a gate electrode coupled to the fourth node; and a capacitor coupled between the first output terminal and the third node.

The first driver may include a fifth transistor coupled between the third power source and the first node, the fifth transistor having a gate electrode coupled to the third power source; a sixth transistor coupled between the first node and the first power source, the sixth transistor having a gate electrode coupled to the first input terminal; a seventh transistor coupled between the third power source and the second node, the seventh transistor having a gate electrode coupled to the first input terminal; an eighth transistor coupled between the second node and a ninth transistor, the eighth transistor having a gate electrode coupled to the first node; and the ninth transistor coupled between the eighth transistor and the first power source, the ninth transistor having a gate electrode coupled to the second input terminal.

The fifth transistor may have a channel length longer than that of the sixth transistor.

The eighth transistor may include a plurality of transistors coupled in series.

The second driver may include a tenth transistor coupled between the third power source and an eleventh transistor, the tenth transistor having a gate electrode coupled to the second node; the eleventh transistor coupled between the tenth transistor and the third node, the eleventh transistor having a gate electrode coupled to the first node; a twelfth transistor coupled between the third node and a thirteenth transistor, the twelfth transistor having a gate electrode coupled to the first input terminal; the thirteenth transistor coupled between the twelfth transistor and the first power source, the thirteenth transistor having a gate electrode coupled to the first input terminal; a fourteenth transistor coupled between the third node and a fifteenth transistor, the fourteenth transistor having a gate electrode coupled to the fourth node; the fifteenth transistor coupled between the fourteenth transistor and the first power source, the fifteenth transistor having a gate electrode coupled to the fourth node; a sixteenth transistor coupled between the third power source and the fourth node, the sixteenth transistor having a gate electrode coupled to the third power source; a seventeenth transistor coupled between the fourth node and the first power source, the seventeenth transistor having a gate electrode coupled to the second node; and an eighteenth transistor coupled between the fourth node and the first power source, the eighteenth transistor having a gate electrode coupled to the first output terminal.

The sixteenth transistor may have a channel length longer than that of the seventeenth or eighteenth transistor.

The controller may include a nineteenth transistor coupled between the first output terminal and a common node of the twelfth and thirteenth transistors, and the nineteenth transistor having a gate electrode coupled to the first output terminal; and a twentieth transistor coupled between the first output terminal and a common node of the fourteenth and fifteenth transistors, and the twentieth transistor having a gate electrode coupled to the first output terminal.

The controller may allow at least one transistor included in the second driver to be completely turned off during a period in which the carry signal is supplied.

According to an embodiment of the present invention, there is provided a scan driver, including: stage circuits respectively coupled to scan lines to supply scan signals to scan lines, the stage circuits being driven by one clock signal, wherein each of the stage circuits includes a first input terminal configured to receive a start signal or a carry signal of a previous stage, a second input terminal configured to receive the clock signal, a first output terminal configured to output a carry signal, and a second output terminal configured to output a scan signal.

The clock signal may repeat high and low levels, and the supply period of the high level may be set longer than that of the low level.

The start signal may be input to the first input terminal of a first stage circuit, and the carry signal of the previous stage may be input to the first input terminals of the other stage circuits.

The start signal may overlap with the high level of the clock signal.

The stage circuits may include N-type transistors.

Each stage circuit may include a first driver coupled to a first power source, a third power source, the first input terminal and the second input terminal to control voltages of first and second nodes; a second driver configured to control voltages of third and fourth nodes, according to voltage of the first power source, the third power source, the first input terminal and the first and second nodes; a first output unit configured to output the carry signal to the first output terminal, according to voltages of the first power source, the second input terminal and the third and fourth nodes; a second output unit configured to output a scan signal to the second output terminal, according to voltages of the second power source, the second input terminal and the third and fourth nodes; and a controller electrically coupled to the first output terminal and the second driver.

The first and second power sources may have a gate-off voltage, and the third power source may have a gate-on voltage.

The second power source may have a voltage higher than that of the first power source.

The second output unit may include a first transistor coupled between the second input terminal and the second output terminal, the first transistor having a gate electrode coupled to the third node; and a second transistor coupled between the second output terminal and the second power source, the second transistor having a gate electrode coupled to the fourth node.

The first output unit may include a third transistor coupled between the second input terminal and the first output terminal, the third transistor having a gate electrode coupled to the third node; a fourth transistor coupled between the first output terminal and the first power source, the fourth transistor having a gate electrode coupled to the fourth node; and a capacitor coupled between the first output terminal and the third node.

The first driver may include a fifth transistor coupled between the third power source and the first node, the fifth transistor having a gate electrode coupled to the third power source; a sixth transistor coupled between the first node and the first power source, the sixth transistor having a gate electrode coupled to the first input terminal; a seventh transistor coupled between the third power source and the second node, the seventh transistor having a gate electrode coupled to the first input terminal; an eighth transistor coupled between the second node and a ninth transistor, the eighth transistor having a gate electrode coupled to the first node; and the ninth transistor coupled between the eighth transistor and the first power source, the ninth transistor having a gate electrode coupled to the second input terminal.

The fifth transistor may have a channel length longer than that of the sixth transistor.

The second driver may include a tenth transistor coupled between the third power source and an eleventh transistor, the tenth transistor having a gate electrode coupled to the second node; the eleventh transistor coupled between the tenth transistor and the third node, the eleventh transistor having a gate electrode coupled to the first node; a twelfth transistor coupled between the third node and a thirteenth transistor, the twelfth transistor having a gate electrode coupled to the first input terminal; the thirteenth transistor coupled between the twelfth transistor and the first power source, the thirteenth transistor having a gate electrode coupled to the first input terminal; a fourteenth transistor coupled between the third node and a fifteenth transistor, the fourteenth transistor having a gate electrode coupled to the fourth node; the fifteenth transistor coupled between the fourteenth transistor and the first power source, the fifteenth transistor having a gate electrode coupled to the fourth node; a sixteenth transistor coupled between the third power source and the fourth node, the sixteenth transistor having a gate electrode coupled to the third power source; a seventeenth transistor coupled between the fourth node and the first power source, the seventeenth transistor having a gate electrode coupled to the second node; and an eighteenth transistor coupled between the fourth node and the first power source, the eighteenth transistor having a gate electrode coupled to the first output terminal.

The sixteenth transistor may have a channel length longer than that of the seventeenth or eighteenth transistor.

The controller may include a nineteenth transistor coupled between the first output terminal and a common node of the twelfth and thirteenth transistors, and the nineteenth transistor having a gate electrode coupled to the first output terminal; and a twentieth transistor coupled between the first output terminal and a common node of the fourteenth and fifteenth transistors, and the twentieth transistor having a gate electrode coupled to the first output terminal.

DETAILED DESCRIPTION

Expressions such as “at least one of,” when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list. Further, the use of “may” when describing embodiments of the present invention refers to “one or more embodiments of the present invention.”

FIG. 1is a diagram illustrating an organic light emitting display device according to an embodiment of the present invention.

Referring toFIG. 1, the organic light emitting display device according to this embodiment includes a display unit40configured to include pixels30positioned at crossing regions of scan lines S1to Sn and data lines D1to Dm, a scan driver10configured to drive the scan lines S1to Sn, a data driver20configured to drive the data lines D1to Dm, and a timing controller50configured to control the scan driver10and the data driver20.

The scan driver10supplies scan signals to the scan lines S1to Sn. For example, the scan driver10may progressively supply the scan signals to the scan lines S1to Sn. To this end, the scan driver10includes stage circuits (not shown) respectively coupled to the scan lines S1to Sn. When the scan signals are progressively supplied to the scan lines S1to Sn, pixels30are selected for each horizontal line.

The data driver20supplies data signals to the data lines D1to Dm in synchronization with the scan signals.

The timing controller50controls the scan driver10and the data driver20. The timing controller50supplies, to the data driver20, data (not shown) from the outside of the organic light emitting display.

Each pixel30stores a voltage corresponding to the data signal when the scan signal is supplied. The pixel30generates light (e.g., light having a predetermined luminance) while controlling the amount of current supplied to an organic light emitting diode (not shown), corresponding to the data signal.

FIG. 2is a diagram illustrating an embodiment of the scan driver shown inFIG. 1. For convenience of illustration, four stages are shown inFIG. 2.

Referring toFIG. 2, the scan driver10includes stage circuits ST1to ST4respectively coupled to scan lines S1to S4. The stage circuits ST1to ST4each have substantially the same circuit architecture as each other. The stage circuits ST1to ST4progressively supply scan signals to the scan lines S1to S4. Hence, the stage circuits ST1to STn would progressively supply scan signals to the scan lines S1to Sn.

Each of the stage circuits ST1to ST4is driven by one clock signal CLK. To this end, each of the stage circuits ST1to ST4includes a first input terminal101, a second input terminal102, a first output terminal103and a second output terminal104.

The first input terminal101included in each of the stage circuits ST1to ST4receives a carry signal carry of a previous stage or a start signal FLM. For example, the start signal FLM is supplied to the first input terminal101of the first stage ST1, and the carry signal carry of the previous stage is supplied to the input terminal101of each of the other stage circuits ST2to ST4.

The clock signal CLK is supplied to the second input terminal102included in each of the stage circuits ST1to ST4. The clock signal CLK, as shown inFIG. 4, repeats high and low levels, and the supply period of the high level is set longer than that of the low level. For convenience of illustration, the supply of the clock signal CLK refers to when the voltage level (e.g., the high level) is supplied, at which transistors included in the stages ST1to ST4are turned on.

A carry signal to be supplied to a next stage is output to the first output terminal103included in each of the stage circuits ST1to ST4, and a scan signal to be supplied to a scan line S is output to the second output terminal104included in each of the stage circuits ST1to ST4.

FIG. 3is a circuit diagram illustrating an embodiment of the stage circuit shown inFIG. 2. For convenience of illustration, the first stage circuit ST1will be shown inFIG. 3.

Referring toFIG. 3, the stage circuit ST1according to this embodiment includes a first driver110, a second driver120, a first output unit130, a second output unit140and a controller150. In one embodiment, each of the first driver110, the second driver120, the first output unit130, the second output unit140and the controller150includes N-type transistors (e.g., NMOS transistors). In other embodiments, other suitable types of transistors (e.g., P-type transistors) may be used.

First and second power sources VSS1and VSS2supplied to the stage circuit ST1are set to a gate-off voltage, and a third power source VDD is set to a gate-on voltage. In this case, the third power source VDD is set to a voltage higher than that of the first or second power source VSS1or VSS2. In an example embodiment of the present invention, the second power source VSS2is set to a voltage higher than that of the first power source VSS1.

The second output140outputs a scan signal to the second output terminal104, corresponding to voltages of third and fourth nodes N3and N4. To this end, the second output unit140includes a first transistor M1and a second transistor M2.

The first transistor M1is coupled between the second input terminal102and the second output terminal104. A gate electrode of the first transistor M1is coupled to the third node N3. The first transistor M1controls the coupling between the second input terminal102and the second output terminal104, corresponding to (e.g., according to, based on, determined by, or controlled by) the voltage applied to the third node N3.

The second transistor M2is coupled between the second output terminal104and the second power source VSS2. A gate electrode of the second transistor M2is coupled to the fourth node N4. The second transistor M2controls the coupling between the second output terminal104and the second power source VSS2, corresponding to (e.g., according to, based on, determined by, or controlled by) the voltage applied to the fourth node N4. Here, the second power source VSS2is set to a voltage higher than that of the first power source VSS1, and hence the second transistor M2can be stably set to a turn-off state even though the first power source VSS1is input to the fourth node N4.

The first output unit130outputs a carry signal carry to the first output terminal103, corresponding to (e.g., according to, based on, determined by, or controlled by) the voltages of the third and fourth nodes N3and N4. To this end, the first output unit130includes a third transistor M3, a fourth transistor M4and a capacitor C1.

The third transistor M3is coupled between the second input terminal102and the first output terminal103. A gate electrode of the third transistor M3is coupled to the third node N3. The third transistor M3controls the coupling between the second input terminal102and the first output terminal103, corresponding to (e.g., according to, based on, determined by, or controlled by) the voltage applied to the third node N3.

The fourth transistor M4is coupled between the first output terminal103and the first power source VSS1. A gate electrode of the fourth transistor M4is coupled to the fourth node N4. The fourth transistor M4controls the coupling between the first output terminal103and the first power source VSS1, corresponding to (e.g., according to, based on, determined by, or controlled by) the voltage applied to the fourth node N4.

The capacitor C1is coupled between the third node N3and the first output terminal103. The capacitor C1controls the voltage of the third node N3, corresponding to (e.g., according to, based on, determined by, or controlled by) the voltage of the first output terminal103.

The first driver110controls voltages of first and second nodes N1and N2. To this end, the first driver110includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8and a ninth transistor M9.

The fifth transistor M5is coupled between the third power source VDD and the first node N1. A gate electrode of the fifth transistor M5is coupled to the third power source VDD. That is, the fifth transistor M5is diode-coupled to supply the voltage of the third power source VDD to the first node N1. The fifth transistor M5is always set to a turn-on state.

The sixth transistor M6is coupled between the first node N1and the first power source VSS1. A gate electrode of the sixth transistor M6is coupled to the first input terminal101. The sixth transistor M6is turned on when the start signal FLM is supplied to the first input terminal101, to allow the first node N1and the first power source VSS1to be electrically coupled to each other.

Meanwhile, the first node N1is electrically coupled to the first power source VSS1and the third power source VDD during the period in which the sixth transistor M6is turned on, and therefore, the voltage of the first node N1may be unstable. Accordingly, in embodiments of the present invention, the fifth transistor M5is formed to have a channel length longer than that of the sixth transistor M6. For example, the fifth transistor M5may be formed to have a channel length more than five times longer than that of the sixth transistor M6. Then, the voltage of the first node N1is dropped to the voltage of the first power source VSS1during the period in which the sixth transistor M6is turned on.

The seventh transistor M7is coupled between the third power source VDD and the second node N2. A gate electrode of the seventh transistor M7is coupled to the first input terminal101. The seventh transistor M7is turned on when the start signal FLM is supplied to the first input terminal101, to allow the third power source VDD and the second node N2to be electrically coupled to each other.

The eighth transistor M8is coupled between the second node N2and the ninth transistor M9. A gate electrode of the eighth transistor M8is coupled to the first node N1. The eighth transistor M8controls the coupling between the second node N2and the ninth transistor M9, corresponding to (e.g., according to, based on, determined by, or controlled by) the voltage of the first node N1. Meanwhile, the eighth transistor M8is configured with a plurality of transistors M8-1and M8-2coupled in series to each other in order to reduce or minimize leakage current.

The ninth transistor M9is coupled between the eighth transistor M8and the first power source VSS1. A gate electrode of the ninth transistor M9is coupled to the second input terminal102. The ninth transistor M9is turned on when the clock signal CLK is supplied to the second input terminal102, to control the coupling between the eighth transistor M8and the first power source VSS1.

The second driver120controls the voltages of the third and fourth nodes N3and N4, corresponding to (e.g., according to, based on, determined by, or controlled by) the voltages of the first and second nodes N1and N2. To this end, the second driver120includes a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14, a fifteenth transistor M15, a sixteenth transistor M16, a seventeenth transistor M17and an eighteenth transistor M18.

The tenth transistor M10is coupled between the eleventh transistor M11and the third power source VDD. A gate electrode of the tenth transistor M10is coupled to the second node N2. The tenth transistor M10controls the coupling between the third power source VDD and the eleventh transistor M11, corresponding to (e.g., according to, based on, determined by, or controlled by) the voltage of the second node N2.

The eleventh transistor M11is coupled between the tenth transistor M10and the third node N3. A gate electrode of the eleventh transistor M11is coupled to the first node N1. The eleventh transistor M11controls the coupling between the tenth transistor M10and the third node N3, corresponding to (e.g., according to, based on, determined by, or controlled by) the voltage of the first node N1.

The twelfth transistor M12is coupled between the third node N3and the thirteenth transistor M13. A gate electrode of the twelfth transistor M12is coupled to the first input terminal101. The twelfth transistor M12is turned on when the start signal FLM is supplied to the first input terminal101, to allow the third node N3and the thirteenth transistor M13to be electrically coupled to each other.

The thirteenth transistor M13is coupled between the twelfth transistor M12and the first power source VSS1. A gate electrode of the thirteenth transistor M13is coupled to the first input terminal101. The thirteenth transistor M13is turned on when the start signal FLM is supplied to the first input terminal101, to allow the twelfth transistor M12and the first power source VSS1to be electrically coupled to each other.

The fourteenth transistor M14is coupled between the third node N3and the fifteenth transistor M15. A gate electrode of the fourteenth transistor M14is coupled to the fourth node N4. The fourteenth transistor M14controls the coupling between the third node N3and the fifteenth transistor M15, corresponding to (e.g., according to, based on, determined by, or controlled by) the voltage of the fourth node N4.

The fifteenth transistor M15is coupled between the fourteenth transistor M14and the first power source VSS1. A gate electrode of the fifteenth transistor M15is coupled to the fourth node N4. The fifteenth transistor M15controls the coupling between the fourteenth transistor M14and the first power source VSS1, corresponding to (e.g., according to, based on, determined by, or controlled by) the voltage of the fourth node N4.

The sixteenth transistor M16is coupled between the third power source VDD and the fourth node N4. A gate electrode of the sixteenth transistor M16is coupled to the third power source VDD. That is, the sixteenth transistor M16is diode-coupled to supply the voltage of the third power source VDD to the fourth node N4. The sixteenth transistor M16is always set to the turn-on state.

The seventeenth transistor M17is coupled between the fourth node N4and the first power source VSS1. A gate electrode of the seventeenth transistor M17is coupled to the second node N2. The seventeenth transistor M17controls the coupling between the fourth node N4and the first power source VSS1, corresponding to (e.g., according to, based on, determined by, or controlled by) the voltage of the second node N2.

The eighteenth transistor M18is coupled between the fourth node N4and the first power source VSS1. A gate electrode of the eighteenth transistor M18is coupled to the first output terminal103. The eighteenth transistor M18is turned on when the carry signal carry is supplied to the first output terminal103, to allow the fourth node N4and the first power source VSS1to be electrically coupled to each other.

Meanwhile, the fourth node N4is electrically coupled to the first and third power sources VSS1and VDD during the period in which the seventeenth transistor M17and/or the eighteenth transistor M18are/is turned on, and therefore, the voltage of the fourth node N4may be unstable. Accordingly, in embodiments of the present invention, the sixteenth transistor M16is formed to have a channel length longer than that of the seventeenth or eighteenth transistor M17or M18. For example, the sixteenth transistor M16may be formed to have a channel length more than five times longer than that of the seventeenth or eighteenth transistor M17or M18. Then, the voltage of the fourth node N4is dropped to the voltage of the first power source VSS1during the period in which the seventeenth transistor M17and/or the eighteenth transistor M18are/is turned on.

The controller150reduces or minimizes leakage current of the third node N3during the period in which the carry signal carry is output, thereby ensuring the reliability of driving. To this end, the controller150includes a nineteenth transistor M19and the twentieth transistor M20.

The nineteenth transistor M19is coupled between the first output terminal103and a common node of the twelfth and thirteenth transistors M12and M13. A gate electrode of the nineteenth transistor M19is coupled to the first output terminal103. That is, the nineteenth transistor M19is diode-coupled, and is turned on during the period in which the carry signal carry is output. When the nineteenth transistor M19is turned on, the common electrode of the twelfth and thirteenth transistors M12and M13is set to the voltage of the carry signal carry, and accordingly, the twelfth transistor M12is completely set to the turn-off state.

The twentieth transistor M20is coupled between the first output terminal103and a common node of the fourteenth and fifteenth transistors M14and M15. A gate electrode of the twentieth transistor M20is coupled to the first output terminal103. That is, the twentieth transistor M20is diode-coupled, and is turned on during the period in which the carry signal carry is output. When the twentieth transistor M20is turned on, the common node of the fourteenth and fifteenth transistors M14and M15is set to the voltage of the carry signal carry, and accordingly, the fourteenth transistor M14is completely set to the turn-off state.

FIG. 4is a waveform diagram illustrating an embodiment of a driving method of the stage circuit shown inFIG. 3.

Referring toFIG. 4, the clock signal repeats high and low levels, and the supply period of the high level is set longer than that of the low level. The start signal FLM supplied to the first stage ST1is supplied in synchronization with the clock signal CLK (i.e., the start signal FLM is overlapped with the high level of the clock signal).

The operating process of the stage circuit will be described in detail. First, the clock signal CLK and the start signal FLM are supplied during a first period T1.

When the start signal FLM is supplied, the sixth, seventh, twelfth and thirteenth transistor M13are turned on as shown inFIG. 5A. When the clock signal CLK is supplied, the ninth transistor M9is turned on.

When the sixth transistor M6is turned on, the voltage of the first power source VSS1is supplied to the first node N1. In this case, the first node N1is dropped to the voltage of the first power source VSS1, regardless of the turn-on of the fifth transistor M5. When the voltage of the first power source VSS1is supplied to the first node N1, the eight transistors M8-1and M8-2and the eleventh transistor M11are set to the turn-off state.

When the seventh transistor M7is turned on, the third power source VDD is supplied to the second node N2. When the third power source VDD is supplied to the second node N2, the tenth and seventeenth transistors M10and M17are turned on. When the tenth transistor M10is turned on, the third power source VDD is supplied to the eleventh transistor M11. In this case, the eleventh transistor M11is set to the turn-off state, and hence the third power source VDD is not supplied to the third node N3.

When the seventeenth transistor M17is turned on, the voltage of the first power source VSS1is supplied to the fourth node N4. In this case, the fourth node N4is dropped to the voltage of the first power source VSS1, regardless of the turn-on of the sixteenth transistor M16. When the fourth node N4is dropped to the voltage of the first power source VSS1, the fourteenth, fifteenth, fourth and second transistors M14, M15, M4and M2are set to the turn-off state.

When the ninth transistor M9is turned on, the first power source VSS1is supplied to the eighth transistor M8-2. In this case, the eighth transistor M8-2is set to the turn-off state, and hence the first power source VSS1is not supplied to the second node N2.

When the twelfth and thirteenth transistors M12and M13are turned on, the voltage of the first power source VSS1is supplied to the third node N3. When the voltage of the first power source VSS1is supplied to the third node N3, the third and first transistors M3and M1are set to the turn-off state.

The third and fourth nodes N3and N4are set to a low voltage during the first period T1, and accordingly, the first to fourth transistors M1to M4are set to the turn-off state. Thus, the first and second output terminals103and104maintain the low voltage, identical to that in the previous period.

The supply of the clock signal CLK and the start signal FLM is stopped (e.g., the level of the clock signal CLK and the start signal FLM is at a low level) during a second period T2. When the supply of the start signal FLM is stopped (e.g., the level of the start signal FLM is at a low level), the sixth, seventh, twelfth and thirteenth transistors M6, M7, M12and M13are turned off as shown inFIG. 5B. When the supply of the clock signal CLK is stopped (e.g., the level of the clock signal CLK is at a low level), the ninth transistor M9is turned off.

When the sixth transistor M6is turned off, the voltage of the first node N1is raised to the voltage of the third power source VDD by the fifth transistor M5. When the voltage of the first node N1is raised to the voltage of the third power source VDD, the eighth transistors M8-1and M8-2and the eleventh transistor M11are turned on. In this case, the ninth transistor M9is set to the turn-off state, and hence the second node N2maintains a high voltage in the previous period, regardless of the turn-on of the eighth transistors M8-1and M8-2. That is, the second node N2set to a floating state during the second period T2maintains the voltage from the previous period by a parasitic capacitor (not shown), etc.

When the eleventh transistor M11is turned on, the tenth transistor M10and the third node N3are electrically coupled to each other. In this case, the tenth transistor M10is set to the turn-on state, and hence the voltage of the third power source VDD is supplied to the third node N3.

When the voltage of the third power source VDD is supplied to the third node N3, the third and first transistors M3and M1are turned on. When the third transistor M3is turned on, the first output terminal103and the second input terminal102are electrically coupled to each other. In this case, the clock signal CLK (i.e., the low level) is not supplied to the second terminal102, and accordingly, the first output terminal103maintains the low voltage.

When the first transistor M1is turned on, the second output terminal104and the second input terminal102are electrically coupled to each other. In this case, the clock signal CLK (i.e., the low level) is not supplied to the second input terminal102, and accordingly, the second output terminal104maintains the low voltage.

Meanwhile, the seventeenth transistor M17is set to the turn-on state during the second period T2, and hence the fourth node N4maintains the voltage of the first power source VSS1. Thus, the fourteenth, fifteenth, fourth and second transistors M14, M15, M4and M2maintain the turn-off state during the second period T2.

The clock signal CLK is supplied to the second input terminal102during a third period T3. When the clock signal CLK is supplied to the second input terminal, the ninth transistor M9is turned on as shown inFIG. 5C. In this case, the eighth transistor M8is set to the turn-on state, corresponding to (e.g., according to, based on, determined by, or controlled by) the voltage of the first node N1. Hence, when the ninth transistor M9is turned on, the voltage of the first power source VSS1is supplied to the second node N2.

When the voltage of the first power source VSS1is supplied to the second node N2, the tenth and seventeenth transistors M10and M17are turned off. When the tenth transistor M10is turned off, the first transistor M11and the third power source VDD are not electrically coupled to each other. Thus, although the eleventh transistor M11is set to the turn-on state, the voltage of the third power source VDD is not supplied to the third node N3. That is, the third node N3is set to the floating state during the third period T3.

Meanwhile, the third node N3is set to the high voltage, and hence the first and third transistors M1and M3maintain the turn-on state during the third period T3. When the third transistor M3is turned on, the clock signal CLK supplied to the second input terminal102is supplied to the first output terminal103. In this case, the voltage of the third node N3is raised by the coupling of the capacitor C1, and accordingly, the third transistor M3stably maintains the turn-on state. The clock signal CLK supplied to the first output terminal103is output as the carry signal carry to the next stage.

Meanwhile, when the carry signal carry is output to the first output terminal103, the nineteenth and twentieth transistors M19and M20are turned on. When the nineteenth transistor M19is turned on, the high voltage (i.e., the carry signal) is supplied to a common node of the twelfth and thirteenth transistors M12and M13. In this case, the low voltage from the first input terminal101is supplied to the gate electrode of the twelfth transistor M12, and accordingly, the twelfth transistor M12is completely set to the turn-off state. When the twelfth transistor M12is completely set to the turn-off state, the leakage current from the third node N3is reduced or minimized, and accordingly, the third node N3can stably maintain the high voltage.

Similarly, when the twentieth transistor M20is turned on, the high voltage is supplied to a common node of the fourteenth and fifteenth transistors M14and M15. Then, the fourteenth transistor of which gate electrode receives the low voltage is completely set to the turn-off state, and accordingly, the leakage current from the third node N3can be reduced or minimized.

When the first transistor M1is turned on, the clock signal CLK is supplied to the second output terminal104. The clock signal CLK supplied to the second output terminal104is supplied as the scan signal to the scan line S1.

The supply of the clock signal CLK is stopped (e.g., the level of the clock signal CLK is at a low level) during a fourth period T4. When the supply of the clock signal CLK is stopped (e.g., the level of the clock signal CLK is at a low level), the ninth transistor M9is turned off as shown inFIG. 5D. When the ninth transistor M9is turned off, the eighth transistor M8and the first power source VSS1are electrically decoupled from each other. In this case, the first node N1maintains the high voltage, and the second node N2maintains the low voltage in the previous period T3.

Meanwhile, the supply of clock signal CLK is stopped (e.g., the level of the clock signal CLK is at a low level), the low voltage is supplied to the first output terminal103, and the voltage of the third node N3set to the floating state by the coupling of the capacitor C1is approximately dropped to the voltage of the third power source VDD. When the low voltage is supplied to the first output terminal103, the eighteenth, nineteenth and twentieth transistors M18, M19and M20are turned off.

The eighteenth transistor M18is set to the turn-off state, and the voltage of the fourth node N4is raised to the voltage of the third power source VDD by the sixteenth transistor M16. When the fourth node N4is set to the voltage of the third power source VDD, the fourteenth, fifteenth, fourth and second transistors M14, M15, M4and M2are turned on.

When the fourteenth and fifteenth transistors M14and M15are turned on, the first power source VSS1is supplied to the third node N3, and accordingly, the third and first transistors M3and M1are turned off. When the fourth transistor M4is turned on, the voltage of the first power source VSS1is output to the first output terminal103(i.e., the supply of the carry signal carry is stopped (e.g., the level of the carry signal carry is at a low level)). When the second transistor M2is turned on, the voltage of the second power source VSS2is output to the second output terminal104(i.e., the supply of the scan signal is stopped (e.g., the level of the scan signal is at a low level)).

The stage circuits of embodiments of the present invention progressively supply the scan signal to the scan lines S1to Sn by repeating the aforementioned process. In embodiments of the present invention, the stages are driven using only one clock signal CLK, and hence the number of signal lines can be reduced or minimized. Accordingly, it is possible to reduce or minimize the power consumption and the mounting area of the signal lines.

Further, in embodiments of the present invention, leakage current can be reduced or minimized using the controller150, and accordingly, it is possible to secure the reliability of driving. Additionally, in embodiments of the present invention, the leakage current in the second output unit140can be reduced or minimized using the second power source VSS2higher than the first power source VSS1. In embodiments of the present invention, the carry signal is output from the first output unit130, and the scan signal is output from the second output unit140. In this case, the load of the first and second output units130and140is distributed, and accordingly, it is possible to ensure the reliability of driving.

FIG. 6is a graph illustrating a simulation result of a stage, corresponding to a driving frequency.

Referring toFIG. 6, the stage circuit of the embodiments of present invention stably outputs the scan signal at a high driving frequency of 122.88 kHz. Thus, the stage circuit of embodiments of the present invention can be applied to a display device that requires a high driving frequency.

FIG. 7is a graph illustrating a simulation result of the stage circuit of embodiments of the present invention.

Referring toFIG. 7, the stage circuits of embodiments of the present invention stably output the scan signal. That is, the transistors included in the stages of embodiments of the present invention are completely set to the turn-off state, and accordingly, it is possible to stably output the scan signal.

Meanwhile, in the embodiments described above, the scan driver has been described using the organic light emitting display, but embodiments of the present invention are not limited thereto. Actually, the scan driver of embodiments of the present invention can be applied to various display devices including the scan lines S1to Sn.

By way of summation and review, an organic light emitting display device includes a data driver configured to supply data signals to data lines, a scan driver configured to supply scan signals to scan lines, and a display unit including a plurality of pixels coupled to the scan lines and the data lines.

Pixels included in the display unit are selected when a scan signal is supplied to a scan line, to receive a data signal from a data line. The pixels receiving the data signal generate light with a predetermined luminance corresponding to the data signal, thereby displaying an image.

Meanwhile, the scan driver includes stage circuits respectively couple to the scan lines. Each stage circuit includes a plurality of transistors configured to supply scan signals to the scan lines. P-type (e.g., PMOS) or N-type (e.g., NMOS) transistors constituting the stage circuit may be concurrently or simultaneously formed with pixels. In this case, it is possible to reduce the manufacturing cost of the organic light emitting display device, etc.

However, in a case where the stage circuit is implemented with N-type transistors, the transistors may be not completely turned off due to the Vth shift of the transistors, and therefore, malfunction of the transistors may occur. Actually, in the N-type transistors, the Vth is negatively shifted, and accordingly, there occurs a case where the transistors are not turned off even in a state in which the voltage Vgs between gate and source electrodes of the transistors becomes 0V (i.e., Vgs=0V).

In the stage circuit and the scan driver using the same according to embodiments of the present invention, it is possible to reduce or minimize leakage current in the output unit, using a first power source and a second power source higher than the first power source. Further, in some embodiments of the present invention, some transistors are completely turned off using the controller during the period in which the carry signal is supplied. Accordingly, it is possible to ensure the reliability of driving. Additionally, the stage circuit of embodiments of the present invention is driven using one clock signal. Accordingly, it is possible to reduce or minimize the number of signal lines, to reduce power consumption of the signal lines and to decrease the mounting area of the signal lines.