Storage device and debugging method thereof

Disclosed is a storage device which generates dump data at occurrence of an error. The storage device includes a buffer memory comprising a dump area for storing the dump data, a wireless module configured to transmit the dump data to a wireless channel, and a storage controller configured to monitor a generation of the dump data, to turn on the wireless module at the generation of the dump data, and to transmit the dump data to the wireless module.

BACKGROUND

Embodiments of the inventive concept relate to a semiconductor memory device, and in particular, to a storage device and a debugging method thereof.

A flash memory device is being used as voice and image data storage media of information devices such as a computer, a smart phone, a personal digital assistant (PDA), a digital camera, a voice recorder, an MP3 player, a handheld PC, and the like. However, since an erase operation is performed before writing data at a flash memory, a unit of data to be written may be greater than a unit of data to be erased. This makes it difficult to utilize a file system for typical hard disk even in the case where a flash memory is used as an auxiliary storage device. In addition, the above-described characteristic means that sequential input/output processing of the flash memory is more efficient than non-sequential input/output processing.

A solid state drive (SSD) is a representative of a flash memory-based mass storage device. The use of the SSD diversifies as the demand for the SSD explosively increases. For example, the use of the SSD is divided into SSD for server, SSD for client, SSD for data center, and the like. The SSD for the above-described uses may be managed and maintained to provide high reliability and optimized quality of service.

However, an unexpected error may occur due to a hardware or software problem during an operation of the above-described SSD. In this case, the SSD may generate and collect dump data. The SSD from which an error arises is connected to a debugging tool or device to perform dump data based debugging. The SSD is separated from a host, on which it is mounted, to the debugging tool and is connected to a separate interface. For this reason, it is difficult to obtain all real-time state information at an error-occurring point in time for exact debugging about the SSD.

SUMMARY

Embodiments of the inventive concept provide a storage device which is capable of transmitting dump data or log information without loss in the case where a problem occurs and a debugging method thereof.

One aspect of embodiments of the inventive concept is directed to provide a storage device which generates dump data at occurrence of an error. The storage device may include a buffer memory comprising a dump area for storing the dump data, a wireless module configured to transmit the dump data to a wireless channel, and a storage controller configured to monitor a generation of the dump data, to turn on the wireless module at the generation of the dump data, and to transmit the dump data to the wireless module.

Another aspect of embodiments of the inventive concept is directed to provide a debugging method of a storage device electrically connected with a host, the debugging method including determining whether dump area exists in a dump area of a buffer memory, turning on a wireless module based on the determination result, transmitting the dump data to a debugging device through the wireless module, and turning off the wireless module.

DETAILED DESCRIPTION

Below an embodiment of the inventive concept is exemplified as a solid state drive using a flash memory device is a storage device according to an embodiment of the inventive concept. However, the scope and spirit of the inventive concept may not limited thereto. The inventive concept may be applied or implemented through different embodiments. In addition, the detailed description may be variously modified or changed without departing from the scope and spirit of the inventive concept.

FIG. 1is a block diagram illustrating a storage device, a server system including the same, and a debugging host according to an embodiment of the inventive concept. Referring toFIG. 1, a server system according to an embodiment of the inventive concept may include a host100and a storage device200. A debugging host300corresponding to a debugging tool may receive dump data from the storage device200through a wireless channel.

The host100may read or write data from or at the storage device200. The host100may write data at the storage device200or may generate a command CMD used to read data stored in the storage device200. In particular, the host100may search data stored in the storage device200in response to a request from a client and may provide the found result to the client.

The storage device200may provide data which the host100requests or may store data write requested by the host100. In particular, when various errors or problems occur, the storage device200may generate dump data and may store the dump data in an internal memory such as a buffer memory220. The dump data thus stored may be transmitted to the debugging host300automatically or in response to an external command. At this time, the dump data may be transmitted using a wireless channel.

To provide the dump data, the storage device200may include a storage controller210, the buffer memory220, and a nonvolatile memory device230. Data which is provided according to a write request of the host100may be programmed at the nonvolatile memory device230through the buffer memory220. If a read request is issued from the host230, data which exists in the nonvolatile memory device230or the buffer memory220may be provided to the host100. The storage controller210may control the buffer memory220and the nonvolatile memory device230based on a request of the host100. The buffer memory220may be, for example, a dynamic random access memory (DRAM).

When an error occurs, the storage controller210may collect information about a point in time when an error occurs and may store the collected information in the buffer memory220. The stored data may be the dump data. If the dump data is generated, the storage controller210may turn on (or activate) a wireless module (not shown) which the storage controller200includes and may transmit the dump data to the debugging host300through the wireless module. The transmission of the dump data may be performed automatically according to a policy of the storage device200or according to a command provided from the host300.

The debugging host300may receive the dump data from the storage device200through the wireless channel. The debugging host300may analyze an error arising from the storage device200using the dump data. The debugging host300may manually receive the dump data transmitted through the wireless channel. Alternatively, the debugging host300may request the dump data by providing a command/address to the storage device200when the wireless channel is activated.

The dump data may be transmitted to the debugging host through the wireless channel by the above-described configuration and function of the storage device according to an embodiment of the inventive concept. Accordingly, it may be possible to obtain the dump data without attaching and detaching the storage device200to and from a device for physical connection with the debugging tool. In addition, it is unnecessary to use a separate test interface (e.g., JTAG) for connecting to the debugging tool. In other words, it may be possible to provide convenience of debugging.

FIG. 2is a block diagram schematically illustrating a storage device200illustrated inFIG. 1. Referring toFIG. 2, the storage device200may include the storage controller210, the buffer memory220, the nonvolatile memory device230, and a wireless module240. The storage controller210may include a separate interface for transmission of dump data through the wireless module240.

The storage controller210may include a central processing unit (CPU)211, an inter-integrated circuit (I2C or I2C) interface212, a host interface213, a buffer manager215, and a flash interface217. The CPU211may transfer a variety of information, needed to perform a read/write operation about the nonvolatile memory device230, to registers of the host interface213and flash interface217. The CPU211may operate based on firmware which is provided for various control operations of the storage controller210. For example, the CPU211may execute a flash translation layer (FTL) for garbage collection for managing the nonvolatile memory device230, address managing, wear leveling, and the like.

The CPU211may detect a point in time when dump data is generated on the buffer memory220and may drive algorithm for activation/inactivation of the wireless module240and transmission of the dump data based on the detection result. That is, the CPU211may drive software modules for transmitting the dump data, collected on the buffer memory220, to the debugging host300. For example, the CPU211may include a detection module for detecting existence of dump data, a path activation module for activating a wireless module based on a detection result, and a transmission module for transmitting the detected dump data to the debugging host300through the wireless module240.

The I2C interface212may be a bus interface which allows a plurality of masters to share at least one slave. The I2C interface212may provide an interface between the storage controller210and an external device. The I2C interface212may be a bus interface which includes one serial data line SDA and one serial clock line SCL and supports bidirectional communication. In the protocol of the I2C interface212, a communication target may be determined as a bus master specifies a unique address of the communication target. The I2C interface212may use a bidirectional open collector line of a serial data line SDA and a serial clock line SCL to which a pull-up resistor is connected. A 7-bit address space may be defined by the protocol of the I2C interface212, and a part thereof may be reserved.

However, it may be understood that the I2C interface212is replaced with various protocols such as a system management bus (SMBus), a universal asynchronous receiver transmitter (UART), a serial peripheral interface (SPI), a high-speed inter-chip (HSIC), and the like. Data communication (e.g., transmission and reception) with any device which the bus master specifies may be possible through the I2C interface212. Since mechanism for evading bus competition is defined by the protocol of the I2C interface212, a device arbitrarily specified may operate as a master. The I2C interface212may establish a transmission path of dump data to the debugging host300at a point in time when the wireless module240is activated.

The host interface213may communicate with the host100. For example, the host interface213may provide a channel for communication with the host100. The host interface213may provide a physical connection between the host100and the storage device200. That is, the host interface213may interface with the storage device200in compliance with the bus format of the host100. The bus format of the host100may include at least one of a universal serial bus (USB), a small computer system interface (SCSI), a PCI express, ATA, a parallel ATA (PTA), a serial ATA (SATA), or a serial attached SCSI (SAS).

The buffer manager215may control read and write operations of the buffer memory220. For example, the buffer manager215may temporarily store write data or read data in the buffer memory220.

The flash interface217may exchange data with the flash memory device230. The flash interface217may write data transferred from the buffer memory220at the flash memory device230. Read data which is read out from the flash memory device230and is provided through a memory channel may be collected by the flash interface217. The collected data may be stored in the buffer memory220.

The buffer memory220may be used as an input/output buffer of the storage device200. In addition, the buffer memory220may store dump data of the storage device200. In the case where an error arises from the storage device200, the storage controller210may generate dump data and may write the dump data at a dump area225of the buffer memory220. The buffer memory220may store a status of the storage device200or various monitored information.

The nonvolatile memory device230may be a storage medium where data write-requested by the host100is finally stored. The nonvolatile memory device230may be connected with the flash interface217of the storage device200. The nonvolatile memory device230may include, for example, a flash memory. The nonvolatile memory device230may be implemented with nonvolatile memory elements such as electrically erasable and programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase-change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), spin-torque magnetic RAM (STT-MRAM), and the like. For descriptive convenience, it may be assumed that the nonvolatile memory device is a NAND flash memory.

In an embodiment of the inventive concept, a three dimensional (3D) memory array is provided. The 3D memory array is monolithically formed in one or more physical levels of arrays of memory cells having an active area disposed above a silicon substrate and circuitry associated with the operation of those memory cells, whether such associated circuitry is above or within such substrate. The term “monolithic” means that layers of each level of the array are directly deposited on the layers of each underlying level of the array.

In an embodiment of the inventive concept, the 3D memory array includes vertical NAND strings that are vertically oriented such that at least one memory cell is located over another memory cell. The at least one memory cell may comprise a charge trap layer. Each vertical NAND string may include at least one select transistor located over memory cells, the at least one select transistor having the same structure with the memory cells and being formed monolithically together with the memory cells.

The following patent documents, which are hereby incorporated by reference, describe suitable configurations for three-dimensional memory arrays, in which the three-dimensional memory array is configured as a plurality of levels, with word lines and/or bit lines shared between levels: U.S. Pat. Nos. 7,679,133; 8,553,466; 8,654,587; 8,559,235; and US Pat. Pub. No. 2011/0233648.

The wireless module240may exchange data with the debugging host300through the I2C interface212. The wireless module240may be a communication module using a ZigBee, Bluetooth or Wi-Fi manner. The wireless module240may be automatically turned on or off by the storage device200. Alternatively, the wireless module240may be turned on or off by a vendor unique command (VUC) provided from the host100.

With the above description, the storage device200may transmit dump data to the debugging host300through the wireless module240. The wireless module240may be controlled to be automatically turned on when the dump data is generated and to be automatically turned off if the transmission of the dump data is completed. Alternatively, the wireless module240may be controlled to be turned on or off according to the vendor unique command VUC. Accordingly, even though an error arises from the storage device200, the debugging host300may obtain dump data without attaching and detaching the storage device200thereto or therefrom.

FIG. 3is a flow chart schematically illustrating a dump data transmitting method of a storage device200according to an embodiment of the inventive concept. Referring toFIG. 3, the storage device200may automatically activate the wireless module240when dump data is generated and may transmit the dump data to the debugging host300.

In step S110, at a booting operation where power is supplied or reset is performed, the storage device200may initialize a setting about an operation of the storage device200. At this time, the wireless module240of the storage device200may be set to have a turn-off state. The wireless module240may be automatically turned on when the dump data is generated, and algorithm for transmitting the dump data to the debugging host300may be activated. In addition, a transfer mode about the dump data may be set. For example, one of an automatic transfer mode and a command transfer mode may be set with respect to the dump data.

In step S120, the storage device200may monitor whether dump data exists at the dump area225of the buffer memory220. A status of a point in time when a hardware problem or a software processing error of the storage device200occurs may be made up as the dump data. The dump data thus made up may be written at the dump area225of the buffer memory220. A detailed description about a manner in which dump data is made up at occurrence of an error is omitted. However, a manner for detecting generation of the dump data will be described using a manner such as writing of data at a specific area (e.g., the dump area225of the buffer memory220). However, the scope and spirit of the inventive concept may not be limited thereto.

In step S130, an operation of the storage controller210may branch according to whether the dump data is stored in the dump area225. If the dump data is not collected or recorded in the dump area225(No), the procedure may return to step S120to monitor the generation of the dump data. In contrast, if the dump data exists in the dump area225(Yes), the procedure may proceed to step S140.

In step S140, the storage controller210may turn on the wireless module240in response to the generation of the dump data. The storage controller210may activate the wireless module240for the transmission of the dump data only when the dump data is detected.

In step S150, the storage controller210may transmit the dump data to the debugging host300through the wireless module240. The transmission of the dump data through the wireless module240may be performed through the I2C interface212of the storage controller210.

If the transmission of the dump data is completed, in step S160, the storage controller210may turn off the wireless module240. Whether the transmission of the dump data is completed may be determined through a response from the debugging host300.

With the above description, it may be possible to transmit the dump data, which is generated at a point in time when an error occurs, to the debugging host300without loss. In addition, since the storage device200is not detached from the host100, it may be possible to prevent information from being lost due to detachment from the host100.

FIG. 4is a flow chart schematically illustrating a dump data transmitting procedure (S150) according to an embodiment of the inventive concept. Referring toFIG. 4, the storage device200may operate in an automatic transfer mode about dump data and a command transfer mode controlled by a command of the debugging host300. This will be in more detail described below.

In step S151, the storage controller210may check a transfer mode about the dump data. The storage controller210may determine whether a transfer mode is an automatic transfer mode or a command transfer mode. If the transfer mode is the automatic transfer mode (Yes), the procedure may proceed to step S152. In contrast, if the transfer mode is the command transfer mode (No), the procedure may proceed to step S154.

In step S152, the storage controller210may automatically transmit the dump data to the debugging host300through the wireless module240without an external command or control. That is, the storage controller210may transmit the dump data stored in the buffer memory220to the wireless module240through the I2C interface212. The wireless module240may transmit the dump data provided through the I2C interface212to the debugging host300in a wireless transmission manner. At this time, a transaction between the wireless module240and the debugging host300may be performed once or two or more times.

In step S153, the storage controller210may determine whether the debugging host300successfully receives the dump data. If receiving from the debugging host300a complete signal informing that the dump data is successfully received (Yes), the storage controller210may determine an overall automatic transfer operation of mode about the dump data as being completed. Accordingly, the storage controller210may terminate step S150for the transmission of the dump data, and the procedure may proceed to step S160in which the wireless module240is turned off. However, if the storage controller210does not receive from the debugging host300a complete signal informing that the dump data is successfully received (No), the procedure may proceed to step S154.

In step S154, the storage controller210may wait for an external command. This may be the case that the transfer mode is not the automatic transfer mode or the storage controller210does not receive a signal indicating that the debugging host300successfully receive dump data. Here, the external command may be a command provided from the debugging host300. However, it may be understood that the external command is provided from the host100of a server.

In step S155, the storage controller210may determine whether the external command exists. In the case where the external command is not provided, the procedure may proceed to step S157to check a time which elapses to wait for the external command. In the case where the external command is provided, the procedure may proceed to step S156.

In step S156, the storage controller may transmit collected dump data to the debugging host300in response to the external command. The debugging host300may request reading about dump data from the storage device200through a wireless channel. The storage controller210may transmit the collected dump data through the wireless channel in response to a command from the debugging host300.

In step S157, the storage controller210may determine whether the external command is provided within a timeout. If a specific time does not elapse (e.g., timeout does not occur) (No), the storage controller210may continue to wait for the external command. If the specific time elapses (e.g., the timeout occurs) (Yes), the procedure may proceed to step S160, in which the wireless module240is turned off, without transmitting the dump data.

A detailed procedure of step S150in which dump data is transmitted to the debugging host300automatically or in response to an external command is exemplified. However, it may be understood that in the automatic transfer mode control signals are exchanged with the debugging host300to transmit the dump data.

FIG. 5is a diagram schematically illustrating a mutual relation between a storage device200and a debugging host300for transmission of dump data. Referring toFIG. 5, if dump data is collected, the storage device200may transmit the dump data to the debugging host300through a wireless module.

In step S10, the storage device200may detect an internal error or failure problem. In particular, the storage device200may determine the internal error or problem occurs, through existence of dump data or crash dump. According to a driving policy of the storage device200, in the case where the internal error occurs, all data associated with the error may be collected, and the collected data may recorded at the dump area225of the buffer memory220.

In step S12, the storage controller200may activate or turn on the wireless module240in response to the generation of the dump data. In a system of which power is not problematic, the wireless module240may be always turned on. However, the wireless module240may be used only in the case where the dump data is transmitted to the debugging host300. For this reason, the wireless module240may be set to be activated or turned on only in the case where the dump data is generated. Control about the wireless module240may be implemented through the I2C interface212as described above.

In step S13, the storage device200may transmit the collected dump data to the debugging host300through the wireless channel. Step S13is illustrated as being one data transmission step, but it may be a transfer mode according to an external mode or the automatic transfer mode. For the automatic transfer mode, the storage controller200may transmit the collected dump data to the debugging host300through the wireless module240. For the command transfer mode, the storage device200may wait until the external command is received. The storage device200may transmit the collected dump data based on a sequence of the external command for reading the dump data.

In step S14, the debugging host300may determine whether to successfully receive the dump data through the wireless channel. The debugging host300may transmit a receive success or a complete to the storage device200based on the determination result.

In step S15, the storage device200may determine the transmission of the dump data as being completed and may turn off the wireless module240. In the storage device200, the wireless module240may be controlled through the I2C interface212.

In step S16, the debugging host300may analyze the dump data including all status information of a point in time when an error occurs, without physical separation from the server or the host100. The dump data transmitted through the wireless channel by the wireless module240may include information which is able to be lost due to detachment of the storage device200for debugging. In addition, in the case of transmitting the dump data through the wireless channel, efforts for connecting to a separate debugging interface (e.g., JTAG) for connection with the debugging tool may be unnecessary. With the above description, in the case of analyzing the dump data transmitted through the wireless channel, it may be possible to analyze an error which is not detected due to information lost according to detachment of the storage device200.

FIG. 6is a flow chart schematically illustrating a dump data transmitting method of a storage device200according to another embodiment of the inventive concept. Even though dump data is generated, the storage device200may control the wireless module240based on a vendor unique command VUC. This will be in more detail described below.

In step S210, at a booting operation, the storage device200may initialize a setting about an operation thereof. The wireless module240of the storage device200may be set to have a turn-off or inactive state. Turn-on/off or activation/inactivation of the wireless module240may be set to be controlled by the vendor unique command VUC. Even though the dump data is collected, thus, the wireless module240may be first turned on or activated by the vendor unique command VUC to transmit the dump data to the debugging host300. In addition, a transfer mode in which the dump data is transmitted to the debugging host300may be set. For example, one of an automatic transfer mode and a command transfer mode may be set with respect to the dump data.

In step S220, the storage controller200may determine whether the vendor unique command VUC for controlling the wireless module240is received. This operation may be performed even in the case where the dump data is collected. However, the wireless module240may be activated to collect user data such as background data or metadata, not the dump data.

In step S230, an operation of the storage controller210may branch according to whether the vendor unique command VUC is received. In the case where the vendor unique command VUC for activating the wireless module240is received (Yes), the procedure may proceed to step S240. In the case where the vendor unique command VUC is not received (No), the procedure may proceed to step S220to continue to determine whether the vendor unique command VUC is received.

In step S240, the storage controller210may turn on the wireless module240in response to the vendor unique command VUC. Here, the storage controller210may use the I2C interface212to control the wireless module240.

In step S250, the storage controller210may transmit the dump data to the debugging host300through the wireless module240. The transmission of the dump data to the debugging host300through the wireless module240may be performed through the I2C interface212of the storage controller210. In addition, the transmission of the dump data may be performed according to the automatic transfer mode or the command transfer mode. An operation of step S250is similar to that of step S150described with reference toFIG. 4, and a detailed description thereof is thus omitted.

If the transmission of the dump data is completed, in step S260, the storage controller210may turn off the wireless module240. Whether the transmission of the dump data is completed may be determined through a response from the debugging host300. Furthermore, it may be understood that the wireless module240is turned off according to the vendor unique command VUC as at turn-on.

An embodiment of the inventive concept is exemplified as activation of the wireless module240and wireless transmission of dump data are performed according to the vendor unique command VUC. In the case where the wireless module240is controlled by the vendor unique command VUC, data may be transmitted independently of collection of the dump data. The wireless module240which is controlled by the vendor unique command VUC may be used to collect user data or background status information as well as dump data.

FIG. 7is a diagram schematically illustrating a method for transmitting dump data in a wireless manner using a vendor unique command VUC ofFIG. 6. Referring toFIG. 7, the wireless module240may be activated by the vendor unique command VUC from the host100. The storage device200may transmit the dump data to the debugging host300using the activated wireless module240.

In step S20, the host100may provide the vendor unique command VUC for controlling the wireless module240to the storage device200. This case may be the case that the vendor unique command VUC is provided after an internal error or problem arises from the storage device200. However, it may be understood that the vendor unique command VUC for activating the wireless module240is provided to establish a wireless channel for an access to user data. Below, it is assumed that the dump data is collected.

In step S21, the storage controller200may turn on or activate the wireless module240in response to the vendor unique command VUC. Control about the wireless module240may be implemented through the I2C interface212as described above.

In step S22, the storage device200may transmit the collected dump data to the debugging host300through the wireless channel. Here, step S22may correspond to an automatic transfer mode about dump data or a transfer mode performed according to an external command from the debugging host300. For the automatic transfer mode, the storage controller200may transmit the collected dump data to the debugging host300through the wireless module240without intervention of an external device. In contrast, in the case of the command transfer mode, the storage device200may transmit the collected dump data in response to the external command from the debugging host300.

In step S23, the debugging host300may determine whether to successfully receive the dump data through the wireless channel and may notify the storage device200of the determination result. The debugging host300may transmit a receive success or a complete to the storage device200.

In step S24, the storage device200may determine the transmission of the dump data as being completed, in response to the receive success. The storage device200may turn off or inactivate the wireless module240.

In step S25, the debugging host300may analyze the dump data including all status information of a point in time when an error occurs, without physical separation from the server or the host100. The dump data transmitted through the wireless channel by the wireless module240may include information which is able to be lost due to detachment of the storage device200for debugging. Furthermore, the debugging host300may establish a wireless access channel about user data using an authentication procedure and may obtain various background data or status information about the storage device200as well as dump data. With the above description, in the case of analyzing the dump data or the user data, it may be possible to analyze a problem which is not detected due to information lost according to detachment of the storage device200.

FIG. 8is a diagram schematically illustrating a method for transmitting dump data in a wireless manner using a vendor unique command, according to an embodiment of the inventive concept. Referring toFIG. 8, the wireless module240may be activated and inactivated by the host100. Steps S30to S33may be substantially the same as those S20to S23ofFIG. 7, and a detailed description thereof is thus omitted. That is, in step S33, the storage device200may receive from the debugging host300that the dump data is successfully received.

In step S34, the storage device200may notify the host100that the transmission of the dump data to the debugging host300is completed. In step S35, the host100may provide the vendor unique command VUC for turning off the wireless module240to the storage device200.

In step S36, the storage device200may turn off the wireless module240in response to the vendor unique command VUC from the host100. In step S37, the debugging host300may analyze the dump data transmitted through the wireless channel.

An embodiment of the inventive concept is exemplified as both turn-on and turn-off the wireless module240of the storage device200are controlled according to the vendor unique command VUC.

FIG. 9is a flow chart illustrating another embodiment of the inventive concept. Referring toFIG. 9, the debugging host300may access the buffer memory220of the storage device200through the wireless module240in a normal mode or an advanced mode. That is, the debugging host300may use the wireless channel in a normal mode manner where an access to the dump area is made for debugging. Alternatively, the debugging host300may use the wireless channel in an advance mode manner where an access to a user area of the buffer memory220of the storage device200is made at a debugging operation. This will be in more detail described below.

In step S310, the storage controller210may activate the wireless module240automatically or in response to the vendor unique command VUC.

In step S320, the storage controller210may determine whether the advanced mode allowing an access to a user area as well as dump data is supported to the debugging host300. An operation of the storage controller210may branch according to the determination result. In the case where the advanced mode is not supported (No), the procedure may proceed to step S345. In contrast, in the case where the storage controller210supports the advanced mode at the debugging operation (Yes), the procedure may proceed to step S330.

In step S330, the storage controller210may perform an authentication procedure of the debugging host300. For example, the storage controller210may request a password or an authentication key from the debugging host300and may determine whether inputted password or authentication key corresponds to specific information. Here, the password or the authentication key may be information which is based on ID information of the storage device210.

In step S340, an operation of the storage controller210may branch according to the authentication result. That is, in the case where authentication of the debugging host300succeeds (Yes), the procedure may proceed to step S350. In contrast, in the case where authentication of the debugging host300fails (No), the procedure may proceed to step S345.

In step S345, the storage controller210may allow the debugging host300to access the dump area225and may prevent the debugging host300from accessing the user area.

In step S350, the storage controller210may receive a command for an access to the user area. The debugging host300may provide the storage device200with a command/address for reading metadata, indicating an operating state of the storage device200, monitoring data, various driving information from the user area. If the command for an access to the user area is not received from the debugging host300(No), the procedure may proceed to step S355. In contrast, if the command for an access to the user area is received from the debugging host300(Yes), the procedure may proceed to step S360.

In step S355, the storage controller210may determine whether a command from the debugging host300is received within timeout. If a command/address for an access to a dump area225is received within the timeout (Yes), the procedure may proceed to step S365. If the command/address for an access to a dump area225is not received within the timeout (No), the procedure may proceed to step S370.

In step S360, the storage controller210may transmit user data, which the debugging host300requests, to the debugging host300through the wireless module240.

In step S370, the storage controller210may turn off or inactivate the wireless module240because the transmission of user data or dump data is completed or a command is not received within the timeout.

Although not shown, the debugging host300may analyze an error about the storage device200using the transmitted dump data or user data. The dump data or user data transmitted through the wireless channel by the wireless module240may include information which is able to be lost due to detachment of the storage device200for debugging. Various background data or state information about the storage device200may be obtained through the user data. With the above description, in the case of analyzing the dump data or the user data provided through the wireless channel, it may be possible to analyze a problem which is not detected due to information lost according to detachment of the storage device200.

FIG. 10is a block diagram schematically illustrating an area of a buffer memory220accessed in a normal mode or an advanced mode ofFIG. 9. Referring toFIG. 10, the dump area225of the buffer memory220may be read through a normal mode access by the debugging host300. In contrast, monitoring data or metadata227stored in a user area may be read by an advanced mode access.

FIG. 11is a block diagram illustrating a server system according to an embodiment of the inventive concept. Referring toFIG. 11, a server system400may include a server host410and a solid state drive420as storage. A debugging host500may receive dump data or user data from the solid state drive420through a wireless channel and may perform a debugging operation based on the received data.

The server host410may store data, which a client requests, in the solid state drive420. The server host410may search the solid state drive420and may provide data which a client requests.

The solid state drive420is connected to the server host410to exchange data therewith. The solid state drive420may include a plurality of solid state drives421,422,423,424, and425. Each of the solid state drives421,422,423,424, and425may include a wireless module which is independently activated/inactivated. In the case where an error arises from at least one (e.g.,424) of the solid state drives421,422,423,424, and425and the dump data is collected, the solid state drive424from which an error arises may activate the wireless module. The solid state drive424may transmit the collected dump data to the debugging host500automatically or based on a command. Here, the automatic transmission may mean that dump data is transmitted without intervention of an external device.

FIG. 12is a block diagram illustrating a server system according to another embodiment of the inventive concept. Referring toFIG. 12, a server system600may include a host610and a solid state drive620.

The solid state drive620may be connected to the server host610to exchange data therewith. The solid state drive620may include a plurality of solid state drives621,622,623,624, and625. Each of the solid state drives621,622,623,624, and625may include a wireless module which is independently activated/inactivated. In the case where an error arises from at least one (e.g.,624) of the solid state drives621,622,623,624, and625and the dump data is collected, the solid state drive624from which an error arises may activate the wireless module. The solid state drive624may transmit the collected dump data to a transceiver700through a wireless channel so as to be transmitted to a debugging host900through a network800. Dump data or user data received through the transceiver700may be transmitted to the debugging host900through the network800.

FIG. 13is a block diagram schematically illustrating a nonvolatile memory described inFIG. 1. Referring toFIG. 13, a nonvolatile memory230may include a memory cell array231, an address decoder232, a control logic and voltage generator circuit235, a page buffer233, and an input/output circuit234.

The memory cell array231may include a plurality of memory cells. Each of the memory blocks may include a plurality of cell strings. Each of the cell strings may include a plurality of memory cells. The memory cells may be connected with a plurality of word lines WL. Each memory cell may be a single level cell (SLC) storing one bit or a multi-level cell (MLC) storing at least two bits.

The address decoder232may be connected with the memory cell array231through the word lines WL, string selection lines SSL, and ground selection lines GSL The address decoder232may receive and decode a physical address ADD from an external device (e.g., the device controller110) and may drive the word lines based on the decoding result. For example, the address decoder232may decode a physical address ADD received from the external device, may select at least one of the word lines based on the decoded physical address ADD, and may drive the selected word line.

The control logic and voltage generator circuit235may control the address decoder232, the page buffer233, and the input/output circuit234in response to a storage command CMD and a control logic CTRL from the external device. For example, the control logic and voltage generator circuit235may control other components in response to the signals CMD and CTRL such that data is stored in the memory cell array231. Alternatively, the control logic and voltage generator circuit235may control other components in response to the signals CMD and CTRL such that data stored in the memory cell array231is transmitted to the external device.

The page buffer233may be connected to the memory cell array231through the bit lines BL. Under control of the control logic and voltage generator circuit235, the page buffer233may control the bit lines BL such that data provided from the input/output circuit234is stored in the memory cell array231. Under control of the control logic and voltage generator circuit235, the page buffer233may read data stored in the memory cell array231and may provide the read data to the input/output circuit234. For example, the page buffer233may be provided with data from the input/output circuit234by the page or may read data from the memory cell array231by the page.

The input/output circuit234may receive data from the external device and may transfer the received data to the page buffer233. Alternatively, the input/output circuit234may receive data from the page buffer233and may transmit the received data to the external device. For example, the input/output circuit234may exchange data with the external device in synchronization with the control signal CTRL.

The control logic and voltage generator circuit235may generate various voltages required for the nonvolatile memory230to operate. For example, the control logic and voltage generator circuit235may generate a plurality of program voltages, a plurality of pass voltages, a plurality of verification voltages, a plurality of selection read voltages, a plurality of non-selection read voltages, a plurality of erase voltages, and the like. The control logic and voltage generator circuit235may provide the generated voltages to the address decoder232or to a substrate of the memory cell array231.

FIG. 14is a circuit diagram schematically illustrating one of memory blocks included in a cell array of a nonvolatile memory device ofFIG. 13. InFIG. 14, there is illustrated a first memory block BLK1having a three-dimensional structure. However, the scope and spirit of the inventive concept is not limited thereto. The remaining memory blocks may have the same structure as the first memory block BLK1.

Referring toFIG. 14, the first memory block BLK1may include a plurality of cell strings CS11, CS21, CS12, and CS22. The cell strings CS11, CS21, CS12, and CS22may be arranged along a row direction and a column direction and may form rows and columns

For example, the cell strings CS11and CS12may be connected to string selection lines SSL1aand SSL1bto form a first row. The cell strings CS21and CS22may be connected to string selection lines SSL2aand SSL2bto form a second row.

For example, the cell strings CS11and CS21may be connected to a first bit line BL1to form a first column. The cell strings CS12and CS22may be connected to a second bit line BL2to form a second column

Each of the cell strings CS11, CS21, CS12, and CS22may include a plurality of cell transistors. Each of the cell strings may include string selection transistor SSTa and SSTb, a plurality of memory cells MC1to MC8, ground selection transistors GSTa and GSTb, and dummy memory cells DMC1and DMC2.

In exemplary embodiments, each of the memory cells included in the cell strings CS11, CS12, CS21, and CS22may be a charge trap flash (CTF) memory cell.

The memory cells MC1to MC8may be serially connected and may be stacked a height direction being a direction perpendicular to a plane defined by a row direction and a column direction. The string selection transistors SSTa and SSTb may be serially connected and may be disposed between the memory cells MC1to MC8and a bit line BL. The ground selection transistors GSTa and GSTb may be serially connected and may be disposed between the memory cells MC1to MC8and a common source line CSL.

In exemplary embodiments, a first dummy memory cell DMC1may be disposed between the memory cells MC1to MC8and the ground selection transistors GSTa and GSTb. In exemplary embodiments, a second dummy memory cell DMC2may be disposed between the memory cells MC1to MC8and the string selection transistors SSTa and SSTb.

The ground selection transistors GSTa and GSTb of the cell strings CS11, CS12, CS21, and CS22may be connected in common to a ground selection line GSL.

In exemplary embodiments, ground selection transistors in the same row may be connected to the same ground selection line, and ground selection transistors in different rows may be connected to different ground selection lines. For example, the first ground selection transistors GSTa of the cell strings CS11and CS12in the first row may be connected to a first ground selection line, and the first ground selection transistors GSTa of the cell strings CS21and CS22in the second row may be connected to a second ground selection line.

In exemplary embodiments, although not shown, ground selection transistors placed at the same height from a substrate may be connected to the same ground selection line, and ground selection transistors placed at different heights therefrom may be connected to different ground selection lines. For example, the first ground selection transistors GSTa of the cell strings CS11, CS12, CS21, and CS22may be connected to the first ground selection line, and the second ground selection transistors GSTb thereof may be connected to the second ground selection line.

Memory cells placed at the same height from the substrate (or the ground selection transistors GSTa and GSTb) may be connected in common to the same word line, and memory cells placed at different heights therefrom may be connected to different word lines. For example, the first to eighth memory cells MC8of the cell strings CS11, CS12, CS21, and CS22may be connected in common to first to eighth word lines WL1to WL8, respectively.

String selection transistors, belonging to the same row, from among the first string selection transistors SSTa at the same height may be connected to the same string selection line, and string selection transistors belonging to different rows may be connected to different string selection lines. For example, the first string selection transistors SSTa of the cell strings CS11and CS12in the first row may be connected in common to the string selection line SSL1a, and the first string selection transistors SSTa of the cell strings CS21and CS22in the second row may be connected in common to the string selection line SSL1a.

Likewise, string selection transistors, belonging to the same row, from among the second string selection transistors SSTb at the same height may be connected to the same string selection line, and string selection transistors in different rows may be connected to different string selection lines. For example, the second string selection transistors SSTb of the cell strings CS11and CS12in the first row may be connected in common to a string selection line SSL1b, and the second string selection transistors SSTb of the cell strings CS21and CS22in the second row may be connected in common to a string selection line SSL2b.

Although not shown, string selection transistors of cell strings in the same row may be connected in common to the same string selection line. For example, the first and second string selection transistors SSTa and SSTb of the cell strings CS11and CS12in the first row may be connected in common to the same string selection line. The first and second string selection transistors SSTa and SSTb of the cell strings CS21and CS22in the second row may be connected in common to the same string selection line.

In exemplary embodiments, dummy memory cells at the same height may be connected to the same dummy word line, and dummy memory cells at different heights may be connected with different dummy word lines. For example, the first dummy memory cells DMC1may be connected to a first dummy word line DWL1, and the second dummy memory cells DMC2may be connected to a second dummy word line DWL2.

In the first memory block BLK1, read and write operations may be performed by the row. For example, one row of the first memory block BLK1may be selected by the string selection lines SSL1a, SSL1b, SSL2a, and SSL2b.

For example, the cell strings CS11and CS12of the first row may be connected to the first and second bit lines BL1and BL2when a turn-on voltage is supplied to the string selection lines SSL1aand SSL1band a turn-off voltage is supplied to the string selection lines SSL2aand SSL2b. The cell strings CS21and CS22of the second row may be connected to the first and second bit lines BL1and BL2when a turn-on voltage is supplied to the string selection lines SSL2aand SSL2band a turn-off voltage is supplied to the string selection lines SSL1aand SSL1b. Memory cells, having the same height, from among memory cells of cell strings in a driven row may be selected by driving a word line. A read or write operation may be performed with respect to the selected memory cells. The selected memory cells may constitute a physical page.

In the first memory block BLK1, erasing may be performed by the memory block or by the sub-block. When erasing is performed by the memory block, all memory cells MC of the first memory block BLK1may be simultaneously erased according to one erase request. When erasing is performed by the sub-block, a part of memory cells MC in the first memory block BLK1may be simultaneously erased according to one erase request, and the other thereof may be erase-inhibited. A low voltage (e.g., a ground voltage) may be supplied to a word line connected to the erased memory cells, and a word line connected to erase-inhibited memory cells may be floated.

The first memory block BLK1illustrated inFIG. 14may be exemplary. For example, the number of cell strings may increase or decrease, and the number of rows of cell strings and the number of columns of cell strings may increase or decrease according to the number of cell strings. In the first memory block BLK1, the number of cell strings (GST, MC, DMC, SST, or the like) may increase or decrease, and a height of the first memory block BLK1may increase or decrease according to the number of cell strings (GST, MC, DMC, SST, or the like). Furthermore, the number of lines (GSL, WL, DWL, SSL, or the like) connected with cell transistors may increase or decrease according to the number of cell strings (GST, MC, DMC, SST, or the like).

FIG. 15is a block diagram illustrating a solid state drive including a nonvolatile memory system according to an embodiment of the inventive concepts. Referring toFIG. 175a solid state drive (SSD) system1000may include a host1100and an SSD1200. The SSD1200may exchange signals SGL with the host1100through the host interface1001and may be supplied with a power through a power connector1002. The SSD1200may include an SSD controller1210, a plurality of flash memories1221to122n, an auxiliary power supply1230, a buffer memory1240, and a wireless module1250.

The SSD controller1210may control the flash memories1221to122nin response to the signal SIG from the host1100. In an embodiment, the SSD controller1210may transmit dump data or user data to a debugging host (not shown) through the wireless module1250based on components described with reference toFIG. 2.

The auxiliary power supply1230may be connected to the host1100via the power connector1002. The auxiliary power supply1230may be charged by a power PWR from the host1100. When a power is not smoothly supplied from the host1100, the auxiliary power supply1230may power the SSD system1000. The auxiliary power supply1230may be placed inside or outside the SSD1200. For example, the auxiliary power supply1230may be put on a main board to supply an auxiliary power to the SSD1200.

The buffer memory1240may act as a buffer memory of the SSD1200. For example, the buffer memory1240may temporarily store data received from the host1100or from the flash memories1221to122nor may temporarily store metadata (e.g., mapping tables) of the flash memories1221to122n. The buffer memory1240may include volatile memories such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, SRAM, and the like or nonvolatile memories such as FRAM ReRAM, STT-MRAM, PRAM, and the like.

FIG. 16is a block diagram illustrating a user system including a storage device according to an embodiment of the inventive concept. Referring toFIG. 16, a user system2000may include an application processor2100, a memory module2200, a network module2300, a storage module2400, and a user interface2500.

The application processor2100may drive components, an operating system, and the like of the user system2000. For example, the application processor2100may include controllers for controlling components of the user system2000, graphics engines, a variety of interfaces, and the like. For example, the application processor2100may be a system-on-chip (SoC).

The memory module2200may operate as a main memory, a working memory, a buffer memory, or a cache memory of the user system2000. The memory module2200may be implemented with a volatile random access memory, such as DRAM, SDRAM, double date rate DRAM (DDR SDRAM), DDR2 SDRAM, DDR3 SDRAM, LPDDR DRAM, LPDDR2 DRAM, or LPDDR3 DRAM or a nonvolatile random access memory, such as PRAM, MRAM, RRAM, or FRAM.

The network module2300may communicate with external devices. For example, the network module2300may support wireless communications, such as code division multiple access (CDMA), global system for mobile communication (GSM), wideband CDMA (WCDMA), CDMA-2000, time division multiple access (TDMA), long term evolution (LTE), Wimax, WLAN, UWB, Bluetooth, WI-DI, and the like. In an embodiment, the network module2300may be included in the application processor2100.

The storage module2400may store data. For example, the storage module2400may store data received from the application processor2100. Alternatively, the storage module2400may provide the application processor2100with data stored therein. For example, the storage module2400may be implemented with a semiconductor memory device such as PRAM, MRAM, RRAM, NAND flash memory, NOR flash memory, or a three-dimensional NAND flash memory.

The storage module2400may include a wireless module2450. The storage module2400may transmit dump data, which is collected in a buffer memory of the storage module2400such as a DRAM, to a debugging device automatically or based on an external command.

The user interface2500may include interfaces which input data or a command in the application processor2100or output data to an external device. For example, the user interface2500may include user input interfaces such as a keyboard, a keypad, buttons, a touch panel, a touch screen, a touch pad, a touch ball, a camera, a microphone, a gyroscope sensor, a vibration sensor, and the like. The user interface2500may further include user output interfaces such as a liquid crystal display (LCD), an organic light-emitting diode (OLED) display device, an active matrix OLED (AMOLED) display device, a light-emitting diode (LED), a speaker, a motor, and the like.

A flash memory device and/or a memory controller according to the inventive concept may be packaged according to any of a variety of different packaging technologies. Examples of such packaging technologies may include the following: package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carrier (PLCC), plastic dual in-line package (PDIP), die in waffle pack, die in wafer form, chip on board (COB), ceramic dual in-line package (CERDIP), plastic metric quad flat pack (MQFP), small outline (SOIC), shrink small outline package (SSOP), thin small outline (TSOP), thin quad flatpack (TQFP), system in package (SIP), multi-chip package (MCP), wafer-level fabricated package (WFP), and wafer-level processed stack package (WSP).

According to an embodiment of the inventive concept, it may be possible to transmit dump data to a debugging tool without physical separation from a host or without power-off of a storage device. In addition, the storage device of the inventive concept may provide state information for monitoring of the storage device through a wireless channel with an authentication procedure at a user request. Accordingly, the storage device of the inventive concept may enable debugging of high reliability and may markedly reduce a cost for the debugging.