Digital phase comparator and frequency synthesizer

The phase of a pulsed test signal is measured with reference to a reference signal of constant frequency by sampling the test signal at times determined by transitions in the reference signal and comparing the sampled test signal with the output of a phase accumulator clocked by the reference signal. A resulting measurement signal represents a difference in the number of transitions occurring in the sampled test signal and a reference state signal output by the phase accumulator. The measurement signal may be averaged and integrated to obtain an error signal which may then be filtered to provide a control signal for an oscillator. A digital frequency synthesizer is provided by frequency dividing the output of the oscillator by a constant multiple to obtain the test signal and integrating an offset signal in addition to the averaged measurement signal so that the operating frequency of the oscillator is offset from a nominal frequency by an amount determined by the offset signal. The digital frequency synthesizer is suitable for use in a synchronous equipment timing source within a telecommunications multiplexer operating at a line transmission rate of 155.52 MHz.

INTRODUCTION 
This invention relates to a digital phase comparator and to a digital 
frequency synthesizer primarily but not exclusively for use in processing 
electronic signals in an optical communications system. 
BACKGROUND TO THE INVENTION 
The use of phase comparators is commonplace in the processing of received 
signals in communications systems, typically forming part of phase locked 
loops in clock recovery circuits and frequency synthesizer circuits. 
Analog phase comparators are well established and are both fast and 
accurate. For certain applications however, analog phase detectors cannot 
be utilised since, for example, they cannot directly derive phase 
information from signals of different frequencies without first dividing 
the signals to a common frequency. 
The output of analog phase detectors is also not suitable for directly 
driving digital circuits. Consequently, all-digital phase comparators have 
been utilised in circuits requiring subsequent digital signal processing, 
as for example disclosed in U.S. Pat. No. 4,504,799. 
A commonly used form of digital phase comparator effects comparison of 
phase by counting over a predetermined time period a number of pulses for 
a signal under test and comparing it with a count for the same period of 
pulses of a reference signal, such as derived from a stable clock. A 
disadvantage of this technique, as discussed in U.S. Pat. No. 5,084,669, 
is that it provides limited resolution since the count is based on 
integral numbers of pulses and also there is a trade off between the 
response time and accuracy because, in order to improve accuracy, the 
predetermined time period must be extended. 
It is also known from U.S. Pat. No. 5,519,343 to utilise a phase 
accumulator to synthesise a desired frequency by adding at each cycle of a 
clock signal a phase value to an accumulator value which is reset to zero 
when the accumulated value reaches a maximum value, one cycle of the 
output frequency being generated at each reset. 
SUMMARY OF THE INVENTION 
It is an object of the present invention to provide an improved digital 
phase comparator capable of achieving a response time comparable with that 
of analog circuits. 
It is a further object of the present invention to provide a digital phase 
comparator with improved accuracy. 
It is a further object of the present invention to provide a digital 
frequency synthesizer employing an improved digital phase comparator. 
According to the present invention there is disclosed a method of measuring 
the phase of a pulsed test signal having a variable test signal frequency, 
the phase being measured with reference to a pulsed reference signal 
having a substantially constant reference signal frequency, the method 
comprising the steps of; 
sampling the test signal at sampling times determined by transition events 
in the reference signal to obtain a sampled test signal; 
driving a phase accumulator clocked by the reference signal to generate a 
pulsed reference state signal having a predetermined frequency which is 
related to the reference frequency by a fixed ratio other than unity; 
comparing the reference state signal and the sampled test signal; and 
outputting as a result of the comparison a measurement signal 
representative of a difference in the number of transitions occurring in 
the reference state signal and the sampled test signal, whereby the 
measurement signal provides a measure of said phase difference. 
According to a further aspect of the invention there is disclosed apparatus 
for measuring the phase of a pulsed test signal having a variable test 
signal frequency, the apparatus comprising; 
a reference oscillator operable to produce a reference signal having a 
substantially constant reference signal frequency; 
sampling means operable to sample the test signal at sampling times 
determined by transition events in the reference signal to obtain a 
sampled test signal; 
a phase accumulator responsive to the reference signal to generate a pulsed 
reference state signal having a predetermined frequency which is related 
to the reference frequency by a fixed ratio other than unity; and 
comparing means operable to compare the reference state signal and the 
sampled test signal and to output as a result of the comparison a 
measurement signal representative of a difference in the number of 
transitions occurring in the reference state signal and the sample state 
signal, whereby the measurement signal comprises a measure of said phase 
difference. 
According to a further aspect of the invention there is disclosed a digital 
frequency synthesizer comprising; 
an oscillator controlled by an analogue control signal to have a nominal 
output signal frequency when the control signal is zero; 
a digital phase detector operable to output a measurement signal 
representative of the phase of the output signal relative to a reference 
signal derived from a stabilised reference signal; 
a digital integrator clocked by the reference signal and responsive to the 
measurement signal to increment a summation value; 
means for converting the summation value of the integrator into the 
analogue control signal; and 
means for generating an offset signal input to the integrator to 
selectively increment the summation value such that the control signal 
controls the oscillator to operate at a frequency which is offset from the 
nominal frequency by an amount determined by the offset signal. 
Preferred embodiments of the present invention will now be described by way 
of example only and with reference to the accompanying drawings.

DESCRIPTION OF THE PREFERRED EMBODIMENTS 
FIG. 1 illustrates a digital phase comparator 1 in which a test signal TS 
from a test signal input 2 is subjected to phase comparison relative to a 
clock reference signal CR from a reference oscillator 3. The frequencies 
of the test signal TS and clock reference signal CR are different and it 
is a function of the digital phase comparator 1 to detect fluctuation in 
the phase or frequency of the test signal TS using the output of the 
reference oscillator for comparison and to output a phase difference 
signal DP in the form of a digital signal synchronised with the clock 
reference signal CR. 
In the present example, the test signal TS has a frequency of 19.44 MHz 
which is greater than the frequency of the reference oscillator 2 which is 
stable frequency of 16.384 MHz. The test signal TS is sampled in a sampler 
4 at the frequency of reference signal CR to produce an aliased clock 
signal AS which, in the absence of error in the test signal TS, has a 
frequency of 3.056 MHz. The aliased clock signal AS is referred to as 
being aliased since it is the product of sampling the test signal TS at a 
sampling frequency which is lower than that of the test signal. 
The clock reference signal CR is also input to a phase accumulator 5, the 
output of which will be referred to as a reference state signal RS having 
a frequency of 3.056 MHz, i.e. the expected value of the frequency of the 
aliased clock signal, but accurately controlled in frequency relative to 
the clock reference signal CR. 
Both the aliased clock signal AS and the reference state signal RS are 
input to a logic circuit 6 operating synchronously with the clock 
reference signal CR to output a value of the phase difference signal DP. 
FIG. 2 illustrates graphically the signals of FIG. 1. The clock reference 
signal CR is a square wave signal which is substantially constant in 
frequency, being generated by the temperature compensated reference 
oscillator 3. The sampler 4 operates to sample the test signal TS at each 
positive going transition of the reference signal to produce the aliased 
clock signal AS which may be regarded as a binary level signal 
synchronised with the clock reference signal CR. 
The phase accumulator 5 is implemented as a ten bit counter which is 
incremented by 191 at each positive going transition of the clock 
reference signal CR, the most significant bit of the counter being output 
as the reference state signal RS. As illustrated in FIG. 2, the reference 
state signal RS is a binary waveform which is irregular in shape but for 
which nevertheless the number of positive going transitions of the 
reference state signal RS is accurately equal to 3.056 MHz, to a stability 
determined by the stability of the reference oscillator 3. 
The logic circuit 6 operates to detect at sampling times at each positive 
going transition of the reference signal CR whether any transition occurs 
in the reference state signal RS and the aliased clock signal AS and 
outputs a measurement signal DP accordingly. As shown in FIG. 2, for a 
given sampling time, the phase measurement signal DP has a value of 1 if 
either a positive or a negative transition occurs in the reference state 
signal RS in the absence of a simultaneous transition in the aliased clock 
signal AS. The phase measurement signal DP has a value of -1 if either a 
positive or negative going transition occurs in the aliased clock signal 
AS in the absence of a simultaneous transition in the reference state 
signal RS. If no transition occurs at a given sampling time in either RS 
or AS, the phase measurement signal DP has zero output. The phase 
measurement signal DP also has zero output if transitions occur 
simultaneously in both the reference state signal RS and the sampled test 
signal AS at a given sampling time. 
The time averaged value of the phase measurement signal DP provides 
therefore a measurement of the phase of the test signal TS such that, a 
time average of zero indicates that the test signal is matched exactly to 
the frequency of the reference state signal RS and any error occurring in 
the frequency of the test signal TS will result in a positive or negative 
average value of the phase measurement signal DP. Phase information is 
made available at each cycle of the clock reference signal CR. This 
information may be utilised in a variety of applications, responsive to a 
phase change of half of each 19.44 MHz cycle of the test signal TS. 
FIG. 3 illustrates an alternative arrangement which differs from the phase 
comparator of FIG. 1 by replacing the logic circuit 6 by an up-down 
counter 8 which is positively incremented at each transition of the 
aliased clock signal AS and decremented at each transition of the 
reference state signal RS. The output from the counter 8 is a count value 
CV which is input to a digital integrator 9. The count value CV represents 
the difference in phase of the test signal TS relative to the reference 
state signal RS so that the output of the integrator 9, when time 
averaged, will be an absolute measurement of phase. 
FIG. 4 illustrates a phase locked loop utilising the phase comparator of 
FIG. 1, corresponding reference numerals being utilised where appropriate 
for corresponding elements. 
The phase measurement signal DP output from the logic circuit 6 of the 
phase comparator is input to a digital integrator 10, the output of which 
is an error signal ES which is filtered in a low pass filter 11 before 
being used as a control input CI to a voltage controlled oscillator 12. 
The voltage controlled oscillator 12 generates a binary waveform having a 
nominal frequency of 155.52 MHz which is reduced by a frequency divider 13 
by a factor of one eighth to generate the test signal TS described above 
with reference to FIG. 1. 
The output of the integrator 10 is a binary signal having value zero when 
the integrand of the integrator is positive and having the value one when 
the integrand is negative. This binary signal is converted to an analog 
signal by the low pass filter 11 which removes high frequency noise. 
The voltage controlled oscillator 12 responds to the control input CI to 
adjust the frequency of output signal OS in a direction which reduces CI, 
thereby stabilising the frequency of the output signal OS to a frequency 
of 155.52 MHz. The circuit of FIG. 4 is therefore useful in applications 
where a single stable output frequency is required, the frequency and 
phase stability of the output signal being determined relative to a 
reference oscillator having a clock reference signal CR which is 
dissimilar from the output signal OS. It is not necessary for the output 
signal OS to be an integral multiple of the clock reference signal CR, the 
relationship between the frequencies being determined by the configuration 
of the phase accumulator 5 and frequency divider 13. 
FIG. 5 illustrates an alternative phase locked loop similar to the 
arrangement of FIG. 4 and which will be described using corresponding 
reference numerals where appropriate. The phase locked loop of FIG. 5 
inputs the phase measurement signal DP to an averager 7 which outputs an 
averaged measurement signal AV having a waveform as shown in FIG. 2A. The 
averaged measurement signal is determined at each positive going 
transition of the clock reference signal CR to be the average value of the 
phase measurement signal DT over the preceding two cycles of the clock 
reference signal, i.e. the previous two values of the phase measurement 
signal. The averaged measurement signal AV is a three bit binary signal 
which is input to the digital integrator 10. The integrator output is 
filtered by the low pass filter 11 before being input as the control input 
signal CI to the voltage controlled oscillator 12. Since the available 
values of the average measurement signal AV are -1, -1.5, 0, 1.5 and 1, 
the use of the averager 7 provides increased resolution in the 
determination of the control input CI. 
More generally, an averager as illustrated in FIG. 5 operates to calculate 
an average over an averaging block of n sample values of the phase 
measurement DP. The n=2 example illustrated in FIG. 2A is the simplest 
arrangement which will provide improved resolution by a factor of 2. 
Extending the average block to n samples will increase the resolution by a 
factor of n, the value of a being generally an integral power of 2. 
FIG. 6 illustrates a frequency synthesizer which incorporates a phase 
detector 15 representing any one of the digital phase comparator circuits 
referred to in preceding figures for presenting the input signal DP or AV 
to the integrator 10. 
The frequency synthesizer of FIG. 6 has a voltage controlled oscillator 12 
of which the frequency of operation is stabilised by operation of a phase 
locked loop relative to the stable clock reference signal CR, any phase 
error being detected by the phase detector 15 and nulled by the effect of 
the error signal ES and control input CI on the oscillator 12. 
In order to variably select the stabilized frequency of output signal OS 
from the voltage controlled oscillator 12, an additional input to the 
integrator 10 is provided by an offset generator 16. The offset generator 
16 outputs pulses OG to either increment or decrement the integrand of the 
integrator 10, the frequency with which such pulses are generated being 
determined by a demand input signal DI from a demand input 17. The effect 
of a constant stream of "UP" pulses OG is to increase the average output 
of the integrator 10 and hence to raise the level of the control input CI 
to the voltage controlled oscillator 12. The effect of a constant stream 
of "DOWN" pulses OG is to decrease the average output of the integrator 
10. In this way, the frequency of the output signal OS can be offset by a 
predetermined amount relative to the nominal value of the frequency of the 
output signal in the absence of pulses OG. 
In this example, the offset generator 16 is a three bit counter used in 
signed notation and counting from -4 to +3. The counter is incremented by 
an external clock pulse provided by the signal DI from the demand input 
17. The counter generates a positive to negative transition at every eight 
clock pulses, the resulting positive to negative transition being used to 
increment or decrement the integrator 10 by outputting the up or down 
pulse OG as required. An increment value input 18 contains a set value 
determining the amount by which the offset generator counter 16 is 
incremented at each cycle of the demand input DI. The amount by which the 
voltage controlled oscillator 12 is offset in operating frequency from the 
nominal frequency is determined therefore both by the frequency of the 
demand input signal DI and the increment value 18. 
In this way the voltage controlled oscillator 12 can be driven at any 
desired frequency different from the clock reference signal CR while at 
the same time being stabilised using digital phase detection in which the 
phase information is measured and processed in synchronism with the clock 
reference signal CR. 
FIG. 7 illustrates a further example of a frequency synthesizer, similar to 
the synthesizer of FIG. 6 but in which the phase detector 15 is replaced 
by a specific example similar to that of FIG. 5. Corresponding reference 
numerals are used where appropriate for corresponding elements in 
preceding figures. 
The frequency synthesizer of FIG. 7 includes a reference oscillator 3 
providing clock reference signal CR at 16.384 MHz and driving a phase 
accumulator 5 which outputs a reference state signal RS having a frequency 
of 3.056 MHz. Test signal TS is input to a sampler 4 where it is sampled 
at each positive transition of the clock reference signal CR, the test 
signal TS being derived from the output signal OS via the one eighth 
frequency divider 13. 
Logic circuit 6 generates phase measurement signal DP in response to the 
input of the reference state signal RS and the aliased clock signal AS 
output from the sampler 4. Averager 7 provides improved resolution by a 
factor n of the phase measurement signal DP and outputs an averaged 
measurement signal AV which is input to an integrator 10. 
The output of the integrator 10 is a binary level error signal ES which is 
filtered in a low pass filter 11 to provide an analogue control input 
signal CI to the voltage controlled oscillator 12. 
FIG. 9 illustrates schematically the integrator 10 which is a digital 
circuit clocked by the clock reference signal CR and including a summing 
block 21 which maintains an integrand by summation of input numerical 
values. The output of the summing block is an integrand signal S, the sign 
of which is extracted by sign block 22 which outputs the error signal ES 
in the form of a binary signal representative of whether the integrand is 
positive or negative. 
An offset generator 16 as shown in FIG. 7 is operable to input pulses OG to 
the integrator 10 for incrementing or decrementing the integrand in order 
to set an offset in the stable oscillating frequency of the voltage 
controlled oscillator 12 relative to its nominal frequency of operation. 
The offset generator 16 is driven by an outer loop control block 19 which 
variably determines the frequency with which the pulses OG are input to 
the integrator 10. The outer loop control block 19 transmits an external 
clock signal EC to the offset generator 16 for this purpose, thereby 
enabling pulses OG from the offset generator to be input at regular 
intervals to the integrator 10. The frequency of EC is determined 
according to user requirements and, in the synthesizer of FIG. 7, a 
multiplexer 20 allows one of three possible external clock signals to be 
selected. Input to the multiplexer 20 is an internal signal INT equal to 
the clock reference signal CR, an external input of 8 KHz, TRIB, and a 
further external signal at 2.048 MHz "EXT". This selection of inputs to 
the multiplexer 20 corresponds to an application of the frequency 
synthesizer of FIG. 7 in a synchronous equipment timing source within an 
STM-1 telecommunications multiplexer operating at a line transmission rate 
of 155.52 MHz. 
In each of the above described embodiments, the accuracy of phase detection 
and subsequent frequency control may be doubled by operating the sampler 4 
so as to sample the test signal TS on both positive and negative 
transitions of the clock reference signal CR. As shown in FIG. 8, two 
aliased clock signals AS1 and AS2 are produced, corresponding to sampling 
on the positive and negative transitions respectively, and are input to 
the logic circuit 6. The count of transitions within logic circuit 6 is 
incremented if a transition is detected on either one of the aliased clock 
signal AS1 and AS2 and incremented by 2 if transitions are detected 
simultaneously on both. The phase accumulator 5 outputs a reference state 
signal RS2 having a frequency which is twice that of the frequency 
required when only single transitions are sampled, i.e. 6.112 MHz. The 
phase accumulator 5 for this embodiment may similarly comprise a ten bit 
counter but taking the output from the 9th bit of the counter instead of 
from the tenth bit as in the case of previous embodiments.