Memory device and power management method using the same

A memory device that is operable at a first voltage domain and a second voltage domain includes a memory array, a power saving mode pin and a word line level shifter circuit. The memory array operates at the first voltage domain. The power saving mode pin is configured to receive a power saving mode enable signal that is at the second voltage domain. The power saving mode enable signal is configured to enable a power saving mode of the memory device. The word line level shifter circuit is coupled to the memory array and the power saving mode pin, and is configured to clamp a word line of the memory array to a predetermined voltage level that corresponds to a first logic state during the power saving mode of the memory device.

BACKGROUND

A memory device may come with a power management mode or without the power management mode. In the memory device with the power management mode, a shutdown (SD) mode and a deep sleep (DSLP) mode may be implemented in the memory device to manage power consumption of the memory device. However, there exists a considerable leakage in the memory device with the existing power management modes (e.g., SD and DSLP modes), as an external power supply to the memory device are not switched off during the SD and DSLP mode and external memory array supply voltage is alive for retaining data in memory array in the DSLP mode. In the memory device without the power management mode, power management is performed at a system level and is shared for all the memory devices in the system. There is a large power dissipation and a large peak current as a word line level of the memory device is unknown during power up of external supply voltage.

As a demand for a memory device with high quality and low power consumption, a creative design of a memory device that is capable of lowering the power consumption is highly desired.

DESCRIPTION OF THE EMBODIMENTS

FIG.1illustrates a schematic diagram of a memory device100that operates at multiple voltage domains (e.g., a VDDM domain and a VDDP domain) in accordance with some embodiments, where the VDDM and VDDP stand for supply voltages of different levels. The voltage levels of the VDDM domain are higher than voltage levels of the VDDP domain. In some embodiments, the memory device100is not equipped with a power management mode such as a shutdown (SD) mode and/or a deep-sleep (DSLP) mode. The power management of the memory device100is performed in a system level by a memory system that includes the memory device100.

In some embodiments, the memory device100includes a memory array110, a word line (WL) level shifter (LS) circuit120, a WL driver130, a control circuit140and an input/output (TO) circuit150. The memory array110may include a plurality of memory cells MC that are configured to store data. The memory cells MC of the memory array110may be coupled to a plurality of word lines, a plurality of bit lines and a plurality of source lines, where a memory operation to the memory cells MC is performed through the word lines, the bit lines and the source lines. In some embodiments, the memory cells MC of the memory array110are static random-access memory cell (SRAM), but the disclosure is not limited to any particular type of memory cells. In some alternative embodiments, the memory cells MC may be phase-change random-access memory (PCRAM) cells, magnetoresistive random-access memory (MRAM) cells, resistive random-access memory (RRAM) cells, or any other suitable memory cells.

The WL driver130may drive the word lines of the memory array110according to a signal WLB that may be outputted by a row decoder (not shown). In some embodiments, the memory array110operates at the VDDM domain and the WL driver130operates at the VDDP domain. As the voltage domains of the WL driver130and the memory array110are different, the WL driver130drives the word lines of the memory array110through the WL level shifter circuit120. The WL level shifter circuit120may operate at both the VDDM domain and the VDDP domain, and is configured to change the voltage domain of the signal WLB from the VDDP domain to the VDDM domain.

In some embodiments, the WL level shifter circuit120is further configured to clamp the word line to a predetermined voltage level (e.g., zero volt) that correspond to the logic state of “0” during a power saving mode of the memory device100. The WL level shifter circuit120may receive a power saving mode enable signal PSM from outside of the memory device100through a pin PSM_PIN of the memory device100. The power saving mode enable signal PSM is configured to enable memory device100to the power saving mode. For example, when the signal PSM is in a first logic state (e.g., logic state of 0), the memory device100is not in the power saving mode; and when the signal PSM is in a second logic state (e.g., logic state of 1), the memory device100is in the power saving mode. In some embodiments, the WL level shifter circuit120is configured to clamp the signal WL at the word line of the memory array110to the predetermined voltage level (e.g., zero volt) when the signal PSM is in the second logic state.

In some embodiments, the memory device100is included in the memory system, and the power management of the memory device100is performed in a system level and is shared for all memory devices included in the memory system. During a system-level SD mode or a system-level DSLP mode of the memory system, the voltage levels of the word lines of the memory array110are unknown and are within a range of voltage levels corresponding to logic states of “1” and “0”, thus causing a large power leakage inside the memory device100. In some embodiments, the signal PSM is in the second logic state when the memory system is in the system-level SD mode or the system-level DSLP mode. As the WL level shifter circuit120may clamp the word lines of the memory device100to the predetermined voltage level (e.g., 0 volt) during the power saving mode, the power leakage is prevented and the power consumption of the memory device100is reduced.

In some embodiments, the IO circuit150is coupled to the memory array110and is configured to communicate with the memory array110in different memory operations. In some embodiments, the IO circuit150may include a read circuit (not shown) that is configured to read data from the memory array110, a write circuit (not shown) that is configured to write data to the memory array, and other suitable circuits that are required for operations of the memory device100.

In some embodiments, the control circuit140includes control logic circuits that are configured to control overall operations of the memory device100. The control circuit140may be coupled to the WL driver130and the IO circuit150to control the operations of the WL driver130and the IO circuit150. For example, the control circuit140may send control signals to the WL driver130to control the driving of the WL driver130. The control circuit140may send control signals to the IO circuit150to control operations of inputting or outputting data between the memory array110and other circuits.

FIG.2is a schematic diagram of the WL level shifter circuit120as shown inFIG.1in accordance with some embodiments. The WL level shifter circuit120may include a plurality of transistors P21, P22, N21, N22and N23, and logic circuits122and124. The transistor P21is cross-coupled to the transistor P22through nodes ND21and ND22. More particularly, the sources of the transistors P21and P22are coupled to each other to receive a voltage VDDM of the VDDM domain; and the drains of the transistors P21and P22are coupled to the nodes ND21and ND22, respectively. The gate of the transistor P21is coupled to the node ND22and the gate of the transistor P22is coupled to the node ND21.

In some embodiments, the drains of the transistors N21and N23are coupled to the node ND2, and the sources of the transistors N21and N23are coupled to a reference node (e.g., ground). The gates of the transistors N21and N23are configured to receive the signals WBL and PSM, respectively. As such, the switching operation of the transistor N21is controlled by the signal WBL, and the switching operation of the transistor N23is controlled by the signal PSM. During the power saving mode of the memory device (e.g., when the signal PSM is in the second logic state), the transistor N23is turned on to clamp the node ND21to zero volt. Accordingly, the transistor P22is turned on and the node ND22is clamped to the voltage level of the voltage VDDM. In other words, during the power saving mode of the memory device100, the signal WLB_VDDM is clamped to the voltage level of the voltage VDDM.

In some embodiments, the logic circuit122that operates in the VDDP domain is coupled to the pin PSM_PIN to receive the signal PSM and is coupled to a row decoder (not shown) to receive the signal WLB. The logic circuit122may perform a logic operation to the signals WLB and PSM to output a signal WLB_VDDP. In some embodiments, the logic circuit122is a NOR logic gate that is configured to perform a NOR operation to the signals WLB and the PSM to generate the signal WLB_VDDP. The signal WLB_VDDP is provided to the gate of the transistor N22to control switching operations of the transistor N22. During the power saving mode of the memory device, the signal PSM is in the second logic state of “1”, thus the signal WLB_VDDP has the first logic state of “0” and the transistor N22is turned off. In this way, the node ND22is securely clamped to the voltage level of the voltage VDDM.

In some embodiments, the logic circuit124that operates in the VDDM domain has an input terminal coupled to the node ND22and an output terminal coupled to the word line. The logic circuit124may perform a logic operation to the signal WLB_VDDM at the node ND22to generate the signal WL at the output of the logic circuit124. In some embodiments, the logic circuit124is an inverter or a NOT logic gate that is configured to invert the logic state of the signal WLB_VDDM to generate the signal WL. During the power saving mode of the memory device, the signal WLB_VDDM at the node ND22is clamped to the level of the voltage VDDM. As such, the signal WL is clamped to the zero volt as the result of the inverting operation performed by the inverter124. In this way, the WL level shifter circuit120may clamp the word line to zero volt during the power saving mode. As the word line is clamped to the zero volts during the power saving mode, the large power dissipation on the logic circuit124is reduced and the leakage current caused by the non-zero voltage level in the word line is prevented.

FIG.3is a schematic diagram of a memory system30that includes a memory block310and power management circuits320and330in accordance with some embodiments. The memory block310may include a plurality of memory devices M1through Mn, where n is a positive integer. Each of the memory devices M1through Mn may be same as or different from the memory100shown inFIG.1. In some embodiments, the power management circuit320is coupled to the memory devices M1through Mn and is configured to control the power supply in the VDDP domain for the memory devices M1through Mn. In some embodiments, the power management circuit330is coupled to the memory devices M1through Mn and is configured to control the power supply in the VDDM domain for the memory devices M1through Mn.

In some embodiments, the power management circuit320includes a logic circuit322and a plurality of transistors P21through P2n, in which the gates of the transistors P21through P2nare coupled to an output OUT1of the logic circuit322. The transistors P21through P2nare respectively coupled between the memory devices M1through Mn and an external node that receives a voltage VDDP_EXT. The voltage VDDP_EXT is in the VDDP domain and may be referred to as an external voltage of the memory devices M1through Mn. The transistors P21through P2nare configured to control the supply of the voltage VDDP_EXT to the memory devices M1through Mn based on the output OUT1of the logic circuit322. For example, when the output OUT1of the logic circuit322is in the logic state of “0”, the transistors P21through P2nare configured to conduct the external node connecting to the voltage VDD_EXT to the memory devices M1through Mn. When the output OUT1of the logic circuit322is in the logic state of “1”, the transistors P21through P2nare configured to insulate the external node connecting to the voltage VDD_EXT from the memory devices M1through Mn.

The logic circuit322may receive a shutdown signal SD and a deep-sleep signal DSLP, and perform a logic operation to the received inputs to generate the output OUT1. In some embodiments, the logic circuit322is an OR logic gate that is configured to perform an OR operation to the received shutdown signal SD and the deep-sleep signal DSLP to generate the output OUT1. In some embodiments, when the shutdown signal SD and the deep-sleep signal DSLP indicate that at least one of the shutdown mode and the deep-sleep mode is enabled, the output OUT1of logic circuit322is configured to insulate the external voltage VDDP_EXT from the memory devices M1through Mn. When the shutdown mode and the deep-sleep mode are not enabled, the transistors P21through P2nare controlled to conduct the memory devices M1through Mn to the voltage VDDP_EXT.

In some embodiments, the power management circuit330includes level shifters LS31and LS32, a logic circuit326, and circuits338_1through338_n. The level shifters LS31and LS31receive the shutdown signal SD and the deep-sleep signal DSLP, respectively, and are configured to perform level shifting operations to generate signals SD_LS and DSLP_LS, respectively. The level shifters LS31and LS31operate at the VDDM domain, and the signals SD_LS and DSLP_LS are in the VDDM domain. The logic circuit336is coupled to the level shifters LS31and LS32to receive the signals SD_LS and DSLP_LS, and is configured to perform a logic operation to generate the signal SLP_LS. In some embodiments, the logic circuit336is an OR logic gate that is configured to perform the OR operation on the signals SD_LS and DSLP_LS to generate the signal SLP_LS.

In some embodiments, each of the circuits338_1through338_nincludes a plurality of transistors P21through P34, and is configured to control the supply of the voltage VDDM_EXT to the memory devices M1through Mn. For example, the circuit338_1includes transistors P21through P34, in which the gate of the transistor P34is controlled by the signal SLP_LS and the gate of the transistor P33is controlled by the signal SD_LS. The transistors P31and P32are coupled between the transistor P33and the memory device M1and are configured as diodes.

In some embodiments, when the memory system30is in the shutdown mode, the shutdown signal SD is in the logic state of “1” and the deep-sleep signal DSLP is in the logic state of “0”. As a result, the signals SD_LS and SLP_LS are in the logic state of “1” and the transistors P33and P34are turned off in the shutdown mode. Accordingly, the voltage VDDM_EXT is not supplied to the memory devices M1through Mn during the shutdown mode. When the memory system30is in the deep-sleep mode, the shutdown signal SD is in the logic state of “0” and the deep-sleep signal DSLP is in the logic state of “1”. As the deep-sleep signal DSLP is in the logic state of “1”, the signal SLP_LS is in the logic state of “1” and the transistor P34is turned off during the deep-sleep mode. As the shutdown signal SD is in the logic state of “0”, the transistor P33is turned on and the voltage VDDM_EXT is supplied to the memory devices M1through Mn through the diodes P31and P32. In this way, the data stored in the memory devices M1through Mn are retained during the deep-sleep mode.

FIG.4is a schematic diagram of a memory device400that operates at multiple voltage domains (e.g., a VDDM domain and a VDDP domain) in accordance with some embodiments. The memory device400may include a memory array410, a WL level shifter circuit420, a WL driver430, a control logic440, an IO circuit450, power management circuits460and470, logic circuits480and490, and level shifters LS41and LS42. The memory array410, the WL driver430and the control circuit440of the memory device400are similar to the memory array110, the WL driver130and the control circuit140of the memory device100inFIG.1, thus the detailed descriptions about these components are omitted hereafter.

In some embodiments, the WL level shifter circuit420operates at both the VDDM domain and the VDDP domain and is coupled between the WL driver430and the memory array410. The WL level shifter circuit420is configured to change the voltage domain of the signal WLB from the VDDP domain to the VDDM domain to generate the signal WL. In addition, the WL level shifter circuit420is further configured to clamp the signal WL on the word line of the memory array410to zero volt during power saving modes of the memory device400. In some embodiments, the memory device400is equipped with power management modes that may include a shutdown mode, a deep-sleep mode and an ultra-deep sleep mode, in which the data stored in the memory array410is not retained in the shutdown mode and the data stored in the memory array410is retained in the deep-sleep mode and the ultra-deep-sleep mode. The shutdown mode, the deep-sleep mode and the ultra-deep-sleep mode are enabled by the shutdown signal SD, the deep-sleep signal DSLP and an ultra-deep-sleep signal UDSLP, respectively. In some embodiments, the ultra-deep-sleep signal UDSLP is in the VDDM domain, and the shutdown signal SD and the deep-sleep signal DSLP are in the VDDP domain.

In some embodiments, the shutdown signal SD and the deep-sleep signal DSLP are inputted to the level shifters LS41and LS42, respectively. The level shifters LS41and LS42are configured to shift the levels of the shutdown signal SD and the deep-sleep signal DSLP from the VDDP domain to the VDDM domain to generate the signals SD1and DSLP1, respectively. The logic circuit480receives the signals SD1, DSLP1and UDSLP, and is configured to perform a logic operation on the signals SD1, DSLP1and UDSLP to generate the signal SLP1. In some embodiments, the logic circuit480is an OR logic gate that is configured to perform an OR logic operation on the signals SD1, DSLP1and UDSLP to generate the signal SLP1. The level shifter LS41, LS42and the logic circuit480may operate in the VDDM domain.

In some embodiments, the logic circuit490is configured to perform a logic operation on the signals SD, DSLP and UDSLP to generate the signal SLP. The logic circuit490may be an OR logic gate that may perform the OR logic operation on the signals SD, DSLP and UDSLP to generate the signal SLP. In some embodiments, the logic circuit490operates at VDDM domain when the memory device400is in the ultra-deep-sleep mode, and operates at the VDDP domain when the memory device400is not in the ultra-deep sleep mode. The supply of the voltages VDDM and VDDP in the VDDM domain and the VDDP domain is controlled by the power management circuit470.

In some embodiments, the power management circuit470includes an inverter471and transistors P71and P72, in which the gate of the transistor P71is coupled to an input of the inverter471and the gate of the transistor P72is coupled to an output of the inverter471. The input of the inverter471may receive the ultra-deep-sleep signal UDSLP and the output of the inverter471is the signal UDSLPB, where the logic state of the signal UDSLPB is opposite to the logic state of the ultra-deep-sleep signal UDSLP. Particularly, when the ultra-deep-sleep signal UDSLP is at the logic state of “1”, the signal UDSLPB is at the logic state of “0”, and vice versa. In some embodiments, when the ultra-deep-sleep signal UDSLP is at the logic state of “1”, the transistor P72is turned on and the transistor P71is turned off. Accordingly, the voltage VDDM is supplied to the logic circuit490. When the ultra-deep-sleep signal UDSLP is at the logic state of “0”, the transistor P72is turned off, the transistor P71is turned on, and the voltage VDDP is supplied to the logic circuit490. In this way, during the ultra-deep-sleep mode, the supply of the voltage VDDP to the memory device400is not necessary. Thus, the supply of the voltage VDDP to the memory device400may be cut off, and more power is saved during the ultra-deep-sleep mode.

In some embodiments, the memory device400may further includes a power switch MPL, where a control terminal of the power switch MPL is coupled to the output of the logic circuit490. In other words, the power switch MPL is controlled by the signal SLP that is generated by the logic circuit490. The power switch MPL may has a first terminal coupled to the voltage VDDP and a second terminal coupled to a bus which may connect to subsequent circuits such as the WL level shifter circuit420, the WL driver430, the control circuit440and the IO circuit450. The power switch MPL is configured to output the voltage VDDPI to the bus based on the control of the signal SLP. During the shutdown mode or the deep-sleep mode, if the voltage VDDPI is floated, there is a considerable leakage flowing in the subsequent circuits such as the WL level shifter circuit420, the WL driver430, the control circuit440and the IO circuit450. In some embodiments, during the ultra-deep-sleep mode, the power switch MPL is turned off and the voltage VDDPI is clamped to the zero volt. As the voltage VDDPI is clamped to zero volt during the ultra-deep-sleep mode, the leakage flowing in the subsequent circuits is reduced.

In some embodiments, during the shutdown mode or the deep-sleep mode, the logic circuit490is supplied with the voltage VDDP and is configured to output the signal SLP having the logic state of “1”. Accordingly, the power switch MPL is turned off and the voltage VDDPI that is outputted by the power switch MPL is clamped to the zero volt. As the voltage VDDPI is clamped to zero volt during the shutdown mode and the deep-sleep mode, the leakage flowing in the subsequent circuits is reduced. In some embodiments, during a non-power saving mode (or a normal operation mode), the signal SLP is in the logic state of “0”, and the power switch MPL is turned on to supply the voltage VDDP to the WL level shifter circuit420, the WL driver430, the control circuit440and the IO circuit450.

In some embodiments, the power management circuit460includes a plurality of transistors P61through P64, in which the gate of the transistor P61receive the signal SLP1from the logic circuit480, and the gate of the transistor P62receives the signal SD1from the level shifter LS41. The transistors P63and P64functions as diodes, and are coupled between the transistor P62and the memory array410. In some embodiments, when the memory device400is in the shutdown mode, the signal SD is in the logic state of “1” and the signals DSLP and UDSLP are in the logic state of “0”. Accordingly, the signals SD1and SLP1are in the logic state of “1” and the transistors P61and P62are turned off, thus insulating the memory array410from the voltage VDDM. When the memory device400is in the deep-sleep mode or in the ultra-deep-sleep mode, the signal SLP1is in the logic state of “1” and the signal SD1is in the logic state of “0”. Accordingly, the transistor P62is turned on and the voltage VDDM is supplied to the memory array410through the transistors P62, P63and P64. The voltage VDDM is turned to the voltage VDDMI as the voltage drops on the transistors P62through P64. As the voltage VDDMI is supplied to the memory array410during the deep-sleep mode and the ultra-deep-sleep mode, the data stored in the memory array410is retained during the deep-sleep mode and the ultra-deep-sleep mode.

FIG.5illustrate a schematic diagram of the WL level shifter circuit420of the memory device400shown inFIG.4in accordance with some embodiments. The WL level shifter circuit420may include a plurality of transistors P41, P42, N41, N42and N43, and logic circuits422and424. The transistors P41, P42, N41, N42, N43and nodes ND41and ND42are similar to the transistors P21, P22, N21, N22, N23and nodes ND21and ND22inFIG.2, thus the detailed descriptions of these components are omitted hereafter.

A difference between the WL level shifter circuit120and the WL level shifter circuit420is that the logic circuit422of the WL level shifter circuit420may receive the signal WLB and SLP, in which the signal SLP is generated by the logic circuit490inFIG.4. The logic circuit422may operate in the VDDP domain and is configured to perform a logic operation (e.g., NOR operation) to the signals WLB and SLP to generate the signal WLB_VDDP. The signal WLB_VDDP is provided to the gate of the transistor N42. Another difference between the WL level shifter circuit120and the WL level shifter circuit420is that the WL level shifter circuit420further includes the transistor P43that is coupled between the logic circuit424and the voltage VDDM, where the gate of the transistor P43is configured to receive the signal SLP1.

In some embodiments, when the memory device400operates in the shutdown mode or the deep-sleep mode, the signal SLP that is in the VDDP domain, and when the memory device400operates in the ultra-deep-sleep mode, the signal SLP that is in the VDDM domain. In addition, when the memory device400operates in the shutdown mode, the deep-sleep mode or the ultra-deep-sleep mode, the signal SLP is in the logic state of “1” and the transistor N43is turned on to clamp the node N41to zero volt. Accordingly, the transistor P42is turned on to clamp the node ND42to the level of the voltage VDDM. In addition, as the signal SLP is in the logic state of “1”, the signal WLB_VDDP that is generated by the logic circuit422is in the logic state of “0”. Accordingly, the transistor N42is turned off and the node ND42is securely clamped to the level of the voltage VDDM. In some embodiments, the logic circuit424is an inverter that is configured to invert the logic state of the signal WLB_VDDM at the node ND42to generate the signal WL that is clamped to zero volt. In this way, the word line of the memory array410is clamped to zero volt during the shutdown mode, the deep-sleep mode and the ultra-deep-sleep mode. As such, the large power dissipation on the logic circuit124is reduced and the leakage current caused by the non-zero voltage level in the word line is prevented.

FIG.6is a flowchart diagram illustrating a power management method of compensating a mismatch in a circuit in accordance with some embodiments. In step S610, it determines whether a memory device operates in a power saving mode according to a power saving mode enable signal. In step S620, in response to determining that the memory device operates in the power saving mode, a word line of a memory array is clamped to a predetermined voltage level that corresponds to a first logic state during the power saving mode. In some embodiments, the predetermined voltage level is zero volt. As the word line of the memory device is clamped to zero volt during the power saving mode, the power dissipation and leakage power are reduced in the memory device.

In accordance with some embodiments, a word line level shifter circuit of the memory device is configured to clamp a word line voltage of a memory array to zero volt during a power saving mode of the memory device. As such, the power dissipation of the word line level shifter circuit and the power leakage of the memory device during the power saving mode is prevented. Accordingly, power consumption of the memory device in the power saving mode is reduced. In some embodiments, a power management circuit are included in the memory device for providing a first voltage in the VDDM domain during an ultra-deep-sleep mode and for providing a second voltage in the VDDP domain during the other power saving mode (e.g., shutdown mode and deep-sleep mode). In this way, the supply of the external VDDP during the ultra-deep-sleep mode is not necessary and may be insulated from the memory device. Furthermore, during the ultra-deep-sleep mode, a power switch of the memory device is turned off, thereby preventing the leaking current to the subsequent circuits that are coupled to the power switch. Accordingly, more power is saved in the ultra-deep-sleep mode of the memory device.

In accordance with some embodiments, a memory device that is operable at a first voltage domain and a second voltage domain includes a memory array, a power saving mode pin and a word line level shifter circuit. The memory array operates at the first voltage domain. The power saving mode pin is configured to receive a power saving mode enable signal that is at the second voltage domain. The power saving mode enable signal is configured to enable a power saving mode of the memory device. The word line level shifter circuit is coupled to the memory array and the power saving mode pin, and is configured to clamp a word line of the memory array to a predetermined voltage level that corresponds to a first logic state during the power saving mode of the memory device.

In accordance with some embodiments, a memory device that is operable at a first voltage domain and a second voltage domain includes a memory array, a first logic circuit and a word line level shifter circuit. The memory array is configured to operate at the first voltage domain. The first logic circuit is configured to operate at the first voltage domain when the memory device is in a first power saving mode and to operate at the second voltage domain when the memory device is not in the first power saving mode. The word line level shifter circuit is coupled to the memory array, configured to clamp a word line of the memory array to a predetermined voltage level that corresponds to a first logic state during the first power saving mode of the memory device. The predetermined voltage level may be zero volt.

In accordance with some embodiments, a power management method for a memory device operable at a first voltage domain and a second voltage domain is introduced. The power management method includes steps of determining whether the memory device operates in a power saving mode according to a power saving mode enable signal; and in response to determining that the memory device operates in the power saving mode, clamping a word line of a memory array to a predetermined voltage level that corresponds to a first logic state during the power saving mode.