Level shifter for display device

A semiconductor device having a level shifter, a differential amplifier circuit, and the like, where power consumption is reduced by reducing an unnecessary through current and distortion of an output waveform can be suppressed. A gate terminal of the first transistor is a first input terminal and a gate terminal of a second transistor is a second input terminal. The gate terminal of the first transistor is connected to a source terminal of the second transistor. The gate terminal of the second transistor is connected to a source terminal of the first transistor.

TECHNICAL FIELD

The present invention relates to an art of a semiconductor device having an amplification function. More specifically, the invention relates to a semiconductor device having a circuit typified by a differential amplifier circuit, a sense amplifier, a level shifter, and the like. Further, the invention relates to a display device having these. In addition, the invention relates to an electronic device having the display device in a display portion.

BACKGROUND ART

In recent years, an integrated circuit (IC), which is widely used for a portable phone, a portable terminal, and the like and which has several hundreds of thousands to several millions of transistors and resistors formed over a silicon substrate having a size of about 5 mm square, has been playing an important role for downsizing and improving reliability of a device and for the mass production of the device.

In the case of designing a circuit used for an integrated circuit (IC) and the like, an amplifier circuit having a function to amplify a voltage or a current of a signal with small amplitude is designed. An amplifier circuit is used widely as an essential circuit for eliminating a distortion so that a circuit can operate stably.

Here, description is made on a differential amplifier circuit as an example of an amplifier circuit. A differential amplifier circuit is often used for a level shifter and an operational amplifier. Here,FIG. 6shows a configuration example of a conventional level shifter and description is made on the configuration and operation thereof (see the conventional art of Patent Document 1: Japanese Patent Laid-Open No. 6-216753).

It is to be noted in this specification that each power source potential is referred to as VDD# and VSS# (# refers to a number). Here, VDD1, VDD2, VSS1, VSS2, and VSS3are used and their levels are set to satisfy VSS3<VSS2<VSS1<VDD1<VDD2.

First, description is made on a configuration of a level shifter shown inFIG. 6(A). The level shifter shown inFIG. 6(A)shifts a high potential side while fixing a low potential side and outputs a signal with amplitude of a difference between a voltage level VSS1and a voltage level VDD2relatively to an input signal with amplitude of a difference between a voltage level VSS1and a voltage level VDD1. This level shifter has the following configuration. A source region of a p-channel transistor601and a source region of a p-channel transistor602are both connected to a high potential power source (a power source potential VDD2). A gate electrode of the p-channel transistor601and a gate electrode of the p-channel transistor602are connected to each other and to a drain region of the p-channel transistor602. A drain region of the p-channel transistor601is connected to a drain region of an n-channel transistor603. A source region of the n-channel transistor603and a source region of an n-channel transistor are both connected to a low potential power source (a power source potential VSS1). Further, a first input signal in1(a voltage thereof is expressed as Vin1) is inputted to a gate electrode of the n-channel transistor603and a second input signal in2(a voltage thereof is expressed as Vin2) is inputted to a gate electrode of the n-channel transistor604. It is to be noted that the second input signal in2is an inverted signal of the first input signal in1. The drain region of the p-channel transistor602is connected to a drain region of the n-channel transistor604, and an output signal out (a voltage thereof is expressed as Vout) is obtained from this node.

Next, description is made on a basic operation of the level shifter shown inFIG. 6(A). When a High signal is inputted as the first input signal in1, the n-channel transistor603becomes conductive and a drain potential thereof becomes VSS1. On the other hand, as the gate electrode and the drain region of the p-channel transistor602are connected to each other, the p-channel transistor602operates in a saturation region. Accordingly, a potential which is obtained by dividing a voltage between VDD2and VDD1by resistance of the n-channel transistor604and the p-channel transistor602is inputted to the gate electrode of the p-channel transistor601. This potential is expressed as V601. When the first input signal in1is a High signal, the second input signal is a Low signal; therefore, the n-channel transistor604becomes non-conductive. Accordingly, the potential V601inputted to the gate electrode of the p-channel transistor601becomes higher in accordance with the power source potential VDD2. Therefore, the p-channel transistor601becomes non-conductive and a potential of the output signal out becomes VSS1.

When a Low signal is inputted as the first input signal in1, the n-channel transistor603becomes non-conductive. On the other hand, the second input signal becomes a High signal; therefore, the n-channel transistor604becomes conductive. Accordingly, the potential V601inputted to the gate electrode of the p-channel transistor601becomes lower in accordance with the power source potential VSS1. Therefore, the p-channel transistor601becomes conductive and a potential of the output signal out becomes VDD2.

In this manner, the input signal with amplitude of a difference between the voltage level VSS1and the voltage level VDD1is converted into an output signal with amplitude of a difference between the voltage level VSS1and the voltage level VDD2.

Next, description is made on a configuration of a level shifter shown inFIG. 6(B). The level shifter shown inFIG. 6(B)shifts a low potential side while fixing a high potential side and outputs a signal with amplitude of a difference between a voltage level VSS3and the voltage level VSS1relatively to an input signal with amplitude of a difference between the voltage level VSS2and the voltage level VSS1. This level shifter has the following configuration. A source region of an n-channel transistor607and a source region of an n-channel transistor608are both connected to a low potential power source (a power source potential VSS3). A gate electrode of the n-channel transistor607and a gate electrode of the n-channel transistor608are connected to each other and to a drain region of the n-channel transistor608and a drain region of a p-channel transistor606. A drain region of the n-channel transistor607is connected to a drain region of a p-channel transistor605. A source region of the p-channel transistor605and a source region of the p-channel transistor606are both connected to a low potential power source (a power source potential VSS1). Further, a first input signal in1is inputted to a gate electrode of the p-channel transistor605and a second input signal in2is inputted to a gate electrode of the p-channel transistor606. It is to be noted that the second input signal in2is an inverted signal of the first input signal in1. An output signal out is obtained from the drain region of the first p-channel transistor605.

Next, description is made on a basic operation of the level shifter shown inFIG. 6(B). When a Low signal is inputted as the first input signal in1, the p-channel transistor605becomes conductive and a drain potential of the p-channel transistor605becomes VSS1. On the other hand, as the gate electrode and the drain region of the n-channel transistor608are connected to each other, the n-channel transistor608operates in a saturation region. Accordingly, a potential obtained by dividing a voltage between VSS1and VSS3by resistance of the p-channel transistor606and the n-channel transistor608is inputted to the gate electrode of the n-channel transistor607. This potential is expressed as V607. When the first input signal in1is a Low signal, the second input signal becomes a High signal; therefore, the p-channel transistor606becomes non-conductive. Accordingly, the potential V607inputted to the gate electrode of the n-channel transistor607becomes lower in accordance with the power source potential VSS3. Therefore, the n-channel transistor607becomes non-conductive and a potential of the output signal out becomes VSS1.

When a High signal is inputted as the first input signal in1, the p-channel transistor605becomes non-conductive. On the other hand, the second input signal becomes a Low signal; therefore, the p-channel transistor606becomes conductive. Accordingly, the potential V607inputted to the gate electrode of the n-channel transistor607becomes higher in accordance with the power source potential VSS1. Therefore, the n-channel transistor607becomes conductive and a potential of the output signal out becomes VSS3.

In this manner, the input signal with amplitude of a difference between the voltage level VSS2and the voltage level VSS1is converted into an output signal with amplitude of a difference between the voltage level VSS3and the voltage level VSS1.

DISCLOSURE OF INVENTION

Problems to be Solved by the Invention

A problem of the level shifters shown inFIG. 6is described. It is to be noted that both of the level shifters shown inFIGS. 6(A) and 6(B)have a common problem; therefore, the level shifter shown inFIG. 6(A)only is taken as an example here.

When a High signal is inputted as the second input signal in2, the n-channel transistor604becomes conductive. Further, the p-channel transistor602always operates in a saturation region. As a result, a current flows between VDD2and VSS1through the p-channel transistor602and the n-channel transistor604. This state continues unless the n-channel transistor604becomes non-conductive. As a current keeps flowing, the level shifter consumes more power.

Here, description is made with reference toFIG. 7on the case where the second input signal in2changes from a High signal to a Low signal.FIG. 7(A)shows the potential Vin2of the second input signal in2with the ordinate and a time passage of the second input signal in2.FIG. 7(B)shows the potential Vin1of the first input signal in1with the ordinate and the time passage of the first input signal in1with abscissa. A gate-source voltage Vgs604of the n-channel transistor604is obtained by a following formula (1).
Vgs604=Vin2−VSS1  (1)

Here, the time passage of Vgs604is shown inFIG. 7(C). In particular, in the case where the second input signal in2changes from a High signal to a Low signal over a long time, Vin2eventually decreases from VDD1to VSS1. Therefore, it takes additional time until Vgs604becomes a level of a threshold voltage Vth604of the n-channel transistor604or lower. That is, it takes more time than required until the n-channel transistor604becomes non-conductive. Accordingly, an additional current flows between VDD2and VSS1through the p-channel transistor602and the n-channel transistor604. As a result, power consumption of the level shifter is increased. Further, due to the additional current, an output waveform is distorted.

Further, similarly in the case where the second input signal in2changes from a Low signal to a High signal and the case where the signal changes from the Low signal to the High signal over a long time, Vin2eventually increases from VSS1to VDD1. Therefore, it takes additional time until Vgs604which is as high as a threshold voltage Vth604of the n-channel transistor604or higher reaches VDD1. That is, it takes more time than required until the n-channel transistor604becomes conductive. Accordingly, an additional current flows between VDD2and VSS1through the p-channel transistor602and the n-channel transistor604.

Therefore, it is an object of the invention to provide a semiconductor device where no additional current flows even in the case where an input signal changes from a High signal to a Low signal or from a Low signal to a High signal over a long time as described above and where power consumption can be reduced and distortion of an output waveform can be suppressed.

Means for Solving the Problems

In view of solving the aforementioned problems, a semiconductor device as described below is suggested in the invention.

A semiconductor device of the invention includes a first transistor having a gate electrode to which a first signal is inputted and a first terminal to which a second signal is inputted, a second transistor having a gate electrode to which a second signal is inputted and a first terminal to which a first signal is inputted, a third transistor having a first terminal to which a predetermined potential is inputted and a second terminal connected to a second terminal of the first transistor, and a fourth transistor having a gate electrode connected to a gate electrode of the third transistor, a first terminal to which a predetermined potential is inputted, a second terminal connected to a second terminal of the second transistor, and the gate electrode and the second terminal of which are connected to each other.

A semiconductor device of the invention with another configuration includes a first transistor, a second transistor, a third transistor, and a fourth transistor. A gate electrode of the third transistor is connected to a gate electrode of the fourth transistor. A first terminal of the third transistor is connected to a first wire. A first terminal of the fourth transistor is connected to a second wire and a second terminal of the fourth transistor is connected to the gate electrode of the fourth transistor. A gate electrode of the first transistor is connected to a third wire, a first terminal of the first transistor is connected to a fourth wire, and a second terminal of the first transistor is connected to a second terminal of the third transistor. A gate electrode of the second transistor is connected to the fourth wire, a first terminal of the second transistor is connected to the third wire, and a second terminal of the second transistor is connected to the second terminal of the fourth transistor.

For example, a gate terminal of the first transistor is used as a first input terminal and a gate terminal of the second transistor is used as a second input terminal. The gate terminal of the first transistor is connected to the source terminal of the second transistor. Further, the gate terminal of the second transistor is connected to a source terminal of the first transistor.

In the aforementioned configuration, a semiconductor device with another configuration includes the third wire connected to the gate electrode of the third transistor through a first level shifter and the fourth wire is connected to the gate electrode of the fourth transistor through a second level shifter circuit.

In the aforementioned configuration, a semiconductor device with another configuration includes the third wire to which a first input signal is inputted and the fourth wire to which a second input signal is inputted.

In the aforementioned configuration, a semiconductor device with another configuration includes the first transistor and the second transistor which are the same first conductive type, and the third transistor and the fourth transistor which are the same second conductive type.

It is to be noted that it is difficult to distinguish between a source region and a drain region of a transistor due to a structure thereof. Further, potential levels may be interchanged depending on a circuit operation. Therefore, the source region and the drain region are not specified here and described as a first terminal and a second terminal. For example, in the case where the first terminal is a source region, the second terminal corresponds to a drain region. On the contrary, in the case where the first terminal is a drain region, the second terminal corresponds to a source region.

There are an n-channel type and a p-channel type as conductive types of a transistor, which are described as a first conductive type and a second conductive type in this specification unless conductivity thereof is especially specified. For example, in the case where a first conductive type transistor is an n-channel transistor, a second conductive type corresponds to a p-channel type. On the contrary, in the case where a first conductive type transistor is a p-channel transistor, a second conductive type corresponds to an n-channel type.

It is to be noted that a connection in the invention means an electrical connection. Therefore, in the configuration disclosed in the invention, another element (for example, a transistor, a diode, a resistor, a capacitor, a switch, and the like) which enables electrical connection may be provided in addition to a predetermined connection.

Effect of the Invention

According to a semiconductor device of the invention, a current can be reduced even when an input signal changes over a long time and additional power consumption can be reduced, and at the same time, distortion of an output waveform can be suppressed.

BEST MODE FOR CARRYING OUT THE INVENTION

First, description is made with reference toFIG. 1on a basic configuration of a semiconductor device of this embodiment mode.

FIG. 1is a circuit diagram of a semiconductor device of this embodiment mode. The semiconductor device of this embodiment mode has a following configuration. A source region of a p-channel transistor101is connected to a first wire105. A source region of a p-channel transistor102is connected to a second wire106. Gate electrodes of the p-channel transistor101and the p-channel transistor102are connected to each other and to a drain region of the p-channel transistor102. A drain region of the p-channel transistor101is connected to a drain region of the n-channel transistor103and an output signal out is obtained from this node. A source region of the n-channel transistor103is connected to a gate electrode of an n-channel transistor104. A source region of the n-channel transistor104is connected to a gate electrode of the n-channel transistor103. A first input signal in1(voltage Vin1) is inputted to the gate electrode of the n-channel transistor103and a second input signal in2(voltage Vin2) is inputted to the gate electrode of the n-channel transistor104.

Next, description is made on a basic operation of the semiconductor device of this embodiment mode. Here, description is made as an example on the case of using a semiconductor device of this embodiment mode as a level shifter. It is to be noted that each of the first and second input signals has amplitude of a difference between the voltage level VSS1and the voltage level VDD1. The first wire105and the second wire106are both applied a power source potential VDD2and an inverted signal of the first input signal is inputted as the second input signal. Here, the power source potentials are set to satisfy VSS1<VDD1<VDD2.

First, a signal with amplitude of a difference between the voltage level VSS1and the voltage level VDD1is inputted to the gate electrode of the n-channel transistor103as the first input signal in1. A signal with amplitude of a difference between the voltage level VSS1and the voltage level VDD1is inputted to the gate electrode of the n-channel transistor104as the second input signal. Here, the source region of the n-channel transistor103is connected to the gate electrode of the n-channel transistor104; therefore, a source potential of the n-channel transistor103becomes Vin2. Similarly, the source region of the n-channel transistor104is connected to the gate electrode of the n-channel transistor103; therefore, a source potential of the n-channel transistor104becomes Vin1.

When a High signal is inputted as the first input signal, the second input signal becomes a Low signal. Therefore, the source potential of the n-channel transistor103becomes VSS1and the n-channel transistor103becomes conductive. Then, a drain potential of the n-channel transistor103becomes VSS1. On the other hand, the gate electrode and the drain region of the p-channel transistor102are connected to each other; therefore, the p-channel transistor102operates in a saturation region. Accordingly, a potential obtained by dividing a voltage between VDD2and Vin1by resistance of the n-channel transistor104and the p-channel transistor102is inputted to the gate electrode of the p-channel transistor101. This potential is expressed as V101. When the first input signal in1is a High signal, the second input signal becomes a Low signal. Therefore, the source potential of the n-channel transistor104becomes VDD1and the n-channel transistor104becomes non-conductive. Accordingly, the potential V101inputted to the gate electrode of the p-channel transistor101becomes higher in accordance with the power source potential VDD2. Therefore, the p-channel transistor101becomes non-conductive and a potential of the output signal out becomes VSS1.

When a Low signal is inputted as the first input signal, the second input signal becomes a High signal. Therefore, the source potential of the n-channel transistor103becomes VDD1and the n-channel transistor becomes non-conductive. On the other hand, the source potential of the n-channel transistor104becomes VSS1and an n-channel transistor604becomes conductive. Accordingly, the potential V101inputted to the gate electrode of the p-channel transistor101becomes lower in accordance with the power source potential VSS1. Accordingly, the p-channel transistor101becomes conductive and a potential of the output signal out becomes VDD2.

FIG. 22shows output waveforms of the semiconductor device of this embodiment mode.FIGS. 22(A) to 22(C)show a time passage of the potential Vin1of the first input signal in, the potential Vin2of the second input signal in2, and the potential Vout of the output signal out respectively.

In this manner, the input signal with amplitude of a difference between the voltage level VSS1and the voltage level VDD1is converted into an output signal with amplitude of a difference between the voltage level VSS1and the voltage level VDD2.

Here, description is made with reference toFIG. 2on the case where the second input signal in2changes from a High signal to a Low signal.FIG. 2(A)shows the ordinate showing the potential of the second input signal in2and the abscissa showing a time passage of the second input signal in2.FIG. 2(B)shows the ordinate showing the potential of the first input signal in1and the abscissa showing a time passage of the first input signal in1. A gate-source voltage Vgs104of the n-channel transistor104can be obtained by the following formula (2).
Vgs104=Vin2−Vin1  (2)

Here, a time passage of Vgs104is shown inFIG. 2(C). In particular, in the case where the second input signal in2changes from a High signal to a Low signal over a long time, Vin1increases from VSS1to VDD1at the same time as Vin2decreases from VDD1to VSS1. Therefore, compared with the conventional level shifter, time required for Vgs104to be a level of a threshold voltage Vth104of the n-channel transistor104or lower can be reduced. That is, time required for the n-channel transistor104to be non-conductive can be reduced. Accordingly, a current flowing between VDD2and VSS1through the p-channel transistor102and the n-channel transistor104can be reduced. As a result, power consumption is reduced. Further, due to the reduction in current, distortion of an output waveform can be suppressed.

Further, similarly in the case where the second input signal in2changes from a Low signal to a High signal, Vin1decreases from VDD1to VSS1at the same time as Vin2increases from VSS1to VDD1. Therefore, time required for Vgs104which is as high as a threshold voltage Vth104of the n-channel transistor104or higher reaches VDD2can be reduced. That is, time required for the second n-channel transistor104to be conductive can be reduced. Accordingly, a current flowing between VDD2and VSS1through the p-channel transistor102and the n-channel transistor104can be reduced. As a result, power consumption is reduced. Further, due to the reduced current, distortion of an output waveform can be suppressed.

Here,FIG. 3shows a top plan view of the level shifter of this embodiment mode. Transistors (the p-channel transistor101, the p-channel transistor102, the n-channel transistor103, and the n-channel transistor104) shown inFIG. 3correspond to the transistors' numbers the p-channel transistor101, the p-channel transistor102, the n-channel transistor103, and the n-channel transistor104in the circuit diagram shown inFIG. 1respectively.

It is to be noted that an insulating film is provided between a wire metal and a gate metal, and between the gate metal and a semiconductor layer and that there is no short-circuit at overlapped portions thereof. They are connected to each other at a portion provided with a contact hole.

Here, as an example of a transistor used in this embodiment mode, a cross section of a CMOS transistor is shown inFIG. 4. Reference numeral401denotes an n-channel transistor and402denotes a p-channel transistor. Reference numeral403denotes a substrate. Reference numeral404denotes a base film. The base film is formed of an insulating film such as a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. Reference numeral405denotes a semiconductor layer. As a material of the semiconductor layer, silicon, a silicon-germanium alloy, and the like can be used. Reference numeral406denotes a gate insulating film which covers the semiconductor layer. An insulating film containing silicon is used for the gate insulating film. Reference numerals411and412denote a first conductive film and a second conductive film respectively. The first and second conductive films are formed to form gate electrodes using an element selected from Ta, W, Ti, Mo, Al, Cu, and the like, or an alloy material or a compound material containing the aforementioned element as a main component. Reference numeral407denotes an n-type impurity region. The n-type impurity region is formed in a self-aligned manner by first doping treatment to add an impurity element (typically, phosphorus or arsenic is used) which imparts n-type conductivity. Reference numeral408denotes a p-type impurity region. The p-type impurity region is formed in a self-aligned manner by second doping treatment to add an impurity element (typically, boron is used) which imparts p-type conductivity only to a semiconductor layer of the p-channel transistor. Reference numerals409and410denote a first interlayer insulating film and a second interlayer insulating film respectively. Reference numeral413denotes a source wire413which forms a contact with a source region of the semiconductor layer and414denotes a drain wire which forms a contact with a drain region thereof.

It is to be noted in the invention that a kind of a transistor applicable to the invention is not limited, and a transistor used for the invention may be a thin film transistor (TFT) using a non-single crystal semiconductor film represented by amorphous silicon or polycrystalline silicon, a MOS transistor formed by using a semiconductor substrate or an SOI substrate, a junction transistor, a bipolar transistor, a transistor using an organic semiconductor or a carbon nanotube, or the like. Furthermore, a substrate on which a transistor is mounted is not exclusively limited to a certain type. It may be a single crystalline substrate, an SOI substrate, a glass substrate, and the like.

It is preferable that the level shifter of this embodiment mode have transistors with few variations in characteristics due to its operating characteristics. Therefore, the transistors which form each circuit are preferably arranged close to each other. Also, when a manufacturing process of a transistor substrate includes laser irradiation or the like, variations in characteristics of the transistors due to uneven irradiation or the like can be reduced by closely arranging the transistors as shown inFIG. 3. In addition, since the aforementioned laser irradiation or the like is normally carried out in a form of linear irradiation, it is preferable to arrange each transistor in parallel with one another as the variations in characteristics of the transistors due to aforementioned uneven irradiation or the like can further be reduced.

It is to be noted thatFIG. 3shows an example of a top plan view of the level shifter described in this embodiment mode and the level shifter circuit described in this embodiment mode is not limited to the configuration shown inFIG. 3.

It is to be noted in this embodiment mode that an inverted signal of the first input signal is the second input signal; however, it is not limited to this. In the case of using it as a differential circuit, any signal may be used as long as the potentials Vin1and Vin2of the two input signals have a difference from each other. Further, a power source voltage is applied to the first wire105and the second wire106; however, the invention is not limited to this, and a signal from another circuit or a clock signal may be inputted thereto. Further, different potentials may be applied to the first wire105and the second wire106.

In this embodiment mode, description is made with reference toFIG. 5on the case where the polarity of the transistor is changed in Embodiment Mode 1.

FIG. 5shows a circuit diagram of a semiconductor device of this embodiment mode. The semiconductor device of this embodiment mode has the following configuration. A source region of an n-channel transistor503is connected to a first wire505. A source region of an n-channel transistor504is connected to a second wire506. Gate electrodes of the n-channel transistor503and the n-channel transistor504are connected to each other and to a drain region of the n-channel transistor504. A drain region of the n-channel transistor503is connected to a drain region of a p-channel transistor501and an output signal out is obtained from this node. A source region of the p-channel transistor501is connected to a gate electrode of a p-channel transistor502and a source region of the p-channel transistor502is connected to a gate electrode of the p-channel transistor501. A first input signal in1(voltage Vin1) is inputted to the gate electrode of the p-channel transistor501and a second input signal in2(voltage Vin2) is inputted to the gate electrode of the p-channel transistor502.

Next, description is made on a basic operation of the semiconductor device of this embodiment mode. Here, description is made as an example on the case of using the semiconductor device of this embodiment mode as a level shifter. It is to be noted that each of the first and second input signals has amplitude of a difference between a voltage level VSS1and a voltage level VSS2. The first wire505and the second wire506are both applied a power source potential VSS3. An inverted signal of the first input signal is inputted as the second input signal. Here, the power source potentials are set to satisfy VSS3<VSS2<VSS1.

First, a signal with amplitude of a difference between the voltage level VSS1and the voltage level VSS2is inputted as the first input signal in1to the gate electrode of the p-channel transistor501, and a signal with amplitude of a difference between the voltage level VSS1and the voltage level VSS2is inputted as the second input signal to the gate electrode of the p-channel transistor502. Here, as the source region of the p-channel transistor501is connected to the gate electrode of the p-channel transistor502, a source potential of the p-channel transistor501becomes Vin2. Similarly, as the source region of the p-channel transistor502is connected to the gate electrode of the p-channel transistor501, a source potential of the p-channel transistor502becomes Vin1.

When a High signal is inputted as the first input signal, the second input signal becomes a Low signal. Therefore, the source potential of the p-channel transistor501becomes VSS2and the p-channel transistor501becomes non-conductive. On the other hand, as the gate electrode and the drain region of the n-channel transistor504are connected, the n-channel transistor504operates in a saturation region. Accordingly, a potential obtained by dividing a voltage between Vin1and VSS3by resistance of the p-channel transistor502and the n-channel transistor504is inputted to the gate electrode of the n-channel transistor503. This potential is expressed as V503. When the first input signal in1is a High signal, the second input signal becomes a Low signal. Therefore, the source potential of the p-channel transistor502becomes VSS1and the p-channel transistor502becomes conductive. Accordingly, the potential V503inputted to the gate electrode of the n-channel transistor503becomes higher in accordance with the power source potential VSS1. Therefore, the n-channel transistor503becomes conductive and a potential of the output signal out becomes VSS3.

When a Low signal is inputted as the first input signal, the second input signal becomes a High signal. Therefore, the source potential of the p-channel transistor501becomes VSS1and the p-channel transistor501becomes conductive. Then, the drain potential of the p-channel transistor501becomes VSS1. On the other hand, the source potential of the p-channel transistor502becomes VSS2and the p-channel transistor502becomes non-conductive. Accordingly, the potential V503inputted to the gate electrode of the n-channel transistor503becomes lower in accordance with the power source potential VSS3. Therefore, the n-channel transistor503becomes non-conductive and a potential of the output signal out becomes VSS1.

FIG. 23shows output waveforms of the semiconductor device of this embodiment mode.FIGS. 23(A) to 23(C)show a time passage of the potential Vin1of the first input signal in1, the potential Vin2of the second input signal in2, and a potential Vout of the output signal out respectively.

In this manner, an input signal with amplitude of a difference between the voltage level VSS1and the voltage level VSS2is converted into an output signal with amplitude of a difference between the voltage level VSS1and the voltage level VSS3.

It is to be noted in this embodiment mode that an inverted signal of the first input signal is the second input signal; however, it is not limited to this. In the case of a differential circuit, any signal may be used as long as the potentials Vin1and Vin2of the two input signals have a difference from each other. Further, a power source voltage is applied to the first wire505and the second wire506; however, the invention is not limited to this, and a signal from another circuit or a clock signal may be inputted thereto. Further, different potentials may be applied to the first wire505and the second wire506.

In Embodiment Mode 1 (FIG. 1), when a threshold voltage of each of the n-channel transistors103and104is higher than voltage amplitude of each of the input signals in1and in2, the n-channel transistor103and the n-channel transistor104become non-conductive and do not operate normally in some cases. In view of this, in this embodiment mode, gate potentials applied to the n-channel transistor103and the n-channel transistor104are set high so that the n-channel transistor103and the n-channel transistor104can easily be conductive.

First, description is made with reference toFIG. 8on a basic configuration of the semiconductor device of this embodiment mode.

The semiconductor device of this embodiment mode is formed of a differential circuit portion807, a first level shifter circuit808, and a second level shifter circuit809. The differential circuit portion807has a following configuration. A source region of a p-channel transistor801is connected to a first wire805. A source region of a p-channel transistor802is connected to a second wire806. Gate electrodes of the p-channel transistor801and the p-channel transistor802are connected to each other and to a drain region of the p-channel transistor802. A drain region of the p-channel transistor801is connected to a drain region of an n-channel transistor803and an output signal out is obtained from this node. A first input signal in1(voltage Vin1) is inputted to a source region of an n-channel transistor804and a second input signal in2(voltage Vin2) is inputted to a source region of the n-channel transistor803. The first level shifter circuit808is connected to a gate electrode of the n-channel transistor803and the source region of the n-channel transistor804. The second level shifter circuit809is connected to a gate electrode of the n-channel transistor804and the source region of the n-channel transistor803.

Here, description is made with reference toFIG. 9on the case of using the semiconductor device of this embodiment mode as a level shifter.FIG. 9is a specific diagram of the first level shifter circuit808and the second level shifter circuit809. It is to be noted that each of the first and second input signals has amplitude of a difference between the voltage level VSS1and the voltage level VDD1, the first wire805and the second wire806are both applied a power source potential VDD2, and an inverted signal of the first input signal is inputted as the second input signal. Here, the power source potentials are set to satisfy VSS1<VDD1<VDD2.

The level shifter of this embodiment mode is formed of a differential circuit portion909, a first level shifter circuit910, and a second level shifter circuit911. The differential circuit portion909is formed of a p-channel transistor901, a p-channel transistor902, an n-channel transistor903, and an n-channel transistor904. The first level shifter circuit910is formed of a current source905and an n-channel transistor906. A gate electrode of the n-channel transistor906and a gate electrode of the n-channel transistor903included in the differential circuit portion909are connected to each other and to a drain region of the n-channel transistor906and the current source905. The second level shifter circuit911is formed of a current source907and an n-channel transistor908. A gate electrode of the n-channel transistor908and a gate electrode of the n-channel transistor904included in the differential circuit portion909are connected to each other and to a drain region of the n-channel transistor908and the current source907. As for an input signal, the first input signal in1(voltage Vin1) is inputted to source regions of the n-channel transistor904included in the differential circuit portion909and of the n-channel transistor906included in the first level shifter circuit910. The second input signal in2(voltage Vin2) is inputted to source regions of the n-channel transistor903included in the differential circuit portion909and of the n-channel transistor908included in the second level shifter circuit911.

Next, description is made on a basic operation of the level shifter of this embodiment mode.

First, a signal with amplitude of a difference between the voltage level VSS1and the voltage level VDD1is inputted as the first input signal in1to source regions of the n-channel transistor904and the n-channel transistor906. A signal with amplitude of a difference between the voltage level VSS1and the voltage level VDD1is inputted as the second input signal in2to source regions of the n-channel transistor903and the n-channel transistor908. Accordingly, each of source potentials of the n-channel transistor904and the n-channel transistor906becomes Vin1and each of source potentials of the n-channel transistor903and the n-channel transistor908becomes Vin2.

Next, description is made on operations of the first level shifter circuit910and the second level shifter circuit911. Each of the n-channel transistor906and the n-channel transistor908has a gate electrode and a drain region connected to each other; therefore, the n-channel transistor906and the n-channel transistor908both operate in a saturation region. Accordingly, a potential obtained by resistance division of a voltage between Vin1and VDD2is inputted to the gate electrode of the n-channel transistor903. This potential is expressed as V903. Similarly, a potential obtained by resistance division of a voltage between Vin2and VDD2is inputted to the gate electrode of the n-channel transistor904. This potential is expressed as V904. It is to be noted that the level shifter circuit910and the level shifter circuit911are set so that at least one of the potentials V903and V904inputted to the gate electrodes of the n-channel transistor903and the n-channel transistor904becomes higher than a threshold voltage of each of the n-channel transistor903and the n-channel transistor904.

When the first input signal in1is a High signal, the second input signal becomes a Low signal. Therefore, the input potentials V903and V904to the differential circuit portion909are set so as to satisfy V903>V904. Further, a source potential of the n-channel transistor903becomes VSS1and a source potential of the n-channel transistor904becomes VDD1. Accordingly, a gate-source voltage of the n-channel transistor903becomes high and a gate-source voltage of the n-channel transistor904becomes low. Therefore, a potential of an output signal out falls to be VSS1due to the differential circuit portion909. It is to be noted that a basic operation of the differential circuit portion909is the same as that of the level shifter (FIG. 1) described in Embodiment Mode 1; therefore, detailed description thereof is omitted here.

When the first input signal in1is a Low signal, the second input signal becomes a High signal. Therefore, the input potentials V903and V904to the differential circuit portion909are set to satisfy V903<V904. Further, the source potential of the n-channel transistor903becomes VDD1and the source potential of the n-channel transistor904becomes VSS1. Accordingly, the gate-source voltage of the n-channel transistor903becomes low and the gate-source voltage of the n-channel transistor904becomes high. Therefore, a potential of an output signal out rises to be VDD2due to the differential circuit portion909.

In this manner, an input signal with amplitude of a difference between the voltage level VSS1and the voltage level VDD1is converted into an output signal with amplitude of a difference between the voltage level VSS1and the voltage level VDD2.

The level shifter of this embodiment mode can realize reduction in power consumption as well as suppressing distortion of an output waveform by reducing the current when converting voltage amplitude. Further, by using the first level shifter circuit910and the second level shifter circuit911, the gate potentials V903and V904applied to the n-channel transistor903and the n-channel transistor904can be set higher than the threshold voltage of each of the n-channel transistor903and the n-channel transistor904. Therefore, an operation is possible even when the threshold voltage of each of the n-channel transistor903and the n-channel transistor904is higher than voltage amplitude of the input signal.

It is to be noted that the level shifter circuit shown inFIG. 9is a circuit using a current source; however, the level shifter circuit of this embodiment mode is not limited to this. Examples of a circuit which can be used as a level shifter circuit are shown inFIG. 10.FIG. 10(A)is a circuit in which a resistor1001and a diode1002are connected in series.FIG. 10(B)is a circuit in which a diode1003and a resistor1004are connected in series, which is an opposite connection to the circuit shown inFIG. 10(A).FIG. 10(C)is a circuit in which a diode1005and a diode1006are connected in series. It is to be noted that the circuits shown inFIG. 10are examples of the level shifter circuit and the invention is not limited to these.

In this embodiment mode, an inverted signal of the first input signal is the second input signal; however, it is not limited to this. In the case of a differential circuit, any signal may be used as long as the potentials Vin1and Vin2of the two input signals have a difference from each other. Further, a power source voltage is applied to the first wire805and the second wire806; however, the invention is not limited to this, and a signal from another circuit or a clock signal may be inputted thereto. Further, different potentials may be applied to the first wire805and the second wire806.

In this embodiment mode, description is made with reference toFIG. 11on the case where the polarity of the transistor is changed in Embodiment Mode 3. In Embodiment Mode 2 (FIG. 5), when the threshold voltage of each of the p-channel transistor501and the p-channel transistor502is lower than voltage amplitude of each of the input signals in1and in2, the p-channel transistor501and the p-channel transistor502become non-conductive and do not operate normally in some cases. In view of this, in this embodiment mode, gate potentials applied to the p-channel transistor501and the p-channel transistor502are set lower so that the p-channel transistor501and the p-channel transistor502can easily be conductive.

The semiconductor device of this embodiment mode is formed of a differential circuit portion1107, a first level shifter circuit1108, and a second level shifter circuit1109. The differential circuit portion1107has a following configuration. A source region of an n-channel transistor1103is connected to a first wire1105. A source region of an n-channel transistor1104is connected to a second wire1106. Gate electrodes of the n-channel transistor1103and the n-channel transistor1104are connected to each other and to a drain region of the n-channel transistor1104. A drain region of the n-channel transistor1103is connected to a drain region of a p-channel transistor1101and an output signal out is obtained from this node. A first input signal in1(voltage Vin1) is inputted to a source region of the p-channel transistor1102and a second input signal in2(voltage Vin2) is inputted to a source region of the p-channel transistor1101. The first level shifter circuit1108is connected to a gate electrode of the p-channel transistor1101and the source region of the p-channel transistor1102. The second level shifter circuit1109is connected to a gate electrode of the p-channel transistor1102and the source region of the p-channel transistor1101.

Here, description is made with reference toFIG. 12on the case of using the semiconductor device of this embodiment mode as a level shifter.FIG. 12is a specific diagram of the first level shifter circuit1108and the second level shifter circuit1109. It is to be noted that each of the first and second input signals has amplitude of a difference between the voltage level VSS1and the voltage level VSS2. The first wire1105and the second wire1106are both applied a power source potential VSS3. An inverted signal of the first input signal is inputted as the second input signal. Here, the power source potentials are set so as to satisfy VSS3<VSS2<VSS1.

The level shifter of this embodiment mode is formed of a differential circuit portion1209, a first level shifter circuit1210, and a second level shifter circuit1211. The differential circuit portion1209is formed of a p-channel transistor1201, a p-channel transistor1202, an n-channel transistor1203, and an n-channel transistor1204. The first level shifter circuit910is formed of the current source905and the n-channel transistor906. The first level shifter circuit1210is formed of a p-channel transistor1205and a current source1206. A gate electrode of the p-channel transistor1205and a gate electrode of the p-channel transistor1201included in the differential circuit portion1209are connected to each other and to a drain region of the p-channel transistor1205and the current source1206. The second level shifter circuit1211is formed of a p-channel transistor1207and a current source1208. A gate electrode of the p-channel transistor1207and a gate electrode of the p-channel transistor1202included in the differential circuit portion1209are connected to each other and to a drain region of the p-channel transistor1207and the current source1208. As for an input signal, the first input signal in1(voltage Vin1) is inputted to source regions of the p-channel transistor1202included in the differential circuit portion1209and the p-channel transistor1205included in the first level shifter circuit1210. The second input signal in2(voltage Vin2) is inputted to source regions of the p-channel transistor1201included in the differential circuit portion1209and the p-channel transistor1207included in the second level shifter circuit1211.

Next, description is made on a basic operation of the level shifter of this embodiment mode.

First, a signal with amplitude of a difference between the voltage level VSS1and the voltage level VSS2is inputted as the first input signal in1to source regions of the p-channel transistor1202and the p-channel transistor1205. A signal with amplitude of a difference between the voltage level VSS1and the voltage level VSS2is inputted as the second input signal to the source regions of the p-channel transistor1201and the p-channel transistor1207. Accordingly, each of source potentials of the p-channel transistor1202and the p-channel transistor1205becomes Vin1and each of source potentials of the p-channel transistor1201and the p-channel transistor1207becomes Vin2.

Next, description is made on operations of the first level shifter circuit1210and the second level shifter circuit1211. Each of the p-channel transistor1205and the p-channel transistor1207has a gate electrode and a drain electrode connected to each other; therefore, the p-channel transistor1205and the p-channel transistor1207both operate in a saturation region. Accordingly, a potential obtained by resistance division of a voltage between VSS3and Vin2is inputted to the gate electrode of the p-channel transistor1201. This potential is expressed as V1201. Similarly, a potential obtained by resistance division of a voltage between VSS3and Vin1is inputted to the gate electrode of the p-channel transistor1202. This potential is expressed as V1202.

When the first input signal in1is a High signal, the second input signal becomes a Low signal. Therefore, the input potentials V1201and V1202to the differential circuit portion1209are set so as to satisfy V1201>V1202. Further, the source potential of the p-channel transistor1201becomes VSS2and the source potential of the p-channel transistor1202becomes VSS1; therefore, a gate-source voltage of the p-channel transistor1201becomes low while a gate-source voltage of the p-channel transistor1202becomes high. Accordingly, a potential of the output signal out falls to VSS3due to the differential circuit portion1209.

It is to be noted that a basic operation of the differential circuit portion1209is the same as that of the level shifter described in Embodiment Mode 2 (FIG. 5); therefore, detailed description thereof is omitted here.

When the first input signal in1is a Low signal, the second input signal becomes a High signal. Therefore, the input potentials V1201and V1202to the differential circuit portion1209are set so as to satisfy V1201<V1202. Further, the source potential of the p-channel transistor1201becomes VSS1and the source potential of the p-channel transistor1202becomes VSS2; therefore, a gate-source voltage of the p-channel transistor1201becomes high while a gate-source voltage of the p-channel transistor1202becomes low. Accordingly, a potential of the output signal out rises to VSS1due to the differential circuit portion1209.

In this manner, an input signal with amplitude of a difference between the voltage level VSS1and the voltage level VSS2is converted into an output signal with amplitude of a difference between the voltage level VSS1and the voltage level VSS3.

The level shifter of this embodiment mode can realize reduction in power consumption as well as suppressing distortion of an output wave by reducing the current when converting voltage amplitude. Further, by using the first level shifter circuit1210and the second level shifter circuit1211, the gate potentials V1201and V1202applied to the p-channel transistor1201and the p-channel transistor1202can be set lower than the threshold voltage of each of the p-channel transistor1201and the p-channel transistor1202. Therefore, an operation is possible even when the threshold voltage of each of the p-channel transistor1201and the p-channel transistor1202is lower than voltage amplitude of an input signal.

It is to be noted that the level shifter circuit shown inFIG. 12uses a current source; however, the level shifter circuit of this embodiment mode is not limited to this.FIG. 10shows examples of circuits which can be used as a level shifter circuit. It is to be noted that the circuits shown inFIG. 10are examples of a level shifter and the invention is not limited to this.

Further, in this embodiment mode, an inverted signal of the first input signal is the second input signal; however, it is not limited to this. In the case of using as a differential circuit, any signal may be used as long as the potentials Vin1and Vin2of the two input signals have a difference. Further, a power source voltage is applied to the first wire1105and the second wire1106; however, the invention is not limited to this. A signal from another circuit or a clock signal may be inputted thereto. Further, different potentials may be applied to the first wire1105and the second wire1106.

The semiconductor device described in the aforementioned embodiment modes is used as a level shifter which fixes one of a low potential side or a high potential side of an input signal while shifting the other. In this embodiment mode, description is made with reference toFIG. 13on the case where the semiconductor device is used as a level shifter which shifts both a low potential side and a high potential side of an input signal.

By using the semiconductor devices described in Embodiment Mode 1 and Embodiment Mode 2 in combination, a level shifter which shifts both a low potential side and a high potential side of an input signal can be formed.FIG. 13shows schematic diagrams showing this embodiment mode.FIG. 13(A)shows the case where first and second input signals in1and in2are inputted to a high potential side level shifter1301first to shift a high potential side of the input signal, and then a low potential side level shifter1302is used to shift a low potential side of the input signal. On the contrary toFIG. 13(A),FIG. 13(B)shows the case where the first and second input signals in1and in2are inputted to the low potential side level shifter1302first to shift the low potential side of the input signal, and then the high potential side level shifter1301is used to shift the high potential side of the input signal. In this embodiment mode, the semiconductor device described in Embodiment Mode 1 can be used as the high potential side level shifter1301and the semiconductor device described in Embodiment Mode 2 can be used as the low potential side level shifter1302.

Here, description is made with reference toFIGS. 14(A) and 14(B)on an example where the semiconductor device described in Embodiment Mode 1 is used as the high potential side level shifter1301and the semiconductor device described in Embodiment Mode 2 is used as the low potential side level shifter1302.FIG. 14(A)shows an example of a level shifter which shifts a low potential side after shifting a high potential side of an input signal whileFIG. 14(B)shows an example of a level shifter which shifts a high potential side after shifting a low potential side of an input signal. It is to be noted in this embodiment mode that each of the first and second input signals has amplitude of a difference between the voltage level VSS1and the voltage level VDD1, a power source potential of the high potential side is VDD2, a power source potential of the low potential side is VSS3, and an inverted signal of the first input signal is inputted as the second input signal. Here, the power source potentials are set so as to satisfy VSS3<VSS1<VDD1<VDD2.

First, description is made on the level shifter shown inFIG. 14(A), which shifts the low potential side after shifting the high potential side of the input signal.

The level shifter shown inFIG. 14(A)has a following configuration. A high potential side level shifter1409has a similar configuration to that of the semiconductor device (FIG. 1) described in Embodiment Mode 1 and a low potential side level shifter1410has a similar configuration to that of the semiconductor device (FIG. 5) described in Embodiment Mode 2. The high potential side level shifter1409has a p-channel transistor1401, a p-channel transistor1402, an n-channel transistor1403, and an n-channel transistor1404. The low potential side level shifter1410has a p-channel transistor1405, a p-channel transistor1406, an n-channel transistor1407, an n-channel transistor1408, and an inverter1411.

In the high potential side level shifter1409, a first input signal in1is inputted to a gate electrode of the n-channel transistor1403and a source region of the n-channel transistor1404. A second input signal in2is inputted to a gate electrode of the n-channel transistor1404and a source region of the n-channel transistor1403. A drain region of the p-channel transistor1402is connected to a drain region of the n-channel transistor1404and an output signal out1is obtained from this node.

In the low potential side level shifter1410, the output signal out1of the high potential side level shifter1409is inputted to a gate electrode of the p-channel transistor1405and a source region of the p-channel transistor1406. An inverted signal of the output signal out1of the high potential side level shifter1409is inputted to a gate electrode of the p-channel transistor1406and a source region of the p-channel transistor1405. A drain region of the p-channel transistor1406is connected to a drain region of the n-channel transistor1408and an output signal out is obtained from this node.

Next, description is made on a basic operation of the level shifter shown inFIG. 14(A).

First, description is made on the high potential side level shifter1409. As the first input signal in1, a signal with amplitude of a difference between the voltage level VSS1and the voltage level VDD1is inputted to the gate electrode of the n-channel transistor1403and the source region of the n-channel transistor1404. As the second input signal, a signal with amplitude of a difference between the voltage level VSS1and the voltage level VDD1is inputted to the gate electrode of the n-channel transistor1404and the source region of the n-channel transistor1403. A basic operation of the high potential side level shifter1409is the same as that of the semiconductor device shown inFIG. 1; therefore, detailed description thereof is omitted here. At last, a signal with amplitude of a difference between the voltage level VSS1and the voltage level VDD2is obtained as the output signal out1.

Next, description is made on the low potential side level shifter1410. The output signal out1of the high potential side level shifter1409with amplitude of a difference between the voltage level VSS1and the voltage level VDD2is inputted to the gate electrode of the p-channel transistor1405and the source region of the p-channel transistor1406. The output signal out1of the high potential side level shifter1409with amplitude of a difference between the voltage level VSS1and the voltage level VDD2is inputted to the gate electrode of the p-channel transistor1406and the source region of the p-channel transistor1405through the inverter1411. A basic operation of the low potential side level shifter1410is the same as the level shifter shown inFIG. 5; therefore, detailed description thereof is omitted here. At last, a signal with amplitude of a difference between the voltage level VSS3and the voltage level VDD2is obtained as the output signal out.

Next, description is made on the level shifter shown inFIG. 14(B)which shifts the high potential side after shifting the low potential side of the input signal.

The level shifter shown inFIG. 14(B)has a following configuration. A high potential side level shifter1420has a similar configuration to the semiconductor device (FIG. 1) described in Embodiment Mode 1 and a low potential side level shifter1421has a similar configuration to the semiconductor device (FIG. 5) described in Embodiment Mode 2. The high potential side level shifter1420includes a p-channel transistor1412, a p-channel transistor1413, an n-channel transistor1414, an n-channel transistor1415, and an inverter1422. The low potential side level shifter1421includes a p-channel transistor1416, a p-channel transistor1417, an n-channel transistor1418, and an n-channel transistor1419.

In the low potential side level shifter1421, the first input signal in1is inputted to a gate electrode of the p-channel transistor1416and a source region of the p-channel transistor1417. The second input signal in2is inputted to a gate electrode of the p-channel transistor1417and a source region of the p-channel transistor1416. A drain region of the n-channel transistor1418is connected to a drain region of the p-channel transistor1416and an output signal out1is obtained from this node.

In the high potential side level shifter1420, the output signal out1of the low potential side level shifter1421is inputted to a gate electrode of the n-channel transistor1415and a source region of the n-channel transistor1414. An inverted signal of the output signal out1of the low potential side level shifter1421is inputted to a gate electrode of the n-channel transistor1414and a source region of the n-channel transistor1415. A drain region of the p-channel transistor1412is connected to a drain region of the n-channel transistor1414and an output signal out is obtained from this node.

Next, description is made on a basic operation of the level shifter shown inFIG. 14(B).

First, description is made on the low potential side level shifter1421. As the first input signal in1, a signal with amplitude of a difference between the voltage level VSS1and the voltage level VDD1is inputted to the gate electrode of the p-channel transistor1416and the source region of the p-channel transistor1417. As the second input signal, a signal with amplitude of a difference between the voltage level VSS1and the voltage level VDD1is inputted to the gate electrode of the p-channel transistor1417and the source region of the p-channel transistor1416. A basic operation of the low potential side level shifter1421is as described above; therefore, detailed description thereof is omitted here. At last, a signal with amplitude of a difference between the voltage level VSS3and the voltage level VDD1is obtained as an output signal out1.

Next, description is made on the high potential side level shifter1420. The output signal out1of the low potential side level shifter1421with amplitude of a difference between the voltage level VSS3and the voltage level VDD1is inputted to the gate electrode of the n-channel transistor1415and the source region of the n-channel transistor1414. The output signal out1of the low potential side level shifter1421with amplitude of a difference between the voltage level VSS3and the voltage level VDD1is inputted to the gate electrode of the n-channel transistor1414and the source region of the n-channel transistor1415through the inverter1422. A basic operation of the high potential side level shifter1420is as described above; therefore, detailed description thereof is omitted here. At last, a signal with amplitude of a difference between the voltage level VSS3and the voltage level VDD2is obtained as the output signal out.

In this manner, by using the level shifter of this embodiment mode, a signal with amplitude of a difference between the voltage level VSS3and the voltage level VDD1can be converted into a signal with amplitude of a difference between the voltage level VSS3and the voltage level VDD2.

It is to be noted in this embodiment mode that the semiconductor device described in Embodiment Mode 1 is used as the high potential side level shifter and the semiconductor device described in Embodiment Mode 2 is used as the low potential side level shifter; however, circuits used as the high potential side and low potential side level shifters are not limited to these. The semiconductor device described in other embodiment modes may be used as well. Further, a conventional level shifter circuit and the semiconductor device described in other embodiment modes may be used in combination.

In this embodiment mode, in a display device having a signal line driver circuit, a scan line driver circuit, or a display element, description is made on an example of mounting the semiconductor device of the invention to the signal line driver circuit or the scan line driver circuit.

FIG. 15(A)shows a display device which has over a substrate1501a pixel portion1502in which a plurality of pixels are arranged in matrix, a signal line driver circuit1503, a first scan line driver circuit1504, and a second scan line driver circuit1505in the periphery of the pixel potion1502. The display device shown inFIG. 15(A)has the signal line driver circuit1503and the two scan line driver circuits (the first scan line driver circuit1504and the second scan line driver circuit1505); however, this embodiment mode is not limited to this and the number of the signal line driver circuit and the scan line driver circuit can be appropriately determined in accordance with a pixel configuration. Further, signals are externally inputted through an FPC1506to the signal line driver circuit1503and the two scan line driver circuits (the first scan line driver circuit1504and the second scan line driver circuit1505). However, this embodiment mode is not limited to this and a signal may be externally inputted by using an IC and the like to a semiconductor device besides the pixel portion.

First, description is made with reference toFIG. 15(B)on the signal line driver circuit1503.FIG. 15(B)shows a configuration of the signal line driver circuit1503. The signal line driver circuit1503includes a shift register1507, a first latch circuit1508, a second latch circuit1509, and a level shifter circuit1510.

Next, description is briefly made on an operation of the signal line driver circuit1503. The shift register1507is formed by using a plurality of columns of flip-flop circuits (FF) and the like and a clock signal (S-CLK), a start pulse (S-SP), and a clock inverting signal (S-CLKB) are inputted thereto. Sampling pulses are sequentially outputted in accordance with the timing of these signals.

The sampling pulses outputted from the shift register1507are inputted to the first latch circuit1508. A video signal (Video Data) is inputted to the first latch circuit1508, thereby video signals are held in each column in accordance with the timing at which the sampling pulses are inputted.

After the video signals are held up to the last column in the first latch circuit1508, a latch pulse (Latch Pulse) is inputted to the second latch circuit1509during a horizontal flyback period. The video signals held in the first latch circuit1508are transferred to the second latch circuit1509all at once. After that, the video signals held in the second latch circuit1509are inputted to the level shifter circuit1510one row at a time, where a voltage thereof is amplified and sent to a signal line.

Next, description is made with reference toFIG. 15(C)on the first scan line driver circuit1504and the second scan line driver circuit1505.FIG. 15(C)shows configurations of the first scan line driver circuit1504and the second scan line driver circuit1505. Each of the first scan line driver circuit1504and the second scan line driver circuit1505includes a shift register1511, a level shifter circuit1512, and a buffer1513.

Next, description is briefly made on operations of the first scan line driver circuit1504and the second scan line driver circuit1505. The shift register1511is formed by using a plurality of columns of flip-flop circuits (FF) and the like and a clock signal (G-CLK), a start pulse (G-SP), and a clock inverting signal (G-CLKB) are inputted thereto. Sampling pulses are sequentially outputted in accordance with timing of these signals. After that, the sampling pulses amplified by the level shifter circuit1512and the buffer1513are inputted to the scan line, which are selected row by row.

Here, description is made with reference toFIG. 16on the case where the semiconductor device of the invention is mounted as the level shifter circuit1510of the signal line driver circuit1503.FIG. 16(A)is a circuit diagram of one column of the signal line driver circuit1503of this embodiment mode. A level shifter circuit shown inFIG. 16(A)is the level shifter circuit described in Embodiment Mode 1. A level shifter circuit1604includes a p-channel transistor1605, a p-channel transistor1606, an n-channel transistor1607, an n-channel transistor1608, and an inverter1609. A video signal outputted from a second latch circuit1603is inputted to a gate electrode of the n-channel transistor1607of the level shifter circuit1604through the inverter1609and a video signal outputted from a second latch circuit1603is inputted to a gate electrode of the n-channel transistor1608, thereby an output signal out is obtained from a drain region of the n-channel transistor1607. An operation of the level shifter circuit1604is as described above; therefore, description thereof is omitted here. At last, voltage amplitude of the video signal outputted from the second latch circuit1603can be amplified.

FIG. 16(B)shows an example of a timing chart of the signal line driver circuit of this embodiment mode.FIG. 16(B)shows an example where each of a clock signal (S-CLK), a start pulse (S-SP), a clock inverting signal (S-CLKB), a video signal (Video Data), and a latch pulse (Latch Pulse) has amplitude of a difference between the voltage level VSS1and the voltage level VDD1. A signal inputted to the level shifter circuit1604through the shift register1601, the first latch circuit1602, and the second latch circuit1603is a signal which is High for a short period. On the other hand, a current flows when a High signal is inputted to a gate electrode of the n-channel transistor1608in the level shifter circuit1604used in this embodiment mode. Therefore, by connecting the inverter1609to a gate electrode of the n-channel transistor1607, time during which a High signal is inputted to the gate electrode of the n-channel transistor1608can be drastically reduced, which leads to realize reduction in current and power consumption.

Next, description is made with reference toFIG. 17on the case where the semiconductor device of the invention is mounted as a level shifter circuit1510and a level shifter circuit1512of the first scan line driver circuit1504and the second scan line driver circuit1505respectively.FIG. 17(A)is a circuit diagram of one row of the first scan line driver circuit1504and the second scan line driver circuit1505of this embodiment mode. A level shifter circuit shown inFIG. 17(A)is the level shifter circuit described in Embodiment Mode 1. A level shifter circuit1702includes a p-channel transistor1704, a p-channel transistor1705, an n-channel transistor1706, an n-channel transistor1707, and an inverter1708. Sampling pulses outputted from the shift register1701are inputted to a gate electrode of the n-channel transistor1706of the level shifter circuit1702through the inverter1708and the sampling pulses outputted from the shift register1701are inputted to a gate electrode of the n-channel transistor1707, thereby an output signal out is obtained from a drain region of the n-channel transistor1706and inputted to the buffer1703. An operation of the level shifter circuit1702is as described above; therefore, description thereof is omitted here. At last, voltage amplitude of the sampling pulses outputted from the shift register1701can be amplified.

FIG. 17(B)shows an example of a timing chart of the scan line driver circuit of this embodiment mode.FIG. 17(B)shows an example where each of a clock signal (G-CLK), a start pulse (G-SP), and a clock inverting signal (G-CLKB) has amplitude of a difference between the voltage level VSS1and the voltage level VDD1. A signal inputted to the level shifter circuit1702through the shift register1701is a signal which is High for a short period. On the other hand, a current flows when a High signal is inputted to a gate electrode of the n-channel transistor1707in the level shifter circuit1702used in this embodiment mode. Therefore, by connecting the inverter1708to a gate electrode of the n-channel transistor1706, time during which a High signal is inputted to the gate electrode of the n-channel transistor1707can be drastically reduced, which leads to realize reduction in current and power consumption.

Further, by mounting the level shifter circuit of the invention, time during which a current flows to the level shifter when converting voltage amplitude can be reduced, which leads to suppress distortion of an output wave.

It is to be noted in this embodiment mode that the level shifter circuit of the invention is used as the level shifter circuit1510and the level shifter circuit1512of the signal line driver circuit and the scan line driver circuit as an example; however, the level shifter circuit of the invention may be used for other parts of the signal line driver circuit and the scan line driver circuit.

For example, the level shifter circuit of the invention may be used as an amplifier circuit of a clock signal inputted to the signal line driver circuit and the scan line driver circuit.FIGS. 20 and 21show these examples.

FIG. 20shows an example where the level shifter circuit of the invention is used as an amplifier circuit of a clock signal inputted to the signal line driver circuit. A first level shifter circuit2001includes a p-channel transistor2002, a p-channel transistor2003, an n-channel transistor2004, an n-channel transistor2005, and an inverter2006. A clock signal (Input S-CLK) with amplitude of a difference between the voltage level VSS1and the voltage level VDD3is inputted to the first level shifter circuit2001, thereby a clock signal (S-CLK) with amplitude of a difference between the voltage level VSS1and the voltage level VDD1is generated. Here, the power source voltages are set so as to satisfy VSS1<VDD3<VDD1.

FIG. 21shows an example where the level shifter circuit of the invention is used as an amplifier circuit of a clock signal inputted to the scan line driver circuit. A first level shifter circuit2101includes a p-channel transistor2102, a p-channel transistor2103, an n-channel transistor2104, an n-channel transistor2105, and an inverter2106. A clock signal (Input G-CLK) with amplitude of a difference between the voltage level VSS1and the voltage level VDD3is inputted to the first level shifter circuit2101, thereby a clock signal (G-CLK) with amplitude of a difference between the voltage level VSS1and the voltage level VDD1is generated. Here, the power source voltages are set so as to satisfy VSS1<VDD3<VDD1.

In this manner, by using the level shifter circuit of the invention as an amplifier circuit of a clock signal inputted to the signal line driver circuit and the scan line driver circuit, voltage amplitude of the clock signal (Input S-CLK and Input G-CLK) can be reduced. Therefore, load on a wire which sends the clock signal can be reduced, and at the same time, power consumption can be reduced as well. Further, time during which a current flows to the level shifter when converting voltage amplitude can be reduced; therefore, distortion of an output wave can be suppressed.

It is to be noted that the semiconductor device (FIG. 1) described in Embodiment Mode 1 is used in this embodiment mode; however, a circuit used as the level shifter circuit is not limited to this. The semiconductor device described in other embodiment modes may be used as well.

Further, the display element used for the semiconductor device described in this embodiment mode is not limited. The invention can be applied to a liquid crystal display device using liquid crystals, an EL display device which emits light by electroluminescence (Electro Luminescence: EL) using inorganic or organic material, a display device using a Digital Micromirror Device (DMD) element, a field emission display (Field Emission Display: FED), a surface-conduction electron-emitter display (Surface-conduction Electron-emitter Display: SED), electronic paper, and the like.

In this embodiment mode, description is made with reference toFIG. 18on an example where the semiconductor device of the invention is applied to an operational amplifier.

FIG. 18(A)shows a circuit symbol of an operational amplifier. An operational amplifier has a function to output an amplified output potential Vout relatively to a first input potential Vin1and a second input potential Vin2. There are various circuit configurations for an operational amplifier although it is mainly formed of a differential circuit and an amplifier circuit. In this embodiment mode, description is made on an example where the semiconductor device of the invention is employed as a differential circuit and used in combination with a common source circuit to be used as an amplifier circuit. It is to be noted that the power source potentials VSS1and VDD2are used, which satisfy VSS1<VDD2.

FIG. 18(B)is a circuit diagram of an operational amplifier of this embodiment mode. The operational amplifier of this embodiment mode has a following configuration.

The operational amplifier of this embodiment mode is formed of a differential circuit1807and an amplifier circuit1808. The semiconductor device (FIG. 1) described in Embodiment Mode 1 is applied as the differential circuit1807. The differential circuit1807is formed of a p-channel transistor1801, a p-channel transistor1802, an n-channel transistor1803, and an n-channel transistor1804. The first input potential Vin1is applied to a gate electrode of the n-channel transistor1804and a source region of the n-channel transistor1803. The second input potential Vin2is applied to a gate electrode of the n-channel transistor1803and a source region of the n-channel transistor1804. A drain region of the n-channel transistor1804is connected to a drain region of the p-channel transistor1802and an output potential Vout1is obtained from this node.

An amplifier circuit1808is a common source circuit formed of an n-channel transistor1805and an n-channel transistor1806. A drain region of the n-channel transistor1805is connected to a high potential power source (a power source potential VDD2). A gate electrode and the drain region of the n-channel transistor1805are connected to each other. A source region of the n-channel transistor1806is connected to a low potential power source (power source potential VSS1). The output potential Vout1from the differential circuit1807is applied to a gate electrode of the n-channel transistor1806. A drain region of the n-channel transistor1806is connected to a source region of the n-channel transistor1805and an output potential Vout is obtained from this node.

Next, description is made on a basic operation of the operational amplifier of this embodiment mode.

In the case where there is a difference between the first input potential Vin1and the second input potential Vin2in the differential circuit1807, a current (I1803-I1804) which corresponds to a difference between the current I1803flowing through the n-channel transistor1803and the current I1804flowing through the n-channel transistor1804flows through an output terminal. Therefore, a potential due to the current of the difference is obtained as the output potential Vout1. In the case where the first input potential Vin1and the second input potential Vin2are set so as to satisfy Vin1>Vin2, the current I1803flowing through the n-channel transistor1803decreases while the current I1804flowing through the n-channel transistor1804increases. Accordingly, the output potential Vout1falls.

Next, in the amplifier circuit1808, as the gate electrode and the drain region of the n-channel transistor1805are connected to each other, the n-channel transistor1805operates in a saturation region. Therefore, an output potential Vout is a potential obtained by resistance division of a voltage between VDD2and VSS1. In the case where the first input potential Vin1and the second input potential Vin2are set so as to satisfy Vin1>Vin2, the output potential Vout1of the differential circuit1807falls, and thus a gate-source voltage of the n-channel transistor1806becomes low. Accordingly, the output potential Vout rises in accordance with the power source potential VDD2. It is to be noted that the larger the potential difference between the first input potential Vin1and the second input potential Vin2is, the closer to the power source potential VDD2the output potential Vout becomes.

On the other hand, when the first input potential Vin1and the second input potential Vin2are set so as to satisfy Vin1<Vin2, the current I1803flowing through the n-channel transistor1803increases and the current I1804flowing through the n-channel transistor1804decreases in the differential circuit1807. Therefore, the output potential Vout1rises. Accordingly, a gate-source voltage of the n-channel transistor1806becomes high in the amplifier circuit1808. Accordingly, the output potential Vout becomes low in accordance with the power source potential VSS1. It is to be noted that the larger the potential difference between the first input potential Vin1and the second input potential Vin2is, the closer to the power source potential VSS1the output potential Vout becomes.

In this manner, the output potential Vout which is amplified between VSS1and VDD2is obtained relatively to the potential difference between the input potentials Vin1and Vin2.

It is to be noted in this embodiment mode that the semiconductor device described in Embodiment Mode 1 is used as the differential circuit; however, a circuit used as the differential circuit is not limited to this. The semiconductor device described in other embodiment modes may be used as well. Further, a common source circuit is used as the amplifier circuit; however, a circuit used as the amplifier circuit is not limited to this.

Electronic devices using the semiconductor device of the invention include a video camera, a digital camera, a goggle type display (head mounted display), a navigation system, an audio reproducing device (car audio set, audio component set, and the like), a notebook type personal computer, a game machine, a portable information terminal (mobile computer, portable phone, portable game machine, electronic book, and the like), an image reproducing device provided with a memory medium (specifically a device which reproduces a memory medium such as a Digital Versatile Disc (DVD) and has a display capable of displaying the reproduced image), and the like. Specific examples of these electronic devices are shown inFIG. 19.

FIG. 19(A)illustrates a television including a housing1901, a support base1902, a display portion1903, speaker portions1904, a video input terminal1905, and the like. The invention can be used for a semiconductor device which forms the display portion1903. By using the semiconductor device of the invention, a television with reduced power consumption can be provided.

FIG. 19(B)illustrates a digital still camera including a main body1906, a display portion1907, an image receiving portion1908, operating keys1909, an external connecting port1910, a shutter1911, and the like. The invention can be used for a semiconductor device which forms the display portion1907. By using the semiconductor device of the invention, a digital still camera with reduced power consumption can be provided.

FIG. 19(C)illustrates a notebook type personal computer including a main body1912, a housing1913, a display portion1914, a keyboard1915, an external connecting port1916, a pointing mouse1917, and the like. The invention can be used for a semiconductor device which forms the display portion1914. By using the semiconductor device of the invention, a notebook type personal computer with reduced power consumption can be provided.

FIG. 19(D)illustrates a mobile computer including a main body1918, a display portion1919, a switch1920, operating keys1921, an infrared port1922, and the like. The invention can be used for a semiconductor device which forms the display portion1919. By using the semiconductor device of the invention, a mobile computer with reduced power consumption can be provided.

FIG. 19(E)illustrates a portable image reproducing device (specifically a DVD reproducing device) provided with a memory medium device, including a main body1923, a housing1924, a display portion A1925, a display portion B1926, a memory medium (DVD and the like) reading portion1927, an operating key1928, a speaker portion1929, and the like. The display portion A1925mainly displays image data while the display portion B mainly displays text data. The invention can be used for a semiconductor device which forms the display portions A and B1925and1926. It is to be noted that the image reproducing device provided with a recording medium includes a home game machine and the like. By using the semiconductor device of the invention, an image reproducing device with reduced power consumption can be provided.

FIG. 19(F)illustrates a goggle type display (head mounted display) including a main body1930, a display portion1931, an arm portion1932, and the like. The invention can be used for a semiconductor device which forms the display portion1931. By using the semiconductor device of the invention, a goggle type display (head mounted display) with reduced power consumption can be provided.

FIG. 19(G)illustrates a video camera including a main body1933, a display portion1934, a housing1935, an external connecting port1936, a remote control receiving portion1937, an image receiving portion1938, a battery1939, an audio input portion1940, operating keys1941, and the like. The invention can be used for a semiconductor device which forms the display portion1934. By using the semiconductor device of the invention, a video camera with reduced power consumption can be provided.

FIG. 19(H)illustrates a portable phone including a main body1942, a housing1943, a display portion1944, an audio input portion1945, an audio output portion1946, an operating key1947, an external connecting port1948, an antenna1949, and the like. The invention can be used for a semiconductor device which forms the display portion1944. By using the semiconductor device of the invention, a portable phone with reduced power consumption can be provided.

As described above, the application range of the invention is quite wide and the invention can be applied to electronic devices of various fields.