Daisy-chained synchronous ethernet clock recovery

A PHY chip for a synchronous Ethernet system includes N network input/output (I/O) ports, a first external recovered clock input, a first recovered clock output, and a first clock multiplexer having a plurality of data inputs, a select input, and an output coupled to the first recovered clock output, at least one of the data inputs coupled to a first recovered clock from a respective one of the N network I/O ports, a first additional data input coupled to the first external recovered clock input.

BACKGROUND

The present invention relates to synchronous Ethernet systems. More particularly, the present invention relates to synchronous Ethernet clock recovery.

A system supporting Synchronous Ethernet should be capable of using two clocks recovered from any two Ethernet ports as its primary and secondary timing references. This is commonly implemented by having each Ethernet physical layer device (PHY device, or PHY chip) provide two or more clock outputs, all of which are connected to the Synchronous Ethernet timing element (e.g. a digital phase locked loop (DPLL) device).

A large number of clocks must be connected to this timing element if the system has a large number of Ethernet ports. All the recovered clocks occupy printed circuit board (PCB) routing space and either require a DPLL with many clock inputs or there must be a separate input clock multiplexer circuit placed in front of the DPLL. This increases the PCB cost and the component cost.

FIG. 1shows an exemplary 48-port Ethernet system10implemented using twelve four-port PHY chips (two of which are represented by reference numerals12and14). The four network I/O ports of the PHY chip #112are connected to interfaces to the network by printed circuit board traces that are indicated at reference numeral16and the four network I/O ports of the PHY chip #1214are connected to interfaces to the network by printed circuit board traces that are indicated at reference numeral18. Four ports are connected to system interfaces such as Ethernet MAC interfaces to the system from the PHY chip #112and the PHY chip #1214on printed circuit board traces that are shown collectively at reference numerals20and22, respectively.

The two recovered clocks from each PHY chip are provided to a multi-input digital phase locked loop (DPLL)24inside of the synchronous Ethernet timing element26. The synchronous Ethernet timing element26is separate from the PHY chips. As shown inFIG. 1, the recovered clock A from the PHY chip #112is connected to the synchronous Ethernet timing element26by a printed circuit board trace shown at reference numeral28and the recovered clock B from the PHY chip #112is connected to the synchronous Ethernet timing element26by a printed circuit board trace shown at reference numeral30. Similarly, the recovered clock A from the PHY chip #1214is connected to the synchronous Ethernet timing element26by a printed circuit board trace shown at reference numeral32and the recovered clock B from the PHY chip #1214is connected to the synchronous Ethernet timing element26by a printed circuit board trace shown at reference numeral34. The DPLL24is synchronized to a stable frequency source such as an oven-controlled crystal oscillator (OCXO) shown at reference numeral36. The 48-port Ethernet system10implementation shown inFIG. 1requires a 24-input DPLL to accommodate the recovered clocks A and B from each of the twelve PHY chips. The synchronous Ethernet timing element26provides a synchronous Ethernet reference clock output to the system as shown at reference numeral38.

Existing multiport Ethernet PHY chip solutions typically provide an internal clock multiplexer that selects between the recovered clocks of the internal PHYs and provide two or more recovered clock outputs. Referring now toFIG. 2, an illustrative PHY chip clock multiplexer arrangement50is shown.

A clock multiplexer A52has a data input54supplying the Port 1 recovered A clock, a data input56supplying the Port 2 recovered A clock, a data input58supplying the Port 3 recovered A clock, and a data input60supplying the Port 4 recovered A clock. The data output62of the clock multiplexer A52supplies the recovered clock output A as selected by the value presented on the select inputs64of the multiplexer A52.

A clock multiplexer B66has a data input68supplying the Port 1 recovered B clock, a data input70supplying the Port 2 recovered B clock, a data input72supplying the Port 3 recovered B clock, and a data input74supplying the Port 4 recovered B clock. The data output76of the clock multiplexer B66supplies the recovered clock output B as selected by the value presented on the select inputs78of the clock multiplexer B66.

As indicated previously, known existing solutions such as VSC8574 and VSC8584 available from Microchip Technology, Inc., of Chandler, Ariz., provide clock multiplexers supporting two recovered clock outputs (A and B). Other existing solutions such as Microchip's VSC8488 provide a single recovered clock output per port. These solutions have the drawbacks noted above. One such drawback is illustrated inFIG. 1at reference numeral80where the PCB traces providing recovered clock A line28and the recovered clock B line30that are provided from the PHY chip #112to the DPLL24in the synchronous Ethernet timing element26cross over the printed circuit board traces22connecting the four ports from the PHY chip #1214to the interfaces to the system. While not shown inFIG. 1, similar PCB trace crossovers exist for the recovered clock A line and the recovered clock B line that are provided from the PHY chips #2through #11(not shown) to the DPLL24in the synchronous Ethernet timing element26.

BRIEF DESCRIPTION

According to an aspect of the invention, a physical layer (PHY) chip for a synchronous Ethernet system includes N network input/output (I/O) ports where N is an integer, a first external recovered clock input, a first recovered clock output, and a first clock multiplexer having a plurality of data inputs, a select input, and an output coupled to the first recovered clock output, at least one of the data inputs coupled to a first recovered clock from a respective one of the N network I/O ports, a first additional data input coupled to the first external recovered clock input.

According to an aspect of the invention, a recovered clock from each of the N network I/O ports are coupled to respective ones of the plurality of data inputs.

According to an aspect of the invention, the PHY chip further includes a first source of configuration bits coupled to the select input of the first clock multiplexer.

According to an aspect of the invention, the first source of configuration bits is a first configuration bits register.

According to an aspect of the invention, N=4.

According to an aspect of the invention, the PHY chip further includes a first clock output divider having an input coupled to the output of the first clock multiplexer, an output coupled to the first recovered clock output, the first clock output divider controlled by configuration bits supplied by a configuration bits register.

According to an aspect of the invention, the PHY chip further includes M system interfaces where M is an integer, wherein the N network input/output (I/O) ports are connected to a first set of I/O pins on the PHY chip, the M system interfaces are connected to a second set of I/O pins on the PHY chip, the first external recovered clock input is connected to a third set of I/O pins on the PHY chip, the first recovered clock output is connected to a fourth set of I/O pins on the PHY chip, and the sets of I/O pins are arranged radially around a periphery of the PHY chip in the order of one of the first and second sets of I/O pins, one of the third and fourth sets of I/O pins, the other of the first and second sets of I/O pins, and the other of the third and fourth sets of I/O pins.

According to an aspect of the invention, the third and fourth sets of I/O pins and at least one of the first and second sets of I/O pins are physically located on a same side of a package containing the PHY chip.

According to an aspect of the invention, the PHY chip further includes a second external recovered clock input, a second recovered clock output, and a second clock multiplexer having a plurality of data inputs, a respective select input, and an output coupled to the second recovered clock output, at least one of the data inputs coupled to a second recovered clock from a respective one of the N network I/O ports, a first additional data input coupled to the first external recovered clock input and a second additional data input coupled to the second external recovered clock input.

According to an aspect of the invention, the second external recovered clock input is coupled to a second additional data input of the first clock multiplexer.

According to an aspect of the invention, the PHY chip further includes a second source of configuration bits coupled to the respective select input of the second clock multiplexer.

According to an aspect of the invention, the second source of configuration bits is a second configuration bits register.

According to an aspect of the invention, a method for providing a recovered clock in a PHY chip for a synchronous Ethernet system having a plurality of network interface ports includes receiving an external recovered clock signal from at least one of the plurality of network interface ports of the PHY chip, receiving a recovered clock signal from a source outside the PHY chip, and selecting an output clock signal from among the recovered clock signal from the source outside the PHY chip and the external recovered clock signal from the at least one of the plurality of network interface ports of the PHY chip.

According to an aspect of the invention, the method further includes dividing the output clock signal by a divisor.

According to an aspect of the invention, receiving a recovered clock signal from a source outside the PHY chip includes receiving first and second recovered clock signals from sources outside the PHY chip, and selecting an output clock signal from among the recovered clock signal from the source outside the PHY chip and the external recovered clock signal from the at least one of the plurality of network interface ports of the PHY chip comprises selecting a first output clock signal from among the first and second recovered clock signals from the source outside the PHY chip and the external recovered clock signals from the at least one of the plurality of network interface ports of the PHY chip, and selecting a second output clock signal from among the first and second recovered clock signals from the source outside the PHY chip and the external recovered clock signals from the at least one of the plurality of network interface ports of the PHY chip.

According to an aspect of the invention, the method further includes dividing the first output clock signal by a first divisor, and dividing the second output clock signal by a second divisor.

According to an aspect of the invention, the first divisor and the second divisor are equal.

According to an aspect of the invention, the first divisor and the second divisor are not equal.

DETAILED DESCRIPTION

Persons of ordinary skill in the art will realize that the following description is illustrative only and not in any way limiting. Other embodiments will readily suggest themselves to such skilled persons.

Referring now toFIG. 3, a diagram shows an illustrative multi-port Ethernet system90in accordance with an aspect of the present invention implemented using twelve PHY chips (three of which are represented by reference numerals92,94, and96). Though exemplary Ethernet system90is shown to include twelve PHY chips, in other embodiments more or fewer PHY chips could be used. Persons of ordinary skill in the art will appreciate that PHY chips in accordance with the present invention can be generalized as including N network I/O ports. The N network I/O ports of the PHY chip #192that are connected to Ethernet media interfaces to the network are indicated symbolically as rectangles in dashed lines at reference numeral98, the N network I/O ports of the PHY chip #294that are connected to interfaces to the network are indicated symbolically as rectangles in dashed lines at reference numeral100, and the N network I/O ports of the PHY chip #1296that are connected to interfaces to the network are indicated symbolically as rectangles in dashed lines at reference numeral102.

In the system90, M ports to system interfaces such as Ethernet MAC interfaces are shown from each of PHY chip #192, the PHY chip #294, and the PHY chip #1296. These ports are shown symbolically as rectangles in dashed lines in each PHY chip at reference numerals104,106, and108, respectively. Furthermore, for purposes of illustration only, in PHY chip #192, N=4 and M=3, in PHY chip #294, N=3 and M=4, in PHY chip #1296, N=4 and M=4, for the sole purpose of showing that M may be less than, equal to or greater than N Persons of ordinary skill in the art will understand that the values of N and M will typically be the same for each PHY chip in any given system.

In accordance with an aspect of the present invention, the recovered clock output A signals from the PHY chips in the system shown inFIG. 3are connected in a daisy chain fashion instead of each being provided to the multi-input DPLL110inside of a synchronous Ethernet timing element112. As shown inFIG. 3, the PHY chip #192has a recovered clock input carried by a printed circuit board trace114which is not used since the PHY chip #192is the first PHY chip in the daisy chained system. The recovered clock output A from the PHY chip #192is carried to the external recovered clock input A of the PHY chip #2by a printed circuit board trace shown at reference numeral116instead of to the DPLL110in the synchronous Ethernet timing element112as in the prior-art system depicted inFIG. 1.

Similarly, the recovered clock output A from the PHY chip #294is carried by a printed circuit board trace shown at reference numeral118and is provided to the external recovered clock input A of the next PHY chip #3(not shown). The recovered clock output A from the PHY chip #11(not shown) is provided to the external recovered clock input A of PHY chip #1296by printed circuit board trace120as shown. The recovered clock output A from the PHY chip #1296, is provided to the DPLL110of the synchronous Ethernet timing element112by a printed circuit board trace shown at reference numeral122. The DPLL110is synchronized to a stable frequency source such as an oven-controlled crystal oscillator (OCXO) shown at reference numeral124. DPLL110is advantageously a 1-input DPLL thus providing reduced cost over the prior-art arrangement shown inFIG. 1, which required one input per PHY chip in the system.

The illustrative embodiment shown inFIG. 3is being described in relation to recovery of a single clock, i.e. each PHY chip outputs a first recovered clock (clock output A). However, this is not meant to be limiting in any way, and in certain embodiments as will be shown herein, more than one recovered clock output can be provided from at least one of the PHY chips.

The multiport Ethernet PHY chip solution of the present invention provides at least one clock multiplexer internal to each PHY chip (e.g. PHY chips92,94,96) that selects between the recovered clocks of the PHY which contains it and at least one external recovered clock input. The internal clock multiplexer also provides one or more recovered clock outputs. One of the advantages of the present invention is that in some embodiments of the invention a clock recovered from any of the network I/O ports 1-48 (from among98,100,102inFIG. 3) may be provided as the recovered clock output A from the PHY chip #1296, on the printed circuit board trace shown at reference numeral124and fed to the synchronous Ethernet timing element112.

Referring now toFIG. 4, an illustrative PHY chip clock multiplexer arrangement130is shown in accordance with an aspect of the present invention. A clock multiplexer (A)132has a data input134supplying the network I/O Port 1 recovered A clock, a data input136supplying the network I/O Port 2 recovered A clock, a data input138supplying the network I/O Port 3 recovered A clock, and a data input140supplying the network I/O Port 4 recovered A clock. Persons of ordinary skill in the art will appreciate that in embodiments of the invention it is not necessary that recovered clocks from all of the network I/O ports be connected to clock multiplexer data inputs. In a PHY chip having N network I/O ports, the clock multiplexer132may have data inputs connected to recovered clocks of fewer than all N of the network I/O ports (e.g., from 1 to N of the network I/O ports be connected to clock multiplexer data inputs) as shown by the data inputs134,136,138, and140of the clock multiplexer132being represented as dashed lines. At a minimum, at least one of the N network I/O ports are connected to a respective clock multiplexer data input.

In addition to the up to four data inputs sourced by the recovered A clocks from the Ports 1-4, the clock multiplexer132has an additional data input. The additional data input142is a first external recovered clock input and provides the external recovered clock input A from the previous PHY chip in the daisy chain. The additional data input142is sourced by the recovered clock output A from the previous PHY chip in the daisy chain. This input is not used by the first PHY chip in the daisy chain as shown by the printed circuit board trace114of the PHY chip #112inFIG. 3. The data output144of the clock multiplexer (A)132supplies the recovered clock output A as selected by the value presented on the select inputs146of the clock multiplexer A132, denoted as output A clock select configuration.

In accordance with another aspect of the present invention, the data output144of the clock multiplexer132may optionally drive a clock output divider148. The output of the clock output divider148is presented on line150as the recovered clock output A. The divisor of the clock output divider148is configurable and is controlled by output A divider configuration bits presented to the clock output divider148on divider configuration input lines152. The output A clock select configuration bits for the clock multiplexer (A)132on lines146and the output A divider configuration bits on divider configuration input lines152are supplied by a source of configuration bits such as a configuration-bits register154as is known in the art. While a single configuration-bits register154is illustrated, there is no requirement that the optional output A divider configuration bits and the output A clock select configuration bits be part of a single register, and multiple configuration-bits registers may be utilized without exceeding the scope of the invention.

Referring now toFIG. 5, a table shows of the use of the clock multiplexer A132and clock output divider148at example port speeds of 10 Mbps, 100 Mbps, and 1000 Mbps providing an output clock frequency of 2.5 MHz. The clock output divider148provides a choice of divisors that may be set to allow the recovered clocks to be at the same frequency regardless of Ethernet port speed.

Referring now toFIG. 6, a diagram shows another illustrative 48-port Ethernet system170in accordance with an aspect of the present invention implemented using twelve four-port PHY chips (three of which are represented by reference numerals92,94, and96). The Ethernet system170ofFIG. 6shares certain ones of its elements with the Ethernet system90ofFIG. 3. Elements in the Ethernet system170ofFIG. 6that are common to the Ethernet system90ofFIG. 3will be referred to inFIG. 6using the same reference numerals that identified those elements inFIG. 3.

The four network I/O ports of the PHY chip #192that provide Ethernet media interfaces to the network are indicated symbolically as rectangles in dashed lines at reference numeral98, the four network I/O ports of the PHY chip #294that provide interfaces to the network are indicated symbolically as rectangles in dashed lines at reference numeral100, and the four network I/O ports of the PHY chip #1296that provide interfaces to the network are indicated symbolically as rectangles in dashed lines at reference numeral102.

Four ports to the system interfaces from the PHY chip #192, the PHY chip #294, and the PHY chip #1296are shown symbolically as rectangles in dashed lines at reference numerals104,106, and108, respectively. While twelve PHY chips are included in the 48-port Ethernet system170ofFIG. 6, those skilled in the art will recognize that any number of PHY chips may be utilized. Furthermore, which each PHY chip (92,94,96) are illustrated as having 4 system interfaces, M system interfaces may be provided for each PHY chip, with M being an integer and M may be less than, equal to or greater than N. As previously noted, in some embodiments of the invention, the system interfaces to which ports104,106, and108are connected may be Ethernet MAC interfaces. In the illustrative example ofFIG. 6, the connections to the network I/O ports are numbered consecutively, from I/O port 1 being the first network I/O port of PHY chip #192to I/O port 48 being the fourth network I/O port of PHY chip #1296.

Each of the PHY chips92,94, and96in the Ethernet system170ofFIG. 6is provided with two recovered clock inputs including the recovered clock input A and an additional recovered clock input B. Each of the PHY chips92,94, and96in the Ethernet system170ofFIG. 6provides two recovered clock outputs including the recovered clock output A and an additional recovered clock output B.

The recovered clock A and B inputs and outputs to/from the PHY chips in the Ethernet system170shown inFIG. 6are connected in a daisy chain fashion like the recovered clock A inputs and outputs in the Ethernet system90ofFIG. 3. As shown inFIG. 6, the recovered clock output A of PHY chip #192is connected to the recovered clock input A of PHY chip #294by printed circuit board trace116. The recovered clock output B of PHY chip #192is connected to the recovered clock input B of PHY chip #294by printed circuit board trace174. Similarly, the recovered clock output A from the PHY chip #294and the recovered clock output B from the PHY chip #294are provided to the recovered clock input A and the recovered clock input B of the next PHY chip (not shown) by printed circuit board traces118and176, respectively. The recovered clock outputs A and B from the PHY chip #11(not shown) are provided to the external recovered clock input A and external recovered clock input B of PHY chip #1296by printed circuit board traces120and178, respectively. The recovered clock output A from the PHY chip #1296, and the recovered clock output B from the PHY chip #1296, are both provided to the DPLL110of synchronous Ethernet timing element112by printed circuit board traces122and180, respectively. The DPLL110is synchronized to a stable frequency source such as an oven-controlled crystal oscillator (OCXO) shown at reference numeral124. The DPLL110in the system ofFIG. 6is advantageously a 2-input DPLL thus providing reduced cost over the prior art.

The illustrative embodiment shown inFIG. 6is being described in relation to recovery of 2 clocks, i.e. each PHY chip outputs a first clock (clock output A) and a second clock (clock output B). However this is not meant to be limiting in any way, and in certain embodiments, such as the one described above with reference toFIG. 3, only a single clock output is provided from at least one of the PHY chips or more than one clock output can be provided from at least one of the PHY chips.

The multiport Ethernet PHY chip solution of the present invention provides clock multiplexers internal to each PHY chip (e.g. PHY chips92,94,96) that selects between the recovered clocks of the internal PHYs and the external recovered clock inputs and provides one or more recovered clock outputs. One of the advantages of the present invention is that a clock recovered from any of the network I/O ports 1-48 (from among98,100,102inFIG. 6) may be provided as the recovered clock output A from the PHY chip #1296, and as the recovered clock output B from the PHY chip #1296, and fed to the DPLL110in the synchronous Ethernet timing element112.

Referring now toFIG. 7, an illustrative PHY chip clock multiplexer arrangement190is shown in accordance with an aspect of the present invention. A first clock multiplexer (A)192has a data input194supplying the network I/O Port 1 recovered A clock, a data input196supplying the network I/O Port 2 recovered A clock, a data input198supplying the network I/O Port 3 recovered A clock, and a data input200supplying the network I/O Port 4 recovered A clock. Persons of ordinary skill in the art will appreciate that in embodiments of the invention it is not necessary that recovered clocks from all of the network I/O ports be connected to clock multiplexer data inputs. In a PHY chip having N network I/O ports, the first clock multiplexer192may have data inputs connected to recovered clocks of fewer than all N of the network I/O ports (e.g., from 1 to N of the network I/O ports be connected to clock multiplexer data inputs). At a minimum, at least one of the N network I/O ports are connected to a respective clock multiplexer data input of the first clock multiplexer (A)192.

In addition to the four data inputs sourced by the recovered A clocks from the Ports 1-4, the first clock multiplexer (A)192has two additional data inputs. The first additional data input202is a first external recovered clock input and provides the external recovered clock input A from the previous PHY chip in the daisy chain. The second additional data input204is a second external recovered clock input and provides the external recovered clock input B from the previous PHY chip in the daisy chain. The data input202and the data input204are sourced by the recovered clock outputs A and B from the previous PHY chip in the daisy chain. These data inputs are not used by the first PHY chip in the daisy chain as shown by inputs114and172of the PHY chip #112inFIG. 6. The data output206of the first clock multiplexer (A)192is the source of the recovered clock output A208as selected by the value presented on the select inputs210of the first clock multiplexer (A)192, denoted as output A clock select configuration.

In accordance with another aspect of the present invention, the data output206of the first clock multiplexer (A)192may optionally drive a first clock output divider212. The output of the first clock divider212is presented on line208as the recovered clock output A. The divisor of the first clock output divider212is configurable and is controlled by output A divider configuration bits presented to the first clock output divider212on divider configuration input lines214. The output A clock select configuration bits for the first clock multiplexer (A)192on the select inputs210and the output A divider configuration bits on divider configuration input lines214for the first clock output divider212are supplied by a source of configuration bits such as a first configuration-bits register216as is known in the art. While a single first configuration-bits register216is illustrated, there is no requirement that the optional output A divider configuration bits and the output A clock select configuration bits be provided by a single first configuration bits register216, and multiple configuration-bits registers may be utilized without exceeding the scope of the present invention.

A second clock multiplexer (B)222is configured similarly to the first clock multiplexer (A)192and has a data input224supplying the network I/O Port 1 recovered B clock, a data input226supplying the network I/O Port 2 recovered B clock, a data input228supplying the network I/O Port 3 recovered B clock, and a data input230supplying the network I/O Port 4 recovered B clock. Persons of ordinary skill in the art will appreciate that in embodiments of the invention it is not necessary that recovered clocks from all of the network I/O ports be connected to clock multiplexer data inputs. In a PHY chip having N network I/O ports, the second clock multiplexer222may have data inputs connected to recovered clocks of fewer than all N of the network I/O ports (e.g., from 1 to N of the network I/O ports be connected to clock multiplexer data inputs). At a minimum, at least one of the N network I/O ports are connected to a respective clock multiplexer data input of the second clock multiplexer (B)222. Providing both the external recovered clock input A and the external recovered clock input A to the first and second clock multiplexers192and222allows maximum flexibility for selecting a recovered output clock.

In addition to the four data inputs sourced by the recovered B clocks from the Ports 1-4, the second clock multiplexer (B)222has two additional data inputs. The first additional data input232is a first external recovered clock input and provides the external recovered clock input A from the previous PHY chip in the daisy chain. The second additional data input234is a second external recovered clock input and provides the external recovered clock input B from the previous PHY chip in the daisy chain. The first additional data input232and the second additional data input234are sourced by the recovered clock outputs A and B from the previous PHY chip in the daisy chain. These additional inputs are not used by the first PHY chip in the daisy chain as shown by inputs114and172of the PHY chip #192inFIG. 6. The first additional data inputs202and232are tied together and the second additional data inputs204and234are tied together since they are driven from the same signals. The data output236of the second clock multiplexer (B)222supplies the recovered clock output B238as selected by the value presented on the select inputs240of the clock multiplexer B222, denoted as output B clock select configuration bits.

As with the first clock multiplexer (A)192, the data output236of the second clock multiplexer222may optionally drive a second clock output divider242. The output of the second clock divider242is presented on line238as the recovered clock output B. The divisor of the second clock output divider242is configurable and is controlled by output B divider configuration bits presented to the second clock output divider242on divider configuration input lines244. The output B clock select configuration bits for the second clock multiplexer222on select input240and the output B divider configuration bits for the clock output divider242are supplied by a source of configuration bits such as a second configuration-bits register246as is known in the art. Persons of ordinary skill in the art will appreciate that the output B clock select configuration bits and the optional output B divider configuration bits can be provided by multiple configuration-bits registers may be utilized without exceeding the scope of the invention.

Referring again toFIG. 5, a table shows of the use of the clock multiplexer A192and clock multiplexer B222and clock output dividers212and242at example port speeds of 10 Mbps, 100 Mbps, and 1000 Mbps providing an output clock frequency of 2.5 MHz. The configurable clock output dividers212,242each independently provide a choice of divisors that may be set to divide by the same divisor or by different divisors to allow the recovered clocks to be at the same frequency regardless of Ethernet port speed.

As can be seen from an examination ofFIG. 6andFIG. 7, it is possible to daisy-chain the recovered clocks by expanding the internal recovered clock multiplexer to take in two more clock inputs from the previous PHY chip in the chain.

Referring again toFIG. 3andFIG. 6, another aspect of the present invention is illustrated. In both the illustrative 48-port Ethernet systems90ofFIG. 3 and 170ofFIG. 6, each of the 4-Port Ethernet PHY chips92,94and96have a plurality of I/O pins. Some chips have I/O pads depending on the physical configuration of the chip but the word “pins” will be used herein to designate both types of I/O structures. Certain ones of these I/O pins are represented by small squares inFIG. 3and inFIG. 6disposed around the periphery of the PHY chip. For purposes of the I/O pins, the rectangles defining the PHY chips inFIG. 3andFIG. 6are intended to represent top views showing physical boundaries of the peripheries of all four sides of the PHY chips and the relative locations of the I/O pins.

A first set of I/O pins250of each of the PHY chips92,94and96are associated with the network I/O ports (reference numerals98,100, and102inFIG. 3andFIG. 6), and connect to the Ethernet media interfaces by printed circuit board traces collectively identified by reference numeral252a,252b, and252n, respectively. A second set of I/O pins254are associated with the system interfaces (reference numerals104,106, and108inFIG. 3andFIG. 6), and connect to the System Interfaces by printed circuit board traces collectively identified by reference numeral256a,256b, and256n, respectively. A third set of I/O pins258are associated with the first external recovered clock input (external recovered clock input A) ofFIG. 3, and the first and second external recovered clock inputs (external recovered clock input A and external recovered clock input B), respectively, ofFIG. 6, and a fourth set of I/O pins260are associated with the first external recovered clock output (external recovered clock output A) ofFIG. 3, and the first and second recovered clock outputs (external recovered clock input A and external recovered clock input B), respectively, ofFIG. 6.

In most designs the printed circuit board traces (252a,252b,252n,256a,256b, and256n) from the first and second sets of I/O pins250and254tend to run east-west while the printed circuit board traces (114,116,118,120,122,172,174,176,178, and180) from the third and fourth sets of I/O pins258and260tend to run north-south. In accordance with an aspect of the invention, the locations of the sets of I/O pins on the PHY chips are chosen to facilitate this arrangement without having to provide for printed circuit board traces connected to these sets of I/O pins to cross each other. Viewed another way, as positioned at the periphery of the PHY chips, the sets of I/O pins are arranged radially in the order of one of sets250and252, one of sets254and256, the other of250and252and the other of254and256. In the particular embodiment shown inFIG. 6, the second, third and fourth sets of I/O pins252,254, and256are located at the same (west) sides of each PHY chip and the first set of I/O pins250is located on the east sides of each PHY chip and it can be seen that (radially moving counterclockwise) the sets of I/O pins are arranged in the order of set250, then set254, then set252, then set206. In other embodiments, the first, third and fourth sets of I/O pins250,254, and256are located at the same (west) sides of the PHY chips and the second set of I/O pins252is located on the east sides of each PHY chip. In other embodiments, the first and second sets of I/O pins250and252may be located on the same sides (east or west) or on opposite sides (east and west) of the PHY chips as shown inFIG. 6and the third set of I/O pins254may be located on the south sides of the PHY chips and the fourth set of the I/O pins256may be located on the north sides of the PHY chips. In all of these configurations, the third set of I/O pins254may be connected to the fourth set of I/O pins256of successive PHY chips (e.g., PHY chip #1(92) to PHY chip #2(94) without the printed circuit board traces having to cross any of the printed circuit board traces used to access the first and second sets of I/O pins250,252on any of the PHY chips. This simplifies and lowers the cost of printed circuit board design.

The clock output dividers (148inFIGS. 4, 212 and 242inFIG. 7) allow the recovered clocks to be at the same frequency regardless of the Ethernet port speed, further simplifying the requirements for the DPLL110. By physically locating the recovered clock inputs and outputs on a single side of the PHY chip it is relatively easy to route the signals on the PCB without adding layers or plate throughs to accomplish cross over wiring.

The present invention as shown in the illustrative embodiment ofFIG. 6integrates two clock multiplexers inside the physical layer devices as shown inFIG. 7, each of which can select between internal recovered clocks as well as external recovered clocks and provide the outputs of the clock multiplexers to the next physical layer device or DPLL. For a 48-port Ethernet system the present invention requires only a two-input DPLL instead of a 48-input DPLL, further reducing system cost. This multiplexing structure allows the clock recovered from any two ports in the system170to be connected to the DPLL110.

Persons of ordinary skill in the art will appreciate that clock cleanup (e.g. jitter attenuation) is performed in the DPLL110, so some jitter accumulation is acceptable in the daisy-chaining. Such skilled persons will appreciate that there will still be practical limits on the number of PHY chips in the daisy-chain due to jitter accumulation, which will vary from system to system.