Manufacturing method of semiconductor structure

A manufacturing method of a semiconductor structure is provided. The manufacturing method of the semiconductor structure includes the following steps: providing a substrate; forming a gate structure on the substrate; forming a recess in the substrate at a lateral side of the gate structure; performing a pre-bake process at a temperature of 740-840° C. and under a pressure of equal to or higher than 150 torr; and forming an epitaxial buffer layer in the recess.

BACKGROUND

Technical Field

The disclosure relates in general to a manufacturing method of a semiconductor structure, and more particularly to a manufacturing method of a semiconductor structure having a low-defective epitaxial buffer layer.

Description of the Related Art

With the development of variety types of semiconductor devices, epitaxial growth technology has been widely used in manufacturing semiconductor devices.

In order to provide excellent performance of a semiconductor device, it is crucial to form an epitaxial layer with desired crystalline orientation on the substrate of the semiconductor device. Accordingly, treatments to the surface where the epitaxial layer is deposited have been studied and improved by the industry.

SUMMARY OF THE INVENTION

The disclosure is directed to a manufacturing method of a semiconductor structure. According to the embodiments of the present disclosure, native oxides on the deposition surface of the recess can be effectively removed by the pre-bake process with the specific processing window of a temperature of about 740-840° C. and a pressure of equal to or higher than 150 torr, such that a low-defective epitaxial buffer layer can be formed in the recess, and thus the performance of the semiconductor structure can be improved.

According to an embodiment of the present disclosure, a manufacturing method of a semiconductor structure is disclosed. The manufacturing method of the semiconductor structure includes the following steps: providing a substrate; forming a gate structure on the substrate; forming a recess in the substrate at a lateral side of the gate structure; performing a pre-bake process at a temperature of 740-840° C. and under a pressure of equal to or higher than 150 torr; and forming an epitaxial buffer layer in the recess.

DETAILED DESCRIPTION OF THE INVENTION

According to the embodiments of the present disclosure, native oxides on the deposition surface of the recess can be effectively removed by the pre-bake process with the specific processing window of a temperature of about 740-840° C. and a pressure of equal to or higher than 150 torr, such that a low-defective epitaxial buffer layer can be formed in the recess, and thus the performance of the semiconductor structure can be improved. The identical or similar elements of the embodiments are designated with the same reference numerals. It is to be noted that the drawings are simplified for clearly describing the embodiments, and the details of the structure(s) of the embodiment(s) are for exemplification only, not for limiting the scope of protection of the disclosure. Ones having ordinary skills in the art may modify or change the structure(s) according to the embodiments of the present disclosure.

FIGS. 1-4illustrate a manufacturing method of a semiconductor structure according to an embodiment of the present disclosure. Referring toFIG. 1, a substrate10is provided, and a gate structure20is formed on the substrate10. In the embodiment, the substrate10may be a semiconductor substrate including but not limited to a silicon substrate or a SOI substrate. In the embodiment, as shown inFIG. 1, a plurality of the gate structures20may be formed on the substrate10.

Referring toFIG. 1, in the embodiment, the step of forming the gate structure20may include forming a gate conductive layer21on the substrate10, forming a gate dielectric layer23between the substrate10and the gate conductive layer21, and forming a spacer27on sidewalls around the gate conductive layer21. In the embodiment, the gate conductive layer21may be formed of polysilicon, and the spacer27may be formed of silicon carbon nitride, silicon nitride, or a combination thereof. Optionally, the step of forming the gate structure20may further include forming a cap layer25on the gate conductive layer21. The cap layer25may be a hard mask layer.

Referring toFIG. 2, a recess30is formed in the substrate10at a lateral side of the gate structure20. The recess30is formed by such as an etching process. In the embodiment, as shown inFIG. 2, a plurality of the recesses30may be formed at lateral sides of the gate structures20.

After the recess30is formed, a pre-bake process is performed at a temperature of 740-840° C. and under a pressure of equal to or higher than 150 torr. Particularly, the pre-bake process is performed on a deposition surface of the recess30. As the recess30is formed, due to the etching process for forming the recess30in the substrate10, native oxides may form and remain on the etched surface of the recess30. The native oxides remained on the surface of the recess30may influence the epitaxial growth(s) of any following layer(s) to be formed thereon in the following steps. According to the embodiments of the present disclosure, the native oxides on the deposition surface of the recess can be effectively removed by the pre-bake process with the specific processing window of a temperature of about 740-840° C. and a pressure of equal to or higher than 150 torr, such that a low-defective epitaxial buffer layer can be formed in the recess, and thus the performance of the semiconductor structure can be improved.

In an embodiment, the pre-bake process may be performed under a pressure of about 200-600 torr. In an embodiment, the pre-bake process may be performed for about 30-300 seconds. In an embodiment, the pre-bake process may be performed with a pure hydrogen (H2) atmosphere.

In some embodiments, the manufacturing method of the present disclosure may further include chemically cleaning the deposition surface of the recess30before performing the pre-bake process. In some embodiments, chemically cleaning the deposition surface of the recess30may include one or more cleaning steps.

In some embodiments, chemically cleaning the deposition surface of the recess30may include treating the deposition surface of the recess30with a first etching solution, and the first etching solution includes a mixture of sulfonic acid (H2SO4) and hydrogen peroxide (H2O2).

In some embodiments, chemically cleaning the deposition surface of the recess30may further include treating the deposition surface of the recess30with a second etching solution, and the second etching solution includes a mixture of ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2), and water (H2O). In the embodiment, the deposition surface of the recess30is treated with the first etching solution followed by the second etching solution.

In some embodiments, chemically cleaning the deposition surface of the recess30may further include treating the deposition surface of the recess30with an etching gas, and the etching gas includes a mixture of ammonia (NH3) and nitrogen trifluoride (NF3). After the treatment of the etching gas, the deposition surface of the recess30is etched by less than 20 Å. In the embodiment, the deposition surface of the recess30is treated with the etching gas after the treatments of the first etching solution and the second etching solution.

In the embodiment, despite the deposition surface of the recess30may be treated with the first etching solution, the second etching solution, and/or the etching gas, chemically cleaning the deposition surface of the recess30is free from treating the deposition surface of the recess30with hydrofluoric (HF) acid. That is, in the whole chemical cleaning process, the deposition surface of the recess30is not treated with hydrofluoric (HF) acid. According to the embodiments of the present disclosure, the native oxides on the deposition surface of the recess can be effectively removed by the pre-bake process with the disclosed specific processing window without chemically cleaning the deposition surface by hydrofluoric (HF) acid etching, and thus the manufacturing steps can be simplified. In addition, without applying hydrofluoric (HF) acid in the recess30of the substrate10, particularly on the deposition surface of the recess30, any possible damage that may be caused by hydrofluoric (HF) acid to the semiconductor structure can be effectively prevented, and the morphology of the recess30as well as the gate structure20can remain intact.

Referring toFIG. 3, an epitaxial buffer layer40is formed in the recess30. In the embodiment, the epitaxial buffer layer40is formed on the deposition surface of the recess30after the deposition surface is chemically cleaned.

In the embodiment, the epitaxial buffer layer40may be formed of SiP or SiGe. In the embodiment, the epitaxial buffer layer40may have a thickness of about 70-80 Å. In the embodiment, as shown inFIG. 3, the epitaxial buffer layer40is formed on and conformal with the surface of the recess30.

Referring toFIG. 4, an epitaxial layer50is formed on the epitaxial buffer layer40for filling up the recess30. As such, the semiconductor structure is formed according to the manufacturing method of the present disclosure.

Further explanation is provided with the following examples. The influences of temperature and pressure in the pre-bake process on the defective percentage of the epitaxial buffer layer40formed in the recess30of the present disclosure are presented for showing the special effects provided by the manufacturing method according to the embodiments of the disclosure. However, the following examples are for purposes of describing particular embodiments only, and are not intended to be limiting.

FIG. 5illustrates the relationship of temperature of a pre-bake process vs. defective percentage of an epitaxial buffer layer of a semiconductor structure according to an embodiment of the present disclosure. In the examples as shown inFIG. 5, before the epitaxial buffer layers are formed in the recesses, the deposition surfaces of the recesses are chemically cleaned with the first etching solution, the second etching solution, and the etching gas, without being treated with hydrofluoric (HF) acid, followed by the pre-bake process performed under a pressure of 150 torr and at temperatures of 700° C., 790° C., and 850° C., respectively.

As shown inFIG. 5, when the pre-bake processes are performed under 150 torr and at 700° C. and 850° C., respectively, the measured defective percentages of the epitaxial buffer layers are about 0.8% and 1%, respectively. In contrast, when the pre-bake process is performed under 150 torr and at 790° C., the measured defective percentage of the epitaxial buffer layer is greatly reduced to below 0.3%. The C-shaped curve as shown inFIG. 5clearly shows the preferred processing window for making low-defective epitaxial buffer layers. That is, when the pre-bake process is performed under the combination of the specific numerical ranges of temperature and pressure as illustrated inFIG. 5, the measured defective percentage of the epitaxial buffer layer may be largely reduced, for example, by 55-70%.

FIG. 6illustrates the relationship of pressure of a pre-bake process vs. defective percentage of an epitaxial buffer layer of a semiconductor structure according to an embodiment of the present disclosure. In the examples as shown inFIG. 6, before the epitaxial buffer layers are formed in the recesses, the deposition surfaces of the recesses are chemically cleaned with the first etching solution, the second etching solution, and the etching gas, without being treated with hydrofluoric (HF) acid, followed by the pre-bake process performed at a temperature of 790° C. and under pressures of 100 torr, 150 torr, and 600 torr, respectively.

As shown inFIG. 6, when the pre-bake process is performed at 790° C. and under 100 torr, the measured defective percentage of the epitaxial buffer layer is about 0.8%. In contrast, when the pre-bake process is performed at 790° C. and under 150 torr, the measured defective percentage of the epitaxial buffer layer is greatly reduced to below 0.3%. Furthermore, when the pre-bake process is performed at 790° C. and under 600 torr, the measured defective percentage of the epitaxial buffer layer is greatly reduced to even below 0.15%. The curve as shown inFIG. 6clearly shows the preferred processing window for making low-defective epitaxial buffer layers. That is, when the pre-bake process is performed under the combination of the specific numerical ranges of temperature and pressure as illustrated inFIG. 6, the measured defective percentage of the epitaxial buffer layer may be largely reduced, for example, by 55-80%.

In summary, as presented in the examples shown inFIGS. 5-6, within the processing window of the pre-bake temperature of about 740-840° C. and the pre-bake pressure of equal to or higher than 150 torr, even when hydrofluoric (HF) acid is not used for treating the deposition surface of the recess, the native oxides on the deposition surface of the recess can still be effectively removed by the pre-bake process having the specific processing window, and thus a low-defective epitaxial buffer layer can be formed in the recess. Moreover, without applying hydrofluoric (HF) acid in the recess of the substrate, damages caused by hydrofluoric (HF) acid to the semiconductor structure can be effectively prevented, the morphology of the recess as well as the gate structure can remain intact, and thus the performance of the semiconductor structure can be further improved.