MEMORY DEVICE

A memory device includes a peripheral substrate and an array substrate. The peripheral substrate includes a page buffer and a high voltage processing circuits and has a peripheral substrate area. The array substrate includes an array. The array substrate and the peripheral substrate are stacked on each other, and a circuit distribution area of the high voltage processing circuit accounts for less than 10% of the peripheral substrate area.

TECHNICAL FIELD

The disclosure relates in general to a memory device.

BACKGROUND

With the shrinking of the chip size and the faster and faster development of the operating speed, the chip is more likely to generate a large amount of heat during operation. Therefore, how to dissipate the heat generated during the operation of the chip is one issue of the industry in this technical field.

SUMMARY

According to one embodiment, a memory device is provided. The memory device includes a peripheral substrate and an array substrate. The peripheral substrate includes a page buffer and a first high voltage processing circuit and has a peripheral substrate area. The array substrate includes an array. The array substrate and the peripheral substrate are stacked on each other, and a first circuit distribution area of the first high voltage processing circuit accounts for less than 10% of the peripheral substrate area.

According to another embodiment, a memory device is provided. The memory device includes a peripheral substrate, an array substrate and a high voltage processing substrate. The peripheral substrate includes a page buffer. The array substrate includes an array. The high voltage processing substrate includes a high voltage processing circuit. The array substrate, the peripheral substrate and the high voltage processing substrate are stacked on each other, and the peripheral substrate does not have any high voltage processing circuit.

According to another embodiment, a memory device is provided. The memory device includes a circuit board, a peripheral substrate, an array substrate and a high voltage processing substrate. The peripheral substrate includes a page buffer. The high voltage processing substrate includes a high voltage processing circuit and has a high voltage processing substrate area. The array substrate includes an array. The array substrate and the peripheral substrate are stacked on the circuit board, and the high voltage processing substrate is disposed on the circuit board, and a high voltage processing circuit area of the high voltage processing circuit accounts for greater than 90% of the high voltage processing substrate area.

DETAILED DESCRIPTION

Referring toFIGS.1A to1B,FIG.1Aillustrates a schematic diagram of a side view of a memory device100according to an embodiment of the present invention, andFIG.1Billustrates a schematic diagram of a top view of a peripheral substrate110and an array substrate120inFIG.1A. The memory device100is, for example, a flash memory, such as a NAND memory.

As shown inFIG.1B, the memory device100includes the peripheral substrate110and the array substrate120. The peripheral substrate110includes at least one page buffer111and a first high voltage processing circuit112and has a peripheral substrate area A110. The array substrate120includes an array121. The array substrate120and the peripheral substrate110are stacked on each other, and a first circuit distribution area A112of the first high voltage processing circuit112accounts for less than 10% of the peripheral substrate area A110, such as 1%, 2%, 3%, 4%, 5%, 6%, 7%, 8%, 9%, 10% or a real number between the aforementioned two proportional values. In comparison with the page buffer111, the first high voltage processing circuit112and the array121formed on the same substrate, since the array121is formed on the array substrate120in the present embodiment, the peripheral substrate110could spare a more space for the page buffer111with a larger area. The page buffer111with a larger area could provide more storage space for data reading, and meet the requirement of higher operating speed. In addition, the peripheral substrate110and the array substrate120could be manufactured separately, and it could simplify the overall manufacturing process and/or circuit design complexity of the memory device100.

A base of the peripheral substrate110and a base of the array substrate120are, for example, silicon wafers. The circuits on the peripheral substrate110and the array substrate120are, for example, formed by semiconductor manufacturing process.

As shown inFIG.1A, the peripheral substrate110further includes at least one low voltage input contact113and at least one high voltage input contact114. The low voltage input contact113is configured to receive one set or more of low voltage LV between 1.8 volts (V) to 5 V, and the high voltage input contact114is configured to receive a high voltage HV equal to or higher than 5 V. Due to the memory device100directly receiving the high voltage HV to reduce a boosting load of the first high voltage processing circuit112(for example, simplifying circuit design, reducing occupied space, etc.), a ratio of the first circuit distribution area A112of the first high voltage processing circuit112to the peripheral substrate area A110could be relatively reduced (In comparison with the fact that the peripheral substrate110does not receive the high voltage HV).

The “contact” herein refers to various input/output contacts, for example, a conductive pad, a conductive bump, a conductive pillar, etc.

The “high voltage processing circuit” herein is, for example, configured to raise the low voltage to the high voltage, for example, to an operating voltage of the array, such as 30 V. Specifically, the high voltage processing circuit is, for example, a charge pumping circuit, a word line decoder, a word line switch, or other circuits capable of converting or processing high voltage and the low voltage.

As shown inFIG.1B, the peripheral substrate110includes circuits other than the array. In other words, the peripheral substrate110does not include the array, and circuits other than the array could be formed on the peripheral substrate110. The peripheral substrate110and the array substrate120could be connected through face to face cu—cu hybrid bonding and through-silicon via (TSV) (similar to the conductive via510vand the conductive via530vinFIG.5A) for signal vertical connection. In other embodiment, the peripheral substrate110and the array substrate120could be connected through hybrid bonding for signal vertical connection, wherein the hybrid bonding is, for example, that: the metal pads for connection could be formed on the peripheral substrate110and the array substrate120respectively, and the peripheral substrate110and the array substrate120could be connected through the metal pads for electrical connection and signally connection.

As shown inFIG.1B, the array substrate120has an array substrate area A120. In the present embodiment, the array substrate120does not include a second high voltage processing circuit. In another embodiment, the array substrate120may include the second high voltage processing circuit having a second circuit distribution area, wherein the second circuit distribution area of the second high voltage processing circuit accounts for less than 1% of the array substrate area A120. Since the memory device100could directly receive the high voltage HV, the proportion of the second high voltage processing circuit in the array substrate120could be reduced, or even completely omitted.

Referring toFIGS.2A to2B,FIG.2Aillustrates a schematic diagram of a side view of a memory device200according to another embodiment of the present invention, andFIG.2Billustrates a schematic diagram of a top view of a peripheral substrate210, an array substrate220and a high voltage processing substrate230of the memory device200inFIG.2A. The memory device200is, for example, a flash memory, such as a NAND memory.

As shown inFIG.2A, the memory device200includes the peripheral substrate210, the array substrate220and the high voltage processing substrate230. The array substrate220, the peripheral substrate210and the high voltage processing substrate230are stacked on each other. One of the array substrate220, the peripheral substrate210and the high voltage processing substrate230could be disposed between the other two of the array substrate220, the peripheral substrate210and the high voltage processing substrate230. A base of the peripheral substrate210, the base of the array substrate220and the base of the high voltage processing substrate230are, for example, silicon wafers. The circuits on the peripheral substrate210, the array substrate220and the high voltage processing substrate230are formed by semiconductor process.

As shown inFIG.2B, the peripheral substrate210includes a page buffer211and has a peripheral substrate area A210. The array substrate220includes an array221. A first circuit distribution area A212of the first high voltage processing circuit212accounts for less than 10% of the peripheral substrate area A210, such as 1%, 2%, 3%, 4%, 5%, 6%, 7%, 8%, 9% %, 10%, or a real number between the aforementioned two proportional values. In comparison with the page buffer211, the first high voltage processing circuit212and the peripheral substrate210are formed on the same substrate, since the array221is formed on the array substrate220in the present embodiment, the peripheral substrate210could spare a more space for the page buffer211with a larger area. The page buffer211with a larger area could provide more storage space for data reading, and meet the requirement of higher operating speed. In addition, the peripheral substrate210, the array substrate220and the high voltage processing substrate230are manufactured separately, and could simplify the overall manufacturing process and/or circuit design complexity of the memory device200.

As shown inFIG.2B, the peripheral substrate210includes circuits other than the array. In other words, the peripheral substrate210does not include the array, and circuits other than the array could be formed on the peripheral substrate210. Two of the peripheral substrate210, the array substrate220and high voltage processing substrate230could be connected through at least one TSV (similar to the conductive via510vand the conductive via530vinFIG.5A) for signal vertical connection. In other embodiment, two of the peripheral substrate210, the array substrate220and high voltage processing substrate230could be connected through hybrid bonding for signal vertical connection, wherein the hybrid bonding is, for example, that: the metal pads for connection could be formed on two substrates respectively, and the two substrates could be connected through the metal pads for electrical connection and signally connection.

As shown inFIG.2B, the array substrate220has an array substrate area A220. In the present embodiment, the array substrate220does not include the second high voltage processing circuit. In another embodiment, the array substrate220may include the second high voltage processing circuit having a second circuit distribution area, wherein the second circuit distribution area of the second high voltage processing circuit accounts for less than 1% of the array substrate area A220. Since the memory device200could receive the high voltage HV, the proportion of the second high voltage processing circuit in the array substrate220could be reduced, or even completely omitted.

As shown inFIG.2B, the high voltage processing substrate230includes a third high voltage processing circuit231, at least one low voltage input contact232and at least one high voltage input contact233. The low voltage input contact232is configured to receive the low voltage LV less than 5 V, and the high voltage input contact233is configured to receive the high voltage HV equal to or higher than 5 V. The memory device200could selectively receive the high voltage HV. In the present embodiment, a third circuit distribution area A231of the third high voltage processing circuit231accounts for more than 90% of the high voltage processing substrate area A230of the high voltage processing substrate230, for example, 90%, 91%, 92%, 93%. %, 94%, 95%, 96%, 97%, 98%, 98%, 100%, or a real number between the aforementioned two proportional values. In the present embodiment, even if the high voltage input contact233is omitted, due to the third circuit distribution area A231of the third high voltage processing circuit231accounting for more than 90% of the high voltage processing substrate area A230of the high voltage processing substrate230, there is enough space to form a boost circuit capable of boosting the low voltage LV to the high voltage HV in the high voltage processing substrate230.

In the present embodiment, due to most of the high voltage processing circuits of the memory device200being disposed on the high voltage processing substrate230, the overall thermal management of the memory device200could be performed on the high voltage processing substrate230alone, and it is conduce to the heat dissipation rate of the memory device200.

Referring toFIGS.3A to3B,FIG.3Aillustrates a schematic diagram of a side view of a memory device300according to another embodiment of the present invention, andFIG.3Billustrates a schematic diagram of a top view of the peripheral substrate210, the array substrate220and a high voltage processing substrate330of the memory device300inFIG.3A. The memory device300is, for example, a flash memory, such as a NAND memory.

As shown inFIG.3B, the memory device300includes the peripheral substrate210, the array substrate220and the high voltage processing substrate330. The array substrate220, the peripheral substrate210and the high voltage processing substrate330are stacked on each other. One of the array substrate220, the peripheral substrate210and the high voltage processing substrate330could be disposed between the other two of the array substrate220, the peripheral substrate210and the high voltage processing substrate330. The base of the peripheral substrate210, the base of the array substrate220and the base of the high voltage processing substrate330are, for example, silicon wafers. The circuits on the peripheral substrate210, the array substrate220and the high voltage processing substrate330are formed by semiconductor process.

The memory device300of the embodiment of the present invention includes the features (structure, connection relationship, etc.) the same as or similar to that of the memory device200, and difference is that a size (for example, a top-view area) of the high voltage processing substrate330of the memory device300is smaller.

Two of the peripheral substrate210, the array substrate220and high voltage processing substrate330could be connected through at least one TSV (similar to the conductive via510vand the conductive via530vinFIG.5A) for signal vertical connection. In other embodiment, two of the peripheral substrate210, the array substrate220and high voltage processing substrate330could be connected through hybrid bonding for signal vertical connection, wherein the hybrid bonding is, for example, that: the metal pads for connection could be formed on two substrates respectively, and the two substrates could be connected through the metal pads for electrical connection and signally connection.

As shown inFIG.3B, the high voltage processing substrate330includes a third high voltage processing circuit331, at least one low voltage input contact332and at least one high voltage input contact333. The low voltage input contact332is configured to receive the low voltage LV less than 5 V, and the high voltage input contact333is configured to receive the high voltage HV equal to or higher than 5 V. In the present embodiment, a third circuit distribution area A331of the third high voltage processing circuit331accounts for more than 90% of a high voltage processing substrate area A320of the high voltage processing substrate330, for example, 90%, 91%, 92%, 93%. %, 94%, 95%, 96%, 97%, 98%, 98%, 100%, or a real number between the aforementioned two proportional values. In the present embodiment, due to the memory device300directly receiving the high voltage HV to reduce a boosting load of the first high voltage processing circuit331(for example, simplifying circuit design, reducing occupied space, etc.), a size of the high voltage processing substrate330could be reduced.

Referring toFIGS.4A to4B,FIG.4Aillustrates a schematic diagram of a side view of a memory device400according to another embodiment of the present invention, andFIG.4Billustrates a schematic diagram of a top view of a peripheral substrate410, the array substrate220and the high voltage processing substrate330of the memory device400in IFG.4A. The memory device400is, for example, a flash memory, such as a NAND memory.

As shown inFIG.4A, the memory device400includes the peripheral substrate410, the array substrate220and the high voltage processing substrate330. The peripheral substrate410, the array substrate220and the high voltage processing substrate330are stacked on each other. One of the peripheral substrate410, the array substrate220and the high voltage processing substrate330could be disposed between the other two of the peripheral substrate410, the array substrate220and the high voltage processing substrate330. The base of the peripheral substrate410, the base material of the array substrate220and the base of the high voltage processing substrate330are, for example, silicon wafers. The circuits on the peripheral substrate410, the array substrate220and the high voltage processing substrate330are formed by, for example, semiconductor manufacturing processes.

The memory device400of the embodiment of the present invention includes features (for example, structure, connection relationship, etc.) the same as or similar to that of the memory device300, and difference is that the peripheral substrate410could omit the first high voltage processing circuit212.

As shown inFIG.4B, the high voltage processing substrate330includes the third high voltage processing circuit331, at least one low voltage input contact332and at least one high voltage input contact333. The low voltage input contact332is configured to receive the low voltage LV less than 5 V, and the high voltage input contact333is configured to receive the high voltage HV equal to or higher than 5 V. In the present embodiment, the third circuit distribution area A331of the third high voltage processing circuit331accounts for more than 90% of the high voltage processing substrate area A320of the high voltage processing substrate330, for example, 90%, 91%, 92%, 93%. %, 94%, 95%, 96%, 97%, 98%, 98%, 100%, or a real number between the aforementioned two proportional values. In the present embodiment, due to the memory device400directly receiving the high voltage HV to reduce a boosting load of the first high voltage processing circuit331(for example, simplifying circuit design, reducing occupied space, etc.), the size of the high voltage processing substrate330could be reduced.

Two of the peripheral substrate410, the array substrate220and high voltage processing substrate330could be connected through at least one TSV (similar to the conductive via510vand the conductive via530vinFIG.5A) for signal vertical connection. In other embodiment, two of the peripheral substrate410, the array substrate220and high voltage processing substrate330could be connected through hybrid bonding for signal vertical connection, wherein the hybrid bonding is, for example, that: the metal pads for connection could be formed on two substrates respectively, and the two substrates could be connected through the metal pads for electrical connection and signally connection.

Referring toFIG.5A,FIG.5Aillustrates a schematic diagram of a cross-sectional view of a memory device500according to another embodiment of the present invention. The memory device500is, for example, a flash memory, such as a NAND memory. The memory device500includes a peripheral substrate510, an array substrate520and a high voltage processing substrate530. The peripheral substrate510, the array substrate520and the high voltage processing substrate530are stacked on each other. One of the peripheral substrate510, the array substrate520and the high voltage processing substrate530could be disposed between the other two of the peripheral substrate510, the array substrate520and the high voltage processing substrate530.

As shown inFIG.5A, in the present embodiment, the peripheral substrate510includes the features the same as or similar to that of the peripheral substrates in other embodiments, and it will not be repeated here. The array substrate520includes the features the same as or similar to that of the array substrate in other embodiment, and it will not be repeated here. The high voltage processing substrate530includes the features the same as or similar to that of the high voltage processing substrates in other embodiments, and it will not be repeated here.

As shown inFIG.5A, in the present embodiment, one of the peripheral substrate510, the array substrate520, and the high voltage processing substrate530includes at least one conductive via, and the conductive via is electrically connected to another of the peripheral substrate510, the array substrate520and the high voltage processing substrate530. For example, as shown inFIG.5A, the peripheral substrate510has at least one conductive via510v, the high voltage processing substrate530has at least one conductive via530v, and the conductive via510velectrically connects the array substrate520with the conductive via530vof the high voltage processing substrate530. The conductive via herein are, for example, TSV.

Referring toFIG.5B,FIG.5Billustrates a schematic diagram of a cross-sectional view of a memory device500′ according to another embodiment of the present invention. The memory device500′ is, for example, a flash memory, such as a NAND memory. The memory device500includes a peripheral substrate510′, an array substrate520′ and a high voltage processing substrate530′. The peripheral substrate510′, the array substrate520′ and the high voltage processing substrate530′ are stacked on each other. One of the peripheral substrate510′, the array substrate520′ and the high voltage processing substrate530′ could be disposed between the other two of the peripheral substrate510′, the array substrate520′ and the high voltage processing substrate530′.

Different from the memory device500inFIG.5A, two substrates of the memory device500′ in the present embodiment could be connected by hybrid bonding. For example, the peripheral substrate510′ includes at least one pad511′ and at least one pad512′, wherein the pad511′ and the pad512′ are respectively formed on opposite two sides of the array substrate510′. The array substrate520′ includes at least one pad521′. The high voltage processing substrate530′ includes at least one pad531′. The pads512′ of the peripheral substrate510′ and the pads521′ of the array substrate520′ are connected by hybrid bonding, and the pads511′ of the peripheral substrate510′ and the pads531′ of the high-voltage processing substrate530′ are connected by hybrid bonding. In addition, the pad is, for example, metal pad.

Referring toFIGS.6A to6B,FIG.6Aillustrates a schematic diagram of a top view of a memory device600according to another embodiment of the present invention, andFIG.6Billustrates a schematic diagram of a cross-sectional view of the memory device600inFIG.6Ain a direction6A-6B′. The memory device600is, for example, a flash memory, such as a NAND memory.

As shown inFIGS.6A and6B, the memory device600includes the peripheral substrate210, the array substrate220, the high voltage processing substrate330and at least one solder wire640. In the present embodiment, the peripheral substrate210is disposed between the array substrate220and the high voltage processing substrate330, but this is not intended to limit the embodiment of the present invention. A high voltage processing substrate area A330of the high voltage processing substrate330is smaller than the peripheral substrate area A210of the peripheral substrate210, and the solder wire640connects the high voltage processing substrate330with the peripheral substrate210.

Referring toFIGS.7A to7B,FIG.7Aillustrates a schematic diagram a top view of a memory device700according to another embodiment of the present invention, andFIG.7Billustrates a schematic diagram of a cross-sectional view of the memory device700ofFIG.7Ain a direction7A-7B′. The memory device700is, for example, a flash memory, such as a NAND memory.

As shown inFIGS.7A and7B, the memory device700includes the peripheral substrate510, the array substrate520, the high voltage processing substrate330, at least one solder wire640and a circuit board750. In the present embodiment, the peripheral substrate510and the array substrate520are stacked on the circuit board750, and the high voltage processing substrate330is disposed on the circuit board750, wherein a stack structure composed of the peripheral substrate510and the array substrate520is disposed on the circuit board750with the high voltage processing substrate330side by side. The peripheral substrate510includes at least one contact511exposed from the peripheral substrate510and facing upward. The high voltage processing substrate330includes at least one contact334exposed from the high voltage processing substrate330and facing upward. The solder wire640connects the exposed contact331of the high voltage processing substrate330with the exposed contact511of the peripheral substrate510.

Referring toFIGS.8A to8B,FIG.8Aillustrates a schematic diagram of a top view of a memory device800according to another embodiment of the present invention, andFIG.8Billustrates a schematic diagram of a cross-sectional view of the memory device800ofFIG.8Ain a direction8A-8B′. The memory device800is, for example, a flash memory, such as a NAND memory.

As shown inFIGS.8A and8B, the memory device800includes the peripheral substrate510, the array substrate520, the high voltage processing substrate330and a circuit board850. In the present embodiment, the peripheral substrate510and the array substrate520are stacked on the circuit board850, and the high voltage processing substrate330is disposed on the circuit board850, wherein a stack structure composed of the peripheral substrate510and the array substrate520is disposed on the circuit board850with the high voltage processing substrate330side by side. The peripheral substrate510includes at least one conductive via510vwhich is electrically connected to the circuit board850facing downward. The high voltage processing substrate330includes at least one contact331which is electrically connected to the circuit board850facing downward. As a result, the aforementioned stacked structure and the high voltage processing substrate330are electrically connected through the circuit board850.

To sum up, the embodiment of the present invention proposes a memory device including a page buffer, a high voltage processing circuit and an array, wherein the page buffer, most of the high voltage processing circuit and the array could be respectively formed on different substrates. In comparison with the page buffer, the high voltage processing circuit and the array formed on the same one substrate, since the array in the present embodiment is formed to the array substrate, the peripheral substrate could spare a more space for the page buffer with a larger area. The page buffer with a larger area could provide more storage space for data reading, and meet the requirement of higher operating speed. In addition, the peripheral substrate and the array substrate could be manufactured separately, and it could simplify the overall manufacturing process and/or circuit design complexity of the memory device. In another embodiment, at least two of the peripheral substrate, the array substrate and the high voltage processing substrate are stacked on each other to form a stack structure and are disposed on the circuit board, while an another one of the peripheral substrate, the array substrate and the high voltage processing substrate is disposed on the circuit board with the stack structure side by side. In addition, the aforementioned stacked structure could be electrically connected to the another one through a solder wire. Alternatively, the aforementioned stacked structure could be electrically connected to the another one through a circuit board (the solder wire could be omitted).