Semiconductor device with an electrically-coupled protection mechanism and associated systems, devices, and methods

A semiconductor device includes a first die; a first metal enclosure directly contacting and vertically extending below the first die, wherein the first metal enclosure peripherally encircles a first enclosed space; a second die directly contacting the first metal enclosure opposite the first die; a second metal enclosure directly contacting and vertically extending below the second die, wherein the second metal enclosure peripherally encircles a second enclosed space; and an enclosure connection mechanism directly contacting the first metal enclosure and the second metal enclosure for electrically coupling the first metal enclosure and the second metal enclosure.

This application contains subject matter related to a previously-filed U.S. patent application by Wei Zhou, Bret Street, and Mark Tuttle titled “SEMICONDUCTOR DEVICE WITH A PROTECTION MECHANISM AND ASSOCIATED SYSTEMS, DEVICES, AND METHODS.” The related application is assigned to Micron Technology, Inc., and is identified by application Ser. No. 15/693,230, filed Aug. 31, 2017. The subject matter thereof is incorporated herein by reference thereto.

This application contains subject matter related to a concurrently-filed U.S. patent application by Wei Zhou and Bret Street titled “SEMICONDUCTOR DEVICE WITH A LAYERED PROTECTION MECHANISM AND ASSOCIATED SYSTEMS, DEVICES, AND METHODS”. The related application is assigned to Micron Technology, Inc., and is identified by Ser. No. 15/878,755. The subject matter thereof is incorporated herein by reference thereto.

TECHNICAL FIELD

The present technology is related to semiconductor devices, and, in particular, to semiconductor devices with an electrically-coupled protection mechanism.

BACKGROUND

Semiconductor devices dies, including memory chips, microprocessor chips, and imager chips, typically include a semiconductor die mounted on another structure (e.g., a substrate, another die, etc.) and encased in a plastic protective covering. The die includes functional features, such as for memory cells, processor circuits, and imager devices, as well as interconnects that are electrically connected to the functional features. The interconnects can be electrically connected to terminals outside the protective covering to connect the die to higher level circuitry.

As illustrated inFIG. 1, a semiconductor device100(e.g., a three dimensional interconnect (3DI) type of device or a semiconductor package device) can include a die102having die interconnects104thereon connected to a substrate structure106(e.g., a printed circuit board (PCB), a semiconductor or wafer-level substrate, another die, etc.) having substrate interconnects108thereon. The die102and the substrate structure106can be electrically coupled to each other through the die interconnects104and the substrate interconnects108. Further, the die interconnects104and the substrate interconnects108can be directly contacted each other (e.g., through a bonding process, such as diffusion bonding or hybrid bonding) or through an intermediate structure (e.g., solder). The semiconductor device100can further include an encapsulant, such as an underfill110, surrounding or encapsulating the die102, the die interconnects104, the substrate structure106, the substrate interconnects108, a portion thereof, or a combination thereof.

With technological advancements in other areas and increasing applications, the market is continuously looking for faster and smaller devices. To meet the market demand, physical sizes or dimensions of the semiconductor devices are being pushed to the limit. For example, efforts are being made to reduce a separation distance between the die102and the substrate structure106(e.g., for 3DI devices and die-stacked packages).

However, due to various factors (e.g., viscosity level of the underfill110, trapped air/gases, uneven flow of the underfill110, space between the interconnets, etc.), the encapsulation process can be unreliable, such as leaving voids114between the die102and the substrate structure106(e.g., with portions of the interconnects failing to directly contact the underfill110). The voids114can cause shorting and leakage between the interconnects (e.g., between the substrate interconnect108and/or between the die interconnects104), causing an electrical failure for the semiconductor device100. Further, as the device grows smaller, the manufacturing cost can grow (e.g., based on using nano-particle underfill instead of traditional underfill).

DETAILED DESCRIPTION

The technology disclosed herein relates to semiconductor devices, systems with semiconductor devices, and related methods for manufacturing semiconductor devices. The term “semiconductor device” generally refers to a solid-state device that includes one or more semiconductor materials. Examples of semiconductor devices include logic devices, memory devices, and diodes, among others. Furthermore, the term “semiconductor device” can refer to a finished device or to an assembly or other structure at various stages of processing before becoming a finished device. Depending upon the context in which it is used, the term “substrate” can refer to a structure that supports electronic components (e.g., a die), such as a wafer-level substrate or a singulated die-level substrate, another die for die-stacking or 3DI applications, or a printed circuit board (PCB). A person having ordinary skill in the relevant art will recognize that suitable steps of the methods described herein can be performed at the wafer-level or at the die level. Furthermore, unless the context indicates otherwise, structures disclosed herein can be formed using conventional semiconductor-manufacturing techniques. Materials can be deposited, for example, using chemical vapor deposition, physical vapor deposition, atomic layer deposition, spin coating, and/or other suitable techniques. Similarly, materials can be removed, for example, using plasma etching, wet etching, chemical-mechanical planarization, or other suitable techniques.

Many embodiments of the present technology are described below in the context of protecting the semiconductor dies and the associated electrical connections and further utilizing the protection structure to relay electrical signals. For example, semiconductor devices (e.g., 3DI packaging solutions) can each include a semiconductor die with die interconnects thereon connected to a substrate structure (e.g., a PCB or another die). To protect the die and the die interconnects (e.g., against environmental factors, such as moisture, debris, etc.), the semiconductor devices can each include a metal (e.g., copper, aluminum, alloy, etc.) enclosure that surrounds the die interconnects along a horizontal plane. The metal enclosure can further extend vertically between and/or directly contact the die and the substrate to enclose the die interconnects. As such, the semiconductor devices can use the metal enclosure instead of any encapsulants (e.g., underfills) to isolate the die interconnects from surrounding exterior space and/or environment.

Further, the metal enclosure can be electrically coupled to conduct electrical signals or an electrical potential (e.g., for providing a ground connection or a source voltage). The metal enclosure can be electrically coupled using one or more through-silicon vias (TSVs), a conductive paste, one or more wires (e.g., bond wires), or a combination thereof. In some embodiments, the metal enclosure can be connected to (e.g., via a direct contact or through another conductor) an electro-magnetic interference (EMI) shield.

FIG. 2is a cross-sectional view along a line2-2inFIG. 3of a semiconductor device200(e.g., a semiconductor die assembly, including a 3DI device or a die-stacked package) in accordance with an embodiment of the present technology. The semiconductor device200can include one or more semiconductor dies mounted on or connected to a substrate (e.g., another die or a PCB). For example, the semiconductor device200can include a die stack202including a first die212connected on top of a second die214. In some embodiments, the die stack202can further include one or more inner dies216between the first die212and the second die214.

The dies in the semiconductor device200can be electrically connected through metal or conductive interconnects. For example, the first die212, the second die214, the inner dies216, or a combination thereof can be connected to each other and/or another structure (e.g., a PCB or another device) using internal interconnects218. In some embodiments, the internal interconnects218can be structures resulting from bonding or joining (e.g., such as through diffusion bonding or hybrid bonding) pillars, pads, or interconnect structures protruding from or exposed at a first boundary surface222(e.g., one of the surfaces of the dies, such as a bottom surface) to the corresponding structures protruding from or exposed at a second boundary surface224(e.g., an opposing surface of a die or a PCB facing the first boundary surface222, such as a top surface of a connected or an adjacent die or PCB). The first boundary surface222and the second boundary surface224can function as boundaries (e.g., such as top and bottom boundary planes) for an internal space226(“enclosed space226”) between the dies, between the die and the PCB, or a combination thereof.

The semiconductor device200can further include metal (e.g., copper, aluminum, alloy, etc.) enclosure structures220(“enclosures220”) that continuously surrounds or encloses the internal interconnects218along a horizontal plane. The enclosures220can each be a continuous and solid metallic (e.g., copper and/or solder) structure that forms a wall peripherally surrounding the internal interconnects218. The enclosures220can further extend from and directly contact the first boundary surface222to and the second boundary surface224. In some embodiments, the enclosures220(e.g., solid copper and/or solder structures) can be formed through a bonding process (e.g., diffusion bonding, thermal compression bonding, mass reflow, etc.). In some embodiments, the enclosures220can each have a vertical dimension or a height that is less than or equal to 20 μm. In some embodiments, the enclosures220can include solder that can be bonded through thermal compression bonding or mass reflow.

Each of the enclosures220can function as horizontal or peripheral boundaries (e.g., such as vertical planes marking peripheral edges along a horizontal plane) of the enclosed space226. The enclosed space226can be vacuum or filled with inert or specific gas (e.g., without any encapculant material or underfill therein). Accordingly, the enclosures220can isolate the internal interconnects218from external space on the outside of the enclosures220.

In some embodiments, an outer surface of the enclosures220can be located at an edge offset distance228(e.g., a distance measured along a horizontal direction) from a die periphery edge230. In some embodiments, the enclosures220can be located such that an edge or a surface thereof is coplanar or coincident with the die periphery edge230along a vertical plane or line (e.g., where the edge offset distance228is 0). In some embodiments, the enclosures220can be located such that a peripheral portion thereof horizontally extends beyond the die periphery edge230.

For the semiconductor device200, the enclosures220can further provide electrical connections for one or more of the dies, structures, and/or devices therein. For example, the enclosures220can be connected (e.g., through direct contact and/or through another electrical conductor, such as a trace) to one or more TSVs, such as periphery TSVs242(e.g., one or more TSVs located on periphery portions of the corresponding semiconductor die) and/or inner TSVs244(e.g., one or more TSVs located on an inner or central portion of the corresponding semiconductor die). Also for example, one or more of the internal interconnects218can be connected to (e.g., through direct contact and/or through another electrical conductor, such as a trace) to one or more TSVs, such as the inner TSVs244and/or the periphery TSVs242. The enclosures220can be connected to electrical ground, a source voltage, or a signal.

In some embodiments, the semiconductor device200can further include a device substrate262(e.g., a PCB) connected to one or more dies. For example, the device substrate262can be attached to the second die214(e.g., the bottom die) of the die stack202. The device substrate262and the attached die can be electrically coupled through one or more interconnects and/or one or more metal enclosure structures (e.g., that are connected to the TSVs of the bottom die) as discussed above. Alternatively, the device substrate262can be attached to the second die214using device interconnects264(e.g., solder) different from the internal interconnects218and/or the enclosures220. The device interconnects264can directly contact the TSVs of the bottom die and bond pads266on the device substrate262. In some embodiments, an underfill268can be between the bottom die and the device substrate262and encapsulate the device interconnects264. In some embodiments, an enclosure can be mounted between the bottom die and the device substrate262such that no underfill is needed.

In some embodiments, the enclosures220can be connected to each other (e.g., ring-to-ring and/or enclosure-to-enclosure connection) through an outer-enclosure connector, such as the periphery TSVs242. For example, as illustrated inFIG. 2, the semiconductor device200can include multiple semiconductor dies and the enclosures220. All of the dies can be aligned along one or more vertical lines or planes. Similarly, all of the enclosures can be aligned alone one or more vertical lines or planes (e.g., all of the enclosures can have same values for the edge offset distance228). Accordingly, all of the dies can include the periphery TSVs242at the same location and under the enclosures (e.g., shifted from the edge offset distance228, such as by a fraction of a thickness of the enclosures220). In some embodiments, one or more enclosures can be further connected to the device substrate262(e.g., ring-to-substrate or enclosure-to-substrate connection) through the periphery TSVs242and/or the device interconnects264.

As an illustrative example, the first die212can directly contact a first metal enclosure (e.g., one instance of the enclosures220) at a bottom surface of the first die. The first metal enclosure can extend vertically downward and peripherally encircle or surround (e.g., along a horizontal plane) a first enclosed space a first group of the internal interconnects218. The first metal enclosure can further directly contact another die, such as one of the inner dies, opposite the first die212. The one of the inner dies can further have a second metal enclosure directly contacting and extending vertically downward from a bottom surface of thereof. The one of the inner dies can include one or more periphery TSVs242that extends through the inner dies from the top surface to the bottom surface. The one or more periphery TSVs242can directly contact both the first metal enclosure and the second metal enclosure and electrically couple the metal enclosures, such as for grounding the metal enclosures.

FIG. 3is a cross-sectional view along a line3-3inFIG. 2of a semiconductor device in accordance with an embodiment of the present technology.FIG. 3can correspond to a bottom view of the semiconductor device200above the second die214ofFIG. 2(e.g., without showing the second die214and structures below). As discussed above, each of the enclosures220can encircle a periphery or a perimeter of the internal interconnects218along a plane.

For illustrative purposes, the enclosure is shown having a rectangular shape, uniform thickness or width, and concentric with a shape or outline of a corresponding die (e.g., one of the inner dies216ofFIG. 2). However, it is understood that the enclosures220can be different. For example, the enclosures220can have an oval shape, an irregular or asymmetrical shape, or any N-sided polygonal shape. Also for example, the enclosures220can have varying thickness or width at different portions. Also for example, the enclosures220can be offset or non-concentric with respect to the internal interconnects218or an arrangement thereof, the shape or outline of the die, or a combination thereof.

The enclosures220provide decrease in overall size of the semiconductor device. Because underfill is not necessary, the bond line thickness can be reduced, leading to a very low packaging height for multiple-die stacking. Further, the semiconductor device200that excludes solder in the interconnects218(e.g., by using a solid copper structure, such as resulting from Cu—Cu diffusion bonding) can provide a decrease in manufacturing cost by eliminating pillar bumping. Also, the semiconductor device200that exclude solder in the interconnects218provides reduction in failure rates by providing clean joints without solder caps, thereby removing failure modes associated with solder bridging, slumping, starvation, intermetallic compound (IMC), electromagnetic (EM) effect, etc.

The enclosures220can also provide a reduction in manufacturing cost and failure rates as the package height is decreased. The enclosures220can protect and isolate the internal interconnects218from environmental factors (e.g., moisture, debris, etc.), which eliminates the need for underfills (e.g., nano-particle underfills). Accordingly, the costs and the error rates associated with underfill laminate or flowing process, both of which increases rapidly as the space between the first boundary surface222ofFIG. 2and the second boundary surface224ofFIG. 2decreases, can be eliminated based on using the enclosures220to obviate the need for underfill. Further, the enclosures220provide a joint that can provide mechanical, thermal, and electrical traits or benefits previously provided by the underfill.

In some embodiments, the enclosures220throughout the die stack202ofFIG. 2can be connected to each other and to the electrical ground through the periphery TSVs242ofFIG. 2. Grounding the enclosures throughout the die stack202can improve the signal integrity for the die stack202. The grounded enclosures can provide electromagnetic or radio frequency (RF) shielding for the active signals within the enclosures.

The connected enclosures (e.g., for ring-to-ring connections and/or ring-to-substrate connections) can further provide higher current-carrying capacity (e.g., for grounding or source voltage connections) with reduced interference (e.g., in the form of noise or interference) for active signals (e.g., signals through the internal interconnects218). The enclosures and the periphery TSVs242can provide higher current-carrying capacity (e.g., in comparison to other interconnects) that results from increased dimensions and current-carrying material corresponding to the periphery location and the enclosing/encircling shape thereof. Further, the enclosures can be physically spaced apart or separated from the internal interconnects218, which can decrease any noise or interference that the grounding/power connections can have on active signals. Further, the separation can further decrease the likelihood of failure due to unintended electrical shorts (e.g., such as due to misalignment or misconnection, debris or bridges, etc.) between active signals, source voltage, electrical ground, or a combination thereof.

FIG. 4is a cross-sectional view of a semiconductor device400in accordance with an embodiment of the present technology. The semiconductor device400can be similar to the semiconductor device200ofFIG. 2. For example, the semiconductor device400can include multiple dies (e.g., such as for a die stack) with internal interconnects providing electrical connections. Also for example, the semiconductor device400can further include one or more metal enclosure structures420(“enclosures420”) between dies, between a die and a device substrate, or a combination thereof with each enclosure enclosing a space (e.g., enclosed space) that includes the internal interconnects. The enclosed space can otherwise be vacuum or filled with inert or specific gas. The internal interconnects, the enclosures420, or a combination thereof can be electrically connected to (e.g., via direct contact or through a conductor) integrated circuits, bond pads, TSVs, or a combination thereof in or on the dies.

In some embodiments, the enclosures420can be connected to each other (e.g., ring-to-ring and/or enclosure-to-enclosure connection) through an outer-enclosure connector, such as a conductive paste442. For example, as illustrated inFIG. 4, the semiconductor device400can have a fillet of the conductive paste442directly contacting a periphery surface of each of the enclosures420(e.g., along with periphery portions of the dies). The conductive paste442can be continuous along a vertical direction and directly contact one or more bond pads466on device substrate464that is connected to the dies. The conductive paste442can provide an electrical connection between the one or more bond pads466(that are, e.g., electrically connected to the electrical ground, a source voltage, a reference voltage or signal, etc.) and the enclosures420.

The conductive paste442can be isolated from active signals since the enclosures420act as barriers between the conductive paste442and inner/central portions of the dies and/or active surfaces thereof, internal connectors, or a combination thereof. Further the conductive paste442can be isolated from active signals based on an underfill material that is between the die stack and the device substrate464and encapsulates device interconnects that carry the active signals.

The conductive paste442can provide a high-current-capable ground path for the enclosures420. Accordingly, the conductive paste442can provide increase RF shielding along with the enclosures420and improve the signal integrity (e.g., reduced interference and/or noise) of the semiconductor device400. Further, with the enclosures420acting as barriers and physically separated from internal connectors, the enclosures420can further decrease the likelihood of failure due to unintended electrical shorts (e.g., such as due to misalignment or misconnection, debris or bridges, etc.) between active signals, source voltage, electrical ground, or a combination thereof.

FIG. 5is a cross-sectional view of a semiconductor device500in accordance with an embodiment of the present technology. The semiconductor device500can be similar to the semiconductor device200ofFIG. 2. For example, the semiconductor device500can include multiple dies (e.g., such as for a die stack) with internal interconnects providing electrical connections. Also for example, the semiconductor device500can further include one or more metal enclosure structures520(“enclosures520”) between dies, between a die and a device substrate, or a combination thereof with each enclosure enclosing a space (e.g., enclosed space) that includes the internal interconnects. The enclosed space can otherwise be vacuum or filled with inert or specific gas. The internal interconnects, the enclosures520, or a combination thereof can be electrically connected to (e.g., via direct contact or through a conductor) integrated circuits, bond pads, TSVs, or a combination thereof in or on the dies.

In some embodiments, the enclosures520can be connected to each other (e.g., ring-to-ring and/or enclosure-to-enclosure connection) through an outer-enclosure connector, such as bond wires542. For example, as illustrated inFIG. 5, the semiconductor device500can have a bond wire directly contacting a periphery surface of one or more of the enclosures520. The bond wires542can further directly contact one or more bond pads566on device substrate564that is connected to the dies, and provide an electrical connection between the one or more bond pads566(e.g., for providing a connection to the electrical ground, a source voltage, a reference voltage or signal, etc.) and the enclosures520. Also for example, the semiconductor device500can have the bond wires directly contacting and connecting the enclosures520(i.e., without going through the bond pads566), such as daisy-chained wiring schemes.

The exposed periphery surface of the enclosures520can provide greater surface area than a connection pad on the dies and/or bond pads that correspond to active signals. As such, each of the enclosures520can connect to multiple bond wires and/or thicker gauge wires to provide a high-current-capable ground path. Accordingly, the bond wires542and the enclosures520can provide increase RF shielding and improve the signal integrity (e.g., reduced interference and/or noise) of the semiconductor device500.

FIG. 6is a cross-sectional view of a semiconductor device600in accordance with an embodiment of the present technology. The semiconductor device600can be similar to the semiconductor device200ofFIG. 2. For example, the semiconductor device600can include multiple dies, such as arranged in multiple stacks. The semiconductor device600can include a first die stack602and a second die stack604. Each die stack can include multiple dies with internal interconnects providing electrical connections.

Also for example, one or more stacks (e.g., the first die stack602and/or the second die stack604) of the semiconductor device600can further include multiple metal enclosure structures620(“enclosures620”) between dies, between a die and a device substrate, or a combination thereof with each enclosure enclosing a space (e.g., enclosed space) that includes the internal interconnects. The enclosed space can otherwise be vacuum or filled with inert or specific gas. The internal interconnects, the enclosures620, or a combination thereof can be electrically connected to (e.g., via direct contact or through a conductor) integrated circuits, bond pads, TSVs, or a combination thereof in or on the dies.

In some embodiments, the enclosures620can be connected to each other (e.g., ring-to-ring and/or enclosure-to-enclosure connection, including connections within each die stack and/or across die stacks) through an outer-enclosure connector, such as a conductive paste642and/or bond wires644. For example, as illustrated inFIG. 6, the semiconductor device600can have the conductive paste642directly contacting a periphery surface of each of the enclosures620(e.g., along with periphery portions of the dies) for multiple die stacks. As illustrated inFIG. 6, the conductive paste642can be between the first die stack602and the second die stack604, directly contacting the enclosures620in both the first die stack602and the second die stack604. The conductive paste642can provide electrical connection across the enclosures620of multiple die stacks. In some embodiments, the conductive paste642can further contact one or more bond pads646on a device substrate648that is connected to the die stacks.

In some embodiments, the enclosures620can further be connected to each other through the bond wires644. One end of each of the bond wires644can be directly attached to one of the enclosures620. The opposing end of the bond wires644can be directly attached to one or more bond pads646. The bond pads646can provide a connection to the electrical ground, a source voltage, a reference voltage or signal, etc. In some embodiments, one or more of the bond wires644can be used to directly contact and connect the enclosures620across the first die stack602and the second die stack604. For example, the one or more of the bond wires644can extend along a horizontal direction between the first die stack602and the second die stack604and directly contact the enclosures thereof. Accordingly, the one or more of the bond wires644can electrically connect the enclosures in the different die stacks, similarly as the conductive paste642illustrated inFIG. 6.

The conductive paste642directly contacting and electrically shorting the enclosures620across multiple/adjacent die stacks can provide high-current power or ground connection between the die stacks that doesn't pass through an interposer. For example, the conductive paste642can bridge together the enclosures620across adjacent high bandwidth memory (HBM) stacks. The conductive paste642can provide a shorter path (e.g., in comparison to a path through other conductors or circuitry). The shorter path can further eliminate ground loops that interfere with signal integrity for the semiconductor device600.

FIG. 7is a cross-sectional view of a semiconductor device in accordance with an embodiment of the present technology. The semiconductor device700can be similar to the semiconductor device200ofFIG. 2. For example, the semiconductor device700can include multiple dies702(e.g., such as for a die stack) with internal interconnects providing electrical connections. Also for example, the semiconductor device700can further include one or more metal enclosure structures720(“enclosures720”) between the dies702, between a die and a device substrate, or a combination thereof with each enclosure enclosing a space (e.g., enclosed space) that includes the internal interconnects. The enclosed space can otherwise be vacuum or filled with inert or specific gas. The internal interconnects, the enclosures720, or a combination thereof can be electrically connected to (e.g., via direct contact or through a conductor) integrated circuits, bond pads, TSVs, or a combination thereof in or on the dies.

In some embodiments, the enclosures720can be further connected to each other (e.g., ring-to-ring and/or enclosure-to-enclosure connection) through an outer-enclosure connector, such as a metal shield742(e.g., an EMI or RF shield) and/or periphery TSVs744. For example, as illustrated inFIG. 7, the semiconductor device700can have the metal shield742directly contacting, connected to (e.g., via solder, conductive paste, etc.), or integral with (e.g., via a diffusion bonding process) a periphery surface of one or more of the enclosures720(e.g., along with periphery portions of the dies). The metal shield742can encompass or surround the dies (e.g., the die stack) over the device substrate. Also for example, one or more of the dies in the semiconductor device700can include the periphery TSVs744directly connected to the enclosures720. When the rings are grounded (e.g., through the periphery TSVs744), the metal shield742can be grounded through the direct contact with the enclosures720, eliminating any need for an electrical connection between the metal shield742and a device substrate.

FIGS. 8-9are cross-sectional views illustrating a semiconductor device at selected stages in a manufacturing method in accordance with an embodiment of the present technology. As illustrated inFIG. 8, the method can include a stage for providing a first die802. The first die802can include first-die interconnects804(e.g., solid metal structures for providing electrical connections to circuits within the first die802, such as for a portion of the internal interconnects) protruding below a first die bottom surface. The first die802can further include a first-die enclosure810(e.g., a solid metal structure, such as for a portion of the metal enclosure structure) encircling a perimeter of the first die interconnects804along a horizontal plane.

The first die802with the die interconnects804and the die enclosure806can be manufactured using a separate manufacturing process (e.g., wafer or die level manufacturing process). The separate manufacturing process can produce the die interconnects804and the die enclosure806according to a protrusion measure812(e.g., a height of the metal structures, such as a length measured between the die bottom surface and a distal portion of the die interconnects804and the die enclosure806). In some embodiments, the protrusion measure812can include a distance less than 20 μm. According to the protrusion measure812, the distal portions (e.g., relative to the die bottom surface) of the die interconnects804and the die enclosure806can be coplanar along a horizontal plane that is parallel with the die bottom surface. In some embodiments, the separate manufacturing process can include forming one or more TSVs (e.g., inner TSVs and/or periphery TSVs) directly contacting the interconnects and/or the enclosure.

As illustrated inFIG. 9, the method can include a stage for providing a substrate906(e.g., a PCB or another die, such as the second die, one of the inner dies, etc.). The substrate906can include substrate interconnects904(e.g., solid metal structures for providing electrical connections to the substrate906, such as for a portion of the internal interconnects) protruding above a substrate top surface. The substrate906can further include a substrate enclosure910(e.g., a solid metal structure, such as for a portion of the metal enclosure structure) encircling a perimeter of the substrate interconnects904along a horizontal plane.

The substrate906with the substrate interconnects904and the substrate enclosure910can be manufactured using a separate manufacturing process (e.g., wafer or die level manufacturing process or a process for manufacturing a printed circuit board). Similar to the stage illustrated inFIG. 8, the separate manufacturing process can produce the substrate interconnects904and the substrate enclosure910according to a protrusion measure912(e.g., a height of the metal structures, such as a length measured between the second boundary surface224and a distal portion of the substrate interconnects904and the substrate enclosure910). In some embodiments, the protrusion measure912can include a distance less than 20 μm. According to the protrusion measure912, the distal portions (e.g., relative to the substrate top surface) of the substrate interconnects904and the substrate enclosure910can be coplanar along a horizontal plane that is parallel with the substrate top surface. In some embodiments, the separate manufacturing process can include forming one or more TSVs (e.g., inner TSVs and/or periphery TSVs) directly contacting the interconnects and/or the enclosure

As illustrated inFIG. 10, the method can include a stage for aligning the substrate906and the die802. The substrate906and the die802can be aligned based on aligning reference portions (e.g., a center portion, a periphery edge or surface, etc.) thereof along a line or a plane (e.g., a vertical line or plane forFIG. 10). The structures can be aligned such that the die enclosure810and the substrate enclosure910are aligned along a line or a plane (e.g., a vertical line or plane). Further, the structures can be aligned such that the die enclosure810and the substrate enclosure910directly contact each other. The die interconnects804and the substrate interconnects904can be similarly aligned.

As illustrated inFIG. 11, the method can include a stage for bonding the metal structures (e.g., the die enclosure810to the substrate enclosure910and/or the die interconnects804to the substrate interconnects904). For example,FIG. 11can represent a diffusion bonding process1100(e.g., Cu—Cu diffusion bonding) that includes a solid-state welding process (e.g., utilizing coalescence at temperatures essentially below the melting point of the structures, with or without pressure/force pushing the structures together) for joining metals based on solid-state diffusion. The diffusion bonding process1100can include creating a vacuum condition or filling the space (e.g., the enclosed space) with inert gas, heating the metal structures, pressing the metal structures together, or a combination thereof.

Based on the bonding stage, the metal structures can bond or fuse and form a continuous structure. For example, the die enclosure810and the substrate enclosure910can be bonded to form the enclosures220ofFIG. 2, the enclosures420ofFIG. 4, the enclosures520ofFIG. 5, the enclosures620ofFIG. 6, the enclosures720ofFIG. 7, or a combination thereof. Also for example, the die interconnects804and the substrate interconnects904can be bonded to form the internal interconnects (such as for218ofFIG. 2).

Diffusion bonding the die enclosure810to the substrate enclosure910(e.g., Cu—Cu diffusion bonding) and the die interconnects804and the substrate interconnects904(e.g., Cu—Cu diffusion bonding) provides reduced manufacturing failures and cost. The diffusion bonding process can eliminate solder, thereby reducing any potential failures and costs associated with the soldering process. Further, the interconnects and the enclosures can be bonded using one bonding process, which can further simply the manufacturing process.

FIG. 12is a flow diagram illustrating an example method1200(“method1200”) of manufacturing a semiconductor device in accordance with an embodiment of the present technology. For example, the method1200can be implemented to manufacture the semiconductor device200ofFIG. 2, the semiconductor device300ofFIG. 3, the semiconductor device400ofFIG. 4, the semiconductor device500ofFIG. 5, the semiconductor device600ofFIG. 6, and/or the semiconductor device700ofFIG. 7. Also for example, the method1200can include stages illustrated inFIGS. 8-11.

The method1200can include providing one or more semiconductor die stacks (e.g., the die stack202ofFIG. 2, the die stack ofFIG. 4, the die stack ofFIG. 5, the first die stack602ofFIG. 6, the second die stack604ofFIG. 6, the die stack ofFIG. 7, etc.), such as the die stacks formed according to stages illustrated inFIGS. 8-11(e.g., semiconductor/wafer level processes, as illustrated in block1220), as illustrated at block1202. The one or more semiconductor die stacks can include multiple metal enclosures (e.g., the enclosures220ofFIG. 2, the enclosures420ofFIG. 4, the enclosures520ofFIG. 5, the enclosures620ofFIG. 6, the enclosures720ofFIG. 7, etc.) disposed between multiple semiconductor dies (e.g., the top die, one or more middle dies, the bottom die, etc. as illustrated inFIGS. 2-7).

For example, the die stack can include a first metal enclosure that directly contacts and vertically extend below from a bottom surface of a top die. The first metal enclosure can directly contact a top surface of an adjacent die opposite the bottom surface of the top die. The die stack can further include a second metal enclosure that directly contacts and vertically extend below from a bottom surface of the adjacent die, and further directly contacts a next adjacent die.

The enclosures in each of the stacks can encircle or surround internal interconnects (e.g., conductors for communicating active signals to/from/between dies). Each of the enclosures can further surround or enclose an enclosed space between a pair of dies. The enclosed spaces can be vacuum or a gas. Otherwise, the die stack can be without any underfill or encapsulation between the dies and/or within the enclosed spaces.

In some embodiments, the die stacks can include solder bumps (e.g., device interconnects) attached to a bottom surface of a bottom die in the die stack. In some embodiments, the die stacks can also include underfill directly on the bottom surface of the bottom die. The underfill can encompass the solder bumps.

The method1200can include providing a substrate (e.g., the device substrate, such as a PCB, illustrated inFIG. 2and/orFIGS. 4-7) as illustrated at block1204. In some embodiment, providing the substrate can include manufacturing the substrate, such as based on forming traces, vias, masks, etc., and/or based on attaching/connecting circuit components to the substrate. In some embodiments, providing the substrate can include positioning and/or attaching to a frame for further processing.

The method1200can include attaching the structures as illustrated at block1206. For example, one or more die stacks can be attached to the substrate, such as based on reflowing the solder flows. For attaching multiple die stacks to the substrate, the die stacks can be separated or spaced apart from each other along horizontal directions. Accordingly, a gap or a separation space can be between a pair/set of die stacks.

The method1200can include electrically coupling the enclosures using one or more enclosure connection mechanisms (e.g., the periphery TSVs242ofFIG. 2, the conductive paste442ofFIG. 4 and 642ofFIG. 6, the bond wires544ofFIG. 5, the metal shield742ofFIG. 7, etc.) as illustrated at block1208. For example, the enclosure connection mechanism can directly contact and electrically couple together multiple enclosures within the die stack. Also for example, the enclosure connection mechanism can directly contact and electrically couple together multiple enclosures across multiple die stacks.

In some embodiments, electrically coupling the enclosures can include applying a fillet of the conductive paste442to the enclosures as illustrated at block1212. The conductive paste442can be applied as a continuous fillet extending in a vertical direction and directly contacting the metal enclosures within the die stack, such as illustrated inFIG. 4. The conductive paste442can also be applied to fill a space or a gap between a pair/set of die stacks, such that the conductive paste442directly contacts the metal enclosures across multiple die stacks, such as illustrated inFIG. 6.

In some embodiments, electrically coupling the enclosures can include attaching the bond wires544to the enclosures as illustrated at block1214. The bond wires544can be attached to the metal enclosures at one end. Opposite the metal enclosures, the bond wires544can be attached to one or more bond pads on the device substrate. In some embodiments, the bond wires544can each be connected to a pair of adjacent enclosures, such as for daisy-chained wiring schemes.

In some embodiments, electrically coupling the enclosures can include attaching the metal shield742to the enclosures, the dies, and/or the device substrate as illustrated at block1216. The metal shield742can be placed or attached to surround the die stack and the dies therein.

In some embodiments, the metal shield742can directly contact the metal enclosures in the die stack. In some embodiments, the metal shield742can be attached and/or integral with the enclosures. For example, the metal shield742can be attached to the enclosures using solder. Also for example, the metal shield742can be bonded to the metal enclosures, such as through a diffusion bonding process.

FIG. 13is a flow diagram illustrating a further example method1300(“method1300”) of manufacturing a semiconductor device in accordance with an embodiment of the present technology. For example, the method1300can be implemented to manufacture one or more device stacks for the semiconductor device200ofFIG. 2, the semiconductor device300ofFIG. 3, the semiconductor device400ofFIG. 4, the semiconductor device500ofFIG. 5, the semiconductor device600ofFIG. 6, and/or the semiconductor device700ofFIG. 7. Also for example, the method1300can include stages illustrated inFIGS. 8-11.

The method1300can include providing semiconductor dies as illustrated at block1302. Providing the semiconductor die can correspond to the stage(s) illustrated inFIG. 8and/orFIG. 9. The provided die can include die interconnects (e.g., the die interconnects804ofFIG. 8, inter connects904ofFIG. 9, etc.) and a die enclosure (e.g., the die enclosure810ofFIG. 8, enclosure910ofFIG. 9, etc.) protruding downward from a die bottom surface. The die enclosure can peripherally surround the die interconnects on or along the die bottom surface. The provided die can further have bottom or distal portions or surfaces of the die interconnects coplanar with bottom or distal portions or surfaces of the die enclosure. For example, the bottom or distal portions of the die interconnects and the die enclosure can be coplanar along a horizontal plane that is parallel to the die bottom surface and is vertically offset from the die bottom surface by a protrusion measure. In some embodiments the die enclosure can include copper, aluminum, nickel, other metals, or a combination thereof.

The die can be manufactured or formed using a separate manufacturing process, as illustrated at block1320. For example, the die manufacturing process can include wafer-level processing, such as a doping process to form integrated circuitry and a singulating process to separate the individual dies. Also for example, the die manufacturing process can include electrically coupling the enclosures as illustrated at block1350.

In some embodiments, electrically coupling the enclosures can include forming one or more TSVs (e.g., the periphery TSVs242ofFIG. 2at a periphery portion of the corresponding die). For example, the TSVs can be formed based on lithography or etching, masking or depositing seed layer, plating, back-side processing, or a combination thereof.

In some embodiments, electrically coupling the enclosures can also include forming the enclosure rings (e.g., die enclosure) connected to one or more of the TSVs. For example, the enclosure rings can be formed directly contacting or integral with the periphery TSVs242. The enclosure rings can be formed using a process similar to the TSVs.

The method1300can include aligning the structures as illustrated at block1304(e.g., the dies and the metal enclosures). Aligning the structures can correspond to the stage illustrated inFIG. 10. For example, the alignment process can align the dies over the substrate with a portion of each die interconnect coincident with a corresponding portion of each substrate interconnect along vertical lines and/or a portion of the die enclosure coincident with the substrate enclosure along vertical lines. Also for example, the alignment process can align the die over the substrate with the die enclosure directly contacting the substrate enclosure.

The method1300can further include bonding the structures (e.g., the die interconnects to the substrate interconnects and/or the die enclosure to the substrate enclosure) as illustrated at block1306. The bonding process can correspond to the stage illustrated in FIG.11. The bonding process can include controlling temperature of one or more of the structures (e.g., heating to bond and then cooling to solidify the jointed structures), applying pressure on the structures, or a combination thereof. For example, the bonding process can include diffusion bonding (e.g., thermal compression bonding or TCB) as illustrated at block1312.

Through the bonding process, the enclosures and the enclosed spaces can form. Since metal (e.g., copper, solder, etc.) sufficiently blocks moisture and other debris, underfill is no longer needed for the manufacturing process. As such, the bonding process can bond the structures without any underfill in the enclosed spaces. Further, the above described bonding process can eliminate oxide to oxide bonding (e.g., for hybrid bonding) and/or the requirement on wafer surface conditions (e.g., surface roughness control), which can lead to lower manufacturing cost and error.

In some embodiments, solder bumps can be added to a bottom surface of the bonded structure (e.g., the die stack). In some embodiments, underfill can be applied to the bottom surface of the die stack.

FIG. 14is a block diagram illustrating a system that incorporates a semiconductor device in accordance with embodiments of the present technology. Any one of the semiconductor devices having the features described above with reference toFIGS. 2-13can be incorporated into any of a myriad of larger and/or more complex systems, a representative example of which is system1490shown schematically inFIG. 14. The system1490can include a processor1492, a memory1494(e.g., SRAM, DRAM, flash, and/or other memory devices), input/output devices1496, and/or other subsystems or components1498. The semiconductor assemblies, devices, and device packages described above with reference toFIGS. 2-13can be included in any of the elements shown inFIG. 14. The resulting system1490can be configured to perform any of a wide variety of suitable computing, processing, storage, sensing, imaging, and/or other functions. Accordingly, representative examples of the system1490include, without limitation, computers and/or other data processors, such as desktop computers, laptop computers, Internet appliances, hand-held devices (e.g., palm-top computers, wearable computers, cellular or mobile phones, personal digital assistants, music players, etc.), tablets, multi-processor systems, processor-based or programmable consumer electronics, network computers, and minicomputers. Additional representative examples of the system1490include lights, cameras, vehicles, etc. With regard to these and other examples, the system1490can be housed in a single unit or distributed over multiple interconnected units, e.g., through a communication network. The components of the system1490can accordingly include local and/or remote memory storage devices and any of a wide variety of suitable computer-readable media.

From the foregoing, it will be appreciated that specific embodiments of the present technology have been described herein for purposes of illustration, but that various modifications may be made without deviating from the disclosure. In addition, certain aspects of the disclosure described in the context of particular embodiments may be combined or eliminated in other embodiments. Further, while advantages associated with certain embodiments have been described in the context of those embodiments, other embodiments may also exhibit such advantages. Not all embodiments need necessarily exhibit such advantages to fall within the scope of the present disclosure. Accordingly, the disclosure and associated technology can encompass other embodiments not expressly shown or described herein.