Multiple-stage gate network having independent reference voltage sources

A circuit technique for eliminating history-dependent skew and distortion of signals as they propagate through multiple gate stages in critical timing paths. It has been discovered that spurious effects can be attributed to signal coupling between stages, and that such coupling may be reduced by providing separate threshold voltage supplies for the critical gates. Each of the first and second gate stages comprises first and second transistors having their respective emitters coupled to a common circuit point, a current source coupled to the common circuit point to provide current flow through the transistors, with the relative current flow through said transistors being determined by the relative voltage levels at the respective bases. The output signal is taken from the collector of one of the transistors. First and second threshold voltage sources are coupled to the respective bases of the second transistors of the first and second gate stages. The threshold voltage sources are isolated from one another such that current drawn from either results in substantially no change in the voltage delivered by the other. This circuit technique has applicability to configurations where the first and second gate stages are cascaded and to configurations where the gate stages are parallel stages in different branches of the signal path.

FIELD OF THE INVENTION 
The present invention relates generally to automatic test equipment used 
for testing integrated circuits, and more specifically to a technique for 
providing precise adjustable time delays. 
BACKGROUND OF THE INVENTION 
In the normal course of designing integrated circuits, one solves the 
problem of signal propagation delay by attempting to minimize such delay. 
To this end, the manufacturers of integrated circuits have developed 
smaller, thinner, and more densely packed structures, thereby achieving 
speeds of operation that could scarcely have been dreamed of a decade ago. 
By keeping the delay through any given gate stage small enough, the 
overall response time of the circuit may be kept below the predetermined 
design level. 
There are, however, certain applications where the "less-is-better" 
approach does not suffice. Rather, these applications require that gate 
delays be kept highly stable under a wide variety of conditions. An 
example is circuitry for deskewing electrical signals within automatic 
test equipment used for testing integrated circuits. 
Typical automatic test equipment applies a plurality of input signals to 
selected pins of a device under test ("DUT") which in response produces a 
plurality of output signals at other selected pins. The test equipment 
senses the output signals and analyzes them for their compliance with 
quality control standards. 
Under control of the test system computer and its programs, the test 
equipment can perform tests on a variety of integrated circuit devices. 
Because of the versatility of the test equipment, a particular input 
signal may be applied to a DUT pin over a number of different paths, and 
the output signals may follow a number of different paths from a DUT pin 
to the analysis circuitry. The resultant timing variations, commonly 
termed skew, must be corrected to assure the validity of the test being 
performed. 
A typical automatic test system has in excess of 100 pins, each with 
associated receivers and drivers. Thus, it is required to adjustably 
correct hundreds of timing paths. There have been developed programmable 
delay lines, typically hybrid devices having a data input and a signal 
input and output. A binary code applied to the data input results in a 
corresponding propagation delay between the signal input and the signal 
output. Typical resolution requirements are illustrated by the Fairchild 
Series 20 Test System which specifies that any input timing edge can be 
placed anywhere from the beginning of a cycle up to 20 ns before the end 
of the following cycle, in increments of 156 ps. 
As faster and faster test systems are designed, the resolution requirements 
become even more stringent. However attempts to provide programmable delay 
elements having a resolution at the level of 10 ps have been frustrated by 
apparently spurious timing fluctuations and signal distortions within the 
integrated circuit portion of the delay device. 
SUMMARY OF THE INVENTION 
The present invention provides a circuit technique for eliminating 
history-dependent skew and distortion of signals as they propagate through 
multiple gate stages in critical timing paths. 
Broadly, it has been discovered that spurious effects can be attributed to 
signal coupling between stages, and that such coupling may be reduced by 
providing separate threshold voltage supplies for the critical gates. In 
the preferred implementation, each of the first and second gate stages 
comprises first and second transistors having their respective emitters 
coupled to a common circuit point, a current source coupled to the common 
circuit point to provide current flow through the transistors, with the 
relative current flow through said transistors being determined by the 
relative voltage levels at the respective bases. The output signal is 
taken from the collector of one of the transistors, and exhibits a voltage 
change when current is steered from one transistor to the other. 
First and second threshold voltage sources are coupled to the respective 
bases of the second transistors of the first and second gate stages. The 
threshold voltage sources are isolated from one another such that current 
drawn from either results in substantially no change in the voltage 
delivered by the other. Thus, when the second transistor in one of the 
gates stages is turned on or off, the increment of current that flows from 
or to one threshold voltage supply to charge or discharge the active 
region of the base does not affect the voltage provided by the other 
threshold voltage supply. 
This circuit technique has applicability to configurations where the first 
and second gate stages are cascaded and to configurations where the gate 
stages are parallel stages in different branches of the signal path, which 
gate stages might be expected to undergo signal transitions within the 
same narrow time interval. The threshold voltage may be a nominally fixed 
voltage or a controlled variable voltage.

DESCRIPTION OF THE PREFERRED EMBODIMENTS 
General Circuit Operation and Structure 
The present invention may best be understood by reference to its operation 
when incorporated into certain critical timing paths within a solid state 
deskew element used in automatic test equipment. FIG. 1 is a logical 
schematic of such a deskew element 10. In its broadest sense, the 
operation of deskew element 10 is to take an incoming pulse at a 
differential input 12, delay it by a variable amount of time according to 
the digital code at a multi-bit data input 15, and present the delayed 
signal at a differential output 17. 
The present invention relates to techniques for maintaining very precise 
timing. While particular timing parameters will be described, it is to be 
understood that the present invention is not so limited. Deskew element 10 
is designed to take an incoming pulse of 5-ns width at a 20-ns repetition 
rate, and to provide a variable increment of delay in the range of 0-5.12 
ns from nominal in steps of approximately 10 ps. To this end, the deskew 
element has the capability of providing an overall delay of 8.2 ns, as 
will now be described. 
The main components of deskew element 10 are fine delay circuitry 20, 
coarse delay circuitry 22, latching circuitry 25, and a 7-bit 
digital/analog converter ("DAC") 30. Data input 15 has ten bits, seven 
bits of which (B0-B6) are communicated to the inputs of DAC 30; the 
remaining three bits (B7-B9) are communicated (as complementary pairs) to 
coarse delay circuitry 22. DAC 30 produces an analog voltage of 0.25-1.25 
volts corresponding to the 7-bit code at its input, and a voltage derived 
from this is communicated to fine delay circuitry 20. The particular 
construction of latching circuitry 25 and DAC 30 is not directly related 
to the present invention, and will not be described further. 
Fine delay circuitry 20 includes a differential receiver 32, first and 
second ramp generators 33 and 33', and a reconstruction (set/reset) latch 
35. Broadly, fine delay circuitry 20 takes the differential input pulses 
and splits the leading and trailing edges into ramp generators 33 and 33' 
which compare those edges with a threshold derived from the DAC output 
voltage. Ramp generators 33 and 33' comprise respective capacitors 37 and 
37' and respective comparators 38 and 38'. After the ramp voltages are 
sensed by comparators 38 and 38', the pulse is reconstructed by 
reconstruction latch 35. 
Edge timing in fine delay circuitry 20 is approximately 800 mv/ns, 
whereupon the 1-volt variation in the output voltage from DAC 30 provides 
up to approximately 1.25 ns of controlled fine delay variation. 
Latch 35 includes cross-coupled gates 40 and 41 which receive as set and 
reset inputs the signals from comparators 38 and 38'. The output from 
comparator 38 is also communicated to a first input of a gate 43. The 
respective outputs of gates 41 and 43 are communicated to a latch output 
gate 45, the differential outputs of which communicate to coarse delay 
circuitry 22 and also communicate via a feedback gate 47 to a second input 
of gate 43. 
The pulse, as reconstructed at the output of gate 45, is communicated to 
coarse delay circuitry 22. Coarse delay circuitry 22 includes a delay line 
50 comprising cascaded gate stages 50(1), 50(2), . . . and 50(7), the 
respective outputs of which also communicate to respective multiplexer 
output gates 52(1), 52(2), . . . and 52(7). (A dummy gate 50(8) ensures 
that the capacitance is the same at the outputs of all the gates in delay 
line 50.) The reconstructed pulse communicates to the input of gate 50(1), 
and also to a multiplexer output gate 52(0). The outputs of all output 
gates 52(0-7) are tied to an output buffer 55. Each gate in delay line 50 
produces a 1-ns delay, for a total of up to 7 ns of coarse delay, 
depending on which of output gates 52(0-7) is selected by bits B7-B9 of 
the data inputs. 
The preferred embodiment of the present invention is implemented in emitter 
coupled logic ("ECL"). Although the details of the circuitry will be 
described with reference to the circuit schematics of FIGS. 3A-8D, the 
basic features will be outlined at this point. In accordance with known 
practice, each gate stage includes a differential transistor pair having 
the transistors' emitters coupled to a common circuit point, and a current 
source coupled thereto. The transistors' collectors are resistively 
coupled to a supply voltage, and at least one of the transistors' 
collectors is coupled through an emitter follower to an output terminal. 
The relative current flow through the transistors (and hence the relative 
collector voltage) is determined by the relative voltages at the 
transistors' bases. 
For a differential input signal, the two components are communicated to the 
bases; for a singlesided signal, one base receives the signal and the 
other base is held at a threshold voltage. The threshold voltage may be a 
nominally fixed reference level (as in gates 40, 41, 43, and 45) or a 
controlled signal reference (as in comparators 38 and 38'). The emitter 
follower stages through which the output signals are coupled use constant 
current sources for their loads. 
Fine Delay Timing 
The operation of fine delay circuitry 20 may best be understood with 
reference to FIG. 2 which is the timing diagram showing the signals at 
nodes A-H in the circuitry. The nodes are defined as follows: 
A--input to comparator 38 
B--output from comparator 38 
C--input to comparator 38' 
D--output from comparator 38' 
E--output from gate 40 
F--output from gate 41 
G--output from gate 43 
H--output from gate 45 
I--output from gate 47 
For purposes of illustration, the input signal may be assumed to be a 5-ns 
wide pulse having differential components IN+ and IN-. In the discussion 
that follows, it will be assumed that each gate except feedback gate 47 
provides a fixed increment of delay, designated .delta., which is 
approximately 1 ns. Feedback gate 47 is characterized by a longer gate 
delay, designated .delta.', which is approximately 2 ns. 
The positive input signal IN+is communicated through differential input 
gate 32 to node A. Since the input gate has an emitter follower, the rise 
in IN+causes a rapid rise at node A, one gate delay later. However, the 
fall in IN+ does not result in a rapid fall at node A, but rather a more 
gradual fall which has a slope defined by the load current and the 
capacitor value. Thus, the fall at node A is linear with a fall time of 
approximately 1.5 ns. For purposes of illustration, it will be assumed 
that the voltage at node A becomes equal to the DAC voltage a time 
interval .DELTA. after the voltage at A begins to fall. 
Consider now the signal at node B. Comparator 38 introduces one gate delay 
as well as inversion. When A rises, B falls one gate delay later. B rises 
one gate delay after A falls to a level matching the voltage of DAC 30. 
The trailing (rising) edge of the signal at B is one of the two edges that 
is ultimately reconstructed into the delayed pulse. 
Similarly, the negative input signal IN- produces a signal at node C which 
has a leading (falling) edge having a slope defined by the constant 
current source and the capacitor, and a trailing (rising) edge that rises 
rapidly. As above, where the voltage at C reaches the DAC voltage after an 
interval .DELTA., the rising edge at node D occurs one gate delay later, 
and the trailing edge occurs one gate delay after C rises. The leading 
(rising) edge of the signal at D is the other edge that is ultimately 
reconstructed. 
Gates 40 and 41 define a set/reset latch whose state changes each time 
either B or D goes high. Thus, since it is the rising edges of the signals 
at B and D that are to be reconstructed, the latch has the effect of 
reconstructing the pulse. The signals at B and D follow different paths 
prior to being reconstructed at H. When D rises, F falls one gate delay 
later, and then H falls one more gate delay later, thereby reconstructing 
the leading edge of D (which corresponds to the delayed leading edge of 
the input signal). The signal at B follows a slightly different path prior 
to reaching to node H. Rather than go through the latch which would add an 
extra delay, a look-ahead path is utilized. The signal at B is propagated 
through gate 43, whereupon G rises one gate delay after B rises, and H 
rises one more gate delay later to reconstruct the trailing edge of B 
(which corresponds to the delayed trailing edge of the input signal). 
However, the rise in H is propagated through the feedback network 
(characterized by the longer gate delay) to I (one of the inputs of gate 
43) which causes G to fall. Thus, when B rises, G rises, but then falls a 
short time later because of the feedback. However, by that time, B has 
risen and has reset latch 35. F rises again and reinforces G so that by 
the time G falls, F has risen to keep H high. 
In this manner, the outputs at gate 45 are delayed relative to the 
differential input signal by a variable amount .DELTA. (in addition to 
four fixed gate delays). 
It will be appreciated that the paths through fine delay circuitry 20 and 
coarse delay circuitry 22 represent critical timing paths where the 
stability of delays must be maintained. Moreover, the pulse width must not 
be distorted on passage of the pulse through the circuitry. The techniques 
for maintaining stable timing may be understood by referring to the 
circuit schematics of FIGS. 3A-8D. 
Generation of Fixed Voltages 
In order that the understanding of the schematics be facilitated, and 
further in view of the fact that certain aspects of the present invention 
relate to the nominally fixed voltages and their characteristics, these 
voltages will be discussed first. 
The highest voltage in the circuit, designated V.sub.CC, is at ground. The 
lowest voltage in the circuit, designated V.sub.EE, is nominally 4.5 volts 
below V.sub.CC, although this can vary by as much as .+-.10%. 
A first set of voltages is referenced to V.sub.CC. These include V.sub.BB 1 
and L.sub.BB 1 which are 1.3 volts below V.sub.CC (that is, -1.3 volts), 
and V.sub.BB 2 and L.sub.BB 2 which are one diode drop lower than V.sub.BB 
1 and L.sub.BB 1 (that is, -2.1 volts). Signal swings relative to these 
voltages are 0.4 volts above for a high and 0.4 volts below for a low. 
A second set of voltages in the circuit are referenced relative to 
V.sub.EE. These include V.sub.CS A and V.sub.CS B which are 1.3 volts 
above V.sub.EE (nominally -3.2 volts), and V.sub.LD 1 and V.sub.LD 2 which 
are 1.5 volts above V.sub.EE. 
FIG. 3A is a circuit schematic illustrating the generation of the L.sub.BB 
1 voltage. For reasons to be discussed below, three separate isolated 
threshold voltage sources 80a, 80b, and 80c are used to provide 
corresponding (and nominally equal) voltages L.sub.BB 1A, L.sub.BB 1B, and 
L.sub.BB 1C. Referring, for example, to voltage source 80a, the level 
L.sub.BB 1 relative to V.sub.CC is determined by a dropping resistor 81 
and a current source 82 controlled by the voltage V.sub.CS relative to 
V.sub.EE. The L.sub.BB 1 voltage is provided at an emitter follower 83 
having a load current source 84 (also controlled b V.sub.CS) 
FIG. 3B is a circuit schematic illustrating the generation of the threshold 
voltage from DAC 30 as provided to comparators 38 and 38'. For reasons to 
be discussed below, separate isolated threshold voltage sources 87a and 
87b are used to provide corresponding (and nominally equal) voltages 
V.sub.RAMP 1 and V.sub.RAMP 2. The voltage DACOUT drives separate emitter 
followers 88a and 88b whose loads are respective current sources 90a and 
90b controlled by the voltage V.sub.LD 2. 
FIG. 3C is a circuit schematic illustrating the generation of the voltages 
V.sub.BB 1 and V.sub.BB 2 by a voltage source 95 and the voltages V.sub.BO 
1 and V.sub.BO 2 by a voltage source 97. These four voltages, like and 
L.sub.BB 1, are controlled by V.sub.CS. 
FIG. 4A is a simplified circuit schematic of a band-gap regulator 100 used 
to generate the V.sub.CS voltage which, as discussed above, provides a 
1.3-volt interval above V.sub.EE. The basic operation of band-gap 
regulator 100 is to provide an output voltage V.sub.O having a 
substantially zero temperature coefficient, which is achieved by balancing 
the negative temperature coefficient of a base-emitter junction with the 
positive temperature coefficient of a resistive voltage drop. V.sub.0 is 
provided at a node 102 which is coupled to the emitter of a transistor 
103. Band-gap regulator further includes a regulating transistor 105, a 
current source pair of transistors 107 (Q1) and 110 (Q2), and resistors 
112 and 113 having respective values R.sub.1 and R.sub.2. Transistors 107 
and 110 are in a "current mirror" configuration, but carry different 
currents due to the fact that the emitter of transistor 110 is coupled 
directly to V.sub.EE while the emitter of transistor 107 is coupled to 
V.sub.EE through a resistor 113. A node 120, which is the commonly coupled 
collector of transistor 107 and base of transistor 105 is coupled to node 
102 through resistor 112. Node 102 (first output terminal) is at a voltage 
V.sub.O, node 120 at a voltage V.sub.1, and the emitter of transistor 107 
at a voltage V.sub.2, all voltages being defined relative to V.sub.EE 
(second output terminal). 
The voltage V.sub.0 is the sum of the voltage drop across resistor 112 and 
the voltage V.sub.1 across the base-emitter junction of transistor 105. 
Also, assuming a negligible amount of base current into transistor 105, 
the voltage drop across resistor 112 is related to the voltage drop across 
resistor 113 by the ratio of the resistor values. This may be expressed 
mathematically as follows: 
EQU V.sub.0 =V.sub.1 +(R.sub.1 /R.sub.2) V.sub.2 (Eq. 1) 
The voltage V.sub.2 may be determined from the diode equation and is given 
in terms of the ratio of the currents through transistors 107 and 110 as 
follows: 
EQU V.sub.2 =(kT/q) ln (J.sub.2 /J.sub.1) (Eq. 2) 
where 
KT/q is the thermal voltage 26 mv for 300.degree. K., and 
J.sub.1 and J.sub.2 are the current densities through transistors 107 and 
110. 
For V.sub.1 =0.7 volts, it is found that (dV.sub.1 /dT)=-2.0 mv/.degree.C. 
Also, for (J.sub.2 /J.sub.1)=10, it is found that V.sub.2 =60 mv at 
300.degree. C. and (dV.sub.2 /dT)=+0.2 mv/.degree.C. 
Differentiating Equation 1 with respect to T and setting (dV.sub.0 /dT)=0 
leads to the requirement that (R.sub.1 /R.sub.2)=10. Substituting into 
Equation 1 gives V.sub.0 =0.7+(10)(0.060) volts=1.3 volts, the "band-gap" 
voltage with the desired zero temperature coefficient. 
While the above represents a simplified explanation, it is nevertheless 
substantially correct. FIG. 4B shows the preferred implementation of 
band-gap regulator 100 with reference numerals corresponding to those in 
FIG. 4A being used where appropriate. The voltage at the base of 
transistor 103 is communicated to output cells 130a and 130b, more 
specifically to the respective bases of transistors 132a and 132b therein. 
The emitters of transistors 132a and 132b provide the desired output 
voltages and V.sub.CSB. So long as transistors 132a and 132b and 
transistor 103 have the same temperature characteristics for their 
base-emitter junctions, the voltages V.sub.CS A and V.sub.CS B will have 
the same zero temperature coefficient as the voltage V.sub.O at node 102. 
Output cells 130a and 130b also contain compensating networks to provide 
second-order correction. 
FIG. 5A is a simplified circuit schematic of a band-gap regulator 150 used 
to generate the voltages V.sub.LD 1A, V.sub.LD 1B and V.sub.LD 2, 
designated generically as V.sub.LD. As will be described below, the 
V.sub.LD voltages are required to have a non-zero, but well defined, 
temperature coefficient in order to provide load current sources having 
particular temperature dependence. Primed reference numerals will be used 
for circuit components corresponding to those in FIG. 4A. 
Band-gap regulator 150 differs from band-gap regulator 100 in FIG. 4A by 
the provision of a resistor 155 having a value R.sub.3 between node 120' 
and V.sub.EE. The dominant temperature characteristic of the circuit is 
provided by resistor 155. The above analysis follows through with certain 
modifications. More particularly, the voltage drop across resistor 112' is 
no longer related to the voltage drop across resistor 113' by the simple 
ratio of the resistor values, since resistor 155 provides an additional 
current path. Rather, Equation 1 is modified to account for this as 
follows: 
##EQU1## 
This equation may be differentiated with respect to temperature, and the 
temperature coefficient of V.sub.0 is given as follows: 
##EQU2## 
If the desired V.sub.0 and dV.sub.0 /dT are known, Equations 3 and 4 can be 
solved for the required resistor ratios. For example, for V.sub.1 =0.8 
volts, V.sub.2 =0.06 volts, dV.sub.1 /dT=-2 mv/.degree.C. and dV.sub.2 
/dT=+0.2 mv/.degree.C., and further assuming a desired value of V.sub.0 
=1.5 volts and a desired temperature coefficient of -0.6 mv/.degree.C., 
the equations to be solved may be written as follows: 
##EQU3## 
Solving these equations yields the resistor ratios (R.sub.1 /R.sub.3)=0.2 
and (R.sub.1 /R.sub.2)=9. 
This discussion is somewhat idealized in that the temperature coefficient 
of V.sub.2 does not remain precisely constant at 0.2 mv/.degree.C. when 
V.sub.O is no longer temperature independent. Accordingly, rather than the 
simple set of linear equations, transcendental equations would have to be 
solved, as for example by means of a circuit simulation computer program. 
However, the basic discussion above adequately illustrates the behavior 
and general considerations involved in designing the circuit. FIGS. 5B and 
5C are circuit schematics of band-gap regulator circuits 157 and 158 for 
generating the V.sub.LD voltages. 
General Gate Structure 
FIGS. 6A-B are circuit schematics illustrating input receiver 32, 
capacitors 37 and 37', and comparators 38 and 38' in fine delay circuitry 
20. FIGS. 7A-E are circuit schematics illustrating gates 40, 41, 43, 45, 
and 47 in fine delay circuitry 20. FIGS. 8A-D are circuit schematics 
illustrating gate stage 50(1), multiplexer output gates 52(0-1), and 
output buffer 55 in coarse delay circuitry 22. 
The structure of the gates may be understood with initial reference to gate 
50(1) shown in FIG. 8A. Gate 50(1) comprises a differential pair having 
emitter-coupled transistors 160 and 162, a current source 165, a collector 
network 167, and emitter followers 170 and 171. Collector network 167 
includes the series combination of a pair of cross-coupled diodes 172 and 
173 and a pair of resistors 177 and 178. 
In accordance with prior known practice, gate 50(1) (as well as the other 
gates in the deskew element) is temperature-compensated to provide signal 
levels that do not vary with temperature. To this end, current source 165 
is controlled by a voltage (V.sub.CS) that is stable with respect to 
temperature, and the diode pair is included so that its temperature 
characteristics compensate for the temperature dependence of the 
base-emitter junction voltage of the transistors in emitter followers 170 
and 171. 
The remaining discussion deals with specific circuit techniques for 
stabilizing the timing of signals in critical timing paths. These will be 
described in connection with various gates shown in the circuit schematics 
of FIGS. 6A-8D. 
Isolated Voltage References 
As discussed above in connection with the timing diagram of FIG. 2, the 
critical timing paths are A-B-G-H and C-D-F-H. Thus, the trailing edge of 
IN+has to propagate through cascaded stages 38, 43, and 45 while the 
leading edge of IN- has to propagate through cascaded stages 38, 41, and 
50(0). 
It has been discovered that spurious timing effects can arise from signal 
coupling between stages, and more particularly from coupling via the 
voltage supply that defines the threshold levels for such stages. Such 
coupling has been found to occur between cascaded gate stages, and also 
between parallel stages which are expected to undergo signal transitions 
within the same narrow time interval. 
With reference to FIGS. 7C-D, consider cascaded gate stages 43 and 45 
through which the signal DP2 (from comparator 38) must propagate. Gate 43 
includes a differential pair having first and second transistors 182 and 
183, the emitters of which are coupled to a common circuit point 184, and 
a current source 185 coupled to circuit point 184. The collectors of 
transistors 182 and 183 are coupled via a collector network 187. The 
collector of transistor 183 is communicated to an emitter follower 188, 
the output of which is communicated to the input of gate 45. In a similar 
fashion, gate 45 includes a differential pair having first and second 
transistors 190 and 192 and a current source 195. The input signal DP2 is 
communicated to the base of transistor 182; the output from gate 43 is 
communicated to the base of transistor 190. 
The bases of respective second transistors 183 and 192 are held at voltage 
L.sub.BB 1 (nominally -1.3 volts). However, in accordance with the desire 
to eliminate signal coupling, the threshold reference voltages supplied to 
the bases of transistors 183 and 192 are provided by separate isolated 
voltage sources 80a and 80c (FIG. 3A) for V.sub.BB 1A and V.sub.BB 1C. 
Similarly, with reference to FIGS. 7B and 7D, since gates 41 and 45 are 
cascaded, gate 41 is thresholded with V.sub.BB 1B as provided by voltage 
source 80b (FIG. 3A). 
The use of isolated threshold voltage supplies has the effect of 
eliminating spurious coupling between stages. The significance of this is 
best understood by considering the hypothetical operation of a circuit 
having cascaded gate stages that are thresholded by the same supply. 
Basically, when the input signal to the first transistor goes low, the 
second transistor in the pair is turned on, and an extra increment of 
charge (q.sub.F) is drawn from the threshold voltage supply in order to 
charge up the active region in the base of the transistor. The extra 
current draw causes a small dip in the threshold voltage that is sensed in 
the second gate stage. This dip persists beyond the propagation delay 
time, so that the output signal from the first stage is sensed at the 
second gate against a different threshold. Thus, for example, if the 
voltage dips from -1.3 volts to -1.4 volts, the timing would be disturbed 
by an increment that corresponds to the time difference between the output 
signal passing through -1.3 volts and -1.4 volts. Similarly, when the 
input signal to the first transistor goes high, the second transistor in 
the pair is turned off, and current flows into the threshold voltage 
supply. This causes an increase in the threshold voltage, with a 
corresponding increment in the timing. Depending on the relative sense of 
the output from the first gate stage (inverting or non-inverting), both 
edges will be subjected to delay or advancement. This delay or advancement 
is cumulative as the signal passes through several cascaded stages. 
However, the problem of signal coupling is not merely one of absolute 
delays, since other signals in the system can cause only one edge of the 
signal to be affected. Moreover, a system without isolated threshold 
supplies can suffer from problems where the trailing edge of the signal in 
the first stage has its timing disturbed by the switching caused by the 
leading edge of the same signal in the second (or later) stage. 
As alluded to above, an analogous problem is present in parallel stages 
such as comparators 38 and 38'. In this case, both comparators are 
conditioned, in effect, by the same analog voltage from DAC 30. Were a 
single voltage derived from the DAC output (designated DACOUT) used, the 
initial rapid switching at node A would cause a change in the voltage due 
to the extra increment of current, and this would upset the timing at 
which the comparison of the sloping edge at node C occurred. Similarly, 
when the voltage at node C rose rapidly at the trailing edge of the pulse, 
the threshold voltage would change, and adversely affect the critical 
timing on the sloping edge of the pulse at node A. This is not a problem 
of cascaded stages, but rather is a problem of parallel stages where 
cross-coupling occurs through the common threshold voltage. As can be seen 
in FIG. 6B, the present invention overcomes this problem by providing 
comparators 38 and 38' with separate commonly derived voltages V.sub.RAMP 
1 and V.sub.RAMP 2 generated by isolated supplies 87a and 87b (FIG. 3B). 
Thus, by using isolated threshold voltage sources, unpredictability and 
signal dependence are eliminated so that signals may propagate through 
cascaded or parallel gate stages without signal history dependent skew and 
distortion. 
Balanced Collector Network 
As can be seen in FIGS. 6A-8D, the temperature compensating networks are of 
a special symmetric configuration. For example, in gate 50(1) in FIG. 8A, 
the series resistance with the diode pair (172 and 173) is split between 
two resistors (177 and 178). 
It has been discovered that significant signal distortion and skew can be 
attributed to unbalanced capacitance at the collector nodes. This 
distortion and skew may be avoided by the present configuration which 
provides a symmetric collector network so that the capacitance is balanced 
at both collector nodes. 
The significance of this is best understood by considering a hypothetical 
structure in which the load was not so balanced. In such a case, the 
signal on one collector would encounter a different capacitance than that 
on the other, which would mean that the absolute delay would be different 
for the inverting and non-inverting outputs. In a differential gate this 
would cause some uncertainty in the transitions on succeeding gate stages. 
This would present a stability problem, and also a pulse integrity 
problem, since each gate stage could have the effect of shortening or 
lengthening the pulse passing through it. 
While this balanced load configuration is used in almost all the other 
differential pair gates in the circuitry, the benefits are most critical 
in delay gates 50(1-7). This is because each stage must be noninverting so 
that the output signal may be taken off any stage, as selected by the 
three high order data bits (B7-B9). It is therefore impossible to cancel 
out effects of the imbalance by switching from positive to negative 
between stages. Even a relatively small disparity, as for example 0.05 ns, 
could result in a cumulative distortion of 0.4 ns arising solely out of 
the passage through gates 50(1-7). 
An additional problem with the hypothetical unbalanced node structure 
relates to the temperature dependence of the delays. As will be described 
in more detail below, it has been discovered that the increase in gate 
delay as a function of temperature can be offset by providing a current 
source in the emitter follower having particular temperature 
characteristics. In the event that the rise and fall characteristics were 
different for the two collector nodes, the two emitter followers would 
have to be configured differently, which would add an undesirable degree 
of complication to the circuit. 
Temperature-Compensating Load Current 
As can be seen in FIGS. 6A-8D, the output of each gate stage includes an 
emitter follower which comprises a transistor and a current source 
(controlled by one of the V.sub.LD voltages) as the emitter load. It has 
been discovered that it is possible to maintain timing that is stable with 
respect to temperature variations by suitable configuration of load 
current source temperature coefficient. This is to be contrasted to the 
standard compensated current sources within the gates which have a 
controlling voltage (V.sub.CS) which is characterized by a zero 
temperature coefficient. 
Referring to FIG. 6A for a specific example, node A at the output of 
differential receiver 32 is perhaps the most sensitive node in the whole 
system. Node A is driven by an emitter follower comprising a transistor 
220 and a current source 222. Current source 222 includes a transistor 225 
and a resistor 227 in a standard current source configuration. The base of 
transistor 225 is controlled by one of the V.sub.LD voltages, namely 
V.sub.LD 2. 
The delay through a gate stage will normally increase with respect to 
temperature due to a decrease in the transistors' transconductance. It has 
been discovered that this increase can be offset by providing a load 
current having a particular temperature dependence. Increasing the load 
current has the effect of slowing down the rise time (increased load) and 
speeding up the fall time (faster pull down). While these effects offset 
one another, the speeding of the fall is found to predominate, so that the 
delay actually decreases with increasing load (at least when the load 
current is considerably less than the gate current). Thus, the 
temperature-dependence of the delay may be offset by providing suitably 
tailored load current source. The standard compensated current sources 
(controlled by V.sub.CS) within the gates are not suitable, since they 
over-correct. A source having a reduced temperature coefficient is needed. 
Consider a specific case where analysis (as for example a computer 
simulation) shows that the temperature dependence required to stabilize 
delay is (1/I)(dI/dT)=+0.06%/.degree.C. The required temperature 
dependence of the control voltage may be found as follows. 
The voltage V.sub.LD is the sum of the voltage V.sub.BE across the 
base-emitter junction of transistor 225 and the voltage drop IR across 
resistor 227. 
EQU V.sub.LD =V.sub.BE +IR (Eq. 6) 
Differentiating Equation 6 with respect to temperature gives: 
##EQU4## 
The base-emitter voltage of transistor 225 has a negative temperature 
coefficient while resistor 227 has a positive temperature coefficient. For 
IR=0.7 volts, (dV.sub.BE /dT)=-1.4 mv/.degree.C., 
(1/I)(dI/dT)=+0.06%/.degree.C., and (1/R)(dR/dT)=+0.06%/.degree.C. 
Equation 6 leads to a value 
##EQU5## 
A voltage source suitable for providing such a temperature coefficient was 
discussed above in connection with the description of band-gap regulators 
157 and 158 for generating the V.sub.LD voltages (FIGS. 5A-C). 
The constant current loads are also important in the coarse delay stages 
since the capacitance at the output is high. Referring to FIG. 8A, the 
load currents powering the outputs of gates 50(1-7) and the common output 
of gates 52(0-7) are controlled b V.sub.LD 1B. To give an indication of 
the significance of choosing the current source temperature coefficient 
properly, if the standard compensated current source (controlled by 
V.sub.CS) were used, the resulting increase in current with temperature 
would result in approximately a 30 ps/.degree.C. increase in speed at the 
multiplexer output. Such a characteristic is clearly intolerable in a 
circuit where timing delays are maintained stable with respect to other 
parameters at the picosecond level. 
In summary it can be seen that the present invention provides a circuit 
technique for establishing and maintaining extremely precise and 
reproducible delay increments. While the above description and 
illustration provide a full and complete disclosure of the preferred 
embodiment of the invention, alternate constructions, modifications, and 
equivalents may be employed without departing from the true spirit and 
scope of the present invention. Accordingly, the scope of the present 
invention is to be determined by the appended claims.