Accuracy power detection unit

Techniques are disclosed relating to radio frequency (RF) power detection. In one embodiment, a power detection unit is disclosed that includes a multiplier circuit configured to receive a first voltage of a voltage differential signal at gates of a first transistor pair and a second voltage of the voltage differential signal at gates of a second transistor pair. The first multiplier is configured to output a current that varies proportionally to a square of a voltage difference between the first and second voltages. In some embodiments, sources of the first transistor pair are coupled to sources of the second transistor pair, and the sources of the second transistor pair are coupled together. In some embodiments, the power detection unit is configured to compensate for mismatched transistors by applying offset voltages to bodies of transistors in the first and second transistor pairs.

BACKGROUND

1. Technical Field

This disclosure relates generally to processing radio frequency (RF) signals, and, more specifically, to RF power detection.

2. Description of the Related Art

RF circuits typically perform a variety of operations to process a received signal. Such operations may include filtering the signal, demodulating it, sampling it, etc. In order to perform some of these operations, various circuits in the receiver chain may require that the RF signal have a signal strength within a particular range (e.g., a range of 60-80 dB). Often, however, an RF signal is too weak by the time it arrives at the receiver. To account for this, the receiver may attempt to amplify the signal before processing it further.

In many instances, RF circuits employ a feedback loop in which an incoming signal passes through an amplifier and then a power detector, which measures the signal's power. If the signal strength is too high or too low, the RF circuit adjusts the gain of amplifier accordingly. This form of feedback loop is commonly referred to as an automatic gain control (AGC) system.

SUMMARY OF EMBODIMENTS

The present disclosure describes structures and methods for improving the accuracy of multiplier circuits and power detection circuits.

In one embodiment, a power detection unit is disclosed. The power detection unit includes a multiplier circuit configured to receive a first voltage of a voltage differential signal at gates of a first transistor pair and a second voltage of the voltage differential signal at gates of a second transistor pair. The multiplier circuit is configured to output a current that varies proportionally to a square of a voltage difference between the first and second voltages. In such an embodiment, sources of the first transistor pair are coupled to sources of the second transistor pair, and the sources of the second transistor pair are coupled together.

In another embodiment, power detection unit is disclosed. The power detection unit includes a multiplier circuit configured to receive a first voltage of a voltage differential signal at gates of a first transistor pair and a second voltage of the voltage differential signal at gates of a second transistor pair. The multiplier circuit is configured to output a current that varies proportionally to a square of a voltage difference between the first and second voltages. The power detection unit is configured to adjust a threshold voltage of a transistor in the first transistor pair and a threshold voltage of a transistor in the second transistor pair.

In still another embodiment, a method is disclosed. The method includes providing positive and negative voltage differential signals to gates of first and second transistor pairs in a multiplier circuit. The multiplier circuit is configured to output a current that varies proportionally to a square of a voltage difference between the gates of the first transistor pair and the gates of the second transistor pair. The method further includes determining whether the multiplier circuit produces the same current in response to the positive and negative voltage differential signals. The method further includes applying offset voltages to a body of a transistor in the first transistor pair and a body of a transistor in the second transistor pair based on the determining.

DETAILED DESCRIPTION

The present disclosure describes embodiments of a power detection unit and embodiments of circuitry, which may be included within such a unit. As will be described below, the accuracy of the power detection unit may be affected by various factors, which can reduce performance of the unit. To account for such factors, the power detection unit, in various embodiments, may employ any of variety of techniques such as described below. It is noted that, while certain techniques are described within the context of power detection, such techniques may also be applicable to other applications in some embodiments.

Turning now toFIG. 1, a block diagram of an RF circuit100is depicted. RF circuit100in one embodiment of an automatic gain control (AGC) system that is configured to amplify a received RF input signal102based on its strength (i.e., power). As shown, RF circuit100includes an adjustable amplifier110, power detection unit120, and a control unit130. RF circuit100may be used in various applications such as television receivers, cellular phones, modems, network devices, satellite radios, etc. In some embodiments, RF circuit100may be used in wireless devices; in other embodiments, RF circuit100may be used in wired devices. In short, RF circuit100may be used in any suitable application.

In the illustrated embodiment, RF circuit100provides an incoming RF signal102to adjustable amplifier110to produce an amplified output signal104. In one embodiment, power detection unit120measures the power of signal104and indicates the result to control unit130. Control unit130(which may be implement using a microcontroller, in some embodiments) is configured to then adjust the gain of amplifier110so that the amplified output signal104falls within a desired range for circuit100. Accordingly, control unit130may increase or decrease the gain of amplifier110depending on whether signal104is too strong or too weak, respectively. In various embodiments, the amplified output signal104may then be provided to additional circuitry (not shown) in a receiver chain for further processing.

In many instances, the accuracy of power detection unit120is important for ensuring that signal102is amplified appropriately. If power detection unit120were to have a large offset error, amplifier110might over amplify signal102causing saturation problems or under amplify signal102making it too weak to process. As will be described next in conjunction withFIG. 2, in various embodiments, power detection unit120may measure the power of signal104by using one or more multiplier circuits that are configured to perform a squaring operation (since the power of a signal varies proportional to the square of the signal's voltage as defined by the combination of Joule's law and Ohm's law). In many instances, the accuracy of power detection unit120is dependent on the accuracy of its multipliers. In various embodiments described below, power detection unit120may employ various techniques to improve their accuracy.

Turning now toFIG. 2, one embodiment of power detection unit120is depicted. In the illustrated embodiment, power detection unit120includes multipliers210A and210B, current sources216A and216B, a comparison unit220, and an output offset unit250. In some embodiments, power detection unit120may include additional multipliers210, current sources216, comparison units220, and/or output offset units250.

Multiplier210A, in one embodiment, is configured to square the voltage of a signal (such as RF signal104, in one embodiment) to determine its power. In the illustrated embodiment, multiplier210A receives the signal as a voltage differential signal202(a signal represented by the difference between voltages Vin+and Vin−), and produces a corresponding current signal Iin212that varies proportionally to the square of the voltage of signal202such that Iin≈(Vin+−Vin−)2. An example illustrating this relationship is described in further detail below in conjunction withFIG. 4.

Multiplier210B, in one embodiment, is configured to generate a reference signal for comparison with the signal produced by multiplier210A. In the illustrated embodiment, multiplier210B receives a voltage reference signal as a differential voltage signal204(again, the signal represented by the difference between voltages VRef+and VRef−) and produces a corresponding reference current signal IRef214that varies proportionally to the square of the voltage of signal204such that IRef≈(VRef+−VRef−)2.

In the illustrated embodiment, current sources216are used to shift the respective input signal independent DC currents212and214to prepare them for comparison within comparison unit220.

Comparison unit220, in one embodiment, is configured to compare signals212and214and to generate a corresponding output signal242(i.e., a comparison indication) for control unit130. In the illustrated embodiment, signals212and214pass through respective current-to-voltage converters230A and230B to produce voltages comparable by voltage comparator240(in other embodiments, a current comparator may be used instead). In various embodiments, converters230produce voltages based on initial respective offset voltages (shown as VOffset222and VOffset224; as will be described below, these reference voltages may be adjusted (e.g., using output offset unit250) to compensate for when multipliers210produce different currents for the same input). After converters230have produced corresponding voltages, comparator240compares the voltages and generates a corresponding output signal242for control unit130. Accordingly, in one embodiment, comparator240may output a voltage representative of a logical one for signal242if the voltage produced from current212is greater than the voltage produced from current214, and a logical zero for signal242otherwise.

In some instances, multipliers210may produce a less than ideal square function, which can affect the accuracy of power detection unit120. For example, a multiplier210may produce a square function that has additional factors, which introduce non-linearity into the output current such as V3, V4, and V5factors. A multiplier210may also produce a square that is asymmetric (such as described in conjunction withFIG. 4). Both of these problems may be caused by mismatches of transistors (e.g., caused by impurities in the silicon, variances in the manufacturing of the multipliers210, etc.), problems with the circuitry that provides the input signals202and204for multipliers210, etc. In various embodiments, multipliers210may include circuitry (or be coupled to circuitry) that is configured to correct the square function (i.e., make it closer to ideal) such as described below in conjunction withFIGS. 2-6.

Another problem is that multipliers210may produce near-ideal square functions, but produce slightly different currents given the same input signal, which also affects the accuracy of power detection unit120. In the illustrated embodiment, output offset unit250is configured to change voltage224to cause converter230B change the DC offset of the voltage provided to comparator240(and, thus, the output offset of multiplier210B) in order to compensate for the difference in output currents. Output offset unit250is described in further detail below in conjunction withFIGS. 7 and 8.

Turning now toFIG. 3A, one embodiment of a multiplier210is depicted. In the illustrated embodiment, multiplier210includes capacitors310A and310B, transistors320A-D, current source330, and DC input unit340, which, in turn, includes current source342, transistors344A and344B, resistors346A1-B2, and a ground reference348. As shown, capacitor310A is coupled to the gates of transistors320A and320C, which form a first transistor pair. Capacitor310B is coupled to the gates of transistors320B and320D, which form a second transistor pair. The drains and bodies of transistors320A and320B, in turn, are coupled respectively to current source330and ground reference334A. The sources of transistors320A and320B are coupled via line336to sources of transistors320C and320D. The drains and bodies of transistors320C and320D, in turn, are respectively coupled to ground reference334B and voltage source VDD. In one embodiment, transistors320A and320B are N-type metal-oxide-semiconductor field-effect transistors (nMOSFETs) and transistors320C and320D P-type MOSFETS (pMOSFETS).

In the illustrated embodiment, multiplier210receives voltages302A and302B of a voltage differential signal (e.g., signal202or signal204) at capacitors310A and310B, which high-pass filter the signal to remove its DC component and leave only its AC component when it arrives at the gates of transistors320. The DC component at the gates of transistors320is supplied by DC input unit340. These DC and AC components change the gate-to-source voltages of transistors320causing them to source (i.e., pull) current from current source330. The remaining current from current source330, which does not pass through transistors320, becomes the output current304of multiplier circuit210shown as Iout. As discussed above, multiplier210is configured to vary the current Ioutproportionally to the square of the voltage difference between voltages302A and302B.

In some instances, transistors320A and320B may be mismatched relative to transistors320C and320D such that a body effect would normally (i.e., without the benefit of line336) introduce unwanted nonlinearity into Ioutsuch as V3, V4, V5factors. A mismatch may occur, for example, if transistor320A has a lower threshold voltage than the threshold voltage of transistor320C. One approach for canceling out this nonlinearity is to couple to the bodies of transistors320A and320B to their respective sources, which reduces their body-to-source voltages. A problem with this approach is that it also increases the parasitic capacitances of transistors320A and320B, which can reduce RF performance. A better approach is to couple the sources of transistors320via line336as shown in the illustrated embodiment. In many instances, the insertion of line336can reduce the presence of nonlinearity without compromising RF performance.

In some instances, the multiplier210may still produce a square function that is asymmetric due to the presence of offsets. These offsets may be introduced by the circuitry providing signals302, a mismatch of transistors320A and320B, a mismatch of transistors320C and320D, etc. In some embodiments, multiplier210may further include a threshold-voltage calibration unit350to compensate for these problems such as described next.

Turning now toFIG. 3B, another embodiment of a multiplier210is depicted. In the illustrated embodiment, multiplier210includes the same elements302-348as shown inFIG. 3A, except that the bodies of transistors320C and320D are no longer coupled to a voltage source VDDand, instead, are coupled to a calibration unit350via lines352and354. As will be described in conjunction withFIGS. 4-6, in various embodiments, calibration unit350is configured to apply offset voltages (i.e., different voltages) to the bodies (i.e., back gates) of transistors320C and320D via lines352and354to change their respective threshold voltages. By changing the threshold voltages, calibration unit350is configured to compensate for unwanted DC offsets, which can produce an asymmetric squaring function such as described next withFIG. 4.

Turning now toFIG. 4, a graph400illustrating to examples of two possible transfer functions402and404of a multiplier210is depicted. As discussed above, multiplier210may receive a voltage input (or differential voltage input) shown within the range of −300 mV to 300 mV, in the illustrated embodiment. Multiplier210may then produce a corresponding current shown within the range of 10 to 35 μA, in the illustrated embodiment. Since a square function is parabolic function that produces the same output for a given input regardless of its sign, the ideal (i.e., correct) transfer function for a multiplier210is a squaring function centered around the 0V origin such as transfer function402. Transfer function402illustrates this as it has the same output current (e.g., 24 μA) regardless of a given input's sign (e.g., −200 mV vs. 200 mV). Unfortunately, multiplier210may, in some instances, produce an asymmetric (i.e., non-ideal) squaring function such as transfer function404. Here, transfer function404is shifted by a negative DC offset of 30 mV. As a result, a −200 mV input voltage produces 20 μA current while a 200 mV input voltage produces a 26 μA current. In various embodiments, calibration unit350may be configured to detect this shift and apply an appropriate set of offset voltages to compensate for it.

Turning now toFIG. 5, a flow chart of a method500for calibrating transistors in a multiplier circuit is depicted. Method500is one embodiment of a method that may be performed by a circuit that includes a multiplier circuits such as power detection unit120or a circuit that is included within a multiplier circuit such as calibration unit350. In some embodiments, method500may be performed as part of an initial calibration for a circuit (such as during the circuit's startup, during testing of the circuit by automated testing equipment (ATE), etc.). In many instances, performance of method500can improve the accuracy of a multiplier circuit.

In step510, signals having positive and negative voltages (e.g., a differential signal having a voltage of 200 mV and a differential signal having a voltage of −200 mV such as described withFIG. 4) are provided to gates of a multiplier circuit (e.g., as voltages302at gates of transistors320) to cause the multiplier circuit output corresponding currents Iout.

In step520, the output currents (e.g., the 20 μA current and the 26 μA current described above) are measured to determine whether the multiplier circuit produces the same current in response to both signals—thus, indicating that the multiplier has an ideal or non-ideal transfer function. In some embodiments, step520may include measuring the currents by using an analog-to-digital converter (ADC) as shown in substep522. In one embodiment, this ADC may be located within calibration unit350(e.g., within control unit670described below). In other embodiments, this ADC may be located elsewhere within multiplier210or RF circuit100. In other embodiments, step520may include usage of an array of comparators to measure the currents.

In step530, offset voltages are applied (e.g., by a calibration unit350) to bodies of transistors (e.g., transistors320C and320D) of the multiplier based on the determination in step520. In some embodiments, the amount of offset voltages may be selected in substep532based on the currents measured by an ADC in step522. For example, greater offset voltages may be selected if the measured currents differ by a significant amount. Alternatively, step530may also include not applying offset voltages (in other words, applying the same voltage) if the currents are not different or have negligible differences within permissible tolerances that do not heavily impact the accuracy of the multiplier. For example, in one embodiment, a multiplier210is considered to produce an ideal transfer function if the input referred offset voltage for the multiplier is within +/−1 mV of 0V.

As will be described next, in one embodiment, calibration unit350may be configured to generate the offset voltages (e.g., during step530) by passing a current through a resistor ladder that includes a plurality of resistors coupled together in series. Calibration unit350may select various ones of the resistors to select a desired offset voltage. In some embodiments, calibration unit350is further configured to change the generated offset voltage of a selected resistor by coupling a resistor in parallel with one of the plurality of resistors in the resistor ladder.

Turning now toFIG. 6, one embodiment of calibration unit350is depicted. In the illustrated embodiment, calibration unit350includes current sources610A and610B, resistors620A-F (which are coupled together in series and may collectively be referred to herein as a “resistor ladder”), transistors630A-F, transistors640AD, and a voltage reference650, transistors660A and660B, and resistors662A and662B. Calibration unit350also includes a control unit670to manage operation of unit350. In some embodiments, calibration unit350may include additional resistors620and transistors630.

As discussed above, in various embodiments, calibration unit350is configured to apply offset voltages to the bodies of transistors320C and320D. In the illustrated embodiment, calibration unit350generates the voltages by passing a current from current source610A through resistors620. The voltages are generated around a common-mode voltage Vcmreceived from reference650. Calibration unit350then controls which voltages are selected by switching on or off transistors630. Calibration unit350then routes the selected voltages out to lines352and354by using transistors640. For example, calibration unit350may select the voltage created by the voltage drop across resistor620A to by activating transistor630A. Calibration unit350may then route the voltage to line354by activating transistor640B.

In the illustrated embodiment, calibration unit350is configured to further control the selection of offset voltages by using transistors660A and660B to couple one or both of resistors662in parallel with resistors620C and620D, respectively. By doing so, calibration unit350is able to reduce the voltage drop across resistors620C and620D (e.g., by a half when resistors662and620have the same resistance). Thus, if a particular desired offset voltage falls between a pair of voltages selectable by using transistors630(e.g., between 30 mV and 35 mV), calibration unit350can couple a resistor662to change the voltage so that it falls within the desired range (e.g., 32.5 mV).

In one embodiment, control unit670is configured to determine whether offset voltages are needed and to control the selection of offset voltages using transistors630,640, and660. Thus, in some embodiments, control unit670may perform (or facilitate performance of) method500described above. Accordingly, in some embodiments, control unit670is configured to select the appropriate pair of offset voltages based on the difference in the produced currents. In other embodiments, however, control unit670may be configured to test multiple pairs of offset voltages until it can determine the best pair based on trial-and-error. In both instances, control unit670may need to apply the same pair of offset voltages twice to test both arrangements of the voltages (i.e., the arrangement in which a first voltage and a second voltage are applied respectively to transistors320C and320D, and the arrangement in which the second voltage and the first voltage are applied respectively to transistors320C and320D).

While calibration unit350may be able to correct a non-ideal transfer function of a multiplier210, a pair of multipliers210may still produce different currents relative to one another given the same input. The method described next, in many instances, is able to account for this additional problem.

Turning now toFIG. 7, a flow chart of a method700for calibrating output offsets for multipliers is depicted. Method700is one embodiment of a method that may be performed by a circuit that includes multipliers (such as power detection unit120) or circuit coupled to a multiplier such as output offset unit250. Like method500, method700, in some embodiments, may be performed as part of an initial calibration for the circuit (such as during the circuit's startup, during testing of the circuit by automated testing equipment (ATE), etc.).

In step710, the same input is provided to a pair of multipliers (e.g., multipliers210) coupled to a comparator (e.g., comparator240). As discussed above, in some embodiments, this signal may be a voltage differential signal, and the multipliers may produce currents that vary proportional to the square of the input signal (e.g., Iin212and IREF214, described above).

In step720, adjustments are made to the output offset for one of the multipliers (e.g., multiplier210B; in other embodiments, adjustments to output offsets for both multipliers may be made) by a full offset value and starting from an initial value. As will be described below in conjunction withFIG. 8, in various embodiments, output offset unit250may be configured to produce a range of voltages for converter230B. Unit250may start at the lower part of the range and begin increasing the voltages by a particular amount (i.e., a “full offset value”) causing converter230to produce a voltage with an increasing DC offset. For example, unit250may cause converter230B to increase the DC offset of produced voltages by 1 mV increments until reaching step730.

In step730, a change in the output of the comparator is detected. Since the multipliers are being provided the same input in step710, this change in the output at the comparator indicates that the inputs of the comparator are now similar. For example, if the output of converter230A is 99.5 mV for the given input and the output of converter230B is 99 mV, an adjustment in step720, which causes converter230B to produce 100 mV, will produce a change in the output of comparator240—thus, indicating that the inputs are similar.

In step740, the multiplier output offset is adjusted back by half an offset value after the change in step730is detected. For example, if adjustments of lmV are being made in step720and the output of converter230B changes from 99 mV to 100 mV, an adjustment back to 99.5 mV would be made in the illustrated embodiment since 0.5 mV is half of 1 mV. In this way, step740is able to better compensate for an over adjustment in step720. In other words, adjusting the output of converter230B back to 99.5 mV is closer to the 99.5 mV output by converter230A than the initial 100 mV output at the end of step720.

As will be described below, in various embodiments, output offset unit250is configured to produce voltages for converter230B by passing a current through a resistor ladder and selecting various ones of the resistors (such as described with calibration unit350). In some embodiments, output offset unit250is also configured to change the generated voltage of a selected resistor by coupling a resistor in parallel with one of the resistors in the resistor ladder.

Turning now toFIG. 8, one embodiment of output offset unit250is depicted. In the illustrated embodiment, output offset unit250includes current sources810A-C, transistors820A-D, resistors830A-E, transistors840A-C, voltage reference850, transistor860, and resistor862. Output offset unit250also includes a control unit870to manage operation of unit250. In some embodiments, output offset unit250may include additional resistors830and transistors840.

In the illustrated embodiment, output offset unit250generates the offset voltages by passing a current from current source810A through resistors830. The voltages are generated around a common-mode voltage Vcmreceived from reference850. Output offset unit250then controls which voltages are selected and provided to converter230B by activating transistors840. To reduce the number of resistors830(which can be substantially large, in some embodiments), output offset unit250, in the illustrated embodiment, is configured to use transistors820to change the direction of the current flowing through resistors830. In this way, output offset unit250is able to produce voltages lower than Vcmby causing the current generated by source810A to flow from node850to current source810C, instead of through resistors830to current source810B. In other embodiments in which unit250does not include transistors820, however, unit250may include additional resistors after node850to produce voltages lower than Vcm.

In the illustrated embodiment, output offset unit250is also configured to couple resistor862in parallel with resistor830E to reduce the voltage drop across resistors830E (e.g., by a half when resistors862and820E have the same resistance). Thus, if a particular desired voltage falls between a pair of voltages selectable by using transistors830(e.g., between 99 mV and 100 mV such as described above), output offset unit250can couple resistor862to change the voltage so that it falls within the desired range (e.g., 99.5 mV).

In various embodiments, control unit870is configured to determine which output offset to apply and control transistors820,840, and860, accordingly. As discussed above in conjunction with method700, in one embodiment, control unit870is configured to determine the output offset based on when output242of comparator240changes.