Nonvolatile memory cells and nonvolatile memory devices including the same

A nonvolatile memory cell may include a bidirectional switch having a first threshold voltage when a forward current is applied to the bidirectional switch and a second threshold voltage when a reverse current is applied to the bidirectional switch; and a variable resistor connected to the bidirectional switch in series. A state of resistance of the variable resistor may be controlled according to voltage applied to the variable resistor. A sum of a magnitude of the first threshold voltage and a magnitude of the second threshold voltage may be greater than a write voltage that is used to perform a write operation on the variable resistor.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2009-0118454, filed on Dec. 2, 2009, in the Korean Intellectual Property Office (KIPO), the disclosure of which is incorporated herein in its entirety by reference.

BACKGROUND

Example embodiments relate to nonvolatile memory cells, and more particularly, to nonvolatile memory cells and nonvolatile memory devices including the nonvolatile memory cells.

Next generation memory devices include, for example, nonvolatile memory devices which do not require a refresh operation to retain stored data. These memory devices have high storage capacity and low power consumption. These next-generation memory devices may also be required to have a high integration like that of, for example, a dynamic random access memory (DRAM), a nonvolatile characteristic like that of, for example, a flash memory, and a high-speed of operation like that of, for example, a static RAM (SRAM) or the like. Examples of memory devices that possess the above characteristics include phase change RAMs (PRAMs), nano floating gate memories (NFGMs), polymer RAMs (PoRAMs), magnetic RAMs (MRAMs), ferroelectric RAMs (FeRAMs), resistive RAMs (RRAMs) or the like.

SUMMARY

According to example embodiments, a nonvolatile memory cell includes a bidirectional switch having a first threshold voltage when a forward current is applied to the bidirectional switch and a second threshold voltage when a reverse current is applied to the bidirectional switch; and a variable resistor connected to the bidirectional switch in series, the variable resistor being in a high resistance state or low resistance state based on a voltage applied to the variable resistor. A sum of a magnitude of the first threshold voltage and a magnitude of the second threshold voltage is greater than a write voltage used to perform a write operation on the variable resistor.

According to example embodiments, a potential difference across the nonvolatile memory cell during the write operation is greater than or equal to a sum of the first threshold voltage and the write voltage or a sum of the second threshold voltage and the write voltage.

According to example embodiments, the write voltage includes a first write voltage having a positive value and a second write voltage having a negative value.

According to example embodiments, the first write voltage writes data ‘0’ in the nonvolatile memory cell and is a reset voltage, and the second write voltage writes data ‘1’ in the nonvolatile memory cell and is a set voltage.

According to example embodiments, the bidirectional switch comprises a bidirectional diode.

According to example embodiments, when the magnitude of the first threshold voltage is less than the magnitude of the second threshold voltage and a magnitude of the first write voltage is greater than a magnitude of the second write voltage, the bidirectional switch is connected to the variable resistor in the same direction as the variable resistor.

According to example embodiments, when the magnitude of the first threshold voltage is greater than the magnitude of the second threshold voltage and the magnitude of the first write voltage is less than the magnitude of the second write voltage, the bidirectional switch is connected to the variable resistor in the same direction as the variable resistor.

According to example embodiments, when the magnitude of the first threshold voltage is less than the magnitude of the second threshold voltage and the magnitude of the first write voltage is less than the magnitude of the second write voltage, the bidirectional switch is connected to the variable resistor in an opposite direction to the variable resistor.

According to example embodiments, when the magnitude of the first threshold voltage is greater than the magnitude of the second threshold voltage and the magnitude of the first write voltage is greater than the magnitude of the second write voltage, the bidirectional switch is connected to the variable resistor in an opposite direction to the variable resistor.

According to example embodiments, a nonvolatile memory device includes a memory cell array unit including a plurality of word lines, a plurality of bit lines; and a plurality of nonvolatile memory cells. The plurality of memory cells are at intersections of the plurality of bit lines and the plurality of bit lines. Each of the plurality of nonvolatile memory cells comprises a bidirectional switch and a variable resistor connected to the bidirectional switch in series. The nonvolatile memory device may also include a row driver configured to supply voltage to the plurality of word lines, the row driver including at least one replica element corresponding to the bidirectional switch and the row driver configured to control voltage applied to a nonvolatile memory cell of the plurality of nonvolatile memory cells in which a write operation is not performed.

According to example embodiments, the bidirectional switch has a first threshold voltage when a forward current is applied to the bidirectional switch and a second threshold voltage when a reverse current is applied to the bidirectional switch, and a resistance state of the variable resistor depends on a voltage applied to a word line of the plurality of word lines connected to the variable resistor and a voltage applied to a bit line of the plurality of bit lines connected to the variable resistor.

According to example embodiments, the row driver includes a first driver configured to supply a write voltage to the plurality of word lines based on a write signal and configured to supply a ground voltage to the plurality of word lines based on a discharge signal; and a second driver including the at least one replica element and configured to supply an inhibit voltage to the plurality of word lines based on a plurality of inhibit signals, the inhibit voltage being controlled by a threshold voltage of the at least one replica element.

According to example embodiments, the first driver includes a write voltage supplying unit configured to supply the write voltage when the write enable signal is activated; and a ground voltage supplying unit connected to the write voltage supplying unit and configured to supply the ground voltage when the discharge signal is activated.

According to example embodiments, the second driver includes first and second replica elements corresponding to the bidirectional switch, the first and second replica elements respectively connected to a write voltage terminal to which the write voltage is applied and a ground voltage terminal to which the ground voltage is applied; a first inhibit voltage supplying unit configured to supply a difference of the write voltage and a threshold voltage of the first replica element as a first inhibit voltage when a first inhibit signal of the plurality of inhibit signals is activated; a second inhibit voltage supplying unit configured to supply a threshold voltage of the second replica element as a second inhibit voltage when a second inhibit signal of the plurality of inhibit signals is activated; and a third inhibit voltage supplying unit configured to supply a power supply voltage as a third inhibit voltage when a third inhibit signal of the plurality of inhibit signals is activated.

According to example embodiments, the nonvolatile memory device further includes a row decoder configured to decode an input row address into an address signal and to apply the voltage supplied by the row driver to the plurality of word lines based on the address signal.

According to example embodiments, the row decoder includes a first decoder configured to decode a desired bit value of the row address into a first address signal corresponding to a plurality of main word lines; and a second decoder configured to decode a remainder of bit values of the row address not decoded by the first decoder into a second address signal, the second address signal corresponding to the plurality of word lines, and the second decoder configured to connect word lines corresponding to the second address signal to the plurality of main word lines.

According to example embodiments, at least one of the first decoder and the second decoder includes at least one replica element corresponding to the bidirectional switch.

According to example embodiments, the nonvolatile memory device further includes a row decoder configured to decode a row address into an address signal and configured to supply a voltage to the plurality of word lines according to the decoded address signal. The row decoder includes at least one replica element corresponding to the bidirectional switch and the row decoder controls the voltage supplied to the plurality of memory cells.

According to example embodiments, a resistance state of the variable resistor depends on a voltage applied to a word line of the plurality of word lines connected to the variable resistor and voltage applied to a bit line of the plurality of bit lines connected to the variable resistor.

According to example embodiments, the row decoder includes a first decoder configured to decode a desired bit value of the row address into a first address signal corresponding to a plurality of main word lines; and a second decoder configured to decode a remainder of the bit values of the row address not decoded by the first decoder into a second address signal, the second address signal corresponding to the plurality of word lines, and the second decoder configured to connect word lines corresponding to the second address signal to the plurality of main word lines.

According to example embodiments, the row driver supplies at least one of a write voltage, an inhibit voltage and a ground voltage to the plurality of word lines based on the address signal decoded by the row decoder, the row driver including at least one replica element corresponding to the bidirectional switch and the row driver configured to control the inhibit voltage applied to the memory cell of the plurality of memory cells in which a write operation is not performed.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

FIG. 1is a circuit diagram of a nonvolatile memory device1according to example embodiments. Referring toFIG. 1, the nonvolatile memory device1includes a plurality of first signal lines WL1, WL2, WL3, and WL4, a plurality of second signal lines BL1, BL2, BL3, and BL4, and a plurality of memory cells MC1, MC2, MC3, MC4, and MC5. For example, the plurality of first signal lines WL1, WL2, WL3, and WL4may be word lines, and the plurality of second signal lines BL1, BL2, BL3, and BL4may be bit lines. Hereinafter, a case where the plurality of first signal lines WL1, WL2, WL3, and WL4are the word lines and the plurality of second signal lines BL1, BL2, BL3, and BL4are the bit lines will be described. However, example embodiments are not limited thereto, and the plurality of first signal lines may be the bit lines, and the plurality of second signal lines may be the word lines.

The plurality of word lines WL1, WL2, WL3, and WL4may extend in a first direction while being parallel to one another. Only four word lines WL1, WL2, WL3, and WL4are illustrated inFIG. 1. However, this is just an example, and the number word lines in the nonvolatile memory device1may be greater than or less than four.

The plurality of bit lines BL1, BL2, BL3, and BL4may extend in a second direction that is perpendicular to the first direction while being parallel to one another. In other words, the plurality of bit lines BL1, BL2, BL3, and BL4may intersect the plurality of word lines WL1, WL2, WL3, and WL4. Only four bit lines BL1, BL2, BL3, and BL4are illustrated inFIG. 1. However, this is just an example, and the nonvolatile memory device1may include bit lines greater than or less than four.

The plurality of memory cells MC1, MC2, MC3, MC4, and MC5may be disposed in regions in which the plurality of word lines WL1, WL2, WL3, and WL4and the plurality of bit lines BL1, BL2, BL3, and BL4intersect one another. Each of the plurality of memory cells MC1, MC2, MC3, MC4, and MC5may include a bidirectional switch D and a variable resistor R connected in series to the bidirectional switch D. One end of the bidirectional switch D may be connected to one of the plurality of word lines WL1, WL2, WL3, and WL4, and one end of the variable resistor R may be connected to one of the plurality of bit lines BL1, BL2, BL3, and BL4.

FIG. 2is a graph showing voltage versus current (VI) characteristics of the bidirectional switch D disposed in each of a plurality of memory cells of the nonvolatile memory device ofFIG. 1. Referring toFIGS. 1 and 2, the bidirectional switch D may be implemented as a bidirectional diode, for example. Hereinafter, a case where the bidirectional switch D is a bidirectional diode. However, example embodiments are not limited thereto, and the bidirectional switch D may be implemented as a transistor, for example.

The bidirectional diode D has a first threshold voltage VTHpthat is a threshold voltage in case that a forward current is applied to the bidirectional diode D and a second threshold voltage VTHn, that is a threshold voltage in case that a reverse current is applied to the bidirectional diode D. In detail, when a voltage smaller than the first threshold voltage VTHpis applied to the bidirectional diode D in a forward direction, the bidirectional diode D may not turned on and thus, current may not flow through the bidirectional diode D. On the other hand, when voltage that is greater than or equal to the first threshold voltage VTHpis applied to the bidirectional diode D in the forward direction, the bidirectional diode D may turn on and thus, current may flow through the bidirectional diode D in the forward direction. Similarly, when a voltage smaller than the second threshold voltage VTHnis applied to the bidirectional diode D in a reverse direction, the bidirectional diode D may not turn on and thus, current may not flow through the bidirectional diode D. On the other hand, when a voltage greater than the second threshold voltage VTHnis applied to the bidirectional diode D in the reverse direction, the bidirectional diode D may be turned on and thus, current may flow through the bidirectional diode D in the reverse direction.

For example, the bidirectional diode D may include two diodes that are connected to each other in parallel in opposite directions. A smaller of the forward threshold voltages of the two diodes may be a first threshold voltage of the bidirectional diode D, and a smaller of the backward threshold voltages of the two diodes may be a second threshold voltage of the bidirectional diode D. Alternatively, the bidirectional diode D may include a Zener diode. A breakdown voltage of the Zener diode may be the second threshold voltage of the bidirectional diode D.

In this way, when a positive voltage that is greater than the magnitude of the first threshold voltage VTHpis applied to the bidirectional diode D, the bidirectional diode D is turned on in the forward direction, and when a negative voltage that is greater than the magnitude of the second threshold voltage VTHnis applied to the bidirectional diode D, the bidirectional diode is turned on in the reverse direction. Thus, a voltage that is used to turn on the bidirectional diode D has to be greater in magnitude than the first threshold voltage VTHpor the second threshold voltage VTHn.

FIG. 3is a graph showing voltage versus current (VI) characteristics of the variable resistor R disposed in each of the memory cells of the nonvolatile memory device1ofFIG. 1, andFIG. 4is a graph showing voltage versus resistance (VR) characteristics of the variable resistor R disposed in each of the memory cells of the nonvolatile memory device1ofFIG. 1.

Referring toFIGS. 1,3, and4, the variable resistor R may be in a high resistance state RHin which a very small amount of current flows through the variable resistor R, or a low resistance state RLin which a relatively large amount of current flows through the variable resistor R. The resistance state of the variable resistor R is based on the magnitude or direction of voltage applied to the variable resistor R or the magnitude or direction of current flowing through the variable resistor R. When a reset voltage Vresetis applied to the variable resistor R, the variable resistor R is may attain the low resistance state RL. The variable resistor R is reset to data ‘0’ from data ‘1’. When a set voltage Vsetis applied to the variable resistor R, the variable resistor R may attain the high resistance state RHfrom the low resistance state RL. The variable resistor R is set to the data ‘1’ from the data ‘0’.

In this way, when a voltage greater than the magnitude of the reset voltage Vresetis applied to the variable resistor R, an operation of writing the data ‘0’ is performed on the variable resistor R, and when a voltage greater than the magnitude of the set voltage Vsetis applied to the variable resistor R, an operation of writing the data ‘1’ is performed on the variable resistor R. Thus, a write voltage VWRthat is used to perform the operation of writing the data ‘0’ or ‘1’ on the variable resistor R has to be greater than the magnitude of the reset voltage Vresetor the magnitude of the set voltage Vset.

Referring back toFIG. 1, when a write operation is performed on the first memory cell MC1of the plurality of memory cells MC1, MC2, MC3, MC4, and MC5, a voltage Vw(potential difference) applied to both ends of the first memory cell MC1has to be greater than or equal to the sum of the threshold voltage VTHof the bidirectional diode D and the write voltage VWRof the variable resistor R. In other words, a minimum voltage Vwthat is applied to both ends of the first memory cell MC1to perform the write operation on the first memory cell MC1is the sum of the threshold voltage VTHof the bidirectional diode D and the write voltage VWRof the variable resistor R (that is, Vw=VTH+VWR). The threshold voltage VTHof the bidirectional diode D may be the first threshold voltage VTHpor the second threshold voltage VTHnaccording to a direction in which current that flows through the first memory cell MC1.

In order to apply the voltage Vwto both ends of the first memory cell MC1, a given voltage has to be applied to the third word line WL3and the second bit line BL2connected to the first memory cell MC1. For example, 0 V may be applied to the third word line WL3and the voltage Vwmay be applied to the second bit line BL2, or the voltage Vwmay be applied to the third word line WL3and 0 V may be applied to the second bit line BL2. Alternatively, a voltage +½Vwmay be applied to the third word line WL3and a voltage −½Vwmay be applied to the second bit line BL2, or the voltage −½Vwmay be applied to the third word line WL3and the voltage +½Vwmay be applied to the second bit line BL2.

Although the write operation is not performed on the adjacent second memory cell MC2that is connected to the third word line WL3, a leakage current may be generated due to a voltage applied to the third word line WL3. Thus, voltage applied to the third bit line BL3connected to the second memory cell MC2is controlled so that a potential difference across the second memory cell MC2may be less than the threshold voltage of the bidirectional diode D of the second memory cell MC2(that is, ΔV<VTH).

Similarly, although the write operation is not performed on the adjacent third memory cell MC3that is connected to the second bit line BL2, a leakage current may be generated due to a voltage applied to the second bit line BL2. Thus, voltage applied to the fourth word line WL4connected to the third memory cell MC3is controlled so that a potential difference across the third memory cell MC3may be less than the threshold voltage of the bidirectional diode D of the third memory cell MC3(that is, ΔV<VTH).

Meanwhile, a difference between voltages applied to both ends of, for example, the fifth memory cell MC5has to be about 0 so that a leakage current may not be generated in the fifth memory cell MC5that is not connected to the third word line WL3and the second bit line BL2(that is, ΔV=0).

FIG. 5is a circuit diagram of a region indicated by a dotted line in the nonvolatile memory device1ofFIG. 1, illustrating a write operation performed on a memory cell in a first voltage condition.FIG. 5illustrates first through fourth memory cells MC1, MC2, MC3, and MC4of the nonvolatile memory device1ofFIG. 1that are disposed in regions in which the third and fourth word lines WL3and WL4and the second and third bit lines BL2and BL3intersect one another. The first memory cell MC1is a memory cell that is selected so that the write operation may be performed on the first memory cell MC1, and a potential difference ΔV1across the first memory cell MC1may be greater than or equal to the write voltage V. The write voltage VWcorresponds to the sum of the threshold voltage VTHof the bidirectional diode D and the write voltage VWRof the variable resistor R. The threshold voltage of the bidirectional diode D may be the first threshold voltage VTHPor the second threshold voltage VTHnaccording to a direction in which current flows through the first memory cell MC1.

During a write operation of the first memory cell MC1, in the first voltage condition, a voltage higher than voltage applied to the third word line WL3is applied to the second bit line BL2connected to the first memory cell MC1. For example, Vwmay be applied to the second bit line BL2, and 0 V may be applied to the third word line WL3. Here, current may flow through the first memory cell MC1in the forward direction from the second bit line BL2to the third word line WL3. Thus, the threshold voltage of the bidirectional diode D may be the first threshold voltage VTHp, and the potential difference ΔV1across the first memory cell MC1is equal to the write voltage Vw(sum of the first threshold voltage VTHpof the bidirectional diode D and the write voltage VWRof the variable resistor R, ΔV1=Vw=VTHp+VWR).

A potential difference across each of the second through fourth memory cells MC2, MC3, and MC4, which are adjacent to the first memory cell MC1and in which the write operation is not performed, is controlled so that a leakage current may not flow through the second through fourth memory cells MC2, MC3, and MC4. In other words, the potential difference across each of the second through fourth memory cells MC2, MC3, and MC4is controlled to be less than or equal to the threshold voltage of the bidirectional diode D included in the second through fourth memory cells MC2, MC3, and MC4and, as a result, a leakage current may not flow through the second through fourth memory cells MC2, MC3, and MC4. Hereinafter, an operation of controlling the potential difference across the second through fourth memory cells MC2, MC3, and MC4is described.

First, a potential difference ΔV2across the second memory cell MC2is controlled to be less than or equal to the threshold voltage of the bidirectional diode D so that a leakage current may not flow through the second memory cell MC2. Since voltage applied to the third word line WL3is 0 V, current may flow through the second memory cell MC2in the forward direction from the third bit line BL3to the third word line WL3. Thus, the potential difference ΔV2across the second memory cell MC2has to be less than or equal to the first threshold voltage VTHpof the bidirectional diode D in the forward direction. Thus, voltage applied to the third bit line BL3is first threshold voltage VTHp, and the potential difference ΔV2across the second memory cell MC2is the first threshold voltage VTHp(that is, ΔV2=VTHp).

Next, a potential difference Δ3across the third memory cell MC3is controlled to be less than or equal to the threshold voltage of the bidirectional diode D so that a leakage current may not flow through the third memory cell MC3. Since the voltage applied to the second bit line BL2is Vw, current may flow through the third memory cell MC3in the forward direction from the second bit line BL2to the fourth word line WL4. Thus, the potential difference ΔV3across the third memory cell MC3has to be less than or equal to the first threshold voltage VTHpof the bidirectional diode D in the forward direction. Thus, voltage applied to the fourth word line WL4is a minimal voltage (Vw−VTHp) and the potential difference ΔV3across of the third memory cell MC3is equal to the first threshold voltage VTHp(that is, ΔV3=VTHp).

Next, a potential difference ΔV4across the fourth memory cell MC4is controlled to be less than or equal to the threshold voltage of the bidirectional diode D so that the leakage current may not flow through the fourth memory cell MC4. Since the voltage applied to the fourth word line WL4is voltage (Vw−VTHp) and the voltage applied to the third bit line BL3is VTHp, a reverse current may flow through the fourth memory cell MC4from the fourth word line WL4to the third bit line BL3. Thus, the potential difference ΔV4across the fourth memory cell MC4has to be less than the magnitude of the second threshold voltage VTHpof the bidirectional diode D in the reverse direction.

Thus, the potential difference ΔV4(Vw−2VTHp) across the fourth memory cell MC4has to be less than the magnitude of the second threshold voltage VTHn(that is, Δ4<|VTHp|). Since the write voltage Vwis equal to the sum of the first threshold voltage VTHpof the bidirectional diode D and the write voltage VWRof the variable resistor R, ΔV4=Vw−2VTHp=(VTHp+VWR)−2VTHp=VWR−VTHp<|VTHp|. Thus, the write voltage VWRof the variable resistor R has to be less than the sum of the magnitude of the first threshold voltage VTHp, and the magnitude of the second threshold voltage VTHn(that is, VWR<|VTHp|+|VTHp|).

FIG. 6is a circuit diagram, according to example embodiments, of a region indicated by a dotted line in the nonvolatile memory device1ofFIG. 1, illustrating a write operation that is performed on a memory cell on a second voltage condition.FIG. 6illustrates the first through fourth memory cells MC1, MC2, MC3, and MC4of the nonvolatile memory device1that are disposed in regions in which the third and fourth word lines WL3and WL4and the second and third bit lines BL2and BL3intersect. The first memory cell MC1is selected to perform the write operation, and a potential difference ΔV1across the first memory cell MC1is greater than or equal to the write voltage Vw. The write voltage Vwcorresponds to the sum of the threshold voltage VTHof the bidirectional diode D and the write voltage VWRof the variable resistor R, and the threshold voltage applied to the bidirectional diode D may be the first threshold voltage VTHpor the second threshold voltage VTHnaccording to a direction in which current flows through the first memory cell MC1.

In the second voltage condition, a voltage higher than voltage applied to the second bit line BL2is applied to the third word line WL3that is connected to the first memory cell MC1. For example, VWmay be applied to the third word line WL3, and 0 V may be applied to the second bit line BL2. Here, current may flow through the first memory cell MC1in the reverse direction from the third word line WL3to the second bit line BL2. Thus, the threshold voltage applied to the bidirectional diode D is the second threshold voltage VTHn, and the potential difference ΔV1across the first memory cell MC1is equal to the write voltage Vw. The write voltage Vwcorresponds to a sum of the second threshold voltage VTHpof the bidirectional diode D and the write voltage VWRof the variable resistor R (that is, ΔV1=Vw=VTHn+VWR).

In this case, the potential difference across the second through fourth memory cells MC2, MC3, and MC4is controlled so that a leakage current may not flow through the second through fourth memory cells MC2, MC3, and MC4. As is seen, the second through fourth memory cells MC2, MC3, and MC4are adjacent to the first memory cell MC1and the write operation is not performed on them. In other words, the potential difference across the second through fourth memory cells MC2, MC3, and MC4may be less than or equal to the threshold voltage of the bidirectional diode D included in each of the second through fourth memory cells MC2, MC3, and MC4and a leakage current may not flow through each of the second through fourth memory cells MC2, MC3, and MC4. Hereinafter, an operation of controlling the potential difference across the second through fourth memory cells MC2, MC3, and MC4is described.

First, a potential difference ΔV2across the second memory cell MC2is controlled to be less than or equal to the threshold voltage of the bidirectional diode D so that a leakage current may not flow through the second memory cell MC2. Since voltage applied to the third word line WL3is Vw, current may flow through the second memory cell MC2in the backward direction from the third word line WL3to the third bit line BL3. Thus, the potential difference ΔV2across the second memory cell MC2has to be less than or equal to the second threshold voltage VTHnapplied to the bidirectional diode D in the reverse direction. Thus, voltage of the third bit line BL3is voltage (Vw−VTHn), and the potential difference ΔV2across the second memory cell MC2is equal to the second threshold voltage VTHn(that is, ΔV2=VTHn).

Next, a potential difference ΔV3across the third memory cell MC3has to be controlled to be less than or equal to the threshold voltage applied to the third memory cell MC3so that a leakage current may not flow through the third memory cell MC3. Since the voltage applied to the second bit line BL2is 0 V, current may flow through the third memory cell MC3in the reverse direction from the fourth word line WL4to the second bit line BL2. Thus, the potential difference ΔV3across the third memory cell MC3has to be less than or equal to the second threshold voltage VTHnof the bidirectional diode D in the reverse direction. Thus, a magnitude of the voltage applied to the fourth word line WL4is a maximal voltage VTHn, and the potential difference ΔV3across the third memory cell MC3is equal to the second threshold voltage VTHn(that is, ΔV3=VTHn).

Next, a potential difference ΔV4across the fourth memory cell MC4has to be controlled to be less than or equal to the threshold voltage of the bidirectional diode D so that the leakage current may not flow through the fourth memory cell MC4. Since the voltage applied to the third bit line BL3is voltage (Vw−VTHn) and the voltage applied to the fourth word line WL4is VTHn, current may flow through the fourth memory cell MC4in the forward direction from the third bit line BL3to the fourth word line WL4. Thus, the potential difference ΔV4across the fourth memory cell MC4may be less than the magnitude of the first threshold voltage VTHp, of the bidirectional diode D in the forward direction.

Thus, the potential difference ΔV4(Vw−2VTHn) across the fourth memory cell MC4has to be less than the magnitude of the first threshold voltage VTHp(that is, ΔV4<|VTHp|). Since the write voltage Vwis equal to the sum of the second threshold voltage VTHnof the bidirectional diode D and the write voltage VWRof the variable resistor R, ΔV4=Vw−2VTHn=(VTHn+VWR)−2VTHn=VWR−VTHn<|VTHp|. Thus, the write voltage VWRof the variable resistor R has to be less than the sum of the magnitude of the first threshold voltage VTHpand the magnitude of the second threshold voltage VTHn(that is, VWR<|VTHp|+|VTHn|).

As described above, in the nonvolatile memory device1including the plurality of memory cells, wherein each of the memory cells includes the bidirectional diode D and the variable resistor R, in order to prevent leakage current, the write voltage VWRof the variable resistor R has to be less than the sum of the magnitude of the first threshold voltage VTHp, and the magnitude of the second threshold voltage VTHn(that is, VWR<|VTHp+|+|VTHn|). Thus, when designing the nonvolatile memory device1, the variable resistor R may be selected according to the write voltage VWRthat is obtained based on the first and second threshold voltages VTHpand VTHnof the bidirectional diode D, and the bidirectional diode D may be selected according to the first and second threshold voltages VTHpand VTHnthat are obtained based on the write voltage VWRof the variable resistor R.

FIG. 7is a graph showing voltage versus current (VI) characteristics of a bidirectional diode according to example embodiments.FIG. 8is a graph showing voltage versus current (VI) characteristics of a variable resistor according to example embodiments.FIG. 9is a circuit diagram of a memory cell including the bidirectional diode ofFIG. 7and the variable resistor ofFIG. 8.FIG. 10is a graph showing current versus voltage (VI) characteristics of the memory cell ofFIG. 9.

Referring toFIGS. 7 through 10, a first bidirectional diode D1may have a first threshold voltage VTHpthat is a threshold voltage in case that a forward current flows through the first bidirectional diode D, and a second threshold voltage VTHnthat is a threshold voltage in case that a reverse current flows through the first bidirectional diode D1, and the magnitude of the first threshold voltage VTHpmay be less than the magnitude of the second threshold voltage VTHn. Also, the variable resistor R1may have a first write voltage Vresetand a second write voltage Vset, and the magnitude of the first write voltage Vresetmay be greater than the magnitude of the second write voltage Vset.

In order to perform a write operation on each of memory cells of a memory cell array, voltage having a desired magnitude has to be applied to the memory cell in the forward or reverse direction. In order to write data ‘0’ in the memory cell, the voltage has to be applied to the memory cell in the forward direction. The voltage applied to the memory cell has to be greater than or equal to the sum of the first threshold voltage of the bidirectional diode and the first write voltage of the variable resistor. Also, in order to write data ‘1’ in the memory cell, the voltage has to be applied to the memory cell in the reverse direction. The magnitude of the voltage applied to the memory cell has to be greater than or equal to the sum of the magnitude of the second threshold voltage applied to the bidirectional diode D and the magnitude of the second write voltage applied to the variable resistor R.

Thus, when a memory cell MC11(FIG. 9) includes a bidirectional diode D1having the voltage-current characteristic ofFIG. 7and a variable resistor R1having the voltage-current characteristic ofFIG. 8, the bidirectional diode D1and the variable resistor R1may be connected to each other in series in a same direction. A series connection of the bidirectional diode D1and the variable resistor R1may result in the current-voltage (VI) characteristic curve as shown inFIG. 10.

When the write operation is performed on the memory cell MC11, voltage applied to the memory cell MC11in the forward direction has to be greater than or equal to the sum of the first threshold voltage VTHp(a relatively small value) and the first write voltage Vreset(a relatively large value), and voltage applied to the memory cell MC11in the reverse direction has to be greater than or equal to the sum of the second threshold voltage VTHn(a relatively large value) and the second write voltage Vset(a relatively small value).

Since the sum of the first threshold voltage VTHp, and the first write voltage Vresetis somewhat similar to the sum of the second threshold voltage VTHnand the second write voltage Vset, the voltage applied to the memory cell MC11in the forward direction is somewhat similar to the voltage applied to the memory cell MC11in the reverse direction. Thus, since the write voltage applied to the memory cell MC11may be reduced, a size of a boosting circuit for boosting voltage may be reduced, and the level of current that flows through the memory cell MC11may be reduced.

Similarly, even when the magnitude of the first threshold voltage VTHpof the bidirectional diode D1is greater than the magnitude of the second threshold voltage VTHnand the magnitude of the first write voltage Vresetof the variable resistor R is less than the magnitude of the second write voltage Vset, the bidirectional diode D1and the variable resistor R1may be connected to each other in series in the same direction, as illustrated inFIG. 9.

FIG. 11is a graph showing voltage versus current (VI) characteristics of a bidirectional diode D2according to example embodiments.FIG. 12is a graph showing voltage versus current (VI) characteristics of a variable resistor R2according to example embodiments.FIG. 13is a circuit diagram illustrating the connection between the bidirectional diode D2ofFIG. 11and the variable resistor R2ofFIG. 12.

Referring toFIGS. 11 through 13, the bidirectional diode D2may have a first threshold voltage VTHpwhen a forward current is applied to the bidirectional diode D2and a second threshold voltage VTHnwhen a reverse current is applied to the bidirectional diode D2, wherein the magnitude of the first threshold voltage VTHpmay be less than the magnitude of the second threshold voltage VTHn. Also, the variable resistor R2may have a first write voltage Vresetand a second write voltage Vset, wherein the magnitude of the first write voltage Vresetmay be less than the magnitude of the second write voltage Vset.

When the bidirectional diode D2having the voltage-current characteristics ofFIG. 11and the variable resistor R2having the voltage-current characteristics ofFIG. 12constitute a memory cell MC22, the bidirectional diode D2and the variable resistor R2may be connected to each other in series in opposite directions, as illustrated inFIG. 13. Such a series connection may result in the current-voltage characteristic curve of the memory cell MC22as shown inFIG. 10.

When a write operation is performed on the memory cell MC22, a forward voltage applied to the memory cell MC22has to be greater than or equal to the sum of the second threshold voltage VTHn(a relatively large value) and the first write voltage Vreset(a relatively small value), and a reverse voltage applied to the memory cell MC22has to be greater than or equal to the sum of the first threshold voltage VTHp(a relatively small value) and the second write voltage Vset(a relatively large value). Since the sum of the second threshold voltage VTHnand the first write voltage Vresetis somewhat similar to the sum of the first threshold voltage VTHpand the second threshold voltage Vset, the forward voltage applied to the memory cell MC22is somewhat similar to the reverse voltage applied to the memory cell MC22. Thus, since the write voltage applied to the memory cell MC22may be reduced, the size of a boosting circuit for boosting voltage may be reduced, and the level of current that flows through the memory cell MC22may be reduced.

Similarly, even when the magnitude of the first threshold voltage VTHpof the bidirectional diode D2is greater than the magnitude of the second threshold voltage VTHnand the magnitude of the first write voltage Vresetof the variable resistor R2is greater than the magnitude of the second write voltage Vset, the bidirectional diode D2and the variable resistor R2may be connected to each other in series in opposite directions and may constitute the memory cell MC22, as illustrated inFIG. 13.

FIG. 14is a block diagram of a nonvolatile memory device2according to example embodiments. Referring toFIG. 14, the nonvolatile memory device2may include a memory cell array10, a row driver20, a row decoder30, an auxiliary decoder40, a column decoder50, and a sense amplifier/write driver60.

The memory cell array10may include a plurality of word lines, a plurality of bit lines, and a plurality of memory cells disposed in a region in which the plurality of word lines and the plurality of bit lines intersect. The plurality of memory cells may include the bidirectional diode D and the variable resistor R, as illustrated inFIG. 1. The plurality of word lines may include a plurality of main word lines and a plurality of sub-word lines.

The row driver20may generate a driving voltage VDthat is applied to the plurality of word lines of the memory cell array10. The row decoder30may decode a desired bit value of a row address X_ADD into a first address signal that corresponds to the plurality of main word lines to activate at least one of the main word lines. The auxiliary decoder40may decode the remaining bit value of the row address X_ADD into a second address signal that corresponds to the plurality of sub-word lines to activate at least one of the sub-word lines. The main word lines may correspond to global word lines, and the sub-word lines may correspond to local word lines. Alternatively, the nonvolatile memory device2may not include the auxiliary decoder40, and the row decoder30may decode the row address X_ADD into an address signal that corresponds to the plurality of word lines.

The column decoder50may decode a column address Y_ADD to select at least one bit line that corresponds to the column address Y_ADD. The sense amplifier/write driver60may receive data from the memory cells of the memory cell array10and may perform a read operation on the memory cells of the memory cell array10, or may supply voltage to the plurality of bit lines of the memory cell array10and may perform a write operation on the memory cells of the memory cell array10.

FIG. 15is a block diagram of the row driver20ofFIG. 14, according to example embodiments. Referring toFIG. 15, the row driver20may include a first driver21for supplying a driving voltage to a memory cell of the plurality of memory cells in which a write operation is performed, and a second driver22for supplying a driving voltage to a memory cell of the plurality of memory cells in which the write operation is not performed.

The first driver21may supply a write voltage or a ground voltage to the plurality of word lines based on a write enable signal WEN and a discharge signal DIS, and may include a write voltage supplying unit211and a ground voltage supplying unit212.

The write voltage supplying unit211may supply a write voltage Vwto the word lines when the write enable signal WEN is activated. For example, the write voltage supplying unit211may include a first PMOS transistor P21, and the first PMOS transistor P21may have a source connected to a write voltage terminal to which the write voltage Vwis applied, and a gate to which an inverted write enable signal nWEN is applied. When the write enable signal WEN is activated, i.e., when the inverted write enable signal nWEN is at a logic ‘low’ level, the first PMOS transistor P21may be turned on and may supply the write voltage Vwto the word lines.

The ground voltage supplying unit212may supply a ground voltage to the word lines when the discharge signal DIS is activated. For example, the ground voltage supplying unit212may include a first NMOS transistor N21, and the first NMOS transistor N21may have a drain connected to a drain of the first PMOS transistor P21, a gate to which the discharge signal DIS is applied, and a source connected to a ground voltage terminal to which the ground voltage is applied. When the discharge signal DIS is activated, i.e., when the discharge signal DIS is at a logic ‘high’ level, the first NMOS transistor N21may be turned on and may supply the ground voltage to the word lines.

The second driver22that supplies a inhibit voltage to the word lines based on a plurality of inhibit signals INH0, INH1, and INH2and may include first and second replica elements221and222corresponding to the bidirectional diode D, a first inhibit voltage supplying unit223, a second inhibit voltage supplying unit224, and a third inhibit voltage supplying unit225.

The first replica element221corresponding to the bidirectional diode D of a memory cell of the memory cell array10may be connected to a write voltage terminal. The second replica element222corresponding to the bidirectional diode D of the memory cell of the memory cell array10may be connected to a ground voltage terminal. Due to a variation of temperature, pressure or process, for example, a magnitude of a threshold voltage of the bidirectional diode D of the memory cell of the memory cell array10may vary. Accordingly, the first and second replica elements221and222corresponding to the bidirectional diode D may be included outside the memory cell array10, for example, in the row driver20so that the amount of a change of the threshold voltage of the bidirectional diode D included in the memory cell array10may be corrected.

The first inhibit voltage supplying unit223may supply a first inhibit voltage to the memory cell of the memory cell array10when the first inhibit signal INH0is activated. For example, the first inhibit voltage supplying unit223may include a second PMOS transistor P22, and the second PMOS transistor P22may have a source connected to the first replica element221and a gate to which the first inhibit signal INH0is applied. When the first inhibit signal INH0is activated (for example, logic ‘low’ level), the second PMOS transistor P22may turn on and may supply a voltage corresponding to a voltage obtained by subtracting a threshold voltage VTHof the first replica element221from the write voltage Vw(Vw−VTH) as the first inhibit voltage to the memory cell of the memory cell array10.

The second inhibit voltage supplying unit224may supply a second inhibit voltage to the memory cell of the memory cell array10when the second inhibit signal INH1is activated. For example, the second inhibit voltage supplying unit224may include a third PMOS transistor P23, and the third PMOS transistor P23may have a source connected to a power supply voltage terminal to which the power supply voltage VDD is applied, and a gate to which the second inhibit signal INH1is applied. When the second inhibit signal INH0is activated (for example, logic ‘low’ level) the third PMOS transistor P23may be turned on and may supply the power supply voltage VDD as the second inhibit voltage to the memory cell of the memory cell array10.

The third inhibit voltage supplying unit225may supply a third inhibit voltage to the memory cell of the memory cell array10when the third inhibit signal INH2is activated. For example, the third inhibit voltage supplying unit225may include a second NMOS transistor N22, and the second NMOS transistor N22may have a drain connected to the drain of the second PMOS transistor P22, a gate to which the third inhibit signal INH2is applied, and a source connected to the second replica element222. When the third inhibit signal INH2is activated (for example, logic ‘high’ level) the second NMOS transistor N22may be turned on and may supply a threshold voltage VTHof the second replica element222as the third inhibit voltage to the memory cell of the memory cell array10.

According to the example embodiments ofFIG. 15, the row driver20includes the first driver21that supplies the write voltage or the ground voltage and the second driver22that supplies first through third inhibit voltages. Thus, the row driver20may not include a voltage generator that generates the first through third inhibit voltages and, as a result, the area of the nonvolatile memory device1ofFIG. 14may be reduced.

Also, the second driver22of the row driver20includes first and second replica elements221and222corresponding to the bidirectional diode D included in the memory cell array10, thereby supplying the first and third inhibit voltages that are generated based on the threshold voltages VTHof the first and second replica elements221and222to the memory cell array10. As such, the memory cell array10receives an inhibit voltage that is corrected based on the threshold voltages VTHof the first and second replica elements221and222, thereby reducing a leakage current or noise that may occur in the memory cells due to a change of the threshold voltage of the bidirectional diode D included in the memory cell array10.

In other words, due to a change of the threshold voltage of the bidirectional diode of the memory cell array10, the leakage current may flow through the memory cell of the memory cell array10in which the write operation does not have to be performed. The row driver20may supply a inhibit voltage (e.g., VW−VTHor VTH) that is corrected based on the change of the threshold voltages VTHby using the first and second replica elements221and222with respect to the bidirectional diode D. As such, the inhibit voltage applied to the memory cell of the memory cell array10in which the write operation does not have to be performed, may be reduced by the threshold voltage VTHof the first replica element221or may be increased by the threshold voltage VTHof the second replica element222. Thus, in the memory cells of the memory cell array10in which the write operation does not have to be performed, although the threshold voltage of the bidirectional diode D included in the memory cells is varied, the inhibit voltage is also varied so that the leakage current or noise may not occur.

FIG. 16is a circuit diagram of the row decoder30and the auxiliary decoder40ofFIG. 14according to example embodiments. Referring toFIG. 16, the row decoder30may encode a desired bit value of a row address X_ADD into a first address signal corresponding to main word lines MWL and may include first through eighth transmission units31to38. When the first address signal is at the logic ‘low’ level, the first through eighth transmission units31to38may supply a driving voltage VD that is supplied by the row driver20to sub-word lines WL. Meanwhile, when the first address signal is at the logic ‘high’ level, the first through eighth transmission units31to38may supply voltage that is supplied by the auxiliary decoder40to the sub-word lines WL.

The auxiliary decoder40may decode the remaining bit value (for example, bit values not encoded by the row decoder30) of the row address X_ADD into a second address signal corresponding to the sub-word lines WL and may include ninth through twelfth transmission units41,42,43, and44. When the second address signal is at the logic ‘low’ level, the ninth through twelfth transmission units41,42,43, and44may supply the driving voltage VD that is supplied by the row driver20. Meanwhile, when the second address signal is at the logic ‘high’ level, the ninth through twelfth transmission units41,42,43, and44may supply the write voltage Vw or the ground voltage 0 V. As such, since the forward or reverse voltage may be applied to each memory cell of the memory cell array10, an operation of writing data ‘0’ or ‘1’ may be performed on each memory cell.

The first through eighth transmission units31to38included in the row decoder30may include a replica element corresponding to the bidirectional diode D included in the memory cell array10. The ninth through twelfth transmission units41,42,43, and44included in the auxiliary decoder40may also include the replica element corresponding to the bidirectional diode D included in the memory cell array10. Thus, the occurrence of the leakage current or noise due to the change of the threshold voltage of the bidirectional diode D included in the memory cell array10may be prevented.

FIG. 17is a block diagram of a nonvolatile memory device100according to example embodiments. Referring toFIG. 17, the nonvolatile memory device100may include a memory core unit110and a peripheral circuit unit120. The memory core unit110may include a plurality of memory cell arrays MCA111, a plurality of row decoders X-DEC112, a plurality of column decoders Y-DEC113, a plurality of sense amplifiers S/A/write drivers W/D114, and a main row decoder115. The peripheral circuit unit120may include the row driver20ofFIG. 15.

Thus, the peripheral circuit unit120includes a replica element corresponding to the bidirectional diode D included in the memory cell arrays MCA111, thereby correcting the amount of a change of the threshold voltage of the bidirectional diode D included in the memory cell arrays MCA111. Alternatively, the plurality of column decoders Y-DEC113or the plurality of sense amplifiers S/A/write drivers W/D114may include the replica element corresponding to the bidirectional diode D included in the memory cell arrays MCA111.

FIG. 18is a perspective view of a nonvolatile memory device200according to example embodiments. Referring toFIG. 18, the nonvolatile memory device200may include a plurality of bit lines BL, a plurality of word lines WL, and a plurality of memory cells. The plurality of bit lines BL may be disposed to intersect the plurality of word lines WL. Each of the plurality of memory cells may be disposed in a region in which the bit lines BL and the word lines WL intersect one another, and may include a bidirectional diode D and a variable resistor R.

FIG. 19is a perspective view of a nonvolatile memory device300according to example embodiments. Referring toFIG. 19, the nonvolatile memory device300may include a plurality of bit lines BL disposed in parallel to a substrate SUB, a plurality of word lines WL disposed perpendicular to the substrate SUB, and a plurality of memory cells disposed between the bit lines BL and the word lines WL. Each of the memory cells may include a diode material D and a variable resistor material R, which are formed perpendicular to the substrate SUB. The variable resistor material R may be, for example, amorphous silicon doped with vanadium (V), cobalt (Co), nickel (Ni), palladium (Pd), iron (Fe) or manganese (Mn) or a perovskite material, such as Pr1-xCaxMnO3, La1-xCaxMnO3(LCMO), LaSrMnO3(LSMO) or GdBaCoxOy(GBCO).

FIG. 20is a plan view of a nonvolatile memory device according to example embodiments. Referring toFIG. 20, a decoder that is commonly connected to first and second memory cell arrays MCA1and MCA2may be disposed in a layer other than the layers of the first and second memory cell arrays MCA1and MCA2. For example, the first and second memory cell arrays MCA1and MCA2may be disposed in upper layers of the nonvolatile memory device, and the decoder may be disposed in a lower layer of the nonvolatile memory device so that the area of the nonvolatile memory device may be reduced. Alternatively, the decoder may be disposed in an upper layer of the nonvolatile memory device, or the first and second memory cell arrays MCA1and MCA2may be disposed in lower layers of the nonvolatile memory device.

A gate electrode GP is disposed on an active region ACT of the decoder, and a source/drain region may be formed on both sides of the gate electrode GP. The source/drain region may be connected to a plurality of bit lines or a plurality of word lines of the first and second memory cell arrays MCA1and MCA2via a contact CON.

FIG. 21is a block diagram of a memory card2100according to example embodiments. Referring toFIG. 21, the memory card2100may include a controller2110and a memory unit2120, which are disposed in a housing2130, wherein the controller2110and the memory unit2120may exchange electrical signals. For example, the memory unit2120and the controller2110may exchange data based on a command from the controller2110. Thus, the memory card2100may store data in the memory unit2120or may output the data from the memory unit2120to an external device.

For example, the memory unit2100may include any one of the nonvolatile memory devices according to example embodiments ofFIGS. 1 through 20. The memory card2100may be used as a data storage medium for various mobile devices. For example, the memory card2100may include a multimedia card (MMC) or a secure digital (SD) card.

FIG. 22is a block diagram of an electronic system2200according to example embodiments. Referring toFIG. 22, the electronic system2200may include a processor2210, a memory unit2220, and an input/output unit2230, wherein the processor2210, the memory unit2220, and the input/output unit2230may communicate data with one another via a bus2240. The processor2210may execute a program and may control the electronic system2200. The input/output unit2230may be used to input or output data output from the electronic system2200. The electronic system2200may be connected to an external device, such as a personal computer or a network, via the input/output unit2230and may exchange data with the external device. The memory unit2220may store codes for operating the processor2210and the data. For example, the memory unit2220may include any one of the nonvolatile memory devices according to example embodiments ofFIGS. 1 through 20.

For example, the electronic system2200may include various electronic devices including a memory unit and may be used in mobile phones, MP3 players, navigation devices, solid state drives (SSD), household appliances or the like.

According to the one or more example embodiments, in a nonvolatile memory cell including a bidirectional diode and a variable resistor, the sum of magnitudes of first and second threshold voltages may be controlled to be greater than a write voltage of the variable resistor so that a leakage current and noise that may occur in a nonvolatile memory cell in which a write operation is not performed, may be reduced.

Furthermore, when the magnitude of the first threshold voltage of the bidirectional diode is greater than the magnitude of the second threshold voltage of the bidirectional diode and the magnitude of a first write voltage of the variable resistor is greater than the magnitude of a second write voltage of the variable resistor, the bidirectional diode may be connected to the variable resistor in an opposite direction to the variable resistor, and when the magnitude of the first threshold voltage of the bidirectional diode is greater than the magnitude of the second threshold voltage of the bidirectional diode and the magnitude of the first write voltage of the variable resistor is less than the magnitude of the second write voltage of the variable resistor, the bidirectional diode may be connected to the variable resistor in the same direction as the variable resistor so that the magnitudes of forward and reverse voltages that are used to perform a write operation on a memory cell may be controlled to be somewhat similar to each other. Thus, since the level of voltage that is used to perform the write operation on the memory cell may be reduced, the size of a boosting circuit may be reduced, and the level of current that flows through the memory cell during the Write operation may be reduced.

Furthermore, a replica element corresponding to the bidirectional diode included in a memory cell array may be disposed in a row decoder or a row driver disposed outside the memory cell array. Thus, although the threshold voltage of the bidirectional diode is varied due to a variation of temperature, pressure or process, a driving voltage that is corrected based on the varied threshold voltage may be applied to the memory cell array so that the leakage current and noise may be reduced. Furthermore, an additional voltage generator for supplying a inhibit voltage to be applied to the memory cell of the memory cell array in which the write operation is not performed, does not have to be provided so that the area of the nonvolatile memory device may be reduced.