Semiconductor devices and circuits with increased breakdown voltage

A switching circuit includes a main circuit including a number of first transistors. The main circuit has a first node, a second node, and a third node and is operative in response to a control signal received by the first node, and the second node is configured to receive a supply voltage. The switching circuit also includes an auxiliary circuit electrically coupled to the second node of the main circuit and configured to provide surge protection for the main circuit. The auxiliary circuit includes a second transistor. A breakdown voltage of the second transistor is different than a breakdown voltage of each first transistor of the number of first transistors.

BACKGROUND

In semiconductor technology, Group III-Group V (or III-V) semiconductor compounds (e.g., gallium nitride (GaN)) may be used to form various integrated circuit (IC) devices, such as high-power field-effect transistors (FETs), high frequency transistors, or high-electron-mobility transistors (HEMTs). A high-electron-mobility transistor (HEMT) is a field effect transistor having a 2-dimensional electron gas (2DEG) layer close to a junction between two materials with different band gaps (i.e., a heterojunction). The 2-DEG layer is used as the transistor channel instead of a doped region, as is generally the case for metal oxide semiconductor field effect transistors (MOSFETs). Compared with MOSFETs, HEMTs have a number of attractive properties such as high breakdown voltage and low on-resistance. In some examples, due to its high breakdown voltage and low on-resistance, GaN-based HEMT may be used in an integrated circuit (e.g., switching power supplies). However, turning off the switches in the switching power supplies may create voltage spikes, also known as surges. To prevent the damages caused by the voltage spikes, there is a need to further increase the breakdown voltage of the GaN-based HEMT. Accordingly, improvements in this area are needed.

DETAILED DESCRIPTION

Compared with MOSFETs, HEMTs have a number of attractive properties such as high breakdown voltage and low on-resistance, and thus, HEMTs are widely used in various applications. In some embodiments, a switching circuit that includes a number of switch transistors (e.g., HEMTs) may be used in a power conversion circuit (e.g., a DC-DC converter). For example, a number of switch transistors may include HEMTs and may be coupled to a power supply. Turning off those switch transistors may lead to voltage spikes or surges, thereby damaging those switch transistors. For example, each switch transistor may have a breakdown voltage that is about, for example, 650V, and the surge voltage may be about, for example, 800V. Breakdown voltage of those HEMTs may be increased to prevent those HEMT-based switch transistors from being damaged by the voltage spikes. However, increasing the breakdown voltage of those HEMTs from 650V to 800V may include introducing a complicated field plate design and/or increasing a drift region length (i.e., a distance between gate structure and drain feature of the HEMTs), which may provide an increased fabrication cost associated with the formation of the HEMTs or an increased footprint for each HEMT of those HEMTs, thereby taking up an undue amount of real estate in an IC chip.

The present embodiments are directed to methods and circuits that provide surge protection to those HEMTs without increasing the breakdown voltage of the HEMTs. In an embodiment, a switching circuit includes a number of HEMTs connected in parallel and coupled to a power supply. Each of those HEMTs has a first breakdown voltage BV1. The power supply may generate a surge voltage that is greater than the first breakdown voltage BV1. An auxiliary circuit is electrically coupled to the switching circuit to provide surge protection. In an embodiment, the auxiliary circuit includes a HEMT having a second breakdown voltage BV2 greater than the first breakdown voltage BV1. When a surge voltage is generated, the surge voltage may be discharged by the HEMT in the auxiliary circuit. By providing the auxiliary circuit, without increasing the first breakdown voltage BV1, HEMTs in the switching circuit are protected from damage due to voltage overshoot spikes. The various aspects of the present disclosure will now be described in more detail with reference to the figures.

FIG.1illustrates a schematic of an exemplary simplified switching circuit100having an auxiliary circuit130, according to various aspects of the present disclosure. In embodiments represented inFIG.1, the switching circuit100includes a main circuit110. The main circuit110has a first node110aelectrically coupled to a drive circuit120and configured to receive a control signal from the drive circuit120. The main circuit110also has a second node110bconfigured to receive a supply voltage Vpp from a power line115(or a power supply115). The main circuit110also includes a third node110cconfigured to receive a reference voltage (e.g., ground voltage GND). In the present embodiment, the third node110cis coupled to a ground voltage. In some embodiments, the main circuit110includes a number of switch transistors (e.g., switch transistors1101,1102, . . .110Nshown inFIG.2). Those switch transistors may have a same breakdown voltage BV1. An exemplary schematic of the main circuit110is described in further detail with reference toFIG.2. As described above, turning off those switch transistors in the main circuit110may introduce a surge voltage to the power line115. For example, the power line115is configured to provide a normal level of voltage V1, and in situations where those switch transistors are turned off, a surge voltage V2 that is greater than the voltage V1 and greater than the breakdown voltage BV1 may be created. That is, the supply voltage Vpp provided by the power line115may be equal to the normal level of voltage V1 or the surge voltage V2. If the surge voltage V2 is fully applied to the second node110bof the main circuit110, since the surge voltage V2 is greater than the breakdown voltage BV1, those switch transistors in the main circuit110may be damaged. To prevent the main circuit110from being damaged by the surge voltage V2, an auxiliary circuit130is electrically coupled to main circuit110to provide a surge protection.

The auxiliary circuit130includes a capacitor140. One terminal140aof the capacitor140is electrically coupled to the second node110bof the main circuit110. In an embodiment, a capacitance of the capacitor140may be between about 1 pF and about 100 nF. The auxiliary circuit130also includes a resistor150electrically coupled to the other terminal140bof the capacitor140a. In the present embodiments, the other terminal of the resistor150is configured to receive a reference voltage (e.g., ground voltage GND). In an embodiment, a resistance of the resistor150may be between about 1 KΩ and about 100 KΩ.

The auxiliary circuit130also includes a transistor160. The transistor160has a first terminal160a(e.g., gate terminal) electrically coupled to the terminal140bof the capacitor140, a second terminal160belectrically coupled to the second node110bof the main circuit110, and a third terminal160cconfigured to receive a reference voltage (e.g., ground voltage GND). In an embodiment, the transistor160includes a GaN-based HEMT and has a breakdown voltage BV2 that is higher than the breakdown voltage BV1 of the switching transistors in the main circuit110. It is understood that transistor160is not limited to a GaN-based HEMT. In an embodiment, an operation voltage of the transistor160is higher than an operation voltage of each of the switch transistors in the main circuit110. When the switching transistors in the main circuit110are turned off and a surge voltage V2 is generated, or there is a spike voltage V2 from system, a surge current will flow through the capacitor140and build up a voltage by the resistor150. This built-up voltage may then turn on the transistor160. Thus, the surge voltage/spike voltage V2 may be discharged by the transistor160. An exemplary cross-sectional view of a structure of the transistor160will be described in detail with reference toFIG.4. In some embodiments, by providing different transistors160(having different breakdown voltages) for the auxiliary circuit130, the switching circuit100may be configured to sustain different surge voltages, and thus the switching circuit100may be implemented in different applications.

FIG.2illustrates a schematic of an exemplary simplified main circuit110of the switching circuit100shown inFIG.1, according to various aspects of the present disclosure. In embodiments represented inFIG.2, the main circuit110includes a number of switch transistors1101,1102, . . .110Nin parallel connection. N is an integer and may be greater than 1000. The switch transistors1101,1102, . . .110Nare connected in parallel. More specifically, each of the switch transistors1101,1102, . . .110Nincludes a gate terminal, a drain terminal, and a source terminal. The gate terminals of those switch transistors1101,1102, . . .110Nare electrically coupled to an output of the drive circuit120and are configured to receive the control signal from the drive circuit120, the drain terminals of those switch transistors1101,1102, . . .110Nare electrically coupled to the power line115, and the source terminals of those switch transistors1101,1102, . . .110Nare configured to receive, for example, a ground voltage. In an embodiment, each of the switch transistors1101,1102, . . .110Nincludes a GaN-based HEMT, and each HEMT has the same structure and configuration, and thus has the same breakdown voltage BV1. For example, those HEMTs in the main circuit110have the same gate width Wg1 (shown inFIG.5) and same distance between the gate structure and its respective drain feature (i.e., Lgd1 shown inFIG.3andFIG.5). The distance between the gate structure and its respective drain feature of the HEMT based transistor160in the auxiliary circuit130may be referred to as Lgd2 (shown inFIG.4andFIG.6) and is greater than the distance Lgd1. A fragmentary cross-sectional view of an exemplary structure of the switch transistors1101,1102, . . .110Nwill be described in further detail with reference toFIG.3. It is understood that each of the switch transistors1101,1102, . . .110Nis not limited to a GaN-based HEMT.

In an embodiment, the first breakdown voltage BV1 may be about 500V, and the second breakdown voltage BV2 may be about 800V, and the main circuit110may include 3000 switch transistors, a total gate width of the 3000 switch transistors may be about 300 mm. To prevent the main circuit110from being damaged due to surge voltage, instead of providing the auxiliary circuit130, another possible method may include increasing the length of the drain drift region (i.e., the region between gate structure and its respective drain feature) of each switch transistor of those 3000 switch transistors in the main circuit110from Lgd1 to Lgd2. However, increasing the length of the drain drift region of each switch transistor from Lgd1 to Lgd2 may significantly and disadvantageously increase a total footprint of the main circuit110. For example, a total chip area of a main circuit that includes switch transistors each having the second breakdown voltage BV2 may be about 7 mm2; however, a total chip area of a main circuit that includes switch transistors each having the first breakdown voltage BV1 may be about 4.2 mm2and a total chip area of the auxiliary circuit may be about 0.02 mm2. Therefore, compared with embodiments where the length of the drain drift region of each switch transistor is increased from Lgd1 to Lgd2 to increase the breakdown voltage from BV1 to BV2, the switching circuit100that implements the auxiliary circuit130may have a smaller footprint (reduced by 40%) and takes less amount of real estate of an IC chip.

FIG.3illustrates an exemplary cross-sectional view of the switch transistor1101implemented in the main circuit110shown inFIG.2, according to various aspects of the present disclosure. Since the switch transistor1101includes a HEMT, the switch transistor1101may be referred to as a semiconductor device1101or a HEMT1101. The semiconductor device1101includes a substrate310. The substrate310may include silicon carbide (SiC), sapphire, or silicon (Si). In the present embodiment, the substrate310is a silicon substrate.

The semiconductor device1101also includes a nucleation layer320formed over the substrate310. The nucleation layer320has a lattice structure and/or a thermal expansion coefficient (TEC) suitable for, for example, bridging the lattice mismatch and/or the TEC mismatch between the substrate310and a layer thereover. In some embodiments, the nucleation layer320includes aluminum nitride (AlN).

The semiconductor device1101also includes a buffer layer330formed over the nucleation layer320. In some embodiments, the buffer layer330includes a graded aluminum-gallium nitride (AlxGa1-xN, x is the aluminum content ratio in the aluminum-gallium constituent, 0<x<1) layer. In some embodiments, the buffer layer330may include multiple aluminum gallium nitride layers with different x ratios. In some other embodiments, instead of having multiple layers with different x ratios, the buffer layer330may have a continuous gradient of the ratio x.

The semiconductor device1101also includes a super lattice structure340formed over the buffer layer330. The super lattice structure340may include a number of first group III-V layers and a number of second group III-V layers (not separately labeled) vertically and alternatingly stacked, and the first group III-V layers have a lattice constant different than the second group III-V layers. For example, the first group III-V layers may include AlN, and the second group III-V layers may include GaN.

The semiconductor device1101also includes a channel layer350formed over the super lattice structure340. In some embodiments, the channel layer350may include one or more Group III-V compound layers such as GaN, AlGaN, InGaN and InAlGaN. In one embodiment, the channel layer350includes a GaN layer.

The semiconductor device1101also includes an active layer360formed over the channel layer350. The active layer360includes one or more Group III-V compound layers which are different from the Group III-V compound layers of the channel layer350in composition. In an embodiment, the active layer360may include AlGaN. The active layer360is configured to cause a 2-dimensional electron gas (2DEG) to be formed in the channel layer350along an interface between the channel layer350and the active layer360. A heterojunction is formed between the active layer360and the channel layer350having two different semiconductor materials.

The semiconductor device1101also includes a source feature365and a drain feature370disposed over the active layer360. In the present embodiments, the source feature365and drain feature370are formed to be in ohmic contact with an upper surface of the active layer360. In some situations, the source feature365may be referred to as a source contact365, and the drain feature370may be referred to as a drain contact370. In some embodiments, the source contact365and the drain contact370may have the same composition and may include a metal layer that include titanium (Ti), titanium nitride (TiN), aluminum copper (AlCu) alloy, combinations thereof, or other suitable materials.

The semiconductor device1101also includes a gate structure375disposed over the active layer360and between the source feature365and the drain feature370. The gate structure375includes a gate dielectric layer and a gate electrode layer disposed over the gate dielectric layer. The gate electrode includes a conductive material layer. In various examples, the conductive material layer may include nickel (Ni), gold (Au) copper (Cu), titanium (Ti), titanium nitride (TiN), titanium tungsten (TiW), titanium tungsten nitride (TiWN), tungsten (W) or tungsten nitride (WN), combinations thereof, or other suitable materials. In the present embodiments, along the X direction, a distance Lgd1 between the gate structure375and the drain contact370is greater than a distance between the gate structure and the source contact365. A dielectric layer380is formed over the source feature365, the drain feature370, and the gate structure375. The dielectric layer380may include multiple layers and each layer may include silicon oxide (SiO2), silicon nitride (SiN), combinations thereof, or other suitable materials. The semiconductor device1101also includes contact vias penetrating through the dielectric layer380and in direct contact with the source feature365, the drain feature370, or the gate structure375. For example, the semiconductor device1101includes a contact via385extending through the dielectric layer380and in direct contact with the source feature365. In some embodiments, the semiconductor device1101may also include one or more field plates (e.g., field plate390) disposed over the dielectric layer380. In the present embodiments, the semiconductor device1101includes a field plate390disposed over the dielectric layer380and electrically coupled to the source feature365via the contact via385.

FIG.4illustrates an exemplary cross-sectional view of the transistor160implemented in the auxiliary circuit1630shown inFIG.1, according to various aspects of the present disclosure. In the present embodiments, a structure of the transistor160is in a way similar to that of the switch transistor1101. For example, the transistor160also includes the substrate310, the nucleation layer320formed over the substrate310, the buffer layer330formed over the nucleation layer320, the super lattice structure340formed over the buffer layer330, the channel layer350formed over the super lattice structure340, and the active layer360formed over the channel layer. The transistor160also includes a source feature465and a drain feature470disposed over the active layer360, and a gate structure475disposed between the source feature465and the drain feature470. A distance Lgd2 between the gate structure475and the drain feature470is greater than a distance between the gate structure475and the source feature465. Since the auxiliary circuit130is configured to provide surge protection for the transistors1101,1102, . . . ,110Nin the main circuit110, a breakdown voltage BV2 of the transistor160is higher than a breakdown voltage BV1 of the switch transistor1101. In the present embodiments, the distance Lgd2 between the gate structure475and the drain feature470is greater than the distance Lgd1 between the gate structure375and the drain feature370such that the transistor160has a higher breakdown voltage than the switch transistor1101.

FIG.5illustrates a fragmentary top view of the switch transistor1101, according to various aspects of the present disclosure. In the present embodiments, the gate structure375extends along the Y direction and has a gate width Wg1 along the Y direction. In an embodiment, the gate width Wg1 is between about 50 um and about 150 um. The distance Lgd1 may be configured accordingly with respect to a satisfactory breakdown voltage BV1 of the switch transistor1101. In an embodiment, the breakdown voltage BV1 of the switch transistor1101may be about 500V, and the distance Lgd1 may be between about 6 um and about 18 um nm. The gate width Wg1 and the distance Lgd1 may affect a footprint of the transistor1101.

FIG.6illustrates a fragmentary top view of the transistor160, according to various aspects of the present disclosure. In the present embodiments, the gate structure475extends along the Y direction and has a gate width Wg2 along the Y direction. In an embodiment, Wg2 is between about 50 um and about 150 um. The distance Lgd2 is greater than the distance Lgd1. The distance Lgd2 may be configured with respect to a satisfactory breakdown voltage BV2 of the transistor160and is no more than 1000 um. If the distance Lgd2 is greater than 1000 um, a larger current is needed to turn on the transistor160, more time may be needed to charge the capacitor to generate this larger current, and the transistor160may thus not be able to discharge the surge voltage in time.

In an embodiment, the breakdown voltage BV2 of the transistor160may be about 800V, and the distance Lgd2 is greater than the distance Lgd1 and may be between about 9 um and about 27 um. In an embodiment, to provide the transistor160a higher breakdown voltage (e.g., 1000V), the distance Lgd2 may be increased and between about 12 um and about 35 um. In an embodiment, the distance Lgd2 may be greater than 23 um. The gate width Wg2 and the distance Lgd2 may affect a footprint of the transistor160. In some embodiments, the gate width Wg2 may be equal to the gate width Wg1. In an embodiment, a footprint of the transistor160is greater than a footprint of each switch transistor of the switch transistors1101,1102, . . . ,110Nin the main circuit110, and the footprint of the transistor160is less than a total footprint of the switch transistors1101,1102, . . . ,110Nin the main circuit110.

FIG.7illustrates simulated timing diagrams710,720,730, and740showing voltages over time or current over time at different nodes of the switching circuit100shown inFIG.1. More specifically, timing diagram710represents a voltage signal Vpp provided by the power line115, timing diagram720represents a voltage signal Vdd measured at the second node110bof the main circuit110, timing diagram730represents a voltage signal Vg measured at the first node110aof the main circuit110, and timing diagram740represents a current Irq that flows through the transistor160.

In this present simulation, the power line115is configured to provide a voltage Vpp. A normal level V1 of the voltage Vpp is ranged between about 300V and about 500V, the switch transistors1101,1102, . . . ,110Nin the main circuit110each has the distance Lgd1 (shown inFIG.3andFIG.5), each transistor in the main circuit110has an operation voltage that is about 400V and a breakdown voltage that is about 500V, and the transistor160in the auxiliary circuit130has a distance Lgd2 (shown inFIG.4andFIG.6), operation voltage that is about 650V, and a breakdown voltage that is about 800V. When the switch transistors1101,1102, . . . ,110Nin the main circuit110are turned off, as represented by the timing diagram730, the power line115provides surge voltages V2. The surge voltages may be greater than 800V. By providing the auxiliary circuit130, as represented by the timing diagram720, the voltage Vdd that is supplied to the main circuit110may be between about 395V and about 405V, which is less than the breakdown voltage of the transistors1101,1102, . . . ,110Nin the main circuit110, and the surge voltage is discharged by the transistor160, as presented by the timing diagram740. Therefore, providing the auxiliary circuit130to increase the breakdown voltage of the switching circuit100may advantageously prevent the switch transistors1101,1102, . . . ,110Nin the main circuit110from being damaged by the surge voltage V2. Besides providing surge protection, compared with embodiments where the breakdown voltage of the transistors1101,1102, . . . ,110Nin the main circuit110are increased to prevent damages due to surge voltage, the implementation of the auxiliary circuit130also advantageously reduces a total footprint of the switching circuit100.

FIG.8illustrates a flow chart of a method800for configuring a switch circuit to have an increased breakdown voltage. In an embodiment, the method800includes, at802, determining a configuration of switch transistors in a main circuit. For example, a breakdown voltage BV1 and the length Lgd1 of each switch transistor of the transistors1101,1102, . . . ,110Nin the main circuit110may be determined. The method800also includes, at804, estimating a surge voltage/spike voltage (e.g., V2) of a power line (e.g., power line115) that is configured to provide power supply to the main circuit110. The method800also includes, at806, in response to the configuration of the main circuit and the surge/spike voltage, determining a configuration of an auxiliary circuit to provide a surge/spike protection for the main circuit110. For example, based on the surge voltage V2 and the breakdown voltage BV1 of the switch transistors1101,1102, . . . ,110Nin the main circuit110, a breakdown voltage BV2 of the transistor160in the auxiliary circuit130may be determined. The method800also includes, at808, in response to the determined breakdown voltage BV2 of the transistor160, determining a configuration of the transistor160. For example, a distance Lgd2 between a gate structure and a drain feature of the transistor160may be determined such that the transistor160has the breakdown voltage BV2. As such, the auxiliary circuit130may be configured to provide surge/spike protection for the main circuit110. In other words, the breakdown voltage of the switching circuit100is increased by the auxiliary circuit130.

FIG.9illustrates a schematic of another exemplary simplified switching circuit100′ having an auxiliary circuit130′, according to various aspects of the present disclosure. In the present embodiments, the switching circuit100′ includes the main circuit110having the first node110aelectrically coupled to the drive circuit120, the second node110belectrically coupled to the power line115, and the third node110celectrically coupled to a reference voltage such as a ground voltage. As described above with reference toFIGS.1and2, the main circuit110includes a number of switch transistors1101,1102, . . . ,110Nconnected in parallel.

The switching circuit100′ also includes an auxiliary circuit130′ electrically coupled to the second node110bof the main circuit110. The auxiliary circuit130′ includes the capacitor140. One terminal140aof the capacitor140is electrically coupled to the second node110bof the main circuit110. The auxiliary circuit130′ also includes the resistor150electrically coupled to the other terminal140bof the capacitor140a. The auxiliary circuit130′ also includes the transistor160. The first terminal160a(e.g., gate terminal) of the transistor160is electrically coupled to the terminal140bof the capacitor140, the second terminal160b(e.g., drain terminal) of the transistor160is electrically coupled to the second node110bof the main circuit110, and the third terminal160cis configured to receive a reference voltage (e.g., ground voltage GND). In an embodiment, the transistor160includes a GaN-based HEMT and has a breakdown voltage BV2 that is higher than the breakdown voltage BV1 of the switching transistors in the main circuit110. Thus, when the switching transistors in the main circuit110are turned off and when a surge voltage V2 is generated, the capacitor140may turn on the transistor160and thus the surge voltage V2 may be discharged by the transistor160.

As described above, when switch transistors1101,1102, . . . ,110Nin the main circuit110are turned off, a surge voltage V2 that is greater than the voltage V1 and greater than the breakdown voltage BV1 may be created. The gate terminal (i.e., the first terminal160a) of the transistor160is susceptible to damage due to voltage overshoot spikes that exceed its gate breakdown voltage. The auxiliary circuit130′ includes a gate protection circuit170electrically coupled to the terminal140bof the capacitor140and the first terminal160aof the transistor160. More specifically, the gate protection circuit170includes one terminal connected to the terminal140bof the capacitor140, and the other terminal configured to receive a reference voltage (e.g., a ground voltage). In the present embodiments, the gate protection circuit170includes a number of diodes1701, . . . ,170M, connected in serial. M is an integer and is greater than 1. In some embodiments, M may be between 2 and 10, depending on the threshold voltage of each of the diodes1701, . . . ,170Mand the gate breakdown voltage of the transistor160. Current that is generated due to the surge event may partially flow through the path170p. By implementing the gate protection circuit170, a gate input voltage of the transistor160may be clamped during a surge event, protecting the gate terminal of the transistor160from being damaged. In some embodiments, the gate protection circuit170may consume portions of the surge voltage not consumed by the resistor150or the transistor160.

FIG.10illustrates simulated timing diagrams1010,1020,1030,1040, and1050showing the voltage or current over time at different nodes of the switching circuit shown inFIG.9. More specifically, timing diagram1010represents a voltage signal Vpp provided by the power line115, timing diagram1020represents a voltage signal Vdd measured at the second node110bof the main circuit110, timing diagram930represents a voltage signal Vg measured at the first node110aof the main circuit110, timing diagram1040represents a voltage signal Vr1measured at the terminal140bof the capacitor140, and timing diagram1050represents a current Irq that flows through the transistor160. The timing diagrams1010,1020,1030, and1050are in a way similar to the timing diagrams710,720,730, and740described with reference toFIG.7and repeated description is omitted for reason of simplicity. When the transistors1101,1102, . . . ,110Nin the main circuit110are turned on or off, as represented by the timing diagram1040, current that is generated due to the surge event may flow through the path170p, protecting the gate terminal of the transistor160from being damaged.

Although not intended to be limiting, one or more embodiments of the present disclosure provide many benefits to a switching circuit. In an embodiment, a switching circuit includes a main circuit and an auxiliary circuit electrically coupled to the main circuit. The auxiliary circuit includes a power device (e.g., GaN-based HEMT) and is configured to provide surge protection for the main circuit. The main circuit may include a number of transistors that have a breakdown voltage less than a breakdown voltage of the power device. Therefore, without significantly consuming an amount of real estate of an IC chip, the main circuit may be protected from damage due to voltage overshoot spikes. In some embodiments, the breakdown voltage of the power device may be adjusted by changing a distance between a gate structure and a drain feature of the power device. As such, by providing the power device different breakdown voltages, without changing the configuration of the main circuit, the switching circuit may be designed to be implemented for various applications having different surge voltages. In some embodiments, a gate protection circuit is electrically coupled to the power device to protect the gate terminal of the power device. In some embodiments, the auxiliary circuit may be implemented to provide surge protection for other circuits that can adjust the distance between the gate structure and the drain feature to design breakdown voltages. The auxiliary circuit may be readily integrated into existing HEMTs and circuits.

The present disclosure provides for many different embodiments. Semiconductor structures and methods of fabrication thereof are disclosed herein. In one exemplary aspect, the present disclosure is directed to a switching circuit. The switching circuit includes a main circuit including a plurality of first transistors and having a first node, a second node, and a third node, where the main circuit is operative in response to a control signal received by the first node, and the second node is configured to receive a supply voltage. The switching circuit also includes an auxiliary circuit electrically coupled to the second node of the main circuit and configured to provide surge protection for the main circuit, where the auxiliary circuit comprises a second transistor. A breakdown voltage of the second transistor is different than a breakdown voltage of each first transistor of the plurality of first transistors.

In some embodiments, the breakdown voltage of the second transistor may be greater than the breakdown voltage of each first transistor of the plurality of first transistors. In an embodiment, each first transistor of the plurality of first transistors may include a gate terminal electrically coupled to the first node, a drain terminal electrically coupled to the second node, and a source terminal electrically coupled to the third node. In an embodiment, the auxiliary circuit may also include a capacitive element comprising a first terminal and a second terminal, where the first terminal of the capacitive element may be electrically coupled to the second node. The auxiliary circuit may also include a resistive element comprising a third terminal and a fourth terminal, the third terminal being electrically coupled to the second terminal, and the fourth terminal being electrically coupled to a ground voltage. In an embodiment, a gate terminal of the second transistor may be electrically coupled to the second terminal of the capacitive element, a drain terminal of the second transistor may be electrically coupled to the second node, and a source terminal of the second transistor may be electrically coupled to a ground voltage. In an embodiment, the switching circuit may also include a gate protection circuit electrically coupled to the second terminal of the capacitive element, where the gate protection circuit may include a plurality of diodes connected in serial. In an embodiment, the first transistor may be a first III-V based high-electron-mobility transistor (HEMT) and the second transistor may be a second III-V based HEMT. In an embodiment, a substrate of the first III-V based HEMT and a substrate of the second III-V based HEMT may include silicon. In an embodiment, the first III-V based HEMT may be a first gate structure and a first drain feature, and the first gate structure may be spaced apart from the first drain feature by a first distance along a first direction, and the second III-V based HEMT may be a second gate structure and a second drain feature, and the second gate structure may be spaced apart from the second drain feature by a second distance along the first direction, where the second distance may be greater than the first distance. In an embodiment, a width of the first gate structure along a second direction may be equal to a width of the second gate structure along the second direction, the second direction being substantially perpendicular to the first direction.

In another exemplary aspect, the present disclosure is directed to a circuit. The circuit includes a drain voltage input terminal configured to receive a first voltage, a source voltage input terminal configured to receive a second voltage, a main circuit connected between the drain voltage input terminal and the source voltage input terminal and comprising a plurality of first transistors in parallel connection, a second transistor comprising a drain terminal electrically coupled to the drain voltage input terminal, a source terminal electrically coupled to the source voltage input terminal, and a gate terminal, a capacitive element comprising a first terminal and a second terminal, the first terminal of the capacitive element being electrically coupled to the drain voltage input terminal, and a resistive element comprising a third terminal and a fourth terminal, the third terminal being electrically coupled to the second terminal, and the fourth terminal being electrically coupled to the source voltage input terminal, where the gate terminal of the second transistor is electrically coupled to the second terminal of the capacitive element.

In some embodiments, a breakdown voltage of the second transistor may be greater than a breakdown voltage of each first transistor of the plurality of first transistors. In some embodiments, a sum of the breakdown voltage of the second transistor and the breakdown voltage of each first transistor of the plurality of first transistors may be greater than a surge voltage associated with the first voltage. In some embodiments, an operation voltage of the second transistor may be greater than an operation voltage of each first transistor of the plurality of first transistors. In some embodiments, a footprint of the second transistor may be greater than a footprint of each first transistor of the plurality of first transistors and may be smaller than a total footprint of the plurality of first transistors. In some embodiments, the circuit may also include a plurality of diodes connected in serial and connected between the second terminal of the capacitive element and the source voltage input terminal.

In yet another exemplary aspect, the present disclosure is directed to a circuit. The circuit includes a first circuit configured to receive a power supply voltage from a power line and comprising a plurality of first power devices connected in parallel, wherein each first power device of the plurality of first power devices comprises a first breakdown voltage, a second circuit configured to provide surge protection to the first circuit and comprising a second power device having a second breakdown voltage, where the first breakdown voltage is less than the second breakdown voltage.

In some embodiments, the second circuit may also include a capacitive element comprising a first terminal and a second terminal, the first terminal of the capacitive element being electrically coupled to the power line, and a resistive element comprising a third terminal and a fourth terminal, the third terminal being electrically coupled to the second terminal, and the fourth terminal being electrically coupled to a ground voltage, where a gate terminal of the second power device may be electrically coupled to the second terminal of the capacitive element, a drain terminal of the second power device may be electrically coupled to the power line, and a source terminal of the second power device may be electrically coupled to the ground voltage. In some embodiments, the circuit may also include a gate protection circuit electrically connected between the second terminal of the capacitive element and the ground voltage, where the gate protection circuit may include a plurality of diodes connected in serial. In some embodiments, each of the plurality of first power devices may include a gate structure spaced from a drain feature by a first distance, the second power device may include a gate structure spaced from a drain feature by a second distance, where the second distance may include greater than the first distance.