Method of integrated circuit fabrication

A method for fabricating an integrated circuit including forming a first trench in a rear side of a semiconductor wafer, wherein the first trench has a depth extending partially through a thickness of the semiconductor wafer, coating the rear side with a layer of coating material, including filling the first trench with the coating material, and forming a second trench in a front side of the semiconductor wafer, wherein the second trench is aligned with and has a width less than a width of the first trench, and wherein the second trench has a depth extending at least through a remaining portion of the semiconductor wafer so as to be in communication with the coating material filling the first trench.

BACKGROUND

Multiples of integrated circuits are typically formed in a grid-like pattern on an active or front side of semiconductor substrate, such as silicon wafer. A metal layer is often deposited on a rear side of the wafer, opposite the front side. After formation of the integrated circuits, such as by photolithographic processes, for example, the wafer is separated or partitioned into a plurality of semiconductor chips by cutting or sawing the wafer along lines between the individual integrated circuits. This process often referred to as “dicing” or “singulating”.

As mentioned above, dicing is commonly performed by using a dicing blade to saw or grind the wafer between the individual integrated circuits of the grid, including the metal layer if present. However, sawing through the wafer in this fashion can create defects, such as cracking and chipping of the semiconductor material along the cut edges proximate to the rear side of the wafer, and chipping, cracking, and burring along the cut edges of the metal layer.

Such defects can adversely impact the electrical characteristics of the semiconductor chip and also diminish its physical stability which can create problems during subsequent die bonding processes. Tiny chips of semiconductor material and metal created by sawing can also disturb chip packaging processes. Additionally, cracks in the semiconductor chip, particularly in the semiconductor material, can interrupt contact between the semiconductor material and the metal layer, with such cracks also being known to propagate when the semiconductor chip is thermally cycled.

For these and other reasons, there is a need for an improved semiconductor wafer dicing or singulating process.

SUMMARY

In one embodiment, a method is provided for fabricating an integrated circuit including forming a first trench in a rear side of a semiconductor wafer, wherein the first trench has a depth extending partially through a thickness of the semiconductor wafer, coating the rear side with a layer of coating material, including filling the first trench with the coating material, and forming a second trench in a front side of the semiconductor wafer, wherein the second trench is aligned with and has a width less than a width of the first trench, and wherein the second trench has a depth extending at least through a remaining portion of the semiconductor wafer so as to be in communication with the coating material filling the first trench.

DETAILED DESCRIPTION

Embodiments described herein provide methods for dicing or singulating a semiconductor substrate, such as a silicon wafer, which reduce or eliminate cutting- or sawing-related defects (e.g. chipping, cracking) in the resulting individual or singulated semiconductor chips.

FIG. 1is a top view of an example semiconductor wafer30to which embodiments of dicing or singulating processes as described herein may be applied. In one embodiment, wafer30is formed in a flat, plate-like shape from a semiconductor material, such as silicon. Wafer30includes a semiconductor layer31(e.g. silicon) having an active or front surface32in which a plurality of integrated circuits34(as indicated by squares) have been formed in a grid-like pattern, such as through photolithographic processes, for example. In one embodiment, with reference to FIG.2below, wafer30includes a metal layer36deposited on a rear surface38, which is opposite front surface32. In one embodiment, kerf or dicing lines, as indicated at40, are provided (e.g. scribed) on front surface32both vertically and horizontally in a grid like fashion between individual integrated circuits34. Dicing lines40indicate the lines along which wafer30will be diced or singulated to form individual semiconductor chips.

FIG. 2is a cross-sectional view of an individual semiconductor chip50after being singulated from a wafer, such as wafer30, using a “die cutter” or “dicing saw” according to conventional saw-cutting or grinding techniques. As described above, sawing through wafer30, including through metal layer36, produces undesirable burrs52and/or cracks54. Burrs52protrude from metal layer36and adversely affect electrical performance/contact of the chip when coupled to another electronic device. Cracks54can potentially interrupt the electrical contact between semiconductor layer31and metal layer36. In addition, cracks54in semiconductor layer31are known to propagate when semiconductor chip50is thermally cycled and potentially interrupting electrical connection for the chip.

FIGS. 3 through 7below, with further reference toFIGS. 1 and 2, describe embodiments of die cutting or singulating processes which reduce and/or eliminate the described defects.FIG. 3is a perspective view illustrating a portion of wafer30. For clarity, integrated circuits34and kerf lines40are illustrated in dashed lines. Together, semiconductor layer31and metal layer36provide wafer30with a total thickness DW, as indicated at56. It is noted that the relative depths of semiconductor layer31and metal layer36as shown inFIG. 3are for illustrative purposes only and may vary for different types of wafers. In one example embodiment, semiconductor layer31and metal layer36each have a thickness of 10 μm, such that wafer30has a total thickness DW56of 20 μm.

With reference toFIG. 4, according to one embodiment, wafer30is flipped (relative toFIG. 3) and, contrary to conventional techniques, dicing trenches, such as trench60, are formed in rear surface38along kerf lines, such as kerf line40′, which are aligned with kerf lines40on front surface32. In one embodiment, as illustrated byFIG. 4, the trenches are cut using a dicing blade62. InFIG. 4, dicing blade62is illustrated as having already formed trench60and as in the process of cutting a second trench64along kerf line40′. Dicing blade62has a kerf width such that the trenches, such as trench60, have a width W1, as illustrated at66. Dicing blade62cuts at a depth such that the trenches have a desired depth D1, as illustrated at68, which comprises a portion of total thickness DW56of wafer30. In one embodiment, the depth D168is at least equal to 20% of the total thickness DW56. In one embodiment, depth D168is not more than 80% the of the total thickness DW56of wafer30.

Although illustrated and described inFIG. 4, and other Figures herein, as being cut with a conventional dicing blade, it is noted that trenches, such as trench60, may be formed using dicing techniques such as laser dicing, water-guided laser dicing, waterbeam dicing (e.g. containing abrasives), plasma dicing, or any other suitable dicing technique.

With reference toFIG. 5, after formation of the trenches on rear side38, such as trenches60and64, a coating or layer70having a thickness D272is applied to cover rear side38of wafer30and to fill the trenches, including trenches60and64. In one embodiment, coating70comprises a non-conductive material. In one embodiment, coating70comprises a photoresist material such as a polymer material, for example. In one embodiment, coating70comprises a non-conductive thermoset epoxy material. In one embodiment, coating70comprises a non-conductive resin-material. In one embodiment, coating70has a thickness Dc72in a range from approximately 1 μm to 100 μm. In one embodiment, thickness Dc72is approximately equal to 50% of the total thickness DW.

With reference toFIG. 6, after coating70has been applied, wafer30is flipped (relative toFIG. 5), and dicing trenches, such as trench74, are formed in front side32along kerf lines40. InFIG. 6, dicing blade76is illustrated as having already cut trench74and as in the process of cutting a trench78along kerf line40. As illustrated, the trenches in front face32are aligned with the trenches in rear face32, as illustrated by trenches74and78being respectively aligned with trenches60and64.

In one embodiment, dicing blade76has a kerf width which is narrower than the kerf width of dicing blade62used to form the trenches in rear side38, such that the trenches formed in front surface32, including trenches74and78, have a width W2, as illustrated at80, which is narrower than width W166of the trenches formed in rear side38, including trenches60and64.

In one embodiment, dicing blade76cuts at a depth such that the trenches in front surface32, including trenches74and78, have a desired depth D2, as illustrated at82, which is substantially equal to total thickness DW56of wafer30minus depth D168of the trenches in rear side38. In this fashion, the trenches in front surface32have a depth D168such that the trenches in front surface32join or are in communication with the material or coating70filling the trenches the rear surface38, as illustrated by trench74and the material of coating70filling trench60.

With reference toFIG. 7, which is a cross-section of the portion of wafer30illustrated byFIG. 6, in one embodiment, a dicing blade86having a kerf width which is less than the kerf width of dicing blade76(seeFIG. 6) is employed to singulate the individual semiconductor chips, such as semiconductor chip90, from wafer30. As illustrated, dicing blade76is aligned with trenches in front side32, such as trenches74and78, and cuts through the coating70filling the trenches in and covering the rear side38, such as trenches60and64, so as to separate the individual semiconductor chips from wafer30, such as semiconductor chip90. In one embodiment, dicing blade76is substantially centered with trenches in front side32. In other embodiment, dicing blade76is aligned with, but off-center from trenches in front side32so as to make off-center cuts.

FIG. 8is perspective view semiconductor chip90ofFIG. 7after it has been separated or singulated from wafer30. Although, for clarity, the cutting of wafer30is illustrated above as taking place in one direction, it is noted that the cutting is carried out in a grid-like fashion in both the vertical and horizontal directions along kerf lines40(seeFIG. 1). As such, as illustrated byFIG. 8, after being singulated from wafer30as described above byFIGS. 4-7, a lower portion of semiconductor chip90, including all four sides and bottom side38, is encased or framed by a layer of coating70.

FIGS. 9A and 9Brespectively illustrate end and top views of semiconductor chip90ofFIG. 8. In such an embodiment, coating70framing semiconductor chip90extend beyond the edges of semiconductor layer31by a distance DEindicated at92.

The framing or encasement by coating70protects semiconductor chip90from potential damage resulting from handling during subsequent die bonding processes. Additionally, by making the final cut to singulate semiconductor chip90from wafer30through the material of coating70, the defects resulting from cutting directly through the material of wafer30(e.g. chipping and cracking of semiconductor material30, and burring of metal36) is reduced and/or eliminated.

FIGS. 10A and 10Brespectively illustrate and end top views of an alternate embodiment of semiconductor chip90ofFIG. 6. With reference toFIG. 6, in lieu of cutting only partially through wafer30to form trenches74and78, dicing blade76is employed to cut completely through wafer30and through the coating70covering rear side38and filling trenches60and64. As a result, while coating70still encases or frames a lower portion of semiconductor chip90, coating70does not extend beyond, but is substantially flush with semiconductor layer31.

FIGS.11and12A-B, with further reference toFIG. 6, illustrate another alternate embodiment for forming semiconductor chip90. With reference toFIG. 11(which illustrates a section through a portion of wafer30), after being cut into front surface32with dicing blade76, trenches74and78are filled with a material the same as that of coating70such that coating70fills trenches60and64in rear side38and trenches74and78in front side32. A dicing blade having a kerf width narrower than that of dicing blade76, such as dicing blade86(seeFIG. 7), is then aligned with trenches74and78and used to cut completely through coating70and separate or singulate semiconductor chip90from wafer30. In one embodiment, dicing blade86is substantially centered with trenches74and78.

FIGS. 12A and 12Brespectively illustrate end and top views of the embodiment of semiconductor chip90formed by the process illustrated ofFIG. 11. As illustrated, coating70frames or encases all but front side32of semiconductor layer31of singulated semiconductor chip90. In this embodiment, coating70is thicker around a lower portion of semiconductor chip90in areas corresponding to trenches60and64formed in rear side38than around an upper portion of semiconductor chip90in areas corresponding to trenches74and78formed in front side32.

FIGS. 13 through 17below illustrate alternate embodiments for singulating semiconductor chips from a wafer.FIG. 13is a cross-sectional view of a portion of a wafer130, similar to wafer30ofFIG. 1. It is noted, however, that a metal layer is not illustrated along a rear side138of a semiconductor layer131of wafer130. In one embodiment, trenches are cut in rear side138, such as trenches160and164, using a beveled dicing blade162such that the bottom of trenches160and164are correspondingly beveled so as to have first and second angled legs161aand161bforming a desired bevel angle θ163there between.

With reference toFIG. 14, after trenches160and164are formed, a coating170, similar to coating70described above, is applied to cover rear side138and to fill trenches160and164. Wafer130is then flipped, relative toFIG. 13, and a dicing blade186is aligned with trenches160and164and used to cut completely through wafer130and coating170so as to separate or singulate a semiconductor chip, such as semiconductor chip190, from wafer130. In one embodiment, dicing blade186is substantially centered with trenches160and164.

FIG. 15is a cross-sectional view of semiconductor chip190ofFIG. 14. Semiconductor chip190is similar to semiconductor chip90as illustrated byFIGS. 10A and 10Bin that coating170frames a lower portion of semiconductor chip190and is flush with semiconductor layer131along its sides. However, due to angled legs161aand161bforming the beveled bottoms of trenches160and164, a lower edge of semiconductor layer131has an angled or beveled segment165having a length LBwhich is in contact with coating170. In addition to further reducing the potential for cracking or other defects, the beveled lower edge of semiconductor layer131strengthens the bond between semiconductor layer131and coating170, thereby increasing the robustness of coating170and semiconductor chip190.

It is noted that the strength or robustness of the bond between coating170and semiconductor chip190is proportional to the bevel angle θ163and the length LBof the beveled segment165of semiconductor layer131. In one embodiment, the length LBof beveled segment165is adjusted by varying a depth DB167(seeFIG. 14) of trenches160and164by varying the cutting depth of dicing blade162. In one embodiment, the bevel angle θ163is adjusted by using a different dicing blade162. In one embodiment, the bevel angle θ163(i.e. the bevel of the dicing blade) is within in range from 30° to 135°, such that an angle β of the beveled segment165to rear side138, as indicated at169(seeFIG. 15), is within a range from 105° to 165°. In one embodiment, depth DB167of trenches160and164and bevel angle θ163are adjusted such that the length LBof beveled segment165is in a range from 5 to 150 μm.

FIG. 16is a cross-sectional view of wafer130and illustrates an alternate embodiment for forming semiconductor chip190. With further reference toFIG. 14, after coating170is applied to cover rear side138and fill trenches160and164, wafer130is flipped and a dicing blade176is employed to cut trenches174and178in front side132which respectively align with trenches160and164. In one embodiment, as illustrated, trenches174and178having a width less than that of trenches160and164, and are cut to depth so at to be in communication with trenches160and164but so as not extend beyond rear side138.

In one embodiment, a dicing blade186, having a kerf width less than that of dicing blade176, is aligned with trenches174and178and subsequently used to cut completely through the remaining coating170so as to singulate semiconductor chip190from wafer130. In one embodiment, dicing blade186is substantially centered with trenches174and178. Relative to the embodiment ofFIG. 15, the embodiment ofFIG. 16still includes a lower edge of semiconductor layer131having a beveled edge, but coating170framing singulated semiconductor chip190now includes a portion extending beyond the boundaries of semiconductor layer131.

FIG. 17is a cross-sectional view of wafer130and illustrates another embodiment for forming semiconductor chip190. With further reference toFIG. 16, after being cut into front surface132, trenches174and178are filled with a same material as that of coating170so that coating170now covers rear side138and fills trenches160and164in rear side138and trenches174and178in front side132. Dicing blade186is subsequently aligned with trenches174and178and employed to cut completely through coating170and separate or singulate semiconductor chip190from wafer130. In one embodiment, dicing blade186is substantially centered with trenches174and178. Although not explicitly illustrated, the resulting singulated semiconductor chip190is similar to semiconductor chip90illustrated above byFIGS. 12A and 12Bin that coating170frames or encases all but front side132of semiconductor layer131, but semiconductor layer131additionally includes a beveled lower edge (as described above) that is in contact with coating170.

FIGS. 18-21below illustrate additional embodiments for singulating semiconductor chip190. The processes ofFIGS. 18-21are similar to those illustrated byFIGS. 13-17, but vary with respect to the depth of cut made by beveled dicing blade162to form trenches160and162in rear side138of wafer130.FIG. 18is a cross-sectional view of a portion of wafer130. As illustrated, beveled dicing blade162is employed to cut trenches160and164in rear side138, but cuts to a deeper depth DB167relative to the embodiments illustrated byFIGS. 13-17such that trenches160and164now have a beveled bottom and vertical sidewall portions171aand171b.

With reference toFIG. 19, after trenches160and164are formed, coating170is applied to cover rear side138and to fill trenches160and164, and wafer130is subsequently flipped, relative toFIG. 18. In one embodiment, dicing blade186is aligned with trenches160and164and employed to cut completely through wafer130and coating170so as to separate or singulate semiconductor chip190from wafer130. In one embodiment, dicing blade186is substantially centered with trenches160and164.

FIG. 20is a cross-sectional view of semiconductor chip190ofFIG. 19. The embodiment of semiconductor190ofFIG. 20is similar to that illustrated byFIG. 15, but that in addition to semiconductor layer131having a lower edge with a beveled segment165of length LB, the lower edge also has a segment173formed by vertical sidewall portions171aand171b, which further increases the robustness of the bond between coating170and semiconductor layer131.

With reference toFIG. 21, in one embodiment, prior to singulating wafer30with dicing blade186as illustrated byFIG. 19, dicing blade176is employed to cut trenches174and178in front side132of wafer130and which are aligned with trenches160and164. In one embodiment, trenches174and178have a width less than that of trenches160and164, and are cut to a depth so as to extend into coating170in trenches160and164but not beyond rear side138. Dicing blade186is subsequently aligned with trenches174and178and employed to completely cut through the remaining portion of coating170in trenches160and164so as to separate or singulate semiconductor chip190from wafer130. In one embodiment, dicing blade186is substantially centered with trenches174and178. The semiconductor chip190resulting from the process described byFIG. 21is similar to that ofFIG. 16, but includes both a beveled edge and a vertical portion along the lower edge of semiconductor layer131.

FIG. 22is a cross-sectional view of wafer130and illustrates another embodiment for forming semiconductor chip190. With further reference toFIG. 21, after being cut into front surface132, trenches174and178are filled with a same material as that of coating170so that coating170now covers rear side138and fills trenches160and164in rear side138and trenches174and178in front side132. Dicing blade186is subsequently aligned with trenches174and178and employed to cut completely through coating170and separate or singulate semiconductor chip190from wafer130. In one embodiment, dicing blade186is substantially centered with trenches174and178. Although not explicitly illustrated, the resulting singulated semiconductor chip190is similar to semiconductor chip90resulting from the process ofFIG. 17and illustrated above byFIGS. 12A and 12Bin that coating170frames or encases all but front side132of semiconductor layer131, but in addition to a beveled edge, semiconductor layer131additionally includes a vertical portion161.