Reference voltage generator, display device including the same, and method of driving display device

Provided is a display device which comprises a display panel including a plurality of pixels displaying an image based on a driving voltage, a reference voltage generator converting a sensing driving voltage generated by measuring the driving voltage into a sensing driving current, converting a preset reference driving voltage into a reference driving current, comparing the sensing driving current and the reference driving current, and generating a first reference voltage and a second reference voltage based on a difference between the sensing driving current and the reference driving current, a gamma voltage generator generating a plurality of gamma voltages by dividing the first reference voltage and the second reference voltage, and a data driver converting image data into a data voltage based on the gamma voltages and providing the data voltage to each of the pixels.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application claims priority under 35 USC § 119 to Korean Patent Application No. 10-2022-0007657 filed on Jan. 19, 2022 in the Korean Intellectual Property Office (KIPO), the entire disclosure of which is incorporated by reference herein.

BACKGROUND

The present disclosure generally relates to a display device. More particularly, the present disclosure relates to a display device including a reference voltage generator and a method of driving the same.

2. Description of the Related Art

With the development of multimedia, the importance of a display device is gradually increasing. Accordingly, various display devices such as a liquid crystal display (LCD) device, an organic light emitting display (OLED) device, and etc. have been developed.

The display device may include a display panel and a driver. The display panel may include a plurality of pixels. The driver may include a scan driver that provides scan signals to the pixels and a data driver that provides data voltages to the pixels. The data driver may convert digital image data into analog data voltages based on gamma voltages (or grayscale voltages).

A driving voltage for driving the pixels may be provided to the display panel. When the driving voltage changes, a driving current may change so that an undesired pattern (e.g., a crosstalk pattern) may be visually recognized on a display screen. The driving voltage may change depending on resistances of wirings in the display panel, a capacitance between the wirings, or the like.

SUMMARY

Embodiments provide a reference voltage generator for rapidly compensating a change in the driving voltage and generating a reference voltage that does not include noise.

Embodiments provide a display device including the reference voltage generator.

Embodiments provide a method of driving the display device.

A display device according to embodiments may include a display panel including a plurality of pixels displaying an image based on a driving voltage, a reference voltage generator converting a sensing driving voltage generated by measuring the driving voltage into a sensing driving current, converting a preset reference driving voltage into a reference driving current, comparing the sensing driving current and the reference driving current, and generating a first reference voltage and a second reference voltage based on a difference between the sensing driving current and the reference driving current, a gamma voltage generator generating a plurality of gamma voltages by dividing the first reference voltage and the second reference voltage, and a data driver converting image data into a data voltage based on the gamma voltages and providing the data voltage to each of the pixels.

In an embodiment, the reference voltage generator may include a first voltage-to-current converter converting the sensing driving voltage into the sensing driving current, a second voltage-to-current converter converting the reference driving voltage into the reference driving current, a current comparator comparing the sensing driving current and the reference driving current, and a current-to-voltage converter generating the first reference voltage and the second reference voltage based on the difference between the sensing driving current and the reference driving current.

In an embodiment, the current-to-voltage converter may include a first current-to-voltage converter generating the first reference voltage based on a first initial reference voltage and the difference between the sensing driving current and the reference driving current, and a second current-to-voltage converter generating the second reference voltage based on a second initial reference voltage and the difference between the sensing driving current and the reference driving current.

In an embodiment, the first current-to-voltage converter may include a first amplifier outputting the first reference voltage based on the first initial reference voltage and the difference between the sensing driving current and the reference driving current, and the second current-to-voltage converter may include a second amplifier outputting the second reference voltage based on the second initial reference voltage and the difference between the sensing driving current and the reference driving current.

In an embodiment, the first voltage-to-current converter may include a first amplifier having a first input terminal to which the sensing driving voltage is applied, a first resistor connected to a second input terminal of the first amplifier, and through which the sensing driving current flows, and a first transistor series-connected to the first resistor, and having a gate electrode connected to an output terminal of the first amplifier. The second voltage-to-current converter may include a second amplifier having a first input terminal to which the reference driving voltage is applied, a second resistor connected to a second input terminal of the second amplifier, and through which the reference driving current flows, and a second transistor series-connected to the second resistor, and having a gate electrode connected to an output terminal of the second amplifier.

In an embodiment, the current comparator may include a first transistor through which the sensing driving current flows, and a second transistor series-connected to the first transistor, and through which the reference driving current flows.

In an embodiment, the first transistor may be an N-type metal oxide semiconductor (“NMOS”) transistor, and the second transistor may be a P-type metal oxide semiconductor (“PMOS”) transistor.

In an embodiment, the reference voltage generator may further include a current minor block transmitting the sensing driving current generated from the first voltage-to-current converter and the reference driving current generated from the second voltage-to-current converter to the current comparator.

In an embodiment, the reference voltage generator may further include a first current clamp limiting a range of the sensing driving current, and a second current clamp limiting a range of the reference driving current.

In an embodiment, the display device may further include a timing controller controlling a driving of the data driver, and providing the reference driving current to the reference voltage generator.

In an embodiment, the reference driving voltage may be a target driving voltage in driving the pixels normally.

In an embodiment, the display device may further include a power supply providing the driving voltage to the pixels, and providing a first initial reference voltage for generating the first reference voltage and a second initial reference voltage in order to generate the second reference voltage to the reference voltage generator.

A reference voltage generator according to embodiments may include a first voltage-to-current converter converting a sensing driving voltage generated by measuring a driving voltage provided to pixels into a sensing driving current, a second voltage-to-current converter converting a preset reference driving voltage into a reference driving current, a current comparator comparing the sensing driving current and the reference driving current, and a current-to-voltage converter generating a first reference voltage and a second reference voltage based on a difference between the sensing driving current and the reference driving current.

In an embodiment, the current-to-voltage converter may include a first current-to-voltage converter generating the first reference voltage based on a first initial reference voltage and the difference between the sensing driving current and the reference driving current, and a second current-to-voltage converter generating the second reference voltage based on a second initial reference voltage and the difference between the sensing driving current and the reference driving current.

In an embodiment, the first current-to-voltage converter may include a first amplifier outputting the first reference voltage based on the first initial reference voltage and the difference between the sensing driving current and the reference driving current, and the second current-to-voltage converter may include a second amplifier outputting the second reference voltage based on the second initial reference voltage and the difference between the sensing driving current and the reference driving current.

In an embodiment, the current comparator may include a first transistor through which the sensing driving current flows, and a second transistor series-connected to the first transistor, and through which the reference driving current flows.

In an embodiment, the first transistor may be an NMOS transistor, and the second transistor may be a PMOS transistor.

In an embodiment, the reference voltage generator may further include a current minor block transmitting the sensing driving current generated from the first voltage-to-current converter and the reference driving current generated from the second voltage-to-current converter to the current comparator.

A method of driving a display device according to embodiments may include steps of generating a sensing driving voltage by measuring a driving voltage provided to a plurality of pixels, converting the sensing driving voltage into a sensing driving current, converting a preset reference driving voltage into a reference driving current, comparing the sensing driving current and the reference driving current, generating a first reference voltage and a second reference voltage based on a difference between the sensing driving current and the reference driving current, and generating a plurality of gamma voltages by dividing the first reference voltage and the second reference voltage.

In an embodiment, generating the first reference voltage and the second reference voltage may be accomplished by generating the first reference voltage based on a first initial reference voltage and the difference between the sensing driving current and the reference driving current, and generating the second reference voltage based on a second initial reference voltage and the difference between the sensing driving current and the reference driving current.

In the reference voltage generator, the display device, and the method of driving the display device according to the embodiments, the sensing driving voltage and the reference driving voltage may be respectively converted into the sensing driving current and the reference driving current, the sensing driving current and the reference driving current may be compared, and the reference voltage may be generated based on the difference between the sensing driving current and the reference driving current, so that the change in the driving voltage may be rapidly compensated, and the reference voltage may not include the noise.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Hereinafter, display devices, reference voltage generators, and methods of driving display devices in accordance with embodiments will be explained in detail with reference to the accompanying drawings.

FIG.1is a block diagram illustrating a display device10according to an embodiment.

Referring toFIG.1, the display device10may include a display panel100, a scan driver200, a data driver300, a gamma voltage generator400, a reference voltage generator500, a power supply600, and a timing controller700.

The display panel100may display an image. The display panel100may include various display elements such as an organic light emitting diode (OLED) or the like. Hereinafter, the display device10including the organic light emitting diode as a display element will be described for convenience. However, the present disclosure is not limited thereto, and the display device10may include various display elements such as a liquid crystal display (LCD) element, an electrophoretic display (EPD) element, and an inorganic light emitting diode, or the like.

The display panel100may include a plurality of pixels PX. Each of the pixels PX may be electrically connected to a data line DL inFIG.2Aand a scan line SL inFIG.2A. Further, each of the pixels PX may be electrically connected to a driving voltage line ELVDDL inFIG.2Aand a common voltage line ELVSSL inFIG.2A, and may receive a driving voltage ELVDD and a common voltage ELVSS from the driving voltage line ELVDDL and the common voltage line ELVSSL, respectively.

Each of the pixels PX may emit light with a luminance corresponding to a data voltage VDT provided through the data line DL in response to a scan signal SS provided through the scan line SL. Configuration and operation of the pixel PX will be described below with reference toFIGS.2A and2B.

The scan driver200(or a gate driver) may generate the scan signal SS (or a gate signal) based on a scan control signal SCS, and may transmit the scan signal SS to the scan line SL. The scan control signal SCS may include a start signal, a clock signal, or the like. For example, the scan driver200may sequentially generate and output the scan signal SS corresponding to the start signal using the clock signal. The scan driver200may be implemented as a shift register, but is not limited thereto. In an embodiment, the scan driver200may be formed on the display panel100. In another embodiment, the scan driver200may be implemented as an integrated circuit and mounted on a flexible circuit board to be connected to the display panel100.

The data driver300may generate the data voltage VDT based on image data ID, a data control signal DCS, and gamma voltages V0to V255, and may provide the data voltage VDT to the data line DL. The data driver300may convert the image data ID into the data voltage VDT based on the gamma voltages V0to V255. The data control signal DCS may include a load signal, a start signal, a clock signal, or the like. In an embodiment, the data driver300may be implemented as an integrated circuit (IC) (e.g., a driving IC), and mounted on a flexible circuit board to be connected to the display panel100.

The gamma voltage generator400(or a grayscale voltage generator) may receive a first reference voltage VR1and a second reference voltage VR2. The gamma voltage generator400may divide the first reference voltage VR1and the second reference voltage VR2to generate the plurality of gamma voltages V0to V255for a plurality of grayscales, and may provide the gamma voltages V0to V255to the data driver300.

The gamma voltages V0to V255(or grayscale voltages) may be intermediate voltages between the first reference voltage VR1and the second reference voltage VR2. The gamma voltages V0to V255may vary in response to the first reference voltage VR1and the second reference voltage VR2. For example, when the first reference voltage VR1and the second reference voltage VR2increase at a constant rate, the gamma voltages V0to V255may also increase at a rate substantially equal to or similar to the rate at which the first reference voltage VR1and the second reference voltage VR2increase.

Hereinafter, for convenience of description, it will be described that a total of 256 grayscales from 0 grayscale (a minimum grayscale) to 255 grayscale (a maximum grayscale) exist, however, more grayscales may exist when expressing the grayscale values in excess of 8 bits. In this case, the minimum grayscale may be the darkest grayscale, and the maximum grayscale may be the brightest grayscale.

The reference voltage generator500may receive a reference driving voltage ELVDD_R, a sensing driving voltage ELVDD_S, a first initial reference voltage VIR1, and a second initial reference voltage VIR2, and may generate or control the first reference voltage VR1and the second reference voltage VR2based on the reference driving voltage ELVDD_R, the sensing driving voltage ELVDD_S, the first initial reference voltage VIR1, and the second initial reference voltage VIR2. The reference voltage generator500may provide the first reference voltage VR1and the second reference voltage VR2to the gamma voltage generator400.

In an embodiment, a voltage level of the first reference voltage VR1and a voltage level of the second reference voltage VR2may be lower than a voltage level of the driving voltage ELVDD. In another embodiment, the voltage level of the first reference voltage VR1may be higher than the voltage level of the driving voltage ELVDD, and the voltage level of the second reference voltage VR2may be lower than the voltage level of the driving voltage ELVDD.

The reference driving voltage ELVDD_R may be a target driving voltage for normally driving the pixels PX of the display panel100. The sensing driving voltage ELVDD_S may be a voltage generated by measuring the driving voltage ELVDD substantially provided to the pixels PX.

The power supply600may provide the driving voltage ELVDD and the common voltage ELVSS to the display panel100. The voltage level of the driving voltage ELVDD may be higher than a voltage level of the common voltage ELVSS. The driving voltage ELVDD may be provided to a first side of the display panel100. A voltage level of the driving voltage ELVDD provided to a second side opposite to the first side of the display panel100may be lower than a voltage level of the driving voltage ELVDD provided to the first side of the display panel100due to resistances of wirings of the display panel100, a capacitance between the wirings, or the like. In other words, a voltage drop may occur in the driving voltage ELVDD due to the resistances of the wirings that transmit the driving voltage ELVDD to the pixels PX and the capacitance between the wirings. Accordingly, a voltage level of the driving voltage substantially provided to the pixels PX may be different from the voltage level of the driving voltage ELVDD provided from the power supply600.

The power supply600may provide the first initial reference voltage VIR1and the second initial reference voltage VIR2to the reference voltage generator500. The first initial reference voltage VIR1and the second initial reference voltage VIR2may be voltages determined in a gamma voltage setting process performed during a manufacturing process of the display device10. In the gamma voltage setting process, the display device10may be connected to a separate test device instead of the power supply600, and may receive a test driving voltage from the test device. The display device10may determine the first initial reference voltage VIR1and the second initial reference voltage VIR2in response to the test driving voltage, and may set initial gamma voltages based thereon. For example, in the gamma voltage setting process, the display device10may set the initial gamma voltages based on the first initial reference voltage VIR1and the second initial reference voltage VIR2such that luminances according to grayscales of the pixels PX become a predetermined gamma curve (e.g., a 2.2 gamma curve).

The reference voltage generator500may convert the sensing driving voltage ELVDD_S generated by measuring a driving voltage detected from the pixels PX into a sensing driving current, may convert the preset reference driving voltage ELVDD_R into a reference driving current, may compare the sensing driving current and the reference driving current, and may generate the first reference voltage VR1and the second reference voltage VR2based on a difference between the sensing driving current and the reference driving current. The first reference voltage VR1and the second reference voltage VR2may compensate for a change in the driving voltage ELVDD in the display panel100so that the pixels PX may be normally driven.

Configuration and operation of the reference voltage generator500will be described below with reference toFIG.3.

The timing controller700may receive input image data and an input control signal from an external device (e.g., graphic processor). The input image data may include grayscale values corresponding to the pixels PX. The input control signal may include a vertical synchronization signal, a horizontal synchronization signal, a main clock signal, a data enable signal, or the like.

The timing controller700may generate the image data ID based on the input image data, and may generate the scan control signal SCS and the data control signal DCS based on the input control signal. The timing controller700may provide the scan control signal SCS to the scan driver200, and may provide the data control signal DCS and the image data ID to the data driver300. Further, the timing controller700may provide the reference driving voltage ELVDD_R to the reference voltage generator500.

FIG.1illustrates that the timing controller700is implemented independently from the data driver300, however, the present disclosure is not limited thereto. For example, the timing controller700may be implemented as a single integrated circuit (a timing controller embedded driver, TED) together with the data driver300.

Further, althoughFIG.1illustrates that the gamma voltage generator400and the reference voltage generator500are implemented independently from the data driver300or the timing controller700, however, the present disclosure is not limited thereto. For example, the gamma voltage generator400and the reference voltage generator500may be implemented as a single integrated circuit together with the data driver300or the timing controller700. Alternatively, the gamma voltage generator400and the reference voltage generator500may be included in the data driver300or the timing controller700, and may be implemented in software.

FIG.2Ais a circuit diagram illustrating the pixel PX included in the display device10inFIG.1.FIG.2Bis a diagram for describing a method of driving the pixel PX inFIG.2A.

Referring toFIGS.2A and2B, the pixel PX may be connected to the scan line SL and the data line DL. The pixel PX may include a light emitting element LD, a plurality of transistors M1and M2, and a storage capacitor Cst.

AlthoughFIG.2Aillustrates that each of the transistors M1and M2is a P-type transistor, however, the present disclosure is not limited thereto. For example, at least one of the transistors M1and M2may be an N-type transistor.

A first electrode (e.g., an anode electrode) of the light emitting element LD may be connected to the driving voltage line ELVDDL via the first pixel transistor M1, and a second electrode (e.g., a cathode electrode) of the light emitting element LD may be connected to the common voltage line ELVSSL. The driving voltage line ELVDDL may be a line providing the driving voltage ELVDD inFIG.1, and the common voltage line ELVSSL may be a line providing the common voltage ELVSS inFIG.1.

A first electrode (e.g., a source electrode) of the first pixel transistor M1(a driving transistor) may be connected to the driving voltage line ELVDDL, and a second electrode (e.g., a drain electrode) of the first pixel transistor M1may be connected to the first electrode of the light emitting element LD. A gate electrode of the first pixel transistor M1may be connected to a first node N1. The first pixel transistor M1may control a driving current supplied to the light emitting element LD in response to a voltage of the first node N1.

A first electrode (e.g., a source electrode) of the second pixel transistor M2(a switching transistor) may be connected to the data line DL, and a second electrode (e.g., a drain electrode) of the second pixel transistor M2may be connected to the first node N1. A gate electrode of the second pixel transistor M2may be connected to the scan line SL.

A first electrode of the storage capacitor Cst may be connected to the first node N1, and a second electrode of the storage capacitor Cst may be connected to the driving voltage line ELVDDL. The storage capacitor Cst may be charged with a voltage corresponding to the data voltage VDT of a current frame supplied to the first node N1, and may maintain the charged voltage until the data voltage VDT of a next frame is supplied.

When the scan signal SS of a turn-on level (a low level) is supplied to the gate electrode of the second pixel transistor M2through the scan line SL, the second pixel transistor M2may electrically connect the data line DL to the first electrode of the storage capacitor Cst. Accordingly, a voltage corresponding to a difference between the data voltage VDT applied through the data line DL and the driving voltage ELVDD of the driving voltage line ELVDDL may be written in the storage capacitor Cst. For example, the data voltage VDT may correspond to one of the gamma voltages V0to V255inFIG.1.

The first pixel transistor M1may allow a driving current determined according to the voltage written in the storage capacitor Cst to flow from the driving voltage line ELVDDL to the common voltage line ELVSSL. The light emitting element LD may emit light with a luminance corresponding to the driving current.

AlthoughFIG.2Aillustrates a pixel PX including two transistors M1and M2and one capacitor Cst, the present disclosure is not limited thereto. For example, the pixel PX may further include transistors such as a compensation transistor for compensating a threshold voltage of the first pixel transistor M1, an initialization transistor for initializing the first node N1or the first electrode of the light emitting element LD, an emission control transistor for controlling an emission time of the light emitting element LD, or the like.

FIG.3is a circuit diagram illustrating a reference voltage generator500according to an embodiment.

Referring toFIG.3, the reference voltage generator500may include a first voltage-to-current converter510, a second voltage-to-current converter520, a current minor block530, a current comparator540, and a current-to-voltage converter550.

The first voltage-to-current converter510may convert the sensing driving voltage ELVDD_S into a sensing driving current I_SEN. The first voltage-to-current converter510may include a first amplifier AMP1, a first transistor T1, and a first resistor R1.

The sensing driving voltage ELVDD_S may be applied to a first input terminal (+) of the first amplifier AMP1via a fifth resistor R5, and a ground voltage may be applied to the first input terminal (+) of the first amplifier AMP1via a sixth resistor R6. For example, a resistance of the fifth resistor R5may be four times a resistance of the sixth resistor R6. A second input terminal (−) of the first amplifier AMP1may be connected to a first terminal of the first resistor R1and a first electrode of the first transistor T1. An output terminal of the first amplifier AMP1may be connected to a gate electrode of the first transistor T1.

The ground voltage may be applied to the first electrode (e.g., a source electrode) of the first transistor T1via the first resistor R1, andan analog driving voltage AVDD may be applied to a second electrode (e.g., a drain electrode) of the first transistor T1via a third transistor T3. The gate electrode of the first transistor T1may be connected to the output terminal of the first amplifier AMP1. In an embodiment, the first transistor T1may be an N-type metal oxide semiconductor (“NMOS”) transistor.

The first terminal of the first resistor R1may be connected to the second input terminal (−) of the first amplifier AMP1and the first electrode of the first transistor T1, and the ground voltage may be applied to a second terminal of the first resistor R1.

A voltage of the first input terminal (+) of the first amplifier AMP1may be substantially equal to a voltage of the second input terminal (−) of the first amplifier AMP1by a virtual short-circuit between the first input terminal (+) of the first amplifier AMP1and the second input terminal (−) of the first amplifier AMP1. Accordingly, a voltage between the opposite terminals of the first resistor R1may be equal to the voltage of the first input terminal (+) of the first amplifier AMP1. When a resistance of the first resistor R1is Rc, a value of the sensing driving current I_SEN flowing through the first resistor R1may be calculated according to Equation 1.
I_SEN=(⅕*ELVDD_S)/RC[Equation 1]

The second voltage-to-current converter520may convert the reference driving voltage ELVDD_R into a reference driving current I_REF. The second voltage-to-current converter520may include a second amplifier AMP2, a second transistor T2, and a second resistor R2.

A value obtained by converting the reference driving voltage ELVDD_R by a digital-to-analog converter DAC may be applied to a first input terminal (+) of the second amplifier AMP2. For example, the digital-to-analog converter DAC may apply a voltage of ⅕*ELVDD_REF to the first input terminal (+) of the second amplifier AMP2by converting the reference driving voltage ELVDD_R. A second input terminal (−) of the second amplifier AMP2may be connected to a first terminal of the second resistor R2and a first electrode of the second transistor T2. An output terminal of the second amplifier AMP2may be connected to a gate electrode of the second transistor T2.

The ground voltage may be applied to the first electrode (e.g., a source electrode) of the second transistor T2via the second resistor R2, and the analog driving voltage AVDD may be applied to a second electrode (e.g., a drain electrode) of the second transistor T2via a sixth transistor T6. The gate electrode of the second transistor T2may be connected to the output terminal of the second amplifier AMP2. In an embodiment, the second transistor T2may be an NMOS transistor.

The first terminal of the second resistor R2may be connected to the second input terminal (−) of the second amplifier AMP2and the first electrode of the second transistor T2, and the ground voltage may be applied to the second terminal of the second resistor R2.

A voltage of the first input terminal (+) of the second amplifier AMP2may be substantially equal to a voltage of the second input terminal (−) of the second amplifier AMP2by a virtual short-circuit between the first input terminal (+) of the second amplifier AMP2and the second input terminal (−) of the second amplifier AMP2. Accordingly, a voltage between the opposite terminals of the second resistor R2may be equal to the voltage of the first input terminal (+) of the second amplifier AMP2. When a resistance of the second resistor R2is Rc, a value of the reference driving current I_REF flowing through the second resistor R2may be calculated according to Equation 2.
I_REF=(⅕*ELVDD_R)/Rc[Equation 2]

The current minor block530may transmit the sensing driving current I_SEN generated by the first voltage-to-current converter510and the reference driving current I_REF generated by the second voltage-to-current converter520to the current comparator540. The current minor block530may include the third transistor T3, a fourth transistor T4, a fifth transistor T5, and the sixth transistor T6.

The analog driving voltage AVDD may be applied to a first electrode (e.g., a source electrode) of the third transistor T3, and a second electrode (e.g., a drain electrode) of the third transistor T3may be connected to the second electrode of the first transistor T1. A gate electrode of the third transistor T3may be connected to the second electrode of the third transistor T3and a gate electrode of the fourth transistor T4. In an embodiment, the third transistor T3may be a P-type metal oxide semiconductor (“PMOS”) transistor. Since the third transistor T3is series-connected to the first transistor T1, the sensing driving current I_SEN flowing through the first transistor T1may flow through the third transistor T3.

The analog driving voltage AVDD may be applied to a first electrode (e.g., a source electrode) of the fourth transistor T4, and a second electrode (e.g., a drain electrode) of the fourth transistor T4may be connected to a second electrode of the fifth transistor T5. A gate electrode of the fourth transistor T4may be connected to the gate electrode of the third transistor T3. In an embodiment, the fourth transistor T4may be a PMOS transistor. The third transistor T3and the fourth transistor T4may form a circuit structure of a current minor. Accordingly, the sensing driving current I_SEN may flow through the fourth transistor T4.

The ground voltage may be applied to a first electrode (e.g., a source electrode) of the fifth transistor T5, and a second electrode (e.g., a drain electrode) of the fifth transistor T5may be connected to the second electrode of the fourth transistor T4. A gate electrode of the fifth transistor T5may be connected to a gate electrode of a seventh transistor T7and a gate electrode of an eighth transistor T8. In an embodiment, the fifth transistor T5may be an NMOS transistor. Since the fifth transistor T5is series-connected to the fourth transistor T4, the sensing driving current I_SEN flowing through the fourth transistor T4may flow through the fifth transistor T5.

The analog driving voltage AVDD may be applied to a first electrode (e.g., a source electrode) of the sixth transistor T6, and a second electrode (e.g., a drain electrode) of the sixth transistor T6may be connected to the second electrode of the second transistor T2. A gate electrode of the sixth transistor T6may be connected to the second electrode of the sixth transistor T6, a gate electrode of a ninth transistor T9, and a gate electrode of a tenth transistor T10. In an embodiment, the sixth transistor T6may be a PMOS transistor. Since the sixth transistor T6is series-connected to the second transistor T2, the reference driving current I_REF flowing through the second transistor T2may flow through the sixth transistor T6.

The current comparator540may compare the sensing driving current I_SEN with the reference driving current I_REF. The current comparator540may include the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10.

The ground voltage may be applied to a first electrode (e.g., a source electrode) of the seventh transistor T7, and a second electrode (e.g., a drain electrode) of the seventh transistor T7may be connected to a first node ND1. The gate electrode of the seventh transistor T7may be connected to the gate electrode of the fifth transistor T5. In an embodiment, the seventh transistor T7may be an NMOS transistor. The fifth transistor T5and the seventh transistor T7may form a circuit structure of a current minor. Accordingly, the sensing driving current I_SEN may flow through the seventh transistor T7.

The ground voltage may be applied to a first electrode (e.g., a source electrode) of the eighth transistor T8, and a second electrode (e.g., a drain electrode) of the eighth transistor T8may be connected to a second node ND2. The gate electrode of the eighth transistor T8may be connected to the gate electrode of the fifth transistor T5. In an embodiment, the eighth transistor T8may be an NMOS transistor. The fifth transistor T5and the eighth transistor T8may form a circuit structure of a current minor. Accordingly, the sensing driving current I_SEN may flow through the eighth transistor T8.

The analog driving voltage AVDD may be applied to a first electrode (e.g., a source electrode) of the ninth transistor T9, and a second electrode (e.g., a drain electrode) of the ninth transistor T9may be connected to the first node ND1. The gate electrode of the ninth transistor T9may be connected to the gate electrode of the sixth transistor T6. In an embodiment, the ninth transistor T9may be a PMOS transistor. The sixth transistor T6and the ninth transistor T9may form a circuit structure of a current minor. Accordingly, the reference driving current I_REF may flow through the ninth transistor T9.

The analog driving voltage AVDD may be applied to a first electrode (e.g., a source electrode) of the tenth transistor T10, and a second electrode (e.g., a drain electrode) of the tenth transistor T10may be connected to the second node ND2. The gate electrode of the tenth transistor T10may be connected to the gate electrode of the sixth transistor T6. In an embodiment, the tenth transistor T10may be a PMOS transistor. The sixth transistor T6and the tenth transistor T10may form a circuit structure of a current minor. Accordingly, the reference driving current I_REF may flow through the tenth transistor T10.

Since the sensing driving current I_SEN flows through the seventh transistor T7, the reference driving current I_REF flows through the ninth transistor T9, and the ninth transistor T9is series-connected to the seventh transistor T7through the first node ND1, a current I_SEN-I_REF corresponding to a difference between the sensing driving current I_SEN and the reference driving current I_REF may flow from the current-to-voltage converter550to the first node ND1. Since the sensing driving current I_SEN flows through the eighth transistor T8, the reference driving current I_REF flows through the tenth transistor T10, and the tenth transistor T10is series-connected to the eighth transistor T8through the second node ND2, a current I_SEN-I_REF corresponding to a difference between the sensing driving current I_SEN and the reference driving current I_REF may flow from the current-to-voltage converter550to the second node ND2.

The current-to-voltage converter550may generate the first reference voltage VR1and the second reference voltage VR2based on the difference between the sensing driving current I_SEN and the reference driving current I_REF. The current-to-voltage converter550may include a first current-to-voltage converter551and a second current-to-voltage converter552.

The first current-to-voltage converter551may generate the first reference voltage VR1based on the difference between the sensing driving current I_SEN and the reference driving current I_REF. The first current-to-voltage converter551may include a third amplifier AMP3and a third resistor R3.

A first initial reference voltage VIR1may be applied to a first input terminal (+) of the third amplifier AMP3. A second input terminal (−) of the third amplifier AMP3may be connected to the first node ND1. An output terminal of the third amplifier AMP3may be connected to a first output terminal from which the first reference voltage VR1is output.

A first terminal of the third resistor R3may be connected to the first node ND1, and a second terminal of the third resistor R3may be connected to the output terminal of the third amplifier AMP3.

Since the third resistor R3is connected between the second input terminal (−) and the output terminal of the third amplifier AMP3, a value obtained by subtracting a value obtained by multiplying a resistance of the third resistor R3by a valueI_SEN-IREF obtained by subtracting the reference driving current I_REF from the sensing driving current I_SEN from a voltage of the output terminal of the third amplifier AMP3may be applied to the second input terminal (−) of the third amplifier AMP3. When the resistance of the third resistor R3is 5*Rc, a value of the first reference voltage VR1may be calculated according to Equation 3.
VR1=VIR1+5*Rc*(I_SEN−I_REF)=VIR1+(ELVDD_S−ELVDD_R)   [Equation 3]

Accordingly, the first reference voltage VR1may have a value in which a change in the driving voltage is compensated with the first initial reference voltage VIR1.

The second current-to-voltage converter552may generate the second reference voltage VR2based on the difference between the sensing driving current I_SEN and the reference driving current I_REF. The second current-to-voltage converter552may include a fourth amplifier AMP4and a fourth resistor R4.

A second initial reference voltage VIR2may be applied to a first input terminal (+) of the fourth amplifier AMP4. A second input terminal (−) of the fourth amplifier AMP4may be connected to the second node ND2. An output terminal of the fourth amplifier AMP4may be connected to a second output terminal from which the second reference voltage VR2is output.

A first terminal of the fourth resistor R4may be connected to the second node ND2, and a second terminal of the fourth resistor R4may be connected to the output terminal of the fourth amplifier AMP4.

Since the fourth resistor R4is connected between the second input terminal (−) and the output terminal of the fourth amplifier AMP4, a value obtained by subtracting a value obtained by multiplying a resistance of the fourth resistor R4by a valueI_SEN-IREF obtained by subtracting the reference driving current I_REF from the sensing driving current I_SEN from a voltage of the output terminal of the fourth amplifier AMP4may be applied to the second input terminal (−) of the fourth amplifier AMP4. When the resistance of the fourth resistor R3is 5*Rc, a value of the second reference voltage VR2may be calculated according to Equation 4.
Vr2=VIR2+5*Rc*(I_SEN−I_REF)=VIR2+(ELVDD_S−ELVDD_R)   [Equation 4]

Accordingly, the second reference voltage VR2may have a value in which a change in the driving voltage is compensated with the second initial reference voltage VIR2.

In an embodiment, the reference voltage generator500may further include a first current clamp561and a second current clamp562. The first current clamp561may limit a range of the sensing driving current I_SEN. For example, the first current clamp561may define an upper limit of the sensing driving current I_SEN. The second current clamp562may limit a range of the reference driving current I_REF. For example, the second current clamp562may define an upper limit of the reference driving current I_REF.

The first current clamp561may be connected to the gate electrode of the fifth transistor T5, the gate electrode of the seventh transistor T7, and the gate electrode of the eighth transistor T8. The second current clamp562may be connected to the gate electrode of the sixth transistor T6, the gate electrode of the ninth transistor T9, and the gate electrode of the tenth transistor T10.

As the first current clamp561limits the range of the sensing driving current I_SEN and the second current clamp562limits the range of the reference driving current I_REF, a range of the first reference voltage VR1and a range of the second reference voltage VR2may be limited. For example, when the upper limit of the sensing driving current I_SEN and the upper limit of the reference driving current I_REF are defined, each of the first reference voltage VR1and the second reference voltage VR2may operate only within a predetermined range. In other words, when the upper limit of the sensing driving current I_SEN and the upper limit of the reference driving current I_REF are defined, an upper limit and a lower limit of each of the first reference voltage VR1and the second reference voltage VR2may be defined.

FIGS.4A and4Bare diagrams for describing reaction rates of a voltage method and a current method. The voltage method refers to a method of comparing the sensing driving voltage ELVDD_S and the reference driving voltage ELVDD_R, and the current method refers to a method of comparing the sensing driving current I_SEN and the reference driving current I_REF.

Referring toFIG.4A, when the reference voltages VR1and VR2are generated by the voltage method according to a comparative embodiment of the prior art, a time period (e.g., about 1.4 μs) from a time point in which the sensing driving voltage ELVDD_S changes to a time point in which the first reference voltage VR1and the second reference voltage VR2changes may be relatively large. In other words, when the reference voltages VR1and VR2are generated by the voltage method according to a comparative embodiment of the prior art, reaction rates of the reference voltages VR1and VR2to the change of the sensing driving voltage ELVDD_S may be relatively slow. In the case of the voltage method according to the comparative example of the prior art, since the voltage loss, such as a voltage drop or the like, is large due to impedance or the like, the reaction rates of the reference voltages VR1and VR2to the change of the sensing driving voltage ELVDD_S may be relatively slow. When the reaction rates of the reference voltages VR1and VR2to the change of the sensing driving voltage ELVDD_S is slow, the gamma voltages V0to V255may change slowly in response to the change of the sensing driving voltage ELVDD_S, and accordingly, noise or flicker may be generated on a display screen.

However, referring toFIG.4B, when the reference voltages VR1and VR2are generated by the current method according to the embodiment of the present disclosure, a time period (e.g., about 0.3 μs) from a time point in which the sensing driving voltage ELVDD_S changes to a time point in which the first reference voltage VR1and the second reference voltage VR2changes may be relatively small. In other words, when the reference voltages VR1and VR2are generated by the current method according to the embodiment of the present disclosure, the reaction rates of the reference voltages VR1and VR2to the change of the sensing driving voltage ELVDD_S is relatively fast. In the case of the current method according to the embodiment of the present disclosure, since the distortion is small because the current loss is small and the influence of the impedance or the like is small, the reaction rates of the reference voltages VR1and VR2to the change of the sensing driving voltage ELVDD_S may be relatively fast. When the reaction rates of the reference voltages VR1and VR2to the change of the sensing driving voltage ELVDD_S is fast, the gamma voltages V0to V255may change rapidly in response to the change of the sensing driving voltage ELVDD_S, and accordingly, noise or flicker may not occur on the display screen.

FIGS.5A and5Bare diagrams for describing noise of the voltage method and the current method.

Referring toFIG.5A, when the reference voltage VR1is generated by the voltage method according to the comparative example of the prior art, a ground noise applied to the ground voltage V_GND may affect the reference voltage VR1. In other words, when the reference voltage VR1is generated by the voltage method according to the comparative example of the prior art, the reference voltage VR1may include a noise corresponding to the ground noise. In the case of the voltage method according to the comparative example of the prior art, since the ground noise is amplified by the amplifier, the ground noise applied to the ground voltage V_GND may affect the reference voltage VR1. When the ground noise applied to the ground voltage V_GND affects the reference voltage VR1, the gamma voltages V0to V255may include a noise, and accordingly, the noise may be generated on the display screen.

However, referring toFIG.5B, when the reference voltage VR1is generated by the current method according to the embodiment of the present disclosure, the ground noise applied to the ground voltage V_GND may not affect the reference voltage VR1. In other words, when the reference voltage VR1is generated by the current method according to the embodiment of the present disclosure, the reference voltage VR1may not include the noise corresponding to the ground noise. In the case of the current method according to the embodiment of the present disclosure, since the change in the initial reference voltages VIR1and VIR2due to the ground noise is offset by the change in the difference between the sensing driving current I_SEN and the reference driving current I_REF due to the ground noise, the ground noise applied to the ground voltage V_GND may not affect the reference voltage VR1. For example, when the initial reference voltages VIR1and VIR2increase due to the ground noise, the difference between the sensing driving current I_SEN and the reference driving current I_REF may decrease due to the ground noise. Further, when the initial reference voltages VIR1and VIR2decrease due to the ground noise, the difference between the sensing driving current I_SEN and the reference driving current I_REF may increase due to the ground noise. When the ground noise applied to the ground voltage V_GND does not affect the reference voltage VR1, the gamma voltages V0to V255may not include a noise, and accordingly, the noise may not be generated on the display screen.

FIG.6is a flowchart illustrating a method of driving a display device according to an embodiment.

Referring toFIG.6, the sensing driving voltage ELVDD_S may be generated by measuring the driving voltage ELVDD provided to the plurality of pixels PX (S110). The power supply600may provide the driving voltage ELVDD to the pixels PX, and the sensing driving voltage ELVDD_S may be a voltage generated by measuring the driving voltage ELVDD provided to the pixels PX.

Then, the first voltage-to-current converter510of the reference voltage generator500may convert the sensing driving voltage ELVDD_S into the sensing driving current I_SEN (S120).

Then, the second voltage-to-current converter520of the reference voltage generator500may convert the preset reference driving voltage EVLDD_R into the reference driving current I_REF (S130). The timing controller700may provide the reference driving voltage EVLDD_R to the reference voltage generator500, and the reference driving voltage ELVDD_R may be a target driving voltage for normally driving the pixels PX.

Then, the current comparator540of the reference voltage generator500may compare the sensing driving current I_SEN and the reference driving current I_REF (S140). The current minor block530of the reference voltage generator500may transmit the sensing driving current I_SEN generated by the first voltage-to-current converter510and the reference driving current I_REF generated by the second voltage-to-current converter520to the current comparator540.

Then, the current-to-voltage converter550of the reference voltage generator500may generate the first reference voltage VR1and the second reference voltage VR2based on the difference between the sensing driving current I_SEN and the reference driving current I_REF. The first current-to-voltage converter551of the current-to-voltage converter550may generate the first reference voltage VR1based on the first initial reference voltage VIR1and the difference between the sensing driving current I_SEN and the reference driving current I_REF (S150), and the second current-to-voltage converter552of the current-to-voltage converter550may generate the second reference voltage VR2based on the second initial reference voltage VIR2and the difference between the sensing driving current I_SEN and the reference driving current I_REF (S160).

Then, the gamma voltage generator400may divide the first reference voltage VR1and the second reference voltage VR2to generate the plurality of gamma voltages V0to V255(S170). The gamma voltages V0to V255may be intermediate voltages between the first reference voltage VR1and the second reference voltage VR2. The gamma voltages V0to V255may vary in response to the first reference voltage VR1and the second reference voltage VR2.

Then, the data driver300may convert the image data ID into the data voltage VDT based on the gamma voltages V0to V255(S180). The data driver300may provide the data voltage VDT to the pixels PX.

FIG.7is a block diagram illustrating an electronic apparatus1100including a display device1160according to an embodiment.

Referring toFIG.7, the electronic apparatus1100may include a processor1110, a memory device1120, a storage device1130, an input/output (“I/O”) device1140, and a display device1160. The electronic apparatus1100may further include a plurality of ports for communicating with a video card, a sound card, a memory card, a universal serial bus (“USB”) device, and etc.

The processor1110may perform particular calculations or tasks. In an embodiment, the processor1110may be a microprocessor, a central processing unit (“CPU”), or the like. The processor1110may be coupled to other components via an address bus, a control bus, a data bus, or the like. In an embodiment, the processor1110may be coupled to an extended bus such as a peripheral component interconnection (“PCI”) bus.

The memory device1120may store data for operations of the electronic apparatus1100. In an embodiment, the memory device1120may include a non-volatile memory device such as an erasable programmable read-only memory (“EPROM”) device, an electrically erasable programmable read-only memory (“EEPROM”) device, a flash memory device, a phase change random access memory (“PRAM”) device, a resistance random access memory (“RRAM”) device, a nano floating gate memory (“NFGM”) device, a polymer random access memory (“PoRAM”) device, a magnetic random access memory (“MRAM”) device, a ferroelectric random access memory (“FRAM”) device, etc., and/or a volatile memory device such as a dynamic random access memory (“DRAM”) device, a static random access memory (“SRAM”) device, a mobile DRAM device, etc.

The storage device1130may include a solid state drive (“SSD”) device, a hard disk drive (“HDD”) device, a CD-ROM device, or the like. The I/O device1140may include an input device such as a keyboard, a keypad, a touchpad, a touch-screen, a mouse device, etc., and an output device such as a speaker, a printer, and etc. The display device1160may be coupled to other components via the buses or other communication links.

In the display device1160, each of the sensing driving voltage and the reference driving voltage may be respectively converted into the sensing driving current and the reference driving current. Then, the sensing driving current and the reference driving current may be compared, and the reference voltage may be generated based on the difference between the sensing driving current and the reference driving current so that the change in the driving voltage may be rapidly compensated, and the reference voltage may not include the noise.

The display device according to the embodiments may be applied to a display device included in a computer, a notebook, a mobile phone, a smartphone, a smart pad, a PMP, a PDA, an MP3player, or the like.

Although the display devices, the reference voltage generators, and the methods of driving the display devices according to the embodiments have been described with reference to the drawings, the illustrated embodiments are examples, and may be modified and changed by a person having ordinary knowledge in the relevant technical field without departing from the technical spirit described in the following claims.