Fault detection for loss of feeback in forced switching power supplies with power factor correction

A device corrects the power factor in forced switching power supplies and includes a converter and a control device to obtain a regulated voltage on an output terminal. The control device comprises an error amplifier having an inverting terminal (Vout) and a non-inverting terminal receiving a reference voltage. The device includes first and second resistances coupled in series with a conduction element positioned between the first resistance and the inverting terminal of the error amplifier and a fault detector suitable for detecting the electrical connection of the conduction element with the output terminal and suitable for detecting an output signal of the second resistance. The fault detector is suitable for supplying a malfunction signal upon detecting an electric disconnection of the conduction element from the output terminal or when the output signal of the second resistance tends to zero.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention refers to a device for the correction of the power factor in forced switching power supplies.

2. Description of the Related Art

The use of power factor correction (PFC) devices for the active correction of the power factor (PF) for forced switching power supplies is generally known when used in electronic appliances of common use such as computers, television sets, monitors, etc. and also for the supply of fluorescent lamps, that is of forced switching pre-regulator stages whose task is to absorb current from the mains supply that is almost sinusoidal and is in phase with the mains voltage. Therefore a forced switching power supply of the current type comprises a PFC and a DC-DC converter connected to the output of the PFC.

A forced switching power supply of the traditional type comprises a DC-DC converter and an input stage connected to the distribution mains supply of electrical energy constituted by a full wave diode rectifier bridge and by a capacitor connected immediately downstream so as to produce a direct non-regulated voltage starting from the sinusoidal alternating mains voltage. The capacity of the capacitor is big enough to have a relatively small ripple at its terminals in relation to a continuous level. The rectifier diodes of the bridge, thus, will only conduct for a small portion of each half-cycle of the mains voltage, since its instantaneous value is lower than the voltage on the capacitor for the majority of the cycle. The result is that the current absorbed from the mains will be constituted by a series of narrow pulses whose amplitude is 5-10 times the resulting average value.

This has considerable consequences: the current absorbed from the line has much greater peak values and effectiveness compared with the case of absorption of sinusoidal current, the mains voltage is distorted by effect of the almost simultaneous pulse absorption of all the utilities connected to the mains, in the case of three-phase systems the current in the neutral conductor is greatly increased and there is a low utilization of the energetic potentialities of the electrical energy production system. In fact, the waveform of pulse current is very rich with odd harmonics which, even not contributing to the power given to the load, contribute to increasing the effective current absorbed from the mains and thus to increasing the dissipation of energy.

In quantitative terms all this can be expressed both in power factor (PF) terms, intended as ratio between the real power (that given to the load by the power supply gives plus that dissipated internally in the form of heat) and the apparent power (the product of the effective mains voltage by the effective current absorbed), and in terms of total harmonic distortion (THD), generally intended as percentage ratio between the energy associated with all the harmonics of higher orders and that associated with the fundamental harmonic. Typically, a power supply with capacitive filter has a PF of between 0.4-0.6 and a THD exceeding 100%.

A PFC, positioned between the rectifier bridge and the input of the DC-DC converter, permits an almost sinusoidal current, in phase with the voltage, to be absorbed from the mains, making the PF near 1 and reducing the THD.

FIG. 1schematically shows a pre-regulator PFC stage comprising a boost converter20and a control device1, in this case the control device L6561 produced by STMicroelectronics S.p.A. The boost converter20comprises a full wave diode rectifier bridge2having in input a mains voltage Vin, a capacitor C1(that serves as filter for the high frequency) having a terminal connected to the diode bridge2and the other terminal connected to ground, an inductance L connected to a terminal of the capacitor C1, a MOS power transistor M having the drain terminal connected to a terminal of the inductance L downstream thereof and having the source terminal connected to a resistance Rs connected to ground, a diode D having the anode connected to the common terminal of the inductance L and of the transistor M and the cathode connected to a capacitor Co having the other terminal connected to ground. In output the boost converter20generates a direct voltage Vout on the capacitor Co exceeding the maximum peak mains voltage, typically 400 V for systems powered with European mains or with universal powering. Such voltage Vout will be the input voltage of the DC-DC converter connected to the PFC.

The control device1must keep the output voltage Vout at a constant value by means of a feedback control action. The control device1comprises an operational error amplifier3suitable for comparing a part of the output voltage Vout, that is the voltage Vr given by Vr=R2×Vout/(R2+R1) (where the resistances R1and R2are connected in series to each other and in parallel with the capacitor Co) with a reference voltage Vref, for example of the value of 2.5V, and generates an error signal proportional to their difference. The output voltage Vout presents a ripple at a frequency that is double that of the mains and overlays the continuous value. If however the band amplitude of the error amplifier is considerably reduced (typically lower than 20 Hz) by means of the use of a suitable compensation network comprising at least a capacitor and we assume almost stationary operation, that is with constant effective input voltage and output load, this ripple will be gradually attenuated and the error signal will become constant.

The error signal Se is sent to a multiplier4where it is multiplied by a signal Vi given by a part of the mains voltage rectified by the diode bridge2. At the output of the multiplier4a signal Sm will be present and will be a rectified sinusoid whose amplitude will depend, obviously, on the effective mains voltage and on the error signal Se.

The signal Sm is sent to the non-inverting input of a comparator PWM5while on the inverting input there is the signal Srs present on the resistance Rs. If the signals Srs and Sm are equal the comparator5sends a signal to a control block6suitable for driving the transistor M and which, in this case, provides for turning it off. In this manner the output signal Sm of the multiplier determines the peak current of the transistor M and this will thus be enveloped by a rectified sinusoid. A filter disposed at the input of the stage eliminates the switching frequency component and ensures that the current absorbed from the mains has the form of the sinusoidal envelope. The block6comprises a zero current detecting block7capable of sending a pulse signal to an OR gate8whose other input is connected to a starter10, suitable for sending a signal to the OR gate8immediately at the initial time; the output signal S of the OR gate8is the set input S of a set-reset flip-flop11having another input R which is the output signal of the device5, and having an output signal Q. The signal Q is sent in input to a driver12that controls the turn-on or the turn-off of the transistor M.

The error amplifier3can be made in two manners: either as a real voltage amplifier, in which the output voltage is proportional to the difference between the voltages at its input terminals, or as a transconductance amplifier, whose output current is proportional to the difference between the voltages present at the input terminals. It is preferable to use voltage amplifiers as error amplifiers for their greater immunity to noise such as in the device L6561 mentioned.

Considering that in all closed-loop feedback control systems it is necessary to modify the transfer function of the gain of the loop so as to ensure the stability of the loop itself as well as to provide a satisfying dynamic behavior thereof, in the case of the PFCs this is normally done by modifying the frequency reply of the error amplifier. Using a voltage amplifier as error amplifier, the compensation network comprises at least a capacitance C connected in feedback between the output and the inverting input of the amplifier3.

One of the possible breakdowns in a forced switching power supply with PFC is the breaking of the control loop of the voltage.

The most frequent cause is due to the opening of the resistance R1of the output divider connected to the high voltage: in this case the system loses the information on the output voltage and the resistance R2tends to carry the input of the error amplifier towards ground. In this manner the output is unbalanced upwards and therefore the turn-on of the transistor M is commanded for the maximum possible duration. It follows that the output voltage will increase without control, carrying the load fed by the PFC as well as the PFC itself to destruction.

With the error amplifier3, the presence of the compensation network with the capacitor C positioned between the output and the inverting input limits the latter to the same potential as the other input for the whole time in which the current can flow through the capacitor C, that is until the output of the error amplifier3has the possibility of increasing. When the output reaches the upper end of its dynamics or, as is said, the error amplifier3is at high saturation, current does not pass any longer in the capacitor and the inverting input can go to zero.

On the market there are integrated PFCs that offer a protection against the opening of the control loop of the voltage. The solution in these PFCs consists of adding another resistive divider (constituted by the resistances R1aand R2ain series to each other) connected to the output of the PFC that permits the reading of the voltage and of using another comparator28that has its inverting input connected to the common terminal of the resistances R1aand R2aand the non-inverting input connected to a reference voltage Vth10, as can be seen inFIG. 2. At the moment in which the resistance R1opens, the voltage on the inverting input of the comparator28exceeds the voltage Vth10and the output29of the comparator28takes care of turning off the transistor M.

BRIEF SUMMARY OF THE INVENTION

One embodiment of the present invention is a device for the correction of the power factor in forced switching power supplies that is different from known devices.

One embodiment of the present invention is a device for the correction of the power factor in forced switching power supplies, comprising a converter and a control device coupled with said converter in order to obtain from an alternated mains input voltage a regulated voltage on the output terminal, said converter comprising a power transistor and said control device comprising an error amplifier having in input on the inverting terminal a signal proportional to said regulated voltage and on the non-inverting terminal a reference voltage, said signal proportional to said regulated voltage being produced by a first resistance and a second resistance coupled in series to which said regulated voltage is applied, a terminal of said second resistance being connected with said inverting terminal of the error amplifier, wherein the device comprises first means positioned between said first resistance and the inverting terminal of the error amplifier and second means suitable for detecting the electrical connection of said first means with the output terminal of said device for the correction of the power factor and suitable for detecting an output signal from said second resistance, said second means being suitable for supplying a malfunction signal of the device for the correction of the power factor when said second means detect the electrical disconnection of said first means from said output terminal or when the output signal of said second resistance tends to zero.

The device permits the protection of the device PFC itself if the value of the signal proportional to the output voltage and in input to the control device of the PFC tends to zero due to a breaking of the control loop.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 3shows a circuit diagram of a PFC for a forced switching power supply in accordance with a first embodiment of the present invention; the elements the same as the circuit ofFIG. 1will be indicated with the same references. The PFC comprises a converter20fitted with a full wave diode rectifier bridge2having in input a mains voltage Vin, a capacitor C1(that serves as filter for the high frequency) having a terminal connected to the diode bridge2and the other terminal connected to ground, an inductance L connected to a terminal of the capacitor C1, a MOS power transistor M having the drain terminal connected to a terminal of the inductance L downstream from the latter and having the source terminal connected to a resistance Rs connected to ground, a diode D having the anode connected to the common terminal of the inductance L and of the transistor M and the cathode connected to the output terminal Out of the PFC; a capacitor Co is also present connected between the terminal Out and ground. The boost converter20generates in output a direct voltage Vout on the capacitor Co exceeding the maximum mains peak voltage, typically 400 V for systems powered with European mains or with universal powering. This voltage Vout will be the input voltage of the DC-DC converter connected to the PFC.

The PFC comprises a control circuit100suitable for keeping the output voltage Vout at a constant value by means of a feedback control action. The control circuit100comprises an error amplifier3suitable for comparing a part of the output voltage Vout, that is the voltage Vr obtained by means of the resistive divider constituted by the resistances R1and R2, with a reference voltage Vref, for example of the value of 2.5V, and generates an error signal Se proportional to their difference. The output voltage Vout presents a ripple at a frequency that is double that of the mains and is superimposed on the continuous value. If however the band amplitude of the error amplifier is reduced considerably (typically lower than 20 Hz) by means of the use of a suitable compensation network comprising at least one capacitor and we assume almost stationary operation, that is with constant effective input voltage and output load, this ripple will be exceeded and the error signal will become constant. The error amplifier3is made like a voltage amplifier and is compensated by means of a compensation network comprising at least one capacitance C connected between its inverting input terminal and its output terminal.

The error signal Se is sent to a multiplier4where it is multiplied by a signal Vi given by a part of the mains voltage rectified by the diode bridge2. At the output of the multiplier4a signal Sm will be present given by a rectified sinusoid whose amplitude will obviously depend on the effective mains voltage and on the error signal.

The signal Sm is sent to the non-inverting input of a pulse width modulation (PWM) comparator5while on the inverting input there is the signal Srs present on a resistance Rs added between the non-drivable terminal of the transistor MOS M and ground. If the signals Srs and Sm are equal the comparator5sends a reset signal R to a set-reset flip-flop11being part of a control block6to command the turn-off of the transistor M. The block6comprises a zero current detecting block7capable of sending a pulse signal to an OR gate8whose other input is connected to a starter10, suitable for sending a signal to the OR gate8at the initial time instant; the output signal S of the OR gate8is the set input S of the flip-flop11that has an output signal Q. The signal Q is sent in input to a driver12that commands the turn-on and turn-off of the transistor M. In this manner the output signal Sm of the multiplier determines the peak current of the transistor M and this will then be enveloped by a rectified sinusoid. A filter positioned at the input of the stage eliminates the switching frequency component and ensures that the current absorbed from the mains has the shape of the sinusoidal envelope.

The control circuit100also comprises a diode D50having the anode connected to the resistance R1and the cathode connected to the inverting terminal of the error amplifier3connected to a terminal of the resistance R2; the control circuit100also comprises a circuit block50suitable for detecting the electrical connection of the diode D50with the output terminal Out of said device for the correction of the power factor and suitable for detecting a signal in output Vr2from the second resistance R2. Said circuit block50is suitable for supplying a malfunction signal Fault of the device for the correction of the power factor when it detects the electric disconnection of the D50from said output terminal Out or when the output signal Vr2of the second resistance R2tends to zero.

Said circuit block50is suitable for commanding the turn-off of the power transistor M and the deactivation of said control circuit100by means of emission of the signal Fault; in fact the signal Fault commands the turn-off of the transistor M and permits the disconnection of the supply Vdd of the control circuit100by acting on a switch80, positioned between the supply voltage Vdd and the circuits being part of the control device100, causing the PFC to turn-off.

FIG. 4shows a first embodiment of the diode D50and of the circuit block50. The latter comprises a first comparator52having the inverting terminal connected to the anode of the diode D50and the non-inverting terminal, on which the signal Vr2is present, connected to the cathode of the diode D50and a second comparator53having the inverting terminal, on which the signal Vr2is present, connected to the cathode of the diode D50and the non-inverting terminal connectable to a reference voltage Vth2or to the reference voltage Vth1by means of a switch54driven by the output of the comparator52. The output of the comparator53represents the set signal of a set-reset flip-flop56; the latter generates in output the signal Fault for the deactivation of the control circuit100and the turn-off of the transistor M. A current generator I50which generates a current of a smaller value than the current that flows through the diode D50and that is of approximately 1 μA is coupled to the anode of the diode D50, for example by means of a current mirror58; the current generator I50is coupled to ground and the current150is such that it leaves the anode of the diode D50. Another current generator I51is coupled to the cathode of the diode D50, again of approximately 1 μA.

Normally, that is in regular operating conditions, the voltage on the inverting terminal of the operational amplifier3, that is the signal Vr2, is equal to Vref while that on the anode of the diode D50, that is the signal Vr1, is equal to Vref+Vd50where Vd50is the voltage drop on the diode D50. The output of the comparator52is low and the switch54is driven so as to be connected to the voltage Vth1that is lower than Vref; in this manner the output of the comparator53is low.

If the resistance R1opens, the voltage Vr1on the anode of the diode D50will tend to zero thanks to the current I50; this will cause an inversion of the voltage drop at the terminals of the diode D50that will cause the comparator52to change state. The latter drives the switch54to connect itself to the voltage Vth2that exceeds Vref; the comparator53changes state and sends in output the set signal to the flip-flop56and the latter generates the signal Fault.

If the resistance R2goes in short circuit the signal Vr2tends to zero, the comparator53changes state and activates the flip-flop56that sends the signal Fault.

Preferably the circuit block50comprises a third comparator51having the inverting input terminal connected to the anode of the diode D50and the non-inverting terminal connected to a reference voltage Vth3. The circuit block50also comprises an OR gate55that has in input the outputs of the comparators51and53and whose output is the set signal of the flip-flop56. The comparator51protects the control device100from the opening of the connections of the diode D50or the breaking of the same diode D50; in fact, in this case, the voltage Vr1on the non-inverting terminal of the comparator51tends to rise and when it exceeds the voltage Vth3, that is greater than the voltage Vth2, it will cause the change of state of the comparator51which, through the OR gate55, will activate the flip-flop56which in turn will cause the signal Fault for the turn-off of the PFC.

InFIG. 5the diode D50and the circuit block50in accordance with a variant to the first embodiment of the invention are shown. In said variant the function previously carried out by the comparator52is carried out by the transistor T2. The bipolar pnp transistor T2has the base terminal coupled to the anode of the diode D50by means of a resistance R53, the emitter terminal connected to ground and the collector terminal coupled to a reference voltage Vref2by means of the series of two resistances R51and R52. The comparator53has the inverting terminal connected to the cathode of the diode D50and the non-inverting terminal connected to the common terminal of the resistances R51and R52. The output of the comparator53is the set signal of the flip-flop56suitable for generating the signal Fault. The voltage Vref2is set lower than the voltage given by the voltage Vref and by the voltage drop Vd50on the diode D50, Vref2<Vref+Vd50, and greater than the voltage Vref, Vref2>Vref.

In normal functioning conditions of the PFC the transistor T2is on considering that on the base terminal the voltage Vr1is present given by Vref+Vd50where Vd50is the voltage drop at the terminals of the diode D50. The voltage present on the non-inverting terminal of the comparator53is lower than Vref (is given by Vref2×R52/(R51+R52) where the resistances are set to obtain a voltage lower than Vref so that the output of the comparator is low.

If the resistance R1opens, the terminal constituted by the anode of the diode D50remains insulated and the transistor T2turns off since the base is no longer powered. The voltage on the non-inverting terminal of the comparator53is Vref2that permits the change of state of the comparator53itself; said change of state of the comparator53permits the generation of the signal Fault by sending the set signal to the flip-flop56.

If the resistance R2goes into short circuit the signal Vr2tends to zero, the comparator53changes state and activates the flip-flop56that sends the signal Fault.

Still in the circuit block50ofFIG. 5the function carried out by the comparator51is carried out by the transistor T1. The pnp transistor T1has the base terminal connected to the voltage Vref2, the collector terminal connected to the non-inverting input of the comparator53and the emitter terminal connected to the anode of the diode D50.

During normal functioning of the PFC the transistor T1remains off. If the diode D50opens or its connections with the terminals of the resistances R1and R2opens, or the resistance R2opens, the voltage Vr1on the terminal constituted by the anode of the diode D50is carried upwards turning on the transistor T1; this causes an increase of the value of the voltage on the non-inverting input of the comparator53which, becoming greater than Vref, permits a change of state of the comparator itself and the consequent generation of the signal Fault by activation of the flip-flop56.

InFIG. 6the diode D50and the circuit block50in accordance with another variant of the first embodiment of the invention are shown. Said variant differentiates from the variant ofFIG. 5only by the introduction of a further bipolar npn transistor T3having the emitter terminal connected to ground, the collector terminal connected to the base terminal of the transistor T2and the base terminal coupled to the collector terminal of the transistor T1by means of the resistance R54; the collector terminal of the transistor T1is no longer connected to the non-inverting input terminal of the comparator53. During normal functioning of the PFC the transistors T1and T3are off. If the diode D50opens, or its connections with the terminals of the resistances R1and R2opens, or the resistance R2opens, the voltage on the terminal constituted by the anode of the diode D50is carried upwards turning on the transistor T1; this causes the turn-on of the transistor T3that provides for the transistor T2to be turned off. Therefore there is an increase of the value of the voltage on the non-inverting input of the comparator53to Vref2that permits a change of state of the comparator itself and the consequent generation of the signal Fault by activation of the flip-flop56.

InFIG. 7a second embodiment of circuit comprising the diode D50and the circuit block50is shown. The latter comprises a first comparator62having the inverting terminal, on which the voltage Vr1is present, connected to the anode of the diode D50and the non-inverting terminal, on which the signal Vr2is present, connected to the cathode of the diode D50and a second comparator63having the inverting terminal, on which the signal Vr2is present, connected to the cathode of the diode D50and the non-inverting terminal connected to a reference voltage Vt1lower than Vref. The outputs of the comparators62and63are in input to an OR gate64whose output signal represents the set signal of a set-reset flip-flop65; the latter generates in output the signal Fault for the deactivation of the control circuit100and for the turn-off of the transistor M. A current generator I50, which generates a current of a smaller value than the current that flows through the diode D50and that is of approximately 1 μA, is coupled to the anode of the diode D50, for example by means of a current mirror58; the current generator I50is coupled to ground and the current I50is such that it leaves the anode of the diode D50. Another current generator I51again of approximately 1 μA is connected to the cathode.

Normally, that is in regular operating conditions, the voltage on the inverting terminal of the operational amplifier3is equal to Vref while that on the anode of the diode D50is equal to Vref+Vd50where Vd50is the voltage drop on the diode D50. The outputs of the comparators62and63are low.

If the resistance R1opens, the voltage Vr1on the anode of the diode D50will tend to zero thanks to the current I50; this will cause an inversion of the voltage drop at the terminals of the diode D50that will make the comparator62to change state. The latter activates the OR gate64that outputs the set signal to the flip-flop56and the latter generates the signal Fault.

If the resistance R2goes into short circuit the signal Vr2tends to zero, the comparator63changes state and activates, through the OR gate64, the flip-flop65that sends the signal Fault.

Preferably the circuit block50comprises a third comparator61having the inverting input terminal connected to the anode of the diode D50, the non-inverting terminal connected to a reference voltage Vt2and the output in input to the OR gate64. The comparator61protects the control device100from the opening of the connections of the diode D50or the breaking of the same diode D50; in fact, in this case, the voltage on the non-inverting terminal of the comparator61tends to rise and when it exceeds the voltage Vt2, that is greater than Vref+Vd50, it will cause the change of state of the comparator61which, through the OR gate64, will activate the flip-flop65which in turn will produce the signal Fault for the turn-off of the PFC.

InFIG. 8the diode D50and the circuit block50in accordance with a variant to the second embodiment of the invention are shown. In said variant the function carried out by the comparator62is carried out by the transistors M1and Q2. The bipolar npn transistor Q2has the base terminal coupled to the anode of the diode D50by means of a resistance R63, the emitter terminal connected to ground and the collector terminal coupled to the source terminal of the transistor MOS M1. The latter has the gate terminal connected to the cathode of the diode D50and the drain terminal coupled to the reference voltage Vref2, whose value is lower than Vref+Vd50but is greater than Vref, by means of a resistance R61. The drain terminal is connected with the set input of the flip-flop65suitable for generating the signal Fault.

In normal functioning conditions of the PFC the transistor Q2is on since on the base terminal there is the voltage Vr1given by Vref+Vd50where Vd50is the voltage drop at the terminals of the diode D50and also the transistor M1is on. The voltage present on the drain terminal of the transistor M1is near zero so that the flip-flop65does not generate the signal Fault.

If the resistance R1opens, the terminal constituted by the anode of the diode D50remains insulated and the transistor Q2turns off since the base is no longer powered and the voltage on the source terminal of the transistor M1tends to rise and to turn off transistor M1itself. The voltage on the drain terminal of the transistor M1is Vref2that permits the generation of the signal Fault by sending the set signal to the flip-flop65.

If the resistance R2goes into short circuit the transistor M1turns off and the voltage on the drain terminal becomes Vref2that activates the flip-flop56for the generation of the signal Fault.

Still in the circuit block50ofFIG. 8the function carried out by the comparator61is carried out by the transistors Q1and Q3. The pnp transistor Q1has the base terminal connected to the voltage Vref2, the emitter terminal connected to the anode of the diode D50and the collector terminal connected to the base terminal of the transistor Q3. The latter has the emitter terminal connected to ground and the collector terminal connected to the base terminal of the transistor Q2; a resistance R62is positioned between the base and emitter terminals of the transistor Q3.

If the diode D50opens, or its connections with the terminals of the resistances R1and R2opens, or the resistance R2opens, the voltage on the terminal constituted by the anode of the diode D50is carried upwards turning on the transistor Q1; this causes the turn-on of the transistor Q3that then turns off the transistor Q2. Therefore there is an increase of the value of the voltage on the source terminal of the transistor M1that tends to turn off the transistor M1itself. The voltage on the drain terminal of the transistor M1is Vref2that permits the generation of the signal Fault by activation of the flip-flop65.

In both solutions the optional current generator I51is shown. Its purpose is to eliminate the static error caused by the generator I50, whose value typically is not precise and whose statistic variation worsens the precision of the output voltage. From the current balance on the terminal constituted by the anode and by the cathode of the diode D50we have:

I⁡(R⁢⁢1)=Vout-(Vref+Vd⁢⁢50)R⁢⁢1=I⁡(D⁢⁢50)+I⁢⁢50=I⁡(R⁢⁢2)+I⁢⁢50=VrefR⁢⁢2+I⁢⁢50
where I(R1) is the current that flows through the resistance R1, I(R2) is the current that flows through the resistance R2and I(D50) is the current that flows through the diode D50.

Resolving in relation to Vout we obtain:

While the voltage Vd50is definitely negligible in relation to the voltage Vout (less than 0.2%), so that all the more so its statistic and temperature variations are also, the term I50×R1, by effect of the statistic and temperature variation, could even exceed 1%, thereby considerably influencing the precision of the voltage Vout (the tolerance of the voltage Vref is typically around 2-3%).

With the addition of the generator I2we have:
I(D50)=I(R1)−150; I(R2)=I(D50)+I51=I(R1)−I50+I51
and, choosing I50=I51, we obtain I(R2)=I(R1) and thus:

To be exact, a residual error remains due to the fact that the currents I50and I51are not exactly equal, however this error is at least of a lower order.

In all the circuit structures present in theFIGS. 3-8the circuit components indicated as being part of the control circuit100are integrated in the same chip.