Method and system for a high-speed backward-compatible ethernet connector

Aspects of a method and system for a high-speed backward-compatible Ethernet connector are provided. Which, if any, of a plurality of pins of a connector are coupled to a first portion of one or more circuits of an Ethernet PHY may be controlled via one or more switching elements in the Ethernet PHY. The switching element(s) may reside in a signal path between the first portion of the one or more circuits and a second portion of the one or more circuits. One or more configurations of the switching element(s) may couple less than all of the plurality of pins to the first circuit(s). Each signal into and out of the switching element(s) may be a digital signal. The first portion of the one or more circuit may comprise a media independent interface. The second portion of the one or more circuit may comprise a media dependent interface.

INCORPORATION BY REFERENCE

This patent application makes reference to U.S. patent application Ser. No. 12/853,945 filed on Aug. 10, 2010, which is hereby incorporated herein by reference in its entirety.

FIELD OF THE INVENTION

Certain embodiments of the invention relate to networking. More specifically, certain embodiments of the invention relate to a method and system for a high-speed backward-compatible Ethernet connector.

BACKGROUND OF THE INVENTION

Communications networks and in particular Ethernet networks, are becoming an increasingly popular means of exchanging data of various types and sizes for a variety of applications. In this regard, Ethernet networks are increasingly being utilized to carry voice, data, and multimedia traffic. Accordingly more and more devices are being equipped to interface to Ethernet networks. Ethernet-over-copper standards 10BASE-T, 100BASE-T, 1GBASE-T, and 10GBASE-T specify a common “RJ-45” connector.

BRIEF SUMMARY OF THE INVENTION

A system and/or method is provided for a configurable high-speed backward-compatible Ethernet connector, substantially as illustrated by and/or described in connection with at least one of the figures, as set forth more completely in the claims.

DETAILED DESCRIPTION OF THE INVENTION

Certain embodiments of the invention may be found in a method and system for a high-speed backward-compatible Ethernet connector. In various embodiments of the invention, which, if any, of a plurality of pins of a connector are coupled to a first portion of one or more circuits of an Ethernet PHY may be controlled via one or more switching elements in the Ethernet PHY. The one or more switching elements may reside in a signal path between the first portion of the one or more circuits of the Ethernet PHY and a second portion of the one or more circuits of the Ethernet PHY. The first portion of the one or more circuits may comprise a media independent interface. The second portion of the one or more circuits may comprise a media dependent interface. One or more configurations of the one or more switching elements may couple less than all of the plurality of pins to the first portion of the one or more circuits. Each signal into and out of the one or more switching elements may be a digital signal. A voltage and/or current present on one or more of the plurality of pins may be detected, and the one or more switching elements may be controlled based on a result of the detecting. The Ethernet PHY may be configurable to support a plurality of Ethernet physical layer standards. The one or more switching elements may be configured based on which one of said plurality of physical layer standards said Ethernet PHY is configured to support.

A first subset of the plurality of pins may be coupled to the first portion of the one or more circuits when a data rate of communications via the connector is less than or equal to the maximum data rate set forth in the 10GBASE-T standard. A second subset of the plurality of pins may be coupled to the first portion of the one or more circuits when a data rate of communications via the connector is greater than the maximum data rate set forth in the 10GBASE-T standard. A first subset of the plurality of pins may be coupled to the first portion of the one or more circuits when the Ethernet PHY is configured to communicate in accordance with one of 10BASE-T, 100BASE-T, 1GBASE-T, and 10GBASE-T standards. A second subset of the plurality of pins may be coupled to the first portion of the one or more circuits when the Ethernet PHY is configured to communicate in accordance with one of the 40GBASE-T and 1000BASE-T standards. The one or more switching elements may switch between one or more pins mounted on a first wall of the connector and one or more pins mounted on a second wall of the connector opposite the first wall. The first portion of the one or more circuits, the second portion of the one or more circuits, and the one or more switching elements may be integrated on a single integrated circuit die.

FIG. 1is a block diagram of an exemplary Ethernet device, in accordance with an embodiment of the invention. Referring toFIG. 1there is shown an Ethernet device100comprising a host subsystem124, a media access control (MAC) controller122, physical layer device (PHY)120, a connector108of the device100, and a cable assembly150comprising a connector152, and one or more conductors154.

The cable assembly150may comprise the connector152, one or more conductors154, and one or more connectors or other terminations on the opposite end (not shown) of the cable assembly150. The conductor(s)154may comprise, for example, one or more twisted pairs of aluminum or copper. Characteristics of the cable assembly150, such as number of conductors154, presence of shielding, length of the cable assembly150, and/or wire gauge of the conductor(s)154may determine which protocols and/or which data rates the cable assembly150may support. For example, the cable assembly may be a Cat 7a, Cat 7, Cat 6a, Cat 5e, or Cat 3 cable assembly, or a standard to be defined in the future. In some instances, mechanical and electrical characteristics of the connector152may be compatible with a standard RJ-45 type Ethernet connector. In some instances, mechanical and electrical characteristics of the connector152may be compatible with an ARJ-45 type Ethernet connector. In an exemplary embodiment of the invention, the cable assembly150may be compatible with both RJ-45 and ARJ-45 connectors. An ARJ-45 may, for example, have specifications similar to or the same as those found on the CA76 family of patch cable Cords from Bel Stewert Connector. In such an embodiment, the cable assembly150may comprise four twisted pairs terminated in four of the six pin pairs, comprise six twisted pairs terminated in six pin pairs of the connector152, or comprise any number of twisted pairs terminated in one or more of the six pin pairs.

The host124may comprise suitable logic, circuitry, interfaces, and/or code that may be operable to handle functionality of OSI layer 3 and above in the network device100. The host124may, for example, implement an operating system of the host125and may be operable to perform system control and management. The host124may communicate with the MAC122via, for example, a PCI or other similar or suitable bus128.

The MAC122may comprise suitable logic, circuitry, interfaces, and/or code that may be operable to perform data encapsulation and/or media access management, where media access management may comprise operations that handle conflicts arising from multiple network devices sharing the cable assembly150. In this regard, the MAC122may provide an interface between the Ethernet PHY120and the host124. The MAC122may communicate with the host124via a PCI or similar bus128and may communicate with the Ethernet PHY120via a bus126. In an embodiment of the invention, the MAC122may comprise media independent interface (xxxMII) for communicating over the bus126. In this regard, “media independent interface (xxxMII)” is utilized generically herein and may refer to a variety of interfaces including, but not limited to, a media independent interface (MII), a gigabit MII (GMII), a reduced MII (RMII), reduced gigabit MII (RGMII), 10 gigabit MII (XGMII), 40 gigabit MII (XLGMII), and 100 gigabit MII (CGMII) or a MII extender such as the 10 gigabit XAUI.

The Ethernet PHY120may comprise a twisted pair Ethernet PHY capable of operating at a variable data rate and supporting various Ethernet standards. The Ethernet PHY may comprise a media independent interface (xxxMII) for communicating with the MAC122via the bus126. The Ethernet PHY120may be operable to support, for example, one or more of 10BASE-T, 100BASE-T, 1GBASE-T, 10GBASE-T, 40GBASE-T, and 100GASE-T. In an embodiment of the invention, the PHY120may comprise one or more switching elements via which one or more of the pins101-106may be coupled to transmit and/or receive circuitry of the PHY120via the traces111-116.

In operation, one or more switching elements in the PHY120may be configured to determine which of the pins101a-106aand101b-106bare coupled to transmit and/or receive circuitry of the PHY120.

FIG. 2Ais a block diagram illustrating an exemplary Ethernet PHY operable to control which pins of a connector are coupled to transmit and/or receive circuitry of the PHY, in accordance with an embodiment of the invention. Referring toFIG. 2A, the PHY120comprises digital processing module252representing suitable logic, circuitry, interfaces, and/or code for implementing digital signal processing functions; switching elements2221and2222; switch control modules2261and2262representing suitable logic, circuitry, interfaces, and/or code for controlling switching elements2221and2222; and analog processing modules2101-2106representing suitable logic, circuitry, and/or code for implementing analog front end functions. In an embodiment of the invention, the digital processing module252, the switching elements2221and2222, the switch control modules2261and2262, the analog processing modules2101-2106, and other components of the PHY120may be integrated on a single integrated circuit die. In various embodiments of the invention, such a die may, for example, be integrated on and/or within the connector108, on and/or within a cable assembly, and on and/or within a network interface card.

The digital processing module252represents suitable logic, circuitry, interfaces, and/or code that may be operable to perform various digital-domain functions. The digital processing modules252may be operable to, for example, perform various digital signal processing operations such as echo cancellation, crosstalk cancellation, error correction, encoding, decoding, and/or filtering and/or any other handling of digital signals and/or information. The digital processing module252may comprise sub-modules2201-2204which may process information on a per-pair basis. The digital processing module252may comprise sub-module248which may combine and process information received from the sub-modules2201-2204and processing and segment data to be conveyed to the sub-modules2201-2204. The digital processing modules252may comprise an xxxMll for communicating with the MAC122via the bus126(FIG. 1).

Each of the analog processing modules2101-2106represents suitable logic, circuitry, interfaces, and/or code for performing analog front end functions. Such functions may comprise, for example, filtering, amplification, digital-to-analog conversion, and analog-to-digital conversion. The analog processing modules2101-2106may, for example, comprise a media dependent interface (MDI) operable to transmit and receive Ethernet physical layer signals over twisted pair cabling. The physical layer signals may, for example, be compatible with one or more of 10BASE-T, 100BASE-T, 1GBASE-T, 10GBASE-T, and Ethernet physical layer standards which may be defined in the future such as 40GBASE-T, and 100GBASE-T standards. Signals may be coupled from pin pairs101-106to analog processing modules2101-2106via traces111-116.

Each of the switch control modules2261and2262represents suitable logic, circuitry, interfaces, and/or code that may be operable to generate a signal230which may control the switching elements2221and2222. In an embodiment of the invention, each of the signals2301and2302may be an analog signal or may be a digital signal of one or more bits. In an embodiment of the invention, each of the switch control modules2261and2262may be operable to control the switching elements2221and2222based on a voltage and/or current sensed on the one or more of the pin pairs101-106. In an embodiment of the invention, the switch control modules2261and2262may be controlled, in part, by signal228which may be generated by the host124, the MAC122, and/or generated in the PHY120. In an embodiment of the invention, the switch control modules2261and2262may be controlled independently and/or in unison.

In operation, Ethernet physical layer signals may be transmitted and/or received via one or more of the pin pairs101-106. For reception, Ethernet physical layer signals received via a pin pair may be processed by an analog processing module210Xcoupled to the pin pair, where X is an integer from 1 to 6. Such processing may comprise conversion to a digital representation. If the analog processing module210Xis coupled to a digital processing sub-module220Y, the digital signals may then be conveyed from the analog processing module210Xto the digital processing sub-module220Y, where Y is an integer from 1 to 4. The digital processing sub-module220Ymay then further process the signals before communicating them to the MAC122. For transmission, digital signals output by a digital processing sub-module220Ymay be conveyed to an analog processing module210Xto which the digital processing sub-module220Yis coupled. The analog processing module210Xmay convert the digital signals to Ethernet physical layer signals and transmit the Ethernet physical layer signals onto a twisted pair to which it is coupled via one of the pin pairs101-106.

The switch control module2261may control the switching element2221based on the signal2241which may indicate a voltage and/or current on the pin pair101and/or on the pin pair103. In an embodiment of the invention, the digital processing sub-module2201may be coupled to the analog processing module2101when a non-zero voltage and/or current is detected on pin pair101and coupled to the analog processing module2103when zero voltage and/or current is detected on pin pair103. In an embodiment of the invention, the digital processing sub-module2201may be coupled to analog processing module2101when a particular voltage and/or current, or particular pattern or series of voltage and/or current, is detected on pin pair101, and coupled to the analog processing module2103when a particular voltage and/or current, or particular pattern or series of voltage and/or current, is detected on pin pair103. In an embodiment of the invention, the digital processing sub-module2201may be coupled to the analog processing module2101when a zero voltage and/or current is detected on pin pair103and coupled to the analog processing module2103when a zero voltage and/or current is detected on pin pair101.

Similarly, the switch control module2262may control the switching element2222based on the signal2242which may indicate a voltage and/or current on the pin pair106and/or on the pin pair104. In an embodiment of the invention, digital processing sub-module2204may be coupled to analog processing module2106when a non-zero voltage and/or current is detected on pin pair106and coupled to analog processing module2104when a non-zero voltage and/or current is detected on pin pair104. In an embodiment of the invention, digital processing sub-module2204may be coupled to analog processing module2106when a particular voltage and/or current, or particular pattern or series of voltage and/or current, is detected on pin pair106, and coupled to analog processing module2104when a particular voltage and/or current, or particular pattern or series of voltage and/or current, is detected on pin pair104. In an embodiment of the invention, digital processing sub-module2204may be coupled to analog processing module2106when a zero voltage and/or current is detected on pin pair104and coupled to analog processing module2104when a zero voltage and/or current is detected on pin pair106.

In an embodiment of the invention, the switch control modules2261and2262may control the switching elements2221and2222, based, at least in part, on the signal228which may indicate a mode of the PHY120. In this regard, the PHY120may support more than one physical layer protocol, and the signal228may indicate which of the supported protocols the PHY120is currently configured, or being configured, to support. In an embodiment of the invention, when the signal228indicates that the PHY120is to be configured to support speeds higher than10gigabits per second, for example configured to operate in 40GBASE-T mode or 100GBASE-T mode, the switch control module2261may configure the switching element2221to couple the digital processing sub-module2201to the analog processing module2101and the switch control module2262may configure the switching element2222to couple the digital processing sub-module2204to the analog processing module2106. In an embodiment of the invention, when the signal228indicates that the PHY120is to be configured to support speeds less than or equal to 10 gigabits per second, for example configured to operate in 10BASE-T mode, 100BASE-T mode, 1GBASE-Tmode, or 10GBASE-T mode, the switch control module2261may configure the switching element2221to couple the digital processing sub-module2201to the analog processing module2103and the switch control module2262may configure the switching element2222to couple the digital processing sub-module2204to the analog processing module2104.

FIG. 2Bis a block diagram illustrating an exemplary Ethernet PHY operable to control which pins of a connector are coupled to transmit and/or receive circuitry of the PHY, in accordance with an embodiment of the invention.FIG. 2Bis similar toFIG. 2Ain many respects, but depicts an embodiment in which switching elements2221and2222are controlled via a single switch control module2261. In this manner, the Ethernet PHY120, as depicted inFIG. 2B, may be smaller and/or less costly as it may require less circuitry than inFIG. 1A.

FIG. 2Cis a block diagram illustrating an exemplary Ethernet PHY operable to control which pins of a connector are coupled to transmit and/or receive circuitry of the PHY, in accordance with an embodiment of the invention. Referring toFIG. 2C, the Ethernet PHY may comprise a switching element232operable to couple any four of the analog processing modules2101-2106to the digital processing sub-modules2201-2204. That is, each of the digital processing sub-modules2201-2204may be coupled to any one of the analog processing modules2101-2106.

FIG. 2Dis a block diagram illustrating an exemplary Ethernet PHY operable to control which pins of a connector are coupled to transmit and/or receive circuitry of the PHY, in accordance with an embodiment of the invention. Referring toFIG. 2D, the Ethernet PHY120may be operable to communicate over four twisted pairs and over six twisted pairs.

In a first configuration, the switching element2361may establish two communication paths, a first path comprising digital processing sub-module2205, analog processing module2101, and pin pair101, and a second path comprising digital processing sub-module2201, analog processing module2103, and pin pair113. While the switching element2361is in the first configuration, either or both of the paths may be active and either or both of the paths may be inactive. A path may be inactive when it is not coupled to a twisted pair, and/or when it is coupled to a twisted pair but communication over that twisted pair is unnecessary or undesirable. For example, paths may be placed in an inactive mode to conserve energy. In a second configuration of the switching element2361digital processing sub-module2205may not be coupled to any pins of the connector108, and a communication path comprising digital processing sub-module2201, analog processing module2101, and pin pair101may be established.

In a first configuration, the switching element2362may establish two communication paths, a first path comprising the digital processing sub-module2206, the analog processing module2106, and pin pair116, and a second path comprising the digital processing sub-module2204, the analog processing module2104, and pin pair114. While the switching element2362is in the first configuration either or both of the paths may be active and either or both of the paths may be inactive. A path may be inactive when it is not coupled to a twisted pair, and/or when it is coupled to a twisted pair but communication over that twisted pair is unnecessary or undesirable. For example, paths may be placed in an inactive mode to conserve energy. In a second configuration of the switching element2362, the digital processing sub-module2206may not be coupled to any pins of the connector108, and a communication path comprising the digital processing sub-module2201, the analog processing module2101, and the pin pair101may be established.

In instances in which the Ethernet PHY120interfaces with a MAC that is operable to support communication over six twisted pairs, the switching elements2361and2362may be unnecessary and/or may remain configured into the first configuration. The switching elements2361and2362may, however, enable the Ethernet PHY120ofFIG. 2Dto be a drop-in replacement for an Ethernet PHY which only supports communication over four twisted pairs, such as the Ethernet PHY120ofFIG. 2A, for example.

FIGS. 3A-3Dillustrates a front-view of a connector, in accordance with an embodiment of the invention. Referring toFIG. 3A, the pins101aand101bmay be located on a wall opposite the wall on which the pins102a,102b,103a,103b,104a,104b,105a, and105bare located. Similarly, the pins106aand106bmay be located on a wall opposite the wall on which the pins102a,102b,103a,103b,104a,104b,105a, and105bare located. In instances that an RJ-45 connector is mated with the connector108, the coupling to four twisted pairs may be as depicted inFIG. 3B. In instances that an ARJ-45 connector is mated with the connector108, the coupling to four twisted pairs may be as depicted inFIG. 3C. In instances that a cable assembly comprising six pairs is inserted into the connector108, the coupling to the six twisted pairs may be as depicted inFIG. 3D.

FIG. 4is a flow chart illustrating exemplary steps for configuring an Ethernet PHY, in accordance with an embodiment of the invention. Referring toFIG. 4, the exemplary steps may begin with step402in which the cable assembly150(FIG. 1) is inserted into the connector108. In step404, the Ethernet PHY may sense a voltage and/or current on one or more of pin pairs101,103,104, and106. In step406, one or more switching elements may be configured to select which one or more of pin pairs101-106are coupled to which one or more of digital processing sub-modules2201-2204. In step408, after configuration of the switching elements, Ethernet communications may begin by, for example, entering an autonegotiation mode.

FIG. 5is a flow chart illustrating exemplary steps for configuring an Ethernet PHY, in accordance with an embodiment of the invention. Referring toFIG. 5, the exemplary steps may begin with step502in which a mode of operation of the Ethernet PHY120may be determined. The determination may be made based on one or more parameters such as, for example, user input, characteristics of the cable assembly150coupled to the connector108, an amount of data to be communicated, a type of data to be communicated, a rate at which data is to be communicated over the cable assembly150, based on applications running on a host124to which the Ethernet PHY is coupled, capabilities of the MAC122, measured error rates of communications conducted over the cable assembly, or any other suitable parameter(s). Any one or more of these parameters, and/or other parameters, may be determined utilizing autonegotiation and/or similar protocols. Alternatively, any one or more of these parameters, and/or other parameters, may be determined before and/or after autonegotiation. The determination may be performed by the Ethernet PHY120, the MAC122, and/or the host124. In step104, one or more switching elements in the Ethernet PHY120may be configured based on the determination made in step502. In step506, after configuration of the switching elements, the communication of data in the form of Ethernet physical layer signals may begin.

FIG. 6is a flow chart illustrating exemplary steps for configuring an Ethernet PHY, in accordance with an embodiment of the invention. Referring toFIG. 6, the exemplary steps may begin with step602in which the PHY102may be powered up with its one or more switching elements222,232, and/or236configured into a first configuration that supports a first one or more communication protocols. For example, in the first configuration the PHY120may support one or more Ethernet physical layer protocols that support 40 Gbps and/or 100 Gbps communications.

In step604, the PHY102may attempt autonegotiation with a link partner. In step606it may be determined whether the PHY102was able to successfully establish a connection to a link partner utilizing autonegotiation. In instances that a connection is successfully established, the exemplary steps advance to step616and the PHY102may begin communicating data utilizing the physical layer protocol(s) selected during autonegotiation.

Returning to step606, in instances that a connection is not successfully established with a link partner, the exemplary steps advance to step608. In step608, the one or more switching elements222,232, and/or236may be reconfigured into a second configuration that supports a second one or more communication protocols. For example, in the second configuration the PHY120may support a first one or more Ethernet physical layer protocols comprising one or more of 10BASE-T, 100BASE-T, 1GBASE-T and 10GBASE-T

In step610, the PHY102may attempt to establish a connection to a link partner using the one or more second protocols. In step612it may be determined whether the PHY102was able to successfully establish a connection to a link partner utilizing the second one or more protocols. In instances that an establishment of a connection is unsuccessful, the exemplary steps may return to step604. In instances that a connection is established, the exemplary steps may advance to step614and the PHY102may begin communicating data utilizing the second one or more protocols.

Various aspects of a method and system for a high-speed backward compatible Ethernet connector are provided. In an exemplary embodiment of the invention, one or more switching elements222,232, and/or236, in the Ethernet PHY120, may be operable to control which of a plurality of pins101a-106aand101b-106bof a connector108are coupled to a first portion of one or more circuits, represented by analog processing modules210, of an Ethernet PHY120. The one or more switching elements222,232, and/or236may reside in a signal path between the first portion of the one or more circuits of the Ethernet PHY120and a second portion of the one or more circuits, represented by one or more digital processing sub-modules220, of the Ethernet PHY120. One or more configurations of the one or more switching elements222,232, and/or236may couple less than all of the plurality of pins to the first portion of the one or more circuits. Each signal into and out of the one or more switching elements222,232, and/or236may be a digital signal. The first portion of the one or more circuits may comprise a media independent interface. The portion of the one or more circuits may comprise a media dependent interface. A voltage and/or current present on one or more of the plurality of pins may be detected, and the one or more switching elements222,232, and/or236may be controlled based on a result of the detecting. The Ethernet PHY120may be configurable to support a plurality of Ethernet physical layer standards. At any given time, the one or more switching elements222,232, and/or236may be configured based on which one of said plurality of physical layer standards said Ethernet PHY120is configured to support at that time.

A first subset of the plurality of pins101a-106aand101b-106bmay be coupled to the first portion of the one or more circuits, represented by one or more digital processing sub-modules220, when a data rate of communications via the connector108is less than or equal to the maximum data rate set forth in the 10GBASE-T standard. A second subset of the plurality of pins may be coupled to the first portion of the one or more circuits when a data rate of communications via the connector is greater than the maximum data rate set forth in the 10GBASE-T standard. A first subset of the plurality of pins may be coupled to the first portion of the one or more circuits when the Ethernet PHY is configured to communicate in accordance with one of 10BASE-T, 100BASE-T, 1GBASE-T, and 10GBASE-T standards. A second subset of the plurality of pins may be coupled to the first portion of the one or more circuits when the Ethernet PHY is configured to communicate in accordance with one of 40GBASE-T and 100GBASE-T standards. The one or more switching elements222,232, and/or236may switch between one or more pins mounted on a first wall of the connector, pins102aand102b, for example, and one or more pins mounted on a second wall of the connector opposite the first wall, pins101aand101b, for example. The first portion of the one or more circuits, represented by one or more digital processing sub-modules220, the second portion of the one or more circuits, represented by one or more analog processing modules210, and the one or more switching elements222,232, and/or236may be integrated on a single integrated circuit die.