Dynamic bit-line clamping circuit for computing-in-memory applications and clamping method thereof

A dynamic bit-line clamping circuit for computing-in-memory applications is configured to clamp a bit line via at least one reference signal and includes a clamping node, a first clamping unit, a second clamping unit, a first feedback controlling unit and a second feedback controlling unit. The first clamping unit is electrically connected between the bit line and the clamping node. The second clamping unit is electrically connected between the clamping node and a power source voltage and includes a switch. The second feedback controlling unit is electrically connected to the clamping node and the switch. The second feedback controlling unit generates a switching signal according to the at least one reference signal and a voltage level of the clamping node. The switch is switched by the switching signal so as to clamp the voltage level of the clamping node according to the at least one reference signal.

BACKGROUND

Technical Field

The present disclosure relates to a bit-line clamping circuit and a clamping method thereof. More particularly, the present disclosure relates to a dynamic bit-line clamping circuit for computing-in-memory applications and a clamping method thereof.

Description of Related Art

In these years, due to the industrial growth of mobile device, medical electrical equipment, portable storage, etc., requirement of memory with low power, high speed and high density is increased. For computing in memory, a large number of word lines (WL) are activated at same time. Various input patterns cause a widely bit-line (BL) current distribution which leads lower control of BL clamping voltage in current sensing. The BL current distribution of computational results (multiply-and-accumulate (MAC) value) is dependent on the various input patterns. However, in a conventional BL clamping scheme, most BL voltages are clamped by one transistor and one feedback control circuit. The current range of corresponding voltage is limited by the conventional BL clamping scheme. Therefore, a dynamic bit-line clamping circuit for computing-in-memory applications and a clamping method thereof having the features of dynamically clamping the BL voltage to induce accurate currents in the widely BL current distribution are commercially desirable.

SUMMARY

According to one aspect of the present disclosure, a dynamic bit-line clamping circuit for computing-in-memory applications is configured to clamp a bit line via at least one reference signal. The dynamic bit-line clamping circuit for the computing-in-memory applications includes a clamping node, a first clamping unit, a second clamping unit, a first feedback controlling unit and a second feedback controlling unit. The first clamping unit is electrically connected between the bit line and the clamping node. The second clamping unit is electrically connected between the clamping node and a power source voltage. The second clamping unit includes a first top transistor, a second top transistor and a switch. The first top transistor is electrically connected between the clamping node and the power source voltage. The second top transistor is electrically connected between the clamping node and the power source voltage. The switch is electrically connected between the clamping node and the second top transistor. The first feedback controlling unit is electrically connected to the first clamping unit and the bit line. The first feedback controlling unit generates a controlling signal to control the first clamping unit according to a voltage level of the bit line. The second feedback controlling unit is electrically connected to the clamping node and the switch. The second feedback controlling unit generates a switching signal according to the at least one reference signal and a voltage level of the clamping node. The switch is switched by the switching signal so as to clamp the voltage level of the clamping node according to the at least one reference signal.

According to another aspect of the present disclosure, a dynamic bit-line clamping circuit for computing-in-memory applications is configured to clamp a bit line via at least one reference signal. The dynamic bit-line clamping circuit for the computing-in-memory applications includes a master portion, a second feedback controlling unit and a slave portion. The master portion includes a clamping node, a first clamping unit, a second clamping unit and a first feedback controlling unit. The first clamping unit is electrically connected between the bit line and the clamping node. The second clamping unit is electrically connected between the clamping node and a power source voltage. The second clamping unit includes a first top transistor, a second top transistor and a switch. The first top transistor is electrically connected between the clamping node and the power source voltage. The second top transistor is electrically connected between the clamping node and the power source voltage. The switch is electrically connected between the clamping node and the second top transistor. The first feedback controlling unit is electrically connected to the first clamping unit and the bit line. The first feedback controlling unit generates a controlling signal to control the first clamping unit according to a voltage level of the bit line. The second feedback controlling unit is electrically connected to the clamping node and the switch. The second feedback controlling unit generates a switching signal according to the at least one reference signal and a voltage level of the clamping node. The slave portion is electrically connected to the master portion and has a slave clamping node. The slave portion generates a voltage level of the slave clamping node according to the voltage level of the clamping node and the switching signal. The switch is switched by the switching signal so as to clamp the voltage level of the clamping node and the voltage level of the slave clamping node according to the at least one reference signal.

According to further another aspect of the present disclosure, a clamping method of the dynamic bit-line clamping circuit for the computing-in-memory applications provides a voltage level applying step, a first clamping step and a second clamping step. The voltage level applying step is for applying a voltage level to the switching signal according to the at least one reference signal and the voltage level of the clamping node. The first clamping step is for driving the first clamping unit and the first feedback controlling unit to clamp the voltage level of the bit line. The second clamping step is for driving the second clamping unit and the second feedback controlling unit to clamp the voltage level of the clamping node.

DETAILED DESCRIPTION

Before describing any embodiments in detail, some terms used in the following are described. A voltage level of “1” represents that the voltage is equal to a power source voltage VDD. The voltage level of “0” represents that the voltage is equal to a ground voltage. A PMOS transistor and an NMOS transistor represent a P-type MOS transistor and an N-type MOS transistor, respectively.

FIG. 1shows a block diagram of a dynamic bit-line clamping circuit100for computing-in-memory applications according to a first embodiment of the present disclosure. The dynamic bit-line clamping circuit100for the computing-in-memory applications is configured to clamp a bit line BL via at least one reference signal REF<1>. The dynamic bit-line clamping circuit100for computing-in-memory applications includes a clamping node VG_p1, a first clamping unit200, a second clamping unit300, a first feedback controlling unit400and a second feedback controlling unit500.

The first clamping unit200is electrically connected between the bit line BL and the clamping node VG_p1. In detail, the first clamping unit200includes a first bottom transistor N_1and a second bottom transistor N_2. The first bottom transistor N_1is an NMOS transistor and has a first bottom gate, a first bottom drain and a first bottom source. The first bottom gate is coupled to the controlling signal. The first bottom drain is coupled to the clamping node VG_p1, and the first bottom source is coupled to the bit line BL. The second bottom transistor N_2is an NMOS transistor and has a second bottom gate, a second bottom drain and a second bottom source. The second bottom gate is coupled to the controlling signal. The second bottom drain is coupled to the clamping node VG_p1, and the second bottom source is coupled to the bit line BL.

The second clamping unit300is electrically connected between the clamping node VG_p1and the power source voltage VDD. The second clamping unit300includes a first top transistor PM_1, a second top transistor PM_2and a switch SW. The first top transistor PM_1is electrically connected between the clamping node VG_p1and the power source voltage VDD. The second top transistor PM_2is electrically connected between the clamping node VG_p1and the power source voltage VDD. The switch SW is electrically connected between the clamping node VG_p1and the second top transistor PM_2. In detail, the first top transistor PM_1is a PMOS transistor and has a first top gate, a first top drain and a first top source. The first top gate and the first top drain are coupled to the clamping node VG_p1, and the first top source is coupled to the power source voltage VDD. The second top transistor PM_2is a PMOS transistor and has a second top gate, a second top drain and a second top source. The second top gate is coupled to the switch SW. The second top drain is coupled to the clamping node VG_p1, and the second top source is coupled to the power source voltage VDD.

The first feedback controlling unit400is electrically connected to the first clamping unit200and the bit line BL. The first feedback controlling unit400generates a controlling signal to control the first clamping unit200according to a voltage level VBLof the bit line BL. The controlling signal is coupled to the first bottom gate of the first bottom transistor N_1and the second bottom gate of the second bottom transistor N_2. In one embodiment, the first feedback controlling unit400may be implemented as a sense amplifier to feedback control the first clamping unit200according to a bit-line reference signal ref_BL, thereby effectively controlling the voltage level VBLof the bit line BL.

The second feedback controlling unit500is electrically connected to the clamping node VG_p1and the switch SW. The second feedback controlling unit500generates a switching signal SW<1> according to the at least one reference signal REF<1> and a voltage level of the clamping node VG_p1. The switch SW is switched by the switching signal SW<1> so as to clamp the voltage level of the clamping node VG_p1according to the at least one reference signal REF<1>. When a voltage level of the switching signal SW<1> is equal to zero, the second top gate is coupled to the power source voltage VDD via the switch SW. On the contrary, when the voltage level of the switching signal SW<1> is equal to one, the second top gate is coupled to the clamping node VG_p1via the switch SW. The second feedback controlling unit500may be implemented as a sense amplifier to feedback control the second clamping unit300according to the reference signal REF<1>, thus effectively controlling the voltage level of the clamping node VG_p1. Therefore, the dynamic bit-line clamping circuit100of the present disclosure utilizes a dynamically configurable bit-line clamping scheme with automatically changeable configurations with a readout result from a prior cycle and a current read cycle, so that the dynamic bit-line clamping circuit100of the present disclosure is suitable for the computing-in-memory applications.

FIG. 2shows a block diagram of a dynamic bit-line clamping circuit100afor computing-in-memory applications according to a second embodiment of the present disclosure. The dynamic bit-line clamping circuit100afor computing-in-memory applications is configured to clamp a bit line via at least one reference signal REF<1> and includes a master portion110, a second feedback controlling unit500and a slave portion120.

The master portion110includes a clamping node VG_p1, a first clamping unit200, a second clamping unit300and a first feedback controlling unit400. InFIG. 2, the detail of the clamping node VG_p1, the first clamping unit200, the second clamping unit300and the first feedback controlling unit400and the second feedback controlling unit500is the same as the embodiments ofFIG. 1, and will not be described again herein. InFIG. 2, the dynamic bit-line clamping circuit100afor the computing-in-memory applications further includes the slave portion120. The slave portion120is electrically connected to the master portion110and has a slave clamping node VG_n. The slave portion120generates a voltage level of the slave clamping node VG_naccording to the voltage level of the clamping node VG_p1and the switching signal SW<1>. The switch SW is switched by the switching signal SW<1> so as to clamp the voltage level of the clamping node VG_p1and the voltage level of the slave clamping node VG_naccording to the at least one reference signal REF<1>. In detail, the slave portion120includes a first slave unit600and a second slave unit700. The first slave unit600is electrically connected between the power source voltage VDD and the slave clamping node VG_nand includes a first slave top transistor PS_1, a first slave switch SSW1and a second slave top transistor PS_2. The first slave top transistor PS_1is a PMOS transistor and has a first slave top gate, a first slave top drain and a first slave top source. The first slave top gate is coupled to the clamping node VG_p1. The first slave top drain is coupled to the slave clamping node VG_n, and the first slave top source is coupled to the power source voltage VDD. The first slave switch SSW1is coupled to the clamping node VG_p1and controlled by the switching signal SW<1>. The second slave top transistor PS_2is a PMOS transistor and has a second slave top gate, a second slave top drain and a second slave top source. The second slave top gate is coupled to the first slave switch SSW1. The second slave top drain is coupled to the slave clamping node VG_n, and the second slave top source is coupled to the power source voltage VDD. In addition, the second slave unit700is electrically connected between the slave clamping node VG_nand the ground voltage and includes a first slave bottom transistor NS_1, a second slave switch SSW2and a second slave bottom transistor NS_2. The first slave bottom transistor NS_1is an NMOS transistor and has a first slave bottom gate, a first slave bottom drain and a first slave bottom source. The first slave bottom gate and the first slave bottom drain are coupled to the slave clamping node VG_n, and the first slave bottom source is coupled to the ground voltage. The second slave switch SSW2is coupled to the slave clamping node VG_nand controlled by the switching signal SW<1>. The second slave bottom transistor NS_2is an NMOS transistor and has a second slave bottom gate, a second slave bottom drain and a second slave bottom source. The second slave bottom gate is coupled to the second slave switch SSW2. The second slave bottom drain is coupled to the slave clamping node VG_n, and the second slave bottom source is coupled to the ground voltage. Accordingly, the dynamic bit-line clamping circuit100aof the present disclosure utilizes a dynamically configurable bit-line clamping scheme with automatically changeable configurations with a readout result from a prior cycle and a current read cycle, so that the dynamic bit-line clamping circuit100aof the present disclosure is suitable for the computing-in-memory applications. Furthermore, the slave portion120of the present disclosure utilizes a current mirror scheme to generate the voltage level of the slave clamping node VG_naccording to the voltage level of the clamping node VG_p1, so that the voltage level of the slave clamping node VG_ncan be used by a subsequent circuit to avoid disturbing the clamping node VG_p1.

FIG. 3shows a block diagram of a dynamic bit-line clamping circuit100bfor computing-in-memory applications according to a third embodiment of the present disclosure. The dynamic bit-line clamping circuit100bfor the computing-in-memory applications is configured to clamp a bit line BL via a plurality of reference signals REF<3:0>. The dynamic bit-line clamping circuit100bfor the computing-in-memory applications includes a clamping node VG_p1, a first clamping unit200b, a second clamping unit300b, a first feedback controlling unit400and a second feedback controlling unit500b.

The first clamping unit200bis electrically connected between the bit line BL and the clamping node VG_p1. The first clamping unit200bincludes a first bottom transistor N_1, a second bottom transistor N_2, a third bottom transistor N_3and a fourth bottom transistor N_4. InFIG. 3, the detail of the first bottom transistor N_1and the second bottom transistor N_2is the same as the embodiments ofFIG. 1, and will not be described again herein. The third bottom transistor N_3is an NMOS transistor and has a third bottom gate, a third bottom drain and a third bottom source. The third bottom gate is coupled to the controlling signal. The third bottom drain is coupled to the clamping node VG_p1, and the third bottom source is coupled to the bit line BL. The fourth bottom transistor N_4is an NMOS transistor and has a fourth bottom gate, a fourth bottom drain and a fourth bottom source. The fourth bottom gate is coupled to the controlling signal. The fourth bottom drain is coupled to the clamping node VG_p1, and the fourth bottom source is coupled to the bit line BL.

The second clamping unit300bis electrically connected between the clamping node VG_p1and the power source voltage VDD. The second clamping unit300bincludes a first top transistor PM_1, a second top transistor PM_2, a third top transistor PM_3, a fourth top transistor PM_4, a first switch SW1, a second switch SW2and a third switch SW3. The second switch SW1is electrically connected to the clamping node VG_p1and the second top transistor PM_2. The second switch SW2is electrically connected to the clamping node VG_p1and the third top transistor PM_3. The third switch SW3is electrically connected to the clamping node VG_p1and the fourth top transistor PM_4. InFIG. 3, the detail of the first top transistor PM_1and the second top transistor PM_2is the same as the embodiments ofFIG. 1, and will not be described again herein. The third top transistor PM_3is a PMOS transistor and has a third top gate, a third top drain and a third top source. The third top gate is coupled to the second switch SW2. The third top drain is coupled to the clamping node VG_p1, and the third top source is coupled to the power source voltage VDD. The fourth top transistor PM_4is a PMOS transistor and has a fourth top gate, a fourth top drain and a fourth top source. The fourth top gate is coupled to the third switch SW3. The fourth top drain is coupled to the clamping node VG_p1, and the fourth top source is coupled to the power source voltage VDD.

The first feedback controlling unit400is electrically connected to the first clamping unit200band the bit line BL. The first feedback controlling unit400generates a controlling signal to control the first clamping unit200baccording to a voltage level VBLof the bit line BL. The controlling signal is coupled to the first bottom gate of the first bottom transistor N_1, the second bottom gate of the second bottom transistor N_2, the third bottom gate of the third bottom transistor N_3and the fourth bottom gate of the fourth bottom transistor N_4. In one embodiment, the first feedback controlling unit400may be implemented as a sense amplifier to feedback control the first clamping unit200baccording to a bit-line reference signal ref_BL, thereby effectively controlling the voltage level VBLof the bit line BL. Accordingly, the third bottom gate of the third bottom transistor N_3and the fourth bottom gate of the fourth bottom transistor N_4may be decoupled for shorter stable time on the first bottom gate of the first bottom transistor N_1and the second bottom gate of the second bottom transistor N_2.

The second feedback controlling unit500bis electrically connected to the clamping node VG_p1, the first switch SW1, the second switch SW2and the third switch SW3. A plurality of reference signals REF<3:0> are transmitted into the second feedback controlling unit500b. The second feedback controlling unit500bgenerates a plurality of switching signals SW<3:0> according to differences between the reference signals REF<3:0> and the voltage level of the clamping node VG_p1. The switching signals SW<3:0> include a first switching signal SW<1>, a second switching signal SW<2> and a third switching signal SW<3> which are correspondingly coupled to the first switch SW1, the second switch SW2and the third switch SW3, respectively. When a voltage level of the first switching signal SW<1> is equal to zero, the second top gate is coupled to the power source voltage VDD via the first switch SW1. When the voltage level of the first switching signal SW<1> is equal to one, the second top gate is coupled to the clamping node VG_p1via the first switch SW1. When a voltage level of the second switching signal SW<2> is equal to zero, the third top gate is coupled to the power source voltage VDD via the second switch SW2. When the voltage level of the second switching signal SW<2> is equal to one, the third top gate is coupled to the clamping node VG_p1via the second switch SW2. When a voltage level of the third switching signal SW<3> is equal to zero, the fourth top gate is coupled to the power source voltage VDD via the third switch SW3. When the voltage level of the third switching signal SW<3> is equal to one, the fourth top gate is coupled to the clamping node VG_p1via the third switch SW3. In addition, the second feedback controlling unit500bincludes a plurality of sense amplifiers510and a digital logic controller520. The sense amplifiers510are configured to receive the reference signals REF<3:0>. The sense amplifiers510are electrically connected to the clamping node VG_p1and generate a plurality of sensing output signals, respectively. The digital logic controller520is electrically connected among the sense amplifiers510and the second clamping unit300b. The digital logic controller520generates the switching signals SW<3:0> according to the sensing output signals. In one embodiment, the digital logic controller520may be implemented as a decoder to correctly generate the switching signals SW<3:0>.

FIG. 4shows a block diagram of a dynamic bit-line clamping circuit100cfor computing-in-memory applications according to a fourth embodiment of the present disclosure. The dynamic bit-line clamping circuit100cfor the computing-in-memory applications is configured to clamp a bit line BL via a plurality of reference signals REF<3:0> and includes a master portion110c, a second feedback controlling unit500band a slave portion120c.

The master portion110cincludes a clamping node VG_p1, a first clamping unit200b, a second clamping unit300band a first feedback controlling unit400. InFIG. 4, the detail of the clamping node VG_p1, a first clamping unit200b, a second clamping unit300b, a first feedback controlling unit400and the second feedback controlling unit500bis the same as the embodiments ofFIG. 3, and will not be described again herein. InFIG. 4, the dynamic bit-line clamping circuit100cfor the computing-in-memory applications further includes the slave portion120c. The slave portion120is electrically connected to the master portion110cand has a slave clamping node VG_n. The slave portion120cgenerates a voltage level of the slave clamping node VG_naccording to the voltage level of the clamping node VG_p1and the switching signals SW<3:0>. The first switch SW1, the second switch SW2and the third switch SW3are switched by the first switching signal SW<1>, the second switching signal SW<2> and the third switching signal SW<3>, respectively, thereby effectively clamping the voltage level of the clamping node VG_p1and the voltage level of the slave clamping node VG_naccording to the reference signals REF<3:0>.

FIG. 5shows timing diagrams of the dynamic bit-line clamping circuit100cfor the computing-in-memory applications ofFIG. 4. It is obvious that the unselected PMOS transistor(s) (i.e., the second top transistor PM_2, the third top transistor PM_3and/or the fourth top transistor PM_4) will be turned off according to the first switch SW1, the second switch SW2and the third switch SW3switched by the first switching signal SW<1>, the second switching signal SW<2> and the third switching signal SW<3>, respectively. The voltage level of the clamping node VG_p1can be effectively clamped according to the first switching signal SW<1>, the second switching signal SW<2> and the third switching signal SW<3> in a read cycle.

FIG. 6shows a flow chart of a clamping method800of the dynamic bit-line clamping circuit100for the computing-in-memory applications ofFIG. 1according to one embodiment of the present disclosure. The clamping method800provides a voltage level applying step S12, a first clamping step S14and a second clamping step S16. The voltage level applying step S12is for applying a voltage level to the switching signal SW<1> according to the at least one reference signal REF<1> and the voltage level of the clamping node VG_p1. The first clamping step S14is for driving the first clamping unit200and the first feedback controlling unit400to clamp the voltage level of the bit line BL. The second clamping step S16is for driving the second clamping unit300and the second feedback controlling unit500to clamp the voltage level of the clamping node VG_p1. Certainly, the clamping method800may be applied to the dynamic bit-line clamping circuit100bfor the computing-in-memory applications ofFIG. 3. Therefore, the clamping method800of the present disclosure utilizes a dynamically configurable bit-line clamping scheme with automatically changeable configurations with a readout result from a prior cycle and a current read cycle, so that the dynamic bit-line clamping circuits100,100bof the present disclosure are suitable for the computing-in-memory applications.

FIG. 7shows a flow chart of a clamping method800aof the dynamic bit-line clamping circuit100cfor the computing-in-memory applications ofFIG. 4according to another embodiment of the present disclosure. The clamping method800aprovides a voltage level applying step S22, a first clamping step S24, a second clamping step S26and a third clamping step S28.

The voltage level applying step S22is for applying a plurality of voltage levels to the first switching signal SW<1>, the second switching signal SW<2> and the third switching signal SW<3> according to the reference signal REF<3:0> and the voltage level of the clamping node VG_p1. The first clamping step S24is for driving the first clamping unit200band the first feedback controlling unit400to clamp the voltage level of the bit line BL.

The second clamping step S26is for driving the second clamping unit300band the second feedback controlling unit500bto clamp the voltage level of the clamping node VG_p1. In detail, when the voltage level of the first switching signal SW<1> is equal to zero, the second top gate of the second top transistor PM_2is coupled to the power source voltage VDD via the first switch SW1. When the voltage level of the first switching signal SW<1> is equal to one, the second top gate is coupled to the clamping node VG_p1via the first switch SW1. When the voltage level of the second switching signal SW<2> is equal to zero, the third top gate of the third top transistor PM_3is coupled to the power source voltage VDD via the second switch SW2. When the voltage level of the second switching signal SW<2> is equal to one, the third top gate is coupled to the clamping node VG_p1via the second switch SW2. When a voltage level of the third switching signal SW<3> is equal to zero, the fourth top gate of the fourth top transistor PM_4is coupled to the power source voltage VDD via the third switch SW3. When the voltage level of the third switching signal SW<3> is equal to one, the fourth top gate is coupled to the clamping node VG_p1via the third switch SW3.

The third clamping step S28is for driving the slave portion120cto clamp a voltage level of the slave clamping node VG_naccording to the voltage level of the clamping node VG_p1, the first switching signal SW<1>, the second switching signal SW<2> and the third switching signal SW<3>. The slave portion120cis electrically connected to the clamping node VG_p1. Certainly, the clamping method800amay be applied to the dynamic bit-line clamping circuit100afor the computing-in-memory applications ofFIG. 2. Hence, the clamping method800aof the present disclosure utilizes a dynamically configurable bit-line clamping scheme with automatically changeable configurations with a readout result from a prior cycle and a current read cycle, so that the dynamic bit-line clamping circuits100a,100cof the present disclosure are suitable for the computing-in-memory applications. Furthermore, the third clamping step S28of the present disclosure utilizes a current mirror scheme to generate the voltage level of the slave clamping node VG_naccording to the voltage level of the clamping node VG_p1, so that the voltage level of the slave clamping node VG_ncan be used by a subsequent circuit to avoid disturbing the clamping node VG_p1.

FIG. 8shows a comparison result of error rates between the clamping method800of the present disclosure and conventional methods. The clamping method800is applied to the dynamic bit-line clamping circuit100bfor the computing-in-memory applications ofFIG. 3. The conventional methods include a small-size conventional method and a large-size conventional method. The small-size conventional method represents that only one small-size MOS transistor is utilized in the conventional bit-line clamping circuit. The large-size conventional method represents that only one large-size MOS transistor is utilized in the conventional bit-line clamping circuit. The clamping method800of the present disclosure represents that the second clamping unit300bof the dynamic bit-line clamping circuit100butilizes a plurality of small-size MOS transistors (e.g., the first top transistor PM_1, the second top transistor PM_2, the third top transistor PM_3and the fourth top transistor PM_4inFIG. 3). The horizontal axis “lin, DC” represents DC currents of the bit line BL. Therefore, the comparison result shows that the clamping method800of the present disclosure can effectively improve the error rates of the conventional methods via the dynamically configurable bit-line clamping scheme in the widely bit-line current distribution.

According to the aforementioned embodiments and examples, the advantages of the present disclosure are described as follows.

1. The dynamic bit-line clamping circuit of the present disclosure utilizes a dynamically configurable bit-line clamping scheme with automatically changeable configurations with a readout result from a prior cycle and a current read cycle, so that the dynamic bit-line clamping circuit of the present disclosure is suitable for the computing-in-memory applications.

2. The slave portion of the present disclosure utilizes a current mirror scheme to generate the voltage level of the slave clamping node according to the voltage level of the clamping node, so that the voltage level of the slave clamping node can be used by a subsequent circuit to avoid disturbing the clamping node.

3. The current mirror scheme of the present disclosure can reconfigure currents of PMOS transistors according to the current flow through.

4. The clamping method of the present disclosure can effectively improve the error rates of the conventional methods via the dynamically configurable bit-line clamping scheme in the widely bit-line current distribution.