Computer system and memory bridge for processor socket thereof

A multi-processor computer system includes a memory bridge configured in a processor socket on a motherboard. The memory bridge module electrically connects a processor bus and a memory bus that connect to the processor socket. Thus, an adjacent processor is capable of accessing an unused memory by way of the processor bus, the memory bridge and the memory bus.

BACKGROUND OF THE INVENTION

1. Field of Invention

The present invention relates to a computer system for data processing, and more particularly, to a computer system having a memory bridge configured in a processor socket to electrically connect a processor bus and a memory bus.

2. Related Art

The most significant component in a computer system is the CPU (Central Processing Unit), which is undoubtedly as important as a heart to a human. To precisely process data that becomes larger and more complex at a higher speed, several CPUs are configured on a mother board and/or an expansive CPU card to build up a multi-processor computer system. However, the mechanism of accessing memory still creates a bottleneck in high performance computing.

In a conventional system with south/north bridge architecture, memory accessing is controlled by a north bridge chip. As Shown inFIG. 1A, two processors71and72of a dual-processor system share a system memory74, wherein the north bridge is utilized as a memory controller hub (MCH)73. When only one of processor71and72is operating, almost all the system memory74is available. However, the accessing speed will be limited due to the control process of the MCH73. And such situation becomes more obvious while the processor71and72are both operating and sharing the bandwidth of a memory bus between the MCH73and the system memory74.

To solve the problem, cache memory is used to save common commands and data for CPU to access. No matter imbedded in the CPU or configured externally, the cache memory avoids the CPU from accessing system memory frequently and from slowing down the whole system. But for the system memory that managed by the MCH or north bridge, this sharing architecture is still a limitation itself.

Please refer toFIGS. 1B and 1C. In the illustrated four-processor system, each of the processor P0, P1, P2and P3has dedicated memory M0, M1, M2and M3respectively. The processor P0, P1, P2and P3connect each other by processor buses PB, and connect to an I/O controller IOC such as a south bridge or a PCI bridge by an I/O bus IOB. In each of the processor P0, P1, P2and P3, a crossbar switch XBAR is configured to connect a Bus Port BP0, BP1and BP2, and a memory controller MCT and a system request queue SRQ. The system request queue SRQ manages data processing requests for the processing core C while each memory controller MCT controls the accessing processes of the memory M0, M1, M2and M3through each memory bus MB. Under certain conditions, the memory accessing architecture shown inFIG. 1Bprovides higher accessing speed than the one shown inFIG. 1A, thereby allowing the processor P0, P1, P2and P3achieve the best performance. Furthermore, the processor P0, P1, P2and P3are capable of sharing memory M0, M1, M2and M3by way of processor buses PB and crossbar switch XBAR to reach optimum efficiency of memory utilization.

However, when one CPU fails in this multi-processor system, or one or more CPUs are removed by the user due to special reasons, those memories connected to the failed/removed will become unused. That is truly a waste.

SUMMARY OF THE INVENTION

To solve the problems mentioned above, the present invention discloses a computer system and a memory bridge thereof to enable a processor to communicate with an unused memory, an I/O controller or a subsystem in circuit connection with an unused processor socket, without configuring an additional processor in the unused processor socket or any system architecture changes.

According to an embodiment of the present invention, a computer system includes a mother board that further includes at least one first processor socket, at least one second processor socket, at least one memory, at least one processor bus, at least one memory bus, at least one processor and at least one memory bridge. The processor bus is for electrically connecting the first processor socket and the second processor socket. The memory bus is for electrically connecting the second processor socket and the memory. The processor is configured in the first processor socket for electrically connecting the processor bus through the first processor socket. And the memory bridge is configured in the second processor socket for electrically connecting both the processor bus and the memory bus through the second processor socket. Thus, the processor accesses the memory through the processor bus, the memory bridge and the memory bus.

According to an embodiment of the present invention, a computer system includes a mother board that further includes at least one first processor socket, at least one second processor socket, at least one processor, at least one I/O bus, at least one memory bus, at least one processor and at least one memory bridge. The processor bus is for electrically connecting the first processor socket and the second processor socket. The I/O bus is for electrically connecting the second processor socket. The memory bus is for electrically connecting the second processor socket. The processor is configured in the first processor socket for electrically connecting the processor bus through the first processor socket. And the memory bridge is configured in the second processor socket for electrically connecting the processor bus, the I/O bus and the memory bus through the second processor socket. Thus, the processor electrically connects to the I/O bus and the memory bus through the processor bus and the memory bridge.

According to an embodiment of the present invention, a memory bridge is provided for replacing a second processor to configure in a second processor socket on a mother board. The second processor socket electrically connects a processor bus and a memory bus. The memory bridge includes a plurality of first and second electrical contacts, a memory controller and a control unit. The first electrical contacts are for configuring into the second processor socket to electrically connect the processor bus. The second electrical contacts are for configuring in the second processor socket to electrically connect the memory bus. The memory controller is in circuit connection with the second electrical contacts. And the control unit is in circuit connection with the first electrical contacts and the memory controller to control signal/data transmission between the first electrical contacts and the memory controller.

DETAILED DESCRIPTION OF THE INVENTION

Please refer toFIG. 2, which shows a dual-processor computer system and a memory bridge thereof according to an embodiment of the present invention. A mother board40configures thereon a processor bus31, two memory buses32, a processor11, a memory bridge12, a first processor socket41, a second processor socket42and two memory22and22′. The processor11inserts in the first processor socket41while the memory bridge12replaces a processor11′ to insert in the second processor socket42to achieve indirectly electrical connection with the processor bus31and the memory bus32. Thus, the processor bus31and the memory bus32are linked together.

The processor11and11′ disclosed in the present embodiment are central processing units (CPUs) while the memory22and22′ are system memories for the processor11and11′ respectively. The processor bus31is substantially of dual uni-directional point-to-point bus, such as a bus compatible with HyperTransport standard, capable of applying to the communication between a processor and a chipset, an I/O controller or a “subsystem” (generally the second mother board with expansion buses or other expansion functions). The processor bus31is configured between the first processor socket41and the second processor socket42to electrically connect the processor11and the memory bridge12. The memory bus32located between the second processor socket42and the memory22′ is for connecting the memory bridge12and the memory22′. Therefore, the processor11is capable of accessing the memory22′ through the processor bus31, the memory bridge12and the memory bus32, without configuring the second processor11′ in the second processor socket42.

The memory bridge12may be a circuit board module. To be configured in the second processor socket42, the memory bridge12has the same package structure as the processor11or11′. The first processor socket41and the second processor socket42will have the same specification if the mother board40remains the same architecture for the memory bridge12. If the specification of the second processor socket42is changed, the memory bridge12will no longer need to have the same specification as the processor11′, but need to be compatible with the second processor socket42and its pins that have certain definitions.

Please refer toFIGS. 3A and 3B. The memory bridge12is a circuit board module with processor-package structure to be configured in a pedestal421of the second processor socket42. The pedestal421is fastened on the mother board40. When the memory bridge12is inserted in the pedestal421, a cover422is closed to the pedestal421, with a lever423of the cover422engaged with a hook425of the pedestal421. The memory bridge12has a first surface124that configures a plurality of first electrical contacts121and second electrical contacts122for configuring into the first and second processor sockets41and42respectively. The first electrical contacts121serve as a bus port to connect a processor bus or an I/O bus while the second electrical contacts122serve as a memory port to connect a memory bus. When the memory bridge12is inserted in the pedestal421, the first electrical contacts121and the second electrical contacts122connect a plurality of responsive flexible members424on the pedestal421respectively. Each of the flexible members424is for electrically connecting to the traces (not shown) of the processor bus31and the memory bus32(referring toFIG. 2) on the mother board40respectively. Each of the first electrical contacts121is responding to one of the second electrical contact122(having the same definition), using electrical components123(integrated circuits shown inFIG. 3B) located on a second surface125and essential circuits to connect each other, thereby linking the processor bus31and the memory bus32. The first and second electrical contacts121and122and the connected electrical component123should have unlimited relative positions. For those skilled in the art, the practical forms of the memory bridge12may be integrated circuits with semiconductor processing package for a processor. Providing that the second processor socket42is unchanged, the first electrical contacts121and the second electrical contacts122are metal pads with the same pitches and diameters as the processor11′. The second processor socket42illustrated inFIGS. 3A and 3Bis of a LGA (Land Grid Array) package type, which is only for explanation and should not be a limitation for the application field of the memory bridge12. InFIG. 4, if the replaced processor11′ has a package type of PGA (Pin Grid Array), then the memory bridge12will need a plurality of metal pins for serving as electrical contacts. Correspondingly, the pedestal421of the second processor socket12will need insert holes for receiving the pins and furthermore, other electrical contacts located in the insert holes to electrically connect the inserted pins. Except the first and second electrical contacts121and122, other electrical contacts configured on the processor11′ are optional for the memory bridge12.

As to the definition of each of the first electrical contacts121, since aforesaid processor bus31is a dual uni-directional point-to-point bus, such as a HyperTransport-compatible bus, the first electrical contacts and the electrical contacts of the second processor socket42must follow the same specification as well. Generally, when a processor configured in a processor socket, it could possibly support more than two dual uni-directional point-to-point buses. For example, an AMD Opteron™ MP processor supports three HyperTransport buses each holds the equal position for BIOS (Basic Input/Output System). That means no master/slave differences for the three buses when processing data. So the positions of these 3 buses are equal to each other and not restricted to certain linking processors, buses or controllers. However, if a memory bridge is configured, the processor bus31needs to meet the same requirements to provide a transmission channel between the memory bridge12and the processor11configured in the first processor socket41, as shown inFIG. 2. According to the embodiment of the present invention, the memory bus32has to fit the type of system memory and data transmission specifications. Same requirements are also necessary to the second electrical contacts122that serve as the memory port.

Please refer toFIG. 5, which is to further disclose the electrical components123and essential circuits (shown inFIG. 3A) configured on the memory bridge12. The memory bridge12includes a control unit13, a bus port141, a memory port142and a memory controller143. In practice the bus port141serves as the first electrical contacts121inFIGS. 3A and 3Bwhile the memory port142are provide by the second electrical contacts122inFIGS. 3A and 3B. The control unit13includes a transmit physical layer131, a receive physical layer132, a transmit logic133, a receive logic134, a phase locked loop135, a reset logic136and a link-cycle controller137, which are of integrated circuits or chips.

The transmit physical layer131, the receive physical layer132, the transmit logic133and the receive logic134enable the control unit13to connect via the bus port141to the processor bus31. And similarly, the memory controller143connects the memory22′ through the memory port142and the memory bus32for access management.

The receive physical layer132is in circuit connection with the receive logic134and the bus port141(the first electrical contacts) to receive signal/data from the processor bus31and transmit to the receive logic134for processing. The transmit physical layer131is in circuit connection with the transmit logic133and the bus port141. Signal/data from the memory controller143will be first processed by the transmit logic133and then be transmitted through the transmit physical layer131, the bus port141to the processor bus31.

The memory controller143is in circuit connection with the transmit logic133, the receive logic134and the memory port142(the second electrical contacts122). When the processor11needs to access the memory22′, the memory controller143processes all the related management tasks through the processor bus31, the receive physical layer132, the transmit physical layer131, the receive logic134and the transmit logic133.

The phase locked loop135is to generate the core clock for the transmit physical layer131, the receive physical layer132, the transmit logic133and the receive logic134to limit all the electrical components of the entire memory bridge12to a specific operating frequency range. The reset logic136is to process the reset and initialization tasks for the memory bridge12, including resetting the state machine to an initial state. The link-cycle controller137is to manage link communication of the transmit physical layer131, the receive physical layer132, the transmit logic133, the receive logic134and the memory controller143.

As to those systems that apply HyperTransport technology, said transmit physical layer131, the receive physical layer132, the transmit logic133and the receive logic134should follow the data receive/transmit protocol for HyperTransport.

Please refer toFIG. 6. In another practical embodiment for a dual-processor system according to the present invention, a mother board40has a processor bus31, two I/O (input/output) buses33and33′, two memory buses32and32′, a processor11, a memory bridge12, a first processor socket41, a second processor socket42, two I/O controllers21and21′ and two memories22and22′. The processor11is configured in the first processor socket41while the memory bridge12replaces another processor11′ to be configured in the second processor socket42, thereby electrically connecting with the processor bus31, the I/O bus33′ and the memory bus32′ to transmit signal/data. In practice the processor11and11′ are CPUs while the I/O controller21may be north bridge, south bridge, a I/O bridge, or a single bridge chip integrating south and north bridges.

The processor bus31and the I/O bus33/33′ are substantially dual uni-directional point-to-point buses that have the same data transmission protocol, such as HyperTransport-compatible buses for applying to data and signal transmission between processors, or between a processors and a chipset, an I/O controller or a subsystem. Therefore, the processor11is enabled to connect to the memory bridge12through the processor bus31, thereby utilizing the I/O controller21′ via the I/O bus33′, or accessing the memory22′ through the memory bus32′.

As shown inFIG. 7, to realize the architecture mentioned above, except all the components shown inFIG. 5(including the bus port141, the transmit physical layer131, the receive physical layer132, the transmit logic133, the receive logic134, the phase locked loop135, the reset logic136and the link-cycle controller137), the memory bridge12needs additionally a second bus port144and another set of a second transmit physical layer151, a second receive physical layer153, a second transmit logic152and a second receive logic154with the link-cycle controller137serving as a switch controller.

The second bus port144may be practical by a set of third electrical contacts (not shown). The second bus port144(the third electrical contacts) has the same definitions as the first electrical contacts, such as HyperTransport standard, to connect the I/O bus33′.

the second receive physical layer153is in circuit connection with the second receive logic154and the second bus port144to receive signal/data from the I/O bus33′ and transmit to the second receive logic154for processing. The second receive logic154is in circuit connection with the transmit logic133and the memory controller143to transmit signal/data. The second transmit physical layer151is in circuit connection with the second transmit logic152and the second bus port144while the second transmit logic152is in circuit connection with the receive logic134and the memory controller143. After being processed by the second transmit logic152, signal/data from the memory controller143or the receive logic134will be transmitted through the second transmit physical layer151, the second bus port144to the I/O bus33′.

The present invention provides a memory bridge to achieve bridge connection of processor to processor, processor to unused memory, and processor to I/O controller. Furthermore, the memory is applicable to multi-processor system such as 2-way, 4-way and 8-way systems or even cluster computers.

Please refer toFIG. 8A, which illustrates a embodiment of a four-processor computer system with two processors11′ replaced by memory bridges12. In the present embodiment, the memory bridge12is similar to the one inFIG. 7. Two processors11are capable of accessing two memories22′ through the processor bus31, the memory bridge12and the memory bus32. Since the memory bridge12provides link to the processor bus31′, the processor bus31′ can operate normally. The processor11in the left-up corner can also access the memory22′ in the right-bottom corner. However, if a memory bridge as shown inFIG. 5is applied, the processor bus31′ will not be able to operate.

Please refer toFIG. 8B. A four-processor computer system have two memory bridges12configured in two second processor sockets42to connect two pairs of processor bus31and memory bus32, thereby enabling the two processors11configured in the two first processor sockets41to communicate with each other. Now we define Transmission Latency between processors as: the number of buses needed to achieve communications between any two processors. Then the replacement of the memory bridge12in the present embodiment causes no additional Transmission Latency, which means Latency maintain 2 without any increase. Each of the two processors11can access the two unused memories22′ connected by the two memory bridges12.

Please refer toFIG. 9. Three memory bridges12replaces processors11′ to configure in the second processor sockets42to enable the processors11to access one dedicated memory22and three unused memories22′.

Please refer toFIG. 10. In a 8-processor computer system according to the present embodiment, each processor11supports three HyperTransport bus (processor bus31and I/O bus33) and one memory bus32for the memory22, while the memory bridge12can support only two HyperTransport bus and one memory bus32′ for the memory22′. The processor bus31′ will not be functional when the memory bridge12is configured. For the two processors11in a diagonal corner, the transmission latency will remain as 3 without any increase. Similarly, multi-processor computer systems that have more than 8 processors can be operating in the same way with the technical features of the present invention.

The memory disclosed in the present invention is system memory dedicated to CPUs. In practice the memory may include one or more memory module with RAM (Random Access Memory) units such as SDRAM.

As to detecting and determining whether a processor or a memory bridge is configured in a processor socket, one or more GPIO (General Purpose Input/Output) pin of an I/O controller will be available for current computer systems to change the voltage level, which can be detected by BIOS to make related modifications. However, that is not the major feature of the present invention and further description herein is necessary.