SEMICONDUCTOR STRUCTURE AND FORMATION METHOD THEREOF

A semiconductor structure includes a substrate, a covering layer on the substrate, an auxiliary layer on the covering layer, a first dielectric layer on surfaces of the substrate and the auxiliary layer, and a conductive structure in the first dielectric layer. The semiconductor structure also includes a second dielectric layer on surfaces of the first dielectric layer and the conductive structure, a first opening in the second dielectric layer and the first dielectric layer, and a second opening in the second dielectric layer. The first opening exposes the auxiliary layer, and the second opening exposes the top surface of the conductive structure. A first conductive layer is in the first opening, and a second conductive layer is in the second opening. A growth rate of the first conductive layer over the auxiliary layer is higher than the growth rate of the first conductive layer over the covering layer.

TECHNICAL FIELD

The present disclosure generally relates to the field of semiconductor manufacturing technology and, more particularly, relates to a semiconductor structure and a formation method thereof.

BACKGROUND

As integration levels of semiconductor devices continuously increase, critical dimensions of transistors may continuously decrease. Various practical and fundamental limitations and technical challenges begin to emerge, and further reduction in device sizes is becoming increasingly difficult.

The rapid development of integrated circuit technology has put forward higher requirements for metal interconnection technology. Traditional aluminum metal interconnection technology may no longer meet needs of the development of modern interconnection technology. Damascus-structure copper metal interconnection technology has become one of key development directions of interconnection technology. However, as the characteristic line width of integrated circuits shrinks to a few nanometers, copper interconnect technology also faces huge challenges. There are more and more layers of metal wiring, and resistance of metal wires and parasitic capacitance between the metal wires are becoming more and more restrictive factors affecting speeds of devices.

As such, existing metal interconnection line technology needs to be further improved.

SUMMARY

The present disclosure provides a semiconductor structure and a formation method thereof to improve performance of semiconductor structures.

To solve the above technical problems, the present disclosure provides a semiconductor structure. The semiconductor structure includes: a substrate; a covering layer located over part of the substrate; an auxiliary layer located over a surface of the covering layer; a first dielectric layer located over surfaces of the substrate and the auxiliary layer; a conductive structure located in the first dielectric layer, where a top surface of the first dielectric layer is flush with a top surface of the conductive structure; a second dielectric layer located over surfaces of the first dielectric layer and the conductive structure; a first opening located in the second dielectric layer and the first dielectric layer, where the first opening exposes the auxiliary layer, and a second opening located in the second dielectric layer, where the second opening exposes the top surface of the conductive structure; and a first conductive layer located in the first opening, and a second conductive layer located in the second opening.

Optionally, the substrate includes a base, a gate structure located over the base, and an interlayer dielectric layer located over the base, where the interlayer dielectric layer is also located over sidewalls of the gate structure and exposes a top surface of the gate structure, and the covering layer is located over the top surface of the gate structure.

Optionally, the substrate also includes a source/drain layer located in the substrate on two sides of the gate structure, where a bottom of the conductive structure is deep into the substrate and is located over a surface of the source/drain layer.

Optionally, a material of the covering layer includes metal.

Correspondingly, the present disclosure also provides a method of forming a semiconductor structure. The method includes: providing a substrate; forming a covering layer over part of the substrate; using a first selective deposition process to form an auxiliary layer over a surface of the covering layer; forming a first dielectric layer over surfaces of the substrate and the auxiliary layer; forming a conductive structure in the first dielectric layer, where a top surface of the first dielectric layer is flush with a top surface of the conductive structure; forming a second dielectric layer over surfaces of the first dielectric layer and the conductive structure; forming a first opening and a second opening, where the first opening is located in the second dielectric layer and the first dielectric layer, and the first opening exposes the auxiliary layer, and the second opening is located in the second dielectric layer and the second opening exposes the top surface of the conductive structure; and forming a first conductive layer in the first opening and forming a second conductive layer in the second opening, where a growth rate of a material of the first conductive layer over the surface of the auxiliary layer is higher than the growth rate of the material of the first conductive layer over the surface of the covering layer.

Optionally, a material of the auxiliary layer includes tungsten.

Optionally, a process of forming the auxiliary layer includes a chemical vapor deposition process; and process parameters of the chemical vapor deposition process include: reaction gas includes tungsten hexafluoride and hydrogen, and reaction temperature ranges from 300 degrees Celsius to 400 degrees Celsius.

Optionally, the substrate includes a base, a gate structure located over the base, and an interlayer dielectric layer located over the base, where the interlayer dielectric layer is also located over sidewalls of the gate structure and exposes a top surface of the gate structure, and the covering layer is located over the top surface of the gate structure.

Optionally, the substrate further includes a source/drain layer located in the substrate on two sides of the gate structure, where a bottom of the conductive structure is deep into the substrate and is located over a surface of the source/drain layer.

Optionally, the covering layer includes first ions, a material of the covering layer includes metal ions, the first ions and the metal ions form first chemical bonds; the auxiliary layer includes the metal ions and second ions, the second ions and the metal ions form second chemical bonds, and bond energy of the second chemical bonds is lower than bond energy of the first chemical bonds.

Optionally, the first ions include chloride ions, and the second ions include fluoride ions.

Optionally, the metal includes tungsten.

Optionally, a process of forming the covering layer includes a selective atomic layer deposition process.

Optionally, process parameters of the atomic layer deposition process include: reaction gas includes tungsten chloride and hydrogen, and reaction temperature ranges from 400 degrees Celsius to 500 degrees Celsius.

Optionally, a process of forming the first conductive layer and the second conductive layer includes a second selective deposition process.

Optionally, process parameters of the second selective deposition process include: reaction gas includes tungsten hexafluoride and hydrogen, and reaction temperature ranges from 300 degrees Celsius to 400 degrees Celsius.

Optionally, a process of forming the first conductive layer and the second conductive layer includes: depositing a conductive material layer in the first opening and the second opening until the first opening and the second opening are fully filled; and planarizing the conductive material layer until the second dielectric layer is exposed.

Optionally, a growth rate of the conductive material layer over the surface of the auxiliary layer is higher than a growth rate of the conductive material layer over the surface of the conductive structure.

Optionally, a material of the first conductive layer and the second conductive layer includes tungsten.

Optionally, a thickness of the auxiliary layer ranges from 1 nanometer to 10 nanometers.

Optionally, a material of the conductive structure includes cobalt.

Compared with the existing technology, the technical solution of the present disclosure has the following advantages.

In the formation method provided by the present disclosure uses uses a first selective deposition process to form an auxiliary layer over the surface of the covering layer. A first conductive layer is formed in the first opening, and a second conductive layer is formed in the second opening. The growth rate of the first conductive layer material over the surface of the auxiliary layer is higher than the growth rate of the first conductive layer material over the surface of the covering layer. Accordingly, the difference between the growth rate of the material of the first conductive layer in the first opening over the surface of the auxiliary layer and the growth rate of the material of the second conductive layer in the second opening over the surface of the conductive structure may be reduced. As such, the chance that the first opening on the auxiliary layer is closed in advance before being fully filled may be reduced, and the performance of the semiconductor structure formed may be improved.

Further, the covering layer includes first ions. The material of the covering layer includes metal ions. First chemical bonds may be formed between the first ions and the metal ions. The auxiliary layer includes metal ions and second ions. The second ions and the metal ions form second chemical bonds, and the second chemical bond energy is lower than the first chemical bond energy. The second chemical bonds are easier to break than the first chemical bonds. Accordingly, the rate of the reaction that subsequently forms the material of the first conductive layer over the surface of the auxiliary layer may be improved.

Further, the first ions include chloride ions and the second ions include fluoride ions. The auxiliary layer includes tungsten-fluorine bonds. The existence of tungsten-fluorine bonds provides preparation for the formation of tungsten material, shortening the time for adsorbing tungsten hexafluoride gas during the process of forming the first conductive layer. The growth rate of the tungsten material formed over the surface of the auxiliary layer may be increased, and the growth rate of the tungsten material in the first opening may be higher than the growth rate of the tungsten material in the second opening. Accordingly, the chance that the first opening may be closed in advance before being fully filled may be reduced, and the performance of the semiconductor structure formed may thus be improved.

DETAILED DESCRIPTION

It should be noted that terms “surface” and “over” in the present disclosure are used to describe relative positional relationships in space, and are not limited to direct contact.

As mentioned in the background, performance of semiconductor structures formed using existing metal interconnection line technology needs to be improved urgently. Explanation and analysis will now be made in conjunction with a method of forming a semiconductor structure.

FIGS.1-5illustrate schematic cross-sectional views corresponding to certain stages of a process of forming a semiconductor structure.

Referring toFIG.1, the process includes proving a substrate101. A gate structure is disposed over the substrate101. The gate structure includes a metal gate101and a gate dielectric layer102. A spacer103is disposed over a sidewall of the gate structure. A source/drain region104is disposed in the substrate101on two sides of the spacers103. An interlayer dielectric layer105is disposed over the substrate100. The interlayer dielectric layer105is located over the sidewalls of the spacers103and exposes the top surface of the gate structure.

Referring toFIG.2, the process also includes forming a covering layer106over the surface of the metal gate101; forming a first etch stop layer108over the interlayer dielectric layer105, the surface of the gate structure and the top of the spacer102; and forming a first dielectric layer107over the surface of the first etching stop layer108.

Referring toFIG.3, the process also includes forming a first opening (not marked inFIG.3) in the first dielectric layer107, the first etch stop layer108and the interlayer dielectric layer105, the first opening exposing the source/drain regions104; and forming a conductive structure109within the first opening.

Referring toFIG.4, the process also includes forming a second etching stop layer110over the surface of the conductive structure109and the first dielectric layer107; forming a second dielectric layer112over the surface of the second etching stop layer110; forming a second opening112in the second dielectric layer112, the second etching stop layer110, the first dielectric layer107and the first etching stop layer108, the second opening112exposing the top surface of the covering layer106; forming a third opening113in the second dielectric layer112and the second etching stop layer110, the third opening113exposing the top surface of the conductive structure109.

Referring toFIG.5, the process also includes forming a metal layer114in the second opening112and the third opening113.

The above process may be used in metal interconnection line technology. The covering layer106may be made of tungsten and may be formed using an atomic layer deposition (ALD) process. The metal tungsten formed may have good selectivity over the surface of the metal gate101, and the covering layer106formed may have good uniformity and good density. The atomic layer deposition process does not contain fluorine ions to avoid adverse effects of fluorine ions over the work function layer of the gate structure, but the deposition rate may be low. The conductive structure109is made of cobalt. The material of the metal layer114is also tungsten. Since a chemical vapor deposition (CVD) process may have better step coverage and takes less time than the atomic layer deposition process, the metal layer114may be formed using the chemical vapor deposition process.

However, since the atomic layer deposition process uses reaction between tungsten chloride (such as WCl3) and hydrogen, the covering layer106may have a large number of tungsten-chlorine bonds. In the atomic layer deposition process, the reaction temperature of the reaction between tungsten chloride and hydrogen is 460 degrees Celsius. In the process of forming the metal layer114using the chemical vapor deposition process, metal tungsten selectively grows over the surface of the metal material. The reaction gases include tungsten hexafluoride and hydrogen, and the reaction temperature is below 400 degrees Celsius. Under conditions below 400 degrees Celsius, the large number of tungsten-chlorine bonds present in the covering layer106are more stable than the tungsten-fluorine bonds in the reaction gas tungsten hexafluoride. The existence of the tungsten-chlorine bonds may make it difficult to form a tungsten material film in the chemical vapor deposition process. As such, a growth rate of tungsten material over the surface of the covering layer106may be much lower than a growth rate of tungsten material over the surface of the conductive structure109. In addition, the depth of the second opening112is greater than the depth of the third opening113. Furthermore, after the third opening113is fully filled with tungsten material, the second opening112may not be fully filled with tungsten material. After the third opening113is fully filled, the tungsten material may continue to grow and may cover the surface of the second opening112, causing the second opening112to be closed in advance. As a result, defects such as holes may appear in the metal layer114formed in the second opening112, affecting the conductive performance of the metal layer114and lowering the performance of the semiconductor structure formed.

To solve the above problems, the present disclosure provides a method of forming a semiconductor structure. The method uses a first selective deposition process to form an auxiliary layer over the surface of the covering layer. A first conductive layer is formed in the first opening, and a second conductive layer is formed in the second opening. The growth rate of the first conductive layer material over the surface of the auxiliary layer is higher than the growth rate of the first conductive layer material over the surface of the covering layer. Accordingly, the difference between the growth rate of the material of the first conductive layer in the first opening over the surface of the auxiliary layer and the growth rate of the material of the second conductive layer in the second opening over the surface of the conductive structure may be reduced. As such, the chance that the first opening over the auxiliary layer is closed in advance before being fully filled may be reduced, and the performance of the semiconductor structure formed may be improved.

To make the above objects, features and beneficial effects of the present disclosure more obvious and understandable, specific embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

FIGS.6-12illustrate structural schematics corresponding to certain stages of a method of forming a semiconductor structure, consistent with the disclosed embodiments of the present disclosure.

Referring toFIG.6, the method includes providing a substrate.

In one embodiment, the substrate includes a base201, a gate structure located over the base201, and an interlayer dielectric layer202located over the base201. The interlayer dielectric layer202is also located over sidewalls of the gate structure and exposes a top surface of the gate structure.

The gate structure includes a gate layer203and a spacer204located over a sidewall of the gate layer203.

The gate layer203is made of metal. In one embodiment, the gate layer203is made of aluminum.

A process of forming the gate structure includes: forming a dummy gate (not marked inFIG.6) over the base201; forming the spacer204over a sidewall of the dummy gate; forming the interlayer dielectric layer202over the surface of the base201, the interlayer dielectric layer202exposing the top surface of the dummy gate; etching away the dummy gate to form a groove (not marked inFIG.6) in the interlayer dielectric layer202; and forming the gate layer203within the groove.

In one embodiment, after forming the groove and before forming the gate layer203, a gate dielectric layer205is also formed over the side walls and bottom of the groove. The material of the gate dielectric layer205includes a high-K dielectric material.

In one embodiment, the gate structure also includes a work function layer (not marked inFIG.6) located between the gate dielectric layer205and the gate layer203.

In one embodiment, the substrate200also includes a source/drain layer206located in the base201on two sides of the gate structure.

Referring toFIG.7, the method also includes forming a covering layer207over a part of the substrate; and using a first selective deposition process to form an auxiliary layer208over a surface of the covering layer207.

The auxiliary layer208may be used to subsequently increase a growth rate of the material of the first conductive layer over the covering layer207.

In one embodiment, the covering layer207is located over the top surface of the gate structure202. Specifically, the covering layer207is located over the top surface of the gate layer203. The covering layer207may be used to block the diffusion of ions into the gate layer203, and thus the threshold voltage and other properties of the device formed may be maintained.

The material of the covering layer207includes metal, and the metal includes tungsten. In one embodiment, the metal is tungsten.

A process of forming the covering layer207includes a selective atomic layer deposition process.

In one embodiment, process parameters of the atomic layer deposition process include: the reaction gas includes tungsten chloride and hydrogen, and the reaction temperature ranges from 400 degrees Celsius to 500 degrees Celsius. Tungsten chloride reacts with hydrogen to form tungsten. The selective atomic layer deposition process may make the tungsten material have good selectivity over the surface of the gate layer203and a uniform and dense material film may be formed. The process of forming the covering layer207does not include fluorine ions to avoid the adverse effects of fluorine ions over the work function layer of the gate structure. However, limited by the atomic layer deposition process, the deposition rate may be slow.

The covering layer207includes first ions. The material of the covering layer207includes metal ions. First chemical bonds may be formed between the first ions and the metal ions.

Specifically, the first ions include chloride ions. In one embodiment, the covering layer207is formed by the reaction of tungsten chloride and hydrogen, and chloride ions are thus introduced into the covering layer207. The first ions are chloride ions. In addition, the material of the covering layer207includes tungsten ions, and the first chemical bonds formed between chlorine ions and tungsten ions are tungsten-chlorine bonds. The tungsten-chlorine bonds are not easily broken compared to the tungsten-fluorine bonds. When tungsten hexafluoride and hydrogen are reacted over the surface of the covering layer207to form the first conductive layer of tungsten material, the growth of the tungsten material may become difficult due to the presence of tungsten-chlorine bonds.

The auxiliary layer208includes metal ions and second ions. The second ions and the metal ions form second chemical bonds, and the second chemical bond energy is lower than the first chemical bond energy. The second chemical bonds are easier to break than the first chemical bonds. Accordingly, the rate of the reaction that subsequently forms the material of the first conductive layer over the surface of the auxiliary layer208may be improved.

Specifically, the material of the auxiliary layer208includes tungsten; and the second ions include fluorine ions. In one embodiment, the material of the auxiliary layer208is tungsten; and the second ions are fluorine ions.

A process of forming the auxiliary layer208includes a chemical vapor deposition process. Process parameters of the chemical vapor deposition process include: the reaction gas includes tungsten hexafluoride and hydrogen, and the reaction temperature ranges from 300 degrees Celsius to 400 degrees Celsius.

Specifically, in one embodiment, the auxiliary layer208includes tungsten-fluorine bonds, and the covering layer207includes chlorine-tungsten bonds. Since the bond energy of the tungsten-fluorine bonds is lower than the bond energy of the chlorine-tungsten bonds, compared to forming the first conductive layer over the surface of the covering layer207, growing the tungsten material over the surface of the auxiliary layer208is relatively easy.

The thickness of the auxiliary layer208ranges from 1 nanometer to 10 nanometers. In a subsequent etching process of forming the first opening to expose the auxiliary layer208, the auxiliary layer208may be damaged. When the thickness of the auxiliary layer208is too small (i.e., less than 1 nanometer), the auxiliary layer208may be consumed and become ineffective. When the thickness of the auxiliary layer208is too large, that is, greater than 10 nanometers, on the one hand, the surface of the first dielectric layer210material film subsequently formed over the substrate surface may be uneven, affecting device performance, and on the other hand, unnecessary process waste may be caused.

Referring toFIG.8, the method also includes forming a first dielectric layer210over the surface of the substrate and the auxiliary layer208.

The material of the first dielectric layer210is a dielectric material. The dielectric material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxynitride.

In one embodiment, before forming the first dielectric layer210, a first etch stop layer209is also formed over the surface of the substrate and the auxiliary layer208. When the first opening is subsequently formed, the first etch stop layer209may be used to reduce etching damage to the auxiliary layer208.

Referring toFIG.9, the method also includes forming a conductive structure211in the first dielectric layer210. The top surface of the first dielectric layer210is flush with the top surface of the conductive structure211.

In one embodiment, the bottom of the conductive structure211is deep into the substrate and is located over the surface of the source/drain layer206.

A process of forming the conductive structure211includes: forming a first patterned layer (not shown inFIG.9) over the surface of the first dielectric layer210, the first patterned layer exposing part of the first dielectric layer210; using the first patterned layer as a mask to etch the first dielectric layer210, the first etch stop layer209, and the interlayer dielectric layer202until the surface of the source/drain layer206is exposed; forming a third opening (not marked inFIG.9) in the first dielectric layer, the first etch stop layer209and the interlayer dielectric layer206; and depositing metal material in the third opening to form the conductive structure211.

The conductive structure211is made of cobalt. As a wire material, cobalt material has good filling capacity and conductivity, making the device formed have high conductivity and low power consumption.

Referring toFIG.10, the method also includes forming a second dielectric layer213over the surface of the first dielectric layer210and the conductive structure211.

The material of the second dielectric layer213is a dielectric material. The dielectric material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxynitride.

In one embodiment, before forming the second dielectric layer213, a second etching stop layer212is also formed over the surface of the first dielectric layer210and the conductive structure211. When subsequently forming a second opening, the second etching stop layer212may be used to reduce etching damage to the conductive structure211.

Referring toFIG.11, the method also includes forming a first opening214and a second opening215. The first opening214is located in the second dielectric layer213and the first dielectric layer210, and the first opening214exposes the auxiliary layer208. The second opening215is located in the second dielectric layer213, and the second opening215exposes the top surface of the conductive structure211.

A process of forming the first opening214includes a dry etching process; and a process of forming the second opening215includes a dry etching process. By using the dry etching process, openings with good morphology may be formed.

In one embodiment, a process of forming the second opening215includes: forming a second patterned layer over the surface of the second dielectric layer213, the second patterned layer exposing part of the second dielectric layer213over the conductive structure211; and using the second patterned layer as a mask to etch the second dielectric layer213until the conductive structure211is exposed.

In one embodiment, a process of forming the first opening214includes: forming a third patterned layer over the surface of the second dielectric layer213and in the second opening215, the third patterned layer exposing part of the second dielectric layer213over the auxiliary layer208; using the third patterned layer as a mask to etch the second dielectric layer213and the first dielectric layer210until the auxiliary layer208is exposed; and after the auxiliary layer208is formed, removing the third patterned layer. In one embodiment, the first opening214is formed after the second opening215is formed. In some other embodiments, the sequence of forming the first opening214and forming the second opening215is not limited.

Referring toFIG.12, the method also includes forming a first conductive layer216in the first opening214and forming a second conductive layer217in the second opening215. A growth rate of the material of the first conductive layer216over the surface of the auxiliary layer208is higher than a growth rate of the material of the first conductive layer216over the surface of the covering layer207.

Since the growth rate of the material of the first conductive layer216over the surface of the auxiliary layer208is higher than the growth rate of the material of the first conductive layer216over the surface of the covering layer207, the difference between the growth rate of the material of the first conductive layer216in the first opening214and the growth rate of the material of the second conductive layer217in the second opening215may be reduced. As such, the chance that the first opening214over the auxiliary layer208is closed in advance before being fully filled may be reduced, and the performance of the semiconductor structure formed may thus be improved.

The material of the first conductive layer216and the second conductive layer217includes tungsten.

A process of forming the first conductive layer216and the second conductive layer217includes: depositing a conductive material layer (not marked inFIG.12) in the first opening214and the second opening215until the first opening214and the second opening215are fully filled; and planarizing the conductive material layer until the second dielectric layer213is exposed. The first conductive layer216and the second conductive layer217may be deposited simultaneously using a same metal material and in a same process, and production costs may thus be reduced.

The process of forming the first conductive layer216and the second conductive layer217includes a second selective deposition process. Specifically, the process of forming the first conductive layer216and the second conductive layer217includes a chemical vapor deposition process. The chemical vapor deposition process may have good step coverage. Compared to the atomic layer deposition process, the chemical vapor deposition may take less time and have lower costs.

Process parameters of the second selective deposition process include: the reaction gas includes tungsten hexafluoride and hydrogen, and the reaction temperature ranges from 300 degrees Celsius to 400 degrees Celsius.

The growth rate of the conductive material layer over the surface of the auxiliary layer208is higher than the growth rate over the surface of the conductive structure211. Since the depth of the first opening214is greater than the depth of the second opening215, the first opening214may not be fully filled. After the second opening215is fully filled, further deposition may make the material of the second conductive layer in the second opening215continue to grow. As such, the first opening214may be covered, causing the first opening214to be closed in advance. In one embodiment, the auxiliary layer208includes tungsten-fluorine bonds. The existence of tungsten-fluorine bonds provides preparation for the formation of tungsten material, shortening the time for adsorbing tungsten hexafluoride gas during the process of forming the first conductive layer. The growth rate of the tungsten material formed over the surface of the auxiliary layer208may be increased, and the growth rate of the tungsten material in the first opening214may be higher than the growth rate of the tungsten material in the second opening215. Accordingly, the chance that the first opening214may be closed in advance before being fully filled may be reduced, and the performance of the semiconductor structure formed may thus be improved.

Correspondingly, the present disclosure also provides a semiconductor structure formed by the method provided by the present disclosure. With continuous reference toFIG.12, the semiconductor structure includes: a substrate; a covering layer207located over part of the substrate; an auxiliary layer208located over the surface of the covering layer207; a first dielectric layer210located over the surface of the substrate and the auxiliary layer208; a conductive structure211located in the first dielectric layer210, where a top surface of the first dielectric layer210is flush with a top surface of the conductive structure211; a second dielectric layer213located over surfaces of the first dielectric layer210and the conductive structure211; a first opening214(as shown inFIG.11) located in the second dielectric layer213and the first dielectric layer210, where the first opening214exposes the auxiliary layer208; a second opening215located in the second dielectric layer213(as shown inFIG.11), where the second opening215exposes the top surface of the conductive structure211; a first conductive layer216located in the first opening214; and a second conductive layer217located in the second opening215.

The substrate includes a base201, a gate structure located over the base201, and an interlayer dielectric layer211located over the base201(as shown inFIG.11). The interlayer dielectric layer211is also located over sidewalls of the gate structure and exposes the top surface of the gate structure. The covering layer207is located over the top surface of the gate structure.

The substrate also includes a source/drain layer206located in the substrate on two sides of the gate structure. The bottom of the conductive structure211is deep into the substrate and is located over the surface of the source/drain layer206.

The material of the covering layer207includes metal, and the metal includes tungsten. In one embodiment, the material of the covering layer207is tungsten.

Although the present disclosure has been disclosed above, the present disclosure may not be limited thereto. Changes and modifications may be made by those skilled in the art without departing from the spirit and scope of the present disclosure. Therefore, the scope of the present disclosure should be determined by the scope defined by appended claims.