Enhanced state dual memory cell

A circuit may include a memory cell. The memory cell may include a first memory element, a second memory element, a first transistor, and a second transistor. The first memory element may be connected to a bit line. The second memory element may be connected to a select line. The first transistor may be connected to a first word line. The second transistor may be connected to a second word line. The first memory element may be programmed by applying a first write voltage to the bit line, applying a second write voltage to the second word line, applying a first intermediate voltage to the select line, and applying a second intermediate voltage to the first word line. The select line may be connected to a high impedance. The first write voltage may be a positive supply voltage, the second write voltage may be a negative supply voltage.

BACKGROUND

The present invention relates generally to a memory array structure and a method of programming the same. More particularly, the present invention relates to a memory array structure that includes an enhanced state dual memory cell.

Deep learning is a machine learning method based on artificial neural networks inspired by information processing in biological systems. Deep learning may be used in a wide spectrum of applications, including image processing, machine translation, speech recognition, and many others. In each of these domains, deep neural networks achieve superior accuracy through the use of very large and deep models. These deep models may include reduced-precision methods for data representation and computation.

SUMMARY

According to one embodiment of the present invention, a circuit is provided. The circuit may include a memory array. The memory array may include a plurality of bit lines, a plurality of word lines, a plurality of select lines. The plurality of bit lines and the plurality of select lines may intersect the plurality of word lines. The memory array may include a plurality of memory cells each including a first transistor, a second transistor, a first memory element, and a second memory element. The first and second memory elements may be connected to the plurality of word lines by way of the first and second transistors. The first and second memory elements may be connected to the plurality of bit lines and the plurality of select lines. The first transistor and the second transistor may be a complementary pair of bipolar junction pass transistors. The complementary pair of bipolar junction pass transistors may include an NPN bipolar junction pass transistor and a PNP bipolar junction pass transistor. The first transistor and the second transistor may be a complementary pair of junction field-effect transistors. The complementary pair of junction field-effect transistors may include an n-channel junction field-effect transistor and a p-channel junction field effect-transistor. The first memory element may be connected between one of the plurality of bit lines and a first shared collector emitter or source drain terminal of the complementary pair. The second memory element may be connected between one of the plurality of select lines and a second shared collector emitter or source drain terminal of the complementary pair. The second transistor in the one of the plurality of memory cells and a transistor of an opposite channel type in a memory cell adjacent to the one of the plurality of memory cells may have a base or a gate terminal connected to a same one of the plurality of word lines. The first memory element and the second memory element may be a phase-change memory, a resistive random access memory, or a magnetic random access memory. The first memory element and the second memory element may have same characteristics and the first memory element and the second memory element may be programmable to N states and the memory cell is programmable to

N⁡(N+1)2
states. The first memory element and the second memory element may have different characteristics and the first memory element and the second memory element may be programmable to N states and the memory cell is programmable to N2states.

According to another embodiment of the present invention, a circuit is provided. The circuit may include a memory cell. The memory cell may include a first memory element, a second memory element, a first transistor, and a second transistor. The first memory element may be connected to a bit line. The second memory element may be connected to a select line. The first transistor may be connected to a first word line, and the second transistor may be connected to a second word line. The first memory element may be programmed by applying a first write voltage to the bit line, applying a second write voltage to the second word line, applying a first intermediate voltage to the select line, and applying a second intermediate voltage to the first word line. The select line may be connected to a high impedance. The first write voltage may be a positive supply voltage, the second write voltage may be a negative supply voltage, and the first and second intermediate voltages may be ground voltages. The first write voltage may be greater than the first intermediate voltage, the first intermediate voltage may be greater than or equal to the second intermediate voltage, and the second intermediate voltage may be greater than the second write voltage. The first memory element may be erased by applying a first erase voltage to the first word line, applying a second erase voltage to the bit line, applying a first intermediate voltage to the select line, and applying a second intermediate voltage to the second word line. The first erase voltage may be a positive supply voltage, the second erase voltage may be a negative supply voltage, and the first and second intermediate voltages may be ground voltages. The first erase voltage may be greater than the first intermediate voltage, the first intermediate voltage may be greater than or equal to the second intermediate voltage, and the second intermediate voltage may be greater than the second erase voltage. The first transistor and the second transistor may be a complementary pair of bipolar junction pass transistors. The complementary pair of bipolar junction pass transistors may include an NPN bipolar junction pass transistor and a PNP bipolar junction pass transistor. The first transistor and the second transistor may be a complementary pair of junction field-effect transistors. The complementary pair of junction field-effect transistors may include an n-type junction field-effect transistor and a p-type junction field effect-transistor. The first memory element and the second memory element may be a phase-change memory, a resistive random access memory, or a magnetic random access memory.

According to another embodiment of the present invention, a method of reading a memory cell within a memory array is provided. The method may include applying a first read voltage of a first pair of read voltages to a bit line, applying a second read voltage of the first pair of read voltages to a select line connected to a second memory element, applying a first read voltage of a second pair of read voltages to a first word line, applying a second read voltage of the second pair of read voltages to a second word line, and applying an intermediate voltage to rest of bit lines, word lines, and select lines within the memory array. The bit line may be connected to a first memory element. The first word line may be connected to a first transistor. The second word line may be connected to a second transistor. The first transistor and the second transistor may be a complimentary pair of bipolar junction pass transistors. The first transistor may be an NPN bipolar junction pass transistor and the second transistor may be a PNP bipolar junction pass transistor. The first word line may be connected to a base of the NPN bipolar junction pass transistor and the second word line may be connected to a base of the PNP bipolar junction pass transistor. The first transistor and the second transistor may be a complementary pair of junction field-effect transistors. The first transistor may be an n-channel junction field-effect transistor and the second transistor may be a p-channel junction field effect transistor. The first word line may be connected to a gate of the n-channel junction field-effect transistor and the second word line may be s connected to a gate of the p-channel junction field-effect transistor. The first read voltage of the first pair of read voltages may be greater than the first read voltage of the second pair of read voltages, the first read voltage of the second pair of read voltages may be greater than the intermediate voltage, the intermediate voltage may be greater than the second read voltage of the second pair of read voltages, and the second read voltage of the second pair of read voltages may be greater than the second read voltage of the first pair of read voltages. The first read voltages of the first and second pair of read voltages may be positive voltage, and the second read voltages of the first and second pair of read voltages may be negative voltages, the second read voltages may have same amplitude as the first read voltages, and the intermediate voltage may be a ground voltage.

DETAILED DESCRIPTION

Deep learning is a machine learning method based on artificial neural networks. Deep learning may be used in a wide spectrum of applications, including image processing, machine translation, speech recognition, and many others. In each of these domains, deep neural networks achieve superior accuracy through the use of very large and deep models. These deep models may include reduced-precision methods for data representation and computation. Computation for deep neural networks may include both training and forward inference.

Multiplication operations (including convolution and matrix multiplication) are one of the most area and power consuming components in hardware implementation of deep neural networks. Recent advances in reduced-precision optimization suggest that at least a portion of the multiplication operations may be performed at lower precision. This means that the multiplication operations may be performed with a fewer number of bits, without compromising the end-to-end accuracy. This provides opportunities for power and/or area savings by employing analog devices such as resistive random access memory (RRAM) for weight storage. Further, it is desirable to employ analog devices (i.e. memory elements) with multiple (more than two) states, to increase the memory density for a given memory cell or a given memory design.

Conventional memory elements, in practice, are dual state, because they either have a state 0 or a state 1. These conventional memory elements cannot have more than two states because of reliability issues. As a result, conventional memory elements may be limited by the practical number of states (typically two).

In theory, increasing the number of memory elements per cell may increase the effective number of states per cell. For example, having two memory elements in each memory cell may increase the number of states from two states to four states, given that each memory element has two states. The two memory elements may be combined to obtain four states by using mathematical permutations of their two states. For example, if the first memory element has a state 0, and the second memory element has a state 0, then the combination of the two memory element states may provide memory cell State 1. If the first memory element has a state 0 and the second memory element has a state 1, then the combination of the two memory element states may provide memory cell State 2. If the first memory element has a state 1 and the second memory element has a state 0, then the combination of the two memory element states may provide memory cell State 3. If the first memory element has a state 1 and the second memory element has a state 1, then the combination of the two memory element states may provide memory cell State 4.

In practice however, additional circuitry and processors such as, for example, transistors, are needed to combine the states of two or more memory elements in a useable way that may then be deployed. Having additional transistors, and corresponding wires, may increase the footprint of the circuit thus reducing memory density. The result may be a single memory cell that includes more than two states but whose footprint is larger than two memory cells, where each cell has two states. As such, there exists a need for a memory cell that includes more than two states and that is smaller than the footprint of two memory cells combined.

Embodiments of the present invention provide a new circuit structure. The new circuit structure is a cross-point memory array that includes a plurality of enhanced state dual memory cells. Each of the dual memory cells includes two transistors and two memory elements. As such, the memory cell may also be referred to as a 2T2R cell. The cross-point memory array, having a plurality of the 2T2R cells may increase the effective number of states per cell when compared to a conventional memory array. In an embodiment, the transistors within the memory cell are configured as complementary pass gates (transmission gates). In an embodiment, the memory cells are configured as RRAM/pass-gate/RRAM vertically-stacked structures thus minimizing the cell footprint and achieving a high density of bits per area.

FIGS.1-6illustrate an exemplary circuit structure that includes a plurality of memory cells. Each memory cell includes two transistors integrated with two memory elements.

Referring now toFIG.1, a memory array100is shown, in accordance with an embodiment. Although the memory array100includes two rows and four columns, it should be appreciated that embodiments of the present invention may include the memory array100with any number of rows and columns. The memory array100includes a plurality of bit lines102, a plurality of word lines104, a plurality of select lines106. The bit lines102and select lines106run parallel to each other and are perpendicular to the word lines104. The plurality of word lines104intersect the plurality of bit lines102and the plurality of select lines106. The memory array100also includes a plurality of memory cells200. Each memory cell200includes a complimentary pair of transistors108a,108b, a first memory element110a, and a second memory element110b. Although eight memory cells200are shown, it should be appreciated that embodiments of the present invention may include any number of memory cells200.

As stated above, each memory cell200includes a complimentary pair of transistors108a,108b. The transistors108a,108bmay be bipolar junction transistors (BJTs) or junction field-effect transistors (JFETs). In a preferred embodiment, the transistors108a,108bare a complimentary pair of BJTs such that transistor108ais an NPN type and transistor108bis a PNP type. In an alternative embodiment, the transistors108a,108bare a complimentary pair of JFETs such that transistor108ais an n-channel JFET (nJFET) and transistor108bis a p-channel JFET (pJFET). In an embodiment, the transistors108a,108bare configured as complementary transmission gates. In an embodiment, the transistor108bin the memory cell200and the transistor108ain a memory cell adjacent to the memory cell200have a base or a gate terminal connected to the same respective word line104b. The transistor108ais an opposite channel type than the transistor108b.

The first and second memory elements110a,110bmay be any type of memory element such as, for example, RRAM, phase change memory, magnetic random access memory, or the like. The first memory element110ais connected between the bit line102aand a first shared collector emitter terminal (in BJT embodiments) or source drain terminal (in JFET embodiments) of the complimentary pair of transistors108a,108b. The second memory element110bis connected between the select line106aand a second shared collector emitter or source drain terminal of the complimentary pair of transistors108a,108b.

Referring now toFIG.2, an example of a programming, or writing, operation of the first memory element110awithin the memory array100is shown, in accordance with an embodiment. Embodiments of the present invention provide a method of programming the first memory element110awithout substantially disturbing the second memory element110bwithin the memory cell200. During the programming operation, resistance of the first memory element110ais decreased to create the programmed state of the memory element (which may be referred to as, for example, 1).

To program the first memory element110a, a first write voltage is applied to the bit line102bthat is connected to the first memory element110a. In an embodiment, the word line104cis connected to the base of the PNP transistor108b. In an alternative embodiment, the word line104cis connected to the gate of the pJFET transistor108b. The first write voltage is a positive supply voltage V+. A second write voltage is applied to the word line104c. The second write voltage is a negative supply voltage V−. The first write voltage is sufficiently larger than the second write voltage to forward bias the base or the gate junction of the transistor108b, allowing for the first memory element110ato be selected to be programmed. For example, if the voltage drop across the forward biased junction is approximately 0.7 volts (typical for a silicon p-n junction), the program voltage selectively applied across the first memory element110awill be approximately V+−V−−0.7 volts.

During the programming of the first memory element110aas described above, in order to minimize disturbing the second memory element110bas well as all other memory elements in the rest of memory cells, a first and second intermediate voltages may be applied to certain parts of the memory array100. In an embodiment, the first intermediate voltage is applied to the select line106bthat is connected to the second memory element110b. In an alternative embodiment, the select line106bis connected to a high impedance. The second intermediate voltage is applied to the remaining bit lines102, word lines104, and select lines106. For example, as illustrated inFIG.2, the select line106bmay either be connected to the first intermediate voltage Vmor to a float, which refers to the high impedance. The second intermediate voltage, V0, is applied to the bit line102a, the select line106a, and the word lines104a,104b,104d, and104e. As stated above, the first write voltage V+is applied to the bit line102band the second write voltage V−is applied to the word line104c. In this example, voltages are chosen as follows:
V+>Vm≥V0>V−
As such, the first write voltage is greater than the first intermediate voltage, the first intermediate voltage is greater than or equal to the second intermediate voltage, and the second intermediate voltage is greater than the second write voltage. As a result, the bias voltages across all memory elements except the first memory element110aare either negligible, or sufficiently smaller than V+−V−to not substantially alter their states. In one embodiment, Vmand V0are both 0 volts (i.e. ground potential). In another embodiment, V+=−V−. In yet another embodiment, the bit line102aand/or the select line106aare connected to a float (high impedance) instead of V0. Further variations and bias configurations may also be contemplated.

As stated above, during the programming operation of the first memory element110a, current flows through the first memory element110aand the emitter-base or source-gate junction of transistor108b. The transistor108bacts as a two-terminal device during this operation. By choosing the different write and intermediate voltages, described above, the first memory element110amay be programmed to a desired value without disturbing the second memory element110bwithin the memory cell200or any other memory elements within the other memory cells within the memory array100. As a result, the first memory element110aprogrammed independently.

Referring now toFIG.3, an example of an erase operation of the first memory element110awithin the memory array100is shown, in accordance with an embodiment. The erase operation is similar to the write operation with opposite voltage polarities transferred across the first memory element110a. The write operation of the first memory element110a, illustrated byFIG.2, may be performed via the PNP BJT transistor108b, whereas the erase operation of the first memory element110a, illustrated byFIG.3, may be performed via the NPN BJT transistor108a.

The erase operation independently erases the state of only the first memory element110a. All other memory elements, including the second memory element110bwithin the memory cell200, are substantially unaffected by this operation. To erase the state of the first memory element110a, its resistance is increased. This is accomplished by applying a first erase voltage to the word line104b. The word line104bis connected to the transistor108a. In an embodiment, if the transistor108ais an NPN BJT transistor then the word line104bis connected to the base of said NPN BJT transistor. In an alternative embodiment, if the transistor108bis an nJFET transistor, then the word line104bis connected to the gate of said nJFET transistor. The transistor108ais connected to the first memory element110a. The first erase voltage is a positive supply voltage V+. In addition to the first erase voltage, a second erase voltage is applied to the bit line102b. The bit line102bis connected to the top terminal of the first memory element110a. The second erase voltage is a negative supply voltage V−. The first erase voltage is sufficiently larger than the second erase voltage to forward bias the base or the gate junction of the transistor108b, allowing for the first memory element110ato be selected to be erased. For example, if the voltage drop across the forward biased junction is approximately 0.7 volts (typical for a silicon p-n junction), the erase voltage selectively applied across the first memory element110awill be approximately V+−V−−0.7 volts.

During the erasing of the first memory element110aas described above, in order to minimize disturbing the second memory element110bas well as all other memory elements in the rest of memory cells, a first and second intermediate voltages may be applied to certain parts of the memory array100. In an embodiment, the first intermediate voltage is applied to the select line106bthat is connected to the second memory element110b. In an alternative embodiment, the select line106bis connected to a high impedance. The second intermediate voltage is applied to the remaining bit lines102, word lines104, and select lines106. For example, as illustrated inFIG.3, the select line106bmay either be connected to the first intermediate voltage Vm−or to a float, which refers to the high impedance. The second intermediate voltage, V0, is applied to the bit line102a, the select line106a, and the word lines104a,104c,104d, and104e. As stated above, the first erase voltage V+is applied to the word line104band the second erase voltage V−is applied to the bit line102b. In this example, voltages are chosen as follows:
V+>V0≥Vm−>V−
As such, the first erase voltage is greater than the second intermediate voltage, the second intermediate voltage is greater than or equal to the first intermediate voltage, and the first intermediate voltage is greater than the second erase voltage. As a result, the bias voltages across all memory elements except the first memory element110aare either negligible, or sufficiently smaller than V+−V−to not substantially alter their states. In one embodiment, Vm−and V0are both 0 volts (i.e. ground potential). In another embodiment, V+=−V−. In yet another embodiment, the bit line102aand/or the select line106aare connected to a float (high impedance) instead of V0. Further variations and bias configurations may also be contemplated. It should be appreciated that the V+and V−used for the erasing of a state of a memory element may be, and typically are, different from the V+and V−used for the writing of a state of a memory element. Further, other voltages V0or Vm−may also be different.

Referring now toFIG.4, an example of a writing operation of the second memory element110bwithin the memory array100is shown, in accordance with an embodiment. The writing, or programming, of the second memory element110bis similar to the writing operation of the first memory element110a, described herein with reference toFIG.2. In the example illustrated inFIG.2the first memory element110ais written via the transistor108bwhereas, in the example, illustrated inFIG.4, the second memory element110bis written via the transistor108a.

In an embodiment, in order to write, or program, the second memory element110bwithout substantially disturbing the first memory element110awithin the memory cell200, or any other memory element within the memory array100, the first and second write voltages are applied to the word line104band the select line106b, respectively. As described herein with respect toFIG.2, the word line104bmay either be connected to the gate of an nJFET transistor108a, or to the base of an NPN BJT transistor108a. The transistor108ais connected to the second memory element110b. The select line106bis connected to the bottom terminal of the second memory element110b.

During the programming of the second memory element110b, the first and second intermediate voltages may be applied to certain bit lines102, word lines104, and select lines106. In an embodiment, the first intermediate voltage is applied to the bit line102b, which is connected to the top terminal of the first memory element110a. In an alternative embodiment, the bit line102bis connected to a high impedance. The second intermediate voltage is applied to the rest of the bit lines102, word lines104, and select lines106. For example, as illustrated inFIG.4, the bit line102bmay either be connected to the first intermediate voltage Vm−or to a float, which refers to the high impedance. The second intermediate voltage, V0, is applied to the bit line102a, the select line106a, and the word lines104a,104c,104d, and104e. As stated above, the first write voltage V+is applied to the word line104band the second write voltage V−is applied to the select line106b. In this example, voltages are chosen as follows:
V+>V0≥Vm−>V−
As such, the first write voltage is greater than the second intermediate voltage, the second intermediate voltage is greater than or equal to the first intermediate voltage, and the first intermediate voltage is greater than the second write voltage.

Having the first write voltage greater than the second write voltage allows for the second memory element110bto be selected for the writing operation. The first write voltage is sufficiently larger than the second write voltage to forward bias the base or the gate junction of the transistor108a. For example, the write voltage selectively applied across the second memory element110bmay be approximately V+−V−−0.7 volts. As such, the current flows through the base-emitter or gate-source junction of transistor108ato the second memory element110b. The transistor108aacts as a two terminal device during this operation. When the current flows through the second memory element110b, the second memory element110bmay be programmed to the desired state without substantially disturbing any other memory elements within the memory array100or the first memory element110awithin the memory cell200. As such, the second memory element110bmay be independently programmed.

Referring now toFIG.5, an example of an erase operation of the second memory element110bwithin the memory array100is shown, in accordance with an embodiment. The erasing of the second memory element110bis similar to the erasing operation of the first memory element110a, described herein with reference toFIG.3. In the example, illustrated inFIG.3, the first memory element110ais erased via the transistor108awhereas, in the example, illustrated inFIG.5, the second memory element110bis erased via the transistor108b. As stated above with respect toFIG.3, embodiments of the present invention provide a method of independently erasing the state of one memory element within the memory array100.

With continued reference toFIG.5, to erase the state of the second memory element110b, the first erase voltage Vis applied to the select line106bthat is connected to the bottom terminal of the second memory element110b, and the second erase voltage Vis applied to the word line104c. In an embodiment, the word line104cis connected to the base of the PNP BJT transistor108b. In an alternative embodiment, the word line104cis connected to the gate of the pJFET transistor108b. In both embodiments, the transistor108bis connected to the second memory element110b. The first erase voltage is sufficiently larger than the second erase voltage to forward bias the base or the gate junction of the transistor108b. For example, the erase voltage selectively applied across the second memory element110bmay be approximately V+−V−−0.7 volts. As such, the current flows from the second memory element110bthrough the emitter-base or source-gate junction of transistor108b. The transistor108bacts as a two terminal device during this operation. When the current flows through the second memory element110b, the second memory element110bmay be erased to the desired state without substantially disturbing any other memory elements within the memory array100or the first memory element110awithin the memory cell200. As such, the second memory element110bmay be independently erased.

In addition to the first and second erase voltages, the first and second intermediate voltages may also be applied to certain bit lines102, word lines104, and select lines106. In an embodiment, the first intermediate voltage is applied to the bit line102b, which is connected to the top terminal of the first memory element110a. In an alternative embodiment, the bit line102bis connected to a high impedance. The second intermediate voltage is applied to the bit line102a, word lines104a,104b,104d,104e, and select line106a.

In the example illustrated inFIG.5, voltages are chosen as follows:
V+>Vm≥V0>V−
As such, the first erase voltage is greater than the first intermediate voltage, the first intermediate voltage is greater than or equal to the second intermediate voltage, and the second intermediate voltage is greater than the second erase voltage.

Referring now toFIG.6, an example of a reading operation of the memory cell200within the memory array100is shown, in accordance with an embodiment. In order to read the memory cell200, two pairs of read voltages, with the right values in relation to each other, are applied to the memory array100. The first pair of voltages may include a first read voltage, Vread 1+, and a second read voltage, Vread 1−. The second pair of voltages may include a first read voltage, Vread 2+, and a second read voltage Vread 2−. The first read voltage Vread 1+of the first pair of read voltages is applied to the bit line102bthat is connected to the first memory element110a. The second read voltage Vread 1−of the first pair of voltages is applied to the select line106bthat is connected to the second memory element110b. Further, the first read voltage Vread 2+of the second pair of read voltages is applied to the word line104bthat is either connected to the base of the NPN BJT transistor108a, or to the gate of the nJFET transistor108a. The second read voltage Vread 2−of the second pair of read voltages is applied to the word line104cthat is either connected to the base of the PNP BJT transistor108b, or to the gate of the pJFET transistor108b. In addition to the two pairs of read voltages, an intermediate voltage is also applied to the rest of the bit lines102, word lines104, and select lines106. As such, bit line102a, word lines104a,104d,104e, and select line106aare connected to the intermediate voltage. In some embodiments, the intermediate voltage V0is the ground voltage (i.e. zero volts).

In the example illustrated inFIG.6the read voltages are chosen as follows:
Vread 1+>Vread 2+>V0>Vread 2−>Vread 1−

As such, the first read voltage of the first pair of read voltages is greater than the first read voltage of the second pair of read voltages, the first read voltage of the second pair of read voltages is greater than the intermediate voltage, the intermediate voltage is greater than the second read voltage of the second pair of read voltages, and the second read voltage of the second pair of read voltages is greater than the second read voltage of the first pair of read voltages. During the read operation, transistors108aand108bare biased in the linear (triode) region and the read current flowing through the memory elements110aand110band measured by the external circuitry is

Iread=(Vread⁢⁢1+-Vread⁢⁢1-)-Vo⁢nR1+R2
where V0nis the voltage drop across the collector-emitter or drain-source of the parallel-connected transistors108aand108b, and R1and R2are the resistance values (i.e. previously programmed states) of the memory elements110aand110b, respectively. As known, V0nis small in the triode region, particularly for a complementary pair of parallel-connected pass transistors; therefore,

Iread≈(Vread⁢⁢1+-Vread⁢⁢1-)R1+R2
which is inversely proportional to R1+R2, the sum of the resistance values of the memory elements110aand110b. As such, R1+R2can be extracted by the external circuitry. As will be explained below, R1+R2may be interpreted as the state of the memory cell. The read voltages are chosen appropriately to obtain the bias conditions described above. For example, Vread 1+−Vread 2−is chosen sufficiently larger than the turn on voltage of the PNP BJT108bor the threshold voltage of the pJFET108bto provide the required overdrive, whereas Vread 1+−Vread 2+and Vread 1+−V0are not large enough to overdrive the PNP BJTs or pJFETs in the rest of memory cells. Similarly, Vread 2+−Vread 1−is chosen sufficiently larger than the turn on voltage of the NPN BJT108bor the threshold voltage of the nJFET108bto provide the required overdrive, whereas Vread 2−−Vread 1−and V0−Vread 1−are not large enough to overdrive the NPN BJTs or nJFETs in the rest of memory cells.

In an embodiment, the first read voltage of the first and second pair of voltages is a positive voltage V+and the second read voltage of the first and second pair of voltages is a negative voltage V−having the same amplitude as the first read voltage. In another embodiment, the voltages are as follows:
V0=0 V (ground)
Vread 1+=Vread 1−
Vread 2+=Vread 2−

It should be appreciated that read voltages are typically smaller than the write and erase voltages as known from a memory element operation.

As described above, during the reading of the memory cell200, read voltages are applied with the use of the external circuitry such that the current flows through both the first memory element110aand the second memory element110b, and the read current sensed by the read circuitry is a measure of the combined states of the first and second memory elements110a,110b. As a result, the memory cell200can have a larger number of states when compared to a single memory element110, as will be further explained below.

In addition, as described above, during the reading of the memory cell200, both transistors108a,108bare turned on such that the transistors108a,108bform a complementary pass transistor pair, also known as a transmission gate. As known, this is advantageous since the transmission gate has a lower voltage drop and a higher dynamic range than a single pass transistor. Therefore, the read current measured by the external circuitry is substantially proportional to R1+R2, the sum of the resistance values of memory elements110aand110b, which may be interpreted as the state of the memory cell. In an embodiment, the first and second memory elements110a,110band the transistors108a,108bmay be configured as vertically stacked structures. For example, memory element110amay be stacked on top of transistors108aand108b, which are in turn stacked in top of memory element110b. In addition, transistors108aand108bmay be vertical transistors with stacked transistor regions. These stacked structures minimize the footprint of the memory cell200and achieve a high density of memory states per area.

Embodiments of the present invention provide the memory array110that includes a plurality of memory cells200. Each of the memory cells200includes two memory elements and two transistors. The memory cell200may be programed to a number of states larger than that of each of the memory elements. In some embodiments, a larger number of memory cell states may be possible if the first and second memory elements110a,110b, within the memory cell200, have different characteristics. For example, if the first and second memory elements110a,110bare identical, and have a first state RH(denoting a high resistance) and a second state RL(denoting a low resistance), the memory cell200may have three states, 2RH, 2RL, and RH+RL. Similarly, if the first memory element110aand the second memory element110bhave three states, RH, RL, and RM(denoting a medium resistance), there are six possible states 2RH, 2RL, 2RM, RH+RL, RH+RMand RL+RM. More generally, if the two memory elements within the memory cell200are identical, and if the first memory element110aand the second memory element110bhave N states, the memory cell200is programmable to

N⁡(N+1)2
states. In this example, it is assumed that memory elements110aand110bare symmetric or otherwise biased with the same voltage polarities in the memory cell so that they have the same states as each other. As known, a memory element may be asymmetric where the polarities of the write and erase voltages affect the states of the memory element.

The memory cell200may have up to N2states for N bits when the first memory element110ais different from the second memory element110b. For example, by using different material compositions, thicknesses, and/or structure, the first memory element110amay be different from the second memory element110b. For example, if the first memory element110ahas two states RH1and RL1, and the second memory element110bhas two states RH2and RL2, the memory cell200may have four possible states: RH1+RH2, RH1+RL2, RL1+RH2and RL1+RL2. Similarly, if the memory elements110aand110bare identical, but asymmetric and biased with opposite voltage polarities with respect to each other (e.g. if the bottom terminal of memory element110ais connected to BL102band its top terminal connected to transistors108aand108b), the first memory element110amay have two states RH1and RL1, and the second memory element110bmay have two states RH2and RL2, and the memory cell200may have four possible states: RH1+RH2, RH1+RL2, RL1+RH2and RL1+RL2. More generally, with N states instead of two, the memory cell200may have up to N2states in this manner.

Embodiments of the present invention described herein with reference toFIGS.1-6provide a new circuit structure. The new circuit structure is the cross-point memory array100that includes a plurality of memory cells200. The memory cells200may also be referred to as enhanced state dual memory cells. The memory cells200are 2T2R memory cells. As described herein above, each of the memory cells200includes two transistors108a,108band two memory elements110a,110b. This combination of transistors and memory elements increases the effective number of states per cell when compared to a conventional memory array.