STORAGE DEVICE AND STORAGE SYSTEM

Provided is a storage device including a non-volatile memory, a memory controller configured to communicate with a host device through a first channel and configured to control the non-volatile memory, and a sub controller configured to communicate with the host device through a second channel and configured to monitor an operation status of the memory controller. The sub controller is configured to perform operations including broadcasting state information of the storage device including the operation status to at least one external device through the second channel, and performing a recovery operation on the memory controller when recovery information is received from the at least one external device through the second channel.

CROSS-REFERENCE TO RELATED APPLICATION

BACKGROUND

The inventive concept relates to a storage device, and more particularly, to a storage device capable of recovering an abnormal state to a normal state.

Recently, storage devices including a non-volatile memory, such as a solid state drive (SSD), an embedded universal flash storage (UFS) memory device, and/or an embedded multi-media card (eMMC), have been widely used. A memory controller included in the storage device may control data write operations and read operations to and from the non-volatile memory, and may also manage the non-volatile memory. The memory controller may operate by executing firmware for controlling the non-volatile memory, and the firmware may include pieces of code, and data generated by the execution of the pieces of code may be stored in a memory.

The memory controller may enter an abnormal state, such as a deadlock, when an error occurs or an abnormal operation is detected during code execution. For example, when a register value used for an operation of pieces of code including firmware is out of a normal range, the memory controller may be in an abnormal state. If the operation state of the memory controller is abnormal, communication between the memory controller and a host device becomes impossible and accordingly, normal operations of the storage device including the memory controller and an electronic device including the storage device may become difficult. Therefore, it is necessary to develop a method for restoring the operation status of the memory controller to a normal state.

SUMMARY

The inventive concept provides a storage device capable of recovering a memory controller from an abnormal state to a normal state.

According to some embodiments of the inventive concept, there is provided a storage device including a non-volatile memory, a memory controller configured to communicate with a host device through a first channel and configured to control the non-volatile memory, and a sub controller configured to communicate with the host device through a second channel and configured to monitor an operation status of the memory controller The sub controller is configured to perform operations including broadcasting state information of the storage device including the operation status to at least one external device through the second channel, and performing a recovery operation on the memory controller when recovery information is received from the at least one external device through the second channel.

According to some embodiments of the inventive concept, there is provided a storage device including a first storage device including a first non-volatile memory, a first memory controller configured to communicate with a host device through a first channel, and a first sub controller configured to communicate with the host device through a second channel, and a second storage device including a second non-volatile memory, a second memory controller configured to communicate with the host device through the first channel, and a second sub controller configured to communicate with the host device through the second channel. The first sub controller is configured to broadcast state information of the first storage device including an operation status of the first memory controller through the second channel. The second sub controller is configured to generate recovery information of the first storage device based on previous state information of the first storage device when the operation status of the first memory controller is abnormal in response to the state information of the first storage device, and configured to transmit the recovery information that was generated to the first storage device through the second channel.

According to some embodiments of the inventive concept, there is provided a storage system including a host device, and a plurality of storage devices including a non-volatile memory, a memory controller configured to communicate with the host device through a first channel, and a sub controller configured to communicate with the host device through a second channel. A first sub controller included in a first storage device among the plurality of storage devices is configured to broadcast state information including an operation status that is an abnormal state through the second channel. A second sub controller included in a second storage device among the plurality of storage devices is configured to generate recovery information of the first storage device based on previous state information of the first storage device, and is configured to transmit the recovery information that was generated to the first storage device through the second channel.

DETAILED DESCRIPTION

FIG.1is a diagram illustrating a storage system according to some embodiments of the present disclosure.

Referring toFIG.1, a storage system10according to some embodiments of the present disclosure may include a first storage device110, a second storage device120, a third storage device130, and a host device200. The first storage device110, the second storage device120, and the third storage device130may be referred to as a plurality of storage devices.

In some embodiments of the present disclosure, the storage system10may be implemented as a personal computer (PC), a data server, a network-coupled storage, an Internet of Things (IoT) device, or a portable electronic device. The portable electronic device may be any one of a laptop computer, a mobile phone, a smartphone, a tablet PC, a personal digital assistant (PDA), an enterprise digital assistant (EDA), a digital still camera, a digital video camera, an audio device, a portable multimedia player (PMP), a personal navigation device (PND), an MP3 player, a handheld game console, an e-book, a wearable device, or the like.

Each of the plurality of storage devices110,120, and130may be an internal memory embedded in an electronic device. For example, each of the plurality of storage devices110,120, and130may be a solid state drive (SSD), an embedded universal flash storage (UFS) memory device, or an embedded multi-media card (eMMC). In some embodiments, each of the plurality of storage devices110,120, and130may be an external memory detachable from the electronic device. For example, the plurality of storage devices110,120, and130may be a UFS memory card, a Compact Flash (CF) card, a Secure Digital (SD), Micro Secure Digital (Micro-SD) card, a Mini Secure Digital (Mini-SD) card, an extreme digital (xD) card or a Memory Stick.

RegardingFIG.1, although some embodiments in which the storage system10includes the first storage device110, the second storage device120, and the third storage device130is illustrated, the present disclosure is not limited thereto. That is, unlike the embodiment ofFIG.1, the storage system10may include only the first storage device110and the second storage device120, and/or may further include an additional storage device, such as a fourth storage device.

The host device200may communicate with the plurality of storage devices110,120, and130through various interfaces. In some embodiments, the host device200may be implemented as an application processor (AP) or a system-on-a-chip (SoC).

The plurality of storage devices110,120, and130and the host device200may be connected to one another through a first channel300and a second channel400.

In some embodiments of the present disclosure, the first channel300may be an in-band channel. The first channel300may be used for data exchange between the plurality of storage devices110,120, and130and the host device200. The host device200may transmit a read request or a write request to the plurality of storage devices110,120, and130through the first channel300. In addition, the plurality of storage devices110,120, and130may transmit data corresponding to a read request or a response corresponding to a write request through the first channel300.

In some embodiments of the present disclosure, the second channel400may be an out-of-band channel. The second channel400may be used for a recovery operation of the plurality of storage devices110,120, and130. The plurality of storage devices110,120, and130may broadcast state information to be described later through the second channel400. Also, the plurality of storage devices110,120, and130may transmit recovery information to be described later through the second channel400.

The first channel300and the second channel400may be channels that enable communication between devices using at least one of various interface protocols, such as Serial Advanced Technology Attachment (SATA), Small Computer Small Interface (SCSI), Non-Volatile Memory Express (NVMe), Serial Attached SCSI (SAS), Compute eXpress Link (CXL), UFS, eMMC, or the like.

A more detailed configuration and operation of the plurality of storage devices110,120,130and the host device200, and the connection between the first channel300and the second channel400of the plurality of storage devices110,120, and130and the host device200may be described in more detail with reference toFIG.2.

FIG.2is a block diagram illustrating in more detail components of a host device and a storage device included in a storage system according to some embodiments of the present disclosure.

Referring toFIG.2, the storage system10according to some embodiments of the present disclosure may include a first storage device110, a second storage device120, and a host device200.

The first storage device110may include a first non-volatile memory111, a first memory controller112, and a first sub controller113. Also, the second storage device120may include a second non-volatile memory121, a second memory controller122, and a second sub controller123. At this time, althoughFIG.2shows some embodiments in which the storage system10includes the first storage device110and the second storage device120, the present disclosure is not limited thereto, and the storage system10may further include one or more storage devices each including a non-volatile memory, a memory controller, and/or a sub controller.

In the following description with reference toFIG.2, the first storage device110and the second storage device120may be collectively referred to as storage devices110and120, the first non-volatile memory111and the second non-volatile memory121may be collectively referred to as non-volatile memories111and121, the first memory controller112and the second memory controller122may be collectively referred to as memory controllers112and122, and the first sub controller113and the second sub controller123may be collectively referred to as sub controllers113and123.

The non-volatile memories111and121may include a memory cell array (MCA). The MCA may include memory blocks. The memory block may include a plurality of pages. Here, z and k may be positive integers, respectively, and may be variously changed according to embodiments. For example, a memory block may be a unit of erasing, and a page may be a unit of writing and reading.

In some embodiments, the MCA may include a plurality of planes, a plurality of dies, or a plurality of chips. In some embodiments, the non-volatile memories111and121may include a flash memory device, for example, a NAND flash memory device. However, the inventive concept is not limited thereto, and the non-volatile memories111and121may include resistive memory devices, such as resistive RAM (ReRAM), phase change RAM (PRAM), and/or magnetic RAM (MRAM).

The memory controllers112and122may be connected to the host device200through the first channel300. The memory controllers112and122may receive a read request for data stored in the non-volatile memories111and121from the host device200through the first channel300. Also, the memory controllers112and122may receive a write request to store data in the non-volatile memories111and121from the host device200through the first channel300.

The memory controllers112and122may control the non-volatile memories111and121. The memory controllers112and122may read data corresponding to the read request received from the host device200from the non-volatile memories111and121. Also, the memory controllers112and122may write data corresponding to the write request received from the host device200into the non-volatile memories111and121.

Also, the memory controllers112and122may perform various functions, such as address mapping, wear leveling, garbage collection, and the like. The address mapping operation is an operation of changing a logical address received from the host device200into a physical address used to actually store data in the non-volatile memories111and121. The wear leveling is an operation to prevent excessive deterioration of a certain block by allowing blocks in the non-volatile memories111and121to be uniformly used. The garbage collection is an operation to secure usable capacity in the non-volatile memories111and121by copying valid data of a block to a new block and then erasing the existing block.

The above-described operations of the memory controllers112and122may be implemented by firmware that includes of pieces of code. At this time, when the memory controllers112and122operate through the execution of pieces of code, the memory controllers112and122may be in a hang state in which an operation is unintentionally stopped due to an error in the code or may be in an abort state in which an abnormal operation in the memory controllers112and122is detected and the operation is intentionally stopped during code execution. The hang state and the abort state may collectively be referred to as a deadlock.

When the memory controllers112and122enter the hang state or the abort state, the memory controllers112and122may not communicate with the host device200. Therefore, the storage devices110and120may not perform normal operations. Therefore, when the memory controllers112and122are in a hang state or an abort state, an operation to solve the problem may need to be performed.

The sub controllers113and123may be connected to the host device200through the second channel400. Also, the sub controllers113and123may be connected to other sub controllers113and123through the second channel400. In this case, the sub controllers113and123communicate through the second channel400, and when the memory controllers112and122are in an abnormal state, a recovery operation may be performed.

In some embodiments of the present disclosure, the sub controllers113and123may be micro controller units (MCUs), and may be formed of chips separate from the memory controllers112and122.

The sub controllers113and123may monitor respective operation statuses of the memory controllers112and122.

The sub controllers113and123may monitor whether the memory controllers112and122are in a hang state or an abort state. When the operation status of the memory controllers112and122is a hang state or an abort state, the sub controllers113and123may determine the operation status of the memory controllers112and122to be an abnormal state. Also, when the operation status of the memory controllers112and122is not a hang state or an abort state, the sub controllers113and123may determine the operation status of the memory controllers112and122to be a normal state.

The sub controllers113and123may monitor the operation status of the memory controllers112and122at preset reference cycle intervals. The reference cycle is a cycle for monitoring the operation status of the memory controllers112and122, and may be set considering the frequency of performing operations of the memory controllers112and122.

The sub controllers113and123may broadcast state information of the storage devices110and120including the operation status through the second channel400. Accordingly, at least one external device connected to the second channel400may receive state information of the storage devices110and120. In this case, the at least one external device may be any one of the other storage devices110and120that do not broadcast state information among the storage devices110and120connected to the second channel400. For example, when the first storage device110broadcasts state information, the second storage device120may be at least one external device.

The state information may include at least one of identification information, an operation status, a register value, and time information.

The identification information may be information that allows the storage devices110and120that have broadcast state information through the second channel400to be distinguished from other storage devices110and120. The storage devices110and120may determine which storage devices110and120state information is the state information broadcast through the second channel400based on the identification information included in the state information.

The register value may be a value stored by a register included in the memory controllers112and122. In some embodiments of the present disclosure, the register value may include at least one of the number of times garbage collection check logic is performed, a loop count of certain logic (e.g., a while statement or an if statement that is encountered), and the like.

When the register value is out of the normal range, the memory controllers112and122may be in a hang state or an abort state. When the operation status of the memory controllers112and122is in a normal state, the register value is stored in the other storage devices110and120and may be used to generate recovery information later.

The time information may be information indicating a time when the state information is generated. For example, the time information may be a time stamp. The storage devices110and120may distinguish the most recently stored state information from among a plurality of pre-stored state information, based on the time information.

The sub controllers113and123may broadcast state information through the second channel400at a reference cycle interval. For example, the cycle at which the sub controllers113and123broadcast state information may be the same as the cycle at which the sub controllers113and123monitor the operation status of the memory controllers112and122, but the present disclosure is not limited thereto. Accordingly, the sub controllers113and123may broadcast all of the generated state information through the second channel400.

Also, when the storage devices110and120are in an idle state, the sub controllers113and123may broadcast state information of the storage devices110and120through the second channel400. In this case, the sub controllers113and123may broadcast the initial state information together with main state information of the storage devices110and120through the second channel400.

The sub controllers113and123may receive state information of other storage devices110and120through the second channel400. For example, the first sub controller113may broadcast state information of the first storage device110through the second channel400and receive state information of the second storage device120.

The sub controllers113and123may store state information of other storage devices110and120received through the second channel400. In addition, the sub controllers113and123may use the stored state information of the other storage devices110and120when generating recovery information of the other storage devices110and120.

If the received operation status of the memory controllers112and122of the other storage devices110and120is abnormal, the sub controllers113and123may generate recovery information of the other storage devices110and120based on previous state information of the other storage devices110and120. Previous state information is pre-stored state information of other storage devices110and120, and may be state information of the other storage devices110and120received when the operation status of the memory controllers112and122of the other storage devices110and120is in a normal state.

When receiving state information of other storage devices110and120through the second channel400, the sub controllers113and123may check the operation status of the memory controllers112and122of the other storage devices110and120included in the state information. In addition, when it is confirmed that the operation status of the memory controllers112and122of the other storage devices110and120is abnormal, the sub controllers113and123may generate recovery information of the other storage devices110and120based on previously stored previous state information of the other storage devices110and120.

The recovery information may include at least one of identification information of a transmitting device, identification information of a receiving target device, a register value, and time information.

The identification information of the transmitting device is information that distinguishes the storage devices110and120that have transmitted the recovery information through the second channel400from other storage devices110and120.

The identification information of the receiving target device is information that allows the storage devices110and120to receive recovery information through the second channel400to be distinguished from other storage devices110and120. For example, the first sub controller113may determine whether the received recovery information is information to be used for recovery of the first memory controller112connected to the first sub controller113based on the identification information of the receiving target device included in the recovery information.

The register value may be a register value to be used for recovery of the memory controllers112and122included in the receiving target device. The register value may be used to recover the memory controllers112and122in an abnormal state as being input as the register value of the memory controllers112and122of the receiving target device by the sub controllers113and123of the receiving target device.

In this case, the sub controllers113and123may set a register value included in state information having the most recent time information among previously stored previous state information as a register value of the recovery information. Accordingly, when the memory controllers112and122in the abnormal state are in the normal state, the most recently used register value may be transmitted as recovery information.

The time information may be information indicating a time at which the recovery information is generated.

The sub controllers113and123may transmit the generated recovery information of the other storage devices110and120to the other storage devices110and120through the second channel400. Accordingly, when the other storage devices110and120are in an abnormal state, they may receive recovery information.

The sub controllers113and123may receive recovery information from other storage devices110and120through the second channel400. The sub controllers113and123may perform a recovery operation on the memory controllers112and122by using the received recovery information. The sub controllers113and123may perform a recovery operation on the memory controllers112and122by inputting a register value included in the recovery information to the memory controllers112and122. Since the memory controllers112and122may be in a hang state and/or an abort state when the register value is out of the normal range, the sub controllers113and123may allow the register values of the memory controllers112and122to have the most recent values they had when the memory controllers112and122were in a normal state by inputting the register value included in the recovery information as the register value of the memory controllers112and122.

As such, in the storage devices110and120of the present disclosure, the sub controllers113and123broadcast state information including the operation status of the memory controllers112and122, receive recovery information from the other storage devices110and120, perform a recovery operation on the memory controllers112and122, and restore the storage devices110and120that are in an abnormal state so that they may quickly operate normally.

The host device200may include a central processing unit (CPU)210and a baseboard management controller (BMC)220.

The CPU210may be connected to the memory controllers112and122of the storage devices110and120through the first channel300. The CPU210may transmit a read request or a write request to the storage devices110and120through the first channel300.

The BMC220may be connected to the sub controllers113and123of the storage devices110and120through the second channel400. The BMC220may receive state information broadcast by the sub controllers113and123through the second channel400.

FIG.3is a diagram illustrating movement of state information between storage devices according to some embodiments of the present disclosure.

Referring toFIG.3, the storage system10according to some embodiments of the present disclosure may include a first storage device110, a second storage device120, and a third storage device130. In addition, the first storage device110, the second storage device120, and the third storage device130may be connected to each other through the first channel300and the second channel400.

The first memory controller112, the second memory controller122, and the third memory controller132may communicate with each other through the first channel300. In addition, the first sub controller113, the second sub controller123, and the third sub controller133may communicate with each other through the second channel400.

In this case, the state information generated by any one of the first sub controller113, the second sub controller123, and the third sub controller133may be broadcast through the second channel400. In embodiments ofFIG.3, the state information generated by the first sub controller113may be broadcast to the second sub controller123and the third sub controller133through the second channel400.

FIG.4is a diagram illustrating an example of state information broadcast by a storage device according to some embodiments of the present disclosure.

Referring toFIG.4, state information may include identification information IDENTIFICATION FROM, an operation status OPERATION STATUS, a register value REGISTER VALUE, and time information TIME.

In embodiments ofFIG.4, the identification information IDENTIFICATION FROM may be FIRST, and may indicate that the storage device broadcasting the state information is the first storage device110. In some embodiments, the identification information IDENTIFICATION FROM may be SECOND, THIRD, or the like, and refer to the second storage device120, the third storage device130, etc.

In embodiments ofFIG.4, the operation status OPERATION STATUS may be ABNORMAL, and may indicate that the memory controller of the storage device broadcasting the state information is in an abnormal state. In some embodiments, the operation status OPERATION STATUS may be NORMAL, and may indicate that the memory controller of the storage device broadcasting the state information is in a normal state.

In embodiments ofFIG.4, the register value REGISTER VALUE may have a certain value SOME VALUE, which may be a register value stored in the memory controller of the storage device broadcasting state information.

In embodiments ofFIG.4, the time information TIME may be 202201230123, and may indicate a time when the storage device generates state information.

FIG.5is a diagram illustrating movement of recovery information between storage devices according to some embodiments of the present disclosure.

Referring toFIG.5, a diagram showing the movement of recovery information to the storage system10as shown inFIG.3may be confirmed.

As shown inFIG.3, when the first sub controller113broadcasts state information through the second channel400, the second sub controller123and the third sub controller133may determine whether the operation status included in the received state information is an abnormal state. In addition, if the operation status included in the received state information is abnormal, the second sub controller123and the third sub controller133may generate recovery information of the first storage device110based on previously stored previous state information of the first storage device110.

As the operation status included in the state information broadcast by the first sub controller113is in an abnormal state, both the second sub controller123and the third sub controller133may generate recovery information. At this time, in some embodiments of the present disclosure, among the second sub controller123and the third sub controller133, the sub controller that first completes generation of the recovery information may transmit the recovery information of the first storage device110through the second channel400.

In general, the recovery information may be generated by any of the second sub controller123and the third sub controller133. However, if the operation status included in the state information first broadcast by the first sub controller113is in an abnormal state, since the second sub controller123and the third sub controller133do not have pre-stored previous state information, they may not generate recovery information. In this case, among the second storage device120including the second sub controller123and the third storage device130including the third sub controller133, recovery information may be generated using a register value of a memory controller included in a storage device disposed in the same redundant array of inexpensive disks (RAID) as the first storage device110. That is, only when the operation status included in the state information first broadcast by the first sub controller113is in an abnormal state, the recovery information may be generated by the sub controller of the storage device disposed in the same RAID as the first storage device110, not by any sub controller.

FIG.5shows some embodiments in which the second sub controller123generates recovery information and transmits the generated recovery information to the first sub controller113through the second channel400. In this case, the second sub controller123for transmitting the recovery information may be set as a master device among devices connected to the second channel400. Accordingly, the second sub controller123may transmit the recovery information to the first sub controller113with priority over other sub controllers broadcasting state information.

By setting the sub controller that transmits the recovery information in this way as a master device between devices connected to the second channel400, it is possible to recover the memory controller in an abnormal state more quickly, and it is possible to prevent a collision between information transmitted through the second channel400.

FIG.6is a diagram illustrating an example of recovery information received by a storage device according to some embodiments of the present disclosure.

Referring toFIG.6, recovery information may include identification information IDENTIFICATION FROM of the transmitting device, identification information IDENTIFICATION TO of the receiving target device, a register value REGISTER VALUE, and time information TIME.

In embodiments ofFIG.6, the identification information IDENTIFICATION FROM of the transmitting device may be SECOND, and may indicate that the storage device transmitting the recovery information is the second storage device120. In some embodiments, the identification information IDENTIFICATION FROM of the transmitting device may be FIRST, THIRD, or the like.

In embodiments ofFIG.6, the identification information IDENTIFICATION TO of the receiving target device may be FIRST, and may indicate that the storage device that is supposed to receive the recovery information is the first storage device110. In some embodiments, the identification information IDENTIFICATION FROM of the transmitting device may be SECOND, THIRD, or the like.

In embodiments ofFIG.6, the register value REGISTER VALUE may have a certain value SOME VALUE, which may be a register value to be input to the memory controller of the storage device that has received the recovery information.

In embodiments ofFIG.6, the time information TIME may be 202201230124 and may indicate a time when the storage device generates the recovery information.

FIG.7is a flowchart illustrating a method of operating a storage device, according to some embodiments of the present disclosure. Hereinafter, for convenience of description, some embodiments in which an operation as in the flowchart ofFIG.7is performed in the first storage device110will be mainly described.

Referring toFIG.7, in operation S710, the first sub controller113may monitor the operation status of the first memory controller112. The first sub controller113may monitor the operation status of the first memory controller112at a preset reference cycle interval. The first sub controller113may monitor the operation status of the first memory controller112and generate state information of the first storage device110including the operation status of the first memory controller112.

In operation S720, the first sub controller113may broadcast state information of the first storage device110including the operation status of the first memory controller112through the second channel400. The first sub controller113may broadcast state information of the first storage device110at a preset reference cycle interval. Accordingly, the sub controller (e.g., the second sub controller123of the second storage device120or the third sub controller133of the third storage device130) of another storage device connected to the second channel400may receive state information. The sub controller of the other storage device that has received the state information may generate recovery information when the operation status included in the state information is in an abnormal state. In addition, the sub controller of the other storage device may transmit the generated recovery information to the first sub controller113of the first storage device110through the second channel400.

In operation S730, the first sub controller113may receive recovery information. At this time, the first sub controller113may monitor that the operation status of the memory controller is abnormal in operation S710, and receive recovery information when the device broadcasts the state information in which the operation status is abnormal in operation S720through the second channel400.

In operation S740, the first sub controller113may perform a recovery operation on the first memory controller112using the received recovery information. The first sub controller113may perform a recovery operation on the first memory controller112by inputting a register value included in the recovery information to the first memory controller112.

FIG.8is a flowchart illustrating an operation when a storage device receives state information of another storage device according to some embodiments of the present disclosure. Hereinafter, for convenience of description, some embodiments in which an operation as in the flowchart ofFIG.8is performed in the second storage device120will be mainly described.

Referring toFIG.8, in operation S810, the second sub controller123may receive state information of another storage device (e.g., the first storage device110or the third storage device130). The second sub controller123may receive state information broadcast by another storage device through the second channel400.

In operation S820, the second sub controller123may determine whether the operation status in the received state information is a normal state.

If it is determined that the operation status in the received state information is a normal state, in operation S830, the second sub controller123may store the received state information. The stored state information becomes previous state information and may be used to generate recovery information later.

Conversely, if it is determined that the operation status in the received state information is in an abnormal state, in operation S840, the second sub controller123may generate recovery information based on previous state information of another storage device. In addition, in operation S850, the second sub controller123may transmit recovery information to another storage device through the second channel400.

FIG.9is a flowchart illustrating an operation after a storage device performs a recovery operation according to some embodiments of the present disclosure. Hereinafter, for convenience of description, some embodiments in which an operation as in the flowchart ofFIG.9is performed in the first storage device110will be mainly described.

Referring toFIG.9, in operation S910, the first memory controller112may determine whether the operation status is in a normal state by performing a verification operation after the recovery operation by the first sub controller113is completed. The first memory controller112may execute verification code to perform a verification operation. In this case, if an error does not occur after performing the verification code, the first memory controller112may determine the operation status to be a normal state. In addition, if an error occurs after performing the verification code, the first memory controller112may determine the operation status to be an abnormal state.

If it is determined that the operation status is in a normal state, in operation S920, the first memory controller112may be reconnected with the host device200through the first channel300. Then, in operation S930, the first memory controller112may perform a normal operation such as exchanging data with the host device200.

Conversely, if it is determined that the operation status is an abnormal state, in operation S940, the first memory controller112may perform a hardware reset operation or a software reset operation.

In this case, when the abnormal state of the first memory controller112is not caused by an error in a register value, but by a hardware failure or an error in firmware, in the verification operation performed after the recovery operation, the operation status of the first memory controller112may be determined to be an abnormal state. Accordingly, the first memory controller112may restore the first memory controller112to a normal state by performing a hardware reset operation or a software reset operation.

The first memory controller112may initialize the firmware by performing a software reset operation when the normal state is not restored through the input of the register value by the first sub controller113. In some embodiments of the present disclosure, the software reset operation may be performed by inputting a predefined register value to the first memory controller112. When the operation status of the first memory controller112is not restored to a normal state through a software reset operation, the first memory controller112may perform a hardware reset operation.

In some embodiments of the present disclosure, the hardware reset operation may be performed using a dedicated pin connected between the host device200and the first storage device110. That is, the hardware reset operation may be performed using a dedicated pin configured separately from an existing reset pin, a data transmission pin, and the like connected between the host device200and the first storage device110.

FIG.10is a flowchart illustrating a method of operating a storage system, according to some embodiments of the present disclosure.

Referring toFIG.10, in operation S1010, the first sub controller113may monitor the operation status of the first memory controller112.

In operation S1020, the first sub controller113may generate state information of the first storage device110.

In operation S1030, the first sub controller113may broadcast state information of the first storage device110through the second channel400. Accordingly, the second sub controller123and the third sub controller133may receive state information of the first storage device110.

In operation S1040, the third sub controller133may determine whether the operation status included in the state information of the first storage device110is in an abnormal state.

If it is determined that the operation status included in the state information of the first storage device110is in an abnormal state, in operation S1050, the third sub controller133may generate recovery information of the first storage device110.

In operation S1060, the third sub controller133may transmit recovery information of the first storage device110to the first sub controller113. Accordingly, the first sub controller113may receive recovery information of the first storage device110.

In operation S1070, the first sub controller113may perform a recovery operation of the first memory controller112based on the received recovery information.

FIG.11is a block diagram illustrating an electronic device according to some embodiments of the present disclosure.

Referring toFIG.11, an electronic device1000may include a processor1100, a memory device1200, a storage device1300, a modem1400, an input/output (I/O) device1500, and a power supply1600.

The storage device1300may include a plurality of storage devices, and each of the plurality of storage devices may include a non-volatile memory, a memory controller, and a sub controller. The storage device1300and the processor1100, the memory device1200, the modem1400, the I/O device1500, and the power supply1600may be connected through the channel1700, and the channel1700may include a first channel used for data exchange and a second channel used for a recovery operation of the storage device1300. Although not clearly illustrated inFIG.11, a plurality of storage devices may be connected through the first channel and the second channel.

In some embodiments of the present disclosure, each of the plurality of storage devices broadcasts state information including the operation status of the memory controller through the sub controller, and receives recovery information from another storage device and performs a recovery operation on the memory controller, so that a storage device that is in an abnormal state may be quickly restored to thereby operate normally.