Supply voltage independent Schmitt trigger inverter

A Schmitt trigger inverter circuit can include a first inverter. The first inverter can include a first pull-up device, a first pull-down device and a second pull-down device. The first inverter can receive an input signal. The Schmitt trigger inverter circuit can include a second inverter coupled in series with the first inverter and including an output that generates an output signal. The Schmitt trigger inverter circuit further can include a switch coupled to the output of the second inverter circuit and that is selectively enabled by the output signal. The switch can couple a predetermined reference voltage to a source terminal of the first pull-down device when in an enabled state. Coupling the predetermined reference voltage to the source terminal of the first pull-down device can alter a threshold voltage of the Schmitt trigger inverter circuit.

FIELD OF THE INVENTION

The embodiments disclosed within this specification relate to semiconductor integrated circuits (ICs). More particularly, the embodiments relate to a Schmitt trigger inverter circuit for an IC.

BACKGROUND

A Schmitt trigger inverter refers to a type of inverter circuit that alters the threshold voltage at which an output signal of the Schmitt trigger inverter changes state dependent upon whether the input signal to the Schmitt trigger inverter is increasing or decreasing. When the input signal is increasing and higher than a first selected threshold voltage, the output is a logic low. When the input signal is decreasing and below a second selected threshold voltage, the output is a logic high. When the input signal resides between the two selected threshold voltages, the output signal retains its state. The Schmitt trigger inverter retains its state until the input signal exceeds the appropriate threshold voltage to “trigger” a state change. The Schmitt trigger inverter is said to have memory due to the existence of the two distinct threshold voltage levels, with each threshold voltage being dependent upon the slope of the input signal. The presence of memory implies the presence of hysteresis within the Schmitt trigger inverter. Hysteresis generally refers to the dependence of the current state of a system on the history of the system.

Schmitt trigger inverter architectures are typically used to improve the noise and/or the distortion immunity of an inverter circuit. Conventional inverters switch as their input signal crosses a single threshold voltage regardless of the previous state of the inverter. When the input signal to a conventional inverter resides close to the singular threshold voltage, any noise appearing within the input signal can cause the voltage of the input signal to transition back and forth across the threshold voltage. For example, as large blocks of digital circuits within an IC are switched, a noise signal associated with the switching can propagate within the IC and appear at the input to, or within, a supply voltage powering the inverter. The noise within the input signal can result in unintended changes in the output state of the inverter.

The presence of hysteresis within the Schmitt trigger inverter can prevent the output state of the Schmitt trigger inverter from being changed by noise so long as the noise resides within the voltage range between the two threshold voltages selected for the Schmitt trigger inverter. In this manner, noise is prevented from altering the output state of the Schmitt trigger inverter or, in a worst case, causing the Schmitt trigger inverter to oscillate. As such, Schmitt trigger inverters are frequently used within ICs generating, or operating within, high noise environments.

SUMMARY

The embodiments disclosed within this specification relate to integrated circuits (ICs) and, more particularly, to a Schmitt trigger inverter circuit (Schmitt trigger). In one embodiment, a Schmitt trigger can include a first inverter including a first pull-up device, a first pull-down device, and a second pull-down device. The first inverter can be configured to receive an input signal. The Schmitt trigger also can include a second inverter coupled in series with the first inverter and include an output configured to generate an output signal. The Schmitt trigger can include a switch coupled to the output of the second inverter. The switch can be selectively enabled responsive to the output signal. The switch can be configured to couple a predetermined reference voltage to a source terminal of the first pull-down device when in an enabled state. Coupling the predetermined reference voltage can alter a threshold voltage of the Schmitt trigger.

In one aspect, a voltage range of the output signal of the second inverter can vary between a ground potential and the predetermined reference voltage. The predetermined reference voltage can be independent of a supply voltage powering the Schmitt trigger.

The switch can include a P-type field effect transistor (PFET) device. The PFET device can include a gate terminal coupled to the output of the second inverter, a source terminal coupled to the predetermined reference voltage, and a drain terminal coupled to the source terminal of the first pull-down device.

The first inverter can include a second pull-up device including a source terminal coupled to a drain terminal of the first pull-up device and a gate terminal coupled to a first bias voltage. The first inverter also can include a third pull-down device including a source terminal coupled to a drain terminal of the first pull-down device, a drain terminal coupled to a drain terminal of the second pull-up device, and a gate terminal coupled to a second bias voltage.

In another aspect, the first pull-up device and the second pull-up device each can include a PFET device. The first bias voltage can be set to a selected voltage that limits a voltage across each of the first pull-up device and the second pull-up device to not exceed a voltage tolerance associated with each respective device during operation of the Schmitt trigger.

The first pull-down device, the second pull-down device, and the third pull-down device each can include an N-type field effect transistor (NFET) device. The second bias voltage can be set to a selected voltage that limits a voltage across each of the first pull-down device, the second pull-down device, and the third pull-down device to not exceed a voltage tolerance associated with each respective device during operation of the Schmitt trigger.

The second inverter can include a second pull-up device including a drain terminal, a source terminal coupled to a supply voltage powering the Schmitt trigger, and a gate terminal coupled to the output of the first inverter. The second inverter can include a third pull-up device including a drain terminal, a source terminal coupled to the drain terminal of the second pull-up device, and a gate terminal coupled to a first bias voltage. The second inverter also can include a third pull-down device including a source terminal, a drain terminal coupled to the drain terminal of the third pull-up device, and a gate terminal coupled to the predetermined reference voltage. The second inverter further can include a fourth pull-down device including a drain terminal coupled to the source terminal of the third pull-down device, a source terminal coupled to a ground potential, and a gate terminal coupled to the output of the first inverter. The output of the second inverter can be a node coupling the source terminal of the third pull-down device and the drain terminal of the fourth pull-down device. In one aspect, the second pull-up device and the third pull-up device each can include a PFET device. Further, the third pull-down device and the fourth pull-down device each can include an NFET device.

Another embodiment can include a Schmitt trigger disposed in a complementary metal oxide semiconductor (CMOS) IC. The Schmitt trigger can include a first inverter including a first PFET device, a first NFET device, and a second NFET device, wherein the first inverter is configured to receive an input signal. A second inverter can be included that is coupled in series with an output of the first inverter. The second inverter can include an output configured to generate an output signal. The Schmitt trigger can include a PFET switch including a gate terminal coupled to an output of the second inverter, a source terminal coupled to a predetermined reference voltage, and a drain terminal coupled to the source terminal of the first NFET device. The PFET switch can be configured to couple the predetermine voltage to the source terminal of the first NFET device when in an enabled state. The predetermined reference voltage can be independent of a supply voltage powering the Schmitt trigger.

In one aspect, a voltage range of the output signal of the second inverter can vary between a ground potential and the predetermined reference voltage.

The first inverter can include a second PFET device including a source terminal coupled to a drain terminal of the first PFET device and a gate terminal coupled to a first bias voltage. The first inverter also can include a third NFET device including a source terminal coupled to a drain terminal of the first NFET device, a drain terminal coupled to a drain terminal of the second PFET device, and a gate terminal coupled to a second bias voltage.

The first bias voltage and the second bias voltage each can be selected, so that, for each PFET device and NFET device used to implement the Schmitt trigger, voltage across each PFET device and NFET device does not exceed a voltage tolerance associated with each respective device during operation of the Schmitt trigger.

The second inverter can include a second PFET device including a drain terminal, a source terminal coupled to the supply voltage, and a gate terminal coupled to the output of the first inverter and a third PFET device including a drain terminal, a source terminal coupled to the drain terminal of the second PFET device, and a gate terminal coupled to a bias voltage. The second inverter can include a third NFET device including a source terminal, a drain terminal coupled to the drain terminal of the third PFET device, and a gate terminal coupled to the predetermined reference voltage. A fourth NFET device can be included that has a drain terminal coupled to the source terminal third NFET device, a source terminal coupled to a ground potential, and a gate terminal coupled to the output of the first inverter. The output of the second inverter can be a node coupling the source terminal of the third NFET device and the drain terminal of the fourth NFET device.

Another embodiment can include a Schmitt trigger. The Schmitt trigger can include a first inverter including a first pull-up device, a first pull-down device, and a second pull-down device, wherein the first inverter is configured to receive an input signal. A second inverter can be included that is coupled in series with the first inverter. The second inverter can include an output configured to generate an output signal. A voltage range of the output signal can vary between a ground potential and a predetermined reference voltage. The predetermined reference voltage can be independent of a supply voltage powering the Schmitt trigger. The Schmitt trigger also can include a switch coupled to the output of the second inverter. The switch can be selectively enabled responsive to the output signal. The switch can be configured to couple a predetermined reference voltage to a source terminal of the first pull-down device when in an enabled state. Coupling the predetermined reference voltage can alter a threshold voltage of the Schmitt trigger.

The first inverter can include a second pull-up device including a source terminal coupled to a drain terminal of the first pull-up device and a gate terminal coupled to a first bias voltage. The first inverter also can include a third pull-down device including a source terminal coupled to a drain terminal of the first pull-down device, a drain terminal coupled to a drain terminal of the second pull-up device, and a gate terminal coupled to a second bias voltage.

The switch can include a PFET device. The PFET device can include a gate terminal coupled to the output of the second inverter, a source terminal coupled to the predetermined reference voltage, and a drain terminal coupled to the source terminal of the first pull-down device.

The second inverter can include a second pull-up device including a drain terminal, a source terminal coupled to a supply voltage powering the Schmitt trigger, and a gate terminal coupled to the output of the first inverter. A third pull-up device can be included that has a drain terminal, a source terminal coupled to the drain terminal of the second pull-up device, and a gate terminal coupled to a first bias voltage. The second inverter can include a third pull-down device and a fourth pull-down device. The third pull-down device can include a source terminal, a drain terminal coupled to the drain terminal of the third pull-up device, and a gate terminal coupled to the predetermined reference voltage. The fourth pull-down device can include a drain terminal coupled to the source terminal of the third pull-down device, a source terminal coupled to the ground potential, and a gate terminal coupled to the output of the first inverter. The output of the second inverter can be a node coupling the source terminal of the third pull-down device and the drain terminal of the fourth pull-down device.

DETAILED DESCRIPTION

The embodiments disclosed within this specification relate to integrated circuits (ICs) and, more particularly, to a Schmitt trigger type of inverter circuit that can be used within an IC. In accordance with one or more embodiments disclosed herein, a Schmitt trigger inverter circuit is provided that can function independently of a supply voltage. The Schmitt trigger inverter circuit can be implemented within a complementary metal oxide semiconductor (CMOS) type of IC. The Schmitt trigger inverter circuit can include a first inverter that receives an input signal and a second inverter coupled in series with the first inverter. An output signal from the second inverter can enable a switch that generates hysteresis within the Schmitt trigger inverter circuit. Enabling the switch can couple a predetermined reference voltage to a node within the first inverter.

Hysteresis can be generated within the Schmitt trigger inverter circuit by closing or opening the switch, thereby coupling or uncoupling the predetermined reference voltage from the node within the first inverter. The application of the predetermined reference voltage shifts a threshold voltage at which the Schmitt trigger inverter circuit changes state. The predetermined reference voltage coupled to the first inverter and the voltage range of the output signal from the second inverter used to enable the switch can be independent of the supply voltage. As a result, the amount of hysteresis generated within the Schmitt trigger inverter circuit can remain constant despite variations that can occur in the supply voltage.

FIG. 1is a first schematic diagram illustrating a Schmitt trigger inverter circuit (Schmitt trigger)100. Schmitt trigger100can provide a predetermined quantity of hysteresis that is independent of variations in a supply voltage powering Schmitt trigger100. Schmitt trigger100can include an inverter105, an inverter110, and a switch115.

Inverter105can include a pull-up device120and pull-down devices125and130. Coupled together in series between supply voltage VCC135and ground denoted as GND140, pull-up device120, pull-down device125, and pull-down device130, form a first inverter of Schmitt trigger100. The gate terminal of pull-up device120can receive signal Vin145. When enabled by signal Vin145, pull-up device120can couple VCC135to pull-down device125. The gate terminal of each of pull-down devices125and130can receive signal Vin145. When enabled by signal Vin145, pull-down device125can couple pull-up device120to pull-down device130. When enabled by signal Vin145, pull-down device130can couple pull-down device125to GND140. Inverter105can generate output signal Vout1150.

A “pull-up” or “pull-down” device can refer to a transistor that can functionally operate as a switch and, when enabled, couple a first node of a circuit at a predetermined reference voltage to a second node of the circuit. Depending upon the relative voltage differential between the first node and the second node, the transistor can be classified as a pull-up or a pull-down type of device. A pull-up device can source current to pull-up the voltage at the second node. A pull-down device can sink current to pull-down the voltage at the second node.

The term “couple” can refer to the formation of an electrical connection between two or more nodes that allows the exchange of an electrical property, such as a voltage, a current, or a signal, between the nodes. For example, the output of a first inverter can be coupled to the input of a second inverter allowing an output signal of the first inverter to be received as an input signal by the second inverter. The closing of a switch between two nodes can be said to “couple” the two nodes together, thereby allowing current to flow between the two nodes. In another example, the enabling of a CMOS device can create a current path from the source terminal of the CMOS device through the body of the CMOS device to the drain terminal of the CMOS device, thereby coupling a node at the source terminal to a node at the drain terminal. Thus, a node at a drain terminal of a CMOS device and a node at a source terminal of the CMOS device can be said to be coupled when the CMOS device is enabled, and decoupled when the CMOS device is disabled.

Throughout this specifications pull-up devices are depicted as being P-type field effect transistors (PFETs) and pull-down devices are depicted as being N-type field effect transistors (NFETs). Although illustrated in this manner, pull-up devices and pull-down devices can be implemented with either complementary CMOS device. As such, the use of PFETs for pull-up devices and NFETs for pull-down devices, as described within this specification, is for descriptive purposes only and is not intended to limit the embodiments disclosed within this specification.

Inverter110can include an input coupled to the output of inverter105. The output of inverter105is illustrated withinFIG. 1as node170. The input of inverter110can receive signal Vout1150. The output of inverter110is coupled to a gate terminal of switch115. A source terminal of switch115is coupled to Vaux160. Vaux160can be a predetermined reference voltage less than, and independent of, VCC135. A drain terminal of switch115can be coupled to a drain terminal of pull-down device130and a source terminal of pull-down device125, which is illustrated withinFIG. 1as node175.

In operation, Schmitt trigger100can display hysteresis with a threshold voltage at which Schmitt trigger100changes state. The threshold voltage can vary depending upon a current logic state of Schmitt trigger100prior to any change in the state of the logic. An operating point of nodes within Schmitt trigger100varies as Schmitt trigger100changes logic states, e.g., from a logic high to a logic low. This change of operating point of nodes within Schmitt trigger100, as Schmitt trigger100changes states, results in Schmitt trigger100behaving differently when receiving an input signal transitioning from a logic high to a logic low than the input signal transitioning from a logic low to a logic high.

Throughout this specification, signals are described in terms of logic levels, e.g., a logic high or a logic low, where the difference between a logic high and a logic low can represent a full output voltage range of a circuit. In general, the voltage associated with a logic high and a logic low is approximately equal to the voltage of each associated supply rail powering the circuit. The lowest and highest voltages to the circuit can be provided by a power supply coupled to an IC within which the circuit is implemented. Alternatively, a predetermined reference voltage can be generated, and/or used, within the IC to implement one end of the full output range of a circuit and thereby implement a logic state within the IC.

Throughout this specification reference is made to various voltage sources to which components of Schmitt trigger100can be coupled. As such, each voltage source can represent a node to which a component can be coupled as well as a particular voltage potential associated with that node. For example, the source terminal of pull-up device120is coupled the voltage source VCC135. Being coupled to VCC135, the voltage of VCC is present at the source terminal of pull-up device120. Thus, when referring to a node, reference numbers will be used. When referring to a voltage, the symbol, e.g., VCC or GND, generally will be used unaccompanied by the reference numbers. Similarly, a circuit whose output voltage range is limited to the voltage of the voltage sources powering the circuit can be said to vary between the voltages associated with each voltage source powering the circuit. For example, inverter105is coupled to, and powered by, voltage sources VCC135and GND140. Being powered by voltage sources VCC135and GND140, the voltage range of an output signal from inverter105can be referred to generally as varying between VCC and GND.

A “voltage range” can refer to a voltage differential between a highest and a lowest voltage provided, or specified, by a signal or supply voltage of a circuit. For example, an input signal that has a logic high of 2 V and a logic low of 1 V has a voltage range between 1 and 2 volts, e.g., a range of 1 V. Additionally, the signal voltage range of a first block can differ from the signal voltage range of a second block within a same circuit. Accordingly, the voltage of a logic high for each of the two blocks can differ. For example, assuming that the voltage of VCC135is 3.3 V, a voltage for a logic high at the output of inverter105can be approximately 3.3 V. Alternatively, assuming the voltage of Vaux160is 1.8 V, a logic high at the output of inverter110can be approximately 1.8 V. As such, a signal voltage range of inverter105can differ from a signal voltage range of inverter110.

Referring toFIG. 1at a time T1, the voltage of signal Vin145is in steady state at a logic high and approximately equal to VCC. As signal Vin145is the input signal to inverter105, the output of inverter105is at a logic low and the voltage of signal Vout1150is approximately equal to GND. More particularly, with the voltage of signal Vin145approximately equal to VCC, pull-up device120is disabled and pull-down devices125and130are enabled. In one or more embodiments, signal Vin145can be implemented with two separate signals. A first of the two signals can be coupled to the gate terminal of pull-up device120and a second of the two signals can be coupled to the gate terminal of each of pull-down devices125and130.

Enabling pull-down devices125and130creates a conductive pathway from node170to GND140. The conductive pathway from node170to GND140can discharge nodes170and175until the voltage at each of nodes170and175is approximately equal to GND. With signal Vout1150being the input signal to inverter110and at a logic low, the output signal from inverter110, which is denoted as Vout2155, is at a logic high. When at a logic high, the voltage of signal Vout2155is approximately equal to the voltage of Vaux160. In one embodiment, Vaux160can represent a supply voltage that provides power to inverter110and that is separate and distinct from VCC135. For example, Vaux160can be a predetermined reference voltage established within, or provided to, inverter110as a separate and distinct voltage source from VCC135.

Continuing at time T1, the voltage at the gate terminal of switch115, being coupled to signal Vout2155, is approximately Vaux. The voltage at the source terminal of switch115is approximately Vaux. As switch115can be implemented with a PFET device, the gate terminal to source terminal voltage (Vgs) of switch115is approximately zero volts. With the Vgsof switch115being approximately equal to zero volts, switch115is disabled. The disabling of switch115decouples Vaux160from node175. With switch115disabled and pull-down devices125and130enabled, the voltage at node175is approximately GND. It should be noted that at time T1, the voltage at the source terminal of each of pull-down devices125and130is approximately GND. Subsequent to time T1, and prior to time T2, signal Vin145can begin transitioning from a logic high to a logic low. The voltage at the gate terminals of each of pull-up device120and pull-down devices125and130transitions from approximately VCC to GND.

During the period of time from time T1to time T2, the Vgsacross pull-up device120transitions from approximately zero volts to approximately VCC. Additionally, during the period of time from time T1to time T2, the Vgsacross each of pull-down devices125and130transitions from approximately VCC to approximately zero volts.

As the Vgsacross pull-up device120increases, pull-up device120is enabled. As Vgsacross pull-down devices125and130decreases, pull-down devices125and130are disabled. As signal Vin145transitions from a logic high to a logic low, at a particular voltage of signal Vin145, pull-up device120sources, and each of pull-down devices125and130sinks, a substantially equal quantity of current. At the particular voltage of signal Vin145that results in equal quantities of current being sourced and sunk within inverter105by each of devices120,125, and130, the voltage at node170is approximately one half of VCC.

The particular voltage of signal Vin145at which the voltage at node170is approximately one half VCC can be considered a first threshold voltage at which the output of inverter105changes state from a logic low to a logic high. The particular voltage of signal Vin145at which the first threshold voltage of inverter105occurs is affected by one or more device characteristics of each of pull-up device120and pull-down devices125and130. For example, the particular voltage of the first threshold voltage is affected by the sizing ratio between the size of pull-up device120and the size of each of pull-down devices125and130.

It should be noted that at time T1switch115is disabled. Being disabled, switch115cannot source current to pull-down device130. As a result, as signal Vin145transitions from a logic high to a logic low, the current through pull-down device130is substantially equal to the current, denoted as I125, sourced through pull-down device125. Since the Vgsof a CMOS device is a function of the current flowing through the CMOS device, as signal Vin145transitions from a logic high to a logic low, the Vgs of pull-down device130is a function of I125.

As inverter105crosses the first threshold voltage, signal Vout1150transitions from approximately zero volts to approximately VCC. With signal Vout1150at a logic high, inverter110changes state and signal Vout2155transitions to a logic low. As signal Vout2155transitions from a logic high to a logic low, the Vgsacross switch115transitions from approximately zero volts to approximately negative Vaux. As the Vgsacross switch115decreases, switch115is enabled. Enabling switch115couples Vaux160to node175.

It should be noted that subsequent to Vaux160being coupled to node175, the operating conditions for pull-down device125are altered with the voltage at the source terminal of pull-down device125transitioning from approximately zero volts to approximately Vaux. With the voltage at the source terminal of pull-down device125at Vaux, the voltage required at the gate terminal of pull-down device125to enable pull-down device125must increase from the voltage required at time T1.

Continuing, subsequent to time T2and prior to time T3, signal Vin145can begin transitioning from a logic low to a logic high. The voltage at the gate terminals of pull-up device120, pull-down device125, and pull-down device130transitions from approximately GND to approximately VCC. During the period of time from time T2to time T3, the Vgsacross pull-up device120transitions from approximately VCC to approximately zero volts. Additionally, during the period of time from time T2to time T3, the voltage at the gate terminal of each of pull-down devices125and130transitions from approximately zero volts to approximately VCC.

As the Vgsacross pull-up device120decreases, pull-up device120is disabled. As the voltage at the gate terminal of each of pull-down devices125and130increases, initially only the Vgsof pull-down device130increases sufficiently to enable pull-down device130as the source terminal of pull-down device130is coupled to GND140. While the source terminal of pull-down device130is coupled to GND140, the source terminal of pull-down device125is coupled to node175. Node175is initially coupled to Vaux160through switch115. With the voltage at the source terminal of pull-down device125initially at approximately Vaux, the gate voltage necessary to enable pull-down device125is greater than the gate voltage necessary to enable pull-down device130. In that case, pull-down device130is enabled prior to the enabling of pull-down device125.

The enabling of pull-down device130results in pull-down device130being simultaneously enabled with switch115. Enabled pull-down device130can attempt to sink charge away from node175to GND140. Concurrently, switch115can attempt to source charge to node175from Vaux160. The size of the device used to implement pull-down device130relative to the size of the device used to implement switch115can be such that the current carrying capabilities of pull-down device130exceeds switch115. Sized in this manner, pull-down device130can sink more current than switch115can source. Accordingly, with each of pull-down device130and switch115enabled simultaneously, the voltage at node175can begin discharging down from approximately Vaux.

It should be noted that at time T2switch115is enabled. Being enabled, switch115sources current, denoted as I115, to pull-down device130. As a result, as signal Vin145transitions from a logic low to a logic high, the current through pull-down device130is equal to a sum of I115and I125. In contrast, the current through pull-down device130as signal Vin145transitions from logic high to a logic low is equal to I125. Accordingly, the value of Vgsrequired to sink current through pull-down device130as signal Vin145transitions from logic high to a logic low is less than the value of Vgsrequired to sink current through pull-down device130as signal Vin145transitions from logic low to a logic high. The additional current that is provided when switch115is enabled alters the location of the second threshold voltage at which Schmitt trigger100changes state from the location of the first threshold voltage at which Schmitt trigger100changes state. In this manner, hysteresis is introduced into Schmitt trigger100.

The enabling of pull-down device125, subsequent to the enabling of pull-down device130, creates a conductive pathway between node170and GND140. Through the conductive pathway, charge flows away from node170until the voltage at node170reaches approximately GND. Sizing pull-down device130and switch115to achieve a particular sizing ratio, a second threshold voltage that is higher than the first threshold voltage can be selected for Schmitt trigger100. The first threshold voltage can be triggered by a falling edge of Vin145. The second threshold voltage can be triggered by a rising edge of Vin145.

Subsequent to signal Vout1150transitioning to a logic low, signal Vout2155transitions to a logic high. With signal Vout2155at a logic low, the Vgsacross switch115approaches zero volts and switch115is disabled. Disabling switch115decouples Vaux160from node175, thereby allowing pull-down device130to pull the voltage at node175to approximately GND. At time T3, Schmitt trigger100achieves the same operational steady state as initially described at time T1. Subsequent to time T3, the operational behavior of Schmitt trigger100can repeat according to Vin145as described.

Within some electronic systems, an IC implemented within the system can be required to operate using a supply voltage that varies across a range of voltages. For example, an IC can be required to operate with both a 2.7 V supply voltage and a 3.3 V supply voltage. In addition, the IC also can be designed to operate within ±10% of the voltage specified for the supply voltage, e.g., 3.0-3.6 V for a 3.3 V supply voltage. For these reasons, the IC must remain stable and operable over a range of possible supply voltages.

In a conventional Schmitt trigger, switch115is implemented with an NFET device that, when enabled, couples VCC135to node175. A source terminal of the NFET device is coupled to node175. A gate terminal of the NFET device is coupled to node170and a drain terminal of the NFET device is coupled to VCC135. As the voltage of the voltage source coupled to node175by switch115, i.e., approximately VCC, influences the second threshold voltage, any variation in the voltage of VCC135can vary the location of the second threshold voltage of the conventional Schmitt trigger.

In addition, the NFET device used to implement switch115within a conventional Schmitt trigger is enabled by the output of inverter105, i.e., signal Vout1150. The NFET device used to implement switch115is enabled in the conventional Schmitt trigger when signal Vout1150is a logic high. Since signal Vout1150is the output signal of inverter105, the voltage associated with a logic high in signal Vout1150is determined by the voltage of VCC135when powering inverter105. As the voltage of VCC135varies, the Vgsacross the NFET device used to implement switch115varies.

Further, the current driving capability and Ronof the NFET device in the conventional Schmitt trigger is a function of the Vgsacross the NFET device. The current driving capability and Ronof the NFET device influences the location of the second threshold voltage of the conventional Schmitt trigger. As a result, any variation in the voltage of VCC135can vary the current driving capability and Ronof the NFET device and the location of the second threshold voltage of the conventional Schmitt trigger.

In accordance with one or more embodiments disclosed within this specification, the voltage source coupled to node175is Vaux160. Vaux160can be implemented with a stable voltage source that is independent of VCC135and, thus, any variation in VCC135. In addition, the PFET device used to implement switch115within Schmitt trigger100is enabled when signal Vout2155transitions to a logic low. The voltage associated with a logic low within signal Vout2155is approximately the voltage of GND140. The voltage associated with GND140can be considered a stable voltage that is independent of VCC135. As a result, in an enabled state, switch115is driven by a stable voltage that is independent of VCC135.

Within Schmitt trigger100, the voltage of Vaux160is unaffected by voltage variations within VCC135. Accordingly, switch115is enabled with a stable voltage independent of VCC135. As a result, the embodiments disclosed within this specification are not subject to variations in the location of the second threshold voltage caused by variations in the voltage of VCC135as is the case with conventional Schmitt triggers.

FIG. 2is a second schematic diagram illustrating the Schmitt trigger100ofFIG. 1.FIG. 2illustrates a more detailed view of Schmitt trigger100. As such, like numbers are used to refer to the same items throughout this specification.FIG. 2illustrates an embodiment of Schmitt trigger100that allows NFET and PFET devices to be implemented within Schmitt trigger100that possess voltage tolerances less than a supply voltage powering Schmitt trigger100. Thus, the embodiment of Schmitt trigger100illustrated inFIG. 2can be implemented within an IC powered by, or receiving, a voltage greater than the voltage tolerance of one or more CMOS devices of an IC manufacturing process within which the IC is implemented.

As pictured inFIG. 2, inverter105can include pull-up device205and a pull-down device210, each being an additional device not previously described with reference toFIG. 1. A gate terminal of pull-up device205can be coupled to a voltage source Vpbias215. Vpbias215can provide a static voltage that biases pull-up device205to a selected operating point. Pull-down device210can be coupled to a voltage source Vnbias220. Vnbias220can provide a static voltage that biases pull-down device210to a selected operating point. WithinFIG. 2, inverter105receives a pair of input signals denoted as signals Vin145A and Vin145B as opposed to a single input signal as illustrated withinFIG. 1. In this regard, inverter105outputs a pair of output signals denoted as signals Vout1150A and Vout1150B.

As device feature size decreases in CMOS IC processes, electric fields generated across junctions within a CMOS device can increase as a power supply voltage to the CMOS device remains constant. The same increase in electric field also can occur across oxide layers within CMOS processes, e.g., gate oxides, as oxide layers decrease in thickness. When large enough, electric fields can damage junctions and oxide layers within the CMOS device. Additionally, large electric fields can degrade performance parameters of the CMOS device. To prevent damage to CMOS devices as device feature size is reduced, the maximum voltage applied to a CMOS device must be scaled downward.

VCC135represents a supply voltage with a voltage greater than the breakdown voltages of the CMOS devices used to implement Schmitt trigger100. As the voltage of VCC135is greater than the breakdown voltages of pull-up device120, pull-up device205can be implemented within inverter105to prevent the full voltage of VCC135from being applied across any two terminals of pull-up device120. Within this specification, the phrase “breakdown voltage,” also denoted as “VBK,” can refer to a highest voltage that can be applied across any two terminals of a CMOS device without damaging a junction and/or a dielectric layer within the CMOS device.

For purposes of illustration, the value of the VBKcan be assumed to be common to each pair of terminals of each CMOS device type. The embodiments disclosed herein, however, are not intended to be limited by the commonality of VBKacross devices. For example, CMOS devices implemented within most modern IC manufacturing processes can possess two or more values for VBKdepending upon which terminal pair of the CMOS device the value of VBKis associated. In illustration, a gate terminal to source terminal value of VBKfor a CMOS device can differ from a drain terminal to source terminal value of VBKfor the CMOS device.

In order to protect pull-up devices120and205from voltages exceeding VBK, a voltage can be selected for Vpbias215such that Vpbias is less than or equal to VBK, and VCC minus Vpbias is less than or equal to VBK. In addition, VBKfor each CMOS device within Schmitt trigger100must be greater than one half of approximately VCC. With Vpbias215coupled to the gate terminal of pull-up device205, pull-up device205is disabled when the voltage of signal Vout150A is less than or equal to Vpbias215. In that case, the Vgsacross pull-up device205is approximately zero volts, thereby assuring that pull-up device205is disabled.

Since pull-up device205is disabled when signal Vout150A is less than or equal to Vpbias215, the voltage at the source terminal of pull-up device205cannot be discharged below Vpbias215. Accordingly, the voltage range of signal Vout1150A is limited to a range defined by VCC and Vpbias. In that case, the Vgsacross pull-up device205cannot exceed VCC minus Vpbias. In addition, neither the gate terminal to drain terminal voltage (Vgd) nor the drain terminal to source terminal voltage (Vds) applied across pull-up device205can exceed Vpbias. With Vpbias selected such that Vpbias is less than or equal to VBK, and VCC minus Vpbias being less than or equal to VBK, each of the Vgs, the Vgd, and the Vdsacross pull-up device205cannot exceed VBK.

Further, with voltage of signal Vout1150A unable to discharge below Vpbias, pull-up device120can be protected by limiting the voltage range of signal Vin145A to vary between VCC and Vpbias. With the voltage range of signal Vin145A limited in this manner, each of the Vgs, the Vgd, and the Vdsacross pull-up device120cannot exceed VBK.

For example, Schmitt trigger100can be implemented using CMOS devices with a VBKof 1.8 V. VCC can be equal to 3.3 V and Vpbias can be selected to be 1.65 V. The voltage range of Vin145A can be limited to vary between 1.65 V and 3.3 V. When Schmitt trigger100is operational, node250can swing between GND and VCC. Under these conditions, the maximum Vgdacross pull-up device205is 1.65 V, i.e., 3.3 V−1.65 V or 1.65 V−0 V. The maximum Vgsis 1.65 V, i.e., 3.3 V−1.65 V. The maximum Vdsoccurs when signal Vin150A is a logic high and pull-up device205is disabled. In that case, the Vdsis 1.65 V with the voltage of signal Vout1150A being equal to approximately 1.65 V and the voltage at node245being equal to approximately zero volts.

With signal Vout1150A varying between 1.65 V and 3.3 V, the voltage at the gate terminal of pull-up device120at 1.65 V, and the voltage at the source terminal of pull-up device120at 3.3 V, each of the Vgs, the Vgd, and the Vdsof pull-up device120cannot exceed 1.65 V. With the Vgs, the Vgd, and the Vdsof each of pull-up devices120and/or205not exceeding 1.65 V and VBKequal to 1.8 V, each of pull-up devices120and205is protected from receiving a voltage exceeding VBK.

As noted, the voltage range of signal Vout1150A can vary between Vpbias and VCC. Signal Vout1150A is coupled to the gate terminal of pull-up device225within inverter110. Vpbias215is coupled to the gate terminal of pull-up device230within inverter110. With the selected voltage range of signal Vin145A being approximately equal to the voltage range of signal Vout1150A, the operating conditions for pull-up devices225and230are approximately equal to the operation conditions for pull-up devices120and205. For this reason, under these same operating conditions, each of the Vgs, the Vgd, and the Vdsof each of pull-up devices225and230does not exceed VBK.

The techniques used to protect pull-up devices120and205can be applied to protect pull-down devices125,130, and210. Referring toFIG. 2, pull-down device210is added to inverter105in order to limit voltage across any pair of terminals of pull-down devices125and130to less than or equal to VBK. To protect pull-down devices125and130, Vnbias can be selected such that Vnbias is less than or equal to VBK, and VCC minus Vnbias is less than or equal to VBK. With Vnbias220coupled to the gate terminal of pull-down device210, the voltage of signal Vout1150B is prevented from increasing above Vnbias.

For example, VCC can be 3.3 V and Vnbias can be selected to be 1.65 V. VBKfor the CMOS devices used to implement Schmitt trigger100can be 1.8 V. The selected voltage of 1.65 V for Vnbias meets the conditions that the voltage of Vnbias be less than or equal to VBK, i.e., 1.65 V is less than 1.8 V, and VCC minus Vnbias be less than or equal to VBK, i.e., 3.3 V−1.65 V=1.65 V, which is less than 1.8 V. As the voltage at node255approaches 1.65 V, the Vgsfor pull-down device210approaches zero volts and pull-down device210is completely disabled. For this reason, signal Vout1150B is limited to a voltage range of 0 V to 1.65 V before pull-down device210is disabled and no further charge can be sourced through pull-down device210to node255.

With the voltage of signal Vout1150B limited to Vnbias, signal Vin145B can be implemented with a voltage range varying between GND and Vnbias. Limiting the voltage range of signal Vin145B to be less than or equal to Vnbias assures that, for each of pull-down devices125,130, and220, each of the Vgs, the Vgd, and the Vdsdoes not exceed VBK.

Signal Vout1150B is coupled to the gate terminal of pull-down device240within inverter110. Vaux160is coupled to the gate terminal of pull-down device235within inverter110. Vaux can be selected to meet the conditions set forth for Vnbias, i.e., where Vaux is less than or equal to VBK, and VCC minus Vaux is less than or equal to VBK. Selecting Vaux that meets these conditions assures that the Vgs, the Vgd, and the Vdsfor each of pull-down devices235and240does not exceed VBK.

With Vaux160coupled to the gate terminal of pull-down device235, pull-down device235is disabled upon the voltage of signal Vout2155increasing to Vaux. As a result, the voltage range of signal Vout2155is limited to varying between GND and Vaux. By selecting Vaux to be less than the lowest possible voltage allowable for VCC as a supply voltage to Schmitt trigger100, the voltage of signal Vout2155can be assured of increasing to Vaux regardless of the voltage of VCC. As such, the voltage range of signal Vout2155remains constant even as the voltage of VCC varies.

It should be noted that the output signal from Schmitt trigger100is represented with signal Vout260. The voltage range of signal Vout260is approximately 0 V to the voltage of VCC135. Should a voltage limited output signal be desired from Schmitt trigger100, the output signal can be output at the coupling point between the drain terminal of pull-up device225and the source terminal of pull-up device230and/or the coupling point between the drain terminal of pull-down device240and the source terminal of pull-down device235. As such, implementation of the output signal from Schmitt trigger100with signal Vout260, as described within this specification, is for descriptive purposes only and is not intended to limit the embodiments disclosed within this specification.

Signal Vout2155is coupled to the gate terminal of switch115and controls the enabling and disabling of switch115. To assure that switch115is fully disabled, the Vgsfor switch115must approach zero volts. As the source terminal of switch115is coupled to Vaux160, in order to achieve a Vgsof zero volts across switch115, the voltage of signal Vout2155must increase to Vaux.

Switch115is enabled when signal Vout2155is a logic low and a voltage of approximately GND140is applied to the gate terminal of switch115. Since GND140is a voltage source independent of VCC135, the enabling of switch115is not affected by variation in VCC. The source terminal of switch115is coupled to Vaux160, and a voltage of approximately that of Vaux160is coupled to node175subsequent to switch115being enabled. Since Vaux160is a voltage source independent of VCC135, the voltage coupled to node175subsequent to switch115being enabled is independent of variations in the voltage of VCC135.

As previously noted, within conventional Schmitt triggers, the voltage that enables switch115can be dependent upon VCC. Additionally, within conventional Schmitt triggers, the voltage coupled to node175can be VCC. Each of the voltages that enable switch115and the voltage coupled to node175can influence the location of the second threshold voltage within conventional Schmitt triggers. As such, conventional Schmitt trigger inverters are susceptible to changes in operational behavior that arise due to the second threshold voltage varying along with the voltage of VCC135.

Within Schmitt trigger100, the voltage that enables switch115, the voltage that disables switch115, and the voltage coupled to node175affects the location of the second threshold voltage within Schmitt trigger100. Within Schmitt trigger100, the voltage that enables switch115, the voltage that disables switch115, and the voltage coupled to node175each is independent of variations in the voltage of VCC. Thus, as VCC varies, the second threshold voltage within Schmitt trigger100remains constant.

FIG. 3is a signal graph illustrating exemplary signal changes at various nodes of Schmitt trigger100as described with reference toFIGS. 1 and 2.FIG. 3illustrates a case where the input signal to the Schmitt trigger inverter100transitions from a logic low to a logic high and then transitions back to a logic low. WithinFIG. 3, a ramp function is used as the input signal to Schmitt trigger100, i.e., signals Vin145A and145B. Implementing signals Vin145A and145B as ramp functions provides clarity as to the voltage level of the two differing input voltage thresholds at which Schmitt trigger100changes state.

Beginning at a time T1, signals Vin145A and145B are initially in a logic low state. Signal Vin145A is implemented such that the voltage of signal Vin145A cannot decrease below Vpbias. For that reason, the initial voltage of a logic low for signal Vin145A is approximately Vpbias. Thus, the voltage of the segment of the ramp function within signal145A residing between times T1and T2is truncated at approximately Vpbias. In a similar manner, Signal Vin145B is implemented such that the voltage of signal Vin145B cannot increase above Vnbias. Thus, the voltage of the segment of the ramp function within signal145B residing between times T2and T4is truncated at approximately Vnbias.

WithinFIG. 3, Vpbias is set equal to Vnbias. It should be appreciated, however, that Vpbias and Vnbias can be two different voltages. Vpbias is described with reference toFIG. 3as being equal to Vnbias for descriptive purposes only. As such, the embodiments disclosed within this specification are not limited to Vpbias being equal to Vnbias.

At time T1, input signals Vin145A and Vin145B are providing logic lows as inputs to inverter105ofFIG. 2. With the input signal to inverter105being a logic low, output signals Vout1150A and Vout2150B of inverter105are logic highs. The voltage of a logic high for signal Vout1150B is limited to Vnbias. Assuming the voltages Vpbias and Vnbias are selected to be less than a VBKassociated with the CMOS devices used to implement Schmitt trigger100, limiting the voltage range of each of signals Vin145A, Vin145B, Vout1150A, and Vout1150B limits the voltage applied across any pair of terminals within each CMOS device of Schmitt trigger100to less than VBK. Limiting the voltage of signals Vin145A, Vin1458, Vout1150A, and Vout1150B allows Schmitt trigger100to be implemented with CMOS devices having a VBKless than VCC.

Since signals Vout150A and150B are inputting a logic high to inverter110, output signal Vout2155from inverter110is a logic low. When at a logic low, signal Vout2155discharges the gate terminal of switch115to approximately zero volts and switch115is enabled. With switch115enabled, Vaux160is coupled to node175and the voltage at node175is approximately Vaux.

Subsequent to time T1and prior to a time T2, the voltage of signal Vin145A exceeds Vpbias and signal Vin145A begins increasing, consistent with a ramp function, toward VCC. Concurrently, the voltage of signal Vin145B increases to approximately Vnbias. As the voltage of signal Vin145B is limited to Vnbias, the top of the ramp function is truncated at a voltage of Vnbias.

At time T2, the voltage of signals Vin145A and Vin1458are sufficient to change the output state of inverter105. In order to change the output state of inverter105, node175must discharge sufficiently to allow pull-down device125within inverter105to be enabled. At time T2, pull-up device130and switch115are both enabled. In addition, pull-down device125is transitioning from off to enabled and beginning to sink current from node170. As such, pull-down device130simultaneously sinks current from switch115and pull-down device125.

Eventually, pull-down device130sufficiently discharges node175to fully enable pull-down device125. With pull-down device125enabled, inverter105changes logic state and output signals Vout1150A and Vout1150B of inverter105transition from a logic high to a logic low. The voltage of signal Vout1150A decreases to Vpbias as signal Vout1150A transitions to a logic low. The voltage of signal Vout1150B decreases to approximately zero volts as signal Vout1150B transitions to a logic low.

With signals Vout1150A and Vout1150B provided to inverter110at logic lows, output signal Vout2155from inverter110transitions to a logic high. The voltage of signal Vout2155at a logic high is approximately Vaux. Applying a voltage of approximately Vaux to the gate terminal of switch115disables switch115. Disabling switch115decouples Vaux160from node175. As switch115decouples Vaux160from node175, node175can continue discharging until the voltage at node175is approximately zero volts. The voltage level of signals Vin145A and Vin145B at which the logic state of Schmitt trigger100changes is a threshold voltage for the Schmitt trigger100. Vth305denotes the second threshold voltage of Schmitt trigger100that occurs as signals Vin145A and Vin145B transition from a logic low to a logic high.

Subsequent to time T2, signal Vin145A continues increasing in voltage and signal Vin145B increases to a logic high with a voltage limited at approximately Vnbias. At time T3, each of signals Vin145A and Vin145B begin transitioning to a logic low. At time T4, the voltage of each of signals Vin145A and Vin145B decreases sufficiently to alter the output state of inverter105from a logic low to a logic high. Vth310denotes the voltage level of each of signals Vin145A and Vin1458that transitions the output state of inverter105from a logic low to a logic high.

As inverter105changes output state to a logic high, each of signals Vout1150A and Vout1150B transition to a logic high. With each of signals Vout1150A and Vout1150B at a logic high, the output state of inverter110transitions to a logic low. Accordingly, the voltage of signal Vout2155decreases to approximately zero volts and switch115is enabled. With switch115enabled, Vaux160is coupled to node175and the voltage at node175increases to approximately Vaux. With Vaux160coupled to node175, Schmitt trigger100has transitioned from one logic state to another. Therefore, voltage Vth310represents the first threshold voltage of Schmitt trigger100that occurs as signals Vin145A and Vin145B transition from a logic high to a logic low.

It should be noted that at time T2, node175begins transitioning prior to signals Vout1150A, Vout1150B, and Vout2155. This occurs as the voltage at node175must be decreased sufficiently to fully enable pull-down device125and allow inverter105to change states. Alternatively, at time T4node175transitions subsequent to signals Vout1150A, Vout1150B, and Vout2155. This occurs as the voltage at node175cannot change until switch115is enabled and Vaux is coupled to node175. Subsequent to time T4, switch115cannot be enabled until signal Vout2155changes state and the voltage at the gate terminal of switch115is discharged to zero volts.

In addition, the threshold voltage level of signals Vin145A and Vin145B at time T2, i.e., Vth305, differs from the threshold voltage level of signals Vin145A and Vin145B at time T4, i.e., Vth310. Further, at time T2the voltage at node175is higher than the voltage at node175at time T4. The increase in voltage at node175and current sourced by switch115at time T2requires a higher threshold voltage from signals Vin145A and Vin1458at time T2to change the state of inverter105than required to change the state of inverter105at time T4. Thus, the difference in voltage at node175and current sourced by switch115between when signals Vin145A and145B transition from a logic high to a logic low, as compared to when signals Vin145A and145B transition from a logic low to a logic high, produces the hysteresis that is inherent within Schmitt trigger100.

The terms “a” and “an,” as used herein, are defined as one or more than one. The term “plurality,” as used herein, is defined as two or more than two. The term “another,” as used herein, is defined as at least a second or more. The terms “including” and/or “having,” as used herein, are defined as comprising, i.e., open language.