Magnetoresistive random access memory cell

A magneto-resistive random access memory (MRAM) cell includes a substrate having a dielectric layer disposed thereon, a conductive via disposed in the dielectric layer, and a cylindrical stack disposed on the conductive via. The cylindrical stack includes a bottom electrode, a magnetic tunneling junction (MTJ) layer on the bottom electrode, and a top electrode on the MTJ layer. A spacer layer is disposed on a sidewall of the cylindrical stack. The top electrode protrudes from a top surface of the spacer layer.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to the field of semiconductor technology, and more particularly to a spin-transfer torque magnetoresistive random access memory (STT-MRAM) cell structure.

2. Description of the Prior Art

As known in the art, spin-transfer torque magnetoresistive random access memory (STT-MRAM) is a non-volatile memory that has come under much scrutiny recently in the industry, which has several advantages over the conventional magnetoresistive random access memory. For example, these advantages include higher endurance, lower-power consumption, and faster operating speed.

In a magneto-tunnel junction (MTJ) including two ferromagnetic layers having a thin insulating layer therebetween, the tunnel resistance varies depending on the relative directions of magnetization of the two ferromagnetic layers. A magnetoresistive random access memory may be a semiconductor device where magnetic elements (MTJ elements) having MTJs utilizing a tunnel magneto resistance (TMR) effect are arranged in a matrix form as a memory cell.

SUMMARY OF THE INVENTION

The present invention provides an improved spin-transfer torque magnetoresistive random access memory (STT-MRAM) cell structure.

An aspect of the invention provides a magnetoresistive random access memory (MRAM) cell, comprising: a substrate having a dielectric layer thereon; a conductive via hole disposed in the dielectric layer; and a cylindrical stack disposed on the conductive via. The cylindrical stack includes a bottom electrode, a magnetic tunneling junction (MTJ) layer disposed on the bottom electrode, and a top electrode disposed on the MTJ layer. A spacer layer is disposed on the sidewall of the cylindrical stack. The top electrode protrudes from a top surface of the spacer layer.

According to an embodiment of the invention, the top electrode comprises a ruthenium (Ru) layer and a tantalum (Ta) layer on the Ru layer. The top electrode has a conical shape with its vertex pointing upwardly above the top surface of the spacer layer.

According to another embodiment of the present invention, the top electrode comprises a ruthenium (Ru) layer and a titanium nitride (TiN) layer on the Ru layer. The top electrode includes an upwardly convex curved top surface profile.

DETAILED DESCRIPTION

In the following detailed description of the disclosure, reference is made to the accompanying drawings, which form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention.

Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. Therefore, the following detailed description is not to be considered as limiting, but the embodiments included herein are defined by the scope of the accompanying claims.

Please refer toFIG. 1, which is a cross-sectional view of a magnetoresistive random access memory (MRAM) cell according to an embodiment of the invention. As shown inFIG. 1, the MRAM cell1comprises a substrate10, such as a silicon substrate, having a dielectric layer stack100thereon, including, but not limited to, a dielectric layer110, a stop layer112, and a dielectric layer120, an interlayer dielectric (ILD) layer130, a stop layer140, and an interlayer dielectric layer150. For example, the dielectric layer110may be an ultra low-k material layer, and the dielectric layer120may be a silicon oxide layer, but is not limited thereto. For example, the stop layers112,140may be a nitrogen-doped silicon carbide layer or a silicon nitride layer, but are not limited thereto. For example, the stop layer140is a nitrogen-doped silicon carbide layer.

According to an embodiment of the invention, a lower metal interconnect structure111may be formed in the dielectric layer110. A conductive via121is provided in the dielectric layer120. According to an embodiment of the invention, the lower metal interconnect structure111may be a copper wire, and the conductive via121may be a tungsten metal via, but is not limited thereto.

According to an embodiment of the invention, a cylindrical stack30is disposed on the conductive via121. According to an embodiment of the invention, the cylindrical stack30includes a bottom electrode310, a magnetic tunneling junction (MTJ) layer320disposed on the bottom electrode310, and a top electrode330disposed on the MTJ layer320. According to an embodiment of the invention, the width of the bottom electrode310is greater than the width (or diameter) of the conductive via121. The bottom electrode310may include, for example, but not limited to, tantalum (Ta), platinum (Pt), copper (Cu), gold (Au), aluminum (Al), or the like. According to an embodiment of the invention, the sidewall30aof the cylindrical stack30tapers from the bottom electrode310to the top electrode330.

The multi-layer structure of the MTJ layer320is well known, and the details thereof will not be described herein. For example, the MTJ layer320may include a fixed layer, a free layer, and a capping layer, but is not limited thereto. The fixed layer may be composed of an antiferromagnetic (AFM) material such as iron manganese (FeMn), platinum manganese (PtMn), lanthanum manganese (IrMn), nickel oxide (NiO), etc., to fix or limit the direction of the magnetic moment of the proximity layer. The free layer may be composed of a ferromagnetic material such as iron, cobalt, nickel, or an alloy thereof such as cobalt-iron-boron (CoFeB), but is not limited thereto.

According to an embodiment of the invention, the top electrode330comprises a ruthenium (Ru) layer331and a tantalum (Ta) layer332disposed on the base ruthenium layer331.

According to an embodiment of the invention, the MRAM cell1further comprises a spacer layer340disposed on the sidewall30aof the cylindrical stack30. According to an embodiment of the invention, the spacer layer340may be a silicon nitride spacer layer. In accordance with an embodiment of the invention, the spacer layer340has a thickness of between about 300 angstroms and about 600 angstroms. In accordance with an embodiment of the invention, the top electrode330protrudes from the top surface340aof the spacer layer340.

According to an embodiment of the invention, the dielectric layer120surrounds the conductive via121and has a tapered outer surface120a. In accordance with an embodiment of the invention, the spacer layer340extends to the tapered outer surface120aof the dielectric layer120. According to an embodiment of the invention, the bottom electrode310is in direct contact with the conductive via121and the dielectric layer120surrounding the conductive via121. In accordance with an embodiment of the invention, the top electrode330has a conical shape330awith its vertex pointing upwardly above the top surface340aof the spacer layer340.

According to an embodiment of the invention, the interlayer dielectric layer130covers the dielectric layer120, the cylindrical stack30, and the spacer layer340. The stop layer140is disposed on the interlayer dielectric layer130. The interlayer dielectric layer150is disposed on the stop layer140. A dual damascene metal interconnect structure50is embedded in the interlayer dielectric layer150, the stop layer140, and the interlayer dielectric layer130. The dual damascene metal interconnect structure50includes a via plug510and a metal trace520formed integrally with the via plug510. The dual damascene metal interconnect structure50can be formed by a copper dual damascene process. The copper dual damascene process is well known, so the details are not described herein.

According to an embodiment of the invention, the via plug510is electrically coupled to the top electrode330. In accordance with an embodiment of the present invention, the via plug510completely covers the portion with conical shape330aof the top electrode330and may cover a portion of the top surface340aof the spacer layer340.

Another feature inFIG. 1is that the spacer layer340is etched and formed only on the sidewall30aof the cylindrical stack30and extends slightly downward to the upwardly tapered outer surface120aof the dielectric layer120. During the anisotropic dry etching of the spacer layer340, a recess structure123is formed on the dielectric layer120.

FIG. 2is a cross-sectional view of a MRAM cell according to another embodiment of the present invention, wherein the same regions, material layers or elements are still denoted by the same numeral numbers.

As shown inFIG. 2, the MRAM cell1ahas substantially the same structure as the MRAM cell1ofFIG. 1except that the spacer layer340of the MRAM cell1acompletely covers the surface of the dielectric layer120and the spacer layer340is not etched, and thus the recess structure123on the dielectric layer120inFIG. 1is not formed. In addition, the via plug510penetrates through the spacer layer340to be electrically coupled to a portion of the portion with conical shape330aof the top electrode330.

FIG. 3is a cross-sectional view of a MRAM cell according to still another embodiment of the present invention, wherein the same regions, material layers or elements are still denoted by the same numeral numbers.

As shown inFIG. 3, the MRAM cell2has substantially the same structure as the MRAM cell1ofFIG. 1except that the top electrodes of the cylindrical stack are different. The cylindrical stack40of the MRAM cell2includes a bottom electrode410, a magnetic tunneling junction (MTJ) layer420disposed on the bottom electrode410, and a top electrode430disposed on the MTJ layer420. According to an embodiment of the invention, the top electrode430comprises a ruthenium (Ru) layer431and a titanium nitride (TiN) metal layer432disposed on the Ru layer431.

According to an embodiment of the invention, likewise, the MRAM cell2comprises the spacer layer340that is disposed on the sidewall40aof the cylindrical stack40. According to an embodiment of the invention, the spacer layer340may be a silicon nitride spacer layer. In accordance with an embodiment of the invention, the spacer layer340has a thickness of between about 300 angstroms and about 600 angstroms. In accordance with an embodiment of the invention, the top electrode430protrudes from the top surface340aof the spacer layer340.

According to an embodiment of the invention, likewise, the dielectric layer120surrounds the conductive via121and has a tapered outer surface120a. In accordance with an embodiment of the invention, the spacer layer340extends to the tapered outer surface120aof the dielectric layer120. According to an embodiment of the invention, the bottom electrode410directly contacts the conductive via121and the dielectric layer120surrounding the conductive via121. In accordance with an embodiment of the invention, the top electrode430has an upwardly convex curved top surface profile430aabove the top surface340aof the spacer layer340.

FIG. 4is a cross-sectional view of a MRAM cell according to still another embodiment of the present invention, wherein the same regions, material layers or elements are still denoted by the same numeral numbers.

As shown inFIG. 4, the MRAM cell2ahas substantially the same structure as the MRAM cell2ofFIG. 3except that the spacer layer340of the MRAM cell2acompletely covers the surface of the dielectric layer120and the spacer layer340is not etched, and thus the recess structure123on the dielectric layer120inFIG. 3is not formed. In addition, the via plug510penetrates through the spacer layer340to be electrically coupled to the portion with the upwardly convex curved top surface profile430aof the top electrode430.