Hysteretic mode controller for capacitor voltage divider

A hysteretic mode controller for controlling a capacitor voltage divider which has a flying capacitor. In one embodiment, the hysteretic mode controller includes an amplifier, a gain circuit and a hysteretic comparator circuit. The amplifier has an input for coupling to the flying capacitor and an output providing a fly voltage. The gain circuit has an input for receiving the input voltage and an output coupled to a reference node providing a reference voltage. The hysteretic comparator circuit has a first input coupled to the output of the amplifier, a second input receiving the reference voltage, and an output for providing a PWM signal to control the capacitor voltage divider. The fly voltage is compared to voltage limits of a hysteretic voltage window for switching the PWM signal. The switching frequency is increased with higher load current to maintain high efficiency.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to power electronics, and more particularly to a hysteretic mode controller for a capacitor voltage divider for dividing a voltage with high efficiency.

2. Description of the Related Art

Electronic circuits use a variety of voltage levels suitable for various purposes. Lower voltage levels are suitable for smaller devices to prevent damage or to reduce power. A power or voltage converter is often used to reduce a higher voltage to a lower voltage level, such as a conventional buck converter or the like. A buck converter, however, has several disadvantages, such as diode reverse recovery, inductor power loss, etc. Capacitive voltage dividers have also been used to reduce voltage level and do not have many of the disadvantages of conventional converters. It is desired to maximize efficiency of a capacitive voltage divider within an electronic circuit.

DETAILED DESCRIPTION

FIG. 1is a schematic and block diagram of a capacitor voltage divider with hysteretic mode control circuit100implemented according to an exemplary embodiment. The capacitor voltage divider with hysteretic mode control circuit100includes a capacitor voltage divider102controlled by a pulse width modulation (PWM) signal and a hysteretic mode controller104providing the PWM signal. The capacitor voltage divider102includes an upper switch circuit103, a lower switch circuit105, and a capacitor C3. The upper switch circuit103includes a pair of electronic switches Q1and Q2and a capacitor C1and the lower switch circuit105includes another pair of electronic switches Q3and Q4and another capacitor C2. In the illustrated embodiment, the electronic switches Q1-Q4are each configured as an N-channel metal oxide semiconductor, field-effect transistor (MOSFET), although other types of electronic switches are contemplated (e.g., P channel devices, other types of FETs, other types of transistors, etc.). Q1has a drain coupled to an input node107providing an input voltage VIN and a source coupled to a first phase node109developing a positive “fly” voltage VFLY+. Q2has a drain coupled to phase node109and a source coupled to an output node111developing an output voltage VOUT. Q3has a drain coupled to the output node111and a source coupled to a second phase node113developing a negative “fly” voltage VFLY−. Q4has a drain coupled to the phase node113and a source coupled to a reference node115, which is shown as a ground (GND) node. The capacitor C1is coupled between the input and output nodes107and111, and the capacitor C2is coupled between the output and reference nodes111and115. The capacitor C3is a “flying” capacitor coupled between the positive and negative fly nodes109and113.

The switch driver circuit101has an input receiving the PWM signal, a first output providing a first upper gate signal UG1to the gate of Q1, a second output providing a first lower gate signal LG1to the gate of Q2, a third output providing a second upper gate signal UG2to the gate of Q3, and fourth output providing a second lower gate signal LG2to the gate of Q4. The switch driver circuit101is configured to drive the control inputs of the electronic switches Q1-Q4, such as, for example, a MOSFET gate driver circuit for driving the gates of the switches Q1-Q4when implemented as MOSFETs. The switch driver circuit101is also shown with inputs for sensing the phase nodes109and113and the output node111. In operation, the switch driver circuit101drives the upper gate signals UG1and UG2high to turn on the switches Q1and Q3when the PWM signal is in an active state (e.g., at a high logic level), and drives the lower gate signals LG1and LG2high to turn on the switches Q2and Q4when the PWM signal is in an inactive state (e.g., at a logic low level). The switch driver circuit101also operates to ensure that the upper switches Q1and Q3are not turned on at the same time as the lower switches Q2and Q4, and vice-versa. For example, the switches Q2and Q4are turned off before the switches Q1and Q3are turned on, and the switches Q1and Q3are turned off before the switches Q2and Q4are turned on, and so on.

The hysteretic mode controller104receives the VFLY+ and VFLY− signals (VFLY+/−) and the VIN signal and controls the PWM signal to maintain VOUT at approximately one-half the voltage level of VIN. The capacitor voltage divider with hysteretic mode control circuit100provides the VOUT signal to a load circuit117coupled between nodes111and115. The load circuit117receives a load current IL from node111.

FIG. 2is a more detailed schematic diagram of the hysteretic mode controller104according to an exemplary embodiment. The hysteretic mode controller104includes a gain circuit201having an input coupled to input node107to receive the VIN signal and an output coupled to a node202developing a reference voltage VREF within a hysteretic comparator circuit204. The gain circuit201multiplies VIN by a gain value K1, which is any suitable fraction between 0 and 1. In one embodiment, the hysteretic mode controller104operates to control the voltage level of VOUT to be approximately one-half the voltage level of VIN. In this embodiment, K1=½ to provide the voltage of VREF to be approximately one-half the voltage level of VIN. The hysteretic comparator circuit204includes first and second voltage sources203and205, first and second hysteretic comparators207and209, and a logic circuit213. The first voltage source203has its negative terminal coupled to node202and its positive terminal coupled to the inverting or negative input of the first hysteretic comparator207. The second voltage source205has its positive terminal coupled to the node202and its negative terminal coupled to the non-inverting or positive input of the second hysteretic comparator209. The voltage sources203and205have relatively small voltages to develop a hysteretic voltage window just above and below VREF, shown as VHYSTP and VHYSTN, respectively. The hysteretic mode controller104includes an amplifier211(e.g., a differential amplifier) having a non-inverting or positive input coupled to node109for receiving the VFLY+ signal and an inverting or negative input coupled to node113for receiving the VFLY− signal. The amplifier211has an output coupled to the non-inverting input of the comparator207and to the inverting input of the comparator209. The amplifier211amplifies the voltage difference between VFLY+ and VFLY− to develop a signal VFLY provided as another input of the hysteretic comparator circuit204.

The outputs of the comparators207and209are provided to respective inputs of the logic circuit213. In one embodiment, the logic circuit213is a set-reset (SR) logic circuit (such as an SR flip-flop or latch circuit or the like) having a reset (R) input coupled to the output of the comparator207, a set (S) input coupled to the output of the comparator209, and a Q output providing the PWM signal. In operation, when the voltage VFLY+, VFLY− across the flying capacitor C3causes the VFLY voltage to fall below VHSYTN, the comparator209asserts its output high to cause the logic circuit213to assert the PWM signal high, and when the voltage VFLY+, VFLY− across the capacitor C3causes the VFLY voltage to rise above VHSYTP, the comparator207asserts its output high to cause the logic circuit213to assert the PWM signal low. It is noted that as the load current IL increases, the capacitor C3charges more quickly when the switches Q1and Q3are turned on (and the switches Q2and Q4are turned off) and that the capacitor C3discharges more quickly when the switches Q2and Q4are turned on (and the switches Q1and Q3are turned off). In this manner, the switching frequency of the PWM signal, as controlled by the hysteretic mode controller104, increases with increasing load current IL.

FIG. 3is a graph diagram plotting percentage efficiency of the capacitor voltage divider102versus load current IL in Amperes (A) for various fixed frequencies of the PWM signal having a 50% duty cycle. In each case the input voltage VIN is the same (e.g., 12 volts) and the load current IL is increased from 0 to over 10 A. Several curves301,303,305,307and309are plotted for switching frequencies 100, 200, 300, 400 and 500 kilohertz (kHz), respectively. The curve301for 100 kHz illustrates that efficiency is higher for the switching frequency of 100 kHz for load current IL up to about 3 A. From about 3 A to 5 A, efficiency is higher for switching frequency of 200 kHz as shown by curve303. From about 5 A to 6.5 A, efficiency is higher for switching frequency of 300 kHz as shown by curve305. From about 6.5 to 10 A, efficiency is higher for switching frequency of 400 kHz as shown by curve307. And above 10 A, efficiency is highest for switching frequency of 500 kHz as shown by curve309. In general,FIG. 3illustrates that efficiency of the capacitor voltage divider102is maintained at a higher level when switching frequency is increased with increased load current.

FIG. 4is a graph diagram plotting load current IL (A), VFLY (in Volts or V), and VOUT (V) versus time (in microseconds or μs) for an exemplary embodiment of the capacitor voltage divider with hysteretic mode control circuit100. VREF is set to approximately 12V and the voltage of each voltage source203and205is approximately 0.1V, so that VHYSTP is approximately 6.1V and VHSYTN is approximately 5.9V. In this manner, VFLY has a ripple voltage and oscillates between VHYSTP and VHYSTN. At a time T0, the load current IL increases linearly from a lower current level (e.g., OA) towards a higher current level (e.g., 8 A). As the load current IL increases, the time of charging and discharging of the fly capacitor decreases so that the switching frequency increases. In this manner, the switching frequency increases with increasing load current, so that efficiency is maintained at a higher level as compared to a constant frequency configuration. The output voltage VOUT also has a ripple voltage and remains centered between approximately 5.9 and 5.95V, while decreasing slightly for larger load current IL.

FIG. 5is a graph diagram plotting efficiency of the an exemplary embodiment of the capacitor voltage divider with hysteretic mode control circuit100with load current for various input levels of the input voltage VIN. As shown, a first curve501is plotted for VIN=8.4V, a second curve503is plotted for VIN=12.6V, and a third curve505is plotted for VIN=19V.FIG. 5illustrates that efficiency increases with increasing level of the input voltage VIN. Yet even at a relatively low VIN level of 8.4V, the efficiency is relatively high up to IL=15 A (e.g., above 95%).

FIG. 6is a block diagram illustrating an exemplary use of the capacitor voltage divider with hysteretic mode control circuit100in a power conversion circuit. An AC input signal is provided to an AC/DC adapter601providing DC voltage to a power switch603and a battery charger605. The battery charger605charges a battery pack607when the AC input signal is available. The power switch603converts the DC input voltage to provide power via a first power bus609with voltage within a range 8.7V-19V. The battery pack607provides power to the power switch603when the AC input signal is not available. A system voltage regulator (VR) is coupled to the power bus609and provides regulated voltage signals at 3.3V and 5V. The capacitor voltage divider with hysteretic mode control circuit100is shown dividing the voltage of the power bus609to a second power bus613with voltage within a half range 4.35V-9.5V. Various devices are coupled to the power bus613, including a central processing unit (CPU)615, a graphics processing unit (GPU)617providing a 5-bit VID (voltage identification) interface, a voltage dual switcher block619providing computer voltage rail levels 1.5V and 1.05V (e.g., used to power memory control hub chip set, front side bus, wireless communications, etc.), and a double data rate (DDR) regulator device621for providing power to DDR memory devices.

A hysteretic mode controller is disclosed which provides a pulse width modulation (PWM) signal for controlling a capacitor voltage divider. The capacitor voltage divider has a flying capacitor and divides an input voltage to provide an output voltage. In one embodiment, the hysteretic mode controller includes an amplifier, a gain circuit and a hysteretic comparator circuit. The amplifier has an input for coupling to the flying capacitor and an output providing a fly voltage. The gain circuit has an input for receiving the input voltage and an output coupled to a reference node providing a reference voltage. The hysteretic comparator circuit has a first input coupled to the output of the amplifier, a second input receiving the reference voltage, and an output for providing the PWM signal.

In one embodiment the gain circuit has a gain between zero and one. In a more specific embodiment the gain circuit has a gain of approximately one-half. The hysteretic comparator circuit compares the reference voltage with a hysteretic voltage window based on the reference voltage. In one embodiment, the hysteretic comparator circuit includes first and second voltage sources, first and second comparators, and a logic circuit. In a more specific embodiment, the first voltage source is coupled to the reference node and provides a positive hysteretic voltage. The second voltage source is coupled to the reference node and provides a negative hysteretic voltage. The first comparator has a first input coupled to the output of the amplifier, a second input receiving the positive hysteretic voltage, and an output. The second comparator has a first input coupled to the output of the amplifier, a second input receiving the negative hysteretic voltage, and an output. The logic circuit has a first input coupled to the output of the first comparator, a second input coupled to the output of the second comparator, and an output providing the PWM signal. The logic circuit may be a set-reset flip-flop having a set input coupled to the output of the second comparator, a reset input coupled to the output of the first comparator, and an output for providing the PWM signal.

A capacitor voltage divider with hysteretic mode control according to another embodiment includes a capacitive voltage divider and a hysteretic mode control circuit. In one embodiment, the capacitor voltage divider includes second and third capacitors, first and second switching circuits, and a switch driver circuit. The second capacitor is coupled between the input node and the output node. The third capacitor is coupled between the output node and a second reference node (e.g., ground). The first switching circuit is coupled between the input node and the output node and forms a first phase node. The second switching circuit is coupled between the output node and the second reference node and forms a second phase node. The switch driver circuit has an input receiving the PWM signal, a first output coupled to the first switching circuit and a second output coupled to the second switching circuit. The flying capacitor is coupled between the first and second phase nodes.

A method of providing a PWM signal to control a capacitor voltage divider, where the capacitor voltage divider has a flying capacitor and divides an input voltage to an output voltage, includes determining the voltage across the flying capacitor and providing a corresponding fly voltage, amplifying the input voltage to provide a reference voltage, and comparing the fly voltage within a hysteretic voltage window based on the reference voltage to provide the PWM signal.

The method may include amplifying the voltage across the flying capacitor using a differential amplifier. The method may include multiplying the input voltage by a gain between zero and one. The method may include adding a first voltage to the reference voltage to provide a positive hysteretic voltage, subtracting a second voltage from the reference voltage to provide a negative hysteretic voltage, where the positive and negative hysteretic voltages determine the hysteretic voltage window. The method may include comparing the fly voltage with the positive hysteretic voltage to provide a first logic signal, comparing the fly voltage with the negative hysteretic voltage to provide a second logic signal, and determining the state of the PWM signal based on the first and second logic signals. The method may include asserting the PWM signal high when the second logic signal is high and asserting the PWM signal low when the first logic signal is high.

Although the present invention has been described in considerable detail with reference to certain preferred versions thereof, other versions and variations are possible and contemplated. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiments as a basis for designing or modifying other structures for providing out the same purposes of the present invention without departing from the spirit and scope of the invention as defined by the following claims.