Graphics processing unit and operating method thereof

An operating method of a graphics processing unit includes: receiving a first read request for texels, detecting whether decompression data associated with each of the texels are present in a first cache, decompressing part of a first texture compression block associated with a first texel among the texels when a result of the detecting indicates decompression data for the first texel is not present in the first cache, to generate first decompression data, and generating first texture data corresponding to the first read request, based on the first decompression data and second decompression present in the first cache.

CROSS-REFERENCE TO RELATED APPLICATIONS

This U.S. non-provisional patent application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2021-0039940 filed on Mar. 26, 2021, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference in its entirety herein.

1. Technical Field

Embodiments of the present disclosure described herein relate to a graphics processing unit and an operating method thereof, and more particularly, relate to a graphics processing unit including a texture processing unit and an operating method thereof.

2. Discussion of Related Art

Three-dimensional graphics application program interface (API) standards include OpenGL, OpenGL ES, and Direct 3. The API standards include a way to perform rendering on each frame of a three-dimensional graphics and to display an image. The rendering of each frame of the three-dimensional graphics requires many computations, thereby causing increased power consumption.

A texture image that is used to determine a color of a pixel in performing rendering may be compressed and stored in a texture cache in compliance with various compression formats such as adaptive scalable texture compression (ASTC). Accordingly, texture images may need to be decompressed when rendering is performed. As a compression ratio of a texture image increases, an algorithm for performing the compression may become more complicated, thereby causing increased power consumption.

SUMMARY

At least one embodiment of the present disclosure provide a graphics processing unit including a cache storing decompressed texture data and a decompressor decompressing at least part of a texture compression block, and an operating method thereof.

According to an embodiment of the present disclosure, a graphics processing unit includes a first cache, a second cache, a controller, and a decompressor. The first cache is configured to store texture compression blocks respectively corresponding to texels. The second cache is configured to store texel data decompressed from the first cache. The controller is configured to receive a first read request for first texels of the texels and determine whether decompressed texel data corresponding to the first texels are present in the second cache. The decompressor is configured to decompress the texture compression blocks stored in the first cache under control of the controller. In response to determining that decompressed texel data corresponding to second texels of the first texels are not present in the second cache, the decompressor decompresses a part corresponding to the second texels from a texture compression block corresponding to the second texels from among the texture compression blocks.

According to an embodiment of the present disclosure, an operating method of a graphics processing unit includes: receiving a first read request for texels, detecting whether decompression data associated with each of the texels are present in a first cache, decompressing part of a first texture compression block associated with a first texel among the texels when a result of the detecting indicates decompression data for the first texel is not present in the first cache, to generate first decompression data, and generating first texture data corresponding to the first read request, based on first decompression data and second decompression data detected to be present in the first cache.

According to an embodiment of the present disclosure, a device includes a processor, and a memory that stores instructions executable by the processor. The instructions, when executed, cause the processor to in response to a first request, detect whether decompression data of texels associated with the first request are present in a first cache, decompress part of a first texture compression block associated with a first texel among the texels when a result of the detect indicates decompression data for the first texel is not present in the first cache, to generate first decompression data, and generate first texture data corresponding to the first request, based on first decompression data and second decompression data detected to be present in the first cache.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Below, embodiments of the present disclosure will be described in detail and clearly to such an extent that one skilled in the art may implement the present disclosure.

Hereinafter, embodiments of the present disclosure will be described in more detail with reference to accompanying drawings. In describing the present disclosure, to make the overall understanding clear, like components/elements will be marked by like reference signs/numerals in the drawings, and thus, additional description will be omitted to avoid redundancy.

FIG.1illustrates a block diagram of a computing system10according to an embodiment of the present disclosure. Referring toFIG.1, the computing system10includes a central processing unit (CPU)1, an external memory2, and a graphics processing unit (GPU)100.

The CPU1may perform various operations necessary for the computing system10to operate. The CPU1may load software, firmware, or a program code stored in the external memory2. The CPU1may store results of the operations in the external memory2or may transmit the results to the GPU100. The CPU1may request the GPU100to process graphics data. For example, the CPU1can offload some or all of the graphics data it would otherwise process to the GPU100for processing.

The external memory2may store data or information necessary for the CPU1or the GPU100to process data. The external memory2may store data processed by the CPU1and the GPU100. The external memory2may store software, firmware, a program code, or instructions that are executable by the CPU1or the GPU100. The external memory2may include a static random access memory (SRAM) or a dynamic random access memory (DRAM).

The GPU100may perform various operations associated with graphics processing by using data transmitted from the CPU1and data stored in the external memory2. The GPU100may include an on-chip memory110and a processor120.

The on-chip memory110may store data that are used frequently by the processor120or are to be used presently by the processor120. The on-chip memory110may include various program codes or instructions executable by the processor120, data that the processor120intends to process, or data processed by the processor120. The on-chip memory110may include a DRAM or an SRAM.

The processor120may perform various operations for processing a graphics present in the external memory2or the on-chip memory110. For example, the processor120may process (or generate) the graphics by executing program codes or instructions present in the external memory2or the on-chip memory110or compiled codes provided from the CPU1.

FIG.2illustrates a block diagram of a GPU200in detail, according to an embodiment of the present disclosure. Referring toFIG.2, the GPU200includes an on-chip memory210, a rasterizer220, a shader core230, a texture processing unit240, a pixel processing unit250, and a tile buffer260. In some embodiments, the processor120ofFIG.1may include the rasterizer220, the shader core230, the texture processing unit240, and the pixel processing unit250or may perform operations to be performed respectively by the components220to250. In an embodiment, each of the components220to250is implemented by a respective a processor.

In an embodiment, the GPU200ofFIG.2is configured to process a three-dimensional graphics by using tile based rendering (TBR). For example, the GPU200may perform the following operations to generate a three-dimensional (3D) graphics corresponding to one frame: 1) rasterize a plurality of tiles segmented by a given size, 2) perform pixel shading, 3) perform texture processing, and 4) process pixels corresponding to processed tiles. For example, the 3D graphics or image data may be divided into a plurality of tiles of the given size. The rasterize may include performing a rasterization that converts a given one of the tiles into a raster image. The 3D graphics may be in a vector graphics format. The raster image may include a series of pixels, dots, or lines. For example, the pixel shading may be performed on first pixels of the raster image to generate second pixels, the texture processing may be performed on the second pixels to generate third pixels, and then the third pixels from may be processed to generate a processed tile. That is, a plurality of tiles may be processed through the rasterizer220, the shader core230, and the pixel processing unit250, and the processed tiles may be stored in the tile buffer260. The GPU200may process all tiles constituting one frame in parallel by using a plurality of channels each composed of the rasterizer220, the shader core230, the texture processing unit240, and the pixel processing unit250. When a plurality of tiles corresponding to one frame are processed, the GPU200may transmit processing results stored in the tile buffer260to a frame buffer (not illustrated) present in the external memory2. The GPU200may store a result, which is frequently used or which is to be used next, from among the processing results in the on-chip memory210(or may store data associated with the result therein).

The shader core230may include a pixel shader. In an embodiment, the pixel shader combines constant variables, texture data, interpolated per-vertex values, and other data to produce per-pixel outputs. The shader core230may further include a vertex shader or may be implemented with an integrated shader where the pixel shader and the vertex shader are integrated. In an embodiment, the vertex shader is a programmable stage in a rendering pipeline that handles the processing of individual vertices. In an embodiment where the shader core230performs a function of the vertex shader, the shader core230may generate a primitive indicating an object that is to be transferred to the rasterizer220.

The rasterizer220may perform rasterization on a primitive generated from the vertex shader through a geometric transformation process.

The shader core230may receive the rasterized primitive from the rasterizer220. The shader core230may perform pixel shading on the rasterized primitive. For example, to determine colors of all pixels constituting a tile, the shader core230may perform pixel shading on tiles including a fragment of the primitive generated through the rasterization. To generate a three-dimensional graphics being stereoscopic and realistic in the pixel shading process, the shader core230may use a pixel value generated by using a texture.

The shader core230may request a pixel value corresponding to a desired pixel from the texture processing unit240. In response to the request of the shader core230, the texture processing unit240may provide the shader core230with a pixel value generated by processing a texture prepared (or stored) in advance. A texture may be stored in an internal space (e.g., a texture cache242ofFIG.4) of the texture processing unit240, an external space of the texture processing unit240, the on-chip memory210, or an external memory of the GPU200(e.g., the external memory2ofFIG.1). In an embodiment where a texture to be used to generate the pixel value requested from the shader core230is absent from the texture processing unit240, the texture processing unit240may fetch the texture from the external space (e.g., the on-chip memory210) of the texture processing unit240or the external memory2and may use the fetched texture. If the texture is present in the internal space, the texture is not considered absent, and thus need not be fetched.

The pixel processing unit250may perform a depth test on pixels corresponding to the same location in one tile and may determine a pixel value to be finally displayed in a display device (not illustrated). In an embodiment, the depth test is used to check visibility at the fragment (pixel) level, and if multiple pixels are on the same line of sight, the color of the pixel closest to the camera will override all the other pixels. As in the above description, the pixel processing unit250may determine all pixel values corresponding to one tile. The pixel processing unit250may transmit the determined pixel values to the tile buffer260.

The tile buffer260may store all the pixel values corresponding to one tile received from the pixel processing unit250. When graphics processing associated with all tiles constituting one frame is completed, a processing result that is stored in the tile buffer260may be transmitted to the frame buffer of the external memory2.

FIG.3is a flowchart illustrating a process in which a graphics processing unit processes a three-dimensional graphics, according to an embodiment of the present disclosure. The process of processing a three-dimensional graphics may be divided into three phases: 1) geometric transformation, 2) rasterization, and 3) pixel shading. The three phases will be described in more detail with reference toFIG.3. Referring toFIG.3, a three-dimensional (3D) graphics may be processed by the GPU200ofFIG.2through operation11to operation18.

In operation11, vertices associated with an image are generated. The vertices are generated to indicate objects included in a 3D graphics of an image. The vertices may be points in 3D space having 3D coordinates such as x, y, and z coordinates.

In operation12, the generated vertices are shaded. A vertex shader may perform shading on the vertices by specifying locations (e.g., three-dimensional locations or three-dimensional coordinates) of the vertices generated in operation11.

In operation13, primitives are generated based on the generated vertices or the generated vertices that were shaded. A primitive may mean a point, a line, a polygon, etc. formed by using at least one of a plurality of vertices. For example, the primitive may be a triangle that is formed by connecting at least three vertices. For example, a triangle may be formed by connecting at least three of the vertices that were shaded.

In operation14, the primitives are rasterized. To rasterize a primitive may mean to divide primitives into fragments. A fragment may be a basic unit for performing graphics processing on a primitive. Since a primitive includes only information about a vertex or a collection of related vertices (e.g., connected to form a certain polygon or line), processing for the 3D graphics may be possible by generating a fragment between a vertex and a vertex in the rasterization process. In an embodiment, rasterizing a primitive means to convert a primitive into pixels.

In operation15, at least one pixel is shaded based on a result (e.g., generated fragments) of the rasterization. Fragments that are generated by the rasterization and constitute a primitive may include one or more of pixels of a tile. The terms “fragment” and “pixel” may be interchangeably used in some cases. For example, a pixel shader may be referred to as a “fragment shader”. In general, a basic unit of graphics processing associated with a primitive may be referred to as a “fragment”, and afterwards, a basic unit of graphics processing associated with pixel shading may be referred to as a “pixel”. A color of a pixel may be determined in the pixel shading process.

In operation16, texturing for determining a color of a pixel is performed. Texturing refers to a process of determining a color of a pixel by using an image prepared in advance, that is, a texture. To express the appearance of various colors and patterns in the real world, calculating and determining a color of each pixel causes a considerable increase in both the amount of data computation required for graphics processing and a graphics processing time. For this reason, the color of the pixel may be determined by using a texture prepared in advance. For example, a surface color of an object may be stored in advance as a separate two-dimensional (2D) image being a texture. Afterwards, the color of the pixel may be determined by expanding or reducing the stored texture depending on a location and a size of an object on the screen or by mixing texel values by using textures having various resolutions.

For example, pixel values that are generated by using a previously prepared (or desired) texture can be used to process the 3D graphics more quickly in the pixel shading process. In an embodiment, to adaptively cope with a size of a 3D object, a plurality of textures having different resolutions are prepared in advance and may be combined to generate a pixel value. In this embodiment, textures that are prepared in advance and have different resolutions may be referred to as a “mipmap”. For example, to generate pixel values of an object having an intermediate resolution of two mipmaps prepared in advance, texel values of a location corresponding to the object may be extracted from the two mipmaps and may then be filtered. As such, pixel values constituting the object may be generated. In an embodiment, a texel (e.g., a texture element) is a fundamental unit of a texture map. A texture or texture image may be represented by an array of texels. A texel may be a pixel within a texture image. In an embodiment, a texel represents a smallest graphical element in 2D texture mapping to “wallpaper” the rendering of a 3D object to create the impression of a textured surface.

In operation17, testing and mixing are performed. Pixel values corresponding to one tile may be determined by determining pixel values to be finally displayed through a process of performing a depth test on pixels corresponding to the same location in the tile. A plurality of tiles generated through the above process may be mixed to generate a 3D graphics corresponding to one frame.

In operation18, the frame generated through operation11to operation17is stored in the frame buffer. A frame stored in the frame buffer may be displayed through a display device.

Referring again toFIGS.1and2, a texture (or a texture image) may be stored in the external memory2ofFIG.1in the form of compression (e.g., in a compressed form), or a frame generated by the GPU200may be stored in the frame buffer present in the external memory2. The external memory2may store a frame, which is generated as a rendering result of the GPU200, in the frame buffer of the external memory2. The external memory2may store a frame generated as a rendering result of the GPU200in the frame buffer of the external memory2. The external memory2may transmit a texture (or a compressed texture) to the texture processing unit240in response to a request of the texture processing unit240.

However, it may be physically impossible to store all textures for various objects and mipmaps respectively corresponding to the textures in a given space of the texture processing unit240. In rendering for the 3D graphics, to minimize a space necessary to store textures and to efficiently transmit a texture, textures may be generally stored or transmitted in the form of compression. One texture may be divided into a plurality of texture blocks having the same size (or including an equal number of texels), and each of the texture blocks may be compressed to an equal number of bits.

FIG.4illustrates a block diagram of the texture processing unit240in detail, according to an embodiment of the present disclosure. Referring toFIG.4, the texture processing unit240includes a controller241(e.g., a control circuit), the texture cache242, a decompressor243(e.g., a logic circuit), a post decompression cache (PDC)444, a texture merge unit245(e.g., a logic circuit), and a texture filter246(e.g., a logic circuit).

The controller241may control operations of the components of the texture processing unit240. For example, the controller241may perform various operations that are used to control the texture processing unit240or may transmit control signals to the remaining components of the texture processing unit240.

The controller241may receive a request (or a read request) for texture processing from the shader core230. For example, the shader core230may request a value of at least one texel corresponding to at least one pixel (e.g., at least one quad (i.e., a group of four pixels)) from the texture processing unit240. For example, the request for texture processing may include texture image information indicating a texture block in which texels corresponding to pixels to be processed by the shader core230are included (or information indicating a level of a mipmap texture in which texels corresponding to pixels to be processed by the shader core230are included), and location (or coordinate) information of the texels on the texture block. In response to the request of the shader core230, the controller241may read data present in the texture cache242or the PDC244and may generate signals for controlling the decompressor243, the texture merge unit245, and the texture filter246.

The controller241may determine whether it needs to decompress data necessary for texture processing, based on the information provided from the shader core230. For example, the controller241may determine whether data of texels requested by the shader core230(e.g., decompressed values corresponding to the texels requested by the shader core230) are present in the PDC244. The controller241may calculate one or more addresses corresponding to the data of the texels requested by the shader core230, based on the information provided from the shader core230. The controller241may compare the calculated addresses with addresses corresponding to data previously stored in the PDC244.

When at least one of the calculated addresses matches with at least one of the addresses of the data previously stored in the PDC244, at least part of the data of the texels requested by the shader core230may be determined as being present in the PDC244(i.e., may be determined as a cache hit). The controller241may read at least part of data of texels corresponding to the calculated addresses from the PDC244.

When the calculated addresses do not match with the addresses of the data previously stored in the PDC244, at least part of the data of the texels requested by the shader core230may be determined as being absent from the PDC244.

The controller241may determine that there is a need to decompress texels determined as data thereof when they are absent from the PDC244. The controller241may calculate an address and a tag(s) of a texture compression block(s) corresponding to the texels targeted for decompression, based on the information provided from the shader core230. The controller241may determine whether a texture compression block(s) corresponding to texel data absent from the PDC244is present in the texture cache242, based on the calculated tag. For example, the controller241may search the texture cache242for the calculated tag(s). In an embodiment, the tag is stored data including information identifying a given texture compression block and indicating whether the given texture compression block corresponds to texel data absent from the PDC244but present in the texture cache242.

When the calculated tag(s) is present in the texture cache242, at least part of the texture compression block(s) may be determined as being present in the texture cache242(i.e., may be determined as a cache hit), and the controller241may read the at least part of the texture compression block(s) corresponding to the tag(s) from the texture cache242.

When the calculated tag(s) is absent from the texture cache242, at least part of the texture compression block(s) may be determined as being absent from the texture cache242(i.e., may be determined as a cache miss), and the controller241may read the texture compression block(s), which is absent from the texture cache242, from the on-chip memory210or the external memory2based on the address and may store the texture compression block(s) in the texture cache242together with the tag(s). The controller241may read at least part of a texture compression block(s) corresponding to texels requiring decompression from the texture cache242and may transmit the at least part to the decompressor243.

The texture cache242may store a texture to be used in 3D graphics processing. In an embodiment, the texture cache242stores a texture (e.g., a texture compression block) in the form of compression. For example, the texture cache242may store a compressed texture. Also, the texture cache242may receive and store various resolutions of mipmaps for one texture from the external memory2. The texture cache242may include one or more cache lines or rows each including at least one texture compression block. In response to a request of the controller241, the texture cache242may provide (or output) at least part of data determined as a cache hit to the controller241.

The decompressor243may decompress at least part of a texture compression block under control of the controller241. The decompressor243may include a decoder (e.g., a decoder circuit) that decodes a texture compression block. In response to a request of the controller241, the decompressor243may extract compression parameters to be used in a compression process from at least part of a texture compression block received from the controller241and may generate corresponding texel data from the extracted compression parameters. To generate texel data, the decompressor243may find a specific value based on the compression parameters or may obtain a specific value by performing various operations including interpolation. The decompressor243may decompress at least part of a texture block and may transmit decompressed texel data to the controller241. The decompressor243may store at least part of the decompressed texel data in the PDC244under control of the controller241.

The PDC244may store texel data decompressed by the decompressor243. For example, texel data that are determined as frequently used or as having a high probability of being used again may be stored in the PDC244under control of the controller241. The controller241may determine whether to store decompressed texel data in the PDC244, based on requests received from the shader core230. For example, the controller241may replace data present in the PDC244by using algorithms such as FIFO (First-In First-Out), LRU (Least Recently Used), or LFU (Least Frequently Used). The PDC244may provide (or output) texel data corresponding to a request of the controller241to the controller241.

Under control of the controller241, the texture merge unit245may merge texel data read from the PDC244and texel data decompressed by the decompressor243. For example, the texture merge unit245may merge texels as a texel block corresponding to a request from the shader core230. For example, a texel block includes a plurality of texels, and when first texels of a given requested texel block are located in the PDC244and second texels of the given requested texel block have just been decompressed by the decompressor243, the texture merge unit245can combine the first texels and the second texels to generate the given requested texel block.

The texture filter246may filter a texel block merged by the texture merge unit245. The texture filter246may obtain a color value corresponding to one pixel by mixing texel data of a texel block. For example, the texture filter246may filter the texel data of the texel block by performing operations such as point sampling, bilinear filtering, trilinear filtering, and anisotropic filtering. The texel data filtered by the texture filter246may be transmitted to the shader core230.

FIG.5illustrates a block diagram of texture compression blocks stored in the texture cache242, according to an embodiment of the present disclosure. One texture may include a plurality of texels and may be divided into texels of a block unit, for example, texture blocks, and each texture block may be compressed. In the embodiment illustrated inFIG.5, a size of a texture block is illustrated as 4*4 by way of example, but the present disclosure is not limited thereto. For example, a size of a texture block may be 3*3 or 12*12.

In the embodiment illustrated inFIG.5, a first texture includes texels TX1to TX32. The first texture may be divided into 4*4 texture blocks each including 16 texels. For example, the first texture may include a first texture block including the texels TX1to TX16and a second texture block including the texels TX17to TX32.

The first texture block and the second texture block may be compressed in compliance with various compression formats such as ASTC (Adaptive Scalable Texture Compression), 3STC (3S Texture Compression), and ETC (Ericsson Texture Compression). The first texture block may be compressed to a first texture compression block TCB1, and the second texture block may be compressed to a second texture compression block TCB2. The first texture compression block TCB1and the second texture compression block TCB2may be stored in the texture cache242.

FIG.6illustrates an operation of a texture processing unit corresponding to a first read request, according to an embodiment of the present disclosure. Referring toFIGS.4to6, the texture processing unit240ofFIG.4receives a first read request for the texels TX1to TX16from the shader core230. The first read request may include information indicating that the texels TX1to TX16correspond to the first texture block of the first texture (or a base address associated with a texture image), and coordinates of the texels TX1to TX16on a texture space (or the first texture). In the embodiment illustrated inFIG.6, the texture processing unit240may receive a read request for 16 texels within one cycle, but embodiments of the present disclosure is not limited thereto.

In response to the first read request, the controller241may determine whether data of the texels TX1to TX16are present in the PDC244and may determine whether to perform decompression on any texels. When the data of the texels TX1to TX16are absent from the PDC244, the controller241may determine that it needs to perform decompression on the texels TX1to TX16. In the embodiment illustrated inFIG.6, it has been assumed that the data of the texels TX1to TX16are absent from the PDC244.

The controller241may determine whether the first texture compression block TCB1including the texels TX1to TX16is present in the texture cache242. When it is determined that the first texture compression block TCB1including the texels TX1to TX16is present in the texture cache242, the controller241may read the first texture compression block TCB1from the texture cache242and may request decompression from the decompressor243. Unlike the embodiment illustrated inFIG.6, when it is determined that the first texture compression block TCB1is absent from the texture cache242, the controller241may read the first texture compression block TCB1from the on-chip memory210or the external memory2and may request decompression from the decompressor243.

The decompressor243may decompress the first texture compression block TCB1and may generate the data of the texels TX1to TX16. Under control of the controller241, the decompressor243may store the data of the texels TX1to TX16in the PDC244. Under control of the controller241, the data of the texels TX1to TX16generated by the decompressor243may be transmitted to the texture filter246, and the texture filter246may filter the data of the texels TX1to TX16and may provide a result of the filtering to the shader core230.

FIG.7illustrates an operation of a texture processing unit corresponding to a second read request, according to an embodiment of the present disclosure. Referring toFIGS.4to7, the texture processing unit240ofFIG.4receives a second read request for the texels TX9to TX24from the shader core230. As in the first read request, the second read request may include information indicating that the texels TX9to TX16correspond to the first texture block of the first texture and the texels TX17to TX24correspond to the second texture block of the second texture, and coordinates of the texels TX9to TX24on a texture space.

The data of the texels TX1to TX16decompressed in response to the first read request may be present in one (or more) cache line of the PDC244. For convenience of description, the texels TX1to TX16are illustrated as being present in the PDC244in the form of a block, but embodiments of the present disclosure are not limited thereto.

In response to the second read request, the controller241may determine whether data of the texels TX9to TX24are present in the PDC244and may determine whether to perform decompression on any texels. Because the data of the texels TX9to TX16are stored according to the first read request, the controller241does not perform decompression on the texels TX9to TX16, the data of which are present in the PDC244, and may determine that there is a need to perform decompression on the texels TX17to TX24, the data of which are absent from the PDC244.

The controller241may determine whether the second texture compression block TCB2including the texels TX17to TX24is present in the texture cache242. When it is determined that the second texture compression block TCB2is present in the texture cache242, the controller241may read the second texture compression block TCB2from the texture cache242and may request the decompressor243to decompress the texels TX17to TX24.

Under control of the controller241, the decompressor243may decompress only a part of the second texture compression block TCB2and may generate the data of the texels TX17to TX24. In other words, the decompressor243may decode only a part of the second texture compression block TCB2, which corresponds to the texels TX17to TX24, and may generate the data of the texels TX17to TX24. Under control of the controller241, the decompressor243may store the data of the texels TX17to TX24in the PDC244.

Under control of the controller241, the texture merge unit245may merge the data of the texels TX9to TX16stored (or present) in the PDC244and the data of the texels TX17to TX24generated by the decompressor243. For example, the texture merge unit245may generate a 4*4 texel block by merging the data of the texels TX9to TX16stored (or present) in the PDC244and the data of the texels TX17to TX24generated by the decompressor243. Under control of the controller241, the texture filter246may filter a merged result of the texture filter246so as to be provided to the shader core230.

In an embodiment, consecutive read requests from the shader core230may require duplicated texel data. For example, the shader core230may consecutively transmit read requests for adjacent quads to the texture processing unit240and texels associated with the adjacent quads may be at least partially duplicated. The texture processing unit240may store data, which are determined as being frequently requested or to be again used, from among the decompressed texel data in the PDC244in response to a request of the shader core230. For example, the data of the texels TX1to TX16decompressed in response to the first read request may be stored in the PDC244, and afterwards, a part of the stored texel data may be reused in response to the second read request following the first read request.

As texel data stored in the PDC244are reused, the texture processing unit240may decompress only at least part of one texture compression block present in the texture cache242. For example, without decompressing the whole texture compression block corresponding to one cache line of the texture cache242, in response to a read request of the shader core230, the texture processing unit240may generate and filter appropriate texel data so as to be provided to the shader core230. Since decompressed texel data are stored in the PDC244, power consumption of the texture processing unit240due to decompression compared to the occupied area may be reduced.

FIG.8is a flowchart illustrating an operating method of the texture processing unit240according to an embodiment of the present disclosure. Referring toFIGS.4and8, the texture processing unit240ofFIG.4perform operation S101to operation S104.

In operation S101, the texture processing unit240receives a read request from the shader core230. For example, the texture processing unit240may receive a request for texture processing, such as the first read request ofFIG.6or the second read request ofFIG.7, from the shader core230.

In operation S102, the texture processing unit240determines whether texels (or data of the texels) requested in operation S101are present in the PDC244. In an embodiment, the texture processing unit240calculates an address corresponding to a first texel of the texels requested in operation S101and determines whether the address corresponding to the first texel matches with an address of data previously stored in the PDC244to determine whether the first texel is present in the PDC244.

In operation S103, the texture processing unit240determines whether to perform decompression on any texel(s), based on a determination result in operation S102. For example, the texture processing unit240may determine that the texels absent from the PDC244, are targeted for decompression.

In operation S104, the texture processing unit240generates texture data corresponding to the read request in operation S101, based on decompressed texel data stored in the PDC244and texture compression block(s) stored in the texture cache242. For example, in response to determining that decompression for a second texel of the texels requested in operation S101is needed, the texture processing unit240may decompress a part associated with the second texel from a texture compression block corresponding to the second texel.

In an embodiment, the processor120ofFIG.1performs operation S101to operation S104by executing instructions stored in the external memory2or the on-chip memory110.

FIG.9is a flowchart illustrating an operating method of the texture processing unit240according to an embodiment of the present disclosure. Referring toFIGS.4and9, the texture processing unit240ofFIG.4may perform operation S201to operation S208.

In operation S201, the texture processing unit240receives a read request from the shader core230. In operation S202, the texture processing unit240determines whether data of texels requested from the shader core230are present in the PDC244.

The texture processing unit240may perform operation S203and operation S204on at least one texel, the data of which are absent from the PDC244. In operation S203, the texture processing unit240reads a texture compression block(s) including the at least one texel from the texture cache242. When the corresponding texture compression block(s) is absent from the texture cache242, the texture processing unit240may read the corresponding texture compression block(s) from the on-chip memory210or the external memory2and may store the texture compression block thus read in the texture cache242.

In operation S204, the texture processing unit240decompresses at least part of the texture compression block(s) read in operation S203. For example, the texture processing unit240may generate data of the at least one texel by decompressing only a part of the texture compression block(s), which corresponds to the at least one texel. In an embodiment, the texture processing unit240may store the data of the at least one texel thus generated in the PDC244.

The texture processing unit240may perform operation S205on the texel(s), the data of which are present in the PDC244. In operation S205, the texture processing unit240reads data of a texel(s), the data of which are determined as present in the PDC244, from the PDC244. For example, the texture processing unit240may read decompressed texel data from the PDC244.

In operation S206, the texture processing unit240merges the texel data decompressed in operation S204and the decompressed texel data read in operation S205. In operation S207, the texture processing unit240performs texture filtering on the texel data merged in operation S206. In operation S208, the texture processing unit240transmits a result of operation S207, for example, a result of the texture filtering to the shader core230.

In an embodiment, the processor120ofFIG.1performs operation S201to operation S206by executing instructions stored in the external memory2or the on-chip memory110.

A graphics processing unit according to an embodiment of the present disclosure includes a cache storing decompressed texel data and a decompressor decompressing at least part of a texture compression block (e.g., a compressed texture block). The graphics processing unit may perform decompression only on a texel, the data of which is absent in the cache. As such, power consumption of the graphics processing unit may be reduced.