Power semiconductor device including a double metal contact

A power semiconductor device that includes a stack of a thin metal layer and a thick metal layer over the active region thereof, and a method for the fabrication thereof.

FIELD OF INVENTION

The present invention relates to power semiconductor devices and a method for the fabrication thereof.

BACKGROUND OF THE INVENTION

Conventional power MOSFETs use a thick (4 to 10 μm) top layer of metalization for connection to the source regions thereof due to the large currents that the metal has to conduct during the operation of the device. Because of the thickness of the top metal, wet etching is used to pattern the same during fabrication. The use of wet etching requires the metal design rules to be large. Therefore, multiple gate buses in a conventional power MOSFET consume a large area of the semiconductor die, which could otherwise be used for the active part of the device.

When a power MOSFET is configured for flip-mounting onto conductive pads using solder or the like additional issues further lead to the inefficient use of semiconductor area. For example, the gate pad required for flip-mounting is large compared with a wire-bonded device, which wastes more semiconductor area that could be used for the active region of the device. In addition, the layout of a large source pad required for flip-mounting may restrict the use of multiple gate buses.

SUMMARY OF THE INVENTION

In a power semiconductor according to the present invention the thick metal layer in a conventional device is replaced by a thin metal layer (e.g. 1-2 μm) which can be dry etched. The thin metal layer is then patterned to obtain a metallic gate bus that is then preferably encapsulated in a hermetic seal, followed by formation of a thick stress relieving buffer body. The buffer body allows the deposition of a thick (e.g. 4-20 μm) second metal layer to be added by preventing stress-related cracking of the hermetic seal during reliability testing such as temperature cycling. The thick second metal layer, which is thick enough to carry current as required by a power semiconductor device, can be then wet etched.

Advantageously, the thick second metal layer can be thicker than conventional front metal bodies in that no gate buses are required to be patterned out of the same.

DETAILED DESCRIPTION OF THE FIGURES

Referring toFIGS. 1A and 1B, a power semiconductor device according to the present invention is preferably a power MOSFET which includes a semiconductor body10having an active region formed on one surface thereof. The active region includes a drift region12of one conductivity (e.g. N-type), a base region14of another conductivity (e.g. P-type), a plurality of gate trenches formed inside semiconductor body10and extending from the top surface thereof through base region14into at least drift region12, an insulated gate received inside each gate trench16(each insulated gate including a gate dielectric18such as SiO2along at least the sidewalls of a respective trench16and a gate electrode20formed with polysilicon or the like), source regions22formed inside base region14adjacent respective trenches16, high conductivity contact regions24of the same conductivity type as base region14formed therein between respective source regions22, a first metal (e.g. aluminum) layer26disposed over and coupled to source regions22and high conductivity contact regions24, a metallic gate bus28disposed over the top surface of semiconductor body10lateral to and spaced from first metal layer26, buffer body30disposed over metallic gate bus28and the space between gate bus28and first metal layer26, and a second metal (e.g. aluminum) layer disposed over first metal layer26and extending over buffer layer30. Note that buffer layer30may reside over a hermetic sealant body38. Note further that preferably semiconductor body10resides on a semiconductor substrate44of the same conductivity to which a drain contact46is ohmically coupled. In addition, insulation interlayers23are provided to insulate each gate electrode20from first metal layer26.

Metallic gate bus28is preferably disposed over and ohmically coupled to a polysilicon gate bus34which is connected to gate electrodes20. Polysilicon gate bus34is disposed over an insulation body36(e.g. SiO2), which is atop semiconductor body10to insulate polysilicon gate bus34from semiconductor body10. Metallic gate bus28is coupled to a metallic gate pad29(FIG. 1A) somewhere over body10, gate pad29serving as a pad for external connection. Note that second metal body32also serves as a source contact pad for external connection. Preferably, second metal layer32and the gate pad are configured for flip-mounting onto a conductive pad of a circuit board using a conductive adhesive (e.g. solder or the like).

Referring toFIG. 1C, in an alternative embodiment, polysilicon gate bus34resides inside an insulated trench16, and metallic gate bus28makes connection to polysilicon gate bus34preferably inside trench16. Note that insulation body36insulates metallic gate bus from the semiconductor body therebelow.

Preferably, first metal layer26and metallic gate bus28are less than 2 microns thick, while second metal layer32is between 4 to 20 microns thick. Furthermore, buffer body30is made of polyimide, while hermetic sealant body38is a stack including a layer of photo silicate glass40(PSG), and a silicon nitride layer42between PSG40and buffer body30.

Referring next toFIGS. 2A-2B, a device according to the present invention is fabricated by first forming the active region of the device up until the deposition of first metal layer26(FIG. 2A). Thereafter, a layer of metal (e.g. aluminum) for forming first metal layer26is deposited atop at least the active region of the device including polysilicon gate bus34. The metal layer so deposited may be less than two microns thick (e.g. 1-2 microns). The metal layer for forming first metal layer26is then patterned using dry etching or a similarly accurate etching process in order to obtain metallic gate bus28that is spaced and lateral first metal layer26. Note that in one embodiment, metallic gate bus28may be 9 microns wide and may be spaced from first metal layer26by a gap of about 2.5 microns.

A layer of PSG40is then deposited followed by the deposition of a layer of silicon nitride42, both layers covering first metal layer26, metallic gate bus28and the space between gate bus28and first metal layer26(seeFIG. 2C). Then, buffer body30(e.g. polyimide body) is formed over metallic gate bus28and the space between metallic gate bus28and first metal layer26using any suitable method (seeFIG. 2D). Next, PSG40and silicon nitride42are removed from areas not covered by buffer body30. Note that PSG40and silicon nitride42under buffer body30preferably hermetically seal metallic gate bus28(seeFIG. 2E). Thereafter, second metal layer32which can be preferably between 4 to 20 microns thick is deposited followed by deposition of drain contact46to obtain a device according to the present invention as depicted byFIG. 1. Note that second metal layer32is patterned to obtain gate pad29(FIG. 1A), which is preferably coupled to one or more metallic gate buses28through an insulated via31as schematically illustrated byFIG. 1A. Optionally, solderable bodies may be formed on all contacts including source, drain and gate contacts. Solderable bodies can have any pattern required by packaging.

The following are some of the advantages of having two metal layers according to the present invention particularly, but not limited to, on low voltage power MOSFETs.

Thus, the use of two metal layers according to the present invention allows for better active area usage by allowing the area under the gate pad to be utilized for active cells, which may be especially important for flip-mountable devices that require larger gate pads and allowing large shrinkage in the metal space design rules.

A device according to the present invention may also exhibit lower Rdson resulting from a lower metal spreading resistance due to the thick metal stack of the first and second metal layers. For example, 10% reduction in overall silicon RDson has been shown possible.

A device according to the present invention may further exhibit lower controlled Rg because it can include multiple gate buses (not normally feasible in flip-mountable devices that require large source contacts) in the first metal layer that do not consume much active area due to the tighter design rules

Note that although in the preferred embodiment polyimide is used to form buffer body30other materials may be used without deviating from the scope and spirit of the present invention. For example, other organic films such as BCB, or even a thick planarised hard dielectric body, such as a stack of TEOS/SOG/TEOS, can be used instead of polyimide.

The seal provided over the metallic gate bus also contributes further to the reliability of the device.