Composite bridge die-to-die interconnects for integrated-circuit packages

Disclosed embodiments include composite-bridge die-to-die interconnects that are on a die side of an integrated-circuit package substrate and that contacts two IC dice and a passive device that is in a molding material, where the molding material also contacts the two IC dice.

PRIORITY APPLICATION

This application claims the benefit of priority to Malaysian Application Serial Number PI2019007401, filed Dec. 11, 2019, which is incorporated herein by reference in its entirety.

FIELD

This disclosure relates to power delivery for integrated-circuit device packages.

BACKGROUND

Integration of multiple integrated-circuit chips within a package, for example multi-chip package (MCP) integrated-circuit devices with high interconnect density between chips has power-delivery issues such as undesired inductance loops and impedance peak profiles.

DETAILED DESCRIPTION

Disclosed embodiments include composite bridge die-to-die interconnects that are assembled to the die sides of integrated circuit (IC) package substrates, where passive devices are located in the molding layer between die-side mounted integrated-circuit (IC) dice. Power-delivery networks (PDNs) are facilitated where passive devices such as decoupling capacitors are located in the molding layer with IC dice and that are assembled to the composite bridge die-to-die interconnects. Such passive-device interconnects, facilitate decoupling power-delivery issues that are faster by the proximate location of the passive devices. In an embodiment, the capacitor is a multi-layer ceramic capacitor. In an embodiment, the capacitor is a silicon capacitor.

Ball-grid array densities are facilitated for input-output (I/O) density changes where keep-out-zone issues are addressed. Location of the passive devices, closer to the integrated-circuit dice, relieves integrated-circuit package substrate real estate issues to increase interconnect densities.

Power integrity of electrical performance is achieved by reduced package inductance looping. Decoupling capacitors are directly coupled to power (Vcc) rails and to ground reference voltage (Vss), which lowers power delivery network impedance (ZPDN) and jitter behaviors.

FIG.1Ais a cross-section elevation101during assembly of a composite bridge die-to-die interconnect that becomes part of an integrated-circuit package according to several embodiments. The vertical orientation is inverted, compared to the application of composite bridge die-to-die interconnects as are further disclosed. (See, e.g.FIG.1).

A first integrated-circuit (IC) die10and a subsequent IC die20are being seated on a carrier110, along with a passive device112according to an embodiment. The first IC die10includes an active layer and metallization9, that includes transistors and other active devices fabricated in semiconductive material. Similarly, the subsequent IC die20includes an active layer and metallization19.

FIG.1Bis a cross-section elevation102of the assembly101depicted inFIG.1Aafter further assembly according to an embodiment. A mask114, such as a dry-film resist (DFR)114has been patterned over portions of the first and subsequent IC dice10and20, and the DFR covers larger, package-connect bond pads116and116′ and leaves exposed, composite-bridge bond pads118and118′, respectively, for further connection to the composite-bridge die-to-die interconnect132(seeFIG.1H).

FIG.1Cis a cross-section elevation103of the assembly102depicted inFIG.1Bafter further processing according to an embodiment. A molding layer120is filled into spaces between the first and subsequent IC dice10and20, such that the passive device112is located in the molding layer between the first and subsequent IC dice10and20. The molding layer120also covers the composite-bridge bond pads118and118′ in preparation for opening contact corridors and forming interconnect vias. The composite-bridge bond pads118and118′, make a tighter bump-pitch geometry that is facilitated by the composite-bridge die-to-die interconnect embodiments.

FIG.1Dis a cross-section elevation104of the assembly103depicted inFIG.1Cafter further processing according to an embodiment. Patterning of the molding layer120has been accomplished, to open contact corridors122to the composite-bridge bond pads118and118′. Patterning of the molding layer120has also been accomplished, in the case of a capacitor passive device120, such as a decoupling capacitor120, to open contact corridors124to respective anode and cathode contacts. In an embodiment, a laser-drilling technique is done to open the contact corridors122and124. In an embodiment, a photolithographic technique is done to open the contact corridors122and124, such as patterning an etching through a mask. In an embodiment, laser drilling is used as well as photolithographic processing.

FIG.1Eis a cross-section elevation105of the assembly104depicted inFIG.1Dafter further processing according to an embodiment. Composite-bridge contacts126and126′, fill the contact corridors122(seeFIG.1D) such as by an electroplating technique, followed by a directional etch to remove material from the upper surfaces of the molding layer120. Similarly, passive-device contacts128are simultaneously filled into contact corridors124to contact the electrodes of the passive device112.

In an embodiment, lateral interconnects130and130′ (first130and subsequent130′) couple the passive device112to composite-bridge contacts126and126′. Patterning of the molding layer120has been accomplished, to open contact corridors122to the composite-bridge bond pads118and118′. Patterning of the molding layer120has also been accomplished, in the case of a capacitor passive device112, to couple the passive device112to composite-bridge bond pads118and118′. In an embodiment, the traces130and130′ are simultaneously formed with the contacts126and128, by plating the contacts and the traces, followed by masking a directional etch at the upper surface of the molding material120, followed by removing the mask to reveal the traces130and130′.

FIG.1Fis a cross-section elevation of a composite-bridge die-to-die interconnect132in an integrated-circuit apparatus106after further processing of structures depicted inFIG.1Eaccording to an embodiment. The composite-bridge die-to-die interconnect132incudes the contacts126and126′, the passive-device contacts128and the lateral interconnects130and130′, along with conductive traces134(die-to-die trace134) that bypass the passive device112. These structures couple the passive device112to the composite-bridge die-to-die interconnect132, and there are interlayer dielectrics136and138by way of non-limiting example, that support e.g. the conductive trace134.

FIG.1Gis a cross-section elevation of the composite-bridge die-to-die interconnect132in the integrated-circuit apparatus106depicted inFIG.1Fafter further processing of structures according to an embodiment. The IC apparatus107has further structure assembled to the composite-bridge die-to-die interconnect132. These include interlayer dielectric layers (ILDs) such as first ILD136and a subsequent ILD138. Further structures include a conductive shield140that will seat upon a die side of an integrated-circuit package substrate. As illustrated, the conductive shield140projects a footprint onto the composite-bridge bond pads118and118′, and onto the passive device112. The conductive shield140provides protection from electromagnetic coupling between the several conductive traces, e.g.130,130′ and134and any conductive traces and vias that are close by in an integrated-circuit package substrate (see, e.g. the IC package substrate142inFIG.1H).

FIG.1His a cross-section elevation of the composite-bridge die-to-die interconnect132as part of the integrated-circuit apparatus107depicted inFIG.1Gafter further processing of structures according to an embodiment.

An integrated-circuit package108includes the IC dice10and20, the composite-bridge die-to-die interconnect132that couples the IC dice10and20, and the assembly has been inverted and is being seated onto an IC package substrate142on a die side143according to an embodiment. The composite-bridge die-to-die interconnect132, exposes package-connect bond pads116and116′ on each of the first and subsequent IC dice10and20, and the composite-bridge die-to-die interconnect132, contacts the composite-bridge bond pads118and118′.

The larger bond pads116and116′ are being fiducial-connected to die-side electrical bumps117and117′ respectively, that may either begin on the IC package die side143, or may be pre-attached to the respective larger bond pads116and116′ after removal of the carrier110(seeFIG.1G), and after inversion of the IC dice10and20and the composite-bridge die-to-die interconnect132. In any event, standoff created by the die-side electrical bumps117and117′, after reflow upon the die side143, accommodates the standoff of the composite-bridge die-to-die interconnect132.

In an embodiment, the IC package substrate142includes a core layer144for rigidity. Above and below the core layer144, build-up layers146include organic layers that accommodate interconnects such as package vias148and traces150to facilitate interconnection of integrated-circuit (IC) dice10and20with composite-bridge die-to-die interconnect132, as well as pin-out connections on the land side141of the IC package substrate142, to an electrical bump array152. In an embodiment, the organic layers146are fabricated from composites of epoxy polymer resins and silica particulate materials. In an embodiment width of the traces150is in a range from 5 μm to 40 μm. In an embodiment, the IC package substrate142may exclude the core layer144for package z-height (or thickness) reduction. In any event, the composite-bridge die-to-die interconnect132, obviates the need for a silicon-bridge interposer, which would require added Z-height. Further, the composite-bridge die-to-die interconnect132also obviates the need for a silicon-bridge such as an embedded multi-die interconnect bridge (EMIB), which would take up useful under-die real estate, under the IC dice10and20.

FIG.1Iis a cross-section elevation of an integrated-circuit package apparatus100such as the IC package that includes the composite-bridge die-to-die interconnect132depicted inFIG.1Haccording to several embodiments. The apparatus100that includes the first and subsequent IC dice10and20, the composite-bridge die-to-die interconnect132and the passive device112, is seated on the die side143of the IC package substrate142. An underfill mass154has been flowed onto the die side143under the IC dice10and20and also to contact the composite-bridge die-to-die interconnect132.

Where the passive device112is a decoupling capacitor112, improved power integrity is enabled by shortened loop inductance between the capacitor112and the IC die that it is servicing, which facilitates uninterrupted current flow that is useful to direct-current (DC) load-line performance and consequently the computing performance of the IC die and any computing system of which it is a part.

Where the passive device112is a decoupling capacitor112, it is coupled to power (Vcc) and to ground (Vss) portion of the several conductive traces within the composite-bridge die-to-die interconnect132. Other conductive traces and vias within the composite-bridge die-to-die interconnect132are used as signal connections, such as data-transmission connections.

As illustrated in an embodiment, the IC package substrate142that carries the IC dice10and20and the composite-bridge die-to-die interconnect132, is being brought toward a board156such as a motherboard156or a printed wiring board156. Electrical contact is made by an electrical bump array, one bump of which is indicated by reference number152. In an embodiment, the board156has an external shell157that provides at least one of physical and electrical insulative protection for components on the board156. For example, the external shell157is an integral portion of the board156, that is part of a hand-held computing system such as a communication device. In an embodiment, the external shell157is an integral portion of the board156, that is part of the exterior of a mobile computing platform such as a drone.

FIG.1Jis a top plan109of the composite-bridge die-to-die interconnect-containing integrated-circuit package apparatus100depicted inFIG.1according to several embodiments. The cross-section elevation depicted inFIG.1may be taken from the section line A-A′ inFIG.1J. The die side143supports the first and subsequent IC dice10and20, and the composite-bridge die-to-die interconnect132with several passive devices in the molding material between the IC dice10and20.

In an embodiment, the passive device112is a first capacitor112and a subsequent passive device158is a subsequent capacitor158that couples into the composite-bridge die-to-die interconnect132. Further passive devices, where the passive device112is a first passive device in the molding material120, include the subsequent passive device158, a third passive device160, a fourth162and a fifth passive device164according to several embodiments. The several passive devices are in the molding material120, and they are integral portions of the composite-bridge die-to-die interconnect132, such that the several passive devices support the IC dice10and20, without the need to be embedded in the IC package substrate142.

In an embodiment, the passive devices are decoupling capacitors112,158,160,162and164. In an embodiment, subsets of the capacitors are separately coupled to different potential power rails, such as a 1.0 Volt power rail for the first capacitors112, and158and a 1.5 V power rail for the capacitors160,162and164. In an embodiment, the capacitors have a thickness in a range from 20 μm to 500 μm. In an embodiment, at least one passive device illustrated is a resistor. In an embodiment, at least one passive device illustrate is an inductor.

In an embodiment, a first integrated-circuit die10is a central processing unit such as a processor made by Intel Corporation of Santa Clara, Calif. In an embodiment, the subsequent IC die20is a graphics processor20. In an embodiment, the first IC die10is bumped onto the die side143with a bump array117and117′ (seeFIG.1) with a bump-pitch geometry in a range from 70 micrometer (μm) to 150 μm.

FIG.1Kis a detail section portion of a composite-bridge die-to-die interconnect as it interfaces with an integrated-circuit package and integrated-circuit dice. Item 1L is omitted. The detail section may be taken for example from the integrated-circuit package apparatus100depicted inFIG.1. The active devices and metallization9and19are further illustrated with respective active devices8and18at the respective IC dice10and20.

FIG.2is a cross-section elevation of an integrated-circuit package apparatus200with a composite-bridge die-to-die interconnect232according to an embodiment. The IC package200includes a first and a subsequent IC die10and20, respectively, the composite-bridge die-to-die interconnect232and a passive device212that is located in a molding layer220between the IC dice10and20, while the IC dice10and20and the composite-bridge die-to-die interconnect232, are seated on a die side243of an IC package substrate242. An underfill mass254has been flowed onto the die side243under the IC dice10and20and also to contact the composite-bridge die-to-die interconnect232.

In an embodiment, a land-side passive device266is mounted “opossum” style on a land side241of the IC package substrate242. The land-side passive device266is coupled by vertical-package interconnects (VPIs), substantially vertically from the land side241, to the die side243and into the composite-bridge die-to-die interconnect232. In concert with the capacitor212, the land-side capacitor266provides enhanced power-supply noise suppression according to an embodiment. In an embodiment, the passive device212is a resistor.

Electrical bumps217and217′ assist to couple the IC dice10and20to the IC package substrate242. The electrical bumps217and217′ create standoff, after reflow upon the die side243for usefully seating the composite-bridge die-to-die interconnect232on the die side243.

In an embodiment, the IC package substrate242includes a core layer244for rigidity. Above and below the core layer244, build-up layers246include organic layers that accommodate interconnects such as package vias248and traces250to facilitate interconnection of integrated-circuit (IC) dice10and20with composite-bridge die-to-die interconnect232, as well as pin-out connections on the land side241of the IC package substrate242, to an electrical bump array252. In an embodiment, the organic layers246are fabricated from composites of epoxy polymer resins and silica particulate materials. In an embodiment width of the traces250is in a range from 5 μm to 40 μm. In an embodiment, the IC package substrate242may exclude the core layer244for package z-height (or thickness) reduction.

As illustrated in an embodiment, the IC package substrate242that carries the IC dice10and20and the composite-bridge die-to-die interconnect232, is being brought toward a board256such as a motherboard256or a printed wiring board256, and the land-side passive device266has a through-path from the land side241to the die side243and into the composite-bridge die-to-die interconnect232.

In an embodiment, the board256has an external shell257that provides at least one of physical and electrical insulative protection for components on the board256.

FIG.3is a cross-section elevation of an integrated-circuit package300with a composite-bridge die-to-die interconnect332according to an embodiment. The IC package300includes a first and a subsequent IC die10and20, respectively, the composite-bridge die-to-die interconnect332and an upper passive device312that is located in the molding layer320between the IC dice10and20, while the IC dice10and20and the composite-bridge die-to-die interconnect332, are seated on a die side343of an IC package substrate342. An underfill mass354has been flowed onto the die side343under the IC dice10and20and also to contact the composite-bridge die-to-die interconnect332.

In an embodiment, an inner passive device368is mounted in a fashion such that the first, upper passive device312is “astride” the inner passive device368, while each of the passive devices312and368are contacting the composite-bridge die-to-die interconnect332. In any event, with the molding material320, the stacked passive components312and368are isolated from each other.

In an embodiment, the first IC die10has a through-silicon via (TSV)370that communicates to an active layer and metallization29, first backside-die chiplet11, such as a memory die. Similarly, a first IC die, subsequent backside-die chiplet12is also on the first IC die10, and is coupled through a TSV. In an embodiment, the subsequent IC die20has a through-silicon via (TSV)372that communicates to an active layer and metallization39, first backside-die chiplet21, such as a memory die. Similarly, a subsequent IC die, subsequent backside-die chiplet22is also on the subsequent IC die20, and is coupled through a TSV.

First and subsequent electrical bumps317and317′ assist to couple the respective first and subsequent IC dice10and20to the IC package substrate342. The electrical bumps317and317′ create a standoff, after reflow upon the die side343for usefully seating the composite-bridge die-to-die interconnect332on the die side343.

In an embodiment, the IC package substrate342includes a core layer344for rigidity. Above and below the core layer344, build-up layers346include organic layers that accommodate interconnects such as package vias348and traces350to facilitate interconnection of integrated-circuit (IC) dice10and20with composite-bridge die-to-die interconnect332, as well as pin-out connections on the land side341of the IC package substrate342, to an electrical bump array352. In an embodiment, the organic layers346are fabricated from composites of epoxy polymer resins and silica particulate materials. In an embodiment, width of the traces350is in a range from 5 μm to 40 μm. In an embodiment, the IC package substrate342may exclude the core layer344for package z-height (or thickness) reduction.

As illustrated in an embodiment, the IC package substrate342that carries the IC dice10and20and the composite-bridge die-to-die interconnect332, is being brought toward a board356such as a motherboard356or a printed wiring board356.

In an embodiment, the board356has an external shell357that provides at least one of physical and electrical insulative protection for components on the board356.

FIG.3Ais a top plan301of the composite-bridge die-to-die interconnect-containing integrated-circuit package apparatus300depicted inFIG.3according to several embodiments. The cross-section elevation depicted inFIG.3may be taken from the section line A-A′ inFIG.3A. The board356is not represented. The die side343supports the first and subsequent IC dice10and20, and the composite-bridge die-to-die interconnect332with the several passive devices in the molding layer320between the IC dice10and20.

In the plan view, the first IC die10carries several chiplets11,11′,12and12′, and the subsequent IC die20carries several chiplets21,21′,22and22′.

In the plan view, the inner passive device368(seeFIG.3) is obscured by the first, upper passive device312. In an embodiment, the passive device312is a first capacitor312and a subsequent passive device358is a subsequent capacitor358that couples into the composite-bridge die-to-die interconnect332. In an embodiment, a subsequent inner passive device is deployed below the subsequent passive device358. Further passive devices, where the passive device312is a first passive device in the molding material320, include the subsequent passive device358, a third passive device360, a fourth362and a fifth passive device364according to several embodiments. In an embodiment, at least two of the upper passive devices are astride an inner passive device, such as the first passive device312and the subsequent passive device358are each astride the first inner passive device368as depicted inFIG.3. In an embodiment, more than two inner passive devices are below the several upper passive devices as illustrated. In an embodiment, more than three inner passive devices are below the several upper passive devices as illustrated. In an embodiment, more than four inner passive devices are below the several upper passive devices as illustrated.

The several upper passive and inner passive device embodiments are in the molding material320and are an integral portion of the composite-bridge die-to-die interconnect332, such that the several upper passive and inner passive devices, support the IC dice10and20, without the need to be embedded in the IC package substrate342.

In an embodiment, the several passive devices are decoupling capacitors312,358,360,362and364and the several inner passive-device embodiments are also decoupling capacitors. In an embodiment, subsets of the capacitors are separately coupled to different potential power rails, such as a 1.0 Volt power rail for the first and subsequent capacitors312, and358and a 1.5 V power rail for the capacitors360,362and364. In an embodiment, the several inner passive devices have the same power-rail connection and use for a 1.0 V power rail. In an embodiment, a subset of the several inner passive devices have the same power-rail connection and use for a 1.0 V power rail, and a subset of the several inner passive devices have a power-rail connection for either a higher than 1.0 V usage or a lower than 1.0 V usage. In an embodiment, the capacitors have a thickness in a range from 20 μm to 500 μm, and the inner capacitors have a width or a length less than that of the capacitors that are astride the inner capacitors.

In an embodiment, a first integrated-circuit die10is a central processing unit such as a processor made by Intel Corporation of Santa Clara, Calif. In an embodiment, the subsequent IC die20is a graphics processor20. In an embodiment, the first IC die10is a processor die that supports more than one TSV-connected memory die such as dice11and11′. In an embodiment, the subsequent IC die20is a graphics-processor die that supports more than one TSV-connected memory die such as dice21and21′.

In an embodiment, the first IC die10is bumped onto the die side343with a bump array317and317′ (seeFIG.3) with a bump-pitch geometry in a range from 70 micrometer (μm) to 150 μm.

FIG.3Bis a top plan302of a composite-bridge die-to-die interconnect-containing integrated-circuit package apparatus, such as the composite-bridge die-to-die interconnect-containing integrated-circuit package apparatus300depicted inFIG.3according to several embodiments. The cross-section elevation depicted inFIG.3may be taken from the section line B-B′ inFIG.3B. The board356is not represented. In an embodiment, the first passive device312straddles a first inner passive device368(seeFIG.3). In an embodiment, the first passive device312is seated atop a first lower passive device476such as is illustrated inFIG.4.

The die side343supports the first and subsequent IC dice10and20, and the composite-bridge die-to-die interconnect332with the several passive devices in the molding layer320between the IC dice10and20. Additionally, a third IC die30and a fourth IC die40are also on the die side343of the IC package substrate342.

In the plan view, the first IC die10carries several chiplets11and12, and the subsequent IC die20carries several chiplets21and22.

In the plan view, the first, subsequent and third passive devices312,358and360are in the molding material320, and contacting the composite-bridge die-to-die interconnect332. In an embodiment, a fourth passive device362is in the molding material320, between the first IC die10and the fourth IC die40. In an embodiment, a fifth passive device364is in the molding material320, between the first IC die10and the fourth IC die40, and also adjacent the subsequent passive device358. In an embodiment, a sixth passive device368is in the molding material320, between the subsequent IC die20and the fourth IC die40, and also adjacent the subsequent passive device358. In an embodiment, a seventh passive device374is in the molding material320, between the subsequent IC die20and the fourth IC die40, and also adjacent the sixth passive device368.

The several passive device embodiments are in the molding material320and are an integral portion of the composite-bridge die-to-die interconnect332, such that the several passive devices, support the IC dice10,20,30and40, without the need to be embedded in the IC package substrate342.

In an embodiment, the several passive devices are decoupling capacitors312,358,360,362,364,368and374. In an embodiment, subsets of the capacitors are separately coupled to different potential power rails, such as a 1.0 Volt power rail for the capacitor312, and358and a 1.5 V power rail for the capacitors360,362and364. In an embodiment, the several passive devices have the same power-rail connection and use for a 1.0 V power rail. In an embodiment, a subset of the several passive devices368and374have the same power-rail connection and use for a 1.0 V power rail, and a subset of the several passive devices368and374have a power-rail connection for either a higher than 1.0 V usage or a lower than 1.0 V usage. In an embodiment, the capacitors have a thickness in a range from 20 μm to 500 μm.

In an embodiment, a first integrated-circuit die10is a central processing unit such as a processor made by Intel Corporation of Santa Clara, Calif. In an embodiment, the subsequent IC die20is a graphics processor20. In an embodiment, the third IC die30is a platform controller hub30. In an embodiment, the fourth IC die40is a baseband processor40. In an embodiment, the several dice10,20,30and40include functions of a CPU, GPU, memory, a field-programmable gate array (FPGA), and baseband processor.

In an embodiment, the first IC die10is a processor die that supports more than one TSV-connected memory die such as dice11and12. In an embodiment, the subsequent IC die20is a graphics-processor die that supports more than one TSV-connected memory die such as dice21and22.

In an embodiment, the first IC die10is bumped onto the die side343with a bump array317and317′ (seeFIG.3) with a bump-pitch geometry in a range from 70 micrometer (μm) to 150 μm.

In an embodiment as illustrated, the composite-bridge die-to-die interconnect332is a die-to-die bridge332where permutations of the several dice are directly connected such as with die-to-die trace134depicted inFIG.1G. For example, the composite-bridge die-to-die interconnect332has die-to-die traces between any adjacent IC dice, in non-equivalent embodiments: IC dice10and20, IC dice10and30, IC dice10and40, IC dice20and40, and IC dice20and30. Further and similar to the die-to-die trace134that couples the IC dice10and20inFIG.1G, a die-to-die trace in the composite-bridge die-to-die interconnect332, couples the third and fourth IC dice30and40.

FIG.4is a cross-section elevation of an integrated-circuit package apparatus400with a composite-bridge die-to-die interconnect432according to an embodiment. The IC package400includes a first and a subsequent IC die10and20, respectively, the composite-bridge die-to-die interconnect432and an upper passive device412that is located in a molding layer420between the IC dice10and20, while the IC dice10and20and the composite-bridge die-to-die interconnect432, are seated on a die side443of an IC package substrate442. An underfill mass454has been flowed onto the die side443under the IC dice10and20and also to contact the composite-bridge die-to-die interconnect432.

In an embodiment, a lower passive device476is mounted in a fashion such that a first, upper passive device412is above and on (in e.g. direct-soldered contact) the lower passive device476, while the lower passive device476is contacting the composite-bridge die-to-die interconnect432.

In an embodiment, the first IC die10has a through-silicon via (TSV)470that communicates to an active layer and metallization49, first backside-die chiplet11, such as a memory die. Similarly, a first IC die, subsequent backside-die chiplet12is also on the first IC die10, and is coupled through a TSV. In an embodiment, the subsequent IC die20has a through-silicon via (TSV)472that communicates to an active layer and metallization49, first backside-die chiplet21, such as a memory die. Similarly, a subsequent IC die, subsequent backside-die chiplet22is also on the subsequent IC die20, and is coupled through a TSV.

Electrical bumps417and417′ assist to couple the IC dice10and20to the IC package substrate442. The electrical bumps417and417′ create standoff, after reflow upon the die side443for usefully seating the composite-bridge die-to-die interconnect432on the die side443.

In an embodiment, the IC package substrate442includes a core layer444for rigidity. Above and below the core layer444, build-up layers446include organic layers that accommodate interconnects such as package vias448and traces450to facilitate interconnection of integrated-circuit (IC) dice10and20with composite-bridge die-to-die interconnect432, as well as pin-out connections on the land side441of the IC package substrate442, to an electrical bump array452. In an embodiment, the organic layers446are fabricated from composites of epoxy polymer resins and silica particulate materials. In an embodiment width of the traces550is in a range from 5 μm to 40 μm. In an embodiment, the IC package substrate442may exclude the core layer444for package z-height (or thickness) reduction.

As illustrated in an embodiment, the IC package substrate442that carries the IC dice10and20and the composite-bridge die-to-die interconnect432, is being brought toward a board456such as a motherboard456or a printed wiring board456.

In an embodiment, the board456has an external shell457that provides at least one of physical and electrical insulative protection for components on the board456.

It may now be understood that the integrated-circuit package400with the composite-bridge die-to-die interconnect432as depicted inFIG.4, may also be viewed accordingFIG.3A, with the upper and lower passive devices, e.g.412and476inFIG.4, replacing the first upper and inner passive devices312and368, respectively inFIGS.3and3A. Accordingly, the several different voltage ratings set forth for the several capacitors inFIGS.3and3Amay be mapped to equivalent capacitors inFIG.4, with the limitation as the capacitors412and476are in direct contact, they are rated in series.

It may now be understood that the integrated-circuit package400with the composite-bridge die-to-die interconnect432as depicted inFIG.4, may also be viewed accordingFIG.3B, with the upper and lower passive devices, e.g.412and476inFIG.4, replacing the several capacitors312,358and360with stacked upper and lower capacitors inFIG.3B. Accordingly, the several different voltage ratings set forth for the several capacitors inFIG.3Bmay be mapped to equivalent capacitors inFIG.4, with the limitation as the capacitors412and476are in direct contact, they are rated in series.

FIG.5is a process flow diagram for assembling a composite-bridge die-to-die interconnect to an integrated-circuit package apparatus according to several embodiments.

At510, the process includes assembling a composite-bridge die-to-die interconnect onto a first IC die and a subsequent IC die, and to a passive device between the first and subsequent IC dice. In a non-limiting example embodiment, the first and subsequent IC dice10and20, and the composite-bridge die-to-die interconnect132inFIG.1G, have been assembled with the passive device112by use of the molding layer120.

At520, the process includes assembling the composite-bridge die-to-die interconnect to an integrated-circuit package substrate. In a non-limiting example embodiment, the integrated-circuit device apparatus including the IC dice10and20, the composite-bridge die-to-die interconnect132and the passive device112, are seated onto bumps117and117′ on a die side143of the IC package substrate142, as illustrated inFIG.1H. It may now be understood any of the IC device packages depicted inFIGS.1,2,3,3A,3B and4with their disclosed permutations, may be assembled to an IC package substrate at the die side.

At530, the process includes assembling the IC package with the composite-bridge die-to-die interconnect, to a computing system. In a non-limiting example embodiment, the computing system600depicted inFIG.6is used.

FIG.6is included to show an example of a higher-level device application for the disclosed embodiments. The composite-bridge die-to-die interconnect embodiments may be found in several parts of a computing system. In an embodiment, the composite-bridge die-to-die interconnect embodiments can be part of a communications apparatus such as is affixed to a cellular communications tower. In an embodiment, a computing system600includes, but is not limited to, a desktop computer. In an embodiment, a computing system600includes, but is not limited to a laptop computer. In an embodiment, a computing system600includes, but is not limited to a tablet. In an embodiment, a computing system600includes, but is not limited to a notebook computer. In an embodiment, a computing system600includes, but is not limited to a personal digital assistant (PDA). In an embodiment, a computing system600includes, but is not limited to a server. In an embodiment, a computing system600includes, but is not limited to a workstation. In an embodiment, a computing system600includes, but is not limited to a cellular telephone. In an embodiment, a computing system600includes, but is not limited to a mobile computing device. In an embodiment, a computing system600includes, but is not limited to a smart phone. In an embodiment, a system600includes, but is not limited to an internet appliance. Other types of computing devices may be configured with the microelectronic device that includes composite-bridge die-to-die interconnect embodiments.

In an embodiment, the processor610has one or more processing cores612and612N, where612N represents the Nth processor core inside processor610where N is a positive integer. In an embodiment, the electronic device system600using a composite-bridge die-to-die interconnect embodiment that includes multiple processors including 610 and 605, where the processor605has logic similar or identical to the logic of the processor610. In an embodiment, the processing core612includes, but is not limited to, pre-fetch logic to fetch instructions, decode logic to decode the instructions, execution logic to execute instructions and the like. In an embodiment, the processor610has a cache memory616to cache at least one of instructions and data for the composite-bridge die-to-die interconnect element on an integrated-circuit package substrate in the system600. The cache memory616may be organized into a hierarchal structure including one or more levels of cache memory.

In an embodiment, the processor610includes a memory controller614, which is operable to perform functions that enable the processor610to access and communicate with memory630that includes at least one of a volatile memory632and a non-volatile memory634. In an embodiment, the processor610is coupled with memory630and chipset620. In an embodiment, the chipset620is part of a composite-bridge die-to-die interconnect embodiment depicted, e.g. inFIGS.1,2,3,3A,3B and4.

The processor610may also be coupled to a wireless antenna678to communicate with any device configured to at least one of transmit and receive wireless signals. In an embodiment, the wireless antenna interface678operates in accordance with, but is not limited to, the IEEE 802.11 standard and its related family, Home Plug AV (HPAV). Ultra Wide Band (UWB), Bluetooth, WiMax, or any form of wireless communication protocol.

In an embodiment, the volatile memory632includes, but is not limited to, Synchronous Dynamic Random-Access Memory (SDRAM), Dynamic Random-Access Memory (DRAM), RAMBUS Dynamic Random-Access Memory (RDRAM), and/or any other type of random access memory device. The non-volatile memory634includes, but is not limited to, flash memory, phase change memory (PCM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), or any other type of non-volatile memory device.

The memory630stores information and instructions to be executed by the processor610. In an embodiment, the memory630may also store temporary variables or other intermediate information while the processor610is executing instructions. In the illustrated embodiment, the chipset620connects with processor610via Point-to-Point (PtP or P-P) interfaces617and622. Either of these PtP embodiments may be achieved using a composite-bridge die-to-die interconnect embodiment as set forth in this disclosure. The chipset620enables the processor610to connect to other elements in a composite-bridge die-to-die interconnect embodiment in a system600. In an embodiment, interfaces617and622operate in accordance with a PtP communication protocol such as the Intel® QuickPath Interconnect (QPI) or the like. In other embodiments, a different interconnect may be used.

In an embodiment, the chipset620is operable to communicate with the processor610,605N, the display device640, and other devices672,676,674,660,662,664,666,677, etc. The chipset620may also be coupled to a wireless antenna678to communicate with any device configured to at least do one of transmit and receive wireless signals.

The chipset620connects to the display device640via the interface626. The display640may be, for example, a liquid crystal display (LCD), a plasma display, cathode ray tube (CRT) display, or any other form of visual display device. In an embodiment, the processor610and the chipset620are merged into a composite-bridge die-to-die interconnect embodiment in a system. Additionally, the chipset620connects to one or more buses650and655that interconnect various elements674,660,662,664, and666. Buses650and655may be interconnected together via a bus bridge672such as at least one composite-bridge die-to-die interconnect embodiment. In an embodiment, the chipset620, via interface624, couples with a non-volatile memory660, a mass storage device(s)662, a keyboard/mouse664, a network interface666, smart TV676, and the consumer electronics677, etc.

While the modules shown inFIG.6are depicted as separate blocks within the composite-bridge die-to-die interconnect embodiments in a computing system600, the functions performed by some of these blocks may be integrated within a single semiconductor circuit or may be implemented using two or more separate integrated circuits. For example, although cache memory616is depicted as a separate block within processor610, cache memory616(or selected aspects of616) can be incorporated into the processor core612.

To illustrate the composite-bridge die-to-die interconnect IC package embodiments and methods disclosed herein, a non-limiting list of examples is provided herein:

Example 1 is an integrated-circuit apparatus, comprising: a first integrated-circuit (IC) die; a subsequent IC die; a composite-bridge die-to-die interconnect contacting composite-bridge bond pads on each of the first and subsequent IC dice, and wherein the composite-bridge die-to-die interconnect exposes package-connect bond pads on each of the first and subsequent IC dice; a passive device between the first and subsequent IC dice, and contacting the composite-bridge die-to-die interconnect; and a molding material that contacts the first and subsequent IC dice, the passive device and the composite-bridge die-to-die interconnect.

In Example 2, the subject matter of Example 1 optionally includes a first lateral interconnect in the composite-bridge die-to-die interconnect, that couples to the first IC die and to the passive device; and a subsequent lateral interconnect in the composite-bridge die-to-die interconnect, that couples to the subsequent IC die and to the passive device.

In Example 3, the subject matter of any one or more of Examples 1-2 optionally include a die-to-die trace in the composite-bridge die-to-die interconnect, that bypasses the passive device and couples the first and subsequent IC dice.

In Example 4, the subject matter of any one or more of Examples 1-3 optionally include a conductive shield in the composite-bridge die-to-die interconnect, wherein the conductive shield projects a footprint onto the composite-bridge bond pads, and onto the passive device.

In Example 5, the subject matter of any one or more of Examples 1-4 optionally include a first lateral interconnect in the composite-bridge die-to-die interconnect, that couples to the first IC die and to the passive device; a subsequent lateral interconnect in the composite-bridge die-to-die interconnect, that couples to the subsequent IC die and to the passive device; and a die-to-die trace in the composite-bridge die-to-die interconnect, that bypasses the passive device and couples the first and subsequent IC dice.

In Example 6, the subject matter of any one or more of Examples 1-5 optionally include a first lateral interconnect in the composite-bridge die-to-die interconnect, that couples to the first IC die and to the passive device; a subsequent lateral interconnect in the composite-bridge die-to-die interconnect, that couples to the subsequent IC die and to the passive device; and a conductive shield in the composite-bridge die-to-die interconnect, wherein the conductive shield projects a footprint onto the composite-bridge bond pads, and onto the passive device.

In Example 7, the subject matter of any one or more of Examples 1-6 optionally include a first lateral interconnect in the composite-bridge die-to-die interconnect, that couples to the first IC die and to the passive device; a subsequent lateral interconnect in the composite-bridge die-to-die interconnect, that couples to the subsequent IC die and to the passive device; a die-to-die trace in the composite-bridge die-to-die interconnect, that bypasses the passive device and couples the first and subsequent IC dice; and a conductive shield in the composite-bridge die-to-die interconnect, wherein the conductive shield projects a footprint onto the composite-bridge bond pads, and onto the passive device.

In Example 8, the subject matter of any one or more of Examples 1-7 optionally include an integrated-circuit package substrate; and package-connect electrical bumps contacting the package-connect bond pads, wherein the electrical bumps are on the integrated-circuit package substrate at a die side.

In Example 9, the subject matter of any one or more of Examples 1-8 optionally include an integrated-circuit package substrate; package-connect electrical bumps contacting the package-connect bond pads, wherein the electrical bumps are on the integrated-circuit package substrate at a die side; and wherein the composite-bridge die-to-die interconnect is also on the die side.

In Example 10, the subject matter of any one or more of Examples 1-9 optionally include wherein the passive device is an embedded passive device, further including: an integrated-circuit package substrate including a die side and a land side; package-connect electrical bumps contacting the package-connect bond pads, wherein the electrical bumps are on the integrated-circuit package substrate at the die side; and a bottom passive device on the land side, wherein the bottom passive device is coupled to at least one of the first and subsequent IC dice.

Example 11 is an integrated-circuit package apparatus, comprising: an integrated-circuit package substrate including a die side and a land side; a first integrated-circuit (IC) die on the die side; a subsequent IC die on the die side; a composite-bridge die-to-die interconnect contacting composite-bridge bond pads on each of the first and subsequent IC dice, and wherein the composite-bridge die-to-die interconnect exposes package-connect bond pads on each of the first and subsequent IC dice; package-connect bond pads contacting the first and subsequent IC dice at the die side; a passive device between the first and subsequent IC dice, and coupled to the composite-bridge die-to-die interconnect; and a molding material that contacts the first and subsequent IC dice, the passive device and the composite-bridge die-to-die interconnect.

In Example 12, the subject matter of Example 11 optionally includes wherein the passive device contacts the composite-bridge die-to-die interconnect.

In Example 13, the subject matter of any one or more of Examples 11-12 optionally include at least one chiplet on the first IC die, and coupled to the first IC die by a through-silicon via.

In Example 14, the subject matter of any one or more of Examples 11-13 optionally include at least one chiplet on the first IC die, and coupled to the first IC die by a through-silicon via; and at least one chiplet on the subsequent IC die, and coupled to the subsequent IC die by a through-silicon via.

In Example 15, the subject matter of any one or more of Examples 11-14 optionally include wherein the passive device is a first passive device, further including a subsequent passive device between the first and subsequent IC dice and in the molding material, wherein the subsequent passive device contacts the composite-bridge die-to-die interconnect.

In Example 16, the subject matter of any one or more of Examples 11-15 optionally include wherein the passive device is a first passive device, further including a first inner passive device below the first passive device and in the molding material, wherein the first inner passive device contacts the composite-bridge die-to-die interconnect.

In Example 17, the subject matter of any one or more of Examples 11-16 optionally include wherein the passive device is a first passive device, further including: a first inner passive device below the first passive device and in the molding material, wherein the first inner passive device contacts the composite-bridge die-to-die interconnect; a subsequent passive device between the first and subsequent IC dice and in the molding material, wherein the subsequent passive device contacts the composite-bridge die-to-die interconnect; and a subsequent inner passive device below the subsequent passive device and in the molding material, wherein the subsequent inner passive device contacts the composite-bridge die-to-die interconnect.

In Example 18, the subject matter of any one or more of Examples 11-17 optionally include wherein the passive device is a first passive device, further including: a subsequent passive device between the first and subsequent IC dice and in the molding material, wherein the subsequent passive device contacts the composite-bridge die-to-die interconnect; a third IC die on the die side, adjacent each of the first and subsequent IC dice; a fourth IC die on the die side, adjacent each of the first and subsequent IC dice; and a third passive device between the first and fourth IC dice and in the molding material, wherein the third passive device contacts the composite-bridge die-to-die interconnect.

In Example 19, the subject matter of any one or more of Examples 11-18 optionally include wherein the passive device is a first upper passive device, further including a first lower passive device below and contacting the first upper passive device and in the molding material, wherein the first lower passive device contacts the composite-bridge die-to-die interconnect.

In Example 20, the subject matter of any one or more of Examples 11-19 optionally include a printed wiring board coupled to the land side; and a chipset coupled to the printed wiring board.

In Example 21, the subject matter of Example 20 optionally includes wherein the printed wiring board includes an external shell that is a dielectric material, and wherein the external shell is at least part of the exterior of an apparatus selected from a mobile computing system and a drone.

Example 22 is a method of assembling an integrated-circuit apparatus, comprising: assembling a composite-bridge die-to-die interconnect on a first integrated-circuit die, a passive device and a subsequent integrated-circuit die, wherein the passive device is between the first and subsequent integrated-circuit dice; and contacting a molding material to the composite-bridge die-to-die interconnect, the first and subsequent integrated-circuit dice, and to the passive device.

In Example 23, the subject matter of Example 22 optionally includes assembling the composite-bridge die-to-die interconnect to an integrated-circuit package substrate on a die side, wherein electrical bumps on the first and subsequent integrated-circuit dice contact the die side; and underfilling the first and subsequent integrated-circuit dice.

In Example 24, the subject matter of any one or more of Examples 22-23 optionally include assembling the composite-bridge die-to-die interconnect to an integrated-circuit package substrate on a die side, wherein electrical bumps on the first and subsequent integrated-circuit dice contact the die side; underfilling the first and subsequent integrated-circuit dice; and assembling the integrated-circuit package substrate at a land side to a printed wiring board.