Method and system for using a multi-RF input receiver for diversity selection

Aspects of a method and system for signal processing are disclosed and may include receiving a plurality of wireless signals via a plurality of M receive antennas. Each of M phase shifters coupled to each of the M receive antennas may be set to operate in a bypass mode or with an arbitrary phase setting. Corresponding signal strengths of M signals generated when each of the M phase-shifters is coupled to each of the M receive antennas may be measured, while at least a portion of the M receive antennas are turned off. Selecting one of the M generated signals for processing without the use of an antenna switch, based on the measured signal strength. A signal strength of each of the generated M amplified signals may be measured while turning off at least one of the plurality of M receive antennas and without the use of the phase-shifters.

Not Applicable

FIELD OF THE INVENTION

Certain embodiments of the invention relate to signal processing. More specifically, certain embodiments of the invention relate to a method and system for using a multi-RF input receiver for diversity selection.

BACKGROUND OF THE INVENTION

Electronic devices can now communicate with each other using a variety of wireless communication systems, such as wireless local area network (WLAN) systems, 802.11 network systems, Wi-Fi network systems, etc. Demands for higher data rate wireless communication are increasing day to day and it is becoming difficult to achieve further improvement in spectral efficiency using only time and/or frequency domain methods.

Multiple antenna systems are known to be an efficient solution to increase data rate and/or increase robustness by taking advantage of multi-path scattering present in most indoor and urban environments. Phase shifters (PS) are used to set the phase of the received signal from each antenna. These radio frequency (RF) phase shifters have to meet certain requirements, such as having adjustable phase with the range of 360 degrees, having low loss and control complexity, consuming low power, and/or being compact and low cost to be able to be used in commercial applications. As such, it would be desirable to provide a phase shifter (e.g., an RF phase shifter) that has a high shift range, a small size, a low cost, and/or a low power consumption.

BRIEF SUMMARY OF THE INVENTION

A system and/or method is provided for using a multi-RF input receiver for diversity selection, substantially as shown in and/or described in connection with at least one of the figures, as set forth more completely in the claims.

DETAILED DESCRIPTION OF THE INVENTION

Certain embodiments of the invention may be found in a method and system for using a multi-RF input receiver for diversity selection. Aspects of the method may comprise receiving a plurality of wireless signals via a plurality of M receive antennas. Each of M phase shifters coupled to each of the M receive antennas may be set to operate in a bypass mode or with an arbitrary phase setting. Corresponding signal strengths of M signals generated when each of the M phase-shifters is coupled to each of the M receive antennas may be measured, while at least a portion of the M receive antennas are turned off. Selecting one of the M generated signals for processing without the use of an antenna switch, based on the measured signal strength. Aspect of the method may also include receiving a plurality of wireless signals via a plurality of M receive antennas. Each of the plurality of wireless signals received via the plurality of M receive antennas may be amplified to generate M amplified signals. A signal strength of each of the generated M amplified signals may be measured while turning off at least a portion of the plurality of M receive antennas. Selecting one of the M amplified signals for processing without the use of an antenna switch, based on the measured signal strength of each of the generated M amplified signals.

An exemplary embodiment of the present invention provides a phase shifter that is high in shift range, small in size, low in cost, high in performance, and/or low in power consumption. Signals of a RF phase shifter can be described in terms of one or more sinusoidal waveforms. For example, in a simple electronic-circuit application, a signal (e.g., a current or a voltage) can be varied sinusoidally as a function of time as represented below:
I(t)=Asin(2πft+θ),
where A is the amplitude, f is the frequency, and θ is the phase angle with respect to some arbitrary phase angle. More specifically, the amplitude A is related to a peak signal value (e.g., a peak current or voltage) of the sinusoidal wave, the frequency f is related to the inverse of a period T of the wave, and the phase angle θ is the phase angle of the wave with respect to a phase reference. The phase reference can be chosen arbitrarily to define the initial value of the phase angle θ at the input to a RF phase shifter or RF phase shifting circuit.

In general, a phase angle θ is used to measure the progression of a periodic wave in time or space from a chosen instant or position. That is, the phase angle θ of the periodic wave having the frequency f, which corresponds to the period T, is the fractional part (t/T) of the period T through which t has shifted relative to an arbitrary origin or phase reference.

To simplify the following description, a phasor or vector concept is used to represent a sinusoidal wave. As is known to those skilled in the art, a phasor or a vector represents a particular complex number that contains information about a sinusoidal wave's amplitude A and phase angle θ.

Referring now toFIGS. 1A to 1F, a concept of the present invention is to add two perpendicular vectors with variable amplitudes A together to represent a third vector. As is shown inFIG. 1Aand assuming a constant frequency f is applied to two sinusoidal waves, the two waves can be represented by vectors100,110. As are shown inFIGS. 1B to 1C, by changing the amplitude A (e.g., by varying a gain) and adding these two vectors100,110, a third vector120having any phase angle θ between 0 and 90 degrees is achievable. In particular, by changing a first gain G1of the vector100from 0 to 1, the phase angle θ of the third vector120will change from 90 degrees to 45 degrees and by changing a second gain G2from 1 to 0, the phase angle (or phase) of the third vector100will change from 45 degrees to 0 degrees.

FIGS. 1D to 1Fshow exemplary embodiments {e.g., using inversely connected phase shifter components) to provide a negative vector100′ and/or a negative vector110′. In particular, the addition of the positive vector100and the negative vector110′ results in a vector130as schematically indicated inFIG. 1D. The addition of the positive vector110and the negative vector110′ results in a vector140inFIG. 1Eand the addition of the negative vector100′ and the negative vector110′ results in a vector150inFIG. 1F. As such, referring now toFIGS. 1A to 1F, by changing a gain of the vectors100,110,100′, and/or110′ from 0 to 1, the phase angle θ of the resultant vector (e.g.,120,130,140,150, etc) can change from 0 to 360 degrees.

FIG. 2shows the variation of the phase angle (or phase) θ (in degree) versus the first gain G1of the vector100. As is shown inFIG. 2, the phase angle θ (in a substantially linear fashion) increases as the first gain G1decreases and decreases as the first gain G1increases.

As envisioned, an embodiment of the present invention is a phase shifter or an active RF phase shifter that is designed to produce the phase shift effects required for the operation of certain antenna systems or multiple antenna systems. The phase shifter can include non-silicon based technologies (e.g., technologies using gallium-arsenide (GaAs) MOSFET) and/or be implemented in CMOS.

In particular, an embodiment of the present invention uses two 90 degree phase shift signals and/or a simple RC-CR circuit with gain control to generate the vectors ofFIGS. 1A to 1Fto produce a 360 degree phase shift.

In addition, an embodiment of the present invention is an active phase shifter and/or uses transistors to perform amplitude (or gain) control rather then using a pure passive solution. As such, the size and cost of the embodiment of the present invention can be substantially less than a 360 degree phase shifter using an inductor and/or a passive phase shifter.

Referring now toFIG. 3A, a phase shifter according to an exemplary embodiment of the present invention is provided. The phase shifter ofFIG. 3Ais a 90 degree phase shifter where the RC-CR network300shown inFIG. 3Ais used. The RC-CR network300can be used as a broadband 90 degree phase shifter. The RC-CR network300includes an input Vi, first and second outputs Vo1, Vo2, first and second capacitors C1, C2, and first and second resistors R1, R2. The input Vi is connected to a ground voltage via the first resistor R1and the first capacitor C1in that order, and the first output Vo1is connected to a first connection node310between the first resistor R1and the first capacitor C1. In addition, the input Vi is connected to the ground via the second capacitor C2and the second resistor R2in that order, and the output Vo1is connected to a second connection node310between the second capacitor C2and the second resistor R2.

In operation, when the input (or input voltage) Vi is applied to the RC-CR network300, the first and second outputs (or output voltages) Vo1, Vo2are outputted with a 90 degree difference in phase (or phase angle). That is, the output Vo1and the output Vo2are given as follow:

where Vi represent voltage of the input Vi; Vo1and Vo2respectively represent voltage of the first and second outputs Vo1, Vo2; R1and R2respectively represent resistance of the first and second resistors R1, R2; C1and C2respectively represent capacitance of the first and second capacitors C1, C2; and s represent the complex frequency. Since s=jω and ω=2πf the output Vo1and the output Vo2can also be given as follow:

As such, the phase (or phase angle) of the first output Vo1and the phase of the second output Vo2are given as follow:

where <Vo1and <Vo2respectively represent the phase of the outputs Vo1, Vo2; and <Vi represents the phase of the input Vi. Thus, if R1=R2and C1=C2, the phase difference of the outputs Vo1, Vo2(i.e., <Vo1−<Vo2) is equal to π/2 or 90 degrees. Also, at ω=I/R1C1(or 1/R2C2), the amplitudes of the output Vo1and the output Vo2are equal.

Referring now toFIG. 3B, a phase shifter according to an exemplary embodiment of the present invention is provided. The phase shifter ofFIG. 3Bis substantially similar to the 90 degree phase shifter ofFIG. 3Awith the addition of first and second gain controllers330,340and an adder380. Specifically, the phase shifter ofFIG. 3Buses an RC-CR network300′ shown inFIG. 3B. The RC-CR network300′ ofFIG. 3Bis substantially similar to the RC-CR network300ofFIG. 3Awith the addition of the first gain controller330being connected to the first connection node310via the first resistor R1, the second gain controller340being connected to the second connection node320via the second capacitor C2, and the adder380being connected to the outputs Vo1, Vo2.

In operation, when the input (or input voltage) Vi is applied to the RC-CR network300′ and when no gains are provided by the first and second gain controllers330,340(or gains are equal), the first and second outputs (or output voltages) Vo1, Vo2are outputted with a 90 degree difference in phase (or phase angle) and equal in amplitude at ω=1/R1C1(or I/R2C2). In this case, the output Vo of the adder is outputted with a signal having a 45 degree difference in phase (or phase angle) with respect to the first output Vo1or the second output Vo2(e.g., seeFIG. 1B). Moreover, by selectively changing the gain of the first and/or second gain controllers330,340, other desired phase or phase angle θ can be generated at the output Vo of the adder380(e.g., seeFIG. 1C).

FIG. 4shows a differential circuit embodiment of the present invention. First and second differential pairs402,404include differential inputs Vi+, Vi−that are fed from an output of a previous stage (not shown). The first and second differential pairs402,404convert voltage to current. By passing the currents through the RC-CR circuit pairs412,414, the 90 degree phase shifted signals are generated and they are added with each other in adders450a,450bto give the final signal (or final output voltage). By changing the gain of each of the first and second differential pairs402,404, via the gain controllers430a,430b,440a,440b, the desired phase or phase angle θ can be generated at the output of the adder450a,450b. To get 360 degree phase shifting, the embodiment ofFIG. 4just needs to change the polarity of the input of the differential pairs402,404.

In more detail, loads ZLare coupled to the first and second differential pairs402,404via the adders450a,450b. The first and second differential pairs402,404include cascoded transistor pairs having NMOS FETS (e.g. Mc1and M1) serially coupled together such that the source of a cascode transistor (e.g. NMOS FET Mc1) is coupled to the drain of a transconductance transistor (e.g. NMOS FET M1) via a connection-control node (e.g.,400a). In addition, a gain controller430a,430b,440a,440bis respectively coupled to each connection-control node400a,400b,410a,410b. In this embodiment, at least one of differential input voltages Vi+, Vi−is coupled to each of the transconductance transistors (M1-M4) of the first and second differential pairs402,404. The transconductance transistors (M1-M4) are for changing voltage(s) into current(s). Further, the cascode transistors (Mc1-Mc4) of the first and second differential pairs402,404are, by way of example, coupled to control voltages Vb. The cascode transistors (Mc1-Mc4) are for impedance balancing, gain control assisting, increasing output impedance, reducing an effective capacitance input, and/or improving linearity.

In operation, the first differential pair402converts a differential input voltage into a first differential current as a function of an input voltage Vi+, Vi−. In addition, the gain controllers430a,430bvia the connection-control nodes400a,400bcontrol a gain of the first differential current. In a similar manner, the second differential pair404controls the output current and gain of the second differential pair404. For example, the gain controllers440a,440bvia the connection-control nodes410a,410bcontrol a gain of a second differential current after the second differential pair404current converts a differential input voltage into the second differential current in accordance with the input voltage Vi+, Vi−. As such, by passing the currents outputted from the first and second differential pairs402,404through the RC-CR network pairs412,414, the 90 degree phase shifted signals are generated and they are added up in the adders450a,450b(and/or the loads ZL) to give the final signal. In addition, by changing the gain of the each of the first and second differential pairs402,404via the gain controllers430a,430b,440a,440b, the desired phase or phase angle θ can be generated after adding the two currents. To get 360 degree phase shifting, the embodiment ofFIG. 4just needs to change the polarity of the currents initially generated by one or both of the differential pairs402,404.

Referring now toFIG. 5A, a gain of a phase shifter in one embodiment of the present invention is varied by controlling an amount of a current that passes through a load. In particular, the embodiment ofFIG. 5Aincludes first and second transconductance transistors M1′, M2′ for converting voltage to current and first and second cascode transistors Mc1′, Mc2′. The first and second cascode transistors Mc1′, Mc2′ are coupled to the first and second transconductance transistors M1′, M2′ via first and second connection-control nodes500,510such that the source of a cascode transistor (e.g. NMOS FET Mc1′) is coupled to the drain of a transconductance transistor (e.g. NMOS FET M1′). In addition, the first connection-control node500is coupled to one or more control transistors Mc11, Mc12such that the source of each control transistor (e.g. NMOS FET Mc11or NMOS FET Mc12) is coupled to the drain of the first transconductance transistor M1′. The second connection-control node510is coupled to one or more other control transistors Mc21, Mc22such that the source of each control transistor (e.g. NMOS FET Mc21or NMOS FET Mc22) is coupled to the drain of the second transconductance transistor M2′. In this embodiment, at least one of the input voltages Vi+′, Vi−′ is coupled to each of the transconductance transistors (M1′, M2′) and the cascode transistors (Mc1′, Mc2′) are coupled to cascode control voltage Vb. Further, the control transistors (Mc11, Mc12, Mc22, Mc22) of the first and second connection-control nodes500,510are individually coupled to separate control voltages Vc1, Vc2respectively.

In operation, when the control voltages Vc1, Vc2are both low, all of the current (i.e., the desired signal) goes to the load. However, when one or both of the control voltages Vc1, Vc2are high, some portion of the current goes to the load and the rest goes to a voltage VDDor a ground voltage. As such, by defining a size (e.g., an aspect ratio) of the control transistors (Mc11, Mc12, Mc21, Mc22) and/or the control voltages Vc1, Vc2, the embodiment can adjust how much current goes to the load via the cascode transistors (Mc1′, Mc2′) to thereby provide a variable and controllable gain.

Referring now toFIG. 5B, to get 360 degree phase shifting, an embodiment of the present invention provides third and fourth cascode transistors (Mc1″, Mc2″) to change the polarity of the currents initially generated by a differential pair (e.g., the differential pair402,404ofFIG. 4).

As shown, the embodiment ofFIG. 5Bis substantially similar to the gain varying embodiment ofFIG. 5Awith the addition of the third and fourth cascode transistors (Mc1″, Mc2″). In particular, the first and second cascode transistors Mc1′, Mc2′ are coupled to the first and second transconductance transistors M1′, M2′ via first and second connection-control nodes500,510such that the source of a cascode transistor (e.g. NMOS FET Mc1′) is coupled to the drain of a transconductance transistor (e.g. NMOS FET M1). Similarly, the third and fourth cascode transistors Mc1″, Mc2″ are also coupled to the first and second transconductance transistors M1′, M2′ via the first and second connection-control nodes500,510such that the source of a cascode transistor (e.g. NMOS FET Mc1″) is coupled to the drain of a transconductance transistor (e.g. NMOS FET M1′). However, to provide the polarity change, the drain of the first cascode transistor Mc1′ is coupled to the first polarity-control node520; the drain of the second cascode transistor Mc2′ is coupled to the second polarity-control node530; the drain of the third cascode transistor Mc1″ is coupled to the second polarity-control node530; and the drain of the fourth cascode transistor Mc2″ is coupled to the first polarity-control node520. In this embodiment, the first and second cascode transistors (Mc1′, Mc2′) are coupled to cascode control voltage Vb1and the third and fourth cascode transistors (Mc1″, Mc2″) are coupled to cascode control voltage Vb2.

In operation, the embodiment ofFIG. 5Bprovides a first polarity using the first and second cascode transistors (Mc1′, Mc2′) and provides a second polarity using the third and fourth cascode transistors (Mc1″, Mc2″). That is, in this embodiment, the first polarity is provided when Vb2is low and Vb1is high and the second polarity is provided when Vb2is high and Vb1is low.

Referring back toFIG. 4, each of the first and second differential pairs402,404may include the gain control components and/or polarity control components ofFIGS. 5Aand/or5B to provide a variable and controllable gain and/or to change a polarity of an input voltage. In one embodiment, the components for varying the gain of each of the first and second differential pairs402,404are controlled separately (i.e., with control voltages Vc1, Vc2for one differential pair402, and different control voltages for another differential pair404) in a manner that is substantially similar to how the first and second cascode transistors (Mc1′-Mc2′) and the third and fourth cascode transistors (Mc1″-Mc2″) ofFIG. 5Bare individually coupled to separate cascode control voltages Vb1and Vb2. As such, the gain of the first and second differential pairs402,404can be individually controlled by changing the logic level (i.e., switching between high and low logic level) of the separate control voltages.

One of skill in the art will appreciate that the invention is applicable to differential and/or non-differential implementations. For example,FIG. 6shows a non-differential circuit embodiment of the present invention. The embodiment ofFIG. 6includes a load ZLcoupled to an RC-CR circuit600via an adder650. The RC-CR circuit600includes a capacitor C2having a first capacitor node660and a second capacitor node665and a resistor R2coupled between the first capacitor node660and a ground or a voltage Vdd. The RC-CR circuit600also includes a resistor R1having a first resistor node670and a second resistor node675and a capacitor C1coupled between the first resistor node670and the ground or the voltage Vdd. Cascode transistors Mc11′, Mc12′ are respectively coupled transconductance transistors Mc11″, M12via connection-control nodes610,620. In addition, control transistors Mc31), MC32′ are coupled to the connection-control node620and control transistor Mc21′ and Mc22′ are coupled to the connection-control node610. In this embodiment, an input voltage V1′ is coupled to each of the transconductance transistors (M11-M12). The transconductance transistors (M11′-M12′) are for changing voltage(s) into current(s). The cascode transistors (Mc11′-Mc12′) are coupled to control voltages Vb. The cascode transistors (Mc11′-Mc12′) are for impedance balancing, reducing an effective capacitance input, gain control assisting, increasing output impedance, and/or improving linearity. Moreover, the control transistors Mc31′, MC32′, MC21′, Mc22′ are each respectively coupled to a control voltage Vc1, Vc2, Vc3, Vc4. The control transistors Mc31′, MC32′, Mc21′, Mc22′ are for controlling a gain of the RC-CR circuit600. As shown, the gain on each arm615,625of the present embodiment can be individually controlled by individually changing the logic level (i.e., switching between high and low logic level) of the separate control voltages Vc1, Vc2, Vc3, Vc4.

An exemplary phase shifter of the present invention may be integrated into any of a variety of RF circuit applications and/or wireless systems to increase their sensitivity at a minimal cost. For example, referring toFIG. 7, the described exemplary phase shifter may be incorporated into a receiving node710of a typical communication system700for receiving and processing radio frequency signals705from a transmit node702that transmits the transmitted RF signals. In addition, the described exemplary phase shifter and/or another phase shifter of the present invention may be incorporated into the transmit node702.

FIG. 8Aillustrates a conventional receive node using an antenna diversity switch. Referring toFIG. 8A, the conventional receive node800amay comprise antennas802a,804a, an antenna diversity switch806a, and a low noise amplifier (LNA)808a. The conventional receive node may also comprise a frequency mixer810a, an intermediate processing stage812a, an analog-to-digital (A/D) converter814a, and a digital signal processor816a.

The intermediate processing stage812amay comprise a baseband processor and or a filter for filtering the mixed signal received from the mixer810a. The antenna diversity switch806amay be used to switch between the two receive antennas802a,804a, and select a signal for processing.

In one embodiment of the invention, the receiver node800amay be further improved by eliminating the antenna diversity switch806aand using one or more phase shifters for diversity selection.

FIG. 8Billustrates the receive node ofFIG. 7using phase shifters, in accordance with an embodiment of the invention. Referring toFIG. 8B, the receive node710bmay comprise phase shifters770b(e.g., as illustrated inFIGS. 1,2,3,4,5and/or6), low noise amplifiers (LNAs)755b, frequency mixers760b, intermediate processing stages750b, a digital signal processor, or a communications controller (DSP)730b, a combiner780b, and antennas740b. In one embodiment of the invention, the digital signal processor730bmay be operating in accordance with one or more standards, including but not limited to, IEEE 802.11, Bluetooth, advanced mobile phone services (AMPS), global systems for mobile communications (GSM), code division multiple access (CDMA), local multi-point distribution systems (LMDS), multi-channel multi-point distribution systems (MMDS), and/or variations thereof. In another embodiment of the invention, the digital signal processor730bmay be coupled to the phase shifters770band may comprise an integrated digital controller with multiple inputs and outputs, such as a transmit data output and a receive data input.

In the illustrated receiver node710b, each of the phase shifters770bis coupled to a corresponding one of the antennas740b. In one embodiment, each of the phase shifters770bmay provide 0 to 360 degrees of phase shifts to the received signals.

InFIG. 8B, the phase shifters770bare shown to be coupled to the adder780b. The adder780bis then coupled to the frequency mixers760band then to the intermediate processing stages750b. One of the frequency mixers760bmay comprise an I path mixer (or for mixing a sine waveform) and another one of the frequency mixers760bmay comprise a Q path mixer (or for mixing a cosine waveform). Each of the intermediate processing stages750bmay comprise a filter and/or a variable gain amplifier (VGA).

In an exemplary operation of the illustrated receiver node710bofFIG. 8B, the phase shifters770breceive inbound RF signals from the antennas740bvia respective one of the low noise amplifiers (LNAs)755bcoupled between the antennas740band the phase shifters770b. Each of the phase shifters770bthen respectively phase shifts the RF signals. The phase-shifted RF signals are then combined by the adder780binto combine-phase-shifted RF signals (e.g., having a first 0 to 360 degrees of phase shifts and a second 0 to 360 degree of phase shifts).

The frequency mixers760bthen respectively mix the combined RF signals into a first mixed signals (e.g., having a sine waveform) and a second mixed signals (e.g., having a cosine waveform). The intermediate processing stages750bthen preliminarily process the first and second mixed signals, respectively (e.g., by filtering and/or amplifying the signals) to produce preliminarily processed signals. The digital signal processor (or communications controller)730bmay then recover and/or further process the raw data from the preliminarily processed signals in accordance with the particular communications standard in use.

In view of the forgoing, an exemplary embodiment of the present invention provides an RF phase shifter. The RF phase shifter may comprise a transconductor, a 90 degrees phase shifting circuit, a gain controller, and/or an adder. The transconductor produces first and second currents from an input voltage. The 90 degrees phase shifting circuit is coupled to the transconductor and generates 90 degree phase shift between these two currents. The gain controller is providing a first gain to the first current and a second gain to the second current. The adder is coupled to the first and second parts of the 90 degrees phase shifting circuit and adds the first current with the second current, where the two currents may have 90 degrees phase difference and may have different amplitudes. In this exemplary RF phase shifter, when the gain controller is turned off, the 90 degrees phase shifting circuit provides the first current and the second current with a phase angle of 90 degrees with respective to each other and/or with equal amplitudes and the adder then adds the first current and the second current to generate an output current having a phase angle of 45 degrees with respective to the first current; and, when the gain controller is turned on, the gain controller provides the first gain and the second gain to the first and second currents to vary the amplitudes of the first and/or second currents and/or to vary the phase angle of the output current with respect to the first current.

In one exemplary embodiment of the present invention, an RF phase shifter may comprise a first capacitor, a first resistor, a second resistor, a second capacitor, at least one input node, at least one output node, a first gain controller, and a second gain controller. The first capacitor has a first capacitor node and a second capacitor node. The first resistor is coupled between the first capacitor node and a ground. The second resistor has a first resistor node and a second resistor node. The second capacitor is coupled between the first resistor node and the ground. The at least one input node is coupled to the first capacitor node and the first resistor node. The at least one output node is coupled to the second capacitor node and the second resistor node. The first gain controller is coupled to the first capacitor node, and the second gain controller is coupled to the first resistor node. In this exemplary embodiment, the first capacitor and the first resistor and the second resistor and the second capacitor provide first and second signals with 90 degrees different in phase angle; the first gain controller provides a first gain to the first signal and the second gain controller provides a second gain to the second signal; and the at least one output node adds the first signal with the second signal to provide a third signal having a desired phase angle with respect to the first signal. The desired phase angle can range from about 0 to 360 degrees with respect to the first signal.

In one exemplary embodiment of the present invention, an RF communication system includes a transmit node for transmitting RF signals and a receive node having a plurality of antennas for receiving the RF signals. The receive node has a plurality of phase shifters, each of the phase shifters coupling a respective one of the antennas and having a transconductor, a 90 degrees phase shifting circuit, a gain controller, and an adder. The transconductor produces first and second currents from an input voltage. The 90 degrees phase shifting circuit is coupled to the transconductor and has first and second circuit portions for providing the first and second currents with a 90 degrees difference in phase angle. The gain controller is for providing a first gain to the first current and a second gain to the second current. The adder is coupled to the first and second parts of the 90 degrees phase shifting circuit and adds the first and second current. In this exemplary embodiment, when the gain controller is turned off, the 90 degrees phase shifting circuit provides the first current and the second current with a phase angle of 90 degrees with respect to each other; and, when the gain controller is turned on, the gain controller provides the first gain and the second gain to the 90 degrees phase shifting circuit to vary the amplitude of the first current and/or the amplitude of the second current and the adder adds the first and second currents with the varied amplitude(s) to generate an output current with a desired phase angle with respect to the first current.

In one embodiment of the invention, the receiver node710bmay receive a plurality of wireless signals via the receive antennas740b. Each of M phase shifters770bcoupled to each of the M receive antennas740bmay be set to operate in a bypass mode or with an arbitrary phase setting. Corresponding signal strengths of M signals generated when each of the M phase-shifters770bis coupled to each of the M receive antennas740bmay be measured, while at least a portion of the M receive antennas740bare turned off. Selecting one of the M generated signals for processing without the use of an antenna switch, based on the measured signal strength.

Each of the plurality of received wireless signals may be amplified by the LNAs755bprior to the measuring. An in-phase (I) component and/or a quadrature (Q) component may be generated for each of the M generated signals using the frequency mixers760b. Each of the generated in-phase (I) component and/or the quadrature (Q) component for each of the M generated signals may be filtered by the baseband/IF stages750bto obtain filtered signals. Each of the filtered signals may be analog-to-digital converted by the A/D converters745bto generate digital signals. A signal strength of each of the filtered signals may be measured, for example, by a signal strength measuring block or other suitable circuit (not pictured). One of the filtered signals may then be selected for processing by the DSP730bby turning off the other paths without the use of an antenna switch, based on the measured signal strength of each of the filtered signals.

FIG. 8Cillustrates the receive node ofFIG. 7without the use of phase shifters, in accordance with an embodiment of the invention. Referring toFIG. 8C, the receiver node710cmay use the same circuits as the receiver node710bofFIG. 8B. However, to further simplify the receiver node710b, the phase-shifters770bhave been removed in the embodiment710cinFIG. 8C.

A plurality of wireless signals may be received by the receiver node710cvia the receive antennas740c. Each of the plurality of wireless signals received via the receive antennas740cmay be amplified by the LNAs755cto generate amplified signals. A signal strength of each of the generated amplified signals may be measured by a signal strength measuring block while the other amplifiers are turned off or while at least a portion of the receive antennas740care turned off. The signal strength measuring block (not pictured inFIG. 8C) may be located anywhere along the signal processing path, after the LNAs755c. For example, a signal strength measuring block may be located after the baseband/IF processing stages750cfor measuring signal strength.

One of the amplified signals may be selected for processing by the DSP730cby turning off at least a portion of the remaining other receive paths without the use of an antenna switch, based on the measured signal strength of each of the amplified signals. The frequency mixers760cmay generate an in-phase (I) component and/or a quadrature (Q) component for each of the amplified signals. Each of the generated in-phase (I) component and/or the quadrature (Q) component for each of the amplified signals may be filtered by the baseband/IF blocks750cto obtain filtered signals. The A/D converters745cmay analog-to-digital convert each of the filtered signals to generate digital signals. Signal strength of each of the filtered signals may be measured, for example, after the baseband/IF blocks750c. One of the filtered signals may be selected by turning off the other paths for processing by the DSP730cwithout the use of an antenna switch, based on the measured signal strength of each of the M filtered signals.

In one embodiment of the invention, a method for processing signals in the receiver710cmay comprise receiving a plurality of wireless signals via a plurality of M receive antennas740c. Each of the plurality of wireless signals received via the plurality of M receive antennas740cmay be amplified using the LNAs755cto generate M amplified signals. At least two measurements of signal strength of the M amplified signals may be made, while turning off at least a portion of said plurality of M receive antennas. For example the at least two measurements may be performed while N receive antennas, selected from the M receive antennas740c, are turned off, where N is smaller than M. At least one of the M amplified signals may be selected for processing by the DSP730cwithout the use of an antenna switch, based on the at least two measurements of signal strength.

In yet another embodiment of the invention, a system for processing signals in the receiver710cmay comprise one or more receiver processing circuits that enable receiving of a plurality of wireless signals via a plurality of M receive antennas740c. The one or more receiver processing circuits may enable amplification of each of the plurality of wireless signals received via the plurality of M receive antennas740cto generate M amplified signals. The one or more receiver processing circuits may enable making at least two measurements of signal strength of the M amplified signals, while turning off at least a portion of said plurality of M receive antennas. For example the at least two measurements may be performed while N receive antennas, selected from the M receive antennas740c, are turned off, where N is smaller than M. The one or more receiver processing circuits may enable selection of at least one of the M amplified signals for processing by the DSP730cwithout the use of an antenna switch, based on the at least two measurements of signal strength.

FIG. 8Dillustrates exemplary steps for processing signals within a receiver, in accordance with an embodiment of the invention. Referring toFIGS. 8B and 8D, at802d, a plurality of wireless signals may be received via the receive antennas740b. At804d, each of M phase shifters coupled to each of the M receive antennas may be set to operate in a bypass mode or with an arbitrary phase setting. At806d, corresponding signal strengths of M signals generated when each of the M phase-shifters is coupled to each of the M receive antennas may be measured, while at least a portion of the M receive antennas are turned off. At808d, one of the M generated signals may be selected for processing without the use of an antenna switch, based on the measured signal strength.

FIG. 8Eillustrates exemplary steps for processing signals within a receiver, in accordance with an embodiment of the invention. Referring toFIGS. 8C and 8E, at802e, a plurality of wireless signals may be received via the receive antennas740c. At804e, the LNAs755cmay amplify each of the plurality of wireless signals received via the receive antennas740cto generate amplified signals. At806e, signal strength of each of the amplified signals may be measured along the signal processing path within the receiver node710cwhile at least a portion of the remaining amplifiers (LNAs) are turned off or at least a portion of the receive antennas740care turned off. At808e, the DSP730cmay select one of the amplified signals for processing without the use of an antenna switch by turning off the other paths, based on the measured signal strength of each of the generated M amplified signals.

Certain embodiments of the invention may comprise a machine-readable storage having stored thereon, a computer program having at least one code section for processing signals in a receiver, the at least one code section being executable by a machine for causing the machine to perform one or more of the steps described herein.