Memory device comprising a top via electrode and methods of making such a memory device

An illustrative device disclosed herein includes at least one layer of insulating material, a conductive contact structure having a conductive line portion and a conductive via portion and a memory cell positioned in a first opening in the at least one layer of insulating material. In this illustrative example, the memory cell includes a bottom electrode, a memory state material positioned above the bottom electrode and an internal sidewall spacer positioned within the first opening and above at least a portion of the memory state material, wherein the internal sidewall spacer defines a spacer opening and wherein the conductive via portion is positioned within the spacer opening and above a portion of the memory state material.

BACKGROUND OF THE INVENTION

Field of the Invention

The present disclosure generally relates to the fabrication of integrated circuits, and, more particularly, to various novel embodiments of a memory device comprising a top via electrode and various novel methods of making such a memory device.

Description of the Related Art

In many modern integrated circuit products, embedded memory devices and logic circuits (e.g., microprocessors) are formed on the same substrate or chip. Such embedded memory devices may come in a variety of forms, e.g., an MTJ (magnetic tunnel junction) memory device, an RRAM (resistive random access memory) device, a PRAM (phase-change random access memory) device, an MRAM (magnetic random access memory) device, a FRAM (ferroelectric random access memory) device, etc. Typically, all of the embedded memory devices have a top electrode to which a conductive contact structure must be formed for the device to be operational.

Various techniques have been employed to try to form such a conductive contact structure to the top electrode of such a memory device. Typically, after the top electrode is formed, it is covered by a layer of insulating material. At some point later in the process flow, the upper surface of the top electrode must be exposed to allow for formation of the conductive contact structure. One technique involves etching a trench into the layer of insulating material so as to expose or “reveal” the top electrode. This necessitates that the bottom of the trench extends past the upper surface of the top electrode. One problem with this technique is that it typically requires that the top electrode be made relatively thicker so as to provide an increased process window and reduce the chances of the trench exposing other parts of the memory device, leading to the creation of an undesirable electrical short that would render the memory device inoperable. Another manufacturing technique that is commonly employed involves directly patterning (via masking and etching) a via that is positioned and aligned so as to expose the upper surface of the top electrode. One problem with this approach is the fact that, as device dimensions continue to shrink, it is very difficult to properly align the via such that it only exposes a portion of the upper surface of the top electrode. Any misalignment of the via relative to the top electrode can result in undesirable exposure of the sidewalls of the top electrode, which can also lead to undesirable electrical shorts and device inoperability. Additionally, these processing steps lead to higher manufacturing costs and require the use of additional masking layers.

The present disclosure is generally directed to various novel embodiments of memory device comprising a top via electrode and various novel methods of making such a memory device that may at least reduce one or more of the problems identified above.

SUMMARY

Generally, the present disclosure is directed to various novel embodiments of a memory device comprising a top via electrode and various novel methods of making such a memory device. An illustrative device disclosed herein includes at least one layer of insulating material, a conductive contact structure having a conductive line portion and a conductive via portion and a memory cell positioned in a first opening in the at least one layer of insulating material. In this illustrative example, the memory cell includes a bottom electrode, a memory state material positioned above the bottom electrode and an internal sidewall spacer positioned within the first opening and above at least a portion of the memory state material, wherein the internal sidewall spacer defines a spacer opening and wherein the conductive via portion is positioned within the spacer opening and above a portion of the memory state material.

An illustrative method disclosed herein includes forming a generally U-shaped spacer structure above a memory state material of a memory cell, forming at least one layer of insulating material above the generally U-shaped spacer structure and forming a contact opening in the at least one layer of insulating material, whereby the contact opening exposes the generally U-shaped spacer structure. In this example, the method also includes performing an etching process through the contact opening on the generally U-shaped spacer structure so as to remove a portion of the generally U-shaped spacer structure and thereby form an internal sidewall spacer positioned above at least a portion of the memory state material, wherein the internal sidewall spacer defines a spacer opening that exposes at least a portion of the memory state material and forming a conductive contact structure in the contact opening, the conductive contact structure having a conductive line portion and a conductive via portion, wherein the conductive via portion is formed in the spacer opening and wherein the conductive via portion contacts the memory state material.

DETAILED DESCRIPTION

As will be readily apparent to those skilled in the art upon a complete reading of the present application, the presently disclosed structures and method may be applicable to a variety of products, stand-alone memory products, embedded memory products, etc. The various components, structures and layers of material depicted herein may be formed using a variety of different materials and by performing a variety of known process operations, e.g., chemical vapor deposition (CVD), atomic layer deposition (ALD), a thermal growth process, spin-coating techniques, etc. The thicknesses of these various layers of material may also vary depending upon the particular application. With reference to the attached figures, various illustrative embodiments of the methods and devices disclosed herein will now be described in more detail.

FIGS.1-16depict various novel embodiments of a memory device101comprising a top via electrode on an IC product100and various novel methods of making such a memory device101. The IC product100will be formed on and above a semiconductor substrate (not shown). The semiconductor substrate may have a variety of configurations, such as a bulk silicon configuration. The substrate may also have a semiconductor-on-insulator (SOI) configuration that includes a base semiconductor layer, a buried insulation layer and an active semiconductor layer positioned above the buried insulation layer, wherein transistor devices (not shown) that are formed on the substrate are formed in and above the active semiconductor layer. The substrate may be made of silicon or it may be made of materials other than silicon. Thus, the terms “substrate” or “semiconductor substrate” should be understood to cover all semiconducting materials and all forms of such materials.

In general, and with reference toFIG.1, in one illustrative embodiment, the IC product100comprises a memory region102where one or more memory devices101will be formed and a logic region104where one or more logic circuits (e.g., microprocessor circuits) will be formed in and above a semiconductor substrate (not shown in the attached figures). As is typical, the IC product100includes a plurality of metallization layers that constitute the overall wiring pattern for the IC product100. These metallization layers may be formed on the IC product100by performing traditional manufacturing processes. These metallization layers are typically comprised of layers of insulating material (e.g., silicon dioxide, a low-k insulating material) with a plurality of conductive metal lines and conductive vias formed in the layers of insulating material. The conductive metal lines are routed across the substrate in various patterns and arrangements and provide the means for intra-layer electrical communication between the devices and structures formed on or above the substrate. The conductive vias provide the means for allowing inter-level electrical communication between the conductive metal lines in adjacent metallization layers. The first metallization layer of an IC product is typically referred to as the “M1” layer (or in some cases the “M0” layer), while the conductive vias that are used to establish electrical connection between the M1 layer and the conductive lines in the immediately adjacent upper metallization layer (the “M2 layer) are typically referred to as “V1” vias. So-called device level contacts (not shown) are formed above the substrate so as to provide electrical communication between the various devices, e.g., transistors, resistors, etc., that are formed on or immediately adjacent the semiconductor substrate.

FIG.1depicts the IC product100after several process operations were formed. More specifically,FIG.1depicts the IC product100at a point in time wherein an illustrative (and representative) metallization layer105was formed above the semiconductor substrate (not shown). As will be appreciated by those skilled in the art after a complete reading of the present application, the metallization layer105is intended to be representative of any metallization layer that may be formed on the IC product100irrespective of its location relative to an upper surface of the semiconductor substrate or any of the other metallization layers formed on the IC product100.

With continued reference toFIG.1, the IC product100is depicted at a point in time where a layer of insulating material106, e.g., silicon dioxide, for a representative metallization layer—Mx—of the IC product100has been formed above the semiconductor substrate. As noted above the Mx metallization layer is intended to be representative of any metallization layer formed at any level on the IC product100. In the example shown inFIG.1, various illustrative conductive metal lines108have been formed in the layer of insulating material106in both the memory region102and the logic region104. The number, size, shape, configuration and overall routing of the metal lines108may vary depending upon the particular application. In one example, the conductive metal lines108are elongated features that extend across the IC product100in a direction that is transverse to the plane of the drawing inFIG.1. The metal lines108may be comprised of any of a variety of different conductive materials, e.g., copper, aluminum, tungsten, etc., and they may be formed by traditional manufacturing techniques, e.g., by performing a damascene process for cases where the conductive lines108are made of copper and perhaps by performing traditional deposition and etching processes when the conductive lines108are made of a conductive material that may readily be patterned using traditional masking and patterning (e.g., etching) techniques.

Also depicted inFIG.1is a layer of insulating material112that was blanket-deposited on the IC product100. If desired, a planarization process may be performed on the layer of insulating material112to substantially planarize its upper surface. The layer of insulating material112is representative in nature is that it may represent a single layer of material or multiple layers of material. The single or multiple layers of insulating material112may be comprised of a variety of different insulating materials, e.g., silicon carbon nitride (SiCN), SiN, Al2O3, HfOx, SiO2, SiON, SiOCN, etc., and its vertical thickness may vary depending upon the particular application.

Next, a patterned etch mask (not shown) was formed on the IC product100. This particular patterned etch mask covers the logic region104but exposes portions of the layer of insulating material112at locations in the memory region102where it is desired to establish electrical contact with the conductive lines108formed in the layer of insulating material106within the memory region102. At that point, an etching process was performed through the patterned etch mask (not shown) so as to remove exposed portions of the layer of insulating material112in the memory region102. This etching process operation results in the formation of overall contact openings111that extend through the layer of insulating material112and thereby expose at least a portion of the upper surface of the conductive lines108in the memory region102. At that point, the patterned etch mask may be removed. Then, a conductive via114was formed in each of the openings111by performing traditional manufacturing processing techniques, e.g., by performing a deposition process so as to overfill the openings111in the memory region102with conductive material(s), followed by performing a chemical mechanical planarization (CMP) process operation and/or a dry etch-back process to remove the excess amounts of the conductive material for the conductive vias114that are positioned on or above the upper surface of the layer of insulating material112. In one illustrative embodiment, when viewed from above, the conductive vias114may have a substantially circular configuration. In other situations, the conductive vias114may have a substantially oval configuration. The vertical thickness of the illustrative vias114may vary depending upon the particular application, and they may be comprised of a variety of conductive materials, e.g., copper, tungsten, aluminum, TiN, TaN, etc. The conductive vias114may be comprised of the same material of construction as that of the conductive metal line108to which it is conductively coupled, but that may not be the case in all applications. Of course, as will be appreciated by those skilled in the art after a complete reading of the present application, various barrier layers or liner layers (neither of which is shown) may be formed as part of the process of forming the illustrative conductive lines108and the conductive vias114. Moreover, various additional conductive structures that will be formed on the IC product100, as discussed more fully below, may or may not include such illustrative barrier layers and/or liner layers, which are not depicted so as to not overly complicate the attached drawings.

As will be appreciated by those skilled in the art after a complete reading of the present application, the present disclosure is directed to the formation of a conductive top via electrode for a memory cell101, as described more fully below. The memory cell101depicted herein is intended to be generic and representative in nature. By way of example only, and not by way of limitation, the generic memory cells101depicted herein may take a variety of forms, have a variety of different configurations and may comprise different materials. For example, the memory cells101depicted herein may be an RRAM (resistive random access memory) device, an MTJ (magnetic tunnel junction) memory device, a PRAM (phase-change random access memory) device, an MRAM (magnetic random access memory) device, a FRAM (ferroelectric random access memory) device, etc. Such a memory cell101includes some form of a memory state material118that is typically positioned between a bottom electrode and a top electrode, e.g., the switching layer in an RRAM device. In some applications, some characteristic of the memory state material118, e.g., resistivity, may be altered by the application of an electrical charge to the memory device101, and these altered states may be representative of a logical “1” or a logical “0” in a digital circuit. In some situations, the memory state material118may actually store an electrical charge. In any event, sensing circuitry on the IC product100may be used to sense the state of the memory state material118, to determine whether or not a particular memory cell101represents a logical “1” or a logical “0” and use that information within the various circuits on the IC product100. The particular materials used for the memory state material118may vary depending upon the particular type of memory device that is fabricated. Moreover, the single layer of memory state material118depicted in the drawings is intended to be representative in that, in a real-world device, the memory state material118may comprise a plurality of layers of material. Thus, the reference to any “memory state material” in the specification and in the attached claims should be understood to cover any form of any material(s) that may be employed on any form of a memory device that can be manipulated or changed so as to reflect two opposite logical states of the memory device. For purposes of disclosing the subject matter herein, the memory cell101will be depicted as being an RRAM device, but the presently disclosed subject matter should not be considered to be limited to RRAM devices.

FIG.2depicts the IC product100after several process operations were performed. First, a layer of bottom electrode conductive material116was formed above the layer of insulating material112such that it conductively contacts the conductive vias114. The layer of bottom electrode conductive material116may be formed to any desired thickness and it may comprise any conductive material, e.g., copper, tungsten, ruthenium, aluminum, Ta, Ti, TaN, TiN, etc. As will be appreciated by those skilled in the art after a complete reading of the present application, a portion of the layer of bottom electrode conductive material116will become the bottom electrode for each of the memory cells101disclosed herein. Thereafter, a layer of memory state material118was formed above the layer of bottom electrode conductive material116. The layer of memory state material118may be formed to any desired thickness and it may comprise any of a variety of different materials, e.g., stoichiometric ZrO2, ZnO, HfO2, a doped metal oxide, phase-change chalcoenides (GeSbTe, AgInSbTe), binary transition metal oxide (NiO or TiN), perovskites (e.g., SrTiO3), solid-state electrolytes (GeS, GeSe, SiOx), organic charge-transfer complexes (CuTCNQ), organic donor-acceptor systems (AlDCN), two dimension insulating materials (e.g., boron nitride), etc.

Next, a sacrificial layer of material120was formed above the memory state material118. The sacrificial layer of material120may be formed to any desired thickness and it may comprise any of a variety of different materials, e.g., amorphous silicon, amorphous carbon, SiO2, SOH, SiON, SiOCN, etc. In some applications, a chemical mechanical planarization (CMP) process operation and/or a dry etch-back process may be performed to planarize the upper surface of the sacrificial layer of material120. At that point, a patterned etch mask122was formed above the sacrificial layer of material120. The patterned etch mask122exposes portions of the memory region102and all of the logic region104. The patterned etch mask122may be made by performing known manufacturing techniques and it may be comprised of a variety of different materials, e.g., photoresist, organic planarization layer (OPL), silicon nitride, silicon dioxide, SiON, etc.

FIG.3depicts the IC product100after one or more etching processes were performed through the patterned etch mask122to remove exposed portions of the sacrificial layer of material120, the layer of memory state material118and the first layer of bottom electrode conductive material116. Note that, during these etching processes, the layer of insulating material112may be slightly recessed. As will be appreciated by those skilled in the art after a complete reading of the present application, the patterned portions of the sacrificial layer of material120are dummy or sacrificial placeholders for the area or volume where a top via electrode130(described below) and an internal sidewall spacer128S (described below) will be formed after the patterned portions of the sacrificial layer of material120are removed.

FIG.4depicts the IC product100after several process operations were performed. First, the patterned etch mask122was removed. Then, a conformal deposition process was performed to form a conformal encapsulation layer123across the product100. The conformal encapsulation layer123may be of any desired thickness, e.g., several to hundreds of nanometers, and it may be comprised of any of a variety of different materials, e.g., SiN, SiC, SiCN, SiOCN, Al2O3, HfOx, etc.

FIG.5depicts the IC product100after several process operations were performed. First, a layer of insulating material124was formed in both the memory region102and the logic region104. The layer of insulating material124is intended to be representative in nature as it may in fact comprise multiple layers of material. As initially formed, the layer of insulating material124may overfill the spaces between the regions of the patterned material layers120/118/116. At that point, a CMP process may be performed to remove a portion of the vertical thickness of the layer of insulating material124until such time as the upper surface124S of the layer of insulating material124is substantially coplanar with the upper surface120S of the sacrificial layer of material120. As depicted, this process operation removes portions of the conformal layer123positioned above the upper surface120S of the sacrificial layer of material120and exposes the portions of the sacrificial layer of material120in the memory region102for further processing. The layer of insulating material124may be initially formed to any desired thickness. The layer of insulating material124should be made of a material that exhibits good etch selectivity to the material of the sacrificial layer of material120. In general, the layer of insulating material124may be comprised of any of a variety of different materials, e.g., a low-k material (k value of 3.9 or less) SOH, SiOC, SiOCN, silicon dioxide, etc.

FIG.6depicts the IC product100after one or more etching processes were performed to remove the exposed portions of the sacrificial layer of material120selectively relative to the surrounding materials. These process operations result in the formation of a cavity126that exposes the layers of memory state material118in the memory region102.

FIG.7depicts the IC product100after a conformal deposition process was performed to form a conformal layer of spacer material128across the product100and in the cavities126. The layer of spacer material128may be of any desired thickness, e.g., 1-100 nm, and it may be comprised of any of a variety of different materials, e.g., SiN, SiCN, SiOCN, SiC, SiOC, Al2O3, amorphous silicon, etc.

As will be described more fully below, in one illustrative process flow, the layer of spacer material128may be made relatively thick such that the top via electrode130(described below) for the memory device101will occupy a relatively smaller volume of the cavity126as compared to the volume of the cavity126occupied by the internal sidewall spacer128S. Moreover, using the methods and devices disclosed herein, the top via electrode130may be substantially smaller, e.g., in terms of volume and/or physical dimensions (vertical height, lateral width, etc.), as compared to the top electrode on prior art memory cells.

FIG.8depicts the product100after a layer of sacrificial protective material129, e.g., was formed on the layer of spacer material128. As depicted, the layer of sacrificial protective material129overfills the recesses in the layer of spacer material128.

FIG.9depicts the product100after a recess etching process was performed on the layer of sacrificial protective material129to remove a portion of the vertical thickness of the layer of sacrificial protective material129. As depicted, at the end of this recess etching process, some of the material of the layer of sacrificial protective material129remains positioned in the recesses in the layer of spacer material128.

FIG.10depicts the product100after an anisotropic etching process, i.e., a spacer chamfering process, was performed to remove horizontally positioned portions of the layer of spacer material128. As depicted, during this spacer chamfering process, the remaining portions of the layer of sacrificial protective material129protect the underlying layer of spacer material128. This etching process results in the formation of a generally U-shaped structure128X (when viewed in a vertical cross-section through the structure128X) comprised of the layer of spacer material128.

FIG.11depicts the IC product100after several process operations were performed. First, the remaining portions of the layer of sacrificial protective material129were removed. Next, a layer of insulating material134was formed in both the memory region102and the logic region104. The layer of insulating material134is intended to be representative in nature as it may in fact comprise multiple layers of material. At that point, a CMP process may be performed to planarize the upper surface of the layer of insulating material134. The layer of insulating material134may be initially formed to any desired thickness. In general, the layer of insulating material134may be comprised of any of a variety of different materials, e.g., a low-k material (k value of 3.9 or less) SOH, SiOC, SiOCN, silicon dioxide, etc. In some cases, the layer of insulating material134and the layer of insulating material124may comprise the same material, but that may not be the case in all applications.

At the point of processing depicted inFIG.11, various process operations may be performed to form various contact openings in the various layers of material for various conductive contact structures to be formed in the next metallization layer—Mx+1—of the IC product100. As will be appreciated by those skilled in the art after a complete reading of the present application, there are several possible process flows for forming such conductive contacts. Accordingly,FIG.12depicts the product100after oner or more patterned etch masks (not shown) were formed above the product100and after various etching process operations were performed to form contact openings135for the memory cells101and a contact opening136in the logic region104for contacting the metal line108in the logic region104. The conductive contact openings135expose the generally U-shaped structure128X. The conductive contact opening136exposes the metal line108in the logic region104.

FIG.13depicts the product100after an anisotropic etching process was performed to remove the portions of the structure128X previously protected by the layer of sacrificial protective material129(seeFIG.10). This process operation results in the formation of the above-mentioned internal sidewall spacer128S in each of the cavities126above at least a portion of the layer of memory state material118. In one particular example, the internal sidewall spacer128S may be formed such that it is positioned on and in physical contact with an upper surface of the memory state material118. The internal sidewall spacer128S has a spacer opening128Y. The internal sidewall spacers128S may be of any desired thickness (as measured at its base), e.g., 1-100 nm. In one particular embodiment, the thickness of the internal sidewall spacer128S may be such that the spacer occupies approximately 10-90% of the volume of the cavity126. In one particular embodiment, the thickness of the internal sidewall spacer128S may be such that the spacer occupies at least 50% of the volume of the cavity126.

FIGS.14and15depict the product100after various process operations were performed to form a conductive contact structure138in each of the contact openings135and a conductive contact structure140in the contact opening136.FIG.15is a vertical cross-sectional view taken through the memory cell101where indicated inFIG.14, i.e., a cross-sectional view that is transverse to the cross-sectional view shown inFIG.14.FIG.16is a view of just the conductive contact structure138shown inFIG.15. As will be appreciated by those skilled in the art, the memory cells101disclosed herein may be arranged in an array on the IC product, i.e., additional memory cells101are formed in front and in back of the two illustrative memory cells101shown inFIG.14. With reference toFIGS.15and16, the conductive contact structure138is a one-piece (unitary) structure that comprises a line type portion138A and a plurality of downward extending conductive via portions138B that are positioned in the opening128Y in the internal sidewall spacer128S. Each of the conductive vias138B constitute a top via electrode130for each of the memory cells101.

The conductive contact structures138,140may be formed using a variety of techniques. In one example, various conformal liners and/or barrier layers may be formed in the trench/via openings. Thereafter, a conductive material, such as tungsten, may be deposited so as to overfill the remaining portions of the contact openings135,136. At that point, a CMP process operation may be performed to remove all conductive material positioned above the upper surface of the layer of insulating material134. Note that a portion of the conductive contact structure138is positioned on and in physical contact with an upper surface of the internal sidewall spacer128S.

As mentioned above, in one illustrative embodiment, the top via electrode130disclosed herein may be significantly smaller in size (in terms of volume and/or physical dimensions) as compared to top electrode structures on prior art memory cells. For example, in one embodiment, the combination of the internal sidewall spacer128S and the top via electrode130define a combined volume wherein the internal sidewall spacer128S occupies a first portion of the combined volume and the top via electrode130occupies a second portion of the combined volume, wherein the first portion is greater than the second portion. In some embodiments, the first portion—the portion of the combined volume occupied by the internal sidewall spacer128S—is about 10-90% of the combined volume, and the second portion—the portion of the combined volume occupied by the top via electrode130—is at most about 10-90% of the combined volume according to memory cell design and performance request. Stated another way, the internal sidewall spacer128S may occupy a first volume of the cavity126and the top via electrode130may occupy a second volume of the cavity, wherein the first volume is greater than the second volume. In one particular embodiment, the thickness of the internal sidewall spacer128S may be such that the top via electrode130occupies less than 50% of the volume of the cavity126. When viewed from above, in the case where the internal sidewall spacer128S has a substantially circular ring type structure, the internal sidewall spacer128S may have an outer diameter of about several nanometers to several micrometers, while the diameter of the spacer opening128X may be about 50% of the whole area. Similarly, when viewed from above, the top via electrode130may be a substantially cylindrical type structure having a diameter several nanometers to several micrometers depending upon the desired performance characteristics of the memory cell. Of course, as will be appreciated by those skilled in the art after a complete reading of the present application, the internal sidewall spacer128S and the top via electrode130have a different configuration than that depicted in the drawings, e.g., they both may have a substantially square configuration when viewed from above.

By making the top via electrode130disclosed herein relatively smaller than the top electrode on prior art memory cells, several benefits may be achieved. For example, the relatively smaller top via electrode130disclosed herein is useful to confine the conduct filament with a localized electrical field in the memory cell101, thereby leading to a memory cell101with highly stable endurance and data retention capabilities.