Memory device and data processing device

According to one embodiment, a memory device includes one or more semiconductor devices connected in common to a bus. Each of the one or more semiconductor devices includes a memory unit to store data, and an input/output control unit. The input/output control unit is configured to acquire address information from a data processing device via the bus and access the memory unit according to the acquired address information. The data processing device is configured to divide the address information into a plurality of cycles to transmit to the bus. The input/output control unit is configured to switch a number of cycles in which the address information is to be acquired, according to setting information acquired from the data processing device.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2017-167201, filed on Aug. 31, 2017; the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to a memory device and a data processing device.

BACKGROUND

Data processing devices such as central processing units (CPUs), when accessing a nonvolatile memory device, transmit a command and then transmit address information over a predetermined number of cycles. In these years, as the capacity of the nonvolatile memory device is increasing, address information is increasing in size.

Nonvolatile memory devices (Multi-Dies) including multiple semiconductor chips are known. When accessing the nonvolatile memory device including multiple semiconductor chips, a CPU transmits address information including information to select a chip (a chip address). The chip address is, for example, three bits of information and can identify eight chips. When the chip address included in the address information coincides with its own identification value, each semiconductor chip performs data write or read or so on. On the other hand, when the chip address included in the address information does not coincide with its own identification value, each semiconductor chip does not perform data write nor read nor so on.

The nonvolatile memory device can be configured to include only one semiconductor chip. In this case, when receiving address information, the semiconductor chip performs data write or read or so on every time without referring to the chip address.

However, the CPU transmits address information including a chip address regardless of whether the nonvolatile memory device is configured to include only one semiconductor chip or multiple ones. Thus, in a system using the nonvolatile memory device configured to include only one semiconductor chip, the CPU has to transmit address information including a chip address, although the chip address is not used. Further, the semiconductor chip may have to perform an extra acquisition process for the unused chip address.

DETAILED DESCRIPTION

In general, according to one embodiment, a memory device including one or more semiconductor devices connected in common to a bus is provided. Each of the one or more semiconductor devices includes a memory unit to store data; and an input/output control unit. The input/output control unit is configured to acquire address information from a data processing device via the bus and access the memory unit according to the acquired address information. The data processing device is configured to divide the address information into a plurality of cycles to transmit to the bus. The input/output control unit is configured to switch a number of cycles in which the address information is to be acquired, according to setting information acquired from the data processing device.

A memory device30and a data processing device20according to embodiments will be described in detail below with reference to the accompanying drawings. The present invention is not limited to these embodiments.

First Embodiment

FIG. 1is a block diagram illustrating the configuration of an information processing device10.

The information processing device10comprises the data processing device20and the memory device30. The data processing device20is a processing circuit such as a CPU. The data processing device20may be another device, not being limited to a CPU, as long as the device can access the memory device30.

The memory device30is a storage to store data and accessed by the data processing device20. The memory device30incorporates one or more semiconductor chips of the same type in its package.

The data processing device20and the memory device30are connected via a bus (I/O[7:0]). The data processing device20transmits commands and address information to the memory device30via the bus. Further, the data processing device20and the memory device30transmit and receive data via the bus. In this example, the bus is eight bits wide but, not being limited to the eight bit width, may have another bit width.

The data processing device20, after transmitting a command, transmits address information designating the area to access through the command to the bus. In this case, the data processing device20divides the address information temporally into multiple cycles to transmit to the bus.

Further, the data processing device20transmits various control signals to the memory device30via corresponding dedicated lines. For example, the data processing device20transmits a chip enable signal (CEn), a command latch enable signal (CLE), an address latch enable signal (ALE), a write enable signal (WEn), a read enable signal (REn), and a write protect signal (WPn) to the memory device30. The data processing device20may transmit control signals other than these to the memory device30.

The information processing device10may comprise a control logic circuit between the data processing device20and the memory device30. In this case, the data processing device20may transmit some of the control signals via the control logic circuit to the memory device30.

FIG. 2is a block diagram illustrating the configuration of the memory device30.

The memory device30includes one or more semiconductor devices32. InFIG. 2, the memory device30includes eight semiconductor devices32, but the number of semiconductor devices32included in the memory device30is not limited to eight.

The one or more semiconductor devices32are the same type of semiconductor chips. The one or more semiconductor devices32are packaged to be treated as one device. If the memory device30has a plurality of semiconductor devices32, the plurality of semiconductor devices32may be stacked and packaged or laterally arranged and packaged.

The one or more semiconductor devices32are connected in common to the bus (I/O[7:0]) over which commands and data are transmitted. Thus, all of the one or more semiconductor devices32can receive commands and data transmitted from the data processing device20. And the data processing device20can receive data from all of the one or more semiconductor devices32. The one or more semiconductor devices32receive various control signals transmitted from the data processing device20in common.

Different identification values are assigned to the one or more semiconductor devices32. Each of the one or more semiconductor devices32receives a signal indicating an identification value assigned to itself. For example, if the memory device30has eight semiconductor devices32, each of the one or more semiconductor devices32receives an identification value of three bits.

FIG. 3is a block diagram illustrating the configuration of the semiconductor device32.

Each of the one or more semiconductor devices32includes circuits having functions as shown inFIG. 3. Each of the one or more semiconductor devices32includes a memory unit42, a control signal acquiring unit44, a mode register46, an input/output control unit48, a command register50, a memory control unit52, and an address register54.

The memory unit42stores data. In this example, the memory unit42is nonvolatile. Not being limited to being nonvolatile, the memory unit42may be volatile.

The memory unit42includes a memory cell array60, a data register62, a column decoder64, a row decoder66, and a sense amplifier68.

The memory cell array60includes multiple memory cells arranged in a matrix. Each of the memory cells is connected to one of multiple bit lines and one of multiple word lines. In the memory cell array60, by selecting one bit line and one word line, one memory cell is selected.

The memory cell includes, for example, a resistance change element. The resistance change element is connected between a corresponding bit line and a corresponding word line. When a predetermined voltage is applied, the resistance change element switches between a high resistance state and a low resistance state. The memory cell stores binary data by switching the resistance change element between these resistance states. Note that the memory cell may include another type of element that can store data instead of the resistance change element.

The data register62temporarily stores data acquired from the data processing device20in writing. The data register62temporarily stores data read from the memory cell array60in reading.

The column decoder64selects the bit lines connected to memory cells to be accessed based on address information acquired from the data processing device20. The row decoder66selects the word line connected to the memory cells to be accessed based on address information acquired from the data processing device20. The column decoder64and the row decoder66write data stored in the data register62into the memory cells connected to the selected bit lines and word line in writing.

The sense amplifier68reads data from the memory cells connected to the bit lines and word line selected by the column decoder64and the row decoder66in reading. Then the sense amplifier68writes the data read from the memory cells into the data register62in reading.

The control signal acquiring unit44acquires various control signals transmitted from the data processing device20. For example, the control signal acquiring unit44acquires the chip enable signal (CEn), command latch enable signal (CLE), address latch enable signal (ALE), write enable signal (WEn), read enable signal (REn), and write protect signal (WPn). The control signal acquiring unit44may acquire control signals other than these from the data processing device20. The control signal acquiring unit44gives the acquired control signals to the input/output control unit48and the memory control unit52.

The control signal acquiring unit44acquires a setting value assigned to itself via a setting value input terminal. Then the control signal acquiring unit44gives an acquired identification value to the input/output control unit48and the memory control unit52.

For example, the setting value input terminal of the semiconductor device32is connected to a power supply line or a ground line depending on the setting value in manufacturing. Thus, the control signal acquiring unit44can acquire the setting value assigned to itself.

In this example, the semiconductor device32includes a CADD0terminal, a CADD1terminal, and a CADD2terminal. And, in the example ofFIG. 3, the CADD0terminal is connected to a ground line; the CADD1terminal is connected to a power supply line; and the CADD2terminal is connected to the power supply line. Thus, an identification value of “011” (CADD0=0, CADD1=1, CADD2=1) is assigned to the semiconductor device32ofFIG. 3. Note that other identification values are assigned to the other semiconductor devices32.

The mode register46stores various setting values. The data processing device20can rewrite the various setting values stored in the mode register46. The setting information stored in the mode register46may be initially set to predetermined values at the time of factory shipment.

The input/output control unit48is connected to the data processing device20via the bus (I/O[7:0]). The input/output control unit48acquires a command, data, and address information from the data processing device20via the bus at timings identified by the various control signals acquired by the control signal acquiring unit44. Then the input/output control unit48accesses the memory unit42according to the acquired command, data, and address information. In this case, the input/output control unit48operates according to the various setting values stored in the mode register46.

For example, the input/output control unit48writes the command acquired from the data processing device20into the command register50. Further, the input/output control unit48writes the address information acquired from the data processing device20into the address register54. In writing, the input/output control unit48writes the data acquired from the data processing device20into the data register62in the memory unit42. In reading, the input/output control unit48reads data from the data register62in the memory unit42to transmit to the data processing device20via the bus.

The address register54stores the address information acquired by the input/output control unit48. The address information stored in the address register54is read into the column decoder64and the row decoder66in the memory unit42.

The command register50stores the command acquired by the input/output control unit48. The command stored in the command register50is read by the memory control unit52.

The memory control unit52controls the operation of the entire semiconductor device32according to the command stored in the command register50. When receiving a command (mode register write command) to instruct to write a setting value into the mode register46, the memory control unit52writes the setting value specified by the received command into the mode register46at a specified address. By this means, the memory control unit52can switch the operation mode or the like of the input/output control unit48according to the instruction from the data processing device20.

FIG. 4is a block diagram illustrating the function of transmitting address information, in the data processing device20. The data processing device20includes an address information generating unit72and an address transmitting unit74as the function for transmitting address information.

In writing or reading data into or from the memory device30, the address information generating unit72generates address information including a memory address and a chip address. The memory address is information designating an area to be accessed in the memory unit42. The memory units42each included in one of the one or more semiconductor devices32have a common address space. Thus, the data processing device20can access the memory units42each included in one of the one or more semiconductor devices32in a common way.

The chip address is information designating one semiconductor device32to be accessed from among the one or more semiconductor devices32. By this means, the data processing device20can access only any one designated semiconductor device32when the memory device30is configured to include a plurality of semiconductor devices32.

When the memory device30includes only one semiconductor device32(a single chip), the data processing device20can switch between transmitting address information including a memory address and a chip address and transmitting address information including a memory address but not a chip address. The address information generating unit72generates address information including a memory address and a chip address or address information including a memory address but not a chip address depending on a set mode.

The address transmitting unit74divides the address information generated by the address information generating unit72into multiple cycles to transmit to the bus. For example, the address transmitting unit74, after transmitting a command, transmits address information designating the area to access by that command.

When transmitting address information including a memory address and a chip address, the address transmitting unit74divides the address information into a first cycle number of cycles to transmit. In contrast, when transmitting address information including a memory address but not a chip address, the address transmitting unit74divides the address information into a second cycle number of cycles to transmit, the second cycle number being smaller than the first cycle number. Thus, when transmitting address information not including a chip address, the address transmitting unit74can transmit the address information with a smaller number of cycles than when transmitting address information including a chip address.

Further, the address transmitting unit74transmits setting information in one of the cycles, where address information is included. The setting information indicates whether address information of the first cycle number or address information of the second cycle number is transmitted. When transmitting address information of the first cycle number (e.g., address information including a chip address), the data processing device20transmits setting information set to a first value (e.g., 1). When transmitting address information of the second cycle number (e.g., address information not including a chip address), the data processing device20transmits setting information set to a second value (e.g., 0).

Then the input/output control unit48included in each of the one or more semiconductor devices32switches the number of cycles in which address information is to be acquired, according to the setting information acquired from the data processing device20. Specifically, when the setting information indicates the first value (e.g., 1), the input/output control unit48acquires address information of the first cycle number. When the setting information indicates the first value (e.g., 1), the input/output control unit48acquires address information including, e.g., a memory address and a chip address.

When the setting information indicates the second value (e.g., 0), the input/output control unit48acquires address information of the second cycle number. When the setting information indicates the second value (e.g., 0), the input/output control unit48acquires address information including, e.g., a memory address but not a chip address.

When the memory device30includes a predetermined number of, two or more, semiconductor devices32, the data processing device20can switch between transmitting address information including a memory address and a chip address of a first bit width and transmitting address information including a memory address and a chip address of a second bit width smaller than the first bit width. For example, when the memory device30includes two semiconductor devices32, the data processing device20can switch between transmitting address information including a memory address and a chip address of three bits and transmitting address information including a memory address and a chip address of one bit.

When transmitting address information including a memory address and a chip address of the first bit width, the address transmitting unit74divides the address information into the first cycle number of cycles to transmit. In contrast, when transmitting address information including a memory address and a chip address of the second bit width, the address transmitting unit74divides the address information into the second cycle number of cycles to transmit, the second cycle number being smaller than the first cycle number. Thus, when transmitting address information including a chip address of a smaller bit width, the address transmitting unit74can transmit the address information with a smaller number of cycles than when transmitting address information including a chip address of a larger bit width.

Further, when transmitting address information of the first cycle number (e.g., address information including a chip address of the first bit width), the data processing device20transmits setting information set to the first value (e.g., 1). When transmitting address information of the second cycle number (e.g., address information including a chip address of the second bit width), the data processing device20transmits setting information set to the second value (e.g., 0).

Then when the setting information indicates the first value (e.g., 1), the input/output control unit48acquires address information including, e.g., a memory address and a chip address of the first bit width. When the setting information indicates the second value (e.g., 0), the input/output control unit48acquires address information including, e.g., a memory address and a chip address of the second bit width.

FIG. 5is a diagram illustrating example address information in the first embodiment. The data processing device20transmits, for example, a column address of 12 bits (CA0to CA11) and a page address of 25 bits (PA0to PA24) as the address information.

In this example, the memory unit42is divided into multiple pages. Each of the multiple pages is divided into multiple columns.

The column address of 12 bits (CA0to CA11) is information designating a column to be accessed in the memory unit42. A page address of low 22 bits (PA0to PA21) out of the 25 bits is information designating a page to be accessed in the memory unit42. Thus, in the present example, the column address of 12 bits (CA0to CA11) and the page address of low 22 bits (PA0to PA21) correspond to the memory address designating an area to be accessed in the memory unit42.

A page address of high three bits (PA22to PA24) out of the 25 bits is information designating one semiconductor device32to be accessed from among the plurality of semiconductor devices32incorporated in the memory device30. Thus, in the present example, the page address of high three bits (PA22to PA24) corresponds to the chip address.

If the memory device30includes one semiconductor device32(a single chip), and if transmitting address information including a chip address, the data processing device20divides the address information into six cycles to transmit.

In this case, specifically, the data processing device20transmits a column address of the first to eighth bits (CA0to CA7) in the first cycle. The data processing device20transmits a column address of the ninth to twelfth bits (CA8to CA11) in the second cycle. The data processing device20transmits a page address of the first to seventh bits (PA0to PA6) in the third cycle. The data processing device20transmits a page address of the eighth to fifteenth bits (PA7to PA14) in the fourth cycle. The data processing device20transmits a page address of the sixteenth to twenty-third bits (PA15to PA22) in the fifth cycle. The data processing device20transmits a page address of the twenty-fourth to twenty-fifth bits (PA23to PA24) in the sixth cycle.

If the memory device30includes one semiconductor device32(a single chip), and if transmitting address information not including a chip address, the data processing device20divides the address information into five cycles to transmit. In this case, specifically, the data processing device20transmits over the first to fourth cycles the same information as if transmitting address information including a chip address. The data processing device20transmits a page address of the sixteenth to twenty-second bits (PA15to PA21) in the fifth cycle.

If the memory device30includes a predetermined number of, two or more (herein two), semiconductor devices32, and if transmitting address information including a chip address of the first bit width (herein a three bit width), the data processing device20divides the address information into six cycles to transmit. In this case, specifically, the data processing device20transmits over the first to sixth cycles the same information as if the memory device30includes one semiconductor device32(a single chip) and if the data processing device20transmits address information including a chip address.

If the memory device30includes a predetermined number of, two or more (herein two), semiconductor devices32, and if transmitting address information including a chip address of the second bit width (herein a one bit width), the data processing device20divides the address information into five cycles to transmit. In this case, specifically, the data processing device20transmits over the first to fourth cycles the same information as if the memory device30includes one semiconductor device32(a single chip) and if the data processing device20transmits address information including a chip address. Then the data processing device20transmits a page address of the sixteenth to twenty-third bits (PA15to PA22) in the fifth cycle.

Further, the data processing device20transmits setting information (MC) as well in a cycle in which address information is transmitted. For example, if the memory device30includes only one semiconductor device32(a single chip), and if transmitting address information including a chip address, the data processing device20transmits setting information MC set equal to the first value (e.g., 1). For example, if the memory device30includes one semiconductor device32(a single chip), and if transmitting address information not including a chip address, the data processing device20transmits setting information MC set equal to the second value (e.g., 0).

For example, if the memory device30includes a predetermined number of (herein two) semiconductor devices32, and if transmitting address information including a chip address of the first bit width (herein a three bit width), the data processing device20transmits setting information MC set equal to the first value (e.g., 1). For example, if the memory device30includes a predetermined number of (herein two) semiconductor devices32, and if transmitting address information including a chip address of the second bit width (herein a one bit width), the data processing device20transmits setting information MC set equal to the second value (e.g., 0).

Note that the data processing device20transmits setting information in a cycle prior to the cycle in which a chip address is transmitted. In this example, the data processing device20transmits setting information (MC) in the third cycle. Thus, before acquiring a chip address (PA22to PA24), the semiconductor device32can determine whether the chip address (PA22to PA24) needs to be dealt with.

The data processing device20transmits at least part of the chip address in the last cycle of multiple cycles and does not transmit information other than the chip address in the last cycle. Thus, the data processing device20can make the arrangement (format) of information transmitted in cycles other than the last cycle be the same between when transmitting address information not including a chip address and when transmitting address information including a chip address. The semiconductor device32can perform the same process on the data piece of the same arrangement (format) between when receiving address information not including a chip address and when receiving address information including a chip address.

FIG. 6is a flow chart illustrating the determination process of whether the input/output control unit48is to deal with the sixth cycle. When receiving address information from the data processing device20, the input/output control unit48in the memory device30performs the process shown inFIG. 6before dealing with the sixth cycle.

First, the input/output control unit48acquires setting information (MC) at S11. Then at S12the input/output control unit48determines whether the setting information is the first value (MC=1). If the setting information is the first value (MC=1) (Yes at S12), the input/output control unit48performs the acquisition process for data in the sixth cycle at S13. Then after performing the acquisition process for data in the sixth cycle, the input/output control unit48ends the acquisition process for address information.

In contrast, if the setting information is not the first value (MC≠1) (No at S12), the input/output control unit48skips the acquisition process for data in the sixth cycle at S14and ends the acquisition process for address information. After performing the acquisition process for data in the first to fifth cycles, the input/output control unit48ends the acquisition process.

By performing the above process, the input/output control unit48can switch the number of cycles in which address information is to be acquired, according to the setting information acquired from the data processing device20. Specifically, if the setting information indicates the first value (MC=1), the input/output control unit48can acquire address information of the first cycle number (six cycles, the first to sixth cycles). For example, if the memory device30includes one semiconductor device32(a single chip), and the setting information indicates the first value (MC=1), the input/output control unit48can acquire address information including a memory address and a chip address. For example, if the memory device30includes a predetermined number of, two or more (e.g., two), semiconductor devices32, and the setting information indicates the first value (MC=1), the input/output control unit48can acquire address information including a memory address and a chip address of the first bit width (e.g., three bits).

If the setting information indicates the second value (MC=0), the input/output control unit48can acquire address information of the second cycle number (five cycles, the first to fifth cycles). For example, if the memory device30includes one semiconductor device32(a single chip), and the setting information indicates the second value (MC=0), the input/output control unit48can acquire address information including a memory address but not a chip address. For example, if the memory device30includes a predetermined number of, two or more (e.g., two), semiconductor devices32, and the setting information indicates the second value (MC=0), the input/output control unit48can acquire address information including a memory address and a chip address of the second bit width (e.g., one bit).

FIG. 7is a diagram illustrating example Fuse information settings. The memory device30stores Fuse information. The Fuse information indicates the number of incorporated semiconductor devices32(the number of chips).

For example, the Fuse information is written into each semiconductor device32at the time of factory shipment. The Fuse information is, for example, two bits of information. In this example, the Fuse information indicates whether the number of them (the number of chips) incorporated in the memory device30is one (one chip), two (two chips), four (four chips), or eight (eight chips).

FIG. 8is a diagram illustrating example identification values assigned to semiconductor devices32. A unique identification value is assigned to each of the one or more semiconductor devices32incorporated in the memory device30. As identification values, 0, 1, 2, 3, 4, 5, 6, and 7 are assigned to eight semiconductor devices32incorporated in the memory device30.

By connecting a predetermined setting-value input terminal to a power supply line or a ground line, an assigned identification value is given to the semiconductor device32. For example, by connecting CADD0, CADD1, and CADD2terminals to a power supply line or a ground line, an identification value is given to the semiconductor device32.

When receiving address information, the input/output control unit48included in each of the plurality of semiconductor devices32acquires the chip address included in the address information. If the memory device30comprises a plurality of semiconductor devices32, the input/output control unit48compares the chip address included in the address information with the assigned identification value. Then if the memory device30comprises a plurality of semiconductor devices32, the input/output control unit48accesses the area in the memory unit42designated by the memory address included in the address information on condition that the chip address and the identification value coincide.

If the memory device30comprises one semiconductor device32, the input/output control unit48, without comparing the chip address included in the address information with the identification value, accesses the area in the memory unit42designated by the memory address included in the address information.

FIG. 9is a flow chart illustrating the process for chip selection. When receiving address information from the data processing device20, the input/output control unit48performs the process as shown in, e.g.,FIG. 9.

When receiving address information, first the input/output control unit48refers to the Fuse information at S21. Then the input/output control unit48detects the number of semiconductor devices32incorporated in the memory device30based on the Fuse information.

If one semiconductor device32is incorporated in the memory device30, the input/output control unit48causes the process to proceed to S22. At S22, the input/output control unit48determines that itself has been selected to be accessed and accesses the location in the memory unit42designated by the memory address. Thus, if the memory device30comprises one semiconductor device32, the input/output control unit48, without comparing the chip address included in the address information with the identification value, can access the area in the memory unit42designated by the memory address included in the address information. Then after finishing the processing at S22, the input/output control unit48ends this flow.

If two or more semiconductor devices32are incorporated in the memory device30, the input/output control unit48causes the process to proceed to S23. At S23, the input/output control unit48compares the chip address and the identification value to see whether they coincide.

For example, if two semiconductor devices32are incorporated in the memory device30, at S23the input/output control unit48compares the first bit (e.g., PA22) of the chip address and the first bit (e.g., CADD0) of the identification value. If four semiconductor devices32are incorporated in the memory device30, at S23the input/output control unit48compares the first and second bits (e.g., PA22and PA23) of the chip address and the first and second bits (e.g., CADD0and CADD1) of the identification value. If eight semiconductor devices32are incorporated in the memory device30, at S23the input/output control unit48compares the first to third bits (e.g., PA22to PA24) of the chip address and the first to third bits (e.g., CADD0to CADD2) of the identification value.

If the chip address and the identification value coincide (Yes at S23), at S24the input/output control unit48determines that itself has been selected to be accessed and accesses the location in the memory unit42designated by the memory address. Thus, if the memory device30comprises a plurality of semiconductor devices32, the input/output control unit48can access the area in the memory unit42designated by the memory address included in the address information on condition that the chip address and the identification value coincide. Then after finishing the processing at S24, the input/output control unit48ends this flow.

If the chip address and the identification value do not coincide (No at S23), the input/output control unit48determines that itself has not been selected to be accessed and ends this flow without performing any processing.

As such, the data processing device20according to the first embodiment divides address information including a memory address and a chip address into the first cycle number of (e.g., six) cycles to transmit and divides address information including a memory address but not a chip address into the second cycle number of (e.g., five) cycles to transmit. Further, the data processing device20transmits the setting information indicating whether address information including a chip address or address information not including a chip address is transmitted, as well in a cycle in which address information is transmitted.

Then each of one or more semiconductor devices32incorporated in the memory device30according to the first embodiment switches the number of cycles in which address information is to be acquired, according to the setting information acquired from the data processing device20. Thus, when receiving address information not including a chip address, the memory device30according to the first embodiment does not need to perform the process for acquiring a chip address. Therefore, the memory device30according to the first embodiment can efficiently deal with address information without a wasteful process in acquiring the address information.

Second Embodiment

Next, an information processing device10according to a second embodiment will be described. The information processing device10according to the second embodiment has substantially the same configuration and functions as the information processing device10according to the first embodiment. In the description of the second embodiment, the same reference numerals are used to denote the units having substantially the same functions and configurations as those described in the first embodiment, with detailed description thereof being omitted except for differences.

FIG. 10is a diagram illustrating a memory control unit52and a mode register46in the semiconductor device32. In the second embodiment, the data processing device20causes the mode register46in the semiconductor device32to store the setting information before transmitting address information, instead of transmitting the setting information in a cycle in which address information is transmitted. Specifically, the data processing device20issues a mode-register write command to the memory device30so as to cause it to store the setting information into the mode register46at a predetermined address.

For example, if the memory device30includes one semiconductor device32(a single chip), and if transmitting address information including a memory address and a chip address, the data processing device20causes the mode register46to store the setting information indicating the first value (here, e.g., 1). If the memory device30includes one semiconductor device32(a single chip), and if transmitting address information including a memory address but not a chip address, the data processing device20causes the mode register46to store the setting information indicating the second value (here, e.g., 0).

For example, if the memory device30includes a predetermined number of, two or more (e.g., two), semiconductor devices32, and if transmitting address information including a memory address and a chip address of the first bit width (e.g., a three bit width), the data processing device20causes the mode register46to store the setting information indicating the first value (here, e.g., 1). For example, if the memory device30includes a predetermined number of, two or more (e.g., two), semiconductor devices32, and if transmitting address information including a memory address and a chip address of the second bit width (e.g., a one bit width), the data processing device20causes the mode register46to store the setting information indicating the second value (here, e.g., 0).

When receiving the mode-register write command and the setting information, the memory control unit52included in each of the one or more semiconductor devices32writes the received setting information into the mode register46at a predetermined address. When the setting information indicating the first value (here, e.g., 1) is written, the mode register46outputs a selection signal indicating “1” (EN_6TH_CYCLE=1) to the input/output control unit48. When the setting information indicating the second value (here, e.g., 0) is written, the mode register46outputs the selection signal indicating “0” (EN_6TH_CYCLE=0) to the input/output control unit48.

FIG. 11is a diagram illustrating example address information in the second embodiment. In the second embodiment, the data processing device20transmits address information not including the setting information to the memory device30.

For example, if the memory device30includes one semiconductor device32(a single chip), the data processing device20divides address information including a chip address into six cycles to transmit without the setting information. Specifically, the data processing device20transmits a column address of the first to eighth bits (CA0to CA7) in the first cycle. The data processing device20transmits a column address of the ninth to twelfth bits (CA8to CA11) in the second cycle. The data processing device20transmits a page address of the first to eighth bits (PA0to PA7) in the third cycle. The data processing device20transmits a page address of the ninth to sixteenth bits (PA8to PA15) in the fourth cycle. The data processing device20transmits a page address of the seventeenth to twenty-fourth bits (PA16to PA23) in the fifth cycle. The data processing device20transmits a page address of the twenty-fifth to twenty-sixth bits (PA24to PA25) in the sixth cycle.

If the memory device30includes one semiconductor device32(a single chip), the data processing device20divides address information not including a chip address into five cycles to transmit without the setting information. In this case, specifically, the data processing device20transmits over the first to fourth cycles the same information as if transmitting address information including a chip address. The data processing device20transmits a page address of the seventeenth to twenty-third bits (PA16to PA22) in the fifth cycle.

For example, if the memory device30includes two semiconductor devices32, the data processing device20divides address information including a chip address of the first bit width (e.g., three bits) into six cycles to transmit without the setting information. Specifically, the data processing device20transmits in the same way as if the memory device30includes one semiconductor device32(a single chip) and if the data processing device20transmits address information including a chip address.

For example, if the memory device30includes two semiconductor devices32, the data processing device20divides address information including a chip address of the second bit width (e.g., one bit) into five cycles to transmit without the setting information. Specifically, the data processing device20transmits over the first to fourth cycles the same information as if the memory device30includes one semiconductor device32(a single chip) and if the data processing device20transmits address information including a chip address. Then the data processing device20transmits a page address of the seventeenth to twenty-fourth bits (PA16to PA23) in the fifth cycle.

Then in the second embodiment, if the selection signal (EN_6TH_CYCLE) indicates “1”, the input/output control unit48performs the process of acquiring data in the sixth cycle. That is, if the selection signal (EN_6TH_CYCLE) indicates “1”, after performing the process of acquiring data in the sixth cycle, the input/output control unit48ends the process of acquiring address information.

In contrast, if the selection signal (EN_6TH_CYCLE) indicates “0”, the input/output control unit48does not perform the process of acquiring data in the sixth cycle. That is, if the selection signal (EN_6TH_CYCLE) indicates “0”, after performing the process of acquiring data in the fifth cycle, the input/output control unit48ends the process of acquiring address information.

As such, if the memory device30includes one semiconductor device32(a single chip), the data processing device20according to the second embodiment causes the mode register46of each of one or more semiconductor devices32incorporated in the memory device30to store the setting information indicating whether to transmit address information including a chip address or address information not including a chip address. If the memory device30includes a predetermined number of, two or more (e.g., two), semiconductor devices32, the data processing device20according to the second embodiment causes the mode register46of each of a plurality of semiconductor devices32incorporated in the memory device30to store the setting information indicating whether to transmit address information including a chip address of the first bit width or address information including a chip address of the second bit width.

Then each of one or more semiconductor devices32incorporated in the memory device30according to the second embodiment switches the number of cycles in which address information is to be acquired, according to the setting information stored in the mode register46. Thus, if the memory device30includes one semiconductor device32(a single chip), when receiving address information not including a chip address, the memory device30according to the second embodiment does not need to perform the process for acquiring a chip address. If the memory device30includes a predetermined number of, two or more (e.g., two), semiconductor devices32, when receiving address information including a chip address of the second bit width, the memory device30according to the second embodiment does not need to perform the process for acquiring unnecessary bits. Therefore, the memory device30according to the second embodiment can efficiently deal with address information without a wasteful process in acquiring the address information.