Apparatus and method for counting high-speed early/late pulses from a high speed phase detector using a pulse accumulator

The method and device according to the present invention provides a control system, method and apparatus for synchronizing a reference signal to high frequency data signals. Pulses are accumulated before reaching the integrator. Pulse accumulation is provided in a DLL clock and data recovery circuit. Pulses are accumulated using a ripple divider for rising transitions only. In another exemplary embodiment, pulses are accumulated using a ripple divider for both rising and falling transitions.

TECHNICAL FIELD

The present invention generally relates to delay locked loop (“DLL”) and phase locked loop (“PLL”) devices. More particularly, the present invention relates to a digital clock and data recovery method and device for counting pulses from a high speed phase detector using a pulse accumulator in a DLL or a PLL.

BACKGROUND OF THE INVENTION

A PLL is an electronic circuit that controls an oscillator so that the oscillator maintains a constant phase angle relative to a reference signal. Clock recovery circuits typically use a phase-locked loop circuit to track and reduce the phase offset between clock and data signals. The basic architecture of a simple PLL circuit is illustrated in FIG.1. PLL circuits are used in applications such as generating a clean periodic signal from a noisy signal, frequency multiplication, and clock and data recovery.

A typical voltage-controlled oscillator or (“VCO”)100may be used to generate an output102which is a periodic signal at a desired frequency. The phase locked loop is designed to allow the VCO output102to be phase locked to an external reference signal104. The external reference signal104may, for example, be a periodic signal such as a sinusoidal or square wave at a fixed frequency (e.g., for frequency synthesizers and multipliers applications), a modulated waveform (e.g., for a demodulator application), or a non-periodic waveform with timing information such as a data waveform (e.g., for clock and data recovery applications). The phase of the VCO output102and the reference signal are compared by phase detector106, which generates an output signal108which indicates whether VCO output signal102is earlier or later than the reference signal. Phase detector output108is filtered by a loop filter, typically an integrator110, which generates a control voltage112that adjusts the VCO output and aligns the VCO output to the reference frequency and phase.

The implementation of integrator110may use a low-pass filter or may, in the alternative, use digital methods to integrate the output of phase detector106. Digital integrators are often desirable because such integrators offer design flexibility compared to analog integrators. However, such digital integrators are often more complex than analog integrators and, at relatively high frequencies, the digital integrators consume more power than analog integrators.

The basic architecture of a delay locked loop is illustrated inFIG. 2. ADLL is typically a digital device similar to a PLL, however, a DLL uses a variable delay or phase shifter element instead of a voltage controlled oscillator. A periodic input signal200is provided to the delay locked loop. The signal is delayed by a variable delay or phase shifter202, generating an output signal204which is a delayed version of the input signal. The DLL output signal204can be delay locked to the reference input206if the periodic input200is relatively close in frequency to the reference input206and if the variable delay202can be varied in such a way as to ensure that the phase of the output204tracks the phase of the reference input206.

The delay locked loop circuit provides the phase tracking mechanism by using a phase detector208that compares the relative phase of the output204and the reference206, and by generating an output210that is proportional to the difference in phase. The phase difference is integrated by an integrator212, generating a control voltage214to adjust the delay in variable delay device202, essentially trying to zero out the difference in phase between output204and reference206. The external reference signal206may be a periodic signal such as a sinusoidal or square wave at a fixed frequency (e.g., for clock synthesizers and multipliers applications), or a non-periodic waveform with timing information such as a data waveform (e.g., for clock and data recovery applications).

FIG. 3illustrates, schematically, a prior art early/late transition based phase detector300used in PLL or DLL based clock and data recovery. Phase detector300may be substituted for phase detector208ofFIG. 2to form a delay locked loop circuit suitable for reducing phase offset between clock and data signals. Phase detector300contains a first flip-flop311, second flip-flop312, third flip-flop313, and fourth flip-flop314. Phase detector300receives a data wave form at input301, and a clock input320from the VCO100or variable delay202. The outputs of phase detector300are late output303, early output305, and data output302. The flip-flops of device300are illustrated as being D flip-flops, with flip-flop312,313, and314being positive edge-triggered and flip-flop311being negative edge-triggered. It is known in the art that the output of a D flip-flop latches the input at the time of the triggering. Phase detector300is configured to provide a late output signal303for every clock cycle in which the reference signal lags behind the data signal, and to provide an early output signal305for every clock cycle in which the reference signal leads the data signal.

Phase detector300is incorporated into a DLL loop filter such as that shown in FIG.4. VCO400provides phase selector402with a multi-phase periodic inputs that are close to but not necessarily equal to the desired clock frequency for the clock signal422. For example, the frequency may be obtained through either digital control of the VCO tuning voltage or by placing the VCO in a PLL with an appropriate reference input. Phase detector401receives an input data signal421, and a clock signal422from phase selector402. Phase detector401compares the clock “feedback” signal422and the data signal421and generates early signal403and late signal405which are provided to integrator412. Integrator412integrates (i.e., counts) the number of early and late pulses. The average early and late information changes relatively slowly, and may be sub-sampled by sub sampler415at, for example, one tenth the clock rate of the integration. The output of sub sampler415is a digital control word which is provided to phase select device402for selection of a phase from VCO400.

That being said, difficulties and drawbacks exist due to the high frequency operation of the integrator. In order to process high frequency input data, digital integrators are configured to count early and late pulses at high frequencies. High frequency integrator operation typically results in high power consumption, heat dissipation problems, and the design of complex, and accordingly expensive, integrators that are able to perform high frequency integration. Thus, due to the need for ever increasing communication bandwidth, there is a need for a more efficient method and apparatus for implementation of digital integrators for high frequency phase locked loop and delay locked loop circuits.

SUMMARY OF THE INVENTION

The method and device according to the present invention addresses many of the shortcomings of the prior art. In accordance with one aspect of the present invention, a control system, method and apparatus are provided for synchronizing a reference signal to high frequency data signals. In accordance with another aspect of the present invention, pulses are accumulated before reaching the integrator. In an exemplary embodiment, pulse accumulation is provided in a DLL clock and data recovery circuit. In a further exemplary embodiment, pulses are accumulated using a ripple divider for rising transitions only. In another exemplary embodiment, pulses are accumulated using a ripple divider for both rising and falling transitions.

The present invention may be described herein in terms of various functional components and various processing steps. It should be appreciated that such functional components may be realized by any number of hardware or structural components configured to perform the specified functions. For example, the present invention may employ various integrated components, such as buffers, voltage and current references, logic devices, memory components and the like, comprised of various electrical devices, e.g. (resistors, transistors, capacitors, diodes or other devices), whose values may be suitably configured for various intended purposes. In addition, the present invention may be practiced in any microcontroller-based application, data communication application or similar signal processing applications. Such general applications that may be appreciated by those skilled in the art in light of the present disclosure are not described in detail herein. However for purposes of illustration only, exemplary embodiments of the present invention are described herein in connection with the clock and data recovery operation of a micro-controller device.

Further, it should be noted that while various components may be suitably coupled or connected to other components within exemplary circuits, such connections and couplings can be realized by direct connection between components, or by connection through other components and devices located there between. To understand the various embodiments of the present invention, an exemplary description is provided. However, it should be understood that the following examples are for illustration purposes only and that the present invention is not limited to the embodiments disclosed.

That being said, in accordance with one aspect of the present invention, a control system, method and apparatus are provided for synchronizing a reference signal to high frequency data signals. The reference signal synchronization is accomplished without the high frequency integration problems described above by scaling or dividing the early and late pulse signals. In accordance with another aspect of the present invention, pulses are accumulated before reaching the integrator. The scaling of the early and late pulse signals occurs, for example, in a pulse accumulator configured to scale the early and late pulse signals before they reach the integrator. Thus, in a divide by 16 pulse accumulator, for example, the integrator is configured to integrate at a frequency 16 times lower than the configuration used without the pulse accumulator. In this manner, the power draw is reduced and heat dissipation problems discussed above are diminished.

In an exemplary embodiment, and with reference toFIG. 5, the basic architecture of a delay locked loop incorporating pre-integrator pulse accumulation is illustrated. In accordance with one exemplary embodiment, a pulse accumulator550is provided in communication with a phase detector508and an integrator512. Integrator512communicates with variable delay device502which also receives a data signal500. Output504from variable delay device502is received along with a reference signal506at phase detector508.

During operation of the delay locked loop, a periodic input signal500is provided to the delay locked loop. The signal is delayed by a variable delay or phase shifter502, generating an output signal504which is a delayed version of the input signal. The DLL output signal504can be phase locked to the reference input signal506if the reference input506is relatively close in frequency to periodic input500, for example, within 100 parts per million (PPM) or 0.01% (i.e., the frequency of signal504may differ from the frequency of signal500by less than 100 PPM when signal504is phase locked to signal506).

Furthermore, variable delay device502may both vary the frequency and shift the phase of data input signal500. The frequency is varied by smoothly advancing the phase such that, over a period of time, an entire cycle is swallowed or created. The phase is shifted by selecting a signal with the appropriate phase angle. The phase is shifted such that output signal504tracks the phase of the reference input506. Note that reference input506may be a periodic signal such as a sinusoidal or square wave at a fixed frequency (e.g., for clock synthesizers and multipliers applications), or a non-periodic waveform with timing information such as a data waveform (e.g., for clock and data recovery applications).

The DLL provides the phase tracking mechanism by using a phase detector508. Phase detector508compares the relative phase difference of output signal504and reference signal506and generates a phase detector output signal510in the form of early and late signals representing the leading or lagging phase difference between the reference signal506and output signal504. The early and late signals are accumulated in pulse accumulator550which is configured to provide a pulse accumulator output signal511to integrator512indicating the phase difference between the reference signal506and output signal504. The phase difference is integrated by an integrator512, generating a control voltage514to adjust the delay in variable delay device502, essentially trying to zero out the difference in phase between output504and reference506.

Specifically, pulse accumulator550is configured to generate a signal representing a scaled down count of the accumulated early and late pulses. Pulse accumulator550is further configured such that data is not lost due to sub-sampling, but that the frequency of the early and late signals passed to the integrator is reduced from the frequency of the early and late signals received at the pulse accumulator from the phase detector. Although the pulse accumulator is shown here in conjunction with a DLL device, the pulse accumulator is also suitable for use in other digital applications, including a digital version of a PLL device.

In a further exemplary embodiment, and with reference toFIG. 6, an exemplary loop filter is provided with pulse accumulators651and652. In accordance with one exemplary embodiment, a pulse accumulator651is configured to accumulate early pulses from phase detector601and to provide a terminal count pulse to integrator612when pulse accumulator651receives a particular number of early pulses. Similarly, late pulse accumulator652is configured to accumulate late pulses from phase detector601and to provide a terminal count pulse to integrator612when pulse accumulator651has received a particular number of early pulses. The terminal count may be, for example, after 16 pulses have been received, but other terminal count values may also be used in the present invention.

Integrator612is configured to operate at a lower frequency than the data frequency. For example, a divide by 10 clock divider device611reduces the operating frequency of integrator612by one tenth the high speed clock rate. Furthermore, other integrator612operating frequencies may be selected as appropriate, so long as the integrator operating frequency is at least as high as the frequency of pulse accumulator (e.g.,651, and652) output. In the present example, with a divide by 16 pulse accumulator, the integrator operating frequency clock divider611must not be greater than the operating frequency of a divide by 16 device.

In another exemplary embodiment, and with reference toFIG. 7, a DLL clock and data recovery circuit includes a pulse accumulator750. Note that this embodiment comprises both a phase locked loop780for generating a periodic input to phase selector738of delay locked loop781, and a delay locked loop781that phase locks the periodic input to a data input700.

During normal operation, data input700is provided to phase detector742which provides early and late pulses to pulse accumulator750. Pulse accumulator750provides scaled early and late pulse counts to integrator744permitting the integrator to operate at a reduced frequency without loss of data. Integrator744provides an integrator output signal746to phase selector738. Integrator output signal746is a control “word” causing phase selector738to select an output phase, for use as a clock signal706, from among several output phases generated by VCO710.

The clock signal706is generated using a phase locked loop780to multiply a reference clock708. Reference clock708is close to the target data rate divided by a fixed number. VCO710generates multiple signals that are phase shifted from each other. In an exemplary embodiment, an eight phase VCO generates eight signals that are shifted 45 degrees from each other to create 8 identical signals that are evenly phase shifted from one to the next over 360 degrees. In other embodiments, more or less signals may be generated by VCO710that are shifted more or less than 45 degrees. Furthermore, the phase shifts may be non-uniform in other embodiments.

VCO output726is used to drive a frequency divider728, which generates an output730which is at the VCO frequency divided by a fixed number. The divider output730and the reference input708are compared in a phase detector732. The output of phase detector732is proportional to the difference between the phases and is provided to integrator734. A VCO control signal736is generated by integrator734to drive VCO710. The VCO control signal736tunes outputs712,714,716,718,720,722,724, and726of VCO710such that the reference input708and frequency divider output730are phase locked, and the VCO outputs (e.g.,712,714,716,718,720,722,724, and726) are at a multiple of the reference frequency708.

The phase selector control signal746from integrator744is used in phase selector738to select one of the phases provided by VCO710to generate a clock signal706that is synchronized to the incoming data700. In this manner, phase selector738effectively implements a variable delay or phase shift of the VCO outputs (e.g.,712,714,716,718,720,722,724, and726). The phase selector output706is used to clock a decision circuit702and a phase detector742. Again, the phase detector742drives integrator744, through pulse accumulator750, whose output746is used to drive selection of the phase in phase selector738. In this manner, the output clock signal706of the phase selector738is phase locked to data input700, providing appropriate timing for the decision circuit702and resulting in improved timing for generating the reclocked data output704.

The use of a pulse accumulator enables the use of a simple phase detector. With reference toFIG. 8, phase detector800receives an input data signal801which is provided to the inputs of flip flops811and812. A clock signal802is provided to flip flop811and812. In accordance with an exemplary embodiment of the present invention, flip flop811is a negative edge triggered flip flop. Therefore, the output805of flip flop812, designated Q, holds the value that was on “data in”801when the clock changed from a logic low to a logic high signal. In contrast, the output803of flip flop811, designated Y, holds the value that was on “data in”801when the clock changes from a logic high to a logic low signal. In this exemplary embodiment, early pulses and late pulses from phase detector800are provided to the pulse accumulator on outputs803and805respectively.

In a further exemplary embodiment, pulses are accumulated using a ripple divider for only rising transitions in the data signal. With reference toFIG. 9, an exemplary embodiment of a simplified pulse accumulator comprises an exemplary ripple divider. The exemplary pulse accumulator comprises XOR gates, flip flops, and AND gates configured to form an accumulator for counting by 4's.

An XOR gate902receives an inverted signal from input980, which, in this exemplary embodiment, is the Y output of the phase detector. XOR gate904receives a non-inverted signal from input980. The operation of an XOR gate is well-known in the art, with the output of an XOR gate being logically high if one, and only one, of the inputs is logically high. If the inputs are either both logically low or both logically high, then the output is logically low.

The output of XOR gate902is coupled to flip-flop912and the output of XOR gate904is coupled to flip-flop914. The output of flip-flop912is coupled to the input of XOR gate902and provides the clock signal to flip-flop930. Similarly, the output of flip-flop914is coupled to the input of XOR gate904and provides the clock signal to flip-flop940. The clock signals929and939respectively provide an EARLYX2and LATEX2clock signal to the respective flip-flops. Flip-flops930and940respectively provide an output, EARLYX4931and LATEX4941, which are respectively coupled to their own inverted inputs and to flip-flops936and946. The output of flip-flops936and946are respectively coupled to the inputs of flip-flop938and948. In this exemplary embodiment, all flip-flop logic circuits are positive-edge triggered.

The output of flip-flops936and938, are coupled to the inputs of AND gate960. The output of flip-flops946and948are coupled to the inputs of AND gate962. AND gates960and962provide a logically high output only if both inputs are logically high. However, as illustrated, both AND gates960and962contain one inverting input. The output of AND gates960and962are coupled to synchronous pulse counter (i.e., integrator)970. More particularly, the output of AND gate960is coupled to the up input of pulse counter970and the output of AND gate962is coupled to the down input of pulse counter970. In this exemplary embodiment, output972of pulse counter970is coupled to a voltage controlled oscillator (“VCO”) to control the frequency of the VCO.

In this exemplary embodiment, the integrator is configured to operate at ¼ the serial clock rate. This series of flip-flops serve to perform a frequency division of 4 on the output of XOR gates902and904. Furthermore, this exemplary embodiment only counts early and late pulses on the rising data transitions. In this manner, the high frequency is reduced to a frequency that requires less power to process and results in a faster processing.

The pulse accumulator, in one exemplary embodiment, carries out pulse accumulation when, on each rising transition of the reclocked data Q981, either flip-flop902or904toggles its output. The transition sample Y980indicates which flip-flop should be toggled. If Y is a logic low “0”, the clock was early and the output of flip-flop912, the signal named EarlyX2929, is toggled. If Y is a logic 1, the clock was late, and therefore the output of flip-flop914, the signal named LateX2939, is toggled. The toggling function is accomplished through the use of XOR gates902and904.

Similarly flip-flop930toggles its output EarlyX4931on rising edges of EarlyX2929and flip-flop940toggles its output LateX4941on rising edges of LateX2939. In this manner, Early X4toggles from 0 to 1 and back to 0 when 4 early decisions have been made and LateX4toggles from 0 to 1 and back to 0 when 4 late decisions have been made. The rising transitions of EarlyX4are detected using flip-flops936,938, and AND gate960, and reclocked by a divide by 4 clock signal991which is generated from the recovered clock982and a divide by 4 circuit990. The rising transitions of LateX4are detected using flip-flops946,948, and AND gate962, and reclocked by a divide by 4 clock991. In this manner, for example,936holds the current value,938holds the previous value, and960provides a pulse for one complete scaled down reclocked clock cycle when a pulse is detected (the current and previous values do not agree).

The divide by 4 clock also drives an integrator970, that increments and decrements based on the EarlyX4TC965and LateX4TC967inputs from the outputs of AND gates960and962respectively. Thus integrator970increments its count by 1 every 4 early decisions and decrements by 1 every 4 late decisions. The output of integrator970can drive the phase selector directly, or the LSBs of the integrator can be quantized and driven by the MSBs of the integrator. This change in scale has the effect of changing the gain and bandwidth of the clock and data recovery loop.

In another exemplary embodiment, pulses are accumulated using a ripple divider for both rising and falling transitions. In an exemplary embodiment, and with reference toFIG. 10, the pulse accumulator is changed to count early and late pulses on both rising and falling transitions of Q. In other words, early/late decisions are made on both the 0-1 transitions and the 1-0 transitions in the data signal.

Flip-flop1012and XOR1002serve the same function as flip-flop912and XOR902inFIG. 9, where the flip-flop output EarlyX2A1028toggles on every early decision made on a rising transition of Q, similar to flip-flop912. Flip-flop1013and XOR1003are provided such that flip-flop output EarlyX2B1027toggles on every early decision made on a falling transition of Q. XOR1020then combines both output signals1028and1027such that XOR1020output EarlyX21029toggles on every early decision made on either transition of Q.

A similar modification is made to the late transition pulse accumulator. Flip-flop1014and XOR1004serve the same function as flip-flop914and XOR904inFIG. 9, where the flip-flop output LateX2A1026toggles on every late decision made on a rising transition of Q, similar to flip-flop914. Flip-flop1015and XOR1005are provided such that flip-flop output LateX2B1025toggles on every late decision made on a falling transition of Q. XOR1022then combines both1026and1025such that XOR1022output LateX21039toggles on every late decision made on either transition of Q. The remaining circuits1030,1036,1038,1060,1070,1040,1046,1048,1062, and1090have similar function as similar circuits described with reference to FIG.9. Also, signals1030and1040serve similar functions as describe with reference to similar signals930and940in FIG.9.

FIG. 11is an exemplary timing diagram of a representative waveform for the exemplary circuit in FIG.9.FIG. 12is an exemplary timing diagram of a representative waveform for the exemplary circuit in FIG.10.

Although the above described “simplified” pulse accumulators are described as divide by 4 pulse accumulators, in other exemplary embodiments, the pulse accumulators may be configured as divide by 16 pulse accumulators. In other exemplary embodiments, other divisors may be used to scale down the early/late pulse counts before they are provided to the integrator. The recovered clock signal is also scaled down and is such that the integrator operates at a lower clock frequency that is at least as great as the rate of terminal early and late counts being provided to the integrator.

A divide by 16 pulse counter can be made from a divide by 4 pulse counter by adding flip-flops1032,1034,1042, and1044as described with reference toFIGS. 13 and 14. FIG.'s13and illustrate exemplary pulse accumulators/integrators in accordance with the present invention. Gates1002,1004,1003, and1005are XOR gates. XOR gate1002and XOR gate1005each contain one normal input, one inverting input, and one output. XOR gates1003and1004each contain two normal inputs and one output. The inverting input of both XOR gate1002and XOR gate1005are coupled to input1080, which is coupled to the output Y of a phase detector. One of the inputs of both XOR gate1003and XOR gate1004is also coupled to input1080.

The output of each of XOR gate1002,1004,1003, and1005is coupled to a D flip-flop. More particularly, the output of XOR gate1002is coupled to flip-flop1012; the output of XOR gate1004is coupled to flip-flop1014; the output of XOR gate1006is coupled to flip-flop1016; and the output of XOR gate1008is coupled to flip-flop1018. In this exemplary embodiment, both flip-flop1012and flip-flop1014are positive-edge triggered, while flip-flops1013and1015are both negative-edge triggered.

The outputs of flip-flop1012and flip-flop1013serve as the inputs to XOR gate1020as well as to XOR gates1002and1003respectively. The outputs of flip-flop1014and flip-flop1015serve as the inputs to XOR gate1022as well as to XOR gates1004and1005respectively. The output of XOR gate1020is coupled to flip-flops1030,1032,1034,1036, and1038which serve to perform a frequency division of 16 on the output of XOR gate1020. In a similar manner, the output of XOR gate1022is coupled to flip-flops1040,1042,1044,1046, and1048. In this manner, the high frequency is reduced to a frequency that requires less power to process and results in a faster processing.

Flip-flops1030,1032,1034,1040,1042, and1044are each D flip-flops with an inverting input. Flip-flops1036,1038,1046, and1048are each D flip-flops with inverting input. AND gates1060and1062are known in the art to provide a logically high output only if both inputs are logically high. It should be noted, however, that, as illustrated, both AND gates1060and1062contain one inverting input.

The output of AND gates1060and1062are coupled to synchronous pulse counter1070. More particularly, the output of AND gate1060is coupled to the “up” input of pulse counter1070and the output of AND gate1062is coupled to the “down” input of pulse counter1070. In this exemplary embodiment, output1072of pulse counter1070is coupled to a voltage controlled oscillator (“VCO”) to control the frequency of the VCO.

In this exemplary embodiment, and similar to the embodiment discussed with reference toFIG. 9, early decisions are detected as a logic low level on the input Y1080during transitions on input Q1081. Late decisions are detected as a logic high level on the input Y1080during transitions on input Q1081. The output of flip-flop1030toggles from 0 to 1 and back to 0 after 4 early decisions have been made and the output of flip-flop1040toggles from 0 to 1 and back to 0 after 4 late decisions have been made. Flip-flops1032and1034are set us as a ripple divider such that the output of flip-flop1034toggles every 4 transitions of flip-flop1030. Similarly, flip-flop1044toggles every 4 transitions of flip-flop1040. In this manner, the output of flip-flop1034toggles from 0 to 1 and back to 0 after 16 early decisions have been made and the output of flip-flop1044toggles from 0 to 1 and back to 0 when 16 late decisions have been made.

Similarly, in one exemplary embodiment, the rising transitions on the output of flip-flop1034are detected and synchronized to the clock by flip-flops1036and1038and AND gate1060, and the rising transitions on the output of flip-flop1044are detected and synchronized to the clock by flip-flops1046and1048and AND gate1062. In this manner, the frequency of early and late data signals provided to the integrator is reduced and the high frequency operation of integrator1070is reduced to a lower frequency that requires less power to process and results in a faster processing.

In another exemplary embodiment, with reference toFIG. 14, pulses are accumulated using a divide by 16 ripple divider for both rising and falling transitions. Similarly to the embodiment discussed with reference toFIG. 10, early decisions are detected as a logic low level on the input Y1080during rising transitions on input Q1081or a logic high level on the input Y1080during falling transitions on input Q1081, and late decisions are detected as a logic high level on the input Y1080during rising transitions on input Q1081or as a logic low level on the input Y1080during falling transitions on input Q1081.

Similar to the embodiment discussed with reference toFIG. 12, flip-flops1030,1032and1034, and flip-flops1040,1042, and1044are set us as a ripple dividers such that the output of flip-flop1034toggles from 0 to 1 and back to 0 after 16 early decisions are made and the output of flip-flop1044toggles from 0 to 1 and back to 0 after 16 late decisions are made.

Therefore, in accordance with various aspects of the present invention, a lower frequency integrator can be used without reducing the data transfer rate. Stated another way, the use of pulse accumulators with high frequency integrators enables obtaining even higher data transfer rates. Therefore the present invention may be used, for example, to provide faster download or exchange of data over the internet, in wireless communication, and in other data communication applications. Other exemplary applications include the tuning of a radio station and a clock multiplier. Although the pulse accumulator has been described in one exemplary embodiment as a ripple divider, other methods of lowering the clock rate of the early and late counts are also contemplated within the scope of the present invention. For example, a synchronous divider may be used instead of a ripple divider. Other suitable dividers or logic device arrangements may also be employed in the systems of the present invention.

Although the present invention is set forth herein in the context of the appended drawing figures, it should be appreciated that the invention is not so limited to the specific form shown. Various modifications, variations, and enhancements in the design and the arrangement of the method and apparatus set forth herein may be made without departing from the spirit and scope of the present invention. For example, the D flip-flops may be replaced with other forms of flip-flops or other circuitry that performs similar functions. Also, the various components may be implemented in alternate ways, such as varying or alternating the steps in different orders. These alternatives can be suitably selected depending upon the particular application or in consideration of any number of factors associated with the operation of the system. As a further example, the pulse accumulator may be used in other applications where digital integrators are used to count the number of high frequency events that are not necessarily binary in nature. These and other changes or modifications are intended to be included within the scope of the present invention.