An optoelectronic (OE) package or system and method for fabrication is disclosed which includes a silicon layer with a wiring layer. The silicon layer has an optical via for allowing light to pass therethrough. An optical coupling layer is bonded to the silicon layer, and the optical coupling layer includes a plurality of microlenses for focusing and or collimating the light through the optical via. One or more first OE elements are coupled to the silicon layer and electrically communicating with the wiring. At least one of the first OE elements positioned in optical alignment with the optical via for receiving the light. A second OE element embedded within the wiring layer. A carrier may be interposed between electrical interconnect elements and positioned between the wiring layer and a circuit board.

CROSS REFERENCE TO RELATED APPLICATION

This application is related to the following commonly-owned, co-pending United States Patent Application filed on even date herewith, the entire contents and disclosure of which is expressly incorporated by reference herein in its entirety: U.S. patent application Ser. No. (24249), for “SILICON CARRIER OPTOELECTRONIC PACKAGING”.

BACKGROUND

The present invention relates generally to the field of integrated circuits and silicon chip technology, and more particularly, relates to a packaging system or packaging assembly and method thereof for optoelectronic devices in integrated circuits and silicon chip technology.

Computer system performance is increasingly important in current computer systems and data centers, including for example, personal computers, servers and server farms. Computer performance is measured by, for example, system availability, speed of computation, processor speed, among other measurable aspects. The communication bandwidth between computers and within a computer is important in a computer system's overall performance. The current trend towards multi-core processors and multiple processors per machine requires an increase in communication between processors, and between a processor and its memory. Current use of electrical data links perform best over short distances, but they reach a performance limit as the link distance and frequency increases. Optical data links over fiber are capable of high speed communication with low loss over large distances, however, current optical transceivers are bulky and expensive compared with their electrical counterparts.

Therefore, there is a need for a system or assembly/package and a method for reducing the size of optical transceivers used in computers, integrated circuits and chips. It would also be desirable for a system or assembly/package and method to lower the cost of using optical transceivers in computers, integrated circuits and chips.

BRIEF SUMMARY

In an aspect of the invention, an optoelectronic (OE) assembly for a semiconductor or computer chip includes a silicon layer including a wiring layer. The silicon layer defines at least one optical via for allowing light to pass therethrough. An optical coupling layer is bonded to the silicon layer, and the optical coupling layer includes a plurality of microlenses for focusing and or collimating the light through the optical via. At least one first OE element is coupled to the silicon layer and electrically communicating with the wiring layer. The first OE element is positioned in optical alignment with the optical via for receiving the light, and a second OE element embedded within the wiring layer. In a related aspect, the first OE element is attached beneath the silicon layer and electrically communicating with the wiring, and the first OE element is positioned in optical alignment with the optical via for receiving the light. In another related aspect, the assembly further comprises VCSELs (vertical cavity surface emitting lasers) and/or photodiodes as the first OE element. The assembly may further include a plurality of interconnect elements electrically communicating with the wiring layer for attaching the assembly to an additional element providing an additional level of packaging. In a related aspect, the first OE element includes a vertical cavity surface emitting lasers (VCSEL) and/or a photodiode (PD) array. The VCSEL and/or PD array may includes circuitry connected to the wiring layer, the VCSEL and/or PD array being positioned between the wiring layer and a carrier. The assembly may further include a heat spreader between the first OE element and the carrier. In a related aspect, the second OE element includes a laser diode driver (LDD) and/or a trans-impedance amplifier (TIA) including a chip having LDD/TIA circuitry. The LDD/TIA circuitry may include a circuitry pitch that is a multiple of an OE pad pitch. The assembly may further include a carrier positioned between the wiring layer of the silicon layer and a circuit board. The carrier may be electrically connecting first interconnect elements connected to the wiring layer of the silicon layer and second interconnect elements connected to the circuit board. Additionally, the assembly may include a carrier for interposing between a plurality of electrical interconnect elements including C4s and compressions bond pads. The carrier may include one or more recessed portions for housing at least one of the first OE elements. The carrier may be positioned between the wiring layer of the silicon layer and a circuit board and electrically connecting first interconnect elements connected to the wiring layer and second interconnect elements connected to the circuit board. The assembly may further include a spacer electrically connecting one or more first OE elements to a PCB. A thermal heat spreader may be positioned above one or more first OE elements and in thermal contact with the first OE elements. The assembly may also include a carrier interposer positioned over the OE elements and in thermal contact with the OE elements providing a thermal sink, and the carrier including an alignment feature for positioning the carrier in mating relation with the optical coupling layer. In a related aspect, at least one semiconductor element may be attached to the wiring layer of the silicon layer. In another related aspect, the semiconductor element is selected from a group comprising: a processor, and an application specific integrated circuit (ASIC) chip. The assembly may further include at least one additional silicon layer including active devices connected to the wiring layer of the silicon layer and connected to a carrier, and the carrier electrically connected to the wiring layer and a circuit board using through vias. In a related aspect, the assembly includes a plurality of silicon spacer layers forming a frame around a bottom of the silicon layer defining a central region on the bottom of the silicon layer. In a related aspect, the silicon spacer layers thermally communicate with at least one of the first and/or second OE devices as a thermal sink.

In another aspect of the invention, an optoelectronic (OE) package or system for semiconductor fabrication includes a silicon layer with a wiring layer. The silicon layer defines at least one optical via for allowing light to pass therethrough. An optical coupling layer is bonded to the silicon layer, and the optical coupling layer including a plurality of microlenses for focusing and or collimating the light through the optical via. At least one first OE element coupled to the silicon layer and electrically communicating with the wiring layer. The first OE element positioned in optical alignment with the optical via for receiving the light. A second OE element is embedded within the wiring layer. A carrier interposes between electrical interconnect elements. The carrier is positioned between the wiring layer of the silicon layer and a circuit board and the carrier electrically connecting first interconnect elements connected to the wiring layer and second interconnect elements connected to the circuit board. In a related aspect, at least one of the second OE elements is a laser diode driver and transimpedance amplifier (LDD/TIA) element, the LDD/TIA element includes a chip having circuitry. In another related aspect, the package further includes a thermal sink interposer positioned over the first OE element and in thermal contact with the first OE element, and the carrier including an alignment feature for positioning the carrier in mating relation with the optical coupling layer. The package may also include at least one additional silicon layer including active devices connected to the wiring layer of the silicon layer and the carrier.

In an aspect of the invention, a method for assembling or packaging a semiconductor or chip includes: fabricating a silicon layer with a wiring layer, the silicon layer defining at least one optical via for allowing light to pass therethrough; bonding an optical coupling layer to the silicon layer, the optical coupling layer including a plurality of microlenses for focusing and or collimating the light through the optical via; coupling at least one first OE element to the silicon layer and the first OE element electrically communicating with the wiring layer; positioning the first OE element in optical alignment with the optical via for receiving the light; a second OE element embedded within the wiring layer; and interposing a carrier between electrical interconnect elements and positioning the carrier between the wiring layer of the silicon layer and a circuit board, and electrically connecting first interconnect elements to the wiring of the silicon layer and second interconnect elements to the circuit board.

In a related aspect, the method includes positioning a thermal sink interposer over the first OE element and in thermal contact with the first OE element. In another relate aspect, the method includes connecting at least one additional silicon layer including active devices connected to the wiring layer of the silicon layer and the carrier.

DETAILED DESCRIPTION

Referring toFIG. 1, an integrated OE assembly10includes a silicon wafer14(or thinned silicon) having circuitry/wiring layers18. The circuitry/wiring layers18drive an OE element embodied as a laser diode array (e.g., vertical cavity surface emitting lasers (VCSEL)) and/or amplifies the signals from a photodiode (PD) array, collectively referred to as a VCSEL/PD or OE array22. The OE arrays22communicate with laser diode drivers (LDD) and transimpedance amplifiers (TIAs) collectively referred to as LDD/TIA circuitry50, shown inFIG. 2b. In the embodiment of the invention show inFIG. 1, LDD drivers and/or TIAs are integrated in the wiring circuitry, using LDD/TIA circuitry54, shown inFIG. 2b.

It is understood that an OE element may be comprised of either active or passive components, and may serve an optical function (send, receive, direct or pass light) and an electrical function (process, amplify signals, wiring, or electrical pads, or contacts).

In one embodiment of the invention, the silicon wafer14may be fabricated using standard CMOS (complementary metal oxide semiconductor) processes. During fabrication of the OE assembly10, after the circuitry/wiring layers18are complete, an optical through hole30via is fabricated there through. The OE element through hole30enables light to pass from the OE array (VCSEL/PD)22to a microlens array34positioned over the silicon wafer14. The through hole30, in one embodiment of the invention, may be about 10 to 200 microns in diameter and may be realized using an etch process such as a Bosch™® etch, or other etch process. The through hole may be larger, and in an alternative embodiment, a slot hole may be used to accommodate many optical ports.

The microlens array34collimate or focuses the light to and from the OE array22. The silicon wafer14is bumped by attaching C4 balls46, or other interconnect elements, for example, pins, or columns. The VSCEL array (laser diode array) and/or a photodiode array22is bonded to, and positioned below the silicon wafer14.

During fabrication, in another embodiment of the invention, a silicon wafer is attached to a temporary handling wafer (not shown), and is ground and polished to a thickness of about between 5 to 50 microns. After polishing, the silicon wafer may be further thinned by chemical etching (using TMAH, KOH, or other means) to just leave silicon wiring and silicon circuitry on the glass handler. By removing the bulk silicon and leaving just the silicon wiring the assembly's high speed electrical performance is improved. Also, by leaving just the silicon wiring and circuitry on the glass handler there is no need to fabricate an optical via or optical window since the bulk silicon is removed.

The silicon wafer14is then transferred and attached to a glass wafer which contains microlenses34as shown inFIG. 1. The glass microlens array wafer may have a thickness of about 200 to 800 microns. The temporary handling wafer is then removed exposing the silicon circuitry18and pads42. The silicon wafer14is then bumped by attaching C4 balls46, or other interconnect elements, for example, pins, or columns. The next step in the fabrication of the OE assembly10, is to attach the OE array22. The VSCEL array (laser diode array) and/or a photodiode array22is bonded to the silicon wafer14using standard flip chip bonding tools (such as SUSS® Microtech flip chip bonder Model 150 or Model 250). The OE array22to silicon wafer14join may consist of, for example, C4s or micro C4s, compression bonds, or other interconnects. Thereby, the resulting OE assembly10, as shown inFIG. 1, is fabricated. Other embodiments of the fabrication of the OE assembly10may include the glass wafer having microlenses of spherical or aspherical shapes. The microlenses can be refractive or diffractive, or a combination of both. Alternatively, instead of glass other optically transparent materials could be used such as InP (indium phosphorus) or GaAs (gallium arsenide) or suitable optical plastic. In one embodiment of the invention, the silicon wafer may be fabricated using standard CMOS processes. Alternatively other device substrates could be used such as substrates made of, for example, SiGe, GaAs, SOI (silicon on insulator). The bonding of the glass lens wafer to the silicon wafer is performed using standard wafer to wafer bonding tools, for example, with an alignment accuracy of about +/−1 micron.

Referring toFIG. 2a, the lens array34of the OE assembly10is shown in a 1×12 array of microlenses. It is understood that other lens arrangements are possible, such as a 1×4 array or a two dimensional array of lenses. Referring toFIG. 2b, the OE assembly10is shown with the OE array22removed. The interconnect pads42(which may be bumped with C4 solder balls) connect the OE assembly10and a next level of packaging. High density wiring18connects the pads42to the laser diode drivers (LDD) and/or trans-impedance amplifiers (TIA) (LDD/TIA) circuitry54. The LDD/TIA circuitry54is connected to the pads42to which the OE devices22are mounted. The through hole optical via30allows light32to pass between the microlenses34and the OE array22. When using high frequency electrical signals, controlling the electrical impedance, controlling near neighbor electrical signal crosstalk, and balance the timing skew between different channels between the input (interconnect) pads of the LDD/TIA circuitry54and the output (OE) pads42is considered to manage signal integrity. One way to manage and maintain signal integrity is by minimizing the electrical signal lines length difference between the channels in the layout of the LDD/TIA circuitry54layout. Another optimization of the circuitry54layout includes minimizing the area of the LDD/TIA circuitry54layout which may include placing the individual LDD/TIA channel circuitry54on the same pitch as the OE pads42or OE diodes. In another embodiment of the invention, the OE assembly10has LDD/TIA circuitry including a circuitry pitch that is a multiple of an OE pad pitch.

Referring toFIG. 2c, the VCSEL array22contains a source region58. The pads42interconnect the source region58to silicon drive circuitry. The arrangement of pads is similar for photodiode (PD) arrays. It is understood that the OE array22may be multidimensional, for example a 2×12, 4×12 or a larger array of active elements.

Referring toFIG. 3, two of the OE assemblies10shown inFIG. 1are mounted on a carrier60. The carrier60may be, for example, an organic laminate. The OE arrays22on the OE assemblies10protrude into cavities64in the carrier60. C4 solder balls interconnect the OE assemblies10to the carrier60. The carrier60is attached to a printed circuit board (PCB)72using a ball grid array (BGA) or land grid array (LGA) interconnect76having pads77and solder balls78, resulting in an OE package80. The carrier60serves as an electrical and mechanical interposer between the OE assembly10and the PCB72.

Referring toFIG. 4, another embodiment of an OE assembly90includes two OE arrays22. Similar elements in the OE assembly90to elements in the OE assembly10shown inFIG. 1, have the same reference numerals. It is understood that the number of OE arrays may be extended beyond two arrays. It is also understood that the combination VCSEL and photodiode arrays22may be used on the OE assembly90to function as a transceiver.

Referring toFIG. 5, the OE assembly90shown inFIG. 4is connected to the carrier60with the two OE arrays22in a recess65in the carrier60. The carrier is connected to PCB72using BGA/LGA interconnect76to form an OE package100. The carrier60also provides an electrical and mechanical interposer between the OE assembly90and the PCB72. A heat spreader68is positioned between the bottom of the recess65and the OE arrays22. The heat spreader68may be used to transfer heat from the OE arrays22and CMOS devices such as the integrated LDD drivers/TIA50,54, to the side of the package100for removal, for example, by an air cooled heat sink, a water cooled heat sink, or by other standard heat removal devices.

Referring toFIG. 6, an OE assembly110includes a multidimensional OE array (VCSEL/PD array)114. In the OE assembly110, like features with respect to the OE assembly90shown inFIG. 4have the same reference numerals. The multidimensional array114enables dense packing of OE devices, such as VCSELs and PDs, on a single OE chip, such as the thinned silicon wafer14of the OE assembly110.

Referring toFIG. 7, another embodiment of an OE arrangement120includes a silicon wafer124which is thicker than in the previous embodiments. However, like features with respect to the OE assembly10shown inFIG. 1have the same reference numerals. The silicon wafer124may be, for example, about 100 to 800 microns thick. An optical coupling glass wafer/lens array128is reversed with respect to the previous embodiment of the invention, such that the microlens array128faces the OE array22. The present embodiment is advantageous because less grinding and polishing of the silicon wafer124is required.

Referring toFIG. 8, an OE assembly130includes an additional device attached to the silicon wafer14, and like features with respect to the OE assembly10shown inFIG. 1have the same reference numerals. The additional device may be a processor or ASIC (application specific integrated circuit) device as shown inFIG. 8. In one embodiment, the additional device138is positioned as close as possible to the VCSE1/PD22to minimize the electrical power and cost by incorporating some or all of the LDD circuitry154within the additional device. In another embodiment, it may be desirable to use standard (non-custom) additional device(s) where the needed LDD/TIA circuitry154requirements are in the thinned silicon14.

Referring toFIG. 9a, an OE assembly140includes a through via148silicon spacer144. In the OE assembly140, like features with respect to the OE assembly90shown inFIG. 4have the same reference numerals. The silicon spacer144may also incorporate passive and/or active electrical components152, as well as provide the electrical pad42interposing between the OE assembly140and the PCB72as shown inFIG. 10resulting in an OE package160. The OE assembly140also includes underfill153as shown inFIG. 9a. Referring toFIG. 10, a heat spreader164is used to transfer heat away from the LDD chip/TIA50, and OE devices22.

Referring toFIGS. 9band9c, the silicon spacers144may be positioned individually around the periphery of the silicon wafer14with the OE arrays22centrally positioned, as shown inFIG. 9b. Alternatively, the silicon spacer144may be a single part with a center opening156receiving the OE arrays22.

Referring toFIG. 10, the OE assembly shown inFIG. 9may be mounted on a further organic, or ceramic, or other suitable substrate. A heat spreader (made of a high thermal conductive material) may be positioned below the OE assembly to aid the removal of heat from the OE devices and drive circuitry.

Referring toFIG. 11, the OE assembly140is part of an OE package170including an extended silicon spacer174and a top side heat spreader172. The silicon spacer174also serves as a thermal interposer between the thinned silicon14and the heat spreader172. The top side heat spreader172may also incorporate a feature, such as a notch or curvature173, to align an optical connector (not shown). The heat spreader172may be passively aligned to the lens array by referencing the lens edge or referencing a lithographically defined notch on the top of the lens array. Instead of incorporation the VCSEL drive circuitry in the thinned silicon layer as shown, separate CMOS driver chips (not shown) may be mounted adjacent to the OE devices.

Thereby, the OE packages and OE assemblies shown in the embodiments of the invention, integrate the OE transceiver elements in a compact space. Thereby, the present invention provides a system and assembly of integrated packaging, and a method of integrated packaging for reducing the size and lowering the cost of optical transceivers. More specifically, the optoelectronic drivers and receivers are processed and packaged with optical coupling elements, and OE (VCSEL and PD) elements using a wafer scale packaging technology, together with 3D stacking, for integrating the elements in a compact space, resulting in improved density of components and lower cost manufacturing or fabrication.

While the present invention has been particularly shown and described with respect to preferred embodiments thereof, it will be understood by those skilled in the art that changes in forms and details may be made without departing from the spirit and scope of the present application. It is therefore intended that the present invention not be limited to the exact forms and details described and illustrated herein, but falls within the scope of the appended claims.