Depth image sensor with always-depleted photodiodes

Examples are disclosed that relate to the use of an always-depleted photodiode in a ToF depth image sensor. One example provides a method of operating a pixel of a depth image sensor, the method comprising receiving photons in a photocharge generation region of the pixel, the photocharge generation region of the pixel comprising an always-depleted photodiode formed by a doped first region comprising one of p-doping or n-doping and a more lightly-doped second region comprising the other of p-doping or n-doping. The method further comprises, during an integration phase, energizing a clock gate for a pixel tap, thereby directing photocharge generated in the photocharge generation region to an in-pixel storage comprising a capacitor, and in a readout phase, reading charge out from the in-pixel storage.

BACKGROUND

Time-of-flight (ToF) cameras determine depth by measuring the round-trip travel time for light between the camera and an object. In some ToF cameras, a temporally-modulated illumination light signal illuminates a scene, and image sensor pixels capture phase information for the reflected illumination light, from which a distance value is calculated for each pixel.

SUMMARY

Examples are disclosed that relate to the use of an always-depleted photodiode in a ToF depth image sensor. One example provides a method of operating a pixel of a depth image sensor, the method comprising receiving photons in a photocharge generation region of the pixel, the photocharge generation region of the pixel comprising an always-depleted photodiode formed by a doped first region comprising one of p-doping or n-doping and a more lightly-doped second region comprising the other of p-doping or n-doping. The method further comprises, during an integration phase, energizing a clock gate for a pixel tap, thereby directing photocharge generated in the photocharge generation region to an in-pixel storage comprising a capacitor, and in a readout phase, reading charge out from the in-pixel storage.

DETAILED DESCRIPTION

A time-of-flight (ToF) camera determines, for each addressable pixel of an image sensor of the camera, a depth of a subject (a distance from the subject to the pixel) based on a phase of a received light signal that is temporally modulated by a time-of-flight illuminator. The received light signal generates photocharge in a region of the pixel, thereby producing an electric charge signal. A ToF sensor modulates the pixel response in synchronization with the modulated illumination source to direct the charge to different taps of the pixel during an integration period. A global shutter mechanism may be used to simultaneously modulate the entire pixel array. Data is sampled at a plurality of different phases of the temporally modulated light signal, and a depth value for each pixel is determined using the signals acquired for each pixel tap at each illumination phase that is sampled.

Modulating the pixel response comprises modulating a voltage bias of one or more clock gates in the pixel to alternately direct photocharge to in-pixel storage of the respective pixel taps. Photocharge is generated as electron-hole pairs in a semiconductor material. In some depth image sensors, semiconductor material in a photocharge generation region of the pixel can be configured as a high-resistivity material to inhibit photoelectron-hole recombination. In such a pixel, the clock gates are operated at biases sufficient to transport the photocharge to the in-pixel storage within a corresponding modulation period. The use of too low a bias may result in slower transport that can harm modulation contrast due to photocharge migrating to the wrong pixel tap when the pixel tap polarities are switched.

Depth image sensors can be incorporated into wearable devices that are battery powered. As such devices often use batteries as power supplies, lower power operation of a depth image sensor can help to extend time between battery charges. However, power savings may be difficult to achieve for a ToF camera without undesirable trade-offs. For example, as mentioned above, using a relatively higher bias swing to effect faster electron transport in a high resistivity semiconductor material increases modulation contrast and distance accuracy at the expense of power efficiency. Conversely, operating a pixel with smaller bias swings can achieve power cost savings at the expense of a reduction in modulation contrast. Power efficiency may be even more of a concern at smaller pixel sizes (smaller pixel pitch) due to heat dissipation concerns.

One option to reduce power consumption is to employ a lower-resistivity semiconductor in the photocharge generation region. However, using a lower-resistivity material may result in prompt photoelectron-hole recombination, leading to an undesirable loss of signal strength. Increasing the illumination device power output to compensate may negate any such power savings in the pixels. Further, operating at higher voltages creates electron-hole pairs at photodiode or photogate junctions even in the absence of light that may increase dark current, which may impact signal-to-noise ratios.

Another strategy to lower power consumption is to selectively operate a subset of ToF pixels rather than the entire array of pixels on the depth image sensor, and to selectively direct illumination light to a corresponding region in the scene being imaged, rather than broadly across the scene. However, photocharge can accumulate in pixels outside the ROI and diffuse or “bloom” into pixels inside the ROI, thus adding signal noise and lowering modulation contrast.

Accordingly, examples are disclosed related to a depth image sensor pixel comprising an always-depleted photodiode. The always-depleted photodiode comprises a doped first region of one of p-doping or n-doping, and a more lightly-doped second region of the other of p-doping and n-doping located within the first region. The resulting p-n junction between the more heavily-doped first region and the more lightly-doped second region creates an always-depleted region within the more lightly-doped second region due to thermally-induced charge diffusion and drift that occurs under normal operating temperatures (e.g., 0° C. to 80° C.). As a result, a permanent electric field is created that extends substantially or completely through the depth of the pixel. The electric field helps to separate photogenerated electron-hole pairs without the use of a higher resistivity semiconductor material, and thereby allows lower power operation without sacrificing modulation contrast. Further, in some examples, a ToF pixel comprising an always-depleted photodiode may be operated selectively in a lower power mode for power savings, or a higher-power mode that provides for a higher in-pixel storage capacity (or higher “full well capacity”) and higher modulation frequencies.

As mentioned above, a ToF image sensor can be operated to image just a region of interest toward which illumination light is selectively directed. In such examples, blooming of photocharge from pixels outside of the region of interest into pixels within the region of interest can impact modulation contrast. As such, examples are also disclosed that utilize horizontal anti-blooming gates and vertical anti-blooming gates to drain photocharge from pixels outside of the region of interest.

Prior to discussing these examples in detail,FIG.1shows aspects of an example depth image sensor100comprising a ToF camera. The term ‘camera’ refers herein to any imaging component having at least one optical aperture and sensor array configured to image a scene102or subject. Depth image sensor100includes a sensor array104of individually addressable pixels106integrated into a semiconductor die, such as a silicon die. As described in more detail below, pixels106comprise always-depleted photodiodes (ADP). In some implementations, the pixels may be complementary metal-oxide semiconductor (CMOS) elements, but other suitable architectures are also envisaged. Each pixel may be responsive to light over a broad wavelength band, although this is not required. Sensor array104is schematically illustrated with twenty-five individually addressable pixels106for simplicity, although any suitable number of pixels106may be used.

In some implementations, the pixels106of sensor array104may be differential pixels. Each differential pixel may include different collection terminals (“taps”) that are energized according to different clock signals. In one example, to measure modulated illumination light using two taps, two clock signals that are substantially complementary (e.g., the two clock signals have 50% duty cycles that are 180 degrees out of phase) can be used to control the taps. In other examples, the two different clock signals may have a different relationship, such as for measuring ambient illumination or non-modulated active illumination. In other camera implementations that do not include sensor arrays of differential pixels, additional clock cycles may be used to perform a differential measurement. While differential pixels can provide advantages, other types of sensor array, including non-differential sensor arrays, may be used.

Microlens array108optionally may be arranged over sensor array104. Microlens array108includes a plurality of microlens elements110. Each microlens element110of microlens array108may be registered to a pixel106of the sensor array104. When included, microlens array108may provide a larger effective fill factor at each of the pixels, for increased collection efficiency and reduced cross-talk between pixels.

A ToF illuminator112is configured to selectively emit active light to illuminate the scene102. In one example, ToF illuminator112includes an IR laser configured to emit IR light. In some examples, ToF illuminator112optionally may include a diffuser covering a field of illumination of ToF illuminator112. Depth measurements may be taken using IR light, including near infrared (NIR) light, far infrared (FIR) light, or any other suitable wavelength. Although not shown inFIG.1, the depth image sensor optionally may include a bandpass filter to limit the portion of the electromagnetic spectrum reaching the pixels106to the portion of the electromagnetic spectrum emitted by ToF illuminator112.

In other examples, ToF illuminator112may be configured to emit active illumination light in a visible spectral band. In some examples, ToF illuminator112may include a broad-band illumination source, such as a white light source. Further, in some examples, ToF illuminator112may include a plurality of spectral illuminators (e.g. LEDs). In some such examples, the plurality of spectral illuminators may be configured to emit active illumination in the same spectral band, although this is not required.

In some examples, ToF illuminator112comprises a steerable illumination source configured to selectively emit active illumination light having a narrow field that is sized to illuminate one or more illumination zones in the scene102. Further, the steerable illumination source comprises a steering element113configured to steer the active illumination light122emitted from steerable illumination source to individually actively illuminate different illumination zones (e.g., zone124a) of a plurality of target illumination zones124in scene102viewed by sensor array104. Such a zoned arrangement produces an illumination light having a smaller angular extent than the field of view of sensor array104, and thereby may provide a greater power density for the same peak power of the illumination relative to full-field imaging. An illumination zone may be configured to be any suitable size that is less than an entire field of view of the scene viewed by sensor array104. Any suitable number of illumination zones may be used to collectively cover the field of view of the sensor array104. Further, any suitable number of pixels of the sensor array may be mapped to each illumination zone.

Steering element113may include any suitable mechanical, electro optical, micro-electro-mechanical-systems (MEMS), electrowetting prism componentry, and/or other steering componentry configured to suitably steer the active illumination emitted from the steerable illumination source to illuminate a designated illumination zone. In some examples, steering element113may comprise a movable mirror, providing for a mechanical steering component to steer the active illumination light to illuminate an illumination zone in scene102. In other examples, steering element113may comprises a refracting lens (e.g., Fresnel, prismatic, etc.) that directs, or steers, light in differing directions based on the input light's lateral position. In further examples, steering element113may comprise a switchable polarization grating, providing for an electro-optical steering component. In yet further examples, steering element113may comprise a liquid crystal lens system (for example a pair of liquid crystal lenses), providing for steering by an electrowetting steering solution (an electrowetting component). In some such examples, the liquid crystal lenses may be arrays of microlenses suspended in a liquid crystal that can be adjusted electrically to steer light.

In some implementations, ToF illuminator112optionally may include one or more optical elements114. For example, the optical element(s)114may include one or more of a collimating element, a diffusing element, and a focusing element. The collimating element may be operative to collimate light emitted from ToF illuminator112into collimated light. The diffusing element may be operative to diffuse light emitted from ToF illuminator112, thereby converting the collimated light into diffused light having a desired profile (e.g., uniform or Gaussian power profile). The focusing element may be operative to focus the diffused light at a designated focal length. Such a designated focal length may be selected based on application or any other suitable factors. In some implementations, any or all of these optical elements may be omitted from ToF illuminator112.

Electronic controller116may include a logic machine118and storage machine120. The storage machine may hold instructions that cause the logic machine to enact any operation, algorithm, computation, or transformation disclosed herein. In some implementations, the logic machine may take the form of an application-specific integrated circuit (ASIC) or system-on-a-chip (SoC), in which some or all of the instructions are hardware- or firmware-encoded. Electronic controller116may be operatively connected to sensor array104, ToF illuminator112, and/or steering element113. In some examples, electronic controller116includes a ToF controller machine and/or an output machine, which may be implemented as separate physical hardware and/or firmware components or incorporated into a single hardware and/or firmware component.

Electronic controller116is configured to repeatedly activate the ToF illuminator112and synchronously address the pixels106of sensor array104to acquire IR images. The active light signal emitted from ToF illuminator112may be temporally modulated in different modulation frequencies for different image captures. In the illustrated example, electronic controller116activates ToF illuminator112to illuminate scene102with modulated IR light122and addresses the pixels of sensor array104in synchronicity. IR light122′ reflects from the scene102back to the camera100. The reflected IR light122′ passes through receiving optics and is incident on the pixels of sensor array104to provide a measurement. For example, the measurement may be an intensity measurement of active IR light back-reflected from the subject to the pixel. In the illustrated example, IR light122′ is measured by a pixel106of sensor array104, thus providing phase information useable with the knowledge of the camera's configuration to determine the world space position of a locus of scene102.

In some examples, electronic controller116controls steering element113to steer active light122towards illumination zone124. As such, reflected light122′ from objects in illumination zone124passes through receiving optics, indicated schematically at130, and is incident on pixels within a region of interest (ROI)126. As discussed below with respect toFIG.9, electronic controller116may selectively operate the pixels within ROI126to determine depth values for the pixels, while pixels outside ROI126are operated to drain photocharge to prevent blooming. In some examples, ROI depth imaging can be performed across a plurality of illumination zones (e.g., by scanning through ROIs) to produce a full array depth image. In other examples, ROI depth imaging can be performed on demand where the ROI is identified via intensity changes in a mono or RGB camera image. Such an image may be acquired via a separate camera or via depth image sensor100operating in a passive mode, as examples.

Electronic controller116is configured to generate a depth image128based on a plurality of captured IR images. The term ‘depth image’ refers to an array of individually addressable image pixels registered to corresponding regions (Xi, Yi) of an imaged scene, with a depth value Ziindicating, for each image pixel, the depth of the corresponding region. ‘Depth’ is defined as a coordinate parallel to the optical axis of the camera, which increases with increasing distance from the camera. The term ‘depth video’ can be used to refer to a time-resolved sequence of depth images. Electronic controller116is configured to output depth image128.

The depth or distance value for a pixel is calculated based on the phase shift of the sensed back-reflected light. The quality of the depth determination may depend on the quantum efficiency (QE) of the image sensor, defined as the number of electrons generated per incident photon, and on the signal contrast between the taps, also known as demodulation contrast. As mentioned above, current ToF pixels may utilize high-resistivity material in the photocharge generation region to impede electron-hole recombination, combined with the use of relatively larger voltage bias swings to achieve sufficient demodulation contrast. However, the relatively larger bias swings may increase power consumption compared to relatively smaller bias swings.

Thus, as mentioned above, an always-depleted photodiode can be used to provide an electric field that separates electron-hole pairs, thereby allowing the use of smaller bias swings in combination with a lower-resistivity semiconductor material.

FIG.2shows an electrical schematic diagram for an example ToF pixel200comprising an always-depleted photodiode (ADP)202. ToF pixel200includes two pixels taps, indicated here as tap201A and tap201B. In other examples, a ToF pixel may include any other suitable number of taps, including a single tap or more than two taps. ToF pixel200further includes a horizontal anti-blooming gate (AB_hor)230and a vertical anti-blooming gate (AB_ver)232.

Each pixel tap includes a clock gate CLK_A204a, CLK_B204bconfigured to direct charge from ADP202to a respective pixel tap during an integration period. During an integration period, clock gates204aand204bare modulated out of phase from each other. Each pixel tap further includes a bias gate BIAS_A206a, BIAS_B206band an in-pixel storage capacitor CAP_A208a, CAP_B208b. Capacitors208a,208bare configured to receive and store charge that is collected via the corresponding clock gate204a,204bduring the integration period, and thus act as in-pixel storage during integration. Bias gates206aand206bare operable to direct charge to capacitors208aand208b, during integration, and to prevent backflow of charge from capacitors208a,208bduring other phases of operation than integration. After integration and during readout, charges stored on capacitors208a,208bare transferred to respective floating diffusion (FD) capacitors210a,210bvia operation of transfer gate212a,212b. Charge on each FD capacitor210a,210bis read as a voltage across a corresponding source follower gate214a,214b, thereby providing an analog voltage signal for that pixel tap. The controller then drains charge via a reset gate216a,216b(RG_A, RG_B). The ToF pixel200further includes a selection gate218a,218b(READ_A, READ_B) operable to select a tap for readout.

In some examples, two or more pixels can share readout circuitry.FIG.3shows an electrical schematic diagram for ToF image sensor in which taps of two pixels300,350share common readout circuitry. More particularly, ToF pixels300,350each comprises an ADP302,352and an “A” pixel tap301A,351A, where each “A” pixel tap comprises a clock gate, a bias gate, in-pixel storage, and a transfer gate. ToF pixels300,350further each comprises a “B” pixel tap301B,351B, each “B” pixel tap having the same components as the “A” pixel taps. The two “A” pixel taps301B,351B share readout circuitry304b, while the two “B” pixel taps301B,351B share readout circuitry304b. As such, photocharge from either tap301B or351B may be read out at collection node306b(BITLINE_A). Likewise, photocharge from either tap301B or tap351B may be read out at collection node306b(BITLINE_B).

FIG.4Ashows a sectional view of an example ToF pixel400comprising an ADP including P-N junction402. Pixel400is an example implementation of pixel200ofFIG.2. Pixel400can be controlled to modulate voltage at pixel taps during an integration period to acquire a depth image. During an integration period, clock gates404a,404bare alternately energized to direct charge to corresponding in-pixel storage capacitors via bias gates.

Pixel400comprises a doped first region410of a semiconductor die, and a more lightly-doped second region412formed within doped first region410. Doped first region410comprises a different doping than more lightly-doped second region412. In some examples, doped first region410may comprise p-doping (e.g., B-doped Si) while more lightly-doped second region412comprises n-doping (e.g., As or P-doped Si). Alternatively, ToF pixel may comprise an n-doped first region with a more-lightly p-doped second region. More lightly-doped second region412may comprise a dopant concentration that is orders of magnitude less than doped first region410. For example, dopant concentration in more lightly-doped second region412may be less than 1016dopant atoms/cm3, or even less than 1014dopant atoms/cm3while dopant concentration in doped first region410may be twice as high or greater (e.g., 10×, 100×, or 1000× greater). In some examples, doping concentration in doped first region410is greater than 1017dopant atoms/cm3.

Light incident on pixel400generates photocharge (electron/hole pairs) in regions410and412. After generation, electron-hole pairs may recombine, or may separate and become integrated photocharge. As mentioned above, ToF pixel400comprises an electric field across P-N junction402of the ADP. The volume and magnitude of the attractive field is a function of the volume of the always-depleted region created by P-N junction402. In some examples, the pixel may be configured such that the P-N junction extends through the thickness of the pixel (e.g., from top to bottom inFIG.4A) to thereby drive photocharge transport from all areas within the photocharge generation region. Referring toFIG.4B, graph442shows an example modeled electrostatic potential of pixel400along line440ofFIG.4A. This model is based upon the pixel400comprising a p-well and lightly n-doped region therein, and would have an opposite polarity for an n-well with a lightly p-doped region therein. The electrostatic potential increases from the bulk (back) side to the transistor (front) side. As such, photoelectrons generated in the ADP migrate towards the clock gates due to this electric field. The drop in electrostatic potential at the transistor side represents divider region416. The vertical electric field along line440is represented by graph444. InFIG.4C, graph444depicts a relatively strong electric field throughout most of the doped first region and the more lightly-doped second region. Again, the more abrupt changes in field strength near the transistor side represent the edges of divider region416.

Returning toFIG.4A, in some examples, pixel400further comprises shallow trench isolation (STI) regions414a,414bdisposed at the transistor side of pixel400, and/or a divider region416disposed within more lightly-doped second region412and between clock gate404aand clock gate404b. As the relative bias is modulated, divider region416may help reduce transfer of uncaptured photocharge from one clock gate to the other. Divider region416comprises a different doping than more lightly-doped second region412.

In some examples, the depth image sensor also includes deep trench isolation (DTI) regions420comprising a dielectric material disposed between pixels. DTI regions420can help to prevent optical cross-talk (due to total internal reflection) and also prevent electrical cross-talk (due to photocharge diffusion) between neighboring pixels. DTI regions420each comprises a trench etched into the pixel array. In some examples, an oxide passivation layer can be deposited on the walls of the etched trench to passivate etch damage. This may help to avoid unwanted diffusion of dopants that can arise when annealing is used to repair etch damage. DTI regions420further comprise a high-κ dielectric material (e.g., a Ta-containing and/or Hf-containing material). In the case of a pixel with a p-well and a more lightly n-doped region forming the always depleted charge collection region, the high-κ dielectric may be chosen to form a fixed negative charge near the etch wall, which attracts holes in the Si semiconductor die, and thus helps to reduce dark current.

FIGS.5A-5Billustrate an example operation of a ToF pixel such as pixel200or pixel400in a relatively lower power “charge-transfer” mode.FIG.5Ashows an example timing diagram500, andFIG.5Bschematically illustrates potentials in the pixel and also charge flow at various stages in the timing diagram500. The potential diagrams inFIG.5Brepresent only one tap channel and includes only one anti-blooming gate for simplicity. Further, the y-axis represents voltage. The description ofFIGS.5A and5Bis in the context of a lightly n-doped region. However, it will be understood that the description can be adapted to a lightly p-doped region in an n-well with appropriate adjustments to signal polarities.

Timing diagram500illustrates a non-integration phase502, an integration phase504, an anti-blooming phase506, and a readout phase508. In the non-integration phase, clock gate A and clock gate B are not modulated, but instead are held at a relatively lower voltage, thereby posing a potential barrier to photoelectrons and preventing the photoelectrons from reaching either pixel tap. Further, anti-blooming gates (AB) are held high to drain photoelectrons that are produced by the ADP during the non-integration period, and bias gates (BIAS) and storage capacitors (CAP) are held low. This phase is illustrated at potential diagram510ofFIG.5B, which shows charges being drained to Vddvia the anti-blooming gates and the reset gates.

Integration phase504is illustrated by potential diagram520. In the integration phase, the clock gates are alternately energized to direct photoelectrons to respective storage capacitors (CAP) (e.g. CAP_A and CAP_B ofFIG.2), which are switched high to store photoelectrons. Likewise, the anti-blooming gates are switched to low to avoid draining photoelectrons via the anti-blooming gates. As shown inFIG.5Bat520, modulation of a clock gate (CLK) alternately prevents and allows photoelectron transfer to storage capacitor (CAP) across the bias gate (BIAS). In a two-tap pixel, when one clock gate is high, the other clock gate is low. At the end of integration phase504, the integrated charge from all modulation cycles is held at storage capacitor (CAP) for a respective pixel tap. Any suitable number of cycles may be used during the integration phase. As discussed above, the relative CLK bias changes during integration phase504may be relatively small due to the built-in electric field created by the P-N junction than in pixels in which a higher resistivity semiconductor material is used without an ADP. The relatively smaller bias change may lead to lower power consumption.

During anti-blooming phase506, represented by potential diagram530ofFIG.5B, the anti-blooming gates are energized to drain photoelectrons from the ADP. Additionally, the bias of the transfer gate (TX) is decreased to provide voltage headroom on the FD capacitor. However, the bias gate potential remains slightly higher than the transfer gate potential. Furthermore, the clock gates and bias gates are turned off during the anti-blooming phase, decreasing their potentials to prevent collecting photoelectrons from the ADP during this phase.

During readout phase508, represented by potential diagram540, the bias of the reset gate is decreased, and the integrated photocharge is transferred by lowering the bias applied to the storage capacitors, thereby transferring charge to the FD capacitor. Anti-blooming gates may be energized to drain photoelectrons from the ADP during this phase.

FIGS.6A-6Billustrate an example operation of a ToF pixel, such as pixel200or pixel400, in a relatively higher power “charge pump” mode. As opposed to the “charge transfer” mode ofFIGS.5A-5B, the charge pump mode ofFIGS.6A and6Bmay provide for faster modulation frequencies and higher modulation contrast, but also may consume more power. The potential diagrams inFIG.6Brepresent only one tap channel and includes only one anti-blooming gate for simplicity.

Timing diagram600illustrates a non-integration phase602, an integration phase604, an anti-blooming phase606, and a readout phase608. Non-integration phase604is illustrated by potential diagram610. In the non-integration phase, clock gate A and clock gate B are not modulated, but instead are held at a relatively lower voltage, thereby posing a potential barrier to photoelectrons and preventing the photoelectrons from reaching either pixel tap. As before, anti-blooming gates (AB) are held high to drain photoelectrons that are produced by the ADP during the non-integration period, while bias gates (BIAS) and storage capacitors (CAP) are held low. Charges are drained to Vddvia AB and reset gates (RESET).

Integration phase604is illustrated by potential diagram620. In the integration phase, the clock gates are alternatively energized to direct photoelectrons to respective storage capacitors (CAP). Capacitors are biased high to store photoelectrons and anti-blooming gates are biased low to avoid draining photoelectrons. As shown inFIG.6Bat620, modulation of a clock gate alternately draws photoelectrons from the ADP to trap the photoelectrons at the clock gate and then “pumps” accumulated photoelectrons across the bias gate into the capacitor. At the end of integration phase604, the integrated charge from all modulation cycles is held at the storage capacitor for a respective pixel tap. When held high, the relatively large potential difference between the CLK and the ADP creates a stronger electric field compared to the integration phase of the “charge-transfer” mode illustrated in potential diagram520. As discussed above, the higher electric field may better attract charge and achieve a greater modulation contrast.

During anti-blooming phase606, represented by potential diagram630ofFIG.6B, the anti-blooming gates are energized to drain photoelectrons from the ADP. The potentials of the clock gates and bias gates are decreased during the anti-blooming phase to prevent collecting electrons from the ADP during this phase.

During readout phase608, represented by potential diagram640, the bias of the reset gate is decreased, and the integrated photoelectrons are transferred by lowering the bias applied to the storage capacitors, thereby transferring charge to the FD capacitor. Anti-blooming gates may be energized to drain photoelectrons from the ADP during this phase.

In some ToF imaging applications, a higher dynamic range may be desired for pixels of a camera. The dynamic range of a ToF pixel is a function of a full-well capacity of the pixel. Thus,FIG.7schematically shows a sectional view of an example ToF pixel comprising potential barriers730a,730bcorresponding to each pixel tap. The potential barriers730a,730ballow for the pixel700to have a higher full-well capacity than pixels200and400. Pixel700is another example implementation of pixel200ofFIG.2.

Similar to pixels200and400, pixel700comprises a doped first region710of one of p-doping and n-doping, and a more lightly-doped second region712of the other of p-doping and n-doping formed within the doped first region, forming P-N junction702therebetween and an always-depleted region within the more lightly-doped second region712. As discussed above, the resulting electric field promotes separation of electron-hole pairs and the transport of photocharge within the pixel. Photocharge collected at clock gates704a,704bis transferred to in-pixel storage via bias gates. In some examples, pixel700further comprises STI regions714a,714bdisposed at the transistor side of pixel700, DTI regions720, and/or divider region716, as discussed above. In other examples, one or more of these features may be omitted.

As seen inFIG.7, the barriers730a,730bare positioned within the more lightly-doped second region adjacent to and spaced from their respective clock gate704a,704b. The barriers may comprise the same doping as doped first region710. Inclusion of barriers730a,730bmay achieve higher dynamic range by enabling creation of potential barriers (i.e., potential barriers812, discussed below with respect toFIG.8B). During an integration phase, charge transfer to storage capacitors (CAP) occurs when the clock gates are deenergized, similar to the “charge pump” mode described above. However, in contrast toFIGS.6A-6B, pixel700enables use of relatively lower clock voltages, as barriers730a,730bcontain charge close to the clock gates. Further, residual charge at the clock gate after charge transfer is prevented from being expelled back to the ADP by the potential at barriers730a,730b. As discussed below, this can provide for a larger full well capacity compared to pixel400, as the storage capacity of capacitors is not limited by the ADP potential.

FIGS.8A-8Billustrate an example operation of ToF pixel700.FIG.8Ashows an example timing diagram800, andFIG.8Bschematically illustrates potentials in the pixel and also charge flow at various phases of timing diagram800. The description ofFIGS.8A and8Bis in the context of a more lightly-doped n region within a more heavily-doped p region, but may be applied a lightly-doped p region within a more heavily-doped n-region by appropriate changes in biases applied the various components according to the timing diagram.

Timing diagram800illustrates a non-integration phase802, an integration phase804, an anti-blooming phase806, and a readout phase808. In the non-integration phase, clock gate A and clock gate B are not modulated, but instead are held at a relatively lower voltage, thereby preventing the photoelectrons from being stored at in-pixel storage. Further, anti-blooming gates (AB) are held high to drain photoelectrons that are produced by the ADP during the non-integration period, and bias gates (BIAS) and storage capacitors (CAP) are held low. This phase is illustrated at potential diagram810ofFIG.8B, which shows charges drained to Vddvia the anti-blooming gates and the reset gates during this phase. Potential barriers812are also held at a relatively low biases via their respective clock gates.

Integration phase804is illustrated by potential diagram820. In the integration phase, the clock gates (CLK) are alternately energized to direct photoelectrons to respective storage capacitors (CAP), which are switched to high to store photoelectrons. Potential barrier812is formed for each tap by energizing barriers (e.g., barriers730a,730bofFIG.7) with their respective clock gates (e.g., clock gates704a,704bofFIG.7), thereby lowering the barrier so that photoelectrons in the ADP are transferred into the respective taps by the clock gates. The anti-blooming gates are switched to low to avoid draining photoelectrons via the anti-blooming gates. As shown inFIG.8Bat820, modulation of a clock gate (CLK) alternately draws photoelectrons from the ADP for accumulation in the clock gate and “pumps” accumulated photoelectrons across the bias gate into the capacitor. When the clock gate is modulated low, the potential barrier812prevents photoelectrons from backflowing to the ADP, and instead directs flow to CAP. At the end of integration phase804, the integrated charge from all modulation cycles is held at the storage capacitor for a respective pixel tap. In contrast toFIGS.5B and6B, the potential of transfer gates (TX_A&B) may be held low in all phases.

In contrast to potential diagram620ofFIG.6B, the potential of the bias gates is held lower than the ADP potential in potential diagram820. In this scheme, photoelectron backflow is prevented via the potential barriers (e.g., barriers730a,730bofFIG.7). Photoelectron flow during clock gate modulation is represented by the arrows in potential diagram820. When the clock gate is high, the potential barrier is lowered by the clock gate to allow photoelectrons to flow from the ADP to accumulate at the clock gate. When the clock gate is low, photoelectrons accumulated at the clock gate transfer to the capacitor via the bias gate, while the potential barrier prevents backflow of photoelectrons to the ADP. As the potential of the bias gate can be held lower than the ADP potential during integration phase804, the storage capacity of the capacitor is increased. This storage capacity increase822is represented by the difference between the dotted lines.

During anti-blooming phase806, represented by potential diagram830ofFIG.8B, the anti-blooming gates are energized to drain photoelectrons from the ADP. Furthermore, the clock gates and bias gates are turned off during the anti-blooming phase, decreasing their potentials to prevent collecting photoelectrons from the ADP during this phase.

During readout phase808, represented by potential diagram840, the bias applied to the reset gate is decreased, and the integrated photocharge is transferred by lowering the bias applied to the storage capacitors, thereby transferring charge to the FD capacitor. Anti-blooming gates may be energized to drain photoelectrons from the ADP during this phase.

As mentioned above, some ToF cameras may be configured to image regions of interest (ROI). In such cameras, illumination light is directed to the region of interest rather than the entire field of view of the camera, and the image sensor senses using a subset of pixels mapped to the region of interest, rather than with all pixels.FIG.9schematically illustrates pixels902mapped to an ROI. For example, pixels902may represent pixels in ROI126in depth image sensor100ofFIG.1. In the example shown, pixel array900comprises sixty-four pixels and ROI pixels902comprises nine pixels for illustrative purposes, but it will be understood that a pixel array and a ROI within the array may each comprise any number of pixels.

Pixels902mapped to the ROI may be controlled as described above, e.g. by any of timing diagram500, timing diagram600, and timing diagram800, as examples. As such, the controller of the depth image sensor obtains a depth value for each pixel of ROI pixels902. However, outside the ROI, horizontal anti-blooming (AB) gates and vertical AB gates are energized to drain photocharge during integration. In this example, horizontal AB gates are connected along a row, while vertical AB gates are connected along a column. Controlling a column, for example, controls AB gates for each pixel in that column. As such, the vertical AB gates in the columns corresponding to the ROI are not controlled to drain photocharge. Likewise, horizontal AB gates in the rows corresponding to the ROI are not controlled to drain photocharge. The use of both column and row AB gates allows the AB gates to be operated for all pixels outside of the ROI.

In some examples, the depth image sensor may be configured to operate full-time in a ROI depth image capture mode. In other examples, the depth image sensor may operate in a ROI capture mode on-demand. In either case, the use of the ROI imaging mode may help to conserve device power, as the pixel tap modulation occurs only within a sub-array of pixels. Further, where the illumination source is configured to illuminate a sub-field of view corresponding to the ROI, a higher-intensity illumination may be used in the sub-field. This may increase the intensity of reflected light122′, thereby contributing to a stronger signal to noise ratio.

FIG.10shows an example method1000of operating a pixel of a depth image sensor, such as pixel200, pixel400, or pixel700. Method1000comprises, at1002, receiving photons in a photocharge generation region of the pixel, the photocharge generation region of the pixel comprising an always-depleted photodiode formed by a doped first region comprising one of p-doping or n-doping and a more lightly-doped second region located within the doped first region, the more lightly-doped second region comprising the other of p-doping or n-doping. Method1000further comprises, at1004, during an integration phase, energizing a clock gate for a pixel tap, thereby directing photocharge generated in the photocharge generation region to an in-pixel storage comprising a capacitor.

In some examples, method1000may comprise, at1006, operating the pixel in a charge transfer mode, wherein energizing the clock gate comprises changing a bias applied to the clock gate from a potential that poses a barrier to the photocharge from moving to the in-pixel storage to a potential that allows the photocharge to move to the in-pixel storage.

Further, in some examples, at1010, the method may comprise operating the pixel in a charge pump mode, wherein energizing the clock gate comprises changing a bias applied to the clock gate between a potential that traps photocharge at the clock gate and a potential that directs photocharge to the in-pixel storage. In some examples, at1012, the method comprises switching from operating the pixel in a charge pump mode to operating the pixel in a charge transfer mode. In some such examples, the pixel comprises a barrier region of the one of p-doping or n-doping that is positioned within the more lightly-doped second region adjacent to and spaced from the clock gate. In such examples, operating the clock gate lowers a potential barrier to photocharge posed by the barrier region, as indicated at1014.

In some examples, as indicated at1016, directing photocharge to the in-pixel storage comprises directing photocharge through a bias gate. As discussed above, the potential of the bias gate may be set to prevent backflow of photocharge from a storage capacitor to the ADP. Further, in some examples, when the pixel is located outside of a region of interest, method1000comprises, at1018, operating one or more of a horizontal anti-blooming gate and a vertical anti-blooming gate to drain photocharge.

In examples that utilize two or more pixel taps per pixel, the clock gate for the pixel tap is a first clock gate for a first pixel tap and the in-pixel storage is a first in-pixel storage comprising a first capacitor. In such examples, method1000further comprises, at1020, during the integration phase, energizing a second clock gate for a second pixel tap alternately with the first clock gate thereby alternately directing photocharge to a second in-pixel storage comprising a second capacitor, and during the readout phase, reading charge out from the second in-pixel storage. Method1000further comprises, at1022, in a readout phase, reading charge out from the in-pixel storage, and at1024, determining a distance value for the pixel.

FIG.11schematically shows a non-limiting embodiment of a computing system1100that can enact one or more of the methods and processes described above. Computing system1100is shown in simplified form. Computing system1100may take the form of one or more personal computers, server computers, tablet computers, home-entertainment computers, network computing devices, gaming devices, mobile computing devices, mobile communication devices (e.g., smart phone), and/or other computing devices.

Computing system1100includes a logic machine1102and a storage machine1104. Computing system1100may optionally include a display subsystem1106, input subsystem1108, communication subsystem1110, and/or other components not shown inFIG.11.

Storage machine1104includes one or more physical devices configured to hold instructions executable by the logic machine to implement the methods and processes described herein. When such methods and processes are implemented, the state of storage machine1104may be transformed—e.g., to hold different data.

Aspects of logic machine1102and storage machine1104may be integrated together into one or more hardware-logic components. Such hardware-logic components may include field-programmable gate arrays (FPGAs), program- and application-specific integrated circuits (PASIC/ASICs), program- and application-specific standard products (PSSP/ASSPs), system-on-a-chip (SOC), and complex programmable logic devices (CPLDs), for example.

When included, display subsystem1106may be used to present a visual representation of data held by storage machine1104. This visual representation may take the form of a graphical user interface (GUI). As the herein described methods and processes change the data held by the storage machine, and thus transform the state of the storage machine, the state of display subsystem1106may likewise be transformed to visually represent changes in the underlying data. Display subsystem1106may include one or more display devices utilizing virtually any type of technology. Such display devices may be combined with logic machine1102and/or storage machine1104in a shared enclosure, or such display devices may be peripheral display devices.

Another example provides a method of operating a pixel of a depth image sensor, the method comprising receiving photons in a photocharge generation region of the pixel, the photocharge generation region of the pixel comprising an always-depleted photodiode formed by a doped first region comprising one of p-doping or n-doping and a more lightly-doped second region located within the doped first region, the more lightly-doped second region comprising the other of p-doping or n-doping; during an integration phase, energizing a clock gate for a pixel tap, thereby directing photocharge generated in the photocharge generation region to an in-pixel storage comprising a capacitor; and in a readout phase, reading charge out from the in-pixel storage. In some such examples, the method may comprise operating the pixel in a charge transfer mode, wherein energizing the clock gate comprises changing a bias applied to the clock gate from a potential that poses a barrier to the photocharge from moving to the in-pixel storage to a potential that allows the photocharge to move to the in-pixel storage. In some such examples, the method comprises operating the pixel in a charge pump mode, wherein energizing the clock gate comprises changing a bias applied to the clock gate between a potential that traps photocharge at the clock gate and a potential that directs photocharge to the in-pixel storage. Additionally or alternatively, the method further comprises switching from operating the pixel in the charge pump mode to operating the pixel in the charge transfer mode. Additionally or alternatively, the pixel further comprises a barrier region of the one of p-doping or n-doping that is positioned within the more lightly-doped second region adjacent to and spaced from the clock gate, and energizing the clock gate lowers a potential barrier to photocharge posed by the barrier region. Additionally or alternatively, directing photocharge to the in-pixel storage comprises directing photocharge across a bias gate. Additionally or alternatively, the clock gate for the pixel tap is a first clock gate for a first pixel tap, the in-pixel storage is a first in-pixel storage comprising a first capacitor, and the method further comprises, during the integration phase, energizing a second clock gate for a second pixel tap alternately with the first clock gate thereby alternately directing photocharge to a second in-pixel storage comprising a second capacitor, and during the readout phase, reading charge out from the second in-pixel storage. Additionally or alternatively, the method further comprises, when the pixel is located outside of a region of interest, operating one or more of a horizontal anti-blooming gate and a vertical anti-blooming gate to drain photocharge. In some such examples, the method may additionally or alternatively comprise, based on the reading charge out, determining a distance value for the pixel.

Another example provides a depth image sensor, comprising a plurality of pixels, each pixel configured to sense light incident on the pixel, and each pixel of the plurality of pixels comprising a doped first region comprising one of p-doping or n-doping, and a more lightly-doped second region disposed within the doped first region, the more lightly-doped second region comprising the other of p-doping or n-doping, thereby forming an always-depleted photodiode (ADP), a first pixel tap comprising a first clock gate disposed adjacent to the more lightly-doped second region of the ADP, and also comprising a first in-pixel storage capacitor, and a second pixel tap comprising a second clock gate disposed adjacent to the more lightly-doped second region of the ADP, and also comprising a second in-pixel storage capacitor and a controller configured to control each pixel of the plurality of pixels to, during an integration phase, alternately apply a first relative bias to the first clock gate and the second clock gate to direct photocharge generated in the ADP to the first in-pixel storage capacitor, and a second relative bias to the first clock gate and the second clock gate to direct photocharge generated in the ADP to the second in-pixel storage capacitor, and in a readout phase, read charge out from the first in-pixel storage capacitor and the second in-pixel storage capacitor. In some such examples, for each pixel of the plurality of pixels, the first pixel tap comprises a first bias gate between the first clock gate and the first in-pixel storage, and the second pixel tap comprises a second bias gate between the second clock gate and the second in-pixel storage. Additionally or alternatively, the controller is configured to control the first bias gate to set a first relative bias at the first bias gate during the integration phase to allow photocharge to flow to the first in-pixel storage, and to set a second relative bias at the first bias gate to prevent charge from backflowing. Additionally or alternatively, the first relative bias comprises a voltage that traps photocharge at the first clock gate, and a voltage on the second clock gate that directs photocharge trapped at the second clock gate across the second bias gate to the second in-pixel storage, and the second relative bias comprises a bias on the first clock gate that directs photocharge trapped at the first clock gate across the first bias gate to the first in-pixel storage, and a bias on the second clock gate that traps photocharge at the second clock gate. Additionally or alternatively, for each pixel of the plurality of pixels, the first pixel tap further comprises a first potential barrier positioned within the more lightly-doped second region adjacent to and spaced from the first clock gate, and the second pixel tap further comprises a second potential barrier positioned within the more lightly-doped second region adjacent to and spaced from the second clock gate. Additionally or alternatively, the depth image sensor further comprises a deep trench isolation region disposed between neighboring pixels of the plurality of pixels. Additionally or alternatively, the depth image sensor further comprises, for each pixel of the plurality of pixels, a divider region disposed within the more lightly-doped second region and between the first clock gate and the second clock gate, the divider region comprising the one of p-doping or n-doping. Additionally or alternatively, the more lightly-doped second region is doped at a doping concentration between 1.0% to 10% of a doping concentration of the doped first region. Additionally or alternatively, each pixel of the plurality of pixels further comprises a horizontal anti-blooming gate and a vertical anti-blooming gate. Additionally or alternatively, the controller is configured to operate the horizontal anti-blooming gate and the vertical anti-blooming gate between the integration phase and the readout phase to drain photocharge between the integration phase and the readout phase. Additionally or alternatively, the controller is configured to control the pixels outside the region of interest to, during the integration phase, drain photocharge in the ADP by operating one or more of the horizontal anti-blooming gate and the vertical anti-blooming gate.

Another example provides a depth image sensor, comprising a steerable illumination device configured to selectively illuminate a space in a 3D scene, an image sensor comprising a plurality of pixels, each pixel configured to sense light incident on the pixel, and each pixel of the plurality of pixels comprising a doped first region of the semiconductor die, the doped first region comprising one of p-doping or n-doping, and a more lightly-doped second region of the semiconductor die disposed within the doped first region, the more lightly-doped second region comprising the other of p-doping or n-doping, thereby forming an always-depleted photodiode (ADP), a pixel tap comprising a clock gate disposed adjacent to the more lightly-doped second region of the ADP, and in-pixel storage, a horizontal anti-blooming gate, and a vertical anti-blooming gate, and a controller. The controller is configured to steer illumination light to selectively illuminate a region of interest in the 3D scene, the region of interest in the 3D scene corresponding to a region of interest on the image sensor, for each pixel within the region of interest on the image sensor, control the pixel to during an integration phase, apply a bias to the clock gate to direct photocharge generated in the ADP to the in-pixel storage capacitor, and in a readout phase, read charge out from the in-pixel storage capacitor, and for each pixel outside the region of interest, control the pixel to energize one or more of the horizontal anti-blooming gate and the vertical anti-blooming gate to drain photocharge. Additionally or alternatively, for each pixel of the plurality of pixels, the pixel tap further comprises a potential barrier positioned within the more lightly-doped second region adjacent to and spaced from the clock gate. Additionally or alternatively, the controller is configured to, for each pixel within the region of interest, control the pixel to energize the horizontal anti-blooming gate and the vertical anti-blooming gate between the integration phase and the readout phase to drain photocharge between the integration phase and a subsequent integration phase.