Test apparatus

A main power supply is arranged such that its output terminal Po is connected to a power supply terminal of a DUT via a power supply line, and is configured to feedback control an output voltage VOUT output from the output terminal such that a detection value VDD′ that corresponds to a power supply voltage VDD at the power supply terminal approaches a target value VREF′. When a test pattern is supplied to the DUT, a power supply control unit is configured to feedforward control the main power supply such that the power supply voltage VDD approaches a predetermined target waveform VTGT.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to Japanese Patent Application No. 2012-045860 filed on Mar. 1, 2012, the disclosure of which is incorporated herein by reference in its entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a test apparatus configured to test a device under test, and particularly to a power supply circuit for the test apparatus.

2. Description of the Related Art

In a testing operation for a semiconductor integrated circuit (which will be referred to as the “DUT” hereafter) that employs CMOS (Complementary Metal Oxide Semiconductor) technology such as a CPU (Central Processing Unit), DSP (Digital Signal Processor), memory, or the like, electric current flows in a flip-flop or a latch included in the DUT while it operates receiving the supply of a clock. When the clock is stopped, the circuit enters a static state in which the amount of current decreases. Accordingly, the sum total of the operating current (load current) of the DUT changes over time depending on the content of the test operation, and so forth.

A power supply circuit configured to supply electric power to such a DUT has a configuration employing a regulator, for example. Ideally, such a power supply circuit is capable of supplying constant electric power regardless of the load current. However, in actuality, such a power supply circuit has an output impedance that is not negligible. Furthermore, between the power supply circuit and the DUT, there is an impedance component that is not negligible. Accordingly, the power supply voltage fluctuates due to fluctuation in the load.

Fluctuation in the power supply voltage seriously affects the test margin for the DUT. Furthermore, such fluctuation in the power supply voltage affects the operations of other circuit blocks included in the test apparatus, such as a pattern generator configured to generate a pattern to be supplied to the DUT, a timing generator configured to control the pattern transition timing, etc., leading to deterioration in the test accuracy.

With such a technique described in Patent document 2, a power supply apparatus includes a compensation circuit including a switch configured such that its switching on/off is controlled according to the output of a driver, in addition to a main power supply configured to supply power supply voltage to a device under test.

FIG. 1is a block diagram showing a configuration of a power supply apparatus including a compensation circuit investigated by the present inventors. A DUT1is arranged such that a power supply voltage VDDis supplied to a power supply terminal P1thereof, and a ground terminal P2thereof is grounded. Furthermore, a test pattern STESTis supplied to an I/O terminal P3of the DUT1from a driver included in an unshown test apparatus.

A power supply apparatus8includes a main power supply10and a power supply compensation circuit12, and is configured to supply the power supply voltage VDDto the power supply terminal P1of the DUT1. The output terminal of the main power supply10is connected to the power supply terminal P1of the DUT1via a power supply line. The main power supply10is configured as a combination circuit composed of a digital circuit and a digital/analog converter, a linear regulator, a switching regulator, or the like. The main power supply10is configured to receive a feedback signal that corresponds to the power supply voltage VDDat the power supply terminal P1, and to feedback control the output voltage VOUTsuch that the power supply voltage VDDmatches a target voltage VREF.

A source current source12bincluded in the power supply compensation circuit12is configured to perform a switching operation according to a control pattern SCNT1, and to inject a pulse-shaped compensation current ISRC(functions as a source) into the power supply terminal P1of the DUT1via a path that differs from that of the main power supply10. A sink current source12cis configured to perform a switching operation according to a control pattern SCNT2, and to draw a pulse-shaped compensation current ISINK(functions as a sink) via a path that differs from that of the DUT1.

With such an arrangement, the compensation control patterns SCNT1and SCNT2to be applied to the power supply compensation circuit12are defined such that they are associated with the test pattern STEST, so as to cancel out changes in the power supply voltage VDDthat occur according to the supply of the test pattern STESTto the DUT. In an actual test operation, by controlling the power supply compensation circuit12according to the control patterns SCNT1and SCNT2while supplying the test pattern STESTto the DUT1, such an arrangement allows the power supply voltage VDDto be maintained at a constant voltage.

RELATED ART DOCUMENTS

Patent Documents

It is rare for an ideal power supply to be employed in an environment in which such a DUT is actually operated (which will be referred to as an “actual operation environment”). In actuality, typical circuits employ a power supply having a poor response speed or having a large output impedance from the viewpoint of costs or the circuit area. In such an actual operation environment, the power supply voltage cannot be maintained at a constant voltage, i.e., it dynamically fluctuates according to the operation state of the DUT.

Thus, there is a demand for a technique in which, in such a test of a DUT, intentional fluctuation is applied to the power supply voltage so as to provide the same power supply environment as that in the actual operation environment of the DUT. Such a technique will be referred as an “emulation of a power supply environment” in the present specification. The aforementioned compensation circuit is effectively employed for such an emulation of a power supply environment. That is to say, the control patterns are determined so as to provide a desired power supply voltage waveform, and the compensation current generated by the compensation circuit is changed over time according to the control patterns thus generated.

SUMMARY OF THE INVENTION

The present inventors have investigated such an emulation of a power supply environment, and has come to recognize the following problem.

FIGS. 2A and 2Bare diagrams for describing such an emulation of a power supply environment. Let us consider a case in which the operating current IOPthat flows into the power supply terminal of the DUT1rises at a time point t1according to the test pattern.

FIG. 2Ashows an emulation operation in a case of emulating an ideal power supply having no power supply voltage fluctuation. VDDrepresents the waveform of the power supply voltage VDDwhen the power supply compensation circuit12is not operated. When the operating current IOPincreases at the time point t1, the power supply voltage VDDdrops from the target value VREFdue to the response delay of the main power supply10. Subsequently, the power supply voltage VDDapproaches the target value VREFwith the passage of time. VTGTrepresents the waveform of the power supply voltage to be emulated. In a case of emulating an ideal power supply, VTGTmatches a target value VREFwhich is a constant value.

The power supply compensation circuit12generates (i) a compensation current ICMPthat matches the fluctuation of the operating current IOP, or otherwise (ii) a compensation current ICMPthat matches the fluctuation of the operating current IOPimmediately after the time point t1, and which attenuates at a speed that is sufficiently slower than the response speed of the power supply voltage VDD. Such a power supply compensation circuit12allows the response speed of the main power supply10to be compensated for, thereby maintaining the power supply voltage VDDat a constant voltage.

FIG. 2Bshows an emulation operation in a case of emulating an actual operating environment. In this case, a power supply apparatus to be emulated has a non-negligible output DC resistance. In addition, the power supply to be emulated has a response speed that is slower than that of the main power supply10, leading to a long voltage recovery time. Accordingly, the power supply voltage VTGTto be emulated drops according to an increase in the operating current IOP. The main power supply10shown inFIG. 1is designed such that it has a very small output DC current resistance. Thus, in order to emulate the power supply voltage waveform VTGTshown inFIG. 2Bby means of the power supply apparatus8, the power supply compensation circuit12must always generate a very large negative compensation current ICMP(i.e., a sink current ISINK), leading to a problem of very large power consumption of the power supply apparatus8.

The present invention has been made in order to solve such a problem. Accordingly, it is an exemplary purpose of an embodiment of the present invention to provide a power supply apparatus which is capable of emulating a desired power supply voltage waveform with small power consumption.

An embodiment of the present invention relates to a test apparatus configured to test a device under test. The test apparatus comprises: a test unit configured to supply a predetermined test pattern to the device under test; a main power supply arranged such that its output terminal is connected to a power supply terminal of the device under test via a power supply line, and is configured to feedback control an output voltage output via the output terminal such that a detection value that corresponds to a power supply voltage at the power supply terminal approaches a target value; and a power supply control unit configured to feedforward control the main power supply such that the power supply voltage approaches a predetermined target waveform when the test unit supplies the test pattern to the device under test.

With such an embodiment, by feedforward controlling the feedback-type main power supply according to the waveform of the operating current of the device under test determined according to the test pattern, such an arrangement is capable of emulating a desired power supply voltage waveform.

Furthermore, even if the level of the target waveform after transition differs from that before transition, such an arrangement does not require very large power consumption of the main power supply. Thus, such an arrangement provides reduced power consumption as compared with an arrangement in which intentional fluctuation is applied to the power supply voltage by means of the compensation circuit alone.

Also, the main power supply may comprise: an error signal generating unit configured to generate an error signal that corresponds to an error between the detection value and the target value; and a feedback output unit configured to feedback control the output voltage according to the error signal such that the error becomes zero. Also, the power supply control unit may be configured to superimpose on the target value a correction voltage that corresponds to the target waveform.

Such an embodiment allows the target value for the feedback control operation of the main power supply to be changed according to the target waveform, thereby controlling the power supply voltage such that it approaches the target waveform.

Also, the main power supply may comprise: an error signal generating unit configured to generate an error signal that corresponds to an error between the detection value and the target value; and a feedback output unit configured to feedback control the output voltage according to the error signal such that the error becomes zero. Also, the power supply control unit may be configured to superimpose on the detection value a correction voltage that corresponds to the target waveform.

Such an embodiment allows the target value for the feedback control operation of the main power supply to be changed according to the target waveform, thereby controlling the power supply voltage such that it approaches the target waveform.

Also, the power supply control unit may comprise: a first waveform acquisition unit configured to acquire a first waveform, which is a waveform of the power supply voltage supplied to the device under test in a state in which the target value set for the main power supply is fixed, when the device under test operates according to the test pattern; a target waveform acquisition unit configured to acquire the target waveform; and a correction voltage calculation unit configured to calculate the correction voltage based on the differential waveform between the first waveform and the target waveform.

The differential waveform represents the waveform of voltage fluctuation to be intentionally applied to the power supply voltage by means of the main power supply. Thus, by calculating the correction voltage according to the differential waveform, such an arrangement is capable of controlling the power supply voltage such that it approaches the target waveform.

Also, the correction voltage calculation unit may be configured to generate the correction voltage by multiplying the differential waveform by a predetermined coefficient K. Also, the coefficient K may be represented by VREF/VDD, with VREFas the target value when the correction voltage is zero, and with VDDas the power supply voltage.

Also, the correction voltage calculation unit may be configured to generate the correction voltage by multiplying the differential waveform by an inverse function of a transfer function of the main power supply.

Also, the correction voltage calculation unit may be configured to boost a high-frequency component of the differential waveform.

The high-frequency component range of the transfer function of the main power supply has a low gain. Thus, by boosting the high-frequency component beforehand, such an arrangement is capable of controlling the power supply voltage such that it approaches the target waveform.

Also, a test apparatus according to an embodiment may further comprise a compensation circuit configured such that, when the device under test executes a given operation sequence in response to the test pattern, the aforementioned compensation circuit (i) injects a compensation current that corresponds to the operation sequence into the power supply terminal via a path that differs from that of the main power supply, and additionally or alternatively (ii) draws, via a path that differs from that of the device under test, the compensation current from the power supply current that flows from the main power supply to the device under test.

Also, the power supply control unit may further comprise: a second waveform acquisition unit configured to acquire a second waveform, which is a waveform of the power supply voltage supplied to the device under test in a state in which the main power supply is feedforward controlled by the power supply control unit, when the device under test operates in response to the test pattern; and a compensation current calculation unit configured to calculate the compensation current to be generated by the compensation circuit, based on the differential waveform between the second waveform and the target waveform.

In some cases, an arrangement including the main power supply alone cannot control the power supply voltage such that it perfectly matches the target waveform. In this case, by providing such a compensation circuit having a responsiveness that is higher than that of the main power supply, such an arrangement is capable of controlling the power supply voltage such that it approaches closer to the target waveform.

Also, the main power supply may comprise: an error signal generating unit configured to generate an error signal that corresponds to the error between the detection value and the target value; and a feedback output unit configured to feedback control the output voltage according to the error signal such that the error becomes zero. Also, at least one from among a transfer function of the error signal generating unit and a transfer function of the feedback output unit is configured to be adjustable. Also, the power supply control unit may be configured to control the transfer function of the error signal generating unit and the transfer function of the feedback output unit according to the target waveform.

Also, the main power supply may be configured as a switching regulator. Also, the power supply control unit may be configured to control at least one from among a switching frequency of the switching regulator, a transistor size (i.e., on resistance) of a switching transistor, an amplitude of a driving signal (gate voltage or otherwise base current) to be supplied to the switching transistor, and an inductance of an inductor.

Also, the main power supply may be configured as a digital control power supply. Also, the error signal generating unit may comprise a subtractor configured to generate deviation between the detection value and the target value. Also, the feedback output unit may comprise a digital calculation unit configured to perform any one from among P (Proportional) control, PI (Proportional Integral) control, and PID (Proportional Integral Derivative) control. Also, the power supply control unit may be configured to control a control parameter of the digital calculation unit.

Also, the main power supply may be configured as an analog control power supply. Also, the error signal generating unit may comprise: an error amplifier configured to amplify an error between the detection value and the target value; and a phase compensation circuit provided to the error amplifier. Also, the power supply control unit may be configured to control at least one from among a bias current of the error amplifier and a time constant of the phase compensation circuit.

It is to be noted that any arbitrary combination or rearrangement of the above-described structural components and so forth is effective as and encompassed by the present embodiments. Moreover, this summary of the invention does not necessarily describe all necessary features so that the invention may also be a sub-combination of these described features.

DETAILED DESCRIPTION OF THE INVENTION

In the present specification, a state represented by the phrase “the member A is connected to the member B” includes a state in which the member A is indirectly connected to the member B via another member that does not affect the electric connection therebetween, in addition to a state in which the member A is physically and directly connected to the member B. Similarly, a state represented by the phrase “the member C is provided between the member A and the member B” includes a state in which the member A is indirectly connected to the member C, or the member B is indirectly connected to the member C via another member that does not affect the electric connection therebetween, in addition to a state in which the member A is directly connected to the member C, or the member B is directly connected to the member C.

FIG. 3is a block diagram which shows a configuration of a test apparatus according to an embodiment.FIG. 3shows a semiconductor device (which will be referred to as “DUT” hereafter)1to be tested, in addition to the test apparatus2.

The DUT1includes multiple pins. At least one of the multiple pins is a power supply terminal P1configured to receive a power supply voltage VDD, and at least one other pin is configured as a ground terminal P2. The multiple input/output (I/O) pins P3are each configured to receive data from outside the circuit or to output data to outside the circuit. In the test operation, the multiple input/output terminals P3receive a test signal (test pattern) STESToutput from the test apparatus2, or output data that corresponds to the test signal STESTto the test apparatus2.FIG. 3shows only a part of the configuration of the test apparatus2, which is configured to supply a test signal to the DUT1. That is to say, another configuration thereof configured to evaluate a signal received from the DUT1is not shown.

The test apparatus2includes a power supply apparatus8, a pattern generator PG, multiple timing generators TG, multiple waveform shapers FC, and multiple drivers DR.

The test apparatus2includes multiple channels, i.e., n channels CH1through CHn, several channels (CH1through CH4) of which are respectively assigned to the multiple I/O terminals P3of the DUT1.FIG. 3shows an arrangement in which n=7. However, in practical use, the number of channels of the test apparatus2is on the order of several hundred to several thousand. With the test apparatus2, the first through the fourth channels CH1through CH4each function as a test unit configured to supply a test pattern to the DUT1.

The power supply apparatus8is configured to generate the power supply voltage VDDto be supplied to the power supply terminal P1of the DUT1. The power supply apparatus8includes a main power supply10and a power supply compensation circuit12.

The main power supply10is configured as a linear regulator, a switching regulator, a combination circuit composed of a digital circuit and a digital/analog converter, or the like. Specifically, the output terminal Po of the main power supply10is connected to the power supply terminal P1of the DUT1via a power supply line LVDD.

Typically, the impedance of the power supply line VDDis not zero. Thus, the output voltage VOUTof the main power supply10is not the same as the power supply voltage VDDat the power supply terminal P1. The detection value VDD′ that corresponds to the power supply voltage VDDat the power supply terminal P1is fed back to the main power supply10. The main power supply10is configured to feedback control the output voltage VOUToutput via the output terminal Po such that the detection value VDD′ that corresponds to the power supply voltage VDDapproaches the target value VREF. It should be noted that, in a case in which there is no need to reduce the effects of the impedance of the power supply line LVDD, the detection value VDD′ may be obtained based on the output voltage VOUTthat develops in the vicinity of the output terminal of the main power supply10.

The capacitor Cs is provided in order to smooth the power supply voltage VDD. The main power supply10is configured to generate a power supply voltage to be supplied to the DUT1. In addition, the main power supply10is further configured to generate a power supply voltage to be supplied to the other circuit blocks included in the test apparatus2. The output current flowing from the main power supply10to the power supply terminal P1of the DUT1will be referred to as the “power supply current IDD”.

The main power supply10is configured as a voltage/current source having a limited response speed. Accordingly, in some cases, the main power supply10cannot follow a sudden change in the load current, i.e., the operating current IOPof the DUT1. For example, when the operating current IOPchanges in a stepwise manner, overshoot or undershoot occurs in the power supply voltage VDD, following which, in some cases, ringing occurs in the power supply voltage VDD. Such fluctuation in the power supply voltage VDDleads to difficulty in testing the DUT1with high precision. This is why, when an error is detected in the operation of the DUT1, such an arrangement cannot judge whether such an error is due a manufacturing fault in the DUT1or due to the fluctuation in the power supply voltage VDD.

The power supply compensation circuit12is provided in order to compensate for the response speed of the main power supply10. The designer of the DUT1can estimate the change in the operating rate of an internal circuit of the DUT1and the like over time when a known test signal STEST(test pattern SPTN) is supplied to the DUT1. Accordingly, the designer can predict the waveform of the operating current IOPof the DUT1over time with high precision. Examples of such a prediction method include a calculation method using computer simulation, or an actual measurement method in which a device having the same configuration as that of the DUT1is measured. Such a prediction method is not restricted in particular.

Furthermore, in a case in which the response speed of the main power supply10(gain, feedback band) is known, the designer can also estimate the power supply current IDD, the output voltage VOUT, and the power supply voltage VDD, generated by the main power supply10according to the estimated operating current IOP. In this case, by compensating for the difference between the estimated operating current IOPand the estimated power supply current IDDby means of the power supply compensation circuit12, such an arrangement is capable of stabilizing the power supply voltage VDD.

It should be noted that there is a differential relation or otherwise an integral relation between the power supply voltage VDD′ and the power supply current IDD. Specifically, whether the relation between the voltage and the current is a differential relation or an integral relation is determined depending upon which component is dominant from among the capacitance, the inductance, and the resistance, with respect to the output impedance of the main power supply10and the impedance of a path from the main power supply10up to the power supply terminal P1.

The power supply compensation circuit12includes a source current source12band a sink current source12c. The source current source12band the sink current source12ceach include a switch using a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), for example, and are respectively controlled according to the respective control signals SCNT1and SCNT2.

When the source current source12bis turned on according to the control signal SCNT1, a compensation pulse current (which will also be referred to as the “source pulse current”) ISRCis generated. The power supply compensation circuit12injects the source pulse current ISRCinto the power supply terminal P1via a path that differs from that of the main power supply10. The sink current source12cis arranged between another fixed voltage terminal (e.g., the ground terminal) and the power supply terminal P1of the DUT1. When the sink current source12cis turned on according to the control signal SCNT2, a compensation pulse current ISINK(which will also be referred to as the “sink pulse current”) is generated. The power supply compensation circuit12draws, via a path that differs from that to the DUT1, the sink pulse current ISINKfrom the power supply current IDDthat flows to the power supply terminal P1.

The relation between the operating current Iopthat flows into the power supply terminal P1of the DUT1, the power supply current IDDoutput from the main power supply10, and the compensation current ICMPoutput from the power supply compensation circuit12, is represented by the following Expressions (1) and (2) based on the law of conservation of current.
IOP=IDD+ICMP(1)
ICMP=ISRC−ISINK(2)

That is to say, the source current source12bsupplies the positive component of the compensation current ICMPas a source pulse current ISRC. Furthermore, the sink current source12csupplies the negative component of the compensation current ICMPas a sink pulse current ISINK.

Among the drivers DR1through DR6, the driver DR6is assigned to the source current source12b, and the driver DR5is assigned to the sink current source12c. Of the other drivers, i.e., the drivers DR1through DR4, at least one is respectively assigned to at least one of the I/O terminals P3of the DUT1.

A pair comprising the waveform shaper FC and the timing generator TG is collectively referred to as an “interface circuit4”. Multiple interface circuits41through46are respectively provided for the channels CH1through CH6, i.e., for the drivers DR1through DR6. The i-th (1≦i≦6) interface circuit4ishapes the input pattern signal SPTNisuch that it has a signal format that is suitable for the driver DR, and outputs the pattern signal thus shaped to the corresponding driver DRi.

The pattern generator PG generates the pattern signals SPTNfor the interface circuits41through46according to a test program. Specifically, with regard to the drivers DR1through DR4respectively assigned to the I/O terminals P3of the DUT1, the pattern generator PG outputs the test patterns SPTNi, each specifying a test signal STESTito be generated by the corresponding driver DRi, to the respective interface circuits4ithat correspond to the respective drivers DRi. Each test pattern SPTNiincludes data which represents the signal level of the test signal STESTifor each cycle (unit interval), and data which indicates the timing at which the signal level transits.

Furthermore, the pattern generator PG generates the compensation control pattern SPTN—CMPdetermined according to the required compensation current ICMP. The control pattern SPTN—CMPincludes a control pattern SPTN—CMP1that specifies the control signal SCNT1which is to be generated by the driver DR6assigned to the source current source12b, and a control pattern SPTN—CMP2that specifies the control signal SCNT2which is to be generated by the driver DR5assigned to the sink current source12c. The control pattern SPTN—CMP1includes data which specifies the on/off state of the source current source12band its on/off switching timing, and the control pattern SPTN—CMP2includes data which specifies the on/off state of the sink current source12cand its on/off switching timing.

The pattern generator PG generates the control patterns SPTN—CMP1and SPTN—CMP2which provide compensation for fluctuation in the operating current of the DUT1based on the test patterns SPTN1through SPTN4, i.e., according to the fluctuation in the operating current of the DUT1. Subsequently, the pattern generator PG outputs the control patterns SPTN—CMP1and SPTN—CMP2thus generated to the respective interface circuits46and45.

As described above, if the test patterns SPTN1through SPTN4are known, the waveform over time of the operating current IOPof the DUT1can be estimated. Thus, the compensation current ICMPto generated in order to maintain the power supply voltage VDDat a constant voltage, i.e., the waveforms over time of the compensation currents ISRCand ISINKcan be calculated.

When the estimated operating current IOPis greater than the power supply current IDD, the power supply compensation circuit12generates a source compensation current ISRCso as to compensate for a shortfall in the current. The required current waveform of such a source compensation current ISRCcan be predicted. Thus, the source current source12bis controlled so as to appropriately generate such a source compensation current ISRC. For example, the source current source12bmay be controlled by pulse width modulation. Alternatively, pulse amplitude modulation, delta-sigma modulation, pulse density modulation, pulse frequency modulation, or the like, may be employed.

With such a test apparatus2, the fifth channel CH5and the sixth channel CH6correspond to a power supply control unit configured to control the power supply compensation circuit12.

FIG. 4is a flowchart showing an example of a method for calculating the control pattern. The operating current IOPof the DUT1is estimated based on the test pattern input to the DUT1and/or the circuit information (S100). Furthermore, such an arrangement calculates the power supply current IDDoutput from the main power supply10for when a given event occurs in a state in which the DUT1is connected as a load to the main power supply10(S102). In a case in which an ideal power supply is to be provided, the compensation current ICMPto be generated by the power supply compensation circuit12is set to the difference between the estimated operating current IOPand the power supply current IDD(S104).

Subsequently, the waveform of the compensation current ICMPto be generated is subjected to delta-sigma modulation, PWM (pulse width modulation), PDM (pulse density modulation), PAM (pulse amplitude modulation), PFM (pulse frequency modulation), or the like, so as to generate a bitstream control pattern SPTN—CMP(S106). For example, an arrangement may be made in which the compensation current ICMPis sampled for each test cycle, and the compensation circuit ICMPthus sampled is subjected to pulse modulation.

FIG. 5is a waveform diagram which shows an example of the operating current IOP, the power supply current IDD, the compensation current ICMP, and the source pulse current ISRC. Let us say that, when a certain test signal STESTis supplied to the DUT1, the operating current IOPof the DUT1rises in a stepwise manner. In response to the increase in the operating current IOP, the power supply current IDDis supplied from the main power supply10. However, such a power supply current IDDdoes not have an ideal step waveform because of the limited response speed. This leads to a shortfall in the current to be supplied to the DUT1. As a result, if the compensation current ISRCis not supplied, the power supply voltage VDDfalls as indicated by the broken line.

The power supply compensation circuit12generates the source compensation current ICMPthat corresponds to the difference between the operating current IOPand the power supply current IDD. The source compensation current ICMPis generated as the source pulse current ISRCgenerated according to the control signal SCNT1. The source compensation current ICMPis required to be at its maximum value immediately after the change in the operating current IOP, and is required to gradually fall from its maximum value. Accordingly, the on time (duty ratio) of the source current source12bis reduced over time using PWM (pulse width modulation), for example, thereby generating the required source compensation current ICMP.

In a case in which all the channels of the test apparatus2operate in synchronization with a test rate, the period of the control signal SCNT1matches the period (unit interval) of data to be supplied to the DUT1, or a period obtained by multiplying or dividing the period of the data by an integer. For example, in a case in which the period of the control signal SCNT1is set to 4 ns in a system in which the unit interval is 4 ns, the on period TONof each pulse included in the control signal SCNT1can be adjusted in a range between 0 and 4 ns. The response speed of the main power supply10is on the order of several hundred ns to several μs. Thus, the waveform of the compensation current ICMPcan be controlled by adjusting several hundred of the pulses included in the control signal SCNT1. A method for deriving the control signal SCNT1required to generate the source compensation current ICMPbased upon the waveform thereof will be described later.

Conversely, when the operating current IOPis smaller than the power supply current IDD, the power supply compensation circuit12generates a sink pulse current ISINKso as to provide the sink compensation current ICMP, thereby drawing the excess current.

By providing such a power supply compensation circuit12, such an arrangement is capable of compensating for a shortfall in the response speed of the main power supply10, thereby maintaining the power supply voltage VDDat a constant level as indicated by the solid line inFIG. 4. It should be noted that the configuration of the power supply compensation circuit12is not restricted in particular. Rather, various kinds of current sources and various kinds of voltage sources may be employed as the power supply compensation circuit12.

Description has been made regarding an arrangement in which the power supply apparatus8is operated as an ideal power supply which is capable of maintaining its power supply voltage VDDat a constant level regardless of the operating state of the DUT1. Description will be made below regarding a technique for emulating a desired power supply voltage waveform by intentionally applying fluctuation to the power supply voltage VDDby means of the power supply apparatus8.

Returning toFIG. 3, with the test apparatus2, the seventh channel CH7corresponds to a main power supply control unit configured to control the main power supply10.

When the test unit (CH1through CH4) supplies the test pattern STESTto the DUT1, the main power supply control unit (CH7) feedforward controls the main power supply10such that the power supply voltage VDDapproaches a predetermined target waveform VTGT(t).

Description will be made regarding a specific example of the feedforward control operation.

FIGS. 6A and 6Bare block diagrams each showing an example configuration of the main power supply10. As shown inFIGS. 6A and 6B, a typical feedback control power supply configured to perform an analog control operation or otherwise a digital control operation includes an error signal generating unit112configured to generate an error signal VERRthat corresponds to the error (deviation) between the detection value VDD′ of the power supply voltage VDDand the target value VREF′, and a feedback output unit114configured to feedback control the output voltage VOUTaccording to the error signal VERRsuch that the error between them becomes zero.

The correction voltage ΔVCMP(t) is fed forward to the main power supply10from an unshown main power supply control unit. With such a configuration shown inFIG. 6A, the main power supply control unit is configured to superimpose the correction voltage ΔVCMP(t) that corresponds to the target waveform VTGT(t) on the target value VREF′. On the other hand, with such a configuration shown inFIG. 6B, the main power supply control unit is configured to superimpose the correction ΔVCMP(t) that corresponds to the target waveform VTGT(t) on the detection value VDD′(t).

FIG. 7is a block diagram showing a specific example configuration of the main power supply10shown inFIG. 6A. The main power supply10shown inFIG. 7is configured as an analog control power supply, and mainly includes a reference voltage source110, an error amplifier112, and a feedback output unit114. The reference voltage source110includes a bandgap reference circuit, for example, and is configured to generate a reference voltage VREFwhich does not depend on either the temperature or the power supply voltage. The error signal generating unit112is configured as a so-called error amplifier which amplifies the error (deviation) between the detection value VDD′ and the target value VREF′ so as to generate an error signal VERR. For example, a voltage dividing circuit130, which divides the power supply voltage VDDby a predetermined voltage division ratio K, is provided on a feedback path of the power supply voltage VDD, thereby generating the detection value VDD′.

The feedback output unit114is configured to feedback control the output voltage VOUTsuch that the error between the two voltages VREF′ and VDD′ becomes zero. The feedback output unit114includes a feedback circuit116and a power output stage118. The feedback circuit116is configured to generate an instruction value having a level adjusted according to the error signal VERRsuch that the error between the detection value VDD′ and the target value VREF′ becomes zero. The power output stage118is configured to generate an output voltage VOUTaccording to the instruction value.

A main power supply control unit90ais configured to superimpose the correction voltage ΔVCMP(t) that corresponds to the target waveform VTGT(t) on the target value VREF′. In order to provide such a function, the main power supply10shown inFIG. 7includes an adder120and a digital/analog converter122. The digital/analog converter122is configured to receive, from the main power supply control unit90a, the data (which will be referred to as the “main power supply control pattern”) SMAINwhich represents the correction voltage ΔVCMP(t), and to convert the data SMAINthus received into an analog voltage ΔVCMP.

The adder120is configured to generate the sum of the reference voltage VREFand the correction voltage ΔVCMP, thereby superimposing the correction voltage ΔVCMP(t) on the target value VREF′. As described later, by appropriately determining the correction voltage ΔVCMP(t) according to the target waveform VTGT(t), the target voltage VREF′ is feedforward controlled, thereby allowing the power supply voltage VDDto be controlled such that it approaches the target waveform VTGT.

FIG. 8is a block diagram showing an example configuration of a power supply control unit90. The power supply control unit90includes the main power supply control unit90aconfigured to control the main power supply10, and a compensation circuit control unit90bconfigured to control the power supply compensation circuit12.

As described above, the main power supply control unit90aincludes the pattern generator PG, the interface circuit47, and the driver DR7.FIG. 8shows a part that corresponds to the pattern generator PG of the power supply control unit90.

The power supply control unit90includes a first waveform acquisition unit91, a target waveform acquisition unit92, a subtractor93, a correction voltage calculation unit94, an encoder95, a second waveform acquisition unit96, a subtractor97, a compensation current calculation unit98, and an encoder99. First, description will be made regarding the generation of the control pattern SPTN−MAIN.

The control pattern SPTN—MAINis generated by the main power supply control unit90a, which includes the first waveform acquisition unit91, the target waveform acquisition unit92, the subtractor93, the correction voltage calculation unit94, and the encoder95.

The test pattern STEST, which is an instruction supplied to the DUT1from the pattern generator PG, is known. Thus, the waveform over time of the operating current IOPof the DUT1can be estimated. Furthermore, if the characteristics of the error amplifier112, the feedback circuit116, and the power output stage118, which are included in the main power supply10, are known, the waveform of the power supply voltage VDDthat corresponds to the operating current waveform IOP(which will also be referred to as the “first waveform VDD1(t)”) can also be estimated. The first waveform VDD1(t) represents a power supply voltage waveform in a case in which the power supply control unit90does not feedforward control the main power supply10(i.e., the target value is fixed), and the power supply compensation circuit12does not perform a compensation operation. The first waveform acquisition unit91is configured to calculate the first waveform VDD1(t), or otherwise to acquire the first waveform VDD1(t) by actual measurement.

The target waveform acquisition unit92is configured to acquire the target waveform VTGT(t). The target waveform VTGT(t) is prepared beforehand by the user.

The subtractor93is configured to generate the differential waveform ΔVDD1(t), which is the difference between the first waveform VDD1(t) and the target waveform VTGT(t). The correction voltage calculation unit94is configured to calculate the correction voltage ΔVCMP(t) based on the differential waveform VDD1(t).

For example, the correction voltage calculation unit94is configured to multiply the differential waveform ΔVDD1(t) by a predetermined coefficient K, so as to generate the correction voltage ΔVCMP(t). The coefficient K is represented by the ratio VREF/VDDwith VREFas the target value in a static state in which the correction voltage ΔVCMPis zero and with VDDas the power supply voltage VDD. Referring to the circuit diagram shown inFIG. 7, the coefficient K corresponds to the division ratio K of the voltage dividing circuit130.

A modification may be made in which the correction voltage calculation unit94multiplies the differential waveform ΔVDD1(t) by the inverse function of the transfer function H(s) of the main power supply10, which is represented by VOUT/VREF, so as to calculate the correction voltage ΔVCMP(t). In a case in which the differential waveform ΔVDD1(t) is multiplied by the coefficient K, such an arrangement provides a correction voltage that is not influenced by the frequency characteristics. In contrast, in a case in which the differential waveform ΔVDD1(t) is multiplied by the inverse function of the transfer function H(s), such an arrangement provides a correction voltage that is also influenced by the frequency characteristics.

Also, before the correction voltage calculation unit94calculates the correction voltage ΔVCMP(t), the high-frequency component of the differential waveform ΔVDD1(t) may be boosted. In a typical transfer function of the main power supply10, the high-frequency component has a low gain. Thus, by boosting the high-frequency component of the differential waveform ΔVDD1(t) beforehand, such an arrangement is capable of controlling the power supply voltage VDDsuch that it approaches the target waveform VTGT(t).

The encoder95is configured to encode the correction voltage ΔVCMP(t) in a predetermined format, so as to generate the control pattern SPTN—MAINfor the main power supply10. The format may be determined according to the configuration of the interface circuit4and the main power supply10, and is not restricted in particular.

Next, description will be made regarding the control pattern SPTN—CMPto be supplied to the power supply compensation circuit12. The control pattern SPTN—CMPis generated by the compensation circuit control unit90bincluding the second waveform acquisition unit96, the subtractor97, the compensation current calculation unit98, and the encoder99.

When the DUT1operates according to the test pattern STEST, the second waveform acquisition unit96is configured to acquire the waveform of the power supply voltage in a state in which the main power supply10is feedforward controlled using the correction voltage ΔVCMP(t), and the operation of the power supply compensation circuit12is stopped (which will be referred to as the “second waveform VDD2(t)”). The second waveform VDD2(t) can be calculated, or otherwise can be acquired by actual measurement.

The subtractor97is configured to generate the differential voltage ΔVDD2(t), which is the difference between the second waveform VDD2(t) and the target waveform VTGT. The compensation current calculation unit98is configured to calculate the compensation current ICMPto be generated by the power supply compensation circuit12, based on the differential voltage ΔVDD2(t). The encoder99is configured to apply pulse modulation or the like to the compensation current ICMPso as to generate the control pattern SPTN—CMP.

The above is the configuration of the test apparatus2. Next, description will be made regarding the operation of the test apparatus2.

FIG. 9is a waveform diagram showing a power supply voltage waveform emulation provided by the test apparatus2shown inFIG. 3.

When a certain test pattern STESTis supplied to the DUT1, the operating current IOPof the DUT1suddenly rises at the time point t1. In this case, the target waveform VTGTto be emulated drops according to the increase in the operating current IOP, following which the target waveform VTGTis maintained at a dropped level.

The correction voltage ΔVCMP(t) is calculated based on the difference between the first waveform VDD1(t) and the target waveform VTGT(t). The correction voltage ΔVCMP(t) thus calculated is fed forward to the main power supply10, thereby allowing the second waveform VDD2(t) to be controlled such that it is closer to the target waveform VTGT(t) than is the first waveform VDD1(t).

Furthermore, the correction current ICMPis calculated based on the difference ΔVDD2(t) between the second waveform VDD2(t) and the target waveform VTGT(t), and the correction current ICMPis generated by means of the power supply compensation circuit12, thereby controlling the power supply voltage VDD(t) such that it approaches closer to the target waveform VTGT(t).

The above is the operation of the test apparatus2.

With the test apparatus2according to the embodiment, by feedforward controlling the feedback-type main power supply10according to the operating current IOPof the DUT1which is determined by the test pattern STEST, such an arrangement allows a desired power supply voltage waveform to be emulated.

As described above with reference toFIG. 2, in a case in which such a feedforward control operation is not performed for the main power supply10, in a case in which the level of the target waveform VTGT(t) after transition differs from the level before transition, such an arrangement is required to generate the compensation current ICMPat all times, leading to a problem of large power consumption of the power supply apparatus8. In contrast, with the test apparatus2according to the embodiment, the compensation current ICMPis generated only in a short period of time immediately after the time point t1. Furthermore, such a feedforward control operation does not require large current consumption of the main power supply10. Thus, such an arrangement allows power consumption to be reduced as compared with an arrangement in which intentional fluctuation is applied to the power supply voltage by means of the compensation circuit alone.

Description has been made regarding the present invention with reference to the embodiments. The above-described embodiment has been described for exemplary purposes only, and is by no means intended to be interpreted restrictively. Rather, it can be readily conceived by those skilled in this art that various modifications may be made by making various combinations of the aforementioned components or processes, which are also encompassed in the technical scope of the present invention. Description will be made below regarding such modifications.

Description has been made above regarding a feedforward control operation in which the target value or otherwise the detection value is controlled according to the target waveform VTGT. However, the present invention is not restricted to such an arrangement.FIG. 10is a block diagram showing a configuration of a test apparatus2according to a first modification. A main power supply10includes an error signal generating unit112and a feedback output unit114. With such a modification, at least one of the error signal generating unit112or the feedback output unit114is configured to have an adjustable transfer function. A main power supply control unit90ais configured to control the transfer function of the error signal generating unit112or the transfer function of the feedback output unit114according to the target waveform VTGT(t).

For example, the main power supply10is configured as a switching regulator. In this case, the main power supply control unit90amay control at least one of the switching frequency of the switching regulator, the transistor size of the switching transistor, the amplitude of the driving signal for the switching transistor (gate voltage or otherwise the base current), or the inductance of the inductor, according to the target waveform. Such an arrangement allows the transfer function of the feedback output unit114to be changed, thereby providing such a feedforward control operation such that the power supply voltage VDDapproaches the target waveform VTGT(t). The size of the switching transistor can be changed by configuring the switching transistor such that multiple transistor units each having a gate terminal that can be switched independently are connected in parallel, and by changing the number of transistor units that are switched on and off.

Alternatively, an arrangement may be made in which the switching regulator is configured as a synchronous rectification switching regulator, and the operating mode is switched between (i) a mode in which the switching transistor and the synchronous rectification transistor are switched in a complementary manner and (ii) a mode in which the switching operation of the synchronous rectification transistor is stopped so as to cause it to function as a rectifier element (diode), and a switching operation of only the switching transistor is performed.

Also, an arrangement may be made in which multiple channels of switching regulator units are arranged in parallel, and the number of operating channels is changed. With such an arrangement, the multiple channels may be driven in phase or otherwise by multiphase driving. Such an arrangement also allows the transfer function to be controlled. Also, the phase difference between respective channels may be changed so as to control the transfer function.

The main power supply10may be configured as a digital control power supply. In this case, the error signal generating unit112includes a subtractor configured to generate the deviation between the detection value VDD′ and the target value VREF′. Furthermore, the feedback output unit114includes a digital calculation unit configured to perform at least one of P (Proportional) control, PI (Proportional Integral) control, or PID (Proportional Integral Derivative) control. The main power supply control unit90amay control the control parameters of the digital calculation unit so as to control the transfer function.

Examples of adjustments of the control parameters include: (1) adjustment of coefficients and constants defined in the digital calculation unit; and (2) adjustment of calculation processing executed by the digital calculation unit.

With the former adjustment arrangement, the main power supply10may feedforward control the parameters a and b of the transfer function H(s) defined by H(s)=b/(1+a·s). Alternatively, the sampling frequency of the digital calculation processing may be adjusted.

Examples of the latter adjustment arrangements include switching of the filter format of the digital calculation unit. More specifically, the filter may be switched between an FIR (Finite Impulse Response) filter and an IIR (Infinite Impulse Response) filter. Alternatively, the order or the number of stages of such an FIR filter or otherwise an IIR filter may be switched.

The main power supply10may be configured as an analog control power supply. In this case, the error signal generating unit112includes an error amplifier configured to amplify the error between the detection value VDD′ and the target value VREF′, and a phase compensation circuit provided to the error amplifier. The main power supply control unit90amay control at least one of the bias current of the error amplifier or the time constant of the phase compensation circuit. By adjusting the bias current of the error amplifier, such an arrangement is capable of adjusting the response speed and the offset voltage of the error amplifier.

In a case in which the second waveform VDD2(t) obtained only by the feedforward control operation of the main power supply10has sufficient accuracy so as to meet the requirements, or in a case in which the target waveform VTGT(t) is to be changed at a rate that can be followed by the main power supply10, the power supply compensation circuit12may be omitted.

Description has been made in the embodiment regarding an arrangement in which the power supply compensation circuit12includes both the source current source12band the sink current source12c. However, the present invention is not restricted to such an arrangement. Also, the power supply compensation circuit12may include the source current source12balone or otherwise the sink current source12calone. In a case in which the power supply compensation circuit12includes the source current source12balone, the power supply compensation circuit12instructs the source current source12bto generate a constant current IDC. With such an arrangement, if a shortfall occurs in the power supply current IDDwith respect to the operating current IOP, the current ISRCgenerated by the source current source12bis relatively increased from the constant current IDC. Conversely, in a case in which the power supply current IDDis excessive with respect to the operating current IOP, the current ISRCgenerated by the source current source12bis relatively reduced from the constant current IDC.

In a case in which the power supply compensation circuit12may include the sink current source12calone, the power supply compensation circuit12instructs the sink current source12cto generate a constant current IDC. With such an arrangement, if a shortfall occurs in the power supply current IDDwith respect to the operating current IOP, the current ISINKgenerated by the sink current source12cis relatively reduced from the constant current IDC. Conversely, in a case in which the power supply current IDDis excessive with respect to the operating current IOP, the current ISINKgenerated by the sink current source12cis relatively increased from the constant current IDC.

Such an arrangement has a disadvantage of an increase in the overall current consumption of the test apparatus, due to the amount of constant current IDC. However, as a tradeoff, such an arrangement requires only a single switch to generate the compensation currents ISRCor ISINK.