INTEGRATED CIRCUIT DESIGN METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT

A system including a processor configured to perform generating a plurality of different layout blocks; selecting, among the plurality of layout blocks, layout blocks corresponding to a plurality of blocks in a floorplan of a circuit; combining the selected layout blocks in accordance with the floorplan into a layout of the circuit; and storing the layout of the circuit in a cell library or using the layout of the circuit to generate a layout for an integrated circuit (IC) containing the circuit. Each of the plurality of layout blocks satisfies predetermined design rules and includes at least one of a plurality of different first block options associated with a first layout feature, and at least one of a plurality of different second block options associated with a second layout feature different from the first layout feature.

BACKGROUND

An integrated circuit (“IC”) device includes one or more semiconductor devices represented in an IC layout (also referred to as “IC layout diagram”). A layout diagram is hierarchical and includes modules which carry out higher-level functions in accordance with the semiconductor device's design specifications. The modules are often built from a combination of cells, each of which represents one or more semiconductor structures configured to perform a specific function. Cells having pre-designed layout diagrams are stored in cell libraries (sometimes referred to as “libraries” for simplicity) and accessible by various tools, such as electronic design automation (EDA) tools, to generate, optimize and verify designs for ICs.

Layout diagrams are generated in a context of design rules. A set of design rules imposes constraints on the placement of corresponding patterns in a layout diagram, e.g., geographic/spatial restrictions, connectivity restrictions, or the like. Often, a set of design rules includes a subset of design rules pertaining to the spacing and other interactions between patterns in adjacent or abutting cells where the patterns represent conductors in a layer of metallization. Routing is where the different devices in a device are connected.

DETAILED DESCRIPTION

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Source/drain(s) may refer to a source or a drain, individually or collectively dependent upon the context.

In an integrated circuit (IC) design process, a design of an IC device is provided by a circuit designer. An IC layout of the IC device is generated based on the design, e.g., by a placement and routing operation. Various checks and/or simulations are performed for the generated IC layout. When one or more of the checks or simulations indicate one or more yield and/or performance concerns, the IC layout is modified. An approach for modifying an IC layout is to change a current layout of a circuit in the IC layout to another layout of the same circuit. Various design considerations, such as power, performance, area (PPA) may differ, sometimes hugely, from one layout (or layout solution) of a circuit to another layout of the same circuit.

Some embodiments provide multiple, different layouts (or layout solutions) of a circuit, e.g., in one or more cell libraries. In at least one embodiment, it is possible to find, among the provided multiple different layouts, a better layout than the current layout, depending on the particular PPA concern(s) of the current layout. Some embodiments provide an exhaustive search for all possible layouts of a circuit, for a given layout configuration. With all possible layouts of the circuit being identified for a given layout configuration, the likelihood of being able to find a better layout than the current layout is increased, making it possible to improve IC layouts in one or more embodiments.

In some embodiments, a method to find multiple, or all possible, layouts of a circuit comprises generating layout blocks, mapping some of the generated layout blocks with a floorplan of the circuit, and combining the mapped (or selected) layout blocks into a layout of the circuit. In at least one embodiment, the generated layout blocks satisfy predetermined design rules, and are sometimes referred to as design-rule-check (DRC)-free (i.e., the generated layout blocks do not cause a DRC violation when a DRC is executed). In at least one embodiment, the mapping of some of the generated layout blocks with the floorplan of the circuit is performed in a manner that satisfies predetermined layout-versus-schematic (LVS) rules, and is sometimes referred to as LVS-free. In at least one embodiment, the combining the mapped (or selected) layout blocks into a layout of the circuit is performed in a manner that is substantially DRC-free, and is sometimes referred to as DRC-less (i.e., less likely to cause a DRC violation when a DRC is executed). Because various stages in the process of generating layouts of a circuit are DRC-free, LVS-free or DRC-less, the likelihood that the generated layouts may cause IC layouts containing the generated layouts to fail a DRC or LVS check is low, thereby improving the efficiency of the IC design process, in one or more embodiments.

FIG.1Ais a block diagram of an IC device100A, in accordance with some embodiments.

InFIG.1, the IC device100A comprises, among other things, a macro102. In some embodiments, the macro102comprises one or more of a memory, a power grid, a cell or cells, an inverter, a latch, a buffer and/or any other type of circuit arrangement that may be represented digitally in a cell library. In some embodiments, the macro102is understood in the context of an analogy to the architectural hierarchy of modular programming in which subroutines/procedures are called by a main program (or by other subroutines) to carry out a given computational function. In this context, the IC device100A uses the macro102to perform one or more given functions. Accordingly, in this context and in terms of architectural hierarchy, the IC device100A is analogous to the main program and the macro102is analogous to subroutines/procedures. In some embodiments, the macro102is a soft macro. In some embodiments, the macro102is a hard macro. In some embodiments, the macro102is a soft macro which is described digitally in register-transfer level (RTL) code. In some embodiments, synthesis, placement and routing have yet to have been performed on the macro102such that the soft macro can be synthesized, placed and routed for a variety of process nodes. In some embodiments, the macro102is a hard macro which is described digitally in a binary file format (e.g., Graphic Database System II (GDSII) stream format), where the binary file format represents planar geometric shapes, text labels, other information and the like of one or more layout-diagrams of the macro102in hierarchical form. In some embodiments, synthesis, placement and routing have been performed on the macro102such that the hard macro is specific to a particular process node.

The macro102includes a circuit region104which comprises at least one layout for a circuit generated in accordance with some embodiments as described herein. In some embodiments, the circuit region104comprises a substrate having circuitry formed thereon, in a front-end-of-line (FEOL) fabrication. Furthermore, above and/or below the substrate, the circuit region104comprises various metal layers that are stacked over and/or under insulating layers in a Back End of Line (BEOL) fabrication. The BEOL provides a power network and/or routing for circuitry of the IC device100A, including the macro102and the circuit region104.

FIG.1Bis a functional flow chart of at least a portion of an IC design flow100B in accordance with some embodiments. In at least one embodiment, the design flow100B utilizes one or more electronic design automation (EDA) tools for testing a design of an IC before manufacturing the IC. The EDA tools, in some embodiments, are one or more sets of executable instructions for execution by a processor or controller or a programmed computer to perform the indicated functionality. In at least one embodiment, the IC design flow100B is performed by a design house of an IC manufacturing system discussed herein with respect toFIGS.9-10. In some embodiments, the IC design flow100B is performed to design an IC layout for the IC device100A.

At operation110, a design of an IC is provided by a circuit designer. In some embodiments, the design of the IC includes an IC schematic, i.e., an electrical diagram, of the IC. In some embodiments, the schematic is generated or provided in the form of a schematic netlist, such as a Simulation Program with Integrated Circuit Emphasis (SPICE) netlist. Other data formats for describing the design are usable in some embodiments.

At operation120, a pre-layout simulation is performed, e.g., by an EDA tool, on the design to determine whether the design meets a predetermined specification. If the design does not meet the predetermined specification, the IC is redesigned. In some embodiments, a SPICE simulation is performed on the SPICE netlist. Other simulation tools are usable, in place of or in addition to the SPICE simulation, in other embodiments.

At operation130, a layout (or layout diagram) of the IC is generated based on the design. The IC layout diagram comprises the physical positions of various circuit elements (or devices) of the IC as well as the physical positions of various nets and vias interconnecting the circuit elements. In some embodiments, the IC layout is generated in the form of a Graphic Design System (GDS) file by an EDA tool. Other data formats for describing the layout of the IC are within the scope of various embodiments.

In some embodiments, the IC layout diagram is generated at operation130by an EDA tool, such as an Automatic Placement and Routing (APR) tool. The APR tool receives the design of the IC in the form of a netlist as described herein, and performs a placement operation (or placement). For example, cells configured to provide pre-defined functions and having pre-designed layouts are stored in at least one library133. In some embodiments, the at least one library133is stored in at least one non-transitory computer-readable medium. The APR tool accesses various cells from the at least one library133, and places the cells in an abutting manner to generate an IC layout corresponding to the IC schematic. Example cells include, but are not limited to, inverters, adders, multipliers, logic gates, phase lock loops (PLLs), flip-flops, multiplexers, memory cells, combinations thereof, or the like. Example logic gates include, but are not limited to, an AND, OR, NAND, NOR, XOR, INV, AND-OR-Invert (AOI), OR-AND-Invert (OAI), MUX, Flip-flop, BUFF, Latch, delay, clock cells, or the like. In some embodiments, a cell includes one or more active or passive circuit elements. Examples of active elements include, but are not limited to, transistors and diodes. Examples of transistors include, but are not limited to, metal oxide semiconductor field effect transistors (MOSFET), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJT), high voltage transistors, high frequency transistors, p-channel and/or n-channel field effect transistors (PFETs/NFETs), FinFETs, planar MOS transistors with raised source/drain, or the like. Examples of passive elements include, but are not limited to, capacitors, inductors, fuses, and resistors.

The APR tool then performs a routing operation (or routing) to route various nets and vias interconnecting the placed circuit elements. Examples of nets include, but are not limited to, conductive pads, conductive patterns, and conductive redistribution layers, or the like. The routing operation is performed to ensure that the routed interconnections satisfy a set of constraints. After the routing operation, the APR tool outputs the IC layout diagram including the placed circuit elements and the routed nets and vias. Nets and vias are commonly referred to herein as routing features. The described APR tool is an example. Other arrangements are within the scope of various embodiments. For example, in one or more embodiments, one or more of the described operations are omitted.

At operation135, multiple layouts (or layout solutions) are generated for at least one circuit, as described herein with respect to various embodiments. The generated multiple layouts for the at least one circuit are stored in the at least one library133. In some embodiments, the at least one library133stores multiple layouts generated at operation135for each circuit (or cell) among a plurality of circuits (or cells). Accordingly, the at least one library133provides various layout solutions of each cell for a designer to choose from, thereby permitting the designer to pick a layout best suitable for the particular IC being designed, and/or to revise the IC being designed to meet various requirements, such as PPA, timing, frequency, combination performance (e.g., frequency and power), low leakage concern, circuit robustness, constrained metal routing usage, or the like. In the example configuration inFIG.1B, operation135is included as part of the design flow100B. In some embodiments, operation135is a separate process from the design flow100B, and provides multiple layouts of each cell in the at least one library133for use in the design flow100B.

At operation140, a layout-versus-schematic (LVS) check, is performed. The LVS check is performed to ensure that the generated IC layout corresponds to the design. Specifically, an LVS checking tool, i.e., an EDA tool, recognizes electrical components as well as connections therebetween from the patterns of the generated IC layout. The LVS checking tool then generates a layout netlist representing the recognized electrical components and connections. The layout netlist generated from the IC layout is compared, by the LVS checking tool, with the schematic netlist of the design. If the two netlists match within a matching tolerance, the LVS check is passed. Otherwise, correction is made to at least one of the IC layout or the design by returning the process to operation110and/or operation130. Other verification processes are usable in some embodiments. In some embodiments, one or more LVS rules used in, or similar to those used in, an LVS check are used in operation135, as described herein.

At operation150, a design rule check (DRC) is performed, e.g., by an EDA tool, on the GDS file representing the IC layout, to ensure that the IC layout satisfies certain manufacturing design rules, i.e., to ensure manufacturability of the IC. If one or more design rules is/are violated, correction is made to at least one of the IC layout or the design by returning the process to operation110and/or operation130. Examples of design rules include, but are not limited to, a width rule which specifies a minimum width of a pattern in the IC layout, a spacing rule which specifies a minimum spacing between adjacent patterns in the IC layout, an area rule which specifies a minimum area of a pattern in the IC layout, a metal-to-via spacing rule which specifies a minimum spacing between a metal pattern and an adjacent via, a metal-to-metal spacing rule, a polysilicon-to-oxide definition (PO-to-OD) spacing rule, a PO-to-PO spacing rule, or the like. Other verification processes are usable in some embodiments. In some embodiments, one or more design rules used in a DRC are used in operation135, as described herein.

At operation160, a resistance and capacitance (RC) extraction is performed, e.g., by an EDA tool, to determine parasitic parameters, e.g., parasitic resistance and parasitic capacitance, of interconnects in the IC layout for timing simulations in a subsequent operation. Other verification processes are usable in some embodiments.

At operation170, a post-layout simulation is performed by a simulation tool, i.e., an EDA tool, to determine, taking the extracted parasitic parameters into account, whether the IC layout meets a predetermined specification. If the simulation indicates that the IC layout does not meet the predetermined specification, e.g., if the parasitic parameters cause undesirable delays, correction is made to at least one of the IC layout or the design by returning the process to operation110and/or operation130. Otherwise, the IC layout is passed to manufacture or additional verification processes.

In some embodiments, one or more evaluations, checks and/or simulations indicate one or more yield and/or performance concerns, and a determination is made to modify the IC layout, e.g., by returning the process to operation130. An approach for modifying the IC layout is to replace a current layout of a circuit in the IC layout with another layout of the same circuit obtained from the at least one library133. Because multiple layouts of the circuit are available from the at least one library133, the likelihood of being able to find a better layout than the current layout is increased, which makes it possible to successfully modify the IC layout to address one or more concerns in an efficient manner, in accordance with some embodiments. The modified IC layout is subjected to one or more checks and/or simulations, for example, as described with respect to operations140-170. When the modified IC layout does not meet one or more requirements at operations140-170, the process is returned to operation130for further layout modifications, with subsequent checks and verifications as described herein. In some embodiments, the IC layout before modification and/or the modified IC layout and/or the final IC layout for manufacture are stored in a non-transitory computer-readable medium.

In some embodiments, one or more of the described operations are omitted. In an example, one or more of the pre-layout simulation in operation120, the RC extraction in operation160, and the post-layout simulation in operation170is/are omitted, in one or more embodiments. Other arrangements are within the scopes of various embodiments. For simplicity, various operations and/or determinations are described herein as being performed by an APR tool. However, in at least one embodiment, one or more of the described operations and/or determinations are performed outside an APR tool, e.g., by one or more further automated systems, one or more processors, and/or one or more computer systems.

FIG.2is a schematic circuit diagram of a circuit200, in accordance with some embodiments. In at least one embodiment, the circuit200corresponds to a portion of the region104inFIG.1Aand/or corresponds to a circuit for which multiple layouts are generated in operation135inFIG.1B. In the example configuration inFIG.2, the circuit200comprises an AND-OR-Invert (AOI) logic with two 2-input AND gates corresponding to a cell sometimes referred to as an AOI22D1 cell. Other example circuits or cells included in the region104and/or subjected to operation135include, but are not limited to, AND, OR, NAND, NOR, XOR, INV, OR-AND-Invert (OAI), MUX, Flip-flop, BUFF, Latch, delay, clock, memory, combinations thereof, or the like.

Gates of the transistors PA1, NA1are electrically coupled to the input A1. Gates of the transistors PA2, NA2are electrically coupled to the input A2. Gates of the transistors PB1, NB1are electrically coupled to the input B1. Gates of the transistors PB2, NB2are electrically coupled to the input B2.

Sources of the transistors PB1, PB2are electrically coupled to a first node (or rail) of a first power supply voltage. The first node (or rail) and the first power supply voltage are commonly referred to herein as VDD. Drains of the transistors PB1, PB2are electrically coupled to a net con. As a result, the transistors PB1, PB2are electrically coupled in parallel between VDD and the net con. Sources of the transistors PA1, PA2are electrically coupled to the net con. Drains of the transistors PA1, PA2are electrically coupled to the output ZN. As a result, the transistors PA1, PA2are electrically coupled in parallel between the net con and the output ZN. The parallel coupled transistors PB1, PB2and the parallel coupled transistors PA1, PA2are electrically coupled in series at the net con.

Sources of the transistors NA2, NB2are electrically coupled to a second node (or rail) of a second power supply voltage. The second node (or rail) and the second power supply voltage are commonly referred to herein as VSS (or ground). A drain of the transistor NA2is electrically coupled to a source of the transistor NA1at a net n2. As a result, the transistors NA1, NA2are electrically coupled in series. A drain of the transistor NB2is electrically coupled to a source of the transistor NB1at a net n1. As a result, the transistors NB1, NB2are electrically coupled in series. Drains of the transistors NA1, NB1are electrically coupled to the output ZN. As a result, the serially coupled transistors NA1, NA2and the serially coupled transistors NB1, NB2are coupled in parallel between the output ZN and VSS. The described VDD, VSS, A1, A2, B1, B2, ZN, net n1, net n2, and net con are examples of various nets in a floorplan of a circuit, as described herein.

FIG.3Ais a schematic view of a layout300A which includes several layers of a layout300of the circuit200, in accordance with some embodiments. Corresponding elements of the circuit200and the layout300are designated by the same reference numerals.

As shown inFIG.3A, the layout300comprises a plurality of active regions OD-1, OD-2. Active regions are sometimes referred to as oxide-definition (OD) regions or source/drain regions, and are schematically illustrated in the drawings with the label “OD.” The active regions OD-1, OD-2are elongated along a first axis, e.g., the X-axis. The active regions OD-1, OD-2include P-type dopants and/or N-type dopants to form one or more circuit elements or devices. An active region configured to form one or more PMOS devices is sometimes referred to as “PMOS active region,” and an active region configured to form one or more NMOS devices is sometimes referred to as “NMOS active region.” In the example configuration described with respect toFIG.3A, the active region OD-1comprises a PMOS active region, and the active region OD-2comprise an NMOS active region. Other configurations are within the scopes of various embodiments.

The layout300further comprises a plurality of gate regions321,322,323,324,325,326over the active regions OD-1, OD-2. The gate regions321,322,323,324,325,326are elongated along a second axis, e.g., the Y-axis, which is transverse to the X-axis. The gate regions321,322,323,324,325,326are arranged along the X axis at a regular pitch designated at CPP (contacted poly pitch) inFIG.3A. CPP is a center-to-center distance along the X axis between two immediately adjacent gate regions. Two gate regions are considered immediately adjacent where there are no other gate regions therebetween. A width (or cell pitch) of the layout300along the X axis is 5 CPP in the example configuration inFIG.3A. The gate regions321,322,323,324,325,326, in a manufactured IC device corresponding to the layout300, comprise a conductive material, such as, polysilicon, which is sometimes referred to as “poly.” The gate regions321,322,323,324,325,326are schematically illustrated in the drawings with the label “PO.” Other conductive materials for the gate regions, such as metals, are within the scope of various embodiments. In the example configuration inFIG.3A, the gate regions322,323,324,325are functional gate regions which, together with the active regions OD-1, OD-2, configure a plurality of transistors as described herein. In some embodiments, the gate regions321,326are non-functional, or dummy, gate regions. Dummy gate regions are not configured to form transistors together with underlying active regions, and/or one or more transistors formed by dummy gate regions together with the underlying active regions are not electrically coupled to other circuitry. In at least one embodiment, non-functional, or dummy, gate regions include dielectric material in a manufactured IC device.

In the example configuration inFIG.3A, each of the gate regions321,322,323,324,325,326extends continuously across the active regions OD-1, OD-2. In some embodiments, a gate region is cut, or divided, into several portions each over a corresponding active region. For example, in a layout for another circuit, the gate region322is cut, e.g., by a cut-poly (CPO) region described herein, into two gate region portions each over a corresponding one of the active regions OD-1, OD-2. For another example, in a layout for a further circuit with more than two active regions, a gate region is cut by multiple CPO regions into more than two portions over the more than two active regions.

The layout300further comprises a plurality of transistors configured by the gate regions321,322,323,324,325,326and the active regions OD-1, OD-2. For example, the transistors PB2, PB1, PA1, PA2are configured by the PMOS active region OD-1together with the corresponding gate regions322,323,324,325. The transistors NB2, NB1, NA1, NA2are configured by the NMOS active region OD-2together with the corresponding gate regions322,323,324,325. The gate region322corresponds to the gates of the transistors PB2, NB2, and also corresponds to the input B2of the circuit200. The gate region323corresponds to the gates of the transistors PB1, NB1, and also corresponds to the input B1of the circuit200. The gate region324corresponds to the gates of the transistors PA1, NA1, and also corresponds to the input A1of the circuit200. The gate region325corresponds to the gates of the transistors PA2, NA2, and also corresponds to the input A2of the circuit200. Source/drains of the transistors PB2, PB1, PA1, PA2correspond to portions of the active region OD-1on opposite sides of the corresponding gate regions322,323,324,325. Source/drains of the transistors NB2, NB1, NA1, NA2correspond to portions of the active region OD-2on opposite sides of the corresponding gate regions322,323,324,325.

The layout300further comprises source/drain contact regions over the corresponding source/drains in the active regions OD-1, OD-2. Source/drain contact regions are sometimes referred to as metal-to-device (MD) regions, and are schematically illustrated in the drawings with the label “MD.” In a manufactured IC device corresponding to the layout300, an MD region includes a conductive material, e.g., a metal, formed over a corresponding source/drain in the corresponding active region to define an electrical connection from one or more devices formed in the active region to other internal circuitry of the IC device or to outside circuitry. In the example configuration inFIG.3A, MD regions331,332,333,334,335are over the active region OD-1, configured to define electrical contacts with the corresponding source/drains of the transistors PB2, PB1, PA1, PA2, and arranged alternatingly with the gate regions321,322,323,324,325,326along the X-axis. A pitch, i.e., a center-to-center distance along the X axis, between immediately adjacent MD regions is the same as the pitch CPP between immediately adjacent gate regions. A center-to-center distance between a gate region (e.g.,323) and an immediately adjacent MD region (e.g.,338) is 0.5 CPP. MD regions336,337,338,339,340are over the active region OD-2, configured to define electrical contacts with the corresponding source/drains of the transistors NB2, NB1, NA1, NA2, and arranged alternatingly with the gate regions321,322,323,324,325,326along the X-axis. Other configurations are within the scopes of various embodiments.

The MD regions331,333,335correspond to the net con in the circuit200, and are to be electrically coupled together by one or more metal layers as described herein. The MD region332corresponds to VDD in the circuit200. The MD regions334,338correspond to the output ZN in the circuit200, and are to be electrically coupled together by one or more metal layers as described herein. The MD regions336,340correspond to VSS in the circuit200, and are to be electrically coupled together by one or more metal layers as described herein. The MD region337corresponds to the net n1in the circuit200. The MD region339corresponds to the net n2in the circuit200.

The MD regions331and336are aligned with each other along the Y-axis, and are sometimes considered as two portions of an MD region that extends continuously across the active regions OD-1, OD-2, but is cut, or divided, by a cut-MD (CMD) region described herein, into the MD regions331,336correspondingly over the active regions OD-1, OD-2. Similarly, each of the pairs of the MD regions332and337,333and338,334and339,335and340is sometimes considered as two portions of an MD region that extends continuously across the active regions OD-1, OD-2, but is cut by a corresponding cut-MD (CMD) region. Other MD region configurations are within the scopes of various embodiments. For example, in a layout for another circuit, the MD regions331and336are contiguous to each other, and configure an MD region extending continuously over the active regions OD-1, OD-2. For another example, in a layout for a further circuit with more than two active regions, an MD region is cut by multiple CMD regions into mor than two portions over the more than two active regions.

The layout300further comprises a boundary (or cell boundary)360which comprises edges361,362,363,364. The edges361,362are elongated along the X axis, and the edges363,364are elongated along the Y axis. The edges361,362,363,364are connected together to form the closed boundary360. In a place-and-route operation (also referred to as “automated placement and routing (APR)”), cells are placed in an IC layout diagram in abutment with each other at their respective boundaries. The boundary360is sometimes referred to as “place-and-route boundary” and is schematically illustrated in the drawings with the label “prBoundary.” The rectangular shape of the boundary360is an example. Other boundary shapes for various cells are within the scope of various embodiments. The edges361,362coincide with centerlines of corresponding M0conductive patterns (not shown inFIG.3A) as described herein. The edges363,364coincide with centerlines of dummy or non-functional gate regions321,326. Between the edges361,362and along the Y axis, the layout300contains one PMOS active region, i.e., OD-1, and one NMOS active region, i.e., OD-2, and is considered to have a height corresponding to one cell height h. Other configurations are within the scopes of various embodiments. For example, in one or more embodiments, another cell or circuit (not shown) containing along the Y axis two PMOS active regions and two NMOS active regions is considered to have a height corresponding to two cell heights, or double cell height,2h. Cells or circuits with greater cell heights, e.g.,3h,4h, or the like, are within the scopes of various embodiments.

The layout300A inFIG.3Ashows a physical arrangement of a plurality of nets associated with a plurality of alternating gate blocks and source/drain blocks in a floorplan of the circuit200. The floorplan inFIG.3Acomprises a plurality of blocks371-379, including gate blocks372,374,376,378, and source/drain blocks371,373,375,377,379. Each gate block comprises gate regions aligned with each other along the Y-axis. For example, the gate block372comprises the gate regions of the transistors PB2and NB2which are portions of the gate region322and are aligned with each other along the Y-axis. Each source/drain block comprises MD regions aligned with each other along the Y-axis. For example, the source/drain block371comprises the MD regions331,336which are aligned with each other along the Y-axis. Each of the blocks371-379is identified by an X position of the block, in the floorplan, along the X-axis. For example, the source/drain block371is the first block (from the left) in the floorplan, and is identified by X=1. The gate block372is the second block in the floorplan, and is identified by X=2, or the like. Other manners for identifying the blocks in a floorplan are within the scopes of various embodiments.

As described herein, the nets con, B2, VDD, B1, con, A1, ZN, A2, con correspond to alternating MD regions and gate regions331,322,332,323,333,324,334,325,335over the PMOS active region OD1. The nets VSS, B2, n1, B1, ZN, A1, n2, A2, VSS correspond to alternating MD regions and gate regions336,322,337,323,338,324,339,325,340over the NMOS active region OD2. As a result, the source/drain block371which comprises the MD regions331,336is associated with the corresponding nets con, VSS. Similarly, the gate block372is associated with the corresponding nets B2, B2. In some embodiments, it is possible that a block in a floorplan is associated with fewer than two nets, e.g., with one net or zero net. For example, when a gate region or an MD region is unused or non-functional, there is no net associated with the corresponding gate block or source/drain block. In some embodiments, it is possible that a block in a floorplan is associated with more than two nets. For example, in one or more embodiments, another cell or circuit (not shown) contains along the Y axis four active regions, e.g., two PMOS active regions and two NMOS active regions. In such a situation, a block of a floorplan of the cell or circuit is associated with four nets corresponding to the four active regions. Other configurations are within the scopes of various embodiments.

FIG.3Bis a schematic diagram of a floorplan300B of the circuit200, in accordance with some embodiments. The schematic diagram of the floorplan300B inFIG.3Bcorresponds to the physical arrangement of nets and associated blocks in the floorplan described with respect toFIG.3A.

The floorplan300B inFIG.3Bis schematically shown as a table having columns371-379corresponding to the blocks371-379described with respect toFIG.3A, and rows380-382and. The row380indicates the X positions of the blocks371-379, the row381indicates nets over the PMOS active region OD1and associated with the blocks371-379, and the row382indicates nets over the NMOS active region OD2and associated with the blocks371-379. For simplicity, the floorplan300B is referred to in the subsequent description of various examples. Other manners for presenting a floorplan are within the scopes of various embodiments.

FIG.3Cis a schematic view of a layout300C which includes further layers of the layout300of the circuit200, in accordance with some embodiments. For simplicity, the active regions OD-1, OD-2are schematically indicated by curly brackets (or braces) and the boundary360is omitted inFIG.3C. In at least one embodiment, the layout300C inFIG.3Cis one among multiple layouts generated at operation135in accordance with the floorplan300B for the circuit200, and stored in the at least one library133on a non-transitory computer-readable medium. In some embodiments, the layout inFIG.3Cis subsequently read from the at least one library133, and placed at operation130into an IC layout of an actual IC to be designed and/or manufactured.

As shown inFIG.3C, the layout300further comprises cut-MD regions CMD-1, CMD-2, CMD-3, CMD-4, CMD-5. In some embodiments, a cut-MD region is a mask, and corresponds to where an otherwise continuous MD region is disconnected. For example, the cut-MD region CMD-1cuts, or divides an otherwise continuous MD region into the MD regions331and336. Each cut-MD region has a pair of edges along the Y-axis, and correspondingly coinciding with the centerlines of a pair of adjacent gate regions. The size (width) of the cut-MD region along the X-axis is 1 CPP. For example, inFIG.3C, left and right edges of the cut-MD region CMD-3extend along the Y-axis and correspondingly coincide with the centerlines of the adjacent gate regions323,324. Other cut-MD region configurations are within the scopes of various embodiments. In some embodiments as described herein, a layout of another circuit comprises one or more cut-PO regions for cutting, or dividing, an otherwise continuous gate region into several gate region portions. A cut-PO region (e.g., a mask) corresponds to where the gate region is disconnected.

The layout300further comprises vias over the corresponding gate regions or MD regions. A via over a gate region is sometimes referred to as via-to-gate (VG) via. A via over an MD region is sometimes referred to as via-to-device (VD) via. VG and VD vias are schematically illustrated in the drawings with corresponding labels “VG” and “VD.” In the example configuration inFIG.3C, vias VG-1, VG-2, VG-3, VG-4are over the corresponding gate regions322,323,324,325. VD vias inFIG.3Cinclude VD vias for signals, and VD vias for power supply. The VD vias for signals include vias VD-1, VD-2, VD-3, VD-4, VD-5which are over the corresponding MD regions331,333,335,334,338associated with signal nets con and ZN. The VD vias for power supply are schematically illustrated in the drawings with a label “VD2,” and include vias VD2-1, VD2-2, VD2-3which are over the corresponding MD regions332,336,340associated with power supply nets VDD and VSS. In a manufactured IC device corresponding to the layout300, VD vias and VG vias include a conductive material, e.g., a metal. Other vias configurations are within the scopes of various embodiments.

The VD vias and VG vias are configured to form electrical connections from the corresponding MD regions and gate regions to conductive patterns in an overlying metal layer, i.e., a metal-zero (M0) layer. Conductive patterns in the M0layer are referred to herein as M0conductive patterns. Example M0conductive patterns of the layout300are described herein with respect toFIG.3D. M0conductive patterns are formed along one or more tracks M0_VSS, M0_1, M0_2, M0_3, M0_4, M0_5, M0_VDD extending along the X-axis, to ensure that predetermined design rules are satisfied. The tracks M0_VSS, M0_1, M0_2, M0_3, M0_4, M0_5, M0_VDD, or the like are also referred to herein as M0tracks. The tracks M0_1, M0_2, M0_3, M0_4, M0_5correspond to M0conductive patterns configured to carry signals to, from or within the circuit200. The tracks M0_1, M0_2, M0_3, M0_4, M0_5are spaced from each other along the Y-axis, by a distance d1. The tracks M0_VSS, M0_VDD correspond to M0conductive patterns configured to provide power supply to the circuit200. The track M0_VSS is spaced along the Y-axis from the adjacent track M0_1by a distance d2, and the track M0_VDD is spaced along the Y-axis from the adjacent track M0_5by the distance d2. In the example configuration inFIG.3C, d1<d2. Other configurations are within the scopes of various embodiments. The described number of five M0tracks for signals and two M0tracks for power supply is example. Other configurations are within the scopes of various embodiments.

As described with respect toFIG.3D, M0conductive patterns are arranged along the M0tracks. To form electrical connections with overlying M0conductive patterns, the VD vias and VG vias are also arranged along the M0tracks. In the example configuration inFIG.3C, the via VD2-1is arranged along the track M0_VDD to form an electrical connection for receiving VDD, the vias VD-1, VD-2, VD-3are arranged along the track M0_5, the via VD-4is arranged along the track M0_4, the via VG-2is arranged along the track M0_3, the vias VD-5, VG-4are arranged along the track M0_2, the vias VG-1, VG-3are arranged along the track M0_1, and the vias VD2-2, VD2-3are arranged along the track M0_VSS to form an electrical connection for receiving VSS. A VD via is not arrangeable where there is a cut-MD region, i.e., where a underlying MD region does not exist. Likewise, a VG via is not arrangeable where there is a cut-PO region, i.e., where a underlying gate region does not exist. These are example rules to be observed and followed in designing or generating IC layouts.

The presence of multiple VD and/or VG vias associated with different nets along the same M0track requires multiple corresponding M0conductive patterns along the same M0track. This is achieved by a cut-M0(CM0) region, e.g., a mask, which corresponds to where an otherwise continuous M0conductive pattern is disconnected, or divided into two separated M0conductive patterns. For example, a cut-M0region CM0A-2is arranged between the via VD-5(associated with the net ZN) and via VG-4(associated with the net A2) along the same track M0_2, to configure two separated overlying M0conductive patterns, as described with respect toFIG.3D. For another example, a cut-M0region CM0B-1is arranged between the via VG-1(associated with the net B2) and via VG-3(associated with the net A1) along the same track M0_1, to configure two separated overlying M0conductive patterns, as described with respect toFIG.3D. However, when multiple vias associated with the same net are arranged along the same M0track, it is possible to form an M0conductive pattern over and connecting the multiple vias, and a cut-M0region is not required. For example, although the vias VD-1, VD-2, VD-3are arranged along the same track M0_5, no cut-M0region is required because the vias VD-1, VD-2, VD-3are all associated with the net con. For another example, although the vias VD2-2, VD2-3are arranged along the same track M0_VSS, no cut-M0region is required because the vias VD2-2, VD2-3are all associated with the net VSS. These are further example rules to be observed and followed in designing or generating IC layouts.

FIG.3Dis a schematic view of a layout300D which includes further layers of the layout300of the circuit200, in accordance with some embodiments. For simplicity, inFIG.3D, the active regions OD-1, OD-2are schematically indicated by curly brackets (or braces), the gate regions321-326are schematically indicated by the corresponding centerlines, and the boundary360, the cut-MD regions CMD-1, CMD-2, CMD-3, CMD-4, CMD-5, and the CM0regions CM0A-2, CM0B-1are omitted.

An IC layout comprising the layout300comprises a plurality of metal layers and via layers sequentially and alternatingly arranged over the VD and VG vias. The lowermost metal layer immediately over the VD and VG vias is the M0layer, i.e., metal-zero (M0) layer. The M0layer is the lowermost metal layer over, or the closest metal layer to, the active regions OD-1, OD-2. A next metal layer immediately over the M0layer is the M1layer, a next metal layer immediately over the M1layer is the M2layer, or the like. A via layer Vn is arranged between and electrically couple the Mn layer and the Mn+1 layer, where n is an integer form zero and up. For example, a via-zero (V0) layer is the lowermost via layer which is arranged between and electrically couple the M0layer and the M1layer. Other via layers are V1, V2, or the like.

In the example configuration inFIG.3D, the layout300additionally comprises the M0layer, V0layer and M1layer. An IC layout containing the layout300includes higher metal layers and/or via layers, which are omitted inFIG.3D. In some embodiments, layouts of various cells or circuits include different sets of metal layers and via layers. For example, layouts of some cells include no metal layers. Layouts of other cells include no metal layers and no via layers higher than the M0layer. Layouts of further cells include at least one metal layer and/or at least via layer higher than the M1layer. Other configurations are within the scopes of various embodiments.

In the example configuration inFIG.3D, the M0conductive patterns in the layout300are separated into several masks to meet one or more design and/or manufacturing requirements. For example, the layout300further comprises conductive patterns M0A-1, M0A-2, M0A-3, M0A-4, M0A-5corresponding to one M0mask (referred to herein as the M0A mask), and conductive patterns M0B-1, M0B-2, M0B-3, M0B-4corresponding to another M0mask (referred to herein as the M0B mask). The M0A conductive patterns and M0B conductive patterns are arranged alternatingly along the Y-axis. For example, the conductive pattern M0B-1is arranged between the conductive pattern M0A-1on one side and the conductive patterns M0A-2on the other side. The M0A conductive patterns are arranged along the tracks M0_VSS, M0_2, M0_4, M0_VDD. The M0B conductive patterns are arranged along the tracks M0_1, M0_3, M0_5. For example, centerlines of the M0A conductive patterns coincide with the corresponding tracks M0_VSS, M0_2, M0_4, M0_VDD, and centerlines of the M0B conductive patterns coincide with the corresponding tracks M0_1, M0_3, M0_5. The conductive patterns M0A-3, M0A-4are arranged along the same track M0_2, and are separated from each other by a spacing corresponding to the cut-M0region CM0A-2. The cut-M0region CM0A-2belongs to a cut-M0mask CM0A configured to cut M0A conductive patterns. The conductive patterns M0B-3, M0B-4are arranged along the same track M0_1, and are separated from each other by a spacing corresponding to the cut-M0region CM0B-1. The cut-M0region CM0B-1belongs to a further cut-M0mask CM0B configured to cut M0B conductive patterns. In some embodiments, all M0conductive patterns in the M0layer belong to the same mask, and all cut-M0regions belong to the same cut-M0mask. In some embodiments, M0conductive patterns in the M0layer belong to more than two masks, and cut-M0regions correspondingly belong to more than two cut-M0masks.

The conductive pattern M0A-1is configured as a VDD power rail and is over the via VD2-1to be electrically coupled to the MD region332. The conductive pattern M0B-1is over the vias VD-1, VD-2, VD-3, and electrically couples together the MD regions331,333,335corresponding the net con of the circuit200. The conductive pattern M0A-2is over the via VD-4, and is electrically coupled to the MD regions334corresponding the net ZN of the circuit200. The conductive pattern M0B-2is over the via VG-2, and is electrically coupled to the gate region323. The conductive pattern M0A-3is over the via VD-5, and is electrically coupled to the MD regions338corresponding the net ZN of the circuit200. The conductive pattern M0A-4is over the VG-4, and is electrically coupled to the gate region325. The conductive pattern M0B-3is over the VG-1, and is electrically coupled to the gate region322. The conductive pattern M0B-4is over the VG-3, and is electrically coupled to the gate region324. The conductive pattern M0A-5is configured as a VSS power rail and is over the vias VD2-2, VD2-3to be electrically coupled to the MD regions336,340.

The layout300further comprises, in the V0layer over the M0layer, vias V0-1, V0-2, V0-3, V0-4, V0-5, V0-6over the corresponding conductive patterns M0A-2, M0B-2, M0A-3, M0A-4, M0B-3, M0B-4, of the M0layer. In the example configuration inFIG.3D, the vias V0-2, V0-6correspondingly overlap the vias VG-2, VG-3. Other configurations are within the scopes of various embodiments.

The layout300further comprises, in the M1layer over the V0layer, M1conductive patterns separated into several masks to meet one or more design and/or manufacturing requirements. For example, the layout300further comprises conductive patterns M1A-1, MIA-2, M1A-3, M1A-4corresponding to one M1mask (referred to herein as the MIA mask), and a conductive pattern M1B-1corresponding to another M1mask (referred to herein as the M1B mask). The conductive patterns M1A-1, M1A-2, M1A-3, M1A-4, M1B-1correspond to inputs B2, B1, A1, A2and output ZN of the layout300. Other configurations are within the scopes of various embodiments. For example, in some embodiments, a cell or circuit comprises at least one input or output in an upper metal layer other than the M1layer, e.g., in the M2layer, or the M3layer, or a higher metal layer.

The conductive pattern M1A-1is over the via V0-5. As a result, the gate region322is electrically coupled to the conductive pattern M1A-1, through the via VG-1, the conductive pattern M0B-3and the via V0-5, to receive an input signal corresponding to the input B2. The conductive pattern M1A-2is over the via V0-2. As a result, the gate region323is electrically coupled to the conductive pattern M1A-2, through the via VG-2, the conductive pattern M0B-2and the via V0-2, to receive an input signal corresponding to the input B1. The conductive pattern M1A-3is over the via V0-6. As a result, the gate region324is electrically coupled to the conductive pattern M1A-3, through the via VG-3, the conductive pattern M0B-4and the via V0-4, to receive an input signal corresponding to the input A1. The conductive pattern M1A-4is over the via V0-4. As a result, the gate region325is electrically coupled to the conductive pattern M1A-4, through the via VG-4, the conductive pattern M0A-4and the via V0-4, to receive an input signal corresponding to the input A2. The conductive pattern M1B-1is over the vias V0-1, V0-3. As a result, the MD regions334,338are electrically coupled to each other and to the conductive pattern M1B-1, through the corresponding vias VD-4, VD-5, the corresponding conductive patterns M0A-2, M0A-3, and the corresponding vias V0-1, V0-3, to output an output signal corresponding to the output ZN. The conductive patterns M1A-1, M1A-2, M1A-3, M1A-4, M1B-1provide pin-outs corresponding to the inputs B2, B1, A1, A2and the output ZN for electrical connections of the layout300to the other circuitry of the IC device or to external circuitry.

In at least one embodiment, the layout300D is one among multiple layouts generated at operation135in accordance with the floorplan300B for the circuit200, and stored in the at least one library133on a non-transitory computer-readable medium. In some embodiments, the layout300D is subsequently read from the at least one library133, and placed at operation130into an IC layout of an actual IC to be designed and/or manufactured.

In at least one embodiment, the layout300D is generated, at operation130, by reading the layout300C from the at least one library133, placing the layout300C into an IC layout of an actual IC to be designed and/or manufactured, and performing routing to create the M0conductive patterns, V0vias, and M1conductive patterns described with respect toFIG.3D, to connect the nets in the layout300C into a circuit corresponding to the circuit200.

FIG.3Eis a schematic cross-sectional view of an IC device300E, in accordance with some embodiments. The IC device300E comprises a circuit region corresponding to the layout300. A cross-section line along which the cross-sectional view ofFIG.3Eis taken corresponds to the track M0_1inFIG.3D, and over the length of the conductive pattern M0B-3along the X-axis. Components inFIG.3Ehaving corresponding components inFIGS.3A,3C,3Dare designated by the same reference numerals.

As shown inFIG.3E, the IC device300E comprises a substrate385over which the circuit region corresponding to the layout300is formed. The substrate385has a thickness direction along a Z-axis perpendicular to both the X-axis and Y-axis. The substrate385comprises, in at least one embodiment, silicon, silicon germanium (SiGe), gallium arsenic, or other suitable semiconductor or dielectric materials. In some embodiments, the substrate385is a P-doped substrate. In some embodiments, the substrate385is an N-doped substrate. In some embodiments, the substrate385is a rigid crystalline material other than a semiconductor material (e.g., diamond, sapphire, aluminum oxide (Al2O3), or the like) on which an IC is manufactured.

N-type and P-type dopants are added to the substrate385to form corresponding N wells in an NMOS active region corresponding to the active region OD-2, and a P well in a PMOS active region corresponding to the active region OD-1. In some embodiments, isolation structures are formed between adjacent P wells and N wells. The N well defines sources/drains386,387of a transistor NB2. A gate322of the transistor NB2comprises a stack of gate dielectric layers388,389and a gate electrode322. In at least one embodiment, the transistor NB2comprises a gate dielectric layer instead of multiple gate dielectrics. Example materials of the gate dielectric layer or layers include HfO2, ZrO2, or the like. Example materials of the gate electrode322include polysilicon, metal, or the like.

The IC device300E further comprises MD regions336,337for electrically coupling the source/drains386,387of the transistor NB2to other circuit elements in the circuitry of the IC device300E.

The IC device300E further comprises an interconnect structure390which is over the VD and VG vias, and comprises a plurality of metal layers M0, M1, . . . and a plurality of via layers V0, V1, . . . arranged alternatingly in the thickness direction of the substrate385, i.e., along the Z axis. The interconnect structure390further comprises various interlayer dielectric (ILD) layers (not shown) in which the metal layers and via layers are embedded. The metal layers and via layers of the interconnect structure390are configured to electrically couple various elements or circuits of the IC device300E with each other, and with external circuitry. For simplicity, metal layers and via layers above the M1layer are omitted inFIG.3E. As described with respect toFIGS.3A,3C,3D, a gate322of the transistor NB2is coupled by a via VG-1to an M0conductive pattern M0B-3, which is coupled by a via V0-5to an M1conductive pattern M1A-1.

As described herein, the layout300C is one of many layouts corresponding to the floorplan300B. In some embodiments, multiple layouts corresponding to a floorplan of a circuit are generated and stored in at least one library. The multiple layouts provide various options of each cell for a designer to choose from, thereby permitting the designer to pick a layout best suitable for the particular IC being designed, and/or to revise the IC being designed to meet various requirements, such as PPA, timing, or the like. In some embodiments, a method to find multiple, or all possible, layouts of a circuit comprises generating layout blocks, mapping some of the generated layout blocks with a floorplan of the circuit, and combining the mapped (or selected) layout blocks into a layout of the circuit. Examples of generating layout blocks are described with respect to one or more ofFIGS.4A-4F. Examples of mapping some of the generated layout blocks with a floorplan of the circuit are described with respect to one or more ofFIGS.5A-5B. Examples of combining the mapped (or selected) layout blocks into a layout of the circuit are described with respect to one or more ofFIGS.5C-5D,6,7A-7D. In some embodiments, the method, including generating layout blocks, mapping some of the generated layout blocks with a floorplan of the circuit, and combining the mapped (or selected) layout blocks into a layout of the circuit, is performed, fully or at least partially, by at least one processor as described herein.

FIGS.4A,4Bare schematic views showing various block options associated with corresponding layout features, in accordance with some embodiments. InFIG.4A, the layout feature is a gate region, and the block options associated with the layout feature are gate block options collectively referred to as400A. InFIG.4B, the layout feature is a source/drain contact region (or MD region), and the block options associated with the layout feature are source/drain block options collectively referred to as400B. Other layout features are within the scopes of various embodiments, for example, as described with respect toFIGS.4D,4E.

InFIG.4A, the gate block options400A include all possible gate block options corresponding to a given layout configuration. A layout configuration includes one or more factors that affect the numbers and/or configurations of the available block options. An example factor includes the number of M0tracks in the cell or circuit for which multiple layouts are to be generated. A higher number of M0tracks leads to a higher number of locations where various vias (e.g., VD and/or VG vias) are arrangeable in the layout, which, in turn, leads to a higher number of available block options and/or higher complexity of each block option. A further example factor includes the number of active regions (or cell height) in the cell or circuit for which multiple layouts are to be generated. A higher number (e.g., four) of active regions leads to a higher number of locations where various vias (e.g., VD and/or VG vias) and/or various cut regions (e.g., cut-MD regions, cut-PO regions, cut-M0regions or the like) are arrangeable in the layout, which, in turn, leads to a higher number of available block options and/or higher complexity of each block option. Other factors in a layout configuration are within the scopes of various embodiments. Various examples discussed herein are for a layout configuration including five M0tracks for signals, two M0tracks for power supply, and two active regions (one PMOS active region and one NMOS active region), as described with respect toFIGS.3A,3C,3D. Other layout configurations are within the scopes of various embodiments.

The gate block options (referred to herein as PO block options) inFIG.4Ainclude 21 PO block options PO0-PO20. Each of the PO block options400A is a gate region (e.g., the PO block option P014), or a combination (e.g., the PO block options PO0-PO13, PO13-PO20) of a gate region with at least one of (i) at least one first cut region configured to cut or disable a portion of the gate region, or (ii) at least one first via over the gate region.

For example, the PO block option P014is a gate region401that extends continuously over a PMOS active region and an NMOS active region (not shown), similarly to the gate regions322-324described with respect toFIG.3A. There is no cut region or via on, or associated with, the gate region401in the PO block option PO14.

Each of the PO block options PO0-PO3is a combination of a gate region, a cut-PO region, and one VG via. For example, the PO block option PO0is a combination of the gate region401(not numbered), with a cut-PO region402, and a VG via403. The gate region401in the PO block option PO0is divided by the cut-PO region402into gate region portions404,405correspondingly over the PMOS active region and NMOS active region. The cut-PO region402is arranged along the track M0_3in the middle of the cell along the Y-axis. A VG via may not overlap a cut-PO region where a gate region does not exist. Thus, a VG via is arrangeable on one of the other M0tracks for signals, i.e., one of the tracks M0_1, M0_2, M0_4, M0_5. The PO block options PO0includes the VG via403on the track M0_1. The PO block options PG1-PG3are similar to the PO block option PO0, except for the position of the VG via which is correspondingly arranged on the tracks M0_2, M0_4, M0_5.

Each of the PO block options PG4-PO7is a combination of a gate region, a cut-PO region, and two VG vias correspondingly on two gate region portions divided by the cut-PO region. For example, the PO block option PG4is similar to the PO block option PO0with the addition of a second VG via406. The positions of the two VG vias are different among the PO block options PG4-PO7.

Each of the PO block options PG8-PO13is a combination of a gate region, a cut-PO region dividing the gate region into two gate region portions, and a further cut region CPODR that disables one of the gate region portions. A disabled gate region portion may not have a VG via thereon. For example, the PO block option PG8is similar to the PO block option PO0, except that the PO block option PG8additionally includes a cut region CPODR407that disables the gate region portion404. The PO block options PG9, PO11, PO12are correspondingly similar to the PO block options PO1, PG2, PG3, except for an additional cut region CPODR that disables one of the gate region portions. While each of the PO block options PG8, PG9, PO11, PO12includes a VG via, each of the PO block options PO10, P13is without a VG via.

Each of the PO block options PG15-PO19is a combination of a gate region and a VG via. The VG via is arranged correspondingly on the tracks M0_1, M0_2, M0_3, M0_4, M0_5in the PO block options PG15-PO19. For example, PO block option PG15includes the gate region401, and the VG via403on the track M0_1, without a cut region. For another example, PO block option PO16includes the gate region401, and a VG via408on the track M0_2, without a cut region. Unlike the PO block options PO0-PO9, PO11, PO12where no VG via is arrangeable on the track M0_3due to the presence of a cut-PO region (e.g., the cut-PO region402), the PO block option PO17includes a VG via on the track M0_3in the absence of a cut-PO region.

The PO block option P020is a combination of a gate region, and a cut region CPODR409that disables the whole gate region.

All of the PO block options400A satisfy predetermined design rules. In other words, the PO block options400A are DRC-free.

InFIG.4B, the source/drain block options400B include all possible source/drain block options corresponding to a given layout configuration, i.e., the layout configuration described with respect toFIG.4A. Other layout configurations are within the scopes of various embodiments.

The source/drain block options (referred to herein as MD block options) inFIG.4Ainclude 28 MD block options MD0-MD27. Each of the MD block options400B is an MD region (e.g., the MD block option MD9), or a combination (e.g., the MD block options MD0-MD8, MD10-MD27) of an MD region with at least one of (i) at least one first cut region configured to cut or disable a portion of the MD region, or (ii) at least one first via over the MD region.

For example, the MD block option MD9is an MD region411that extends continuously over a PMOS active region and an NMOS active region (not shown). There is no cut region or via on, or associated with, the MD region411in the MD block option MD9.

The MD block option MD0is a combination of the MD region411, with a cut-MD region412, and without a via. The MD region411in the MD block option MD0is divided by the cut-MD region412into MD region portions413,414correspondingly over the PMOS active region and NMOS active region. The cut-MD region412is arranged along the track M0_3in the middle of the cell along the Y-axis.

Each of the MD block options MD1, MD2, MD4, MD6is a combination of an MD region, a cut-MD region, and one VD via. For example, the MD block option MD1includes the MD region411(represented by the MD region portions413,414), the cut-MD region412, and one VD via415. A VD via may not overlap a cut-MD region where an MD region does not exist. Because the cut-MD region412is arranged along the track M0_3, a VD via is arrangeable on one of the other M0tracks for signals, i.e., one of the tracks M0_1, M0_2, M0_4, M0_5. For example, in the MD block option MD1, the VD via415is on the track M0_5. The MD block options MD2, MD4, MD6are similar to the MD block option MD1, except for the position of the VD via which is correspondingly arranged on the tracks M0_1, M0_2, M0_4.

Each of the MD block options MD3, MD5, MD7, MD8is a combination of an MD region, a cut-MD region, and two VD vias correspondingly on two MD region portions divided by the cut-MD region. For example, the MD block option MD3is similar to the MD block option MD1, with the addition of a second VD via416. The positions of the two VD vias are different among the MD block options MD3, MD5, MD7, MD8.

Each of the MD block options MD10-MD14is a combination of an MD region and a VD via, without a cut region. The VD via is arranged correspondingly on the tracks M0_1, M0_2, M0_3, M0_4, M0_5in the MD block options MD10-MD14. For example, the MD block option MD13includes the MD region411and a VD via419on the track M0_4. Unlike the MD block options MD1-MD8where no VD via is arrangeable on the track M0_3due to the presence of a cut-MD region (e.g., the cut-MD region412), the MD block option MD12includes a VD via on the track M0_3in the absence of a cut-MD region.

Each of the MD block options MD15-MD20is a combination of an MD region and two VD vias, without a cut region. Each of the two VD vias is arrangeable on one of the tracks M0_1, M0_2, M0_3, M0_4, M0_5. The positions of the two VD vias are different among the MD block options MD15-MD20.

The MD block option MD21is a combination of an MD region, a cut-MD region, and two VD2vias for power supply. For example, the MD block option MD21is similar to the MD block option MD0, with the addition of VD2vias417,418correspondingly on the tracks M0_VDD, M0_VSS.

Each of the MD block options MD22, MD25is a combination of an MD region, a cut-MD region, and one VD2via for power supply. For example, the MD block option MD22is similar to the MD block option MD21, except that the VD2via418is omitted. The MD block option MD25is similar to the MD block option MD21, except that the VD2via417of the MD block option MD21is omitted.

Each of the MD block options MD23, MD24, MD26, MD27is a combination of an MD region, a cut-MD region, one VD via for signal, and one VD2via for power supply. For example, the MD block option MD27is similar to the MD block option MD21, except the VD2via417of the MD block option MD21is replaced with the VD via419. The positions of the VD and VD2vias are different among the MD block options MD23, MD24, MD26, MD27.

All of the MD block options400B satisfy predetermined design rules. In other words, the MD block options400B are DRC-free.

In some embodiments, the PO block options400A and the MD block options400B are stored, e.g., in the at least one library133on a non-transitory computer-readable medium. In at least one embodiment, a PO block option among the PO block options400A is combined with an MD block option among the MD block options400B in a DRC-free manner that satisfies predetermined design rules, to obtain a layout block. In at least one embodiment, all possible DRC-free combinations of a PO block option among the PO block options400A with an MD block option among the MD block options400B are determined, to obtain a plurality of layout blocks each including a PO block option and an MD block option. In some embodiments, because each of the PO block options400A and each of MD block options400B are DRC-free, and the PO block options and MD block options are combined in an DRC-free manner, the resulting plurality of layout blocks are also DRC-free. In some embodiments, the plurality of layout blocks are stored in the at least one library133, to be later retrieved and used to build multiple layouts for various cells or circuits.

FIG.4Cincludes schematic views showing example combinations421,422,423of block options associated with corresponding layout features, in accordance with some embodiments.

The combination421is a combination of the PO block option PO16inFIG.4A, and the MD block option MD21inFIG.4B. The PO block option PO16is combined with the MD block option MD21such that a distance d3along the X-axis between the centerline of the gate region401in the PO block option PO16and the centerline of the MD region411in the MD block option MD21is 0.5 CPP. This distance of 0.5 CPP is the same as the center-to-center distance between a gate region and an immediately adjacent MD region in a cell layout, as described with respect toFIG.3A. In combining the PO block option PO16with the MD block option MD21, an edge (e.g., the left edge) of the cut-MD region412of the MD block option MD21becomes coinciding with the centerline of the gate region401in the PO block option PO16. The PO block option PO16is in abutment with the MD block option MD21in the combination421. The size (width) of the combination421along the X-axis is 1 CPP. The combination421satisfies predetermined design rules, and is accepted as a layout block to be used for building multiple layouts for various cells or circuits. Herein, a combination of a PO block option and an MD block option is referred to as a PO-MD combination, and a layout block corresponding to a PO-MD combination is referred to as a PO-MD layout block. The size (width) of a PO-MD layout block along the X-axis is 1 CPP.

The combination422is a PO-MD combination of the PO block option P04inFIG.4A, and the MD block option MD0inFIG.4B. The PO block option P04is combined (or abutted) with the MD block option MD0in a manner as described with respect to the combination421. The combination422satisfies predetermined design rules, and is accepted as a PO-MD layout block to be used for building multiple layouts for various cells or circuits.

The combination423is a PO-MD combination of the PO block option PO18inFIG.4A, and the MD block option MD13inFIG.4B. The PO block option PO18is combined (or abutted) with the MD block option MD13in a manner as described with respect to the combination421. However, the combination423violates a design rule with respect to an edge-to-edge distance d4along the X-axis between the VG via406of the PO block option PO18and the VD via419of the MD block option MD13. Both the VG via406and the VD via419are arranged on the same track M0_4, and the edge-to-edge distance d4is smaller than a critical distance required by the design rules. The combination423is not accepted as a PO-MD layout block. The combination423is an example that not every combination (or abutment) of a PO block option and an MD block option is acceptable as a PO-MD layout block.

In some embodiments, all possible and acceptable PO-MD layout blocks, which are DRC-free, are determined from the combinations of the PO block options400A and MD block options400B, and are stored to be used for building multiple layouts for various cells or circuits.

The combinations421,422are examples PO-MD layout blocks each obtained by combining one PO block option and one MD block option, and having a width of 1 CPP. Other combinations are within the scopes of various embodiments. For example, from the same PO block options400A and MD block options400B, various PO-MD-PO combinations are obtainable by arranging an MD block option between and abutting two PO block options, in a manner as described with respect to the combination421. Each obtained PO-MD-PO combination is verified for DRC violations between the MD block option and the two PO block options, and/or between the two PO block options. If no DRC violation is found, i.e., the PO-MD-PO combination satisfies the predetermined design rules, the PO-MD-PO combination is stored as a PO-MD-PO layout block for later use. In some embodiments, all possible and acceptable PO-MD-PO layout blocks, which are DRC-free, are determined from the combinations of the PO block options400A and MD block options400B, and are stored to be used for building multiple layouts for various cells or circuits. A PO-MD-PO layout block has a width of 1.5 CPP along the X-axis.

In some embodiments, all possible and acceptable MD-PO-MD layout blocks, which are DRC-free, are determined from the combinations of the PO block options400A and MD block options400B, and are stored to be used for building multiple layouts for various cells or circuits.

In some embodiments, more complex layout blocks with greater widths are obtainable from the PO block options400A and MD block options400B. In at least one embodiment, all possible and acceptable PO-MD-PO-MD layout blocks, which are DRC-free, are determined from the combinations (or alternating abutment) of two PO block options among the PO block options400A with two MD block options among the MD block options400B. All possible and DRC-free PO-MD-PO-MD layout blocks are stored to be used for building multiple layouts for various cells or circuits. A PO-MD-PO-MD layout block has a width of 2 CPP along the X-axis.

In some embodiments, DRC-free layout blocks of a width of up to 10 CPP are obtained from the combinations (or alternating abutment) of up to ten PO block options with up to ten MD block options, and are stored to be used for building multiple layouts for various cells or circuits.

FIGS.4D,4Eare schematic views showing various block options associated with a further layout feature, in accordance with some embodiments. The further layout feature discussed with respect toFIGS.4D,4Eis a cut-M0(CM0) region, and the associated block options are referred to as CM0block options.

InFIG.4D, the CM0block options are not illustrated by themselves; rather, the CM0block options are shown in combinations with the MD block option MD0. For example, inFIG.4D, a CM0block option C0shown in combination with the MD block option MD0is designated as MD0-C0, a CM0block option C1shown in combination with the MD block option MD0is designated as MD0-C1, and so on, a CM0block option C14shown in combination with the MD block option MD0is designated as MD0-C14.

The CM0block options differ from each other by the number and positions of cut-M0regions. For example, the CM0block options C0-C4are CM0block options with one cut-M0region, and correspondingly include cut-M0regions431-435configured to correspondingly cut M0conductive patterns along the tracks M0_1, M0_2, M0_3, M0_4, M0_5. The CM0block options C5-C14are CM0block options with two cut-M0regions, and correspondingly include two of cut-M0regions431-435in various possible combinations. The cut-M0regions432,434belong to a cut-M0mask CM0A configured to cut M0A conductive patterns along the tracks M0_2, M0_4. The cut-M0regions431,433,435belong to a cut-M0mask CM0B configured to cut M0B conductive patterns along the tracks M0_1, M0_3, M0_5.

InFIG.4D, a diagram436shows, at each of a plurality of “X” marks, the M0track being cut by a cut-M0region in a corresponding CM0block option. In an example, the “X” mark437shows that the cut-M0region435in the CM0block option C0is configured to cut a M0conductive pattern along the track M0_5. In another example, the “X” marks438,439show that the cut-M0regions432,431in the CM0block option C14are correspondingly configured to cut M0conductive patterns along the tracks M0_1, M0_2.

The schematic diagram inFIG.4Ddoes not show all possible CM0block options. For example, CM0block options each including three, four or five cut-M0regions are not illustrated, for simplicity. However, all CM0block options each including one, two, three, four or five cut-M0regions are considered for combination with the PO block options400A and/or the MD block options400B to form layout blocks for building multiple layouts for various cells or circuits. As illustrated inFIG.4D, in a combination with an MD block option, the cut-M0region(s) of a CM0block option are arranged over the MD region of the MD block option. In a combination with a PO block option, the cut-M0region(s) of a CM0block option are arranged over the gate region of the PO block option. An example of a combination of a CM0block option with a PO block option is included in a layout block523inFIG.5D.

If a combination of an MD block option and a CM0block option is DRC-free, it is referred to as an MD-MC0block option. For example, inFIG.4D, all combinations of the CM0block options C0-C14with the MD block option MD0satisfy predetermined design rules, and are DRC-free. Thus, all combinations of the CM0block options C0-C14with the MD block option MD0inFIG.4Dare MD-MC0block options. If a combination of a PO block option and a CM0block option is DRC-free, it is referred to as a PO-MC0block option. An MD-MC0block option or an MD block option is considered for further combination with a PO block option or a PO-MC0block option. If the combination is DRC-free, it is considered as a layout block to be used for building multiple layouts for various cells or circuits. In some embodiments, an MD-MC0block option is considered as an MD block option which includes one or more cut-M0region(s), in addition to an MD region, any cut-MD region and/or any VD via. In some embodiments, a PO-MC0block option is considered as a PO block option which includes one or more cut-M0region(s), in addition to a gate region, any cut-PO region and/or any VG via and/or any cut region CPODR.

InFIG.4E, the CM0block options are shown in combination with the MD block option MD1. For example, inFIG.4E, the CM0block option C0shown in combination with the MD block option MD1is designated as MD1-C0, the CM0block option C1shown in combination with the MD block option MD1is designated as MD1-C1, and so on, the CM0block option C14shown in combination with the MD block option MD1is designated as MD1-C14. Similarly toFIG.4D, the schematic diagram inFIG.4Edoes not show all possible CM0block options, e.g., CM0block options each including three, four or five cut-M0regions are not illustrated, for simplicity.

The schematic diagram inFIG.4Eshows that not every combination of a CM0block option and an MD block option is DRC-free or acceptable for further combination with a PO block option. For example, in the combination MD1-C0, the VD via415of the MD block option MD1overlaps the cut-M0region435of the CM0block option C0. The cut-M0region435removes the M0conductive pattern over the VD via415, and leaves no M0conductive pattern to be electrically coupled with the VD via415. This is a DRC violation, and the combination MD1-C0is not considered as an MD-MC0block option and is excluded from further combination with a PO block option. A similar situation with the VD via415overlapping the cut-M0region435is observed in the combinations MD1-C5, MD1-C6, MD1-C7, MD1-C8all of which are not considered as MD-MC0block options and are excluded from further combination with a PO block option.

Although in the combination MD1-C1, the VD via415partially overlaps the cut-M0region434, this is not a DRC violation. A reason is that the cut-M0region434is configured to cut M0conductive patterns along the track M0_4, and does not effect M0conductive patterns along the track M0_5on which the VD via415is arranged. Except for the combinations MD1-C0, MD1-C5, MD1-C6, MD1-C7, MD1-C8, all other combinations of the CM0block options with the MD block option MD1inFIG.4Esatisfy predetermined design rules, are DRC-free, and are MD-MC0block options to be considered for further combination with a PO block option.

The described combinations of some CM0block options with the MD block option MD0inFIG.4D, and with the MD block option MD1inFIG.4Eare examples. In some embodiments, combinations of all CM0block options, including CM0block options with more than two cut-M0regions, with all MD block options MD0-MD27and with all PO block options PO0-PO20are determined. All MD-MC0and PO-MC0combinations that are DRC-free are considered as MD-MC0and PO-MC0block options. All MD-MC0block options and all MD block options MD0-MD27are considered as MD block options. All PO-MC0block option and all PO block options PO0-PO20are considered as PO block options. All possible combinations of all MD block options and all PO block options, with up to 10 CPP in width, are determined. All combinations that are DRC-free are stored as layout blocks to be used for building multiple layouts for various cells or circuits.

FIG.4Fincludes schematic views showing example combinations451,452of block options associated with corresponding layout features, in accordance with some embodiments.

The combination451is a PO-MD-CM0combination of the PO block option P07inFIG.4A, the MD block option MD0inFIG.4B, and the CM0block option C3described with respect toFIG.4D. The cut-M0region432of the CM0block option C3is arranged over the MD region411of the MD block option MD0, resulting in the MD-MC0block option MD0-C3as shown inFIG.4D. The MD-MC0block option MD0-C3is combined (i.e., abutted) with the PO block option P07in a manner similar to that described with respect toFIG.4C, to obtain the combination451. The combination451satisfies predetermined design rules, and is accepted as a layout block, with a width of 1 CPP, to be used for building multiple layouts for various cells or circuits.

The combination452is a PO-MD-CM0combination of the PO block option PO16inFIG.4A, and the MD block option MD21inFIG.4B, and the CM0block option C6described with respect toFIG.4D. The cut-M0regions433,435of the CM0block option C6are arranged over the MD region411of the MD block option MD21, resulting in a MD-MC0block option. The MD-MC0block option is combined (i.e., abutted) with the PO block option PO16in a manner similar to that described with respect toFIG.4C, to obtain the combination452. The combination452satisfies predetermined design rules, and is accepted as a layout block, with a width of 1 CPP, to be used for building multiple layouts for various cells or circuits.

FIG.5Ais a schematic view showing an example of mapping block options associated with a layout feature to a floorplan of a circuit of an IC device, in accordance with some embodiments. In the example inFIG.5A, the MD block options400B are mapped to the source/drain block371in the floorplan300B to determine which of the MD block options400B matches the one or more nets in the source/drain block371. In some embodiments, the mapping is performed in accordance with one or more LVS rules, as follows.

In response to the source/drain block371including two different nets con and VSS, it is determined, e.g., by at least one processor, that a matching MD block option must include a cut-MD region to electrically separate the two nets. As a result, the MD block options MD9-MD20which include no cut-MD region are excluded.

In response to the source/drain block371including the net VSS corresponding to the NMOS active region, it is determined, e.g., by at least one processor, that a matching MD block option must include a VD2via corresponding to the NMOS active region. As a result, all MD block options other than the MD block options MD21, MD25, MD26, MD27are excluded.

In response to the source/drain block371including the net con corresponding to the PMOS active region, it is determined, e.g., by at least one processor, that a matching MD block option must include a VD via corresponding to the PMOS active region for connection for the net con. Among the remaining MD block options MD21, MD25, MD26, MD27, only the MD block options MD26, MD27meet this requirement.

Thus, based on the nets con and VSS associated with the source/drain block371, it is determined, e.g., by at least one processor, that a matching layout block must include one of the MD block options MD26, MD27. In some embodiments, all layout blocks that include the MD block option MD26or MD27are selected to be used for building a layout in accordance with the floorplan300B.

In some embodiments, the described mapping is performed to map, not only the MD block options400B inFIG.4B, but also the available MD-MC0block options with one or more cut-M0regions to the source/drain block371. The described mapping is performed for all other source/drain blocks373,375,377,379in the floorplan300B.

In some embodiments, a similar mapping is performed to map, e.g., by at least one processor, one or more of the available PO block options to each of the gate blocks372,374,376,378of the floorplan300B. An example result of the described gate block mapping and source/drain block mapping is given inFIG.5B.

FIG.5Bis a schematic view showing an example result of mapping various layout blocks to the floorplan300B, in accordance with some embodiments.

As discussed with respect toFIG.5A, all layout blocks that include the MD block option MD26or MD27are selected as layout blocks matching the source/drain block371of the floorplan300B. One of those selected layout blocks is a layout block511which includes the MD block option MD26. The layout block511further comprises the PO block option P20corresponding to a cell boundary on the left side of the source/drain block371.

As a result of a mapping of the available PO block options to the gate block372based on the nets B2, B2associated with the gate block372, it is determined that a matching layout block must include one of the PO block options PO15-PO19. As a result of a mapping of the available MD block options to the source/drain block373based on the nets VDD, n1associated with the source/drain block373, it is determined that a matching layout block must include the MD block option MD22which is the only MD block option that matches the net VDD (VD2on the PMOS) and net n1(no VD on the NMOS). All layout blocks that include one of the PO block options PO15-PO19and the MD block option MD22are selected as layout blocks matching both the gate block372and the source/drain block373of the floorplan300B. One of those selected layout blocks is a layout block512which includes the PO block option PO15and MD block option MD22.

Similar block option mappings and layout block selections are performed for the remaining blocks374-379of the floorplan300B. In the example result inFIG.5B, a layout block513includes the PO block option PO17that matches the gate block374, and a combination of the MD block option MD5with the CM0block option C4that matches the source/drain block375. A layout block514includes the PO block option PO15that matches the gate block376, and a combination of the MD block option MD6with the CM0block option C3that matches the source/drain block377. A layout block515includes the PO block option PO16that matches the gate block378, and the MD block option MD26that matches the source/drain block379. The PO block option P20corresponding to a cell boundary on the right side of the layout block515is added.

In some embodiments, the selected layout blocks511-515are combined by abutment, in a manner similar to that described with respect toFIG.4C. For example, to abut the layout block511with the layout block512, the right edge of the cut-MD region412of the MD block option MD26in the layout block511is aligned with the centerline of the gate region401of the PO block option PO15in the layout block512. The other selected layout blocks513-515are further abutted to each other and to the right side of the layout block512in similar manners.

FIG.5Cis a schematic view of a layout500C obtained by combining the various layout blocks511-515inFIG.5B, in accordance with some embodiments. In this example, the layout500C corresponds to the layout300C described with respect toFIG.3C.

The layout500C is just a layout solution among many other layout solutions that are generated in accordance with the floorplan300B. An alternative layout solution (not shown) includes the MD block option MD26for the source/drain block371, the PO block option PO17for the gate block372, the MD block option MD22for the source/drain block373, the PO block option PO18for the gate block374, a combination of the MD block option MD3and the CM0block option C9for the source/drain block375, the PO block option PO16for the gate block376, the MD block option MD6for the source/drain block377, the PO block option PO17for the gate block378, and the MD block option MD26for the source/drain block379.

In some embodiments, as described herein, all possible layout solutions corresponding to a floorplan, such as the floorplan300B, of a circuit are generated from predetermined layout blocks. As a result, it is possible for an IC designer to find a better layout for the same circuit than the current layout, making it possible to improve IC layouts in one or more embodiments.

In some embodiments, the same predetermined layout blocks are usable to generate layout solutions for different circuits, for example, as described with respect toFIG.5D.

FIG.5Dincludes a schematic view showing an example of mapping various layout blocks to a floorplan of a circuit of an IC device, and a schematic view of a layout500D obtained by combining the various layout blocks, in accordance with some embodiments. The circuit inFIG.5Dis XOR2D1, i.e., different from the AOI22D1 circuit discussed with respect toFIG.5C. XOR2D1 is a 2-input XOR gate with the driving strength of 1. A floorplan of XOR2D1 is different from the floorplan300B, and is not shown inFIG.5D.

InFIG.5D, as a result of mapping the available PO, MD and/or CM0block options to various source/drain blocks and gate blocks in a floorplan of XOR2D1, as described with respect toFIGS.5A-5B, various matching PO, MD and/or CM0block options are identified, and one or more of the available layout blocks are selected based on the matching PO, MD and/or CM0block options. The selected layout blocks together include a set of alternating gate block options and source/drain block options correspondingly mapped to the plurality of alternating gate blocks and source/drain blocks in the floorplan. For example, a set of selected layout blocks inFIG.5Dincludes layout blocks521-525which include various PO, MD and/or CM0block options which are usable to generate various layout solutions for another circuit, e.g., AOI22D1, as described with respect toFIG.5C.

The layout block521includes the PO block option PO16for a gate block, and the MD block option MD21for a source/drain block in the floorplan of XOR2D1. The layout block522includes the PO block option P04for a gate block, and the MD block option MD0for a source/drain block in the floorplan of XOR2D1. The layout block523includes a combination of the PO block option PO17with the CM0block option C11for a gate block, and the MD block option MD7for a source/drain block in the floorplan of XOR2D1. In the combination of the PO block option PO17with the CM0block option C11, cut-M0regions531,532of the CM0block option C11are arranged over a gate region533of the PO block option PO17. The layout block524includes the PO block option P07for a gate block, and a combination of the MD block option MD0with the CM0block option C3for a source/drain block in the floorplan of XOR2D1. The layout block525includes the PO block option PO16for a gate block, and a combination of the MD block option MD21with the CM0block option C6for a source/drain block in the floorplan of XOR2D1. The layout500D is obtained by combining, e.g., abutting, the various layout blocks521-525. The layout500D is just a layout solution among many other layout solutions that are generated in accordance with the floorplan of XOR2D1.

In the described examples, PO-MD and/or PO-MD-CM0layout blocks with a width of 1 CPP are used to generate layout solutions. Other, larger layout blocks with a width of up to 10 CPP are usable in similar manners to generate layout solutions.

FIG.6is a schematic view showing a search600for combining various layout blocks mapped to a floorplan of a circuit of an IC device into various layout diagrams of the circuit, in accordance with some embodiments. In the example inFIG.6, the search600comprises a depth-first search (DFS) algorithm executed by at least one processor. In at least one embodiment, the DFS algorithm starts at the root of a search tree and explores as far (or deep) as possible or necessary along each branch before backtracking.

For example, the floorplan of the circuit comprises blocks601-605each of which comprises a gate block and a source/drain block. The search600starts from a layout block621matching the block601of the floorplan. The search600then looks for and finds a first layout block622matching the block602of the floorplan. The search600then looks for and finds a first layout block623matching the block603of the floorplan. The search600then looks for and finds a first layout block624matching the block604of the floorplan. The search600then looks for and finds a first layout block625matching the block605of the floorplan. At this point a first layout solution including the layout blocks621-625matching the floorplan is obtained and stored. The search600then looks for another layout block matching the block605to be combined with the current layout block624corresponding to the block604.

When a next layout block matching the block605is not found or, due to one or more design rules, is not combinable with the current layout block624corresponding to the block604, the search600backtracks one level to look for a next layout block matching the block604.

When a next layout block matching the block604is not found or, due to one or more design rules, is not combinable with the current layout block623corresponding to the block603, the search600backtracks one further level to look for a next layout block matching the block603.

When a layout block626matching the block603is found, the search600then looks for a first layout block matching the block604of the floorplan and combinable with the layout block626. When a layout block627is found, the search600then looks for a first layout block matching the block605of the floorplan and combinable with the layout block627. When a layout block628is found, a second layout solution including the layout blocks621,622,626,627,628matching the floorplan is obtained and stored.

The search600progresses in similar manners to find third to fifth layout solutions. The third layout solution includes layout blocks621,629,630,631,632. The fourth layout solution includes layout blocks621,629,630,631,633. The fifth layout solution includes layout blocks621,629,630,634,635.

At this point, it is determined that the search for layout solutions starting with the layout block621has been exhaustive, and the search600switches to a new search tree starting from a further layout block matching the block601of the floorplan. The described algorithm is then repeated in a similar manner to perform an exhaustive search for all possible layout solutions matching the floorplan.

While other search methodologies, e.g., breadth-first search, are usable in accordance with some embodiments to find all possible layout solutions corresponding to a floorplan, the described DSF is advantageous in quickly locating first layout solutions.

In some embodiments as described herein, one or more layout blocks are combined with each other by abutting one layout block with another, in a manner similar to that described with respect toFIG.4C. Other ways for combining layout blocks are within the scopes of various embodiments, for example, as described with respect toFIGS.7B-7D.

FIG.7Ais a schematic view showing a potential design rule violation when certain layout blocks are combined.

In the simplified example inFIG.7A, two identical layout blocks701and702are to be combined. The layout blocks701and702also the same as the layout block523described with respect toFIG.5D. The layout blocks701and702are combined, resulting in a combined layout block708in which a center-to-center distance along the X-axis between a cut-M0region703of the layout block701and a cut-M0region704of the layout block702is 1 CPP. A predetermined design rule requires that cut-M0regions on the same M0track should be spaced by a center-to-center distance being greater than 1 CPP. Therefore, the combination of the layout blocks701and702results in a DRC violation.

The example situation described with respect toFIG.7Aillustrates a potential risk of DRC violation when layout blocks are combined. It is possible to make certain checks after layout blocks are combined to determine whether there is a DRC violation in the combined layout block. Such checks, however, may slow down the search for multiple layout solutions corresponding to a floorplan. In at least one embodiment, a potential risk of DRC violation is reduced when layout blocks are combined not by abutting, but by overlapping in an identical border region, as described with respect toFIGS.7B-7D.

FIG.7Bis a schematic views showing an example of combining layout blocks, in accordance with some embodiments.

InFIG.7B, layout blocks711,712are to be combined. Each of the layout blocks711,712is a PO-MD-PO-MD layout block having a width of 2 CPP. The layout block711includes a first region713, and a border region715. The layout block712includes a second region716, and a border region715. The border region715of the layout block711is identical to the border region715of the layout block712. As described herein, layout blocks are generated in such a manner to ensure that predetermined design rules are satisfied, i.e., the layout blocks are DRC-free. As also described herein, to ensure that layout blocks are DRC-free, various block options used to generate layout blocks are DRC-free, and are combined with each other in a DRC-free manner. Combinations of block options are excluded from being used as layout blocks when it is determined that such combinations are not DRC-free, for example, as described with respect toFIGS.4C,4E. Because the layout blocks711,712are DRC-free, there is no risk of DRC violation between the first region713and the border region715in the layout block711, and between the second region716and the border region715in the layout block712.

In some embodiments, the layout blocks711,712are combined by overlapping the layout blocks711,712in their identical border region715, i.e., by overlapping the border region715of the layout block711over the identical border region715of the layout block712. A resulting combined layout block718comprises the first region713, the second region716, and the border region715(which is no longer a border region) between the first region713and the second region716.

Because there is no risk of DRC violation between the first region713and the border region715in the layout block711, there is also no risk of DRC violation between the first region713and the border region715in the combined layout block718. Because there is no risk of DRC violation between the second region716and the border region715in the layout block712, there is also no risk of DRC violation between the second region716and the border region715in the combined layout block718. As a result the combined layout block718is DRC-free, or at least DRC-less, in one or more embodiments. Various approaches for utilizing the described combination technique by overlapping identical border regions are described with respect toFIGS.7C-7D.

FIG.7Cis a schematic views showing an example of combining layout blocks, in accordance with some embodiments.

InFIG.7C, layout blocks721,722are to be combined. For example, the layout block721includes block options A, B, C, D corresponding to blocks X=1, X=2, X=3, X=4 in a floorplan. In some situations, the layout block721is a predetermined layout block that is DRC-free. In other situations, the layout block721is a DRC-free combination of two DRC-free layout blocks, one including the blocks A, B, whereas the other including the block options C, D. The layout block722includes block options E, F corresponding to blocks X=5, X=6 in the floorplan. The layout block721is to be combined with the layout block722such that the block options A, B, C, D become contiguous to the block options E, F in accordance with the corresponding blocks X=1, X=2, X=3, X=4, X=5, X=6 in the floorplan. In some embodiments, the block options A, C, E include PO or MD block options, and the block options B, D, F include MD or PO block options.

An approach for combining the layout blocks721,722, in accordance with some embodiments, involves abutting the layout block721and the layout block722along the corresponding facing edges723,724. There might be, however, a risk of DRC violation in this approach in certain situations, as discussed with respect toFIG.7A.

An alternative approach, in accordance with some embodiments, involves overlapping, rather than abutting layout blocks, as discussed with respect toFIG.7B. In this approach, an intermediate layout block725including block options C, D, E, F is sought among the predetermined layout blocks and/or previously combined, DRC-free layout blocks. The intermediate layout block725includes a first region726, and a border region727. The border region727includes the block options C, D and is identical to a corresponding border region including the block options C, D in the layout block721. The first region726of the intermediate layout block725includes the block options E, F of the layout block722. When the intermediate layout block725is found, the layout block721and the intermediate layout block725are overlapped in their identical border region727, resulting in a combined layout block728which includes the block options A, B, C, D, E, F corresponding to the blocks X=1, X=2, X=3, X=4, X=5, X=6 in the floorplan.

Because each of the layout block721and the intermediate layout block725is predetermined or combined to be DRC-free, there is no risk of DRC violation among block options A, B, C, D of the layout block721, and there is no risk of DRC violation among block options C, D, E, F of the intermediate layout block725. As a result, there is no risk of DRC violation among the block options A, B, C, D, E, F in the combined layout block728which is equivalent to a combination of the layout blocks721,722being abutted along their facing edges723,724.

In some embodiments, instead of abutting the layout blocks721,722along their facing edges723,724and then performing one or more checks for DRC violation, at least one processor is configured to search for an existing, DRC-free intermediate layout block725which is then combined with the layout block721by overlapping the layout blocks721,725in an identical border region727thereof. In at least one embodiment, the obtained combined layout block728is DRC-free or at least DRC-less. As a result, it is possible to quickly combine layout blocks in accordance with the floorplan, while ensuring that obtained layout solutions are DRC-free or at least DRC-less.

FIG.7Dis a schematic views showing an example of combining layout blocks, in accordance with some embodiments.

InFIG.7D, layout blocks721,732are to be combined. The layout block721is described with respect toFIG.7C. The layout block732includes block options E, F, G, H corresponding to blocks X=5, X=6, X=7, X=8 in a floorplan. In some situations, the layout block732is a predetermined layout block that is DRC-free. In other situations, the layout block732is a DRC-free combination of two DRC-free layout blocks, one including the blocks E, F, whereas the other including the block options G, H. The layout block721is to be combined with the layout block732such that the block options A, B, C, D become contiguous to the block options E, F, G, H in accordance with the corresponding blocks X=1, X=2, X=3, X=4, X=5, X=6, X=7, X=8 in the floorplan. In some embodiments, the block options A, C, E, G include PO or MD block options, and the block options B, D, F, H include MD or PO block options.

An approach for combining the layout blocks721,732, in accordance with some embodiments, involves abutting the layout block721and the layout block732along the corresponding facing edges723,734. There might be, however, a risk of DRC violation in this approach in certain situations, as discussed with respect toFIG.7A.

An alternative approach, in accordance with some embodiments, involves overlapping, rather than abutting layout blocks, as discussed with respect toFIGS.7B,7C. In this approach, an intermediate layout block725including block options C, D, E, F is sought among the predetermined layout blocks and/or previously combined, DRC-free layout blocks. The intermediate layout block725includes a first border region726, and a second border region727. The second border region727includes the block options C, D and is identical to a corresponding border region including the block options C, D in the layout block721. The first border region726of the intermediate layout block725includes the block options E, F and is identical to a corresponding border region including the block options E, F in the layout block732.

When the intermediate layout block725is found, the layout block721and the intermediate layout block725are overlapped in their identical border region727, resulting in an intermediate combined layout block728which includes the block options A, B, C, D, E, F corresponding to the blocks X=1, X=2, X=3, X=4, X=5, X=6 in the floorplan.

The intermediate combined layout block728has the border region726identical to the corresponding border region including the block options E, F in the layout block732. The layout block732and the intermediate combined layout block725are overlapped in their identical border region726, resulting in a combined layout block738which includes the block options A, B, C, D, E, F, G, H corresponding to the blocks X=1, X=2, X=3, X=4, X=5, X=6, X=7, X=8 in the floorplan.

Because each of the layout block721, the intermediate layout block725and the layout block732is predetermined or combined to be DRC-free, there is no risk of DRC violation among block options A, B, C, D of the layout block721, there is no risk of DRC violation among block options C, D, E, F of the intermediate layout block725, and there is no risk of DRC violation among block options E, F, G, H of the layout block732. As a result, there is no risk of DRC violation among the block options A, B, C, D, E, F, G, H in the combined layout block738which is equivalent to a combination of the layout blocks721,732being abutted along their facing edges723,734.

In some embodiments, instead of abutting the layout blocks721,732along their facing edges723,734and then performing one or more checks for DRC violation, at least one processor is configured to search for an existing, DRC-free intermediate layout block725which includes two border regions correspondingly identical to border regions in the layout blocks721,732to be combined. The intermediate layout block725is then combined with the layout blocks721,732by overlapping in the identical border regions. In at least one embodiment, the obtained combined layout block738is DRC-free or at least DRC-less. As a result, it is possible to quickly combine layout blocks in accordance with the floorplan, while ensuring that obtained layout solutions are DRC-free or at least DRC-less. In the examples described with respect toFIGS.7B-7D, the border region where one layout block overlaps another layout block, includes a PO block option and an MD block option, and has a width of 1 CPP. Larger border regions (or overlap regions) are within the scopes of various embodiments. In some embodiments, an overlap region has a width of up to 5 CPP. In some embodiments, one or more of the described methods, processes or search methodologies are applicable to find all possible routings in multiple metal layers, e.g., in one or more of the M0, M1, M2, M3layers.

FIG.8Ais a flowchart of a method800A of generating a layout of a circuit, in accordance with some embodiments. In at least one embodiment, method800B is performed by at least one processor.

At operation810, a plurality of different layout blocks is generated. Each layout block satisfies predetermined design rules and comprises at least one first block option associated with a first layout feature, and at least one second block option associated with a second layout feature. For example, as described with respect toFIGS.4C,4F, a plurality of different layout blocks, e.g., layout blocks421,422inFIG.4C, layout blocks451,452inFIG.4Fis generated. Each layout block satisfies predetermined design rules, e.g., each layout block is DRC-free as described herein. Each layout block, e.g., layout block421inFIG.4C, comprises at least one first block option, e.g., PO16, associated with a first layout feature, e.g., gate region, and at least one second block option, e.g., MD21associated with a second layout feature, e.g., MD region. The described layout blocks are examples. A large number of layout blocks is generated, e.g., by combining at least 21 PO block options (FIG.4A) and 28 MD block options (FIG.4B). The number of layout blocks is further increased when at least one additional layout feature, e.g., CM0, is considered, as described with respect toFIGS.4D-4F.

At operation812, among the plurality of layout blocks, layout blocks corresponding to a plurality of blocks in a floorplan of the circuit are selected, for example, as described with respect toFIG.5B.

At operation816, the selected layout blocks are combined in accordance with the floorplan into a layout of the circuit, for example, as described with respect toFIGS.5B-5D,6,7B-7D.

At operation818, the layout of the circuit is stored in a cell library, e.g., in at least one library133inFIG.1B, or used to generate a layout for an integrated circuit (IC) containing the circuit, e.g., as described with respect to operations130-170inFIG.1B.

In some embodiments, the layout blocks generated at operation810include all possible and DRC-free layout blocks obtainable from the PO block options and MD block options. These layout blocks are stored, e.g., in the at least one library133, for later use as predetermined blocks for building multiple layouts for various cells or circuits.

In some embodiments, operations812,816correspond to generating a layout solution based on the floorplan of the circuit. In at least one embodiment, by repeatedly performing operations812,816, multiple, or all possible, layout solutions based on the floorplan of the circuit are generated, as described with respect to operation135inFIG.1B. In at least one embodiment, one or more advantages described herein are achievable by the method800A.

FIG.8Bis a flowchart of a method800B of generating a layout of a circuit, in accordance with some embodiments. In at least one embodiment, method800B is performed by at least one processor.

At operation820, a first mapping is performed to map, to each gate block in a floorplan and based on one or more nets associated with the gate block, one or more gate block options among a plurality of predetermined gate block options. For example, as described with respect toFIG.5B, one or more gate block options among the PO block options400A (FIG.4A) are mapped to each of gate blocks372,374,376,378of the floorplan300B, based on the nets associated with each of the gate blocks372,374,376,378.

At operation822, a second mapping is performed to map, to each source/drain block in a floorplan and based on one or more nets associated with the source/drain block, one or more source/drain block options among a plurality of predetermined source/drain block options. For example, as described with respect toFIGS.5A,5B, one or more MD block options among the MD block options400B (FIG.4B) are mapped to each of source/drain blocks371,373,375,377,379of the floorplan300B, based on the nets associated with each of the source/drain blocks371,373,375,377,379.

At operation824, from a plurality of predetermined layout blocks each satisfying predetermined design rules and including at least one gate block options and at least one source/drain block option, layout blocks are selected. The selected layout blocks together include a set of alternating gate block options and source/drain block options correspondingly mapped to the plurality of alternating gate blocks and source/drain blocks in the floorplan. For example, as described with respect toFIGS.5B,5D, various layout blocks511-515,521-525are selected from a plurality of predetermined layout blocks to match the gate blocks and source/drain blocks in the floorplan.

At operation826, the selected layout blocks are combined in accordance with the floorplan into a layout of the circuit, for example, as described with respect toFIGS.5B-5D,6,7B-7D.

At operation828, the layout of the circuit is stored in a cell library, e.g., in at least one library133inFIG.1B, or used to generate a layout for an integrated circuit (IC) containing the circuit, e.g., as described with respect to operations130-170inFIG.1B. In at least one embodiment, one or more advantages described herein are achievable by the method800B.

FIG.8Cis a flowchart of a method800C of generating a layout of a circuit, in accordance with some embodiments. In at least one embodiment, method800C is performed by at least one processor.

At operation830, a first layout block is obtained. The first layout block includes a first region corresponding to a first portion in the floorplan, and a border region. For example, as described with respect toFIG.7C, a first layout block721including a first region A, B corresponding to a first portion in the floorplan, and a border region C, D (or727).

At operation832, a second layout block is obtained. The second layout block includes a second region corresponding to a second portion in the floorplan, and a border region identical to the border region of the first layout block. For example, as described with respect toFIG.7C, a second layout block725including a second region E, F corresponding to a second portion in the floorplan, and a border region C, D identical to the border region of the first layout block721.

At operation836, the first layout block and the second layout block are combined by overlapping the border region of the first layout block with the identical border region of the second layout block, resulting in a combined layout block of a layout of the circuit. The combined layout block comprises the first region and the second region on opposite sides of the border region. For example, as described with respect toFIG.7C, the first layout block721and the second layout block725are combined by overlapping the border region727of the first layout block721with the identical border region of the second layout block725, resulting in a combined layout block728of a layout of the circuit. The combined layout block728comprises the first region A, B and the second region E, F on opposite sides of the border region C, D.

At operation838, the layout of the circuit is stored in a cell library, e.g., in at least one library133inFIG.1B, or used to generate a layout for an integrated circuit (IC) containing the circuit, e.g., as described with respect to operations130-170inFIG.1B. In at least one embodiment, one or more advantages described herein are achievable by the method800C.

FIG.8Dis a flowchart of a method800D of manufacturing a semiconductor device or IC, in accordance with some embodiments.

Method800D is implementable, for example, using EDA system900(FIG.9, discussed below) and an integrated circuit (IC), manufacturing system1000(FIG.10, discussed below), in accordance with some embodiments.

InFIG.8D, method800D includes operations892,894. At operation892, a layout diagram is generated which, among other things, includes one or more of layouts for various circuits as disclosed herein, or the like. Operation892is implementable, for example, using EDA system900(FIG.9, discussed below), in accordance with some embodiments. From operation892, flow proceeds to operation894.

At operation894, based on the layout diagram, at least one of (A) one or more photolithographic exposures are made or (B) one or more semiconductor masks are fabricated or (C) one or more components in a layer of a semiconductor device are fabricated, as described herein below with respect toFIG.10.

In at least one embodiment, one or more of the described operations are omitted. In at least one embodiment, one or more of the described operations are combined. In at least one embodiment, one or some or all of the described operations are automatically performed by at least one processor.

The described methods include example operations, but they are not necessarily required to be performed in the order shown. Operations may be added, replaced, changed order, and/or eliminated as appropriate, in accordance with the spirit and scope of embodiments of the disclosure. Embodiments that combine different features and/or different embodiments are within the scope of the disclosure and will be apparent to those of ordinary skill in the art after reviewing this disclosure.

In some embodiments, at least one method(s) discussed herein is performed in whole or in part by at least one EDA system. In some embodiments, an EDA system is usable as part of a design house of an IC manufacturing system discussed below.

FIG.9is a block diagram of an electronic design automation (EDA) system900in accordance with some embodiments.

In some embodiments, EDA system900includes an automatic placement and routing (APR) system. Methods described herein of designing layout diagrams represent wire routing arrangements, in accordance with one or more embodiments, are implementable, for example, using EDA system900, in accordance with some embodiments.

In some embodiments, EDA system900is a general purpose computing device including a hardware processor902and a non-transitory, computer-readable storage medium904. Storage medium904, amongst other things, is encoded with, i.e., stores, computer program code906, i.e., a set of executable instructions. Execution of instructions906by hardware processor902represents (at least in part) an EDA tool which implements a portion or all of the methods described herein in accordance with one or more embodiments (hereinafter, the noted processes and/or methods).

Processor902is electrically coupled to computer-readable storage medium904via a bus908. Processor902is also electrically coupled to an I/O interface910by bus908. A network interface912is also electrically connected to processor902via bus908. Network interface912is connected to a network914, so that processor902and computer-readable storage medium904are capable of connecting to external elements via network914. Processor902is configured to execute computer program code906encoded in computer-readable storage medium904in order to cause system900to be usable for performing a portion or all of the noted processes and/or methods. In one or more embodiments, processor902is a central processing unit (CPU), a multi-processor, a distributed processing system, an application specific integrated circuit (ASIC), and/or a suitable processing unit.

In one or more embodiments, storage medium904stores computer program code906configured to cause system900(where such execution represents (at least in part) the EDA tool) to be usable for performing a portion or all of the noted processes and/or methods. In one or more embodiments, storage medium904also stores information which facilitates performing a portion or all of the noted processes and/or methods. In one or more embodiments, storage medium904stores library907of standard cells including such standard cells as disclosed herein. In one or more embodiments, storage medium904stores one or more layout diagrams disclosed herein.

EDA system900also includes network interface912coupled to processor902. Network interface912allows system900to communicate with network914, to which one or more other computer systems are connected. Network interface912includes wireless network interfaces such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or wired network interfaces such as ETHERNET, USB, or IEEE-2164. In one or more embodiments, a portion or all of noted processes and/or methods, is implemented in two or more systems900.

System900is configured to receive information through I/O interface910. The information received through I/O interface910includes one or more of instructions, data, design rules, libraries of standard cells, and/or other parameters for processing by processor902. The information is transferred to processor902via bus908. EDA system900is configured to receive information related to a UI through I/O interface910. The information is stored in computer-readable medium904as user interface (UI)942.

InFIG.10, IC manufacturing system1000includes entities, such as a design house1020, a mask house1030, and an IC manufacturer/fabricator (fab)1050, that interact with one another in the design, development, and manufacturing cycles and/or services related to manufacturing an IC1060. The entities in system1000are connected by a communications network. In some embodiments, the communications network is a single network. In some embodiments, the communications network is a variety of different networks, such as an intranet and the Internet. The communications network includes wired and/or wireless communication channels. Each entity interacts with one or more of the other entities and provides services to and/or receives services from one or more of the other entities. In some embodiments, two or more of design house1020, mask house1030, and IC fab1050is owned by a single larger company. In some embodiments, two or more of design house1020, mask house1030, and IC fab1050coexist in a common facility and use common resources.

Design house (or design team)1020generates an IC design layout diagram1022. IC design layout diagram1022includes various geometrical patterns designed for an IC1060. The geometrical patterns correspond to patterns of metal, oxide, or semiconductor layers that make up the various components of IC1060to be fabricated. The various layers combine to form various IC features. For example, a portion of IC design layout diagram1022includes various IC features, such as an active region, gate electrode, source and drain, metal lines or vias of an interlayer interconnection, and openings for bonding pads, to be formed in a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate. Design house1020implements a proper design procedure to form IC design layout diagram1022. The design procedure includes one or more of logic design, physical design or place and route. IC design layout diagram1022is presented in one or more data files having information of the geometrical patterns. For example, IC design layout diagram1022can be expressed in a GDSII file format or DFII file format.

Mask house1030includes data preparation1032and mask fabrication1044. Mask house1030uses IC design layout diagram1022to manufacture one or more masks1045to be used for fabricating the various layers of IC1060according to IC design layout diagram1022. Mask house1030performs mask data preparation1032, where IC design layout diagram1022is translated into a representative data file (RDF). Mask data preparation1032provides the RDF to mask fabrication1044. Mask fabrication1044includes a mask writer. A mask writer converts the RDF to an image on a substrate, such as a mask (reticle)1045or a semiconductor wafer1053. The design layout diagram1022is manipulated by mask data preparation1032to comply with particular characteristics of the mask writer and/or requirements of IC fab1050. InFIG.10, mask data preparation1032and mask fabrication1044are illustrated as separate elements. In some embodiments, mask data preparation1032and mask fabrication1044can be collectively referred to as mask data preparation.

In some embodiments, mask data preparation1032includes a mask rule checker (MRC) that checks the IC design layout diagram1022that has undergone processes in OPC with a set of mask creation rules which contain certain geometric and/or connectivity restrictions to ensure sufficient margins, to account for variability in semiconductor manufacturing processes, and the like. In some embodiments, the MRC modifies the IC design layout diagram1022to compensate for photolithographic implementation effects during mask fabrication1044, which may undo part of the modifications performed by OPC in order to meet mask creation rules.

In some embodiments, mask data preparation1032includes lithography process checking (LPC) that simulates processing that will be implemented by IC fab1050to fabricate IC1060. LPC simulates this processing based on IC design layout diagram1022to create a simulated manufactured device, such as IC1060. The processing parameters in LPC simulation can include parameters associated with various processes of the IC manufacturing cycle, parameters associated with tools used for manufacturing the IC, and/or other aspects of the manufacturing process. LPC takes into account various factors, such as aerial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, and the like or combinations thereof. In some embodiments, after a simulated manufactured device has been created by LPC, if the simulated device is not close enough in shape to satisfy design rules, OPC and/or MRC are be repeated to further refine IC design layout diagram1022.

It should be understood that the above description of mask data preparation1032has been simplified for the purposes of clarity. In some embodiments, data preparation1032includes additional features such as a logic operation (LOP) to modify the IC design layout diagram1022according to manufacturing rules. Additionally, the processes applied to IC design layout diagram1022during data preparation1032may be executed in a variety of different orders.

After mask data preparation1032and during mask fabrication1044, a mask1045or a group of masks1045are fabricated based on the modified IC design layout diagram1022. In some embodiments, mask fabrication1044includes performing one or more lithographic exposures based on IC design layout diagram1022. In some embodiments, an electron-beam (e-beam) or a mechanism of multiple e-beams is used to form a pattern on a mask (photomask or reticle)1045based on the modified IC design layout diagram1022. Mask1045can be formed in various technologies. In some embodiments, mask1045is formed using binary technology. In some embodiments, a mask pattern includes opaque regions and transparent regions. A radiation beam, such as an ultraviolet (UV) beam, used to expose the image sensitive material layer (e.g., photoresist) which has been coated on a wafer, is blocked by the opaque region and transmits through the transparent regions. In one example, a binary mask version of mask1045includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chromium) coated in the opaque regions of the binary mask. In another example, mask1045is formed using a phase shift technology. In a phase shift mask (PSM) version of mask1045, various features in the pattern formed on the phase shift mask are configured to have proper phase difference to enhance the resolution and imaging quality. In various examples, the phase shift mask can be attenuated PSM or alternating PSM. The mask(s) generated by mask fabrication1044is used in a variety of processes. For example, such a mask(s) is used in an ion implantation process to form various doped regions in semiconductor wafer1053, in an etching process to form various etching regions in semiconductor wafer1053, and/or in other suitable processes.

IC fab1050includes fabrication tools1052configured to execute various manufacturing operations on semiconductor wafer1053such that IC1060is fabricated in accordance with the mask(s), e.g., mask1045. In various embodiments, fabrication tools1052include one or more of a wafer stepper, an ion implanter, a photoresist coater, a process chamber, e.g., a CVD chamber or LPCVD furnace, a CMP system, a plasma etch system, a wafer cleaning system, or other manufacturing equipment capable of performing one or more suitable manufacturing processes as discussed herein.

In some embodiments, a system comprises a processor, and a non-transitory computer readable storage medium connected to the processor, wherein the processor is configured to execute instructions stored on the computer readable storage medium. The processor is configured to perform generating a plurality of different layout blocks, selecting, among the plurality of layout blocks, layout blocks corresponding to a plurality of blocks in a floorplan of a circuit, combining the selected layout blocks in accordance with the floorplan into a layout of the circuit, and storing the layout of the circuit in a cell library or using the layout of the circuit to generate a layout for an integrated circuit (IC) containing the circuit. Each of the plurality of layout blocks satisfies predetermined design rules and comprises at least one of a plurality of different first block options associated with a first layout feature, and at least one of a plurality of different second block options associated with a second layout feature different from the first layout feature.

In some embodiments, a method of generating layouts for a circuit in accordance with a floorplan of the circuit is performed at least partially by a processor. The floorplan comprises a plurality of nets associated with a plurality of alternating gate blocks and source/drain blocks. The method comprises first mapping, to each gate block in the floorplan and based on one or more nets associated with the gate block, one or more gate block options among a plurality of predetermined gate block options. The method further comprises second mapping, to each source/drain block in the floorplan and based on one or more nets associated with the source/drain block, one or more source/drain block options among a plurality of predetermined source/drain block options. The method further comprises selecting, from a plurality of predetermined layout blocks each satisfying predetermined design rules and including at least one of the plurality of predetermined gate block options and at least one of the plurality of predetermined source/drain block options, layout blocks which together include a set of alternating gate block options and source/drain block options correspondingly mapped, by said first mapping and second mapping, to the plurality of alternating gate blocks and source/drain blocks in the floorplan. The method further comprises combining the selected layout blocks in accordance with the floorplan into a layout of the circuit; and storing the layout of the circuit in a cell library or using the layout of the circuit to generate a layout for an integrated circuit (IC) containing the circuit.

In some embodiments, a computer program product comprises a non-transitory, computer-readable medium containing instructions therein. The instructions, when executed, cause the processor to perform generating a layout of a circuit in accordance with a floorplan of the circuit; and storing the generated layout in a cell library or using the generated layout to generate a layout for an integrated circuit (IC) containing the circuit. The generating the layout comprises obtaining a first layout block and a second layout block. The first layout block includes a first region corresponding to a first portion in the floorplan, and a border region. The second layout block includes a second region corresponding to a second portion in the floorplan, and a border region identical to the border region of the first layout block. The generating the layout further comprises combining the first layout block and the second layout block by overlapping the border region of the first layout block with the identical border region of the second layout block, resulting in a combined layout block of the layout of the circuit. The combined layout block comprises the first region and the second region on opposite sides of the border region.