A high performance ceramic block for use with small-scale circuitry is described. The block can be used in an optical sub-assembly (OSA) suitable for optical interconnection with optical fibers and electrical interconnection with a chip sub-assembly (CSA) is formed. The block includes a first surface and a second surface and is formed using one of low temperature co-fired ceramic (LTCC) and high temperature co-fired ceramic (HTCC) techniques. Photonic devices are formed on the first surface of the ceramic block and electrical contacts are formed on a second surface of the block. The electrical contacts being suitable for electrical communication with a chip sub-assembly. Electrical connections are formed so that they pass internally through the ceramic block to electrically interconnect the photonic devices on the first face of the block with the electrical contacts on the second face of the block. Such a block can be advantageously used to form an optoelectronic module.

FIELD OF THE INVENTION

The present invention relates generally to techniques for connecting the optical and electrical device components. More particularly, the invention relates to LTCC (low temperature co-fired ceramic) structures for use in optical subassemblies.

BACKGROUND OF THE INVENTION

Many computer and communication networks being built today, including the Internet, are using fiber optic cabling instead of copper wire. With fiber optic cabling, data is transmitted using light signals, not electrical signals. For example, a logical one may be represented by a light pulse of a specific duration and frequency, a logical zero may be represented by the absence of a light pulse for the same duration. Optical fiber has the advantage of having a much greater bandwidth than copper wire.

While fiber optic cabling is very efficient for transferring data, the use of light signals to process data is still very difficult. For instance, currently there is no efficient way to “store” light signals representative of data. Networks therefore use fiber optics for transmitting data between nodes and silicon chips to process the data within computer nodes. This is accomplished by using fiber optic transceivers, which convert light signals from a fiber optic cable into electrical signals, and vice versa.FIG. 1illustrates a perspective view of an exemplary optoelectronic module100that can be used to form an optical transceiver.

Optoelectronic module100includes a semiconductor chip subassembly (CSA)102and an optical subassembly (OSA)104. CSA102is a packaged semiconductor device. As shown inFIG. 1, CSA102is a rectangular block of molding material106that has electrical contacts108exposed through its bottom and side surfaces. Within the block of molding material106is a semiconductor die that is electrically connected to contacts108. For instance, wire bonds can be used for such connections. Another aspect of CSA102that cannot be seen is the up-linking contacts on the top surface of CSA102. These up-linking contacts are also electrically connected to the encapsulated semiconductor die and therefore provide the electrical communication between the semiconductor die and OSA104. The specific CSA102that is shown is a leadless leadframe semiconductor package (LLP). However, it should be understood that CSA102can be formed of various types of molded packages.

A conventional OSA104includes a conventional backing block110, a circuitry substrate112, and photonic devices114. Backing block110has a front surface116that supports circuitry substrate112and photonic devices114, which are attached to circuitry substrate112. A conventional backing block110can be formed of a variety of materials such as a ceramic material, polyethylene ether ketone (PEEK), or liquid crystal polymer (LCP). Examples of such conventional OSA's104and backing blocks104are known to persons having ordinary skill in the art. One typical example of such a conventional backing block is described, for example, in the U.S. patent application Ser. No. 10/165/711, entitled “CERAMICOPTICALSUB-ASSEMBLYFOROPTO-ELECTRONICMODULES,” filed on Jun. 6, 2002.

In conventional implementation, a circuitry substrate112is attached to a front surface116of backing block110, wraps around the bottom-front corner of backing block110, and covers most of the bottom surface of backing block110. Traces of the circuitry substrate112run from photonic devices114on the front surface to the bottom surface of backing block110where they make contact with the up-linking contacts of CSA102. In an effort to maximize the number of electrical connections possible, size dimensions of the foregoing devices are small. However, even though the size dimensions are made small, the fact that the circuitry substrate112is formed only at the surface (or in some implementations two layers deep) of the backing block110limits the overall number of electrical connections that can be made from the photonic devices114to contacts of the CSA102.

Additionally, such surface mounted circuitry substrates112can suffer from “cross-talk”. In typical implementation, size dimensions involved with circuitry substrate112are small and cause the circuit traces to be positioned very close to each other. The small size is advantageous in the same way that small sizes for most electronic devices are advantageous. However, the close proximity of the traces can cause “cross-talk,” especially at high operational frequencies. Cross-talk is the electrical interference between two or more electrically conducting elements. Such cross-talk can drastically reduce the performance of optoelectronic device100.

FIG. 2is a schematic depiction of a conventional backing block204(depicted upside down) showing a bottom side201and a facing side202. Commonly, the photonic devices214are formed on the facing side202of the block204and electrically connected to contact pads215on the bottom side201. The photonic devices214are electrically connected to contact pads215using surface metallization techniques. Typically, the photonic devices214are electrically connected to contact pads215using electric traces (or leads)216formed on a special contact tape that adheres to the block204. A problem with this implementation is that the electric traces216have a tendency to fail in the region where the tape bends over the edge217of the block204.

In view of the foregoing, what is needed is an efficient technique for forming high density electrical connections from the photonic devices of an optical device to an associated semiconductor chip device such that the connections exhibit high circuit density and low levels of cross-talk.

BRIEF SUMMARY OF THE INVENTION

The present invention is directed to a high performance and small-scale circuitry substrate and supporting block used in optical sub-assemblies. In one embodiment an optical sub-assembly (OSA) suitable for optical interconnection with optical fibers and electrical interconnection with a chip sub-assembly (CSA) is formed. The OSA includes a ceramic block having a first surface and a second surface, the ceramic block being formed using one of low temperature co-fired ceramic (LTCC) and high temperature co-fired ceramic (HTCC) techniques. Photonic devices are formed on the first surface of the ceramic block and electrical contacts are formed on a second surface of the block. The electrical contacts being suitable for electrical communication with a chip sub-assembly. Moreover, the electrical connections being formed so that they pass internally through the ceramic block to electrically interconnect the photonic devices on the first face of the block with the electrical contacts on the second face of the block.

Another embodiment includes a ceramic block having a first face and a second face. The block being formed using one of low temperature co-fired ceramic (LTCC) and high temperature co-fired ceramic (HTCC) techniques. The first face of the ceramic block has at least one photonic device formed thereon. Contact pads are formed on the second face of the ceramic block. The block also includes electrical connections that are electrically connected to the photonic devices and pass through internal portions of the ceramic block to so that the electrical connections can electrically the photonic devices to a chip sub-assembly (CSA). The electrical connections can include both signal connections and ground connections. Moreover, embodiments can include internal shielding layers. The configuration of the block can be designed so that cross-talk is reduced, low levels of ground-bounce and electrical parasitics are exhibited, and optimal impedance levels can be obtained. The circuitry substrate can be advantageously used to form an optical sub-assembly (OSA) used in an optoelectronic module.

In another embodiment, the ceramic block includes a plurality of ceramic layers formed using one of low temperature co-fired ceramic (LTCC) techniques and high temperature co-fired ceramic (HTCC) techniques. The ceramic block includes a front surface and a bottom surface. The front surface of the block includes a plurality of contact pads with a plurality of photonic devices. The bottom surface includes a plurality of solder pads. The block further includes internal electric contact planes having at least one electric contact line formed thereon such that the at least one electric contact line passes internally through the ceramic block and is in electrical communication with the contact pads and associated solder pads. The contact pads having wire bonds for electrically connecting the contact pads with the photonic devices. The block also includes at least one internal ground plane having at least one ground contact line formed thereon such that the at least one ground contact line passes internally through the ceramic block and is in electrical communication with selected solder pads. The module further including a semiconductor chip sub assembly (CSA) having a top surface that has exposed up-linking contacts that are in electrical contact with the solder pads formed on the bottom surface of the ceramic block when the ceramic block is placed onto the top surface of the CSA.

It is to be understood that, in the drawings, like reference numerals designate like structural elements. Also, it is understood that the depictions in the Figures are not necessarily to scale.

DETAILED DESCRIPTION OF THE INVENTION

The present invention will now be described in detail with reference to a few preferred embodiments thereof as illustrated in the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without some or all of these specific details. In other instances, well known operations have not been described in detail so not to unnecessarily obscure the present invention.

One of the limitations of existing technologies used in optical sub-assemblies is the need to form all the electrical interconnections between the photonic devices and the underlying chip sub-assembly (CSA) using surface metallization techniques that form electrical interconnect structures that are one, or at most two layers deep. This results in limited electrical contact density and also results in enormous cross-talk problems between the various electrical interconnections. Cross-talk in existing technologies can run as high as 75%. Moreover, as data transmission rates increase, this problem will likely increase.

The present invention pertains to high performance and small-scale OSA's. An improved OSA of the present invention includes a ceramic block formed of several layers of low temperature co-fired ceramic (LTCC) or high temperature co-fired ceramic (HTCC). A photonic device, or more generally a plurality of photonic devices is formed on one face of the ceramic block. The photonic devices are electrically connected to a plurality of solder pads formed on another face of the ceramic block. Importantly, the electrical connections between the photonic devices and the solder pads pass through internal portions of the ceramic block. Such structures are made possible through the use of LTCC and HTCC technologies. The configuration of the electrical interconnections that pass through internal portions of the ceramic block are designed so that cross-talk is reduced, low levels of ground-bounce and parasitics are exhibited, and optimal impedance levels are obtained. An OSA incorporating such a ceramic block can be advantageously used to form an optoelectronic module.

To achieve the desired properties in a ceramic block constructed in accordance with the principles of the invention, multi-layered ceramic (MLC) fabrication technologies are used. Such technologies are described, for example, in Microelectronics Packaging Handbook, Van Nostrand Reinhold publishers, New York 1989, at pages 455–522 which provides for a thermally efficient, multi-component ceramic structures capable of supporting three-dimensional interconnect circuitry.

In general, such ceramic structures are formed using particles of high temperature withstanding dielectric material such as alumina and glass suspended in an organic binder and formed and dried into so-called “green sheets”. Individual sheets of tape are printed with metallization and other circuit patterns, stacked on each other, laminated together at a predetermined temperature and pressure, and then fired at an elevated temperature routine upon which the majority of the binder material vaporizes off while the remaining material fuses or sinters. Where alumina glass is generally used as the insulating material, tungsten, molybdenum or molymanganese or other suitable materials are typically used for metallization. The green sheets are patterned and then stacked in an appropriate configuration. The stacked laminates are then fired at temperatures of about 1,600° C. (degrees Celsius) in a reducing atmosphere such as hydrogen. This is known as high temperature co-fired ceramic (HTCC) technology. In a typical HTCC process, high-melting point refractory metal pastes are used as conductors.

Other ceramic laminate processes that do not require high processing temperatures or a hydrogen atmosphere are referred to generally, as low temperature co-fired ceramic (LTCC) technology. Low temperature ceramic tape is commercially available from DuPont Company as a GREEN TAPE brand ceramic tape which sinters at approximately 850° C. and exhibits thermal expansion similar to alumina. The low temperature processing permits the use of highly conductive precious metal thick film conductors such as gold, silver or their alloys.

A discussion of thick film technology, and high and low temperature co-fired ceramic tape technology is found in “Development of a Low Temperature Co-fired Multilayer Ceramic Technology”, by William Vitriol et al., ISHM Proceedings 1983, pages 593–598.

Although both HTCC and LTCC technologies can be used in accordance with the principles of the invention, LTCC technology is the preferred implementation.

Ceramic components can be constructed using such HTCC and LTCC techniques. For example, a ceramic block can be constructed and used to connect various types of electrical systems of an opto-electronic module. The advantages of such a ceramic block are more fully evident when connecting electrical systems at a small dimensional scale. For instance, the block can be used to connect an optical device to a semiconductor chip device in an optoelectronic module.FIG. 3will now be described to explain such a use of such a ceramic block.

FIG. 3comprises schematic depictions of a simplified optical subassembly (OSA)300and a chip subassembly (CSA)302, according to one embodiment of the present invention. OSA300and CSA302can be combined to form an optoelectronic module. OSA300and CSA302are placed in electrical connection with each other by connecting the up-linking contacts304on the top surface of CSA302with the contact pads (not shown in this view) on the bottom surface of OSA300. These connections can be facilitated by the use of conductive materials including, but not limited to, solder paste and conductive epoxy.

A CSA302is a packaged semiconductor device (substantially similar to the CSA102described inFIG. 1) in which a semiconductor die (not shown) is encapsulated within a molding material308and electrically connected to up-linking contacts304. Up-linking contacts304provide the path for electrical communication between the semiconductor die with the photonic devices312of OSA300.

An OSA300includes a ceramic block314(also referred to herein as a ceramic body) having a front surface318and a bottom surface320. Typically, a device attachment area332is formed on the front surface318. The device attachment area332is also referred to as a cathode pad. Photonic devices312are attached to the front surface318of the ceramic block314at the device attachment area332. Also, the front surface318includes contact pads338formed thereon. Wire bonds333electrically contact the photonic devices312to the contact pads338. Signal connections322that pass through internal portions of the ceramic block314(depicted schematically by the dashed internal lines) electrically connect the bond pads338to solder pads (not seen in this view). In this way the photonic devices312can be connected to the up-linking contacts304of a chip sub-assembly (CSA)302so that they can ultimately be connected to the semiconductor die within CSA302.

To better illustrate the structure and features of a ceramic block embodiment and its associated electrical connections, discussion of ceramic block embodiment will be made with reference to FIGS.3and4A–C. WhileFIG. 3shows a ceramic block embodiment314in a perspective view,FIGS. 4A–Cillustrate a ceramic block embodiment314in a cross-section side view, a front plan view that looks onto front surface318of ceramic block314, and a bottom plan view that looks onto bottom surface320of ceramic block314, respectively.

Referring toFIGS. 4A,4B, and4C one implementation of a ceramic block OSA is depicted.FIG. 4Ais a cross-section view,FIG. 4Bis a plan view of a facing surface, andFIG. 4Cis a plan view of a bottom surface. Referring toFIG. 4A, ceramic block314is constructed from a plurality of ceramic layers350. The front surface318of the depicted block314includes a device attachment area332having photonic devices312formed thereon. Additionally, the depicted embodiment has contact pads338formed on the front surface318and contact pads306(herein such pads306are differentiated from the contact pads338of the front surface318by referring to them as solder pads306) formed on the bottom surface320. The contact pads338are electrically connected to contact points on the photonic devices312. Typically, such connections are achieved using wire connectors333that are typically formed of gold but can comprise any suitably conductive material. Underlying the depicted contact pad338is a signal connection that passes through internal portions of the ceramic block318. The signal connection being formed to facilitate an electrical connection between the photonic device and the uplinking contacts304of a chip sub-assembly (CSA). In the depicted embodiment, the signal connection includes a signal via351, a signal trace352, a corresponding contact pad338, and a corresponding solder pad306. The signal via351is formed by metallizing an opening in one or more ceramic layer(s)350. Additionally, an associated signal trace352is formed on a ceramic layer350. The signal via351is electrically connected to the associated signal trace352. The signal via351is electrically connected to a corresponding contact pad338and the signal trace352is electrically connected to a corresponding solder pad306. The signal via351, contact pad338, signal trace352, and solder pad306are typically formed of copper materials. However, many other conductive materials may be readily used.

Underlying the device attachment area332and photonic devices312formed thereon is a ground connection that passes through internal portions of the ceramic block318. The ground connection being formed to facilitate an electrical connection between the photonic device uplinking contacts304of a chip sub-assembly (CSA). In the depicted embodiment, the ground connection includes a ground via361and a ground line362. The ground connection is electrically connected to the device attachment area332(and thereby to an associated photonic device312) and a corresponding solder pad306. Thus, a ground connection electrically interconnects a photonic device312to uplinking contacts304of a chip sub-assembly (CSA). The ground via361is formed by metallizing an opening in one or more ceramic layer(s)350and an associated ground line362is formed on a ceramic layer350. As with the signal connection, the ground via361, ground line362, and solder pad306are typically formed of copper materials. However, many other conductive materials may be readily used.

It is to be noted that the ground line362can comprise a single ground line to which all the photonic devices312are electrically connected and thereby grounded. Alternatively, and advantageously, the ground line362can comprise a plurality of ground lines so that each photonic device312can be individually grounded. Such an implementation can provide superior resistance to cross-talk.

Another embodiment of the invention is depicted with respect toFIGS. 5A–5B. Such an embodiment implements an alternating contact pad configuration.FIG. 5Ais a cross section view of a ceramic block embodiment.FIG. 5Bis a plan view of a face surface of the ceramic block embodiment depicted inFIG. 5A. The cross-section view ofFIG. 5Ais taken along the line A–A′ ofFIG. 5B. As with the previously disclosed embodiments the depicted ceramic block514can be used in an optical subassembly (OSA) used in an opto-electronic module.

The ceramic block514has a front surface518and a bottom surface520. The depicted embodiment includes a device attachment area532(cathode pad) is formed on the front surface518. Photonic devices512are formed at the device attachment area532. Additionally, contact pads are formed on the front surface518of the block514. In the depicted implementation, the contact pads include a first set of contact pads538and a second set of contact pads539. The first set of contact pads538and second set of contact pads539are configured in a staggered arrangement with respect to each other. This is more easily seen with reference toFIG. 5Bwhich depicts the offset staggered configuration of the contact pads538of the first set of contact pads with respect to the contact pads539of the second set of contact pads. Such a configuration allows more separation between the contact wires533that connect the photonic devices512to the contact pads538,539. This increased separation reduces cross-talk. This feature becomes extremely advantageous in embodiments having many photonic devices512. In general, where n photonic devices are employed, a first set of n/2 bond pads are formed on one side of the photonic devices and a second set of n/2 other bond pads are formed on an opposing side of the photonic devices

As with the previously described embodiments, the front surface518includes contact pads538,539formed thereon. For the first set of bond pads538, signal connections pass through internal portions of the ceramic block514to electrically connect the first set of contact pads538to the solder pads306formed on the bottom surface520of the block. In this way the photonic devices512can be connected to the up-linking contacts of a chip sub-assembly (CSA) and ultimately be connected to the associated semiconductor die within the CSA. As previously described, the signal connections include signal vias, signal traces, and corresponding contact pads and solder pads. Referring toFIG. 5A, a contact pad538includes a signal via551that passes through one or more ceramic layers550of the block514. The signal via551is electrically connected to a signal trace552formed on one of the ceramic layers550. The signal trace552extends to edge of the block514at the bottom surface520where a solder pad506is formed thereon. Similarly, for the second set of bond pads539, signal connections pass through internal portions of the ceramic block514to electrically connect the second set of bond pads539to the solder pads306formed on the bottom surface520of the block. The signal connection for contact pad539includes a signal via561that passes through one or more ceramic layers550of the block514and electrically connects to a signal trace562formed on one of the ceramic layers550. Signal trace562extends to the bottom surface520of the block514where a solder pad506is formed thereon. In the depicted embodiment, a single ground is used.

Additionally, the block514includes ground connections that pass through internal portions of the ceramic block514. As previously described, each ground connection is electrically connected to the device attachment area532(and thereby to an associated photonic device512) and a corresponding solder pad506. Thus, a ground connection electrically interconnects a photonic device512to uplinking contacts of a chip sub-assembly (CSA). A ground via571is formed in one or more ceramic layer(s)550and an associated ground line572is formed on a ceramic layer550. It is to be noted that the depicted ground line572can comprise a single ground line to which all the photonic devices512are electrically connected and thereby grounded. Alternatively, and advantageously, the ground line572can comprise a plurality of ground lines so that each photonic device512can be individually grounded.

Another embodiment of the invention is depicted with respect toFIGS. 6A–6C.FIG. 6Ais a cross section view of a ceramic block embodiment.FIG. 6Bis a plan view of a face surface of the ceramic block embodiment depicted inFIG. 6A. The cross-section view ofFIG. 5Ais taken along the line6a–6a′ ofFIG. 6B. As with the previously disclosed embodiments the depicted ceramic block614can be used in an optical subassembly (OSA) used in an opto-electronic module.

The ceramic block614has a front surface618and a bottom surface620. The depicted embodiment includes a device attachment area632(cathode pad) formed on the front surface618with photonic devices612formed thereon. Contact pads638,639are formed on the front surface618and are electrically connected to the photonic devices612using bonding wires633. As depicted inFIG. 6B, in this embodiment the contact pads include a first set of contact pads638and a second set of contact pads639configured in an offset staggered arrangement with respect to each other. In such an implementation, the photonic devices612can be implemented as a first set of photonic devices612′ and a second set of photonic devices612″ which are electrically connected to a first set of contact pads638and a second set of contact pads639respectively. This configuration allows more separation between the contact wires633thereby reducing cross-talk.

As with the previously described embodiments, the signal connections that connect the photonic devices612to the solder pads606are formed as described elsewhere in this patent. Such signal connections pass through internal portions of the ceramic block614to electrically connect the photonic devices612to the solder pads606formed on the bottom surface620of the block. As previously described, the signal connections include signal vias651, signal traces652, and corresponding contact pads638and solder pads606. Referring toFIG. 6A, a signal connection to a contact pad638includes a signal via651that passes through one or more ceramic layers650of the block614. The signal via651is electrically connected to a signal trace652formed on one of the ceramic layers650. The signal trace652extends to the edge of the block614at the bottom surface620where a solder pad606is formed thereon. Similarly, for the second set of bond pads639, signal connections pass through internal portions of the ceramic block614to electrically connect the second set of bond pads639to the solder pads606formed on the bottom surface620of the block. The signal connection for contact pad639includes a signal via681(depicted by the indicated dashed line) that passes through one or more ceramic layers650of the block614and electrically connects to a signal trace682(depicted by the indicated dashed line) formed on one of the ceramic layers650. The signal trace682extends to the bottom surface620of the block614where a solder pad606is formed thereon.

The depicted embodiment uses two grounds. Both grounds pass through internal portions of the ceramic block614. The ground connections electrically connect the photonic devices612to an associated solder pad606. In the depicted embodiment, a first set of photonic devices612′ associated with the first set of bond pads638is contacted to a first ground line672. A first ground via671is electrically connected to the first set of photonic devices612′ at the device attachment area632and also to a first ground line672. The first ground line672is electrically connected to a corresponding solder pad606. Thus, a first ground connection electrically interconnects a photonic device612to uplinking contacts of a chip sub-assembly (CSA). It is to be noted that the depicted ground line672can comprise a single ground line to which all the first photonic devices612′ are electrically connected and thereby grounded. In such an implementation the single ground line672is formed on a ceramic layer650thereby defining a first ground plane601. Alternatively, and advantageously, the first ground line672can comprise a plurality of individual ground lines so that each photonic device612′ can be individually grounded.

Also, the second ground passes internally through the ceramic block614. A second set of photonic devices612″ associated with the second set of bond pads639is contacted to a second ground line662. Such ground connections electrically connect the photonic devices612″ to an associated solder pad606. A second ground via661is electrically connected to the second set of photonic devices612″ at the device attachment area632and also to a second ground line662. The second ground line662is electrically connected to a corresponding solder pad606. Thus, a second ground connection electrically interconnects a photonic device612″ to uplinking contacts of a chip sub-assembly (CSA). It is to be noted that the depicted second ground line662can comprise a single ground line to which all the second photonic devices612″ are electrically connected and thereby grounded. In such an implementation the single ground line662is formed on a ceramic layer650thereby defining a second ground plane602. A described previously, second ground line662can comprise a plurality of individual ground lines so that each photonic device612″ can be individually grounded.

Optionally, a shield plane690can be introduced between the two sets of electrical connections for the first set of photonic devices612′ and the second set of photonic devices612″. The shield plane690includes a shield layer699of metallic material formed to reduce the cross-talk between the first set of photonic devices612′ and the second set of photonic devices612″. Such a shield plane690includes openings to facilitate the vias passing through the shield plane690. This can be illustrated with respect toFIG. 6C.FIG. 6Cdepicts an embodiment for a shield layer699in accordance with the principles of the invention. The depicted shield layer699includes openings700,701that allow vias and electrical connections to pass. For example, openings700permit the passage of ground vias661and openings701permit the passage of signal vias681. Additionally, in embodiments where each photonic devices include an individual ground connection and an individual signal connection, such shielding can be formed about each pair of signal and ground connections.

Referring toFIG. 7, block embodiments encompass implementations wherein the spacing pitch between the contact pads702of a set of contact pads is greater than the spacing pitch between individual photonic devices703of an associated set of photonic devices. Thus, the associated electrical connections704(e.g., gold bonding wires) are shown to fan outwards as they extend away from photonic devices703toward the contact pads702. They extend outwards such that each of contact pads702separated from each other by a distance greater than the distance between each of photonic devices703. This fanned-out configuration increases the ability to shield each of electrical connections704from each other since the distance between each of the connections is increased. The greater distance between each of contact pads702also allows greater room for forming contacts with up-linking contacts on a CSA. Specifically, more room is provided for solder ball interconnects.

One specific implementation of the principles of the present invention is a two channel opto-electronic transceiver. A simplified implementation of such a transceiver is schematically depicted inFIG. 8. Such a transceiver is formed on an OSA800that includes a ceramic block810formed using HTCC or LTCC processes. The block810includes a send channel that includes an optical emitter photonic device801(e.g., a semiconductor laser device) and a receive channel that includes an optical receiver photonic device802. The photonic devices (801,802) are arranged in a standard MPO format for interface with standard fiber optic ferrule devices. The embodiment can include shielding to additionally reduce cross-talk. The photonic devices (801,802) are electrically connected to the contact pads803. Additionally, the contact pads803are electrically connected to the solder pads804by electrical connections805(depicted schematically by the dashed lines) that pass through the inside of the block810. In the depicted embodiment, two ground planes are used and ground connections electrically connect the ground to solder pads808by ground electrical connections806(depicted schematically by the dashed lines) that are also depicted as passing through the inside of the block810. Shielding may also optionally be employed. The CSA820includes electrical up-link connections821that can be electrically connected to the solder pads804,808of the OSA to electrically interconnect the photonic devices801,802of the OSA800to a semiconductor chip (not shown) encapsulated within the CSA820.

The embodiments of the present invention provide the advantages of less crosstalk, reduced parasitics, reduced ground-bounce effect, increased connection density, and it makes it easier to control the impedance levels. In one embodiment, total crosstalk of the order of 2.5% can be obtained on a 12-channel module (12 emitters or detectors or combination thereof) at 3.125 Gbps data transmission rate. Various electrical performance characteristics can be achieved by adjusting the spacing of between the contact pads, the width of the electrical connections, the size and spacing of all components as determined by the size of the ceramic blocks.

The OSA of the present invention can be manufactured to various size and performance specifications and therefore is suitable for use with many different connectors and systems. For instance, the OSA is compatible with an MPO connector, which can be implemented with 2-fiber or 12-fiber ribbons (as well as other well known sizes and configurations). The circuitry substrate of the invention can be used in various applications for connecting two electrical systems. Again, the circuitry substrate can advantageously be used with systems that are very small because of its small size, low cost, and excellent electrical performance.

Referring now toFIG. 9A, a ceramic body can made using LTCC or HTCC processing steps well-known in the microelectronic packaging industry. A plurality of ceramic sheets910,920,930,940,950,960, and970are processed together to form the desired ceramic body. The depicted ceramic body is structured to include a shield layer, signal connections, and ground connections. For example, the top layer910is to be the front surface of the body. Photonic devices and alternating contact pads will be formed thereon. The sheet910may then be stamped or punched to form a preform having vias into which are placed electrically conductive material such as metal paste or epoxy doped with electrical conductivity enhancing material such as silver to form conductive vias91,92,93,94in the sheet910. These regions are sized and located to correspond with desired circuit patterns. For example, here via93corresponds to an electrical interconnection structure that will be used for a signal interconnection for a first photonic device. A contact pad will be formed over the metal of via91. Vias92and93will be used for a ground connections that will pass deeper into the body. A device attachment area can later be formed over the vias92and93. Via94is used for another signal connection. Layer920includes further conductive vias that underlie vias91,93, and94. Additionally, a signal trace95is formed extends all the way to the edge of sheet920. The signal trace95underlies and electrically connects to the via91. Layer930includes further conductive vias that underlie vias93and94. Additionally, a ground line96is formed extends all the way to the edge of sheet930. The ground line96underlies and electrically connects to the via92. Layer940includes a shield layer97that includes openings so that further conductive vias can be formed that that underlie vias93and94. The shield layer97is constructed of conductive material (e.g., copper) and is configured so that it does not contact the conductive materials underlying vias93and94. Layer950includes a further conductive via that underlies via93. Additionally, a signal trace98is formed such that it extends all the way to the edge of sheet950. The signal trace98underlies and electrically connects to the via94. Layer960includes a ground line99is formed extends all the way to the edge of sheet960. The ground line99underlies and electrically connects to the via93. Finally, a bottom sheet970can be used under the other sheets. Typically, the sheets are bonded together by bonding materials such as epoxy. Preferably, a B-stage type electrically non-conductive material is selected. In this way, sensitive circuit paths may be routed in the body.

FIG. 9Bdepicts an edge on view of the body900after assembly and sintering. A device attach pad902has been formed on the facing surface of the body900and two photonic devices903,904have been formed on the device attach pad902. Contact pads (only the nearest pad905being visible in this view) are also formed on the facing surface of the body900. The edges of the conductive lines (95,96,98, and99) are exposed on the bottom surface of the body. Solder pads901are formed over the edges of the conductive lines (95,96,98, and99). Later solder balls can be formed on the solder pads901which are then reflowed to the uplink contacts of an associated CSA to complete an opto-electronic module.