SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SAME

The semiconductor device is formed in the form of a GaN-based stacked layer including an n-type drift layer 4, a p-type layer 6, and an n-type top layer 8. The semiconductor device includes a regrown layer 27 formed so as to cover a portion of the GaN-based stacked layer that is exposed to an opening 28, the regrown layer 27 including a channel. The channel is two-dimensional electron gas formed at an interface between the electron drift layer and the electron supply layer. When the electron drift layer 22 is assumed to have a thickness of d, the p-type layer 6 has a thickness in the range of d to 10d, and a graded p-type impurity layer 7 whose concentration decreases from a p-type impurity concentration in the p-type layer is formed so as to extend from a (p-type layer/n-type top layer) interface to the inside of the n-type top layer.

DESCRIPTION OF EMBODIMENTS

FIG. 1is a sectional view showing a semiconductor device10according to an embodiment of the present invention. In this semiconductor device10, an opening28is formed so as to extend from a surface of a GaN-based semiconductor layer constituted by (GaN-based substrate1/buffer layer2/n−-type drift layer4/p-type barrier layer6/n+-type contact layer8) and reach the n−-type drift layer4. The n+-type contact layer8is an alternative name given to an n-type top layer8and is used when the arrangement of an electrode is emphasized. When a top layer of a stacked layer is emphasized, the n+-type contact layer8is also referred to as an n+-type cap layer. The p-type barrier layer6is an alternative name given to a p-type layer6and is used to emphasize a barrier layer against electrons. The n−-type drift layer4serves as an n-type drift layer4.

A regrown layer27including an electron drift layer22and an electron supply layer26is formed so as to cover a portion of the GaN-based semiconductor layer, the portion being exposed to the opening28. A gate electrode G is formed above the regrown layer27with an insulating layer9disposed therebetween. A source electrode S is formed on the GaN-based semiconductor layer so as to be in contact with the electron drift layer22and the electron supply layer26. A drain electrode D is disposed so as to face the source electrode S, with the n−-type drift layer4and the like sandwiched therebetween. Two-dimensional electron gas (2DEG) is formed at an interface between the electron drift layer22and the electron supply layer26. The 2DEG constitutes a channel of a vertical electric current flowing between the source electrode and the drain electrode.

The features of the semiconductor device10according to this embodiment are that (1) when the electron drift layer22is assumed to have a thickness of d, the p-type barrier layer6has a thickness in the range of d to 10d and (2) a graded p-type impurity layer7whose concentration decreases from the p-type impurity concentration in the p-type barrier layer6is formed so as to extend from a (p-type barrier layer6/n+-type contact layer8) interface to the inside of the n+-type contact layer8.

FIG. 2Ais an enlarged sectional view showing the regrown layer27and (n−-type drift layer4/p-type barrier layer6/n+-type contact layer8) at the side surface of the opening28in the semiconductor device10shown inFIG. 1.FIG. 2Bis a diagram showing the distribution of a p-type impurity concentration in a thickness direction. InFIG. 2A, the thickness of the electron drift layer22is represented by d. As described above, when the electron drift layer22is assumed to have a thickness of d, the p-type barrier layer6may have a thickness in the range of d to 10d. The graded p-type impurity layer7may have a thickness in the range of 0.5d to 3.5d.

Focusing on the type of main p-type impurity such as Mg that makes the p-type barrier layer6function as a p-type layer, as shown inFIG. 2B, the thickness of the graded p-type impurity layer7is defined as the thickness from the (p-type barrier layer6/n+-type contact layer8) interface to a portion having a background concentration of Mg in the n+-type contact layer8. For example, the Mg concentration at the (p-type barrier layer6/n+-type contact layer8) interface is equal to the Mg concentration in the p-type barrier layer6, which is about 5×1018(5E+18) (cm−3). The background concentration of Mg in the n+-type contact layer8is, for example, about 1×1016(1E+16) (cm−3). The thickness between the (p-type barrier layer6/n+-type contact layer8) interface and the face (point) at which the Mg concentration of the graded p-type impurity layer7intersects the background concentration of Mg in the n+-type contact layer8corresponds to the thickness of the graded p-type impurity layer7.

By arranging the thin p-type barrier layer6and the graded p-type impurity layer7, the following effects can be provided.

(E1) Since the p-type barrier layer6has a thickness in the range of d to 10d, the length of a channel can be reduced to 10d or less while satisfactory breakdown voltage characteristics are achieved, which can decrease the on-resistance.

(E2) The presence of the graded p-type impurity layer7can improve the breakdown voltage characteristics compared with the case where the p-type barrier layer6alone is disposed. Although the p-type layer alone can provide satisfactory breakdown voltage characteristics, an allowance or a safety margin for the breakdown voltage characteristics can be obtained by the presence of the graded p-type impurity layer7. Furthermore, since the graded p-type impurity layer7is formed so as to penetrate the n-type top layer, the graded p-type impurity layer7does not directly contribute to an increase in the on-resistance or hardly affects the on-resistance.

(E3) In particular, when the thickness of the p-type barrier layer6is decreased in order to decrease the on-resistance, a leakage current flowing from the n+-type contact layer8to the n−-type drift layer4through the electron drift layer (normally, i-type GaN layer)22is easily generated. However, since the graded p-type impurity layer7penetrates the n+-type contact layer8, the n+-type contact layer8substantially occupies a region that has retreated away from the p-type barrier layer6(thin shape formed by the retreat toward the surface) or the thickness of the p-type barrier layer6substantially increases. Therefore, the generation of a leakage current flowing via the electron drift layer22can be suppressed. The graded p-type impurity layer7serves as a resistance to such a leakage current path.

In summary, a decrease in the thickness of the p-type layer (E1) decreases the on-resistance and at the same time the graded p-type impurity layer7(E2) improves the breakdown voltage characteristics and (E3) suppresses the generation of a leakage current.

It is assumed that the graded p-type impurity layer7does not penetrate at least a region of the n+-type contact layer8close to the surface. That is, in at least a region of the n+-type contact layer8close to the surface, the p-type impurity concentration of the graded p-type impurity layer7is decreased to the background level (e.g., 1×1016cm−3).

FIG. 3is a plan view of a chip in which the semiconductor device is formed and shows which part of the chip the sectional view ofFIG. 1corresponds to. As shown inFIG. 3, the opening28and the gate electrode G have a hexagonal shape and a region around the opening28and gate electrode G is substantially covered with the source electrode S while the source electrode S does not overlap a gate wiring line12. Consequently, a closest-packed structure (honey-comb structure) is formed and thus the gate electrode has a long perimeter per unit area, that is, the on-resistance can be decreased. An electric current flows through a path of source electrode S→channel in the regrown layer27→n−-type drift layer4→drain electrode D. The gate electrode G, the gate wiring line12, and a gate pad13constitute a gate structure. In order to prevent the source electrode S and the wiring line thereof from interfering with the gate structure, the source wiring line is disposed on an interlayer-insulating layer (not shown). A via hole is formed in the interlayer-insulating layer, and the source electrode S including a conductive plug is conductively connected to a source conductive layer (not shown) on the interlayer-insulating layer. As a result, a source structure including the source electrode S can have low electrical resistance and high mobility, which are suitable for high-power devices.

The perimeter of the opening per unit area can also be increased by densely arranging elongated openings instead of employing the hexagonal honey-comb structure. Consequently, the current density can be improved.

A method for producing the semiconductor device10according to this embodiment will now be described. As shown inFIG. 4A, a GaN-based stacked layer including n−-type GaN drift layer4/p-type GaN layer6/n+-type GaN contact layer8is epitaxially grown on a GaN substrate1corresponding to the above-described GaN substrate. A GaN-based buffer layer may be inserted between the GaN substrate1and the n−-type GaN drift layer4.

The formation of the above layers is performed by, for example, metal-organic chemical vapor deposition (MOCVD). Instead of the MOCVD, molecular beam epitaxy (MBE) may be employed. Thus, a GaN-based semiconductor layer having good crystallinity can be formed. In the case where the GaN substrate1is formed by growing a gallium nitride film on a conductive substrate using MOCVD, trimethylgallium is used as a gallium raw material. High-purity ammonia is used as a nitrogen raw material. Purified hydrogen is used as a carrier gas. The purity of the high-purity ammonia is 99.999% or more and the purity of the purified hydrogen is 99.999995% or more. A hydrogen-based silane is used as a Si raw material for an n-type dopant and cyclopentadienyl magnesium is used as a Mg raw material for a p-type dopant. A conductive GaN substrate having a diameter of two inches is used as the substrate. The substrate is cleaned at 1030° C. at 100 Torr in an atmosphere of ammonia and hydrogen. Subsequently, the temperature of the substrate is increased to 1050° C. and a gallium nitride layer is grown at 200 Torr at a V/III ratio of 1500, which is the ratio of the nitrogen raw material and gallium raw material.

The n−-type GaN layer4/p-type GaN layer6/n+-type GaN layer8are grown on the GaN substrate1in that order. A method for forming the graded p-type impurity layer7that extends from the (p-type GaN layer6/n+-type GaN layer8) interface to the inside of the n+-type GaN layer8is described below.

(S1) When the growth of the p-type GaN layer6is switched to the growth of the n+-type GaN layer8, the initial temperature in the growth of the n+-type GaN layer8is increased to facilitate the diffusion of a p-type impurity such as Mg from the p-type GaN layer6to the n+-type GaN layer8.

(S2) In the growth of the n+-type GaN layer8, the amount of a p-type dopant introduced, such as cyclopentadienyl magnesium serving as a raw material of Mg, is adjusted to be equal to that in the case of the p-type barrier layer6for an initial short time of the growth of the n+-type GaN layer8and is then decreased in a gradient manner.

The concentration gradient of the p-type impurity of the graded p-type impurity layer7may be 30 nm/decade to 300 nm/decade. A concentration gradient of the p-type impurity of more than 300 nm/decade is not significantly different from an increase in the thickness of the p-type layer, which increases the risk of increasing the on-resistance. A concentration gradient of less than 30 nm/decade provides only a local effect in a thin region, and it is difficult to improve the breakdown voltage characteristics and suppress the generation of a leakage current.

As shown inFIG. 4B, an opening28is formed by etching. In this etching of the opening28, as shown inFIGS. 5A and 5B, a resist pattern Ml is formed on the top of epitaxial layers4,6, and8, and the resist pattern Ml is then etched by reactive ion etching (RIE) to cause the resist pattern Ml to recede, whereby an opening28is formed. Subsequently, the resist pattern Ml is removed and the wafer is cleaned. The wafer is inserted into an MOCVD apparatus and a regrown layer27including an electron drift layer22composed of undoped GaN and an electron supply layer26composed of undoped AlGaN is grown as shown inFIG. 4C. In the growth of the undoped GaN layer22and undoped AlGaN layer26, thermal cleaning is performed in an atmosphere of (NH3+H2), and then an organic metal material is supplied while (NH3+H2) is being introduced.FIG. 6shows a temperature-time pattern in the growth of the GaN layer22and AlGaN layer26.

Subsequently, the wafer is taken out of the MOCVD apparatus. An insulating layer9is grown as shown inFIG. 7A. A source electrode S and a drain electrode D are formed on the top surface of the epitaxial layer and the bottom surface of the GaN-based substrate1, respectively, by photolithography and ion beam deposition as shown inFIG. 7B. A gate electrode G is further formed on the side surface of the opening28.

Examples

The semiconductor device10shown inFIG. 7Bwas produced on the basis of the production method described in the above embodiment to investigate the presence (thickness and concentration gradient) of the graded p-type impurity layer7formed so as to extend from the p-type barrier layer6to the inside of the n+-type contact layer8. Members other than the graded p-type impurity layer7in the semiconductor device10are as follows. Mg was used as a p-type impurity of the p-type GaN barrier layer6. The graded p-type impurity layer7was formed on the basis of the above method (S1). That is, at the beginning of the formation of the n+-type cap layer8, the temperature was increased to 1050° C. to facilitate the diffusion of Mg into the n+-type cap layer8.

ReferringFIG. 6, the undoped GaN layer22was grown at 950° C. for a growth time of about 240 seconds so as to have a thickness of 0.1 μm. The undoped AlGaN layer26was grown at 1080° C. for a growth time of about 100 seconds so as to have a thickness of 0.02 μm. After the undoped AlGaN layer26was grown, the supply of an organic metal material was stopped and the temperature was decreased in a nitrogen atmosphere.

Subsequently, the semiconductor device10serving as a test specimen was etched in the depth direction from the surface of the n+-type cap layer8, and at the same time the concentration distribution of Mg in the depth direction was measured by secondary ion-microprobe mass spectrometry (SIMS).

FIG. 8is a diagram showing the concentration distribution of Mg in the depth direction, the concentration distribution being measured by SIMS. The graded p-type impurity layer (graded Mg-impurity layer)7is formed with a thickness of 0.22 μm. Since the electron drift layer22has a thickness of 0.1 μm (=d), the graded p-type impurity layer7has a thickness of 2.2d. The p-type barrier layer6has a thickness of 0.5 μm, which is a thickness of 5d. By forming the p-type layer6whose thickness is decreased and the graded p-type impurity layer (graded Mg-impurity layer)7, as described above, (E1) the on-resistance can be decreased, (E2) the breakdown voltage characteristics can be improved, and (E3) the generation of a leakage current can be suppressed.

The structures disclosed in the above embodiments of the present invention are mere examples and the scope of the present invention is not limited to these embodiments. The scope of the present invention is defined by the appended claims, and all changes that fall within the scope of the claims and the equivalence thereof are therefore embraced by the claims.

INDUSTRIAL APPLICABILITY

According to the present invention, a semiconductor device in which low on-resistance can be stably achieved while high vertical breakdown voltage is realized can be provided. Therefore, a high current can be controlled substantially without a loss.

REFERENCE SIGNS LIST