RIBBON SHIELD DEVICE AND METHOD

An electronic device and associated methods are disclosed. In one example, the electronic device includes one or more ribbon bond connections along with one or more wire bond connections. In one example, ribbon bond connections are shown, and are coupled to ground, and configured to provide a shielding effect to wire bond connections.

TECHNICAL FIELD

Embodiments described herein generally relate electronic devices, such as semiconductor devices. Some specific embodiments described relate to signal shielding technologies.

BACKGROUND

In operation, wire bond connections may carry high speed data signals. As device sizes continually shrink, and data speeds continually increase, challenges such as adjacent wire bond crosstalk become more pronounced. It is desirable to reduce negative effects such as adjacent wire bond crosstalk and electromagnetic interference (EMI). Configurations described below address these, and other technical challenges related to wire bond connections.

DESCRIPTION OF EMBODIMENTS

FIG.1shows an electronic device100. In one example, the electronic device100includes a memory device. One or more semiconductor dies110are shown coupled to a substrate102. The substrate102includes a number of solder bumps104that may be used to couple to a subsequent circuit board, such as a mother board (not shown). In the example ofFIG.1, a stack of memory dies110are shown in an offset configuration with the dies110being stacked with top edges of all dies110exposed. This offset configuration allows wire bonds to be attached to the exposed top surface portion of the dies110in the stack. In manufacturing of electronic devices such as device100, wire bond connections are fast at transmitting electrical signals, and are relatively inexpensive to manufacture. They are also easy to program for different connection configurations as device layout designs may change. In the example ofFIG.1, four different channels114are shown as channel A, B, C, and D. One or more different dies110can be wire bonded to different channels114. The use of multiple channels114allows each channel114to communicate with a selected number of dies110to best manage bandwidth and speed in communication. It is desirable to improve speed, reduce noise, and otherwise improve performance of communication between the channels114in the substrate102, and the dies110.

FIG.2shows an electronic device200. In the example ofFIG.2, the electronic device200includes multiple memory dies210coupled to a substrate202. Although memory dies are used as an example, the invention is not so limited. Other die types include, but are not limited to, processor dies, controller dies, mixed memory and processor dies, etc. In the example ofFIG.2, the dies210are offset from one another to permit top surface wire bonding. One example of an offset configuration is shown inFIG.2, although the invention is not so limited. other examples of offset die stacking include single stair stepped stacks, multiple stair stepped stacks going in different directions, etc.

A first channel substrate terminal214A and a second channel substrate terminal214B are shown. A number of wire bond connections220are shown coupled from the dies210to the channel substrate terminals214A,214B. In the example shown, the number of wire bond connections220include two separate rows of wire bond connections220from two adjacent dies in the offset stack going to respective channel substrate terminals214A,214B. The invention is not, however, limited to any one channel configuration or to offset dies, or to multiple die stacks.

In operation, wire bond connections220may carry high speed data signals. As device sizes continually shrink, and data speeds continually increase, challenges such as adjacent wire bond crosstalk become more pronounced. It is desirable to reduce negative effects such as adjacent wire bond crosstalk.

FIG.2further shows one or more vertical ribbon bond connections222from a die210to the substrate202. Ribbon bond connections include a flat cross section, with a thickness and a width that is wider than the thickness. In one example, a ribbon bond connection is formed by extruding a round cross section wire bond from a die, then rolling the round wire bond into a flattened cross section. In another example, a ribbon bond is extruded from a flat cross section die. In manufacturing, a robotic arm is used to locate an end of wire bond or ribbon bond connections, and the robotic arm moves from one end of a connection to another while extruding material to form the connections. In one example, a rotation axis on the robotic arm is added to allow a ribbon bond connection to be twisted as described in more detail below.

A ribbon bond connection can be oriented a number of ways. In one orientation, a width dimension is generally parallel to a major plane of the substrate202. This orientation can be defined as a horizontal ribbon bond. In another orientation, the width dimension can lie within a plane that is orthogonal to the major plane of the substrate202. This orientation can be defined as a vertical ribbon bond. In one example, a ribbon bond connection may include some portions along a ribbon bond length that are horizontal, and some portions that are vertical. In one example, it is useful from a manufacturing standpoint to attach a ribbon bond connection to a surface such as a substrate202or a die210in a horizontal orientation, then to twist, or otherwise reorient a middle portion of a ribbon bond connection.

As noted above,FIG.2further shows one or more vertical ribbon bond connections222from a die210to the substrate202. In one example, a vertical ribbon bond connection222is defined as vertical due to a majority of the connection222being vertical. In one example, a vertical ribbon bond connection222is defined as vertical due to a presence of any one portion of the connection222being vertical.

In one example, one or more vertical ribbon bond connections222are coupled to ground voltage and serve as shielding structures. Other voltages apart from ground are also within the scope of the invention. In the example shown, a vertical ribbon bond connection222is located between at least two wire bond connections220. In one example, one or more vertical ribbon bond connections222are interspersed within a row of wire bond connections220from a die210to the substrate202. In one example, a vertical ribbon bond connections222is interspersed as alternating between every wire bond connection220from the die210to the substrate202. As shown inFIG.2, vertical ribbon bond connections222can be interspersed within rows of wire bond connections220on multiple levels of a stack of dies210and to multiple channels214A,214B.

The presence of the vertical ribbon bond connection222at ground voltage provides at least some shielding effect, and reduces crosstalk noise, and/or provides some electromagnetic interference (EMI) protection. Because the vertical ribbon bond connection222is flat and vertical, it provides a greater shielding effect than if it were a single wire with a round cross section.

FIG.3shows a close up view of the channel substrate terminal214A. A vertical ribbon bond connection222is shown between two wire bond connections220. In the example ofFIG.3, the vertical ribbon bond connection222includes a horizontal portion224and a vertical portion226with a twist228that transitions between the two portions224,226. As noted above, in some examples, it is advantageous to manufacture a vertical ribbon bond connection222by twisting to provide both a robust bonding attachment at the channel substrate terminal214A, and to provide good shielding properties along the vertical portion226between the two wire bond connections220.

FIG.4shows a block diagram of cross sections of wire bond connections420and vertical ribbon bond connections422. A width dimension423is shown that is larger than a diameter of the wire bond connections420. The larger width423provide increased shielding effects as discussed above.

FIG.5shows a block diagram of another configuration with cross sections of wire bond connections520. InFIG.5, a vertical group of wire bond connections522A and522B are shown. As in other examples, the vertical group of wire bond connections522A and522B can be coupled to ground voltage. The vertical group of wire bond connections522A and522B acts like a vertical ribbon bond connection, and provides an increased width523. In one example, similar to vertical ribbon bond connections, the vertical group of wire bond connections522A and522B both lie in a vertical plane that is oriented orthogonal to a major plane of a substrate. As with the example ofFIG.4, a width dimension523is larger than a diameter of the wire bond connections520. The larger width523provide increased shielding effects as discussed above.

FIG.6shows an electronic device600. In the example ofFIG.6, the electronic device600includes a stack of offset memory dies610coupled to a substrate602. In the example ofFIG.6, the dies610are offset from one another to permit top surface wire bonding.FIG.6shows one example of an offset stacking configuration that includes stair stepping.

A first channel substrate terminal614A and a second channel substrate terminal614B are shown. Multiple rows of wire bond connections620,622,624,626are shown coupled from multiple dies610in the stack of offset semiconductor dies to the substrate to the channel substrate terminals614A,614B.

FIG.6further shows a row of ribbon bond connections627from a die610in the stack of offset semiconductor dies to the substrate, wherein the row of ribbon bond connections627is vertically adjacent to at least one row of wire bond connections from the multiple rows of wire bond connections. In one example, the row of ribbon bond connections627includes horizontal ribbon bond connections627as described above.

In one example, the at least one row of ribbon bond connections627are coupled to ground voltage at terminal623and serve as shielding structures. Other voltages apart from ground are also within the scope of the invention. In one example, the inclusion of at least one row of ribbon bond connections627provides at least some shielding effect, and reduces crosstalk noise, and/or provides some electromagnetic interference (EMI) protection. Because the row of ribbon bond connections627is flat and horizontal, it provides a greater shielding effect from above and below than if it were a single wire with a round cross section.

FIG.6further shows a second row of ribbon bond connections628. In one example, the second row of ribbon bond connections628are also coupled to ground at terminal630, and provide a shielding effect. In the example shown, the second row of ribbon bond connections628is between two different channels in the stack of offset semiconductor dies. The rows of wire bond connections620and622are coupled to channel substrate terminals614A, while the rows of wire bond connections624and626are coupled to channel substrate terminals614B. The second row of ribbon bond connections628in between the rows of wire bond connections coupled to the different channels614and614B.

In one example, at least one row of wire bond connections (620,622,624,626) is bounded by a row of ribbon bond connections from above and below. For example, at least one row of wire bond connections (one or more of620,622) is bounded by the row of ribbon bond connections627from above and by the second row of ribbon bond connections628from below.

In one example, a row of ribbon bond connections vertically separates two rows of the multiple rows of wire bond connections. For example, inFIG.6, row of ribbon bond connections628vertically separates row of wire bond connections627from row of wire bond connections624. In one example, two or more cascades of ribbon bond connections are electrically coupled together, and vertically separate two rows of the multiple rows of wire bond connections. For example, inFIG.6, two cascades of ribbon bond connections628and629are electrically coupled together to a ground voltage. The two cascades of ribbon bond connections628and629electrically separate row of wire bond connections627from row of wire bond connections624.

FIG.6further shows one example that includes one or more vertical ribbon bond connections640as described in examples above. In one example, one or more vertical ribbon bond connections640are located on an edge of at least one row of wire bond connections. As shown inFIG.6, in one example, at least one row of wire bond connections620is bounded by rows of ribbon bond connections627,628from above and below, and further bounded on sides by vertical ribbon bond connections640.

FIG.7shows a flow diagram of an example method of manufacture. As noted above, a ribbon bonding head may be attached to a robotic arm that is capable of twisting a ribbon orientation. In operation702, a first end of a bond ribbon is attached to a first surface. In operation704, the bond ribbon is twisted to orient a ribbon plane orthogonal to a major plane of the first surface to form a vertical bond ribbon. In operation706, a length of the vertical bond ribbon is extended to a second surface. In operation708, the bond ribbon is twisted to orient the ribbon plane parallel to a major plane of the second surface, and in operation710, a second end of the bond ribbon is attached to the second surface.

FIG.8illustrates a system level diagram, depicting an example of an electronic device (e.g., system) that may include vertical ribbon bond connections, rows of ribbon bonds, and methods described above. In one embodiment, system800includes, but is not limited to, a desktop computer, a laptop computer, a netbook, a tablet, a notebook computer, a personal digital assistant (PDA), a server, a workstation, a cellular telephone, a mobile computing device, a smart phone, an Internet appliance or any other type of computing device. In some embodiments, system800includes a system on a chip (SOC) system.

In one embodiment, processor810has one or more processor cores812and812N, where812N represents the Nth processor core inside processor810where N is a positive integer. In one embodiment, system800includes multiple processors including810and805, where processor805has logic similar or identical to the logic of processor810. In some embodiments, processing core812includes, but is not limited to, pre-fetch logic to fetch instructions, decode logic to decode the instructions, execution logic to execute instructions and the like. In some embodiments, processor810has a cache memory816to cache instructions and/or data for system800. Cache memory816may be organized into a hierarchal structure including one or more levels of cache memory.

In some embodiments, processor810includes a memory controller814, which is operable to perform functions that enable the processor810to access and communicate with memory830that includes a volatile memory832and/or a non-volatile memory834. In some embodiments, processor810is coupled with memory830and chipset820. Processor810may also be coupled to a wireless antenna878to communicate with any device configured to transmit and/or receive wireless signals. In one embodiment, an interface for wireless antenna878operates in accordance with, but is not limited to, the IEEE 802.11 standard and its related family, Home Plug AV (HPAV), Ultra Wide Band (UWB), Bluetooth, WiMax, or any form of wireless communication protocol.

In some embodiments, volatile memory832includes, but is not limited to, Synchronous Dynamic Random Access Memory (SDRAM), Dynamic Random Access Memory (DRAM), RAMBUS Dynamic Random Access Memory (RDRAM), and/or any other type of random access memory device. Non-volatile memory834includes, but is not limited to, flash memory, phase change memory (PCM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), or any other type of non-volatile memory device.

Memory830stores information and instructions to be executed by processor810. In one embodiment, memory830may also store temporary variables or other intermediate information while processor810is executing instructions. In the illustrated embodiment, chipset820connects with processor810via Point-to-Point (PtP or P-P) interfaces817and822. Chipset820enables processor810to connect to other elements in system800. In some embodiments of the example system, interfaces817and822operate in accordance with a PtP communication protocol such as the Intel® QuickPath Interconnect (QPI) or the like. In other embodiments, a different interconnect may be used.

In some embodiments, chipset820is operable to communicate with processor810,805N, display device840, and other devices, including a bus bridge872, a smart TV876, I/O devices874, nonvolatile memory860, a storage medium (such as one or more mass storage devices)862, a keyboard/mouse864, a network interface866, and various forms of consumer electronics877(such as a PDA, smart phone, tablet etc.), etc. In one embodiment, chipset820couples with these devices through an interface824. Chipset820may also be coupled to a wireless antenna878to communicate with any device configured to transmit and/or receive wireless signals. In one example, any combination of components in a chipset may be separated by a continuous flexible shield as described in the present disclosure.

Chipset820connects to display device840via interface826. Display840may be, for example, a liquid crystal display (LCD), a light emitting diode (LED) array, an organic light emitting diode (OLED) array, or any other form of visual display device. In some embodiments of the example system, processor810and chipset820are merged into a single SOC. In addition, chipset820connects to one or more buses850and855that interconnect various system elements, such as I/O devices874, nonvolatile memory860, storage medium862, a keyboard/mouse864, and network interface866. Buses850and855may be interconnected together via a bus bridge872.

While the modules shown inFIG.8are depicted as separate blocks within the system800, the functions performed by some of these blocks may be integrated within a single semiconductor circuit or may be implemented using two or more separate integrated circuits. For example, although cache memory816is depicted as a separate block within processor810, cache memory816(or selected aspects of816) can be incorporated into processor core812.

To better illustrate the method and apparatuses disclosed herein, a non-limiting list of embodiments is provided here:

Example 1 includes an electronic device. The electronic device includes a semiconductor die coupled to a substrate, one or more wire bond connections from the semiconductor die to the substrate, and one or more vertical ribbon bond connections from the semiconductor die to the substrate, wherein at least a portion of the one or more vertical ribbon bond connections is oriented with a ribbon plane orthogonal to a major plane of the substrate.

Example 2 includes the electronic device of example 1, wherein the one or more vertical ribbon bond connections is coupled to a ground voltage when in operation.

Example 3 includes the electronic device of any one of examples 1-2, wherein the one or more vertical ribbon bond connections includes a twist to translate a portion of the vertical ribbon bond connection from horizontal to vertical.

Example 4 includes the electronic device of any one of examples 1-3, wherein the one or more vertical ribbon bond connections are interspersed within a row of wire bond connections from the semiconductor die to the substrate.

Example 5 includes the electronic device of any one of examples 1-4, wherein vertical ribbon bond connections are included alternating between data signal wires within a row of wire bond connections from the semiconductor die to the substrate.

Example 6 includes the electronic device of any one of examples 1-5, wherein the semiconductor die includes a memory die.

Example 7 includes the electronic device of any one of examples 1-6, wherein the semiconductor die is a memory die included within a stack of memory dies.

Example 8 includes the electronic device of any one of examples 1-7, wherein vertical ribbon bond connections are included alternating between data signal wires within multiple rows of wire bond connections between different level dies in the stack of memory dies and the substrate.

Example 9 includes an electronic device. The electronic device includes a stack of offset semiconductor dies coupled to a substrate, multiple rows of wire bond connections from multiple dies in the stack of offset semiconductor dies to the substrate, and a row of ribbon bond connections from a die in the stack of offset semiconductor dies to the substrate, wherein the row of ribbon bond connections is vertically adjacent to at least one row of wire bond connections from the multiple rows of wire bond connections.

Example 10 includes the electronic device of example 9, wherein the row of ribbon bond connections is between two different channels in the stack of offset semiconductor dies.

Example 11 includes the electronic device of any one of examples 9-10, wherein the row of ribbon bond connections is coupled to a ground voltage when in operation.

Example 12 includes the electronic device of any one of examples 9-11, wherein the row of ribbon bond connections vertically separates two rows of the multiple rows of wire bond connections.

Example 13 includes the electronic device of any one of examples 9-12, wherein two or more cascades of ribbon bond connections are electrically coupled together, and vertically separate two rows of the multiple rows of wire bond connections.

Example 14 includes the electronic device of any one of examples 9-13, further including one or more vertical ribbon bond connections from the semiconductor die to the substrate, wherein at least a portion of the one or more vertical ribbon bond connections is oriented with a ribbon plane orthogonal to a major plane of the substrate.

Example 15 includes the electronic device of any one of examples 9-14, wherein the vertical ribbon bond connection is on an edge of at least one row of wire bond connections from the multiple rows of wire bond connections.

Example 16 includes the electronic device of any one of examples 9-15, wherein at least one row of wire bond connections from the multiple rows of wire bond connections is bounded by a row of ribbon bond connections from above and below, and wherein the at least one row of wire bond connections from the multiple rows of wire bond connections is bounded on sides by vertical ribbon bond connections.

Example 17 includes a method that includes attaching a first end of a bond ribbon to a first surface, twisting the bond ribbon to orient a ribbon plane orthogonal to a major plane of the first surface to form a vertical bond ribbon, extending a length of the vertical bond ribbon to a second surface, twisting the bond ribbon to orient the ribbon plane parallel to a major plane of the second surface, and attaching a second end of the bond ribbon to the second surface.

Example 18 includes the method of example 17, further including coupling the vertical bond ribbon to a ground voltage when in operation.

Example 19 includes the method of any one of examples 17-18, further including coupling the vertical bond ribbon laterally between two data signal bond wires.

Example 20 includes the method of any one of examples 17-19, further including coupling the vertical bond ribbon at a lateral edge of a row of wire bond connections, the row of wire bond connections coupled between a die and a substrate.

Example 21 includes the method of any one of examples 17-20, further including coupling a row of ribbon bond connections vertically adjacent to the row of wire bond connections.

Example 22 includes an electronic device. The electronic device includes a semiconductor die coupled to a substrate, two data wire bond connections from the semiconductor die to the substrate, and a ground voltage vertical group of wire bond connections from the semiconductor die to the substrate, wherein the vertical group of wire bond connections both lie in a vertical plane that is oriented orthogonal to a major plane of the substrate, and wherein the vertical group of wire bond connections is between the two data wire bond connections.