System and method for a serial peripheral interface

A system and method are provided to enable first and second devices coupled to a SPI bus to operate as master devices on the SPI bus without collisions between the two devices or race conditions with respect to obtaining control over the SPI bus.

FIELD OF INVENTION

The present disclosure relates to the field of communications via a serial peripheral interface (SPI), and more particularly toward communicating with a slave device via a SPI.

BACKGROUND

In conventional SPI communication systems, a single master device is operable to direct communications with one or more slave devices via a SPI bus. Use of a single master device can impede communications or involve additional circuitry in cases where multiple devices need access to another device on the SPI bus. Because the SPI bus is configured for a single master device, circuit and system designers have accepted these limitations as a tradeoff for using the well-defined SPI interface.

SUMMARY

In general, one innovative aspect of the subject matter described herein can be embodied in a system for communicating with a slave device via a slave SPI. The system may include a serial bus configured to facilitate communications with the slave SPI, a first master device operably coupled to the serial bus to communicate with the slave device via the slave SPI, and a second master device operably coupled to the serial bus to communicate with the slave device via the slave SPI.

The system may include an arbitration interface established between the first master device and the second master device. The arbitration interface may include a SPI hold signal and a SPI arbitration signal, where the SPI arbitration signal may be toggled between an arbitration high state and an arbitration low state. The first master device may be operable to identify availability of the serial bus based on 1) the SPI arbitration signal being the arbitration high state and 2) detection of the SPI hold signal being in an available state. The second master device may be operable to identify availability of the serial bus based on 1) the SPI arbitration signal being the arbitration low state and 2) detection of the SPI hold signal being in the available state.

In some embodiments, the system may include the first master device being operable to detect a state of the SPI hold signal in response to a rising edge of the SPI arbitration signal that corresponds to a transition from the arbitration low state to the arbitration high state. The second master device may be operable to detect the state of the SPI hold signal in response to a falling edge of the SPI arbitration signal that corresponds to a transition from the arbitration high state to the arbitration low state and the SPI hold signal being in an available state.

In some embodiments, the system may include the first master device and the second master device being operable to abstain from controlling the serial bus despite the serial bus being respectively available for the first master device and the second master device.

In some embodiments, the system may include the first master device being operable to change the SPI hold signal to an unavailable state based on identifying availability of the serial bus, whereby the first master device may be operable to control the serial bus in response to changing the SPI hold signal to the unavailable state.

In some embodiments, the system may include the first master device being operable to communicate with the SPI of the slave device via the serial bus while controlling the serial bus.

In some embodiments, the system may include the first master device being operable to control the serial bus for a first control duration.

In some embodiments, the system may include the SPI arbitration signal being toggled periodically according to an arbitration period.

In some embodiments, the system may include the arbitration period being shorter in duration than the first control duration.

In some embodiments, the system may include the first master device being configured to limit the first control duration to a maximum control duration.

In some embodiments, the system may include the first master device being operable to change the SPI hold signal to an available state to release control of the serial bus.

In some embodiments, the system may include the second master device being operable to change the SPI hold signal to an unavailable state based on identifying availability of the serial bus.

In general, one innovative aspect of the subject matter described herein can be embodied in a method of communicating with a slave device via a slave SPI. The method may include providing a serial bus configured to facilitate communications with the slave SPI, toggling a SPI arbitration signal between an arbitration high state and an arbitration low state.

The method may include identifying, in a first master device, availability of the serial bus based on 1) the SPI arbitration signal being the arbitration high state and 2) detection of a SPI hold signal being in an available state. The method may include identifying, in a second master device, availability of the serial bus based on 1) the SPI arbitration signal being the arbitration low state and 2) detection of the SPI hold signal being in the available state; and changing, by the first master device, the SPI hold signal to an unavailable state based on identifying availability of the serial bus. The first master device may be operable to control the serial bus in response to changing the SPI hold signal to the unavailable state.

In some embodiments, the method may include detecting, by the first master device, a state of the SPI hold signal in response to a rising edge of the SPI arbitration signal that corresponds to a transition from the arbitration low state to the arbitration high state, and detecting, by the second master device, the state of the SPI hold signal in response to a falling edge of the SPI arbitration signal that corresponds to a transition from the arbitration high state to the arbitration low state and the SPI hold signal being in an available state.

In some embodiments, the method may include communicating between the first master device and the slave device via the SPI while the first master device controls the serial bus.

In some embodiments, the method may include controlling, by the first master device, the serial bus for a first control duration.

In some embodiments, toggling the SPI arbitration signal may include toggling the SPI arbitration signal periodically according to an arbitration period.

In some embodiments, the arbitration period may be shorter in duration than the first control duration.

In some embodiments, the first master device may be configured to limit the first control duration to a maximum control duration.

In some embodiments, the method may include changing, by the first master device, the SPI hold signal to an available state to release control of the serial bus.

In some embodiments, the method may include changing, by the second master device, the SPI hold signal to an unavailable state based on identifying availability of the serial bus.

In general, one innovative aspect of the subject matter described herein can be embodied in an apparatus that includes at least one memory storing computer program instructions and at least one processor configured to execute the computer program instructions to cause the apparatus at least to provide a serial bus configured to facilitate communications with the slave SPI, toggle a SPI arbitration signal between an arbitration high state and an arbitration low state, identify, in a first master device, availability of the serial bus based on 1) the SPI arbitration signal being the arbitration high state and 2) detection of a SPI hold signal being in an available state, identify, in a second master device, availability of the serial bus based on 1) the SPI arbitration signal being the arbitration low state and 2) detection of the SPI hold signal being in the available state, and change, by the first master device, the SPI hold signal to an unavailable state based on identifying availability of the serial bus. The first master device may be operable to control the serial bus in response to changing the SPI hold signal to the unavailable state.

In some embodiments, the apparatus may be operable to detect, by the first master device, a state of the SPI hold signal in response to a rising edge of the SPI arbitration signal that corresponds to a transition from the arbitration low state to the arbitration high state.

In some embodiments, the apparatus may be operable to detect, by the second master device, the state of the SPI hold signal in response to a falling edge of the SPI arbitration signal that corresponds to a transition from the arbitration high state to the arbitration low state and the SPI hold signal being in an available state.

In some embodiments, the apparatus may be operable to communicating between the first master device and the slave device via the SPI while the first master device controls the serial bus.

In some embodiments, the apparatus may be operable to control, by the first master device, the serial bus for a first control duration.

In some embodiments, the apparatus may be operable to toggle the SPI arbitration signal includes toggling the SPI arbitration signal periodically according to an arbitration period.

In some embodiments, the arbitration period may be shorter in duration than the first control duration.

In some embodiments, the first master device may be configured to limit the first control duration to a maximum control duration.

In some embodiments, the apparatus may be operable to change, by the first master device, the SPI hold signal to an available state to release control of the serial bus.

In some embodiments, the apparatus may be operable to change, by the second master device, the SPI hold signal to an unavailable state based on identifying availability of the serial bus.

DETAILED DESCRIPTION

A system and method are provided to enable first and second devices coupled to a SPI bus to operate as master devices on the SPI bus without collisions between the two devices or race conditions with respect to obtaining control over the SPI bus.

A device or platform in accordance with one embodiment is depicted in the illustrated embodiment ofFIG.1and generally designated102. The platform102may include a first device151and a second device152, both of which may operate as master devices with respect to a SPI bus150. A slave device156may be coupled to the SPI bus150, and operable to communicate with one or both of the first and second devices151,152. Additional slave devices156may be coupled to the SPI bus150. As described herein, a controller154may be provided to control operation of the first and second devices151,152. The first device151may correspond to a Bluetooth Low Energy (BLE) controller, the second device152may correspond to an Ultrawide Band (UWB) controller, and the slave device156may correspond to a CAN controller operable to communicate with either of the BLE controller or the UWB controller to enable transmission and reception of CAN communications for both the BLE controller and the UWB controller. Applications for such CAN communications include phone-as-a-key systems for objects (e.g., a vehicle) and smartphones, including for instance the system described in U.S. Pub. 2021/0392461, entitled SYSTEM AND METHOD FOR AUTOMATED DATA COLLECTION AND ANCHOR LOCATION EVALUATION, published Dec. 16, 2021, to Cooper et al.—the disclosure of which is hereby incorporated by reference in its entirety.

FIG.2illustrates a system configured for communicating with a slave device via a slave SPI, in accordance with one or more embodiments. In some cases, the system100may include one or more computing platforms102. Optionally, the one or more computing platforms102may be communicably coupled with one or more remote platforms104. In some cases, users may access the system100via remote platform(s)104.

The one or more computing platforms102may be configured by machine-readable instructions106. Machine-readable instructions106may include modules. The modules may be implemented as one or more of functional logic, hardware logic, electronic circuitry, software modules, and the like. The modules may include one or more of a SPI line toggling module110, a first device availability identifying module112, a second device availability identifying module114, a first device changing module116, and/or other modules. The modules are described in conjunction with a computing platform102, which may include more than one device or component (e.g., first and second devices, a slave device, and a controller). One or more modules may be provided in one device or component, and one or more other modules may be provided in another device or component. The first device151may include an arbitration interface operable to detect a state of and/or control operation of one or both of a SPI arbitration signal161and a SPI hold signal162. The arbitration interface may include the first device availability identifying module112. The second device152may also include an arbitration interface operable to detect a state of and/or control operation of one or both of a SPI arbitration signal161and a SPI hold signal162, and where the arbitration interface may include the second device availability identifying module114.

The computing platform102may include a SPI bus150operable to facilitate communication between a first device151and a slave device156and between a second device152and the slave device156. The SPI bus150may be shared by the first device151, the second device152, and the slave device156. It is noted that additional slave devices156may be coupled to the SPI bus150for communication via the SPI bus150. The first device151and the second device152may operate independently. Alternatively, operation of the first and second devices151,152may be directed by a controller154, which is shown in dashed lines as an optional component. The first and second devices151,152may be provided on the same circuit board assembly or separate circuit board assemblies.

In the illustrated embodiment, the first device151corresponds to a UWB controller, and the second device corresponds to a BLE controller. The slave device156is a CAN controller operable to facilitate communication, via the SPI bus150, between a CAN bus (not shown) and the first and second devices151,152. The first and second devices151,152may operate as master devices with respect to the slave device156, as described herein. It is to be understood that the present disclosure is not limited to a configuration that involves the first and second devices151,152being a UWB controller and a BLE controller, or the slave device156being a CAN controller; the first and second devices151,152and the slave device156may be any type of devices that utilize a SPI bus150in accordance with one embodiment.

The SPI line toggling module110, in one embodiment, may be configured to toggle a SPI arbitration signal161between an arbitration high state and an arbitration low state. The SPI line toggling module110may be provided in the first device151, which may operate as a master time share device between the first and second devices151,152. The second device may operate as a slave time share device in this context. It is noted that the present disclosure is not limited to the first and second devices151,152being the only master devices for the SPI bus150; one or more additional devices may be provided to operate as master devices on the SPI bus150. Coordination of which device is operating as the master device may be conducted in accordance with one embodiment of the present disclosure.

In one embodiment, the SPI line toggling module110may be configured to toggle the SPI arbitration signal161periodically (e.g., every 5 ms based on a 5 ms CAN task). In the illustrated embodiment, the first device151, operating as a master time share device, includes the SPI line toggling module110and toggles the SPI arbitration signal161accordingly.

An availability identifying module112may be provided in the first device151and may be configured to identify availability of the SPI bus150based on 1) the SPI arbitration signal161being in the arbitration high state and 2) detection of a SPI hold signal162being in an available state. The availability identifying module112may monitor the SPI arbitration signal161for arbitration high states. This may involve detecting rising edges of the SPI arbitration signal161, and at each rising edge, determining if the SPI hold signal162indicates an available state.

If the SPI hold signal162indicates an available state, and the first device151has a pending SPI transaction, the first device151may change the state of the SPI hold signal162to an unavailable state in order to indicate to the second device152that the SPI bus150is unavailable. Alternatively, the first device151may hold the SPI arbitration signal161in an arbitration high state, which may effectively prevent the second device152from making a determination as to whether the SPI bus150is available. After the first device151has indicated it is in control of the SPI bus150, the first device151may operate as the master device of the SPI bus150by beginning the SPI transaction.

If the SPI hold signal162indicates an unavailable state, the availability identifying module112may wait until the next rising edge of the SPI arbitration signal161to repeat the determination of whether the SPI hold signal162indicates an available state.

After the availability identifying module112determines that the SPI bus150is available, as described herein, the first device151may change the state of the SPI hold signal162to an unavailable state or hold the SPI arbitration signal161in an arbitration high state, or both. This way, the first device151may indicate it is in control of the SPI bus150. At this stage, if the first device151is indicating it is in control of the SPI bus150, the first device151may operate as the master of the SPI bus150. The first device151may include a changing module116configured to change the state or control over one or both of the SPI arbitration signal161and the SPI hold signal162, in order to indicate the SPI bus150is in an unavailable state with respect to other devices (e.g., the second device152) and such that the first device151is in control over the SPI bus150.

The first device151operating in this mode as the master may perform one or more pending SPI transactions. After one or more of the pending SPI transactions have completed, the first device151may resume toggling the SPI arbitration signal161, which may enable the second device152to take control of the SPI bus150as the master, if the second device152has one or more pending SPI transactions. As described herein, the second device152may determine the SPI bus150is unavailable based on a state of the SPI arbitration signal161being in a high state or without identifying a falling edge transition of the SPI arbitration signal161from a high state to a low state.

In an alternative embodiment, the SPI hold signal162may be under control of the second device152, and the SPI arbitration signal161may be under control of the first device, where determinations about holding the SPI bus150for communications can be coordinated, based on the SPI arbitration signal161, with the first device151making determinations at rising edges or high states and with the second device152making determinations at falling edges or low states for the second device. This way, the first and second device151,152may avoid a race condition with respect to being a master device on the SPI bus150.

In one embodiment, toggling the SPI arbitration signal161includes toggling the SPI arbitration signal periodically according to an arbitration period. The arbitration period may be shorter in duration than a control duration with respect to the first and second devices151,152. As a result, the first device151and the second device152may control the SPI bus150for a control duration that is longer than the arbitration, such that the control duration is greater than a multiple of the arbitration period. As described herein, the first device151and the second device152may be configured to limit the control duration to a maximum control duration.

The second device152may include an availability identifying module114that may be configured to identify availability of the serial bus based on 1) the SPI arbitration signal being the arbitration low state and 2) detection of the SPI hold signal being in the available state. Instead of determining availability based on the SPI arbitration signal161being in a high state, like the first device151, the availability identifying module114of the second device152may determine availability based on the SPI arbitration signal161being in a low state. In one example, the availability identifying module114may determine availability in response to falling edges of the SPI arbitration signal161from a high state to a low state.

In the second device152, if the availability identifying module114determines the SPI bus150is in an available state and the second device152has a pending transaction, the second device152may change the state of the SPI hold signal162to an unavailable state in order to indicate to the first device151that the SPI bus150is unavailable. After the second device152has indicated it is in control of the SPI bus150, the second device152may operate as the master device of the SPI bus150by beginning the SPI transaction.

If the availability identifying module114determines the SPI bus150is in an unavailable state, the availability identifying module114may wait until after the next falling edge of the SPI arbitration signal161to repeat the determination of whether the SPI bus150is in an available state. The availability identifying module114determines availability with respect to the SPI bus150in response to falling edges of the SPI arbitration signal161.

The availability identifying module114may determine the SPI bus is available in a variety of ways depending on the application. In the illustrated embodiment, the availability identifying module114may determine the SPI bus150is available based on identifying a falling edge of the SPI arbitration signal161, which is under control of the first device151.

Alternatively, the availability identifying module114may determine the SPI bus150is available based on the SPI hold signal162being in an available state. As described herein, the availability identifying module may determine whether the SPI hold signal162is in an available state when the SPI arbitration signal161is in a low state, including in response to when the SPI arbitration signal161transitions from a high state to the low state.

If the second device152indicates to the first device151that the second device152is in control of the SPI bus150(e.g., by changing a state of the SPI hold signal162to an unavailable state), the second device152may operate as the master and perform one or more pending SPI transactions. After one or more of the pending SPI transactions have completed, the second device152may change the state of the SPI hold signal162to an available state in order to indicate to the first device151that the SPI bus150is no longer under control of the second device152.

In one embodiment, the first device151and the second device152may each assert control over the SPI bus150. The respective timing for taking control over the SPI bus150may be configured such that a race condition is avoided between the first device151and the second device152. The first device151and the second device152may each control respectively whether to release the SPI bus150after taking control over the SPI bus150. As a result, for example, if the first device151takes control over the SPI bus150, the second device152may be prevented from taking control until the first device151indicates to the second device152that the first device151no longer has control over the SPI bus150.

In one embodiment, there is a potential for a device to hold the SPI bus150indefinitely and prevent the other device from gaining control over the SPI bus150. As a result, the devices configured to take control over the SPI bus150in accordance with one or more embodiments may be configured to limit a duration of control over the SPI bus150. For instance, the devices may be configured to release control over the SPI bus150according to the lesser of 1) a maximum control duration (e.g., 50 ms) or 2) a time to complete all pending SPI transactions. In this way, if the maximum control duration is reached before all pending SPI transactions are completed, a device may release control over the SPI bus150and attempt to regain control (e.g., at the next rising edge or falling edge of the SPI arbitration signal161) over the SPI bus150after another device has had an opportunity to take control over the SPI bus150and complete one or more pending SPI transactions.

In one embodiment, the first device151or second device152, or both, may be configured to operate without limitations on duration of control. Such a configuration may be permanent or temporary (e.g., a temporary override for an override type of SPI transactions). For instance, if the first device151initiates an override type of SPI transactions that correspond to a firmware upgrade, the first device151may be configured to take control of the SPI bus150and to release control of the SPI bus150after all of the SPI transactions associated with the firmware upgrade have completed, regardless of whether the duration of the SPI transactions extends beyond any limitations on duration of control of the SPI bus150.

In one embodiment, the first and second devices151,152may be configured to determine whether the SPI bus150is available based on a state of the SPI arbitration signal161being in a high state or a low state. The determination may be conducted in response to a transition from a high state to a low state (e.g., a rising edge) or from a low state to a high state (e.g., a falling edge). It is to be understood that the present disclosure is not so limited; the determination may be conducted in response to more complex state changes of the SPI arbitration signal161, including encoded data, such as encoded data that may be associated with one of the devices (e.g., the first and second devices151,152). Such complex state changes may still involve the SPI arbitration signal161being in a high or low state when the first and second devices151,152determine to check availability of the SPI bus150.

In some cases, the one or more computing platforms102may be communicatively coupled to the remote platform(s)104. In some cases, the communicative coupling may include communicative coupling through a networked environment118. The networked environment118may be a radio access network, such as LTE or 5G, BLE, UWB, a local area network (LAN), a wide area network (WAN) such as the Internet, or wireless LAN (WLAN), for example. It is to be understood that this is not intended to be limiting, and that the scope of this disclosure includes implementations in which one or more computing platforms102and remote platform(s)104may be operatively linked via another communication coupling. The one or more computing platforms102may be configured to communicate with the networked environment118via wireless or wired connections. In addition, in one embodiment, the one or more computing platforms102may be configured to communicate directly with each other via wireless or wired connections. Examples of one or more computing platforms102may include, but is not limited to, smartphones, wearable devices, tablets, laptop computers, desktop computers, Internet of Things (IoT) device, or other mobile or stationary devices, including devices disposed on a vehicle or other type of object. In one embodiment, the system100may also include one or more hosts or servers, such as the one or more remote platforms104connected to the networked environment118through wireless or wired connections. According to one embodiment, remote platforms104may be implemented in or function as base stations. In other embodiments, remote platforms104may include web servers, mail servers, application servers, etc. According to certain embodiments, remote platforms104may be standalone servers, networked servers, or an array of servers.

The one or more computing platforms102may include one or more processors120for processing information and executing instructions or operations. The one or more processors120may be any type of general or specific purpose processor. In some cases, multiple processors120may be utilized according to other embodiments. The one or more processors120may include one or more of general-purpose computers, special purpose computers, microprocessors, digital signal processors (DSPs), field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), and processors based on a multi-core processor architecture, as examples. In some cases, the one or more processors120may be remote from the one or more computing platforms102, such as disposed within a remote platform like the one or more remote platforms104ofFIG.2.

The one or more processors120may perform functions associated with the operation of the system100which may include, for example, precoding of antenna gain/phase parameters, encoding and decoding of individual bits forming a communication message, formatting of information, and overall control of the one or more computing platforms102, including processes related to management of communication resources.

The one or more computing platforms102may further include or be coupled to a memory122(internal or external), which may be coupled to one or more processors120, for storing information and instructions that may be executed by one or more processors120. Memory122may be one or more memories and of any type suitable to the local application environment, and may be implemented using any suitable volatile or nonvolatile data storage technology such as a semiconductor-based memory device, a magnetic memory device and system, an optical memory device and system, fixed memory, and removable memory. For example, memory122can consist of any combination of random access memory (RAM), read only memory (ROM), static storage such as a magnetic or optical disk, hard disk drive (HDD), or any other type of non-transitory machine or computer readable media. The instructions stored in memory122may include program instructions or computer program code that, when executed by one or more processors120, enable the one or more computing platforms102to perform tasks as described herein.

In some embodiments, one or more computing platforms102may also include or be coupled to one or more antennas124for transmitting and receiving signals and/or data to and from one or more computing platforms102. The one or more antennas124may be configured to communicate via, for example, a plurality of radio interfaces that may be coupled to the one or more antennas124. The radio interfaces may correspond to a plurality of radio access technologies including one or more of LTE, 5G, WLAN, BLE, near field communication (NFC), radio frequency identifier (RFID), UWB, and the like. The radio interface may include components such as filters, converters (for example, digital-to-analog converters and the like), mappers, a Fast Fourier Transform (FFT) module, and the like, to generate symbols for a transmission via one or more downlinks and to receive symbols (for example, via an uplink).

FIG.3illustrates an example flow diagram of a method200, according to one embodiment. The method200may include providing a serial bus configured to facilitate communications with the slave SPI. Step202. The method200may include toggling a SPI arbitration signal between an arbitration high state and an arbitration low state. Step204. The method200may include identifying, in a first master device, availability of the serial bus based on 1) the SPI arbitration signal being the arbitration high state and 2) detection of a SPI hold signal being in an available state. Step206. The method200may include identifying, in a second master device, availability of the serial bus based on 1) the SPI arbitration signal being the arbitration low state and 2) detection of the SPI hold signal being in the available state. Step208. The method200may include changing, by the first master device, the SPI hold signal to an unavailable state based on identifying availability of the serial bus, whereby the first master device is operable to control the serial bus in response to changing the SPI hold signal to the unavailable state. Step210.

In some cases, the method200may be performed by one or more hardware processors, such as the processors120ofFIG.2, configured by machine-readable instructions, such as the machine-readable instructions106ofFIG.2. In this aspect, the method200may be configured to be implemented by the modules, such as the modules110,112,114and/or116discussed above inFIG.2.