Phase shift circuit and power factor correction circuit including the same

There are provided a phase shift circuit and a power factor correction circuit including the same. The phase shift circuit includes a switching circuit unit charging power in or discharging power from a capacitor through a plurality of switching devices and comparing a voltage of the capacitor with a predetermined reference voltage, and a clock generating unit generating a reference clock signal based on an output of the switching circuit unit, wherein the switching circuit unit turns the plurality of switching devices on or off, based on currents from inductors respectively included in a main circuit and a sub-circuit of a power factor correction circuit to determine a polarity of the voltage of the capacitor.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the priority of Korean Patent Application No. 10-2012-0151303 filed on Dec. 21, 2012, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a phase shift circuit capable of significantly decreasing an electromagnetic interference (EMI) component of an input/output signal by adjusting a phase difference between driving signals of switches operating a main circuit and a sub-circuit included in a power factor correction circuit, and a power factor correction circuit including the same.

2. Description of the Related Art

Recently, in the electrical appliance and electronic device fields, research into a method of removing harmonic components generated in an input terminal of an electronic apparatus in order to significantly decrease an effect on a power line of an electrical appliance or electronic device and reduce interference with other appliances and devices has been actively undertaken. As an efficient method of removing harmonic components, a power factor correction (PFC) circuit may be used. A power factor correction circuit may be classified as a passive-type power factor correction circuit or an active-type power factor correction circuit, according to whether or not it includes a switch. The passive-type power factor correction circuit has disadvantages in that a form factor thereof may be large, and an effect thereof may not be great. Therefore, recently, active-type power factor correction circuits have been widely used.

Among active-type power factor correction circuits, an interleaving-type power factor correction circuit using at least two identical power factor correction circuits connected to each other in parallel has characteristics that depend on a phase difference between signals for operating a plurality of circuits connected to each other in parallel. For example, when it is assumed that two identical power factor correction circuits are connected to each other in parallel in a master-slave scheme, in the case in which driving signals for operating switches respectively included in the two identical power factor correction circuits have a phase difference of 180 degrees therebetween, an electromagnetic interference (EMI) component of an input/output signal may be significantly decreased. When the phase difference between the driving signals for a main circuit and a sub-circuit deviates from 180 degrees, a ripple component of an input current increases, such that an EMI component increases.

In the interleaving-type power factor correction circuit, various type phase shift circuits have been suggested in order to maintain a phase difference between switching devices included in respective circuits at a required value. However, in the phase shift circuit suggested in the related art, a selection condition in selecting a current source included in the circuit was limited or it was difficult to accurately generate a required phase difference.

In the following Related Art Documents, Patent Document 1, which relates to an interleaved-type switching converter, and an apparatus and method of controlling the same, discloses a method of switching power in an interleaving scheme to generate a control signal and maintaining a phase difference at a required value, for example, 180 degrees. Patent Document 2, which relates to a phase shift and synchronization circuit, discloses a feature of adjusting a sink between control signals of the respective switching devices in an interleaving-type power factor correction circuit. However, neither Patent Document 1 nor Patent Document 2 discloses a feature of changing a polarity of a voltage of a capacitor in a circuit controlling a phase difference to operate a switch at a required phase difference.

RELATED ART DOCUMENT

SUMMARY OF THE INVENTION

An aspect of the present invention provides a phase shift circuit capable of decreasing a phase difference due to change in process, voltage, and temperature (PVT) conditions and a mismatch in a process by controlling switches of respective main circuit and sub-circuit included in a power factor correction circuit to have a required phase difference therebetween and controlling a phase difference between driving signals for operating switches of the main circuit and the sub-circuit according to a polarity of a voltage of a capacitor changed in a positive (+) or negative (−) direction, based on a predetermined voltage, and a power factor correction circuit including the same.

According to an aspect of the present invention, there is provided a phase shift circuit including: a switching circuit unit charging power in or discharging power from a capacitor through a plurality of switching devices and comparing a voltage of the capacitor with a predetermined reference voltage; and a clock generating unit generating a reference clock signal based on an output of the switching circuit unit, wherein the switching circuit unit turns the plurality of switching devices on or off based on currents from inductors respectively included in a main circuit and a sub-circuit of a power factor correction circuit to determine a polarity of the voltage of the capacitor.

The plurality of switching devices may include first and second switch groups having different operational timings, and a polarity of the voltage of the capacitor when the first switch group is turned on may be different from a polarity of the voltage of the capacitor when the second switch group is turned on.

The switching circuit unit may include: at least one current source supplying charges to the capacitor; and at least one voltage source generating a voltage having the same level as that of the reference voltage.

The phase shift circuit may further include a detection circuit unit detecting the currents of the inductors respectively included in the main circuit and the sub-circuit, wherein the switching circuit unit determines operations of the plurality of switching devices based on an output of the detection circuit unit.

The clock generating unit may generate the reference clock signal so as to have a phase difference of 180 degrees from a voltage pulse signal corresponding to the current of the inductor included in the main circuit.

The detection circuit unit may detect the currents of the inductors by a zero-crossing method.

The phase shift circuit may further include a control circuit unit generating a control signal based on a voltage signal corresponding to the current of the inductor included in the sub-circuit and the reference clock signal, wherein the control circuit unit determines a level of the control signal by using a phase difference between the voltage signal corresponding to the current of the inductor included in the sub-circuit and the reference clock signal.

According to another aspect of the present invention, there is provided a power factor correction circuit including: a detection circuit unit detecting currents from inductors respectively included in a main circuit and a sub-circuit to generate a voltage pulse signal; a controlling unit generating a control signal based on the voltage pulse signal; and a driving circuit unit determining operations of switches respectively included in the main circuit and the sub-circuit, based on the control signal and the voltage pulse signal, wherein the controlling unit generates the control signal to allow driving signals for respectively operating the switch included in the main circuit and the switch included in the sub-circuit to have a phase difference therebetween so as to allow electromagnetic interference (EMI) to be significantly decreased.

The controlling unit may include: a phase shift circuit including a capacitor in or from which power is charged or discharged through a plurality of switching devices, and a clock generating circuit generating a reference clock signal by using a voltage of the capacitor; and a control signal generating circuit determining a level of the control signal based on the reference clock signal and the voltage pulse signal, the plurality of respective switching devices being turned on or turned off by the voltage pulse signal to determine a polarity of the voltage of the capacitor.

The control signal generating circuit may determine the level of the control signal from a phase difference between the reference clock signal and the voltage pulse signal.

The control signal generating circuit may raise the level of the control signal when a phase of the voltage pulse signal generated from the current of the inductor included in the sub-circuit leads a phase of the reference clock signal, and may lower the level of the control signal when the phase of the voltage pulse signal generated from the current of the inductor included in the sub-circuit lags behind the phase of the reference clock signal.

The clock generating circuit may generate the reference clock signal so as to have a phase difference of 180 degrees from the voltage pulse signal generated from the current of the inductor included in the main circuit.

The detection circuit unit may generate the voltage pulse signal by a zero-crossing method.

The driving circuit unit may include: a ramp generating unit generating a first ramp signal having a fixed gradient and a second ramp signal having a variable gradient from the control signal; a comparing circuit unit comparing the first and second ramp signals with a predetermined reference signal; and a flip-flop generating driving signals for the switches included in the main circuit and the sub-circuit, based on an output of the comparing circuit unit and the voltage pulse signal.

The comparing circuit unit may compare an output signal of at least one of the main circuit and the sub-circuit with a band gap reference (BGR) signal to generate the reference signal.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein.

Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

FIG. 1is a schematic circuit diagram illustrating a power factor correction circuit according to an embodiment of the present invention.

Referring toFIG. 1, the power factor correction (PFC) circuit100according to the present embodiment may include a rectifying unit110receiving and rectifying alternating current (AC) power, a power factor correcting unit120including inductors L1and L2connected to each other in parallel, a resistor RL, and a capacitor C1OUT, and a switch unit130controlling an operation of circuits connected to each other in parallel. The switch unit130may control a current flowing in the inductors L1and L2, and switching devices S1and S2may be turned on or turned off by gate driving signals GDA and GDB, respectively.

AlthoughFIG. 1shows only one resistor RLand one capacitor C1OUTfor convenience, each of the resistor and the capacitor may also be classified as two devices connected to each other in parallel, similar to the inductors L1and L2. That is, the power factor correction circuit100shown inFIG. 1may be an interleaving power factor correction circuit in which two same circuits are connected to each other in parallel in a master-slave scheme. In this case, when the gate driving signals GDA and GDB controlling operations of the respective circuits have a phase difference of 360/2 degrees, that is, 180 degrees therebetween, a ripple component of an input current Iinmay be significantly decreased, and an EMI component thereof may be decreased.

In order to significantly decrease the ripple component and the EMI component of the input current Iin, the power factor correction circuit100may include a phase shift circuit provided in a controlling unit generating the gate driving signals GDA and GDB. The phase shift circuit may allow the phase difference between the gate driving signals GDA and GDB to be maintained as 180 degrees. To this end, the phase shift circuit may receive voltages converted from currents respectively flowing in the inductors L1and L2. Hereinafter, a circuit configuration capable of setting the phase difference between the gate driving signals GDA and GDB to a required value and an operational method thereof will be described with reference toFIGS. 2 through 6.

FIG. 2is a circuit diagram illustrating an example of a phase shift circuit according to the embodiment of the present invention.

Referring toFIG. 2, the phase shift circuit200according to the present embodiment may include switching circuit units210and215including at least one power supply, a plurality of switching devices, a capacitor, a comparator, and the like, and a clock generating unit220generating a reference clock signal φHP. An operation of the phase shift circuit200will first be described with reference toFIGS. 2 and 3, and a circuit and a method for adjusting a phase difference between gate driving signals GDA and GDB from the reference clock signal φHPoutputted by the phase shift circuit200will be described below with reference toFIGS. 4 and 5.

The plurality of switching devices included in the switching circuit units210and215inFIG. 2may be classified as a first switch group of which turning on and turning off are controlled by a first control signal φ1and a second switch group of which turning on and turning off are controlled by a second control signal φ2. The first and second control signals φ1and φ2may be signals generated by the currents flowing in the inductors L1and L2of the power factor correction circuit100. For example, the currents flowing in the inductors L1and L2are detected, and voltage pulse signals VDT1and VDT2of which a pulse is generated at the time at which the detected current becomes 0 are generated. Levels of the first and second control signals φ1and φ2are determined according to operations of the voltage pulse signals VDT1and VDT2, and the turning on and turning off of the first and second switch groups are determined according to the levels of the first and second control signals.

The comparator included in the switching circuit unit210may compare a voltage signal VRT1corresponding to a voltage of a capacitor C1with a reference voltage VDCand output an output signal. As shown inFIG. 2, two switching circuit units210and215may be provided, and outputs of the respective switching circuit units210and215may be applied to AND gates included in the clock generating unit220as input signals. The AND gates may be used to compare the output signals of the respective switching circuit units210and215with the first and second control signals φ1and φ2and apply a comparison result together with VDT1to RS flip-flops, thereby generating the reference clock signal φHP.

Hereinafter, a detailed operation of the phase shift circuit200shown inFIG. 2will be described with reference to both ofFIG. 2and a timing diagram ofFIG. 3.

Referring toFIG. 3, a gate driving signal GDA having a predetermined period is shown. Hereinafter, for convenience of explanation, it will be assumed that a power factor correction circuit operated by the gate driving signal GDA is a main circuit in a master scheme and a power factor correction circuit operated by the gate driving signal GDB is a sub-circuit in a slave scheme. The main circuit of which an operation is controlled by the gate driving signal GDA may perform a free-running operation regardless of an operation of the sub-circuit in the slave scheme.

First, in a section in which the gate driving signal GDA has a high level, a current IL1of the inductor L1is gradually increased by the input current Iinaccording to an AC input signal. In this case, when the first control signal φ1has a high level, sufficient to turn the first switch group on, the voltage VRT1of the capacitor C1is charged by a current source I1based on the reference voltage VDC.

Therefore, since the voltage VRT1of the capacitor C1is higher than the reference voltage VDC, the comparator of the first switching circuit unit210outputs an output signal having a high level. On the other hand, the second switching circuit unit215operated as opposed to the first switching circuit unit210outputs an output signal having a low level. As a result, both of two AND gates included in the clock generating unit output a signal having a low level, such that the reference clock signal φHPhas a low level.

When a voltage VRT2of a capacitor C2(not shown) included in the second switching circuit unit215rises up to the reference voltage VDCas shown inFIG. 3during a time in which the voltage VRT1of the capacitor C1is maintained as a value higher than the reference voltage VDC, the second switching circuit unit215outputs an output signal having a high level. At the time, since the first control signal φ1is in a state in which it is maintained at the high level, a lower AND gate of the clock generating unit220outputs a signal having a high level, such that the reference clock signal φHPis triggered to have a high level.

Then, when a level of the gate driving signal GDA is changed to a low level and the current IL1of the inductor L1is decreased to reach 0, a pulse is again generated in VDT1, such that a level of the first control signal φ1is changed to a low level and a level of the second control signal φ2is changed to a high level. Therefore, a polarity of a voltage of the capacitor C1in the switching circuit units210and215is reversed, and current sources I1and I2simultaneously supply a current2I to the capacitor C1.

As a result, when a pulse of VDT1is generated, the voltage VRT1of the capacitor C1has an instantaneously changed polarity and is increased at a very high speed, specifically, at a gradient two times higher than that of the previous period to be equal to VDC. On the other hand, VDT2is slowly increased from the reference voltage VDCwhile illustrating a tendency to be the same as that of VDT1of the previous period. At a timing at which the pulse of VDT1is generated, since the VRT1has a value smaller than VDC, that is, the polarity thereof is changed, the first switching circuit unit210outputs a signal having a low level. In addition, the second switching circuit unit215continuously outputs the signal having the high level.

When the pulse is re-generated in VDT1, since the level of the first control signal φ1is changed to the low level and the level of the second control signal φ2is changed to the high level as described above, both of the AND gates of the clock generating unit220output signals having a low level. Therefore, both of output signals of the RS flip-flops also have a low level, and the reference clock signal φHPis triggered from a high level to a low level.

When the capacitor C1simultaneously receives the currents supplied from the current sources I1and I2, such that the voltage VRT1of the capacitor C1is rapidly increased to reach the reference voltage VDC, the comparator of the first switching circuit unit210outputs the signal having the high level, such that an upper AND gate of the clock generating unit220outputs a signal having a high level. Therefore, an output signal of an upper RS flip-flop is triggered to a high level, and the reference clock signal φHPis triggered from a low level to a high level. The phase shift circuit200according to the embodiment of the present invention may repeat the above-mentioned operation to generate the reference clock signal φHP.

Although not shown inFIG. 2, the reference clock signal φHPmay be transferred to a control circuit unit connected to the phase shift circuit200. The control circuit unit may generate a predetermined control signal using the reference clock signal φHPand the voltage pulse signals VDT1and VDT2corresponding to the currents detected from the inductors L1and L2. The control signal generated by the control circuit unit may have a voltage signal form and have a level determined by the reference clock signal φHPand the voltage pulse signal VDT2. Next, a description thereof will be provided with reference toFIG. 4.

FIG. 4is a diagram schematically illustrating a phase shift circuit including the control circuit unit described above.

Referring toFIG. 4, the switching circuit units210and215and the clock generating unit220described with reference toFIG. 2may receive the voltage pulse signal VDT1corresponding to the current flowing in the inductor L1to generate the reference clock signal φHP. The reference clock signal φHPmay be transferred to a control circuit unit410, and the control circuit unit410may generate a control signal VCTRLby using the reference clock signal φHPand the voltage pulse signal VDT2corresponding to the current flowing in the inductor L2.

The control circuit unit410may include two D flip-flops receiving the reference clock signal φHPand the reference voltage VDDor the voltage pulse signal VDT2and the reference voltage VDD, one AND gate, a current source, a switch, and the like. The control circuit unit410shown inFIG. 4is only an example, and is not necessarily limited to having the above-mentioned form.

A level of the control signal VCTRLoutput by the control circuit unit410may be determined by output signals φUPand φDNof the D flip-flops, and the output signals φUPand φDNof the D flip-flops may be determined by the voltage pulse signal VDT2and the reference clock signal φHP. Next, an operation of the control circuit unit410will be described with reference to both of the power factor correction circuit ofFIG. 5and the timing diagram ofFIG. 6.

FIG. 5is a circuit diagram illustrating an example of the power factor correction circuit according to the embodiment of the present invention.

Referring toFIG. 5, the entire configuration of the power factor correction circuit500according to the present embodiment is similar to that of the power factor correction circuit100shown inFIG. 1. The power factor correction circuit500may have an interleaving structure in which two power factor correction circuits are connected to each other in parallel, and switches S1and S2respectively controlling operations of the power factor correction circuits are turned on or turned off by gate driving signals GDA and GDB. For convenience of explanation, it is assumed that a power factor correction circuit including an inductor L1and a switch S1is a main circuit and a power factor correction circuit including an inductor L2and a switch S2is a sub-circuit. That is, the main circuit including the inductor L1and the switch S1may perform a free-running operation regardless of an operation of the sub-circuit.

Currents of the inductors L1and L2may be detected in a zero-crossing scheme, and voltage pulse signals VDT1and VDT2may be generated. The voltage pulse signals VDT1and VDT2generated from the currents of the inductors may be transferred to a controlling unit510, and the controlling unit510may output a control signal VCTRL. The control signal VCTRLhas the same meaning as that of the output control signal described above with reference toFIG. 4. That is, the controlling unit510may include a phase shift circuit. The control signal VCTRLmay be transferred to a ramp generating unit520, and the ramp generating unit520may generate first and second ramp signals VR1and VR2.

The first and second ramp signals VR1and VR2may have a predetermined gradient. For example, the first ramp signal VR1may have a fixed gradient, and the second ramp signal VR2may have a variable gradient. In this case, the gradient of the second ramp signal may be determined according to a level of the control signal VCTRL.

The first and second ramp signals VR1and VR2may be input to comparators530and535, respectively, and be compared with a reference signal VCOMP, respectively. The reference signal VCOMPmay be obtained by comparing an output voltage of the power factor correction circuit with a band gap reference (BGR) signal. In an operation of the main circuit, VCOMPmay be compared with the first ramp signal VR1, and the gate driving signal GDA may be determined according to a magnitude relationship therebetween. When the gate driving signal GDA drops to a low level and thus the switch S1is turned off, the current flowing in the inductor L1is decreased. When the current flowing in the inductor L1is decreased up to 0, a pulse may be generated in the voltage pulse signal VDT1by a current detecting unit505, and an RS flip-flop540may output an output signal having a high level. As described above, the main circuit may perform the free-running operation regardless of the operation of the sub-circuit.

On the other hand, the gate driving signal GDB determining the operation of the sub-circuit may be determined by the ramp signal VR2having the variable gradient. VR2may be determined according to the level of the control signal VCTRL, and the level of the control signal VCTRLmay be controlled by a reference clock signal φHPoutput by the phase shift circuit included in the controlling unit510. In addition, since the reference clock signal φHPis determined by the voltage pulse signal VDT1according to the current flowing in the inductor L1of the main circuit, an operation of the sub-circuit may be affected by the main circuit. Hereinafter, an operation of the sub-circuit and an operation of adjusting a phase of the gate driving signal GDB will be described with reference to a timing diagram ofFIG. 6.

FIG. 6is a timing diagram for describing an operation of the power factor correction circuit shown inFIG. 5. First, the phase shift circuit of the controlling unit510may receive the voltage pulse signal VDT1determined from the current flowing in the inductor L1of the main circuit, as an input signal, as described with reference toFIGS. 2 through 4. In addition, as shown in the timing diagram ofFIG. 3, a phase of the reference clock signal φHPmay have a difference of 180 degrees from the voltage pulse signal VDTs. Therefore, when the gate driving signal GDB is controlled so that a point in time at which the voltage pulse signal VDT2rises from a low level to a high level coincides with a point in time at which the reference clock signal φHPrises, a ripple component, an EMI component, and the like, of the input current may be significantly decreased.

First, in the case that a phase of the voltage pulse signal VDT2leads a phase of the reference clock signal φHP, referring to the control circuit unit410shown inFIG. 4, the output signal φDNof the D flip-flop may have a low level, and the output signal φUPthereof may have a high level. Therefore, since a current is supplied from a current source IUP, a level of the control signal VCTRLmay rise, and the ramp generating unit520may decrease the gradient of the second ramp signal VR2. That is, the second ramp signal VR2shows a tendency to be more slowly increased.

Since the second ramp signal VR2is slowly increased, the comparator535comparing the second ramp signal VR2with the reference signal VCOMPmay output a signal having a low level for a long period of time. As a result, the gate driving signal GDB is maintained at a high level for a long period of time, such that a turn-on time of the switch S2may be lengthened. Therefore, as shown in the timing diagram ofFIG. 6, in the next period, the point in time at which the reference clock signal φHPrises and the point in time at which the voltage pulse signal VDT2rises may become close to each other. When the above-mentioned process is repeated several times, the point in time at which the reference clock signal φHPrises and the point in time at which the voltage pulse signal VDT2rises may coincide with each other.

To the contrary, when the phase of the voltage pulse signal VDT2lags behind the phase of the reference clock signal φHP, the output signal φDNof the D flip-flop of the control circuit unit410may have a high level, and the output signal φUPthereof may have a low level, as opposed to the above-mentioned case. Therefore, the level of the control signal VCTRLdrops, and the gradient of the second ramp signal VR2is increased, such that a turn-on time of the switch S2may be shortened. The above-mentioned operation is repeated several times, whereby the point in time at which the reference clock signal φHPrises and the point in time at which the voltage pulse signal VDT2rises may coincide with each other.

In the phase shift circuit according to the present embodiment described above with reference toFIGS. 1 through 6, the current sources outputting the currents having the same magnitude may be included in the switching circuit units210and215. Therefore, matching characteristics between the current sources are excellent, and a separate state for setting an initial value of the ramp signal is not required, such that a phase difference due to a change in process, voltage, and temperature (PVT) conditions and a mismatch in a process may be decreased. In addition, the phase shift circuit according to the present embodiment may be widely applied to a technology of predicting how much the switching period progresses based on a period of the switching signal, as well as to the power factor correction circuit.

As set forth above, according to the embodiments of the present invention, a phase shift circuit capable of accurately controlling a phase difference between switching devices included in an interleaving-type power factor correction circuit to be a value of 360/n (n indicates the number of power factor correction circuits connected to one another in parallel) may be provided. Therefore, the ripple component and the EMI component included in the input current of the power factor correction circuit may be significantly decreased.