Semiconductor device with graphene-based element and method for fabricating the same

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a stacked gate structure positioned on the substrate; first spacers attached on two sides of the stacked gate structure; and second spacers attached on two sides of the first spacers; wherein the first spacers comprise graphene.

TECHNICAL FIELD

The present disclosure relates to a semiconductor device and a method for fabricating the semiconductor device, and more particularly, to a semiconductor device with a graphene-based element and a method for fabricating the semiconductor device with the graphene-based element.

DISCUSSION OF THE BACKGROUND

Semiconductor devices are used in a variety of electronic applications, such as personal computers, cellular telephones, digital cameras, and other electronic equipment. The dimensions of semiconductor devices are continuously being scaled down to meet the increasing demand of computing ability. However, a variety of issues arise during the scaling-down process, and such issues are continuously increasing. Therefore, challenges remain in achieving improved quality, yield, performance, and reliability and reduced complexity.

SUMMARY

One aspect of the present disclosure provides a semiconductor device including a substrate; a stacked gate structure positioned on the substrate; first spacers attached on two sides of the stacked gate structure; and second spacers attached on two sides of the first spacers; wherein the first spacers comprise graphene.

In some embodiments, the semiconductor device further comprises porous spacers positioned between the first spacers and the second spacers.

In some embodiments, the porous spacers have porosities about 30% and about 90%.

In some embodiments, the stacked gate structure comprises a dielectric layer positioned on the substrate, a bottom conductive layer positioned on the dielectric layer, a top conductive layer positioned on the bottom conductive layer, and a capping layer positioned on the top conductive layer.

In some embodiments, the stacked gate structure further comprises a first middle conductive layer positioned between the bottom conductive layer and the top conductive layer.

In some embodiments, the stacked gate structure further comprises a second middle conductive layer positioned between the first middle conductive layer and the top conductive layer.

In some embodiments, a thickness of the first middle conductive layer is about 2 nm and about 20 nm.

In some embodiments, the semiconductor device further comprises air gap spacers positioned between the first spacers and the second spacers.

Another aspect of the present disclosure provides a method for fabricating a semiconductor device, comprising: providing a substrate; forming a stacked gate structure over the substrate; forming first spacers on sidewalls of the gate stack structure, wherein the first spacers comprise graphene; forming sacrificial spacers on sidewall of the first spacers; and forming second spacers on sidewall of the sacrificial spacers.

In some embodiments, the method for preparing a semiconductor device further comprises: performing an energy treatment to turn the sacrificial spacers into porous spacers.

In some embodiments, the porous spacers have porosities about 30% and about 90%.

In some embodiments, forming a stacked gate structure over the substrate comprises: forming a dielectric layer on the substrate, forming a bottom conductive layer on the dielectric layer, forming a top conductive layer on the bottom conductive layer, forming a capping layer on the top conductive layer; and performing an etch process to form the stacked gate structure.

In some embodiments, forming a stacked gate structure over the substrate further comprises: forming a first middle conductive layer between the bottom conductive layer and the top conductive layer.

In some embodiments, forming a stacked gate structure over the substrate further comprises: forming a second middle conductive layer between the first middle conductive layer and the top conductive layer.

In some embodiments, a thickness of the first middle conductive layer is about 2 nm and about 20 nm.

In some embodiments, the method for preparing a semiconductor device further comprises: performing an energy treatment to turn the sacrificial spacers into air gap spacers between the first spacers and the second spacers.

In some embodiments, forming first spacers on sidewall of the gate stack structure comprises: forming a liner layer covering the substrate and the stacked gate structure, and performing a spacer etching process.

Another aspect of the present disclosure provides a semiconductor device including a substrate, a stacked gate structure positioned on the substrate, first spacers attached on two sides of the stacked gate structure, and second spacers attached on two sides of the first spacers. The first spacers include graphene.

In some embodiments, the semiconductor device includes porous spacers positioned between the first spacers and the second spacers.

In some embodiments, the porous spacers have porosities about 30% and about 90%.

In some embodiments, the stacked gate structure includes a dielectric layer positioned on the substrate, a bottom conductive layer positioned on the dielectric layer, a top conductive layer positioned on the bottom conductive layer, and a capping layer positioned on the top conductive layer.

In some embodiments, the stacked gate structure further includes a first middle conductive layer positioned between the bottom conductive layer and the top conductive layer.

In some embodiments, the stacked gate structure further includes a second middle conductive layer positioned between the first middle conductive layer and the top conductive layer.

In some embodiments, a thickness of the first middle conductive layer is about 2 nm and about 20 nm.

Another aspect of the present disclosure provides a method for fabricating a semiconductor device including providing a substrate, forming a first trench in the substrate, conformally forming a buried dielectric layer in the first trench, conformally forming buried covering layers to cover an upper portion of the first trench, forming a buried conductive layer on the buried dielectric layer, between the buried covering layers, and in the first trench, and forming a buried capping layer on the buried conductive layer. The buried conductive layer comprises graphene.

In some embodiments, the method for fabricating the semiconductor device includes a step of conformally forming a buried barrier layer on the buried dielectric layer and in the first trench.

In some embodiments, the buried covering layers are formed of aluminum oxide, hafnium oxide, zirconium oxide, titanium oxide, titanium nitride, tungsten nitride, silicon nitride, or silicon oxide.

Due to the design of the semiconductor device of the present disclosure, the overall cross-sectional area of the buried conductive layer may be increased by the upper portion of the buried conductive layer. Combining with the good conductivity of the buried conductive layer including graphene, the conductivity and performance of the semiconductor device may be improved. In addition, the presence of the buried covering layers may prevent void formation during fabrication of the semiconductor device. Therefore, the reliability of the semiconductor device may be improved.

DETAILED DESCRIPTION

It should be understood that when an element or layer is referred to as being “connected to” or “coupled to” another element or layer, it can be directly connected to or coupled to another element or layer, or intervening elements or layers may be present.

Unless the context indicates otherwise, terms such as “same,” “equal,” “planar,” or “coplanar,” as used herein when referring to orientation, layout, location, shapes, sizes, amounts, or other measures do not necessarily mean an exactly identical orientation, layout, location, shape, size, amount, or other measure, but are intended to encompass nearly identical orientation, layout, location, shapes, sizes, amounts, or other measures within acceptable variations that may occur, for example, due to manufacturing processes. The term “substantially” may be used herein to reflect this meaning. For example, items described as “substantially the same,” “substantially equal,” or “substantially planar,” may be exactly the same, equal, or planar, or may be the same, equal, or planar within acceptable variations that may occur, for example, due to manufacturing processes.

In the present disclosure, a semiconductor device generally means a device which can function by utilizing semiconductor characteristics, and an electro-optic device, a light-emitting display device, a semiconductor circuit, and an electronic device are all included in the category of the semiconductor device.

It should be noted that, in the description of the present disclosure, above (or up) corresponds to the direction of the arrow of the direction Z, and below (or down) corresponds to the opposite direction of the arrow of the direction Z.

It should be noted that, in the description of the present disclosure, a surface of an element (or a feature) located at the highest vertical level along the direction Z is referred to as a top surface of the element (or the feature). A surface of an element (or a feature) located at the lowest vertical level along the direction Z is referred to as a bottom surface of the element (or the feature).

FIG. 1illustrates, in a schematic cross-sectional view diagram, a semiconductor device3A in accordance with another embodiment of the present disclosure.

With reference toFIG. 1, the semiconductor device3A may include a substrate301, second isolation layers303, second source/drain regions305, a dielectric layer307, a bottom conductive layer309, a first middle conductive layer311, a second middle conductive layer313, a top conductive layer315, a capping layer317, first spacers319, porous spacers321, and second spacers323.

With reference toFIG. 1, the substrate301may be formed of a same material as the substrate101but is not limited thereto. The second isolation layers303may be disposed in the substrate301in a manner similar to that illustrated inFIG. 1. The second isolation layers303may be formed of a same material as the first isolation layers103but is not limited thereto.

With reference toFIG. 1, the dielectric layer307may be disposed on the substrate301. In a cross-sectional perspective, the dielectric layer307may be line shape. The dielectric layer307may be formed of a same material as the buried dielectric layer107but is not limited thereto.

With reference toFIG. 1, the second source/drain regions305may be disposed adjacent to two ends of the dielectric layer307and disposed in the substrate301. The second source/drain regions305may be doped with a dopant such as phosphorus, arsenic, antimony, or boron. The dopant concentration of the second source/drain regions305may have a same dopant concentration as the first source/drain regions105but are not limited thereto.

With reference toFIG. 1, the bottom conductive layer309may be disposed on the dielectric layer307. The bottom conductive layer309may be formed of, for example, a conductive material such as polycrystalline silicon, polycrystalline silicon germanium, or a combination thereof. In some embodiments, the bottom conductive layer309may be doped with a dopant such as phosphorus, arsenic, antimony, or boron.

With reference toFIG. 1, the first middle conductive layer311may be disposed on the bottom conductive layer309. The first middle conductive layer311may have a thickness about 2 nm and about 20 nm. The first middle conductive layer311may be formed of, for example, titanium silicide, nickel silicide, nickel platinum silicide, tantalum silicide, or cobalt silicide. The first middle conductive layer311may serve as ohmic contact and reduce the resistance between the bottom conductive layer309and the top conductive layer315.

With reference toFIG. 1, the second middle conductive layer313may be disposed on the first middle conductive layer311. The second middle conductive layer313may be formed of, for example, tungsten nitride, titanium nitride, tantalum nitride, the like, or a combination thereof. The second middle conductive layer313may be structured to prevent subsequent deposition processes from degrading other layers of the semiconductor device3A. For example, some metals from the top conductive layer315may tend to diffuse into silicon-containing layers (e.g. the bottom conductive layer309) during deposition and even after fabrication has completed.

With reference toFIG. 1, the top conductive layer315may be disposed on the second middle conductive layer313. The top conductive layer315may be formed of, for example, any suitable conductor including tungsten, aluminum, copper, titanium, silver, ruthenium, molybdenum, other suitable metals and alloys thereof.

With reference toFIG. 1, the capping layer317may be disposed on the top conductive layer315. The capping layer317may be formed of a same material as the buried capping layer115but is not limited thereto.

The dielectric layer307, the bottom conductive layer309, the first middle conductive layer311, the second middle conductive layer313, the top conductive layer315, and the capping layer317may together form a stacked gate structure SGS.

With reference toFIG. 1, the first spacers319may be attached on sidewalls of the stacked gate structure SGS. The first spacers319may be disposed on the second source/drain regions305. In some embodiments, the first spacers319may be formed of, for example, graphene. In some embodiments, the first spacers319may be formed of, for example, graphene, graphite, or the like. In some embodiments, the first spacers319may be formed of, for example, a material including sp2hybridized carbon atoms. In some embodiments, the first spacers319may be formed of, for example, a material including carbons having hexagonal crystal structures. The first spacers319formed of graphene may have low sheet resistance. Therefore, the conductivity of the semiconductor device3A including the first spacers319may be improved.

With reference toFIG. 1, the porous spacers321may be attached on the sidewalls of the first spacers319and disposed on the second source/drain regions305. The porous spacers321may have porosities about 30% and about 90%. The porous spacers321may include a skeleton and a plurality of empty spaces disposed among the skeleton. The plurality of empty spaces may connect to each other and may be filled with air. The skeleton may include, for example, silicon oxide, low-dielectric materials, or methylsilsesquioxane. The plurality of empty spaces of the porous spacers321may be filled with air. As a result, a dielectric constant of the porous spacers321may be significantly lower than a layer formed of, for example, silicon oxide. Therefore, the porous spacers321may significantly reduce the parasitic capacitance of the semiconductor device3A. That is, the porous spacers321may significantly alleviate an interference effect between electrical signals induced or applied to the semiconductor device3A.

With reference toFIG. 1, the second spacers323may be attached on sidewalls of the porous spacers321and disposed on the second source/drain regions305. The second spacers323may be formed of, for example, silicon nitride, silicon oxide, silicon oxynitride, silicon nitride oxide, the like, or a combination thereof. The second spacers323may electrically insulate the stacked gate structure SGS from adjacent conductive elements and provide protection to the porous spacers321and the first spacers319.

FIGS. 2 to 4illustrate, in schematic cross-sectional view diagrams, semiconductor devices3B,3C, and3D in accordance with some embodiments of the present disclosure.

With reference toFIG. 2, the semiconductor device3B may have a structure similar to that illustrated inFIG. 1. The same or similar elements inFIG. 2as inFIG. 1have been marked with similar reference numbers and duplicative descriptions have been omitted.

With reference toFIG. 2, a width W1of the dielectric layer307may be greater than a width W2of the bottom conductive layer309. The first spacers319may be disposed on the dielectric layer307. The first spacers319may be electrically insulate from the second source/drain regions305by the dielectric layer307.

With reference toFIG. 3, the semiconductor device3C may have a structure similar to that illustrated inFIG. 1. The same or similar elements inFIG. 3as inFIG. 1have been marked with similar reference numbers and duplicative descriptions have been omitted.

With reference toFIG. 1andFIG. 3, the porosities of the porous spacers321inFIG. 1may be 100%, which means the porous spacers321includes only empty spaces. Consequently, the porous spacers321inFIG. 1may be regarded as air gaps325inFIG. 3. The dielectric constant of the air gaps325are 1.0 which may significantly reduce the parasitic capacitance between the stacked gate structure SGS and horizontally neighboring conductive elements.

With reference toFIG. 4, the semiconductor device3D may have a structure similar to that illustrated inFIG. 1. The same or similar elements inFIG. 4as inFIG. 1have been marked with similar reference numbers and duplicative descriptions have been omitted.

With reference toFIG. 4, the semiconductor device3D may include lightly doped regions327. The lightly doped regions327may be respectively correspondingly disposed adjacent to the two ends of the dielectric layer307and in the substrate301. The first spacers319may be disposed on the lightly doped regions327. The second source/drain regions305may be disposed adjacent to the lightly doped regions327. The lightly doped regions327may be doped with a dopant such as phosphorus, arsenic, antimony, or boron. The dopant concentration of the lightly doped regions327may be less than the dopant concentration of the second source/drain regions305. With the presence of the lightly doped regions327, hot-carrier effect may be reduced.

FIG. 5illustrates, in a flowchart diagram form, a method30for fabricating a semiconductor device3A in accordance with one embodiment of the present disclosure.FIGS. 6 to 15illustrate, in schematic cross-sectional view diagrams, a flow for fabricating the semiconductor device3A in accordance with one embodiment of the present disclosure.

With reference toFIG. 5andFIGS. 6 to 9, at step S31, a substrate301may be provided and a stacked gate structure SGS may be formed on the substrate301.

With reference toFIG. 6, the second isolation layers303may be formed with a procedure similar to the first isolation layers103illustrated inFIG. 4. In some embodiments, the dielectric layer307may be formed on the substrate301by a deposition process such as chemical vapor deposition or atomic layer deposition. In some embodiments, the dielectric layer307may be formed by oxidation. The bottom conductive layer309may be formed on the dielectric layer307by chemical vapor deposition or other suitable deposition process.

With reference toFIG. 7, a layer of conductive material may be formed over the intermediate semiconductor device illustrated inFIG. 6. The conductive material may include, for example, titanium, nickel, platinum, tantalum, or cobalt. A thermal treatment may be subsequently performed. During the thermal treatment, metal atoms of the layer of conductive material may react chemically with silicon atoms of the bottom conductive layer309to form the first middle conductive layer311. The first middle conductive layer311may include titanium silicide, nickel silicide, nickel platinum silicide, tantalum silicide, or cobalt silicide. The thermal treatment may be a dynamic surface annealing process. After the thermal treatment, a cleaning process may be performed to remove the unreacted conductive material. The cleaning process may use etchant such as hydrogen peroxide and an SC-1 solution.

With reference toFIG. 8, a series of deposition processes may be performed to sequentially deposit the second middle conductive layer313, the top conductive layer315, the capping layer317, and the first mask layer401. The series of deposition processes may include chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition, physical vapor deposition, sputtering, or spin coating. The first mask layer401may be patterned to define the position of the stacked gate structure SGS.

With reference toFIG. 9, an etch process may be performed to remove portions of the capping layer317, the top conductive layer315, the second middle conductive layer313, the first middle conductive layer311, the bottom conductive layer309, and the dielectric layer307. The remained portion of the capping layer317, the top conductive layer315, the second middle conductive layer313, the first middle conductive layer311, the bottom conductive layer309, and the dielectric layer307together form the stacked gate structure SGS.

With reference toFIGS. 5 and 10, at step S33, second source/drain regions305may be formed in the substrate301.

With reference toFIG. 10, the second source/drain regions305may be formed adjacent to the stacked gate structure SGS and in the substrate301. The second source/drain regions305may be formed by a procedure similar to the first source/drain regions105illustrated inFIG. 4. An annealing process may be performed to activate the second source/drain regions305. The annealing process may have a process temperature about 800° C. and about 1250° C. The annealing process may have a process duration about 1 millisecond and about 500 milliseconds. The annealing process may be, for example, a rapid thermal anneal, a laser spike anneal, or a flash lamp anneal.

With reference toFIGS. 5, 11, and 12, at step S35, first spacers319may be formed on sidewalls of the stacked gate structure SGS.

With reference toFIG. 11, a liner layer403such as a layer of first conductive material may be formed to cover the top surface of the substrate301and the stacked gate structure SGS. In some embodiments, the layer of first conductive material may be formed including, for example, graphene. In some embodiments, the layer of first conductive material may be formed including, for example, graphene, graphite, or the like. In some embodiments, the layer of first conductive material may be formed including, for example, a material including sp2hybridized carbon atoms. In some embodiments, the layer of first conductive material may be formed including, for example, a material including carbons having hexagonal crystal structures.

In some embodiments, the layer of first conductive material may be formed on a catalyst substrate and then transfer onto the intermediate semiconductor device illustrated inFIG. 10. The catalyst substrate may include nickel, copper, cobalt, platinum, silver, ruthenium, iridium, palladium, alloy of iron and nickel, alloy of copper and nickel, alloy of nickel and molybdenum, alloy of gold and nickel, and alloy of cobalt and copper.

In some embodiments, the layer of first conductive material may be formed with assistances of catalysts. The catalysts may be single crystalline metal or polycrystalline metal, binary alloy, or liquid metal. The single crystalline metal or polycrystalline metal may be, for example, nickel, copper, cobalt, platinum, silver, ruthenium, iridium, or palladium. The binary alloy may be, for example, alloy of iron and nickel, alloy of copper and nickel, alloy of nickel and molybdenum, alloy of gold and nickel, and alloy of cobalt and copper. The liquid metal may be, for example, liquid gallium, liquid indium, or liquid copper.

With reference toFIG. 12, an etch process, spacer etching, such as an anisotropic dry etch process, may be performed to remove portions of the layer of first conductive material and concurrently form the first spacers319.

With reference toFIGS. 5 and 13, at step S37, sacrificial spacers405may be formed on sidewalls of the first spacers319.

With reference toFIG. 13, a layer of energy-removable material may be formed over the intermediate semiconductor device illustrated inFIG. 12. The energy-removable material may include a material such as a thermal decomposable material, a photonic decomposable material, an e-beam decomposable material, or a combination thereof. For example, the energy-removable material may include a base material and a decomposable porogen material that is sacrificially removed upon exposure to an energy source. The base material may include a methylsilsesquioxane based material. The decomposable porogen material may include a porogen organic compound that provides porosity to the base material of the energy-removable material. An etch process, such as an anisotropic dry etch process, may be subsequently performed to remove portions of the layer of energy-removable material and concurrently form the sacrificial spacers405.

With reference toFIGS. 5 and 14, at step S39, second spacers323may be formed on sidewalls of the sacrificial spacers405.

With reference toFIG. 14, a layer of insulating material may be formed over the intermediate semiconductor device illustrated inFIG. 13. The insulating material may be, for example, silicon nitride, silicon oxide, silicon oxynitride, silicon nitride oxide, the like, or a combination thereof. An etch process, such as an anisotropic dry etch process, may be subsequently performed to remove portions of the layer of insulating material and concurrently form the second spacers323.

With reference toFIGS. 5 and 15, at step S41, an energy treatment may be performed to turn the sacrificial spacers405into porous spacers321.

With reference toFIG. 15, an energy treatment may be performed to the intermediate semiconductor device illustrated inFIG. 14by applying an energy source thereto. The energy source may include heat, light, or a combination thereof. When heat is used as the energy source, a temperature of the energy treatment may be about 800° C. and about 900° C. When light is used as the energy source, an ultraviolet light may be applied. The energy treatment may remove the decomposable porogen material from the energy-removable material to generate empty spaces (pores), with the base material remaining in place. After the energy treatment, the sacrificial spacers405may be turned into the porous spacers321.

One aspect of the present disclosure provides a semiconductor device including a substrate, a buried dielectric layer inwardly positioned in the substrate, a buried conductive layer including a lower portion positioned on the buried dielectric layer and an upper portion positioned on the lower portion, a buried capping layer positioned on the upper portion, and buried covering layers positioned between the buried capping layer and the buried dielectric layer and between the upper portion of the buried conductive layer and the buried dielectric layer. The buried conductive layer includes graphene.

Due to the design of the semiconductor device of the present disclosure, the overall cross-sectional area of the buried conductive layer113may be increased by the upper portion113-3of the buried conductive layer113. Combining with the good conductivity of the buried conductive layer113including graphene, the conductivity and performance of the semiconductor device1A may be improved. In addition, the presence of the buried covering layers111may prevent void formation during fabrication of the semiconductor device1A. Therefore, the reliability of the semiconductor device1A may be improved.

One aspect of the present disclosure provides a semiconductor device including a substrate; a stacked gate structure positioned on the substrate; first spacers attached on two sides of the stacked gate structure; and second spacers attached on two sides of the first spacers; wherein the first spacers comprise graphene.

Another aspect of the present disclosure provides a method for fabricating a semiconductor device, comprising: providing a substrate; forming a stacked gate structure over the substrate; forming first spacers on sidewalls of the gate stack structure, wherein the first spacers comprise graphene; forming sacrificial spacers on sidewall of the first spacers; and forming second spacers on sidewall of the sacrificial spacers.