Memory system

According to one or more embodiments, a memory system includes a signal terminal, a power line, a resistance element, a nonvolatile semiconductor memory, and a controller. The resistance element is provided between the signal terminal and the power line. The nonvolatile semiconductor memory is configured to transmit and receive a signal to and from a host device via the signal terminal. The controller is configured to determine whether to connect the signal terminal to the power line via the resistance element.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2020-046067, filed Mar. 17, 2020, the entire contents of which are incorporated herein by reference.

FIELD

BACKGROUND

With a higher functionality of a system, a memory capacity of a nonvolatile semiconductor memory provided in a memory system has increased. For example, as the nonvolatile semiconductor memory, a NAND flash memory has been used for it has a low bit cost and can easily increase its memory capacity.

In a NAND flash memory that confirms to a serial peripheral interface, in order to prevent an operation failure, a pull-up resistor or a pull-down resistor may be connected to one or more signal terminals to which a control signal is input. However, when these signal terminals are used as input and output terminals of data, an unnecessary current may flow via the pull-up resistor or the pull-down resistor.

Hence, there is a need for a memory system capable of preventing unnecessary current flow and reducing operating power.

DETAILED DESCRIPTION

According to one or more embodiments, a memory system includes: a signal terminal; a power line; a resistance element; a nonvolatile semiconductor memory; and a controller. The resistance element is provided between the signal terminal and the power line. The nonvolatile semiconductor memory is configured to transmit and receive a signal to and from a host device via the signal terminal. The selection circuit is configured to determine whether to connect the signal terminal to the power line via the resistance element.

Hereinafter, certain example embodiments will be described with reference to the drawings. In description of the drawings, the same components are denoted by the same reference numerals, and description thereof can be omitted in describing subsequent drawings.

First Embodiment

As shown inFIG. 1, a memory system1according to a first embodiment is configured to be connected to a host device2. The memory system1includes a signal terminal10, a controller20, and a nonvolatile semiconductor memory30. The memory system1further includes a first power line Vcc and a second power line Vss. The second power line Vss has a potential lower than that of the first power line Vcc. The potential of the second power line Vss is a reference potential, for example, a ground potential (GND). Hereinafter, the first power line Vcc and the second power line Vss are collectively referred to as a power line in some contexts.

The memory system1transmits data, which has been input to an interface circuit22of the controller20via the signal terminal10, to the nonvolatile semiconductor memory30. The memory system transmits the data, which has been transmitted from the nonvolatile semiconductor memory30thereto, to the host device2via the interface circuit22and the signal terminal10. The nonvolatile semiconductor memory30is, for example, a NAND flash memory.

The controller20controls transmission and reception of a signal between the host device2and the nonvolatile semiconductor memory30. For example, the controller20controls an operation of writing data into the nonvolatile semiconductor memory30according to a write request from the host device2. The controller20controls an operation of reading data from the nonvolatile semiconductor memory30according to a read request from the host device2.

The controller20includes a selection circuit21. The selection circuit21includes a first selection unit211and a second selection unit212. The first selection unit211includes a first resistance element (hereinafter, referred to as a “pull-up resistor R21”). The first selection unit211selects whether to connect the signal terminal10to the first power line Vcc via the pull-up resistor R21. The second selection unit212includes a second resistance element (hereinafter, referred to as a “pull-down resistor R22”). The second selection unit212selects whether to connect the signal terminal10to the second power line Vss via the pull-down resistor R22.

Hereinafter, the pull-up resistor R21and the pull-down resistor R22are collectively referred to as a “resistance element R20” in some contexts. In the present embodiment, the selection circuit21selects whether to connect the signal terminal10to the power line via the resistance element R20.

The pull-up resistor R21that connects the signal terminal10to the first power line Vcc raises the potential of the signal terminal10. The pull-down resistor R22that connects the signal terminal10to the second power line Vss lowers the potential of the signal terminal10.

A central processing unit (CPU)23of the controller20integrally controls an operation of the memory system1. The CPU23transmits a pull-up signal Pu for controlling an operation of the first selection unit211and a pull-down signal Pd for controlling an operation of the second selection unit212to the selection circuit21as control signals. The setting register24stores information associated with a setting of a connection between the signal terminal10and the power line via the resistance element R20. The CPU23sets the control signal with reference to the setting register24.

The CPU23controls whether the signal terminal10is connected to the first power line Vcc via the pull-up resistor R21using the pull-up signal Pu. The CPU23controls whether the signal terminal10is connected to the second power line Vss via the pull-down resistor R22using the pull-down signal Pd. Hereinafter, a first connection between the signal terminal10and the first power line Vcc via the pull-up resistor R21is also referred to as a “pull-up connection” in some contexts. A second connection between the signal terminal10and the second power line Vss via the pull-down resistor R22is also referred to as a “pull-down connection” in some contexts.

The controller20sets either the pull-up connection or the pull-down connection. Alternatively, the controller20sets neither the pull-up connection nor the pull-down connection.FIG. 2shows an equivalent circuit diagram showing a pull-up connection state.FIG. 3shows an equivalent circuit diagram showing a pull-down connection state.

The memory system1is advantageous, for example, when the interface circuit22includes an input stage shown inFIG. 4.

In the input stage of the interface circuit22shown inFIG. 4, when the signal terminal10receives a signal “1”, a P-channel transistor Tp is turned off and a N-channel transistor Tn is turned on. Therefore, an output terminal Vout is at a low (L) state. When the signal terminal10receives a signal “0”, the P-channel transistor Tp is turned on and the N-channel transistor Tn is turned off. Therefore, the output terminal Vout is at a high (H) state.

On the other hand, when the signal terminal10does not receive a signal or the like, the signal terminal10is at an intermediate state between the signal “1” and the signal “0”, and neither the P-channel transistor Tp nor the N-channel transistor Tn may be in an off state. In this case, a through current flows from the first power line Vcc to the second power line Vss through the P-channel transistor Tp and the N-channel transistor Tn, an operating power increases, and a Vout signal inFIG. 4may become unstable, which may cause a malfunction inside the memory system1.

Therefore, it is effective to connect the pull-up resistor R21to the signal terminal10or to connect the pull-down resistor R22to the signal terminal10. In one embodiment, whether to set the pull-up connection or the pull-down connection for the signal terminal10can be arbitrarily selected according to a use method or the like of the memory system1.

For example, in a case of connection to the host device2outside the memory system1, when the unused signal terminal10and the first power line Vcc are connected on a substrate, an unnecessary current may flow from the first power line Vcc to the second power line Vss via the signal terminal10when the pull-down resistor R22is connected to the signal terminal10. Therefore, the controller20controls the first selection unit211to connect the signal terminal10to the first power line Vcc via the pull-up resistor R21. The controller20sets the pull-up connection and does not set the pull-down connection.

In a case of connection to the host device2outside the memory system1, when the unused signal terminal10and the second power line Vss are connected on the substrate, the unnecessary current may flow from the first power line Vcc to the second power line Vss via the signal terminal10when the pull-up resistor R21is connected to the signal terminal10. Therefore, the controller20controls the second selection unit212to connect the signal terminal10to the second power line Vss via the pull-down resistor R22. The controller20sets the pull-down connection and does not set the pull-up connection.

Selecting whether to connect the signal terminal10to the power line via the resistance element R20may be performed by various methods or configurations. For example, a selection switch may be connected in series with the resistance element R20between the signal terminal10and the power line. Then, the controller20controls the selection switch to set a connection state between the signal terminal10and the power line.

In the present embodiment, as shown inFIG. 5, the first selection unit211includes a first selection switch S21connected in series with the pull-up resistor R21between the signal terminal10and the first power line Vcc. The controller20controls an on and off state of the first selection switch S21using the pull-up signal Pu to set the connection state between the signal terminal10and the first power line Vcc. The second selection unit212includes a second selection switch S22connected in series with the pull-down resistor R22between the signal terminal10and the second power line Vss. The controller20controls an on and off state of the second selection switch S22using the pull-down signal Pd to set the connection state between the signal terminal10and the second power line Vss.

Depending on a use method, a use objective or the like of the memory system1, neither the pull-up resistor R21nor the pull-down resistor R22may be connected to the signal terminal10. In such a case, the controller20sets neither the pull-up connection nor the pull-down connection.

The controller20sets, with reference to the setting register24, either one of the pull-up resistor R21and the pull-down resistor R22to be connected to the signal terminal10, or neither the pull-up resistor R21nor the pull-down resistor R22to be connected to the signal terminal10.FIG. 6shows an example of the setting register24. As shown inFIG. 6, when a setting of the setting register24is (0, 0), the selection circuit21does not set the pull-up connection (Off) and does not set the pull-down connection (Off). When the setting of the setting register24is (0, 1), the selection circuit21does not set the pull-up connection (Off) and sets the pull-down connection (On). When the setting of the setting register24is (1, 0), the selection circuit21sets the pull-up connection (On) and does not set the pull-down connection (Off).

The CPU23transmits the pull-up signal Pu and the pull-down signal Pd associated with the setting of the setting register24to the selection circuit21. For example, when neither pull-up connection nor pull-down connection is set, that is, when the pull-up connection is Off and the pull-down connection is Off, the pull-up signal Pu is “0” and the pull-down signal Pd is “0”. When the pull-down connection is set, that is, when the pull-up connection is Off and the pull-down connection is On, the pull-up signal Pu is “0” and the pull-down signal Pd is “1”. When the pull-up connection is set, that is, when the pull-up connection is On and the pull-down connection is Off, the pull-up signal Pu is “1” and the pull-down signal Pd is “0”.

A user sets the setting register24according to a desired setting for the pull-up connection and the pull-down connection, for example, at a time of starting up the memory system1. The controller20determines the pull-up signal Pu and the pull-down signal Pd with reference to the setting of the setting register24.

The memory system1is applicable to, for example, a memory system including a NAND flash memory that conforms to a serial peripheral interface (SPI). The memory system1conforming to SPI operates in a single SPI mode in which 1-bit data is propagated for one clock, or a quad SPI mode in which 4-bit data is propagated for one clock. Hereinafter, an operation in the single SPI mode is also referred to as an “X1 operation” and an operation in the quad SPI mode is also referred to as an “X4 operation” in some contexts.FIG. 7shows an example of a terminal arrangement of the memory system1conforming to SPI.

FIG. 8shows a function of each terminal of the memory system1shown inFIG. 7. A first pin is a chip select terminal (/CS terminal) that receives a chip select (CS) signal for setting the memory system1in a selected state. A second pin is a serial data output terminal (SO terminal) in the X1 operation and is an IO1 terminal through which serial data propagates in the X4 operation. A third pin is a write protect terminal (/WP terminal) that receives a writ protect (WP) signal for controlling the write operation in the memory system1in the X1 operation and is an IO2 terminal through which the serial data propagates in the X4 operation. A fourth pin is a Vss terminal that receives a voltage set for the second power line Vss.

A fifth pin is a serial data input terminal (SI terminal) in the X1 operation and is an IO0 terminal through which the serial data propagates in the X4 operation. A sixth pin is a serial clock terminal (SCK terminal) that receives a serial clock signal SCK. A seventh pin is a hold terminal (/HOLD terminal) that receives a HOLD signal for controlling interruption of input and output of the serial data in the X1 operation and is an IO3 terminal through which the serial data propagates in the X4 operation. An eighth pin is a Vcc terminal that receives a voltage set for the first power line Vcc.

When the memory system1is set to the selected state, the /CS terminal is set to the L state. Then, in the X1 operation of the memory system1, the host device2transmits an H state signal to the /HOLD terminal. When the /HOLD terminal receives an L state signal, an operation is temporarily suspended without setting the memory system1in a non-selected state.

In order to prevent an unintended write operation, an unintended erasing operation and the like in the nonvolatile semiconductor memory30, the memory system1has a block lock function. The block lock function is released by changing a BL bit register in the memory system1. When the BL bit register is changed, the H state signal is transmitted from the host device2to the /WP terminal. On the other hand, when the /WP terminal receives the L state signal and a BRWD bit register is “1”, the BL bit register cannot be changed.

Depending on a use state or the like of the memory system1, a control signal may not be input to the /HOLD terminal or the /WP terminal. In that case, a through current flows from the first power line Vcc to the second power line Vss through the P-channel transistor Tp and the N-channel transistor Tn. An unintended and unnecessary current (through current) maybe generated inside the memory system1, and a Vout signal may become unstable and thus may malfunction inside the memory system1. Setting the pull-up connection or the pull-down connection to the /HOLD terminal or the /WP terminal is effective in preventing the through current and the malfunction.

However, in the X4 operation, the /HOLD terminal and /WP terminal are used as IO terminals through which data propagates. Therefore, when the pull-up resistor R21or the pull-down resistor R22is connected to the /HOLD terminal and /WP terminal, the current flows via the pull-up resistor R21or the pull-down resistor R22when the write data is transferred from the host device2. As a result, the operating power of the memory system1is increased.

In contrast, in the memory system1, the selection circuit21selects whether to connect the /HOLD terminal and the /WP terminal to the power line via the resistance element R20. For example, in the X1 operation, the selection circuit21connects the /HOLD terminal and the /WP terminal to the power line via the resistance element R20. Then, in the X4 operation, the selection circuit21does not connect the /HOLD terminal and /WP terminal to the power line via the resistance element R20. When either one of the /HOLD terminal and the /WP terminal is connected to the power line via the resistance element R20, the selection circuit21selects a setting of a connection for at least the terminal to which the resistance element R20is connected.

The setting register24is used for setting each of the /HOLD terminal and the /WP terminal. With reference to the setting register24, the controller20independently sets either pull-up connection or pull-down connection or sets neither pull-up connection nor pull-down connection for each of the /HOLD terminal and the /WP terminal.

The controller20can dynamically change the connection state between the signal terminal10and the power line without stopping the operation of the memory system1according to a signal transmitted from the host device2to the memory system1to switch between the single SPI mode and the quad SPI mode. For example, at a timing of switching from the quad SPI mode to the single SPI mode, the controller20dynamically changes a state in which the resistance element R20is disconnected from between the signal terminal10and the power line to a state in which the signal terminal10is connected to the power line via the resistance element R20. At a timing of switching from the single SPI mode to the quad SPI mode, the controller20dynamically changes the state in which the signal terminal10is connected to the power line via the resistance element R20to the state in which the resistance element R20is disconnected from between the signal terminal10and the power line.

The memory system1conforming to SPI executes signal input in the quad SPI mode, for example, as in a timing chart shown inFIG. 9. The host device2asserts the CS signal (or sets the CS signal to the L state) and transmits a write command CMD to the SI terminal. Further, the host device2transmits the serial clock signal SCK to the SCK terminal. By receiving the write command CMD in the quad SPI mode, the memory system1starts to receive data in the quad SPI mode. The write command CMD in the quad SPI mode is, for example, “32h”, “34h/C4h”, or the like.

As shown inFIG. 9, the host device2transmits a dummy bit DMY to the SI terminal subsequent to the write command CMD in the quad SPI mode. Next, the host device2transmits an address signal ADD specifying an address to which data is to be written to the SI terminal. The address signal ADD is, for example, an address for specifying a column in a page in the NAND flash memory. Thereafter, the host device2transmits data signals Byte1, Byte2, etc., which are write data, to the IO0 terminal to the IO3 terminal.

In a series of operations of the memory system1, when the SI terminal receives the write command CMD in the quad SPI mode, the controller20transmits the pull-up signal Pu and the pull-down signal Pd to the selection circuit21. The selection circuit21disconnects the resistance element R20from the signal terminal10in a data transfer phase according to the pull-up signal Pu and the pull-down signal Pd. Accordingly, the operating power due to the connection of the pull-up resistor R21and the pull-down resistor R22to the signal terminal10can be reduced.

After a series of operations according to an external command transmitted from the host device2to the memory system1is completed, the controller20may transmit the pull-up signal Pu and the pull-down signal Pd to the selection circuit21and connect the signal terminal10to the power line via the resistance element R20. For example, at a timing when the H state CS signal is received from the host device2, the controller20transmits the pull-up signal Pu and the pull-down signal Pd to the selection circuit21.

In this way, the memory system1can dynamically change a state in which the pull-up resistor R21or the pull-down resistor R22is connected to the signal terminal10and a state in which the pull-up resistor R21or the pull-down resistor R22is not connected to the signal terminal10while continuing the operation of the memory system1.

In the first embodiment, it is possible to dynamically connect or disconnect the pull-up resistor R21or the pull-down resistor R22and the signal terminal10. Accordingly, the operating power in the memory system1can be reduced. For example, the memory system1conforming to SPI prevents the current flowing via the pull-up resistor R21and the pull-down resistor R22in the X4 operation and reduces the operating power.

The host device2may be an information processing device which is a personal computer or the like, a mobile phone, an imaging device, or a mobile terminal which is a tablet computer, a smartphone, or the like. Alternatively, the host device2may be a game device, or may be an in-vehicle terminal such as a car navigation system. The host device2may be a microprocessor in an information processing device, a mobile phone, a mobile terminal, an in-vehicle terminal, or the like.

Although certain example cases have been described as for which the nonvolatile semiconductor memory30is a NAND flash memory, the nonvolatile semiconductor memory30may be another type of nonvolatile semiconductor memory.

Modified Embodiments

In the first embodiment, the memory system1or the selection circuit21comprises both the pull-up resistor R21and the pull-down resistor R22as shown inFIG. 1. In one modified embodiment, if the pull-down resistor R22is not required to be connected to the signal terminal10, the selection circuit21may include the first selection unit211and may not include the second selection unit212as shown inFIG. 10.

In one modified embodiment, if the pull-up resistor R21is not required to be connected to the signal terminal10, the selection circuit21may include the second selection unit212and may not include the first selection unit211as shown inFIG. 11. In a further modified embodiment, a configuration of the memory system1shown inFIGS. 10 and 11can be further simplified.

Second Embodiment

The memory system1according to a second embodiment comprises a resistance element R20whose resistance value is variable as shown inFIG. 12. The controller20selects the resistance value of the resistance element R20from a plurality of candidate resistance values.

In the memory system1shown inFIG. 12, the resistance value of the pull-up resistor R21provided in the first selection unit211is variable, and the resistance value of the pull-down resistor R22provided in the second selection unit212is variable. Other configurations are substantially the same as those in the first embodiment shown inFIG. 1.

In some instances, the selection circuit21may include the resistance element R20which is a variable resistor whose resistance value can be changed using an electric signal or the like. In other instances, the selection circuit21may include a plurality of resistance elements having mutually different resistance values. The selection circuit21including the plurality of resistance elements selects one resistance element as the resistance element R20from the plurality of resistance elements according to the pull-up signal Pu and the pull-down signal Pd. For example, the plurality of resistor elements and a switch that switches connection of these resistance elements are connected in series between a power line and the signal terminal10. Then, the controller20controls a setting of the switch to set the resistance value of the resistance element R20.

The memory system1shown inFIG. 12includes a resistance value selection setting register25associated with the plurality of candidate resistance values that can be set for the resistance element R20. With reference to a setting of the resistance value selection setting register25, the controller20selects the resistance value of the resistance element R20from the plurality of candidate resistance values.

FIG. 13shows an example of correspondence between the setting of the resistance value selection setting register25and the candidate resistance values. As shown inFIG. 13, the controller20selects the candidate resistance value of 1 kΩ when the setting of the resistance value selection setting register25is (0, 0). The controller20selects the candidate resistance value of 10 kΩ when the setting of the resistance value selection setting register25is (0, 1). The controller20selects the candidate resistance value of 50 kΩ when the setting of the resistance value selection setting register25is (1, 0). The controller20selects the candidate resistance value of 100 kΩ when the setting of the resistance value selection setting register25is (1, 1). For example, when the memory system1is started up, the resistance value selection setting register25is set by a user or the like so as to correspond to a desired resistance value of the resistance element R20.

In one embodiment, as shown inFIG. 14, the memory system1conforming to SPI includes the setting register24and the resistance value selection setting register25for each of a /HOLD terminal and a /WP terminal. With reference to the setting register24and the resistance value selection setting register25, the controller20sets either one of the pull-up resistor R21and the pull-down resistor R22to be connected to the /HOLD terminal and /WP terminal or sets neither the pull-up resistor R21nor the pull-down resistor R22to be connected to the /HOLD terminal and /WP terminal, including the resistance value of the resistance element R20. Therefore, in the memory system1shown inFIG. 12, the pull-up signal Pu and the pull-down signal Pd are control signals of a large number of bits associated with the setting of the setting register24and the setting of the resistance value selection setting register25. The setting of the resistance value selection setting register25regarding the pull-up resistor R21is more effective in a case where the pull-up connection is set. The setting of the resistance value selection setting register25regarding the pull-down resistor R22is more effective in a case where the pull-down connection is set.

By reducing the resistance value of the resistance element R20, time until a potential of the signal terminal10becomes stable can be shortened at a time of connection to the power line via the resistance element R20. Malfunction of the memory system1when noise is applied to the signal terminal10can be reduced. Furthermore, by increasing the resistance value of the resistance element R20, the current flowing via the resistance element R20can be reduced.

In the second embodiment, the resistance value of each of the pull-up resistor R21and the pull-down resistor R22as well as connection and disconnection of the pull-up resistor R21and the pull-down resistor R22can be arbitrarily selected by, for example, a user. Accordingly, a degree of design freedom regarding the memory system1is improved. The resistance value of one of the pull-up resistor R21and the pull-down resistor R22may be variable, and the resistance value of the rest of the pull-up resistor R21and the pull-down resistor R22may be fixed.