METHOD FOR IDENTIFYING LATCH-UP STRUCTURE

A method for identifying a latch-up structure includes the following operations. In a chip layout, a first P-type heavily doped region connected to a ground pad and located in a P-type substrate is found, and a first N-type heavily doped region connected to a power pad and located in an N-well is found. A second N-type heavily doped region adjacent to the first P-type heavily doped region and located in the P-type substrate is found. A second P-type heavily doped region adjacent to the first N-type heavily doped region and located in the N-well is found, the N-well is located on the P-type substrate. An area that is formed by the first P-type heavily doped region, the first N-type heavily doped region, the second P-type heavily doped region, the second N-type heavily doped region, the N-well, and the P-type substrate is identified as the latch-up structure.

BACKGROUND

Reliability becomes increasingly important for semiconductor products, and latch-up is an extremely important item in reliability of semiconductor products. In a designed integrated circuit product, there may be various latch-up paths, and particularly in circuits connected to power pads (Power PAD), it is important to effectively inspect these possible latch-up paths and inspect their safety with existing design rules.

SUMMARY

The embodiments of the present disclosure relates to a method of an Electro-Static discharge (ESD) protection circuit of a semiconductor integrated circuit, and particularly provide a method for identifying a latch-up structure.

According to a first aspect of the embodiments of the present disclosure, a method for identifying a latch-up structure is provided. The method includes the following operations. In a chip layout, a first P-type heavily doped region connected to a ground pad and located in a P-type substrate is found, and a first N-type heavily doped region connected to a power pad and located in an N-well is found.

A second N-type heavily doped region adjacent to the first P-type heavily doped region and located in the P-type substrate is found.

A second P-type heavily doped region adjacent to the first N-type heavily doped region and located in the N-well is found, the N-well is located on the P-type substrate.

An area that is formed by the first P-type heavily doped region, the first N-type heavily doped region, the second P-type heavily doped region, the second N-type heavily doped region, the N-well, and the P-type substrate is identified as the latch-up structure.

According to a second aspect of the embodiments of the present disclosure, a method for identifying a latch-up structure is provided, the method may include the following operations.

In a chip layout, a first P-type heavily doped region connected to a ground pad and located in a P-type substrate is found, and a first N-type heavily doped region connected to a power pad and located in a second N-well is found.

A second N-type heavily doped region adjacent to the first P-type heavily doped region and located in a first N-well is found.

A second P-type heavily doped region adjacent to the first N-type heavily doped region and located in the second N-well is found, both the first N-well and the second N-well are located on the P-type substrate.

An area that is formed by the first P-type heavily doped region, the first N-type heavily doped region, the second P-type heavily doped region, the second N-type heavily doped region, the first N-well, the second N-well, and the P-type substrate is identified as the latch-up structure.

According to a third aspect of the embodiments of the present disclosure, a method for identifying a latch-up structure is provided. The method includes the following operations.

In a chip layout, a first P-type heavily doped region connected to a ground pad and located in a P-type substrate is found, and a first N-type heavily doped region connected to a power pad and located in a second N-well is found.

A second N-type heavily doped region adjacent to the first P-type heavily doped region and located in a deep N-well is found.

A second P-type heavily doped region adjacent to the first N-type heavily doped region and located in the second N-well is found, the deep N-well is located in a first N-well, both the first N-well and the second N-well are located on the P-type substrate.

An area that is formed by the first P-type heavily doped region, the first N-type heavily doped region, the second P-type heavily doped region, the second N-type heavily doped region, the deep N-well, the first N-well, the second N-well, and the P-type substrate is identified as the latch-up structure.

REFERENCE NUMERALS

DETAILED DESCRIPTION

Exemplary implementations disclosed in the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary implementations of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited by the specific embodiments described herein. On the contrary, these implementations are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

In the following description, numerous specific details are given in order to provide a more thorough understanding of the present disclosure. However, it would be apparent to those skilled in the art that the present disclosure may be implemented without one or more of these details. In other examples, some technical features known in the art are not described in order to avoid confusion with the present disclosure. That is, not all features of the actual embodiments are described herein, and well-known functions and structures are not described in detail.

In the accompanying drawings, the dimensions of the layers, regions, elements and their relative dimensions may be exaggerated for clarity. The same reference numerals indicate the same elements throughout.

It should be understood that when an element or layer is referred to as being “on . . . ”, “adjacent to . . . ”, and “connected to . . . ” or “coupled to . . . ” other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as being “directly on . . . ”, “directly adjacent to . . . ”, “directly connected to . . . ” or “directly coupled to . . . ” other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third and the like may be used to describe various elements, components, regions, layers and/or portions, these elements, components, regions, layers and/or portions should not be limited by these terms. These terms are used merely to distinguish one element, component, region, layer or portion from another element, component, region, layer or portion. Thus, without departing from the teachings of the present disclosure, a first element, component, region, layer or portion discussed below may be represented as a second element, component, region, layer or portion. And when the second element, component, region, layer or portion is discussed, it does not indicate that the first element, component, region, layer or portion is necessarily present in the present disclosure necessarily.

Spatial relationship terms such as “under . . . ”, “below . . . ”, “below”, “underneath . . . ”, “on . . . ”, “above” may be used herein for ease of description to describe the relationship of one element or feature shown in the figure to other elements or features. It should be understood that, in addition to the orientation shown in the drawings, spatial relationship terms are intended to encompass different orientations of devices in use and operation. For example, if the device in the drawings is turned over, then an element or feature described as “below other elements”, “underneath other elements”, “under other elements” will be oriented “above” other element or feature. Thus, the exemplary terms “under . . . ”, “below . . . ” may encompass both top and bottom orientations. The device may be additionally oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein are interpreted accordingly.

The term used herein is only for a purpose of describing specific embodiments and is not intended as a limitation of the present disclosure. When used herein, the singular form “a”, “one” and “said/the” are also intended to include the plural form unless the context clearly indicates otherwise. It shall also be understood that the terms “composition” and/or “inclusion”, when used in this specification, determine the presence of the features, integers, steps, operations, elements and/or components, but the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups is not precluded. As used herein, the term “and/or” includes any and all combinations of the items listed herein. For example, “A and/or B” may have three meanings: A exists alone, A and B exist at the same time and B exists alone.

In order to fully understand the present disclosure, detailed steps and detailed structures will be proposed in the following description to illustrate the technical solutions of the present disclosure. Preferred embodiments of the present disclosure are described as follows in detail. However, other implementations in addition to these detailed descriptions may also be included in the present disclosure.

The identification and inspection of a parasitic latch-up path in current integrated circuits can ensure that an integrated circuit products do not fail due to latch-up, thus ensuring the reliability of the product. However, at present, there is generally no set of reliable, effective and comprehensive method for identifying and inspecting a parasitic latch-up path, which is a major challenge for prevention of latch-up.

The method for identifying a latch-up structure provided by the present disclosure will be described in detail below through specific embodiments.FIGS.1A to7Cillustrate a total of seven methods for identifying a latch-up structure. For different latch-up structures, the positions of a first N-type heavily doped region, a first P-type heavily doped region, a second N-type heavily doped region and a second P-type heavily doped region are arranged to be different. It should be noted that inFIGS.1A to7C, the P-type heavily doped regions are abbreviated as P+, the N-type heavily doped region are abbreviated as N+, a ground pad is abbreviated as VSS, and a power pad is abbreviated as VDD.

FIG.1Ais a schematic flowchart of a method for identifying a latch-up structure according to an embodiment of the present disclosure. As illustrated, the method includes the following operations.

In101, in a chip layout, a first P-type heavily doped region connected to a ground pad and located in a P-type substrate is found, and a first N-type heavily doped region connected to a power pad and located in an N-well is found.

In102, a second N-type heavily doped region adjacent to the first P-type heavily doped region and located in the P-type substrate is found.

In103, a second P-type heavily doped region adjacent to the first N-type heavily doped region and located in the N-well is found, the N-well is located on the P-type substrate. An area that is formed by the first P-type heavily doped region, the first N-type heavily doped region, the second P-type heavily doped region, the second N-type heavily doped region, the N-well, and the P-type substrate is identified as the latch-up structure.

The method for identifying a latch-up structure provided in the embodiments of the present disclosure is further described in detail below with reference to specific embodiments.

FIG.1Bis a top view of a latch-up structure provided in an embodiment of the present disclosure.FIG.1Cis a sectional view of a latch-up structure provided in an embodiment of the present disclosure.

Before the operation in101is performed, the ground pad and power pad are found, the power pad includes pad such as VDD PAD, VDDQ PAD and the like.

Next, as illustrated inFIG.1C, the operation in101is performed. In a chip layout, a first P-type heavily doped region11connected to a ground pad and located in a P-type substrate15is found, and a first N-type heavily doped region12connected to a power pad and located in a N-well16is found.

In one embodiment, the operation that the first P-type heavily doped region11connected to the ground pad and located in the P-type substrate15is found, includes the following operation. The first P-type heavily doped region11directly or indirectly connected to the ground pad and located in the P-type substrate15is found.

The operation that the first N-type heavily doped region12connected to the power pad and located in the N-well16is found, includes the following operation. The first N-type heavily doped region12directly or indirectly connected to the power supply pad and located in the N-well16is found.

Here, the operation that the first P-type heavily doped region11directly connected to the ground pad is found and the operation that the first N-type heavily doped region12directly connected to the power pad is found, mean that the ground pad is directly connected to the first P-type heavily doped region11and the power pad is directly connected to the first N-type heavily doped region12without other devices.

The operation that the first P-type heavily doped region11indirectly connected to the ground pad is found and the operation that the first N-type heavily doped region12indirectly connected to the power pad is found, mean that the ground pad may be connected to the first P-type heavily doped region11and the power pad may be connected to the first N-type heavily doped region12, respectively, by means of a high current conducting path. Specifically, for example, it may be connected by a resistor having low resistance, a switching device or a diode. More specifically, the ground pad may be connected to the first P-type heavily doped region11by means of a forward diode, and the power pad may be connected to the first N-type heavily doped region12by means of a backward diode.

Next, the operation in102is performed. A second N-type heavily doped region13adjacent to the first P-type heavily doped region11and located in the P-type substrate15is found.

In this embodiment, the second N-type heavily doped region13is connected to the ground pad.

The second N-type heavily doped region13may be directly or indirectly connected to the ground pad. The indirect connection includes a connection by means of a high current conducting path. Specifically, for example, it may be connected by a resistor having low resistance, a switching device or a diode.

Next, the operation in103is performed. A second P-type heavily doped region14adjacent to the first N-type heavily doped region12and located in the N-well16is found. The N-well16is located on the P-type substrate15. An area that is formed by the first P-type heavily doped region11, the first N-type heavily doped region12, the second P-type heavily doped region14, the second N-type heavily doped region13, the N-well16, and the P-type substrate15is identified as the latch-up structure.

In this embodiment, the second P-type heavily doped region14is connected to the power pad.

The second P-type heavily doped region14may be directly or indirectly connected to the power pad. The indirect connection includes a connection by means of a high current conducting path. Specifically, for example, it may be connected by a resistor having low resistance, a switching device or a diode.

In one embodiment, the operation that the second N-type heavily doped region13adjacent to the first P-type heavily doped region11and located in the P-type substrate15is found that by taking the first P-type heavily doped region11as a center and taking a preset distance as a radius, the second N-type heavily doped region13is identified, a distance of which to the first P-type heavily doped region11is less than the preset distance; and/or, the operation that the second P-type heavily doped region14adjacent to the first N-type heavily doped region12and located in the N-well16is found, includes that by taking the first N-type heavily doped region12as a center and taking a preset distance as a radius, the second P-type heavily doped region14is identified, a distance of which to the first N-type heavily doped region12is less than the preset distance.

In one embodiment, as illustrates inFIG.1B, there is a first distance L1between the first P-type heavily doped region11and the second N-type heavily doped region13, a second distance L2between the second N-type heavily doped region13and the second P-type heavily doped region14, and a third distance L3between the second P-type heavily doped region14and the first N-type heavily doped region12.

The operation that by taking the first P-type heavily doped region11as a center and taking a preset distance as a radius, the second N-type heavily doped region13is identified, a distance of which to the first P-type heavily doped region11is less than the preset distance, specifically includes: the first distance is less than the preset distance.

The operation that, by taking the first N-type heavily doped region12as a center and taking a preset distance as a radius, the second P-type heavily doped region14is identified, a distance of which to the first N-type heavily doped region12is less than the preset distance, specifically includes: the third distance is less than the preset distance.

Furthermore, as illustrated inFIG.1C, the N-well16, the P-type substrate15, and the second N-type heavily doped region13constitute a first parasitic NPN transistor T1. The second P-type heavily doped region14, the N-well16, and the P-type substrate15constitute a first parasitic PNP transistor T2.

The P-type substrate15has a first parasitic resistor RPW, a first end of which is connected to the first P-type heavily doped region11, and a second end of which is connected to a base electrode of the first parasitic NPN transistor T1.

The N-well16has a second parasitic resistor RNW, a first end of which is connected to the first N-type heavily doped region12, and a second end of which is connected to a base electrode of the first parasitic PNP transistor T2.

The following describes a principle of generating a latch-up effect in the latch-up structure. Specifically, T2is a vertical PNP transistor, the base electrode is an N-well, a gain from the base electrode to a collector electrode may reach tens of times, T1is a side NPN transistor, the base electrode is a P-type substrate, a gain from the base electrode to the collector electrode may reach tens of times, RNWis a parasitic resistor of the N-well, and Rpw is a parasitic resistor of the P-type substrate.

The above four elements T1, T2, RNWand RPWconstitute a silicon controlled circuit. When there is no external interference and no trigger is caused, the two transistors are in a turned-off state, a collector electrode current is formed by a reverse leakage current of C-B, and a current gain is extremely small, so a latch-up effect will not occur at this time. When a collector electrode current of one of the transistors suddenly increases to a certain value due to external interference, a feedback is sent to the other transistor, so that the two transistors are triggered to be turned on (generally, PNP is easier to be triggered), and a low-impedance path is formed between the power pad VDD and the ground pad VSS. Then, even if the external interference disappears, because a positive feedback is formed between the two triodes, there will still be a leakage current between the power pad VDD and the ground pad VSS, that is, a locked state. This results in a latch-up effect.

FIG.2Ais a schematic flowchart of a method for identifying a latch-up structure provided in an embodiment of the present disclosure. As illustrated, the method includes the following operations:

In201, in a chip layout, a first P-type heavily doped region connected to a ground pad and located in a P-type substrate is found, and a first N-type heavily doped region connected to a power pad and located in a second N-well is found.

In202, a second N-type heavily doped region adjacent to the first P-type heavily doped region and located in a first N-well is found.

In203, a second P-type heavily doped region adjacent to the first N-type heavily doped region and located in the second N-well is found. Both the first N-well and the second N-well are located on the P-type substrate. An area that is formed by the first P-type heavily doped region, the first N-type heavily doped region, the second P-type heavily doped region, the second N-type heavily doped region, the first N-well, the second N-well, and the P-type substrate is identified as the latch-up structure.

The method for identifying a latch-up structure provided in the embodiments of the present disclosure is further described in detail below with reference to specific embodiments.

FIG.2Bis a top view of a latch-up structure provided in an embodiment of the present disclosure.FIG.2Cis a sectional view of a latch-up structure provided in an embodiment of the present disclosure.

Before the operation in201is performed, the ground pad and power pad are found, the power pad includes pad such as VDD PAD, VDDQ PAD and the like.

Next, as illustrated inFIG.2C, the operation in201is performed. In a chip layout, a first P-type heavily doped region21connected to a ground pad and located in a P-type substrate25is found, and a first N-type heavily doped region22connected to a power pad and located in the second N-well27is found.

In one embodiment, the operation that the first P-type heavily doped region21connected to the ground pad and located in the P-type substrate25is found, includes the following operation. The first P-type heavily doped region21directly or indirectly connected to the ground pad and located in the P-type substrate25is found.

The operation that the first N-type heavily doped region22connected to the power pad and located in the second N-well27includes the following operation. The first N-type heavily doped region22directly or indirectly connected to the power supply pad and located in the second N-well27is found.

Here, the operation that the first P-type heavily doped region21directly connected to the ground pad is found, and the operation that the first N-type heavily doped region22directly connected to the power pad is found, mean that the ground pad is directly connected to the first P-type heavily doped region21and the power pad is directly connected to the first N-type heavily doped region22without other devices.

The operation that the first P-type heavily doped region21indirectly connected to the ground pad is found and the operation that the first N-type heavily doped region22indirectly connected to the power pad is found, mean that the ground pad may be connected to the first P-type heavily doped region21and the power pad may be connected to the first N-type heavily doped region22, respectively, by means of a high current conducting path. Specifically, for example, it may be connected by a resistor having low resistance, a switching device or a diode. More specifically, the ground pad may be connected to the first P-type heavily doped region21by means of a forward diode, and the power pad may be connected to the first N-type heavily doped region22by means of a backward diode.

Next, the operation in202is performed. A second N-type heavily doped region23adjacent to the first P-type heavily doped region21and located in the first N-well26is found.

In this embodiment, the second N-type heavily doped region23is connected to the ground pad.

The second N-type heavily doped region23may be directly or indirectly connected to the ground pad. The indirect connection includes a connection by means of a high current conducting path. Specifically, for example, it may be connected by a resistor having low resistance, a switching device or a diode.

Next, the operation in203is performed. A second P-type heavily doped region24adjacent to the first N-type heavily doped region22and located in the second N-well27is found. Both the first N-well26and the second N-well27are located on the P-type substrate25. An area that is formed by the first P-type heavily doped region21, the first N-type heavily doped region22, the second P-type heavily doped region24, the second N-type heavily doped region23, the first N-well26, the second N-well27and the P-type substrate25is identified as the latch-up structure.

In this embodiment, the second P-type heavily doped region24is connected to the power pad.

The second P-type heavily doped region24may be directly or indirectly connected to the power pad. The indirect connection includes a connection by means of a high current conducting path. Specifically, for example, it may be connected by a resistor having low resistance, a switching device or a diode.

In one embodiment, the operation that the second N-type heavily doped region23adjacent to the first P-type heavily doped region21and located in the first N-well26is found, includes that by taking the first P-type heavily doped region21as a center and taking a preset distance as a radius, the second N-type heavily doped region23is identified, a distance of which to the first P-type heavily doped region21is less than the preset distance; and/or, the operation that the second P-type heavily doped region24adjacent to the first N-type heavily doped region22and located in the second N-well27is found, includes that by taking the first N-type heavily doped region22as a center and taking a preset distance as a radius, the second P-type heavily doped region24is identified, a distance of which to the first N-type heavily doped region22is less than the preset distance.

In one embodiment, as illustrates inFIG.2B, there is a first distance L1between the first P-type heavily doped region21and the second N-type heavily doped region23, a second distance L2between the second N-type heavily doped region23and the second P-type heavily doped region24, and a third distance L3between the second P-type heavily doped region24and the first N-type heavily doped region22.

The operation that, by taking the first P-type heavily doped region21as a center and taking a preset distance as a radius, the second N-type heavily doped region23is identified, a distance of which to the first P-type heavily doped region21is less than the preset distance, specifically includes: the first distance is less than the preset distance.

The operation that, by taking the first N-type heavily doped region22as a center and taking a preset distance as a radius, the second P-type heavily doped region24is identified, a distance of which to the first N-type heavily doped region22is less than the preset distance is identified, specifically includes: the third distance is less than the preset distance.

Furthermore, as illustrated inFIG.2C, the second N-well27, the P-type substrate25, and the second N-type heavily doped region23constitute a first parasitic NPN transistor T1. The second P-type heavily doped region24, the second N-well27, and the P-type substrate25constitute a first parasitic PNP transistor T2.

The P-type substrate25has a first parasitic resistor RPW, a first end of which is connected to the first P-type heavily doped region21, and a second end of which is connected to a base electrode of the first parasitic NPN transistor T1.

The second N-well27has a second parasitic resistor RNW, a first end of which is connected to the first N-type heavily doped region22, and a second end of which is connected to a base electrode of the first parasitic PNP transistor T2.

The following describes a principle of generating a latch-up effect in the latch-up structure. Specifically, T2is a vertical PNP transistor, the base electrode is an N-well, a gain from the base electrode to a collector electrode may reach tens of times, T1is a side NPN transistor, the base electrode is a P-type substrate, a gain from the base electrode to the collector electrode may reach tens of times, RNWis a parasitic resistor of the N-well, and Rpw is a parasitic resistor of the P-type substrate.

The above four elements T1, T2, RNWand RPWconstitute a silicon controlled circuit. When there is no external interference and no trigger is caused, the two transistors are in a turned-off state, a collector electrode current is formed by a reverse leakage current of C-B, and a current gain is extremely small, so the latch-up effect will not occur at this time. When a collector electrode current of one of the transistors suddenly increases to a certain value due to external interference, a feedback is sent to the other transistor, so that the two transistors are triggered to be turned on (generally, the PNP is easier to be triggered), and a low-impedance path is formed between the power pad VDD and the ground pad VSS. Then, even if the external interference disappears, because a positive feedback is formed between the two triodes, there will still be a leakage current between the power pad VDD and the ground pad VSS, that is, a locked state. This results in a latch-up effect.

FIG.3Ais a schematic flowchart of a method for identifying a latch-up structure provided in an embodiment of the present disclosure. As illustrated, the method includes the following operations.

In301, in a chip layout, a first P-type heavily doped region connected to a ground pad and located in a P-type substrate is found, and a first N-type heavily doped region connected to a power pad and located in a second N-well is found.

In302, a second N-type heavily doped region adjacent to the first P-type heavily doped region and located in a deep N-well is found.

In303, a second P-type heavily doped region adjacent to the first N-type heavily doped region and located in the second N-well is found. The deep N-well is located in a first N-well, both the first N-well and the second N-well are located on the P-type substrate. An area that is formed by the first P-type heavily doped region, the first N-type heavily doped region, the second P-type heavily doped region, the second N-type heavily doped region, the deep N-well, the first N-well, the second N-well, and the P-type substrate is identified as the latch-up structure.

The method for identifying a latch-up structure provided in the embodiments of the present disclosure is further described in detail below with reference to specific embodiments.

FIG.3Bis a top view of a latch-up structure provided in an embodiment of the present disclosure.FIG.3Cis a sectional view of a latch-up structure provided in an embodiment of the present disclosure.

Before the operation in301is performed, the ground pad and power pad are found, the power pad includes pad such as VDD PAD, VDDQ PAD and the like.

Next, as illustrated inFIG.3C, the operation in301is performed. In the chip layout, a first P-type heavily doped region31connected to a ground pad and located in a P-type substrate35is found, and a first N-type heavily doped region32connected to a power pad and located in a second N-well38is found.

In one embodiment, the operation that the first P-type heavily doped region31connected to the ground pad and located in the P-type substrate35is found, includes the following operation. The first P-type heavily doped region31directly or indirectly connected to the ground pad and located in the P-type substrate35is found.

The operation that the first N-type heavily doped region32connected to the power pad and located in the second N-well38is found, includes the following operation. The first N-type heavily doped region32directly or indirectly connected to the power supply pad and located in the second N-well38is found.

Here, the operation that the first P-type heavily doped region31directly connected to the ground pad is found and the operation that the first N-type heavily doped region32directly connected to the power pad is found, mean that the ground pad is directly connected to the first P-type heavily doped region31and the power pad is directly connected to the first N-type heavily doped region32without other devices.

The operation that the first P-type heavily doped region31indirectly connected to the ground pad is found and the operation that the first N-type heavily doped region32indirectly connected to the power pad is found, mean that the ground pad may be connected to the first P-type heavily doped region31and the power pad may be connected to the first N-type heavily doped region32, respectively, by means of a high current conducting path. Specifically, for example, it may be connected by a resistor having low resistance, a switching device or a diode. More specifically, the ground pad may be connected to the first P-type heavily doped region31by means of a forward diode, and the power pad may be connected to the first N-type heavily doped region32by means of a backward diode.

Next, the operation in302is performed. A second N-type heavily doped region33adjacent to the first P-type heavily doped region31and located in the deep N-well36is found.

In this embodiment, the second N-type heavily doped region33is connected to the ground pad.

The second N-type heavily doped region33may be directly or indirectly connected to the ground pad. The indirect connection includes a connection by means of a high current conducting path. Specifically, for example, it may be connected by a resistor having low resistance, a switching device or a diode.

Next, the operation in303is performed. A second P-type heavily doped region34adjacent to the first N-type heavily doped region32and located in the second N-well38is found. The deep N-well36is located in the first N-well37, both the first N-well37and the second N-well38are located on the P-type substrate35, An area that is formed by the first P-type heavily doped region31, the first N-type heavily doped region32, the second P-type heavily doped region34, the second N-type heavily doped region33, the deep N-well36, the first N-well37, the second N-well38and the P-type substrate35is identified as the latch-up structure.

In this embodiment, the second P-type heavily doped region34is connected to the power pad.

The second P-type heavily doped region34may be directly or indirectly connected to the power pad. The indirect connection includes a connection by means of a high current conducting path. Specifically, for example, it may be connected by a resistor having low resistance, a switching device or a diode.

In one embodiment, the operation that the second N-type heavily doped region33adjacent to the first P-type heavily doped region31and located in the deep N-well36is found, includes that by taking the first P-type heavily doped region31as a center and taking a preset distance as a radius, the second N-type heavily doped region33is identified, a distance of which to the first P-type heavily doped region31is less than the preset distance; and/or, the operation that the second P-type heavily doped region34adjacent to the first N-type heavily doped region32and located in the second N-well38is found, includes that by taking the first N-type heavily doped region32as a center and taking a preset distance as a radius, the second P-type heavily doped region34is identified, a distance of which to the first N-type heavily doped region32is less than the preset distance.

In one embodiment, as illustrates inFIG.3B, there is a first distance L1between the first P-type heavily doped region31and the second N-type heavily doped region33, a second distance L2between the second N-type heavily doped region33and the second P-type heavily doped region34, and a third distance L3between the second P-type heavily doped region34and the first N-type heavily doped region32.

The operation that, by taking the first P-type heavily doped region31as a center and taking a preset distance as a radius, the second N-type heavily doped region33is identified, a distance of which to the first P-type heavily doped region31is less than the preset distance, specifically includes: the first distance is less than the preset distance.

The operation that, by taking the first N-type heavily doped region32as a center and taking a preset distance as a radius, the second P-type heavily doped region34is identified, a distance of which to the first N-type heavily doped region32is less than the preset distance, specifically includes: the third distance is less than the preset distance.

Furthermore, as illustrated inFIG.3C, the second N-well38, the P-type substrate35, and the deep N-well36constitute a first parasitic NPN transistor T1. The second P-type heavily doped region34, the second N-well38, and the P-type substrate35constitute a first parasitic PNP transistor T2.

The P-type substrate35has a first parasitic resistor RPW, a first end of which is connected to the first P-type heavily doped region31, and a second end of which is connected to an emitter of the first parasitic NPN transistor T1.

The second N-well38has a second parasitic resistor RNW, a first end of which is connected to the first N-type heavily doped region32, and a second end of which is connected to a base electrode of the first parasitic PNP transistor T2.

The following describes a principle of generating a latch-up effect in the latch-up structure. Specifically, T2is a vertical PNP transistor, the base electrode is an N-well, a gain from the base electrode to a collector electrode may reach tens of times, T1is a side NPN transistor, the base electrode is a P-type substrate, a gain from the base electrode to the collector electrode may reach tens of times, RNWis a parasitic resistor of the N-well, and Rpw is a parasitic resistor of the P-type substrate.

The above four elements T1, T2, RNWand RPWconstitute a silicon controlled circuit. When there is no external interference and no trigger is caused, the two transistors are in a turned-off state, a collector electrode current is formed by a reverse leakage current of C-B, and a current gain is extremely small, so the latch-up effect will not occur at this time. When a collector electrode current of one of the transistors suddenly increases to a certain value due to external interference, a feedback is sent to the other transistor, so that the two transistors are triggered to be turned on (generally, the PNP is easier to be triggered), and a low-impedance path is formed between the power pad VDD and the ground pad VSS. Then, even if the external interference disappears, because a positive feedback is formed between the two triodes, there will still be a leakage current between the power pad VDD and the ground pad VSS, that is, a locked state. This results in a latch-up effect.

FIG.4Ais a schematic flowchart of a method for identifying a latch-up structure provided in an embodiment of the present disclosure. As illustrated, the method includes the following operations.

In401, in a chip layout, a first P-type heavily doped region connected to a ground pad and located in a P-well is found, and a first N-type heavily doped region connected to a power pad and located in a deep N-well is found.

In402, a second N-type heavily doped region adjacent to the first P-type heavily doped region and located in the P-well is found.

In403, a second P-type heavily doped region adjacent to the first N-type heavily doped region and located in the deep N-well is found. The P-well is located in the deep N-well, the deep N-well is located in an N-well, and the N-well is located in a P-type substrate. An area that is formed by the first P-type heavily doped region, the first N-type heavily doped region, the second P-type heavily doped region, the second N-type heavily doped region, the P-well, the deep N-well, the N-well, and the P-type substrate is identified as the latch-up structure.

The method for identifying a latch-up structure provided in the embodiments of the present disclosure is further described in detail below with reference to specific embodiments.

FIG.4Bis a top view of a latch-up structure provided in an embodiment of the present disclosure.FIG.4Cis a sectional view of a latch-up structure provided in an embodiment of the present disclosure.

Before the operation in401is performed, the ground pad and power pad are found, the power pad includes pad such as VDD PAD, VDDQ PAD and the like.

Next, as illustrated inFIG.4C, the operation in401is performed. In the chip layout, a first P-type heavily doped region41connected to a ground pad and located in a P-well46is found, and a first N-type heavily doped region42connected to a power pad and located in a deep N-well47is found.

In one embodiment, the operation that the first P-type heavily doped region41connected to the ground pad and located in the P-well46is found, includes the following operation. The first P-type heavily doped region41directly or indirectly connected to the ground pad and located in the P-well46is found.

The operation that the first N-type heavily doped region42connected to the power pad and located in the deep N-well47is found, includes the following operation. The first N-type heavily doped region42directly or indirectly connected to the power supply pad and is located in the deep N-well47is found.

Here, the operation that the first P-type heavily doped region41directly connected to the ground pad is found and the operation that the first N-type heavily doped region42directly connected to the power pad is found, mean that the ground pad is directly connected to the first P-type heavily doped region41and the power pad is directly connected to the first N-type heavily doped region42without other devices.

The operation that the first P-type heavily doped region41indirectly connected to the ground pad is found and the operation that the first N-type heavily doped region42indirectly connected to the power pad is found, mean that the ground pad may be connected to the first P-type heavily doped region41and the power pad may be connected to the first N-type heavily doped region42, respectively, by means of a high current conducting path. Specifically, for example, it may be connected by a resistor having low resistance, a switching device or a diode. More specifically, the ground pad may be connected to the first P-type heavily doped region41by means of a forward diode, and the power pad may be connected to the first N-type heavily doped region42by means of a backward diode.

Next, the operation in402is performed. A second N-type heavily doped region43adjacent to the first P-type heavily doped region41and located in the P-well46is found.

In this embodiment, the second N-type heavily doped region43is connected to the ground pad.

The second N-type heavily doped region43may be directly or indirectly connected to the ground pad. The indirect connection includes a connection by means of a high current conducting path. Specifically, for example, it may be connected by a resistor having low resistance, a switching device or a diode.

Next, the operation in403is performed. A second P-type heavily doped region44adjacent to the first N-type heavily doped region42and located in the deep N-well47is found. the P-well46is located in the deep N-well47, the deep N-well47is located in an N-well48, and the N-well48is located in a P-type substrate45. An area that is formed by the first P-type heavily doped region41, the first N-type heavily doped region42, the second P-type heavily doped region44, the second N-type heavily doped region43, the P-well46, the deep N-well47, the N-well48and the P-type substrate45is identified as the latch-up structure.

In this embodiment, the second P-type heavily doped region44is connected to the power pad.

The second P-type heavily doped region44may be directly or indirectly connected to the power pad. The indirect connection includes a connection by means of a high current conducting path. Specifically, for example, it may be connected by a resistor having low resistance, a switching device or a diode.

In one embodiment, the operation that the second N-type heavily doped region43adjacent to the first P-type heavily doped region41and located in the P-well46is found, includes that by taking the first P-type heavily doped region31as a center and taking a preset distance as a radius, the second N-type heavily doped region43is identified, a distance of which to the first P-type heavily doped region41is less than the preset distance; and/or, the operation that the second P-type heavily doped region44adjacent to the first N-type heavily doped region42and located in the deep N-well47is found, includes that by taking the first N-type heavily doped region42as a center and taking a preset distance as a radius, the second P-type heavily doped region44is identified, a distance of which to the first N-type heavily doped region42is less than the preset distance.

In one embodiment, as illustrates inFIG.4B, there is a first distance L1between the first N-type heavily doped region42and the second P-type heavily doped region44, a second distance L2between the second P-type heavily doped region44and the second N-type heavily doped region43, and a third distance L3between the second N-type heavily doped region43and the first P-type heavily doped region41.

The operation that, by taking the first P-type heavily doped region41as a center and taking a preset distance as a radius, the second N-type heavily doped region43is identified, a distance of which to the first P-type heavily doped region41is less than the preset distance, specifically includes: the third distance is less than the preset distance.

The operation that, by taking the first P-type heavily doped region42as a center and taking a preset distance as a radius, the second P-type heavily doped region44is identified, a distance of which to the first N-type heavily doped region42is less than the preset distance, specifically includes: the first distance is less than the preset distance.

Furthermore, as illustrated inFIG.4C, a second P-type heavily doped region44, a deep N-well47and a first P-type heavily doped region41constitute a first parasitic PNP transistor T1. The second N-type heavily doped region43, the P-well46, and the deep N-well47constitute a first parasitic NPN transistor T2.

The deep N-well47has a first parasitic resistor RDNW, a first end of which is connected to the first N-type heavily doped region42, and a second end of which is connected to a base electrode of the first parasitic PNP transistor.

The P-well46has a second parasitic resistor RPW, a first end of which is connected to the first P-type heavily doped region41, and a second end of which is connected to a base electrode of the first parasitic NPN transistor T2and a collector electrode of the first parasitic PNP transistor T1.

The following describes a principle of generating a latch-up effect. Specifically, T1is a vertical PNP transistor, the base electrode is an N-well, a gain from the base electrode to the collector electrode may reach hundreds of times, T2is a side NPN transistor, the base electrode is a P-type substrate, the gain from the base electrode to the collector electrode may reach tens of times, RDNWis the parasitic resistor of the deep N-well, and RPWis the parasitic resistor of the P-well.

The above four elements T1, T2, RDNWand RPWconstitute a silicon controlled circuit. When there is no external interference and no trigger is caused, the two transistors are in a turned-off state, a collector electrode current is formed by a reverse leakage current of C-B, and a current gain is extremely small, so a latch-up effect will not occur at this time. When a collector electrode current of one of the transistors suddenly increases to a certain value due to external interference, a feedback is sent to the other transistor, so that the two transistors are triggered to be turned on (generally, the PNP is easier to be triggered), and a low-impedance path is formed between the power pad VDD and the ground pad VSS. Then, even if the external interference disappears, because a positive feedback is formed between the two triodes, there will still be a leakage current between the power pad VDD and the ground pad VSS, that is, a locked state. This results in a latch-up effect.

FIG.5Ais a schematic flowchart of a method for identifying a latch-up structure provided in an embodiment of the present disclosure. As illustrated, the method includes the following operations.

In501, in a chip layout, a first P-type heavily doped region connected to a ground pad and located in a P-type substrate is found, and a first N-type heavily doped region connected to a power pad and located in an N-well is found.

In502, a second N-type heavily doped region adjacent to the first P-type heavily doped region and located in the P-type substrate is found.

In503, a second P-type heavily doped region adjacent to the first N-type heavily doped region and located in a P-well is found. The P-well is located in the deep N-well, the deep N-well is located an N-well, the N-well is located in a P-type substrate. An area that is formed by the first P-type heavily doped region, the first N-type heavily doped region, the second P-type heavily doped region, the second N-type heavily doped region, the P-well, the deep N-well, the N-well, and the P-type substrate is identified as the latch-up structure.

The method for identifying a latch-up structure provided in the embodiments of the present disclosure is further described in detail below with reference to specific embodiments.

FIG.5Bis a top view of a latch-up structure provided in an embodiment of the present disclosure.FIG.5Cis a sectional view of a latch-up structure provided in an embodiment of the present disclosure.

Before the operation in501is performed, the ground pad and power pad are found, the power pad includes pad such as VDD PAD, VDDQ PAD and the like.

Next, as illustrated inFIG.5C, the operation in501is performed. In a chip layout, a first P-type heavily doped region51connected to a ground pad and located in a P-type substrate55is found, and a first N-type heavily doped region52connected to a power pad and located in an N-well58is found.

In one embodiment, the operation that the first P-type heavily doped region51connected to the ground pad and located in the P-type substrate55is found, includes the following operation. The first P-type heavily doped region51directly or indirectly connected to the ground pad and located in the P-type substrate55is found.

The operation that the first N-type heavily doped region52connected to the power pad and located in the N-well58includes the following operation. The first N-type heavily doped region52directly or indirectly connected to the power supply pad and located in the N-well58is found.

Here, the operation that the first P-type heavily doped region51directly connected to the ground pad is found, and the operation that the first N-type heavily doped region52directly connected to the power pad, mean that the ground pad is directly connected to the first P-type heavily doped region51and the power pad is directly connected to the first N-type heavily doped region52without other devices.

The operation that the first P-type heavily doped region51indirectly connected to the ground pad is found and the operation that the first N-type heavily doped region52indirectly connected to the power pad is found, mean that the ground pad may be connected to the first P-type heavily doped region51and the power pad may be connected to the first N-type heavily doped region52, respectively, by means of a high current conducting path. Specifically, for example, it may be connected by a resistor having low resistance, a switching device or a diode. More specifically, the ground pad may be connected to the first P-type heavily doped region51by means of a forward diode, and the power pad may be connected to the first N-type heavily doped region52by means of a backward diode.

Next, the operation in502is performed. A second N-type heavily doped region53adjacent to the first P-type heavily doped region51and located in the P-type substrate55is found.

In this embodiment, the second N-type heavily doped region53is connected to the ground pad.

The second N-type heavily doped region53may be directly or indirectly connected to the ground pad. The indirect connection includes a connection by means of a high current conducting path. Specifically, for example, it may be connected by a resistor having low resistance, a switching device or a diode.

Next, the operation in503is performed. A second P-type heavily doped region54adjacent to the first N-type heavily doped region52and located in a P-well56is found. The P-well56is located in the deep N-well57, the deep N-well57is located in the N-well58, and the N-well58is located on a P-type substrate55. An area that is formed by the first P-type heavily doped region51, the first N-type heavily doped region52, the second P-type heavily doped region54, the second N-type heavily doped region53, the P-well56, the deep N-well57, the N-well58and the P-type substrate55is identified as the latch-up structure.

In this embodiment, the second P-type heavily doped region54is connected to the power pad.

The second P-type heavily doped region54may be directly or indirectly connected to the power pad. The indirect connection includes a connection by means of a high current conducting path. Specifically, for example, it may be connected by a resistor having low resistance, a switching device or a diode.

In one embodiment, the operation that the second N-type heavily doped region53adjacent to the first P-type heavily doped region51and located in the P-type substrate55includes that by taking the first P-type heavily doped region51as a center and taking a preset distance as a radius, the second N-type heavily doped region53is identified, a distance of which to the first P-type heavily doped region51is less than the preset distance, and/or, the operation that the second P-type heavily doped region54adjacent to the first N-type heavily doped region52and located in a P-well56is found, includes that by taking the first N-type heavily doped region52as a center and taking a preset distance as a radius, the second P-type heavily doped region54is identified, a distance of which to the first N-type heavily doped region52is less than the preset distance.

In one embodiment, as illustrates inFIG.5B, there is a first distance L1between the first N-type heavily doped region52and the second P-type heavily doped region54, a second distance L2between the second P-type heavily doped region54and the second N-type heavily doped region53, and a third distance L3between the second N-type heavily doped region53and the first P-type heavily doped region51.

The operation that, by taking the first P-type heavily doped region51as a center and taking a preset distance as a radius, the second N-type heavily doped region53is identified, a distance of which to the first P-type heavily doped region51is less than the preset distance, specifically includes: the third distance is less than the preset distance.

The operation that, by taking the first N-type heavily doped region52as a center and taking a preset distance as a radius, the second P-type heavily doped region54with a distance to the first N-type heavily doped region52less than the preset distance is identified, specifically includes: the first distance is less than the preset distance.

Furthermore, as illustrated inFIG.5C, the P-well56, the deep N-well57and the P-type substrate55constitute a first parasitic PNP transistor T1. The deep N-well57, the P-type substrate55and the second N-type heavily doped region53constitute a first parasitic NPN transistor T2.

The deep N-well57has a first parasitic resistor RDNW, a first end of which is connected to the first N-type heavily doped region52, and a second end of which is connected to a base electrode of the first parasitic PNP transistor T1.

The P-type substrate55has a second parasitic resistor RPW, a first end of which is connected to the first P-type heavily doped region51, and a second end of which is connected to the base electrode of the first parasitic NPN transistor T2and a collector electrode of the first parasitic PNP transistor T1.

The following describes a principle of generating a latch-up effect. Specifically, T1is a vertical PNP transistor, the base electrode is an N-well, a gain from the base electrode to the collector electrode may reach hundreds of times, T2is a side NPN transistor, the base electrode is a P-type substrate, a gain from the base electrode to the collector electrode may reach tens of times, RDNWis the parasitic resistor of the deep N-well, and RPWis the parasitic resistor of the P-type substrate.

The above four elements T1, T2, RDNWand RPWconstitute a silicon controlled circuit. When there is no external interference and no trigger is caused, the two transistors are in a turned-off state, a collector electrode current is formed by a reverse leakage current of C-B, and a current gain is extremely small, so the latch-up effect will not occur at this time. When a collector electrode current of one of the transistors suddenly increases to a certain value due to external interference, a feedback is sent to the other transistor, so that the two transistors are triggered to be turned on (generally, the PNP is easier to be triggered), and a low-impedance path is formed between the power pad VDD and the ground pad VSS. Then, even if the external interference disappears, because a positive feedback is formed between the two triodes, there will still be a leakage current between the power pad VDD and the ground pad VSS, that is, a locked state. This results in a latch-up effect.

FIG.6Ais a schematic flowchart of a method for identifying a latch-up structure provided in an embodiment of the present disclosure. As illustrated, the method includes the following operations.

In601, in a chip layout, a first P-type heavily doped region connected to a ground pad and located in a P-type substrate is found, and a first N-type heavily doped region connected to a power pad and located in a first N-well is found.

In602, a second N-type heavily doped region adjacent to the first P-type heavily doped region and located in a second N-well is found.

In603, a second P-type heavily doped region adjacent to the first N-type heavily doped region and located in a P-well is found. The P-well is located in a deep N-well, the deep N-well is located in the first N-well, and both the first N-well and the second N-well are located in the P-type substrate. An area that is formed by the first P-type heavily doped region, the first N-type heavily doped region, the second P-type heavily doped region, the second N-type heavily doped region, the P-well, the deep N-well, the first N-well, the second N-well and the P-type substrate is identified as the latch-up structure.

The method for identifying a latch-up structure according to the embodiments of the present disclosure is further described in detail below with reference to specific embodiments.

FIG.6Bis a top view of a latch-up structure provided in an embodiment of the present disclosure.FIG.6Cis a sectional view of a latch-up structure provided in an embodiment of the present disclosure.

Before the operation in601is performed, a ground pad and a power pad are found, the power pad includes pad such as VDD PAD, VDDQ PAD and the like.

Next, as illustrated inFIG.6C, the operation in601is performed. In the chip layout, a first P-type heavily doped region61connected to a ground pad and located in a P-type substrate65is found, and a first N-type heavily doped region62connected to the power pad and located in a first N-well68is found.

In one embodiment, the operation that the first P-type heavily doped region61connected to the ground pad and located in the P-type substrate65is found, includes the following operation. The first P-type heavily doped region61directly or indirectly connected to the ground pad and located in the P-type substrate65is found.

The operation that the first N-type heavily doped region62connected to the power pad and located in a first N-well68is found, includes the following operation. The first N-type heavily doped region62directly or indirectly connected to the power supply pad and located in the first N-well68is found.

Here, the operation that the first P-type heavily doped region61directly connected to the ground pad is found and the operation that the first N-type heavily doped region62directly connected to the power pad is found, mean that the ground pad is directly connected to the first P-type heavily doped region61and the power pad is directly connected to the first N-type heavily doped region62without other devices.

The operation that the first P-type heavily doped region61indirectly connected to the ground pad is found and the operation that the first N-type heavily doped region62indirectly connected to the power pad is found, mean that the ground pad may be connected to the first P-type heavily doped region61and the power pad may be connected to the first N-type heavily doped region62, respectively, by means of a high current conducting path. Specifically, for example, it may be connected by a resistor having low resistance, a switching device or a diode. More specifically, the ground pad may be connected to the first P-type heavily doped region61by means of a forward diode, and the power pad may be connected to the first N-type heavily doped region62by means of a backward diode.

Next, the operation in602is performed. A second N-type heavily doped region63adjacent to the first P-type heavily doped region61and located in the second N-well69is found.

In this embodiment, the second N-type heavily doped region63is connected to the ground pad.

The second N-type heavily doped region63may be directly or indirectly connected to the ground pad. The indirect connection includes a connection by means of a high current conducting path. Specifically, for example, it may be connected by a resistor having low resistance, a switching device or a diode.

Next, the operation in603is performed. A second P-type heavily doped region64adjacent to the first N-type heavily doped region62and located in a P-well66is found. The P-well66is located in the deep N-well67, the deep N-well67is located in the first N-well68, and both the first N-well68and the second N-well69are located in the P-type substrate65. An area that is formed by the first P-type heavily doped region61, the first N-type heavily doped region62, the second P-type heavily doped region64, the second N-type heavily doped region63, the P-well66, the deep N-well67, the first N-well68, the second N-well69and the P-type substrate65is identified as the latch-up structure.

In this embodiment, the second P-type heavily doped region64is connected to the power pad.

The second P-type heavily doped region64may be directly or indirectly connected to the power pad. The indirect connection includes a connection by means of a high current conducting path. Specifically, for example, it may be connected by a resistor having low resistance, a switching device or a diode.

In one embodiment, the operation that the second N-type heavily doped region63adjacent to the first P-type heavily doped region61and located in a second N-well69is found, includes that by taking the first P-type heavily doped region61as a center and taking a preset distance as a radius, the second N-type heavily doped region63is identified, a distance of which to the first P-type heavily doped region61is less than the preset distance; and/or, the operation that the second P-type heavily doped region64adjacent to the first N-type heavily doped region62and located in the P-well66is found, includes that by taking the first N-type heavily doped region22as a center and taking a preset distance as a radius, the second P-type heavily doped region64is identified, a distance of which to the first N-type heavily doped region62is less than the preset distance.

In one embodiment, as illustrates inFIG.6B, there is a first distance L1between the first N-type heavily doped region62and the second P-type heavily doped region64, a second distance L2between the second P-type heavily doped region64and the second N-type heavily doped region63, and a third distance L3between the second N-type heavily doped region63and the first P-type heavily doped region61.

The operation that, by taking the first P-type heavily doped region61as a center and taking a preset distance as a radius, the second N-type heavily doped region63is identified, a distance of which to the first P-type heavily doped region61is less than the preset distance, specifically includes: the first distance is less than the preset distance.

The operation that, by taking the first N-type heavily doped region62as a center and taking a preset distance as a radius, the second P-type heavily doped region64is identified, a distance of which to the first N-type heavily doped region62is less than the preset distance, specifically includes: the first distance is less than the preset distance.

Furthermore, as illustrated inFIG.6C, the P-well66, the deep N-well67and the P-type substrate65constitute a first parasitic PNP transistor T1. The deep N-well67, the P-type substrate65and the second N-well69constitute a first parasitic NPN transistor T2.

The deep N-well67has a first parasitic resistor RDNW, a first end of which is connected to the first N-type heavily doped region62, and a second end of which is connected to a base electrode of the first parasitic PNP transistor.

The P-type substrate65has a second parasitic resistor RPW, a first end of which is connected to the first P-type heavily doped region61, and a second end of which is connected to a base electrode of the first parasitic NPN transistor T2and the collector electrode of the first parasitic PNP transistor T1.

The following describes a principle of generating a latch-up effect.

Specifically, T1is a vertical PNP transistor, the base electrode is an N-well, a gain from the base electrode to the collector electrode may reach hundreds times, T2is a side NPN transistor, the base electrode is a P-type substrate, a gain from the base electrode to the collector electrode may reach tens of times, RDNWis a parasitic resistor of the deep N-well, and RPWis a parasitic resistor of the P-type substrate.

The above four elements T1, T2, RDNWand RPWconstitute a silicon controlled circuit. When there is no external interference and no trigger is caused, the two transistors are in a turned-off state, a collector electrode current is formed by a reverse leakage current of C-B, and a current gain is extremely small, so the latch-up effect will not occur at this time. When a collector electrode current of one of the transistors suddenly increases to a certain value due to external interference, a feedback is sent to the other transistor, so that the two transistors are turned on due to triggering (generally, the PNP is easier to be triggered), and a low-impedance path is formed between the power pad VDD and the ground pad VSS. Then, even if the external interference disappears, because a positive feedback is formed between the two triodes, there will still be a leakage current between the power pad VDD and the ground pad VSS, that is, a locked state. This results in a latch-up effect.

FIG.7Ais a schematic flowchart of a method for identifying a latch-up structure provided in an embodiment of the present disclosure. As illustrated, the method includes the following operations.

In701, in a chip layout, a first P-type heavily doped region connected to a ground pad and located in a P-type substrate is found, and a first N-type heavily doped region connected to a power pad and located in a first N-well is found.

In702, a second N-type heavily doped region adjacent to the first P-type heavily doped region and located in a second deep N-well is found.

In703, a second P-type heavily doped region adjacent to the first N-type heavily doped region and located in a P-well is found. The P-well is located in a first deep N-well, the first deep N-well is located the first N-well, the second deep N-well is located in a second N-well, and both the first N-well and the second N-well are located in a P-type substrate. An area that is formed by the first P-type heavily doped region, the first N-type heavily doped region, the second P-type heavily doped region, the second N-type heavily doped region, the P-well, the first deep N-well, the second deep N-well, the first N-well, the second N-well and the P-type substrate is identified as the latch-up structure.

The method for identifying a latch-up structure provided in the embodiments of the present disclosure is further described in detail below with reference to specific embodiments.

FIG.7Bis a top view of a latch-up structure provided in an embodiment of the present disclosure.FIG.7Cis a sectional view of a latch-up structure provided in an embodiment of the present disclosure.

Before the operation in701is performed, the ground pad and power pad are found, the power pad includes pad such as VDD PAD, VDDQ PAD and the like.

Next, as illustrated inFIG.7C, the operation in701is performed. In the chip layout, a first P-type heavily doped region71connected to a ground pad and located in a P-type substrate75is found, and the first N-type heavily doped region72connected to the power pad and located in a first N-well79is found.

In one embodiment, the operation that the first P-type heavily doped region71connected to the ground pad and located in the P-type substrate75is found, includes the following operation. The first P-type heavily doped region71directly or indirectly connected to the ground pad and located in the P-type substrate75is found.

The operation that the first N-type heavily doped region72connected to the power pad and located in a first N-well79is found, includes the following operation. The first N-type heavily doped region72directly or indirectly connected to the power supply pad and located in the first N-well79is found.

Here, the operation that the first P-type heavily doped region71directly connected to the ground pad is found and the operation that the first N-type heavily doped region72directly connected to the power pad is found, mean that the ground pad is directly connected to the first P-type heavily doped region71and the power pad is directly connected to the first N-type heavily doped region72without other devices.

The operation that the first P-type heavily doped region71indirectly connected to the ground pad is found and the operation that the first N-type heavily doped region72indirectly connected to the power pad, mean that the ground pad may be connected to the first P-type heavily doped region71and the power pad may be connected to the first N-type heavily doped region72, respectively, by means of a high current conducting path. Specifically, for example, it may be connected by a resistor having low resistance, a switching device or a diode. More specifically, the ground pad may be connected to the first P-type heavily doped region71by means of a forward diode, and the power pad may be connected to the first N-type heavily doped region72by means of a backward diode.

Next, the operation in702is performed. A second N-type heavily doped region73adjacent to the first P-type heavily doped region71and located in the second deep N-well78is found.

In this embodiment, the second N-type heavily doped region73is connected to the ground pad.

The second N-type heavily doped region73may be directly or indirectly connected to the ground pad. The indirect connection includes a connection by means of a high current conducting path. Specifically, for example, it may be connected by a resistor having low resistance, a switching device or a diode.

Next, the operation in703is performed. A second P-type heavily doped region74adjacent to the first N-type heavily doped region72and located in a P-well76, the P-well76is located in a first deep N-well77, the first deep N-well77is located in the first N-well79, the second deep N-well78is located in the second N-well80, both the first N-well79and the second N-well80are located in the P-type substrate75, An area that is formed by the first P-type heavily doped region71, the first N-type heavily doped region72, the second P-type heavily doped region74, the second N-type heavily doped region73, the P-well76, the first deep N-well77, the second deep N-well78, the first N-well79, the second N-well80and the P-type substrate75is identified as the latch-up structure.

In this embodiment, the second P-type heavily doped region74is connected to the power pad.

The second P-type heavily doped region74may be directly or indirectly connected to the power pad. The indirect connection includes a connection by means of a high current conducting path. Specifically, for example, it may be connected by a resistor having low resistance, a switching device or a diode.

In one embodiment, the operation that the second N-type heavily doped region73adjacent to the first P-type heavily doped region71and located in a second deep N-well78is found, includes that by taking the first P-type heavily doped region71as a center and taking a preset distance as a radius, the second N-type heavily doped region73is identified, a distance of which to the first P-type heavily doped region71is less than the preset distance; and/or, the operation that the second P-type heavily doped region74adjacent to the first N-type heavily doped region72and located in a P-well76is found, includes that by taking the first N-type heavily doped region72as a center and taking a preset distance as a radius, the second P-type heavily doped region74is identified, a distance of which to the first N-type heavily doped region72is less than the preset distance.

In one embodiment, as illustrates inFIG.7B, there is a first distance L1between the first N-type heavily doped region72and the second P-type heavily doped region74, a second distance L2between the second P-type heavily doped region74and the second N-type heavily doped region73, and a third distance L3between the second N-type heavily doped region73and the first P-type heavily doped region71.

The operation that, by taking the first P-type heavily doped region71as a center and taking a preset distance as a radius, the second N-type heavily doped region73is identified, a distance of which to the first P-type heavily doped region71is less than the preset distance, specifically includes: the first distance is less than the preset distance.

The operation that, by taking the first N-type heavily doped region72as a center and taking a preset distance as a radius, the second P-type heavily doped region74is identified, a distance of which to the first N-type heavily doped region72is less than the preset distance, specifically includes: the first distance is less than the preset distance.

Furthermore, as illustrated inFIG.7C, the P-well76, the first deep N-well77and the P-type substrate75constitute a first parasitic PNP transistor T1. The first deep N-well77, the P-type substrate75and the second deep N-well78constitute a first parasitic NPN transistor T2.

The first deep N-well77has a first parasitic resistor RDNW, a first end of which is connected to the first N-type heavily doped region72, and a second end of which is connected to a base electrode of the first parasitic PNP transistor T1.

The P-type substrate75has a second parasitic resistor RPW, a first end of which is connected to the first P-type heavily doped region71, and a second end of which is connected to the base electrode of the first parasitic NPN transistor T2and a collector electrode of the first parasitic PNP transistor T1.

The following describes a principle of generating a latch-up effect. Specifically, T1is a vertical PNP transistor, the base electrode is an N-well, a gain from the base electrode to a collector electrode may reach hundreds of times, T2is a side NPN transistor, the base electrode is a P-type substrate, a gain from the base electrode to the collector electrode may reach tens of times, RDNWis a parasitic resistor of the first deep N-well, and RPWis a parasitic resistor of the P-type substrate.

The above four elements T1, T2, RDNWand RPWconstitute a silicon controlled circuit. When there is no external interference and no triggering, the two transistors are in a turned-off state, a collector electrode current is formed by a reverse leakage current of C-B, and a current gain is extremely small, so the latch-up effect will not occur at this time. When a collector electrode current of one of the transistors suddenly increases to a certain value due to external interference, a feedback is sent to the other transistor, so that the two transistors are triggered to be turned on (generally, the PNP is easier to be triggered), and a low-impedance path is formed between the power pad VDD and the ground pad VSS. Then, even if the external interference disappears, because a positive feedback is formed between the two triodes, there will still be a leakage current between the power pad VDD and the ground pad VSS, that is, the locked state. This results in a latch-up effect.

The foregoing descriptions are merely preferred embodiments of the present disclosure, and are not intended to limit the scope of protection of the present disclosure. Any modification, equivalent replacement, improvement and the like made within the spirit and principles of the present disclosure shall be included within the scope of protection of the present disclosure.

INDUSTRIAL APPLICABILITY

In the embodiments of the present disclosure, by finding the first P-type heavily doped region connected to the ground pad, the first N-type heavily doped region connected to the power pad, and finding the second N-type heavily doped region and the second P-type heavily doped region respectively by means of the first P-type heavily doped region and the first N-type heavily doped region, the latch-up structure connected to the ground pad and the power pad is identified, thereby corresponding design rules may be used to inspect whether it is safe to ensure the reliability of the device.