Circuit of measuring leakage current in a semiconductor integrated circuit

An integrated circuit includes an operational circuit and a test circuit for measuring a leakage current associated with all or part of the operational circuit. The leakage current measurement circuit may include a mirror circuit configured to mirror leakage current to a current-to-voltage converter and an analog-to-digital converter configured to convert the analog voltage representative of the leakage current developed by the current-to-voltage converter to a digital value.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2014-0017351 filed on Feb. 14, 2014, the disclosure of which is hereby incorporated by reference in its entirety.

BACKGROUND

Field

Embodiments of the inventive concept relate to a semiconductor integrated circuit, and, particularly, to a circuit of measuring a leakage current flowing through transistors or functional blocks included in the semiconductor integrated circuit.

Description of Related Art

Leakage current of a transistor maybe measured in order to ensure proper performance of a semiconductor integrated circuit. In a system-on-chip (SoC) integrated circuit, leakage current flowing through a transistor in a specific location in the SoC may be measured to ensure that the SoC will operate with sufficient speed without consuming excessive power.

Conventionally, leakage current flowing through transistors in a test chip, rather than that flowing through a real product (that is, an operational chip), has been measured. As a result, conventional measurements of leakage current flowing through transistors or functional blocks may not accurately reflect the leakage current flowing through operational chips (operational, that is, in opposition to test chips).

SUMMARY

In various embodiments of inventive concepts a circuit for measuring a leakage current in a semiconductor integrated circuit includes an operational amplifier configured to receive a reference voltage at a non-inverted input terminal and a feedback voltage at an inverted input terminal connected to a feedback node, and to amplify a difference between the reference voltage and the feedback voltage, a first PMOS transistor having a gate to which an output voltage of the operational amplifier is applied, a source connected to a first supply voltage, and a drain connected to the feedback node, a first switch connected between the feedback node and a circuit block to be tested, a second PMOS transistor having a gate connected to the gate of the first PMOS transistor, and a source connected to the first supply voltage, a resistor connected between a drain of the second PMOS transistor and a ground voltage and an analog-to-digital (A/D) converter configured to perform an A/D conversion on a first voltage signal measured from the resistor to generate output data.

In various embodiments of inventive concepts a circuit for measuring a leakage current includes a reference voltage configured to have a voltage level lower than the first supply voltage.

In various embodiments of inventive concepts a circuit for measuring a leakage current includes a second switch connected between the circuit block to be tested and the ground voltage.

In various embodiments of inventive concepts a circuit for measuring a leakage current includes a circuit block to be tested that includes a first NMOS transistor.

In various embodiments of inventive concepts a circuit for measuring a leakage current includes a second switch connected between the source of the first NMOS transistor and the ground voltage, a third switch having a first terminal connected to a first terminal of the first switch, a second terminal connected to the ground voltage, and a third terminal connected to a gate of the first NMOS transistor, and a fourth switch having a first terminal connected to a first terminal of the first switch, a second terminal connected to the ground voltage, and a third terminal connected to a drain of the first NMOS transistor.

In various embodiments of inventive concepts a circuit for measuring a leakage current a circuit block to be tested includes a third PMOS transistor.

In various embodiments of inventive concepts a circuit for measuring a leakage current includes a second switch connected between the drain of the third PMOS transistor and the ground voltage, a third switch having a first terminal connected to a first terminal of the first switch, a second terminal connected to a second supply voltage, and a third terminal connected to a gate of the third PMOS transistor, a fourth switch having a first terminal connected to the first terminal of the first switch, a second terminal connected to the second supply voltage, and a third terminal connected to a source of the third PMOS transistor, and a fifth switch having a first terminal connected to the first terminal of the first switch, a second terminal connected to the second supply voltage, and a third terminal connected to the bulk of the third PMOS transistor.

In various embodiments of inventive concepts a circuit for measuring a leakage current the circuit block to be tested includes a first NMOS transistor and a third PMOS transistor.

In various embodiments of inventive concepts a circuit for measuring a leakage current includes a second switch connected between a source of the first NMOS transistor and the ground voltage, a third switch having a first terminal connected to a first terminal of the first switch, a second terminal connected to the ground voltage, and a third terminal connected to the gate of the first NMOS transistor, a fourth switch having a first terminal connected to the first terminal of the first switch, a second terminal connected to the ground voltage, and a third terminal connected to the drain of the first NMOS transistor, a fifth switch connected between a drain of the third PMOS transistor and the ground voltage, a sixth switch having a first terminal connected to the first terminal of the first switch, a second terminal connected to a second supply voltage, and a third terminal connected to the gate of the third PMOS transistor, a seventh switch having the first terminal connected to the first terminal of the first switch, a second terminal connected to the second supply voltage, and a third terminal connected to the source of the third PMOS transistor and an eighth switch having a first terminal connected to the first terminal of the first switch, a second terminal connected to the second supply voltage, and a third terminal connected to the bulk of the third PMOS transistor.

In various embodiments of inventive concepts a circuit for measuring a leakage current a gate-on current (Ig_on) of an NMOS transistor is measured with the gate of the first NMOS transistor electrically connected to the feedback node, and the source and drain of the first NMOS transistor electrically connected to the ground voltage.

In various embodiments of inventive concepts a circuit for measuring a leakage current a drain-off current (Id_off) of an NMOS transistor is measured with the gate and source of the first NMOS transistor electrically connected to the ground voltage, and the drain of the first NMOS transistor electrically connected to the feedback node.

In various embodiments of inventive concepts a circuit for measuring a leakage current a gate-off current (Ig_off) of a PMOS transistor is measured with the gate of the third PMOS transistor electrically connected to the feedback node, the source and bulk of the third PMOS transistor electrically connected to the second supply voltage, and the drain of the third PMOS transistor electrically connected to the ground voltage.

In various embodiments of inventive concepts a circuit for measuring a leakage current a source-off current (Is_off) of a PMOS transistor is measured with the gate and bulk of the third PMOS transistor electrically connected to the second supply voltage, the source of the third PMOS transistor electrically connected to the feedback node, and the drain of the third PMOS transistor electrically connected to the ground voltage.

In various embodiments of inventive concepts a circuit for measuring a leakage current a bulk-off current (Ib_off) of a PMOS transistor is measured with the gate and source of the third PMOS transistor electrically connected to the second supply voltage, the bulk of the third PMOS transistor electrically connected to the feedback node, and the drain of the third PMOS transistor electrically connected to the ground voltage.

In various embodiments of inventive concepts a semiconductor integrated circuit includes a circuit block to be tested and a circuit for measuring leakage current from the test block, wherein the circuit for measuring includes an operational amplifier configured to receive a reference voltage at a non-inverted input terminal and a feedback voltage at an inverted input terminal connected to a feedback node, and amplify a difference between the reference voltage and the feedback voltage, a first PMOS transistor having a gate to which an output voltage of the operational amplifier is applied, a source connected to a first supply voltage, and a drain connected to the feedback node, a first switch connected between the feedback node and the circuit block to be tested, a second PMOS transistor having a gate connected to the gate of the first PMOS transistor, and a source connected to the first supply voltage, a resistor connected between a drain of the second PMOS transistor and a ground voltage, and an A/D converter configured to perform an A/D conversion on a first voltage signal measured from the resistor to generate output data.

In various embodiments of inventive concepts a semiconductor integrated circuit includes an operational circuit for which leakage current is to be tested and a leakage current measurement circuit configured to test leakage current of the operational circuit, including a mirror circuit to mirror leakage current to a current-to-voltage converter and an analog-to-digital converter configured to convert the analog voltage representative of the leakage current developed by the current-to-voltage converter to a digital value.

In various embodiments of inventive concepts a semiconductor integrated circuit includes a mirror circuit that includes transistors of different sizes to yield an output current that is a multiple of the leakage current, the multiplying factor being the ratio of sizes of mirror circuit transistors.

In various embodiments of inventive concepts a semiconductor integrated circuit includes a current-to-voltage converter that is a resistor.

In various embodiments of inventive concepts a semiconductor integrated circuit leakage current measurement circuit is switchably connected to the operational circuit for which leakage current is to be tested.

In various embodiments of inventive concepts a semiconductor integrated circuit the multiple of a current mirror is chosen to correlate the input range of the analog-to-digital-converter to the output of the current to voltage converter.

DESCRIPTION

Various exemplary embodiments will be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments are shown. Exemplary embodiments may, however, be embodied in many different forms and should not be construed as limited to exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough, and will convey the scope of exemplary embodiments to those skilled in the art. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which exemplary embodiments belong. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. When it is possible to implement any embodiment in any other way, a function or an operation specified in a specific block may be performed differently from a flow specified in a flowchart. For example, two consecutive blocks may actually perform the function or the operation simultaneously, and the two blocks may perform the function or the operation conversely according to a related operation or function.

Inventive concepts will now be described more fully with reference to the accompanying drawings, in which embodiments of inventive concepts are shown.

In exemplary embodiments in accordance with principles of inventive concepts, a semiconductor device may incorporate one or more leakage testing circuits to measure the leakage current of devices, circuits, or functional blocks that are a part of the same device that the testing circuit is a part of. By employing “on-board” leakage current test circuits (that is, leakage current test circuits that are a part of the operational device, rather than a separate device devoted to testing) a system and method in accordance with principles of inventive concepts may improve testing results and reduce requirements for output pads, for example. In exemplary embodiments a leakage current testing circuit may include an amplifier that may be connected through switches to a circuit to be tested and an analog-to-digital converter, configured to measure the circuit's leakage current. Switches may be operated by a self-test circuit or by processor integral to the integrated circuit, for example, to measure various currents. A plurality of such leakage current test circuits may be incorporated in a semiconductor device in accordance with principles of inventive concepts, each dedicated to one or more circuits to be tested. In various configurations test circuits may be configured to test NAND, NOR, or INVERTER circuits, for example. Semiconductor devices in accordance with principles of inventive concepts may be implemented in system-on-chip (SoC) circuits, for example. A leakage current measurement circuit in accordance with principles of inventive concepts may include a mirror circuit configured to mirror leakage current to a current-to-voltage converter (which may be a resistor), and an analog-to-digital converter configured to convert the analog voltage representative of the leakage current developed by the current-to-voltage converter to a digital value. A leakage current measurement circuit in accordance with principles of inventive concepts may be switchably configured to test leakage current during a test mode or to be disconnected from the circuit during an operational mode. The mode in which the leakage current measurement test circuit operates may be controlled by a self-test circuit or processor, for example, that also resides in the operational integrated circuit.

FIG. 1is a circuit diagram illustrating a semiconductor integrated circuit100that includes an exemplary embodiment of a circuit for measuring leakage current in accordance with principles of inventive concepts. Semiconductor integrated circuit100may include a block to be tested150and a circuit110for measuring the leakage current of the block to be tested150.

The circuit110for measuring a leakage current may include an operational amplifier OP1, a first PMOS transistor MP1, a first switch113, a second PMOS transistor MP2, a resistor R1and an analog-to-digital (A/D) converter111.

In exemplary embodiments operational amplifier OP1receives a reference voltage VREF1at a non-inverted input terminal and a feedback voltage VFB at an inverted input terminal connected to a feedback node NFB, and amplifies a difference between the reference voltage VREF1and the feedback voltage VFB. The first PMOS transistor MP1has a gate to which an output voltage of the operational amplifier OP1is applied, a source connected to a first supply voltage VDDH, and a drain connected to the feedback node NFB. The first switch113is connected between the feedback node NFB and the block to be tested150. The second PMOS transistor MP2has a gate connected to the gate of the first PMOS transistor MP1, and a source connected to the first supply voltage VDDH. The resistor R1is connected between a drain of the second PMOS transistor MP2and a ground voltage GND. The A/D converter111performs an A/D conversion on a first voltage signal measured from the resistor R1to generate output data DOUT. This digital representation of the measured leakage current may be employed by a semiconductor chip in accordance with principles of inventive concepts as a measure of the chip's, or segment of the chip's, operational efficiency, for example.

In exemplary embodiments circuit110for measuring leakage current includes a second switch112connected between the block to be tested150and the ground voltage GND.

The reference voltage VREF1may have a voltage level lower than the first supply voltage VDDH. The first supply voltage VDDH may have a voltage level higher than a second supply voltage VDD supplied to the block to be tested150. In exemplary embodiments, the reference voltage VREF1may have a voltage level of the second supply voltage VDD. Additionally, the voltage of the feedback node NFB, that is a feedback voltage VFB, may have nearly the same voltage level of the reference voltage VREF1.

The leakage current ILK flowing through the block to be tested150flows through the first PMOS transistor MP1, and then flows through the second PMOS transistor MP2connected to the first PMOS transistor MP1in a current-mirror form and the resistor R1. That is, because transistors MP1and MP2are arranged as a current mirror, the leakage current ILK flowing through transistor MP1is reflected in transistor MP2. When the size (W/L) of the second PMOS transistor MP2is A times larger than the first PMOS transistor MP1, a current corresponding to A times of ILK may flow through the second PMOS transistor MP2. That is, leakage current ILK may be multiplied by the size ratio of the first transistor to the second transistor. The A/D converter111performs an A/D conversion on the first voltage signal measured from the resistor R1to generate output data DOUT, a digital representation of leakage current ILK. In this manner, the circuit110for measuring a leakage current may measure a leakage current flowing through transistors or functional blocks included in each of semiconductor integrated circuits of a real product (that is, an operational integrated circuit), without requiring separate pads that may be required for testing were a conventional approach to testing, one requiring external test circuits, employed.

FIG. 2is a circuit diagram illustrating an exemplary embodiment of a semiconductor integrated circuit200that includes a circuit for measuring a leakage in accordance with principles of inventive concepts. Semiconductor integrated circuit200may include a block to be tested250and a circuit210for measuring a leakage current from the block to be tested250. The block to be tested250may include a first NMOS transistor MN1.

The circuit210for measuring leakage current may include an operational amplifier OP1, a first PMOS transistor MP1, a first switch113, a second PMOS transistor MP2, a resistor R1, an A/D converter111, a second switch112, a third switch114and a fourth switch115.

In exemplary embodiments second switch112is connected between a source of the first NMOS transistor MN1and the ground voltage GND. The third switch114has a first terminal connected to a first terminal of the first switch113, a second terminal connected to the ground voltage GND, and a third terminal connected to a gate of the first NMOS transistor MN1. The fourth switch115has a first tensional connected to a first terminal of the first switch113, a second terminal connected to the ground voltage GND, and a third terminal connected to a drain of the first NMOS transistor MN1.

In exemplary embodiments, switches112through115may be operated so that, when gate-on current (Ig_on) of an NMOS transistor is measured, the gate of the first NMOS transistor may be electrically connected to the feedback node NFB, and the source and drain of the first NMOS transistor MN1may be electrically connected to the ground voltage GND and when drain-off current (Id_off) of an NMOS transistor is measured, the gate and source of the first NMOS transistor MN1may be electrically connected to the ground voltage GND, and the drain of the first NMOS transistor MN1may be electrically connected to the feedback node NFB. Operation of current mirror MP1/MP2, operational amplifier OP1, and A/D converter111has been described in detail in the discussion related toFIG. 1and that description will not be repeated here.

FIG. 3is a circuit diagram illustrating an exemplary embodiment of a semiconductor integrated circuit300that includes a circuit for measuring a leakage current in accordance with principles of inventive concepts. Semiconductor integrated circuit300may include a block to be tested350and a circuit310for measuring a leakage current associated with the block to be tested350. The block to be tested350may include a third PMOS transistor MP3.

The circuit310for measuring a leakage current may include an operational amplifier OP1, a first PMOS transistor MP1, a first switch113, a second PMOS transistor MP2, a resistor R1, an A/D converter111, a second switch120, a third switch117, a fourth switch118and a fifth switch119.

In exemplary embodiments, second switch120is connected between a drain of the third PMOS transistor MP3and the ground voltage GND. Third switch117has a first terminal connected to a first terminal of the first switch113, a second terminal connected to a second supply voltage VDD, and a third terminal connected to a gate of the third PMOS transistor MP3. The fourth switch118has a first terminal connected to the first terminal of the first switch113, a second terminal connected to the second supply voltage VDD, and a third terminal connected to a source of the third PMOS transistor MP3. The fifth switch119has a first terminal connected to the first terminal of the first switch113, a second terminal connected to the second supply voltage VDD, and a third terminal connected to a bulk of the third PMOS transistor MP3.

In exemplary embodiments switches113,117,118,119, and120may be operated so that, when a gate-off current (Ig_off) of a PMOS transistor is measured, the gate of the third PMOS transistor MP3may be electrically connected to the feedback node NFB, the source and bulk of the third PMOS transistor MP3may be electrically connected to the second supply voltage VDD, and the drain of the third PMOS transistor MP3may be electrically connected to the ground voltage GND. Additionally, when a source-off current (Is_off) of a PMOS transistor is measured, the gate and bulk of the third PMOS transistor MP3may be electrically connected to the second supply voltage VDD, the source of the third PMOS transistor MP3may be electrically connected to the feedback node NFB, and the drain of the third PMOS transistor MP3may be electrically connected to the ground voltage GND. Also, when a bulk-off current (Ig_off) of a PMOS transistor is measured, the gate and source of the third PMOS transistor MP3may be electrically connected to the second supply voltage VDD, the bulk of the third PMOS transistor MP3may be electrically connected to the feedback node NFB, and the drain of the third PMOS transistor MP3may be electrically connected to the ground voltage GND. Operation of current mirror MP1/MP2, operational amplifier OP1, and A/D converter111has been described in detail in the discussion related toFIG. 1and that description will not be repeated here.

FIG. 4is a circuit diagram illustrating an exemplary embodiment of a semiconductor integrated circuit400that includes a circuit for measuring a leakage current in accordance with principles of inventive concepts. Semiconductor integrated circuit400may include a block to be tested450and a circuit410for measuring leakage current associated with the block to be tested450. The block to be tested450may include a second NMOS transistor MN2and a fourth PMOS transistor MP4.

The circuit410for measuring a leakage current may include an operational amplifier OP1, a first PMOS transistor MP1, a first switch113, a second PMOS transistor MP2, a resistor R1, an A/D converter111, a second switch112, a third switch114, a fourth switch115, a fifth switch120, a sixth switch117, a seventh switch118and an eighth switch119.

The second switch112is connected between a source of the second NMOS transistor MN2and the ground voltage GND. The third switch114has a first terminal connected to a first terminal of the first switch113, a second terminal connected to the ground voltage GND, and a third ten final connected to a gate of the second NMOS transistor MN2. The fourth switch115has a first terminal connected to the first terminal of the first switch113, a second terminal connected to the ground voltage GND, and a third terminal connected to a drain of the second NMOS transistor MN2. The fifth switch120is connected between a drain of the fourth PMOS transistor MP4and the ground voltage GND. The sixth switch117has a first terminal connected to the first terminal of the first switch113, a second terminal connected to a second supply voltage VDD, and a third terminal connected to a gate of the fourth PMOS transistor MP4. The seventh switch118has the first terminal connected to the first terminal of the first switch113, a second terminal connected to the second supply voltage VDD, and a third terminal connected to a source of the third PMOS transistor. The eighth switch119has the first terminal connected to the first terminal of the first switch113, the second terminal connected to the second supply voltage VDD, and a third terminal connected to a bulk of the fourth PMOS transistor MP4.

In exemplary embodiments switches112,112,114,115,117,118,119, and120may be operated so that, when a gate-on current (Ig_on) of an NMOS transistor is measured, the gate of the second NMOS transistor MN2may be electrically connected to the feedback node NFB, and the source and drain of the second NMOS transistor MN2may be electrically connected to the ground voltage GND. When a drain-off current (Id_off) of an NMOS transistor is measured, the gate and source of the second NMOS transistor MN2may be electrically connected to the ground voltage GND, and the drain of the second NMOS transistor MN2may be electrically connected to the feedback node NFB. Additionally, when a gate-off current (Ig_off) of a PMOS transistor is measured, the gate of the fourth PMOS transistor MP4may be electrically connected to the feedback node NFB, the source and bulk of the fourth PMOS transistor MP4may be electrically connected to the second supply voltage VDD, and the drain of the fourth PMOS transistor MP4may be electrically connected to the ground voltage GND. And when a source-off current (Is_off) of a PMOS transistor is measured, the gate and bulk of the fourth PMOS transistor MP4may be electrically connected to the second supply voltage VDD, the source of the fourth PMOS transistor MP4may be electrically connected to the feedback node NFB, and the drain of the fourth PMOS transistor MP4may be electrically connected to the ground voltage GND. Also, when a bulk-off current (Ib_off) of a PMOS transistor is measured, the gate and source of the fourth PMOS transistor MP4may be electrically connected to the second supply voltage VDD, the bulk of the fourth PMOS transistor MP4may be electrically connected to the feedback node NFB, and the drain of the fourth PMOS transistor MP4may be electrically connected to the ground voltage GND. Operation of current mirror MP1/MP2, operational amplifier OP1, and A/D converter111has been described in detail in the discussion related toFIG. 1and that description will not be repeated here.

FIG. 5is a table illustrating voltages applied to transistors included in an integrated circuit according to modes of measuring a leakage current in accordance with principles of inventive concepts. As indicated in the table, in the mode in which a gate-on current Ig_on of an NMOS transistor is measured, the feedback voltage VFB may be applied to the gate of the NMOS transistor, and the source and drain of the NMOS transistor may be electrically connected to the ground voltage GND. In the mode in which a drain-off current Id_off of an NMOS transistor is measured, the gate and source of the NMOS transistor may be electrically connected to the ground voltage GND, and the feedback voltage VFB may be applied to the drain of the NMOS transistor.

In the mode in which a gate-off current Ig_off of a PMOS transistor is measured, the feedback voltage VFB may be applied to the gate of the PMOS transistor, the second supply voltage VDD may be applied to the source and bulk of the PMOS transistor, and the drain of the PMOS transistor may be electrically connected to the ground voltage GND. In the mode in which a source-off current Is_off of a PMOS transistor is measured, the second supply voltage VDD may be applied to the gate and bulk of the PMOS transistor, the feedback voltage VFB may be applied to the source of the PMOS transistor, and the drain of the fourth PMOS transistor MP4may be electrically connected to the ground voltage GND. In the mode in which a bulk-off current Ib_off of a PMOS transistor is measured, the second supply voltage VDD may be applied to the gate and source of the fourth PMOS transistor MP4, the feedback voltage VFB may be applied to the bulk of the PMOS transistor, and the drain of the PMOS transistor may be electrically connected to the ground voltage GND.

FIG. 6is a circuit diagram illustrating an exemplary embodiment of a semiconductor integrated circuit500that includes a circuit for measuring a leakage current in accordance with principles of inventive concepts. Semiconductor integrated circuit500may include a block to be tested550and a circuit110for measuring a leakage current from the block to be tested550. The circuit110for measuring a leakage current inFIG. 6may have the same configuration as the circuit110for measuring a leakage current shown inFIG. 1. The block to be tested550may include an inverter that includes a PMOS transistor MP11and an NMOS transistor MN11. The circuit110for measuring a leakage current inFIG. 6may measure a leakage current flowing through the block to be tested550that includes the inverter. Operation of current mirror MP1/MP2, operational amplifier OP1, and A/D converter111has been described in detail in the discussion related toFIG. 1and that description will not be repeated here.

FIG. 7is a circuit diagram illustrating an exemplary embodiment of a semiconductor integrated circuit600that includes a circuit for measuring a leakage current in accordance with principles of inventive concepts. Semiconductor integrated circuit600may include a block to be tested650and a circuit110for measuring a leakage current from the block to be tested650. The circuit110for measuring a leakage current inFIG. 7may have the same configuration as the circuit110for measuring a leakage current shown inFIG. 1. The block to be tested650may include a NAND gate. The circuit110for measuring a leakage current inFIG. 7may measure a leakage current flowing through the block to be tested650that includes the NAND gate. Operation of current mirror MP1/MP2, operational amplifier OP1, and A/D converter111has been described in detail in the discussion related toFIG. 1and that description will not be repeated here.

FIG. 8is a circuit diagram illustrating an exemplary embodiment of a semiconductor integrated circuit700that includes a circuit for measuring a leakage current in accordance with principles of inventive concepts. Semiconductor integrated circuit700may include a block to be tested750and a circuit110for measuring a leakage current from the block to be tested750. The circuit110for measuring a leakage current inFIG. 8may have the same configuration as the circuit110for measuring a leakage current shown inFIG. 1. The block to be tested750may include a NOR gate. The circuit110for measuring a leakage current inFIG. 8may measure a leakage current flowing through the block to be tested750that includes the NOR gate. Operation of current mirror MP1/MP2, operational amplifier OP1, and A/D converter111has been described in detail in the discussion related toFIG. 1and that description will not be repeated here.

FIG. 9is a circuit diagram illustrating an exemplary embodiment of a semiconductor integrated circuit800that includes a circuit for measuring a leakage current in accordance with principles of inventive concepts. Semiconductor integrated circuit800may include a plurality of leakage current measuring circuits802and804and a plurality of functional blocks810to860.

The semiconductor integrated circuit800shown inFIG. 9may measure leakage current flowing through functional blocks810to860using leakage current measuring circuits802and804included in the semiconductor integrated circuit800. Each of the leakage current measuring circuits802and804may be configured as any of the circuits110,210,310or410for measuring a leakage current according to exemplary embodiments in accordance with principles of inventive concepts and may measure leakage currents flowing through the functional blocks810to860.

A circuit for measuring leakage current from a semiconductor integrated circuit according to embodiments of inventive concepts is able to precisely measure leakage current flowing through transistors or functional blocks included in a semiconductor integrated circuit of a real product (that is, an operational chip, not a test chip). Because the testing takes place “on board” the chip, no additional pads are required for testing. Exemplary embodiments of inventive concepts may be applied to a semiconductor integrated circuit, and particularly, to a system-on-chip (SoC).