PIXEL DEFINING ENCAPSULATING BARRIER FOR RGB COLOR PATTERNING

Examples disclosed herein relate to device. The device includes a substrate, a plurality of adjacent pixel-defining layer (PDL structures disposed over the substrate, and a plurality of sub-pixels. The PDL structure have a top surface coupled to adjacent sidewalls of the PDL structure. The plurality of sub-pixels are defined by the PDL structures. Each sub-pixel includes an anode, an organic light emitting diode (OLED), a cathode, and an encapsulation layer. The organic light emitting diode (OLED) material disposed over the anode. The OLED material extends over the top surface of the PDL structure past the adjacent sidewalls. The cathode is disposed over the OLED material. The cathode extends over the top surface of the PDL structure past the adjacent sidewalls. The encapsulation layer is disposed over the cathode. The encapsulation layer has a first sidewall and a second sidewall.

BACKGROUND

Field

Embodiments of the present disclosure generally relate to a display. More specifically, embodiments described herein relate to sub-pixel circuits and methods of forming sub-pixel circuits that may be utilized in a display such as an organic light-emitting diode (OLED) display.

Description of the Related Art

Input devices including display devices may be used in a variety of electronic systems. An organic light-emitting diode (OLED) is a light-emitting diode (LED) in which the emissive electroluminescent layer is a film of an organic compound that emits light in response to an electric current. OLED devices are classified as bottom emission devices if light emitted passes through the transparent or semi-transparent bottom electrode and substrate on which the panel was manufactured. Top emission devices are classified based on whether or not the light emitted from the OLED device exits through the lid that is added following the fabrication of the device. OLEDs are used to create display devices in many electronics today. Today's electronics manufacturers are pushing these display devices to shrink in size while providing higher resolution than just a few years ago.

OLED pixel patterning is currently based on a process that restricts panel size, pixel resolution, and substrate size. Rather than utilizing a fine metal mask, photolithography should be used to pattern pixels. Currently, OLED pixel patterning requires lifting off organic material after the patterning process. When lifted off, the organic material leaves behind a particle issue that disrupts OLED performance. Accordingly, what is needed in the art are sub-pixel circuits and methods of forming sub-pixel circuits that may be utilized in a display such as an organic OLED display.

SUMMARY

In one embodiment, a device is provided. The device includes a substrate, a plurality of adjacent pixel-defining layer (PDL) structures disposed over the substrate, and a plurality of sub-pixels defined by the PDL structures. The PDL structure has a top surface coupled to adjacent sidewalls of the PDL structure. Each sub-pixel includes an anode, an organic light emitting diode (OLED) material, a cathode, and an encapsulation layer. The organic light emitting diode (OLED) material is disposed over the anode. The OLED material has a first OLED end and a second OLED end that extend over the top surface of the PDL structure past the adjacent sidewalls. The cathode is disposed over the OLED material. The cathode has a first cathode end and a second cathode end that extend over the top surface of the PDL structure past the adjacent sidewalls. An encapsulation layer is disposed over the cathode. The encapsulation layer has a first sidewall and a second sidewall, wherein the first sidewall and the second sidewall extend past the first OLED end, the second OLED end, the first cathode end, and the second cathode end.

In another embodiment, a method of forming a device is provided. The method includes positioning a substrate. The substrate includes a first opening of a first sub-pixel defined by a plurality of adjacent pixel-defining layer (PDL) structures disposed over the substrate and a first anode defined by the adjacent PDL structures. The method further includes depositing an OLED material, a cathode, and an encapsulation layer of the first sub-pixel over the substrate, forming a resist in a well of the first sub-pixel, removing the encapsulation layer of the first sub-pixel exposed by the resist of the first sub-pixel, removing the OLED material and the cathode of the first sub-pixel exposed by the resist of the first sub-pixel. The method further includes positioning the substrate, the substrate further including a second opening of a second sub-pixel defined by the plurality of PDL structures disposed over the substrate and a second anode defined by the adjacent PDL structures. The method then includes depositing an OLED material, a cathode, and an encapsulation layer of the second sub-pixel over the substrate, forming a resist in a well of the second sub-pixel, removing the encapsulation layer of the second sub-pixel exposed by the resist, removing the OLED material and cathode of the second sub-pixel exposed by the resist, and removing the resist of the second sub-pixel.

In another embodiment, a device is provided. The device includes a substrate, a plurality of adjacent pixel-defining layer (PDL) structures disposed over the substrate, and a plurality of sub-pixels defined by the PDL structures. The PDL structure has a top surface coupled to adjacent sidewalls of the PDL structure. Each sub-pixel includes an anode, an organic light emitting diode (OLED) material, a cathode disposed over the anode, a plug, an encapsulation layer disposed over the plug. The OLED material has a first OLED end and a second OLED end that extend over the top surface of the PDL structure past the adjacent sidewalls. The cathode has a first cathode end and a second cathode end that extend over the top surface of the PDL structure past the adjacent sidewalls. The plug is disposed over the cathode. The encapsulation layer is disposed over the plug. The encapsulation layer has a first sidewall and a second sidewall. The first sidewall and the second sidewall extend past the first OLED end, the second OLED end, the first cathode end, and the second cathode end.

In another embodiment, a method of forming a device is provided. The method includes positioning a substrate. The substrate includes a first opening of a first sub-pixel defined by a plurality of adjacent pixel-defining layer (PDL) structures disposed over the substrate and a first anode defined by the adjacent PDL structures. The method further includes depositing an OLED material, a cathode, and an encapsulation layer of the first sub-pixel over the substrate, forming a plug in a well of the first sub-pixel, the plug having a first plug transmittance that is matched or substantially matched to an OLED transmittance of the OLED material of the first sub-pixel, removing the encapsulation layer of the first sub-pixel exposed by the plug of the first sub-pixel, removing the OLED material and the cathode of the first sub-pixel exposed by the plug of the first sub-pixel, depositing a second encapsulation layer over the plug and first encapsulation layer of the first sub-pixel, and removing portions of the second encapsulation layer disposed over a second sub-pixel. The method further includes positioning the substrate. The substrate further includes a second opening of the second sub-pixel defined by the plurality of PDL structures disposed over the substrate and a second anode defined by the adjacent PDL structures. The method further includes depositing an OLED material, a cathode, and an encapsulation layer of the second sub-pixel over the substrate, forming a plug in a well of the second sub-pixel, the plug having a first plug transmittance that is matched or substantially matched to an OLED transmittance of the OLED material of the first sub-pixel, removing the first encapsulation layer of the second sub-pixel exposed by the plug of the second sub-pixel, removing the OLED material and cathode of the second sub-pixel exposed by the plug of the second sub-pixel, depositing a second encapsulation layer over the plug and first encapsulation layer of the second sub-pixel, and removing portions of the second encapsulation layer disposed over a first sub-pixel.

DETAILED DESCRIPTION

Embodiments described herein generally relate to a display. More specifically, embodiments described herein relate to sub-pixel circuits and methods of forming sub-pixel circuits that may be utilized in a display such as an organic light-emitting diode (OLED) display.

FIG.1Ais a schematic, cross-sectional view of a sub-pixel circuit100having a plugless arrangement101A. The cross-sectional view ofFIG.1Ais taken along section line1″-1″ ofFIGS.1C and1D.FIG.1Bis a schematic, cross-sectional view of a sub-pixel circuit100having a plug arrangement101B. The cross-sectional view ofFIG.1Bis taken along section line1″-1″ ofFIGS.1C and1D.

The sub-pixel circuit100includes a substrate102. Metal-containing layers104may be patterned on the substrate102and are defined by adjacent pixel-defining layer (PDL) structures126disposed on the substrate102. In one embodiment, the metal-containing layers104are pre-patterned on the substrate102. E.g., the substrate102is a pre-patterned indium tin oxide (ITO) glass substrate. The metal-containing layers104are configured to operate as anodes of respective sub-pixels. In one embodiment, the metal-containing layer104is a layer stack of a first transparent conductive oxide (TCO) layer, a second metal-containing layer disposed on the first TCO layer, and a third TCO layer disposed on the second metal containing layer. The metal-containing layers104include, but are not limited to, chromium, titanium, gold, silver, copper, aluminum, ITO, a combination thereof, or other suitably conductive materials.

The PDL structures126are disposed on the substrate102. The PDL structures include a top surface126A coupled to two adjacent sidewalls126B. The PDL structures126include one of an organic material, an organic material with an inorganic coating disposed thereover, or an inorganic material. The organic material of the PDL structures126includes, but is not limited to, polyimides. The inorganic material of the PDL structures126includes, but is not limited to, silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (Si2N2O), magnesium fluoride (MgF2), or combinations thereof. Adjacent PDL structures126define a respective sub-pixel and expose the anode (i.e., metal-containing layer104) of the respective sub-pixel of the sub-pixel circuit100.

The sub-pixel circuit100has a plurality of sub-pixels106including at least a first sub-pixel108A and a second sub-pixel108B. While the Figures depict the first sub-pixel108A and the second sub-pixel108B, the sub-pixel circuit100of the embodiments described herein may include three or more sub-pixels106, such as a third and fourth sub-pixel. Each sub-pixel106has an organic light-emitting diode (OLED) material112configured to emit a white, red, green, blue or other color light when energized. E.g., the OLED material112of the first sub-pixel108A emits a red light when energized, the OLED material of the second sub-pixel108B emits a green light when energized, the OLED material of a third sub-pixel emits a blue light when energized, and the OLED material of a fourth sub-pixel and a fifth sub-pixel emits another color light when energized. In one embodiment, the OLED material is different than the material of the PDL structures126. The OLED material112is disposed over the PDL structures126. In one embodiment, the OLED material112is disposed on the top surface126A of the PDL structures126. In one embodiment, the OLED material has a first end112A and a second end112B disposed over a top surface126A of the adjacent PDL structures126and extending past an endpoint of the metal-containing layer104. In another embodiment, the first end112A of the OLED material112extends past a respective sidewall126B of the PDL structures126and the second end112B of the OLED material112extends past another respective sidewall126B of the PDL structures126.

A cathode114is disposed over the OLED material112. In one embodiment, the cathode114is disposed on the OLED material112. The cathode includes a conductive material, such as a metal or metal alloy. E.g., the cathode114includes, but is not limited to, chromium, titanium, aluminum, ITO, or a combination thereof. In one embodiment, the material of the cathode114is different from the material of the OLED material112and the PDL structures126. In one embodiment, the cathode114contacts an assistant cathode (not shown). In another embodiment, the cathode114contacts busbars (not shown) outside of an active area of the sub-pixel circuit100. The cathode further includes a first end114A and a second end114B. The first end114A and the second end114B are disposed over the top surface126A of the adjacent PDL structures126. In one embodiment, the first end112A and second end112B of the OLED material extends further over the top surface126A of the adjacent PDL structures126than the first end114A and second end114B of the cathode. In one embodiment, the first end114A and the second end114B of the cathode114extend past the endpoint of the metal-containing layer104. In another embodiment, the first end114A of the cathode114extends past a respective sidewall126B of the PDL structures126and the second end114B of the cathode114extends past another respective sidewall126B of the PDL structures126.

Each sub-pixel106includes include an encapsulation layer116. The encapsulation layer116may be or may correspond to a local passivation layer. The encapsulation layer116of a respective sub-pixel is disposed over the cathode114(and OLED material112) with the encapsulation layer116. The encapsulation layer116includes a first sidewall116A and a second sidewall116B. The first sidewall116A and second sidewall116B of the encapsulation layer116extend beyond the first end112A and second end112B of the OLED material112. The first sidewall116A and second sidewall116B of the encapsulation layer116extend beyond the first end114A and second end114B of the cathode114. The encapsulation layer116contacts the first end112A, the second end112B, the first end114A, the second end114B, and the top surface126A. In one embodiment, a gap G separates the second sidewall116B of the encapsulation layer116of the first pixel108A from the first sidewall116A of the encapsulation layer116of the second pixel108B. The encapsulation layer116may be varied using deposition thicknesses. E.g., the encapsulation layer116may have a thickness 0.1 μm, and 2 μm. The encapsulation layer116includes a non-conductive inorganic material, such as a silicon-containing material. The silicon containing material may include Si3N4containing materials. In one embodiment, the material of the encapsulation layer116is different from the material of the cathode114, the OLED material112and the PDL structures126.

In embodiments including one or more capping layers, the capping layers are disposed between the cathode114and the encapsulation layer116. E.g., a first capping layer and a second capping layer are disposed between the cathode114and the encapsulation layer116. Each of the embodiments described herein may include one or more capping layers disposed between the cathode114and the encapsulation layer116. The first capping layer may include an organic material. The second capping layer may include an inorganic material, such as lithium fluoride. The first capping layer and the second capping layer may be deposited by evaporation deposition. The plugless arrangement101A and the plug arrangement101B of the sub-pixel circuit100further includes a global passivation layer121. The global passivation layer121is disposed over the encapsulation layer116. In one embodiment, the global passivation layer121is disposed over the first sidewall116A and second sidewall116B of the encapsulation layer116and a portion of the top surface126A of the PDL structures126in the gap G. In another embodiment, the global passivation layer121is disposed on the top surface126A of the PDL structures126in the gap G. In yet another embodiment, the global passivation layer121may include an intermediate layer118and a passivation layer120. In one embodiment, the intermediate layer118is disposed over the first sidewall116A and second sidewall126B of the PDL structures126and a portion of the top surface126A of the PDL structures126in the gap G. In another embodiment, the intermediate layer118is disposed on the top surface126A of the PDL structures126in the gap G. In another embodiment, the global passivation layer121, the intermediate layer118, and the passivation layer120do not contact the OLED material112or the cathode114. The intermediate layer118may include an inkjet material, such as an acrylic material.

The plug arrangement101B includes a plug122disposed within the encapsulation layers116. Each plug122is disposed in a respective sub-pixel106of the sub-pixel circuit100. The plugs122may have an additional passivation layer disposed thereon. The plugs include, but are not limited to, a photoresist, a color filter, or a photosensitive monomer. The plugs122have a plug transmittance that is matched or substantially matched to an OLED transmittance of the OLED material112. The plugs122may each be the same material and match the OLED transmittance. The plugs122may be different materials that match the OLED transmittance of each respective sub-pixel of the plurality of sub-pixels106. The matched or substantially matched plug transmittance and OLED transmittance allow for the plugs122to remain over the sub-pixels106over the sub-pixels106without blocking the emitted light from the OLED material112. The plugs122are able to remain in place and thus do not require a lift off procedure to be removed from the sub-pixel circuit100. Additional pattern resist materials disposed over the formed sub-pixels106at subsequent operations are not required because the plugs122remain. Eliminating the need for a lift-off procedure on the plugs and the need for additional pattern resist materials on the sub-pixel100increases throughout.

FIG.1Cis a schematic, top sectional view of a sub-pixel circuit100having a dot-type architecture101C.FIG.1Dis a schematic, cross-sectional view of a sub-pixel circuit100having a line-type architecture101D. Each of the top sectional views ofFIGS.1C and1Dare taken along section line1′-1′ ofFIGS.1A and1B. The dot-type architecture101C includes a plurality of pixel openings124A from adjacent PDL structures126. Each of pixel openings124A defines each of the sub-pixels106of the dot-type architecture101C. The line-type architecture101D includes a plurality of pixel openings124B from adjacent PDL structures126. Each of pixel openings124B define each of the sub-pixels106of the line-type architecture101D.

FIG.2is a flow diagram of a method200for forming a sub-pixel circuit100having a plugless arrangement101A.FIGS.3A-3Pare schematic, cross-sectional views of substrate102during a method200for forming a sub-pixel circuit100having a plugless arrangement101A.

At operation201, as shown inFIG.3A, the OLED material112, the cathode114, and a first encapsulation layer116A of the first sub-pixel108A are deposited over the substrate102. The OLED material112, the cathode114, and a first encapsulation layer116A are disposed over the PDL structures126and the metal-containing layer104. In embodiments including capping layers, the capping layers are deposited between the cathode114and the first encapsulation layer116A. The capping layers may be deposited by evaporation deposition. In one embodiment, the OLED material112and the cathode114are deposited using evaporation deposition.

At operation202, as shown inFIG.3B, a resist302is formed in a well of the first sub-pixel108A. The resist302is disposed over the first encapsulation layer116A. The resist302has a width W. The resist302is a positive resist or a negative resist. A positive resist includes portions of the resist which, when exposed to electromagnetic radiation, are respectively soluble to a resist developer applied to the resist after the pattern is written into the resist using the electromagnetic radiation. A negative resist includes portions of the resist which, when exposed to electromagnetic radiation, are respectively insoluble to a resist developer applied to the resist after the pattern is written into the resist using the electromagnetic radiation. The chemical composition of resist302determines whether the resist is a positive resist or a negative resist. The resist302is patterned to form one of a pixel opening124A of the dot-type architecture101C or a pixel opening124B of the line-type architecture101D of a first sub-pixel108A. The patterning is one of a photolithography, digital lithography process, or laser ablation process.

At operation203, as shown inFIG.3C, the first encapsulation layer116A exposed by the resist302is removed. The first encapsulation layer116A exposed by resist302may be removed by dry etch process. At operation204, as shown inFIG.3D, the cathode114and the OLED material112exposed by the resist302are removed. The cathode114and the OLED material112exposed by resist302may be removed by dry etch process. The dry etch processes of operations203and204are anisotropic or substantially anisotropic. The width W1of resist302creates a buffer zone303over the PDL structure126. Any residual isotropic etching that occurs during the dry etch processes is limited to the buffer zone303. This results in limited damage to the OLED material112and cathode114of the first sub-pixel108A.

At an operation205, as shown inFIG.3E, a second encapsulation layer116B is deposited. The second encapsulation layer116B is disposed over the resist302and the first encapsulation layer116A. At optional operation206, as shown inFIG.3F, a resist304is formed over the second encapsulation layer in a well of the first sub-pixel108A. In one embodiment, the resist304has a width W2that is greater than the width W1of the resist302. The resist304is a positive resist or a negative resist.

At optional operation207, as shown inFIG.3G, the second encapsulation layer116B exposed by the resist304is removed. The second encapsulation layer116B exposed by resist304may be removed by dry etch process. The dry etch process is anisotropic or substantially anisotropic. The width W2of the resist304creates a buffer zone305over the PDL structure126. Any residual isotropic etching that occurs during the dry etch process is limited to the buffer zone305. This results in the second encapsulation layer116B between the resist302and the resist304and a residual thickness t1adjacent to the first encapsulation layer116A. The residual thickness t1of second encapsulation layer116B isolates the cathode114and OLED material112from exposure to etchant in further etching operations. The first encapsulation layer116A and the residual thickness t1of second encapsulation layer116B result in the encapsulation layer116ofFIG.1A.

At operation208, as shown inFIG.3H, the resist302, the optional resist304, and the second encapsulation layer116B between the resist302and the resist304are removed, forming the first sub-pixel108A.

At operation209, as shown inFIG.3I, the OLED material112, the cathode114, and a first encapsulation layer116A of the second sub-pixel108B are deposited over the substrate102. The OLED material112, the cathode114, and a first encapsulation layer116A are disposed over the PDL structures126and the metal-containing layer104. In embodiments including capping layers, the capping layers are deposited between the cathode114and the first encapsulation layer116A. The capping layers may be deposited by evaporation deposition. In one embodiment, the OLED material112and the cathode114are deposited using evaporation deposition.

At operation210, as shown inFIG.3J, a resist306is formed in a well of the second sub-pixel108B. The resist306is disposed over the first encapsulation layer116A. The resist306has a width W3. The resist306is a positive resist or a negative resist. The resist306is patterned to form one of a pixel opening124A of the dot-type architecture101C or a pixel opening124B of the line-type architecture101D of a second sub-pixel108B. The patterning is one of a photolithography, digital lithography process, or laser ablation process.

At operation211, as shown inFIG.3K, the first encapsulation layer116A exposed by the resist306is removed. The first encapsulation layer116A exposed by resist306may be removed by dry etch process. At operation212, as shown inFIG.3L, the cathode114and the OLED material112exposed by the resist306are removed. The cathode114and the OLED material112exposed by resist306may be removed by dry etch process. The dry etch processes of operations211and212are anisotropic or substantially anisotropic. The width W3of resist306creates a buffer zone307over the PDL structure126. Any residual isotropic etching that occurs during the dry etch processes is limited to the buffer zone307. This results in limited damage to the OLED material112and cathode114of the second sub-pixel108B.

At an operation213, as shown inFIG.3M, a second encapsulation layer116B is deposited. The second encapsulation layer116B is disposed over the resist306and the first encapsulation layer116A. At optional operation214, as shown inFIG.3N, a resist308is formed over the second encapsulation layer in a well of the second sub-pixel108B. In one embodiment, the resist304has a width W4that is greater than the width W3of the resist306. The resist308is a positive resist or a negative resist.

At optional operation215, as shown inFIG.3O, the second encapsulation layer116B exposed by the resist308is removed. The second encapsulation layer116B exposed by resist308may be removed by dry etch process. The dry etch process is anisotropic or substantially anisotropic. The width W4of the resist308creates a buffer zone309over the PDL structure126. Any residual isotropic etching that occurs during the dry etch process is limited to the buffer zone309. This results in the second encapsulation layer116B between the resist306and the resist308and a residual thickness t2adjacent to the first encapsulation layer116A. The residual thickness t2of second encapsulation layer116B isolates the cathode114and OLED material112from further etching operations. The first encapsulation layer116A and the residual thickness t2of second encapsulation layer116B result in the encapsulation layer116ofFIG.1A.

At operation216, as shown inFIG.3P, the resist306, the optional resist308, and the second encapsulation layer116B between the resist306and the resist308are removed, forming the second sub-pixel108B.

FIG.4is a flow diagram of a method400for forming a sub-pixel circuit100having a plug arrangement101B.FIGS.5A-5Pare schematic, cross-sectional views of a substrate102during the method400for forming a sub-pixel circuit100having a plug arrangement101B.

At operation401, as shown inFIG.5A, the OLED material112, the cathode114, and a first encapsulation layer116A of the first sub-pixel108A are deposited over the substrate102. The OLED material112, the cathode114, and a first encapsulation layer116A are disposed over the PDL structures126and the metal-containing layer104. In embodiments including capping layers, the capping layers are deposited between the cathode114and the first encapsulation layer116A. The capping layers may be deposited by evaporation deposition. In one embodiment, the OLED material112and the cathode114are deposited using evaporation deposition.

At operation402, as shown inFIG.5B, a plug122A is formed in a well of the first sub-pixel108A. The plug122A is disposed over the first encapsulation layer116A. The plug122A has a width W5. The plug122A includes, but is not limited to, a photoresist, a color filter, or a photosensitive monomer. The plug122A have a plug transmittance that is matched or substantially matched to an OLED transmittance of the OLED material112. The plug122A may each be the same material and match the OLED transmittance. The plug122A may be different materials that match the OLED transmittance of each respective sub-pixel of the plurality of sub-pixels106. The matched or substantially matched plug transmittance and OLED transmittance allow for the plug122A to remain over the sub-pixels106without blocking the emitted light from the OLED material112. The plug122A is able to remain in place and thus do not require a lift off procedure to be removed from the sub-pixel circuit100. The plug122A is patterned to form one of a pixel opening124A of the dot-type architecture101C or a pixel opening124B of the line-type architecture101D of a first sub-pixel108A.

At operation403, as shown inFIG.5C, the first encapsulation layer116A exposed by the plug122A is removed. The first encapsulation layer116A exposed by plug122A may be removed by dry etch process. At operation404, as shown inFIG.5D, the cathode114and the OLED material112exposed by the plug122A are removed. The cathode114and the OLED material112exposed by plug122A may be removed by dry etch process. The dry etch processes of operations403and404are anisotropic or substantially anisotropic. The width W5of plug122A creates a buffer zone503over the PDL structure126. Any residual isotropic etching that occurs during the dry etch processes is limited to the buffer zone503. This results in limited damage to the OLED material112and cathode114of the first sub-pixel108A.

At an operation405, as shown inFIG.5E, a second encapsulation layer116B is deposited. The second encapsulation layer116B is disposed over the plug122A and the first encapsulation layer116A. At optional operation406, as shown inFIG.5F, a resist504is formed in a well of the first sub-pixel108A. In one embodiment, the resist504has a width W6that is greater than the width W5of the plug122A. The resist504is a positive resist or a negative resist.

At operation407, as shown inFIG.5H, portions of the second encapsulation layer116B are removed. In embodiments without a resist504, the second encapsulation layer116B disposed in the well of the first sub-pixel108A is removed. In embodiments with the resist504, as shown inFIG.5G, the portions of the second encapsulation layer116B exposed by the resist504is removed. The second encapsulation layer116B may be removed by dry etch process. The dry etch process is anisotropic or substantially anisotropic. The width W6of the resist504creates a buffer zone505over the PDL structure126. Any residual isotropic etching that occurs during the dry etch process is limited to the buffer zone505. This results in the second encapsulation layer116B between the plug122A and the resist504and a residual thickness t3of the first encapsulation layer116A and second encapsulation layer116B adjacent to the cathode114and OLED material112. The first encapsulation layer116A and the second encapsulation layer116B result in the encapsulation layer116ofFIG.1B. The residual thickness t3of encapsulation layer116isolates the cathode114and OLED material112from further etching operations. At optional operation408, as shown inFIG.5H, the resist504is removed, forming the first sub-pixel108A.

At operation409, as shown inFIG.5I, the OLED material112, the cathode114, and a first encapsulation layer116A of the second sub-pixel108B are deposited over the substrate102. The OLED material112, the cathode114, and a first encapsulation layer116A are disposed over the PDL structures126and the metal-containing layer104. In embodiments including capping layers, the capping layers are deposited between the cathode114and the first encapsulation layer116A. The capping layers may be deposited by evaporation deposition. In one embodiment, the OLED material112and the cathode114are deposited using evaporation deposition.

At operation410, as shown inFIG.5J, a plug122B is formed in a well of the second sub-pixel108B. The plug122B is disposed over the first encapsulation layer116A. The plug122B has a width W7. The plug122B includes, but is not limited to, a photoresist, a color filter, or a photosensitive monomer. The plug122B have a plug transmittance that is matched or substantially matched to an OLED transmittance of the OLED material112. The plug122B may each be the same material and match the OLED transmittance. The plug122B may be different materials that match the OLED transmittance of each respective sub-pixel of the plurality of sub-pixels106. The matched or substantially matched plug transmittance and OLED transmittance allow for the plug122B to remain over the sub-pixels106without blocking the emitted light from the OLED material112. The plug122B is able to remain in place and thus do not require a lift off procedure to be removed from the sub-pixel circuit100. The plug122B is patterned to form one of a pixel opening124A of the dot-type architecture101C or a pixel opening124B of the line-type architecture101D of a second sub-pixel108B.

At operation411, as shown inFIG.5K, the first encapsulation layer116A exposed by the plug122B is removed. The first encapsulation layer116A exposed by plug122B may be removed by dry etch process. At operation412, as shown inFIG.5L, the cathode114and the OLED material112exposed by the plug122B are removed. The cathode114and the OLED material112exposed by plug122B may be removed by dry etch process. The dry etch processes of operations411and412are anisotropic or substantially anisotropic. The width W7of plug122B creates a buffer zone507over the PDL structure126. Any residual isotropic etching that occurs during the dry etch processes is limited to the buffer zone507. This results in limited damage to the OLED material112and cathode114of the second sub-pixel108B.

At an operation413, as shown inFIG.5M, a second encapsulation layer116B is deposited. The second encapsulation layer116B is disposed over the plug122B and the first encapsulation layer116A. At optional operation414, as shown inFIG.5N, a resist508is formed in a well of the second sub-pixel108B. In one embodiment, the resist508has a width W8that is greater than the width W7of the plug122B. The resist508is a positive resist or a negative resist.

At operation415, as shown inFIG.5P, portions of the second encapsulation layer are removed. In embodiments without a resist508, the second encapsulation layer116B disposed in the well of the second sub-pixel108A is removed. In embodiments with the resist508, as shown inFIG.5G, the portions of the second encapsulation layer116B exposed by the resist508is removed. The second encapsulation layer116B may be removed by dry etch process. The dry etch process is anisotropic or substantially anisotropic. The width W8of the resist508creates a buffer zone509over the PDL structure126. Any residual isotropic etching that occurs during the dry etch process is limited to the buffer zone509. This results in the second encapsulation layer116B between the plug122B and the resist508and a residual thickness t4of the first encapsulation layer116A and second encapsulation layer116B adjacent to the cathode114and OLED material112. The first encapsulation layer116A and the second encapsulation layer116B result in the encapsulation layer116ofFIG.1B. The residual thickness t4of the encapsulation layer116isolates the cathode114and OLED material112from further etching operations. At operation416, as shown inFIG.5P, the resist508is removed, forming the second sub-pixel108B.

In summation, described herein are sub-pixel circuits and methods of forming sub-pixel circuits that may be utilized in a display such as an organic light-emitting diode (OLED) display. Adjacent PDL structures define each sub-pixel of the sub-pixel circuit using evaporation deposition. Evaporation deposition may be utilized for deposition of OLED materials, cathodes, and encapsulation layers. Resists may be deposited to control the ends of the OLED materials, ends of the cathodes, and the sidewalls of the encapsulation layer to insulate the OLED materials and cathodes from etchant in further etching operations. A plug may be used to augment the performance of the OLED display.