Image sensor with digital output and inherent pixel non-uniformity suppression

The image sensing device provides a digital output for each pixel. As charge builds up in a pixel, the pixel output increases until it reaches a reference level. When the reference level is crossed the pixel is reset. This process is repeated several times in a given frame time cycle with the reference level steadily decreasing. The various reset times represent the light intensity on the pixel. For an image sensor array, the array is scanned multiple times during one image frame time cycle and the reference level is lowered each scan. This provides an image sensor that has built-in pixel non-uniformity suppression, digital output, and high sensitivity.

FIELD OF THE INVENTION

The present invention relates to solid-state image sensors, specifically to CMOS image sensors that have very low pixel non-uniformity and employ a single bit column A/D conversion.

BACKGROUND OF THE INVENTION

A typical image sensor senses light by converting impinging photons into electrons that are integrated (collected) in sensor pixels. After completion of integration cycle charge is converted into a voltage that is supplied to output terminals of the sensor. In CMOS image sensors the charge to voltage conversion is accomplished directly in the pixel itself and the analog pixel voltage is transferred to the output through various pixel addressing and scanning schemes. The pixels have incorporated in them a buffer amplifier, typically a source follower, which drives the sense lines that are connected to the pixels by suitable addressing transistors. The analog pixel signal can also be converted into a digital signal format on its way to the output. The digital signals are less susceptible to distortions, attenuation, and noise pickup and for this reason it is advantageous to make the conversion to digital format at the very beginning of the signal processing chain. Examples of sensors with signal conversion to digital format directly in the pixel itself can be found in U.S. Pat. No. 6,229,133 to Hynecek and in U.S. Pat. No. 5,461,425 to Fowler at al. However, this approach has also its own problems. The pixel with digital conversion incorporates many transistors and as a result has smaller aperture efficiency and sensitivity. Another problem is the A/D converter itself. The conversion typically relies on some reference voltage or a threshold to which the pixel output is compared. Since the pixel buffer amplifier has its own DC output offset level, that can vary from pixel to pixel, and the reference threshold of the A/D converter can also vary, the resulting digital output may be very non-uniform. This problem is tackled by using various analog readout schemes, such as the Correlated Double Sampling (CDS) that is applied before the A/D conversion. The CDS minimizes pixel non-uniformities by reading the pixel signal twice, once with charge and once without it. The difference is then free of the pixel DC level variations and the A/D conversion can take place. The CDS concept, however, does not eliminate non-uniformities in the column readout circuits even if the column readout is digital. The A/D converter threshold uniformity problems are minimized by using complicated self-calibrating and auto zeroing techniques as mentioned for example in the article: “A 1¼ inch 8.3 M Pixel Digital Output CMOS APS fro UDTV Applications” by: I. Takayanagi at al. published in: “Digest of Technical Papers 2003 IEEE International ISSCC Conference, pp. 216”. Unfortunately such complicated systems can be used only in the array columns, since it would not be practical to integrate them into the pixels themselves. Such circuits also consume power and occupy a significant chip area thus contributing to increased cost of these sensors.

The sensor pixel non-uniformities, the column-to-column non-uniformities, and the A/D threshold variations thus represent persistent problem in CMOS image sensors that is not easily solved.

SUMMARY OF THE INVENTION

It is an object of the present invention to overcome limitations in prior art. It is further object of the present invention to provide a practical CMOS image-sensing concept that is not sensitive to pixel or column non-uniformities. It is yet another object of the present invention to provide a practical high performance image sensor that has digital output and high sensitivity. Incorporating the single bit A/D converter in each column of the array and selectively resetting the sensor pixels only when the pixel output exceeds a certain programmed reference level accomplishes this goal. The array is scanned many times during the standard image frame time cycle and the programmed level is changed for each scan. The signal output is calculated from the number of digital pulses obtained from the sensor pixel in a given frame time cycle. It is shown that the output is proportional to a certain ratio of pulse counts, which is independent of the pixel absolute DC output level or any other DC offset shift that may be encountered in the analog signal chain as for example in the comparator or the A/D converter. Thus incorporating the variable reference, the single bit column A/D, and using multiple array's scans in one frame time cycle in a CMOS image sensor together with computing certain timing interval ratios allows achieving the pixel non-uniformity and column-to-column non-uniformity suppression and other objects of the invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

InFIG. 1the drawing100represents the circuit diagram of a prior art pixel used in CMOS image sensors. Transistor101(Q1) is connected as a source follower buffering the voltage of sense node107. The source of transistor101is connected through addressing transistor102(Q2) to column sense line108. Transistor102is turned on when horizontal (row) address line109is activated. Node107is reset when reset transistor103(Q3) is turned on. This is accomplished by activating another horizontal (row) line110. When the rows of CMOS sensor array are always scanned in a sequential order, it is possible to eliminate row reset line110and use address line109of the neighboring pixel row for this purpose. This arrangement simplifies array wiring and usually increases the pixel aperture efficiency. The Vdd bias is supplied to the pixel through connection106. Photo sensing element105is typically a reverse biased diode, but it can also be replaced by a pinned photodiode or any other suitable combination of similar light sensing elements. The important point to notice in this diagram, however, is that the reset command is supplied to pixels by row addressing lines and that all the pixels in the addressed row are reset at the same time.

FIG. 2represents the circuit diagram200of a pixel according to the present invention. Transistors201(Q1),202(Q2) and203(Q3) serve here the same purpose as transistors101,102, and103in the circuit diagram inFIG. 1. The new elements added to this pixel are transistor204(Q4) and reset column line211. The reset signal will reach pixel-reset transistor203only when the appropriate row addressing line210is activated. Similarly as in the previous case, line210can be eliminated and line209of the neighboring row of pixels used in its place when the array is always scanned progressively. Line210can also be eliminated all together and the gate of transistor204connected to the same address line as the gate of address transistor202. Sense line208, Vdd connection206, sense node207, and photo-sensing element205correspond to the same elements described in the circuit diagram inFIG. 1. The key difference to note here, however, is that the reset signal for pixels is supplied via column lines211and not via the row reset lines. In the prior art case there is no possibility to selectively reset only some of the pixels in a row. The pixel circuit shown inFIG. 2provides this important difference and capability. It is also clear to those skilled in the art that photo sensing element205can be replaced by many other light sensitive structures in particular those that have a complete charge reset and therefore do not generate kTC noise.

FIG. 3represents a block diagram300and a simplified floor plan of a CMOS image sensor that incorporates the present invention. Array301consists of pixels302that are addressed via vertical scanner306using row address lines303. The pixel output is supplied through column sense lines305to a bank of comparators307located at the bottom edge of the array. Supplying an appropriate command signal through lines311activates comparators307and the addressed pixel output is compared with the reference voltage available on line317at that time. The outputs from comparators307are stored in latches308when the store command is applied to line312. The logical output from latches308appearing on lines314is also loaded into horizontal scan register319for readout. The reset commands to reset the addressed pixels is supplied to pixels from “AND” gates309via column lines304. The pixels are reset when the reset command is applied to “AND” gate inputs via line313and when the corresponding latches are in the state of logical “1”. It is clear that not all of the pixels of an addressed row will be reset. The reset depends on the amount of integrated signal in the particular pixel and on the reference voltage level appearing on line317. When the reset occurs, however, a logical “1” appears at the appropriate time for that pixel during the sensor readout sequence on output line320. The horizontal register is readout by applying a clocking signal to line318. When the horizontal register is completely readout a pulse is applied to line316that advances vertical addressing register306to select the next row of pixels for comparison and to reset the horizontal register making it ready for the next horizontal scan. This process is repeated until all the rows of the array are processed and read out. In the next step a pulse is applied to line310. This pulse resets the vertical shift register to make it ready for the new array scan and at the same time causes reference generator315to decrement the reference voltage by one unit step. Finally, applying the reset pulse to line323resets the reference generator315. This completes the sensor frame time cycle. It is clear that the sensor array is completely scanned many times during one frame time cycle and that the number of scans equals the number of decrements of the reference voltage. The power is applied to the sensor through line321and the ground connection is established through line322. The described example represents a sensor with only a single serial digital output. It is clear to those skilled in the art that the digital signal loaded into horizontal register319can be formatted in many ways and that multiple serial/parallel output combinations are possible to increase the data throughput when required by a particular device application. Various layout modifications are also possible with comparators and serial registers located on both the top and the bottom edges of the array.

The operation of the system can be best understood with the help of the timing diagram400appearing inFIG. 4. The diagram shows graph406representing signal in a pixel (Vp) and graph403representing voltage of the reference generator (Vr), both as a function of time. When the pixel signal exceeds the reference level, the pixel is reset. This occurs at times t1, t2, t3, . . . and continues until the time tnwhen level402is crossed. After this point the pixel is always reset until the end of the frame time cycle ti. Level402(Vu) represents the pixel DC output in dark and all other thresholds encountered in the analog signal chain. The variations of this threshold would normally cause pixel-to-pixel non-uniformities. When more intense light impinges on the pixel the slope of graph406increases as is indicated by graph407. It can be shown that the output signal representing light intensity is proportional to ratio (tn−t1)/t1, which is the time interval410divided by the time interval409. From this figure it can be easily observed that this ratio is independent of level402providing that the reference voltage is decremented linearly in time from level401and the pixel voltage grows linearly with time. The detail of the reference voltage graph is shown enlarged in inset408. The graph consists of unit step decrements404, as described previously, that stay constant during time intervals405(ts) when the array is scanned. The linearity of both waveforms403and406is not too difficult to achieve. A suitable D/A converter can easily generate the required reference voltage waveform. This is well known to those skilled in the art and will not be further discussed here. The pixel response to illumination is also known to be quite linear, however, some precautions are necessary since the capacitance of the sense node generally depends on voltage. In an actual device it may not be possible to exactly detect the time point tn. This is due to discrete nature of time that is measured in increments of tsand due to discrete nature of reference voltage waveform403. However, it is always possible to compute the time point tnfrom any of the preceding times t1, t2, t3, . . . . There are many ways to compute this time interval value that can be devised by those skilled in the art.

An example of realization of data processing flow500and computation of the output signal is shown inFIG. 5. The digital output from the sensor is received at input terminal508of shift register507. The register is clocked by a clock signal applied to terminal509. Each stage of register507interfaces with corresponding counter506. Each pixel (m,n) of the sensor has a corresponding stack of memory locations502(m,n) in the memory block501that are “k” places deep. When shift register506receives all the data for a given addressed line of the sensor, counters506are activated and loaded with data stored in memory locations504via bi-directional data bus505. This is performed for all the pixels in that line simultaneously. In the next step counters506for each pixel, which has not been reset and therefore does not contain logical “1”, are advanced by one count. The result is placed back in same locations504into memory block501. However, when the pixel has been reset, the result for this pixel is placed in a different memory location, for example location503situated deeper in the memory block. The counters will not retrieve this result any more and this count will not be advanced again during the current frame time cycle. This process is repeated for all the lines and for all the array scans in a given frame time cycle. At the end of the frame time cycle, memory locations for each pixel will thus contain counts corresponding to times t1, t2, t3. . . shown inFIG. 4. The output signal is obtain by scanning memory block501pixel by pixel and calculating the output for each pixel from data contained in each pixel memory stack510. Suitable CPU or DSP device511can be used for this purpose and calculate the simple time interval ratios or other more complex and accurate mathematical expressions that can be derived for the output signal. The result is supplied to other systems in a digital format through port513or it can be converted to analog format by suitable D/A converter512to make it available for display at terminal514. After the readout is completed all the memory locations can be reset and the process repeated. There are many variations and alterations possible for this system as is clear to those skilled in the art.

Having described preferred embodiments of a novel digital CMOS image sensor concept with 1-bit column A/D converter that has built in pixel non-uniformity suppression, which are intended to be illustrative and not limiting, it is noted that persons skilled in the art can make modifications and variations in light of the above teachings. It is therefore to be understood that changes may be made in the particular embodiments of the invention disclosed, which are within the scope and spirit of the invention as defined by the appended claims.