Electronic component handling and testing apparatus and method for electronic component handling and testing

The present invention discloses an electronic testing apparatus and a continuous test method for electronic component, which includes multiple test areas, each area possesses respective pick and place module. The apparatus includes multiple shuttles located between the test area and input/output trays. Moreover, a further pick and place module is utilized, between the shuttles and the input/output trays, for picking and placing the devices under test or tested device. The method delivers different electronic component to different test area for testing by different shuttles and to perform testing continuously.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to an electronic component test device and the method for electronic component testing, and more particularly to an Integrated Circuit (ICs) test device and the method for ICs testing, which includes a plurality of shuttles having individual pick and place module.

2. Description of the Prior Art

During the packaging process, Integrated circuit (ICs) may be damaged or packaging may not be correctly performed. The failures introduced during packaging typically cause 1 percent or more of ICs to fail. Therefore it is necessary to perform the final test, which fully inspection performed on each packaged IC prior to shipment, in order to satisfy customer's requirement.

FIG. 1shows the vertical plan view of conventional test apparatus (handler100). The handler100is a piece of equipment that “handles” the ICs and makes connections to an automatic tester (not shown) via connecting cable. The handler can be divided into two zones, the input/output zone is located in the front area of the handler and the test zone is located in the rear area of the handler. There are several input trays104and several output trays105stacking arrangement in the input/output zone of the handler. The input trays are used to store the ICs, and the output trays are used to grade the tested ICs according to Binning process, which is a process of sorting parts based on some measured performance parameter such as speed of operation or other criteria.

As shown inFIG. 1, the handling of the ICs/tested ICs is fully automated from the input trays104to the output trays105by using a fast pick and place module108based on XY mechanism with linear motors on magnetic suspension technology. The pick and place module108can take any positions of the input/output zone by slipping through x-rail109and y-rail108. The pick and place module108picks one IC from input tray104, putting it in the front depression115aof the shuttle114, then moving the shuttle114from the input/output zone of the handler100to the test zone by the way of track116.

The other pick and place module112located in the test zone picks another tested IC (which had completed the final test) from test area118by slipping through y-rail113and x-rail111, and then putting it in the rear depression115bof the shuttle114, picking the IC that had previously stored in the front depression115aof the shuttle114, putting it in the socket119of one test area118, and proceeding to undergo the final test.

While the final test is undergoing, the pick and place module108picks the tested IC which had previously stored in the rear depression115bof the shuttle114by way of the track116, sorting it by grade then putting in the output tray105.

Although the conventional handler100shown inFIG. 1has multiple test area118(six in theFIG. 1), it has only one shuttle114and only one pick and place module112can pick the IC to undergo the final test. Accordingly, it is usually more than one tested IC in the test area waiting to be picked to the shuttle114, but it can be picked until the shuttle114is back to the test zone from the input/output zone. In the meantime, the IC that had stored in the front depression115aalso cannot be picked into the test area, that is to say, wasting too much time on wait, and consequently tact time of conventional handler is too long, the tact time is the time needed to manufacture/test one unit of a product, measured as the elapsed time between the completion of one unit and the completion of the next. The long tact time cause the yield decreases significantly. Moreover, if the test time of the IC is shorter, then the time during wait will get longer. For example, if the time need to pick and place is 5 seconds, but the time need to complete test one IC is less than 30 seconds such as 10-15 seconds, then the time of stay in test area will become 10 seconds or longer.

The modern semiconductor production test equipment is increasingly complex to design, build and maintain. In order to decreasing the cost and increasing the yield, it is necessary to make full use of the handler100and to avoid idle and to increase the quantity of test per unit time, a need has arisen to propose an apparatus and a method for ICs testing, that allows for decreasing the tact time and increasing the yield.

SUMMARY OF THE INVENTION

In view of the foregoing, it is an object of the present invention to provide a test apparatus and a test method for decreasing the probability of tested component stayed in the test area when the final test has finished, and therefore increasing the yield.

In a preferred embodiment, the present invention provides an electronic component testing apparatus, which includes multiple test area and each test area includes individual pick and place module. Furthermore, multiple shuttles are provided, which is moved between the test zone and the input/output zone. In addition, one pick and place module locating in the input/output zone is provided for conveying the ICs or the tested ICs. Besides, the present invention provides a continuous test method for electronic component, which include follow steps: (a) providing at least one input tray and at least one output tray; (b) picking up the first electronic component stored in the input tray and place module and placing it in a shuttle; (c) carrying the first electronic component to first test area; (d) picking up first electronic component form the first shuttle and placing it in the first test area; (e) testing the first electronic component; (f) picking up the first tested electronic component form the first test area and placing it in the first shuttle; (g) carrying the first tested electronic component back; (h) picking up the first tested electronic component form said shuttle and placing it in one of the output trays base on test data of said tested electronic component by said I/O-pick and place module; (i) repeating said steps (b)-(i); and repeating (b)-(i) for carrying the second electronic component stored in the input tray to the second test area by the second shutter and the second test-pick and place module and to be test by the second test area after the electronic component finishes said step (b). Thus, the second electronic component, the third electronic component and so on can be test after the first electronic component is testing and the test apparatus will not be idle.

DESCRIPTION OF THE PREFERRED EMBODIMENT

The detailed description of the present invention will be discussed in the following embodiment, which is not intended to limit the scope of the present invention, but can be adapted for other applications. While drawings are illustrated in details, it is appreciated that the quantity of the disclosed components may be greater or less than that disclosed, except expressly restricting the amount of the components.

FIG. 2shows the vertical plan view of ICs test apparatus according to one embodiment of the present invention. Pluralities of input trays16for storing the ICs are stacking arrangements in the input/output zone of the handler10. Each of the input trays16with a plurality of IC aligned thereon. Similar to input trays16, there is also at least one output tray15located within the input/output zone for storing the tested IC. The tested ICs are graded to output trays15according to measured parameter. The number of input/output trays16/15and their location can be adjusted according to actual requirement.

Several test areas26are provided in the test zone of the handler10, it has four aligning in two columns in this embodiment. Either of the number of test area26or the way of aligned could be changed in other embodiment according to present invention. A socket28is provided in each test area26, it is used to connect the IC and the automatic test system (not shown) for undergoing a final test. In addition, a test-pick and place module27is located in each test area26for picking the tested IC from the socket28, or placing the IC in the socket26. Furthermore, the test-pick and place module27having contact mechanism is employed for pressing and retaining the IC even providing heat to the IC while the final test is undergoing. In this embodiment, the socket28is connected to real system such as motherboard or CD-ROM drive. However, the socket can also be connected to non-real system, for such case, the socket28will be connected to the test head of non-real system.

As shown in theFIG. 2, the handler10has multiple (four in this embodiment) shuttles22, and the shuttle has front depression22aand rear depression22bon it, which is used to store the IC and the tested IC respectively. The shuttles22carry the IC from the input/output zone to the test zone, or carry the tested IC from the test zone to the input/output zone by slipping through several tracks24(two in this embodiment), furthermore, the track24is capable of carrying more than one shuttle on it in the meantime.

A I/O-pick and place module18locating in the input/output zone of the handler10is used for picking one piece of IC from the input tray, and then placing it in the front depression22aof the shuttle22; or picking one piece of tested IC from the rear depression22bof the shuttle22, and then placing it in the different graded output trays according to the test result. There are a X-rail19and a Y-rail20for moving the I/O-pick and place module18in X-direction and Y-direction.

The sequence of whole testing process is becoming simpler, clearer and sooner than before, now describing as following: The I/O-pick and place module18picks one piece of IC form the input tray16, and then placing it in the front depression22aof the shuttle22. After that, the shuttle22moves to the test zone by way of track24. Then the test-pick and place module27picks this IC and placing it into socket28to undergo the final test. According the present invention, because the handler10has multiple shuttles and multiple tracks, so that the shuttles22are capable of moving the IC to the test zone on request immediately, without waiting the shuttles22back to input/output zone. It is the same reason the tested ICs can be carried to the input/output zone without waiting the shuttles22back to test zone. According to this embodiment of the present invention, it has decreased the waiting time of the tested IC significantly as well as makes full use of the test apparatus, consequently increasing the yield.

FIG. 3AandFIG. 3Billustrate two diagrams of IC/tested IC being picked/placed by the I/O-pick and place module18of present invention. The I/O-pick and place module18locating in the input/output zone includes input suction head18a,output suction head18b,and tray picker18c.FIG. 3Ashows the image of sucking the IC12. The input suction head18aaims at the input tray16then sucking the IC12form it, following the direction34then putting the IC12in the front depression22aof the shuttle22. Moreover, the input suction head18ais capable of reversing the IC12if there is a need before it is put into the front depression22a.FIG. 3Bshows the image of placing the IC12. The output suction head18baims at the rear depression22bthen sucking the IC12form it, following the direction38then putting the IC12in the output tray15. Moreover, the output suction head18bis capable of reversing the IC12if there is a need before it is put into the rear depression22b.

FIG. 4shows a side view taken on the front side of the handler10. When all of the ICs in the top of a stack of input trays16have picked and becoming empty, the empty input tray16will be moved away by the tray picker18cfollowing the direction of40, or moving to the output zone as the output tray15. The location of the empty input tray16will be replaced by raising the input tray under it while the empty input tray is picking by tray picker18c.Again, the ICs could be picked from the input tray16which had risen previously.

FIG. 5shows a side view taken on the rear side of the handler10. After the IC12has moved to one test area26of the test zone, the test-pick and place module27picks the IC12and placing it into the socket28following the direction of42, and then proceeding to undergo the final test. The contact mechanism of the test-pick and place module27will press and retain the IC12until the final test is finished. After the final test has done, the test-pick and place module27will pick the tested IC12from the socket28, and then putting it into the rear depression22bfollowing in the opposite direction of42. As show in the right section offigure 5, similar to the left section ofFIG. 5, the IC12follow in the direction of44to undergo the final test, and the IC12follow in the opposite direction of44to store the tested IC in the shuttle22when the final test has finished.

FIG. 6shows the follow chart of the continuous test method of the present invention. First, asFIG. 2andFIG. 6show, providing pluralities of input trays16for storing the ICs in the input/output zone of the handler10wherein pluralities of input trays are stacked, and provided at least one output trays15in the input/output zone (step610). Next, asFIG. 3AandFIG. 6show, picking one piece of IC form the input tray16, and then placing it in the front depression22aof the shuttle22(step612) by the I/O-pick and place module18. Then, carrying the IC form the input/output zone of the handler10to one of the test areas26by moving the shuttle22(step614). After that, asFIG. 5andFIG. 6show, picking the IC and placing it into the socket28of the test area26by the test-pick and place module27of the test area26(step616), and then testing the IC and get the test data of the IC (step618). In the present invention, each of the test areas26has a test-pick and place module27. During the test, the test-pick and place module27will press and retain the IC12until the final test is finished. After the test has done, picking the tested IC from the socket28, and then putting it into the rear depression22bof shuttle22by the test-pick and place module (step620). And then, moving the shuttle22to carry the tested IC back to the input/output zone (step622). After that, picking the tested IC from the rear depression22bof the shuttle22, and then placing it in the different graded output trays according to the test data and result (step624). And then, repeating the steps612-624until all ICs finish the test. In the embodiment showed inFIG. 2, there are several shuttles22on same track24, and the shuttles22are moved together to prevent the shuttles22from colliding with each other. Besides, the shuttles22on the same track24are moved together after the ICs are placed on the shuttles24.

Besides, after the picking first IC form the input tray16and placing it in the front depression22aof the shuttle22(step612), the I/O-pick and place module18is not idle. AsFIG. 6shows, another IC or second IC stored in the input tray16is picked form the input tray16, and then placing it in the front depression22aof the second shuttle22(step612′) by the I/O-pick and place module18. Next, the second IC is carried form the input/output zone of the handler10to the second test area26by moving the second shuttle22(step614′). After that, the second IC is picked and it is placed into the socket28of the second test area26by the second test-pick and place module27of the second test area26(step616′), and then testing the second IC and get the test data of the second IC (step618′). The second test-pick and place module27will press and retain the IC12until the final test is finished. After the test has done, the second tested IC is picked from the socket28, and then it is put into the rear depression22bof the second shuttle22by the second test-pick and place module (step620′). And then, moving the second shuttle22to carry the second tested IC back to the input/output zone (step622′). After that, the second tested IC is picked from the rear depression22bof the second shuttle22, and then it is placed in the different graded output trays according to the test data and result (step624′). And then, before repeating the steps612-624, repeating the step612′-624′ to carry the other ICs form the input tray16to the other test areas26which empty of finished the test to be tested when the I/O-pick and place module18is idle. Thus, the test apparatus will not idle and the IC test is continuous until all ICs have been tested. The method for IC test decreases the idle time of the test apparatus in order to increase the yield and to perform continuous IC test.

FIG. 7shows the detail flow chart of the step620and620′. First, when the test of the first IC is proceeding, another untested IC is picked from the input tray and placed in the front depression of the shuttle by I/O-pick and place module, and then the shuttle carries the untested IC to the test area with it's front depression of the shuttle (step702). And then, the test-pick and place module picks the tested IC to transfers the tested IC to the shuttle, and places the tested IC in the rear depression of the shuttle (step704). Finally, the test-pick and place module picks the untested IC from the front depression of the shuttle and places the untested IC to the test area for testing (step706). Each of the test areas have it's own test-pick and place module and shuttle and the time for transferring IC and waiting can be reduce by this.

FIG. 7shows the detail flow chart of the step624and624′. First, still another untested IC is picked from the input tray by the I/O-pick and place module (step802). And then, the I/O-pick and place module places the untested IC into the front depression of the shuttle and picks the tested IC from the rear depression of the shuttle at the same time (step804). Finally, the tested IC is placed in one of the output trays base on it's test result and the shuttle carry the untested IC to the test area for testing (step806). In the method of the present invention the untested IC and the tested IC are simultaneously transferred between the shuttle and the trays by the I/O-pick and place module. Therefore, neither the transport of the untested IC nor the transport of the untested IC does not need to wait, and the time for transferring IC will be reduced.

In addition, after All ICs in the uppest input tray finish the final test or the uppest input tray is empty, the I/O-pick and place module18will pick the uppest input tray, and then it is placed to other position of the input/output zone to be a out tray. And then the second input tray below the uppest input tray in the stack of the input trays will be a another uppest input tray and the test continuous. Besides, before the I/O-pick and place module places IC in shuttle, input tray or output tray, the IC can be reversed as desired by the I/O-pick and place module.