Memory module and memory system including row hammer counter chip and operating method thereof

A memory module including a row hammer counter chip, a memory system including the same, and a method of operating the memory system are provided. The memory module includes a plurality of data chips each of which is configured to store a data set corresponding to a plurality of burst lengths, and at least one row hammer counter chip including counter memory cells each of which is connected to a word line, among a plurality of word lines, for each of the plurality of data chips, wherein the at least one row hammer counter chip is configured to store in each of the counter memory cells connected to the word line, a number of times the word line is accessed for each of the plurality of data chips during a row hammer monitoring time frame.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based on and claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2021-0188869, filed on Dec. 27, 2021, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety.

BACKGROUND

The disclosure relates to memory systems, and more particularly, to memory modules including a row hammer counter chip.

2. Description of Related Art

Memory systems may include various types of memory modules. Memory processing is generally configured to be performed on a single memory so that the performance and characteristics of the memory processing may be determined by the single memory. Application processing that requires a large memory capacity may utilize a high-capacity memory, such as a dual in-line memory module (DIMM). The DIMM may include a plurality of dynamic random access memory (DRAM) chips implemented on a signal substrate. A controller of the memory system may provide Reliability Availability Serviceability (RAS) functions of DRAM chips.

Recently, DRAM cell sizes are decreasing to increase DRAM capacity and density. Some DRAM-based systems sometimes experience intermittent failure due to heavy workload. These failures are sometimes traced to repetitive access to a row of single memory cells, also known as row hammers. There is a problem in that the memory cells connected to the memory cell rows physically adjacent to each other are disturbed by the row hammer, thereby causing data corruption in which data flips.

Accordingly, there is a need for a method of managing and/or controlling the row hammer at the system level to meet RAS expectations.

SUMMARY

The disclosure provides memory modules including a row hammer counter chip, a memory system including the same, and a method of operating the memory system.

According to an aspect of the disclosure, there is provided a memory module including a plurality of data chips each of which is configured to store a data set corresponding to a plurality of burst lengths, and at least one row hammer counter chip including counter memory cells each of which is connected to a word line, among a plurality of word lines, for each of the plurality of data chips, wherein the at least one row hammer counter chip is configured to store in each of the counter memory cells connected to the word line, a number of times the word line is accessed for each of the plurality of data chips during a row hammer monitoring time frame.

According to another aspect of the disclosure, there is provided a memory system including: a memory module including a plurality of data chips and at least one row hammer counter chip, each of the plurality of data chips configured to store a data set corresponding to a plurality of burst lengths, and the at least one row hammer counter chip including counter memory cells each of which is connected to a word line, among a plurality of word lines of the plurality of data chips; and a memory controller configured to count a number of times the word line, among the plurality of word lines, of each of the plurality of data chips is accessed during a row hammer monitoring time frame, wherein the at least one row hammer counter chip is configured to store in each of the counter memory cells connected to the word line, the number of times the word line is accessed for each of the plurality of data chips.

According to another aspect of the disclosure, there is provided a method of operating a memory system including a memory module and a memory controller for controlling the memory module, wherein the memory module includes a plurality of data chips and a row hammer counter chip including counter memory cells each of which is connected to one of a plurality of word lines of the plurality of data chips, the method including: counting, by the memory controller, a number of times a word line, among the plurality of word lines, of each of the plurality of data chips is accessed during a row hammer monitoring time frame; and storing, by the memory controller, in each of the counter memory cells connected to the word line, the number of times the word line is accessed for each of the plurality of data chips.

DETAILED DESCRIPTION

FIG.1is a diagram illustrating a memory system including a row hammer counter chip according to example embodiments of the disclosure. A memory system1ofFIG.1includes one row hammer counter chip131per memory channel12to store a number of times each of the memory cell rows of each of memory chips110to117is accessed. Each of the memory chips110to117may identify a memory cell row with more than a threshold number of times of access, among the number of times each of the memory cell rows are accessed stored in the row hammer counter chip131, as a row-hammer-risky row, and may control the row-hammer-risky row to be target row refreshed.

Referring toFIG.1, the memory system1may include a memory module10and a memory controller20. The memory controller20may be communicatively connected to the memory module10through a memory bus30. The memory module10may include a plurality of memory chips110to117and131. According to an example embodiment, each of the memory chips110to117and131may be dynamic random access memory (DRAM) that performs the same memory transaction mechanism. According to an example embodiment, each of the memory chips110to117and131may be configured to use 16 bursts (burst length BL=16) per memory processing and provide 4 bits of information through the 4 pins of the chip, thereby performing a DDR5 mechanism with a 32-bit data width divided into 8 memory chips for an x4 implementation. Memory chips implementing the DDR5 mechanism of another example may use 16 bursts per memory processing (burst length BL=16), and may be split into 4 memory chips for an x8 implementation that provides 8 bits of information through the chip's 8 pins.

The memory module10may include one memory channel12including the memory chips110to117and131. The memory channel12may include eight data chips110to117and one row hammer counter chip131. According to another example embodiment, the memory channel12may further include one error detection code chip141and one error correction code chip151, as shown inFIG.5. According to another example embodiment, the memory channel12may include four data chips, one row hammer counter chip831, and one error correction/detection code chip841, as shown inFIG.8. However, the disclosure is not limited thereto, and as such different arrangement of chips may be provided.

The memory controller20may control overall operation of the memory system1, and may control overall data exchange between an external host and the memory chips110to117and131. For example, the host may be a computing system, such as a computer, a notebook computer, a server, a workstation, a portable communication terminal, a personal digital assistant (PDA), a portable multimedia player (PMP), a smartphone, or a wearable device. Alternatively, the host is a functional block configured to implement applications, such as learning systems, such as deep neural networks or applications, such as high-performance computing, graphics operations, and the like, and may include a processing unit such as a Central Processing Unit (CPU), a Digital Signal Processor (DSP), a Graphics Processing Unit (GPU), an Application Processor (AP) encryption processing unit, a physical processing unit, a machine learning processing unit, and the like.

The processing units of the host may control the memory module10through the memory controller20to implement applications. In some configurations, the processing unit and the memory controller20may include separate elements. In other configurations, it may be described that the memory controller20corresponds to a component provided in the processing unit of the host, and the processing unit controls the memory module10.

The memory controller20may control the memory module10according to a memory request from a host. The memory controller20may control a write operation or a read operation performed on the memory chips110to117and131by providing a command and an address to the memory module10. Also, data for a write operation and data read may be transmitted/received between the memory controller20and the memory module10. These memory access operations are performed through a memory bus30between the memory controller20and the memory module10, and may be referred to as memory processing.

The memory controller20and the memory module10may be communicatively coupled through a double data rate (DDR) DRAM interface used to perform memory access operations on the memory bus30. The DDR DRAM interface may be a memory standard interface specification of the Joint Electron Device Engineering Council (JEDEC). According to an example embodiment, one or more memory modules10are connected to the memory controller20according to the DDR DRAM interface, but the disclosure is not limited thereto. The one or more memory modules10of the disclosure may be connected to the host through various types of communication interfaces other than the DDR DRAM interface. For example, the communication interface may include an Industry Standard Architecture (ISA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Serial Advanced Technology Attachment (SATA) interface, a Small Computer System Interface (SCSI) interface, a Serial Attached SCSI (SAS) interface, a universal storage bus (USB) Attached SCSI (UAS) interface, an Internet Small Computer System Interface (iSCSI) interface, a Fiber Channel, Fiber Channel over Ethernet (FCoE) interface, or the like.

The memory controller20may include a row hammer counter21for monitoring a row hammer for all memory cell rows of each of the data chips110to117. The row hammer counter21may count a number of times each of the memory cell rows of each of the data chips110to117is accessed during a specific period of time. According to an example embodiment, the specific period of time is a preset time period. The preset time period may be set as a basic refresh rate time tREFi or a refresh window time tREFw as described below with reference toFIG.4. The memory controller20may store the number of times of access for each of the memory cell rows as counted by the row hammer counter21, in the memory cell row of the row hammer counter chip131corresponding to the memory cell row of the data chips110to117.

The memory controller20may provide the number of times of access of each of the memory cell rows of each of the data chips110to117, which is stored in the row hammer counter chip131, to the corresponding data chips110to117. In each of the data chips110to117, memory cell rows for which the number of times of access is greater than or equal to a threshold may be identified as row-hammer-risky rows to be target row refreshed.

In general, DRAM uses a limited number of registers to manage the row hammer, and the number of hammer addresses may be determined by the number of historical access times for a given time, and further, may be determined by the number of registers storing the number of times of access. As the hammer addresses are newly stored in the registers, the hammer addresses stored in the registers may be evicted from the registers, and thus, monitored row hammer information may be lost. There is a problem in that the evicted hammer address is vulnerable to the row hammer. To solve this problem, the row hammer counter21and the row hammer counter chip131may provide a per-row hammer tracking (PRHT) function for each of the data chips110to117without row hammer information loss. The PRHT function monitors a row hammer based on the number of times of access of all memory cell rows of each of the data chips110to117, thereby preventing a missing hammer address.

According to an example embodiment, the row hammer counter chip131may store metadata related to data stored in each of the data chips110to117, or store chipkill error data for disabling a nonfunctional data chip among the data chips110to117.

FIG.2is a block diagram illustrating a memory device according to example embodiments of the disclosure.FIG.3is a diagram for explaining a refresh operation of the memory device ofFIG.2.FIG.2shows the memory chip110as a representative memory chip among the memory chips110to117and131ofFIG.1. While the DRAM configuration shown inFIG.2is provided as an example, the disclosure is not limited thereto, and as such, a DRAM may have other configurations. Furthermore, the DRAM configuration shown inFIG.2as an example does not represent or imply limitations on the present disclosure. For convenience of description, the memory chip110may be a memory device or a DRAM chip and hereinafter referred to as a memory device.

Referring toFIGS.1and2, the memory device110may include a memory cell array200, a row decoder202, a column decoder206, an input and output (i.e., input/output (I/O)) gating circuit208, a control logic circuit220, an address buffer230, a refresh control circuit240, and an I/O circuit250. According to an example embodiment, the memory device110may further include a clock buffer, a mode register set (MRS), a bank control logic, a voltage generating circuit, and the like.

The address buffer230may receive an address ADDR including a bank address, a row address ROW_ADDR, and a column address COL_ADDR from the memory controller20. The address buffer230may provide the received bank address to the bank control logic, provide the received row address ROW_ADDR to the row decoder202, and provide the received column address COL_ADDR to the column decoder206.

The memory cell array200includes a plurality of memory cells provided in a matrix form arranged in rows and columns. The memory cell array200includes a plurality of word lines WL and a plurality of bit lines BL connected to the memory cells. The plurality of word lines WL may be connected to rows of memory cells, and the plurality of bit lines BL may be connected to columns of memory cells. Data of memory cells connected to an activated word line WL may be sensed and amplified by sense amplifiers connected to the bit lines BL.

The memory cell array200may include a first bank BANK 1, a second bank BANK 2, a third band BANK 3, and a fourth bank BANK 4. The bank control logic generates bank control signals based on the bank address, and the row decoder202and the column decoder206of a bank corresponding to a bank address among the first bank BANK 1, the second bank BANK 2, the third band BANK 3, and the fourth bank BANK 4 may be activated based on the bank control signals. Although an example embodiment shows an example of the memory device110including four banks, the memory device110may include any number of banks depending on the embodiment.

The row decoder202and the column decoder206may be provided to correspond to each of the first bank BANK 1, the second bank BANK 2, the third band BANK 3, and the fourth bank BANK 4, and the row decoder202and the column decoder206connected to the bank corresponding to the bank address may be activated. The row decoder202may decode the row address ROW_ADDR received from the address buffer230to select a word line WL corresponding to the row address ROW_ADDR from among the plurality of word lines WL, and connect to a word line driver that activates the selected word line WL.

The column decoder206may select preset bit lines BL from among a plurality of bit lines BL of the memory cell array200. The column decoder206may generate a column selection signal by decoding a burst address that is gradually increased by +1 based on the column address COL_ADDR in the burst mode, and connect the bit lines BL selected by the column selection signal to the I/O gating circuit208. Burst addresses refer to addresses of column locations that may be accessed in terms of burst length BL for read and/or write commands.

The I/O gating circuit208may include read data latches for storing read data of the bit lines BL selected by the column select signal, and a write driver for writing write data into the memory cell array200. The I/O circuit250may include a data input buffer260and a data output buffer270. The read data stored in the read data latches of the I/O gating circuit208may be provided to a data DQ bus through the data output buffer270. Write data may be written to the memory cell array200through the data input buffer260coupled to the data DQ bus and through the write driver of the I/O gating circuit208. According to an example embodiment, the I/O circuit250may input/output a 64-bit data set DQ_BL per memory processing through four pins DQ0 to DQ3, as shown inFIG.6. According to another example embodiment, as shown inFIG.9, the I/O circuit250may input/output a 128-bit data set DQ_BLa per memory processing through eight pins DQ0 to DQ7.

The control logic circuit220may receive a clock signal CLK and the command CMD and may generate control signals for controlling an operation timing and/or a memory operation of the memory device110. The control logic circuit220may provide control signals to circuits of the memory device110to operate as set in the operation and control parameters stored by the MRS. The control logic circuit220may read data from and write data to the memory cell array200by using control signals. Although the control logic circuit220and the address buffer230are illustrated as separate components inFIG.2, the control logic circuit220and the address buffer230may be implemented as inseparable single component. In addition, although it is illustrated inFIG.2that the command CMD and an address may be considered to be included in a command as by the DDR standard or LPDDR standard, and the like.

The control logic circuit220may receive the number of times of access of each of the memory cell rows in the memory cell array200of the memory device110from the row hammer counter chip131of the memory module10. The control logic circuit220may include a row hammer control circuit210that determines whether the number of times of access of any of the memory cell rows is greater than or equal to a threshold, and identifies a memory cell row for which the number of times of access is equal to or greater than the threshold as a row-hammer-risky row.

The row hammer control circuit210may be configured to monitor a row hammer for a memory cell row for which the number of times of access is equal to or greater than a threshold in the memory cell array200and to detect a row hammer of a particular memory cell row. A particular memory cell row refers to a memory cell row for which the number of times of access is greater than or equal to the threshold during a preset time period. As shown inFIG.3, the preset time period may be set to a 32 ms or 64 ms refresh window time tREFw defined by the JEDEC standard. According to an example embodiment, the preset time period may be set as a basic refresh rate time tREFi, as shown inFIG.3. The basic refresh rate is defined as, for example, the number of refresh commands REFRESH on the order of 8K within a 32 ms refresh window. A preset time period may be referred to as a row hammer monitor time frame or time window set by the memory controller20.

According to an example embodiment, the row hammer control circuit210may transmit information on the detected row-hammer-risky row to the memory controller20. The memory controller20may issue a normal refresh command based on row-hammer-risky row information. The memory controller20may transmit an address signal of one or more memory cell rows physically adjacent to a row-hammer-risky row to the memory device110together with a refresh command. The memory device110may refresh the one or more memory cell rows physically adjacent to the row-hammer-risky row, according to a normal refresh command.

According to an example embodiment, the row hammer control circuit210may be configured to target refresh a row of memory cells physically adjacent to a row-hammer-risky row. The row hammer control circuit210collectively refers to those implemented in hardware, firmware, software, or a combination thereof for controlling or managing the row hammer. In the following embodiment, it will be described that the row hammer control circuit210controls the row hammer accessed above a threshold during the row hammer monitoring time frame, but embodiments of the disclosure are not limited thereto. For example, it may be described that the row hammer control circuit210corresponds to a configuration provided in the control logic circuit220, and the control logic circuit220controls the row hammer.

The control logic circuit220may control the refresh control circuit240to perform a normal refresh operation by increasing the refresh counter value by +1, based on the refresh command CMD. Also, the control logic circuit220may control the refresh control circuit240to perform a target row refresh operation, based on the row hammer addresses RH_ADDR. The refresh control circuit240may generate a refresh address REF_ADDR corresponding to a memory cell row on which a normal refresh operation or a target row refresh operation is to be performed. Moreover, the refresh control circuit240may generate a refresh address REF_ADDR corresponding to a memory cell row on which a normal refresh operation and a target row refresh operation are to be performed.

FIG.4is a diagram conceptually illustrating an example in which a memory cell array of a row hammer counter chip is configured according to an example embodiment of the disclosure.FIG.4shows a first bank BANK 1 as an exemplified part of the memory cell array200(seeFIG.2) in the row hammer counter chip131ofFIG.1. Descriptions related to the first bank BANK 1 may be equally applied to the second to fourth banks BANK2 to BANK 4.

Referring toFIGS.1,2, and4, in the row hammer counter chip131of the memory module10, the first bank BANK 1 may include a plurality of word lines WL1 to WLm and bit lines BL1 to BLn, like the data chips110to117. The plurality of memory cells MC may be positioned at intersections of the word lines WL1 to WLm and the bit lines BL1 to BLn. In the row hammer counter chip131, the memory cells MC connected to the respective word lines WL1 to WLm may be divided into first memory cells410and second memory cells420.

The first memory cells410connected to each of the word lines WL1 to WLm may include preset counter memory cells C110to C117storing the number of times of access of the corresponding word lines WL1 to WLm of the data chips110to117. For example, the counter memory cells C110to C117connected to the first word line WL1 may store the number of times of access for activating the memory cell row of the first word line WL1 of each of the data chips110to117. The first counter memory cells C110may store the number of times of access of the first word line WL1 of the first data chip110, the second counter memory cells C111may store the number of times of access of the first word line WL1 of the second data chip111, and similarly, the seventh counter memory cells C117may store the number of times of access of the first word line WL1 of the seventh data chip117.

The first to seventh counter memory cells C110to C117may also be repeated in each of the second bank BANK 2, the third bank BANK 3 and the fourth bank BANK 4 of the memory cell array200. The number and positions of the first to seventh counter memory cells C110to C117may be reconfigured according to a greatest number of times of access expected by the memory controller20. Depending on the embodiment, there may be between 8 and 24 counter memory cells along each word line. For example, the counter memory cells may include 8, 12, 16, or 24 counter memory cells. In other examples, more or fewer counter memory cells may be used.

The second memory cells420may store metadata supposed to be stored together with data stored in the data chips110to117. Metadata may include data-related validity, identification parameters, compression information, file properties, security or access control information, and the like. Additionally, the metadata may include vendor metadata related to an information of the memory module10. For example, in the case of security metadata, it is possible to check whether an operation related to data access is permissible or correct.

The second memory cells420may include preset metadata cells M118for storing metadata related to data stored in the data chips110to117. The number and location of the metadata cells M118may be reconfigured according to metadata provided by the memory controller20. Depending on the embodiment, there may be between 3 and 32 metadata cells along each word line. For example, the number of metadata cells may be 3, 8, 16, or 32. In other examples, more or fewer metadata cells may be used.

The second memory cells420may be used to support chipkill mechanisms for erasing or disabling the nonfunctional data chips among the data chips110to117. Additionally or alternatively, the chipkill mechanism may be supported in an error correction code chip (e.g., an ECC chip141ofFIG.5) instead of the row hammer counter chip131.

When the memory controller20recognizes the occurrence of an error in the memory module10, the memory controller20may attempt to determine an error pattern. Depending on the error pattern, the memory controller20may determine whether the error corresponds to a random error (non-permanent error), a permanent error, or a chipkill error. According to the determination of the type of error, the memory controller20may perform error correction. Among the different kinds of errors, one kind of error may be referred to as a chipkill error. A chipkill error generally corresponds to a permanent failure of one chip/die or chip that exceeds a threshold of bit errors.

Failure of one data chip of the memory channel12may cause a large number of errors with the data chip providing incorrect data in a large number of bursts during memory processing. Accordingly, when all detected errors correspond to one data chip, the memory controller20may support a chipkill error for displaying one data chip as an erased chip.

The memory controller20may store the chipkill error data in the chipkill error data cell K119of the second memory cells420. Nonfunctional data chips may be deactivated by the chip-kill error data stored in the chip-kill error data cell K119. The number and location of the chip-kill error data cells K119may be reconfigured according to the chip-kill error data provided by the memory controller20.

As described above, the row hammer counter chip131may provide an increased RAS function because it provides the row hammer coverage, metadata and/or chipkill coverage.

FIG.5is a diagram illustrating a memory system including a row hammer counter chip according to example embodiments of the disclosure.FIG.6is a diagram for explaining a data architecture of each of the memory chips110to117,120to127,131,132,141,142,151, and152ofFIG.5.FIG.7is a block diagram illustrating an error detection code generator22and an error correction code generator23of the memory controller20ofFIG.5.

Referring toFIG.5, a memory system4may include a memory module100and a memory controller20. The memory module100shows one memory rank implemented as a double data rate synchronous dynamic random-access memory dual in-line memory module (DDR DIMM). The memory controller20may transmit data to the various memory chips110to117,120to127,131,132,141,142,151, and152of the memory module100, and receive data from various memory chips110to117,120to127,131,132,141,142,151, and152.

Illustratively, as shown inFIG.6, each of the memory chips110to117,120to127,131,132,141,142,151, and152may include four pins DQ0 to DQ3 connected to the I/O circuit250, use 16 bursts per memory transaction (burst length BL=16), and provide 4 bits of information through 4 pins DQ0 to DQ3. Accordingly, a 64-bit data set DQ_BL per memory processing may be input/output to/from each of the memory chips110to117,120to127,131,132,141,142,151, and152.

The memory module100ofFIG.5may include two memory channels310and320for each memory rank. Each of the memory channels310and320may include 8 data chips dedicated to storing data, one row hammer counter chip (hereinafter, referred to as RH chip), one error correction code chip (hereinafter, referred to as ECC chip), and one error detection code chip (hereinafter, referred to as CRC chip). The error detection code may include a cyclic redundancy check. For convenience of description, an error correction code may be used interchangeably with an ECC code, and an error detection code may be used interchangeably with a CRC code. The first memory channel310may include eight data chips110to117, one RH chip131, one CRC chip141, and one ECC chip151. The second memory channel320may include eight data chips120to127, one RH chip132, one CRC chip142, and one ECC chip152.

Since each of the memory channels310and320includes eight 4-bit data chips110to117, and120to127dedicated to storing data, the data width for each of the memory channels310and320is 32 bits. In addition, because of using 16 bursts per memory process (burst length BL=16), 512 bits per each of the memory channels310and320for each memory process are transmitted. The 512 bits per each of the memory channels310and320may be referred to as a user data set.

The memory channels310and320include the RH chips131and132, respectively. The RH chips131and132of the memory channels310and320may respectively store the numbers of times accessing the word lines of the data chips110to117and120to127.

The RH chips131and132of the memory channels310and320may respectively store the numbers of times accessing the word lines of the data chips110to117and120to127. The first RH chip131of the first memory channel310may store metadata related to the number of times of access of the word lines corresponding to each of the data chips110to117and/or data stored in each of the data chips110to117. The second RH chip132of the second memory channel320may store metadata related to the number of times of access of the corresponding word lines of each of the data chips120to127and/or data stored in each of the data chips120to127.

Additionally, the respective RH chips131and132of the memory channels310and320may store chipkill error data for disabling nonfunctional data chip(s) in each of the memory channels310and320. The first RH chip131of the first memory channel310may store chipkill error data for inactivating nonfunctional data chip(s) among the data chips110to117. The second RH chip132of the second memory channel320may store chipkill error data for inactivating nonfunctional data chip(s) among the data chips120to127.

The memory channels310and320include CRC chips141and142, respectively. The CRC chips141and142respectively of the memory channels310and320may store CRC data associated with 64 bits of a data set DQ_BL corresponding to a burst length BL=16 of each of the data chips110to117and120to127. The first CRC chip141of the first memory channel310may store error detection code CRC bits generated based on 64 bits of the data set DQ_BL of each of the data chips110to117. The second CRC chip142of the second memory channel320may store error detection code CRC bits generated based on 64 bits of the data set DQ_BL of each of the data chips120to127.

The ECC width for each of the memory channels310and320is 4 bits because one of the ECC chips141and142is included. 36 bits per each of the memory channels310and320are sent for each burst, which corresponds to a total of 576 bits per memory processing of each of the memory channels310and320. It will be understood that the user data set is 512 bits and the remaining 64 bits correspond to the ECC data of the respective ECC chips141and142of the memory channels310and320.

The memory controller20may include a row hammer counter21, a CRC generator22, and a parity generator23. The row hammer counter21may count the number of active accesses of the word lines of each of the data chips110to117and120to127of the memory module100during the row hammer monitor time frame. The row hammer counter21may store the number of times of access of the word lines of each of the data chips110to117in the counter memory cells C110to C117(seeFIG.4) connected to corresponding word lines of the first RH chip131of the first memory channel310. Likewise, the row hammer counter21may store the number of times of access of the word lines of each of the data chips120to127in the counter memory cells connected to the corresponding word lines of the second RH chip132of the second memory channel320.

InFIG.7, the CRC generator22may generate an 8-bit error detection code CRC based on the 64-bit data set DQ_BL corresponding to the burst length BL=16 to be provided to each of the data chips110to117and120to127of each of the memory channels310and320. Accordingly, the CRC generator22may generate a 64-bit CRC bit for each of the memory channels310and320. The CRC generator22may store the 64-bit CRC bits generated based on the data sets DQ_BL of the eight data chips110to117in the first CRC chip141of the first memory channel310. The CRC generator22may store the 64-bit CRC bit generated based on the data set DQ_BL of each of the eight data chips120to127in the second CRC chip142of the second memory channel320.

The parity generator23may generate a 64-bit error correction code ECC based on the user data set DQ_SET corresponding to all of the 64-bit data sets DQ_BL corresponding to the burst length BL=16 to be provided to the data chips110to117and120to127of each of the memory channels310and320. The user data set DQ_SET is 512 bits, and the parity generator23may be configured as an ECC encoder.

The 64-bit ECC bits for the 512-bit user data set DQ_SET of the first memory channel310may be provided to the first memory channel310together with the user data set DQ_SET. 512 bits of the user data set DQ_SET of the first memory channel310may be stored in the data chips110to117, and ECC bits of 64 bits may be stored in the first ECC chip151. After this, the memory controller20is to transmit a particular command to the memory module100, and is to receive information in the ECC bits stored in the first ECC chip151during memory processing with the first memory channel310. When the memory controller20detects an error in the data of the data chips110to117, the memory controller20may correct a 1-bit error in the 512-bit data of the first memory channel310by using the 64-bit ECC bit.

Similarly, the 64-bit ECC bits for the 512-bit user data set DQ_SET of the second memory channel320may be provided to the second memory channel320together with the user data set DQ_SET. 512 bits of the user data set DQ_SET of the second memory channel320may be stored in the second data chips120to127, and ECC bits of 64 bits may be stored in the second ECC chip152. A 1-bit error within 512 bits of the second memory channel320may be corrected by using the 64-bit ECC bit.

Accordingly, since the memory module100may correct a 1-bit error per each of the memory channels310and320using the ECC chips141and142, a 2-bit error may be corrected.

Returning toFIG.5, the memory module100may further include a serial presence detect chip (hereinafter SPD chip)160, a power management integrated circuit chip (hereinafter, referred to as PMIC chip),170and a Registering Clock Driver chip (hereinafter, referred to as RCD chip)180. The SPD chip160may store extended RAS information related to row hammer coverage, metadata, and/or chipkill coverage for the row hammer counter chips131and132per the respective memory channels310and320. Also, the SPD chip160may include device information of the memory module100. For example, the SPD chip160may include initial information or device information such as a module type, module configuration, storage capacity, module type, implement environment, and the like of the memory module100.

When the memory system4is booted, the memory controller20may read device information from the SPD chip160of the memory module100and recognize the memory module100based on the read device information. The memory controller20may control the memory module100based on device information and extended RAS information from the SPD chip160. For example, the memory controller20may identify the memory channel(s) and memory chips included in the memory module100according to device information from the SPD chip160, and may control the row hammer counter chip of each memory channel according to the extended RAS information.

The PMIC chip170may generate a power supply voltage based on an input voltage and provide the generated power supply voltage to the memory chips110to117,210to217,131,132141,142,151and152. The memory chips110to117,210to217,131,132,141,142,151, and152may operate based on a power supply voltage.

The RCD chip180may control the memory chips110to117,210to217,131,132,141,142,151,152, the SPD chip160, and the PMIC chip170under the control of the memory controller20. For example, the RCD chip180may receive a command, an address, a clock signal and a control signal from the memory controller20through the memory bus30, and may perform a buffer function for distributing the received signals to the first memory channel310and the second memory channel320. The memory chips110to117,210to217,131,132,141,142,151, and152of each of the memory channels310and320perform data exchange with the memory controller20based on a command, address, clock signal and control signal provided from the RCD chip180.

As mentioned above, when performing the DDR5 mechanism divided into 8 data chips110to117and210to217for an x4 implementation for each of the memory channels310and320, since the memory module100provides row hammer coverage, metadata, and/or chipkill coverage using the row hammer counter chips131and132, it is possible to provide an increased RAS function.

FIG.8is a diagram illustrating a memory system including a row hammer counter chip according to example embodiments of the disclosure.FIG.9is a view for explaining a data architecture of each of the memory chips810to813,820to823,831,832,841and842ofFIG.8. Hereinafter, subscripts (e.g., a in100a) attached to the same reference numbers in different drawings are used to distinguish a plurality of circuits having similar or identical functions.

Referring toFIG.8, the memory system6may include a memory module100aand a memory controller20. Compared with the memory module100ofFIG.5, the memory module100aofFIG.8shows that the number of memory chips810to813,820to823,831,832,841, and842of each of the memory channels310and320is different, and the remaining components are the same. Hereinafter, differences fromFIG.5will be mainly described.

In the memory module100a, as shown inFIG.9, the memory chips810to813,820to823,831,832,841,842of each of the memory channels310and320may include eight pins DQ0-DQ7 connected to the I/O circuit250, use 16 bursts per memory transaction (burst length BL=16), and provide 8 bits of information via 8 pins DQ0 to DQ7. Accordingly, a 128-bit data set DQ_BL per memory processing may be input/output to/from each of the memory chips810to813,820to823,831,832,841, and842.

In the memory module100aofFIG.8, each of the memory channels310and320may include four data chips, one row hammer counter chip, and one error correction/detection code chip. The first memory channel310may include four data chips810to813, one row hammer counter chip831, and one error correction/detection code chip841. The second memory channel320may include four data chips820to823, one row hammer counter chip832, and one error correction/detection code chip842.

Since each of the memory channels310and320includes four 8-bit data chips810to813and820to823dedicated to storing data, the data width for each of the memory channels310and320is 32 bits. In addition, because of using 16 bursts per memory process (burst length BL=16), 512 bits per each of the memory channels310and320for each memory process are transmitted.

The CRC generator22may generate a 16-bit error detection code CRC based on the 128-bit data set DQ_BLa corresponding to the burst length BL=16 to be provided to each of the data chips810to813and820to823of each of the memory channels310and320. Accordingly, the CRC generator22may generate a 64-bit CRC bit for the four data chips810to813and820to823for each of the memory channels310and320.

The parity generator23may generate a 64-bit error correction code ECC based on 512 bits of the user data set DQ_SET corresponding to all of the 128-bit data sets DQ_BLa corresponding to the burst length BL=16 to be provided to the data chips810to813and820to823of each of the memory channels310and320.

The memory channels310and320include row hammer counter chips831and832, respectively. The respective row hammer counter chips831and832of the memory channels310and320may store the number of times of access of the word lines corresponding to each of the data chips810to813and820to823. Additionally, the respective row hammer counter chips831and832of the memory channel310and320may store metadata related to data stored in each of the data chips810to813and820to823and/or chipkill error data for disabling nonfunctional data chip(s) in each of the memory channels310and320.

The memory channel310and320include error correction/detection code chips841and842, respectively. The respective error correction/detection code chips841and842of the memory channels310and320store 64-bit CRC bits for the data chips810to813and820to823generated by the CRC generator22. The respective error correction/detection code chips841and842of the memory channels310and320may store 64-bit ECC bits for the data chips810to813and820to823generated by the parity generator23.

As mentioned above, when performing the DDR5 mechanism divided into 4 data chips810to813and820to823for ×8 implementation for each of the memory channels310and320, since the memory module100aprovides row hammer coverage, metadata, and/or chipkill coverage using the row hammer counter chips831and832, it is possible to provide an increased RAS function.

FIG.10is a flow diagram illustrating an operation of a memory system including a row hammer counter chip according to embodiments of the disclosure.

Referring toFIG.10in conjunction withFIGS.1to4, the memory system1may perform initialization in operation S1010. When the memory system1is powered up, the memory controller20and the memory module10may perform an initial setting operation according to a preset method. Default operation parameters may be set in initialization of the memory module10. In the initialization of the memory system1, a supplier or a user of the memory system1may set a row hammer monitor time frame tREFi or tREFw, and may set a threshold as a criterion for determining a row hammer.

In operation S1010, the memory controller20may reset the number of accesses to each word line WL1 to WLm of the data chips110to117to “0”. The memory controller20may store the number of times of access of each word line WL1 to WLm of the data chips110to117as “0” in the counter memory cells C110to C117of the row hammer counter chip131.

In operation S1020, the memory controller20may monitor a row hammer for a memory cell row of the word lines WL1 to WLm of the data chips110to117. The memory controller20may perform a write operation or a read operation performed on the data chips110to117for each memory process for data exchange with the memory module10according to a memory request from the host. At this time, as the memory controller20instructs the data chips110to117to input and output the data set DQ_BL, one of the word lines WL1 to WLm of all the data chips110to117is may be accessed. During the access operation, a voltage may be applied to the accessed word lines WL1 to WLm, and write data may be written into or read data from the memory cells connected to the accessed word lines WL1 to WLm.

In operation51030the memory controller20may count a number of times each of the word lines WL1 to WLm of all the data chips110to117are accessed. The memory controller20may calculate the access counts of the word lines WL1 to WLm accessed of all the data chips110to117by using the row hammer counter21.

In operation S1040, the memory controller20may update the number of times of access of the accessed word lines WL1 to WLm of all data chips110to117for each memory processing to the access count value calculated in operation S1030.

In operation S1050, the memory controller20may store the access count values of the accessed word lines WL1 to WLm of each of the data chips110to117in the counter memory cells C110to C117connected to the accessed word lines WL1 to WLm of the row hammer counter chip131. As the access count values of all the word lines WL1 to WLm of each of the data chips110to117are stored in the counter memory cells C110to C117connected to the corresponding word lines WL1 to WLm of the row hammer counter chip131, the memory controller20may perform a PRHT function. In each of the data chips110to117, when the number of times of access of the word lines WL1 to WLm stored in the row hammer counter chip131is equal to or greater than the threshold, a memory cell row physically adjacent to the memory cell row associated with the accessed word line WL1 to WLm may be target-refreshed.

In operation S1060, the memory controller20may determine whether the row hammer monitor time frame tREFi or tREFw has elapsed. If the row hammer monitor time frame has not elapsed (NO), the operation flow proceeds to operation S1020, the memory controller20may repeatedly monitor access to memory cell rows of the word lines WL1 to WLm of the data chips110to117. When the row hammer monitor time frame elapses (YES), the operation flow proceeds to operation S1010, the memory controller20may reset the number of accesses to each word line WL1 to WLm of the data chips110to117to “0”.

The above-described operation flow may be implemented in any of the memory systems described with reference toFIGS.5to9. AlthoughFIG.10illustrates an example embodiment, in which, row hammer coverage is provided in relation to the PRHT function of the row hammer counter chip131, by storing metadata and/or chip-kill error data in the row hammer counter chip131, the RAS function may be increased. In addition, the memory system may generate an error detection code based on the data set to be provided to each of the plurality of data chips for each memory processing per memory channel, generate an error correction code based on the user data set corresponding to the entire data set, and provide a basic RAS function by storing the error detection/correction code in the error detection/correction code chip.

FIG.11is a block diagram illustrating a system1000including a memory module for controlling a row hammer according to embodiments of the disclosure.

Referring toFIG.11, the system1000may include a camera1100, a display1200, an audio processor1300, a modem1400, DRAMs1500aand1500b, flash memories1600aand1600b, I/O devices1700aand1700b, and an application processor (AP)1800. The system1000may be implemented as a laptop computer, a mobile phone, a smartphone, a tablet personal computer, a wearable device, a healthcare device, or an Internet of Things (IoT) device. In addition, the system1000may be implemented as a server or a personal computer.

The camera1100may take a still image or a moving picture according to a user's control, and may store the captured image/video data or transmit the stored captured image/video data to the display1200. The audio processor1300may process audio data included in content of the flash memory devices1600aand1600bor a network. The modem1400modulates and transmits a signal to transmit/receive wired/wireless data, and may demodulate the modulated signal to restore the original signal at the receiving end. The I/O devices1700aand1700bmay include devices that provide digital input and/or output functionality such as a Universal Serial Bus (USB) or storage, a digital camera, a Secure Digital (SD) card, a Digital Versatile Disc (DVD), a network adapter, a touch screen, and the like.

The AP1800may control the overall operation of the system1000. The AP1800may control the display1200so that a part of the content stored in the flash memory devices1600aand1600bis displayed on the display1200. When a user input is received through the I/O devices1700aand1700b, the AP1800may perform a control operation corresponding to the user input. The AP1800may include an accelerator block, which is a dedicated circuit for artificial intelligence (AI) data operation, or may include an accelerator chip1820separately from the AP1800. DRAM1500bmay be additionally mounted to the accelerator block or accelerator chip1820. The accelerator is a function block that professionally performs a particular function of the AP1800, and may include a GPU that is a function block that specializes in processing graphic data, a Neural Processing Unit (NPU) that is a block for professionally performing AI calculations and inference, and a Data Processing Unit (DPU) that is a block for specializing in data transfer.

The system1000may include the plurality of DRAMs1500aand1500b. The AP1800may control the DRAMs1500aand1500bthrough the command and mode register (MRS) setting that meets the Joint Electron Device Engineering Council (JEDEC) standard, and communicate by setting the DRAM interface protocol to use company-particular functions such as low voltage/high speed/reliability and Cyclic Redundancy Check (CRC)/Error Correction Code (ECC) functions. For example, the AP1800may communicate with the DRAM1500athrough an interface conforming to JEDEC standards, such as LPDDR4 and LPDDR5, and the accelerator block or accelerator chip1820may communicate by setting a new DRAM interface protocol to control the accelerator DRAM1500bhaving a higher bandwidth than the DRAM1500a.

Although only the DRAMs1500aand1500bare illustrated inFIG.11, the disclosure is not limited thereto, and if the AP1800or accelerator chip1820bandwidth, reaction speed, and voltage conditions are satisfied, any memory, such as PRAM, SRAM, MRAM, RRAM, FRAM, or Hybrid RAM, may be used. The DRAMs1500aand1500bhave relatively smaller latency and bandwidth than the I/O devices1700aand1700bor the flash memories1600aand1600b. The DRAMs1500aand1500bmay be initialized at the power-on time point of system1000, and may be used as a temporary storage location for the operating system and application data loaded with the operating system and application data, or may be used as an execution space for various software codes.

In the DRAMs1500aand1500b, addition/subtraction/multiplication/division operations, vector operations, address operations, or Fast Fourier Transform (FFT) operations may be performed. In addition, a function used for inference may be performed in the DRAMs1500aand1500b. Here, the inference may be performed in a deep learning algorithm using an artificial neural network. The deep learning algorithm may include a training operation of learning a model through various data and an inference operation of recognizing data with the learned model. As an example embodiment, the image captured by the user through the camera1100is signal-processed and stored in the DRAM1500b, and the accelerator block or accelerator chip1820may perform AI data operation for recognizing data using data stored in the DRAM1500band a function used for inference.

The system1000may include a plurality of storage or a plurality of flash memories1600aand1600bhaving a larger capacity than the DRAMs1500aand1500b. The accelerator block or accelerator chip1820may perform a training operation and AI data operation by using the flash memory devices1600aand1600b. In an example embodiment, the flash memories1600aand1600bmay more efficiently perform a training operation and an inference AI data operation performed by the AP1800and/or the accelerator chip1820using the arithmetic device provided in the memory controller1610. The flash memories1600aand1600bmay store pictures taken through the camera1100or data transmitted through a data network. For example, augmented reality/virtual reality, High Definition (HD), or Ultra High Definition (UHD) content may be stored.

In the system1000, the DRAMs1500aand1500bmay employ a memory module including a plurality of data chips and a row hammer counter chip described with reference toFIGS.1to10. The DRAMs1500aand1500bmay store an access count value of an accessed word line of each data chip in counter memory cells connected to an accessed word line of the row hammer counter chip during a row hammer monitor time frame. In addition, the row hammer counter chip may store metadata related to data stored in each of the plurality of data chips and/or chipkill error data for inactivating a nonfunctional data chip among the plurality of data chips. In each of the data chips, when the number of accesses to the word line stored in the row hammer counter chip exceeds the threshold, the information on the accessed word line is provided to the memory controller that controls the refresh operation of the DRAMs1500aand1500b, or a memory cell row physically adjacent to the memory cell row associated with the accessed word line may be target-refreshed. In addition, the DRAMs1500aand1500bmay generate an error detection code based on a data set to be provided to each of a plurality of data chips for each memory processing per memory channel, generate an error correction code based on the user data set corresponding to the entire data set, and store the error detection/correction code in the error detection/correction code chip. Accordingly, the DRAMs1500aand1500bmay provide an increased RAS function by providing row hammer coverage, metadata, and/or chipkill coverage in addition to the RAS function providing an error detection code and an error correction code.