Communication control device having multiprocessor

A communication control device comprising a plurality of network processors for performing high-speed communication among these network processors. The communication device connects a plurality of processor interfaces to each other using an internal communication path. Each processor interface is connected to one or a plurality of the network processors. The processor interface comprises a selector for each connected network processor. In one preferred embodiment of this invention, transmission rights are granted to a selector which received a token cell. The selector outputs communication cells received from a network processor onto the internal communication path only when the selector possesses the transmission rights. Having outputted all of the communication cells, the selector outputs the token cell onto the internal communication path. When the token cell is outputted, the selector loses the transmission rights.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a communication control device for performing parallel processing using a plurality of processors. The present invention is applied to a router, load balancer, and so on for a communication network.

2. Description of Related Art

Routers and load balancers execute relay processing of communication data (packets and the like) inputted from an external communication path.

A router is a device for performing relay processing at the network layer of the Open Systems Interconnection (OSI) Reference Model. A plurality of communication paths is connected to the router. The router receives IP (Internet Protocol) packets from each communication path. The router then determines the communication path to which the IP packet is to be outputted in accordance with a destination IP address noted in a header part of the IP packet. A routing table stored in the router in advance is referenced to determine the communication path.

A load balancer is a device for performing relay processing at the transport layer or above of the OSI Reference Model. The load balancer connects a communication network to a plurality of Web servers. More specifically, this type of load balancer distributes HTTP requests received from a client among the plurality of Web servers. A URL conversion table or the like which is stored in the load balancer in advance is referenced to perform this distribution. By using a load balancer, an HTTP request pertaining to a single URL can be divided among the plurality of Web servers. In so doing, increases in the load on each individual Web server are suppressed, and thus the response performance of the Web servers is improved.

Many routers and load balancers comprise a plurality of processors. By means of parallel processing using a plurality of processors, IP packets can be controlled at high speed and with a high degree of reliability.

In a control device for causing a plurality of processors to operate in parallel, it is desirable that inter-processor communication be performed at sufficiently high speed. This is due to the fact that when communication speed is low, processing time increases.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a communication control device with a high inter-processor communication speed and at a low cost.

In order to achieve this object, a communication control device according to the present invention comprises: an internal communication path connecting a plurality of processor interfaces to each other; a plurality of processors, one or a plurality of which is connected to each of the processor interfaces; a cell distributor provided within the processor interface and connected to each of the processors for transferring a communication cell received from the internal communication path to a connected processor when the destination of the communication cell is the connected processor; and a selector provided within the processor interface and connected to each of the processors for outputting a communication cell received from a connected processor onto the internal communication path only when said selector possesses transmission rights.

The communication control device of the present invention comprises an internal communication path, and therefore high-speed communication can be performed. Moreover, only a selector which holds transmission rights outputs communication cells onto the internal communication path, and thus the reliability of data stored in the communication cells is not damaged.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Embodiments of the present invention will now be described using the drawings. In the drawings, the magnitude, form, and positional relationships of each constitutional component are merely illustrated schematically in order to facilitate understanding of the present invention. Further, the numerical conditions described below are simply examples thereof.

First Embodiment

FIG. 1is a block diagram showing the overall constitution of a communication control device according to this embodiment.

As shown inFIG. 1, a communication control device100according to this embodiment comprises network processors111,112,113,114, processor interfaces121,122, a connection switch131, termination circuits141,142, control buses CB1to CB5, and internal buses IB1to IB9.

The network processors111to114perform predetermined parallel processing. The internal constitution of the network processors111to114may be identical or not identical. In this embodiment, an example will be described in which all of the network processors111to114have the same internal constitution. The internal constitution of the network processors111to114will be described below usingFIG. 2. As shown inFIG. 1, the network processors111to114are connected to each other via the control buses CB1to CB5.

The processor interfaces121,122serve as interfaces for enabling communication among the network processors111to114and between the network processors111to114and the connection switch131. As shown inFIG. 1, the processor interface121is connected to the internal buses IB1, IB2, IB5, IB9, and the processor interface122is connected to the internal buses IB3, IB4, IB6, IB9. The internal constitution of the processor interfaces121,122may be identical or not identical. In this embodiment, an example will be described in which the processor interfaces121,122have the same constitution. The internal constitution of the processor interfaces121,122will be described below usingFIG. 3.

The connection switch131connects the processor interfaces121,122to the termination circuits141,142. More specifically, the connection switch131connects the internal bus IB5to either of the internal buses IB7, IB8and connects the internal bus IB6to either of the internal buses IB7, IB8. Connections made by the connection switch131can be switched at any time.

The termination circuits141,142receive IP packets from communication paths P1, P2and transmit the IP packets to the internal buses IB7, IB8. The termination circuits141,142also receive IP packets from the internal buses IB7, IB8and transmit the IP packets to the communication paths P1, P2. Discrepancies at the data-link layer or below in the IP packets received from the communication paths P1, P2are absorbed by the termination circuits141,142.

The control buses CB1to CB5are mainly used in the initialization of the communication control device100. Hence it is sufficient to use narrowband buses, or in other words buses with a low communication speed, as the control buses CB1to CB5. For example, PCI (Protocol Control Information) buses may be used as the control buses CB1to CB5.

The internal buses IB1to IB9are used in the communication of data to be processed, the communication of control information (an HTTP request or the like) for parallel processing, and so on. Hence the traffic on the internal buses IB1to IB9is extremely heavy. Therefore, broadband buses are used as the internal buses IB1to IB9.

FIG. 2is a block diagram showing the internal constitution of the network processor111. As noted above, the internal constitution of the network processors112to114is identical to the internal constitution of the network processor111.

As shown inFIG. 2, the network processor111comprises a processor unit210, a coprocessor unit220, a control bus interface230, an internal bus interface240, and a memory interface250.

The processor unit210comprises one or a plurality of processing circuits. In the example inFIG. 2, the processor unit210comprises four processing circuits211to214. The processor unit210is connected to the coprocessor unit220via a bus PB0within the network processor111. The processor unit210and coprocessor unit220communicate using the bus PB0. The processor unit210cannot communicate directly with the high-speed bus IB1. The processing circuits211to214communicate with the bus IB1via the coprocessor unit220. It is generally difficult to broaden the band of the bus PB0within the network processor111. Hence the processor unit210mainly performs processing in which high-speed communication is unlikely to be needed. In this embodiment, the processor unit210executes a processing program stored within the processor unit210. When the processor unit210executes the program, a signal which is communicated between the units210,220via the bus PB0is a control signal, and therefore high-speed communication is not required. This processing is executed in parallel by the four processing circuits211to214. The processing circuits211to214are capable of communicating with each other.

The coprocessor unit220comprises one or a plurality of coprocessing circuits. In the example inFIG. 2, the coprocessor unit220comprises four coprocessing circuits221to224. The coprocessor unit220is capable of direct communication with the high-speed bus IB1via the internal bus interface240. Hence the coprocessor unit220mainly performs processing in which high-speed communication is likely to be needed. In this embodiment, the coprocessor unit220mainly performs communication data processing. Communication data processing is executed on the basis of the program processing executed by the processor unit210. Communication data processing is executed in parallel by the four coprocessing circuits221to224. The coprocessing circuits221to224are capable of communicating with each other.

The control bus interface230is an interface for making a communication connection between the processor unit210and the control bus CB2.

The internal bus interface240is an interface for making a communication connection between the coprocessor unit220and the internal bus IB1.

The memory interface250is an interface for making a communication connection between the processor unit210and a memory device260. The memory device260is shared memory connected to all of the network processors111to114. The processor unit210uses the memory device260when the internal memory capacity is insufficient and so on. The memory device260may also be used during control signal communication among the network processors111to114. The processor unit in one of the network processors writes control information to the memory device260, the processor unit in another network processor reads the control information from the memory device260, and thus control information communication is performed. The system of performing control information communication via the shared memory260is known as a tightly-coupled system. Conversely, a system of performing control information communication via a bus, interface, or the like is known as a loosely-coupled system. The communication control device100according to this embodiment is capable of implementing both a tightly-coupled system and a loosely-coupled system.

FIG. 3is a block diagram showing the internal constitution of the processor interface121. As noted above, the internal constitution of the processor interface122is identical to the internal constitution of the processor interface121.

As shown inFIG. 3, the processor interface121comprises bus interfaces311,312, buffer units320,330,340,350, cell distributors361,362, and format converters371,372.

The bus interface311is an interface for making a communication connection between the internal bus IB1and the buffer units320,330. The bus interface312is an interface for making a communication connection between the internal bus IB2and the buffer units340,350.

The buffer unit320temporarily stores cells received from the cell distributor361. The buffer unit320comprises a writer321, a buffer322, and a reader323. The writer321stores cells received from the cell distributor361in the buffer322. The reader323reads the cells stored in the buffer322appropriately and outputs the cells to the bus interface311.

The buffer unit330temporarily stores cells received from the bus interface311. The buffer unit330comprises a writer331, a buffer332, a reader333, and a selector334. The writer331stores cells received from the bus interface311in the buffer332. The reader333reads the cells stored in the buffer332appropriately and outputs the cells to the selector334. The selector334receives cells from the reader333and the cell distributor361and outputs the cells to the cell distributor362(described below).

The buffer unit340temporarily stores cells received from the cell distributor362. The buffer unit340comprises a writer341, a buffer342, and a reader343. The writer341stores cells received from the cell distributor362in the buffer342. The reader343reads the cells stored in the buffer342appropriately and outputs the cells to the bus interface312.

The buffer unit350temporarily stores cells received from the bus interface312. The buffer unit350comprises a writer351, a buffer352, a reader353, and a selector354. The writer351stores cells received from the bus interface312in the buffer352. The reader353reads the cells stored in the buffer352appropriately and outputs the cells to the selector354. The selector354receives cells from the reader353and the cell distributor362, and outputs the cells to the format converter372(described below).

The cell distributor361receives cells from the format converter371. As will be described below, two types of cells, a user cell and a token cell, are used in this embodiment. The cell distributor361determines whether a received cell is a user cell or a token cell from the header information of the cell, and when the received cell is a user cell, also determines the destination thereof. The cell distributor361then transmits the cell to the writer321or selector334in accordance with the results of these determinations.

The cell distributor362receives cells from the selector334. The cell distributor362determines whether the received cell is a user cell or token cell from the header information of the cell, and if the received cell is a user cell, determines the destination thereof. The cell distributor362then transmits the cell to the writer341or selector354in accordance with the results of these determinations.

The format converter371receives cells from the internal bus IB5and IB9a. Here, the internal bus IB9ais a part of the internal bus IB9which performs cell transfer from the processor interface122to the processor interface121. When necessary, the format converter371converts the format of the received cell. The converted cell is then transmitted to the cell distributor361or internal bus IB5.

The format converter372receives cells from the selector354. When necessary, the format converter372converts the preliminary format of the received cell. The format converter372then transmits the cell to an internal bus IB9b. Here, the internal bus IB9bis a part of the internal bus IB9which performs cell transfer from the processor interface121to the processor interface122. The internal bus IB9btransfers cells to the processor interface122. When necessary, the processor interface122converts the format of the cells received from the internal bus IB9b.

Note that if format conversion is not required, the format converters371,372do not have to be provided.

FIGS. 4A and 4Bare schematic diagrams showing an example of the cell format used in the processor interface121.

As shown inFIG. 4A, the cell comprises a header field HD and a user data field UD.

The header HD comprises a token cell field TKN, a reserve field RSV, a bit enable field BE, a destination field DST, and a loop inhibition field SRC.

The token cell field TKN stores the token cell/user cell classification. For example, “1” is stored in the token cell field TKN of a token cell and “0” is stored in the token cell field TKN of a user cell (seeFIG. 4B). The difference between a token cell and a user cell will be described below.

The reserve field RSV is a field enabling a user to store arbitrary data.

The bit enable field BE stores the data length of the user data field UD. In other words, the bit enable field BE stores data indicating the boundary between a region in which data are actually stored and a region in which data are not stored. For example, when “0011”, that is “3” in the decimal system, is stored in the bit enable field BE (seeFIG. 4B), only the first 23bytes, that is eight bytes, of the user data field UD are valid data, and data from the ninth byte onward are meaning less data.

The destination field DST stores the destination address of the cell. A single address or a plurality of addresses can be stored in the destination field DST. If the destination field DST is set at four bits, then all combinations of the network processors111to114may be displayed. For example, the destination field can be defined such that when the least significant bit is “1”, the network processor111is included in the destination, when the second bit is “1”, the network processor112is included in the destination, when the third bit is “1”, the network processor113is included in the destination, and when the most significant bit is “1”, the network processor114is included in the destination. When the destination field DST is “0001”, for example, only the network processor111is included in the destination, when the destination field DST is “0010”, only the network processor112is included in the destination, and when the destination field is “0011”, the network processors111,112are included in the destination (seeFIG. 4B).

The loop inhibition field SRC stores the transmission source address of the cell. The transmission source address is defined in accordance with the destination field DST. For example, the address of the network processor111is defined as “0001”, the address of the network processor112is defined as “0010”, the address of the network processor113is defined as “0100” (seeFIG. 4B), and the address of the network processor114is defined as “1000”.

The user data field UD stores data to be processed by the network processors111to114and the like. The size of the user data field UD may be fixed or variable.

Next, an operation of the communication control device100according to this embodiment will be described.

As described above, the communication control device100of this embodiment performs communications of data to be processed and communications of control information for parallel processing, and so on, with using the internal buses IB1to IB9. Hence in this embodiment, an internal communication path having a ring-type topology is constituted by the cell distributors, format converters, and selectors inside the processor interfaces121,122. On a topology-type internal communication path, a collision occurs when control information cells is generated by different network processors and these cells become mixed. And this collision causes a signal breakdown. Hence in order to perform normal communication, a signal information cell generated by one of the network processors must not be inputted onto the internal communication path when a signal information cell generated by another network processor is being transported on the internal communication path. In order to achieve this, in the communication control device100of this embodiment, a token cell is used to set transmission rights in the selectors (see reference numerals334,354inFIG. 3).

The token cell is generated at the time of power source start-up, for example, and outputted onto the internal communication path. This embodiment will be described using as an example in which a token cell is generated by the selector334. Note, however, that the token cell may be generated anywhere. The token cell may also be generated in the selector354, the cell distributors361,362, or the format converters371,372.

Only one token cell exists on the internal communication path. This token cell circulates through the internal communication path. The token cell is generated in the selector334, transferred to the cell distributor362, selector354, and format converter372, and then transmitted to the processor interface122. The token cell then passes through a cell distributor, selector, and format converter within the processor interface122and is transferred to the format converter371. Having been received by the format converter371, the token cell is transferred to the cell distributor361and then transferred to the selector334.

The network processors111to114generate user cells according to necessity. A cell in which communication data are stored and a cell in which control data are stored are examples of a user cell. Of a sequence of processes relating to communication data, the first half of the processes may be executed by the network processor111and the second half by the network processor112, for example. In such a case, data to be processed and control data are transmitted from the network processor111via the processor interface121to the network processor112.

User cells generated by the network processor111are transmitted on the corresponding internal bus IB1to the bus interface311inside the processor interface121. The writer331writes the user cells into the buffer332. As will be described below, the user cells stored in the buffer332are not read until the selector334sends a read command to the reader333.

Likewise, user cells generated in the network processor112are stored in the buffer352. In addition, user cells generated in the network processors113,114are stored in buffers (not shown) inside the processor interface122.

The selector334receives a cell from the cell distributor361. The selector checks the classification (token cell or user cell) of the received cell. If the received cell is a user cell, the cell is transmitted to the cell distributor362without performing other processing. If the received cell is the token cell, the selector334obtains transmission rights. Once transmission rights have been obtained, the selector334transmits a user cell read command to the reader333. If user cells are stored in the buffer332, the reader333successively reads the user cells stored in the buffer332in accordance with the command. The selector334then successively transfers the user cells read by the reader333to the cell distributor362. When all of the user cells stored in the buffer332have been transferred to the cell distributor362, the selector334transmits the token cell to the cell distributor362. If no user cells are stored in the buffer332, the token cell is transferred to the cell distributor362without performing user cell reading. Once the token cell has been outputted from the selector334, the selector334loses transmission rights.

The cell distributor362checks the classification of the cell received from the selector334. If the received cell is the token cell, the received cell is transferred to the selector354without performing other processing. If the received cell is a user cell, the cell distributor362reads the destination address from the destination field DST of the user cell. If the network processor112is not included in the destination addresses, the cell distributor362does not copy the user cell. If the network processor112is included in the destination addresses, the cell distributor362transmits a copy of the user cell to the writer341. The writer341stores the received user cell in the buffer342. The user cell stored in the buffer342is read by the reader343at a later stage and then transmitted to the network processor112via the bus interface312and internal bus IB2.

Next, the cell distributor362reads the transmission source address from the loop inhibition field SRC of the cell received from the selector334. If the transmission source address is the address of the network processor112, this means that the cell has traveled a complete circuit of the internal communication path. In this case, the cell distributor362disposes of the cell. If the transmission source address is not the address of the network processor112, the cell distributor362transfers the cell to the selector354.

The selector354operates in an identical manner to the selector334. When the received cell is a user cell, the selector354transfers the cell to the format converter372. If the received cell is the token cell, or in other words if the selector354obtains transmission rights, the selector354reads the user cells stored in the buffer352. The read user cells are transmitted to the format converter372. When reading is complete, the selector354transmits the token cell to the format converter372.

As described above, the format converter372converts the format of the received cells when necessary, and then transfers the cells to the processor interface122.

The format converter371receives cells from the internal buses IB5, IB9a, and when necessary converts the format of the received cells. Cells received from the internal bus IB9aare transferred to the cell distributor361or internal bus IB5. The format converter371transfers cells inputted from the internal bus IB5to the cell distributor361only when the token cell has been received thereby (in other words, when transmission rights have been obtained). If transmission rights are not held, the format converter371stores the cells received from the internal bus IB5in an internal buffer not shown in the drawing.

The cell distributor361operates in an identical manner to the cell distributor362. When the network processor111is included in the destination of the received user cell, the cell distributor361transmits a copy of the user cell to the writer321. The writer321stores the received user cell in the buffer322. The user cells stored in the buffer322are read by the reader323at a later stage and then transmitted to the network processor111via the bus interface311and internal bus IB1. When the transmission source of the received cell is the network processor111, the cell distributor361disposes of the cell. User cells which are not disposed of and the token cell are transferred to the selector334.

The processor interface122operates in an identical manner to the processor interface121and hence description thereof has been omitted.

FIG. 5is a diagram showing in outline the internal communication path of the communication control device100.

As shown inFIG. 5, the network processors111to114are connected to a ring-type internal communication path500via internal communication paths501to504(corresponding to the internal buses IB1to IB4). Here, the communication path501may be considered schematically as a communication path which connects a processor unit210and a coprocessor unit220(seeFIG. 2) to the ring-type internal communication path500(in actual fact, the processor unit210communicates with the processor interface121via the coprocessor unit220). Hence each of processor units in the network processors111to114are capable of communicating not only with other processor units, but also with coprocessor units of other network processors. Similarly, the coprocessor units in the network processors111to114are capable of communicating not only with other coprocessor units, but also with the processor units of other network processors. Note, however, that there is a case where the processor units does not need to be provided with a communication function.

Further, in the communication control device100of this embodiment, the connection switch131and network processors111to114are connected via the ring-type internal communication path500. Note, however, that the connection switch131and network processors111to114may be connected by a separate communication path (not shown). If a separate communication path is used, it is possible to use a cell format different from the cell format of the ring-type internal communication path500(seeFIGS. 4A,4B). For example, a cell format employed in an external network connected to the communication paths P1, P2can become to be used.

As described above, in this embodiment the control buses CB1to CB5are mainly used in the initialization of the communication control device100. However, the present invention may be applied to a communication control device in which the control buses CB1to CB5are used for controlling communication other than initialization. The present invention may also be applied to a communication control device not provided with the control buses CB1to CB5.

This embodiment was described employing as a case in which two processor interfaces121,122and four network processors111to114are used. However, the present invention does not limit the number of processor interfaces and network processors.

The communication control device100of this embodiment uses a token cell, and thus signal breakdowns on the internal communication path can be prevented. In other words, the communication control device100uses a token cell to manage transmission rights, and thus the internal communication path may be set in a plurality of processor interfaces. As a result, communication speed among network processors in the communication control device100is high, and accordingly processing speed in the communication control device is also high. Further, by providing the internal communication path, the number of communication ports in each network processor can be reduced.

Second Embodiment

The overall constitution of a communication control device according to this embodiment is identical to the overall constitution of the communication control device100according to the first embodiment (seeFIG. 1). The communication control device according to this embodiment differs from that of the first embodiment in the internal constitution of the processor interfaces.

FIG. 6is a view illustrating the internal constitution of processor interfaces610,620according to this embodiment. InFIG. 6, constitutional elements having identical reference numerals toFIG. 3have the same constitution as the corresponding constitutional elements inFIG. 3.

As shown inFIG. 6, the processor interface610comprises cell controllers611,612and a transmission rights manager613. Similarly, the processor interface620comprises cell controllers621,622and a transmission rights manager623. In this embodiment, a bus-type internal communication path is set in the processor interfaces610,620. The bus-type internal communication path is constituted by buses BP0to BP4. These buses BP0to BP4correspond to the internal bus IB9in FIG.1.

The cell controller611comprises the functions of the cell distributor and selector of the first embodiment. The cell controller611receives a user cell from the bus BP1and checks the destination of the user cell. If the network processor111is included in the destination of the cell, the cell controller611transmits the received cell to the buffer unit320. If the cell controller611has transmission rights, the cell controller611reads cells from the buffer unit330and outputs the cells to the bus BP1. The cell controllers612,621,622comprises the same functions as that of the cell controller611.

The transmission rights managers613,623grant transmission rights to the cell controllers611,612,621,622. Similarly to the first embodiment, transmission rights are never granted simultaneously to two or more cell controllers. When the transmission rights manager613receives a request for transmission rights from the cell controllers611,612, the other cell controllers lose transmission rights and then transmission rights are granted. In order to achieve this, the transmission rights manager613receives information relating to the presence or absence of transmission rights in the cell controllers621,622from the transmission rights manager623. Likewise, when the transmission rights manager623receives a request for transmission rights from the cell controllers621,622, the other cell controllers lose transmission rights and then transmission rights are granted. The transmission rights manager623receives information relating to the presence or absence of transmission rights in the cell controllers611,612from the transmission rights manager613. If requests are received simultaneously from a plurality of cell controllers, the transmission rights managers613,623grant transmission rights to one of the cell controllers on a preferential basis in accordance with predetermined rules.

In this embodiment, a token cell is not used in the determination of transmission rights and only user cells are transmitted along the internal communication paths BP0to BP4. Hence there is no need to provide the cells used in this embodiment with the token cell field TKN (seeFIG. 4A).

In this embodiment, a bus-type internal communication path is used instead of a ring-type. Accordingly, user cells do not circulate around the internal communication path but are transmitted in series from the transmission source cell controller to the other cell controllers. Hence there is no need to provide the cells used in this embodiment with the loop inhibition field SRC (seeFIG. 4A).

In the first and second embodiments, the processor interface may be constituted by either hardware or software.