Fabrication of a vertical fin field effect transistor with an asymmetric gate structure

A method of forming a vertical fin field effect transistor (vertical finFET) with two concentric gate structures, including forming one or more tubular vertical fins on a substrate, forming a first gate structure around an outer wall of at least one of the one or more tubular vertical fins, and forming a second gate structure within an inner wall of at least one of the one or more tubular vertical fins having the first gate structure around the outer wall.

BACKGROUND

Technical Field

The present invention generally relates to a vertical fin field effect transistor structure with two separate gates, and more particularly to a vertical fin field effect transistor (vertical finFET) with a channel control gate and a back gate.

Description of the Related Art

A Field Effect Transistor (FET) typically has a source, a channel, and a drain, where current flows from the source to the drain, and a gate that controls the flow of current through the channel. Field Effect Transistors (FETs) can have a variety of different structures, for example, FETs have been fabricated with the source, channel, and drain formed in the substrate material itself, where the current flows horizontally (i.e., in the plane of the substrate), and finFETs have been formed with the channel extending outward from the substrate, but where the current also flows horizontally from a source to a drain. A vertical finFET can also be configured with a bottom source/drain in the substrate and a top source/drain on the vertical fin, where the current then flows in a direction perpendicular to the substrate. The channel for the finFET can typically be an upright slab of thin rectangular Si, commonly referred to as the fin with a gate on the fin, as compared to a MOSFET with a gate on the substrate. Depending on the doping of the source and drain, an n-FET or a p-FET may be formed.

Examples of FETs can include a metal-oxide-semiconductor field effect transistor (MOSFET) and an insulated-gate field-effect transistor (IGFET). Two FETs also may be coupled to form a complementary metal oxide semiconductor (CMOS) device, where a p-channel MOSFET and n-channel MOSFET are coupled together.

With ever decreasing device dimensions, forming the individual components and electrical contacts become more difficult. An approach is therefore needed that retains the positive aspects of traditional FET structures, while overcoming the scaling issues created by forming smaller device components.

SUMMARY

In accordance with an embodiment of the present principles, a method is provided for forming a vertical fin field effect transistor (vertical finFET) with two concentric gate structures. The method includes the step of forming one or more tubular vertical fins on a substrate, forming a first gate structure around an outer wall of at least one of the one or more tubular vertical fins, and forming a second gate structure within an inner wall of at least one of the one or more tubular vertical fins having the first gate structure around the outer wall.

In accordance with an embodiment of the present principles, a method is provided for forming a vertical fin field effect transistor (vertical finFET) with two concentric gate structures. The method includes the step of forming a plurality of sacrificial mandrels on a substrate and reducing the lateral dimensions of the sacrificial mandrels. The method further includes the step of forming a tubular vertical fin on each of the plurality of sacrificial mandrels. The method further includes the step of forming a first gate structure around an outer wall of at least one of the plurality tubular vertical fins, removing the plurality of sacrificial mandrels, and forming a second gate structure on at least a portion of an inner wall of each tubular vertical fin.

In accordance with another embodiment of the present principles, a vertical fin field effect transistor device with a concentric gate structure is provided. The device includes a tubular vertical fin, a first gate structure formed on at least a portion of the outer wall of the tubular vertical fin, and a second gate structure formed on at least a portion of the inner wall of the tubular vertical fin.

DETAILED DESCRIPTION

Principles and embodiments of the present disclosure relate generally to fabricating two separate gate structures on the same vertical fin to affect broader control of current in the vertical channel of a finFET. A first gate may be configured and used for current control in the channel, while the second gate may be configured and used as a back gate to apply a voltage bias to adjust a threshold voltage of the finFET. In various embodiments, the two separate gate structures may operate independently, where each gate structure may have a separate electrical contact. In various embodiments, the two separate gate structures may be formed on the vertical fins without greatly increasing the complexity of the fabrication process.

Principles and embodiments of the present disclosure relate generally to avoiding formation of a wrap-around gate on a vertical fin by arranging the two gates and the channel concentrically, where a first gate is surrounded by a wall of the fin material and a second gate surrounds the fin wall, such that the second gate is in contact with the outer face of the fin wall and the first gate is in contact with the inner face of the fin wall. A fin wall can have a tubular configuration having two sides but no ends, thereby providing a geometry in which the channel, itself, acts as a barrier that separates asymmetric gate structures, where the current flows perpendicular to the substrate.

Due to the concentric arrangement, two or more vertical fin walls may be surrounded by the same second gate structure. The second gate structure may be partitioned by etching and forming isolation regions between neighboring fins to form different vertical finFETs. The vertical fin(s) may form a plurality of devices each having single or multiple tubular vertical fins, where the gates and/or source/drains may be electrically coupled.

Exemplary applications/uses to which the present principles can be applied include, but are not limited to: formation of vertical finFETs, complementary metal oxide silicon (CMOS) field effect transistors (FETs) formed by coupled finFETs, and digital gate devices (e.g., NAND, NOR, XOR, etc.).

In various embodiments, the materials and layers may be deposited by physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), or any of the various modifications thereof, for example plasma-enhanced chemical vapor deposition (PECVD), metal-organic chemical vapor deposition (MOCVD), low pressure chemical vapor deposition (LPCVD), electron-beam physical vapor deposition (EB-PVD), and plasma-enhanced atomic layer deposition (PE-ALD). The depositions may be epitaxial processes, and the deposited material may be crystalline. In various embodiments, formation of a layer may be by one or more deposition processes, where, for example, a conformal layer may be formed by a first process (e.g., ALD, PE-ALD, etc.) and a fill may be formed by a second process (e.g., CVD, electrodeposition, PVD, etc.).

Referring now to the drawings in which like numerals represent the same or similar elements and initially toFIG. 1, shows a cross-sectional side view of a substrate with a mandrel layer formed on the substrate surface, in accordance with an exemplary embodiment.

It should be noted that certain features may not be shown in all figures for the sake of clarity. This is not intended to be interpreted as a limitation of any particular embodiment, or illustration, or scope of the claims.

In one or more embodiments, a substrate110may be a semiconductor or an insulator with an active surface semiconductor layer. The substrate may be crystalline, semi-crystalline, microcrystalline, or amorphous. The substrate may be essentially (i.e., except for contaminants) a single element (e.g., silicon), primarily (i.e., with doping) of a single element, for example, silicon (Si) or germanium (Ge), or the substrate may include a compound, for example, Al2O3, SiO2, GaAs, SiC, or SiGe. The substrate may also have multiple material layers, for example, a semiconductor-on-insulator substrate (SeOI), a silicon-on-insulator substrate (SOI), germanium-on-insulator substrate (GeOI), or silicon-germanium-on-insulator substrate (SGOI). The substrate may also have other layers forming the substrate, including high-k oxides and/or nitrides. In one or more embodiments, the substrate110may be a silicon wafer. In various embodiments, the substrate may be a single crystal silicon (Si), silicon germanium (SiGe), or III-V semiconductor (e.g., GaAs) wafer, or have a single crystal silicon (Si), silicon germanium (SiGe), or III-V semiconductor (e.g., GaAs) surface/active layer.

In one or more embodiments, a mandrel layer120may be formed on the surface115of the substrate110. The mandrel layer120may be epitaxially grown on a crystalline surface of the substrate110, where the mandrel layer120may have the same crystal structure as the underlying substrate. In various embodiments, the mandrel layer120may be silicon germanium (SiGe) grown by heteroepitaxy on the surface of a single crystal silicon substrate110.

FIG. 2is a cross-sectional side view of a hardmask layer patterned on a liner layer on a plurality of sacrificial mandrels formed from the mandrel layer, in accordance with an exemplary embodiment.

In one or more embodiments, a liner layer may be formed on at least a portion of the substrate mandrel layer120. A hardmask layer may be formed on at least a portion of the liner layer. The liner layer may have a thickness in the range of about 1 nm to about 10 nm, or in the range of about 2 nm to about 5 nm.

In one or more embodiments, a liner layer may be an oxide, for example, silicon oxide (SiO), silicon oxynitride (SiON), or a combination thereof. The liner layer may be deposited or formed by a thermal process, such as, for example, oxidation and/or nitridation of the top portion of the mandrel layer120. The liner layer may protect the underlying material from having defects introduced by formation of a hardmask layer. The liner layer may be a material different than the hardmask layer, where the liner layer may act as an etch stop layer. In various embodiments, the hardmask layer may be formed directly on the mandrel layer120without an intervening liner layer.

In one or more embodiments, a hardmask layer may be formed on an exposed surface of the liner layer. In various embodiments, the hardmask layer may be an oxide, for example, silicon oxide (SiO), a nitride, for example, a silicon nitride (SiN), or an oxynitride, for example, silicon oxynitride (SiON), or a combination thereof. In various embodiments, the hardmask layer may be silicon nitride (SiN), for example, Si3N4.

In one or more embodiments, the hardmask layer may have a thickness in the range of about 20 nm to about 100 nm, or in the range of about 35 nm to about 75 nm, or in the range of about 45 nm to about 55 nm, although other thicknesses are contemplated.

A photo mask layer may be formed and patterned on the exposed surface of the hardmask layer to form photo mask(s). The photo mask layer may be a temporary resist (e.g., poly methyl methacrylate (PMMA)) that may be deposited on the hardmask layer, patterned, and developed to expose portions of the hardmask layer. The photo mask layer may be a positive resist or a negative resist.

In one or more embodiments, the hardmask layer may be etched to form one or more hardmask slab(s)141, where the photo mask defines the width, length, and location of the hardmask slab(s)141on the mandrel layer120. In various embodiments, the liner layer may act as an etch stop. The liner layer may be etched to form a liner plate131below each hardmask slab141.

In one or more embodiments, a portion of the mandrel layer120may be removed to form one or more sacrificial mandrels121on the substrate.

In one or more embodiments, the photo mask(s), liner plate(s)131, and/or hardmask slab(s)141may have a width in the range of about 6 nm to about 20 nm, or may have a width in the range of about 8 nm to about 15 nm, or may have a width in the range of about 10 nm to about 12 nm. The photo mask(s), liner plate(s)131, and/or hardmask slab(s)141may have a length in the range of about 100 nm to about 1000 nm, or in the range of about 100 nm to about 500 nm, or in the range of about 100 nm to about 400 nm, or in the range of about 100 nm to about 200 nm.

In various embodiments, there may be a pitch, P1, between adjacent hardmask slabs141in the range of about 30 nm to about 200 nm, or in the range of about 30 nm to about 100 nm, or in the range of about 30 nm to about 50 nm, or about 42 nm.

In one or more embodiments, portions of the mandrel layer120may be removed by an isotropic etch or an anisotropic etch. An anisotropic etch may be a directional dry plasma etch that preferentially removes material from exposed surfaces approximately perpendicular to the incident direction of the plasma. The dry plasma etch may be a reactive ion etch (RIE). An isotropic etch may be a wet chemical etch that removes material from exposed surfaces approximately uniformly depending on the selectivity of the wet chemical etchant. In one or more embodiments, an RIE may be used to form one or more mandrel trenches to separate the mandrel layer into a plurality of sacrificial mandrels121.

FIG. 3is a cross-sectional side view of a hardmask slab and liner plate on each of a plurality of laterally reduced sacrificial mandrels on a substrate, in accordance with an exemplary embodiment.

In one or more embodiments, a portion of the sacrificial mandrel(s)121may be removed, where the removed portion may be from the sidewall of the sacrificial mandrel(s)121to reduce the lateral dimensions of the sacrificial mandrel(s)121.

In various embodiments, a portion of the sacrificial mandrel sidewalls may be removed by an oxidation and etching process, where a portion of the sacrificial mandrel121is converted to a thermal oxide and removed by a hydrofluoric acid (HF) wet etch. In various embodiments, a portion of the sacrificial mandrel sidewalls may be removed directly by a selective isotropic wet etch that preferentially removes the material of the sacrificial mandrel(s)121, while minimizing or avoiding etching of the substrate surface115, liner plate(s)131, and hardmask slab(s)141. The sacrificial mandrel(s)121may have a smaller lateral dimensions (i.e., width, length) than the liner plate(s)131, and/or hardmask slab(s)141after removal of the mandrel/oxide material.

In a non-limiting example, a SiGe sacrificial mandrel121may be exposed to an oxidizing atmosphere that reacts with the Si of the sacrificial mandrel121to form a layer of silicon oxide on the perimeter of the sacrificial mandrel121. The layer of silicon oxide on the perimeter of the sacrificial mandrel121may then be removed by a HF wet etch leaving a sacrificial mandrel121with a reduced width and length (i.e., lateral dimensions).

In one or more embodiments, a doped region230may be formed in the substrate110. The doped region may be formed in-situ or ex-situ below the vertical fin(s)151. One or more doped regions230may be formed in the substrate above which each of the one or more vertical fins may be formed. The dopant may be provided to the doped region(s)230by ion implantation, and source/drains formed by annealing the doped region(s). In various embodiments, the doped region230(i.e., source/drain region) may be n-doped or p-doped. The doped region230may form a bottom source/drain of a vertical fin field effect transistor (vertical finFET). In various embodiments, a plurality of vertical fins111may be electrically coupled to the same bottom source/drain to form a multi-fin vertical FET. The vertical fin(s) and bottom source/drain(s) may be suitably doped to form an NFET or a PFET.

FIG. 4is a cross-sectional side view of a vertical fin formed on each of the sacrificial mandrels, in accordance with an exemplary embodiment.

In one or more embodiments, a vertical fin151may be formed on each sacrificial mandrel121. The vertical fin151may be formed on the sacrificial mandrel121by a heteroepitaxial growth process, where the vertical fin151is crystalline and has the same crystal orientation and structure as the underlying substrate surface and sidewall surface of the sacrificial mandrel. In a non-limiting embodiment, a crystalline silicon vertical fin151may be grown on a single crystal silicon substrate and a SiGe sacrificial mandrel. In various embodiments, the vertical fin(s)151may be suitably doped to form channels of a vertical finFET, where the vertical fin may be doped in-situ or ex-situ.

FIG. 5is a cross-sectional top view of a vertical fin formed on a sacrificial mandrel on the substrate, in accordance with an exemplary embodiment.

In one or more embodiments, the vertical fin151may have an annular shape that surrounds the sacrificial mandrel121, where the sacrificial mandrel may be rectangular, circular, oval, oblong, elliptical, etc., and where the vertical fin151has a thickness in the lateral direction In various embodiments, the channel of a vertical finFET may be configured as a tube having an outer wall153, an inner wall157, each with a height, and a wall thickness, TF, therebetween. The vertical fin151may be in direct contact with the outer surface of the sacrificial mandrel121.

In various embodiments, the vertical fin(s)151may have a thickness, TF, in the range of about 6 nm to about 20 nm, or may have a width in the range of about 8 nm to about 15 nm, or in the range of about 10 nm to about 12 nm.

FIG. 6is a cross-sectional side view of a bottom spacer formed around each vertical fin on the sacrificial mandrels, in accordance with an exemplary embodiment.

In one or more embodiments, a bottom spacer161may be formed on the surface115of the substrate110, where the bottom spacer may be formed in the region(s) between each vertical fin151on a sacrificial mandrel. The bottom spacer may surround at least one vertical fin151. In various embodiments, the bottom spacer161may be formed by a blanket deposition over the hardmask slab(s)141and substrate surface115, and etched back to leave the bottom spacers161. The bottom spacers161also may be formed by a directional deposition, for example, a gas cluster ion beam (GCIB) deposition process that preferentially forms the bottom layer on the surfaces approximately normal to the direction of the ion beam. Portions of the bottom spacer161may be removed from the hardmask slab(s)141and/or sidewalls of the vertical fin(s)151, for example, by masking and etching to leave a bottom spacers161on the exposed portions of the substrate surface115adjacent to the lower portion(s) of the vertical fin(s)151. The bottom spacer161may be referred to as a first bottom spacer.

In one or more embodiments, the first bottom spacer161may have a thickness in the range of about 3 nm to about 25 nm, or in the range of about 5 nm to about 20 nm. The thickness of the first bottom spacer161may provide electrical isolation of subsequently formed work function layer(s) and/or a conducting gate fill layer from a doped region230in the substrate110.

FIG. 7is a cross-sectional side view of a gate structure formed on a bottom spacer around a plurality of vertical fins, in accordance with an exemplary embodiment.

In one or more embodiments, a gate structure may be formed on at least a portion of an outer wall153of a vertical fin151, where the outer wall may be a vertical sidewall of a tubular vertical fin151. A gate structure may include one or more material layers that insulate a conductive gate electrode from a vertical fin forming a channel.

In one or more embodiments, a gate dielectric layer171may be formed on at least a portion of a vertical fin151, where the gate dielectric layer171may be formed on the outer wall153of a vertical fin151. The gate dielectric layer171may be formed on at least a portion of a first bottom spacer161. The gate dielectric layer171may be referred to a first gate dielectric layer.

In various embodiments, the gate dielectric layer171may be an insulating dielectric material, for example, silicon oxide (SiO) or a high-k dielectric material.

In one or more embodiments, a gate structure may include a gate fill layer181, In one or more embodiments, a gate fill layer181may be formed on the first bottom spacer161and/or first gate dielectric layer171, where the gate fill layer181may be a conductive material that forms part of a gate electrode on a vertical fin151. In various embodiments, the gate fill layer181may be formed on the first bottom spacer161and/or a work function layer191. The gate fill layer181may be formed by a blanket deposition that fills the spaces between the vertical fins151, for example, by ALD, CVD, PVD, or a combination thereof. The gate fill layer181may extend above the tops surfaces of the vertical fin(s)151. The portion of gate fill layer181above the top surfaces of the vertical fin(s)151may be removed, for example, by chemical-mechanical polishing (CMP).

In various embodiments, the conductive gate fill layer181may be a metal, where the metal may be tungsten (W), titanium (Ti), molybdenum (Mo), cobalt (Co), or a combination thereof.

In one or more embodiments, a work function layer191may be formed between the gate dielectric layer171and the gate fill layer181. A work function layer191may be deposited over the gate dielectric layer171. The work function layer191may form part of a gate structure, where the gate structure may be on at least a portion of a vertical fin151.

In various embodiments, a work function layer191may be formed on the gate dielectric layer171by a blanket deposition, for example, CVD, and etched back.

In various embodiments, the work function layer191may be a nitride, including but not limited to titanium nitride (TiN), titanium aluminum nitride (TiAlN), hafnium nitride (HfN), hafnium silicon nitride (HfSiN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tungsten nitride (WN), molybdenum nitride (MoN), niobium nitride (NbN); a carbide, including but not limited to titanium carbide (TiC), titanium aluminum carbide (TiAlC), tantalum carbide (TaC), hafnium carbide (HfC), and combinations thereof.

In various embodiments, the work function layer191may have a thickness in the range of about 3 nm to about 11 nm, or may have a thickness in the range of about 5 nm to about 8 nm.

In one or more embodiments, a portion of the first gate fill layer181, first gate dielectric layer171, and/or first work function layer191may be removed to reduce the height of the first gate fill layer181, first gate dielectric layer171, and/or first work function layer191. In various embodiments, the first gate fill layer181, first gate dielectric layer171, and/or first work function layer191may be removed by a chemical-mechanical polishing (CMP). The height may be reduced to the top surface of the hardmask slab(s)141.

FIG. 8is a cross-sectional side view of a gate structure formed on a plurality of vertical fins, in accordance with an exemplary embodiment.

In one or more embodiments, the hardmask slab(s)141and/or liner plate(s)131may be removed to expose the underlying sacrificial mandrel121and vertical fin(s)151. The hardmask slab(s)141and/or liner plate(s)131may be removed by an anisotropic etch, for example, a dry plasma etch, or an isotropic etch, for example, a selective wet etch, where the gate dielectric layer171, work function layer191, and the gate fill layer181may be masked prior to the etch and removed after the etch.

FIG. 9is a cross-sectional side view of a plurality of vertical fins after removal of the sacrificial mandrels, in accordance with an exemplary embodiment.

In one or more embodiments, a sacrificial mandrel121may be removed from within a tubular vertical fin151, where removal of the sacrificial mandrel121forms an open space within the tubular vertical fin151and exposes the inner wall157of the vertical fin151. In various embodiments, the sacrificial mandrel(s)121may be removed using a selective wet etch, RIE, or a combination thereof.

FIG. 10is a cross-sectional side view of a second bottom spacer formed within the tubular vertical fins after removal of the sacrificial mandrels, in accordance with an exemplary embodiment.

In one or more embodiments, a second bottom spacer162may be formed with the confines of a tubular vertical fin151, where the second bottom spacer162may be formed on the surface of the substrate110and on a portion of the vertical fin151. The second bottom spacer162may be formed preferentially on the substrate surface by a directional deposition, for example, PVD or GCIB. Material of the second bottom spacer162may be etched back and/or selectively removed from the inner wall157of the vertical fin151. The bottom spacers161,162may be over a doped portion of the substrate.

In one or more embodiments, the second bottom spacer(s)162may have a thickness in the range of about 3 nm to about 25 nm, or in the range of about 5 nm to about 20 nm. The thickness of the second bottom spacer162may provide electrical isolation of subsequently formed work function layer(s) and/or a conducting gate fill layer from a doped region230in the substrate110.

FIG. 11is a cross-sectional side view of the second bottom spacer formed within the tubular vertical fins and a second gate dielectric layer on the second bottom spacer and inner walls of the tubular vertical fins, in accordance with an exemplary embodiment.

In one or more embodiments, a second gate structure may be formed on at least a portion of an inner wall157of a vertical fin151, where the inner wall may be a vertical sidewall of a tubular vertical fin151opposite the outer wall153. A gate structure may include one or more material layers that insulate a conductive gate electrode from a vertical fin forming a channel.

In one or more embodiments, a second gate dielectric layer172may be formed on at least a portion of a vertical fin151, where the second gate dielectric layer172may be formed on the inner wall157of a vertical fin151. The gate dielectric layer172may be formed on at least a portion of a second bottom spacer162.

In various embodiments, the second gate dielectric layer172may be an insulating dielectric material, for example, silicon oxide (SiO) or a high-k dielectric material.

In various embodiments, the second gate dielectric layer172may be a high-K dielectric material that may include, but is not limited to, metal oxides such as hafnium oxide (e.g., HfO2), hafnium silicon oxide (e.g., HfSiO4), hafnium silicon oxynitride (HfwSixOyNz), lanthanum oxide (e.g., La2O3), lanthanum aluminum oxide (e.g., LaAlO3), zirconium oxide (e.g., ZrO2), zirconium silicon oxide (e.g., ZrSiO4), zirconium silicon oxynitride (ZrwSixOyNz), tantalum oxide (e.g., TaO2, Ta2O5), titanium oxide (e.g., TiO2), barium strontium titanium oxide (e.g., BaTiO3-SrTiO3), barium titanium oxide (e.g., BaTiO3), strontium titanium oxide (e.g., SrTiO3), yttrium oxide (e.g., Y2O3), aluminum oxide (e.g., Al2O3), lead scandium tantalum oxide (Pb(ScxTa1-x)O3), and lead zinc niobate (e.g., PbZn1/3Nb2/3O3). The high-k material may further include dopants such as lanthanum and/or aluminum. The stoichiometry of the high-k dielectric compounds may vary. In various embodiments, the second gate dielectric layer172may be the same material or a different material than the first gate dielectric layer171.

FIG. 12is a cross-sectional side view of the gate dielectric layer on the second bottom spacer and inner walls of the tubular vertical fins and a gate fill layer to form a second gate structure, in accordance with an exemplary embodiment.

In one or more embodiments, a second gate structure may include a second gate fill layer182. In one or more embodiments, a second gate fill layer182may be formed on the second bottom spacer162and/or second gate dielectric layer172, where the second gate fill layer182may be a conductive material that forms part of a gate electrode on a vertical fin151. In various embodiments, the gate fill layer182may be formed on the bottom spacer162and/or a work function layer192. The second gate fill layer182may be formed by a blanket deposition that fills the spaces within tubular vertical fin(s)151, for example, by ALD, CVD, PVD, or a combination thereof. The second gate fill layer182may extend above the tops surfaces of the vertical fin(s)151. The portion of gate fill layer182above the top surfaces of the vertical fin(s)151may be removed, for example, by chemical-mechanical polishing (CMP).

In various embodiments, the conductive second gate fill layer182may be a metal, where the metal may be tungsten (W), titanium (Ti), molybdenum (Mo), cobalt (Co), or a combination thereof. The second gate fill layer182may be the same material or a different material than the first gate fill layer181.

In one or more embodiments, a second work function layer192may be formed between the second gate dielectric layer172and the second gate fill layer182. A second work function layer192may be deposited over the second gate dielectric layer172. The second work function layer192may form part of the second gate structure, where the gate structure may be on at least a portion of a vertical fin151. The second work function layer192may be the same material or a different material than the first work function layer191.

In various embodiments, a second work function layer192may be formed on the second gate dielectric layer172by a blanket deposition, for example, CVD, and etched back.

In various embodiments, the second work function layer192may be a nitride, including but not limited to titanium nitride (TiN), titanium aluminum nitride (TiAlN), hafnium nitride (HfN), hafnium silicon nitride (HfSiN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tungsten nitride (WN), molybdenum nitride (MoN), niobium nitride (NbN); a carbide, including but not limited to titanium carbide (TiC), titanium aluminum carbide (TiAlC), tantalum carbide (TaC), hafnium carbide (HfC), and combinations thereof. The second work function layer192may be the same material or a different material than the first work function layer191.

In various embodiments, the second work function layer192may have a thickness in the range of about 3 nm to about 11 nm, or may have a thickness in the range of about 5 nm to about 8 nm.

In one or more embodiments, the channel of a vertical finFET is configured as a tube of semiconductor material having a wall thickness with a first gate outside and adjacent to the perimeter of the tube and a second gate within the tube.

FIG. 13is a cross-sectional side view of a gate fill layer and a gate dielectric layer on the inner walls of the tubular vertical fins after planarization, in accordance with an exemplary embodiment.

In one or more embodiments, a portion of the second gate fill layer182, second gate dielectric layer172, and/or second work function layer192may be removed to reduce the height of the second gate fill layer182, second gate dielectric layer172, and/or second work function layer192. In various embodiments, the second gate fill layer182, second gate dielectric layer172, and/or second work function layer192may be removed by a chemical-mechanical polishing (CMP) or etch-back. The height may be reduced to approximately the top surface of the first gate fill layer181.

FIG. 14is a cross-sectional side view of a first and second gate fill layers and gate dielectric layers with a reduced height, in accordance with an exemplary embodiment.

In one or more embodiments, the heights of the first gate fill layer181, second gate fill layer182, first gate dielectric layer171, second gate dielectric layer172, and/or first and second work function layers191,192may be reduced to below the top surface(s)155of the tubular vertical fin(s)151. The heights of the first gate fill layer181, second gate fill layer182, first gate dielectric layer171, second gate dielectric layer172, and/or first and second work function layers191,192may be reduced by an amount sufficient to provide space for the formation of a top spacer on the first and second gate structures, while leaving a portion of the vertical fin(s)151exposed for formation of a top source/drain.

FIG. 15is a cross-sectional side view of a top spacer formed on the first and second gate structures, in accordance with an exemplary embodiment.

In one or more embodiments, a top spacer layer may be formed on the exposed surfaces of the first gate fill layer181, second gate fill layer182, first gate dielectric layer171, second gate dielectric layer172, and/or first and second work function layers191,192, as well as on the top surface(s)155of the tubular vertical fin(s)151.

The first gate fill layer181, second gate fill layer182, first gate dielectric layer171, second gate dielectric layer172, and/or first and second work function layers191,192, may be removed (e.g., by RIE) until the top surface of the first gate fill layer181and second gate fill layer182is below the top surface(s)155of the tubular vertical fin(s)151by an intended thickness of the top spacers200. Top spacer(s)200may be formed on the exposed surfaces of the first gate fill layer181, second gate fill layer182, first gate dielectric layer171, second gate dielectric layer172, and/or first and second work function layers191,192, for example, by CVD, PVD, ALD, GCIB, or a combination thereof. The top spacers200may provide electrical isolation of the gate structures from a top source/drain.

FIG. 16is a cross-sectional side view of a capping layer over the top spacers on the first and second gate structures, in accordance with an exemplary embodiment.

In one or more embodiments, a capping layer210may be formed on the top spacers200, where the capping layer may be a silicon nitride (SiN) or low-K dielectric material, for example, fluorine doped SiO, carbon doped SiO, porous SiO, or combinations thereof, where the capping layer may be formed by processes known in the art.

In one or more embodiments, the capping layer may be blanket deposited over the top spacers200and vertical fins151. The capping layer210may extend above the tops of the top spacers200and vertical fins151.

FIG. 17is a cross-sectional side view of a capping layer on the top spacers after etching back, in accordance with an exemplary embodiment.

In one or more embodiments, the height of the capping layer may be reduced by a CMP. The height of the capping layer may be reduced to the top surface of the capping layer210on the vertical fins151.

In various embodiments, the capping layer210may be selectively etched back to expose at least a portion of the top spacers200on the top surfaces155of the vertical fin(s)151. The capping layer may be selectively etched back by a directional reactive ion etch (RIE) or a selective wet etch. The capping layer210may be selectively etched back to the level of the top surfaces155of the vertical fin(s)151.

FIG. 18is a cross-sectional side view of a capping layer on the top spacers after removal of the top spacers from the top surfaces of the vertical fins, in accordance with an exemplary embodiment.

In one or more embodiments, the portion of the top spacers200formed on the top surfaces155of the vertical fin(s)151may be removed to expose the top surfaces155of the vertical fin(s)151. The portion of the top spacers200formed on the top surfaces155may be removed by CMP, a selective wet etch, selective RIE, or a combination thereof, where the capping layer210remaining on the top spacers200between the vertical fins151can act as an etch stop layer and/or a protective layer during removal of the portion of the top spacers200. The top surfaces155of the vertical fin(s)151may be exposed after removal of the top spacers200.

FIG. 19is a cross-sectional side view of an exposed surface of the top spacers after removal of the capping layer, in accordance with an exemplary embodiment.

In one or more embodiments, the capping layer210remaining on the top spacers200between the vertical fins151may be selectively removed to expose the top spacers200. In various embodiments, the capping layer may be adjacent to and cover a portion of the sidewall(s) of the vertical fins151. When the capping layer is removed, a portion of the sidewall(s) of the vertical fins151may also be exposed. The portion of the capping layer210may be removed by a selective wet etch, selective RIE, or a combination thereof.

FIG. 20is a cross-sectional side view of a top source/drain formed on the exposed portion of the vertical fins, and an interlayer dielectric on the top source/drains, in accordance with an exemplary embodiment.

In one or more embodiments, a top source/drain220may be formed on the sidewalls153,157and/or top surfaces155of the vertical fin(s)151. The top source/drain(s)220may be formed by epitaxially growth on the exposed surfaces of the vertical fin(s)151, where the top source/drains220may have the same crystal structure and orientation as the vertical fin(s)151.

In various embodiments, the top source/drain(s)220may be doped in-situ or ex-situ, where the doping may be p-type doping or n-type doping to form an n-type vertical FET (NFET) or a p-type vertical FET (PFET). The channel may be suitably doped to affect the carrier concentrations and to form an n-type vertical finFET or a p-type vertical finFET in relation to the top source/drains220and doped region(s)230forming bottom source drain(s) of the vertical finFETs.

In various embodiments, the top source/drain220may be the same material as the vertical fin151on which the top source/drain220is formed. In various embodiments, the source and drain may be interchanged, where the doped regions230can form a drain and the epitaxially formed doped material at the top of the vertical fin151may be the source.

In one or more embodiments, an interlayer dielectric240may be formed on the top spacer(s)200and the top source/drain220, where the interlayer dielectric240may be blanket deposited on the exposed top surfaces of the top spacers200and top source/drain(s)220. The height of the interlayer dielectric240may then be reduced, for example, by CMP.

In various embodiments, the interlayer dielectric240may be, for example, silicon oxide (SiO), silicon nitride (SiN), silicon boron carbonitride (SiBCN), silicon oxycarbide (SiOC), etc. The interlayer dielectric240may be the same or different material as the top spacer(s)200. In one or more embodiments, an interlayer dielectric240may be a low-K dielectric material, for example, fluorine doped SiO, carbon doped SiO, porous SiO, or combinations thereof. The interlayer dielectric240may be an insulating material that electrically insulates electrical contacts formed to the gate structures, and/or source/drains.

FIG. 21is a cross-sectional side view of electrical contacts formed in interlayer dielectric to the gate structure and top source/drains, in accordance with an exemplary embodiment.

In one or more embodiments, interconnect vias may be formed in the interlayer dielectric240and filled with a conductive material (e.g., tungsten. copper, titanium, molybdenum, aluminum, or combinations thereof) to form electrical contacts250,251,252, where the electrical contacts may be first gate structure contacts250, top source/drain contacts251, or second gate structure contacts252. The interconnect vias and electrical contacts250,252may extend through the top spacer(s)200to the first gate fill layer181or second gate fill layer182, respectively.

In one or more embodiments, a trench may be cut into the interlayer dielectric240and first gate structure, and down into the substrate110. The trench may be filled with an insulating dielectric material to form an isolation region260to electrically isolate one or more tubular vertical fin(s)151into a vertical finFET device.

FIG. 22is a cross-sectional top view ofFIG. 21showing two tubular vertical fins surrounded by the same first gate structure and an isolation region to form a vertical finFET, in accordance with an exemplary embodiment.

In one or more embodiments, an isolation region260may be formed around one or more tubular vertical fin(s)151to electrically isolate the one or more tubular vertical fin(s)151and gate structures into a single vertical finFET device. The first gate fill layer181may surround the first gate dielectric layer171forming a first gate structure on the outer wall of the vertical fin151, and the isolation region260may surround the first gate structure. The vertical fin151may surround the second gate dielectric layer172and second gate fill layer182forming a second gate structure on the inner wall of each vertical fin151, where the first gate structure, tubular vertical fin151, and second gate structure are concentric device components. The first gate structure and second gate structure may, thereby, be physically separate and independent.

In various embodiments, two or more second gate structures on the inner wall of each vertical fin151forming the same vertical finFET device may be electrically coupled, so the two or more second gate structures operate in tandem. The first gate structure and second gate structure may not be electrically coupled together, so the first and second gate structures operate independently, or the first and second gate structures may be electrically coupled together to operate in tandem.

FIG. 23is a cross-sectional top view ofFIG. 21showing the interlayer dielectric, two top source/drains, and electrical contacts forming a vertical finFET, in accordance with an exemplary embodiment.

In one or more embodiments, isolation region260may surround a portion of the interlayer dielectric240and top source/drain(s)220of a vertical finFET device. One or more second gate structure contacts252may be formed in an interconnect via through the interlayer dielectric240to a second gate fill layer182to electrically couple the second gate structure to an external electrical contact. One or more first gate structure contacts250may be formed in an interconnect via through the interlayer dielectric240to a first gate fill layer181to electrically couple the first gate structure to an external electrical contact. A top source/drain contact251may be formed in an interconnect via through the interlayer dielectric240to each top source/drain220to electrically couple the top source/drain(s) to an external electrical contact. In various embodiments, the first gate structure may be used as a channel control gate, and the second gate structure may be used for back bias (e.g. threshold voltage adjustment).

FIG. 24is a cross-sectional side view of a hardmask slab and liner plate on each of a plurality of laterally reduced sacrificial mandrels on a substrate similar toFIG. 3, in accordance with another exemplary embodiment.

FIG. 25is a cross-sectional side view of a vertical fin epitaxially grown on each of the sacrificial mandrels and epitaxially grown substrate layer, in accordance with another exemplary embodiment.

In one or more embodiments, the formation of vertical fin(s)151may also include forming additional material116on the surface115of the substrate110, where the material may be the same material as the vertical fin(s). In various embodiments, the formation of vertical fin(s)151may be altered to also epitaxially grow additional substrate material116on the surface115of the substrate110, while epitaxially growing the vertical fin(s)151on the sacrificial mandrel(s)121. The thickness of the substrate may be increased in the areas between the sacrificial mandrels121to produce a relatively deeper second gate structure within the tubular vertical fin151, and a relatively higher first gate structure outside the vertical fin151. The additional substrate material116may be grown on the substrate surface115by preparing the surface for epitaxial growth and leaving the prepared surface exposed during formation of the vertical fin(s)151.

In various embodiments, the distance from the top surface155of the tubular vertical fin to the substrate surface115is greater within the tubular vertical fin than the distance from the top surface155of the tubular vertical fin151to the substrate surface115outside the same tubular vertical fin151, such that the heights of the walls on the inside and outside of the tubular vertical fin151are different to provide an asymmetric gate structure.

In various embodiments, the additional substrate material116may have a thickness, TAd, in the range of about 6 nm to about 20 nm, or in the range of about 8 nm to about 15 nm, or in the range of about 10 nm to about 12 nm. The additional substrate material116may be added to the portion of the substrate110outside of the tubular vertical fin151, where the additional thickness may be the same thickness as the vertical fin151formed during the epitaxial growth process.

FIG. 26is a cross-sectional side view of a gate structure and bottom spacer on the additional substrate material around a plurality of vertical fins, in accordance with another exemplary embodiment.

A first bottom spacer161and first gate structure including a first gate dielectric layer171and first gate fill layer181may be formed on the substrate area having the additional substrate material116, such that the first gate structure is raised in reference to the level of the substrate surface within the tubular vertical fin151.

FIG. 27is a cross-sectional side view of a bottom spacer formed within the tubular vertical fins after removal of the sacrificial mandrels and hardmask slab(s), in accordance with another exemplary embodiment.

In one or more embodiments, the hardmask slab(s)141and liner plate(s)131may be removed to expose sacrificial mandrel(s)121. The sacrificial mandrel(s)121may then be removed to expose the substrate surface within the tubular vertical fin(s)151, and a second bottom spacer162may be formed on the substrate surface115within the tubular vertical fin(s)151, as described forFIGS. 9 and 10. In various embodiments, the second bottom spacer162may be below the level of the first bottom spacer161.

FIG. 28is a cross-sectional side view of a gate dielectric layer on the second bottom spacer and inner walls of the tubular vertical fins and a gate fill layer to form a second gate structure, in accordance with another exemplary embodiment.

In one or more embodiments, a second gate structure may include a second gate fill layer182. In one or more embodiments, a second gate fill layer182may be formed on the second bottom spacer162and/or second gate dielectric layer172, where the second gate fill layer182may be a conductive material that forms part of a gate electrode on a vertical fin151. In various embodiments, the gate fill layer182may be formed on the bottom spacer162and/or a work function layer192, where the work function layer192is formed between the second gate dielectric layer and the second gate fill layer. The second gate fill layer182may be formed by a blanket deposition that fills the spaces within tubular vertical fin(s)151, for example, by ALD, CVD, PVD, or a combination thereof. The second gate fill layer182may extend above the tops surfaces of the vertical fin(s)151. The portion of gate fill layer182above the top surfaces of the vertical fin(s)151may be removed, for example, by chemical-mechanical polishing (CMP). In various embodiments, the second gate dielectric layer and the second gate fill layer may be below the level of the first gate dielectric layer and the first gate fill layer to provide a first gate structure and a second gate structure with asymmetric dimensions.

In various embodiments, the conductive second gate fill layer182may be a metal, where the metal may be tungsten (W), titanium (Ti), molybdenum (Mo), cobalt (Co), or a combination thereof. The second gate fill layer182may be the same material or a different material than the first gate fill layer181.

FIG. 29is a cross-sectional side view of an exposed surface of the top spacers after formation of the second gate structure, in accordance with another exemplary embodiment.

In various embodiments, the second gate structure may be adjusted and top spacer layers200formed as described forFIGS. 13 to 19.

An interlayer dielectric240and interconnect vias may be formed and filled with a conductive material (e.g., tungsten. copper, titanium, aluminum, or combinations thereof) to form electrical contacts, where the electrical contacts may be first gate structure contacts, top source/drain contacts, or second gate structure contacts, as described forFIGS. 20 and 21, to form the vertical finFET devices described inFIGS. 22 and 23, with asymmetric first and second gate structures.