SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR DEVICE INCLUDING THE SAME

A semiconductor package may include a first substrate, a second substrate at least partially surrounding the first substrate, the first substrate disposed in an opening penetrating the second substrate, and a semiconductor chip on the first substrate. The first substrate may be spaced apart from the second substrate in the opening, and a thickness of the first substrate may be less than a thickness of the second substrate.

CROSS-REFERENCE TO RELATED APPLICATION

This U.S. non-provisional patent application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2019-0062189, filed on May 27, 2019, in the Korean Intellectual Property Office, the disclosure of which is hereby incorporated by reference in its entirety.

TECHNICAL FIELD

The present disclosure relates to semiconductors and, more specifically, to a semiconductor package and a semiconductor device including the same.

DISCUSSION OF THE RELATED ART

There are many methods by which a semiconductor die may be packaged. According to a ball grid array (BGA) method for semiconductor packaging, a plurality of solder balls may be bonded onto a top surface or bottom surface of a substrate. The solder balls may each be in contact with an external terminal or device.

Semiconductor chips have become highly integrated as the number of circuit elements on a single chip has increased. The larger and more highly integrated a semiconductor chip becomes, the more points of electrical contact will be needed to connect the packaged semiconductor chip to a circuit board or other external devices. As these points of electrical contact may be made with the solder balls, a large number of solder balls may be required in packaged semiconductor chips that are large and highly integrated, such as those semiconductor chips that are used in products such as a server and a modern television.

As the size and complexity of semiconductor chips increases, there is a possibility that a substrate of the semiconductor chip may warp. Thus, a substrate of at least a certain thickness may be used to control warpage. However, when a thick substrate is used, it may be difficult to control power integrity and signal integrity within the semiconductor chip.

When a semiconductor chip is thinly formed to realize a limited package thickness, a thermal resistance within the semiconductor chip may be increased.

SUMMARY

Embodiments of the inventive concepts may provide a flip chip-ball grid array (FC-BGA) semiconductor package capable of maintaining power integrity and reducing a spreading thermal resistance while maintaining mechanical strength of a general FC-BGA having a large size and a thick substrate. A semiconductor device may include the FC-BGA semiconductor package.

According to an exemplary embodiment of the present disclosure, a semiconductor package includes a first substrate. A second substrate at least partially surrounds the first substrate. The first substrate is disposed in an opening penetrating the second substrate. A semiconductor chip is disposed on the first substrate. The first substrate is spaced apart from the second substrate in the opening. A thickness of the first substrate is less than a thickness of the second substrate.

According to an exemplary embodiment of the present disclosure, a semiconductor device includes a first semiconductor package. A plurality of second semiconductor packages is disposed on the first semiconductor package. The first semiconductor package includes a first substrate, a second substrate including an opening in which the first substrate is disposed, and a semiconductor chip on the first substrate. A thickness of the first substrate is less than a thickness of the second substrate.

According to an exemplary embodiment of the present disclosure, a semiconductor package includes a first substrate. A second substrate at least partially surrounds the first substrate. The first substrate is disposed in an opening penetrating the second substrate. A semiconductor chip is disposed on the first substrate. A plurality of bumps is disposed between the first substrate and the semiconductor chip. A plurality of wires electrically connects the first substrate and the second substrate. A molding member covers the first substrate and the second substrate and fills a gap between the first and second substrates. A plurality of first solder balls is disposed on a bottom surface of the first substrate. A plurality of second solder balls is disposed on a bottom surface of the second substrate. The first substrate is spaced apart from the second substrate in the opening. A thickness of the first substrate is equal to or less than a half of a thickness of the second substrate. A level of a bottom surface of the first substrate is the same as a level of a bottom surface of the second substrate. The first substrate is a coreless substrate, and the second substrate has a core.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Semiconductor packages and methods of manufacturing the same, according to exemplary embodiments of the inventive concepts, will be described hereinafter in detail with reference to the accompanying drawings.

FIG. 1Ais a plan view illustrating a semiconductor package according to some exemplary embodiments of the inventive concepts.FIG. 1Bis a cross-sectional view taken along a line I-I′ ofFIG. 1A. Some components ofFIG. 1Bare omitted inFIG. 1Afor the purpose of ease, clearness and convenience in illustration. However, it is to be understood that these figures are not intended to be exclusive of additional elements, which may be included thereto within the scope of the disclosure.

Referring toFIGS. 1A and 1B, a semiconductor package1000, according to some exemplary embodiments of the inventive concepts, may include a first substrate100and a second substrate200at least partially surrounding the first substrate100. Each of the first and second substrates100and200may include a printed circuit board (PCB).

A core might not be disposed in the first substrate100(i.e., the first substrate100may be a coreless substrate), or a relatively thin core may be disposed in a central portion of the first substrate100. The first substrate100may be an organic material-based substrate or a silicon-based substrate. The organic material may include, for example, an epoxy-based compound.

The second substrate200may include a core201in its central portion. The core201may include, for example, a glass fiber. Metal patterns202may be provided on opposite surfaces (e.g., top and bottom surfaces) of the core201.

The first substrate100may have a first width100in a first direction D1parallel to a top surface of the first substrate100. The second substrate200may have a second width Δ200in the first direction D1. The second width Δ200may be, for example, 40 mm. The first width Δ100may be less than the second width Δ200. For example, the first width100may be ⅓ of the second width Δ200.

The first substrate100may have a first thickness ΔH1in a second direction D2that is perpendicular to the top surface of the first substrate100. For example, the first thickness ΔH1may range from several tens of micrometers (μm) to several hundreds of micrometers (μm). The second substrate200may have a second thickness ΔH2in the second direction D2. The second thickness ΔH2may range from several hundreds of micrometers (μm) to several millimeters (mm). The first thickness ΔH1may be less than the second thickness ΔH2. For example, the first thickness ΔH1may be equal to or less than a half of the second thickness ΔH2.

The core201in the second substrate200may have a thickness ΔC in the second direction D2, and the thickness ΔC of the core201may be, for example, several hundreds of micrometers (μm).

A level of a bottom surface100L of the first substrate100may be the same as a level of a bottom surface200L of the second substrate200. Since the first thickness ΔH1is less than the second thickness ΔH2, a level of a top surface100T of the first substrate100may be lower than a level of a top surface200T of the second substrate200.

A gap300may exist between the first substrate100and the second substrate200. The gap300may be a region between the first substrate100and the second substrate200, and the first substrate100and the second substrate200may be separated from each other by the gap300. The gap300may have a thickness Δ300in the first direction D1.

A plurality of first solder balls600amay be provided on the bottom surface100L of the first substrate100. The first solder balls600amay be in contact with the bottom surface100L of the first substrate100. A connection member (e.g., a pad) may be disposed between each of the first solder balls600aand the first substrate100. The connection member may be a part of the first substrate100. A plurality of second solder balls600bmay be provided on the bottom surface200L of the second substrate200. The second solder balls600bmay be in contact with the bottom surface200L of the second substrate200. A connection member (e.g., a pad) may be disposed between each of the second solder balls600band the second substrate200. The connection member may be a part of the second substrate200.

A semiconductor chip400may be provided on the first substrate100so as to overlap the first substrate. The semiconductor chip might not be provided on the second substrate200or the gap300and might therefore not overlap either the second substrate200or the gap300. The semiconductor chip400may include, for example, a system-on-chip (SOC). A level of a top surface400T of the semiconductor chip400may be higher than the level of the top surface200T of the second substrate200. Alternatively, the level of the top surface400T of the semiconductor chip400may be the same as or lower than the level of the top surface200T of the second substrate200.

A plurality of bumps401may be provided between the first substrate100and the semiconductor chip400. The first substrate100and the semiconductor chip400may be electrically connected to each other through the bumps401.

A plurality of bonding wires700electrically connecting the first and second substrates100and200to each other may be provided. The semiconductor chip400may be electrically connected to the second substrate200through the first substrate100and the bonding wires700.

A molding member500(e.g. a mold) may cover the first substrate100, the second substrate200, and the semiconductor chip400. The first substrate100may be physically and mechanically connected to the second substrate200by the molding member500, which is in contact with both the first and second substrates100and200. The molding member500may include, for example, an epoxy resin. The molding member500may fill the gap300. A solder ball might not be disposed under the gap300filled with the molding member500.

FIGS. 2A to 2Gare cross-sectional views illustrating a method of manufacturing a semiconductor package, according to some exemplary embodiments of the inventive concepts. Hereinafter, the descriptions to the same features as mentioned with reference toFIGS. 1A and 1Bwill be omitted for the purpose of ease and convenience in explanation. It will be assumed that the omitted elements are at least similar to those corresponding elements ofFIGS. 1A and 1B.

Referring toFIGS. 2A and 2B, an opening OP may be formed in a portion of the second substrate200. The portion of the second substrate200in which the opening OP is formed may be, for example, a central portion of the second substrate200. For example, the opening OP may be centered within the second substrate200. The opening OP may be formed by a mechanical punching or laser drilling process performed in a direction from a region over the second substrate200toward the top surface200T of the second substrate200. For example, a width ΔOP of the opening OP in the first direction D1may be ⅓ of the second width Δ200of the second substrate200.

Referring toFIG. 2C, a carrier substrate CR may be adhered to the bottom surface200L of the second substrate200in which the opening OP is formed. The carrier substrate CR may be adhered to the bottom surface200L of the second substrate200by an adhesive layer that may be, or may be on, a top surface of the carrier substrate CR.

Referring toFIG. 2D, the first substrate100may be disposed in the opening OP of the second substrate200. The first substrate100may be provided on a portion of the carrier substrate CR exposed by the opening OP. The bottom surface100L of the first substrate100may be adhered to the carrier substrate CR by the adhesive layer that may be, or may be on, the top surface of the carrier substrate CR. The gap300may extend between the first substrate100and the second substrate200. The gap300may be an empty region between the first and second substrates100and200and may overlap with a portion of the opening OP.

Referring toFIG. 2E, the semiconductor chip400may be mounted on the first substrate100. The semiconductor chip400and the first substrate100may be connected to each other by a reflow process of bumps401between the semiconductor chip400and the first substrate100. This connection may be an electrical connection for transmitting power and/or signals between the semiconductor chip400and the first substrate100.

Referring toFIG. 2F, the bonding wires700electrically connecting the first and second substrates100and200may be formed. The bonding wire700may be in contact with a connection member (e.g., a pad) on the first substrate100and a connection member (e.g., a pad) on the second substrate200. This connection may be an electrical connection for transmitting power and/or signals between the first and second substrates100and200.

Referring toFIG. 2G, the molding member500may be formed to cover each of the first substrate100, the second substrate200, and the semiconductor chip400. The molding member500may fill the gap300.

Referring again toFIG. 1B, the carrier substrate CR may be removed. A solution treatment and/or a heat treatment may be performed to remove any portion of the adhesive layer remaining on the bottom surface100L of the first substrate100, the bottom surface200L of the second substrate200, and a bottom surface of the molding member500filling the gap300.

Next, the first solder balls600amay be formed on connection members (e.g., pads) of the bottom surface100L of the first substrate100, and the second solder balls600bmay be formed on connection members (e.g., pads) of the bottom surface200L of the second substrate200.

FIGS. 3A to 3Dare cross-sectional views illustrating examples of a semiconductor package according to some embodiments of the inventive concepts. Hereinafter, the descriptions to the same features as mentioned with reference toFIGS. 1A and 1Bwill be omitted for the purpose of ease and convenience in explanation and it is to be understood that omitted features may be at least similar to corresponding features shown inFIGS. 1A and 1B.

Referring toFIG. 3A, a semiconductor package1001, according to an example of some embodiments of the inventive concepts, may further include a capacitor100cembedded in the first substrate100. The embedded capacitor100cmay be electrically connected to the semiconductor chip400. Solder balls600include both the first solder balls600athat are in contact with the first substrate100and the second solder balls600bthat are in contact with the second substrate200.

Referring toFIG. 3B, a semiconductor package1002, according to an example of some embodiments of the inventive concepts, may further include a heat conductive material800aon the semiconductor chip400, and a heat dissipation plate800bcovering both the heat conductive material800aand the molding member500.

For example, the heat conductive material800amay include thermal grease, a thermal sheet/film, a thermal pad, and/or a thermal adhesive. The heat dissipation plate800bmay include copper (Cu), aluminum (Al), and/or an alloy of one or more of these metals. Heat generated from the semiconductor chip400may be effectively released to the outside through the heat conductive material800aand the heat dissipation plate800b.

Referring toFIG. 3C, a semiconductor package1003, according to an example of some embodiments of the inventive concepts, may further include a third substrate101on the first substrate100. The third substrate101may be spaced apart from the first substrate100and may face the first substrate100. A third thickness ΔH3of the third substrate101in the second direction D2may be less than the second thickness ΔH2of the second substrate200in the second direction D2.

The third substrate101may be substantially identical to the first substrate100. For example, the third substrate101may also be a coreless organic material-based substrate or an organic material-based substrate having a core having a thickness of several tens micrometers (μm).

A plurality of interconnection members102may be disposed between the first substrate100and the third substrate101. The plurality of interconnection members102may include a conductive material, and the first substrate100and the third substrate101may be electrically connected to each other through the interconnection members102.

A first molding member501may be provided to fill a space between the first substrate100and the third substrate101. A second molding member502may be provided to cover both the third substrate101and the second substrate200and to fill a space between the first molding member501and the second substrate200. The second molding member502may correspond to the molding member500ofFIG. 1B. The first and second molding members501and502may include, for example, an epoxy compound. The first and second molding members501and502may be made of a same material or may be made of different materials.

A plurality of bonding wires701electrically connecting the third substrate101and the second substrate200may be provided. The semiconductor chip400may be electrically connected to the second substrate200through the first substrate100, the interconnection members102, the third substrate101, and the bonding wires701. The heat dissipation plate800bmay be provided on the second molding member502. Heat generated from the semiconductor chip400may be effectively released to the outside through the heat dissipation plate800b.

Referring toFIG. 3D, a semiconductor package1004, according to an example of some embodiments of the inventive concepts, may include a plurality of semiconductor chips400a,400b, and400con the first substrate100. For example, the plurality of semiconductor chips400a,400b, and400cmay include a first semiconductor chip400a, a second semiconductor chip400bstacked on the first semiconductor chip400a, and a third semiconductor chip400cstacked on the second semiconductor chip400b. Adhesive layers may be disposed between each of the semiconductor chips400a,400b, and400c.

The first semiconductor chip400amay be electrically connected to the first substrate100through a plurality of bumps401being in contact with a bottom surface of the first semiconductor chip400a.

The second semiconductor chip400bmay be electrically connected to the first substrate100through first bonding wires700a. The third semiconductor chip400cmay be electrically connected to the first substrate100through second bonding wires700b. The first substrate100may be electrically connected to the second substrate200through third bonding wires700c. Alternatively, the first through third bonding wires700a,700b, and700cmay be omitted and the second semiconductor chip400bmay be electrically connected to the first substrate100through the first semiconductor chip400awhile the third semiconductor chip400cmay be electrically connected to the first substrate100through the first and second semiconductor chips400band400c. In such an arrangement, there may be additional bumps disposed between the first and second semiconductor chips400aand400b, as well as between the third and second semiconductor chips400cand400b.

The molding member500may cover each of the second substrate200, the plurality of semiconductor chips400a,400b, and400c, and the first substrate100. The heat dissipation plate800bmay be provided on the molding member500. Heat generated from the semiconductor chips400a,400b, and400c, may be effectively released to the outside through the heat dissipation plate800b.

FIG. 4Ais a plan view illustrating a semiconductor device including a semiconductor package according to some exemplary embodiments of the inventive concepts.FIG. 4Bis a cross-sectional view taken along a line I-I′ ofFIG. 4A. Some components ofFIG. 4Bare omitted inFIG. 4Afor the purpose of ease, clearness and convenience in illustration. Hereinafter, the descriptions to the same features as mentioned with reference toFIGS. 1A and 1Bwill be omitted for the purpose of ease and convenience in explanation. It may therefore be assumed that the omitted elements are at least similar to corresponding elements previously illustrated and described.

Referring toFIGS. 4A and 4B, a semiconductor device1500, including the semiconductor package, according to some exemplary embodiments of the inventive concepts, may include a first semiconductor package PK1and a plurality of second semiconductor packages PK2on the first semiconductor package PK1.

Except for positional relation of the first and second substrates100and200in a plan view and a region covered by the molding member500in a plan view, other components and features of the first semiconductor package PK1may be substantially identical to as corresponding components and features of the semiconductor package1000ofFIG. 1B.

Sides of the first substrate100of the first semiconductor package PK1might not be parallel to sides of the second substrate200of the first semiconductor package PK1when viewed in a plan view. For example, each of the sides of the first substrate100may form a rotation angle with each of the sides of the second substrate200. For example, one diagonal line of the first substrate100may be parallel to one of two sides of the second substrate200and may be perpendicular to the other of the two sides of the second substrate200.

The molding member500may cover both the semiconductor chip400and the first substrate100and may fill the gap300. The molding member500may cover a portion of the top surface of the second substrate200.

The second semiconductor packages PK2may be configured to perform different functions from that of the semiconductor chip400disposed on the first substrate100. The second semiconductor package PK2may be provided on the top surface of the second substrate200and might not be covered by the molding member500. For example, the semiconductor chip400may include a system-on-chip (SOC), and the second semiconductor packages PK2may include memory semiconductor packages (e.g., DRAM packages).

The second semiconductor packages PK2may be spaced apart from each other with the semiconductor chip400interposed therebetween. The second semiconductor packages PK2may be disposed on a peripheral portion of the second substrate200. For example, four second semiconductor packages PK2may be disposed on the second substrate200, for example, at four corners thereof.

The second semiconductor packages PK2may be electrically connected to the first semiconductor package PK1through a plurality of bumps16disposed on the second substrate200.

FIG. 4Cis a plan view illustrating an example of a semiconductor device including a semiconductor package according to some exemplary embodiments of the inventive concepts. Hereinafter, the descriptions to the same features as mentioned with reference toFIGS. 4A and 4Bwill be omitted for the purpose of ease and convenience in explanation. It may therefore be assumed that the omitted elements are at least similar to corresponding elements previously illustrated and described.

Referring toFIG. 4C, except for positional relation of a first substrate100, a gap300and a second substrate200of a first semiconductor package PK1and the number of second semiconductor packages PK2, other components and features of a semiconductor device1501according to the present example may be substantially identical to corresponding components and features of the semiconductor device1500described with reference toFIGS. 4A and 4B.

Each side of the first substrate100and each side of the second substrate200which face each other may be parallel to each other when viewed in a plan view. The first substrate100may be disposed in a central portion of the second substrate200or may be disposed at a position spaced apart from the central portion of the second substrate200in a direction away from the second semiconductor packages PK2. Likewise, the gap300may be disposed in the central portion of the second substrate200or may be disposed at a position spaced apart from the central portion of the second substrate200in the direction away from the second semiconductor packages PK2.

The second semiconductor packages PK2may be configured to perform different functions from that of the semiconductor chip400disposed on the first substrate100. The second semiconductor package PK2may be provided on the top surface of the second substrate200. For example, the second semiconductor packages PK2may be arranged in a line at a side of the semiconductor chip400. InFIG. 4C, two second semiconductor packages PK2are arranged in a line at a side of the semiconductor chip400. However, embodiments of the inventive concepts are not limited thereto.

FIG. 5Ais a plan view illustrating a semiconductor package according to some exemplary embodiments of the inventive concepts.FIG. 5Bis a cross-sectional view taken along a line I-I′ ofFIG. 5A. Some components ofFIG. 5Bare omitted inFIG. 5Afor the purpose of ease, clearness and convenience in illustration.

Hereinafter, the descriptions to the same features as mentioned with reference toFIGS. 1A and 1Bwill be omitted for the purpose of ease and convenience in explanation. It may therefore be assumed that the omitted elements are at least similar to corresponding elements previously illustrated and described.

Referring toFIGS. 5A and 5B, a semiconductor package2000, according to some embodiments of the inventive concepts, may include an inner package IPK, a redistribution layer900, a second substrate200, and a second molding member502.

The inner package IPK may include a first substrate100, a semiconductor chip400, bumps401, and a first molding member501. The semiconductor chip400may be disposed on the first substrate100with the bumps401interposed therebetween. The first molding member501may at least partially cover the first substrate100and the semiconductor chip400. The first molding member501may include, for example, an epoxy material.

The second molding member502may at least partially cover the second substrate200and the first molding member501and may fill the gap300. The second molding member502may include, for example, an epoxy material.

The redistribution layer900may be provided on the bottom surface100L of the first substrate100and the bottom surface200L of the second substrate200. The redistribution layer900may include one or two insulating layers and a metal pattern disposed between the insulating layers. A fourth thickness ΔH4of the redistribution layer900in the second direction D2may be several tens of micrometers (μm).

A top surface of the redistribution layer900may be in contact with the bottom surface100L of the first substrate100and the bottom surface200L of the second substrate200. The first substrate100and the second substrate200may be electrically connected to each other through the redistribution layer900.

Third solder balls600cand fourth solder balls600dmay be disposed on a bottom surface of the redistribution layer900. The third solder balls600cmay at least partially overlap with the first substrate100in the second direction D2, and the fourth solder balls600dmay at least partially overlap with the second substrate200in the second direction D2. The third solder balls600cmight not overlap with the second substrate200and the fourth solder balls600dmight not overlap with the first substrate100.

The third solder balls600cand the fourth solder balls600dmay each be in contact with the bottom surface of the redistribution layer900. A connection member (e.g., a pad) may be disposed between each of the third solder balls600cand the redistribution layer900. A connection member (e.g., a pad) may be disposed between each of the fourth solder balls600dand the redistribution layer900.

FIGS. 6A to 6Care cross-sectional views illustrating a method of manufacturing a semiconductor package, according to some exemplary embodiments of the inventive concepts.

First, as described with reference toFIG. 2C, a carrier substrate CR may be adhered to the bottom surface200L of the second substrate200in which the opening OP is formed. The carrier substrate CR may be adhered to the bottom surface200L of the second substrate200by an adhesive layer that is part of or on a top surface of the carrier substrate CR.

Referring toFIG. 6A, the inner package IPK may be disposed in the opening OP. The inner package IPK may be provided on a portion of the carrier substrate CR exposed by the opening OP. The bottom surface of the first substrate100may be adhered to the carrier substrate CR by an adhesive layer of the top surface of the carrier substrate CR. The gap300may be defined between the inner package IPK and the second substrate200. The gap300may be an empty region between the inner package IPK and the second substrate200and may at least partially overlap with a portion of the opening OP.

Referring toFIG. 6B, the second molding member502may be formed on the carrier substrate CR. The second molding member502may cover the second substrate200and the inner package IPK. The second molding member502may fill the gap300.

Referring toFIG. 6C, the carrier substrate CR may be removed. A solution treatment and/or a heat treatment may be performed to remove the adhesive layer remaining on the bottom surface100L of the first substrate100, a bottom surface of the second molding member502in the gap300, and the bottom surface200L of the second substrate200.

Subsequently, the redistribution layer900may be formed on the bottom surface100L of the first substrate100, the bottom surface of the second molding member502in the gap300, and the bottom surface200L of the second substrate200.

Referring again toFIG. 5B, a plurality of solder balls600cand600dmay be formed on a bottom surface of the redistribution layer900. The third solder balls600cand the fourth solder balls600dmay be in contact with the bottom surface of the redistribution layer900. The third solder balls600cmay at least partially overlap with the first substrate100in the second direction D2, and the fourth solder balls600dmay at least partially overlap with the second substrate200in the second direction D2. The third solder balls600cmight not overlap with the second substrate in the second direction D2and the fourth solder balls600dmight not overlap with the first substrate100in the second direction D2.

FIGS. 7A and 7Bare cross-sectional views illustrating examples of a semiconductor package according to some exemplary embodiments of the inventive concepts. Hereinafter, the descriptions to the same features as mentioned with reference toFIGS. 5A and 5Bwill be omitted for the purpose of ease and convenience in explanation. It may therefore be assumed that the omitted elements are at least similar to corresponding elements previously illustrated and described.

Referring toFIG. 7A, a semiconductor package2001, according to the present example, may further include a heat dissipation plate800bcovering the second molding member502. Heat generated from the semiconductor chip400may be effectively released to the outside through the heat dissipation plate800b.

Referring toFIG. 7B, a semiconductor package2002, according to the present example, may include an inner package IPK including a plurality of semiconductor chips400a,400b, and400c. For example, the plurality of semiconductor chips400a,400b, and400cmay include a first semiconductor chip400aon the first substrate100, a second semiconductor chip400bon the first semiconductor chip400a, and a third semiconductor chip400con the second semiconductor chip400b. Adhesive layers may be disposed between the semiconductor chips400a,400band400c.

The first semiconductor chip400aand the first substrate100may be electrically connected to each other through a plurality of bumps401disposed therebetween. The second semiconductor chip400bmay be electrically connected to the first substrate100through first bonding wires700a. The third semiconductor chip400cmay be electrically connected to the first substrate100through second bonding wires700b. The first substrate100may be electrically connected to the second substrate200through the redistribution layer900.

The first molding member501may cover the plurality of semiconductor chips400a,400b, and400cand the first substrate100. The second molding member502may cover the second substrate200, the inner package IPK, and the gap300. The heat dissipation plate800bmay be provided on the second molding member502.

FIG. 8is a cross-sectional view illustrating a semiconductor device including a semiconductor package, according to some exemplary embodiments of the inventive concepts. Hereinafter, the descriptions to the same features as mentioned with reference to FIGS. SA and SB will be omitted for the purpose of ease and convenience in explanation. It may therefore be assumed that the omitted elements are at least similar to corresponding elements previously illustrated and described.

Referring toFIG. 8, a semiconductor device2500including the semiconductor package according to some exemplary embodiments of the inventive concepts may include an inner package IPK, a third semiconductor package PK3including the inner package IPK, and a plurality of fourth semiconductor packages PK4on the third semiconductor package PK3.

The inner package IPK may include a first substrate100and a third substrate101facing the first substrate100. The third substrate101may be spaced apart from the first substrate100and may face the first substrate100. The third substrate101may be substantially identical to the first substrate100. For example, the third substrate101may also be a coreless organic material-based substrate or an organic material-based substrate having a core having a thickness of several tens of micrometers (μm).

A plurality of interconnection members102may be disposed between the first substrate100and the third substrate101. The plurality of interconnection members102may include a conductive material, and the first substrate100and the third substrate101may be electrically connected to each other through the interconnection members102.

A first molding member501may be provided to fill a space between the first substrate100and the third substrate101.

The third semiconductor package PK3may include a second substrate200, a first redistribution layer901, a second redistribution layer902, a plurality of solder balls600cand600d, and a second molding member502.

The second substrate200may surround the inner package IPK with a gap300interposed therebetween. The first redistribution layer901may be provided on a bottom surface of the inner package IPK and a bottom surface of the second substrate200. A top surface of the first redistribution layer901may be in contact with a bottom surface of the first substrate100and the bottom surface of the second substrate200. The second redistribution layer902may be provided on a top surface of the inner package IPK and a top surface of the second substrate200. A bottom surface of the second redistribution layer902may be in contact with a top surface of the third substrate101and the top surface of the second substrate200.

The plurality of solder balls600cand600dmay be disposed on a bottom surface of the first redistribution layer901. Third solder balls600cmay at least partially overlap with the first substrate100in the second direction D2. Fourth solder balls600dmay at least partially overlap with the second substrate200in the second direction D2. The third solder balls600cmight not overlap with the second substrate200in the second direction D2and the fourth solder balls600dmight not overlap with the first substrate100in the second direction D2.

The second molding member502may fill the gap300between the inner package IPK and the second substrate200. The inner package IPK and the second substrate200may be physically connected to each other by the second molding member502being in contact with both the inner package IPK and the second substrate200.

The fourth semiconductor packages PK4may be disposed on the second redistribution layer902. The fourth semiconductor packages PK4may perform a different function from that of the third semiconductor package PK3.

For example, the third semiconductor package PK3may be a semiconductor package including a system-on-chip (SOC), and the fourth semiconductor packages PK4may be semiconductor packages including memory chips (e.g., DRAM chips).

FIG. 9is a graph showing a reduction effect of a resistance junction ambient (Rja) according to a change in height of a package according to some exemplary embodiments of the inventive concepts.

A sample of an experimental example 1 may be a FC-BGA package including the relatively thin first substrate and the relatively thick second substrate, like the semiconductor package according to the example of the inventive concepts ofFIG. 3B. A sample of a comparative example 1 may be a FC-BGA package including a single substrate having the same thickness as the second substrate of the experimental example 1.

A total size of the package of the experimental example 1 may be equal to a total size of the package of the comparative example 1, and a thickness of a semiconductor chip of the experimental example 1 may be greater than a thickness of a semiconductor chip of the comparative example 1. Other components (e.g., a size of a solder ball, a height of a heat dissipation plate, a thickness of a heat conductive material, etc.) of the experimental example 1 may be the same as corresponding components of the comparative example.

Referring toFIG. 9, the resistance junction ambient (Rja) of the experimental example 1 is excellent as compared with that of the comparative example 1. In addition, a change amount of the resistance junction ambient (Rja) value is less even though a height of the package is reduced.

FIG. 10is a graph showing an effect of reduction of an electrical resistance of a package according to some exemplary embodiments of the inventive concepts.

A sample of an experimental example 1 may be a FC-BGA package including the first relatively thin substrate and the second relatively thick substrate, like the semiconductor package according to the embodiments of the inventive concepts ofFIG. 1B.

A sample of an experimental example 2 may be a FC-BGA package including the capacitor embedded in the first substrate, like the example of the inventive concepts ofFIG. 3A.

A sample of a comparative example 1 may be a FC-BGA package including a single substrate having the same thickness as the second substrate of the experimental example 1. For example, the package of the comparative example 1 might not use a plurality of substrates.

A self-impedance of PDN of the experimental example 1 according to the inventive concepts is better than that of the comparative example 1, in an experimental frequency range. In addition, referring to the results of the experimental example 2, characteristics of the self-impedance of PDN are more desirable when the package includes the capacitor embedded in the first substrate.

According to exemplary embodiments of the inventive concepts, the first substrate under the semiconductor chip may be the coreless substrate or may include the relatively thin core, and thus the thickness of the first substrate may be less than the thickness of the second substrate. As a result, the thickness of the semiconductor chip may be increased while maintaining a total thickness of the package, and thus thermal characteristics may be more desirable (e.g., reduction of a spreading thermal resistance). In addition, power vias may be distributed at the first substrate under the semiconductor chip. Since the first substrate is relatively thin, lengths of the vias may be reduced to obtain an effect of reduction of an insertion voltage loss and an effect of reduction of cross talk.

The second substrate may be relatively thick and may have excellent strength so as not to easily warp. The first substrate may be physically and mechanically connected to the second substrate by the molding member, and thus mechanical strength of the FC-BGA package with respect to warpage may be maintained or increased.

According to the embodiments of the inventive concepts, it is possible to increase power integrity and thermal characteristics of the semiconductor package while maintaining or increasing mechanical strength of the semiconductor package.

While the inventive concepts have been described with reference to example embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirits and scopes of the inventive concepts.