Electric signal transmission device

Provided is an electric signal transmission device which corrects a data error caused by data transition in a pulse amplitude modulation signal to increase an EYE width. The electric signal transmission device can operate as follows: A data pattern determined by an equalizer and a phase relationship between data and a clock detected by a phase detector are used to calculate a correction amount according to the data pattern and the phase relationship, and the received data is corrected to a correct value by adding a correction amount in a data transition direction.

TECHNICAL FIELD

The present invention relates to a receiver for high-speed wired transmission and a semiconductor integrated circuit usable for the receiver, and more particularly to a technique for correcting a signal error.

BACKGROUND ART

In recent years, attention has been focused on the use of big data, and traffic volume and data processing volume in data centers are increasing. Correspondingly, the data volumes and the processing capabilities of information communication devices are increasing. At that time, the communication speeds inside and outside the devices which are a bottleneck of large-scale data processing are also improving. For example, in communication outside the device, a transmission rate of 56 Gbps per channel is being standardized.

It is thought that communication is made difficult with a conventional non return to zero (NRZ) modulated signal because high-speed communication causes an increase in transmission loss in a communication path and 1 unit interval (UI) width of data is reduced. As described above, there is a limit to high-speed communication in a time direction, and it has been proposed to use pulse amplitude modulation-4 (PAM) which is a type of multi-level modulation, for a generation of 56 Gbps transmission rate per channel (see NPL 1).

CITATION LIST

Non Patent Literature

SUMMARY OF INVENTION

Technical Problem

In signal transmission using a PAM modulated signal, the number of data transition patterns increases compared with that in signal transmission using an NRZ modulated signal. Therefore, a phenomenon is seen in which an EYE width narrows in data transition pattern which would not be a problem in the NRZ modulated signal. For example, a time required for transition from −1 to +1 and a time required for transition from −3 to +3 are different, and the time required for transition from −3 to +3 has an increased transition time due to the increase of voltage change. For this reason, the EYE width tends to be narrow in a data pattern requiring a long time for data transition. These effects have influences independently of inter symbol interference (ISI), which has become a problem, and cannot be cancelled with filters, such as feed forward equalizer (FFE), continuous-time linear equalizer (CTLE), and decision feedback equalizer (DFE).

Therefore, in the present invention, it is an object to suppress a reduction of an EYE width due to change of transition time caused by a data pattern.

Solution to Problem

As means for solving the above problems, the present invention has the following features.

The present invention relates to a receiver having a data pattern correcting unit for suppressing EYE width reduction even though a transition time varies depending on input data patterns.

Although the transition time varies depending on the data input patterns and the EYE width is reduced, conversely, it can be said that there are patterns of data errors depending on data patterns. For example, when timing of fetching data is delayed in data transition, −3→+3, the data is incorrectly changed, for example, −1→+3. That is, it is uniformly determined how an error highly probably occurs depending on a data pattern and data capturing timing. For this reason, it is possible to correct data by extracting a data pattern on the basis of received data in which an error remains and applying a correction signal to the received signal according to a phase in the data pattern extraction.

Advantageous Effects of Invention

It is possible to suppress the reduction of the EYE width caused by the data pattern to suppress a bit error rate.

DESCRIPTION OF EMBODIMENTS

Details will be described below with reference to the drawings.

FIG. 1illustrates one aspect of wired transmission, exemplifying wired transmission on a single board. A signal processing ASIC102having a waveform equalization function, a communication ASIC103having a waveform equalization function, and a connector104are mounted on the board101, and the ASIC102and the ASIC103communicate with each other, and the ASIC103communicates with another device through the connector104.

FIG. 2illustrates an example in which the communication ofFIG. 1is performed not on a single board but on different boards via a transmission line, and a repeater is mounted on each of the boards. In the device, a board201on which a signal processing ASIC204and a repeater205are mounted is connected to a transmission line202via a connector208, and a transmission line202is connected to a board203on which, a repeater206, a communication ASIC207, and a connector210are mounted, via a connector209. The transmission line202may be a board or a cable. As in the signal flow ofFIG. 1, the signal processing ASIC204communicates with another device connected to the connector210via the communication ASIC207. A signal output from the ASIC204is relayed by the repeater205, passed through the connector208, the transmission line202and the connector209, further relayed by the repeater206, sent to the communication ASIC207, and transmitted to an external device through the connector210. Conversely, a signal received by the ASIC207from the external device through the connector210is sent to the repeater206and relayed, passed through the connector209, the transmission line202, and the connector208, is relayed by the repeater205, and received by the ASIC204.

FIG. 3illustrates an example in which the repeaters205and206ofFIG. 2are positioned in connectors304and305. The ASIC204mounted on a board301and the ASIC207mounted on a board303communicate with each other via the repeater205and the repeater206. The repeater205mounted on the connector304communicates with the repeater206mounted on the connector305via a transmission line302.

FIG. 4is a diagram illustrating only the transmitter and the receiver that perform waveform equalization of the ASIC102, the ASIC103, the ASIC204, the repeater205, the repeater206, and the ASIC206illustrated inFIGS. 1 to 3.FIG. 4is a schematic diagram in which a signal is transmitted from a semiconductor401and a semiconductor403receives the signal through a transmission line402. A transmitter404in the semiconductor401includes a feed forward equalizer (FFE)409, a multiplexer407, and a phase locked loop (PLL)408. A receiver405in the semiconductor403includes a continuous time linear equalizer (CTLE)410, an analog to digital converter (ADC)411, a decision feedback equalizer (DFE)412, a PLL413, and a clock and data recovery (CDR)414.

Next, a signal flow in the transmitter404will be described. The transmitter404receives a data signal421from a signal processing unit406, and the data signal421, which is transmitted in parallel, is converted in synchronization with a clock422from the PLL408in the multiplexer407, and transmitted in serial. A waveform of the data signal423output from the multiplexer407is equalized so as to reduce the gain on the low-frequency side in the FFE409, and an output signal424is output to the transmission line402. A signal425passing through the transmission line402is transmitted to the receiving unit405in the semiconductor403.

Next, a signal flow in the receiver405will be described. The data signal424output from the transmitter404attenuates through the transmission line402, the CTLE410amplifies and equalizes the high-frequency side of the data signal424to obtain an equalized signal426, and the equalized signal426is output to the ADC411. In the ADC411, the signal426amplified by the CTLE410is sampled by the CDR414in synchronization with a clock430obtained by adjusting the phase of an output clock429from the PLL413, and converted into a digital signal427. The output427from the ADC411is output to the DFE412. In the DFE412, the output427of the ADC411is filtered so as to be attenuated on the low-frequency side and amplified on the high-frequency side, and determined to have four values in the case of the PAM-4. receiver output data428determined to have four values is input to a signal processing unit415and the CDR414. In the CDR414, the phase of the output PLL output clock429is adjusted on the basis of the ADC output data427and the DFE output data428so that the data can be taken at a point where the EYE is most open. In addition, the signal processing unit415sends the receiver output data428to the transmitter, and is transmitted from the transmitter to the transmission line, and the data signal is relayed.

A conventional transceiver used also for the NRZ signal illustrated inFIG. 4has three equalizers of the FFE, CTLE, and DFE, but although these three equalizers are effective for ISI, the EYE width reduction due to a difference in data transition time cannot be corrected. The EYE width reduction due to the data transition time will be described with reference toFIG. 5.

FIG. 5illustrates an EYE waveform of a signal obtained after passing a 56 Gbps PAM-4 signal through a raised cosine filter with a bandwidth of 22 GHz and a roll-off of 0.5. InFIG. 5, when the signal has a value higher than a determination threshold501, the signal is determined to be +3, when the signal has a value between the determination threshold501and a determination threshold502, the signal is determined to be +1, when the signal has a value between the determination threshold502and a determination threshold503, the signal is determined to be −1, and when the signal has a value lower than the determination threshold503, the signal is determined to be −3. Ranges above the determination thresholds501,502, and503through which the signal does not pass is referred to as the EYE widths. As seen inFIG. 5, the EYE width is defined by the upper EYE width505and the lower the EYE width506, and the EYE widths505and506are defined by the data transition time, −3→+3 and +3→−3. The EYE width is narrowed by approximately 15 ps even under the condition that the bandwidth is limited by a frequency higher than the Nyquist frequency and there is almost no influence of ISI. In this manner, the EYE width of the PAM multilevel signal is narrowed relative to that of the NRZ signal due to data pattern dependence.

We propose a method of correcting data by detecting a data pattern which tends to be incorrectly transitioned from received data and correcting the detected data pattern to correct the data, considering that it can be predicted how transmitted data will be incorrectly transitioned depending on a pattern.

FIG. 6illustrates an example of PAM-4 where a phase is delayed. In this example, data is determined to be +3 when the data has a value above a threshold607, +1 when the data has a value between a threshold608and the threshold607, −1 when the data has a value between a threshold609and the threshold608, and −3 when the data has a value below the threshold609. In ideal data sampling timing, it is determined that data is +1 at the second data sampling timing601before current data sampling timing603, −3 at the previous data sampling timing602to the current data sampling timing603, and +3 at the current data sampling timing603. However, when the phase of the data sampling is delayed, a value at a phase advanced by the amount equal to the phase delay is sampled. Therefore, the data is determined to be +1 at the second data sampling timing604before the current data sampling timing603, and −1 at the previous data sampling timing605, and +1 at the current data sampling timing606, and at the data sampling timing603and the data sampling timing606, the data is incorrectly transitioned +3→+1. However, application of correction611with the same polarity as that of a value changing direction610enables correction to the original data. When the phase of a data pattern to be detected is delayed, the data pattern changes due to the influence of the previous data, so basically it is sufficient to detect data to be corrected and some previous data sequences.

FIG. 7illustrates an example of PAM-4 where a phase advances. In this example, data is determined to be +3 when the data has a value above a threshold707, +1 when the data has a value between a threshold708and the threshold707, −1 when the data has a value between a threshold709and the threshold708, and −3 when the data has a value below the threshold709. In ideal data sampling timing, it is determined that the data is +3 at current data sampling timing701, −3 at the subsequent data sampling timing702to the current data sampling timing701, and +3 at the second data sampling timing703after the current data sampling timing701. However, when the phase of data sampling advances, a value at a phase delayed by the amount equal to the phase advance is sampled. Therefore, the data is determined to be +1 at the current data sampling timing704, and −1 at the subsequent data sampling timing705, and +1 at the second data sampling timing706after the current data sampling timing704, and at the data sampling timing701and the data sampling timing703, the data is incorrectly transitioned +3→+1. However, application of correction711with the opposite polarity to that of a value change direction710enables correction to the original data. InFIG. 7, since the polarity of the correction is opposite to that in the phase delay ofFIG. 6, it is necessary to detect the advance and the delay of the phase. In addition, when the phase of a data pattern to be detected advances, the data pattern changes due to the influence of the subsequent data, so basically it is sufficient to detect data to be corrected and some subsequent data sequences.

First Embodiment

To achieve the above description,FIG. 8illustrates a configuration according to a first embodiment. To the receiver405ofFIG. 4, a phase detector801, a data pattern filter802, and a DFE803with correction are added. The phase detector801receives input of the output data427from the ADC410and output data811from the DFE411, detects whether the phase advances or delays, and outputs a phase detection result812. The data pattern filter802receives the input of the phase detection result812from the phase detector801and the output data811from the DFE411, compares a data pattern sequence to be corrected and the output data811, and outputs either phase-advance correction data813or phase-delay correction data814according to the phase detection result812, when the data pattern sequence to be corrected and the output data811match. When the phase of the phase detection result812is detected to advance, the phase-delay correction data814becomes 0, when the phase of the phase detection result812is detected to lags, the phase-advance correction data813becomes 0, and when the phase detection result812shows that the phase of the phase does not advance or lag, both the phase-advance correction data813and the phase-delay correction data814become 0. In the DFE803with correction, the output data427from the ADC410, the phase detection result812from the phase detector801, the phase-advance correction data813, and the phase-delay correction data814are input, the correction data813and the correction data814are added to the ADC output data427for determination, and the receiver output data428is corrected and output. For example, when the PAM-4 is used, data is determined to be −3, −1, +1, or +3, and when a PAM-8 is used, data is determined to be −7, −5, −3, −1, +1, +3, 5, or +7.

FIG. 9illustrates an example of the phase detector801. A shift register901receives the input of the DFE output data811and generates a delayed data sequence921. The data sequence921is input to a data pattern detector902. The data pattern detector902detects a data pattern (for example, −1, −1, +1, +1) with a reducing ISI, sets a data pattern detection result922to high when the input data sequence921and the data pattern match, and outputs the data pattern detection result922as low when the delayed data sequence921and the data pattern do not match. A delay difference between the ADC output data427and a path passing through the shift register901and the data pattern detector902is adjusted by an N-clock delay line903, converted into an absolute value by an absolute value converter904, and becomes amplitude data923. The amplitude data923and data obtained by delaying the amplitude data923by a 1-clock delay line905are multiplied by the data pattern detection result922in a multiplier906and a multiplier907, respectively. The data pattern detection result922operates as an enable signal, and sets input data to 0 when the data pattern detection result922is not high. A moving averager908performs moving average on phase-advance-side amplitude data924which is an output from the multiplier906, and the phase-advance-side amplitude data924becomes phase-advance-side average amplitude data926. Similarly, a moving averager909performs moving average on phase-delay-side amplitude data925which is an output from the multiplier907, and the phase-delay-side amplitude data925becomes phase-delay-side average amplitude data927. Ranges of the number of data sets for performing the moving average of the moving averager908and the moving averager909have a fixed amount, and an averaging range may be adjusted by register setting or the like. The subtractor910subtracts the phase-delay average amplitude data927from the phase-advance-side average amplitude data926, and outputs an amplitude difference928. The amplitude difference928is input to a dead zone911, and an amplitude below a threshold is converted to 0. The threshold of the dead zone911is settable by a register or the like. A phase advance degree929, which is an output from the dead zone911, is input to a multi-value determiner912, and the phase advance degree929is determined. It is determined whether the input929is at least positive or negative, or 0. When the phase detection result812is positive, the phase is detected to advance, and when the phase detection result812is negative, the phase is detected to be delayed.

FIG. 10illustrates an example of the data pattern filter802. The shift register1001delays the output data811from the DFE411and outputs a data sequence1011. The data sequence1011requires a data sequence including at least five data sets. The data sequence1011is input to a phase-delay data pattern detector1003and a phase-advance data pattern detector1002, when the phase detection result812to be input is likewisely positive, only the phase-advance data pattern detector1002operates, and when the phase detection result812Is negative, only the phase-delay data pattern detector1003operates. Although the phase-advance data pattern detector1002and the phase-delay data pattern detector1003have different correction values to be output to an input data pattern, the operation principle is the same, and when an input matches a preset data pattern, a corresponding correction value is output. The phase-advance data pattern detector1002and the phase-delay data pattern detector1003each contain a lookup table, and store a correction value corresponding to an input data sequence. The correction value can be changed by changing a register value by using a program, or can be changed by using automatic convergence. The phase-advance correction data813is output from the phase-advance data pattern detector1002and the phase-delay correction data814is output from the phase-delay data pattern detector1003.

FIG. 11illustrates an example of the DFE803with correction. A delay amount of the ADC output data427is adjusted by an N-clock delay line1101, an adder1102applies a filter tap1127including tap-2 and subsequent taps to the ADC output data427, and the adder1102outputs a higher-order tap addition result1121. The higher-order tap addition result1121and tap-1 data1128are input to an adder1103and added to each other, and delayed by a 1-clock delay line1104, and then the 1-clock delay line1104outputs a DFE filter output1122. The DFE filter output1122is input to a differentiator1105, the differentiator1105calculates an amount of change relating to the DFE filter output1122, and a determiner1107receives input of the amount of change and determines a data transition polarity1123in phase delay. A multiplier1109receives the data transition polarity1123in phase delay and phase-delay correction data814delay-adjusted by an M-clock delay line1113, multiplies the data transition polarity1123and the phase-delay correction data814, and outputs a correction value1125in phase delay. The higher-order tap addition result1121is input to a differentiator1106, the differentiator1106calculates an amount of change relating to the higher-order tap addition result1121, a determiner1108determines the amount of change and outputs a data transition polarity1124in phase advance. A multiplier1110receives the data transition polarity1124in phase advance and phase-advance correction data813delay-adjusted by an M-clock delay line1114, multiplies the data transition polarity1124and the phase-advance correction data813, and outputs a correction value1126in phase advance. The DFE filter output1122, the correction value1125in phase delay, and the correction value1126in phase advance are input to an adder1111and added to each other to calculate a corrected signal, and a multi-value determiner1112determines the corrected signal and outputs the receiver output data428. For example, the multi-value determiner1112determines data as four values of −3, −1, +1, and +3 when PAM-4 is used, and determines data as eight values when PAM-8 is used. The receiver output data428is fed back and multiplied by a filter coefficient, and added to the input. A high order tap filter1117receives input of the receiver output data428, delays the receiver output data428internally and multiplies the receiver output data428by a tap coefficient, and outputs an output1127from a higher-order tap filter, that is, tap-2 to Tap-n. For tap-1, tap-1 coefficient data1129is output depending on the phase detection result812from a lookup table1115to which the phase detection result812is input. The multiplier1116receives input of the receiver output data428and the tap-1 coefficient data1129, multiplies the receiver output data428and the tap-1 coefficient data1129, and outputs the tap-1 data1128. Then, the tap-1 data1128is added to an input.

FIG. 12illustrates bathtub curves showing bit error rates (BER) representing effects of using the present invention. A BER using the present invention (corrected) and a BER not using the present invention (not corrected). In the example ofFIG. 12, an EYE width which is error free is improved by 0.15 UI, effectively improving the EYE width.

Second Embodiment

When there is a bit error in the DFE, the influences of the errors, the number of which is equal to the number of taps of the DFE, disadvantageously remain. For this reason, in the DFE that is not corrected in the first embodiment, the influences remain, and there is a possibility that all the data to be compared with the data pattern filter may be data with errors, and there is a possibility of erroneous correction.

Therefore, in the second embodiment, a higher-order tap of the DFE inputs corrected data so as not to transfer an error as much as possible. Therefore, correction is also applied to an unnecessary data pattern to prevent correct data from being converted to wrong data.

FIG. 13illustrates the second embodiment. An output428from the DFE803with correction is input to a DFE1301, and replace the output428with data that is fed back in the DFE1301. The output428from the DFE803with correction is also input to a data pattern filter1302, and the data is partially changed to corrected data.

FIG. 14illustrates an example of the DFE1301. InFIG. 14, it is assumed that an N-tap DFE and the data pattern filter1302filter data to be corrected by using L previous data patterns. In the DFE1301, ADC output427is input, and the ADC output data427is added to a higher-order tap signal1414obtained by delaying an output428from the DFE with correction and multiplying the output428by a tap coefficient in a higher-order tap block1405, in the adder1401. An output1411from the adder1401is added to a lower-order tap signal obtained by delaying a DFE output811and multiplying the DFE output811by a tap coefficient in the adder1402, in a lower-order tap block1404. An output1412from the adder1402is determined by a decision unit1403. A PAM-4 signal is determined as four values, and a PAM-8 signal is determined as eight values.

FIG. 15illustrates an example of the data pattern filter1302. The data pattern filter1302includes two shift registers for generating delayed data sequences, data with less delay uses a delayed DFE output811, and data with more delay uses a delayed output428from the DFE with correction. A shift register1501receives input of a DFE output811and outputs a maximum of L delayed data sequences1511. Here, the number L is the same as the number L inFIG. 14. The shift register1502receives input of the output428from the DFE with correction, and outputs a delayed data sequence1512. The delayed data sequences1511and the delayed data sequence1512are collected into one bus line and become a delayed data sequence1513. The delayed data sequence1513is input to the phase-advance data pattern detector1002and the phase-delay data pattern detector1003, and whether the delayed data sequence1513and a data pattern match is detected.

Third Embodiment

As a third embodiment,FIG. 16illustrates a receiver in which an output811from the DFE411is added to a DFE1601with correction. InFIG. 16, a value calculated from the DFE output811is compared with a value of an ADC output427, and when a difference between the values is small, correction is not applied. In the embodiments described above, since it is expected that correction is necessary from a wrong data sequence and correction is made, there is a possibility of applying a correction and causing a mistake even if data is not wrong. Therefore, when a difference between a value calculated from the DFE output811and the ADC output427is small, no correction is applied assuming that no data error is made, thereby making it possible to suppress the correction more than necessary.

FIG. 17illustrates an example of the DFE1601with correction at that time. The DFE1601is basically the same as the DFE803with correction inFIG. 11, and a correction control circuit is added. The correction control circuit has the following configuration. A DFE output811is delay-adjusted by a delay line1701and multiplied by amplitude data corresponding to data determined by an amplitude converter1702. a subtractor1703obtains a difference between the DFE output811and a DFE filter result1122, converted into an absolute value by an absolute value converter1704, compared with a threshold set by a comparator or the like by a comparator1705, and converted to a correction control signal1708. The correction control signal1708less than the threshold represents 0, and the correction control signal1708more than the threshold represents 1. The correction control signal1708is multiplied by a correction value1125in phase delay in a multiplier1706, and the correction control signal1708is multiplied by a correction value1126in a multiplier1707. Each correction control signal1708is added to the DFE filter result1122in the adder1111. That is, when a difference between the DFE filter result1122and the DFE output811which is returned to data before the determination is small, it is determined that no data error occurs, and the correction value is set to 0 so that no correction is applied.

REFERENCE SIGNS LIST

101internal board102semiconductor integrated device for signal processing103semiconductor integrated device for communication104connector201internal board202internal transmission line203internal board204semiconductor integrated device for signal processing205repeater206repeater207semiconductor integrated device for communication208connector209connector210connector301internal board302internal transmission line303internal board304connector305connector401semiconductor integrated device402transmission line303semiconductor integrated device404transmitter405receiver406signal processing unit407multiplexer408PLL (Phase Locked Loop)409FFE (Feed Forward Equalizer)410CTLE (Continuous Linear Equalizer)411ADC (Analog to Digital Converter)412DFE (Decision Feedback Equalizer)413PLL (Phase Locked Loop)414CDR (Clock and Data Recovery)415signal processing unit421transmission signal parallel data422transmitter clock423transmission signal serial data424output from transmitter425input to receiver426CTLE output signal427ADC output data428receiver output data429output clock from receiver PLL430receiver clock501determination threshold502determination threshold503determination threshold504upper EYE width505lower EYE width601data sampling timing two clocks before current data sampling timing when there is no timing difference602data sampling timing one clock before current data sampling timing when there is no timing difference603data sampling timing without timing difference604data sampling timing two clocks before current data sampling timing when there is clock phase delay605data sampling timing one clock before current data sampling timing when there is clock phase delay606data sampling timing when there is clock phase delay607+3/+1 data determination threshold608+1/−1 data determination threshold609−1/−3 data determination threshold610received-data transition direction611correction direction701data sampling timing two clocks before current data sampling timing when there is no timing difference702data sampling timing one clock before current data sampling timing when there is no timing difference703data sampling timing without timing difference704data sampling timing two clocks before current data sampling timing when there is clock phase advance705data sampling timing one clock before current data sampling timing when there is clock phase advance706data sampling timing when there is clock phase advance707+3/+1 data determination threshold708+1/−1 data determination threshold709−1/−3 data determination threshold710received-data transition direction711correction direction801phase detector802data pattern filter803DFE with correction811DFE output data812phase detection result813phase-advance correction data814phase-delay correction data901shift register902data pattern filter903N-clock delay line904absolute value converter9051-clock delay line906multiplier907multiplier908moving averager909moving averager910subtractor911dead zone912multi-value determiner921delayed data sequence922data pattern detection result923amplitude data924phase-advance-side amplitude data925phase-delay-side amplitude data926phase-advance-side average amplitude data927phase-delay-side average amplitude data928amplitude difference929phase advance degree1001shift register1002phase-advance data pattern detector1003phase-delay data pattern detector1011delayed data sequence1101N-clock data delay line1102adder1103adder11041-clock delay line1105differentiator1106differentiator11070/1 determiner11080/1 determiner1109multiplier1110multiplier1111adder1112multi-value determiner1113M-clock data delay line1114M-clock data delay line1115lookup table1116multiplier1117higher-order tap filter1121higher-order tap addition result1122DFE filter result1123data transition polarity in phase delay1124data transition polarity in phase advance1125correction value when there is phase delay1126correction value in phase advance1127output from higher-order tap filter1128tap-1 data1129tap-1 coefficient data1301DFE for correction data input1302data pattern filter using correction data1401adder1402adder1403multi-value determiner1404low-order tap filter1405higher-order tap filter1411higher-order tap addition result1412DFE filter result1413output from low-order tap filter1414output from higher-order tap filter1501shift register1502shift register1511delayed data sequence1512delayed data sequence after correction1513delayed data sequence to which corrected data is added1601DFE with correction1701delay line1702amplitude converter1703subtractor1704absolute value converter1705comparator1706multiplier1707multiplier1708correction control signal