Active rectifying apparatus

A semiconductor apparatus includes: a first transistor; a second transistor having a higher withstand voltage than the first transistor, a source of the second transistor coupled to a drain of the first transistor, a gate of the second transistor coupled to a source of the first transistor; a third transistor having a higher withstand voltage than the first transistor and a drain of the third transistor coupled to a drain of the second transistor; and a comparator that compares a source voltage of the first transistor with a source voltage of the third transistor, and controls a gate voltage of the first transistor.

BACKGROUND

The embodiments discussed herein relate to a semiconductor apparatus.

2. Description of Related Art

A rectifier device includes a diode in which a p-type semiconductor and a n-type semiconductor are joined. A diode, which requires a forward voltage of, for example, 0.7 V, may have a large power loss.

A related technology is disclosed in, for example, Japanese Laid-open Patent Publication No. H7-297699.

SUMMARY

According to one aspect of the embodiments, a semiconductor apparatus includes: a first transistor; a second transistor having a higher withstand voltage than the first transistor, a source of the second transistor coupled to a drain of the first transistor, a gate of the second transistor coupled to a source of the first transistor; a third transistor having a higher withstand voltage than the first transistor and a drain of the third transistor coupled to a drain of the second transistor; and a comparator that compares a source voltage of the first transistor with a source voltage of the third transistor, and controls a voltage of a gate of the first transistor.

DESCRIPTION OF EMBODIMENTS

Power consumption may be reduced by detecting the voltage between the terminals of a diode and short-circuiting the terminals of the diode using a switch during forward conduction.

FIG. 1illustrates an exemplary semiconductor apparatus. The semiconductor apparatus illustrated inFIG. 1includes transistors Q1, Q2, and Q3, a comparator10, a diode D1, and a capacitor C1.FIG. 2illustrates exemplary characteristics of transistors. Referring toFIG. 2, the transistor Q1may be a normally-off enhancement transistor, and the transistors Q2and Q3may be normally-on depletion mode transistors. The transistors Q2and Q3may be high-voltage (several hundreds to a thousand volts, for example) transistors, in comparison with the transistor Q1. For example, the transistor Q1may by an n-channel silicon MOSFET, and the transistors Q2and Q3may be high electron mobility transistors (HEMTs) including a wide band gap semiconductor such as gallium nitride (GaN). The comparator10includes a non-inverting input terminal and an inverting input terminal. The comparator10outputs a low level when a voltage applied to the inverting input terminal is higher than a voltage applied to the non-inverting input terminal and outputs a high level when a voltage applied to the inverting input terminal is lower than a voltage applied to the non-inverting input terminal.

The source of the transistor Q2is coupled to the drain of the transistor Q1, the gate of the transistor Q2is coupled to the source of the transistor Q1, and the drain of the transistor Q2corresponds to a cathode K. The drain and gate of the transistor Q3are respectively coupled to the drain and gate of the transistor Q2, and the source of the transistor Q3is coupled to the anode of the diode D1and the inverting input terminal of the comparator10. The cathode of the diode D1is coupled to the power input terminal of the comparator10and the capacitor C1. The source of the transistor Q1is coupled to the back gate, the power input terminal of the comparator10, the non-inverting input terminal of the comparator10, and the capacitor C1, and may correspond to an anode A. The output terminal of the comparator10is coupled to the gate of the transistor Q1.

The semiconductor apparatus illustrated inFIG. 1performs a rectifying operation. For example, the semiconductor apparatus decreases or blocks a current that flows when a higher voltage is applied to the cathode K side, and passes a current therethrough when a higher voltage is applied to the anode A side. The anode A may be the ground. When a high positive voltage is applied to the cathode K, the source voltages of the depletion mode transistors Q2and Q3increase, and the transistors Q2and Q3operate so as not to pass drain currents ID therethrough. Referring toFIG. 2, when the transistors Q2and Q3have a negative threshold voltage Vth1and the drain currents ID are zero, the gate voltage of the transistors Q2and Q3is lower than the source voltage by the absolute value |Vth1| of the threshold voltage Vth1. Since the gates of the transistors Q2and Q3, which are coupled to the anode A, are at the ground level, a voltage having increased to the absolute value |Vth1| of the threshold voltage Vth1is generated at the sources of the transistors Q2and Q3. The capacitor C1is charged through the diode D1. Since a positive voltage is applied to the inverting input terminal of the comparator10, the output of the comparator10is at the ground level, whereby the transistor Q1turns off.

When a negative voltage is applied to the cathode K, the source voltage of the depletion mode transistors Q2and Q3becomes negative, and the transistors Q2and Q3operate so as to pass the drain currents ID therethrough. Since a negative voltage is applied to the inverting input terminal of the comparator10, the output of the comparator10becomes positive, whereby the transistor Q1turns on. A current for making the transistor Q1turn on is supplied from the capacitor C1, and the diode D1decreases or blocks a reverse current.

The semiconductor apparatus illustrated inFIG. 1may be a diode which allows a current to flow therethrough when a negative voltage is applied to the cathode K side. The transistors Q2and Q3may be high-voltage HEMTs, whereby a withstand voltage characteristic in reverse biasing is increased (high-voltage characteristic). In reverse biasing in which a high positive voltage is applied to the cathode K, a voltage generated at the sources of the transistors Q2and Q3may be a voltage which has increased up to the absolute value |Vth1| of the threshold voltage Vth1, for example, 2 to 3 V. The transistor Q1may be a low-voltage silicon MOSFET, whereby the on-resistance may be decreased. The resistance during forward biasing is lowered and power loss is decreased. Further, since minor carriers are not used, high-speed operation and high-frequency rectification may be performed.

The source of the transistor Q2may be input to the comparator10when the transistor Q3is not provided. For instance, inFIG. 1, when the source of the transistor Q2is input to the comparator10, if the on-resistance of the transistor Q1is small, the voltage input to the respective input terminals of the comparator10become close to each other, whereby the operation of the comparator10may become unstable. The operation of the comparator10is stabilized by the transistor Q3for monitoring. A current of, for example, 100 A may flow through the transistor Q2. A current flowing through the transistor Q3is smaller than that of the transistor Q2. Hence, the size of the transistor Q3may be smaller than that of the transistor Q2, whereby the chip size may be reduced.

When a high positive voltage is applied to the cathode K, the capacitor C1is charged, and when a negative voltage is applied to the cathode K, the diode D1decreases or blocks a reverse current, whereby electric charges are supplied to the comparator10from the capacitor C1. Consequently, when an input to the anode A and the cathode K is an AC input in which positive and negative currents are alternately repeated, self-sufficient operations are performed even though a power supply for the comparator10is not provided.

FIG. 3illustrates an exemplary semiconductor apparatus. In the semiconductor apparatus illustrated inFIG. 3, the diode D1of the semiconductor apparatus illustrated inFIG. 1may be replaced by a transistor Q4. The transistor Q4may be, for example, a p-channel silicon MOSFET. The drain of the transistor Q4is coupled the source of the transistor Q3, the source of the transistor Q4is coupled to the power input terminal of the comparator10and the capacitor C1, and the gate of the transistor Q4is coupled to the output terminal of the comparator10.

When the anode A is at the ground level, if a high positive voltage is applied to the cathode K, the output level of the comparator10becomes the ground level, whereby the transistor Q4turns on. When a negative voltage is applied to the cathode K, the output of the comparator10becomes positive, whereby the transistor Q4turns off. The transistor Q4illustrated inFIG. 3may have a function substantially the same as or similar to the function of the diode D1illustrated inFIG. 1. Since the transistor Q4is used instead of the diode D1, the forward voltage drop caused by the diode D1is decreased. Hence, the voltage generated at the source of the transistor Q3may be utilized as a power source for the comparator10without a loss.

FIG. 4illustrates an exemplary semiconductor apparatus. In the semiconductor apparatus illustrated inFIG. 4, the gate of the transistor Q3is coupled to the source of the transistor Q2. Since the gate of the transistor Q3is coupled to the source of the transistor Q2, when a high positive voltage is applied to the cathode K and the capacitor C1is charged, a voltage having increased to twice the absolute value |Vth1| of the threshold voltage Vth1is generated at the source of the transistor Q3with the anode A being the reference voltage. In the semiconductor apparatus illustrated inFIG. 4, a sufficient voltage for the comparator10is ensured, whereby the capability of driving the transistor Q1is improved.

FIG. 5illustrates an exemplary diode bridge rectifying circuit that performs a full-wave rectification, with the diode being incorporated in the bridge circuit. Referring toFIG. 5, during the positive half cycle of an AC power supply output, diodes D30and D20conduct, and a current flows through the diode D30, a load R10, and the diode D20. During the negative half cycle of the AC power supply output, diodes D10and D40conduct, and a current flows through the diode D10, the load R10, and the diode D40. A capacitor C10smoothes the voltage. A DC current to be applied to the load R10is obtained from the AC power supply.

The semiconductor apparatuses illustrated inFIGS. 1,3, and4have a function of a diode, and may operate self-sufficiently without being supplied with power. The semiconductor apparatuses illustrated inFIGS. 1,3, and4may be applied to the diodes D10to D40illustrated inFIG. 5. The diodes D10and D20or the diodes D30and D40may be turned on substantially at the same time, depending on the offset voltage of the comparator10, whereby a reverse current may flow.

FIG. 6illustrates an exemplary semiconductor apparatus. The negative terminal of a voltage source that supplies a voltage V1is coupled to the source of the transistor Q1. Resistors R1and R2are coupled in series between the positive terminal of the voltage source that supplies the voltage V1and the source of the transistor Q3. A comparator10may be used and the non-inverting input terminal of the comparator10is coupled to the source of the transistor Q1, the inverting input terminal is coupled to a divided voltage point between the resistors R1and R2. InFIG. 6, components which are substantially the same as those inFIG. 3are denoted by the same reference symbols, and the descriptions thereof may be omitted or reduced.

The anode A may be the ground. When the cathode K has a positive voltage with respect to the anode A, since a positive voltage is applied to the inverting input terminal of the comparator10, the comparator10turns off the transistor Q1. When a negative voltage is applied to the cathode K with respect to the anode A, the comparator10makes the inverting input terminal level the ground level similarly to the non-inverting input terminal. The voltage of the cathode K may be Vk, and a current may flow from the voltage source that supplies the voltage V1to the source of the transistor Q3through the resistors R1and R2. Since the current does not flow into the inverting input terminal of the comparator10, a current (V1−0)/R1flowing through the resistor R1is substantially equal to a current (0−Vk)/R2flowing through the resistor R2. Since (V1−0)/R1=(0−Vk)/R2, the voltage of the cathode Vk=−V1×R2/R1. Hence, when a negative voltage is applied to the cathode K with respect to the anode A, the comparator10turns on the transistor Q1such that the voltage of the cathode K becomes −V1×R2/R1, and the transistor Q1is turned off when the voltage of the cathode K exceeds −V1×R2/R1.

When the semiconductor apparatus illustrated inFIG. 6is applied in the diode bridge rectifying circuit illustrated inFIG. 5, the following configuration is employed. That is, the semiconductor apparatuses illustrated inFIG. 6are respectively provided between four nodes of the diode bridge rectifying circuit.

The semiconductor apparatus illustrated inFIG. 6may not be turned on unless the voltage of the cathode K becomes negative with respect to the anode A. For example, in the diode bridge illustrated inFIG. 5, the diode D10and the diode D20, or the diode D30and the diode D40may not be turned on substantially at the same time.

FIG. 7illustrates an exemplary drive circuit. The drive circuit illustrated inFIG. 7may be a drive circuit for a three-phase motor. Insulated gate bipolar transistors (IGBTs) are coupled such that a high voltage V10or the ground voltage is applied to each of the U-phase, V-phase, and W-phase. Voltages V11to V16are applied to respective control terminals IGBT1to IGBT6with pulse width modulation (PWM) control, whereby the rotational speed of a motor M is controlled. Diodes D11to D16may be arranged in parallel with each of the IGBT1to IGBT6.

When the IGBT is turned off, since the rotating motor M works as a generator, a current flows in a direction opposite to the direction at the time when the IGBT is turned on. While the IGBT is off, a current may not flow from an emitter E to a collector C. Hence, referring toFIG. 8, for example, a diode D having substantially the same current capacity as the IGBT may be arranged in parallel with each of the IGBTs.

FIG. 9illustrates an exemplary semiconductor apparatus. The semiconductor apparatus illustrated inFIG. 9may correspond to the parallel connection of an IGBT and a diode illustrated inFIG. 8. The power input terminals of a comparator20are respectively coupled in common with those of the comparator10. The negative terminal of a voltage source that supplies a voltage V2is coupled to the source of the transistor Q1. The inverting input terminal of the comparator20is coupled to the positive terminal of the voltage supply that supplies the voltage V2. The non-inverting input terminal may be a control terminal CONT through which a control signal is input. The output terminal of the comparator20is coupled to the non-inverting input terminal of the comparator10. Other elements may be substantially the same as those inFIG. 6. In the semiconductor apparatus illustrated inFIG. 9, elements that are substantially the same as those inFIG. 6are denoted by the same reference symbols, and the descriptions thereof may be omitted or reduced.

When a control signal input through the control terminal CONT is at a low level, the output of the comparator20is at the voltage level of a collector E. Hence, the semiconductor apparatus illustrated inFIG. 9operates as a diode similarly to the semiconductor apparatus illustrated inFIG. 6. When the control signal input through the control terminal CONT is at a high level, the output level of the comparator20becomes high, whereby a high-level signal is applied to the non-inverting input terminal of the comparator10. Hence, the transistor Q1is turned on, and a collector C and the collector E conduct.

When the semiconductor apparatus illustrated inFIG. 9is applied in the drive circuit for the three-phase motor illustrated inFIG. 7, the following configuration is employed. The semiconductor apparatus illustrated inFIG. 9is abbreviated with a power semiconductor apparatus. That is, three series circuits, in each of which two power semiconductor apparatuses are coupled in series, are coupled in parallel (in bridge fashion across) between two terminals of a power supply with a high voltage V10. And, coils for each of the phases (U phase, V phase, W phase) of the three-phase motor are coupled at each of the coupling nodes between the two power semiconductor apparatuses in the three series circuits. Further, this drive circuit outputs a control signal (external control signal) to a control terminal Cont coupled to the non-inverting input terminals of the comparators20of these power semiconductor apparatuses. This power semiconductor apparatus may be applied not to a three-phase motor, but to motors with various multiple phases. In this case, a plurality of series circuits, in each of which two power semiconductor apparatuses are coupled in series, are coupled in parallel between two terminals of a power supply. And, each of coupling nodes between the two power semiconductor apparatuses in the plurality of series circuits are coupled to coils for each phase of a multiphase motor. Further, this multiphase motor driving circuit outputs control signals to the comparators20of these power semiconductor apparatuses.

Since the semiconductor apparatus illustrated inFIG. 9operates as a diode when the control signal input through the control terminal CONT is at a low level and conducts when the control signal CONT is at a high level, may operate, the semiconductor apparatus operates as a circuit in which the IGBT and diode illustrated inFIG. 8are coupled in parallel with one another. Referring toFIG. 8, a current flows through the IGBT or the diode in accordance with the direction of the flow. The IGBT and the diode D may have sizes in accordance with the permissible currents. As for the maximum applied voltage at the time when the IGBT is in an off state, the IGBT and the diode D may have substantially the same withstand voltage. In the semiconductor apparatus illustrated inFIG. 9, a high voltage is applied to the transistors Q2and Q3corresponding to high-voltage HEMTs, and a low voltage is applied to the transistor Q1. Since a current flows through the transistors Q1and Q2irrespective of the direction of the current, devices may be reduced in size. Compared with the circuit illustrated inFIG. 8, the semiconductor apparatus illustrated inFIG. 9has lower resistance, resulting in a reduction in heat radiation. When the semiconductor apparatus illustrated inFIG. 9is used to drive for the motor of a hybrid automobile, the heat radiation system may be simplified, leading to a reduction in weight and size.

FIG. 10is a circuit diagram illustrating an example of a power supply circuit, to explain a sixth embodiment. The power supply circuit1comprises a step-up switching regulator30, a capacitor C2which accumulates as charge a portion of the current output by the switching regulator30, and terminals T1and T2coupled to a load40.

The switching regulator30comprises a coil (inductor) L1, a terminal of which is coupled to a voltage source which supplies a voltage V20, a transistor Q5provided between another terminal of coil L1and a reference power supply (reference voltage), such as for example ground GND, and the coil L1, a diode D17the anode of which is coupled to a coupling node N1of the coil L1and transistor Q5, and a pulse generation circuit31which generates driving pulses for driving the transistor Q5.

The transistor Q5is for example an NMOS transistor; in the following explanation it is assumed that the transistor Q5is an NMOS transistor. The drain of the transistor Q5is coupled to the other end of the coil L1, and the source is coupled to ground GND. The pulse generation circuit31outputs in alternation a high-level conducting pulse to put the transistor Q5into the conducting state, and a low-level non-conducting pulse to put the transistor Q5into the non-conducting state. The coil L1receives current from the voltage source which supplies the voltage V20during conduction of the transistor Q5, accumulates magnetic energy, and discharges this accumulated magnetic energy as a current during non-conduction of the transistor Q5. The diode D17is a diode for rectification, the anode of which is coupled to the coupling node N1and the cathode of which is coupled to a coupling node N2.

FIG. 11explains operation of the power supply circuit1ofFIG. 10; illustrated in order from above are the driving pulse Dp output by the pulse generation circuit31, the transistor Q5on/off state, the voltage Vc at the coupling node N1, the diode D17on/off state, the current Ic flowing in the coil L1, the current Id flowing in the diode D17, and the current Iq flowing in the transistor Q5.

Below, operation of the power supply circuit1ofFIG. 10is explained, referring toFIG. 11. First, operation of the power supply circuit1in the interval from time X0to time X1inFIG. 11is explained. When the pulse generation circuit31outputs a high-level driving pulse Dp to the transistor Q5, the transistor Q5enters the on state (conducting state) due to this high-level driving pulse Dp. At this time, the voltage Vc at the coupling node N1is at ground level GND. Further, the output voltage Vout at the terminal T1is at a voltage higher than the voltage at the coupling node N1(ground level GND) due to charge accumulated on the capacitor C2. As a result, the diode D17is reverse-biased, and the diode D17enters the off state. Further, when the transistor Q5enters the on state, current flows to the coil L1from the voltage source supplying the voltage V20, and the coil L1accumulates magnetic energy. At this time the current Ic in the coil L1rises, and moreover the current Id becomes 0 A and the current Iq rises. While the transistor Q5is in the on state, that is, while the current Id is 0 A, the load40operates due to charge already accumulated on the capacitor C2.

Next, operation in the interval from time X1to time X2inFIG. 11is explained. When the pulse generation circuit31outputs a low-level driving pulse Dp to the transistor Q5, the transistor Q5enters the off state (non-conducting state) due to this low-level driving pulse Dp. Then, a reverse emf E′ occurs across the terminals of the coil L1. The voltage Vc at the coupling node N1at this time rises rapidly (voltage rise). If the voltage of the voltage V20is E and the reverse emf of the coil L1is E′, then the voltage Vc is “E+E′.”

Due to this rise of the voltage Vc, the diode D17enters the on state, and current begins to flow from the anode toward the cathode of the diode D17. As a result, the coil current Ic flows as the current Id, and the current Iq becomes 0 A. Then, the coil current Ic occurring due to the reverse emf E′ of the coil L1gradually declines, and the current Id also declines. At this time, the current Id accumulates as charge on the capacitor C2, and is supplied to the load40via the terminal T1. If the voltage of the voltage V20is E, the reverse emf of the coil L1is E′, and the forward-direction voltage drop across the diode D17is Vf, then the output voltage Vout is “E+E′−Vf.”

In this way, the pulse generation circuit31outputs high-level conducting pulses and low-level non-conducting pulses to the transistor Q5, and by this means causes the transistor Q5to repeatedly be conducting and non-conducting, supplies a current Id to the side of the output terminal T1by means of magnetic energy accumulated in the coil L1, and steps up the output voltage Vout to the voltage V20.

FIG. 12illustrates a circuit diagram of the power supply circuit2, in which the diode D17provided in the power supply circuit1ofFIG. 10is replaced with the semiconductor apparatus explained inFIG. 3. This replacement is to reduce power loss due to the forward-direction voltage drop across the diode D17. In the switching regulator30′ ofFIG. 12, the anode A of the semiconductor apparatus explained inFIG. 3is coupled to the coupling node N1, and the cathode K is coupled to the coupling node N2. Otherwise the configuration is similar to that of the power supply circuit1explained inFIG. 10, and so inFIG. 12, portions corresponding to portions inFIG. 10are assigned the same symbols, and explanations are omitted.

If the diode D17is replaced with the semiconductor apparatus ofFIG. 3in this way, when the semiconductor apparatus changes from the on state to the off state, a reverse current flows in the direction from the cathode K to the anode A. Then, this reverse current is absorbed by ground GND, and power for supply to the capacitor C2and load40is lost.

FIG. 13explains a reason for the flow of this reverse current; in order from above are the driving pulse Dp output by the pulse generation circuit31, the transistor Q5on/off state, the voltage Vc at the coupling node N1, the voltage Vcmpin applied to the inverting input terminal of the comparator10, the comparison signal CmpOut output by the comparator10, the transistor Q1on/off state, and the current Id.

First, operation of the power supply circuit2in the interval from time X0to time X1inFIG. 13is explained. When the pulse generation circuit31ofFIG. 12outputs a high-level driving pulse Dp to the transistor Q5, the transistor Q5enters the on state due to this high-level driving pulse Dp, and the voltage Vc at the coupling node N1goes to ground GND. Further, the voltage at the coupling node N2(output voltage Vout) is at a higher voltage than ground GND due to charge accumulated on the capacitor C2. That is, ground voltage is applied to the anode A coupled to the coupling node N1, and a higher voltage than ground GND is applied to the cathode K coupled to the coupling node N2.

Then, as explained inFIG. 1, the voltage Vcmpin corresponding to the threshold voltage Vth1of the transistors Q2and Q3is applied to the inverting input terminal of the comparator10ofFIG. 12. Because the voltage applied to the non-inverting input terminal (ground GND) is lower than the voltage Vcmpin applied to the inverting input terminal, the comparator10outputs a low-level comparison signal CmpOut.

However, the timing with which this low-level comparison signal CmpOut is output is not the same as the timing with which the voltage Vcmpin is applied to the inverting input terminal of the comparator10, but is slightly delayed, as indicated by the symbol DLY. This delay is a time delay of approximately several tens of nanoseconds. This delay necessarily occurs due to the characteristics of the comparator, which is an analog circuit, and shortening this delay is extremely difficult.

During this delay DLY, the comparator10continues to output the high-level comparison signal CmpOut as indicated inFIG. 13, and the transistor Q1remains in the on state. During this interval, a reverse current flows from the cathode K to the anode A. This reverse current is absorbed by ground GND, and as a result power for supply to the capacitor C2and load40is lost.

Although the reverse current flows for a very short interval of several tens of nanoseconds, the power loss due to this reverse current may not be neglected for the following reason. That is, with the increasing need at present to miniaturize power supply circuits mounted on electronic equipment, in order to achieve miniaturization of power supply circuits, the coil L1is miniaturized. In order to miniaturize the coil L1and moreover step up the input voltage to a prescribed output voltage, the frequency of driving pulses Dp generated by the pulse generation circuit31is raised, and the period of the driving pulses Dp is shortened. For this reason, the frequency of the driving pulses Dp is raised from hundreds of kHrz to several MHz, and the period of the driving pulses Dp is shortened. For example, if the frequency of the driving pulses Dp is 1 MHz, then the period of the driving pulses Dp is shortened to 1 μs.

If the frequency of driving pulses Dp is raised and the period shortened in this way, when in one period of the driving pulses Dp the transistor Q1switches from the on state to the off state, if a reverse current flows even for several tens of nanoseconds and power loss occurs in one period of the driving pulses Dp, the total power loss due to reverse currents during the interval in which the power supply circuit is operating becomes too large to ignore. Hence in the sixth embodiment, a semiconductor apparatus inFIG. 3was added to the technical means to reliably reduce this reverse current.

FIG. 14illustrates the circuit diagram of the sixth embodiment. In the sixth embodiment, a logic circuit, such as an AND circuit50, is provided between the comparator10and the gate of the transistor Q1. The logic circuit changes the comparison signal (control signal) CmpOut output by the comparator10from a first level for conducting transistor Q1into a second level for non-conducting transistor Q1, in response to an external control signal Ctrl input to the control terminal Cont from an external circuit, in order to reduce flow of the above-described reverse current. The first level is a high level at which the transistor Q1is conducting, and the second level is a low level at which the transistor Q1is non-conducting.

The AND circuit50takes as inputs the comparison signal CmpOut from the comparator10and the control signal Ctrl from the control terminal Cont, takes the logical product of the voltage of the comparison signal CmpOut and the voltage of the control signal Ctrl, and outputs the result, as an output signal AndOut, to the gate of the transistor Q1. The power necessary for operation of the AND circuit50is supplied from the capacitor C1, as explained inFIG. 1. Otherwise the configuration is similar to that of the semiconductor apparatus explained inFIG. 3, and so inFIG. 14, portions corresponding to portions inFIG. 3are assigned the same symbols, and explanations are omitted. The above-described logic circuit may be added to the semiconductor apparatus ofFIG. 1,FIG. 4or similar, instead of to the semiconductor apparatus ofFIG. 3.

FIG. 15is a circuit diagram of a power supply circuit5, illustrating a configuration in which the semiconductor apparatus (high-withstand voltage diode) ofFIG. 3in the power supply circuit2ofFIG. 12is replaced with the semiconductor apparatus ofFIG. 14. In the switching regulator60of the power supply circuit5, the semiconductor apparatus ofFIG. 14is provided between an output terminal T1and the coupling node N1. That is the anode A of the semiconductor apparatus ofFIG. 14is coupled to the coupling node N1, the cathode K is coupled to the coupling node N2, and inverted pulses of the driving pulses Dp of the pulse generation circuit31are input, via a level converter33, to the control terminal Cont.

Further, the power supply circuit5ofFIG. 15comprises, in addition to the configuration of the power supply circuit2ofFIG. 12, an inverter32which outputs to a level converter33inverted pulses Inv obtained by inverting the driving pulses Dp generated by the pulse generation circuit31, and the level converter33which converts (raises) the voltage level of the inverted pulses Inv and outputs the result, as a external control signal Ctrl, to the control terminal Cont. That is, the external control signal Ctrl is generated based on the driving pulses Dp. The external control signal Ctrl is input to the semiconductor apparatus AND circuit50(logic circuit) ofFIG. 14.

The reason for providing the level converter33is explained below. The comparator10operates by means of charge stored on the capacitor C1and outputs the comparison signal CmpOut, but the voltage level of this comparison signal CmpOut is higher than the voltage level of the driving pulses Dp generated by the pulse generation circuit31. Hence the level converter33raises the voltage level of inverted pulses Inv of the driving pulses Dp and outputs the result as the control signal Ctrl to the AND circuit50. By this means, the AND circuit50may take the logical product of the voltage of the comparison signal CmpOut and the voltage of the control signal Ctrl. Further, a voltage from the voltage source which supplies the voltage V20is supplied to the inverter32, and a voltage from for example a voltage source, not illustrated, is supplied to the level converter33. Otherwise the configuration is similar to that of the power supply circuit1explained inFIG. 10, and so inFIG. 15, portions which are the same as corresponding portions inFIG. 10are assigned the same symbols, and explanations are omitted.

FIG. 16explains operation of the power supply circuit5ofFIG. 15; illustrated in order from above are the driving pulse Dp output by the pulse generation circuit31, the transistor Q5on/off state, the voltage Vc at the coupling node N1, the voltage Vcmpin applied to the inverting input terminal of the comparator10, the comparison signal CmpOut output by the comparator10, the control signal Ctrl, the output signal AndOut of the AND circuit50, and the transistor Q1on/off state.

Below, operation of the power supply circuit5ofFIG. 15is explained referring toFIG. 16. First, operation of the power supply circuit5in the interval from time X0to time X1inFIG. 16is explained. As explained inFIG. 13, when the pulse generation circuit31outputs a high-level driving pulse Dp to the transistor Q5, after a delay DLY from the timing with which a voltage Vcmpin corresponding to the threshold voltage Vth1of the transistor Q3is applied to the inverting input terminal of the comparator10, the comparator10outputs a low-level comparison signal CmpOut to the AND circuit50. However, a low-level external control signal Ctrl, which is the inverted pulse of the high-level driving pulse Dp, is input to the AND circuit50with the timing of the output by the pulse generation circuit31of the high-level driving pulse Dp to the transistor Q5.

The AND circuit50takes the logical product of the voltage of the comparison signal CmpOut and the (low-level) voltage of the control signal Ctrl, and outputs a low-level output signal AndOut to the gate of the transistor Q1. As a result, at the delay time DLY the transistor Q1enters the off state, so that flow of a reverse current from the cathode K toward the anode A, described above, may be reduced.

In this way, the transistor Q1is forced into the off state based on a control signal from an external circuit, so that a reverse current which flows when the semiconductor apparatus functioning as a rectifying element switches from the on state to the off state may be reduced.

Next, operation in the interval from time X1to time X2inFIG. 16is explained. In this case also, as explained inFIG. 11, when the pulse generation circuit31outputs a low-level driving pulse Dp to the transistor Q5, the transistor Q5enters the off state (non-conducting state) due to the low-level driving pulse Dp, and the voltage Vc rises. Then, the voltage of the cathode K of the semiconductor apparatus ofFIG. 15declines relative to the anode A. As a result, as explained inFIG. 1, a negative voltage Vcmpin is applied to the inverting input terminal of the comparator10ofFIG. 15, and the comparator10outputs a high-level comparison signal CmpOut to the AND circuit50. Further, a high-level external control signal Ctrl, which is the inverted pulse of the low-level driving pulse Dp, is input to the AND circuit50with the timing of the output by the pulse generation circuit31of the low-level driving pulse Dp to the transistor Q5.

And, the AND circuit50outputs the high-level output signal AndOut to the gate of the transistor Q1. Then the transistor Q1enters the on state, and the current Id flows in the load40. The time over which the transistor Q1is in the on state is shortened by the delay time DLY, but as explained above, this shortened time is short, approximately several tens of nanoseconds, and so instability in the power supplied to the load40is avoided.

A high-voltage and low-resistance diode and a high-voltage and low-resistance switch may be provided by cascading the high-voltage transistor Q2and the low-voltage transistor Q1.

For example, the transistors Q2and Q3may be HEMTs corresponding to a wide band gap semiconductor such as gallium nitride (GaN) or may be other depletion mode transistors having a high-voltage characteristic.

Further, the comparator10,20may be an operational amplifier (op-amp). For example, the comparators10in the fourth embodiment and fifth embodiment may be op-amps.

By means of the disclosed embodiments, a transistor with a high withstand voltage and a transistor with a low withstand voltage may be combined to realize a diode and switch with high withstand voltage and low resistance.

In the semiconductor apparatus illustrated inFIG. 4, the source voltages of monitoring transistors Q3coupled in multiple stages may be adjusted.