Fabrication method using angled deposition and shadow walls

A method of fabricating a device, comprising forming portions of electronic circuitry and a shadow wall structure over a substrate, and subsequently depositing a conducting layer over the substrate by angled deposition of a conducting material in at least a first deposition direction at an acute angle relative to the plane of the substrate. The shadow wall structure is arranged to cast a shadow in the deposition, leaving areas where the conducting material is not deposited. The shadow wall structure comprises one or more gaps each shorter than a shadow length of a respective part of the shadow wall structure casting the shadow into the gap, to prevent the conducting material forming in the gaps and to thereby create regions of said upper conducting layer that are electrically isolated from one another. These are arranged to form conducting elements for applying signals to, and/or receiving signals from, the electronic circuitry.

CROSS REFERENCE TO RELATED APPLICATIONS

This is the U.S. National Stage of International Application No. PCT/US2019/018284, filed Feb. 15, 2019, which was published in English under PCT Article 21(2), and which is incorporated by reference herein in its entirety.

TECHNICAL FIELD

The disclosure relates to the formation of an electrically conducting layer by means of angled deposition, using shadow walls so as to leave shadowed areas where the conducting material is not deposited. The disclosed techniques have an example application in the fabrication of quantum computing devices comprising semiconductor-superconductor nanowires, or indeed other nanofabrication applications.

BACKGROUND

Topological quantum computing is based on the phenomenon whereby non-abelian anyons, in the form of “Majorana zero modes” (MZMs), can be formed in regions where a semiconductor is coupled to a superconductor. A non-abelian anyon is a type of quasiparticle, meaning not a particle per se, but an excitation in an electron liquid that behaves at least partially like a particle. An MZM is a particular bound state of such quasiparticles. Under certain conditions, these states can be formed close to the semiconductor-superconductor interface in a nanowire formed from a length of semiconductor coated with a superconductor. When MZMs are induced in the nanowire, it is said to be in the “topological regime”. To induce this requires the application of a magnetic field to the nanowire, and also cooling of the nanowire to a temperature that induces superconducting behaviour in the superconductor material. It may also involve gating a part of the nanowire by applying a variation in an electrostatic potential.

By forming a network of such nanowires and inducing MZMs in parts of the network, it is possible to create a quantum bit (qubit) which can be manipulated for the purpose of quantum computing. A quantum bit, or qubit, is an element upon which a measurement with two possible outcomes can be performed, but which at any given time (when not being measured) can in fact be in a quantum superposition of the two states corresponding to the different outcomes.

SUMMARY

Conventionally, the fabrication process involves one or more “post-fabrication” steps after the formation of the nanowires in order to form related electrically conducting elements such as gates, leads and bond pads. This post-fabrication typically involves etching or lithography. However, the performance of semiconductor nanowire devices is prone to detrimental effects related to adsorbates and surface potential fluctuations. Standard lithography and other post-fabrication steps that are usually performed to create complex nanoelectronics devices can be harmful to the device performance. It would be desirable to create a process flow that involves as few steps as possible after the semiconducting nanowires have been introduced on the target device wafer, ideally circumventing electron-beam resists and physical or wet-chemical etching steps altogether.

Similar considerations could also apply to the fabrication of other types of semiconductor, quantum or electronic devices, where it may be also be desirable to reduce or even eliminate potentially damaging post-fabrication steps that would otherwise follow the formation of the active structures of the device themselves in order to form electrical contacts and the like. Other such example applications may include other types of quantum devices such as SIS junctions, SIN junctions, and SQUIDS; spintronic devices such as spin transistors, spin-based storage elements or spin-based sensing elements; or conventional semiconductor electronic devices.

According to a first aspect of the present disclosure, there is provided method of fabricating a device, comprising: forming portions of circuitry and a shadow wall structure over a substrate, and subsequently depositing an upper conducting layer over the substrate by angled deposition of a conductor such as a metal. E.g. this may be performed using vapour deposition. The angled deposition is performed in at least one deposition direction at an acute angle of elevation relative to the plane of the substrate, wherein the shadow wall structure is arranged to cast a shadow in the deposition process, leaving areas where the conductor is not deposited. The shadow wall structure comprises one or more gaps each shorter than the shadow length of the respective part of the shadow wall structure which casts the shadow into the gap, so as to prevent the conductor forming in the gaps during the deposition, and to thereby create regions of said upper conducting layer that are electrically isolated from one another. These electrically isolated regions are arranged to form conducting elements such as terminals and/or leads for applying signals to, and/or receiving signals from, one or more components of the electronic circuitry. For instance these components may comprise one or more semiconductor-superconductor nanowires, e.g. arranged to form a qubit. The conducting elements may be used e.g. to create gates for gating these nanowires, or bond pads for connecting leads for reading out the qubits, or internal conducting lines for connecting between components in the semiconductor layer, etc.

The shadow length is the extent, in the plane of the substrate in the direction of the deposition beam, of the shadow that would be cast by the respective part of the wall, given its height and the direction of deposition, if the shadow was not interrupted by the part of the wall structure on the other side of the gap. The fact that the gaps are shorter than the shadow length means that the metal is not deposited onto the underlying layer or substrate (the “floor” of the gap) in the areas between the walls enclosing gaps, thus ensuring electrical isolation. This technique can be used to form electrically conducting circuit elements such as bond pads, conducting lines and/or gates, and can thus reduce or even eliminate the need for damaging post-fabrication steps such as etching and lithography for this purpose. In some embodiments no etching or lithography steps are used to form any upper conducting layers after the formation of the semiconductor layer. In the case of semiconductor-superconductor nanowires, the conducting elements such as contacts and gates may be formed in the same deposition step (or one or more of the same deposition steps) as the superconductor coating of the nanowires.

According to a second aspect of the present disclosure, there may be provided a method of angled deposition comprising forming a vertical template perpendicular to a substrate. The vertical template comprises one or more holes, corresponding to one or more areas in the plane of the substrate over which said deposition is to be performed, given a direction of deposition at an acute angle relative to the plane of the substrate. The method then comprises depositing a material (e.g. a conductor such as a metal) through the one or more holes in said direction at said angle, thereby depositing the material over said one or more areas. The template may be placed around one or more sides of the substrate, to allow for deposition from one or more directions. The template may be left in place or removed when the device is capped.

The first and second aspects may be used together or independently. Any features disclosed or claimed in relation to the first aspect may optionally be used in conjunction with the second aspect and vice versa.

According to another aspect disclosed herein there is provided a device fabricated by the method of any embodiment of the first or second aspect.

DETAILED DESCRIPTION OF EMBODIMENTS

Embodiments disclosed herein provide a device design and fabrication flow for producing devices such as Majorana devices comprising semiconductor-superconductor nanowires, or other hybrid superconductor-semiconductor devices. The flow reduces or even eliminates the need to perform any fabrication steps after the deposition or growth of the nanowire(s) and angled evaporation of the metal on the nanowires. The semiconductor (e.g. nanowire cores) may be grown for example by selective area growth (SAG) or vapour-liquid-solid (VLS) growth. However, conventional etching or lithography that are traditionally used to define structured electrical contacts and other such conducting elements after semiconductor growth and subsequent metal deposition can damage the underlying structure. Thus reducing or eliminating such steps will increase the performance of such devices. The disclosed fabrication flow generates devices that include elements such as gates, leads, high-quality dielectric, and/or pads for bonding, etc. After the growth or deposition of the nanowire core, metal is deposited to create the semiconductor-superconductor hybrid needed for the qubits (this step is always needed). This metal needs to be selectively deposited only in some areas of the nanowire. To create this selective deposition, one could perform blanket metallic deposition and then locally etch the metal where not wanted, but this is an example of a fabrication step that will damage the device. Embodiments disclosed herein solve the problem of etching, fabricating gates and contacts, thus eliminating every fabrication step after the metal deposition.

In a first aspect, the solution utilizes a unique design of shadow walls with specially formed gaps in between that allow for electrical isolation of contacts to the wire and prevent the occurrence of shorts that would otherwise be created by angled blanket deposition of metals. Preferably the walls form “pockets” or enclosures in the plane of the substrate, with one or more of the gaps in the walls of each pocket. Each pocket thus encloses its own respective isolated region. In a second aspect, which may be used together with the first aspect or independently, the flow uses metal deposition through a vertical hard mask template patterned with holes to prevent that large areas of the chip are shorted by a metal film.

As mentioned, the performance of semiconductor nanowires is prone to detrimental effects related to adsorbates and surface potential fluctuations, e.g. due to the intrinsically large surface-to-volume ratio. Standard lithography and other post-fabrication steps that are usually performed to create complex nanoelectronics devices (for instance hybrid semiconducting-superconducting devices that function as topological qubits) can be harmful to the device performance (e.g. due to low thermal budget). Post-fabrication is defined herein as any steps after the angled metal deposition (or more generally the angled deposition of the conducting material). It may comprise the series of cleanroom fabrication steps that would conventionally occur after either the wire growth in the case of SAG wires, or wire deposition on the substrate in case of VLS. It would be desirable to create a process flow that involves as few steps as possible after the semiconducting nanowires have been introduced on the target/device chip, ideally circumventing electron-beam resists and physical or wet-chemical etching steps altogether.

This problem is particularly (but not exclusively) relevant in hybrid semiconductor-superconductor structures where the semiconductor comprises InSb and the superconductor comprises Al. Since InSb/Al is a very delicate material combination, then heat, aging, etching, or other traditional fabrication processes can affect the material quality and the InSb/Al interface, generating inter-diffusion or defects and hindering Majorana signatures. Embodiments disclosed herein provide a device design and fabrication flow that shifts all device fabrication steps to prior to the growth or deposition of the InSb structure and subsequent metallization.

Stencil masks would be an alternative solution to obtain a device that requires no fabrication after metal deposition. However, stencil masks require very precise mechanical positioning of the mask, which requires the introduction of complex additional machinery in the deposition chamber. Further, for each new deposition a new stencil mask is required (typically multiple depositions are needed for a single device). The presently disclosed solution on the other hand uses selective deposition of shadow walls, e.g. by lithographic positioning of the walls, followed by angled deposition of the metal or other such conductor. This is both more accurate and easier.

Embodiments provide a design of shadow walls that includes pockets and gaps that allow to create multiple isolated structures (e.g. contact leads, gates, dielectrics, and/or mesoscopic metallic structures) using directional deposition. One benefit of this design for metallic deposition, or deposition of other conductors, is that these structures are not electrically shorted to each other or the outside environment, as would be the case when using angled blanket directional deposition without these designs.

Embodiments also provide a technique of metal directional deposition through a vertical hard mask template selectively patterned with holes to prevent that large areas of the chip are shorted by a metallic film. Moreover, this enables capping the device from the top via blanket deposition of a dielectric.

The following describes a fabrication flow which generates devices that include gates, leads, high-quality dielectrics, and pads for wire bonding. The flow is described in relation to the fabrication of a quantum computing device comprising a network of semiconductor-superconductor nanowires for forming MZM-based qubits. However more generally, the designs and fabrication flows presented herein may be used to create various different types of device without any post-fabrication steps. Such devices may include quantum devices such as semiconductor-insulator-semiconductor (SIS) junctions, semiconductor-insulator-normal (SIN) junctions, islands, superconducting quantum interference devices (SQUIDs), and/or superconducting flux/phase/charge qubits.

FIG.1Aillustrates an example device (or part thereof) formed in accordance with embodiments disclosed herein. The device comprises a wafer1comprising a substrate2and multiple layers formed over the substrate2. The multiple layers comprise at least a first layer4comprising patterned portions of electronic circuitry, and an upper conducting layer5comprising patterned portions of conductor. The first layer4may also be referred to as the active layer, in that this is where functional parts of the electronic components are formed (be they quantum components, spintronic components or traditional electronic components). In embodiments the first layer4comprises a semiconductor layer comprising patterned portions of semiconductor. For instance the semiconductor may be InSb or InAs. Examples herein may be described in terms of a semiconductor layer4, but this layer4may alternatively or additionally comprise one or more types of material such as a dielectric.

Note the term “circuitry” as used herein does not necessarily imply any particular kind of device, logic or electronic phenomenon unless stated otherwise. For instance it may refer to quantum devices based on any quantum phenomenon (e.g. MZMs, superconducting quantum interference, etc.); or spintronic circuitry (e.g. spin transistors, spin-based sensing or storage elements, etc.); or traditional electronics (e.g. transistors, diodes, capacitors, etc.). A “portion” of circuitry may refer to a single continuous element of material or multiple elements. A given portion may form a complete electronic component in its own right, or a constituent part of a component in conjunction with one or more elements in one or more upper and/or lower layers (e.g. an upper and/or lower conductor5,6).

The upper conductor5may be a superconducting metal such as Al. The semiconductor layer4is formed over the substrate2, e.g. by selective area growth (SAG) or vapour-liquid-solid (VLS) and subsequent deposition over the substrate2. Various fabrication techniques for forming semiconductor structures are, in themselves, known in the art. Subsequently the upper conducting layer5is formed over the semiconductor layer4. This is formed by means of an angled deposition technique performed in accordance with the teachings of the present disclosure. In embodiments the medium for the disposition is vapour deposition.

Optionally, in embodiments the wafer1may further comprise a bottom structure or lower structure3. This may comprise a lower conducting layer6, and/or a lower dielectric layer7. In embodiments the lower conducting layer6is formed over the substrate2and the lower dielectric layer7is subsequently formed over the lower conducting layer. In other embodiments, these lower layers6,7could be applied in the opposite order, and/or only one of these lower layers6,7may be present, and/or one or more other layers (not shown) may be included in the bottom structure. In embodiments the lower conducting layer6may comprise for example gold, tungsten or silver. The lower dielectric layer7may be formed from any suitable dielectric, e.g. SiO2or SiOx. Any suitable fabrication technique may be used to form these layers6,7such as vapour deposition or lithography. Various materials and fabrication techniques for forming conducting and dielectric layers6,7are, in themselves, known in the art.

The semiconductor layer4may comprise various functional electronic circuit portions. In embodiments these may comprise one or more quantum computing components used to form qubits or the like. E.g. the semiconductor layer4may comprise the semiconductor cores of a network of semiconductor-superconductor nanowires arranged to form MZM-based qubits.

FIG.1Bschematically illustrates an example structure that may be formed in the semiconductor and upper conducting layers4,5. Here the structure comprises a semiconductor-superconductor nanowire9, shown in cross section perpendicular to its axis inFIG.1B(i.e. with the length of the nanowire9running perpendicular to the page). The nanowire9comprises a length of semiconductor4nforming the core of the nanowire9, and a coating of superconductor5nformed at least part way round the semiconductor core4n. The superconductor coating5nmay be formed directly on or indirectly over the semiconductor core4n(e.g. there may be a ferromagnetic insulator, not shown, disposed between at least part of the superconductor coating5nand the semiconductor core4n).

The structure also comprises one or more associated conducting elements such as electrical contacts, leads and/or signal terminals formed in the conducting layer5, such as a gate5gfor applying an electrostatic potential to the nanowire9.

As will be familiar to a person skilled in the art, majorana zero modes (MZMs) can be induced in a semiconductor-superconductor nanowire9by cooling the device1to a temperature at which the superconductor5nexhibits superconducting behaviour, and applying a magnetic field to the nanowire9. The magnetic field may be applied from a source external to the device1, e.g. an external electromagnet; and/or may be applied by means of a magnetic element integrated into the device1itself, e.g. a ferromagnetic insulator (not shown) formed on at least part of the nanowire core4n. Inducing an MZM typically also involves gating, i.e. applying an electrostatic field to the nanowire5nvia a suitable gate element5g. However, it is also possible to induce MZMs without gating using full-shell nanowires (having a superconducting coating all the way round the nanowire's circumference). Techniques for inducing MZMs in nanowires are, in themselves, known in the art. In the illustrated example the gate is a side gate5g, but a top gate or bottom gate formed in the lower conducting layer6are also a possibility.

One nanowire9is shown inFIG.1Bfor illustrative purposes, but it will be appreciated that, depending on the device being fabricated, there may be more present (as well as associated conducting elements in the upper conducting layer5, and any associated structures in the lower conducting layer6and/or dielectric layer7). A network of such nanowires9formed in the plane of the substrate2can be arranged to form a qubit or a quantum computing device comprising a plurality of such qubits. Arrangements for forming qubits and quantum computing devices from networks of nanowires are, in themselves, known in the art.

The upper conducting layer5comprises various electrically conducting elements which may be used to form contacts with ones of the electronic components formed in the semiconductor layer4, and/or to apply an electrical potential to such components. E.g. these may include internal conducting wires (lines) connecting between different components in the semiconductor layer4, and/or terminals such as gates5gfor gating components such as the nanowires9. Some of the terminals may comprise bond pads for connecting external leads to the device1, enabling signals to be applied to the device1or read out from the device from an external equipment such as an external computer system (not shown). E.g. signals from room temperature electronics may be applied to the leads and gates via the bond pads.

Preferably, as will be discussed in more detail shortly, according to embodiments disclosed herein, the superconductor coating5nmay be formed in the same deposition step (or at least one of the same steps) as the other conducting elements such as the gates5g, bond pads5b, and/or conducting lines, etc.

Optionally one or more other layers may be included. For instance, part or all of the semiconductor layer4may be separated from the conducting layer5by an intermediate dielectric layer (not shown) to create one or more gates. And/or, one or more further, upper layers (not shown) of the wafer1may be formed over the upper conducting layer5, e.g. an oxide layer to protect from oxidation, and/or an encapsulating dielectric layer. And/or, one or more further or alternative lower layers (not shown) may be included in the lower structure3.

Note that the described process does not exclude the possibility of additional pre-fabricated bond pads. E.g. it may be advantageous to already have relatively thick metal pads in place, facilitating the wire bonding, cf.5binFIG.6. E.g. this may be formed in the lower layer6.

Note also again that theFIGS.1A and1Bare schematic and the shapes and dimensions shown therein are not intended to be limiting. E.g. in embodiments the nanowire9may in fact be hexagonal in cross section.

On a point of terminology, the “substrate”2herein refers to the ultimate base of the wafer1, and the “wafer” refers to the base plus any additional layers formed on or over the substrate2at any point in the fabrication or in the final finished wafer. “Over” herein may mean either formed directly on, or indirectly over with any one or more intermediate layers in between. So “over” the substrate herein may mean either formed directly on the substrate2, or with one or more intervening layers such as a dielectric layer between the substrate2and the semiconductor4. “On” herein means directly on, i.e. in contact with, without any intermediate layer. Neither term necessarily implies that one layer is formed across the entirety of the underlying layer. Note also that the terms “on” or “over”, “upper” and “lower”, “horizontal” and “vertical”, or such like, as used herein, do not necessarily imply a particular orientation relative to gravity. Rather, they refer to the position relative to the surface of the substrate2that is being worked (the surface upon which the formation of layers begins). Note also that “upper” and “lower” are merely relative terms, and do not necessarily imply that any layers referred to by these terms are the absolute uppermost or lowermost layers of their type. Also the mention of an “upper” conducting layer5does not necessarily imply the presence of a lower conducting layer, and the mention of a lower dielectric layer7does not necessarily imply the presence of an upper dielectric layer. Further, the term “layer” does not necessarily imply a continuous or unbroken layer and can also refer to a patterned or structured layer. Furthermore, any given pair of the various different layers2-7are not necessarily separated by a flat horizontal plane as they are represented schematically inFIG.1A. E.g. as shown by way of example inFIG.1B, parts of the metal layer5can “wrap” or descend downwards over structures in the semiconductor layer4, or similarly in any pair of adjacent layers.

Once fabrication is complete, the wafer1is packaged into an integrated circuit (IC) package using known IC packaging techniques. The packaging may comprise inserting leads connecting between the external connectors (e.g. pins or ball pads) of the package and the internal bond pads5b(shown later) formed in the upper conducting layer5, thus enabling the external equipment to control or read out from the semiconductor components in the semiconductor layer4. The packaging may comprise covering the wafer and leads with a suitable encapsulant, typically a dielectric, examples of which will be known in the art.

An example fabrication process flow in accordance with embodiments of the present disclosure is now discussed with reference toFIGS.1to7. By way of illustration these will be described in relation to the example where the deposited metal5is a conductor, e.g. a superconductor such as Al for forming the coating5nof the nanowires9, and the lower conducting layer6is also formed from a metal, e.g. gold or tungsten. However it will be appreciated that this is not limiting.

FIG.1illustrates a stage where the lower structure3has already been formed over the substrate2. In embodiments, the semiconductor4and upper conducting layer5are only to be formed on one or more selected, active circuit areas12, and not other areas over the substrate2. One such area12is illustrated inFIG.1but there could also be more present. The dielectric6may also only be formed in this layer. The other areas outside the selected areas may be used for other purposes. E.g. the metal layer6in such other areas could be patterned to provide a coplanar waveguide resonator to read out a qubit formed in the selected area12. Alternatively the other areas could simply be left as non-functional areas.

The deposition of the conductor5(e.g. metal) is performed by angled vapour disposition, whereby a beam of vapour5′ comprising the conducting material being deposited is directed toward the substrate, e.g. by electron-beam physical vapour deposition, chemical vapour deposition, or plasma-enhanced chemical vapour deposition. The arrow labelled5′ represents deposition of the conductor (e.g. metal) under a steep angle. The angle of deposition is at least acute relative to the plane of the substrate2, i.e. a non-perpendicular angle in between the normal to the plane of the substrate2and the plane of the substrate2. Preferably the angle is less than 45 degrees relative to the plane of the substrate (greater than 45 degrees to the normal), and in embodiments may be much less, e.g. less than 22.5 degrees, or less than 12.25 degrees. The particular desired angle may depend on the geometry of the SAG or VLS wire. The relevant condition may be that the deposition must enable an electrical connection via the substrate (or a metallic loop running across the substrate connecting several semiconductor segments). The actual angle depends on the facets of the nanowire. For a hexagonal nanowire cross-section the maximal deposition angle to the plane of the substrate is 60 degree. In reality it may be beneficial to use a steeper angle than that to ensure proper coverage of the lowest hexagon facet. For instance embodiments use 30 degrees.

In embodiments, the substrate2is provided with a vertical hard mask template10placed on at least one side of the substrate2. The template comprises one or more holes11, each corresponding to a respective one of the selected deposition regions12. The evaporated material5′ is deposited through the hole(s)11so as to only form on the corresponding areas12over the substrate2. The template12can be fabricated for example by 3D printing on the chip1, e.g. from special resins, or it could be a thin patterned Cu mask placed on top of the chip (it can be included into the sample clamp to ensure accurate alignment between the sample and the template). The position, size and shape of these areas12is a function of the size and position of the holes11, and the direction of deposition including the angle of deposition. The purpose of the template structure10is to prevent that large areas of the chip1are covered by a metal film5during metal deposition. The vertical template10enables coarse structuring of the deposited metal film5. However, in alternative embodiments, other suitably focused beam-based vapour deposition techniques could be used that do not involve the template10; though a template may be preferred to achieve the desired accuracy if the area12(or any of the areas12) is smaller than 100×100 μm2(or smaller than 100 μm in any dimension in the plane of the substrate).

In the example illustrated, the depicted coplanar waveguide resonator has been fabricated in the lower metal layer6prior to the nanowire deposition. Only the area12on the chip1is covered selectively with metal during the deposition process.

If deposition is required from multiple angles, several vertical hard mask templates11may be placed on different sides of the substrate. In embodiments, the vertical template may contain holes11that are approximately 100 μm wide and may have an inclination that equals the evaporation angle.

The holes11in the vertical template10are positioned such that metal is only selectively deposited in the vicinity of the nanowire devices. In embodiments, this allows for example to incorporate the nanowire devices into coplanar waveguide resonators for qubit readout and two-qubit entanglement. In embodiments the vertical template structure10can be left in place when the overall device is finally capped and packaged into an IC package. Since the hard mask template10is oriented vertically the final device can be protected after the deposition of the metallic leads by in situ capping with a dielectric layer. Thus, the devices are protected from degradation when exposed to air, preserving high quality. However, this is not essential and in alternative embodiments the template structure10may be removed before encapsulation.

Within a given deposition area12, the metal5may be patterned by means of a structure of shadow walls13, also called “smart walls”. These are shown inFIGS.2-7, to be discussed in more detail shortly. In embodiments the shadow walls13are formed from a dielectric material. Preferably these walls13are formed before growth of the semiconductor layer4to avoid possible damage caused by the processing involved in forming the shadow walls13. However it is not excluded that they could be formed after the semiconductor4.

The basic, general idea of shadowing is known. However, the original shadow wall idea was aimed only at removing the need to do local patterning near the device area. The inventors have found that, when using the smart walls without the additional features presented herein, then much etching is still required to create a device that has multiple metallic sections, which must be completely electrically-isolated from each other (such as is needed when connecting leads to the device). This means that the smart walls by themselves are not enough to create a device without post-fabrication. The problem is illustrated inFIGS.2-3. The disclosed solution uses gaps15to inherently pattern electrically isolated pockets of metal as illustrated inFIG.4and described below.

FIG.2illustrates an example of a “pocket” structure14defined by shadow walls13.FIG.2represents a simplified version of a potential pocket structure made of walls13and fabricated on a dielectric layer7or substrate2. In this example the pocket14comprises a region enclosed by the wall structure13on all sides.FIG.2illustrates a particular structure that may be formed inside part of one selected deposition area12inFIG.1(so the scale inFIG.1is much larger than inFIG.2, and indeedFIGS.3-7). By way of contrast with the ideas disclosed herein, the walls13of the pocket structure inFIG.2do not comprise any gaps.

FIG.3shows the pocket structure ofFIG.2, without gaps, after the metal deposition by the angled evaporation technique. The arrow labelled5′ represents the direction of metal evaporation, i.e. the deposition direction. The pocket becomes shorted to the outer film via the depicted path around the walls, so there is no electrical isolation.

To elaborate, when metal vapour5′ is deposited at the angle shown by the large arrow inFIG.3(e.g. <45° with respect to the sample horizontal), the walls13will cast a shadow over the substrate that can be seen in black. This disconnects most regions where the outer film5could contact the inner pocket area14. Nevertheless, there are still regions where the metal5′ climbs the wall13vertically from the deposition direction and continues horizontally on top of the wall13, where it will eventually find its way down to the pocket. Put another way, the metal vapour5′ will “creep” over the wall13. As the resulting metal film5is then deposited on the top of the walls13, and the inner sides of the walls13within the pocket14, and furthermore on the floor of the pocket14, this means electrical contact is made between the metal5inside and outside of the pocket (i.e. they are shorted). The arrowed path inFIGS.3(and4) depicts an example electronic path of charge carriers in the film5(not a direction of the metal vapour5′). Here it can be seen that, in the case ofFIG.3, there is a path connecting the outer film with the inside of the pocket14. Hence the deposited film5inside the pocket14cannot be used as an isolated electrical contact such as, say, a bond pad for connecting between the lower conducting layer6and a lead. Therefore this pocket structure13is not, without modification, suitable for forming such contacts.

To prevent this problem, a disruption can be added to the pocket-wall structure in the form of gaps15, as shown inFIG.4.FIG.4shows a pocket structure14after metal evaporation, similar toFIG.3, but with gaps15in the walls13. Incorporating gaps15in the structure prevents an electrical connection around the walls13. The inside of the pocket14is electrically isolated from the outer film.

Thanks to these gaps15, the film is not continuous on top of the walls13. The size of such gaps15is by design small enough to not allow any metal inside the gap for the desired evaporation angle, achieving with this full electrical isolation of the pocket14with respect to the outer film. The shadow length of a given part of the wall structure13is the extent of the shadow which that part of the wall structure would cast, extending out from that part of the wall structure, projected onto the plane of the substrate2, if not interrupted by the wall on the other side of the gap15. It is a function of not just the height and shape of the relevant part of the wall structure13itself, but also the deposition direction, including the polar angle of the disposition direction. In other words, the gap15is short enough that the metal (or other conducting material) that is being deposited does not hit the bottom of the gap15.

The inventors have discovered that as long as the gap15is kept shorter than the shadow length of the part of the wall structure13forming that shadow, then the metal vapour5′ will not fall onto the floor of the gaps15. The effect is a geometric one: the angle of the deposition is not steep enough that the deposited beam5′, projected onto the plane of the substrate2, can reach the bottom of the gap15before hitting the side of the opposing wall13on the far side of the gap. If the gap15is larger than the shadow, metal5′ would fall inside the gap15, onto the floor of the gap15(substrate2or underlying layer6/7). In that case, the resulting metal film5outside the pocket14inFIG.4would then be connected to that inside of the pocket via the floor inside the gap15(not via the wall in this case, but still connecting the outer metallic film with the metal inside the pocket14).

Thus unlike inFIG.3, the metal film5deposited inside the pocket14ofFIG.4is electrically isolated from the metal film5deposited outside the pocket14. This means the deposited film5inside the pocket14can be arranged as an isolated electrical contact for controlling or reading out from one the components of the device.

E.g. the metal film5deposited inside the pocket14may be arranged as a bond pad for connecting a lead and the lower conducting layer6, which may vicariously connect on to other active components such as one of the semiconductor components in the semiconductor layer, e.g. the nanowire. In embodiments, in order to connect to the nanowire9, an opening may be formed extending from the base to the top of the wall, in the furthest wall13, assuming the nanowire is located outside of the pocket14(see alsoFIGS.5and6, discussed in more detail shortly). Alternatively a connection to the nanowire9could be formed via the lower conducting layer6.

As another example, the metal film5deposited inside the pocket14may be arranged as a gate for gating a nanowire9. In this case, the gate may be separated from the nanowire by a dielectric, but applies an electrostatic potential to the nanowire9which propagates through the dielectric. The gate may be controlled via a connection between the metal film5in the pocket4and the lower conducting layer6. In embodiments this may be done by bonding through the dielectric layer7in between. In one possibility, the gate could be formed from the metal film15inside the pocket14and the dielectric could be formed from the wall13itself. However, given the fact that in embodiments the walls13are much larger than 100 nm, this would allow only for very weak coupling to a gate electrode. A more preferable realization for a gate would be by means of a patterned layer6covered with a thin dielectric layer7. These “bottom gates” can be efficiently coupled to the semiconductor (allowing for more pronounced changes in the electrostatic potential) as the gate is very close to the semiconductor channel. This gate could be connected to the film5inside a pocket4to enable electric connection to another component or an external source.

Note that the shape of the walls13inFIGS.2-4is a trapezoid, as is reflected in the shapes of the shadows inFIGS.3and4. The trapezoid has two parallel walls13(the bases of the trapezoid) and two non-parallel walls (the sides or legs of the trapezoid). The longest base of the trapezoid is arranged as a front wall substantially facing the direction of deposition (the first wall13of the pocket13to be met travelling in the direction of deposition), whilst the shortest base of the trapezoid is arranged as a rear wall behind the front wall (the last wall of the pocket14to be met travelling in the direction of deposition). The bases are preferably substantially perpendicular to the deposition direction. The side walls13taper inwards from the front wall to the back wall, at an angle in the plane of the substrate2that is steeper than parallel to the deposition beam direction. Hence the regions behind the side walls get shadowed.

A trapezoidal shape is advantageous since it allows for tolerance in the azimuthal angle of evaporation. In the case of rectangular walls, if the evaporation comes slightly from the side, the metal5′/5will cover the outer side of the walls. This is however not necessarily detrimental, since the gaps can be adjusted accordingly. The rectangular shape is only a problem if the deposition is not perfectly directional. If a wall13is completely straight and parallel to the deposition direction, which is also perfectly directional (or close enough), then the metal vapour would not deposit on the sides of the wall, since the impinging flux on that wall equals zero. Nonetheless, by having trapezoidal shapes, one can know for sure on which of the two side walls the metal is evaporated even in the presence of an imperfectly directional beam.

A similar effect can be achieved with other pocket shapes having a front wall wider than the back wall and one or more side walls that taper backwards along at least part of the length. E.g. see the pocket shape shown inFIG.6, to be discussed in more detail shortly.

FIG.5illustrates another example of the trapezoidal pocket shape. Here the pocket is used to form a contact to a nanowire9(a nanowire9may require both a gate and a contact to the superconducting coating5nin order to operate as part of a qubit). Panel a) shows a layout of shadow walls13and semiconductor core4nof a nanowire, all formed over the substrate2and any intermediate layers6,7of the lower structure3. One pocket14ihas its longest base arranged as a front wall facing a first deposition direction, being the direction of deposition of a first beam of metal vapour5′. The shortest base (rear wall to the first direction) has an opening16which opens out onto part of the nanowire core4n. When the first beam of metal5′ is deposited, as shown in panel b), it not only forms a contact such as bond pad5bin the pocket14, but also passes through the opening16and coats the corresponding part of the nanowire core4nto form the superconducting coating5n(assuming the deposited metal is a suitable superconductor such as Al). Via the material deposited in the opening16, this also makes electrical contact between the film5in the pocket14and the nanowire coating5n. Thus the superconductor coating5nof the semiconductor-superconductor nanowire(s)9can be formed from the same deposition step as the rest of the angled metal deposition.

Note that this superconductor (e.g. Al) coating5nis only formed over a relatively small length of the semiconductor core of the nanowire, where the small opening of the pocket meets the semiconductor inFIG.5(andFIG.6, or where the un-shadowed “cut-outs” in the walls meet the nanowire9inFIG.7, to be discussed in more detail shortly).

Referring also to panel c),FIG.5also illustrates dual-angle deposition employing smart walls (shadow walls)13with gaps15on both sides of the nanowire9. A double wall13is employed to avoid electrically shorting parts of the device.

A second pocket14iihas its longest base arranged as a front wall facing a second deposition direction, being the direction of deposition of a second beam of metal vapour5″. In general this may be the same or a different kind of metal than deposited in the first beam. The shortest base (rear wall to the second direction) of the second pocket14iihas an opening16which opens out onto another part of the nanowire core4n. When the second beam of metal5″ is deposited, as shown in panel c), it not only forms a contact such as bond pad5bin the second pocket14ii, but also passes through the opening16and coats the corresponding part of the nanowire core4nto form the superconducting coating5n(similarly to the situation described in relation to the first pocket14i, but in the opposite direction and coating another part of the length of semiconductor4).

While the methodology with gaps15described above works for a single evaporation step, shorts can still occur when multiple depositions at different angles are performed, even when using gaps. Hence, the design may be modified to allow for multiple angles. In embodiments the modification made is to use double-wall structures, with both walls at a distance small enough to prevent metal deposition between them (again shorter than the shadow length).FIG.5depicts an example of this.

More generally, deposition of a metal or conductor5could be performed from any two or more different directions. Note that a given direction as referred to herein includes both the polar angle and the azimuthal angle. The polar angle is the angle of elevation relative to the plane of the substrate2, or equivalently the angle formed with the normal to the substrate. The azimuthal angle is the angle in the plane of the substrate2. The different deposition directions could comprise angles at different polar angles, azimuthal angles or both.

Using such methods, it is possible to make complex isolated patterns that contact the wire and nothing else on the chip 1, or even generate superconducting and normal contacts on the semiconducting wire that are electrically isolated from each other, as shown inFIGS.5A-5C. In embodiments such as shown in these figures, this can be achieved by using two in situ evaporation steps with two different metals present in the deposition cluster (e.g., aluminium and gold) at two different evaporation angles (FIGS.5B and5C, from the top and the bottom of the picture, respectively). InFIGS.5A-5Cthese are represented by5iand5ii. The deposition of the two different first and second metals in their vapour form are labelled5′ and5″ respectively. The corresponding first and second deposited films are labelled5iand5ii, respectively. If two evaporation angles are used, the designed wall structure may contain double walls similar to the ones ofFIGS.5A-5Cin order to achieve full isolation between the metals5i,5ii.

FIG.6gives a schematic illustration of the smart walls13surrounding two bond pockets. Gaps15are incorporated to electrically isolate the metal films5inside the two pockets from one another as well as from the outside of the walls13. The metal film5formed inside each of the pockets5comprises a bond pad5b. The raised parts (in this case squares) shown inside the pockets14can be patterned previous to the nanowire deposition and then coated with the metal film5along with the rest of the metal layer. The reason for this is that wire bonding exerts force onto chip, so to avoid damage to the layers a relatively thick metal layer may be pre-fabricated in the bond pocket area. However this is optional and instead the floor of the pocket14forming the bond pad5bcould just be flat. Note also thatFIG.6shows a variant of the idea behind the trapezoidal shape exemplified inFIGS.4and5. In the case ofFIG.6the shape is not a trapezoid but functions similarly. The longer, front walls of the pocket face the oncoming deposition beam5′. The side walls taper backwards along at least part of their length. Also in this case two adjacent pockets share a central wall.

The pockets are isolated similarly to the previous example. The deposited metal5also covers at least some of the sides and the tops of the walls (though not shown as doing so inFIG.6). However, this layout (which is only an illustrative schematic) avoids shorts between the two pockets14. The central wall is tapered inwards. Thus, no metal5is deposited on either the left or on the right sides of the centre wall. Having some straight walls (as is the case here) can in some cases be a problem, for instance if the deposition is not perfectly directional and thus metal can cover the inner AND the outer side of the walls. However this is not necessarily a problem since the evaporation5′ can be made very directional.

The example ofFIG.6also shows the idea of an opening16on the shorter rear wall, opening out onto the nanowire, for coating the nanowire core4nand at the same time forming a contact between the nanowire coating5nand the bond pad5bin the pocket. However in the case ofFIG.6, this involves only a single deposition direction and corresponding pocket direction, as opposed to the dual disposition angle approach ofFIG.5. Except for the case of dual- or multi-angle deposition such as inFIG.5, in embodiments the process requires only a single metal deposition step. The nanowires are semiconducting and the hybrid semi-/superconducting segments on the nanowire are created in this evaporation. An advantage of this method is that not only superconducting contacts but also effectively normalconducting contacts can be fabricated this way in a single deposition (the electrical superconducting contacts made from Al that are placed several micrometers away from the critical device effectively act as normalconducting leads).

In embodiments, following the post-fabless paradigm, the device1does not comprise top gates for electrostatically tuning the devices. Instead, it employs bottom and/or side gate structures that are fabricated prior to the smart walls13(as well as the nanowire deposition or growth), and which locally control the electrochemical potential of the nanowires from underneath. To connect these gates to the outside world, pockets14are created for wire bonding using the method described above (e.g.FIG.5or6). Since the bottom gates are fabricated prior to the nanowire deposition or selective nanowire growth, the process allows for a higher thermal budget and for higher-quality dielectrics. If desired additional gates or metal leads can be guided from the device to these bond pockets through the shadowed area and the previously described gaps, providing electrical connection to the bond areas.

FIG.7shows an exemplary realization of hybrid semiconducting-superconducting structures separated by a normalconducting segment. The left-hand panel shows the wafer1before metal deposition, and the right-hand side after. Note that in the left-hand panel, the lower dielectric layer7is not shown so as to illustrate bottom gates6gformed in the lower metal layer6, but nonetheless the lower dielectric layer7will be understood to be present over the top of the lower metal layer6. In embodiments the lower dielectric layer7is a uniform coating but it could alternatively be patterned, e.g. a patterned structure on top of the gates6g. Pockets14are not shown inFIG.7, but one or more such pockets may be formed in the large white regions marked “metal film5”, e.g. for connecting to the nanowire9, e.g. in a similar manner as discussed in relation toFIGS.4-6.FIG.7highlights the incorporation of bottom gates in the process flow (following the post-fabless approach).

In the example ofFIG.7, the wall structure13shadows most of the length of the semiconductor4nthat forms the core(s) of one or more nanowires, except that one or more channels17and/or cut-out regions18are left in the wall structure13. These channels17and/or cut-outs18prevent corresponding sections of the semiconductor4nbeing showed, and hence the deposition5′ coats these each of these sections with a metal coating5nto form a respective semiconductor-superconductor nanowire9. Further, the shadow is long enough to leave some parts of the lower dielectric layer7exposed, uncovered by the metal film5.

The gates5g/6gare conducting and one can induce a topological phase in the nanowire9by applying appropriate voltages to the gates. These gates are however electrically isolated from the nanowire as the gates and the wire are physically separated by the gate dielectric (e.g. Al2O3, HfO2, or Si3N4or similar). They apply an electro static potential to the gates via an electric field that propagates through the dielectric. This is how most types of gates are implemented in research/industry. The electric field created by the potential on the gate locally changes the energy level of the nanowire9, which is required to enable the phase transition. The normalconducting segment is the very narrow shadowed region at the centre of the nanowire

In conclusion, the present disclosure has presented an approach that reduces the need for fabrication steps after the deposition or growth of the semiconductor layer and subsequent metal deposition (e.g. including the semiconducting nanowires), and in embodiments eliminates the need for any such steps altogether. By designing shadow wall structure, preferably using a small evaporation angle with respect to the substrate plane in combination with a vertical hard mask template, then the electrical contacts can be patterned onto the semiconductor structure4in a manner that keeps the contacts isolated from the global film5that lays on the substrate after evaporation. This will prevent or at least reduce the need for any fabrication on the chip after metal deposition. In embodiments the bottom or side gates also may be fabricated prior to the deposition or growth of the semiconductor

If an in-situ dielectric capping method is possible in the deposition cluster, a device that is clean, protected and resilient against degradation and aging can be obtained, an achievement that is not possible with any of the usual fabrication designs and flows currently available. The disclosed process involves smart walls, and in embodiments a hard mask template. Such techniques enable complex hybrid nanowire devices to be fabricated without relying on additional nanofabrication steps.FIG.8shows a scanning electron microscope (SEM) image of a device containing smart wall networks with gaps and pads following a fabrication flow as described herein. It allows one to achieve electrically isolated contacts to the wire after metal deposition, avoiding metal etching. If bottom gates are introduced, no port-fabrication will be needed on this device. This last development is currently ongoing.

It will be appreciated that the above embodiments have been described by way of example only.

For instance, similar techniques could be applied to form any structure where it would be desirable to avoid or reduce potential damage by post-fabrications steps such as etching or lithography that are conventionally used to form the upper conducting structure. The disclosed techniques could be used to form other types of qubit or quantum device other than just MZM-based qubits based on semiconductor-superconductor nanowires. E.g. the semiconductor layer4could comprise components of other types of qubit or other quantum devices such as SIS junctions, SIN junctions and SQUIDS; or spintronic devices such as spin transistors, spin-based storage elements or spin-based sensing elements; or even conventional semiconductor components such as transistors.

The conducting material5used in the upper and/or lower conducting layers6,5need not necessarily be a metal. More generally, it could comprise a superconductor or other conductor. It could comprise a metal, or another conductor such as a conducting polymer. In some embodiments the conducting material5being deposited in the angled deposition may even comprise a semiconductor. In embodiments multiple sublayers of different types of conducting material could be applied in different steps at different deposition angles.

In embodiments, any of the disclosed method could even be used for angled deposition of any type of material generally. For instance, in embodiments the angled deposition process could additionally be used to form one or other types of layer, e.g. a dielectric, in addition to the conducting material5. For instance, the method may be used to evaporate a dielectric material such as Al2O3as a gate dielectric, followed by a metal layer. Alternatively the deposited material5may comprise only another type of material, e.g. only a dielectric. This may be especially relevant in the case of the vertical template10. For instance it could be desired to only want to deposit dielectric in the middle of the chip, and have some bond pads around this area without dielectric, where one can bond.

The semiconductor4may comprise any semiconductor material such as InAs, GaSb or InSb, including any kind of combination of these (e.g. GaxIn1−xAsySb1−y), with or without any kind of doping (e.g. Bi, Te), of either single component or multi-component (e.g. multi-layer), in form of either nanoparticles, nanowires, films or bulk crystals. Or more generally still, the first or active layer4in which the circuit portions are formed prior to the angled deposition of the conducting material5need not necessarily comprise, or not solely comprise, a semiconductor material. In principle that layer4could also be some previously patterned material (e.g. dielectric or metal), that could even have been deposited using the shadow walls in a previous deposition step. For instance in the case for forming a layer of SIS quantum components, each component may comprise two metallic leads deposited on top of a piece of dielectric (forming the “I” part of the component) that is lying on or over the substrate2.

Where a dielectric is used for any part of the device1, this could be any of a variety of dielectric materials known to a person skilled in the art. Further, the shadow walls13are not limited to being formed from dielectric. E.g. the walls13may instead be made from a metal or a semiconductor. For instance, this actually enables some of the walls to be used as gates. To not run into the risk of having accidental shorts, and due to the ease of structuring thick layers of dielectric, then dielectrics may be preferred. However, this is not a fundamental issue. If designed appropriately the risk of having shorts is not much higher in case of a metallic smart wall. Moreover, there are also feasible fabrication techniques for metal etching.

It is also not excluded that other layers than those shown in the Figures could be present.

More generally, according to a first aspect of the present disclosure, there is provided a method of fabricating a device, comprising: providing a substrate defining a plane; forming portions of electronic circuitry over the substrate; forming a shadow wall structure over the substrate; and after forming said portions and the shadow walls, depositing an upper conducting layer over the substrate by angled deposition of a conducting material in at least a first deposition direction at an acute angle to the plane of the substrate, wherein the shadow wall structure is arranged to cast a shadow in the deposition, leaving areas where the conducting material is not deposited; wherein the shadow wall structure comprises one or more gaps each shorter than a shadow length of a respective part of the shadow wall structure casting the shadow into the gap, to prevent the conducting material forming in the gaps and to thereby create regions of said upper conducting layer that are electrically isolated from one another; and wherein said electrically isolated regions are arranged to form conducting elements for applying signals to, and/or receiving signals from, the electronic circuitry.

In embodiments, the conducting elements may comprise one or more of: one or more bond pads for connecting an external lead to one or more of the active components, one or more internal conducting lines connecting between two or more of the active components, and/or one or more gates for gating one or more of the portions of circuitry.

In embodiments, the method may comprise forming a lower structure over the substrate prior to forming said portions and shadow walls, the lower structure comprising a lower conducting layer and/or lower dielectric layer.

In embodiments, the conducting elements may comprise one or more bond pads connecting to the lower conducting layer, and/or one or more internal lines connecting between the lower conducting layer and one or more of said portions.

In embodiments the conducting material is a conductor. In embodiments the conductor may comprise a metal. Alternatively the conductor may comprise a conducting polymer. In embodiments the conductor may comprise a superconductor (e.g. Al). Alternatively the conductor may comprise a semiconductor.

In embodiments said portions of circuitry comprise portions of semiconductor. Alternatively or additionally said portions of circuitry may comprise one or more portions of dielectric.

In embodiments, the device being fabricated may comprise a topological quantum computing device comprising a network of semiconductor-superconductor nanowires, each nanowire comprising a length of semiconductor and a superconductor coating formed over at least part of the semiconductor. The portions of semiconductor may comprise said lengths of semiconductor. One or more of the electrical contacts may be arranged for applying signals to, and/or reading out from, one or more of the nanowires.

In embodiments, the conducting material may comprise a superconductor and said coating may comprise some of the superconductor deposited as part of said upper conducting layer, the conducting elements thus being formed as part of in the same angled deposition as the superconducting coating.

In embodiments, the shadow wall structure may comprise one or more partially enclosed pockets formed in the plane of the substrate, each comprising walls enclosing the region forming a respective one of said conducting elements within the walls of the pocket. The walls of each pocket may have one or more gaps for creating the electrical isolation, and optionally an opening for forming a connection to at least one of the portions of circuitry. In embodiments, preferably there are no other discontinuities in the walls of the pocket.

In embodiments, at least one of the pockets comprises no opening for forming a connection to any of the of the semiconductor components, but instead the respective conducting component connects to one or more of the portions of circuitry via the lower conducting layer.

In embodiments, at least one of the pockets may have a front wall facing the first deposition direction, a rear wall behind the front wall from perspective of the first deposition direction, and side walls joining the front and rear walls. The rear wall may be shorter than the front wall, and at least one of the side wall may tapers backwards at least part way between the front and rear walls so that the shadow of the at least one side wall prevents the conducting material being deposited on an outside of the at least one side wall.

In embodiments the rear wall may comprise said opening.

In embodiments the pocket may take the shape of a trapezoid, the front and rear walls being the parallel bases of the trapezoid and the side walls being the sides of the trapezoid.

In embodiments the front wall may be arranged to be substantially perpendicular to the direction of deposition (or at least one of the directions of deposition).

In embodiments, it may be that no etching or lithography steps are used to form any conducting layers after the forming of the portions of circuitry.

In embodiments, said depositing of the upper conducting layer over the substrate may be by angled deposition of a conducting material in each of a plurality of deposition directions each at an acute angle to the plane of the substrate, the shadow wall structure thus casting a plurality of respective shadows in the deposition. The gaps may be are shorter than the shadow length of the respective parts of the wall structure casting all of said plurality of shadows, to prevent the conducting material from being deposited in the gaps from any of said deposition directions.

The different directions may comprise different polar angles (perpendicular) and/or different azimuthal angle (in the plane of the substrate). In embodiments the directions may comprise at least first and second directions, or only first and second directions. The first and second directions may have opposite parallel azimuthal angles (opposite and parallel in the projection of the directions onto the plane of the substrate).

In embodiments, the angled deposition may comprise: forming a vertical template perpendicular to the substrate on one or more sides of the substrate, the vertical template comprising one or more holes corresponding to one or more areas in the plane of the substrate over which said deposition is to be performed given the angle of the deposition direction or directions relative to the substrate; and depositing said conducting material through the one or more holes in the deposition direction or directions, at the angle of each deposition direction, thereby depositing the conducting material over said one or more areas. The vertical template may either be left in place or removed when the device is subsequently capped.

According to a more general variant of the first aspect, there is provided a method of fabricating a device, comprising: providing a substrate defining a plane; forming portions of electronic circuitry over the substrate; forming a shadow wall structure over the substrate; and after forming said portions and the shadow walls, depositing an upper layer over the substrate by angled deposition of any material in at least a first deposition direction at an acute angle to the plane of the substrate, wherein the shadow wall structure is arranged to cast a shadow in the deposition, leaving areas where the conducting material is not deposited; wherein the shadow wall structure comprises one or more gaps each shorter than a shadow length of a respective part of the shadow wall structure casting the shadow into the gap, to thereby create discontinuous regions of said material. In embodiments, any of the features disclosed above may additionally be applied in conjunction with this definition of the first aspect.

According to a second aspect disclosed herein, there may be provided a method of fabricating a device by angled deposition, comprising: providing a substrate defining a plane; forming a vertical template perpendicular to the substrate, the vertical template comprising one or more holes corresponding to one or more areas in the plane of the substrate over which said deposition is to be performed given a direction of deposition at an acute angle to the plane of the substrate; and depositing a material through the one or more holes in said direction at said angle, thereby depositing the material over said one or more areas.

The first and second aspects may be used together of independently of one another. In embodiments, any feature described in relation to the first aspect may or may or may not be used in conjunction with the second aspect, and vice versa.

According to another aspect disclosed herein there is provided a device formed by any method disclosed herein.

According to another aspect disclosed herein there is provided a method of operating the device. The method may comprise: applying an internal or external magnetic field to one or more of the nanowires, and cooling the device to a temperature inducing superconductivity in the superconductor, in order to induce majorana zero modes, MZMs, in the one or more nanowires.

In embodiments, the inducement of the MZMs may further comprise gating the nanowires with an electrostatic potential applied via one of said conducting elements.

Other variants or use cases of the disclosed techniques may become apparent to the person skilled in the art once given the disclosure herein. The scope of the disclosure is not limited by the described embodiments but only by the accompanying claims.