Circuit in dynamic random access memory devices

A circuit in dynamic random access memory devices includes a command extension circuit. The command extension circuit is configured to generate at least one multiple-cycle command signal by lengthening a single-cycle clock command signal from a command decoding circuit. Control logic extends and reduces the multiple-cycle command signal to provide additional functions such as burst length and burst chop. Additional control logic is configured to determine whether a clock signal is enabled in output control logic circuitry according to the multiple-cycle command and logic level generated in the output logic circuitry.

FIELD OF THE INVENTION

The present invention relates to a circuit and, in particular, to a circuit for command generation and clock control in dynamic random access memory devices and method thereof.

DISCUSSION OF THE BACKGROUND

In current DRAM, for gapless read/write, a single-cycle command pulse would be generated and propagate through the DRAM. However, since the command pulse is single-cycle wide, the command logic of the DRAM would run continuously for gapless access and the power consumption of the DRAM would be extremely high.

Therefore, in order to reducing the power consumption of the DRAM, area saving and ensure outputs and termination are enabled correctly, a circuit for command generation and clock control in DRAM devices and method thereof is necessary.

SUMMARY

In accordance with one embodiment of the present invention, a circuit for command generation in dynamic random access memory devices comprises a command extension circuit and a first And circuit. The command extension circuit is configured to generate at least one multiple-cycle command signal by lengthening a single-cycle command signal from a command decoding circuit. Then, the at least one multiple-cycle command signal is outputted to a delay lock loop (DLL) circuit.

The first And circuit is configured to determine whether a clock signal is allowed to be sent to an output control logic circuit according to a logic level, generated by the DLL circuit or the command decoding circuit. The DLL circuit is disposed between the command extension circuit and the output control logic circuit.

In accordance with one embodiment of the present invention, a method for clock control in dynamic random access memory devices comprises the steps of transitioning a logic level according to availability of an active zone of a dQ-enable-delay (QED) shifter stack, or whether a gap command signal is received; calculating the logic level with a logic level of a clock signal and generating a result; and enabling or disabling the clock signal according to the result.

In order to provide further understanding of the techniques, means, and effects of the current disclosure, the following detailed description and drawings are hereby presented, such that the purposes, features and aspects of the current disclosure may be thoroughly and concretely appreciated; however, the drawings are provided solely for reference and illustration, without any intention to be used for limiting the current disclosure.

DETAILED DESCRIPTION

FIG. 1is a schematic view of a circuit10for clock control in dynamic random access memory devices of one embodiment of the present invention.

As shown inFIG. 1, the circuit10comprises a command extension circuit11, a first And circuit13, a command decoding circuit15, a delay lock loop (DLL)17, an output control logic19and a DQ logic circuit12. The command extension circuit11is configured to generate at least one multiple-cycle command signal by lengthening a single-cycle command signal from the command decoding circuit15. Then, the at least one multiple-cycle command signal is outputted to later control logic, for example, a delay lock loop (DLL) circuit17.

The first And circuit13is configured to determine whether a clock signal is allowed to be sent to the output control logic circuit19, which is according to a logic level generated by the command decoding circuit15or the DLL circuit17and outputted from the output control logic circuit19.

FIG. 2shows a schematic view of a multiple-cycle command and clocks of one embodiment of the present invention. As shown inFIG. 2, in the current embodiment, the multiple-cycle command signal is corresponding to four clocks but is not limited.

FIG. 3shows a schematic view of a command extension circuit of one embodiment of the present invention.

As shown inFIG. 3, the command extension circuit11further comprises a first flip-flop31, a second flip-flop33, a third flip-flop35, a first Or circuit37, a second Or circuit39and a second And circuit32.

The first flip-flop31is coupled to the command decoding circuit15, the second flip-flop33and the first Or circuit37respectively, wherein the first flip-flop31generates a first delay signal according to the single-cycle command signal from the command decoding circuit15and then sends the first delay signal to the second flip-flop33and the first Or circuit37.

The third flip-flop35is coupled to the second Or circuit39, the second flip-flop33and the first Or circuit37respectively, wherein the third flip-flop35generates a third delay signal according to a second delay signal from the second flip-flop33and a reset signal from a second Or circuit39and then sends the third delay signal to the first Or circuit37.

Moreover, the second delay signal is generated by the second flip-flop33according the first delay signal and the reset signal. The reset signal is generated by the second Or circuit39according to a burst length4signal and an output signal from the second And circuit32. The second And circuit32generates its output signal according to a A12 signal and a burst chop4signal, and the first Or circuit37is configured to generate its output signal (the multiple-cycle command signal) to the DLL circuit17according to the first delay signal of the first flip-flop33, the second delay signal of the second flip-flop35, the third delay signal of the third flop-flip37and the single-cycle command signal of the command decoding circuit15.

Moreover, the output control logic19further comprises a QED shifter stack, wherein the QED shifter stack comprises a plurality of shifters, wherein the active zone comprises a portion of the shifters.

FIG. 4shows a schematic view of the QED shifter stack of the output control logic circuit. As shown inFIG. 4, the QED shifter stack41comprises of the shifters. The active zone43comprises of the portion of the shifters. Furthermore, a first-in-first-out (FIFO) algorithm is implemented on the active zone. Therefore, with the multiple-cycle command signals being generated repeatedly, the multiple-cycle command signals would fill up the portion of the shifters from entry to exit.

In this state, referring back toFIG. 1, the logic level is transitioned by the DLL circuit17, in the current embodiment, from high to low, but is not limited as such. Then, the logic level is sent to the And circuit to disable the clock signal entering into the output control logic circuit19. Meanwhile, the shifters of the active zone43would be frozen.

Moreover, the shifters of the active zone43would be kept frozen until a command having “gap” information is received by the command decoding circuit15. In this state, referring back toFIG. 1, the logic level would be transitioned, in the current embodiment, from low to high but not limited, by the command decoding circuit15and sent, via the command extension circuit11, the DLL circuit17and the control logic circuit19, to the And circuit for enabling the clock signal entering into the output control logic circuit19.

FIG. 5shows a flow chart of a method for clock control in dynamic random access memory devices of one embodiment of the present invention.

As shown inFIG. 5, in the step S501, a logic level would be transitioned according to availability of an active zone of a QED shifter stack, or whether a gap command signal is received. In step S503, the logic level would be calculated with a logic level of a clock signal by an And logical operation for generating a result.

In step S505, the clock signal would be enabled or disabled according the result, wherein the clock signal would be enabled while a multiple-cycle command having “gap” information is received by a command decoding circuit, wherein the clock signal would be disabled while an active zone of a QED shifter stack of a DLL circuit is filled up with multiple-cycle commands.

Moreover, the QED shifter stack comprises a plurality of shifters and the active zone comprises a portion of the shifters, wherein a first-in-first-out (FIFO) algorithm is implemented on the active zone.

Although the current disclosure and its objectives have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, many of the processes discussed above can be implemented using different methodologies, replaced by other processes, or a combination thereof.