System and method for shuffling mapping sequences

A sequence mapping circuit and method for digital audio circuits generates a pulsed output. Over time, the mapping circuit generates pulses with a substantially identical average centroid for each of the possible output waveforms. For at least some of the output waveforms, two or more sets of pulses are provided representing the same waveform but having different centroids. The output is alternated among the available sets of pulses to maintain the desired average centroid over time. Shuffling of the output among the available pulses representing a given waveform may be randomly determined, or the pulses used may be tracked and the output pulses sequentially alternated among the available output pulses. The shuffled mapping method reduces output harmonics compared to conventional static mappers.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to improved apparatus and methods for shuffling mapping sequences in digital modulation circuits, and includes particular applications of these circuits to digital modulators of a type useful in high fidelity audio processing.

2. Related Art

Digital-to-analog converters (DACs) are used to process digital audio signals. Typically digital data signals are received from a digital replay device or over a network, such as a cable television network. The signals are then processed by a DAC in an audio amplifier, cable receiver, or other audio device to produce an analog output within a frequency range that, when connected to a transducer such as a speaker, generates human audible sounds.

DACs used in high-fidelity audio processing typical include digital modulators that convert highly over-sampled digital values from high precision (16-20 bits) to low precision (1-3 bits), with the objective of substantially eliminating noise from the human audible band.

To prepare these low precision signals for conversion to analog form, they are mapped into digital sequences to prevent parasitic elements from degrading the signal. This process is known as sequence mapping. An analog signal is then generated from the mapped digital signal and transmitted to audio reproduction equipment.

Dither signals are commonly generated in audio circuits to overcome the tendency of high-gain feedback amplification circuits to generate audible output tones (referred to as idle tones) during periods of low or zero input amplitude when the output should be low or zero. Dither signals in the form of white noise are typically introduced into the feedback circuit during periods of low input amplitude. However, this dithering function introduces a small but measurable amount of noise into the circuit and therefore reduces signal-to-noise ratios.

Known DACs are susceptible to various types of signal distortion, harmonics, dependency on past output, and generation of unwanted output at low signal input levels. These circuits achieve high fidelity output through high-precision digital signal processing. In this context the inventor has discovered that conventional sequence mapping processes may be responsible for introducing harmonic content that propagates to the output signal. Therefore, improvements in sequence mapping are desirable to improve the fidelity of these circuits.

SUMMARY OF THE INVENTION

An improved sequence mapping circuit and method for digital audio circuits generates a pulsed output. Over time, the mapping circuit generates pulses with a substantially identical average centroid for each of the possible output waveforms. For at least some of the output waveforms, two or more sets of pulses are provided representing the same waveform but having different centroids. The output is alternated among the available sets of pulses to maintain a desired average centroid over time. The shuffling of the output among the available pulses representing a given waveform may be randomly determined, or the pulses used may be tracked and alternated among the available output pulses. The shuffled mapping method disclosed herein reduces output harmonics compared to conventional static mappers.

These improved sequence mapping methods and circuits are particularly useful in the context of high-fidelity digital modulator circuits, and in combination with other novel features developed by the same inventor for such circuits. As disclosed herein, the improved sequence mapping methods are optionally and advantageously combined with particular improvements in spectral shaping of a dither signal, and with the inclusion of the mapping function in the circuit's main feedback loop.

DETAILED DESCRIPTION OF THE INVENTION

The invention will be described with reference to several exemplary embodiments.FIG. 1shows a first embodiment of the invention in the form of a digital modulator. In this embodiment, a pulse width modulation mapping function is performed within a high-gain digital modulator feedback loop, rather than subsequent to the feedback loop. InFIG. 1, the digital modulator is shown generally at100. Digital modulator100has an input102and an output138. The circuit of digital modulator100comprises a gain stage104, a summing point106, an integrator108, a gain stage110, a dither control input112, a dither generation circuit114, a gain stage116, a gain stage118, a summing point120, an integrator122, a gain stage124, a summing point126, an integrator128, a gain stage130, a summing point132, one or more clock inputs134, a gain stage140, and a mapping circuit136incorporating a quantizer142and a mapper144. Mapping circuit136has an input146and a feedback point148at its output138from which a feedback loop150extends to an input of each of gain stages116,118and140, respectively.

Digital modulator100, represented inFIG. 1, may be implemented in software operating on a general purpose processor, in hardware such as a custom integrated circuit, or in combinations thereof. Both hardware and software implementations are workable; hardware implementations currently have a lower cost and may be faster, and are generally preferred for these reasons.

The design of digital modulator100is particularly useful in high-fidelity audio applications such as cable television receivers (sometimes referred to as “set top boxes”). In the cable receiver application, digital modulator100converts highly over-sampled digital values from high precision (typically 16-20 bits) to low precision (1-3 bits). Quantization noise inherently increases with the reduction in precision. The digital modulation process is designed to push quantization noise out of the frequency band of interest, which in the case of a high-fidelity audio circuit is the human-audible band (typically between zero and no more than 40,000 Hz). The low-precision digital values are then quantized and mapped to digital sequences, for example by a pulse-width modulation process. The output of the circuit at output138is a digital bipolar pulse-width-modulated signal. In the exemplary cable receiver audio application, output138is connected through a low pass filter to an audio output jack (not shown).

Input102is connected to receive a high-precision digital signal (typically 18-20 bits) such as, for example, a digital cable TV audio signal or other high-precision information signal. Input102is connected to the input of gain stage104and is also connected as a control input to dither generation circuit114. When the received input signal at input102has a low amplitude (below a predetermined threshold), dither generation circuit114is activated to introduce a dither signal to prevent the circuit from generating audible idle tones at its output. The dither signal output of dither generation circuit114is connected to summing point132and may be generated conventionally, such as by operating a linear feedback shift register to generate a pseudo-random noise sequence. Or, in another embodiment of the invention, dither generation may be accomplished using the novel dithering circuits and methods described below with reference toFIGS. 5 and 6.

Each of gain stages104and116has an output connected to summing point106, the output of which is connected to an input of integrator108.

Integrator108has an output connected to an input of gain stage110. Gain stage110has an output connected to one input of summing point120.

As noted above, feedback loop150extends from feedback point148at output138of mapping circuit136back to the inputs of gain stages116,118and140, respectively. Gain stage118has an output connected to a second input of summing point120. The signals received at summing point120are transmitted to an input of integrator122. An output of integrator122is connected to an input of gain stage124. An output of gain stage124is connected to an input of summing point126. The output signal of gain stage140is provided to an input of summing point126. The sum of the signals received at summing point126is provided as an input to integrator128. An output of integrator128is connected to an input of summing point132. The sum of the signals transmitted to summing point132by integrator128and the output of dither generation circuit114is connected at an output146of summing point132to an input of quantizer142. Another feedback loop is connected from the output of integrator128(at its input to summing point132to the input of gain stage130, with the output of gain stage130connected to a third input of summing point120.

Table A shows exemplary gain values for the gain stages used in the circuit:

The gain values may be adjusted depending on the application and the bandwidth of both the input and the desired output. The example given has conjugate zeros of the filter established at about 23 kHz, providing a compromise between optimizing 20 kHz and 40 kHz output bandwidths.

Quantizer142converts data received from the modulator at output146to one of a plurality of voltage levels at one or more defined sampling rates. Quantizer specifications may be determined according to the requirements of the individual application. As an example, a seven-level quantizer that approximates the received data with an output belonging to the set consisting of {−6, −4, −2, 0, 2, 4, 6} works well in the application example described herein. Quantizer142has one or more clock inputs134, such that quantizer142is provided with or can derive a clock signal for each sampling rate desired during operation. For example, in the cable receiver example described herein, a sample rate of 27 Mhz may be established, with a 3.375 Mhz clock also available at one-eighth of the overall sample rate. A seven-level sample is generated at the 27 Mhz rate with a new level evaluated and output every eight clocks at the 3.375 Mhz rate. In this example, mapper144puts out an 8-bit sequence corresponding to the evaluated level for eight clock cycles. Then the level is re-evaluated and a new output level is initiated based on the new level determination.

Mapper144may be a conventional mapper, such as a static type mapper, or may be capable of a novel “shuffle mapping” approach as described below with reference to FIG.2and FIGS.3and/or4.

Feedback loop150differs from conventional feedback arrangements in that the modulator feedback loop typically includes the quantizer function only, and not the mapping function. That is, the feedback point is typically between quantizer142and mapper144in conventional systems of this type, and mapping functions are thus performed after the feedback loop. The inventor has discovered that the pulse width modulation mapping function of mapper144generates a fairly large harmonic content when cascaded with the digital modulator circuit and tends to dramatically change the shape of the noise floor in the desired band, e.g. 0-40,000 Hz. In contrast, placing the mapping function within high-gain digital modulator feedback loop150, as shown inFIG. 1, tends to compensate for the non-linear features of the mapping function, thus reducing harmonic generation and simplifying the task of suppressing harmonic generation to an acceptable level. In addition to reducing harmonic generation, this arrangement simplifies feedback processing and the accumulation of feedback information within the various integrators in the modulator circuit. The arrangement of the feedback loop and the generation of the same output signal for successive clock cycles suppresses harmonic content and pushes the noise floor back to its original shape. In exemplary implementations the signal-to-noise ratio (SNR) is 109 dB for 0-20,000 Hz and 96 dB for 0-40,000 Hz signal ranges, respectively.

FIG. 2is a block schematic diagram showing various embodiments and design options for an improved mapper200. The features disclosed herein with reference to mapper200may be implemented in combination with any or all of the other circuit features disclosed in this specification. Some or all of the features of mapper200may also implemented separately for use with any other type of circuit and/or application where a mapping is desired. As an example, mapper200may be used in generalized pulse width modulation applications or in other appropriate mapping processes where the features of mapper200provide useful advantages.

Mapper200, in the embodiment shown, comprises quantizer202, static mapper204, set shuffler mapper206, code shuffler mapper208, and mode selection switch210. Static mapper204has an input230, set shuffler mapper206has an input232, and code shuffler mapper208has an input234, respectively. Quantizer202has an input212to which an input signal is applied and an output connected to three points: input230of static mapper204, input232of set shuffler mapper206, and input234of code shuffler mapper208. Mapper200has an output214at mode selection switch210. Output214provides a pulse width modulated signal based on the level of the input signal at input212. A system clock216is connected to both quantizer202and mode selection switch210. Quantizer enable signal218is connected to quantizer202, and mapper enable signal220is connected to mode selection switch210. Quantizer enable signal218and mapper enable signal220are actuated by a control circuit (not shown) to enable the operation of quantizer202and the output of mapper200, respectively.

Mode selection switch210has three signal inputs (0,1,2) and a mode control input228. Static mapper204has an output222, set shuffler mapper206has an output224, and code shuffler mapper208has an output226. Outputs222,224and226are connected to the three inputs of mode selection switch210respectively. Mode selection switch210provides one of the signals received at its three inputs to its output214depending on the mode selected by a signal provided at mode control input228. In this way, mode selection switch210can be used to selectively transmit to mapper output214the output of static mapper204, set shuffler mapper206, or code shuffler mapper208depending on the desired mapping operation. The type of mapping to be used can be selected as desired by the operator in a manner that will be described later in more detail.

In cases where multi-mode operation is not required, it is not necessary to provide three different parallel mapping circuits selected through mode selection switch210as shown in FIG.2. Any single mapping circuit or any two of the mapping circuits can be selected if the other types of mapping operations are not required for the application. In the case of a single mapping circuit, either set shuffler mapper206or code shuffler mapper208is provided alone, without the other mapping circuits. In this case, if desired, mode selection switch210may be omitted so that the respective output of set shuffler mapper206or code shuffler mapper208is provided directly to output214.

In the embodiment shown, quantizer202is a seven-level quantizer that receives a digital representation of an analog signal level and generates an output that is one of seven levels from the set consisting of {6, 4, 2, 0, −2, −4, −6}. The selected output varies with the value of the input signal as follows: The expected range of input levels is divided into, in this case, seven sub-ranges. The value of the input signal is determined in response to a level change in system clock216. Then, the sub-range to which the input signal value belongs is determined, and the voltage level output corresponding to that sub-range is generated. In a preferred embodiment, the same voltage level output is maintained for eight clock cycles. Thereafter the level may change to a new value for the next eight clock cycles, as the process repeats beginning with the determination of the value of the input signal.

In operation, static mapper204receives one of the seven voltage levels and generates a serial digital output corresponding to that level. One appropriate serial digital bit sequence for this static mapping is illustrated in Table B.

FIG. 7is a waveform diagram corresponding to the bit sequences of Table B.FIGS. 7athrough7gshow waveforms702,706,710,714,718,722and726produced at the output of static mapper204, corresponding to level numbers 1 through 7 in Table B respectively. Waveforms702,706,710,714,718,722and726have time-based centroids704,708,712,716,720,724and728respectively. As can be seen inFIGS. 7athrough7g,the centroid position varies; centroids704,712,720and728are located at t=4.5 clock cycles from the beginning of the pulse output, while centroids708,716and located at t=5 clock cycles after the beginning of the pulse output.

Based on experimental analysis, the inventor has identified this shifting of centroids as a source of non-linearity in the mapper output, and has determined that centroid shifting is a significant source of harmonic generation in the circuit. The inventor has further determined that if the centroids of the output waveforms can be kept at the same time point measured from the start of each waveform, non-linearities and thus harmonic levels are substantially reduced.

FIGS. 7h,7iand7jshow waveforms that are identical to the waveforms shown inFIGS. 7b,7dand7frespectively, but are time-shifted by one clock cycle. Pulse730inFIG. 7hhas a duration of two clock cycles, corresponding to pulse706inFIG. 7b.Pulse733inFIG. 7ihas a duration of four clock cycles, corresponding to pulse714inFIG. 7d.Pulse736inFIG. 7jhas a duration of six clock cycles corresponding to pulse722inFIG. 7f.Pulses730,733and736have centroids732,734, and738respectively. Centroids732,734and738are located at t=4 clock cycles, rather than at t=5 clock cycles as in the case of pulses706,714, and722. The pulses shown inFIGS. 7h,7iand7jconstitute a set of pulses (referred to as Set A) with centroids at t=4, and the pulses shown inFIGS. 7b,7dand7fconstitute a set of pulses (referred to as Set B) having centroids at t=5. The inventor has discovered that if an equal number of otherwise identical pulses from Set A and Set B are transmitted, over time the average centroid of the resulting transmission will be at t=4.5. Exemplary serial bit transmission sequences for Set A and Set B outputs are shown in Table C.

Referring again toFIG. 2, the operation of set shuffler mapper206and code shuffler mapper208will now be described in further detail. These shuffler mappers reduce output harmonics compared to static mapper204by maintaining a substantially identical average centroid for each of the seven possible output waveforms. In general, this objective is accomplished by generating waveforms using the bit sequences shown in Table C, alternating between Set A and Set B. More than two sets could be used if desired as long as the sets provide the desired centroid output when used in combination.

An embodiment of set shuffler mapper206operates according to the flow chart of FIG.3.FIG. 3shows a process300for shuffling between the Set A and Set B outputs shown in Table C. The process begins at block302where a tracking flag is initialized. The initialization is optional and the initial setting of the flag may be selected arbitrarily, since the output will merely be shuffled over time between settings corresponding to the two possible tracking flag values.

Next, in block304, the process determines whether output shuffling is required, based on the input value. In this example, output shuffling is required when the input value is −4, 0, or 4. In the embodiment shown, for input values −6, −2, 2, and 6, the Set A and Set B outputs are identical so no output shuffling is required. Thus, if the input value is not −4, 0, or 4, control passes to block305and the output sequence is transmitted as shown in Table C with no differences between Set A and Set B operation. If output shuffling is required, control passes to block306. If the tracking flag was set, Set B output is indicated; if the tracking flag was not set, Set A output is indicated. Thus, in Block306, if the tracking flag is set control passes to block312and the Set B serial bit sequence corresponding to the input value is generated; the tracking flag is then reset in block314. If the tracking flag is not set, control passes to block308and the Set A serial bit sequence corresponding to the input value is generated, after which the tracking flag is set in block310. After these output operations and flag setting operations, control returns to block304where the next input is processed. Thus, the process ofFIG. 3generates outputs that alternate between Set A and Set B for those serial bit sequences with a waveform centroid differing from an overall average centroid location.

In the embodiment shown, inputs −6, −2, 2, and 6 generate output sequences with a waveform centroid centered at t=4.5 clock cycles. For the other three input values, −4, 0 and 4, the process ofFIG. 3alternates between generating waveforms from a set with centroids at t=4 clock cycles (Set A) and waveforms from a set with centroids at t=5 clock cycles. This operation produces seven different output waveforms, each with a time-averaged centroid at t=4.5 clock cycles. Maintaining the same average centroid for each output waveform produces increased linearity of operation and reduces output harmonics.

FIG. 4shows a process flow chart for an embodiment of code shuffler mapper208(shown in FIG.2). This process will describe code shuffling for a mapper with a seven-level quantizer input as shown inFIG. 2, and can also be easily adapted by those skilled in the art to operate with a different input structure. Code shuffling process400begins at block402where three flags are initialized—one each for the −4, 0, and 4 voltage input levels. In general, in code shuffling process400, a flag is provided for each input level that will generate shuffled pulse outputs. The determination of whether to initialize the flags to one or zero is arbitrary, and in fact initialization can be omitted if desired. The flag will be inverted each time the input corresponds to the voltage level corresponding to that flag, and the output will shuffle alternately between the settings corresponding to flag=0 and flag=1; over time it will not matter which of the shuffled outputs was generated first.

Next, the value of the input is determined and a branching operation is performed based on the input level starting at block404. If the input level is −4, control passes to block410. If the input level is zero, control passes from block404to block406and then to block420. If the input level is +4, control passes through block406to block408and then to block420. If the input level is another value, i.e. a value that will not involve shuffling in this embodiment, control passes to block440where the non-shuffled pulse corresponding to the input level is generated as an output. The process then begins again at block404.

If the input level is −4, the value of the −4 flag is evaluated at block410. If this flag is set, the Set B pulse for level −4 is generated as an output at block412, the −4 flag is reset at block414to complete the operation, and control passes back to block404. If the −4 flag is not set, the Set A pulse for level −4 is generated as an output at block416, the −4 flag is set at block418to complete the operation, and control passes to block404.

If the input level is zero, the value of the zero flag is evaluated at block420. If this flag is set, the Set B pulse for level zero is generated as an output at block422, the zero flag is reset at block424to complete the operation, and control passes back to block404. If the zero flag is not set, the Set A pulse for level zero is generated as an output at block426, the zero flag is set at block428to complete the operation, and control passes to block404.

If the input level is +4, the value of the +4 flag is evaluated at block430. If this flag is set, the Set B pulse for level +4 is generated as an output at block432, the +4 flag is reset at block434to complete the operation, and control passes back to block404. If the +4 flag is not set, the Set A pulse for level +4 is generated as an output at block436, the +4 flag is set at block438to complete the operation, and control passes to block404.

As can be seen, code shuffler mapping process400differs from set shuffler mapping process300(shown inFIG. 3) in that code shuffler mapping process400tracks output corresponding to each of the input levels with individual flags, and shuffles the output codes individually for each such input level. That is, in the set shuffler mapping process, each time an even-width pulse is to be generated, it is generated with a shifted centroid relative to the last even-width pulse generated. In the code shuffler mapping process, each time a pulse is generated with width=2 (or width=4 or 6) is generated, it is generated with a centroid shifted relative to the last pulse generated with width=2 (or 4 or 6), regardless of the centroid status of other recent even-width pulses. The code shuffler mapping process requires additional data storage in the form of flag bits and a marginal increase in program code to implement the branching operations, but these additional storage requirements can be met without significant difficulty if the code shuffler mapping process is considered desirable for a particular application.

As can be seen, embodiments of the shuffler mappers take two sequences defined for each level, with different pulse centroids, and chooses each of the two sequences 50% of the time. The result of this operation is that the average output centroid corresponding to the level is midway between the pulse centroids of two sequences that are alternately generated. Some code levels have an output with a single pulse that has the desired centroid location; the output corresponding to these code levels is not shuffled.

In the embodiments described herein for both set shuffler mapper206and code shuffler mapper208the shuffled pulse outputs are those outputs having a pulse width of an even number of bits or clock cycles. In particular the pulses of width 2, 4, and 6 are shuffled while the pulses with width 1, 3, 5, and 7 are not shuffled. It should be noted that it is also possible to reverse this structure and shuffle the odd-width pulses while generating the even-width pulses with a constant centroid. For example, the even width pulses may be generated so their centroids are at t=4 and the odd width pulses may each be alternated (shuffled) between centroids of t=3.5 and t=4.5 to likewise generate an average centroid at t=4. In the seven-level embodiments shown, it is preferred to shuffle the even-width pulses because shuffling a pulse of width 7 (shown inFIG. 7g) would raise the first bit of each byte in half of those pulse generations. Having a “Ø” as the first bit ensures that all 8 bit sequences start from the same level, therefore eleminating sequence-to-sequence interaction.

FIG. 5is a block schematic diagram showing a modification of the circuit ofFIG. 1to provide spectral shaping of a dither signal. In general, a dither signal is a random word sequence added to the quantizer input of the modulator to break up idle tones which would otherwise be generated due to inherent circuit characteristics when the input data stream is “idle,” e.g. has a low input amplitude.

FIG. 5shows the modulator circuit100modified to incorporate an improved dither generation circuit502. Dither generation circuit502includes pseudo-random number (PRN) generator circuit504and filter circuit506. Input102, the high speed data input of the modulator circuit, is connected to input510of PRN generator circuit504. A control input508is also connected to PRN generator circuit504. PRN generator circuit504monitors input510to determine when the input signal level has an amplitude below a predetermined threshold, such that a dither signal should be generated to prevent idle tone outputs from the modulator circuit. PRN generator circuit504provides circuitry for generating a pseudo-random number sequence. For example, PRN generator circuit504may incorporate a linear feedback shift register. Control input508provides further activating control signals to the PRN generator circuit to control the generation of dither signals. For example, dither signals may be enabled or disabled by an external control circuit depending on operational requirements.

The output of PRN generator circuit504is connected to filter circuit506. Filter circuit506is a high-pass filter (HPF) circuit. The output of HPF filter circuit506is connected to summer132; thus the dither signal output generated by dither generation circuit502is added to the signal at output146provided to quantizer142.

The inventor has found that pre-filtering the dither signal using HPF filter circuit506before the dither signal is added to the quantizer input reduces signal-to-noise ratio degradation. In particular, for the modulator application it is desirable to filter the dither signal so it has little or no energy in the audio band. In particular, the energy of the signal should be concentrated in the band above 20 kHz and even more preferably in the band above 40 kHz. Pre-filtering of the dither signal can be accomplished using several methods, either individually or in combination. The first method involves the generation and interpretation of the noise signal used to generate the dither. As noted previously, a linear feedback shift register can be used to produce a pseudo-random number sequence in the dither generator. The bits of the shift register in the linear feedback shift register are then formed as digital words that can be used in a variety of formats. The inventor has discovered that the choice of format affects the quality of the output. If the shift register output words are interpreted as offset binary words, a constant can be subtracted from each value in the sequence to produce a DC mean of zero. This results in a white (flat) noise spectrum usable as a dither signal. The inventor has discovered that interpreting the shift register output as 2's complement binary words produces a signal that is immediately bipolar and has an inherent high-pass characteristic. In addition to interpreting the generated pseudo-random numbers as 2's complement words, the resulting words are preferably passed through a first order difference network with a zero at DC. Combining these two methods produces a dither signal with approximately a 40 dB per decade slope having a high-pass characteristic. This reduces noise resulting from the introduction of dither in the low pass band and increases the overall signal-to-noise ratio of the modulator.

The inventor has found that pre-filtering the dither signal before adding it to the quantizer input as described above effectively minimizes dither energy in the audio band, thereby reducing degradation of the signal-to-noise ratio occurring in more conventional dither circuits.

The dithering methods disclosed herein are particularly useful in circuits of the type shown inFIG. 5; however, those skilled in the art will recognize that the improved dithering methods disclosed herein can be applied to other types of circuits including dithering functions.

FIG. 6is a flow chart showing the generation of a dither signal according to an embodiment of the improved method disclosed herein. Dither generation process600begins with generation of a pseudo-random number (PRN) in block602. Then, in block604, the PRN is interpreted as a 2's complement number representing a bipolar signal. In block606, the resulting value is high-pass filtered, and in block608the filtered bipolar value is added to the signal input of the quantizer as a dither signal.