Structure for circuit assembly

A structure for circuit assembly is applied to positional alignment in bonding process. The structure for circuit assembly comprises a first substrate, having a plurality of first terminals and both a first alignment mark and a second alignment mark located in the vicinity of the first terminals, and a second substrate, having a plurality of second terminals and a transmissive area located in the vicinity of second terminals. During the first substrate bonding with the second substrate, as the edge of the transmissive area is located between the first alignment mark and the second alignment mark, and the first alignment mark is outside of the transmissive area, the first terminals are normally connected with the second terminals.

BACKGROUND OF THE INVENTION

(1) Field of the Invention

The invention relates to a structure for circuit assembly, specifically to such a structure which is used for circuit assembly of a display apparatus.

(2) Description of the Prior Art

Assembly for display normally uses the technology of tape automated bonding (TAB) or of chip on glass bonding (COG), and so on. Compared to TAB, COG uses less amount of flexible circuit boards and printed circuit boards, and thereby can reduce the production cost.

For further reducing the demand of the amount of flexible circuit boards and the layers of printed circuit board to gain more cost benefit, those products using the technology of COG also apply the wiring-on-array (WOA) on array substrate to cascade driver chips. Among the cascaded driver chips, data and control signals are transmitted only to the first driver chip, and thereafter they can be delivered to the other cascaded driver chips. As a result, the amount of wiring on the flexible circuit board and printed circuit board can be reduced, and the cost can be further decreased. Because driver chips are cascaded with the WOA on the array substrate, thereby simplifying the design for printed circuit board and reducing the number of layers of circuit board can lead to further cost down.

Because function of signals on gate drivers is less than those on source drivers, the number of connections required for gate drivers is relatively limited. It thus makes it easier to design the peripheral layout surrounding the display area and the arrangement of bonding pads to the design with cascade. For the cost-down requirement today, an attempt to cascade source drivers has become a dedicated approach field in the panel manufacture. While there are a number of function of signals on the source drivers, the flexibility of design for the peripheral layout will be restricted by the limit of size of a flip-chip; moreover, it has increased the difficulty to be compatible with the present process, such as using the same testing method, module tools, and so on. Therefore, how to improve the design of WOA on the array substrate so as to further reduce the cost of components on panel has become a request to achieve in the panel manufacture.

Refer toFIG. 1A, showing a conventional display. A panel10comprises a display area11, a plurality of source drivers12, and a plurality of gate drivers13disposed at the surrounding of the display area11. The source drivers12and the gate drivers13respectively connect with printed circuit boards17aand printed circuit boards17bvia respective flexible circuit boards20. As shown inFIG. 1B, on the panel10, an area14between two source drivers, the driver12aand the driver12bwhich are not cascaded but adjacent to each other, only keeps a few of dummy patterns16and an alignment structure15, providing for circuit assembly of the panel10and the flexible circuit board20.

As shown inFIG. 1C, the alignment structure15includes an alignment mark151. While assembling the panel10and the flexible circuit board20, a positional alignment is examined for the board20though a transmissive area21which is light-transmissive and the alignment mark151on the panel10. If the alignment mark151is properly positioned inside the transmissive area21, the pads121the from source driver12are aligned to leads22of the flexible circuit board20. As shown inFIG. 1D, while the location of the transmissive area21shifts from that of the mark151, this means that the location of the pad121also shifts from that of the lead22. However, the degree of assembly shift is not very clear for visual check.

As shown from the layout design in the figure, the edge of every panel10is required to keep the alignment mark151during a bonding process. Because these alignment marks151are located between two drivers and their positions can not be changed arbitrarily under the limitation of manufacturing tools, the space between every two adjacent leads of the drivers can not be effectively utilized for constructing prospective wiring. In particular, the demand in increasing number of contacts for the source drivers can't be met and thereby the pattern design with the WOA on array substrate is greatly limited.

SUMMARY OF THE INVENTION

The object of the present invention is to provide a structure for circuit assembly where the layout between two driver chips is took as a portion of the alignment structure so that consideration to both the design for WOA on array substrate and the improvement of the alignment precision for circuit assembly can be involved.

The structure for circuit assembly in the present invention is applied to the positional alignment for bonding two substrates with different material, such as the bonding of a display panel and a flexible circuit board. The structure for circuit assembly comprises a first substrate having a plurality of first terminals, a second substrate having a plurality of second terminals. Both a first alignment mark and a second alignment mark are included to be located in the vicinity of the first terminals, while a transmissive area located in the vicinity of the second terminals. In the case that the first substrate is bonded with the second substrate, that the edge of the transmissive area is located between the first alignment mark and the second alignment mark, and that the first alignment mark is located outside the transmissive area, then the first terminals are normally connected with the second terminals.

The first alignment mark as above can be a conductive pattern, a wiring, or an ID mark such as chip ID or plate ID, and so on. As to a display panel where the first alignment mark and the second alignment mark are located between two adjacent driver chips, the spacing between the alignment mark and the pattern surrounding the mark provides a novel method for checking the precision of positional alignment as a double-check effect to make sure whether the terminals are aligned and whether the deviation of alignment is within the tolerance. In addition, the utilization of the area between two driver chips for wiring layout can also raise the flexibility of design for WOA on array substrate.

DESCRIPTION OF THE PREFERRED EMBODIMENT

According to accompanying figures attached, the structure for circuit assembly in present invention is illustrated in details, and preferred embodiments are listed and described as following.

Refer toFIG. 2, showing a preferred structure for circuit assembly in accordance with the present invention. The structure30for circuit assembly is located on a first substrate31and a second substrate32. The first substrate31has a plurality of first terminals311, a first alignment mark33and a second alignment mark34, both located at the same side where the first terminals311are located. The second substrate32has a plurality of second terminals321and a transmissive area322, located at the side where the second terminals321are located. In the case that the first substrate31joins the second substrate32, that the edge of the transmissive area322is located within the distance D between the first alignment mark33and the second alignment mark34, and that the first alignment mark33is located outside the transmissive area322, the first terminals311can then contact with the respective second terminals321.

The structure as above for circuit assembly located at a bonding part of the two boards is applicable to various displays and the like, such as the electronic products having a bonding structure on circuit boards or a bonding structure between a circuit board and a panel. This can lead to a hike in accuracy of the alignment while leads join. In the present invention, the first substrate31can be a liquid crystal panel with a thin film transistor array or an organic illuminating panel, where the first terminal311can be connected to the driver chip on the panel. The second substrate32can be a flexible substrate such as a flexible printed circuit board. The transmissive area322can be an empty area without any wire as shown inFIG. 2, or be formed by employing an edge line drawn on the second transparent substrate32or by drilling a hole on the second substrate32. The first alignment mark33and the second alignment mark34can be light-proof structures of any shape but with a proper distance D in between as a tolerant range for the rim shift of the transmissive area. The first alignment mark33can be a conductive pattern, a track of wiring, or an ID mark, which will be described respectively in the following embodiments.

Refer toFIGS. 3A-3C, showing embodiments using a conductive pattern as the first alignment mark33and illustrating a preferred alignment method in accordance with the present invention. The conductive pattern35on the first substrate31covers a side area of the first terminal311and connects the first terminal311but reserving an uncovering area313. A circular second alignment mark34is disposed inside the uncovering area313at a distance D from the conductive pattern35. The transmissive area322on the second substrate32is also circular for matching the shape of the second alignment34, while in another preferred embodiment its diameter may be somewhat bigger than that of the circular second alignment mark34but smaller than the width of the uncovering area.

As shown inFIG. 3A, in the case that the second substrate32joins the first substrate31, and that the rim323of the transmissive area322is located at the center of the distance D between the conductive pattern35and the second alignment mark34, it represents that the first terminals311are exactly aligned on the second terminals321. As shown inFIG. 3B, if the rim323of the transmissive area322is located at the intersection of the conductive pattern35and the uncovering area313, it indicates that the first terminals311are not completely aligned on the second terminals321. This, however, is still within the range of deviation tolerance. As shown inFIG. 3C, when the rim323of transmissive area322is outside the intersection area of the conductive pattern35and the uncovering area313and when the rim323goes into the cover area of the conductive pattern35, the first terminals311are completely away from the second terminals321without any contact, or with only little contact but not reaching the quality requirement of manufacturing.

FIGS. 3A-3Calso symbolize an method for the alignment of circuit assembly in accordance with the present invention. Firstly, an anisotropic conductive film (ACF) is adhered onto a plurality of the first terminals311in advance while an alignment reference mark312can be used for reference. When the second substrate32overlaps the first substrate31, the situation that the rim323of the transmissive area322falls inside the distance D between the conductive pattern35and the second alignment mark34is determined so as to verify whether the first terminals311and the second terminal321are aligned to each other. If the situation inFIG. 3Awere met, a thermal clamp is used for bonding the first terminals311and the second terminals321together by using the anisotropic conductive film. Compared to technologies shown inFIGS. 1C-1Dwhere the conventional technology can only verify whether the leads are aligned, the technology in the present invention can further employ the width of the distance D to specify the tolerant range of alignment deviation, and therefore the effectiveness on double-checks can be obtained.

Refer toFIG. 4, showing an embodiment of the present invention using wiring as first alignment mark33. The area aside the first terminals311can be arbitrarily routed with wires, such as an outer short ring36(OSR) inFIG. 4for preventing from possible electro-static discharge damage. A second alignment mark34is located between the ring36and the first terminals311by a distance D from the ring36for providing an alignment check.

Refer toFIG. 5, showing an embodiment of the present invention using ID marks such as Chip IDs, glass Plate IDs and so on as the first alignment marks33. The second alignment mark34can be disposed between a ID mark37and a spare dummy leads38on the first substrate31, and the mark34is spaced a distance D from the mark37for providing an alignment check.

As in the above embodiments, the first alignment mark33and the second alignment mark34can be made of a metal material such as an aluminum, molybdenum, chromium, any alloy involving the forgoing metals, and so on. The distance D between the first alignment mark33and the second alignment mark34can be from 50 μm to 150 μm; preferably, 100 μm. The second alignment mark34can be a circle mark with a diameter from 150 μm to 250 μm so as to fit the area between the first terminal311and the first alignment mark33. Now the transmissive area34is specified with a circle area having a diameter from 250 μm to 350 μm, i.e. having an area larger than that of the second alignment mark. Therefore, the tolerance for aligning the first substrate31to the second substrate32is about ±50 μm.

Refer toFIG. 6, showing a structure of bonding pad connecting the first terminals in accordance with the present invention. While there are other parts on the first substrate31, a bonding pad39is normally used for connecting the first terminals311with those components to provide for transmitting the signals from the second substrate32to the components on the first substrate31. The structure of bonding pad39comprises a first conductive layer391formed on the first substrate31and contacted with the first terminals311, an dielectric layer392located on a first conductive layer391and having a via3921, and a second conductive layer393connected with the first conductive layer391through the via3921. The other end of the first conductive layer391is connected with a thin film transistor40while the second conductive layer393is connected with a driver chip50, a source driver chip or a gate driver chip.

Refer toFIG. 7A, where a liquid crystal display is used as an instance for illustrating a typical application for the structure for circuit assembly in accordance with the present invention. A liquid crystal display70has a liquid crystal panel71communicating with a printed circuit board73through a flexible circuit board72. On the liquid crystal panel71, a plurality of cascaded driver chips are shown to have cascaded source driver chips711and cascaded gate driver chips712. As the example of the source driver chips711while referring toFIG. 7BandFIG. 3A, the chips711are mounted on the array substrate by using the method of chip on glass bonding (COG), thereafter cascaded by wiring on array (WOA) on the array substrate, and thereby extended to have a plurality of the leads311. The flexible printed circuit board72has a plurality of the second terminals321and a transmissive area322located in the vicinity of the second terminals321.

FIG. 7Bshows an enlarged view for the junction part74of the liquid crystal panel71and the flexible circuit board72. The conductive pattern35and the second alignment mark34are constructed between two adjacent source driver chips,711aand711b. When the bonding pad of the liquid crystal panel71overlaps on the flexible circuit board72, the edge of transmissive area322is disposed between the conductive pattern35and the second alignment mark34so as to have the conductive pattern35located outside the transmissive area322. Upon such an arrangement, the first terminals311can align respectively to the second terminals321.

The comparison betweenFIG. 7BandFIG. 1Bshows that the conductive pattern35is a new design for wiring on array substrate where an empty area for avoiding the second alignment mark34can be used to relieve the space aside the junction area for further designing a variety of wiring, such as the wiring714for cascading driver chips711aand711b. Therefore, both the compatibility of the existing manufacturing system and the precision of alignment can be enhanced, and the production cost can be substantially reduced.

The technology of the present invention, while compared to the conventional technology, has the following advantages over the conventional design:1. No change in the bonding tool for the existing machines is required. Thus, the introduction of new designs for modules can be expedited and the compatibility of manufacturing process can be raised.2. It increases the accuracy of the alignment check for the fine pitch bonding process.3. It raises the flexibility of design for wiring on array (WOA) on glass substrate and increases the area for additional wires.4. Under the situation that the second alignment mark is fixed, the bonding area between two adjacent driver chips can be used for the design of wiring on array (WOA) on the glass substrate.5. It employs the distance between the alignment mark and its surrounding wires for checking the accuracy of alignment.6. The effectiveness on double-checks can be assured.

The above detailed description is a substantial illustration for the preferred embodiments of the present invention. However, the embodiments as above should not be construed as limiting the scope of the invention. Any equivalent embodiment or minor modification will not exempt from infringing the object of this present invention and should be included within the scope of patent in this case.