Display apparatus and driving method therefor

A display apparatus disclosed herein includes a plurality of pixel circuits, each having a plurality of switches configured to receive a driving signal of a predetermined period and to be controlled for opening and closing operation by the driving signal, a drive circuit configured to control the open/closed state of the switches, being operable to scan the pixel circuits and open and close the switches in periods independent of each other.

CROSS REFERENCES TO RELATED APPLICATIONS

The present invention contains subject matter related to Japanese Patent Application JP 2007-092809, filed in the Japan Patent Office on Mar. 30, 2007, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to an active matrix type display apparatus from among display apparatus wherein pixel circuits are arrayed in a matrix, such as an organic electroluminescence (EL) display apparatus, and a driving method for the active matrix type display apparatus.

2. Description of the Related Art

In an image display apparatus such as, for example, a liquid crystal display (LCD) apparatus (hereinafter referred to as LCD apparatus), a large number of pixels are arrayed in a matrix and the intensity of light is controlled for each pixel in response to image information to be displayed to display an image.

Meanwhile, an organic EL display apparatus is a display apparatus of the self luminous display apparatus wherein each pixel circuit includes a light emitting device. The organic EL display apparatus is advantageous when compared with the LCD apparatus in that it is high in visual observability of a display image, no backlight is required and the response speed is high.

Further, the luminance of each light emitting device is controlled with the value of current flowing through the light emitting device to obtain a gradation of color development. In other words, the organic EL display apparatus is much different in characteristic from the LCD apparatus in that the light emitting device is of the current controlled type.

A simple matrix type driving system and an active matrix type driving system are available as a driving system for an organic EL display similarly to an LCD apparatus. Although the former system is simple in structure, it is not suitable to implement a display apparatus of a large size and a high definition. Therefore, development of the latter active matrix type driving system wherein an active device provided in the inside of each pixel circuit, usually a thin film transistor (TFT), is used for control is proceeding energetically.

Here, a principle of operation of a typical active matrix type organic EL display apparatus is described.

FIG. 1shows a configuration of a typical organic EL display apparatus.

Referring toFIG. 1, the display apparatus10shown includes a pixel array section12wherein pixel circuits (PXLC)12aare arrayed in a m×n matrix, a horizontal selector (HSEL)13, a vertical scanner (VSCN)14, data lines DTL1to DTLn selected by the horizontal selector13that is supplied with a data signal according to luminance information, and scanning lines WSL1to WSLm selectively driven by the vertical scanner14.

It is to be noted that the horizontal selector13and/or the vertical scanner14may be formed on polycrystalline silicon or formed from a MOSIC or the like and formed around the pixels.

An example of a configuration of the pixel circuits12ashown inFIG. 1is shown inFIG. 2.

Referring toFIG. 2, a pixel circuit20has the simplest circuit configuration among various circuit configurations proposed heretofore.

The pixel circuit20includes a p-channel TFT21, an n-channel TFT22, a capacitor C21, and a light emitting device23formed from an organic EL device (OLED).

The TFT21of the pixel circuit20is connected at the base thereof to a power supply potential VDD and at the gate thereof to the drain of the TFT22. The light emitting device23is connected at the anode thereof to the drain of the TFT21and at the cathode thereof to a reference potential GND, which may be, for example, the ground potential.

The TFT22of the pixel circuit20is connected at the source thereof to a data line DTL (DTL1to DTLn) of a corresponding column and at the gate thereof to a scanning line WSL (WSL1to WSLm) of a corresponding row. The capacitor C21is connected at one terminal thereof to the power supply potential VDD and at the other terminal thereof to the drain of the TFT22.

It is to be noted that, since an organic EL device in most cases has a rectification property, it is sometimes called an OLED (Organic Light Emitting Diode) and is represented using a symbol of a diode as a light emitting device inFIG. 2and so forth. However, in the following description, the rectification property is not necessarily required for the OLED.

Where the pixel circuit20having such a configuration as described above is used, and when luminance data are to be written into such pixels, a pixel row including the pixels is selected through a corresponding scanning line WSL by the vertical scanner14, and the TFT22in the pixels of the row is turned on.

At this time, the luminance data is supplied in the form of a voltage from the horizontal selector13through the data line DTL and written into the capacitor C21for retaining a data voltage through the TFT22.

The luminance data written in the capacitor C21is retained for a period of one field. The retained data voltage is applied to the gate of the TFT21.

Consequently, the TFT21drives the light emitting device23with electric current in accordance with the retained data. At this time, a gradation representation of the light emitting device23is carried out by modulating gate-source voltage Vdata (<0) of the TFT21retained by the capacitor C21.

It is to be noted that, since the TFT transistors used in the configuration example ofFIG. 2behave as switch devices, in the following description, the switch devices can be formed from a n-channel TFT, a p-channel TFT or any other switch device.

Generally, the luminance Loled of an organic EL device increases in proportion to the current Ioled flowing through the organic EL device. Accordingly, the luminance Loled and the current Ioled of the light emitting device23satisfy the following expression (1):
Loled∝Ioled=k(Vdata−Vth)  (1)
where k=½·μ·Cox·W/L. Here, μ is the mobility of the carriers in the TFT21, Cox the gate capacitance of the TFT21per unit area, W the gate width of the TFT21, and L the gate length of the TFT21.

Accordingly, the dispersion of the mobility μ and the threshold voltage Vth (<0) of the TFT21have a direct influence on the dispersion of the luminance of the light emitting devices23.

In this instance, for example, even if the same potential Vdata is written into different pixels, the threshold voltage Vth of the TFT21disperses among the different pixels. Consequently, the current Ioled flowing through the light emitting device23disperses by a great amount among different pixels, and is displaced by a great amount from a desired value. As a result, a high picture quality cannot be expected with the display apparatus.

A large number of pixel circuits which solve the problem just described have been proposed, and a representative one of such pixel circuits is shown inFIG. 3.

Referring toFIG. 3, the pixel circuit30shown includes a p-channel TFT31, n-channel TFTs32to34, capacitors C31and C32, and a light emitting device (OLED)35formed from an organic EL device. InFIG. 3, also, a data line DTL, a scanning line WSL, an auto zero line AZL and a driving line DSL are shown.

The operation of the pixel circuit30is described below with reference toFIGS. 4A to 4E.

The signal on the driving line DSL and the auto zero line AZL are set to the high level, as seen inFIGS. 4A and 4B, to place the TFT32and the TFT33into a conducting state, respectively. At this time, current flows through the TFT31because the TFT31is connected in a diode-connection state to the light emitting device35.

Then, the signal on the driving line DSL is set to the low level to place the TFT32into a non-conducting state as seen inFIG. 4A. At this time, the scanning line WSL is placed into the high level state, as seen inFIG. 4C, to place the TFT34into a conducting state. Consequently, a reference potential Vref is applied to the data line DTL, as seen inFIG. 4D. Since the current flowing to the TFT31is interrupted thereby, the gate potential Vg of the TFT31rises, as seen inFIG. 4E. However, at a point in time at which the gate potential Vg rises to a potential of VDD−|Vth|, the TFT31enters a non-conducting state and the potential is stabilized. This operation is hereinafter referred to sometimes as an “auto zero operation”.

Then, the auto zero line AZL is set to the low level to place the TFT33into a non-conducting state and the potential at the data line DTL is set to a potential lower than the reference potential Vref by a voltage AVdata. The variation of the signal line potential lowers the gate potential of the TFT31by a voltage AVg through a capacitor C31, as seen fromFIG. 4E.

Then, if the scanning line WSL is set to the low level to place the TFT34into a non-conducting state and the driving line DSL is set to the high level to place the TFT32into a conducting state, as seen inFIGS. 4A and 4C, respectively, then current flows through the TFT31and the light emitting device35. Consequently, the light emitting device35begins to emit light.

If the parasitic capacitance can be ignored, then the voltage ΔVg and the gate potential Vg of the TFT31are determined in accordance with the following expression (2) and (3), respectively:
ΔVg=ΔVdata×C1/(C1+C2)  (2)
Vg=VCC−|Vth|−ΔVdata×C1/(C1+C2)  (3)
where C1is the capacitance value of the capacitor C31, and C2the capacitance value of a capacitor C32.

On the other hand, where the current flowing through the light emitting device35upon light emission is represented by Ioled, the current Ioled is controlled by the TFT31connected in series to the light emitting device35. If it is assumed that the TFT31operates in a saturation region, then a relationship given by the following expression (4) can be obtained using a well-known expression of the MOS transistor and the expression (3) above:

Ioled=μ⁢⁢CoxW/L/2⁢⁢(VCC-Vg-Vth)⁢⁢2=μ⁢⁢CoxW/L/2⁢⁢(Δ⁢⁢Vdata×C⁢⁢1/(C⁢⁢1+C⁢⁢2))⁢⁢2(4)
where μ is the mobility of the carrier, Cox the gate capacitance per unit area, W the gate width, and L the gate length.

According to the expression (4), the current Ioled is controlled with the potential ΔVdata provided from the outside independently of the threshold voltage Vth of the TFT31. In other words, if the pixel circuit30ofFIG. 3is used, then a display apparatus which is comparatively high in uniformity of the current, and hence in uniformity of the luminance without being influenced by the threshold voltage Vth which disperses among different pixels can be implement.

The pixel circuit described above is disclosed, for example, in U.S. Pat. No. 5,684,365, Japanese Patent Laid-Open No. Hei 8-234683 or JP-2002-514320T.

SUMMARY OF THE INVENTION

Although the particular example described above is an example of a solution to the elimination of the non-uniformity of luminance by the dispersion in TFT characteristic, as can be recognized even from a reference toFIG. 3or4, generally, a plurality of control signal lines, such as the scanning line WSL and the driving line DSL, are required in order to control one pixel circuit.

Now, a driving method for a pixel circuit in a typical active matrix type organic EL display apparatus is described. For a simplified description, a driving method wherein a scanning signal propagated along a scanning line WSL to control writing into pixel circuits and a driving signal propagated along a driving line DSL to control light emitting devices35are used is described.

FIG. 5shows a display apparatus10ain the form of an active matrix type organic EL display apparatus. Referring toFIG. 5, the display apparatus10aincludes pixel circuits30, a horizontal selector (HSEL)13, a vertical scanner (VSCN)14and a drive scanner (DSCN)15. Such pixel circuits30, as shown inFIG. 3, are arrayed in a 480×n matrix in a pixel array section. The pixel circuits30are individually connected to the horizontal selector13by data lines DTL1to DTLn, the vertical scanner14by scanning lines WSL1to WSL480, and the drive scanner15through driving lines DSL1to DSL480.

The vertical scanner14, the drive scanner15, and the horizontal selector13successively drive the scanning lines WSL1to WSL480, driving lines DSL1to DSL480and data lines DTL1to DTLn in accordance with a clock signal to select a predetermined pixel circuit30and carry out writing into the selected pixel circuit30.

The vertical scanner14includes shift registers SRW1to SRW480and logic circuits LW1to LW480for 480 stages therein. The shift registers SRW1to SRW480are connected in series, and the logic circuits LW1to LW480are connected to the shift registers SRW1to SRW480for the individual stages, respectively.

A start signal SCLK1of a period equal to that for writing into the pixel circuits30is inputted to the shift register SRW1at the first stage. Further, clock signals CLK1of the same period are inputted in parallel to the shift registers SRW1to SRW480.

The shift registers SRW1to SRW480individually output an input signal to the logic circuits LW1to LW480, each formed from a plurality of devices, and the logic circuits LW1to LW480carry out a predetermined process for the input signal so that scanning signals are propagated along the scanning lines WSL1to WSL480.

The drive scanner15has shift registers SRD1to SRD480and logic circuits LD1to LD480for 480 stages provided therein. The shift registers SRD1to SRD480are connected in series, and the logic circuits LD1to LD480are connected to the shift registers SRW1to SRW480for the individual stages, respectively.

To the shift register SRD1at the first stage, a start signal SCLK2of a period equal to that of the driving signal for controlling the TFT32of the pixel circuit30is inputted. Further, clock signals CLK2of the same period are inputted in parallel to the shift registers SRD1to SRD480.

The shift registers SRD1to SRD480output an input signal to the logic circuits LD1to LD480, each formed from a plurality of devices, and the logic circuits LD1to LD480carry out a predetermined process for the input signal so that driving signals are propagated along the driving lines DSL1to DSL480, respectively.

A set of shift registers are provided for one scanning signal outputted from the vertical scanner14, and similarly a set of shift registers are provided for one driving signal outputted from the drive scanner15. However, general active matrix type organic EL display apparatuses also have a similar configuration.

Now, the operation of the vertical scanner14and the drive scanner15is described with reference toFIGS. 6A to 6T.

FIGS. 6A to 6Tillustrates the operation of the vertical scanner14and the drive scanner15in the display apparatus10a. In particular,FIG. 6Aillustrates the clock signal CLK1;FIG. 6Billustrates the start signal SCLK1;FIGS. 6C to 6Jillustrate scanning signals propagated along the scanning lines WSL1to WSL244;FIG. 6Killustrates the clock signal CLK2;FIG. 6Lillustrates the start signal SCLK2; andFIGS. 6M to 6Trepresent driving signals propagated along the driving lines DSL1to DSL244, respectively. It is to be noted that the scanning signals and the driving signals illustrated inFIGS. 6C to 6Tillustrate only parts thereof.

It is assumed that, as seen inFIGS. 6C to 6J, an on/off scanning signal is propagated once along the scanning lines WSL1to WSL480within a period of one field, and as seen inFIGS. 6M to 6T, an on/off driving signal is propagated twice within a period of one field. It is to be noted that the scanning lines WSL and the driving lines DSL illustrated inFIGS. 6C to 6Tillustrate only part of the signal lines. Further, it is assumed that, in an initial state, input and output signals of all shift registers SRW are set to the low level.

The clock signal CLK1is inputted to the shift registers SRW1to SRW480of the vertical scanner14, as seen inFIG. 6A, and the clock signal CLK2is inputted to the shift registers SRD1to SRD480of the drive scanner15, as seen inFIG. 6K.

Meanwhile, the start signal SCLK1is inputted to the shift register SRW1at the first stage, as seen inFIG. 6B, and the start signal SCLK2is inputted to the shift register SRD1at the first stage, as seen inFIG. 6L.

It is to be noted that the clock signals CLK1and CLK2of 480 pulses are inputted to the shift registers SRW1to SRW480and shift registers SRD1to SRD480within a period of one field, respectively.

The start signal SCLK1inputted to the shift register SRW1at the first stage is successively shifted to the shift registers SRW2to SRW480in synchronism with the clock signal CLK1. Then, the shift registers SRW1to SRW480successively propagate a scanning signal to the scanning lines WSL1to WSL480through the logic circuits LW1to LW480, as seen inFIGS. 6C to 6J, respectively, to control the TFT34(refer toFIG. 3) of the pixel circuits30.

Also, the drive scanner15operates similarly to the vertical scanner14and successively propagates a driving signal to the driving lines DSL1to DSL480, as seen inFIGS. 6M to 6T, to control the TFT32(refer toFIG. 3) of the pixel circuits30similarly as in the operation of the vertical scanner14.

Incidentally, an active matrix type organic EL display apparatus includes a number of driving signal lines which is greater than that in a general active matrix type LCD apparatus which requires only one scanning line for one pixel circuit. Further, the active matrix type organic EL display apparatus has an increased size of peripheral elements of a circuit for production of driving signals, because a greater number of driving signal lines are required, and since the driving signal lines are produced using TFTs on a glass substrate, a framework of an increased size is required for the display apparatus. This gives rise to a problem that the power consumption is increased thereby.

One of solutions to the problem described above is to use a set of shift registers for one pixel to produce a plurality of output signals of different drive circuits.

Now, an example of the solutions to the problem described above is described with reference toFIGS. 7 and 8Ato8R.

FIG. 7shows an example of a display apparatus10baccording to the solution example to the problem.

Referring toFIG. 7, the display apparatus10bis configured so as to use a set of shift registers and a logic circuit to carry out writing into a pixel. A vertical scanner14ahas a configuration similar to that of the vertical scanner14ofFIG. 5and includes shift registers SR1to SR480and logic circuits L1to L480for individual rows of pixel circuits30. The logic circuits L1to L480are connected to the pixel circuits30for individual rows through the scanning lines WSL1to WSL480and the driving lines DSL1to DSL480, respectively.

Now, the operation of the vertical scanner14ais described with reference toFIGS. 8A to 8R.

FIGS. 8A to 8Rare timing charts illustrating the operation of the vertical scanner14ain the display apparatus10b.FIG. 8Aillustrates the clock signal CLK;FIG. 8Billustrates the start signal SCLK;FIGS. 8C to 8Jillustrate scanning signals propagated along the scanning lines WSL1to WSL244; andFIGS. 8K to 8Rillustrate driving signals propagated along the driving lines DSL1to DSL244. It is to be noted that the signals on the scanning lines and the driving lines are illustrated at only a part thereof.

As seen inFIGS. 8C to 8J, an on/off scanning signal and a driving signal are propagated once within a period of one field along the scanning lines WSL1to WSL480and the driving lines DSL1to DSL480.

It is to be noted that it is assumed that, in an initial state, the inputs and outputs of all of the shift registers SRW are set to the low level. Further, the clock signal CLK of 480 pulses is inputted to the shift registers SR1to SR480within a period of one field.

In the vertical scanner14ashown inFIG. 7, the clock signal CLK is inputted to the shift registers SR1to SR480of the vertical scanner14a(FIG. 8A) and the start signal SCLK is inputted to the shift register SR1at the first stage (FIG. 8B) similarly as in the vertical scanner14of the display apparatus10adescribed hereinabove.

The start signal SCLK inputted to the shift register SR1at the first stage is successively shifted to the shift registers SR2to SR480in synchronism with the clock signal CLK1.

Then, the shift registers SR1to SR480successively propagate an input signal to the scanning lines WSL1to WSL480, as seen inFIGS. 8C to 8J, through the logic circuits L1to L480to control the TFT34(refer toFIG. 3) of the pixel circuits30.

If a signal delayed by one half clock is used for the driving signal, then the TFT32of the pixel circuits30can be controlled, for example, using the scanning signal of the scanning line WSL2as a driving signal for the driving line DSL1, as seen inFIG. 8K.

If the number of an arbitrary shift stage of a shift register is represented by i, then the driving signal propagated along the driving line DSL(i) is equal to the scanning signal propagated to the scanning line WSL(i+1), and a plurality of driving signals can be outputted from one set of shift registers.

However, although the method described above can be used if the on/off periods of signals propagated along a scanning line WSL and a driving line DSL are the same, where such a plurality of scanner signals as seen inFIGS. 6C to 6Jare used and different operations having different on/off periods are carried out for the individual scanner signals, desired scanner signals cannot be produced. Therefore, the method described above cannot be used as it is.

Therefore, it is demanded to provide a display apparatus and a driving method therefor by which shift registers can be used commonly for a plurality of scanner signals having different periods from each other while the shift registers are scanned with the same clock.

According to an embodiment of the present invention, there is provided a display apparatus including a plurality of pixel circuits, each having a plurality of switches configured to receive a driving signal of a predetermined period that is to be controlled for an opening and closing operation by the driving signal, and a drive circuit configured to control the open/closed state of the switches, the drive circuit being operable to scan the pixel circuits and open and close the switches in periods independent of each other.

Preferably, the drive circuit is divided into a desired plural number of regions for the pixel circuits in the scanning direction, and selects only a desired one of the divisional regions with a select signal and controls the open/closed state of the switches in the selected divisional region.

In this instance, preferably, the display apparatus is configured such that each of the pixel circuits includes a first switch connected to a first driving line controlled in a first period, and a second switch connected to a second driving line controlled in a second period, and the drive circuit including a plurality of shift registers connected in series. Each of the shift registers has a first input to which a clock signal of a predetermined period is inputted and a second input, with one of the shift registers which is at a first stage receiving a signal of a predetermined period at the second input thereof, and the drive circuit being configured to successively select the divisional regions with the select signal and control the first and second switches in the first and second periods in response to input and output states of the shift registers.

Preferably, the display apparatus is configured such that each of the pixel circuits includes an electro-optical device, a drive transistor configured to drive the electro-optical device with a write signal to emit light, a first switch configured to be opened and closed with a first scanning signal, and a second switch configured to be opened and closed with the second scanning signal to supply the write signal to a control terminal for the drive signal, and the drive circuit being configured to set the second opening and closing period longer than the opening and closing period of the first switch and drive the second switch in the second opening and closing period.

According to another embodiment of the present invention, there is provided a driving method for a display apparatus which includes a plurality of pixel circuits, each including a plurality of switches configured to receive a driving signal of a predetermined period and to be controlled for an opening and closing operation by the driving signal, including a step of scanning the pixel circuits in the predetermined period and controlling the switches individually in periods independent of each other.

In the display apparatus and the driving method therefor, the plural switches of each pixel circuit receive driving signals from the drive circuit and are controlled so as to be opened and closed with the driving signals. At this time, the switches are controlled so as to be opened and closed in the periods independent of each other.

With the display apparatus and the driving method therefor, since the shift registers can be shared among a plurality of scanning signals having different periods from each other, a reduction in size of the framework can be implemented.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

A preferred embodiment of the present invention is explained by referring to diagrams as follows.

FIG. 9shows an example of a configuration of an organic EL display apparatus to which the present invention is applied, andFIG. 10shows an example of a particular configuration of a pixel circuit employed in the organic EL display apparatus.

Referring toFIGS. 9 and 10, the display apparatus100includes a pixel array section102wherein pixel circuits101are arrayed in a m×n matrix, a horizontal selector (HSEL)103, a vertical scanner (VSCN)104serving as a drive circuit, a first auto zero circuit (AZRD1)105and a second auto zero circuit (AZRD2)106.

Each of the pixel circuits101is connected to the horizontal selector103by a data line DTL and connected to the vertical scanner104by a scanning line WSL for controlling writing into the pixel circuits101and a driving line DSL for driving a light emitting device. Further, each pixel circuit101is connected to the first auto zero circuit105by a first auto zero line AZL1serving as a third driving line and connected to the second auto zero circuit106by a second auto zero line AZL2serving as a fourth driving line.

In the following description, it is assumed that the pixel array section102includes pixel circuits101arrayed in a 480 (=m)×n matrix.

Each of the pixel circuits101includes a p-channel TFT111which corresponds to a second switch, n-channel TFTs112and113, a further n-channel TFT114which corresponds to a first switch, a still further n-channel TFT115, a capacitor C111, a light emitting device116formed from an organic EL device, a first node ND111and a second node ND112.

In the pixel circuit101, the TFT111, the TFT112serving as a driving transistor, the first node ND111and the light emitting device116are all connected in series between the first reference voltage, power supply potential VCC, and the second reference potential, the ground potential Vcathode, which are in the present embodiment. More particularly, the light emitting device116is connected at the cathode thereof to the ground potential Vcathode and at the anode thereof to the first node ND111. The TFT112is connected at the source thereof to the first node ND111, the TFT111is connected at the drain thereof to the drain of the TFT112, and the TFT111is connected at the source thereof to the power supply potential VCC.

The TFT112is connected at the gate thereof to the second node ND112, and the TFT111is connected at the gate thereof to a driving line DSL. The TFT113is connected at the drain thereof to the first node ND111and the first electrode of the capacitor C111and at the source thereof is fixed at the potential VSS2. Further, the TFT113is connected at the gate thereof to a second auto zero line AZL2. Further, the capacitor C111is connected at a second electrode thereof to the second node ND112.

The source and the drain of the TFT114are connected to and between the data line DTL and the second node ND112. The TFT114is connected at the gate thereof to a scanning line WSL. Further, the source and the drain of the TFT115are connected to and between the second node ND112and a predetermined potential Vssl. The TFT115is connected at the gate thereof to a first auto zero line AZL1.

When a scanning signal propagated along the scanning line WSL has a high level, the TFT114exhibits an on state and writing into the pixel is carried out.

On the other hand, when the driving signal propagated along the driving line DSL has a low level, the TFT111exhibits an on state and current flows to the light emitting device116so that the light emitting device116emits light.

Now, a first example of a configuration of the vertical scanner104is described.

FIRST CONFIGURATION EXAMPLE

FIG. 11shows the first configuration example of the vertical scanner104.

The vertical scanner104of the display apparatus100shares shift registers for a plurality of signals having different periods while scanning the shift registers with the same clock. The following description is given focusing on the vertical scanner104for a simplified illustration and description. Therefore, a description of the first auto zero circuit105, second auto zero circuit106, first auto zero line AZL1, and second auto zero line AZL2is omitted here.

The pixel circuits101are connected to the horizontal selector103by data lines DTL1to DTLn and connected to the vertical scanner104by scanning lines WSL1to WSL480and driving lines DSL1to DSL480.

The shift registers SR1to SR480are connected in series and have the logic circuits L1to L480connected thereto for individual shift stages. Clock signals CLK of the same period are inputted to the shift registers SR1to SR480, and a start signal SCLK having a driving period for the light emitting devices is inputted to the shift register SR1at the first stage.

The vertical scanner104shown inFIG. 11is divided into a first region REG1including the shift registers SR1to SR240and the logic circuits L1to L240disposed on the first to 240th shift stages, respectively, and a second region REG2including the shift registers SR241to SR480and the logic circuits L241to L480disposed on the 241st to 480th shift stages, respectively.

In the present configuration example, in order to change over between the first region REG1and the second region REG2, the vertical scanner104includes a select signal line SLCTL, a first select signal line SLCTL1, a second select signal line SLCTL2, an inverter1041, inverters1042for the 480 stages, and AND gates1043for the 480 stages.

As seen inFIG. 11, the select signal line SLCTL is distributed to the first select signal line SLCTL1and the second select signal line SLCTL2. Further, the inverter1041is connected to the first select signal line SLCTL1so as to invert a signal inputted to the vertical scanner104.

First Region REG1

In the first region REG1, each of the logic circuits L1to L240is connected at a first output terminal thereof to a second input terminal of an AND gate1043and at a second output terminal thereof to an input terminal of an inverter1042, each by a signal line. The AND gate1043is connected at a first input terminal thereof to the second select signal line SLCTL2and at the second input terminal thereof to a first output terminal of one of the logic circuits L1to L240on the corresponding stage, each by a signal line, and connected at an output terminal thereof to the pixel circuit101on the same stage by a corresponding one of the scanning lines WSL1to WSL240. The inverters1042are connected to the pixel circuits101of the same stages by the driving lines DSL1to DSL240, respectively.

Second Region REG2

In the second region REG2, each of the logic circuits L241to L480is connected at a first output terminal thereof to a second input terminal of an AND gate1043and at a second output terminal thereof to an input terminal of an inverter1042, each by a signal line. The AND gate1043is connected at a first input terminal thereof to the second select signal line SLCTL2and at the second input terminal thereof to a first output terminal of one of the logic circuits L241to L480on the corresponding stage, each by a signal line. Further, the AND gate1043is connected at an output terminal thereof to those of the pixel circuits101and one of the scanning lines WSL241to WSL480on the same stage. The inverters1042are connected to the pixel circuits101of the same stages by the driving lines DSL241to DSL480.

Now, the selection of the regions REG1and REG2in the present configuration example is described.

Selection of the First Region REG1

If a select signal SLCT propagated to the select signal line SLCTL is changed over to the high level, then the signal level of the second select signal line SLCTL2is hereafter held at the high level, and the signal level of the first select signal line SLCTL1is changed over to the low level by the inverter1041. Accordingly, the scanning lines WSL1to WSL240disposed in the first region REG1are selected by the AND gates1043, and writing is carried out only into those pixel circuits101, which are connected to the scanning lines WSL1to WSL240.

Selection of the Second Region REG1

If the select signal SLCT propagated to the select signal line SLCTL is changed over to the low level, then the signal level of the first select signal line SLCTL1is changed over to the high level by the inverter1041, and the signal level of the second select signal line SLCTL2is changed over to the low level. Accordingly, the scanning lines WSL241to WSL480disposed in the second region REG2are selected by the AND gates1043, and writing is carried out only into those pixel circuits101that are connected to the scanning lines WSL241to WSL480.

To the driving lines DSL1to DSL480, output signals of the logic circuits L1to L480are propagated irrespective of the select signal SLCT. When any of the output signals has the high level, the signal level is inverted to the low level by the inverter1042, and consequently, the TFT111(refer toFIG. 10) of the pixel circuits101connected to a corresponding one of the driving lines DSL1to DSL480is turned on and the light emitting device116emits light.

In short, if the select signal SLCT is kept at the high level, then writing into the pixel circuits101in the first region REG1is enabled, but if the select signal SLCT is kept at the low level, then writing into the pixel circuits101in the second region REG2is enabled.

Now, a circuit configuration of the vertical scanner104in the present configuration example is described.

FIG. 12shows an example of a circuit configuration of the vertical scanner104.

Referring toFIG. 12, shift transistors SR(i) to SR(i+2) are connected in series. The shift transistors SR(i) to SR(i+2) have a clock input terminal CK, an inverted clock input terminal XCK, an input terminal IN and an output terminal OUT, to which a clock signal CLK, an inverted clock signal XCLK, and an input signal INS are inputted and from which an output signal OUTS is outputted, respectively. Further, logic circuits L(i) to L(i+2) include an AND gate122and an inverter123. Here, the suffix i indicates a shift register or the like on the ith stage.

For example, the ith shift register SR(i) is connected at the input terminal IN thereof to a first input terminal of the AND gate122and at the output terminal OUT thereof to an input terminal of the inverter123and an input terminal of the output buffer124through a node NDi.

The inverter123is connected at the input terminal thereof to the node NDi and at an output terminal thereof to a second input terminal of the AND gate122.

The AND gate122is connected at the first input terminal thereof to the input terminal IN of the shift register SR(i), at the second input terminal thereof to the output terminal of the inverter123and at an output terminal thereof to a second input terminal of the AND gate1043. The AND gate1043is connected at a first input terminal thereof to the select signal line SLCTL, at the second input terminal thereof to the output terminal of the AND gate122and at the output terminal thereof to the input terminal of the output buffer124.

The output buffer124is connected at the input terminal thereof to the output terminal of the AND gate1043and at an output terminal thereof to the scanning line WSL(i). The inverter1042is connected at the input terminal thereof to the node NDi and at an output terminal thereof to the driving line DSL(i).

It is to be noted that the select signal line SLCTL shown inFIG. 12represents one of the select signal lines SLCT1and SLCT2. For example, where the shift register SR(i) is disposed in the first region REG1, the select signal line SLCTL represents the second select signal line SLCTL2, but where the shift register SR(i) is disposed in the second region REG2, the select signal line SLCTL represents the first select signal line SLCTL1.

A similar connection scheme also is used for the shift registers SR(i+1) and SR(i+2).

Now, the operation of the components of the vertical scanner104is described taking the ith shift register SR(i) as an example.

The driving line DSL(i) reflects the output signal OUTS of the shift register SR(i) irrespective of the select signal SLCT. The output signal OUTS of the shift register SR(i) is inverted in signal level by the output buffer124. When the output signal OUTS has the high level, the light emitting device emits light, but when the output signal OUTS has the low level, the light emitting device emits no light.

(A) Operation when the Select Signal SLCT is Kept at the High Level is Described.

If the shift register SR(i) receives the input signal INS of the high level and outputs the output signal OUTS of the low level, then the AND gate122receives a signal of the high level at the first input terminal thereof and receives a signal of the high level inverted by the inverter123at the second input terminal thereof. Then, the AND gate122outputs a signal of the high level.

Then, the AND gate1043receives a signal of the high level at the first input terminal thereof and receives a signal of the high level outputted from the AND gate122at the second input terminal thereof. Then, the AND gate1043propagates a signal of the high level to the scanning line WSL(i).

Then, if the shift register SR(i) receives the input signal INS of the high level and outputs the output signal OUTS of the high level, then the AND gate122receives a signal of the high level at the first input terminal thereof and a signal of the low level inverted by the inverter123at the second input terminal. Then, the AND gate122outputs a signal of the low level.

Then, the AND gate1043receives a signal of the high level at the first input terminal thereof and a signal of the low level outputted from the AND gate122at the second input terminal thereof, and outputs a signal of the low level. The output buffer124receives a signal of the low level from the AND gate1043and propagates a signal of the low level to the scanning line WSL(i).

Then, if the shift register SR(i) receives the input signal INS of the low level and outputs the output signal OUTS of the high level, then the AND gate122receives a signal of the low level at the first input terminal thereof and receives a signal of the low level inverted by the inverter123at the second input terminal thereof. Then, the AND gate122outputs a signal of the low level.

Then, the AND gate1043receives a signal of the high level at the first input terminal thereof and receives a low level signal outputted from the AND gate122at the second input terminal thereof, and outputs a signal of the low level. The output buffer124receives a signal of the low level from the AND gate1043and propagates a signal of the low level to the scanning line WSL(i).

On the other hand, if the shift register SR(i) receives the input signal INS of the low level and outputs the output signal OUTS of the low level, then the AND gate122receives a signal of the low level at the first input terminal thereof and receives a signal of the high level inverted by the inverter123at the second input terminal thereof. Then, the AND gate122outputs a signal of the low level.

Then, the AND gate1043receives a signal of the high level at the first input terminal thereof and receives a signal of the low level outputted from the AND gate122at the second input terminal thereof, and outputs a signal of the low level. The output buffer124receives a signal of the low level from the AND gate1043and propagates a signal of the low level to the scanning line WSL(i).

(B) Operation when the Select Signal SLCT is Kept at the Low Level is Described.

Since a signal of the low level is inputted to the first input terminal of the AND gate1043, the output of the AND gate1043exhibits the low level. Accordingly, the scanning line WSL(i) exhibits the low level irrespective of the signal level of the input and output signals of the shift register SR(i).

As described above, only when a state of the select signal SLCT is selected and the shift register SR(i) receives the input signal INS of the high level and outputs the output signal OUTS of the low level, a signal of the high level is propagated to the scanning line WSL(i) to carry out writing of pixels.

Now, the operation of the shift registers according to the present configuration example is described.

FIG. 13shows an example of an equivalent model of the shift registers.

Referring toFIG. 13, the shift register SR(i) according to the present configuration example has a clock input terminal CK, an inverted clock input terminal XCK, an input terminal IN and an output terminal OUT.

The shift register SR(i) operates at a rising edge of a clock signal CLK and an inverted clock signal XCLK.

FIGS. 14A to 14Dillustrate the operation of the shift register shown inFIG. 13.

The clock signal CLK illustrated inFIG. 14Aand the inverted clock signal XCLK illustrated inFIG. 14bare inputted to the clock input terminal CK and the inverted clock input terminal XCK, respectively.

If the input signal INS illustrated inFIG. 14Cis inputted to the input terminal IN of the shift register SR(i), then since the input signal INS has the low level, the shift register SR(i) outputs such an output signal OUTS of the low level, as seen inFIG. 14D, from the output terminal OUT and then keeps the low level until a next rising edge of the clock signal CLK.

Then, at the second rising edge of the clock signal CLK, since the input signal INS has the high level, the shift register SR(i) outputs the output signal OUTS of the high level and keeps the output signal OUTS of the low level until a next third rising edge of the clock signal CLK.

At the third rising edge of the clock signal CLK, since the input signal INS has the low level, the shift register SR(i) outputs the output signal OUTS of the low level and keeps the output signal OUTS of the low level until a fourth rising edge of the clock signal CLK (not shown).

In this manner, the shift register SR(i) successively shifts the input signal INS by one stage in synchronism with the clock signal CLK and outputs the shifted input signal INS.

Now, the operation of the vertical scanner104is described with reference toFIGS. 15A to 15S.

FIGS. 15A to 15Sare timing charts of the vertical scanner104according to the present configuration example. In particular,FIGS. 15A to 15Cillustrate the clock signal CLK, the start signal SCLK and the select signal SLCT, respectively;FIGS. 15D to 15Killustrate scanning signals propagated along the scanning lines WSL1to WSL244; andFIGS. 15L to 15Sillustrate driving signals propagated along the driving lines DSL1to DSL244. It is to be noted that the scanning signals and the driving signals illustrated inFIGS. 15D to 15Sonly show part thereof.

As seen fromFIGS. 15D to 15K, an on/off scanning signal is propagated once within a period of one field along each of the scanning lines WSL1to WSL480, and as seen fromFIGS. 15L to 15S, an on/off driving signal is propagated twice within a period of one field along the driving lines DSL1to DSL480. It is to be noted that, in an initial state, the input and output signals of all the shift registers SR1to SR480are set to the low level.

As seen inFIG. 15A, the clock signal CLK of 480 pulses is inputted to each of the shift registers SR1to SR480of the vertical scanner104within a period of one field, and as seen inFIG. 15B, the start signal SCLK is inputted to the shift register SR1at the first stage.

Further, the shift registers SR1to SR480receive the input signal INS and output the output signal OUTS to the logic circuits L1to L480.

As seen inFIG. 15A, the clock signal CLK is inputted to the shift registers SR1to SR480. Further, such a start signal SCLK, as seen inFIG. 15B, is inputted to the shift register SR1. The start signal SCLK has a period of a scanning signal equal to twice that of the driving signal, that is, it has the period of emission of light of the light emitting device116illustrated inFIG. 10

The select signal SLCT is kept at the high level, as seen inFIG. 15C, until the 240th stage in the first region REG1is scanned and then kept at the low level on the 241st to 480th stages in the second region REG2.

Within the period in which the select signal SLCT is kept at the high level, the first region REG1is selected, but within the period within which the select signal SLCT is kept at the low level, the second region REG2is selected.

At a first rising edge of the clock signal CLK, the start signal SCLK of the high level illustrated inFIG. 15Bis inputted to the shift register SR1. Further, at this time, the output signal OUTS of the shift register SR1is kept at the initial low level.

Accordingly, as seen inFIG. 15D, the scanning line WSL1is changed over to the high level and is kept at the high level until a next rising edge of the clock signal CLK while writing into the pixels on the scanning line WSL1is carried out.

Since both the input signal INS and the output signal OUTS of the shift registers SR2to SR480have the low level, the scanning lines WSL2to WSL480are kept at the low level and writing into the pixel circuits101is not carried out. Further, the output signals OUTS of all the shift registers SR1to SR480and the driving lines DSL1to DSL480are kept at the low level, and the light emitting devices116do not emit light.

At a second rising edge of the clock signal CLK, the input signal INS of the shift register SR1is kept at the high level, as seen inFIG. 15B.

The shift register SR1shifts the input signal INS by an amount corresponding to one half clock, and the output signal OUTS of the shift register SR1and the input signal INS of the shift register SR2are changed over to the high level. Further, output signal OUTS of the shift register SR2and the input and output signals of the shift registers SR3to SR480are all kept at the low level.

Accordingly, as seen inFIG. 15E, the scanning signal of the scanning line WSL1is changed over to the low level, and the scanning signal of the scanning line WSL2is changed over to the high level. Then, the scanning signal of the scanning line WSL2is kept at the high level until a next rising edge of the clock signal CLK, and writing into the pixel circuits101on the scanning line WSL2is carried out. Further, as seen inFIG. 15L, the light emitting devices116on the driving line DSL1carry out first time light emission within a period within which the start signal SCLK is kept at the high level.

At a third rising edge of the clock signal CLK, the input signal INS of the shift register SR1is kept at the high level, as seen inFIG. 15B.

The shift register SR1shifts the input signal INS by one half clock, and the output signal OUTS of the shift register SR1and the input signal INS of the shift register SR2are kept at the high level.

The shift register SR2shifts the input signal INS by one half clock, and the output signal OUTS of the shift register SR2and the input signal INS of the shift register SR3are kept at the high level. Further, the output signal OUTS of the shift register SR3and the input and output signals of the shift registers SR4to SR480are kept at the low level.

Accordingly, as seen inFIG. 15F, the scanning signal of the scanning line WSL2is changed over to the low level and the scanning signal of the scanning line SL3is changed over to the high level and kept at the high level until a next rising edge of the clock signal CLK while writing into the pixel circuits101on the scanning line SL3is carried out. Further, as seen inFIG. 15M, the light emitting devices116on the driving line DSL2carry out first time light emission while the start signal SCLK is kept at the high level.

At a fourth rising edge of the clock signal CLK, the input signal INS of the shift register SR1is kept at the high level as seen inFIG. 15B.

The shift register SR1shifts the input signal INS by one half clock, and the output signal OUTS of the shift register SR1and the input signal INS of the shift register SR2are kept at the high level.

The shift register SR2shifts the input signal INS by one half clock, and the output signal OUTS of the shift register SR2and the input signal INS of the shift register SR3are kept at the high level.

The shift register SR3shifts the input signal INS by one half clock, and the output signal OUTS of the shift register SR3and the input signal INS of the shift register SR4are changed over to the high level. Further, the output signal OUTS of the shift register SR4and the input and output signals of the shift registers SR5to SR480are kept at the low level.

Accordingly, as seen inFIG. 15G, the scanning signal of the scanning line WSL3is changed over to the low level, and the scanning signal of the scanning line WSL4is changed over to and kept at the high level until a next rising edge of the clock input terminal CK while writing into the pixel circuits101on the scanning line WSL4is carried out. Further, as seen inFIG. 15N, the light emitting devices116on the driving line DSL3carry out first time light emission within a period within which the start signal SCLK is kept at the high level.

Thereafter, in the first region REG1within which the select signal SLCT is kept at the high level, the shift registers SR1to SR480successively shift the input signal INS by one stage by one half clock in synchronism with the clock signal CLK so that pulses of the scanning signal and the driving signal are successively propagated in the scanning direction until the 240th clock signal CLK is developed.

At the 241st rising edge of the clock signal CLK, the shift register SR240shifts the input signal INS by one half clock, and the output signal OUTS of the shift register SR240and the input signal INS of the shift register SR241are changed over to the high level. Further, the output signal OUTS of the shift register SR241and the input and output signals of the shift registers SR242to SR480are kept at the low level.

Accordingly, as seen inFIG. 15H, the scanning signal of the scanning line WSL240is changed over to the low level, and the scanning signal of the scanning line WSL241is changed over to the high level and kept at the high level until a next rising edge of the clock signal CLK while writing into the pixel circuits101on the scanning line WSL241is carried out.

Further, the light emitting devices116on the driving line DSL240carry out first time light emission within a period within which the start signal SCLK is kept at the high level.

At a 242nd rising edge of the clock signal CLK, the shift register S241shifts the input signal INS by one half clock, and the output signal OUTS of the shift register SR241and the input signal INS of the shift register SR242are changed over to the high level. Further, the output signal OUTS of the shift register SR242and the input and output signals of the shift registers SR243to SR480are kept at the low level.

Accordingly, as seen inFIG. 15I, the scanning signal of the scanning line WSL241is changed over to the low level, and the scanning signal of the scanning line WSL242is changed over to the high level and kept at the high level until a next rising edge of the clock signal CLK while writing into the pixel circuits101on the scanning line WSL242is carried out. Further, as seen inFIG. 15P, the light emitting devices116on the driving line DSL241carry out second time light emission within a period in which the start signal SCLK is kept at the high level.

Thereafter, in the second region REG2within which the select signal SLCT is kept at the low level, the shift register SR(i) shifts the input signal INS by one stage in one half clock in synchronism with the clock signal CLK until the 480th clock signal CLK is reached. Thus, pulses of the scanning signal and the driving signal are successively propagated in the scanning direction, as seen inFIGS. 15J to 15Kand15Q to15S.

As described above, according to the present configuration example, even if the signal periods of the scanning signal and the driving signal are different from each other, by dividing the vertical scanner104in the scanning direction and selectively using the select signals to select the divisional regions, scanning in the same clock period with the shared shift registers can be anticipated.

SECOND CONFIGURATION EXAMPLE

Now, a second configuration example of the vertical scanner is described.

FIG. 16shows the second configuration example of the vertical scanner.

Referring toFIG. 16, the vertical scanner104aof the second configuration example includes shift registers SR1to SR480and logic circuits L1to L480, similarly as in the vertical scanner104of the first configuration example, and has a connection scheme similar to that in the first configuration example. However, in the vertical scanner104a, the area thereof is divided into four regions in the scanning direction. The vertical scanner104afurther includes a decoder107for selecting a desired one of the divisional regions.

The following description is a simplified description principally of the vertical scanner104a. Therefore, the descriptions of the first auto zero circuit105, the second auto zero circuit106, and the first auto zero line AZL1and second auto zero line AZL2are omitted here.

In particular, the vertical scanner104aincludes a first region REG1composed of shift registers SR1to SR120and logic circuits L1to L120, a second region REG2composed of shift registers SR121to SR240and logic circuits L121to L240, a third region REG3composed of shift registers SR241to SR360and logic circuits L241to L360, and a fourth region REG4composed of shift registers SR361to SR480and logic circuits L361to L480.

In the present configuration example, in order to carry out the changeover of the regions REG1to REG4, the vertical scanner104aincludes a decoder107, a first select signal line SLCTL00, a second select signal line SLCTL01, a third select signal line SLCTL10, a fourth select signal line SLCTL11, inverters1042for 480 stages, and AND gates1043afor 480 stages.

First Region REG1

In the first region REG1, each of the logic circuits L1to L120is connected at a first output terminal thereof to a second input terminal of an AND gate1043aand at a second output terminal thereof to an input terminal of an inverter1042, each by a signal line. The AND gate1043ais connected at a first input terminal thereof to the first select signal line SLCTL00and at the second input terminal thereof to a first output terminal of a corresponding one of the logic circuits L1to L120, each by a signal line. The AND gate1043ais connected at an output terminal thereof to the pixel circuits101on the same stage by a corresponding one of the scanning lines WSL1to WSL120. The inverter1042is connected at an output terminal thereof to the pixel circuits101on the same stage by a corresponding one of the driving lines DSL1to DSL120.

Second Region REG2

In the second region REG2, each of the logic circuits L121to L240is connected at a first output terminal thereof to a second input terminal of an AND gate1043aand at a second output terminal thereof to an input terminal of an inverter1042, each by a signal line. The AND gate1043ais connected at a first input terminal thereof to the second select signal line SLCTL01and at the second input terminal thereof to a first output terminal of a corresponding one of the logic circuits L121to L240, each by a signal line. The AND gate1043ais connected at an output terminal thereof to the pixel circuits101on the same stage by a corresponding one of the scanning lines WSL121to WSL240. The inverter1042is connected at an output terminal thereof to the pixel circuits101on the same stage by a corresponding one of the driving lines DSL121to DSL240.

Third Region REG3

In the third region REG3, each of the logic circuits L241to L360is connected at a first output terminal thereof to a second input terminal of an AND gate1043aand at a second output terminal thereof to an input terminal of an inverter1042, each by a signal line. The AND gate1043ais connected at a first input terminal thereof to the third select signal line SLCTL10and at the second input terminal thereof to a first output terminal of a corresponding one of the logic circuits L241to L360, each by a signal line. The AND gate1043ais connected at an output terminal thereof to the pixel circuits101on the same stage by a corresponding one of the scanning lines WSL241to WSL360. The inverter1042is connected at an output terminal thereof to the pixel circuits101on the same stage by a corresponding one of the driving lines DSL241to DSL360.

Fourth Region REG4

In the fourth region REG4, each of the logic circuits L361to L480is connected at a first output terminal thereof to a second input terminal of an AND gate1043aand at a second output terminal thereof to an input terminal of an inverter1042, each by a-signal line. The AND gate1043ais connected at a first input terminal thereof to the fourth select signal line SLCTL11and at the second input terminal thereof to a first output terminal of a corresponding one of the logic circuits L361to L480, each by a signal line. The AND gate1043ais connected at an output terminal thereof to the pixel circuits101on the same stage by a corresponding one of the scanning lines WSL361to WSL480. The inverter1042is connected at an output terminal thereof to the pixel circuits101on the same stage by a corresponding one of the driving lines DSL361to DSL480.

The first select signal line SLCTL00, the second select signal line SLCTL01, the third select signal line SLCTL10, and the fourth select signal line SLCTL11are connected to the decoder107.

A select signal SLCT0and another select signal SLCT1are inputted to the decoder107. The decoder107carries out a predetermined process and outputs select signals SLCT00, SLCT01, SLCT10and SLCT11to the select signal lines SLCTL00, SLCTLO1, SLCTL10and SLCT11, respectively.

Now, the selection of the regions REG1to REG4in the present configuration example is described.

Selection of the First Region REG1

If the select signal SLCT0of the low level and the select signal SLCT1of the low level are inputted to the decoder107, then the decoder107outputs the select signal SLCT00of the high level, the select signal SLCT01of the low level, the select signal SLCT10of the low level, and the select signal SLCT11of the low level. At this time, the first region REG1is selected and writing into the pixel circuits101connected to the scanning lines WSL1to WSL120is carried out.

Selection of the Second Region REG2

If the select signal SLCT0of the high level and the select signal SLCT1of the low level are inputted to the decoder107, then the decoder107outputs the select signal SLCTO0of the low level, the select signal SLCT01of the high level, the select signal SLCT10of the low level, and the select signal SLCT11of the low level. At this time, the second region REG2is selected and writing into the pixel circuits101connected to the scanning lines WSL121to WSL240is carried out.

Selection of the Third Region REG3

If the select signal SLCT0of the low level and the select signal SLCT1of the high level are inputted to the decoder107, then the decoder107outputs the select signal SLCT00of the low level, the select signal SLCT01of the low level, the select signal SLCT10of the high level, and the select signal SLCT11of the low level. At this time, the third region REG3is selected and writing into the pixel circuits101connected to the scanning lines WSL241to WSL360is carried out.

Selection of the Fourth Region REG4

If the select signal SLCT0of the high level and the select signal SLCT1of the high level are inputted to the decoder107, then the decoder107outputs the select signal SLCT00of the low level, the select signal SLCT01of the low level, the select signal SLCT10of the low level, and the select signal SLCT11of the high level. At this time, the fourth region REG4is selected and writing into the pixel circuits101connected to the scanning lines WSL361to WSL480is carried out.

To the driving lines DSL1to DSL480, signals from the logic circuits L1to L480are propagated, respectively.

The operation of the present vertical scanner104ais described with reference toFIGS. 17A to 17X.

FIGS. 17A to 17Xillustrate the operation of the vertical scanner104aaccording to the present configuration example. In particular,FIG. 17Aillustrates the clock signal CLK;FIG. 17Billustrates the start signal SCLK;FIG. 17Cillustrates the select signal SLCT0;FIG. 17Dillustrates the select signal SLCT1;FIG. 17Eillustrates the select signal SLCT00;FIG. 17Fillustrates the select signal SLCT01;FIG. 17Gillustrates the select signal SLCT10;FIG. 17Hillustrates the select signal SLCT11;FIGS. 17I to 17Pillustrate scanning signals propagated to the scanning lines WSL1to WSL362; andFIGS. 17Q to 17Xillustrate driving signals propagated to the driving lines DSL1to DSL362. It is to be noted that the scanning signals and the driving signals illustrated inFIG. 17only are shown at a part thereof.

An on/off scanning signal is propagated once within a period of one field to the scanning lines WSL1to WSL480, and an on/off driving signal is outputted four times within a period of one field to the driving lines DSL1to DSL480. It is to be noted that the input and output signals of the shift registers SR1to SR480initially have the low level.

As seen inFIG. 17A, the clock signals CLK of the same period are inputted to the shift registers SR1to SR480. Further, as seen inFIG. 17B, the start signal SCLK of a period equal to four times the period of light emission of the light emitting devices116is inputted to the shift register SR1at the first stage.

As seen inFIG. 17C, a signal of a period equal to twice the period of the start signal SCLK is propagated to the select signal SLCT0. Further, another signal of a period four times that of the start signal SCLK is propagated to the select signal SLCT1, as seen inFIG. 17D.

Then, as seen inFIGS. 17E to 17H, the decoder107outputs the select signals SLCT00, SLCT01, SLCT10and SLCT11in response to the signal levels of the select signal SLCT0and the select signal SLCT1.

In the second configuration example, the decoder107successively selects the regions REG1to REG4in order, and the vertical scanner104acarries out scanning in the scanning direction in synchronism with the clock signal CLK similarly as in the first configuration example.

The scanning signal generated at a rising edge of such a clock signal CLK, as seen inFIG. 17I, is successively shifted, as seen inFIGS. 17J to 17P, in synchronism with the clock signal CLK to carry out writing into the pixel circuits101.

Further, the drive signal generated at a rising edge of such a clock signal CLK, as seen inFIG. 17Q, is successively shifted, as seen fromFIGS. 17R to 17X, in synchronism with the clock signal CLK, and the light emitting devices116emit light four times within a period of one field.

Further, in the present configuration example, while the select signals SLCT00, SLCT01, SLCT10and SLCT11have such a signal period that one of them keeps the high level once at any timing, they may otherwise have a different signal period, in which one of them keeps the high level twice.

Further, in the present configuration example, the select signals SLCT00, SLCT01, SLCT10and SLCT11for the four divisional regions are provided only with regard to the scanning signal. If select signals for three divisional regions are provided with regard to the driving signals, then the scanning period of the scanning signals can be set to a non-integral multiple, such as 4/3, times the driving period of the driving signals.

Further, in the first and second configuration examples, the driving signals of the driving lines DSL1to DSL244have a frequency equal to twice or four times that of the scanning signals of the scanning lines WSL1to WSL244. If the driving signals of the driving lines DSL1to DSL244have such a plurality of frequency components, as are represented by logically ORing a signal of a frequency equal to twice or four times that of the scanning signals and its corresponding frequency of the scanning lines WSL1to WSL244, then a combination of signals may be carried out by a logic circuit again after a region is selected by the select signals.

With the first and second configuration examples described above, even if the periods of a scanning signal and a driving signal are different from each other, scanning with the same clock frequency can be executed by dividing the region of a vertical scanner in the scanning line direction and selectively using the divisional regions.

With the display apparatus and the driving method thereof according to the present invention, the transfer of a plurality of vertical scanner signals having different periods with the same clock can be shared by the same shift registers. Therefore, an organic EL display apparatus which does not suffer from flickering and displays an image of high picture quality can be provided. Further, since the shift registers can be shared, miniaturization, a reduction in power consumption input signals of an organic EL display apparatus can be anticipated.