Magnetic tunnel junction device and formation method thereof

A method of forming a magnetic tunnel junction (MTJ) device includes forming MTJ layers over a dielectric layer; performing a first etching operation on the MTJ layers to form MTJ stacks, in which the first etching operation is performed such that a metal-containing doped region is formed in the dielectric layer and between the MTJ stacks; and performing a second etching operation to break through the metal-containing doped region.

BACKGROUND

In integrated circuit (IC) devices, magnetroresistive random access memory (MRAM) is an emerging technology for next generation embedded memory devices. MRAM is a non-volatile memory where data is stored in magnetic storage elements. In simple configurations, each cell has two ferromagnetic plates, each of which can hold a magnetic field, separated by a thin insulating layer. MRAM has a simple cell structure and complementary metal oxide semiconductor (CMOS) logic comparable processes which result in a reduction of the manufacturing complexity and cost in comparison with other non-volatile memory structures.

DETAILED DESCRIPTION

According to some embodiments of this disclosure, a magnetoresistive random access memory (MRAM) device is formed. The MRAM device includes a magnetic tunnel junction (MTJ) stack. The MTJ stack includes a tunnel barrier layer formed between a ferromagnetic pinned layer and a ferromagnetic free layer. The tunnel barrier layer is thin enough (such a few nanometers) to permit electrons to tunnel from one ferromagnetic layer to the other. A resistance of the MTJ stack is adjusted by changing a direction of a magnetic moment of the ferromagnetic free layer with respect to that of the ferromagnetic pinned layer. When the magnetic moment of the ferromagnetic free layer is parallel to that of the ferromagnetic pinned layer, the resistance of the MTJ stack is in a lower resistive state, corresponding to a digital signal “0”. When the magnetic moment of the ferromagnetic free layer is anti-parallel to that of the ferromagnetic pinned layer, the resistance of the MTJ stack is in a higher resistive state, corresponding to a digital signal “1”. The MTJ stack is coupled between top and bottom electrode and an electric current flowing through the MTJ stack (tunneling through the tunnel barrier layer) from one electrode to the other is detected to determine the resistance and the digital signal state of the MTJ stack.

According to some embodiments of this disclosure, the MRAM device is formed within a chip region of a substrate. A plurality of semiconductor chip regions is marked on the substrate by scribe lines between the chip regions. The substrate will go through a variety of cleaning, layering, patterning, etching and doping steps to form the MRAM devices. The term “substrate” herein generally refers to a bulk substrate on which various layers and device elements are formed. In some embodiments, the bulk substrate includes, for example, silicon or a compound semiconductor, such as GaAs, InP, SiGe, or SiC. Examples of the layers include dielectric layers, doped layers, polysilicon layers or conductive layers. Examples of the device elements include transistors, resistors, and/or capacitors, which may be interconnected through an interconnect layer to additional integrated circuits.

FIG. 1is a cross-sectional view of the MRAM device100at an intermediate stage of manufacture according to various embodiments of the present disclosure. Reference is made toFIG. 1. In some embodiments, an interconnect structure102having an inter-layer dielectric (ILD) layer or inter-metal dielectric layer (IMD) layer104with a metallization pattern106is formed over a substrate (not shown inFIG. 1). The ILD layer104may be silicon oxide, fluorinated silica glass (FSG), carbon doped silicon oxide, tetra-ethyl-ortho-silicate (TEOS) formed oxide, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), Black Diamond® (Applied Materials of Santa Clara, Calif.), amorphous fluorinated carbon, low-k dielectric material, the like or combinations thereof. The metallization patterns106may be aluminum, aluminum alloy, copper, copper alloy, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, the like, and/or combinations thereof. Formation of the metallization patterns106and the ILD layer104may be a dual-damascene process and/or a single-damascene process.

FIG. 2is a cross-sectional view of the MRAM device100at an intermediate stage of manufacture according to various embodiments of the present disclosure. Reference is then made toFIG. 2. An etch stop layer108may be blanket formed over the interconnect structure102. The etch stop layer108controls the end point of a subsequent etch process. In various embodiments, the etch stop layer108may be formed by a vapor deposition technique (e.g., physical vapor deposition, chemical vapor deposition, etc.) and include a silicon nitride (SiN) layer, a silicon carbide (SiC) layer, a silicon oxycarbide (SiOC) layer, and/or some other suitable etch stop layers. A dielectric layer110is formed over the etch stop layer108. The dielectric layer110may be formed by acceptable deposition techniques, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), the like, and/or a combination thereof. A chemical-mechanical polish (CMP) process is optionally performed to the dielectric layer110, until a desirable thickness is achieved. The dielectric layer110can be, for example, silicon dioxide layer, silicon carbide layer, silicon nitride layer, silicon oxycarbide layer, silicon oxynitride layer, low-k dielectric (e.g., having a dielectric constant of less than about 3.9) layer, extreme low-k (ELK) dielectric (e.g., having a dielectric constant of less than about 2.5) layer, the like, or combinations thereof.

FIG. 3is a cross-sectional view of the MRAM device100at an intermediate stage of manufacture according to various embodiments of the present disclosure. As shown inFIG. 3, bottom electrode vias (BEVA)112are then formed within the dielectric layer110and the etch stop layer108. An exemplary formation method of the BEVAs112includes etching an opening in the dielectric layer110and etching an opening in the etch stop layer108, filling metal into the openings, and performing a planarization process, such as a CMP process, to remove excess materials of the filling metal outside the opening in the dielectric layer110. The remaining filling metal in the opening in the dielectric layer110can serve as the BEVAs112. In some embodiments, the BEVAs112are electrically connected to an underlying electrical component, such as a transistor (e.g., transistor as shown inFIG. 11), through the metallization patterns106. In some embodiments, the filling metal is titanium (Ti), tantalum (Ta), platinum (Pt), ruthenium (Ru), tungsten (W), aluminum (Al), copper (Cu), the like, and/or combinations thereof. Formation of the filling metal may be exemplarily performed using CVD, PVD, ALD, the like, and/or a combination thereof.

A bottom electrode layer114is then blank formed over the BEVAs112and over the dielectric layer110, so that the bottom electrode layer114extends along top surfaces of the BEVAs112and of the dielectric layer110. The bottom electrode layer114can be a single-layered structure or a multi-layered structure. The bottom electrode layer114includes a material the same as the filling metal of the BEVAs112in some embodiments. In some other embodiments, the bottom electrode layer114includes a material different from the filling metal of the BEVAs112. In some embodiments, bottom electrode layer114is titanium (Ti), tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), tungsten (W), ruthenium (Ru), molybdenum (Mo), cobaltum (Co), the like, and/or combinations thereof. Formation of the bottom electrode layer114may be exemplarily performed using CVD, PVD, ALD, the like, and/or a combination thereof. The bottom electrode layer114may have a thickness in a range from 10 nm to about 100 nm in some embodiments.

FIG. 4is a cross-sectional view of the MRAM device100at an intermediate stage of manufacture according to various embodiments of the present disclosure. Reference is made toFIG. 4. Magnetic tunnel junction (MTJ) layers are formed over the bottom electrode layer114. The MTJ layers116include a seed layer118, a ferromagnetic pinned layer120, a tunneling layer122, a ferromagnetic free layer124, and a capping layer126formed in sequence over the bottom electrode layer114. The seed layer118includes Ta, TaN, Cr, Ti, TiN, Pt, Mg, Mo, Co, Ni, Mn, or alloys thereof, and serves to promote a smooth and uniform grain structure in overlying layers. The seed layer118may have a thickness in a range from 5 nm to about 10 nm in some embodiments. The ferromagnetic pinned layer120may be formed of an anti ferromagnetic (AFM) layer and a pinned ferroelectric layer over the AFM layer. The AFM layer is used to pin or fix the magnetic direction of the overlying pinned ferroelectric layer. The ferromagnetic pinned layer120may be formed of, for example, ferroelectric metal or alloy (e.g., Co, Fe, Ni, B, Mo, Mg, Ru, Mn, Ir, Pt, or alloys thereof) having a thickness in a range from about 3 nm to about 7 nm.

The tunneling layer122is formed over the ferromagnetic pinned layer120. The tunneling layer122is thin enough that electrons are able to tunnel through the tunneling layer122when a biasing voltage is applied on a resulting MTJ stack116′ fabricated from the MTJ layers116. In some embodiments, the tunneling layer122includes magnesium oxide (MgO), aluminum oxide (Al2O3), aluminum nitride (AlN), aluminum oxynitride (AlON), hafnium oxide (HfO2) or zirconium oxide (ZrO2), or combinations thereof. The tunneling layer122has a thickness in a range from about 0.5 nm to about 2 nm in some embodiments. Exemplary formation methods of the tunneling layer122include sputtering, PVD, ALD, or the like.

Still referring toFIG. 4, the ferromagnetic free layer124is formed over the tunneling layer122. A direction of a magnetic moment of the ferromagnetic free layer124is not pinned because there is no anti-ferromagnetic material adjacent the ferromagnetic free layer124. Therefore, the magnetic orientation of this layer124is adjustable, thus the layer124is referred to as a free layer. In some embodiments, the direction of the magnetic moment of the ferromagnetic free layer124is free to rotate parallel or anti-parallel to the pinned direction of the magnetic moment of the ferromagnetic pinned layer120. The ferromagnetic free layer124may include a ferromagnetic material similar to the material in the ferromagnetic pinned layer120. In some embodiments, the ferromagnetic free layer124includes Co, Fe, B, Mo, or combinations thereof. The ferromagnetic free layer124has a thickness in a range from about 1 nm to about 3 nm in some embodiments. Exemplary formation methods of the ferromagnetic free layer124include sputtering, PVD, ALD, or the like.

The capping layer126is deposited over the ferromagnetic free layer124. The capping layer126includes Ta, Co, B, Ru, Mo, MgO, AlO, or combinations thereof. The material of the capping layer126is chosen such that it has an adequate etching resistance in a subsequent etching which will be described details later. A thickness of the capping layer126is chosen such that it provides an adequate protection for the ferromagnetic free layer124in the subsequent etching and meets a target of tunneling magnetoresistance (TMR) of the MRAM device100. As an example, a thickness of the capping layer126is in a range from about 1 nm to about 4 nm. The capping layer126may be deposited by PVD or alternatively other suitable processes.

A top electrode layer128is formed on the capping layer126. In some embodiments, the top electrode layer128is similar to the bottom electrode layer114in terms of composition. In some embodiments, the top electrode layer128includes Ti, Ta, Ru, W, TaN, TiN, the like or combinations thereof. An exemplary formation method of the top electrode layer128includes sputtering, PVD, ALD or the like. The top electrode layer128may have a thickness in a range from 10 nm to about 100 nm in some embodiments.

A hard mask layer129is formed over the top electrode layer128. In some embodiments, the hard mask layer129may be silicon carbide (SiC), silicon oxynitride (SiON), silicon nitride (SiN), silicon dioxide (SiO2), the like, and/or combinations thereof. The hard mask layer129may be formed by acceptable deposition techniques, such as CVD, ALD, PVD, the like, and/or combinations thereof.

In some embodiments, a patterned resist mask P is formed over the hard mask layer129. A resist layer is formed over the hard mask layer129and then patterned into a patterned resist mask P using a suitable photolithography process, such that portions of the hard mask layer129are exposed by the patterned resist mask P. In some embodiments, the patterned resist mask P is a photoresist. In some embodiments, the patterned resist mask P is an ashing removable dielectric (ARD), which is a photoresist-like material generally having generally the properties of a photoresist and amendable to etching and patterning like a photoresist. An exemplary photolithography process may include photoresist coating (e.g., spin-on coating), soft baking, mask aligning, exposure, post-exposure baking, developing the photoresist, rinsing, drying (e.g., hard baking), other suitable processes, or combinations thereof.

FIG. 5is a cross-sectional view of the MRAM device100at an intermediate stage of manufacture according to various embodiments of the present disclosure. As shown inFIG. 5, the hard mask layer129and the underlying top electrode layer128are then etched, and hence forming top electrodes128′. The patterned resist mask P and the hard mask layer129are then removed using suitable processes such as ashing and/or etching. Top electrodes128′ are used as etch masks for patterning the underlying layers.

FIG. 6is a cross-sectional view of the MRAM device100at an intermediate stage of manufacture according to various embodiments of the present disclosure. As shown inFIG. 6, an etching process E1is performed to pattern the MTJ layers116using the top electrodes128′ as etch masks. In greater detail, the etching process El removes portions of the MTJ layers116, the bottom electrode layer114, and the underlying dielectric layer110not protected by the top electrodes128′. The etching process El further etches the dielectric layer110, thus resulting in a recess R1in the dielectric layer110. After the etching process E1, remaining capping layers126′, remaining ferromagnetic free layers124′, remaining tunneling layers122′, remaining ferromagnetic pinned layers120′, and remaining seed layers118′ are in combination referred to as MTJ stacks116′. The bottom electrode layer114is patterned as bottom electrodes114′ under the respective MTJ stacks116′. Opposite sidewalls and a top surface of the dielectric layer110are exposed to the recess R1. The etching process El may be an anisotropic etching process. For example, the etching process El is a dry etching process including an ion beam etch (IBE) process as illustrated inFIG. 6. In embodiments where the etching process El is an IBE process, the MTJ layers116, the bottom electrode layer114, and the underlying dielectric layer110are exposed to a bombardment of ions. Removed materials M (e.g., etching by-products which include metal ions) of the MTJ layers116and the bottom electrode layer114are dislodged from their exposed surfaces and may be driven into the dielectric layer110. During the IBE process, the removed materials M (e.g., etching by-products which include metal ions) have enough energy to penetrate through the dielectric layer110. A top portion and opposite side portions of the dielectric layer110are thus doped with such removed metal materials M, thus leading to an increased conductivity in doped regions of the dielectric layer110. These doped top portion and doped side portions are thus collectively referred to as a conductive doped region130, as shown inFIG. 7. That is to say, the conductive doped region130includes etching by-products resulting from the etching process E1. In this way, the conductive doped region130has metal materials of the MTJ layers116and/or the bottom electrode layer114. The conductive doped region130is formed to line the recess R1. In particular, the conductive doped region130has a U-shaped cross section profile and extends to reach bottom surfaces114′bof the bottom electrodes114′ of two neighboring MTJ stacks116′. As a result, the conductive doped region130constitutes one leakage path between two neighboring MTJ stacks116′, thereby causing electrical shorts therebetween. Because the MTJ layers116include metals, the conductive doped region130can be referred to as a metal-containing doped region as well.

A spacer layer132is formed over a top surface of the conductive doped region130, along a sidewall of the conductive doped region130, along a sidewall of the bottom electrode, along a sidewall of the MTJ stack116′, along a sidewall of the top electrode, and over a top surface of the top electrode. The spacer layer132encapsulates the conductive doped region130, the bottom electrodes114′, the MTJ stacks116′, and the top electrodes128′. In some embodiments, the spacer layer132includes SiN, the like, or combinations thereof. The spacer layer132may be formed using CVD, ALD, or PVD the like, and/or combinations thereof. The spacer layer132is thin enough such that a width of the recess R1is still wide enough, which in turn improves a gap fill window of a subsequently formed IMD layer (e.g, an ILD layer134inFIG. 10).

FIG. 8is a cross-sectional view of the MRAM device100at an intermediate stage of manufacture according to various embodiments of the present disclosure. Reference is made toFIG. 8. An etching process is performed to etch the spacer layer132into at least one spacer132′. The etching process may be an anisotropic etch process. After the etching process, the top surface of the conductive doped region130is partially exposed. The spacer132′ remains on and is in contact with the sidewalls of the top electrodes128′, of the MTJ stacks116′, and of the bottom electrodes114′. The spacer132′ remains on and is in contact with the sidewall, a portion of the top surface, and a corner between the sidewall and the portion of the top surface of the conductive doped region130as well. The spacer132′ laterally surrounds the bottom electrode114′, the MTJ stack116′, and the top electrode128′. In some embodiments, the spacer132′ has a thickness T1in a range from about 1 nm to about 30 nm.

FIG. 9is a cross-sectional view of the MRAM device100at an intermediate stage of manufacture according to various embodiments of the present disclosure. Reference is made toFIG. 9. An etching process E2is performed to deepen the recess R1to break through the conductive doped region130. That is, an exposed region of the conductive doped region130not covered by the spacer132′ is etched. In particular, the etching process E2is performed to etch the conductive doped region130and the underlying dielectric layer110to form a recess extension R2under the recess R1to extend a vertical depth T2and a horizontal width W1. A bottommost position of the spacer132′ is higher than a bottommost position of the recess extension R2in a top surface of the dielectric layer110. A bottommost position of the conductive doped region130′ is higher than a bottommost position of the recess extension R2in a top surface of the dielectric layer110. In some embodiments, the recess extension R2may be etched until the recess extension R2has the vertical depth T2from an exposed top surface of the dielectric layer110and horizontally extends a width W1from the recess R1to the sidewall of the dielectric layer110. In some embodiments, the vertical depth T2of the recess extension R2is in a range from about 2 nm to about 5 nm. In some embodiments, the width W1of the recess extension R2is in a range from about 1 nm to about 3 nm. The etching process may be a wet chemical etch or a dry chemical etch.

The conductive doped region130has a horizontal portion and side portions connected to opposite sides of the horizontal portion. The horizontal portion of the conductive doped region130is thus removed and at least one side portion of the conductive doped region130remains. The remaining side portion of the conductive doped region130can be referred to as a conductive doped region130′, as shown inFIG. 9. The conductive doped region130′ is in a side portion of the dielectric layer110between the spacer132′ and the BEVA112. The conductive doped region130′ forms a curved interface, for example, a concave interface with the spacer132′. An interface between the dielectric layer110and the bottom electrode114′ is coterminous with an interface between the conductive doped region130′ and the bottom electrode114′. The etching process E2can thereby prevent electrical shorts between the two neighboring MTJ stacks116′. After the etching process E2, a portion of the top surface and a portion of the sidewall of the dielectric layer110and a sidewall of the conductive doped region130′ are exposed. The conductive doped region130′ has a vertical length L1extending from an interface between a top surface of the conductive doped region130′ and the bottom surface114′bof the bottom electrode to an interface between a bottom surface of the conductive film and the dielectric layer110. In some embodiments, the length L1is in a range from about 10 nm to about 200 nm. The conductive doped region130′ and the underlying dielectric layer110are etched self-aligned using the MTJ stack116′ and the spacers132′ as a self-aligned mask without using a lithography patterning process. Therefore, the etching process is referred to as a self-aligned etching process. The fabrication cost is reduced.

FIG. 10is a cross-sectional view of the MRAM device100at various intermediate stages of manufacture according to various embodiments of the present disclosure. Reference is made toFIG. 10. Another ILD layer134is formed over the interconnect structure102, and upper metallization patterns136are then formed in the ILD layer134. Formation of the upper metallization patterns136may be formed by etching an opening in the ILD layer134, and then filling one or more metals in the opening to form the upper metallization patterns136, so that the upper metallization patterns136can reach on the top electrode. In some embodiments, the opening and the metallization pattern may be formed by a dual-damascene process. Trenches and via openings are formed through the ILD layer134, and then filled with a conductive material (e.g., copper). A planarization is then performed.

In some embodiments, the ILD layer134may have the same material as the ILD layer104. In some other embodiments, the ILD layer134may have a different material than the ILD layer104. In some embodiments, the ILD layer134includes silicon oxide, fluorinated silica glass (FSG), carbon doped silicon oxide, tetra-ethyl-ortho-silicate (TEOS) formed oxide, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), Black Diamond® (Applied Materials of Santa Clara, Calif.), amorphous fluorinated carbon, low-k dielectric material, the like or combinations thereof.

FIG. 11illustrates an integrated circuit including MRAM devices and logic devices. The integrated circuit includes a logic region900and a MRAM region901. Logic region may900include circuitry, such as the exemplary transistor, for processing information received from MRAM devices920in the MRAM region901and for controlling reading and writing functions of MRAM devices920. In some embodiments, the MRAM device920includes an MTJ stack916, a top electrode928over the MTJ stack916, a bottom electrode914under the MTJ stack916, and a BEVA912under the bottom electrode914and in the dielectric layer910and an etch stop layer ESL3. The MRAM device920includes conductive films930in contact with sidewalls of the dielectric layer910and in contact with a bottom surface914bof the bottom electrode914. The conductive films930are separated from each other, such that an unwanted electrical connection between the bottom electrodes914of the two neighboring MTJ stacks916can be prevented. The MRAM device920further includes spacers932extending along the conductive film930, the bottom electrode914, the MTJ stack916, and the top electrode928.

As depicted, the integrated circuit is fabricated using five metallization layers, labeled as M1through M4, with five layers of metallization vias or interconnects, labeled as V2through V4. Other embodiments may contain more or fewer metallization layers and a corresponding more or fewer number of vias. Logic region900includes a full metallization stack, including a portion of each of metallization layers M1-M4connected by interconnects V2-V4, with M1connecting the stack to a source/drain contact of logic transistor902. The MRAM region901includes a full metallization stack connecting MRAM devices920to transistors911in the MRAM region901, and a partial metallization stack connecting a source line to transistors911in the MRAM region901. MRAM devices920are depicted as being fabricated in between the top of the M2layer and the bottom the M4layer. Also included in integrated circuit is a plurality of ILD layers. Five ILD layers, identified as ILD0through ILD4are depicted inFIG. 11as spanning the logic region900and the MRAM region901. The ILD layers may provide electrical insulation as well as structural support for the various features of the integrated circuit during many fabrication process steps. The ILD layers between two metallization layers may include etch stop layers, identified as ESL1-ESL4therebetween to signaling the termination point of an etching process and protect any underlying layer or layers during the etching process.

Based on the above discussions, it can be seen that the present disclosure offers advantages. It is understood, however, that other embodiments may offer additional advantages, and not all advantages are necessarily disclosed herein, and that no particular advantage is required for all embodiments. One advantage is that unwanted leakage path caused by the etching by-products, which may be driven into the dielectric layer between two neighboring MTJ stacks, is avoided by an additional recessing process. Another advantage is that such recessing process can be performed using the MTJ stack and the spacer as a self-aligned mask without the need for extra masks.

In some embodiments, a method of forming a magnetic tunnel junction (MTJ) device includes forming MTJ layers over a dielectric layer; performing a first etching operation on the MTJ layers to form MTJ stacks, in which the first etching operation is performed such that a metal-containing doped region is formed in the dielectric layer and between the MTJ stacks; and performing a second etching operation to break through the metal-containing doped region.

In some embodiments, a method of forming a magnetic tunnel junction (MTJ) device includes forming a bottom electrode layer over a dielectric layer; forming MTJ layers over the bottom electrode layer; forming a top electrode over the MTJ layers; patterning the MTJ layers and the bottom electrode layer to form an MTJ stack and a bottom electrode under the MTJ stack; forming a spacer that laterally surrounds the bottom electrode, the MTJ stack, and the top electrode; and after forming the spacer, etching an exposed region of the dielectric layer that is not covered by the spacer.

In some embodiments, a magnetic tunnel junction (MTJ) device includes a bottom electrode via, a MTJ stack, a spacer, and a metal-containing doped region. The bottom electrode via extends through a dielectric layer. The MTJ stack is over the bottom electrode and includes a ferromagnetic pinned layer, a tunneling layer, and a ferromagnetic free layer. The tunneling layer is over the ferromagnetic pinned layer. The ferromagnetic free layer is over the tunneling layer. The spacer laterally surrounds the MTJ stack. The metal-containing doped region is in the dielectric layer and under the spacer.