Vertical-cavity surface-emitting laser and method for forming the same

A vertical cavity surface emitting laser includes an active area, an inner trench, an outer trench, and a first implantation region. The active area includes a first mirror, an active region, a second mirror, and an etch stop layer. The first mirror is formed over a substrate. The active region is formed over the first mirror. The second mirror is formed over the active region. The etch stop layer with an aperture is formed between the active region and the second mirror. The inner trench surrounds the active area in a top view. The outer trench is formed beside the inner trench. The first implantation region is formed below the inner trench.

BACKGROUND

Technical Field

The disclosure relates to a semiconductor structure, and more particularly to a vertical-cavity surface-emitting laser (VCSEL) and a method for forming a VCSEL.

Description of the Related Art

A vertical-cavity surface-emitting laser (VCSEL) is a semiconductor laser diode whose laser beam is emitted in the direction perpendicularly to its surface. VCSEL may be tested during production. VCSEL is widely adopted for use in various applications, such as optical fiber communications and biometrics.

The mesa of the active area of a VCSEL may be isolated by trenches. The power performance of a VCSEL may be affected by the depth of the trench. However, the depth of the trench varies within a wafer of 6 inches or beyond. In addition, an implantation region may be formed to isolate the emitter area of a VCSEL. However, if the implantation region is too deep, higher photo resistor and wider photo resistor spacing is needed. Therefore, the chip design may be limited.

Although existing VCSEL have generally been adequate for their intended purposes, they have not been entirely satisfactory in all respects, and need to be improved. This is especially true of the improvement of uniformity and chip design window.

BRIEF SUMMARY

The present disclosure provides a VCSEL includes an active area, an inner trench, an outer trench, and a first implantation region. The active area includes a first mirror, an active region, a second mirror, and an etch stop layer. The first mirror is formed over a substrate. The active region is formed over the first mirror. The second mirror is formed over the active region. The etch stop layer with an aperture is formed between the active region and the second mirror. The inner trench surrounds the active area in a top view. The outer trench is formed beside the inner trench. The first implantation region is formed below the inner trench.

The present disclosure also provides a VCSEL including an active region sandwiched between a first mirror and a second mirror. An etch stop layer is formed between the active region and the second mirror. An outer trench is formed through the second mirror, the etch stop layer, the active region, and the first mirror. An inner trench is formed through the second mirror. A first implantation region is formed under the inner trench. A second implantation region is formed under the outer trench. The bottom surface of the inner trench is level with the etch stop layer.

The present disclosure also provides a method for forming a VCSEL. The method includes a first mirror over a substrate. The method also includes forming an active region over the first mirror. The method also includes forming a second mirror over the active region. The method also includes forming an outer trench in the first mirror, the active region, and the second mirror. The method also includes oxidizing a spacer layer between the active region and the second mirror to form an etch stop layer at the top surface of the spacer layer. The method also includes forming an inner trench stopping on the etch stop layer. The method also includes forming a first implantation region under the inner trench.

DETAILED DESCRIPTION

Herein, the terms “around,” “about,” “substantial” usually mean within 20% of a given value or range, preferably within 10%, and better within 5%, or 3%, or 2%, or 1%, or 0.5%. It should be noted that the quantity herein is a substantial quantity, which means that the meaning of “around,” “about,” “substantial” are still implied even without specific mention of the terms “around,” “about,” “substantial.”

Although some embodiments are discussed with operations performed in a particular order, these operations may be performed in another logical order. In different embodiments, additional operations can be provided before, during, and/or after the stages described the present disclosure. Some of the stages that are described can be replaced or eliminated for different embodiments. Additional features can be added to the semiconductor structure in the present disclosure. Some of the features described below can be replaced or eliminated for different embodiments.

The embodiments of the present disclosure provide a vertical cavity surface emitting laser (VCSEL). The oxidation layer can be used as an etch stop layer, so that an extra trench surrounding the active area of the VCSEL is formed with well-controlled trench depth. Therefore, the depth uniformity of the extra trench can be improved. In addition, an implantation region is formed below the extra trench to vertically isolate the device. Since lower implantation energy is needed, the thickness and the spacing of the photo resistor of forming the implantation region may be reduced. Therefore, the design window may be improved.

FIG.1is a top view of a VCSEL10ain accordance with some embodiments.FIGS.2A-2Eare cross-sectional representations of various stages of forming a VCSEL10ain accordance with some embodiments. TheFIGS.2A-2Eshow cross-sectional representations taken along line2-2inFIG.1.

A substrate102is provided, as shown inFIG.2Ain accordance with some embodiments. The substrate102may be a semiconductor substrate. The substrate102may include III-V semiconductors, such as GaAs, GaN, AlGaN, AlN, AlGaAs, InP, InAlAs, InGaAs, or a combination thereof. In some embodiments, the substrate102includes GaAs.

Next, a first mirror104ais formed over the substrate102, as shown inFIG.2Ain accordance with some embodiments. The first mirror104aincludes first semiconductor layers106aand second semiconductor layers108a. The first mirror104ais stacked alternately with the first semiconductor layer106aand the second semiconductor layer108aover the substrate102. The first semiconductor layer106aand the second semiconductor layer108aare used in pairs. The first semiconductor layers106aand the second semiconductor layers108amay include III-V semiconductors, such as GaAs, AlGaAs, AlAs, GaN, AlGaN, AlN, InP, InAlAs, InGaAs, or a combination thereof. The first semiconductor layers106aand the second semiconductor layers108amay be made of different materials with different refractive indexes. In some embodiments, the first semiconductor layers106aand the second semiconductor layers108ahave a first conductivity type. In some embodiments, the first conductivity type is N-type. The first mirror104amay be referred to as a distributed Bragg reflector (DBR) of a first conductivity type. The thickness of each layer of the first semiconductor layers106aand the second semiconductor layers108adepends on the center wavelength of laser light generated in the VCSEL. The first semiconductor layers106aand the second semiconductor layers108amay be formed by low pressure chemical vapor deposition (LPCVD) process, epitaxial growth process, other applicable methods, or a combination thereof. The epitaxial growth process may include molecular beam epitaxy (MBE), metal organic chemical vapor deposition (MOCVD), or vapor phase epitaxy (VPE).

It should be noted that, although there are only two pairs of the first semiconductor layers106aand second semiconductor layers108astacked alternately as shown inFIG.2A, the total number of such pairs of the first semiconductor layers106aand the second semiconductor layers108aare not limited herein, depending on the demand of design.

Next, a first spacer110ais formed over the first mirror104a, as shown inFIG.2Ain accordance with some embodiments. The first spacer110amay include a III-V semiconductor with a gradient refractive indexes. The first spacer110amay include III-V semiconductors such as GaAs, AlGaAs, AlAs, GaN, AlGaN, AlN, InP, InAlAs, InGaAs, or a combination thereof. In some embodiments, the first spacer110ahas a first conductivity type. In some embodiments, the first conductivity type is N-type. The dopant concentration of the first spacer110amay be less than the dopant concentration of the first semiconductor layers106aand the second semiconductor layers108a. The first spacer110amay be multiple III-V semiconductor layers with different dopants and doping concentrations. The first spacer110amay be formed by a low pressure chemical vapor deposition (LPCVD) process, epitaxial growth process, other applicable methods, or a combination thereof. The epitaxial growth process may include molecular beam epitaxy (MBE), metal organic chemical vapor deposition (MOCVD), or vapor phase epitaxy (VPE).

Afterwards, an active region112is formed over the first spacer110a, as shown inFIG.2Ain accordance with some embodiments. The active region112may include a number of quantum wells114and quantum well barriers116. The quantum wells114and the quantum well barriers116may include III-V semiconductors such as GaAs, AlGaAs, AlAs, GaN, AlGaN, AlN, InP, InAlAs, InGaAs, or a combination thereof. The quantum wells114and the quantum well barriers116may be made of different materials, and the quantum well barriers116may have a greater energy band gap than the quantum wells114. The active region112may generate the optical power for the VCSEL. The active region112, including the quantum wells114and the quantum well barriers116, may be formed by a low pressure chemical vapor deposition (LPCVD) process, an epitaxial growth process, other applicable methods, or a combination thereof. The epitaxial growth process may include molecular beam epitaxy (MBE), metal organic chemical vapor deposition (MOCVD), or vapor phase epitaxy (VPE). The active region112may separate the underlying first mirror104a, the first spacer110a, and the subsequently formed second spacer and second mirror.

Next, a second spacer110bis formed over the active region112, as shown inFIG.2Ain accordance with some embodiments. The second spacer110bmay include a III-V semiconductor with a gradient refractive indexes. The second spacer110bmay include III-V semiconductors, such as GaAs, AlGaAs, AlAs, GaN, AlGaN, AlN, InP, InAlAs, InGaAs, or a combination thereof. In some embodiments, the second spacer110bincludes AlGaAs. In some embodiments, the second spacer110bhas a second conductivity type. The second conductivity type may be an opposite type to the first conductivity type. In some embodiments, the second conductivity type is P-type. The dopant concentration of the second spacer110bmay be less than the dopant concentration of the layers in the subsequently formed second mirrors. Processes used to form the second spacer110bmay be similar to, or the same as, those used to form the first spacer110adescribed previously and are not repeated herein for brevity.

Next, a second mirror104bis formed over the second spacer110b, as shown inFIG.2Ain accordance with some embodiments. The second mirror104bmay include third semiconductor layers106band fourth semiconductor layers108balternating stacked over the second spacer110b. The third semiconductor layers106band the fourth semiconductor layers108bmay include III-V semiconductors, such as GaAs, AlGaAs, AlAs, GaN, AlGaN, AlN, InP, InAlAs, InGaAs, or a combination thereof. The third semiconductor layers106band the fourth semiconductor layers108bmay be made of different materials with different refractive indexes. In some embodiments, the third semiconductor layers106band the fourth semiconductor layers108bhave a second conductivity type. In some embodiments, the second conductivity type is P-type. The second mirror104bmay be referred to as a distributed Bragg reflector (DBR) of a second conductivity type. The light generated by the active region112may be reflected by the first mirror104aand the second mirror104b. The light may be resonated between the first mirror104aand the second mirror104b. Processes used to form the second mirror104bmay be similar to, or the same as, those used to form the first mirror104adescribed previously and are not repeated herein for brevity.

It should be noted that, although there are two layers of the third semiconductor layers106band three layers of the fourth semiconductor layers108bas shown inFIG.2A, the number of the third semiconductor layers106band the fourth semiconductor layers108bare not limited herein, depending on the demand of design.

Next, a cap layer118is formed over the second mirror104b, as shown inFIG.2Ain accordance with some embodiments. The cap layer118may include III-V semiconductors, such as GaAs, AlGaAs, AlAs, GaN, AlGaN, AlN, InP, InAlAs, InGaAs, or a combination thereof. In some embodiments, the cap layer118has a second conductivity type. In some embodiments, the second conductivity type is P-type. In some embodiments, the cap layer118is a highly doped, which may help to form ohmic contact between the cap layer118and the subsequently formed contact electrode. The cap layer118may be formed by a low pressure chemical vapor deposition (LPCVD) process, an epitaxial growth process, other applicable methods, or a combination thereof. The epitaxial growth process may include molecular beam epitaxy (MBE), metal organic chemical vapor deposition (MOCVD), or vapor phase epitaxy (VPE).

Next, as shown inFIG.2A, a contact electrode120is formed on the cap layer118. The contact electrode120may include Au, Ti, Al, Pd, Pt, Cu, W, other suitable metal, its alloy, or a combination thereof. A contact electrode material may be formed on the cap layer118first by e-beam evaporation, resistive heating evaporation, electroplating, sputtering, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), another suitable method, or a combination thereof. In some embodiments, the contact electrode material is formed by e-beam evaporation. The electrode material is then patterned by a photolithography and etching process, and the contact electrode120is formed.

Next, a first dielectric layer122is conformally formed over the cap layer118and the contact electrode120, as shown inFIG.2Ain accordance with some embodiments. As shown inFIG.2A, the first dielectric layer122is over the second mirror104b. The first dielectric layer122may be made of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon nitride (SiCN), silicon oxide carbonitride (SiOCN), or a combination thereof. In some embodiments, the first dielectric layer122includes silicon nitride. The first dielectric layer122may be formed by a deposition process. The deposition process may include a CVD process (such as LPCVD, PECVD, SACVD, or FCVD), an ALD process, another applicable method, or a combination thereof. In some embodiments, the first dielectric layer122is deposited by a PECVD process.

Next, an outer trench124is formed through the first dielectric layer122, the cap layer118, the second mirror104b, the second spacer110b, the active region112, the first spacer110a, and stopped in the first mirror104a, as shown inFIG.2Ain accordance with some embodiments. The outer trench124may be formed by performing a patterning and etching process. The patterning process may include a photolithography process and etching process. Examples of photolithography processes include photoresist coating, soft baking, mask aligning, exposure, post-exposure baking, developing the photoresist, rinsing and drying. The etching process may be a dry etching process or a wet etching process. In some embodiments, the etching process is a reactive-ion etching (RIE) using inductively coupled plasma (ICP) as etchers. In some embodiments, as shown inFIG.2A, the first mirror104ais exposed from the outer trench124. Part of the first mirror104amay be consumed due to the etching process during forming the outer trench124. In some embodiments, the bottom surface of the outer trench124is below the bottom surface of the active region112. In some embodiments, the bottom surface of the outer trench124is in the first mirror104a.

As shown inFIGS.1and2A, the outer trench124includes trench segments separated from each other in a top view. It should be noted that, although there are six trench segments of outer trench124as shown inFIG.1, the number of trench segments of outer trench124are not limited herein, depending on the demand of design.

Next, as shown inFIG.2B, the top portion of the second spacer110bis oxidized to form an oxidation layer126at the top surface of the second spacer110b. The oxidation layer126may be an etch stop layer126for a subsequent etching process. The top portion of the second spacer110bmay be Al doped layer with high Al composition. In some embodiments, the top portion of the second spacer110bhas an Al composition from about 97% to about 100%. The Al composition may affect the oxidation rate. It may be better to keep oxidation rate stable. If the Al composition is too high, Al diffusion may be too fast and it may be hard to control the position of the oxidation layer126. If the Al composition is too less, the oxidation duration may be too long. In some embodiments, the top portion of the second spacer110bis made of AlGaAs. The high Al composition portion of the second spacer110bmay be oxidized to form the oxidation layer126. In some embodiments, the oxidation layer126includes oxides. In some embodiments, the oxidation layer126includes Al2O3. In some embodiments, the oxidation layer126is formed by a furnace oxidation process.

As shown inFIG.2B, only a portion of the upper surface of the second spacer110bis oxidized. In some embodiments, a central current aperture127is formed separating the etch stop layer126. The central current aperture127may confine a current from the contact electrode120passing through the underlying active region112and the first mirror104a.

Next, an inner trench128is formed through the first dielectric layer122, the cap layer118, and the second mirror104b, as shown inFIG.2Cin accordance with some embodiments. The inner trench128may be formed by performing a patterning and etching process. Processes used to form the inner trench128may be similar to, or the same as, those used to form the outer trench124described previously and are not repeated herein for brevity. In some embodiments, the inner trench128is formed by reactive-ion etching (ME) using inductively coupled plasma (ICP) as etchers. In some embodiments, as shown inFIG.2C, the etching process used for forming the inner trench128stops on the etch stop layer126. Therefore, the etch stop layer126is exposed from the inner trench128. In some embodiments, the bottom surface of the inner trench128is substantially level with the top surface of the etch stop layer126. Therefore, the depth of the inner trench128may be well-controlled by forming the etch stop layer126. As shown inFIG.2C, the depth of the inner trench128is less than the depth of the outer trench124. In addition, as shown inFIG.2C, the inner trench128and the outer trench124are separated from each other.

As shown inFIGS.1and2C, a mesa129of the cap layer118, the contact electrode120, and the second mirror104babove the central current aperture127is surrounded by the inner trench128in a top view. The mesa129may be surrounded by the inner trench128. The first mirror104a, the active region112, the central current aperture127, and the second mirror104bsurrounded by the inner trench128may be referred to as an active area129or an emitter area129of the VCSEL. The inner trench128may provide lateral isolation to the active area129.

Afterwards, a second dielectric layer130is conformally formed over the cap layer118, the contact electrode120, the first dielectric layer122, and the sidewalls and the bottom surface of the inner trench128and the outer trench124, as shown inFIG.2Din accordance with some embodiments. As shown inFIG.2D, the second dielectric layer130is formed in the inner trench128and the outer trench124. Processes and materials used to form the second dielectric layer130may be similar to, or the same as, those used to form the first dielectric layer122described previously and are not repeated herein for brevity. In some embodiments, the second dielectric layer130and the first dielectric layer122are made of the same materials. In some embodiments, the second dielectric layer130includes silicon nitride.

Next, an implantation region132is formed using an implantation process, as shown inFIG.2Din accordance with some embodiments. As shown inFIG.2D, the implantation region132includes a first implantation region132aunder the inner trench128, a second implantation region132bunder the outer trench124, and a third implantation region132cbetween the inner trench128and the outer trench124. In some embodiments, the first implantation region132a, the second implantation region132b, and the third implantation region132care formed in the same implantation process. In some embodiments, the implantation region132is doped by Helium or Boron that will decide the implantation depth.

As shown inFIG.2D, the bottom surface of the first implantation region132ais below the bottom surface of the first spacer110a. In addition, the bottom surface of the first implantation region132ais below the top surface of the first mirror104a. The bottom surface of the second implantation region132bis also below the top surface of the first mirror104a. The first implantation region132amay penetrate through the active region112for chip isolation. In some embodiments, the bottom surface of the first implantation region132ais below the bottom surface of the active region112.

When forming the inner trench128through the second mirror104b, non-radiative recombination center may be produced near the inner trench128. The first implantation region132amay vertically isolate the active area129to reduce the effect of non-radiative recombination center. Since the inner trench128is in a ring shape in the top view, the implantation energy used to form the first implantation region132aunder the inner trench128may be lowered. With lower implant energy, a high-resistivity material may be obtained, and the leakage may be reduced. The implantation process may also be easier to control. As shown inFIG.2D, the first implantation region132ahas a depth of about 0.60 μm to about 0.70 μm. In some embodiments, the first implantation region132ahas a depth of about 0.65 μm. In some embodiments, the first implantation region132ahas a depth of about half of the wavelength of laser light generated in the VCSEL. If the first implantation region132ais too deep, the thickness and the spacing of the photo resistor may be too great, and the chip design may be limited. If the first implantation region132ais too shallow, the isolation preventing the effect of non-radiative recombination center may be not enough.

In some embodiments as shown inFIG.2D, since the first implantation region132aand the second implantation region132bare formed using the same mask, the depth D1of the first implantation region132aand the depth D2of the second implantation region132bare substantially the same. In addition, since the implantation is performed with a tilted angle, the sidewalls of the inner trench128and the outer trench124may be also implanted. Therefore, the third implantation region132cis formed between the inner trench128and the outer trench124. In some embodiments, the implantation has a tilted angle in a range of about 6° to about 8°. In some embodiments, the tilted angle of the implantation is about 7°. The implantation energy or source may be increased to achieve the needed implantation depth. As shown inFIG.2D, the implantation region132also forms in the cap layer118and a portion of the second mirror104boutside the outer trench124.

Afterwards, a third dielectric layer134is conformally formed over the cap layer118, the contact electrode120, and the sidewalls and the bottom surface of the inner trench128and the outer trench124, as shown inFIG.2Ein accordance with some embodiments. As shown inFIG.2E, the third dielectric layer134is formed in the inner trench128and the outer trench124. Processes and materials used to form the third dielectric layer134may be similar to, or the same as, those used to form the first dielectric layer122and the second dielectric layer130described previously and are not repeated herein for brevity. In some embodiments, the third dielectric layer134, the second dielectric layer130, and the first dielectric layer122are made of the same materials. In some embodiments, the third dielectric layer134includes silicon nitride.

Next, openings (not shown) are formed through the third dielectric layer134, the second dielectric layer130, and the first dielectric layer122over the contact electrode120. The contact electrode120may be exposed from the openings. The openings may be formed in third dielectric layer134, the second dielectric layer130, and the first dielectric layer122by a lithography process (e.g., coating the resist, soft baking, exposure, post-exposure baking, developing, other applicable processes, or a combination thereof), an etching process (e.g., wet etching process, a dry etching process, other applicable processes, or a combination thereof), other applicable processes, or a combination thereof.

Next, as shown inFIG.2E, a metal layer136is conformally formed over the cap layer118, the sidewalls and the bottom surface of the openings, the inner trench128, and the outer trench124. In some embodiments, the metal layer136is in direct contact with the contact electrode120. The metal layer136may include conductive material such as Au, Ti, Al, Pd, Pt, Cu, W, other suitable metal, its alloy, or a combination thereof. A metal layer material may be formed by electroplating, e-beam evaporation, resistive heating evaporation, sputtering, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), another suitable method, or a combination thereof. In some embodiments, the metal layer136is formed in the electroplating process. The metal layer material is then patterned by a photolithography and etching process to form an opening138over the central current aperture127in the etch stop layer126. The opening138in the metal layer136may be directly above the central current aperture127in the etch stop layer126.

In some embodiments as shown inFIG.2E, the inner trench128is filled with the metal layer136. In some embodiments, the inner trench128is substantially filled up with the metal layer136. The metal layer136filled in the inner trench128may improve VCSEL thermal dissipation.

Next, the substrate102is thinned to a target thickness (not shown). In some embodiments, the substrate102is thinned by a grinding and a polishing process. With thinner substrate102, the thermal resistance may be reduced. Thinner wafer may improve thermal conductivity and thermal dissipation.

Next, a backside electrode140is formed over the backside of the substrate102, as shown inFIG.2Ein accordance with some embodiments. The backside electrode140may be a metal layer. The backside electrode140may include Au, Ti, Al, Pd, Pt, Cu, W, other suitable metal, its alloy, or a combination thereof. A backside electrode140may be formed on backside of the substrate102first by e-beam evaporation, resistive heating evaporation, electroplating, sputtering, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), another suitable method, or a combination thereof. In some embodiments, the backside electrode140is formed by e-beam evaporation.

Many variations and/or modifications may be made to the embodiments of the disclosure.FIGS.3A-3Bare cross-sectional representations of various stages of forming a VCSEL10bin accordance with some other embodiments. Some processes or devices are the same as, or similar to, those described in the embodiments above, and therefore the descriptions of these processes and devices are not repeated herein. The difference from the embodiments described above is that, as shown inFIG.3Ain accordance with some other embodiments, the implantation process and the etching of the inner trench128are performed using the same mask.

As shown inFIG.3A, after forming the inner trench128, the implantation process is performed by the same mask. Therefore, the implantation region132only includes the first implantation region132aformed below the inner trench128and the third implantation region132cover the sidewall of the inner trench128. In some embodiments, the third implantation region132cformed in a portion of the second mirror104bbetween the inner trench128and the outer trench124. Since the bottom surface of the first implantation region132ais lower than the active region112, the active area129is isolated from the outer area by the inner trench128and the first implantation region132a. Therefore, a mask may be saved, and the cost and time required for production may be reduced.

As described above, an inner trench128is stopping on the oxide etch stop layer126. The depth of the inner trench128may be well controlled and the uniformity within the wafer may be improved. As shown inFIG.3B, the inner trench128may be filled with the metal layer136, and the heat passivation may be improved. With the inner trench128, the implantation region132may be formed by a lower implant energy, and the chip design window may be improved and the cost and time required for production may be reduced. The implantation process and the formation of the inner trench may be performed using the same mask, further reducing the cost and time required for production.

Many variations and/or modifications may be made to the embodiments of the disclosure.FIG.4is a top view of a VCSEL10cin accordance with some embodiments. Some processes or devices are the same as, or similar to, those described in the embodiments above, and therefore the descriptions of these processes and devices are not repeated herein. The difference from the embodiments described above is that, as shown inFIG.4in accordance with some other embodiments, the outer trench124is ring-shaped in the top view.

As long as the inner trench128and the first implantation region132amay provide the isolation between the active area129to the outer area, the shape of the outer trench124in a top view may not be limited. The outer trench124may be ring-shaped or any other pattern that may separate the active area129to the outer area as long as sufficient oxidation may be provided to form an etch stop layer for the inner trench128.

As described above, an inner trench128is formed stopping on the oxide etch stop layer126. The depth of the inner trench128may be well controlled and the uniformity within the wafer may be improved. The inner trench128may be filled with the metal layer136, and the heat passivation may be improved. With the inner trench128, the implantation region132may be formed by a lower implant energy, and the chip design window may be improved and the cost and time required for production may be reduced. The shape of the outer trench124in the top view may not be limited, depending on the need of chip design.

Many variations and/or modifications may be made to the embodiments of the disclosure.FIG.5is a cross-sectional view of a VCSEL10din accordance with some embodiments. Some processes or devices are the same as, or similar to, those described in the embodiments above, and therefore the descriptions of these processes and devices are not repeated herein. The difference from the embodiments described above is that, as shown in FIG.5in accordance with some other embodiments, the second spacer110bmay be multiple III-V semiconductor layers with different element compositions.

In some embodiments, the second spacer110bmay be multiple III-V semiconductor layers with different Al compositions. As shown inFIG.5, the second spacer110bincludes multiple second spacer layers110b-1,110b-2, and110b-3with different Al compositions. The oxidation rate of the following oxidation process may depend on the Al compositions of the second spacer layers. The oxidation rate may be greater with higher Al composition of the second spacer layers. As shown inFIG.5, after the oxidation process, oxidation layers126-1,126-2, and126-3are formed in the second spacer layers110b-1,110b-2, and110b-3, respectively. As shown inFIG.5, the central current apertures formed in the second spacer layers110b-1,110b-2, and110b-3have different widths. Second spacer layers110b-1,110b-2, and110b-3with higher Al content may have narrower central current apertures.

It should be noted that, although there are three layers of the oxidation layers126-1,126-2, and126-3as shown inFIG.5, the number of oxidation layers are not limited herein, depending on the demand of process. In addition, although the topmost oxidation layer126-3has the narrowest central current aperture as shown inFIG.5, the widths of the central current apertures in the oxidation layers126-1,126-2, and126-3are not limited herein. Each of the oxidation layers126-1,126-2, and126-3may have the narrowest central current aperture.

Next, the inner trench128is formed using an etching process, and the etching process stops at one of the oxidation layers126-1,126-2, and126-3, as shown inFIG.5in accordance with some embodiments. The oxidation layers126-1,126-2, and126-3may also be referred as etch stop layers126-1,126-2, and126-3.

It should be noted that, although the etching process using to form the inner trench128stops at the topmost oxidation layer126-3, the oxidation layer which the etching process stops at is not limited herein. In addition, although the etching process using to form the inner trench128stops at the oxidation layer126-3with the narrowest central current aperture, the oxidation layer which the etching process stops at is not limited herein. The etching process using to form the inner trench128may stop at any layer of the oxidation layers126-1,126-2, and126-3formed in the second spacer layers110b.

As described above, an inner trench128is formed stopping on the oxide etch stop layer126. The depth of the inner trench128may be well controlled and the uniformity within the wafer may be improved. The inner trench128may be filled with the metal layer136, and the heat dissipation may be improved. With the inner trench128, the implantation region132may be formed by a lower implant energy, and the chip design window may be improved and the cost and time required for production may be reduced. The second spacer110bmay be multiple layers with different Al compositions, which may lead to oxidation layers with different central current aperture widths. The etching process using to form the inner trench128may stop at any one of the oxidation layers.

As mentioned above, in the present disclosure, a VCSEL and a method of forming a VCSEL is provided. With an extra inner trench formed over an etch stop layer, the uniformity of inner trench depth may be improved. In addition, the implantation depth of the implantation region under the inner trench may be reduced, and the design window may be improved due to a lower photo resistor. A metal layer may be filled in the inner trench, and heat passivation may also be improved. The inner trench and the implantation region may be formed using the same mask, and the cost and time required for production may be reduced.

It should be noted that although some of the benefits and effects are described in the embodiments above, not every embodiment needs to achieve all the benefits and effects.