Multi-channel receiver circuits implemented with time-multiplexed successive approximation register (SAR) analog-to-digital converter (ADC) circuits and methods for operating such receiver circuits are disclosed. One example receiver circuit generally includes a first multiplexer having a plurality of inputs coupled to a plurality of in-phase (I) receive paths associated with different channels of the receiver circuit, a first SAR ADC circuit having an input coupled to an output of the first multiplexer, a second multiplexer having a plurality of inputs coupled to a plurality of quadrature (Q) receive paths associated with the different channels of the receiver circuit, and a second SAR ADC circuit having an input coupled to an output of the second multiplexer.

TECHNICAL FIELD

Certain aspects of the present disclosure generally relate to electronic circuits and, more particularly, to time-multiplexed successive approximation register (SAR) analog-to-digital converters (ADCs).

BACKGROUND

Wireless communication networks are widely deployed to provide various communication services such as telephony, video, data, messaging, broadcasts, and so on. A wireless communication network may include a number of base stations that can support communication for a number of mobile stations. A mobile station (MS) may communicate with a base station (BS) via a downlink and an uplink. The downlink (or forward link) refers to the communication link from the base station to the mobile station, and the uplink (or reverse link) refers to the communication link from the mobile station to the base station. A base station may transmit data and control information on the downlink to a mobile station and/or may receive data and control information on the uplink from the mobile station.

A mobile station or a base station may include one or more analog-to-digital converters (ADCs), for converting received, amplified, filtered, and downconverted analog signals to digital signals for additional processing in the digital domain, for example. Several types of ADCs are available, each with varying advantages and disadvantages. For example, a successive approximation register (SAR) ADC may provide an area and power-efficient architecture for low to medium accuracy analog-to-digital conversion applications. A SAR ADC may use a digital-to-analog converter (DAC) and a comparator to approximate a digital value corresponding to an analog input. Another type of ADC referred to as a flash ADC may provide a faster conversion speed at the cost of an exponential increase in power and area consumption.

SUMMARY

Certain aspects of the present disclosure generally relate to multi-channel receiver circuits implemented with time-multiplexed successive approximation register (SAR) analog-to-digital converter (ADC) circuits.

Certain aspects of the present disclosure provide a receiver circuit. The receiver circuit generally includes a first multiplexer having a plurality of inputs coupled to a plurality of in-phase (I) receive paths associated with different channels of the receiver circuit, a first SAR ADC circuit having an input coupled to an output of the first multiplexer, a second multiplexer having a plurality of inputs coupled to a plurality of quadrature (Q) receive paths associated with the different channels of the receiver circuit, and a second SAR ADC circuit having an input coupled to an output of the second multiplexer.

Certain aspects of the present disclosure provide a method for sampling signals in a multi-channel receiver circuit. The method generally includes selecting, with a first multiplexer, a first analog signal from among a plurality of inputs of the first multiplexer, the plurality of inputs of the first multiplexer being coupled to a plurality of I receive paths associated with different channels of the receiver circuit; sampling the first analog signal with a first SAR ADC circuit; selecting, with a second multiplexer, a second analog signal from among a plurality of inputs of the second multiplexer, the plurality of inputs of the second multiplexer being coupled to a plurality of Q receive paths associated with the different channels of the receiver circuit; and sampling the second analog signal with a second SAR ADC circuit.

Certain aspects of the present disclosure provide an apparatus for wireless communications. The apparatus generally includes first means for selecting a first analog signal from among a plurality of inputs of the first means for selecting, the plurality of inputs of the first means for selecting being coupled to a plurality of I receive paths associated with different channels of the apparatus; first means for sampling the first analog signal; second means for selecting a second analog signal from among a plurality of inputs of the second means for selecting, the plurality of inputs of the second means for selecting being coupled to a plurality of Q receive paths associated with the different channels of the apparatus; and second means for sampling the second analog signal.

DETAILED DESCRIPTION

As used herein, the term “connected with” in the various tenses of the verb “connect” may mean that element A is directly connected to element B or that other elements may be connected between elements A and B (i.e., that element A is indirectly connected with element B). In the case of electrical components, the term “connected with” may also be used herein to mean that a wire, trace, or other electrically conductive material is used to electrically connect elements A and B (and any components electrically connected therebetween).

An Example Wireless System

FIG. 1illustrates a wireless communications system100with access points110and user terminals120, in which aspects of the present disclosure may be practiced. For simplicity, only one access point110is shown inFIG. 1. An access point (AP) is generally a fixed station that communicates with the user terminals and may also be referred to as a base station (BS), an evolved Node B (eNB), or some other terminology. A user terminal (UT) may be fixed or mobile and may also be referred to as a mobile station (MS), an access terminal, user equipment (UE), a station (STA), a client, a wireless device, or some other terminology. A user terminal may be a wireless device, such as a cellular phone, a personal digital assistant (PDA), a handheld device, a wireless modem, a laptop computer, a tablet, a personal computer, etc.

Access point110may communicate with one or more user terminals120at any given moment on the downlink and uplink. The downlink (i.e., forward link) is the communication link from the access point to the user terminals, and the uplink (i.e., reverse link) is the communication link from the user terminals to the access point. A user terminal may also communicate peer-to-peer with another user terminal. A system controller130couples to and provides coordination and control for the access points.

Wireless communications system100employs multiple transmit and multiple receive antennas for data transmission on the downlink and uplink. Access point110may be equipped with a number Napof antennas to achieve transmit diversity for downlink transmissions and/or receive diversity for uplink transmissions. A set Nuof selected user terminals120may receive downlink transmissions and transmit uplink transmissions. Each selected user terminal transmits user-specific data to and/or receives user-specific data from the access point. In general, each selected user terminal may be equipped with one or multiple antennas (i.e., Nut≥1). The Nuselected user terminals can have the same or different number of antennas.

Wireless communications system100may be a time division duplex (TDD) system or a frequency division duplex (FDD) system. For a TDD system, the downlink and uplink share the same frequency band. For an FDD system, the downlink and uplink use different frequency bands. Wireless communications system100may also utilize a single carrier or multiple carriers for transmission. Each user terminal120may be equipped with a single antenna (e.g., to keep costs down) or multiple antennas (e.g., where the additional cost can be supported).

The access point110and/or user terminal120may include a multi-channel receiver circuit with multiple analog-to-digital converters (ADCs). The ADCs may be used, for example, to convert in-phase (I) and/or quadrature (Q) baseband analog signals to digital signals for digital signal processing. In certain aspects of the present disclosure, the ADCs may be implemented with time-multiplexed successive approximation register (SAR) ADC circuits, as described in more detail below.

On the uplink, at each user terminal120selected for uplink transmission, a TX data processor288receives traffic data from a data source286and control data from a controller280. TX data processor288processes (e.g., encodes, interleaves, and modulates) the traffic data {dup} for the user terminal based on the coding and modulation schemes associated with the rate selected for the user terminal and provides a data symbol stream {sup} for one of the Nut,mantennas. A transceiver front end (TX/RX)254(also known as a radio frequency front end (RFFE)) receives and processes (e.g., converts to analog, amplifies, filters, and frequency upconverts) a respective symbol stream to generate an uplink signal. The transceiver front end254may also route the uplink signal to one of the Nut,mantennas for transmit diversity via an RF switch, for example. The controller280may control the routing within the transceiver front end254. Memory282may store data and program codes for the user terminal120and may interface with the controller280.

A number Nupof user terminals120may be scheduled for simultaneous transmission on the uplink. Each of these user terminals transmits its set of processed symbol streams on the uplink to the access point.

At access point110, Napantennas224athrough224apreceive the uplink signals from all Nupuser terminals transmitting on the uplink. For receive diversity, a transceiver front end222may select signals received from one of the antennas224for processing. The signals received from multiple antennas224may be combined for enhanced receive diversity. The access point's transceiver front end222also performs processing complementary to that performed by the user terminal's transceiver front end254and provides a recovered uplink data symbol stream. The recovered uplink data symbol stream is an estimate of a data symbol stream {sup} transmitted by a user terminal. An RX data processor242processes (e.g., demodulates, deinterleaves, and decodes) the recovered uplink data symbol stream in accordance with the rate used for that stream to obtain decoded data. The decoded data for each user terminal may be provided to a data sink244for storage and/or a controller230for further processing.

The transceiver front end (TX/RX)222of access point110and/or the transceiver front end254of user terminal120may include a multi-channel receiver circuit with multiple ADCs. The ADCs may be used, for example, to convert I and/or Q baseband analog signals to digital signals for digital signal processing. In certain aspects of the present disclosure, the ADCs may be implemented with time-multiplexed SAR ADC circuits, as described in more detail below.

On the downlink, at access point110, a TX data processor210receives traffic data from a data source208for Ndnuser terminals scheduled for downlink transmission, control data from a controller230and possibly other data from a scheduler234. The various types of data may be sent on different transport channels. TX data processor210processes (e.g., encodes, interleaves, and modulates) the traffic data for each user terminal based on the rate selected for that user terminal. TX data processor210may provide a downlink data symbol streams for one of more of the Ndnuser terminals to be transmitted from one of the Napantennas. The transceiver front end222receives and processes (e.g., converts to analog, amplifies, filters, and frequency upconverts) the symbol stream to generate a downlink signal. The transceiver front end222may also route the downlink signal to one or more of the Napantennas224for transmit diversity via an RF switch, for example. The controller230may control the routing within the transceiver front end222. Memory232may store data and program codes for the access point110and may interface with the controller230.

At each user terminal120, Nut,mantennas252receive the downlink signals from access point110. For receive diversity at the user terminal120, the transceiver front end254may select signals received from one of the antennas252for processing. The signals received from multiple antennas252may be combined for enhanced receive diversity. The user terminal's transceiver front end254also performs processing complementary to that performed by the access point's transceiver front end222and provides a recovered downlink data symbol stream. An RX data processor270processes (e.g., demodulates, deinterleaves, and decodes) the recovered downlink data symbol stream to obtain decoded data for the user terminal.

FIG. 3is a block diagram of an example transceiver front end300, such as transceiver front ends222,254inFIG. 2, in which aspects of the present disclosure may be practiced. The transceiver front end300includes a transmit (TX) path302(also known as a transmit chain) for transmitting signals via one or more antennas and a receive (RX) path304(also known as a receive chain) for receiving signals via the antennas. When the TX path302and the RX path304share an antenna303, the paths may be connected with the antenna via an interface306, which may include any of various suitable RF devices, such as a duplexer, a switch, a diplexer, and the like.

Receiving in-phase (I) or quadrature (Q) baseband analog signals from a digital-to-analog converter (DAC)308, the TX path302may include a baseband filter (BBF)310, a mixer312, a driver amplifier (DA)314, and a power amplifier (PA)316. The BBF310, the mixer312, and the DA314may be included in a radio frequency integrated circuit (RFIC), while the PA316may be external to the RFIC. The BBF310filters the baseband signals received from the DAC308, and the mixer312mixes the filtered baseband signals with a transmit local oscillator (LO) signal to convert the baseband signal of interest to a different frequency (e.g., upconvert from baseband to RF). This frequency conversion process produces the sum and difference frequencies of the LO frequency and the frequency of the signal of interest. The sum and difference frequencies are referred to as the beat frequencies. The beat frequencies are typically in the RF range, such that the signals output by the mixer312are typically RF signals, which may be amplified by the DA314and/or by the PA316before transmission by the antenna303.

The RX path304includes a low noise amplifier (LNA)322, a mixer324, and a baseband filter (BBF)326. The LNA322, the mixer324, and the BBF326may be included in a radio frequency integrated circuit (RFIC), which may or may not be the same RFIC that includes the TX path components. RF signals received via the antenna303may be amplified by the LNA322, and the mixer324mixes the amplified RF signals with a receive local oscillator (LO) signal to convert the RF signal of interest to a different baseband frequency (i.e., downconvert). The baseband signals output by the mixer324may be filtered by the BBF326before being converted by an analog-to-digital converter (ADC)328to digital I or Q signals for digital signal processing.

In certain aspects of the present disclosure, the transceiver front end300may include a multi-channel receiver circuit with multiple ADCs. The ADCs may be used, for example, to convert I and/or Q baseband analog signals to digital signals for digital signal processing. In certain aspects of the present disclosure, the ADCs may be implemented with time-multiplexed SAR ADC circuits, as described in more detail below.

While it is desirable for the output of an LO to remain stable in frequency, tuning the LO to different frequencies typically entails using a variable-frequency oscillator, which involves compromises between stability and tunability. Contemporary systems may employ frequency synthesizers with a voltage-controlled oscillator (VCO) to generate a stable, tunable LO with a particular tuning range. Thus, the transmit LO frequency may be produced by a TX frequency synthesizer318, which may be buffered or amplified by amplifier320before being mixed with the baseband signals in the mixer312. Similarly, the receive LO frequency may be produced by an RX frequency synthesizer330, which may be buffered or amplified by amplifier332before being mixed with the RF signals in the mixer324.

Example Time-Multiplexed SAR ADC Circuits

In addition to supporting ever more advanced wireless applications, a modern transceiver system usually contains multiple receiver channels to improve the sensitivity (e.g., primary and diversity receiver channels (PRX/DRX)), increase the bandwidth (e.g., carrier aggregation (CA)), support multiple users (e.g., multiple input, multiple output (MIMO)), and/or support multiple standards (e.g., Dual-Band Simultaneous (DBS)). In one existing design, each radio frequency (RF) downlink channel has a dedicated baseband receiver (BBRx) (including, for example, a dedicated successive approximation register (SAR) or delta-sigma analog-to-digital converter (ADC)). For example,FIG. 4illustrates an example architecture400for processing M downlink channels with M SAR ADC circuits402(labeled4021through402m) for sampling and converting baseband analog signals (labeled “Ch_1” through “Ch_m”) to digital signals (labeled “D_ch_1” through “D_ch_m”), where M is an integer greater than 1. In other words, each downlink channel has its own dedicated SAR ADC circuit402.

The total area and/or power budgets of such a design with dedicated ADCs can be significant, especially for a design involving several ADCs. Furthermore, with a modular design that is replicated for the various channels, the BBRx may be overdesigned for particular channels. In the highly competitive wireless communications market, reducing the area and power consumed without expending undue resources on design efforts is typically desirable.

Certain aspects of the present disclosure provide a receiver architecture using one or more time-multiplexing SAR ADCs to process multiple downlink channels. SAR ADCs are different from delta-sigma ADCs, in which the loop filter contains the previous cycle information. In contrast, SAR ADCs sample and convert the input signal every cycle and involve no memory effect from the previous cycle. Since every conversion cycle is independent from other cycles, a single SAR ADC core may be used to support multiple downlink channels in a sequentially time-multiplexed fashion.

For example,FIG. 4illustrates an example architecture410for time-multiplexing a single SAR ADC circuit412to process M downlink channels. In addition to the SAR ADC circuit412, the architecture410includes a multiplexing circuit414and a demultiplexing circuit416. As shown inFIG. 4, the multiplexing circuit414and/or the demultiplexing circuit416may be implemented with a plurality of switches, the operation of which may be controlled by a processing unit (e.g., a controller in a digital signal processor (DSP), which may be included in a modem). Each of the SAR ADC circuits402,412may include a digital-to-analog converter (DAC) array404, a comparator406, and a successive approximation register (SAR) with associated logic408. Since the operation of the DAC array404, the comparator406, and the SAR logic408is understood by a person having ordinary skill in the art, this operation is not further described herein.

Time-multiplexing can be implemented for in-phase (I) and/or quadrature (Q) paths of the same or different downlink channels. The majority of the SAR analog core may be fully reused, with the exception of the anti-aliasing filter (AAF), sampling switches, and the demultiplexer (demux) logic in certain aspects. For certain aspects, the analog input multiplexer (mux) may be implemented inside the SAR ADC core via the sampling switches. For other aspects, the analog input mux may be implemented separately, outside of the SAR ADC core. In either case, this architecture may be easily converted back to a non-time-multiplexed SAR if other channels are deactivated. Ideally, the multiplexed ADC uses only 1/Mthof the original area budget for processing M downlink channels with M dedicated ADCs.

Example Multi-Channel Receiver Circuits

FIGS. 5A-5Eare related to the same architecture500for an example quadrature receiver (Rx) with a SAR ADC circuit502for time-multiplexing between an in-phase (I) signal and a quadrature (Q) signal. Although differential I and Q signals are illustrated inFIGS. 5A-5D, the reader will understand that the architecture may alternatively be implemented with single-ended I and Q signals. The reader may wish to refer to the timing diagram550ofFIG. 5Ethroughout the description for an example of the timing between the sampling, conversion, and reset phases for each of the I and Q signals (which may also be referred to as I and Q channels (labeled “CH_I” and “CH_Q”)). The scheme described below with respect toFIGS. 5A-5Ecan be easily extended to multiple I/Q channels with time-multiplexed ADCs in concurrently running receive paths.

Starting withFIG. 5A, the architecture may include a radio frequency (RF) module501, a baseband receiver (BBRx) module503coupled to the RF module, and a modulator/demodulator (modem) module505coupled to the BBRx module. The RF module501may include a low noise amplifier (LNA)506, an in-phase (I) mixer508, a quadrature (Q) mixer510, a local oscillator (LO)512, an I baseband filter (BBF)514, and a Q BBF516. The LNA506, I/Q mixers508and510, and I/Q BBFs514and516inFIG. 5Amay be analogous to the LNA322, the mixer324, and the BBF326inFIG. 3, respectively. The LO512inFIG. 5Amay be a frequency synthesizer capable of producing an in-phase (I) LO signal511and a quadrature (Q) LO signal513, which is phase shifted 90° from the I LO signal. The LO512may be analogous to the RX frequency synthesizer330(and optional amplifier332) inFIG. 3.

During operation, an RF signal504(labeled “RFin”) received by an antenna (e.g., antenna303inFIG. 3) may be amplified by the LNA506. The I mixer508may mix the amplified RF signal with the I LO signal511output by the LO512for downconversion, and the I BBF514may filter the mixed signal to generate an in-phase (I) baseband signal. The differential I baseband signal has components labeled “IP0” and “IN0,” representing positive (“P”) and negative (“N”) components for the I baseband signal for this particular channel (referred to as Channel0). Likewise, the Q mixer510may mix the amplified RF signal with the Q LO signal513output by the LO512for downconversion, and the Q BBF516may filter the mixed signal to generate a quadrature (Q) baseband signal. The differential Q baseband signal has components labeled “QP0” and “QN0.”

The BBRx module503may include an anti-aliasing filter in the in-phase path (AAF-I520), an anti-aliasing filter in the quadrature path (AAF-Q522), the SAR ADC circuit502, and the demultiplexing circuit416. The SAR ADC circuit502may include a multiplexing circuit414, a DAC array404, a comparator406, and SAR logic408as described above with respect toFIG. 4. The multiplexing circuit414may be implemented with a plurality of switches S1, S2, S3, and S4. The DAC array404may include N+1 capacitors (labeled “C0” to “CN”). Although drawn as single switches for illustrating the concept inFIG. 4, the reader will understand that each of switches S1, S2, S3, and S4actually represents a plurality of distributed switches connected with capacitors C0to CN. The DAC array404may be associated with a number of reset switches for the reset phase.FIG. 5Aillustrates two reset switches S5and S6. The DAC array404may also be associated with a number of sampling switches for the sampling phase. Two sampling switches S7and S8are depicted in the architecture500ofFIG. 5A.

For certain aspects, the BBRx module503may also include a controller540. For other aspects, the controller540may be disposed external to the BBRx module503. The controller540may include a clock generator and a state machine for controlling the state of the various switches, based on the generated clock signal(s). As illustrated inFIG. 5A, the controller540has an input for receiving a clock signal (“Clk_in”) and outputs for controlling the sampling switches S7and S8(“samp”), for controlling the reset switches S5and S6(“rst”), for controlling the switches S1and S3associated with the I baseband signal components (“Track_I”), and for controlling the switches S2and S4associated with the Q baseband signal components (“Track_Q”).

During operation of the BBRx module, the AAF-I520low-pass filters the I baseband components IP0and IN0to generate filtered I baseband signals (labeled “ip” and “in”), and the AAF-Q522low-pass filters the Q baseband components QP0and QN0to generate filtered Q baseband signals (labeled “qp” and “qn”). During the sampling phase552for the I path, the controller540asserts the Track_I signal to close switches S1and S3as represented inFIGS. 5A and 5E. During this time, the controller540also asserts the samp signal such that switches S7and S8are closed. Also during this time, the Track_Q signal and the rst signal are deasserted, such that switches S2, S4, S5, and S6are open. In this manner, the SAR ADC circuit502differentially samples the filtered I baseband signal components during the sampling phase552for the I path.

During the sampling phase554for the Q path, the controller540asserts the Track_Q signal to close switches S2and S4as represented inFIGS. 5B and 5E. During this time, the controller540also asserts the samp signal such that switches S7and S8are closed. Also during this time, the Track_I signal and the rst signal are deasserted, such that switches S1, S3, S5, and S6are open. In this manner, the SAR ADC circuit502differentially samples the filtered Q baseband signal components during the sampling phase554for the Q path.

During the conversion phase556following either the sampling phase552for the I path or the sampling phase554for the Q path, the controller540deasserts the samp, Track_I, Track_Q, and rst signals, as represented inFIG. 5E. In this manner, switches S1, S2, S3, S4, S5, S6, S7, and S8are all open, as illustrated inFIG. 5C. During the conversion phase556, the SAR ADC circuit502outputs a digital signal representing either the I or Q filtered baseband analog signal.

An input of the demultiplexing circuit416is connected to the output of the SAR ADC circuit502. During operation, the demultiplexing circuit416receives the digital I or Q signal (labeled “D_I” or “D_Q”) after each conversion phase556and outputs these signals to the modem module505.

The modem module505may include I/Q phase adjustment logic530and post-processing logic532. The I/Q phase adjustment logic530may be implemented with a phase interpolator or phase delay. Because the I and Q paths for the same downlink channel are sequentially sampled with this time-multiplexed SAR ADC scheme the I/Q phase adjustment logic530may be included to correct, or at least adjust, for any change in the signal(s) that occurred during the interval560between samples of the I and Q baseband signals. For certain aspects, the interval560may be 4.167 ns long, as an example. InFIG. 5E, one can see that the valid data for the current sample of the Q baseband signal (labeled “D_Q[N]”) is available approximately one interval560after valid data for the current sample of the I baseband signal (labeled “D_I[N]”) is available, where the Q baseband signal lags the I baseband signal. For other aspects, the I baseband signal may lag the Q baseband signal, depending on whether the I or Q baseband signal is sampled first. The post-processing logic532may include a demodulator for performing demodulation (including quadrature detection, for example) on the phase-adjusted digital I/Q signals to recover the information content from the received RF signal504.

For certain aspects, a reset phase558may follow each conversion phase556, as illustrated inFIG. 5E. During the reset phase558, the controller540asserts the rst signal, such that the reset switches S5and S6are closed as depicted inFIG. 5D. The samp, Track_I, and Track_Q signals remain deasserted during the reset phase558, such that switches S1, S2, S3, S4, S7, and S8remain open. In this manner, the capacitors in the DAC array404may be discharged before any further sampling. For other aspects, no reset phase is included (i.e., a reset phase may not follow each conversion phase556). For example, a reset phase may not be implemented if the anti-aliasing filter (e.g., AAF-I520or AAF-Q522) is able to fully settle during the respective sampling phase (e.g., sampling phase552or554).

The sequence of the sampling phase552or554, the conversion phase556, and the reset phase558may be repeated, as illustrated inFIG. 5E. The sum of the time lengths for the sampling phase552or554, the conversion phase556, and the reset phase558may equal the interval560.

Instead of time multiplexing between I and Q signals of the same channel as described above, certain aspects of the present disclosure involve time multiplexing between two or more different channels (i.e., channel multiplexing) using two concurrently operating time-multiplexed SAR ADC circuits.FIGS. 6A-6Gare related to the same architecture600for an example receiver circuit with two downlink channels, illustrating channel multiplexing using two time-multiplexed SAR ADC circuits6020and6021(collectively “SAR ADC circuits602”). Although differential I and Q signals are illustrated inFIGS. 6A-6F, the reader will understand that the architecture may alternatively be implemented with single-ended I and Q signals. The reader may wish to refer to the timing diagram650ofFIG. 6Gthroughout the description of architecture600for an example of the timing between the sampling, conversion and reset phases for each of the channels (labeled “CH0” and “CH1”)).

Starting withFIGS. 6A and 6B, the architecture600may include one RF module5010(labeled “RF0”) for CH0, one RF module5011(labeled “RF1”) for CH1, a BBRx module603coupled to the RF modules5010and5011, and a modulator/demodulator (modem) module605coupled to the BBRx module. Each of the RF modules5010and5011may include the same components and operate in the same manner as the RF module501inFIG. 5A. In this architecture600, each channel may have its own LO, separate from the LO of another channel. The RF module5010for CH0may output a differential I baseband signal having components labeled “IP0” and “IN0” and a differential Q baseband signal having components labeled “QP0” and “QN0.” Similarly, the RF module5011for CH1may output a differential I baseband signal having components labeled “IP1” and “IN1” and a differential Q baseband signal having components labeled “QP1” and “QN1.”

The BBRx module603may include an anti-aliasing filter in the in-phase path for CH0(AAF-I5200), an anti-aliasing filter in the quadrature path for CH0(AAF-Q5220), an anti-aliasing filter in the I path for CH1(AAF-I5201), an anti-aliasing filter in the Q path for CH1(AAF-Q5221), the SAR ADC circuits602, a demultiplexing circuit4160for CH0, and a demultiplexing circuit4161for CH1. Each of the SAR ADC circuits602may include a multiplexing circuit414, a DAC array404, a comparator406, and SAR logic408as described above with respect toFIG. 4. Each of the multiplexing circuits4140and4141may be implemented with a plurality of switches S9, S10, S11, and S12. Although drawn as single switches for illustrating the concept inFIGS. 6A-6F, the reader will understand that each of switches S9, S10, S11, and S12actually represents a plurality of distributed switches connected with capacitors C0to CN. Each DAC array404may be associated with a number of reset switches for the reset phase.FIGS. 6A and 6Billustrate two reset switches S13and S14in each DAC array404. Each DAC array404may also be associated with a number of sampling switches for the sampling phase. Two sampling switches S15and S16in each SAR ADC circuit602are depicted in the architecture600ofFIGS. 6A and 6B.

For certain aspects, the BBRx module603may also include a controller640. For other aspects, the controller640may be disposed external to the BBRx module603. The controller640may include a clock generator and a state machine for controlling the state of the various switches, based on the generated clock signal(s). As illustrated inFIGS. 6A and 6B, the controller640has an input for receiving a clock signal (“Clk_in”) and outputs for controlling the sampling switches S15and S16(“samp”), for controlling the reset switches S13and S14(“rst”), for controlling the switches S9and S11associated with the I/Q baseband signal components for CH0(“Track_0”), and for controlling the switches S10and S12associated with the I/Q baseband signal components for CH1(“Track_1”).

During operation of the BBRx module603, the AAF-I5200may low-pass filter the I baseband components IP0and IN0to generate filtered I baseband signals (labeled “ip0” and “in0”), and the AAF-Q5220may low-pass filter the Q baseband components QP0and QN0to generate filtered Q baseband signals (labeled “qp0” and “qn0”). Similarly, the AAF-I5201may low-pass filter the I baseband components IP1and IN1to generate filtered I baseband signals (labeled “ip1” and “in1”), and the AAF-Q5221may low-pass filter the Q baseband components QP1and QN1to generate filtered Q baseband signals (labeled “qp1” and “qn1”). During the sampling phase652for CH0or the sampling phase654for CH1, the controller640asserts the samp signal such that switches S15and S16are closed, as represented inFIGS. 6A, 6B, and 6G. Also during either of these sampling phases652,654, the rst signal is deasserted, such that switches S13and S14are open for both SAR ADC circuits602.

During the sampling phase652for CH0, the controller640also asserts the Track_0signal to close switches S9and S11in both SAR ADC circuits602, and the Track_1signal is deasserted such that switches S10and S12in both SAR circuits are open (as specifically illustrated by the position of the switches S9-S12inFIGS. 6A and 6Band by the signals inFIG. 6G). In this manner, the SAR ADC circuit6020differentially samples the filtered I baseband signal components ip0and in0, and the SAR ADC circuit6021differentially samples the filtered Q baseband signal components qp0and qn0, concurrently during the sampling phase652for CH0.

During the sampling phase654for CH1, the controller640alternatively asserts the Track_1signal to close switches S10and S12in both SAR ADC circuits602, and the Track_0signal is deasserted such that switches S9and S11in both SAR circuits are open (as represented by the position of the switches S9-S12inFIGS. 8A and 8B, described below, and illustrated by the signals inFIG. 6G). In this manner, the SAR ADC circuit6020differentially samples the filtered I baseband signal components ip1and in1, and the SAR ADC circuit6021differentially samples the filtered Q baseband signal components qp1and qn1, concurrently during the sampling phase654for CH1.

During the conversion phase656following either the sampling phase652for CH0or the sampling phase654for CH1, the controller640deasserts the samp, Track_I, Track_Q, and rst signals, as represented inFIG. 6G. In this manner, switches S9, S10, S11, S12, S13, S14, S15, and S16are all open, as illustrated inFIGS. 6C and 6D. During the conversion phase556, the SAR ADC circuit6020outputs a digital signal representing the I filtered baseband analog signal for either CH0or CH1, and the SAR ADC circuit6021outputs a digital signal representing the Q filtered baseband analog signal for either CH0or CH1. By sequentially switching between CH0and CH1, the time-multiplexed SAR ADC circuits602may be effectively used to channel multiplex between sampling and converting the I/Q baseband signals of both channels.

An input of the demultiplexing circuit4160is connected to the output of the SAR ADC circuit6020, and an input of the demultiplexing circuit4161is connected to the output of the SAR ADC circuit6021. During operation, the demultiplexing circuit4160may route the digital I signal for CH0or CH1(labeled “D0_I” or “D1_I”), and the demultiplexing circuit4161may route the digital Q signal for CH0or CH1(labeled “D0_Q” or “D1_Q”), after each conversion phase656to the associated post-processing logic in the modem module605. The D0_I and D0_Q signals for CH0may be routed by the demultiplexing circuits4160,4161to the post-processing logic6320, while the D1_I and D1_Q signals for CH1may be routed by the demultiplexing circuits4160,4161to the post-processing logic6321. As described above for post-processing logic532, post-processing logic6320and6321may include demodulators for performing demodulation on the digital I/Q signals to recover the information content from the received RF signals504associated with the different downlink channels.

With this time-multiplexed SAR ADC scheme, the I signals from both channels are time-multiplexed in the SAR ADC circuit6020, while the Q signals from both channels are time-multiplexed in the other SAR ADC circuit6021. Because the I and Q paths for the same downlink channel (either CH0or CH1) are concurrently sampled with this scheme, the architecture600need not include any phase adjustment or interpolation logic (e.g., in the modem module605).

For certain aspects, a reset phase658may follow each conversion phase656, as illustrated inFIG. 6G. During the reset phase658, the controller640asserts the rst signal, such that the reset switches S13and S14are closed in both SAR ADC circuits602as illustrated inFIGS. 6E and 6F. The samp, Track_0, and Track_1signals remain deasserted during the reset phase658, such that switches S9, S10, S11, S12, S15, and S16remain open in both SAR ADC circuits602. In this manner, the capacitors in the DAC arrays404may be discharged before any further sampling. For other aspects, no reset phase is included (i.e., a reset phase658may not follow each conversion phase656). For example, a reset phase may not be implemented if the anti-aliasing filters are able to fully settle during a respective sampling phase (e.g., sampling phase652or654).

The sequence of the sampling phase652or654, the conversion phase656, and the reset phase658may be repeated, as illustrated inFIG. 6G. The sum of the time lengths for the sampling phase652or654, the conversion phase656, and the reset phase658may equal a multiplexing interval660. For certain aspects, the multiplexing interval660may be the same for both channels, whereas in other aspects, the multiplexing interval for each channel may be different.

The architecture600inFIGS. 6A-6Fmay be expanded to more than two downlink channels. As an example,FIGS. 7A-7Care a block diagram of an example architecture700for a receiver circuit, illustrating the example receiver circuit ofFIGS. 6A and 6Bexpanded to three downlink channels (CH0, CH1, and CH2), in accordance with certain aspects of the present disclosure. The addition of an extra channel (e.g., CH2) may add an extra RF module (e.g., RF module5012, labeled “RF2”) for producing another set of differential I/Q baseband signals (e.g., with I components labeled “IP2” and “IN2” and Q components labeled “QP2” and “QN2”) and another pair of I/Q anti-aliasing filters (e.g., AAF-I5202and AAF-Q5222) in the BBRx module603. The addition of an extra channel may also add another pair of switches (e.g., switches S17and S18) to each of the multiplexing circuits4140and4141, another control signal (e.g., Track_2signal) output from the controller640for sampling the extra channel by controlling this pair of switches, an extra digital output signal (e.g., D2_I and D2_Q) from each of the demultiplexing circuits4160and4161, and additional post-processing logic (e.g., post-processing logic6322) in the modem module605. Specifically, the positions of the switches shown inFIGS. 7A-7Crepresent a sampling phase for CH2for the architecture700with the Track_2signal depicted as being asserted. Although drawn as single switches for illustrating the concept inFIGS. 7A-7C, the reader will understand that each of switches S9, S10, S11, S12, S17, and S18actually represents a plurality of distributed switches connected with capacitors C0to CN.

As described above, each of the RF modules5010and5011in the architecture600(or architecture700) may include an LO such that each channel may have its own LO, separate from the LO of another channel. For other aspects, two or more RF modules may share an LO. For example,FIGS. 8A and 8Bare a block diagram of an example receiver circuit800, which is based on the architecture600of the receiver circuit ofFIGS. 6A-6F, but with an LO812shared between the various RF modules5010and5011, in accordance with certain aspects of the present disclosure. Specifically, the positions of the switches shown inFIGS. 8A and 8Brepresent a sampling phase for CH1for the receiver circuit800with the Track_1signal shown as being asserted.

FIG. 9is a flow diagram illustrating example operations900for sampling signals in a multi-channel receiver circuit, in accordance with certain aspects of the present disclosure. The operations900may be performed by a receiver circuit, such as the receiver circuit in the architecture600ofFIGS. 6A-6F, the receiver circuit in the architecture700ofFIGS. 7A-7C, or the receiver circuit800ofFIGS. 8A and 8B.

The operations900may begin, at block902, with a first multiplexer (e.g., multiplexing circuit4140) in the receiver circuit selecting a first analog signal (e.g., ip0or in0) from among a plurality of inputs of the first multiplexer. The plurality of inputs of the first multiplexer are coupled to a plurality of in-phase (I) receive paths associated with different channels (e.g., CH0, CH1, . . . ) of the receiver circuit. At block904, the first analog signal may be sampled with a first successive approximation register (SAR) analog-to-digital converter (ADC) circuit (e.g., SAR ADC circuit6020) in the receiver circuit. At block906, a second multiplexer (e.g., multiplexing circuit4141) may select a second analog signal (e.g., qp0or qn0) from among a plurality of inputs of the second multiplexer. The plurality of inputs of the second multiplexer are coupled to a plurality of quadrature (Q) receive paths associated with the different channels of the receiver circuit. At block908, the second analog signal may be sampled with a second SAR ADC circuit (e.g., SAR ADC circuit6021).

According to certain aspects, the operations900may further involve the first multiplexer selecting a third analog signal (e.g., ip1or in1) from among the plurality of inputs of the first multiplexer. In this case, the third analog signal may be sampled with the first SAR ADC circuit. For certain aspects, the operations900may further include the second multiplexer selecting a fourth analog signal (e.g., qp1or qn1) from among the plurality of inputs of the second multiplexer. In this case, the fourth analog signal may be sampled with the second SAR ADC circuit. For certain aspects, the operations900may further entail the first SAR ADC circuit converting the sampled first signal to a first digital signal (e.g., D0_I), the second SAR ADC circuit converting the sampled second signal to a second digital signal (e.g., D0_Q), the first SAR ADC circuit converting the sampled third signal to a third digital signal (e.g., D1_I), and/or the second SAR ADC circuit converting the sampled fourth signal to a fourth digital signal (e.g., D1_Q). For certain aspects, the operations900may further involve a first demultiplexer (e.g., demultiplexing circuit4160) demultiplexing between the first digital signal and the third digital signal output from the first SAR ADC circuit and a second demultiplexer (e.g., demultiplexing circuit4161) demultiplexing between the second digital signal and the fourth digital signal output from the second SAR ADC circuit. For certain aspects, the operations900may further entail at least one of: (1) resetting the first SAR ADC circuit after converting the sampled first signal and before sampling the third signal; or (2) resetting the second SAR ADC circuit after converting the sampled second signal and before sampling the fourth signal.

According to aspects, the operations900may further include the first multiplexer selecting a fifth analog signal (e.g., ip2or in2) from among the plurality of inputs of the first multiplexer and the first SAR ADC circuit sampling the fifth analog signal. For certain aspects, the operations900may further involve the second multiplexer selecting a sixth analog signal (e.g., qp2or qn2) from among the plurality of inputs of the second multiplexer and the second SAR ADC circuit sampling the sixth analog signal. In this case, the operations900may further entail the first SAR ADC circuit converting the sampled first signal to a first digital signal (e.g., D0_I), the second SAR ADC circuit converting the sampled second signal to a second digital signal (e.g., D0_Q), the first SAR ADC circuit converting the sampled third signal to a third digital signal (e.g., D1_I), the second SAR ADC circuit converting the sampled fourth signal to a fourth digital signal (e.g., D1_Q), the first SAR ADC circuit converting the sampled fifth signal to a fifth digital signal (e.g., D2_I), and/or the second SAR ADC circuit converting the sampled sixth signal to a sixth digital signal (e.g., D2_Q). For certain aspects, the operations900may further include a first demultiplexer (e.g., demultiplexing circuit4160) demultiplexing between the first digital signal, the third digital signal, and the fifth digital signal output from the first SAR ADC circuit and a second demultiplexer (e.g., demultiplexing circuit4161) demultiplexing between the second digital signal, the fourth digital signal, and the sixth digital signal output from the second SAR ADC circuit.

According to certain aspects, the operations900further entail mixing a first amplified signal with an in-phase (I) local oscillator (LO) signal (e.g., I LO signal511) to generate a first intermediate signal, filtering the first intermediate signal to generate the first analog signal, mixing the first amplified signal with a quadrature (Q) LO signal (e.g., Q LO signal513) to generate a second intermediate signal, and filtering the second intermediate signal to generate the second analog signal. For certain aspects, the operations900may further include mixing a second amplified signal with another I LO signal (e.g., I LO signal511) to generate a third intermediate signal, filtering the third intermediate signal to generate the third analog signal, mixing the second amplified signal with another Q LO signal (e.g., Q LO signal513) to generate a fourth intermediate signal, and filtering the fourth intermediate signal to generate the fourth analog signal. For other aspects, the operations900may further involve mixing a second amplified signal with the I LO signal to generate a third intermediate signal, filtering the third intermediate signal to generate the third analog signal, mixing the second amplified signal with the Q LO signal to generate a fourth intermediate signal, and filtering the fourth intermediate signal to generate the fourth analog signal.

According to certain aspects, the sampling of the first analog signal at block904occurs concurrently with the sampling of the second analog signal at block908.

According to certain aspects, at least one of the first analog signal or the second analog signal comprises a differential signal. For other aspects, the first analog signal and the second analog signal comprise single-ended signals.

Certain aspects of the present disclosure provide a receiver circuit. The receiver circuit generally includes a first multiplexer (e.g., multiplexing circuit4140) having a plurality of inputs coupled to a plurality of in-phase (I) receive paths associated with different channels (e.g., CH0, CH1, . . . ) of the receiver circuit, a first successive approximation register (SAR) analog-to-digital converter (ADC) circuit (e.g., SAR ADC circuit6020) having an input coupled to an output of the first multiplexer, a second multiplexer (e.g., multiplexing circuit4141) having a plurality of inputs coupled to a plurality of quadrature (Q) receive paths associated with the different channels of the receiver circuit, and a second SAR ADC circuit (e.g., SAR ADC circuit6021) having an input coupled to an output of the second multiplexer.

According to certain aspects, the receiver circuit further includes: (1) a first demultiplexer (e.g., demultiplexing circuit4160) having a plurality of I outputs and an input coupled to an output of the first SAR ADC circuit and (2) a second demultiplexer (e.g., demultiplexing circuit4161) comprising a plurality of Q outputs and an input coupled to an output of the second SAR ADC circuit. For certain aspects, the receiver circuit further includes at least one processing unit (e.g., post-processing logic6320,6321, and/or6322) comprising at least one demodulator and a plurality of inputs coupled to the plurality of I outputs of the first demultiplexer and to the plurality of Q outputs of the second demultiplexer. In this case, the receiver circuit may not include a phase adjustment circuit (e.g., I/Q phase adjustment logic530) coupled between the plurality of I outputs of the first demultiplexer and the at least one demodulator or between the plurality of Q outputs of the second demultiplexer and the at least one demodulator.

According to certain aspects, a first receive chain associated with a first one of the channels (e.g., CH0) generally includes a first amplifier (e.g., LNA506); a first in-phase (I) mixer (e.g., I mixer508) having an input coupled to an output of the first amplifier and an output coupled to a first one of the plurality of inputs (e.g., ip0or in0) of the first multiplexer; a first quadrature (Q) mixer (e.g., Q mixer510) having an input coupled to the output of the first amplifier and an output coupled to a first one of the plurality of inputs (e.g., qp0or qn0) of the second multiplexer; and a local oscillator (e.g., LO512or812) having an I output for carrying an I oscillation signal (e.g., I LO signal511) coupled to another input of the first I mixer and a Q output for carrying a Q oscillation signal (e.g., Q LO signal513) coupled to another input of the first Q mixer. For certain aspects, a second receive chain associated with a second one of the channels (e.g., CH1) generally includes a second amplifier (e.g., LNA506), a second I mixer (e.g., I mixer508) having an input coupled to an output of the second amplifier and an output coupled to a second one of the plurality of inputs (e.g., ip1or in1) of the first multiplexer, and a second Q mixer (e.g., Q mixer510) having an input coupled to the output of the second amplifier and an output coupled to a second one of the plurality of inputs (e.g., qp1or qn1) of the second multiplexer. For certain aspects, the receiver circuit may further include another local oscillator (e.g., LO512) having: (1) an I output for carrying another I oscillation signal coupled to another input of the second I mixer and (2) a Q output for carrying another Q oscillation signal coupled to another input of the second Q mixer. For certain aspects, the I output of the local oscillator (e.g., LO812) is coupled to another input of the second I mixer, and the Q output of the local oscillator is coupled to another input of the second Q mixer. For certain aspects, a third receive chain (e.g., in RF module5012) associated with a third one of the channels (e.g., CH2) generally includes a third amplifier (e.g., LNA506), a third I mixer (e.g., I mixer508) having an input coupled to an output of the third amplifier and an output coupled to a third one of the plurality of inputs (e.g., ip2or in2) of the first multiplexer, and a third Q mixer (e.g., Q mixer510) having an input coupled to the output of the third amplifier and an output coupled to a third one of the plurality of inputs (e.g., qp2or qn2) of the second multiplexer. For certain aspects, the receiver circuit further includes: (1) a first filter (e.g., BBF514and/or AAF-I5200) coupled between the output of the first I mixer and the first one of the plurality of inputs of the first multiplexer and (2) a second filter (e.g., BBF516and/or AAF-Q5220) coupled between the output of the first Q mixer and the first one of the plurality of inputs of the second multiplexer.

The various operations of methods described above may be performed by any suitable means capable of performing the corresponding functions. The means may include various hardware component(s) and/or module(s), including, but not limited to one or more circuits. Generally, where there are operations illustrated in figures, those operations may have corresponding counterpart means-plus-function components with similar numbering.

For example, means for selecting may include a multiplexer, such as multiplexing circuit4140or4141as illustrated inFIGS. 6A-6F, 7A-7C, 8A, and 8B. Means for sampling may include an ADC circuit, such as SAR ADC circuit6020or6021as shown inFIGS. 6A-6F, 7A-7C, 8A, and 8B. Means for demultiplexing may include a demultiplexer, such as demultiplexing circuit4160or4161as illustrated inFIGS. 6A-6F, 7A-7C, 8A, and 8B. Means for resetting may include switches for shorting capacitive elements, such as switches S13and S14as depicted inFIGS. 6A-6F, 7A-7C, 8A, and 8B. Means for generating an LO signal may include a frequency synthesizer, which may include a local oscillator (LO) (e.g., LO512as illustrated inFIGS. 6A-6F and 7A-7Cor LO812as shown inFIG. 8A). Means for mixing may include a mixer, such as I mixer508or Q mixer510as portrayed inFIGS. 6A-6F, 7A-7C, 8A, and 8B. Means for filtering may include a filter, such as a BBF514or516; an AAF-I5200,5201, or5202; and/or an AAF-Q5220,5221, or5222as depicted inFIGS. 6A-6F, 7A-7C, 8A, and 8B.

The various illustrative logical blocks, modules, and circuits described in connection with the present disclosure may be implemented or performed with discrete hardware components designed to perform the functions described herein.