Nonvolatile memory device and method for fabricating the same

A nonvolatile memory device includes: a channel layer protruding perpendicular to a surface of a substrate; a tunnel insulation layer formed on a surface of the channel layer; a stack structure, in which a plurality of floating gate electrodes and a plurality of control gate electrodes are alternately formed along the channel layer; and a charge blocking layer interposed between each floating gate electrode, of the plurality of floating gate electrodes, and each control gate electrode of the plurality of control gate electrodes, wherein the floating gate electrode includes a first floating gate electrode between two control gate electrodes and a second floating gate electrode positioned in the lowermost and uppermost parts of the stack structure and having a smaller width in a direction parallel to the substrate than the first floating gate electrode.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority of Korean Patent Application No. 10-2012-0051572, filed on May 15, 2012, which is incorporated herein by reference in its entirety.

BACKGROUND

Exemplary embodiments of the present invention relate to a nonvolatile memory device and a method for fabricating the same, and more particularly, to a nonvolatile memory device having a 3D structure in which a plurality of memory cells are stacked vertically from a substrate, and a method for fabricating the same.

2. Description of the Related Art

A nonvolatile memory device is a memory device, which maintains data stored therein although power supply is cut off. Currently, various nonvolatile memory devices, for example, Flash memory and the like are widely used.

Recently, as the improvement in integration degree of nonvolatile memory devices having a 2D structure in which memory cells are formed as a single layer over a semiconductor substrate approaches the limit, a nonvolatile memory device having a 3D structure in which a plurality of memory cells are formed along a channel layer protruding vertically from a semiconductor substrate has been proposed. Specifically, the nonvolatile memory device having a 3D structure may include a structure for storing changes in a floating gate electrode formed of a conductor and a structure for storing charges in a charge trap layer formed of an insulator.

FIGS. 1A and 1Bare cross-sectional views of a conventional nonvolatile memory device having a 3D structure.

Referring toFIGS. 1A and 1B, the 3D nonvolatile memory device which stores charges in a floating gate electrode may include a channel layer70formed through a plurality of interlayer dielectric layers20and a plurality of control gate electrodes30which are alternately stacked over a substrate10, a tunnel insulation layer60surrounding the channel layer70, a floating gate electrode50interposed between the interlayer dielectric layers20and the tunnel insulation layer60, and a charge blocking layer40surrounding the floating gate electrode50.

In the nonvolatile memory device ofFIG. 1A, the floating gate electrodes50positioned in the uppermost and lowermost parts are dummy floating gate electrodes adjacent to only one control gate electrode30, and thus difficult to control. Accordingly, an abnormal program operation may occur, and a channel current may be reduced during a read operation.

Meanwhile, when a control gate electrode30is disposed on the substrate10as illustrated inFIG. 1B, a dummy floating gate electrode is not formed in the lowermost part, but the control gate electrode30is directly connected to the substrate10. Therefore, the control gate electrode30is shorted to a well pick-up area, and cannot be controlled independently of the well pick-up area. Therefore, there is a demand for the development of a structure capable of solving the above-described problems.

SUMMARY

An embodiment of the present invention is directed to a nonvolatile memory device and a method for fabricating the same, which minimizes the size of a dummy floating gate electrode to reduce a coupling ratio between the dummy floating gate electrode and a control gate electrode, thereby improving an operation characteristic.

In accordance with an embodiment of the present invention, a nonvolatile memory device includes: a channel layer protruding perpendicular to a surface of a substrate; a tunnel insulation layer formed on a surface of the channel layer; a stack structure, in which a plurality of floating gate electrodes and a plurality of control gate electrodes are alternately formed along the channel layer; and a charge blocking layer interposed between each floating gate electrode, of the plurality of floating gate electrodes, and each control gate electrode of the plurality of control gate electrodes, wherein a first portion of the plurality of the floating gate electrodes arranged so that each floating gate electrode, of the first portion of floating gate electrodes, is positioned between two control gate electrodes of the plurality of control gate electrodes, and wherein a floating gate electrode, of the plurality of floating gate electrodes, is positioned at a lowermost and at an uppermost part of the stack structure, and wherein the floating gate electrode, of the plurality of floating gate electrodes, positioned at the lowermost and at the uppermost part of the stack structure each has a smaller width, in a direction parallel to the substrate, than a width of each floating gate electrode of the first portion of the plurality of floating gate electrodes.

In accordance with another embodiment of the present invention, a method for fabricating a nonvolatile memory device includes: forming a first interlayer dielectric layer over a substrate; forming a stack structure in which a plurality of sacrificial layers and a plurality of second interlayer dielectric layers are alternately stacked over the first interlayer dielectric layer; forming a third interlayer dielectric layer over an uppermost sacrificial layer of the plurality of sacrificial layers; forming a hole in the first to third interlayer dielectric layers and the sacrificial layers, the hole exposing the first to third interlayer dielectric layers, the sacrificial layers, and the substrate; etching the first to third interlayer dielectric layers, exposed through the hole, to form a plurality of grooves; and sequentially forming a charge blocking layer and a floating gate electrode in each of the plurality of grooves, wherein the first and third interlayer dielectric layers have a lower etch rate than plurality of the second interlayer dielectric layer.

DETAILED DESCRIPTION

FIGS. 2A to 2Jare cross-sectional views for explaining a nonvolatile memory device and a method for fabricating the same in accordance with an embodiment of the present invention.FIG. 2Jis a cross-sectional view of the nonvolatile memory device in accordance with the embodiment of the present invention, andFIGS. 2A to 2Iare cross-sectional views illustrating examples of intermediate processes for fabricating the nonvolatile memory device ofFIG. 2J.

Referring toFIG. 2A, a first interlayer dielectric layer110is formed over a substrate100. The substrate100may include a semiconductor substrate formed of single-crystal silicon, and have a predetermined lower structure (not illustrated).

Here, the first interlayer dielectric layer110is densely formed to have a lower etch rate than a second interlayer dielectric layer to be described below. For example, the first interlayer dielectric layer110may be formed of an oxide-based material. In the case of silicon oxide (SiO2), the density of a thin film may differ depending on a deposition process such as low-pressure chemical vapor deposition (LP-CVD), plasma enhanced CVD (PE-CVD), atomic layer deposition (ALD) or physical vapor deposition (PVD). For example, silicon oxide formed by atmospheric pressure CVD (AP-CVD) has larger resistance to a wet etching solution, such as buffered oxide etchant or hydrofluoric acid (HF), than tetra ethyl ortho silicate (TEOS) or high temperature oxide (HTO).

Furthermore, although the same deposition method is applied, the etch rate may be reduced through a densification process. For example, after a dielectric layer is formed, annealing or rapid thermal processing (RTP) may be performed to densify the dielectric layer, thereby increasing the resistance to wet etching.

Referring toFIG. 2B, a plurality of sacrificial layers120and a plurality of second interlayer dielectric layers130are alternately stacked over the first interlayer dielectric layer110. Hereafter, for convenience of description, the structure in which the plurality of sacrificial layers120and the plurality of interlayer dielectric layers130are alternately stacked is referred to as a stack structure.

Here, the sacrificial layer120may be arranged at the lowermost and uppermost parts of the stack structure, and the second interlayer dielectric layer130may be formed of an oxide-based material having a higher etch rate than the first interlayer dielectric layer110and a third interlayer dielectric layer to be described below. Furthermore, the sacrificial layer120is removed through a subsequent process to provide a space in which a control gate electrode to be described below is to be formed, may be formed of a material having an etching selectivity with the first interlayer dielectric layer110, the second interlayer dielectric layer130, and the third interlayer dielectric layer to be described below, for example, a nitride-based material.FIG. 2Billustrates five sacrificial layers120. However, the number of sacrificial layers120is only an example, and may be set to less or more than five.

Referring toFIG. 2C, the third dielectric layer140is formed over the sacrificial layer120formed at the uppermost part of the stack structure. The third interlayer dielectric layer140is densely formed to have a lower etch rate than the second interlayer dielectric layer130. For example, the third interlayer dielectric layer140may be formed of the same oxide-based material as the first interlayer dielectric layer110.

Here, the third interlayer dielectric layer140may be formed by a different deposition method from the second interlayer dielectric layer130, which may be selected from LP-CVD, PE-CVD, ALD, PVD and the like. Alternatively, although the third interlayer dielectric layer140is deposited by the same method, a densification process such as annealing or RTP may be performed to reduce the etch rate.

Referring toFIG. 2D, the third interlayer dielectric layer140, the stack structure, and the first interlayer dielectric layer110are selectively etched to form a hole H opening the substrate100.

Here, the hole H may have a circular or elliptical shape when seen from the top, and a plurality of holes H may be arranged in a matrix shape. In particular, when oxide and nitride layers are alternately stacked to form the stack structure, the stack structure having a vertical etch profile may be more easily formed than in an existing method in which oxide and polysilicon layers are alternately stacked.

Referring toFIG. 2E, the first to third interlayer dielectric layers110,130, and140exposed through the hole H are partially etched and recessed from the side surfaces of the sacrificial layers120.

Here, a wet etching process using an etching selectivity between the first to third interlayer dielectric layers110,130, and140and the sacrificial layer120may be performed to recess the first to third interlayer dielectric layers110,130, and140. At this time, the first and third interlayer dielectric layers110and140having a low etch rate are etched less than the second interlayer dielectric layer130. Furthermore, when the first and third interlayer dielectric layers110and140have a large difference in etch rate from the second interlayer dielectric layer130, the first and third interlayer dielectric layers110and140may be hardly etched. As the result of this process, uneven grooves are formed in the sidewalls of the hole H, and the remaining first to third interlayer dielectric layers110,130and140are referred to as first to third primary interlayer dielectric layer patterns110A,130A, and140A, respectively.

Referring toFIG. 2F, a charge blocking layer150and floating gate electrodes160A and160B are sequentially formed in the grooves formed in the sidewalls of the hole H. At this time, the uppermost and lowermost floating gate electrodes formed in the grooves of the first and third primary interlayer dielectric layers110A and140A are dummy floating gate electrodes160B which are formed to have a smaller width in a direction parallel to the substrate100than the floating gate electrodes160A formed in the grooves of the primary second interlayer dielectric layer patterns130A.

Here, the charge blocking layer150serves to block charges stored in the floating gate electrodes160A and160B from moving to the outside, and may be formed by conformally depositing an insulation material along inner walls of the grooves formed in the sidewalls of the hole H according to ALD or CVD. Furthermore, the floating gate electrodes160A and160B may be formed by the following process: a conductive material such as doped polysilicon is deposited to such a thickness to fill the grooves formed in the sidewalls of the hole H, etched until the side surfaces of the sacrificial layers120are exposed, and separated for the respective layers.

Referring toFIG. 2G, a tunnel insulation layer170is formed along the sidewalls of the hole H. The tunnel insulation layer170is a layer for charge tunneling, and may be formed by depositing an oxide-based material according to ALD or CVD.

Then, a channel layer180is formed in the hole H having the tunnel insulation layer170formed thereon. The channel layer180may be formed by depositing or growing a semiconductor material, for example, polysilicon. In this embodiment of the present invention, the channel layer180may be formed to such a thickness as to completely fill the hole H, but the present invention is not limited thereto. In another embodiment, the channel layer180may be formed to such a thickness as not to completely fill the hole H.

Referring toFIG. 2H, the first to third primary interlayer dielectric layer patterns110A,130A, and140A and the sacrificial layers120in both sides of the hole H are selectively etched to form a trench T exposing side surfaces of the sacrificial layers120.

Here, a plurality of trenches T may be arranged in a slit shape extended in a direction crossing the cross-sectional direction ofFIG. 2H. The remaining first to third primary interlayer dielectric layer patterns110A,130A, and140A and the remaining sacrificial layer120are referred to as first to third secondary interlayer dielectric layer patterns1108,130B, and140B and a sacrificial layer pattern120A, respectively.

Referring toFIG. 2I, the sacrificial layer pattern120A exposed through the trench T is removed. At this time, a wet etching process based on a dip-out method using an etching selectivity between the sacrificial layer pattern120A and the first to third secondary interlayer dielectric layer patterns1108,130B, and140B may be performed to remove the sacrificial layer pattern120A.

Referring toFIG. 2J, a control gate electrode190is formed in a space where the sacrificial layer pattern120A is removed. The control gate electrode190may be formed to have a larger width in a direction parallel to the substrate100than the floating gate electrodes160A and160B.

Here, the control gate electrode190may be formed by the following process: a conductive material such as doped polysilicon or metal is deposited to such a thickness as to fill the space where the sacrificial layer pattern120A is removed, etched until the side surfaces of the first to third secondary interlayer dielectric layers1108,130B, and140B are exposed, and separated for the respective layers. Meanwhile, in order to improve an interfacial characteristic before the control gate electrode190is formed, a barrier metal layer may be formed by conformally depositing titanium nitride (TiN) or the like along the inner walls of the spaces where the sacrificial layer patterns120A are removed.

Through the above-described fabrication method, it is possible to fabricate the nonvolatile memory device in accordance with the embodiment of the present invention.

Referring toFIG. 2J, the nonvolatile memory device in accordance with the embodiment of the present invention may include the channel layer180protruding vertically from the substrate100, the tunnel insulation layer170surrounding the side surface of the channel layer180, the stack structure in which the plurality of floating gate electrodes160A and160B and the plurality of control gate electrodes190are alternately stacked along the channel layer180, the charge blocking layer150interposed between the floating gate electrodes160A and1608and the control gate electrode190, and the first to third secondary interlayer dielectric layer patterns110B,130B, and140B surrounding the outer surfaces of the floating gate electrodes160A and160B.

Here, the floating gate electrodes1608positioned at the lowermost and uppermost parts of the stack structure are dummy floating gate electrodes, and have a smaller width in a direction parallel to the substrate100than the floating gate electrode160A positioned between two control gate electrodes190. Furthermore, the control gate electrode190may have a larger width in the direction parallel to the substrate100than the floating gate electrodes160A and160B.

Meanwhile, the nonvolatile memory device in accordance with the embodiment of the present invention may include a plurality of memory cells arranged along the channel layer180, and each of the memory cells may include the floating gate electrode160A and the pair of control gate electrodes190adjacent to the floating gate electrode160A.

In the nonvolatile memory device and the method for fabricating the same in accordance with the embodiment of the present invention, it is possible to minimize the size of the dummy floating gate electrode positioned in the uppermost or lowermost part among the plurality of floating gate electrodes formed along the channel protruding vertically from the substrate and adjacent to the control gate electrode and the substrate. Accordingly, an area where the dummy floating gate electrode is contacted with the control gate electrode decreases to reduce a coupling ratio therebetween. Therefore, it is possible to not only prevent an abnormal program operation in the dummy floating gate electrode but also prevent a channel current from decreasing during a read operation.

In accordance with the embodiments of the present invention, the size of the dummy floating gate electrode may be minimized to reduce a coupling ratio between the dummy floating gate electrode and the control gate electrode, which makes it possible to improve an operation characteristic of the nonvolatile memory device.