Method to smooth transitions in an ADC for current regulation

The present invention is directed at providing methods in a circuit for smoothing transitions relating to a signal processing function. A reference signal is produced that relates to a DAC output code. The reference signal is used as a starting point, and is compared to the input signal. A feedback signal is produced that is used to adjust the reference. The invention can be used to implement signal processing functions such as peak detection, noise filtering, peak suppression, and the like, in which the transitions in the signal are smoothed. The invention can implement these functions with a minimal complexity and a minimal die area.

FIELD OF THE INVENTION

The present invention is related to signal processing, and more specifically to smoothing transitions in an ADC.

BACKGROUND OF THE INVENTION

Generally, signal processing involves the use of a digital signal processor to perform the desired signal processing function. Typically, the following method is used in performing a signal processing function. First, an analog signal is filtered with an anti-alias filter. The analog signal is then converted to a digital signal by means of an ADC (analog to digital converter). Next, a DSP (digital signal processor) is used to perform the desired signal processing function on the digital signal. The digital signal is then converted back to an analog signal by means of a DAC (digital to analog converter). Finally, the signal is filtered with a low pass filter.

The signal processing system described above requires many complex components taking up resources on the circuit. For example, extra power supplies may be needed to provide power to the DSP (digital signal processor), ADC, or other components. Additionally, the available die area on the chip is reduced by each extra component placed on it. For example, the DSP takes up valuable resources on the circuit. Even simple signal processing functions may require many extra components taking up valuable resources.

Many signal processing tracking functions may dither between values, creating a noisy signal. As a result of the noise, unnecessary adjustments within a circuit may be made. What is needed is a way to smooth the transitions and reduce the unwanted noise from the signal processing function.

SUMMARY OF THE INVENTION

The present invention is directed at smoothing transitions in an ADC. The invention is also directed at implementing peak detection with minimal complexity and a minimal die area.

According to one aspect of the invention, a reference signal, is used as a starting point and is adjusted by logic to produce the desired peak detection signal processing function that has smooth transitions. Comparisons are made between the reference signal and an input signal. The reference signal is adjusted to obtain the smoothed peak detection function.

According to another aspect of the invention, algorithms implement a signal processing function based on the history of the last n comparisons between the reference signal and the incoming signal, where n is a pre-determined number greater than zero. The algorithm may also generate feedback that modifies the reference signal.

According to another aspect of the invention, a decision level processing circuit that is arranged to make a comparison between the reference signal and an input signal. The decision level processing circuit is configured to produce a desired signal processing function in response to the comparison.

According to another aspect of the invention, a method for performing peak detection for an incoming signal is provided. The method includes making a comparison between a reference code relating to a code and another signal, applying a peak detection signal processing function to the signal, and producing an output signal in response to the comparison and the peak detection signal processing function.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Throughout the specification and claims, the following terms take the meanings explicitly associated herein, unless the context clearly dictates otherwise. The meaning of a, an, and the includes plural reference, the meaning of in includes in and on. The term connected means a direct electrical connection between the items connected, without any intermediate devices. The term coupled means a direct electrical connection between the items connected or an indirect connection through one or more passive or active intermediary devices. The term circuit means either a single component or a multiplicity of components, either active and/or passive, that are coupled to provide a desired function. The term signal means at least one current, voltage, or data signal.

Briefly described, the present invention is directed at a method for smoothing transitions in an ADC for current regulation. A reference signal is used as a starting point and is adjusted to obtain the desired peak detection function. According to one embodiment of the invention, comparisons are made between a reference signal, relating to the output code of a DAC (digital to analog conversion) circuit, and the input signal thereby generating a comparison result signal. A method may then be applied to the comparison result signal to implement the method for smoothing transitions of a signal. The method is also used to help generate a feedback signal that may modify the reference signal.

FIG. 1 is an overview schematic block diagram of a circuit that may be used to smooth transitions in an ADC, in accordance with aspects of the invention. As shown in the figure, smoothing circuit 100 includes anti-alias filter 102 , controlled reference circuit 104 , resistance circuit 106 , comparator circuit 108 , and logic circuit 110 .

Logic circuit 100 is connected as follows. Anti-alias filter 102 includes an input coupled to signal SI, an output coupled that is coupled to an input of controlled reference circuit 104 , and an output that is coupled to resistance circuit 106 . Controlled reference circuit 104 has an input that is coupled to anti-alias filter 102 , an input that is coupled to logic circuit 110 , and an output that is coupled to comparator circuit 108 . Resistance circuit 106 has an input that is coupled to anti-alias filter 102 , and an output that is coupled to comparator circuit 108 . Comparator circuit 108 has an input that is coupled to controlled reference circuit 104 , an input that is coupled to resistance circuit 106 , and an output that is coupled to logic circuit 110 . Logic circuit has an input that is coupled to comparator circuit 108 , an output that is coupled to controlled reference circuit 104 , and another output coupled to signal S 4 .

Logic circuit 100 operates as follows. Input signal S 1 is filtered by anti-alias filter 102 producing signal S 2 . Controlled reference circuit 104 produces reference signal S 3 that relates to signal S 2 . According to one embodiment of the invention, controlled reference circuit 104 is a DAC. According to an embodiment, controlled reference circuit 104 produces a reference voltage signal that corresponds to a given input signal (S 2 ). Signal S 3 is adjusted in response signal S 8 output by peak detector logic circuit 110 . By directly adjusting the controlled reference circuit output reference signal S 3 , a signal processing function in which unwanted transitions are smoothed may be applied to input signal S 1 without the use of a DSP and ADC.

Resistance circuit 106 produces signal S 7 in response to incoming signal S 2 . Signal S 7 directly relates to input signal S 2 . Comparator circuit 108 compares signal S 3 , output from controlled reference circuit 104 , and signal S 7 , output by resistance circuit 106 . Comparator circuit 108 determines when the reference signal is larger/smaller than the input signal. In response to the comparison between signal S 3 output from controlled reference circuit 104 , and the input signal S 7 , comparator circuit 108 produces signal S 20 that relates to the comparison. Smoothing logic circuit 110 produces feedback signal S 8 that is used to adjust signal S 3 produced by controlled reference circuit 104 . Logic circuit 110 contains the logic necessary to provide feedback signal S 8 used to adjust signal S 3 output by controlled reference circuit 104 to perform the smoothing function on the incoming signal. Logic circuit 110 may also contain counters and other components to produce the desired smoothing function. According to one embodiment of the invention, the smoothing is applied to a peak detection signal processing algorithm. Signal S 3 is adjusted upward when the input signal moves up and signal S 3 is adjusted downward when the input signal moves down.

Circuit 100 has several advantages. The architecture has a very low cost of manufacture, and utilizes a small die area. Additionally, the circuit does not require the use of a digital signal processor to perform the smoothing functions.

FIG. 2 is a schematic diagram of a detector circuit, in accordance with aspects of the invention. As shown in the figure, detector circuit 200 includes, resistor array X 301 (resistor R 4 , resistor R 6 , and resistor R 8 ), current source IRef 1 , current source IRef 2 , resistor array X 302 , multiplexer X 304 , comparator X 310 , register Reg 3 , and decision circuit X 314 . Multiplexer X 304 includes switches MR 1 through MR 33 . Resistor array X 302 includes resistors RMR 1 through RMR 33 .

Detector circuit 200 is connected as follows. Resistor R 4 is coupled between node N 31 and node N 32 . Resistor R 6 is coupled between node N 32 and node N 33 . Resistor R 8 is coupled between node N 33 and node N 34 . Current source IRef 1 is coupled between node N 34 and node N 36 . Node N 36 is coupled to a reference voltage (gnd). Resistor RMR 1 is coupled between node N 32 and node NMR 1 . Switch MR 1 is coupled between node NMR 1 and node N 35 , and has a switch control coupled to an input to register reg 3 . Resistor RMR 2 is coupled between node NMR 1 and node NMR 2 . Switch MR 2 is coupled between node NMR 2 and node N 35 , and has a switch control coupled to the input to register reg 3 . Resistor MR 3 is coupled between node NRM 2 and node NMR 3 . Switch MR 3 is coupled between node NMR 3 and node N 35 , and has a switch control coupled to the input to register reg 3 . These connections continue until resistor RMR 33 is coupled between NMR 32 and node NMR 33 , and switch MR 33 is coupled between node NMR 33 and node N 35 , and has a switch control coupled to the input to register reg 3 . Current source IRef 2 is coupled between node NMR 33 and a reference voltage (gnd). Comparator X 310 has a non-inverting input ( ) coupled to node N 35 , an inverting input ( ) coupled to node N 34 , and an output coupled to node N 312 . Peak detection decision circuit X 314 has an input coupled to node N 312 , an output coupled to register Reg 3 , and another output coupled to register Reg 3 .

Detector circuit 200 operates as follows. Detector circuit 200 is directed at peak detection for voltage VPS and smoothing the transitions relating to the peak detection (See FIGS. 4A and 4B and related discussion).

The specific operation of detector circuit 200 will now be described. Resistor array X 302 , current source IRef 2 , and multiplexer X 304 act together as a controlled reference circuit (in this particular case a DAC), producing reference signal S 3 in response to incoming signal S 2 . Resistor array X 301 provides a VPS voltage representation signal (S 7 ). Resistor array X 302 provides a reference voltage relating to the input signal S 2 . The switches (MR 1 -MR 33 ) actuate in response to signal S 8 . Signal S 8 has a corresponding VPS voltage (VS 8 rep). In response to the switches actuating, the signal S 3 at node N 35 increases or decreases. According to one embodiment of the invention, current source Iref 1 is created by a shunt circuit that sets the voltage at node N 33 to a known voltage. Other reference voltages may be implemented and used.

Comparator X 310 compares signal S 3 to signal S 7 producing comparison result signal S 20 at node N 312 . Signal S 20 has a voltage corresponding to a logical level of low when the voltage of signal S 7 is greater than the voltage of signal S 3 . Correspondingly, signal S 20 has a voltage corresponding to a logical level of high when the voltage of signal S 7 is less than the voltage of signal S 3 . Signal S 8 is produced by register Reg 3 in response to comparison result signal S 20 , signal S 3 , clock signal CLK, and control signal ENABLE. Decision circuit X 314 receives comparison result signal S 20 and determines when signal S 3 should increase and when it should decrease, and the result is stored in register reg 3 . According to one embodiment of the invention, signal S 3 increases when the voltage of S 3 is lower than the voltage of S 7 and, correspondingly, signal S 3 decreases when the voltage of S 3 is higher than the voltage of signal S 7 .

According to one embodiment of the invention, detector circuit 200 is used in a battery charging circuit.

FIGS. 3A-3B are schematic block diagrams of the detector circuit illustrated in FIG. 2 incorporated into a battery charging circuit, in accordance with aspects of the invention. As shown in the figure, battery charging circuit 300 includes the following additional components as shown in FIG. 2 . The components include transistor Q 1 , decision logic circuit X 306 , transistor array X 308 , cell X 318 , and input VIN. Transistor array X 308 includes transistors M 5 - 1 through M 5 - 33 and resistors RM 501 through RM 533 . Decision logic circuit X 306 includes register Reg 1 , register Reg 2 , register Reg 3 , decision up/down circuit X 312 , decision circuit X 314 , and charger shifting circuit X 316 .

Battery charging circuit 300 is directed at detecting peaks in voltage VPS and smoothing the transitions relating to the signal (See FIGS. 4A and 4B and related discussion). According to one embodiment of the invention, battery charging circuit 300 is configured to respond with a fast attack rate and a slow decay rate. In other words, battery charging circuit 300 responds smoothly and quickly to increases in voltage and smoothly and slowly to decreases in voltage.

The operation of the additional components illustrated in FIGS. 3A and 3B will now be described. Samples of comparison result signal S 20 are stored in registers Reg 1 and Reg 2 . A first result from comparison result signal S 20 is stored in register Reg 1 , and a second result from comparison signal S 20 is stored in register Reg 2 . According to one embodiment of the invention, only one register is used. According to this particular embodiment, the input is sampled directly by the decision logic. Decision up/down circuit X 312 utilizes an attack counter and delay counter to aid in determining when signal S 4 should increase, decrease, or remain the same. Using an algorithm based upon the two comparator results stored in Reg 1 and Reg 2 , the logic in decision up/down circuit X 312 determines when the decay counter should be increased, decreased, or reset, and determines when the attack counter should be increased, decreased, or reset. Incrementing and decrementing the attack counter and decay counter affects how quickly the detector reacts to changes in VPS. Generally, decision logic circuit X 312 implements a fast attack and slow decay. Using the fast attack allows the peak detector to quickly react to the peaks of VPS. Using the slow decay allows the peak detector to slowly react to a diminishing VPS (See FIG. 4B for an exemplary graph). Additionally, the peak detector will not dither between two values, thereby smoothing the output of the circuit. Based on the values of the attack counter and decay counter, decision circuit X 312 makes a determination as to whether signal S 4 should increase, decrease, or remain the same.

Charger shifting circuit X 316 includes drivers that produce a signal S 4 to control transistor array X 308 . Transistor array X 308 acts as a DAC (digital/analog converter). Charger shifting circuit X 316 adjusts signal S 4 according to the input that it receives from decision logic circuit X 312 . Signal S 4 is converted into signal S 5 by transistor array X 308 and is propagates to cell X 318 .

The addition of detector circuit 200 to a battery charging circuit allows a smoother operation of the battery charger with a low cost and a small die area. The use of the peak detector avoids seeing the temporary VPS variations that could be detected as a charger not present signal thereby affecting the charging of cell X 318 .

FIG. 4A illustrates an exemplary graph of VPS and VIN over time. As shown in figure, the graph shows voltage VPS periodically dropping below the VIN voltage. Each time VPS drops below VIN, a charger not present signal could be detected by the battery charging circuit thereby adversely affecting the charging of the battery.

FIG. 4B illustrates an exemplary graph of a peak detector signal processing function applied to VPS over time, in accordance with aspects of the invention. As shown in the figure, the graph illustrates voltage VPS and signal VS 8 rep over time. Signal VS 8 rep is the corresponding VPS voltage defined for a given S 8 code. As can be seen, signal VS 8 rep does not drop below the VIN voltage thereby avoiding any charger not present signals. According to one embodiment of the invention, when VPS increases for two consecutive clock cycles, signal VS 8 rep increases. The peak detector signal illustrated in FIG. 4B is produced by the peak detector circuit illustrated in FIG. 3 . The peak detector used in the battery charging circuit has a fast attack and a slow decay. In other words, signal VS 8 rep increases rapidly in response to increases in voltage VPS and signal VS 8 rep decreases slowly in response to decreases in voltage VPS. According to one embodiment, signal VS 8 rep decreases when voltage VPS decreases for 255 consecutive clock cycles. This results in a slow decay, so that signal VS 8 rep decreases slowly when voltage VPS decreases. The slow decay prevents erratic behavior of the overall circuit. If decay were too fast, valleys in the VPS voltage might be detected as charger not present, as shown in FIG. 4 A. The attack counter and decay counter may be adjusted to change the characteristics of signal VS 8 rep.

FIG. 5 shows a flow chart for an exemplary peak detection signal processing circuit, according to one embodiment of the invention. The method for signal processing architecture 500 includes blocks 502 , 504 , 506 , and 508 .

The flow for signal processing architecture 500 proceeds as follows. After a start block, the logic moves to block 502 . At block 502 , a signal is filtered with an anti-alias filter producing a filtered signal. The logic then moves to block 504 , at which point the filtered signal is converted into a reference signal. According to one embodiment of the invention, the reference signal relates to a DAC output code. The reference signal itself is adjusted to obtain the desired peak detection signal processing function. The reference signal may be adjusted for feedback generated in response to the peak detection algorithm implemented at block 508 . Stepping to block 506 , a comparison is made between the incoming signal and the reference signal. Moving to block 508 , the reference signal may be adjusted to perform a peak detection function on the incoming signal. The logic then steps to an end block and terminates.

FIG. 6 illustrates a flow chart implementing an exemplary method of peak detection with smooth transitions, in accordance with aspects of the invention. Other algorithms may be implemented using the signal processing architecture described (See FIGURES and related discussion below). For example, single comparison algorithms may be implemented.

After a start block, the logical flow moves to block 602 . At block 602 , the multiplexer node is set by the analog/digital conversion of the analog signal. Transitioning to block 604 , the method determines the logical value of the comparison between the reference signal relating to the output code and the input signal itself. Moving to block 606 , the method determines whether the logical value of the comparison between the signals is high or low. When the logical value of the comparison between the reference signal and the input signal is low, the logic moves to block 608 . At block 608 , the process decrements the multiplexer counter. Stepping to block 610 , another comparison is made between the signals. At the second comparison, the output code signal has been reduced by one least significant bit. Moving to decision block 612 , the process determines whether the second comparison is high or low. When the logical value of the second comparison between the signals is low, the logic moves to block 614 . At block 614 , the process resets the attack counter and increases the decay counter. Next, at decision block 616 , the process determines whether the decay counter has overflowed. When the decay counter has not overflowed the process moves to block 618 at which point the process increments the multiplexer counter. When the decay counter overflows, the logic moves to block 622 . At block 622 , the process resets the decay counter and decrements the address counter. The logic then returns to block 604 .

When the second comparison between the signals is high, the logic moves to block 620 . At block 620 , the process resets the decay counter and the attack counter. The logical flow then moves to moves to block 618 .

When the logical value of the first comparison between the reference signal relating to the output code and the input signal is high, the logic moves to block 624 . At block 624 , the process increments the multiplexer counter. Moving to block 626 , the decay counter is reset and the attack counter is incremented. Transitioning to decision block 628 , the method determines whether the attack counter has overflowed. When the attack counter has overflowed, the logic moves to block 632 , at which point the attack counter is reset, and the address counter is incremented. When the attack counter has not overflowed, the logic moves to block 630 , at which point the multiplexer counter is decremented. The logic then returns to block 604 and repeats itself.

FIG. 7 illustrates a flowchart for smoothing transitions for a peak detection function, according to one embodiment of the invention. After a start block, the logic moves to decision block 701 , at which point the logic determines whether a voltage of a signal has decreased by more than a pre-determined voltage. The pre-determined voltage may be zero. When the signal voltage has not increased by more than the pre-determined voltage, then the logic moves to block 710 . When the signal voltage has decreased by more than the pre-determined voltage, the logic moves to block 702 , where an attack counter is reset. Transitioning to block 703 , a decay counter is incremented. The logic then moves to decision block 704 , at which point the method determines whether the decay counter has overflowed. When the attack counter has not overflowed, the logic moves to block 705 , where the multiplexer counter is adjusted if the multiplexer counter was previously adjusted at block 701 . If the multiplexer counter was adjusted at block 701 , then the multiplexer counter will be changed to what it was previous to the determination at block 701 . The logic then steps to an end block and terminates. When the attack counter has overflowed, the logic moves to block 706 .

At block 706 , where the address counter is decremented. The logic then moves to block 707 where the decay counter is reset. Flowing to block 708 , the multiplexer counter is decremented, unless the multiplexer counter was previously decremented at block 701 . The logic then steps to an end block and terminates.

Returning to the no path for decision block 701 , when the signal has not decreased by a pre-determined voltage the logic moves to decision block 710 , where the method determines whether the signal voltage has increased by more than a second pre-determined voltage. The second pre-determined voltage may be zero. When the signal has increased by more than the second pre-determined voltage, the logic moves to block 712 , at which point the decay counter is reset. Transitioning to block 713 , the attack counter is incremented. Moving to decision block 714 , the method determines whether the attack counter has overflowed. When the attack counter has not overflowed, the logic moves to block 718 where the multiplexer counter is adjusted to the value it was at the beginning of block 701 . The logic then steps to an end block and terminates. When the attack counter has overflowed, the logic moves to block 722 . At block 722 , the address counter is incremented. The logic then moves to block 726 , where the attack counter is reset. Transitioning to block 730 , the multiplexer counter is incremented, unless it was already incremented at block 710 . The logic then ends.

Returning to the no path for decision block 710 , when the signal voltage has not increased by more than the second pre-determined voltage, the logic moves to block 734 where the attack counter is reset. Moving to block 738 , the decay counter is reset. Transitioning to block 744 , the multiplexer counter is adjusted to the value it was at the beginning of block 710 if the multiplexer counter was changed at block 701 or block 710 . The logic then steps to an end block and terminates.

FIG. 8 is a flowchart of a method for smoothing transitions of an ADC relating to a peak detection function, according to one embodiment of the invention.

After a start block, the logical flow moves to block 802 . At block 802 , the multiplexer node is set by the analog/digital conversion of the analog signal. Transitioning to block 804 , the method determines the logical value of the comparison between the reference signal relating to the output code and the input signal itself. Moving to block 806 , the method determines whether the logical value of the comparison between the signals is high or low. When the logical value of the comparison between the reference signal and the input signal is low, the logic moves to block 808 . At block 808 , an attack counter is reset, and a decay counter is incremented. The logic then moves to decision block 810 , where the method determines whether the decay counter has overflowed. When the decay counter has not overflowed, the logic returns to block 804 . When the decay counter has overflowed, the logic moves to block 812 . At block 812 , the address counter is decremented, the multiplexer counter is decremented, and the decay counter is reset. The logic then moves to block 804 .

When the logical value of the comparison made by the logic at decision block 806 between the reference signal and the input signal is high, the logic flows to block 814 . At block 814 , the decay counter is reset and the attack counter is incremented. Transitioning to decision block 816 , a determination is made as to whether the attack counter has overflowed. When the attack counter has not overflowed, the logic returns to block 804 . When the attack counter has overflowed, the logic moves to block 818 . At block 818 , the address counter is incremented, the multiplexer counter is incremented, and the attack counter is reset. The logic then returns to block 804 .