Test Architecture for High Throughput Testing of Pixel Driver Chips for Display Application

Test structures and methods of testing pixel driver chip donor wafers are described. In an embodiment, a redistribution layer is formed over a pixel driver chip donor wafer and probed to determine known good dies, followed by removal of the RDL. In other embodiments, test routing is formed in the pixel driver chip using a polycide material or doped region in the semiconductor wafer.

BACKGROUND

Field

Embodiments described herein relate to design-for-test architecture. More particularly, embodiments relate to design-for-test architectures for pixel driver chip donor wafers for micro LED displays.

Background Information

Micro light emitting diode (LED), also known as μLED, is an emerging flat panel display technology. The μLED-based display panel includes arrays of microscopic LEDs forming the individual pixel elements. The pixel elements in turn can be operated with a backplane formed of thin film transistors (TFT), metal-oxide semiconductor field-effect transistor (MOSFET) technology, or an array of pixel driver chips where local arrays of the μLEDs may each be driven by a corresponding pixel driver chip, which may also have microscopic dimensions on the order of the μLEDs to multiple pixel groups. It has been proposed to fabricate a display panel backplane with redundant uLEDs and redundant pixel driver chips to compensate for potential defects associated with the fabrication and pick-and-place bonding technologies.

SUMMARY

In accordance with embodiments, methods of testing pixel driver chip donor wafers are described utilizing both temporary and permanent test structures. In an embodiment, a temporary redistribution layer (RDL) is formed over a pixel driver chip donor wafer and probed to determine known good dies, followed by removal of the RDL. In an embodiment, a method of testing a pixel driver chip donor wafer for known good dies includes forming an array of pixel driver chip areas in a wafer, forming a back-end-of-the-line (BEOL) build-up structure over the array of pixel driver chip areas, forming a redistribution layer (RDL) over the BEOL build-up structure, the RDL including an array of reticle areas; each reticle area encompassing a corresponding sub-array of pixel driver chip areas and including a sub-area of test pads, probing each sub-area of test pads to test the corresponding sub-array of pixel driver chip areas, and removing the RDL.

In other embodiments, permanent test routing is formed in the pixel driver chip using a polycide material or doped region in the semiconductor wafer. In an embodiment a pixel driver chip includes a semiconductor substrate including a device region, a BEOL build-up structure on the semiconductor substrate, the BEOL build-up structure including a plurality of metal wiring layers, and a plurality of landing pads, chip sidewalls spanning the semiconductor substrate and the BEOL build-up structure, and an electrical connection extending to a first sidewall of the chip sidewalls, wherein the electrical connection is formed of a polycide material or doped region of the semiconductor substrate.

DETAILED DESCRIPTION

Embodiments describe design-for-test (DFT) architectures, and methods of testing an array of pixel driver chips on a donor wafer. Specifically, the pixel driver chips may be designed for μLED-based display panels. Testing may be performed on the donor wafer prior to singulation of the pixel driver chips to qualify the pixel driver chips prior to assembly into the μLED-based display panels. In this manner only known good pixel driver chips are integrated into a display, mitigating display yield losses that could otherwise be associated with defective pixel driver chips, for example, obtained from outlier donor wafers or process variation across a donor wafer. Token-based control schemes for the pixel driver chip areas can also be leveraged in order to select entire rows and/or columns within a reticle area.

In one aspect, pixel driver chips with dimensions on the order of the μLEDs to multiple pixel groups, along with the number of landing pads for operation can require the pixel driver chip landing pads to be insufficiently large for landing of test probes. Furthermore, the number of pixel driver chips per donor wafer can be in the range of hundreds of thousands which can take a prohibitively long time for testing of each wafer during manufacturing. In accordance with embodiments, DFT architectures and methods are described in which pixel driver chips within each reticle field are connected together through an interconnect such as a sacrificial metal layer, polycide, or diffusion region and tested together with larger test pads, utilizing space at the edge of the reticle field which can also be used to provide power and ground signal, etc. In this manner it may be possible to test all pixel driver chips in one reticle field in one touchdown, and to test all pixel driver chips on a donor wafer in significantly reduced time.

Referring now toFIG.1a cross-sectional side view illustration is provided of a donor wafer102including an array of reticle areas104, each reticle area104including a sub-array of pixel driver chip areas106and test pad area108in accordance with an embodiment. For example, the test pad area108including test pads114can be along a single edge110of the reticle area104or a plurality of edges110, including all edges/sides.

FIG.2is a process flow for a method of testing a donor wafer102including an array of pixel driver chip areas106in accordance with an embodiment.FIG.3is a schematic cross-sectional side view illustration of a redistribution layer (RDL) formed over a donor wafer102reticle area104including a sub-array of pixel driver chip areas106and a sub-array of test pads114in accordance with an embodiment. In interest of clarity and conciseness, the description of the process flow ofFIG.2is made with reference to the structure ofFIG.3.

At operation2010an array of pixel driver chip areas106is formed in a semiconductor substrate100. A back-end-of-the-line (BEOL) build-up structure116is then formed over the array of pixel driver chip areas104at operation2020. The BEOL build-up structure116may include various dielectric layers118(e.g. oxides, low-k materials, etc.) and metal wiring layers120connected with vias122. Metal wiring layers120may be referred to as M1-Mz, with M1 being a lower metal layer and Mz being an upper metal layer. In accordance with embodiments, Mz metal wiring layer can also be used for metal routing at the reticle edge. The BEOL build up structure116may additionally include a top passivation layer124(e.g. nitride) and an array of landing pads126. As shown, the BEOL build-up structure116can further include a perimeter (metal) seal ring128. Together the perimeter seal ring128and top passivation layer124can provide mechanical protection and prevent the ingress of moisture, etc.

At operation2030a redistribution layer (RDL)130is then formed over the BEOL build-up structure116. Referring briefly back toFIG.1the RDL130is formed over the entire array of reticle areas104, with each reticle area encompassing a corresponding sub-array of pixel driver chip areas106and a sub-array of test pads114. The RDL130can be formed in the same facility as the BEOL build-up structure or alternatively in a packaging facility using different deposition techniques. As shown, the RDL130similarly include one or more dielectric layers132and one or more metal wiring layers134connected with vias136, as well as the sub-arrays of test pads114. The test pads114may have a larger area than landing pads126to facilitate probing. In accordance with embodiment, metal routing in upper metal layer(s), such a Mz metal wiring layer120, can help reduce wiring required in the RDL130. For example, this may facilitate use of a single metal wiring layer134RDL130. This may reduce process time, and overall cost.

The sub-arrays of test pads114can be arranged in test pad areas108that are optionally laterally outside of the pixel driver chip areas106. This may facilitate row/column testing processes at operation2040where each sub-array of test pads is probed to test the corresponding sub-arrays of pixel driver chip areas106for known good dies (KGD). Once KGD testing is complete the RDL130can be removed at operation2050, followed by cleaning and singulation of individual pixel driver chips for subsequent integration into an optoelectronic module. For example, singulation may include etching through the wafer and the BEOL build-up structure using a suitable technique such as dry reactive ion etching (DRIE).

Referring now toFIGS.4-6schematic top view illustrations are provided for various columnar and row routing connections in accordance with embodiments. For example, this may be routing within the RDL130which is connected to landing pads126for each pixel driver chip area106. It is to be appreciated that whileFIGS.4-6are illustrated separately, this is for clarity, and that the routings for each ofFIGS.4-6can be combined. Furthermore, the routings illustrated are exemplary and actual implementation may be more complex. Lastly, the routings illustrated are not limited to the RDL130and may be otherwise provide, such as with diffusion layers, polycide layers, and metal wiring layers within the BEOL build-up structure as will be described in further detail with regard toFIGS.9-13.

FIG.4is a schematic top view illustration of columnar connection layout for reticle probe pads in accordance with an embodiment. The test pads114shown inFIG.4can be for a variety of signals such as data, data clock, DFT scan enable, DFT program enable, vertical selection token (VST) pixel clock, pixel driver chip mode, configuration update, etc. In the exemplary embodiment illustrated, a scan data in (SDI) and scan data out (SDO) signals can be applied to test pads114A and114B, respectively. Data line column142can be connected to a landing pad126A for each pixel driver chip area106to input a scan data signal. Similarly, data line column144can be connected to a landing pad126B for each pixel driver chip. VST signals can be applied to test pads114C, with pixel driver chip areas106connected through a daisy-chain within a VST line column146formed of tie bars147connecting landing pads126C and126D of adjacent pixel driver chip areas106.

FIG.5is a schematic top view illustration of row connection layout for reticle probe pads in accordance with an embodiment. In accordance with embodiments, power and ground can potentially be shared through horizontal row connections. Power and ground may be shared by all pixel driver chip areas106in one reticle area104. In the exemplary embodiment illustrated, a power (Vdd) and ground (Vss) signals can be applied to test pads114D and114E, respectively. Power line rows148can connect to a corresponding row of pixel driver chip areas106and landing pads126E. Similarly ground line rows150can connect to a corresponding row of pixel driver chip areas106and landing pads126F.

FIG.6is a schematic top view illustration of shared global connection in accordance with an embodiment. The test pads114shown inFIG.6can be for a variety of signals such as bias voltage (Vbias), reference voltage (Vref), initialization voltage (Vini), etc. The global signals may be shared by multiple columns through a shorting bar at the reticle area104edge. In the exemplary embodiment illustrated, a Vref and Vbias signals can be applied to test pads114F and114G, respectively. Global reference voltage line columns152can connect to a corresponding column of pixel driver chip areas106and landing pads126G. Global bias voltage line columns154can connect to a corresponding column of pixel driver chip areas106and landing pads126H. In the illustrated embodiment, the plurality of global reference voltage line columns152is divided into a plurality of sets, each set connected to a different global reference voltage test pad114F. This may be achieved with a shorting bar156. Similarly, the global vias voltage line columns154can be connected with a shorting bar158, and test pad114G. While not similarly illustrated, the power and ground routing inFIG.5can be similarly connected and shared.

In an exemplary testing procedure token-based control schemes for the pixel driver chip areas can be leveraged, where adjacent pixel driver chip areas in a column are connected through a daisy-chain. Data, data clock, and VST probing pads can be dedicated for each column, and global signals can be shared by multiple columns with a shorting bar at the reticle area edge. Power and ground can additionally be shared by all pixel driver chip areas within one reticle area.

In an embodiment, the wafer102may be tested one reticle area104at a time. Testing of each reticle area104can include broadcasting a plurality of cycles of scan-data in (SDI) to all pixel driver chip areas106in a row of pixel driver chip areas, producing a scan-data out (SDO) data stream for each pixel driver chip area, comparing a downstream version of the SDO data stream for each pixel driver chip areas with an expected data stream, storing values of the compared data streams (e.g. with the stored values (e.g. 0, 1) indicative if an error is present in the compared data streams), and shifting out the stored values as the DFT output.

In operation, a DFT controller may first send VST signals to each test pad114C to turn on a specified row, or rows, and broadcast pixel driver configuration data across a row of pixel driver chip areas106. Thus, all pixel driver chip areas106in the same row may be tested at once, and receive the same signal.

The scan-data out from all pixel drivers in the same column share a common scan-data out (SDO) bus to send the data back to the DFT controller. The SDO bus lines may be data line columns144. Likewise, the SDI bus lines may be data line columns142. In an embodiment the data line columns are bi-directional, and the SDO and SDI signals share the same data line column.

Referring now toFIG.7, an illustration is provided of the scan-chain connection between a pixel driver chip area106and DFT controller101. As shown in the scan-chain, pipelined positive triggered flip-flops160and negative triggered flip-flops162are located near SDI output terminals of the DFT controller101, and SDO input terminals of the DFT controller. SDI data line column142and SDO data line column142routing on the wafer may be through routing of the pixel driver scan connections, to landing pads126A,126B on the pixel driver chip areas106chips as SDI and SDO input and output terminals. The shift path165within a pixel driver chip area106may include a chain of positive triggered flip-flops166, including a first positive triggered flip-flop160coupled to the SDI terminal. A clock gater168is coupled to a last positive triggered flip-flop in the chain of positive triggered flip-flops166to covert logical 1 non-return-to-zero (NRZ) output Q1from the last positive triggered flip-flop to a pulse (P) return-to-zero (RZ) output Q2from the clock gater168. Simplified illustrations of the positive triggered flip-flops166are provided to show the scan input (SI), output (Q), and scan clock (triangle). Simplified clock gater168illustration includes enable (E), test enable (TE), enable clock (ECK), and scan clock (triangle). As shown, the output Q1is fed to the enable (E) input of the clock gater168. As shown, the flip-flops166in the scan-chain are negatively triggered, and the clock gater168is inserted in the shift path between the last flip-flop166and the SDO data line column142.

In an embodiment, a method of testing a pixel driver chip area106includes broadcasting a plurality of cycles of scan-data in (SDI)210to a pixel driver chip area, generating a square waveform output signal (e.g. 0, 1) from a chain of positive triggered flip-flops166, receiving the square waveform output signal with a clock gater168in the pixel driver chip area, and transmitting a pulse P signal from the clock gater168to a negative triggered flip-flop162in DFT controller101, and generating a square waveform output signal with the negative triggered flip-flop162in the DFT controller101. In an embodiment, an automatic test pattern generation (ATPG) model is run in which the clock gater168is modeled as a positive triggered flip-flop160.

While the exemplary embodiments thus far have illustrated testing capability with digital data SDI/SDO scans embodiments are not so limited. For example, analog testing can also be performed.

Referring toFIG.8, an exemplary 6 transistor (6T) and 1 storage capacitor (1C) pixel circuit is illustrated which may include Cst: storage capacitor for holding the data voltage, T1: current driving transistor, T2: switch for sample and hold, T3: switch for sense column line connection, T4: switch (row) for turning the emission on and off, T5: switch (column) for turning the emission on and off, and T6: switch (column) for selecting sense column. In one embodiment, T6may be part of a readout column select. In one embodiment, the digital signals are SCAN: generated by row driver (e.g., to sample Vdata), READ: generated by row driver (e.g., to connect a pixel circuit to sense column line), EM-ROW (e.g., to emit light if EM-COL is also active), and EM-COL (e.g., to emit light if EM-ROW is also active). In one embodiment, the analog signals are Vdata (input): analog data to be sampled and which sets the gate voltage of the current driving transistor T1, Isense (output): when the read-out switch T3and switches T5and T6are closed and the emission switch T4is open, the current from T1may be flowing through the sense column line and may be measured outside the chip, and Vsense (output): when the read-out switch T3and switches T5and T6are closed and both emission switches are closed, the current from T1may flow through the display element (e.g., μLED) and the voltage level on the display element (e.g., μLED anode, minus voltage drop of T4and T5) may be measured from the sense column line. In accordance with embodiments, the pixel driver chip areas can include a variety of digital configurations, analog configurations, and combinations thereof.

Referring now toFIGS.9-10, schematic cross-sectional side view illustrations similar toFIG.3are provided where instead building a temporary RDL130for test routing, the test routing can be integrated into the diffused electrical connections170(FIG.9) or polycide electrical connections172(FIG.10). For example, the diffused electrical connections170can be provided by diffusing and/or implanting a dopant into the semiconductor substrate100. The diffused electrical connections170may tunnel in the semiconductor substrate100(e.g. silicon), possibly below active devices. The polycide electrical connections172(e.g. silicide on top of polysilicon) can be formed on top of the semiconductor substrate100.

The diffused electrical connections170or polycide electrical connections172may be used in place of the temporary RDL to provide test routing. Furthermore, diffused electrical connections170and polycide electrical connections172are compatible with DRIE etching used for singulation of the pixel driver chips. More specifically, DRIE etching can be used to etch through silicon, polysilicon, oxide, polycide, though not for metals. As such, singulation is not performed through metal routing layers, though the diffused electrical connections170and polycide electrical connections172may extend to a singulated sidewall of a pixel driver chip.

Still referring toFIGS.9-10, the diffused electrical connections170and polycide electrical connections172can additionally be connected with metal trace routings174, which can also be inside the perimeter seal rings128. In this manner, metal trace routings can still be used to provide long connections and connect to the diffused electrical connections170and polycide electrical connections172at localized singulation regions. The metal trace routings may optionally be connected with the device region, or not be connected to the device region of the pixel driver chip areas. In the illustrated embodiments, the diffused electrical connections170and polycide electrical connections172extend underneath the perimeter metal seal ring128to provide chip-to-chip connections for the test routing.

In the embodiments illustrated inFIGS.9-10the test pad area108is outside of the pixel driver chip areas106. Electrical connection to the test pads114can be made with vertical interconnects115formed of stacked vias122and optionally metal wiring layers120.

Referring now toFIG.11a schematic top view illustration is provided of a reticle area104including a plurality of pixel driver chip areas106serially connected with polycide or diffused test routing in accordance with an embodiment. As shown, the serial connections can reduce the number of test pads114needed. In an embodiment adjacent pixel driver chip areas106can be shorted with switches for high throughput analog testing. Once singulated along the dotted lines, the diffused electrical connections170or polycide electrical connections172can extend to one or more chip sidewalls180(formed by singulation).

FIG.12is a schematic top view illustration of a reticle area104including a plurality of pixel driver chip areas104connected with rows and columns of polycide or diffused test routing in accordance with an embodiment. In this configuration, individual pixel driver chip areas106can be tested. Furthermore, in this configuration, where polycide is used, a singulated pixel driver chip may include a floating polycide electrical connection172, indicated as trace182, may be present adjacent a sidewall180of the pixel driver chip.

FIG.13is a schematic top view illustration of a reticle area104including a plurality of pixel driver chip areas106connected with metal test routing and polycide bridges in accordance with an embodiment. In this configuration, metal trace (test) routings174can provide a bulk of the test routing, while the polycide electrical connection172areas can function as short local interconnects as polycide bridges184to provide a material that can be etched for singulation purposes. In this manner, the metal trace routings174do not extend to the chip sidewalls180, and instead polycide bridges184can extend to the chip sidewalls180.

In utilizing the various aspects of the embodiments, it would become apparent to one skilled in the art that combinations or variations of the above embodiments are possible for testing a pixel driver chip donor wafer. Although the embodiments have been described in language specific to structural features and/or methodological acts, it is to be understood that the appended claims are not necessarily limited to the specific features or acts described. The specific features and acts disclosed are instead to be understood as embodiments of the claims useful for illustration.