Interconnect structure and method for forming the same

A interconnect structure includes a first etch stop layer over a substrate, a dielectric layer over the first etch stop layer, a conductor in the dielectric layer, and a second etch stop layer over the dielectric layer. The dielectric layer contains carbon and has a top portion and a bottom portion. A difference of C content in the top portion and the bottom portion is less than 2 at %. An oxygen content in a surface of the conductor is less than about 1 at %.

TECHNICAL FIELD

The present invention relates to semiconductor devices, and particularly to copper interconnects and method for fabrication.

BACKGROUND

Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment, as examples. As technology has progressed, the demand for smaller semiconductor devices with improved performance has increased. As feature densities increase, widths of conductive lines and spacing between the conductive lines of back-end of line (BEOL) interconnect structures also need to be scaled smaller.

A move is being made away from traditional materials used in the past in semiconductor device designs, in order to meet these demands. To reduce an RC time delay, low dielectric constant (low-k) materials are being used as insulating materials, and there is a switch being made to the use of copper for interconnect materials, rather than aluminum. Advantages of using copper for semiconductor device interconnects include abilities to operate faster and manufacture thinner conductive lines because copper has lower resistivity and increased electromigration resistance compared to aluminum. Combining copper interconnects with low-k dielectric materials increases interconnect speed by reducing the RC time delay.

Copper interconnects are often formed using damascene processes rather than by direct etching. Damascene processes are typically either single or dual damascene, which includes forming openings by patterning and etching inter-metal dielectric (IMD) layers and filling the openings with copper. However, there are some challenges in the copper damascene structure, such as adhesion issues between the low-k dielectric material and the underlying layer. The adhesion issues may cause film cracking and/or peeling, therefore, result device package qualification failure.

DETAILED DESCRIPTION

With reference to FIGS.1and2-9, a method100and a semiconductor device200are collectively described below. The semiconductor device200illustrates an integrated circuit, or portion thereof, that can comprise memory cells and/or logic circuits. The semiconductor device200can include passive components such as resistors, capacitors, inductors, and/or fuses; and active components, such as P-channel field effect transistors (PFETs), N-channel field effect transistors (NFETs), metal-oxide-semiconductor field effect transistors (MOSFETs), complementary metal-oxide-semiconductor transistors (CMOS s), high voltage transistors, and/or high frequency transistors, other suitable components, and/or combinations thereof. It is understood that additional steps can be provided before, during, and/or after the method100, and some of the steps described below can be replaced or eliminated, for additional embodiments of the method. It is further understood that additional features can be added in the semiconductor device200, and some of the features described below can be replaced or eliminated, for additional embodiments of the semiconductor device200.

Referring toFIGS. 1 and 2, the method100begins at step102, wherein a first etch stop layer (ESL)220is formed over a substrate210. In the present embodiment, the substrate210is a semiconductor substrate comprising silicon. Alternatively, the substrate210comprises an elementary semiconductor including silicon and/or germanium in crystal; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations thereof. The alloy semiconductor substrate may have a gradient SiGe feature in which the Si and Ge composition change from one ratio at one location to another ratio at another location of the gradient SiGe feature. The alloy SiGe may be formed over a silicon substrate. The SiGe substrate may be strained. Furthermore, the semiconductor substrate may be a semiconductor on insulator (SOI). In some embodiments, the semiconductor substrate may include a doped epi layer. In other embodiments, the silicon substrate may include a multilayer compound semiconductor structure.

The substrate210may include various doped regions depending on design requirements (e.g., p-type wells or n-type wells). The doped regions may be doped with p-type dopants, such as boron or BF2; n-type dopants, such as phosphorus or arsenic; or a combination thereof. The doped regions may be formed directly in the substrate210, in a P-well structure, in an N-well structure, in a dual-well structure, or using a raised structure. The semiconductor device200may include a PFET device and/or an NFET device, and thus, the substrate210may include various doped regions configured for the PFET device and/or the NFET device.

The first etch stop layer220for controlling an end point during subsequent etching processes is deposited on the above-described substrate210. In some embodiments, the first etch stop layer220comprises elements of C, Si, N and H. In some embodiments, the first etch stop layer220is formed of silicon oxide, silicon nitride, silicon carbide, silicon oxynitride or combinations thereof. In some embodiments, the first etch stop layer220has a thickness of about 10 angstroms to about 1000 angstroms. In some embodiments, the first etch stop layer220is formed through any of a variety of deposition techniques, including low-pressure chemical vapor deposition (LPCVD), atmospheric-pressure chemical vapor deposition (APCVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), sputtering and other suitable deposition techniques. Alternatively, the first etch stop layer220is formed by a thermal process. In some embodiments, the first etch stop layer220has a thickness ranging between about 100 Angstroms and about 300 Angstroms.

Referring toFIGS. 1 and 3, the method100continues with step104in which an adhesion layer230is formed over the first etch stop layer220. In some embodiments, the adhesion layer230includes SiOx-containing material, SiCN-containing material, SiON-containing material, or combinations thereof. In some embodiments, the adhesion layer230is formed using LPCVD, APCVD, PECVD, PVD, or sputtering. Alternatively, the adhesion layer230is formed using a thermal process. In the present embodiment, the adhesion layer230is tetraethoxysilane (TEOS). In some embodiments, the adhesion layer230has a thickness ranging between about 100 Angstroms and about 300 Angstroms.

Referring toFIGS. 1 and 4, the method100continues with step106in which a dielectric layer240is formed over the adhesion layer230. The dielectric layer240may be a single layer or a multi-layered structure. In some embodiments, the dielectric layer240is formed using a CVD process, such as PECVD, LPCVD, or atomic-layer deposition (ALD). In some embodiments, the dielectric layer240comprises elements of Si, C, O, and H. In some embodiments, the dielectric layer240is a C-containing layer with C content greater than 10 at %. In alternative embodiments, the dielectric layer240is a C-containing layer with C content ranging between about 10 at % and about 13 at %. In some embodiments, the dielectric layer240has a thickness ranging between about 300 Angstroms and about 2500 Angstroms.

In some embodiments, the dielectric layer240is formed by PECVD. In some embodiments, the dielectric layer240use at least one precursor, such as tetramethylcyclotetrasiloxane (TMCTS), octamethylcyclotetrasiloxane (OMCTS), diethoxymethylsilane (DEMS), diethoxyldimethylsilane (DEDMS) or other related cyclic and non-cyclic silanes and siloxanes. In some embodiments, the precursor may be used in conjunction with an inert gas such as He or Ar and/or a reactant gas such as H2O, O2, or CO2. In some embodiments, the dielectric layer240is formed using a C-containing gas, an O-containing gas, and a H-containing gas with flow rates ranging between about 1700 sccm (standard cubic center per minute) and about 3000 sccm, about 700 sccm and about 1200 sccm, and about 20 sccm and about 300 sccm, respectively. In some embodiments, the dielectric layer240is formed using an RF power ranging between about 600 watts and about 1100 watts. In some embodiments, the dielectric layer240is formed at a temperature ranging between about 200° C. and about 320° C.

In some embodiments, the dielectric layer240is a low dielectric constant (low-k) layer having a dielectric constant of less than 3.0 and functions as an inter-metal dielectric (IMD) layer. In some embodiments, the dielectric layer240is a low-k layer having a dielectric constant ranging between about 2.5 and about 2.8. A wide variety of low-k materials may be employed in accordance with embodiments, for example, spin-on inorganic dielectrics, spin-on organic dielectrics, porous dielectric materials, organic polymer, organic silica glass, fused silica glass (FSG) (SiOF series material), hydrogen silsesquioxane (HSQ) series material, methyl silsesquioxane (MSQ) series material, or porous organic series material.

Referring toFIGS. 1 and 5, the method100continues with step108in which an opening250is formed in the dielectric layer240. In some embodiments, the opening250is formed through the dielectric layer240, the adhesion layer230, and the first etch stop layer220. In some embodiments, the opening250is a dual damascene opening including an upper trench section250aand a lower via-hole section250bto define a contact region. AlthoughFIG. 5illustrates a dual damascene opening in the dielectric layer240, the use of single damascene openings in the IMD layer is possible in some embodiments. In dual damascene techniques including a “via-first” patterning method or a “trench-first” patterning method, the upper trench section250aand the lower via-hole section250bmay be formed using a typical lithographic process with masking technologies and anisotropic etch operations (e.g., plasma etching or reactive ion etching). A bottom etch stop layer, a middle etch stop layer, a polish stop layer, or an anti-reflective coating (ARC) layer may be optionally deposited on or intermediately within the dielectric layer240, providing a clear indicator of an end point for a particular etching process.

Referring toFIGS. 1 and 6, the method100continues with step110in which a conductor260is formed in the opening250. In some embodiments, the conductor260is formed by a deposition process, e.g., electro-chemical plating (ECP). In some embodiments, the conductor260contains at least one main metal element, e.g., copper (Cu). In alternative embodiments, the conductor260further contains an additive metal element different from the main metal element, such as aluminum.

Still referring toFIG. 6, a barrier layer (not shown) may be deposited to line the sidewalls the openings250before forming the conductor260. In some embodiment, the barrier layer includes Ti, TiN, Ta, TaN, other proper material, or combinations thereof. A conductive seed layer (not shown) may be further formed over the barrier layer before forming the conductor260. In one embodiment, the conductive seed layer is a metal alloy layer containing at least a main metal element, e.g., copper (Cu). In at least one embodiment, the conductive seed layer is formed by using PVD, CVD, PECVD, LPCVD, or other deposition techniques. A chemical mechanical polishing (CMP) process may be performed after the formation of the conductor260to remove excess portions of the conductor260over the dielectric layer240, thus exposing the top surface of the dielectric layer240and achieving a planarized surface.

Referring toFIGS. 1 and 7, the method100continues with step112in which a treatment270is performed over the conductor260. In some embodiments, the treatment270reduces native oxide (e.g., CuOx) in a surface of the conductor260such that the element of oxygen in the surface of the conductor260is less than about 1 at %. In some embodiments, the treatment270is performed by remote plasma using NH3gas. In alternative embodiments, the treatment270is performed by remote plasma using NH3and N2gases, wherein a ratio of flow rates of N2to NH3is less than 1. In some embodiments, the treatment270is performed using NH3with a gas flow rate ranging between about 700 sccm and about 1000 sccm. In some embodiments, the treatment270is performed using an RF power ranging between about 700 watts and about 3000 watts. In some embodiments, the treatment270is performed at a temperature ranging between about 200° C. and about 400° C.

FIG. 8is an exemplary schematic of a remote control reactor300. The remote control reactor300comprises a first chamber310, a filter320, a shower head distributor (SHD)330, and a second chamber340. In some embodiments, an initial plasma350comprising radicals and charged ions is generated in the first chamber310, then radicals of the resultant plasma pass through the filter320and thereafter enter into the second chamber340after passing through the SHD330to form a remote plasma360in the second chamber340. In some embodiments, the charged ions in the initial plasma350do not pass through the filter320, therefore the charged ions do not enter into the second chamber340. In some embodiments, the substrate is positioned in the second chamber340and treated by the remote plasma360.

Still referring toFIG. 7, the treatment270is performed over the dielectric layer240as well to form a treated dielectric region240′ in an upper portion of the dielectric layer240. In some embodiments, the treated dielectric region240′ has a thickness ranging between about 10 Angstroms and about 50 Angstroms. In some embodiments, a thickness of the treated dielectric region240′ is about 1% to about 5% of the thickness of the dielectric layer240. Comparing with the direct plasma treatment, the treatment270using remote plasma results in less damage to the surface of the dielectric layer240because of free or less charged ions in the remote plasma, thereby resulting in less carbon loss in the treated dielectric region240′. In some embodiments, the treated dielectric region240′ comprises a C content substantially the same as the C content in the dielectric layer240. In alternative embodiment, the treated dielectric region240′ comprises a C content less than the C content in the dielectric layer240, while the difference of C contents in the treated dielectric region240′ and the dielectric layer240is less than 2 at %. In some embodiment, the treated dielectric region240′ comprises a C content not less than about 10 at %. In some embodiments, the treated dielectric region240′ has a dielectric constant ranging between about 2.5 and about 2.8. In some embodiments, the dielectric constant of the treated dielectric region240′ is substantially the same as the dielectric constant of the dielectric layer240. In alternative embodiments, a difference between the dielectric constants of the treated dielectric region240′ and the dielectric layer240is less than about 2%.

Referring toFIGS. 1 and 9, the method100continues with step114in which a second etch stop layer290is formed over the treated conductor260. Alternatively, the second etch stop layer290is formed over the treated conductor260and the treated dielectric region240′. The second etch stop layer290may control an end point during subsequent etching processes. The second etch stop layer290may be formed of silicon oxide, silicon nitride, silicon carbide, silicon oxynitride or combinations thereof. In some embodiments, the second etch stop layer290has a thickness of about 10 Angstroms to about 1000 Angstroms. In some embodiments, the second etch stop layer290may be formed through any of a variety of deposition techniques, including, LPCVD, APCVD, PECVD, PVD, and sputtering.

An adhesion value between the second etch stop layer290and the treated dielectric region240′ is improved by reduced carbon loss during the treatment270, as mentioned above. In some embodiments, an adhesion value between the second etch stop layer290and the treated dielectric region240′ is about 13 J/m2or greater. The adhesion value is higher than that formed using methods in which no remote plasma is applied to the dielectric layer240by about 20% or greater.

Still referring toFIG. 9, a capping layer280may be formed between the conductor260and the second etch stop layer290. In some embodiments, the capping layer280is formed before the deposition of the second etch stop layer290and functions as a diffusion barrier or adhesion promoter. In some embodiments, the capping layer280comprises cobalt or aluminum. In some embodiments, the capping layer280is selectively formed over the conductor260by ALD or PECVD.

In summary, the disclosed methods and integrated circuit devices result in improved device performance, including but not limited to, improved adhesion between the IMD layer, e.g., dielectric layer240, and a subsequently formed etch stop layer, e.g., second etch stop layer290, and thus peeling can be suppressed. Further, the method can improve package capabilities.

In one embodiment, a device comprises a substrate, a first etch stop layer over the substrate, a dielectric layer over the first etch stop layer, a conductor in the dielectric layer, and a second etch stop layer over the dielectric layer. The dielectric layer contains carbon and has a top portion and a bottom portion. A difference of C content within the top portion and the bottom portion is less than 2 at %. Oxygen content in a surface of the conductor is less than about 1 at %.

In another embodiment, a semiconductor device comprises a semiconductor substrate, a first etch stop layer over the semiconductor substrate, an adhesion layer over the first etch stop layer, a low-k dielectric layer comprising C, Si, O elements over the adhesion layer, a conductor in the dielectric layer, and a second etch stop layer over the conductor and the low-k dielectric layer. The low-k dielectric layer has an upper portion and a lower portion, an atomic percent of C in the upper portion is less than an atomic percent of C in the lower portion, and a difference of C content in the upper portion and the lower portion is less than about 2 at %. An oxygen content in a surface of the conductor is less than about 1 at %.

In still another embodiment, a method comprises forming a first etch stop layer over a substrate, forming a low-k dielectric layer comprising C over the first etch stop layer, forming an opening in the low-k dielectric layer, filling the opening with a conductive layer, performing a remote plasma treatment on the low-k dielectric layer and the conductive layer, and forming a second etch stop layer over the treated conductive layer and the treated low-k dielectric layer.

Although the present invention has been described in its preferred embodiments, it is not intended to limit the invention to the precise embodiments disclosed herein. Those skilled in this technology can still make various alterations and modifications without departing from the scope and spirit of this invention. Therefore, the scope of the present invention shall be defined and protected by the following claims and their equivalents.