Demodulator system and method

A demodulator system and method is disclosed. In an embodiment, the demodulator system can include a Coordinate Rotation Digital Computer (CORDIC) mixer to mix a first signal substantially to baseband using a first input frequency and to mix a second signal substantially to baseband using a second input frequency. In another embodiment, the demodulator system can include a phase detector to receive a pilot signal and to generate a control signal to adjust a decimation rate based on the pilot signal. In another embodiment, the demodulator system can include a symbol decoder to determine a symbol from a phase signal.

FIELD OF THE DISCLOSURE

The present disclosure is generally related to demodulator systems and methods.

BACKGROUND

Demodulator systems can be used for applications such as television, radio, and satellite communications. Audio data can be encoded in a modulated signal using a variety of modulation techniques. Some methods of audio data encoding require the use of a phase lock loop to extract the audio data from encoded signals. Establishing a phase lock can enable audio data to be extracted from some data signals by determining a phase difference between sequential samples of the data signal. However, phase lock loop circuits can be costly or unreliable, and noisy signals can interfere with recovery of phase differences encoded in an audio signal

Therefore, there is a need for an improved demodulator system and method.

DETAILED DESCRIPTION OF THE DRAWINGS

In an embodiment, a demodulator system is disclosed that includes an analog-to-digital converter (ADC) configured to sample a modulated signal and to output a digital signal. The demodulator system includes a Coordinate Rotation Digital Computer (CORDIC) mixer coupled to an output of the ADC, the CORDIC mixer to generate an Inphase (I) signal and a Quadrature (Q) signal based on the digital signal output by the ADC and further based on an input frequency. The demodulator system also includes a filter path to process the I signal and the Q signal generated at the CORDIC mixer and a demodulation stage to demodulate an output of the filter path, where the demodulation stage includes a CORDIC demodulator.

In another embodiment, a demodulator system is disclosed that includes a Coordinate Rotation Digital Computer (CORDIC) mixer to receive a first input signal modulated using a first modulation mode. The CORDIC mixer is configured to generate a first Inphase (I) signal and a first Quadrature (Q) signal by mixing the first input signal substantially to baseband using a first input frequency. The CORDIC mixer is further configured to receive a second input signal modulated using a second modulation mode. The CORDIC mixer is also configured to generate a second I signal and a second Q signal by mixing the second input signal substantially to baseband using a second input frequency. The second demodulator system also includes a filter path to process an output of the CORDIC mixer and a demodulation stage to demodulate an output of the filter path, where the demodulation stage includes a CORDIC demodulator.

In another embodiment, a demodulator system is disclosed that includes a Coordinate Rotation Digital Computer (CORDIC) mixer to generate an Inphase (I) signal and a Quadrature (Q) signal based on a modulated input signal and an input frequency. The demodulator system includes a decimator to perform decimation of the I signal and the Q signal at an adjustable decimation rate and a phase detector to receive a pilot signal. The phase detector includes decimation rate logic to generate a control signal to adjust the decimation rate based on the pilot signal. An oversample rate of the pilot signal is not less than approximately two and not more than approximately sixty-four. The demodulator system also includes a demodulation stage to demodulate a filtered output of the decimator, where the demodulation stage includes a CORDIC demodulator.

In another embodiment, a demodulator system is disclosed that includes a Coordinate Rotation Digital Computer (CORDIC) mixer to generate an Inphase (I) signal and a Quadrature (Q) signal. The demodulator system also includes a decimator coupled to the CORDIC mixer to adjust a sample rate of at least one of the I signal and the Q signal. The demodulator system includes a filter path coupled to the decimator to process an output of the decimator. The demodulator system further includes a demodulation stage to demodulate an output of the filter path, where the demodulation stage includes a CORDIC demodulator. The demodulator system also includes a symbol decoder to receive a phase signal from the CORDIC demodulator. The symbol decoder includes symbol recognition logic to adjust a sample of the phase signal by an offset value and to map the adjusted sample to a nearest predetermined phase value of a plurality of predetermined phase values. The symbol recognition logic is also configured to determine a symbol using a difference between the nearest predetermined phase value and a prior nearest predetermined phase value. The offset value at least partially compensates for a phase drift generated at the CORDIC mixer.

In another embodiment, a demodulation method is disclosed. The method includes receiving a modulated signal and mixing the audio signal substantially to baseband at a Coordinate Rotation Digital Computer (CORDIC) mixer having multiple pipelined mixing stages. The method also includes decimating an output of the CORDIC mixer at a decimator having an adjustable decimation rate. The method further includes demodulating a filtered output of the decimator with a CORDIC demodulator.

Referring toFIG. 1, a particular illustrative embodiment of a digital demodulator system is depicted and generally designated100. The system100includes an analog-to-digital converter (ADC)102to sample a modulated input signal101received at the demodulator system100and to generate a corresponding digital signal output103. The output103of the ADC102is coupled to an automatic gain controller (AGC)104, a first CORDIC mixer106and a second CORDIC mixer124. A first channel path includes a first decimator114coupled to receive outputs105and107of the first CORDIC mixer106and providing outputs109and111to a channel filter116. A second channel path includes a second decimator126coupled to receive outputs117and119of the second CORDIC mixer124and providing outputs121and123to the channel filter116.

The channel filter116is coupled to a CORDIC demodulator118. Outputs152,154,156and158of the CORDIC demodulator118are received at a composite decoder120. A deemphasis and stereo matrix122receives an output of the composite decoder120and provides left and right audio signals. An audio standard detector (ASD)148is coupled to the first channel output113of the channel filter116and to the second channel output125of the channel filter116.

The first channel path includes a pilot filter128coupled to the output113and the output115of the channel filter116. The first channel path is further coupled to a phase output152of the CORDIC demodulator118. A phase detector136is coupled to an output129of the pilot filter128and provides an output131to the first decimator114. A symbol decoder142is coupled to phase output152of the CORDIC demodulator118and provides an output to the composite decoder120.

In a specific embodiment, the ADC102can be an eight-bit pipeline ADC followed by a 3-bit flash ADC. The ADC102can sample the input signal101at 24.576 MHz and can have a signal-to-noise ratio (SNR) better than 54 dB. The ADC102can include a synchronization circuit to prevent metastable conditions.

In a specific embodiment, the AGC104can provide a gain signal to a variable gain amplifier (not shown) that provides the input signal101to the ADC102. The gain signal can enable the variable gain amplifier to adjust an output to maintain the input signal101at about 80% of full scale. Operation of the AGC104can be modified when the ASD148determines that the input signal101includes an amplitude modulated (AM) signal.

In a particular embodiment, the demodulator system100supports at least twelve audio standards including A2, Near Instantaneous Companded Audio Multiplex (NICAM), Broadcast Television Systems Committee (BTSC), and Electronic Industries Association of Japan (EIAJ). In an embodiment, the ASD148can determine a new audio standard of the input signal101when the input signal101changes. In a specific embodiment, when the ASD148receives notice that the input signal101has changed, the ASD148can set the decimation rate of the first decimator114and the second decimator126to a predetermined rate and can set the channel filter116to pass a predetermined bandwidth. The ASD148can provide various frequencies108to the first CORDIC mixer106and various frequencies150to the second CORDIC mixer124to mix the input signal101to baseband. The ASD148can detect an energy level associated with each frequency to determine the most likely standard received. When the ASD148has determined the standard of the new input signal101, the ASD148can select the input frequency108provided to the first CORDIC mixer106and the second frequency150provided to the second CORDIC mixer124according to the determined standard. The ASD can also determine initial decimation rates of the first decimator114and the second decimator126, as well as coefficient values for filters within the channel filter116.

In an embodiment, the first CORDIC mixer106can generate a first Inphase signal (I1)105and a first Quadrature signal (Q1)107for the first channel by mixing the signal103received from the ADC102substantially to baseband using an input frequency108. In a particular embodiment, the first CORDIC mixer106can have multiple pipelined mixing stages, including a first mixing stage110and a second mixing stage112. In a particular embodiment, the first CORDIC mixer106can perform a predetermined number of CORDIC iterations for each sample of the signal103. In another particular embodiment, the first CORDIC mixer106can achieve a predetermined mixing accuracy without using an oscillator or a multiplication function.

In an embodiment, the first decimator114can perform decimation on each of the I1signal105and the Q1signal107output by the first CORDIC mixer106at an adjustable decimation rate to produce a second Inphase signal (I1′)109and a second Quadrature signal (Q1′)111for the first channel. The decimation rate is expressed as a sample rate at a decimator input divided by the output sample rate. In a particular embodiment, the first decimator114can include a first independent decimation circuit (not shown) to decimate the I1signal105and a second independent decimation circuit (not shown) to decimate the Q1signal107. In a particular embodiment, the first decimator114can be a variable rate, fractional decimator. The first decimator114can be responsive to a control signal131from the phase detector136to adjust the decimation rate. In a specific embodiment, the first decimator114can adjust the decimation rate while maintaining a continuous output of the I1′ signal109and the Q1′ signal111.

In an embodiment, the channel filter116can include multiple filtering components (not shown) to filter a high frequency image that is produced in the I1signal105and the Q1signal107at the first CORDIC mixer106. The channel filter116can also filter a high frequency image that is produced in a first Inphase signal (I2)117and a first Quadrature signal (Q2)119for the second channel at the second CORDIC mixer124. The channel filter116can also reject out of band noise in the I1′ signal109and the Q1′ signal111received from the first decimator114and in a second Inphase signal (I2′)121and a second Quadrature signal (Q2′)123for the second channel received from the second decimator126. In a specific embodiment, the channel filter116can include 26-tap finite impulse response (FIR) filters for the first and second channel path.

In a particular embodiment, the pilot filter128can include a narrow bandpass filter (BPF)134to recover an oversampled pilot signal129and to provide the pilot signal129to the phase detector136. The pilot filter can selectively recover the pilot signal129from either a third Inphase signal (I1″)113and a third Quadrature signal (Q1″)115for the first channel, or from the phase output152of the CORDIC demodulator118. In a particular embodiment, the first channel processes frequency modulation (FM) data such as BTSC data, and the pilot filter128can receive the phase signal152at the BPF134to generate the pilot signal129.

In another particular embodiment, the first channel processes Differential Quadrature Phase-Shift Keying (DQPSK) modulated data, such as NICAM digital data, and the pilot filter128can receive the I1″ signal113and the Q1″ signal115at an absolute value circuit (ABS)130. The pilot filter128can combine the absolute values corresponding to each of the I1″ signal113and the Q1″ signal115at a summer132. The BPF134can filter an output of the summer132to generate the pilot signal129. The recovered pilot signal129can have a pilot signal frequency approximately equal to a NICAM symbol rate of 364 kHz.

In a particular embodiment, the phase detector136can receive the pilot signal129and provide a control signal131to the first decimator114to adjust the decimation rate. Generally, the pilot signal can be oversampled at any oversampling rate. In a particular embodiment, the oversampling rate of the pilot signal can be not less than approximately two and not more than approximately sixty-four. In a specific embodiment, the oversampling rate can be approximately four for NICAM data. In another specific embodiment, the oversampling rate can be approximately thirty-two for BTSC data. In a particular embodiment, the phase detector136can include sample logic138to sample the pilot signal129at a rate approximately equal to an integer multiple of a frequency of the pilot signal129. In a particular embodiment, the integer multiple can be determined by the ASD148to have a value of one. In another specific embodiment, the integer multiple can be two, and a sign of every other sample can be inverted. In another specific embodiment, the sample logic138can also sample the pilot signal at one or more quarter-wavelengths of the pilot signal to determine a strength of the pilot signal.

In an embodiment, the phase detector136can include decimation rate logic140to generate the control signal131based on the samples of the pilot signal. The control signal131can be used to achieve and maintain a phase lock to the pilot signal129for processing DQPSK and BTSC data. In some embodiments, the control signal131can increase the decimation rate when a sample of the pilot signal129is negative and can decrease the decimation rate when a sample of the pilot signal129is positive.

In a particular embodiment, the phase detector136can be a second-order phase detector. The phase detector136can compare samples of the pilot signal129to zero. The decimation rate logic140can also determine a slope by comparing a sample of the pilot signal129to a previous sample of the pilot signal129. In a specific embodiment, the sample value and the slope value can be independently weighted and used to determine an error value. The error value can be determined using techniques such as a moving average or leaky bucket integration (LBI) of all or some prior weighted sample values and weighted slope values, and the error value can be compared to a predetermined threshold value.

In an particular embodiment, the second CORDIC mixer124can generate the first Inphase signal (I2)117and the first Quadrature signal (Q2)119for the second channel by mixing the signal103received from the ADC102substantially to baseband using the input frequency150. The second CORDIC mixer124can also include multiple pipelined mixing stages (not shown). In a particular embodiment, the second CORDIC mixer124can perform a predetermined number of CORDIC iterations for each received sample of the signal103. The CORDIC mixer can thus attain a predetermined mixing accuracy without using an oscillator or a multiplication function.

In an illustrative embodiment, the second decimator126can perform decimation on each of the I2signal117and Q2signal119at an adjustable decimation rate to produce the second Inphase signal (I2′)121and the second Quadrature signal (Q2′)123for the second channel. In a particular embodiment, the second decimator126can include a first independent decimation circuit (not shown) to decimate the I2signal117and a second independent decimation circuit (not shown) to decimate the Q2signal119. In a particular illustrative embodiment, the second decimator126can be a variable rate, fractional decimator. In an embodiment, the second channel does not require phase lock to process received data, and therefore the second decimator126is not responsive to the control signal131. However, the second decimator126can be responsive to the initial decimation rate corresponding to an audio standard that is determined by the ASD148.

Broadly, the CORDIC demodulator118transforms Inphase and Quadrature data into instantaneous magnitude and instantaneous phase. The instantaneous magnitude can represent amplitude modulation (AM) content. The instantaneous phase, when differentiated, can represent instantaneous frequency of frequency modulation (FM) content. In an embodiment, the CORDIC demodulator118can include a single CORDIC core (not shown) that is shared between the first channel, the second channel, and the composite decoder120. In another embodiment, the CORDIC demodulator118can include multiple CORDIC cores (not shown) to avoid or reduce arbitration between the first and second channels and the composite decoder120.

In a particular embodiment, the CORDIC demodulator118can transform the I1″ signal113and the Q1″ signal115from the first channel into an instantaneous phase value. The CORDIC demodulator can represent a phase differential of samples of the I1″ signal113and the Q1″ signal115at the phase signal152. The phase signal152can be a first-order approximation to a phase differential that indicates a difference between a current sample of the I1″ signal113and the Q1″ signal115and the prior sample of the I1″ signal113and the Q1″ signal115.

In a particular embodiment, the CORDIC demodulator118can translate the I2″ signal125and the Q2″ signal127from the second channel into an instantaneous phase value and an instantaneous magnitude value. The CORDIC demodulator118can represent a phase differential of samples of the I2″ signal125and the Q2″ signal127at the phase signal154. The phase signal154can be a first-order approximation to a phase differential that indicates a difference between a current sample of the I2″ signal125and the Q2″ signal127and the prior sample of the I2″ signal125and the Q2″ signal127. The instantaneous magnitude value can be output to the composite decoder120via the signal156.

In an illustrative embodiment, the CORDIC demodulator118can also receive an I signal160and a Q signal162from the composite decoder120. The CORDIC demodulator118can generate and output a signal158that represents a phase differential corresponding to the I signal160and the Q signal162.

In an embodiment, the composite decoder120separates different audio channels transmitted across one or more carriers, such as SUM and DIFFERENCE signals of EIAJ, or Second Audio Program (SAP) signals of BTSC. The composite decoder120can include multiple filters (not shown) that can be shared between some or all of the audio standards supported by the demodulator system100. In an embodiment, the composite decoder120can perform AM demodulation for double side band transmissions or suppressed carrier transmissions. In an embodiment, the composite decoder120can initiate a second round of FM demodulation at the CORDIC demodulator118via the I output signal160and the Q output signal162. In another embodiment, the composite encoder120can detect the presence of SAP in a BTSC input signal. In another embodiment, the composite encoder120can identify a pilot signal in an A2 input signal to determine if the A2 data includes Mono, Stereo, or Dual Channel audio modes.

In an embodiment, the symbol decoder142can receive the phase signal152. The symbol decoder142can include symbol recognition logic144to adjust a sample of the phase signal152by an offset value and to map the adjusted sample to a nearest predetermined phase value of a plurality of phase values. The symbol recognition logic144can determine a symbol using a difference between the nearest predetermined phase value and a prior nearest predetermined phase value. The offset value can be computed to at least partially compensate for a phase drift that is introduced to the I1signal105and the Q1signal107by an imperfect frequency match at the first CORDIC mixer106. In a particular embodiment, a phase accumulator146can store the offset value. The phase accumulator146can be updated by a detected error of each sample of the phase signal152.

In a particular embodiment, the symbol decoder142can also include logic (not shown) to translate the determined symbol to audio data for input to the composite decoder120. In a particular illustrative embodiment, the symbol decoder142can receive phase data corresponding to a NICAM signal in the phase signal152. The symbol decoder142can determine a NICAM symbol based at least partially on a phase difference between consecutive phase values. The symbol decoder142can translate the NICAM symbol to corresponding bit pairs, generate a lock to a NICAM frame sequence in the resulting bit sequence, and provide the NICAM A and B data to the composite decoder120.

In a particular embodiment, the deemphasis and stereo matrix122can receive multiple signals from the composite decoder120and apply an appropriate deemphasis to the signal. In an embodiment, the deemphasis and stereo matrix122can use unique deemphasis filter coefficients for each supported audio standard to enable a normalized audio output level across different standards with different system gains.

Referring toFIG. 2, a particular illustrative embodiment of a demodulator system is depicted and generally designated200. The system200includes a CORDIC mixer201that receives a modulated signal202and an input frequency204. The CORDIC mixer201can use the input frequency204to mix the modulated signal202substantially to baseband using multiple CORDIC iterations performed by multiple pipelined mixing stages208and210. The CORDIC mixer201provides an Inphase (I) signal236, a Quadrature (Q) signal234, and a Phase signal232.

In a particular embodiment, all signals202received at the demodulator system200may be mixed at the CORDIC mixer201, independent of the modulation mode of the signal202. Thus, CORDIC mixer201can be configured to receive a first signal having a first modulation mode and a second signal having a second modulation mode. Generally, the first modulation mode and the second modulation mode can be any known modulation mode. In a particular embodiment, the first modulation mode can be a first one of amplitude modulation (AM), frequency modulation (FM), and differential quadrature phase shift key (DQPSK) modulation, and the second modulation mode can be a different one of AM, FM, and DQPSK modulation. In a particular embodiment, a first frequency can be received to mix the first signal substantially to baseband, and a second frequency can be received to mix the second signal substantially to baseband.

In a particular embodiment, the modulated signal202can be received from an analog-to-digital converter (ADC), such as the ADC102ofFIG. 1. The input frequency204can be determined by an Audio Standard Detector (ASD), such as the ASD148ofFIG. 1. The I signal236and Q signal234can be coupled to a demodulator, such as the CORDIC demodulator118ofFIG. 1, via a filter path, such as the channel filter116ofFIG. 1.

In an embodiment, the CORDIC mixer201can have input logic206to process the modulated signal202and the input frequency204and to output an initial I signal254, an initial Q signal203, and an initial Phase signal205to a first mixing stage208. The first mixing stage208can include multiplexer logic212coupled to a first CORDIC element214. The first CORDIC element214is configured to perform a CORDIC iteration on input data including an I signal207, a Q signal209, and a Phase signal211. The first mixing stage208can also have a second CORDIC element216to perform another CORDIC iteration on an I signal213, a Q signal215, and a Phase signal217output by the first CORDIC element214. A pipeline register218can store values of an I signal219, a Q signal221, and a Phase signal223output by the second CORDIC element216. “Pipeline register” as used herein can be a register, one or more flipflops, any other device or component that can store a data value, or any combination thereof.

In an embodiment, the multiplexer logic212can selectively provide the I signal254, the Q signal203, and the Phase signal205, or the I signal225, the Q signal227, and the Phase signal229to the first CORDIC element214of the first mixing stage208. In a particular embodiment, when a new sample of the modulated signal202is received, the multiplexer logic212can send the I signal254, the Q signal203, and the Phase signal205from the input logic206to the first mixing stage208. When a new sample of the modulated signal202is not received, the multiplexer logic212can select the I signal225, the Q signal227and the Phase signal229as the input of the first mixing stage208for further CORDIC iterations.

In an embodiment, a second mixing stage210can have multiplexer logic220coupled to a first CORDIC element222. The first CORDIC element is configured to perform a CORDIC iteration on an I signal237, a Q signal239, and a Phase signal241. The second mixing stage210can also have a second CORDIC element224to perform another CORDIC iteration on an I signal243, a Q signal245, and a Phase signal247output by the first CORDIC element222. A pipeline register226can store values of an I signal249, a Q signal251, and a Phase signal253that are output by the second CORDIC element224.

In an embodiment, the multiplexer logic220can selectively provide the first CORDIC element222with either the I signal225, the Q signal227, and the Phase signal229from the first mixing stage208, or with the I signal236, the Q signal234, and the Phase signal232from the pipeline register226. In a particular embodiment, when a new sample of the modulated signal202is received, the multiplexer logic220can send the I signal225, the Q signal227, and the Phase signal229from the first mixing stage208to the second mixing stage210. When a new sample of the modulated signal202is not received, the multiplexer logic220can select the I signal236, the Q signal234, and the Phase signal232as the input to the first CORDIC element222for further CORDIC iterations.

In a particular embodiment, each CORDIC element214,216,222, and224performs a single CORDIC iteration per set of the I, Q, and Phase signals corresponding to a single sample of the modulated signal202received at the CORDIC element214,216,222, and224. In a specific embodiment, a CORDIC iteration can include receiving data corresponding to an I value and a Q value, generating a new I value by shifting the received Q value and adding or subtracting the received I value, and generate a new Q value by shifting the received I value and adding or subtracting the received Q value. The received I value and Q value can be shifted by a number of bits determined by the CORDIC iteration number. In a particular embodiment, the I value and the Q value can be shifted one bit on a first CORDIC iteration for an input signal, and shifted five bits on a fifth CORDIC iteration for the input signal. A phase value can be generated by adding a received phase value to a phase constant that corresponds to the CORDIC iteration number.

In a particular embodiment, each of the first mixing stage208and the second mixing stage210can perform at least four CORDIC iterations per sample of the modulated signal202. In a particular embodiment, each of the first mixing stage208and the second mixing stage210can perform two “processing loops” for each sample of the modulated signal202. A “processing loop” as used herein is composed of a number of consecutive CORDIC iterations that are serially performed by a mixing stage208or210, where each CORDIC element of the mixing stage performs a single CORDIC iteration per processing loop.

In a particular embodiment, the first mixing stage208performs a first processing loop of two CORDIC iterations on the I signal254, the Q signal203, and the Phase signal205corresponding to a sample of the modulated signal202. The first processing loop is followed by a second processing loop of two CORDIC iterations using the I signal225, the Q signal227, and the Phase signal229generated by the previous processing loop. The second mixing stage210receives the I signal225, the Q signal227, and the Phase signal229generated by the second processing loop of the first mixing stage208and performs a third processing loop of two CORDIC iterations, followed by a fourth processing loop of two CORDIC iterations on the I signal236, the Q signal234, and the Phase signal232generated by the third processing loop. Thus, each sample of the modulated signal202can be processed by a total of eight CORDIC iterations.

Referring toFIG. 3, a particular illustrative embodiment of a digital audio processing system is depicted and generally designated300. The system300receives samples of a phase signal input302. The phase signal302is received at symbol recognition logic304. The symbol recognition logic304includes sample adjustment logic308to provide an adjusted sample output322by adjusting a sample of the phase signal302using an offset value328representing a phase drift. The adjusted sample322is received at an error detector310. The error detector310can map the adjusted sample322to a nearest predetermined phase value of a plurality of predetermined phase values. The error detector310can output an error value324based on a difference between the adjusted sample and the nearest predetermined phase value.

An adjusted sample output320of the sample adjustment logic308is received at a symbol slicer316. The symbol slicer316determines a symbol using a difference between the nearest predetermined phase value corresponding to one adjusted sample of the sample output320and a prior nearest predetermined phase value corresponding to the preceding adjusted sample of the sample output320. The symbol determined by the symbol slicer316is indicated via an output306.

The error detector310can provide an output324to error processing logic312to update the offset value328that is received at the sample adjustment logic308. The output324can be based on a difference between the adjusted sample322and the nearest predetermined phase value corresponding to the adjusted sample322. In a specific embodiment, the error processing logic312can filter the output324of the error detector310using a low-pass filter (LPF), integrate an output of the LPF at an integrator, and output a weighted average of the output of the LPF and the output of the integrator. An output326of the error processing logic312updates a value stored at a phase accumulator314. The phase accumulator314accumulates output values received from the error processing logic312, wraps the resulting offset value at 2*PI and provides the offset value328to the sample adjustment logic308.

In a particular embodiment, the input signal302to the system300can include NICAM phase data. The symbol recognition logic304can adjust each sample of the input signal302by the offset value328received from the phase accumulator314that represents a phase drift. In a particular embodiment, the offset value can compensate for a nearly constant phase drift that can be introduced by an imperfect mixing of a received signal to baseband. The symbol slicer316can receive a first adjusted sample N−1 and determine a nearest predetermined phase value to the first adjusted sample N−1 from a plurality of predetermined phase values that can include 0 degrees, 90 degrees, 180 degrees, and 270 degrees. The symbol slicer316can receive a next adjusted sample N and determine a symbol from a predetermined set of symbols based on a phase difference between the nearest predetermined phase value for N−1 and the adjusted phase value of N. In a particular embodiment, the input signal includes NICAM phase data and the predetermined set of symbols indicates a phase difference of 0 degrees, 90 degrees, 180 degrees, or 270 degrees between the sample N and the prior sample N−1.

In a particular embodiment, the phase signal302can be received from a demodulation stage, such as the CORDIC demodulator118ofFIG. 1, which in turn can receive an input from a CORDIC mixer, such as the CORDIC mixer106ofFIG. 1, via a decimator, such as the decimator114ofFIG. 1, and via a filter path such as the channel filter116ofFIG. 1. The output306can provide an indication of the symbol to logic that recovers a data signal and provides the data signal to a composite decoder, such as the composite decoder120ofFIG. 1.

Referring toFIG. 4, a graphical diagram depicting a particular illustrative embodiment of an operation of a digital audio processing system is shown and generally designated400. An illustrative signal402is received and sampled at a substantially predetermined sampling rate. In the particular illustrative embodiment ofFIG. 4, the sample rate is approximately four times the frequency of the signal402. Samples406,408,410,412and414indicate sample values of the signal402. The value of the signal402at sample406is approximately zero, and when phase lock to the signal402is acquired the value of the sample414will also equal zero, illustrated by phase lock sample416. However, as depicted in the illustrative embodiment ofFIG. 4, sample414is less than zero, indicating that the signal402is being sampled at too fast of a sample rate. Phase lock will be achieved when the sample rate is reduced so that every fourth sample, such as sample406and sample414, has a zero value.

Referring toFIG. 5, a graphical diagram depicting a particular illustrative embodiment of an operation of a digital audio processing system is shown and generally designated500. Samples520,522,524,526and528of a signal518demonstrate that the signal518is sampled at too slow of a sample rate. In particular, sample520and sample528will both have a zero value when phase lock is acquired and maintained. However, sample528is greater than zero, indicating that the sample rate should be increased until sample528coincides with the illustrated phase lock sample530.

Referring toFIG. 6, a graphical diagram depicting a particular illustrative embodiment of an operation of a digital audio processing system is shown and generally designated600. A set of predetermined phase values602,604,606and608are indicated at phase values of 0 degrees, 90 degrees, 180 degrees, and 270 degrees, respectively. A first phase boundary614and a second phase boundary616together bisect each quadrant and graphically indicate which of the predetermined phase values602,604,606and608is nearest to a received phase value. A vector610depicts a received phase value having angle620. Because the endpoint of the phase value vector610is less than the phase boundary614and greater than the phase boundary616, the nearest predetermined phase value to vector610is the predetermined phase value602at 0 degrees. Likewise, a received phase value with an endpoint greater than the first phase boundary614and the second phase boundary616can be mapped to the predetermined phase value604at 90 degrees, a received phase value with an endpoint greater than the first phase boundary614and less than the second phase boundary616can be mapped to the predetermined phase value606at 180 degrees, and a received phase value that is less than the first phase boundary614and the second phase boundary616can be mapped to the predetermined phase value608at 270 degrees. An error vector618graphically depicts the error of the vector610as an offset from the nearest predetermined phase value602.

Referring toFIG. 7, a flowchart of a particular illustrative embodiment of a demodulator method is depicted. The method begins with receiving a modulated signal, at700. The modulated signal is mixed substantially to baseband at a Coordinate Rotation Digital Computer (CORDIC) mixer having multiple pipelined mixing stages, at702. An output of the CORDIC mixer is decimated at a decimator having an adjustable decimation rate, at704. In a particular embodiment, a signal output by the decimator has a sampling frequency approximately equal to a pilot frequency multiplied by an oversample factor. The oversample factor can be an integer not less than two and not more than sixty-four. A filtered output of the decimator is demodulated with a CORDIC demodulator, at706.

In a particular embodiment, a pilot signal is sampled at a phase detector, at708. In an embodiment, the pilot signal can be oversampled at an oversample factor N that can vary with the modulated signal type. In a specific embodiment, the modulated signal includes a NICAM signal and the pilot frequency is approximately 364 kHz. The NICAM pilot signal can be recovered from the filtered output of the decimator with an oversample factor of four. In another specific embodiment, the modulated signal includes a BTSC signal and the pilot frequency is approximately 15.734 kHz. The BTSC pilot signal can be recovered from an output of the CORDIC demodulator with an oversample factor of thirty-two.

In a particular embodiment, a sample of the pilot signal is compared to zero, at710. In a particular embodiment, the sample can be compared to zero every N samples of the pilot signal, where N is the oversample factor of the pilot signal. In another particular embodiment, an Nth sample is subtracted from the previous Nth sample to find a slope of the Nth sample over time, at712.

In a particular embodiment, the decimation rate is adjusted based on the comparison of the sample to zero and based on the slope, at714. The decimation rate can be decreased based on the sample of the pilot signal having a positive value, a positive slope, or an error value computed from both the value and slope of the sample exceeding a positive threshold. The decimation rate can be increased based on the sample of the pilot signal having a negative value, a negative slope, or an error value computed from both the value and slope of the sample being more negative than a negative threshold. In an illustrative embodiment, the decimation rate can be adjusted based on the samples of the pilot signal to achieve and maintain a phase lock to the pilot signal.

In a particular embodiment, a phase value output is adjusted by an offset value, at716. The phase value can be output by the CORDIC demodulator, and the offset value can be based on a detected error of a prior phase value output by the CORDIC demodulator. The adjusted phase value is mapped to a nearest predetermined phase value of a plurality of predetermined phase values, at718. A symbol corresponding to a difference between the nearest predetermined phase value and a prior nearest predetermined phase value is determined, at720. The method terminates at722.

While specific systems and components of systems have been shown, it should be understood that many alternatives are available for such systems and components. In a particular illustrative embodiment, for example, a demodulator system may include hardware, software, firmware, or any combination thereof to perform functions and methods of operation as described. It should be understood that particular embodiments may be practiced solely by a processor executing processor instructions and accessing a processor readable memory, or in combination with hardware, firmware, software, or any combination thereof.