Trench field electrode termination structure for transistor devices

A semiconductor device includes: a trench formed in a surface of a semiconductor substrate and extending lengthwise in a direction parallel to the surface; a body region adjoining the trench; a source region adjoining the trench above the body region; a drift region adjoining the trench below the body region; a field electrode in a lower part of the trench and separated from the substrate; and a gate electrode in an upper part of the trench and separated from the substrate and the field electrode. A first section of the field electrode is buried below the gate electrode in the trench. A second section of the field electrode transitions upward from the first section in a direction toward the surface. The separation between the second section and the gate electrode is greater than or equal to the separation between the first section and the gate electrode.

BACKGROUND

Charge-balanced trench field-plate MOSFETs (metal-oxide-semiconductor field-effect transistors) are commonly used in DC-DC buck converters to step down the voltage from input to output. These devices can achieve the desired breakdown voltage rating with higher drift region doping due to a charge balance mechanism. As a result, these devices offer low on-resistance (Rdson) and gate charge (Qgd, Qg); thereby reducing conduction and switching losses, and enabling an improvement in overall system efficiency.

The edge termination design, however, requires careful attention and should be designed in a way that can achieve a similar extent of charge balance in the edge termination as in the active cells. Often times the edge termination becomes the limiting part of the design and device performance may need to be reduced to improve termination robustness.

The buried field electrode in the edge termination region should have a low resistance electrical connection to the desired potential, for example, source or gate potential, for effective 2-dimensional charge coupling in the device to achieve optimal performance. The field electrode resistance also determines how fast the MOSFET cells can transition from on-state to off-state and vice-versa, which can greatly influence the dynamic behavior of the device during switching. As switching frequencies for these applications continue to increase, dead-time requirements become more stringent and the underlying MOSFET devices must switch on and off very quickly, making it desirable to have a low resistance connection to the field electrode.

However, forming a good ohmic connection to the buried field electrode introduces processing complexities such as accessing the field electrode beneath the gate electrode in the same trench and making the metallic connection, for example, to the bulk of the source metal.

Thus, there is a need for an improved trench field electrode termination structure for transistor devices and methods of manufacturing thereof.

SUMMARY

According to an embodiment of a semiconductor device, the semiconductor device comprises: a trench formed in a first main surface of a semiconductor substrate and extending lengthwise in a direction parallel to the first main surface; a body region of a second conductivity type adjoining the trench; a source region of a first conductivity type adjoining the trench above the body region; a drift region of the first conductivity type adjoining the trench below the body region; a field electrode disposed in a lower part of the trench and separated from the semiconductor substrate; and a gate electrode disposed in an upper part of the trench and separated from the semiconductor substrate and the field electrode, wherein a first section of the field electrode is buried below the gate electrode in the trench, wherein a second section of the field electrode transitions upward from the first section in a direction toward the first main surface, wherein the separation between the second section of the field electrode and the gate electrode is greater than or equal to the separation between the first section of the field electrode and the gate electrode.

According to an embodiment of a method of producing a semiconductor device, the method comprises: forming a trench in a first main surface of a semiconductor substrate, the trench extending lengthwise in a direction parallel to the first main surface; forming a field electrode in a lower part of the trench and separated from the semiconductor substrate; forming a gate electrode in an upper part of the trench and separated from the semiconductor substrate and the field electrode so that a first section of the field electrode is buried below the gate electrode in the trench, a second section of the field electrode transitions upward from the first section in a direction toward the first main surface, and the separation between the second section of the field electrode and the gate electrode is greater than or equal to the separation between the first section of the field electrode and the gate electrode; forming a body region of a second conductivity type adjoining the trench; forming a source region of a first conductivity type adjoining the trench above the body region; and forming a drift region of the first conductivity type adjoining the trench below the body region.

According to another embodiment of a method of producing a semiconductor device, the method comprises: forming trenches in a first main surface of a semiconductor substrate, the trenches extending lengthwise in a direction parallel to the first main surface; forming a field electrode in a lower part of the trenches and separated from the semiconductor substrate; forming a gate electrode in an upper part of the trenches and separated from the semiconductor substrate and the field electrode so that a first section of the field electrode is buried below the gate electrode in the trenches, a second section of the field electrode transitions upward from the first section in a direction toward the first main surface in an intermediate part of the trenches between opposing ends of the trenches, and the separation between the second section of the field electrode and the gate electrode is greater than or equal to the separation between the first section of the field electrode and the gate electrode; forming body regions of a second conductivity type adjoining the trenches; forming source regions of a first conductivity type adjoining the trenches above the body regions; forming a drift region of the first conductivity type adjoining the trenches below the body regions; and forming an electrically conductive layer above the trenches and which is electrically connected to the field electrode in the trenches at the second section and has a lengthwise extension which is transverse to the lengthwise extension of the trenches.

DETAILED DESCRIPTION

The embodiments described herein provide a trench field electrode termination structure for transistor devices which enables easy electrical connection to the field electrode with robust dielectric breakdown characteristics at the point of electrical connection, and methods of manufacturing such a device. The trench is formed in a main surface of a semiconductor substrate and extends lengthwise in a direction parallel to the main surface. A field electrode is formed in a lower part of the trench and separated from the semiconductor substrate. A gate electrode for the device is formed in an upper part of the trench and separated from the semiconductor substrate and the field electrode. A first section of the field electrode is buried below the gate electrode in the trench. A second section of the field electrode transitions upward from the first section in a direction toward the first main surface, to enable a low resistance electrical connection to the desired potential, for example, source or gate potential. The separation between the second section of the field electrode and the gate electrode is greater than or equal to the separation between the first section of the field electrode and the gate electrode, thereby providing robust dielectric breakdown characteristics at the point of electrical connection to the field electrode.

FIG. 1illustrates a cross-sectional view of part of a semiconductor device. The part of the device illustrated includes a trench100formed in a first main surface102of a semiconductor substrate104. The semiconductor substrate104may include a semiconductor base and one or more epitaxial layers grown on the semiconductor base. The semiconductor substrate104may be made of a single semiconductor such as Si, Ge, etc. or may be made of a compound semiconductor such as SiC, GaN, SiGe, etc.

The trench100extends lengthwise in a direction ‘x’ parallel to the first main surface102of the semiconductor substrate104. The cross-section illustrated inFIG. 1is taken along the lengthwise extension of the trench100. A body region of a second conductivity type adjoins the trench100. A source region of a first conductivity type also adjoins the trench100, above the body region. The body and source regions are positioned along both longitudinal sides of the trench100and therefore are out of view inFIG. 1. A drift region106of the first conductivity type adjoins the trench100below the body region, and a drain region107of the first conductivity type is between the drift region106at the second main surface109of the semiconductor substrate104. The drift region106may be an epitaxial region grown on the semiconductor substrate104, e.g., before the trench100is formed. In the case of an n-channel device, the first conductivity type is n-type and the second conductivity type is p-type. Conversely, the first conductivity type is p-type and the second conductivity type is n-type in the case of a p-channel device.

A field electrode108is disposed in a lower part of the trench100and separated from the semiconductor substrate104by a dielectric110such as an oxide. A gate electrode112is disposed in an upper part of the trench100and separated from the semiconductor substrate104and the field electrode109by one or more dielectrics114. The field electrode108, when biased accordingly, balances the charge in the drift region106to increase breakdown voltage of the device.

To facilitate easy electrical connection to the buried field electrode108and without compromising the breakdown characteristic of the dielectric114at the point of electrical connection, a first section116of the field electrode108is buried below the gate electrode112in the trench100and a second section118of the field electrode108transitions upward from the first section116in a direction toward the first main surface102of the semiconductor substrate104. The second section118of the field electrode108provides for a low resistance electrical connection to a desired potential, for example, source or gate potential, via a corresponding electrode120which is formed on an interlayer dielectric122. The lateral separation ‘S1’ between the second section118of the field electrode108and the gate electrode112is greater than or equal to the vertical separation ‘S2’ between the first section116of the field electrode108and the gate electrode112to ensure robust dielectric breakdown characteristics at the point of electrical connection. In one embodiment, the lateral separation ‘S1’ between the second section118of the field electrode108and the gate electrode112is greater than the vertical separation ‘S2’ between the first section116of the field electrode108and the gate electrode112.

Such separation is realized in accordance with various processing methods described later herein and according to which first and second lithographic layers are used to enable an electrical connection to the buried field electrode108without compromising the dielectric breakdown characteristics at the point of electrical connection.

FIG. 2illustrates a partial top plan view of the semiconductor device shown inFIG. 1, with the interlayer dielectric122omitted so as to provide an unobstructed view of the gate electrode112and the second section118of the field electrode108at the first main surface102of the semiconductor substrate104.FIG. 2shows multiple trenches100in parallel, each trench100having the construction shown inFIG. 1. The cross-sectional view ofFIG. 1is taken along the line labelled A-A′ inFIG. 2.

After a first dielectric material (out of view inFIG. 2) lines the bottom and sidewalls of the trenches100and a field electrode material is deposited in the dielectric lined trenches100, a first lithographic layer200is used as a mask to selectively thin the field electrode material in an active area202of the device while allowing the field electrode material to remain closer to the first main surface102of the substrate104in an electrode connection/bus region204of the device. The second section118of the field electrode108corresponds to where the field electrode material is protected by the first lithographic layer200and allowed to remain closer to the first main surface102of the substrate104. The second section118of the field electrode108facilitates electrical connection of the buried field electrode108to the desired potential such as source potential, gate potential, etc. The corresponding overlying electrode is not shown inFIG. 2to provide an unobstructed view of the trench structure in the electrode connection/bus region204of the device. The first lithographic layer200has a width W1inFIG. 2.

After depositing or growing the dielectric114and thinning the field electrode material in the active area202of the device, a second lithographic layer206is used to define the lateral separation ‘S1’ between the second section118of the field electrode108and the edge208of the gate electrode112facing the second section118of the field electrode108. The dielectric material114that separates the field electrode118from the gate electrode112is thinned partly or completely to the buried first section116of the field electrode108in those regions unprotected by the second lithographic layer206, and a gate dielectric210is formed on the exposed part of the upper sidewalls of the trenches100in the active area202of the device.

The second lithographic layer206has a width W2inFIG. 2which is greater than the width W1of the first lithographic layer200. The difference ΔW between W2and W1, also referred to herein as overhang, defines the amount of lateral separation ‘S1’ shown inFIG. 1between the second section118of the field electrode108and the gate electrode112at or near the first main surface102of the semiconductor substrate104. The width W1of the first lithographic layer200and the width W2of the second lithographic layer206are chosen so that the width difference/overhang ΔW results in the lateral separation ‘S1’ shown inFIG. 1between the second section118of the field electrode108and the gate electrode112being greater than or equal to the vertical separation ‘S2’ shown inFIG. 1between the first section116of the field electrode108and the gate electrode112. In other words, the widths of the first and second lithographic layers200,206determines the degree to which the lateral separation ‘S1’ between the second section118of the field electrode108and the gate electrode112is greater than or equal to the vertical separation ‘S2’ between the first section116of the field electrode108and the gate electrode112.

InFIG. 2, the second section118of the field electrode108transitions upward from the first section116in an intermediate part of each trench100between opposing ends of the gate electrode112. An electrically conductive layer120formed above the trenches100in the electrode connection/bus region204of the device, e.g. as shown inFIG. 1, is electrically connected to each field electrode108at the second section118and has a lengthwise extension in direction ‘y’ which is transverse to the lengthwise extension of the trenches100in direction ‘x’. InFIGS. 1 and 2, directions ‘x’ and ‘y’ are horizontal directions with respect to the first main surface102of the semiconductor substrate104, and direction ‘z’ is a vertical direction with respect to the first main surface102of the semiconductor substrate104.

FIG. 3illustrates another partial top plan view of the semiconductor device shown inFIG. 1, in a different part of the device than what is shown inFIG. 2. Similar toFIG. 2, the interlayer dielectric is omitted inFIG. 3to provide an unobstructed view of the gate electrode112and second section118of the field electrode108at the first main surface102of the semiconductor substrate104. InFIG. 3, the second section118of the field electrode108transitions upward from the first section116at the end of each trench100which is adjacent an edge termination region300formed in the semiconductor substrate104. The edge termination region300is positioned between the active area202of the device and an edge302of the semiconductor substrate104. The edge termination region300may include termination trenches304with electrodes306for supporting the voltage of the device but which do not contribute to the main current path of the device. Such termination trenches are well known in the power semiconductor art, and therefore no further description of the termination trenches304is provided.

FIG. 4shows a cross-sectional view of the device along the line labeled B-B′ inFIG. 3.

As inFIG. 2, the difference/overhang ΔW between the with W2of the second lithographic layer206and the width W1of the first lithographic layer200determines the amount of lateral separation ‘S1’ shown inFIG. 4between the second section118of the field electrode108and the gate electrode112at or near the first main surface102of the semiconductor substrate104. The width W1of the first lithographic layer200and the width W2of the second lithographic layer206are chosen so that the width difference/overhang ΔW results in the lateral separation ‘S1’ shown inFIG. 4between the second section118of the field electrode108and the gate electrode112being greater than or equal to the vertical separation ‘S2’ shown inFIG. 4between the first section116of the field electrode108and the gate electrode112.

The semiconductor device may include both the intermediate field electrode connection arrangement shown inFIG. 2and the end field electrode connection arrangement shown inFIG. 3, or one of the field electrode connection arrangements shown inFIGS. 2 and 3but not the other.

FIGS. 5A through 5Fillustrate partial schematic views during different stages of a method of producing the intermediate field electrode connection arrangement shown inFIG. 2.

FIG. 5Ashows the semiconductor substrate104after forming the trenches100in the first main surface102of the semiconductor substrate104, lining a bottom and sidewalls of the trenches100with a first dielectric500, filling the trenches100with an electrically conductive material502such as polysilicon and/or metal after lining the bottom and sidewalls of the trenches100with the first dielectric500, and thinning part of the electrically conductive material502to form the first and the second sections116,118of the field electrode108in each trench100. Although not shown inFIG. 5A, the first dielectric500may also be on the first main surface102of the semiconductor substrate104to protect the mesa section104between the trenches100during subsequent etching.

A first mask504having a width W1is used to selectively thin the field electrode material502in the active area202of the device while allowing the field electrode material502to extend to the first main surface102of the substrate104in the electrode connection/bus region204of the device. The first mask504protects a portion of the electrically conductive material502which corresponds to the second section118of the field electrodes108. The part of the electrically conductive material502unprotected by the first mask504is thinned to define the first section116of the field electrodes108.

The first mask504corresponds to the first lithographic layer previously described herein and is shown inFIG. 5Aas a dashed box so as to not full obstruct the underlying trench structures. In one embodiment, first mask504is a photoresist used to cover the areas where the second section118of the field electrodes108are to be defined.

FIG. 5Bshows the semiconductor substrate104after the space in the trenches formed by thinning the electrically conductive material is filled with a second dielectric506. In one embodiment, the first dielectric500and the second dielectric506are the same type of dielectric material, e.g., silicon dioxide.

FIG. 5Cshows the semiconductor substrate104after planarizing the second dielectric506over the first section116of each field electrode108.

FIG. 5Dshows the semiconductor substrate104after forming a second mask508which protects a part510of the second dielectric506adjoining the second section118of the field electrodes108, and after thinning the part512of the second dielectric506unprotected by the second mask508. The thinning of the exposed part512of the second dielectric506stops before reaching the buried first section116of the field electrodes108, according to this embodiment. For example, a timed etch process may be employed and which stops before exposing the buried first section116of the field electrodes108. The remaining thickness of the part512of the second dielectric506unprotected by the second mask508defines the vertical separation ‘S2’ between the first section116of the field electrode108and the gate electrode112to be formed in the trenches100.

The second mask508corresponds to the second lithographic layer previously described herein, has a width W2, and is shown inFIG. 5Das a dashed box so as to not full obstruct the underlying trench structures. In one embodiment, the second mask508is a photoresist used to cover the area of separation518between the gate electrode112to be formed and the second section118of the field electrode108in the same trench100. The overhang (W2−W1) between the second mask508and the first mask504defines the amount of lateral separation S1between the second section118of the field electrode108and the gate electrode112to be formed in the same trench100.

FIG. 5Eshows the semiconductor substrate104after the gate dielectric210is formed on the exposed upper part of the trench sidewalls. Although not shown inFIG. 5E, the gate dielectric210may also be on the first main surface102of the semiconductor substrate104.

FIG. 5Fshows the semiconductor substrate104after an electrically conductive material514such as polysilicon and/or metal is deposited in the trenches100and planarized to form the gate electrodes112. The gate dielectric210separates the gate electrode112in each trench from the surrounding semiconductor substrate104.

FIGS. 6A through 6Fillustrate partial schematic views during different stages of a method of producing the intermediate field electrode connection arrangement shown inFIG. 2, according to another embodiment. The processing shown inFIGS. 6A through 6Ccorresponds to the processing shown inFIGS. 5A through 5C, respectively. Hence, no further description ofFIGS. 6A through 6Cis provided. Although not shown inFIG. 6A, the first dielectric500may also be on the first main surface102of the semiconductor substrate104to protect the mesa section104between the trenches100during subsequent etching. Although not shown inFIG. 6E, the gate dielectric210may also be on the first main surface102of the semiconductor substrate104.

However, according to the embodiment illustrated inFIGS. 6A through 6F, the part512of the second dielectric506unprotected by the second mask508is thinned down to the buried first section116of the field electrodes108. For example, the field electrode material502may be used as an etch stop in determining when to stop the etching process. Unlike the embodiment illustrated inFIG. 5D, the embodiment illustrated inFIG. 6Dexposes the top surface of the first section116of the field electrodes108. By etching the second dielectric506to expose the first section116of each field electrode108, the second dielectric506remains only along sidewalls of the second section118of the field electrodes108where the part510of the second dielectric506is protected by the second mask508.

FIG. 6Eshows the semiconductor substrate104after the gate dielectric210is formed on the exposed upper prat of the trench sidewalls, and an inter-electrode dielectric600is formed on the exposed part of the first section116of each field electrode108. The thickness of the inter-electrode dielectric600defines the vertical separation ‘S2’ between the first section116of the field electrode108and the gate electrode112to be formed in the trenches100, according to this embodiment.

In one embodiment, the gate dielectric210is formed along an upper (exposed) part of the trench sidewalls after exposing the first section116of the field electrodes108as shown inFIG. 6Dand after depositing the inter-electrode dielectric600but before forming the gate electrode112. Separately or in combination, the inter-electrode dielectric600may be deposited by high density plasma chemical vapor deposition. Another option is to use the enhanced oxidation rate of N-doped polysilicon field plate to form the inter-electrode dielectric600at the same time as the gate oxidation.

FIG. 6Fshows the semiconductor substrate104after an electrically conductive material514such as polysilicon and/or metal is deposited in the trenches100and planarized to form the gate electrodes112. The gate dielectric210separates the gate electrode112in each trench100from the surrounding semiconductor substrate104, and the inter-electrode dielectric600separates each gate electrode112from the buried first section116of the field electrode108in the same trench100.

FIGS. 7A through 7Sillustrate partial schematic views during different stages of a method of producing the end field electrode connection arrangement shown inFIGS. 3 and 4. The leftmost drawing of each ofFIGS. 7A through 7Sis a partial cross-section through the active area202of the device. The middle drawing of each ofFIGS. 7A through 7Sis a cross-section through a termination region where the active trenches100end. The rightmost drawing of each ofFIGS. 7A through 7Sis a cross-section through the edge termination region300of the device.

FIG. 7Ashows a mask700formed on the first main surface102of the semiconductor substrate104and trenches100,304etched into the first main surface104of the substrate104through openings in the mask700. The trenches100,304extend lengthwise in a direction parallel to the first main surface102of the substrate104, and may be arranged in any desired pattern such as stripes, serpentine, etc. In one embodiment, the mask700is made of nitride.

FIG. 7Bshows a first dielectric702deposited on the sidewalls and bottom of the trenches100,304. The first dielectric702may be TEOS (tetraethyl orthosilicate) or a thermal oxide, for example.

FIG. 7Cshows an electrically conductive material704filling the trenches100,304and separated from the surrounding semiconductor substrate104by the first dielectric702. In one embodiment, the electrically conductive material704is deposited polysilicon.

FIG. 7Dshows the electrically conductive material704after being planarized to form the basic structure of the field electrodes108. In one embodiment, the electrically conductive material704is planarized by a CMP (chemical-mechanical polishing) process which stops on the first dielectric702.

FIG. 7Eshows a mask706formed on part of the device and used to selectively thin the electrically conductive material704in the active area202of the device while protecting the field electrode material704at the first main surface102of the substrate104in the electrode connection/bus region204of the device and in part of the edge termination region300. The mask706protects a part of the electrically conductive material704which corresponds to the second section118of the field electrodes108. The part of the electrically conductive material704unprotected by the mask706is thinned to define the first section116of the field electrodes108. The mask706corresponds to the first lithographic layer previously described herein, and also protects the first dielectric material702which surrounds the second section118of the field electrodes108in the electrode connection/bus region204of the device during thinning of the field electrode material704in the active area202of the device. In one embodiment, the mask706is a photoresist used to cover the areas where the second section118of the field electrodes108are to be defined.

FIG. 7Fshows the first dielectric702removed from the upper part of the sidewalls708of the trenches100which are fully active/conducting trenches. The first mask706may be used to remove the first dielectric702from the upper part of the trench sidewalls708, and is then removed.

FIG. 7Gshows a second dielectric710deposited in the trenches100,304. In one embodiment, the second dielectric710is a high-density plasma (HDP) oxide deposited by chemical vapor deposition (CVD).

FIG. 7Hshows the second dielectric710after being planarized, e.g., using CMP, to form an inter-electrode dielectric712at least in the fully active/conducting trenches100. The planarization process may stop on the mask700used to etch the trenches100,304, if still present, and the mask700is then removed.

FIG. 7Ishows a mask714formed on part of the device and used to protect a part of the second dielectric712adjoining the second section118of the field electrodes108. The unprotected part of the second dielectric712is thinned to form a space716in the upper part of at least the fully active/conducting trenches100for the gate electrode and to again expose the upper part of the sidewalls708of at least the fully active/conducting trenches100. In the case of the HDP oxide example given above, any typical oxide etching process may be used. The mask714used to define the space716for the gate electrode in the upper part of at least the fully active/conducting trenches100corresponds to the second lithographic layer previously described herein and has an overhang with respect to the mask706used inFIG. 7Eto thin an unprotected part of the electrically conductive material704to define the first section116of the field electrodes108.

As explained previously herein, the extent or degree by which the second mask714overhangs the first mask706defines the amount of lateral separation ‘S1’ between the second section118of each field electrode108and the gate electrode to be formed in the same trench100. That is, the overhang between the two masks714,706defines the lateral thickness of the second dielectric710between the second section118of each field electrode108and the gate electrode to be formed in the same trench100.

The thinning of the exposed part of the second dielectric710may stop before reaching the buried first section116of the field electrodes108, e.g., as previously described herein in connection withFIG. 5D. Alternatively, the exposed part of the second dielectric710may be etched so that the first section116of each field electrode108is exposed, e.g., as previously described herein in connection withFIG. 6D. In this case, a new inter-electrode dielectric may be formed on the exposed part of the first section116of each field electrode108as previously described herein, e.g., as previously described herein in connection withFIG. 6E.

FIG. 7Jshows a gate dielectric718formed on the exposed upper part of the sidewalls708of at least the fully active/conducting trenches100. In one embodiment, the gate dielectric718is an oxide formed.

FIG. 7Kshows an electrically conductive material720such as polysilicon and/or metal deposited in the space716previously formed in the upper part of at least the fully active/conducting trenches100.

FIG. 7Lshows the device after the electrically conductive material720is planarized, e.g., by CMP. In one embodiment, the planarization process stops on the underlying gate dielectric.

The planarized electrically conductive material720forms the gate electrode112in the upper part of at least the fully active/conducting trenches100. The gate dielectric718separates the gate electrode112in each trench100from the surrounding semiconductor substrate104. As previously explained herein, the lateral separation ‘S1’ between the second section118of the field electrode108and the gate electrode112in the same trench100is greater than or equal to the vertical separation ‘S2’ between the first section116of the field electrode108and the gate electrode112to ensure robust dielectric breakdown characteristics at the point of electrical connection. Also as previously explained herein, the widths of the masks714,706shown inFIGS. 7E and 7Idetermines the degree to which the lateral separation ‘S1’ between the second section118of the field electrode108and the gate electrode112in the same trench100is greater than or equal to the vertical separation ‘S2’ between the first section116of the field electrode108and the gate electrode112.

FIG. 7Mshows the device after the gate dielectric718is removed from the semiconductor mesas722between adjacent trenches100,304. In the active area202of the device, the body and source regions are subsequently formed in the semiconductor mesas722.

FIG. 7Nshows the device after a screen dielectric724such as oxide is formed on the surface of the device.

FIG. 7Oshows the device after dopants of the second conductivity type are implanted through the screen dielectric724into the semiconductor mesas722between at least the fully active/conducting trenches100and annealed to form the body regions726of the device. The body regions726include a channel which runs along the trench sidewall708between the drift region106and the source region to be formed, and is controlled by a voltage applied to the adjacent gate electrode112.

FIG. 7Pshows the device after dopants of the first conductivity type are implanted through the screen dielectric724into the body regions726, and after an interlayer dielectric728is formed on the surface of the device. The source regions are not shown inFIG. 7P, because the implanted dopants of the first conductivity type have not been activated yet.

FIG. 7Qshows the device after contact openings730are formed in the interlayer dielectric728which expose the body regions726and the second section118of the field electrodes108. The contact openings730may be realized by forming a mask (not shown) with corresponding openings on the interlayer dielectric728, and etching the exposed parts of the interlayer dielectric728.

FIG. 7Rshows the device after dopants of the second conductivity type are implanted through the contact openings730in the interlayer dielectric728into the body regions726, and after an annealing process which activates both dopant types to form highly doped body contact regions732of the second conductivity type and source regions734of the first conductivity type, respectively. Each body region726of the second conductivity type adjoins an adjacent trench100. Each source region734of the first conductivity type also adjoins an adjacent trench100above the corresponding body region726. The drift region106of the first conductivity type adjoins the trenches100below the body regions726. The semiconductor substrate104may have a base doping concentration which yields the drift region106. For example, as previously explained herein, the drift region106may be an epitaxial region grown on the semiconductor substrate104before the trenches100are formed.

FIG. 7Sshows the device after a source metallization738is formed on the interlayer dielectric728and filling the contact openings730in the interlayer dielectric728. The source metallization738provide source potential to the source and body regions,734,726, and to the field electrodes108via the second section118in this embodiment. The field electrodes108may instead be coupled to a different potential such as the gate metallization which is out of view inFIG. 7S.

As mentioned above, the rightmost drawing of each ofFIGS. 7A through 7Sis a cross-section through the edge termination region of the device. From left to right in the rightmost drawing of each ofFIGS. 7A through 7S: the first trench is a fully active/conducting trench; the second trench is an active/conducting on the left-hand side; the third and fourth trenches are non-conducting in the on-state of the device; and the fifth trench and onward are electric field termination trenches. The electric field termination trenches, some of which have floating field electrodes, may be used for termination, especially for higher voltage devices, with the voltage gradually being dropped in the semiconductor mesas between these trenches. The electric field termination trenches may also serve to ensure pattern density requirements are met in the trench layer, such that the first active trench from the edge has a critical dimension which is on target.

FIG. 8illustrates a top plan view of another embodiment of a semiconductor device having a trench field electrode termination structure which enables easy electrical connection to the field electrode with robust dielectric breakdown characteristics at the point of electrical connection. According to this embodiment, the semiconductor device includes trenches100formed in a first main surface of a semiconductor substrate802, the trenches800extending lengthwise in a direction ‘x’ parallel to the first main surface. A field electrode is formed in the lower part of the trenches800and separated from the semiconductor substrate802by a dielectric. A gate electrode is formed in an upper part of the trenches800and separated from the semiconductor substrate802and the field electrode so that a first section of the field electrode is buried below the gate electrode in the trenches800, a second section of the field electrode transitions upward from the first section in a direction toward the first main surface in an intermediate part of the trenches between opposing ends of the trenches, and the separation between the second section of the field electrode and the gate electrode is greater than or equal to the separation between the first section of the field electrode and the gate electrode.

Body regions of a second conductivity type adjoin the trenches800, source regions of a first conductivity type also adjoin the trenches800above the body regions, and a drift region of the first conductivity type adjoins the trenches800below the body regions. A simplified representation of the trenches800and device regions is shown inFIG. 8, to emphasize the serpentine-like layout of the trenches800. The field and gate electrodes may be disposed in the trenches800as shown in any one of the preceding figures, and the device regions may also be arranged as previously described herein and illustrated. The source implantation region is represented by the boxes labelled ‘Source’ inFIG. 8.

An electrically conductive layer formed above the trenches800is electrically connected to the field electrode in the trenches800at the second section and has a lengthwise extension in direction ‘y’ which is transverse to the lengthwise extension of the trenches in direction ‘x’. For example, the second section of the field electrodes disposed in the trenches800may be contacted at the ends of the trenches800to a source metallization804by contacts806which extend through an interlayer dielectric separating the source metallization804from the underlying substrate802. The gate electrodes disposed in the trenches800may be contacted in an intermediate region800to a gate metallization808by contacts810which extend through the interlayer dielectric. The masks/lithographic layers which define the amount of separation between the second section of the field electrode and the gate electrode in each trench800are labelled ‘SPP’ and ‘OXP’ inFIG. 8, with the overhang between the masks/lithographic layers being labelled ‘Overlap’.

After forming the gate electrode in the upper part of the trenches800but before forming the source and gate metallizations804,808above the trenches800, an interlayer dielectric may be formed over the semiconductor substrate802, e.g., as shown inFIG. 7P. Using a common lithography process, contact openings may be formed which extend through the interlayer dielectric to the source regions, the body regions, the gate electrodes, the second section of the field electrodes and to field termination structures formed in an edge termination region of the semiconductor substrate802. According to this embodiment, all device contacts have the identical critical dimension and depth, making it easier for all device contacts to be implemented using a single lithography step, e.g., as shown inFIG. 7Q.

Example 1. A semiconductor device, comprising: a trench formed in a first main surface of a semiconductor substrate and extending lengthwise in a direction parallel to the first main surface; a body region of a second conductivity type adjoining the trench; a source region of a first conductivity type adjoining the trench above the body region; a drift region of the first conductivity type adjoining the trench below the body region; a field electrode disposed in a lower part of the trench and separated from the semiconductor substrate; and a gate electrode disposed in an upper part of the trench and separated from the semiconductor substrate and the field electrode, wherein a first section of the field electrode is buried below the gate electrode in the trench, wherein a second section of the field electrode transitions upward from the first section in a direction toward the first main surface, wherein the separation between the second section of the field electrode and the gate electrode is greater than or equal to the separation between the first section of the field electrode and the gate electrode.

Example 2. The semiconductor device of example 1, wherein the separation between the second section of the field electrode and the gate electrode is greater than the separation between the first section of the field electrode and the gate electrode.

Example 3. The semiconductor device of examples 1 or 2, wherein a same type of dielectric material separates the first and the second sections of the field electrode from the gate electrode.

Example 4. The semiconductor device of any one of examples 1 through 3, wherein the second section of the field electrode transitions upward from the first section in an intermediate part of the trench between opposing ends of the trench, and wherein an electrically conductive layer formed above the trench and which is electrically connected to the field electrode at the second section has a lengthwise extension which is transverse to the lengthwise extension of the trench.

Example 5. The semiconductor device of any one of examples 1 through 3, wherein the second section of the field electrode transitions upward from the first section at an end of the trench which is adjacent an edge termination region formed in the semiconductor substrate.

Example 6. A method of producing a semiconductor device, the method comprising: forming a trench in a first main surface of a semiconductor substrate, the trench extending lengthwise in a direction parallel to the first main surface; forming a field electrode in a lower part of the trench and separated from the semiconductor substrate; forming a gate electrode in an upper part of the trench and separated from the semiconductor substrate and the field electrode so that a first section of the field electrode is buried below the gate electrode in the trench, a second section of the field electrode transitions upward from the first section in a direction toward the first main surface, and the separation between the second section of the field electrode and the gate electrode is greater than or equal to the separation between the first section of the field electrode and the gate electrode; forming a body region of a second conductivity type adjoining the trench; forming a source region of a first conductivity type adjoining the trench above the body region; and forming a drift region of the first conductivity type adjoining the trench below the body region. As previously explained herein, the drift region may be an epitaxial region grown on the semiconductor substrate, e.g., before the trench is formed.

Example 7. The method of example 6, wherein forming the field electrode comprises: lining a bottom and sidewalls of the trench with a first dielectric; after lining the bottom and the sidewalls of the trench with the first dielectric, filling the trench with an electrically conductive material; thinning part of the electrically conductive material to form the first and the second sections of the field electrode; filling a space in the trench formed by thinning the electrically conductive material with a second dielectric; thinning the second dielectric over the first section of the field electrode so that a lateral thickness of the second dielectric measured in a horizontal direction toward the second section of the field electrode is greater than or equal to a vertical thickness of the second dielectric measured in a vertical direction toward the first section of the field electrode; and forming the gate electrode in a space formed in the trench after the second dielectric is thinned over the first section of the field electrode.

Example 8. The method of example 7, wherein thinning part of the electrically conductive material to form the first and the second sections of the field electrode comprises: forming a first mask which protects a portion of the electrically conductive material; and thinning the part of the electrically conductive material unprotected by the first mask.

Example 9. The method of example 8, wherein thinning the second dielectric over the first section of the field electrode comprises: forming a second mask which protects a part of the second dielectric adjoining the portion of the electrically conductive material which was protected by the first mask during the thinning of the electrically conductive material; and thinning the part of the second dielectric unprotected by the second mask, wherein an overhang between the second mask and the first mask defines the amount of separation between the second section of the field electrode and the gate electrode.

Example 10. The method of example 9, further comprising: after thinning the part of the second dielectric unprotected by the second mask but before forming the gate electrode, forming a gate dielectric along an upper part of the sidewalls of the trench.

Example 11. The method of example 6, wherein forming the field electrode comprises: lining a bottom and sidewalls of the trench with a first dielectric; after lining the bottom and the sidewalls of the trench with the first dielectric, filling the trench with an electrically conductive material; thinning part of the electrically conductive material to form the first and the second sections of the field electrode; filling a space in the trench formed by thinning the electrically conductive material with a second dielectric; etching the second dielectric so that the first section of the field electrode is exposed and the second dielectric remains only along sidewalls of the second section of the field electrode; forming a third dielectric on the exposed part of the first section of the field electrode and on the remaining part of the second dielectric, so that a combined lateral thickness of the third dielectric and the remaining part of the second dielectric measured in a horizontal direction toward the second section of the field electrode is greater than or equal to a vertical thickness of the third dielectric measured in a vertical direction toward the first section of the field electrode; and forming the gate electrode in a space formed in the trench after depositing the third dielectric.

Example 12. The method of example 11, wherein thinning part of the electrically conductive material to form the first and the second sections of the field electrode comprises: forming a first mask which protects a portion of the electrically conductive material; and thinning the part of the electrically conductive material unprotected by the first mask.

Example 13. The method of example 12, wherein etching the second dielectric comprises: forming a second mask which protects a part of the second dielectric adjoining the portion of the electrically conductive material which was protected by the first mask during the thinning of the electrically conductive material; and etching a part of the second dielectric unprotected by the second mask down to the first section of the field electrode to expose the first section, wherein an overhang between the second mask and the first mask defines the amount of separation between the second section of the field electrode and the gate electrode.

Example 14. The method of example 13, further comprising: after exposing the first section of the field electrode and after depositing the third dielectric but before forming the gate electrode, forming a gate dielectric along an upper part of the sidewalls of the trench.

Example 15. The method of any one of examples 11 through 14, wherein the third dielectric is deposited by high density plasma chemical vapor deposition.

Example 16. The method of any one of examples 11 through 14, wherein the third dielectric is formed as part of a gate oxidation process during which an accelerated oxidation rate of heavily phosphorus-doped polysilicon forms the third dielectric.

Example 17. The method of example 6, further comprising: forming an edge termination region in the semiconductor substrate, wherein a first end of the trench terminates adjacent the edge termination region, wherein the second section of the field electrode transitions upward from the first section at the first end of the trench, wherein forming the field electrode comprises: lining a bottom and sidewalls of the trench with a first dielectric; after lining the bottom and the sidewalls of the trench with the first dielectric, filling the trench with an electrically conductive material; thinning part of the electrically conductive material spaced apart from the first end of the trench to form the first and the second sections of the field electrode, the first section being disposed in the first end of the trench; filling a space in the trench formed by thinning the electrically conductive material with a second dielectric; thinning the second dielectric over the first section of the field electrode so that a lateral thickness of the second dielectric measured in a horizontal direction toward the second section of the field electrode is greater than or equal to a vertical thickness of the second dielectric measured in a vertical direction toward the first section of the field electrode; and forming the gate electrode in a space formed in the trench after the second dielectric is thinned over the first section of the field electrode.

Example 18. The method of example 17, wherein thinning part of the electrically conductive material spaced apart from the first end of the trench comprises: forming a first mask which protects the part of the electrically conductive material disposed in the first end of the trench; and thinning the part of the electrically conductive material spaced apart from the first end of the trench and unprotected by the first mask.

Example 19. The method of example 18, wherein thinning the second dielectric over the first section of the field electrode comprises: forming a second mask which protects a part of the second dielectric adjoining the part of the electrically conductive material disposed in the first end of the trench and which was protected by the first mask during the thinning of the electrically conductive material; and thinning the part of the second dielectric spaced apart from the first end of the trench and unprotected by the second mask, wherein an overhang between the second mask and the first mask defines the amount of separation between the second section of the field electrode and the gate electrode.

Example 20. The method of example 6, wherein gate oxidation forms both the gate oxide and the dielectric between the first section of the field electrode and the gate electrode.

Example 21. A method of producing a semiconductor device, the method comprising: forming trenches in a first main surface of a semiconductor substrate, the trenches extending lengthwise in a direction parallel to the first main surface; forming a field electrode in a lower part of the trenches and separated from the semiconductor substrate; forming a gate electrode in an upper part of the trenches and separated from the semiconductor substrate and the field electrode so that a first section of the field electrode is buried below the gate electrode in the trenches, a second section of the field electrode transitions upward from the first section in a direction toward the first main surface in an intermediate part of the trenches between opposing ends of the trenches, and the separation between the second section of the field electrode and the gate electrode is greater than or equal to the separation between the first section of the field electrode and the gate electrode; forming body regions of a second conductivity type adjoining the trenches; forming source regions of a first conductivity type adjoining the trenches above the body regions; forming a drift region of the first conductivity type adjoining the trenches below the body regions; and forming an electrically conductive layer above the trenches and which is electrically connected to the field electrode in the trenches at the second section and has a lengthwise extension which is transverse to the lengthwise extension of the trenches. As previously explained previously herein, the drift region may be an epitaxial region grown on the semiconductor substrate, e.g., before the trenches are formed.

Example 22. The method of example 21, further comprising: after forming the gate electrode in the upper part of the trenches but before forming the electrically conductive layer above the trenches, forming an interlayer dielectric over the semiconductor substrate; and forming, using a common lithography process, contact openings which extend through the interlayer dielectric to the source regions, the body regions, the gate electrodes, the second section of the field electrodes and to field termination structures formed in an edge termination region of the semiconductor substrate.