Integrated circuit package system with device cavity

An integrated circuit package system is provided including connecting an integrated circuit die with an external interconnect, forming a first encapsulation having a device cavity with the integrated circuit die therein, mounting a device in the device cavity over the integrated circuit die, and forming a cover over the device and the first encapsulation.

TECHNICAL FIELD

The present invention relates generally to an integrated circuit package system, and more particularly to an integrated circuit package system with encapsulating features.

BACKGROUND ART

Increased miniaturization of components, greater packaging density of integrated circuits (“ICs”), higher performance, and lower cost are ongoing goals of the computer industry. As new generations of IC products are released, the number of devices used to fabricate them tends to decrease due to advances in technology. Simultaneously, the functionality of these products increases.

Semiconductor package structures continue to advance toward miniaturization and thinning to increase the density of the components that are packaged therein while decreasing the sizes of the products that are made therefrom. This is in response to continually increasing demands on information and communication apparatus for ever-reduced sizes, thicknesses, and costs, along with ever-increasing performance.

These increasing requirements for miniaturization are particularly noteworthy, for example, in portable information and communication devices such as cellular phones, hands-free cellular phone headsets, personal data assistants (“PDA's”), camcorders, notebook personal computers, and so forth. All of these devices continue to be made smaller and thinner to improve their portability. Accordingly, large-scale IC (“LSI”) packages that are incorporated into these devices are required to be made smaller and thinner. The package configurations that house and protect LSI require them to be made smaller and thinner as well.

Many conventional semiconductor die (or “chip”) packages are of the type where a semiconductor die is molded into a package with a resin, such as an epoxy molding compound. The packages have a lead frame whose leads are projected from the package body, to provide a path for signal transfer between the die and external devices. Other conventional package configurations have contact terminals or pads formed directly on the surface of the package.

Such a conventional semiconductor package is fabricated through the following processes: a die-bonding process (mounting the semiconductor die onto the paddle of a lead frame), a wire-bonding process (electrically connecting the semiconductor die on the paddle to inner leads using lead frame wires), a molding process (encapsulating a predetermined portion of the assembly, containing the die, inner leads and lead frame wires, with an epoxy resin to form a package body), and a trimming process (completing each assembly as individual, independent packages).

The semiconductor packages, thus manufactured, are then mounted by matching and soldering the external leads or contact pads thereof to a matching pattern on a circuit board, to thereby enable power and signal input/output (“I/O”) operations between the semiconductor devices in the packages and the circuit board.

An exemplary semiconductor package, well known in the electronics industry, is the quad flat package (“QFP”). QFP packages typically comprise a lead frame, such as a conductive sheet stamped and etched, with a semiconductor die having a multitude of bond pads mounted to the top side of the lead frame. Wire bonds electrically connect the bond pads, of the semiconductor die, to a series of conductive lead fingers on the topside of the lead frame. Typically, the semiconductor die and the wire bonds are encapsulated within a molding compound.

In order to reduce manufacturing costs, the electronics industry is increasing the usage of QFP packages. In the manufacturing process, many obstacles must be overcome to deliver extremely small packages with thinner and thinner profile in high volume. Despite the trend towards miniaturization and thinner profile, more functions and more integrated circuits are continued to be packed into QFP packages.

Thus, a need still remains for an integrated circuit package system providing low cost manufacturing, improved yield, and improved reliability. In view of the ever-increasing need to save costs and improve efficiencies, it is more and more critical that answers be found to these problems.

DISCLOSURE OF THE INVENTION

The present invention provides an integrated circuit package system including connecting an integrated circuit die with an external interconnect, forming a first encapsulation having a device cavity with the integrated circuit die therein, mounting a device in the device cavity over the integrated circuit die, and forming a cover over the device and the first encapsulation.

BEST MODE FOR CARRYING OUT THE INVENTION

In the following description, numerous specific details are given to provide a thorough understanding of the invention. However, it will be apparent that the invention may be practiced without these specific details. In order to avoid obscuring the present invention, some well-known circuits, system configurations, and process steps are not disclosed in detail. Likewise, the drawings showing embodiments of the system are semi-diagrammatic and not to scale and, particularly, some of the dimensions are for the clarity of presentation and are shown greatly exaggerated in the drawing FIGs.

For expository purposes, the term “horizontal” as used herein is defined as a plane parallel to the plane or surface of the integrated circuit, regardless of its orientation. The term “vertical” refers to a direction perpendicular to the horizontal as just defined. Terms, such as “above”, “below”, “bottom”, “top”, “side” (as in “sidewall”), “higher”, “lower”, “upper”, “over”, and “under”, are defined with respect to the horizontal plane. The term “on” means there is direct contact among elements. The term “processing” as used herein includes deposition of material, patterning, exposure, development, etching, cleaning, molding, and/or removal of the material or as required in forming a described structure. The term “system” as used herein means and refers to the method and to the apparatus of the present invention in accordance with the context in which the term is used.

Referring now toFIG. 1, therein is shown a bottom view of an integrated circuit package system100in a first embodiment of the present invention. The bottom view depicts a first encapsulation102, such as an epoxy molded compound, with external interconnects104extending therefrom. The external interconnects104may be a number of types of leads. For example, the external interconnects104may be leads for a quad flat package.

For illustrative purposes, the external interconnects104are shown extending from the first encapsulation102, although it is understood that the external interconnects104may not extend from the first encapsulation102. For example, the external interconnects104may be within and exposed by the first encapsulation102.

Referring now toFIG. 2, therein is shown a cross-sectional view of the integrated circuit package system100ofFIG. 1along a line2-2. The cross-sectional view depicts the first encapsulation102having a device cavity202extending below a first portion204of the external interconnects104. The cross-sectional view also depicts a cover206, such as an epoxy molding compound, over the first encapsulation102.

A first integrated circuit die208having a first active side210and a first non-active side212is preferably in the device cavity202. The first active side210preferably faces the first encapsulation102and the first non-active side212faces upwards and away from the first encapsulation102. First lower interconnects214, such as bond wires or ribbon bonds, connect the first active side210and a predetermined selection of the external interconnects104.

The first encapsulation102covers the first active side210and exposes the first non-active side212in the device cavity202. The first encapsulation102also covers the first lower interconnects214. The first encapsulation102covers the inner portion of the first portion204of the external interconnects104.

A first device216, such as an integrated circuit die, having a first non-passive side218and a first passive side220is preferably over the first integrated circuit die208and in the device cavity202. The first passive side220faces the first non-active side212. First upper interconnects222, such as bond wires or ribbon bonds, connect the first non-passive side218and a predetermined selection of the external interconnects104.

The cover206covers the first device216, the first upper interconnects222, the first non-active side212, and the inner portion of the first portion204of the external interconnects104. A non-horizontal cover side of the cover206faces a non-horizontal encapsulation side of the first encapsulation102. The cover206fills the device cavity202. The first encapsulation102and the cover206form a hermetic interface with each other forming a package encapsulation224for the integrated circuit package system100.

Referring now toFIG. 3, therein is shown a cross-sectional view of an integrated circuit package system300along line2-2of a bottom view as exemplified byFIG. 1in a second embodiment of the present invention. The cross-sectional view depicts a first encapsulation301having a device cavity302extending below a first portion304of external interconnects305. The cross-sectional view also depicts a cover306, such as an epoxy molding compound, over the first encapsulation301.

A first integrated circuit die308having a first active side310and a first non-active side312is preferably in the device cavity302. The first active side310preferably faces the first encapsulation301and the first non-active side312faces upwards and away from the first encapsulation301. First lower interconnects314, such as bond wires or ribbon bonds, connect the first active side310and a predetermined selection of the external interconnects305.

The first encapsulation301covers the first active side310and exposes the first non-active side312in the device cavity302. The first encapsulation301also covers the first lower interconnects314. The first encapsulation301covers the inner portion of the first portion304of the external interconnects305.

A first device316, such as an integrated circuit die, having a first non-passive side318and a first passive side320is preferably over the first integrated circuit die308and in the device cavity302. The first passive side320faces the first non-active side312. First upper interconnects322, such as bond wires or ribbon bonds, connect the first non-passive side318and a predetermined selection of the external interconnects305.

A second device326, such as an integrated circuit die, having a second non-passive side328and a second passive side330is preferably over the first device316and the device cavity302. The second passive side330faces the first active side310. The first upper interconnects322, connect the second non-passive side328and a predetermined selection of the external interconnects305. For illustrative purposes, the first device316and the second device326are shown both connecting with the external interconnects305with the first upper interconnects322, although it is understood that the interconnect type may not be the same to connect to the first device316and the second device326.

The cover306covers the first device316, the first upper interconnects322, the first non-active side312, the second device326, and the inner portion of the first portion304of the external interconnects305. The cover306fills the device cavity302. The first encapsulation301and the cover306form a hermetic interface with each other forming a package encapsulation324for the integrated circuit package system300.

Referring now toFIG. 4, therein is shown a cross-sectional view of an integrated circuit package system400along line2-2of a bottom view as exemplified byFIG. 1in a third embodiment of the present invention. The cross-sectional view depicts a first encapsulation401having a device cavity402extending below a first portion404of external interconnects405. The cross-sectional view also depicts a cover406, such as an epoxy molding compound, over the first encapsulation401.

A first integrated circuit die408having a first active side410and a first non-active side412is preferably in the device cavity402. The first active side410preferably faces the first encapsulation401and the first non-active side412faces upwards and away from the first encapsulation401. First lower interconnects414, such as bond wires or ribbon bonds, connect the first active side410and a predetermined selection of the external interconnects405.

A second integrated circuit die426having a second active side428and a second non-active side430preferably stacks below the first integrated circuit die408. The second non-active side430faces the first active side410. The first lower interconnects414also connect the second active side428and a predetermined selection of the first portion404of the external interconnects405. For illustrative purposes, the first integrated circuit die408and the second integrated circuit die426are shown both connecting with the external interconnects405with the first lower interconnects414, although it is understood that the interconnect type may not be the same to connect to the first integrated circuit die408and the second integrated circuit die426.

The first encapsulation401covers the first active side410and exposes the first non-active side412in the device cavity402. The first encapsulation401also covers the first lower interconnects414and the second integrated circuit die426. The first encapsulation401covers the inner portion of the first portion404of the external interconnects405.

A first device416, such as an integrated circuit die, having a first non-passive side418and a first passive side420is preferably over the first integrated circuit die408and in the device cavity402. The first passive side420faces the first non-active side412. First upper interconnects422, such as bond wires or ribbon bonds, connect the first non-passive side418and a predetermined selection of the external interconnects405.

A second device432, such as an integrated circuit die, having a second non-passive side434and a second passive side436is preferably over the first device416and the device cavity402. The second passive side436faces the first active side410. The first upper interconnects422, connect the second non-passive side434and a predetermined selection of the external interconnects405. For illustrative purposes, the first device416and the second device432are shown both connecting with the external interconnects405with the first upper interconnects422, although it is understood that the interconnect type may not be the same to connect to the first device416and the second device432.

The cover406covers the first device416, the first upper interconnects422, the first non-active side412, the second device432, and the inner portion of the first portion404of the external interconnects405. The cover406fills the device cavity402. The first encapsulation401and the cover406form a hermetic interface with each other forming a package encapsulation424for the integrated circuit package system400.

Referring now toFIG. 5, therein is shown a cross-sectional view of an integrated circuit package system500along line2-2of a bottom view as exemplified byFIG. 1in a fourth embodiment of the present invention. The cross-sectional view depicts a first encapsulation501having a device cavity502extending below a first portion504of external interconnects505. The cross-sectional view also depicts a cover506, such as an epoxy molding compound, over the first encapsulation501.

A first integrated circuit die508having a first active side510and a first non-active side512is preferably in the device cavity502. The first active side510preferably faces the first encapsulation501and the first non-active side512faces upwards and away from the first encapsulation501. First lower interconnects514, such as bond wires or ribbon bonds, connect the first active side510and a predetermined selection of the external interconnects505.

The first encapsulation501covers the first active side510and exposes the first non-active side512in the device cavity502. The first encapsulation501also covers the first lower interconnects514. The first encapsulation501covers the inner portion of the first portion504of the external interconnects505.

A first device516, such as a laminated substrate or an integrated circuit die having a redistribution layer, having a first non-passive side518and a first passive side520is preferably over the first integrated circuit die508and in the device cavity502. The first passive side520faces the first non-active side512. First upper interconnects522, such as bond wires or ribbon bonds, connect pads526, such as terminal pads, of the first non-passive side518and a predetermined selection of the external interconnects505.

The cover506covers the first upper interconnects522, the first non-active side512, and the inner portion of the first portion504of the external interconnects505. The cover506also fills the device cavity502. The cover506includes a recess528exposing the first non-passive side518. Other devices, such as an integrated circuit die (not shown) or other integrated circuit package system (not shown), may mount over the first device516in the recess528. The first encapsulation501and the cover506form a hermetic interface with each other forming a package encapsulation524for the integrated circuit package system500.

Referring now toFIG. 6, therein is shown a cross-sectional view of an integrated circuit package system600along line2-2of a bottom view as exemplified byFIG. 1in a fifth embodiment of the present invention. The cross-sectional view depicts a first encapsulation601having a device cavity602extending below a first portion604of external interconnects605. The cross-sectional view also depicts a cover606, such as an optically clear grade resin encapsulant, over the first encapsulation601.

A first integrated circuit die608having a first active side610and a first non-active side612is preferably in the device cavity602. The first active side610preferably faces the first encapsulation601and the first non-active side612faces upwards and away from the first encapsulation601. First lower interconnects614, such as bond wires or ribbon bonds, connect the first active side610and a predetermined selection of the external interconnects605.

The first encapsulation601covers the first active side610and exposes the first non-active side612in the device cavity602. The first encapsulation601also covers the first lower interconnects614. The first encapsulation601covers the inner portion of the first portion604of the external interconnects605.

A first device616, such as an image sensor, having a first non-passive side618and a first passive side620is preferably over the first integrated circuit die608and in the device cavity602. The first passive side620faces the first non-active side612. First upper interconnects622, such as bond wires or ribbon bonds, connect the first non-passive side618and a predetermined selection of the external interconnects605.

The cover606covers the first device616, the first upper interconnects622, the first non-active side612, and the inner portion of the first portion604of the external interconnects605. The cover606fills the device cavity602. The optical translucent or transparent properties of the cover606allows light to pass through to and from the first device616. The first encapsulation601and the cover606form a hermetic interface with each other forming a package encapsulation624for the integrated circuit package system600.

Referring now toFIG. 7, therein is shown a cross-sectional view of an integrated circuit package system700along line2-2of a bottom view as exemplified byFIG. 1in a sixth embodiment of the present invention. The cross-sectional view depicts a first encapsulation701having a device cavity702extending below a first portion704of external interconnects705. The cross-sectional view also depicts a cover706, such as an optically clear grade resin encapsulant, over and within a recess707of the first encapsulation701.

A first integrated circuit die708having a first active side710and a first non-active side712is preferably in the device cavity702. The first active side710preferably faces the first encapsulation701and the first non-active side712faces upwards and away from the first encapsulation701. First lower interconnects714, such as bond wires or ribbon bonds, connect the first active side710and a predetermined selection of the external interconnects705.

The first encapsulation701covers the first active side710and exposes the first non-active side712in the device cavity702. The first encapsulation701also covers the first lower interconnects714. The first encapsulation701covers the inner portion of the first portion704of the external interconnects705. The first encapsulation701exposes the cover706.

For illustrative purposes, the integrated circuit package system700is shown with the first encapsulation701having the recess707and the cover706therein, although it is understood that the surrounding encapsulation around the cover706may be different than the first encapsulation701. For example, the surrounding encapsulation may have different properties from the first encapsulation701. The surrounding encapsulation may absorb light aiding in collimating light through the cover706.

A first device716, such as an image sensor, having a first non-passive side718and a first passive side720is preferably over the first integrated circuit die708and in the device cavity702. The first passive side720faces the first non-active side712. First upper interconnects722, such as bond wires or ribbon bonds, connect the first non-passive side718and a predetermined selection of the external interconnects705.

The cover706covers the first device716, the first upper interconnects722, the first non-active side712, and the inner portion of the first portion704of the external interconnects705. The cover706fills the device cavity702. The optical translucent or transparent properties of the cover706allows light to pass through to and from the first device716. The first encapsulation701and the cover706form a hermetic interface with each other forming a package encapsulation724for the integrated circuit package system700.

Referring now toFIG. 8, therein is shown a cross-sectional view of an integrated circuit package system800along line2-2of a bottom view as exemplified byFIG. 1in a seventh embodiment of the present invention. The cross-sectional view depicts a first encapsulation801having a device cavity802extending below a first portion804of external interconnects805. The cross-sectional view also depicts a cover806, such as an optical glass, over and within a stepped recess807of the first encapsulation801.

A first integrated circuit die808having a first active side810and a first non-active side812is preferably in the device cavity802. The first active side810preferably faces the first encapsulation801and the first non-active side812faces upwards and away from the first encapsulation801. First lower interconnects814, such as bond wires or ribbon bonds, connect the first active side810and a predetermined selection of the external interconnects805.

The first encapsulation801covers the first active side810and exposes the first non-active side812in the device cavity802. The first encapsulation801also covers the first lower interconnects814. The first encapsulation801covers the inner portion of the first portion804of the external interconnects805. The cover806is attached to the first encapsulation801in an indentation815of the stepped recess807.

For illustrative purposes, the integrated circuit package system800is shown with the first encapsulation801having the stepped recess807and the cover806therein, although it is understood that the surrounding encapsulation around the cover806may be different than the first encapsulation801. For example, the surrounding encapsulation may have different properties from the first encapsulation801. The surrounding encapsulation may absorb light aiding in collimating light through the cover806.

A first device816, such as an image sensor, having a first non-passive side818and a first passive side820is preferably over the first integrated circuit die808and in the device cavity802. The first passive side820faces the first non-active side812. First upper interconnects822, such as bond wires or ribbon bonds, connect the first non-passive side818and a predetermined selection of the external interconnects805.

The cover806covers the first device816, the first upper interconnects822, and the first non-active side812exposed in the device cavity802. A number of items may occupy the stepped recess807below the cover806and the device cavity802. For example, the stepped recess807below the cover806and the device cavity802may be a vacuum, filled with air (not shown), filled with an inert gas (not shown), or may have an optically translucent encapsulation (not shown). The first encapsulation801and the cover806form a hermetic interface with each other forming a package encapsulation824for the integrated circuit package system800.

Referring now toFIG. 9, therein is shown a cross-sectional view of a lead frame902. The lead frame902is on a tape904, such as a coverlay tape. The tape904attaches to a first side906of the lead frame902and provides a planar surface between the first side906and a space908within the lead frame902.

Referring now toFIG. 10, therein is shown the structure ofFIG. 9in a forming phase of the first encapsulation102. An integrated circuit die1002, such as the first integrated circuit die208ofFIG. 2without thinning, mounts on the tape904with the first active side210facing away from the tape904. The first lower interconnects214connect the first active side210and a second side1004of the lead frame902. The tape904secures the integrated circuit die1002to be coplanar with the first side906.

The first encapsulation102is formed covering the integrated circuit die1002and the first lower interconnects214. The first encapsulation102partially covers the second side1004. The tape904prevents the first encapsulation102from covering the first side906. The first encapsulation102may be formed in a number of ways, such as injection molding with a mold cap (not shown) over the integrated circuit die1002, the first lower interconnects214, and the lead frame902.

Referring now toFIG. 11, therein is shown the structure ofFIG. 10in a forming phase of the first integrated circuit die208. The structure ofFIG. 10is vertically flipped providing the first encapsulation102below the lead frame902. The tape904ofFIG. 10has been removed or peeled from the lead frame902exposing the first encapsulation102and the integrated circuit die1002ofFIG. 10.

The exposed portion of the integrated circuit die1002undergoes a thinning process whereby a portion of the exposed side of the integrated circuit die1002removed forming the first integrated circuit die208and the device cavity202in the first encapsulation102. The thinning process may be performed by a number of processes, such as die etching.

For illustrative purpose, the thinning process is shown forming the device cavity202having substantially the same width as the first integrated circuit die208, although it is understood that the device cavity202may have a different width than the width of the first integrated circuit die208. For example, the integrated circuit die1002may be locally thinned forming a localized recess (not shown) within the backside of the integrated circuit die1002.

Referring now toFIG. 12, therein is shown the structure ofFIG. 11in a forming phase of the cover206. The first device216mounts over the first integrated circuit die208in the device cavity202. The first passive side220attaches to the first non-active side212with an adhesive1202, such as a die-attach adhesive. The first upper interconnects222connect the first non-passive side218and the second side1004of the lead frame902ofFIG. 11.

The cover206is formed covering the first device216, the first upper interconnects222, and the first non-active side212filling in the device cavity202. The cover206partially covers the second side1004. The cover206may be formed in a number of ways, such as injection molding with a mold cap (not shown) over the first integrated circuit die208, the first upper interconnects222, and the lead frame902. The lead frame902may undergo formation of the external interconnects104, such as bending or stamping, and singulation forming the integrated circuit package system100.

Referring now toFIG. 13, therein is shown a perspective view of a wafer1302in a thinning phase. The perspective view depicts a back portion1304of the wafer1302. The wafer1302undergoes a thinning process from the back portion1304. The back portion1304does not have active circuitry or active elements thereon. The back portion1304may be thinned with a number of processes, such as lapping, grinding, or etching.

Referring now toFIG. 14, therein is shown the structure ofFIG. 13in a forming phase of a backside element1402. The backside element1402, also referred to as backside concealer, may be a number of different materials, such as a plastic layer, a polymer film, solder, copper, aluminum, or an silica filled epoxy mold compound. The backside element1402provides planar rigidity to the wafer1302.

The backside element1402may be formed at the back portion1304in a number of ways. For example, the plastic layer may be formed with screen printing and cured epoxy paste. Another example, the polymer film may be formed as a laminated layer. Yet another example, the backside element1402may be premolded.

Referring now toFIG. 15, therein is shown the structure ofFIG. 14in a singulating phase of the wafer1302. The wafer1302is in a vertically flipped orientation to that shown inFIG. 14displaying an active portion1502of the wafer1302. The active portion1502is on an opposing side of the back portion1304ofFIG. 14. The active portion1502includes active circuitry or active elements fabricated thereon.

The backside element1402does not cover the active portion1502. The wafer1302undergoes singulation depicted by singulation lines1504. A portion of the wafer1302within the singulation lines1504is an integrated circuit die1506.

Referring now toFIG. 16, therein is shown the structure ofFIG. 15in a separating phase of the integrated circuit die1506. A removal apparatus1602, such as a pick and place mechanism, removes the integrated circuit die1506from the wafer1302and moves the integrated circuit die1506to a lead frame1604. The integrated circuit die1506also has the backside element1402.

Referring now toFIG. 17, therein is shown a cross-sectional view of the lead frame1604ofFIG. 16along line17-17. The lead frame1604may be similar or substantially the same as the lead frame902ofFIG. 9. The lead frame1604is on a tape1702, such as a coverlay tape. The tape1702attaches to a first side1704of the lead frame1604and provides a planar surface between the first side1704and a space1706within the lead frame1604.

Referring now toFIG. 18, therein is shown the structure ofFIG. 17in a forming phase of the first encapsulation102. The integrated circuit die1506mounts on the tape1702with the backside element1402substantially coplanar with the first side1704of the lead frame1604.

The first lower interconnects214connect the first active side210and a second side1802of the lead frame1604. The tape1702secures the backside element1402to be coplanar with the first side1704of the lead frame1604.

The first encapsulation102is formed covering the integrated circuit die1506and the first lower interconnects214. The first encapsulation102partially covers the second side1802. The tape1702prevents the first encapsulation102from covering the first side1704. The first encapsulation102may be formed in a number of ways, such as injection molding with a mold cap (not shown) over the integrated circuit die1506, the first lower interconnects214, and the lead frame1604.

Referring now toFIG. 19, therein is shown the structure ofFIG. 18in a removing phase of the tape1702ofFIG. 18. The structure ofFIG. 18is vertically flipped providing the first encapsulation102below the lead frame1604. The tape1702has been removed or peeled from the lead frame1604exposing the first encapsulation102and the backside element1402.

Referring now toFIG. 20, therein is shown the structure ofFIG. 19in a forming phase of the first integrated circuit die208. The backside element1402undergoes a removal process forming the first integrated circuit die208and the device cavity202in the first encapsulation102. The removal process may be performed by a number of processes, such as etching, dissolving, or tape-assisted peeling.

Referring now toFIG. 21, therein is shown the structure ofFIG. 20in a forming phase of the cover206. The first device216mounts over the first integrated circuit die208in the device cavity202. The first passive side220attaches to the first non-active side212with an adhesive2102, such as a die-attach adhesive. The first upper interconnects222connect the first non-passive side218and the second side1802of the lead frame1604ofFIG. 19.

The cover206is formed covering the first device216, the first upper interconnects222, and the first non-active side212filling in the device cavity202. The cover206partially covers the second side1802. The cover206may be formed in a number of ways, such as injection molding with a mold cap (not shown) over the first integrated circuit die208, the first upper interconnects222, and the lead frame1604. The lead frame1604may undergo formation of the external interconnects104, such as bending or stamping, and singulation forming the integrated circuit package system100.

Referring now toFIG. 22, therein is shown an isometric view of a tape2202having an integral protrusion2204. The tape2202may be a coverlay tape having the integral protrusion2204. The integral protrusion2204is shown in a rectangular geometric configuration. The integral protrusion2204is shown having a planar surface2206. For illustrative purposes, the tape2202is shown with the integral protrusion2204, although it is understood that the tape2202may have more than one of the integral protrusion2204.

Referring now toFIG. 23, therein is shown a cross-sectional view of a lead frame2302. The lead frame2302may be similar or substantially the same as the lead frame902ofFIG. 9. The lead frame2302is on the tape2202with the integral protrusion2204within a space2304of the lead frame2302. The tape2202attaches to a first side2306of the lead frame2302and provides a planar surface between the first side2306and the space2304within the lead frame2302.

Referring now toFIG. 24, therein is shown the structure ofFIG. 23in a forming phase of the first encapsulation102. The first integrated circuit die208mounts over the integral protrusion2204. For illustrative purposes, a width of the integral protrusion2204is shown substantially the same as a width of the first integrated circuit die208, although it is understood that the width of the integral protrusion2204and the width of the first integrated circuit die208may be different. The first lower interconnects214connect the first active side210and a second side2402of the lead frame2302.

The first encapsulation102is formed covering the first integrated circuit die208, the first lower interconnects214, and the integral protrusion2204. The first encapsulation102partially covers the second side2402. The tape2202prevents the first encapsulation102from covering the first side2306. The first encapsulation102may be formed in a number of ways, such as injection molding with a mold cap (not shown) over the first integrated circuit die208, the first lower interconnects214, and the lead frame2302.

Referring now toFIG. 25, therein is shown the structure ofFIG. 24in a removing phase of the tape2202ofFIG. 24. The structure ofFIG. 18is vertically flipped providing the first encapsulation102below the lead frame2302. The tape2202has been removed or peeled from the lead frame2302exposing the first encapsulation102and the first non-active side212. The removal of the tape2202also removes the integral protrusion2204ofFIG. 24forming the device cavity202.

Referring now toFIG. 26, therein is shown the structure ofFIG. 25in a forming phase of the cover206. The first device216mounts over the first integrated circuit die208in the device cavity202. The first passive side220attaches to the first non-active side212with an adhesive2602, such as a die-attach adhesive. The first upper interconnects222connect the first non-passive side218and the second side2402of the lead frame2302ofFIG. 25.

The cover206is formed covering the first device216, the first upper interconnects222, and the first non-active side212filling in the device cavity202. The cover206partially covers the second side2402. The cover206may be formed in a number of ways, such as injection molding with a mold cap (not shown) over the first integrated circuit die208, the first upper interconnects222, and the lead frame2302. The lead frame2302may undergo formation of the external interconnects104, such as bending or stamping, and singulation forming the integrated circuit package system100.

Referring now toFIG. 27, therein is shown a cross-sectional view of the integrated circuit package system100ofFIG. 2in a forming phase of the first encapsulation102. A lead frame2702is on a tape2704, such as a coverlay tape. The lead frame2702may be similar or substantially the same as the lead frame902ofFIG. 9. The tape2704attaches to a first side2706of the lead frame2702and provides a planar surface between the first side2706and a space2708within the lead frame2702. A spacer2710, such as a tape segment, is placed on the tape2704in the space2708within the lead frame2702.

The first integrated circuit die208mounts over the spacer2710. For illustrative purposes, a width of the spacer2710is shown substantially the same as a width of the first integrated circuit die208, although it is understood that the width of the spacer2710and the width of the first integrated circuit die208may be different. The first lower interconnects214connect the first active side210and a second side2712of the lead frame2702.

The first encapsulation102is formed covering the first integrated circuit die208, the first lower interconnects214, and the spacer2710. The first encapsulation102partially covers the second side2712. The tape2704prevents the first encapsulation102from covering the first side2706. The first encapsulation102may be formed in a number of ways, such as injection molding with a mold cap (not shown) over the first integrated circuit die208, the first lower interconnects214, and the lead frame2702.

Referring now toFIG. 28, therein is shown the structure ofFIG. 27in a removing phase of the tape2704ofFIG. 27. The structure ofFIG. 27is vertically flipped providing the first encapsulation102below the lead frame2702. The tape2704has been removed or peeled from the lead frame2702exposing the first encapsulation102and the spacer2710.

Referring now toFIG. 29, therein is shown the structure ofFIG. 28in a removing phase of the spacer2710. The spacer2710undergoes a removal process exposing the first non-active side212of the first integrated circuit die208and forming the device cavity202in the first encapsulation102. The removal process may be performed by a number of processes, such as tape-assisted peeling or selective dissolving with a solvent.

Referring now toFIG. 30, therein is shown the structure ofFIG. 29in forming the cover206. The first device216mounts over the first integrated circuit die208in the device cavity202. The first passive side220attaches to the first non-active side212with an adhesive3002, such as a die-attach adhesive. The first upper interconnects222connect the first non-passive side218and the second side2712of the lead frame2702ofFIG. 28.

The cover206is formed covering the first device216, the first upper interconnects222, and the first non-active side212filling in the device cavity202. The cover206partially covers the second side2712. The cover206may be formed in a number of ways, such as injection molding with a mold cap (not shown) over the first integrated circuit die208, the first upper interconnects222, and the lead frame2702. The lead frame2702may undergo formation of the external interconnects104, such as bending or stamping, and singulation forming the integrated circuit package system100.

Referring now toFIG. 31, therein is shown a flow chart of an integrated circuit package system3100for manufacturing the integrated circuit package system100in an embodiment of the present invention. The system3100includes connecting an integrated circuit die with an external interconnect in a block3102; forming a first encapsulation having a device cavity with the integrated circuit die therein in a block3104; mounting a device in the device cavity over the integrated circuit die in a block3106; and forming a cover over the device and the first encapsulation in a block3108.

Thus, it has been discovered that the integrated circuit package system of the present invention furnishes important and heretofore unknown and unavailable solutions, capabilities, and functional aspects for improving yield, increasing reliability, and reducing cost of integrated circuit package system. The resulting processes and configurations are straightforward, cost-effective, uncomplicated, highly versatile, accurate, sensitive, and effective, and can be implemented by adapting known components for ready, efficient, and economical manufacturing, application, and utilization.