Circuit for controlling the base of a power transistor used in high tension switching

A first transistor (T.sub.2) is connected between the secondary winding of a pulse transformer (TC) and the base of a power transistor (T.sub.6) to be controlled. A second and third transistors (T.sub.3, T.sub.4) are arranged as a latch with dominant reset. The third transistor (T.sub.4) turns on the first (T.sub.2) during the interval of a control pulse, provided that the second (T.sub.3) is off. The second transistor further plays the role of a comparator and is associated with means (R.sub.16, R.sub.15, R.sub.14, R.sub.13, CTN) for tapping a voltage representative of the current delivered by the power transistor to a load and for comparing the said voltage with its base-emitter voltage. A resistor-capacitor circuit (R.sub.17 -C.sub.2) is arranged for supplying a negative bias once a capacitor (C.sub.2) has been energized by the pulse current and associated to a fourth transistor (T.sub.5) arranged for applying the said negative bias to the base of the power transistor during the intervals between two successive pulses.

BACKGROUND OF THE INVENTION 
The invention relates to the control of the base of a power transistor used 
in high tension switching. 
In choppers and chopped power supplies of a relatively low power, for 
example between 30 W and 500 W, a power transistor is generally used whose 
collector-emitter Vce bias is formed by the rectified AC mains and to the 
base of which are applied current pulses, of a frequency between 20 and 
100 KHz for example. This transistor operates under saturated ON condition 
during the interval of a pulse, and under off condition in the intervals 
between one pulse and the next pulse. 
To increase the switching frequency, while minimizing the losses and, when 
the circuit comprises a regulation loop, so as to obtain satisfactory 
regulation dynamics, it is important to minimize the saturation storage 
time of the transistor, which is often achieved by providing the base 
control device with a so-called "anti-saturation" diode circuit, which 
ensures that the transistor will not become saturated in the ON condition. 
DESCRIPTION OF THE PRIOR ART 
To this end, it has already been proposed, more especially in patents U.S. 
Pat. No. 3,566,158 and GB Pat. A No. 1 396 314, to use anti-saturation 
circuits for controlling the base of a transistor. However, for reasons 
which will be explained further on, it has proved desirable, in such 
control devices, to provide means for applying a reverse bias voltage to 
the transistor during the off condition. 
SUMMARY OF THE INVENTION 
A first aim of the invention is then to propose a circuit for controlling a 
transistor, using a relatively simple pulse transformer, having only a 
single primary winding and a single secondary winding and in which a 
reverse bias voltage supplied by the transformer is applied to the base of 
the transistor during turn off thereof. 
To arrive at this result, the control circuit of the invention uses a pulse 
transformer comprising a primary winding connected to the base of the 
power transistor by means of a first switching device which is made 
conducting for the duration of each pulse so as to obtain the ON condition 
of the transistor. This circuit is more particularly characterized in that 
it further comprises means for reversely biassing the base of the power 
transistor which comprise at least one capacitor, a circuit for charging 
said capacitor, from the secondary winding of the transformer, to a 
voltage corresponding to a turn off voltage of the transistor, and circuit 
means connecting said capacitor to the base of said transistor, this 
circuit means comprising a second switching device which is made 
conducting in the intervals between one pulse and the next pulse. 
Moreover, self-protection of the transistor requires the use of means for 
limiting the current which flows therethrough, so the comparison of this 
current with a reference voltage, which is generally obtained by means of 
a voltage source. When the current is tapped, at the level of the pulse 
transformer, the circuit is relatively complex, such is particularly the 
case in the circuit described in the patent U.S. Pat. No. 4,339,671 in 
which monitoring of the current supplied by the transistor is provided by 
means of a current transformer. It is clear that the addition of such 
current limiting means leads to relatively complex and expensive base 
control circuits. 
The invention has therefore also as its aim to integrate in the previously 
described base control circuit a limiter circuit of a such simpler and yet 
effective type. Thus, according to another feature of the invention, this 
circuit comprises means for tapping a voltage representative of a current 
which flows in the transistor, comparing it with a threshold and 
interrupting the conduction of said first switching device should said 
threshold be exceeded. 
According to another feature of the invention, the control terminal of said 
first switching device is connected to the output of a latch with dominant 
reset whose setting input received the rising and falling edges of the 
pulses transmitted by the secondary winding of the transformer and whose 
reset input is connected to the output of a threshold device which 
receives at one of its inputs a DC threshold voltage and at the other 
input a voltage representative of the current flowing in the transistor. 
According to a preferred embodiment of the invention, said first-switching 
device comprises a second transistor (the first transistor being the power 
transistor) and the latch with dominant reset comprises a third transistor 
connected by its collector to the base of the second transistor, and whose 
base is connected to its emitter through the emitter-collector junction of 
a fourth transistor playing the role of comparator, whose base is 
connected to means for tapping a voltage representative of the current 
delivered by the first transistor and comparing said voltage with its 
base-emitter voltage. Moreover, the circuit for charging said capacitor 
may advantageously comprise a resistor in series with the secondary 
winding of the transformer, and to the terminals of which is connected in 
parallel a circuit comprising in series a diode and said capacitor. This 
capacitor may further be connected to the emitter of a fifth transistor 
adapted for comparing the reverse voltage generated by the secondary of 
the transformer during the intervals between one pulse and the next pulse, 
with its own base-emitter voltage and for applying said negative bias 
voltage to the base of the first transistor during said intervals between 
one pulse and the next pulse. Thus, by means of a simple circuit, the 
invention allows the three previously mentioned functions to be obtained, 
namely anti-saturation, the generation of a negative base bias and 
limitation of the current delivered by the power transistor, by means of a 
small number of components and without using additional voltage sources.

DESCRIPTION OF THE PREFERRED EMBODIMENT 
The circuit shown in FIGS. 1 and 3 comprises a power chopping transistor 
T.sub.6 whose base is to be controlled, connected between the positive 
terminal V.sub.cc and the ground terminal ground of an appropriate DC 
voltage, with a load Z connected to its collector and a current measuring 
resistor R.sub.16 connected to its emitter. A switching assisting network 
Z.sub.6, known per se (FIG. 1) is illustrated in FIG. 3 as formed by a 
capacitor C.sub.6 in series with a resistor R.sub.19 and a diode D.sub.9 
in parallel across R.sub.19. This network is connected in parallel across 
the transistor T.sub.6. The control pulses, of period T (FIG. 2), with 
conduction duration t.sub.1 and non conduction duration t.sub.2, are 
applied to a switch T.sub.1 (FIGS. 1 and 3) connected in the primary 
winding n.sub.1 of a transformer TC supplied with a DC voltage T.sub.in. 
In the preferred embodiment of FIG. 3, switch T.sub.1 is a bipolar 
transistor whose base receives the control pulses through a bridge formed 
by resistors R.sub.1 and R.sub.2 ; a diode D.sub.2 connects resistor 
R.sub.1 to said base, whereas a diode D.sub.1 connects the collector of 
T.sub.1 to the common point between R.sub.1 and D.sub.2. A resistor 
R.sub.3 is connected in series with the primary winding of the 
transformer. In FIGS. 1 and 3, the hot point of the secondary winding 
n.sub.2 of transformer TC is connected to the base of transistor T.sub.6 
through a diode D.sub.5, a switch T.sub.2 and a diode D.sub.6. A diode 
D.sub.3 connects the common point between switch T.sub.2 and diode D.sub.6 
to the collector of transistor T.sub.6 and, with diode D.sub.6, forms, for 
this latter transistor T.sub.6, an anti-saturation device well known per 
se. A resistor R.sub.6 connects the base of transistor T.sub.6 to its 
emitter. Between the anode of diode D.sub.6 and the hot point of the 
secondary winding n.sub.2 there is connected in parallel across the 
circuit D.sub.5 T.sub.2 D.sub.6, a series circuit formed by a diode 
D.sub.4 and a resistor R.sub.4. 
Moreover, the secondary winding n.sub.2 of transformer T.sub.C is 
connected, on the other side, to the terminal ground through a resistor 
R.sub.17 to the terminals of which is connected in parallel a circuit 
comprising, in series, a capacitor C.sub.2 and a diode D.sub.8. 
Switch T.sub.2 is controlled by a latch B (FIG. 1) forming an RS flip-flop 
with R dominant which receives, at its set input S, the rising and 
following edge of the pulse transmitted by the diode D.sub.5 and a 
resistor R.sub.7 and whose reset input R is connected to the output of a 
comparator CO.sub.1. The negative input of this latter receives a DC 
threshold voltage S.sub.1 and, at its positive input, the voltage R.sub.16 
.times.IE is applied to the terminals of a resistor R.sub.16, connecting 
the emitter of transistor T.sub.6 to the terminal OV.sub.ce, IE being the 
emitter current of transistor T.sub.6. 
An AND gate, designated P in FIG. 1, has its output connected to the 
control input of switch T.sub.2 and its inputs connected respectively to 
the Q output of latch B and to resistor R.sub.7. 
A comparator CO.sub.2 has its positive input connected to the ground point 
of the secondary winding, whereas to its negative input is applied a DC 
threshold voltage -S.sub.2. The output of the comparator CO.sub.2 controls 
a switch T.sub.5, connected to the anode of the diode D.sub.6 and to the 
base of transistor T.sub.6 through a resistor R.sub.9 and to the 
connection between capacitor C.sub.2 and diode D.sub.8. 
In a preferred embodiment of FIG. 3, switches T.sub.2 and T.sub.5 are 
formed by bipolar transistors and comparators CO.sub.1 and CO.sub.2 are 
formed respectively by a transistor T.sub.3 (bipolar or MOS) and by 
transistor T.sub.5, T.sub.3 and T.sub.5 therefore playing the double role 
of comparator and switch. The threshold S.sub.1 which corresponds to the 
base-emitter voltage of transistor T.sub.3 is compared with a voltage 
defined by a voltage divider bridge connected in parallel across resistor 
R.sub.16 and which comprises a resistor R.sub.15 connecting the emitter of 
transistor T.sub.6 to the base of transistor T.sub.3 and a circuit 
connecting the base of transistor T.sub.3 to terminal ground, this circuit 
comprising in series an adjustable resistor R.sub.13 and a resistor with 
negative temperature coefficient NTC, chosen for compensating the 
variations in the base-emitter voltage of the transistor T.sub.3 with the 
temperature. In this circuit (R.sub.13,NTC) are connected in parallel a 
capacity C.sub.1 as well possibly as a resistor R.sub.14 shown with broken 
lines. 
Furthermore, according to a particularly advantageous embodiment of the 
invention, the base of the transistor T.sub.3 may be further connected, 
through a resistor R.sub.X, to a terminal +Vce brought to a voltage 
representative of the emitter-collector voltage of transistor T.sub.6, the 
purpose of this circuit being to correct the measurement of the emitter 
current of transistor T.sub.6 as a function of the amplitude of the 
collector-emitter voltage of transistor T.sub.6. This circuit, shown in 
FIG. 3, thus contributes to obtaining limitation of the power switched by 
transistor T.sub.6, independently of the power supply voltage through the 
resistor R.sub.16 (the current limitation threshold is then dependent on 
the voltage Vce), and independently of the temperature, through the 
negative temperature coefficient resistor NTC. 
The base of transistor T.sub.3 is further connected to the base of 
transistor T.sub.5 through a resistor R.sub.12, a capacitor C.sub.3 and 
the parallel circuit formed by a resistor R.sub.18 and a capacitor 
C.sub.4, whose common point with capacitor C.sub.3 is connected to the 
ground point of the secondary winding. 
Threshold S.sub.2 corresponds to the voltage V.sub.BE of transistor 
T.sub.5. The latch B of FIG. 1 is, in FIG. 3, formed by the two 
transistors T.sub.3 and T.sub.4 relooped by the resistor R.sub.10, whereas 
the gate P is formed by transistor T.sub.4 and resistors R.sub.7 and 
R.sub.5, R.sub.8, connected as shown in FIG. 3. 
In FIG. 2 there is shown: the voltage V.sub.1 at the terminals of the 
primary winding; the voltage V.sub.2 =V.sub.1 .multidot.(n.sub.2 /n.sub.1) 
at the terminals of the secondary windings; the current IB.sub.1 in the 
base of transistor T.sub.6 ; the current IC in the collector of transistor 
T.sub.6 and the base voltage V.sub.B of transistor T.sub.6. The first 
period t.sub.1 +t.sub.2 shown corresponds to normal operation; the second 
period corresponds to self-protection operation. 
Normal operation is as follows: 
At the beginning of the time interval t.sub.1, voltage V.sub.2 appears at 
the terminals of the secondary winding n.sub.2 and, consequently, latch B 
(FIG. 1) is latched at a logic level one. The output of the gate P is 
therefore at logic level one 1 and switch T.sub.2 closes. The 
anti-saturation device then applies a current IB.sub.1 to the base of 
transistor T.sub.6. The current I.sub.2 charges capacitor C.sub.2, which 
is transmitted through resistor R.sub.17 and diode D.sub.8 to the base of 
transistor T.sub.6 during the time interval t.sub.2 for negatively 
biassing the said base. There can be seen, because of this charge, a peak 
of the current IB.sub.1 at the beginning of the interval t.sub.1. (FIG. 2) 
This current peak accelerates the switching on of transistor T.sub.6. 
The output of comparator CO.sub.2 is at logic level zero and, consequently, 
switch T.sub.5 is open. 
At the end of time t.sub.1, the voltage V.sub.2 is cancelled out before 
being reversed and, consequently, the output of gate P passes to logic 
level zero and switch T.sub.2 opens. 
The current I.sub.2, so the voltage at the terminals of resistor R.sub.17, 
is reversed, which causes the output of comparator CO.sub.2 to pass to 
logic level one. 
The result is that switch T.sub.5 closes. 
The transistor T.sub.6 is in the off condition and its base is negatively 
biassed by the voltage -V.sub.p, transmitted through transistor T.sub.5 
and resistor R.sub.9. This negative biassing provides immunity to noise 
and improves the voltage resistance in the cut off condition. 
The base current IB.sub.2 corresponding to the accumulated charges is 
discharged, on the one hand through transistor T.sub.5 with an intensity 
limited by resistor R.sub.9 and on the other hand in the secondary winding 
through diode D.sub.4 and resistor R.sub.4, as long as voltage V.sub.2 is 
negative. Once the transformer is demagnetized, V.sub.2 returns to zero. 
The base voltage of transistor T.sub.6 is however maintained negative 
because of the voltage -V.sub.p. 
The self-protection operation is the following: 
If it happens that the emitter current I.sub.E of transistor T.sub.6 
reaches or exceeds S1/R16, the output of comparator CO.sub.1 passes to 1 
and resets the latch B. The result is that transistor T.sub.2 opens 
immediately and the current I.sub.2 is cancelled out despite the fact that 
V.sub.2 is maintained at a positive value for the whole time t.sub.1. 
The cancelling of I.sub.2 causes switch T.sub.5 to close and the base 
voltage of transistor T.sub.6, which is in the OFF condition, is 
maintained at a negative value. As soon as transistor T.sub.6 passes to 
the off condition, current I.sub.E decreases. So that the current limiting 
circuit which has just been described does not start oscillating, it is 
important for the effect of the emitter current overshoot to be memorized 
for the whole of the remainder of time t.sub.1. This result is obtained 
because latch B is adapted so as to be held at logic level zero as long as 
a new rising edge of voltage V.sub.2 is not applied thereto. 
If we now consider the practical circuit of FIG. 3, as soon as current 
limitation has taken place, resistor R.sub.12 and capacitors C.sub.3 
-C.sub.4 have a useful effect in accelerating the enabling of transistor 
T.sub.5, so the negative biasing of the base of transistor T.sub.6. In 
fact, resistor R.sub.12 and capacitor C.sub.3 play the role of a 
differentiator which applies a negative pulse providing a negative bias at 
the beginning of a falling edge of the positive half-wave. 
The memory function of the latch formed by T.sub.3 and T.sub.4 is provided 
by resistor R.sub.10 ; in fact, as soon as transistor T.sub.4 is off, the 
base potential of transistor T.sub.3 assumes, because of the current 
flowing through resistors R.sub.10,R.sub.13,NTC, a value such that 
transistor T.sub.4 is maintained in the off condition at the beginning of 
conduction of transistor T.sub.6. The action of transistor T.sub.3 (which 
normally plays also the role of comparator CO.sub.1) is therefore masked 
for a short time (of the order 1 .mu.s) by capacitor C.sub.1, resistor 
R.sub.12 and capacitor C.sub.3, which also form a low-pass filter 
eliminating the very rapid transitories, which prevents transistor T.sub.4 
from being latched off inopportunely under the effect of the substantial 
parasite current peaks likely to occur at the time of latching on. 
It can then be finally seen that there is provided, by means of a simple 
circuit formed with a small number of current and very inexpensive 
components and a single pulse transformer, without using any source of 
positive or negative low voltage, a base control circuit comprising 
insulation between the control circuit and the switched load (transformer 
TC) and fulfilling efficiently the functions of minimizing the storage 
time of the chopper transistor (anti-saturation diodes), of applying a 
negative base bias during disabling (source resistor R.sub.17, diode 
D.sub.8, capacitor C.sub.2, comparator CO.sub.2 and switch T.sub.5) and of 
self-protection of the transistor (measuring resistor R.sub.16, comparator 
CO.sub.1, latch B and switch T.sub.2). 
It goes without saying that, although the embodiment shown in FIG. 3 is 
preferred, different variants may be devised by a man skilled in that art, 
without departing from the scope and spirit of the invention.