EMBOSSED INDUCTOR DESIGN FOR MOTHERBOARD VOLTAGE REGULATORS TO INCREASE OVERALL SYSTEM POWER DENSITY

Embodiments disclosed herein include a motherboard. In an embodiment, the motherboard comprises a first layer with a first trace with a shape. In an embodiment, an insulating layer is provided over the first layer. In an embodiment, a second layer with a second trace with the shape is over the insulating layer. In an embodiment, the second trace is provided directly over the first trace.

TECHNICAL FIELD

Embodiments of the present disclosure relate to electronic systems, and more particularly to motherboard voltage regulators that increase overall system power density.

BACKGROUND

With increasing demand for higher performance of next generation central processing units (CPUs), power requirements for the CPUs increases. However, many of the data centers reuse platform and board form factors between generations in order to minimize the need for new server infrastructure. As CPU power requirements increase with a fixed system form factor, there is an utmost need to increase system power density. That is, systems need to support higher power demand within a restricted area.

Motherboard voltage regulators (MBVR) sourcing power to different CPU domains occupies significant board real estate. With increase in power demands, especially for CPU cores, a higher number of MBVR phases need to be supported from generation to generation. With each MBVR phase increment, additional power stage and output LC filters need to be added that linearly increases the board real estate. Output inductors, especially for high current rails such as VCCIN, occupy a third of the overall MBVR area on the board. Factors contributing to larger inductor sizes include equivalent series resistance (ESR) to improve quality factor, higher saturation current, and the like. For a multiphase MBVR, any reductions in real estate occupied by output inductors can significantly help increase overall system power density.

EMBODIMENTS OF THE PRESENT DISCLOSURE

Referring now toFIG.1, a plan view illustration of a board100, such as a motherboard, is shown, in accordance with an embodiment. The board100may include a substrate101, such as a printed circuit board (PCB). The substrate101may include a plurality of layers with conductive routing, insulating layers, and the like. In an embodiment, a motherboard voltage regulator (MBVR) may be provided on the substrate101. The MBVR may comprise power stages110, output inductors115, and output capacitors117. The power stages110and output inductors115may be grouped together in phases112. For example, four phases112are shown inFIG.1. That is, each phase includes one power stage110and one output inductor115. The number of output capacitors117may be different than the number of phases112. For example, three output capacitors117are shown inFIG.1.

As noted above, increasing power demands are forcing MBVRs to increase power density. This can be done through shrinking the component sizes. However, with respect to the output inductors115, smaller inductors result in decreases in the inductance and max saturation current limit that is not desirable for high power applications. Typically, the output inductors115are discrete components that are mounted on the board100. Using discrete components for the inductors115leads to several challenges, such as Z-height limitations, supply chain issues, fixed discrete values available, and a reduction in the space on the top or bottom layers for signal routing.

Accordingly, embodiments disclosed herein include integrated output inductors115. That is, the inductors115are integrated into the fabrication of the substrate101. This structure provides several benefits. For example, Z-height issues are no longer problematic since the inductor is within the thickness of the substrate101. Additionally, since the inductors115are fabricated as part of the substrate101manufacturing, there are minimal supply chain issues since discrete components no longer need to be acquired. Further, space is freed up on the top and bottom layers for signal routing.

The use of an integrated inductor115is also beneficial since it allows designers to more specifically control the inductance of the inductor115and fine tune the value to achieve optimum transient and steady state performance of MBVR. In some embodiments, the inductors115may be air core inductors. As used herein, an air core inductor115may refer to an inductor that includes an actual air core, or a core that is formed from standard board substrate materials (e.g., dielectric materials). In other embodiments, inductances can be increased by including magnetic cores within inductors115structure. The magnetic cores may be integrated into the inductors115through an embossing technique, as will be described in greater detail below.

Referring now toFIG.2, a plan view illustration of a board200is shown, in accordance with an embodiment. In an embodiment, the board200may comprise a substrate201. The substrate201may comprise laminated dielectric layers. Conductive traces220may be provided on the signal/conductive layers. For example, a top layer is covered by an S-shaped trace220. Additional S-shaped traces220may be provided below the top layer to form an inductor215. In an embodiment, the layers of the traces220may be electrically coupled together through vias222(shown with dashed lines to indicate they are below the trace220). The vias222may be provided on a first end and a second end of the trace220. That is, the traces220on different layers may be connected to each other electrically in parallel. While six vias222are shown on each end, it is to be appreciated that one or more vias222may be used based on current requirement.

In the illustrated embodiment, the shape of the trace220is an S-shaped trace. The S-shape provides turns that enable the formation of a desired level of inductance in the inductor215. While an S-shape is shown inFIG.2as one example, it is to be appreciated that other inductor architectures may be used as well, as will be described in greater detail below. In an embodiment the shape of the trace220in each layer may be substantially the same. For example, the traces220on different layers of the substrate201may have the same S-shape, and each traces220may be positioned directly over the underlying traces220.

In an embodiment, the traces220are different than the signaling traces203. In one instance, the difference between signaling traces203and traces220may be in a width dimension. That is, a width of the traces220may be wider than widths of adjacent signaling traces203. In an embodiment, the traces220may have a width that is up to approximately twice as large as the width of signaling traces203, up to approximately five times as large as the width of the signaling traces203, or up to ten times as large or larger than the width of the signaling traces203. A thickness of the traces220may also be greater than a thickness of adjacent signaling traces203.

Referring now toFIG.3A, an exploded view of a board300is shown, in accordance with an embodiment. The board300may include a plurality of layers331-335. While five layers are shown inFIG.3A, it is to be appreciated that the board300may comprise any number of layers. In an embodiment, the routing layers331-333may be separated from each other by insulating layers334and335. The routing layers331-333may include traces320A,320B, and320C. The traces320A,320B, and320C may have the same shape and be provided directly over each other. For example, the traces320A,320B, and320C have an S-shape inFIG.3A. In an embodiment, the traces320may be provided over the routing layers331-333. In other embodiments, the traces320may be embedded in the routing layers331-333.

The insulating layers334and335may include any suitable insulating material, such as an organic dielectric material. The insulating layers334may comprise the same material as the routing layers331-333. However, the insulating layers334may not include conductive traces320. In order to electrically couple the traces320A,320B, and320B together, vias (not shown) may pass through the insulating layers334and335. The vias may be provided at both ends of the traces320A,320B, and320C.

Referring now toFIG.3B, a cross-section of the board300along line B-B′ inFIG.3Ais shown, in accordance with an embodiment. The cross-sectional illustration depicts the layers331-335after they have been laminated over each other. As shown, insulating layer334is between routing layers331and332, and insulating layer335is between routing layers332and333. In the illustrated embodiment, the traces320A,320B, and320C are provided over the routing layers331,332, and333, respectively. However, it is to be appreciated that the traces320may be embedded in the respective routing layers331-333in some embodiments. When the traces320are over the routing layers331-333, the insulating layers334and335may conform to the shape of the traces.

In an embodiment, the cross-section of B-B′ is provided along one end of the traces320. The end of the traces320may comprise a plurality of vias322. The vias322may pass through the routing layers331,332and333, and through the insulating layers334and335. In the illustrated embodiment, a set of four vias322are shown. Though, it is to be appreciated that any number of vias322may be used in accordance with an embodiment. In an embodiment, the vias322may electrically couple the traces320together. For example, the traces320may be electrically coupled to each other in parallel. That is, both a first end (shown inFIG.3B) and a second end of the traces320may be electrically coupled together through vias322.

Referring now toFIG.3C, a cross-section of the board300along line C-C′ inFIG.3Ais shown, in accordance with an embodiment. As shown, the plurality of traces320A,320B, and320C are spaced apart from each other by the insulating layers334,335and the routing layers332and333. In such an embodiment, the traces320may be part of an inductor that is referred to as being an air core inductor. As noted above, air core inductors include inductors with dielectric cores, such as the insulating layers334,335, and the routing layers332and333.

As shown inFIG.3C, the traces320A,320B, and320C are directly over each other. That is, edges of the traces320A,320B, and320C are substantially aligned with each other. Further, the width of the traces320A,320B, and320C are substantially similar to each other. However, due to alignment tolerances in the manufacturing process, the edge of the traces320may be misaligned and/or the widths of the traces320may be non-uniform in some embodiments. That is, reference to being “substantially aligned” or “directly over” each other may include traces320that have at least 80% of their footprints overlapping, at least 90% of their footprints overlapping, at least 95% of their footprints overlapping, or at least 99% of their footprints overlapping.

Referring now toFIG.4A, an exploded view of a board400is shown, in accordance with an additional embodiment. In an embodiment, the board400may comprise a plurality of layers431-435that are stacked over each other. The layers431-435may include routing layers431-433and insulating layers434and435. The routing layers431-433may be substantially similar to the routing layers331-333described above with respect toFIG.3A. That is, the routing layers431-433may each comprise a trace420A,420B, or420C. The traces420may have any suitable shape for forming an inductor, such as an S-shape or the like. The traces420may be on the surface of the routing layers431-433, or the traces420may be embedded in the routing layers431-433.

In an embodiment, the insulating layers434and435may be organic dielectric layers. Further, the insulating layers434and435may include cutouts that are filled with magnetic blocks440. The magnetic blocks440may be any suitable magnetic material. In a particular embodiment, the magnetic blocks440may have a relative magnetic permeability that is approximately 200 or more at frequencies up to 1,200 KHz. For example, the magnetic blocks440may comprise a ferrite based material in some embodiments, such as a ferrite comprising manganese and zinc.

The magnetic blocks440may pass through substantially the entire thickness of the insulating layers434and435. The magnetic blocks440may also be provided at least partially within a footprint of the traces420A,420B, and420C. For example, the magnetic blocks440may span across three of the lengths of the traces420. However, the magnetic blocks440may be within an outer perimeter of the traces420. For example, ends of the traces420may be outside of the footprint of the magnetic blocks440. This allows for the vias (not shown inFIG.4A) to pass only through the routing layers431-433and the insulating layers434and435. Though, in some embodiments, vias may also pass through the magnetic blocks440.

The presence of the magnetic blocks440increases the inductance of the inductor in the board400. This allows for higher power density in the MBVR in some embodiments. Further, by increasing the power density, the size of the output inductor can be decreased while maintaining the same power delivery effect. This can reduce the footprint of the MBVR in some embodiments.

Referring now toFIG.4B, a cross-sectional illustration of the board400along line B-B′ inFIG.4Ais shown, in accordance with an embodiment. In an embodiment, the illustration ofFIG.4Bshows the board400after the layers431-435are bonded together. As shown, the magnetic blocks440extend over the three lengths of each of the traces420A,420B, and420C. That is, a width of the magnetic blocks440may be wider than a width of the traces420A,420B, and420C. Though, in other embodiments, the magnetic blocks440may have edges that are substantially aligned with the outer edges of the traces420A,420B, and420C.

In the illustrated embodiment, the magnetic blocks440conform to the shape of the traces420. However, in some embodiments, the traces420may be embedded in the routing layers431-433. In such instances, the magnetic blocks440may have top and bottom surfaces that are entirely flat, since there is no longer a need to conform to the shape of the traces420. This may expand the group of materials that can be used for the magnetic blocks440since the material does not need to be a material that is soft enough to conform to an undulating surface.

Referring now toFIGS.5A-5E, a series of cross-sectional illustrations depicting a process for forming an insulating layer with an embedded magnetic block is shown, in accordance with an embodiment. In the particular embodiment shown inFIGS.5A-5E, an embossing technique is used to form an opening into which the magnetic block is inserted. The magnetic block may be secured in the insulating layer with an adhesive in some embodiments.

Referring now toFIG.5A, a cross-sectional illustration of an insulating layer535is shown, in accordance with an embodiment. The insulating layer535may comprise an organic dielectric material. For example, the insulating layer535may be a buildup film or the like. The insulating layer535may have any suitable thickness. For example, the insulating layer535may have a thickness up to approximately 50 μm, or up to approximately 150 μm in some embodiments. Though, thicker insulating layers535may also be used in some embodiments. The insulating layer535may be substantially free from electrically conductive features. For example, no traces may be formed on and/or in the insulating layer535. Though, in some embodiments, one or more vias (not shown) may be provided through the insulating layer535. In other embodiments, vias through the insulating layer535are formed after the formation of the magnetic block.

Referring now toFIG.5B, a cross-sectional illustration of the insulating layer535during an embossing process is shown, in accordance with an embodiment. In an embodiment, a stamp560may be pressed into the insulating layer535. The stamp560may include a protrusion that extends substantially through a thickness of the insulating layer535. Though in some embodiments, the stamps560may not extend entirely through a thickness of the insulating layer535. In such embodiments, a portion of the insulating layer535may remain below the protrusion. As indicated by the arrow, the stamp560is pressed down into the insulating layer535. In an embodiment, the stamp560may be any rigid material, such as stainless steel or the like. The protrusion of the stamp560may have a form factor that is similar to the magnetic block that will be inserted into the insulating layer535.

Referring now toFIG.5C, a cross-sectional illustration of the insulating layer535during removal of the stamp560is shown, in accordance with an embodiment. As indicated by the arrow, the stamp560may be retracted vertically from the insulating layer535. The removal of the stamp560results in the formation of an opening538in the insulating layer535. The opening538may have substantially vertical sidewalls in some embodiments. Though, some embodiments may include an opening538that has sloped sidewalls in order to allow for easier removal of the stamp560. In the particular embodiment shown inFIGS.5A-5E, the opening538is formed with an embossing process. However, other fabrication processes (e.g., etching, laser ablation, etc.) may also be used in order to form the opening538in the insulating layer535.

Referring now toFIG.5D, a cross-sectional illustration of the insulating layer535after the opening538is fully formed is shown, in accordance with an embodiment. As described above, the opening538may have substantially vertical sidewalls, or the sidewalls may be sloped so that a bottom of the opening538is narrower than a top of the opening538. While a single opening538is shown in the insulating layer535, it is to be appreciated that multiple openings538may be provided in the insulating layer535. Such embodiments allow for the formation of a plurality of magnetic core inductors on the same board. Each of the openings538may be positioned in locations where overlying and underlying traces (not shown) will be formed in order to provide the conductive loops of the inductors. Multiple magnetic core inductors enables high power density multi-phase MBVRs.

Referring now toFIG.5E, a cross-sectional illustration of the insulating layer535after the insertion of a magnetic block540is shown, in accordance with an embodiment. In an embodiment, the magnetic block540may be inserted with a pick-and-place tool. That is, the magnetic block540may be a discrete component that is inserted into the opening538. In an embodiment, the magnetic block540may be a material that has a relative magnetic permeability of 200 or greater at frequencies up to 1,200 KHz. For example the magnetic block540may comprise a ferrite based material.

In an embodiment, the magnetic block540may be secured to the insulating layer535by an adhesive541. The adhesive541may line the sidewalls of the magnetic block540. In some embodiments, the adhesive541may surround an entire perimeter of the magnetic block540. In other embodiments, the adhesive541may be located at isolated locations of the magnetic block540(e.g., at the corners of the magnetic block540, at midpoints of each edge of the magnetic block540, etc.). While shown as having an adhesive541, it is to be appreciated that an adhesive541is optional depending on the design of the opening538. For example, the magnetic block540may be press fit into the opening538. That is, the opening538may be formed slightly smaller that dimensions of the magnetic block540, and the magnetic block540is pressed into the smaller opening538.

Referring now toFIGS.6A-6F, a series of plan view illustrations of different inductor shapes are shown, in accordance with various embodiments. While particular shapes are shown, it is to be appreciated that embodiments are not limited to any specific shape. More generally, any shaped trace that can be used to form an inductive component of an MBVR can be used in accordance with embodiments described herein.

Referring now toFIG.6A, a plan view illustration of a board600is shown, in accordance with an embodiment. In an embodiment, the board600comprises a substrate601. The substrate601may comprise a plurality of layers, similar to embodiments described in greater detail above. For example, the layers may include routing layers that are separated from each other by insulating layers. In an embodiment, each of the routing layers may include a trace620used to form an inductor615. In the embodiment shown inFIG.6A, the trace620has a single loop configuration. The single loop of the trace620may be rectangular shaped, square shaped, circular, or any other shaped loop.

Referring now toFIG.6B, a plan view illustration of a board600is shown, in accordance with an additional embodiment. As shown, the inductor615includes a trace620that includes a plurality of turns. For example, two turns are shown inFIG.6B. It is to be appreciated that increasing the number of turns may allow for an increased amount of inductance. The shape of the inductor615shown inFIG.6Bmay be referred to as having an S-shape. While the turns are formed with ninety degree angles, it is to be appreciated that the turns may include curves or non-ninety degree angles.

Referring now toFIG.6C, a plan view illustration of a board600is shown, in accordance with an additional embodiment. As shown, the inductor615comprises a U-shaped loop. That is, the loop of the inductor does not need to be based on a circular or a standard polygonal shaped structure (e.g., triangle, rectangle, pentagon, hexagon, etc.). More complex loop shapes, such as the U-shaped loop may allow for higher inductances within a smaller area, and provides enhanced power density to the MBVR.

Referring now toFIG.6D, a plan view illustration of a board600is shown in accordance with an additional embodiment. As shown, the inductor615comprises a solenoid type structure. That is, embodiments disclosed herein may include structures that are not traditional loop type structures.

Referring now toFIG.6E, a plan view illustration of a board600is shown, in accordance with an additional embodiment. As shown, the inductor615comprises a pair of pads621on the top surface of the substrate601. In an embodiment, the turns of the trace620are provided on an embedded layer of the substrate601(as indicated by the dashed lines). This opens up the surface of the substrate for additional routing purposes. In an embodiment, the inductor615shown inFIG.6Emay have an S-shape design. More particularly, each routing layer of the substrate601does not have to have a trace620with the same shape. For example, the top surface of the substrate601only includes pads621.

Referring now toFIG.6F, a plan view illustration of a board600is shown, in accordance with an additional embodiment. Similar to the embodiment shown inFIG.6E, the inductor615includes a buried loop structure with pads621on the top surface. The loop shown inFIG.6Fmay be U-shaped, or any other non-standard polygonal shape, such as those described in greater detail above.

In the embodiments described in greater detail above, emphasis was placed on inductor architectures that can be utilized in voltage regulator application (e.g., motherboard voltage regulator output inductors). However, embodiments are not limited to such topologies. Additionally, inductor architectures described herein can be used for many different applications. For example, noise filtering circuits on boards may utilize inductors such as those described in greater detail herein.

Referring now toFIG.7, a cross-sectional illustration of a computing system790is shown, in accordance with an embodiment. In an embodiment, the computing system790may comprise a board700. The board700may be similar to any of the boards described in greater detail herein. For example, the board700may comprise an integrated inductor715. For example, the inductor715may include a first trace720A and a second trace720B that is positioned over the first trace720A. The first trace720A may be a loop with a shape, and the second trace720B may be a loop with the same shape. The first trace720A may be electrically coupled to the second trace720B through vias (not shown).

In an embodiment, the first trace720A may be separated from the second traces720B by a magnetic block740. The magnetic block740may be a ferrite based material that increases the inductance of the inductor715. Though, an air core inductor may also be used in some embodiments.

In an embodiment, the inductor715may be part of an MBVR. For example, the MBVR may further comprise a power stage710and an output capacitor717. The power stage710and the output capacitor717may be discrete components mounted to the board700and/or integrated as part of the board700. While a single phase MBVR is shown inFIG.7, it is to be appreciated that multi-phase MBVRs may be formed with substantially similar processes and architectures.

In an embodiment, the board700may be coupled to a package substrate792by interconnects791. The interconnects791may comprise solder bumps, sockets, or the like. In an embodiment, the board700may comprise dielectric buildup layers (e.g., buildup film) with (or without) a core. The core may be an organic core, a glass core, or the like.

In an embodiment, the package substrate792may be coupled to one or more dies795by interconnects796. The interconnects796may be solder bumps, copper bumps, or any other suitable first level interconnect (FLI). In some embodiments, an interposer or the like (not shown) may be provided between the package substrate792and the dies795. The one or more dies795may comprise compute dies, such as a central processing unit (CPU), a graphics processing unit (GPU), an XPU, a system on a chip (SoC), a communications die, or the like. One or more dies795may also be memory dies or the like.

FIG.8illustrates a computing device800in accordance with one implementation of the invention. The computing device800houses a board802. The board802may include a number of components, including but not limited to a processor804and at least one communication chip806. The processor804is physically and electrically coupled to the board802. In some implementations the at least one communication chip806is also physically and electrically coupled to the board802. In further implementations, the communication chip806is part of the processor804.

The processor804of the computing device800includes an integrated circuit die packaged within the processor804. In some implementations of the invention, the integrated circuit die of the processor may be part of an electronic package with a motherboard that includes an MBVR that comprises an integrated output inductor that is an air core inductor or a magnetic core inductor, in accordance with embodiments described herein. The term “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip806also includes an integrated circuit die packaged within the communication chip806. In accordance with another implementation of the invention, the integrated circuit die of the communication chip may be part of an electronic package with a motherboard that includes an MBVR that comprises an integrated output inductor that is an air core inductor or a magnetic core inductor, in accordance with embodiments described herein.

In an embodiment, the computing device800may be part of any apparatus. For example, the computing device may be part of a personal computer, a server, a mobile device, a tablet, an automobile, or the like. That is, the computing device800is not limited to being used for any particular type of system, and the computing device800may be included in any apparatus that may benefit from computing functionality.

Example 1: a motherboard, comprising: a first layer with a first trace with a shape; a layer comprising insulating material over the first layer; and a second layer with a second trace with the shape over the insulating layer, wherein the second trace is provided directly over the first trace, and wherein the first trace is electrically coupled to the second trace by one or more vias through the layer.

Example 2: the motherboard of Example 1, wherein the one or more vias are at a first end of the shape and/or a second end of the shape.

Example 3: the motherboard of Examples 1-2, further comprising: a magnetic block embedded in the insulating layer between the first trace and the second trace.

Example 4: the motherboard of Example 3, wherein the magnetic block is secured to the insulating layer by an adhesive or, wherein the magnetic block is press fitted to the insulating layer.

Example 5: the motherboard of Examples 1-4, wherein the first trace and the second trace form an inductor that is integrated into the motherboard.

Example 6: the motherboard of Example 5, wherein the inductor is part of a voltage regulator or part of a noise filtering circuit.

Example 7: the motherboard of Examples 1-6, wherein the shape is an S-shape.

Example 8: the motherboard of Examples 1-6, wherein the shape is a U-shape.

Example 9: the motherboard of Examples 1-8, further comprising: a second insulator over the second layer; and a third layer with a third trace with the shape over the second insulating layer, wherein the third trace is provided directly over the first trace and the second trace.

Example 10: the motherboard of Examples 1-9, wherein the first trace and the second trace have a first width, and wherein an adjacent third trace has a second width, wherein the first width is greater than the second width.

Example 11: a motherboard, comprising: a voltage regulator, wherein the voltage regulator comprises: a power stage; an output inductor, wherein the output inductor is integrated into the motherboard, wherein being integrated into the motherboard comprises one or more conductive layers that are embedded within layers of the motherboard; and an output capacitor.

Example 12: the motherboard of Example 11, wherein a number of power stages is equal to a number of output inductors to provide a multi-phase voltage regulator.

Example 13: the motherboard of Example 11 or Example 12, wherein the output inductor comprises a first trace with a shape and a second trace with the shape directly over the first trace.

Example 14: the motherboard of Example 13, wherein the first trace is electrically coupled to the second trace in parallel.

Example 15: the motherboard of Example 13 or Example 14, further comprising: a magnetic block between the first trace and the second trace.

Example 16: the motherboard of Example 15, wherein the magnetic block comprises manganese and zinc.

Example 17: the motherboard of Examples 13-16, wherein the shape is an S-shape or a U-shape.

Example 18: a computing system, comprising: a board with a voltage regulator or noise filtering circuit that comprises an output inductor with a first trace, a second trace, and a magnetic block between the first trace and the second trace; a package substrate coupled to the board; and a die coupled to the package substrate.

Example 19: the computing system of Example 18, wherein the second trace is over the first trace, and wherein the first trace is electrically coupled to the second trace in parallel.

Example 20: the computing system of Example 18 or Example 19, wherein the computing system is part of a personal computer, a server, a mobile device, a tablet, or an automobile.