Apparatus for receiver with carrier frequency offset correction using phase and frequency information and associated methods

An apparatus includes a radio-frequency (RF) receiver for receiving an RF signal using a plurality of antennas. The RF receiver includes a demodulator to provide a switch signal to cause the RF receiver to use an antenna in the plurality of antennas. The RF receiver further includes a carrier frequency offset (CFO) correction circuit that uses an estimation of the carrier frequency offset and an estimation of phase differences to remove the carrier frequency offset.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is related to U.S. patent application Ser. No. 17/138,836, filed on Dec. 30, 2020, titled “Apparatus for Receiver with Carrier Frequency Offset Correction Using Frequency Information and Associated Methods”.

TECHNICAL FIELD

The disclosure relates generally to communication apparatus and associated methods. More particularly, the disclosure relates to apparatus for radio-frequency (RF), such as RF receivers, with carrier frequency offset (CFO) correction, and associated methods.

BACKGROUND

With advances in technology, an increasing number of circuit elements have been integrated into devices, such as integrated circuits (ICs). Furthermore, a growing number of devices, such as ICs, or subsystems, have been integrated into products. With developments such as the Internet of Things (IoT), this trend is expected to continue.

Some apparatus, such as IoT apparatus, operate at least in part wirelessly. In other words, such apparatus use radio frequency (RF) receivers (RX) and/or transmitters (TX). As persons of ordinary skill in the art understand, RF receivers typically suffer from carrier frequency offset (CFO).

FIG.1shows a conventional RF receiver that includes CFO estimation and removal.FIG.2shows details of a conventional CFO estimation circuit and a conventional CFO removal circuit. The circuitry inFIGS.1and2are known to persons of ordinary skill in the art. As such, the details of their operation is understood by persons of ordinary skill in the art and are therefore not further described here.

The description in this section and any corresponding figure(s) are included as background information materials. The materials in this section should not be considered as an admission that such materials constitute prior art to the present patent application.

SUMMARY

A variety of apparatus and associated methods for RF apparatus are contemplated according to exemplary embodiments. According to one exemplary embodiment, an apparatus includes an RF receiver for receiving an RF signal using a plurality of antennas. The RF receiver includes a demodulator to provide a switch signal to cause the RF receiver to use an antenna in the plurality of antennas. The RF receiver further includes a CFO correction circuit that uses an estimation of the carrier frequency offset and an estimation of phase differences to remove the carrier frequency offset.

According to another exemplary embodiment, an apparatus includes an RF receiver for receiving an RF signal using a plurality of antennas. The RF receiver includes a demodulator to provide a switch signal to cause the RF receiver to use an antenna in the plurality of antennas. The RF receiver includes a phase difference estimation (PDE) circuit to provide an estimation of phase differences in a set of phase samples, and a phase difference removal (PDR) circuit to remove phase differences based on the estimation of the phase differences in the set of phase samples to generate an output signal. The RF receiver further includes a CFO estimation circuit to use the output signal of the PDR circuit to provide an estimation of a carrier frequency offset, and a CFO removal circuit to use the estimation of the carrier frequency offset and the switch signal to remove the carrier frequency offset.

According to another exemplary embodiment, a method of correcting CFO in a radio-frequency (RF) receiver using a plurality of antennas includes using a demodulator to provide a switch signal to cause the RF receiver to use an antenna in the plurality of antennas, and using a CFO correction circuit to estimate the carrier frequency offset by using the switch signal, and to remove the carrier frequency offset.

DETAILED DESCRIPTION

The disclosure relates generally to communication apparatus and associated methods. More particularly, the disclosure relates to apparatus for RF communications, such as RF receivers, with CFO correction, and associated methods relating to such apparatus. In exemplary embodiments, CFO correction is provided for RF receivers and/or transceivers that use antenna diversity.

Antenna diversity, as known to persons of ordinary skill in the art, allows a receiver to use more than one antenna. Based on one or more criteria, such as one or more quality measures or metrics related to the signal received by the RF receiver, the RF receiver may at any given time use one antenna from among a set of antennas. As also known to persons of ordinary skill in the art, the choice of antenna for the RF receiver can change over time, for instance, in response to the changes in the one or more quality measures or metrics mentioned above.

Conventional RF receivers use a single antenna, for example, as shown inFIG.1, i.e., they do not use antenna diversity.FIG.3shows a plot10of chip time for such a receiver. More specifically, the plot10shows the chip phase of the receiver as a linear function of time, with no discontinuities or “jumps.” The CFO estimation and removal circuitry can take advantage of the linear phase as a function of time in a single-antenna receiver. The result is relatively straightforward CFO estimation and removal schemes.

When, however, two or more antennas are used, i.e., antenna diversity, non-contiguous “segments” of data for each antenna result in the plot of chip phase versus time. (Chips, also sometimes called samples, are constituent parts or fragments of a symbol. For example, a symbol consisting of 1010 has four chips of alternating ones and zeros.) Because of the use of multiple antennas, discontinuities are present in the function of chip (or sample) phase versus time.

FIGS.4-5show plots of chip phase for an RF receiver with antenna diversity according to an exemplary embodiment. The RF receiver may, for example, constitute the RF receiver20inFIG.6, which uses two antennas: antenna23and antenna26. Depending on one or more measures of received signal quality, such as received signal strength indicator (RSSI), the receiver20may use antenna23or antenna26. In other words, as the one or more measures of received signal quality using one antenna degrades, the receiver20switches to using another antenna, such as the antenna26. The switching between antennas may occur multiple times as a function of time.

Referring toFIG.4, a plot of chip phase as a function of time includes segments13and segments16. The segments13correspond to the chip phase using one antenna (e.g., the antenna23), and the segments16correspond to the chip phase using another antenna (e.g., the antenna26). As part of CFO correction, the RF receiver20uses the segments from the antenna that provides better measure(s) of received signal quality.

For example, asFIG.5shows, the segments16may be used.FIG.5shows a plot of the chip phase, which includes the segments16, as a function of spliced time. In other words, the segments13inFIG.4are removed, and the segments16are joined to arrive at the chip phase plot inFIG.5. The splicing (removing the segments13and joining together the segments16results in the discontinuities or “jumps” in the plot of chip phase inFIG.5. The term “antenna switch” refers to switches relative to spliced time and not normal time. In other words, inFIG.5, there are two such switches shown which correspond to the chip phase discontinuities, i.e., the two discontinuities between the segments16.

Given that frequency is the derivative of phase with respect to time, differences in the characteristics of the reference crystals and other non-idealities give rise to carrier frequency offsets (CFO). This phenomenon is further exacerbated when noisy phase values are present. CFO can cause a variety of undesirable outcomes. As an example, CFO can cause a +1 symbol, which ordinary is at the +1 point on the unit circle, to rotate around the unit circle. Other effects of CFO are understood by persons of ordinary skill in the art and are not discussed further.

When switching antennas in an antenna diversity receiver, multi-symbol sequences of chips are composed of multiple discontinuous intervals, as discussed above. In order to correct the CFO in this situation, in exemplary embodiments the CFO parameters are calculated relatively reliably. Ideally, CFO calculation precision would not be a limiting factor in RF receiver sensitivity. With antenna diversity, these CFO correction techniques provide a sensitivity versus frequency offset curve that is within a fraction of a decibel of the ideal non-CFO case.

Apparatus and methods according to various embodiments provide CFO correction, as discussed above. CFO correction according to exemplary embodiments is effective when the phase measurement for each in-phase (I) and quadrature (Q) sample in the RF receiver is noisy. In such circumstances, simpler schemes (e.g., those used for single-antenna systems) may fail altogether, or may not function or function well with phase locked loops (PLLs) having 20 parts-per-million (ppm) or worse accuracy or precision.

Noisy phase values tend to be pronounced in some particular applications, such as Internet of Things (IoT) apparatus (e.g., ICs) and systems. Such systems tend to have relatively stringent constraints for both power consumption and cost. Using CFO correction techniques according to various embodiments in such systems provides an advantage over conventional approaches.

In exemplary embodiments, discontinuities in phase are estimated and removed separately. Accordingly, CFO correction in such embodiments uses two separate loops instead of one loop used conventionally. The following description provides examples of such embodiments.

FIG.6shows a circuit arrangement for an RF receiver20according to an exemplary embodiment. The RF receiver20includes CFO correction circuitry, as described below in detail. The RF receiver20uses two antennas23and26, respectively, via the switch29. The switch29is controlled by demodulator circuit59, i.e., via a control signal provided by the demodulator59, the switch29provides signals received by either the antenna23or the antenna26to the low noise amplifier (LNA)32. The choice of antenna may be made as described above, i.e., based on one or more criteria, such as one or more quality measures or metrics related to the signal received by the RF receiver.

The LNA32amplifies the signal received the switch29. The amount of amplification depends on a gain signal provided by the automatic gain control (AGC) circuit62. The LNA32provides an amplified signal to the IQ mixer38. The IQ mixer mixes the amplified signal with a local oscillator (LO) signal from LO circuit35to generate a down-converted signal.

The down-converted signal is provided to programmable gain amplifier (PGA) circuit41. In response to the gain signal from the AGC circuit62, the PGA circuit41amplifies the down-converted signal to generate an input signal for the IQ analog-to-digital converter (ADC) circuit44.

The ADC circuit44converts the IQ signals from the PGA circuit41into digital IQ signals. The digital IQ signals are provided to the decimation, filtering, and sampling rate conversion (SRC) circuit50provides, as the name suggests, decimation, filtering, and SRC operations on the signal received from the ADC circuit44. Details of the decimation, filtering, and SRC operations depend on factors such as design and operation specifications for a given application, cost, complexity, modulation schemes, frequency plans, etc., as persons of ordinary skill in the art will understand.

The CFO correction circuit52in the RF receiver20includes CFO estimation circuit53and CFO removal circuit56. The output of the decimation, filtering, and SRC (DFS) circuit50fees the input of the CFO correction circuit52. The output of the CFO estimation circuit53feeds the input of CFO removal circuit56, while the output of the CFO removal circuit56drives the input of demodulator circuit59(as described below in detail).

As described below, the CFO estimation circuit53provides an estimation of the CFO to the CFO removal circuit56in response to control signals from the demodulator59. The control signals provide the antenna or chip phase switching points (seeFIGS.4-5).

The CFO removal circuit56removes (or nearly removes, in a practical implementation with non-ideal circuitry, as persons of ordinary skill in the art will understand) the CFO. Put another way, one of the design goals of the CFO estimation circuit53and CFO removal circuit make the multi-antenna case (seeFIG.5) to appear similar to the single-antenna case (seeFIG.3).

FIG.7shows a circuit arrangement for CFO correction circuit52according to an exemplary embodiment. More specifically, the figure illustrates the details of the CFO estimation circuit53and the CFO removal circuit56used in the receiver ofFIG.6. The CFO estimation circuit and the CFO removal circuit56make the multi-antenna case appear like a single-antenna case by removing the “jumps” or discontinuities (see, for example,FIG.5).

Referring again toFIG.7, the CFO removal circuit80includes a multiplier80, which receives the I and Q (IQ_IN) signals, which are provided to the CFO correction circuit52from the decimation, filtering, and SRC (DFS) circuit50. The multiplier80multiplies the output of a D-latch98(described below) with the IQ_IN signals to generate the output I and Q (IQ_OUT) signals. The IQ_OUT signals are provided to the demodulator59(seeFIG.6).

Referring again toFIG.7, the demodulator59provides control signals to various blocks in the CFO correction circuit52via the register block137. For example, the demodulator59, via register block137, provides control signals to the derotator83, the demultiplexer (DeMUX)86, and the averaging circuit128. The control signals from the demodulator59indicate, for example, the switching points from one antenna to another, e.g., from the antenna23to the antenna26(seeFIG.6). Note that averaging refers to the sum of N elements divided by N, where N represents a positive integer greater than unity. The derotator is essentially adding/subtracting a fixed phase sequence (determined by the specification of the given wireless standard or protocol according to which the RF receiver operates) so that all chips have ideally the same phase.

Referring again toFIG.7, the output of the multiplier80are fed to derotator83in the CFO estimation circuit53. Disregarding CFO effects, the derotator83ensures that all chips have the same phase (or nearly the same phase, in a practical real-life implementation). In response to control signals from the demodulator59(provided via the register block circuit137), the DeMUX86provides the output of the derotator83to either the averaging circuit89, the averaging circuit107, or the averaging circuit116, depending on for which of the intervals where a particular antenna is used the CFO estimation is performed. The register block holds configuration information and control signals from the demodulator59and provides those signals to various blocks in the CFO estimation circuit53.

The averaging circuit89, the averaging circuit107, and the averaging circuit116are part of three branches or loops in the CFO estimation circuit53, each of which includes phase averaging, followed by conversion of phase to frequency, followed by frequency averaging. In the first branch, the averaging circuit89averages the phase output signals of the derotator83and provides the resulting signals to the multiplier95.

The averaging performed by the averaging circuit89(and similarly by the averaging circuits107and116) improve the signal to noise ratio (SNR) of the phase samples. The multiplier95together with delay circuit92provide a phase to frequency conversion. The frequency output signals of the multiplier95are provided to the averaging circuit101. The averaging circuit101provides averaging of the frequency values and provides a CFO value, CFO1.

The second branch (phase averaging circuit107, phase to frequency converter (multiplier110and delay circuit104), and frequency averaging circuit113operate similarly to provide a CFO value, CFO2. Finally, the third branch (phase averaging circuit116, phase to frequency converter (multiplier122and delay circuit119), and frequency averaging circuit125operate similarly to provide a CFO value, CFO3.

The CFO1, CFO2, and CFO3values, corresponding to the time periods when a particular antenna is used, are shown inFIG.9. Referring again toFIG.7, the number of phase and/or frequency samples are averaged by the averaging circuits in the three branches may be configured or programmed, for example, by the demodulator59or a controller, etc. As persons of ordinary skill in the art will understand, other numbers of circuit branches, such as two or more than three, may be used, depending on factors such as design and performance specifications, cost, target performance, target markets, etc.

The outputs of the three branches, i.e., the outputs of frequency averaging circuits101,113, and123, respectively, are provided as inputs to the averaging circuit128. Under the control of the demodulator59, via the register block137, the averaging circuit128improves the SNR of the frequency samples.

The Coordinate Rotation Digital Computer (Cordic)131converts the IQ samples from the averaging circuit128into frequency samples, and then creates IQ samples with estimated constant frequency. The exponentiation block134converts the phase increment received from the CORDIC131to a complex vector of phase increment. The exponentiation block134may be implemented using a CORDIC, as desired. In other words for each phase Ph the CORDIC calculates Exp(i*Ph)=cos(Ph)+i*sin(Ph), where i is the imaginary unit or square root of −1. In exemplary embodiments, the exponentiation block134may be implemented using a CORDIC, as desired.

The output of the exponentiation block134(coefficients of rotation) is provided to the D-latch98. A clock signal, labeled “Iteration CLK,” clocks the latch98(the demodulator or a controller (not shown) may provide the clock signal to the latch98). The output of the latch98is provided as an input to the multiplier80. Before each time the latch98is clocked, via the register block137, the demodulator59increases the level of filtering by increasing the number of averaging operations performed by the averaging circuit128, i.e., by increasing N.

FIGS.8A-8Bshow flow diagrams for a method of CFO correction according to an exemplary embodiment. More specifically,FIGS.8A-8Billustrate flow diagrams for the exemplary embodiments ofFIGS.6-7. Referring toFIG.8A, at153, a packet is detected by the RF receiver (e.g., the receiver inFIG.6). At156, the CFO is estimated and stored (e.g., CFO1inFIG.9).

At159, a check is made whether the antenna switch count exceeds a threshold, N, where N denotes a positive integer. If not, control returns to156. If the count exceeds N, however, at162the CFOs are averaged, and at165the CFO is removed. Note that the number of antenna switches multiplied by switch time cannot exceed the preamble time. Therefore, as merely one example, in the case of the Zigbee specification, there are 8 zero symbols in the preamble. If each switch duration is 1 symbol, 8/(number of antennas) is the absolute maximum value for N, and the switch counter will determine when the loop is exited.

FIG.8Billustrates details of estimating and storing CFO at156inFIG.8A. Referring toFIG.8B, at156A, IQ symbol derotation is performed. At156B, fixed phase averaging is performed. At156C, frequency is derived from the phase samples. At156D, frequency averaging is performed.

FIG.10shows a circuit arrangement for an RF receiver20according to an exemplary embodiment. The RF receiver20inFIG.10is similar to the RF receiver20inFIG.6, but differs in the CFO correction circuit52. Referring toFIG.10, the CFO correction circuit includes the CFO estimation circuit53, the CFO removal circuit56, and a phase delta removal or phase difference removal (PDR) circuit175.

FIG.11shows a circuit arrangement for CFO correction according to an exemplary embodiment. More specifically,FIG.11shows details of the CFO correction circuit52inFIG.10. Referring again toFIG.11, the CFO removal circuit56is the same as that shown inFIG.7.

Furthermore, the CFO estimation circuit53inFIG.11is similar to the CFO estimation circuit inFIG.7. In the embodiment inFIG.11, however, one branch or loop is used (rather than three inFIG.7). More specifically, the embodiment inFIG.11uses the first branch shown inFIG.7, with the averaging circuit101omitted.

In addition, the exponentiation circuit134is used like inFIG.7. Unlike the embodiment inFIG.7, the output of the CORDIC131inFIG.11drives an input of the PDR circuit175.

The PDR circuit175includes a DeMUX178that receives the output of the CORDIC131. In response to a control signal from the demodulator (not shown) provided via the register block137, the DeMUX176provides its input signal either to a multiplier178or to a multiplexer (MUX)181.

If the input signal of the DeMUX176is provided to the multiplier178, then the multiplier178multiplies the frequency samples by 32, which denotes the number of chips per symbol. As persons of ordinary skill in the art will understand, however, the number of chips per symbol may in other embodiments differ from 32, depending on factors such as design and performance specifications, etc. Furthermore, multiplying by 32 assumes switching antennas for each symbol, thus every 32 chips in the case of the Zigbee example discussed above.

As another option, depending on the control signal from the register block137, the DeMUX176provides its input signal to the MUX181without modification. In effect, the DeMUX circuit176determines whether to use unmodified frequency samples or use frequency samples that have been multiplied by the number of chips per symbol.

In response to a control signal from the demodulator (not shown) provided via the register block137, the MUX181provides one of its input signals to the exponentiation circuit134. As noted above, the exponentiation block134may be implemented using a CORDIC, as desired.

FIG.12A-12Cshow flow diagrams for a method of CFO correction according to an exemplary embodiment. More specifically,FIGS.12A-12Cillustrate flow diagrams for CFO correction in the exemplary embodiments ofFIGS.10-11.

Referring toFIG.12A, at153, a packet is detected by the RF receiver (e.g., the receiver inFIG.10). At203, the CFO is estimated and stored (e.g., CFO1inFIG.9). At206, the phase differences are removed. At209, non-constant frequency removal is performed. At212, a check is made whether the iteration count exceeds a threshold, N, where N denotes a positive integer. If not, control returns to203. If the count exceeds N, however, CFO correction concludes.

FIG.12Billustrates details of estimating and storing CFO at203inFIG.12A. Referring toFIG.12B, at203A, IQ symbol derotation is performed. At203B, fixed phase averaging is performed. At203C, frequency is derived from the phase samples. At203D, frequency averaging is performed.FIG.12Cillustrates details of removing phase differences at206inFIG.12A.

At206A, a check is made whether the iteration count equals the chip number for each antenna switch time, i.e., (32) in the case of switching for every symbol for the Zigbee example. If so, the frequency samples are multiplied by the number of chips per symbol (e.g., 32). If not, control passes to206C, where the results are combined. At206D, a check is made whether the iteration count exceeds the number of total chips. If yes, the process continues (e.g., to209inFIG.12A), otherwise control returns to206A.

The RF receiver20shown inFIG.10may be used with CFO correction circuits52other than the exemplary embodiment shown inFIG.11.FIG.13shows a block diagram of such an alternative CFO correction circuit52. The CFO removal circuit inFIG.13is the same as shown inFIG.11, and described above.

The CFO estimation circuit53is similar to the counterpart circuit show inFIG.11, but in the embodiment inFIG.13, the PDR circuit175(described below in detail) is coupled between the output of the multiplier95and the input of the averaging circuit128. More specifically, the output of the multiplier95feeds an input of the PDR circuit175, and the output of the PDR circuit175feeds the input of the averaging circuit128.

Although it operates on frequency samples, functionally, the PDR circuit175performs phase difference removal. Phase difference removal includes zeroing (via the binary 0 input to the MUX220) some frequency samples. The PDR circuit175includes a counter223and a MUX220. One input of the MUX220receives a binary logic 0 level. The other input of the MUX220receives the output of the multiplier95.

The counter223provides the select or control signal of the MUX220. More specifically, under control of the demodulator59, via the register block137, the counter223counts in response to a clock signal labeled “Sample CLK.” The counter223is programmed by the register block134because the position of the samples to zero out (set to zero by virtue of the binary 0 input to the MUX220) depends on the position of the antenna switch (e.g., the switch29inFIG.10) and the current iteration number (the number of times information has been processed via the loop in the CFO correction circuit52).

Essentially, the PDR circuit175zeros out (by virtue of the binary 0 applied to an input of the MUX220) some frequency samples. More specifically, via the select signal from the demodulator59(provided via the register block134), the MUX220provides a binary 0 as its output when there is a “jump” or discontinuity. The counter223is programmed by the register block137because the position of the samples to zero out depends on the position of the antenna switches, and the iteration number (how many cycles of the “Iteration CLK” signal have been applied to the latch98). The demodulator59provides both of those quantities to the register block137.

FIG.14A-14Cshow flow diagrams for a method of CFO correction according to an exemplary embodiment. More specifically,FIGS.14A-14Cillustrate flow diagrams for CFO correction in the exemplary embodiments ofFIGS.10and13.

Referring toFIG.14A, at153, a packet is detected by the RF receiver (e.g., the receiver inFIG.10). At223, an initial frequency calculation is made. At236, antenna switch values are nulled (set to 0, as described above). More specifically, differential phase values (frequency values) are calculated and values corresponding to transitions are nulled. At239, the CFO is estimated and stored.

At242, a check is made whether the iteration count exceeds a threshold, N, where N denotes a positive integer. If so, CFO correction concludes. Otherwise, control passes to248, where the null points are changed. Thereafter, at245, the number of averaging operations, M, is increased, where M denotes a positive integer, and control returns to233.

FIG.14Billustrates details of the initial frequency calculation performed at233inFIG.14A. Referring toFIG.14B, at233A, the chips are derotated. At233B, an M-sample phase averaging operation is performed. At233C, frequency values are derived from the phase samples.

FIG.14Cillustrates details of the CFO estimation and removal performed at239inFIG.14A. At239A, frequency averaging is performed. At239B, constant frequency removal is performed.

FIG.15shows a circuit arrangement for an RF receiver20according to an exemplary embodiment. The RF receiver20inFIG.15is similar to the RF receiver20inFIG.10, but differs in the CFO correction circuit52. Referring toFIG.15, the CFO correction circuit includes the CFO estimation circuit53, the CFO removal circuit56, the PDR circuit262, and a phase delta estimation or phase difference estimation (PDE) circuit260.

FIG.16shows a circuit arrangement for CFO correction according to an exemplary embodiment. More specifically,FIG.16shows details of the CFO correction circuit52inFIG.15. Referring again toFIG.16, the CFO removal circuit56is the same as that shown inFIG.7.

Furthermore, the CFO estimation circuit53inFIG.16is similar to the CFO estimation circuit inFIG.7. In the embodiment inFIG.16, however, one branch or loop is used (rather than three inFIG.7). More specifically, the embodiment inFIG.16uses the first branch shown inFIG.7, with the averaging circuit101, the derotator83, and the DeMUX86omitted. Thus, the CFO estimation circuit53inFIG.16includes the phase averaging circuit279, phase to frequency converter circuit (including the multiplier285and the delay circuit282), the frequency averaging circuit288, the CORDIC131, and the exponentiation circuit134.

Referring again toFIG.16, the PDE circuit260is similar to the CFO estimation circuit53, but with the following differences. First, no second averaging circuit (averaging circuit288in the CFO estimation circuit53) is used. Second, instead of one branch or loop in the CFO estimation circuit53, the PDE circuit260uses two branches or loops, i.e., two circuit branches that operate on and modify the output of the derotator83, as provided by the MUX86(in response to control signals from the register block137), and provide the results to the PDR circuit262. The MUX86also provides the output of the derotator83to the PDR circuit262(in response to control signals from the register block137). The first branch includes the averaging circuit89A, the multiplier95A, the delay circuit92A, the CORDIC131A, and the exponentiation circuit134A. The second branch includes the averaging circuit89B, the multiplier95B, the delay circuit92B, the CORDIC131B, and the exponentiation circuit134B.

Third, the DeMUX86receives the output of the derotator83, and under the control of the demodulator59(via the register block134) provides that output to one of the two branches described above. The derotator83receives its input from the output of the multiplier80. Fourth, the phase to frequency converters in each of the first and second branches operate on k samples instead of a fixed sample (hence the use of the notation Z-k for the delay circuits92A and92B) in response to the control signals137D and137C (provided by the demodulator59via the register block137), respectively.

The PDR circuit262is similar to the CFO removal circuit56, with the following differences. First, the PDR circuit262uses a MUX276that under the control of the demodulator59(via the register block134) provides one of its three input signals to the CFO estimation circuit53.

Second, the PDR circuit262two multipliers,273A and273B. The multiplier273A multiplies the output of the exponentiation circuit134A with the output of the multiplier273B, and provides the resulting output to the MUX276. The multiplier273B multiples the output of the exponentiation circuit134B with the output of the derotator83(as provided by the DeMUX86) and provides the resulting output to the MUX276as a second input.

Finally, the output of the derotator83(as provided by the DeMUX86) drives a third input of the MUX276. The three inputs of the MUX276correspond to three intervals, the first corresponding to the output of the derotator83without any modification, the second having been rotated once (the output of the multiplier273B), and the third having been rotated twice (the output of the multiplier273A). As persons of ordinary skill in the art will understand, other numbers of circuit branches may be used, depending on factors such as design and performance specifications, cost, target performance, target markets, etc.

FIG.17A-17Cshow flow diagrams for a method of CFO correction according to an exemplary embodiment. More specifically,FIGS.17A-17Cillustrate flow diagrams for CFO correction in the exemplary embodiments ofFIGS.15-16.

Referring toFIG.17A, at153, a packet is detected by the RF receiver (e.g., the receiver inFIG.15). At303, IQ symbol derotation is performed. At309, phase differences are estimated and removed. At312, the CFO is estimated and stored.

At315, a check is made whether the iteration count exceeds a threshold, N, where N denotes a positive integer. If so, CFO correction concludes. Otherwise, control passes to306, where the number of averaging operations (M and N) are increased, and control passes to303.

FIG.17Billustrates details of the estimation and removal of phase differences performed at309inFIG.17A. Referring toFIG.17B, at309A, the phase difference is calculated as the mean (average) phase of N samples after the antenna switch point minus the mean (or average) phase of N samples before the antenna switch point.

At309B, a constant phase removal operation is performed. At309C, a check is performed whether the iteration count exceeds the number of antenna switches. If so, control passes to312(seeFIG.17A), otherwise, control returns to309A (i.e., another iteration is performed).

FIG.17Cillustrates details of the estimation and removal of the CFO performed at312inFIG.17A. Referring toFIG.17B, at312A, an M-sample phase averaging is performed. At312B, frequency values are derived from the averaged phase values. At312C, an averaging operation is performed on the frequency values. At312D, constant frequency removal is performed.

Receivers according to exemplary embodiments may be used in a variety of communication arrangements, systems, sub-systems, networks, etc., as desired.FIG.18shows a system500for radio communication according to an exemplary embodiment. The system includes RF receivers5, as described above.

System500includes a transmitter515, coupled to antenna10A. Via antenna10A, transmitter515transmits RF signals. The RF signals may be received by receiver20B via antenna10B. In addition, or alternatively, transceiver520A and/or transceiver520B might receive (via receivers20C and20D, respectively) the transmitted RF signals.

In addition to receive capability, transceiver520A and transceiver520B can also transmit RF signals. The transmitted RF signals might be received by receiver20, either in the stand-alone receiver (20B), or via the receiver circuitry of the non-transmitting transceiver (20C or20D).

Other systems or sub-systems with varying configuration and/or capabilities are also contemplated. For example, in some exemplary embodiments, two or more transceivers (e.g., transceiver520A and transceiver520B) might form a network, such as an ad-hoc or mesh network. As another example, in some exemplary embodiments, transceiver520A and transceiver520B might form part of a network, for example, in conjunction with transmitter515.

RF receivers, such as RF receiver20described above, may be used in a variety of circuits, blocks, subsystems, and/or systems. For example, in some embodiments, such RF receivers may be integrated in an IC, such as a microcontroller unit (MCU).FIG.19shows a block diagram of an IC550according to an exemplary embodiment.FIG.20is similar to the embodiment ofFIG.19, and shows an IC550that, in addition to the RF receiver5, also includes RF transmitter515. Thus, the embodiment inFIG.20has RF transceiver capability.

Referring toFIG.19, IC550constitutes or includes an MCU. IC550includes a number of blocks (e.g., processor(s)565, data converter605, I/O circuitry585, etc.) that communicate with one another using a link560. In exemplary embodiments, link560may constitute a coupling mechanism, such as a bus, a set of conductors or semiconductor elements (e.g., traces, devices, etc.) for communicating information, such as data, commands, status information, and the like.

IC550may include link560coupled to one or more processors565, clock circuitry575, and power management circuitry or power management unit (PMU)580. In some embodiments, processor(s)565may include circuitry or blocks for providing information processing (or data processing or computing) functions, such as central-processing units (CPUs), arithmetic-logic units (ALUs), and the like. In some embodiments, in addition, or as an alternative, processor(s)565may include one or more DSPs. The DSPs may provide a variety of signal processing functions, such as arithmetic functions, filtering, delay blocks, and the like, as desired.

Clock circuitry575may generate one or more clock signals that facilitate or control the timing of operations of one or more blocks in IC550. Clock circuitry575may also control the timing of operations that use link560, as desired. In some embodiments, clock circuitry575may provide one or more clock signals via link560to other blocks in IC550.

In some embodiments, PMU580may reduce an apparatus's (e.g., IC550) clock speed, turn off the clock, reduce power, turn off power, disable (or power down or place in a lower power consumption or sleep or inactive or idle state), enable (or power up or place in a higher power consumption or normal or active state) or any combination of the foregoing with respect to part of a circuit or all components of a circuit, such as one or more blocks in IC550. Further, PMU580may turn on a clock, increase a clock rate, turn on power, increase power, or any combination of the foregoing in response to a transition from an inactive state to an active state (including, without limitation, when processor(s)565make a transition from a low-power or idle or sleep state to a normal operating state).

Link560may couple to one or more circuits600through serial interface595. Through serial interface595, one or more circuits or blocks coupled to link560may communicate with circuits600. Circuits600may communicate using one or more serial protocols, e.g., SMBUS, I2C, SPI, and the like, as person of ordinary skill in the art will understand.

Link560may couple to one or more peripherals590through I/O circuitry585. Through I/O circuitry585, one or more peripherals590may couple to link560and may therefore communicate with one or more blocks coupled to link560, e.g., processor(s)565, memory circuit625, etc.

In exemplary embodiments, peripherals590may include a variety of circuitry, blocks, and the like. Examples include I/O devices (keypads, keyboards, speakers, display devices, storage devices, timers, sensors, etc.). Note that in some embodiments, some peripherals590may be external to IC550. Examples include keypads, speakers, and the like.

In some embodiments, with respect to some peripherals, I/O circuitry585may be bypassed. In such embodiments, some peripherals590may couple to and communicate with link560without using I/O circuitry585. In some embodiments, such peripherals may be external to IC550, as described above.

Link560may couple to analog circuitry620via data converter(s)605. Data converter(s)605may include one or more ADCs605A and/or one or more DACs605B.

ADC(s)605A receive analog signal(s) from analog circuitry620, and convert the analog signal(s) to a digital format, which they communicate to one or more blocks coupled to link560. Conversely, DAC(s)605B receive digital signal(s) from one or more blocks coupled to link560, and convert the digital signal(s) to analog format, which they communicate to analog circuitry620.

Analog circuitry620may include a wide variety of circuitry that provides and/or receives analog signals. Examples include sensors, transducers, and the like, as person of ordinary skill in the art will understand. In some embodiments, analog circuitry620may communicate with circuitry external to IC550to form more complex systems, sub-systems, control blocks or systems, feedback systems, and information processing blocks, as desired.

Control circuitry570couples to link560. Thus, control circuitry570may communicate with and/or control the operation of various blocks coupled to link560by providing control information or signals. In some embodiments, control circuitry570also receives status information or signals from various blocks coupled to link560. In addition, in some embodiments, control circuitry570facilitates (or controls or supervises) communication or cooperation between various blocks coupled to link560.

In some embodiments, control circuitry570may initiate or respond to a reset operation or signal. The reset operation may cause a reset of one or more blocks coupled to link560, of IC550, etc., as person of ordinary skill in the art will understand. For example, control circuitry570may cause PMU580, and circuitry such as RF receiver5or various blocks, circuits, or components of it, to reset to an initial or known state.

In exemplary embodiments, control circuitry570may include a variety of types and blocks of circuitry. In some embodiments, control circuitry570may include logic circuitry, finite-state machines (FSMs), or other circuitry to perform operations such as the operations described above.

Communication circuitry640couples to link560and also to circuitry or blocks (not shown) external to IC550. Through communication circuitry640, various blocks coupled to link560(or IC550, generally) can communicate with the external circuitry or blocks (not shown) via one or more communication protocols. Examples of communications include USB, Ethernet, and the like. In exemplary embodiments, other communication protocols may be used, depending on factors such as design or performance specifications for a given application, as person of ordinary skill in the art will understand.

As noted, memory circuit625couples to link560. Consequently, memory circuit625may communicate with one or more blocks coupled to link560, such as processor(s)565, control circuitry570, I/O circuitry585, etc.

Memory circuit625provides storage for various information or data in IC550, such as operands, flags, data, instructions, and the like, as persons of ordinary skill in the art will understand. Memory circuit625may support various protocols, such as double data rate (DDR), DDR2, DDR3, DDR4, and the like, as desired.

In some embodiments, memory read and/or write operations by memory circuit625involve the use of one or more blocks in IC550, such as processor(s)565. A direct memory access (DMA) arrangement (not shown) allows increased performance of memory operations in some situations. More specifically, DMA (not shown) provides a mechanism for performing memory read and write operations directly between the source or destination of the data and memory circuit625, rather than through blocks such as processor(s)565.

Memory circuit625may include a variety of memory circuits or blocks. In the embodiment shown, memory circuit625includes non-volatile (NV) memory635. In addition, or instead, memory circuit625may include volatile memory (not shown), such as random access memory (RAM). NV memory635may be used for storing information related to performance, control, or configuration of one or more blocks in IC550. For example, NV memory635may store configuration information related to the operation of RF receiver20, such as configuration information for various blocks, circuits, components, etc. of RF receiver20.

RF receiver20couples to link560. Through link560, RF receiver20may receive control and/or status information from one or more blocks in IC550. Conversely, through link560, RF receiver20may provide information, such as control and/or status information, and information received through RF signals via antenna10.

Various circuits and blocks including digital and/or mixed-signal circuitry described above and used in exemplary embodiments may be implemented in a variety of ways and using a variety of circuit elements or blocks. For example, the ADC35, decimation, filtering, and SRC (DFS) circuit50, the CFO correction circuitry52(including the CFO estimation circuit, the CFO removal circuit, the PDE circuit, and the PDR circuit), the demodulator59, etc. may generally be implemented using digital circuitry. The digital circuitry may include circuit elements or blocks such as gates, digital multiplexers (MUXs), latches, flip-flops, registers, finite state machines (FSMs), processors, programmable logic (e.g., field programmable gate arrays (FPGAs) or other types of programmable logic), arithmetic-logic units (ALUs), standard cells, custom cells, custom analog cells, etc., as desired, and as persons of ordinary skill in the art will understand. In addition, analog circuitry or mixed-signal circuitry or both may be included, for instance, power converters, discrete devices (transistors, capacitors, resistors, inductors, diodes, etc.), and the like, as desired. The analog circuitry may include bias circuits, decoupling circuits, coupling circuits, supply circuits, current mirrors, current and/or voltage sources, filters, amplifiers, converters, signal processing circuits (e.g., multipliers), detectors, transducers, discrete components (transistors, diodes, resistors, capacitors, inductors), analog MUXs and the like, as desired, and as persons of ordinary skill in the art will understand. The mixed-signal circuitry may include analog to digital converters (ADCs), digital to analog converters (DACs), etc.) in addition to analog circuitry and digital circuitry, as described above, and as persons of ordinary skill in the art will understand. The choice of circuitry for a given implementation depends on a variety of factors, as persons of ordinary skill in the art will understand. Such factors include design specifications, performance specifications, cost, IC or device area, available technology, such as semiconductor fabrication technology), target markets, target end-users, etc.

Various circuits and blocks including analog circuitry described above and used in exemplary embodiments may be implemented in a variety of ways and using a variety of circuit elements or blocks. For example, the LNA32, the mixer38, the LO35, and the PGA41may generally be implemented using analog circuitry. The analog circuitry may include bias circuits, decoupling circuits, coupling circuits, supply circuits, current mirrors, current and/or voltage sources, filters, amplifiers, converters, signal processing circuits (e.g., multipliers), sensors or detectors, transducers, discrete components (transistors, diodes, resistors, capacitors, inductors), analog MUXs, and the like, as desired, and as persons of ordinary skill in the art will understand. In addition, digital circuitry or mixed-signal circuitry or both may be included. The digital circuitry may include circuit elements or blocks such as gates, digital multiplexers (MUXs), latches, flip-flops, registers, finite state machines (FSMs), processors, programmable logic (e.g., field programmable gate arrays (FPGAs) or other types of programmable logic), arithmetic-logic units (ALUs), standard cells, custom cells, custom analog cells, etc., as desired, and as persons of ordinary skill in the art will understand. The mixed-signal circuitry may include analog to digital converters (ADCs), digital to analog converters (DACs), etc.) in addition to analog circuitry and digital circuitry, as described above, and as persons of ordinary skill in the art will understand. The choice of circuitry for a given implementation depends on a variety of factors, as persons of ordinary skill in the art will understand. Such factors include design specifications, performance specifications, cost, IC or device area, available technology, such as semiconductor fabrication technology), target markets, target end-users, etc.

Referring to the figures, persons of ordinary skill in the art will note that the various blocks shown might depict mainly the conceptual functions and signal flow. The actual circuit implementation might or might not contain separately identifiable hardware for the various functional blocks and might or might not use the particular circuitry shown. For example, one may combine the functionality of various blocks into one circuit block, as desired. Furthermore, one may realize the functionality of a single block in several circuit blocks, as desired. The choice of circuit implementation depends on various factors, such as particular design and performance specifications for a given implementation. Other modifications and alternative embodiments in addition to the embodiments in the disclosure will be apparent to persons of ordinary skill in the art. Accordingly, the disclosure teaches those skilled in the art the manner of carrying out the disclosed concepts according to exemplary embodiments, and is to be construed as illustrative only. Where applicable, the figures might or might not be drawn to scale, as persons of ordinary skill in the art will understand.

The particular forms and embodiments shown and described constitute merely exemplary embodiments. Persons skilled in the art may make various changes in the shape, size and arrangement of parts without departing from the scope of the disclosure. For example, persons skilled in the art may substitute equivalent elements for the elements illustrated and described. Moreover, persons skilled in the art may use certain features of the disclosed concepts independently of the use of other features, without departing from the scope of the disclosure.