Distributed power supply system for phased arrays

A phased array system includes an antenna system includes multiple antennas configured to transmit or receive signals and a power supply circuit configured to generate a supply power and provide the supply power to a plurality of distributed power supply circuits. The phased array system includes distributed power supply circuits, each of the plurality of distributed power supply circuits configured to receive the supply power from the power supply circuit and generate radio frequency supply powers for one multiple radio frequency circuits. The phased array system includes radio frequency circuits, each of the radio frequency circuits configured to cause one of the antennas to transmit or receive the signals based on the plurality of radio frequency supply powers.

BACKGROUND

Embodiments of the inventive concepts disclosed herein relate generally to the field of phased array systems. More particularly, embodiments of the inventive concepts disclosed herein relate to power supply systems for phased array systems.

A phased array system is a computer-controlled array of antennas which generate a beam of radio waves which can be electronically steered in a particular direction without physically moving the array of antennas. Phased arrays can be used in various forms of communication and radar. Types of phased arrays can be Active Electronically Scanned Array (AESA) or Passive Electronically Scanned Array (PESA). Phased array systems can require large amounts of power, in some cases over 500 watts, and can include a power supply that generates multiple voltage outputs for the phased array system. Multiple units of the phased array, e.g., radio frequency circuits that generate or receive a signal at each of the antenna of the array, can share the multiple supply powers. However, if one of the radio frequency circuits fails in such a way as to disrupt the power supply, every radio frequency circuit may fail.

Furthermore, the radio frequency circuits can require multiple supply powers, e.g., over four. This adds a high level of expense to printed circuit board (PCB) fabrication and/or system design due to requiring additional layers for the multiple power supplies. Furthermore, storage capacitance for each voltage rail for the supply powers is difficult to obtain in a small lattice area which many phase array systems have. Furthermore, as frequency of the phase array system increases, the size of the radio frequency circuits reduces to lower node size integrated circuits which require lower supply voltages. For example, voltages may be under 1 volt across wire lengths greater than twelve inches and currents greater than 500 amps.

SUMMARY

In one aspect, the inventive concepts disclosed herein are directed to a phased array system. The phased array system includes an antenna system including multiple antennas configured to transmit or receive signals. The phased array system includes a power supply circuit configured to generate a supply power and provide the supply power to multiple distributed power supply circuits. The phased array system includes the distributed power supply circuits, each of the distributed power supply circuits configured to receive the supply power from the power supply circuit and generate radio frequency supply powers for one of the radio frequency circuits. The phased array system includes the radio frequency circuits, each of the radio frequency circuits configured to cause one of the antennas to transmit or receive the signals based on the radio frequency supply powers.

In a further aspect, the inventive concepts disclosed herein are directed to a power supply system for a phased array system. The power supply system includes a power supply circuit configured to generate a supply power and provide the supply power to distributed power supply circuits and the distributed power supply circuits, each of the distributed power supply circuits configured to receive the supply power from the power supply circuit and generate radio frequency supply powers for one of the radio frequency circuits of the phased array system.

In a further aspect, the inventive concepts disclosed herein are directed to a multi-chip-module for a phased array system. The multi-chip-module includes a distributed power supply circuit, the distributed power supply circuit configured to receive a supply power from a power supply circuit and generate radio frequency supply powers for a radio frequency circuit of the multi-chip-module. The multi-chip-module further includes the radio frequency circuit, the radio frequency circuit configured to cause an antenna to transmit or receive a signal based on the radio frequency supply powers.

DETAILED DESCRIPTION

Before describing in detail the inventive concepts disclosed herein, it should be observed that the inventive concepts disclosed herein include, but are not limited to, a novel structural combination of power supplies, analog circuits, data/signal processing components, sensors, and/or communications circuits, and not in the particular detailed configurations thereof. Accordingly, the structure, methods, functions, control and arrangement of components, software, and circuits have, for the most part, been illustrated in the drawings by readily understandable block representations and schematic diagrams, in order not to obscure the disclosure with structural details which will be readily apparent to those skilled in the art, having the benefit of the description herein. Further, the inventive concepts disclosed herein are not limited to the particular embodiments depicted in the exemplary diagrams, but should be construed in accordance with the language in the claims.

Referring generally to the figures, systems and methods for distributed power supply circuits for a phased array system are described with respect to various aspects of the inventive concepts. In some embodiments, a phased array system includes a single power supply that provides multiple supply voltages to radio frequency circuits of the phased array. However, if one of the radio frequency circuits fails and disrupts the supply voltage, all of the radio frequency circuits can fail since they each share the same power supply. In this respect, a distributed power supply including multiple distributed power supply circuits configured to each locally generate the supply voltages for individual radio frequency circuits can be implemented in the phased array system. This distributed solution increases fault tolerance of the phased array system and improves efficiency by utilizing less power for the phased array system.

Since the power supply is distributed, startup and shutdown power sequencing and/or bulk storage of the radio frequency circuits can be performed by the distributed power supply circuits on an individual basis. By distributing the power supply circuits, parasitic capacitance can be reduced and a higher degree of confidence can be achieved. The distributed power supply can implement local radio frequency circuit envelope tracking and/or dynamic power control and can include efficient taper by implementing switch-mode power supply back off at the radio frequency level as opposed to linear regulation.

Efficient taper can be implemented by the distributed power supply circuits by decreasing output power of the elements that are further away from the center of the phased array (e.g., power supply circuits can decrease the output power they generate, lower voltage, if they are located farther away from the center of the phased array system). This creates a beam pattern with lower sidelobe levels. With all components on the same voltage supply, taper is implemented by backing off the input power and running all but a few cells (e.g., a predefined number of cells) below maximum power which means running almost every cell at the same direct current (DC) power consumption. With distributed power supplies, the voltage can be lowered for cells further away from the center allowing each cell to be run at close to maximum power which minimizes the DC power consumption of the array.

Each distributed power supply can be programmed with an indication of where in the array they are located so that the distributed power supply can perform the particular taper operations (e.g., certain locations may correspond with backing off power while others may not). In various embodiments, the distributed power supply circuits can receive an indication of location and/or an indication to act as a power supply that backs off power to implement efficient taper. The indications can be programmed such that a power supply circuit can be programmed and/or reprogrammed with the location/back off indication so that the power supply circuits can all be identical in construction, only the programmed indication may be different.

While the distributed power supply circuits provide many operational efficiency and fault tolerance benefits, the distributed power supply circuits also provide design and testing benefits. For example, utilizing distributed power supply circuits allows for co-simulation down to the junction scale across full process, voltage, and temperature (PVT). The distributed power supply allows for easy array size flexibility as each radio frequency circuit is associated with its own particular power supply circuit, reducing the design cycle time of a phased array system.

Further regarding design and testing, a distributed power supply can simplify factory testing. For example, standalone tests can be performed for the phased array system (e.g., phased array panel stand-alone tests) and are possible since the power supply circuits are distributed and specific for each RF circuit. The equipment performing the tests does not need to perform power sequencing. In some cases, improper test equipment power sequencing can damage phased array systems, this failure point is removed if the distributed power supply circuits each perform power sequencing locally and do not require the test equipment to perform power sequencing for the phased array system. Local sequencing of the RF integrated circuits can further be implemented when the phased array system is being turned on and/or off when in the field.

Digital integration of the distributed power supply with the RF integrated circuits allows for complex tuning and algorithm control to be implemented along with system monitoring. Furthermore, since shorter (or no) traces are run between the distributed power supply circuits and the radio frequency circuits, wire losses for transporting power can be minimized. Furthermore, instead of creating multiple PCB layers for each of the multiple power supplies generated locally by the distributed power supply, the amount of copper in the PCB layers is reduced allowing for lower inductance and resistance. Since multiple traces are not run across the board, less current is required for supply powers. The high level of integration of the distributed power supply allows for efficient voltage sampling at many locations in the power supply, allowing for higher levels of control and higher precision across Process, Voltage, and Temperature (PVT) variations in both power supplies and beamformer integrated circuits.

By distributing power supply circuits across the phased array system to unit cells improves power supply efficiencies for the phased array system and simplifies the most expensive component of a phased array system, the main PCB. Not only does distributing the power supplies to the unit cell improve power supply efficiency for the phased array system by quickly reacting to varying loads (systems with varying loads e.g., pulsed radar systems or time division duplex (TDD) systems), it drastically increases mean time between failure (MTBF) due to its fault tolerant nature.

The distributed power supply as discussed herein enables hybrid low earth orbit (LEO) and geostationary earth orbit (GEO) (or GEO-only) airborne phased arrays. The distributed power supply system permits smaller apertures (lower power, lower cost, lower drag) to be installed on an airplane and still operate at baseline spectral efficiencies, preserving profit margins on data services.

Referring now toFIG. 1, an aircraft100including a phased array system102is shown, according to an exemplary embodiment. The aircraft100is shown to be an airliner. However, aircraft100may be any kind of commercial aircraft, military aircraft, helicopter, unmanned aerial vehicle (UAV), spacecraft, car, truck, motorcycle, tank, Humvee, and/or any other kind of vehicle, manned or unmanned. The aircraft100is shown to include a phased array system102. The phased array system can be a radar or communication system configured to transmit and receive signals.

The phased array system102can be a computer-controlled array of antennas which generate a beam of radio waves electronically steered in a particular direction without physically moving the array of antennas. The phased array system102can be configured to perform communication and/or radar. The phased array system102can be an Active Electronically Scanned Array (AESA) system or a Passive Electronically Scanned Array (PESA) system.

Referring now toFIG. 2, a circuit block diagram of the phased array system102is shown, according to an exemplary embodiment. The phased array system102is shown to include a power supply202and multiple RF integrated circuits214. The power supply202is configured to generate supply powers204-212for the RF integrated circuits214. The supply powers204-212can be distributed to the integrated circuits214via various electrical connections (e.g., wires, circuit board traces, etc.). The power supply202can include one or multiple circuits to generate each of the supply powers204-212, e.g., transformer circuits, switch mode power supply (SMPS) circuits, linear power supply circuits, buck converter circuits, inverting charge pump circuits, and/or any other power supply circuit. The power supply202can be and/or can include generators, batteries, solar cells, and/or any other energy generating source for generating the supply powers204-212.

The supply powers204-212can include a supply power for a low-noise amplifier (LNA), i.e., LNA supply power204, a RF supply power206, a BIAS supply power208, a core supply power210, and an input/output (I/O) supply power212. The voltages generated for the supply powers204-212can be any value and, in some embodiments, can have a nominal range from 0.5 volts to 5 volts and/or higher dependent on the use of the supply powers204-212. A voltage of 2.5 volts and a current of 25.6 amperes (or any other voltage or current) can be generated for the LNA supply power204. A voltage of 2.2 volts and a current of 46.5 amperes (or any other voltage or current) can be generated for the RF supply power206. A voltage of −5.0 volts and a current of 12.8 mille amperes (or any other voltage or current) can be generated for the BIAS supply power208. A voltage of 1.2 volts and 4.25 amperes (or any other voltage or current) can be generated for the core supply power210. Finally, a voltage of 2.5 volts and current of 4.25 amperes (or any other voltage or current) can for generated by the I/O supply power212.

If the current of one of the supply powers204-212is high, (e.g., 46.5 amps and/or above any particular value) this may indicate that one of the RF integrated circuits214is malfunctioning since this high current draw from the power supply202can be caused by one of the RF integrated circuits214malfunctioning. This high current draw may cause a fire or the power supply202to fail in its entirety. In this regard, a single RF integrated circuit214failing can cause the entire phased array system102to fail.

Each of the supply powers204-212is supplied to the RF integrated circuits214, according to some embodiments. The RF integrated circuits214can be configured to generate signals and/or receive signals via antenna of phased array system102, perform modulation, perform demodulation, perform amplification, phase shifting, and/or any other operation to implement the phased array system102via the supply powers204-212. The RF integrated circuits214may be “beamformer” circuits, circuits configured to generate or receive signals, e.g., generate beams for the phased array system102. Examples of beamformer circuits and other RF circuits that the RF integrated circuits214may be can be found in U.S. patent application Ser. No. 15/792,479 filed Oct. 24, 2017, U.S. patent application Ser. No. 15/697,262 filed Sep. 6, 2017, and U.S. patent application Ser. No. 15/600,497 filed May 19, 2017, the entirety of each of these patent applications is incorporated by reference herein.

The phased array system102, i.e., the RF integrated circuits214, may require multiple different supply voltages, each with a voltage tolerance that may be within five to ten percent for the RF integrated circuit214to operate correctly. Therefore, if each of the supply powers204-212is routed via various traces or voltage rails to the RF integrated circuits214, factors such as parasitic capacitance can create reliability and/or design issues to properly power the RF integrated circuits214. Furthermore, at each of the integrated circuits214, there may not be any way to correct for the errors in the voltage level.

Using a single power supply, e.g., the power supply202, to generate all the supply powers necessary for the RF integrated circuits214can give acceptable results for lower power and higher voltage devices. However, for high frequency phased array systems which require low voltage and high current, PCB fabrication may be difficult. Furthermore, not having redundancy in the power supply decreases mean time between failure (MTBF).

In some embodiments, a redundant power supply can be implemented to supplement the power supply202in case the power supply202fails. However, this doubles the cost and PCB area consumption as compared to a single power supply. In some embodiments, a single power supply can include feeder linear regulators for low current rails, however, this results in lower efficiency due to the linear regulators. Overall, low voltage but high current rails are difficult to maintain in the phased array system102since small resistive losses on the PCBs causes large percentage swings on the supply voltage. This can cause calibration issues as beamformers do not have the same transfer characteristics across voltage.

Referring now toFIG. 3, a circuit block diagram of a circuit300configured to implement local power supplies for multiple RF integrated circuits is shown, according to an exemplary embodiment. The circuit300includes the power supply202configured to generate a single supply power. The power supply202can be configured to provide the single supply power, e.g., a voltage and current, to each of multiple power management integrated circuits (PMICs), i.e., PMICs302-306. Each of the PMICs302-306can be configured to generate multiple supply powers based on the single supply power received from the power supply202and provide the multiple supply powers to the RF integrated circuits308. The PMICs302-306can be silicon on insulator (SOI) complementary metal-oxide-semiconductor (CMOS) circuits and/or circuits built with any other semiconductor process. In some embodiments, the signal supply power is a high voltage supply power and the multiple supply powers are low voltage supply powers. The RF integrated circuits308may be the same as and/or similar to the RF integrated circuits214as described with reference toFIG. 2.

The high level of digital integration of the circuit300allows for the circuit300, specifically the PMICs302-306, to be a smarter power supply that can adapt to more situations. Furthermore, a high level of analog-to-digital conversion (ADC) and voltage/current monitoring can be done on chip so the PMICS302-306has move information on power supply and load operation.

The circuit300can be implemented in the phased array system102such that one of the PMICs302-306is implemented for each of the RF integrated circuits308-312. The PMICs302-306implemented in a phased array system102provide a distributed power supply within the phased array system102. In this regard, each of the PMICs302-316is configured to operate independently from each other and can each be configured to power the integrated circuits308-312. In the event that one of the PMICs302-306fails, each of the PMICs302-306can be configured to open (e.g., operate an electronic or mechanical switch), so as not to disrupt the supply power generated by the power supply202(e.g., operating the switch causes the PMICs302-306to form an open circuit with the power supply202).

Taking PMIC302and RF integrated circuit308as an example, the PMIC302and the RF integrated circuit308can be configured to communicate with each other. The RF integrated circuit308can provide information to the PMIC302regarding the load which the integrated circuit308places on the PMIC302. In some embodiments, the communication is a serial communication protocol, e.g., Serial Peripheral Interface (SPI), Inter-Integrated Circuit (I2C), Universal Asynchronous Receiver-Transmitter (UART), Universal Synchronous And Asynchronous Receiver-Transmitter (USART), and/or any other communication protocol. The communication between the RF integrated circuits308and the PMIC302and even among multiple PMICs302-306can implement a highly integrated level of operation for each PMIC since each PMIC of the PMICs302-306knows the current state of the RF integrated circuits308-312, itself, and the other PMICS304and306.

The PMIC302can be configured to adjust the supply powers (one or multiple of the supply powers) that the PMIC302is configured to generate and provide the RF integrated circuit308. For example, the RF integrated circuit308can implement envelope tracking based on communication received from the RF integrated circuit308to adjust a voltage level of one of the supply powers to reduce unnecessary power usage of the PMIC302. The PMICs302-306can implement efficient modulation on transmission of signals and dynamic linearity on receiving signals for anti jam capabilities based on the communication between the PMIC302and the RF integrated circuit308. In this regard, the communication between the PMIC304and the RF integrated circuit310can allow for dynamic supply requests and control of the supply powers (e.g., control of a voltage level of the supply powers) generated by the PMIC302.

The PMICs302-306can be configured to implement anti jam capabilities. The PMICs302-306can be configured to receive and/or detect an indication that there is a large signal, a jamming signal, (e.g., the antennas associated with the RF integrated circuits308-312can receive the jamming signal and the RF integrated circuits308-312can detect the jamming signal and communicate the presence of the jamming signal to the PMICs302-306). The PMICs302-306can increase the supply voltages they generate pulling the receivers out of compression at the expense of increased DC power consumption to perform anti-jam.

Furthermore, in some embodiments, each of the RF integrated circuits308-312(or the PMICs302-306) can include temperature sensors. The temperature sensors can be analog and/or digital temperature sensing devices and can be and/or include Negative Temperature Coefficient (NTC) thermistors, Resistance Temperature Detectors (RTDs), thermocouples, and/or semiconductor-based sensors. Since there are multiple integrated circuits308-310, often formed implemented as a grid of devices, heat may concentrate in the center of the grid. In this regard, based on measured temperature (and/or communicated temperature measurements), the PMICs302-306can adjust the supply powers to prevent overheating in certain areas of the board, e.g., in the center.

Referring now toFIG. 4, a circuit block diagram of a circuit400is shown, according to an exemplary embodiment. The circuit400may be similar to the circuit300with the exception that PMICs are implemented within RF integrated circuits. In this regard, a communication protocol is not necessarily required since the PMICs are local within the RF integrated circuits although a communication can in some embodiments be implemented between PMICs408-412so that each of PMICs408-412receives an indication of the state of the other PMICs408-412.

RF integrated circuits402-406can be the same as or similar to the RF integrated circuits308-312as described with reference toFIG. 3and the RF integrated circuits214as described with reference toFIG. 2. The PMICs408-412can be the same as or similar to the PMICs302-306as described with reference toFIG. 3. The power supply202can generate a single supply power and provide the supply power to the RF integrated circuits402-406. Since each of the RF integrated circuits402-406include a PMIC, the PMICs408-412, each of the PMICs408-412can generate one or multiple supply powers based on the single supply power generated by the power supply202for operating the RF integrated circuits402-406.

However, the PMICs408-412can be integrated within the RF integrated circuits402-406. Integrating the PMICs408-412within the RF integrated circuits402-406can reduce circuit board size and/or reduce the area which the RF integrated circuits402-406and the PMICs408-412take up. Furthermore, the same dynamic control of supply powers as described with reference toFIG. 3can be implemented without requiring the communication between integrated circuits, i.e., communication protocols for communicating between chips.

Referring now toFIG. 5, the PMIC302ofFIG. 3is shown in greater detail, according to an exemplary embodiment. Although the PMIC302is shown to be separate from the RF integrated circuit308(e.g., as shown inFIG. 3), the PMIC302can also be integrated within the RF integrated circuit308(e.g., as shown inFIG. 4). PMIC302is configured to receive the supply power from power supply202and utilize multiple circuits to generate various supply powers for the RF integrated circuit308. The PMIC302can include multiple power converters500-508. The power converters500-508can be, but are not limited to, buck converters, boost converters, inverting charge pumps, switched capacitors, etc. The power converters500-508can be configured to generate an LNA supply power, an RF supply power, a BIAS, a core supply power, an I/O supply power, and/or any other power supply power.

The PMIC302, based on a supply power generated by the power supply202(e.g., a 5 volt supply power or any other supply power), can generate any power supply, for example, 0.5 volt to 5 volt power supplies. Examples of the voltages and currents that the PMIC302can generate with the power converters500-508can be a 1.5 volt 0.133 ampere LNA supply power, a 1.0 volt 0.4 ampere RF supply power, a −0.5 volt 5 mille ampere BIAS, a 1 or 0.9 volt 50 mille ampere core supply power, and/or a 1.2 volt 50 mille ampere I/O supply power, however, any voltage or current level can be generated by the power converters500-508of the PMIC302. As compared to the single power supply system ofFIG. 2, instead of requiring a high voltage (e.g., a 28 volt supply power) to be generated by the power supply202, only a low voltage supply (e.g., a 5 volt supply power) is needed to be generated. Because of the distributed nature of the PMICs, to generate the same 1 volt rail with the PMICs requires approximately 20 percent of the current that the power supply ofFIG. 2requires. Using less current realizes less wire losses (IR losses) which implements higher efficiency in the power supply system.

Referring now toFIG. 6, the PMIC ofFIG. 3is shown in greater detail, according to an exemplary embodiment. The PMIC302includes various circuits and devices within the PMIC302and various external components610outside the PMIC302. The external components610are power supply capacitors612and filter inductors614.

The power supply capacitors612can include decoupling capacitors, filtering capacitors, and/or any other capacitor for a power supply. The capacitors can include electrolytic capacitors, ceramic capacitors, tantalum capacitors, polycarbonate capacitors, and/or any other type of capacitor. The filter inductors614can be configured to perform power supply filtering and can be air core inductors, iron core inductors, ferrite core inductors, and/or any other type of inductor.

The PMIC302is shown to include power devices608. The power devices can include regulators, transistors, diodes, and/or any other component for generating one or multiple supply powers. PMIC302is further shown to include monitoring/BIT circuit600, margining circuit604, sequencing circuit602, and control circuit606. The circuits600-606can operate the power devices608to adjust each of the supply powers generated by the PMIC302. The circuits600-606can be implemented as one or multiple processing circuits, e.g., logic circuits (e.g., complementary metal-oxide-semiconductor (CMOS) logic circuits), processors, memory devices, etc.

The monitoring/BIT circuit600can be configured to implement power supply monitoring and testing (i.e., built in test (BIT)). The monitoring/BIT circuit600can be configured to perform tests on the PMIC302and the external components610in addition to monitoring the PMIC302to determine if a fault has occurred (e.g., measure voltages, currents, etc.). In response to a detection of a fault (e.g., a supply voltage rising or falling below a predefined amount), the monitoring/BIT circuit600can be configured to shut off the PMIC302and “open” e.g., stop using power from the power supply202by opening various switches.

The margining circuit604can be configured to adjust voltages of the supply powers by operating the power devices608to verify system performance margin with respect to a supply voltage. The sequencing circuit602can be configured to control the voltages of the supply powers generated by the PMIC302for powering up and/or powering down the RF integrated circuit that the PMIC302provides power to. For example, the sequencing circuit602is configured to operate the power devices608to provide power at particular sequences for the various supply powers generated by the PMIC302in some embodiments.

The control circuit606can be configured to operate power devices608to reduce power consumption of the RF circuits which the PMIC302operates. For example, the control circuit606can perform envelope tracking by tracking an envelope of a transmission signal and adjusting the voltage of the supply powers based on the tracked envelope. The PMIC302can be coupled to a particular RF integrated circuit in order to track the envelope of the transmission signal of the RF integrated circuit or may receive data from the particular RF integrated circuit indicative of the envelope. Since envelope tracking is implemented on a PMIC by PMIC basis, multiple PMICs could each perform envelope tracking simultaneously, each adjusting the voltage of a supply power differently based on the envelope of the transmitted signal.

The load which the RF integrated circuit places on the PMIC302can be dynamic. More specifically, the load may be changing over time, i.e., the load is time varying. In this regard, the control circuit606can operate voltage levels of supply powers generated for the RF integrated circuit to adapt to change based on the time varying load.

Furthermore, the control circuit606can be configured, based on communication with other PMICs, to sequence the operation of supply powers to stagger the power draw of the RF circuits which the PMICs power. Furthermore, the control circuit606can perform dynamic linearity for received signals for anti jam capabilities. The control circuit606can also, based on temperatures measured across the phased array system102, operate the supply voltages to prevent heat from being concentrated in the center of the phased array system102.

Referring now toFIG. 7, a buck converter circuit700is shown, according to an exemplary embodiment. The buck converter circuit700can illustrate one or multiple of the power converters500-508as described with reference toFIG. 5.

The buck converter circuit700is shown to include the power supply202. The power supply is shown to be connected to a P-channel metal-oxide-semiconductor field-effect transistor (MOSFET), transistor704. Although the transistor704is shown inFIG. 7as a P-channel MSOFET, the transistor704can be an N-channel MOSFET, a N-channel field-effect transistor (FET), a P-channel FET, a N-type bipolar junction transistor (BJT), and/or a P-type BJT. In some embodiments, the transistor704is a silicon on insulator (SOI) transistor. SOI transistors may be high performance switches due to their low parasitic capacitances. The transistor704is shown to be controlled by a PWM signal generated by voltage source702.

The circuit700is shown to include a diode706(which can also be any other switching component e.g., a MOSFET, a BJT, etc.), inductor708, and capacitor710. The circuit700can create a voltage over load712at a particular level relative to the voltage of the power supply202, and based on how transistor704is switched by voltage source702. More specifically, the voltage of the load712is a function of the duty cycle of the PWM wave generated by voltage source702and the voltage level of the voltage source202.

The output voltage over the load712can be defined with the equation:

D=Vout-VD(Vin-VTrans-VD)
where D is the duty cycle of the PWM signal, Voutis the voltage over the load712, VDis the voltage over the diode706, Vinis the voltage of the voltage source702, and VTransis the voltage over the transistor704. The equation above is a generalized equation and can be modified to account for core magnetic element losses and/or IR losses in the physical connections of the circuit700.

Neglecting the voltage drops over the transistor704and the diode706, the output voltage can be defined as:
Vout=DVin
the equation Vout=DVinis a generalized equation and can be modified to account for core magnetic element losses and/or IR losses in the physical connections of the circuit700.

The circuit700can be implemented within the PMIC302as described with reference toFIG. 6. In this regard, PWM signal source702, the transistor704, and the diode706can be the power devices608that the PMIC302can be configured to control to generate specific output voltage (e.g., for use in envelope tracking) while the inductor708and the capacitor710can be the external components610. The PMIC302can be configured to adjust the duty cycle of the PWM signal source702to control the voltage level across load712.

In some embodiments, multiple transistors are stacked in parallel instead of the single transistor704. The number of switches that are in parallel and are on at a time can control the slew rate and can reduce emissions of the entire power supply (e.g., reduce spurs generated by switching transistor704). The PMICs can be configured to turn a certain number of transistors on at the same time.

Referring now toFIG. 8, a multi-chip-module (MCM)800is shown for the phased array system102, according to an exemplary embodiment. The MCM800can include multiple die on an interposer. The MCM800includes multiple integrated circuits interconnected on a substrate. The substrate can be a printed circuit board (PCB), a high density interconnection (HDI) substrate, and/or any other type of substrate. The MCM800can be any kind of MCM, for example, a laminated MCM (MCM-L), a deposited MCM (MCM-D), a ceramic substrate MCM (MCM-C) and/or any other type of MCM. The MCM800is shown to include multiple RF circuits including a beamformer802and a PMIC804. Where multiple MCM800are implemented in a phased array system, each MCM can have separate negative bias supply, removing failures were one negative supply shorts to ground causing explosive failure of entire board

MCM800may be a single cell of a phased array, e.g., the phased array system102. The beamformer802can be the same as and/or similar to the RF integrated circuits as described with reference toFIGS. 2-7while the PMIC804can be the same as and/or similar to the PMICs as described with reference toFIGS. 3-8. The PMIC804is located on the substrate of MCM800separate from the beamformer802. Capacitors and/or inductors for the PMIC804can be located on the substrate of the MCM800and/or can be integrated within the PMIC804. Implementing the inductor and capacitor on the MCM substrate can enable higher densities and/or improve efficiency of the PMIC804. While the PMIC804can receive an external supply power (e.g., a single supply power), the beamformer802can be powered via multiple supply powers generated by the PMIC804. Furthermore, communication can occur between the beamformer802and the PMIC804to dynamically adjust voltage levels of the supply powers generated by the PMIC804for the beamformer802based on the time changing load of the beamformer802.

Multiple MCMs, similar to the MCM800can be implemented as cells in the phased array system102. In this regard, each MCM can include its own beamformer circuit. Since the PMICs can be distributed across the MCMs, the efficiency and/or fault tolerance of the phased array system102can increase since one or multiple MCM power supplies (PMICs) can fail without disrupting the phased array system102.

Referring now toFIG. 9, a MCM900is shown including multiple RF integrated circuits and a PMIC integrated within one of the RF integrated circuits, according to an exemplary embodiment. MCM900is shown to include a beamformer902. The beamformer902can be the same as and/or similar to the RF integrated circuits as described with referenced toFIGS. 1-7. The PMIC904can be integrated within the beamformer902instead of outside the PMIC904as shown in the MCM800as described with reference toFIG. 8. The PMIC904can be the same as or similar to the PMICs as described with reference toFIGS. 3-7.

Referring generally toFIGS. 8-9, multiple MCMs similar to MCM800or MCM900can provide fault tolerant operation and easy building and testing of phased array systems. Since if any one PMIC fails, only that MCM will fail and the other MCMs can continue to operate properly, i.e., the phased array system has soft failure capabilities since only a single cell of the phased array system would fail and the remainder of the array can continue to operate. In some cases, 10-20% of cells can fail but the phased array system can continue to operate. Furthermore, design and testing can be improved since a number of cells for the phased array system is modular and does not depend on designing or redesigning power supplies.

The MCM ofFIG. 9can provide the highest level of integration possible and the ability to share information between the beamformer902and the PMIC904. The MCM ofFIG. 9may also realize the lowest amount of resource consumption and lowest reoccurring cost to manufacture and smallest area consumption. The MCM ofFIG. 8can realize the potential to reuse existing beamformer designs and does not require a redesign to accommodate the incorporation of the PMIC. Furthermore, designing MCMs such as the MCM800may not require for the PMIC and beamformer to be designed together, decoupling dependencies in design.

Referring now toFIGS. 10-11, the phased array system102is shown in greater detail including MCMs similar to the MCM800as described with reference toFIG. 8and MCMs similar to the MCM900as described with reference toFIG. 9. Referring more particularly toFIG. 10, the phased array system102is shown to include an antenna system1002. The antenna system1002can include multiple antennas ordered in a matrix. For illustrative purposes, three antennas1004-1008are shown configured to transmit or receive signals although any number of individual antennas can be included in the antenna system1002. As shown inFIG. 10each antenna is associated with a particular unit cell, e.g., MCM900, MCM1010including beamformer circuit1012with an integrated PMIC1014, and MCM1016with a beamformer circuit1018with an integrated PMIC1020. Similarly, inFIG. 11, each of the antenna1004are associated with (controlled to send or receive by) the MCM800, MCM1102including beamformer circuit1104and PMIC1106, and MCM1108including beamformer circuit1110and PMIC1112.

The scope of this disclosure should be determined by the claims, their legal equivalents and the fact that it fully encompasses other embodiments which may become apparent to those skilled in the art. All structural, electrical and functional equivalents to the elements of the above-described disclosure that are known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be encompassed by the present claims. A reference to an element in the singular is not intended to mean one and only one, unless explicitly so stated, but rather it should be construed to mean at least one. No claim element herein is to be construed under the provisions of 35 U.S.C. § 112, sixth paragraph, unless the element is expressly recited using the phrase “means for.” Furthermore, no element, component or method step in the present disclosure is intended to be dedicated to the public, regardless of whether the element, component or method step is explicitly recited in the claims.

Embodiments of the inventive concepts disclosed herein have been described with reference to drawings. The drawings illustrate certain details of specific embodiments that implement the systems and methods and programs of the present disclosure. However, describing the embodiments with drawings should not be construed as imposing any limitations that may be present in the drawings. The present disclosure contemplates methods, systems and program products on any machine-readable media for accomplishing its operations. Embodiments of the inventive concepts disclosed herein may be implemented using an existing computer processor, or by a special purpose computer processor incorporated for this or another purpose or by a hardwired system.

The foregoing description of embodiments has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the subject matter to the precise form disclosed, and modifications and variations are possible in light of the above teachings or may be acquired from practice of the subject matter disclosed herein. The embodiments were chosen and described in order to explain the principals of the disclosed subject matter and its practical application to enable one skilled in the art to utilize the disclosed subject matter in various embodiments and with various modifications as are suited to the particular use contemplated. Other substitutions, modifications, changes and omissions may be made in the design, operating conditions and arrangement of the embodiments without departing from the scope of the presently disclosed subject matter.