Semiconductor device and method of manufacturing the same

The present invention provides a semiconductor device that includes: stacked semiconductor chips, each semiconductor chip including a semiconductor substrate and a first insulating layer that is provided on side faces of the semiconductor substrate and has concavities formed on side faces thereof; first metal layers that are provided in center portions of inner side faces of the concavities; and second metal layers that are provided in the concavities and are connected to the first metal layers formed on each semiconductor chip. The present invention also provides a method of manufacturing the semiconductor device.

FIELD OF THE INVENTION

The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device, and more particularly, to a semiconductor device that is formed with stacked semiconductor chips and a method of manufacturing the semiconductor device.

BACKGROUND OF THE INVENTION

In recent years, there has been an increasing demand for smaller semiconductor devices that can be used as non-volatile memory media for portable electronic devices such as portable telephone devices and IC memory cards. In this trend, techniques of efficiently packaging semiconductor chips have been developed. As one of such techniques, there is a method of packaging stacked semiconductor chips.

Japanese Patent Application Publication No. 2004-342861 discloses the following technique (conventional technique 1). Firstly, grooves are formed on the upper face of a semiconductor wafer, and an insulating layer is embedded in the grooves. Through holes having conductors embedded therein are then formed in the insulating layer. The through holes are cut so as to divide the semiconductor wafer into semiconductor chips. The through holes become concavities formed on the side faces of the semiconductor chip, and the conductors formed in the through holes electrically connect the upper face and the lower face of the semiconductor chip.

Japanese Patent Application Publication No. 2004-221372 discloses the following technique (conventional technique 2). Through holes having side walls covered with conductors are formed in a semiconductor wafer. The through holes are cut so as to divide the semiconductor wafer into semiconductor chips. The semiconductor chips are stacked, and metal resin layers are formed in the concavities formed from the through holes in the side faces of the semiconductor chips. The stacked semiconductor chips are electrically connected to one another via the metal resin layers formed in the concavities.

Japanese Patent Application Publication No. 2001-250906 discloses the following technique (conventional technique 3). After semiconductor chips are stacked, wiring patterns are formed on the side faces of the stacked semiconductor chips. The stacked semiconductor chips are electrically connected to one another via the wiring patterns.

As in the conventional technique 1 and the conventional technique 2, however, the following problems are caused in a case where through holes are formed in a semiconductor wafer and are cut to divide the semiconductor wafer into semiconductor chips. Since the conductors that are embedded in the through holes or cover the side walls of the through holes are cut, the conductors are likely to come off when the wafer is divided into chips. Also, to form through holes in a semiconductor wafer or an insulating layer, deep etching needs to be performed. This is technologically difficult, and results in higher production costs. In the conventional technique3, wiring patterns are formed in semiconductor chips after the semiconductor chips are stacked. As a result, the production costs become higher.

SUMMARY OF THE INVENTION

The present invention has been made in view of the above circumstances and provides a semiconductor device that has metal layers that can be formed on side faces of stacked semiconductor chips at low costs and electrically connect the semiconductor chips to one another. The present invention also provides a method of manufacturing such a semiconductor device.

According to a first aspect of the present invention, there is provided a semiconductor device including: a plurality of stacked semiconductor chips, at least one of the semiconductor chips including a semiconductor substrate, a first insulating layer that is provided on side faces of the semiconductor substrate and has concavities formed on side faces thereof, and first metal layers that are provided in center portions of inner side faces of the concavities; and second metal layers that are provided in the concavities and are connected to the first metal layers formed on the at least one of the semiconductor chips. The concavities are formed in the first insulating layer. Accordingly, the formation of these concavities is easier than the formation of concavities in a semiconductor substrate. Also, since the first metal layers are formed in the center portions of the concavities, removal of the first metal layers can be prevented when through holes are cut. Thus, a semiconductor device that has second metal layers that electrically connect the semiconductor chips and can be formed at low costs can be provided.

According to another aspect of the present invention, there is provided a semiconductor device including: a plurality of stacked semiconductor chips, at least one of the semiconductor chips including a semiconductor substrate, a first insulating layer that is provided on side faces and an upper face of the semiconductor substrate, first metal layers that are provided on side faces and an upper face of the first insulating layer, and a second insulating layer that is provided on upper faces of the first metal layers and side faces of the first insulating layer and has concavities on side faces thereof; and second metal layers that are provided in the concavities and are connected to the first metal layers formed on the at least one of the semiconductor chips, the second metal layers being connected to the first metal layers through the concavities. The concavities are formed in the first insulating layer. Accordingly, the formation of these concavities is easier than the formation of concavities in a semiconductor substrate. Also, since the first metal layers are formed in the center portions of the concavities, removal of the first metal layers can be prevented when through holes are cut. Further, electric contact between the upper semiconductor chip of the stacked semiconductor chips and the first metal layers can be prevented. Further, when the second insulating layer is formed, the second insulating layer can be prevented from not covering the first metal layers due to poor accuracy of alignment. Thus, it is possible to provide a semiconductor device that has second metal layers that electrically connect the semiconductor chips and can be formed at low costs.

According to another aspect of the present invention, there is provided a semiconductor device including a package that has a built-in semiconductor device mounted therein, the built-in semiconductor device being the above-described semiconductor device.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device including: forming first grooves on an upper face of a semiconductor wafer; forming a first insulating layer that covers the upper face of the semiconductor wafer and side faces of the first grooves, and has second grooves that are formed in the first grooves and has concavities on side faces thereof, forming first metal layers on side faces of the concavities; and dividing the semiconductor wafer into a plurality of semiconductor chips by removing a bottom portion of the semiconductor wafer until the removal reaches bottom faces of the second grooves. Through holes are not formed, and accordingly, there is no need to perform the etching for forming through holes. Thus, the production costs can be lowered. Also, the bottom portion of the semiconductor substrate is removed to divide the semiconductor wafer into semiconductor chips, without the dicing of the metal layers. Thus, the first metal layers can be prevented from coming off.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device including: forming first grooves on an upper face of a semiconductor wafer; forming a first insulating layer that covers the upper face of the semiconductor wafer and side faces of the first grooves, and has second grooves that are formed in the first grooves, forming first metal layers on an upper face and side faces of the first insulating layer; forming a second insulating layer that covers the upper face of the first insulating layer and side faces of the second grooves, and has third grooves that are formed in the second grooves and has concavities on side faces thereof, with the first metal layers being exposed through the concavities; and dividing the semiconductor wafer into a plurality of semiconductor chips by removing a bottom portion of the semiconductor wafer until the removal reaches bottom faces of the third grooves. Through holes are not formed, and accordingly, there is no need to perform the etching for forming through holes. Thus, the production costs can be lowered. Also, the bottom portion of the semiconductor substrate is removed to divide the semiconductor wafer into semiconductor chips, without the dicing of the metal layers. Thus, the first metal layers can be prevented from coming off. Further, as the second insulating layer covers the first metal layers except for the portions exposed through the concavities, short-circuiting due to misalignment can be prevented between the first metal layers and the semiconductor substrate located above the first metal layers.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

A description will now be given, with reference to the accompanying drawings, of embodiments of the present invention.

First Embodiment

A first embodiment is an example of a structure formed with stacked semiconductor chips.FIG. 1is a perspective view of a semiconductor device in accordance with the first embodiment.FIG. 2is a cross-sectional view of the semiconductor device, taken along the line A-A ofFIG. 1. As shown inFIG. 1, the semiconductor device includes stacked semiconductor chips10having circuits formed therein. In the example described in the following, four semiconductor chips10are stacked, but the present invention can be applied to any semiconductor device that are formed with more than four or less than four stacked semiconductor chips10. Pad units18are formed on the upper surface of the stack of the semiconductor chips10. Second metal layers24are formed on the side faces of each semiconductor chip10.

As shown inFIG. 2, each stacked semiconductor chip10includes a semiconductor substrate12and a first insulating layer16formed on the side faces and the upper face of the semiconductor substrate12. Pad electrodes14are formed on the semiconductor substrate12. A first metal layer20is formed on the first insulating layer16and the side faces of the first insulating layer16. The first metal layer20is electrically connected to the pad electrodes14in an opening formed in the first insulating layer16, so as to form the pad units18. A second insulating layer22is provided between each two neighboring semiconductor chips10. The second insulating layer22electrically separates the semiconductor substrate12of the upper semiconductor chip10from the first metal layer20formed on the lower semiconductor chip10. The second metal layers24are provided so as to electrically connect the first metal layers20formed on the side faces of the respective semiconductor chips10.

Referring now toFIGS. 3A through 7B, a method of manufacturing the semiconductor device in accordance with the first embodiment is described.FIGS. 3A through 4Bare perspective views of the portion of a semiconductor chip10indicated by “B” inFIG. 1, illustrating the procedures for forming the semiconductor chips from semiconductor wafers. Referring first toFIG. 3A, the pad electrodes14made of aluminum, for example, are formed on the semiconductor substrate12that is a silicon semiconductor wafer. The pad electrodes14are electrically connected to a circuit pattern formed on the semiconductor substrate12. First grooves40that contain the scribe lines for dividing the semiconductor substrate12into semiconductor chips are formed in the upper face of the semiconductor substrate12. Each of the first grooves40has a depth of 50 μm or greater, for example, and a width of 100 μm or greater, for example. As shown inFIG. 3B, a photosensitive polyimide film15is formed to cover the upper face of the semiconductor substrate12and the side faces of the first grooves40by a spin coat technique, for example. The film thickness of the polyimide film15on the semiconductor substrate12is about 10 μm, for example.

As shown inFIG. 4A, the photosensitive polyimide film15is exposed through a predetermined pattern, so as to form second grooves42having concavities52in the first grooves40and the first insulating layer16having openings50on the pad electrodes14. The concavities52extend from the upper face of the first insulating layer16to the bottom faces of the second grooves42. The depth of each of the second groove42is 50 μm or greater, for example, and the width of each second groove42is 20 μm or greater, for example. The depth of each of the concavities52is 20 μm, for example. As shown inFIG. 4B, the upper face of the first insulating layer16and the center of each concavity52are plated with copper, for example, so as to form the first metal layers20.

FIG. 5Ais a top view of the structure in the above situation.FIGS. 5B and 5Care cross-sectional views of the semiconductor chip10, taken along the lines C-C and D-D ofFIG. 5A, respectively. As shown inFIGS. 5A through 5C, the concavities52are formed in the second grooves42formed in the first insulating layer16. The first metal layers20are formed in the centers of the respective concavities52. The first metal layers20are connected to the pad electrodes14formed on the semiconductor substrate12through the openings50.

FIG. 6is a cross-sectional view of the structure, taken along the line D-D ofFIG. 5A. As shown inFIG. 6, polishing is performed on the bottom face of the semiconductor substrate12until it reaches the semiconductor grooves42. At this point, the thickness of the semiconductor substrate12is about 50 μm, for example. Since the depth of each of the second grooves42is 50 μm or greater, for example, the semiconductor substrate12is divided by the second grooves42, so as to produce semiconductor chips10. The procedure for thinning the semiconductor substrate12may be carried out using a technique other than polishing.

FIGS. 7A and 7Bare perspective views of the portion B ofFIG. 1. As shown inFIG. 7A, the semiconductor chips10divided in the manner shown inFIG. 6are stacked. A second insulating layer22is interposed between each two semiconductor chips10, so that the semiconductor chips10are bonded to one another with an adhesive agent. At this point, the concavities52in each of the semiconductor chips10form the concavity portions52extending from the upper face of the uppermost one of the stacked semiconductor chips10to the lower face of the lowermost one. The second insulating layers22may be formed on the first metal layers20before the polishing is performed on the bottom face inFIG. 6.

As shown inFIG. 7B, the concavity portions52of the semiconductor chips10are squeegeed and filled with silver paste, for example, so as to form the second metal layers24. With the second metal layers24, the first metal layers20formed in the respective semiconductor chips10are electrically connected. Thus, the semiconductor device in accordance with the first embodiment is completed.

In the first embodiment, the stacked semiconductor chips10are not necessarily identical semiconductor chips. For example, it is possible to stack semiconductor chips having semiconductor memory devices formed thereon, on semiconductor chips having logic circuits formed thereon. Also, not all the stacked semiconductor chips10necessarily have the pad electrodes14connected to all the second metal layers24formed in the concavity portions52. Meanwhile, more than one pad electrode14may be connected to one second metal layer24in one semiconductor chip10. It is possible to determine which pad electrode(s)14of each semiconductor chip10is (are) to be connected to the corresponding one(s) of the concavity portions52, in accordance with which function is to be realized in a stacked semiconductor chips30. In the first embodiment, each semiconductor chip10includes the first insulating layer16having the concavities52, and the first metal layers20. However, at least one of the stacked semiconductor chips should include the first insulating layer16having the concavities52formed therein, and the first metal layers20.

As shown inFIG. 8, second metal layers24amade of copper may be formed by an electroless plating technique, for example. In a case where the second metal layers are formed by an electroless plating technique, the plating layers formed on the first metal layers20each have a reasonable thickness. Accordingly, the plating layers formed on the first metal layers20of the semiconductor chips10having spaces in between are connected to one another over the first metal layers20. If the first metal layers20of the respective semiconductor chips10having spaces in between are not electrically connected, an electroless plating technique is utilized to form the second metal layers24, so as to connect the first metal layers20to one another.

In the semiconductor device in accordance with the first embodiment, each semiconductor chip10has the first insulating layer16formed on the side faces of the semiconductor substrate12. The first insulating layer16has the concavities52formed at regular intervals between the top face and the lower face of the semiconductor chip10. The first metal layers20are formed in the centers of the inner side faces of the concavities52. In the semiconductor device formed with stacked semiconductor chips10, the second metal layers24that electrically connect the first metal layers20formed on the respective semiconductor chips10are formed in the concavities52of each semiconductor chip10.

The first metal layers20and the second metal layers24formed on each semiconductor chip10are connected, so as to connect the semiconductor chips10to one another via the second metal layers24. In a case where the concavities52are formed in the semiconductor substrate12as in the first conventional example, it is necessary to perform etching on the semiconductor substrate12. In the first embodiment, on the other hand, the first insulating layer16is formed on the side faces of the semiconductor substrate12, and the first insulating layer16has the concavities52. Accordingly, the concavities52can be easily formed. The first metal layers20are formed in the centers of the inner side faces of the concavities52. More specifically, each first metal layer20formed on the inner side faces of the concavities52extends from the first metal layer20formed on the upper face of the first insulating layer16. Any first metal layer20is not formed in the regions in contact with the second grooves42. With the first metal layers20being formed in this manner, it is possible to avoid the problem that is observed with the first and second conventional examples that the first metal layers20come off when through holes are formed. Further, it is possible to squeegee the concavities52with silver paste, so as to readily form the second metal layers24, as shown inFIG. 7B. As at least one semiconductor chip10among the stacked semiconductor chips30includes the first insulating layer16having the concavities52and the first metal layers20, the above described effects can be achieved with the semiconductor chip10.

The first insulating layer16is provided on the upper face and the side faces of the semiconductor substrate12. Accordingly, the first insulating layer16can be easily formed through the application of the polyimide film16and an exposing and developing process.

Further, the second insulating layer22is provided on the first metal layers20formed on the upper face of the first insulating layer16. With this arrangement, the first metal layers20can be prevented from coming into contact with the semiconductor chip10located above the subject semiconductor chip10. The second insulating layer22formed on the first metal layers20serves to prevent short-circuiting with the semiconductor chip10located above. However, if there is unevenness in the upper face of the subject semiconductor chip10, the thermal resistance between the semiconductor chips10becomes higher. Therefore, the second insulating layer22should preferably cover the entire upper face of each semiconductor chip10.

Further, each semiconductor chip10has the pad electrodes14formed on the upper face of the semiconductor substrate12. The first insulating layer16has the openings50on the respective pad electrodes14. The first metal layers20are also formed on the upper face of the first insulating layer16, and are connected to the pad electrodes14through the openings50. With this arrangement, the pad electrodes14of different semiconductor chips10can be connected to one another via the second metal layers24.

By the method of manufacturing the semiconductor device in accordance with the first embodiment, the first grooves40are formed in the upper face of the semiconductor substrate12that is a semiconductor wafer, as shown inFIG. 3A. As shown inFIG. 4A, the first insulating layer16that covers the upper face of the semiconductor substrate12and the side faces of the first grooves40is formed. The first insulating layer16also has the second grooves42inside the first grooves40, and the second grooves42have the concavities52formed on the side faces thereof. As shown inFIG. 4B, the first metal layer20covers the inner side faces of the concavities52. As shown inFIG. 6, polishing is performed on the bottom face of the semiconductor substrate12until it reaches the bottom faces of the second grooves42, so as to divide the semiconductor substrate12into semiconductor chips10. By this manufacturing method, there is no need to form through holes. Accordingly, there is no need to perform etching for forming the through holes, and the production costs can be reduced. As the polishing is performed on the lower face of the semiconductor substrate12, there is no need to cut the metal layers by a dicing technique to obtain individual semiconductor chips10. Thus, the first metal layers20can be prevented from coming off.

Also, to form the first insulating layer16, the polyimide film15(an insulating film) is formed on the upper face of the semiconductor substrate12and the side faces of the first grooves40, as shown inFIG. 3B. The second grooves42having the concavities52are then formed in the polyimide film15, as shown inFIG. 4A. Through this procedure, the second grooves42and the concavities52can be easily formed, without the formation of through holes. The insulating film to be the first insulating film is an insulating film other than the polyimide film15. In the first embodiment, a predetermined region of the photosensitive polyimide film15is exposed to light, so as to form the second grooves42and the concavities52. However, the second grooves42and the concavities52may be formed by forming a photoresist on the insulating film to be the first insulating film and then performing etching.

Further, as shown inFIG. 4A, the first insulating layer16is formed so as to have the openings50on the pad electrodes14formed on the semiconductor substrate12. As shown inFIG. 4B, the first metal layers20are formed on the upper face of the first insulating layer16, so that the first metal layers20are connected to the pad electrodes14through the openings50. Through these procedures, the circuits formed on the semiconductor chip10can be electrically connected to the second metal layers24via the first metal layers20.

Further, as shown inFIG. 4B, the first metal layers20are formed in the centers of the inner side faces of the concavities52. Although the first metal layers20may be formed on the entire concavities52, the formation of the first metal layers20in the centers of the inner side faces of the concavities52is advantageous in that the silver paste is stuck on the first metal layers20at the time of the squeegee in the first embodiment, so as to prevent the first metal layers from coming off, as shown inFIG. 7B. Also, as shown inFIG. 8, the second metal layers24formed by an electroless plating technique can prevent short-circuiting between the plating layer grown from the first metal layers20and the first metal layers20in the concavities52.

Further, as shown inFIG. 7A, more than one semiconductor chips10are stacked on one another. As shown inFIG. 7B, the second metal layers24are formed in the concavities52and are connected to the respective first metal layers20of the semiconductor chips10. In this manner, the second metal layers24to be connected to the first metal layers20can be easily formed, as the concavities52are filled with the silver paste used for the squeegee.

Second Embodiment

A second embodiment is an example of a semiconductor device that has a second insulating layer formed on the first metal layers20and the side faces of the first insulating layer, and also has concavities on its side faces. Referring toFIGS. 9A through 12, a method of manufacturing the semiconductor device in accordance with the second embodiment is described. LikeFIG. 3A,FIGS. 9A through 10Bare perspective views of the portion B of the semiconductor device. As shown inFIG. 9A, the procedures of the first embodiment illustrated inFIGS. 3A and 3Bare carried out. More specifically, the second grooves42are formed in the first grooves40, and the first insulating layer16having the openings50on the pad electrodes14is formed. The width of each of the first grooves40is about 100 μm, and the width of each of the second grooves42is about 40 μm, for example. The depths of each first groove40and each second groove42are both 50 μm or greater, for example. The film thickness of the first insulating layer16is about 10 μm, for example. As shown inFIG. 9B, the first metal layers20are formed on the upper face and the side faces of the first insulating layer16. The first metal layers20are connected to the pad electrodes14through the openings50, so as to form the pad units18.

As shown inFIG. 10A, a photosensitive polyimide film27of 10 about μm, for example, is applied to the second grooves42in such a manner as to cover the upper face of the first insulating layer16and the side faces of the second grooves42. As shown inFIG. 10B, a predetermined region of the polyimide film27is exposed and developed. In this manner, third grooves44having concavities54formed on the inner side faces of the second grooves42are formed. The depth of each of the third grooves44is 50 μm or greater, for example, and the width of each of the third grooves44is about 20 μm, for example. The depth of each of the concavities54is about 20 μm, for example.

FIG. 11Ais a top view of this structure.FIG. 11Bis a cross-sectional view of the structure, taken along the line E-E ofFIG. 11A. As shown inFIGS. 11A and 11B, the concavities54are formed in such a manner that the first metal layers20formed on the upper face and the side faces of the first insulating film16are exposed through the centers of the inner side faces of the concavities54. Since the total width of each third groove44(20 μm, for example) and the depth of the concavities on both sides (2×20 μm, for example) is greater than the width of each second groove42(40 μm, for example), the first metal layers20can be exposed through the inner side faces of the concavities54.

FIG. 12is a cross-sectional view of the structure, taken along the line E-E ofFIG. 11A. As shown inFIG. 12, polishing is performed on the bottom face of the semiconductor substrate12until it reaches the third grooves44. At this point, the thickness of the semiconductor substrate12is 50 μm, for example. Since the dept of each of the third grooves44is 50 μm or greater, for example, the semiconductor substrate12is divided by the third grooves44into the semiconductor chips10. The same manufacturing procedures as those of the first embodiment illustrated inFIGS. 7A and 7Bare then carried out to complete the semiconductor device in accordance with the second embodiment.

Unlike the structure of the first embodiment, the structure of the second embodiment includes a second insulating layer26that is formed on the upper faces of the first metal layers20and the side faces of the first insulating layer16, and has the concavities54on its side faces. Further, the second metal layers24are connected to the first metal layers20formed on each semiconductor chip10through the concavities52. By virtue of the second insulating layer26, electric contact between the semiconductor substrate12of the semiconductor chip10stacked on the subject semiconductor chip10and the first metal layers20can be prevented. Also, since the second insulating layer26is provided on the side faces of the first insulating layer16, the second insulating layer26is prevented from not covering the first metal layers20when the positioning accuracy in the formation of the second insulating layer26is poor. As in the first embodiment, at least one of the stacked semiconductor chips should include the first insulating layer16having the concavities52, the first metal layer20, and the second insulating layer26.

By the method of manufacturing the semiconductor device in accordance with the second embodiment, the first grooves40are formed on the upper face of the semiconductor substrate12that is a semiconductor wafer, as shown inFIG. 9A. The first insulating layer16having second grooves42formed therein is formed in the first grooves40, so as to cover the upper face of the semiconductor substrate12and the side faces of the first grooves40. As shown inFIG. 9B, the first metal layers20are formed on the upper face of the first insulating layer16. As shown inFIG. 10B, the third grooves44having the concavities54formed on the inner side faces of the second grooves42are provided to cover the upper face of the first insulating layer16and the side faces of the second grooves42. The second insulating layer26is formed in such a manner as to expose the first metal layers20through the inner side faces of the concavities54. As shown inFIG. 12, polishing is performed on the bottom face of the semiconductor substrate12until it reaches the bottom faces of the third grooves44, so as to divide the semiconductor substrate12into semiconductor chips10. In the first embodiment, misalignment might be caused between the second insulating layer22and the first metal layers20. For example, if the second insulating layer22does not properly cover the first metal layers20, short-circuiting is caused between the first metal layers20and the semiconductor substrate12of the semiconductor chip10stacked on the subject semiconductor chip10. Meanwhile, if a second insulating layer is formed in the concavities54of the first insulating layer16, it is difficult to form the second metal layers24. In addition to the same effects as those of the first embodiment, the manufacturing method in accordance with the second embodiment can achieve the effect that short-circuiting between the first metal layers20and the semiconductor substrate12above the first metal layers20due to misalignment can be prevented, since the second insulating layer26can cover the first metal layers20except for the first metal layers20exposed through the concavities54.

Further, as shown inFIG. 10A, to form the second insulating layer26, the polyimide film27(an insulating film) is formed on the first metal layers20and the first insulating layer16. As shown inFIG. 10B, the third grooves44having the concavities54are formed in the polyimide film27. Through these procedures, the second grooves44and the concavities54can be easily formed. The insulating film to be the second insulating film may be an insulating film other than the polyimide film27. Also, the third grooves44and the concavities54may be formed by forming a photoresist on the insulating film to be the second insulating film and then performing etching.

Third Embodiment

Third through fifth embodiments are examples of semiconductor devices each having stacked semiconductor chips (built-in semiconductor devices) mounted in packages. As shown inFIG. 13, the package has a printed board32made of glass epoxy resin, and the stacked semiconductor chips30of the first or the second embodiment are flip-chip mounted on the printed board32with solder balls33. The solder balls33are provided on the pad units18of the uppermost semiconductor chip10of the first embodiment shown inFIG. 1, for example. Solder balls31are provided on the opposite face from the semiconductor chips30stacked on the printed board32. The solder balls31and the solder balls33are connected with connecting portions (not shown) of the printed board32.

Fourth Embodiment

As shown inFIG. 14, the package includes a printed board32and epoxy resin35, and stacked semiconductor chips (built-in semiconductor devices) are face-up mounted on the printed board32. The printed board32and the semiconductor chips30are connected with wires34. The wires34are connected to the pad units18of the uppermost semiconductor chip10of the first embodiment shown inFIG. 1, for example. The stacked semiconductor chips30are sealed with the epoxy resin35. In the third and fourth embodiments, the stacked semiconductor chips are mounted on the printed board32. However, the stacked semiconductor chips may be mounted on a substrate having conductive wires formed on an insulating substrate.

Fifth Embodiment

As shown inFIG. 15, the package includes a lead frame36and epoxy resin37, and stacked semiconductor chips30(built-in semiconductor devices) are mounted on the lead frame36. The lead frame36and the stacked semiconductor chips30are connected with wires38. The stacked semiconductor chips30are resin-sealed with the epoxy resin37, for example. As in the third through fifth embodiments, the stacked semiconductor chips30(built-in semiconductor devices) of the first or second embodiment may form a semiconductor device mounted in a package. In the first and second embodiments, the first insulating layer16and the second insulating layer26are insulating films made of polyimide. However, those insulating layers are not necessarily polyimide films. For example, it is possible to employ an inorganic film such as silicon oxide film, or an organic film. The first metal layers20are made of copper and formed by a plating method. However, other metal layers can be employed for the first metal layers20. For example, it is possible to employ aluminum or gold. The second metal layers24are metal layers formed with silver paste by an electroless plating technique. However, other metal layers may be employed for the second metal layers24. For example, it is possible to employ gold or copper.

Embodiments generally relates to semiconductor devices. More particularly, embodiments allow lower-cost semiconductor devices. In one implementation, the various embodiments are applicable to flash memory and devices that utilize flash memory. Flash memory is a form of non-volatile memory that can be electrically erased and reprogrammed. As such, flash memory, in general, is a type of electrically erasable programmable read only memory (EEPROM).

Like Electrically Erasable Programmable Read Only Memory (EEPROM), flash memory is nonvolatile and thus can maintain its contents even without power. However, flash memory is not standard EEPROM. Standard EEPROMs are differentiated from flash memory because they can be erased and reprogrammed on an individual byte or word basis while flash memory can be programmed on a byte or word basis, but is generally erased on a block basis. Although standard EEPROMs may appear to be more versatile, their functionality requires two transistors to hold one bit of data. In contrast, flash memory requires only one transistor to hold one bit of data, which results in a lower cost per bit. As flash memory costs far less than EEPROM, it has become the dominant technology wherever a significant amount of non-volatile, solid-state storage is needed.

Exemplary applications of flash memory include digital audio players, digital cameras, digital video recorders, and mobile phones. Flash memory is also used in USB flash drives, which are used for general storage and transfer of data between computers. Also, flash memory is gaining popularity in the gaming market, where low-cost fast-loading memory in the order of a few hundred megabytes is required, such as in game cartridges. Additionally, flash memory is applicable to cellular handsets, smartphones, personal digital assistants, set-top boxes, digital video recorders, networking and telecommunication equipments, printers, computer peripherals, automotive nagivation devices, and gaming systems.

As flash memory is a type of non-volatile memory, it does not need power to maintain the information stored in the chip. In addition, flash memory offers fast read access times and better shock resistance than traditional hard disks. These characteristics explain the popularity of flash memory for applications such as storage on battery-powered devices (e.g., cellular phones, mobile phones, IP phones, wireless phones, etc.).

Flash memory stores information in an array of floating gate transistors, called “cells”, each of which traditionally stores one bit of information. However, newer flash memory devices, such as MirrorBit® Flash Technology from Spansion Inc., can store more than1bit per cell. The MirrorBit cell doubles the intrinsic density of a Flash memory array by storing two physically distinct bits on opposite sides of a memory cell. Each bit serves as a binary bit of data (e.g., either 1 or 0) that is mapped directly to the memory array. Reading or programming one side of a memory cell occurs independently of whatever data is stored on the opposite side of the cell.

With regards to wireless markets, flash memory that utilizes MirrorBit® technology has several key advantages. For example, flash memory that utilizes MirrorBit® technology is capable of burst-mode access as fast as 80 MHz, page access times as fast as 25 ns, simultaneous read-write operation for combined code and data storage, and low standby power (e.g., 1 μA).

FIG. 16shows a block diagram of a conventional portable telephone2010(e.g., cell phone, cellular phone, mobile phone, internet protocol phone, wireless phone, etc.), upon which embodiments can be implemented. The cell phone2010includes an antenna2012coupled to a transmitter2014and a receiver2016, as well as a microphone2018, a speaker2020, a keypad2022, and a display2024. The cell phone2010also includes a power supply2026and a central processing unit (CPU)2028, which may be an embedded controller, conventional microprocessor, or the like. In addition, the cell phone2010includes integrated, flash memory2030. Flash memory2030includes a plurality of stacked semiconductor chips, at least one of the semiconductor chips including a semiconductor substrate, a first insulating layer that is provided on side faces of the semiconductor substrate and has concavities formed on side faces thereof, and first metal layers that are provided in center portions of inner side faces of the concavities; and second metal layers that are provided in the concavities and are connected to the first metal layers formed on the at least one of the semiconductor chips. According to various embodiments, it is possible to provide a semiconductor device, such as flash memory, that has metal layers that are formed on the side faces of stacked semiconductor chips, and electrically connect the semiconductor chips. The present invention also provides a method of manufacturing such a semiconductor device. As a result, the flash memory2030is able to be manufactured at a much lower cost than previous. This decreased cost for the flash memory translates into lower costs for various devices, such as mobile phones, cellular phones, internet protocol phones, and/or wireless phones.

Flash memory comes in two primary varieties, NOR-type flash and NAND-type flash. While the general memory storage transistor is the same for all flash memory, it is the interconnection of the memory cells that differentiates the designs. In a conventional NOR-type flash memory, the memory cell transistors are connected to the bit lines in a parallel configuration, while in a conventional NAND-type flash memory, the memory cell transistors are connected to the bit lines in series. For this reason, NOR-type flash is sometimes referred to as “parallel flash” and NAND-type flash is referred to as “serial flash.”

Traditionally, portable phone (e.g., cell phone) CPUs have needed only a small amount of integrated NOR-type flash memory to operate. However, as portable phones (e.g., cell phone) have become more complex, offering more features and more services (e.g., voice service, text messaging, camera, ring tones, email, multimedia, mobile TV, MP3, location, productivity software, multiplayer games, calendar, and maps.), flash memory requirements have steadily increased. Thus, a less expensive flash memory will render a portable phone more competitive in the telecommunications market.

Also, as mentioned above, flash memory is applicable to a variety of devices other than portable phones. For instance, flash memory can be utilized in personal digital assistants, set-top boxes, digital video recorders, networking and telecommunication equipments, printers, computer peripherals, automotive navigation devices, and gaming systems.

FIG. 17illustrates a block diagram of a computing device2100, upon which embodiments of the present claimed subject matter can be implemented. Although computing device2100is shown and described inFIG. 17as having certain numbers and types of elements, the embodiments are not necessarily limited to the exemplary implementation. That is, computing device2100can include elements other than those shown, and can include more than one of the elements that are shown. For example, computing device2100can include a greater number of processing units than the one (processing unit2102) shown. Similarly, in another example, computing device2100can include additional components not shown inFIG. 17.

Also, it is appreciated that the computing device2100can be a variety of things. For example, computing device2100may be, but is not limited to, a personal desktop computer, a portable notebook computer, a personal digital assistant (PDA), and a gaming system. Flash memory is especially useful with small-form-factor computing devices such as PDAs and portable gaming devices. Flash memory offers several advantages. In one example, flash memory is able to offer fast read access times while at the same time being able to withstand shocks and bumps better than standard hard disks. This is important as small computing devices are often moved around and encounter frequent physical impacts. Also, flash memory is more able than other types of memory to withstand intense physical pressure and/or heat. Thus, portable computing devices are able to be used in a greater range of environmental variables.

In its most basic configuration, computing device2100typically includes at least one processing unit2102and memory2104. Depending on the exact configuration and type of computing device, memory2104may be volatile (such as RAM), non-volatile (such as ROM, flash memory, etc.) or some combination of the two. This most basic configuration of computing device2100is illustrated inFIG. 17by line2106. Additionally, device2100may also have additional features/functionality. For example, device2100may also include additional storage (removable and/or non-removable) including, but not limited to, magnetic or optical disks or tape. In one example, in the context of a gaming system, the removable storage could a game cartridge receiving component utilized to receive different game cartridges. In another example, in the context of a Digital Versatile Disc (DVD) recorder, the removable storage is a DVD receiving component utilized to receive and read DVDs. Such additional storage is illustrated inFIG. 17by removable storage2108and non-removable storage2110. Computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. Memory2104, removable storage2108and non-removable storage2110are all examples of computer storage media. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory2120or other memory technology, CD-ROM, digital video disks (DVD) or other optical storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can accessed by device2100. Any such computer storage media may be part of device2100.

In the present embodiment, the flash memory2120comprises: a plurality of stacked semiconductor chips, at least one of the semiconductor chips including a semiconductor substrate, a first insulating layer that is provided on side faces of the semiconductor substrate and has concavities formed on side faces thereof, and first metal layers that are provided in center portions of inner side faces of the concavities; and second metal layers that are provided in the concavities and are connected to the first metal layers formed on the at least one of the semiconductor chips. According to various embodiments, it is possible to provide a semiconductor device, such as flash memory, that has metal layers that are formed on the side faces of stacked semiconductor chips, and electrically connect the semiconductor chips. The present invention also provides a method of manufacturing such a semiconductor device. As a result, the flash memory2030is able to be manufactured at a much lower cost than previous. This decreased cost for the flash memory translates into lower costs for various devices, such as personal digital assistants, set-top boxes, digital video recorders, networking and telecommunication equipments, printers, computer peripherals, automotive navigation devices, gaming systems, mobile phones, cellular phones, internet protocol phones, and/or wireless phones. Further, in one embodiment, the flash memory2120utilizes MirrorBit® technology to allow storing of two physically distinct bits on opposite sides of a memory cell.

Device2100may also have input device(s)2114such as keyboard, mouse, pen, voice input device, game input device (e.g., a joy stick, a game control pad, and/or other types of game input device), touch input device, etc. Output device(s)2116such as a display (e.g., a computer monitor and/or a projection system), speakers, printer, network peripherals, etc., may also be included. All these devices are well known in the art and need not be discussed at length here.

Aside from mobile phones and portable computing devices, flash memory is also widely used in portable multimedia devices, such as portable music players. As users would desire a portable multimedia device to have as large a storage capacity as possible, an increase in memory density would be advantageous. Users would also benefit from reduced memory read time and reduced cost.

FIG. 18shows an exemplary portable multimedia device, or media player,3100in accordance with an embodiment of the invention. The media player3100includes a processor3102that pertains to a microprocessor or controller for controlling the overall operation of the media player3100. The media player3100stores media data pertaining to media assets in a file system3104and a cache3106. The file system3104is, typically, a storage medium or a plurality of storage media, such as disks, memory cells, and the like. The file system3104typically provides high capacity storage capability for the media player3100. Also, file system3104includes flash memory3130. In the present embodiment, the flash memory3130comprises: a plurality of stacked semiconductor chips, at least one of the semiconductor chips including a semiconductor substrate, a first insulating layer that is provided on side faces of the semiconductor substrate and has concavities formed on side faces thereof, and first metal layers that are provided in center portions of inner side faces of the concavities; and second metal layers that are provided in the concavities and are connected to the first metal layers formed on the at least one of the semiconductor chips. According to various embodiments, it is possible to provide a semiconductor device, such as flash memory, that has metal layers that are formed on the side faces of stacked semiconductor chips, and electrically connect the semiconductor chips. The present invention also provides a method of manufacturing such a semiconductor device. As a result, the flash memory2030is able to be manufactured at a much lower cost than previous. This decreased cost for the flash memory translates into lower costs for various devices, such as personal digital assistants, set-top boxes, digital video recorders, networking and telecommunication equipments, printers, computer peripherals, automotive navigation devices, gaming systems, mobile phones, cellular phones, internet protocol phones, and/or wireless phones. However, since the access time to the file system3104is relatively slow, the media player3100can also include a cache3106. The cache3106is, for example, Random-Access Memory (RAM) provided by semiconductor memory. The relative access time to the cache3106is substantially shorter than for the file system3104. However, the cache3106does not have the large storage capacity of the file system3104. Further, the file system3104, when active, consumes more power than does the cache3106. The power consumption is particularly important when the media player3100is a portable media player that is powered by a battery (not shown). The media player3100also includes a RAM3122and a Read-Only Memory (ROM)3120. The ROM3120can store programs, utilities or processes to be executed in a non-volatile manner. The RAM3122provides volatile data storage, such as for the cache3106.

The media player3100also includes a user input device3108that allows a user of the media player3100to interact with the media player3100. For example, the user input device3108can take a variety of forms, such as a button, keypad, dial, etc. Still further, the media player3100includes a display3110(screen display) that can be controlled by the processor3102to display information to the user. A data bus3124can facilitate data transfer between at least the file system3104, the cache3106, the processor3102, and the CODEC3112. The media player3100also includes a bus interface3116that couples to a data link3118. The data link3118allows the media player3100to couple to a host computer.

In one embodiment, the media player3100serves to store a plurality of media assets (e.g., songs, photos, video, etc.) in the file system3104. When a user desires to have the media player play/display a particular media item, a list of available media assets is displayed on the display3110. Then, using the user input device3108, a user can select one of the available media assets. The processor3102, upon receiving a selection of a particular media item, supplies the media data (e.g., audio file, graphic file, video file, etc.) for the particular media item to a coder/decoder (CODEC)3110. The CODEC3110then produces analog output signals for a speaker3114or a display3110. The speaker3114can be a speaker internal to the media player3100or external to the media player3100. For example, headphones or earphones that connect to the media player3100would be considered an external speaker.

In a particular embodiment, the available media assets are arranged in a hierarchical manner based upon a selected number and type of groupings appropriate to the available media assets. For example, in the case where the media player3100is an MP3-type media player, the available media assets take the form of MP3 files (each of which corresponds to a digitally encoded song or other audio rendition) stored at least in part in the file system3104. The available media assets (or in this case, songs) can be grouped in any manner deemed appropriate. In one arrangement, the songs can be arranged hierarchically as a list of music genres at a first level, a list of artists associated with each genre at a second level, a list of albums for each artist listed in the second level at a third level, while at a fourth level a list of songs for each album listed in the third level, and so on.

Finally, various aspects of the present invention are summarized in the following.

According to a first aspect of the present invention, there is provided a semiconductor device including: a plurality of stacked semiconductor chips, at least one of the semiconductor chips including a semiconductor substrate, a first insulating layer that is provided on side faces of the semiconductor substrate and has concavities formed on side faces thereof, and first metal layers that are provided in center portions of inner side faces of the concavities; and second metal layers that are provided in the concavities and are connected to the first metal layers formed on the at least one of the semiconductor chips.

In the above-described semiconductor device, the first insulating layer may be provided on an upper face of the semiconductor substrate. The first insulating layer can be easily formed.

In the above-described semiconductor device, the first metal layers may be provided on an upper face of the first insulating layer; and the semiconductor device may further include a second insulating layer that is formed on upper faces of the first metal layers. Electric contact between the upper semiconductor chip of the stacked semiconductor chips and the first metal layers can be prevented.

According to a second aspect of the present invention, there is provided a semiconductor device including: a plurality of stacked semiconductor chips, at least one of the semiconductor chips including a semiconductor substrate, a first insulating layer that is provided on side faces and an upper face of the semiconductor substrate, first metal layers that are provided on side faces and an upper face of the first insulating layer, and a second insulating layer that is provided on upper faces of the first metal layers and side faces of the first insulating layer and has concavities on side faces thereof; and second metal layers that are provided in the concavities and are connected to the first metal layers formed on the at least one of the semiconductor chips, the second metal layers being connected to the first metal layers through the concavities.

In the above-described semiconductor device, the at least one of the semiconductor chips may include pad electrodes that are provided on the semiconductor substrate; the first insulating layer may have openings that are formed over the pad electrodes; and the first metal layers may be also provided on an upper face of the first insulating layer, and are connected to the pad electrodes through the openings. The pad electrodes of different semiconductor chips can be connected via the second metal layers.

According to a third aspect of the present invention, there is provided a semiconductor device including a package that has a built-in semiconductor device mounted therein, the built-in semiconductor device being the above-described semiconductor device. In the above-described structure, the package may have a substrate; and the built-in semiconductor device may be face-down mounted on the substrate. In the above-described structure, the package may have a substrate; and the built-in semiconductor device may be face-up mounted on the substrate. In the above-described structure, the package may have a lead frame; and the built-in semiconductor device may be sealed with resin.

According to a fourth aspect of the present invention, there is provided a method of manufacturing a semiconductor device including: forming first grooves on an upper face of a semiconductor wafer; forming a first insulating layer that covers the upper face of the semiconductor wafer and side faces of the first grooves, and has second grooves that are formed in the first grooves and has concavities on side faces thereof, forming first metal layers on side faces of the concavities; and dividing the semiconductor wafer into a plurality of semiconductor chips by removing a bottom portion of the semiconductor wafer until the removal reaches bottom faces of the second grooves.

In the above-described method, forming the first insulating layer may include: forming an insulating film on the upper face of the semiconductor wafer; and forming the second grooves that have the concavities formed in the insulating film. The second grooves and the concavities can be easily formed.

In the above-described method, forming the first insulating layer may include: forming the first insulating layer that has openings on pad electrodes formed on the semiconductor wafer; and forming the first metal layers may include forming the first metal layers that are formed on an upper face of the first insulating layer and are connected to the pad electrodes through the openings. The circuits formed on the semiconductor chips and the second metal layers can be electrically connected via the first metal layers.

In the above-described method, forming the first metal layers may include forming the first metal layers on an upper face of the first insulating layer; and the method may further include forming a second insulating layer on upper faces of the first metal layers. Electric contact between the upper semiconductor chip of the stacked semiconductor chips and the first metal layers can be prevented.

In the above-described method, forming the first metal layers may include forming the first metal layers at center portions of inner side faces of the concavities. The first meal layers can be prevented from coming off.

According to a fifth aspect of the present invention, there is provided a method of manufacturing a semiconductor device including: forming first grooves on an upper face of a semiconductor wafer; forming a first insulating layer that covers the upper face of the semiconductor wafer and side faces of the first grooves, and has second grooves that are formed in the first grooves, forming first metal layers on an upper face and side faces of the first insulating layer; forming a second insulating layer that covers the upper face of the first insulating layer and side faces of the second grooves, and has third grooves that are formed in the second grooves and has concavities on side faces thereof, with the first metal layers being exposed through the concavities; and dividing the semiconductor wafer into a plurality of semiconductor chips by removing a bottom portion of the semiconductor wafer until the removal reaches bottom faces of the third grooves.

In the above-described method, forming the second insulating layer may include: forming an insulating film on the semiconductor wafer; and forming the third grooves that have the concavities formed in the insulating film. The second grooves and the concavities can be easily formed.

The above-described method may further include: stacking a plurality of semiconductor chips that include at least one semiconductor chip divided from the semiconductor wafer; and forming second metal layers in the concavities, the first metal layers being connected to the second metal layers. The second metal layers to be connected to the respective first metal layers can be easily formed by carrying out a squeegee process with silver paste and filling the concavities with the silver paste.

In the above-described method, forming the second metal layers may include forming the second metal layers by an electroless plating technique. The second metal layers can be formed so that the respective first metal layers are connected the second metal layers.

As described above, the present invention provides a semiconductor device that has metal layers that are formed on the side faces of stacked semiconductor chips at low costs, and electrically connect the semiconductor chips. The present invention also provides a method of manufacturing such a semiconductor device.

Although the preferred embodiments of the present invention have been described so far, the present invention is not limited to the above specific examples, and various changes and modifications may be made to them within the scope of the present invention.