Integrated circuit including a hetero-interface and self adjusted diffusion method for manufacturing the same

An integrated circuit including a hetero-interface and a manufacturing method thereof is disclosed. One embodiment includes forming a hetero-structure including a hetero-interface at a junction between a first region and a second region, and, thereafter introducing a material into the first region and at least up to the hetero-interface, wherein a diffusion constant of the material is higher in the first region than in the second region.

BACKGROUND

Demands on semiconductor devices with regard to scale integration, access speed and energy consumption are steadily increasing. In order to meet these demands, circuit devices may be scaled down. Scaling down of circuit devices such as field effect transistors (FETs) may, however, be accompanied by undesired physical effects, e.g., the so-called short channel defect, becoming noticeable in FETs having small channel lengths.

A method allowing manufacture of an integrated circuit with small minimum feature sizes would thus be desirable.

SUMMARY

One embodiment provides a method for manufacturing an integrated circuit. The method includes forming a hetero-structure including a hetero-interface at a junction between a first region and a second region, and thereafter introducing a material into the first region and at least up to the hetero-interface, wherein a diffusion constant of the material is higher in the first region than in the second region.

DETAILED DESCRIPTION

In the following detailed description, reference is made to the accompanying drawings which form a part hereof and in which are shown by way of illustration specific embodiments in which the invention may be practiced. In this regard directional terminology, such as “top”, “bottom”, “vertical”, “horizontal”, “planar”, etc. is used with reference to the orientation of the Figure(s) being described. As components of embodiments may be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description therefore is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.

It is to be understood that the features of various exemplary embodiments described herein may be combined with each other unless specifically noted otherwise.

FIG. 1illustrates a schematic cross-sectional view of one embodiment of an integrated circuit100. Integrated circuit100includes a field effect transistor (FET)101. FET101includes source/drain regions102,103and a channel region104sandwiched in-between source/drain regions102,103. Source/drain region102and channel region104differ in at least one semiconductor component. The interface between source/drain region102and channel region104is a hetero-interface105.

The term “hetero-structure” used herein refers to a structure comprising at least two regions of different material composition, the two regions adjoining to each other via a hetero-interface. By way of example, the hetero-structure may include insulating/metallic regions, semiconducting/insulating regions, or semiconducting/metallic regions. The hetero-structure may also include adjoining semiconducting regions of different material composition, e.g., Si/SiGe or adjoining metallic regions of different material composition.

Furthermore, source/drain region103and channel region104also differ in at least one semiconductor component. An interface between source/drain region103and channel region104is a hetero-interface106. A material reservoir107is formed adjacent to source/drain region102and a further material reservoir108is formed adjacent to source/drain region103. A gate structure109including a gate dielectric110and a gate electrode111is formed adjacent to channel region104. Source/drain region102is formed on a conductive region112, the conductive region112being formed over a carrier113. Contact structures114,115are electrically coupled to gate electrode111and source/drain region102, respectively. To provide electrical isolation between neighboring conductive elements, e.g., contact regions114,115and source/drain region103, an insulating structure116is provided. The insulating structure116may include one or multiple insulating layers.

As used herein, the term “electrically coupled” is not limited to a direct coupling of elements and intervening elements may be provided between the “electrically coupled” elements. In this regard conductive region112is provided between the electrically coupled source/drain region102and contact region115. In other embodiments contact region115may be directly coupled to source/drain region102. Furthermore, an intervening element may be provided between contact region114and gate electrode111.

Carrier113may comprise an arbitrary semiconductor material. Examples comprise Si, a Si compound such as SiGe, silicon-on-insulator (SOI), III-V semiconductor compounds such as GaAs or any other suitable substrate material. Carrier113may also be formed as a semiconductor layer, e.g., as an epitaxial layer on a substrate. Furthermore, conductive region112may be part of carrier113. By way of example, conductive layer112may be a patterned conductive layer of a carrier including a layer stack of a substrate material, an insulating layer and the conductive layer, e.g., a layer stack of a silicon substrate, a SiO2layer and a conductive layer such as a doped silicon layer or a single crystalline layer such as Si, Ge, SiGe, sapphire, III-V or II-VI compound semiconductors. Furthermore, components and devices may already be formed within carrier113.

Source/drain regions102,103and channel region104may be parts of a nanowire. The term “nanowire” used herein refers to a structure having a lateral size constrained to tens of nanometers or less and unconstrained longitudinal size. If so, a length of channel region104may be defined in relation to a distance between hetero-interfaces105,106without lithographic constraints. Materials from material reservoirs107,108are introduced into source/drain regions102,103up to hetero-interfaces105,106, respectively. The materials introduced into source/drain regions102,103from material reservoirs107,108have a diffusion constant that is higher in the source/drain regions102,103than in channel region104, respectively. Hence, propagation of the material from the reservoirs107,108up to hetero-interfaces105,106is faster than within channel region104.

In one embodiment, the material introduced into source/drain regions102,103is a metal leading to the formation of a metal-semiconductor alloy. Formation of this alloy proceeds from the material reservoirs107,108towards the hetero-interfaces105,106, respectively. By way of example, a silicide such as NiSi2, NiSi, or Ni2Si may be formed starting from material reservoirs107,108towards hetero-interfaces105,106, respectively. The formation of silicide can be limited to source/drain regions102,103by choosing semiconductor materials for source/drain regions102,103and channel region104such that a diffusion constant of the material to be introduced into source/drain regions102,103is higher in source/drain regions102,103than in channel region104. In the context of this embodiment, the term “diffusion constant of the material” relates to the speed of metal-semiconductor alloy or compound formation starting from material reservoirs107,108towards hetero-interfaces105,106, respectively.

Besides forming source/drain regions102,103of metal-semiconductor alloy, in another embodiment, material reservoirs107,108may include dopants for source/drain regions102,103. These dopants may be diffused into source/drain regions102,103, respectively. Again, these dopants have a diffusion constant that is higher in source/drain regions102,103than in channel region104in order to precisely control the channel dimension.

The hetero-structure including source/drain region102, channel region104and source/drain region103may be formed of a vast variety of material combinations provided that the material, e.g., metal or dopant, to be introduced from material reservoirs107,108into source/drain regions102,103up to hetero-interfaces105,106has a diffusion constant that is higher in source/drain regions102,103than in channel region104, respectively. By way of example, the hetero-structure of source/drain regions102,103and channel region104may include any of the group of Si, SiGe, SiGeC, SiC, SiSn, SiGeSn, or SiGeCSn. The hetero-structure of source/drain regions102,103and channel region104may also include Si/III-V semiconductors/Si, e.g., Si/GaAs/Si, or Si/II-VI semiconductors/Si, e.g., Si/CdTe/Si. In one embodiment, source/drain regions102,103may include Si and channel region104may be formed of SiGe. In this case, material reservoirs107,108may be reservoirs including Ni. When introducing Ni from reservoirs107,108into Si regions102,103, e.g., by thermal processing, Ni may be diffused towards hetero-interfaces105,106and may react with Si to form NiSi2, NiSi, or Ni2Si. The definition of source/drain regions102,103and channel region104by introduction of the materials from reservoirs107,108may be precisely controlled as the formation of the NiSi2proceeds slower within SiGe channel region104than in Si source/drain regions102,103.

Integrated circuit100ofFIG. 1may be varied in many ways. Although material reservoirs107,108remain in the embodiment illustrated inFIG. 1, one or both of these regions may also be removed during manufacture of integrated circuit100, e.g., by an etch process.

In a further embodiment, one of source/drain regions102,103may be a metal-semiconductor alloy region, whereas the other one of source/drain regions102,103may be a doped semiconductor region. Hence, one of material reservoirs107,108is a reservoir including metal, whereas the other one of material reservoirs107,108is a reservoir including dopants, e.g., an oxide of dopants such as B2O3, P2O5, As2O3, or Sb2O3.

In yet another embodiment, the stack of source/drain region102, channel region104and source/drain region103includes a single hetero-interface. By way of example, hetero-interface105may be formed between source/drain region102and channel region104, whereas source/drain region103and channel region104may be formed of same semiconductor materials. As an alternative, the hetero-interface106may be formed between source/drain region103and channel region104whereas source/drain region102and channel region104may be formed of same semiconductor materials or yet a different material formed by another method such as epitaxy, for example. Even if both hetero-interfaces105,106are present, source/drain regions102,103may be formed of different semiconductor components.

Gate structure109may partly or completely surround channel region104. Furthermore, gate structure109may include a stack of at least one insulating layer and one conductive layer. Gate structure109may also include a charge storage layer, e.g., a floating gate layer. Conductive layer102may be a seed layer for growth of a nanowire thereon, for example.

Integrated circuit200furthermore includes a storage capacitor. The storage capacitor may comprise a capacitor dielectric217and a first capacitor electrode218. In this embodiment, source/drain region202is extended compared to the structure shown inFIG. 1and also constitutes the second capacitor electrode of capacitor219. FET201and capacitor219may constitute a DRAM (Dynamic Random Access Memory) cell. It is to be noted that further embodiments including a hetero-structure as elucidated above with reference toFIG. 1may relate to memory concepts other than DRAM or embedded DRAM such as EPROM (Erasable Programmable Read only Memory), EEPROM (Electrically Erasable Programmable Read Only Memory), NROM (Nitrided Read Only Memory) and further volatile and non-volatile memory concepts. The storage capacitor may as well be disposed over the substrate surface.

FIG. 3illustrates a simplified cross-sectional view of one embodiment of an integrated circuit300including a hetero-interface. Similarly to the embodiments illustrated inFIGS. 1 and 2, integrated circuit300includes carrier313and conductive layer312. Again, conductive layer312may be a seed layer assisting growth of nanowire hetero-structure319. Nanowire hetero-structure319includes a stack of source/drain region302, barrier region320, channel region304, barrier region321and source/drain region303. Source/drain regions302,303and barrier regions320,321may include semiconductor and/or metal components. By way of example, nanowire hetero-structure319may be a layer stack of Si/TiN/Si/TiN/Si, Si/TiN/SiGe/TiN/Si Si/TaN/Si/TaN/Si, Si/TaN/SiGe/TaN/Si, Si/Ru/Si/Ru/Si, or SI/Ru/SiGe/Ru/Si. Here, barrier layers320,321formed of TiN act as a diffusion barrier for materials to be introduced from material reservoir307into the nanowire hetero-structure319. It is to be noted that integrated circuit300may include further elements, e.g., any additional elements illustrated in the embodiments ofFIGS. 1 and 2, e.g., a further material reservoir adjacent to source/drain region303. Layers320,321are chosen such that the diffusion constant for materials introduced from material reservoir307into nanowire hetero-structure319is lower than that of regions302,303independently of the diffusion constant in region304.

Although the embodiments illustrated inFIGS. 1 to 3relate to vertical FET concepts having source/drain regions and channel region stacked in a direction perpendicular to a surface of carrier113,213,313, e.g., perpendicular to surface322inFIG. 3, other embodiments may cover other FET concepts, other transistor concepts or diodes.

FET401is planar, i.e., source/drain regions402,403and channel region404are arranged along a surface422of carrier413. Similarly to the embodiment illustrated inFIG. 1, the sequence of source/drain region402, channel region404and source/drain region403includes at least one hetero-interface. Material reservoirs may be formed adjacent to any of source/drain regions402,403(not shown inFIG. 4). The variations illustrated with regard to the vertical FET concepts ofFIGS. 1 and 3also apply to the planar FET concept illustrated inFIG. 4.

It is to be noted that integrated circuits100-400illustrated in the schematic cross-sectional views ofFIGS. 1 to 4may include a plurality of the illustrated FETs, i.e., an array of FETs, as well as further circuit parts, e.g., sense amplifiers. By way of example, these integrated circuits may include chips for applications such as memory, automotive, consumer, chip card and security, industrial, wireless communications, wireline.

FIG. 5illustrates one embodiment of an integrated circuit500including an array of semiconductor memory cells523. Each of semiconductor memory cells523includes a FET according to any of the embodiments described above. Each of memory cell523may be a 1T (1 transistor) memory cell having a storage region within a gate structure, i.e., lacking a storage capacitor, for example. Memory cells523may, however, also be 1T-1C (1 transistor-1 capacitor) memory cells such as DRAM memory cells or any other memory cell concept may be adopted that includes a FET according to any of the embodiments described above. Each of the FETs of the memory cell523may be electrically coupled to a word line524by its gate structure and may further be coupled to a bit line525by one of its source/drain regions. Word lines524and bit lines525may run perpendicular to each other, for example. Each of word lines524and bit lines525may be electrically coupled to further circuits (not shown inFIG. 5) configured to support a read/write operation with respect to a memory cell523. These further circuits may include sense amplifiers and decoders, for example.

FIG. 6is a block diagram illustrating one embodiment of a method for manufacturing an integrated circuit including a hetero-interface. In S600a hetero-structure is formed, the hetero-structure including a hetero-interface at a junction between a first region and a second region. Thereafter, in S610, a material is introduced into the first region and at least up to the hetero-interface wherein a diffusion constant of the material is higher in the first region than in the second semiconductor region. This allows alteration of the material in the first region in a self-aligned manner. By way of example, the first region may be doped or alloyed. A precise adjustment of device dimensions also in a range of several nanometers to several tens of nanometers may thus be achieved. First/second regions may be any regions of semiconductor/semiconductor, metal/semiconductor, semiconductor/phase change, insulator/semiconductor and insulator/phase change, for example. Phase change regions may be formed of chalcogenide glasses such as GeSbTe or AgInSbTe, for example. By introducing the material into the first region in case of the second region being a phase change region, the first region may be used as a conductive region providing electrical connection to the phase change region for example. The material may be introduced by diffusion. As a further example, the material may be implanted.

The material may form a substitial or interstitial with regard to the lattice of the first region.

In one embodiment, the material is a metal and a metal-semiconductor alloy is formed from the first region and the metal. To introduce the metal into the first region, a metal diffusion reservoir may be formed adjacent to the first region and the metal may be diffused from the metal diffusion reservoir into the first region. Apart from forming a metal-semiconductor alloy, e.g., a metal silicide, the material may also be chosen as a dopant of the first semiconductor region. In latter case, a dopant reservoir such as an oxide of the dopant, e.g., P2O5, may be formed adjacent to the first semiconductor region.

In one embodiment, the first region and the second region may form at least part of a nanowire. The first semiconductor region may define at least part of a source/drain region of a FET and the second semiconductor region may define at least part of a channel region of the FET.

In yet another embodiment, a further hetero-structure is formed, the further semiconductor hetero-structure including a hetero-interface, a junction between the second region and a third region. Thereafter, a material may be introduced into the third region and at least up to the further hetero-interface, wherein a diffusion constant of the material is higher in the third region than in the second region. As source/drain regions may be formed of the first and third regions by introducing the material therein, e.g., by doping these regions with dopants or by forming a metal-semiconductor alloy, such as a metal silicide, dimensions of a channel region to be formed within the second region may be precisely controlled as the material diffuses slower within the second region than within the first region, and, optionally within the third semiconductor region. Hence, a self-controlled process for forming source/drain regions may be achieved. Channel lengths in the range of several nanometers to several tens of nanometers may be formed.

The hetero-structure nanowire may be formed by any known method, e.g., using an eutectic such as Al/Si, Au/Si, Ti/Si, Pd/Si, In/Si, Ga/Si on a Si seed layer and supplying a source gas, e.g., SiH4, to grow a silicon nanowire in a direction perpendicular to a surface of the Si seed layer. The hetero-structure may be achieved by control of supply gases, e.g., SiH4and GeH4to form a Si/SiGe hetero-structure.