Silicon-on-insulator structure and method of reducing backside drain-induced barrier lowering

The invention relates to a transistor that includes a semiconductive layer on an insulator layer. Below the insulator layer is a substrate and a contact is disposed in the insulator layer that originates at the substrate and terminates in the insulator layer. The contact is aligned below the transistor junction. The invention also relates to a process flow that is used to fabricate the transistor. The process flow includes forming the contact by either a spacer etch or a directional, angular etch.

FIELD OF THE INVENTION

An embodiment of the present invention relates to transistors that address drain-induced barrier lowering (DIBL). An embodiment of the present invention relates generally to integrated circuit fabrication. More particularly, an embodiment of the present invention relates to a drain disposed in a substrate.

BACKGROUND OF THE INVENTION

Description of Related Art

Advances in semiconductor process technology and digital system architecture have led to integrated circuits having increased operating frequencies. Higher operating frequencies result in undesirable increases in power consumption. Power consumption is a significant problem in integrated circuit design generally, and particularly in large scale, high speed products such as processors and microprocessors.

One way to improve integrated circuit performance, is by reducing the loading capacitance of transistors. Transistor loading capacitance generally has three components, intrinsic gate capacitance, overlap capacitance, and junction capacitance. To reduce junction capacitance, MOSFETs have been constructed on an insulating substrate such as a silicon-on-insulator (SOI) substrate. Typical SOI processes reduce junction capacitance by isolating junctions from the substrate by interposing a thick buried insulator layer. However, short-channel MOSFETs constructed with thick buried insulator layers tend to have poor punch-through characteristics, poor short-channel characteristics and other effects related to the floating body.

FIG. 1is an elevational cross section of an existing SOI transistor10. Transistor10includes a semiconductive substrate12, an insulator14, an isolation structure16, a semiconductive layer18that includes a source/drain region20, a channel region22, and a salicided contact landing24. Transistor10also includes a gate electrode26, a gate dielectric layer28, and a spacer30.

A significant issue that arises when dealing with transistors of the present art involves current leakage from the source to the drain. One of the limiting factors in the scaling of transistors to smaller dimensions is the inability of the gate to fully control the channel region22below the gate. An electrical field exists between the source or drain20and the channel region22. As the source and drain junctions32(the left junction32only is indicated with a reference numeral for clarity) approach one another, the lines of force34(the electrical field at the right junction32only is illustrated for clarity) resulting from the potential that is applied to the drain terminate on the source junction32, to cause drain-induced barrier lowering (DIBL). DIBL results in a leakage current between the source and drain, and at short enough channel lengths, results in failure of the device.

DETAILED DESCRIPTION OF THE INVENTION

An embodiment of the present invention relates to a process flow and a device that addresses drain-induced barrier lowering (DIBL) that is experienced in a transistor junction. An embodiment includes a drain in contact with the substrate. In one embodiment, the drain is a vertically oriented conductor that is positioned at and below the junction in order to intersect a significant amount of the electrical field created at the junction.

The following description includes terms, such as upper, lower, first, second, etc. that are used for descriptive purposes only and are not to be construed as limiting. The embodiments of an apparatus or article of the present invention described herein can be manufactured, used, or shipped in a number of positions and orientations. The terms “semiconductor” and “substrate” generally refer to the physical object that is the basic workpiece that is transformed by various process operations into the desired integrated circuit. A semiconductive substrate is typically made of semiconductive material that has been singulated from a wafer after integrated processing. Wafers may be made of semiconducting, non-semiconducting, or combinations of semiconducting and non-semiconducting material. Examples include silicon-on-oxide (SOI), silicide on a substrate, or a lattice-matched conductor. A substrate may also be a dielectric material such as silica glass or the like, onto which semiconductive material is formed.

Reference will now be made to the drawings wherein like structures will be provided with like reference designations. In order to show the structures of embodiments of the present invention most clearly, the drawings included herein are diagrammatic representations of integrated circuit structures. Thus, the actual appearance of the fabricated structures, for example in a photomicrograph, may appear different while still incorporating the essential structures of embodiments of the present invention. Moreover, the drawings show only the structures necessary to understand embodiments of the present invention. Additional structures known in the art have not been included to maintain the clarity of the drawings.

FIG. 2is a cross-section of a semiconductor structure110during fabrication according to a first general embodiment. In one embodiment, semiconductor structure110includes a silicon-on-insulator (SOI) substrate that has a substrate112that is optionally semiconductive, an insulator114, and a semiconductive layer116. Additionally, an isolation structure118establishes lateral boundaries of a transistor that is being fabricated. A gate stack120is disposed on semiconductive layer116. Gate stack120includes a gate electrode122, a gate dielectric layer124, and a first spacer126.

Processing according to an embodiment commences with an etch.FIG. 3illustrates the result of a first etch during which a first recess128is formed. First recess128bottoms out into, but does not necessarily penetrate through insulator114. Thereafter, a dielectric film is deposited such as by chemical vapor deposition (CVD), and spacer etched to form a second spacer130. In one embodiment, second spacer130is formed according to a known technique, and is a dielectric selected from an oxide, a nitride, an oxynitride, and the like.

FIG. 4illustrates further processing. After the formation of second spacer130, a second etch is carried out that penetrates through insulator114and stops on substrate112. The second etch forms a second recess132that also forms an undercut134below second spacer130. Accordingly, the second etch is selective to both the substrate112and to second spacer130. In one embodiment, the second etch is an isotropic wet etch according to known technique. In another embodiment, the second etch is an isotropic dry etch according to known technique.

FIG. 5illustrates further processing. After the formation of second recess132, a conductive film136is formed by CVD. In one embodiment, conductive film136is a metal. In one embodiment, conductive film136is a refractory metal such as titanium, zirconium, hafnium, and the like. Other refractory metals for conductive film136include nickel, cobalt, palladium, platinum, and the like. Other refractory metals for conductive film136include chromium, molybdenum, tungsten, and the like. Other refractory metals for conductive film136include scandium, yttrium, lanthanum, cerium, and the like. In another embodiment, conductive film136is a metal nitride. The metal in a metal nitride film may be selected from one of the aforementioned metals. In one embodiment, conductive film136is titanium nitride in either stoichiometric or other solid solution ratios.

After the formation of conductive film136, an anisotropic etch process is done to substantially remove all of conductive film136, except that portion that escapes the etch beneath undercut134(FIG.4).FIG. 6depicts semiconductor structure110after the anisotropic etch. A contact138is the remainder of conductive film136(FIG. 5) after the etch. Contact138extends at a bottom end140from substrate112, but it does not terminate in connection with what remains of semiconductive layer116. In one embodiment, contact138has a height-to-width (aspect) ratio of greater than or equal to about 1. In one embodiment, contact138has an aspect ratio of greater than or equal to about 2. In one embodiment, contact138has an aspect ratio of greater than or equal to about 10.

FIG. 7illustrates the result of another etch and an epitaxial growth process. Second spacer130(FIG. 6) is stripped in order to expose what remains of semiconductive layer116(FIG.6). Thereafter, an epitaxial first growth142laterally extends from the edge of semiconductive layer116. Epitaxial growth processing is known in the art, and a supply material such as silane may be used for the formation of epitaxial first growth142. After the formation of epitaxial first growth142, a dielectric material144is deposited into second recess132as depicted in FIG.8. In one embodiment, dielectric material144is deposited into second recess132by a first CVD of a dielectric and a center masking over gate stack120, followed by an etch.

After the formation of dielectric material144, further epitaxial growth is carried out to form an epitaxial second growth146as illustrated in FIG.9. Epitaxial second growth146is depicted with reference numeral146only on the left side for explanative clarity. The composite of semiconductive layer116, epitaxial first growth142, and epitaxial second growth146represent a composite source/drain and channel structure. After the formation of epitaxial second growth146, optional doping thereof may be carried out in order to achieve a preferred doping gradient that forms a junction148within the composite source/drain and channel structure. Accordingly, the doping concentration within epitaxial first- and second growth142and146, respectively is higher than in semiconductive layer116.

InFIG. 9, it is noted that there is a gap with a distance, S, between the bottom extremity of the composite source/drain and channel structure116,142,146, and the top end150of contact138where it terminates in filler insulator144. The distance S, that forms the gap, may be extremely small such as on the order of about 100 Å to about 500 Å.

If contact138were an entire layer that filled second recess132, it would act to lower DIBL, but it would also have a larger capacitance due to its larger surface area that is presented opposite to the bottom of composite source/drain and channel structure116,142,146. Because of the inventive process flow, contact138is disposed in a substantially self-aligned location beneath junction148. Accordingly, the electromagnetic lines of force152(illustrated only at the right side ofFIG. 9for explanative clarity), terminate into contact138instead of into the channel that is semiconductive layer116.

Further processing is carried out as depicted inFIG. 9, wherein a self-aligned silicide (salicided) contact landing154is formed. Additionally and simultaneously, a salicided gate electrode156is formed.

Salicidation is carried out after the optional source/drain implant at an elevated epitaxial tip158of epitaxial second growth146. In one embodiment, a refractory conductive film is blanket deposited. The refractory metal may be selected from nickel (Ni), cobalt (Co), palladium (Pd) and the like. The refractory metal may also be selected from aluminum (Al), titanium (Ti), tungsten (W), ti-tungsten (TiW), chromium (Cr), and the like. Other refractory metals may be selected according to integration with a given process flow and/or a given end product. In an embodiment of the present invention, a cobalt film is deposited to a thickness in a range from about 100 Å to about 200 Å. The refractory metal film may be formed by any well-known method including sputter deposition such as physical vapor deposition (PVD) or by CVD. An Endura® system, made by Applied Materials (AMAT) of Santa Clara, Calif. can be used to sputter deposit the refractory metal film.

After the formation of the refractory metal film, a protective layer of for example titanium nitride, is deposited directly onto the refractory metal film. In one embodiment, the protective layer is titanium nitride that is deposited to a thickness in a range from about 500 Å to about 200 Å. The protective layer can be formed by any well-known technique such as by PVD with an Applied Materials Endura® system or it can be formed by CVD. The protective layer protects the underlying refractory metal film from oxidation during a subsequent silicide anneal.

After the formation of the protective layer, semiconductor structure110is heated to a temperature and for a period of time sufficient to cause the refractory metal film to react with underlying silicon to form a refractory metal salicided contact landing154as depicted in FIG.9. The heating process may be carried out in an inert atmosphere such as argon (Ar) or in some instances, nitrogen (N2) and a temperature in a range from about 400° C. to about 500° C. for a time range from about 45 seconds to about 2 minutes. In one embodiment, heating is carried out at about 450° C. for about 90 seconds. Semiconductor structure110can be suitably annealed in an AMAT 5000® or AMAT 5200® RTP tool. Such a heating process causes the reaction of the refractory metal film and underlying silicon of epitaxial first- and second growth142and146, respectively to form a low sheet-resistance phase film.

Any unsalicided refractory metal film is removed, for example, with a 50:1 buffered HF wet etch for a time period from about 90 seconds to about 150 seconds. In one embodiment, the HF wet etch is carried out for about 2 minutes. After the wet etch, the low sheet-resistance phase salicided contact landing154remains on the source/drain regions. Similarly, salicided gate electrode156is exposed.

A second general process flow embodiment is illustrated beginning inFIG. 2, and proceeding to FIG.10. Semiconductor structure110(FIG. 2, but hereinafter referred to as semiconductor structure210) includes a gate stack220that includes a gate electrode122, a gate dielectric layer124, and a spacer126. First by a gate stack self-aligned etch, a recess260is etched that stops on substrate212that is optionally semiconductive. Further processing is depicted in FIG.11. After the formation of recess260, a conductive film is formed by CVD and two angled, directional etches and an optional orthogonal directional spacer etch are done that leave an inside contact262and an outside contact264in recess260. Inside contact262is self-aligned to one edge of gate stack220. Outside contact264is spaced apart and opposite inside contact262. In one embodiment, inside contact238has a aspect ratio of greater than or equal to about 1. In one embodiment, inside contact238has an aspect ratio of greater than or equal to about 2. In one embodiment, inside contact238has an aspect ratio of greater than or equal to about 10. In any event, inside contact262does not touch semiconductive layer216.

In one embodiment, the conductive film is a metal that is etched to form inside contact262and outside contact264. In one embodiment, the conductive film is a refractory metal such as titanium, zirconium, hafnium, and the like. Other refractory metals for the conductive film include nickel, cobalt, palladium, platinum, and the like. Other refractory metals for the conductive film include chromium, molybdenum, tungsten, and the like. Other refractory metals for the conductive film include scandium, yttrium, lanthanum, cerium, and the like. In another embodiment, the conductive film is a metal nitride. The metal in a metal nitride film may be selected from one of the aforementioned metals. In one embodiment, the conductive film is titanium nitride in either stoichiometric or other solid solution ratios.

Further processing is carried out according to a process flow embodiment.FIG. 12illustrates the result of an epitaxial growth process. An epitaxial first growth266laterally extends from the edge of semiconductive layer216. After the formation of epitaxial first growth266, a dielectric material268is deposited into recess260. In one embodiment, dielectric material268is deposited into recess260by a first CVD of a dielectric material and a center masking over gate stack220, followed by an etch.

After the formation of dielectric material268, further epitaxial growth is carried out to form an epitaxial second growth270as illustrated in FIG.13. Epitaxial second growth270is depicted with reference numeral270only on the left side for explanative clarity. The composite of semiconductive layer216, epitaxial first growth266, and epitaxial second growth270represent a composite source/drain and channel structure. After the formation of epitaxial second growth270, optional doping thereof may be carried out in order to achieve a preferred doping gradient that forms a junction272within the composite source/drain and channel structure. Accordingly, the doping concentration within epitaxial first- and second growth266and270respectively is higher than in semiconductive layer216.

InFIG. 13, it is noted that there is a gap with a distance, S, between the bottom extremity of the composite source/drain and channel structure216,266,270, and the top end250of inside- and outside contacts262and264, respectfully, where they terminate in dielectric material268. The distance, S of the gap may be extremely small such as on the order of about 100 Å to about 500 Å.

Because of the inventive process flow according to this second general embodiment, inside contact262is disposed in a substantially self-aligned location beneath junction272. Accordingly, a significant amount of the electrical field (illustrated by the electromagnetic lines of force274only at the right side ofFIG. 13for explanative clarity), terminates into inside contact262instead of into the channel that is semiconductive layer216.

Further processing is carried out as depicted inFIG. 13, wherein a salicided contact landing276is formed. Additionally and simultaneously, a salicided gate electrode278is formed. Salicidation is carried out as set forth herein.

In a third general embodiment, processing begins on a semiconductor structure110(depicted inFIG. 2, but hereinafter referred to as semiconductive structure310) depicted inFIGS. 14 and 15. Processing begins similar to the second general embodiment in that inside362and outside contacts364are formed in a recess380. Thereafter, a dielectric material382is deposited and patterned to form a channel384that opens to substrate312that is optionally semiconductive. Channel384may or may not expose outside contact364. In the embodiment depicted inFIG. 14, channel384exposes outside contact364.

Further processing, depicted atFIG. 15, includes epitaxial growth386that originates both at semiconductor layer316and at substrate312. Under process flow embodiments similar to the first and second general embodiments, a salicided contact landing388and a salicided gate electrode390are produced.

It is noted that throughout the written description, the structures designated “contact”138,262, and362are not the traditional contact structure as is often used. Rather, the contacts138,262, and362act more as antennae that intercept and drain some of the electromagnetic energy that is represented by the lines of force152and274.

FIG. 16is a process flow diagram of an embodiment. The process flow400includes forming410a gate stack including a first spacer on a semiconductive layer. Next a first etching420is done through the semiconductive layer by a gate stack self-aligned etch. Thereafter, forming a second spacer430is done at the gate stack. After forming the second spacer430, a second etching440is done through an insulator layer disposed beneath the semiconductive layer to form an undercut beneath the second spacer. After the undercut is achieved, a contact is formed450at the undercut. In an alternative process, after conducting a gate-stack self-aligned etch460that exposes the semiconductive substrate, a contact is formed470that is connected to the semiconductive substrate.

In the above two process flows, after forming the contact, the recess is filled480, and a composite source/drain and channel structure is grown490. Finally if selected, salicidation500is carried out on the source/drain regions.

In a method embodiment, the method of reducing DIBL is carried out. The method is undertaken by operating a transistor that has structure according to embodiments set forth herein. The structure may be part of a larger microelectronic device. The microelectronic device may be a sub-component of a variety of electronic systems, such as a clock, a television, a cell phone, a personal computer, an automobile, an industrial control system, an aircraft and others. In another method embodiment, the microelectronic device is operated at a frequency in a range between about 1 MHz and about 2 GHz. In another embodiment, the microelectronic device is operated at a frequency in a range between about 33 MHz and about 1 GHz.

It will be readily understood to those skilled in the art that various other changes in the details, material, and arrangements of the parts and method stages which have been described and illustrated in order to explain the nature of this invention may be made without departing from the principles and scope of the invention as expressed in the subjoined claims.