System and method for preventing read margin degradation for a memory array

An ultra cycling nitride read only memory (NROM) device is coupled to a NROM array such that both bits of the ultra cycling NROM device will be erased when all NROM devices of the NROM array are erased. The ultra cycling NROM device is then programmed at its right bit. A threshold voltage difference will be obtained for the ultra cycling NROM device for the un-programmed left bit. Next, a cycling number is obtained based on the threshold voltage difference for the ultra cycling NROM device. A threshold voltage shift can be found based on the cycling number for the NROM array. Finally, an erase voltage will be calculated according to the threshold voltage shift for the NROM array. If the NROM array is programmed again, the erase voltage will be applied to un-programmed NROM devices of the NROM array to further reduce the threshold voltages.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to a flash memory device, and more particularly, to a system and a method for preventing read margin degradation for a nitride read only memory array.

2. Description of the Related Art

Nitride Read Only Memory (NROM) devices are widely used in the semiconductor industry. As is well known in the art, a NROM device stores charges at both ends of a composite oxide-nitride-oxide (ONO) layer, thus being capable of two bits operation. When a bit of the NROM device is programmed with a charge, the threshold voltage for that bit of the NROM device will be increased. A programmed bit of the NROM device represents a logic “0,” while an un-programmed or erased bit of the NROM device represents a logic “1.” The charge stored at one bit of the NROM device will affect the threshold voltage of the other bit, which is the second bit effect of the NROM device.

The charge retention ability of a NROM device is affected by both the cycling numbers and the aging of the NROM device. A cycling of a NROM device includes a program operation and an erase operation. As the number of cyclings for a NROM device increases, the ONO layer of the NROM device will suffer damage, thus resulting in charge losses and the decrease of the threshold voltage for the NROM device. The aging of a NROM device contributes to the charge loss as well. Therefore, the aging of a NROM device will also decrease its threshold voltage.

FIG. 1shows the threshold voltage Vt distributions for a NROM array100after 10,000 cyclings and 150° C. baking for 20 hours. The high Vt distribution110represents the threshold voltage distribution of the NROM array100at a programmed state after 10,000 cyclings, whereas the low Vt distribution130represents the threshold voltage distribution of the NROM array100at an erased state after 10,000 cyclings. Each distribution has its high bond and low bond. The threshold voltage difference between the high Vt distribution110at its low bond and the low Vt distribution130at its high bond forms the read margin150, which is the read margin for the NROM array100after 10,000 cyclings. No aging effect is considered for the high Vt distribution110and the low Vt distribution130of the NROM array100.

In order to demonstrate the aging effect for the NROM array100, after 10,000 cyclings, the NROM array100is baked at 150° C. for 20 hours, which is equivalent to the aging of the NROM array100at 25° C. for ten years. The high Vt distribution120represents the threshold voltage distribution for the NROM array100at a programmed state after 150° C. baking for 20 hours and 10,000 cyclings, whereas the low Vt distribution140represents the threshold voltage distribution for the NROM array100at an erased state after 150° C. baking for 20 hours and 10,000 cyclings. As shown, the threshold voltages of the NROM array at both the programmed state and the erase state are decreased due to the aging effect. The threshold voltage difference between the low bonds of the high Vt distributions110and120is ΔPV, while the threshold voltage difference between the high bonds of the low Vt distributions130and140is ΔEV. The threshold voltage difference between the high Vt distribution120at its low bond and the low Vt distribution140at its high bond forms the read margin160, which is the degraded read margin for the NROM array100after the aging effect and 10,000 cyclings.

As indicated inFIG. 1, the read margin160is much narrower than the read margin150due to the aging effect. A narrow read margin could cause errors in a read operation for the NROM array100. As shown, ΔPV, i.e., the decrease of the threshold voltage of the NROM array100at a programmed state after the NROM array100is affected by the aging, is the cause for the read margin degradation for the NROM array100.

In view of the foregoing, there is a need for a system and a method that can prevent read margin degradation for a NROM array that is affected by the aging.

SUMMARY OF THE INVENTION

Broadly speaking, the present invention fills this need by providing a method for a nitride read only memory (NROM) array to overcome the read margin degradation problem after the NROM array is affected by aging. A system for utilizing this method is also disclosed.

In accordance with one aspect of the present invention, a system for preventing read margin degradation is provided. The system includes an ultra cycling NROM device and a NROM array. The ultra cycling NROM device is coupled to the NROM array such that both bits of the ultra cycling NROM device are erased when all the NROM devices of the NROM array are erased. The ultra cycling NROM device is identical to all the NROM devices of the NROM array. In one embodiment, both bits of the ultra cycling NROM device are erased concurrently with the NROM array.

In accordance with another aspect of the present invention, a method for preventing read margin degradation for a NROM array that is affected by aging is described. First of all, all the NROM devices of the NROM array along with both bits of the ultra cycling NROM device are erased. A first current is measured for the first bit of the ultra cycling NROM device. Next, the second bit of the ultra cycling NROM device is programmed. A second current is measured for the first bit of the ultra cycling NROM device. First and second threshold voltages are obtained based on the first current and second current for the ultra cycling NROM device. Because of the second bit effect, there exists a threshold voltage difference between the first and second threshold voltages. A cycling number is found based on the threshold voltage difference for the ultra cycling NROM device. Since the NROM array and the ultra cycling NROM device have the same cycling number, a threshold voltage shift for the NROM array is found based on the cycling number. An erase voltage is calculated based on the threshold voltage shift for the NROM array. When the NROM array is programmed, the calculated erase voltage will be applied to the un-programmed NROM devices of the NROM array to reduce the threshold voltages of the NROM array at an erased state.

DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS

Reference is made in detail to embodiments of the invention. While the invention is described in conjunction with the embodiments, the invention is not intended to be limited by these embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents, which may be included within the spirit and scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of the invention, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, as is obvious to one ordinarily skilled in the art, the invention may be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail so that aspects of the invention will not be obscured.

FIGS. 2(a)-(c) demonstrate a system200for preventing read margin degradation for a NROM array100in accordance with one embodiment of the present invention. As shown, the system200includes a NROM array100and an ultra cycling NROM device210. The NROM array100comprises a plurality of NROM devices, while the ultra cycling NROM device210is capable of storing charges at both its right bit and its left bit. The ultra cycling NROM device210is identical to the NROM devices of the NROM array100. The ultra cycling NROM device210is coupled to the NROM array100such that the ultra cycling NROM device210will have the same cycling number as the NROM array100, i.e., both bits of the ultra cycling NROM device210will be erased if all the NROM devices of the NROM array100are erased.

As shown inFIG. 2(a), the NROM array100and both bits of the ultra cycling NROM device210are erased concurrently. The “1” and “1” for both bits of the ultra cycling NROM device210represent both erased bits of the ultra cycling NROM device210. Then, a current for the left bit of the ultra cycling NROM device210is measured and recorded as I1.

Next, the right bit of the ultra cycling NROM device210is programmed. As indicated inFIG. 2(b), the programmed right bit of the ultra cycling NROM device210is represented by “0.” The current for the left bit of the ultra cycling NROM device210is measured again and recorded as I2. Because of the second bit effect, there exists a difference between I1and I2.

FIG. 2(c) shows that threshold voltages LVt1and LVt2of the ultra cycling NROM device210correspond with I1and I2of the ultra cycling NROM device210, respectively. The threshold voltage difference ΔLVt between the threshold voltages LVt1and LVt2will be used to define a threshold voltage shift ΔPV for the NROM array100at an erased state.

FIG. 3shows an exemplary diagram that illustrates the relationship between the threshold voltage difference ΔLVt and the cycling number for the ultra cycling NROM device210in accordance with one embodiment of the present invention. As shown, the threshold voltage difference ΔLVt will increase as the cycling number increases. Therefore, a cycling number can be estimated based on the threshold voltage difference ΔLVt of the ultra cycling NROM device210obtained from the steps inFIGS. 2(a)-(c). Because the ultra cycling NROM device210has the same cycling number as the NROM array100, the estimated cycling number for the ultra cycling NROM device210is also the cycling number of the NROM array100.

FIG. 4shows an exemplary diagram that illustrates the relationship between the threshold voltage shift ΔPV and the cycling number for the NROM array100with different baking temperatures and baking time in accordance with one embodiment of the present invention. Using the estimated cycling number obtained from the step inFIG. 3, one can find the corresponding threshold voltage shift ΔPV for the NROM array100from this diagram.

FIG. 5shows the threshold voltage Vt distributions of the NROM array100after 10,000 cyclings and 150° C. baking for 20 hours in accordance with one embodiment of the present invention. The 150° C. baking for 20 hours for the NROM array100is equivalent to the aging of the NROM array100at 25° C. for 10 years. In order to improve the read margin160after the NROM array100is affected by aging, the low Vt distribution140needs to be shifted to the left (to a lower threshold voltage region) to form the low Vt distribution510such that the threshold voltage difference between the low Vt distributions140and510at their high bonds is as much as ΔPV.

To achieve the low Vt distribution shift for the NROM array100, an erase voltage is calculated based on the threshold voltage shift ΔPV obtained from the step inFIG. 4. After the NROM array is programmed, the erase voltage will be applied to the un-programmed NROM devices of the NROM array100to further reduce the threshold voltages of the un-programmed NROM devices of the NROM array100. As shown, the read margin520between the low bond of the high Vt distribution120and the high bond of the low Vt distribution510is much larger than the read margin160between low bond of the high Vt distribution120and the high bond of the low Vt distribution140. As a result, the read margin between the programmed state and the erased state of the NROM array100is improved.

Overall, a system and an exemplary method for preventing read margin degradation for a NROM array100that is affected by aging are disclosed. The system includes a NROM array100and an ultra cycling NROM device210. The ultra cycling NROM device210is coupled to the NROM array100such that the ultra cycling NROM device210will have the same cycling number as the NROM array100. Whenever all the NROM devices of the NROM array100are erased, both bits of the ultra cycling NROM device210will be erased. After the both bits of the ultra cycling NROM device210along with the NROM array are erased, the ultra cycling NROM device210is programmed at its right bit. A threshold voltage difference ΔLVt will be obtained for the ultra cycling NROM device210. Then, a cycling number is obtained based on the threshold voltage difference ΔLVt for the ultra cycling NROM device210. Since the ultra cycling NROM device210has the same cycling number as the NROM array100, a threshold voltage shift ΔPV for the NROM array100can be found based on the obtained cycling number. Finally, an erase voltage will be calculated according to the threshold voltage shift ΔPV for the NROM array100. When the NROM array100is programmed again, an erase operation will be performed for the un-programmed NROM devices of the NROM array100by applying the calculated erase voltage to the un-programmed NROM devices of the NROM array100.

The foregoing descriptions of specific embodiments of the invention have been presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Obviously, many modifications and variations are possible in light of the above teachings. The embodiments were chosen and described in order to explain the principles and the application of the invention, thereby enabling others skilled in the art to utilize the invention in its various embodiments and modifications according to the particular purpose contemplated. The scope of the invention is intended to be defined by the claims appended hereto and their equivalents.