Systems and methods for multi-level encoding and decoding

A storage system includes a storage medium operable to maintain a data set, a read/write head assembly operable to write the data set to the storage medium and to read the data set from the storage medium, a multi-level encoder operable to encode the data set at a plurality of different code rates before it is written to the storage medium, and a multi-level decoder operable to decode the data set retrieved from the storage medium and to apply decoded values encoded at a lower code rate when decoding values encoded at a higher code rate.

FIELD OF THE INVENTION

Various embodiments of the present invention provide systems and methods for data processing, and more particularly to systems and methods for encoding and decoding data in a data processing system.

BACKGROUND

Various data processing systems have been developed including storage systems, cellular telephone systems, and radio transmission systems. In such systems data is transferred from a sender to a receiver via some medium. For example, in a storage system, data is sent from a sender (i.e., a write function) to a receiver (i.e., a read function) via a storage medium. As information is stored and transmitted in the form of digital data, errors are introduced that, if not corrected, can corrupt the data and render the information unusable. The effectiveness of any transfer is impacted by any losses in data caused by various factors. Data may be encoded and decoded to enable error correction, for example adding parity bits to the data that allow errors to be detected and corrected downstream.

SUMMARY

Various embodiments of the present invention provide systems and methods for multi-level encoding and decoding.

A storage system includes a storage medium operable to maintain a data set, a read/write head assembly operable to write the data set to the storage medium and to read the data set from the storage medium, a multi-level encoder operable to encode the data set at a plurality of different code rates before it is written to the storage medium, and a multi-level decoder operable to decode the data set retrieved from the storage medium and to apply decoded values encoded at a lower code rate when decoding values encoded at a higher code rate.

This summary provides only a general outline of some embodiments of the invention. The phrases “in one embodiment,” “according to one embodiment,” “in various embodiments”, “in one or more embodiments”, “in particular embodiments” and the like generally mean the particular feature, structure, or characteristic following the phrase is included in at least one embodiment of the present invention, and may be included in more than one embodiment of the present invention. Importantly, such phrases do not necessarily refer to the same embodiment. This summary provides only a general outline of some embodiments of the invention. Additional embodiments are disclosed in the following detailed description, the appended claims and the accompanying drawings.

DETAILED DESCRIPTION OF THE INVENTION

Various embodiments of the present invention provide data processing systems with multi-level encoding and multi-level decoding in which data to be encoded is subdivided, with each resulting group of data encoded at a different code rate, and with the decoded data from some groups being used to guide decoding of other groups. In some embodiments, the multi-level encoding is a parallel coding scheme with several sub-codes of various code rates, where the code rate defines how many encoded output symbols are produced for a particular number of input symbols. Multi-level encoding and decoding can be used in any data processing system to provide benefits such as, but not limited to, reducing inter-symbol interference (ISI), including inter-track interference (ITI) in a magnetic storage device such as a hard disk drive. As the recording density is increased in magnetic storage, two-dimensional inter-symbol interference, or interference between bits or symbols in adjacent data tracks, increases. With the multi-level encoding, bits from all sub-codes are alternately recorded on the two-dimensional magnetic recording medium. The multi-level encoding and decoding makes use of soft information, or value probabilities, between decoders on different levels. The multi-level decoding results from a sub-code of a lower code rate is used to guide the detector of the next level to reduce the inter-symbol interference, improving detection. This reduces the two-dimensional inter-symbol interference level by level and provides pseudo-two dimensional detection, thereby providing improved bit error rate performance at the same overall code rate.

Turning toFIG. 1, a magnetic storage medium100for which two-dimensional inter-symbol interference can be reduced by multi-level encoding and decoding is depicted in accordance with some embodiments of the present invention. An example data track116and its two adjacent data tracks118,120are shown, indicated as dashed lines. The tracks116,118,120are segregated by servo data written within servo wedges112,114. It should be noted that while two tracks116,120and two servo wedges112,114are shown, hundreds of wedges and tens of thousands of tracks may be included on a given storage medium.

The servo wedges112,114include servo data130that is used for control and synchronization of a read/write head assembly over a desired location on storage medium100. In particular, the servo data130generally includes a preamble pattern132followed by a servo address mark134, followed by a Gray code136, a burst field138, and a repeatable run-out (RRO) field140. It should be noted that a servo data set may have two or more fields of burst information. Further, it should be noted that different information may be included in the servo fields. Between the servo data bit patterns130aand130b, a user data region142is provided. User data region142may include one or more sets of data that are stored to storage medium100. The data sets may include user synchronization information some of which may be used as a mark to establish a point of reference from which processing of the data within user data region142may begin.

In operation, storage medium100is rotated in relation to a sensor that senses information from the storage medium. In a read operation, the sensor would sense servo data from wedge112(i.e., during a servo data period) followed by user data from a user data region between wedge112and wedge114(i.e., during a user data period) and then servo data from wedge114. In a write operation, the sensor would sense servo data from wedge112then write data to the user data region between wedge112and wedge114, with location information in the user data region provided by a user sync mark144and a user preamble146.

Interference between symbols in a single data track116is referred to herein as one dimensional inter-symbol interference. Interference between symbols in neighboring tracks, such as interference from symbols in track120upon symbols in track116, or interference from symbols in track118upon symbols in track116, is referred to herein as two-dimensional inter-symbol interference or inter-track interference. The term “symbol” is used herein to refer to an object of data for which the value is detected in a data detector. A symbol can be a single bit or multiple bits in various embodiments. The multi-level encoding and decoding disclosed herein reduces the two-dimensional inter-symbol interference level by level between tracks (e.g.,120and116,118and116), providing pseudo-two dimensional detection and improved bit error rate performance at the same overall code rate.

Turning toFIG. 2, a storage system200is illustrated as an example application of multi-level encoding and decoding in accordance with some embodiments of the present invention. The storage system200includes a read channel circuit202with a multi-level encoder and decoder. Storage system200may be, for example, a hard disk drive. Storage system200also includes a preamplifier204, an interface controller206, a hard disk controller210, a motor controller212, a spindle motor214, a disk platter216, and a read/write head assembly220. Interface controller206controls addressing and timing of data to/from disk platter216. The data on disk platter216consists of groups of magnetic signals that may be detected by read/write head assembly220when the assembly is properly positioned over disk platter216. In one embodiment, disk platter216includes magnetic signals recorded in accordance with either a longitudinal or a perpendicular recording scheme.

In a typical read operation, read/write head assembly220is accurately positioned by motor controller212over a desired data track on disk platter216. Motor controller212both positions read/write head assembly220in relation to disk platter216and drives spindle motor214by moving read/write head assembly220to the proper data track on disk platter216under the direction of hard disk controller210. Spindle motor214spins disk platter216at a determined spin rate (RPMs). Once read/write head assembly220is positioned adjacent the proper data track, magnetic signals representing data on disk platter216are sensed by read/write head assembly220as disk platter216is rotated by spindle motor214. The sensed magnetic signals are provided as a continuous, minute analog signal representative of the magnetic data on disk platter216. This minute analog signal is transferred from read/write head assembly220to read channel circuit202via preamplifier204. Preamplifier204is operable to amplify the minute analog signals accessed from disk platter216. In turn, read channel circuit202decodes and digitizes the received analog signal to recreate the information originally written to disk platter216. This data is provided as read data222to a receiving circuit. As part of processing the received information, read channel circuit202performs multi-level decoding. A write operation is substantially the opposite of the preceding read operation with write data224being provided to read channel circuit202. This data is then encoded with a multi-level encoder and written to disk platter216. Such a multi-level encoder and decoder can be implemented consistent with that disclosed below in relation toFIGS. 3-7. In some embodiments, the multi-level encoding and decoding is performed consistent with the flow diagrams disclosed below in relation toFIGS. 8-9.

It should be noted that storage system200may be integrated into a larger storage system such as, for example, a RAID (redundant array of inexpensive disks or redundant array of independent disks) based storage system. Such a RAID storage system increases stability and reliability through redundancy, combining multiple disks as a logical unit. Data may be spread across a number of disks included in the RAID storage system according to a variety of algorithms and accessed by an operating system as if it were a single disk. For example, data may be mirrored to multiple disks in the RAID storage system, or may be sliced and distributed across multiple disks in a number of techniques. If a small number of disks in the RAID storage system fail or become unavailable, error correction techniques may be used to recreate the missing data based on the remaining portions of the data from the other disks in the RAID storage system. The disks in the RAID storage system may be, but are not limited to, individual storage systems such storage system200, and may be located in close proximity to each other or distributed more widely for increased security. In a write operation, write data is provided to a controller, which stores the write data across the disks, for example by mirroring or by striping the write data. In a read operation, the controller retrieves the data from the disks. The controller then yields the resulting read data as if the RAID storage system were a single disk.

In addition, it should be noted that storage system200may be modified to include solid state memory that is used to store data in addition to the storage offered by disk platter216. This solid state memory may be used in parallel to disk platter216to provide additional storage. In such a case, the solid state memory receives and provides information directly to read channel circuit202. Alternatively, the solid state memory may be used as a cache where it offers faster access time than that offered by disk platter216. In such a case, the solid state memory may be disposed between interface controller206and read channel circuit202where it operates as a pass through to disk platter216when requested data is not available in the solid state memory or when the solid state memory does not have sufficient storage to hold a newly written data set. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of storage systems including both disk platter216and a solid state memory.

Turning toFIG. 3, state graph300shows the inter-symbol interference between symbols stored in a two-dimensional pattern on a magnetic storage medium in accordance with some embodiments of the present invention. In state graph300, circles (e.g.,302,304) represent symbols stored on the magnetic storage medium, and lines (e.g.,306) between two circles represent inter-symbol interference between the two symbols represented by the circles. Inter-symbol interference occurs between a target symbol310and its preceding symbol312and following symbol314on a data track316. Inter-symbol interference occurs between target symbol310and neighboring symbols320,322,324,326,330,332on neighboring tracks334,336. When detecting the value of target symbol310, the effect of the eight neighboring symbols312,314, and320-332is accounted for in a simple and effective manner by the multi-level encoding and decoding. Notably, multi-level encoding and decoding may be applied to any two-dimensional pattern of symbols on a recording medium, and is not limited to use with the regular grid shown inFIG. 3.

Turning toFIG. 4A, a multi-level encoder400is depicted in accordance with some embodiments of the present invention. Data to be stored is received by serial to parallel converter404at input402, which separates the data into divided data406u1,414u2and422u3. Data at input402can have any content and can be derived from any suitable source. In some embodiments, divided data406,414and422are non-overlapping portions of the data at input402. In some embodiments, serial to parallel converter404operates as a multiplexer to alternately direct symbols at input402to different divided data signals406,414or422in streams. In some embodiments, data at input402is aggregated in a memory and separated by serial to parallel converter404using memory access techniques rather than stream separation. The serial to parallel converter404can include any circuitry to divide data at input402into multiple divided data signals406,414and422. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of serial to parallel converters that may be used in relation to different embodiments of the present invention. Furthermore, the multi-level encoder and decoder are not limited to the three levels disclosed in example embodiments herein.

The divided data406,414and422are each encoded at different code rates in data encoders410,416,424, yielding encoded data412,420,426. Data encoders410,416,424may be, but are not limited to, low density parity check encoder circuits or Reed Solomon encoder circuits as are known in the art. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of data encoder circuits that may be used in relation to different embodiments of the present invention. In some embodiments, data encoders410,416,424add parity symbols or check symbols to the data, enabling corresponding data decoders to detect and correct errors in retrieved copies of the data based on the parity symbols or check symbols. In some embodiments, data encoders410,416,424apply the same encoding algorithms but with different code rates. In some other embodiments, data encoders410,416,424apply different encoding algorithms. Encoder 1410encodes divided data406at code rate R1, encoder 2416encodes divided data414at code rate R2, and encoder 3424encodes divided data422at code rate R3, where R1<R2<R3. In some embodiments, R1=0.25, R2=0.5, and R3=0.75.

The encoded data412,420,426from data encoders410,416,424is merged or recombined by parallel to serial converter430, yielding encoded data432. Encoded data432is an encoded version of data at input402, having been encoded in multi-level encoder400with multiple code rates. The encoded data432can be in, but is not limited to, the same order as at input402. The encoded data432can be further processed if desired and stored in a storage device such as, but not limited to, a magnetic recording medium such as a hard disk drive platter.

Turning toFIG. 4B, a multi-level decoder440is depicted in accordance with some embodiments of the present invention. An analog signal450based on the encoded data432that has been retrieved from storage is sampled by analog to digital converter452to yield a series of digital samples454. In some embodiments, analog signal422is derived from a read/write head assembly (not shown) that is disposed in relation to a storage medium. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of source from which analog signal450may be derived. Analog to digital converter circuit452converts the analog signal450into a corresponding series of digital samples454. Analog to digital converter circuit452may be any circuit known in the art that is capable of producing digital samples corresponding to an analog input signal. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of analog to digital converter circuits that may be used in relation to different embodiments of the present invention.

The digital samples454are provided to an equalizer circuit456in some embodiments. Equalizer circuit454applies an equalization algorithm to the digital samples454to yield an equalized output458. In some embodiments of the present invention, equalizer circuit456is a digital finite impulse response filter circuit as are known in the art.

Again, the retrieved value of a symbol is affected by its neighboring bits due to inter-symbol interference. The equalized samples458from the output of a three-tap, two-dimensional equalizer456can be represented as:

where ym,nis the equalized sample for the symbol recorded at location m, n on a storage medium, where m is the track index, where n is the symbol index, where T represents the weight of the target symbol and its neighboring symbols, and where u represents the target symbol and its neighboring symbols. Track offset value i and symbol offset value j are used to reference the target symbol (where i and j=0) and its eight neighboring symbols. For a one-dimensional case having no inter-track interference, i would be 0.

The equalized samples458are provided to a serial to parallel converter460, which separates the equalized samples458into divided data462,474and486. Divided data462contains equalized samples corresponding to divided data406u1, which was encoded at code rate R1. Divided data474contains equalized samples corresponding to divided data414u2, which was encoded at code rate R2. Divided data486contains equalized samples corresponding to divided data422u3, which was encoded at code rate R3. In some embodiments, serial to parallel converter460operates as a multiplexer to alternately direct symbols in equalized samples458to different divided data signals462,474and486in streams. In some embodiments, equalized samples458are aggregated in a memory and separated by serial to parallel converter460using memory access techniques rather than stream separation. The serial to parallel converter460can include any circuitry to divide equalized samples458into multiple divided data signals462,474and486. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of serial to parallel converters that may be used in relation to different embodiments of the present invention. Furthermore, the multi-level encoder and decoder are not limited to the three levels disclosed in example embodiments herein.

Multiple data detectors464,476,488are included in the multi-level decoder440. Data detectors464,476,488are operable to apply a data detection algorithm to an input data set to detect values of the data set. In some embodiments of the present invention, data detector464is a Viterbi algorithm data detector circuit as are known in the art. In other embodiments of the present invention, data detector464is a maximum a posteriori data detector circuit as are known in the art. Of note, the general phrases “Viterbi data detection algorithm” or “Viterbi algorithm data detector circuit” are used in their broadest sense to mean any Viterbi detection algorithm or Viterbi algorithm detector circuit or variations thereof including, but not limited to, bi-direction Viterbi detection algorithm or bi-direction Viterbi algorithm detector circuit. Also, the general phrases “maximum a posteriori data detection algorithm” or “maximum a posteriori data detector circuit” are used in their broadest sense to mean any maximum a posteriori detection algorithm or detector circuit or variations thereof including, but not limited to, simplified maximum a posteriori data detection algorithm and a max-log maximum a posteriori data detection algorithm, or corresponding detector circuits. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of data detector circuits that may be used in relation to different embodiments of the present invention. Upon completion, data detectors464,476,488provide detected outputs466,478,490which include soft data. As used herein, the phrase “soft data” is used in its broadest sense to mean reliability data with each instance of the reliability data indicating a likelihood that a corresponding bit position or group of bit positions has been correctly detected. In some embodiments of the present invention, the soft data or reliability data is log likelihood ratio data as is known in the art.

Multiple data decoders468,480,492are also included in the multi-level decoder440. The data decoders468,480,492used in various embodiments may be any type of decoders to reverse the encoding performed by data encoders410,416,424, such as, but not limited to, low density parity check decoder or Reed Solomon decoders, which are each operable to decode data encoded at a different code rate as it was encoded. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of data decoder circuits that may be used in relation to different embodiments of the present invention. The data decoders468,480,492apply data decode algorithms to decoder inputs466,478,490in a variable number of local decoding iterations. In some embodiments, data decoders468,480,492and their corresponding data detectors464,476,488also perform a variable number of global detection/decoding iterations, with the detector (e.g.,464) applying the data detection algorithm to the divided data input462with guidance from decoded output from the decoder (e.g.,468) generated during a previous global iteration.

The divided data462for code rate R1from serial to parallel converter460is provided to data detector464, which applies a data detection algorithm to divided data462to yield detected values466. The detected values466are provided to decoder468, which applies a data decoding algorithm to detected values466, reversing the encoding performed in encoder410, and yielding a soft decoder output472and a hard decision output470û1. The soft decoder output472contains likelihood information about each possible value for each symbol, and hard decision output470contains the most likely value of each symbol. Hard decision output470û1thus corresponds to divided data406u1, either exactly or to the best of the ability of the data detector464and decoder468to determine.

The soft decoder output472is used by data detector476in some embodiments in the same manner that data detector476applies soft information from data decoder480to guide the detection process for divided data474. For example, if the soft decoder output472indicates that the neighboring symbols have a value of +1, and given that the effect that inter-symbol interference by a symbol with a value of +1 in a particular system has on a target symbol is known, then that interference value is subtracted from the soft output for the target symbol to remove the interference. In some embodiments, the interference values are subtracted from the soft values in the detector before they are output from the detector. This removes the interference, as long as the decision for the interfering symbol was correct.

The divided data474for code rate R2from serial to parallel converter460is provided to data detector476, which applies a data detection algorithm to divided data474to yield detected values478. During the data detection process, the data detector476reverses the effect on divided data474from neighboring symbols, based on the soft decoder output472from decoder468. Because the divided data406u1was encoded at the lowest code rate R1, it has a greater level of redundancy than divided data474. This greater level of redundancy increases the likelihood that the soft decoder output472and hard decision output470will be correct, even though inter-symbol interference is not cancelled in the first decoding level that yields soft decoder output472and hard decision output470. The interference from the symbols in divided data462on the symbols in divided data474can therefore be cancelled out or reduced in data detector476.

The detected values478are provided to decoder480, which applies a data decoding algorithm to detected values478, reversing the encoding performed in encoder416, and yielding a soft decoder output484and a hard decision output482û2. The soft decoder output484contains likelihood information about each possible value for each symbol, and hard decision output482contains the most likely value of each symbol. Hard decision output482û2thus corresponds to divided data414u2.

The divided data486for code rate R3from serial to parallel converter460is provided to data detector488, which applies a data detection algorithm to divided data486to yield detected values490. During the data detection process, the data detector488reverses the effect on divided data486from neighboring symbols, based on the soft decoder output484from decoder480. Because the divided data474u2was encoded at a lower code rate R2than the code rate R3of divided data486, it has a greater level of redundancy than divided data486. The interference from the symbols in divided data474and divided data462on the symbols in divided data486can therefore be cancelled out or reduced in data detector488.

The detected values490are provided to decoder492, which applies a data decoding algorithm to detected values490, reversing the encoding performed in encoder424, and yielding a hard decision output494û3. The hard decision output494contains the most likely value of each symbol. Hard decision output494û2thus corresponds to divided data422u3.

Although the lower code rate levels of decoding that yield hard decision outputs482and494are at least partially dependent on earlier levels, the detection and decoding operations can be performed at least partially in parallel in some embodiments. For example some detection and decoding iterations in detector476and decoder480can be performed while detector464and decoder468are still operating on divided data462, with the soft decoder output472from decoder468being applied in data detector476as soon as the data has converged and decoding is complete in decoder468. In some other embodiments, the soft decoder output472from decoder468is applied in data detector476before the data has converged and decoding is complete in decoder468, as soon as at least one iteration is complete in decoder468and soft decoder output472is available. In yet other embodiments, each level or stage waits to begin until decoding is complete in the previous level stage, where a decoder stage in some embodiments of the multi-level decoder440includes a data detector and data decoder.

The hard decision outputs470,482,494from data decoders468,480,492are merged or recombined by parallel to serial converter496, yielding hard decisions498, which correspond to data at input402provided to multi-level encoder400. The hard decisions498can be further processed if desired and output for use. For example, in some embodiments, the multi-level encoding and decoding is performed on a sector-by-sector basis, with an entire decoded sector being output as hard decisions498once the data for the sector has converged in all three decoders468,480,492.

Turning toFIG. 5, the recording pattern500on a storage medium for data encoded by a multi-level encoder is depicted in accordance with some embodiments of the present invention. The serial to parallel converter404and parallel to serial converter430divide the data into portions to be encoded with different code rates in an order that causes data to be recorded on the storage medium in a pattern such as inFIG. 5. This enables a multi-level decoder to apply the soft information from lower level decoding to subsequent level decoding to cancel or reduce the effects of inter-symbol interference. Data encoded at different code rates is thus interleaved when written to the disk so that the values of symbols encoded at lower code rates can be determined and the interference they have on neighboring symbols encoded at higher code rates can be cancelled or reduced. The symbols encoded at code rate R1are represented inFIG. 5by circles (e.g.,502) marked as number 1, the symbols encoded at code rate R2are represented by circles (e.g.,504) marked as number 2, and the symbols encoded at code rate R3are represented inFIG. 5by circles (e.g.,506) marked as number 3. In some embodiments, the recording pattern places symbols encoded at the highest code rate on alternating tracks510,512,514, and on the intervening tracks516,518, alternates symbols encoded at the lower code rates. However, the multi-level encoding and decoding is not limited to the pattern shown inFIG. 5, but can be used with any recording pattern that reduces the effect of two-dimensional inter-symbol interference during the detection process.

The serial to parallel and parallel to serial conversion is thus based at least in part on the location at which each symbol will be stored on the magnetic storage medium. For example, if the data corresponds entirely to a data sector being written to a track (e.g.,512) that is assigned code rate 3, the data will all be encoded by encoder 3424at code rate 3, and the serial to parallel converter404will direct all symbols from input402to data stream422. If the data corresponds entirely to a data sector being written to a track (e.g.,516) that is assigned to code rates 1 and 2, the serial to parallel converter404will alternately direct each successive symbol from input402to data stream406or data stream414. If the data will span two adjacent tracks, the serial to parallel converter404will direct symbols from input402to each of the data streams406,414,422according to their target storage locations to yield the pattern shown inFIG. 5or in any other pattern that reduces the effect of two-dimensional inter-symbol interference when detecting the values of retrieved data.

Turning toFIG. 6, a channel model600shows the two-dimensional inter-symbol interference remaining after the first detection and decoding level. Notably, the effect of symbols encoded at code rate R1on symbols encoded at code rates R2and R3has been cancelled. The cancelled two-dimensional inter-symbol interference from symbols encoded at code rate R1is shown by dashed lines (e.g.,602).

Turning toFIG. 7, a channel model700shows the one-dimensional inter-symbol interference remaining after the second detection and decoding level. Notably, the effect of symbols encoded at code rates R1and R2on symbols encoded at code rate R3has been cancelled. The cancelled two-dimensional inter-symbol interference from symbols encoded at code rates R1and R2is shown by dashed lines (e.g.,702). The multi-level encoding and decoding thus cancels or reduces two-dimensional inter-symbol interference without requiring a two-dimensional detector. Symbols encoded at code rates R1and R2will also benefit from the multi-level encoding and decoding even though the inter-symbol interference of higher code rate encoded symbols is not cancelled on lower code rate encoded symbols, because of the lower code rates and greater redundancy. Thus, bit error rate performance is improved without increasing the overall code rate.

Turning toFIG. 8, flow diagram800discloses a method for multi-level data encoding in accordance with one or more embodiments of the present invention. Following flow diagram800, a data input is received (block802). The data input is divided into multiple data segments (block804). The data input is divided such that, when recombined and recorded on a storage medium, symbols having been encoded at different data rates will be interspersed in a pattern allowing two-dimensional inter-symbol interference to be cancelled during a multi-level detection process. Each of the data segments is encoded at a different code rate, yielding encoded data segments (block806). The encoded data segments are combined to yield an encoded data output (block808). The encoded data output can then be recorded on a storage medium such as a magnetic hard disk platter.

Turning toFIG. 9, flow diagram900discloses a method for multi-level data decoding in accordance with one or more embodiments of the present invention. Following flow diagram900, encoded data samples are divided into multiple data segments, each having been encoded at a different code rate (block902). Values of the data segment encoded at lowest data rate are determined (block904). In some embodiments, this includes performing a data detection process such as, but not limited to, a Viterbi or maximum a posteriori detection algorithm, and a data decoding process such as, but not limited to, a low density parity check or Reed Solomon decoding algorithm. Values of the data segment encoded at the next higher data rate are determined, subtracting out interference from symbols at the next lower data rate (block906). A determination is made as to whether all levels have been decoded, or whether a data segment encoded at a higher data rate remains (block908). If not, the process continues at block906for the data segment encoded at the next higher data rate. When all levels have been processed, the values of data segments encoded at each different data rate are combined, yielding decoded data (block910). The decoded data may then be output (block912) or processed further.