Maximum likelihood timing synchronizers for sampled PSK burst TDMA system

A method of producing a correction signal includes receiving a predetermined data sequence (500). The data sequence is sampled at predetermined times, thereby producing a sampled data sequence (522, 532). The sampled data sequence is separated into first and second sampled data sequences. A ratio is calculated (550, 558) from the first and second sampled data sequences. A correction signal is produced (556, 564) in response to the ratio.

FIELD OF THE INVENTION

This invention relates to time division multiple access (TDMA) for a communication system and more particularly to a method for synchronizing carrier phase and symbol timing in a mobile receiver.

BACKGROUND OF THE INVENTION

Present time division multiple access (TDMA) systems are characterized by simultaneous transmission of different data signals over a common channel by assigning each signal a unique time period. These data signals are typically transmitted as binary phase shift keyed (BPSK) or quadrature phase shift keyed (QPSK) data symbols during such unique time periods. These unique periods are allocated to a selected receiver to determine the proper recipient of a data signal. Allocation of such unique periods establishes a communication channel between a transmitter and selected remote receivers for narrow band transmission. This communication channel may be utilized for cable networks, modem transmission via phone lines or for wireless applications.

A selected TDMA receiver must determine both carrier phase and symbol timing of its unique period from the received signal for data recovery. The carrier phase is necessary for generating a reference carrier with the same phase as the received signal. This reference carrier is used to coherently demodulate the received signal, thereby creating a baseband signal. Symbol timing synchronization of the receiver with the transmitter is necessary for the receiver to extract correct data symbols from the baseband signal.

Previous studies, such as J. G. Proakis,Digital Communications347–350 (1995), have utilized decision-directed phase locked loops (PLL) to estimate carrier phase. An exemplary decision-directed phase-locked loop (PLL) circuit of the prior art is shown atFIG. 1. The circuit receives baseband signal r(t) at lead100. Respective quadrature carriers at leads104and108developed from voltage-controlled oscillator (VCO) circuit132are multiplied by the received signal. The product signal is integrated over symbol time T by integrator112and sampled by circuit114according to the symbol time base circuit116. Decision circuit118produces output signal A(t) at lead120. A product signal from multiplier circuit110is delayed by circuit124to compensate for the decision circuit delay. The signals at leads120and126are multiplied by circuit122to produce error signal e(t) at lead128. This error signal is filtered by loop filter circuit130to eliminate double frequency components and applied to VCO circuit132. Problems with the PLL circuit ofFIG. 1when used for phase estimation, however, include circuit complexity and likelihood of hang-up. Furthermore, the circuit of Proakis requires synchronization circuitry to correctly sample each symbol near the center of the respective symbol time.

Other studies determine maximum likelihood (ML) estimates for symbol timing by calculating a derivative of a matched filter output signal. Id. at 359–361. Referring toFIG. 2, there is, a circuit of the prior art that receives baseband signal r(t) on lead100. The baseband signal is filtered by matched filter202. Circuit204then calculates a derivative of the signal, which is then sampled by circuit206according to voltage-controlled clock (VCC) circuit220. Circuit212then multiplies the derivative at lead208by the known symbol sequence Inat lead210. The product of this multiplication is summed by circuit216and applied to the VCC circuit220. A limitation of this circuit, however, is that calculation of a matched filter output derivative for symbol timing synchronization is not possible with modern digital receivers which work on sampled data input signals. Another study by L. E. Franks,Carrier and Bit Synchronization in Data Communication-A Tutorial Review, IEEE Trans. on Communications, August 1980 1107, 1117, teaches a method for joint tracking of both carrier phase and symbol timing. Therein (FIG. 9), Franks teaches a circuit that combines a PLL for carrier phase determination and a circuit to calculate a derivative of a low pass filter output. This method, therefore, is subject to the same limitations of the previously discussed methods.

SUMMARY OF THE INVENTION

These problems are resolved by a method of producing a correction signal by receiving a predetermined data sequence. The data sequence is sampled at predetermined times, thereby producing a sampled data sequence. The sampled data sequence is separated into first and second sampled data sequences. A ratio is calculated from the first and second sampled data sequences. A correction signal is produced in response to the ratio.

The present invention improves reception and reduces circuit complexity by providing maximum likelihood carrier phase and symbol timing correction signals. The method improves bit error rate compared to methods of the prior art and is comparable to the Cramer-Rao bound.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring now toFIG. 5, a received baseband signal y(t) given by equation [1] is applied to lead500. This baseband signal is preferably a quadrature phase shift keyed (QPSK) signal of discrete symbols received from a remote base station transmitter. Input signal samples Iiinclude in-phase (I real) and quadrature (Q imaginary) components of the sampled training data ofFIG. 3A.

This training data is a sequence of unique data words transmitted as a preamble or midamble by the remote base station to the receiver. Referring toFIG. 3B, the samples are designated full samples wiand yiof the I and Q components and half samples xiand ziof the I and Q components, respectively, for the training data sequence { . . . (1+j),−(1+j),(1+j),−(1+j), . . . }. By convention, the full samples are assumed near the center of the symbol time T and the half samples are assumed near a boundary between symbols. Samples of the received signal are treated as an infinite series for purposes of the following discussion.y⁡(t)=∑i=-∞i=∞⁢Ii⁢g⁡(t-iT-τ)⁢ⅇjϕ+n⁡(t)[1]

The received baseband signal is filtered by a transmit pulse shaping filter502having a filter characteristic g(t) and having a shaping factor of α≧0.2. Simulations show small degradation of finite-length sequences compared to idealized infinite-length sequences with this shaping factor constraint. The filter is typically a square root raised cosine (RC) filter having a characteristic as inFIG. 4. The output of the RC filter is given in equation [2]. Both carrier phase φ and symbol timing τ must be determined from samples of the received signal to recover the I and Q components of the signal transmitted by the base station. The symbol timing error ofFIG. 4showing a positive value for τ, indicates the time of the full sample prior to the center of the symbol time t/T. The range of τ is determined by (2i−1)/2≦(t−τ)/T≦(2i−1)/2, having an absolute value of τ≦T/2, where T is the symbol time period. The filter function ofFIG. 4is given by equation [3] where −T/2≦t≦T/2.r⁡(t)=rl⁡(t)+jrQ⁡(t)=(Iil+jIiQ)⁢f⁡(t-iT-τ)⁢ⅇjϕ+N⁡(t)[2]f⁢(t)=∑i=-∞i=∞⁢Iil⁢h⁡(t-iT)[3]

The received signal is applied to multiplier circuits506and514. A free-running local oscillator circuit516produces a reference carrier signal on lead512. This reference carrier is multiplied by the received signal to produce a quadrature signal that is applied to low pass filter circuit528. A time synchronization circuit524produces a clock signal on lead526having twice the frequency of the symbol frequency transmitted signal from the base station. This clock signal on lead526is applied to analog-to-digital converter (ADC) circuit530. The ADC takes two samples of the quadrature signal corresponding to each symbol period T and produces a digital sample on lead532given by equation [4]. Likewise, the ADC circuit520takes two samples of the in-phase signal corresponding to each symbol period T and produces a digital sample on lead522. The samples on either of lead522and532, therefore, include sample sequences given by equations [5] and [6], corresponding to full-symbol and half-symbol samples and their respective noise terms.
r(l)=Iiƒ(lTS−iT−τ)ejφ+N(l)  [4]
rƒ(l)=I1ƒ(−τ)ejφ+Nƒ(l)  [5]
rh(l)=I1ƒ(TS−τ)ejφ+Nh(l)  [6]

Operation of sum circuits534,538,566and568and ratio circuits550and558will now be explained in detail. If the received signal is rewritten as a vector R including full and half samples as in equation [7], then the mean or expected value E[R] of these samples after filtering is given by equation [8]. Furthermore, the covariance H is given by equation [9]. The matrix I is an L×L unity matrix. The matrix B is an L×L correlation matrix with elements having an expected value given by βjk=h(2(j−k)+1)TS), j, k=0, . . . ,L−1, where the function h(t)=g(t)*g(−t) is the RC filter response. The superscript *T in the following discussion denotes a conjugate transpose or Hermitian matrix.

The matrix inversion lemma of equation [10] is applied to equation [9] to produce inverted covariance matrix H−1in equation [11], where Γ=(I−BB*T)−1and Ψ=(I−B*TB)−1.R⁢⌊rf⁡(0),rf⁡(1),…⁢,rf⁡(L-1),rh⁡(0),rh⁡(1),…⁢,rh⁡(L-1)⌋[7]E⁡[R]=[[I0,I1,…⁢,IL-1]⁢f⁡(-τ),[I0,I1,…⁢,IL-1]⁢f⁡(TS-τ)]⁢ⅇjϕ[8]H=E⁡[(R-E⁡[R])*⁢T⁢(R-E⁡[R])]=N0⁢IB*⁢TBI[9](I-B*⁢T⁢B)-1=I+B*⁢T⁡(I-BB*⁢T)-1⁢B[10]H-1=I+B*⁢T⁢Γ⁢⁢B-B*⁢T⁢Γ-B⁢⁢ΨI+B⁢⁢ΨB*⁢T[11]

The maximum likelihood (ML) estimate of φ is a value that satisfies equation [12]. Thus, the real part of the partial derivative in equation [13] must also be equal to zero. Since received vector R is independent of φ, its partial derivative is zero resulting in equation [14]. A substitution of equations [11] and [14] into equation [13] produces equation [15].∂∂ϕ⁢((R-E⁡[R])⁢H-1⁡(R-E⁡[R])*⁢T)=0[12]R⁢{(∂∂ϕ⁢(R-E⁡[R]))⁢H-1⁡(R-E⁡[R])*⁢T}=0[13]-∂∂ϕ⁢E⁡[R]=-j[[I0,I1,…⁢,IL-1]⁢f⁡(-τ),⁢[I0,I1,…⁢,IL-1]⁢f⁡(TS-τ)⁢ⅇjθ=-jE⁡[R][14]R⁢{-j⁡(∂∂ϕ⁢E⁡[R])⁢I+B*⁢T⁢Γ⁢⁢B-B*⁢T⁢Γ-B⁢⁢ΨI+B⁢⁢Ψ⁢⁢B*⁢T⁢(R-E⁡[R])*⁢T}=0[15]

A simplification of equation [16] is applied to equation [15], thereby producing equation [17]. This simplification is appropriate, since sums of respective full and half samples of known training data alternate between +1 and −1. Thus, for large L, matrix products [I0, . . . , IL−1]B≈0 and [I0, . . . , IL−1]BT≈0.E⁡[R]⁢H-1=E⁡[R]N0⁢I+B*⁢T⁢Γ⁢⁢B-B*⁢T⁢Γ-B⁢⁢ΨI⁢+B⁢⁢Ψ⁢⁢B*⁢T≈E⁡[R]N0⁢I00I=E⁡[R]N0[16]R⁢{-j⁢⁢E⁡[R]⁢R*⁢T}=0[17]

Sum circuits534, and542calculate respective I and Q sums for φ according to equation [18], where I1=I11+jI1Q, A,Bε{I,Q}, and Dε{f,h}. Thus, real and imaginary values of variables on the right side of equation [18] are indicated by I and Q subscripts, respectively. Substitution of equation [7] and [8] in summation form of equation [18] for respective matrices R and expected value E[R] yields equation [19]. Equation [19] is rewritten as equation [20] to further explain circuit operation. Ratio circuit550receives respective I and Q sums on leads536and544. The ratio circuit also receives current values for ƒ({circumflex over (τ)}) and ƒ(TS−τ) on lead564as will be explained in detail. The ratio circuit550then calculates the ratio on the right side of equation [20] and applies the calculated ratio to lead552. The ROM lookup table554receives the calculated ratio on lead552and responsively produces carrier phase estimate φ on lead556.SABD=∑l=0L-1⁢rAD⁡(l)⁢IBlD[18]sin⁢⁢ϕ⁢{f⁡(-τ)⁢(Sllf+SQQf)+f⁡(TS-τ)⁢(Sllh+SQQh)}-⁢cos⁢⁢ϕ⁢{f⁡(-τ)⁢(SOIf+SIQf)+f⁡(TS-τ)⁢(SQIh+SIQh)}=0[19]tan⁢⁢ϕ=f⁡(-τ)⁢(SQIf+SIQf)+f⁡(TS-τ)⁢(SQIh+SIQh)f⁡(-τ)⁢(SIIf+SQQf)+f⁡(TS-τ)⁢(SIIh+SQQh)[20]

The desired ML estimate for τ is the value that satisfies equation [21] The real part of equation [21], therefore, must also be satisfied according to equation [22]. Substitution of equation [23] and the previously discussed simplification of equation [24] yields equation [25]. A further substitution of received matrix R full and half samples into equation [25] yields equation [26].∂∂τ⁢((R-E⁡[R])⁢H-1⁡(R-E⁡[R])*T)=0[21]R⁢{(∂∂τ⁢(R-E⁡[R]))⁢H-1⁡(R-E⁡[R])*T}=0[22]∂∂τ⁢(R-E⁡[R])=-j⁡[[I0,I1,…⁢,IL-1]⁢f′⁡(-τ),[I0,I1,…⁢,IL-1]⁢f′⁡(Ts-τ)]⁢ⅇj⁢⁢θ[23](∂∂τ⁢E⁡[R])⁢H-1≈1N0⁢(∂∂τ⁢E⁡[R])⁢I00I=1N0⁢∂∂τ⁢E⁡[R][24]f′⁡(-τ^)⁢[-(SIIf-SQQf)⁢cos⁢⁢ϕ+(SIQf-SQIf)⁢sin⁢⁢ϕ-∑l=0L-1⁢Il2⁢f⁡(-τ^)]+⁢f′⁡(TS-τ^)⁡[-(SIIh-SQQh)⁢cos⁢⁢ϕ+(SIQh-SQIh)⁢sin⁢⁢ϕ-∑l=0L-1⁢Il2⁢f⁡(TS-τ^)]=0[25]
noise+[ƒ′(−{circumflex over (τ)})ƒ(−τ)+ƒ′(TS−{circumflex over (τ)})ƒ(TS−τ)]−[ƒ′(−{circumflex over (τ)})ƒ(−{circumflex over (τ)})+ƒ′(TS−{circumflex over (τ)})ƒ(TS−{circumflex over (τ)})]=0  [26]

The terms ƒ′(−{circumflex over (τ)})ƒ(−{circumflex over (τ)})+ƒ′(TS−{circumflex over (τ)})ƒ(TS−{circumflex over (τ)}) of equation [26] are small and may be neglected. A further simplification of equation [26], given in equation [27], is possible for RC filters having a shaping factor α≧0.2 as previously described. This simplification yields equation [28]. Sum circuits538and546calculate respective symbol timing sums as previously described for the carrier phase estimate. The ratio circuit558receives these sums on leads540and548and calculates the ratio in the center term of equation [28]. The function q(−{circumflex over (τ)}), defined by equation [30], is substituted into equation [28] and yields quadratic equation [30]. This quadratic equation has one positive and one negative real root. The positive real root corresponds to the desired ML estimate for τ. This positive real root is calculated by ratio circuit558and applied to ROM lookup table562via lead560. The contents of ROM lookup table562correspond to values of the function q(−{circumflex over (τ)}) inFIG. 6. The ROM lookup table produces the corresponding τ on lead564.∂∂τ⁢(f2⁡(-τ)+f2⁡(TS-τ))=f′⁡(-τ)⁢f⁡(-τ)+f′⁡(TS-τ)⁢f⁡(TS-τ)≈0[27]f⁡(-τ^)f⁡(TS-τ^)-f⁡(TS-τ^)f⁡(-τ^)=(SIIf+SQQf)2-(SIIh+SQQh)2+(SIQf+SQIf)2-(SIQh+SQIh)2(SIIf+SQQf)⁢(SIIh+SQQh)+(SIQf+SQIf)⁢(SIQh+SQIh)≡Δ[28]q⁡(-τ^)=f⁡(-τ^)f⁡(TS-τ^)[29]q2⁡(-τ^)-Δ⁢⁢q⁡(-τ^)-1=0[30]

Interpolate circuits566and568receive respective I and Q signal samples on leads522and532together with the ML symbol estimate corresponding τ on lead564. The interpolate circuits correct the symbol timing of the signal samples according to the ML estimate of τ and produce corrected I and Q signal samples on leads570and572, respectively. Derotate circuit574receives the corrected signal samples together with the ML carrier phase estimate φ on lead556. The derotate circuit produces phase corrected I and Q signal samples on leads576and578, respectively, in response to the ML carrier phase estimate φ.

Turning now toFIGS. 7A–7D, there are Monte-Carlo simulations of the ML carrier phase estimate of the present invention for various parameters compared to the Cramer-Rao bound. The Cramer-Rao bound is significant as a theoretical limit. The upper curves in each simulation show a 32-sample sequence compared to a 64-sample sequence. The 64-sample sequence improves the bit error rate by approximately 3 dB for each parameter set. Each simulation, however, shows performance of the present ML estimator is very close to the Cramer-Rao bound. Referring toFIG. 8A–8D, corresponding Monte-Carlo simulations of the ML symbol timing estimate show approximately the same result. The worst-case difference of symbol timing estimate ofFIG. 8Ashows the present ML error is within 0.5 dB of the Cramer-Rao bound. Finally, referring toFIGS. 9A–9B, performance of the present ML estimator is compared to Gardner's method, presented in Gardner, A BPSK/QPSKtiming-error detector for sampled receivers, IEEE Trans. on Communications, May 1986, at 423. The simulation ofFIG. 9Afor α=0.5, τ/T=0.1 and φ=π/8, shows a 4 dB improvement over Gardner's method. The simulation ofFIG. 9Bfor α=0.5, τ/T=0.05 and φ=π/4, including a smaller symbol time error and a larger carrier phase error, shows a 2 dB improvement over Gardner's method.

The ML estimates of the present invention are highly advantageous with respect to methods of the prior art for several reasons. First, the bit error rate of the present ML estimate is substantially lower than previous methods. Second the present invention resolves all ambiguities of sampled data. Positions of the full and half data samples are inconsequential to the present method and long as the positive root of equation [30] is selected. Third, the present invention avoids the complexity of PLL circuits of the prior art and avoids hangup. Finally, the ML estimate signals are derived from a ratio of signal samples. Thus, they are insensitive to signal strength and do not require automatic gain control (AGC).

Although the invention has been described in detail with reference to its preferred embodiment, it is to be understood that this description is by way of example only and is not to be construed in a limiting sense. For example, the present invention may be easily applied to a BPSK system of alternating ones and zeros for the in-phase component and zero for the quadrature component. Moreover, many functions the present invention may be performed by a digital signal processor or other processor as will be understood by those of ordinary skill in the art having access to the present specification.

It is to be further understood that numerous changes in the details of the embodiments of the invention will be apparent to persons of ordinary skill in the art having reference to this description. It is contemplated that such changes and additional embodiments are within the spirit and true scope of the invention as claimed below.