DISPLAY DEVICE AND GRAYSCALE COMPENSATION METHOD THEREOF

A display device and a grayscale compensation method thereof. The display device includes a data conversion circuit, a voltage drop estimation circuit, and a compensation circuit. The data conversion circuit converts a plurality of original grayscale data of a target pixel block into current data. The voltage drop estimation circuit converts the current data into transmission line voltage drop information of the target pixel block. The compensation circuit converts the transmission line voltage drop information into at least one pixel compensation value of the target pixel block, and uses the at least one pixel compensation value to compensate the original grayscale data of the target pixel block, so as to generate a plurality of compensated grayscale data of the target pixel block.

BACKGROUND

Technical Field

The disclosure relates to an electronic device. Particularly, the disclosure relates to a display device and a grayscale compensation method thereof.

Description of Related Art

A source driver may drive a plurality of data lines of a display panel. Because of the impedance of the data line, there may be different voltage drops (also referred to as IR drops) at different positions of the data line. For example, among a plurality of sub-pixels connected to the same data line, there may be a more serious voltage drop in a sub-pixel farther away from the source driver (the signal source), and there may be a slighter voltage drop in a sub-pixel closer to the source driver.

In addition, a plurality of data lines of a large-sized display panel are typically connected to a plurality of source drivers. A power circuit may supply power to these source drivers through a source driver power line. Therefore, because of the impedance of the source driver power line, there may also be different voltage drops at different positions of the source driver power line. For example, among a plurality of source drivers connected to the same source driver power line, there may be a more serious voltage drop in a source driver farther away from the power circuit (the power source), and there may be a slighter voltage drop in a source driver closer to the power circuit.

SUMMARY

The disclosure provides a display device and a grayscale compensation method thereof to compensate a voltage drop of a transmission line.

In an embodiment of the disclosure, the display device includes a data conversion circuit, a voltage drop estimation circuit, and a compensation circuit. The data conversion circuit is configured to convert a plurality of original grayscale data of a target pixel block into current data. The voltage drop estimation circuit is coupled to the data conversion circuit to receive the current data of the target pixel block. The voltage drop estimation circuit is configured to convert the current data into transmission line voltage drop information of the target pixel block. The compensation circuit is coupled to the voltage drop estimation circuit to receive the transmission line voltage drop information of the target pixel block. The compensation circuit is configured to convert the transmission line voltage drop information into at least one pixel compensation value of the target pixel block, and uses the at least one pixel compensation value to compensate the plurality of original grayscale data of the target pixel block, so as to generate a plurality of compensated grayscale data of the target pixel block.

In an embodiment of the disclosure, the grayscale compensation method includes the following. A plurality of original grayscale data of a target pixel block are converted into current data by a data conversion circuit of the display device. The current data is converted into transmission line voltage drop information of the target pixel block by a voltage drop estimation circuit of the display device. The transmission line voltage drop information is converted into at least one pixel compensation value of the target pixel block by a compensation circuit of the display device. The at least one pixel compensation value is used to compensate the plurality of original grayscale data of the target pixel block by the compensation circuit, so as to generate a plurality of compensated grayscale data of the target pixel block.

Based on the foregoing, the display device in the embodiments of the disclosure may convert the original grayscale data into the current data, and then convert the current data into the transmission line voltage drop information. The display device may convert the transmission line voltage drop information into the pixel compensation value, and use the pixel compensation value to compensate the original grayscale data. Therefore, the display device may compensate the voltage drop of the transmission line.

DESCRIPTION OF THE EMBODIMENTS

The term “coupling (or connection)” used throughout this specification (including the claims) may refer to any direct or indirect means of connection. For example, if it is herein described that a first device is coupled (or connected) to a second device, it should be interpreted that the first device may be directly connected to the second device, or the first device may be indirectly connected to the second device through other devices or some connection means. Terms such as “first” and “second” mentioned throughout this specification (including the claims) are used to name elements, or to distinguish between different embodiments or scopes, and are not used to limit the upper or lower bound of the number of elements, nor used to limit the sequence of elements. In addition, wherever possible, elements/members/steps using the same reference numerals in the drawings and embodiments denote the same or similar parts. Cross-reference may be made to relevant descriptions of elements/members/steps using the same reference numerals or using the same terms in different embodiments.

FIG.1is a schematic circuit block diagram of a display device100according to an embodiment of the disclosure. The display device100shown inFIG.1includes a display panel110, source drivers120_1to120_n, and a power circuit130. All pixels of the display panel110may be divided into a plurality of pixel blocks depending on the actual design. Each pixel block includes a plurality of pixels. The source drivers120_1to120_n may drive a plurality of data lines (transmission lines) of the display panel110. Because of the impedance of the data line, there may be different voltage drops (also referred to as IR drops) at different positions of the data line. For example, among a plurality of pixels connected to the same data line, there may be a more serious voltage drop in a sub-pixel farther away from the source driver (the signal source), and there may be a slighter voltage drop in a sub-pixel closer to the source driver.

Based on the actual applications, the number n of the source drivers120_1to120_n may be any integer. The plurality of source drivers120_1to120_n may drive the large-sized display panel110. The power circuit130may supply power to the source drivers120_1to120_n through a source driver power line (a transmission line). Because of the impedance of the source driver power line, there may also be different voltage drops at different positions of the source driver power line. For example, among the plurality of source drivers120_1to120_n connected to the same source driver power line, there may be a more serious voltage drop in a source driver farther away from the power circuit130(the power source), and there may be a slighter voltage drop in a source driver closer to the power circuit130.

FIG.2is a schematic circuit block diagram of a display device200according to an embodiment of the disclosure. The display device200shown inFIG.2includes a data conversion circuit210, a voltage drop estimation circuit220, a compensation circuit230, a driving circuit240, and a display panel250. The driving circuit240may drive a plurality of data lines (not shown inFIG.2) of the display panel250. Reference may be made to the relevant description of the display device100shown inFIG.1for the display device200shown inFIG.2, reference may be made to the relevant description of the source drivers120_1to120_n shown inFIG.1for the driving circuit240shown inFIG.2, and reference may be made to the relevant description of the display panel110shown inFIG.1for the display panel250shown inFIG.2, which will thus not be repeatedly described.

Based on the actual design, in some embodiments, the data conversion circuit210, the voltage drop estimation circuit220, the compensation circuit230, and the drive circuit240may be integrated in a source driver integrated circuit. In some other embodiments, the driving circuit240may be integrated in a source driver integrated circuit, and the data conversion circuit210, the voltage drop estimation circuit220, and the compensation circuit230may be realized as another integrated circuit. In some further other embodiments, the data conversion circuit210, the voltage drop estimation circuit220, and the compensation circuit230may be integrated in a timing controller or other integrated circuits.

According to different designs, in some embodiments, the data conversion circuit210, the voltage drop estimation circuit220, and (or) the compensation circuit230may be realized as a hardware circuit. In other embodiments, the data conversion circuit210, the voltage drop estimation circuit220, and (or) the compensation circuit230may be realized as firmware, software (i.e., programs), or a combination thereof. In some embodiments, the data conversion circuit210, the voltage drop estimation circuit220, and (or) the compensation circuit230may be realized as a combination of multiple ones of hardware, firmware, and software.

In terms of hardware form, the data conversion circuit210, the voltage drop estimation circuit220, and (or) the compensation circuit230may be realized as a logic circuit on an integrated circuit. For example, the relevant functions of the data conversion circuit210, the voltage drop estimation circuit220, and (or) the compensation circuit230may be realized as various logic blocks, modules, and circuits in one or more controllers, microcontrollers, microprocessors, application-specific integrated circuits (ASICs), digital signal processors (DSPs), field programmable gate arrays (FPGAs), central processing units (CPUs), and/or other processing units. The relevant functions of the data conversion circuit210, the voltage drop estimation circuit220, and (or) the compensation circuit230may be realized as a hardware circuit, such as various logic blocks, modules, and circuits in an integrated circuit, by utilizing hardware description languages (e.g., Verilog HDL or VHDL) or other suitable programming languages.

In terms of software form and/or firmware form, the relevant functions of the data conversion circuit210, the voltage drop estimation circuit220, and (or) the compensation circuit230may be realized as programming codes. For example, the data conversion circuit210, the voltage drop estimation circuit220, and (or) the compensation circuit230are realized by utilizing general programming languages (e.g., C, C++, or assembly language) or other suitable programming languages. The programming codes may be recorded/stored in a “non-transitory machine-readable storage medium”. In some embodiments, the non-transitory machine-readable storage medium includes, for example, a semiconductor memory and/or a storage device. The semiconductor memory includes a memory card, read only memory (ROM), flash memory, a programmable logic circuit, or other semiconductor memory. The storage device includes a tape, a disk, a hard disk drive (HDD), a solid-state drive (SSD), or other storage devices. Electronic equipment (e.g., a computer, CPU, a controller, a microcontroller, or a microprocessor) may read and execute the programming codes from the non-transitory machine-readable storage medium so as to realize the relevant functions of the data conversion circuit210, the voltage drop estimation circuit220, and (or) the compensation circuit230. Alternatively, the programming codes may be provided to the electronic equipment via any transmission medium (e.g., a communication network or a radio wave). The communication network is, for example, the Internet, a wired communication network, a wireless communication network, or other communication media.

FIG.3is a schematic flowchart of a grayscale compensation method of a display device according to an embodiment of the disclosure. With reference toFIG.2andFIG.3, in step S310, the data conversion circuit210may convert a plurality of original grayscale data D1 of a target pixel block into current data DI corresponding to the target pixel block. For example, the data conversion circuit210may convert the plurality of original grayscale data D1 of the target pixel block into a plurality of sub-pixel current values corresponding to a plurality of sub-pixels of the target pixel block based on one or more grayscale-to-current conversion curves. The grayscale-to-current conversion curve may be set depending on the actual design. For example, in an embodiment, the grayscale-to-current conversion curve may be the well-known Gamma 2.2 curve or other conversion curves.

FIG.4is a schematic diagram of a grayscale-to-current conversion curve according to another embodiment of the disclosure. The horizontal axis shown inFIG.4represents the grayscale, and the vertical axis shown inFIG.4represents the current (brightness). In the embodiment shown inFIG.4, although it is assumed that the maximum grayscale is 255, the actual maximum grayscale may be set to other grayscale values depending on the actual design. The grayscale-to-current conversion curve shown inFIG.4is dependent on the display characteristics of the display panel250.

FIG.5is a schematic diagram of a grayscale-to-current conversion curve according to yet another embodiment of the disclosure. The horizontal axis shown inFIG.5represents the grayscale, and the vertical axis shown inFIG.5represents the current (brightness). In the embodiment shown inFIG.5, although it is assumed that the maximum grayscale is 255, the actual maximum grayscale may be set to other grayscale values depending on the actual design. In the embodiment shown inFIG.5, the range of the grayscale data may be divided into a plurality of intervals (e.g., intervals510,520, and530shown inFIG.5). In the embodiment shown inFIG.5, although it is assumed that the dividing points of the intervals are 24 and 233, the actual dividing points and the number of intervals may be set depending on the actual design.

In the embodiment shown inFIG.5, there are different grayscale-to-current conversion curves in different intervals. For example (but not limited thereto), the grayscale-to-current conversion curve in the interval510is a linear curve, the grayscale-to-current conversion curve in the interval530is the Gamma 2.2 curve, and the grayscale-to-current conversion curve in the interval520is a conversion curve other than the Gamma 2.2 curve. For example (but not limited thereto), the grayscale-to-current conversion curve in the interval520may be Formula (1) below. In Formula (1), I represents the sub-pixel current value corresponding to the sub-pixel, U represents the upper boundary grayscale value (e.g., 233 or other real numbers) of the interval520, L represents the lower boundary grayscale value (e.g., 24 or other real numbers) of the interval520, M represents the maximum grayscale value (e.g., 255 or other real numbers) of the range of the original grayscale data D1, and D1 represents the original grayscale data of the sub-pixel. The data conversion circuit210may convert the plurality of original grayscale data of the target pixel block into a plurality of sub-pixel current values corresponding to a plurality of sub-pixels of the target pixel block based on the plurality of grayscale-to-current conversion curves shown inFIG.5.

With reference toFIG.2andFIG.3, the data conversion circuit210may use the plurality of sub-pixel current values of the target pixel block to calculate the current data DI corresponding to the target pixel block in step S310. For example, the data conversion circuit210may perform average calculation on the plurality of sub-pixel current values of the target pixel block according to colors to generate a plurality of color current average values of the target pixel block. The data conversion circuit210may perform weighting calculation on the plurality of color current average values of the target pixel block to generate the current data DI of the target pixel block.

It is assumed that the target pixel block includes a plurality of red sub-pixels, a plurality of green sub-pixels, and a plurality of blue sub-pixels. The data conversion circuit210may average red sub-pixel current values to generate a red current average value. The data conversion circuit210may average green sub-pixel current values to generate a green current average value. The data conversion circuit210may average blue sub-pixel current values to generate a blue current average value. The data conversion circuit210may perform weighting calculation on the red current average value, the green current average value, and the blue current average value of the target pixel block to generate the current data DI corresponding to the target pixel block. For example (but not limited thereto), the data conversion circuit210may calculate Formula (2) below. In Formula (2), DI represents the current data corresponding to the target pixel block, Wr represents the red weight, R represents the red current average value, Wg represents the green weight, G represents the green current average value, Wb represents the blue weight, B represents the blue current average value, and M represents the maximum grayscale value (e.g., 255 or other real numbers). The values of the red weight Wr, the green weight Wg, and the blue weight Wb may be set depending on the actual design.

With reference toFIG.2andFIG.3, the voltage drop estimation circuit220is coupled to the data conversion circuit210to receive the current data DI of the target pixel block. In step S320, the voltage drop estimation circuit220may convert the current data DI into transmission line voltage drop information of the target pixel block. Assuming that a transmission line of the display panel250corresponds to a plurality of pixel groups (e.g., all pixel blocks in one pixel block column) of the display panel250, the data conversion circuit210may provide the current data DI of all pixel blocks of one pixel block column to the voltage drop estimation circuit220. The voltage drop estimation circuit220may accumulate the current data DI of the pixel blocks of the same pixel block column along an inverse transmission direction of the transmission line to know a current accumulation value corresponding to each pixel block. The voltage drop estimation circuit220may count the current accumulation values of the pixel blocks of the same pixel block column along a transmission direction of the transmission line to get a voltage drop characteristic value (an IR drop characteristic value) corresponding to each pixel block. The voltage drop estimation circuit220may use the voltage drop characteristic value of the target pixel block and a reference voltage drop characteristic value of the target pixel block to calculate a voltage drop ratio (the transmission line voltage drop information).

FIG.6is a schematic diagram of one pixel block column according to an embodiment of the disclosure. The number of pixel blocks of one pixel block column may be determined depending on the actual design. For example, the pixel block column shown inFIG.6includes pixel blocks611,612,613,614,615,616,617, and618. In a case where the transmission line is a data line, a plurality of pixel groups corresponding to the transmission line are different pixel blocks in a same column (e.g., the pixel blocks611to618shown inFIG.6) of the display panel, and the voltage drop ratio may include a 1-D (one-dimensional) voltage drop ratio. It is assumed that the current data DI of the pixel blocks611to618are respectively DI61, DI62, DI63, DI64, DI65, DI66, DI67, and DI68. The voltage drop estimation circuit220may accumulate current data DI61 to DI68 of the pixel blocks611to618of the same pixel block column along the inverse transmission direction of the transmission line (the data line) to know the current accumulation value corresponding to each pixel block. The current accumulation value of the pixel block611shown inFIG.6is CA61=DI61. The current accumulation value of the pixel block612shown inFIG.6is CA62=CA61+DI62. The current accumulation value of the pixel block613shown inFIG.6is CA63=CA62+DI63. The current accumulation value of the pixel block614shown inFIG.6is CA64=CA63+DI64. The current accumulation value of the pixel block615shown inFIG.6is CA65=CA64+DI65. The current accumulation value of the pixel block616shown inFIG.6is CA66=CA65+DI66. The current accumulation value of the pixel block617shown inFIG.6is CA67=CA66+DI67. The current accumulation value of the pixel block618shown inFIG.6is CA68=CA67+DI68.

The voltage drop estimation circuit220may count the current accumulation values of the pixel blocks611to618of the same pixel block column along the transmission direction of the transmission line to know the voltage drop characteristic value corresponding to each pixel block. The voltage drop characteristic value of the pixel block618is IRD68=CA68. The voltage drop characteristic value of the pixel block617is IRD67=IRD68+CA67. The voltage drop characteristic value of the pixel block616is IRD66=IRD67+CA66. The voltage drop characteristic value of the pixel block615is IRD65=IRD66+CA65. The voltage drop characteristic value of the pixel block614is IRD64=IRD65+CA64. The voltage drop characteristic value of the pixel block613is IRD63=IRD64+CA63. The voltage drop characteristic value of the pixel block612is IRD62=IRD63+CA62. The voltage drop characteristic value of the pixel block611is IRD61=IRD62+CA61.

The voltage drop estimation circuit220may use the voltage drop characteristic value of the target pixel block and the reference voltage drop characteristic value of the target pixel block to calculate the 1-D voltage drop ratio (the transmission line voltage drop information). The reference voltage drop characteristic value may be set depending on the actual design. For example, the reference voltage drop characteristic value includes a maximum voltage drop characteristic value of the target pixel block in a case where each sub-pixel of all pixel blocks corresponding to the transmission line (the data line) is a maximum grayscale. It is assumed that the maximum voltage drop characteristic values of the pixel blocks611to618shown inFIG.6are respectively IRDM61, IRDM62, IRDM63, IRDM64, IRDM65, IRDM66, IRDM67, and IRDM68. The 1-D voltage drop ratio (the transmission line voltage drop information) of the pixel block611is R1D61=IRD61/IRDM61. By analogy, the 1-D voltage drop ratio (the transmission line voltage drop information) of the pixel block618is R1D68=IRD68/IRDM68.

In the scenario shown inFIG.6, the transmission line voltage drop information of different pixel blocks in the same pixel block column has been taken into consideration, that is, the transmission line voltage drop in the vertical direction of the display panel has been taken into consideration. Analogy of the same concept may be made to the transmission line voltage drop in the horizontal direction of the display panel. In a case where the transmission line is a source driver power line, “pixel groups corresponding to the transmission line” may be a plurality of pixel block columns of the display panel, and the voltage drop ratio may include a 2-D (two-dimensional) voltage drop ratio.

FIG.7is a schematic diagram of a plurality of pixel block columns according to an embodiment of the disclosure. The number of pixel block columns of one display panel may be determined depending on the actual design. For example, the display panel shown inFIG.7includes pixel block columns711,712,713,714,715,716,717, and718. Analogy may be made with reference to the relevant description of the pixel block column shown inFIG.6for any one of the pixel block columns711to718shown inFIG.7, which are thus not repeatedly described. The voltage drop estimation circuit220may accumulate the current data DI of all pixel blocks of the same pixel block column (see the description of the embodiment shown inFIG.6for details) to know the current data of the pixel block column. It is assumed that current data of the pixel block columns711to718are respectively DI71, DI72, DI73, DI74, DI75, DI76, DI77, and DI78. The voltage drop estimation circuit220may accumulate the current data DI71 to DI78 of the pixel block columns711to718along an inverse transmission direction of the transmission line (the source driver power line) to know the current accumulation value corresponding to each pixel block column. The current accumulation value of the pixel block column711shown inFIG.7is CA71=DI71. The current accumulation value of the pixel block column712shown inFIG.7is CA72=CA71+DI72. The current accumulation value of the pixel block column713shown inFIG.7is CA73=CA72+DI73. The current accumulation value of the pixel block column714shown inFIG.7is CA74=CA73+DI74. The current accumulation value of the pixel block column715shown inFIG.7is CA75=CA74+DI75. The current accumulation value of the pixel block column716shown inFIG.7is CA76=CA75+DI76. The current accumulation value of the pixel block column717shown inFIG.7is CA77=CA76+DI77. The current accumulation value of the pixel block column718shown inFIG.7is CA78=CA77+DI78.

The voltage drop estimation circuit220may count the current accumulation values of the pixel block columns711to718along a transmission direction of the transmission line to know the voltage drop characteristic value corresponding to each pixel block column. The voltage drop characteristic value of the pixel block column718is IRD78=CA78. The voltage drop characteristic value of the pixel block column717is IRD77=IRD78+CA77. The voltage drop characteristic value of the pixel block column716is IRD76=IRD77+CA76. The voltage drop characteristic value of the pixel block column715is IRD75=IRD76+CA75. The voltage drop characteristic value of the pixel block column714is IRD74=IRD75+CA74. The voltage drop characteristic value of the pixel block column713is IRD73=IRD74+CA73. The voltage drop characteristic value of the pixel block column712is IRD72=IRD73+CA72. The voltage drop characteristic value of the pixel block column711is IRD71=IRD72+CA71.

The voltage drop estimation circuit220may use the voltage drop characteristic value of a target pixel block column and a reference voltage drop characteristic value of the target pixel block column to calculate the 2-D voltage drop ratio (the transmission line voltage drop information). The reference voltage drop characteristic value of the target pixel block column may be set depending on the actual design. For example, the reference voltage drop characteristic value of the target pixel block column includes a maximum voltage drop characteristic value of the target pixel block column in a case where each sub-pixel of the target pixel block column is a maximum grayscale. It is assumed that the maximum voltage drop characteristic values of the pixel block columns711to718shown inFIG.7are respectively IRDM71, IRDM72, IRDM73, IRDM74, IRDM75, IRDM76, IRDM77, and IRDM78. The 2-D voltage drop ratio (the transmission line voltage drop information) of the pixel block column711is R2D71=IRD71/IRDM71. By analogy, the 2-D voltage drop ratio (the transmission line voltage drop information) of the pixel block column718is R2D78=IRD78/IRDM78.

With reference toFIG.2andFIG.3, the compensation circuit230is coupled to the voltage drop estimation circuit220to receive the transmission line voltage drop information of the target pixel block (and/or the transmission line voltage drop information of the target pixel block column). In step S330, the compensation circuit230may convert the transmission line voltage drop information into at least one pixel compensation value of the target pixel block (and/or at least one pixel compensation value of the target pixel block column). For example (but not limited thereto), the compensation circuit230may obtain at least one first compensation value corresponding to the target pixel block from at least one lookup table based on a position of the target pixel block. The compensation circuit230may use the first compensation value and the transmission line voltage drop information of the target pixel block to calculate a second compensation value of the target pixel block. The compensation circuit230may convert the second compensation value into the pixel compensation value of the target pixel block. The compensation circuit230may use the pixel compensation value to compensate the original grayscale data of the target pixel block, so as to generate compensated grayscale data D2 of the target pixel block.

As an example, the at least one lookup table may include a maximum (Max) loading condition lookup table and a minimum (Min) loading condition lookup table, the first compensation value corresponding to the target pixel block includes a maximum loading condition compensation value and a minimum loading condition compensation value, and the transmission line voltage drop information of the target pixel block includes the 1-D voltage drop ratio and the 2-D voltage drop ratio corresponding to the target pixel block. The content of the maximum loading condition lookup table may be ideal compensation values (the maximum loading condition compensation values) corresponding to pixel blocks at different positions in a case where all pixels of the display panel emit light at the maximum grayscale. The content of the minimum loading condition lookup table may be ideal compensation values (the minimum loading condition compensation values) corresponding to pixel blocks at different positions in a case where all pixels of the display panel emit light at the minimum grayscale. The compensation circuit230may obtain the maximum loading condition compensation value corresponding to the target pixel block from the maximum loading condition lookup table based on the position of the target pixel block in the display panel. In addition, the compensation circuit230may obtain the minimum loading condition compensation value corresponding to the target pixel block from the minimum loading condition lookup table based on the position of the target pixel block.

The compensation circuit230may use the maximum loading condition compensation value, the minimum loading condition compensation value, the 1-D voltage drop ratio, and the 2-D voltage drop ratio to calculate the second compensation value of the target pixel block. For example (but not limited thereto), the compensation circuit230may calculate Formula (3) below. In Formula (3), Comp represents the second compensation value, Cmin represents the minimum loading condition compensation value, Cmax represents the maximum loading condition compensation value, R1D represents the 1-D voltage drop ratio, and R2D represents the 2-D voltage drop ratio.

In some embodiments, the compensation circuit230may use the second compensation value as the at least one pixel compensation value. In some other embodiments, the compensation circuit230may convert the second compensation value of the target pixel block into the at least one pixel compensation value of the target pixel block. With reference toFIG.2andFIG.3, in step S340, the compensation circuit230may use the at least one pixel compensation value to compensate the original grayscale data of the target pixel block, so as to generate the compensated grayscale data D2 of the target pixel block. The compensation circuit230may provide the compensated grayscale data D2 to the driving circuit240so as to drive the display panel250to display images.

As an example, in some embodiments, the at least one pixel compensation value includes a plurality of sub-pixel compensation values corresponding to different sub-pixels in the target pixel block. The compensation circuit230may convert the second compensation value of the target pixel block into the sub-pixel compensation value corresponding to each of a plurality of edge sub-pixels of the target pixel block. For example (but not limited thereto), the compensation circuit230may use the second compensation value of the target pixel block and the second compensation value of an adjacent pixel block adjacent to the target pixel block to perform interpolation/extrapolation to calculate the second compensation values of the plurality of edge sub-pixels (e.g., sub-pixels at four corners) of the target pixel block. The compensation circuit230may use the sub-pixel compensation values of these edge sub-pixels to perform interpolation/extrapolation to calculate the sub-pixel compensation value corresponding to each of the other sub-pixels in the target pixel block. Therefore, the compensation circuit230may use the pixel compensation values corresponding to different sub-pixels to compensate the original grayscale data of different sub-pixels, so as to generate the compensated grayscale data D2 of these sub-pixels.

FIG.8is a schematic circuit block diagram of a data conversion circuit210, a voltage drop estimation circuit220, and a compensation circuit230according to an embodiment of the disclosure. The data conversion circuit210, the voltage drop estimation circuit220, and the compensation circuit230shown inFIG.8may be taken as one of many implementation examples of the data conversion circuit210, the voltage drop estimation circuit220, and the compensation circuit230shown inFIG.2. Reference may be made to the relevant descriptions of the data conversion circuit210, the voltage drop estimation circuit220, and the compensation circuit230shown inFIG.2for the data conversion circuit210, the voltage drop estimation circuit220, and the compensation circuit230shown inFIG.8, which will thus not be repeatedly described.

In the embodiment shown inFIG.8, the data conversion circuit210includes a current index mapping circuit211, a block average circuit212, and a color weighting circuit213. The current index mapping circuit211may convert the original grayscale data D1 of the target pixel block into a plurality of sub-pixel current values corresponding to a plurality of sub-pixels of the target pixel block based on a grayscale-to-current conversion curve. For example (but not limited thereto), the current index mapping circuit211may convert the original grayscale data D1 of the target pixel block into a plurality of sub-pixel current values corresponding to a plurality of sub-pixels of the target pixel block based on the grayscale-to-current conversion curve shown inFIG.4, the grayscale-to-current conversion curve shown inFIG.5, or other conversion curves.

The block average circuit212is coupled to the current index mapping circuit211to receive the sub-pixel current values. The block average circuit212may perform average calculation on the sub-pixel current values of the target pixel block according to colors to generate a plurality of color current average values of the target pixel block. It is assumed that the target pixel block includes a plurality of red sub-pixels, a plurality of green sub-pixels, and a plurality of blue sub-pixels. The block average circuit212may average red sub-pixel current values to generate a red current average value R. The block average circuit212may average green sub-pixel current values to generate a green current average value G. The block average circuit212may average blue sub-pixel current values to generate a blue current average value B.

The color weighting circuit213is coupled to the block average circuit212to receive the color current average values. The color weighting circuit213may perform weighting calculation on the color current average values of the target pixel block to generate the current data DI of the target pixel block. For example (but not limited thereto), the data conversion circuit210may calculate Formula (2) above to generate the current data DI of the target pixel block.

In the embodiment shown inFIG.8, the voltage drop estimation circuit220includes a current accumulation circuit221, a voltage drop calculation (IR drop calculation) circuit222, a one-dimensional (1-D) ratio circuit223, and a two-dimensional (2-D) ratio circuit224. The current accumulation circuit221is coupled to the data conversion circuit210to receive the current data DI of each pixel block of the display panel. The current accumulation circuit221may accumulate the current data of different pixel blocks in the same pixel block column along an inverse transmission direction of the data line of the display panel to know the current accumulation value corresponding to each pixel block in the same pixel block column. For example (but not limited thereto), with reference to the relevant description ofFIG.6, the current accumulation circuit221may accumulate the current data of different pixel blocks in the same pixel block column to know the current accumulation value corresponding to each pixel block in the same pixel block column.

In addition, the current accumulation circuit221may sum up the current data of all pixel blocks in any pixel block column to know column current data of each pixel block column. The current accumulation circuit221may accumulate the column current data of different pixel block columns along an inverse transmission direction of the source driver power line to know a column current accumulation value corresponding to each pixel block column. For example (but not limited thereto), with reference to the relevant description ofFIG.7, the current accumulation circuit221may accumulate the current data (the column current data) of different pixel block columns to know the current accumulation value (the column current accumulation value) corresponding to each pixel block column.

The voltage drop calculation circuit222is coupled to the current accumulation circuit221to receive the current accumulation value and the column current accumulation value. The voltage drop calculation circuit222may count the current accumulation values of different pixel blocks in the same pixel block column along the transmission direction of the data line to know a column voltage drop characteristic value (a column IR drop characteristic value) corresponding to each pixel block in the same pixel block column. For example (but not limited thereto), with reference to the relevant description ofFIG.6, the voltage drop calculation circuit222may count the current accumulation values (the column current accumulation values) of different pixel blocks in the same pixel block column to know the voltage drop characteristic value (the column voltage drop characteristic value) corresponding to each pixel block in the same pixel block column.

In addition, the voltage drop calculation circuit222may count the column current accumulation values of different pixel block columns along the transmission direction of the source driver power line to know a row voltage drop characteristic value (a row IR drop characteristic value) corresponding to each pixel block column. For example (but not limited thereto), with reference to the relevant description ofFIG.7, the voltage drop calculation circuit222may count the current accumulation values (the column current accumulation values) of different pixel block columns to know the voltage drop characteristic value (the row voltage drop characteristic value) corresponding to each pixel block column.

The 1-D ratio circuit223is coupled to the voltage drop calculation circuit222to receive the column voltage drop characteristic value. The 1-D ratio circuit223may use the column voltage drop characteristic value of the target pixel block and a reference column voltage drop characteristic value of the target pixel block to calculate a 1-D voltage drop ratio corresponding to the target pixel block. For example, assuming that the column voltage drop characteristic value of the target pixel block is IRD68 and the reference column voltage drop characteristic value of the target pixel block is IRDM68, then the 1-D voltage drop ratio (the transmission line voltage drop information) of the target pixel block is R1D68=IRD68/IRDM68.

The 2-D ratio circuit224is coupled to the voltage drop calculation circuit222to receive the row voltage drop characteristic value. The 2-D ratio circuit224may use the row voltage drop characteristic value of a target pixel block column corresponding to the target pixel block and a reference row voltage drop characteristic value of the target pixel block column to calculate a 2-D voltage drop ratio corresponding to the target pixel block. For example, assuming that the row voltage drop characteristic value of the target pixel block column corresponding to the target pixel block is IRD78 and the reference row voltage drop characteristic value of the target pixel block column is IRDM78, then the 2-D voltage drop ratio (the transmission line voltage drop information) of the target pixel block is R2D78=IRD78/IRDM78.

In the embodiment shown inFIG.8, the compensation circuit230includes a lookup table circuit231, a compensation value generation circuit232, and a grayscale compensation circuit233. The lookup table circuit231is coupled to the voltage drop estimation circuit to receive the transmission line voltage drop information. Here, the transmission line voltage drop information of the target pixel block may include the 1-D voltage drop ratio and the 2-D voltage drop ratio. The lookup table circuit231may obtain at least one first compensation value corresponding to the target pixel block from at least one lookup table based on a position of the target pixel block. The lookup table circuit231may use the first compensation value and the transmission line voltage drop information of the target pixel block to calculate a second compensation value of the target pixel block.

For example (but not limited thereto), the at least one lookup table may include a maximum loading condition lookup table and a minimum loading condition lookup table. The lookup table circuit231may obtain the maximum loading condition compensation value corresponding to the target pixel block from the maximum loading condition lookup table, and obtain the minimum loading condition compensation value corresponding to the target pixel block from the minimum loading condition lookup table based on the position of the target pixel block in the display panel. Using the maximum loading condition compensation value and the minimum loading condition compensation value (the first compensation value), and using the 1-D voltage drop ratio and the 2-D voltage drop ratio (the transmission line voltage drop information) of the target pixel block, the lookup table circuit231may calculate the second compensation value of the target pixel block. For example, the lookup table circuit231may calculate Formula (3) above to generate the second compensation value of the target pixel block.

The compensation value generation circuit232is coupled to the lookup table circuit231to receive the second compensation value. The compensation value generation circuit232may convert the second compensation value of the target pixel block into at least one pixel compensation value of the target pixel block (e.g., the sub-pixel compensation values corresponding to a plurality of edge sub-pixels of the target pixel block). For example, the compensation value generation circuit232may use the second compensation value of the target pixel block and the second compensation value of an adjacent pixel block adjacent to the target pixel block to perform interpolation/extrapolation to calculate the second compensation values of the plurality of edge sub-pixels (e.g., the second compensation values of sub-pixels at four corners) of the target pixel block. Then, the compensation value generation circuit232may use the second compensation values (the sub-pixel compensation values) of these edge sub-pixels to perform interpolation/extrapolation to calculate the sub-pixel compensation value corresponding to each of the other sub-pixels in the target pixel block.

The grayscale compensation circuit233is coupled to the compensation value generation circuit232to receive the pixel compensation value. The grayscale compensation circuit233may use the pixel compensation value to compensate the original grayscale data of the target pixel block, so as to generate the compensated grayscale data D2 of the target pixel block.

In summary of the foregoing, the display device according to the embodiments above may convert the original grayscale data D1 into the current data, then convert the current data into the transmission line voltage drop information, further convert the transmission line voltage drop information into the pixel compensation value, and use the pixel compensation value to compensate the original grayscale data D1. Therefore, the display device may compensate the voltage drop of the transmission line.