Level indicating circuit

A level indicating circuit includes a pair of transistors, arranged as a differential amplifier and to whose bases an input signal is applied, a level-detecting circuit to supply to a meter or the like an indicating current whose level is related to the magnitude of the input signal; and a network connecting the collector of at least one of the transistors of the differential amplifier to the level-detecting circuit and establishing a threshold for the input signal such that the level-detecting circuit supplies its indicating current only when the input signal exceeds the threshold. The level-detecting circuit can include a transistor which is biased so as to begin conducting only when the magnitude of the input signal exceeds the dynamic range of the differential amplifier and drives one or the other of the transistors thereto to cutoff or saturation.

BACKGROUND OF THE INVENTION 
1. Field of the Invention 
This invention generally relates to a level indicating circuit, and is 
particularly directed to an improved level indicating circuit of simple 
construction and which can be used with an intermediate frequency 
amplifier without draining its signal current. 
2. Description of the Prior Art 
In an FM receiver, input signal level (received electric field level) is 
conventionally indicated by rectifying an intermediate frequency signal 
and supplying such rectified intermediate frequency signal to a meter or 
the like. 
Unfortunately, with this conventional technique, the rectifying circuit 
acts as a load on the intermediate frequency amplifier and drains current 
from the intermediate frequency signal. Also, the rectifying diode of the 
rectifying circuit needs to be supplied with voltage bias which requires a 
circuit of considerable complexity. 
OBJECTS AND SUMMARY OF THE INVENTION 
It is an object of this invention to provide a novel level indicating 
circuit which is simple in construction. 
It is another object of this invention to provide a level indicating 
circuit which does not drain the signal current in an intermediate 
frequency amplifier. 
It is a further object of this invention to provide a level indicating 
circuit which readily lends itself to construction as an integrated 
circuit. 
According to an aspect of this invention, a level indicating circuit for 
indicating the magnitude or level of an input signal comprises first and 
second transistors whose collectors are connected through first and second 
resistors, respectively, to a source of potential, whose emitters are 
coupled to ground via an emitter resistor, and whose bases are arranged to 
receive the input signal; a level measuring circuit to produce an output 
current whose level is related to the magnitude of the input signal; and a 
network connecting the collector of the first transistor to the 
level-measuring circuit and effecting a threshold for the input signal 
such that the level-measuring circuit produces its output current only if 
the magnitude of the input signal is beyond the dynamic range of this 
first transistor, that is, only if the magnitude of the input signal is 
great enough to drive the first transistor to either saturation or cutoff. 
The above, and other objects, features and advantages of the invention, 
will be apparent from the following description taken in conjunction with 
the accompanying drawings.

DESCRIPTION OF THE PREFERRED EMBODIMENTS 
Referring to the drawings in detail, and initially to FIG. 1 thereof, it 
will be seen that an intermediate-frequency stage of a 
frequency-modulation receiver is there shown to be formed of front-stage, 
middle-stage, and rear-stage intermediate frequency amplifiers 1, 2 and 3, 
respectively, with the middle-stage intermediate frequency amplifier 2 
being constituted by two differential amplifiers 21 and 22. Differential 
amplifier 21 includes transistors Q.sub.1 and Q.sub.2 whose emitter 
electrodes are connected in common to ground through a resistor R.sub.1, 
and the collector electrodes of transistors Q.sub.1 and Q.sub.2 are 
connected through equal-value resistors R.sub.2 and R.sub.3, respectively, 
to a voltage supply terminal T to which a source voltage +V.sub.cc is 
supplied. The base electrodes of transistors Q.sub.1 and Q.sub.2 are 
biased by means of biasing transistors Q.sub.9 and Q.sub.10. 
Differential amplifier 22 similarly includes transistors Q.sub.7 and 
Q.sub.8 having their emitter electrodes connected in common to ground 
through a resistor R.sub.11, while the collector electrodes are connected 
through resistors R.sub.12 and R.sub.13 to voltage supply terminal T and 
the base electrodes are biased from biasing transistors Q.sub.9 and 
Q.sub.10. 
Intermediate frequency amplifier 1 delivers oppositely phased versions of 
an intermediate frequency signal to the bases of transistors Q.sub.1 and 
Q.sub.2, respectively, for passage through differential amplifiers 21 and 
22 to the rear-stage intermediate frequency amplifier 3. 
Equal-value series resistors R.sub.4 and R.sub.5 are coupled to the 
collector electrodes of transistors Q.sub.1 and Q.sub.2, respectively, and 
are connected together to form a junction P therebetween. Similarly, 
equal-value resistors R.sub.14 and R.sub.15 are coupled to the collector 
electrodes of transistors Q.sub.7 and Q.sub.8, respectively, and also are 
connected together to form another junction therebetween. 
A level-sensing circuit for sensing the level of the voltage appearing at 
the junction P includes a transistor Q.sub.3 complementary to the 
transistors Q.sub.1 and Q.sub.2, a resistor R.sub.6 connecting the emitter 
of transistor Q.sub.3 to the voltage supply terminal T, and a current 
mirror circuit 23. The base of transistor Q.sub.3 is coupled to the 
junction P. An additional transistor Q.sub.4 which is of the same type as 
transistor Q.sub.3 and is thus complementary to transistors Q.sub.7 and 
Q.sub.8 is included to sense the level of the voltage appearing at the 
junction of resistors R.sub.14 and R.sub.15. A resistor R.sub.7 couples 
the emitter of transistor Q.sub.4 to the voltage supply terminal T, and 
the collector of transistor Q.sub.4 is coupled to the collector of 
transistor Q.sub.3 and to the current mirror circuit 23. The base of 
transistor Q.sub.4 is connected to the junction formed between resistors 
R.sub.14 and R.sub.15. 
The current mirror circuit 23 includes an input-side transistor Q.sub.5 
whose base and collector are coupled to the collectors of transistors 
Q.sub.3 and Q.sub.4 and whose emitter is coupled to ground, and an 
output-side transistor Q.sub.6 whose base is connected to the base and 
collector of the transistor Q.sub.5 and whose emitter is coupled to 
ground. An indicator M, which can, for example, by any convenient meter, 
connects the collector of transistor Q.sub.6 to the voltage supply 
terminal T. It is apparent that a current proportional to the sum of 
currents flowing in the collectors of transistors Q.sub.3 and Q.sub.4 will 
be provided in the indicator M by reason of the mirror circuit 23. 
According to this invention, the values of the resistors R.sub.1 to R.sub.5 
of differential amplifier 21 and the value of resistor R.sub.6 in the 
level sensing circuit are selected to have appropriate values such that 
the transistor Q.sub.3 begins to conduct only when one or the other of 
transistors Q.sub.1 and Q.sub.2 is driven outside its linear range of 
amplification to saturation or cutoff. The values of resistors R.sub.7 and 
R.sub.11 to R.sub.15 are similarly selected so that transistor Q.sub.4 
does not begin to conduct until one of transistors Q.sub.7 and Q.sub.8 is 
driven to saturation or cutoff. 
As shown in FIG. 2A, a quiescent base bias voltage V.sub.0 is applied to 
the base of each of transistors Q.sub.1 and Q.sub.2 which have respective 
collector currents I.sub.C1 and I.sub.C2 which follow the 
current-to-voltage characteristics illustrated by the solid lines. When no 
signal is applied to the bases of transistors Q.sub.1 and Q.sub.2, the 
currents I.sub.C1 and I.sub.C2 are each equal to a quiescent collector 
current value I.sub.0. 
An input signal E.sub.i, here occurring as complementarily varying voltages 
V.sub.B1 and V.sub.B2, fluctuates above and below the quiescent voltage 
V.sub.0. The voltages V.sub.B1 and V.sub.B2 appear at the bases of 
transistors Q.sub.1 and Q.sub.2, and the collector currents I.sub.C1 and 
I.sub.C2 of these transistors are caused to vary complementarily so long 
as the magnitude, or center-to-peak value of the input signal E.sub.i 
remains in a linear range (Region I of FIG. 2A) of the differential 
amplifier 21, and the voltages V.sub.B1 and V.sub.B2 satisfy the 
relations. 
(V.sub.0 -.DELTA.V.sub.a)&lt;V.sub.B1 &lt;(V.sub.0 +.DELTA.V.sub.a), and 
(V.sub.0 -.DELTA.V.sub.a)&lt;V.sub.B2 &lt;(V.sub.0 +.DELTA.V.sub.a) 
where .DELTA.V.sub.a is the input signal amplitude required to drive the 
transistors Q.sub.1 and Q.sub.2 to cutoff. In the linear range, collector 
currents I.sub.C1 and I.sub.C2 remain proportional to voltages V.sub.B1 
and V.sub.B2, respectively, with the result that collector currents 
I.sub.C1 and I.sub.C2 have a constant sum equal to twice the quiescent 
collector current 
EQU I.sub.C1 +I.sub.C2 =2I.sub.0. 
When the magnitude of the input signal E.sub.i extends into a semi-linear 
region (Region II of FIG. 2A), voltages V.sub.B1 and V.sub.B2 satisfy the 
relations 
(V.sub.0 +.DELTA.V.sub.a).ltoreq.V.sub.B1 &lt;(V.sub.0 +.DELTA.V.sub.b) and 
(V.sub.0 -.DELTA.V.sub.b)&lt;V.sub.B2 .ltoreq.(V.sub.0 -.DELTA.V.sub.a), 
where .DELTA.V.sub.b is the voltage required to drive the transistors 
Q.sub.1 and Q.sub.2 to saturation. In the semi-linear region the 
transistor Q.sub.2 is turned off, and its emitter current I.sub.C2 becomes 
zero. Here, the amplifier 21 behaves as though transistor Q.sub.1 were a 
simple grounded emitter transistor, so that the current I.sub.C1 is 
proportional to the voltage V.sub.B1, but the gain afforded by amplifier 
21 is somewhat less than for the input signal E.sub.i in region I. 
Further, when input signal E.sub.i extends into a saturated region (Region 
II of FIG. 2A) and the relations 
V.sub.0 +.DELTA.V.sub.b .ltoreq.V.sub.B1 and V.sub.B2 .ltoreq.V.sub.0 
-.DELTA.V.sub.b 
are satisfied, the transistor Q.sub.2 is turned off so that its collector 
current I.sub.C2 becomes zero, and the transistor Q.sub.1 is turned on, or 
saturated, so that its collector current I.sub.C1 is constant. 
Because of the selection of quiescent voltage V.sub.0 and the symmetrical 
arrangement of the differential amplifier 21, the relation of voltages 
V.sub.B1 and V.sub.B2 to respective collector currents I.sub.C1 and 
I.sub.C2 is symmetric about the center with the characteristic as shown in 
FIG. 2A. Therefore, if the input signal E.sub.i is an intermediate 
frequency signal superimposed on a DC voltage V.sub.0, the transistors 
Q.sub.1 and Q.sub.2 of the differential amplifier 21 amplify the input 
signal. Furthermore, the differential amplifier acts as a limiter when the 
magnitude of the input signal exceeds a predetermined level (here 
.DELTA.V.sub.b). 
Since the collector currents I.sub.C1 and I.sub.C2 fluctuate with the 
intermediate frequency input signal E.sub.i, transistors Q.sub.1 and 
Q.sub.2 will have collector voltages V.sub.C1 and V.sub.C2 that fluctuate 
in a corresponding inverted fashion, as indicated by solid lines in FIG. 
2B. At the same time since the voltage V.sub.P at the junction P 
represents the average of the two collector voltages V.sub.C1 and V.sub.C2 
and satisfies the relation 
EQU V.sub.P =1/2(V.sub.C1 +V.sub.C2), 
the voltage V.sub.P will fluctuate with the magnitude of input signal 
E.sub.i as shown by the broken line in FIG. 2B. In other words, when the 
instantaneous value of the magnitude of intermediate frequency signal 
E.sub.i does not exceed .DELTA.V.sub.a, the relation V.sub.P =V.sub.cc 
-V.sub.D is satisfied where V.sub.D is the quiescent voltage drop of the 
transistors Q.sub.1 and Q.sub.2 and the resistor R.sub.3, so that the 
voltage V.sub.P is a constant. When the instantaneous value of the 
magnitude of signal E.sub.i exceeds .DELTA.V.sub.a but does not exceed 
.DELTA.V.sub.b, the voltage V.sub.P changes in accordance with the signal 
voltage E.sub.i. Further, when the instantaneous value of the signal 
E.sub.i exceeds .DELTA.V.sub.b, the voltage V.sub.P is also constant. The 
voltage V.sub.D can be arbitrarily determined by selecting the values of 
the resistors R.sub.1 through R.sub.5. 
As mentioned earlier, voltage V.sub.P is supplied to the base electrode of 
the transistor Q.sub.3. Thus, if the threshold level for rendering the 
transistor Q.sub.3 conductive is set equal to the voltage V.sub.D, the 
transistor Q.sub.3 will provide a collector current I.sub.C3 having a 
relationship to the magnitude of the input signal E.sub.i as depicted by 
the solid line in FIG. 2C. As shown, when the input signal E.sub.i 
satisfies the relation E.sub.i &lt;.DELTA.V.sub.a, the current I.sub.C3 is 
zero; when the signal E.sub.i has sufficient magnitude so as to satisfy 
the relation 
EQU .DELTA.V.sub.a .ltoreq.E.sub.i .ltoreq.V.sub.b, 
the current I.sub.C3 increases with corresponding increases in the 
magnitude of signal E.sub.i ; and when E.sub.i is sufficiently great so as 
to satisfy the relation E.sub.i &gt;.DELTA.V.sub.b, the current I.sub.C3 is 
constant. 
As the current I.sub.C3 is supplied to input-side transistor Q.sub.5 of 
current mirror circuit 23, a current proportional to current I.sub.C3 will 
flow through output-side transistor Q.sub.6 and hence through indicator M. 
A similar operation is also carried out by the differential amplifier 22 
and by transistor Q.sub.4, except that transistors Q.sub.7 and Q.sub.8 
reach their cutoff and saturation levels faster than transistors Q.sub.1 
and Q.sub.2 owing to the gain afforded the input signal E.sub.i by the 
amplifier 21. Transistor Q.sub.4 also supplies current I.sub.C4 to the 
current mirror circuit 23. Current I.sub.C4 of the transistor Q.sub.4 
varies with respect to the magnitude of signal E.sub.i as depicted by dash 
lines in FIG. 2C. Thus, a current equivalent to the sum of currents 
I.sub.C3 and I.sub.C4 flows through the indicator M, so that the 
indication on indicator M will respond to the input signal E.sub.i as 
shown in chain lines in FIG. 2C. Accordingly, the indication on the 
indicator M will represent the received field level by indicating the 
level, or magnitude of the input signal E.sub.i. 
Resistors R.sub.4 and R.sub.5, coupled with the emitter-base capacitance of 
transistor Q.sub.3 form a low-pass filter. Similarly, resistors R.sub.14 
and R.sub.15 and the emitter-base capacitance of transistor Q.sub.4 also 
form a low-pass filter. Transistors Q.sub.3 and Q.sub.4 are also selected 
to have a characteristic that is relatively insensitive at high 
frequencies. As a result, currents I.sub.C3 and I.sub.C4 are essentially 
DC currents. 
In the indicating circuit according to this invention, only that portion of 
the magnitude of the input signal E.sub.i exceeds the dynamic range of the 
amplifiers 21 and 22 is utilized for indication of the input signal level. 
When the received signal level is too low, the indicator M will not draw 
current to provide an indication. In other words, the level of the input 
signal E.sub.i has to be sufficient to drive at least one of the 
transistors Q.sub.1, Q.sub.2, Q.sub.7, and Q.sub.8 outside its linear 
range (to saturation or to cutoff) before the indicator M begins to draw 
current. Because the indicator M does not place a drain on amplifiers 21 
and 22 when the magnitude of the signal E.sub.i is small, the amplifiers 
21 and 22 do not suffer a signal loss as a result of the level indication. 
Further, the simple construction of this circuit enables the intermediate 
frequency amplifiers 1, 2, 3 to be formed as an integrated circuit. 
In FIG. 3 which illustrates another embodiment of this invention, elements 
corresponding to those described above with reference to FIG. 1 are 
identified by the same reference numerals. As shown on FIG. 3, if the 
quiescent collector current I.sub.0 or the values of resistors R.sub.2 and 
R.sub.3 are relatively large so that the voltage V.sub.P is too low when 
the magnitude of the intermediate frequency input signal E.sub.i is zero, 
additional resistors R.sub.8 and R.sub.9, of equal value, can be included 
between the collectors of transistors Q.sub.1 and Q.sub.2 and the 
resistors R.sub.2 and R.sub.3, respectively. Here the series-connected 
resistors R.sub.2, R.sub.8 and R.sub.3, R.sub.9 act as voltage dividers. 
Resistors R.sub.4 and R.sub.5 are coupled between the junction formed 
between resistors R.sub.2 and R.sub.8 and the junction formed between 
resistors R.sub.3 and R.sub.9. The arrangement of the resistors R.sub.2, 
R.sub.3, R.sub.4, R.sub.5, R.sub.8 and R.sub.9 acts to raise the voltage 
V.sub.P to an appropriate level. 
Although illustrative embodiments of the invention have been described in 
detail with reference to the accompanying drawings, it will be apparent 
that the invention is not limited thereto, and that many modifications and 
variations may be effected therein by one skilled in the art without 
departing from the spirit or scope of this invention as defined in the 
appended claims.