Printed wiring board and a method of manufacturing a printed wiring board

A method of manufacturing a printed wiring board with solder bumps includes forming a solder-resist layer having small and large apertures exposing a respective conductive pad of the printed wiring board, loading a solder ball in each of the small and large apertures using a mask with aperture areas corresponding to the apertures of the solder-resist layer, forming a first bump having a first height, from the solder ball in the small aperture, and a second bump having a second height, from the solder ball in the large aperture, the first height being greater than the second height, and pressing a top of the first bump such that the first height becomes substantially the same as the second height. A multilayer printed wiring board includes a solder-resist layer with apertures of differing sizes and solder bumps having substantially equal volumes but a difference in height no greater than 10 μm.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a printed wiring board which can suitably be used for a package substrate comprising a build-up multilayer wiring board for mounting an IC chip and a method of manufacturing the printed wiring board.

2. Discussion of the Background

Solder bumps are used for an electrical connection between a package substrate and an IC chip. Solder bumps are formed with the following steps.

(1) A step of printing flux on connection pads formed in a package substrate.

(2) A step of loading solder balls on the connection pads with flux printed thereon.

(3) A step of forming solder bumps out of solder balls by reflow.

An IC chip is placed on solder bumps after the solder bumps are formed on a package substrate and the solder bumps and the pads (terminals) on the IC chip are connected by reflow such that the IC chip is mounted on the package substrate. For the above-described step of loading solder balls on connection pads, the printing technology using concurrently a ball arrangement mask and a squeegee is shown in Japanese Unexamined Patent Application Publication No. 2001-267731, the entire content of which is incorporated herein by reference.

SUMMARY OF THE INVENTION

One aspect of the present invention includes a method of manufacturing a printed wiring board having bumps. The method includes forming a solder-resist layer having a small-diameter aperture and a large-diameter aperture, each aperture exposing a respective conductive pad of the printed wiring board, loading a solder ball in each of the small-diameter aperture and the large-diameter aperture using a mask with aperture areas that correspond to the small-diameter aperture and the large-diameter aperture of the solder-resist layer, forming a first bump, having a first height, from the solder ball in the small-diameter aperture, and forming a second bump, having a second height, from the solder ball in the large-diameter aperture, where the first height is greater than the second height. The method further includes pressing a top of the first bump in the small-diameter aperture such that the first height of the first bump becomes substantially the same as the second height of the second bump. Another aspect of the invention includes a multilayer printed wiring board including a substrate with a first side, and a second side opposing the first side. The wiring board further includes a laminated structure including alternately laminated interlayer resin insulating layers and conductor layers, the laminated structure being provided on at least one of the first or second side of the substrate, and a solder-resist layer provided on an outermost layer of the laminated structure, the solder resist layer having apertures of differing sizes each exposing portions of the second conductor layer. The wiring board further includes a solder bump provided in each of the apertures, the solder bumps having substantially equal volumes but a difference in height no greater than 10 μm.

DETAILED DESCRIPTION OF EMBODIMENTS

Because a small-diameter solder ball can become smaller than a sand grain, for example, in the method for concomitantly using a mask for aligning a ball and a squeegee as in JP 2001-267731, the solder ball is deformed by the squeegee and the height of the solder bump can vary, resulting in quality and reliability deterioration of the end device. For example, when a solder ball becomes smaller, the ratio of the weight to the surface area decreases and an attraction phenomenon occurs to the solder ball due to the intermolecular force thereby causing the solder balls to easily stick or cling together. In the related art, because solder balls that stick or cling together come in contact with a squeegee, the solder balls are damaged and partially defected. If the solder ball is partially defected, the volume of the solder bump becomes different on each joint pad and the height of the solder bump varies as mentioned above. With high speed IC chips, there has been a demand for larger diameters for the bumps constituting power supply lines and ground lines so as to be capable of conducting large electrical currents, and, conversely, with highly integrated IC chips there has been a demand for small diameters for the pads and bumps constituting signal lines. Accordingly, the present applicant conducted studies on a provision for power supply and ground of large-diameter opening solder bumps78P (solder volume being large) in large-diameter openings71P and on a provision for signal line of small-diameter opening solder bumps71S (solder volume being small) in the small-diameter openings71S in the solder-resist layer70, as illustrated inFIG. 17(A). However, it was learned that with the structure illustrated inFIG. 17(A), the solder constituting the small-diameter opening solder bump78S flows out to the pad92side on the IC chip90when an IC chip is mounted, as illustrated inFIG. 17(B), such that there occurs a disconnection between the pad92on the IC chip and the pad158on the printed wiring board.

One of the objectives for the present invention is to provide a printed wiring board and a method of manufacturing the printed wiring board whereby bumps can be formed in roughly the same height on the connection pads (conductor circuits exposed out of the solder-resist layer and varying in size) having varying opening diameters in the solder-resist. And another objective is to provide a printed wiring board and a method of manufacturing the printed wiring board having a high mountability yield and connection reliability after the mounting.

One embodiment of the invention includes a method of manufacturing a printed wiring board with solder bumps including at least the following steps (a) through (d):

(a) a step of forming a solder-resist layer having small-diameter openings and large-diameter openings exposing connection pads;

(b) a step of loading, with the use of a mask provided with opening portions corresponding to the small-diameter openings and large-diameter openings in the above-described solder-resist layer, metal balls having a low melting point in said small-diameter openings and large-diameter openings;

(c) a step of forming by reflow bumps having a high height out of the metal balls having a low melting point in the above-described small-diameter openings and bumps having a low height out of the metal balls having a low melting point in the above-described large-diameter openings; and

(d) a step of pressing from the top on the bumps having a high height in the above-described small-diameter openings such that the height thereof is nearly the same as that of the bumps having a low height in the above-described large-diameter openings.

According to another embodiment of the invention, a multilayer printed wiring board on a core substrate has through-hole conductors penetrating the front face and the rear face, and there are alternately laminated interlayer resin insulating layers and conductor layers. Via-hole conductors connect a conductor layer to another conductor layer. A solder-resist layer is provided on the outermost layer. A portion of the conductor layer is exposed from an opening in the solder-resist layer, constituting a pad to mount an electronic part, and solder bumps are formed on these pads.

The above-described openings have different apertures. Some have small-diameter apertures having a relatively small diameter and some have large-diameter apertures having a relatively large diameter.

The solder bumps formed in said small-diameter apertures and the solder bumps formed in the above-described large-diameter apertures are adjusted such that they are approximated to each other in height by the solder bumps formed in the above-described small-diameter apertures and in the above-described large-diameter apertures having the same volume and by the solder bumps formed in the above-described small-diameter apertures by being flattened.

With the use of a mask, metal balls having a low melting point, of substantially equal volume, are loaded into the large-diameter apertures and the small-diameter apertures in the solder-resist layer. Bumps having a high height are formed out of metal balls having a low melting point in the small-diameter apertures in the solder-resist layer and bumps having a low height are formed out of metal balls having a low melting point in the large-diameter apertures in the solder-resist layer. Then, the bumps having a high height in the small-diameter apertures are pressed down from the top such that they are made nearly the same in height as the bumps having a low height in the large-diameter apertures. Accordingly, even when solder-resist aperture diameters to expose connection pads vary, bumps can be formed in nearly the same height. Since the bumps in the small-diameter apertures have the same volume of the metal having a low melting point as the bumps in the large-diameter apertures, the chance of non-connection at the bumps in the small-diameter apertures when an IC chip is loaded via the bumps in the small-diameter apertures and the bumps in the large-diameter apertures is reduced, increasing the connection reliability between the IC chip and the printed wiring board.

According to yet another embodiment, the metal balls having a low melting point are gathered with the use of a mask provided with aperture portions corresponding to the apertures in the solder-resist layer and a cylinder member located above said mask. Air is sucked in from said cylinder member, such that the metal balls are gathered directly below the cylinder member. By the above-described cylinder member or the printed wiring board and the mask being moved relative to each other in a horizontal direction, the gathered metal balls are dropped into the small-diameter apertures and large-diameter apertures of the solder-resist layer via the aperture portions of the mask. Accordingly, this enables fine metal balls having a low melting point to be loaded with certainty and accuracy in all (or essentially all) the apertures of the solder-resist layer. Because the metal balls are moved without being contacted by a moving member such as a squeegee, the metal balls can be loaded in the small-diameter apertures and large-diameter apertures without being damaged and deformed, allowing the height of the resulting bumps to be uniform. Further, this enables metal balls having a low melting point to be properly placed in the apertures even on a printed wiring board with a largely irregular or undulated surface such as a built-up multilayer wiring board.

By flattening the solder bumps formed in the small-diameter apertures, the height of the solder bumps in the small-diameter apertures and the height of the solder bumps in the large-diameter apertures are approximately equal to each other even when the same volume metal balls are used in different apertures. Thus, there occurs minimal non-connection at the solder bumps in the small-diameter apertures when an IC chip is loaded via the solder bumps in the small-diameter apertures and the solder bumps in the large-diameter apertures, allowing the connection reliability between the IC chip and the printed wiring board to be ensured.

According to yet another embodiment, pads for power supply and ground connections are formed in large-diameter apertures and mainly disposed on the center area of the printed wiring board such that the length of the wiring is short resulting in lower resistance value so that the voltage drop is minimized during a sudden increase in power consumption to prevent the IC chip from malfunctioning. Further, because the solder bumps formed in the large diameter apertures are not flattened but maintain in a semi-spherical shape, voids can easily be let out in reflow when the IC chip is loaded. Thus the resistance value of the connection can be prevented from being elevated due to the formation of voids. Conversely, by forming pads for signal in small-diameter apertures, wiring density can be enhanced and concurrently by said small-diameter apertures being mainly disposed on the outer area the printed wiring board, where the large-diameter apertures are on the center area, the solder bumps in said small-diameter apertures are flattened with a flattening plate material having aperture portions corresponding to the sites where the large-diameter apertures are formed, so that the large aperture bumps are not pressed by the flattening plate.

According to yet another embodiment, when solder-resist aperture diameters vary, by flattening the solder bumps formed in small-diameter apertures, the solder bumps in the small-diameter apertures and the solder bumps in large-diameter apertures are approximated to the height of 10 μm and have the same volume. Since the solder bumps in the small-diameter apertures are the same in volume with the solder bumps in large-diameter apertures, there occurs no non-connection at the solder bumps in small-diameter apertures when an IC chip is loaded via the solder bumps in small-diameter apertures and the solder bumps in large-diameter apertures allowing the connection reliability between the IC chip and the printed wiring board to be ensured.

FIG. 14(A)shows the framework of a device for mounting a solder ball related to one example of the embodiments in the present invention, andFIG. 14(B) shows the view from arrow B of the device for mounting a solder ball inFIG. 14(A). For example, the device ofFIGS. 14A and 14Bmay be used to mount a small solder ball77(less than 200 μm in diameter) on a joint pad of the multilayered printed wiring board.

A device for mounting a solder ball100comprises: a XYθ suction table114that holds the positioning of a multilayered printed wiring board10, a vertically moving axis112that moves said XYθ suction table114up and down, and a mask for aligning a ball16, the mask comprising an aperture that corresponds to a joint pad of the multilayered printed wiring board. Also included is a mount cylinder (cylindrical member)124that guides a solder ball moving on the mask for aligning a ball16, a suction box126that provides negative pressure on the mount cylinder124, a cylinder for removing absorbed balls161to collect redundant solder balls, and a suction box166that provides negative pressure on said cylinder for removing absorbed balls161. Also included is a suction device for removing absorbed balls168that holds the collected solder balls, a mask clamp144that clamps the mask for aligning a ball16; and a moving axis in the X direction140that sends the mount cylinder124and the cylinder for removing absorbed balls161in an X direction. In one embodiment, the clamp144may be fixed to the table114such that the mask moves with the table when the table is movable. Further included in the embodiment ofFIGS. 1A and 1Bis a support guide for the moving axis142that supports the moving axis in an X direction140, an alignment camera146that images a multilayered printed wiring board10, a sensor for detecting remaining quantity118that detects the remaining quantity of solder balls under the mount cylinder124, and a feeding device for solder balls122that feeds solder balls to the mount cylinder124according to the remaining quantity detected by the sensor for detecting remaining quantity118.

Next, with reference toFIG. 1toFIG. 13, the constitution of the multilayered printing wiring board10related to embodiments of the present invention is explained.FIG. 11illustrates a sectional view of said multilayer printed wiring board10, andFIG. 12the condition in which the multilayer printed wiring board illustrated inFIG. 11has an IC chip90attached thereto, which is placed on a daughter board94.FIG. 13illustrates a plan view of the multilayer printed wiring board10prior to an IC chip being attached.FIG. 11andFIG. 12show illustratively with the numbers of solder bumps78P and solder bumps78sillustrated inFIG. 13being reduced. In addition, on an actual package substrate hundreds of solder bumps78P and solder bumps78S are provided.

As shown inFIG. 11, with respect to the multilayer printed wiring board10, conductive circuits34are formed on the surfaces of a core substrate30. The top face and the bottom face of the core substrate30are connected via through holes36. On the core substrate30are provided interlayer resin insulating layers50, having via holes60and conductor circuits58formed thereon, and interlayer resin insulating layers150, having via holes160and conductor circuits158formed thereon. On said via holes160and conductor circuits158are formed solder-resist layers70. In the solder-resist layers70are formed large-diameter (D1=105 μm in diameter) apertures71P and small-diameter (D2=80 μm in diameter) apertures71S, and there are provided solder bumps78P for power supply and ground on pads73P in the large-diameter apertures71P and solder bumps78S for signal on pads73S in the small-diameter apertures71S. The solder bumps for power supply and ground78P and the solder bumps for signal78S are constituted out of solder balls having the same volumetric displacement as described below, such that they have the same volume. The height H1of the large-diameter solder bumps78P is set to about 30 μm and the height H2of the small-diameter solder bumps78S is set by being flattened to about 30 μm, which is the same as the height of the large-diameter solder bumps78P. Many of the large-diameter solder bumps for power supply and ground78P are disposed closer toward the center of the multilayer printed wiring board, such that the wiring distance would be short, and the small-diameter solder bumps for signal78S are disposed relatively lopsidedly on the outer side of the large-diameter solder bumps78P. On the lower face side of the multilayer printed wiring board are formed solder bumps78D via the apertures of said solder-resist layer70. In addition, while inFIG. 11the apertures in the solder-resist are formed such that a portion of the conductor circuits158is exposed, the apertures may be formed such that they include only via holes160or via holes160and a portion of the conductor circuits158.

As shown inFIG. 12, the solder bumps for power supply and ground78P on the upper face side of the multilayer printed wiring board10are connected to the electrodes for power supply and ground92P of an IC chip90and the small-diameter aperture solder bumps78S to the electrodes for signal92S. On the other hand, the solder bumps78D on the lower side are connected to the lands96of the daughter board94.

As shown inFIG. 13, a plan view of the multilayer printed wiring board prior to an IC chip being mounted, the multilayer printed wiring board10has pads for power supply and ground78P formed in large-diameter apertures71P and mainly disposed on the center area (the area inside the dotted lines PL) of the multilayer printed wiring board10. This way the length of the wiring from the IC chip90to the daughter board94is short and the resistance is reduced. Thus, a drop in supply voltage is minimized when there is a sudden increase in consumed power by the IC chip to prevent the IC chip90from malfunctioning. Conversely, wiring density is increased by pads for signal78S disposed inside the area indicated by the broken lines SL being formed in the small-diameter apertures71S.

With highly integrated IC chips, there has been a demand for the apertures in the solder-resist for the signal line of the package substrate to be smaller in diameter and narrower in pitch. Conversely, in order to be able to handle a sudden increase in power consumption by the IC chip, an extremely small diameter of the solder bumps for power supply and ground on the package substrate is not desired. Namely, a small diameter of the solder bumps made of a solder alloy leads to a high resistance value causing a voltage drop when there is a sudden increase in power consumption causing the IC chip to malfunction. A solution to satisfy this mutually conflicting requirement is for the solder-resist apertures for signal to be of a small diameter and for the solder bumps for power supply and ground to be of a large diameter.

Continuously, with reference toFIG. 1throughFIG. 6, the method of manufacturing the aforementioned multilayer printed wiring board10, that was mentioned above with reference toFIG. 11, is explained.

A copper-foil laminated board30A, wherein a copper foil being 5 to 250 μm is laminated on both faces of an insulation substrate made of a glass-epoxy resin or a BT (bismaleimide triazine) resin 0.2 to 0.8 mm in thickness, was used as a starting material (FIG. 1(A)). First, this copper-clad laminated board was drilled to bore through holes33(FIG. 1(B)), which was electroless-plated and electroplated to form side-wall conductor layers36bof the through holes36(FIG. 1(C)).

(2) Next, the substrate30having through holes36formed therein is washed with water and dried. Then the substrate30undergoes a blacking process with an aqueous solution containing NaOH (10 g/l), NaClO2(40 g/l), and Na3PO4(6 g/l) as a blacking bath (an oxidation bath) and a reduction process with an aqueous solution containing NaOH (10 g/l) and NaBH4 (6 g/l) as a reduction bath to form roughened faces36α on the side-wall conductor layers36bof the through holes36and the surfaces (FIG. 1(D)).

(3) Next, the through holes36are filled with a filler37containing copper particles of the average particle diameter being 10 μm (for example, a non-conductive plugging copper paste made by Tatsuta Electric Wire & Cable Co., Ltd., Product Name: DD PASTE) with screen printing, which is dried and hardened (FIG. 2(A)). This is performed such that a coating is given with a printing method on the substrate with a mask placed thereon and provided with apertures at the through hole portions to be filled in the through holes, and following the filling it is dried and hardened.

Continuing on, the filler37which oozed out of the through holes36is removed by belt-sanding with the use of a #600 belt sanding paper (for example, sanding paper made by Sankyo Rikagaku Co., Ltd.), and further buffed to remove the flaws due to this belt-sanding to level the surfaces of substrate30(FIG. 2(B)). In this manner, a substrate30in which the side wall conductor layers36bof the through holes36and the resin filler37are effectively attached through the roughened layers36α is obtained.

(4) A palladium catalyst is added to the surfaces of the substrate30leveled under the above-described step (3) which is electroless copper-plated to form electroless copper-plated films23of 0.6 μm in thickness (refer toFIG. 2(C)).

(5) Then, an electrolytic copper plating is conducted under the following conditions to form electrolytic copper plated films24of 15 μm in thickness such that an added thickness for the portions to constitute conductor circuits34and the portions to constitute the cover plated layers (through-hole lands) covering the filler37filled in through holes36are formed (FIG. 2(D)).

The aqueous solution for electrolytic plating includes:

Conditions for electrolytic plating include:

(6) On both faces of the substrate30with the portions to constitute conductor circuits and cover plated layers formed thereon, a commercially available photosensitive dry film is attached, a mask is placed, which is exposed at 100 mJ/cm2and developed with 0.8% sodium carbonate to form etching resists25of 15 μm in thickness (refer toFIG. 2(E)).

(7) And, the plated films23,24and the copper foils32at the portions where the etching resist25are not formed are dissolved and removed with an etching solution having cupric chloride as the main ingredient thereof, and, further, the etching resists25are stripped and removed with 5% KOH to form independent conductor circuits34and the cover plated layers36acovering the filler37(refer toFIG. 3(A)).

(8) Next, on the surfaces of the cover plated layer36acovering the conductor circuits34and the filler37there a roughened layer (an uneven layer)34β of 2.5 μm in thickness made of a Cu—Ni—P alloy is formed, and further, on the surface of this roughened layer34β there an Sn layer of 0.3 μm in thickness is formed (refer toFIG. 3(B), except, the Sn layer is not shown).

(9) On both faces of the substrate there is formed an interlayer resin insulating layer50, after a resin film for interlayer resin insulating layer (for example, manufactured by Ajinomoto Co., Inc., Product Name: ABF-45SH) 50γ being slightly larger than the substrate being placed on the substrate and preliminarily pressure-bonded under the conditions of the pressure being 0.45 MPa, the temperature being 80° C., and the pressure-bonding time being 10 seconds and sheared, by being laminated with the use of a vacuum laminator by the following method (FIG. 3(C)). Namely, the resin film for interlayer resin insulating layer is fully pressure-bonded under the conditions of the degree of vacuum being 67 Pa, the pressure being 0.47 MPa, the temperature being 85° C., and the pressure-bonding time being 60 seconds and subsequently thermoset at 170° C. for 40 minutes.

(10) Next, apertures for via holes51are formed in the interlayer resin insulating layers50with a CO2gas laser at the wavelength of 10.4 μm under the conditions of the beam diameter of 4.00 mm, a top hat mode, the pulse width of 3 to 30 μm, and 1 to 3 shots (FIG. 3(D)).

(11) The substrate with the apertures51for via holes is immersed in a solution containing 60 g/l permanganic acid at 80° C. for 10 minutes to remove particles present on the surfaces of the interlayer resin insulating layers50, such that roughened faces50are formed on the surfaces of the interlayer resin insulating layers50inclusive of the inner walls of the apertures for via holes51(FIG. 4(A)).

(12) Next, the above-treated substrate is immersed in a neutralizing solution (for example, manufactured by Shipley Company, LLC) and then washed with water. Further, to the surfaces of said substrate which have been roughened (roughening depth being 3 μm) a palladium catalyst is added such that the catalyst nucleus is adhered to the surfaces of the interlayer resin insulating layers and the inner wall surfaces of the apertures for via holes. Namely, the above-described substrate is immersed in a catalyst solution containing palladium chloride (PbCl2) and stannous chloride (SnCl2) to allow palladium metal to precipitate and provide the catalyst.

(13) Next, the substrate provided with the catalyst is immersed in an electroless copper plating aqueous solution (for example, Thru-cup PEA manufactured by Uyemura Industries Co. Ltd.) to form an electroless copper plated film of 0.3 to 3.0 μm in thickness over the entire roughened surfaces, to obtain a substrate wherein electroless copper plated films are formed on the surfaces of the interlayer resin insulating layers50, inclusive of the inner walls of the apertures for via holes51(FIG. 4(B)). Conditions for electroless plating are 34° C. solution temperature for 45 minutes.

(14) Commercially available photosensitive dry films are attached to the substrate on which electroless copper plated films52had been formed and a mask was placed, which was exposed at 110 mJ/cm2and developed with 0.8% sodium carbonate aqueous solution to provide plating resists54of 25 μm in thickness. Then, the substrate is washed with water at 50° C. to remove grease, and then it is washed with water at 25° C. and further washed with sulfuric acid and subsequently it is electroplated under the following conditions to form electrolytic copper plated film56of 15 μm in thickness on the portions where the plating resists54had not been formed (FIG. 4(C)).

(15) Further, after the plating resists54have been stripped and removed with 5% KOH, the electroless plating films below the plating resists are dissolved and removed by an etching process with a mixture solution of sulfuric acid and hydrogen peroxide to constitute independent conductor circuits58and via holes60(FIG. 4(D)).

(16) Then, the similar processing as in the above-described (4) is conducted to from roughened faces58α on the surfaces of the conductor circuits58and via holes60. The thickness of the lower layer conductor circuit58is 15 μm (FIG. 5(A)). The lower layer conductor circuit may be formed as having the thickness over the range of 5 to 25 μm.

(17) By repeating the above-mentioned steps (9) through (16), an interlayer insulating layer150having upper layer conductor circuits158and via holes160is further formed to obtain a multilayer wiring board (FIG. 5(B)).

(18) Next, a commercially available solder-resist (or solder-mask) composition70is coated in a thickness of 20 μm on both faces of the multilayer wiring substrate, and then it is dried for 20 minutes at 70° C. and then for 30 minutes at 70° C. Then, a photo mask of 5 mm thickness on which a pattern of the aperture portion of the solder-resist is drawn is tightly adhered to the solder-resist layer70, after the solder-resist layer70was exposed to an ultraviolet ray of 1,000 mJ/cm2and developed with a DMTG solution to form large-diameter (D1=105 μm) apertures71P and small-diameter (D2=80 μm) apertures71S on the upper face side, and apertures71of 200 μm in diameter on the lower face side, and large-diameter pads73P formed by a portion of the conductor circuits158exposed in the large-diameter apertures71P and the small-diameter pads73S formed by a portion of the conductor circuits158exposed in the small-diameter apertures71S (FIG. 5(C)).

Further, the solder-resist layers are hardened by heat processes under the conditions of for one hour at 80° C., for one hour at 100° C., for one hour at 120° C., and for three hours at 150° C. to form solder-resist pattern layers of 15 to 25 μm in thickness having apertures.

(19) Next, the substrate on which solder-resist layers70is formed is immersed in an electroless nickel plating solution at pH=4.5 and containing nickel chloride (2.3×10−1mol/l), sodium hypophosphite (2.8×10−1mol/l), and sodium citrate (1.6×10−1mol/l) for 20 minutes to form nickel plated layer72of about 5 μm in thickness in the aperture areas71,71S, and71P. Furthermore, the substrate is immersed in an electroless gold plating solution containing potassium gold cyanide (7.6×10−3mol/l), ammonium chloride (1.9×10−1mol/l), sodium citrate (1.2×10−1mol/l), and sodium hypophosphite (1.7×10−1mol/l) under the conditions of for 7.5 minutes at 80° C. to form a gold plated layer74of about 0.03 μm in thickness on the nickel plated layer72(FIG. 5(D)). Besides a nickel-gold layer, a single layer of tin or a precious metal (gold, silver, palladium, platinum, etc.) may be formed. Further, a conductive pad may be formed without adding metal layers.

(20) A process to mount a solder ball.

Continuing on, a process of loading solder balls onto the multilayer printed wiring board10with the solder ball loading apparatus100described above with reference toFIG. 14will be described with reference toFIG. 6throughFIG. 8.

(I) Position Recognition and Correction of the Multilayer Printed Wiring Board.

The alignment mark34M of the multilayer printed wiring board10is recognized with the alignment camera146, as illustrated inFIG. 6(A), such that the position of the multilayer printed wiring board10with respect to the ball arrangement mask16is corrected with the XYθ suction table114. In other words, the position is adjusted such that each of the apertures16aof the ball arrangement mask16corresponds to each of the small-diameter apertures71S and the large-diameter apertures71P of the multilayer printed wiring board10.

(II) Feeding of Solder Balls.

As shown inFIG. 6(B), the solder balls77(75 μm in diameter, Sn63Pb37 (for example, manufactured by Hitachi Metals, Ltd.)) are supplied in a specified quantity from the solder ball supply unit122to the side of a plurality of loading cylinders124. In addition, they may in advance be supplied to be stored in a loading cylinder. While Sn/Pb solder balls are used for solder balls in this example, Pb-free solder balls selected from a group of Sn and Ag, Cu, In, Bi, Zn, etc. can be used.

(III) Loading of Solder Balls.

The loading cylinders124are positioned above the ball arrangement mask16while maintaining a predetermined clearance (for example, 0.5 to 4 times the ball diameter) to the ball arrangement mask, as illustrated inFIG. 7(A), and air is suctioned from the suction portion124bsuch that the flow velocity at the gap between the loading cylinder and the printed wiring board is set to 5 m/sec to 35 m/sec to allow the solder balls77to gather on the ball arrangement mask16directly below the aperture portion124A of said loading cylinder124.

Subsequently, the loading cylinders124lined up along the Y axis of the multilayer wiring board10as illustrated inFIG. 7(B) andFIG. 8(A) as well asFIG. 14(B) andFIG. 14(A) are moved in a horizontal direction along the X axis via the X-direction moving shaft140. This causes the solder balls77gathered on the ball arrangement mask16to be moved with the movement of the loading cylinders124, such that they are dropped via the apertures16aof the ball arrangement mask16and loaded into the small-diameter apertures71S and the large-diameter apertures71P of the multilayer printed wiring board10. The solder balls77are successively arranged on all the connection pads on the side of the multilayer printed wiring board10.

While the loading cylinders124are moved, it is possible, instead, to move the multilayer printed wiring board10and the ball arrangement mask16with the loading cylinders124held stationary such that the solder balls77gathered directly below the loading cylinders124are loaded into the small-diameter apertures71S and the large-diameter apertures71P of the multilayer printed wiring board10via the apertures16aof the ball arrangement mask16.

(IV) Removal of Excess Solder Balls.

As illustrated inFIG. 8(B), the excess solder balls77are guided by the loading cylinders124to the locations where there are no apertures16aon the ball arrangement mask16to suction out and remove them with the ball removal cylinder161.

(21) Then, the solder balls77on the upper face are melted by reflow at 230° C. to form large-diameter aperture solder bumps78P having a low height (H1≈30 μm, the height protruding out of the surface of the solder-resist) out of the solder balls77in the large-diameter apertures71P, and small-diameter aperture solder bumps78S having a high height (H3≈40 μm, the height protruding out of the surface of the solder-resist) out of the solder balls77in the small-diameter apertures71S and solder bumps78D on the lower face (FIG. 9).

(22) Then, as shown inFIG. 10, the solder bumps having a high height78S in the small-diameter apertures71S are flattened by a flat plate80having an aperture80A at the position corresponding to the large-diameter aperture solder bump portion being pressed on such that it is brought to the same height (H2≈30 μm) as the height (H1≈30 μm) of the solder bumps78P in the large-diameter apertures71P (FIG. 11). The flat plate80may be heated.

In accordance with an embodiment of the invention, the solder bumps in small-diameter apertures71S, being disposed mainly on the outer side of the large-diameter apertures71P, which are on the center side, are flattened with the flat plate80having an aperture80A corresponding to the positions at which the large-diameter apertures71P are disposed. This results in solder bumps78S in the small-diameter apertures71S having the approximate height of the solder bumps78P in the large-diameter apertures71P with the same volume.

Thus the IC chip90is loaded onto the multilayer printed wiring board10, and by reflow the connections pads of the printed wiring board and the electrodes of the IC chip are connected via the solder bumps78P and78S. At that juncture, since the solder amount of the solder bumps78S in the small-diameter apertures71S is the same as that of the solder bumps78P in the large-diameter apertures71P, no non-connection occurs at the solder bumps78S in the small-diameter apertures71S, allowing the connection reliability between the IC chip90and the multilayer printed wiring board10to be ensured. Subsequently, the multilayer printed wiring board10is attached to a daughter board94via solder bumps78D (FIG. 12).

In accordance with an embodiment of the invention, by the solder bumps having a high height78S in the small-diameter apertures71S being flattened, the solder bumps78S will result in solder bumps formed roughly at the same height as solder bumps78P formed in large-diameter apertures71P, even if the small aperture diameter varies. Thus, the mounting yield of the IC chip can be enhanced and an improvement of the connection reliability between the IC chip90and the multilayer printed wiring board10becomes possible.

Further, in accordance an embodiment of the invention, because the solder bumps for power supply and ground78P in the large-diameter apertures71P are not flattened and maintain a semi-spherical shape, voids are easily let out during reflow when the IC chip is loaded, preventing the occurrence of voids due to air inside the solder bumps. This prevents high resistance connections, and is highly advantageous for a power supply connection.

According to an embodiment of the invention, with the loading cylinders124positioned above the ball arrangement mask16, the solder balls77are gathered directly below the loading cylinders124by air being suctioned out of said loading cylinders124. The solder balls77are moved over the ball arrangement mask16by the movement of the loading cylinders124, or by the movement of the ball arrangement mask16while the loading cylinders124are held still. The solder balls77are dropped into the small-diameter apertures71S and the large-diameter apertures71P of the multilayer printed wiring board10via the apertures16aof the ball arrangement mask16. This allows with certainty fine solder balls77to be loaded into all of the small-diameter apertures71S and large-diameter apertures71P of the multilayer printed wiring board10. And, since the solder balls are moved without touching a mechanical movement part such as a squeegee, the solder balls can be loaded into the small-diameter apertures71S and large-diameter apertures71P without being damaged or deformed, resulting in an even height of the solder bumps78S and78P, unlike the case where a squeegee is used. Further, since the solder balls are guided by suction force, the aggregation and adhesion of solder balls can be prevented. Since they present themselves as solder bumps of a large volume having a uniform height, they present themselves as, not only having a high cold and heat shock resistance, but also having low resistance solder bumps which are advantageous for power supply.

In accordance an embodiment of the invention, the height of small-diameter solder bumps78S and the height of the large-diameter solder bumps78P are set to the same 30 μm. It becomes difficult to ensure no non-connection bumps if the difference in height is greater than 10 μm.

Continuing on, a multilayer printed wiring board and a method of manufacturing the multilayer printed wiring board pertaining to another embodiment of the present invention will be described with reference toFIG. 15andFIG. 16.

As described above with reference toFIG. 10andFIG. 11, only the small-diameter solder bumps having a high height78S were flattened. In accordance with another embodiment of the invention, as illustrated inFIG. 15, the large-diameter solder bumps having a low height78P are also flattened. The large-diameter solder bumps formed in the large-diameter (D1=105 μm) apertures71P and the small-diameter solder bumps78S having a high height formed in the small-diameter (D2=80 μm) apertures71S are pressed with the flat plate80. The solder bumps78S having a high height in the small-diameter apertures71S and the solder bumps78P in the large-diameter apertures71P are flattened such that the heights (H2≈30 μm) are the same (FIG. 11). In addition, the solder bumps78S and the solder bumps78P are formed out of solder balls having the same diameter and have the same volume.

As shown inFIG. 16, the solder bumps78S in the small-diameter apertures71S are flattened as a whole and the large-diameter solder bumps78P are flattened at the top only. In accordance to this embodiment, the height of all the solder bumps can advantageously be set uniformly to a desired height.