Storage unit controller and control method thereof, and storage device

A storage unit controller and a control method thereof, and a storage device are provided. The storage unit controller includes an address mapping unit, a nonvolatile buffer and an update indicator. The update indicator sets an indicated flag according to whether a first data saved in the nonvolatile buffer is written to a storage unit. The address mapping unit checks the indicated flag when power is on. When the checked indicated flag indicates that writing the first data is not completed, the address mapping unit enables an update operation mode so as to perform background operations: the first data has not yet been successfully addressed to the storage unit previously, but saved in a simulated address of the nonvolatile buffer to transfer the first data from the simulated address to an actual address of the storage unit.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefit of Taiwan application serial no. 103114512, filed on Apr. 22, 2014. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.

BACKGROUND OF THE INVENTION

Field of the Invention

The embodiments of this invention are related to a storage unit controller and a control method thereof.

Description of Related Art

FIG. 1is a block diagram illustrating a conventional storage device. Please refer toFIG. 1. A storage device100includes a nonvolatile memory10and a controller20. When a host transmits data to the storage device100for storage, if the power of the storage device100is unstable or turned off during the writing process, data errors or data loss will occur.

For example, the storage device100may be a flash drive. During the process of data writing, when the user inappropriately removes the flash drive from the host, normally the incompletely updated data will be lost.

In addition, a general nonvolatile memory is either an NAND flash memory or an exclusive NOR flash memory which does not write at a fast speed. When the storage device100writes the data into the nonvolatile memory10, it normally takes the user a long time to wait, which consequently causes inconvenience to the user.

SUMMARY OF THE INVENTION

An embodiment of present invention provides a storage unit controller. The storage unit controller includes an address mapping unit, a nonvolatile buffer and an update indicator. The nonvolatile buffer is coupled to the address mapping unit. The update indicator is coupled to the address mapping unit and the nonvolatile buffer. The update indicator sets an indicated flag according to whether a first data saved in the nonvolatile buffer is written to a storage unit. The address mapping unit checks the indicated flag when a power is on. When the checked indicated flag indicates that writing the first data is not completed, the address mapping unit enables an update operation mode.

Based on another perspective, another embodiment of the invention provides a memory control method, which includes setting the indicated flag according to whether the first data saved in the nonvolatile buffer is written into the storage unit; checking the indicated flag when the power is on; and enabling the update operation mode when the checked indicated flag indicates that the first data is not completed.

Based on another perspective, another embodiment of the invention provides a storage device, which includes a storage unit and a nonvolatile buffer. The nonvolatile buffer is coupled to a storage unit. When the host is to write the first data to the storage unit, the first data is written to a simulated address of the nonvolatile buffer, and then the first data is written to a first actual address of the storage unit from the simulated address.

It should be noted that the above general descriptions and the following embodiments are provided as examples for explanations only and therefore should not be construed as a limitation to the invention.

In order to make the aforementioned features and advantages of the invention more comprehensible, embodiments accompanying figures are described in detail below.

DESCRIPTION OF EMBODIMENTS

Descriptions of the disclosure are given with reference to the exemplary embodiments illustrated with accompanied drawings. Moreover, elements/components with same reference or similar numerals represent same or similar parts in the drawings and embodiments.

FIG. 2is a block diagram illustrating a storage device according to an embodiment of the invention. Please refer toFIG. 2; a storage device200includes a storage unit (e.g. a nonvolatile memory260) and a storage unit controller (e.g. a memory controller210). InFIG. 2and some embodiments of the invention, although the nonvolatile memory260and the memory controller210are provided as examples for description, they should not be construed as a limitation to the invention. In other embodiments, the storage device200may be a hard disk and other types of storage devices. InFIG. 2, the nonvolatile memory260(storage unit) may be replaced with, for example, a storage sector in the hard disk.

The memory controller210includes an address mapping unit220, a nonvolatile buffer230and an update indicator240. The update indicator240may be coupled to the address mapping unit220and the nonvolatile buffer230. The nonvolatile buffer230may be coupled to the address mapping unit220and the nonvolatile memory260. In the write operation, the nonvolatile buffer230may be used as a write buffer; in the read operation, the nonvolatile buffer230may be used as a read buffer.

The update indicator240may set an indicated flag IFL according to whether first data DA1saved in the nonvolatile buffer230is written to the nonvolatile memory260.

The address mapping unit220may be addressed using a mechanism of a simulated address and an actual address. The address mapping unit220may check the indicated flag IFL. When the indicated flag IFL indicates that writing the first data DA1is completed, the normal operation mode may be enabled for performing subsequent write operation or read operation. When the indicated flag IFL indicates that writing the first data DA1is not completed, it may be because the data is not completely updated during the writing operation. In other embodiments, the occurrence of power-off during the previous writing process may result in an incomplete operation of writing the first data DA1. At that point, an update operation mode may be enabled to update the incomplete previous operation of writing the first data DA1.

Under the normal operation mode, if the host280notifies via a bus270that the address mapping unit220of the storage device200is to write the first data DA1to an actual address Add1of the nonvolatile memory260, the address mapping unit220may address the first data DA1as follows: providing a simulated address Bdd1corresponding to the actual address Add1, wherein the actual address Add1may have the same address value as the simulated address Bdd1, and the simulated address Bdd1and the actual address Add1refer to memory locations disposed in the nonvolatile buffer230and the nonvolatile memory260respectively; recording the simulated address Bdd1and then the update operation mode may be enabled for performing an update operation; saving the first data DA1at the simulated address Bdd1of the nonvolatile buffer230; transferring the first data DA1from the simulated address Bdd1of the nonvolatile buffer230to the actual address Add1of the nonvolatile memory260. After executing the abovementioned addressing and update operation, the address mapping unit220adopts a normal address mapping for the first data DA1. More specifically, the abovementioned normal address mapping is, for example, if a host280is to read the first data DA1, the first data DA1may be read from the actual address Add1of the nonvolatile memory260or via another read buffer.

A speed of data written to the nonvolatile buffer230may be far faster than a speed of the data written to the nonvolatile memory260. For instance, the nonvolatile buffer230may be a resistive random access memory (RRAM), a magnetoresistance random access memory (MRAM), a ferroelectric random access memory (FRAM), a phase change random access memory (PRAM), a conductive bridge random access memory (CBRAM), or other memories that may implement the embodiments of the invention. The nonvolatile memory may be an NAND flash memory, an exclusive NOR flash memory, or a solid state disk. In other embodiments, the nonvolatile memory may also be the abovementioned RRAM, MRAM, FRAM, PRAM, CBRAM, or other memories that may implement the embodiments of the invention. In that case, before the first data DA1is saved in the actual address Add1, the nonvolatile buffer230may save the first data DA1at a high speed.

In the writing process of the saving the data in the actual address Add1, when the power supply for the storage device200is removed, even if the first data DA1is not completely written to the actual address Add1, the first data DA1is saved at the simulated address Bdd1of the nonvolatile buffer230so that the data may not be lost. On the other hand, the first data DA1may be a general term for a plurality of data. When a plurality of data is to be written to the storage device200, since the plurality of data may be saved in the nonvolatile buffer230and transferred, if the speed of the data written to the nonvolatile buffer230is far faster than the speed of the data written to the nonvolatile memory260, the user may not suffer from the inconvenience of spending a long time waiting for the memory to be updated.

In addition, under the update operation mode, a simulated address mapping may be adopted for the first data DA1.

When the checked indicated flag IFL indicates that writing the first data DA1is not completed, the address mapping unit220may enable the update operation mode so as to execute the background operation: in an embodiment, the first data DA1may not be completely written to the nonvolatile memory260due to sudden removal of the power supply for the storage device200; nevertheless, the first data DA1has been saved at the simulated address Bdd1of the nonvolatile buffer230. Therefore, after the power supply is recovered, the background operation may be executed so as to transfer the first data DA1from the simulated address Bdd1of the nonvolatile buffer230to the actual address Add1of the nonvolatile memory260. When the update operation is completed, the update indicator240may clear the incomplete status indicated by the indicated flag IFL.

In one embodiment, the process of reading data via the simulated address mapping is described. For example, when the checked indicated flag IFL indicates that writing the first data DA1is not completed while the host280is to read the first data DA1of the storage device200via the bus270, the address mapping unit220may transmit the first data DA1at the simulated address Bdd1via the nonvolatile buffer230to the host280.

Furthermore, after the read operation is performed, the address mapping unit220may transfer the first data DA1from the nonvolatile buffer230to the actual address Add1of the nonvolatile memory260. When the update operation is completed, the update indicator240clears the incomplete status indicated by the indicated flag IFL.

In one embodiment, the nonvolatile buffer230may include a first buffer unit232and a second buffer unit234. The first buffer unit232may be coupled to the address mapping unit220and the update indicator240. The second buffer unit234may be coupled to the address mapping unit220, the update indicator240and the first buffer unit232. The first buffer unit232may function as a write buffer. During the process in which the address mapping unit220addresses and updates the first data DA1, the first data DA1is initially saved at the simulated address Bdd1of the first buffer unit232, and then the first data DA1is transferred from the simulated address Bdd1to the actual address Add1of the nonvolatile memory260. The second buffer unit234may function as a write backup buffer of the first buffer unit232or a read buffer of the nonvolatile memory260.

In another embodiment, if the host280is to read the data at other addresses under the update operation mode, the second buffer unit234may function as the read buffer of the nonvolatile memory260. Table 1 explains the corresponding functions of the first buffer unit232and the second buffer unit234under different modes in one of the embodiments. Please refer to Table 1, which should not be construed as a limitation to the embodiments of the invention. The first buffer unit or the second buffer unit may have different functions depending on actual requirements.

Under the update operation mode, the address mapping unit220may execute the background operation to transfer the first data DA1at the simulated address Bdd1from the first buffer unit232to the actual address Add1of the nonvolatile memory. When the first buffer unit232is under the update operation mode while the host280is to write the second data DA2via the memory controller210, the address mapping unit220not only may execute the abovementioned background operation, but also save the second data DA2at the simulated address Bdd2via the second buffer unit234, and transfer the second data DA2to the actual address Add2of the nonvolatile memory260.

The memory controller210may also include a status register250. The status register250may be coupled to the update indicator240and the address mapping unit220. The status register250may generate busy status information based on the indicated flag IFL. The address mapping unit220may check the status register250to know whether the buffer unit is busy such as performing the update operation.

FIG. 3is a flowchart illustrating a method for controlling a storage unit such as a memory according to an embodiment of the invention. Please refer to bothFIGS. 2-3, in step S301, the power is on may represent that the storage device200is connected to the power supply.

In step S302, the indicated flag IFL is checked to see whether it is set as “update is completed”. If yes, in step S303, the normal operation mode is enabled and step S304is carried out; if not, in step S306, the update operation mode is enabled to proceed with the update operation mode.

In step S304, it may be determined whether the data at a specific address is written/erased. If not, step S303is resumed; if determined “yes” in step S304, step S305is carried out and the indicated flag IFL is cleared to be set as “data writing is not completed”. The abovementioned specific address may be an actual address Add1. Before the first data DA1is to be written to the actual address Add1, the address mapping unit may perform addressing first; the addressing operation may include providing a simulated address Bdd1corresponding to the actual address Add1and recording the simulated address Bdd1. Thereafter, the update operation mode is enabled in step S306.

In step S306, the update operation mode is enabled. Thereafter, as shown in step S307, the status register250is checked to see whether it is not busy (for example, the update procedure is completed). If yes, in step S308, the indicated flag IFL is set as “update is completed”; in step S303, the normal operation mode is enabled. In one embodiment, the indicated flag IFL may be set as “update is completed” via the first buffer unit232or the second buffer unit234. If determined “no” in step S307, step S306is resumed to execute the update procedure again.

Based on the disclosure of the above embodiments, a universal method for controlling the storage unit may be developed. More specifically,FIG. 4is a flowchart illustrating a method for controlling a storage unit such as a memory according to an embodiment of the invention. Please see bothFIGS. 2 and 4. The method for controlling the storage unit of the embodiments may include the following steps.

The indicated flag IFL is set according to whether the first data DA1saved in the nonvolatile buffer230is written to the nonvolatile memory260(storage unit) (step S401). The indicated flag IFL is checked when power is on (step S402). When the checked indicated flag IFL indicates that writing the first data DA1is not completed, the update operation mode is enabled so as to execute the background operation. The background operation can be that the first data DA1, which is not completely written to the nonvolatile memory260during the previous operation and saved at the simulated address Bdd1of the nonvolatile buffer230, is transferred from the simulated address Bdd1of the nonvolatile buffer230to the actual address Add1of the nonvolatile memory260(step S403).

In addition, when the checked indicated flag IFL indicates that writing the first data DA1is not completed while the host280is to read the first data DA1, the first data DA1may be read via the nonvolatile buffer230. More specifically, the first data DA1located at the simulated address Bdd1may be transmitted to the host280via the first buffer unit232. When the first buffer unit232is under the update operation mode while the host280is to write the second data DA2, the second data DA2may be addressed to the actual address Add2of the nonvolatile memory260via the second buffer unit234. In another embodiment, when the checked indicated flag IFL indicates that writing the first data DA1is not completed while the host280is to read third data (not shown) saved in the nonvolatile memory260, the third data may be read via the second buffer unit234.

Based on the above, in the embodiments of the invention, before the data is written to the actual address, the data may be saved in the nonvolatile buffer at a high speed, and the content may still be kept after the power supply is removed, the problem of data loss caused by the user's inappropriate operation in prior art may be effectively solved. On the other hand, the speed of the data written to the simulated address of nonvolatile buffer is faster than the speed of the data written to the actual address of the nonvolatile memory. Accordingly, when a plurality of data is written to the storage device, the user may not suffer from the inconvenience of spending a long time waiting for the memory to be updated.

Moreover, any advantages or benefits of the all the objects of the disclosure described may not apply to all embodiments or claims of the invention. Meanwhile, the abstract and title of the disclosure are provided to facilitate a searcher to locate patent literature, and it is submitted with the understanding that they will not be used to limit the scope or meaning of the claims.