Method for optimizing direct wafer bond line width for reduction of parasitic capacitance in MEMS accelerometers

A method for optimizing direct wafer bond line width for reduction of parasitic capacitance in a MEMS device by reducing the width of a bond line between a first and a second wafer, exposing the MEMS device to a water vapor for a predetermined time period and at a first temperature capable of evaporating water, cooling the MEMS device at a second temperature capable of freezing the water, and operating the MEMS device at a third temperature capable of freezing the water to determine if there is discontinuity during operation.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates generally to Micro-Electro-Mechanical Systems (MEMS). More particularly, the invention relates to a method for optimizing wafer bond line width for reduction of parasitic capacitance in MEMS accelerometers.

2. Description of Related Art

Micro-Electro-Mechanical Systems (MEMS) is the integration of mechanical elements, sensors, actuators, and electronics on a common silicon substrate through microfabrication technology. The electronics in a MEMS device are fabricated using Integrated Circuit (IC) technology (CMOS, Bipolar, or BICMOS processes), while the micromechanical components are fabricated using “micromachining” techniques that selectively etch away or add new layers to the silicon wafer to form mechanical and electromechanical devices.

MEMS devices are widely used in automotives, navigation systems, chemical and biological sensors, microoptics, accelerometers, pressure sensors and other devices. A common approach to fabrication of MEMS devices is the so-called bulk MEMS process. This process consists of processing two or three silicon wafers with patterns machined by Deep Reactive Ion Etching (DRIE) to form the structure used in each layer, and then bonding these layers together by a process called direct bonding to form a hermetic cavity.

SUMMARY OF THE INVENTION

A process for optimizing direct wafer bond line width for reduction of parasitic capacitance in a MEMS device. The process involves reducing the width of a bond line between a first and a second wafer, exposing the MEMS device to water vapor for a predetermined time period and at a first temperature capable of evaporating the water, cooling the MEMS device at a second temperature capable of freezing the water, and operating the MEMS device at a third temperature capable of freezing the water to determine if there is discontinuity during operation.

In one embodiment the bond line width is reduced to approximately 100-200 microns. To optimize direct wafer bond, a different bond line width can be used to determine its operability and reliability at design conditions.

In another embodiment the first temperature used for evaporating water is approximately 100° C. The second temperature can approximately be below 0° C., preferably about −55° C. The third temperature can be approximately equal to the second temperature.

The process further includes a method of calculating the leak rate through the bond line by dividing the volume of fluid in the MEMS device by the predetermined time period. To achieve an acceptable leak rate, a different bond line width of the MEMS device can be used to reduce discontinuity during operation and achieve optimum operability and reliability of the MEMS device.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Methods and systems that implement the embodiments of the various features of the invention will now be described with reference to the drawings. The drawings and the associated descriptions are provided to illustrate embodiments of the invention and not to limit the scope of the invention. Reference in the specification to “one embodiment” or “an embodiment” is intended to indicate that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least an embodiment of the invention. The appearances of the phrase “in one embodiment” or “an embodiment” in various places in the specification are not necessarily all referring to the same embodiment. Throughout the drawings, reference numbers are re-used to indicate correspondence between referenced elements. In addition, the first digit of each reference number indicates the figure in which the element first appears.

FIG. 1is a perspective view of a prior art silicon accelerometer sensor100before assembly. The sensor100has a first outside layer110, a second outside layer115, a first guard layer120, a second guard layer125, and a proof mass layer130. The proof mass layer130is sandwiched between the first and second guard layers120and125, which are then sandwiched between the first and second outside layers110and115. The sensor100also has a via135to facilitate a path or opening for circuit shorting. The sensor100is fabricated from two silicon-on-insulator (SOI) wafers and one prime silicon wafer. The SOI wafers provide the first and second outside layers110and115, and the first and second guard layers120and125. The prime silicon wafer provides the proof mass layer130.

On the surface of each wafer layer110-130is a layer of oxide, typically 1 micron thick. When the layers120-130are bonded together, a 2 micron layer of oxide is formed between the guard layers120and125and the proof mass layer130.

One technique to bond all the wafer layers110-130together is by a process called direct bonding. Before bonding, the wafer layers110-130are preferably cleaned and activated. Activation is done by either chemical or plasma surface activation. The wafer layers110-130are properly aligned and coupled to each other. Van Der Waals forces will cause the layers110-130to bond to each other. Since the Van Der Waals forces are relatively weak, the wafer layers110-130may be annealed at an elevated temperature. This temperature depends on the activation process. Older processes used temperatures in excess of 1000° C. With newer plasma processes, 400° C. may suffice. It can be envisioned that other methods or techniques can be used to bond the layers110-130together and achieve the same objective of the present invention.

FIG. 2is an assembly drawing of the silicon accelerometer sensor100ofFIG. 1. The assembly drawing shows the internal components of sensor100. Contained within the proof mass layer130is a proof mass paddle205that may be coupled to the proof mass layer130by silicon hinges. On opposite sides of the paddle205are electrodes.FIGS. 2and3show electrodes210contained within the guard layers120and125and parallel to one another. This configuration forms a capacitor between each electrode210and the paddle205. In operation, the capacitance is used to determine the gap between the paddle205and each electrode210. An electronic circuit supplies the proper voltage pulses to force the paddle to null, defined as the paddle position where both capacitances are equal.

FIG. 3is a side view of a silicon accelerometer sensor300, according to one embodiment of the present invention. The sensor300has an internal cavity315enclosed by layers110-130. The internal cavity315houses the paddle205and electrodes210, leaving a gap320between them. The sensor300also has a PM-G bond line305formed between the proof mass layer130and first and second guard layers120and125. Similarly, the sensor300has a G-E bond line310formed between the guard layers120and125and the outside wafer layers110and115, respectively.

To decrease the PM-G parasitic capacitance, the width of the bond line305between the proof mass and guard should be decreased. However, as the width of the bond line305is decreased, the bond strength is decreased, and the ruggedness and reliability of the chip may become compromised. Typically, the prior art width used for bond line305is 400 microns. This prior art width is a consequence of fabrication techniques used that does not account for the optimum width necessary to reduce parasitic capacitance and maintain reliable bond strength.

From a bond strength standpoint, the bond line305can be reduced substantially without compromising the reliability of the chip. Using a prior art bond line305of 400 microns, the sensor300can withstand a tensile force of about 50 lbs. Given the mass of the outside wafer layer110or115is 30 mg, the G loading would be about 700,000 G and the tensile strength of the oxide would be about 3400 PSI. On a number of sensors300, the bonds do not necessarily delaminate, but the silicon breaks instead. Consequently, from a strength standpoint, the bond line305can be reduced by a factor of 2 to 4 without compromising the reliability of the chip.

Although a decrease in the width of the bond line305may not substantially affect the bond strength of the sensor300, it may affect the hermeticity of the chip, either by increased leak failures or inherent permeability of the silicon dioxide. According to one embodiment of the present invention, a method for optimizing bond line305width for reduction of parasitic capacitance in MEMS accelerometers is provided.

Referring toFIGS. 4 and 5, an application for practicing the method embodying the present invention, is generally designated400. The sensor300is exposed to water vapor using a steam furnace or oven405. Although a method utilizing an oven405is described herein, the method of the present invention applies equally to other steam producing sources.

According to a method embodying the present invention, the steam oven405is heated, at step500, to an elevated temperature for evaporating water. For example, the temperature of the oven or furnace405can be preheated to approximately 100° C. A thermal controller410can be used to set the temperature of the steam oven405, and a timer415can be used to set the period of exposure of the sensor300to the water vapor420.

Once the steam oven405reaches the desired temperature, the MEMS device or sensor300is inserted, at step510, for a desirable or predetermined period, for example, 24 hours. The period of exposure to the water vapor420is used in calculating the leak rate, which is discussed in detail below.

After bombing the MEMS device or sensor300with water vapor420for a specific period, the MEMS device is removed, at step520, from the steam oven405and allowed to cool, at step530, at a temperature below 0° C. In one embodiment, the MEMS device is cooled to a temperature of −55° C., as required by the military operational guidelines. At step540, the MEMS device or sensor300is then tested at the temperature (below 0° C.) to determine if there is any discontinuity in performance of the device during operation.

Referring toFIG. 6, a method for determining leak rate of an accelerometer sensor300is provided in accordance with the present invention. When a MEMS device or sensor300is tested at a temperature below 0° C., for example −55° C., discontinuity during operation (Step600) may occur. If the sensor300does not show any discontinuity during operation at −55° C., then the sensor300does not leak, at step610, and consequently, the reduced width of bond line305does not compromise the reliability of the chip.

Conversely, at step620, if there is a discontinuity in performance during operation, then the MEMS device or sensor300has a leak that allowed water vapor420to seep through and crystallize at lower temperature. Because the gap320between the paddle205and the electrodes210is about 2 microns, when the temperature is lowered to the −55° C. lower operating limit, even a very small vapor pressure in the sensor300will form an ice crystal or dendrite that blocks the motion of the paddle. This shows up as a discontinuity in the accelerometer test. At a temperature of −60° C., there is enough water in the chip to form a pillar of ice over 3 microns in diameter on both sides of the paddle205.

At step630, the leak rate can be calculated by dividing the volume of the sensor's internal cavity315by the water vapor bombing time period. The leak rate depends on (1) the temperature at which discontinuity occurs, and (2) the time and temperature at which a MEMS device is bombed with water vapor. For example, suppose a MEMS device is bombed with saturated steam at about 100° C. for 24 hours. If there is discontinuity at 0° C., it indicates that the vapor pressure of water in the MEMS device is above the equilibrium vapor pressure of ice or water at that temperature (4.58 mm of Hg). Given the volume of the internal cavity315of a sensor300is about 4.36 μL, the chip would contain about 2.6×10−6cm3of water. Since, the MEMS device was exposed for 24 hours, it would have accumulated that water in 86,400 seconds, so the leak rate would be 3×10−10cm3/s.

Similarly, if the chip shows a discontinuity at −50° C., where the vapor pressure is 0.03 torr, then the leak rate is 2×10−12cm3/s. These results show that the method embodying the present invention provides greater sensitivity than the prior art krypton bombing method.

It can be envisioned that bombing with water vapor420can be accomplished at a different time and temperature. For example, the bomb time or temperature could be increased. A temperature of 120° C. would approximately double the external water vapor pressure and a temperature of 180° C. would increase it 10 fold. Alternatively, the MEMS device can be cooled to a temperature even lower than −55° C. during testing.

One factor that should be taken into account at low temperatures, where the total amount of water condensing is low, is the possibility that all the water vapor420in the MEMS device could condense at some benign spot, so that the operation of the device would be unaffected. This may result in a false pass. However, based on experimental results obtained for low temperature failures, it appears that the gap320is a good nucleation area for the water vapor420.

It is understood by a person skilled in the art that a sensor300can be fabricated with a combination of the prior art bond line305width of 400 microns with the reduced bond line305width of 100-200 microns. If this sensor300is subjected to water vapor bombing, at step510, then any compromise of hermeticity with the reduced bond line305width could be determined statistically during operation testing, at step540.

Although a decrease in the width of the bond line305may not substantially affect the bond strength of the sensor300, it may affect the hermeticity of the chip, either by increased leak failures or inherent permeability of the silicon dioxide.

Although the hermeticity of a MEMS device depends on leak rates, it is also affected by inherent permeability of the silicon dioxide. Even if there is a perfect seal, permeation of water vapor420through the oxide may affect hermeticity. To determine the effect of permeation on the hermeticity of MEMS devices, permeation data were ascertained for Helium, Hydrogen, Deuterium and Neon at 700° C. At this temperature the permeation coefficient of Neon (the closest of the four to water in size) is about 1×10−9cm3mm/cm2sec cm of Hg. Hydrogen and Deuterium are about twice as large as Neon, while Helium is about 20 times as large as Neon. The permeation coefficient of Neon would be equivalent to a leak rate of about 10−9cm3/s.

If the MEMS device is bombed with water vapor420at a temperature of 100° C., the permeation constants would likely be several orders of magnitude lower than Neon at 700° C. Consequently, permeation through the oxide layer would not affect the hermeticity and reliability of a MEMS device with a reduced bond line305width of 100-200 microns. Even if permeation proved to be an issue for the long term stability of the MEMS device, it could be dealt with, for example, by filling the MEMS device with the same gas as the system housing the device.