Monitoring testkey used in semiconductor fabrication

A monitoring testkey for a wafer is provided. The monitoring testkey includes a first metal oxide semiconductor (MOS) transistor having a channel extending in a first direction, a second MOS transistor having a channel extending in a second direction, a common gate pad electrically connected to gate electrodes of the first MOS transistor and the second MOS transistor, a first source pad electrically connected to source electrodes of the first MOS transistor and the second MOS transistor, a first drain pad electrically connected to a drain electrode of the first MOS transistor, and a second drain pad electrically connected to a drain electrode of the second MOS transistor. The monitoring testkey helps to improve the critical dimension uniformity and electrical characteristics uniformity of elements in a wafer.

TECHNICAL FIELD

The present invention relates generally to a monitoring testkey, and more particularly to a monitoring testkey used in semiconductor fabrication.

BACKGROUND

In fabrication of semiconductors, the minimum line width of the circuit element is called critical dimension (CD). The smaller the circuit element is, the less variation of the CD is allowed. Thus, many techniques for improving the critical dimension uniformity (CDU) are developed, and exposure-dose control system, which is named DoseMapper (DOMA) and developed by ASML Company, is a typical one of such techniques.

However, CDU improvement is just one of the factors should be considered during fabrication of semiconductors. There is also a desire to improve uniformity of electrical characteristics of different devices at different positions of a wafer.

SUMMARY

In one embodiment, a monitoring testkey includes a first metal oxide semiconductor (MOS) transistor having a channel extending in a first direction, a second MOS transistor having a channel extending in a second direction, a common gate pad electrically connected to gate electrodes of the first MOS transistor and the second MOS transistor, a first source pad electrically connected to source electrodes of the first MOS transistor and the second MOS transistor, a first drain pad electrically connected to a drain electrode of the first MOS transistor, and a second drain pad electrically connected to a drain electrode of the second MOS transistor.

In another embodiment, a testing method of the above monitoring testkey includes: applying a first on-state voltage to the first MOS transistor from the common gate pad while grounding the first source pad; and applying a first voltage to the first drain pad and measuring a first on-state current.

In still another embodiment, a monitoring testkey includes a MOS transistor, a source pad electrically connected to a source electrode of the MOS transistor, a drain pad electrically connected to a drain electrode and a gate electrode of the MOS transistor; and a monitoring pattern formed below the drain pad. The monitoring pattern includes a plurality of bar shaped structures arranged in parallel.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

FIG. 1illustrates a monitoring pattern, which includes a number of bar shaped patterns10arranged in parallel. This monitoring pattern can be formed by a lithography method with a standard exposure. In addition, this monitoring pattern can be distributed at different positions of a wafer. As such, the width of the bar shaped patterns10can be measured, and the CD variation at different positions of a wafer is accordingly obtained. The exposure can be controlled and adjusted according to the obtained CD variation. Thus, the CDU is improved.

FIG. 2illustrates a layout of a monitoring testkey in accordance with an embodiment of the present invention. The monitoring testkey includes four metal oxide semiconductor (MOS) transistors of different conductivity type and extends in different directions. In the present embodiment, the four MOS transistor includes a NMOS21having a channel extending along an x-axis direction, a NMOS22having a channel extending along a y-axis direction, a PMOS23having a channel extending along the x-axis direction, and a PMOS24having a channel extending along the y-axis direction. The channel extends along the x-axis direction means that a lengthwise direction of the channel is parallel to the x-axis direction. The x-axis direction, for example, is parallel to lateral scribe lines of a wafer, and the y-axis directions, for example, is parallel to longitudinal scribe lines of the wafer.

Gate electrodes of the four MOS transistors are connected to a common gate pad251and a monitoring pattern same to that shown inFIG. 1is directly below the common gate pad251. The monitoring pattern includes a number of bar shaped polysilicon20arranged in parallel. In addition, the NMOS21and22share a first source pad252, the PMOS23and24share a second source pad253. The NMOS22and the PMOS23share a first drain pad254, and the NMOS21and the PMOS24share a second drain pad255. As such, the monitoring testkey has a compact layout and a symmetrical shape. In total, the monitoring testkey includes five pads and a monitoring pattern. Besides, similar to the monitoring pattern ofFIG. 1, the monitoring testkey can also be distributed at different positions of a wafer.

As shown inFIG. 2and related descriptions above, the present embodiment forms four MOS transistors of different conductivity type and extending directions around the bar shaped polysilicon20. Except the CD variation obtained by measuring the width of the bar shaped polysilicon20at different positions of a wafer, the on-sate current variation can also be obtained by measuring the four MOS transistors. Thus, the exposure or other process parameters can be controlled and adjusted according both to the CD variation and the on-state current variation. Accordingly, the CDU and uniformity of electrical characteristics such as on-state current can be improved.

FIGS. 3A,3B, and3C are schematic view illustrating the distribution of the monitoring testkey in a wafer. As shown inFIG. 3A, a wafer includes a number of square chips31arranged in an array, and a monitoring testkey30ofFIG. 2is located at each of the four corners of each of the chips31. Because the monitoring testkey30is located at the corner, this distribution minimizes the influence to the layout of the functional circuits and elements in the chips31. To maximize the uniformity of electrical characteristics, as shown inFIG. 3B, a number of (e.g., five) monitoring testkeys can be uniformly distributed in each of the chips31. To balance the influence to the layout of the functional circuits and elements in the chips31and the uniformity of electrical characteristics, as shown inFIG. 3C, each of the chips31may include one monitoring testkey30located at a center thereof.

The monitoring testkey can be simultaneously formed with the elements in the chip, which is described as follows with reference toFIGS. 4A through 4G. First, in a process for defining active regions of functional circuits and elements, a pattern as shown inFIG. 4Ais also defined, wherein regions41,42,43,44define the total regions including source, drain and channel in the four MOS transistors21,22,23,24, respectively. Regions45,46,47,48define the substrate contact regions of the four MOS transistors21,22,23,24, respectively. A region40defines a region for forming the common gate pad and the monitoring pattern shown inFIG. 1. In general, the regions inFIG. 4A, except the regions40through48, are field oxide layers (not shown).

Referring toFIG. 4B, N wells431and441are formed to surround and enclose regions43,44,47,48that are used to form PMOS in the following process. After that, as shown inFIG. 4C, bar shaped polysilicon400and gate wires410,420,430,440required by the DOMA process are simultaneously formed in a process for defining the gate structure of the functional elements in the chip.

Referring toFIG. 4D, a high concentration N type implantation is performed using the gate wires410,420,430,440as a mask to form source/drain regions411,421of NMOS and substrate contact regions47,48of PMOS. The source/drain regions45to48define substrate contact regions of the four MOS transistors21,22,23,24, respectively. Similarly, as shown inFIG. 4E, a high concentration P type implantation is performed using the gate wires410,420,430,440as a mask to form source/drain regions411,421of PMOS and substrate contact regions45,46of NMOS.

Referring toFIG. 4F, a contact forming process is performed to form a number of contacts49on the source/drain regions, the substrate regions and the gate wires. Finally, as shownFIG. 4G, metal wires are formed. After this process, the five pads as shown inFIG. 2and the metal wires50for connecting the five pads to the corresponding source/drain regions are finished. The common gate pad251is electrically connected to the gate wires410,420,430,440of the four MOS transistors. In addition, source electrode of the NMOS21,22and the substrate share the first source pad252, the source electrode of the PMOS23,24and the substrate share the second source pad253. The drain electrode of the NMOS22and the drain electrode of the PMOS23share the first drain pad254. The drain electrode of the NMOS21and the drain electrode of the PMOS24share the second drain pad255.

As such, the monitoring testkey of the present embodiment and the original DOMA pattern (i.e., the bar-shaped polysilicon400) coexists and share regions of chips. In the present embodiment, the DOMA pattern is located directly under the gate pad251but is not electrically connected to any other circuits or elements. The monitoring testkey of the present embodiment includes MOS transistors of different conductivity type and orientation. These MOS transistors can demonstrate electrical characteristics of MOS transistors of different conductivity type and orientation and the DOMA pattern can show the CDU of circuits. During a wafer acceptance test (WAT), the pads251,252,253,254are used to perform the current test. For example, a positive on-state voltage is applied to the NMOS from the common gate pad251, and the first source pad252, the first drain pad254are grounded. Then, a voltage is applied between the second source pad253and the second drain pad255to measure the on-state current. Accordingly, on-state current of the NMOS21,22are obtained. Alternately, a negative on-state voltage is applied to the PMOS from the common gate pad251, and the first source pad252and the first drain pad254are grounded. Then, a voltage is applied between the second source pad253and the second drain pad255to measure the on-state current. Accordingly, on-state current of the PMOS23,24are obtained. Repeating the above testing process in each monitoring testkey in the wafer, on-state current variation can be obtained. The exposure or other process parameters can be adjusted according to the on-state current variation to improve the uniformity of on-state current. Besides, other electrical characteristics can also be measured to obtain the variations. Accordingly, the uniformity of other electrical characteristics can also be improved by adjusting the process parameters such as exposure.

In another embodiment, the monitoring testkey shown inFIG. 4Gis simplified as the one shown inFIG. 5. The monitoring testkey of the present embodiment includes a MOS transistor40and a monitoring pattern41. A source pad42that is electrically connected to a source electrode of the MOS transistor40is grounded. After an on-state voltage is applied to a drain pad43that is electrically connected to a drain electrode and a gate electrode of the MOS transistor40, the on-state current of the MOS transistor40is obtained. The monitoring testkey of the present embodiment has smaller area, and thus can be distributed in scribe lines of a wafer. As such, the monitoring testkey doesn't affect the layout of the functional elements in the chip. The monitoring pattern41can be formed directly below the drain pad43. The monitoring pattern41includes a number of bar shaped structures arranged in parallel. The bar shaped structures may be consisting of polysilicon, and are used to obtain the CD variation. The MOS transistor40is of a P type or an N type transistor, and a lengthwise direction of a channel thereof is parallel to the x-axis or the y-axis.