Display apparatus

A display apparatus includes: a display panel includes: a plurality of pixels to display an image; a gate driver to drive the pixels; a first part electrically connected to the pixels; and a second part electrically connected to the gate driver. The gate driver includes: a plurality of stages to generate a gate signal to be provided to the pixels; k number of clock wirings to provide k number of clock signals to the plurality of stages; and k number of clock bar wirings to provide k number of clock bar signals to the plurality of stages (where k is a natural number of one or greater), and the second part includes: k number of clock pads electrically connected to the k number of clock wirings, respectively; and k number of clock bar pads electrically connected to the k number of clock bar wirings, respectively. The k number of clock wirings and the k number of clock bar wirings are arranged in a first order, and the k number of clock pads and the k number of clock bar pads are arranged in a second order different from the first order.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority from and the benefit of Korean Patent Application No. 10-2020-0049436, filed on Apr. 23, 2020, which is hereby incorporated by reference for all purposes as if fully set forth herein.

BACKGROUND

Field

Implementations of the invention relate generally to a display apparatus and, more specifically, to a display apparatus having a gate driver embedded in a display panel with improved display quality.

Discussion of the Background

In general, a display apparatus includes a display panel including a plurality of gate lines, a plurality of data lines, and a plurality of pixels connected to the plurality of gate lines and the plurality of data lines. A gate driver provides gate signals to the plurality of gate lines and a data driver outputs data signals to the plurality of data lines are connected to the display panel.

The gate driver may be embedded directly in the display panel through a thin film process. The gate driver includes a plurality of stages and a plurality of wirings providing a gate driving signal to the plurality of stages.

SUMMARY

Display apparatus constructed according to the principles and embodiments of the invention can improve display quality by removing horizontal line smear.

For example, if the clock wirings and the clock bar wirings are alternately arranged, the magnitude of a ripple voltage generated in the reference voltage may decrease, thereby the horizontal line smear can be reduced or prevented from appearing on the screen of the display panel, thereby improving display quality.

Further, when the clock wirings and the clock bar wirings are alternately arranged, the difference in length between bridge wirings electrically connected to the clock wirings to which the clock signals are applied and the bridge wirings electrically connected to the clock bar wirings to which the clock bar signals are applied are reduced. When the difference in length between the bridge wirings is reduced, the difference decreases between the parasitic capacitances formed between the bridge wirings and the reference electrode, and as a result, the magnitude of a ripple voltage generated in the reference voltage can be reduced.

According to one aspect of the invention, a display apparatus including a display panel includes: a plurality of pixels to display an image; a gate driver to drive the pixels; a first part electrically connected to the pixels; and a second part electrically connected to the gate driver. The gate driver includes: a plurality of stages to generate a gate signal to be provided to the pixels; k number of clock wirings to provide k number of clock signals to the plurality of stages; and k number of clock bar wirings to provide k number of clock bar signals to the plurality of stages (where k is a natural number of one or greater), and the second part includes: k number of clock pads electrically connected to the k number of clock wirings, respectively; and k number of clock bar pads electrically connected to the k number of clock bar wirings, respectively. The k number of clock wirings and the k number of clock bar wirings are arranged in a first order, and the k number of clock pads and the k number of clock bar pads are arranged in a second order different from the first order.

A first clock wiring of the k number of clock wirings to receive a first clock signal may be disposed adjacent to a first clock bar wiring of the k number of clock bar wirings, receive a first clock bar signal having a phase inverted with respect to a phase of the first clock signal.

The first clock bar wiring may be disposed between the first clock wiring and a second clock wiring to receive a second clock signal delayed from the first clock signal.

The first part may include a first pad part and the second part may include a second pad part and the display panel may further include an intermediate wiring part to electrically connect the second pad part and the gate driver. The intermediate wiring part may further include: k number of first intermediate wirings to electrically connect the k number of clock pads to the k number of clock wirings, respectively; and k number of second intermediate wirings to electrically connect the k number of clock bar pads to the k number of clock bar wirings, respectively.

At least one of the k number of first intermediate wirings may intersect at least one of the k number of second intermediate wirings.

The k number of first intermediate wirings may be disposed on a first layer, and each of the k number of second intermediate wirings may include: a lower wiring disposed on the first layer; and an upper wiring disposed on a second layer different from the first layer.

At least one of the k numbers of first intermediate wiring may intersect the upper wiring of at least one of the k number of second intermediate wirings.

The intermediate wiring part may further include a contact part to which the lower wiring and the upper wiring are connected.

The lower wiring and the upper wiring may be directly connected in the contact part.

The contact part may include a bridge electrode to connect the lower wiring and the upper wiring.

The gate driver may further include: k number of first bridge wirings to connect the k number of clock wirings to the plurality of stages; and k number of second bridge wirings to connect the k number of clock bar wirings to the plurality of stages.

A first one of the k number of clock wirings to receive a first clock signal may be disposed adjacent to a first one of the k number of clock bar wirings, to receive a first clock bar signal having a phase inverted with respect to a phase of the first clock signal.

The first clock bar wiring may be disposed between the first clock wiring and a second clock wiring to receive a second clock signal delayed from the first clock signal.

A first bridge wiring connected to the first clock wiring may be longer than a second bridge wiring connected to the first clock bar wiring, and a first bridge wiring connected to the second clock wiring may be shorter than the second bridge wiring connected to the first clock bar wiring.

According to another aspect of the invention, a display apparatus including a display panel includes: a plurality of pixels to display an image; a gate driver to drive the pixels; a first part electrically connected to the pixels; and a second part electrically connected to the gate driver. The gate driver includes: a plurality of stages to generate a gate signal to be applied to the pixels; k number of clock wirings to apply k number of clock signals to the plurality of stages; and k number of clock bar wirings to apply k number of clock bar signals to the plurality of stages (where k is a natural number of one or greater), and the second part includes: k number of clock pads electrically connected to the k number of clock wirings, respectively; and k number of clock bar pads electrically connected to the k number of clock bar wirings, respectively. A first clock wiring of the k number of clock wirings to receive a first clock signal is disposed adjacent to a first clock bar wiring of the k number of clock bar wirings, to receive a first clock bar signal having a phase inverted with respect to a phase of the first clock signal, and a first clock pad electrically connected to the first clock wiring of the k number of clock pads is disposed adjacent to a second clock pad to receive a second clock signal delayed from the first clock signal.

The display apparatus may further include a flexible film coupled to one side of the display panel. The flexible film is electrically connected to the first part and the second part.

The first part may include a first pad part and the second part may include a second pad part and the display panel may further include an intermediate wiring part to connect the second pad part and the gate driver. The intermediate wiring part may further include: k number of first intermediate wirings to electrically connect the k number of clock pads to the k number of clock wirings, respectively; and k number of second intermediate wirings to electrically connect the k number of clock bar pads to the k number of clock bar wirings, respectively.

At least one of the k number of first intermediate wirings may intersect at least one of the k number of second intermediate wirings.

The k number of first intermediate wirings may be disposed on a first layer, and each of the k number of second intermediate wirings may include: a lower wiring disposed on the first layer; and an upper wiring disposed on a second layer different from the first layer.

At least one of the k number of first intermediate wirings may intersect the upper wiring of at least one of the k number of second intermediate wirings.

DETAILED DESCRIPTION

FIG.1is a plan view of an embodiment of a display apparatus constructed according to the principles of the invention.FIG.2Ais a plan view of a display panel shown inFIG.1, andFIG.2Bis a cross-sectional view taken along line BB-BB′ ofFIG.2A.

Referring toFIGS.1and2A, a display apparatus DD includes a display panel DP for displaying an image and a panel driver for driving the display panel DP. The panel driver may include a gate driver GDC and a data driver DDC.

The display panel DP includes a display area DA displaying an image and a non-display area NDA adjacent to the display area DA. The display area DA is an area in which an image is substantially displayed, and the non-display area NDA is a bezel area in which an image is not displayed. AlthoughFIG.1illustrates a structure in which the non-display area NDA is disposed to surround the display area DA, the embodiments are not limited thereto. The non-display area NDA may be disposed only on at least one side of the display area DA.

The display panel DP includes a plurality of gate lines GL1to GLn, a plurality of data lines DL1to DLm, and a plurality of pixels PX11to PXnm. The plurality of gate lines GL1to GLn extend in a first direction DR1and are arranged in parallel with each other in a second direction DR2crossing the first direction DR1. The second direction DR2may be orthogonal to the first direction DR1. The plurality of data lines DL1to DLm may be arranged in parallel in the first direction DR1and may extend in the second direction DR2.

The plurality of pixels PX11to PXnm may be arranged in the first and second directions DR1and DR2in the display area DA. The plurality of pixels PX11to PXnm may be arranged in a matrix form. Each of the plurality of pixels PX11to PXnm may be electrically connected to one of the plurality of gate lines GL1to GLn and one of the plurality of data lines DL1to DLm. Each of the pixels PX11to PXnm is turned on by a gate signal applied from a corresponding one of the gate lines, and receives a data voltage from a corresponding one of the data lines to display an image of a desired gradation.

The gate driver GDC sequentially outputs gate signals to the gate lines GL1to GLn. Accordingly, the plurality of pixels PX11to PXnm may be sequentially scanned row by row by the gate signals. The gate driver GDC may include a first gate driver GDC1and a second gate driver GDC2. The first gate driver GDC1may be electrically connected to one ends of the gate lines GL1to GLn, and the second gate driver GDC2may be electrically connected to the other ends of the gate lines GL1to GLn. Each of the first and second gate drivers GDC1and GDC2may include a shift register that sequentially outputs the gate signals. The first and second gate drivers GDC1and GDC2may operate simultaneously to output a gate signal to the same gate line at the same time. Accordingly, each of the gate lines GL1to GLn may receive the gate signal from the first and second gate drivers GDC1and GDC2through both ends of the gate line.

FIGS.1and2Aillustrate a structure in which the two gate drivers GDC1and GDC2are electrically connected to both the ends, respectively, of the gate lines GL1to GLn, but the embodiments are not limited thereto. That is, a structure may be employed in which only one of the first and second gate drivers GDC1and GDC2is electrically connected to the gate lines GL1to GLn.

The first and second gate drivers GDC1and GDC2may be embedded in the display panel DP. In other words, the first and second gate drivers GDC1and GDC2may be formed in the non-display area NDA of the display panel DP through a thin film process in which the pixels PX11to PXnm are formed in the display area DA of the display panel DP.

The data driver DDC converts image signals into data voltages and applies the data voltages to the data lines DL1to DLm of the display panel DP. The data driver DDC may include a plurality of data driving chips DIC1to DIC4. Each of the plurality of data driving chips DIC1to DIC4is electrically connected to corresponding data lines of the data lines DL1to DLm. Although the four data driving chips DIC1to DIC4are illustrated inFIG.1, the number of the data driving chips DIC1to DIC4is not particularly limited and may be variously changed.

The display apparatus DD may further include a plurality of flexible films CF1to CF4and a printed circuit board PCB. The plurality of flexible films CF1to CF4may be provided between the display panel DP and the printed circuit board PCB, and may electrically connect the display panel DP and the printed circuit board PCB. One end of each of the flexible films CF1to CF4is coupled to the display panel DP, and the other end of each of the flexible films CF1to CF4is coupled to the printed circuit board PCB.

InFIG.1, a structure is illustrated in which the data driving chips DIC1to DIC4are respectively mounted on the flexible films CF1to CF4, but the embodiments are not limited thereto. That is, the data driving chips DIC1to DIC4may be mounted directly on the display panel DP in a chip on glass (COG) method.

Various circuits for generating various control signals and power signals necessary to drive the display panel DP and the panel driver may be provided on the printed circuit board PCB.

Referring toFIG.2A, the display panel DP may further include first and second parts in the form of a first pad part PD1and a second pad part PD2, respectively. The first and second pad parts PD1and PD2are disposed in the non-display area NDA. The first pad part PD1may include a plurality of data pads electrically connected to the data lines DL1to DLm which connect with the pixels PX11to PXnm. The first pad part PD1may be coupled to the flexible films CF1to CF4to receive the data voltages from the data driving chips DIC1to DIC4mounted on the flexible films CF1to CF4.

The second pad part PD2includes a first driving pad part PD2_1electrically connected to the first gate driver GDC1and a second driving pad part PD2_2electrically connected to the second gate driver GDC2. The first driving pad part PD2_1includes a plurality of first driving pads for providing a first gate driving signal to the first gate driver GDC1, and the second driving pad part PD2_2includes a plurality of second driving pads for providing a second gate driving signal to the second gate driver GDC2.

The second pad part PD2may be connected to some of the flexible films CF1to CF4. The first driving pad part PD2_1is connected to a first flexible film CF1among the flexible films CF1to CF4, and the second driving pad part PD2_2is connected to a fourth flexible film CF4among the flexible films CF1to CF4. The first gate driving signal may be a signal outputted from a first data driving chip DIC1mounted on the first flexible film CF1, or a signal provided from the printed circuit board PCB. The second gate driving signal may be a signal outputted from a fourth data driving chip DIC4mounted on the fourth flexible film CF4, or a signal provided from the printed circuit board PCB.

The display panel DP further includes an intermediate wiring part CLP that electrically connects the second pad part PD2to the gate driver GDC. The intermediate wiring part CLP may include a first intermediate wiring part CLP1and a second intermediate wiring part CLP2. The first intermediate wiring part CLP1electrically connects the first driving pad part PD2_1to the first gate driver GDC1, and the second intermediate wiring part CLP2electrically connects the second driving pad part PD2_2to the second gate driver GDC2.

The second pad part PD2and the intermediate wiring part CLP will be described in detail later with reference toFIGS.5to12.

A backlight unit for providing light to the display panel DP may further be included in the display apparatus DD. In the case that the display panel DP is a liquid crystal display panel which does not emit light on its own, the backlight unit may be disposed on a rear surface of the liquid crystal display panel to provide light to the liquid crystal display panel. Each of the pixels PX11to PXnm may display an image having a desired gradation by adjusting the degree of transmission of the light provided from the backlight unit.

Referring toFIGS.2A and2B, the display panel DP includes a first display substrate FS, a second display substrate SS, and a liquid crystal layer LC. The first display substrate FS includes a first base substrate BS1and a pixel layer PP disposed on the first base substrate BS1. The pixel layer PP may include a thin film transistor, a pixel electrode, and a plurality of insulating layers constituting each of the pixels PX11to PXnm. The pixel layer PP may be provided in correspondence with the display area DA of the display panel DP. The first and second gate drivers GDC1and GDC2are disposed on the first base substrate BS1in correspondence with the non-display area NDA.

The second display substrate SS includes a second base substrate BS2and a reference electrode RE. The second base substrate BS2is disposed to face the first base substrate BS1. The liquid crystal layer LC is interposed between the first and second display substrates FS and SS. The reference electrode RE is disposed on the second base substrate BS2so as to face the pixel electrode with the liquid crystal layer LC interposed between the first and second display substrates FS and SS. A reference voltage is provided to the reference electrode RE. The reference electrode RE may be disposed on the entirety of a rear surface of the second base substrate BS2. Accordingly, the reference electrode RE may face the first and second gate drivers GDC1and GDC2in the non-display area NDA. The second display substrate SS may further include a color filter layer and a black matrix layer.

The display panel DP further includes a sealant SLT disposed in the non-display area NDA to couple the first and second display substrates FS and SS. The space between the first and second display substrates FS and SS may be sealed by the sealant SLT. The first and second gate drivers GDC1and GDC2may overlap the sealant SLT.

FIG.3Ais a block diagram of a first gate driver shown inFIG.1, andFIG.3Bis a waveform diagram of first to fourth clock signals and first to fourth clock bar signals applied to the first gate driver ofFIG.3A.FIG.4is a circuit diagram of an embodiment of the first stage ofFIG.3A.

Although the block diagram of the first gate driver GDC1is illustrated inFIG.3A, the second gate driver GDC2has a configuration similar to that of the first gate driver GDC1. Accordingly, the configuration of the first gate driver GDC1is described with reference toFIG.3A, and a description of the configuration of the second gate driver GDC2will be omitted to avoid redundancy.

Referring toFIG.3A, the first gate driver GDC1may include a plurality of stages dependently connected to each other. The stages may be electrically connected to the gate lines GL1to GLn (illustrated inFIG.2A), respectively. The plurality of stages may respectively output the gate signals to the gate lines GL1to GLn.

Hereinafter, first to eighth stages SRC1to SRC8among the plurality of stages are exemplarily illustrated inFIG.3A. Although the first to eighth stages SRC1to SRC8are illustrated, additional stages may also be provided in substantially the same configuration.

Each of the first to eighth stages SRC1to SRC8(hereinafter referred to as stages SRC1to SRC8) includes an input terminal IN, a control terminal CT, a clock terminal CK, a first voltage terminal V1, a second voltage terminal V2, a reset terminal SP, an output terminal OUT, and a carry terminal CR.

The carry terminal CR of each of the stages SRC1to SRC8is electrically connected to an input terminal IN of a next stage. An i-th stage may output an i-th carry signal through the carry terminal CR. Here, i is defined as a natural number. The input terminal IN of the first stage SRC1receives, instead of a carry signal of a previous stage, a vertical start signal STV that starts the driving of the gate driver GDC1through a start signal wiring STVL. The input terminal IN of each of the stages SRC2to SRC8after the first stage SRC1receives a carry signal of a previous stage. The input terminal IN of the i-th stage is electrically connected to the carry terminal CR of an (i−1)-th stage. For example, the input terminal IN of the second stage SRC2receives a carry signal of the first stage SRC1, and the input terminal IN of the third stage SRC3receives a carry signal of the second stage SRC2.

This configuration is only an example, and the input terminal IN of the i-th stage may also be electrically connected to a carry terminal of a previous stage, for example, a carry terminal of the (i−1)-th stage, an (i−2)-th stage, an (i−3)-th stage, or the like.

The control terminal CT of the i-th stage is electrically connected to the carry terminal CR of an (i+1)-th stage, and receives a carry signal of the (i+1)-th stage. For example, the control terminal CT of the first stage SRC1receives the carry signal of the second stage SRC2, and the control terminal CT of the second stage SRC2receives a carry signal of the third stage SRC3.

The clock terminal CK of the i-th stage receives a corresponding signal among a plurality of clock signals and a plurality of clock bar signals through a plurality of clock wirings (e.g., first to fourth clock wirings CKL1to CKL4), and a plurality of clock bar wirings (e.g., first to fourth clock bar wirings CKBL1to CKBL4). The plurality of clock signals may be first to fourth clock signals CK1to CK4, and the plurality of clock bar signals may be first to fourth clock bar signals CKB1to CKB4. However, the number of the plurality of clock signals CK1to CK4and the number of the plurality of clock bar signals CKB1to CKB4are not limited thereto, and may have various values.

Specifically, referring toFIG.3B, a first period P1may be a period in which the level of each of the first to fourth clock signals CK1to CK4becomes a high voltage, and a second period P2may be a period in which the level of each of the first to fourth clock signals CK1to CK4becomes a low voltage. Also, the first period P1may be a period in which the level of each of the first to fourth clock bar signals CKB1to CKB4becomes a low voltage, and the second period P2may be a period in which the level of each of the first to fourth clock bar signals CKB1to CKB4becomes a high voltage. That is, the first clock signal CK1and the first clock bar signal CKB1have a phase difference of about 180 degrees, and the second clock signal CK2and the second clock bar signal CKB2have a phase difference of about 180 degrees. The third clock signal CK3and the third clock bar signal CKB3have a phase difference of about 180 degrees, and the fourth clock signal CK4and the fourth clock bar signal CKB4have a phase difference of about 180 degrees. Periods during which the first to fourth clock signals CK1to CK4are respectively at the high voltage may overlap each other, and periods during which the first to fourth clock bar signals CKB1to CKB4are respectively at the high voltage may overlap each other.

According to an embodiment, the first to fourth clock signals CK1to CK4are respectively provided to the clock terminals CK of the first to fourth stages SRC1to SRC4. Accordingly, the first to fourth stages SRC1to SRC4sequentially output first to fourth gate signals to the output terminals OUT thereof in response to the first to fourth clock signals CK1to CK4. The output terminals OUT of the first to fourth stages SRC1to SRC4are respectively connected to first to fourth gate lines GL1to GL4. Thereafter, the first to fourth clock bar signals CKB1to CKB4are respectively provided to the clock terminals CK of the fifth to eighth stages SRC5to SRC8. Accordingly, the fifth to eighth stages SRC5to SRC8sequentially output fifth to eighth gate signals to the output terminals OUT thereof in response to the first to fourth clock bar signals CKB1to CKB4. The output terminals OUT of the fifth to eighth stages SRC5to SRC8are respectively connected to fifth to eighth gate lines GL5to GL8.

The above-described operation method may be repeatedly performed in units of eight stages. When the number of the clock signals is k and the number of the clock bar signals is k, the operation may be repeatedly performed in units of 2k number of stages. Here, k may be a natural number of one or greater.

The first gate driver GDC1includes a plurality of clock wirings and a plurality of clock bar wirings. The plurality of clock signals are respectively provided to corresponding stages among the plurality of stages through the plurality of clock wirings. The plurality of clock wirings may be four clock wirings (hereinafter referred to as first to fourth clock wirings CKL1to CKL4), and the plurality of clock bar wirings may be four clock bar wirings (hereinafter referred to as first to fourth clock bar wirings CKBL1to CKBL4). The first to fourth clock signals CK1to CK4are respectively provided to the first to fourth stages SRC1to SRC4through the first to fourth clock wirings CKL1to CKL4. The first to fourth clock bar signals CKB1to CKB4are respectively provided to the fifth to eighth stages SRC5to SRC8through the first to fourth clock bar wirings CKBL1to CKBL4. When the number of the clock signals is k and the number of the clock bar signals is k, the first gate driver GDC1includes k number of clock wirings and k number of clock bar wirings.

A first discharge voltage is supplied to the first voltage terminal V1of each of the stages SRC1to SRC8through a first voltage wiring VL1, and a second discharge voltage is supplied to the second voltage terminal V2of each of the stages SRC1to SRC8through a second voltage wiring VL2. For example, the first discharge voltage and the second discharge voltage may be supplied at a level lower than a ground voltage.

For example, the level of the first discharge voltage may be higher than the level of the second discharge voltage. The first discharge voltage may be set to about −10 V to about −5 V, and the second discharge voltage may be set to about −16 V to about −10 V. As another example, the first discharge voltage and the second discharge voltage may have substantially the same voltage level.

The first gate driver GDC1further includes first and second voltage wirings VL1and VL2. The first discharge voltage is supplied to the stages SRC1to SRC8through the first voltage wiring VL1, and the second discharge voltage is supplied to the stages SRC1to SRC8through the second voltage wiring VL2. The number of the discharge voltages supplied to each of the stages SRC1to SRC8is not limited thereto. That is, only one of the first and second discharge voltages may be supplied to each of the stages SRC1to SRC8, or a third discharge voltage may further be supplied in addition to the first and second discharge voltages.

A reset signal may be provided to the reset terminal SP of each of the stages SRC1to SRC8. The reset signal may be the vertical start signal STV. The vertical start signal STV is provided to the reset terminals SP of the stages SRC1to SRC8through a start signal wiring STVL. For example, in one frame period, the vertical start signal STV has a low state in a period other than a period in which the first gate line GL1operates. Accordingly, the stages may be reset in a period in which the first stage SRC1operates. However, the reset period of the stages is not limited thereto. In other words, when a separate reset signal different from the vertical start signal is provided to the reset terminal SP, the reset period of the stages may change.

Referring toFIG.4, the first stage SRC1includes a first output unit111, a second output unit112, a first discharge unit113, a second discharge unit114, a control unit115, a switching unit116, and a reset unit117. Although the circuit configuration of the first stage SRC1among the plurality of stages is illustrated inFIG.4, the other stages also have the same circuit configuration as the first stage SRC1.

The first output unit111is electrically connected to the output terminal OUT and outputs the first gate signal through the output terminal OUT. The second output unit112is electrically connected to the carry terminal CR and outputs a first carry signal through the carry terminal CR. The first gate signal is applied to the first gate line, and the first carry signal is provided to a next stage (i.e., the second stage SRC2). The first output unit111may include a first output transistor T1electrically connected to the clock terminal CK, a first node NQ, and the output terminal OUT. The second output unit112may include a second output transistor T13electrically connected to the clock terminal CK, the first node NQ, and the carry terminal CR.

The control unit115controls operations of the first output unit111and the second output unit112. The control unit115turns on the first output unit111and the second output unit112in response to an input signal provided to the input terminal IN, and turns off the first output unit111and the second output unit112in response to a control signal provided to the control terminal CT. Here, the input signal may be a carry signal provided from a previous stage or the vertical start signal. The control signal may be a carry signal provided from a next stage. The control unit115includes a first control transistor T4and a second control transistor T6. The first control transistor T4is electrically connected to the input terminal IN and the first node NQ, and the second control transistor T6is electrically connected to the control terminal CT, the first node NQ, and the second voltage terminal V2. The second control transistor T6may lower the potential of the first node NQ to the second discharge voltage in response to the control signal.

The first discharge unit113lowers the potential of the output terminal OUT to the first discharge voltage, and the second discharge unit114lowers the potential of the carry terminal CR to the second discharge voltage. The first discharge unit113includes first and second discharge transistors T2and T3. The first discharge transistor T2is electrically connected to the control terminal CT, the output terminal OUT, and the first voltage terminal V1, and the second discharge transistor T3is electrically connected to a second node NA, the output terminal OUT, and the first voltage terminal V1. The second discharge unit114includes a third discharge transistor T12electrically connected to the second node NA, the carry terminal CR, and the second voltage terminal V2.

The switching unit116controls the operations of the first and second discharge units113and114. The switching unit116provides the second node NA with a switching signal for turning on and off the first and second discharge units113and114. The switching unit116includes first to fourth switching transistors T10, T7, T9and T8.

The reset unit117may reset the voltage level of the first node NQ to the second discharge voltage. The reset unit117may include a reset transistor T5electrically connected to the reset terminal SP, the first node NQ, and the second voltage terminal V2. The signal applied to the reset terminal SP may be the vertical start signal.

The circuit configuration of each of the plurality of stages is not limited to the circuit configuration illustrated inFIG.4and may be variously changed.

FIG.5is an enlarged plan view of a first embodiment of the part AA shown inFIG.2A.FIG.6Ais an enlarged view of the portion A1ofFIG.5, andFIG.6Bis a cross-sectional view taken along line I-I′ ofFIG.6A.FIG.6Cis an enlarged plan view of the portion A2ofFIG.5, andFIG.6Dis a cross-sectional view taken along line ofFIG.6C.

Referring toFIGS.2A,5and6A, the first gate driver GDC1includes the plurality of stages and a plurality of signal wirings disposed adjacent to the plurality of stages. The plurality of signal wirings may include the plurality of clock wirings, the plurality of clock bar wirings, the first and second voltage wirings VL1and VL2, and the start signal wiring STVL. The plurality of clock wirings may be the first to fourth clock wirings CKL1to CKL4, and the plurality of clock bar wirings may be the first to fourth clock bar wirings CKBL1to CKBL4.

As shown inFIG.5, the first clock wiring CKL1and the first clock bar wiring CKBL1are disposed adjacent to each other, and the second clock wiring CKL2and the second clock bar wiring CKBL2are disposed adjacent to each other. In addition, the third clock wiring CKL3and the third clock bar wiring CKBL3are disposed adjacent to each other, and the fourth clock wiring CKL4and the fourth clock bar wiring CKBL4are disposed adjacent to each other. The plurality of clock wirings and the plurality of clock bar wirings may be arranged in a first order. Here, the first order refers to an order in which the first clock wiring CKL1, the first clock bar wiring CKBL1, the second clock wiring CKL2, the second clock bar wiring CKBL2, the third clock wiring CKL3, the third clock bar wiring CKBL3, the fourth clock wiring CKL4, and the fourth clock bar wiring CKBL4are sequentially arranged. When k number of clock wirings and k number of clock bar wirings are provided, the first order may be an order in which the k number of clock wirings and the k number of clock bar wirings are alternately arranged.

The first to fourth clock wirings CKL1to CKL4and the first to fourth clock bar wirings CKBL1to CKBL4may be disposed on the same layer and may be formed of the same material. The first to fourth clock wirings CKL1to CKL4and the first to fourth clock bar wirings CKBL1to CKBL4may be formed of a first metal material.

The plurality of signal wirings receives the first gate driving signal from the outside through the first driving pad part PD2_1shown inFIG.2A. The first driving pad part PD2_1may include a plurality of clock pads, a plurality of clock bar pads, first and second voltage pads VP1and VP2shown inFIG.5, and a start signal pad STP shown inFIG.5. For example, referring toFIG.5, the plurality of clock pads may be first to fourth clock pads CKP1to CKP4, and the plurality of clock bar pads may be first to fourth clock bar pads CKBP1to CKBP4.

The first to fourth clock pads CKP1to CKP4are disposed adjacent to each other as shown inFIG.5. The first and second clock pads CKP1and CKP2are adjacent to each other, the second and third clock pads CKP2and CKP3are adjacent to each other, and the third and fourth clock pads CKP3and CKP4are adjacent to each other. The first to fourth clock bar pads CKBP1to CKBP4are disposed adjacent to each other. The first and second clock bar pads CKBP1and CKBP2are adjacent to each other, the second and third clock bar pads CKBP2and CKBP3are adjacent to each other, and the third and fourth clock bar pads CKBP3and CKBP4are adjacent to each other. That is, the plurality of clock pads and the plurality of clock bar pads may be arranged in a second order different from the first order. Here, the second order refers to an order in which the first clock pad CKP1, the second clock pad CKP2, the third clock pad CKP3, the fourth clock pad CKP4, the first clock bar pad CKBP1, the second clock bar pad CKBP2, the third clock bar pad CKBP3, and the fourth clock bar pad CKBP4are sequentially arranged. When k number of clock pads and k number of clock bar pads are provided, the second order may be an order in which the k number of clock pads are arranged and then the k number of clock bar pads are arranged. The k number of clock pads and the k number of clock bar pads may not be alternately arranged.

The first to fourth clock pads CKP1to CKP4are disposed on a first layer, and the first to fourth clock bar pads CKBP1to CKBP4are disposed on a second layer. Here, the first layer may be the first base substrate BS1shown inFIG.6Band the second layer may be a gate insulating layer GIL shown inFIG.6B. The first to fourth clock pads CKP1to CKP4may be formed of the first metal material, and the first to fourth clock bar pads CKBP1to CKBP4may be formed of a second metal material. The first and second metal materials may be the same material or materials different from each other.

Referring toFIGS.2A and5, the first intermediate wiring part CLP1is disposed between the first driving pad part PD2_1and the first gate driver GDC1, and electrically connects the first driving pad part PD2_1to the signal wirings of the first gate driver GDC1. Specifically, as shown inFIGS.5and6A, the first intermediate wiring part CLP1may include a plurality of clock intermediate wirings CL1to CL4, a plurality of clock bar intermediate wirings CBL1to CBL4, first and second voltage intermediate wirings VCL1and VCL2, and a start signal intermediate wiring STCL. Referring toFIG.6A, the plurality of clock intermediate wirings may be first to fourth clock intermediate wirings CL1to CL4, and the plurality of clock bar intermediate wirings may be first to fourth clock bar intermediate wirings CBL1to CBL4.

The first to fourth clock intermediate wirings CL1to CL4electrically connect the first to fourth clock wirings CKL1to CKL4and the first to fourth clock pads CKP1to CKP4. The first to fourth clock intermediate wirings CL1to CL4are disposed on a layer the same as that on which the first to fourth clock wirings CKL1to CKL4are disposed. The first to fourth clock intermediate wirings CL1to CL4may be integrally formed with the first to fourth clock wirings CKL1to CKL4. The first to fourth clock intermediate wirings CL1to CL4and the first to fourth clock wirings CKL1to CKL4may be formed of the first metal material.

The first to fourth clock bar intermediate wirings CBL1to CBL4connect the first to fourth clock bar wirings CKBL1to CKBL4and the first to fourth clock bar pads CKBP1to CKBP4. Referring toFIG.6A, the first clock bar intermediate wiring CBL1includes a first upper wiring CBL1_1and a first lower wiring CBL1_2. The second clock bar intermediate wiring CBL2includes a second upper wiring CBL2_1and a second lower wiring CBL2_2. The third clock bar intermediate wiring CBL3includes a third upper wiring CBL3_1and a third lower wiring CBL3_2. The fourth clock bar intermediate wiring CBL4includes a fourth upper wiring CBL4_1and a fourth lower wiring CBL4_2.

The first to fourth upper wirings CBL1_1to CBL4_1are disposed on a different layer from the layer on which the first to fourth lower wirings CBL1_2to CBL4_2are disposed. The first to fourth upper wirings CBL1_1to CBL4_1may be disposed on the second layer, and the first to fourth lower wirings CBL1_2to CBL4_2may be disposed on the first layer. Here, the first layer may be the first base substrate BS1, and the second layer may be the gate insulating layer GIL.

Referring toFIG.6A, the first to fourth upper wirings CBL1_1to CBL4_1are electrically connected to the first to fourth lower wirings CBL1_2to CBL4_2, respectively, through a first contact part CNT1. The first contact part CNT1may include first to fourth contact holes CNT1_1to CNT1_4. The first upper wiring CBL1_1and the first lower wiring CBL1_2are directly connected through the first contact hole CNT1_1, and the second upper wiring CBL2_1and the second lower wiring CBL2_2are directly connected through the second contact hole CNT1_2. The third upper wiring CBL3_1and the third lower wiring CBL3_2are directly connected through the third contact hole CNT1_3, and the fourth upper wiring CBL4_1and the fourth lower wiring CBL4_2are directly connected through the fourth contact hole CNT1_4.

As illustrated inFIG.6B, the first lower wiring CBL1_2is disposed on the first base substrate BS1and is covered by the gate insulating layer GIL. The first contact hole CNT1_1is provided in the gate insulating layer GIL to expose a portion of the first lower wiring CBL1_2. The first upper wiring CBL1_1is disposed on the gate insulating layer GIL. The first upper wiring CBL1_1partially overlaps the first lower wiring CBL1_2, and is directly connected, in a portion in which the first upper wiring CBL1_1overlaps the first lower wiring CBL1_2, to the first lower wiring CBL1_2through the first contact hole CNT1_1.

Although only the configuration of the first clock bar intermediate wiring CBL1is illustrated inFIG.6B, each of the second to fourth clock bar intermediate wirings CBL2to CBL4has the same configuration as the first clock bar intermediate wiring CBL1, and a repetitive description will be omitted to avoid redundancy.

Referring toFIG.6Aagain, the first upper wiring CBL1_1may cross the second to fourth clock intermediate wirings CL2to CL4. The second upper wiring CBL2_1may cross the third to fourth clock intermediate wirings CL3and CL4, and the third upper wiring CBL3_1may cross the fourth clock intermediate wiring CL4.

Referring toFIGS.6C and6D, the plurality of clock wirings and the plurality of clock bar wirings are electrically connected to the stages SRC1˜SRC8through a plurality of bridge wirings. The plurality of bridge wirings may include first to eighth bridge wirings BL1to BL8. Referring toFIGS.5and6C, the first to fourth bridge wirings BL1to BL4electrically connect the first to fourth clock wirings CKL1to CKL4to the first to fourth stages SRC1to SRC4, respectively. The fifth to eighth bridge wirings BL5to BL8electrically connect the first to fourth clock bar wirings CKBL1to CKBL4to the fifth to eighth stages SRC5to SRC8, respectively.

The first to eighth bridge wirings BL1to BL8are disposed on a different layer from the layer on which the first to fourth clock wirings CKL1to CKL4and the first to fourth clock bar wirings CKBL1to CKBL4are disposed. The first to fourth clock wirings CKL1to CKL4and the first to fourth clock bar wirings CKBL1to CKBL4are disposed on the first layer, and the first to eighth bridge wirings BL1to BL8are disposed on the second layer. The first layer may be the first base substrate BS1and the second layer may be the gate insulating layer GIL.

Referring toFIGS.5and6C, the first clock wiring CKL1is disposed adjacent to the first clock bar wiring CKBL1. The first clock bar wiring CKBL1may be disposed between the first clock wiring CKL1and the second clock wiring CKL2. For example, as shown in FIG.6C, The first clock wiring CKL1is spaced apart from the first stage SRC1at a first distance L1, and the first clock bar wiring CKBL1is spaced apart from the fifth stage SRC5at a second distance L2. The first distance L1is greater than the second distance L2. The second clock wiring CKL2may be spaced apart from the second stage SRC2at a third distance L3. The third distance L3may be smaller than the first and second distances L1and L2. Accordingly, the length L1of the first bridge wiring BL1is longer than the lengths of the second and fifth bridge wirings BL2and BL5, and the length L2of the fifth bridge wiring BL5is longer than the length L3of the second bridge wiring BL2.

As the clock wirings and the clock bar wirings are alternately arranged as described above, the difference in length may decrease between bridge wirings connected to the clock wirings to which the clock signals are applied and bridge wirings connected to the clock bar wirings to which the clock bar signals are applied. In particular, the difference in length is reduced between the first and fifth bridge wirings BL1and BL5respectively connected to the first clock wiring CKL1and the first clock bar wiring CKBL1which are disposed on the outermost side. When the difference in length between the first and fifth bridge wirings BL1and BL5increases, the difference between a first parasitic capacitance formed between the first bridge wiring BL1and the reference electrode and a second parasitic capacitance formed between the fifth bridge wiring BL5and the reference electrode increases. As the difference between the first and second parasitic capacitances decreases, the magnitude of a ripple voltage generated in the reference voltage may be reduced. The difference value between the first and second parasitic capacitances may be reduced to a level of about 8.0070E−14.

As the clock wirings and the clock bar wirings are alternately arranged as described above, the magnitude of the ripple generated in the reference voltage may decrease, and as a result, the phenomenon of a horizontal line smear appearing on the screen of the display panel DP may be reduced or prevented.

Referring toFIG.6C, The first to fourth bridge wirings BL1to BL4are respectively connected to the first to fourth clock wirings CKL1to CKL4through first to fourth contact electrodes CTE1to CTE4. The fifth to eighth bridge wirings BL5to BL8are respectively connected to the first to fourth clock bar wirings CKBL1to CKBL4through fifth to eighth contact electrodes CTBE1to CTBE4.

As illustrated inFIG.6D, the first contact electrode CTE1is disposed on a third layer covering the first bridge wiring BL1. The third layer may be a protective layer PL. A first bridge contact hole B_CNT1exposing the first clock wiring CKL1is provided in the protective layer PL and the gate insulating layer GIL, and a second bridge contact hole B_CNT2exposing the first bridge wiring BL1is provided in the protective layer PL. The first contact electrode CTE1may be connected to the first clock wiring CKL1and the first bridge wiring BL1through the first and second bridge contact holes B_CNT1and B_CNT2, respectively. As such, the first clock wiring CKL1and the first bridge wiring BL1may be electrically connected through the first contact electrode CTE1.

Each of the clock wirings CKL2to CKL4remaining and the clock bar wirings CKBL1to CKBL4may also be electrically connected to a corresponding one of the bridge wirings BL2to BL8in the above-described manner.

FIG.7is an enlarged plan view of a second embodiment of the part AA shown inFIG.2A.FIG.8Ais an enlarged plan view of the portion A3ofFIG.7, andFIG.8Bis a cross-sectional view taken along line ofFIG.8A. However, the same reference numeral is given to an element, among the elements ofFIGS.7to8B, the same as the element illustrated in FIGS.5to6B, and a detailed description thereof will be omitted to avoid redundancy.

Referring toFIGS.7and8A, a first clock bar intermediate wiring CBL1includes a first upper wiring CBL1_1and a first lower wiring CBL1_2. A second clock bar intermediate wiring CBL2includes a second upper wiring CBL2_1and a second lower wiring CBL2_2. A third clock bar intermediate wiring CBL3includes a third upper wiring CBL3_1and a third lower wiring CBL3_2. A fourth clock bar intermediate wiring CBL4includes a fourth upper wiring CBL4_1and a fourth lower wiring CBL4_2.

The first to fourth upper wirings CBL1_1to CBL4_1are disposed on a different layer from a layer on which the first to fourth lower wirings CBL1_2to CBL4_2are disposed. The first to fourth upper wirings CBL1_1to CBL4_1may be disposed on a second layer, and the first to fourth lower wirings CBL1_2to CBL4_2may be disposed on a first layer. Here, the first layer may be a first base substrate BS1and the second layer may be a gate insulating layer GIL.

Referring toFIG.8A, the first to fourth upper wirings CBL1_1to CBL4_1are respectively connected to the first to fourth lower wirings CBL1_2to CBL4_2through a second contact part CNT2. The second contact part CNT2may include first to fourth upper contact holes CNT2_11to CNT2_41and first to fourth lower contact holes CNT2_12to CNT2_42.

The second contact part CNT2further includes first to fourth bridge electrodes BE11to BE14. The first to fourth bridge electrodes BE11to BE14are provided on a third layer. The third layer may be a protective layer PL. The first bridge electrode BE11is connected to the first upper wiring CBL1_1and the first lower wiring CBL1_2through the first upper contact hole CNT2_11and the first lower contact hole CNT2_12, respectively. As illustrated inFIG.8B, the first upper contact hole CNT2_11is provided in the protective layer PL to expose the first upper wiring CBL1_1, and the first lower contact hole CNT2_12is provided in the protective layer PL and the gate insulating layer GIL to expose the first lower wiring CBL1_2. Accordingly, the first upper wiring CBL1_1and the first lower wiring CBL1_2provided on different layers may be electrically connected through the first bridge electrode BE11. The first upper wiring CBL1_1and the first lower wiring CBL1_2may not overlap each other when viewed in a plane.

The second bridge electrode BE12is connected to the second upper wiring CBL2_1and the second lower wiring CBL2_2through the second upper contact hole CNT2_21and the second lower contact hole CNT2_22, respectively. The third bridge electrode BE13is connected to the third upper wiring CBL3_1and the third lower wiring CBL3_2through the third upper contact hole CNT2_31and the third lower contact hole CNT2_32, respectively. The fourth bridge electrode BE14is connected to the fourth upper wiring CBL4_1and the fourth lower wiring CBL4_2through the fourth upper contact hole CNT2_41and the fourth lower contact hole CNT2_42, respectively.

Because the connection structures of the second to fourth bridge electrodes BE12to BE14are similar to the connection structure of the first bridge electrode BE11illustrated inFIG.8B, a description of the connection structures of the second to fourth bridge electrodes BE12to BE14will be omitted to avoid redundancy.

FIG.9is an enlarged plan view of a third embodiment of the part AA shown inFIG.2A.FIG.10Ais an enlarged plan view of an embodiment of the portion A4ofFIG.9, andFIG.10Bis a cross-sectional view taken along line IV-IV′ ofFIG.10A.FIG.10Cis a cross-sectional view taken along line V-V ofFIG.10A. However, the same reference numeral is given to an element, among the elements illustrated inFIGS.9to10C, the same as the element illustrated inFIGS.5to6C, and a detailed description thereof will be omitted to avoid redundancy.

Referring toFIGS.9and10A, a first intermediate wiring part CLP1is disposed between a first driving pad part PD2_1and a first gate driver GDC1, and electrically connects the first driving pad part PD2_1to signal wirings of the first gate driver GDC1. Specifically, as shown inFIG.10A, the first intermediate wiring part CLP1may include a plurality of clock intermediate wirings CL1to CL4, a plurality of clock bar intermediate wirings CBL1to CBL4, first and second voltage intermediate wirings VCL1and VCL2, and a start signal intermediate wiring STCL. The plurality of clock intermediate wirings may be first to fourth clock intermediate wirings CL1to CL4, and the plurality of clock bar intermediate wirings may be first to fourth clock bar intermediate wirings CBL1to CBL4.

The first to fourth clock intermediate wirings CL1to CL4connect first to fourth clock wirings CKL1to CKL4and first to fourth clock pads CKP1to CKP4. Each of the first to fourth clock intermediate wirings CL1to CL4may have a double layer structure. Specifically, referring toFIG.10A, the first clock intermediate wiring CL1includes a first lower conductive layer CL1_1and a first upper conductive layer CL1_2, and the second clock intermediate wiring CL2includes a second lower conductive layer CL2_1and a second upper conductive layer CL2_2. The third clock intermediate wiring CL3includes a third lower conductive layer CL3_1and a third upper conductive layer CL3_2, and the fourth clock intermediate wiring CL4includes a fourth lower conductive layer CL4_1and a fourth upper conductive layer CL4_2.

The first to fourth lower conductive layers CL1_1to CL4_1are disposed on a different layer from a layer on which the first to fourth upper conductive layers CL_2to CL4_2are disposed. The first to fourth lower conductive layers CL1_1to CL4_1are directly connected to the first to fourth clock pads CKP1to CKP4.

The first to fourth clock bar intermediate wirings CBL1to CBL4connect first to fourth clock bar wirings CKBL1to CKBL4and first to fourth clock bar pads CKBP1to CKBP4. Each of the first to fourth clock bar intermediate wirings CBL1to CBL4may have a double layer structure. Specifically, referring toFIG.10A, the first clock bar intermediate wiring CBL1includes a fifth upper conductive layer CBL11and a fifth lower conductive layer CBL12, and the second clock bar intermediate wiring CBL2includes a sixth upper conductive layer CBL21and a sixth lower conductive layer CBL22. The third clock bar intermediate wiring CBL3includes a seventh upper conductive layer CBL31and a seventh lower conductive layer CBL32, and the fourth clock bar intermediate wiring CBL4includes an eighth upper conductive layer CBL41and an eighth lower conductive layer CBL42.

The fifth to eighth lower conductive layers CBL12to CBL42are disposed on a different layer from the layer on which the fifth to eighth upper conductive layers CBL11to CBL41are disposed. The fifth to eighth upper conductive layers CBL11to CBL41are directly connected to the first to fourth clock bar pads CKBP1to CKBP4.

The fifth to seventh upper conductive layers CBL11to CBL31may cross the second to fourth lower conductive layers CL2_1to CL4_1. Specifically, referring toFIG.10A, the fifth upper conductive layer CBL11crosses the second to fourth lower conductive layers CL2_1to CL4_1, the sixth upper conductive layer CBL21crosses the third and fourth lower conductive layers CL3_1and CL4_1, and the seventh upper conductive layer CBL31crosses the fourth lower conductive layer CL4_1.

The first to eighth lower conductive layers CL1_1to CL4_1and CBL12to CBL42are respectively connected to the first to eighth upper conductive layers CL1_2to CL4_2and CBL11to CBL41through a third contact part CNT3. The third contact part CNT3includes first to eighth sub contact parts CNT3_1to CNT3_8.

FIG.10Billustrates the structure of the first sub contact part CNT3_1. The first lower conductive layer CL1_1is provided on a first base substrate BS1, and the first upper conductive layer CL1_2is disposed on a gate insulating layer GIL. The first sub contact part CNT3_1includes a first sub contact hole CNT3_11and a second sub contact hole CNT3_12. The first and second sub contact holes CNT3_11and CNT3_12are provided in the gate insulating layer GIL to expose the first lower conductive layer CL1_1. The first upper conductive layer CL1_2is directly connected to the first lower conductive layer CL1_1through the first and second sub contact holes CNT3_11and CNT3_12.

Because the structures of the third, fifth and seventh sub contact parts CNT3_3, CNT3_5and CNT3_7are similar to the structure of the first sub contact part CNT3_1, a description of the structures of the third, fifth and seventh sub contact parts CNT3_3, CNT3_5and CNT3_7is omitted to avoid redundancy.

FIG.10Cillustrates the structure of the second sub contact part CNT3_2. The fifth lower conductive layer CBL12is provided on the first base substrate BS1, and the fifth upper conductive layer CBL11is disposed on the gate insulating layer GIL. The second sub contact part CNT3_2includes a third sub contact hole CNT3_21and a fourth sub contact hole CNT3_22. The third and fourth sub contact holes CNT3_21and CNT3_22are provided in the gate insulating layer GIL to expose the fifth lower conductive layer CBL12. The fifth upper conductive layer CBL11is directly connected to the fifth lower conductive layer CBL12through the third and fourth sub contact holes CNT3_21and CNT3_22.

Because the structures of the fourth, sixth and eighth sub contact parts CNT3_4, CNT3_6and CNT3_8are similar to the structure of the second sub contact part CNT3_2, a description of the structures of the fourth, sixth and eighth sub contact parts CNT3_4, CNT3_6and CNT3_8is omitted to avoid redundancy.

FIG.11Ais an enlarged plan view of another embodiment of the portion A4ofFIG.9,FIG.11Bis a cross-sectional view taken along line VI-VI′ ofFIG.11A, andFIG.11Cis a cross-sectional view taken along line VII-VII′ ofFIG.11A.

Referring toFIGS.11A to11C, first to eighth lower conductive layers CL1_1to CL4_1and CBL12to CBL42are respectively connected to first to eighth upper conductive layers CL1_2to CL4_2and CBL11to CBL41through a fourth contact part CNT4. The fourth contact part CNT4includes first to eighth sub contact parts CNT4_1to CNT4_8. First to eighth bridge electrodes BE21to BE28are respectively provided to the first to eighth sub contact parts CNT4_1to CNT4_8.

FIG.11Billustrates the structure of the first sub contact part CNT4_1. The first lower conductive layer CL1_1is provided on a first base substrate BS1, and the first upper conductive layer CL1_2is disposed on a gate insulating layer GIL. The first sub contact part CNT4_1includes a first sub contact hole CNT4_11, a second sub contact hole CNT4_12, and the first bridge electrode BE21. The first sub contact hole CNT4_11is provided in a protective layer PL to expose the first upper conductive layer CL1_2. The second sub contact hole CNT4_12is provided in the protective layer PL and the gate insulating layer GIL to expose the first lower conductive layer CL1_1.

The first bridge electrode BE21is connected to the first lower conductive layer CL1_1and the first upper conductive layer CL1_2through the first and second sub contact holes CNT4_11and CNT4_12. Accordingly, the first lower conductive layer CL1_1and the first upper conductive layer CL1_2are electrically connected to each other through the first bridge electrode BE21.

Because the structures of the third, fifth and seventh sub contact parts CNT4_3, CNT4_5and CNT4_7are similar to the structure of the first sub contact part CNT4_1, a description of the structures of the third, fifth and seventh sub contact parts CNT4_3, CNT4_5and CNT4_7is omitted to avoid redundancy.

FIG.11Cillustrates the structure of the second sub contact part CNT4_2. The fifth lower conductive layer CBL12is provided on the first base substrate BS1, and the fifth upper conductive layer CBL11is disposed on the gate insulating layer GIL. The second sub contact part CNT4_2includes a third sub contact hole CNT4_21, a fourth sub contact hole CNT4_22, a fifth sub contact hole CNT4_23, and the second bridge electrode BE22. The third sub contact hole CNT4_21is provided in the gate insulating layer GIL to expose the fifth lower conductive layer CBL12. The fifth upper conductive layer CBL11is directly connected to the fifth lower conductive layer CBL12through the third sub contact hole CNT4_21. The fourth and fifth sub contact holes CNT4_22and CNT4_23are provided in the protective layer PL to expose the fifth upper conductive layer CBL11. The second bridge electrode BE22is directly connected to the fifth upper conductive layer CBL11through the fourth and fifth sub contact holes CNT4_22and CNT4_23. The second bridge electrode BE22may be omitted.

The structures of the fourth, sixth and eighth sub contact parts CNT4_4, CNT4_6and CNT4_8are similar to the structure of the second sub contact part CNT4_2, and thus a description of the structures of the fourth, sixth and eighth sub contact parts CNT4_4, CNT4_6and CNT4_8is omitted to avoid redundancy.

FIG.12is an enlarged plan view of a fourth embodiment of the part AA shown inFIG.2A. However, the same reference numeral is given to an element, among the elements illustrated inFIG.12, the same as the element illustrated inFIG.5, and a detailed description thereof will be omitted to avoid redundancy.

Referring toFIG.12, a first gate driver GDC1further includes a compensation part DCP to compensate for a difference in length between bridge wirings. The compensation part DCP may be disposed in a separation space SA between a fourth clock bar wiring CKBL4and a second voltage wiring VL2. However, the position of the compensation part DCP is not limited thereto. For example, the compensation part DCP may be disposed between a first voltage wiring VL1and stages SRC1to SRC8.

The compensation part DCP includes a plurality of compensation patterns. The plurality of compensation patterns may include first to eighth compensation patterns CP1to CP8respectively connected to first to eighth bridge wirings BL1to BL8.

The length of each of the compensation patterns may be inversely proportional to the length of a corresponding one of the bridge wirings. That is, when the length of a bridge wiring of the bridge wirings is long, the length of a compensation pattern connected thereto may be short, and when the length of a bridge wiring is short, the length of a compensation pattern connected thereto may be long. Accordingly, the sum of the length of the first compensation pattern CP1and the length of the first bridge wiring BL1may be the same as the sum of the length of the second compensation pattern CP2and the length of the second bridge wiring BL2. By respectively connecting the compensation patterns having different lengths to the bridge wirings, the difference in length between the bridge wirings may be compensated.

According to the principles and embodiments of the invention illustrated above, as the clock wirings and the clock bar wirings are alternately arranged, the difference in length may be reduced between the bridge wirings electrically connected to the clock wirings to which the clock signals are applied and the bridge wirings electrically connected to the clock bar wirings to which the clock bar signals are applied.

When the difference in length between the bridge wirings is reduced, the difference between the parasitic capacitances formed between the bridge wirings and the reference electrode decreases, and as a result, the magnitude of a ripple voltage generated in the reference voltage may be reduced.

As the clock wirings and the clock bar wirings are alternately arranged as described above, the magnitude of a ripple voltage generated in the reference voltage may decrease, and as a result, horizontal line smear may be prevented from appearing on the screen of the display panel, thereby improving display quality.