FERROELECTRIC MEMORY DEVICE AND SEMICONDUCTOR DIE

A ferroelectric memory device and a semiconductor die are provided. The ferroelectric memory device includes a gate electrode; a channel layer, overlapped with the gate electrode; source/drain contacts, in contact with separate ends of the channel layer; a ferroelectric layer, lying between the gate electrode and the channel layer; and a first insertion layer, extending in between the ferroelectric layer and the channel layer, and comprising a metal carbonitride or a metal nitride.

BACKGROUND

In recent development of nonvolatile memories, ferroelectric material has been utilized as a storage medium. Information can be stored as a certain polarization state of the ferroelectric material, and such polarization state can be maintained even in absence of a voltage applied across the ferroelectric material. Due to non-volatility and superior data process speed, ferroelectric memory device has attracted considerable attention as a next generation memory device. However, further increase of memory window and endurance is required for improving the ferroelectric memory device.

DETAILED DESCRIPTION

Moreover, source/drain contacts may each refer to a contact to a source terminal or a contact to a drain terminal. Similarly, source/drain terminals may respectively refer to a source electrode or a drain electrode.

FIG.1is a schematic cross-sectional view illustrating a ferroelectric memory device100, according to some embodiments of the present disclosure.

Referring toFIG.1, the ferroelectric memory device100is a ferroelectric field effect transistor (FET). In the ferroelectric memory device100, a ferroelectric layer102lies between a gate electrode104and a channel layer106, and a pair of source/drain contacts108are in contact with separate ends of the channel layer106. The gate electrode104is capacitively coupled to the channel layer106through the ferroelectric layer102. When a gate voltage applied across the ferroelectric layer102exceeds a threshold voltage, electrical current can be established through the channel layer106, and can be sensed at one of the source/drain contacts108. On the other hand, if the gate voltage does not reach the threshold voltage, such current may be absent or have a very low magnitude.

Particularly, the ferroelectric layer102can be programmed with and switched between a first polarization state and a second polarization state having a polarity opposite to a polarity of the first polarization state. By changing the polarization state of the ferroelectric layer102, the threshold voltage can be altered. For instance, when the ferroelectric layer102is programmed with the first polarization state, the ferroelectric memory device100may have a low threshold voltage. On the other hand, when the ferroelectric layer102is programmed with the second polarization state, a high threshold voltage may be resulted. When a gate voltage greater than the low threshold voltage but lower than the high threshold voltage is provided across the ferroelectric layer102, the electrical current may be established through the channel layer106if the ferroelectric layer102is programmed with the first polarization state (which results the low threshold voltage), but may be absent or have a very low magnitude if the ferroelectric layer102is programmed with the second polarization state (which results the high threshold voltage). By sensing the electrical current, whether the ferroelectric layer102is programmed with the first polarization state or the second polarization state can be identified. In this way, information can be stored in the ferroelectric layer102as a specific polarization state. For instance, a logic data “1” can be stored as the first polarization state of the ferroelectric layer102, while a logic data “0” can be stored as the second polarization state of the ferroelectric layer102.

In some embodiments, the gate electrode104is formed of a single conductive material. In other embodiments, the gate electrode104is a multilayer structure including multiple conductive layers formed of a combination of conductive materials. Alternatives of the conductive materials may include titanium nitride (TiN), tantalum nitride (TaN), tungsten and other metallic materials. As similar to the gate electrode104, the source/drain contacts108are respectively formed of one or more of the conductive materials.

The channel layer106is formed of a semiconductor material. In some embodiments, the semiconductor material for forming the channel layer106is an oxide semiconductor material. Examples of the oxide semiconductor material may include zinc oxide, indium gallium zinc oxide (IGZO), indium oxide, indium zinc oxide (InZnO or IZO), indium tin oxide (ITO), indium oxide (e.g., In2O3), gallium oxide (e.g., Ga2O3), indium gallium zinc oxide (InGaZnO or IGZO), zinc oxide (ZnO), aluminum doped zinc oxide (AZO, such as Al2O5Zn2), indium tungsten oxide (IWO), titanium oxide, magnesium oxide or the like. In alternative embodiments, the semiconductor material for forming the channel layer106is a group IV semiconductor material, a group III-V semiconductor material or a group II-VI semiconductor material. The group IV semiconductor material may include Si, Ge, SiGe, Sn, SiC. In addition, the group III-V semiconductor material may include BN, BP, BAs, AlN, AlP, AlAs, AlSb, GaN, GaP, GaAs, GaSb, InN, InP, InAs, InSb or InGaAs, and the group II-VI semiconductor material may include MgO, MgS, MgSe, MgTe, ZnS, ZnSe, ZnTe, CdS, CdSe, CdTe, HgS, HgSe or HgTe.

The ferroelectric layer102is formed of a ferroelectric material. In some embodiments, the ferroelectric material includes hafnium zirconium oxide (HZO). The HZO can be represented as HfxZr(1-x)Oy, where x may be greater than 0 and less than 1, while y may range from 0.1 to 2. In addition, a tetragonal phase, an orthorhombic phase and a cubic phase in the HZO may be collectively greater than 50% of a total volume of the HZO. Further, in these embodiments, the ferroelectric layer102may also include a blocking layer (not shown) lying along a side of the HZO facing toward the channel layer106. The blocking layer may be formed of silicon doped hafnium oxide, and an atomic ration of silicon in the blocking layer may be greater than 10 at %. In some embodiments, a thickness of the HZO ranges from about 0.1 nm to about 100 nm, while a thickness of the blocking layer ranges from about 0.1 nm to about 10 nm. At an interface (of about 2 nm in thickness) between the blocking layer and the HZO, a ratio of oxygen over zirconium may be equal to or greater than 1, and a ratio of oxygen over hafnium may be equal to or greater than 1.

In alternative embodiments, the ferroelectric material for forming the ferroelectric layer102includes hafnium oxide, lead titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), barium titanate, strontium titanate, Sc-doped aluminum nitride (AlScN) or any other suitable ferroelectric material or combinations thereof, and may also include blocking layer(s) at a side of the ferroelectric layer102facing toward the channel layer106.

Undesirably, inter-diffusion may take place at an interface between the ferroelectric layer102and the channel layer106. In addition, defects (such as oxygen vacancies) may be inevitably formed in the ferroelectric layer102. Such inter-diffusion and formation of the defects may result in weaker polarization as well as shorter endurance of the ferroelectric layer102. A memory window (or referred to as a read margin) of the ferroelectric memory device100is defined as a difference between the low threshold voltage and the high threshold voltage of the ferroelectric memory device100, which is resulted from a total remnant polarization of the first and second polarization states of the ferroelectric layer102. If each of the first and second polarization states is lowered in magnitude (i.e., weaker polarization), a smaller total remnant polarization would be resulted. As a consequence, a difference between the low threshold voltage and the high threshold voltage of the ferroelectric memory device100is reduced, thus the ferroelectric memory device100may have a narrower memory window (i.e., a smaller read margin). In addition, the endurance of the ferroelectric layer102is defined as how may write operations does the ferroelectric layer102can maintain its total remnant polarization at a sufficiently high level. A shorter endurance of the ferroelectric layer102indicates that fewer write operations can be performed by the ferroelectric memory device100. In other words, reliability of the ferroelectric memory device100may be compromised when the ferroelectric layer102has a shorter endurance.

An insertion layer110is disposed between the ferroelectric layer102and the channel layer106, to block the inter-diffusion at the interface between the ferroelectric layer102and the channel layer106, and to passivate dangling bonds at the possible defects in the ferroelectric layer102. The insertion layer110may be electrically conductive. In some embodiments, a metal carbonitride such as WCN, TaCN, CrCN, TiCN or TaCN is used for forming the insertion layer110. In addition, a thermal atomic layer deposition (ALD) process may be performed for forming the insertion layer110of the metal carbonitride. Elements110E in the insertion layer110may diffuse into the ferroelectric layer102. A metal content of the insertion layer110may be functioned as a barrier for blocking the inter-diffusion across the interface between the ferroelectric layer102and the channel layer106, while nitrogen and carbon diffused into the ferroelectric layer102from the insertion layer110may passivate dangling bonds at the possible defects in the ferroelectric layer102. Therefore, by further disposing the insertion layer110, memory window and reliability of the ferroelectric memory device100can be effectively improved.

In alternative embodiments, the insertion layer110is formed of metal nitride by using a thermal ALD process. As similar to the effect of the metal carbonitride, the metal content in the metal nitride may block the inter-diffusion across the interface between the ferroelectric layer102and the channel layer106, and the nitrogen of the metal nitride may diffuse into the ferroelectric layer102and passive dangling bonds at the possible defects in the ferroelectric layer102. Alternatives of the metal nitride may include tungsten nitride (WN), titanium nitride (TiN) and tantalum nitride (TaN).

As indicated inFIG.1, a surface region of the ferroelectric layer102that is in contact with the insertion layer110is doped with the elements110E of the insertion layer110. The elements110E diffusing into the ferroelectric layer102may be rich in the surface region, and may gradually decrease away from the surface region. Concentration profile of the elements110E in the ferroelectric layer102may vary, according to process temperature of the thermal ALD process and/or material selection of the insertion layer110and the ferroelectric layer102. The present disclosure is not limited to the concentration profile of the elements110E in the ferroelectric layer102.

FIG.2Ais a plot diagram illustrating hysteresis loops200,202of the ferroelectric layer102with and without being covered by the insertion layer110. A vertical axis inFIG.2Ashows magnitude of polarization in the ferroelectric layer102, while a horizontal axis inFIG.2Ashows voltage applied across the ferroelectric layer102.

The hysteresis loop200indicates polarization of the ferroelectric layer102without being covered by the insertion layer110, with respect to varying voltage applied across the ferroelectric layer102. Intersections of the hysteresis loop200and the vertical axis (i.e., zero voltage across the ferroelectric layer102) define a remnant polarization Pr1 and a remnant polarization Pr2 in the ferroelectric layer102. The remnant polarization Pr1 and the remnant polarization Pr2 having opposite polarity are each an amount of polarization remained in the ferroelectric layer102while the voltage applied across the ferroelectric layer102is removed, and represent the first and second polarization states that can be programmed to the ferroelectric layer102. A summation (in absolute values) of the remnant polarization Pr1 and the remnant polarization Pr2 relates to the memory window (i.e., read margin) of the ferroelectric memory device100.

On the other hand, the hysteresis loop202indicates polarization of the ferroelectric layer102being covered by the insertion layer110, with respect to varying voltage applied across the ferroelectric layer102. In a similar way, intersections of the hysteresis loop202and the vertical axis define a remnant polarization Pr1′ and a remnant polarization Pr2′ in the ferroelectric layer102, which represents the first and second polarization states can be programmed to the ferroelectric layer102. As shown inFIG.2A, a summation (in absolute value) of the remnant polarization Pr1′ and the remnant polarization Pr2′ is much greater than a summation of the remnant polarization Pr1 and the remnant polarization Pr2. As the summation (in absolute values) of the remnant polarizations with opposite polarity indicates the memory window of the ferroelectric memory device100, it can be verified that the memory window of the ferroelectric memory device100can be effectively enlarged by further disposing the insertion layer110between the ferroelectric layer102and the channel layer106.

FIG.2Bis a plot diagram showing endurances of the ferroelectric layer102with and without being covered by the insertion layer110. A vertical axis inFIG.2Bshows a total remnant polarization 2Pr defined as a difference between the remnant polarizations with opposite polarity in the ferroelectric layer102, whereas a horizontal axis inFIG.2Bshows numbers of operation cycles performed on the ferroelectric layer102.

A data curve204indicates variation of the total remnant polarization 2Pr in the ferroelectric layer102without being covered by the insertion layer110, with respect to increasing operation cycles. As shown by the data curve204, the total remnant polarization 2Pr in the ferroelectric layer102without being covered by the insertion layer110quickly degrades over operation cycles, and is close to zero after 106times of operation cycles.

On the other hand, a data curve206indicates variation of the total remnant polarization 2Pr in the ferroelectric layer102being covered by the insertion layer110, with respect to increasing operation cycles. As shown by the data curves204,206, the ferroelectric layer102being covered by the insertion layer110has a greater total remnant polarization 2Pr, as compared to the ferroelectric layer102without being covered by the insertion layer110. Further, the total remnant polarization 2Pr in the ferroelectric layer110being covered by the insertion layer110degrades very slowly. At 106times of operation cycles, the total remnant polarization 2Pr in the ferroelectric layer110being covered by the insertion layer110is just slightly lower than its maximum value. Therefore, it can be verified that the endurance of the ferroelectric memory device100can be effectively improved as well by further disposing the insertion layer110between the ferroelectric layer102and the channel layer106.

Referring toFIG.1again, the insertion layer110is provided as an ultra-thin layer. In some embodiments, a thickness of the insertion layer110ranges from 1 Å to 100 Å. If the thickness of the insertion layer110is greater than the maximum value, much less or no improvement on total remnant polarization and endurance of the ferroelectric layer102might be resulted. Further, since the insertion layer110may be electrically conductive, switching behavior of the channel layer106underlined with the insertion layer110might be disadvantageously affected when the thickness of the insertion layer110is greater than the maximum value. As described above, elements in the insertion layer110may out diffuse into the ferroelectric layer102. The thickness of the insertion layer110may be evaluated by a number of deposition cycles in the thermal ALD process for forming the insertion layer110. For instance, around 4 deposition cycles in the thermal ALD process are used for forming the insertion layer110to a thickness of 1 Å to 10 Å.

According to some embodiments, an additional insertion layer112is disposed between the ferroelectric layer102and the gate electrode104. As similar to the insertion layer110, the insertion layer112is capable of blocking inter-diffusion across an interface between the ferroelectric layer102and the gate electrode104, and passivating dangling bonds at possible defects in the ferroelectric layer102. In addition, the insertion layer112may be electrically conductive as well. A metal carbonitride or a metal nitride may be used for forming the insertion layer112. Alternatives of the metal carbonitride may include WCN, TaCN, CrCN, TiCN and TaCN, whereas examples of the metal nitride may include WN, TiN and TaN. In some embodiments, the insertion layers110,112are formed of the same metal carbonitride or metal nitride. In alternative embodiments, the insertion layer112is formed of a metal carbonitride or metal nitride different from a metal carbonitride or metal nitride of the insertion layer112. A method for forming the insertion layer112may include a thermal ALD process.

During the thermal ALD process, elements112E of the insertion layer112may diffuse into the ferroelectric layer102. As indicated inFIG.1, a surface region of the ferroelectric layer102that is in contact with the insertion layer112is doped with the elements112E of the insertion layer112. In addition, the elements112E diffusing into the ferroelectric layer102may be rich in the surface region of the ferroelectric layer102, and may gradually decrease away from this surface region. Concentration profile of the elements112E in the ferroelectric layer102may vary, according to process temperature of the thermal ALD process and/or material selection of the insertion layer112and the ferroelectric layer102. The present disclosure is not limited to the concentration profile of the elements112E in the ferroelectric layer102.

As a difference from the insertion layer110, a thickness of the insertion layer112may be much greater than the thickness of the insertion layer110. Further, in some embodiments, the insertion layer112is further functioned as a work function layer for tuning the threshold voltage of the ferroelectric memory device100. In these embodiments, work function of the insertion layer112is different from work function of the gate electrode104.

In some embodiments, the ferroelectric memory device100is formed with a bottom-gate top-contact configuration. In these embodiments, the ferroelectric layer102extends over the gate electrode104, and the channel layer106is disposed on top of the ferroelectric layer102. In addition, the source/drain contacts108are separately formed on the channel layer106. Optionally, the gate electrode104is laterally recessed with respect to an overlying stacking structure including the insertion layer112, the ferroelectric layer102, the insertion layer110and the channel layer106. Moreover, a plurality of the ferroelectric memory device100may be embedded and arranged as an array in a back-end-of-line (BEOL) structure of a semiconductor die. Although not shown, the ferroelectric memory device100may be buried in a stack of dielectric layers (not shown), along with local and global interconnections of the semiconductor die.

As will be further described, ferroelectric memory devices according to other embodiments may be formed with other configurations

FIG.3is a schematic cross-sectional view illustrating a ferroelectric memory device300, according to some embodiments of the present disclosure.

The ferroelectric memory device300is similar to the ferroelectric memory device100as described with reference toFIG.1A, but is formed with a top-gate top-contact configuration. In the ferroelectric memory device300, a gate structure including the ferroelectric layer102and the gate electrode104lying above the ferroelectric layer102is disposed on the channel layer106. In addition, the source/drain contacts108are disposed on the channel layer106at opposite sides of a gate structure. As similar to the ferroelectric memory device100as shown inFIG.1, the ferroelectric memory device300includes the insertion layer110sandwiched between the ferroelectric layer102and the channel layer106, and optionally includes the insertion layer112lying between the ferroelectric layer102and the gate electrode104.

In some embodiments, the channel layer106in the ferroelectric memory device300is a semiconductor substrate (e.g., a semiconductor wafer or a semiconductor-on-insulator (SOI) wafer). In these embodiments, the ferroelectric memory device300is a front-end ferroelectric FET. Further, a plurality of the ferroelectric memory devices300may be arranged as an array in a front-end-of-line (FEOL) structure of a semiconductor die, along with other complementary-metal-oxide-semiconductor (CMOS) transistors.

In alternative embodiments, the channel layer106in the ferroelectric memory device300is a semiconductor layer elevated from a semiconductor substrate. In these alternative embodiments, the ferroelectric memory device300is a back-end ferroelectric FET, and a plurality of the ferroelectric memory devices300may be embedded and arranged as an array in a back-end-of-line (BEOL) structure of a semiconductor die. Although not shown, the ferroelectric memory devices300may be buried in a stack of dielectric layers (not shown), along with local and global interconnections of the semiconductor die.

FIG.4is a schematic cross-sectional view illustrating a ferroelectric memory device400, according to some embodiments of the present disclosure.

The ferroelectric memory device400is similar to the ferroelectric memory device100as described with reference toFIG.1, but is formed with a different configuration. In the ferroelectric memory device400, the source/drain contacts108lie at different heights, and the channel layer106as well as the ferroelectric layer102extend from one of these heights to the other. Further, the gate electrode104may extend along a top surface and a sidewall of the ferroelectric layer102. As similar to the ferroelectric memory device100, the ferroelectric memory device400includes the insertion layer110extending between the ferroelectric layer102and the channel layer106, and optionally includes the channel layer112lying between the ferroelectric layer102and the gate electrode104.

As shown inFIG.4, in some embodiments, one of the source/drain contacts108is disposed on a substrate402, and the other source/drain contact108is disposed on a dielectric pattern404formed on the substrate402. In these embodiments, the channel layer106may extend from a top surface of one of the source/drain contacts108to a top surface of the other source/drain contact108, through a sidewall of the dielectric pattern404. In addition, the insertion layer110, the ferroelectric layer102and the insertion layers112(if any) may conformally cover the channel layer106bridging the source/drain contacts108. Further, the gate electrode104may cover a top corner of the ferroelectric layer102, and is separated from the source/drain contacts108. In those embodiments where the ferroelectric memory device400includes the insertion layer112, the gate electrode104is in contact with the ferroelectric layer102through the insertion layer112.

In some embodiments, the substrate402is a semiconductor substrate (e.g., a semiconductor wafer or a SOI wafer). In these embodiments, a plurality of the ferroelectric memory devices400may be arranged as an array in a front-end-of-line (FEOL) structure of a semiconductor die, along with complementary-metal-oxide-semiconductor (CMOS) transistors.

In alternative embodiments, the substrate402is a dielectric layer elevated from the semiconductor substrate. In these alternative embodiments, the ferroelectric memory device400is a back-end ferroelectric FET, and a plurality of the ferroelectric memory devices400may be embedded and arranged as an array in a back-end-of-line (BEOL) structure of a semiconductor die. Although not shown, the ferroelectric memory devices400may be buried in a stack of dielectric layers (not shown), along with local and global interconnections of the semiconductor die.

FIG.5is a schematic cross-sectional view illustrating an array of ferroelectric memory devices500, according to some embodiments of the present disclosure.

Each of the ferroelectric memory devices500is similar to the ferroelectric memory device100as described with reference toFIG.1, but is formed with a different configuration. In addition, the ferroelectric memory devices500are arranged as a three-dimensional memory array.

As shown inFIG.5, the three-dimensional memory array includes stacks of the ferroelectric memory devices500formed on a substrate502. In some embodiments, the substrate502is an insulating layer elevated from a semiconductor substrate (not shown), such as a semiconductor wafer or a SOI wafer. In these embodiments, active devices (e.g., transistors) and interconnections for routing these active devices (both not shown) may be formed on the semiconductor wafer (or the SOI wafer) and lying below the substrate502. In alternative embodiments, the substrate502is the semiconductor wafer or the SOI wafer.

The stacks of ferroelectric memory devices500are arranged in columns respectively extending along a direction Y (also referred as a column direction). These columns are deployed along a direction X (also referred as a row direction) intersected with the direction Y. In order to clearly illustrate elements in each stack of the ferroelectric memory devices500, a single stack of the ferroelectric memory devices500in one of these columns are particularly depicted as solely standing on the substrate502. Although not shown, there are actually other stacks of the ferroelectric memory devices500in this column. As shown inFIG.5, each stack of the ferroelectric memory devices500contain a segment of a stacking structure504formed on the substrate502. A plurality of the stacking structures504extend along the column direction (i.e., the direction Y), and are laterally spaced apart from one another along the row direction (i.e., the direction X). The stacks of the ferroelectric memory devices500in the same column share the same stacking structure504, and each stacking structure504may be shared by the stacks of the ferroelectric memory devices500in adjacent columns.

A plurality of the gate electrodes104and multiple isolation layers506are each formed in a line shape and alternately stacked along a vertical direction Z in each stacking structure504. A topmost layer in the stacking structure504may be one of the gate electrodes104or one of the isolation layers506. Similarly, a bottommost layer in the stacking structure504may be one of the gate electrodes104or one of the isolation layers506. Further, those skilled in the art may adjust the amount of the gate electrodes104and the isolation layers506in each stacking structure504, the present disclosure is not limited thereto.

A plurality of the ferroelectric layers102span along sidewalls of the stacking structures504. In some embodiments, each ferroelectric layer102covers opposing sidewalls of adjacent stacking structures504, and extends along a portion of the substrate502between these adjacent stacking structures504. In other words, a sidewall and a bottom surface of each trench between adjacent stacking structures504may be covered by one of the ferroelectric layers102. In alternative embodiments, the ferroelectric layers102respectively cover a sidewall of one of the stacking structures504, and are separated from one another.

A plurality of the channel layers106cover surfaces of the ferroelectric layers102facing toward trenches between the stacking structures504. In some embodiments, opposite sidewalls of each stacking structure504are respectively covered by laterally separated ones of the channel layers106, such that each channel layer106may be exclusively shared by a stack of the ferroelectric memory devices500. In these embodiments, cross-talk between adjacent stacks of the ferroelectric memory devices500arranged along the direction Y may be prevented. In addition, in some embodiments, the channel layers106at opposing sidewalls of adjacent stacking structures504are laterally spaced apart. In alternative embodiments, the channel layers106covering opposing sidewalls of each trench between adjacent stacking structures504are connected with each other by a bottom portions extending along a portion of the substrate502between the adjacent stacking structures504.

A plurality of the insertion layers110are respectively sandwiched between each of the channel layers106and the covered ferroelectric layer102. In some embodiments, the insertion layers110respectively have a pattern/shape substantially identical with a pattern/shape of each ferroelectric layer102. In these embodiments, the ferroelectric layers102may be entirely overlapped with the insertion layers110. In alternative embodiments, the insertion layers110respectively have a pattern/shape substantially identical with a pattern/shape of each channel layer106. In these alternative embodiments, the insertion layers110may be entirely overlapped with the channel layers106.

In some embodiments, a plurality of insertion layers112are respectively sandwiched between each ferroelectric layer102and the covered stacking structure(s)504. In some embodiments, the insertion layers112respectively have a pattern/shape substantially identical with a pattern/shape of each ferroelectric layer102. In these embodiments, the ferroelectric layers102may be entirely overlapped with the insertion layers112.

Pairs of the source/drain contacts108(respectively formed as conductive pillars) stand on the portions of the substrate502between the stacking structures504. The source/drain contacts108in each pair are separately in lateral contact with the channel layer(s)106covering opposing sidewalls of adjacent stacking structures504. Further, adjacent pairs of the source/drain contacts108arranged along the direction Y are laterally separated as well. In some embodiments, isolation structures508are respectively filled between the source/drain contacts108in the same pair. In addition, in some embodiments, isolation pillars510respectively stand between adjacent pairs of the source/drain contacts108in the same trench. In these embodiments, channel layers106disposed along a sidewall of one of the stacking structures504are separated from one another by the isolation pillars510standing aside this stacking structure504. Moreover, in some embodiments, pairs of the source/drain contacts108at a side of a stacking structure504are offset along the direction Y from pairs of the source/drain contacts108at the other side of the stacking structure504. In these embodiments, the stacks of ferroelectric memory devices500may be referred as being arranged in a staggered configuration.

A segment of one of the gate electrodes104and portions of the insertion layers112(if any), the ferroelectric layer102, the insertion layer110, the channel layer106and a pair of source/drain contacts108in lateral contact with the segment of the gate electrode104collectively form one of the ferroelectric memory devices500, which may be a ferroelectric FET. The ferroelectric memory devices500in the same stack may share the same ferroelectric layer102, the same channel layer106, and the same pair of the source/drain contacts108, while being controlled by different gate electrodes104in the same stacking structure504. Adjacent stacks of the ferroelectric memory devices500at opposite sides of a pair of the source/drain contacts108may share this pair of the source/drain contacts108, while having different channel layers106and being controlled by the gate electrodes104in adjacent ones of the stacking structures504. Adjacent stacks of the ferroelectric memory devices500at opposite sides of the same stacking structure504may share the gate electrodes104in this stacking structure504, while having different ferroelectric layers102, different channel layers106and different pairs of the source/drain contacts108. In addition, adjacent stacks of the ferroelectric memory devices500in the same column may share the same ferroelectric layer102and the gate electrodes104in the same stacking structure504, while having different channel layers106and different pairs of the source/drain contacts108.

In some embodiments, end portions of the stacking structures504are shaped into staircase structures SC, and the gate electrodes104extend to steps of the staircase structures SC. An end portion of each gate electrode104in a stacking structure504(except for the topmost gate electrode104) laterally protrudes with respect to an end portion of an overlying gate electrode104in the same stacking structure504along the column direction (i.e., the direction Y), to form a step of the staircase structure SC. In this way, each of the gate electrodes104may have an end portion not covered by others of the gate electrodes104, thus can be independently out-routed. In some embodiments, an end portion of each isolation layer506in a stacking structure504is aligned with an end portion of an overlying gate electrode104, and defines a bottom portion of a step. In these embodiments, each step of a staircase structure SC consists of end portions of one of the gate electrodes104and an underlying isolation layer506. It should be noted that,FIG.5merely shows the staircase structures SC at a single side of the memory array. However, opposite sides of each stacking structure504may be respectively shaped into a staircase structure SC.

Up to here, the ferroelectric memory devices as ferroelectric FETs with different configurations have been described. Variations to these ferroelectric memory devices will be discussed in further embodiments.

FIG.6Ais a schematic cross-sectional view illustrating a ferroelectric memory device600a, according to some embodiments of the present disclosure.

The ferroelectric memory device600ais similar to the ferroelectric memory device100described with reference toFIG.1, except that the ferroelectric memory device600afurther includes a dielectric layer602lying between the insertion layer110and the channel layer106, and a metal-ferroelectric-insulator-semiconductor (MFIS) type ferroelectric FET is resulted. By further disposing the dielectric layer602, a leakage path across an interface between the channel layer106and the ferroelectric layer102may be cut off. Therefore, the ferroelectric memory device600amay have improved switching behavior and/or data retention ability. A material of the dielectric layer602may be selected to increase conduction band offset at an interface between the channel layer106and the dielectric layer602. Alternatives of the material for forming the dielectric layer602may include silicon oxide, aluminum oxide or any other large bandgap dielectric material.

As similar to the variation described with reference toFIG.6A, such dielectric layer602may further interpose between the channel layer106and the insertion layer110in each of the ferroelectric memory device300as shown inFIG.3, the ferroelectric memory device400as shown inFIG.4and each ferroelectric memory device500as shown inFIG.5.

FIG.6Bis a schematic cross-sectional view illustrating a ferroelectric memory device600b, according to some embodiments of the present disclosure.

The ferroelectric memory device600bis similar to the ferroelectric memory device600adescribed with reference toFIG.6A, except that the ferroelectric memory device600bfurther includes a floating gate604lying between the insertion layer110and the dielectric layer602, and a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) type ferroelectric FET is resulted. The floating gate604can act as an equipotential layer, such that an effect area of the ferroelectric layer102(a portion of the ferroelectric layer102that is subjected to polarization) is enlarged, so as to saturate polarization of the ferroelectric layer102at a rather low programming voltage. The floating gate604is formed of a conductive material. Alternatives of the conductive material may include titanium nitride (TiN), tantalum nitride (TaN), tungsten and other metallic materials.

As similar to the variation described with reference toFIG.6B, such dielectric layer602and the floating gate604may further interpose between the channel layer106and the insertion layer110in each of the ferroelectric memory device300as shown inFIG.3, the ferroelectric memory device400as shown inFIG.4and each ferroelectric memory device500as shown inFIG.5.

In addition to ferroelectric FETs of different types and configurations, a ferroelectric memory device may further include a ferroelectric capacitor.

FIG.7Ais a schematic cross-sectional view illustrating a ferroelectric memory device700, according to some embodiments of the present disclosure.

Referring toFIG.7A, the ferroelectric memory device700is a ferroelectric capacitor that includes a ferroelectric layer702and a pair of electrodes704lying at opposite sides of the ferroelectric layer702. The ferroelectric layer702is substantially identical with the ferroelectric layer102described with reference toFIG.1, and each of the electrodes704is substantially identical with the gate electrode104described with reference toFIG.1. The ferroelectric layer702can be programmed with and switched between the first and second polarization states with opposite polarity, by controlling a voltage difference between the electrodes704. Binary logic data can be stored in the ferroelectric layer702as the first and second polarization states, and can remain in the ferroelectric layer702even at absence of the voltage applied across the ferroelectric layer702. To read the data stored in the ferroelectric layer702, a read voltage may be provided to one of the electrodes704, and a reference voltage (e.g., a ground voltage) is provided to the other electrode704. If a polarity of the polarization state stored in the ferroelectric layer702is opposite to a polarity of the read voltage, the ferroelectric layer702is switched to the other polarization state, and a current pulse as a result of the switching may be sensed at the electrode704coupled to the reference voltage. On the other hand, if the polarity of the polarization state programmed in the ferroelectric layer702is aligned with the polarity of the read voltage, no polarization switching would occur, thus such current pulse at the electrode704coupled to the reference voltage may be absent. As the read operation is destructive, a restore process for writing the data back to the ferroelectric layer102may be performed after the read operation.

As similar to the ferroelectric memory devices100,300,400,500,600a,600bdescribed with reference toFIG.1,FIG.3,FIG.4,FIG.5,FIG.6AandFIG.6B, an insertion layer706is further disposed between the ferroelectric layer702and one of the electrodes704, for blocking inter-diffusion between the ferroelectric layer702and this electrode704, and/or for passivating dangling bonds at possible defects in the ferroelectric layer702. Similarly, another insertion layer708may be disposed between the ferroelectric layer702and the other electrode704. The insertion layers706,708may be each identical with the insertion layers110,112in terms of material selection and formation method. That is, the insertion layers706,708may be each formed of a metal carbonitride (e.g., WCN, TaCN, CrCN, TiCN or TaCN) or a metal nitride (e.g., WN, TiN or TaN), and each formed by using a thermal ALD process. Some elements706E of the insertion layer706as well as some elements708E of the insertion layer708may diffuse into the ferroelectric layer702as a result of thermal energy provided during formation. As a result, surface regions of the ferroelectric layer702in contact with the insertion layers706,708are doped with the elements706E,708E of the insertion layers706,708. Metal content of the insertion layers706,708may block the inter-diffusion between the ferroelectric layer702and the electrodes704, whereas nitrogen and carbon of the insertion layers706,708may passivate the dangling bonds at the possible defects in the ferroelectric layer702.

As a difference from the insertion layers110,112described with reference toFIG.1, each of the insertion layers706,708is in contact with an electrode layer, rather than a channel layer. According to some embodiments, the insertion layers706,708are respectively formed to a thickness ranging from 1 Å to 100 Å. Further, the insertion layers706,708may have substantially identical with thickness. Alternatively, the thickness of the insertion layer706is less or greater than the thickness of the insertion layer708.

Unlike a ferroelectric FET (e.g., the ferroelectric memory devices100,300,400,500,600a,600bas shown inFIG.1,FIG.3,FIG.4,FIG.5,FIG.6AandFIG.6B), the ferroelectric memory device700as a ferroelectric capacitor may require a selector for controlling access of the ferroelectric memory device700.

FIG.7Bis a schematic diagram illustrating a memory cell MC in a memory array, according to some embodiments of the present disclosure.

In addition to the ferroelectric memory device700as described with reference toFIG.7A, the memory cell MC includes a selector710for controlling access of the ferroelectric memory device700. The selector710is a FET, which can be formed in a FEOL structure or a BEOL structure of a semiconductor die. A source/drain terminal of the selector710may be coupled to one of the electrodes704in the ferroelectric memory device700, and the other source/drain terminal of the selector710may be coupled to a bit line BL. Further, a gate terminal of the selector710may be coupled to a word line WL, and the other electrode704of the ferroelectric memory device700may be coupled to a plate line PL. In this way, switching of a conduction channel between the source/drain terminals of the selector710can be controlled by the word line WL. When the word line WL is asserted, the conduction channel is established, and a voltage applied across the ferroelectric memory device700can be controlled by the bit line BL and the plate line PL. Otherwise, the conduction channel is cut off, and the ferroelectric memory device700becomes inaccessible.

The memory array may include a plurality of the memory cells MC arranged along rows and columns. In some embodiments, a row of the memory cells MC share the same word line WL and the same plate line PL, while a column of the memory cells MC share the same bit line BL.

Up to here, various ferroelectric memory devices according to plenty of embodiments have been described. Some of these ferroelectric memory devices are ferroelectric FETs, and can be respectively employed as a memory cell of a memory array. Another one of these ferroelectric memory devices is a ferroelectric capacitor, and can be functioned as a storage unit in a memory cell of a memory array. Each of these memory arrays can be formed in a stand-alone memory or an embedded memory.

FIG.8is a schematic cross-sectional view illustrating a semiconductor die800including an embedded memory EM, according to some embodiments of the present disclosure.

Referring toFIG.8, the semiconductor die800has a front-end-of-line (FEOL) structure800F built on a semiconductor substrate802, and includes a back-end-of-line (BEOL) structure800B disposed on the FEOL structure800F. The embedded memory EM is integrated in the BEOL structure800B. The afore-described ferroelectric memory devices as ferroelectric FETs can be respectively functioned as a memory cell, and a plurality of the memory cells may be arranged as an array in the embedded memory EM. Alternatively, the afore-described ferroelectric memory device as a ferroelectric capacitor may be functioned as a storage unit in a memory cell, and a plurality of the memory cells may be arranged as an array in the embedded memory EM.

The FEOL structure800F may include transistors (or referred to as front-end transistors)804. Each of the transistors804may include a gate structure806and a pair of source/drain structures808at opposite sides of the gate structure806. Further, adjacent transistors804may be isolated from one another by an isolation structure810formed in the semiconductor substrate802. In some embodiments, the transistors804are planar type transistors. In these embodiments, the gate structures806are formed on planar portions of the semiconductor substrate802, and the source/drain structures808may be formed in the semiconductor substrate802. In alternative embodiments, the transistors804are fin type transistors or gate-all-around (GAA) transistors. In these alternative embodiments, the semiconductor substrate802may be shaped to form fin structures at its top surface, or stacks of channel structures (e.g., stacks of semiconductor nanosheets) may be formed on the semiconductor substrate802. Each fin structure/channel structure may extend between a pair of the source/drain structures808. In addition, the gate structures806may intersect and cover the fin structures or the stacks of channel structures. Moreover, the FEOL structure800F may further include a dielectric layer812and contact structures814formed in the dielectric layer812. The contact structures814penetrate through the dielectric layer812, to establish electrical contact with the source/drain structures808.

The BEOL structure800B may include a stack of interlayer dielectric layers816. For conciseness, only one of the interlayer dielectric layers816is labeled. The embedded memory EM is formed in successive ones of the interlayer dielectric layers816. Further, the BEOL structure800B also includes conductive elements818spreading in the stack of interlayer dielectric layers816, for interconnecting the transistors804, and for out-routing the embedded memory EM.

The conductive elements818may be distributed below, around and over the embedded memory EM, and may include conductive patterns820and conductive vias822. Each conductive pattern820laterally extends in one of the interlayer dielectric layers816. In addition, each conductive via822vertically extends through one or more of the interlayer dielectric layers816to establish electrical contact with one or more of the conductive patterns820, or to establish electrical contact with one of the signal lines in the embedded memory EM. The embedded memory array EM may be routed to some of the transistors804in the FEOL structure800F through some of the conductive elements818, and can be driven by a driving circuit including these transistors804. In those embodiments where the embedded memory array EM including a plurality of the ferroelectric memory devices as ferroelectric capacitors, some of the transistors804may be used as selectors coupled to these ferroelectric memory devices. Alternatively, the selectors may be provided by back-end transistors also integrated in the embedded memory EM.

Although not shown, passivation layer(s) and electrical connectors as die inputs/outputs (I/Os) may be formed on the BEOL structure800B.

As above, ferroelectric memory devices according to various embodiments are provided. Each of the ferroelectric memory devices includes a ferroelectric layer, and includes insertion layer(s) lying at a single side or two opposite sides of the ferroelectric layer. Metal content in the insertion layer(s) may block inter-diffusion between the ferroelectric layer and adjacent material layer(s). Further, some elements diffused into the ferroelectric layer from the insertion layer(s) may passivate dangling bonds at possible defects in the ferroelectric layer. As the inter-diffusion between the ferroelectric layer and the adjacent material layer(s) can be prevented and the possible defects in the ferroelectric layer can be passivated, total remnant polarization (2Pr) in the ferroelectric layer can be increased, and endurance of the ferroelectric layer can be effectively improved. Therefore, by further including the insertion layers, the ferroelectric memory devices can be operated with greater memory window and better reliability.

In an aspect of the present disclosure, a ferroelectric memory device is provided. The ferroelectric memory device comprises: a gate electrode; a channel layer, overlapped with the gate electrode; source/drain contacts, in contact with separate ends of the channel layer; a ferroelectric layer, lying between the gate electrode and the channel layer; and a first insertion layer, extending in between the ferroelectric layer and the channel layer, and comprising a metal carbonitride or a metal nitride.

In another aspect of the present disclosure, a ferroelectric memory device is provided. The ferroelectric memory device comprises: a first electrode and a second electrode, overlapped with each other; a ferroelectric layer, sandwiched between the first and second electrodes; a first insertion layer, lying between the ferroelectric layer and the first electrode; and a second insertion layer, lying between the ferroelectric layer and the second electrode, wherein each of the first and second insertion layers comprises a metal carbonitride.

In yet another aspect of the present disclosure, a semiconductor die is provided. The semiconductor die comprises: a semiconductor substrate; front-end transistors, built on a surface of the semiconductor substrate; a stack of dielectric layers, covering the transistors and the semiconductor substrate; and ferroelectric memory devices, formed in the stack of dielectric layers and elevated from the semiconductor substrate, and respectively comprising a ferroelectric layer and an insertion layer separating the ferroelectric layer from an adjacent channel layer or an electrode, wherein the insertion layer comprises metal carbonitride or metal nitride, and a surface region of the ferroelectric layer in contact with the insertion layer is doped with elements of the insertion layer.