Scan chain in an integrated circuit

In an embodiment, a scannable storage element includes an input circuit for providing a first signal at first node based on a data input and a scan input, where the scan input is of pull-up logic in functional mode. The input circuit includes a first pull-up path comprising a switch receiving data input and a switch receiving scan enable input, and second pull-up path comprising a switch receiving scan input, first pull-down path comprising a switch receiving the scan enable input and a switch receiving the scan input, and second pull-down path comprising a switch receiving the data input. The storage element includes a shifting circuit configured to provide a second signal in response to the first signal at second node, and a scan output buffer coupled to the second node and configured to provide a scan output at a scan output terminal in response to the second signal.

TECHNICAL FIELD

The present disclosure generally relates to scan chains and power and area optimization in Integrated Circuits (ICs).

BACKGROUND

In integrated circuit (IC) testing, the test technique of internal embedded scan design has become a cost effective solution to test the operation of ICs. Scan design is accomplished by altering the structure of standard flip-flops and latches (storage elements) within the IC into scan flip-flops and latches by providing a second alternate scan input for scan data parallel to the functional data input. The alternate input for scan data is generally implemented by placing a multiplexer in front of the standard input which selects either scan data or functional data. These “scannable” elements are then connected together in a serial shift register fashion by connecting the output of one element to the scan input of a next element via a “scan chain”. The scan chain can load and unload internal IC state information by allowing scan data to be transferred from one element to another on each active clock edge when a scan enable signal is asserted.

The static timing analysis (STA) closure frequency in automatic test pattern generation (ATPG) shift mode of the scannable storage circuits are quite high, but production test description languages (TDLs) are run at lower frequencies due to high IR drop and reliability issues caused by the complete design logic toggling in the ATPG shift mode. Combinatorial logic contributes to more than 40% of power consumption in scan mode. It is not required for the logic to toggle during ATPG shift. If the toggle on functional combinational logic can be stopped, the ATPG shift frequency can be increased significantly resulting in lesser test-time and hence lesser tester cost. The power consumption of the design depends upon the choice of a “pull-down” Q gating or a “pull-up” Q gating flop for a particular path. Post silicon test programs' development makes it difficult to decide on a type of circuit that ensures minimum test power for all possible TDL combinations, especially in case of partial usage of “gated Q” flops.

In functional mode of operation, the SD (scan input) pins of flops are connected to SQ (scan output) pins of the previous flop. Whenever there is a signal activity on the D (functional data) pin of a flop, the signal travels to the SD pins of the subsequent flops, thereby causing unnecessary power loss. Considerable amount of power is burnt unnecessarily on test circuits in functional operations. When device is operated in overdrive modes (high frequency modes), the power loss becomes significant causing faster battery discharge.

SUMMARY

A number of exemplary scannable storage elements in Integrated Circuit (ICs), configured for reducing area and power requirement are disclosed. In an embodiment, a scannable storage element for use in an IC is provided. The scannable storage element includes an input circuit configured to provide a signal to a first node in response to one of a data input and a scan input, the scan input being a pull-up logic in a functional mode. The input circuit includes a first pull-up path comprising a first switch receiving a data input and a second switch receiving a scan enable input, and a second pull-up path comprising a third switch receiving a scan input, the second pull-up path and the first pull-up path coupled between a power supply and the first node, a first pull-down path comprising a fourth switch receiving the scan enable input and a fifth switch receiving the scan input, and a second pull-down path comprising a sixth switch receiving the data input, the first pull-down path and the second pull-down path coupled between the first node and a reference supply. The storage element also includes a shifting circuit comprising one or more sequential components, configured to provide a second signal in response to the first signal at a second node, and a scan output buffer coupled to the second node for receiving the second signal, the scan output buffer configured to provide a scan output at a scan output terminal in response to the second signal, where the scan output is one of a pull-up logic and a pull-down logic in the functional mode and the scan output corresponds to the scan input in a shift mode.

In another embodiment, a scannable storage element for use in an IC is provided. The scannable storage element includes an input circuit configured to provide a signal to a first node in response to one of a data input and a scan input, the scan input being a pull-down logic in a functional mode. The input circuit includes a first pull-up path comprising a first switch transistor receiving the scan input and a second switch receiving the data input, and a second pull-up path comprising the first switch and a third switch receiving an inverted scan enable input, the second pull-up path and the first pull-up path coupled between a power supply and the first node, a first pull-down path comprising a fourth switch receiving the inverted scan enable input and a fifth switch receiving the data input, and a second pull-down path comprising a sixth switch receiving the scan input, the first pull-down path and the second pull-down path coupled between the first node and a reference supply. The scannable storage element also includes a shifting circuit comprising one or more sequential components, configured to provide a second signal in response to the first signal at a second node, and a scan output buffer coupled to the second node for receiving the second signal, where the scan output buffer is configured to provide a scan output at a scan output terminal in response to the second signal, where the scan output is one of a pull-up logic and a pull-down logic in the functional mode and the scan output corresponds to the scan input in a shift mode.

In another embodiment, a scannable storage element for use in an IC is provided. The scannable storage element includes an input circuit configured to provide a signal to a first node in response to one of a data input and a scan input, the scan input being one of a pull-up and a pull-down logic in a functional mode. The scannable storage element also includes a shifting circuit comprising one or more sequential components, configured to provide a second signal in response to the first signal at a second node, and a scan output buffer coupled to the second node for receiving the second signal, the scan output buffer configured to provide a scan output at a scan output terminal in response to the second signal, where the scan output is one of a pull-up logic and a pull-down logic in the functional mode and the scan output corresponds to the scan input in a shift mode.

In another embodiment, a method for operating a scannable storage element in an IC. The method includes generating a first signal at a first node of the scannable storage element in response of one of a data input and a scan input, the scan input being one of a pull-up and a pull-down logic in a functional mode. The method includes generating a second signal by one or more sequential elements in response to the first signal at a second node of the scannable storage element. The method further includes generating a scan output at a scan output terminal of the scannable storage element in response to the second signal, wherein the scan output is one of a pull-up logic and a pull-down logic in the functional mode and the scan output corresponds to the scan input in a shift mode.

Other aspects and example embodiments are provided in the drawings and the detailed description that follows.

DETAILED DESCRIPTION

FIG. 1illustrates an example of a scan chain100in an Integrated Circuit (IC) according to an embodiment. As shown inFIG. 1, the scan chain100is formed by a number of scannable storage elements1001,1002. . .100n. Each of the scannable storage element (hereinafter scannable storage element is also referred to as “storage element”) has inputs such as a data input (see, ‘d’) and a scan input (see, ‘sd’), and corresponding outputs a data output (see, ‘d’) and a scan output (see, ‘sq’). The scan chain100is configured to operate in a functional mode or a shift mode. In an embodiment, the storage elements1001,1002. . .100nmay be coupled in a serial manner to configure the scan chain. For instance, a data input ‘d’ of a storage element (for example, of storage element1002) is coupled to a data output ‘q’ of a preceding storage element (storage element1001), and a scan input ‘d’ of the storage element (for example, storage element1002) is coupled to a data output ‘q’ of a preceding storage element (for example, the storage element1001). There may be some combinational components (for example,1021,1022,1023. . . ) between the data input and the data output ‘q’ of the preceding storage element. Various configurations of the storage elements of the scan chain100are described further in reference toFIGS. 2 to 21.

FIG. 2illustrates an example of the first storage element of the scan chain100according to an embodiment. For instance, the storage element200may be an example of the first scannable storage element1001of the scan chain100. In this embodiment, the storage element200is configured such that a scan output of the storage element200is pull-up in functional mode in order to save power by disabling toggling of scan elements in an IC. For instance, by pulling up the scan output terminal in the functional mode, power consumption caused by combinational logic switching in scan path (which is driven by the scan output terminal) may be reduced.

The scannable storage element200includes a node145coupled to a scan output buffer such as a scan output buffer320for driving a scan output terminal. In this example embodiment, the node145is also coupled to a data output buffer440for driving a data output terminal. The storage element200is configured to be selectively coupled to a data input terminal (for receiving a data input) and a scan input terminal (for receiving a scan input) in response to scan enable input. For instance, the storage element200includes a multiplexer260having the data input (see, ‘d’) and a scan input (see, ‘sd’). A scan enable input (SCAN) acts as a select line for the multiplexer260. The multiplexer260is configured by comprising 8 MOS transistors, for example, PMOS transistors262,264,266,268, and NMOS transistors270,272,274and276. An additional transistor280is also required for converting the SCAN to an inverted SCAN signal (SCANZ). The transistors262and264configure a first pull-up path between a power supply (see, VDD) and a node278, where gate of the transistor262is connected to the data input ‘d’, and the gate of the transistor262is connected to the SCAN. The transistors266and268configure a second pull-up path between VDD and the node278, where gate of the transistor266is connected to the scan input ‘sd’, and the gate of the transistor268is connected to SCANZ. The transistors270and272configure a first pull-down path between the node278and a reference supply (see, VSS), where gate of the transistor270is connected to the SCAN, and the gate of the transistor272is connected to the scan input ‘sd’. The transistors274and276configure a second pull-down path between the node278and VSS, where gate of the transistor274is connected to the SCANZ, and the gate of the transistor276is connected to the data input ‘d’.

An output (the node278) of the multiplexer260is connected to a shifting circuit150that is configured to provide a signal at the node145based on the output of the multiplexer260. In the embodiment shown in theFIG. 2, the shifting circuit150includes one or more latches/flip-flops configured by an inverter110, a transmission gate115, an inverter120, an inverter130, a transmission gate125, a transmission gate135, an inverter140, an inverter146, an inverter185and a transmission gate190. It should be noted that there may be various variations of the shifting circuit150from the embodiment shown inFIG. 2. The inverter110is coupled to the output of the multiplexer260, and an output of the inverter110is connected to an input of the transmission gate115. An inverted clock input (CLKZ) is provided to the transmission gate115. The CLKZ may be provided by inverting the clock input CLK using an inverter290. An output of the transmission gate115is connected a node195. The inverter130is connected to the node195. The transmission gate125is connected to an output of the inverter130. Output of the transmission gate125is connected to an input of the inverter120. The transmission gate125is connected to a clock signal (CLK). The output of the inverter130is also connected to a node197. An input of the transmission gate135is connected to the node197. An output of the transmission gate135is connected to the inverter140which is then connected to the node145.

The data output buffer440includes a PMOS transistor425and an NMOS transistor430(comprising an inverter). The source of the transistor425is connected to a power supply voltage (for example, VDD) and the drain of the transistor425is connected to a node435. The source of the transistor430is connected to a reference supply (or ground voltage, see, VSS) and the drain of the transistor430is connected to the node435. The gates of both the transistors (425and430) are connected to the node145. The data output terminal is connected to the node310, from where the data output ‘q’ is taken. The scan output buffer320includes a PMOS transistor302and an NMOS transistor304. Source of the transistor302is connected to the power supply voltage (Vdd) and drain of the transistor302is connected to the node535. The gate of the transistor302is connected to the node145. The source of the transistor304is connected to the drain of another NMOS transistor306and the drain of the transistor304is connected to the node310. Gate of the transistor306is also connected to the node145. Source of the transistor306is connected to the reference supply and the drain of the transistor306is connected to the source of the transistor304. The gate of transistor306is connected to the scan enable input (SCAN). The transistor306is used to disable the direct path between VDD and VSS when SCAN is 0. Another PMOS transistor308is used to pull-up the scan output ‘sq’. Source of the transistor308is connected to the power supply VDD and drain of the transistor308is connected to the node310(that is the scan output ‘sq’). Gate of the transistor308is connected to scan enable input (SCAN). The scan output (sq) of the storage element200is taken from the node310.

The operation of the storage element200is now explained. The multiplexer260causes a signal corresponding to one of the data input and the scan input ‘sd’, to be transferred at the node362. As illustrated in theFIG. 2, when SCAN is logic 0, an inverse of the data input ‘d’ is transferred at the node278, and when SCAN is logic 1, an inverse of the scan input ‘sd’ is transferred at the node278. For explanation, if SCAN is logic 0, the pull-up path comprising the transistor262and264is enabled, and the pull-down path comprising the transistor274and276are enabled. Accordingly, the transistors262,264,274and276form an inverter configuration, and an inverted logic level of ‘d’ is transferred to the node278. Assuming that is set to logic 1, then inverse of ‘d’, for example, logic 0 will then be available at the node278. The shifting circuit150is configured to force a logic level at the node145that is the inverse of the value at the node278. For example, output of the inverter110of the shifting circuit145is logic 1. When CLK is low the transmission gate115becomes transparent and the logic 1 at the input of transmission gets transferred to the node195, forcing the output of the inverter130(node197) to be logic 0. When CLK becomes high the transmission gate125becomes transparent which transfers the value at node197(logic 0) to the inverter120. The inverter120forces logic 1 on the node195. Another transmission gate135in enabled when CLK becomes high and hence transfers the value at node197(logic 0) to the inverter140. The inverter140forces logic 1 on the node145. The inverter185, the transmission gate190and the inverter146comprise a loop back path when CLK is logic 0 and helps to retain the value at the node145. The data output buffer440(an inverter) inverts the value at the node145and force a logic 0 at the node435. The data output ‘q’ is taken from the node435(that is the data output terminal) as inverse of the data input ‘d’. In some other embodiments, another inverter may be added in the data output buffer440to get to the data output ‘q’ that is of same logic level as the data input ‘d’. As SCAN is logic 0, the transistor306is disabled, which stops the data propagation to the node310. At the same time the transistor308is enabled which then pulls up the node310to logic 1. The scan output terminal is coupled to the node310. Accordingly, in functional mode (when SCAN is logic 0), the scan output ‘sq’ is tied to logic 1 (this may help in power reduction in functional mode due to combinational logic switching in scan path which is driven by the scan output terminal). The scan enable input (SCAN) acts as a control signal, which decides whether to tie the scan output terminal ‘sq’ to logic 1 or not. Accordingly, when SCAN is logic 0, the data output ‘q’ follows the inverse of the data input ‘d’ and the scan output ‘sq’ is tied to logic 1.

When SCAN is logic 1, the pull-up path comprising the transistor266and268is enabled, and the pull-down path comprising the transistor270and272are enabled. Accordingly, the transistors266,268,270and272form an inverter configuration, and an inverted logic level of ‘sd’ is transferred to the node278. It should be further be noted that when SCAN is logic 1, the scan output buffer320acts as an inverter, as the transistor308is disabled and the transistors302,304and306form an inverter configuration. The shifting circuit150is configured to force a logic level at the node145that is the inverse of the node278. For instance, if the scan input ‘sd’ is logic 1, the node278is at logic 0, and the node145is at logic 1. The scan output buffer320then transfers logic 0 at the node310that is coupled to the scan output sq. Accordingly, inverse of the scan input ‘sd’ is transferred to the scan output ‘sq’ when the device (IC) operates in the shift mode.

FIG. 3illustrates an example of the first storage element of the scan chain100according to another embodiment. For instance, the storage element300may be an example of the first scannable storage element1001of the scan chain100. In this embodiment, the storage element300is configured such that a scan output of the storage element300is pull-down in functional mode in order to save power by disabling toggling of scan elements in an IC.

The storage element300includes a node145coupled to a scan output buffer such as a scan output buffer340for driving a scan output terminal. In this example embodiment, the node145is also coupled to data output buffer440for driving a data output terminal. The storage element300is configured to be selectively coupled to a data input terminal (for receiving a data input) and a scan input terminal (for receiving a scan input) in response to scan enable input. For instance, the storage element300includes a multiplexer260having the data input (see, ‘d’) and a scan input (see, ‘sd’). A scan enable input (SCAN) acts as a select line for the multiplexer260. The multiplexer260is configured by comprising eight MOS transistors, for example, PMOS transistors262,264,266,268, and NMOS transistors270,272,274and276. An additional transistor280is also required for converting the SCAN to an inverted SCAN signal (SCANZ). The transistors262and264configure a first pull-up path between a power supply (see, VDD) and a node278, where gate of the transistor262is connected to the data input ‘d’, and the gate of the transistor262is connected to the SCAN. The transistors266and268configure a second pull-up path between the VDD and the node278, where gate of the transistor266is connected to the scan input ‘sd’, and the gate of the transistor268is connected to SCANZ. The transistors270and272configure a first pull-down path between the node278and the reference supply (VSS), where gate of the transistor270is connected to the SCAN, and the gate of the transistor272is connected to the scan input ‘sd’. The transistors274and276configure a second pull-down path between the node278and VSS, where gate of the transistor274is connected to the SCANZ, and the gate of the transistor276is connected to the data input ‘id’.

An output (the node278) of the multiplexer260is connected to a shifting circuit150that is configured to provide a signal at the node145based on the output of the multiplexer260. In the embodiment shown in theFIG. 3, the shifting circuit150includes one or more latches/flip-flops configured by an inverter110, a transmission gate115, an inverter120, an inverter130, a transmission gate125, a transmission gate135, an inverter140, an inverter146, an inverter185and a transmission gate190. It should be noted that there may be various variations of the shifting circuit150from the embodiment shown inFIG. 2. The inverter110is coupled to the output of the multiplexer260, and an output of the inverter110is connected to an input of the transmission gate115. An inverted clock input (CLKZ) is provided to the transmission gate115. An output of the transmission gate115is connected a node195. The inverter130is connected to the node195. The transmission gate125is connected to an output of the inverter130. Output of the transmission gate125is connected to an input of the inverter120. The transmission gate125is connected to a clock signal (CLK). The output of the inverter130is also connected to a node197. An input of the transmission gate135is connected to the node197. An output of the transmission gate135is connected to the inverter140which is then connected to the node145.

As also described in reference toFIG. 2, the data output buffer440includes the PMOS transistor425and the NMOS transistor430(comprising an inverter). The data output terminal is connected to the node310, from where the data output ‘q’ is taken. The scan output buffer340includes PMOS transistors322and324and NMOS transistors326and328. Source of the transistor322is connected to power supply voltage (Vdd) and drain of the transistor322is connected to source of the transistor324. Drain of the transistor324is connected to the node330and also to the drain of the transistor326. Gates of the transistor324and326are connected to the node145, and gate of the transistor322is connected to SCANZ. Drain of the NMOS transistor720is connected to the node330, and gate of the transistor328is connected to the SCANZ causing the transistor328to act as a pull-down transistor in the functional mode (when SCANZ is logic 1). Further, the transistor322is used to disable the direct path between VDD and VSS in the functional mode. It should be noted that in the shift mode (when SCANZ is logic 0), the transistor428is disabled; and the transistor322is enabled thereby providing a direct path VDD and VSS in the shift mode. Accordingly, in the shift mode, the transistors322,324and326form an inverter configuration and provide an inverse of the value of the node145to the node330.

The operation of the storage element300is now explained. The multiplexer260causes a signal corresponding to one of the data input ‘d’ and the scan input ‘sd’, to be transferred at the node362. As illustrated in theFIG. 3, when SCAN is logic 0, an inverse of the data input ‘d’ is transferred at the node278, and when SCAN is logic 1, an inverse of the scan input ‘sd’ is transferred at the node278. For explanation, if SCAN is logic 0, the pull-up path comprising the transistor262and264is enabled, and the pull-down path comprising the transistor274and276are enabled. Accordingly, the transistors262,264,274and276form an inverter configuration, and an inverted logic level of is transferred to the node278. Assuming that ‘d’ is set to logic 1, then inverse of ‘d’, for example, logic 0 will then be available at the node278. The shifting circuit150is configured to force a logic level at the node145that is the inverse of the value at the node278. For example, output of the inverter110of the shifting circuit145is logic 1. When CLK is low the transmission gate115becomes transparent and the logic 1 at the input of transmission gets transferred to the node195, forcing the output of the inverter130(node197) to be logic 0. When CLK becomes high the transmission gate125becomes transparent which transfers the value at node197(logic 0) to the inverter120. The inverter120forces logic 1 on the node195. Another transmission gate135in enabled when CLK becomes high and hence transfers the value at node197(logic 0) to the inverter140. The inverter140forces logic 1 on the node145. The inverter185, the transmission gate190and the inverter146comprise a loop back path when CLK is logic 0 and helps to retain the value at the node145. The data output buffer440(an inverter) inverts the value at the node145and force a logic 0 at the node435. The data output ‘q’ is taken from the node435(that is the data output terminal) as inverse of the data input ‘d’. In some other embodiment, another inverter may be added in the data output buffer440to get to the data output ‘q’ that is same as data input ‘d’. As SCAN is logic 0, the transistor322is disabled, which stops the data propagation to the node330. At the same time the transistor328is enabled which then pulls-down the node330to logic 0. The scan output terminal is coupled to the node330. Accordingly, in functional mode (when SCAN is logic 0), the scan output ‘sq’ is tied to logic 0 (this may help in power reduction in functional mode due to combinational logic switching in scan path which is driven by the scan output terminal). The scan enable input (SCAN) acts as a control signal, which decides whether to tie the scan output terminal ‘sq’ to logic 0 or not. Accordingly, when SCAN is logic 0, the data output ‘q’ follows the inverse of the data input ‘d’ and the scan output ‘sq’ is tied to logic 0.

When SCAN is logic 1, the pull-up path comprising the transistor266and268is enabled, and the pull-down path comprising the transistor270and272are enabled. Accordingly, the transistors266,268,270and272final an inverter configuration, and an inverted logic level of ‘sd’ is transferred to the node278. It should be further be noted that when SCAN is logic 1, the scan output buffer340acts as an inverter, as the transistor328is disabled and the transistors322,324and326form an inverter configuration. The shifting circuit150is configured to force a logic level at the node145that is the inverse of the node278. For instance, if the scan input ‘sd’ is logic 1, the node278is at logic 0, and the node145is at logic 1. The scan output buffer340then transfers logic 0 at the node310that is coupled to the scan output ‘sq’. Accordingly, inverse of the scan input ‘sd’ is transferred to the scan output ‘sq’ when the device (IC) operates in the shift mode.

As the scan output is either pull-up or pull-down in the first storage element1001of the scan chain100, its logic state is fixed. Various embodiments of the present technology make use of the information to design input multiplexer circuit for the subsequent storage elements. Such designs of the input multiplexer circuits are capable of reducing the number of transistors in the storage elements, and are explained in reference toFIGS. 4 to 21. Further, various embodiments are also capable of gating one or both of the q and sq, and are explained in reference toFIGS. 4 to 21.

FIG. 4illustrates an example of a storage element other than the first storage element of the scan chain100according to an embodiment. The storage element400may be an example of any of the storage elements1002,1003. . . or100n, in cases where the scan input data ‘sd’ received by the storage element400is pull-up in the functional mode. For instance, the storage element400is utilized when the scan output ‘sq’ (that is coupled to the scan input ‘sd’ of the storage element400) provided by a preceding storage element (of the storage element400) is pull-up in the functional mode (when SCAN is logic 0). For example, when SCAN is logic 0, the scan input ‘sd’ is logic 1.

The storage element400includes a node145(a second node) coupled to a scan output buffer550for driving a scan output terminal535. In this example embodiment, the node145is also coupled to data output buffer505for driving a data output terminal510. In this embodiment, the data output buffer505is shown as an inverter. The storage element400includes an input circuit360that is configured to receive a data input (see, ‘d’) and a scan input (see, ‘sd’) from a data output ‘q’ and a scan output ‘sq’ of the preceding storage element, respectively. The input circuit360is configured to provide a signal (first signal) corresponding to one of the data input ‘d’ and the scan input ‘sd’, at a node362(first node). The input circuit360provides the signal at the node362based on a select signal such as the scan enable input (see, SCAN). The input circuit360includes pull-up components and pull-down components coupled to the node362. For instance, the input circuit360includes two pull-up paths connected between the node362and the power supply (see, VDD), where the first pull-up path includes a first switch to receive the data input ‘d’ and a second switch to receive the scan enable input ‘SCAN’. An example of the first switch may include a PMOS transistor365and an example of the second switch may include a PMOS transistor370as shown in the embodiment ofFIG. 4, and they are coupled such that a drain of the PMOS transistor365is connected to a source of the PMOS transistor370. The second pull-up path includes a third switch (for example, a PMOS transistor375) to receive the scan input ‘sd’. In this embodiment, gates of the PMOS transistors365,370and375are connected to the data input ‘d’, the scan enable input ‘SCAN’ and the scan input ‘sd’, respectively, and sources of the PMOS transistors370and375are coupled with the node362. The input circuit360further includes two pull-down paths connected between the node362and the reference supply (see, VSS) or ground supply. A first pull-down path includes a fourth switch to receive the scan enable input ‘SCAN’ and a fifth switch to receive the scan input ‘sd’. An example of the fourth switch is a NMOS transistor380and an example of the fifth switch is a NMOS transistor385, as shown in the embodiment ofFIG. 4, and they are coupled such that a source of the NMOS transistor380is connected to a drain of the NMOS transistor385. A second pull-down path includes a sixth switch to receive the data input ‘d’. An example of the sixth switch may include an NMOS transistor390as shown inFIG. 4. Gates of the NMOS transistors380,385and390are coupled with the scan enable input ‘SCAN’, the scan input ‘sd’ and the data input ‘d’, respectively, and drains of the NMOS transistors380and390are coupled with the node362. The input circuit360is configured such that it requires only six transistors instead of ten transistors that are otherwise required in the input circuit260, as the ‘sd’ input is fixed (for example, of logic 1) in the functional mode. Though, in the embodiments shown inFIG. 4, the first switch, the second switch, the third switch, the fourth switch, the fifth switch and the sixth switch are shown as PMOS or NMOS transistors, but they can also be configured using other components that are functionally analogous to the MOS transistors, such as BJT transistors, combinations of diodes, and the like.

An output (for example, the node362) of the input circuit360is connected to the shifting circuit150that is configured to transfer a signal corresponding to the node362to the node145. The shifting circuit150includes to the inverter110that takes input from the node362and an output of the inverter110is connected to the transmission gate115. An inverted clock input CLKZ is given to the transmission gate115. The transmission gate115is connected a node195. An inverter130is connected to the node195. Another transmission gate125is connected to an output of the inverter130. Output of the transmission gate125is connected to an input of another inverter120. The transmission gate125is connected to clock signal (see, CLK). The output of the inverter130is also connected to node197. A transmission gate135is connected to the node197. An output of the transmission gate135is connected to an inverter140which is then connected to the node145. The input of the data output buffer505is connected to the node145and the output of the data output buffer505is connected to node510that is the data output terminal. The data output buffer505includes an inverter. The node145is connected to the inverter185. The output of the inverter185is connected to a node152, which then connects to a transmission gate190. The transmission gate190is controlled by inverted clock signal CLKZ. The transmission gate190drives another inverter146. The output of the inverter146is again connected to the node145. The scan output buffer550includes an inverter configured by a PMOS transistor515and an NMOS transistor520, a transistor525(third MOS transistor) and a transistor530(a fourth MOS transistor). Source of the transistor515is connected to power supply voltage (Vdd) and drain of the transistor515is connected to node535. The gate of the transistor515is connected to the node145. The source of the transistor520is connected to the drain of another NMOS transistor525and the drain of the transistor520is connected to the node535. Gate of the transistor525(third MOS transistor) is also connected to the node145. Source of the transistor525is connected to the ground voltage and drain of the transistor525is connected to the source of the transistor520. The gate of transistor525is connected to the scan enable input (SCAN). The transistor525is used to disable the direct path between VDD and VSS when SCAN is 0. The transistor530(for example, a PMOS transistor) is used to pull-up the scan output ‘sq’. Source of the transistor530is connected to the supply voltage and drain of the transistor530is connected to the node535(that is the scan output ‘sq’). Gate of the transistor530is connected to scan enable input (SCAN). The scan output (sq) of the scannable storage element400is taken from the node535.

The operation of the storage element400is now explained. The input circuit360causes a signal corresponding to one of the data input ‘d’ and the scan input ‘sd’, to be transferred at the node362. It should be noted that the scan input ‘sd’ is logic 1, when the SCAN is logic 0. For instance, a scan output ‘sq’ of a preceding storage element (such as the storage element200) of the storage element400is pull-up when the SCAN is logic 0, and this pull-up logic 1 is fed to the scan input ‘sd’ of the storage element400. When the SCAN is logic 1, the scan input ‘sd’ may have either of logic 0 or logic 1 depending upon the test data and value as received from the preceding storage element. As illustrated in theFIG. 4, when SCAN is logic 0, an inverse of the data input ‘d.’ is transferred at the node362, and when SCAN is logic 1, an inverse of the scan input ‘sd’ is transferred at the node362.

For explanation, if SCAN is logic 0 (scan input ‘sd’ is logic 1), the transistor375and380are disabled, and the transistors370and385are enabled. Accordingly, the transistors365,370,390and385form an inverter configuration, and an inverted logic level of ‘d’ is transferred to the node362. Assuming that ‘d’ is set to logic 1, then inverse of ‘d’, for example, logic 0 will then be available at the node362. The shifting circuit150is configured to force a logic level at the node145that is the inverse of the value at the node362. For example, output of inverter110of the shifting circuit145is logic 1. When CLK is low the transmission gate115becomes transparent and the logic 1 at the input of transmission gets transferred to the node195, forcing the output of the inverter130(node197) to be logic 0. When CLK becomes high the transmission gate125becomes transparent which transfers the value at node197(logic 0) to the inverter120. The inverter120forces logic 1 on the node195. Another transmission gate135in enabled when CLK becomes high and hence transfers the value at node197(logic 0) to the inverter140. The inverter140forces logic 1 on the node145. The inverter185, the transmission gate190and the inverter146comprise a loop back path when CLK is logic 0 and helps to retain the value at the node145. The data output buffer505(an inverter) inverts the value at the node145and force a logic 0 at the node410. The data output ‘q’ is taken from the node510(that is the data output terminal) as inverse of the data input ‘d’. In some embodiments, there may be additional inverters added to the data output buffer505so as to receive the data output ‘q’ of same logic as the data input ‘d’. As SCAN is logic 0, the transistor525is disabled, which stops the data propagation to the node535. At the same time the transistor530is enabled which then pulls up the node535to logic 1. The scan output terminal is coupled to the node535. Accordingly, in functional mode (when SCAN is logic 0), the scan output ‘sq’ is tied to logic 1 (this may help in power reduction in functional mode due to combinational logic switching in scan path which is driven by the scan output terminal). The scan enable input (SCAN) acts as a control signal, which decides whether to tie the scan output terminal ‘sq’ to logic 1 or not. Accordingly, when SCAN is logic 0, the data output ‘q’ follows the inverse of the data input ‘d’ and the scan output ‘sq’ is tied to logic 1. In some embodiments, there may be additional inverters added in the scan output buffer550so as to receive the scan output ‘sq’ of same logic as the scan input ‘sd’.

When SCAN is logic 1, the transistor370is disabled, and the transistor375(pull-up) and transistors380and385(pull-down) form an inverter configuration, and an inverse of the scan input ‘sd’ is transferred to the node362. It should be further be noted that when SCAN is logic 1, the scan output buffer550acts as an inverter, as the transistor530is disabled and the transistors515,520and525form an inverter configuration. The shifting circuit150is configured to force a logic level at the node145that is the inverse of the node362. For instance, if the scan input ‘sd’ is logic 1 (provided the SCAN is logic 1), the node362is at logic 0, and the node145is at logic 1. The scan output buffer550then transfers logic 0 at the node535that is coupled to the scan output sq. Accordingly, inverse of the scan input ‘sd’ is transferred to the scan output ‘sq’ when the device (IC) operates in the shift mode.

FIG. 5illustrates an example of a storage element other than the first storage element of the scan chain100according to another embodiment. The storage element500may be an example of any of the storage elements1002,1003. . . or100n, in cases where the scan input data ‘sd’ received by the storage element500is pull-down in the functional mode. For instance, the storage element500is utilized when the scan output ‘sq’ (that is coupled to the scan input ‘sd’ of the storage element500) provided by a preceding storage element (of the storage element500) is pull-down in the functional mode (when SCAN is logic 0). For example, when SCAN is logic 0, the scan input ‘sd’ is logic 0.

The storage element500includes a node145coupled to a scan output buffer550for driving a scan output terminal535. In this example embodiment, the node145is also coupled to data output buffer505for driving a data output terminal510. In this embodiment, the data output buffer505is shown as an inverter. The storage element500includes an input circuit460that is configured to receive a data input (see, ‘d’) and a scan input (see, ‘sd’) from a data output ‘q’ and a scan output ‘sq’ of the preceding storage element, respectively. The input circuit460is configured to provide a signal corresponding to one of the data input ‘d’ and the scan input ‘sd’, at a node462(the first node). The input circuit460provides the signal at the node462based on a select signal such as inverse scan enable input (see, SCANZ). The input circuit460includes pull-up components and pull-down components coupled to the node462. For instance, the input circuit460includes two pull-up paths connected between the node462and the power supply (see, VDD), where the first pull-up path includes a first switch to receive the scan input ‘sd’ and a second switch to receive the data input ‘d’. An example of the first switch may include a PMOS transistor465and an example of the second switch may include a PMOS transistor470as shown in the embodiment ofFIG. 5, and they are coupled such that a drain of the PMOS transistor465is connected to a source of the PMOS transistor470. The second pull-up path includes the first switch and a third switch to receive the inverted scan enable input (SCANZ). An example of the third switch may include a PMOS transistor475. A source of the PMOS transistor475is connected to the drain of the PMOS transistor465. Gates of the PMOS transistors465,470and475are connected to the scan input ‘sd’, the data input ‘d’ and the inverse scan enable input ‘SCANZ’, respectively, and sources of the PMOS transistors470and475are coupled with the node462. The input circuit460further includes two pull-down paths connected between the node462and the reference supply (see, VSS) or ground supply. A first pull-down path includes a fourth switch to receive the inverted scan enable input ‘SCANZ’ and a fifth switch to receive the data input ‘d’. An example of the fourth switch may include a NMOS transistor480and an example of the fifth switch includes a NMOS transistor485, and they are coupled such that a source of the NMOS transistor380is connected to a drain of the NMOS transistor485. The second pull-down path includes a sixth switch to receive the scan input ‘sd’. An example of the sixth switch may include a NMOS transistor490. Gates of the NMOS transistors480,485and490are coupled with SCANZ, the data input and the scan input ‘sd’, respectively, and drains of the NMOS transistors480and490are coupled with the node462. In the embodiment shown inFIG. 5, the input circuit460is configured such that it requires only eight transistors instead of ten transistors that are otherwise required in the input circuit260, as the ‘sd’ input is fixed (either of logic 0 or logic 1). It should be noted that in this embodiment, two additional transistors are required as compared to the embodiment described in reference toFIG. 4, as two transistors are required for generating the inverted scan enable input ‘SCANZ’. Though, in the embodiments shown inFIG. 5, the first switch, the second switch, the third switch, the fourth switch, the fifth switch and the sixth switch are shown as PMOS or NMOS transistors, but they can also be configured using other components that are functionally analogous to the MOS transistors, such as BJT transistors, combinations of diodes, and the like.

An output (for example, the node462) of the input circuit460is connected to the shifting circuit150that is configured to transfer a signal corresponding to the node462to the node145. The shifting circuit150includes to the inverter110that takes input from the node462and an output of the inverter110is connected to the transmission gate115. An inverted clock input CLKZ is given to the transmission gate115. The transmission gate115is connected a node195. The inverter130is connected to the node195. Another transmission gate125is connected to an output of the inverter130. Output of the transmission gate125is connected to an input of another inverter120. The transmission gate125is connected to clock signal (see, CLK). The output of the inverter130is also connected to the node197. A transmission gate135is connected to the node197. An output of the transmission gate135is connected to the inverter140which is then connected to the node145. The input of the data output buffer505is connected to the node145and the output of the data output buffer505is connected to node510(the data output terminal). The data output buffer505includes an inverter. The node145is connected to the inverter185. The output of the inverter185is connected to the node152, which then connects to a transmission gate190. The transmission gate190is controlled by inverted clock signal CLKZ. The transmission gate190drives another inverter146. The output of the inverter146is again connected to the node145. The scan output buffer550includes PMOS transistors515and an NMOS transistor520. Source of the transistor515is connected to power supply voltage (Vdd) and drain of the transistor515is connected to node535. The gate of the transistor515is connected to the node145. The source of the transistor520is connected to the drain of another NMOS transistor525and the drain of the transistor520is connected to the node535. Gate of the transistor525is also connected to the node145. Source of the transistor525is connected to the ground voltage and drain of the transistor525is connected to the source of the transistor520. The gate of transistor525is connected to the scan enable input (SCAN). The transistor525is used to disable the direct path between VDD and VSS when SCAN is 0. Another PMOS transistor530is used to pull-up the scan output ‘sq’. Source of the transistor530is connected to the supply voltage and drain of the transistor530is connected to the node535(that is the scan output ‘sq’). Gate of the transistor530is connected to scan enable input (SCAN). The scan output (sq) of the scannable storage element400is taken from the node535.

The operation of the storage element500is now explained. The input circuit460causes a signal corresponding to one of the data input ‘d’ and the scan input ‘sd’, to be transferred at the node462. It should be noted that the scan input ‘sd’ is logic 0, when the SCAN is logic 0. For instance, a scan output ‘sq’ of the preceding storage element (such as the storage element300) of the storage element500is pull-down when the SCAN is logic 0, and this pull-down logic 0 is fed to the scan input ‘sd’ of the storage element500. When the SCAN is logic 1, the scan input ‘sd’ may have either of logic 0 or logic 1 depending upon the test data and value as received from the preceding storage element. As illustrated in theFIG. 5, when SCAN is logic 0, an inverse of the data input ‘d’ is transferred at the node462, and when SCAN is logic 1 (or when SCANZ is logic 0), an inverse of the scan input ‘sd’ is transferred at the node462.

For explanation, in functional mode (when SCAN is logic 0 or SCANZ is logic 1), the scan input ‘sd’ is logic 0, so the transistor475and490are disabled, and the transistors465and480are enabled. Accordingly, the transistors465,470,480and485form an inverter configuration, and an inverted logic level of ‘d’ is transferred to the node462. Assuming that ‘d’ is set to logic 1, then inverse of ‘d’, for example, logic 0 will then be available at the node462. The shifting circuit150is configured to force a logic level at the node145that is the inverse of value at the node462. For example, logic 1 is transferred at the output of inverter110of the shifting circuit145. When CLK is low the transmission gate115becomes transparent and the logic 1 at the input of transmission gets transferred to the node195, forcing the output of the inverter130(node197) to be logic 0. When CLK becomes high the transmission gate125becomes transparent which transfers the value at node197(logic 0) to the inverter120. The inverter120forces logic 1 on the node195. Another transmission gate135in enabled when CLK becomes high and hence transfers the value at node197(logic 0) to the inverter140. The inverter140forces logic 1 on the node145. The inverter185, the transmission gate190and the inverter146comprise a loop back path when CLK is logic 0 and helps to retain the value at the node145. The data output buffer505(an inverter) inverts the value at the node145and force a logic 0 at the node510. The data output ‘q’ is taken from the node510(that is the data output terminal) as inverse of the data input ‘d’. As SCAN is logic 0, the transistor525is disabled, which stops the data propagation to the node535. At the same time the transistor530is enabled which then pulls up the node535to logic 1. The scan output terminal is coupled to the node535. Accordingly, in functional mode (when SCAN is logic 0), the scan output ‘sq’ is tied to logic 1 (this may help in power reduction in functional mode due to combinational logic switching in scan path which is driven by the scan output terminal). The scan enable input (SCAN) acts as a control signal, which decides whether to tie the scan output terminal ‘sq’ to logic 1 or not. Accordingly, when SCAN is logic 0, the data output ‘q’ follows the inverse of the data input ‘d’ and the scan output ‘sq’ is tied to logic 1.

In shift mode (when SCAN is logic 1 or SCANZ is logic 0), the transistor480is disabled, and the transistors465,475(pull-up) and transistors490(pull-down) form an inverter configuration, and an inverse of the scan input ‘sd’ is transferred to the node462. It should be further be noted that when SCAN is logic 1, the scan output buffer550acts as an inverter, as the transistor530is disabled and the transistors515,520and525form an inverter configuration. The shifting circuit150is configured to force a logic level at the node145that is the inverse of the node462. For instance, if the scan input ‘sd’ is logic 1 (provided the SCAN is logic 1), the node462is at logic 0, and the node145is at logic 1. The scan output buffer550then transfers logic 0 at the node535that is coupled to the scan output ‘sq’. Accordingly, inverted scan input ‘sd’ is transferred to the scan output ‘sq’ when the device operates in the shift mode.

FIG. 6illustrates an example of a storage element other than the first storage element of the scan chain100according to an embodiment. The storage element600may be an example of any of the storage elements1002,1003. . . or100n, in cases where the scan input data ‘sd’ received by the storage element600is pull-up in the functional mode. For instance, the storage element600is utilized when the scan output ‘sq’ (that is coupled to the scan input ‘sd’ of the storage element600) provided by a preceding storage element (of the storage element600) is pull-up in the functional mode (when SCAN is logic 0). For example, when SCAN is logic 0, the scan input ‘sd’ is logic 1.

The storage element600includes a node145coupled to a scan output buffer750for driving a node725(scan output terminal). In this example embodiment, the node145is also coupled to data output buffer505for driving a data output terminal510. In this embodiment, the data output buffer505is shown as an inverter. The storage element600includes the input circuit360that is configured to receive a data input (see, ‘d’) and a scan input (see, ‘sd’) from a data output ‘q’ and a scan output ‘sq’ of the preceding storage element, respectively. The input circuit360is already described in reference with theFIG. 4, and hence its description is not provided for the sake of brevity. The input circuit360is configured to provide a signal corresponding to one of the data input ‘d’ and the scan input ‘sd’, at the node362.

An output (for example, the node362) of the input circuit360is connected to the shifting circuit150that is configured to transfer a signal corresponding to the node362to the node145. The input of the data output buffer505is connected to the node145and the output of the data output buffer505is connected to node510(the data output terminal). The data output buffer505includes an inverter. The scan output buffer750is also connected to the node145. The scan output buffer750includes a PMOS transistor705(first MOS transistor), an inverter (comprising a PMOS transistor710and a NMOS transistors715), and a NMOS transistor720(second MOS transistor). Source of the transistor705is connected to power supply voltage (Vdd) and drain of the transistor705is connected to source of the transistor710. Drain of the transistor710is connected to the node535and also to the drain of the transistor715. Gates of the transistor710and715are connected to the node145, and gate of the transistor705is connected to SCANZ. Drain of the NMOS transistor720is connected to the node535, and gate of the transistor720is connected to the SCANZ causing the transistor720to act as a pull-down transistor in functional mode (when SCANZ is logic 1). Further, the transistor705is used to disable the direct path between VDD and VSS in the functional mode. It should be noted that in the shift mode (when SCANZ is logic 0), the transistor720is disabled; and the transistor705is enabled thereby providing a direct path VDD and VSS in the shift mode. Accordingly, in the shift mode, the transistors705,710and715form an inverter configuration and provide an inverse of the value of the node145to the node725.

The operation of the storage element600is now explained. The input circuit360causes a signal corresponding to one of the data input ‘d’ and the scan input ‘sd’, to be transferred at the node362. It should be noted that the scan input ‘sd’ is logic 1, when the SCAN is logic 0. For instance, a scan output ‘sq’ of a preceding storage element (such as the storage element200) of the storage element600is pull-up when the SCAN is logic 0, and this pull-up logic 1 is fed to the scan input ‘sd’ of the storage element600. When the SCAN is logic 1, the scan input ‘sd’ may have either of logic 0 or logic 1 depending upon the test data and value as received from the preceding storage element. As described in reference toFIG. 4, when SCAN is logic 0, an inverse of the data input ‘d’ is transferred at the node362, and when SCAN is logic 1, an inverse of the scan input ‘sd’ is transferred at the node362.

In functional mode (when SCAN is logic 0 or SCANZ is logic 1), the scan input ‘sd’ is logic 1, so the transistor375and380are disabled, and the transistors370and385are enabled. Accordingly, the transistors365,370,390and385form an inverter configuration, and an inverted logic level of is transferred to the node362. Assuming that ‘d’ is set to logic 1, then inverse of ‘d’, for example, logic 0 will then be available at the node362. The shifting circuit150is configured to force a logic level at the node145that is the inverse of the value at the node362. For example, output of inverter110of the shifting circuit145is logic 1. When CLK is low the transmission gate115becomes transparent and the logic 1 at the input of transmission gets transferred to the node195, forcing the output of the inverter130(node197) to be logic 0. When CLK becomes high the transmission gate125becomes transparent which transfers the value at node197(logic 0) to the inverter120. The inverter120forces logic 1 on the node195. Another transmission gate135in enabled when CLK becomes high and hence transfers the value at node197(logic 0) to the inverter140. The inverter140forces logic 1 on the node145. The inverter185, the transmission gate190and the inverter146comprise a loop back path when CLK is logic 0 and helps to retain the value at the node145. The data output buffer505(an inverter) inverts the value at the node145and force a logic 0 at the node510. The data output ‘q’ is taken from the node510(that is the data output terminal) as inverse of the data input ‘d’. As SCAN is logic 0, the transistor705is disabled, which stops the data propagation to the node725. At the same time the transistor720is enabled which then pulls-down the node725to logic 0. The scan output terminal is coupled to the node725. Accordingly, in functional mode (when SCAN is logic 0), the scan output ‘sq’ is tied to logic 0 (this may help in power reduction in functional mode due to combinational logic switching in scan path which is driven by the scan output terminal). The scan enable input (SCANZ) acts as a control signal, which decides whether to tie the scan output terminal ‘sq’ to logic 1 or not. Accordingly, when SCAN is logic 0, the data output ‘q’ follows the inverse of the data input and the scan output ‘sq’ is tied to logic 0 (i.e., pull-down).

In shift mode (when SCAN is logic 1 or SCANZ is logic 0), the transistor370is disabled, and the transistor375(pull-up) and transistors380and385(pull-down) form an inverter configuration, and an inverse of the scan input ‘sd’ is transferred to the node362. It should be further be noted that when SCAN is logic 1, the scan output buffer750acts as an inverter, as the transistor720is disabled and the transistors705,710and715form an inverter configuration. The shifting circuit150is configured to force a logic level at the node145that is the inverse of the node362. For instance, if the scan input ‘sd’ is logic 1 (provided the SCAN is logic 1), the node362is at logic 0, and the node145is at logic 1. The scan output buffer750then transfers logic 0 at the node725that is coupled to the scan output ‘sq.’. Accordingly, inverse of the scan input ‘sd’ is transferred to the scan output ‘sq’ when the IC operates in the shift mode.

FIG. 7illustrates an example of a storage element other than the first storage element of the scan chain100according to an embodiment. The storage element700may be an example of any of the storage elements1002,1003. . . or100n, in cases where the scan input data ‘sd’ received by the storage element700is pull-down in the functional mode. For instance, the storage element700is utilized when the scan output ‘sq’ (that is coupled to the scan input ‘sd’ of the storage element700) provided by a preceding storage element (of the storage element700) is pull-down in the functional mode (when SCAN is logic 0). For example, when SCAN is logic 0, the scan input ‘sd’ is logic 0.

The storage element700includes a node145coupled to the scan output buffer750for driving the node725(the scan output terminal). In this example embodiment, the node145is also coupled to data output buffer505for driving a data output terminal510. In this embodiment, the data output buffer505is shown as an inverter. The storage element700includes the input circuit460that is configured to receive a data input (see, ‘d’) and a scan input (see, ‘sd’) from a data output ‘q’ and a scan output ‘sq’ of the preceding storage element, respectively. The input circuit460is already described in reference withFIG. 5, and hence its description is not provided for the sake of brevity. The input circuit460is configured to provide a signal corresponding to one of the data input ‘d’ and the scan input ‘sd’, at the node462. For instance, an inverse of the data input is provided at the node462in the shift mode (when SCANZ is logic 1), and an inverse of the scan input ‘sd’ is provided at the node462in the functional mode (when SCANZ is logic 0).

An output (for example, the node462) of the input circuit460is connected to the shifting circuit150that is configured to transfer a signal corresponding to the node462to the node145. The input of the data output buffer505is connected to the node145and the output of the data output buffer505is connected to node510(the data output terminal). The data output buffer505includes an inverter. The scan output buffer750is also connected to the node145. In functional mode, the scan output buffer750is configured to pull-down the node725, however, in the shift mode, the transistors705,710and715form an inverter configuration (and the transistor720is disabled) providing an inverse of the value at the node145to the node725.

The operation of the storage element700is now explained. The input circuit460causes a signal corresponding to one of the data input ‘d’ and the scan input ‘sd’, to be transferred at the node462. It should be noted that in this embodiment, the scan input ‘sd’ is logic 0, when the SCAN is logic 0. For instance, a scan output ‘sq’ of a preceding storage element (such as the storage element200) of the storage element700is pull-down when the SCAN is logic 0, and this pull-down logic 0 is fed to the scan input ‘sd’ of the storage element700. When the SCAN is logic 1, the scan input ‘sd’ may have either of logic 0 or logic 1 depending upon the test data and value as received from the preceding storage element. As illustrated in theFIG. 7, when SCAN is logic 0, an inverse of the data input ‘d’ is transferred at the node462, and when SCAN is logic 1, an inverse of the scan input ‘sd’ is transferred at the node462.

For explanation, in functional mode (when SCAN is logic 0 or SCANZ is logic 1), the scan input ‘sd’ is logic 0, so the transistor475and490are disabled, and the transistors465and480are enabled. Accordingly, the transistors465,470,480and485form an inverter configuration, and an inverted logic level of ‘d’ is transferred to the node462. Assuming that is set to logic 1, then inverse of ‘d’, for example, logic 0 will then be available at the node462. The shifting circuit150is configured to force a logic level at the node145that is the inverse of value at the node462. For example, logic 1 is transferred at the output of inverter110of the shifting circuit145. When CLK is low the transmission gate115becomes transparent and the logic 1 at the input of transmission gets transferred to the node195, forcing the output of the inverter130(node197) to be logic 0. When CLK becomes high the transmission gate125becomes transparent which transfers the value at node197(logic 0) to the inverter120. The inverter120forces logic 1 on the node195. Another transmission gate135in enabled when CLK becomes high and hence transfers the value at the node197(logic 0) to the inverter140. The inverter140forces logic 1 on the node145. The inverter185, the transmission gate190and the inverter146comprise a loop back path when CLK is logic 0 and helps to retain the value at the node145. The data output buffer505(an inverter) inverts the value at the node145and force a logic 0 at the node510. The data output ‘q’ is taken from the node510(that is the data output terminal) as inverse of the data input ‘d’. As SCAN is logic 0, the transistor705is disabled, which stops the data propagation to the node725. At the same time the transistor720is enabled which then pulls-down the node725to logic 0. The scan output terminal is coupled to the node725. Accordingly, in functional mode (when SCAN is logic 0), the scan output ‘sq’ is tied to logic 0 (this may help in power reduction in functional mode due to combinational logic switching in scan path which is driven by the scan output terminal). The scan enable input (SCANZ) acts as a control signal, which decides whether to tie the scan output terminal ‘sq’ to logic 1 or not. Accordingly, when SCAN is logic 0, the data output ‘q’ follows the inverse of the data input ‘d’ and the scan output ‘sq’ is tied to logic 0 (i.e., pull-down).

In shift mode (when SCAN is logic 1 or SCANZ is logic 0), the transistor480is disabled, and the transistors465,475(pull-up) and transistors490(pull-down) form an inverter configuration, and an inverse of the scan input ‘sd’ is transferred to the node462. It should be further be noted that when SCAN is logic 1, the scan output buffer750acts as an inverter, as the transistor720is disabled and the transistors705,710and715form an inverter configuration. The shifting circuit150is configured to force a logic level at the node145that is the inverse of the node462. For instance, if the scan input ‘sd’ is logic 1 (provided the SCAN is logic 1), the node462is at logic 0, and the node145is at logic 1. The scan output buffer750then transfers logic 0 at the node725that is coupled to the scan output ‘sq’. Accordingly, inverse of the scan input ‘sd’ is transferred to the scan output ‘sq’ when the IC operates in the shift mode.

FIG. 8illustrates an example of a storage element other than the first storage element of the scan chain100according to an embodiment. The storage element800may be an example of any of the storage elements1002,1003. . . or100n, in cases where the scan input data ‘sd’ received by the storage element800is pull-up in the functional mode. For instance, the storage element800is utilized when the scan output ‘sq’ (that is coupled to the scan input ‘sd’ of the storage element800) provided by a preceding storage element (of the storage element800) is pull-up in the functional mode (when SCAN is logic 0). For example, when SCAN is logic 0, the scan input ‘sd’ is logic 1.

The storage element800includes the node145that is coupled to a scan output buffer450for driving a node415(scan output terminal). In this example embodiment, the node145is also coupled to data output buffer505for driving a node510(data output terminal). In this embodiment, the data output buffer505is shown as an inverter. The storage element800includes the input circuit360that is configured to receive a data input (see, ‘d’) and a scan input (see, ‘sd’) from a data output ‘q’ and a scan output ‘sq’ of the preceding storage element, respectively. The input circuit360is already described in reference withFIG. 4, and hence its description is not provided for the sake of brevity. The input circuit360is configured to provide a signal corresponding to one of the data input ‘d’ and the scan input ‘sd’, at the node362. For instance, an inverse of the data input ‘d’ is provided at the node362in the shift mode (when SCANZ is logic 1), and an inverse of the scan input ‘sd’ is provided at the node362in the functional mode (when SCANZ is logic 0).

An output (for example, the node362) of the input circuit360is connected to the shifting circuit150that is configured to transfer a signal corresponding to the node362to the node145. The input of the data output buffer505is connected to the node145and the output of the data output buffer505is connected to node510(the data output terminal). The data output buffer505includes an inverter. The scan output buffer450is also connected to the node145. The scan output buffer450includes a PMOS transistor405(fifth MOS transistor) and an NMOS transistor410(sixth MOS transistor) (forming a transmission gate) followed by a pull-down NMOS transistor420(seventh MOS transistor). Drains of the transistors405and410are connected to node145. The sources of the transistors405and410are connected to the node415. The gate of the transistor405is connected to inverted scan enable input (SCANZ). The gate of the transistor410is connected to scan enable input (SCAN). The source of the transistor420(third MOS transistor) is connected to the ground voltage and the drain of the transistor420is connected to node415. The gate of the transistor420is connected to inverted scan enable input (SCANZ) causing the transistor420to act as a pull-down transistor in functional mode (when SCANZ is logic 1). During the functional mode, the transistors405and410are disabled. In the shift mode (when SCANZ is logic 0), the transistor420is disabled; and the transmission gate is enabled and provides the value at the node145to the node415.

The operation of the storage element800is now explained. The input circuit360causes a signal corresponding to one of the data input and the scan input ‘sd’, to be transferred at the node362. It should be noted that the scan input ‘sd’ is logic 1, when the SCAN is logic 0. For instance, a scan output ‘sq’ of a preceding storage element (such as the storage element200) of the storage element800is pull-up when the SCAN is logic 0, and this pull-up logic 1 is fed to the scan input ‘sd’ of the storage element800. When the SCAN is logic 1, the scan input ‘sd’ may have either of logic 0 or logic 1 depending upon the test data and value as received from the preceding storage element. As described in reference toFIG. 4, when SCAN is logic 0, an inverse of the data input ‘d’ is transferred at the node362, and when SCAN is logic 1, an inverse of the scan input ‘sd’ is transferred at the node362.

For explanation, if SCAN is logic 0 (scan input ‘sd’ is logic 1), the transistor375and380are disabled, and the transistors370and385are enabled. Accordingly, the transistors365,370,390and385form an inverter configuration, and an inverted logic level of ‘d’ is transferred to the node362. Assuming that ‘d’ is set to logic 1, then inverse of ‘d’, for example, logic 0 will then be available at the node362. The shifting circuit150is configured to force a logic level at the node145that is the inverse of the value at the node362. For example, output of inverter110of the shifting circuit145is logic 1. When CLK is low the transmission gate115becomes transparent and the logic 1 at the input of transmission gets transferred to the node195, forcing the output of the inverter130(node197) to be logic 0. When CLK becomes high the transmission gate125becomes transparent which transfers the value at the node197(logic 0) to the inverter120. The inverter120forces logic 1 on the node195. Another transmission gate135in enabled when CLK becomes high and hence transfers the value at the node197(logic 0) to the inverter140. The inverter140forces logic 1 on the node145. The inverter185, the transmission gate190and the inverter146comprise a loop back path when CLK is logic 0 and helps to retain the value at the node145. The data output buffer505(an inverter) inverts the value at the node145and force a logic 0 at the node510. The data output ‘q’ is taken from the node510(that is the data output terminal) as inverse of the data input ‘d’. As SCAN is logic 0, the transmission gate formed by the transistors405and410isolates the node415from the node145. At the same time the transistor420is enabled which then pulls-down the node415to logic 0 irrespective of the clock signal CLK in functional mode. The scan output terminal is coupled to the node415. Accordingly, in the functional mode (when SCAN is logic 0), the scan output ‘sq’ is tied to logic 0 (this may help in power reduction in the functional mode due to combinational logic switching in scan path which is driven by the scan output terminal). The scan enable input (SCANZ) acts as a control signal, which decides whether to tie the scan output terminal ‘sq’ to logic 1 or not. Accordingly, when SCAN is logic 0, the data output ‘q’ follows the inverse of the data input ‘d’ and the scan output ‘sq’ is tied to logic 0 (i.e., pull-down).

When SCAN is logic 1, the transistor370is disabled, and the transistor375(pull-up) and transistors380and385(pull-down) form an inverter configuration, and an inverse of the scan input ‘sd’ is transferred to the node362. It should be further be noted that when SCAN is logic 1, the scan output buffer450acts as a transmission gate buffer, as the transistor420is disabled and the transmission gate formed by the transistors405and410transfers the value present at the node145to the node415. The shifting circuit150is configured to force a logic level at the node145that is the inverse of the node362. For instance, if the scan input ‘sd’ is logic 1 (provided the SCAN is logic 1), the node362is at logic 0, and the node145is at logic 1. The scan output buffer450then transfers logic 1 at the node415that is coupled to the scan output ‘sq’. Accordingly, the scan input ‘sd’ is transferred to the scan output ‘sq’ when the IC operates in the shift mode.

FIG. 9illustrates an example of a storage element other than the first storage element of the scan chain100according to an embodiment. The storage element900may be an example of any of the storage elements1002,1003. . . or100n, in cases where the scan input data ‘sd’ received by the storage element900is pull-down in the functional mode. For instance, the storage element900is utilized when the scan output ‘sq’ (that is coupled to the scan input ‘sd’ of the storage element900) provided by a preceding storage element (of the storage element900) is pull-down in the functional mode (when SCAN is logic 0). For example, when SCAN is logic 0, the scan input ‘sd’ is logic 1.

The storage element900includes the node145that is coupled to the scan output buffer450for driving the node415(scan output terminal). In this example embodiment, the node145is also coupled to the data output buffer505for driving the node510(data output terminal). In this embodiment, the data output buffer505is shown as an inverter. The storage element700includes the input circuit460that is configured to receive a data input (see, ‘d’) and a scan input (see, ‘sd’) from a data output and a scan output ‘sq’ of the preceding storage element, respectively. The input circuit460is already described in reference withFIG. 5, and hence its description is not provided for the sake of brevity. The input circuit460is configured to provide a signal corresponding to one of the data input ‘d’ and the scan input ‘sd’, at the node462. For instance, an inverse of the data input is provided at the node462in the functional mode (when SCANZ is logic 1), and an inverse of the scan input ‘sd’ is provided at the node462in the shift mode (when SCANZ is logic 0).

An output (for example, the node462) of the input circuit460is connected to the shifting circuit150that is configured to transfer a signal corresponding to the node462to the node145. The input of the data output buffer505is connected to the node145and the output of the data output buffer505is connected to node510(the data output terminal). The data output buffer505includes an inverter. The scan output buffer450is also connected to the node145. As described in reference toFIG. 8, the scan output buffer450includes the PMOS transistor405(first MOS transistor) and the NMOS transistor410(second MOS transistor) (forming a transmission gate) followed by the pull-down NMOS transistor420. The transistor420to act as a pull-down transistor in functional mode (when SCANZ is logic 1), as the transistors405and410are disabled in the functional mode. In the shift mode (when SCANZ is logic 0), the transistor420is disabled; and the transmission gate is enabled and provides the value at the node145to the node415.

The operation of the storage element900is now explained. The input circuit460causes a signal corresponding to one of the data input ‘d’ and the scan input ‘sd’, to be transferred at the node462. It should be noted that the scan input ‘sd’ is logic 0, when the SCAN is logic 0. For instance, a scan output ‘sq’ of a preceding storage element (such as the storage element200) of the storage element900is pull-down when the SCAN is logic 0, and this pull-down logic 0 is fed to the scan input ‘sd’ of the storage element900. When the SCAN is logic 1, the scan input ‘sd’ may have either of logic 0 or logic 1 depending upon the test data and value as received from the preceding storage element. As described in reference toFIG. 5, when SCAN is logic 0, an inverse of the data input ‘d’ is transferred at the node462, and when SCAN is logic 1, an inverse of the scan input ‘sd’ is transferred at the node462.

In functional mode (when SCAN is logic 0 or SCANZ is logic 1), the scan input ‘sd’ is logic 0, so the transistor475and490are disabled, and the transistors465and480are enabled. Accordingly, the transistors465,470,480and485form an inverter configuration, and an inverted logic level of ‘d’ is transferred to the node462. Assuming that ‘d’ is set to logic 1, then inverse of ‘d’, for example, logic 0 will then be available at the node462. The shifting circuit150is configured to force a logic level at the node145that is the inverse of value at the node462. For example, logic 1 is transferred at the output of inverter110of the shifting circuit145. When CLK is low the transmission gate115becomes transparent and the logic 1 at the input of transmission gets transferred to the node195, forcing the output of the inverter130(node197) to be logic 0. When CLK becomes high the transmission gate125becomes transparent which transfers the value at the node197(logic 0) to the inverter120. The inverter120forces logic 1 on the node195. Another transmission gate135in enabled when CLK becomes high and hence transfers the value at the node197(logic 0) to the inverter140. The inverter140forces logic 1 on the node145. The inverter185, the transmission gate190and the inverter146comprise a loop back path when CLK is logic 0 and helps to retain the value at the node145. The data output buffer505(an inverter) inverts the value at the node145and force a logic 0 at the node510. The data output ‘q’ is taken from the node510(that is the data output terminal) as inverse of the data input ‘d’. As SCAN is logic 0, the transmission gate formed by the transistors405and410isolates the node415from node145. At the same time the transistor420is enabled which then pulls-down the node415to logic 0 irrespective of the clock signal CLK in functional mode. The scan output terminal is coupled to the node415. Accordingly, in the functional mode (when SCAN is logic 0), the scan output ‘sq’ is tied to logic 0 (this may help in power reduction in the functional mode due to combinational logic switching in scan path which is driven by the scan output terminal). The scan enable input (SCANZ) acts as a control signal, which decides whether to tie the scan output terminal ‘sq’ to logic 1 or not. Accordingly, when SCAN is logic 0, the data output ‘q’ follows the inverse of the data input ‘d’ and the scan output ‘sq’ is tied to logic 0 (i.e., pull-down).

In shift mode (when SCAN is logic 1 or SCANZ is logic 0), the transistor480is disabled, and the transistors465,475(pull-up) and transistors490(pull-down) form an inverter configuration, and an inverse of the scan input ‘sd’ is transferred to the node462. It should be further be noted that when SCAN is logic 1, the scan output buffer450acts as a transmission gate buffer, as the transistor420is disabled and the transmission gate formed by the transistors405and410transfers the value present at the node145to the node415. The shifting circuit150is configured to force a logic level at the node145that is the inverse of the node462. For instance, if the scan input ‘sd’ is logic 1 (provided the SCAN is logic 1), the node462is at logic 0, and the node145is at logic 1. The scan output buffer450then transfers logic 1 at the node415that is coupled to the scan output ‘sq’. Accordingly, the scan input ‘sd’ is transferred to the scan output ‘sq’ when the IC operates in the shift mode.

Various embodiment of the present technology also provide pull-up and/or pull-down of both of the data output and the scan output, and these embodiments are further described in reference toFIGS. 10 to 21. For instance, in functional mode, the scan output ‘sq’ may be pull-up or pull-down, and in the shift mode, the data output ‘d’ may be pull-up or pull-down, thereby saving a greater power in the IC during these modes.

FIG. 10illustrates an example of a storage element other than the first storage element of the scan chain100according to an embodiment. The storage element1000may be an example of any of the storage elements1002,1003. . . or 100nin cases where the scan input data ‘sd’ received by the storage element1000is pull-up in the functional mode. For instance, the storage element1000is utilized when the scan output ‘sq’ (that is coupled to the scan input ‘sd’ of the storage element1000) provided by a preceding storage element (of the storage element1000) is pull-up in the functional mode (when SCAN is logic 0). For example, when SCAN is logic 0, the scan input ‘sd’ is logic 1.

The storage element1000includes a node145coupled to a scan output buffer550for driving a node535(scan output terminal). In this example embodiment, the node145is also coupled to a data output buffer250for driving a node225(data output terminal). The storage element1000includes the input circuit360that is configured to receive a data input (see, ‘d’) and a scan input (see, ‘sd’) from a data output ‘q’ and a scan output ‘sq’ of the preceding storage element, respectively. The input circuit360is already described in reference with theFIG. 4, and hence its description is not provided for the sake of brevity. The input circuit360is configured to provide a signal corresponding to one of the data input ‘d’ and the scan input ‘sd’, at the node362. For instance, an inverse of the data input ‘d’ is provided at the node362in the shift mode (when SCAN is logic 1), and an inverse of the scan input ‘sd’ is provided at the node362in the functional mode (when SCANZ is logic 0).

An output (for example, the node362) of the input circuit360is connected to the shifting circuit150that is configured to transfer a signal corresponding to the node362to the node145. The input of the data output buffer250is connected to the node145and the output of the data output buffer250is connected to the node225(the data output terminal). The data output buffer250includes a PMOS transistor205and an NMOS transistor210. The source of the transistor205is connected to power supply voltage and the drain of the transistor205is connected to the node225. The gate of transistor205is connected to node145. The source of the transistor210is connected to the drain of another NMOS transistor215(eighth MOS transistor) and the drain of the transistor210is connected to the node225. The gate of transistor210is also connected to the node145. The source of the transistor215is connected to the ground voltage and the drain of the transistor215is connected to the source of the transistor210. The gate of transistor215is connected to inverted scan enable input (SCANZ). The transistor215is used to disable VDD to VSS direct path when SCAN is 1. Another PMOS transistor220(ninth MOS transistor) is used to pull-up the data output terminal q. The source of the transistor220is connected to the supply voltage and drain of the transistor220is connected to the node225(data output terminal q). The gate of the transistor220is connected to inverted scan enable input (SCANZ). Data output (q) of the storage element1000is taken from the node225. The scan output buffer550is also connected to the node145. In functional mode, the scan output buffer550is configured to pull-up the node550. In the shift mode, the transistors515,520and525form an inverter configuration (and the transistor530is disabled) providing an inverse of the value at the node145to the node535.

The operation of the storage element1000is now explained. The input circuit360causes a signal corresponding to one of the data input ‘d’ and the scan input ‘sd’, to be transferred at the node362. It should be noted that the scan input ‘sd’ is logic 1, when the SCAN is logic 0. For instance, a scan output ‘sq’ of a preceding storage element (such as the storage element200) of the storage element1000is pull-up when the SCAN is logic 0, and this pull-up logic 1 is fed to the scan input ‘sd’ of the storage element1000. When the SCAN is logic 1, the scan input ‘sd’ may have either of logic 0 or logic 1 depending upon the test data and value as received from the preceding storage element. As described in reference toFIG. 4, when SCAN is logic 0, an inverse of the data input ‘d’ is transferred at the node362, and when SCAN is logic 1, an inverse of the scan input ‘sd’ is transferred at the node362.

In functional mode (when SCAN is logic 0 or SCANZ is logic 1), the scan input ‘sd’ is logic 1, so the transistor375and380are disabled, and the transistors370and385are enabled. Accordingly, the transistors365,370,390and385form an inverter configuration, and an inverted logic level of ‘d’ is transferred to the node362. Assuming that is set to logic 1, then inverse of ‘d’, for example, logic 0 will then be available at the node362. The shifting circuit150is configured to force a logic level at the node145that is the inverse of the value at the node362. For example, output of inverter110of the shifting circuit145is logic 1. When CLK is low the transmission gate115becomes transparent and the logic 1 at the input of transmission gets transferred to the node195, forcing the output of the inverter130(node197) to be logic 0. When CLK becomes high the transmission gate125becomes transparent which transfers the value at the node197(logic 0) to the inverter120. The inverter120forces logic 1 on the node195. Another transmission gate135in enabled when CLK becomes high and hence transfers the value at the node197(logic 0) to the inverter140. The inverter140forces logic 1 on the node145. The inverter185, the transmission gate190and the inverter146comprise a loop back path when CLK is logic 0 and helps to retain the value at the node145. The data output buffer250inverts the value at the node145and forces a logic 0 at the node225. As SCAN is logic 0, the transistor220is disabled, and the transistors205,210and215form an inverter configuration, thereby transferring the inverted value of the node145(for example, a logic 0) at the node225. The data output ‘q’ is taken from the node225(that is the data output terminal) as inverse of the data input ‘d’. As SCAN is logic 0, the transistor525is disabled, which stops the data propagation to the node535. At the same time the transistor530is enabled which then pulls up the node535to logic 1. The scan output terminal is coupled to the node535. Accordingly, in functional mode (when SCAN is logic 0), the scan output ‘sq’ is tied to logic 1 (this may help in power reduction in functional mode due to combinational logic switching in scan path which is driven by the scan output terminal). The scan enable input (SCAN) acts as a control signal, which decides whether to tie the scan output terminal ‘sq’ to logic 1 or not. Accordingly, when SCAN is logic 0, the data output ‘q’ follows the inverse of the data input ‘d’ and the scan output ‘sq’ is tied to logic 1.

In shift mode (when SCAN is logic 1 or SCANZ is logic 0), the transistor370is disabled, and the transistor375(pull-up) and transistors380and385(pull-down) form an inverter configuration, and an inverse of the scan input ‘sd’ is transferred to the node362. It should be further be noted that when SCAN is logic 1, the scan output buffer550acts as an inverter, as the transistor530is disabled and the transistors515,520and525form an inverter configuration. The shifting circuit150is configured to force a logic level at the node145that is the inverse of the node362. For instance, if the scan input ‘sd’ is logic 1 (provided the SCAN is logic 1), the node362is at logic 0, and the node145is at logic 1. The scan output buffer550then transfers logic 0 at the node535that is coupled to the scan output ‘sq’. Accordingly, inverted scan input ‘sd’ is transferred to the scan output ‘sq’ when the device operates in the shift mode. As SCAN is logic 1, the transistor215is disabled causing disabling the inverter comprised by transistors205and210. The transistor220is enabled and pulls-up the node225(the data output terminal q) in response to SCANZ being logic 0. It is noted that transistor215is configured to protect leakage current through the inverter (formed by the transistors205and210) when the data output terminal (the node225) is pull-up.

In shift mode, the data output ‘q’ is tied to logic 1 (this will help in power reduction in shift mode due to combinational logic switching which is driven by data output terminal). The scan enable input (SCAN) acts as a control signal, which decides whether to tie the data output terminal ‘q’ to logic 1 or not. When SCAN is 0, the data output ‘q’ follows the inversion of the data input ‘d’ and the scan output ‘sq’ is tied to logic 1. When SCAN is logic 1, the data output q is tied to logic 1 and the scan output ‘sq’ follows the inversion of scan input (sd). According to this embodiment, average power over a number of ATPG shift cycles comes down as all the functional combinational logic does not toggle due to Q gating. Instantaneous peak power over the first shift cycle can be optimized by correctly choosing the type of flop for each logic block (pull-up or pull-down). This technique is extremely useful in case designers decide to convert only a subset of existing scan flops to this new design as then the peak/average power will depend upon the selection of “pull-up” or “pull-down” Q gating.

FIG. 11illustrates an example of a storage element other than the first storage element of the scan chain100according to an embodiment. The storage element1100may be an example of any of the storage elements1002,1003. . . or100n, in cases where the scan input data ‘sd’ received by the storage element1100is pull-up in the functional mode. For instance, the storage element1100is utilized when the scan output ‘sq’ (that is coupled to the scan input ‘sd’ of the storage element1100) provided by a preceding storage element (of the storage element1100) is pull-up in the functional mode (when SCAN is logic 0). For example, when SCAN is logic 0, the scan input ‘sd’ is logic 1.

The storage element1100includes a node145coupled to a scan output buffer550for driving a node535(scan output terminal). In this example embodiment, the node145is also coupled to a data output buffer650for driving a node625(data output terminal). The storage element1100includes the input circuit360that is configured to receive a data input (see, V) and a scan input (see, ‘sd’) from a data output ‘q’ and a scan output ‘sq’ of the preceding storage element, respectively. The input circuit360is configured to provide a signal corresponding to one of the data input ‘d’ and the scan input ‘sd’, at the node362. For instance, an inverse of the data input is provided at the node362in the shift mode (when SCAN is logic 1), and an inverse of the scan input ‘sd’ is provided at the node362in the functional mode (when SCANZ is logic 0).

An output (for example, the node362) of the input circuit360is connected to the shifting circuit150that is configured to transfer a signal corresponding to the node362to the node145. The input of the data output buffer650is connected to the node145and the output of the data output buffer650is connected to the node625(the data output terminal). The data output buffer650also includes a PMOS transistor610and an NMOS transistor615. The source of the transistor610is connected to the drain of another PMOS transistor605(sixteenth MOS transistor) and the drain of the transistor610is connected to the node625. The gate of the transistor610is connected to node145. The source of the transistor620is connected to the ground voltage and the drain of the transistor620is connected to the node625. The gate of transistor620is also connected to node145. The source of the transistor605is connected to the power supply voltage and the drain of the transistor605is connected to the source of the transistor610. The gate of transistor605is connected to the scan enable input (SCAN). Transistor605is used to disable the direct path between VDD and VSS when SCAN is 1. Another NMOS transistor620(sixteenth MOS transistor) is used to pull-down the node625(the data output terminal). The source of the transistor620is connected to the ground voltage and drain of the transistor620is connected to the node625. The gate of the transistor620is connected to SCAN. Data output (q) of the scannable storage element1100is taken from node625. The scan output buffer550is also connected to the node145. In functional mode, the scan output buffer550is configured to pull-up the node550. In the shift mode, the transistors515,520and525form an inverter configuration (and the transistor530is disabled) providing an inverse of the value of the node145to the node535.

The operation of the storage element1100is now explained. The input circuit360causes a signal corresponding to one of the data input ‘d’ and the scan input ‘sd’, to be transferred at the node362. It should be noted that the scan input ‘sd’ is logic 1, when the SCAN is logic 0. For instance, a scan output ‘sq’ of a preceding storage element (such as the storage element200) of the storage element1100is pull-up when the SCAN is logic 0, and this pull-up logic 1 is fed to the scan input ‘sd’ of the storage element1100. When the SCAN is logic 1, the scan input ‘sd’ may have either of logic 0 or logic 1 depending upon the test data and value as received from the preceding storage element. As described in reference toFIG. 4, when SCAN is logic 0, an inverse of the data input ‘d’ is transferred at the node362, and when SCAN is logic 1, an inverse of the scan input ‘sd’ is transferred at the node362.

In functional mode (when SCAN is logic 0 or SCANZ is logic 1), the scan input ‘sd’ is logic 1, so the transistor375and380are disabled, and the transistors370and385are enabled. Accordingly, the transistors365,370,390and385form an inverter configuration, and an inverted logic level of ‘d’ is transferred to the node362. Assuming that is set to logic 1, then inverse of ‘d’, for example, logic 0 will then be available at the node362. The shifting circuit150is configured to force a logic level at the node145that is the inverse of the value at the node362. For example, output of inverter110of the shifting circuit145is logic 1. When CLK is low the transmission gate115becomes transparent and the logic 1 at the input of transmission gets transferred to the node195, forcing the output of the inverter130(node197) to be logic 0. When CLK becomes high the transmission gate125becomes transparent which transfers the value at the node197(logic 0) to the inverter120. The inverter120forces logic 1 on the node195. Another transmission gate135in enabled when CLK becomes high and hence transfers the value at the node197(logic 0) to the inverter140. The inverter140forces logic 1 on the node145. The inverter185, the transmission gate190and the inverter146comprise a loop back path when CLK is logic 0 and helps to retain the value at the node145. The data output buffer650inverts the value at the node145and forces a logic 0 at the node625. As SCAN is logic 0, the transistor620is disabled, and the transistors605,610and615form an inverter configuration, thereby transferring the inverted value of the node145(for example, a logic 0) at the node625. The data output ‘q’ is taken from the node625(that is the data output terminal) as inverse of the data input ‘d’. As SCAN is logic 0, the transistor525is disabled, which stops the data propagation to the node535. At the same time the transistor530is enabled which then pulls up the node535to logic 1. The scan output terminal is coupled to the node535. Accordingly, in functional mode (when SCAN is logic 0), the scan output ‘sq’ is tied to logic 1 (this may help in power reduction in functional mode due to combinational logic switching in scan path which is driven by the scan output terminal). The scan enable input (SCAN) acts as a control signal, which decides whether to tie the scan output terminal ‘sq’ to logic 1 or not. Accordingly, when SCAN is logic 0, the data output ‘q’ follows the inverse of the data input ‘d’ and the scan output ‘sq’ is tied to logic 1.

In shift mode (when SCAN is logic 1 or SCANZ is logic 0), the transistor370is disabled, and the transistor375(pull-up) and transistors380and385(pull-down) form an inverter configuration, and an inverse of the scan input ‘sd’ is transferred to the node362. It should be further be noted that when SCAN is logic 1, the scan output buffer550acts as an inverter, as the transistor530is disabled and the transistors515,520and525form an inverter configuration. The shifting circuit150is configured to force a logic level at the node145that is the inverse of the node362. For instance, if the scan input ‘sd’ is logic 1 (provided the SCAN is logic 1), the node362is at logic 0, and the node145is at logic 1. The scan output buffer550then transfers logic 0 at the node535that is coupled to the scan output ‘sq’. Accordingly, inverted scan input ‘sd’ is transferred to the scan output ‘sq’ when the device operates in the shift mode. As SCAN is logic 1, the transistor605is disabled causing disabling the inverter comprised by transistors605and610. The transistor620is enabled and pulls down the node625(the data output terminal q) in response to SCAN. It is noted that transistor605is configured to protect leakage current through the inverter (formed by the transistors610and615) when the data output terminal625is pull-down.

In shift mode, the data output ‘q’ is tied to logic 0 (this will help in power reduction in shift mode due to combinational logic switching which is driven by data output terminal). The scan enable input (SCAN) acts as a control signal, which decides whether to tie the data output terminal ‘q’ to logical or not. When SCAN is 0, the data output ‘q’ follows the inversion of the data input and the scan output ‘sq’ is tied to logic 1. When SCAN is logic 1, the data output q is tied to logic 0 and the scan output ‘sq’ follows the inversion of scan input (sd). According to this embodiment, average power over a number of ATPG shift cycles comes down as all the functional combinational logic does not toggle due to Q gating. Instantaneous peak power over the first shift cycle can be optimized by correctly choosing the type of flop for each logic block (pull-up or pull-down). This technique is extremely useful in case designers decide to convert only a subset of existing scan flops to this new design as then the peak/average power will depend upon the selection of “pull-up” or “pull-down” Q gating.

FIG. 12illustrates an example of a storage element other than the first storage element of the scan chain100according to an embodiment. The storage element1200may be an example of any of the storage elements1002,1003. . . or100n, in cases where the scan input data ‘sd’ received by the storage element1200is pull-down in the functional mode. For instance, the storage element1200is utilized when the scan output ‘sq’ (that is coupled to the scan input ‘sd’ of the storage element1200) provided by a preceding storage element (of the storage element1200) is pull-down in the functional mode (when SCAN is logic 0). For example, when SCAN is logic 0, the scan input ‘sd’ is logic 1.

The storage element1200includes a node145coupled to a scan output buffer550for driving a node535(scan output terminal). In this example embodiment, the node145is also coupled to a data output buffer250for driving a node225(data output terminal). The storage element1200includes the input circuit460that is configured to receive a data input (see, ‘d’) and a scan input (see, ‘sd’) from a data output ‘q’ and a scan output ‘sq’ of the preceding storage element, respectively. The input circuit460is configured to provide a signal corresponding to one of the data input ‘d’ and the scan input ‘sd’, at the node462. For instance, an inverse of the data input ‘d’ is provided at the node462in the shift mode (when SCANZ is logic 1), and an inverse of the scan input ‘sd’ is provided at the node462in the functional mode (when SCANZ is logic 0).

An output (for example, the node462) of the input circuit460is connected to the shifting circuit150that is configured to transfer a signal corresponding to the node462to the node145. The input of the data output buffer250is connected to the node145and the output of the data output buffer250is connected to the node225(the data output terminal). Data output (q) of the storage element1200is taken from the node225. The scan output buffer550is also connected to the node145. In functional mode, the scan output buffer550is configured to pull-up the node535. In the shift mode, the transistors515,520and525form an inverter configuration (and the transistor530is disabled) providing an inverse of the value of the node145to the node535.

The operation of the storage element1200is now explained. The input circuit460causes a signal corresponding to one of the data input ‘d’ and the scan input ‘sd’, to be transferred at the node462. It should be noted that in this embodiment, the scan input ‘sd’ is logic 0, when the SCAN is logic 0. For instance, a scan output ‘sq’ of a preceding storage element (such as the storage element300) of the storage element1200is pull-down when the SCAN is logic 0, and this pull-down logic 0 is fed to the scan input ‘sd’ of the storage element1200. When the SCAN is logic 1, the scan input ‘sd’ may have either of logic 0 or logic 1 depending upon the test data and value as received from the preceding storage element. As illustrated in theFIG. 12, when SCAN is logic 0, an inverse of the data input ‘d’ is transferred at the node462, and when SCAN is logic 1, an inverse of the scan input ‘sd’ is transferred at the node462.

In functional mode (when SCAN is logic 0 or SCANZ is logic 1), the scan input ‘sd’ is logic 0, so the transistor475and490are disabled, and the transistors465and480are enabled. Accordingly, the transistors465,470,480and485form an inverter configuration, and an inverted logic level of ‘d’ is transferred to the node462. Assuming that ‘d’ is set to logic 1, then inverse of ‘d’, for example, logic 0 will then be available at the node462. The shifting circuit150is configured to force a logic level at the node145that is the inverse of value at the node462. For example, logic 1 is transferred at the output of inverter120of the shifting circuit145. When CLK is low the transmission gate125becomes transparent and the logic 1 at the input of transmission gets transferred to the node195, forcing the output of the inverter130(node197) to be logic 0. When CLK becomes high the transmission gate125becomes transparent which transfers the value at the node197(logic 0) to the inverter120. The inverter120forces logic 1 on the node195. Another transmission gate135in enabled when CLK becomes high and hence transfers the value at the node197(logic 0) to the inverter140. The inverter140forces logic 1 on the node145. The inverter185, the transmission gate190and the inverter146comprise a loop back path when CLK is logic 0 and helps to retain the value at the node145. The data output buffer250inverts the value at the node145and forces a logic 0 at the node225. As SCAN is logic 0, the transistor220is disabled, and the transistors205,210and215form an inverter configuration, thereby transferring the inverted value of the node145(for example, a logic 0) at the node225. The data output ‘q’ is taken from the node225(that is the data output terminal) as inverse of the data input ‘d’. As SCAN is logic 0, the transistor525is disabled, which stops the data propagation to the node535. At the same time the transistor530is enabled which then pulls up the node535to logic 1. The scan output terminal is coupled to the node535. Accordingly, in functional mode (when SCAN is logic 0), the scan output ‘sq’ is tied to logic 1 (this may help in power reduction in functional mode due to combinational logic switching in scan path which is driven by the scan output terminal). The scan enable input (SCAN) acts as a control signal, which decides whether to tie the scan output terminal ‘sq’ to logic 1 or not. Accordingly, when SCAN is logic 0, the data output ‘q’ follows the inverse of the data input ‘d’ and the scan output ‘sq’ is tied to logic 1.

In shift mode (when SCAN is logic 1 or SCANZ is logic 0), the transistor480is disabled, and the transistors465,475(pull-up) and transistors490(pull-down) form an inverter configuration, and an inverse of the scan input ‘sd’ is transferred to the node462. It should be further be noted that when SCAN is logic 1, the scan output buffer550acts as an inverter, as the transistor530is disabled and the transistors515,520and525form an inverter configuration. The shifting circuit150is configured to force a logic level at the node145that is the inverse of the node462. For instance, if the scan input ‘sd’ is logic 1 (provided the SCAN is logic 1), the node462is at logic 0, and the node145is at logic 1. The scan output buffer550then transfers logic 0 at the node535that is coupled to the scan output ‘sq’. Accordingly, inverted scan input ‘sd’ is transferred to the scan output ‘sq’ when the device operates in the shift mode. As SCAN is logic 1, the transistor215is disabled causing disabling the inverter comprised by transistors205and210. The transistor220is enabled and pulls-up the node225(the data output terminal q) in response to SCANZ being logic 0. It is noted that transistor215is configured to protect leakage current through the inverter (formed by the transistors205and210) when the data output terminal (the node225) is pull-up.

In shift mode, the data output ‘q’ is tied to logic 1 (this will help in power reduction in shift mode due to combinational logic switching which is driven by data output terminal). The scan enable input (SCAN) acts as a control signal, which decides whether to tie the data output terminal ‘q’ to logic1 or not. When SCAN is 0, the data output ‘q’ follows the inversion of the data input and the scan output ‘sq’ is tied to logic 1. When SCAN is logic 1, the data output q is tied to logic 1 and the scan output ‘sq’ follows the inversion of scan input (sd). According to this embodiment, average power over a number of ATPG shift cycles comes down as all the functional combinational logic does not toggle due to Q gating. Instantaneous peak power over the first shift cycle can be optimized by correctly choosing the type of flop for each logic block (pull-up or pull-down). This technique is extremely useful in case designers decide to convert only a subset of existing scan flops to this new design as then the peak/average power will depend upon the selection of “pull-up” or “pull-down” Q gating.

FIG. 13illustrates an example of a storage element other than the first storage element of the scan chain100according to an embodiment. The storage element1300may be an example of any of the storage elements1002,1003. . . or100n, in cases where the scan input data ‘sd’ received by the storage element1300is pull-down in the functional mode. For instance, the storage element1300is utilized when the scan output ‘sq’ (that is coupled to the scan input ‘sd’ of the storage element1300) provided by a preceding storage element (of the storage element1300) is pull-down in the functional mode (when SCAN is logic 0). For example, when SCAN is logic 0, the scan input ‘sd’ is logic 1.

The storage element1300includes a node145coupled to a scan output buffer550for driving a node535(scan output terminal). In this example embodiment, the node145is also coupled to the data output buffer650for driving the node625(data output terminal). The storage element1300includes the input circuit460that is configured to receive a data input (see, ‘d’) and a scan input (see, ‘sd’) from a data output ‘q’ and a scan output ‘sq’ of the preceding storage element, respectively. The input circuit460is configured to provide a signal corresponding to one of the data input ‘d’ and the scan input ‘sd’, at the node462. For instance, an inverse of the data input is provided at the node462in the shift mode (when SCANZ is logic 1), and an inverse of the scan input ‘sd’ is provided at the node462in the functional mode (when SCANZ is logic 0).

An output (for example, the node462) of the input circuit460is connected to the shifting circuit150that is configured to transfer a signal corresponding to the node462to the node145. The input of the data output buffer650is connected to the node145and the output of the data output buffer650is connected to the node625(the data output terminal). Data output (q) of the storage element1300is taken from the node625. The scan output buffer550is also connected to the node145. In functional mode, the scan output buffer550is configured to pull-up the node550. In the shift mode, the transistors515,520and525form an inverter configuration (and the transistor530is disabled) providing an inverse of the value of the node145to the node535.

The operation of the storage element1300is now explained. The input circuit460causes a signal corresponding to one of the data input ‘d’ and the scan input ‘sd’, to be transferred at the node462. It should be noted that in this embodiment, the scan input ‘sd’ is logic 0, when the SCAN is logic 0. For instance, a scan output ‘sq’ of a preceding storage element (such as the storage element300) of the storage element1300is pull-down when the SCAN is logic 0, and this pull-down logic 0 is fed to the scan input ‘sd’ of the storage element1300. When the SCAN is logic 1, the scan input ‘sd’ may have either of logic 0 or logic 1 depending upon the test data and value as received from the preceding storage element. As illustrated in theFIG. 13, when SCAN is logic 0, an inverse of the data input ‘d’ is transferred at the node462, and when SCAN is logic 1, an inverse of the scan input ‘sd’ is transferred at the node462.

In functional mode (when SCAN is logic 0 or SCANZ is logic 1), the scan input ‘sd’ is logic 0, so the transistor475and490are disabled, and the transistors465and480are enabled. Accordingly, the transistors465,470,480and485form an inverter configuration, and an inverted logic level of ‘d’ is transferred to the node462. Assuming that ‘d’ is set to logic 1, then inverse of ‘d’, for example, logic 0 will then be available at the node462. The shifting circuit150is configured to force a logic level at the node145that is the inverse of value at the node462. For example, logic 1 is transferred at the output of inverter130of the shifting circuit145. When CLK is low the transmission gate135becomes transparent and the logic 1 at the input of transmission gets transferred to the node195, forcing the output of the inverter130(node197) to be logic 0. When CLK becomes high the transmission gate135becomes transparent which transfers the value at the node197(logic 0) to the inverter130. The inverter130forces logic 1 on the node195. Another transmission gate135in enabled when CLK becomes high and hence transfers the value at the node197(logic 0) to the inverter140. The inverter140forces logic 1 on the node145. The inverter185, the transmission gate190and the inverter146comprise a loop back path when CLK is logic 0 and helps to retain the value at the node145. The data output buffer650inverts the value at the node145and forces a logic 0 at the node625. As SCAN is logic 0, the transistor620is disabled, and the transistors605,610and615form an inverter configuration, thereby transferring the inverted value of the node145(for example, a logic 0) at the node625. The data output ‘q’ is taken from the node625(that is the data output terminal) as inverse of the data input ‘d’. As SCAN is logic 0, the transistor525is disabled, which stops the data propagation to the node535. At the same time the transistor530is enabled which then pulls up the node535to logic 1. The scan output terminal is coupled to the node535. Accordingly, in functional mode (when SCAN is logic 0), the scan output ‘sq’ is tied to logic 1 (this may help in power reduction in functional mode due to combinational logic switching in scan path which is driven by the scan output terminal). The scan enable input (SCAN) acts as a control signal, which decides whether to tie the scan output terminal ‘sq’ to logic 1 or not. Accordingly, when SCAN is logic 0, the data output ‘q’ follows the inverse of the data input and the scan output ‘sq’ is tied to logic 1.

In shift mode (when SCAN is logic 1 or SCANZ is logic 0), the transistor480is disabled, and the transistors465,475(pull-up) and transistors490(pull-down) form an inverter configuration, and an inverse of the scan input ‘sd’ is transferred to the node462. It should be further be noted that when SCAN is logic 1, the scan output buffer550acts as an inverter, as the transistor530is disabled and the transistors515,520and525form an inverter configuration. The shifting circuit150is configured to force a logic level at the node145that is the inverse of the node462. For instance, if the scan input ‘sd’ is logic 1 (provided the SCAN is logic 1), the node462is at logic 0, and the node145is at logic 1. The scan output buffer550then transfers logic 0 at the node535that is coupled to the scan output ‘sq’. Accordingly, inverted scan input ‘sd’ is transferred to the scan output ‘sq’ when the device operates in the shift mode. As SCAN is logic 1, the transistor605is disabled causing disabling the inverter comprised by transistors605and610. The transistor620is enabled and pulls down the node625(the data output terminal q) in response to SCAN. It is noted that transistor605is configured to protect leakage current through the inverter (formed by the transistors610and615) when the data output terminal is pull-down.

In shift mode, the data output ‘q’ is tied to logic 0 (this will help in power reduction in shift mode due to combinational logic switching which is driven by data output terminal). The scan enable input (SCAN) acts as a control signal, which decides whether to tie the data output terminal ‘q’ to logic1 or not. When SCAN is 0, the data output ‘q’ follows the inversion of the data input ‘d’ and the scan output ‘sq’ is tied to logic 1. When SCAN is logic 1, the data output q is tied to logic 0 and the scan output ‘sq’ follows the inversion of scan input (sd). According to this embodiment, average power over a number of ATPG shift cycles comes down as all the functional combinational logic does not toggle due to Q gating. Instantaneous peak power over the first shift cycle can be optimized by correctly choosing the type of flop for each logic block (pull-up or pull-down). This technique is extremely useful in case designers decide to convert only a subset of existing scan flops to this new design as then the peak/average power will depend upon the selection of “pull-up” or “pull-down” Q gating.

FIG. 14illustrates an example of a storage element other than the first storage element of the scan chain100according to an embodiment. The storage element1400may be an example of any of the storage elements1002,1003. . . or100n, in cases where the scan input data ‘sd’ received by the storage element1400is pull-up in the functional mode. For instance, the storage element1400is utilized when the scan output ‘sq’ (that is coupled to the scan input ‘sd’ of the storage element1400) provided by a preceding storage element (of the storage element1400) is pull-up in the functional mode (when SCAN is logic 0). For example, when SCAN is logic 0, the scan input ‘sd’ is logic 1.

The storage element1400includes a node145coupled to a scan output buffer750for driving a node725(scan output terminal). In this example embodiment, the node145is also coupled to a data output buffer250for driving a node225(data output terminal). The storage element1400includes the input circuit360that is configured to receive a data input (see, ‘d’) and a scan input (see, ‘sd’) from a data output and a scan output ‘sq’ of the preceding storage element, respectively. The input circuit360is configured to provide a signal corresponding to one of the data input ‘d’ and the scan input ‘sd’, at the node362. For instance, an inverse of the data input ‘d’ is provided at the node362in the shift mode (when SCAN is logic 1), and an inverse of the scan input ‘sd’ is provided at the node362in the functional mode (when SCANZ is logic 0).

An output (for example, the node362) of the input circuit360is connected to the shifting circuit150that is configured to transfer a signal corresponding to the node362to the node145. The input of the data output buffer250is connected to the node145and the output of the data output buffer250is connected to the node225(the data output terminal). Data output (q) of the storage element1400is taken from the node225. The scan output buffer750is also connected to the node145. In functional mode, the scan output buffer750is configured to pull-up the node725. In the shift mode, the transistors705,710and715form an inverter configuration (and the transistor720is disabled) providing an inverse of the value of the node145to the node725.

The operation of the storage element1400is now explained. The input circuit360causes a signal corresponding to one of the data input and the scan input ‘sd’, to be transferred at the node362. It should be noted that the scan input ‘sd’ is logic 1, when the SCAN is logic 0. For instance, a scan output ‘sq’ of a preceding storage element (such as the storage element200) of the storage element1400is pull-up when the SCAN is logic 0, and this pull-up logic 1 is fed to the scan input ‘sd’ of the storage element1100. When the SCAN is logic 1, the scan input ‘sd’ may have either of logic 0 or logic 1 depending upon the test data and value as received from the preceding storage element. As described in reference toFIG. 4, when SCAN is logic 0, an inverse of the data input ‘d’ is transferred at the node362, and when SCAN is logic 1, an inverse of the scan input ‘sd’ is transferred at the node362.

In functional mode (when SCAN is logic 0 or SCANZ is logic 1), the scan input ‘sd’ is logic 1, so the transistor375and380are disabled, and the transistors370and385are enabled. Accordingly, the transistors365,370,390and385form an inverter configuration, and an inverted logic level of ‘d’ is transferred to the node362. Assuming that ‘d’ is set to logic 1, then inverse of ‘d’, for example, logic 0 will then be available at the node362. The shifting circuit150is configured to force a logic level at the node145that is the inverse of the value at the node362. For example, output of inverter110of the shifting circuit145is logic 1. When CLK is low the transmission gate115becomes transparent and the logic 1 at the input of transmission gets transferred to the node195, forcing the output of the inverter130(node197) to be logic 0. When CLK becomes high the transmission gate125becomes transparent which transfers the value at the node197(logic 0) to the inverter120. The inverter120forces logic 1 on the node195. Another transmission gate135in enabled when CLK becomes high and hence transfers the value at the node197(logic 0) to the inverter140. The inverter140forces logic 1 on the node145. The inverter185, the transmission gate190and the inverter146comprise a loop back path when CLK is logic 0 and helps to retain the value at the node145. The data output buffer250inverts the value at the node145and forces a logic 0 at the node225. As SCAN is logic 0, the transistor220is disabled, and the transistors205,210and215form an inverter configuration, thereby transferring the inverted value of the node145(for example, a logic 0) at the node225. The data output ‘q’ is taken from the node225(that is the data output terminal) as inverse of the data input ‘d’. As SCAN is logic 0, the transistor705is disabled, which stops the data propagation to the node725. At the same time the transistor720is enabled which then pulls-down the node725to logic 0. The scan output terminal is coupled to the node725. Accordingly, in functional mode (when SCAN is logic 0), the scan output ‘sq’ is tied to logic 0 (this may help in power reduction in functional mode due to combinational logic switching in scan path which is driven by the scan output terminal). The scan enable input (SCANZ) acts as a control signal, which decides whether to tie the scan output terminal ‘sq’ to logic 1 or not. Accordingly, when SCAN is logic 0, the data output ‘q’ follows the inverse of the data input ‘d’ and the scan output ‘sq’ is tied to logic 0 (i.e., pull-down).

In shift mode (when SCAN is logic 1 or SCANZ is logic 0), the transistor370is disabled, and the transistor375(pull-up) and transistors380and385(pull-down) form an inverter configuration, and an inverse of the scan input ‘sd’ is transferred to the node362. It should be further be noted that when SCAN is logic 1, the scan output buffer750acts as an inverter, as the transistor720is disabled and the transistors705,710and715form an inverter configuration. The shifting circuit150is configured to force a logic level at the node145that is the inverse of the node362. For instance, if the scan input ‘sd’ is logic 1 (provided the SCAN is logic 1), the node362is at logic 0, and the node145is at logic 1. The scan output buffer750then transfers logic 0 at the node725that is coupled to the scan output ‘sq’. Accordingly, inverse of the scan input ‘sd’ is transferred to the scan output ‘sq’ when the IC operates in the shift mode. As SCAN is logic 1, the transistor215is disabled causing disabling the inverter comprised by transistors205and210. The transistor220is enabled and pulls-up the node225(the data output terminal) in response to SCANZ being logic 0. It is noted that transistor215is configured to protect leakage current through the inverter (formed by the transistors205and210) when the data output terminal (the node225) is pull-up.

In shift mode, the data output ‘q’ is tied to logic 1 (this will help in power reduction in shift mode due to combinational logic switching which is driven by data output terminal). The scan enable input (SCAN) acts as a control signal, which decides whether to tie the data output terminal ‘q’ to logic 1 or not. When SCAN is 0, the data output ‘q’ follows the inversion of the data input ‘d’ and the scan output ‘sq’ is tied to logic 0. When SCAN is logic 1, the data output q is tied to logic 1 and the scan output ‘sq’ follows the inversion of scan input (sd). According to this embodiment, average power over a number of ATPG shift cycles comes down as all the functional combinational logic does not toggle due to Q gating. Instantaneous peak power over the first shift cycle can be optimized by correctly choosing the type of flop for each logic block (pull-up or pull-down). This technique is extremely useful in case designers decide to convert only a subset of existing scan flops to this new design as then the peak/average power will depend upon the selection of “pull-up” or “pull-down” Q gating.

FIG. 15illustrates an example of a storage element other than the first storage element of the scan chain100according to an embodiment. The storage element1500may be an example of any of the storage elements1002,1003. . . or100n, in cases where the scan input data ‘sd’ received by the storage element1500is pull-up in the functional mode. For instance, the storage element1500is utilized when the scan output ‘sq’ (that is coupled to the scan input ‘sd’ of the storage element1500) provided by a preceding storage element (of the storage element1500) is pull-up in the functional mode (when SCAN is logic 0). For example, when SCAN is logic 0, the scan input ‘sd’ is logic 1.

The storage element1500includes a node145coupled to a scan output buffer750for driving a node725(scan output terminal). In this example embodiment, the node145is also coupled to the data output buffer650for driving the node625(data output terminal). The storage element1000includes the input circuit360that is configured to receive a data input (see, ‘d’) and a scan input (see, ‘sd’) from a data output ‘q’ and a scan output ‘sq’ of the preceding storage element, respectively. The input circuit360is configured to provide a signal corresponding to one of the data input ‘d’ and the scan input ‘sd’, at the node362. For instance, an inverse of the data input ‘d’ is provided at the node362in the shift mode (when SCAN is logic 1), and an inverse of the scan input ‘sd’ is provided at the node362in the functional mode (when SCANZ is logic 0).

An output (for example, the node362) of the input circuit360is connected to the shifting circuit150that is configured to transfer a signal corresponding to the node362to the node145. The input of the data output buffer650is connected to the node145and the output of the data output buffer650is connected to the node625(the data output terminal). Data output (q) of the storage element1500is taken from the node625. The scan output buffer750is also connected to the node145. In functional mode, the scan output buffer750is configured to pull-down the node725. In the shift mode, the transistors705,710and715form an inverter configuration (and the transistor720is disabled) providing an inverse of the value of the node145to the node725.

The operation of the storage element1500is now explained. The input circuit360causes a signal corresponding to one of the data input ‘d’ and the scan input ‘sd’, to be transferred at the node362. It should be noted that the scan input ‘sd’ is logic 1, when the SCAN is logic 0. For instance, a scan output ‘sq’ of a preceding storage element (such as the storage element200) of the storage element1500is pull-up when the SCAN is logic 0, and this pull-up logic 1 is fed to the scan input ‘sd’ of the storage element1500. When the SCAN is logic 1, the scan input ‘sd’ may have either of logic 0 or logic 1 depending upon the test data and value as received from the preceding storage element. As described in reference toFIG. 4, when SCAN is logic 0, an inverse of the data input ‘d’ is transferred at the node362, and when SCAN is logic 1, an inverse of the scan input ‘sd’ is transferred at the node362.

In functional mode (when SCAN is logic 0 or SCANZ is logic 1), the scan input ‘sd’ is logic 1, so the transistor375and380are disabled, and the transistors370and385are enabled. Accordingly, the transistors365,370,390and385form an inverter configuration, and an inverted logic level of is transferred to the node362. Assuming that ‘d’ is set to logic 1, then inverse of ‘d’, for example, logic 0 will then be available at the node362. The shifting circuit150is configured to force a logic level at the node145that is the inverse of the value at the node362. For example, output of inverter110of the shifting circuit145is logic 1. When CLK is low the transmission gate115becomes transparent and the logic 1 at the input of transmission gets transferred to the node195, forcing the output of the inverter130(node197) to be logic 0. When CLK becomes high the transmission gate125becomes transparent which transfers the value at the node197(logic 0) to the inverter120. The inverter120forces logic 1 on the node195. Another transmission gate135in enabled when CLK becomes high and hence transfers the value at the node197(logic 0) to the inverter150. The inverter150forces logic 1 on the node145. The inverter185, the transmission gate190and the inverter156comprise a loop back path when CLK is logic 0 and helps to retain the value at the node145. The data output buffer650inverts the value at the node145and forces a logic 0 at the node625. As SCAN is logic 0, the transistor620is disabled, and the transistors605,610and615form an inverter configuration, thereby transferring the inverted value of the node145(for example, a logic 0) at the node625. The data output ‘q’ is taken from the node625(that is the data output terminal) as inverse of the data input ‘d’. As SCAN is logic 0, the transistor705is disabled, which stops the data propagation to the node725. At the same time the transistor720is enabled which then pulls-down the node725to logic 0. The scan output terminal is coupled to the node725. Accordingly, in functional mode (when SCAN is logic 0), the scan output ‘sq’ is tied to logic 0 (this may help in power reduction in functional mode due to combinational logic switching in scan path which is driven by the scan output terminal). The scan enable input (SCANZ) acts as a control signal, which decides whether to tie the scan output terminal ‘sq’ to logic 1 or not. Accordingly, when SCAN is logic 0, the data output ‘q’ follows the inverse of the data input ‘d’ and the scan output ‘sq’ is tied to logic 0 (i.e., pull-down).

In shift mode (when SCAN is logic 1 or SCANZ is logic 0), the transistor370is disabled, and the transistor375(pull-up) and transistors380and385(pull-down) form an inverter configuration, and an inverse of the scan input ‘sd’ is transferred to the node362. It should be further be noted that when SCAN is logic 1, the scan output buffer750acts as an inverter, as the transistor720is disabled and the transistors705,710and715form an inverter configuration. The shifting circuit150is configured to force a logic level at the node145that is the inverse of the node462. For instance, if the scan input ‘sd’ is logic 1 (provided the SCAN is logic 1), the node462is at logic 0, and the node145is at logic 1. The scan output buffer750then transfers logic 0 at the node725that is coupled to the scan output ‘sq’. Accordingly, inverse of the scan input ‘sd’ is transferred to the scan output ‘sq’ when the IC operates in the shift mode. As SCAN is logic 1, the transistor605is disabled causing disabling the inverter comprised by transistors605and610. The transistor620is enabled and pulls down the node625(the data output terminal q) in response to SCAN. It is noted that transistor605is configured to protect leakage current through the inverter (formed by the transistors610and615) when the data output terminal is pull-down.

In shift mode, the data output ‘q’ is tied to logic 0 (this will help in power reduction in shift mode due to combinational logic switching which is driven by data output terminal). The scan enable input (SCAN) acts as a control signal, which decides whether to tie the data output terminal ‘q’ to logic1 or not. When SCAN is 0, the data output ‘q’ follows the inversion of the data input ‘d’ and the scan output ‘sq’ is tied to logic 0. When SCAN is logic 1, the data output q is tied to logic 0 and the scan output ‘sq’ follows the inversion of scan input (sd). According to this embodiment, average power over a number of ATPG shift cycles comes down as all the functional combinational logic does not toggle due to Q gating. Instantaneous peak power over the first shift cycle can be optimized by correctly choosing the type of flop for each logic block (pull-up or pull-down). This technique is extremely useful in case designers decide to convert only a subset of existing scan flops to this new design as then the peak/average power will depend upon the selection of “pull-up” or “pull-down” Q gating.

FIG. 16illustrates an example of a storage element other than the first storage element of the scan chain100according to an embodiment. The storage element1600may be an example of any of the storage elements1002,1003. . . or100n, in cases where the scan input data ‘sd’ received by the storage element1600is pull-down in the functional mode. For instance, the storage element1600is utilized when the scan output ‘sq’ (that is coupled to the scan input ‘sd’ of the storage element1600) provided by a preceding storage element (of the storage element1600) is pull-down in the functional mode (when SCAN is logic 0). For example, when SCAN is logic 0, the scan input ‘sd’ is logic 1.

The storage element1600includes a node145coupled to a scan output buffer750for driving a node725(scan output terminal). In this example embodiment, the node145is also coupled to a data output buffer250for driving a node225(data output terminal). The storage element1600includes the input circuit460that is configured to receive a data input (see, ‘d’) and a scan input (see, ‘sd’) from a data output ‘q’ and a scan output ‘sq’ of the preceding storage element, respectively. The input circuit460is configured to provide a signal corresponding to one of the data input ‘d’ and the scan input ‘sd’, at the node462. For instance, an inverse of the data input ‘d’ is provided at the node462in the shift mode (when SCANZ is logic 1), and an inverse of the scan input ‘sd’ is provided at the node462in the functional mode (when SCANZ is logic 0).

An output (for example, the node462) of the input circuit460is connected to the shifting circuit150that is configured to transfer a signal corresponding to the node462to the node145. The input of the data output buffer250is connected to the node145and the output of the data output buffer250is connected to the node225(the data output terminal). Data output (q) of the storage element1600is taken from the node225. The scan output buffer550is also connected to the node145. In functional mode, the scan output buffer750is configured to pull-down the node725. In the shift mode, the transistors705,710and715form an inverter configuration (and the transistor720is disabled) providing an inverse of the value of the node145to the node725.

The operation of the storage element1600is now explained. The input circuit460causes a signal corresponding to one of the data input and the scan input ‘sd’, to be transferred at the node462. It should be noted that in this embodiment, the scan input ‘sd’ is logic 0, when the SCAN is logic 0. For instance, a scan output ‘sq’ of a preceding storage element (such as the storage element300) of the storage element1600is pull-down when the SCAN is logic 0, and this pull-down logic 0 is fed to the scan input ‘sd’ of the storage element1600. When the SCAN is logic 1, the scan input ‘sd’ may have either of logic 0 or logic 1 depending upon the test data and value as received from the preceding storage element. As illustrated in theFIG. 15, when SCAN is logic 0, an inverse of the data input ‘d’ is transferred at the node462, and when SCAN is logic 1, an inverse of the scan input ‘sd’ is transferred at the node462.

In functional mode (when SCAN is logic 0 or SCANZ is logic 1), the scan input ‘sd’ is logic 0, so the transistor475and490are disabled, and the transistors465and480are enabled. Accordingly, the transistors465,470,480and485form an inverter configuration, and an inverted logic level of ‘d’ is transferred to the node462. Assuming that ‘d’ is set to logic 1, then inverse of ‘d’, for example, logic 0 will then be available at the node462. The shifting circuit150is configured to force a logic level at the node145that is the inverse of value at the node462. For example, logic 1 is transferred at the output of inverter120of the shifting circuit145. When CLK is low the transmission gate125becomes transparent and the logic 1 at the input of transmission gets transferred to the node195, forcing the output of the inverter130(node197) to be logic 0. When CLK becomes high the transmission gate125becomes transparent which transfers the value at the node197(logic 0) to the inverter120. The inverter120forces logic 1 on the node195. Another transmission gate135in enabled when CLK becomes high and hence transfers the value at the node197(logic 0) to the inverter140. The inverter140forces logic 1 on the node145. The inverter185, the transmission gate190and the inverter146comprise a loop back path when CLK is logic 0 and helps to retain the value at the node145. The data output buffer250inverts the value at the node145and forces a logic 0 at the node225. As SCAN is logic 0, the transistor220is disabled, and the transistors205,210and215form an inverter configuration, thereby transferring the inverted value of the node145(for example, a logic 0) at the node225. The data output ‘q’ is taken from the node225(that is the data output terminal) as inverse of the data input ‘d’. As SCAN is logic 0, the transistor705is disabled, which stops the data propagation to the node725. At the same time the transistor720is enabled which then pulls-down the node725to logic 0. The scan output terminal is coupled to the node725. Accordingly, in functional mode (when SCAN is logic 0), the scan output ‘sq’ is tied to logic 0 (this may help in power reduction in functional mode due to combinational logic switching in scan path which is driven by the scan output terminal). The scan enable input (SCANZ) acts as a control signal, which decides whether to tie the scan output terminal ‘sq’ to logic 0 or not. Accordingly, when SCAN is logic 0, the data output ‘q’ follows the inverse of the data input ‘d’ and the scan output ‘sq’ is tied to logic 0 (i.e., pull-down).

In shift mode (when SCAN is logic 1 or SCANZ is logic 0), the transistor480is disabled, and the transistors465,475(pull-up) and transistors490(pull-down) form an inverter configuration, and an inverse of the scan input ‘sd’ is transferred to the node462. It should be further be noted that when SCAN is logic 1, the scan output buffer750acts as an inverter, as the transistor720is disabled and the transistors705,710and715form an inverter configuration. The shifting circuit150is configured to force a logic level at the node145that is the inverse of the node462. For instance, if the scan input ‘sd’ is logic 1 (provided the SCAN is logic 1), the node462is at logic 0, and the node145is at logic 1. The scan output buffer750then transfers logic 0 at the node725that is coupled to the scan output ‘sq’. Accordingly, inverse of the scan input ‘sd’ is transferred to the scan output ‘sq’ when the IC operates in the shift mode. As SCAN is logic 1, the transistor215is disabled causing disabling the inverter comprised by transistors205and210. The transistor220is enabled and pulls-up the node225(the data output terminal q) in response to SCANZ being logic 0. It is noted that transistor215is configured to protect leakage current through the inverter (formed by the transistors205and210) when the data output terminal (the node225) is pull-up.

In shift mode, the data output ‘q’ is tied to logic 1 (this will help in power reduction in shift mode due to combinational logic switching which is driven by data output terminal). The scan enable input (SCAN) acts as a control signal, which decides whether to tie the data output terminal ‘q’ to logic1 or not. When SCAN is 0, the data output ‘q’ follows the inversion of the data input ‘d’ and the scan output ‘sq’ is tied to logic 0. When SCAN is logic 1, the data output q is tied to logic 1 and the scan output ‘sq’ follows the inversion of scan input (sd). According to this embodiment, average power over a number of ATPG shift cycles comes down as all the functional combinational logic does not toggle due to Q gating. Instantaneous peak power over the first shift cycle can be optimized by correctly choosing the type of flop for each logic block (pull-up or pull-down). This technique is extremely useful in case designers decide to convert only a subset of existing scan flops to this new design as then the peak/average power will depend upon the selection of “pull-up” or “pull-down” Q gating.

FIG. 17illustrates an example of a storage element other than the first storage element of the scan chain100according to an embodiment. The storage element1700may be an example of any of the storage elements1002,1003. . . or 100n, in cases where the scan input data ‘sd’ received by the storage element1700is pull-down in the functional mode. For instance, the storage element1700is utilized when the scan output ‘sq’ (that is coupled to the scan input ‘sd’ of the storage element1700) provided by a preceding storage element (of the storage element1700) is pull-down in the functional mode (when SCAN is logic 0). For example, when SCAN is logic 0, the scan input ‘sd’ is logic 1.

The storage element1700includes a node145coupled to a scan output buffer750for driving a node725(scan output terminal). In this example embodiment, the node145is also coupled to a data output buffer650for driving the node625(data output terminal). The storage element1700includes the input circuit460that is configured to receive a data input (see, ‘d’) and a scan input (see, ‘sd’) from a data output ‘q’ and a scan output ‘sq’ of the preceding storage element, respectively. The input circuit460is configured to provide a signal corresponding to one of the data input ‘d’ and the scan input ‘sd’, at the node462. For instance, an inverse of the data input ‘d’ is provided at the node462in the shift mode (when SCANZ is logic 1), and an inverse of the scan input ‘sd’ is provided at the node462in the functional mode (when SCANZ is logic 0).

An output (for example, the node462) of the input circuit460is connected to the shifting circuit150that is configured to transfer a signal corresponding to the node462to the node145. The input of the data output buffer650is connected to the node145and the output of the data output buffer650is connected to the node625(the data output terminal). Data output (q) of the storage element1700is taken from the node625. The scan output buffer550is also connected to the node145. In functional mode, the scan output buffer750is configured to pull-down the node725. In the shift mode, the transistors705,710and715form an inverter configuration (and the transistor720is disabled) providing an inverse of the value of the node145to the node725.

The operation of the storage element1700is now explained. The input circuit460causes a signal corresponding to one of the data input and the scan input ‘sd’, to be transferred at the node462. It should be noted that in this embodiment, the scan input ‘sd’ is logic 0, when the SCAN is logic 0. For instance, a scan output ‘sq’ of a preceding storage element (such as the storage element300) of the storage element1700is pull-down when the SCAN is logic 0, and this pull-down logic 0 is fed to the scan input ‘sd’ of the storage element1700. When the SCAN is logic 1, the scan input ‘sd’ may have either of logic 0 or logic 1 depending upon the test data and value as received from the preceding storage element. As illustrated in theFIG. 17, when SCAN is logic 0, an inverse of the data input ‘d’ is transferred at the node462, and when SCAN is logic 1, an inverse of the scan input ‘sd’ is transferred at the node462.

In functional mode (when SCAN is logic 0 or SCANZ is logic 1), the scan input ‘sd’ is logic 0, so the transistor475and490are disabled, and the transistors465and480are enabled. Accordingly, the transistors465,470,480and485form an inverter configuration, and an inverted logic level of ‘d’ is transferred to the node462. Assuming that ‘d’ is set to logic 1, then inverse of ‘d’, for example, logic 0 will then be available at the node462. The shifting circuit150is configured to force a logic level at the node145that is the inverse of value at the node462. For example, logic 1 is transferred at the output of inverter120of the shifting circuit145. When CLK is low the transmission gate125becomes transparent and the logic 1 at the input of transmission gets transferred to the node195, forcing the output of the inverter130(node197) to be logic 0. When CLK becomes high the transmission gate125becomes transparent which transfers the value at the node197(logic 0) to the inverter120. The inverter120forces logic 1 on the node195. Another transmission gate135in enabled when CLK becomes high and hence transfers the value at the node197(logic 0) to the inverter140. The inverter140forces logic 1 on the node145. The inverter185, the transmission gate190and the inverter146comprise a loop back path when CLK is logic 0 and helps to retain the value at the node145. The data output buffer650inverts the value at the node145and forces a logic 0 at the node625. As SCAN is logic 0, the transistor620is disabled, and the transistors605,610and615form an inverter configuration, thereby transferring the inverted value of the node145(for example, a logic 0) at the node625. The data output ‘q’ is taken from the node625(that is the data output terminal) as inverse of the data input ‘d’. As SCAN is logic 0, the transistor705is disabled, which stops the data propagation to the node725. At the same time the transistor720is enabled which then pulls-down the node725to logic 0. The scan output terminal is coupled to the node725. Accordingly, in functional mode (when SCAN is logic 0), the scan output ‘sq’ is tied to logic 0 (this may help in power reduction in functional mode due to combinational logic switching in scan path which is driven by the scan output terminal). The scan enable input (SCANZ) acts as a control signal, which decides whether to tie the scan output terminal ‘sq’ to logic 0 or not. Accordingly, when SCAN is logic 0, the data output ‘q’ follows the inverse of the data input ‘d’ and the scan output ‘sq’ is tied to logic 0 (i.e., pull-down).

In shift mode (when SCAN is logic 1 or SCANZ is logic 0), the transistor480is disabled, and the transistors465,475(pull-up) and transistors490(pull-down) form an inverter configuration, and an inverse of the scan input ‘sd’ is transferred to the node462. It should be further be noted that when SCAN is logic 1, the scan output buffer750acts as an inverter, as the transistor720is disabled and the transistors705,710and715form an inverter configuration. The shifting circuit150is configured to force a logic level at the node145that is the inverse of the node462. For instance, if the scan input ‘sd’ is logic 1 (provided the SCAN is logic 1), the node462is at logic 0, and the node145is at logic 1. The scan output buffer750then transfers logic 0 at the node725that is coupled to the scan output ‘q’. Accordingly, inverse of the scan input ‘sd’ is transferred to the scan output ‘sq’ when the IC operates in the shift mode. As SCAN is logic 1, the transistor605is disabled causing disabling the inverter comprised by transistors605and610. The transistor620is enabled and pulls down the node625(the data output terminal q) in response to SCAN. It is noted that transistor605is configured to protect leakage current through the inverter (formed by the transistors610and615) when the data output terminal is pull-down.

In shift mode, the data output ‘q’ is tied to logic 0 (this will help in power reduction in shift mode due to combinational logic switching which is driven by data output terminal). The scan enable input (SCAN) acts as a control signal, which decides whether to tie the data output terminal ‘q’ to logic 0 or not. When SCAN is 0, the data output ‘q’ follows the inversion of the data input ‘d’ and the scan output ‘sq’ is tied to logic 0. When SCAN is logic 1, the data output q is tied to logic 0 and the scan output ‘sq’ follows the inversion of scan input (sd). According to this embodiment, average power over a number of ATPG shift cycles comes down as all the functional combinational logic does not toggle due to Q gating. Instantaneous peak power over the first shift cycle can be optimized by correctly choosing the type of flop for each logic block (pull-up or pull-down). This technique is extremely useful in case designers decide to convert only a subset of existing scan flops to this new design as then the peak/average power will depend upon the selection of “pull-up” or “pull-down” q gating.

FIG. 18illustrates an example of a storage element other than the first storage element of the scan chain100according to an embodiment. The storage element1800may be an example of any of the storage elements1002,1003. . . or100n, in cases where the scan input data ‘sd’ received by the storage element1800is pull-up in the functional mode. For instance, the storage element1800is utilized when the scan output ‘sq’ (that is coupled to the scan input ‘sd’ of the storage element1800) provided by a preceding storage element (of the storage element1800) is pull-up in the functional mode (when SCAN is logic 0). For example, when SCAN is logic 0, the scan input ‘sd’ is logic 1.

The storage element1800includes a node145coupled to a scan output buffer450for driving the node415(scan output terminal). In this example embodiment, the node145is also coupled to the data output buffer250for driving the node225(data output terminal). The storage element1800includes the input circuit360that is configured to receive a data input (see, ‘d’) and a scan input (see, ‘sd’) from a data output ‘q’ and a scan output ‘sq’ of the preceding storage element, respectively. The input circuit360is configured to provide a signal corresponding to one of the data input and the scan input ‘sd’, at the node362. For instance, an inverse of the data input ‘d’ is provided at the node362in the shift mode (when SCAN is logic 1), and an inverse of the scan input ‘sd’ is provided at the node362in the functional mode (when SCANZ is logic 0).

An output (for example, the node362) of the input circuit360is connected to the shifting circuit150that is configured to transfer a signal corresponding to the node362to the node145. The input of the data output buffer250is connected to the node145and the output of the data output buffer250is connected to the node225(the data output terminal). Data output (q) of the storage element1800is taken from the node225. The scan output buffer450is also connected to the node145. As described in reference toFIG. 8, the scan output buffer450includes the PMOS transistor405(first MOS transistor) and the NMOS transistor410(second MOS transistor) (forming a transmission gate) followed by the pull-down NMOS transistor420. The transistor420to act as a pull-down transistor in functional mode (when SCANZ is logic 1), as the transistors405and410are disabled in the functional mode. In the shift mode (when SCANZ is logic 0), the transistor420is disabled; and the transmission gate is enabled and provides the value of the node145to the node415.

The operation of the storage element1800is now explained. The input circuit360causes a signal corresponding to one of the data input ‘d’ and the scan input ‘sd’, to be transferred at the node362. It should be noted that the scan input ‘sd’ is logic 1, when the SCAN is logic 0. For instance, a scan output ‘sq’ of a preceding storage element (such as the storage element200) of the storage element1800is pull-up when the SCAN is logic 0, and this pull-up logic 1 is fed to the scan input ‘sd’ of the storage element1800. When the SCAN is logic 1, the scan input ‘sd’ may have either of logic 0 or logic 1 depending upon the test data and value as received from the preceding storage element. As described in reference toFIG. 4, when SCAN is logic 0, an inverse of the data input ‘d’ is transferred at the node362, and when SCAN is logic 1, an inverse of the scan input ‘sd’ is transferred at the node362.

In functional mode (when SCAN is logic 0 or SCANZ is logic 1), the scan input ‘sd’ is logic 1, so the transistor375and380are disabled, and the transistors370and385are enabled. Accordingly, the transistors365,370,390and385form an inverter configuration, and an inverted logic level of ‘d’ is transferred to the node362. Assuming that ‘d’ is set to logic 1, then inverse of ‘d’, for example, logic 0 will then be available at the node362. The shifting circuit150is configured to force a logic level at the node145that is the inverse of the value at the node362. For example, output of inverter110of the shifting circuit145is logic 1. When CLK is low the transmission gate115becomes transparent and the logic 1 at the input of transmission gets transferred to the node195, forcing the output of the inverter130(node197) to be logic 0. When CLK becomes high the transmission gate125becomes transparent which transfers the value at the node197(logic 0) to the inverter120. The inverter120forces logic 1 on the node195. Another transmission gate135in enabled when CLK becomes high and hence transfers the value at the node197(logic 0) to the inverter140. The inverter140forces logic 1 on the node145. The inverter185, the transmission gate190and the inverter146comprise a loop back path when CLK is logic 0 and helps to retain the value at the node145. The data output buffer250inverts the value at the node145and forces a logic 0 at the node225. As SCAN is logic 0, the transistor220is disabled, and the transistors205,210and215form an inverter configuration, thereby transferring the inverted value of the node145(for example, a logic 0) at the node225. The data output ‘q’ is taken from the node225(that is the data output terminal) as inverse of the data input ‘d’. As SCAN is logic 0, the transmission gate formed by the transistors405and410isolates the node415from node145. At the same time the transistor420is enabled which then pulls-down the node415to logic 0 irrespective of the clock signal CLK in functional mode. The scan output terminal is coupled to the node415. Accordingly, in the functional mode (when SCAN is logic 0), the scan output ‘sq’ is tied to logic 0 (this may help in power reduction in the functional mode due to combinational logic switching in scan path which is driven by the scan output terminal). The scan enable input (SCANZ) acts as a control signal, which decides whether to tie the scan output terminal ‘sq’ to logic 1 or not. Accordingly, when SCAN is logic 0, the data output ‘q’ follows the inverse of the data input ‘d’ and the scan output ‘sq’ is tied to logic 0 (i.e., pull-down).

In shift mode (when SCAN is logic 1 or SCANZ is logic 0), the transistor370is disabled, and the transistor375(pull-up) and transistors380and385(pull-down) form an inverter configuration, and an inverse of the scan input ‘sd’ is transferred to the node362. It should be further be noted that when SCAN is logic 1, the scan output buffer450acts as a transmission gate buffer, as the transistor420is disabled and the transmission gate formed by the transistors405and410transfers the value present at the node145to the node415. The shifting circuit150is configured to force a logic level at the node145that is the inverse of the node362. For instance, if the scan input ‘sd’ is logic 1 (provided the SCAN is logic 1), the node362is at logic 0, and the node145is at logic 1. The scan output buffer450then transfers logic 1 at the node415that is coupled to the scan output ‘sq’. Accordingly, the scan input ‘sd’ is transferred to the scan output ‘sq’ when the IC operates in the shift mode. As SCAN is logic 1, the transistor215is disabled causing disabling the inverter comprised by transistors205and210. The transistor220is enabled and pulls-up the node225(the data output terminal) in response to SCANZ being logic 0. It is noted that transistor215is configured to protect leakage current through the inverter (formed by the transistors205and210) when the data output terminal (the node225) is pull-up.

In shift mode, the data output ‘q’ is tied to logic 1 (this will help in power reduction in shift mode due to combinational logic switching which is driven by data output terminal). The scan enable input (SCAN) acts as a control signal, which decides whether to tie the data output terminal ‘q’ to logic 1 or not. When SCAN is 0, the data output ‘q’ follows the inversion of the data input ‘d’ and the scan output ‘sq’ is tied to logic 0. When SCAN is logic 1, the data output ‘q’ is tied to logic 1 and the scan output ‘sq’ follows the scan input (sd). According to this embodiment, average power over a number of ATPG shift cycles comes down as all the functional combinational logic does not toggle due to Q gating. Instantaneous peak power over the first shift cycle can be optimized by correctly choosing the type of flop for each logic block (pull-up or pull-down). This technique is extremely useful in case designers decide to convert only a subset of existing scan flops to this new design as then the peak/average power will depend upon the selection of “pull-up” or “pull-down” Q gating.

FIG. 19illustrates an example of a storage element other than the first storage element of the scan chain100according to an embodiment. The storage element1900may be an example of any of the storage elements1002,1003. . . or100n, in cases where the scan input data ‘sd’ received by the storage element1900is pull-up in the functional mode. For instance, the storage element1900is utilized when the scan output ‘sq’ (that is coupled to the scan input ‘sd’ of the storage element1900) provided by a preceding storage element (of the storage element1900) is pull-up in the functional mode (when SCAN is logic 0). For example, when SCAN is logic 0, the scan input ‘sd’ is logic 1.

The storage element1900includes a node145coupled to a scan output buffer450for driving the node415(scan output terminal). In this example embodiment, the node145is also coupled to the data output buffer650for driving the node625(data output terminal). The storage element1900includes the input circuit360that is configured to receive a data input (see, ‘d’) and a scan input (see, ‘sd’) from a data output ‘q’ and a scan output ‘sq’ of the preceding storage element, respectively. The input circuit360is configured to provide a signal corresponding to one of the data input ‘d’ and the scan input ‘sd’, at the node362. For instance, an inverse of the data input ‘d’ is provided at the node362in the shift mode (when SCAN is logic 1), and an inverse of the scan input ‘sd’ is provided at the node362in the functional mode (when SCANZ is logic 0).

An output (for example, the node362) of the input circuit360is connected to the shifting circuit150that is configured to transfer a signal corresponding to the node362to the node145. The input of the data output buffer650is connected to the node145and the output of the data output buffer650is connected to the node625(the data output terminal). Data output (q) of the storage element1900is taken from the node625. The scan output buffer450is also connected to the node145. As described in reference toFIG. 8, the scan output buffer450includes the PMOS transistor405(first MOS transistor) and the NMOS transistor410(second MOS transistor) (forming a transmission gate) followed by the pull-down NMOS transistor420. The transistor420to act as a pull-down transistor in functional mode (when SCANZ is logic 1), as the transistors405and410are disabled in the functional mode. In the shift mode (when SCANZ is logic 0), the transistor420is disabled; and the transmission gate is enabled and provides the value of the node145to the node415.

The operation of the storage element1900is now explained. The input circuit360causes a signal corresponding to one of the data input ‘d’ and the scan input ‘sd’, to be transferred at the node362. It should be noted that the scan input ‘sd’ is logic 1, when the SCAN is logic 0. For instance, a scan output ‘sq’ of a preceding storage element (such as the storage element200) of the storage element1900is pull-up when the SCAN is logic 0, and this pull-up logic 1 is fed to the scan input ‘sd’ of the storage element1900. When the SCAN is logic 1, the scan input ‘sd’ may have either of logic 0 or logic 1 depending upon the test data and value as received from the preceding storage element. As described in reference toFIG. 4, when SCAN is logic 0, an inverse of the data input ‘d’ is transferred at the node362, and when SCAN is logic 1, an inverse of the scan input ‘sd’ is transferred at the node362.

In functional mode (when SCAN is logic 0 or SCANZ is logic 1), the scan input ‘sd’ is logic 1, so the transistor375and380are disabled, and the transistors370and385are enabled. Accordingly, the transistors365,370,390and385form an inverter configuration, and an inverted logic level of ‘d’ is transferred to the node362. Assuming that ‘d’ is set to logic 1, then inverse of ‘d’, for example, logic 0 will then be available at the node362. The shifting circuit150is configured to force a logic level at the node145that is the inverse of the value at the node362. For example, output of inverter110of the shifting circuit145is logic 1. When CLK is low the transmission gate115becomes transparent and the logic 1 at the input of transmission gets transferred to the node195, forcing the output of the inverter130(node197) to be logic 0. When CLK becomes high the transmission gate125becomes transparent which transfers the value at the node197(logic 0) to the inverter120. The inverter120forces logic 1 on the node195. Another transmission gate135in enabled when CLK becomes high and hence transfers the value at the node197(logic 0) to the inverter140. The inverter140forces logic 1 on the node145. The inverter185, the transmission gate190and the inverter146comprise a loop back path when CLK is logic 0 and helps to retain the value at the node145. The data output buffer650inverts the value at the node145and forces a logic 0 at the node625. As SCAN is logic 0, the transistor620is disabled, and the transistors605,610and615form an inverter configuration, thereby transferring the inverted value of the node145(for example, a logic 0) at the node625. The data output ‘q’ is taken from the node625(that is the data output terminal) as inverse of the data input ‘d’. As SCAN is logic 0, the transmission gate formed by the transistors405and410isolates the node415from node145. At the same time the transistor420is enabled which then pulls-down the node415to logic 0 irrespective of the clock signal CLK in functional mode. The scan output terminal is coupled to the node415. Accordingly, in the functional mode (when SCAN is logic 0), the scan output ‘sq’ is tied to logic 0 (this may help in power reduction in the functional mode due to combinational logic switching in scan path which is driven by the scan output terminal). The scan enable input (SCANZ) acts as a control signal, which decides whether to tie the scan output terminal ‘sq’ to logic 1 or not. Accordingly, when SCAN is logic 0, the data output ‘q’ follows the inverse of the data input ‘d’ and the scan output ‘sq’ is tied to logic 0 (i.e., pull-down).

In shift mode (when SCAN is logic 1 or SCANZ is logic 0), the transistor370is disabled, and the transistor375(pull-up) and transistors380and385(pull-down) form an inverter configuration, and an inverse of the scan input ‘sd’ is transferred to the node362. It should be further be noted that when SCAN is logic 1, the scan output buffer450acts as a transmission gate buffer, as the transistor420is disabled and the transmission gate formed by the transistors405and410transfers the value present at the node145to the node415. The shifting circuit150is configured to force a logic level at the node145that is the inverse of the node362. For instance, if the scan input ‘sd’ is logic 1 (provided the SCAN is logic 1), the node362is at logic 0, and the node145is at logic 1. The scan output buffer450then transfers logic 1 at the node415that is coupled to the scan output ‘sq’. Accordingly, the scan input ‘sd’ is transferred to the scan output ‘sq’ when the IC operates in the shift mode. As SCAN is logic 1, the transistor605is disabled causing disabling the inverter comprised by transistors605and610. The transistor620is enabled and pulls down the node625(the data output terminal q) in response to SCAN. It is noted that transistor605is configured to protect leakage current through the inverter (formed by the transistors610and615) when the data output terminal625is pull-down.

In shift mode, the data output ‘q’ is tied to logic 0 (this will help in power reduction in shift mode due to combinational logic switching which is driven by data output terminal). The scan enable input (SCAN) acts as a control signal, which decides whether to tie the data output terminal ‘q’ to logic 0 or not. When SCAN is 0, the data output ‘q’ follows the inversion of the data input ‘d’ and the scan output ‘sq’ is tied to logic 0. When SCAN is logic 1, the data output ‘q’ is tied to logic 0 and the scan output ‘sq’ follows the scan input (sd). According to this embodiment, average power over a number of ATPG shift cycles comes down as all the functional combinational logic does not toggle due to Q gating. Instantaneous peak power over the first shift cycle can be optimized by correctly choosing the type of flop for each logic block (pull-up or pull-down). This technique is extremely useful in case designers decide to convert only a subset of existing scan flops to this new design as then the peak/average power will depend upon the selection of “pull-up” or “pull-down” Q gating.

FIG. 20illustrates an example of a storage element other than the first storage element of the scan chain100according to an embodiment. The storage element2000may be an example of any of the storage elements1002,1003. . . or100n, in cases where the scan ‘sd’ received by the storage element2000is pull-down in the functional mode. For instance, the storage element2000is utilized when the scan output ‘sq’ (that is coupled to the scan input ‘sd’ of the storage element2000) provided by a preceding storage element (of the storage element2000) is pull-down in the functional mode (when SCAN is logic 0). For example, when SCAN is logic 0, the scan input ‘sd’ is logic 0.

The storage element2000includes a node145coupled to a scan output buffer450for driving the node415(scan output terminal). In this example embodiment, the node145is also coupled to the data output buffer250for driving the node225(data output terminal). The storage element2000includes the input circuit460that is configured to receive a data input (see, ‘d’) and a scan input (see, ‘sd’) from a data output ‘q’ and a scan output ‘sq’ of the preceding storage element, respectively. The input circuit460is configured to provide a signal corresponding to one of the data input ‘sd’ and the scan input ‘sd’, at the node462. For instance, an inverse of the data input ‘d’ is provided at the node462in the shift mode (when SCANZ is logic 1), and an inverse of the scan input ‘sd’ is provided at the node462in the functional mode (when SCANZ is logic 0).

An output (for example, the node462) of the input circuit460is connected to the shifting circuit150that is configured to transfer a signal corresponding to the node462to the node145. The input of the data output buffer250is connected to the node145and the output of the data output buffer250is connected to the node225(the data output terminal). Data output (q) of the storage element2000is taken from the node225. The scan output buffer450is also connected to the node145. As described in reference toFIG. 8, the scan output buffer450includes the PMOS transistor405(first MOS transistor) and the NMOS transistor410(second MOS transistor) (forming a transmission gate) followed by the pull-down NMOS transistor420. The transistor420to act as a pull-down transistor in functional mode (when SCANZ is logic 1), as the transistors405and410are disabled in the functional mode. In the shift mode (when SCANZ is logic 0), the transistor420is disabled; and the transmission gate is enabled and provides the value of the node145to the node415.

The operation of the storage element2000is now explained. The input circuit460causes a signal corresponding to one of the data input ‘d’ and the scan input ‘sd’, to be transferred at the node462. It should be noted that the scan input ‘sd’ is logic 0, when the SCAN is logic 0. For instance, a scan output ‘sq’ of a preceding storage element (such as the storage element200) of the storage element2000is pull-down when the SCAN is logic 0, and this pull-down logic 0 is fed to the scan input ‘sd’ of the storage element1100. When the SCAN is logic 1, the scan input ‘sd’ may have either of logic 0 or logic 1 depending upon the test data and value as received from the preceding storage element. As described in reference toFIG. 5, when SCAN is logic 0, an inverse of the data input ‘d’ is transferred at the node462, and when SCAN is logic 1, an inverse of the scan input ‘sd’ is transferred at the node462.

In functional mode (when SCAN is logic 0 or SCANZ is logic 1), the scan input ‘sd’ is logic 0, so the transistor475and490are disabled, and the transistors465and480are enabled. Accordingly, the transistors465,470,480and485form an inverter configuration, and an inverted logic level of ‘d’ is transferred to the node462. Assuming that ‘d’ is set to logic 1, then inverse of ‘d’, for example, logic 0 will then be available at the node462. The shifting circuit150is configured to force a logic level at the node145that is the inverse of value at the node462. For example, logic 1 is transferred at the output of inverter120of the shifting circuit145. When CLK is low the transmission gate125becomes transparent and the logic 1 at the input of transmission gets transferred to the node195, forcing the output of the inverter130(node197) to be logic 0. When CLK becomes high the transmission gate125becomes transparent which transfers the value at the node197(logic 0) to the inverter120. The inverter120forces logic 1 on the node195. Another transmission gate135in enabled when CLK becomes high and hence transfers the value at the node197(logic 0) to the inverter140. The inverter140forces logic 1 on the node145. The inverter185, the transmission gate190and the inverter146comprise a loop back path when CLK is logic 0 and helps to retain the value at the node145. The data output buffer250inverts the value at the node145and forces a logic 0 at the node225. As SCAN is logic 0, the transistor220is disabled, and the transistors205,210and215form an inverter configuration, thereby transferring the inverted value of the node145(for example, a logic 0) at the node225. The data output ‘d’ is taken from the node225(that is the data output terminal) as inverse of the data input ‘d’. As SCAN is logic 0, the transmission gate formed by the transistors405and410isolates the node415from node145. At the same time the transistor420is enabled which then pulls-down the node415to logic 0 irrespective of the clock signal CLK in functional mode. The scan output terminal is coupled to the node415. Accordingly, in the functional mode (when SCAN is logic 0), the scan output ‘sq’ is tied to logic 0 (this may help in power reduction in the functional mode due to combinational logic switching in scan path which is driven by the scan output terminal). The scan enable input (SCANZ) acts as a control signal, which decides whether to tie the scan output terminal ‘sq’ to logic 1 or not. Accordingly, when SCAN is logic 0, the data output ‘q’ follows the inverse of the data input ‘d’ and the scan output ‘sq’ is tied to logic 0 (i.e., pull-down).

In shift mode (when SCAN is logic 1 or SCANZ is logic 0), the transistor480is disabled, and the transistors465,475(pull-up) and transistors490(pull-down) form an inverter configuration, and an inverse of the scan input ‘sd’ is transferred to the node462. It should be further be noted that when SCAN is logic 1, the scan output buffer450acts as a transmission gate buffer, as the transistor420is disabled and the transmission gate formed by the transistors405and410transfers the value present at the node145to the node415. The shifting circuit150is configured to force a logic level at the node145that is the inverse of the node462. For instance, if the scan input ‘sd’ is logic 1 (provided the SCAN is logic 1), the node462is at logic 0, and the node145is at logic 1. The scan output buffer450then transfers logic 1 at the node415that is coupled to the scan output ‘sq’. Accordingly, the scan input ‘sd’ is transferred to the scan output ‘sq’ when the IC operates in the shift mode. As SCAN is logic 1, the transistor215is disabled causing disabling the inverter comprised by transistors205and210. The transistor220is enabled and pulls-up the node225(the data output terminal) in response to SCANZ being logic 0. It is noted that transistor215is configured to protect leakage current through the inverter (formed by the transistors205and210) when the data output terminal (the node225) is pull-up.

In shift mode, the data output ‘q’ is tied to logic 1 (this will help in power reduction in shift mode due to combinational logic switching which is driven by data output terminal). The scan enable input (SCAN) acts as a control signal, which decides whether to tie the data output terminal ‘q’ to logic 1 or not. When SCAN is 0, the data output ‘q’ follows the inversion of the data input ‘d’ and the scan output ‘sq’ is tied to logic 0. When SCAN is logic 1, the data output ‘q’ is tied to logic 1 and the scan output ‘sq’ follows the scan input (sd). According to this embodiment, average power over a number of ATPG shift cycles comes down as all the functional combinational logic does not toggle due to Q gating. Instantaneous peak power over the first shift cycle can be optimized by correctly choosing the type of flop for each logic block (pull-up or pull-down). This technique is extremely useful in case designers decide to convert only a subset of existing scan flops to this new design as then the peak/average power will depend upon the selection of “pull-up” or “pull-down” Q gating.

FIG. 21illustrates an example of a storage element other than the first storage element of the scan chain100according to an embodiment. The storage element2100may be an example of any of the storage elements1002,1003. . . or100n, in cases where the scan ‘sd’ received by the storage element2100is pull-down in the functional mode. For instance, the storage element2100is utilized when the scan output ‘sq’ (that is coupled to the scan input ‘sd’ of the storage element2100) provided by a preceding storage element (of the storage element2100) is pull-down in the functional mode (when SCAN is logic 0). For example, when SCAN is logic 0, the scan input ‘sd’ is logic 0.

The storage element2100includes a node145coupled to a scan output buffer450for driving the node415(scan output terminal). In this example embodiment, the node145is also coupled to the data output buffer250for driving the node225(data output terminal). The storage element2100includes the input circuit460that is configured to receive a data input (see, ‘d’) and a scan input (see, ‘sd’) from a data output ‘q’ and a scan output ‘sq’ of the preceding storage element, respectively. The input circuit460is configured to provide a signal corresponding to one of the data input ‘d’ and the scan input ‘sd’, at the node462. For instance, an inverse of the data input ‘d’ is provided at the node462in the shift mode (when SCANZ is logic 1), and an inverse of the scan input ‘sd’ is provided at the node462in the functional mode (when SCANZ is logic 0).

An output (for example, the node462) of the input circuit460is connected to the shifting circuit150that is configured to transfer a signal corresponding to the node462to the node145. The input of the data output buffer650is connected to the node145and the output of the data output buffer650is connected to the node625(the data output terminal). Data output (q) of the storage element2100is taken from the node625. The scan output buffer450is also connected to the node145. As described in reference toFIG. 8, the scan output buffer450includes the PMOS transistor405(first MOS transistor) and the NMOS transistor410(second MOS transistor) (forming a transmission gate) followed by the pull-down NMOS transistor420. The transistor420to act as a pull-down transistor in functional mode (when SCANZ is logic 1), as the transistors405and410are disabled in the functional mode. In the shift mode (when SCANZ is logic 0), the transistor420is disabled; and the transmission gate is enabled and provides the value of the node145to the node415.

The operation of the storage element2100is now explained. The input circuit460causes a signal corresponding to one of the data input ‘d’ and the scan input ‘sd’, to be transferred at the node462. It should be noted that the scan input ‘sd’ is logic 0, when the SCAN is logic 0. For instance, a scan output ‘sq’ of a preceding storage element (such as the storage element200) of the storage element2100is pull-down when the SCAN is logic 0, and this pull-down logic 0 is fed to the scan input ‘sd’ of the storage element2100. When the SCAN is logic 1, the scan input ‘sd’ may have either of logic 0 or logic 1 depending upon the test data and value as received from the preceding storage element. As described in reference toFIG. 5, when SCAN is logic 0, an inverse of the data input is transferred at the node462, and when SCAN is logic 1, an inverse of the scan input ‘sd’ is transferred at the node462.

In functional mode (when SCAN is logic 0 or SCANZ is logic 1), the scan input ‘sd’ is logic 0, so the transistor475and490are disabled, and the transistors465and480are enabled. Accordingly, the transistors465,470,480and485form an inverter configuration, and an inverted logic level of ‘d’ is transferred to the node462. Assuming that ‘d’ is set to logic 1, then inverse of ‘d’, for example, logic 0 will then be available at the node462. The shifting circuit150is configured to force a logic level at the node145that is the inverse of value at the node462. For example, logic 1 is transferred at the output of inverter120of the shifting circuit145. When CLK is low the transmission gate125becomes transparent and the logic 1 at the input of transmission gets transferred to the node195, forcing the output of the inverter130(node197) to be logic 0. When CLK becomes high the transmission gate125becomes transparent which transfers the value at the node197(logic 0) to the inverter120. The inverter120forces logic 1 on the node195. Another transmission gate135in enabled when CLK becomes high and hence transfers the value at the node197(logic 0) to the inverter140. The inverter140forces logic 1 on the node145. The inverter185, the transmission gate190and the inverter146comprise a loop back path when CLK is logic 0 and helps to retain the value at the node145. The data output buffer650inverts the value at the node145and forces a logic 0 at the node625. As SCAN is logic 0, the transistor620is disabled, and the transistors605,610and615form an inverter configuration, thereby transferring the inverted value of the node145(for example, a logic 0) at the node625. The data output is taken from the node625(that is the data output terminal) as inverse of the data input ‘d’. As SCAN is logic 0, the transmission gate formed by the transistors405and410isolates the node415from node145. At the same time the transistor420is enabled which then pulls-down the node415to logic 0 irrespective of the clock signal CLK in functional mode. The scan output terminal is coupled to the node415. Accordingly, in the functional mode (when SCAN is logic 0), the scan output ‘sq’ is tied to logic 0 (this may help in power reduction in the functional mode due to combinational logic switching in scan path which is driven by the scan output terminal). The scan enable input (SCANZ) acts as a control signal, which decides whether to tie the scan output terminal ‘sq’ to logic 1 or not. Accordingly, when SCAN is logic 0, the data output ‘q’ follows the inverse of the data input ‘d’ and the scan output ‘sq’ is tied to logic 0 (i.e., pull-down).

In shift mode (when SCAN is logic 1 or SCANZ is logic 0), the transistor480is disabled, and the transistors465,475(pull-up) and transistors490(pull-down) form an inverter configuration, and an inverse of the scan input ‘sd’ is transferred to the node462. It should be further be noted that when SCAN is logic 1, the scan output buffer450acts as a transmission gate buffer, as the transistor420is disabled and the transmission gate formed by the transistors405and410transfers the value present at the node145to the node415. The shifting circuit150is configured to force a logic level at the node145that is the inverse of the node462. For instance, if the scan input ‘sd’ is logic 1 (provided the SCAN is logic 1), the node462is at logic 0, and the node145is at logic 1. The scan output buffer450then transfers logic 1 at the node415that is coupled to the scan output ‘sq’. Accordingly, the scan input ‘sd’ is transferred to the scan output ‘sq’ when the IC operates in the shift mode. As SCAN is logic 1, the transistor215is disabled causing disabling the inverter comprised by transistors205and210. The transistor620is enabled and pulls-down the node625(the data output terminal) in response to SCANZ being logic 1. It is noted that transistor605is configured to protect leakage current through the inverter (formed by the transistors610and615) when the data output terminal is pull-down.

In shift mode, the data output ‘q’ is tied to logic 0 (this will help in power reduction in shift mode due to combinational logic switching which is driven by data output terminal). The scan enable input (SCAN) acts as a control signal, which decides whether to tie the data output terminal ‘q’ to logic 0 or not. When SCAN is 0, the data output ‘q’ follows the inversion of the data input ‘d’ and the scan output ‘sq’ is tied to logic 0. When SCAN is logic 1, the data output ‘q’ is tied to logic 0 and the scan output ‘sq’ follows the scan input (sd). According to this embodiment, average power over a number of ATPG shift cycles comes down as all the functional combinational logic does not toggle due to ‘q’ gating. Instantaneous peak power over the first shift cycle can be optimized by correctly choosing the type of flop for each logic block (pull-up or pull-down). This technique is extremely useful in case designers decide to convert only a subset of existing scan flops to this new design as then the peak/average power will depend upon the selection of “pull-up” or “pull-down” ‘q’ gating.

Various embodiments also provide a method2200for operating a scannable storage element in a scan chain (for example, the scan chain100) an IC is provided. Examples of the scannable storage element may be the scannable storage elements described in reference toFIGS. 4-21. At2205, the method2200includes generating a first signal at a first node of the scannable storage element in response of one of a data input and a scan input. In an embodiment, the scan input may be one of a pull-up and a pull-down logic in a functional mode of testing the IC. In an embodiment, generating the first signal may include providing a first pull-up path comprising a first switch to receive the data input and a second switch to receive a scan enable input and providing a second pull-up path comprising a third switch to receive the scan input, where the first pull-up path and the second pull-up path are coupled between a power supply and the first node. In this embodiment, generating the first signal also includes providing a first pull-down path comprising a fourth switch to receive the scan enable input and a fifth switch to receive the scan input, and providing a second pull-down path comprising a sixth switch to receive the data input, wherein the first pull-down path and the second pull-down path are coupled between the first node and a reference supply. Examples of the first to sixth switches may include MOS transistors or any other electronics/electrical components or a combination of components that may be functionally analogous to the MOS transistors.

In another embodiment, generating the first signal may include providing a first pull-up path comprising a first switch to receive the scan input and a second switch to receive the data input and providing a second pull-up path comprising the first switch and a third switch to receive an inverted scan enable input, where the first pull-up path and the second pull-up path are coupled between a power supply and the first node. In this embodiment, generating the first signal may also include providing a first pull-down path comprising a fourth switch to receive the inverted scan enable input and a fifth switch to receive the data input, and providing a second pull-down path comprising a sixth switch to receive the scan input, where the first pull-down path and the second pull-down path are coupled between the first node and a reference supply. Examples of the first to sixth switches may include MOS transistors or any other electronics/electrical components or a combination of components that may be functionally analogous to the MOS transistors.

At2210, the method2200includes generating a second signal by one or more sequential elements in response to the first signal at a second node of the scannable storage element. Further, at2215, the method2200includes generating a scan output at a scan output terminal of the scannable storage element in response to the second signal, wherein the scan output is one of a pull-up logic and a pull-down logic in the functional mode and the scan output corresponds to the scan input in a shift mode. At2220, the method2200further includes generating a data output in response to the second signal at a data output terminal.

Various embodiments of the present disclosure, as discussed above, may be practiced with steps and/or operations in a different order, and/or with hardware elements in configurations which are different than those which are disclosed. Therefore, although the technology has been described based upon these exemplary embodiments, it is noted that certain modifications, variations, and alternative constructions are apparent and well within the spirit and scope of the technology. Although various exemplary embodiments of the present technology are described herein in a language specific to structural features and/or methodological acts, the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as exemplary forms of implementing the claims.