Substrate bias control circuit for system on chip

A substrate bias control circuit includes a process voltage temperature (PVT) effect transducer that responds to a PVT effect. A PVT effect quantifier is coupled to the PVT effect transducer. The PVT effect quantifier quantifies the PVT effect to provide an output. The PVT effect quantifier includes at least one counter and a period generator. The period generator provides a time period for the counter. A bias controller that is coupled to PVT effect quantifier is configured to receive the output of the PVT effect quantifier. The bias controller is configured to provide a bias voltage. The bias controller includes a bias voltage comparator.

TECHNICAL FIELD

The present disclosure relates generally to an integrated circuit, more particularly a substrate bias control circuit.

BACKGROUND

A conventional substrate bias control circuit uses a phase detector circuit to measure process voltage temperature (PVT) effect. However, because this circuit is generally a combination of digital and analog circuits, it is not easy to be integrated in a system on chip (SOC) design. Also, it is not easy to migrate to other technology node as the integrated circuit scale shrinks. Accordingly, new substrate bias control circuits are desired.

DETAILED DESCRIPTION

An exemplary circuit that is described in the disclosure is configured to provide an appropriate substrate bias (based on PVT variation) to adjust chip performance and power consumption. The circuit can be easily integrated in an SOC design. If the substrate of a metal-oxide-semiconductor field-effect transistor (MOSFET) device is backward biased, power consumption of the devices can be saved. If the substrate of a MOSFET device is forward biased, speed of the devices can be boosted.

FIG. 1illustrates a schematic drawing of an exemplary substrate bias control circuit. The substrate bias control circuit100includes a PVT effect transducer102, a PVT effect quantifier104, and a bias controller106. The PVT effect transducer102responds to the PVT environment change and shows a corresponding physical characteristic change that can be measured, e.g. a frequency change of a ring oscillator. The PVT effect transducer102is coupled to the PVT effect quantifier104.

The PVT effect quantifier104quantifies the physical characteristic change that is detected from the PVT effect transducer102. For example, pulses from a ring oscillator can be counted during a specified time to show its frequency change due to PVT variations. The PVT effect quantifier104is coupled to the bias controller106.

The bias controller106receives the quantified output from the PVT effect quantifier104and controls the substrate bias voltages VPPand VBBfor a p-channel MOSFET (PMOS) transistor108and an n-channel MOSFET (NMOS) transistor110, respectively. The bias controller106can have a programmable or configurable input for threshold values or lookup table for its decision-making.

FIG. 2illustrates an exemplary embodiment of the substrate bias control circuit. InFIG. 2, the PVT effect transducer102includes ring oscillators202. The ring oscillators202generate pulses at certain frequencies and include an odd number of inverters. Each inverter contributes to the delay of the signal passing the ring of inverters. Changing the power supply voltage changes the delay through each inverter, and thus changes the oscillator frequency. For example, higher voltages typically decreasing the delay and increasing the oscillator frequency. The frequencies of the ring oscillators202reflect the PVT environment variations.

In some embodiments, the PVT effect quantifier104includes at least one counter, e.g. counters204, and a period generator206. The period generator206provides a time period for the counters204. The counters204are connected to ring oscillators202. The counters204provide counter values of each ring oscillator202during the time period generated by the period generator206.

The PVT effect quantifier104can further include a counter comparator208, and the counter comparator208compares counter values from each counter204and selects one counter value as the output of the PVT effect quantifier104. The selection of one counter value can be according to any desired criteria, e.g. a median (typical) value, the highest (fastest) value, the lowest (slowest) value, etc.

In some embodiments, the counter comparator208is optional. For example, if only one ring oscillator202and one counter204are used, then the counter comparator208can be saved and the counter value is sent to the bias controller106as the output of the PVT effect quantifier104.

The bias controller106includes bias voltage comparators210and211. The bias controller106can use the output of the PVT effect quantifier104to determine the bias voltages VPPand VBB. When the count value is higher than a high threshold value, then a backward bias for the substrate of a MOSFET device can be used to save power. When the count value is lower than the low threshold value, a forward bias can be used to boost performance. Device characterization data can be used to determine the high/low threshold values. For example, the device characterization data can relate to the count value and corresponding high/low threshold values. The bias voltage comparators210and211can be merged into one bias voltage comparator.

More particularly, the bias voltage comparator210compares the output received from the PVT effect quantifier104to a high threshold value. If the output is higher than the high threshold value, the VPP/VBBcontroller212in the bias controller106increases the bias voltage VPPfor PMOS transistor108. The bias voltage VPPis connected to the substrate of the PMOS transistor108. The increase or decrease step value can be programmed. For example, a 50 mV step can be used in one embodiment.

The bias voltage comparator210compares the output received from the PVT effect quantifier104to a low threshold value. If the output is lower than the low threshold value, the VPP/VBBcontroller212in the bias controller106decreases the bias voltage VPPfor PMOS transistor108.

The bias voltage comparator211compares the output received from the PVT effect quantifier104to a high threshold value. If the output is higher than the high threshold value, the VPP/VBBcontroller212in the bias controller106decreases the bias voltage VBBfor NMOS transistor110. The bias voltage VBBis connected to the substrate of an NMOS transistor110.

The bias voltage comparator211compares the output received from the PVT effect quantifier104to a low threshold value. If the output is lower than the low threshold value, the VPP/VBBcontroller212in the bias controller106increases the bias voltage VBBfor NMOS transistor110.

The embodiment inFIG. 2can be referred to as a closed-loop adaptive substrate bias control circuit in the sense that the bias voltages are continuously adjusted and updated based on the comparison with programmable or configurable threshold values.

FIG. 3illustrates another exemplary embodiment of the substrate bias control circuit. The PVT effect transducer102and the PVT effect quantifier104have similar components as the embodiment shown inFIG. 2. However, the bias controller106has a programmable or configurable bias voltage lookup table302instead of the bias voltage comparators210and211. The bias voltage lookup table302can be updated through an outside input.

In one embodiment, the bias voltage lookup table302can include reference values for the output of the PVT effect quantifier104and VPP/VBBtarget values that correspond to the reference values. In the bias controller106, the output from the PVT effect quantifier104can be compared to the reference values in the bias voltage lookup table302, and corresponding VPP/VBBtarget values can be used to control the substrate bias voltages for PMOS transistor108and NMOS transistor110.

The embodiment inFIG. 3can be referred to as an open-loop adaptive substrate bias control circuit in the sense that the bias voltages can be adjusted at once to the target values, based on the reference values in the bias voltage lookup table302.

FIG. 4illustrates an exemplary bias voltage lookup table associated with the exemplary embodiment of the substrate bias control circuit inFIG. 3. Entry A in the first row includes a typical corner ring oscillator count value as the reference value and Voltage A as the VPP/VBBtarget value. Field of Voltage A contains two target values for VPPand VBB, respectively. The typical corner refers to a portion of integrated circuits on a semiconductor wafer that shows typical NMOS/PMOS transistor performances. Entry B in the second row includes a fast-fast (FF) corner ring oscillator count value as the reference value and Voltage B as the VPP/VBBtarget value. Field of Voltage B contains two target values for VPPand VBB, respectively. The FF corner refers to a portion of integrated circuits on a semiconductor wafer that shows relatively fast NMOS/PMOS transistor performances.

If the count value from PVT effect quantifier104is higher than the entry A's ring oscillator count value, but lower than entry B's ring oscillator count value, then the bias controller106can use Voltage A as the target voltage. If the count value from PVT effect quantifier104is higher than entry B's ring oscillator count value, the bias controller106can use Voltage B as the target voltage. In this simple example, the count value is assumed to be higher than the entry A's ring oscillator count value. Even though one embodiment of the bias voltage lookup table is described above for illustration, the bias voltage lookup table may include different formats and different values, and the bias controller106can use different algorithms in embodiments.

FIG. 5Aillustrates a schematic drawing of an exemplary implementation of the substrate bias control circuit on a SOC chip. The SOC chip502includes a power domain504and closed/open-loop bias control circuit506. The power domain504includes the PVT effect transducer102and other integrated circuits, e.g. memories, logics, NMOS transistors, PMOS transistors, etc. The PVT effect transducer102is located on the SOC chip502where the PVT effects need to be monitored, because PVT effects can affect the integrated circuit performance. The closed/open-loop bias control circuit506includes the PVT effect quantifier104and the bias controller106inFIG. 1. The bias controller106can be either a closed-loop adaptive substrate bias control circuit as shown inFIG. 2, or an open-loop adaptive substrate bias control circuit as shown inFIG. 3. The functions of the PVT effect transducer102, PVT effect quantifier104, and bias controller106are the same as described above.

FIG. 5Billustrates a schematic drawing of another exemplary implementation of the substrate bias control circuit on a SOC chip. The SOC chip508includes two separate power domains510and514and two separate closed/open-loop bias control circuits512and516. Each closed/open-loop bias control circuit512or516includes the PVT effect quantifier104and the bias controller106. Each of the two power domains510or514includes a separate PVT effect transducer102, because different location on the SOC chip508can be subject to different PVT effects. Based on the local PVT effects monitored by the PVT effect transducer102, separate closed/open-loop bias control circuits512and516can adjust the bias voltages separately. The functions of the PVT effect transducer102, PVT effect quantifier104, and bias controller106are the same as described above.

The substrate bias voltage control circuit described above can be implemented solely by logic circuit process, and thus it can be easily integrated in an SOC design. Also programmable or configurable input for threshold values and bias voltage lookup tables allows easy fine-tuning. The methodology described in the present disclosure can be migrated to any technology node easily. A person skilled in the art will appreciate that there can be many embodiment variations for disclosed embodiments.