Die seal layout for VFTL dual damascene in a semiconductor device

A semiconductor may include several vias located in an active region and a die seal region. In the active region, a photoresist can be patterned with openings corresponding to the vias. In the die seal area, however, the photoresist can be patterned to overlap the vias. With this configuration, an underlayer etch will not affect an underlayer resist in the die seal area, allowing the die seal area to be disregarded for purposes of calculating a process window.

BACKGROUND

1. Technical Field

The disclosure generally relates to formation of semiconductor elements, and specifically to performing a via first trench last (VFTL) process in a die seal area of a semiconductor device.

2. Related Art

In semiconductor device manufacturing, it is often necessary to use metal fill technology to form metal in a dielectric trench and via for interconnecting different layers and/or different metal materials in the semiconductor device. One such metal fill process is commonly referred to as a “damascene” process, in which dielectric layers are first etched, and then filled with a desired metal material. There are two types of commonly-used damascene processes: (1) single damascene—separately etching and filling a trench (used for inter-level connections) and a via (used for intra-level connections); and (2) dual damascene—etching the trench and via, and then filling them together at the same time. Generally, dual damascene is preferred over single damascene processes due to reduced manufacturing costs, etc.FIG. 1Aillustrates an preferred semiconductor cross-section after an ideal dual damascene etch. However, various process conditions often cause resulting profiles to be deviated from the desired profile. For purposes of the following discussion,FIGS. 1B and 1Cillustrate exemplary semiconductor devices that result from conventional dual damascene processes, and which include an upper dielectric130, a lower dielectric120, a via150, and a trench155.

There are two preferred types of dual damascene processes that are common in the industry: Trench first via last (TFVL) and via first trench last (VFTL). In TFVL, as its name implies, the trench is etched prior to the via. For example, a first mask is used to define a width of the trench. The device is then etched, using the first mask as a guide to etch the trench in an upper dielectric. Following the creation of the trench, a second mask is patterned within the trench to define a width of the via. A second etch is then performed, using the second mask as a guide, to form the via in a lower dielectric. Once the trench and via have been formed, they are filled with a metal material, such as copper, for example. In VFTL, on the other hand, the via is etched before the trench. In particular, a first mask is used to define the width of the via. The via is formed by etching, using the first mask as a guide, through both an upper and lower dielectric. Once the via has been formed, a spin-on planarization process are used to fill the via holes and provide better pattern process windows. Usually, spin on organic (e.g., resist or organic BARC) or dielectric materials (e.g., spin-on-glass (SOG) or spin on low k materials) are used to fill the via holes and to planarize the wafer surface. After surface planarization, a second mask is formed over the upper dielectric to define a width of the trench. The trench is then formed by etching, using the second mask as a guide, through only the upper dielectric.

As mentioned above, in these conventional VFTL processes a planarization step using a spin technique is used to fill the via holes and to planarize the wafer surface. As a result, the spin-on underlayer may not have uniform thickness among all areas of the semiconductor device. For example, the spin on layer may be thicker in isolated via holes or areas having no vias of the semiconductor device and thinner in the area where via holes are more dense. The thinnest spin on layer will be in a die seal area (e.g., an area of the semiconductor die having a continuous trench line located at the edge of the device area, which is used to stop cracks caused during a cutting process from harming the functional areas), where the trenches are larger and require more spin on materials to fill the trench holes. As a result of the non-uniform coating of the spin on layer, a subsequent etching process may cause defects in the semiconductor device that can greatly affect performance.

For example,FIG. 1Aillustrates a side view of the desired semiconductor device profile resulting from a VFTL process.FIGS. 1B and 1Cillustrate deviations from the desirable profile and can be easily found in many semiconductor devices that employ VFTL approaches. In each area, an etch-stop layer115, a via tetraethylorthosilicate (TEOS) layer120(e.g., lower dielectric layer), a silicon layer125, a trench TEOS layer130(e.g., upper dielectric layer), and a silicon-rich nitride layer135are formed over a substrate110, separated by a via150and a trench155.

As shown inFIG. 1B, when the spin on layer is too thick, the subsequent etching of the conventional processes produces undesired fencings190in the final structure. Similarly, as shown inFIG. 1C, when the spin on layer is too shallow, the etching of the conventional processes produces undesired sub-trenches195. Both the fencings190and the sub-trenches195can cause reliability concerns and defects, which will greatly affect performance of the device. Therefore, it is desired to perform the VFTL processes in a manner that can prevent the formation of these defects in order to enhance device performance and manufacturing yield.

BRIEF SUMMARY OF THE INVENTION

In the VFTL dual damascene process, a first mask (via mask) will include the via holes and die seal openings. The subsequent via etch process will etch vias and die seals through both top and bottom dielectric layers. However, a second mask (metal trench mask) will only open the trench lines in the device area without opening die seals. With this configuration, a subsequent trench etch process will not damage trench corners or cause contamination issues near the die seal area, allowing the die seal area to be disregarded for purposes of calculating a process window.

DETAILED DESCRIPTION

The exemplary embodiments described herein are provided for illustrative purposes, and are not limiting. Other exemplary embodiments are possible, and modifications may be made to the exemplary embodiments within the spirit and scope of the disclosure. Therefore, the Detailed Description is not meant to limit the invention. Rather, the scope of the invention is defined only in accordance with the following claims and their equivalents.

Those skilled in the relevant art(s) will recognize that this description may be applicable to many various semiconductor devices, and should not be limited to flash memory devices, or any other particular type of semiconductor devices. In addition, the following descriptions specifically relate to resist etch back process flow. However, the disclosure can similarly be applied to each of the conventional bi-layer resist and tri-layer dual damascene process flows to achieve similar beneficial results.

An Exemplary Semiconductor Device

As discussed above, sub-trenches and fencings are defects caused by varying underlayer resist layer thickness across a semiconductor device. Although the thickness varies within an active area of the semiconductor device, the greatest variation is between the active area and a die seal area (located near an edge of the semiconductor device). Therefore, by eliminating the need to adjust the underlayer etch to account for the die seal area, the process window can be substantially reduced, thereby greatly increasing manufacturing yield and device performance.

For example,FIG. 6illustrates a semiconductor die600that includes a plurality of semiconductor chips610which are to become the semiconductor devices. As shown in the magnified view ofFIG. 6, a semiconductor chip610A includes a die seal area612around a perimeter of an active area614. The die seal area612can be used to protect the active area614during cutting of the individual semiconductor chip610A.

Die Seal Area

FIGS. 2A-2Hillustrate cross-sectional views of a die seal area612of an exemplary semiconductor device201according to an embodiment. The semiconductor device201includes an etch-stop layer215layered over a substrate210. In embodiments, the substrate210can be a bulk silicon substrate or an intermediate metal layer formed over a substrate. A TEOS layer220, a silicon nitride layer (trench etch stop layer)225, a trench TEOS layer230, and a silicon-rich nitride (anti-reflect coating) layer235are formed over the etch-stop layer215, and are separated by trench250.

In the die seal area612, an underlayer resist layer260is spun on the wafers to fill the trench250and to planarize the wafer surface. An underlayer (UL) resist etch back process is used to remove the resist on top of SiRN (silicon-rich nitride) surface235. As shown inFIG. 2C, the UL resist exists in the die seal area and trench holes only after UL resist etch back, and photoresist patterning process is used to define the trench line. At this time, die seal area is not open during resist patterning process. In particular, as shown inFIG. 2D, a metal resist265is deposited over the trench hole.

In an embodiment, during the trench oxide etch process, since the die seal is protected by photoresist, as shown inFIG. 2E, the die seal area will not be damaged by trench etch process. Instead, the trench oxide etch process will etch a portion of the metal resist265. No additional etch particles can be created in the die seal area and cause yield loss.

In a subsequent step of the VFTL process, an ash and SiN etch is performed on the semiconductor device201. As one skilled in the art will readily recognize, “ashing” is the general process of using a plasma containing oxygen to oxidize (“ash”) a photoresist in order to facilitate its removal. The ash+SiN etch removes the remaining underlayer resist layer260from the die seal area612(as shown inFIG. 2F), as well as the etch-stop layer215from the trench250(as shown inFIG. 2G).

As can be seen inFIG. 2G, this process results in a die seal area612without any sub-trenches or fencings. Once the trench has been prepared according to the method described above, the trench can be filled with a barrier layer275and a metal conductor material270(e.g., metal) to complete the semiconductor device. Further, as will be shown below with respect toFIGS. 3A-3I, by performing the same steps on the active area614with a different structural configuration from that of the die seal area612, sub-trenches and fencing can likewise be avoided in the active area.

Active Area

FIGS. 3A-3Iare side views of an active area614of the exemplary semiconductor device201according to an embodiment. Like the die seal area612, the semiconductor device201in the active area614also includes an etch-stop layer215layered over a substrate210. A via TEOS layer220, a silicon nitride (SiN) layer225, a trench TEOS layer230, and a silicon-rich nitride (SiRN) layer235are formed over the etch-stop layer215, and are separated by via350. In addition, an underlayer resist layer260is spun on the wafer surface to fill the via350and planarize the wafer surface. A UL resist etch back process is used to remove the resist on top of the SiRN layer surface. Additional resist etch will be used to optimize the recess of the resist in the via holes and prevent fencing and sub-trenching that can occur in the active area. Since seal area (thinnest UL resist area) will not be open during trench patterning, the underlayer resist etch back optimization will be easier and the process window will be significantly wider. After etch back, UL resist can only be found in the via holes with proper recesses to provide minimal fencing and sub-trenching at the via corner, as shown for example inFIG. 3C. A second resist (e.g., a metal resist)265is then formed over the area (FIG. 3D) and a resist patterning process is used to define trench lines in the active area, as shown inFIG. 3E. Since die seal area is not open during the resist patterning process, the die seal structure is protected by a photoresist during the subsequent trench oxide etch process.

In conventional VFTL processes, the defects are substantially created during this trench oxide etch step. However, the main cause of the defects is due to the inadequate resist recess in the via holes. Specifically, the difference in thickness between the underlayer resist layer260in the active area614and that of the underlayer resist layer260in the die seal area612required a choice to be made. By choosing to etch the thicker underlayer resist layer in the active area614to a preferred height, the thinner underlayer resist layer in the die seal area612became overetched and resulted in sub-trenches, as shown inFIG. 1C. Alternatively, choosing to etch the thinner underlayer resist layer in the die seal area612to a preferred height resulted in the thicker underlayer resist layer in the active layer614being underetched, which resulted in fencings. Because the trench oxide etch does not affect the die seal area612in this embodiment, the underlayer etch can be performed as preferred in the active area614without negatively affecting the die seal area612.

Therefore, as shown inFIG. 3C, the underlayer etch etches the underlayer resist layer260to a preferred or predetermined height in the via holes. In an embodiment, the preferred height of the underlayer resist layer260after the underlayer etch is approximately even with an upper surface of the silicon nitride layer225.

As shown inFIG. 3F, the trench oxide etching step etches the silicon-rich nitride layer235and the trench TEOS layer230at the opening of the second resist265to form a trench355. As shown inFIG. 3F, this TEOS etching step no longer results in the sub-trenches present in the conventionally-processed semiconductor device.

As shown inFIGS. 3G and 3H, the subsequent ash+SiN etching removes the remaining underlayer resist layer260from the active area, as well as the portion of the etch-stop layer215within the via350. The result of this process is an active area that lacks both sub-trenches and fencings. Once the trench355and via350have been prepared, the via350and trench355can be filled with a barrier layer275and a metal conductor material270, as shown inFIG. 3I. At least the metal conductor material270can be deposited in a single deposition so as to be continuous between the via350and the trench355.

In summary, using the above-described method, a semiconductor device can be manufactured with greater ease because the process window has been widen by effectively making the die seal area immaterial during the initial underlayer etching step. As a result, the semiconductor device can be manufactured at lower cost and with greater yield.

FIG. 7illustrates a cross-sectional view of an exemplary semiconductor device700according to an embodiment. The semiconductor device700illustrated inFIG. 7is provided only for the purpose of comparing the resulting structural configuration of the active area versus that of the die seal area, and omits several details not necessary for this purpose.

As shown inFIG. 7, a substrate750is provided in both the active area and the die seal area. The active area includes a dual damascene structure formed over the substrate750in which a dielectric740is etched to have a trench720formed over top of a via710. Both the trench720and the via710are filled with a continuous metal material730. The die seal area, does not include the dual damascene structure, but rather includes a single trench760that is not coupled with a via formed in the dielectric740. This trench760is filled with a continuous metal material770. The metal material770may be the same or different material as the metal material730, and may be formed simultaneous with or at a different time from the metal material730.

Exemplary Method for Performing VFTL in a Semiconductor Device to Prevent Sub-Trenches or Fencings

FIG. 4illustrates a flowchart400of a method for performing VFTL in a semiconductor device, according to an embodiment. For illustration purposes, flowchart400is described with continued reference toFIGS. 2A-2Gand/or3A-3I, although method400is not limited to these examples.

In step410, referring toFIG. 2B, an underlayer resist260is spun over the via350in the active and the trench250in the die seal area. As shown inFIGS. 2B and 3B, the underlayer resist260is deposited so as to fill the via350and the trench250and cover an upper surface of the die.

In step420, a UL resist etch back is performed. Referring toFIGS. 2C and 3C, the UL etch is more recessed in the die seal area as compared to the active area. Meanwhile, referring toFIG. 3C, the UL etch removes a portion of the underlayer resist layer260within the via350in the active area. The etch is preferably performed to reduce the underlayer resist layer260in the active area to a preferred height. In an embodiment, the underlayer resist layer260is etched in the active area to be approximately even with an upper surface of silicon layer225, at least in the active area.

In step430, a resist patterning process is used to define trench lines (FIG. 3E) in the active area. During the resist patterning process, the die seal area will be covered with resist (FIG. 2D).

In step440, a dielectric etch is performed to form a dual damascene structure on the active area of the wafer. Referring toFIG. 2E, the trench250in the die seal area is protected by the resist it will not be etched away during this process step. Referring toFIG. 3F, the trench etch removes both silicon-rich nitride layer235and trench TEOS layer230from within the opening of the photoresist380to form the trench355.

In step450, an ash+SiN etch is performed. Referring to FIGS.2F/2G and3G/3H, this process removes any remaining underlayer resist layer260and exposes SiRN and SiN layers (235,225, and215). The result of this method is a die seal area (e.g.,FIG. 2D) that lacks sub-trenches or fencings within its trench250, and an active area (e.g.,FIG. 3G) that lacks sub-trenches or fencings within its via350and/or trench355.

Those skilled in the relevant art(s) will recognize that the above method can additionally or alternatively include any of the steps or substeps described above with respect toFIGS. 2A-2Hand/or3A-3I, as well as any of their modifications. Further, the above description of the exemplary method should not be construed to limit the description of the method depicted in FIGS.2A-H2G and/or3A-3I described above.

Exemplary Apparatus for Performing VFTL in a Semiconductor Device to Prevent Sub-Trenches or Fencings

FIG. 5illustrates a block diagram of an exemplary apparatus for performing VFTL in a semiconductor device, according to an embodiment. The apparatus500includes a photoresist module510, a UL resist etching module520, a dielectric etching module530, and an ash+SiN etching module540. For illustration purposes, apparatus500is described with continued reference toFIGS. 2A-2Hand/or3A-3I, although apparatus500is not limited to these examples.

The photoresist module510is configured to spin on a continuous photoresist layer260over a die seal area of a semiconductor device that covers the trenches250of the die seal area, and is also configured to deposit a photoresist layer380over an active area of the semiconductor device that has openings over the vias350of the active area. The widths of the openings of the photoresist380in the active area should be a preferred width of a trench355to be formed later.

The UL resist etching module520performs a UL etch of the semiconductor device. Referring toFIG. 2C, the resulting resist height in the die seal area trench250will be lower that the resist height in the active area vias250, but since the die seal area will be covered with resist during the trench etch process, the lower UL resist in the die seal area will not have any etch damage. Referring toFIG. 3C, the UL etch removes a portion of the underlayer resist layer260within the via350in the active area. The etch is preferably performed to reduce the underlayer resist layer260in the active area to a preferred height. In an embodiment, the underlayer resist layer260is etched in the active area to be approximately even with an upper surface of silicon layer225.

After UL etch, the wafer will go back to photoresist module510for trench patterning. At this time, the trench lines will be defined in the active area. As mentioned before, the die seal area will be covered with resist during this resist patterning process.

The dielectric etching module530is configured to perform a TEOS etch of the semiconductor device. Referring toFIG. 2E, the TEOS etch will not remove oxide in the die seal area since the resist exists in this area. Referring toFIG. 3F, the TEOS etch removes silicon-rich nitride layer235and trench TEOS layer230from within the opening of the photoresist380to form the trench355.

The ash+SiN etching module540is configured to perform an ash+SiN etch of the semiconductor device. Referring toFIGS. 2F and 3G, this resist ash process removes any remaining resist layer380and260from the wafer surface. Following the resist ash process, an SiN etch process will remove a top SiRN, trench and bottom SiN layers from the trench/via openings. The result of this method is a die seal area (e.g.,FIG. 2G) that lacks sub-trenches or fencings in its trenches250, and an active area (e.g.,FIG. 3H) that lacks sub-trenches or fencings within its vias350and/or trenches355. After Cu fill and CMP process, metal can be filled in the via and/or trench, as shown for example inFIG. 2Hfor the die seal area and inFIG. 3Ifor the active area of the semiconductor device.

Those skilled in the relevant art(s) will recognize that the above apparatus500can additionally or alternatively be configured to perform any of the steps or substeps described above with respect toFIGS. 2A-2Hand/or3A-3I, as well as any of their modifications. Further, the above description of the exemplary apparatus500should not be construed to limit the description of the method depicted inFIGS. 2A-2Hand/or3A-3I.

CONCLUSION