Hybrid fin field-effect transistor cell structures and related methods

In one embodiment, an integrated circuit cell includes a first circuit component and a second circuit component. The first circuit component includes fin field-effect transistors (finFETs) formed in a high fin portion of the integrated circuit cell, the high fin portion of the integrated circuit including a plurality of fin structures arranged in rows. The second circuit component that includes finFETs formed in a less fin portion of the integrated circuit cell, the less fin portion of the integrated circuit including a lesser number of fin structures than the high fin portion of the integrated circuit cell.

BACKGROUND

With increasing down-scaling of integrated circuits and increasingly demanding requirements for higher speed of integrated circuits, transistors need to have higher drive currents with increasingly smaller dimensions. Fin field-effect transistors (finFETs) were thus developed, and are often utilized to implement transistors and other devices in an integrated circuit.

DETAILED DESCRIPTION

A finFET typically includes a channel region implemented in a semiconductor “fin” structure and gate structures located adjacent to the fin structures. FinFETs have increased channel widths compared to planar transistors because the channels of a finFET include the sidewall portions in addition to the top surfaces of the fin structure. Since the drive current of a transistor is proportional to its channel widths, the drive currents of finFETs are increased over that of planar transistors. Drive current may be further increased in a finFET by including multiple fin structures. However, the inclusion of multiple fin structures may increase the power consumption and silicon footprint of the finFET. A standard cell library may therefore include both integrated circuit cells that utilize finFETs with multiple fin structures and other integrated circuit cells that utilize finFETs with a single (or lesser number) of fin structures. An integrated circuit designer may, for example, utilize standard cells with more or less fin structures depending on whether speed or power consumption is a more important factor for the particular circuit component.

FIGS.1A and1Brespectively show top and cross-sectional views of a portion of a hybrid finFET integrated circuit cell100. The integrated circuit cell100may, for example, be a standard cell structure for a primitive logic device or other higher-level circuit that is included in a standard cell library for use in the design of larger, more complicated integrated circuits. The integrated circuit cell100includes a plurality of fin field-effect transistors (finFETs) that are formed by the intersection of gate structures with rows of “fin” shaped channel regions (referred to herein as “fins” or “fin structures”). As detailed above, finFET devices may be formed using a single fin structure or using multiple fin structures.FIGS.1A and1B, as well as other diagrams described herein, illustrate rows of fins that are used to form the finFETs making up the integrated circuit cell100, but for simplicity omit the gate structures and other parts of the integrated circuit that are not relevant to the disclosure.

With reference first toFIG.1A, the hybrid integrated circuit cell100includes a high fin portion102(also referred to herein as a “high fin row”) and a less fin portion104(also referred to herein as a “less fin row”). The high fin portion102of the hybrid cell100includes fin rows106,108that each include multiple fin structures. The less fin portion104of the cell includes fin rows110,112that each include a lesser number of fin structures than the fin rows106,108of the high fin portion102. The difference in the number of fin structures in the fin rows of the high and less fin portions102,104of the hybrid cell100is illustrated inFIG.1A(and other diagrams described herein) by the thickness of the lines representing the fin rows. For example, the fin rows106,108in the high fin portion102ofFIG.1Aare drawn thicker than the fin rows110,112in the less fin portion104ofFIG.1A, indicating a larger number of fin structures in the fin rows106,108of the high fin portion102. This is further illustrated by the cross-section diagram shown inFIG.1B.

The cross-section shown inFIG.1Bis taken along line “a” inFIG.1A. The cross-sectional diagram ofFIG.1Bdepicts the fin structures106,108,110,112of the high and less fin rows102,104extending above the cell semiconductor substrate114. Also shown inFIG.1Bare shallow trench isolation (STI) regions116that are formed in the semiconductor substrate114to separate and isolate the different semiconductor regions. The example illustrated inFIG.1Bshows two fin structures in each of the fin rows106,108of the high fin portion102, and one fin structure in each of the fin rows110,112of the less fin portion104. In other examples, however, the high and less fin portions102,104of the hybrid cell100may have a greater number of fin structures, so long as the number of fins in each fin row of the high fin portion102is greater than the number of fins in each fin row of the less fin portion104.

FIG.2is a diagram of an example integrated circuit layout200. The example layout200shown inFIG.2utilizes three types of standard cells, respectively labeled Cell_A, Cell_B and Cell_C, that are each formed using finFETs. Specifically, the example standard cells labeled Cell_A are formed using only high fin rows202, the example standard cells labeled Cell_B are formed using only less fin rows204, and the example standard cell labeled Cell_C is a hybrid cell that is formed using both high and less fin rows202,204. In addition to differentiating the high and less fin rows based on the thickness of the fin rows,FIG.2also illustrates the difference in cell heights, HAand HB, resulting from the different number of fins. As shown, high fin rows take up more area on the integrated circuit, resulting in a larger cell height (HA). The illustrated hybrid standard cell (Cell_C) is referred to as a “double height” cell because it includes two adjacent fin rows202,204, i.e., with a cell height of HA+HB. The other illustrated standard cells (Cell_A and Cell_B) are referred to as “single height” cells because they each include only a single fin row, i.e., with a cell height of either HAor HB. The example hybrid cells described herein are each “double height” cells. It should be understood, however, that in other examples a hybrid cell could include more than two adjacent fin rows.

As detailed above, the number of fin structures in a finFET cell may have a direct effect on both the speed and power consumption of the integrated circuit, as well as the size of the cell's silicon footprint. A finFET cell with a greater number of fin structures will typically operate faster than the same circuit in a finFET cell with a fewer number of fin structures. But a cell with less fin structures often provides power and area benefits over cells with a greater number of fin structures. An integrated circuit designer may, therefore, layout an integrated circuit using standard cells with both high and less fin rows (e.g., Cell_A and Cell_B), as illustrated inFIG.2, depending on whether speed or power consumption is a more important factor for the particular circuit component.

A hybrid finFET cell, such as Cell_C depicted inFIG.2, may be utilized in an integrated circuit design to provide both the speed benefit of the high fin row202and the power and area benefit of the less fin row204. The example integrated circuit layouts depicted inFIGS.3-8provide examples of hybrid standard cells that are optimized for a desired performance. In many cases, these optimized hybrid cells are able to demonstrate better performance than the same circuits implemented using only high fin rows or only less fin rows.

FIGS.3A and3Bdepict an example hybrid finFET cell for a multi-stage buffer. A circuit diagram300of the multi-stage buffer is shown inFIG.3A, and the cell layout302for the multi-stage buffer is shown inFIG.3B. With reference first toFIG.3A, the multi-stage buffer includes a first inverter stage304having an output coupled to the input of a second inverter stage306. In operation, the multi-stage buffer300receives an input (I) and generates a buffered output (Z).

Cross referencingFIGS.3A and3B, the first inverter stage304is included in a less fin row308of the hybrid cell layout302, and the second inverter stage306is included in a high fin row310of the hybrid cell layout302. Implementing the multi-stage buffer300in a double height (HA+HB) cell302with the first inverter stage304in a less fin row308and the second inverter stage306in a high fin row310affects the driving ratio of the circuit. The inventors have concluded that the resultant driving ratio of the first and second inverter stages304,306in the illustrated hybrid cell layout302may improve circuit performance (speed) over that of the same circuit300implemented in a single height cell with only a high fin row (HA). For example, the inventors found an approximate 2-5% improvement in speed over a previous design implemented in a single height cell with only a high fin row (HA).

FIGS.4A and4Bdepict an example hybrid finFET cell for a multi-stage logic gate. A circuit diagram400of the multi-stage logic gate is shown inFIG.4A, and the cell layout402is shown inFIG.4B. With reference first toFIG.4A, the multi-stage logic gate400includes a NAND gate stage404having an output coupled to the input of an inverter stage406. In operation, the multi-stage logic gate400generates an output (Z) that is a logic combination of its inputs (A1, A2).

Cross referencingFIGS.4A and4B, the NAND gate404is included in a high fin row408of the hybrid cell layout402, and the inverter stage406is implemented in both the high fin row408and a less fin row410. Implementing the multi-stage logic gate400in a double height (HA+HB) cell402, as shown, may improve circuit performance (speed) over that of the same circuit400implemented in a single height cell with only a high fin row (HA). For example, the inventors found an approximate 1-4% improvement in speed over a previous design implemented in a single height cell with only a high fin row (HA). This improvement results, at least in part, because placing the NAND gate404in a high fin row408compensates for the weak driving effect of cascade transistors in the NAND gate404.

FIGS.5A and5Bdepict another example hybrid finFET cell for a multi-stage logic gate. A circuit diagram500of the multi-stage logic gate is shown inFIG.5A, and the cell layout502is shown inFIG.5B. With reference first toFIG.5A, the multi-stage logic gate500includes an inverter stage504having an output coupled to an input of a NAND gate stage506. In operation, the multi-stage logic gate500generates an output (ZN) that is a logic combination of its inputs (Ā, B).

Cross referencingFIGS.5A and5B, the NAND gate506is included in a high fin row508of the hybrid cell layout502, and the inverter stage504is included in a less fin row510. Implementing the multi-stage logic gate500in a double height (HA+HB) cell502, as shown, may improve circuit performance (speed) over that of the same circuit500implemented in a single height cell with only a high fin row (HA). For example, the inventors found an approximate 1-3% improvement in speed over a previous design implemented in a single height cell with only a high fin row (HA).

FIGS.6A and6Bdepict an example hybrid finFET cell for a scan flip-flop circuit that is optimized for speed. A circuit diagram600of the scan flip-flop circuit is shown inFIG.6A, and the cell layout602for the scan flip-flop circuit is shown atFIG.6B. A scan flip-flop, such as the example depicted inFIG.6A, is one of the most frequently adopted standard cells. In operation, a scan flip-flop may be switched between a normal operation mode and a scan test mode. With reference first toFIG.6A, the architecture of the scan flip-flop600is equivalent to a multiplexer (P1) followed by a master-slave flip-flop (P2-P6). The scan flip-flop circuit600further includes a multi-stage inverter (P8-P9), where the first inverter stage (P8) inverts clock signal CP to generate clock signal CKB, and the second inverter stage (P9) inverts clock signal CKB to generate clock signal CKBB. Also included in the scan flip-flop circuit600is an inverter (P7) that inverts the signal at the terminal SE to generate an output at terminal SEB.

When the scan flip-flop600operates in scan test mode, the terminal SE is raised to a high logic level so that transistors604,606within the multiplexer (P1) are turned on and transistors608,610are turned off, and the voltage at node612can be controlled by the signal at scan chain terminal SI. When the scan flip-flop600operates in normal operation mode, the terminal SE is pulled down to a low logic level, causing transistors608,610within the multiplexer (P1) to turn on and transistors604,606to turn off, and the voltage at node612can be controlled by the signal at terminal D in a normal flip-flop mode.

The flip-flop portion of the circuit600includes five stages, P2-P6. In the first stage (P2) of the flip-flop circuit, gates of transistors614and616are respectively coupled to clock terminals CKBB and CKB; and the source and drain of transistors614and616are coupled between node612and the stage output. The second stage (P3) of the flip-flop circuit forms a latch that includes a first inverter618coupled in a forward path between the stage input and output, and a second inverter620coupled in a feedback configuration and enabled and disabled by clocks at terminals CKB and CKBB. In the third stage (P4) of the flip-flop circuit, gates of transistors622and624are respectively coupled to clock terminals CKB and CKBB; and the source and drain of transistors622and624are coupled between the stage input and output. The fourth stage (P5) of the flip-flop circuit forms a second latch that includes a first inverter626coupled in a forward path between the stage input and output, and a second inverter628coupled in a feedback configuration and enabled and disabled by clocks at terminals CKBB and CKB. The final stage (P6) of the flip-flip circuit includes an inverter630that inverts the output of the fourth stage (P5) to generate the flip-flip output at terminal Q.

In normal-mode operation, when the clock at terminal CKBB is logic low (0), the clock at terminal CKB is logic high (1), so that transistors614and616in the first flip-flop stage (P2) are turned on, and the transistors622,644in the third stage (P4) are turned off, allowing the signal at the flip-flop input to be conducted through and latched between the inverters618,620of the second stage (P3). When the clock at terminal CKBB transitions to logic high (1), the clock at terminal CKB transitions to logic low (0), so that the transistors622and624in the third flip-flop stage turn on, the transistors618,620in the first stage (P2) turn off, and the signal previously latched in the second stage (P3) is conducted through and latched between the inverters626,628in the fourth stage (P5) and output at terminal Q.

Cross referencingFIGS.6A and6B, portions of the scan flip-flop circuit600are included in a high fin row632of the hybrid cell layout602, and other portions of the scan flip-flop circuit600are included in a less fin row634of the hybrid cell layout602. Circuit components that are included in the high fin row632are identified inFIG.6Awith a reference numeral “2” and circuit components that are included in the less fin row634are identified inFIG.6Awith a reference numeral “1.”

Specifically, the multiplexer (P1) includes a first plurality of transistors in a scan chain portion of the multiplexer circuit that are included in the less fin row634, and a second plurality of transistors in the normal operation portion of the multiplexer circuit that are included in the high fin row632. The first (P2), third (P4), and fifth (P6) stages of the flip-flop circuit are each implemented in the high fin row632. The second (P3) and fourth (P4) stages of the flip-flop circuit each include a first inverter618,626implemented in the high fin row632, and a second inverter620,628implemented in the less fin row632. The multi-stage clock inverter circuit (P8and P9) includes a first inverter stage (P8) included in the high fin row632and a second inverter stage (P9) included in the less fin row634. Finally, the signal inverter (P7) is implemented in the less fin row634.

The scan flip-flop circuit600illustrated inFIGS.6A and6Bis optimized for speed by including both of the first (P2) and third (P4) flip-flop stages within the high fin row632of the of the hybrid cell layout602. The inventors have determined that implementing the scan flip-flop circuit600in a hybrid double height (HA+HB) cell602, as shown, may improve circuit performance (speed) over even that of the same circuit600implemented entirely with high fin rows. This performance optimization is achieved by including circuit components within the critical path of the flip-flop circuit600within the high fin row632, while including components that are less critical to the speed of normal-mode operation within the less fin row602.

FIGS.7A and7Bdepict an example hybrid finFET cell for a scan flip-flop circuit that is optimized to reduce power consumption. The circuit diagram700of the scan flip-flop circuit is shown inFIG.7A, and the cell layout702for the scan flip-flop is shown atFIG.7B. The scan flip-flop circuit700depicted inFIGS.7A and7Bis the same as the scan flip-flop circuit600depicted inFIGS.6A and6B, expect that in the embodiment shown inFIGS.7A and7B, the finFET transistors of the first stage (P2) of the flip-flip portion of the circuit700are implemented in the less fin row704, instead of the high fin row706. By moving the first flip-flop stage (P2) to the less fin row704, the power consumption of the circuit is reduced at the expense of circuit performance (speed.) For example, the inventors found an approximate 15% reduction in internal power consumption over a previous design implemented with only high fin rows.

FIGS.8A and8Bdepict an example hybrid finFET cell for a multiplexer. The circuit diagram800of the example multiplexer circuit is shown inFIG.8A, and the cell layout802for the multiplexer is shown atFIG.8B. With reference first toFIG.8A, the multiplexer circuit800includes two input inverter stages804,806that are respectively coupled to signal input terminals I0and I1, a selection inverter stage808that is coupled to a select terminal S, a switching stage810, and an output inverter stage812. In operation, the switching stage810of the multiplexer800is controlled by the output (SB) of the selection inverter stage808to select one of the two input signals (I0or I1) to pass through to the multiplexer output (Z).

Cross referencingFIGS.8A and8B, portions of the multiplexer circuit800are included in a high fin row814of the hybrid cell layout802, and other portions of the multiplexer circuit800are included in a less fin row816of the hybrid cell layout802. Specifically, the two input inverter stages804,806and the output inverter stage812are each included in the high fin row814, and the selection inverter stage808and switching stage810are each included in the less fin row816. Implementing the multiplexer circuit800in a double height (HA+HB) cell802, as shown, may improve circuit performance (speed) and/or power consumption over that of the same circuit800implemented in other layout configurations. The improved performance results, at least in part, from the resultant driving ratio achieved by placing the input inverter stages804,806in a high fin row814and the switching stage810in a less fin row816. For example, the inventors found an approximate 18% improvement in speed over a previous design that was not optimized in this way.

FIG.9is a flow diagram for an example method900of fabricating an integrated circuit cell to perform a function. While the method900ofFIG.9is applicable to many structures, reference to structures ofFIGS.1A-8Bare included here for each in understanding. At902, a logic design (e.g.,300,400,500,600or700), including a plurality of logic components, is accessed for implementing the function of the integrated circuit cell. At904, a plurality of integrated circuit structures are accessed for implementing one or more of the logic components. The plurality of integrated circuit structures may include a first integrated circuit structure that includes a first circuit component (e.g.,306,406,506) having finFETs formed in a high fin portion of the integrated circuit cell, and a second integrated circuit structure that includes a second circuit component (e.g.,304,404,504) having finFETs formed in a less fin portion of the integrated circuit cell.

At906, a plurality of integrated circuit designs (e.g.,600,700) are generated that use different combinations of the plurality of integrated circuit structures that implement the function. The generated integrated circuit designs (e.g.,600,700) are filtered at908to eliminate designs that do not meet a first integrated circuit criterion (e.g., a speed or power consumption threshold). A remaining integrated circuit design that has an optimum value for a second integrated circuit criterion (e.g., speed or power consumption) is then selected at910. At912, the completed integrated circuit design layout may be used to generate a photomask. The photomask may then be used, at914, to fabricate an integrated circuit.

FIG.10is a functional block diagram of an example system1000for forming and fabricating a layout design in accordance with some embodiments. System1000is usable for implementing one or more operations of the method900disclosed inFIG.9, and further explained in conjunction withFIGS.1-8.

System1000includes a first computer system1010, a second computer system1020, a networked storage device1030, photolithography and fabrication tools1050, and a network1040connecting the first computer system1010, the second computer system1020, the networked storage device1030, and the photolithography and fabrication tools1050.

The first computer system1010includes a hardware processor1012communicatively coupled with a non-transitory computer readable storage medium1014encoded with, i.e., storing, a set of instructions1014a, a layout design1014b, and any intermediate data1014cfor executing the set of instructions1014a. The processor1012is electrically and communicatively coupled with the computer readable storage medium1014. The processor1012is configured to execute the set of instructions1014aencoded in the computer readable storage medium1014in order to cause the computer1010to be usable as a layout designing tool for performing a method900as described in conjunction withFIG.9.

In some embodiments, the set of instructions1014a, the layout design1014b, and/or the intermediate data1014care stored in a non-transitory storage medium other than storage medium1014. In some embodiments, some or all of the set of instructions1014a, the layout design1014b, or the intermediate data1014care stored in a non-transitory storage medium in networked storage device1030or second computer system1020. In such case, some or all of the set of instructions1014a, the layout design1014b, or the intermediate data1014cstored outside computer1010is accessible by the processor1012through the network1040.

In some embodiments, the processor1012is a central processing unit (CPU), a multi-processor, a distributed processing system, an application specific integrated circuit (ASIC), and/or a suitable processing unit.

The computer system1010includes, in at least some embodiments, an input/output interface1016and a display unit1017. The input/output interface1016is coupled to the processor1012and allows the circuit designer to manipulate the first computer system1010. In at least some embodiments, the display unit1017displays the status of executing the set of instructions1014aand, in at least some embodiments, pro-vides a Graphical User Interface (GUI). In at least some embodiments, the display unit1017displays the status of at least some embodiments, the input/output interface1016and the display1017allow an operator to operate the computer system1010in an interactive manner.

In at least some embodiments, the computer system1000also includes a network interface1018coupled to the processor1012. The network interface1018allows the computer system1010to communicate with the network1040, to which one or more other computer systems are connected. The network interface includes wireless network interfaces such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or wired network interface such as ETHERNET, USB, or IEEE-1394.

In some embodiments, an integrated circuit design layout that is completed using the computing system1000in accordance with one or more of the processes described above with reference toFIGS.1-9may be transferred to one or more photolithography and fabrication tools1050to generate a photomask and fabricate an integrated circuit.

In one embodiment, an integrated circuit cell includes a first circuit component and a second circuit component. The first circuit component includes fin field-effect transistors (finFETs) formed in a high fin portion of the integrated circuit cell, the high fin portion of the integrated circuit including a plurality of fin structures arranged in rows. The second circuit component that includes finFETs formed in a less fin portion of the integrated circuit cell, the less fin portion of the integrated circuit including a lesser number of fin structures than the high fin portion of the integrated circuit cell.

In one embodiment, an integrated circuit cell for a flip-flop includes a first stage and a second stage. The first stage is configured to receive a flip-flop input and pass the flip-flop input through to a first stage output in response to a clock signal. The first stage includes field-effect transistors (finFETs) formed in one of a high fin portion of the integrated circuit cell or a less fin portion of the integrated circuit cell based on a performance optimization criterion, wherein the high fin portion of the integrated circuit cell includes a plurality of fin structures arranged in rows, and the less fin portion of the integrated circuit cell includes a lesser number of fin structures than the high fin portion of the integrated circuit cell. The second stage is configured to receive the first stage output and generate a first latched output in response to the clock signal, the second stage including finFETs in a forward path that are formed in the high fin portion of the integrated circuit and finFETs in a feedback path that are formed in the less fin portion of the integrated circuit.