Semiconductor device

A semiconductor device may include: a first receiver configured to receive a chip select signal from a receiving node to which a termination resistor is coupled and configured to generate a first internal chip select signal; a command pulse generation circuit configured to generate a command pulse for entering into a self-refresh operation based on an internal command address and the first internal chip select signal; and an operation control circuit configured to, when the semiconductor device enters the self-refresh operation based on the command pulse, generate a resistor value change signal that adjusts the value of the termination resistor.

CROSS-REFERENCES TO RELATED APPLICATIONS

The present application claims priority under 35 U.S.C. § 119(a) to Korean application number 10-2021-0163829, filed in the Korean Intellectual Property Office on Nov. 24, 2021, the entire disclosure of which is incorporated herein by reference in its entirety.

BACKGROUND

The present disclosure relates to a semiconductor device capable of adjusting the value of a termination resistor during a self-refresh operation.

Among semiconductor devices, DRAM is a volatile memory in which data stored in a memory cell is lost after a predetermined time has elapsed, and needs to perform a refresh operation of re-storing data. The DRAM may perform a self-refresh operation of periodically performing a refresh operation by automatically generating a command for the refresh operation therein.

A semiconductor device may include an ODT (On-Die Termination) circuit for matching external impedance with internal impedance, thereby improving signal integrity.

SUMMARY

In an embodiment, a semiconductor device may include: a first receiver configured to receive a chip select signal from a receiving node to which a termination resistor is coupled and configured to generate a first internal chip select signal; a command pulse generation circuit configured to generate a command pulse for entering into a self-refresh operation based on an internal command address and the first internal chip select signal; and an operation control circuit configured to, when the semiconductor device enters the self-refresh operation based on the command pulse, generate a resistor value change signal that adjusts the value of the termination resistor.

In another embodiment, a semiconductor device may include: an operation control circuit configured to generate a resistor value change signal when a level of a chip select signal transitions so that the semiconductor device enters a self-refresh operation; and an ODT (On-Die Termination) circuit including a termination resistor coupled to a receiving node that receives the chip select signal, and configured to adjust the value of the termination resistor based on the resistor value change signal.

DETAILED DESCRIPTION

In the descriptions of the following embodiments, the term “preset” indicates that the value of a parameter is previously decided, when the parameter is used in a process or algorithm. According to an embodiment, the value of the parameter may be set when the process or algorithm is started or while the process or algorithm is performed.

Terms such as “first” and “second,” which are used to distinguish among various components, are not limited by the components. For example, a first component may be referred to as a second component, and vice versa.

When one component is referred to as being “coupled” or “connected” to another component, it may indicate that the components may be directly coupled or connected to each other or coupled or connected to each other through another component interposed therebetween. On the other hand, when one component is referred to as being “directly coupled” or “directly connected” to another component, it may indicate that the components are directly coupled or connected to each other without another component interposed therebetween.

“Logic high level” and “logic low level” are used to describe the logic levels of signals. A signal with a “logic high level” is distinguished from a signal with a “logic low level.” For example, when a signal with a first voltage corresponds to a “logic high level,” a signal with a second voltage may correspond to a “logic low level.” According to an embodiment, a “logic high level” may be set to a voltage higher than a “logic low level.” According to an embodiment, the logic levels of signals may be set to different logic levels or opposite logic levels. For example, a signal with a logic high level may be set to have a logic low level according to an embodiment, and a signal with a logic low level may be set to have a logic high level according to an embodiment.

Hereafter, the teachings of the present disclosure will be described in more detail through embodiments. The embodiments are only used to exemplify the teachings of the present disclosure, and the scope of the present disclosure is not limited by the embodiments.

Embodiments of the present disclosure are directed to a semiconductor device capable of adjusting the value of a termination resistor during a self-refresh operation.

FIG.1is a block diagram illustrating a configuration of an electronic system100in accordance with an embodiment. As illustrated inFIG.1, the electronic system100may include a controller110and a semiconductor device120. The controller110may transmit a chip select signal CS_n to the semiconductor device120through a first transmission line130_1. The controller110may transmit a command address CA to the semiconductor device120through a second transmission line130_2. The controller110may transmit a clock CK to the semiconductor device120through a third transmission line130_3. The semiconductor device120may be implemented as a memory device. The semiconductor device120may receive the chip select signal CS_n, the command address CA, and the clock CK from the controller110, and may perform a self-refresh operation or normal operation. The normal operation may include various internal operations, such as a write operation, read operation, active operation, and precharge operation.

The controller110may include a chip select signal transmitter (CS_n TX)111configured to drive and output the chip select signal CS_n. The controller110may set the level of the chip select signal CS_n through the chip select signal transmitter111. The controller110may change the level of the chip select signal CS_n from a preset level to a first target level such that the semiconductor device120enters a self-refresh operation. Then, the controller110may change the level of the chip select signal CS_n to the preset level again after a preset period. In the present embodiment, the preset period may be set to one period of the clock CK. In an embodiment, however, the preset period may be set to various periods. When a delay time elapses after the semiconductor device120has entered the self-refresh operation, the controller110may change the level of the chip select signal CS_n from the preset level to a second target level in order to control power that is consumed by the semiconductor device120. The delay time indicates the time required for interrupting an input of the command address CA when the semiconductor device120enters the self-refresh operation. The difference between the preset level and the second target level may be set to a larger value than the difference between the preset level and the first target level.

The controller110may change the level of the chip select signal CS_n from the second target level to the preset level, such that the semiconductor device120ends the self-refresh operation.

When an end delay time elapses after the semiconductor device120has ended the self-refresh operation, the controller110may change the level of the chip select signal CS_n from the preset level to the first target level such that the semiconductor device120recognizes the end of the self-refresh operation. Then, the controller110may change the level of the chip select signal CS_n to the preset level again after the preset period. The end delay time may indicate the time that is required for the semiconductor device120to stably recognize that the self-refresh operation has ended.

The semiconductor device120may include an ODT (On-Die Termination) circuit203, a chip select signal receiver (CS_n RX)205, and an operation control circuit217. The ODT circuit203may include a termination resistor (not illustrated) and a termination driver (not illustrated) configured to adjust the value of the termination resistor. The chip select signal receiver205may receive the chip select signal CS_n from a node to which the termination resistor that is included in the ODT circuit203is coupled.

When the level of the chip select signal CS_n transitions from the preset level to the first target level such that the semiconductor device enters the self-refresh operation, the operation control circuit217may generate a resistor value change signal (RTT_C ofFIG.2) for adjusting the value of the termination resistor that is included in the ODT circuit203. The ODT circuit203may adjust the value of the termination resistor by controlling the drivability of the termination driver based on the resistor value change signal RTT_C. Therefore, the semiconductor device120may stably control the level of the chip select signal CS_n that transitions from the preset level to the second target level after the delay time elapses after the semiconductor device120has entered the self-refresh operation. Thus, the semiconductor device120may prevent a malfunction that is caused by a level variation of the chip select signal CS_n during the self-refresh operation.

When the level of the chip select signal CS_n transitions from the preset level to the second target level after the delay time elapses after the semiconductor device120has entered the self-refresh operation, the operation control circuit217may switch a first receiver (207ofFIG.2) of the chip select signal receiver205to a second receiver (209ofFIG.2) of the chip select signal receiver205and may disable the termination resistor that is included in the ODT circuit203. Thus, the semiconductor device120may reduce power that is consumed during the period in which the self-refresh operation is performed.

When the level of the chip select signal CS_n transitions from the second target level to the preset level after the self-refresh operation ends, the operation control circuit217may switch the second receiver (209ofFIG.2) of the chip select signal receiver205to the first receiver (207ofFIG.2) of the chip select signal receiver205, and enable the termination resistor that is included in the ODT circuit203.

FIG.2is a block diagram illustrating a configuration of the semiconductor device120, illustrated inFIG.1. As illustrated inFIG.2, the semiconductor device120may include a mode register201, the ODT circuit203, the chip select signal receiver205, a command address receiver (CA RX)211, a clock receiver (CK RX)213, a command pulse generation circuit (COMMAND PULSE GEN)215, the operation control circuit217, and an internal circuit219.

The mode register201may store and output a setting code OP. The setting code OP may have a logic level combination for setting the value of a termination resistor (RTT ofFIG.3) that is included in the ODT circuit203.

The ODT circuit203may include the termination resistor (RTT ofFIG.3) that is coupled to a receiving node nd_RX that receives the chip select signal CS_n. The ODT circuit203may enable the termination resistor RTT during a period in which an enable signal EN is activated. The ODT circuit203may include a termination driver (223ofFIG.3) configured to adjust the value of the termination resistor RTT. The ODT circuit203may adjust the value of the termination resistor RTT by controlling the drivability of the termination driver223based on the setting code OP and the resistor value change signal RTT_C. When the resistor value change signal RTT_C is deactivated, the ODT circuit203may set the value of the termination resistor RTT according to the logic level combination of the setting code OP. When the resistor value change signal RTT_C is activated, the ODT circuit203may set the value of the termination resistor RTT to a preset value. The preset value may be set to various values in different embodiments. For example, when the resistor value change signal RTT_C is activated, the ODT circuit203may lower the drivability of the termination driver223to a lower value than when the resistor value change signal RTT_C is deactivated, thereby setting the value of the termination resistor RTT to a high value. That is, the resistor value change signal RTT_C may be activated to adjust the drivability of the termination driver223in order to stably control the level variation of the chip select signal CS_n. The configuration and operation method of the ODT circuit203will be described below in detail with reference toFIG.3.

The chip select signal receiver205may include the first receiver (FIRST RX)207and the second receiver (SECOND RX)209that are configured to receive the chip select signal CS_n from the receiving node nd_RX to which the termination resistor (RTT ofFIG.3) that is included in the ODT circuit203is coupled. The level of the chip select signal CS_n may be set between the level of a supply voltage VDD and the level of a ground voltage VSS. The supply voltage VDD and the ground voltage VSS may be applied from a power pad (not illustrated). In the present embodiment, the preset level of the chip select signal CS_n may be set to the level of the supply voltage VDD, the first target level of the chip select signal CS_n may be set between the level of the supply voltage VDD and a half of the level of the supply voltage VDD, and the second target level of the chip select signal CS_n may be set to the level of the ground voltage VSS. This is only an embodiment, and the preset level, the first target level, and the second target level of the chip select signal CS_n may be set to various levels in different embodiments.

The first receiver207may receive the chip select signal CS_n from the receiving node nd_RX and generate a first internal chip select signal ICS1based on an enable signal EN and a reference voltage VREF_CS. The first receiver207may be enabled during a period in which the enable signal EN is activated. The first receiver207may set the logic level of the first internal chip select signal ICS1by comparing the level of the chip select signal CS_n to the level of the reference voltage VREF_CS during the period in which the enable signal EN is activated. The level of the reference voltage VREF_CS may be set between the preset level and the first target level. For example, when the level of the chip select signal CS_n transitions from the preset level to the first target level such that the semiconductor device enters the self-refresh operation, the first receiver207may set the logic level of the first internal chip select signal ICS1to a preset logic level. For another example, when the level of the chip select signal CS_n transitions from the preset level to the second target level after the delay time elapses after the semiconductor device has entered the self-refresh operation, the first receiver207may set the logic level of the first internal chip select signal ICS1to the preset logic level. For still another example, when the level of the chip select signal CS_n transitions from the preset level to the first target level after the end delay time elapses after the self-refresh operation ends, the first receiver207may set the logic level of the first internal chip select signal ICS1to the preset logic level. In the present embodiment, the preset logic level may be set to a logic low level. However, the preset logic level may be set to a logic high level in different embodiments. The first receiver207may be implemented as a differential amplifier that amplifies the difference between the level of the chip select signal CS_n and the level of the reference voltage VREF_CS and drives an output node from which the first internal chip select signal ICS1is output. The configuration and operation method of the first receiver207will be described below in detail with reference toFIG.6.

The second receiver209may receive the chip select signal CS_n from the receiving node nd_RX and generate a second internal chip select signal ICS2based on a self-refresh signal SREF. The second receiver209may be enabled during a period in which the self-refresh signal SREF is activated. The second receiver209may set the logic level of the second internal chip select signal ICS2according to the level of the chip select signal CS_n during the period in which the self-refresh signal SREF is activated. For example, when the level of the chip select signal CS_n transitions from the preset level to the second target level after the delay time elapses after the semiconductor device has entered the self-refresh operation, the second receiver209may change the logic level of the second internal chip select signal ICS2from the first logic level to the second logic level. For another example, when the level of the chip select signal CS_n transitions from the second target level to the preset level such that the semiconductor device ends the self-refresh operation, the second receiver209may change the logic level of the second internal chip select signal ICS2from the second logic level to the first logic level. In the present embodiment, the first logic level and the second logic level may be set to a logic high level and a logic low level, respectively. However, the first logic level and the second logic level may be set to a logic low level and a logic high level, respectively, in different embodiments. The second receiver209may be implemented as a CMOS (Complementary Metal-Oxide Semiconductor) buffer that drives an output node from the second internal chip select signal ICS2is output according to the level of the chip select signal CS_n. The second receiver209that is implemented as a CMOS buffer may have a lower power consumption than the first receiver207that is implemented as a differential amplifier. The configuration and operation method of the second receiver209will be described below in detail with reference toFIG.7.

The command address receiver211may receive the command address CA and generate an internal command address ICA. The command address receiver211may buffer the command address CA and output the buffered command address as the internal command address ICA.

The clock receiver213may receive the clock CK and generate an internal clock ICK. The clock receiver213may buffer the clock CK and output the buffered clock as the internal clock ICK.

The command pulse generation circuit215may generate a command pulse SREP from the internal command address ICA based on the first internal chip select signal ICS1in synchronization with the internal clock ICK. When the first internal chip select signal ICS1has the preset logic level, the command pulse generation circuit215may generate the command pulse SREP for entering into the self-refresh operation by decoding the internal command address ICA with a logic level combination for entering into the self-refresh operation. The configuration and operation method of the command pulse generation circuit215will be described below in detail with reference toFIG.8.

The operation control circuit217may generate the self-refresh signal SREF, an internal self-refresh signal ISREF, the resistor value change signal RTT_C, and the enable signal EN based on the command pulse SREP, the first internal chip select signal ICS1, and the second internal chip select signal ICS2. The self-refresh signal SREF may be activated until the semiconductor device ends the self-refresh operation after entering the self-refresh operation. The internal self-refresh signal ISREF may be activated until the end delay time elapses after the semiconductor device ends the self-refresh operation. The resistor value change signal RTT_C may be activated to adjust the value of the termination resistor (RTT ofFIG.3), included in the ODT circuit203, to a preset value. The enable signal EN may be activated to enable the first receiver207and the termination resistor RTT that is included in the ODT circuit203.

The operation control circuit217may control the active states of the self-refresh signal SREF and the internal self-refresh signal ISREF based on the command pulse SREP, the first internal chip select signal ICS1, and the second internal chip select signal ICS2. When the semiconductor device enters the self-refresh operation based on the command pulse SREP, the operation control circuit217may activate the self-refresh signal SREF and the internal self-refresh signal ISREF. The operation control circuit217may enable the second receiver209based on the activated self-refresh signal SREF. When the logic level of the second internal chip select signal ICS2transitions from the second logic level to the first logic level after the self-refresh operation ends, the operation control circuit217may deactivate the self-refresh signal SREF. The operation control circuit217may disable the second receiver209based on the deactivated self-refresh signal SREF. When the first internal chip select signal ICS1has the preset logic level in a period in which the self-refresh signal SREF is deactivated after the self-refresh operation ends, the operation control circuit217may deactivate the internal self-refresh signal ISREF. That is, when the first internal chip select signal ICS1has the preset logic level after the end delay time elapses after the self-refresh operation ends, the operation control circuit217may deactivate the internal self-refresh signal ISREF.

The operation control circuit217may control the active state of the resistor value change signal RTT_C based on the command pulse SREP and the second internal chip select signal ICS2. When the semiconductor device enters the self-refresh operation based on the command pulse SREP, the operation control circuit217may activate the resistor value change signal RTT_C. That is, when the semiconductor device enters the self-refresh operation, the operation control circuit217may adjust the value of the termination resistor (RTT ofFIG.3) that is included in the ODT circuit203to a preset value based on the activated resistor value change signal RTT_C. When the logic level of the second internal chip select signal ICS2transitions from the first logic level to the second logic level, the operation control circuit217may deactivate the resistor value change signal RTT_C. That is, when the delay time elapses after the semiconductor device has entered the self-refresh operation, the operation control circuit217may set the value of the termination resistor RTT according to the logic level combination of the setting code OP based on the deactivated resistor value change signal RTT_C. Thus, in order to stably control a level variation of the chip select signal CS_n after the semiconductor device enters the self-refresh operation, the operation control circuit217may adjust the value of the termination resistor RTT coupled to the chip select signal receiver205that receives the chip select signal CS_n when the semiconductor device enters the self-refresh operation, which makes it possible to prevent a malfunction that is caused by the level variation of the chip select signal CS_n during the self-refresh operation.

The operation control circuit217may control the active state of the enable signal EN based on the command pulse SREP, the first internal chip select signal ICS1, and the second internal chip select signal ICS2. When the first internal chip select signal ICS1has the preset logic level in a period in which the self-refresh signal SREF is activated, the operation control circuit217may deactivate the enable signal EN. That is, when the delay time elapses after the semiconductor device has entered the self-refresh operation, the operation control circuit217may disable the first receiver207and the termination resistor (RTT ofFIG.3) that is included in the ODT circuit203based on the deactivated enable signal EN. Thus, when the delay time elapses after the semiconductor device has entered the self-refresh operation, the operation control circuit217may switch the first receiver207of the chip select signal receiver205to the second receiver209of the chip select signal receiver205and may disable the termination resistor RTT that is coupled to the chip select signal receiver205, thereby reducing the power that is consumed during the period in which the self-refresh operation is performed. When the logic level of the second internal chip select signal ICS2transitions from the second logic level to the first logic level after the self-refresh operation ends, the operation control circuit217may activate the enable signal EN. That is, when the self-refresh operation has ended, the operation control circuit217may enable the termination resistor RTT and the first receiver207based on the activated enable signal EN.

The internal circuit219may include a plurality of memory cells (not illustrated). The internal circuit219may perform a refresh operation on the plurality of memory cells during a period in which the internal self-refresh signal ISREF is activated.

FIG.3is a diagram illustrating an example of the ODT circuit203, illustrated inFIG.2. As illustrated inFIG.3, the ODT circuit203may include an internal setting code generation circuit (IOP GEN)221, the termination driver223, and the termination resistor RTT.

The internal setting code generation circuit221may generate an internal setting code IOP based on the setting code OP and the resistor value change signal RTT_C. When the resistor value change signal RTT_C is deactivated, the internal setting code generation circuit221may output the setting code OP as the internal setting code IOP. That is, when the resistor value change signal RTT_C is deactivated, the internal setting code generation circuit221may generate the internal setting code IOP with the same logic level combination as that of the setting code OP. For example, when the resistor value change signal RTT_C is deactivated, the internal setting code generation circuit221may set the logic level combination of the internal setting code IOP to ‘H, H, H’, which are equal to the logic level combination of the setting code OP. When the resistor value change signal RTT_C is activated, the internal setting code generation circuit221may set the combination of the internal setting code IOP to a preset combination. The preset logic level combination may be set to various combinations in different embodiments. For example, when the resistor value change signal RTT_C is activated, the internal setting code generation circuit221may set the logic level combination of the internal setting code IOP to ‘H, L, L’, regardless of the logic level combination of the setting code OP. The configuration and operation method of the internal setting code generation circuit221will be described below with reference toFIGS.4and5.

The termination driver223may include switching elements223_1,223_2, and223_3. The number of switching elements may be set to various values in different embodiments. The switching element223_1may be coupled between a terminal of the supply voltage VDD and an internal node nd11. The switching element223_2may be coupled between the terminal of the supply voltage VDD and an internal node nd12. The switching element223_3may be coupled between the terminal of the supply voltage VDD and an internal node nd13. In different embodiments, one end of each switching element may be coupled to a terminal of the ground voltage VSS. The logic level combination of the internal setting code IOP may decide whether to turn on the switching elements223_1to223_3that are included in the termination driver223. For example, when the logic level combination of the internal setting code IOP is ‘H, H, H’, the switching elements223_1to223_3may be all turned on. For another example, when the logic level combination of the internal setting code IOP is ‘H, L, L’, the switching element223_1may be turned on, and the switching elements223_2and223_3may be turned off. That is, the drivability of the termination driver223may be adjusted according to the logic level combination of the internal setting code IOP.

The termination resistor RTT may include resistance elements R1, R2, and R3. The number of resistance elements may vary in different embodiments. The resistance values of the resistance elements R1, R2, and R3may be set to various values in different embodiments. The resistance element R1may be coupled between the internal node nd11and the receiving node nd_RX that receives the chip select signal CS_n. The resistance element R2may be coupled between the receiving node nd_RX and the internal node nd12. The resistance element R3may be coupled between the receiving node nd_RX and the internal node nd13. The value of the termination resistor RTT may be adjusted according to whether the switching elements223_1to223_3are turned on. The termination resistor RTT may be enabled during a period in which the enable signal EN is activated. More specifically, when the enable signal EN is activated, the resistance elements R1to R3may be enabled and may have their own resistance values. When the enable signal EN is deactivated, the resistance elements R1to R3may be disabled to stay in a high implement (High-Z) state.

FIG.4is a circuit diagram illustrating an example of the internal setting code generation circuit221, illustrated inFIG.3. As illustrated inFIG.4, an internal setting code generation circuit221A may include NOR gates221A_1,221A_2, and221A_3and inverters221A_4,221A_5, and221A_6. When the resistor value change signal RTT_C is deactivated to a logic low level, the NOR gate221A_1and the inverter221A_4may buffer a first bit OP<1> of the setting code and output the buffed bit as a first bit IOP<1> of the internal setting code. When the resistor value change signal RTT_C is activated to a logic high level, the NOR gate221A_1and the inverter221A_4may set the first bit IOP<1> of the internal setting code to a logic high level. The operations of the NOR gate221A_2and the inverter221A_5and the operations of the NOR gate221A_3and the inverter221A_6may be implemented in the same manner as those of the NOR gate221A_1and the inverter221A_4.

FIG.5is a circuit diagram illustrating another example of the internal setting code generation circuit221, illustrated inFIG.3. As illustrated inFIG.5, an internal setting code generation circuit221B may include inverters221B_1,221B_5,221B_6, and221B_7and NAND gates221B_2,221B_3, and221B_4. The inverter221B_1may invert and buffer the resistor value change signal RTT_C and may output the inverted and buffered signal as an inverted resistor value change signal RTT_CB. When the inverted resistor value change signal RTT_CB is at a logic high level, the NAND gate221B_2and the inverter221B_5may buffer the first bit OP<1> of the setting code and output the buffed bit as the first bit IOP<1> of the internal setting code. When the inverted resistor value change signal RTT_CB is at a logic low level, the NAND gate221B_2and the inverter221B_5may set the first bit IOP<1> of the internal setting code to a logic low level. The operations of the NAND gate221B_3and the inverter221B_6and the operations of the NAND gate221B_4and the inverter221B_7are implemented in the same manner as those of the NAND gate221B_2and the inverter221B_5.

FIG.6is a circuit diagram illustrating an example of the first receiver207, illustrated inFIG.2. As illustrated inFIG.6, the first receiver207may include a charge supply circuit231and a charge release circuit233.

The charge supply circuit231may include PMOS transistors231_1and231_2. The PMOS transistor231_1may be coupled between the terminal of the supply voltage VDD and an internal node nd21. The PMOS transistor231_1may supply a charge to the internal node nd21according to the level of the internal node nd21. The PMOS transistor231_2may be coupled between the terminal of the supply voltage VDD and an output node nd22. The PMOS transistor231_2may supply a charge to the output node nd22from which the first internal chip select signal ICS1is output, according to the level of the internal node nd21.

The charge release circuit233may include NMOS transistors233_1,233_2, and233_3. The NMOS transistor233_1may be coupled between the internal node nd21and an internal node nd23, and turned on according to the chip select signal CS_n. The NMOS transistor233_2may be coupled between the output node nd22and the internal node nd23and may be turned on according to the reference voltage VREF_CS. The NMOS transistor233_3may be coupled between the terminal of the ground voltage VSS and the internal node nd23. The NMOS transistor233_3may release the charge of the internal node nd23when the enable signal EN is activated to a logic high level. When the enable signal EN has a logic high level and the chip select signal CS_n has a higher level than the reference voltage VREF_CS, the charge release circuit233may increase the amount of charge that is released from the internal node nd21to be more than the amount of charge that is released from the output node nd22. Thus, the output node nd22from which the first internal chip select signal ICS1is output may be driven to a logic high level. When the enable signal EN has a logic high level and the chip select signal CS_n has a lower level than the reference voltage VREF_CS, the charge release circuit233may increase the amount of charge that is released from the output node nd22to be more than the amount of charge that is released from the internal node nd21. Thus, the output node nd22from which the first internal chip select signal ICS1is output may be driven to a logic low level.

FIG.7is a circuit diagram illustrating an example of the second receiver209, illustrated inFIG.2. As illustrated inFIG.7, the second receiver209may include a first driving circuit241and a second driving circuit243.

The first driving circuit241may include PMOS transistors241_1and241_2and NMOS transistors241_3and241_4. The PMOS transistor241_1may be coupled between the terminal of the supply voltage VDD and the PMOS transistor241_2and may be turned on according to the logic level of an inverted self-refresh signal SREFB. The inverted self-refresh signal SREFB may be generated by inverting and buffering the self-refresh signal SREF. The PMOS transistor241_2may be coupled between the PMOS transistor241_1and an internal node nd31and may be turned on according to the level of the chip select signal CS_n. When both are turned on according to the inverted self-refresh signal SREFB and the chip select signal CS_n, the PMOS transistor241_1and the PMOS transistor241_2may drive the internal node nd31to a logic high level. The NMOS transistor241_3may be coupled between the terminal of the ground voltage VSS and the NMOS transistor241_4and may be turned on according to the logic level of the self-refresh signal SREF. The NMOS transistor241_4may be coupled between the internal node nd31and the NMOS transistor241_3and may be turned on according to the level of the chip select signal CS_n. When both are turned on according to the self-refresh signal SREF and the chip select signal CS_n, the NMOS transistor241_3and the NMOS transistor241_4may drive the internal node nd31to a logic low level.

The second driving circuit243may include a PMOS transistor243_1and an NMOS transistor243_2. The PMOS transistor243_1may be coupled between the terminal of the supply voltage VDD and an output node nd32from which the second internal chip select signal ICS2is output. When the internal node nd31is driven to a logic low level, the PMOS transistor243_1may drive the output node nd32to a logic high level. The NMOS transistor243_2may be coupled between the terminal of the ground voltage VSS and the output node nd32. When the internal node nd31is driven to a logic high level, the NMOS transistor243_2may drive the output node nd32to a logic low level.

FIG.8is a diagram illustrating an example of the command pulse generation circuit215, illustrated inFIG.2. As illustrated inFIG.8, the command pulse generation circuit215may include a first latch circuit (LAT)251, a second latch circuit (LAT)253, and a command decoder255.

The first latch circuit251may latch the internal command address ICA in synchronization with the internal clock ICK and output the latched internal command address ICA as a latched command address ICA_LAT.

The second latch circuit253may latch the first internal chip select signal ICS1in synchronization with the internal clock ICK and output the latched first internal chip select signal ICS1as a latched chip select signal ICS_LAT.

The command decoder255may generate the command pulse SREP by decoding the latched command address ICA_LAT based on the latched chip select signal ICS_LAT. More specifically, when the latched chip select signal ICS_LAT has a preset logic level, the command decoder255may generate the command pulse SREP by decoding the latched command address ICA_LAT with a logic level combination for entering into the self-refresh operation.

FIG.9is a block diagram illustrating an example of the operation control circuit217, illustrated inFIG.2. As illustrated inFIG.9, the operation control circuit217may include a self-refresh control circuit260and an internal operation control circuit270.

The self-refresh control circuit260may include a self-refresh signal generation circuit (SREF GEN)261and an internal self-refresh signal generation circuit (ISREF GEN)263. The self-refresh control circuit260may generate the self-refresh signal SREF and the internal self-refresh signal ISREF based on the command pulse SREP, the first internal chip select signal ICS1, and the second internal chip select signal ICS2.

The self-refresh signal generation circuit261may generate the self-refresh signal SREF based on the command pulse SREP and the second internal chip select signal ICS2. The self-refresh signal generation circuit261may activate the self-refresh signal SREF in synchronization with a point of time at which the command pulse SREP that is activated for entering into the self-refresh operation is deactivated. When the logic level of the second internal chip select signal ICS2transitions from the second logic level to the first logic level after the self-refresh operation ends, the self-refresh signal generation circuit261may deactivate the self-refresh signal SREF. The configuration and operation method of the self-refresh signal generation circuit261will be described below in detail with reference toFIG.10.

The internal self-refresh signal generation circuit263may generate the internal self-refresh signal ISREF based on the command pulse SREP, the self-refresh signal SREF, and the first internal chip select signal ICS1. The internal self-refresh signal generation circuit263may activate the internal self-refresh signal ISREF in synchronization with a point of time at which the command pulse SREP that is activated for entering into the self-refresh operation is deactivated. When the first internal chip select signal ICS1has the preset logic level in a period in which the self-refresh signal SREF is deactivated, the internal self-refresh signal generation circuit263may deactivate the internal self-refresh signal ISREF. That is, when the first internal chip select signal ICS1has the preset logic level after the end delay time elapses after the self-refresh operation ends, the internal self-refresh signal generation circuit263may deactivate the internal self-refresh signal ISREF. The configuration and operation method of the internal self-refresh signal generation circuit263will be described below in detail with reference toFIG.11.

The internal operation control circuit270may include an enable signal generation circuit (EN GEN)271, a flag generation circuit (FLAG GEN)273, and a resistor value change signal generation circuit (RTT_C GEN)275. The internal operation control circuit270may generate the enable signal EN and the resistor value change signal RTT_C based on the self-refresh signal SREF, the first internal chip select signal ICS1, and the second internal chip select signal ICS2.

The enable signal generation circuit271may generate the enable signal EN based on the self-refresh signal SREF, a flag FLAG, the first internal chip select signal ICS1, and the second internal chip select signal ICS2. The flag FLAG may be activated to indicate that the enable signal EN is deactivated and may be deactivated to indicate that the enable signal EN is activated. The enable signal generation circuit271may activate the enable signal EN when the self-refresh signal SREF is deactivated. When the first internal chip select signal ICS1has the preset logic level in a period in which the self-refresh signal SREF is activated, the enable signal generation circuit271may deactivate the enable signal EN. That is, when the first internal chip select signal ICS1has the preset logic level after the delay time elapses after the semiconductor device has entered the self-refresh operation, the enable signal generation circuit271may deactivate the enable signal EN. When the logic level of the second internal chip select signal ICS2transitions from the second logic level to the first logic level while the flag FLAG is activated, the enable signal generation circuit271may activate the enable signal EN. That is, when the logic level of the second internal chip select signal ICS2transitions from the second logic level to the first logic level after the self-refresh operation ends based on the flag FLAG that indicates that the enable signal EN is deactivated, the enable signal generation circuit271may activate the enable signal EN. The configuration and operation method of the enable signal generation circuit271will be described below in detail with reference toFIG.12.

The flag generation circuit273may generate the flag FLAG based on the enable signal EN and the second internal chip select signal ICS2. When the second internal chip select signal ICS2has the second logic level while the enable signal EN is deactivated, the flag generation circuit273may activate the flag FLAG to indicate that the enable signal EN is deactivated. When the enable signal EN is activated, the flag generation circuit273may deactivate the flag FLAG to indicate that the enable signal EN is activated. The configuration and operation method of the flag generation circuit273will be described below in detail with reference toFIG.13.

The resistor value change signal generation circuit275may generate the resistor value change signal RTT_C based on the self-refresh signal SREF and the flag FLAG. When the self-refresh signal SREF is activated while the flag FLAG is deactivated, the resistor value change signal generation circuit275may activate the resistor value change signal RTT_C. That is, when the self-refresh signal SREF is activated based on the flag FLAG that indicates that the enable signal EN is activated, the resistor value change signal generation circuit275may activate the resistor value change signal RTT_C. When the flag FLAG is activated, the resistor value change signal generation circuit275may deactivate the resistor value change signal RTT_C. That is, the resistor value change signal generation circuit275may deactivate the resistor value change signal RTT_C based on the flag FLAG that indicates that the enable signal EN is deactivated. The configuration and operation method of the resistor value change signal generation circuit275will be described below in detail with reference toFIG.14.

FIG.10is a circuit diagram illustrating an example of the self-refresh signal generation circuit261, illustrated inFIG.9. As illustrated inFIG.10, the self-refresh signal generation circuit261may include a first pulse generation circuit281and a first activation control circuit283.

When the logic level of the second internal chip select signal ICS2transitions from a logic low level to a logic high level after the self-refresh operation ends, the first pulse generation circuit281may generate a first self-refresh end pulse SPXP1with a logic low level. The first pulse generation circuit281may be implemented as inverters281_1,281_2, and281_3and a NAND gate281_4.

The first activation control circuit283may control the active state of the self-refresh signal SREF based on the first self-refresh end pulse SRXP1and the command pulse SREP for entering into the self-refresh operation. The first activation control circuit283may activate the self-refresh signal SREF to a logic high level in synchronization with a point of time at which the command pulse SREP that is activated at a logic high level is deactivated to a logic low level. When the first self-refresh end pulse SRXP1has a logic low level, the first activation control circuit283may deactivate the self-refresh signal SREF to a logic low level. The first activation control circuit283may include inverters283_1and283_5and NAND gates283_2,283_3, and283_4. The inverter283_1may invert and buffer the command pulse SREP and output the inverted and buffered pulse to an internal node nd41. When the internal node nd41is driven to a logic low level, the NAND gates283_2and283_3may drive an internal node nd42to a logic high level. When the first self-refresh end pulse SRXP1has a logic low level, the NAND gates283_2and283_3may drive the internal node nd42to a logic low level. The NAND gates283_2and283_3may initialize the internal node nd42to a logic low level based on a reset signal RSTB with a logic low level during an initialization operation. When the internal node nd41is driven to a logic low level, the NAND gate283_4and the inverter283_5may set the self-refresh signal SREF to a logic low level. When the internal node nd41is driven to a logic high level, the NAND gate283_4and the inverter283_5may buffer the signal of the internal node nd42and output the buffered signal as the self-refresh signal SREF.

FIG.11is a circuit diagram illustrating an example of the internal self-refresh signal generation circuit263, illustrated inFIG.9. As illustrated inFIG.11, the internal self-refresh signal generation circuit263may include a second pulse generation circuit291and a second activation control circuit293.

When the first internal chip select signal ICS1has a logic low level in a period in which the self-refresh signal SREF is deactivated at a logic low level, the second pulse generation circuit291may generate a second self-refresh end pulse SRXP2with a logic low level. The second pulse generation circuit291may be implemented as inverters291_1and291_2and a NAND gate291_3.

The second activation control circuit293may control the active state of the internal self-refresh signal ISREF based on the second self-refresh end pulse SRXP2and the command pulse SREP for entering into the self-refresh operation. The second activation control circuit293may activate the internal self-refresh signal ISREF to a logic high level in synchronization with a point of time at which the command pulse SREP that is activated at a logic high level is deactivated to a logic low level. When the second self-refresh end pulse SRXP2has a logic low level, the second activation control circuit293may deactivate the internal self-refresh signal ISREF to a logic low level. The second activation control circuit293may include inverters293_1and293_5and NAND gates293_2,293_3, and293_4. The operation method of the second activation control circuit293may be implemented in the same manner as the operation method of the first activation control circuit283illustrated inFIG.10.

FIG.12is a circuit diagram illustrating an example of the enable signal generation circuit271, illustrated inFIG.9. As illustrated inFIG.12, the enable signal generation circuit271may include a third pulse generation circuit301and a third activation control circuit303.

When the logic level of the second internal chip select signal ICS2transitions from a logic low level to a logic high level after the self-refresh operation ends based on the flag FLAG with a logic high level to indicate that the enable signal EN is deactivated, the third pulse generation circuit301may generate a third self-refresh end pulse SRXP3with a logic low level. The third pulse generation circuit301may be implemented as inverters301_1,301_2,301_3, and301_5and NAND gates301_4and301_6.

The third activation control circuit303may control the active state of the enable signal EN based on the self-refresh signal SREF, the first internal chip select signal ICS1, and the third self-refresh end pulse SRXP3. The third activation control circuit303may activate the enable signal EN to a logic high level during a period in which the self-refresh signal SREF is deactivated to a logic low level. When the first internal chip select signal ICS1has a logic low level in a period in which the self-refresh signal SREF is activated at a logic high level, the third activation control circuit303may deactivate the enable signal EN to a logic low level. When the third self-refresh end pulse SRXP3has a logic low level, the third activation control circuit303may activate the enable signal EN to a logic high level. The third activation control circuit303may include NAND gates303_1,303_3, and303_4and inverters303_2,303_5, and303_6. When the self-refresh signal SREF or the third self-refresh end pulse SRXP3has a logic low level, the NAND gate303_1and the inverter303_2may drive an internal node nd61to a logic low level. When the internal node nd61is driven to a logic low level, the NAND gates303_3and303_4may drive an internal node nd62to a logic high level. When both of the self-refresh signal SREF and the third self-refresh end pulse SRXP3have a logic high level, the NAND gate303_1and the inverter303_2may drive the internal node nd61to a logic high level. When the internal node nd61is driven to a logic high level and the first internal chip select signal ICS1has a logic low level, the NAND gates303_3and303_4may drive the internal node nd62to a logic low level. The NAND gates303_3and303_4may initialize the internal node nd62to a logic high level based on the reset signal RSTB with a logic low level during the initialization operation. The inverters303_5and303_6may buffer the signal of the internal node nd62and output the buffered signal as the enable signal EN.

FIG.13is a circuit diagram illustrating an example of the flag generation circuit273, illustrated inFIG.9. As illustrated inFIG.13, the flag generation circuit273may include a fourth pulse generation circuit311and a fourth activation control circuit313.

The fourth pulse generation circuit311may generate an internal pulse IPUL based on the enable signal EN and the second internal chip select signal ICS2. When the enable signal EN is activated to a logic high level, the fourth pulse generation circuit311may drive the internal pulse IPUL to a logic low level. When the enable signal EN is deactivated to a logic low level and the second internal chip select signal ICS2has a logic low level, the fourth pulse generation circuit311may drive the internal pulse IPUL to a logic high level. The fourth pulse generation circuit311may be implemented as a NOR gate311_1.

The fourth activation control circuit313may control the active state of the flag FLAG based on the enable signal EN and the internal pulse IPUL. When the enable signal EN is activated to a logic high level, the fourth activation control circuit313may deactivate the flag FLAG to a logic low level. When the internal pulse IPUL is at a logic high level, the fourth activation control circuit313may activate the flag FLAG to a logic high level. The fourth activation control circuit313may include inverters313_1,313_4, and313_5and NAND gates313_2and313_3. When the enable signal EN has a logic high level, the inverter313_1may drive an internal node nd71to a logic low level. When the internal node nd71is driven to a logic low level, the NAND gates313_2and313_3may drive an internal node nd72to a logic high level. When the internal pulse IPUL has a logic high level, the inverter313_4may drive an internal node nd73to a logic low level. When the internal node nd73is driven to a logic low level, the NAND gates313_2and313_3may drive the internal node nd72to a logic low level. The inverter313_5may invert and buffer the signal of the internal node nd72and may output the inverted and buffered signal as the flag FLAG.

FIG.14is a circuit diagram illustrating an example of the resistor value change signal generation circuit275, illustrated inFIG.9. As illustrated inFIG.14, the resistor value change signal generation circuit275may include inverters275_1and275_3and a NAND gate275_2. The inverter275_1may generate an inverted flag FLAGB by inverting and buffering the flag FLAG. The inverted flag FLAGB may have a logic high level to indicate that the enable signal (EN ofFIG.9) is activated. The inverted flag FLAGB may have a logic low level to indicate that the enable signal EN is deactivated. When the self-refresh signal SREF is activated to a logic high level and the inverted flag FLAGB has a logic high level to indicate that the enable signal (EN ofFIG.9) is activated, the NAND gate275_2and the inverter275_3may activate the resistor value change signal RTT_C to a logic high level. When the inverted flag FLAGB has a logic low level to indicate that the enable signal EN is deactivated, the NAND gate275_2and the inverter275_3may deactivate the resistor value change signal RTT_C to a logic low level.

FIG.15is a timing diagram for describing an operation that is performed when the semiconductor device120, illustrated inFIG.2enters the self-refresh operation. As illustrated inFIG.15, the semiconductor device120may receive the clock CK, the chip select signal CS_n, and the command address CA from the controller (110ofFIG.1). The preset level of the chip select signal CS_n may be set to the level of the supply voltage VDD, the first target level of the chip select signal CS_n may be set between the level of the supply voltage VDD and half the level of the supply voltage VDD, and the second target level of the chip select signal CS_n may be set to the level of the ground voltage VSS.

In step S11, when the level of the chip select signal CS_n transitions from the preset level to the first target level such that the semiconductor device enters the self-refresh operation, the first receiver207may set the first internal chip select signal ICS1to the preset logic level by comparing the level of the chip select signal CS_n to the level of the reference voltage VREF_CS.

In step S13, when the first internal chip select signal ICS1has the preset logic level, the command pulse generation circuit215may generate the command pulse SREP from the command address CA with a logic level combination for entering into the self-refresh operation.

In step S15, the operation control circuit217may activate the self-refresh signal SREF and the internal self-refresh signal ISREF based on the command pulse SREP. The operation control circuit217may enable the second receiver209based on the activated self-refresh signal SREF. In step S17, the operation control circuit217may activate the resistor value change signal RTT_C for adjusting the value of the termination resistor (RTT ofFIG.3) to the preset value based on the activated self-refresh signal SREF.

FIG.16is a timing diagram for describing an operation that is performed when a delay time td1elapses after the semiconductor device120, illustrated inFIG.2, has entered the self-refresh operation.

In step S21, when the level of the chip select signal CS_n transitions from the preset level to the second target level after the delay time td1elapses after the semiconductor device has entered the self-refresh operation, the first receiver207may set the first internal chip select signal ICS1to the preset logic level by comparing the level of the chip select signal CS_n to the level of the reference voltage VREF_CS.

In step S23, when the first internal chip select signal ICS1has the preset logic level in a period in which the self-refresh signal SREF is activated, the operation control circuit217may deactivate the enable signal EN to disable the first receiver207and the termination resistor (RTT ofFIG.3). Thus, when the delay time td1elapses after the semiconductor device has entered the self-refresh operation, the operation control circuit217may switch the first receiver207of the chip select signal receiver205to the second receiver209of the chip select signal receiver205.

In step S25, when the level of the chip select signal CS_n transitions from the preset level to the second target level after the delay time td1elapses after the semiconductor device has entered the self-refresh operation, the second receiver209may change the logic level of the second internal chip select signal ICS2from the first logic level to the second logic level.

In step S27, when the logic level of the second internal chip select signal ICS2transitions from the first logic level to the second logic level in a period in which the enable signal EN is deactivated, the operation control circuit217may activate the flag (FLAG ofFIG.9). In step S29, when the flag FLAG is activated, the operation control circuit217may deactivate the resistor value change signal RTT_C in order to set the value of the termination resistor (RTT ofFIG.3) to a value that is set by the mode register201.

FIG.17is a timing diagram for describing an operation that is performed when the semiconductor device120, illustrated inFIG.2, ends the self-refresh operation.

In step S31, when the level of the chip select signal CS_n transitions from the second target level to the preset level such that the semiconductor device ends the self-refresh operation, the second receiver209may change the logic level of the second internal chip select signal ICS2from the second logic level to the first logic level.

In step S31, when the logic level of the second internal chip select signal ICS2transitions from the second logic level to the first logic level, the operation control circuit217may deactivate the self-refresh signal SREF. The operation control circuit217may disable the second receiver209based on the deactivated self-refresh signal SREF. Furthermore, in step S33, when the logic level of the second internal chip select signal ICS2transitions from the second logic level to the first logic level, the operation control circuit217may activate the enable signal EN to enable the first receiver207and the termination resistor (RTT ofFIG.3) based on the activated flag (FLAG ofFIG.9). Thus, the operation control circuit217may switch the second receiver209of the chip select signal receiver205to the first receiver207of the chip select signal receiver205, when the semiconductor device ends the self-refresh operation.

In step S35, when the enable signal EN is activated, the operation control circuit217may deactivate the activated flag FLAG.

FIG.18is a timing diagram for describing an operation that is performed when an end delay time td2elapses after the semiconductor device120, illustrated inFIG.2, has entered the self-refresh operation.

In step S41, when the level of the chip select signal CS_n transitions from the preset level to the first target level after the end delay time td2elapses after the semiconductor device has ended the self-refresh operation, the first receiver207may compare the level of the chip select signal CS_n to the level of the reference voltage VREF_CS, and set the first internal chip select signal ICS1to the preset logic level.

In step S43, when the first internal chip select signal ICS1has the preset logic level in a period in which the self-refresh signal SREF is deactivated, the operation control circuit217may deactivate the internal self-refresh signal ISREF.

As described above, the semiconductor device in accordance with the present embodiment may adjust the value of the termination resistor coupled to the receiver that receives the chip select signal when the semiconductor device enters the self-refresh operation to stably control a level variation of the chip select signal, thereby preventing a malfunction that is caused by the level variation of the chip select signal in the self-refresh operation. Furthermore, when the delay time elapses after the semiconductor device has entered the self-refresh operation, the semiconductor device may switch the receiver that receives the chip select signal, and disable the termination resistor coupled to the receiver that receives the chip select signal, thereby reducing the power that is consumed during the period in which the self-refresh operation is performed.

In accordance with some embodiments, the semiconductor device may adjust the value of the termination resistor coupled to the receiver that receives the chip select signal when the semiconductor device enters the self-refresh operation to stably control a level variation of the chip select signal, thereby preventing a malfunction caused by the level variation of the chip select signal in the self-refresh operation.

Furthermore, when the delay time elapses after the semiconductor device has entered the self-refresh operation, the semiconductor device may switch the receiver that receives the chip select signal, and disable the termination resistor coupled to the receiver that receives the chip select signal, thereby reducing the power that is consumed during the period in which the self-refresh operation is performed.

Although some embodiments of the present teachings have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the present teachings as defined in the accompanying claims.