EPROM/flash EEPROM cell and array configuration

An EPROM structure incorporating Vss isolation transistors having gates on wordlines shared by respective rows of conventional self-aligned EPROM cells, and having source and drain regions connected in series between EPROM cell source regions and the ground Vss terminal. An isolation transistor becomes conductive only when an EPROM cell sharing its wordline is selected. During programming, otherwise possible leakage current through unselected cells sharing the selected bitline is blocked by the Vss isolation transistor. Only one unselected adjacent cell, which shares a common source region with the selected cell, can leak. This leakage, if properly suppressed and compensated, has no disturbance on unselected or selected cells during array programming. The EPROM cell drain punchthrough voltage and channel length can thus be reduced to obtain an EPROM cell with a low threshold voltage, low drain programming voltage, short programming time, low cell junction and bitline capacitance, and high read current. EPROM-type products can be constructed with single low power supplies, on-chip high voltage pumping and high speed read and programming. Additional rows of shared isolation transistors can be formed by adding extra poly2 lines in parallel to the wordlines between EPROM source diffusions to achieve fuller programming isolation. This cell and array isolation configuration can be extended to flash EEPROM type products.

BACKGROUND OF THE INVENTION 
1. Field of the Invention 
This invention relates generally to nonvolatile EPROM and flash EEPROM 
circuits, and more particularly to techniques of isolating unselected 
cells during programming and reading of selected cells in EPROM and flash 
EEPROM arrays. 
2. Discussion of the Prior Art 
Referring to FIG. 1, a typical prior art erasable programmable read only 
memory (EPROM) 10 comprises an array of EPROM transistors or cells (of 
which for the sake of clarity only nine cells T1-T9 are shown) sharing 
drain regions D1-D9 which are connected to array bitlines BLa-BLc sharing 
common source regions connected to a hardwire line Vss1 to ground, and 
having control gates C1-C9 which are shared as array wordlines WLa-WLc. 
FIG. 2 shows a prior art N-channel enhancement mode EPROM cell 20 in a 
cross-section across control gate 22. The shared second layer 
polycrystalline silicon (poly2) control gate 22 is stacked on top of oxide 
or nitride/oxide dielectric film 24, which lies over poly1 floating gate 
26, which lies over thermally grown thin oxide layer 28 over channel 30 
between N++ source region 32S and N++ drain region 34D in P-type silicon 
substrate 36. 
The FIG. 1 prior art EPROM array 10 is typically laid out in rows and 
columns on substrate 36 as partially shown in FIG. 3. In columns Ca and Cb 
transistors T1, T4 and T2, T5 have their drain regions D1, D4 and D2, D5 
connected through contacts CD1, CD4 and CD2, CD5, respectively, by metal 
bitlines (omitted for the sake of clarity) overlying insulation on poly2 
wordlines WLa and WLb. Common source region Sa-b is connected through 
contact CS by a Vss hardwire metal line, also not shown, running over 
insulation, to a ground terminal. Poly2 control gate wordlines WLa and WLb 
run over rows of poly1 floating gates F1, F2, and F4, F5 in columns Ca and 
Cb between the discrete drain regions and common source region Sa-b to 
form conventional fully self-aligned EPROM cells T1, T2, T4 and T5. 
An EPROM cell 20 in the unprogrammed state (before programming or after 
erasure by ultra-violet light), has essentially no electron charge 
residing on floating gate 26, and the cell has a low switching voltage 
threshold Vt1 requiring only about 1.5 volts on control gate 22 to 
establish conduction through channel 30. To program the cell to a state 
with a high switching voltage threshold Vth, a high (up to 8V) drain 
programming voltage Vdp is pulsed to drain 34d and a higher (up to 14V) 
control gate programming voltage Vcp is pulsed to control gate 22, while 
both the source 32S voltage Vs and the substrate 36 voltage Vbb are held 
at zero. The high programming drain voltage Vdp and control gate voltage 
Vcp bias EPROM transistor 20 into its saturation condition and control 
gate 22 is capacitively coupled to active channel region 30 to establish a 
strong vertical electrical field which exerts a high (8 to 10) voltage on 
floating gate 26. The vertical field generates many hot electrons in 
channel 30 at the pinch-off region close to the drain junction, some of 
which are attracted toward floating gate 26 with sufficient kinetic energy 
to surmount the Si-Si02 interoxide barrier, penetrate floating gate oxide 
layer 28, become trapped inside floating gate 26 and raise the threshold 
voltage Vt to a programmed high (normally above 5 volts) level Vth. 
Generally, EPROMS are programmed at a high drain voltage Vdp in order to 
generate maximum quantities of channel hot electrons. If a selected cell 
T5 (FIG. 1) is programmed by applying Vdp=8 volts to its drain D5 bitline 
BLb and applying Vcp=14 volts to its gate C5 wordline WLb, then, on the 
selected bitline BLb, the unselected cells T2 and T8 also receive 8 volts 
on their drains D2 and D8 while receiving zero volts on their control 
gates C2 and C8. FIG. 4 shows the equivalent circuit for the adjacent 
unselected cells Tun=T2 and T8 with drains on the selected bitline Blb. 
The high Vdp on bitline BLb shared by unselected cell drains D2 and D8 
couples to their floating gates F2 and F8, slightly turning on unselected 
cells T2 and T8 to conduct leakage currents. This is a "grounded gate 
turn-on" or "grounded gate drain breakdown" (so-called BVDSS) condition. 
The lower the BVDSS. Breakdown Voltage Between the Drain and the Source 
when the gate is shorted to the source ("BVDSS"), the higher the leakage 
current. If a high density memory array 10 incorporates 1,000 wordlines 
and if at this high drain programming voltage Vdp on a selected bitline, 
each unselected cell has a 1uA leakage current, the selected bitline has a 
1mA leakage current added to the programming current (about 0.5mA-1.0mA) 
for the selected cell. At worst, leakage currents can exceed 1mA. High/low 
density EPROM memory cell's BVDSS vary cell by cell, chip by chip, and 
wafer by wafer. Therefore, conventional high/low density and high/regular 
speed nonvolatile EPROM cells require a BVDSS guardband for a margin of 
safety. Prior art cells using a drain programming voltage of Vdp=8 volts 
needed a high drain breakdown voltage of around 10 to 11 volts to 
guarantee suitable unselected cell isolation and programmability. This 
drain breakdown voltage limitation makes it difficult to scale down the 
prior art EPROM cell channel length and implant concentration. Programming 
isolation is a major concern when a conventional EPROM cell channel length 
is scaled down to short channel regions (such as 1.0um). This high BVDSS 
criteria in a conventional EPROM cell 20 requires increasing the doping 
concentration in channel region 30, which undesirably significantly 
reduces cell 20 current, increases the bitline junction capacitance, and 
limits the scale-down capability of the channel 30 length and of the cell 
20 size. Thus, high density megabit EPROMs have been hard to produce at 
high yield rates with consistently optimized array programmability and 
high read/write speeds. Alleviating the BVDSS guardband constraint could 
facilitate manufacturing EPROM arrays with more consistent 
programmability, smaller size, higher read access speed, and higher 
manufacturing yields. 
Referring to FIG. 5, U.S. Pat. No. 4,328,565 to Harari teaches an EPROM 
cell 50 in which control gate 52,52' extends beyond the left edge 56L of 
floating gate 56,56' and beyond underlying (first) channel portion 61 
towards source region 62S to overlap substrate 66 and form a control gate 
(second) channel portion 62 extending from first channel portion 61 in 
series to source region 62S. Control gate 52,52' is less strongly 
capacitively coupled to drain 64D and does not invert the second channel 
portion 62 in an unselected cell when drain region 64D of that cell is 
subjected to a high Vdp during programming of an adjacent selected cell. 
The non-inverted second channel portion 62 blocks leakage current from 
flowing through first channel portion 61. The two channel portions 61 and 
62 are manufactured simultaneously, and hence their combined total length 
60 is constantly defined by a mask (not shown). However, each portion's 
separate length is inconstantly defined by the non-self-aligned gates 
52,52' and 56,56', and these inconstant channel portion lengths 61 and 62 
result in inconstant programmability and read current in Harari's cell. 
FIG. 5 also shows how, in a partially self-aligned split gate EPROM as 
disclosed by Eitan in U.S. Pat. No. 4,639,893, the floating gate channel 
length 61 (which is more important than the total channel length 60) can 
be consistently defined by the poly1 floating gate 56 length (omitting 
floating gate portion 56') and by the drain 64D N++ion implant which is 
self-aligned to the right edge 57 of poly1 floating gate 56. The control 
gate 52,52' (MOS) channel length 62 is not consistent but rather depends 
upon the alignment of the source 62S and drain 64D N++ion implant mask 
(not shown) which is not perfectly aligned to poly1 gate 56. Therefore, in 
Eitan the total channel length 60 is not constant, which compromises the 
cell 50 read current distribution. A too-short channel 60 can cause 
channel "punchthrough" conduction from drain 64D, when at high voltage, to 
source 62S. These non-alignment constraints do not allow making the 
control gate channel length 62 too short, and thereby limit scaling down 
the dimensions of such a prior art partially self-aligned split gate EPROM 
cell 50. 
As shown in FIG. 6 Eitan exploits the constant floating gate channel length 
61 to increase array density by using a virtual ground array structure in 
which, during programming cell T14, all unselected bitlines BLd, BLe and 
BLg and unselected wordlines WLd and WLf are clamped at the ground (zero 
volts) potential while high voltages are applied to selected wordline WLe 
and bitline BLf. Bitline BLf is shared (as the source) by adjacent 
unselected cell T15. In cell T15 hot electrons will be injected toward the 
control gate 52,52' and surface states may be generated at the source side 
62S. A portion of these channel hot electrons reach and become trapped 
inside of the floating gate 56 of T15, to a degree dependent upon the 
electrical field between the T15 floating gate and the T15 channel surface 
beneath the left edge of its floating gate. Surface states and trapped 
electrons both increase the cell T15 threshold voltage Vt and compromise 
its reliability. Another problem of this prior art EPROM structure is that 
for each cell T10-T18 programming current is effectively doubled, which 
diminishes the attractiveness and practicality of multiplebyte 
programming. 
FIG. 5 further shows how a prior art overlapping control gate cell can be 
modified as described by Samachisa et al. in an article entitled "A 128K 
Flash EEPROM Using Double-Polysilicon Technology" in the IEEE Journal of 
Solid-State Circuits, Vol. sc-22, No. 5, Oct. 1987. The flash EEPROM array 
cells are all erased simultaneously by application of a high (19V) voltage 
on the drain with the source and gate grounded. Unlike UV erasure, this 
usually over-erases the floating gate, leaving the floating gate with a 
positive charge so that the flash EEPROM is a (normally-on) depletion mode 
transistor ready to conduct leakage current when an adjacent cell is 
selected for programming or reading. The cell's total channel length 60 is 
constantly defined by the poly2 mask (not shown) between control gate 52 
left edge 51 and right edge 53. However, only the right edge 57 of poly1 
floating gate 56 is self-aligned to edge 53 of poly2 control gate 52, so 
neither the floating gate channel length 61 nor the control gate channel 
length 62 is constant. This flash EEPROM cell has more drawbacks than the 
Eitan partially self-aligned cell because the flash EEPROM variable 
floating gate channel length 61 and resulting uncontrollable MOS 
punch-through voltage and read current cause programming inconsistency and 
limit scale-down of the cell. 
Thus, there remains a need for shorter and more constant length channels in 
EPROM cells isolated from drain turn-on conditions in order to achieve 
high efficiency and consistent programming, fast read speed, and 
scale-down ability without sacrificing performance for high or low density 
EPROM or flash EEPROM products. 
SUMMARY OF THE PRESENT INVENTION 
Briefly, a preferred embodiment of the present invention provides an EPROM 
array with means for isolating unselected non-adjacent cells during 
programming and reading by providing Vss Isolation transistors I shared by 
one or more (conventional fully self-aligned stacked) floating gate EPROM 
transistors Q on each wordline, and thereby allows independent 
optimization for the EPROM cell read current (speed) and drain breakdown 
(turn-on) voltage BVDSS. The EPROM cells' common source N++diffusion 
functions as the drain of the Vss isolation transistor. The size of the 
isolation transistors can be independently optimized for programming and 
reading. The isolation transistors allow scaling down EPROM cells for both 
high speed and high/low density applications. In this invention, EPROM 
cell channels are fully selfaligned and thus have a constant length, 
resulting in a tight distribution of cell read current and access speed. 
Very short and constant length channel cells can be implemented with 
greatly enhanced programming efficiency and reading speed. Because the 
EPROM and Vss isolation transistors are defined by the same (poly2) 
control gate, they track each other closely for read current, drain 
breakdown voltage, threshold voltage, and other characteristics. Another 
significant advantage is that unselected cell isolation is insensitive to 
process variations which in the prior art would otherwise be the major 
cause for yield losses. The short channel length also enables programming 
EPROM cells with a drain voltage Vdp as low as only 5 to 6 volts. With an 
on-chip high voltage pump for the control gate programming voltage Vcp, 
high/low read speed and high/low density EPROM related products can be 
realized with a single TTL power supply of only 5 to 6 volts. 
For flash EEPROM (as well as EPROM) applications, to separate the commonly 
shared source diffusion regions of adjacent unselected cells, an extra 
isolation transistor can be employed by running an extra poly2 line in the 
center, and on top of, the split-common source diffusion, in parallel to 
the wordlines, to form an extra N-channel enhancement mode isolation 
transistor. In either EPROMs or flash EEPROMs with this poly2 layer tied 
to the ground potential during programming, and for EEPROMs during 
reading, any leakage current from possibly over-erased adjacent cells will 
be blocked effectively by the extra isolation transistor in conjunction 
with the Vss isolation transistor. If a flash EEPROM cell can be designed 
to avoid over-erasures (to negative threshold voltages Vt1), this extra 
poly2 enhancement mode N-channel isolation transistor can be dispensed 
with, and the flash EEPROM array layout and read characteristics will be 
the same as those of the EPROM array. Thus, the invention is suitable for 
implementing both low or very high density and low or high speed EPROM and 
flash EEPROM products. 
These and other objects of the present invention will become apparent to 
those of ordinary skill in the art upon reading the following detailed 
description of the preferred embodiments as illustrated in the 
accompanying drawing figures.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
FIG. 7 is a schematic diagram of an EPROM array 70 comprising fully 
self-aligned (floating gate) EPROM cells or transistors Q1 through Q12, 
array wordlines WL1 through WL4 connected to control gates C1-C12 of EPROM 
cells in respective rows, array bitlines BL1 through BL3 connected to 
drains D1-D12 of EPROM cells in respective columns, hardwire line Vss to a 
ground terminal, and, in accordance with this invention, Vss isolation 
transistors I1-I4, preferably enhancement mode N-channel MOS devices 
having gates G1-G4 formed by respective poly2 wordlines WL1-WL4, and each 
having a source and a drain connected in series between the sources of the 
EPROM transistors Q connected to the same wordline WL and the Vss ground 
terminal. 
To program a selected cell 55, the selected cell bitline BL2 potential Vd 
is raised to approximately Vdp=5 to 6 volts and the selected cell wordline 
WL2 potential Vc is raised to a maximum of Vcp=13 to 15 volts. The high 
gate programming voltage Vcp=13 to 15 volts (or reading voltage Vcr=Vcc-Vt 
or Vcc) on selected wordline WL2 rapidly turns on isolation transistor I2. 
The high gate programming voltage Vcp gives the isolation transistors a 
high transconductance and allows making them very small. The isolation 
transistor channel length and width can be designed to independently 
optimize the transconductance Gm, and drain breakdown voltage BVDSS, 
without sacrificing conventional EPROM cell 20 performance. Y-mux lines 
YMUX-1 and YMUX-3 turn on respective pull-down transistors QA and QC to 
clamp nonselected bitlines BL1 and BL3 to ground, and any leakage current 
through selected wordline WL2 unselected transistors Q4 and Q6 assists the 
turned-on isolation transistor I2 to ensure that the selected cell Q5 
source region S5 remains close to the ground potential, which makes 
programming consistent for each cell in the array 70. During programming 
of selected cell Q5, the unselected wordline WL1, WL3 and WL4 potentials 
are clamped through X-decoder N-channel pull-up devices (not shown) to the 
ground potential. 
FIG. 8 shows for the invention the equivalent circuit of an unselected 
non-adjacent cell Qun=Q8 or Q11 on the selected bitline BL2, for 
comparison with the FIG. 1 prior art equivalent circuit shown in FIG. 4. 
In the invention, any leakage (punch-through) current from a nonadjacent 
unselected cell Qun is blocked by Vss isolation transistor Iun, as long as 
Iun stays turned-off to float the source node of Qun. The only cell 
disturbed during programming of cell Q5 is adjacent unselected cell Q2 
which shares with the selected cell Q5 source N++ diffusion region S2=S5 
which is connected through turned-on isolation transistor I2 to the Vss 
ground line. FIG. 9 shows the disturbed adjacent cell drain turn-on 
characteristic curve. The table below shows that repeated disturbances do 
not change an adjacent unselected disturbed cell's switching voltage 
threshold Vt1 or drain turn-on breakdown voltage BVDSS: 
______________________________________ 
Vt1 BVDSS 
______________________________________ 
After UV erase .8 V 3.6 V 
1 pulse (6 V @ 1 ms) 
.8 V 3.6 V 
1000 pulses (6 V @ 1 ms) 
.8 V 3.6 V 
______________________________________ 
In practice, only unprogrammed (or erased) cells can be disturbed, and they 
will only be disturbed once per programming of the array, because the 
source-sharing adjacent cell will at most be programmed only once per 
programming of the array. Once programmed, a cell's BVDSS is typically 3 
volts higher and the cell will not be stressed if its source-sharing 
neighbor is programmed afterwards. In contrast, in the prior art, the 
number of stressings on each cell is proportional to the number of cells 
on the same bitline, which can be up to 1,000 cells. Adjacent unselected 
EPROM cell leakage current can be compensated for by supplying more 
current to the selected bitline during programming. 
Leakage current blocking by the isolation transistors relieves the EPROM 
cell BVDSS guardband constraint and allows reducing the minimum BVDSS, 
which in turn allows shortening the EPROM channel. EPROM arrays can be 
fabricated with short constant length channels of around 1.0um for EPROM 
transistors and constant length channels of around 1.0um to 1.2um for Vss 
isolation transistors. Small variations in channel length do not 
significantly affect the drain breakdown voltages of unselected cells on 
the selected cell bitline because the Vss isolation transistor blocks 
leakage current. This improves the manufacturing yield rate. The drain 
breakdown voltage BVDSS of (unselected and selected) EPROM, cells can even 
be lower than the drain programming voltage Vdp, as long as any leakage 
current is compensated for by using a stronger pull-up device in the data 
input buffer (not shown). Channel length shortening allows scaling down 
cell size for megabit EPROMs, which reduces the cell junction capacitance, 
improves programming efficiency, increases the cell read current, and 
raises EPROM product manufacturing yield rates. 
FIG. 10 shows the one-shot Ids-Vds curve with Vgs=15 volts for a 1um length 
channel EPROM cell. This EPROM cell can be programmed with Vds=6.0 volts. 
The high programming voltage Vcp applied to the control gate draws very 
little current and can be rapidly charged-pumped from a 5 or 6 volt power 
supply. Experimental results show that a BVDSS=3 to 4 volts is 
satisfactory for a programming Vdp=5 to 6 volts. Since according to the 
present invention the drain programming Vdp is as low as the regular TTL 
power supply, there is no need for a high voltage power supply (Vpp). 
Therefore, in EPROM related products, Vpp can be omitted or used for test 
modes or for other control logic to enhance the production yield. This 
invention thus enables designing EPROM type products which require only a 
single 5 or 6 volt low power supply and which therefore can be programmed 
in the field. FIG. 11 shows the Vt1 before and the Vth after a 0.1 msec 
fast programming pulse. A Vth of more than 7 to 8 volts can be easily 
obtained. Whereas the conventional EPROM cell Vt1 ranges from 1.5 to 2 
volts in order to obtain a high drain breakdown voltage, according to this 
invention the cell Vt1 can be as low as 0.8 to 1.0 volts, which allows low 
bitline diffusion capacitance, high read current, and fast access speed. 
The low cell Vt1 eliminates the need for implanting a high dose of Boron 
and eliminates the need for an implant mask to block a high dosage from 
being implanted into periphery transistors, which simplifies the 
conventional EPROM fabrication process, reduces manufacturing costs and 
improves throughput. Since the EPROM cell drain breakdown voltage is no 
longer a major concern, the source/drain oxidation after source/drain 
implantation can be longer to increase the floating gate overlap over the 
drain N++diffusion and thereby further increase programming efficiency and 
manufacturing yield rates. 
This invention is preferably implemented using well known technologies for 
fabricating EPROM products. According to one embodiment of the invention, 
isolation transistors are formed in EPROM arrays laid out generally as 
shown in FIG. 12, for comparison with the prior art EPROM array layout of 
FIG. 3. In FIG. 12, drain regions in each column C1, C2 are connected 
through contacts CD2, CD5-8, and CD3, CD6-9, respectively, by metal lines 
(not shown) lying on insulation over poly2 wordlines WL1, WL2 and WL3. The 
addition of the Vss isolation transistors I1, I2 does not necessarily 
increase the EPROM array die size over prior art EPROM array die sizes 
because the FIG. 3 prior art Vss diffusion Sa-b contact CS "real estate" 
can be used to form FIG. 12 Vss isolation transistors I1, I2, etc. In the 
invention, source N+diffusion region S1-2 has no direct contact but is 
extended vertically and self-aligned to edges of poly2 wordlines WL1, WL2, 
etc. to provide drain regions for isolation transistors I1, I2, etc. The 
vertically opposite sides of poly2 wordlines WL1 and WL2 are provided with 
respective isolation transistor source regions and further provided with 
contacts CS1, CS2, etc. Isolation transistors I1, I2, etc. have no poly1 
floating gate under their poly2 wordline, which is lowered over the 
channels of the isolation transistors to obtain a high current gain. 
On each wordline WL, the number of EPROM transistors Q which can share a 
given Vss isolation transistor I depends upon the intended application and 
speed of the EPROM device. For high density EPROM products 130 as shown in 
FIG. 13, approximately 8 to 16 EPROM cells Q may share each Vss isolation 
transistor I. Low density EPROM ( (R)) product 140 speed can be 
improved by providing each EPROM cell with a respective Vss isolation 
transistor as shown FIG. 14. 
FIGS. 15 and 16 show how this invention can be embodied in flash EEPROM 
structures 155 and 160, respectively, by adding long poly2 lines 150 
parallel to the wordlines WL and in the middle of split common source 
diffusions to form an additional poly2 isolation transistor with a minimum 
channel length, because the separation between its source and drain 
regions is relatively small. To achieve full isolation of adjacent cells 
during programming and reading, each extra poly2 line 150 is held at the 
ground potential, and will block leakage current from a possibly 
over-erased (negative Vt) cell adjacent the selected cell on the same 
bitline. During reading operations, the extra poly2 line 150 can be biased 
to Vcc to electrically remove this isolation to achieve low common source 
resistance for higher speed reading if the cell Vt is positive. The 
majority of drain current during electrical flash erasure will thus result 
from Fowler-Nordheim tunneling, which is very small for single cells. The 
required high voltage on the drain during erasure can be charge-pumped 
from Vcc, permitting realization of a single power supply flash EEPROM. 
This new flash EEPROM cell can be combined with the new Vss isolation 
transistor to achieve very high density products. This increases flash 
EEPROM cell size by about 10% to 15%, but not to the size of the FIG. 5 
prior art flash EEPROM cell. Field isolation by adequate spacing between 
source N++ diffusions can be employed instead of the extra poly2 isolation 
transistor, but would increase the array size. If flash electrical erase 
can be controlled to avoid overerasures, this extra poly2 line can be 
eliminated, to yield EPROM and flash EEPROMs with essentially equivalent 
structures, although in practice flash EEPROM arrays differ slightly from 
EPROM arrays. The extra poly2 line 150 can be used in an EPROM array to 
achieve full isolation during programming. The cell programming efficiency 
is not degraded because a constant length short channel can be used. 
FIG. 17 shows a cross-section through a flash EEPROM cell 170 which may be 
used in arrays according to this invention. This cell is similar to the 
FIG. 2 conventional self-aligned EPROM cell except that it incorporates a 
double-diffused drain region to increase the drain breakdown voltage 
during erasure. The double diffused drain decreases leakage current at the 
drain junction 175 and drain surface beneath the floating gate. 
Although the present invention has been described above in terms of several 
preferred embodiments, it will be appreciated by those skilled in the art 
that additional alterations and modifications thereof may be made without 
departing from the essence of the invention. It is therefore intended that 
the appended claims be interpreted as covering all such alterations and 
modifications as fall within the true spirit and scope of the invention.