Method of manufacturing a super junction structure and super junction structure

A method of manufacturing a super junction structure includes etching a material to define a trench, wherein the trench has a tapered profile. The method further includes implanting dopants into sidewalls and a bottom surface of the trench to define a doped region, wherein the doped region surrounds the trench. The method further includes depositing an undoped material into the trench. The method further includes performing a thermal process, wherein the thermal process drives the dopants from the doped region into the undoped material to form a conductive pillar in the trench.

BACKGROUND

A super junction MOSFET features higher breakdown voltage and lower Rds (i.e., drain-to-source resistance) in view of a typical MOSFET. A super junction structure of the MOSFET is a region of alternating conductivity types in a substrate, such as the super junction structure includes p-type columns and n-type columns alternatively arranged in the substrate.

The p-type columns of the super junction structure are individually under source electrodes of the MOSFET, which however is difficult to have good performance and to integrate the MOSFET in a planar device. On the other hand, concerning the fabrication of the super junction MOSFET, multi-epi and doping processes with masks are required for the p-type columns and n-type columns, which results in poor uniformity, long process time and high cost.

DETAILED DESCRIPTION

As mentioned, the p-type columns of the super junction structure are individually under source electrodes of the MOSFET, which however is difficult to have good performance and integrate the MOSFET in a planar device. Further, the p-type columns and n-type columns are fabricated by multi-epi and doping processes with masks, which however results in poor uniformity, long process time and high cost. To address the above issue, a semiconductor device having a super junction structure, a method for manufacturing the semiconductor device and a method for manufacturing the super junction structure are provided.

Compared with the p-type columns of the super junction structure individually under source electrodes of the MOSFET, the semiconductor device of the present disclosure includes a pillar under a gate trench, which has better performance and makes it possible to integrate semiconductor device in a planar device. In addition, the method for manufacturing the super junction structure, in accordance with the present disclosure, includes forming a trench and a pillar of a conductivity type from an undoped material in the trench, which exhibits better uniformity, less process time and lower cost compared with fabrication of a super junction structure by the multi-epi process.

Embodiments of the semiconductor device having the super junction structure, the method for manufacturing the semiconductor device and the method for manufacturing the super junction structure are sequentially described below in detail.

FIG. 1is a cross-sectional view of a semiconductor device100having a super junction structure, in accordance with some embodiments. InFIG. 1, the semiconductor device100having a super junction structure includes a substrate110, an epitaxial layer120, a plurality of pillars130, a plurality of gate trenches140, an insulating layer150and a plurality of doped wells160.

In some embodiments of the present disclosure, the substrate110is a doped substrate of the first conductivity type. In some embodiments of the present disclosure, the substrate110is an n-doped substrate. In some embodiments of the present disclosure, the n-type dopant includes, but not limited to, arsenic, phosphorous, another suitable n-type dopant or a combination thereof. In some embodiments of the present disclosure, the substrate110is a heavily doped substrate. In some embodiments of the present disclosure, the substrate110is acted as a drain electrode. In some embodiments of the present disclosure, the substrate110includes, but not limited to, an elementary semiconductor including silicon or germanium in crystal, polycrystalline or an amorphous structure; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide or a combination thereof; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP or a combination thereof; any other suitable material or combinations thereof.

The epitaxial layer120of a first conductivity type is on the substrate110. In some embodiments of the present disclosure, the epitaxial layer120is an n-doped epitaxial (n-epi) layer. In some embodiments of the present disclosure, the epitaxial layer120includes silicon, germanium, another suitable n-type semiconductor material or the combination thereof.

The pillars130of a second conductivity type are in the epitaxial layer120. In some embodiments of the present disclosure, the second conductivity type is opposite to the first conductivity type. In some embodiments of the present disclosure, the pillars130are p-doped pillars. In some embodiments of the present disclosure, the pillars130include p-type dopants and thus can be acted as a p-type column. In some embodiments of the present disclosure, the p-type dopants in the pillars130include boron, boron difluoride, another suitable p-type dopant or a combination thereof.

In some embodiments of the present disclosure, each of the pillars130is a multilayer structure. In some embodiments of the present disclosure, the multilayer structure is a multilayer of the second conductivity type. In some embodiments of the present disclosure, each of the pillars130is a p-doped multilayer structure. In some embodiments of the present disclosure, the multilayer structure of the pillars130is fabricated by multi-epi and doping processes with masks.

The gate trenches140are individually correspond to and over the pillars130, and the insulating layer150is in the gate trenches140. In some embodiments of the present disclosure, the pillars130are individually in contact with the insulating layer150in the gate trenches140. In some embodiments of the present disclosure, the insulating layer150includes a conductive material such as polysilicon or another suitable conductive material. In some embodiments of the present disclosure, the insulating layer150includes a dielectric material, such as silicon dioxide, a silicon nitride or another suitable dielectric material. In some embodiments of the present disclosure, the insulating layer150is an air gap. In some embodiments of the present disclosure, the insulating layer150can be acted as a gate insulating layer and in contact with a gate electrode.

In some embodiments of the present disclosure, the semiconductor device100further includes another insulating layer between the insulating layer150and an inner surface of the gate trenches140. In some embodiments of the present disclosure, the additional insulating layer includes silicon dioxide, aerogel, silicon nitride, silicon oxynitride, another suitable insulating material or a combination thereof.

The doped wells160of the second conductivity type are in the epitaxial layer120. In some embodiments of the present disclosure, each of the doped wells160is between two adjacent gate trenches140. In some embodiments of the present disclosure, the doped wells160are p-doped wells. In some embodiments of the present disclosure, the doped wells160include p-type dopants and thus can be acted as a p-type semiconductor wells. In some embodiments of the present disclosure, each of the doped wells160is in contact with a source electrode. In some embodiments of the present disclosure, the p-type dopants in the doped wells160include boron, boron difluoride, another suitable p-type dopant or a combination thereof.

FIG. 2is a cross-sectional view of a semiconductor device200having a super junction structure, in accordance with some embodiments. InFIG. 2, the semiconductor device200having a super junction structure includes a substrate210, an epitaxial layer220, a plurality of pillars230, a plurality of gate trenches240, an insulating layer250and a plurality of doped wells260.

In some embodiments of the present disclosure, the substrate210is a doped substrate of the first conductivity type. In some embodiments of the present disclosure, the substrate210is acted as a drain electrode. The epitaxial layer220of a first conductivity type is on the substrate210. In some embodiments of the present disclosure, the epitaxial layer220is an n-epi layer.

The pillars230of a second conductivity type are in the epitaxial layer220. In some embodiments of the present disclosure, the second conductivity type is opposite to the first conductivity type. In some embodiments of the present disclosure, the pillars230are p-doped pillars. In some embodiments of the present disclosure, the pillars230include p-type dopants and thus can be acted as a p-type column. In some embodiments of the present disclosure, each of the pillars230is a multilayer structure. In some embodiments of the present disclosure, the multilayer structure is a multilayer of the second conductivity type. In some embodiments of the present disclosure, each of the pillars230is a p-doped multilayer structure.

The gate trenches240are individually correspond to and over the pillars230, and the insulating layer250is in the gate trenches240. In some embodiments of the present disclosure, the pillars230are individually in contact with the insulating layer250in the gate trenches240. In some embodiments of the present disclosure, the insulating layer250includes an oxide layer254disposed on an inner surface of the gate trenches240; and a polymer material252disposed on the oxide layer254and in the gate trenches240. In some embodiments of the present disclosure, the polymer material252includes a conductive material such as polysilicon or another suitable conductive material. In some embodiments of the present disclosure, the polymer material252and the oxide layer254individually include a dielectric material, such as silicon dioxide, a silicon nitride or another suitable dielectric material. In some embodiments of the present disclosure, the polymer material252includes an air gap. In some embodiments of the present disclosure, the insulating layer250can be acted as a gate insulating layer and in contact with a gate electrode.

In some embodiments of the present disclosure, the semiconductor device200further includes another insulating layer between the insulating layer250and an inner surface of the gate trenches240. In some embodiments of the present disclosure, the additional insulating layer includes silicon dioxide, aerogel, silicon nitride, silicon oxynitride, another suitable insulating material or a combination thereof.

The doped wells260of the second conductivity type are in the epitaxial layer220. In some embodiments of the present disclosure, each of the doped wells260is between two adjacent gate trenches240. In some embodiments of the present disclosure, the doped wells260are p-doped wells. In some embodiments of the present disclosure, the doped wells260include p-type dopants and thus can be acted as a p-type semiconductor wells. In some embodiments of the present disclosure, each of the doped wells260is in contact with a source electrode.

FIG. 3is a cross-sectional view of a semiconductor device300having a super junction structure, in accordance with some embodiments. InFIG. 3, the semiconductor device300having a super junction structure includes a substrate310, an epitaxial layer320, a plurality of pillars330, a plurality of gate trenches340, an insulating layer350, a plurality of doped wells360and a bury layer370.

In some embodiments of the present disclosure, the substrate310is a doped substrate of the second conductivity type. In some embodiments of the present disclosure, the substrate310is a p-doped substrate. In some embodiments of the present disclosure, the substrate310includes p-type dopants and thus can be acted as a p-type base. In some embodiments of the present disclosure, the p-type dopants in the substrate310include boron, boron difluoride, another suitable p-type dopant or a combination thereof. The epitaxial layer320of a first conductivity type is on the substrate310. In some embodiments of the present disclosure, the epitaxial layer320is an n-epi layer.

The bury layer370of the first conductivity type is between the substrate310and epitaxial layer320. In some embodiments of the present disclosure, the bury layer370is an n-doped bury layer. In some embodiments of the present disclosure, the bury layer370includes silicon, germanium, another suitable n-type semiconductor material or the combination thereof. In some embodiments of the present disclosure, the bury layer370is acted as an interlayer to conduct from a top source electrode to a top drain.

The pillars330of a second conductivity type are in the epitaxial layer320. In some embodiments of the present disclosure, the second conductivity type is opposite to the first conductivity type. In some embodiments of the present disclosure, the pillars330are p-doped pillars. In some embodiments of the present disclosure, the pillars330include p-type dopants and thus can be acted as a p-type column. In some embodiments of the present disclosure, each of the pillars330is a multilayer structure. In some embodiments of the present disclosure, the multilayer structure is a multilayer of the second conductivity type. In some embodiments of the present disclosure, each of the pillars330is a p-doped multilayer structure.

The gate trenches340are individually correspond to and over the pillars330, and the insulating layer350is in the gate trenches340. In some embodiments of the present disclosure, the pillars330are individually in contact with the insulating layer350in the gate trenches340. In some embodiments of the present disclosure, the insulating layer350includes an oxide layer354disposed on an inner surface of the gate trenches340; and a polymer material352disposed on the oxide layer354and in the gate trenches340. In some embodiments of the present disclosure, the insulating layer350can be acted as a gate insulating layer and in contact with a gate electrode. In some embodiments of the present disclosure, the semiconductor device300further includes another insulating layer between the insulating layer350and an inner surface of the gate trenches340.

The doped wells360of the second conductivity type are in the epitaxial layer320. In some embodiments of the present disclosure, each of the doped wells360is between two adjacent gate trenches340. In some embodiments of the present disclosure, the doped wells360are p-doped wells. In some embodiments of the present disclosure, the doped wells360include p-type dopants and thus can be acted as a p-type semiconductor wells. In some embodiments of the present disclosure, each of the doped wells360is in contact with a source electrode.

FIG. 4is a cross-sectional view of a semiconductor device400having a super junction structure, in accordance with some embodiments. InFIG. 4, the semiconductor device400having a super junction structure includes a substrate410, an epitaxial layer420, a plurality of pillars430, a plurality of gate trenches440, an insulating layer450and a plurality of doped wells460.

In some embodiments of the present disclosure, the substrate410is a doped substrate of the first conductivity type. In some embodiments of the present disclosure, the substrate410is acted as a drain electrode. The epitaxial layer420of a first conductivity type is on the substrate410. In some embodiments of the present disclosure, the epitaxial layer420is an n-epi layer.

The pillars430of a second conductivity type are in the epitaxial layer420. In some embodiments of the present disclosure, the second conductivity type is opposite to the first conductivity type. In some embodiments of the present disclosure, the pillars430are p-doped pillars. In some embodiments of the present disclosure, the pillars430include p-type dopants and thus can be acted as a p-type column. In some embodiments of the present disclosure, each of the pillars430is a trench filled with the second conductivity type material. In some embodiments of the present disclosure, the trench has a same pattern as that of the gate trenches.

The gate trenches440are individually correspond to and over the pillars430, and the insulating layer450is in the gate trenches440. In some embodiments of the present disclosure, the pillars430are individually in contact with the insulating layer450in the gate trenches440. In some embodiments of the present disclosure, the insulating layer450includes an oxide layer454disposed on an inner surface of the gate trenches440; and a polymer material452disposed on the oxide layer454and in the gate trenches440. In some embodiments of the present disclosure, the polymer material452includes a conductive material such as polysilicon or another suitable conductive material. In some embodiments of the present disclosure, the polymer material452and the oxide layer454individually include a dielectric material, such as silicon dioxide, a silicon nitride or another suitable dielectric material. In some embodiments of the present disclosure, the polymer material452includes an air gap. In some embodiments of the present disclosure, the insulating layer450can be acted as a gate insulating layer and in contact with a gate electrode. In some embodiments of the present disclosure, the semiconductor device400further includes another insulating layer between the insulating layer450and an inner surface of the gate trenches440.

The doped wells460of the second conductivity type are in the epitaxial layer420. In some embodiments of the present disclosure, each of the doped wells460is between two adjacent gate trenches440. In some embodiments of the present disclosure, the doped wells460are p-doped wells. In some embodiments of the present disclosure, the doped wells460include p-type dopants and thus can be acted as a p-type semiconductor wells. In some embodiments of the present disclosure, each of the doped wells460is in contact with a source electrode.

FIG. 5is a cross-sectional view of a semiconductor device500having a super junction structure, in accordance with some embodiments. InFIG. 5, the semiconductor device500having a super junction structure includes a substrate510, an epitaxial layer520, a plurality of pillars530, a plurality of gate trenches540, an insulating layer550, a plurality of doped wells560and a bury layer570.

In some embodiments of the present disclosure, the substrate510is a doped substrate of the second conductivity type. In some embodiments of the present disclosure, the substrate510is a p-doped substrate. In some embodiments of the present disclosure, the substrate510includes p-type dopants and thus can be acted as a p-type base. The epitaxial layer520of a first conductivity type is on the substrate510. In some embodiments of the present disclosure, the epitaxial layer520is an n-epi layer.

The bury layer570of the first conductivity type is between the substrate510and epitaxial layer520. In some embodiments of the present disclosure, the bury layer570is an n-doped bury layer. In some embodiments of the present disclosure, the bury layer570is acted as an interlayer to conduct from a top source electrode to a top drain.

The pillars530of a second conductivity type are in the epitaxial layer520. In some embodiments of the present disclosure, the second conductivity type is opposite to the first conductivity type. In some embodiments of the present disclosure, the pillars530are p-doped pillars. In some embodiments of the present disclosure, the pillars530include p-type dopants and thus can be acted as a p-type column. In some embodiments of the present disclosure, each of the pillars530is a trench filled with the second conductivity type material. In some embodiments of the present disclosure, the trench has a same pattern as that of the gate trenches.

The gate trenches540are individually correspond to and over the pillars530, and the insulating layer550is in the gate trenches540. In some embodiments of the present disclosure, the pillars530are individually in contact with the insulating layer550in the gate trenches540. In some embodiments of the present disclosure, the insulating layer550includes an oxide layer554disposed on an inner surface of the gate trenches540; and a polymer material552disposed on the oxide layer554and in the gate trenches540. In some embodiments of the present disclosure, the polymer material552includes an air gap. In some embodiments of the present disclosure, the insulating layer550can be acted as a gate insulating layer and in contact with a gate electrode. In some embodiments of the present disclosure, the semiconductor device500further includes another insulating layer between the insulating layer550and an inner surface of the gate trenches540.

The doped wells560of the second conductivity type are in the epitaxial layer520. In some embodiments of the present disclosure, each of the doped wells560is between two adjacent gate trenches540. In some embodiments of the present disclosure, the doped wells560are p-doped wells. In some embodiments of the present disclosure, the doped wells560include p-type dopants and thus can be acted as a p-type semiconductor wells. In some embodiments of the present disclosure, each of the doped wells560is in contact with a source electrode.

FIG. 6is a cross-sectional view of a semiconductor device600having a super junction structure, in accordance with some embodiments. InFIG. 6, the semiconductor device600having a super junction structure includes a substrate610, an epitaxial layer620, a plurality of pillars630, a plurality of gate trenches640, an insulating layer650and a plurality of doped wells660.

In some embodiments of the present disclosure, the substrate610is a doped substrate of the first conductivity type. In some embodiments of the present disclosure, the substrate610is acted as a drain electrode. The epitaxial layer620of a first conductivity type is on the substrate610. In some embodiments of the present disclosure, the epitaxial layer620is an n-epi layer.

The pillars630of a second conductivity type are in the epitaxial layer620. In some embodiments of the present disclosure, the second conductivity type is opposite to the first conductivity type. In some embodiments of the present disclosure, the pillars630are p-doped pillars. In some embodiments of the present disclosure, the pillars630include p-type dopants and thus can be acted as a p-type column. In some embodiments of the present disclosure, each of the pillars630is a trench filled with the second conductivity type material. In some embodiments of the present disclosure, the trench is an angled trench. In some embodiments of the present disclosure, the trench has a same pattern as that of the gate trenches.

The gate trenches640are individually correspond to and over the pillars630, and the insulating layer650is in the gate trenches640. In some embodiments of the present disclosure, the pillars630are individually in contact with the insulating layer650in the gate trenches640. In some embodiments of the present disclosure, the insulating layer650includes an oxide layer654disposed on an inner surface of the gate trenches640; and a polymer material652disposed on the oxide layer654and in the gate trenches640. In some embodiments of the present disclosure, the polymer material652includes a conductive material such as polysilicon or another suitable conductive material. In some embodiments of the present disclosure, the polymer material652and the oxide layer654individually include a dielectric material, such as silicon dioxide, a silicon nitride or another suitable dielectric material. In some embodiments of the present disclosure, the polymer material652includes an air gap. In some embodiments of the present disclosure, the insulating layer650can be acted as a gate insulating layer and in contact with a gate electrode. In some embodiments of the present disclosure, the semiconductor device600further includes another insulating layer between the insulating layer650and an inner surface of the gate trenches640.

The doped wells660of the second conductivity type are in the epitaxial layer620. In some embodiments of the present disclosure, each of the doped wells660is between two adjacent gate trenches640. In some embodiments of the present disclosure, the doped wells660are p-doped wells. In some embodiments of the present disclosure, the doped wells660include p-type dopants and thus can be acted as a p-type semiconductor wells. In some embodiments of the present disclosure, each of the doped wells660is in contact with a source electrode.

FIG. 7is a cross-sectional view of a semiconductor device700having a super junction structure, in accordance with some embodiments. InFIG. 7, the semiconductor device700having a super junction structure includes a substrate710, an epitaxial layer720, a plurality of pillars730, a plurality of gate trenches740, an insulating layer750, a plurality of doped wells760and a bury layer770.

In some embodiments of the present disclosure, the substrate710is a doped substrate of the second conductivity type. In some embodiments of the present disclosure, the substrate710is a p-doped substrate. In some embodiments of the present disclosure, the substrate710includes p-type dopants and thus can be acted as a p-type base. The epitaxial layer720of a first conductivity type is on the substrate710. In some embodiments of the present disclosure, the epitaxial layer720is an n-epi layer.

The bury layer770of the first conductivity type is between the substrate710and epitaxial layer720. In some embodiments of the present disclosure, the bury layer770is an n-doped bury layer. In some embodiments of the present disclosure, the bury layer770is acted as an interlayer to conduct from a top source electrode to a top drain.

The pillars730of a second conductivity type are in the epitaxial layer720. In some embodiments of the present disclosure, the second conductivity type is opposite to the first conductivity type. In some embodiments of the present disclosure, the pillars730are p-doped pillars. In some embodiments of the present disclosure, the pillars630include p-type dopants and thus can be acted as a p-type column. In some embodiments of the present disclosure, each of the pillars730is a trench filled with the second conductivity type material. In some embodiments of the present disclosure, the trench is an angled trench. In some embodiments of the present disclosure, the trench has a same pattern as that of the gate trenches.

The gate trenches740are individually correspond to and over the pillars730, and the insulating layer750is in the gate trenches740. In some embodiments of the present disclosure, the pillars730are individually in contact with the insulating layer750in the gate trenches740. In some embodiments of the present disclosure, the insulating layer750includes an oxide layer754disposed on an inner surface of the gate trenches740; and a polymer material752disposed on the oxide layer754and in the gate trenches740. In some embodiments of the present disclosure, the polymer material752includes a conductive material such as polysilicon or another suitable conductive material. In some embodiments of the present disclosure, the polymer material752and the oxide layer754individually include a dielectric material, such as silicon dioxide, a silicon nitride or another suitable dielectric material. In some embodiments of the present disclosure, the polymer material752includes an air gap. In some embodiments of the present disclosure, the insulating layer750can be acted as a gate insulating layer and in contact with a gate electrode. In some embodiments of the present disclosure, the semiconductor device700further includes another insulating layer between the insulating layer750and an inner surface of the gate trenches740.

The doped wells660of the second conductivity type are in the epitaxial layer720. In some embodiments of the present disclosure, each of the doped wells760is between two adjacent gate trenches740. In some embodiments of the present disclosure, the doped wells760are p-doped wells. In some embodiments of the present disclosure, the doped wells760include p-type dopants and thus can be acted as a p-type semiconductor wells. In some embodiments of the present disclosure, each of the doped wells760is in contact with a source electrode.

FIGS. 8A-8Eare cross-sectional views at various stages of fabricating a semiconductor device800having a super junction structure, in accordance with some embodiments.

As shown inFIG. 8A, a substrate810is provided, and an epitaxial layer820of a first conductivity type is then formed on the substrate810. The epitaxial layer820is formed on the substrate810by an epitaxial process. In some embodiments of the present disclosure, the epitaxial layer820is a first conductivity type. In some embodiments of the present disclosure, the epitaxial layer820is formed an n-type epitaxial layer. In some embodiments of the present disclosure, the epitaxial layer820is doped by introducing dopants during the formation of the epitaxial layer820. In some embodiments of the present disclosure, the epitaxial layer820is doped after formation of the epitaxial layer820.

In some embodiments of the present disclosure, a bury layer of the first conductivity type is formed between the substrate810and the epitaxial layer820. In some embodiments of the present disclosure, the bury layer is formed an n-doped bury layer. In some embodiments of the present disclosure, the bury layer is formed of silicon, germanium, another suitable n-type semiconductor material or the combination thereof. In some embodiments of the present disclosure, the bury layer is formed to be acted as an interlayer to conduct from a top source electrode to a top drain. In some embodiments of the present disclosure, the bury layer is formed by a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, spin-on coating, another suitable formation process or a combination thereof.

Referring toFIG. 8B, ion implantation is performed to deposit dopants of a second conductivity type into the epitaxial layer820, so as to form a doped layer830of the second conductivity type in the epitaxial layer820. In some embodiments of the present disclosure, a vertical ion implantation process is performed on the epitaxial layer820. In some embodiments of the present disclosure, a tilt ion implantation process is performed on the epitaxial layer820. In some embodiments of the present disclosure, the doped layer830is a second conductivity type opposite to the first conductivity type. In some embodiments of the present disclosure, the ion implantation deposits p-type dopants into the epitaxial layer820. In some embodiments of the present disclosure, the p-type dopants include, but not limited to, boron, boron difluoride, another suitable p-type dopant, or a combination thereof.

As shown inFIG. 8C, a plurality of gate trenches840are formed in the doped layer830and the epitaxial layer820. In some embodiments of the present disclosure, a hard mask layer is formed over the doped layer830. In some embodiments of the present disclosure, a hard mask material is formed by a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, spin-on coating, or another suitable formation process, and then patterned by a photolithography/etching process, a laser drilling process or another suitable material removal process to form the hard mask layer. In some embodiments of the present disclosure, the hard mask layer includes silicon dioxide, silicon nitride or another suitable masking material. In some embodiments of the present disclosure, the hard mask layer exposes a portion of the doped layer830for forming the gate trenches840.

In some embodiments of the present disclosure, the exposed portion of the doped layer830is removed according to the hard mask layer to form the gate trenches840in the doped layer830and the epitaxial layer820. In some embodiments of the present disclosure, a part of the doped layer830and a part of the epitaxial layer820are removed by a dry etching process. In some embodiments of the present disclosure, the etchant includes carbon fluorides (CxFy), sulfur hexafluoride (SF6), oxygen gas (O2), helium (He), carbon chlorides (CxCly), argon (Ar), another suitable etchant material or a combination thereof. In some embodiments of the present disclosure, the gate trenches840are a straight walled trench or an angled trench. In the embodiment ofFIG. 8C, the gate trenches840are straight walled trenches.

Referring toFIG. 8D, ion implantation is performed to deposit dopants852of a second conductivity type into the gate trenches840, so as to form a plurality of pillars850in the epitaxial layer820and individually correspond to and under the gate trenches840. In some embodiments of the present disclosure, a vertical ion implantation process is performed into the gate trenches840. In some embodiments of the present disclosure, the pillars850are a second conductivity type. In some embodiments of the present disclosure, the ion implantation deposits p-type dopants into the gate trenches840, so as to form a p-doped pillar850. In some embodiments of the present disclosure, the p-type dopants include, but not limited to, boron, boron difluoride, another suitable p-type dopant, or a combination thereof.

In some embodiments of the present disclosure, the formation of the pillars850includes forming a trench filled with the second conductivity type material or forming a multilayer structure. In some embodiments of the present disclosure, the formation of the trench includes forming an angled trench, and then a second conductivity type material is filled in the trench by an epitaxial method. In some embodiments of the present disclosure, a pattern of the trench is formed the same as that of the gate trenches840.

In some embodiments ofFIG. 8D, each of the pillars850is formed a multilayer structure. In some embodiments of the present disclosure, the formation of the multilayer structure includes forming a multilayer of the second conductivity type by performing an ion implantation. In some embodiments of the present disclosure, each of the pillars850is formed a p-doped multilayer structure. In some embodiments of the present disclosure, the multilayer structure of the pillars850is fabricated by multi-epi and doping processes with masks.

After the dopants852are deposited, the hard mask layer is removed. In some embodiments of the present disclosure, the hard mask layer is removed by an etching process, a planarization process, another suitable material removal process or a combination thereof.

As shown inFIG. 8E, an insulating layer860is filled in the gate trenches840. In some embodiments of the present disclosure, the insulating layer860is omitted. In some embodiments of the present disclosure, the insulating layer860is formed after formation of another insulating layer. In some embodiments, the insulating layer860includes silicon dioxide, aerogel, another suitable insulating material or a combination thereof. In some embodiments of the present disclosure, the insulating layer860is blanket deposited by a CVD process, a PVD process, an atomic layer deposition (ALD) process, a spin-on process or another suitable formation process. In some embodiments of the present disclosure, the insulating layer860includes a conductive material such as polysilicon or another suitable conductive material. In some embodiments of the present disclosure, the insulating layer860includes a dielectric material, such as silicon dioxide, a silicon nitride or another suitable dielectric material. In some embodiments of the present disclosure, the insulating layer860includes an air gap. In some embodiments of the present disclosure, the formation of the insulating layer further includes forming an oxide layer on an inner surface of the gate trenches; and filling a polymer material in the gate trenches.

In some embodiments of the present disclosure, a planarization process is performed. In some embodiments of the present disclosure, the planarization process includes a chemical mechanical polishing (CMP) process, a grinding process, an etching process, another suitable material removal process or a combination thereof. In some embodiments of the present disclosure, the planarization process removes portions of the insulating layer860outside the gate trenches840. In some embodiments of the present disclosure, after the planarization process, a top surface of the insulating layer860and a top surface of the doped wells are coplanar.

FIG. 9is a flow chart illustrating a method for manufacturing a semiconductor device having a super junction structure, in accordance with some embodiments. The operations901to905are disclosed in association with the cross-sectional views of the integrated circuit structure800fromFIGS. 8A to 8Eat various fabrication stages.

In the operation901, the substrate810is provided, and the epitaxial layer820of a first conductivity type is then formed on the substrate810. The epitaxial layer820is formed on the substrate810by an epitaxial process. In some embodiments of the present disclosure, the epitaxial layer820is a first conductivity type. In some embodiments of the present disclosure, the epitaxial layer820is formed an n-type epitaxial layer. In some embodiments of the present disclosure, a bury layer of the first conductivity type is formed between the substrate810and the epitaxial layer820. In some embodiments of the present disclosure, the bury layer is formed an n-doped bury layer.

In the operation902, ion implantation is performed to deposit dopants of the second conductivity type into the epitaxial layer820, so as to form the doped layer830of the second conductivity type in the epitaxial layer820. In some embodiments of the present disclosure, the doped layer830is a second conductivity type opposite to the first conductivity type. In some embodiments of the present disclosure, the ion implantation deposits p-type dopants into the epitaxial layer820.

In the operation903, the gate trenches840are formed in the doped layer830and the epitaxial layer820. In some embodiments of the present disclosure, a hard mask layer is formed over the doped layer830. In some embodiments of the present disclosure, the hard mask layer exposes a portion of the doped layer830for forming the gate trenches840. In some embodiments of the present disclosure, the exposed portion of the doped layer830is removed according to the hard mask layer to form the gate trenches840in the doped layer830and the epitaxial layer820. In some embodiments of the present disclosure, a part of the doped layer830and a part of the epitaxial layer820are removed by a dry etching process. In the embodiment ofFIG. 8C, the gate trenches840are straight walled trenches.

In the operation904, ion implantation is performed to deposit dopants852of the second conductivity type into the gate trenches840, so as to form the pillars850in the epitaxial layer820and individually correspond to and under the gate trenches840. In some embodiments ofFIG. 8D, a vertical ion implantation process is performed into the gate trenches840. In some embodiments of the present disclosure, the pillars850are a second conductivity type. In some embodiments of the present disclosure, the ion implantation deposits p-type dopants into the gate trenches840, so as to form a p-doped pillar850.

In some embodiments of the present disclosure, the formation of the pillars850includes forming a trench filled with the second conductivity type material or forming a multilayer structure. In some embodiments of the present disclosure, the formation of the trench includes forming an angled trench, and then a second conductivity type material is filled in the trench by an epitaxial method. In some embodiments of the present disclosure, a pattern of the trench is formed the same as that of the gate trenches840.

In some embodiments ofFIG. 8D, each of the pillars850is formed a multilayer structure. In some embodiments of the present disclosure, the formation of the multilayer structure includes forming a multilayer of the second conductivity type by performing an ion implantation. In some embodiments of the present disclosure, each of the pillars850is formed a p-doped multilayer structure. In some embodiments of the present disclosure, the multilayer structure of the pillars850is fabricated by multi-epi and doping processes with masks. In some embodiments of the present disclosure, after the dopants852are deposited, the hard mask layer is removed.

In the operation905, an insulating layer860is filled in the gate trenches840. In some embodiments of the present disclosure, the insulating layer860is blanket deposited by a CVD process, a PVD process, an atomic layer deposition (ALD) process, a spin-on process or another suitable formation process. In some embodiments of the present disclosure, the formation of the insulating layer further includes forming an oxide layer on an inner surface of the gate trenches; and filling a polymer material in the gate trenches.

In some embodiments of the present disclosure, a planarization process is performed. In some embodiments of the present disclosure, the planarization process includes a chemical mechanical polishing (CMP) process, a grinding process, an etching process, another suitable material removal process or a combination thereof. In some embodiments of the present disclosure, the planarization process removes portions of the insulating layer860outside the gate trenches840. In some embodiments of the present disclosure, after the planarization process, a top surface of the insulating layer860and a top surface of the doped wells are coplanar.

FIG. 10is a cross-sectional view of a semiconductor device1000having a super junction structure, in accordance with some embodiments. InFIG. 10, the semiconductor device1000having a super junction structure includes a substrate1010, an epitaxial layer1020, a plurality of pillars1030, a plurality of gate trenches1040, an insulating layer1050, a plurality of doped wells1060, a bury layer1070and a doped column1080.

InFIG. 10, the semiconductor device1000having a super junction structure further includes a cell region1001and a terminal region1002adjacent to the cell region1001. In some embodiments ofFIG. 10, the pillars1030, the gate trenches1040, the insulating layer1050and the doped wells1060are positioned in the cell region1001; and the doped column1080is positioned in the terminal region1002.

In some embodiments of the present disclosure, the substrate1010is a doped substrate of the second conductivity type. In some embodiments of the present disclosure, the substrate1010is a p-doped substrate. In some embodiments of the present disclosure, the substrate1010includes p-type dopants and thus can be acted as a p-type base. In some embodiments of the present disclosure, the p-type dopants in the substrate1010include boron, boron difluoride, another suitable p-type dopant or a combination thereof. The epitaxial layer1020of a first conductivity type is on the substrate1010. In some embodiments of the present disclosure, the epitaxial layer1020is an n-epi layer.

The bury layer1070of the first conductivity type is between the substrate1010and epitaxial layer1020. In some embodiments of the present disclosure, the bury layer1070is an n-doped bury layer. In some embodiments of the present disclosure, the bury layer1070includes silicon, germanium, another suitable n-type semiconductor material or the combination thereof.

The pillars1030of a second conductivity type are in the epitaxial layer1020. In some embodiments of the present disclosure, the second conductivity type is opposite to the first conductivity type. In some embodiments of the present disclosure, the pillars1030are p-doped pillars. In some embodiments of the present disclosure, the pillars1030include p-type dopants and thus can be acted as a p-type column. In some embodiments of the present disclosure, each of the pillars1030is a multilayer structure. In some embodiments of the present disclosure, the multilayer structure is a multilayer of the second conductivity type. In some embodiments of the present disclosure, each of the pillars1030is a p-doped multilayer structure.

The gate trenches1040are individually correspond to and over the pillars1030, and the insulating layer1050is in the gate trenches340. In some embodiments of the present disclosure, the pillars1030are individually in contact with the insulating layer1050in the gate trenches1040.

In some embodiments ofFIG. 10, the insulating layer1050includes an oxide layer1054disposed on an inner surface of the gate trenches1040; and a polymer material1052disposed on the oxide layer1054and in the gate trenches1040. In some embodiments of the present disclosure, the insulating layer1050can be acted as a gate insulating layer and in contact with a gate electrode1051. In some embodiments of the present disclosure, the semiconductor device1000further includes another insulating layer between the insulating layer1050and an inner surface of the gate trenches1040.

The doped wells1060are in the epitaxial layer1020. In some embodiments of the present disclosure, each of the doped wells1060is between two adjacent gate trenches1040. In some embodiments ofFIG. 10, each of the doped wells1060includes a p-doped well1062, a heavily p-doped well1068and two heavily n-doped wells1064and1066. In some embodiments of the present disclosure, the heavily n-doped wells1064and1066are disposed on the p-doped well1062, and are not in contact with each other. In some embodiments of the present disclosure, the heavily p-doped well1068is disposed on the p-doped well1062and sandwiched between the heavily n-doped wells1064and1066. In some embodiments of the present disclosure, a source electrode1061is sandwiched between the heavily n-doped wells1064and1066and in contact with the heavily p-doped well1068.

The doped column1080is in the epitaxial layer1020and in contact with the bury layer1070. In some embodiments of the present disclosure, the doped column1080is the first conductivity type. In some embodiments of the present disclosure, the doped column1080is an n-doped bury layer. In some embodiments of the present disclosure, the doped column1080includes silicon, germanium, another suitable n-type semiconductor material or the combination thereof. In some embodiments of the present disclosure, the bury layer1070and the doped column1080are formed to act as an interlayer to conduct from the top source electrode1061to a top drain1081. In some embodiments of the present disclosure, the top drain1081is in contact with a top surface of the doped column1080. In some embodiments of the present disclosure, a heavily n-doped well1082is further sandwiched between the top drain1081and the doped column1080.

FIGS. 11A-11Gare cross-sectional views at various stages of fabricating a super junction structure1100, in accordance with some embodiments.

As shown inFIG. 11A, a plurality of trenches1120are formed in a substrate1110aof a first conductivity type. In some embodiments of the present disclosure, the substrate1110ais an n-doped substrate. In some embodiments of the present disclosure, the n-type dopant includes, but not limited to, arsenic, phosphorous, another suitable n-type dopant or a combination thereof. In some embodiments of the present disclosure, the substrate1110ais a heavily doped substrate. In some embodiments of the present disclosure, the substrate1110ais acted as a drain electrode. In some embodiments of the present disclosure, the substrate1110aincludes, but not limited to, an elementary semiconductor including silicon or germanium in crystal, polycrystalline or an amorphous structure; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide or a combination thereof; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP or a combination thereof; any other suitable material or combinations thereof.

In some embodiments of the present disclosure, a hard mask layer is formed over the substrate1110a. In some embodiments of the present disclosure, a hard mask material is formed by a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, spin-on coating, or another suitable formation process, and then patterned by a photolithography/etching process, a laser drilling process or another suitable material removal process to form the hard mask layer. In some embodiments of the present disclosure, the hard mask layer includes silicon dioxide, silicon nitride or another suitable masking material. In some embodiments of the present disclosure, the hard mask layer exposes a portion of the substrate1110afor forming the trenches1120.

In some embodiments of the present disclosure, the exposed portion of the substrate1110ais removed according to the hard mask layer to form the trenches1120in the substrate1110a. In some embodiments of the present disclosure, a part of the substrate1110ais removed by a dry etching process. In some embodiments of the present disclosure, the etchant includes carbon fluorides (CxFy), sulfur hexafluoride (SF6), oxygen gas (O2), helium (He), carbon chlorides (CxCly), argon (Ar), another suitable etchant material or a combination thereof. In some embodiments ofFIG. 11A, the trenches1120are formed angled trenches.

As shown inFIG. 11B, the trenches1120are formed in an epitaxial layer1112of the first conductivity type, wherein the epitaxial layer1112is deposited on the substrate1110a. In some embodiments of the present disclosure, the epitaxial layer1112is an n-doped epitaxial (n-epi) layer. In some embodiments of the present disclosure, the epitaxial layer1112includes silicon, germanium, another suitable n-type semiconductor material or the combination thereof.

In some embodiments of the present disclosure, a hard mask layer is formed over the epitaxial layer1112. In some embodiments of the present disclosure, a hard mask material is formed by a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, spin-on coating, or another suitable formation process, and then patterned by a photolithography/etching process, a laser drilling process or another suitable material removal process to form the hard mask layer. In some embodiments of the present disclosure, the hard mask layer includes silicon dioxide, silicon nitride or another suitable masking material. In some embodiments of the present disclosure, the hard mask layer exposes a portion of the epitaxial layer1112for forming the trenches1120.

In some embodiments of the present disclosure, the exposed portion of the epitaxial layer1112is removed according to the hard mask layer to form the trenches1120in the epitaxial layer1112. In some embodiments of the present disclosure, a part of the substrate1110ais removed by a dry etching process. In some embodiments of the present disclosure, the etchant includes carbon fluorides (CxFy), sulfur hexafluoride (SF6), oxygen gas (O2), helium (He), carbon chlorides (CxCly), argon (Ar), another suitable etchant material or a combination thereof. In some embodiments ofFIG. 11B, the trenches1120are formed angled trenches.

As shown inFIG. 11C, the trenches1120are formed in an epitaxial layer1112of the first conductivity type, wherein the epitaxial layer1112is deposited on the substrate1110b. In some embodiments of the present disclosure, the substrate1110bis a second conductivity type opposite to the first conductivity type. In some embodiments of the present disclosure, the substrate1110bis a doped substrate of the second conductivity type. In some embodiments of the present disclosure, the substrate1110bis a p-doped substrate. In some embodiments of the present disclosure, the substrate1110bincludes p-type dopants and thus can be acted as a p-type base. In some embodiments of the present disclosure, the p-type dopants in the substrate1110binclude boron, boron difluoride, another suitable p-type dopant or a combination thereof. The epitaxial layer1112of a first conductivity type is on the substrate1110b. In some embodiments of the present disclosure, the epitaxial layer1112is an n-epi layer.

In some embodiments ofFIG. 11C, a bury layer1114of the first conductivity type is sandwiched between the epitaxial layer1112and the substrate1110b. In some embodiments of the present disclosure, the bury layer1114is an n-doped bury layer. In some embodiments of the present disclosure, the bury layer1114includes silicon, germanium, another suitable n-type semiconductor material or the combination thereof. In some embodiments of the present disclosure, the bury layer1114is acted as an interlayer to conduct from a top source electrode to a top drain.

Referring toFIGS. 11D and 11E, ion implantation is performed to deposit dopants1132of the second conductivity type into the trenches1120, so as to form a doped region1130of the second conductivity type in the substrate1110aand surrounding the trenches1120. In some embodiments of the present disclosure, a tilt and vertical ion implantation process is performed into the trenches1120. In some embodiments of the present disclosure, the ion implantation deposits p-type dopants1132into the trenches1120, so as to form a p-doped region1130in the substrate1110aand surrounding the trenches1120. In some embodiments of the present disclosure, the p-type dopants1132include, but not limited to, boron, boron difluoride, another suitable p-type dopant, or a combination thereof.

Referring toFIG. 11F, an undoped material1140is filled in the trenches1120. In some embodiments, filling the undoped material1140in the trenches1120includes depositing an undoped polymer material in the trenches1120. In some embodiments, the undoped material1140includes a conductive material such as polysilicon, another suitable conductive material or a combination thereof. In some embodiments of the present disclosure, the undoped material1140is blanket deposited by a CVD process, a PVD process, an atomic layer deposition (ALD) process, a spin-on process or another suitable formation process.

In some embodiments of the present disclosure, a planarization process is performed. In some embodiments of the present disclosure, the planarization process removes portions of the undoped material1140outside the trenches1120. In some embodiments of the present disclosure, after the planarization process, a top surface of the undoped material1140and a top surface of the substrate1110aare coplanar. In some embodiments of the present disclosure, the planarization process includes a chemical mechanical polishing (CMP) process, a grinding process, an etching process, another suitable material removal process or a combination thereof.

Referring toFIG. 11G, a pillar1150of the second conductivity type is formed from the undoped material1140in the trenches1120. In some embodiments of the present disclosure, the formation of the pillar1150includes performing a thermal diffusion process to diffuse the doped region1130of the second conductivity type surrounding the trenches1120into the undoped material1140in the trenches1120, so as to form the pillar1150of the second conductivity type. In some embodiments of the present disclosure, the thermal process diffuses the p-type dopants1132from the doped region1130into the undoped material1140in the trenches1120, so as to form the p-doped pillar1150in the substrate1110a. In some embodiments of the present disclosure, the pillar1150of the second conductivity type is formed under a gate trench or a doped well of a second conductivity type.

FIG. 12is a flow chart illustrating a method for manufacturing a super junction structure, in accordance with some embodiments. The operations1201to1204are disclosed in association with the cross-sectional views of the integrated circuit structure1100fromFIGS. 11A, 11D to 11Gat various fabrication stages.

In the operation1201, the trenches1120are formed in the substrate1110aof the first conductivity type. In some embodiments of the present disclosure, the substrate1110ais an n-doped substrate. In some embodiments of the present disclosure, a hard mask layer is formed over the substrate1110a. In some embodiments of the present disclosure, the hard mask layer exposes a portion of the substrate1110afor forming the trenches1120. In some embodiments of the present disclosure, the exposed portion of the substrate1110ais removed according to the hard mask layer to form the trenches1120in the substrate1110a. In some embodiments of the present disclosure, a part of the substrate1110ais removed by a dry etching process. Referring toFIG. 11A, the trenches1120are formed angled trenches.

In the operation1202, the doped region1130of the second conductivity type is formed in the substrate1110aand surrounding the trenches1120. Referring toFIG. 11D, ion implantation is performed to deposit dopants1132of the second conductivity type into the trenches1120. Referring toFIG. 11E, the doped region1130is formed in the substrate1110aand surrounding the trenches1120. In some embodiments of the present disclosure, a tilt and vertical ion implantation process is performed into the trenches1120. In some embodiments of the present disclosure, the ion implantation deposits p-type dopants1132into the trenches1120, so as to form a p-doped region1130in the substrate1110aand surrounding the trenches1120.

In the operation1203, the undoped material1140is filled in the trenches1120. In some embodiments, filling the undoped material1140in the trenches1120includes depositing an undoped polymer material in the trenches1120. In some embodiments of the present disclosure, the undoped material1140is blanket deposited by a CVD process, a PVD process, an atomic layer deposition (ALD) process, a spin-on process or another suitable formation process.

In some embodiments of the present disclosure, a planarization process is performed. In some embodiments of the present disclosure, the planarization process removes portions of the undoped material1140outside the trenches1120. In some embodiments of the present disclosure, after the planarization process, a top surface of the undoped material1140and a top surface of the substrate1110aare coplanar.

In the operation1204, the pillar1150of the second conductivity type is formed from the undoped material1140in the trenches1120. In some embodiments of the present disclosure, the formation of the pillar1150includes performing a thermal diffusion process to diffuse the doped region1130of the second conductivity type surrounding the trenches1120into the undoped material1140in the trenches1120, so as to form the pillar1150of the second conductivity type. In some embodiments of the present disclosure, the thermal process diffuses the p-type dopants1132from the doped region1130into the undoped material1140in the trenches1120, so as to form the p-doped pillar1150in the substrate1110a. In some embodiments of the present disclosure, the pillar1150of the second conductivity type is formed under a gate trench or a doped well of a second conductivity type.

According to some embodiments of the present disclosure, a semiconductor device having a super junction structure includes a substrate, an epitaxial layer of a first conductivity type, a plurality of pillars of a second conductivity type, a plurality of gate trenches, an insulating layer and a plurality of doped wells of the second conductivity type. The epitaxial layer of the first conductivity type is on the substrate. The pillars of the second conductivity type are in the epitaxial layer, in which the second conductivity type is opposite to the first conductivity type. The gate trenches are individually corresponding to and over the pillars. The insulating layer is in the gate trenches. The doped wells of the second conductivity type are in the epitaxial layer, in which each of the doped wells is between two adjacent gate trenches.

According to some embodiments of the present disclosure, a method for manufacturing a semiconductor device having a super junction structure includes: forming an epitaxial layer on a substrate, in which the epitaxial layer is a first conductivity type; forming a doped layer in the epitaxial layer, in which the doped layer is a second conductivity type opposite to the first conductivity type; forming a plurality of gate trenches in the doped layer and the epitaxial layer; forming a plurality of pillars in the epitaxial layer and individually correspond to and under the gate trenches; and filling an insulating material in the gate trenches.

According to some embodiments of the present disclosure, a method for manufacturing a super junction structure includes: forming a plurality of trenches in a substrate of a first conductivity type; forming a doped region of a second conductivity type in the substrate and surrounding the trenches, in which the second conductivity type is opposite to the first conductivity type; filling an undoped material in the trenches; and forming a pillar of the second conductivity type from the undoped material in the trenches.

An aspect of this description relates to a method of manufacturing a super junction structure. The method includes etching a material to define a trench, wherein the trench has a tapered profile. The method further includes implanting dopants into sidewalls and a bottom surface of the trench to define a doped region, wherein the doped region surrounds the trench. The method further includes depositing an undoped material into the trench. The method further includes performing a thermal process, wherein the thermal process drives the dopants from the doped region into the undoped material to form a conductive pillar in the trench. In some embodiments, implanting the dopants includes performing a vertical ion implantation and a tilt ion implantation. In some embodiments, depositing the undoped material includes implanting an undoped polymer. In some embodiments, depositing the undoped material includes filling the trench with the undoped material. In some embodiments, the method further includes performing a planarization process to remove the undoped material outside of the trench. In some embodiments, performing the thermal process includes forming a rounded bottom surface of the conductive pillar. In some embodiments, etching the material includes etching a substrate having a first conductivity type, and performing the thermal process includes forming the conductive pillar having a second conductivity type opposite the first conductivity type. In some embodiments, etching the material includes etching an epitaxial layer over a substrate, the epitaxial layer has a first conductivity type, and performing the thermal process includes forming the conductive pillar having a second conductivity type opposite the first conductivity type. In some embodiments, the method further includes forming the epitaxial layer over the substrate. In some embodiments, the method further includes forming a bury layer between the epitaxial layer and the substrate, wherein the bury layer has the first conductivity type, and the substrate has the second conductivity type.

An aspect of this description relates to a method of manufacturing a super junction structure. The method includes forming an epitaxial layer over a substrate, wherein the epitaxial layer has a first conductivity type. The method further includes etching the epitaxial layer to define a trench, wherein sidewalls of the trench are angled with respect to a top-most surface of the epitaxial layer, and a bottom surface of the trench is parallel to the top-most surface of the epitaxial layer. The method further includes implanting dopants into the sidewalls and the bottom surface of the trench to define a doped region, wherein a top surface of the doped region is coplanar with the top-most surface of the epitaxial layer, and the dopants are a second conductivity type opposite the first conductivity type. The method further includes filling the trench with an undoped material. The method further includes driving the dopants from the doped region into the undoped material to form a conductive pillar filling the trench. In some embodiments, driving the dopants from the doped region into the undoped material includes performing a thermal process. In some embodiments, performing the thermal process includes forming a rounded bottom surface of the conductive pillar. In some embodiments, the method further includes forming a bury layer between the substrate and the epitaxial layer, wherein the bury layer has the first conductivity type. In some embodiments, the method further includes electrically connecting the bury layer to a top source/drain electrode. In some embodiments, implanting the dopants includes performing a vertical ion implantation; and performing a tilt ion implantation. In some embodiments, the method further includes forming a gate trench over the conductive pillar. In some embodiments, etching the epitaxial layer includes performing a dry etching process. In some embodiments, forming the epitaxial layer includes forming the epitaxial layer over the substrate, wherein the substrate has the second conductivity type.

An aspect of this description relates to a super junction structure. The super junction structure includes a substrate, wherein the substrate has a first conductivity type. The super junction structure includes an epitaxial layer over the substrate, wherein the epitaxial layer has a second conductivity type opposite the first conductivity type. The super junction structure further includes a bury layer between the epitaxial layer and the substrate, wherein the bury layer has the second conductivity type. The super junction structure further includes a conductive pillar in the epitaxial layer, wherein the conductive pillar has the first conductivity type, sidewalls of the conductive pillar are angled with respect to a top-most surface of the epitaxial layer, a bottom surface of the conductive pillar is rounded, and a top-most surface of the conductive pillar is coplanar with the top-most surface of the epitaxial layer.