Protection circuit for digital integrated chip

A protection circuit includes first and second electronic switches. When a CPU socket does not contain a CPU, a signal pin of the CPU socket outputs a high level signal. The first and second electronic switches are turned on. A data transmitting line of a SMBus is connected to a digital integrated chip. The parameters of the digital integrated chip can thus be regulated. When the CPU socket contains the CPU, the signal pin of the CPU socket outputs a low level signal. The first and second electronic switches are turned off. The data transmitting line of the SMBus is disconnected from the digital integrated chip, to prevent damage to the digital integrated chip.

BACKGROUND

1. Technical Field

The present disclosure relates to a circuit for protecting a digital integrated chip.

2. Description of Related Art

When testing a motherboard, a digital integrated chip arranged on the motherboard is used for controlling the operation of many elements, such as a memory of the motherboard. However, the working parameters of the digital integrated chip should be regulated when a central processing unit (CPU) is not mounted in a CPU socket, otherwise, the digital integrated chip may be damaged.

DETAILED DESCRIPTION

The disclosure, including the drawing, is illustrated by way of example and not by way of limitation. References to “an” or “one” embodiment in this disclosure are not necessarily to the same embodiment, and such references mean at least one.

Referring to the FIGURE, a protection circuit1is connected between a central processing unit (CPU) socket10and a digital integrated chip20, to prevent the digital integrated chip20from being damaged. The protection circuit1in accordance with an exemplary embodiment includes a first electronic switch, such as an n-channel field effect transistor (FET) Q2, a second electronic switch, such as a p-channel FET Q1, and resistors R1-R4. A gate of the FET Q2is connected to a signal pin SKTOCC of the CPU socket10, and also connected to a power source P3V3through the resistor R1. The resistor R2is connected between the gate of the FET Q2and ground. A source of the FET Q2is grounded. A drain of the FET Q2is connected to a power source P5V_SB through the resistor R3and also connected to a gate of the FET Q1through the resistor R4. A drain of the FET Q1is connected to the digital integrated chip20. A source of the FET Q1is connected to a data transmitting line SMBDAT of a system management bus (SMBus)3. In other embodiments, Q1may be an npn transistor, and Q2may be a pnp transistor. The digital integrated chip20is a digital pulse width modulation integrated chip.

In use, when the CPU socket10does not contain a CPU2, the signal pin SKTOCC of the CPU socket10outputs a high level signal to the FET Q2. The FET Q2is turned on. The source of the FET Q2is at a low level. The FET Q1is turned on. The data transmitting line SMBDAT is connected to the digital integrated chip20. Thus, the working parameters of the digital integrated chip20such as voltage can be regulated through the data transmitting line SMBDAT of the SMBus3.

When the CPU socket10contains the CPU2, the signal pin SKTOCC of the CPU socket10outputs a low level signal. The FET Q2is turned off. The gate of the FET Q1receives a high level signal and is turned off. The data transmitting line SMBDAT is disconnected from the digital integrated chip20. Thus, the parameters of the digital integrated chip20cannot be regulated through the data transmitting line SMBDAT of the SMBus3, and any damage to the digital integrated chip20is prevented.

The protection circuit1can control the parameters of the digital integrated chip20to be regulated according to the high or low level signals of the signal pin SKTOCC of the CPU socket10, to prevent the digital integrated chip20from being damaged.