Semiconductor device

A semiconductor device comprises: a pad group including a plurality of pads provided on a semiconductor substrate and arranged in a row to form a pad row as a whole. The pad group includes: at least one first pad provided with a first via-connection part electrically connected therewith and extended in a first direction perpendicular to a row direction of the pad row; and at least one second pad provided with a second via-connection part electrically connected therewith and extended in a second direction opposite to the first direction. The at least one second pad is formed at a position moved in the first direction from the row direction of the pad row passing through a center of the at least one first pad.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device and, in particular, to a pad layout in a semiconductor device.

2. Background Art

Semiconductor devices, such as semiconductor integrated circuits, have incorporated increasingly complicated circuit blocks along with increases in their functionality and scale. Moreover, a greater number of pads have been provided as a connection interface with an external device in such a semiconductor device. Therefore, to reduce the size of such a semiconductor device, it is necessary not only to form a finer circuit block but also to create device design including a pad layout and wiring from the pads to the circuit block.

For example, Japanese Patent Application Laid-Open No. 2004-179184 discloses a semiconductor integrated circuit including: an internal cell region formed in a central part of a substrate; a plurality of input and output cells formed around the internal cell region and arranged in a plurality of rows; and a plurality of pads formed in a peripheral portion of the substrate, in which input and output cells constituting a relatively-inner input and output cell row are connected to the pads via wiring formed above input and output cells constituting a relatively-outer input and output cell row.

Japanese Patent Application Laid-Open No. 2012-235048 discloses a semiconductor device including: a plurality of first buffer cells provided in a row along one side of a substrate; a plurality of second buffer cells provided in a row along the arrangement direction of the plurality of first buffer cells at positions closer to a center of the substrate than the plurality of first buffer cells; a plurality of first pads provided in a row above the plurality of first buffer cells; and a plurality of second pads provided in a row at positions closer to the center of the substrate than the plurality of first buffer cells, in which the plurality of second pads include: a plurality of third pads each individually connected to any one of the plurality of first buffer cells; and a plurality of fourth pads each individually connected to any one of the plurality of second buffer cells.

SUMMARY OF THE INVENTION

Semiconductor devices each typically include a multilayered wiring layer. Pads and wiring from the pads to a circuit block are provided in this multilayered wiring layer. When a semiconductor device is manufactured by providing a multilayered wiring layer on a substrate and a circuit structure layer in which a circuit block is formed, for example, pads are formed on a surface of the multilayered wiring layer. Moreover, the pads are connected to the circuit block by means of metal wiring provided in the multilayered wiring layer. A plurality of through holes are provided in the multilayered wiring layer, and the metal wiring is connected to other wiring layers via the through holes.

On the other hand, a bonding wire is formed on the pad. Thus, at the time of wire bonding to the pad, a head of a bonding apparatus is brought into contact with the pad. Also, before the wire bonding, a probe is brought into contact with the pad when the function of the device is tested. Since physical force is applied on the pad at the time of manufacturing as described above, it is preferable that no through hole directly connected to an internal circuit be formed immediately below the pad.

Moreover, in order to perform the above-described wire bonding and probing test, no passivation film is provided on the pad at least at the time of manufacturing. Thus, if a through hole directly connected to the internal circuit is provided immediately below the pad, the above-described physical force may deform the through hole and a foreign substance such as water may enter the through hole at the time of manufacturing. Due to such quality reasons, a pad is provided with a part extended from its pad region, the extended part is protected by a passivation film, and a through hole is provided under the extended part.

To achieve reduction in device size, it is desirable to study a layout, including not only the size, shape, and arrangement of the pads but also the extended parts.

The present invention has been made in view of the above and it is an object of the present invention to provide a semiconductor device having an optimized layout for pads and extended parts and thus capable of achieving reduction in device size.

A semiconductor device according to the present invention includes a pad group including a plurality of pads provided on a semiconductor substrate and arranged in a row to form a pad row as a whole. The pad group includes: at least one first pad provided with a first via-connection part electrically connected therewith and extended in a first direction perpendicular to a row direction of the pad row; and at least one second pad provided with a second via-connection part electrically connected therewith and extended in a second direction opposite to the first direction. The at least one second pad is formed at a position moved in the first direction from the row direction of the pad row passing through a center of the at least one first pad.

A semiconductor device according to an embodiment of the present invention allows the layout of a pad region, including pads and extended parts, to be optimized, allows a principal surface of a wiring layer to be effectively utilized without wasted space, and allows wiring efficiency to be optimized. Thus, reduction in device size can be achieved.

DETAILED DESCRIPTION OF THE INVENTION

An embodiment of the present invention will now be described below in detail.

First Embodiment

FIG. 1Ais a schematic diagram illustrating an upper surface of a semiconductor device10according to the first embodiment. The semiconductor device10has a configuration in which a circuit block CB is formed in a semiconductor substrate (hereinafter referred to simply as a substrate)11. The circuit block CB is formed in the center of the substrate11as seen from a direction perpendicular to the substrate11, i.e., as seen from the top. The present embodiment describes a case where the substrate11and the circuit block CB each have a rectangular shape as seen from the top.

The semiconductor device10includes a pad group12constituted by a plurality of pads. Each of the plurality of pads is provided with a connection part (via-connection part) CN extended from the pad and connected to wiring to the circuit block CB. The connection parts CN constitute extended parts of the pads. The plurality of pads are arranged in a row and form, together with the connection parts CN, a pad row PL as a whole. The connection parts CN are formed extending from the pads along a direction perpendicular to a longitudinal direction (row direction) of the pad row PL (i.e., a short direction).

Note that the present embodiment describes a case where the pad group12is formed in the outside of the circuit block CB as seen from the top. Moreover, the present embodiment describes a case where two pad rows PL are formed along two opposed sides of the substrate11. Moreover, the present embodiment describes a case where the pad group12is formed along a peripheral portion of the circuit block CB. Moreover, the present embodiment describes a case where the pads in the pad group12each have a rectangular shape and the same length in the short direction of the pad row PL and the connection parts CN each have a rectangular shape and the same length in the short direction of the pad row PL.

In the present embodiment, among the pads in the pad group12, a pad having the connection part CN formed on the side of a peripheral portion of the substrate11is referred to as a pad12A (first pad). Similarly, a pad having the connection part CN formed on the side of the circuit block CB (on the side opposite to the pad12A) is referred to as a pad12B (second pad). The pad group12includes at least one first pad12A and at least one second pad12B.

The semiconductor device10includes a surface wire13provided adjacent to a longer side of the pad group12. A plurality of surface wires13are formed so as to sandwich each pad row PL in a wiring layer having the same hierarchical level as the pad group12and the connection parts CN. A power-supply potential, for example, is inputted to the surface wire13.

FIG. 1Bis a partial enlarged view illustrating a portion BLP defined by a broken line inFIG. 1Ain an enlarged manner. The pad group12is formed in a region (referred to as an inter-wire region) interposed between a pair of surface wires (first and second surface wires13A and13B). The first pad12A is provided with a connection part (first via-connection part) CN1electrically connected to the Pad12A and extended from the pad12A perpendicularly to the row direction of the pad row PL and toward an outer side of the substrate11(in a first direction DR1). Also, the second pad12B is provided with a connection part (second via-connection part) CN2electrically connected to the Pad12B and extended from the pad12B perpendicularly to the row direction of the pad row PL and toward an inner side of the substrate11(in a direction opposite to the first direction (in a second direction DR2)). The first and second connection parts CN1and CN2are connected to the circuit block CB provided in the substrate11.

As shown inFIG. 1B, the pad12B is formed at a position moved in the first direction DR1from the row direction of the pad row PL passing through the center of the pad12A by a length of the connection part CN1along the first direction DR1. More specifically, the pad12A has a center point CP1, which is the center of a region of the pad12A. Similarly, the pad12B has a center point CP2. The pads12A and12B each have a pad length L1, which is the length along the direction perpendicular to the row direction of the pad row PL. The connection parts CN1and CN2each have a connection part length L2, which is the length along the direction perpendicular to the row direction of the pad row PL.

As seen from the direction perpendicular to the substrate11, the center point CP2of the pad12B is located at a position shifted in the first direction DR1by a distance DT1from a central axis CA formed by connecting the center points CP1of the pads12A. In the present embodiment, the distance DT1equals the connection part length L2of the connection part CN1in the adjacent pad12A. In other words, the pad12B is arranged at a position moved in the first direction DR1, which is opposite to the second direction DR2, from the central axis CA by the connection part length L2of the connection part CN1in the adjacent pad12A. The connection part length L2is smaller than the pad length L1.

In this manner, the pads12A and12B are not arranged strictly in a straight line. However, the pads12A and12B and the connection parts CN1and CN2as a whole are arranged in a substantially straight line. Thus, a width PLW of the pad row PL constituted by the pads12A and12B and the connection parts CN1and CN2, i.e., the distance of the pad row PL along the direction perpendicular to the longitudinal direction thereof is minimized. Specifically, the width PLW of the region of the pad row PL equals (the pad length L1)+(the connection part length L2). Moreover, the region of the pad row PL has a substantially rectangular shape with no protrusions and depressions as seen from the top. This allows the formation of simple wires, e.g., the linear formation of the surface wires13adjacent to the pad group12, thus facilitating the wire formation.

If only the pads12A and12B are arranged in a straight line, an effective width of the region of the pad row PL equals (the pad length L1)+(the connection part length L2)+(the connection part length L2), thus substantially increasing the width of the region of the pad row PL. More specifically, a portion of the pad group12where the pad12A is formed has a protrusion in the first direction DR1and a portion thereof where the pad12B is formed has a protrusion in the second direction DR2in the region of the pad row PL. When the surface wires13are formed around such a pad row PL, the surface wires are bent along the protrusions, thus complicating the wire formation.

Note that the shift distance DT1of the pad12B is smaller than the pad length L1in the present embodiment. In other words, the pad12B is provided at a position moved from the central axis CA in the short direction of the pad row PL within a range not exceeding the pad length L1. Thus, as compared to when the pads12A and12B are formed strictly in a straight line, the positions of the pads12A and12B are not greatly changed. Therefore, when a probe card is manufactured so as to correspond to the positions of the pads, the needle assembling of the probe card is not limited to any type because of the small displacement between the pads in the present embodiment. Thus, there is a possibility of being able to employ, as a probe card for the semiconductor device10of the present embodiment, a probe card for testing the function of a semiconductor device in which the pads12A and12B are arranged in a straight line, for example.

FIG. 2Ais a cross-sectional view taken along line V-V inFIG. 1A.FIG. 2Bis a cross-sectional view taken along line W-W inFIG. 1A. First, the configuration of the semiconductor device10will be described with reference toFIG. 2A. Note that the present embodiment describes a case where the semiconductor device10is a semiconductor memory such as a DRAM. First, a circuit structure layer CSL is formed on the substrate11. The circuit block CB is formed in the substrate11and in the circuit structure layer CSL. The circuit block CB includes a transistor and a capacitor, for example. The circuit block CB is constituted by a memory cell array and a control circuit for controlling a storing operation of the memory cell array.

A multilayered wiring layer MWL, constituted by a plurality of metal wiring layers, is formed on the circuit structure layer CSL. The present embodiment describes a case where the multilayered wiring layer MWL has a configuration in which three metal wiring layers, i.e., a first metal wiring layer M1, a second metal wiring layer M2, and a third metal wiring layer M3, are formed on the circuit structure layer CSL. Specifically, the multilayered wiring layer MWL has a configuration in which a first insulating layer ISL1, the first metal wiring layer M1, a second insulating layer ISL2, the second metal wiring layer M2, a third insulating layer ISL3, and the third metal wiring layer M3are sequentially layered in this order on the circuit structure layer CSL. Although not shown in the figure, the third metal wiring layer M3is covered by a passivation film except for regions on the pads.

An example of connection between the first pad12A in the pad group12and the circuit block CB will be described with reference toFIG. 2A. Note thatFIG. 2A or 2Bonly shows connection between one pad12A or12B and the circuit block CB and connection wiring for other pads12A and12B is omitted.

The first pad12A is connected to a first wiring group (first wiring to the circuit block CB) W1in the multilayered wiring layer MWL by means of the connection part CN1thereof. The first pad12A is connected to an electro static discharge (ESD) protection circuit (hereinafter referred to simply as a protection circuit) EPC for protecting the circuit block CB against ESD via the first wiring group W1. The protection circuit EPC includes a diode element, for example. Moreover, the protection circuit EPC is connected to a second wiring group (second wiring to the circuit block CB) W2in the multilayered wiring layer MWL and connected to the circuit block CB via the second wiring group W2. In other words, the pad12A is connected to the circuit block CB via the protection circuit EPC.

Specifically, the pad12A is formed in the third metal wiring layer M3, and the connection part CN1extends from the pad12A in the third metal wiring layer M3. A through hole, which passes through the third insulating layer ISL3and reaches the second metal wiring layer M2, is formed immediately below the connection part CN1. A wire W11is formed in this through hole. In the second metal wiring layer M2, a wire W12, which extends from the wire W11toward the outer side of the substrate11to reach a region above the protection circuit EPC, is formed.

A through hole, which extends from a surface of the wire W12closer to the circuit structure layer CSL, passes through the second insulating layer ISL2, and reaches the first metal wiring layer M1, is formed. A wire W13is formed in this through hole. In the first metal wiring layer M1, a wire W14connected to the wire W13is formed. A through hole, which extends from a surface of the wire W14closer to the substrate11, passes through the first insulating layer ISL1, and reaches the protection circuit EPC in the circuit structure layer CSL, is formed. A wire W15is formed in this through hole. In this manner, the pad12A is connected to the protection circuit EPC via the first wiring group W1.

Next, in the circuit structure layer CSL on the protection circuit EPC where no wire W15is formed, a through hole, which passes through the circuit structure layer CSL and the first insulating layer ISL1and reaches the first metal wiring layer M1, is formed. A wire W21is formed in this through hole. In the first metal wiring layer M1, a wire W22, which extends from the wire W21to reach a region above the circuit block CB, is formed. A through hole, which passes through the first insulating layer ISL1and reaches the circuit block CB in the circuit structure layer CSL, is formed on a surface of the wire W22closer to the circuit structure layer CSL. A wire W23is formed in this through hole. In this manner, the protection circuit EPC is connected to the circuit block CB via the second wiring group W2.

InFIG. 2A, the second wiring group W2is illustrated so as to be formed in a region below the pad12A for ease of comprehension. However, it is desirable that the second wiring group W2be formed so as to circumvent the region below the pad12A. When traversing the pad row PL, it is desirable that the wiring in the multilayered wiring layer MWL be formed in a region of the multilayered wiring layer MWL causing no overlap with the pad region as seen from the top, e.g., in a region between the pads.

The wiring configuration illustrated inFIG. 2Ais merely an example. For example, the first wiring group W1may be provided by sequentially forming: a wire, which passes through the third insulating layer ISL3, the second metal wiring layer M2, and the second insulating layer ISL2and reaches the first metal wiring layer M1, immediately below the first connection part CN1; and a wire, which extends from the wire in the first metal wiring layer M1, passes through the first insulating layer ISL1, and reaches the protection circuit EPC. Alternatively, the second wiring group W2may be provided by sequentially forming: a wire, which extends from the protection circuit EPC, passes through the first insulating layer ISL1, and reaches the first metal wiring layer M1; a wire, which goes through a region between the pads in the same wiring layer, i.e., the first metal wiring layer M1and reaches the region above the circuit block CB; and a wire, which passes through the first insulating layer ISL1and reaches the circuit block CB.

Next, an example of connection between the second pad12B and the circuit block CB will be described with reference toFIG. 2B. The second pad12B is connected to a third wiring group (third wiring to the circuit block CB) W3in the multilayered wiring layer MWL by means of the connection part CN2thereof. The second pad12B is connected to the circuit block CB via the third wiring group W3.

Specifically, the pad12B is formed in the third metal wiring layer M3, and the connection part CN2extends from the pad12B in the third metal wiring layer M3. A through hole, which passes through the third insulating layer ISL3and reaches the second metal wiring layer M2, is formed immediately below the connection part CN2. A wire W31is formed in this through hole. In the second metal wiring layer M2, a wire W32, which extends from the wire W31and reaches a region above the circuit block CB, is formed.

A through hole, which extends from a surface of the wire W32closer to the circuit structure layer CSL, passes through the second insulating layer ISL2, and reaches the first metal wiring layer M1, is formed. A wire W33is formed in this through hole. In the first metal wiring layer M1, a wire W34connected to the wire W33is formed. A through hole, which extends from a surface of the wire W34closer to the substrate11, passes through the first insulating layer ISL1, and reaches the circuit block CB in the circuit structure layer CSL, is formed. A wire W35is formed in this through hole. In this manner, the pad12B is connected to the circuit block CB via the third wiring group W3.

Note that the wiring configuration illustrated inFIG. 2Bis merely an example. For example, the third wiring group W3may be formed in the following manner depending on arrangement of other wiring and circuit. First, a wire, which passes through the third insulating layer ISL3, the second metal wiring layer M2, and the second insulating layer ISL2and reaches the first metal wiring layer M1, is formed immediately below the connection part CN2. Subsequently, a wire, which extends toward the circuit block CB in the first metal wiring layer M1, is formed. Next, a wire, which extends from the first metal wiring layer M1, passes through the second insulating layer ISL2, and reaches the second metal wiring layer M2(in a direction opposite to the substrate11), is formed. Subsequently, a wire, which goes through the second metal wiring layer M2to reach a region above the circuit block CB, is formed. A wire, which passes through the second insulating layer ISL2, the first metal wiring layer M1, and the first insulating layer ISL1and reaches the inside of the circuit structure layer CSL, is then formed. In other words, wiring may be formed so as to be routed through the wiring layers in the up-and-down directions.

Here, a difference between the first pad12A and the second pad12B, i.e., a difference between extending directions of the connection parts CN1and CN2, will be described. In the pad group12, whether to form the first pad12A or the second pad12B, i.e., which direction the connection part is extended from the pad, can be determined (selected) in view of the wiring efficiency.

Specifically, as in the first pad12A, for example, when the pad12A needs to be connected to the protection circuit EPC positioned on the outer side of the substrate11with respect to the pad12A as seen from the top, it is desirable that the connection part CN1thereof be formed (extended) on the side of the protection circuit EPC, i.e., on the outer side of the substrate11as seen from the pad12A.

As in the second pad12B, on the other hand, when the pad12B needs to be connected to the circuit block CB positioned on the inner side of the substrate11with respect to the pad12B, it is desirable that the connection part CN2thereof be formed (extended) on the side of the circuit block CB, i.e., on the inner side of the substrate11as seen from the pad12B.

By determining the formation positions of the connection parts CN1and CN2in the pads as described above, a reduced wiring distance, a reduced number of metal wiring layers, an optimized wiring efficiency, and overall reduction in chip size can be achieved. By setting the formation positions of the pads so as to be shifted from each other in the short direction of the pad row PL as in the pads12A and12B, the overall layout of the pads and the connection parts (extended parts) is optimized, thereby further reducing the chip size.

A certain distance needs to be provided between the pad group12and an end of the substrate11. Specifically, a bonding wire is formed on the pad12A. In a step of this wire bonding, a bonding head of a bonding apparatus is brought into contact with the pad. Thus, force pressing down the device is applied from the pad12A toward the substrate11. If the pad group12is positioned too close to the end of the substrate11, a risk of damaging the multilayered wiring layer MWL or the substrate11is increased in the wire bonding step. Thus, the pad group12needs to be formed at a certain distance from the end of the substrate11.

A region of the multilayered wiring layer MWL positioned between the pad group12and the end of the substrate11can be used as a wiring region. Thus, such a region can be effectively utilized by forming wires such as the above-described surface wires13. Similarly, in a region of the circuit structure layer CSL and the substrate11positioned between the pad group12and the end of the substrate11, a semiconductor circuit can be formed. It is preferable that the protection circuit EPC be formed in this region of the circuit structure layer CSL and the substrate11. Forming the protection circuit EPC in a region closer to the end of the substrate11can improve the wiring efficiency. Furthermore, by physically distancing the protection circuit EPC from the circuit block CB, which is an ESD protected circuit, the ESD protection efficiency can be improved.

Thus, the protection circuit EPC is formed at a position opposite to the circuit block CB with respect to the pad12A. Moreover, in view of the wiring efficiency, it is desirable that the connection part CN1of the pad12A be extended (formed) in the first direction DR1, i.e., on the side of the protection circuit EPC.

In the present embodiment, the second pad12B is not connected to the protection circuit EPC. This is because the pad12B is a pad unnecessary to be connected to the protection circuit EPC. Specifically, the pad12B is a pad not designed for external connection. The pad12B is a non-bonding pad in which no bonding wire is formed thereon. For example, the second pad12B is a pad used for externally applying a power-supply voltage to the circuit block CB upon a functional test (burn-in test, for example) at the time of manufacturing. Also, the pad12B is a pad used for monitoring an internal power supply in the circuit block CB, for example.

Thus, the second pad12B is connected to the circuit block CB with no intervention of the protection circuit EPC in the present embodiment. Thus, in view of the wiring efficiency, it is desirable that the connection part CN2of the pad12B be extended in the second direction DR2(direction opposite to the first direction DR1), i.e., on the side of the circuit block CB. Note that when no bonding wire is formed in the pad12B, the pad size thereof can be made smaller than that of the pad12A. This makes it possible to reduce (shorten) the distance of the pad group12along the longitudinal direction of the pad row PL.

Note that the arrangement order of the pads12A and12B in the pad group12can be determined in view of the efficiency of wiring to the circuit block CB. For example, the pads12B may be first disposed in view of the wiring distance to the circuit block CB from the pad12B, and then other pads12A may be formed between the pads12B. Alternatively, pads constituting the opposite ends of the pad group12may be the pads12B and pads positioned therebetween may be the pads12A. Alternatively, the pads12B may be formed in a scattering manner in the middle of the pad group12.

FIG. 3is a top view schematically illustrating arrangement of pads and protection circuits in the semiconductor device10. First, specific examples of the pad12A connected to the circuit block CB via the protection circuit EPC and the pad12B directly connected to the circuit block CB with no intervention of the protection circuit EPC will be described with reference toFIG. 3. In the present embodiment, DQ pads, a VSSQ pad, a VCCQ pad, ADD pads, a CLK pad, a VSS pad, and a VCC pad are each formed as the pad12A.

The DQ pad is a pad used for inputting and outputting data into and from the circuit block. The VCCQ pad and the VSSQ pad are pads used for applying a power-supply potential and a ground potential, respectively, to the circuit block CB upon inputting and outputting data. The ADD pad is a pad used for assigning an address where inputting and outputting of data are performed. The CLK pad is a pad used for inputting and outputting a clock signal into and from the circuit block CB. The VCC and VSS pads are pads used for applying a power-supply potential and a ground potential, respectively, to the circuit block CB. These pads12A are connected to an external device via the bonding wires, and external signals are inputted into and outputted from these pads during a normal operation. Thus, the pads12A are connected to the protection circuits EPC.

Moreover, in the present embodiment, a VPP pad, a VCP pad, and a VBL pad are formed as the pads12B. The VPP pad is a pad used for applying a high power-supply potential (boosting potential) to the circuit block CB upon inputting and outputting data. The VCP pad is a pad used for applying a potential to a plate line in the circuit block CB. The VBL pad is a pad used for applying a potential to a bit line in the circuit block CB. These pads12B are directly connected to the circuit block CB. Although not illustrated in the figure, a VMON pad used for monitoring a potential in the circuit block CB may be additionally formed as the pad12B.

Next, the arrangement of the protection circuits EPC will be described. In view of the wiring efficiency, it is desirable that the protection circuit EPC be provided at a position opposed to the connection part CN1of the pad12A as seen from the top. Moreover, it is desirable that the protection circuits EPC be arranged in the same direction along the arrangement direction of the pads12A and aligned in a row. This is because forming the same type of circuits in alignment simplifies wiring, thus contributing to reduction in device size.

Although the present embodiment has described the case where the connection parts CN1and CN2are formed along the direction perpendicular to the longitudinal direction of the pad row PL, the formation positions of the connection parts CN1and CN2are not limited thereto. For example, some pads in the pad group may be connected only to connection parts extended along the longitudinal direction of the pad row PL. Alternatively, the pad12A may be connected to a connection part extended along the longitudinal direction of the pad row PL as well as to the connection part CN1, for example.

Moreover, although the present embodiment has described the case where the circuit block CB is formed in the central part of the substrate11and the pad groups12are formed along the peripheries of the circuit block CB, the positional relationship between the circuit block CB and the pad group12is not limited thereto. For example, two circuit blocks may be formed and a pad group may be formed in a central part between the two circuit blocks. Moreover, although the present embodiment has described the case where the pad groups12are formed along the two opposed sides of the substrate11, the formation position of the pad group12is not limited thereto. For example, the pad group may be formed so as to surround the circuit block CB.

Modified Example

FIG. 4is a top view illustrating a configuration of a semiconductor device10A according to a modified example of the first embodiment. The semiconductor device10A has the same configuration as the semiconductor device10except for formation positions of the pads12A and12B and structures of extended parts EP1and EP2. Note thatFIG. 4only shows a single pad12A and the extended part EP1thereof, a single pad12B and the extended part EP2thereof, and a pair of surface wires13A and13B, and illustration of other components is omitted.

In the present modified example, the pads are arranged in view of a distance between the surface wire13A and the pad12B and between the surface wire13B and the pad12A as well as a distance between the pad12A and the connection part CN1and between the pad12B and the connection part CN2. More specifically, in view of a manufacturing error in bonding position upon wire bonding, a certain distance needs to be provided between the pad12A and the connection part CN1(between the pad12A and the wire W11of the wiring W1in the device). Similarly, a certain distance also needs to be provided between the pad12A and the surface wire13B. Such a distance becomes more non-negligible as a wire width and a wire interval, for example, are made finer. If the pads and the connection parts as well as the pads and the surface wires are formed with an interval smaller than such a required distance, the bonding wires and the wires may be short-circuited, thus resulting in connection failure.

In the present modified example, the required distance between the pad and the wire is referred to as a pad-wire distance L3. Although a certain distance needs to be provided also between the connection part CN1and the first surface wire13A, such a distance requires no consideration in positional misalignment at the time of wire bonding. Thus, it is only required that the connection part CN1and the first surface wire13A are spaced apart from each other by a distance L4smaller than the distance L3.

In the present modified example, the pad12A and the connection part CN1are formed with the distance L3provided therebetween. Specifically, an extension part (first extension part) EX1for connecting between the pad12A and the connection part CN1is formed between the pad12A and the connection part CN1. A length of the extension part EX1(extension part length) along the short direction of a pad row PL is at least equal to the distance L3. Note that the connection part CN1and the extension part EX1are collectively referred to as the extended part (first extended part) EP1in the present modified example. In other words, the pad12A is provided with the extended part EP1extended in the first direction DR1from the pad12A, and the extended part EP1is constituted by the connection part CN1and the extension part EX1.

Similarly, the pad12B is provided with the extended part (second extended part) EP2extended in the second direction DR2from the pad12B, and the extended part EP2includes the connection part CN2and an extension part (second extension part) EX2. Moreover, the connection part CN2of the extended part EP2and the second surface wire13B are spaced apart from each other by the distance L4. No wiring to the circuit block CB is formed immediately below the extension parts EX1and EX2. Such wiring is formed immediately below the connection parts CN1and CN2.

Although the present modified example has described the case where the extension part EX1and the connection part CN1together constitute the extended part EP1and the extension part EX2and the connection part CN2together constitute the extended part EP2, the extended parts EP1and EP2may be constituted only by the connection parts CN1and CN2, respectively. Specifically, the pad12A and the extension part EX1extended in the first direction DR1from the pad12A by the distance L3may constitute the first pad, and the connection part CN1extended in the first direction DR1from the extension part EX1by the distance L2may constitute the first extended part EP1. Similarly, the pad12B and the extension part EX2extended in the second direction DR2from the pad12B by the distance L3may constitute the second pad, and the connection part CN2extended in the second direction DR2from the extension part EX2by the distance L2may constitute the second extended part EP2.

In the present modified example, the pad12B is formed at a position moved (shifted) in the first direction DR1from the longitudinal direction (central axis CA) of the pad row PL passing through the center point CP1of the pad12A by a distance equal to addition of the connection part length L2and the distance between the connection part CN1and the first surface wire13A (connection part-wire distance) L4. Specifically, the center point CP2of the pad12B is formed at a position shifted from the central axis CA by the distances L2and L4. Here, the width PLW of the pad row PL equals (the pad length L1)+(the connection part length L2)+(the connection part length L2)+(the extension part length L3). This is the configuration having the smallest pad row width PLW also in view of the pad-wire distance.

Thus, when the required interval between the pad and the wire in view of positional misalignment upon bonding is non-negligible, the pad row width PLW can be minimized by shifting the position of the pad12B from the pad12A by the distance equal to the connection part length L2and the connection part-wire distance L4.

As described above, when the connection parts are extended in the opposite directions from the pads, the pad layout including the connection parts (extended parts) is optimized by shifting the positions of the pads from each other in the short direction of the pad row PL by the length of the connection part and reduction in device size can be thus achieved.

This application is based on a Japanese Patent application No. 2014-145152 which is hereby incorporated by reference.