Method of validating timing issues in gate-level simulation

A method of validating timing issues in a gate-level simulation (GLS) of an integrated circuit design including multiple cells includes running a simulation routine of a behavioral model of the design and obtaining a first simulation result. If there is a possible timing violation at a cell corresponding to a forcing indeterminate value, the simulated output of the cell is forced to a first value and a second simulation result obtained. If this result is negative, a report of apparent timing violations at the cell is generated. If the second simulation result is positive, the output of the cell is then forced to a second value and a third simulation result is obtained. If this result is negative, a report of apparent timing violations at the cell is generated but, if it is positive, a report of no apparent timing violation is generated.

BACKGROUND OF THE INVENTION

The present invention is directed to integrated circuit design and test and, more particularly, to a method of validating timing issues in a gate-level simulation of an integrated circuit design.

During the electronic design automation (EDA) design flow of an integrated circuit (IC) having digital (or mixed digital and analog) circuitry, register-transfer-level (RTL) abstraction typically is used in hardware description languages (HDLs) like Verilog and VHDL to create high-level representations of the IC, selecting standard cell designs and their characteristics from a standard cell library. An RTL description is defined in terms of registers that store signal values, and combinational logic that performs logical operations on signal values. The RTL description is usually converted to a gate-level description (such as a netlist) that is used by placement and routing tools to create a physical layout.

The correct operation and performance of the IC is often limited by timing considerations. Static timing analysis (STA) of an IC enables analysis of simplified delay models of the IC and identification of such issues as hold-time and set-up time violations, glitches, and clock skew, using definitions of critical paths and corners. However, STA constraints may be incorrect and may miss some critical paths so dynamic gate-level simulation of the design is often necessary.

Typically dynamic gate-level simulation determines the output values of a gate based on the input values of the gate. If one or more of the input values is indeterminate (that is to say ambiguous), the behavioral model of the simulator may result in an output value of the gate that is also indeterminate. As the simulation progresses, these indeterminate values are propagated from gate to gate to the outputs of a combinational block. The indeterminate values are designated X in some EDA languages. In particular, in VHDL the values ‘U’, ‘X’, ‘W’, and ‘-’ are metalogical values; they define the behavior of the model itself rather than the behavior of the hardware being synthesized, where ‘U’ represents the value of an object before it is explicitly assigned a value during simulation; ‘X’ and ‘W’ represent forcing and weak values, respectively, for which the model is not able to distinguish between logic levels and are distinct from values from a high impedance source or output, designated Z, which may not propagate from gate to gate. The propagation of the indeterminate X values typically cause the simulation to crash, increasing the difficulty of analyzing the cause and position of a timing violation.

When a possible timing violation can be identified as a false timing violation, that is to say one that will not in fact occur in the physical IC, it is possible in some conventional timing simulation techniques to set a parameter called an Xfilter for the standard cell. In this technique, when the Xfilter parameter is set, the model of the identified cell generates an output value corresponding to the cell input value and the theoretical function of the cell. For example, in the case of a D flip flop with a positive edge clock, the model will generate a definite output value equal to the value at the D input at the positive edge of the clock if the Xfilter parameter is set. In addition, all the timing checks for that cell will be disabled, enabling the simulation to proceed without this cell being the cause of the simulation crashing. However, the behavior of the cell in the simulation with the Xfilter parameter set will be unlike the cell in the physical IC. Also the Xfilter disables all the timing checks for that cell, which may mask real timing violations at other points in time. Moreover, in the case of synchronous circuit blocks, it may be difficult to identify whether clock signals are in the same clock domain or not, and validate the possible timing violation, because there may be many buffers in the clock tree, clock gate cells and clock dividers of the same domain.

Identifying and analyzing timing violations and distinguishing real from false timing violations in the IC design can be very labor-intensive and time-consuming. A method of doing so efficiently and with a higher degree of automation is sought.

Referring now toFIG. 1, a conventional method100of electronic design automation (EDA) for producing a gate-level design of an integrated circuit (IC) and analyzing timing issues in the IC is shown. The method100starts at step102selecting standard cells from a library to include in the IC and producing a register-transfer-level (RTL) description at step104. The RTL description is converted to a gate-level description (such as a netlist) at step106. At step108, static timing analysis (STA) of the gate-level description is performed and any timing issues revealed by the STA may be resolved by changes to the design. Dynamic gate-level simulation of the design is then performed at step110.

FIGS. 2 and 3illustrate a method300in accordance with an embodiment of the present invention of validating timing issues in a gate-level simulation (GLS) of an integrated circuit (IC) design200having a plurality of cells. The method300comprises running a gate-level simulation (GLS) at step302of a behavioral model of the design200and obtaining a first simulation result304. If the first simulation result304yields a possible timing violation at a cell corresponding to the forcing of an indeterminate value, the simulated output of the cell is forced at step306to a first value. The simulation routine is re-run at step308and a second simulation result310is obtained. If the second simulation result310is an apparent timing violation at the cell, a report312of the apparent timing violation at the cell is generated. If the second simulation result310has no apparent timing violation at the cell, a report of the first value and status of the simulated output of the cell is generated at step314. The simulated output of the cell is then forced at step316to a second value. The simulation routine is re-run at step318and a third simulation result320is obtained. If the third simulation result320yields an apparent timing violation at the cell, a report of the apparent timing violation is generated at step312. If the third simulation result320has no apparent timing violation at the cell, the simulation is completed. A report of no apparent timing violation is generated at step324if no timing violation is found at step304or at step320.

A gate-level design of the IC design200may be compiled using standard cells selected from a library (such as the standard cell library shown inFIG. 1at102). As illustrated inFIG. 2, in an example of a behavioral model of a gate-level design of the IC design200, at least some of the behavioral models of standard cells include configurations202for forcing the cell simulated output to the first or second value. The configurations202for forcing the cell simulated output may substitute the first value or the second value of the simulated cell output for a value of the simulated cell output that would otherwise be obtained. The first value may be a random value, and the second value is different from the first value.

If the first simulation result yields a possible timing violation, the simulated outputs of the plurality of cells may be forced to respective first values, which may be randomly defined, the simulation routine can then be re-run and a second simulation result obtained. If the second simulation result is an apparent timing violation at one or more of the plurality of cells, a report of the presence or absence of apparent timing violations, the first values and statuses of the simulated outputs at the plurality of cells may be generated. At least for the cell or cells whose result was no apparent timing violation, the simulated outputs of the cell or cells are forced to second values, different from the respective first values, the simulation routine is re-run and a third simulation result is obtained. If no apparent timing violations appear with the second values either, the simulation may again be re-run, with iterations of the simulation routines and reports until the source of the timing violation of the first simulation result is identified.

Completing the simulation may include checking at step322whether a simulation process is complete and updating a checker for the simulation progress at step326. If the simulation process is not complete (or is imperfect), further simulation routines302can then be run.

The cells of the IC design200are not necessarily combinational cells and at least some of the cells may be connected sequentially.

A report of the simulation result, of the simulated output value of the cell and of whether the simulated output value of the cell was forced may be generated for each of the simulation routines performed. Re-running the simulation routine may use the previous report in defining the value of the simulated output of the cell for re-running the simulation routine. This can simplify validation or verification of the apparent timing issue.

In an embodiment of the invention, a non-transitory computer-readable storage medium stores instructions that, when executed by a computer, cause the computer to perform the method300. The computer-readable storage medium may store standard cells, with or without the configurations202for forcing the cell simulated output to the first or second value, and other elements for the IC design200, as well as instructions for performing the method300.

In more detail,FIG. 2illustrates schematically behavioral models of modules in a gate-level design of an IC design200for simulation in an example of the method300. The IC design200is illustrated as having blocks 1 to N having cells 1.1 to 1.m, up to cells N.1 to N.m respectively. The cells of the blocks 1 to N each have outputs connected to a sea of gates (SOG). The behavioral models of the cells also have configurations202for forcing the cell output to a first or second value, according to instructions from the simulation routine or from the operator. The cells of the blocks 1 to N may be standard cells from a standard cell library. It will be appreciated that the cells may be of various types such as flip-flops, clock-gates, latches and other types and the numbers and types of cells in different blocks 1 to N will typically be different. It is possible for behavioral models of the some of the cells to have the configurations202while others do not need the configurations202. The cells whose behavioral models have the configurations202may also be standard cells available in the standard cell library as well as cells without the configurations202.

The configurations202for forcing the cell output to a first or second value are illustrated inFIG. 2in the form of hardware. It will be appreciated that, for the purpose of simulation of the IC design200, the configurations202will typically be software representing equivalent functions, and which may be stored on non-transitory computer-readable storage medium. In the example shown inFIG. 2, each configuration202has an input from the output such as204of the respective basic cell 1.1 to 1.m, up to cells N.1 to N.m. The cell output204is connected to one input of a respective multiplexer206, the other inputs of which receive a value 0, a value 1, and a random value (0/1). The multiplexer206has an output connected to the SOG, which assumes a value selected from its different inputs by a control signal on a control input208. The control input208may be controlled by the instructions from the simulation routine or from the operator, for example.

Referring again toFIG. 3, for simplicity the configuration202is labeled in the drawing as Xfilter, it being understood that the configuration202of the behavioral model does not block the output204of the cell on a single value equal to its input but substitutes for the output of the basic cell, the random value 0/1 or the value 0 or 1 under the control of the instructions of the simulation routine or of the user. At step306, the configuration202forces the output of the cell to a first value that may be a random value (0/1). Alternatively, the first value could be a predetermined value that is systematically 1 or 0.

In this example, the process step316comprises a decision at step328as to whether the first value to which the simulated output of the cell is forced at step306is high or low. If the first value is low at step306, then at step330the simulated output of the cell is forced high. If the first value is high at step306, then at step332the simulated output of the cell is forced low.

The process step316may be implemented using a software routine such as the following:

The invention may be implemented at least partially in a non-transitory machine-readable medium containing a computer program for running on a computer system. The program includes code portions for performing steps of a method according to the invention when run on the computer system.

FIG. 4is a schematic block diagram of an exemplary computer system400for performing the methods of the present invention described above. The computer system400includes a processor402coupled to a memory404and additional memory or storage406coupled to the memory404. The computer system400also includes a display device408, input devices410and412, and software414. The software414includes operating system software416, applications programs418, and data420. The applications programs418can include, among other things, a gate-level simulator, and the data420can include a gate-level design, a modified or corrected gate-level design, and a cell library. The computer system400and the constituent parts are all well known in the art, and the novelty resides in the methods and steps described above regarding gate level simulation. When software or a program is executing on the processor402, the processor becomes a “means-for” performing the steps or instructions of the software or application code running on the processor402. That is, for different instructions and different data associated with the instructions, the internal circuitry of the processor402takes on different states due to different register values, etc., as is known in the art. Thus, any means-for structures described herein relate to the processor402as it performs the steps of the methods disclosed herein.

The computer program may be stored internally on computer readable storage medium or transmitted to the computer system via a computer readable transmission medium. All or some of the computer program may be provided on non-transitory computer readable media permanently, removably or remotely coupled to an information processing system. The computer readable media may include, for example and without limitation, any number of the following: magnetic storage media including disk and tape storage media; optical storage media such as compact disk media (e.g., CD-ROM, CD-R, etc.) and digital video disk storage media; nonvolatile memory storage media including semiconductor-based memory units such as FLASH memory, EEPROM, EPROM, ROM; ferromagnetic digital memories; MRAM; volatile storage media including registers, buffers or caches, main memory, RAM, etc.; and data transmission media including computer networks, point-to-point telecommunication equipment, and carrier wave transmission media, just to name a few.