Semiconductor devices having varying electrode widths to provide non-uniform gate pitches and related methods

Semiconductor devices including a plurality of unit cells connected in parallel are provided. Each of the unit cells have a first electrode, a second electrode and a gate finger. One of the first electrodes at a center of the semiconductor device has a first width and one of the first electrodes at a periphery of the semiconductor device has a second width, smaller than the first width. The second electrodes have a substantially constant width such that a pitch between the gate fingers is non-uniform. Related methods are also provided.

FIELD OF THE INVENTION

The present invention relates microelectronic devices and more particularly to high power semiconductor devices.

BACKGROUND OF THE INVENTION

Electrical circuits requiring high power handling capability (>20 watts) while operating at high frequencies such as radio frequencies (500 MHz), S-band (3 GHz) and X-band (10 GHz) have in recent years become more prevalent. Because of the increase in high power, high frequency circuits there has been a corresponding increase in demand for transistors that are capable of reliably operating at radio frequencies and above while still being capable of handling higher power loads.

To provide increased power handling capabilities, transistors with a larger effective area have been developed. However, as the area of a transistor increases, the transistor may become less suitable for high frequency operations that, typically, require a small source to drain distance so that the carrier transit times are limited. One technique for increasing the area of a transistor while still providing for high frequency operations is to use a plurality of transistor cells that are connected in parallel. Such a configuration includes a plurality of elongated gate “fingers” which control the flow of current through each of the plurality of unit cells. Thus, the source to drain distance of each cell may be kept relatively small while still providing a transistor with increased power handling capability. Conventionally, when a plurality of parallel transistor cells are connected in parallel on a single chip, the cells are evenly spaced such that the gate-to-gate distance between adjacent cells (referred to herein as “pitch” or “gate pitch”) is uniform from one cell to the next.

When such multi-cell transistors are used in high frequency operations, they may generate a large amount of heat. As a device heats up, performance of the device typically degrades. Such degradation may be seen in gain, linearity and/or reliability. Thus, efforts have been made to keep junction temperatures of the transistors below a peak operating temperature. Typically, heatsinks and/or fans have been used to keep the devices cool so as to ensure proper function and reliability. However, cooling systems may increase size, electrical consumption, manufacturing costs and/or operating costs of systems using such transistors.

With uniform pitch multi-cell transistors, the operating temperature of cells near the center of the array is typically greater than that of the cells at the periphery. This is generally the case because the cells at the periphery have a greater thermal gradient to areas surrounding the cells. Thus, for example, adjacent cells near the center of the multi-cell array will each generate heat and thus, each side of the cells will be at an elevated temperature with respect to cells farther from the center. This results in a thermal profile that is roughly a bell curve with center junction temperatures being the hottest and with the outer most junctions having a substantially reduced operating temperature compared to the center junctions.

An uneven temperature distribution among the junctions of a device may reduce device linearity. For example, for a device with a plurality of evenly spaced gate fingers connected by a manifold, RF phasing errors may occur along both the gate manifold and the individual gate fingers as a result of differing gate resistance as a function of temperature. Conventionally, to address these issues the spacing between the gate fingers is widened and/or the length of the fingers are shortened and additional fingers added to achieve the same net active area. Both of these solutions result in spreading the heat load generated in the center of the device over a wider area. These solutions also result in a larger area for the multi-cell transistor that may reduce the number of die per wafer.

A technique that attempts to solve the temperature distribution problem is discussed in U.S. Pat. No. 6,534,857 to Morse, entitled Thermally Balanced Power Transistor, the disclosure of which is hereby incorporated herein by reference as if set forth in its entirety. As discussed therein, the gate pitch is varied making it smaller for the end units compared to those in the center of the multi-cell array. However, this may lead to non-uniform widths of the source and drain fingers in the device and may cause the drain to source capacitance (Cds) to be non-uniform, which may cause deterioration in device performance. Similar issues are discussed in commonly assigned U.S. patent application Ser. No. 10/734,398 filed Dec. 12, 2004, entitled Non-Uniform Gate Pitch Semiconductor Devices and U.S. patent application Ser. No. 10/977,227 filed Oct. 29, 2004, entitled Asymmetric Layout Structures for Transistors and Methods of Fabricating the Same, the disclosures of which are hereby incorporated herein by reference as if set forth in their entirety.

SUMMARY OF THE INVENTION

Some embodiments of the present invention provide semiconductor devices including a plurality of unit cells connected in parallel. Each of the unit cells have a first electrode, a second electrode and a gate finger. One of the first electrodes at a center of the semiconductor device has a first width and one of the first electrodes at a periphery of the semiconductor device has a second width, smaller than the first width. The second electrodes have a substantially constant width such that a pitch between the gate fingers is non-uniform.

In further embodiments of the present invention, the non-uniform pitch between the gate fingers may provide a substantially uniform junction temperature to a substantial majority of the gate fingers when in operation. The width of the second electrodes may be narrower than the first and second widths and a drain to source capacitance (Cds) may remain substantially constant in the plurality of unit cells when in operation.

In still further embodiments of the present invention, the plurality of unit cells may include a plurality of unit cells arranged in a linear array. The pitch between the gate fingers may be inversely related to a distance of the gate finger from the center of the semiconductor device. The pitch between the gate fingers at the periphery of the semiconductor device may be less than a pitch between gate fingers at a center of the device.

In some embodiments of the present invention, the plurality of unit cells may include a plurality of metal semiconductor field effect transistor (MESFET) unit cells. The semiconductor device may include a silicon carbide (SiC) metal semiconductor field effect transistor (MESFET), a gallium arsenide (GaAs) MESFET or a gallium Nitride (GaN) high electron mobility transistor (HEMT). The plurality of unit cells may include a plurality of silicon carbide transistor unit cells or a plurality of gallium nitride transistor unit cells.

In further embodiments of the present invention, the first and second widths may be from about 20 μm to about 60 μm. The non-uniform pitches between the gate fingers may be from about 10 μm to about 90 μm. The first electrodes may be source electrodes and the second electrodes may be drain electrodes.

Still further embodiments of the present invention provide field effect transistors (FETs) including a plurality of unit cells connected in parallel. Each of the unit cells include a source finger, a drain finger and a gate finger. One of the source fingers at a center of the FET has a first width and one the source fingers at a periphery of the FET has a second width, smaller than the first width. The drain fingers have a substantially constant width such that a pitch between the gate fingers is non-uniform. The non-uniform pitch between the gate fingers provides a substantially uniform junction temperature to a substantial majority of the gate fingers when in operation.

While the present invention is described above primarily with reference to semiconductor devices and FETs, other types of transistors as well as methods of fabricating semiconductor devices and, in particular, FETs are also provided.

DETAILED DESCRIPTION OF THE INVENTION

The invention is described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. It will be understood that when an element or layer is referred to as being “on”, “connected to” or “coupled to” another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly connected to” or “directly coupled to” another element or layer, there are no intervening elements or layers present. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. Like numbers refer to like elements throughout.

It will be understood that although the terms first and second are used herein to describe various regions, layers and/or sections, these regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one region, layer or section from another region, layer or section. Thus, a first region, layer or section discussed below could be termed a second region, layer or section, and similarly, a second region, layer or section may be termed a first region, layer or section without departing from the teachings of the present invention.

As used herein the term “ohmic contact” refers to contacts where an impedance associated therewith is substantially given by the relationship of Impedance=V/I, where V is a voltage across the contact and I is the current, at substantially all expected operating frequencies (i.e., the impedance associated with the ohmic contact is substantially the same at all operating frequencies) and currents.

Embodiments of the present invention will now be described in detail below with reference toFIGS. 1 through 3Ethat illustrate various embodiments of the present invention and various processes of fabricating embodiments of the present invention. Transistors, for example, a metal-semiconductor field effect transistors (MESFETs), according to some embodiments of the present invention, may be thermally balanced and have a substantially constant drain to source capacitance (Cds). In particular, in some embodiments of the present invention, a width of a source contact (finger) at a center of the device may be larger than a width of the source contact (finger) at a periphery of the device, while a width of a drain contact (finger) is kept substantially constant. Thus, a variation in pitch between the gate fingers of the device may be obtained by changing the width of the source finger, which may provide a substantially uniform junction temperature to a substantial majority of the gate fingers when in operation. Furthermore, since the Cdsis mainly determined by the width of the narrower of the source or drain contact, keeping the narrow contact (drain contact) unchanged throughout the device may allow the Cdsto remain substantially constant across the various cells of the device. Details with respect to embodiments of the present invention will be discussed further herein.

It will be understood that although embodiments of the present invention are discussed herein having a constant drain width and a varying source width, embodiments of the present invention are not limited to this configuration. For example, a width of the drain contact may be varied and a width of the source contact may be kept constant to obtain the variation in pitch without departing from the scope of the present invention.

Referring now toFIG. 1, a plan view of transistors, for example, silicon carbide (SiC) Metal Semiconductor Field Effect Transistors (MESFETs) according to some embodiments of the present invention will be discussed. While embodiments of the present invention are illustrated with reference to SiC MESFETs, the present invention should not be construed as limited to such devices. Thus, embodiments of the present invention may include other transistor devices having a plurality of unit cells. Embodiments of the present invention may be suitable for use in any semiconductor device where a more/relatively uniform junction temperature and a constant Cdsare desired and multiple unit cells of the device are present. Thus, for example, embodiments of the present invention may be suitable for use in non-silicon carbide devices, such as gallium nitride (GaN), Gallium Arsenide (GaAs) and/or silicon (Si) devices without departing from the scope of the present invention.

As illustrated inFIG. 1, a plurality of unit cells are provided on a substrate10. Each unit cell includes a first electrode or drain contact22, a gate contact24and a second electrode or source contact20A or20B, the gate contacts24are situated between the source contacts20A and20B and the drain contacts22. It will be understood that although embodiments of the present invention are discussed as having source contacts20A and20B with first and second widths W1and W2, respectively, embodiments of the present invention are not limited to this configuration. For example, source contacts having three or more widths may be provided without departing from the scope of the present invention.

Referring again toFIG. 1, the source contacts20A and20B, the gate contacts24and the drain contacts22are interdigitated. A first width W1of the source contacts20A at the periphery of the device are narrower than a second width W2of the source contacts20B at the center of the device. Furthermore, a width W3of the drain contacts22remains substantially constant throughout the device. Thus an average gate pitch ((P1+P2)/2) is larger at the center of the device than at the periphery of the device. In particular, ((P1+P2C)/2) is larger than ((P1+P2P)/2), where P2Cis the pitch at the center of the device and P2Pis the pitch at the periphery of the device. In some embodiments of the present invention, a pitch may be as small as 10 μm and an average pitch may be from about 20 μm to about 80 μm.

The non-uniform pitch provided by the variation in the width of the source contact may allow provision of a substantially uniform junction temperature to a substantial majority of the gate fingers when in operation. Furthermore, as discussed above, the Cdsof the device is typically determined based on the narrower of the source or drain contact. Thus, according to some embodiments of the present invention the width W3of the drain contact22is narrower than the first width W1of source contacts20A and the second width W2of the source contacts20B.

As further illustrated inFIG. 1, a width W4between source contacts20A and20B and gate contacts24, a width W5between gate contacts24and drain contacts22and a width W6between source contacts20A and20B and drain contacts22may be different so as to allow the pitch to be non-uniform. The width W4may be from about 0.4 μm to about 1.0 μm, the width W5may be from about 1.2 μm to 3.0 μm and the width W6will be from about 2.0 μm to about 5.0 μm.

While embodiments of the present invention illustrated inFIG. 1include five gate electrodes (fingers)24, three source electrodes20A and20B and two drain electrodes22, other numbers of these electrodes may be used. Furthermore, other MESFET or semiconductor device configurations may also be utilized. For example, devices such as those described in U.S. Pat. Nos. 4,762,806; 4,757,028; 5,270,554; 5,925,895 and 6,686,616, the disclosures of which are incorporated herein as if set forth fully, may be utilized in embodiments of the present invention. Also devices such as those described in commonly assigned U.S. patent application Ser. No. 10/136,456, filed Oct. 24, 2001 entitled DELTA DOPED SILICON CARBIDE METAL-SEMICONDUCTOR FIELD EFFECT TRANSISTORS HAVING A GATE DISPOSED IN A DOUBLE RECESS STRUCTURE; Ser. No. 10/304,272, filed Nov. 26, 2002 entitled TRANSISTORS HAVING BURIED P-TYPE LAYERS BENEATH THE SOURCE REGION; Ser. No. 10/977,054, filed on Oct. 29, 2004 entitled METAL-SEMICONDUCTOR FIELD EFFECT TRANSISTORS (MESFETS) HAVING DRAINS COUPLED TO THE SUBSTRATE AND METHODS OF FABRICATING THE SAME; Ser. No. 10/977,227, filed on Oct. 29, 2004 entitled ASYMETRIC LAYOUT STRUCTURES FOR TRANSISTORS AND METHODS OF FABRICATING THE SAME; and Ser. No. 11/012,553, filed on Dec. 15, 2004 entitled TRANSISTORS HAVING BURIED N-TYPE AND P-TYPE REGIONS BENEATH THE SOURCE REGIONS AND METHODS OF FABRICATING THE SAME, the disclosures of which are incorporated herein as if set forth fully, may be used in combination with embodiments of the present invention. However, embodiments of the present invention are not limited to MESFETs but may be utilized with other devices having an array of controlling electrodes and, in certain embodiments, a linear array of controlling electrodes.

In some embodiments of the present invention, the device may be a SiC MESFET as discussed with respect toFIG. 1. The pitch between the gate fingers24varies from a small pitch to a larger pitch toward the center of the device. By increasing the pitch at the center of the device, the increased heat dissipation area may compensate for the decreased thermal gradient at the center of the device such that the junction temperature associated with the respective gate fingers may be moderated. A more uniform junction temperature may provided for a decreased peak junction temperature which may result in improved reliability over a conventional uniform spaced device under the same operating conditions. Furthermore, the more uniform thermal profile may reduce impedance differences between the fingers and, thereby, improve linearity of an RF device.

Referring now toFIG. 2, a cross-section of transistors taken along the A-A′ ofFIG. 1according to some embodiments of the present invention will be discussed. As illustrated inFIG. 2, an exemplary portion of a MESFET incorporating embodiments of the present invention may include a first epitaxial layer12of p-type conductivity provided on a single crystal bulk silicon carbide substrate10of either p-type or n-type conductivity or semi-insulating. The substrate10may, for example, include 6H, 4H, 15R or 3C silicon carbide. The first epitaxial layer of silicon carbide12is disposed between the substrate10and an n-type epitaxial layer14. An optional metallization layer32may be formed on the backside of the substrate10, opposite the first epitaxial layer12.

The first epitaxial layer12may be a p-type conductivity silicon carbide epitaxial layer, an undoped silicon carbide epitaxial layer or a very low doped n-type conductivity silicon carbide epitaxial layer. If a low doped silicon carbide epitaxial layer is utilized, then in certain embodiments, the doping concentration of the first epitaxial layer12is less than about 5×1015cm−3. If an undoped (not intentionally doped) or n-type first epitaxial layer12is utilized, then in certain embodiments, the substrate10may be a semi-insulating silicon carbide substrate. If an undoped or n-type first epitaxial layer12is utilized, a high quality channel layer may be formed without the buffer layer having any significant electrical effect on the transistor.

As further illustrated inFIG. 2, n+regions13A,13B and17are provided that respectively define the source regions and the drain regions of the device. As used herein, “p+” or “n+” refer to regions that are defined by higher carrier concentrations than are present in adjacent or other regions of the same or another layer or substrate. The source and drain regions13A,13B and17are typically of n-type conductivity silicon carbide and have carrier concentrations that are greater than the carrier concentration of the first epitaxial layer14. For the source and drain regions13A,13B and17, carrier concentrations of about 1×1019cm−3may be suitable, but carrier concentrations as high as possible are preferred.

Ohmic contacts20A,20B and22may be formed on the second epitaxial layer14and are spaced apart so as to provide source contacts (fingers)20A and20B and drain contacts (fingers)22. As illustrated ohmic contacts20A,20B and22may be provided on the implanted source and drain regions13A,13B and17, respectively. Schottky gate contacts24, also referred to as gate fingers, are formed on the second epitaxial layer14between the source contacts20and the drain contacts22. As illustrated, optional metal overlayers26A,26B,28and30are formed on the source contacts20A and20B, the drain contacts22and the Schottky gate contacts24. A passivation layer60may also be provided. As illustrated inFIG. 3, certain embodiments of the present invention provide a linear array of cells that are connected in parallel. Thus, the gate contacts24may be connected in parallel in a third dimension.

The gate contact24may be formed of chromium, platinum, platinum silicide, nickel, and/or TiWN, however, other metals such as gold, known to one skilled in the art to achieve the Schottky effect, may be used. The Schottky gate contact24typically has a three layer structure. Such a structure may have advantages because of the high adhesion of chromium (Cr). For example, the gate contact24can optionally include a first gate layer of chromium (Cr) contacting the second epitaxial layer14. The gate contact24may further include an overlayer of platinum (Pt) and gold30or other highly conductive metal.

As is further illustrated inFIG. 2, the source contacts20A at the periphery of the device300have a first width W1and the source contacts20B at the center of the device300have a second width W2, larger than the first width W1. Furthermore, a width W3of the drain contacts22remains substantially constant throughout the device and in some embodiments of the present invention is smaller than both the first W1and second W2widths of the source contacts20A and20B. Accordingly, as discussed above with respect toFIG. 1, the variation in width of the source contacts20A and20B may provide non-uniform pitches between the gate fingers24. Furthermore, the Cdsmay remain substantially constant as the drain contacts22are narrower than the source contacts20A and20B and remain substantially constant throughout the device.

As used herein “a non-uniform gate pitch” refers to a pitch between gate fingers24being larger at the center of the device compared to the periphery of the device. The non-uniform gate pitch may provide a substantially uniform junction temperature for a substantial majority of the gate fingers of a device. In still further embodiments of the present invention, a substantially uniform junction temperature is provided for all of the gate fingers. As further used herein, the Cdsremains “substantially constant” if the Cdsvaries less than about 2.0 percent between cells.

As discussed above, embodiments of the present invention may provide a linear (single dimension) array of cells having a non-uniform gate pitch of a predefined pattern. It will be understood that embodiments of the present invention are not limited to linear arrays of cells. For example, embodiments of the present invention may be provided in two dimensions.

Processing steps in the fabrication of transistors according to some embodiments of the present invention illustrated inFIGS. 1 through 2will now be discussed with respect toFIGS. 3A through 3E. As illustrated inFIG. 3A, a first epitaxial layer12may be grown or deposited on a substrate10. The substrate10may be a semi-insulating substrate, a p-type substrate or an n-type substrate. The substrate10may be very lightly doped. If the substrate10is semi-insulating it may be fabricated as described in commonly assigned U.S. Pat. No. 6,218,680 to Carter et al. entitled “Semi-insulating Silicon Carbide Without Vanadium Domination”, the disclosure of which is hereby incorporated by reference herein as if set forth in its entirety. Other techniques for providing semi-insulating substrates may also be used. The buffer layer12may be of p-type conductivity silicon carbide having a carrier concentration of about 3.0×1015cm−3or less, but typically 1.0×1015cm−3or less. Alternatively, the buffer layer12may be n-type silicon carbide or undoped (not intentionally doped) silicon carbide. As further illustrated inFIG. 3A, a second epitaxial layer14is grown or deposited on the first epitaxial layer12.

As illustrated inFIG. 3B, a mask50may be formed for implanting n+regions13A,13B and17that respectively define first and second source regions and a drain region. The source and drain regions13A,13B and17are typically formed by ion implantation of, for example, nitrogen (N) or phosphorus (P), followed by a high temperature anneal. Suitable anneal temperatures may be from about 1100 to about 1600° C. The ion implantation may be performed on the regions which are not covered by the mask50to form n+regions13A,13B and17as illustrated inFIG. 3C. Thus, the ions are implanted in portions of the second epitaxial layer14to provide highly doped regions of n-type conductivity, for example, n-type conductivity SiC, having higher carrier concentrations greater than the second epitaxial layer14. Once implanted, the dopants may be annealed to activate the implant.

As illustrated inFIG. 3C, an insulator layer60, for example, an oxide layer, may be provided on a surface of the device. The insulator layer60may be grown or deposited over the exposed surface of the existing structure, i.e. on the source and drain regions13A,13B and17and the second epitaxial layer14. It will be understood that in some embodiments of the present invention a mesa may be provided around the perimeter of the MESFET. The mesa may have sidewalls defined by the substrate10, the first epitaxial layer12and the second epitaxial layer14that define the periphery of the transistor. The mesa may extend past the depletion region of the device to confine current flow in the device to the mesa and reduce the capacitance of the device. The mesa may be formed by reactive ion etching the above described device, however, other methods known to one skilled in the art may be used to form the mesa. Furthermore, if a mesa is not utilized the device may be isolated using other methods such as proton bombardment, counterdoping with compensating atoms or other methods known to those skilled in the art.

Referring now toFIG. 3D, contact windows41,42and43may be etched through the insulator layer60to expose a portion of a surface of the source regions13A and13B and drain region17. Nickel may then be evaporated to deposit the source and drain contacts20A,20B and22, respectively. The nickel may be annealed to form the ohmic contacts20A,20B and22as illustrated inFIG. 3E. Such a deposition and annealing process may be carried out utilizing conventional techniques known to those of skill in the art. For example, the ohmic contacts20A,20B and22may be annealed at a temperature of from about 650° C. to about 1200° C. for about 2 minutes. However, other times and temperatures may also be utilized. Times from about 30 seconds to about 10 minutes may be, for example, acceptable.

FIG. 3Eillustrates the formation of the gate contact24and the overlayers26A,26B,28and30. For example, a contact window (not shown) may be opened an insulator60and a layer of chromium may be deposited in the window. Typically, the chromium layer is formed by evaporative deposition. The gate structure may then be completed by deposition of platinum and gold. As will also be appreciated by those of skill in the art, the overlayers26A,26B and28may be formed either before or after formation of the gate structure. In fact, if a titanium/platinum/gold structure is utilized, the platinum and gold portions of the overlayers may be formed in the same processing steps as the platinum and gold portions30of the gate structure. Accordingly, the overlayers26A,26B and28may be formed prior to the formation of a gate contact or after the formation of a gate contact. As further illustrated, a substrate contact32may be provided on the backside of the substrate10.

In some embodiments of the present invention, the ohmic contacts may be the same or similar to contacts discussed in commonly assigned U.S. patent application Ser. No. 10/884,930, filed Jul. 6, 2004, entitled Silicon-Rich Nickel Silicide Ohmic Contacts for SiC Semiconductor Devices, the disclosure of which is incorporated herein by reference as if set forth in its entirety.

As further illustrated inFIG. 3E, the source contacts20A at the periphery of the device have a first width W1and the source contacts20B at the center of the device have a second width W2, larger than the first width W1. Furthermore, a width W3of the drain contacts22remains substantially constant throughout the device and in some embodiments of the present invention is smaller than both the first W1and second W2widths of the source contacts20A and20B. Accordingly, as discussed above, the variation in width of the source contacts20A and20B may provide non-uniform pitches between the gates24. Furthermore, the Cdsmay remain substantially constant as the drain contacts22are narrower than the source contacts20A and20B and remain substantially constant throughout the device.

Although embodiments of the present invention are discussed herein as having source contacts with varying widths, embodiments of the present invention are not limited to this configuration. For example, in further embodiments of the present invention, the drain contacts may have varying widths without departing from the teachings of the present invention.

In some embodiments of the present invention, one of the source contact or the drain contact may be split into first and second portions exposing a surface of the substrate between the contact portions. The absence of metal between the contact portions, may provide a further reduced Cdsand also allow the temperature of the device to be maintained. Details with respect to these embodiments of the present invention are discussed in U.S. patent application Ser. No. 10/977,227, filed on Oct. 29, 2004 entitled ASYMETRIC LAYOUT STRUCTURES FOR TRANSISTORS AND METHODS OF FABRICATING THE SAME, the disclosure of which has been incorporated herein by reference as if set forth in its entirety.

While embodiments of the present invention are discussed herein with reference to SiC MESFETs, the present invention should not be construed as limited to such devices. Embodiments of the present invention may be suitable for use in any semiconductor device where a more/relatively uniform junction temperature is desired or a peak junction temperature is to be maintained without a substantial increase in drain to source capacitance (Cds) and multiple unit cells of the device are present. Thus, for example, embodiments of the present invention may be suitable for use in non-silicon carbide devices, such as gallium nitride (GaN), gallium arsenide (GaAs) and/or silicon (Si) devices. Accordingly, embodiments of the present invention may provide, for example, SiC MESFETs, SiC MESFET MMICs, GaN HEMTs, GaN HEMT MMICs, GaAs MESFETs, GaAs MESFET MMICs, GaAs HEMTs, GaAs HEMT MMICs, GaAs pHEMTs, GaAs pHEMT MMICs and the like.