Hybrid method for forming semiconductor interconnect structure

The present disclosure provides a method for forming semiconductor structures. The method includes providing a device having a substrate, a first dielectric layer over the substrate, and a first conductive feature over the first dielectric layer, the first conductive feature comprising a first metal, the first metal being a noble metal. The method also includes depositing a second dielectric layer over the first dielectric layer and covering at least sidewalls of the first conductive feature; etching the second dielectric layer to form a trench; and forming a second conductive feature in the trench. The second conductive feature comprises a second metal different from the first metal.

BACKGROUND

As a part of the semiconductor fabrication, interconnect structures (e.g., metal lines and vias) may be formed using a damascene (or dual-damascene) process to provide electrical interconnections for various components in an IC. For example, metal lines may be formed by etching trench-like openings in an inter-metal dielectric (IMD) layer and followed by an electro-chemical plating process to fill the trench-like openings with metal (e.g., copper). As semiconductor device sizes continue to shrink, the damascene or dual-damascene process will see a number of potential problems that may affect the quality of the metallization layers. For example, when a metal line critical dimension (CD) is below 20-nanometer (nm), the trench-like openings may become too narrow and thus may not be properly filled with metal through a damascene process, resulting in relatively high resistances. Therefore, while semiconductor interconnect structure formation processes have generally been adequate for their intended purposes, they have not been entirely satisfactory in every aspect.

DETAILED DESCRIPTION

An integrated circuit (IC) contain a plurality of patterned metal lines separated by inter-wiring spacings. Metal patterns of vertically spaced metallization layers are electrically interconnected by vias. Metal lines formed in trench-like openings typically extend substantially parallel to the semiconductor substrate. Semiconductor devices of such type, according to current technology, may comprise eight or more levels of metallization layers to satisfy device geometry and micro-miniaturization requirements.

A common process for forming metal lines or vias is known as “damascene” process. Generally, a damascene process involves forming trench-like openings in an inter-metal dielectric (IMD) layer. A trench-like opening is typically formed using conventional lithographic and etching techniques. After the trench-like opening is formed, a diffusion barrier layer and an adhesion layer are deposited within the trench-like opening. An electro-chemical plating process is then used to fill the trench-like opening with metal or metal alloys to form a metal line and possibly a via underneath the metal line as well. Excess metal material on the surface of the IMD layer is then removed by chemical mechanical planarization (CMP).

With increasing packing density in microelectronic devices, copper (Cu) has been used as an interconnecting metal among other available metal materials due to its superior electrical conductivity (5.96E7 S/m) and excellent resistance against electro migration. The damascene process with copper, which involves copper electroplating followed by CMP of the copper, has been commonly adopted for patterning copper. At the meantime, as semiconductor device sizes continue to shrink, the damascene process with copper also sees a number of potential problems that may affect the quality of the metallization layers. For example, when a metal line critical dimension (CD) is below 20-nanometer (nm), a trench-like opening may become too narrow and the stack of diffusion barrier layer and adhesion layer will occupy substantial portions of the openings, leaving less room for the more conductive copper. The remaining smaller amount of copper has higher resistance and thus degrade semiconductor device performance. This problem is particularly acute in high aspect ratio trench-like openings of small width. Moreover, the trench-like openings may not be properly filled in a damascene process, such that the top portion of the openings may be blocked, which may create a void underneath that deteriorates device performance. Besides, the narrower copper lines may have a shorter lifetime before the higher current density destroys them by electro migration.

This invention is related generally to interconnect structures in integrated circuits, and more particularly to a hybrid method that combines metal etching process and damascene process, which results in an interconnect structure that includes narrow metal lines formed by a noble metal (or other suitable metals) through a metal etching process and relatively wider metal lines formed by copper (or other suitable metals) through damascene process. In embodiments of the present disclosure, the hybrid method allows narrow metal lines to be formed of a bulk metal other than copper, which provides a lower resistance than copper's otherwise problematic filling in narrow trench-like openings, while other metal lines that are relatively wider still benefit from copper's low resistivity.

In a hybrid method for forming interconnect structures, an IC layout defining various metal lines in the same IMD layer is decomposed into two subsets and each of the two subsets appears in a separate photomask layer (or a masking layer) in a data file. The data file is then used to fabricate photomasks. Two photomasks corresponding to the two subsets are then used in two different processes, one defines metal lines narrower than a predetermined width (i.e., narrow metal lines) suitable for metal etching process and another defines metal lines wider than the predetermined width (i.e., wide metal lines) suitable for damascene process, for collectively defining metal lines made of different metals in the same IMD layer. Using two photomasks in two different processes to pattern metal lines in the same IMD layer distinguishes the hybrid method from traditional methods that use merely one process to accomplish the task. As used herein, a photomask (or mask or reticle) is an apparatus used in photolithography (or lithography), such as a plate having fused quartz substrate with a patterned chromium layer for deep ultraviolet (DUV) lithography, while a photomask layer is a data file (such as a GDS file) used for fabricating a photomask.

Decomposing an IC layout may be performed at a design stage by design engineers and/or layout engineers. Alternatively or additionally, it may be performed at a later stage after the design stage, for example, by a foundry in a fabrication stage.FIG. 1is a simplified block diagram of an embodiment of an IC manufacturing system100and an IC manufacturing flow associated therewith. The IC manufacturing system100includes a plurality of entities, such as a design house120, a mask house130, and an IC manufacturer150(i.e., a fab), that interact with one another in the design, development, and manufacturing cycles and/or services related to manufacturing an IC device160. The various entities are connected by a communications network, which may be a single network or a variety of different networks, such as an intranet and the Internet, and may include wired and/or wireless communication channels. Each entity may interact with other entities and may provide services to and/or receive services from the other entities. One or more of the design house120, mask house130, and IC manufacturer150may be owned by separate companies or by a single company, and may even coexist in a common facility and use common resources.

The design house (or design team)120generates an IC design layout (or IC layout)122. The IC design layout122includes various geometrical patterns (e.g., polygons representing metal lines) designed for the IC device160. The geometrical patterns correspond to IC features in one or more semiconductor layers that make up the IC device160. Exemplary IC features include active regions, gate electrodes, source and drain features, isolation features, metal lines, contact plugs, vias, and so on. The design house120implements appropriate design procedures to form the IC design layout122. The design procedures may include logic design, physical design, place and route, and/or various design checking operations. The IC design layout122is presented in one or more data files having information of the geometrical patterns. For example, the IC design layout122can be expressed in a GDSII file format or DFII file format.

The mask house130uses the IC design layout122to manufacture a set of masks to be used for fabricating the various layers of the IC device160according to the IC design layout122. The mask house130performs data preparation132and mask fabrication144. The data preparation132translates the IC design layout122into a form that can be physically written by a mask writer. The mask fabrication144fabricates the set of masks (photomask or reticle).

In the present embodiment, the data preparation132includes a layout decomposition134which is configured to decompose a layout representing metal lines in one IMD layer into two subsets based on metal line widths which would be suitable for two different processes (e.g., metal etching process and damascene process) employed by the fab150. The data preparation132, particularly the layout decomposition134, may produce feedback to the design house120, which may be used to modify (or adjust) the IC design layout122to make it compliant for the manufacturing processes in the fab150. As discussed above, the layout decomposition134may be implemented by the design house120, instead of by the mask house130, in some embodiments. The data preparation132may further include other manufacturing flows such as optical proximity correction (OPC), off-axis illumination, sub-resolution assist features, other suitable techniques, or combinations thereof. The details of the layout decomposition134will be discussed in later section of the present disclosure.

After the data preparation132prepares data for the mask layers, the mask fabrication144fabricates a group of masks including the two masks for the hybrid method for forming interconnect structures. For example, an electron-beam (e-beam) or a mechanism of multiple e-beams is used to form a pattern on a mask based on data files derived from the IC design layout122. The mask can be formed in various technologies such as binary masks, phase shifting masks, and EUV masks. For example, a binary mask includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chromium) coated on the substrate. The opaque material is patterned according to the mask data, thereby forming opaque regions and transparent regions on the binary mask. A radiation beam, such as an ultraviolet (UV) beam, is blocked by the opaque regions and transmits through the transparent regions, thereby transferring an image of the mask to a sensitive material layer (e.g., photoresist) coated on a wafer152. For another example, a EUV mask includes a low thermal expansion substrate, a reflective multilayer (ML) over the substrate, and an absorption layer over the ML. The absorption layer is patterned according to the mask data. A EUV beam is either absorbed by the patterned absorption layer or reflected by the ML, thereby transferring an image of the mask to a sensitive material layer (e.g., photoresist) coated on the wafer152. In some embodiments, the fab150may also employ some kind of maskless lithography, such as e-beam lithography. For example, one of the masks may be based on an e-beam lithography. In such a case, the data preparation132may prepare the direct-write data file for the maskless lithography and the mask fabrication144does not make a photomask for those particular subsets to be produced by the maskless lithography.

The IC manufacturer (fab)150, such as a semiconductor foundry, uses the masks to fabricate the IC device160using, for example, lithography processes. The fab150may include front-end-of-line (FEOL) fabrication facility and back-end-of-line (BEOL) fabrication facility. Particularly, the fab150implements two different patterning processes to define metal lines on the semiconductor wafer152. For example, metal etching process using one of the masks to pattern narrow metal lines and damascene process using another of the masks to define wide metal lines. The narrow metal lines and wide metal lines collectively form interconnect structures in a certain IMD layer on the wafer152.

FIG. 2illustrate a flow chart of a method200, constructed according to various aspects of the present disclosure. Embodiments of the method200may be implemented by the layout decomposition134(FIG. 1). The method200is an example, and is not intended to limit the present disclosure beyond what is explicitly recited in the claims. Additional operations can be provided before, during, and after the method200, and some operations described can be replaced, eliminated, or relocated for additional embodiments of the method. The method200is described below in conjunction withFIG. 3, which graphically illustrate some principles of the method200.

Referring toFIG. 2, at operation202, the method200is provided with a layout of an IC. Referring toFIG. 3, an exemplary layout300includes geometrical patterns (rectangles in this embodiment) ML1, ML2, ML3, ML4, and ML5, each representing a metal line. Each of the metal lines has a width. Particularly, the metal line ML1has a width W1, the metal line ML2has a width W2, the metal line ML3has a width W3, the metal line ML4has a width W4, and the metal line ML5has a width W5. Further, in this embodiment, the widths W1, W4, and W5are smaller than a predetermine value X, while the widths W2and W3are equal to or greater than the predetermined value X. X represents a smallest width that is suitable for a metal line to be formed by a damascene method. For example, X is about 2.5 times of minimum metal line CD. If X is smaller than 2.5 times of minimum metal line CD, a metal line formed by damascene method will face the narrow opening filling difficulties discussed above. In the illustrated embodiment, the metal line CD is about 10 nm and X is about 25 nm. Each of the widths W1, W4, and W5ranges from about 10 nm to about 20 nm, such as equals to the metal line CD at about 10 nm. Each of the widths W2and W3ranges from about 25 nm to about 1 micron (um), such as from 100 nm to 1 um. A ratio of a width of metal line ML2or ML3is at least 2.5 times of a width of metal line ML1, ML4, or ML5, such that width of metal line ML2or ML3is not too small for damascene process.

The metal lines are spaced from each other. Particularly, the patterns ML1and ML2are spaced by a distance (or spacing) S12, the patterns ML2and ML3are spaced by a distance S23, the patterns ML3and ML4are spaced by a distance S34, and the patterns ML4and ML5are spaced by a distance S45. Further, in this embodiment, the distance S45is smaller than the distance S23. In a specific example, W2equals W3, M4equals M5, and W2+S23defines a first pitch P23, W4+S45defines a second pitch P45that is smaller than the first pitch P23.

Referring back toFIG. 2, at operation204, the method200classifies each metal line as either a narrow metal line or a wide metal line by comparing its width to the predetermined value X. In the illustrated embodiment, each of the metal lines ML1, ML4, and ML5has a width less than X. Therefore, each of the metal lines ML1, ML4, and ML5is classified as a narrow metal line. Similarly, each of the metal lines ML2and ML3has a width equal to or larger than X. Therefore, each of the metal lines ML2and ML3is classified as a wide metal line.

At operation206, the method200decomposes the IC layout into two sub-layouts, one including all the narrow metal lines and another one including all the wide metal lines. Referring toFIG. 3, the exemplary layout300is decomposed into a sub-layout302and a sub-layout304. The sub-layout302includes all the narrow metal lines classified in operation204, such as metal lines ML1, ML4, and ML5. In the sub-layout302, the metal lines ML1and ML4originally separated by metal lines ML2and ML3in the exemplary layout300become adjacent metal lines. The sub-layout304includes all the wide metal lines classified in operation204, such as metal lines ML2and ML3. The sub-layouts302and304(in GDSII file format or DFII file format) are subsequently sent to mask fabrication144(FIG. 1) to create two corresponding masks.

FIG. 4illustrate a flow chart of a method400, constructed according to various aspects of the present disclosure. The method400is a hybrid method that utilizes the two masks representing two sub-layouts created in the method200. Embodiments of the method400may be implemented by the fab150(FIG. 1). The method400is an example, and is not intended to limit the present disclosure beyond what is explicitly recited in the claims. Additional operations can be provided before, during, and after the method400, and some operations described can be replaced, eliminated, or relocated for additional embodiments of the method. The method400is described below in conjunction withFIGS. 5-20, which graphically illustrate some principles of the method400.FIGS. 5-20illustrate sectional views of an exemplary integrated circuit500during various fabrication stages of the method400in accordance with some embodiments.

Referring toFIG. 5, the method400begins at operation402by providing or receiving a device500including a substrate502as illustrated inFIG. 5. In some embodiments, the substrate502includes silicon. Alternatively, the substrate502may include other elementary semiconductor such as germanium in accordance with some embodiments. In some embodiments, the substrate502additionally or alternatively includes a compound semiconductor such as silicon carbide, gallium arsenic, indium arsenide, and indium phosphide. In some embodiments, the substrate502includes an alloy semiconductor such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, and gallium indium phosphide.

In some embodiments, the substrate502includes a semiconductor-on-insulator (SOI) structure. For example, the substrate may include a buried oxide (BOX) layer formed by a process such as separation by implanted oxygen (SIMOX). In various embodiments, the substrate502includes various p-type doped regions and/or n-type doped regions, such as p-type wells, n-type wells, p-type source/drain features and/or n-type source/drain features, formed by a process such as ion implantation and/or diffusion. The substrate502may further include other functional features such as a resistor, a capacitor, diode, transistors, such as field effect transistors (FETs). The substrate502may include lateral isolation features configured to separate various devices formed on the substrate502.

The device500includes a dielectric layer504deposited above the substrate502. In some embodiments, the dielectric layer504may comprise tetraethylorthosilicate (TEOS) oxide, un-doped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and/or other suitable dielectric materials. The dielectric layer504may be formed by PECVD, FCVD, or other suitable methods. In some embodiments, the dielectric layer504is formed of a low-k (e.g., a dielectric constant value around 3.5) dielectric layer or an extreme low-k (e.g., a dielectric constant value around 2.5) dielectric layer, such as carbon-containing dielectric materials, and may further contain nitrogen, hydrogen, oxygen, and combinations thereof. If an extreme low-k dielectric layer is used, a curing process may be followed after depositing the extreme low-k dielectric layer to increase its porosity, lower the k value, and improve the mechanical strengths. The operation402may also include performing one or more chemical-mechanical polishing (CMP) processes to planarize the top surface of the device500.

In some embodiments, the dielectric layer504is an inter-metal dielectric (IMD) layer that includes interconnect structures. In some embodiments, the dielectric layer504may include a plurality of IMD layers, not limited to the single IMD layer illustrated in the present embodiment. Each of the IMD layer may have a thickness ranging from about 300 nm to about 1800 nm. The IMD layers provide electrical insulation as well as structural support for a multi-layer interconnect structures. Multi-layer interconnect structures may include a plurality of metallization layers and may further include vias or contacts of the interconnect feature (e.g., back-end-of-the-line (BEOL) features) disposed in the IMD layers. For example, an upper metallization layer (e.g., metal 4 (M4), metal 5 (M5), etc.) includes a plurality of conductive features (e.g., metal lines, contacts, and/or vias) embedded in the IMD layers.

A top portion of the dielectric layer504may include an etch stop layer506. The etch stop layer506functionally provides isolation for the lower portion of the dielectric layer504as a barrier layer and also provides end point control during subsequent etching processes. Material compositions of an etch stop layer are selected such that an etch selectivity exists between the etch stop layer and the material layer to form thereon, such that an etching process etching through the material layer thereon would stop at the etch stop layer without causing etching damages to the underlaying dielectric layer(s). The etch stop layer506may comprise silicon nitride, silicon oxynitride, silicon carbide, silicon carbon nitride, metal oxide (e.g., AlOx), metal oxynitride (e.g., AlOxNy), and/or other suitable materials. In some embodiments, the etch stop layer506has a thickness ranging from about 10 nm to about 100 nm, such as about 50 nm.

At operation404, the method400(FIG. 4) forms a metal layer508over the etch stop layer506. As will be discussed in later section of the present disclosure, the metal layer508is to pattern into metal lines representing those classified as narrow metal lines in method200(FIG. 2). In some embodiments, the metal layer508includes pure noble metal, or alloy of noble metals with noble or non-noble metals. As used herein, the term “noble metal” means a metal selected from the group of ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir), and platinum (Pt). Noble metals have become technologically important as conductive features in integrated circuits. Unlike some other non-noble metals, such as copper, which is not suitable for direct patterning, noble metals can be patterned to form metal lines with a CD less than about 20 nm due to the suitability of being directly patterned in dry-etching approaches (e.g., reactive ion etching (RIE) process). In the illustrated embodiment, the metal layer508includes a noble metal selected from the group of Ru, Ir, Rh, and Pt. In another embodiment, the metal layer508includes alloy of noble metals with noble or non-noble metals, such as PtIr, PdPt, or PdNi. In yet another embodiment, the metal used to form the metal layer508is not limited to noble metals, as long as the metal is suitable for direct patterning, such as Cobalt (Co), Molybdenum (Mo), and Tungsten (W). The metal layer508may be deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), electroplating, or other suitable methods. The metal layer508may have a thickness ranging from about 15 nm to about 80 nm.

At operation406, the method400(FIG. 4) patterns the metal layer508to form narrow metal lines in a metal etching process. Referring toFIG. 7, operation406starts with forming a hard mask layer (e.g., a tri-layer hard mask)510on the metal layer508. Any suitable material or composition may be used in the hard mask layer510, and the illustrated tri-layer hard mask is one such example. The exemplary hard mask layer510includes a bottom layer512, a middle layer514, and a top layer516, each with different or at least independent materials. For example, the bottom layer512may include tetraethyl orthosilicate (TEOS), a nitrogen free anti-reflective coating (NFAARC) film, oxygen-doped silicon carbide (ODC), silicon carbon nitride (SiCN), or plasma-enhanced oxide (PEOx); the middle layer514may include a silicon rich polymer material (e.g., SiCxHyOz); the top layer516may include tetraethyl orthosilicate (TEOS) or silicon oxide (SiO2). It is understood that in other embodiments, one or more layers may be omitted and that additional layers may be provided as a part of the tri-layer hard mask.

The hard mask layer510may subsequently be patterned using suitable processes including double-patterning processes, multi-patterning processes, photolithography, self-aligned processes, and mandrel-spacer processes to define a pattern of narrow lines to be transferred to the underneath metal layer508. In the illustrated embodiment, operation406patterns the hard mask layer510in a lithography process and an etching process. A photoresist layer518is formed on the hard mask layer510using a spin-coating process and soft baking process. Then, the photoresist layer518is exposed to a radiation520. The radiation520is masked by a photomask522fabricated in a mask house130(FIG. 1) based on the sub-layout302(FIG. 3), such that only a portion of the photoresist layer518(e.g., areas518′) is exposed in the radiation520. The radiation520may be an extreme ultraviolet (EUV) radiation using a wavelength of 13.6 nm, an ultraviolet radiation using a wavelength of 436 nm, 405 nm, or 365 nm, or a DUV radiation using a wavelength of 248 nm, 193 nm, or 157 nm, or other available radiation for lithography, such as e-beam. In the case of e-beam lithography (which is maskless lithography), the “photomask” is in the form of a direct-write data pattern based on the sub-layout302(FIG. 3) rather than a physical apparatus.

Referring toFIG. 8, in the illustrated embodiment, the exposed photoresist layer518is developed using post-exposure baking (PEB), developing, and hard baking thereby forming a patterned photoresist layer518′ over the hard mask layer510. The patterned photoresist layer518′ defines a pattern of narrow lines, which will be transferred to the hard mask layer510first and eventually to the metal layer508. Subsequently, the hard mask layer510is etched through the openings of the patterned photoresist layer518′, forming a patterned hard mask layer510′. The patterned photoresist layer518′ is removed thereafter using a suitable process, such as wet stripping or plasma ashing. In one example, the etching process includes applying a dry (or plasma) etch to remove the hard mask layer510within the openings of the patterned photoresist layer518′. In another example, the etching process includes applying a wet etch with a hydrofluoric acid (HF) solution to remove the hard mask layer510within the openings of the patterned photoresist layer518′.

Subsequently, operation406etches the metal layer508in a metal etching process, using the patterned hard mask layer510′ as an etch mask. In the illustrated embodiment, the metal etching process is a dry etching process, such as a plasma etching process. In furtherance of the embodiment, the metal etching process includes an RIE process. The RIE process may include process parameters such as reactor operating pressure ranging from about 10 mTorr to about 300 mTorr, an RF power less than 2700 W (e.g., ranging from about 900 W to about 1600 W), a bias voltage less than about 4500 W, a temperature ranging from about 10 degrees Celsius to about 80 degrees Celsius, and an RIE etching period ranging from about 200 seconds to about 500 seconds. The RIE source gas may include an ion composition, such as argon (Ar), a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, C4F8, C2F6), or a combination thereof. The RIE source gas may further include certain chemical etchants, such as a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4) for chemical etching. In some embodiments, the chemical etchant comprises boron (B) (e.g., B2F4, BCl3, B4Cl4, BBr3). In a specific embodiment, the chemical etchant comprises a combination of boron and chlorine. In some embodiments, the total etchant flow rate is less than 1800 sccm, such as about 1200 sccm. The chemical etchant may have a flow rate about 30% to about 50% of the total etchant flow rate, such as about 40%. The etching of the hard mask layer510and the metal layer508may be in-situ. The resulting metal lines524in the patterned hard mask is shown inFIG. 9, where each of the metal lines524corresponds to a narrow metal line (e.g, ML1, ML4, or ML5) defined in the sub-layout302(FIG. 3). Even though widths of the metal lines524(e.g., W1, W4, or W5) may be within sub-20 nm range, the selection of metal compositions (e.g., noble metal) for the metal layer508results in bulk metal for each narrow metal line which still ensures low resistivity.

At operation408, the method400(FIG. 4) deposits a dielectric layer526covering sidewalls and top surfaces of the metal lines524, such as shown inFIG. 10. In some embodiments, the various material compositions of the dielectric layer526are similar to what have been discussed above with reference to the dielectric layer504inFIG. 1. Alternatively, the dielectric layer526may include a high-k dielectric material such as zirconium oxide (ZrO2). In some other embodiments, the dielectric layer526may optionally include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), or combinations thereof. A variety of suitable processes including chemical vapor depositions (CVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), and atomic layer deposition (ALD) may be used to form the dielectric layer526. A CMP process may be performed to remove excessive dielectric layer526and/or planarize a top surface of the device500. The metal lines524may function as a CMP stop layer. The resulting device500after the CMP process is shown inFIG. 11, where top surfaces of the metal lines524are exposed. The portion of dielectric layer526between ML1and ML4, may suffer more CMP loss than other portions due to the lower metal density between ML1and ML4and have a dishing profile (denoted by dotted line528). A depth of the dishing profile may range from about 0.1 nm to about 10 nm.

At operation410, the method400(FIG. 4) forms a hard mask layer530on the dielectric layer526and the metal lines524, as shown inFIG. 12. In some embodiments, the various material compositions of the hard mask layer530are similar to what have been discussed above with reference to the hard mask layer510inFIG. 7. In the illustrated embodiment, the hard mask layer530is a tri-layer hard mask, which includes a bottom layer532, a middle layer534, and a top layer536, each with different or at least independent materials. For example, the bottom layer532may include tetraethyl orthosilicate (TEOS), a nitrogen free anti-reflective coating (NFAARC) film, oxygen-doped silicon carbide (ODC), silicon carbon nitride (SiCN), or plasma-enhanced oxide (PEOx); the middle layer534may include a silicon rich polymer material (e.g., SiCxHyOz); the top layer536may include tetraethyl orthosilicate (TEOS) or silicon oxide (SiO2). It is understood that in other embodiments, one or more layers may be omitted and that additional layers may be provided as a part of the tri-layer hard mask.

The hard mask layer530may subsequently be patterned using suitable processes including double-patterning processes, multi-patterning processes, photolithography, self-aligned processes, and mandrel-spacer processes to define a pattern to be transferred to the underneath dielectric layer526to form trench-like openings to deposit metal lines therein. In the illustrated embodiment, operation410patterns the hard mask layer530in a lithography process and an etching process. A photoresist layer538is formed on the hard mask layer530using a spin-coating process and soft baking process. Then, the photoresist layer538is exposed to a radiation540. The radiation540is masked by a photomask542fabricated in a mask house130(FIG. 1) based on the sub-layout304(FIG. 3), such that only a portion of the photoresist layer538(e.g., areas538′) is exposed in the radiation520. The radiation520may be an extreme ultraviolet (EUV) radiation using a wavelength of 13.6 nm, an ultraviolet radiation using a wavelength of 436 nm, 405 nm, or 365 nm, or a DUV radiation using a wavelength of 248 nm, 193 nm, or 157 nm, or other available radiation for lithography, such as e-beam. In the case of e-beam lithography (which is maskless lithography), the “photomask” is in the form of a direct-write data pattern based on the sub-layout304(FIG. 3) rather than a physical apparatus. In the illustrated embodiment, photomask542and photomask522(FIG. 7) are of opposite types, such that opaque portions of the photomask542correspond to metal lines in sub-layout304, while transparent portions of the photomask522correspond to metal lines in sub-layout302.

Referring toFIG. 13, in the illustrated embodiment, the exposed photoresist layer538is developed using post-exposure baking (PEB), developing, and hard baking thereby forming a patterned photoresist layer538′ over the hard mask layer530. Opening in the patterned photoresist layer538′ defines a pattern of wide lines, which will be transferred to the hard mask layer530first and then to the dielectric layer526. Subsequently, the hard mask layer530is etched through the openings of the patterned photoresist layer538′, forming a patterned hard mask layer530′. The patterned photoresist layer538′ is removed thereafter using a suitable process, such as wet stripping or plasma ashing. In one example, the etching process includes applying a dry (or plasma) etch to remove the hard mask layer530within the openings of the patterned photoresist layer538′. In another example, the etching process includes applying a wet etch with a hydrofluoric acid (HF) solution to remove the hard mask layer530within the openings of the patterned photoresist layer538′.

At operation412, the method400(FIG. 4) etches the dielectric layer526using the patterned hard mask layer530′ as a mask to form trench-like openings546(also referred to as trenches546) between adjacent narrow metal lines524, as shown inFIG. 14. The etching process can include dry etching, wet etching, reactive ion etching (RIE), and/or other suitable processes. For example, a dry etching process may implement an oxygen-containing gas, a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and/or C2F6), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and/or BCl3), a bromine-containing gas (e.g., HBr and/or CHBR3), an iodine-containing gas, other suitable gases and/or plasmas, and/or combinations thereof. For example, a wet etching process may comprise etching in diluted hydrofluoric acid (DHF); potassium hydroxide (KOH) solution; ammonia; a solution containing hydrofluoric acid (HF), nitric acid (HNO3), and/or acetic acid (CH3COOH); or other suitable wet etchant. As will be explained in further detail below, the trenches546between adjacent narrow metal lines524will be subsequently filled with conductive materials, such as copper, to form wide metal lines.

At operation414, the method400(FIG. 4) forms conductive features in the trenches546as the wide metal lines in a damascene process. Referring toFIG. 15, a conductive liner layer552may be deposited prior to filling the trenches546. The conductive liner layer552is conformally over the device500as a blanket layer, and may comprise a single layer of Ta, TaN, WnN, TiN, or any combinations thereof. The conductive liner layer may be typically used as a barrier layer for preventing the conductive material such as copper from diffusing into the neighboring dielectric layer526and the underlying substrate. The conductive liner layer552may be deposited by using suitable deposition process such as CVD, PVD, atomic layer deposition (ALD), or other suitable methods. The conductive liner layer552may have a thickness in a range from about 5 Å to about 35 Å. Optionally, operation414may form an adhesion layer554conformally over the conductive liner layer552as a blanket layer, and may comprise a single layer of Co, Mn, Ti, Ru, Ir, or any combination thereof. The adhesion layer may be formed by suitable deposition techniques such as PVD, CVD and/or the like. The adhesion layer may have a thickness in a range from about 5 Å to about 35 Å. In addition, the adhesion layer554may be alloyed with a material that improves the adhesive properties of the seed layer so that it can act as an adhesion layer. For example, the adhesion layer554may be alloyed with a material such as manganese or aluminum, which will migrate to the interface between the adhesion layer554and the conductive liner layer552and will enhance the adhesion between these two layers. The alloying material may be introduced during formation of the adhesion layer554. The alloying material may comprise no more than about 10% of the adhesion layer554.

Operation414subsequently fill a conductive material in the trenches546and cover the device300as a bulk metal layer556. The conductive material may be deposited through suitable techniques such as an electroplating process, PVD, or other suitable methods. One advantageous feature of having the bulk metal layer556formed in a damascene process shown is that the conductive material (e.g., Copper) selected may not otherwise be suitable for metal etching. In comparison with conventional etching-based techniques, the total production time of the semiconductor device is reduced. Moreover, without an etching process commonly used in the traditional fabrication process, the resolution of metal lines may be improved. In various embodiments, the conductive material is different from the metal used in the narrow metal lines524. In some embodiments, the narrow metal lines524includes one or more noble metals as discussed above, while the bulk metal layer556includes one or more non-noble metals. For example, the bulk metal layer556may include copper (Cu), although other suitable materials such as cobalt (Co), Nickel (Ni), Silver (Ag), aluminum (Al), combinations thereof, and/or the like, may alternatively be utilized. In some embodiments, the bulk metal layer556also includes a noble metal but different from the one used in the narrow metal lines524. For example, the bulk metal layer556may include Pt, while the narrow metal lines524may include Ru, Ir, or Rh. In some alternative embodiments, the narrow metal lines524and the bulk metal layer556both include non-noble, but indecently different, metals. For example, the narrow metal lines524may include Mo or W, while the bulk metal layer556may include Cu.

A CMP process is then performed to remove excess conductive materials from the top portion of the bulk metal layer556. The conductive liner layer552and the adhesion layer554are also removed from above the narrow metal lines524, such that narrow metal lines524are exposed. The remaining portion of the bulk metal layer556in the trenches546together with the surrounding conductive liner layer552and the adhesion layer554form the wide metal lines558, such as the metal lines ML2and ML3in the illustrated embodiment. In some embodiments, a top surface of the wide metal lines558is configured to have a dishing profile (or a recess)560. In other words, instead of planarizing the top surface of the wide metal lines558, the CMP process may form a recess (the dishing profile560) in the wide metal lines558(e.g., in the bulk metal layer556) such that its top surface is not leveled with the top surface of the rest of the device500(e.g., the dielectric layer526). While the removal of the conductive materials from above the top surface of the wide metal lines558may be controlled by the duration of the polishing process, the formation of the dishing profile560may be controlled by actions of various chemical agents in a CMP slurry configured to tune the removal selectivity of one or more materials. Stated yet another way, the CMP process may be tuned to remove portions of the conductive material in the wide metal lines558at a higher rate than its surrounding components. The dishing profile560may have a depth from about zero (planarization) to about 10% of a height of the wide metal lines558(which substantially equals to the height of the narrow metal lines524), such as ranging from about 0 Å to about 60 Å in some embodiments.

Referring toFIGS. 18 and 19collectively, in some embodiments, the substrate502includes one or more underlying conductive features580in its top portion, and operations412and414may further include processes to open the etch stop layer506and to extend openings546downwardly into the dielectric layer504to form wide metal lines and vias that land on the underlying conductive features580. The underlying conductive feature580is a metal feature, such as a metal line, a metal via, or a metal contact feature. In some embodiments, the underlying conductive feature580includes both a metal line and a metal via, formed by a suitable procedure, such as dual damascene process, or other suitable process including atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), electroless metal deposition (ELD), or electrochemical plating (ECP) process. The material of the underlying conductive feature580may include copper (Cu) or copper alloys. Alternatively, it may also be formed of, or comprise, other conductive materials, such as Nickel (Ni), Cobalt (Co), Ruthenium (Ru), Iridium (Ir), Aluminum (Al), Platinum (Pt), Palladium (Pd), Gold (Au), Silver (Ag), Osmium (Os), Tungsten (W), and the like. The steps for forming the underlying conductive feature580may include forming a damascene opening in the substrate502, forming a diffusion barrier layer in the opening, depositing an adhesion layer, and filling the opening, for example, in an electroplating process.

Operation412may extend the openings546downwardly into the dielectric layer504through one or more etching processes, where the openings546is at least partially aligned with the underlying conductive features580. In the illustrated embodiment, the openings546include the trench openings546′ and the via openings546″. Operation412includes an etching process to remove a portion of the etch stop layer506from the bottom of the trench openings546′ and expose the dielectric layer504. The formation of the via openings546″ may be assisted by photoresist for defining patterns. Photoresist is then removed in a suitable process such as resist stripping or plasma ashing. Operation414subsequently fills the openings546with conductive materials, thereby forming wide metal lines558connecting with the underlying conductive features580through via structures therebetween. A CMP process is then performed to remove excess materials. The remaining portion of the wide metal lines558may include a dishing profile560as shown inFIG. 19, which is similar to what has been discussed above in association withFIG. 17.

In some embodiments, the underlying conductive feature580alternatively can be other conductive features. In some embodiments, the underlying conductive feature580is a capacitor, or resistor. In some embodiments, the underlying conductive feature580is a gate electrode or a source/drain (S/D) contact. Referring toFIG. 20, in the illustrated embodiment, underlying conductive feature580is a S/D contact (referred to as the S/D contact580hereinafter). Operation412opens the etching stop layer506and exposes a top portion of the S/D contact580. Wide metal lines558thereafter land on the S/D contact580and provide electrical routing for the respective transistors underneath to connect with other portions of the integrated circuit.

Still referring toFIG. 20, the device500includes an active region582. In some embodiments, the active region582includes a plurality of fins extending away from a top surface of the substrate502. As such, the active region582is said to provide at least one FinFET. Alternatively, the active region582may provide planar FETs. The active region582may include silicon or another elementary semiconductor, such as germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and/or GaInAsP; or combinations thereof. The active region582may be doped with an n-type dopant or a p-type dopant for forming p-type FET and n-type FET, respectively. If including fins, the active region582may be formed using double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers, or mandrels, may then be used to pattern the fins.

The device500further includes source/drain (S/D) features584disposed in the active region582, a metal gate stack586disposed adjacent the S/D features584, and S/D contacts580disposed over the S/D features584and in an interlayer dielectric (ILD) layer588. In many embodiments, the S/D features584may be suitable for a p-type FET device (e.g., a p-type epitaxial material) or alternatively, an n-type FET device (e.g., an n-type epitaxial material). The p-type epitaxial material may include one or more epitaxial layers of silicon germanium (epi SiGe), where the silicon germanium is doped with a p-type dopant such as boron, germanium, indium, and/or other p-type dopants. The n-type epitaxial material may include one or more epitaxial layers of silicon (epi Si) or silicon carbon (epi SiC), where the silicon or silicon carbon is doped with an n-type dopant such as arsenic, phosphorus, and/or other n-type dopants. The S/D features584may be formed by any suitable techniques, such as etching processes followed by one or more epitaxy processes.

Though not depicted, the metal gate stack586may include a plurality of material layers, such as a high-k dielectric layer and a gate electrode disposed over the high-k dielectric layer. The metal gate stack18may further include other material layers, such as an interfacial layer, barrier layers, hard mask layers, other suitable layers, or combinations thereof. The high-k dielectric layer may include a dielectric material having a high dielectric constant, for example, greater than that of thermal silicon oxide (˜3.9). In one example, the high-k dielectric layer may include a high-K dielectric layer such as hafnium oxide (HfO2). The gate electrode may include at least one work-function metal (WFM) layer and a bulk conductive layer. The gate electrode may include Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, Al, WN, Cu, W, Re, Ir, Co, Ni, other suitable metal materials or a combination thereof. Various layers of the metal gate stack18may be formed by any suitable method, such as chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), plating, other suitable methods, or combinations thereof. A polishing process (e.g., CMP) may be performed to remove excess materials from a top surface of the metal gate stack to planarize a top surface of the metal gate stack586.

In various embodiments, the device500further includes gate spacers590disposed on sidewalls of the metal gate stacks586. The gate spacers590may include a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, other suitable dielectric materials, or combinations thereof. The gate spacers590may be formed by first depositing a blanket of spacer material over the device500, and then performing an anisotropic etching process to remove portions of the spacer material to form the gate spacers590on the sidewalls of the metal gate stacks586.

The S/D contacts580disposed in the ILD layer588and physically contacting the S/D features584. The S/D contacts580are configured to connect the S/D features584with subsequently formed interconnect structures, such as vias and conductive lines. In many embodiments, the S/D contacts580includes a conductive material such as Cu, W, Ru, Mo, Al, Co, Ni, Mn, Ag, other suitable conductive materials, or combinations thereof. The S/D contacts580may be formed by first patterning the ILD layer588to form trenches (not depicted) to expose the S/D features584, and depositing the conductive material by CVD, PVD, ALD, plating, other suitable methods, or combinations thereof to form the S/D contacts580. In many embodiments, the ILD layer588is substantially similar to the dielectric layer504in composition and may be formed by any suitable method as discussed above. In a specific example, the ILD layer588includes a porous low-k dielectric material such as carbon-doped silicon oxide having a porosity of about 1% to about 8%.

Although not intended to be limiting, one or more embodiments of the present disclosure provide many benefits to a semiconductor device and the formation thereof. For example, embodiments of the present disclosure provide a hybrid method that combines metal etching process and damascene process, and a resulting novel interconnect structure that includes narrow metal lines formed by a noble metal (or other suitable metal) through a metal etching process and relatively wider metal lines formed by copper (or other suitable metal) through damascene process. The conductivity of interconnection layers is improved even at the minimum metal line width. Furthermore, the hybrid method for forming interconnect structures can be easily integrated into existing semiconductor fabrication processes.

In one exemplary aspect, the present disclosure is directed to a method. The method includes providing a device having a substrate, a first dielectric layer over the substrate, and a first conductive feature over the first dielectric layer, the first conductive feature comprising a first metal, the first metal being a noble metal; depositing a second dielectric layer over the first dielectric layer and covering at least sidewalls of the first conductive feature; etching the second dielectric layer to form a trench; and forming a second conductive feature in the trench, wherein the second conductive feature comprises a second metal different from the first metal. In some embodiments, the second metal is a non-noble metal. In some embodiments, the first metal is selected from: Ru, Ir, Rh, and Pt, and the second metal is selected from Cu, Co, Ni, Ag, and Al. In some embodiments, the forming of the second conductive feature includes depositing the second conductive feature in the trench and over the first conductive feature and planarizing the second conductive feature to remove a top portion of the second conductive feature over the first conductive feature, thereby exposing the first conductive feature. In some embodiments, after the planarizing of the second conductive feature, a top surface of the second conductive feature has a dishing profile. In some embodiments, the first conductive feature has a first width, and the trench has a second width larger than the first width. In some embodiments, a ratio of the second width over the first width is at least 2.5. In some embodiments, the depositing of the second conductive feature includes depositing a liner layer in the trench and forming a bulk metal layer over the liner layer, wherein the bulk metal layer comprises the second metal. In some embodiments, the device includes a third conductive feature between the substrate and the first dielectric layer, and the third conductive feature is in direct contact with a bottom surface of the first dielectric layer. In some embodiments, the method further includes etching the first dielectric layer to extend the trench downwardly to expose the third conductive feature, where a bottom portion of the second conductive feature lands on the third conductive feature.

In another exemplary aspect, the present disclosure is directed to a method. The method includes providing a substrate; forming a metal layer over the substrate, the metal layer comprising a first metal; patterning the metal layer to form metal lines in an etching process; forming a dielectric layer covering at least sidewalls of the metal lines; recessing the dielectric layer to form a trench between two adjacent metal lines, the trench having a width larger than any of the metal lines; and forming a conductive feature in the trench, the conductive feature comprising a second metal different from the first metal. In some embodiments, the first metal is a noble metal and the second metal is a non-noble metal. In some embodiments, the first metal is selected from: Ru, Ir, Rh, Pt, Co, Mo, and W, and the second metal is selected from Cu, Co, Ni, Ag, and Al. In some embodiments, the etching process includes reactive-ion etching. In some embodiments, the forming of the conductive feature includes a damascene process. In some embodiments, prior to the recessing of the dielectric layer, the method further includes planarizing the dielectric layer to expose the metal lines; forming a hard mask layer covering the dielectric layer and the metal lines; and patterning the hard mark layer to form an opening above the dielectric layer, wherein the recessing of the dielectric layer is performed through the opening. In some embodiments, the forming of the conductive feature includes depositing the conductive feature over the hard mask layer and the metal lines. In some embodiments, the forming of the metal layer includes a physical vapor deposition (PVD) process or a chemical vapor deposition (CVD) process.

In yet another exemplary aspect, the present disclosure is directed to a semiconductor structure. The semiconductor structure includes a substrate and an interconnect layer over the substrate. The interconnect layer includes a dielectric layer, a first conductive feature disposed in the dielectric layer, wherein the first conductive feature has a first width, and wherein the first conductive feature comprises a first metal, and a second conductive feature disposed in the dielectric layer. The second conductive feature has a second width larger than the first width. The second conductive feature includes a second metal different from the first metal and wherein the first and second conductive feature have substantially the same height. In some embodiments, the first metal is a noble metal and the second metal is a non-noble metal. In some embodiments, the first metal is selected from: Ru, Ir, Rh, and Pt, and the second metal is selected from Cu, Co, Ni, Ag, and Al.