Real-time address switching circuit

A real-time address switching circuit is adapted for effecting a DRAM multiple-bits parallel test. The real-time address switching circuit includes selectors for effecting the pattern selection for the AX AY addresses to be added to a device under test, a gate for controlling the selectors at the real time, a register for latching the data bit size data and a multiplexer for receiving the outputs of the selectors and switching the AX AY addresses.

BACKGROUND OF THE INVENTION 
The present invention relates to a real time address switching circuit, 
more particularly to an address signal generation system and circuit for 
adding the address signal to a DRAM when DRAM multiple-bits parallel test 
is carried out on the basis of a 4 MDRAM multiple-bits parallel test 
system adopted by JEDEC (Joint Electron Device Engineering Council) held 
on April, 1987. 
The system adopted by JEDEC is disclosed in the magazine entitled "NIKKEI 
MICRODEVICES" Separate Volume No. 1, published on May of 1987. 
For performing the 4 MDRAM multiple-bits paralell test system (.times.4, 
.times.8, .times.16 parallel bits) adopted by JEDEC, it is necesary to 
automatically switch to the multiple-bits parallel test mode and 
automatically control addresses to be added to a DRAM under test on the 
basis of the mutiple-bits parallel test mode. The number of the data bits 
at the multiple-bits parallel test mode operation increases 2.sup.n as 
many as that at the time of normal mode operation. 
It is necessary to reduce the device address to 1/2.sup.n in response to 
the change of the number of the data bits. 
SUMMARY OF THE INVENTION 
It is an object of the present invention to provide a real-time address 
switching circuit capable of reducing device address to 1/2.sup.n in 
response to the change of the number of data bits and also capable of 
effecting DRAM multiple bits parallel test. 
To achieve the above object, a real-time address switching circuit 
according to the present invention comprises a register 1 for latching a 
data bit size data, a gate 2 for receiving an output of the register 1 and 
a real-time control signal, a first selector 3 for effecting pattern 
selection for an AX address 14 to be added to a device under test 
(hereinafter referred to as DUT) 6 on the basis of the output of the gate 
2, a second selector 4 for effecting pattern selection for an AY address 
15 to be added to the DUT 6 on the basis of the output of the gate 2, and 
a multiplexer 5 for receiving an output of the first selector 3 and an 
output of the second selector 4, and switching data of the selected AX 
address 14 or AY address 15 to its output. 
The above and other objects, features and advantages of the present 
invention will become more apparent from the following description taken 
in conjunction with the accompanying drawings.

PREFERRED EMBODIMENT OF THE INVENTION 
Before describing a real-time address switching circuit of the present 
invention, address signals of DRAM will be first described with reference 
to FIG. 3. 
The addresses of AX AY address are added to the DRAM by time sharing. 
The AX AY addresses are normally memory address bits and added in response 
to the address bits A.sub.0, A.sub.1 ... A.sub.n, such as AX.sub.0, 
AY.sub.0 ... A.sub.n and AX.sub.1, AY.sub.1 ... AY.sub.n 
However, in case of a multiple-bits test, the depth of the memory address 
is reduced to 1/4, 1/8 and 1/16 in response to 4 bits, 8 bits and 16 bits 
of the DUT. 
Accompanied by the reduction of the depth of the address, there is a 
likelihood that the address unnecessitating the AX AY addresses to be 
added to the memory is present. Under the circumstances, when the multibit 
test is made, it is necessary to control the AX AY address to be added in 
response to each data bit size. 
In case of testing the multiple-bits parallel test of the DRAM, there are 
methods for writing in the normal mode and reading by the multiple-bits 
parallel test mode, or writing by the multiple-bits parallel test mode and 
reading by the normal mode or writing and reading by multi-bits parallel 
test mode. In carrying out these methods, it is necessary to automatically 
control the switching to the normal mode or the mutiple-bits parallel test 
mode and the address control due to the reduction of the address at the 
real-time. 
An arrangement of the real-time address switching circuit according to the 
preferred embodiment of the present invention will be described with 
reference to FIGS. 1 and 2. 
In FIG. 1, designated at 1 is a register, 2 is a gate, 3 is a first 
selector, 4 is a second selector, 5 is a multiplexer and 6 is a device 
under test (DUT). 
In the register 1, there is set a data bit size data for testing 
multiple-bits size data such as data for 4 bits, 8 bits and 16 bits. 
The normal mode and the multiple-bits parallel test mode are switched at 
real-time. 
The first selector 3 selects an AX address 14 to be added to the DUT 6 when 
the multiple-bits parallel test is carried out. 
The second selector 4 selects an AY address 15 to be added to the DUT 6 
when multiple-bits parallel test is carried out. 
The multiplexer 5 receives output signals 16 and 17 from the first and 
second selectors and switches data of the selected AX address 14 or AY 
address 15 to its output. 
The real-time address switching circuit having the arrangement set forth 
above will be operated as follows. 
The register 1 receives the data bit size data from a CPU PG serving as an 
exerciser for effecting multiple-bits parallel test and setting and 
delivering it to the gate 2 as signals 11. The signals 11 are data for 
switching the first selector 3 or the second selector 4 for effecting the 
mulitiple-bits parallel test. The signals 11 are issued by the exercizer 
(PG). 
The gate 2 receives the signals 11 at one input thereof and a real-time 
control signal 12 at the other input thereof. Both the signals 11 and 12 
are ANDed at the gate 2 for producing output signals 13. The normal mode 
and the multiple-bits parallel test mode are switched at the real-time by 
the control singal 12. 
The output signals 13 produced by the gate 2 become selection signals of 
the first and second selectors 3 and 4 for adding AX.sub.0 to AX.sub.n and 
AY.sub.O to AY.sub.n to the first and second selectors 3 and 4 
corresponding to the address bits A.sub.0 to A.sub.n of the DUT 6 at the 
normal mode. 
The gate 2 outputs the signals 11 received from the register 1 at the 
muliple-bits parallel test mode. The output signals 13 output by the gate 
2 become the selector data of the first and second selectors 3 and 4 so as 
to add the addresses corresponding to the data bit sizes to the DUT 6. 
Address control circuits of the first and second selectors 3 and 4 each 
comprises multiple-bits selectors of AX.sub.0 to AX.sub.n and AY.sub.0 to 
AY.sub.n. 
Signals 16 selected by the first selector 3 and signals 17 selected by the 
second selector 4 are supplied to the multiplexer 5. The multiplexer 5 is 
multiplexed at time sharing upon reception of a real-time control signal 
18 supplied by the exercizer. The multiplexer 5 outputs the address bits 
A.sub.0 to A.sub.n which are supplied to the DUT 6. 
The operation of the real-time address circuit will be described with 
reference to the timing chart in FIG. 2. 
FIG. 2(a) shows a waveform of the signal 11 and FIG. 2(b) is a waveform of 
the signal 12. The signal 12 comprises the normal mode and the 
mutiple-bits test mode. FIG. 2(c) is a waveform of the output signal 13 
and forms a normal select data and the signal 11 in response to the signal 
11. FIG. 2(d) is a waveform of the AX address signal 14 and forms 
AX.sub.0. FIG. 2(e) is a waveform of the signel 16 and forms AY.sub.0. 
FIG. 2(f) is a waveform of the signal 16 and forms AX.sub.0 at both the 
normal mode and the multiple-bits parallel test mode. FIG. 2(g) is a 
waveform of the signal 17. The signal 17 forms AY.sub.0 at the normal mode 
and "0"at the multiple-bits parallel test mode. FIG. 2(h) is a waveform of 
the signal 18. FIGS. 2(i) to FIG. 2(m) are waveforms to be supplied from 
the multiplexer 5 to the DUT 6. 
The AX AY patterns to be added to the DUT 6 at the normal mode and the 
multiple-bits parallel test mode and the 4 MDRAM 8 bits data bit size are 
listed as follows. 
______________________________________ 
P Q1 Q2 R1 R2 
______________________________________ 
A.sub.0 AX.sub.0 AY.sub.0 AX.sub.0 
-- 
A.sub.1 AX.sub.1 AY.sub.1 AX.sub.1 
AY.sub.0 
A.sub.2 AX.sub.2 AY.sub.2 AX.sub.2 
AY.sub.1 
A.sub.3 AX.sub.3 AY.sub.3 AX.sub.3 
AY.sub.2 
A.sub.4 AX.sub.4 AY.sub.4 AX.sub.4 
AY.sub.3 
A.sub.5 AX.sub.5 AY.sub.5 AX.sub.5 
AY.sub.4 
A.sub.6 AX.sub.6 AY.sub.6 AX.sub.6 
AY.sub.5 
A.sub.7 AX.sub.7 AY.sub.7 AX.sub.7 
AY.sub.6 
A.sub.8 AX.sub.8 AY.sub.8 AX.sub.8 
AY.sub.7 
A.sub.9 AX.sub.9 AY.sub.9 AX.sub.9 
AY.sub.8 
A.sub.10 AX.sub.10 AY.sub.10 
-- -- 
______________________________________ 
This table shows addresses to be added to the DUT 6 at the 4 DRAM 8 bits 
parallel test in which P column shows device addresses, Q1 and Q2 columns 
show addresses at normal mode, and R1 and R2 columns show addresses at 
multiple-bits parallel test mode. 
Inasmuch as the present invention is provided with the selectors 3 and 4 
for subjecting the pattern selection for the AX AY addresses to be added 
to the DUT 6, a gate for controlling the selectors at the real time, a 
register 1 for latching the data bit size data and a multiplexer 5 for 
receiving the outputs of the selectors 3 and 4 and switching the AX AY 
addresses, it is possible to effect the DRAM multiple-bits parallel mode 
test. 
Although the invention has been described in its preferred form with a 
certain degree of paticularity, it is to be understood that many 
variations and changes are possible in the invention without departing 
from the scope thereof.