Asymmetry correction for magneto-resistive heads

An asymmetry-reducing circuit adapted to process an input signal having positive and negative pulses of different amplitudes and generate a corresponding balanced signal having positive and negative pulses of substantially uniform amplitudes. The asymmetry-reducing circuit balances the input signal by providing signal contributions corresponding to the second and third orders of the input signal. In a representative embodiment, the asymmetry-reducing circuit includes a differential amplifier and a plurality of arrayed MOS transistors connected to its inputs and outputs such that source-to-drain conductance of the transistors provides input and feedback resistances to the amplifier. A switch set selectively couples the fingers (gates) of the transistors to the input signal to modulate the source-to-drain conductance with said signal such that the input and feedback resistances change in a complementary manner. Advantageously, circuits of the invention can correct signal asymmetry within a relatively wide asymmetry range.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to magnetic disk drives and, more specifically, to signal processing circuits for magneto-resistive (MR) heads.

2. Description of the Related Art

The principle of operation of MR heads is based on the ability of metals to change their resistance in the presence of a magnetic field. A typical MR head has an MR element composed of a thin film (e.g., about 250 nm in thickness) of Ni—Fe alloy, also called permalloy, which converts magnetic field variations at the surface of a magnetic storage medium (e.g., a magnetic platter) into resistance variations. The resistance variations are then converted into a differential voltage swing at the output of the MR head.

MR technology solves numerous problems associated with magneto-inductive heads, such as the dependence of signal amplitude on the rotational speed of the magnetic disk. However, MR heads have created new challenges for disk drive designers. One problem is the asymmetry in the response of a biased MR element to magnetic flux changes of opposite polarity. As a result, positive and negative pulses in the output signal of the MR head have different amplitudes, which impairs both servo and read channel performance in the disk drive.

SUMMARY OF THE INVENTION

Problems in the prior art are addressed, in accordance with the principles of the present invention, by an asymmetry-reducing circuit adapted to process an input signal having positive and negative pulses of different amplitudes and generate a corresponding balanced signal having positive and negative pulses of substantially uniform amplitudes. The asymmetry-reducing circuit balances the input signal by providing signal contributions corresponding to the second and third orders of the input signal. In a representative embodiment, the asymmetry-reducing circuit includes a differential amplifier and a plurality of arrayed MOS transistors connected to its inputs and outputs such that source-to-drain conductance of the transistors provides input and feedback resistances to the amplifier. A switch set selectively couples the fingers (gates) of the transistors to the input signal to modulate the source-to-drain conductance with said signal such that the input and feedback resistances change in a complementary manner. Advantageously, circuits of the invention can correct signal asymmetry within a relatively wide asymmetry range.

DETAILED DESCRIPTION

Reference herein to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the invention. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments.

FIG. 1shows a block diagram of an exemplary disk drive100, in which the present invention can be practiced. Disk drive100is coupled to a host device, e.g., a computer, and includes one or more magnetic platters102mounted on a spindle motor (not shown), one or more read/write heads104mounted on an actuator assembly124, amplifiers106, a read/write channel108, and a controller110. Read/write channel108is coupled via interfaces114and116to amplifiers106and via interfaces118and120to controller110. For clarity, certain components of disk drive100, e.g., the servo/actuator motor control, are not shown inFIG. 1.

To read from disk drive100, the host device provides to controller110a location identifier for the data to be retrieved. Based on the location identifier, controller110determines the actual physical location, e.g., the cylinder and sector, corresponding to the data on platters102. Controller110then generates an appropriate control signal for actuator assembly124to position read/write heads104such that they can access that physical location. With read/write heads104in the proper position, platters102are spun under the heads, which causes each head to generate an analog signal corresponding to the magnetic flux reversals representing data on the platters. The analog signal is then amplified in amplifiers106and applied via interface114to read/write channel108. As will be discussed in more detail below, read/write channel108decodes the amplified signal and converts it into a digital binary signal that is passed via interface118to controller110. Controller110may apply additional processing, e.g., caching and error detection/correction, to the data carried by the binary signal before providing the data to the host device. The additional processing is usually intended to increase the operating speed and/or reliability of disk drive100.

To write to disk drive100, the host device provides to controller110data to be stored along with a location identifier to be used. Based on the location identifier, controller110generates an appropriate control signal for actuator assembly124to properly position read/write heads104. Controller110then sends the data via interface120to read/write channel108. Read/write channel108encodes the data and generates an appropriate analog signal that is applied via interface116and amplifiers106to read/write heads104. With read/write heads104in the proper position, platters102are spun under the heads, which causes each head to impart magnetic flux reversals corresponding to the data onto the platters.

FIG. 2shows a block diagram of a read/write channel208that can be used as read/write channel108in disk drive100. Read/write channel208has a read path220and a write path250. During a read operation, read path220converts analog signals received from the MR heads via interface114into the corresponding binary digital data that are output from read/write channel208via interface118. Similarly, during a write operation, write path250converts binary digital data received from the host device via interface120into the corresponding analog signals that are output from read/write channel208via interface116and used to impart magnetic flux reversals onto magnetic platters. Read/write channel208also has a clock synthesizer270adapted to generate clock signals for the read and write paths. In one embodiment, read/write channel208is adapted to support Partial Response Maximum Likelihood (PRML) coding and is implemented in an integrated circuit manufactured using a complementary metal oxide semiconductor (CMOS) process.

Write path250includes a parallel-to-serial converter252, a run-length-limited (RLL) encoder254, a parity encoder256, a write pre-compensation circuit258, and a driver circuit260. Parallel-to-serial converter252receives a parallel stream of data, e.g., eight bits per clock cycle, via interface120, converts the parallel stream into a serial stream, and sends the serial stream to RLL encoder254. RLL encoder254encodes the serial stream into symbolic binary sequences according to a known RLL algorithm. An exemplary RLL algorithm uses a 32/33-bit symbol code designed to ensure that flux reversals on the magnetic platter are optimally spaced and that long runs of data without flux reversals are avoided. The RLL-encoded data are then passed to parity encoder256configured to add parity bits to the data and convert the parity-encoded data into a corresponding analog signal. The analog signal is then applied to write pre-compensation circuit258, which dynamically adjusts pulse widths/amplitudes in the analog signal to pre-compensate for signal distortions produced during the recording process. The adjusted analog signal is passed to driver circuit260, which drives the read/write heads via interface116. In one embodiment, driver circuit260is a pseudo emitter-coupled logic (PECL) driver circuit adapted to generate a differential output signal.

Read path220includes an attenuation circuit (input resistance)222, a variable-gain amplifier (VGA)224, a magneto-resistive asymmetry (MRA)-correcting circuit226, a continuous time filter (CTF)228, a buffer230, an analog-to-digital converter (ADC)232, a finite impulse response (FIR) filter234, an interpolated timing recovery (ITR) circuit236, a Viterbi detector238, a parity decoder240, and a run-length-limited (RLL) decoder242. An amplified signal received via interface114from the read/write head is first passed through circuit222serving signal attenuation and impedance matching purposes. The output of circuit222is then coupled to VGA224configured to adjust the signal amplitude for further signal processing. The adjusted signal is applied to MRA circuit226designed to reduce signal imbalance present due to the magneto-resistive asymmetry effects in the read/write head. More details on the principles of operation and structure of MRA circuit226are given below.

The output of MRA circuit226is applied to CTF228to attenuate high-frequency noise and minimize aliasing into the baseband after sampling. ADC232receives, via buffer230, the signal filtered by CTF228, samples it, and converts it into a digital form. The digital signal is passed to FIR filter234(e.g., a 10-tap FIR filter) and timing recovery circuit236. Timing recovery circuit236is connected in a feedback arrangement (not shown inFIG. 2) to FIR filter234, MRA circuit226, and VGA224to provide appropriate timing correction based on the frequency of the signal being processed. The digital signal is then applied to Viterbi detector238adapted to determine the binary bit pattern represented by the signal using a Viterbi algorithm. Parity decoder240then removes the parity bit from the determined bit pattern and RLL decoder242converts the result into a serial bit stream by applying a reverse run-length limited algorithm. The serial bit stream is then converted into a parallel stream (not shown) and output from read path220via interface118.

The analog signal applied to read path220is essentially a series of alternating positive and negative voltage pulses. In an ideal situation, pulses of different polarity would have identical shapes/amplitudes, i.e. the shape of each pulse would be described by the time domain function P(t)=bh(t), where h(t) is a function determining the pulse shape and b=±1 is a coefficient determining the pulse polarity. However, in practice, non-linear effects affecting the response of MR heads cause the amplitudes of positive and negative pulses to differ and vary across the pulse sequence. As already mentioned, this pulse disparity/variation adversely affects the performance of disk drives. MRA circuit226is designed to deal with this problem by reducing said pulse disparity/variation and providing a signal having pulses of substantially uniform amplitudes across the pulse sequence.

FIG. 3shows a block diagram of a prior-art MRA circuit326disclosed in U.S. Pat. No. 6,633,447, the teachings of which are incorporated herein by reference, which circuit can be used as MRA circuit226in read/write channel208. MRA circuit326is adapted to operate in conjunction with an MR head having substantially the following transfer function:
z(t)=x(t)+αx(t)2(1)
where x(t) and z(t) are the input and output signals, respectively, of the MR head at time t, and α is a coefficient. For relatively small values of α, the original non-distorted signal x(t) can be recovered from the output signal z(t) using the following second-order approximation:
y(t)=z(t)−αz(t)2(2)
where y(t) represents an approximated value of x(t).

MRA circuit326is a mixer circuit that implements Eq. (2) to balance pulse amplitudes and, therefore, improve the operation of the disk drive. In MRA circuit326, signal z(t) received from, e.g., VGA224(FIG. 2), is sent along two different signal paths labeled302and304inFIG. 3. Signal path304includes (I) a square-term generator306adapted to square the applied signal and (II) a linear multiplier308adapted to multiply the output of the square-term generator by a constant (a). In a preferred configuration a=−α. A summation circuit310then adds the signals received via the two signal paths to generate balanced signal y(t), in which the pulse imbalance induced by the MR head is reduced.

One problem with MRA circuit326is that it can correct signal asymmetry only within a relatively narrow asymmetry range. Range limitations are due to the fact that the second-order approximation given by Eq. (2) breaks down at relatively high signal asymmetry, i.e., at a relatively large value of α. The breakdown manifests itself, for example, by the fact that, at certain α, signal y(t) produced in accordance with Eq. (2) acquires a different polarity than signal z(t), which is an obviously incorrect result. The present invention deals with this problem by using a higher-order approximation than that of Eq. (2). More specifically, in addition to the second-order correction term, certain embodiments of the invention provide a third-order correction term and, optionally, other high-order correction terms, which is generalized by Eq. (3a) as follows:
y(t)=z(t)+b2z(t)2+b3z(t)3+O(z(t)4)  (3a)
where O(z(t)4) represents a sum of the optional high-order terms starting with the fourth order, and b2and b3are constants. In a preferred embodiment, the following constant values are used:

b2=-α(3⁢b)b3=α22(3⁢c)
One skilled in the art will appreciate that the approximation given by Eqs. (3a–c) holds for a wider range of α values than the approximation of Eq. (2). As a result, MRA circuits of the invention that implement Eq. (3) can correct signal asymmetry within a relatively wide asymmetry range.

FIG. 4shows a block diagram of an MRA circuit426that can be used as MRA circuit226in read/write channel208according to one embodiment of the present invention. MRA circuit426has two cascaded circuits326a–b. More specifically, signal z(t) applied to MRA circuit426, e.g., by VGA224(FIG. 2), is applied to MRA circuit326a, the output of which is then applied to MRA circuit326bto generate balanced signal y(t). Assuming that the multiplication constant (a) of each of linear multipliers308a–bis −c/2, where c is a constant, the transfer function of MRA circuit426is given by Eq. (4) as follows:

y⁡(t)=z⁡(t)-c⁢⁢z⁡(t)2+c22⁢z⁡(t)3-c38⁢z⁡(t)4(4)
Comparing Eqs. (3) and (4), one finds that Eq. (4) is a species of Eq. (3), wherein α=c and O(Z(t)4) is truncated at the fourth-order term.

FIG. 5shows a block diagram of an MRA circuit526that can be used as MRA circuit226in read/write channel208according to another embodiment of the present invention. MRA circuit526is substantially a variable-gain amplifier. Signal z(t) applied to MRA circuit526, e.g., by VGA224(FIG. 2), is sent along two signal paths labeled502and504inFIG. 4. Signal path504has (I) a linear multiplier508that is similar to linear multiplier308(FIG. 3) and (II) an exponential-term generator512adapted to generate an output signal having an amplitude substantially equal to the exponent of the input signal. A multiplier circuit514multiplies the signals received via the two paths to generate balanced signal y(t). Assuming that the multiplication constant of linear multiplier508is −c, the transfer function of MRA circuit526is given by Eq. (5) as follows:

y⁡(t)=z⁡(t)⁢⁢exp⁡(-c⁢⁢z⁡(t))=z⁡(t)-c⁢⁢z⁡(t)2+c22⁢z⁡(t)3-c36⁢z⁡(t)4+…(5)
Similar to Eq. (4), Eq. (5) is a species of Eqs. (3a–c), wherein α=c and O(Z(t)4) corresponds to the residual sum of a Taylor expansion series of the exponent.

FIG. 6shows a block diagram of an MRA circuit626that can be used as MRA circuit226in read/write channel208according to yet another embodiment of the present invention. MRA circuit626is a differential variable-gain amplifier, which has two differential inputs, each input receiving a copy of input signal z(t) of appropriate polarity, and two differential outputs, each output having a copy of output signal y(t) of appropriate polarity. MRA circuit626includes a differential amplifier602in an inverting gain configuration whose gain is controlled by four MOS devices604n,604p,606n, and606p. Each MOS device604is an arrayed MOS transistor having a source (S), a drain (D), and a plurality of fingers (gates, G), each of which fingers controls a conducting channel between the source and the drain. Each MOS device604is connected to differential amplifier602such that its source-to-drain conductance provides an input resistance to the differential amplifier. More specifically, the source of each MOS device604receives, via the corresponding source follower610a, input signal z(t) of appropriate polarity while its drain is connected to the appropriate input of differential amplifier602. Similarly, each MOS device606is an arrayed MOS transistor having a source (S), a drain (D), and a plurality of fingers (gates, G), each of which fingers controls a conducting channel between the source and the drain. Each MOS device606is connected to differential amplifier602such that its source-to-drain conductance provides a feedback resistance to the differential amplifier. The source of each MOS device606receives, via the corresponding source follower610b, output signal y(t) of appropriate polarity while its drain is connected to the drain of the corresponding MOS device604and to the corresponding input of differential amplifier602.

The conductance between the source and the drain of each MOS device604and606is controlled by m (where, m>1) fingers (gates), each of which can be biased independent of other fingers. Switch sets614and616, each controlled by a multi-bit (e.g., n-bit, where n>1) control signal612, can couple each finger to the positive or negative input of MRA circuit626. A representative circuit for generating control signal612is disclosed in U.S. Pat. No. 6,587,292, the teachings of which are incorporated herein by reference. Briefly, the circuit for generating multi-bit control signal612estimates an asymmetry error in the signal generated by the MR head coupled to MRA circuit626(e.g., read/write head104ofFIG. 1), which provides an estimate for the value of α (see Eq. (1)). Multi-bit control signal612is generated based on this estimate and applied to switch sets614and616to connect the gates of MOS devices604and606, respectively, to input signal ±z(t) to appropriately scale the influence of the input signal on the source-to-drain conductance of those MOS devices.

Each of switch sets614and616has m switches, each switch having two input ports and one output port. Each switch in switch set614is coupled to one finger in MOS device604pand one finger in MOS device604n. Similarly, each switch in switch set616is coupled to one finger in MOS device606pand one finger in MOS device606n. Based on multi-bit control signal612, each switch couples a selected input port to the output port. As a result, the gates of MOS devices604and606are coupled to input signal z(t) of selected polarity and the conductance of those MOS devices becomes modulated with the input signal. In addition, finger connections provided by switch sets614and616are such that the conductance of MOS devices604and the conductance of MOS devices606change in a manner complementary to each other. More specifically, the conductance, σ, of each of MOS devices604and606is varied in accordance with Eqs. (6a) and (6b) as follows:

σ604=σi⁡(1-c2⁢z⁡(t))(6⁢a)σ606=σf⁡(1+c2⁢z⁡(t))(6⁢b)
where c is a scaling factor corresponding to control signal612, and σiand σfare constants. Therefore, when the conductance of MOS device604increases, the conductance of MOS device606decreases by a proportionate amount, and vice versa.

The gain, G, of differential amplifier602is determined by the input and feedback resistances, Rinputand Rfeedback, provided by MOS devices604and606, respectively. Using Eqs. (6a) and (6b) and the inverse relationship between resistance and conductance, one obtains the following expression for G:

G=RfeedbackRinput=g0⁢1-c2⁢z⁡(t)1+c2⁢z⁡(t)(7)
where g0=σi/σf. In a representative implementation of MRA circuit626, MOS devices604and606are designed such that the value of g0is approximately 1. However, it may be preferable to have σislightly larger than σfto compensate for gain losses elsewhere in the signal path. Assuming g0=1 and using the definition of G as y(t)/z(t), one arrives at the following transfer function for MRA circuit626:

y⁡(t)=z⁡(t)⁢⁢1-c2⁢z⁡(t)1+c2⁢z⁡(t)=z⁡(t)-c⁢⁢z⁡(t)2+c22⁢z⁡(t)3-c34⁢z⁡(t)4+…(8)
Similar to Eq. (4), Eq. (8) is a species of Eq. (3), wherein α=c and O(z(t)4) corresponds to the residual sum of a Taylor expansion series of the denominator multiplied by the numerator.

FIG. 7shows a diagram of a circuit700that can be used in MRA circuit626according to one embodiment of the present invention. More specifically, circuit700has four MOS devices M0, M1, M7, and M8that can be used as MOS devices604p,604n,606n, and606p, respectively, in MRA circuit626. In circuit700, MOS devices M0, M1, M7, and M8are coupled to a differential amplifier702that is analogous to differential amplifier602ofFIG. 6. Each of MOS devices M0, M1, M7, and M8is a MOS transistor having sixteen fingers (gates). Each finger is connected to a corresponding line in one of the buses labeled gn<15:0> and gp<15:0>, where the former controls the fingers of MOS devices M7and M8and the latter controls the fingers of MOS devices M0and M1. Buses gn<15:0> and gp<15:0> connect MOS devices M0, M1, M7, and M8to switch sets analogous to switch sets614and616ofFIG. 6. Signals labeled sat_ctl and v18aprovide appropriate bias voltages to each of MOS devices M0, M1, M7, and M8, and signals labeled fol_p and fol_n represent buffered, level-shifted versions of the input signal that are generated, e.g., by source followers610ainFIG. 6.

In one embodiment, each of MOS devices M0, M1, M7, and M8is implemented as a device analogous to sixteen NMOS transistors having a common source, a common drain, and sixteen separate gate nodes. Due to the source/drain sharing between adjacent transistors, this embodiment takes up a relatively small chip area. A preferred layout stile is similar to an inter-digitated (double-comb) layout style typically used to implement a single large NMOS transistor having a gate width/length ratio of about 1000, in which the source and the drain appear as alternating stripes separated by the gate areas. However, one difference between these two layouts is that, in the present invention, the gate areas are not connected together to form a single node, but rather, represent sixteen separate gates of sixteen transistors. Using device M0as an example, the first stripe is the drain M0<0>; the second stripe is the source of M0<0> and simultaneously the source of M0<1>; the third stripe is the drain of M0<1> and simultaneously the drain of M0<2>, and so forth; and the last stripe is the drain of M0<15>. The gate of each transistor is located between the stripes serving as the source and drain of that transistor.

FIGS. 8A–Bshow diagrams of circuits810and820that can be used in switch sets614and616according to one embodiment of the present invention. More specifically,FIGS. 8A–Billustrate switch sets adapted for use in conjunction with circuit700ofFIG. 7to connect the differential input signal to buses gn<15:0> and gp<15:0>. Circuit810is adapted to connect the differential input signal to lines gn<0>an gp<0> of buses gn<15:0> and gp<15:0>, respectively, and, as such, can control one finger in each of MOS devices M0, M1, M7, and M8of circuit700. Circuit820is adapted to connect the input signal to lines gn<1> to gn<15> and gp<1> to gp<15> of buses gn<15:0> and gp<15:0>, respectively, and as such, can control the remaining fifteen fingers in each of MOS devices M0, M1, M7, and M8of circuit700.

Each transistor in transistor sets M52<7:0> and M53<7:0> can be switched between the “on” and “off” states using a corresponding line of bus frac_mr<7:0> connected to the gate of that transistor. Signals applied to bus frac_mr<7:0> are generated, e.g., based on the three least significant digits of multi-bit control signal612(seeFIG. 6) and are such that, at any given time, only one of those signals is active low. As a result, only one transistor in each transistor set is in the “on” state, which connects lines gn<0> and gp<0> to the corresponding terminals of resistor divider R2<7:0>. Since both transistor sets are controlled by bus frac_mr<7:0>, they provide complementary fractional switching of lines gn<0> and gp<0> between the levels corresponding to the negative and positive input signals. One skilled in the art will appreciate that this fractional switching can be used, for example, to provide fine adjustment to the value of the scaling factor that determines conductance changes in MOS devices604and606of MRA circuit626(see Eqs. (6a–b) andFIG. 6).

Referring toFIG. 8B, circuit820has four transistor sets M55<15:1>, M56<15:1>, M65<15:1>, and M66<15:1>, each having fifteen transistors. Transistors in transistor sets M55<15:1> and M56<15:1> are connected together at their sources, which are also connected to the positive input signal. Similarly, transistors in transistor sets M65<15:1> and M66<15:1> are connected together at their drains, which are also connected to the negative input signal. The drain of each transistor in transistor set M55<15:1> is connected to the source of a corresponding transistor in transistor set M66<15:1> and to the corresponding line in bus gp<15:1>. Similarly, the drain of each transistor in transistor set M56<15:1> is connected to the source of a corresponding transistor in transistor set M65<15:1> and to the corresponding line in bus gn<15:1>.

Each transistor in transistor sets M55<15:1>, M56<15:1>, M65<15:1>, and M66<15:1> can be switched between the “on” and “off” states using a corresponding line in buses therm_n<15:1> and therm_p<15:1> that is connected to the gate of that transistor. The signals applied to buses therm_n<15:1> and therm_p<15:1> can be generated, e.g., based on multi-bit control signal612(seeFIG. 6) and are complementary to each other. More specifically, at any given time, only one of the two transistors connected to any line gn<k> of bus gn<15:1> or any line gp<k> of bus gp<15:1>, where1≦k≦15, is in the “on” state, thereby connecting that line to the input signal of the corresponding polarity. In addition, when any given line gn<k> of bus gn<15:1> is connected to the positive input signal, the corresponding line gp<k> of bus gp<15:1> is connected to the negative input signal, and vice versa. One skilled in the art will appreciate that the complementary switching implemented in circuit820can be used, for example, to provide complementary conductance changes in MOS devices604and606of MRA circuit626(andFIG. 6).

While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Although the present invention has been described in the context of CMOS technology, it will be understood that the present invention can be implemented using other technologies, such as nMOS, pMOS, or other non-MOS technologies. The substrates used in the circuits of the present invention may be made of any suitable semiconductor material, such as Si, GaAs, or InP, with different dopant types to form various structures. Although circuits of the present invention have been described as adapted to reduce signal asymmetry, one skilled in the art will appreciate that these circuits may also be adapted to change (i.e., increase or reduce) said signal asymmetry. Circuits of the invention may be used in conjunction with MR heads having a transfer function different from that given by Eq. (1). In general, circuits of the invention provide a signal contribution corresponding to an order of the input signal higher than the second order, which contribution may or may not include a third-order term. Various modifications of the described embodiments, as well as other embodiments of the invention, which are apparent to persons skilled in the art to which the invention pertains are deemed to lie within the principle and scope of the invention as expressed in the following claims.

Although the steps in the following method claims, if any, are recited in a particular sequence with corresponding labeling, unless the claim recitations otherwise imply a particular sequence for implementing some or all of those steps, those steps are not necessarily intended to be limited to being implemented in that particular sequence.