SEMICONDUCTOR MEMORY DEVICE

A semiconductor memory device includes a semiconductor substrate, a peripheral circuit structure disposed on the semiconductor substrate, and a cell array structure located on the peripheral circuit structure and including a memory cell array including a plurality of memory cells, wherein each of the plurality of memory cells of the cell array structure includes a bit line extending in a first horizontal direction, a channel pattern including a horizontal channel portion on the bit line and a vertical channel portion vertically protruding from the horizontal channel portion, a first word line extending in a second horizontal direction crossing the first horizontal direction on the channel pattern, a first gate insulating pattern located between the channel pattern and the first word line, a landing pad connected to the vertical channel portion of the channel pattern, and a data storage pattern disposed on the landing pad.

CROSS-REFERENCE TO RELATED APPLICATION

BACKGROUND

The inventive concept relates to a semiconductor memory device, and more particularly, to a semiconductor memory device including vertical channel transistors.

As design rules for semiconductor devices decrease, manufacturing technology has been developed toward improving the degree of integration of semiconductor devices and improving an operation speed and yield. Therefore, a transistor having a vertical channel has been proposed in order to increase the degree of integration, resistance, and current driving capability of the transistor.

SUMMARY

The inventive concept provides a semiconductor memory device having improved electrical characteristics and high integration density.

According to an aspect of the inventive concept, there is provided a semiconductor memory device.

The semiconductor memory device includes a semiconductor substrate, a peripheral circuit structure disposed on the semiconductor substrate, and a cell array structure located on the peripheral circuit structure and including a memory cell array including a plurality of memory cells, wherein the peripheral circuit structure includes a first transistor integrated on an upper surface of the semiconductor substrate and a connection wiring structure located on the first transistor and including a first connection wiring and a first connection contact plug electrically connecting the first connection wiring to the first transistor, wherein each of the plurality of memory cells of the cell array structure includes a bit line extending in a first horizontal direction and electrically connected to the first connection wiring, a channel pattern including a horizontal channel portion on the bit line and a vertical channel portion vertically protruding from the horizontal channel portion, a first word line extending in a second horizontal direction crossing the first horizontal direction on the channel pattern, a first gate insulating pattern located between the channel pattern and the first word line, a landing pad connected to the vertical channel portion of the channel pattern, and a data storage pattern disposed on the landing pad, wherein the first connection wiring and the first connection contact plug electrically connecting the bit line to the first transistor overlap the plurality of memory cells in a vertical direction.

According to another aspect of the inventive concept, there is provided a semiconductor memory device including a semiconductor substrate, a peripheral circuit structure including a sense amplifier region disposed on the semiconductor substrate, in which a sense amplifier is located, a sub-word line driver region in which a sub-word line driver is located, and a coupling region in which a driving circuit driver and a switch for driving the sub-word line driver or the sense amplifier are located, and a cell array structure located on the peripheral circuit structure and including a memory cell array including a plurality of memory cells each including a selection device and a data storage device, wherein the selection device is a vertical channel transistor, wherein at least a portion of at least one of the sense amplifier region, the sub-word line driver region, and the coupling region overlaps the plurality of memory cells in a vertical direction, and wherein an electrical path of the plurality of memory cells and the sense amplifier overlaps the plurality of memory cells in the vertical direction.

According to another aspect of the inventive concept, there is provided a semiconductor memory device including a semiconductor substrate, a peripheral circuit structure including a sense amplifier region disposed on the semiconductor substrate, in which a sense amplifier is located, a sub-word line driver region in which a sub-word line driver is located, and a coupling region in which a driving circuit driver and a switch for driving the sub-word line driver or the sense amplifier are located, and a cell array structure disposed on the peripheral circuit structure and including a memory cell array constituted by a plurality of memory cells, wherein the peripheral circuit structure includes a first transistor integrated on an upper surface of the semiconductor substrate and constituting the sense amplifier and a second transistor constituting the sub-word line driver, a peripheral contact plug electrically connected to each of the first transistor and the second transistor, a peripheral circuit wiring electrically connected to the peripheral contact plug, and a connection wiring structure disposed on the peripheral circuit wiring and including a first connection wiring and a first connection contact plug electrically connecting the first connection wiring to the peripheral circuit wiring, wherein each of the plurality of memory cells of the cell array structure includes a bit line extending in a first horizontal direction and electrically connected to the connection wiring, a channel pattern including a horizontal channel portion on the bit line and a vertical channel portion vertically protruding from the horizontal channel portion, a first word line extending in a second horizontal direction intersecting the first horizontal direction on the channel pattern, a first gate insulating pattern located between the channel pattern and the first word line, a landing pad electrically connected to the vertical channel portion of the channel pattern, and a data storage pattern disposed on the landing pad, wherein at least a portion of the sense amplifier region overlaps the plurality of memory cells in a vertical direction, and the first connection wiring, the first connection contact plug, the peripheral circuit wiring, and the peripheral contact plug electrically connecting the bit line to the first transistor vertically overlap the plurality of memory cells.

DETAILED DESCRIPTION OF THE EMBODIMENTS

FIG.1is a block diagram of a semiconductor memory device according to embodiments.

Referring toFIG.1, the semiconductor memory device may include a memory cell array1, a sub-word line driver2, a row decoder3, a sense amplifier4, a column decoder5, and a control logic6.

The memory cell array1may include a plurality of memory cells MC arranged two-dimensionally or three-dimensionally. Each of the memory cells MC may be connected between a word line WL and a bit line BL that cross each other. For example, each memory cell MC may be disposed between a word line WL and a bit line BL, and may be electrically connected to the word line WL and the bit line BL.

Each of the memory cells MC includes a selection device TR and a data storage device DS, and the selection device TR may be electrically connected to the data storage device DS in series. The selection device TR may be electrically connected between/to the data storage device DS and the word line WL, and the data storage device DS may be electrically connected to the bit line BL through the selection device TR. The selection device TR may be a field effect transistor (FET), and the data storage device DS may be implemented as a capacitor, a magnetic tunnel junction pattern, or a variable resistor. For example, the selection device TR may include or may be a transistor, a gate electrode of the transistor may be electrically connected to the word line WL, and drain/source terminals of the transistor may be electrically connected to the bit line BL and the data storage device DS.

As used herein, components described as being “electrically connected” are configured such that an electrical signal can be transferred from one component to the other (although such electrical signal may be attenuated in strength as it transferred and may be selectively transferred).

The row decoder3may select any one of the word lines WL of the memory cell array1by decoding an externally input address. The address decoded by the row decoder3may be provided to the sub-word line driver2, and the sub-word line driver2may provide a certain voltage to each of the selected word line WL and unselected word lines WL, in response to the control of the control circuits.

The sense amplifier4may sense, amplify, and output a voltage difference between a selected bit line BL and a reference bit line according to a decoded address from the column decoder5.

The column decoder5may provide a data transmission path between the sense amplifier4and an external device (e.g., a memory controller). The column decoder5may select any one of the bit lines BL by decoding an externally input address.

The control logic6may generate control signals for controlling operations of writing or reading data to or from the memory cell array1.

FIG.2is a perspective view schematically illustrating a semiconductor memory device according to embodiments.

Referring toFIG.2, the semiconductor memory device may include a peripheral circuit structure PS on a semiconductor substrate100and a cell array structure CS on the peripheral circuit structure PS.

The peripheral circuit structure PS may include a core and peripheral circuits formed on the semiconductor substrate100. The core and peripheral circuits may include the sub-word line driver2, the row decoder3, the sense amplifier4, the column decoder5, and the control logic6described above with reference toFIG.1. For example, the peripheral circuit structure PS may include a sub-word line driver region SWD, in which the sub-word line driver (2ofFIG.1) is disposed, and a sense amplifier region SA, in which the sense amplifier (4ofFIG.1) is disposed. The peripheral circuit structure PS may be provided between the semiconductor substrate100and the cell array structure CS in a vertical direction (a Z direction) perpendicular to the upper surface of the semiconductor substrate100.

The cell array structure CS may include bit lines BL, word lines WL and memory cells (MCs ofFIG.1) therebetween. The memory cells (MC ofFIG.1) may be arranged two-dimensionally or three-dimensionally on a plane extending in a first horizontal direction (an X direction) and a second horizontal direction (a Y direction) that intersect each other, to configure the memory cell array (1ofFIG.1). The bit lines BL may extend in the first horizontal direction (the X direction), and the word lines WL may extend in the second horizontal direction (the Y direction). Each of the memory cells (MC ofFIG.1) may include a selection device TR and a data storage device DS.

In some embodiments, at least a portion of at least one of the sub-word line driver region SWD and the sense amplifier region SA may be located in the peripheral circuit structure PS to overlap the memory cell array (1ofFIG.1) in the vertical direction (the Z direction). In some embodiments, at a portion in which the sub-word line driver region SWD and the sense amplifier region SA intersect each other, at least a portion of a coupling region (C/J inFIGS.3A to3I), in which a driving circuit driver for driving the sub-word line driver (2ofFIG.1) or the sense amplifier (4ofFIG.1) and a switch are arranged, may be disposed in the peripheral circuit structure PS to overlap the memory cell array (1ofFIG.1) in the vertical direction (the Z direction). For example, at least some of the sub-word line driver (2ofFIG.1), the sense amplifier (4ofFIG.1), a driving circuit driver for driving the sense amplifier (4ofFIG.1), and a switch may be disposed in the peripheral circuit structure PS to overlap the memory cell array (1ofFIG.1) in the vertical direction (the Z direction).

Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe positional relationships. It will be understood that the spatially relative terms encompass different orientations of the device in addition to the orientation depicted in the figures.

In some embodiments, a vertical channel transistor (VCT) may be included as the selection device TR of each memory cell (MC ofFIG.1). The vertical channel transistor may be a structure in which a channel length extends in the vertical direction (the Z direction). In some embodiments, the data storage device DS of each memory cell (MC ofFIG.1) may be a capacitor.

FIGS.3A to3Iare planar layouts schematically illustrating a semiconductor memory device according to embodiments.

Referring toFIGS.3A to3Itogether, the semiconductor memory device may include a memory cell array CELL ARRAY, a sub-word line driver region SWD, a sense amplifier region SA, and a coupling region C/J.

The memory cell array CELL ARRAY may be the memory cell array1shown inFIG.1, and may be located in the cell array structure CS shown inFIG.2. The memory cell array CELL ARRAY may include the memory cells (MC ofFIG.1) electrically connected between the word lines (WL ofFIG.1) and the bit lines (BL ofFIG.1) crossing each other and arranged two-dimensionally or three-dimensionally. The bit lines (BL ofFIG.1) may extend in the first horizontal direction (the X direction), and the word lines (WL ofFIG.1) may extend in the second horizontal direction (the Y direction).

The sub-word line driver2shown inFIG.1may be located in the sub-word line driver region SWD, and the sub-word line driver region SWD may be located in the peripheral circuit structure PS shown inFIG.1. The sense amplifier4shown inFIG.1may be located in the sense amplifier region SA, and the sense amplifier region SA may be located in the peripheral circuit structure PS shown inFIG.2.

A driving circuit driver for driving the sub-word line driver (2ofFIG.1) or the sense amplifier (4ofFIG.1) and a switch are located in the coupling region C/J, and the coupling region C/J may be located in the peripheral circuit structure PS shown inFIG.2. The coupling region C/J may be located between the sub-word line driver region SWD and the sense amplifier region SA. For example, the coupling region C/J may be located at an intersection of the sub-word line driver region SWD and the sense amplifier region SA.

At least a portion of at least one of the sub-word line driver region SWD, the sense amplifier region SA, and the coupling region C/J may overlap the memory cell array CELL ARRAY in a vertical direction (the Z direction). At least one of the sub-word line driver region SWD, the sense amplifier region SA, and the coupling region C/J may be electrically connected to the memory cell array CELL ARRAY through a portion overlapping the memory cell array CELL ARRAY in the vertical direction (the Z direction), which is described in detail below with reference toFIGS.4A to19B. Electrically connecting the sub-word line driver region SWD, the sense amplifier region SA, or the coupling region C/J to the memory cell array CELL ARRAY refers to electrically connecting the sub-word line driver (2ofFIG.1) located in the sub-word line driver region SWD, the sense amplifier (4ofFIG.1) located in the sense amplifier region SA, or the driving circuit driver located in the coupling region C/J and driving the sub-word line driver (2ofFIG.1) or the sense amplifier (4ofFIG.1) and the switch to the memory cell array CELL ARRAY.

Referring toFIGS.3A to3Htogether, in a top view, the sense amplifier region SA may be located on the first horizontal direction (the X direction) side of the memory cell array CELL ARRAY, and the sub-word line driver region SWD may be located on the second horizontal direction (the Y direction) side of the memory cell array CELL ARRAY. The coupling region C/J may be located between the sub-word line driver region SWD and the sense amplifier region SA. For example, the coupling region C/J may be located to be adjacent to one edge of the memory cell array CELL ARRAY between the sub-word line driver region SWD and the sense amplifier region SA.

Referring toFIG.3A, at least a portion of the sense amplifier region SA may overlap the memory cell array CELL ARRAY in the vertical direction (the Z direction), and the sub-word line driver region SWD and the coupling region C/J may not overlap the memory cell array CELL ARRAY in the vertical direction (the Z direction).

The sense amplifier region SA may be electrically connected to the memory cell array CELL ARRAY through a portion overlapping the memory cell array CELL ARRAY in the vertical direction (the Z direction). In some embodiments, the sub-word line driver region SWD may be electrically connected to the memory cell array CELL ARRAY through a portion that does not overlap the memory cell array CELL ARRAY in the vertical direction (the Z direction), for example, a portion of the cell array structure (CS ofFIG.2) located above the sub-word line driver region SWD.

Referring toFIG.3B, at least a portion of the sense amplifier region SA and at least a portion of the sub-word line driver region SWD may overlap the memory cell array CELL ARRAY in the vertical direction (the Z direction), and the coupling region C/J may not overlap the memory cell array CELL ARRAY in the vertical direction (the Z direction).

The sense amplifier region SA and the sub-word line driver region SWD may be electrically connected to the memory cell array CELL ARRAY through a portion overlapping the memory cell array CELL ARRAY in the vertical direction (the Z direction).

Referring toFIG.3C, at least a portion of the sense amplifier region SA and at least a portion of the coupling region C/J may overlap the memory cell array CELL ARRAY in the vertical direction (the Z direction), and the sub-word line driver region SWD may not overlap the memory cell array CELL ARRAY in the vertical direction (the Z direction).

The sense amplifier region SA may be electrically connected to the memory cell array CELL ARRAY through a portion overlapping the memory cell array CELL ARRAY in the vertical direction (the Z direction). In some embodiments, the sub-word line driver region SWD may be electrically connected to the memory cell array CELL ARRAY through a portion that does not overlap the memory cell array CELL ARRAY in the vertical direction (the Z direction), for example, a portion of the cell array structure (CS ofFIG.2) located above the sub-word line driver region SWD.

The coupling region C/J may be electrically connected to the memory cell array CELL ARRAY through a portion overlapping the memory cell array CELL ARRAY in the vertical direction (the Z direction), but the inventive concept is not limited thereto. In some embodiments, the coupling region C/J may be electrically connected to the memory cell array CELL ARRAY through the sense amplifier region SA and/or the sub-word line driver region SWD.

Referring toFIG.3D, at least a portion of the sense amplifier region SA, at least a portion of the sub-word line driver region SWD, and at least a portion of the coupling region C/J may overlap the memory cell array CELL ARRAY in the vertical direction (the Z direction).

The sense amplifier region SA and the sub-word line driver region SWD may be electrically connected to the memory cell array CELL ARRAY through a portion overlapping the memory cell array CELL ARRAY in the vertical direction (the Z direction).

Referring toFIG.3E, at least a portion of the sub-word line driver region SWD may overlap the memory cell array CELL ARRAY in the vertical direction (the Z direction), and the sense amplifier region SA and the coupling region C/J) may not overlap the memory cell array CELL ARRAY in the vertical direction (the Z direction).

The sub-word line driver region SWD may be electrically connected to the memory cell array CELL ARRAY through a portion overlapping the memory cell array CELL ARRAY in the vertical direction (the Z direction). In some embodiments, the sense amplifier region SA may be electrically connected to the memory cell array CELL ARRAY through a portion that does not overlap the memory cell array CELL ARRAY in the vertical direction (the Z direction), for example, a portion of the cell array structure located above the sense amplifier region SA.

Referring toFIG.3F, at least a portion of the coupling region C/J may overlap the memory cell array CELL ARRAY in the vertical direction (the Z direction), and the sense amplifier region SA and the sub-word line driver region SWD may not overlap the memory cell array CELL ARRAY in the vertical direction (the Z direction).

The coupling region C/J may be electrically connected to the memory cell array CELL ARRAY through a portion overlapping the memory cell array CELL ARRAY in the vertical direction (the Z direction). The sense amplifier region SA and the sub-word line driver region SWD may be electrically connected to the memory cell array CELL ARRAY through a portion that does overlap the memory cell array CELL ARRAY in the vertical direction (the Z direction), for example, a position of the cell array structure (CS ofFIG.2) located above the sub-word line driver region SWD.

Referring toFIG.3G, at least a portion of the sub-word line driver region SWD and at least a portion of the coupling region C/J may overlap the memory cell array CELL ARRAY in the vertical direction (the Z direction), and the sense amplifier region SA may not overlap the memory cell array CELL ARRAY in the vertical direction (the Z direction).

The sub-word line driver region SWD may be electrically connected to the memory cell array CELL ARRAY through a portion overlapping the memory cell array CELL ARRAY in the vertical direction (the Z direction). In some embodiments, the sense amplifier region SA may be electrically connected to the memory cell array CELL ARRAY through a portion that does not overlap the memory cell array CELL ARRAY in the vertical direction (the Z direction), for example, a portion of the cell array structure (CS ofFIG.2) located above the sub-word line driver region SWD.

The coupling region C/J may be electrically connected to the memory cell array CELL ARRAY through a portion overlapping the memory cell array CELL ARRAY in the vertical direction (the Z direction), but the inventive concept is not limited thereto. In some embodiments, the coupling region C/J may be electrically connected to the memory cell array CELL ARRAY through the sense amplifier region SA and/or the sub-word line driver region SWD.

Referring toFIG.3H, the sense amplifier region SA, the sub-word line driver region SWD, and the coupling region C/J may overlap the memory cell array CELL ARRAY in the vertical direction (the Z direction). For example, the sense amplifier region SA, the sub-word line driver region SWD, and the coupling region C/J may all overlap the memory cell array CELL ARRAY in the vertical direction (the Z direction). The sense amplifier region SA, the sub-word line driver region SWD, and the coupling region C/J may be electrically connected to the memory cell array CELL through a portion overlapping the memory cell array CELL ARRAY in the vertical direction (the Z direction).

Referring toFIG.3I, in a top-view, the sense amplifier region SA may be located on the second horizontal direction (the Y direction) side of the memory cell array CELL ARRAY, and the sub-word line driver region SWD may be located in the first horizontal direction (the X direction) side of the memory cell array CELL ARRAY. The coupling region C/J may be located between the sub-word line driver region SWD and the sense amplifier region SA. For example, the coupling region C/J may be located to be adjacent to one edge of the memory cell array CELL ARRAY between the sub-word line driver region SWD and the sense amplifier region SA.

FIG.3Ishows that at least a portion of the sense amplifier region SA, at least a portion of the sub-word line driver region SWD, and at least a portion of the coupling region C/J overlap the memory cell array CELL ARRAY in the vertical direction (the Z direction), but the overlap relations are not limited thereto, and an arrangement relationship between the memory cell array CELL ARRAY and the sub-word line driver region SWD, the sense amplifier region SA, and the coupling region C/J may be variously modified with reference toFIGS.3A to3H.

Referring back toFIGS.3A to3I, because at least a portion of the sub-word line driver region SWD, the sense amplifier region SA, and the coupling region C/J included in the semiconductor memory device is located to overlap the memory cell array CELL ARRAY in the vertical direction (the Z direction), an area that may be used by the sub-word line driver region SWD, the sense amplifier region SA, and the coupling region C/J may be increased in a top view. Accordingly, a line width, pitch, and area of components located in the sub-word line driver region SWD, the sense amplifier region SA, and the coupling region C/J, such as transistors, conductive lines, and contact plugs, may be relatively increased, or the components may be arranged freely, so that the design freedom of the components may be increased. For example, the design freedom of the components arranged in the sub-word line driver region SWD, the sense amplifier region SA, and the coupling region C/J may be increased by changing the arrangement of transistors constituting the sense amplifier (4ofFIG.1) located in the sense amplifier region SA or increasing the number of components connected to one conductive line, etc.

FIG.4Ais a plan view of a semiconductor memory device according to embodiments, andFIGS.4B and4Care cross-sectional views of a semiconductor memory device according to embodiments. Specifically,FIG.4Bshows cross-sections taken along lines A-A′ and B-B′ ofFIG.4A, andFIG.4Cshows cross-sections taken along lines C-C′, D-D′, and E-E′ ofFIG.4A.FIGS.5A to5Jare enlarged views of portion P ofFIG.4C, andFIGS.6A to6Dare enlarged views of portion Q ofFIG.4C.

Referring toFIGS.4A to4C, the semiconductor memory device may include a peripheral circuit structure PS and a cell array structure CS. The peripheral circuit structure PS may include first circuit transistors CT and second circuit transistors PT integrated on the upper surface of the semiconductor substrate100, peripheral circuit wirings PCL electrically connected to the first circuit transistors CT and the second circuit transistors PT, an insulating layer110covering the first circuit transistors CT and the second circuit transistors PT, and peripheral contact plugs PCT. For example, the semiconductor substrate100may be a single crystal silicon substrate. The semiconductor substrate100may include a cell array region CAR and a peripheral circuit region PCR.

In the peripheral circuit structure PS, the first circuit transistors CT may be arranged in the cell array region CAR of the semiconductor substrate100, and second circuit transistors PT may be arranged in the peripheral circuit region PCR of the semiconductor substrate100. The first circuit transistors CT may include or may be NMOS and PMOS transistors integrated on the semiconductor substrate100, and the second circuit transistors PT may include or may be NMOS and PMOS transistors integrated on the semiconductor substrate100. The first circuit transistors CT may overlap the memory cell array (1ofFIG.1) in the vertical direction (the Z direction), and the second circuit transistors PT may not overlap the memory cell array (1ofFIG.1) in the vertical direction (the Z direction).

The first circuit transistors CT and the second circuit transistors PT may constitute the sub-word line driver (2ofFIG.1), the row decoder (3ofFIG.1), the sense amplifier (4ofFIG.1), the column decoder (5ofFIG.1) and the control logic (6ofFIG.1). In some embodiments, at least some of the sub-word line driver (2ofFIG.1), the sense amplifier (4ofFIG.1), and the driving circuit driver and the switch for driving the sub-word line driver (2ofFIG.1) and the sense amplifier (4ofFIG.1), among the sub-word line driver (2ofFIG.2), the row decoder (3ofFIG.1), the sense amplifier (4ofFIG.1), the column decoder (5ofFIG.1), and the control logic (6ofFIG.1), may be constituted by the first circuit transistors CT and the others may be constituted by the second circuit transistors PT.

The first circuit transistors CT and the second circuit transistors PT may be electrically connected to the peripheral circuit contact plugs PCT and the peripheral circuit wirings PCL. The peripheral circuit insulating layer110may cover the first circuit transistors CT and the second circuit transistors PT, the peripheral circuit wirings PCL, and the peripheral circuit contact plugs PCT on the semiconductor substrate100. The peripheral circuit insulating layer110may have a substantially flat upper surface. In some embodiments, upper surfaces of the peripheral circuit wirings PCL and the peripheral circuit insulating layer110may be coplanar with each other. The peripheral circuit insulating layer110may include or be formed of insulating layers stacked in and/or having multiple layers. For example, the peripheral circuit insulating layer110may include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and/or a low dielectric layer.

Terms such as “same,” “equal,” “planar,” “symmetry,” or “coplanar,” as used herein encompass identicality or near identicality including variations that may occur, for example, due to manufacturing processes. The term “substantially” may be used herein to emphasize this meaning, unless the context or other statements indicate otherwise.

A connection wiring structure IS may be disposed on the peripheral circuit insulating layer110. The connection wiring structure IS may include a first wiring insulating layer111, a second wiring insulating layer112stacked/formed on the first wiring insulating layer111, first connection wirings CM1passing through the second wiring insulating layer112, and first connection contact plugs CMC1passing through the first wiring insulating layer111to electrically connect the peripheral circuit wirings PCL to the first connection wirings CM1. Each of the first wiring insulating layer111and the second wiring insulating layer112may include or may be a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and/or a low dielectric layer. In some embodiments, the first wiring insulating layer111and the second wiring insulating layer112may be formed together to form an integral body.

The cell array structure CS may be provided on the connection wiring structure IS. In some embodiments, a cover insulating layer116may be located between the second wiring insulating layer112and the cell array structure CS. The cover insulating layer116may include nitride. For example, the cover insulating layer116may include or may be a silicon nitride layer and/or a silicon oxynitride layer.

The cell array structure CS may include bit lines BL, channel patterns CP, first word lines WL1, second word lines WL2, first gate insulating patterns Gox1, second gate insulating patterns Gox2, a gate insulating pattern Gox, and data storage patterns DSP. At least a portion of each of the channel patterns CP may constitute a selection device (TR ofFIG.1), and each of the selection device (TR ofFIG.1) formed by at least a portion of each of the channel patterns CP and each of the data storage patterns DSP may form a memory cell (MC ofFIG.1). The bit lines BL, the channel patterns CP, the first word lines WL1, the second word lines WL2, the first gate insulating patterns Gox1, the second gate insulating patterns Gox2, the gate insulating pattern Gox, and the data storage patterns DSP may constitute a memory cell array (1ofFIG.1).

The bit lines BL may extend in the first horizontal direction (the X direction) on the peripheral circuit structure PS and may be apart from each other in the second horizontal direction (the Y direction). The bit lines BL may have a first width W1in the second horizontal direction (the Y direction), and the first width W1may be about 1 nm to about 50 nm. The bit lines BL may include or be formed of, for example, doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or a combination thereof. The bit lines BL may include or be formed of doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, or a combination thereof, but materials forming or included in the bit lines BL are not limited thereto. The bit lines BL may include or be formed of a single layer or plural layers of the aforementioned materials. In some embodiments, the bit lines BL may include or be formed of one or more of 2D and 3D materials (e.g., 2D/3D semiconductor materials), for example, graphene, which is a carbon-based 2D material, and carbon nanotube, which is a 3D material, or a combination thereof.

The bit lines BL may be respectively electrically connected to the first connection wirings CM1through lower contact plugs LCT. In the peripheral circuit region PCR, the lower conductive patterns LCP may be at the same level as the bit lines BL. The lower conductive patterns LCP may be respectively electrically connected to the first connection wirings CM1through the lower contact plugs LCT. The lower conductive patterns LCP may include or be formed of the same conductive material as that of the bit lines BL.

A lower insulating pattern118surrounding the lower contact plugs LCT may be located between the bit lines BL and the first connection wirings CM1in the cell array region CAR. The lower contact plugs LCT may pass through the cover insulating layer116and the lower insulating pattern118. A charging insulating pattern119may be located to cover the cover insulating layer116and fill a portion between the lower conductive patterns LCP in the peripheral circuit region PCR.

A first insulating pattern121may be located between the bit lines BL. The first insulating pattern121may include or may be, for example, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and/or a low dielectric layer.

Shielding structures SS may be provided between the bit lines BL, respectively, and the shielding structures SS may extend to be parallel with each other in the first horizontal direction (the X direction). The shielding structures SS may include or be formed of a conductive material, such as metal. The shielding structures SS may be provided in the first insulating pattern121, and upper surfaces of the shielding structures SS may be at a level lower than upper surfaces of the bit lines BL, and lower surfaces of the shielding structures SS may be at a level lower than lower surfaces of the bit lines BL.

In some embodiments, the shielding structures SS may include a conductive material and may include an air gap or a void therein. In other embodiments, air gaps may be defined in the first insulating pattern121, instead of the shielding structures SS. For example, the air gap or the void may be in a vacuum state or may include a gas (e.g., a processing gas) or air.

A mold insulating pattern125may be disposed/formed on the first insulating pattern121and the bit lines BL. The mold insulating pattern125may define trenches (refer to T ofFIG.10A) extending in the second horizontal direction (the Y direction) across the bit lines BL and being apart from each other in the first horizontal direction (the X direction). The mold insulating pattern125may cover upper surfaces of the lower conductive patterns LCP in the peripheral circuit region PCR. The mold insulating pattern125may include or be formed of, for example, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and/or a low dielectric layer.

Channel patterns CP may be located on bit lines BL. The channel patterns CP may be apart from each other in the first horizontal direction (the X direction) by the mold insulating pattern125on each bit line BL. For example, the mold insulating pattern125may be interposed between the channel patterns CP. The channel patterns CP may be apart from each other in the second horizontal direction (the Y direction) in each trench of the mold insulating pattern125. For example, the channel patterns CP may be two-dimensionally arranged in the first horizontal direction (the X direction) and the second horizontal direction (the Y direction) intersecting each other. For example, the first and second horizontal directions may be perpendicular to each other.

Each of the channel patterns CP may have a first length L1in the first horizontal direction (the X direction) and may have a second width W2that is substantially equal to or greater than the first width W1of the bit lines BL in the second horizontal direction (the Y direction). An interval between the channel patterns CP in the first horizontal direction (the X direction) may be different from the first length L1of the channel pattern CP in the first horizontal direction (the X direction). In some embodiments, the interval between the channel patterns CP in the first horizontal direction (the X direction) may be less than the first length L1of the channel pattern CP in the first horizontal direction (the X direction). In some embodiments, the interval between the channel patterns CP in the first horizontal direction (the X direction) may be substantially equal to the first length L1of the channel pattern CP in the first horizontal direction (the X direction). In the second horizontal direction (the Y direction), an interval between the channel patterns CP may be substantially equal to or less than the second width W2of the channel pattern CP.

Referring toFIGS.4A to4Ctogether withFIG.5A, each of the channel patterns may include a horizontal channel portion HCP located on the bit line BL and first vertical channel portions VCP1and second vertical channel portions VCP2protruding upward from the horizontal channel portion HCP (e.g., from opposite ends of the horizontal channel portion HCP) and facing each other in the horizontal direction (the X direction). Each of the first vertical channel portions VCP1and the second vertical channel portions VCP2may have an outer wall in contact with the mold insulating pattern125and an inner wall opposite the outer wall, and the inner walls of first vertical channel portions VCP1and the second vertical channel portions VCP2may face each other in the first horizontal direction (the X direction). The outer walls of the first vertical channel portions VCP1and the second vertical channel portions VCP2of the channel patterns CP adjacent to each other in the first horizontal direction (the X direction) may face each other.

It will be understood that when an element is referred to as being “connected” or “coupled” to or “on” another element, it can be directly connected or coupled to or on the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, or as “contacting” or “in contact with” another element, there are no intervening elements present at the point of contact.

Each of the channel patterns CP may have a first length L1in a first horizontal direction (the X direction). The first length L1may be greater than the interval between the adjacent channel patterns CP in the first horizontal direction (the X direction).

Each of the first vertical channel portions VCP1and the second vertical channel portions VCP2may have a vertical length in the vertical direction (the Z direction) perpendicular to the upper surface of the semiconductor substrate100and may have a width in the first horizontal direction (the X direction). The vertical length of each of the first vertical channel portions VCP1and the second vertical channel portions VCP2may be about 2 to 10 times the width thereof, but the inventive concept is not limited thereto. The width of each of the first vertical channel portions VCP1and the second vertical channel portions VCP2in the first horizontal direction (the X direction) may be several nm to several tens of nm. For example, the widths of the first vertical channel portions VCP1and the second vertical channel portions VCP2may be about 1 nm to about 30 nm. In some embodiments, the widths of the first vertical channel portions VCP1and the second vertical channel portions VCP2may be about 1 nm to about 10 nm.

The horizontal channel portions HCP of the channel patterns CP may contact the upper surfaces of the bit lines BL. The thickness of the horizontal channel portions HCP on the upper surfaces of the bit lines BL may be substantially equal to the thickness of the first vertical channel portions VCP1and the second vertical channel portions VCP2on the sidewall of the mold insulating pattern125.

In each of the channel patterns CP, the horizontal channel portion HCP may include a common source/drain region, an upper end of the first vertical channel portion VCP1may include a first source/drain region, and an upper end of the second vertical channel portion VCP2may include a second source/drain region. The first vertical channel portion VCP1may include a first channel region between the first source/drain region and the common source/drain region, and the second vertical channel portion VCP2may include a second channel region between the second source/drain region and the common source/drain region. The channel region of the first vertical channel portion VCP1may be controlled by the first word line WL1, and the channel region of the second vertical channel portion VCP2may be controlled by the second word line WL2.

A portion of the channel pattern CP may be located between the first word lines WL1and the second word lines WL2. The horizontal channel portion HCP of the channel pattern CP may electrically and commonly connect the first vertical channel portions VCP1and the second vertical channel portions VCP2to the bit line BL corresponding thereto. For example, the semiconductor memory device may have a structure in which a pair of vertical channel transistors share one bit line BL.

In some embodiments, the channel patterns CP may include an oxide semiconductor. For example, the oxide semiconductor may be any one of zinc oxide (ZnO) (or ZnxO), gallium oxide (GaO) (or GaxO), tin oxide (TiO) (or TixO), zinc oxynitride (ZnON) (or ZnxOyN), indium zinc oxide (IZO) (or InxZnyO), gallium zinc oxide (GZO) (or GaxZnyO), tin zinc oxide (TZO) (or SnxZnyO), tin gallium oxide (TGO) (or SnxGayO), indium gallium zinc oxide (IGZO) (or InxGayZnzO), indium gallium silicon oxide (IGSO) (or InxGaySizO), indium tin zinc oxide (ITZO) (or InxSnyZnzO), indium tin gallium oxide (ITGO) (or InxSnyGazO), zirconium zinc tin oxide (ZZTO) (or ZrxZnySnzO), hafnium indium zinc oxide (HIZO) (or HfxInyZnzO), gallium zinc tin oxide (GZTO) (or GaxZnySnzO), aluminium zinc tin oxide (AZTO) (or AlxZnySnzO), and ytterbium gallium zinc oxide (YGZO) (or YbxGayZnzO). In some embodiments, the channel patterns CP may include IGZO. The channel patterns CP may include or be formed of a single layer or plural layers of the oxide semiconductor. The channel patterns CP may include, but are not limited to, an amorphous, single-crystalline, polycrystalline, spinel, or c-axis aligned crystalline (CAAC) oxide semiconductor. In some embodiments, the channel patterns CP may include or be formed of a 2D semiconductor material, and the 2D semiconductor material may include or may be, for example, graphene, carbon nanotubes, or a combination thereof. In some embodiments, the channel patterns CP may have a bandgap energy greater than that of silicon. For example, the channel patterns CP may have a bandgap energy of about 1.5 eV to about 5.6 eV. In some embodiments, the channel patterns CP may have a bandgap energy of about 2.0 eV to about 4.0 eV.

The first word lines WL1and the second word lines WL2may extend across the bit lines BL on the channel patterns CP in the second horizontal direction (the Y direction). The first word lines WL1and the second word lines WL2may be alternately arranged in the first horizontal direction (the X direction). A pair of a first word line WL1and a second word line WL2may be symmetrically provided on the horizontal channel portion HCP of each channel pattern CP.

The first word lines WL1and the second word lines WL2may include, for example, doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or a combination thereof. The first word lines WL1and the second word lines WL2may include doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, or a combination thereof, but the inventive concepts are not limited thereto. The first word lines WL1and the second word lines WL2may include or be formed of a single layer or plural layers of the aforementioned materials. In some embodiments, the first word lines WL1and the second word lines WL2may include or be formed of a 2D semiconductor material, and the 2D semiconductor material may include or may be, for example, graphene or carbon nanotubes, or a combination thereof.

The first word line WL1may include a first horizontal portion HP1located on the horizontal channel portion HCP of the channel pattern CP and a first vertical portion VP1vertically protruding from the first horizontal portion HP1. For example, the first horizontal portion HP1of the first word line WL1may extend lengthwise in a horizontal direction, and the first vertical portion VP1may extend lengthwise in a vertical direction, e.g., in a cross-sectional view. The first vertical portion VP1of the first word line WL1may be adjacent to the inner wall of the first vertical channel portion VCP1of the channel pattern CP. The second word line WL2may include a second horizontal portion HP2located on the horizontal channel portion HCP of the channel pattern CP and a second vertical portion VP2vertically protruding from the second horizontal portion HP2. The second vertical portion VP2of the second word line WL2may be adjacent to the inner wall of the second vertical channel portion VCP2of the channel pattern CP. The first word lines WL1and the second word lines WL2may have an L-shaped vertical cross-section and face each other. In the first horizontal direction (the X direction), the first word lines WL1and the second word lines WL2may be arranged mirror-symmetrically with each other.

A pair of a first word line WL1and a second word line WL2may be symmetrically arranged on the horizontal channel portion HCP of the channel pattern CP. The first horizontal portion HP1of the first word line WL1may have a first thickness on the upper surface of the horizontal channel portion HCP, and the first vertical portion VP1of the first word line WL1may have a second thickness, which is substantially equal to the first thickness, on a sidewall of the first vertical channel portion VCP1. The second horizontal portion HP2of the second word line WL2may have a first thickness on the upper surface of the horizontal channel portion HCP, and the second vertical portion VP2of the second word line WL2may a second thickness, which is substantially equal to the first thickness, on a sidewall of the second vertical channel portion VCP2.

The first horizontal portions HP1and the second horizontal portions HP2of the first word lines WL1and the second word lines WL2may have a first horizontal width HW1in the first horizontal direction (the X direction). Here, the first horizontal width HW1may be less than half of the length L1of the channel pattern CP in the first horizontal direction (the X direction).

A first spacer SP1may be disposed on the first horizontal portion HP1of the first word line WL1, and the second spacer SP2may be disposed on the second horizontal portion HP2of the second word line WL2. The first spacer SP1may be aligned with a sidewall of the first horizontal portion HP1of the first word line WL1, and the second spacer SP2may be aligned with a sidewall of the second horizontal portion HP2of the second word line WL2.

A first capping pattern151and a second insulating pattern153may be located between a pair of first and second spacers SP1and SP2. The first capping pattern151may be located between sidewalls of the first spacer SP1and the second spacer SP2and the second insulating pattern153and between the upper surface of the horizontal channel portion HCP of the channel pattern CP and the second insulating pattern153. The first capping pattern151may have a substantially uniform thickness and may include or be formed of an insulating material, different from that of the second insulating pattern153. The first capping pattern151and the second insulating pattern153may extend in the second horizontal direction (the Y direction).

A second capping pattern155may be provided on upper surfaces of the first vertical portions VP1of the first word lines WL1and the second vertical portions VP2of the second word lines WL2. The second capping pattern155may cover/contact upper surfaces of the first capping pattern151and the second insulating pattern153. The second capping pattern155may extend in the second horizontal direction (the Y direction). The upper surface of the second capping pattern155may be substantially coplanar with the upper surface of the mold insulating pattern125. The second capping pattern155may include or be formed of an insulating material, different from that of the second insulating pattern153.

The first gate insulating pattern Gox1may be located between the first word line WL1and the channel pattern CP, and the second gate insulating pattern Gox2may be located between the second word line WL2and the channel pattern CP. The first gate insulating patterns Gox1and the second gate insulating patterns Gox2may extend in the second horizontal direction (the Y direction) to be parallel to the first word lines WL1and the second word lines WL2. The first gate insulating patterns Gox1and the second gate insulating patterns Gox2may cover/contact the surface of the channel patterns CP with a uniform thickness. Between the channel patterns CP adjacent in the second horizontal direction (the Y direction), the first gate insulating patterns Gox1and the second gate insulating patterns Gox2may be in contact with the upper surface of the first insulating pattern121and the sidewalls of the mold insulating pattern125.

Each of the first gate insulating patterns Gox1and the second gate insulating patterns Gox2may substantially have an L-shape to correspond to the first word lines WL1and the second word lines WL2. For example, similarly to the first word lines WL1and the second word lines WL2, each of the first gate insulating patterns Gox1and the second gate insulating patterns Gox2may include a horizontal portion covering/contacting the horizontal channel portion HCP and a vertical portion covering/contacting the first vertical channel portions VCP1and the second vertical channel portions VCP2. Also, the first gate insulating pattern Gox1may be located mirror-symmetrically with the second gate insulating pattern Gox2in the first horizontal direction (the X direction). One sidewall of the first gate insulating pattern Gox1may be aligned with the first spacer SP1, and one sidewall of the second gate insulating pattern Gox2may be aligned with the second spacer SP2.

The first gate insulating patterns Gox1and the second gate insulating patterns Gox2may include or be formed of a silicon oxide layer, a silicon oxynitride layer, a high-k layer having a higher dielectric constant than that of the silicon oxide layer, or a combination thereof. The high-k layer may include or be formed of a metal oxide or a metal oxynitride.

Landing pads LP may be disposed on the first vertical channel portions VCP1and the second vertical channel portions VCP2of the channel pattern CP. The landing pads LP may contact the first vertical channel portions VCP1and the second vertical channel portions VCP2. As shown inFIG.5A, portions of the landing pads LP may be located between the sidewall of the mold insulating pattern125and the sidewalls of the first gate insulating patterns Gox1and the second gate insulating patterns Gox2. The landing pads LP may have various shapes, such as a circular shape, an oval shape, a rectangular shape, a square shape, a rhombus shape, and a hexagon shape, in a plan view. The landing pads LP may include or be formed of doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, or a combination thereof, but the inventive concepts are not limited thereto. Portions between the landing pads LP may be filled with a third insulating pattern. The landing pads LP may be separated from each other by the third insulating pattern165.

The data storage patterns DSP may be respectively disposed on the landing pads LP. The data storage patterns DSP may be electrically connected to the first vertical channel portions VCP1and the second vertical channel portions VCP2of the channel patterns CP through the landing pads LP, respectively. The data storage patterns DSP may be arranged in a matrix form in each of the first horizontal direction (the X direction) and the second horizontal direction (the Y direction) as illustrated inFIG.4A.

In some embodiments, the data storage patterns DSP may be capacitors, and may include lower electrodes, upper electrodes, and a capacitor dielectric layer located therebetween. The lower electrode may contact the landing pad LP, and the lower electrode may have various shapes, such as a circular shape, an oval shape, a rectangular shape, a square shape, a rhombus shape, and a hexagon shape, in a plan view.

In other embodiments, the data storage patterns DSP may be variable resistance patterns that may be switched to two resistance states by an electrical pulse applied to a memory element. For example, the data storage patterns DSP may include a phase-change materials, perovskite compounds, a transition metal oxide, a magnetic material, a ferromagnetic material, or an antiferromagnetic material changed in crystal state according to an amount of current.

Upper conductive patterns UCP may be disposed on the mold insulating pattern125of the peripheral circuit region PCR. The upper conductive patterns UCP may include or be formed of the same conductive material as that of the landing pads LP. The upper conductive patterns UCP may be respectively electrically connected to the lower conductive patterns LCP through the lower conductive vias LVP.

An etch stop layer171may cover/contact upper surfaces of the landing pads LP and the upper conductive patterns UCP. A capping insulating layer173may be disposed on the etch stop layer171. The capping insulating layer173may cover/contact the data storage patterns DSP of the cell array region CAR. The connection wirings CL may be provided on the capping insulating layer173in the peripheral circuit region PCR. The connection wirings CL may be respectively electrically connected to the upper conductive patterns UCP through the upper conductive vias UVP passing through the capping insulating layer173.

Referring toFIGS.4A to4Ctogether withFIG.5B, the gate insulating pattern Gox may cover the surface of the channel pattern CP with a uniform thickness. The gate insulating pattern Gox may be commonly disposed between the channel pattern CP and the first word lines WL1and the second word lines WL2. A portion of the gate insulating pattern Gox may be located between the first word lines WL1and the second word lines WL2, e.g., in a plan view. A portion of the gate insulating pattern Gox may contact the first capping pattern151.

Referring toFIGS.4A to4Ctogether withFIG.5C, first channel patterns CP1and second channel patterns CP2may be apart from each other in the first horizontal direction (the X direction) on the bit line BL and may be arranged mirror-symmetrically to each other. A first channel pattern CP1may include a first horizontal channel portion HCP1in contact with the bit line BL and a first vertical channel portion VCP1vertically protruding from the first horizontal channel portion HCP1and being adjacent to the first vertical portion VP1of the first word line WL1. A second channel pattern CP2may include a second horizontal channel portion HCP2in contact with the bit line BL and a second vertical channel portion VCP2vertically protruding from the second horizontal channel portion HCP2and being adjacent to an outer wall of the second word line WL2.

A sidewall of the first horizontal channel portion HCP1of the first channel pattern CP1and a sidewall of the first gate insulating pattern Gox1may be aligned/coplanar with the sidewall of the first horizontal portion HP1of the first word line WL1, e.g., in a vertical direction. Similarly, a sidewall of the second horizontal channel portion HCP2of the second channel pattern CP2and a sidewall of the second gate insulating pattern Gox2may be aligned/coplanar with the sidewall of the second horizontal portion HP2of the second word line WL2, e.g., in the vertical direction.

The first horizontal portions HP1of the first word lines WL1and the second horizontal portions HP2of the second word lines WL2may have a first horizontal width HW1in the first horizontal direction (the X direction), and the first horizontal channel portions HCP1of the first channel patterns CP1and the second horizontal channel portions HCP2of the second channel patterns CP2may have a second horizontal width HW2in the first horizontal direction, greater than the first horizontal width HW1.

When the first channel patterns CP1and the second channel patterns CP2are apart from each other on the bit line BL, the first capping pattern151may be in contact with the upper surface of the bit line BL between the first channel patterns CP1and the second channel patterns CP2.

Referring toFIGS.4A to4Ctogether withFIG.5D, the first spacer SP1and the second spacer SP2illustrated inFIG.5Amay be omitted, and the first capping pattern151may cover/contact the surfaces of the first word line WL1and the second word line WL2with a uniform thickness. For example, the first capping pattern151may be conformally formed on the surfaces of the first word line WL1, the second word line WL2, the first and second gate insulating patterns Gox1and Gox2, and the channel pattern CP.

Referring toFIGS.4A to4Ctogether withFIG.5E, the first spacer SP1and the second spacer SP2illustrated inFIG.5Cmay be omitted, and the first capping pattern151may cover/contact the surfaces of the first word line WL1and second word line WL2, sidewalls of the first channel pattern CP1and second channel pattern CP2, and a portion of the bit line BL with a uniform thickness. For example, the first capping pattern151may be conformally formed on the surfaces of the first word line WL1, the second word line WL2, the first and second gate insulating patterns Gox1and Gox2, the first and second channel patterns CP1and CP2, and the bit line BL.

Referring toFIGS.4A to4Ctogether withFIG.5F, unlike the first word line WL1and second word line WL2illustrated inFIG.5D, the first word line WL1and the second word line WL2illustrated inFIG.5Fmay have an I-shaped vertical cross-sections and may face each other. For example, the first word line WL1and the second word line WL2shown inFIG.5Fmay correspond to the first vertical portion VP1of the first word line WL1and the second vertical portion VP2of the second word line WL2illustrated inFIG.5D.

Referring toFIGS.4A to4Ctogether withFIG.5G, the first spacer SP1and the second spacer SP2illustrated inFIG.5Bmay be omitted, and unlike the first word line WL1and the second word line WL2illustrated inFIG.5B, the first word line WL1and the second word line WL2illustrated inFIG.5Gmay have an I-shaped vertical cross-sections and face each other. For example, the first word line WL1and the second word line WL2shown inFIG.5Gmay correspond to the first vertical portion VP1of the first word line WL1and the second vertical portion VP2of the second word line WL2shown inFIG.5B.

Referring toFIGS.4A to4Ctogether withFIG.5H, the first spacer SP1and the second spacer SP2illustrated inFIG.5Cmay be omitted, and unlike the first word line WL1and the second word line WL2illustrated inFIG.5C, the first word line WL1and the second word line WL2illustrated inFIG.5Hhave an I-shaped vertical cross-section and may face each other. For example, the first word line WL1and the second word line WL2shown inFIG.5Gmay correspond to the first vertical portion VP1of the first word line WL1and the second vertical portion VP2of the second word line WL2illustrated inFIG.5C.

Referring toFIGS.4A to4Ctogether withFIG.5I, word line shielding structures WS or air gaps may be located between the first word lines WL1and the second word lines WL2, respectively. The word line shielding structures WS may extend in the second horizontal direction (the Y direction) in parallel with the first word lines WL1and the second word lines WL2. In some embodiments, the word line shielding structures WS may be locally formed in the second insulating patterns153by forming an insulating layer defining a gap region and filling the gap region of the insulating layer with a conductive material in the process of forming the second insulating patterns153after the first word lines WL1and the second word lines WL2are formed. In other embodiments, in the process of forming the second insulating patterns153, air gaps may be formed in the second insulating patterns153by depositing an insulating layer by using a deposition method having poor step coverage characteristics. For example, the air gaps may be in a vacuum state or may be filled with a process gas provided in the deposition process.

Referring toFIGS.4A to4Ctogether withFIG.5J, upper surfaces of the bit lines BL may have a concave-convex structure. Upper surfaces of the bit lines BL below the channel patterns CP may be at a vertical level lower than an upper surface BLa of the bit lines BL. The upper surface BLa of the bit lines BL may be an upper surface at the highest vertical level among the upper surfaces of the bit lines BL and may not vertically overlap the channel patterns CP.

The lower surface of the horizontal channel portion HCP of the channel patterns CP may be at a vertical level lower than the upper surface BLa of the bit lines BL. At least a portion of the horizontal channel portion HCP of the channel patterns CP may be buried in an upper portion of the bit lines BL. For example, a bottom surface and a portion of side surfaces of the horizontal channel portion HCP of a channel pattern CP may be surrounded by and contact a bit line BL.

Referring toFIGS.4A to4Ctogether withFIG.6A, the mold insulating pattern125may be in contact with the upper surface of the bit line BL. The channel pattern CP may be disposed on the bit line BL, and the landing pad LP may be disposed on the channel pattern CP. The channel pattern CP may include a pair of source/drain regions apart from each other. A pair of source/drain regions may be located at an upper end of the channel pattern CP in contact with the landing pad LP and at a lower end of the channel pattern CP in contact with the bit line BL. The channel pattern CP may include a channel region between the pair of source/drain regions.

Referring toFIGS.4A to4Ctogether withFIG.6B, a blocking pattern BKP may be located between the mold insulating pattern125and the bit line BL. The blocking pattern BKP may be located between the neighboring channel patterns CP. The blocking pattern BKP may be located to be adjacent to lower portions of the channel patterns CP adjacent on the bit line BL. For example, the blocking pattern BKP may contact side surfaces of the lower portions of the channel patterns CP, a top surface of the bit line BL, and a bottom surface of the mold insulating pattern125. In some embodiments, a plurality of blocking patterns BKP may be disposed on the bit line BL. For example, the plurality of blocking patterns BKP may be apart from each other in the first vertical direction (the X direction) and disposed on the bit line BL. The blocking pattern BKP may include or be formed of at least one of an insulating material and a conductive material. The insulating material may include or may be, for example, at least one of silicon nitride (e.g., SiNx) and metal oxide (e.g., AlOx). The conductive material may include or may be, for example, a metal material.

Referring toFIGS.4A to4Ctogether withFIG.6C, a lower pattern HRP may be located between the mold insulating pattern125and the bit line BL. The lower pattern HRP may be located between the adjacent channel patterns CP. The lower pattern HRP may be disposed to be adjacent to lower portions of the channel patterns CP adjacent on the bit line BL. The lower pattern HRP may separate the mold insulating pattern125from the bit line BL in the vertical direction (the Z direction). For example, the lower pattern HRP may contact side surfaces of the lower portions of the channel patterns CP, a top surface of the bit line BL, and a bottom surface of the mold insulating pattern125. The lower pattern HRP may include or be formed of at least one of hydrogen (H) and deuterium (D). For example, the lower pattern HRP may include or be formed of silicon oxide including at least one of hydrogen and deuterium.

Referring toFIGS.4A to4Ctogether withFIG.6D, the blocking pattern BKP and the lower pattern HRP may be located between the mold insulating pattern125and the bit line BL. The blocking pattern BKP and the lower pattern HRP may be located between the adjacent channel patterns CP and may be located to be adjacent to lower portions of the channel patterns CP. In some embodiments, the lower pattern HRP may be located below the blocking pattern BKP and located between the bit line BL and the blocking pattern BKP. For example, the blocking pattern BKP may contact side surfaces of the channel patterns CP, a top surface of the lower pattern HRP, and a bottom surface of the mold insulating pattern125. For example, the lower pattern HRP may contact side surfaces of the lower portions of the channel patterns CP, a top surface of the bit line BL, and a bottom surface of the blocking pattern BKP.

The blocking pattern BKP may prevent the lower portions of the channel patterns CP from being oxidized due to oxygen (O) included in the mold insulating pattern125. Accordingly, contact resistance between the bit line BL and the channel patterns CP may be reduced, and as a result, electrical characteristics and reliability of the semiconductor memory device may be improved.

Hydrogen or deuterium included in the lower pattern HRP may diffuse to lower portions of the channel patterns CP to compensate for defects in the lattice structure below the channel patterns CP. Accordingly, contact resistance between the bit line BL and the channel patterns CP may be reduced, and as a result, electrical characteristics and reliability of the semiconductor memory device may be improved.

Again, referring toFIGS.4A to4C, the bit lines BL may be electrically connected to the first circuit transistors CT through the connection wiring structure IS. For example, the bit lines BL may be electrically connected to the peripheral circuit wirings PCL through the lower contact plugs LCT, the first connection wirings CM1, and the first connection contact plugs CMC1, and the peripheral circuit wirings PCL may be electrically connected to the first circuit transistors CT through the peripheral circuit contact plugs PCT.

In some embodiments, at least some of the first circuit transistors CT may constitute the sense amplifier (4ofFIG.1). The first circuit transistors CT constituting the sense amplifier (4ofFIG.1) may overlap the cell array (1ofFIG.1) including the memory cells (MC ofFIG.1) of the channel patterns CP in the vertical direction (the Z direction). In addition, the lower contact plugs LCT, the first connection wirings CM1, the first connection contact plugs CMC1, the peripheral circuit wirings PCL, and the peripheral circuit contact plugs PCT forming an electrical connection path between the bit line BL and the first circuit transistors CT constituting the sense amplifier (4ofFIG.1) may overlap the memory cell array (1ofFIG.1) including the memory cells (MC ofFIG.1) constituted by the channel patterns CP in the vertical direction (the Z direction).

Accordingly, an electrical path between the memory cells (MC ofFIG.1) constituted by the channel patterns CP and the first circuit transistors CT, for example, an electrical path between the bit lines BL and the first circuit transistors CT may be located in the cell array region CAR to overlap the memory cell array (1ofFIG.1) including the memory cells (MC ofFIG.1) constituted by the channel patterns CP in the vertical direction (the Z direction), without passing through the peripheral circuit region PCR.

Accordingly, an electrical path between the vertical channel transistors and the first circuit transistors CT included in the selection devices (TR ofFIG.1) may be shortened, so that electrical characteristics and reliability of the vertical channel transistors and the first circuit transistors CT may be improved.

In addition, a region used for the first circuit transistors CT and an electrical path between the memory cells (MC ofFIG.1) and the first circuit transistors CT in a top view may be reduced, or a separate region is not required, thereby improving the degree of integration of the semiconductor memory device.

FIGS.7A and7Bare cross-sectional views of a semiconductor memory device according to embodiments. Specifically,FIG.7Ashows cross-sections taken along lines A-A′ and B-B′ ofFIG.4A,FIG.7Bshows cross-sections taken along lines C-C′, D-D′, and E-E′ ofFIG.4A, and the same descriptions as those of embodiments illustrated inFIGS.4A to4Care omitted in descriptions of embodiments illustrated inFIGS.7A and7B.

Referring toFIGS.4A,7A and7Btogether, a connection wiring structure ISa may be disposed on the peripheral circuit insulating layer110. The connection wiring structure ISa may include a second connection wiring structure IS2stacked on the first connection wiring structure IS1.

The first connection wiring structure IS1may include a first wiring insulating layer111, a second wiring insulating layer112stacked on the first wiring insulating layer111, first connection wirings CM1passing through the second wiring insulating layer112, and first connection contact plugs CMC1electrically connecting the peripheral circuit wirings PCL to the first connection wirings CM1through the first wiring insulating layer111.

The second connection wiring structure IS2may include a third wiring insulating layer113, a fourth wiring insulating layer114stacked on the third wiring insulating layer113, second connection wirings CM2passing through the fourth wiring insulating layer114, and second connection contact plugs CMC2electrically connecting the first connection wirings CM1to the second connection wirings CM2through the third wiring insulating layer113.

The second connection wirings CM2may include connection pads CPD and connection wiring lines CPL. The connection pads CPD may be electrically connected to or contact lower contact plugs LCT electrically connected to or contacting the bit lines BL, and the connection wiring lines CPL may extend in the same direction as an extension direction of the bit lines BL. The connection wiring lines CPL may extend in the first horizontal direction (the X direction). The lower contact plugs LCT may contact the connection pads CPD, but the lower contact plugs LCT may not contact the connection wiring lines CPL. Accordingly, the connection pads CPD may be electrically connected to the bit lines BL, but the connection wiring lines CPL may not be electrically connected to the bit lines BL.

In the peripheral circuit structure PS, the first circuit transistors CT may be arranged in the cell array region CAR of the semiconductor substrate100, and the second circuit transistors PT may be arranged in the peripheral circuit region PCR of the semiconductor substrate100. The first circuit transistors CT may include the first transistors CT1and second transistors CT2.

The bit lines BL may be electrically connected to the first transistors CT1, and the connection wiring lines CPL may be electrically connected to the second transistors CT2. For example, the bit lines BL may be electrically connected to the peripheral circuit wirings PCL through the lower contact plugs LCT, the connection pads CPD among the second connection wirings CM2, the second connection contact plugs CMC2, the first connection wirings CM1, and the first connection contact plugs CMC1, and the peripheral circuit wirings PCL may be electrically connected to the first transistors CT1through the peripheral circuit contact plugs PCT. For example, the connection wiring lines CPL may be electrically connected to the peripheral circuit wirings PCL through the second connection contact plugs CMC2, the first connection wirings CM1, and the first connection contact plugs CMC1, and the peripheral circuit wirings PCL may be electrically connected to the second transistors CT2through the peripheral circuit contact plugs PCT.

In some embodiments, the first transistors CT1may constitute the sense amplifier (4ofFIG.1), and the first transistors CT1may constitute the sub-word line driver (2ofFIG.1).

The first transistors CT1constituting the sense amplifier (4ofFIG.1) may overlap the memory cell array (1ofFIG.1) including the memory cells (MC ofFIG.1) constituted by the channel patterns CP in the vertical direction (the Z direction). In addition, the lower contact plugs LCT, the connection pads CPD among the second connection wirings CM2, the second connection contact plugs CMC2, the first connection wirings CM1, the first connection contact plugs CMC1, the peripheral circuit wirings PCL, and the peripheral circuit contact plugs PCT, forming an electrical connection path between the bit line BL and the first transistors CT1constituting the sense amplifier (4ofFIG.1), may overlap the memory cell array (1ofFIG.1) including the memory cells (MC ofFIG.1) constituted by the channel patterns CP in the vertical direction (the Z direction).

The second transistors CT2constituting the sub-word line driver (2ofFIG.1) may overlap the memory cell array (1ofFIG.1) including the memory cells (MC ofFIG.1) of the channel patterns CP in the vertical direction (the Z direction). In addition, the second connection contact plugs CMC2, the first connection wirings CM1, the first connection contact plugs CMC1, the peripheral circuit wirings PCL, and the peripheral circuit contact plugs PCT, forming an electrical connection path between the connection wiring lines CPL and the second transistors CT2constituting the sub-word line driver (2ofFIG.1) may overlap the memory cell array (1ofFIG.1) including the memory cells (MC ofFIG.1) constituted by the channel patterns CP in the vertical direction (the Z direction).

FIGS.8A,9A,10A,11A,12A,13A,14A, and15Aare plan views illustrating a method of manufacturing a semiconductor memory device, according to embodiments, andFIGS.8B.8C,9B,9C,10B,10C,11B,11C,12B,12C,13B,13C,14B,14C,15B,15C,16A,16B,17A,17B,18A,18B,19A, and19B are cross-sectional views illustrating a method of manufacturing a semiconductor memory device, according to embodiments.

Referring toFIGS.8A,8B, and8Ctogether, the peripheral circuit structure PS including the first circuit transistors CT and the second circuit transistors PT may be formed on the semiconductor substrate100.

The semiconductor substrate100may include the cell array region CAR and the peripheral circuit region PCR. In the cell array region CAR, the first circuit transistors CT may be formed on the semiconductor substrate100. In the peripheral circuit region PCR, the first circuit transistors CT may be formed on the semiconductor substrate100. The first circuit transistors CT and the second circuit transistors PT may include NMOS and PMOS transistors integrated on the semiconductor substrate100.

A peripheral circuit insulating layer110may be formed on the entire surface of the semiconductor substrate100. The peripheral circuit insulating layer110may surround the first circuit transistors CT, the second circuit transistors PT, and the peripheral circuit wirings PCL on the semiconductor substrate100. The peripheral circuit insulating layer110may include insulating layers stacked in multiple layers. The peripheral circuit insulating layer110may include, for example, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and/or a low-k layer.

The peripheral contact plugs PCT and peripheral circuit wirings PCL may be formed in the peripheral circuit insulating layer110. The peripheral contact plugs PCT and the peripheral circuit wirings PCL may be electrically connected to the first circuit transistors CT and the second circuit transistors.

The connection wiring structure IS may be formed on the peripheral circuit insulating layer110. The connection wiring structure IS may include the first wiring insulating layer111, the second wiring insulating layer112stacked on the first wiring insulating layer111, the first connection wirings CM1passing through the second wiring insulating layer112, and the first connection contact plugs CMC1passing through the first wiring insulating layer111to electrically connect the peripheral circuit wirings PCL to the first connection wirings CM1. After the first wiring insulating layer111and the first connection contact plugs CMC1are formed on the peripheral circuit insulating layer110, the second wiring insulating layer112and the first connection wirings CM1may be formed on the first wiring insulating layer111. In some embodiments, the first wiring insulating layer111and the second wiring insulating layer112may be formed together to form an integral body, e.g., one body without any boundary within the integral body. In some embodiments, the first connection wirings CM1and the first connection contact plugs CMC1may be formed together through a damascene process to form an integral body. For example, each of the first connection contact plugs CMC1may be formed as one body with one of the first connection wirings CM1without any boundary within the one body. In some embodiments, a cover insulating layer116may be formed on the second wiring insulating layer112of the connection wiring structure IS.

The bit lines BL may be formed on the connection wiring structure IS in the cell array region CAR. The bit lines BL may extend in the first horizontal direction (the X direction) and may be apart from each other in the second horizontal direction (the Y direction). The bit lines BL on the cell array region CAR may be formed by forming a lower insulating layer covering the entire surface of the semiconductor substrate100on the connection wiring structure IS or the cover insulating layer116, forming the lower contact plugs LCT electrically connected to or contacting the first connection wirings CM1through the lower insulating layer, depositing the lower conductive layer on the lower insulating layer, and then patterning the lower conductive layer and the lower insulating layer in the cell array region CAR. In an etching process for forming the bit lines BL, the lower insulating layer may be etched to form the lower insulating pattern118, and the cover insulating layer116may be exposed.

While the bit lines BL are formed, the lower conductive layer and the lower insulating layer may be patterned in the peripheral circuit region PCR to form the lower conductive patterns LCP. The lower conductive patterns LCP may be electrically connected to the first connection wirings CM1through the lower contact plugs LCT. The lower conductive patterns LCP and the bit lines BL are portions of the lower conductive layer and may each include the same conductive material. For example, the lower conductive patterns LCP and the bit lines BL may be formed of the same conductive material.

Referring toFIGS.9A,9B, and9Ctogether, after the bit lines BL are formed, the first insulating layer120defining the gap region GR is formed between the bit lines BL. The first insulating layer120may have a substantially uniform thickness and may be deposited on the entire surface of the semiconductor substrate100. For example, the first insulating layer120may be conformally formed on the substrate100, e.g., above the bit lines BL. A deposition thickness of the first insulating layer120may be less than half an interval between the bit lines BL adjacent to each other. As the first insulating layer120is deposited as described above, the gap region GR may be defined between the bit lines BL by the first insulating layer120. The gap region GR may extend in the first horizontal direction (the X direction) to be parallel with the bit lines BL. Before forming the first insulating layer120, the charging insulating pattern119may be filled between the lower conductive patterns LCP in the peripheral circuit region PCR.

After the first insulating layer120is formed, shielding structures SS filling at least a portion of the gap regions GR may be formed on the first insulating layer120. The shielding structures SS may be formed between the bit lines BL. The shielding structures SS may be formed by forming a shielding film on the first insulating layer120to fill the gap region GR and then recessing an upper surface of the shielding film. Upper surfaces of the shielding structures SS may be at a level lower than the upper surfaces of the bit lines BL. The shielding structures SS may include or be formed of, for example, a metal material such as tungsten (W), titanium (Ti), nickel (Ni), or cobalt (Co). Alternatively, the shielding structures SS may include or be formed of, for example, a conductive two-dimensional (2D) material, such as graphene.

In some embodiments, a space between the bit lines BL may be filled with the first insulating layer120without forming the shielding structures SS.

Referring toFIGS.10A,10B, and10Ctogether, after the insulating material layer is formed on the shielding structures SS, a planarization process may be performed on the insulating material layer and the first insulating layer, so that the upper surfaces of the bit lines BL are exposed, to form first insulating patterns121including a portion of the insulating material layer and a portion of the first insulating layer120between the bit lines BL and the shielding structures SS.

The mold insulating pattern125may be formed on the first insulating patterns121and the bit lines BL. The mold insulating pattern125may define trenches T that extend in the second horizontal direction (the Y direction) and are apart from each other in the first horizontal direction (the X direction). The trenches T may be formed across the bit lines BL and may expose portions of the bit lines BL. The mold insulating pattern125may include or be formed of an insulating material having etch selectivity with respect to the first insulating pattern121. The mold insulating pattern125may include or be formed of, for example, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and/or a low-k layer.

An interval between the channel patterns CP shown inFIGS.4A to4Cmay vary according to a width of the mold insulating pattern125, that is, an interval between the trenches T. Also, an interval between the first and second word lines WL1and WL2shown inFIGS.4A and4Cmay vary according to a width of the trenches T.

Referring toFIGS.11A,11B, and11Ctogether, a channel layer131may be formed to conformally cover the mold insulating pattern125having the trenches T. The channel layer131may contact the bit lines BL in the trenches T and cover an upper surface and sidewalls of the mold insulating pattern125. The channel layer131may cover the upper surface of the mold insulating pattern125, bottom surfaces and inner walls of the trenches T with a substantially uniform thickness. For example, the channel layer131may be conformally formed on the upper surface of the mold insulating pattern125, bottom surfaces and inner walls of the trenches T. The thickness of the channel layer131may be less than half the width of the trench T. The channel layer131may be formed to have a thickness of several nm to several tens of nm. For example, the channel layer131may be formed to have a thickness of about 1 nm to about 15 nm. In some embodiments, the channel layer131may be formed to a thickness of about 1 nm to about 10 nm. The channel layer131may include or be formed of a semiconductor material, an oxide semiconductor material, or a 2D semiconductor material.

A first sacrificial layer133filling the trenches T may be formed on the channel layer131. The first sacrificial layer133may have a substantially flat upper surface. The first sacrificial layer133may include or be formed of an insulating material having etch selectivity with respect to the mold insulating pattern125. In some embodiments, the first sacrificial layer133may be formed using a spin on glass (SOG) technology.

Referring toFIGS.12A,12B, and12Ctogether, a mask pattern MP may be formed on the first sacrificial layer133. The mask pattern MP may be located across the mold insulating pattern125and may have openings having a major axis (e.g., extending) in the first horizontal direction (the X direction). The openings of the mask pattern MP may be apart from each other in the second horizontal direction (the Y direction). The openings of the mask pattern MP may be located between the bit lines BL and overlap the shielding structures SS in a plan view (e.g., vertically overlap).

The first sacrificial layer133and the channel layer131may be sequentially etched using the mask pattern MP as an etching mask to form openings OP exposing the first insulating pattern121between the bit lines BL. The openings OP may overlap the shielding structures SS in a plan view. The openings OP may extend in the first horizontal direction (the X direction) and may be apart from each other in the second horizontal direction (the Y direction).

By forming the openings OP, the channel layer131may be separated into a plurality of pieces apart from each other in the second horizontal direction (the Y direction). After forming the openings OP, the mask pattern MP may be removed.

Referring toFIGS.12A,12B,12C,13A,13B, and13Ctogether, a second sacrificial layer filling the openings OP may be formed. The second sacrificial layer may include or be formed of the same material as that of the first sacrificial layer133.

After forming the second sacrificial layer, a planarization process may be performed on the first sacrificial layer133, the second sacrificial layer, and the plurality of separated channel layers131so that the upper surface of the mold insulating pattern125is exposed, thereby forming first sacrificial patterns135, second sacrificial patterns137, and channel patterns CP.

The channel patterns CP may be formed to be apart from each other in the first horizontal direction (the X direction) and the second horizontal direction (the Y direction). Each of the channel patterns CP may include a horizontal channel portion contacting the bit line BL and a pair of vertical channel portions extending from the horizontal channel portion and contacting sidewalls of each trench T. The channel patterns CP may be apart from each other in the first horizontal direction (the X direction) by the mold insulating pattern125and may be apart from each other in the second direction by the second sacrificial patterns137.

The first sacrificial pattern135may be formed on each channel pattern CP, and the second sacrificial pattern137may be formed between the channel patterns CP adjacent to each other in the second horizontal direction (the Y direction) and between the first sacrificial patterns135. After the channel patterns CP are formed, the first and second sacrificial patterns135and137may be removed to expose surfaces of the channel patterns CP.

Referring toFIGS.14A,14B, and14Ctogether, a gate insulating layer141, a gate conductive layer143, and a spacer layer145may be sequentially deposited to conformally cover the channel patterns CP. In some embodiments, a channel length of the vertical channel transistors may be adjusted according to a deposition thickness of the spacer layer145.

The gate insulating layer141, the gate conductive layer143, and the spacer layer145may be formed to cover the horizontal and vertical channel portions of the channel patterns CP with a substantially uniform thickness. The sum of the thicknesses of the gate insulating layer141, the gate conductive layer143, and the spacer layer145may be less than half the width of the trench T. The spacer layer145may define a gap space in the trench T and may be deposited on the gate conductive layer143.

The spacer layer145may include or be formed of an insulating material. The spacer layer145may include or be formed of, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SiC), silicon carbon nitride (SiCN), or a combination thereof.

Referring toFIGS.14A,14B,14C,15A,15B, and15Ctogether, an anisotropic etching process is performed on the spacer layer145to form a pair of first spacer SP1and second spacer SP2separated from each other on the gate conductive layer143.

Thereafter, a portion of the gate conductive layer143may be removed to form a pair of first word lines WL1and second word lines WL2separated from each other in each trench T. The first word lines WL1and the second word lines WL2may be formed by performing an anisotropic etching process on the pair of gate conductive layers143using the pair of first and second spacers SP1and SP2as an etch mask.

Upper surfaces of the first word lines WL1and the second word lines WL2may be at a vertical level lower than the upper surface of the channel pattern CP. In some embodiments, an etching process may be additionally performed to remove upper portions of the first word lines WL1and the second word lines WL2.

During the anisotropic etching process for the gate conductive layer143, a portion of the gate insulating layer141may be removed together to expose a horizontal channel portion of the channel pattern CP. A portion of the gate insulating layer141may be removed to form first gate insulating patterns Gox1and second gate insulating patterns Gox2.

In another embodiment, during the anisotropic etching process for the gate conductive layer143, the horizontal channel portion of the channel pattern CP may be etched to expose portions of the bit lines BL in each trench, and a pair of first channel patterns (CP1ofFIG.5C) and second channel patterns (CP2inFIG.5C) and a pair of gate insulating patterns (Gox1inFIG.5C) and second gate insulating patterns (Gox2inFIG.5C) separated from each other may be formed in each trench.

Referring toFIGS.16A and16Btogether, a first capping layer150may be conformally formed on the entire surface of the semiconductor substrate100. The first capping layer150may include or be formed of, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SiC), silicon carbon nitride (SiCN), and/or a combination thereof.

The first capping layer150may cover the surface of the channel patterns CP between the first word line WL1and the second word line WL2. In another embodiment, before forming the first capping layer150, the first spacers SP1and the second spacers SP2may be removed, so that the first capping layer150may directly cover surfaces of the first word line WL1and the second word line WL2.

Subsequently, a second insulating layer152covering the first capping layer150and a second capping layer154may be sequentially formed. The second insulating layer152may include or be formed of an insulating material, different from that of the first capping layer150. The second capping layer154may include or be formed of the same material as that of the first capping layer150. In some embodiments, the second capping layer154may be omitted.

Referring toFIGS.17A and17Btogether, a planarization process may be performed on the first capping layer150, the second insulating layer152, and the second capping layer154so that the upper surface of the mold insulating pattern125is exposed, thereby forming the first capping pattern151, the second insulating pattern153, and the second capping pattern155. The upper surface of the second capping pattern155and an upper surface of the mold insulating pattern125may be coplanar with each other.

After forming the first capping pattern151, the second insulating pattern153, and the second capping pattern155, an etch stop layer160may be formed on the entire surface of the semiconductor substrate100. The etch stop layer160may include or be formed of an insulating material having etch selectivity with respect to the mold insulating pattern125. The etch stop layer160may include or be formed of, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SiC), silicon carbon nitride (SiCN), a combination thereof, or the like.

After the etch stop layer160is formed, lower conductive vias LVP may be formed to be electrically connected to and/or contact the lower conductive pattern LCP through the mold insulating pattern125in the peripheral circuit region PCR.

Referring toFIGS.17A,17B,18A, and18Btogether, after the lower conductive vias LVP is formed, a mask pattern exposing the cell array region CAR may be formed on the etch stop layer160, and the etch stop layer160may be subsequently etched using the mask pattern as an etch mask to expose an upper surface of the mold insulating pattern125and the upper surfaces of the channel patterns CP of the cell array region CAR.

Subsequently, an etching process may be performed on portions of the channel patterns CP so that upper surfaces of the channel patterns CP are located at a vertical level lower than the upper surface of the mold insulating pattern125, thereby forming recess regions between the mold insulating pattern125and the first gate insulating patterns Gox1and the second gate insulating patterns Gox2. The upper surfaces of the channel patterns CP may be at a vertical level lower than the upper surfaces of the first word lines WL1and the second word lines WL2.

Referring toFIGS.18A,18B,19A, and19Btogether, the conductive layer170may be patterned to form landing pads LP that are in contact with the vertical portions of the channel patterns CP and are arranged to be apart from each other. Upper conductive patterns UCP electrically connected to and/or contact the lower conductive vias LVP may be formed in the peripheral circuit region PCR together with the landing pads LP.

After the landing pads LP and the upper conductive patterns UCP are formed, a third insulating pattern165filling the space between the landing pads LP and the upper conductive patterns UCP may be formed.

Subsequently, referring toFIGS.4A,4B, and4Ctogether, an etch stop layer171covering the upper surfaces of the landing pads LP and the upper conductive patterns UCP may be formed.

Data storage patterns DSP may be respectively formed on the landing pads LP. The data storage patterns DSP may pass through the etch stop layer171to contact the landing pads LP, respectively. In some embodiments, when the data storage patterns DSP include capacitors, lower electrodes, a capacitor dielectric layer, and an upper electrode may be sequentially formed, and the lower electrodes may pass through the etch stop layer171to be electrically connected to and/or contact the landing pads LP, respectively.

After the data storage patterns DSP are formed, a capping insulating layer173covering the entire surface of the semiconductor substrate100may be formed. The upper conductive vias UVP may pass through the capping insulating layer173in the peripheral circuit region PCR to be electrically connected to and/or contact the upper conductive patterns UCP. Connection lines CL electrically connected to and/or contact the upper conductive vias UVP may be formed on the capping insulating layer173in the peripheral circuit region PCR.

It will be understood that when an element is referred to as being “connected” or “coupled” to or “on” another element, it can be directly connected or coupled to or on the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, or as “contacting” or “in contact with” another element (or using any form of the word “contact”), there are no intervening elements present at the point of contact.

Even though different figures show variations of exemplary embodiments and different embodiments disclose different features from each other, these figures and embodiments are not necessarily intended to be mutually exclusive from each other. Rather, certain features depicted in different figures and/or described above in different embodiments can be combined with other features from other figures/embodiments to result in additional variations of embodiments, when taking the figures and related descriptions of embodiments as a whole into consideration. For example, components and/or features of different embodiments described above can be interchangeably combined with components and/or features of other embodiments unless the context indicates otherwise.