Semiconductor integrated device for preventing breakdown and degradation of a gate oxide film caused by charge-up in manufacturing steps thereof, design method thereof, designing apparatus method thereof, and maunfacturing apparatus thereof

Semiconductor integrated circuit that prevents breakdown and degradation of a gate oxide film caused by charge-up in manufacturing steps thereof is provided. The circuit includes a gate 12 provided insulated from a transistor diffusion layer 11, wirings 13 and 14 connected to the gate 12, a wiring 15 parallel to and adjacent to the wiring 13, and a wiring 16 connected to the wiring 15. The gate area of the gate 12 is indicated by G_Area, and the gate capacitance of the gate 12 is indicated by G_Cap. The areas of the wirings 13, 14, 15, and 16 are indicated by MG1_Area, MG2_Area, M1_Area, and M2_Area, respectively, and a parasitic capacitance between the wirings 13 and 15 is indicated by M1_Cap. An antenna ratio R1 calculated from the areas is given by an equation R1={(MG1_Area+MG2_Area)+α(M1_Area+M2_Area)}/G_Area. α is a parameter determined by a function of the G_Cap and the M1_Cap. Layout of the wirings is performed so that a relation R1<L1 (which is a specified value that causes damage to a gate oxide film).

FIELD OF THE INVENTION

The present invention relates to a semiconductor integrated device, a design method thereof, a designing apparatus thereof, a program thereof, a manufacturing method thereof, and a manufacturing apparatus thereof. More specifically, the invention relates to the semiconductor integrated device for preventing breakdown and degradation of a gate oxide film caused by charge-up in manufacturing steps thereof, design method thereof, designing apparatus thereof, program thereof, manufacturing method thereof, and manufacturing apparatus thereof.

BACKGROUND OF THE INVENTION

In manufacturing steps of semiconductor integrated circuits, a technology employing plasma or an ion beam is used. In such steps, when a wiring of the semiconductor integrated circuit is the one that is not connected to a diffusion layer connected to a gate electrode, charges are accumulated on the wiring. Then, the amount of the charges exceeds a certain amount, the breakdown or degradation of the gate oxide film is caused, or degradation in the performance of a transistor is caused. Such a phenomenon is referred to as an antenna effect.

In order to prevent charge-up damage to the gate oxide film caused by the antenna effect, it has become a common practice to limit the area of the wiring directly connected to a gate or the peripheral length of the wiring converted to the area of the wiring, according to the area or capacitance of the gate, at the time of designing the semiconductor integrated circuit. A measure against the charge-up is thereby taken.

FIG. 9is a diagram showing a layout of wiring in a conventional semiconductor integrated circuit. Referring toFIG. 9, a gate102is arranged for a diffusion layer101of a transistor. The gate area of the gate102is indicated by G_Area. The area of a wiring103directly wired to the gate102is indicated by MG1_Area. Further, the area of a wiring104in other layer, directly wired to the gate102is indicated by MG2_Area. In this case, ratio given by (MG1_Area+MG2_Area)/G_Area is referred to as an antenna ratio. Incidentally, the antenna ratio may also be a ratio of respective peripheral lengths of the wirings to that of the gate, in place the ratio of their areas. When designing the semiconductor integrated circuit, the wirings103and104directly wired to the gate102are arranged so that the antenna ratio becomes smaller than a predetermined value L.

As a specific example of the wiring arrangement, insertion of a repeater cell or a diode cell to the wiring is performed when the antenna ratio exceeds a predetermined value (refer to Patent Document 1, for example). Further, there is also known a method in which part of the wiring is wired in other wiring layer such as an uppermost wiring layer when the antenna ratio exceeds the predetermined value (refer to Patent Documents 1, 2, and 4). Further, there is also a method of using a cell in which the size of the transistor has been adjusted or to which a new transistor has been added so that the area of the gate based on the antenna ratio becomes a predetermined value or more (refer to Patent Document 3, for example).

SUMMARY OF THE DISCLOSURE

As smaller device geometries are achieved in a semiconductor process, however, the influence of parasitic capacitance between wirings will increase. Thus, it has become difficult to obtain the semiconductor integrated circuit that is sufficiently stable with respect to the antenna effect. For this reason, the need for performing design with a certain allowance with respect to the conventional antenna ratio is generated. The area of the wiring directly connected to the gate would be thereby limited more than necessary. In other words, this results in heavy use of insertion of the repeater cell or the diode cell to the wiring, wiring in the uppermost wiring layer, utilization of the cell in which the size of the transistor has been adjusted or to which the new transistor has been added so that the area of the gate becomes the predetermined value or more or the like. Accordingly, it has more often occurred that sufficient reduction in the size of a chip cannot be achieved.

The inventor of the present invention has noticed that as the smaller device geometries in the semiconductor process have been achieved, there is seen a problem of the charge-up that cannot be solved just by using the conventional method of placing a constraint on the wiring directly connected to the gate. Then, the inventor has found that the semiconductor integrated device should be designed and manufactured also in consideration of the influence of the charge-up through the interconnect capacitance on a wiring adjacent to the wiring directly connected to the gate. The present invention thus has been made.

A design method according to an aspect of the present invention is the method of designing a wiring layout for a semiconductor device by a designing apparatus. In this method, the layout of first to (n+1)th wirings is performed so that an area ratio of an area of an electrode of an element provided insulated from a diffusion layer to a sum of an area of a first wiring connected to the electrode and a summation of areas of the first to nth wirings each multiplied by a predetermined coefficient akbecomes equal to or less than a predetermined value that gives charge-up damage to an insulating film of the electrode, where the k is an integer equal to or larger than one, ranging from one to n, (n being an integer equal to or larger than one). The (k+1)th wiring is provided in parallel to or adjacent to the kth wiring.

A manufacturing method according to an aspect of the present invention is the method of manufacturing a semiconductor integrated device by a manufacturing apparatus. In this method, the semiconductor integrated device is manufactured so that an area ratio of a sum of an area of a first wiring plus the summation of all the areas of a (k+1)th wiring multiplied by a predetermined coefficient ak, (k being an integer equal to or larger than one that) ranging from one to n, (n being an integer equal to or larger than one) to an area of an electrode of an element becomes less than an antenna ratio determined from a manufacturing condition of the manufacturing apparatus. The first wiring is connected to the electrode of the element. The electrode of the element is provided insulated from a diffusion layer. The (k+1)th wiring is parallel to and adjacent to the kth wiring.

A semiconductor integrated device according to an aspect of the present invention includes an element having an electrode provided insulated from a diffusion layer, a first wiring connected to the electrode, and a (k+1)th wiring parallel to and adjacent to a kth wiring (k being an integer equal to or larger than one). The first to (k+1)th wirings are arranged so that the area ratio of the a sum of an area of the first wiring plus a summation of areas of wirings from a second wiring to the (k+1)th wiring to the area of the electrode becomes equal to or less than a predetermined value that gives charge-up damage to the insulating film of the electrode. The summation of the areas of the wiring from the second electrode to the (k+1)th wiring are given as a summation of all the areas of the wirings from the second wiring to the (k+1)th wiring each multiplied by a predetermined coefficient ak, where k ranges from one to n (n being an integer equal to or larger than one).

A designing apparatus according to one aspect of the present invention includes:

a circuit data storage unit for storing circuit data on a semiconductor integrated device targeted for design;

a layout execution unit for reading out the circuit data stored in the circuit data storage unit, for execution of circuit arrangement and wiring, and delivering the result of the arrangement and the wiring to a wiring check unit as layout data, the layout execution unit also changing a wiring condition and executing the circuit arrangement and wiring again when the layout data checked by the wiring check unit does not satisfy an antenna condition, and storing the layout data in a layout data storage unit when the layout data satisfies the antenna condition;

a wiring check unit for checking whether an area ratio of a sum of an area of a first wiring plus a summation of all the areas of a (k+1)th wiring multiplied by a predetermined coefficient ak, (k being an integer equal to or larger than one) ranging from one to n (n being an integer equal to or larger than one), to the area of an electrode is equal to or less than a predetermined value that gives charge-up damage to the insulating film of the electrode, and notifying the result of the check to the layout execution unit, the first wiring being connected to the electrode provided insulated from the diffusion layer of an element in the semiconductor integrated circuit, the (k+1)th wiring being parallel to and adjacent to the kth wiring; and

a layout data storage unit for storing the layout data satisfying the antenna condition.

A manufacturing apparatus according to an aspect of the present invention includes:

a layout data storage unit for storing layout data on a semiconductor integrated device targeted for manufacturing;

a wiring check unit for checking whether the area ratio of a sum of an area of a first wiring plus a summation of all the areas of a (k+1)th wiring multiplied by a predetermined coefficient ak, (k being an integer equal to or larger than one) ranging from one to n (n being an integer equal to or larger than one), to the area of an electrode is equal to or less than a predetermined value that gives charge-up damage to the insulating film of the electrode based on the layout data, and delivering the result of the check to a manufacturing condition comparing unit, the first wiring being connected to the electrode provided insulated from the diffusion layer of an element in the semiconductor integrated circuit, the (k+1)th wiring being parallel to and adjacent to the kth wiring;

a manufacturing condition data storage unit for storing manufacturing conditions for the manufacturing;

the manufacturing condition comparing unit for comparing an antenna ratio obtained by the wiring check unit with an antenna ratio stored in the manufacturing condition data storage unit, notifying a semiconductor integrated device manufacturing unit to manufacture the semiconductor integrated device according to a predetermined one of the manufacturing conditions when the antenna ratio obtained by the wiring check unit satisfies the antenna ratio stored in the manufacturing condition data storage unit as a result of the comparison, and notifying the semiconductor integrated device manufacturing unit to adjust the predetermined one of the manufacturing conditions when the antenna ratio obtained by the wiring check unit does not satisfy the antenna ratio stored in the manufacturing condition data storage unit; and

a semiconductor integrated device manufacturing unit for manufacturing the semiconductor integrated device according to the predetermined one of the manufacturing conditions or the adjusted manufacturing condition.

A program according to an aspect of the present invention is the program for a computer, for performing layout of first to (n+1)th wirings (n being an integer equal to or larger than one). This program causes the computer to function as:

layout means for performing layout on circuit data of a semiconductor integrated device targeted for design and storing the result of the layout in layout data storage means as layout data;

wiring information extracting means for extracting from the layout data stored in the layout data storage means electrode information on an element having an electrode provided insulated from a diffusion layer and wiring information on a first wiring connected to the electrode, for storage in electrode wiring information storage means;

parallel wiring information extracting means for extracting the (k+1)th wiring parallel to and adjacent to the kth wiring (k being an integer from one to n) from the layout data stored in the layout data storage means and the wiring information on the first wiring stored in the electrode wiring information storage means, for storage in parallel wiring information storage means;

area and capacitance extracting means for extracting from the layout data stored in the layout data storage means areas of the first to (k+1)th wirings, a parasitic capacitance between the kth wiring and the (k+1)th wiring, a capacitance of the electrode, and the area of the electrode all stored in the electrode wiring information storage means and the parallel wiring information storage means, for storage in area and capacitance storage means;

antenna ratio checking means for calculating an area ratio of the a sum of areas of the wirings to an area of the electrode, the sum of the areas of the wirings being given as a sum of an area of the first wiring stored in the area and capacitance storage means plus a summation of areas of the (k+1)th wiring multiplied by a predetermined coefficient ak, where k ranges from one to n (n being an integer equal to or larger than one), and comparing the area ratio with a predetermined value stored in antenna ratio condition storage means; and

layout modification means for changing the layout of at least one wiring of the first to (n+1)th wirings when it is found that the area ratio is larger than the predetermined value.

According to the present invention, as a measure against an antenna effect, the semiconductor integrated device is designed and manufactured also in consideration of an influence caused by charge-up on the wiring or the like adjacent to the wiring connected to the gate. Accordingly, even if smaller device geometries is pursued in a semiconductor process, the high-quality semiconductor integrated device having wirings with the proper measure against the antenna effect taken therein and without device degradation can be obtained.

PREFERRED EMBODIMENTS OF THE INVENTION

A semiconductor integrated device according to an embodiment mode of the present invention is a circuit designed and manufactured also in consideration of the influence of charge-up through an interconnect capacitance on a wiring or the like adjacent to and in parallel with a wiring connected to the gate of the semiconductor integrated device. More specifically, the semiconductor integrated circuit includes a gate (indicated by reference numeral12inFIG. 1) provided insulated from the diffusion layer (indicated by reference numeral11) of a transistor, a first wiring (indicated by reference numerals13and14inFIG. 1) connected to the gate (indicated by reference numeral12inFIG. 1), and a second wiring (indicated by reference numerals15and16inFIG. 1) adjacent to and parallel with the first wiring. Then, the semiconductor integrated device is designed so that the first wiring and the second wiring are arranged to make the ratio of the sum of the area of the first wiring and the area of the second wiring multiplied by a predetermined coefficient to the gate area of the gate to be equal to or less than a predetermined value that gives charge-up damage to the gate oxide film of the gate. The predetermined coefficient is the coefficient determined by the interconnect capacitance (parasitic capacitance) between the first wiring and the second wiring. Further, the semiconductor integrated device is manufactured so that an antenna ratio satisfies the antenna condition of a manufacturing apparatus for the semiconductor integrated device.

The semiconductor integrated device designed and manufactured as described above has wirings to which an appropriate measure against an antenna effect has been applied, so that device degradation is eliminated.

In the above description, the antenna ratio is obtained from the ratio among the areas. The area herein includes at least one of the surface (planar surface) areas of the wiring and a gate electrode and the side areas of the wiring and the gate electrode. The damage caused by the antenna effect is sometimes caused mainly by the side area of the wiring rather than the planar surface area of the wiring according to a manufacturing condition. Further, the damage caused by the antenna effect is also sometimes caused mainly by both of the planar surface area of the wiring and the side area of the wiring. When the damage caused by the antenna effect is mainly caused by the side area of the wiring, the antenna ratio may be determined from the side area of the wiring. Further, there is also included a case where the antenna ratio is obtained from a value obtained by adding the planar surface area to the side area multiplied by a predetermined ratio. When the thickness of a wiring film is constant, the area can also be converted from the peripheral length of the wiring.

The antenna effect occurs on a capacitance element as well as the transistor. It goes without saying that the present invention can be applied to the wiring connected to the electrode of the capacitance element such as the capacitance element between polysilicon and polysilicon or between polysilicon and a metal.

Further, at least one of the first wiring and the second wiring may be divided and wired across other layer. Further, when a plurality of wirings in parallel with and adjacent to the first or second wiring is present, and when a plurality of wirings or the like in parallel with and adjacent to any one of the plurality of wirings is present, the antenna ratio in view of the influences of these plurality of wirings may be obtained. Specific examples will be described below in more detail in connection with embodiments.

First Embodiment

FIG. 1is a diagram showing a layout of a semiconductor integrated circuit according to a first embodiment of the present invention. Referring toFIG. 1, a gate12is arranged insulated from the diffusion layer11of the transistor. A wiring13is directly wired to the gate12, and a wiring14connected to the wiring13is wired in other layer. A wiring15is arranged in parallel with the wiring13with a spacing d provided therebetween. Further, a wiring16connected to the wiring15is wired in other layer.

Herein, the gate area of the gate12is indicated by G_Area, the gate capacitance of the gate12is indicated by G_Cap, the peripheral length of the gate wiring of the gate12is indicated by G_Length. The area of the wiring13is indicated by MG1_Area, and the wiring peripheral length of the wiring13is indicated by MG1_Length. The area of the wiring14is indicated by MG2_Area, and the wiring peripheral length of the wiring14is indicated by MG2_Length. The area of the wiring15is indicated by M1_Area, and the wiring peripheral length of the wiring15is indicated by M1_Lenth. The area of the wiring16is indicated by M2_Area, and the wiring peripheral length of the wiring16is indicated by M2_Length. Further, a parasitic capacitance between the wiring13and the wiring15is indicated by M1_Cap.

An antenna ratio R1calculated from capacitances and the areas is given by R1=All_Metal_Area/G_Area, in which All_Metal_Area=(MG1_Area+MG2_Area)+α (M1_Area+M2_Area), and α is the parameter α=f(G_Cap, M1_Cap) determined by a function f of the G_Cap and the M1_Cap. In this case, the layout of the wirings is carried out so that a relation R1<L1(that is a specified value which causes damage to the gate oxide film) is satisfied.

The antenna ratio can also be obtained from the wiring peripheral lengths if the thickness of a wiring film is constant. An antenna ratio R2calculated from the capacitances and the wiring peripheral lengths is given by R2=All_Metal_Lenghth/G_Length, in which All_Metal_Length=(MG1_Length+MG2_Length+α (M1_Length+M2_Length). In this case, the layout of the wirings is carried out so that a relation R2<L2(that is a specified value which causes the damage to the gate oxide film) is satisfied.

When the specified value that causes the damage to the gate oxide film is not satisfied by the layout, the layout of the wirings is changed. A wiring spacing d between the wiring directly connected to the gate and the adjacent wiring, for example, is expanded. This reduces the parasitic capacitance M1_Cap, so that the antenna ratio is reduced. Alternatively, the wiring width of the wiring15is reduced. This reduces the area M1_Area of the wiring15, so that the antenna ratio is reduced. Alternatively, alteration of a wiring route is effective. Further, insertion of a repeater cell or a diode cell as described in a prior art or the like is performed.

The semiconductor integrated circuit having the layout designed as described above is designed and manufactured also in consideration of the influence of the charge-up on the wiring15in parallel with and adjacent to the wiring13directly connected to the gate12. Accordingly, even when smaller device geometries in a semiconductor process are achieved, the wirings with the appropriate measure against the antenna effect taken therein are included, so that the device degradation is eliminated.

Second Embodiment

FIG. 2is a diagram showing a layout of a semiconductor integrated circuit according to a second embodiment of the present invention. Referring toFIG. 2, the same reference numerals as those inFIG. 1indicate components identical to or corresponding to those inFIG. 1. The layout shown inFIG. 2is different from the layout inFIG. 1in that a wiring17is added. The wiring17is arranged in parallel with the wiring16in other layer, and the area of the wiring17is indicated by M22_Area. Further, a parasitic capacitance between the wiring16and the wiring17is indicated by M22_Cap.

An antenna ratio R3calculated from the areas and the capacitances in a configuration as described above is given by R3=All_Metal_Area/G_Area, in which All_Metal_Area=(MG1_Area+MG2_Area)+α (M1_Area+M2_Area)+β (M22_Area), and α is the parameter α=f1(G_Cap, M1_Cap) determined by a function f1of the G_Cap and the M1_Cap. β is the parameter β=f2(G_Cap, M1_Cap, M22_Cap) determined by a function f2of the G_Cap, M1_Cap, and M22_Cap. In this case, the layout of the wirings is carried out so that a relation R3<L1(that is the specified value which causes damage to the gate oxide film) is satisfied.

The antenna ratio calculated from the capacitances and the wiring peripheral lengths are considered in the same manner as in the first embodiment, in view of the wiring17. Further, in regard to a change in the layout of the wirings as well when the specified value that causes the damage to the gate oxide film is not satisfied, the change is performed in the same manner as in the first embodiment.

The semiconductor integrated circuit having the layout designed as described above is designed and manufactured also in consideration of the influence of the charge-up on the wiring15in parallel with and adjacent to the wiring13directly connected to the gate12and the influence of the charge-up on the wiring17in parallel with and adjacent to the wiring16connected to the wiring15. Accordingly, the semiconductor integrated circuit without the device degradation like that in the first embodiment can be obtained.

Third Embodiment

FIG. 3is a diagram showing a layout of a semiconductor integrated circuit according to a third embodiment of the present invention. Referring toFIG. 3, the same reference numerals as those inFIG. 2indicate components identical to or corresponding to those inFIG. 2. The layout shown inFIG. 3is different from the layout inFIG. 2in that a wiring18, a wiring19, a wiring20, and a wiring21are added.

The wiring18is wired adjacent to and in parallel to the wiring14in other layer. The area of the wiring18is indicated by MG22_Area. A parasitic capacitance between the wiring14and the wiring18is indicated by MG22_Cap. The wiring19is wired adjacent to and in parallel with the wiring15, and the area of the wiring19is indicated by M3_Area. A parasitic capacitance between the wiring15and the wiring19is indicated by M3_Cap. The wiring20is wired connected to the wiring19in other layer, and the area of the wiring20is indicated by M4_Area. The wiring21is wired adjacent to and in parallel with the wiring20in the other layer, and the area of the wiring21is indicated by M43_Area. A parasitic capacitance between the wiring20and the wiring21is indicated by M43_Cap.

An antenna ratio R4calculated from the areas and the capacitances in a configuration as described above is given by R4=All_Metal_Area/G_Area, in which All_Metal_Area=(MG1_Area+MG2_Area)+α (M1_Area+M2_Area)+β·MG22_Area+γ·M22_Area+δ (M3_Area+M4_Area)+ε·M43_Area. α is the parameter α=f1(G_Cap, M1_Cap) determined by the function f1of the G_Cap and the M1_Cap. β is the parameter β=f2(G_Cap, M22_Cap) determined by a function f2of the G_Cap and M22_Cap. γ is the parameter γ=f3(G_Cap, M1_Cap, M22_Cap) determined by a function f3of the G_Cap, the M1_Cap, and M22_Cap. δ is the parameter δ=f4(G_Cap, M1_Cap, M3_Cap) determined by a function f4of the G_Cap, M1_Cap, and M3_Cap. ε is the parameter ε=f5(G_Cap, M1_Cap, M3_Cap, M43_Cap) determined by a function f5of the G_Cap, M1_Cap, M3_Cap, and M43_Cap. In this case, the layout of the wirings is performed so that a relation R4<L1(that is the specified value which causes damage to the gate oxide film) is satisfied.

The antenna ratio calculated from the capacitances and the wiring peripheral lengths is considered in the same manner as in the second embodiment, in view of the wiring18, wiring19, wiring20, and wiring21. Further, in regard to a change in the layout of the wirings as well when the specified value that causes the damage to the gate oxide film is not satisfied, the change is performed in the same manner as in the first embodiment.

The semiconductor integrated circuit having the layout designed as described above is designed and manufactured also in view of the influence of the charge-up on the wiring17, wiring18, wiring19, wiring20, wiring21as well as the wiring15in parallel with and adjacent to the wiring13directly connected to the gate12. Accordingly, the semiconductor integrated circuit without the device degradation like the semiconductor integrated circuit in the first embodiment can be obtained.

In addition, even when an adjacent wiring is further increased, the increase is handled by performing expansion of a calculation formula as in the first to three embodiments.

Fourth Embodiment

Next, a designing apparatus of the semiconductor integrated circuit according to an embodiment of the present invention will be described.FIG. 4is a block diagram showing a configuration of the designing apparatus of the semiconductor integrated circuit according to the embodiment of the present invention. Referring toFIG. 4, the designing apparatus of the semiconductor integrated circuit includes a circuit data storage unit31, a layout execution unit32, a wiring check unit33, and a layout data storage unit34.

Using a system not shown, the circuit data storage unit31obtains circuit data on wiring information and the like in advance, for storage, based on information on the functions of the semiconductor integrated circuit and the like.

The layout execution unit32reads out the circuit data stored in the circuit data storage unit31, and executes arrangement and wiring for the circuit. The result of the arrangement and the wiring is delivered to the wiring check unit33as layout data. When the layout data for which check by the wiring check unit33has been completed does not satisfy the antenna condition based on the manufacturing steps of the semiconductor integrated circuit, the layout execution unit changes a wiring condition again, and executes the arrangement and the wiring for the circuit. When the layout data satisfies the antenna condition, the layout execution unit32stores the layout data in the layout data storage unit34.

The wiring check unit33makes a check on the antenna condition based on the layout data. That is, the wiring check unit33extracts a wiring directly connected to the gate, and extracts a wiring adjacent to and parallel with this wiring. Then, the wiring check unit33extracts the gate capacitance, gate area, areas of the wirings, and an interconnect capacitance between the wirings. Further, the wiring check unit obtains the antenna ratio in the gate, as described in the first to third embodiment, and checks whether the antenna ratio satisfies the specified vale that causes the damage to the gate oxide film (without violation) or not (in violation). The result of the check is notified to the layout execution unit32.

The layout data storage unit34stores the layout data that satisfies the antenna condition. This layout data is referred to when the semiconductor integrated circuit is manufactured.

Next, a design method of the semiconductor integrated circuit will be described.FIG. 5is a flowchart showing the design method of the semiconductor integrated circuit according to an embodiment of the present invention. When design is started, the layout execution unit32obtains from the circuit data storage unit31the circuit data necessary for the layout of the semiconductor integrated circuit targeted for the design at step S11.

At step S12, based on the obtained circuit data, the layout of the semiconductor integrated circuit is performed. At this point, the wiring check unit33is made to check whether the violation of the antenna ratio is present or not. When the violation of the antenna ratio has occurred, the layout of the wirings is changed. The spacing of the wirings is expanded, or the wiring route is altered, for example. Further, insertion of the repeater cell or the diode cell as described in the prior art is performed.

At step S13, a wiring directly connected to the gate is extracted.

At step S14, extraction of a wiring having a portion adjacent to and parallel with the wiring directly connected to the gate is extracted.

At step S15, the gate capacitance and gate area of the gate, areas of the wirings, and the interconnect capacitance between the wirings are extracted.

At step S16, the wiring check unit33obtains the antenna ratio and checks whether the antenna ratio satisfies the specified value that causes the damage to the gate oxide film (without the violation) or not (with the violation). When the violation is present, the operation is returned to the step S12. When the violation is not present, the layout is completed.

As described above, according to this embodiment, the layout of the semiconductor integrated circuit that satisfies the antenna ratio is performed, and the design of the semiconductor integrated circuit in sufficient consideration of the influence of the charge-up will be performed.

Fifth Embodiment

Next, a program for designing the semiconductor integrated circuit according to an embodiment of the present invention will be described.FIG. 6is a block diagram showing a configuration of the program for performing layout of wirings in the semiconductor integrated circuit according to the embodiment of the present invention. Referring toFIG. 6, the program for performing the layout of the wirings includes layout means42, wiring information extracting means44, parallel wiring information extracting means46, area and capacitance extracting means48, antenna ratio checking means51, and layout modification means52. As storage means for storing information used in the program, circuit data storage means41, layout data storage means43, electrode wiring information storage means45, parallel wiring information storage means47, area and capacitance storage means49, and antenna ratio condition storage means50are provided.

The layout means42performs layout for circuit data stored in the circuit data storage means41, and stores the result of the layout in the layout data storage means43. The layout data for the circuit such as a wiring width, a wiring length, and a capacitance between adjacent wirings is stored in the layout data storage means43. Information inFIG. 3shown before is a part of information stored as the layout data.

The wiring information extracting means44extracts from the layout data stored in the layout data storage means43information on an electrode provided insulated from the diffusion layer and information on a wiring connected to this electrode, and stores the result of extraction in the electrode wiring information storage means45. The electrode wiring information storage means45stores information on the gate12, wiring13, and wiring14in an example shown inFIG. 3.

The parallel wiring information extracting means46extracts a wiring having a portion parallel to the wiring connected to the electrode stored in the electrode wiring information storage means45from the layout data stored in the layout data storage means43. When a wiring having a portion parallel to the extracted wiring is further present, the parallel wiring information extracting means46extracts the wiring as well. Then, the parallel wiring information extracting means46extracts the predetermined number of parallel wirings one after another, and stores them in the parallel wiring information storage means47. The parallel wiring information storage means47stores information on each of the wiring15having a portion parallel to the wiring13, wirings16and18having portions parallel to the wiring14, the wiring19having a portion parallel to the wring15, and the wirings17and20having portions parallel to the wiring16, and the wiring21having a portion parallel to the wiring20in the example shown inFIG. 3.

The area and capacitance extracting means48extracts from the layout data stored in the layout data storage means43information shown in following (1) to (6), based on the information stored in the electrode wiring information storage means45and the information stored in the parallel wiring information storage means47, for storage in the area and capacitance storage means49. Specific reference values will be indicated, using the case ofFIG. 3as an example.(1) the capacitance and area of an electrode insulated from the diffusion layer. In the case ofFIG. 3, G_Area, G_Cap.(2) the area of a wiring connected to the electrode insulated from the diffusion layer. In the case ofFIG. 3, MG1_Area, MG2_Area.(3) the area of a wiring having a portion parallel to the wiring connected to the electrode insulated from the diffusion layer. In the case ofFIG. 3, M1_Area, M2_Area, and MG22_Area.(4) the area of a wiring having a portion parallel to the wiring in (3). When there is another wiring having a portion parallel to this wiring, the area of the wiring. In the case ofFIG. 3, M3_Area, M4_Area, M22_Area, M43_Area.(5) an adjacent parasitic capacitance between the wiring in (2) and the wiring in (3). In the case ofFIG. 3, M1_Cap, MG22_Cap.(6) an adjacent parasitic capacitance between the wiring in (3) and the wiring in (4). In the case ofFIG. 3, M3_Cap, M22_Cap, M43_Cap.

The antenna ratio checking means51calculates the antenna ratio from information stored in the area and capacitance storage means49, and compares the calculated antenna ratio with a predetermined antenna ratio stored in the antenna ratio condition storage means50, which gives the charge-up damage to the insulating film of the electrode. In the case ofFIG. 3, calculation of the antenna ratio is performed, as in the third embodiment.

The layout modification means52performs wiring modification on the layout data stored in the layout data storage means43when the result of comparison by the antenna ratio checking means51shows the violation (or the calculated antenna ratio exceeds the antenna ratio stored in the antenna ratio condition storage means50).

The program configured as described above is executed by a computer constituting the designing apparatus. According to the program as described above, layout of the semiconductor integrated circuit that satisfies the antenna ratio is performed. The design of the semiconductor integrated circuit in sufficient consideration of the influence of the charge-up will be performed.

Sixth Embodiment

Next, a manufacturing apparatus of the semiconductor integrated circuit according to an embodiment of the present invention will be described.FIG. 7is a block diagram showing a configuration of the manufacturing apparatus of the semiconductor integrated circuit according to the embodiment of the present invention. Referring toFIG. 7, the manufacturing apparatus of the semiconductor integrated circuit includes a layout data storage unit61, a wiring check unit62, a manufacturing condition data storage unit63, a manufacturing condition comparing unit64, and a semiconductor circuit manufacturing unit65.

The layout data storage unit61stores layout data for the semiconductor integrated circuit targeted for manufacturing.

The wiring check unit62extracts a wiring directly connected to the gate based on the layout data and extracts a wiring adjacent to and in parallel with this wiring. Then, the wiring check unit62extracts the gate capacitance, gate area, areas of the wirings, and an interconnect capacitance between the wirings, and obtains the antenna ratio as described in the first to third embodiment. Information on the obtained antenna ratio is delivered to the manufacturing condition comparing unit64.

The manufacturing condition data storage unit63determines conditions in the manufacturing steps of the manufacturing apparatus such as the antenna ratio determined from a plasma condition, in advance, for storage.

The manufacturing condition comparing unit64compares the antenna ratio obtained by the wiring check unit62with the antenna ratio stored in the manufacturing condition data storage unit63. When it is found as the result of comparison that the antenna ratio obtained by the wiring check unit62satisfies the antenna ratio stored in the manufacturing condition data storage unit63, the manufacturing condition comparing unit64notifies the semiconductor circuit manufacturing unit65that the semiconductor integrated circuit should be manufactured according to the manufacturing conditions determined in advance. When it is found that the antenna ratio is not satisfied, the manufacturing condition comparing unit64notifies the semiconductor circuit manufacturing unit65that adjustment of the manufacturing conditions such as adjustment of reducing a plasma etching speed or the like should be made. Alternatively, when it is found that the antenna ratio is not satisfied, an approach may be used in which data on a plurality of manufacturing conditions is stored in advance, and an optimal condition is selected from the plurality of manufacturing conditions according to the antenna ratio.

The semiconductor circuit manufacturing unit65manufactures the semiconductor circuit using the steps of mask manufacture, wafer process execution, assembly, and the like, according to the manufacturing conditions, thereby completing the semiconductor integrated circuit.

Next, a manufacturing method of the semiconductor integrated circuit will be described.FIG. 8is a flowchart showing the manufacturing method of the semiconductor integrated circuit according to an embodiment of the present invention. After the start of the operation, the wiring check unit62obtains from the layout data storage unit61the layout data of the semiconductor integrated circuit targeted for manufacturing, at step S21.

At step S22, the wiring directly connected to the gate is extracted from the layout data.

At step S23, the wiring having the portion adjacent to and parallel with the wiring directly connected to the gate is extracted from the layout data.

At step S24, the gate capacitance and gate area of the gate and the areas of the wirings and the interconnect capacitance between the wirings are extracted.

The manufacturing condition comparing unit64obtains the antenna ratio determined by the layout of the wirings, for comparison with the antenna ratio determined from the manufacturing conditions (such as the plasma condition) of the semiconductor integrated circuit. When the antenna ratio in the layout of the wirings is smaller than the antenna ratio determined from the manufacturing conditions (without the violation), the operation proceeds to step S27. When the antenna ratio is larger (which is the violation of the antenna ratio), the operation proceeds to the step S26.

At step S26, the manufacturing condition comparing unit64notifies the semiconductor circuit manufacturing unit65that adjustment of the manufacturing conditions such as reduction of the plasma etching speed should be made, for example.

At step S27, the semiconductor circuit manufacturing unit65manufactures the mask of the semiconductor integrated circuit.

At step S28, using the manufactured mask, a wafer process such as diffusion and plasma etching is performed on the semiconductor integrated circuit based on the manufacturing conditions.

At step S29, wafer cutting is performed, and wiring and the like are performed, thereby assembling the semiconductor integrated circuit.

At step S30, the semiconductor integrated circuit is completed.

As described above, according to this embodiment, a semiconductor integrated circuit without the device degradation, in sufficient consideration of the influence caused by the charge-up so as to satisfy the antenna ratio determined from the manufacturing conditions will be manufactured.

According to the present invention, the following specific modes are further realized.Mode 1. A designing apparatus for a semiconductor integrated device comprising: a circuit data storage unit for storing circuit data on a semiconductor integrated device targeted for design; a layout execution unit for reading out the circuit data stored in said circuit data storage unit, for execution of circuit arrangement and wiring, and delivering a result of the arrangement and the wiring to a wiring check unit as layout data, said layout execution unit also changing a wiring condition and executing the circuit arrangement and wiring again when the layout data checked by said wiring check unit does not satisfy an antenna condition, and storing the layout data in a layout data storage unit when the layout data satisfies the antenna condition; a wiring check unit for checking whether an area ratio of a sum of an area of a first wiring plus a summation of all areas of a (k+1)th wiring multiplied by a predetermined coefficient ak, (k being an integer equal to or larger than one) ranging from one to n, (n being an integer equal to or larger than one) to an electrode of an element is equal to or less than a predetermined value that gives charge-up damage to an insulating film of said electrode, and notifying a result of the check to said layout execution unit, said first wiring being connected to said electrode of said element, said electrode of said element being provided insulated from a diffusion layer of an element in said semiconductor integrated circuit, the (k+1)th wiring being parallel to and adjacent to the kth wiring; and a layout data storage unit for storing the layout data satisfying the antenna condition.Mode 2. The designing apparatus for a semiconductor integrated device according to Mode 1, wherein each of the areas includes at least one of a surface area and a side area.Mode 3. The designing apparatus for a semiconductor integrated device according to Mode 1, wherein the predetermined coefficient akis a value determined from an electrode capacitance of said electrode and each wiring capacitance between the mth wiring and the (m+1)th wiring (m being an integer ranging from one to k).Mode 4. The designing apparatus for a semiconductor integrated circuit according to Mode 1, wherein at least one of said first to (k+1)th wirings is wired across two or more wiring layers.Mode 5. The designing apparatus for a semiconductor integrated circuit according to Mode 1, wherein each of the second to (k+1)th wirings comprises j wires (j being an integer equal to or larger than one).Mode 6. A manufacturing apparatus for a semiconductor integrated device comprising: a layout data storage unit for storing layout data on said semiconductor integrated device targeted for manufacturing; a wiring check unit for checking whether an area ratio of a sum of an area of a first wiring plus a summation of all areas of a (k+1)th wiring multiplied by a predetermined coefficient ak, (k being an integer equal to or larger than one) ranging from one to n,(n being an integer equal to or larger than one), to an electrode area of an electrode is equal to or less than a predetermined value that gives charge-up damage to an insulating film of said electrode based on the layout data, and delivering a result of the check to a manufacturing condition comparing unit, said first wiring being connected to said electrode provided insulated from a diffusion layer of an element in said semiconductor integrated circuit, the (k+1)th wiring being parallel to and adjacent to the kth wiring; a manufacturing condition data storage unit for storing manufacturing conditions for the manufacturing; a manufacturing condition comparing unit for comparing an antenna ratio obtained by said wiring check unit with an antenna ratio stored in said manufacturing condition data storage unit, notifying a semiconductor integrated device manufacturing unit to manufacture said semiconductor integrated device according to a predetermined one of the manufacturing conditions when the antenna ratio obtained by said wiring check unit satisfies the antenna ratio stored in said manufacturing condition data storage unit as a result of the comparison, and notifying said semiconductor integrated device manufacturing unit to adjust the predetermined one of the manufacturing conditions when the antenna ratio obtained by said wiring check unit does not satisfy the antenna ratio stored in said manufacturing condition data storage unit; and a semiconductor integrated device manufacturing unit for manufacturing said semiconductor integrated device according to the predetermined one of the manufacturing conditions or the adjusted manufacturing condition.Mode 7. The manufacturing apparatus for a semiconductor integrated device according to Mode 6, wherein each of the areas includes at least one of a surface area and a side area.Mode 8. The manufacturing apparatus for a semiconductor integrated device according to Mode 6, wherein the predetermined coefficient akis a value determined from an electrode capacitance of said electrode and each wiring capacitance between the mth wiring and the (m+1)th wiring (m being an integer ranging from one to k).Mode 9. The manufacturing apparatus for a semiconductor integrated circuit according to Mode 6, wherein at least one of said first to (k+1)th wirings is wired across two or more wiring layers.Mode 10. The manufacturing apparatus for a semiconductor integrated circuit according to Mode 6, wherein each of the second to (k+1)th wirings comprises j wires (j being an integer equal to or larger than one).Mode 11. A computer program for performing layout of first to (n+1)th wirings (n being an integer equal to or larger than one), said computer program causing a computer to function as: layout means for performing layout on circuit data of a semiconductor integrated device targeted for design and storing a result of the layout in layout data storage means as layout data; wiring information extracting means for extracting from the layout data stored in said layout data storage means electrode information on an element having an electrode provided insulated from a diffusion layer and wiring information on a first wiring connected to said electrode, for storage in electrode wiring information storage means; parallel wiring information extracting means for extracting the (k+1)th wiring parallel to and adjacent to the kth wiring (k being an integer from one to n) from the layout data stored in said layout data storage means and the wiring information on said first wiring stored in said electrode wiring information storage means, for storage in parallel wiring information storage means; area and capacitance extracting means for extracting from the layout data stored in said layout data storage means areas of said first to (k+1)th wirings, a parasitic capacitance between the kth wiring and the (k+1)th wiring, a capacitance of said electrode, and an area of said electrode all stored in said electrode wiring information storage means and said parallel wiring information storage means, for storage in area and capacitance storage means; antenna ratio checking means for calculating an area ratio of a sum of areas of the wirings to an area of said electrode, said sum of the areas of the wirings being given as a sum of an area of said first wiring stored in said area and capacitance storage means plus a summation of areas of the (k+1)th wiring multiplied by a predetermined coefficient ak, where k ranges from one to n (n being an integer equal to or larger than one), and comparing the area ratio with a predetermined value stored in antenna ratio condition storage means; and layout modification means for changing the layout of at least one wiring of said first to (n+1)th wirings when it is found that the area ratio is larger than the predetermined value.Mode 12. The program according to Mode 11, wherein the predetermined coefficient akis a value determined from the capacitance of said electrode and the parasitic capacitance between the mth wiring and the (m+1)th wiring, m being an integer ranging from one to k.