Multi-processor system receiving input from a pre-fetch buffer

Multi-processor systems and methods are disclosed that employ a pre-fetch buffer to provide data fills to a source processor in response to a request. A pre-fetch buffer retrieves data as a uncached data fill. The source processor processes the data in response to a source request.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is related to the following commonly assigned co-pending patent applications entitled: “COHERENT SIGNAL IN A MULTI-PROCESSOR SYSTEM,” application Ser. No. 10/756,636; “MULTI-PROCESSOR SYSTEMS AND METHODS FOR BACKUP FOR NON-COHERENT SPECULATIVE FILLS,” application Ser. No. 10/756,637; “CACHE SYSTEMS AND METHODS FOR EMPLOYING SPECULATIVE FILLS,” application Ser. No. 10/756,638; “REGISTER FILES SYSTEMS AND METHODS FOR EMPLOYING SPECULATIVE FILLS,” application Ser. No. 10/756,644; “SYSTEMS AND METHODS FOR EXECUTING ACROSS AT LEAST ONE MEMORY BARRIER EMPLOYING SPECULATIVE FILLS,” application Ser. No. 10/756,639; “MULTI-PROCESSOR SYSTEM UTILIZING SPECULATIVE SOURCE REQUESTS,” application Ser. No. 10/756,640; “SOURCE REQUEST ARBITRATION,” application Ser. No. 10/755,919; “SYSTEMS AND METHODS FOR EMPLOYING SPECULATIVE FILLS,” application Ser. No. 10/755,938; “CONSISTENCY EVALUATION OF PROGRAM EXECUTION ACROSS AT LEAST ONE MEMORY BARRIER,” application Ser. No. 10/756,534 all of which are filed contemporaneously herewith and are incorporated herein by reference.

BACKGROUND

Multiprocessor systems employ two or more computer processors that can communicate with each other, such as over a bus or a general interconnect network. In such systems, each processor may have its own memory cache (or cache store) that is separate from the main system memory that the individual processors can access. Cache memory connected to each processor of the computer system can often enable faster access to data than if accessed from the main system memory. Caches are useful because they tend to reduce latency associated with accessing data on cache hits, and they work to reduce the number of requests to system memory. In particular, a write-back cache enables a processor to write changes to data in the cache without simultaneously updating the contents of memory. Modified data can be written back to memory at a later time.

Another technique for reducing processor latency times is pre-fetching. Pre-fetching is the providing of data, such as processor instructions, from a first memory location (e.g., main memory) to a second, more accessible memory location (e.g., a dedicated pre-fetch buffer) before the information is required by the processor. The pre-fetch buffer “anticipates” the data that will be required by the processor, retrieving data according to a pre-fetching algorithm. Proper selection of the pre-fetched data can significantly reduce the access time of the processor for the required data.

Coherency protocols have been developed to ensure that whenever a processor reads or writes to a memory location it receives the correct or true data. Additionally, coherency protocols help ensure that the system state remains deterministic by providing rules to enable only one processor to modify any part of the data at any one time. If proper coherency protocols are not implemented, however, inconsistent copies of data can be generated.

SUMMARY

One embodiment of the present invention may comprise a system that employs a pre-fetch buffer to provide uncached data fills to a source processor in response to a request. A pre-fetch buffer retrieves data as a uncached data fill. The source processor processes the data in response to a source request.

Another embodiment of the present invention may comprise a multiprocessor system having a pre-fetch buffer that stores uncached data fills associated with a pre-fetch request. A source processor receives an uncached data fill from the pre-fetch buffer in response to a source request and executes with the uncached data fill. The system employs a cache coherency protocol that returns a coherent copy of the data fill and a coherent signal in response to the source request.

Yet another embodiment of the present invention may comprise a multiprocessor system comprising means for executing program instructions associated with a source processor. The system may further comprise means for retrieving a data fill, having an associated state, from at least one other processor without changing the associated state of the data fill. The system may further comprise means for storing the retrieved data fill at a buffer to be provided to the means for executing and means for providing a coherent signal that indicates if the retrieved data fill is coherent at the time it is provided to the means for executing.

Still another embodiment of the invention may comprise a method for utilizing data at a pre-fetch buffer. A copy of a data fill is stored in a pre-fetch buffer. The copied data fill is provided to a processor associated with the pre-fetch buffer in response to the source request. It is then determined If the copied data fill is coherent at the time when the copied data fill is provided to the processor.

DETAILED DESCRIPTION

This disclosure relates generally to multi-processor communication systems and methods. The systems and methods employ one or more pre-fetch buffers, each of which can be operative to acquire a desired data fill prior to a source request from an associated processor. A data fill refers to a copy of a memory block associated with a given cache line. A given pre-fetch buffer can acquire a data fill without filtering the state of other processing units and nodes within the system, such that the processing unit presently in possession of the data, the “owner” node, can continue to read and modify the data. This is referred to as an uncached fill. When the pre-fetch buffer acquires the data, the acquired data can be a coherent copy or a non-coherent copy of the desired data. A coherent copy of data is a copy that is determined to be the latest or most up to date version. When the processor retrieves the data from the pre-fetch buffer, the copy acquired by the pre-fetch buffer may no longer be a coherent copy due to subsequent changes to the data by the owner node.

In response to a source request, the pre-fetch buffer provides the data to the processor as a speculative fill. A speculative fill is a data fill that is not known to be coherent. The processor generates a source request to obtain a coherent copy of the data fill from the system. The system provides a coherent signal to the processor, indicating whether the pre-fetched speculative fill is coherent. Once the coherent signal is returned, the source can continue execution if the speculative fill is the same as the coherent fill or backup and re-execute instructions with a coherent copy if the speculative fill is different from the coherent fill. The systems and methods can be employed in multi-processor system utilizing a cache coherency protocol. The coherent signal can be part of or work in cooperation with the cache coherency protocol.

FIG. 1depicts an example of a system10that can utilize one or more pre-fetch buffers12and14in combination with a coherent signal to unobtrusively pre-fetch data for one or more associated processors16and18(indicated as PROCESSOR 1 through PROCESSOR N, where N is a positive integer (N>1)). A given pre-fetch buffer (e.g.,12) determines one or more blocks of data that are likely to be needed by its associated processor (e.g.,16) based upon the current activity of the processor (e.g., current program instruction execution). For example, where a processor16has failed to find a desired data block in its cache, its associated pre-fetch buffer12can obtain one or more additional blocks of data related to the desired data block (e.g., spatially proximate in memory, subsequent in a known pattern of access, etc.) from a system memory22. It will be appreciated that the blocks of data can represent executable program instructions for the processors. A variety of pre-fetch algorithms of varying complexity can be utilized to select the related data in accordance with the present invention. The memory22can be implemented as a globally accessible aggregate memory. For example, the memory22can include a one or more memory storage devices (e.g., dynamic random access memory (DRAM)).

The processors16and18and memory22define nodes in the system that can communicate with each other via requests and corresponding responses through a system interconnect24. For example, the system interconnect24can be implemented as a switch fabric or a hierarchical switch. Also associated with the system10can be one or more other nodes, indicated schematically at26. The other nodes26can correspond to one or more other multi-processor systems connected to the system interconnect24, such as through an appropriate interconnect interface (not shown.)

Each of the processors16and18includes at least one corresponding cache30and32. For purposes of brevity, each of the respective caches30and32are depicted as unitary memory devices, although they may include a plurality of memory devices or different cache levels. Each of the caches30and32contains a plurality of cache lines. Each cache line has an associated address that identifies corresponding data stored in the line. The cache lines can also include information identifying the state of the data for the respective lines.

The system thus employs the caches30and32and the memory22to store books of data, referred to herein as “memory blocks” or “data fills”. A memory block or data fill can occupy part of a memory line, an entire memory line or span across multiple lines. For purposes of simplicity of explanation, however, it will be assumed that a “memory block” occupies a single “memory line” in memory or a “cache line” in a cache. Additionally, a given memory block can be stored in a cache line of one or more caches as well as in a memory line of the memory22.

The system10implements a cache coherency protocol to manage the sharing of memory blocks so as to guarantee coherence of data. The cache coherency protocol of the system10utilizes a plurality of states to identify the state of each memory block stored in a respective cache line and the memory22. The coherency protocol establishes rules for transitioning between states, such as if data is read from or written to memory22or one of the caches30and32.

As used herein, a node that issues a request, such as a read or write request, defines a source node. Other nodes within the system10are potential targets of the request. Additionally, each memory block in the system10can be assigned a “home node” that maintains necessary global information and a data value for that memory block. The home node can be defined as a processor (or central processing unit), associated cache and associated memory/directory.

For example, when a source node, such as a processor16, requires a copy of a given memory block, it typically first requests the memory block from its local, private cache (e.g.,30) by identifying the address associated with the memory block. If the data is not in the cache, the processor can search its local pre-fetch buffer (e.g.,12) for a copy of the data. If the data is found locally, the memory access is resolved without communication via the system interconnect24. Where the requested memory block is not found locally, the source node16can request the memory block from the system10, including the memory22. In addition to the request identifying an address associated with the requested memory block, the request usually identifies the type of request or command being issued by the requester.

By way of example, assume that the processor16(a source node) requires a copy of data associated with a particular address, and assume that the data is unavailable from its own local cache30and pre-fetch buffer12. Since the processor16is unable to access the data in its local cache30, the processor16, as the source node, transmits a source request to other nodes and memory22via the system interconnect24. For example, the request can correspond to a source read request for a memory block associated with the address identified in the request. The request also can identify what type of request is being issued by source node16. In the illustrated example, a pre-fetch request for data from a related address accompanies the source request.

In a directory based cache coherency protocol, the pre-fetch request is transmitted from the source processor16to a home node in the system10. The home node retains location information (e.g., in a directory) of the owner of the requested cache lines representing the requested data. The home node provides a forward signal to the owner. The owner then responds with a coherent copy of the requested data, which is received by the requester and stored in the pre-fetch buffer12. The pre-fetch request does not result in a change in the state of the requested data. For example, the pre-fetch request can return a copy of the data to the pre-fetch buffer while allowing the desired cache lines to retain their existing state with regard to the plurality of processors. This copy, taken outside of the normal coherency protocols, is referred to as an uncached fill.

If the data provided to the pre-fetch buffer12is not required by the processor16, it is eventually overwritten by new data. If the data is required, however, it may be accessed some time after it was originally obtained. The data could be changed by the owner node during the intervening interval, such that the copy of the data stored in the pre-fetch buffer is no longer a coherent copy. Accordingly, the possibly outdated data can be provided to the processor as a speculative fill. A speculative fill is a data fill that may or may not be the latest version of the memory block. The use of a speculative fill allows the requesting processor to execute several thousands of program instructions ahead prior to receiving a coherent copy of the requested memory block.

The source processor16reads the speculative data fill from the pre-fetch buffer and begins executing the provided instructions. While the instructions are being processed, the processor16sends a source request for a coherent copy of the provided data to the home node. This request can change the associated state of the data in accordance with the cache coherency protocol of the system10. The home node provides a forward signal to the owner. The owner then provides a coherent copy of the requested data to the home node, which compares it with the speculative data fill provided by the pre-fetch buffer12.

If the speculative fill from the pre-fetch buffer matches the coherent copy, a coherent signal is provided to the source processor16indicating that the speculative data fill from the pre-fetch buffer12is a coherent copy of the data. The processor16continues execution uninterrupted, mitigating the latency that would have resulted had the processor remained in an idle state until the coherent copy was received. If the coherent copy does not match the pre-fetched speculative fill (e.g., the data had been altered during the intervening interval), the coherent fill is provided to the processor16along with a coherent signal indicating that the coherent fill is a coherent copy of the data. The processor16then backs up and begins executing again with the new data, but loses little or no time from the execution of the speculative fill as the processor16would have remained latent during the retrieval of the coherent copy regardless. The cache coherency protocol can continue executing after the coherent copy is retrieved to change states of one or more copies of the memory block in the system based on the request (e.g., read, write) of the processor16.

FIG. 2depicts an example of a multiprocessor computing system50. The system50, for example, includes an SMP (symmetric multi-processor) node52that includes processors (P1, P2, P3, P4)54,56,58and60in communication with each other via an interconnect62. The interconnect62facilitates transferring data between processors and memory of the system50. While four processors54,56,58and60are depicted in the example ofFIG. 2, those skilled in the art will appreciate that a greater or smaller number of processors can be implemented in the node52.

Each processor54,56,58and60includes a pre-fetch buffer64,66,68, and70that obtains data that may be required by its respective processor within a predetermined interval. Generally, pre-fetch requests are sent out about the same time as fill requests by a processor (e.g.,54). Appropriate data for each of the pre-fetch buffers64,66,68, and70is determined according to respective pre-fetch algorithms that identify data related to that requested by the processor in the fill request. For example, the pre-fetch algorithm can select data that is spatially proximate to the desired data in memory or subsequent to the desired data in a known pattern (e.g., every tenth block or every hundredth block can be selected).

Each processor54,56,58, and60also includes an associated cache72,74,76and78. The caches72,74,76and78can enable faster access to data than is available from an associated main memory80of the node52. The system50implements a cache coherency protocol designed to guarantee coherency of data in the system. By way of example, the cache coherency protocol can be implemented to include a source protocol in which requests for data are transmitted to a home node, which retains owner information in a directory associated with a given cache line.

The memory80can include multiple memory modules (M1, M2, M3, M4)82,84,86and88. For example, the memory80can be organized as a single address space that is shared by the processors54,56,58, and60as well as other nodes90of the system50. Alternatively, each memory module82,84,86and88can be associated with a respective one of the processors54,56,58, and60. Each of the memory modules82,84,86and88can include a corresponding directory92,94,96and98that defines how the memory blocks are apportioned in each respective module as well as where the corresponding coherent copy of data should reside in the system50. The coherent copy of data, for example, may reside in the home memory module or, alternatively, in a cache of one of the processors54,56,58, and60.

The other node(s)90can include one or more other SMP nodes associated with the SMP node52via the interconnect62. For example, the interconnect62can be implemented as a switch fabric or hierarchical switch programmed and/or configured to manage transferring requests and responses between the processors54,56,58, and60and the memory80, as well as those to and from the other nodes90.

When data desired by a processor (e.g.,56) is not available from its associated cache, the processor56can receive speculative copies or fills of the desired data from its associated pre-fetch buffer. The source processor can employ the speculative copy to execute several thousands of instructions ahead prior to receiving a coherent version of the data. The processor56then issues a source request (e.g., a read request or write request) to the system50. A home node responds to the request by providing a forwarding signal to an owner processor. The owner processor returns a coherent copy of the data fill. The system50also returns a coherent signal that indicates that the copy returned from the owner processor is the coherent version of the requested data. If the coherent data fill is different from the pre-fetched speculative fill, the processor can back up and re-execute program instructions with the new data. If the coherent data fill is the same as the speculative fill, the processor can continue execution of new program instructions.

FIG. 3illustrates a network100having a source processor102, a pre-fetch buffer104, a owner node106, and a home node108.FIG. 3illustrates various interrelationships between requests and responses and state transitions that can occur for a given memory address in different memory devices or caches. In the illustrated example, time flows in the direction of an arrow labeled “TIME”. The illustrated relationships focus on the acquisition of a cache line from the owner node106by the source processor102via a source read request. The cache line can assume a number of states with respect to the source processor102, the owner node106and other nodes and processors in the multi-processor system. These states are summarized in the following table:

TABLE 1STATEDESCRIPTIONIInvalid - The cache line is not present in the processorcache.SShared - The cache line is valid and unmodified by cachingprocessor. Other processors may have valid copies.EExclusive - The cache line is valid and unmodified bycaching processor. The caching processor has the onlycached copy in the system.MModified - The cache line is valid and has been modified bythe caching processor. The caching processor has the onlycached copy in the system.

In the illustrated example, the cache line is initially exclusive to the owner node, such that the owner node is in an exclusive state and the source node is in an invalid state. During a cache miss or other trigger incident, the pre-fetch buffer104can generate a pre-fetch request that requests an uncached fill of the cache line from the owner node. An uncached fill is the retrieval of a copy of a particular item of data outside of the cache coherency protocol of the system, such that data is retrieved without changing the state associated with the data. The pre-fetch buffer104can contain a plurality of pre-fetched cache lines for use by an associated source processor102. The cache lines stored can be selected according to a pre-fetch algorithm associated with the pre-fetch buffer104. The owner node106returns the requested uncached fill, but the cache line remains in an exclusive state.

The source processor provides a speculative fill request to the pre-fetch buffer104in response to a cache miss on the cache line. The pre-fetch buffer provides the buffered copy of the cache line to the processor102as a speculative fill. The pre-fetched copy is a speculative fill because it is unknown at the time the copy is sent to the requesting processor102if the pre-fetched copy is coherent. The source processor102executes the provided speculative fill, but also generates a source read request to a home node108to request a coherent copy of the cache line. The home node or processor108determines the owner106of the cache line requested from a home directory, and forwards the request to the owner106. The owner106replies by providing a coherent fill of the requested cache line to the source processor102. The cache line then assumes a shared state as the owner node106no longer has an exclusive copy of the cache line.

A coherent signal accompanies the coherent fill of the cache line provided to the source processor102. The coherent signal is an indicator that provides an indication to the source that the copy provided by the owner is the coherent version of the cache line. In the example ofFIG. 3, the coherent signal is provided by the owner. However, the coherent signal can be provided by control logic associated with the multi-processor system, by the home node or processor108or by some other structure in the multi-processor system. The coherent signal can be a structure such as a data packet, or a tag associated with each data fill that is marked to indicate which of the data fills are coherent, or a tag associated with only the coherent version of the cache line. The coherent signal can be a mask or vector that indicated which portions (e.g., data fields, data quantums, data blocks) of a data fill are coherent. Additionally, the coherent signal can be a mask or vector that indicates which of a plurality of responses to a plurality of requests have returned coherent copies. The coherent signal can be sent prior to, after or concurrently with the coherent version of the cache line.

Once the source processor102receives the coherent signal, the source processor has a verified copy of the cache line shared with at least the owner node. A comparison of the coherent fill and the speculative fill provided by the pre-fetch buffer104is performed to determine the coherency of the speculative fill. If the coherent data fill is different from the speculative fill, the source processor102can back up to its state prior to the speculative fill and start executing again with the coherent data. If the coherent data fill is the same as the speculative fill, the source processor can continue execution.

FIG. 4illustrates a block diagram of a miss address file (MAF) entry150that can be employed to track data fills received in response to a source request. A MAF entry is generated by a source each time a source processor generates a source request. The MAF entry150contains fields associated with outstanding source requests corresponding to respective cache lines. The MAF fields can include the cache line address being requested152, the copy of the latest fill block154returned by the system and a flag156that provides an indication of whether or not the coherent signal has been received. Other entries or fields can be employed to maintain information associated with a given cache line broadcast request.

During operation, the field for the latest fill block154is filled by a speculative fill from the pre-fetch buffer, if the desired data is available in the pre-fetch buffer. Otherwise, the entry is filled by a first response from a system source request. A system source request can produce multiple responses, including a coherent fill of the data and one or more speculative fills from other processor caches. Each time a new fill is received, the source determines if new fill is the same as the data fill in the MAF entry150. If the new fill is different, the source replaces the previous data fill with the new fill. If the new data fill is different from the speculative fill used by the source processor to continue execution, the processor may backup and re-execute program instructions. This may be the case if it is determined that a subsequent fill is more likely coherent than the original fill employed by the processor to continue execution.

The source also checks to see if the state of the coherent flag156has changed indicating that the coherent signal has been received. Once the coherent flag156changes state, the source can compare the coherent fill154stored in the MAF entry150with the speculative fill used to continue execution of the processor to determine if execution should continue or whether the processor needs to re-execute the program instructions.

FIG. 5illustrates a processor system200that employs a pre-fetch buffer202. The system200includes an execution engine204that is executing instructions associated with a processor pipeline205. During a load or store instruction, the execution engine204searches a local cache206to determine if a desired cache line resides in the local cache206. If the cache line does not reside in the local cache206, the execution engine204initiates a cache miss to the pre-fetch buffer202and a request engine208. In response to the cache miss, the pre-fetch buffer is searched for a copy of the desired cache line. If a copy is available, it is provided directly to the request engine208as a speculative data fill. If no copy is available in the pre-fetch buffer202, the request engine208can retrieve one or more cache lines related to the desired cache line as uncached fills and store them in the pre-fetch buffer for later use by the processor.

The speculative fill is stored in a copy of the latest fill block field in the MAF entry210by the request engine208. A fill control component214retrieves a copy of the speculative fill from the MAF entry210and provides the speculative fill to the processor pipeline205. The processor pipeline205employs the speculative fill to continue execution of program instructions. The request engine208creates a MAF entry210in response to the cache miss. The MAF entry210can be implemented as a table, an array, a linked list or other data structure programmed to manage and track requests for each cache line. The MAF entry210includes fields that identify, for example, the address of the data being requested, the type of request, and response information received from other nodes in response to the request. The request engine208thus employs the MAF entry210to manage requests issued by the request engine208as well as responses to such requests.

The request engine208sends a system source request through a system interconnect212to obtain a coherent copy of the cache line. In response to the system source request, the system can provide a number of additional data fills to the request engine. As new fills are received from the system, the request engine208continues storing the new fills in the copy of latest fill block field of the MAF entry210overwriting the previous fills. These subsequent data fills can be ignored. Alternatively, if the subsequent data fill is different from the speculative fill used by the source processor to continue execution, the processor can backup and re-execute program instructions. This may be the case if it is determined that a subsequent fill is more likely coherent than the original fill employed by the processor to continue execution.

The fill control component214monitors a coherent flag field in the MAF entry210to determine if the coherent flag has changed state, which is an indication that the coherent signal has been received. Once the coherent signal is received from the system, the request engine208changes the state of the coherent flag field in the MAF entry210.

The fill control214detects the change in the state of the coherent fill and retrieves a copy of the latest fill block, which corresponds to the coherent version of the data fill. The fill control214then compares the speculative fill provided by the fill control214to the processor pipeline205with the coherent fill. If the coherent data fill is different from the speculative fill, the fill control214provides the coherent fill to the processor pipeline205. The processor pipeline205can back up and start executing program instructions again with the new coherent data. If the coherent data fill is the same as the speculative fill, the fill control214provides the coherent signal to the processor pipeline205indicating that the processor pipeline205has already been provided with the coherent data. The processor pipeline205can continue execution, until another load or store instruction is encountered.

In view of the foregoing structural and functional features described above, certain methods will be better appreciated with reference toFIGS. 6 and 7. It is to be understood and appreciated that the illustrated actions, in other embodiments, may occur in different orders and/or concurrently with other actions. Moreover, not all illustrated features may be required to implement a method. It is to be further understood that the following methodologies can be implemented in hardware (e.g., as one or more integrated circuits or circuit boards containing a plurality of microprocessors), software (e.g., as executable instructions running on one or more processors), or any combination thereof.

FIG. 6depicts a method300for obtaining data in a pre-fetch buffer and providing the pre-fetched data as a speculative fill for an associated processor. At302, a pre-fetch algorithm determines data of potential interest to the processor according to the present activity of the processor. For example, the pre-fetch algorithm can determine the address of the data block presently being processed by the processor and locate data blocks that are spatially proximate in memory or subsequent in a known pattern of access to the current block.

At304, a coherent copy of the data of interest is retrieved from an associated owner node as an uncached fill at a first point in time. In an uncached fill, the state of the data or cache line is not changed. Thus, the data can be altered by other processors in the multiprocessor system while the uncached copy is held at the pre-fetch buffer. At306, the pre-fetch buffer holds the retrieved copy until it is overwritten or retrieved by its associated processor. If the processor does not retrieve the data, the data is overwritten and the method ends. If the processor does require the data, the method advances to308, where the pre-fetched copy of the data of interest is provided to the processor. The processor can be provided with the pre-fetched copy at a second point in time, some time after the first time.

At310, the processor begins executing the pre-fetched copy of the data. At312, the process transmits a source request to the system for a coherent copy of the data. The coherent copy will be provided through the normal cache coherency protocol of the system. Accordingly, the state of the data or cache line can be changed based on the source request type (e.g., read or write) and the cache coherency protocol that is employed.

At314, it is determined if the coherent copy of the data matches the pre-fetched copy. If the copies match (Y), a coherent signal is sent to the processor at316. The coherent signal indicates to the processor that the executed pre-fetched copy of the data is a coherent copy, and the processor continues processing the pre-fetched data. The method then ends. If the copies do not match (N), the method proceeds to318, where the processor is restored to its state at the time at which the processor began processing the pre-fetched copy. This can be accomplished via one or more structures (e.g., memory cache structures) for recording the state of the processor registers at the time of the fill and the changes to the associated cache. At320, the processor is provided with a coherent copy of the data for processing. A coherent signal can be sent to the processor to indicate that the copy is a coherent copy. The method then ends.

FIG. 7depicts a method350for providing pre-fetched data to a processor. At352, a copy of a data fill is stored in a pre-fetch buffer. At354, the copied data fill is provided to a processor associated with the pre-fetch buffer in response to a source request. At356, it is determined if the copied data fill is coherent.