PLL circuit, method, and electronic apparatus

A PLL circuit includes a frequency divider dividing an oscillation signal to generate a divided signal having a cycle of T/M (M: an integer greater than one); a phase comparator generating M reference signals by sequentially delaying a reference signal having a cycle of T one after another by a predetermined delay time and generating an Exclusive OR calculation result of the M reference signals and the divided signal; a loop filter generating a voltage signal based on the Exclusive OR calculation result input thereto; a voltage-controlled oscillator generating the oscillation signal by oscillating at a frequency in accordance with the voltage signal; and a control circuit adjusting the predetermined delay time to be equal to T/2M based on an Exclusive OR calculation result of at least two of the M reference signals.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2014-172919, filed on Aug. 27, 2014, the entire contents of which are incorporated herein by reference.

FIELD

The embodiment discussed herein is related to a PLL circuit, a method of controlling the PLL circuit, and an electronic apparatus.

BACKGROUND

The phase noise characteristics of a signal generated by a Phase Locked Loop (PLL) circuit are used as an index indicating the purity of the signal. The phase noise of the PLL circuit is the characteristic that influences the performance of the radio apparatus using the PLL circuit therein, so that the phase noise of the PLL circuit is an important performance index for the PLL circuit.

The PLL circuit generally includes a phase comparator, a loop filter, a voltage-controlled oscillator (VCO), and a frequency divider. The frequency divider divides the frequency of the oscillation signal output from the VCO into 1/N frequency, and outputs the divided signal (frequency divided signal). The phase comparator compares the phases between the reference signal from the reference oscillator and the divided signal, and outputs the signal indicating the phase comparison result. The loop filter integrates the signal indicating the phase comparison result, and supplies a voltage signal having a voltage level corresponding to the integration result to the VCO. The VCO oscillates at the frequency based on the voltage signal. In the case where the frequency difference between the reference signal and the divided signal becomes zero when the VCO oscillates based on the voltage signal generated by the loop filter, the voltage of the voltage signal converges to a constant voltage and the PLL circuit is in a locked state.

References are made to Japanese Laid-open Patent Publication Nos. 05-308283 and 2011-119903.

SUMMARY

According to an aspect of the present invention, a PLL circuit includes a frequency divider dividing an oscillation signal to generate a divided signal having a cycle of T/M (M: an integer greater than one); a phase comparator generating M reference signals by sequentially delaying a reference signal having a cycle of T one after another by a predetermined delay time and generating an Exclusive OR calculation result of the M reference signals and the divided signal; a loop filter generating a voltage signal based on the Exclusive OR calculation result input thereto; a voltage-controlled oscillator generating the oscillation signal by oscillating at a frequency in accordance with the voltage signal; and a control circuit adjusting the predetermined delay time to be equal to T/2M based on an Exclusive OR calculation result of at least two of the M reference signals.

The objects and advantages of the embodiments disclosed herein will be realized and attained by means of the elements and combinations particularly pointed out in the claims.

DESCRIPTION OF EMBODIMENT

FIG. 1illustrates typical phase noise characteristics in a PLL circuit. In the figure, the horizontal axis indicates frequency and the vertical axis indicates power of phase noise. The frequency “f0” is the oscillation frequency of the PLL circuit. The phase noise of the PLL circuit can be classified into the phase noise of the area10, the phase noise of the area11, and the phase noise of the area12. As the phase noise of the area10, the phase noise of the reference oscillator is dominant. As the phase noise of the area11, the phase noise of the phase comparator is dominant. As the phase noise of the area12, the phase noise of the VCO is dominant. Here, those phase noises occur mainly caused by thermal noise of resistors, fluctuations of the current flowing through active devices, etc.

Among those phase noises, the phase noise of the area11largely influences the performance of the radio apparatus. Theoretically, the phase noise “SPLL” of the area11can be expressed by the following Formula (1).
SPLL≈SPD/Kd2·N2Formula (1)

Here, the “SPD” denotes the output noise of the phase comparator, the “Kd” denotes the gain of the phase comparator, and the “N” denotes the frequency division ratio of the frequency divider. As described, those three factors mainly determine the phase noise of the area11. According to Formula (1), it is understood that by reducing the frequency division ratio “N”, the phase noise of the area11can be reduced.

In a general-purpose PLL circuit, the frequency of the reference signal and the frequency of the divided signal are set to be equal to each other. On the other hand, in order to reduce the phase noise by reducing the frequency division ratio “N”, there is a technique in which plural (M) phase comparators are arranged in parallel so that the frequency division ratio “N” can be reduced to 1/M. In this technique, when the frequency division ratio is set to “N/M”, the phase noise can be reduced by 1/M2times.

However, when the plural (M) phase comparators are arranged in parallel, the circuit area and energy consumption are increased accordingly. Further, in this case, plural (M) reference signals are generated to compare plural (M) phases. Due to this, the spurious characteristics of the PLL circuit may be degraded depending on the accuracies between the plural reference signals.

In light of the above problem, it is desired to provide a PLL circuit having good characteristics of the phase noise with a simple circuit configuration.

According at least one embodiment of the present invention, it becomes possible to provide a PLL circuit having good characteristics of the phase noise with a simple circuit configuration.

FIG. 2illustrates an example configuration of a PLL circuit according to an embodiment. The PLL circuit ofFIG. 2includes a reference oscillator20, a phase comparator21, a loop filter22, a VCO23, a frequency divider24, a delay error detector25, an AD converter26, a signal processor27, and a DA converter28. InFIG. 2and other figures similar toFIG. 2, note that a boundary between a circuit or functional block illustrated as a block and another circuit or functional block basically refers to a functional boundary, and may not correspond to any of physical positional separation, electrical signal separation, control theoretical separation, etc. Each circuit and functional block may be provided as a single hardware module which is physically separated from any other blocks to some extent, or may indicate one function integrated in a single hardware module which physically includes any other block as well.

The frequency divider24divides an oscillation signal output from the VCO23, and generates a divided signal (frequency-divided signal) “fd”. The phase comparator21compares the phases between a reference signal “fref1” from the reference oscillator20and the divided signal “fd”, and outputs a signal “out4” indicating the phase comparison result (e.g., a signal based on the phase difference). The loop filter22integrates the signal “out4” indicating the phase comparison result, and supplies a voltage signal having a voltage level corresponding to the integration result. The VCO23oscillates at the frequency based on the voltage signal from the loop filter22. In a case where the phase difference between the reference signal “fref1” and the divided signal “fd” becomes zero when the VCO23oscillates based on the voltage signal generated by the loop filter22, the voltage of the voltage signal converges to a constant voltage and the PLL circuit is in a locked state.

More specifically, the frequency divider24performs frequency division on the oscillation signal from the VCO23, and generates the divided signal “fd” having a cycle of T/M. Here, “M” is an integer greater than one. In this example, it is assumed that “M” is four (M=4). Further, “T” refers to a cycle of the reference signal “fref1” oscillated by the reference oscillator20. The phase comparator21generates M reference signals “fref1” through “fref4”, in which the reference signal “fref1” has a cycle of T, and the reference signals “fref2” through “fref4” are delayed from the reference signals “fref1” through “fref3”, respectively, by a predetermined delay time. Further, the phase comparator21generates the Exclusive OR of the M reference signals “fref1” through “fref4” and the divided signal “fd”, and outputs the Exclusive OR as the phase comparison result. As described, the loop filter22inputs the phase comparison result, and generates the voltage signal. Further, by oscillation based on the voltage signal, the VCO23generates the oscillation signal.

The phase comparator21includes variable delay circuits31-1through31-3, and exclusive OR (XOR) circuits32through35. The variable delay circuits31-1through31-3generate the (M−1) reference signals “fref2” through “fref4”, respectively, by sequentially delaying the reference signal “fref1” having the cycle of T by the predetermined delay time. Ideally, the predetermined delay time is equal to T/2M.

As illustrated inFIG. 2, the phase comparator21includes the M (e.g., 4 in this example) two-input XOR circuits connected in series. Among those XOR circuits, the first-stage XOR circuit32calculates the XOR result of (between) two signals selected from a group consisting of the M reference signals “fref1” through “fref4” and the divided signal “fd”. In this example, the XOR (result) of the reference signal “fref1” and the divided signal “fd” is calculated. Each of the XOR circuits33through35calculates the XOR result of two signals, one of which is selected from the group consisting of the M reference signals “fref1” through “fref4” and the divided signal “fd” and the other of which is the output from the previous-stage XOR circuit. In this example, the XOR circuits33through35calculate the XOR (results) of the reference signals “fref2” through “fref4” and the previous-stage XOR circuits32through34, respectively.

The result of the Exclusive OR (XOR) operation relative to M+1 (M+1-bit) inputs becomes 1 when the number of bits having a value 1 among input bits is an odd number. On the other hand, the result of the XOR operation relative to M+1 (M+1-bit) inputs becomes 0 when the number of bits having a value 1 among input bits is an even number. This XOR operation can be calculated by a single XOR circuit having M+1 inputs, and by M two-input XOR circuits connected in cascade (in series). Therefore, the phase comparator21may calculate the XOR result, for example, by using a single XOR circuit having M+1 inputs or by using M two-input XOR circuits connected in cascade (in series). In this case, note that which input signal is applied to which of the M+1 input terminals does not influence the XOR result of the phase comparator21. Accordingly, for example, the reference signals “fref1” and “fref2” may be applied to the two inputs of the XOR circuit32. In this case, the reference signals “fref3” and “fref4” and the output from the previous-stage XOR circuits32and33may be applied to the two inputs of the XOR circuits33and34, respectively. Further, the output from the previous-stage XOR circuit34and the divided signal “fd” may be applied to the two inputs of the XOR circuit35.

In the variable delay circuits31-1through31-3, the delay time may differ from the desired (predetermined) delay time due to causes of process variation, power voltage fluctuation, temperature change, etc. The delay error detector25, the AD converter26, the signal processor27, and the DA converter28collectively function as a control circuit which adjusts the delay time of the variable delay circuits31-1through31-3to be equal to T/2M based on an XOR result of at least two signals of the M reference signals. In the configuration ofFIG. 2, the delay error detector25includes a two-input XOR circuit41and a low path filter42. The two-input XOR circuit41calculates the XOR result between the signal “out4” indicating the XOR result (phase comparison result) generated by the phase comparator21and the divided signal “fd” generated by the frequency divider24. The output from the two-input XOR circuit41is smoothed by the low path filter42. The AD converter26converts the analog voltage output from the low path filter42into a digital voltage value. The signal processor27converts the digital voltage value into another digital voltage value based on a predetermined relationship. The DA converter28converts the digital voltage value, which is generated by the signal processor27, into an analog voltage, and applies the analog voltage to the variable delay circuits31-1through31-3. Based on the feedback control described above, it becomes possible to adjust the predetermined delay time (i.e., the delay time of the variable delay circuits31-1through31-3) to be equal to T/2M.

Here, calculation value of the XOR result “out4” is the XOR result of M+1 (5) signals which are the M (4) reference signals “fref1” through “fref4” and the divided signal “fd”. In the calculation of the XOR result “out4”, one divided signal “fd” is included (used). Therefore, in the calculation between the XOR result “out4” and the divided signal “fd”, two divided signals “fd” are included. The XOR result between the two divided signals “fd” always becomes zero. Thus, the XOR result between the XOR result “out4” and the divided signal “fd” is equal to the XOR result between the M reference signals “fref1” through “fref4”.

In order to calculate the XOR result between the M reference signals, it is desired to have a single XOR circuit having M+1 inputs or M two-input XOR circuits. By calculating the XOR result between the XOR result (phase comparison result) “out4” and the divided signal “fd” by using the configuration of FIG.2, it becomes possible to calculate the value which is equal to the XOR result between the M reference signals by using one two-input XOR circuit41.

FIG. 3is a timing chart illustrating an example of an Exclusive OR (XOR) operation in a case where the delay time difference between the reference signals is ideal. The output signal “out4” from the phase comparator21can be obtained by calculating the XOR result between five signals, which are one divided signal “fd” having a cycle of T/M (T/4 in this example) and four reference signals “fref1” through “fref4” having a cycle of T.FIG. 3illustrates a case where the reference signals “fref1” through “fref4” are ideally shifted one from another by the delay time T/2M (T/8 in the example). The output signal “out4”, which is the phase comparison result, indicates the phase differences between the rising and falling edges of the divided signal “fd” and the edges of the corresponding reference signals. That is, the amounts of the phase differences correspond to the pulse widths of the pulses of the output signal “out4”.

When the difference between the edge timings (i.e., the phase difference between the edges) becomes greater, the corresponding pulse width of the output signal “out4” becomes greater accordingly. On the other hand, when the difference between the edge timings (i.e., the phase difference between the edges) is reduced, the corresponding pulse width of the output signal “out4” is reduced accordingly. Therefore, by smoothing the output signal “out4” ofFIG. 2, which is the phase comparison result of the phase comparator21, by using the loop filter22and controlling the oscillation frequency of the VCO23in accordance with the output voltage of the loop filter22, it becomes possible to lock the PLL circuit. That is, when the phase difference between the reference signal “fref1” and the divided signal “fd” becomes zero, the output voltage signal of the loop filter22converges to a constant voltage, so that the PLL circuit is in a locked state.

Further, the XOR operation ofFIG. 3is equal to the XOR operation in which a first XOR result is calculated between the reference signals “fref1” through “fref4”, and then the XOR result is calculated between the first XOR result and the divided signal “fd”. By calculating the first XOR result between the reference signals “fref1” through “fref4”, a reference signal can be generated which has the same cycle (T/4) as that of the divided signal “fd”, four-times frequency of that of the reference signals, and the phases of the reference signals “fref1” through “fref4”. Then, by calculating the XOR result between the reference signal (having a cycle of T/4) having four-time frequency and the divided signal “fd” (having a cycle of T/4), the phase difference result is obtained (calculated).

In the above PLL circuit, the ratio of the cycle of the reference signals “fref1” through “fref4” to the cycle of the divided signal “fd” is 1:1/M. That is, when compared with the case where the ratio of the cycle of the reference signals to the cycle of the divided signal is 1:1, in the PLL circuit ofFIG. 2, the cycle of the divided signal “fd” is relatively short (the frequency is relatively high). In other words, when compared with a usual PLL circuit, the frequency division ratio of the frequency divider24inFIG. 2is smaller.

The output signal of the phase comparator includes the phase noise which is generated by the phase comparator. In this case, as illustrated in Formula (1), the phase noise, which presents in the output oscillation signal of the PLL circuit caused by the phase noise, is proportional to the square of the frequency division ratio “N”. In this regard, by reducing the frequency division ratio “N”, it becomes possible to reduce the phase noise which presents in the output oscillation signal of the PLL circuit. In the following, more details are described. In the PLL circuit ofFIG. 2, by arranging M (4 in this example) phase comparators (XOR circuits), it becomes possible to reduce the frequency division ratio of the frequency divider24(by 1/M times). Here, it is assumed that the frequency division ratio, which is reduced as described above, is “N0/M”. Generally, a feedback gain by the frequency divider having the frequency division ratio “N0/M” is “M/N0”, which is M times greater than the gain “1/N0” which is before the frequency division ratio is reduced. When the feedback gain is increased by M times, the feedback amount is amplified by M times. Thus, the amount of contribution of the noise after the feedback is given is reduced by 1/M times. That is, the contribution of the phase comparator noise to the PLL phase noise is reduced by 1/M times.

Further, the phase noise generated by the phase comparator is mainly caused by the thermal noise, the shot noise, and the flicker noise of the transistor of the output final stage. Accordingly, the phase noise generated by the phase comparator having plural XOR circuits connected in series does not substantially differ from the phase noise generated by the phase comparator having one (stage of) XOR circuit. Therefore, the effect of reducing the phase noise by the circuit configuration ofFIG. 2is remarkably large.

Further, in the circuit configuration ofFIG. 2, in order to obtain (calculate) the phase comparison result by the phase comparator21, it is only desired to calculate XOR results by the XOR circuits. Therefore, according to an embodiment, it becomes possible to provide a PLL circuit having a low phase noise with a relatively simple configuration without necessity to mount plural phase comparators in a related art technology.

FIG. 4is a timing chart illustrating an example of an Exclusive OR (XOR) operation in a case where the delay time difference between the reference signals is shifted from the ideal value. The output signal “out4” of the phase comparator21is obtained by calculating the XOR result between five signals, which are the divided signal “fd” having a cycle of T/M (T/4 in this example) and the reference signals “fref1” through “fref4” having a cycle of T.

In the variable delay circuits31-1through31-3, the delay time may differ from the desired delay time due to causes of process variation, power voltage fluctuation, temperature change, etc. InFIG. 4, the time difference between the reference signals “fref1” and the reference signal “fref4”, that is, the time difference between the reference signal “fref1” and the reference signal “fref2”, time difference between the reference signal “fref2” and the reference signal “fref3”, and time difference between the reference signal “fref3” and the reference signal “fref4”, is longer than T/2M (T/8 in this example). In this case, even when the phase difference between the divided signal “fd” and the reference signal “fref2” is the same as that inFIG. 3, the average of the pulse widths of the output signal “out4”, which is the phase comparison result, becomes greater than the average of the pulse width of the output signal “out4” inFIG. 3. Further, the operation is repeated in which the pulse width is gradually increased.

As described, in the case where the delay time difference between the reference signals differs from the ideal value, the pulse widths in the output signal “out4”, which indicates the phase comparison result, differ from the pulse width which is desired. As a result, the characteristics of the PLL circuit may be degraded. More specifically, a low-frequency spurious component may be present, which degrades the spurious characteristics of the PLL circuit.

In light of the above point, the PLL circuit ofFIG. 2includes a control circuit (i.e., the delay error detector25, the AD converter26, the signal processor27, and the DA converter28) to adjust the delay time (delay time difference) by feedback control. By the feedback control by the control circuit, it becomes possible to adjust the delay time to be equal to T/2M based on the XOR result of at least two reference signals among the M reference signals.

FIG. 5is a timing chart illustrating an example of an Exclusive OR (XOR) operation in a case where the delay time difference between the reference signals is longer than the ideal value. The output signal “out4” of the phase comparator21is obtained by calculating the XOR result between five signals, which are the divided signal “fd” having a cycle of T/M (T/4 in this example) and the reference signals “fref1” through “fref4” having a cycle of T. The two-input XOR circuit41ofFIG. 2generates the “XOR output” waveform, which is illustrated in the bottom ofFIG. 5, by calculating the XOR result between the output signal “out4” and the divided signal “fd”. As described above, when two divided signals “fd” are cancelled by each other, the “XOR output” becomes equal to the XOR result of the four reference signals “fref1” through “fref4”.

In a case where the delay time difference between the reference signals is the ideal value “T/2M (“T/8” in this example)”, the XOR result of the reference signals “fref1” through “fref4” is obtained as a pulse signal having a cycle of T/4 and a duty ratio of 50%. When the delay time difference between the reference signals “fref1” through “fref4” is gradually longer than the ideal value “T/2M (“T/8” in this example)”, the pulse width of the XOR result is gradually increased.FIG. 5illustrates the case where the pulse width of the “XOR output” is increased as such. Further, when the delay time difference between the reference signals “fref1” through “fref4” exceeds a certain value, the pulse width of the “XOR output” starts decreasing.

FIG. 6is a timing chart illustrating an example of an Exclusive OR (XOR) operation in a case where the delay time difference between the reference signals is shorter than the ideal value. The “XOR output” waveform, which is illustrated in the bottom ofFIG. 6, refers to the XOR result between the output signal “out4” from the phase comparator21and the divided signal “fd”. The “XOR output” becomes equal to the XOR result of the four reference signals “fref1” through “fref4”.

In a case where the delay time difference between the reference signals is the ideal value “T/2M (“T/8” in this example)”, the XOR result of the reference signals “fref1” through “fref4” is obtained as a pulse signal having a cycle of T/4 and a duty ratio of 50%. When the delay time difference between the reference signals “fref1” through “fref4” is gradually shorter than the ideal value “T/2M (“T/8” in this example)”, the pulse width of the XOR result is gradually decreased.FIG. 6illustrates the case where the pulse width of the “XOR output” is decreased as such. Further, when the delay time difference between the reference signals “fref1” through “fref4” becomes zero, the pulse width of the “XOR output” also becomes zero.

FIG. 7is a graph illustrating the delay time of the variable delay circuits and the output voltage of a delay detection circuit (the delay error detector25). InFIG. 7, the horizontal axis indicates the delay time “var_delay” of the variable delay circuits and the vertical axis indicates the output voltage “Int_XOUT” of the delay error detector25. Here, the ideal value of the delay time “var_delay” is set to 1.0, and the actual delay time is indicated as the ratio of the actual delay time to the ideal delay time. The output voltage “Int_XOUT” refers to the output voltage of the low path filter42when it is assumed that the voltage levels of “HIGH” and “LOW” outputs of the two-input XOR circuit41are 1.0 and 0, respectively.

InFIG. 7, a characteristic straight line51indicates the output characteristics of the delay error detector25. When the value of the delay time “var_delay” is 1.0, the value of the output voltage “Int_XOUT” indicated by the characteristic straight line51is 0.5. That is, in a case where the value of the delay time is ideal, as described above, the output of the two-input XOR circuit41is a pulse signal having the duty ratio of 50%. Accordingly, the output of the low path filter42acquired by smoothing the pulse signal is an intermediate (average) voltage which is between the HIGH voltage and LOW voltage. Further, for example, in a case where the value of the delay time “var_delay” is 1.2 which is longer than the ideal value, the output voltage value indicated by the characteristic straight line51is approximately 0.57. On the other hand, for example, in a case where the value of the delay time “var_delay” is 0.8 which is shorter than the ideal value, the output voltage value indicated by the characteristic straight line51is approximately 0.43.

In accordance with the output voltage of the delay error detector25acquired as described above, by adjusting the delay value of the variable delay circuits31-1through31-3by the AD converter26, the signal processor27, and the DA converter28, it becomes possible to bring the delay time close to the ideal value of T/2M. Specifically, when the output voltage of the delay error detector25is higher than 0.5, the delay amount of the variable delay circuits31-1through31-3is reduced (shortened). On the other hand, when the output voltage of the delay error detector25is lower than 0.5, the delay amount of the variable delay circuits31-1through31-3is increased (elongated).

FIG. 8illustrates an example configuration of the variable delay circuit. The variable delay circuit ofFIG. 8may be used in the phase comparator21ofFIG. 2. The variable delay circuit ofFIG. 8includes inverters52and53, resistor elements54and55, and capacitor elements56and57. The inverter52generates an output signal which is logically inverted from the input signal and presents the output signal from the output terminal thereof. Depending on the voltage of the output signal, a current flows through the resistor element54and the capacitor element56, so that the capacitor element56is charged or discharged. Based on the charged or discharged operation of the capacitor element56, the input signal voltage of the of the inverter53varies, so that, when the input signal voltage of the of the inverter53exceeds a threshold voltage of the inverter53, the output signal voltage of the inverter53changes. Based on the change of the output signal voltage of the inverter53, similarly, the capacitor element57is charged or discharged. The rate (speed) of changing the voltage between the terminals of the capacitor element is determined based on the resistance value “R” of the resistor element and the capacitance value “C” of the capacitor element. Based on the rate (speed) of changing the voltage between the terminals of the capacitor element, the delay, time which is necessary to transmit the signal from the input terminal to the output terminal of the variable delay circuit, is determined.

In the configuration of the variable delay circuit ofFIG. 8, a variable capacitance element (varactor) is used as the capacitor elements56and57. By changing the varactor control voltage which is applied to the control terminals of the capacitor elements56and57, the capacitance values of the capacitor elements56and57can be changed. By doing this, a desired delay time can be obtained.

FIG. 9is a flowchart of an example procedure of the operation control of the PLL circuit ofFIG. 2. Note that the execution order of steps described in the flowchart is an example only, and a technical scope of the present application is not limited thereto. For example, even when the description of the present invention recites that step “B” is executed after step “A”, it is not only that step “B” can be executed after step “A”, but also that step “A” may be physically or theoretically executed after step “B”. In this case, if all the results which influence the processes of the flowchart are the same regardless of the execution order of steps “A” and “B”, it is obvious that step “A” may be executed after step “B” in view of disclosing the technique of the present application. That is, even in a case where the description of the present application explains that step “B” is executed after step “A”, which is not intended to exclude the obvious case as described above from the scope of the present application, so that when it is obvious as described above, it is to be understood that the case is also included in the technical scope of the present application.

In step S1, a correction mode starts. That is, in the PLL circuit ofFIG. 2, the operation of the correction mode starts which adjusts the delay time of the variable delay circuits31-1through31-3. Specifically, the oscillation signal of the PLL circuit is set to a mode in which the oscillation signal is not used in any other circuits, and the operations of the delay error detector25, the AD converter26, the signal processor27, and the DA converter28are started.

In step S2, the AD converter26performs AD conversion on the output voltage of the delay error detector25, and the acquired digital voltage is referred to “Vt”. In step S3, the signal processor27calculates a voltage difference “dv” which is between the center voltage “Vcm” (the intermediate (average) voltage between HIGH voltage and LOW voltage) and the voltage “Vt”. When it is determined that the voltage difference “dv” is less than or equal to (within) a predetermined reference value (YES in step4), the process goes to step S7so that the correction mode ends. As a result of ending the correction mode, the usual oscillation and the phase follow-up operation in the PLL circuit may be started, so that a mode is set in which the oscillation signal of the PLL circuit can be used in any other circuit. Further, the operations of the delay error detector25, the AD converter26, the signal processor27, and the DA converter28may be stopped.

When it is determined that the voltage difference “dv” exceeds the predetermined reference value (NO in step4), the process goes to step S5. In step S5, the signal processor27reads the digital voltage value, which corresponds to the voltage difference “dv”, from a characteristic table of the variable delay circuits. Based on the digital voltage value, the voltage value to be applied to the variable delay circuits31-1through31-3is calculated. In step S6, the DA converter28converts the digital voltage value, which is calculated by the signal processor27, into an analog voltage, so that the analog voltage is applied to the variable delay circuits31-1through31-3.

FIG. 10illustrates another example of the configuration of the PLL circuit according to an embodiment. InFIG. 10, the same reference numerals are used to describe the same or corresponding elements described inFIG. 2, and the repeated descriptions thereof are herein omitted.

In the PLL circuit ofFIG. 10, a delay error detector25A is provided in place of the delay error detector25of the PLL circuit inFIG. 2. The delay error detector25A includes a four-input XOR circuit41A and the low path filter42. The delay error detector25A, the AD converter26, the signal processor27, and the DA converter28function as a control circuit to adjust the delay time of the variable delay circuits31-1through31-3to be equal to T/2M based on the XOR result between at least two reference signals among M reference signals. In the example ofFIG. 10, the four-input XOR circuit41A calculates the XOR result between the M (4 in this example) reference signals.

The logical operation, which is performed by the four-input XOR circuit41A of the delay error detector25A inFIG. 10, is equivalent to the logical operation performed by the two-input XOR circuit41of the delay error detector25inFIG. 2. Therefore, the PLL circuit ofFIG. 10operates similar to the PLL circuit ofFIG. 2.

FIG. 11illustrates still another example of the configuration of the PLL circuit according to an embodiment. InFIG. 11, the same reference numerals are used to describe the same or corresponding elements described inFIG. 2, and the repeated descriptions thereof are herein omitted.

In the PLL circuit ofFIG. 11, a delay error detector25B is provided in place of the delay error detector25of the PLL circuit inFIG. 2. The delay error detector25B includes a two-input XOR circuit41B and the low path filter42. The delay error detector25B, the AD converter26, the signal processor27, and the DA converter28function as a control circuit to adjust the delay time of the variable delay circuits31-1through31-3to be equal to T/2M based on the XOR result between at least two reference signals among M reference signals. In the example ofFIG. 11, the two-input XOR circuit41B calculates the XOR result between the two reference signals.

Especially, the two-input XOR circuit41B calculates the XOR result between two reference signals which are ideally shifted from each other by T/M (T/4 in this example). The XOR result between two reference signals which are ideally shifted from each other by T/4 is indicated as a pulse signal having a cycle of T/2 and a duty ratio of 50%. When the time difference between the two reference signals becomes longer than the ideal value, the pulse width of the pulse signal of the XOR result becomes longer. On the other hand, when the time difference between the two reference signals becomes shorter than the ideal value, the pulse width of the pulse signal of the XOR result becomes shorter. Therefore, similar to the case of the delay error detector25ofFIG. 2, by performing the feedback control on the delay time of the variable delay circuits31-1through31-3based on the output voltage of the delay error detector25B, it becomes possible to set an appropriate delay time to the variable delay circuits31-1through31-3.

When compared with the calculation of the XOR result of four reference signals, in a case where the XOR result is calculated between two reference signals, a range of the delay time where the pulse width is monotonically increased is extended with the increase of the delay time. Therefore, in the PLL circuit ofFIG. 11, it becomes possible to properly converge the delay time of the variable delay circuits31-1through31-3to a desired value relative to the delay time in a wider range.

FIG. 12illustrates still another example of the configuration of the PLL circuit according to an embodiment. InFIG. 12, the same reference numerals are used to describe the same or corresponding elements described inFIG. 2, and the repeated descriptions thereof are herein omitted.

In the PLL circuit ofFIG. 12, a voltage converter60and a switcher61are provided in place of the AD converter26, the signal processor27, and the DA converter28. In the PLL circuits described above, the output analog voltage of the delay error detector is converted into the digital value, and the digital conversion is performed from the output voltage of the delay error detector into the voltage to be applied to the variable delay circuits in a digital region. In the PLL circuit ofFIG. 12, on the other hand, the voltage converter60converts the output voltage of the delay error detector into the voltage to be applied to the variable delay circuits in an analog region directly. The switcher61is provided to control whether the output of the voltage converter60is applied to the variable delay circuits31-1through31-3.

FIG. 13is an example configuration of a transceiver100according to an embodiment. InFIG. 13, the same reference numerals are used to describe the same or corresponding elements described inFIG. 2, and the repeated descriptions thereof are herein omitted.

The transceiver100ofFIG. 13includes a PLL circuit101, an AD signal processor102, a mixer103, and amplifiers104and105. The frequency division ratio of the frequency divider24in the PLL circuit101is variable, and is set in accordance with the value of the input data “DIN”. By having this configuration, the PLL circuit101generates an oscillation signal having a frequency corresponding to the value of the input data “DIN”. The oscillation signal generated by the PLL circuit101is amplified by the amplifier104and transmitted from the transmission antenna110as radio waves.

The received signal based on the radio waves received by the receiving antenna111is amplified by the amplifier105, and is input in the mixer103. The mixer103mixes the oscillation signal generated by the PLL circuit101with the received signal to generate a beat signal. The generated beat signal is converted into digital values and appropriate signal processing is performed on the digital values by the AD signal processor102, so that the processed signal is supplied externally as the data “DOUT”.

In this example, the PLL circuit having the configuration ofFIG. 2is used as the PLL circuit101. In place of the PLL circuit ofFIG. 2, a PLL circuit having a configuration ofFIG. 10, 11, or12may be used.

FIG. 14illustrates an example configuration of an in-vehicle radar system200according to an embodiment. The in-vehicle radar system200ofFIG. 14includes a power supply201, a communicator202, a signal processor203, a transceiver100, a transmission antenna110, and a receiving antenna111. The power supply201supplies power voltages to the communicator202, the signal processor203, and the transceiver100. The communicator202is a circuit to communicate with a vehicle control system. The signal processor203performs, for example, calculations to obtain a distance to and a speed relative to an object, and controls the operations of the transceiver100and the communicator202.

As the transceiver100ofFIG. 14, the transceiver100ofFIG. 13may be used. For example, in a Frequency Modulation Continuous Wave (FMCW) radar apparatus, it is possible to obtain a distance to and a speed relative to an object by transmitting triangular-wave frequency-modulated millimeter radio waves and calculating based on the frequency difference between the transmission signal and a receiving signal, etc. In this case, the transmission signal from the transceiver100is transmitted from the transmission antenna110as the millimeter radio waves, and the millimeter radio waves reflected by the object are received by the receiving antenna111, so that the received signal is supplied to the transceiver100. The beat signal extracted from the received signal by the transceiver100is supplied to the signal processor203, so that the frequency component of the beat signal is detected by performing signal processing by the signal processor203, and the distance to and the speed relative to the object are obtained. Note that the operations of the steps in the flowchart ofFIG. 9may be executed under the control of the signal processor203.