A SAR ADC and a method thereof are provided. Particularly, in each bit determining duration of last several bit determining durations, a comparer is used to consecutively compare a first potential with a second potential on a sampling and digital-to-analog converting circuit a plurality of times to obtain a plurality of comparison results, and then an SAR control circuit generates a corresponding output bit according to the obtained plurality of comparison results.

CROSS-REFERENCES TO RELATED APPLICATIONS

This non-provisional application claims priority under 35 U.S.C. §119(a) on Patent Application No. 102115940 filed in Taiwan, R.O.C. on 2013 May 3, the entire contents of which are hereby incorporated by reference.

BACKGROUND

1. Technical Field

The present invention relates to an analog-to-digital conversion technology, and more particularly to a successive-approximation-register (SAR) analog-to-digital converter (ADC) and a method thereof.

2. Related Art

An ADC is of various architectures, such as: a flash ADC, a pipelined ADC, and an SAR ADC. These architectures have respective advantages, and are generally selected according to different application demands. Compared with other architectures, the SAR ADC is lower in power consumption, smaller in area and lower in cost.

Conventionally, an SAR ADC obtains a digital output code matching an input signal by adopting a binary search algorithm. In a converting procedure, according to a comparison result of a comparer each time, in a digital-to-analog converting circuit in the SAR ADC, a binary scaled voltage generally needs to be added or subtracted, and after a last bit cycle ends, the difference between an input signal and a reference voltage is less than a least significant bit (LSB). However, when the input signal is small, the input signal is easily subjected to interference of a noise (this interference includes interference of the comparer, interference of a chip system itself, and interference of a power source), and thus there is occurrence of misjudgment in the converting procedure.

SUMMARY

In an embodiment, an SAR analog-to-digital converting method includes: generating a first potential by sampling an analog signal; generating a plurality of output bits sequentially according to the first potential and a plurality of second potentials occurring consecutively on the digital-to-analog converting circuit by using a comparer; and outputting a digital signal based on these output bits. Here, these second potentials correspond to these output bits respectively. A step of generating a last output bit includes: comparing the first potential with a second potential occurring at the last time a plurality of times consecutively by using the comparer, so as to obtain a plurality of first comparison results; and generating the last output bit according to these first comparison results.

In another embodiment, an SAR analog-to-digital converting method includes: generating a first potential by sampling an analog signal; generating a plurality of output bits sequentially according to the first potential and a plurality of second potentials occurring consecutively on the digital-to-analog converting circuit by using a comparer; and outputting a digital signal based on these output bits. A step of generating last j output bits of these output bits includes: comparing the first potential with a second potential occurring at the last time a plurality of times consecutively by using the comparer, so as to obtain a plurality of first comparison results respectively; and generating last j output bits according to these first comparison results. Here, j is an integer greater than 1.

In still another embodiment, an SAR ADC includes: a sampling and digital-to-analog converting circuit, a comparer and an SAR control circuit. The SAR control circuit includes: a first determining module, at least one second determining module and an output logic. The first determining module is corresponding to a last bit determining duration of a plurality of bit determining durations, and each second determining module is corresponding to one of the rest bit determining durations.

The sampling and digital-to-analog converting circuit generates a first potential by sampling an analog signal. In the last bit determining duration, the comparer compares the first potential with a second potential on the sampling and digital-to-analog converting circuit a plurality of times consecutively to obtain a plurality of first comparison results respectively, and the first determining module generates a group of last output bits according to these first comparison results. In each bit determining duration of the rest bit determining durations, the comparer compares the first potential with the second potential once to obtain a corresponding second comparison result, and the corresponding second determining module generates an output bit according to the corresponding second comparison result, and controls the sampling and digital-to-analog converting circuit according to the corresponding second comparison result, so as to adjust the second potential on the sampling and digital-to-analog converting circuit. The output logic outputs a digital signal according to at least one output bit and the group of last output bits.

To summarize, according to the SAR ADC and the method thereof of the present invention, the number of comparison times of the comparer is increased in the last several bit determining durations, so under the situation that no complex signal detecting apparatus is added, the influence of a noise (such as: noise interference generated by the comparer, a chip system itself, or a power source), on the signal-to-noise ratio (SNR) of the SAR ADC is effectively reduced. Additionally, for results of a plurality of comparison times, the energy of the noise may be further reduced in a manner of majority decision, averaging and round-off or specific encoding.

DETAILED DESCRIPTION

FIG. 1is a schematic diagram of an SAR ADC according to an embodiment of the present invention.FIG. 2andFIG. 3are a schematic flow chart of an SAR analog-to-digital converting method according to an embodiment of the present invention.

Please refer toFIG. 1, in which an SAR ADC10includes a sampling and digital-to-analog converting circuit110, a comparer130and an SAR control circuit150.

The sampling and digital-to-analog converting circuit110is coupled to two input ends of the comparer130, an output end of the comparer130is coupled to the SAR control circuit150, and the SAR control circuit150is coupled to a control end of the sampling and digital-to-analog converting circuit110.

Please refer toFIG. 2, in which the operating of the SAR ADC10starts from a sampling phase. During the sampling phase, the SAR control circuit150controls the sampling and digital-to-analog converting circuit110through a digital control signal Sc, so that the sampling and digital-to-analog converting circuit110samples and stores a sampling analog signal Vin (step S21). In other words, the sampling and digital-to-analog converting circuit110generates a first potential V1by sampling the analog signal Vin.

Next, the SAR ADC10enters a bit-cycling phase, namely, a converting phase, so as to determine a converting output of a digital output. The bit-cycling phase includes N bit determining durations connected sequentially. N is an integer greater than 1. In each bit determining duration, the sampling and digital-to-analog converting circuit110converts a bit and generates a second potential V2. Here, the sampling and digital-to-analog converting circuit110only converts a bit in a same bit determining duration, and begins to convert a most significant bit (MSB) into an LSB.

In some embodiments, the SAR control circuit150includes N determining modules153-1to153-N and an output logic157.

The determining modules153-1to153-(N−1) are individually coupled between the output end of the comparer130and the control end of the sampling and digital-to-analog converting circuit110. Furthermore, output ends of the determining modules153-1to153-(N−1) are connected to the output logic157. Each of the determining modules153-1to153-(N−1) is coupled to a next determining module.

The N determining modules153-1to153-N are respectively corresponding to the N bit determining durations, and in each bit determining duration, the corresponding determining module determines an output bit according to outputs OUT_p and OUT_n of the comparer130.

For convenience of description, the determining module153-N is referred to as a first determining module153-N, and the rest determining modules153-1to153-(N−1) are referred to as second determining modules153-1to153-(N−1) below.

In the first bit determining duration, the SAR control circuit150outputs the digital control signal Sc to the sampling and digital-to-analog converting circuit110. In some embodiments, the SAR control circuit150generates the digital control signal Sc according to the outputs (namely, output bits B1to B(N−1)) of the second determining modules153-1to153-(N−1).

The sampling and digital-to-analog converting circuit110then generates the second potential V2according to the received digital control signal Sc (step S23). Here, the highest (the first) bit of the digital control signal Sc is “1”, and the rest bits are “0”.

Next, the comparer130compares the first potential V1on the sampling and digital-to-analog converting circuit110with the second potential V2on the sampling and digital-to-analog converting circuit110once to obtain a first comparison result OUT_p and OUT_n (step S25). Here, the comparison result OUT_p and OUT_n is a differential signal.

The second determining module153-1generates an output bit B1according to this comparison result OUT_p and OUT_n (step S27). For example, it is assumed that the first potential V1is the input signal Vin, and the second potential V2is an analog output (VDAC) obtained after the digital control signal Sc is converted. At this time, when the comparison result OUT_p and OUT_n of the comparer130is that the analog output VDACis less than the input signal Vin, the second determining module153-1sets the value of the output bit B1to “1”, namely, the first bit of the output signal B[1:N] is 1. On the contrary, when the comparison result OUT_p and OUT_n of the comparer130is that the analog output VDACis greater than or equal to the input signal Vin, the second determining module153-1sets the output bit B1to “0”, namely, the first bit of the output signal B[1:N] is 0.

Furthermore, the SAR control circuit150controls the sampling and digital-to-analog converting circuit110according to this comparison result OUT_p and OUT_n (step S29), so as to adjust the second potential V2on the sampling and digital-to-analog converting circuit110. In other words, the SAR control circuit150performs adjustment according to the output bit B1generated by the second determining module153-1and outputs a new digital control signal Sc to the sampling and digital-to-analog converting circuit110, so that the sampling and digital-to-analog converting circuit110generates the second potential V2according to the new digital control signal Sc (step S23). Taking that the first comparison result OUT_p and OUT_n is that the analog output VDACis less than the input signal Vin as an example, at this time, the highest (the first), bit of the digital control signal Sc is maintained to be “1”, the second highest (the second), bit is set from “0” to “1”, and the remaining bits are also maintained to be “0”. The sampling and digital-to-analog converting circuit110generates the second potential V2according to the new digital control signal Sc. Similarly, if that the first comparison result OUT_p and OUT_n is that the analog output VDACis not less than the input signal Vin is taken as an example, the highest (the first), bit of the digital control signal Sc is set to “0”, the second highest (the second), bit is set from “0” to “1”, and the rest bits are also maintained to be “0”.

The comparer130again compares the first potential V1on the sampling and digital-to-analog converting circuit110with the second potential V2on the sampling and digital-to-analog converting circuit110once to obtain a second comparison result OUT_p and OUT_n (step S25).

The second determining module153-1Next generates (sets), a corresponding output bit B2according to this comparison result OUT_p and OUT_n, namely, the second bit of the output signal B[1:N] (step S27).

Furthermore, the SAR control circuit150again controls the sampling and digital-to-analog converting circuit110according to this comparison result OUT_p and OUT_n (step S29), so as to again adjust the second potential V2on the sampling and digital-to-analog converting circuit110.

That is to say, (step S23), (step S25), (step S27), and (step S29), are executed repetitively and sequentially, until the last but one bit determining duration is completed. At this time, the second determining modules153-1to153-(N−1) have respectively generated (set) the output bits B1to B(N−1), namely, the first bit to the (N−1)th bit of the output signal B[1:N].

In the Nth bit determining duration (namely, the last bit determining duration), the comparer130repetitively compares the first potential V1with the second potential V2to obtain a plurality of comparison results OUT_p and OUT_n, namely, consecutively compares the first potential V1with the second potential V2a plurality of times. For convenience of description, the comparison result OUT_p and OUT_n generated in the Nth bit determining duration are referred to as a first comparison result OUT_p and OUT_n, and the comparison result OUT_p and OUT_n generated in the rest bit determining durations is referred to as a second comparison result OUT_p and OUT_n. In other words, in the last bit determining duration, the comparer130consecutively performs comparison m times and obtains m first comparison results OUT_p and OUT_n. Here, m is an integer greater than 1. in the last bit determining duration, after the comparer130completes the comparison, the SAR control circuit150does not control the sampling and digital-to-analog converting circuit110according to the comparison result OUT_p and OUT_n obtained each time to adjust the second potential V2on the sampling and digital-to-analog converting circuit110. That is to say, in the last bit determining duration, the SAR control circuit150does not change the output digital control signal Sc, so that the second potential V2used when comparison is performed a plurality of times is maintained invariable.

In other words, in a same bit-cycling phase, the first determining module consecutively processes a plurality of comparison results, while the second determining module only processes one comparison result.

In some embodiments, the first determining module153-N includes m generating units154and a judging unit155. The m generating units154are individually coupled between the output end of the comparer130and the input end of the judging unit155.

The m generating units are respectively corresponding to m first comparison results OUT_p and OUT_n, and generate a corresponding digit code according to a corresponding first comparison result OUT_p and OUT_n.

FIG. 4is a schematic diagram of an embodiment of a first determining module153-N inFIG. 1.

Taking that comparison performed consecutively thrice (namely, m=3) as an example, please refer toFIG. 3andFIG. 4collaboratively, the first determining module153-N includes three generating units154-1,154-2, and154-3and a judging unit155. The generating units154-1,154-2, and154-3are individually coupled between the output end of the comparer130and the input end of the judging unit155. The output end of the judging unit155is connected to the control end of the sampling and digital-to-analog converting circuit110and the output logic157.

In the Nth bit determining duration, the sampling and digital-to-analog converting circuit110generates the second potential V2according to the new digital control signal Sc (step S43). Next, the comparer130performs first comparison (the Nth comparison of the entire bit-cycling phase), namely, compares the first potential V1with the second potential V2to obtain a first comparison result OUT_p and OUT_n (step S45). The generating unit154-1generates a digit code B3_a according to this first comparison result OUT_p and OUT_n (step S47).

Next, the comparer130performs second comparison (the (N+1)th comparison of the entire bit-cycling phase), namely, compares the first potential V1with the second potential V2to obtain a second first comparison result OUT_p and OUT_n (step S45). The generating unit154-2then generates a digit code B3_b according to this first comparison result OUT_p and OUT_n (step S47).

Next, the comparer130performs third comparison (the (N+2)th comparison of the entire bit-cycling phase), namely, compares the first potential V1with the second potential V2to obtain a third first comparison result OUT_p and OUT_n (step S45). The generating unit154-3then generates a digit code B3_c according to this first comparison result OUT_p and OUT_n (step S47).

After the set number of comparison times is completed, the judging unit155generates (sets) the last output bit BN according to the digit codes B3_a, B3_b, and B3_c corresponding to these three first comparison results OUT_p and OUT_n (step S48).

Next, the output logic157uses all the set output bits B1to BN as a digital signal B[1:N], and outputs this digital signal B[1:N] to a next-stage circuit (step S51).

FIG. 5is a partial flow chart of an SAR analog-to-digital converting method according to another embodiment of the present invention.FIG. 6is a schematic diagram of an SAR ADC according to another embodiment of the present invention.

In some embodiments, please refer toFIG. 5andFIG. 6, in which the first determining module153-N may generate a plurality of output bits BN to B(N+j−1) according to digit codes of m first comparison results OUT_p and OUT_n (step S48′). j is an integer greater than 1.

At this time, the output logic157uses all the output bits B1to B(N+j−1) as a digital signal B[1:N+j−1], and outputs this digital signal B[1:N+j−1] to a next stage (step S51).

FIG. 7is a schematic diagram of an embodiment of a first determining module153-N inFIG. 6.

Taking that comparison performed consecutively twice and in which two output bits are generated as an example, please refer toFIG. 7collaboratively, in which the first determining module153-N includes two generating units154-1and154-2, and a judging unit155. The generating units154-1and154-2are individually coupled between the output end of the comparer130and the input end of the judging unit155. The output end of the judging unit155is connected to the control end of the sampling and digital-to-analog converting circuit110and the output logic157.

In the Nth bit determining duration, the comparer130consecutively performs comparison twice (the Nth comparison and the (N+1)th comparison of the entire bit-cycling phase), and sequentially obtains two first comparison results OUT_p and OUT_n. The generating unit154-1generates a digit code B3_a according to the first comparison result OUT_p and OUT_n, and the generating unit154-2generates a digit code B3_b according to the second first comparison result OUT_p and OUT_n (step S47). Next, the judging unit155may obtain the last two output bits BN and B(N+1) according to the digit codes BN_a and BN_b by using a conversion table (Table 1 shown below) (step S48′).

In some embodiments, in each of the last several bit determining durations, the comparer130consecutively performs comparison a plurality of times, thereby further enhancing the SNR of the SAR ADC10.

In other words, each of the determining modules153-(N−k−1) to153-N corresponding to the last but k+1 bit determining duration to the Nth bit determining duration includes a plurality of generating units154and a judging unit155. For convenience of description, the determining module153-N is referred to as a first determining module153-N, the determining modules153-(N−k−1) to153-(N−1) are referred to as third determining modules153-(N−k−1) to153-(N−1), and the rest determining modules153-1to153-(N−k−2) are referred to as second determining modules153-1to153-(N−k−2) below. Furthermore, the comparison result OUT_p and OUT_n generated in the Nth bit determining duration is referred to as a first comparison result OUT_p and OUT_n, the comparison result OUT_p and OUT_n generated in the last but k+1 bit determining duration to the (N−1)th bit determining duration is referred to as a third comparison result OUT_p and OUT_n, and the comparison result OUT_p and OUT_n generated in the rest bit determining durations is referred to as a second comparison result OUT_p and OUT_n below.

FIG. 8andFIG. 9are a partial flow chart of an SAR analog-to-digital converting method according to still another embodiment of the present invention. In the drawings, k is an integer, and k+2 is less than the total sum of output bits.FIG. 10is a locally schematic diagram of another embodiment of an SAR control circuit150inFIG. 1.

Please refer toFIG. 8,FIG. 9andFIG. 10, in which it is assumed that the SAR ADC10is designed into that in the last two bit determining durations (namely, k=0 in the drawings), the comparer130individually performs comparison thrice (namely, m=0 in the drawings).

In the last but one bit determining duration (namely, the (N−1)th bit determining duration), the sampling and digital-to-analog converting circuit110generates the second potential V2according to the new digital control signal Sc (step S33). Next, the comparer130performs first comparison in the (N−1)th bit determining duration, namely, compares the first potential V1with the second potential V2to obtain a third comparison result OUT_p and OUT_n (step S35). The generating unit154-1in the third determining module153-(N−1) generates a digit code B(N−1)_a according to this third comparison result OUT_p and OUT_n (step S37).

Next, the comparer130again performs second comparison in the (N−1)th bit determining duration, namely, compares the first potential V1with the second potential V2to again obtain a third comparison result OUT_p and OUT_n (step S35). The generating unit154-1in the third determining module153-(N−1) generates a digit code B(N−2)_b according to this third comparison result OUT_p and OUT_n (step S37).

Next, the comparer130again performs third comparison in the (N−1)th bit determining duration, namely, compares the first potential V1with the second potential V2to again obtain a third comparison result OUT_p and OUT_n (step S35). The generating unit154-1in the third determining module153-(N−1) generates a digit code B(N−3)_c according to this third comparison result OUT_p and OUT_n (step S37).

Before the number of comparison times set in this bit determining duration is completed, the SAR control circuit150does not change the output digital control signal Sc, so that the second potential V2used when comparison is performed a plurality of times is maintained invariable.

After the set number of comparison times is completed, the judging unit155in the third determining module153-(N−1) generates (sets) the (N−1)th output bit B(N−1) according to the digit codes B(N−1)_a, B(N−1)_b, and B(N−1)_c corresponding to the third comparison results OUT_p and OUT_n generated after comparison is performed thrice (step S38).

The SAR control circuit150again controls the sampling and digital-to-analog converting circuit110according to these third comparison results OUT_p and OUT_n (step S39), so as to again adjust the second potential V2on the sampling and digital-to-analog converting circuit110(step43). In other words, the SAR control circuit150performs adjustment based on the (N−1)th output bit B(N−1) set by the judging unit155in the third determining module153-(N−1) and outputs the digital control signal Sc to the sampling and digital-to-analog converting circuit110.

In the Nth bit determining duration, please refer toFIG. 3orFIG. 5collaboratively, in which after the sampling and digital-to-analog converting circuit110adjusts the second potential V2according to the new digital control signal Sc (step43), the comparer130consecutively compares the first potential V1with the second potential V2thrice, so as to obtain three first comparison results OUT_p and OUT_n (step45). Furthermore, the generating units154-1,154-2, and154-3in the first determining module153-N generate digit codes BN_a, BN_b, and BN_c according to these first comparison results OUT_p and OUT_n respectively (step47). Next, the judging unit155in the third determining module153-N generates (sets) the Nth output bit BN (step S48) or generates the Nth and (N+1)th output bits BN and B(N+1) (step S48′) according to the digit codes BN_a, BN_b, and BN_c corresponding to the first comparison results OUT_p and OUT_n generated after comparison is performed thrice.

In other words, in a same bit-cycling phase, both the first determining module and the third determining module process a plurality of comparison results, while the second determining module only processes one comparison result. Additionally, a plurality of generating units in a same determining module is respectively corresponding to a plurality of comparison results generated by a same bit determining duration. Furthermore, except for the last bit determining duration, for a bit determining duration in which comparison is performed a plurality of times, before the number of comparison times set in this bit determining duration is completed, the SAR control circuit150does not change the output digital control signal Sc, so that the second potential V2used when comparison is performed a plurality of times is maintained invariable.

In some embodiments, when the comparer130consecutively performs comparison a plurality of times in each of the last several bit determining durations, the comparer130may execute comparison same times or different times in all the bit determining durations, or same times in part of the bit determining durations and different times in part of the bit determining durations. For example, it is assumed that inFIG. 8, k=0, the SAR ADC10may be designed the same as that in the aforementioned example. However, the SAR ADC10may also be designed into that the comparer130consecutively performs comparison twice in the (N−1)th bit determining duration (namely, the third determining module has two generating units), and consecutively performs comparison thrice in the Nth bit determining duration (namely, the first determining module has three generating units).

In step S38or step S48, the judging unit155may obtain a corresponding output bit in a majority decision manner or in an averaging and round-off manner.

Taking the Nth bit determining duration and m=3 as an example, the judging unit155performs majority decision on the corresponding digit codes BN_a, BN_b, and BN_c to obtain the last output bit BN, as shown in Table 2 below.

In other words, when the majority decision manner is used, m must be an odd number, namely, the number of comparison times of the comparer130in this bit determining duration is an odd number.

Next, taking the Nth bit determining duration and m=3 as an example, the judging unit155performs averaging and round-off (round-off of the decimal place), on the corresponding digit codes BN_a, BN_b, and BN_c to obtain the last output bit BN, as shown in Table 3 below.

FIG. 11is a locally schematic diagram of an SAR ADC according to another embodiment of the present invention.

Taking N=3 as an example, please refer toFIG. 11, in which embodiment, in the first and second bit determining durations, the comparer130individually performs comparison once, while in the third bit determining duration, the comparer130performs comparison thrice.

The SAR control circuit150includes an input logic151, second determining modules153-1and153-2, a first determining module and an output logic. The first determining module includes three generating units154-1,154-2, and154-3and a judging unit155. The output logic includes a logic element1571and an output unit1573. Two input ends of the input logic151are coupled to a positive output end and a negative output end of the comparer130.

The second determining modules153-1and153-2and the generating units154-1,154-2, and154-3may be implemented flip-flops DFF connected in series. Here, each of the second determining modules153-1and153-2and the generating units154-1,154-2, and154-3includes two flip-flops DFF (which are referred to as a first flip-flop DFF and a second flip-flop DFF respectively below for convenience of illustration).

The set end or reset end of the first flip-flop DFF in each of the second determining modules153-1and153-2, and the generating units154-1,154-2, and154-3receives a system clock CKs, and performs setting or resetting according to the system clock CKs.

The output end of each first flip-flop DFF is coupled to the control end of the second flip-flop DFF of the corresponding same bit or same digit code and the input end of the first flip-flop DFF of the corresponding next bit or next digit code. The input end of the first flip-flop DFF of the second determining module153-1is coupled to the power supply end (supply voltage VDD).

In other words, the output end of the first flip-flop DFF of the second determining module153-1is coupled to the control end of the second flip-flop DFF of the second determining module153-1and the input end of the first flip-flop DFF of the second determining module153-2. The output end of the first flip-flop DFF of the second determining module153-2is coupled to the control end of the second flip-flop DFF of the second determining module153-2and the input end of the first flip-flop DFF of the generating unit154-1. The output end of the first flip-flop DFF of the generating unit154-1is coupled to the control end of the second flip-flop DFF of the generating unit154-1and the input end of the first flip-flop DFF of the generating unit154-2. The output end of the first flip-flop DFF of the generating unit154-3is coupled to the control end of the second flip-flop DFF of the generating unit154-3and the first input end of the logic element1571.

The input end of each second flip-flop DFF is coupled to the positive output end of the comparer130. The output end of the second flip-flop DFF of each of the generating units154-1,154-2, and154-3is connected to the input end of the judging unit155. The output end of the second flip-flop DFF of each of the second determining modules153-1and153-2and the output end of the judging unit155are coupled to the output end of the output unit1573, and the output end of the second flip-flop DFF of each of the second determining modules153-1and153-2is electrically connected to the sampling and digital-to-analog converting circuit110.

The output end of the input logic151is coupled to the control end of each first flip-flop DFF and the second input end of the logic element1571. The third input end of the logic element1571receives the system clock CKs. The output end of the logic element1571is connected to the control end of the output unit1573.

The input logic151receives the positive end output and the negative end output (the comparison result OUT_p and OUT_n), of the comparer130, and performs a logic operation on the comparison result OUT_p and OUT_n to output a valid signal Valid to the control end of each first flip-flop DFF and the input end of the logic element1571. In some embodiments, the input logic151may be a NAND gate.

The first flip-flop DFF of the second determining module153-1generates a clock signal CK1according to the valid signal Valid and the supply voltage VDD. The second flip-flop DFF of the second determining module153-1then sets the first output bit B1according to the positive end comparison result OUT_p and the clock signal CK1. Furthermore, the first flip-flop DFF of the second determining module153-1further provides this clock signal CK1to the first flip-flop DFF of the second determining module153-2, so as to be used as input data of the first flip-flop DFF of the second determining module153-2.

The first flip-flop DFF of the second determining module153-2generates a clock signal CK2according to the valid signal Valid and the clock signal CK1. The second flip-flop DFF of the second determining module153-1then sets the second output bit B2according to the positive end comparison result OUT_p and the clock signal CK2. Furthermore, the first flip-flop DFF of the second determining module153-2further provides this clock signal CK2to the first flip-flop DFF of the generating unit154-1, so as to be used as input data of the first flip-flop DFF of the generating unit154-1.

The generating unit154-1generates a clock signal CK3according to the valid signal Valid and the clock signal CK2. The second flip-flop DFF of the generating unit154-1then outputs a digit code B3_a according to the positive end comparison result OUT_p and the clock signal CK3. Furthermore, the first flip-flop DFF of the generating unit154-1further provides this clock signal CK3to the first flip-flop DFF of the generating unit154-2, so as to be used as input data of the first flip-flop DFF of the generating unit154-2.

The generating unit154-2generates a clock signal CK4according to the valid signal Valid and the clock signal CK2. The second flip-flop DFF of the generating unit154-2then outputs a digit code B3_b according to the positive end comparison result OUT_p and the clock signal CK4. Furthermore, the first flip-flop DFF of the generating unit154-2further provides this clock signal CK4to the first flip-flop DFF of the generating unit154-3, so as to be used as input data of the first flip-flop DFF of the generating unit154-3.

The generating unit154-3generates a clock signal CK5according to the valid signal Valid and the clock signal CK4. The second flip-flop DFF of the generating unit154-3then outputs a digit code B3_c according to the positive end comparison result OUT_p and the clock signal CK5. Furthermore, the first flip-flop DFF of the generating unit154-1further provides this clock signal CK5to the logic element1571.

The judging unit155sets the third output bit B3according to the digit codes B3_a, B3_b, and B3_c. Here, the judging unit155may determine the third output bit B3in a majority decision manner or in an averaging and round-off manner.

The logic element1571generates a control clock CKc according to the system clock CKs, the valid signal Valid and the clock signal CK5, so that the output unit1573reads the first output bit B1, the second output bit B2and the third output bit B3according to the control clock CKc, and outputs the first output bit B1, the second output bit B2and the third output bit B3as an output signal B[1:3]. In some embodiments, the logic element1571may be implemented through an OR gate.

In this embodiment, the timing relationship among the system clock CKs, the clock signals CK1to CK5, and the control clock CKc is shown inFIG. 12.

The sampling and digital-to-analog converting circuit110basically includes a plurality of switches and a plurality of capacitors. A first end of each of these capacitors is connected to an input end of the comparer130, and a second end thereof selectively receives a reference voltage through a switch. The SAR control circuit150is coupled to the control end of each of these switches, and determines the potential of the first end of each of these capacitors (such as, the second potential V2) by controlling the operating of these switches. In some embodiments, the sampling and digital-to-analog converting circuit110may include a sampling and storing circuit and a digital-to-analog converter or a capacitive digital-to-analog converter. The implementation aspect and the detailed operating of the sampling and digital-to-analog converting circuit are well known by persons skilled in the art, so no more details are given here.

To summarize, according to the SAR ADC and the method thereof of the present invention, the number of comparison times of the comparer is increased in last several bit determining durations, so under the situation that no complex signal detecting apparatus is added, the influence of a noise (such as: noise interference generated by the comparer, a chip system itself, or a power source), on the SNR of the SAR ADC is effectively reduced. Additionally, for results of a plurality of comparison times, the energy of the noise may be further reduced in a manner of majority decision, averaging and round-off or specific encoding.