Power converter with co-packaged secondary field effect transistors (FETs)

A power converter with co-packaged secondary field effect transistors (FETs) are described. The power converter can include a first circuit, a transformer connected to an output of the first circuit, and a second circuit connected to an output of the transformer. The second circuit can include an inductor, a first FET coupled between the transformer and the inductor, and a second FET coupled between the first FET and ground. The first FET and the second FET can be co-packaged as a single package.

BACKGROUND

The present disclosure relates in general to power converters that utilize a transformer to alter output voltage.

A power converter, such as a forward converter, can use a transformer to increase or decrease voltages. The transformer can include a primary inductor and a secondary inductor magnetically coupled to each other. The amount in which voltage is increased or decreased can be based on a ratio between the size (e.g., winding size) of the primary and secondary inductors. The primary inductor can be connected to a primary circuit (e.g., input section of the power converter) and the secondary inductor can be connected to a secondary circuit (e.g., section of the power converter that receives current from the secondary inductor of the transformer). The primary circuit can receive an input voltage, and the secondary circuit can output voltage that results from the transformer increasing or decreasing the input voltage.

SUMMARY

In some examples, a structure is generally described. The structure can include a transformer, an inductor, and a circuit. The circuit can include a first field-effect transistor (FET) and a second FET. The first FET can be coupled between the transformer and the inductor. The second FET can be coupled between the first FET and ground.

In some examples, a power converter is generally described. The power converter can include a first circuit, a transformer connected to an output of the first circuit, and a second circuit connected to an output of the transformer. The second circuit can include an inductor, a first field-effect transistor (FET) that can be coupled between the transformer and the inductor, and a second FET that can be coupled between the first FET and ground.

In some examples, a method of constructing a power converter is generally described. The method can include arranging a circuit, a transformer, and an inductor on a circuit board. The method can further include connecting the transformer to an output of the circuit. The method can further include forming a package that comprises a first field-effect transistor (FET) and a second FET. The method can further include connecting the first FET of the package to the transformer and to the inductor. The method can further include connecting the second FET of the package to the first FET and a ground terminal of the circuit board.

DETAILED DESCRIPTION

FIG.1illustrates a circuit diagram of a power converter100with co-packaged secondary field effect transistors (FETs) in one embodiment. In an example, secondary FETs can be FETs that are located in a secondary circuit of a power converter. The power converter100can include a primary circuit101(or a control circuit), a secondary circuit102(or a filter circuit), and a transformer103. The primary circuit101can control a flow of current from an input terminal105to the transformer103. The secondary circuit102can control a flow of current outputted by the transformer103towards a load106(e.g., RO).

The example power converter100shown inFIG.1can be an active clamp forward converter. The primary circuit101of an active clamp forward converter can include field-effect transistors (FETs) denoted as QRand QM, and a clamping capacitor denoted as CC. The FETs QRand QMcan be metal-oxide-semiconductor field-effect transistors (MOSFETs), and can include respective body diode. The FETs QRand QMcan be referred to as primary FETs, such as FETs located in the primary circuit101. The FET QMcan operate as a main switch of the power converter100operable to switch the power converter100ON or OFF. When QMis switched ON, current can flow from the input terminal105towards the transformer103. When QMis switched OFF, current may not be able to flow from the input terminal105and the transformer103to FET QM. The FET QRcan be an auxiliary switch, and can be used with the clamping capacitor Ccto reset residual energy flux from the transformer103. InFIG.1, LLdenotes the leakage inductance of the transformer103and LMdenotes the magnetizing inductance of the transformer103.

The transformer103can include a pair of inductors or windings, such as a first winding108and a second winding109. The winding108can be connected to an output of the primary circuit101, and the winding109can be connected to the load106through the secondary circuit102. An input voltage measured at the input terminal105can be denoted as YIN. The winding108of the transformer103can receive current from the input terminal105, through the primary circuit101. A voltage measured at the winding108can be denoted as V1. The transformer103can either increase or decrease V1, resulting in a measurement of voltage V2at the winding109. A difference between V1and V2can be based on sizes (e.g., number of turns) of the winding108and the winding109. For example, the difference between V1and V2can be based on a ratio of the size of the winding to the size of the winding109. Current can flow from the transformer103towards the load106, where an output voltage measured at the load106can be denoted as VOUT.

The secondary circuit102can include a circuit110, an output inductor104(denoted as LO), and an output capacitor CO. The circuit110can be an electronic package, a circuit, or a device, that includes electronic components (e.g., transistors) connected to each other. The circuit110can be connected to the load106. In some examples, the load106(denoted as RO), the output inductor104, and the output capacitor CO, can form a RLC circuit (a circuit with a resistor (R), an inductor (L), a capacitor (C)) that operates as a low pass filter. To be described in more detail below, the circuit110can occupy a relatively small area on a circuit board being used to construct the power converter100. Further, the arrangement of components within the circuit110can provide a reduction in parasitic loss that may result from, for example, a manufacturing process of one or more portions of the power converter100.

FIG.2shows another circuit diagram illustrating a power converter with co-packaged secondary field effect transistors (FETs) in one embodiment.FIG.2may include components that are labeled identically to components ofFIG.1, which are not described again for the purposes of clarity. The description ofFIG.2may reference at least some of the components ofFIG.1.

In an example embodiment shown inFIG.2, the circuit110can include three terminals201,202, and203, and can include two FETs210(denoted as Q1), and212(denoted as Q2). In an example embodiment, the FETs210and212can be N-type FETs. In another example embodiment, the FET210can be a P-type FET and the FET212can be an N-type FET. In another example embodiment, the FETs210and212can be P-type FETs. Although the circuit110shown inFIG.2includes two FETS, other numbers of FETs and various combinations of N-type and P-type FETs are possible, depending on a desirable implementation of the power converter100. The FETs Q1and Q2can be referred to as secondary FETs, such as FETs located in the secondary circuit102. The terminals201,202, and203can be external connections that can connect the circuit110with other components (e.g., transformer103and output inductor104).

In examples where both FET210and212are N-type FETs, the current input terminal, of the FET210can be connected to the winding109of the transformer103through the terminal201. The current output terminal, of the FET210can be connected to the output inductor104through the terminal202. The current input terminal of the FET212, can be connected to ground (GND) through the terminal203. The current output terminal, of the FET212can be connected to the output inductor104through the terminal202. Note that when a FET is an N-type FET, the current input terminal can be the drain terminal and the current output terminal can be the source terminal. When a FET is a P-type FET, the current input terminal can be the source terminal and the current output terminal can be the drain terminal. In some examples, the FET210can operate in a similar manner as a forward bias diode to control current flowing from the transformer103to the output inductor104, and the FET212can operate in a similar manner as a freewheel diode to eliminate sudden voltage spike seen across an inductive load (e.g., RO) when its supply current is suddenly reduced or interrupted. Further, in some examples, when compared to diodes, FETs can have lower conduction loss when conducting current. In an example embodiment, the FETs210and212shown inFIG.2can be integrated as distinct components in a circuit board being used to construct the power converter100.

FIG.3shows another circuit diagram illustrating a power converter with co-packaged secondary field effect transistors (FETs) in one embodiment. Such configuration may include a row-column arrangement of circuit components.FIG.3may include components that are labeled identically to components ofFIGS.1-2, which will not be described again for the purposes of clarity. The description ofFIG.3may reference at least some of the components ofFIGS.1-2.

In an example embodiment shown inFIG.3, the circuit110can include two FETs310(denoted as Q3), and312(denoted as Q4). Each one of the FETs310and312can be N-type FETs or P-type FETS. The FETs Q3and Q4can be referred to as secondary FETs, such as FETs located in the secondary circuit102. In examples where both FET310and FET312are N-type FETs, the current input terminal of the FET310can be connected to the winding109of the transformer103through the terminal201. The current output terminal of the FET310can be connected to the drain terminal of the FET312via an internal connection. The current output terminal of the FET312can be connected to ground (GND) through the terminal203. The current output terminal of the FET310and the current input terminal of the FET312can also be connected to the output inductor104through the terminal202. The current flowing into the inductor104can be fed from either the current output terminal of the FET310or the current input terminal of the FET312. In some examples, the FETs310and/or312can operate in a similar manner as a forward bias diode to control current flowing from the transformer103to the output inductor104, and can operate in a similar manner as a freewheel diode to eliminate sudden voltage spike seen across an inductive load (e.g., RO) when its supply current is suddenly reduced or interrupted.

In the example embodiment shown inFIG.3, the FETs310and312can be co-packaged, such as being packaged within a single electronic package to form the circuit110. The FETs310and312can be co-packaged on the same substrate (e.g., substrate301) in a stacked configuration (e.g., on top of each other). The circuit110can be integrated into a substrate of a circuit board (which can be different from substrate301) being used to construct the power converter100as a single component. In some examples, the FETs310and312can be vertical FETs where a top surface of a vertical FET is a drain terminal and a bottom surface of the vertical FET is a source terminal. In an example shown inFIG.3, the terminal201can represent a piece or layer of metal (e.g., foil) that can connect the FET310to the winding109. The terminal202can represent a piece of metal that can connect the FET310and312to the output inductor104. The terminal203can represent a metal layer on the substrate301that can connect the FET312to ground. Co-packaging the FETs310and312to form the circuit110prior to integrating the circuit110with other components of the power converter100may reduce parasitic loss. Further, the circuit110with co-packaged FETs310and312can occupy a relatively smaller area of a circuit board of the power converter100when compared to integrating the FETs310and312as distinct components.

FIG.4shows another circuit diagram illustrating a power converter with co-packaged secondary field effect transistors (FETs) in one embodiment.FIG.4may include components that are labeled identically to components ofFIGS.1-3, which will not be described again for the purposes of clarity. The description ofFIG.4may reference at least some of the components ofFIGS.1-3.

In an example embodiment shown inFIG.4, the transformer103and the output inductor104can be magnetically coupled using a magnetic core. For example, the transformer103and the output inductor104can be magnetically coupled using a magnetic core401, where the magnetic core401can be an E-shaped magnetic core, or E-core. In the example shown inFIG.4, the magnetic core401can include a leg402, a leg403, and a leg404. The winding108of the transformer103and the winding109of the transformer103can be both wrapped around the leg403to form a transformer. The winding or output inductor104can be wrapped around the leg404, or the leg402, or403plus404, or402plus403. In other words, the leg403can be wrapped by wires and/or coil (e.g., the winding109) between the terminal201and the terminal203, and the leg404can be wrapped by wires and/or coils (e.g., the winding104) between terminal202and terminal203. The wrapping of the winding109of the transformer103around the leg403, and the wrapping of the inductor104around the leg404, causes the transformer103to be magnetically coupled to the output inductor104.

The power converter100can be constructed using the magnetic core401and a magnetic core410, where the magnetic core410can be an I-shaped magnetic core, or I-core. In an example, construction of the power converter100can include arranging components of the primary circuit101, the transformer103, and the output inductor104on a substrate or a circuit board. In some examples, the primary circuit101, the transformer103, and the output inductor104can be arranged or mounted on the circuit board by soldering. The construction of the power converter100can further include co-packaging the FET310and the FET312, in a stacked configuration, to form the circuit110. The circuit110can be integrated or mounted on the circuit board that may already include the primary circuit101, the transformer103, and the output inductor104. In some examples, the circuit110can be mounted to the circuit board by, for example, surface mount, through-hold mount, flip-chip mount, depending on a configuration of the circuit board. The construction of the power converter100can include connecting the circuit110(which may be mounted on the circuit board) to the transformer103via the terminal201, and connecting the circuit110to the output inductor104via the terminal202. The construction of the power converter100can include connecting the circuit110(which may be mounted on the circuit board) to a ground pin, or ground terminal, that may be arranged on the circuit board. The connecting of the circuit110to the transformer103can include wrapping wires and/or coils (e.g., winding109) around the leg403of the magnetic core401. The connecting of the circuit110to the output inductor104can include wrapping wires and/or coils around the leg404or402of the magnetic core401. The magnetic core410can be added to a top side of the magnetic core401, and can be positioned such that an air gap exists between the magnetic core410and the top side of the magnetic core401.

FIG.5shows another circuit diagram illustrating a power converter with co-packaged secondary field effect transistors (FETs) in one embodiment.FIG.5may include components that are labeled identically to components ofFIGS.1-4, which are not described again for the purposes of clarity. The description ofFIG.5may reference at least some of the components ofFIGS.1-4.

In an example embodiment shown inFIG.5, the circuit110can include two FETs510(denoted as Q5), and512(denoted as Q6). The FETs510and512can be N-type FETs. The FETs Q5and Q6can be referred to as secondary FETs, such as FETs located in the secondary circuit102. The drain terminal of the FET510can be connected to the winding109of the transformer103through a terminal501. The source terminal of the FET510and the source terminal of the FET512can be connected to ground (GND) through the terminal503. The drain terminal of the FET512can be connected to the output inductor104through the terminal502. In some examples, the FETs510and/or512can operate in a similar manner as a forward bias diode to control current flowing from the transformer103to the output inductor104, and can operate in a similar manner as a freewheel diode to eliminate sudden voltage spike seen across an inductive load (e.g., RO) when its supply current is suddenly reduced or interrupted.

In the example embodiment shown inFIG.5, the FETs510and512can be co-packaged, such as being packaged within a single electronic package to form the circuit110. The FETs510and512can be co-packaged on the same substrate (e.g., a substrate505) in a stacked configuration. Co-packaging the FETs510and512to form the circuit110prior to integrating the circuit110with other components of the power converter100may reduce parasitic loss. Further, the circuit110with co-packaged FETs510and512can occupy a relatively smaller area of a circuit board of the power converter100when compared to integrating the FETs510and512as distinct components.

FIG.6is a flow diagram illustrating a process600that can be performed to construct a power converter with co-packaged secondary field effect transistors (FETs) in one embodiment. An example process may include one or more operations, actions, or functions as illustrated by one or more of blocks602,604,606, and/or608. Although illustrated as discrete blocks, various blocks can be divided into additional blocks, combined into fewer blocks, eliminated, or performed in parallel, depending on the desired implementation.

The process600can begin at block602, where a circuit, a transformer, and an inductor can be arranged on a circuit board. The process600can continue from block602to block604. At block604, the transformer can be connected to an output of the circuit. The process600can continue from block604to block606. At block606, a package that comprises a first field-effect transistor (FET) and a second FET can be formed. The process600can continue from block606to block608. At block608, the first FET of the package can be connected to the transformer and to the inductor. The process600can continue from block608to block610. At block610, the second FET of the package can be connected to the first FET and a ground terminal of the circuit board. In an example, the first FET and the second FET can be co-packaged in a stacked configuration.

In an example embodiment, the layer of substrate can include a metal layer that can facilitate connections to ground. The second FET can be disposed on top of the metal layer to connect a terminal, such as a current output terminal, of the second FET to ground. A first metal layer can be disposed on top of the second FET, where the first metal layer can operate as a terminal to connect another terminal, such as a current input terminal, of the second FET to one or more components external to the second FET. The first FET can be disposed on top of the first metal layer to connect a terminal, such as a current output terminal, of the first FET to the current input terminal of the second FET via the first metal layer. A second metal layer can be disposed on top of the first FET to connect another terminal, such as current input terminal, of the first FET to one or more components external to the first FET. The transformer can be connected to the first FET via the second metal layer, and the inductor can be connected to the first FET via the first metal layer.