MANUFACTURING METHOD OF DISPLAY DEVICE

According to one embodiment, a manufacturing method is a method for manufacturing a display device including first, second and third display elements which emit light of different colors and includes preparing a substrate, forming the first display element on the substrate, and performing a first lighting inspection for causing the first display element to light up before forming the second display element and the third display element.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2023-021708, filed Feb. 15, 2023, the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to a manufacturing method of a display device.

BACKGROUND

Recently, display devices to which an organic light emitting diode (OLED) is applied as a display element have been put into practical use. This display element comprises a lower electrode, an organic layer which covers the lower electrode, and an upper electrode which covers the organic layer.

Normally, in the manufacturing process of display devices, after all of a plurality of types of display elements which exhibit different colors are formed, lighting inspection of each display element is performed. In this case, when a defect is detected in a display element which exhibits a color in lighting inspection, the substrate which underwent the manufacturing process so far goes to waste.

DETAILED DESCRIPTION

In general, according to one embodiment, a manufacturing method of a display device is a method for manufacturing a display device including first, second and third display elements which emit light of different colors and includes preparing a substrate, forming the first display element on the substrate, and performing a first lighting inspection for causing the first display element to light up before forming the second display element and the third display element.

This configuration can improve the manufacturing yield of the display device.

Embodiments will be described with reference to the accompanying drawings.

In the drawings, in order to facilitate understanding, an X-axis, a Y-axis and a Z-axis orthogonal to each other are shown depending on the need. A direction parallel to the X-axis is referred to as a first direction X. A direction parallel to the Y-axis is referred to as a second direction Y. A direction parallel to the Z-axis is referred to as a third direction Z. The third direction Z is a normal direction relative to a plane including the first direction X and the second direction Y. When various elements are viewed parallel to the third direction Z, the appearance is defined as a plan view.

The display device of each embodiment is an organic electroluminescent display device comprising an organic light emitting diode (OLED) as a display element, and could be mounted on various types of electronic devices such as a television, a personal computer, a vehicle-mounted device, a tablet, a smartphone, a mobile phone and a wearable terminal.

First Embodiment

FIG.1is a diagram showing a configuration example of a display device DSP according to a first embodiment. The display device DSP comprises a display panel PNL including an insulating substrate10. The display panel PNL comprises a display area DA which displays an image, and a surrounding area SA around the display area DA. The substrate10may be glass or a resinous film having flexibility.

In the embodiment, the substrate10is rectangular as seen in plan view. It should be noted that the shape of the substrate10in plan view is not limited to a rectangle and may be another shape such as a square, a circle or an oval.

The display area DA comprises a plurality of pixels PX arrayed in matrix in a first direction X and a second direction Y. Each pixel PX includes a plurality of subpixels SP. For example, each pixel PX includes a blue subpixel SP1, a green subpixel SP2and a red subpixel SP3. Each pixel PX may include a subpixel SP which exhibits another color such as white in addition to subpixels SP1, SP2and SP3or instead of one of subpixels SP1, SP2and SP3.

Each subpixel SP comprises a pixel circuit1and a display element DE driven by the pixel circuit1. The pixel circuit1comprises a pixel switch2, a drive transistor3and a capacitor4. The pixel switch2and the drive transistor3are, for example, switching elements consisting of thin-film transistors.

The gate electrode of the pixel switch2is connected to a scanning line GL. One of the source electrode and drain electrode of the pixel switch2is connected to a signal line SL. The other one is connected to the gate electrode of the drive transistor3and the capacitor4. In the drive transistor3, one of the source electrode and the drain electrode is connected to a power line PL and the capacitor4, and the other one is connected to the display element DE.

It should be noted that the configuration of the pixel circuit1is not limited to the example shown in the figure. For example, the pixel circuit1may comprise more thin-film transistors and capacitors.

FIG.2is a schematic plan view showing an example of the layout of subpixels SP1, SP2and SP3. In the example ofFIG.2, each of subpixels SP2and SP3is adjacent to subpixel SP1in the first direction X. Further, subpixels SP2and SP3are arranged in the second direction Y.

When subpixels SP1, SP2and SP3are provided in line with this layout, in the display area DA, a column in which subpixels SP2and SP3are alternately provided in the second direction Y and a column in which a plurality of subpixels SP1are repeatedly provided in the second direction Y are formed. These columns are alternately arranged in the first direction X. It should be noted that the layout of subpixels SP1, SP2and SP3is not limited to the example ofFIG.2.

A rib5is provided in the display area DA. The rib5comprises pixel apertures (first to third pixel apertures) AP1, AP2and AP3in subpixels SP1, SP2and SP3, respectively. In the example ofFIG.2, the pixel aperture AP1is larger than the pixel aperture AP2. The pixel aperture AP2is larger than the pixel aperture AP3.

Of the lower electrode LE1, the upper electrode UE1and the organic layer OR1, the portions which overlap the pixel aperture AP1constitute the display element (first display element) DE1of subpixel SP1. Of the lower electrode LE2, the upper electrode UE2and the organic layer OR2, the portions which overlap the pixel aperture AP2constitute the display element (second display element) DE2of subpixel SP2. Of the lower electrode LE3, the upper electrode UE3and the organic layer OR3, the portions which overlap the pixel aperture AP3constitute the display element (third display element) DE3of subpixel SP3. Each of the display elements DE1, DE2and DE3may further include a cap layer and a sealing layer as described later. The rib5surrounds each of these display elements DE1, DE2and DE3.

The lower electrode LE1is connected to the pixel circuit1(seeFIG.1) of subpixel SP1through a contact hole CH1. The lower electrode LE2is connected to the pixel circuit1of subpixel SP2through a contact hole CH2. The lower electrode LE3is connected to the pixel circuit1of subpixel SP3through a contact hole CH3.

A partition6is provided on the rib5. The partition6overlaps the rib5as a whole and has the same planar shape as the rib5. In other words, the partition6comprises an aperture in each of subpixels SP1, SP2and SP3. From another viewpoint, the rib5and the partition6are provided between the display elements DE1, DE2and DE3, and have grating shapes as seen in plan view.

FIG.3is a schematic cross-sectional view of the display panel PNL along the III-III line ofFIG.2. A circuit layer11is provided on the substrate10described above. The circuit layer11includes various circuits and lines such as the pixel circuit1, scanning line GL, signal line SL and power line PL shown inFIG.1.

The circuit layer11is covered with an organic insulating layer12. The organic insulating layer12functions as a planarization film which planarizes the irregularities formed by the circuit layer11. Although not shown in the section ofFIG.3, the contact holes CH1, CH2and CH3described above are provided in the organic insulating layer12.

The lower electrodes LE1, LE2and LE3are provided on the organic insulating layer12. The rib5is provided on the organic insulating layer12and the lower electrodes LE1, LE2and LE3. The end portions of the lower electrodes LE1, LE2and LE3are covered with the rib5.

The partition6includes a conductive lower portion61provided on the rib5and an upper portion62provided on the lower portion61. The upper portion62has a width greater than that of the lower portion61. By this configuration, the both end portions of the upper portion62protrude relative to the side surfaces of the lower portion61. This shape of the partition6is called an overhang shape.

The organic layer OR1covers the lower electrode LE1through the pixel aperture AP1. The upper electrode UE1covers the organic layer OR1and faces the lower electrode LE1. The organic layer OR2covers the lower electrode LE2through the pixel aperture AP2. The upper electrode UE2covers the organic layer OR2and faces the lower electrode LE2. The organic layer OR3covers the lower electrode LE3through the pixel aperture AP3. The upper electrode UE3covers the organic layer OR3and faces the lower electrode LE3. The upper electrodes UE1, UE2and UE3are in contact with the side surfaces of the lower portion61of the partition6.

The display element DE1includes a cap layer (first cap layer) CP1provided on the upper electrode UE1. The display element DE2includes a cap layer (second cap layer) CP2provided on the upper electrode UE2. The display element DE3includes a cap layer (third cap layer) CP3provided on the upper electrode UE3. The cap layers CP1, CP2and CP3function as optical adjustment layers which improve the extraction efficiency of the light emitted from the organic layers OR1, OR2and OR3, respectively.

In the following explanation, a multilayer body including the organic layer OR1, the upper electrode UE1and the cap layer CP1is called a stacked film (first stacked film) FL1. A multilayer body including the organic layer OR2, the upper electrode UE2and the cap layer CP2is called a stacked film (second stacked film) FL2. A multilayer body including the organic layer OR3, the upper electrode UE3and the cap layer CP3is called a stacked film (third stacked film) FL3.

The stacked film FL1is partly located on the upper portion62. This portion is spaced apart from, of the stacked film FL1, the portion located under the partition6(in other words, the portion which constitutes the display element DE1). Similarly, the stacked film FL2is partly located on the upper portion62. This portion is spaced apart from, of the stacked film FL2, the portion located under the partition6(in other words, the portion which constitutes the display element DE2). Further, the stacked film FL3is partly located on the upper portion62. This portion is spaced apart from, of the stacked film FL3, the portion located under the partition6(in other words, the portion which constitutes the display element DE3).

The display element DE1includes a sealing layer (first sealing layer) SE1. The display element DE2includes a sealing layer (second sealing layer) SE2. The display element DE3includes a sealing layer (third sealing layer) SE3. The sealing layer SE1continuously covers the stacked film FL1and the partition6around subpixel SP1. The sealing layer SE2continuously covers the stacked film FL2and the partition6around subpixel SP2. The sealing layer SE3continuously covers the stacked film FL3and the partition6around subpixel SP3.

In the example ofFIG.3, the stacked film FL1and sealing layer SE1located on the partition6between subpixels SP1and SP2are spaced apart from the stacked film FL2and sealing layer SE2located on this partition6. The stacked film FL1and sealing layer SE1located on the partition6between subpixels SP1and SP3are spaced apart from the stacked film FL3and sealing layer SE3located on this partition6.

The sealing layers SE1, SE2and SE3are covered with a resin layer13. The resin layer13is covered with a sealing layer14. The sealing layer14is covered with a resin layer15. The resin layers13and15and the sealing layer14are continuously provided in at least the entire display area DA and partly extend in the surrounding area SA as well.

A cover member such as a polarizer, a touch panel, a protective film or a cover glass may be further provided above the resin layer15. This cover member may be attached to the resin layer15via, for example, an adhesive layer such as an optical clear adhesive (OCA).

The organic insulating layer12is formed of an organic insulating material such as polyimide. Each of the rib5and the sealing layers14, SE1, SE2and SE3is formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON) or aluminum oxide (Al2O3). For example, the rib5is formed of silicon oxynitride, and each of the sealing layers14, SE1, SE2and SE3is formed of silicon nitride. Each of the resin layers13and15is formed of, for example, a resinous material (organic insulating material) such as epoxy resin or acrylic resin.

Each of the lower electrodes LE1, LE2and LE3comprises a reflective layer formed of, for example, silver (Ag), and a pair of conductive oxide layers covering the upper and lower surfaces of the reflective layer. Each conductive oxide layer may be formed of, for example, a transparent conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO) or indium gallium zinc oxide (IGZO).

Each of the upper electrodes UE1, UE2and UE3is formed of, for example, a metal material such as an alloy of magnesium and silver (MgAg). For example, the lower electrodes LE1, LE2and LE3correspond to anodes, and the upper electrodes UE1, UE2and UE3correspond to cathodes.

For example, each of the organic layers OR1, OR2and OR3comprises a multilayer structure consisting of a hole injection layer, a hole transport layer, an electron blocking layer, a light emitting layer, a hole blocking layer, an electron transport layer and an electron injection layer. Each of the organic layers OR1, OR2and OR3may comprise a tandem structure including a plurality of light emitting layers.

Each of the cap layers CP1, CP2and CP3comprises, for example, a multilayer structure in which a plurality of transparent thin films are stacked. The thin films may include a thin film formed of an inorganic material and a thin film formed of an organic material. These thin films have refractive indices different from each other. For example, the refractive indices of these thin films are different from the refractive indices of the upper electrodes UE1, UE2and UE3and the refractive indices of the sealing layers SE1, SE2and SE3. It should be noted that at least one of the cap layers CP1, CP2and CP3may be omitted.

The lower portion61of the partition6is formed of, for example, aluminum. The lower portion61may be formed of an aluminum alloy such as an aluminum-neodymium alloy (AlNd), an aluminum-yttrium alloy (AlY) or an aluminum-silicon alloy (AlSi), or may comprise a multilayer structure consisting of an aluminum layer and an aluminum alloy layer. Further, the lower portion61may comprise a bottom layer formed of a metal material different from aluminum and an aluminum alloy under the aluminum layer or the aluminum alloy layer. For the metal material forming the bottom layer, for example, molybdenum (Mo), titanium nitride (TiN), a molybdenum-tungsten alloy (MoW) or a molybdenum-niobium alloy (MoNb) may be used.

For example, the upper portion62of the partition6comprises a multilayer structure consisting of a lower layer formed of a metal material and an upper layer formed of conductive oxide. For the metal material forming the lower layer, for example, titanium, titanium nitride, molybdenum, tungsten, a molybdenum-tungsten alloy or a molybdenum-niobium alloy may be used. For the conductive oxide forming the upper layer, for example, ITO or IZO may be used. It should be noted that the upper portion62may comprise a single-layer structure of a metal material.

Common voltage is applied to the partition6. This common voltage is applied to each of the upper electrodes UE1, UE2and UE3which are in contact with the side surfaces of the lower portions61. Pixel voltage is applied to the lower electrodes LE1, LE2and LE3through the pixel circuits1provided in subpixels SP1, SP2and SP3, respectively.

The organic layers OR1, OR2and OR3emit light based on the application of voltage. Specifically, when a potential difference is formed between the lower electrode LE1and the upper electrode UE1, the light emitting layer of the organic layer OR1emits light in a blue wavelength range. When a potential difference is formed between the lower electrode LE2and the upper electrode UE2, the light emitting layer of the organic layer OR2emits light in a green wavelength range. When a potential difference is formed between the lower electrode LE3and the upper electrode UE3, the light emitting layer of the organic layer OR3emits light in a red wavelength range.

As another example, the light emitting layers of the organic layers OR1, OR2and OR3may emit light exhibiting the same color (for example, white). In this case, the display device DSP may comprise color filters which convert the light emitted from the light emitting layers into light exhibiting colors corresponding to subpixels SP1, SP2and SP3. The display device DSP may comprise a layer including quantum dots which generate light exhibiting colors corresponding to subpixels SP1, SP2and SP3by the excitation caused by the light emitted from the light emitting layers.

When the display device DSP is manufactured, a large mother substrate in which a plurality of areas (panel portions) each corresponding to the display panel PNL are formed is prepared. A configuration which could be applied to this mother substrate is explained below.

FIG.4is a schematic plan view of a mother substrate MB (a mother substrate for a display device) according to the embodiment. The mother substrate MB comprises an insulating substrate10awhich is a base. In the example ofFIG.4, the substrate10ais rectangular. However, the shape is not limited to this example.

The substrate10acomprises a plurality of panel portions PP arranged in matrix. The outer shape of each panel portion PP corresponds to a cut line for cutting the panel portion PP from the mother substrate MB. Each panel portion PP comprises the display area DA and surrounding area SA described above.

Now, this specification explains the manufacturing facility and manufacturing method of the mother substrate MB and the display device DSP. In the embodiment, this specification assumes a case where the display element DE1is formed firstly, and the display element DE2is formed secondly, and the display element DE3is formed lastly. It should be noted that the formation order of the display elements DE1, DE2and DE3is not limited to this example.

FIG.5is a diagram schematically showing the configuration of part of the manufacturing facility. The manufacturing facility comprises manufacturing lines ML1, ML2, ML3and ML4and an inspection device7. The manufacturing line ML1forms the stacked film FL1and the sealing layer SE1. The manufacturing line FL2forms the stacked film FL2and the sealing layer SE2. The manufacturing line ML3forms the stacked film FL3and the sealing layer SE3. The manufacturing line ML4forms the resin layer13, the sealing layer14and the resin layer15. Each of the manufacturing lines ML1, ML2, ML3and ML4includes a plurality of evaporation devices for forming various elements, a chemical vapor deposition (CVD) device, etc. These evaporation devices, CVD device and the like include a chamber maintained as a vacuum.

In the figure, the dashed arrows show the conveyance path of the mother substrate MB. The mother substrate MB is conveyed through the manufacturing lines ML1, ML2, ML3and ML4in order. InFIG.5, manufacturing lines for performing the process prior to the manufacturing line ML1and manufacturing lines for performing the process subsequent to the manufacturing line ML4are omitted.

The inspection device7performs the lighting inspection of the display elements DE1, DE2and DE3formed in the mother substrate MB. In the example ofFIG.5, the inspection device7comprises a controller70and cameras71,72,73and74. The camera71captures an image of the mother substrate MB which underwent the manufacturing line ML1. The camera72captures an image of the mother substrate MB which underwent the manufacturing line ML2. The camera73captures an image of the mother substrate MB which underwent the manufacturing line ML3. The camera74captures an image of the mother substrate MB which underwent the manufacturing line ML4. The images captured by the cameras71,72,73and74may be color images or monochromatic images.

The controller70causes the cameras71,72,73and74to capture an image of the mother substrate MB in which at least one of the display elements DE1, DE2and DE3lights up. Further, the controller70detects a lighting defect based on the images captured by the cameras71,72,73and74.

It should be noted that the number of cameras provided in the inspection device7is not limited to four. For example, the inspection device7may comprise only one camera. In this case, the conveyance path of the mother substrate MB may be set such that the mother substrate MB which underwent each of the manufacturing lines ML1, ML2, ML3and ML4is conveyed to the capture position of the camera.

FIG.6is a flowchart showing an example of the manufacturing method of the display device DSP. Each ofFIG.7toFIG.17is a diagram showing a process of the manufacturing method. To manufacture the display device DSP, first, a large substrate10aincluding areas corresponding to a plurality of panel portions PP is prepared (process PR1). Subsequently, the circuit layer11and the organic insulating layer12are formed on the substrate10a(process PR2).

After process PR2, the lower electrodes LE1, LE2and LE3are formed (process PR3). Further, the rib5and the partition6are formed (process PR4). The flow of process PR4is as shown inFIG.7andFIG.8.

Specifically, first, as shown inFIG.7, an inorganic insulating layer100which should be processed into the rib5is formed in the entire mother substrate MB. Further, a first layer101which should be processed into the lower portion61is formed on the inorganic insulating layer100. A second layer102which should be processed into the upper portion62is formed on the first layer101.

Subsequently, as shown inFIG.8, the first layer101and the second layer102are patterned. This patterning includes etching for processing the second layer102into the shape of the upper portion62and etching for processing the first layer101into the shape of the lower portion61. By these etching processes, the partition6including the lower portion61and the upper portion62is formed in the display area DA.

After the formation of the partition6, as shown inFIG.8, the pixel apertures AP1, AP2and AP3are formed in the inorganic insulating layer100. By this process, the rib5is formed in the display area DA.FIG.7andFIG.8show a case where the pixel apertures AP1, AP2and AP3are formed after the formation of the partition6. As another example, the partition6may be formed after the formation of the pixel apertures AP1, AP2and AP3.

After the formation of the rib5and the partition6, the mother substrate MB is conveyed to the manufacturing line ML1, and a process for forming the display element DE1is performed. To form the display element DE1, first, as shown inFIG.9, the stacked film FL1and the sealing layer SE1are formed (process PR5). The stacked film FL1includes, as shown inFIG.3, the organic layer OR1which is in contact with the lower electrode LE1through the pixel aperture AP1, the upper electrode UE1which covers the organic layer OR1and the cap layer CP1which covers the upper electrode UE1. The organic layer OR1, the upper electrode UE1and the cap layer CP1are formed by vapor deposition. The sealing layer SE1is formed by CVD.

The stacked film FL1is divided into a plurality of portions by the partition6having an overhang shape. The stacked film FL1covers the lower electrodes LE1, LE2and LE3exposed through the pixel apertures AP1, AP2and AP3, the rib5and the partition6. The sealing layer SE1continuously covers the divided portions of the stacked film FL1and the partition6.

After process PR5, the stacked film FL1and the sealing layer SE1are patterned (process PR6). In this patterning, as shown inFIG.9, a resist R1is provided on the sealing layer SE1. The resist R1covers subpixel SP1and part of the partition6around the subpixel.

Subsequently, as shown inFIG.10, the portions of the stacked film FL1and the sealing layer SE1exposed from the resist R1are removed by etching using the resist R1as a mask. In other words, of the stacked film FL1and the sealing layer SE1, the portions which overlap the lower electrode LE1remain, and the other portions are removed. By this process, the display element DE1is formed in subpixel SP1. For example, this etching includes dry etching and wet etching processes which are performed in order for the sealing layer SE1, the cap layer CP1, the upper electrode UE1and the organic layer OR1. After this etching, the resist R1is removed.

In each panel portion PP of the mother substrate MB which underwent the above process PR6, the display element DE1is formed in subpixel SP1, and neither the display element DE2nor the display element DE3is formed in subpixel SP2or subpixel SP3. In each display element DE1, the stacked film FL1is formed in an area surrounded by the partition6which overlaps the end portion of the lower electrode LE1. Further, the sealing layer SE1continuously covers the stacked film FL1and the partition6around the stacked film FL1.

After process PR6, a first lighting inspection is performed by the inspection device7(process PR7). When the first lighting inspection is performed, the mother substrate MB which underwent the manufacturing line ML1is provided in the air. Further, a terminal provided in the mother substrate MB for inspection is electrically connected to the inspection device7.

FIG.11is a plan view showing an example of the first lighting inspection and shows part of the display area DA. The shaded portions shown inFIG.11indicate areas which light up in the first lighting inspection. Thus, the controller70of the inspection device7causes all of the display elements DE1included in the display area DA to simultaneously light up. Further, the controller70causes the camera71to capture an image of the display area DA in a state where the display elements DE1light up.

Subsequently, the controller70determines whether or not a defect is present regarding a plurality of predetermined inspection items based on the image captured by the camera71. For example, as the inspection items, the non-uniformity in luminance in the entire display area DA, a defect in the luminance and color chromaticity of each display element DE1and a pixel defect and line defect in the display area DA are considered. A pixel defect indicates that a display element (in the first lighting inspection, a display element DE1) which does not light up at any time or lights up with a higher luminance than the surrounding area at all times is present. A line defect indicates that a display defect is generated in a plurality of display elements (in the first lighting inspection, display elements DE1) which are linearly arranged.

The condition for determining that a defect is present regarding each inspection item is set in advance and stored in a memory of the controller70. For example, as the condition regarding a pixel defect, the threshold to be compared with the number of pixels having a defect in the display area DA in the image can be used. Regarding the other inspection items, similarly, the thresholds to be compared with the values obtained from the image may be determined as the conditions for the determination of defects.

The first lighting inspection may be performed at the same time for all of the panel portions PP provided in the mother substrate MB. As another example, in the first lighting inspection, the panel portions PP provided in the mother substrate MB may be divided into some groups, and the first lighting inspection may be performed for each of these groups.

When a defect is detected regarding an inspection item in the first lighting inspection (NG in process PR7), the manufacturing facility is stopped (process PR21). For example, the mother substrate MB in which a defect has been detected is discarded without going through the subsequent process. Cleaning is performed for part of or all of the chambers included in the manufacturing line ML1.

When a defect is not detected for any inspection item in the first lighting inspection (OK in process PR7), the mother substrate MB is conveyed to the manufacturing line ML2, and a process for forming the display element DE2is performed.

The display element DE2is formed by a procedure similar to that of the display element DE1. Specifically, to form the display element DE2, first, as shown inFIG.12, the stacked film FL2and the sealing layer SE2are formed (process PR8). The stacked film FL2includes, as shown inFIG.3, the organic layer OR2which is in contact with the lower electrode LE2through the pixel aperture AP2, the upper electrode UE2which covers the organic layer OR2and the cap layer CP2which covers the upper electrode UE2. The organic layer OR2, the upper electrode UE2and the cap layer CP2are formed by vapor deposition. The sealing layer SE2is formed by CVD. The stacked film FL2is divided into a plurality of portions by the partition6having an overhang shape. The sealing layer SE2continuously covers the divided portions of the stacked film FL2and the partition6.

After process PR8, the stacked film FL2and the sealing layer SE2are patterned (process PR9). In this patterning, as shown inFIG.12, a resist R2is provided on the sealing layer SE2. The resist R2covers subpixel SP2and part of the partition6around the subpixel.

Subsequently, as shown inFIG.13, the portions of the stacked film FL2and the sealing layer SE2exposed from the resist R2are removed by etching using the resist R2as a mask. By this process, the display element DE2is formed in subpixel SP2.

After process PR9, a second lighting inspection is performed by the inspection device7(process PR10). When the second lighting inspection is performed, the mother substrate MB which underwent the manufacturing line ML2is provided in the air. Further, the terminal provided in the mother substrate MB for inspection is electrically connected to the inspection device7.

FIG.14is a plan view showing an example of the second lighting inspection and shows part of the display area DA. The shaded portions shown inFIG.14indicate areas which light up in the second lighting inspection. Thus, as shown inFIG.14(a), the controller70of the inspection device7causes all of the display elements DE1included in the display area DA to simultaneously light up, and causes the camera72to capture an image of the display area DA in a state where the display elements DE1light up.

Subsequently, as shown inFIG.14(b), the controller70causes all of the display elements DE2included in the display area DA to simultaneously light up, and causes the camera72to capture an image of the display area DA in a state where the display elements DE2light up.

Further, as shown inFIG.14(c), the controller70causes all of the display elements DE1and all of the display elements DE2included in the display area DA to simultaneously light up, and causes the camera72to capture an image of the display area DA in a state where the display elements DE1and DE2light up.

Subsequently, the controller70determines whether or not a defect is present regarding a plurality of predetermined inspection items based on each image captured by the camera72. The inspection items of the second lighting inspection are, for example, the same as the first lighting inspection. Different inspection items or different conditions for the determination of detects may be determined for the images obtained inFIG.14(a),FIG.14(b)andFIG.14(c).

The second lighting inspection may be performed at the same time for all of the panel portions PP provided in the mother substrate MB. As another example, in the second lighting inspection, the panel portions PP provided in the mother substrate MB may be divided into some groups, and the second lighting inspection may be performed for each of these groups.

When a defect is detected regarding an inspection item in the second lighting inspection (NG in process PR10), the manufacturing facility is stopped (process PR22). For example, the mother substrate MB in which a defect has been detected is discarded without going through the subsequent process. Cleaning is performed for part of or all of the chambers included in the manufacturing line ML2.

When a defect is not detected for any inspection item in the second lighting inspection (OK in process PR10), the mother substrate MB is conveyed to the manufacturing line ML3, and a process for forming the display element DE3is performed.

The display element DE3is formed by a procedure similar to the procedures of the display elements DE1and DE2. Specifically, to form the display element DE3, first, as shown inFIG.15, the stacked film FL3and the sealing layer SE3are formed (process PR11). The stacked film FL3includes, as shown inFIG.3, the organic layer OR3which is in contact with the lower electrode LE3through the pixel aperture AP3, the upper electrode UE3which covers the organic layer OR3and the cap layer CP3which covers the upper electrode UE3. The organic layer OR3, the upper electrode UE3and the cap layer CP3are formed by vapor deposition. The sealing layer SE3is formed by CVD. The stacked film FL3is divided into a plurality of portions by the partition6having an overhang shape. The sealing layer SE3continuously covers the divided portions of the stacked film FL3and the partition6.

After process PR11, the stacked film FL3and the sealing layer SE3are patterned (process PR12). In this patterning, as shown inFIG.15, a resist R3is provided on the sealing layer SE3. The resist R3covers subpixel SP3and part of the partition6around the subpixel.

Subsequently, as shown inFIG.16, the portions of the stacked film FL3and the sealing layer SE3exposed from the resist R3are removed by etching using the resist R3as a mask. By this process, the display element DE3is formed in subpixel SP3.

After process PR12, a third lighting inspection is performed by the inspection device7(process PR13). When the third lighting inspection is performed, the mother substrate MB which underwent the manufacturing line ML3is provided in the air. Further, the terminal provided in the mother substrate MB for inspection is electrically connected to the inspection device7.

FIG.17is a plan view showing an example of the third lighting inspection and shows part of the display area DA. The shaded portions shown inFIG.17indicate areas which light up in the third lighting inspection. Thus, as shown inFIG.17(a), the controller70of the inspection device7causes all of the display elements DE1included in the display area DA to simultaneously light up, and causes the camera73to capture an image of the display area DA in a state where the display elements DE1light up.

Subsequently, as shown inFIG.17(b), the controller70causes all of the display elements DE2included in the display area DA to simultaneously light up, and causes the camera73to capture an image of the display area DA in a state where the display elements DE2light up.

Subsequently, as shown inFIG.17(c), the controller70causes all of the display elements DE3included in the display area DA to simultaneously light up, and causes the camera73to capture an image of the display area DA in a state where the display elements DE3light up.

Further, as shown inFIG.17(d), the controller70causes all of the display elements DE1, DE2and DE3included in the display area DA to simultaneously light up, and causes the camera73to capture an image of the display area DA in a state where the display elements DE1, DE2and DE3light up.

Subsequently, the controller70determines whether or not a defect is present regarding a plurality of predetermined inspection items based on each image captured by the camera73. The inspection items of the third lighting inspection are, for example, the same as the first and second lighting inspections. Different inspection items or different conditions for the determination of detects may be determined for the images obtained inFIG.17(a),FIG.17(b),FIG.17(c)andFIG.17(d).

The third lighting inspection may be performed at the same time for all of the panel portions PP provided in the mother substrate MB. As another example, in the third lighting inspection, the panel portions PP provided in the mother substrate MB may be divided into some groups, and the third lighting inspection may be performed for each of these groups.

When a defect is detected regarding an inspection item in the third lighting inspection (NG in process PR13), the manufacturing facility is stopped (process PR23). For example, the mother substrate MB in which a defect has been detected is discarded without going through the subsequent process. Cleaning is performed for part of or all of the chambers included in the manufacturing line ML3.

When a defect is not detected for any inspection item in the third lighting inspection (OK in process PR13), the mother substrate MB is conveyed to the manufacturing line ML4, and the resin layer13, sealing layer14and resin layer15shown inFIG.3are formed in order (process PR14). Further, the mother substrate MB which underwent the manufacturing line ML4is provided in the air, and a fourth lighting inspection is performed (process PR15).

The flow of the fourth lighting inspection is, for example, the same as the third lighting inspection shown inFIG.17. When a defect is detected regarding an inspection item in the fourth lighting inspection (NG in process PR15), the manufacturing facility is stopped (process PR24). For example, the mother substrate MB in which a defect has been detected is discarded without going through the subsequent process. Cleaning is performed for part of or all of the chambers included in the manufacturing line ML4.

When a defect is not detected for any inspection item in the fourth lighting inspection (OK in process PR15), each panel portion PP is cut out from the mother substrate MB (process PR16). Each of the panel portions PP which have been cut out corresponds to the display panel PNL.

As described above, in the embodiment, the first to fourth lighting inspections are performed for the display device DSP (mother substrate MB) in the middle of manufacturing. As a comparative example of the embodiment, a lighting inspection (fourth lighting inspection) may be performed for only the mother substrate MB immediately before the panel portions PP are cut. However, in this case, for example, even if a defect is generated in the process of forming the display element DE1, the defect can be detected only after the formation of the other elements such as the display elements DE2and DE3.

To the contrary, if the first lighting inspection is performed immediately after the formation of the display element DE1as in the case of the embodiment, manufacturing can be stopped so as not to uselessly perform the process of forming the display element DE2or DE3.

In the embodiment, the stacked film FL1of the display element DE1is sealed by the sealing layer SE1before the formation of the display elements DE2and DE3. If the stacked film FL1is not sealed until the formation of the display elements DE2and DE3, to prevent moisture from entering the stacked film FL1, the mother substrate MB should undergo a lighting inspection in a vacuum environment. To the contrary, in the configuration of the display element DE1of the embodiment, a lighting inspection can be performed in the air. In this manner, the configuration of the manufacturing facility for lighting inspection can be simplified.

In the embodiment, the second lighting inspection is performed immediately after the formation of the display element DE2, and the third lighting inspection is performed immediately after the formation of the display element DE3. Thus, effects similar to those explained regarding the display element DE1are obtained for the display elements DE2and DE3.

Second Embodiment

A second embodiment is explained. The configurations or effects which are not particularly referred to are the same as the first embodiment.

FIG.18is a flowchart showing an example of the manufacturing method of a display device DSP according to the second embodiment. Process PR1to process PR16are the same as the first embodiment (seeFIG.6). In this embodiment, instead of processes PR21, PR22and PR23shown inFIG.6, processes PR31, PR32and PR33are performed.

Specifically, when a defect is detected regarding an inspection item in a first lighting inspection (NG in process PR7), a sealing layer SE1and a stacked film FL1are removed from a mother substrate MB (process PR31). This process includes dry etching and wet etching for removing the sealing layer SE1and the stacked film FL1in series.

After process PR31, processes PR5to PR7are performed again. Specifically, a sealing layer SE1and a stacked film FL1are formed in the mother substrate MB. A display element DE1is formed again by patterning these sealing layer SE1and stacked film FL1. Further, the first lighting inspection is performed again. After process PR31, part of or all of the chambers included in a manufacturing line ML1may be cleaned before process PR5is performed again.

In a second lighting inspection, similarly, when a defect is detected regarding an inspection item (NG in process PR10), a sealing layer SE2and a stacked film FL2are removed from the mother substrate MB (process PR32). For example, process PR32includes a process for covering the display element DE1with a resist and removing the sealing layer SE2and the stacked film FL2in series by dry etching and wet etching.

After process PR32, processes PR8to PR10are performed again. Specifically, a sealing layer SE2and a stacked film FL2are formed in the mother substrate MB. A display element DE2is formed again by patterning these sealing layer SE2and stacked film FL2. Further, the second lighting inspection is performed again. After process PR32, part of or all of the chambers included in a manufacturing line ML2may be cleaned before process PR8is performed again.

In a third lighting inspection, similarly, when a defect is detected regarding an inspection item (NG in process PR13), a sealing layer SE3and a stacked film FL3are removed from the mother substrate MB (process PR33). For example, process PR13includes a process for covering the display elements DE1and DE2with a resist and removing the sealing layer SE3and the stacked film FL3in series by dry etching and wet etching.

After process PR33, processes PR11to PR13are performed again. Specifically, a sealing layer SE3and a stacked film FL3are formed in the mother substrate MB. A display element DE3is formed again by patterning these sealing layer SE3and stacked film FL3. Further, the third lighting inspection is performed again. After process PR33, part of or all of the chambers included in a manufacturing line ML3may be cleaned before process PR11is performed again.

In the example ofFIG.18, when a defect is detected regarding an inspection item in a fourth lighting inspection (NG in process PR15), the manufacturing facility is stopped in a manner similar to that of process PR24ofFIG.6(process PR34). As another example, the display elements DE1, DE2and DE3, the resin layer13, the sealing layer14and the resin layer15may be removed in process PR34. Further, for this mother substrate MB after the removal, the process from process PR5may be performed again.

By the manufacturing method of the embodiment, even if a defect is found in the first to third lighting inspections, the mother substrate MB can be reused. By this configuration, a further improvement in yield can be expected.

All of the display devices that can be implemented by a person of ordinary skill in the art through arbitrary design changes to the display device described above as the embodiments of the present invention come within the scope of the present invention as long as they are in keeping with the spirit of the present invention.

Various modification examples which may be conceived by a person of ordinary skill in the art in the scope of the idea of the present invention will also fall within the scope of the invention. For example, even if a person of ordinary skill in the art arbitrarily modifies the above embodiments by adding or deleting a structural element or changing the design of a structural element, or adding or omitting a step or changing the condition of a step, all of the modifications fall within the scope of the present invention as long as they are in keeping with the spirit of the invention.

Further, other effects which may be obtained from each embodiment and are self-explanatory from the descriptions of the specification or can be arbitrarily conceived by a person of ordinary skill in the art are considered as the effects of the present invention as a matter of course.