Phase interpolator

Apparatus to implement several high performance phase interpolators are disclosed. Some embodiments are directed to a full-wave integrating phase interpolation core comprising two pairs of in-phase and quadrature-phase current DACs arranged in a cascode architecture to drive an integrating capacitor and produce an interpolation voltage waveform. The current DACs are biased, weighted, and controlled by in-phase and quadrature-phase input clocks to yield an interpolation waveform that presents a phase value between the phases of the input clocks. Some embodiments deploying the interpolator core use feedback circuitry and reference voltages to adjust the common mode and amplitude of the interpolation voltage waveform to obtain both optimal performance and operation within the interpolator linear region or output compliance range. Both the single-core and dual-core implementations, as well as other implementations of the interpolator core, exhibit high power supply rejection, highly linear interpolation, a wide frequency range, and low cost duty cycle correction.

BACKGROUND

Data communication speeds in electronic systems continue to increase well into multiple Gbps (gigabits per second). Such speeds are prevalent in systems deploying serial data communication PHYs (physical layers) and in standards that include physical layer specifications (e.g., PCIe1/2/3, SATA 1/2/3, GbE, XAUI/2xXAUI, 10GBase-KR, Interlaken, USB 2/3, etc.) as well as in memory data standards for interfaces (e.g., DDR3, DDR4, LPDDR3, LPDDR4, etc.). At these speeds, clock and data recovery (CDR) circuitry is required to accurately (with low bit-error rate) recover the received data. Many CDR circuits include phase interpolators to enable adjustment of the phase of the clock or clocks used to sample or re-time the incoming data stream.

Unfortunately, legacy phase interpolators have limited capabilities. As data speeds increase and power budgets decrease in electronic systems, particularly in mobile or battery-powered applications, circuits must also scale to lower power consumption levels and accommodate more sophisticated power management schemes that deploy lower supply voltages, increased power state switching. Such circuits may be subjected to the presence of relatively higher power supply noise. Legacy phase interpolators have not scaled with today's power requirements both in terms of power consumption and power supply rejection (PSR). Further, legacy phase interpolators do not exhibit highly linear interpolation between phases, which limits phase adjustment accuracy and can be insufficient for higher speed data. Legacy phase interpolators are also limited in the frequency range over which the interpolator can be used, in turn limiting the re-use of the core design which is critical in today's fast time-to-market and cost sensitive electronics industry. Still worse, legacy phase interpolators deploy complicated phase and duty cycle adjustment techniques that require significant integrated circuit area and potentially longer calibration and test times.

Techniques are needed to address the problem of implementing a low power phase interpolator that exhibits high power supply rejection, highly linear interpolation, over a wide frequency range, and exhibiting low cost duty cycle distortion.

None of the aforementioned legacy approaches achieve the capabilities of the herein-disclosed high performance phase interpolators. Therefore, there is a need for improvements.

SUMMARY

The present disclosure provides improved systems and methods to address the aforementioned issues with legacy approaches. More specifically, the present disclosure provides a detailed description of techniques used in systems and methods for high performance phase interpolators. Some of the claimed embodiments address the problem of implementing a low power phase interpolator that exhibits high power supply rejection, highly linear interpolation, a wide frequency range of operation, and low cost duty cycle correction. More specifically, some claims are directed to approaches for combining two full-wave integrating phase interpolation cores with feedback to form a pseudo-differential interpolator architecture with duty cycle control. Such claims advance the technical fields for addressing the problem of implementing low power phase interpolators, as well as advancing peripheral technical fields. Some claims improve the functioning of multiple systems within the disclosed environments.

Some embodiments of the present disclosure are directed to a full-wave integrating phase interpolation core comprising a pair of in-phase and quadrature-phase digitally-controlled current sources (e.g., current DACs), and a pair of in-phase and quadrature-phase digitally-controlled current sinks (e.g., multiplying DACs), arranged in a cascode architecture to drive an integrating capacitor and produce an interpolation voltage waveform (e.g., triangle wave). The current sources and current sinks are biased, weighted, and controlled by in-phase and quadrature-phase input clocks to yield an interpolation waveform that represents a phase interpolated between the phases of the input clocks. Some embodiments deploying the interpolator core use feedback circuitry (e.g. switched capacitor feedback, linear feedback, etc.) and digitally-controlled reference voltages to adjust the common mode and amplitude of the interpolation voltage waveform to obtain highly-tuned performance and operation within the interpolator linear region or output compliance range. The interpolation core can be deployed in a single-core implementation with a comparator output stage that compares the interpolation voltage waveform to a digitally-controlled reference voltage to produce an interpolation clock output. The interpolation core can also be deployed in a dual-core implementation that generates a pseudo-differential interpolation voltage waveform that a comparator can convert to an interpolation clock output. Both the single-core and dual-core implementations, as well as other implementations of the interpolator core, exhibit high power supply rejection, highly linear interpolation, a wide frequency range, and low cost duty cycle correction.

DETAILED DESCRIPTION

Overview

High speed data communication in electronic systems requires CDR circuitry with phase interpolators to accurately recover received data. The legacy phase interpolators deployed today, however, have limited capability. For example, legacy phase interpolators have not scaled with today's power requirements both in terms of power consumption and power supply rejection or “PSR”. Further, legacy phase interpolators do not exhibit highly linear interpolation between phases, which limits phase adjustment accuracy and can be insufficient for higher speed data. Legacy phase interpolators are also limited in the frequency range over which the interpolator can be used, in turn limiting the re-use of the core design which is critical in today's fast time-to-market and cost sensitive electronics industry. Finally, legacy phase interpolators deploy complicated phase and duty cycle adjustment techniques that require significant chip area and potentially longer calibration and test times, all contributing to overall chip costs.

Some embodiments of the present disclosure address the problem of implementing a low power phase interpolator that exhibits high power supply rejection, highly linear interpolation, a wide frequency range, and low cost duty cycle correction and some embodiments are directed to approaches for combining two full-wave integrating phase interpolation cores with feedback to form a pseudo-differential interpolator architecture. More particularly, disclosed herein and in the accompanying figures are exemplary environments, methods, and systems for high performance phase interpolators.

Some embodiments of the present disclosure are directed to a full-wave integrating phase interpolation core comprising a pair of in-phase and quadrature-phase digitally-controlled current sources (e.g., current DACs), and a pair of in-phase and quadrature-phase digitally-controlled current sinks (e.g., multiplying DACs), arranged in a cascode architecture to drive an integrating capacitor and produce an interpolation voltage waveform (e.g., triangle wave). The current sources and current sinks are biased, weighted, and controlled by in-phase and quadrature-phase input clocks to yield an interpolation waveform that represents a phase interpolated between the phases of the input clocks. Some embodiments deploying the interpolator core use feedback circuitry (e.g. switched capacitor feedback, linear feedback) and digitally-controlled reference voltages to adjust the common mode and amplitude of the interpolation voltage waveform to obtain both optimal performance and operation within the interpolator linear region or output compliance range. The interpolation core can be deployed in a single-core implementation with a comparator output stage that compares the interpolation voltage waveform to a digitally-controlled reference voltage to produce an interpolation clock output. The interpolation core can also be deployed in a dual-core implementation that generates a pseudo-differential interpolation voltage waveform that a comparator can convert to an interpolation clock output. Both the single-core and dual-core implementations, as well as other implementations of the interpolator core, exhibit high power supply rejection, highly linear interpolation, a wide frequency range, and low cost duty cycle correction.

Definitions

Reference is now made in detail to certain embodiments. The disclosed embodiments are not intended to be limiting of the claims.

DESCRIPTIONS OF EXEMPLARY EMBODIMENTS

FIG. 1depicts a data receiver system100that includes a phase interpolator.

As shown inFIG. 1, system100comprises a data sampler102, a reference clock loop104, and a clock and data recovery circuit106(CDR) including a phase interpolator108. System100can be implemented as a stand-alone chip, a system-on-chip (“SOC”), or larger electronic system. System100can also be representative of similar systems in a variety of environments and applications, such as serial data communication links and memory data interfaces. System100illustrates that input data110from such environments and applications is received by data sampler102and sampled according to the timing and phase attributes of a sampling clock112to produce recovered data114. Sampling clock112can comprise more than one signal (e.g., data clock and edge clock) depending on the design requirements of data sampler102. Sampling clock112is generated by CDR circuit106utilizing multiple reference clocks116having varying phases and produced by reference clock loop104. Phase interpolator108is a critical component of CDR circuit106and system100in that it generates and controls the timing and phase of sampling clock112required for an accurate sampling and recovery of input data110. Phase interpolator108accomplishes this, in part, by controlled interpolation of the phases of reference clocks116provided by reference clock loop104. Phase interpolator108can also require various feedback and control signals118to provide the required sampling clock112. Feedback and control signals118can originate internally (e.g., from feedback and control1181) and/or can originate or derive from a local component (e.g., from feedback and control1182) and/or can originate or derive from an external source.

The system100can be implemented in a semiconductor package, and the semiconductor package may include components in addition to the elements shown inFIG. 1. For example, a semiconductor package may have a boundary (e.g., semiconductor package boundary1011) within which is disposed a memory core and/or a decoder core. In some situations, a semiconductor package might comprise an integrated transceiver circuit device that might have a relatively smaller boundary (e.g., semiconductor package boundary1012) within which is disposed one or more components in addition to the shown CDR circuitry.

FIG. 2Ais a diagram of a digital phase interpolator2A00. As an option, one or more instances of digital phase interpolator2A00or any aspect thereof may be implemented in the context of the architecture and functionality of the embodiments described herein. Also, digital phase interpolator2A00or any aspect thereof may be implemented in any desired environment.

As shown inFIG. 2A, digital phase interpolator2A00comprises a first selectable clock buffer set2021, a second selectable clock buffer set2022, and an output clock buffer206. First clock buffer set2021receives at each buffer input of set2021a clock signal phn203having a first phase, and second clock buffer set2022receives at each buffer input of set2022a clock signal phn-1204having a second phase. The outputs of each buffer in first clock buffer set2021and second clock buffer set2022are summed or mixed at output clock buffer206to provide an output clock signal clkout207having an interpolated phase. Each buffer in clock buffer sets2021and2022is controlled (e.g., enabled or disabled) by a set of digital buffer control signals205having a separate control signal for each buffer in set2021and a corresponding complement control signal for each buffer in set2022. For example, if clock buffer sets2021and2022each have sixteen buffers, the digital buffer control signals205will comprise sixteen digital signals to control set2021and the complement of those sixteen digital signals to control set2022. By selecting various combinations of control signals205, or “weighting” the clock buffers, the clock buffers will compete or “jam” each other to produce a clock signal clkout207having a phase between the phase of clock signal phn203and the phase of clock signal phn-1204.

FIG. 2Bdepicts selected waveforms2B00of a digital phase interpolator. As shown inFIG. 2B, waveforms2B00comprises timing diagrams for clock signals phn203, phn-1204, and clkout207from digital phase interpolator2A00. As different combinations or weighting of control signals205are selected, the phase of clkout207will traverse a clkout phase range208from the phase of phn-1204to the phase of phn203. The adjustment of phases across clkout phase range208of digital phase interpolator2A00is known to have poor linearity and be limited in overall phase adjustment range (e.g., the difference between phn-1and phn). The design of digital phase interpolator2A00and similar interpolators also exhibit high power dissipation and low PSR. These performance metrics, along with chip costs (e.g., due to chip area), are degraded further as digital phase interpolator2A00is scaled to more precise phase adjustment resolutions.

FIG. 3Ais a schematic of a trigonometric phase interpolator3A00. As an option, one or more instances of trigonometric phase interpolator3A00or any aspect thereof may be implemented in the context of the architecture and functionality of the embodiments described herein. Also, trigonometric phase interpolator3A00or any aspect thereof may be implemented in any desired environment.

As shown inFIG. 3A, trigonometric phase interpolator3A00comprises a weighted current DAC302, an in-phase clock gate3041, and a quadrature-phase clock gate3042. Current DAC302is controlled to provide weighted or “steering” currents II308and IQ309to in-phase clock gate3041and quadrature-phase clock gate3042, respectively. In-phase clock gate3041receives an in-phase clock signal CKI306(and its differential complement CKIB), and quadrature-phase clock gate3042receives a quadrature-phase clock signal CKQ307(and its differential complement CKQB). The outputs of clock gates3041and3042or weighted currents II308and IQ309, respectively, are summed or mixed according to the level of clock signals CKI306and CKQ307, respectively, to provide an interpolated output clock signal OUT310(and its differential complement OUTB). When clock signals CKI306and CKQ307are sinusoidal, interpolated clock signal OUT310will be determined by:
OUT(t)=Acos(φ)sin(ωt)−Asin(φ)cos(ωt)  [EQ. 1]
where,CKI(t)=A sin(ωt),CKQ(t)=A sin(ωt−π/2)=−A cos(ωt), and0≦φ≦π/2, adjusted according to current DAC302settings.

FIG. 3Bdepicts selected waveforms3B00of trigonometric phase interpolator3A00. As shown inFIG. 3B, waveforms3B00comprises representations of signals CKI306, CKQ307, and OUT310from trigonometric phase interpolator3A00. The phase of OUT310will traverse from the phase of CKQ307to the phase of CKI306according to equation [EQ. 1] as different weighting of currents II308and IQ309is established by current DAC302to determine φ. When operating according to equation [EQ. 1], trigonometric phase interpolator3A00exhibits good high frequency performance and phase step linearity. However, generation of sinusoidal inputs and conversion of the sinusoidal output to a digital clock can be costly (e.g., chip area, design resources, etc.) to implement. Further, trigonometric phase interpolator3A00has no inherent PSR as the output stage is directly coupled to the power supply VDD311. PSR can be improved by implementing successive stages, but at the cost of additional chip area and design verification resources. As an alternative, signals CKI306and CKQ307can be digital signals rather than sinusoidal signals, with a shunt capacitor at output clock signal OUT310and its complement to provide an “integrating” type interpolator. However, while eliminating the need to source sinusoidal clock inputs, this solution can exhibit further degraded linearity, PSR, and output waveform distortion due to the saturation of input and output stages.

FIG. 4Ais a schematic of a half-wave integrating phase interpolator4A00. As an option, one or more instances of half-wave integrating phase interpolator4A00or any aspect thereof may be implemented in the context of the architecture and functionality of the embodiments described herein. Also, half-wave integrating phase interpolator4A00or any aspect thereof may be implemented in any desired environment.

As shown inFIG. 4A, half-wave integrating phase interpolator4A00comprises an in-phase controlled current source4021, a quadrature-phase controlled current source4022, an integrating capacitor CINT404, an output clock buffer406, and a reset circuit408. In-phase controlled current source4021receives an in-phase clock signal phi410and a set of in-phase current control signals daci411. Quadrature-phase controlled current source4022receives a quadrature-phase clock signal phq412and a set of quadrature-phase current control signals dacq413. In this configuration, current sources4021and4022function as current DACs, controlled by digital signals at daci411and dacq413. The number (e.g., 30) of control signals daci411and dacq413depends on the current adjustment precision required for half-wave integrating phase interpolator4A00. The currents from each current source4021and4022are summed or mixed in integrating capacitor Cint404which in turn stores the energy to support a voltage Vintset414. Voltage Vintset414drives output clock buffer406to produce an amplified and limited output pulse signal set415when Vintset414is greater than the inherent switching threshold voltage of buffer406. Reset circuit408receives an in-phase reset signal phir416and a quadrature-phase reset signal phqr417. When both reset signals phir416and phqr417are high, the voltage across integrating capacitor Cint404or voltage Vintset414is “reset” to 0 volts.

FIG. 4Bdepicts selected waveforms4B00of a half-wave integrating phase interpolator4A00. As shown inFIG. 4B, waveforms4B00comprises representations of signals phi410, phq412, phqr417, phir416, set415, and Vintset414from half-wave integrating phase interpolator4A00. Waveforms4B00also introduces a voltage Vth418, the threshold voltage of output clock buffer406. Output pulse signal set415of output clock buffer406will be in a low or high state when the input to buffer406, or Vintset414, is lower or higher than Vth418, respectively. For illustrative purposes, waveforms4B00further shows an in-phase integration voltage Vinti419and a quadrature-phase integration voltage Vintq420, representing the voltage contribution to Vintset414from in-phase controlled current source4021and quadrature-phase controlled current source4022, respectively.

The interpolation cycle of period T (e.g., equal to the data period) begins with a “pedestal” stage422during which only in-phase controlled current source4021is enabled by a low phi signal410and begins to charge capacitor Cint404and ramp voltage Vintset414. After a time of T/4, a “ramp” stage423begins and signal phq412also goes low to enable quadrature-phase controlled current source4022. During ramp stage423, both voltage Vinti419and voltage Vintq420are contributing to voltage Vintset414. When voltage Vintset414surpasses voltage Vth418, output pulse signal set415goes from low to high at a transition point tφ421. Transition point tφ421defines the phase generated by half-wave integrating phase interpolator4A00. In a final “reset” stage424of the interpolation cycle, reset signals phir416and phqr417both go high to reset voltage Vintset414across integrating capacitor Cint404to 0 volts and prepare the circuit for the next interpolation cycle. Waveforms4B00show a fixed reset stage424covering the last quarter of the cycle, but an asynchronous reset following the occurrence of transition tφ421can also be implemented.

Transition tφ421can be adjusted by adjusting the relative currents generated by current sources4021and4022, which in turn change the slopes of voltages Vinti419and Vintq420, respectively, and therefore the slope of their sum, voltage Vintset414. As the slope of Vintset414varies against a fixed Vth418, transition point tφ421will also vary. Due to the constant slope of Vintset414during ramp stage423, half-wave integrating phase interpolator4A00exhibits good phase step linearity. PSR of the core circuit of interpolator4A00is also good. However, operation of interpolator4A00as shown is not guaranteed by design, as manufacturing process variations and the like may result in voltage Vintset414not crossing threshold voltage Vth418during ramp stage423, thus rendering interpolator4A00inoperable. Further, legacy interpolator designs similar to half-wave integrating phase interpolator4A00do not incorporate frequency dependent duty cycle offset tuning.

FIG. 5presents a diagram of a dual-core half-wave integrating phase interpolator. A dual-core half-wave implementation500can be used to generate an interpolated clock with a 50% duty cycle. Implementation500comprises a first clock multiplexer5021, a second clock multiplexer5022, a first half-wave interpolation core5051, a second half-wave interpolation core5052, and an SR latch508. Clock multiplexers5021and5022each receive a set of four reference clocks (e.g., set5031and set5032) respectively, where each of the four clocks in set5031and set5032are separated in phase by π/2 radians or 90 degrees. Clock multiplexers5021and5022also each receive a set of two mux control signals, signal5041and signal5042, respectively, to select two reference clocks that will be passed through to interpolation cores5051and5052. Interpolation cores5051and5052operate as described inFIGS. 4A and 4Bto produce a set pulse506on the “set” or “S” input of SR latch508and a reset pulse507on the “reset” or “R” input of SR latch508, respectively. Through the operation of SR latch508, the timing of set pulse506and the timing of reset pulse507will produce the rising and falling edges, respectively, of a clock signal ckout510, thus allowing for control of the duty cycle of ckout510. While dual-core half-wave integrating phase interpolator500provides duty cycle control, SR latch508significantly degrades the PSR of the system.

FIG. 6is a functional diagram of a full-wave integrating phase interpolator600asused to implement various high performance phase interpolators. As an option, one or more instances of interpolator600or any aspect thereof may be implemented in the context of the architecture and functionality of the embodiments described herein. Also, interpolator600or any aspect thereof may be implemented in any desired environment.

As shown inFIG. 6, full-wave integrating phase interpolator600comprises a full-wave interpolation core601and a feedback circuit607. Full-wave interpolation core601further comprises an in-phase current source6021, a quadrature-phase current source6022, an in-phase current sink6041, a quadrature-phase current sink6042, a first in-phase current switch6031, a first quadrature-phase current switch6032, a second in-phase current switch6051, a second quadrature-phase current switch6052, and an integrating capacitor Cint606. Switches6051and6031are controlled by an in-phase clock signal ck0611, and switches6052and6032are controlled by a quadrature-phase clock signal ck90613. The switches are closed and opened according to the state of the clock signals to source and sink current into and out of integrating capacitor Cint606to produce an interpolation voltage Vintep615. Switches6051and6031can be configured to be in opposite positions (e.g., switch6051“closed” and switch6031“open”) for a given state of in-phase clock signal ck0611. Likewise, switches6052and6032can be configured to be in opposite positions (e.g., switch6052“closed” and switch6032“open”) for a given state of quadrature-phase clock signal ck90613. Current sources6021and6022, and current sinks6041and6042, are each digitally-controlled (e.g., current DACs, multiplying DACs) to provide a desired response or waveform (e.g., triangle wave) at Vintep615throughout the entire interpolation cycle. In some embodiments, feedback circuit607receives voltage Vintep615, a midpoint reference voltage Vmid—ref616, and a current bias reference voltage Vbias—ref617, to produce a feedback voltage Vctrl—fb618. Feedback circuit607allows for optimization of the dynamic voltage range of full-wave interpolation core601through control of the common mode and amplitude of the waveform at Vintep615.

FIG. 7depicts selected output waveforms700of full-wave integrating phase interpolator600. Specifically, waveforms700represent the voltage at Vintep615at various settings or weightings of current sources6021and6022and current sinks6041and6042, in some embodiments. For example, a first waveform702can represent the voltage at Vintep615when quadrature-phase current source6022and quadrature-phase current sink6042are biased and weighted such that changes in the state of quadrature-phase clock signal ck90613, and subsequently, changes in the state of switches6052and6032, have no impact on the voltage at Vintep615. First waveform702can therefore represent a pass through of the phase of in-phase clock signal ck0611. Similarly, a second waveform704can represent the voltage at Vintep615when in-phase current source6021and in-phase current sink6041are biased and weighted such that changes in the state of in-phase clock signal ck0611, and subsequently, changes in the state of switches6051and6031, have no impact on the voltage at Vintep615. Second waveform704can therefore represent a pass through of the phase of quadrature-phase clock signal ck90613. Waveforms700further shows a set of six interpolation waveforms706that represent a range of interpolation settings (e.g., biasings and weightings of current sources and sinks) between first waveform702(e.g., phase of in-phase clock ck0611) and second waveform704(e.g., phase of quadrature-phase clock ck90613). All waveforms702,704, and706exhibit constant slopes at the zero crossing in both directions which contribute to a high phase step linearity.

FIG. 8is a basic transistor-level schematic800of full-wave integrating phase interpolation core601as used to implement various high performance phase interpolators. As an option, one or more instances of elements of schematic800, or interpolation core601, or any aspect thereof may be implemented in the context of the architecture and functionality of the embodiments described herein.

As shown inFIG. 8, schematic800shows that full-wave integrating phase interpolation core601comprises an in-phase source current DAC8021, a quadrature-phase source current DAC8022, an in-phase sink current DAC8041, and a quadrature-phase sink current DAC8042. In some embodiments, current DACs8021,8022,8041, and8042, are fully segmented with unary or thermometer encoding. Current DACs8041and8042can also be called multiplying DACs. The basic functional transistors for a single representative bit slice of each current DAC8021,8022,8041, and8042are shown in schematic800for illustrative purposes. Specifically, each bit slice comprises three basic functional transistors: a first transistor acting as a switch responsive to a DAC control bit, a second transistor acting as a switch responsive to an input clock, and a third transistor acting as a bias current control responsive to a control voltage. A current source or sink will be actively sourcing or sinking current to support Vintep615when the two switch transistors are both activated (e.g., closed or conducting). More specifically, referring to schematic800, transistors M11and M12act as switches responsive to a DAC control bit and receive DAC control bit signals DAC_sel805and DAC_sel_b806, respectively. Transistors M1and M2also act as switches responsive to a DAC control bit and receive DAC control bit signals DAC_sel_b807and DAC_sel808, respectively. Transistors M9and M3act as switches responsive to an input clock and receive in-phase clock signal ck0611. Transistors M10and M4also act as switches responsive to an input clock and receive quadrature-phase clock signal ck90613. Transistors M7and M8act as bias current control responsive to a control voltage and receive current bias reference voltage Vbias—ref617. Transistors M5and M6also act as bias current control responsive to a control voltage and receive feedback voltage Vctrl—fb618.

Full-wave integrating phase interpolation core601operates within its linear region or output compliance range by controlling the supplied bias current (Ibias) and the resulting peak-to-peak amplitude of the waveform at Vintep615(Vintep-pp) according the following relationship:
Vintep-pp=(2*Ibias)/(Cint*Fck)  [EQ. 2]
where,Cint=value of Cint606, andFck=interpolator clock frequency.
The interpolator output amplitude is therefore inversely related to the interpolator clock frequency and value of the integrating capacitor. Variations in Fckand Cint606can therefore impact output amplitude which can degrade PSR and phase step linearity. To maintain an optimal amplitude over a wide range of Fck, some embodiments can deploy a switched capacitor frequency-to-current converter having an output current inversely proportional to Fckand providing the bias current Ibiasfor interpolation core601. To mitigate amplitude variations due to capacitor value variance (e.g., in Cint606), some embodiments can deploy a switched capacitor frequency-to-current converter having an output current that is dependent on the same type of capacitor as that used in the integrating capacitor of the interpolation core. Thus, full-wave integrating phase interpolation core601can exhibit good PSR and phase step linearity over a wide frequency range and process variation range.

Further, the cascode configuration of current DACs8021,8022,8041, and8042within full-wave integrating phase interpolation core601is vital to providing several high performance features to phase interpolators deploying this design. For example, complementary switching among the current DACs in the cascode configuration significantly reduces clock (e.g., ck0611and ck90613) feed-through to Vintep615. Further, the cascode configuration is characterized by a high output impedance which in turn provides a high PSR, as well as a high single-stage gain, resulting in a high-fidelity triangle waveform at Vintep615and highly linear interpolation phase steps (e.g., seeFIG. 7).

FIG. 9Ais a schematic of a single-core full-wave integrating phase interpolator9A00used to implement various high performance phase interpolators. As an option, one or more instances of elements of single-core full-wave integrating phase interpolator9A00or any aspect thereof may be implemented in the context of the architecture and functionality of the embodiments described herein.

As shown inFIG. 9A, single-core full-wave integrating phase interpolator9A00comprises a first full-wave integrating phase interpolation core9021, a first feedback circuit9041, a clock multiplexer906, and a comparator908. Interpolation core9021has the same architecture, and thus the same inherent advantages, as that of full-wave integrating phase interpolation core601shown inFIG. 6and described herein. Interpolation core9021further connects to and interacts with feedback circuit9041in the same manner as full-wave integrating phase interpolation core601and feedback circuit607shown inFIG. 6and described herein. Interpolation core9021receives a first in-phase clock ck0911and a first quadrature-phase clock ck90912to produce a first interpolation voltage waveform Vintep—p921. Clocks ck0911and ck90912are selected from a set of reference clocks910by clock multiplexer906. The waveform (e.g., triangle wave) at voltage Vintep—p921is compared to a reference voltage Vref930at comparator908to generate a differential digital interpolation clock output925with edges or transitions at the crossing points of Vintep—p921and Vref930. In some embodiments, reference voltage Vref930can be related to a set of reference voltages931received at feedback circuit9041.

Single-core full-wave integrating phase interpolator9A00described herein offers many advantages. The high PSR, linearity, and signal integrity inherent in interpolation core9021is maintained by remaining in a compliant linear or analog operating region until the final generation of clock output925by comparator908. Designing comparator908to have a high gain, a non-saturating first stage, and a good common-mode rejection, can help maintain a high PSR for the entire interpolator system. Voltage Vref930can also be adjusted to correct for clock output925duty cycle deviations due to input offset voltages of comparator908, feedback gain variations of circuit9041, mismatches in the DAC currents of core9021, and the like. Duty cycle correction is discussed further in reference toFIG. 12AandFIG. 12B.

FIG. 9Bis a schematic of a dual-core full-wave integrating phase interpolator9B00used to implement various high performance phase interpolators. As an option, one or more instances of elements of dual-core full-wave integrating phase interpolator9B00or any aspect thereof may be implemented in the context of the architecture and functionality of the embodiments described herein.

As shown inFIG. 9B, dual-core full-wave integrating phase interpolator9B00comprises the same components as single-core full-wave integrating phase interpolator9A00with additional components that comprise the second core and related support circuitry. Specifically, dual-core full-wave integrating phase interpolator9B00comprises a first full-wave integrating phase interpolation core9021, a second full-wave integrating phase interpolation core9022, a first feedback circuit9041, a second feedback circuit9042, a clock multiplexer906, and a comparator908. Interpolation cores9021and9022have the same architecture, and thus the same inherent advantages, as that of full-wave integrating phase interpolation core601shown inFIG. 6and described herein. Interpolation cores9021and9022further connect to and interact with feedback circuits9041and9042, respectively, in the same manner as full-wave integrating phase interpolation core601and feedback circuit607shown inFIG. 6and described herein. Interpolation core9021receives a first in-phase clock ck0911and a first quadrature-phase clock ck90912to produce a first interpolation voltage waveform Vintep—p921. Interpolation core9022receives a second in-phase clock ck180913and a second quadrature-phase clock ck270914to produce a second interpolation voltage waveform Vintep—n922. Clocks ck0911, ck90912, ck180913, and ck270914are selected from a set of reference clocks910by clock multiplexer906. The phase of clock ck180913is shifted by π radians or 180 degrees relative to the phase of clock ck0911. Similarly, the phase of clock ck270914is shifted by π radians or 180 degrees relative to the phase of clock ck90912. The waveforms (e.g., triangle waves) at voltages Vintep—p921and Vintep—n922will therefore also be offset such that they are largely the inverse of one another (e.g., like a differential signal), allowing comparator908to generate an accurate differential digital interpolation clock output925with edges or transitions at the crossing points of Vintep—p921and Vintep—n922. In some embodiments, a set of reference voltages931received at first feedback circuit9041can be related to a set of reference voltages932received at second feedback circuit9042.

Dual-core full-wave integrating phase interpolator9B00described herein offers many advantages. The high PSR, linearity, and signal integrity inherent in interpolation cores9021and9022is maintained by remaining in a linear or analog operating region until the final generation of clock output925by comparator908. Designing comparator908to have a high gain, a non-saturating first stage, and a good common-mode rejection, can help maintain a high PSR for the entire interpolator system. The common zero-crossing point and pseudo-differential nature of the waveforms at Vintep—p921and Vintep—n922not only improve PSR, but also increase the effective waveform slope at the phase transition or switch point, reducing sensitivity to amplitude-induced jitter in cores9021and9022.

FIG. 10exemplifies a switched capacitor feedback circuit1000for implementing high performance phase interpolators. As an option, one or more instances of switched capacitor feedback circuit1000or any aspect thereof may be implemented in the context of the architecture and functionality of the embodiments described herein. Also, switched capacitor feedback circuit1000or any aspect thereof may be implemented in any desired environment. The figure depicts a switched capacitor output voltage control circuit for the phase interpolator. In some embodiments, feedback circuit607of full-wave integrating phase interpolator600can comprise circuit1000. The following describes such embodiments.

As shown inFIG. 10, and with reference toFIG. 6, switched capacitor feedback circuit1000receives interpolation voltage Vintep615, midpoint reference voltage Vmid—ref616, and current bias reference voltage Vbias—ref617, and drives feedback voltage Vctrl—fb618. The simplified schematic of circuit1000comprises a storage capacitor set C11002, a load capacitor C21004, a first set of switches responding to a first activation pulse P11006, and a second set of switches responding to a second activation pulse P21008. Storage capacitor set C11002comprises two identical capacitors symmetric about the output node at Vctrl—fb618to optimize the performance (e.g., consistent load impedance during pulse P11006and pulse P21008) of circuit1000. One purpose of circuit1000is to sense voltages Vintep615, Vmid—ref616, and Vbias—ref617, and drive feedback voltage Vctrl—fb618such that the performance of interpolation core601is optimized through control of the common mode voltage level at Vintep615.

FIG. 11exemplifies a linear feedback circuit1100for implementing high performance phase interpolators. As an option, one or more instances of linear feedback circuit1100or any aspect thereof may be implemented in the context of the architecture and functionality of the embodiments described herein. Also, linear feedback circuit1100or any aspect thereof may be implemented in any desired environment. The figure depicts a linear output voltage control circuit for the phase interpolator. In some embodiments, feedback circuit607of full-wave integrating phase interpolator600can comprise circuit1100. The following describes such embodiments.

As shown inFIG. 11, and with reference toFIG. 6, linear feedback circuit1100receives interpolation voltage Vintep615and midpoint reference voltage Vmid—ref616, and drives feedback voltage Vctrl—fb618. The simplified schematic of circuit1100comprises an operational amplifier or op amp1102and a linear low pass RC filter1104. One purpose of circuit1100is to sense voltages Vintep615and Vmid—ref616, and drive feedback voltage Vctrl—fb618such that the performance of the interpolation core601is optimized through control of the common mode voltage level at Vintep615. Specifically, the waveform (e.g., large amplitude triangle wave) at Vintep615is transferred by RC filter1104to a DC voltage representing the common mode of the interpolation output voltage and delivered to the negative input of op amp1102. An adjustable reference voltage Vmid—ref616representing the target common-mode or crossing voltage is delivered to the positive input of op amp1102. Op amp1102is configured to compare the actual common mode voltage at the negative input to the target common mode voltage at the positive input and drive an output voltage at Vctrl—fb618within the closed loop of circuit1100and the entire interpolator system, such that the actual common-mode voltage equals the target common-mode voltage in steady state.

FIG. 12Adepicts selected waveforms12A00exhibiting duty cycle correction of dual-core full-wave integrating phase interpolator9B00. Specifically, waveforms12A00represent the voltages at Vintep—p921and Vintep—n922, and the digital output signal of interpolation clock output925, to illustrate the impact of interpolator offsets on duty cycle. For example, a first core output waveform1232can represent the voltage at Vintep—p921, a second core output with offset waveform12341can represent the voltage at Vintep—n922when a common-mode offset exists, and an output clock with offset waveform12361can represent the digital output signal of interpolation clock output925responsive to waveforms1232and12341. The common-mode offset present in waveform12341results in a shift in the zero crossing of pseudo-differential waveforms1232and12341such that waveform12361exhibits a duty cycle less than 50%. By controlling the common mode of interpolation cores9021and9022in interpolator9B00(e.g., through feedback circuits9041and9042) this duty cycle deviation can be corrected. A corrected duty cycle is illustrated in waveforms12A00with a second core output with corrected offset waveform12342representing the voltage at Vintep—n922when a common-mode offset is corrected, and an output clock with corrected offset waveform12362representing the digital output signal of interpolation clock output925responsive to waveforms1232and12342. With the common-mode offset corrected, the zero crossing of pseudo-differential waveforms1232and12342are such that waveform12362exhibits a duty cycle of 50%. Techniques for duty cycle correction and calibration are disclosed inFIG. 12Band the corresponding description as follows.

FIG. 12Bexemplifies a duty cycle calibration setup12B00for calibrating an instance of a high performance phase interpolators. As an option, one or more instances of duty cycle calibration setup12B00or any aspect thereof may be implemented in the context of the architecture and functionality of the embodiments described herein. Also, duty cycle calibration setup12B00or any aspect thereof may be implemented in any desired environment.

As shown inFIG. 12B, duty cycle calibration setup12B00comprises a high performance phase interpolator, similar to dual-core full-wave integrating phase interpolator9B00, having a first full-wave integrating phase interpolation core12021, a second full-wave integrating phase interpolation core12022, a first feedback circuit12041, a second feedback circuit12042, and a comparator1208. Setup12B00further comprises a first voltage control DAC12061controlling a voltage Vmid—ref—p1211of first feedback circuit12041, and a second voltage control DAC12062controlling a voltage Vmid—ref—n1212of second feedback circuit12041. Voltage control DACs12061and12062are used to precisely and accurately control voltages Vmid—ref—p1211and Vmid—ref—n1212, respectively, to correct for clock output duty cycle deviations due to input offset voltages of comparator1208, feedback gain variations of circuits12041and12042, mismatches in the DAC currents of cores12021and12022, and the like. In some embodiments, voltage control DACs12061and12062can be implemented as charge-redistribution DACs when feedback circuits12041and12042are of a switched capacitor type similar to that described inFIG. 10. Other controllable precision voltage sources (e.g., trimmable voltage regulators) can also be used to drive voltages Vmid—ref—p1211and Vmid—ref—n1212.

Setup12B00can be implemented within a calibration environment. Such a calibration environment might comprise instrumentation to assist in determining the voltages Vmid—ref—p1211and Vmid—ref—n1212required to achieve the target duty cycle (e.g., 50%) of the interpolator clock output or other performance attributes of the interpolator. Specifically, the setup12B00ofFIG. 12Bcomprises a first digital signal source12221connected to and controlling DAC12061, a second digital signal source12222connected to and controlling DAC12062, and a digital signal capture instrument1224connected to and sensing the state of the digital output of comparator1208. In some situations, a calibration environment can be implemented on-chip with the interpolator (e.g., within a single semiconductor package, in a multi-chip package with the interpolator, etc.) or a calibration environment can be implemented off-chip (e.g., in a testing environment).

The dual-core full-wave integrating phase interpolator in setup12B00offers several features related to duty cycle correction and calibration. Specifically, no time measurement instrumentation is required to calibrate duty cycle, optimizing test and calibration costs in terms of throughput and test equipment costs. More specifically, to determine the optimal voltages Vmid—ref—p1211and Vmid—ref—n1212, the current DACs of interpolation cores12021and12022are first enabled at half strength (e.g., the input clocks are disabled). Digital sources12221and12222are then used to control DACs12061and12062, and in turn, adjust voltages Vmid—ref—p1211and Vmid—ref—n1212, until digital capture instrument1224senses a state change at the output of comparator1208. The voltages Vmid—ref—p1211and Vmid—ref—n1212at this switch point are the best voltages to correct for any offsets in the system that may contribute to duty cycle deviations. In some test environments, a search (e.g., binary search, successive approximation search) for the optimal voltages at Vmid—ref—p1211and Vmid—ref—n1212can be completed in a few passes, requiring only a few milliseconds. Search instrumentation and search logic can also be implemented on-chip. In some embodiments, the digital settings of DACs12061and12062corresponding to the desired correction voltages Vmid—ref—p1211and Vmid—ref—n1212can be stored in on-chip memory (e.g., EPROM). Finally, in some embodiments, conventional on-chip duty cycle error detectors can also be implemented to provide continuous adjustment of voltages Vmid—ref—p1211and Vmid—ref—n1212for the dual-core full-wave integrating phase interpolator described herein.

The embodiment ofFIG. 12Bcan be implemented in a packaged semiconductor device that includes one or more phase interpolation devices. Such a device is powered by a first voltage from a positive power supply terminal, a second voltage from a negative power supply terminal. The power is supplied to an interpolation device as well as to other devices implemented in the same package (e.g., on the same or on different die). The shown interpolation device includes a first interpolation core comprising a positive in-phase cascode current source having a positive in-phase input coupled to the positive power supply terminal through a programmable positive in-phase control, and having a positive in-phase output coupled to a first common node. Also, the shown interpolation device includes a positive quadrature phase cascode current source having a positive quadrature phase input coupled to the positive power supply terminal through a programmable positive quadrature phase control, and having a positive quadrature phase output coupled to the first common node.

A 50/50 duty cycle is implemented by adding a negative in-phase cascode current source having a negative in-phase input coupled to the negative power supply terminal through a programmable negative in-phase control, and having a negative in-phase output coupled to the first common node. A negative quadrature phase cascode current source having a negative quadrature phase input is coupled to the negative power supply terminal through a programmable negative quadrature phase control. The negative quadrature phase output is coupled to the first common node.

Full-wave integrating interpolation is implemented by including a second interpolation core having a second common node (as shown) and a comparator having a plus terminal, a negative terminal, and a phase interpolation output. The plus terminal of the comparator is coupled to the first common node and negative terminal of the comparator is coupled to the second common node.

Duty cycle correction for phase interpolation device is implemented by adding a first common mode feedback circuit coupled to the first common node and a second common mode feedback circuit coupled to the second common node. The first common mode feedback circuit comprises a first common mode voltage generator; and the second common mode feedback circuit comprises a second common mode voltage generator.

Any of the foregoing design choices or features can be implemented in a semiconductor package comprising one or more die.

Finally, it should be noted that there are alternative ways of implementing the embodiments disclosed herein. Accordingly, the present embodiments are to be considered as illustrative and not restrictive, and the claims are not to be limited to the details given herein, but may be modified within the scope and equivalents thereof.

In the foregoing specification, the disclosure has been described with reference to specific embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the disclosure. For example, the above-described schematics and circuits are described with reference to a particular set of named signals and named waveforms. However, the set of named signals and waveforms may be changed without affecting the scope or operation of the disclosed techniques. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than in a restrictive sense.