Bidirectional semiconductor device and a manufacturing method thereof

A semiconductor device and a method of fabrication thereof includes a bidirectional device having a high breakdown voltage and a decreased ON voltage. An n-type extended drain region is formed in the bottom surface of each trench. A p-type offset region is formed in each split semiconductor region. First and second n-source regions are formed in the surface of the p-type offset region. This reduces the in-plane distance between the first and second n-source regions to thereby increase the density of cells. The breakdown voltage is maintained along the trenches. This increases the resistance to high voltages. Channels are formed in the sidewalls of the trenches by making the voltage across each gate electrode higher than the voltage across each of the first and second n-source electrodes. Thus, a bidirectional LMOSFET through which current flows in both directions is achieved. The LMOSFET has a high breakdown voltage and a decreased ON voltage.

BACKGROUND

A power supply device, such as a battery, needs to be controlled when the battery is charged and when the battery is discharged (i.e., electrical current is supplied to the load) to prevent overcharging and overdischarging of the battery. Therefore, bidirectional semiconductor switches that can turn ON and OFF an AC signal or AC power are necessary. A composite bidirectional device consisting of a reverse parallel combination of unidirectional semiconductor devices has been used as such a bidirectional semiconductor switch. Furthermore, it has been attempted to provide a miniaturized power supply device using a power IC consisting of a semiconductor substrate on which such a composite directional device and an IC for controlling it are integrated. In addition, a single (i.e., noncomposite) bidirectional device has been developed. In this respect, a bidirectional lateral insulated gate bipolar transistor (LIGBT) has been proposed in ISPSD (International Symposium on Power Semiconductor Devices and ICs) 1997, pp. 37-40, for example. The structure and operation of the bidirectional LIGBT are described below.

FIG. 30is a cross-sectional view of main portions of the bidirectional LIGBT. In the bidirectional LIGBT, two p+well regions504and505are formed on the surface side of an n-type semiconductor layer503, and n+emitter regions506and507are formed in the p+well regions504and505, respectively. The p+well regions504and505are formed with their surfaces exposed on the surface of the n-type semiconductor layer503, and are spaced from each other by a given or predetermined distance (drift distance) to maintain a given breakdown voltage. Furthermore, the n+emitter regions506and507are formed with their surfaces exposed on the surface of the n-type semiconductor layer503(i.e., the surfaces of the p+well regions504and505).

Insulated-gate type gate electrodes510and511consisting of polysilicon are formed over the portion located between the two n+emitter regions506and507of the p+well regions504and505via gate insulator films508and509. Furthermore, emitter electrodes512and513are formed to bridge across both the p+well region504and the n+emitter region506and across both the p+well region505and the n+emitter region507. In this configuration, the main current flowing in both directions between the emitter electrodes512and513can be controllably turned ON and OFF by controlling the voltage applied to the gate electrodes510and511.

FIG. 31is a diagram showing the output characteristics of the bidirectional LIGBT ofFIG. 30. Since the main current does not begin to flow unless the voltage exceeds the rising voltage (0.6 V) arising from the internal potential of the pn-junction, the ON voltage is high and ON loss is large at a small current region. As an improvement of the configuration ofFIG. 30, a single bidirectional MOSFET comprising a bidirectional device consisting of a MOSFET whose voltage decreases down to 0 V when the device is started to be operated is described, for example, in JP-A-11-224950, which is described below.

FIG. 32is a cross section of main portions of the related art bidirectional MOSFET. Here, a bidirectional LDMOSFET (lateral double-diffused MOSFET) is shown as an example. In the same way as the above-described example, this transistor has an SOI structure. An n-type semiconductor layer103is formed over a semiconductor substrate101with an insulator layer102formed therebetween. Two n++drain regions104and105are formed on the surface side of the n-type semiconductor layer103. A p+well region106is formed between the n++drain regions104and105. The p+well region106is formed to a depth reaching the insulator layer102, dividing the n-type semiconductor layer103into two regions. Two n++source regions107and108are formed in the p+well region106. A p++base contact region109is formed between both the n++source regions107and108. The n++drain regions104,105and the p+well region106are exposed on the surface of the n-type semiconductor layer103. The n++source regions107,108and p++base contact region109are exposed on the surface of the p+well region106. Insulated-gate type gate electrodes112and113are formed over the p+well region106with gate insulator films110and111formed therebetween. The gate electrodes112and113are connected together. Drain electrodes114and115are connected with the n++drain regions104and105, respectively. A source electrode117is connected across both the n++source region107and the p++base contact region109and across both the n++source region108and the p++base contact region109.

To turn ON the aforementioned bidirectional LDMOSFET, a voltage is applied between the gate electrode112and the source electrode117and between the gate electrode113and the source electrode117such that the gate electrodes112and113are placed at a positive potential. At this time, channels are formed immediately under the gate insulator films110and111in the p+well region106. If it is assumed that a voltage is applied between the drain electrodes114and115to place the drain electrode114at a higher potential, an electron current flows from the drain electrode114to the drain electrode115via the n++drain region104, the n-type semiconductor layer103, the channel corresponding to the gate electrode112, the n++source region107, the source electrode117, the n++source region108, the channel corresponding to the gate electrode113, the n-type semiconductor layer103, and the n++drain region105in this order. At this time, the electron current dominates the electrical current, i.e., unipolar. Since there is no junction in the current path, no offset component is produced even at low potentials. That is, the linearity becomes good even at very small currents. Where the polarity of the voltage applied between the drain electrodes114and115is reversed, the sense of the current is reversed but the operation is similar. As a result, as shown inFIG. 33, an AC current can be supplied. It also can be expected that operation of good linearity occurs even at very small currents.

On the other hand, in order to turn OFF the above-described bidirectional LDMOSFET, the gate electrodes112and113are shorted to the source electrode117. This annihilates the channels formed immediately under the gate insulator films110and111in the p+well region106. The electron current no longer flows and hence the device is turned OFF. In the OFF state, no current flows even if either positive or negative voltage is applied between the drain electrodes114and115. That is, the device takes an OFF state for AC voltage. Under this state, the breakdown voltage is equal to the breakdown voltage of a half portion of the bidirectional LDMOSFET.

The AC power can be turned ON and OFF with one chip using the bidirectional LDMOSFET. Furthermore, during conduction, the linearity of the voltage-to-current characteristics is good even at very small currents. The device can be used to turn ON and OFF a signal current. In addition, the gate electrodes112and113are connected together, and there is only one source electrode117. Therefore, only one driver circuit is necessary to supply a control signal to the gates. Consequently, the device becomes easy to control.

As mentioned previously, the main current flows through the channels without via a pn junction. Therefore, the main current is fundamentally the same as the current flowing through a resistor. The current flows at zero or higher voltage. The ON voltage is small at small currents, and thus the ON loss can be reduced. However, in the bidirectional LDMOSFET ofFIG. 32, the breakdown voltage is sustained by one MOSFET of the bidirectional LDMOSFET. Therefore, to sustain forward-reverse breakdown voltages, both MOSFETs are required to show breakdown voltage. Hence, the area occupied is doubled. This increases the area occupied between the drain regions. Furthermore, the planar structure makes it difficult to reduce the size of cells forming the bidirectional LDMOSFETs. Accordingly, it is difficult to improve the ON voltage.

Accordingly, there still remains a need for a semiconductor device with high breakdown voltage, with the reduced ON voltage without the foregoing problems and while increasing the cell density of the bidirectional device.

SUMMARY OF THE INVENTION

The present invention relates to a semiconductor device such as a power integrated circuit (power IC) having a bidirectional device and to a method of fabricating the semiconductor device.

One aspect of the present invention is a bidirectional semiconductor device, which includes a semiconductor region of a first conductivity type. A plurality of spaced trenches can extend from a surface of the semiconductor region to split the semiconductor region into first and second split semiconductor regions. First regions of the first conductivity type can be formed at least in the bottom surfaces of the trenches. That is, the first regions can be formed in the sidewalls of the trenches and/or bottom surfaces thereof. Second and third regions of a second conductivity type can be formed in the first and second split semiconductor regions, respectively, with the second and third regions contacting the sidewalls of the trenches and the first regions. Fourth regions of the first conductivity type can be formed in the first split semiconductor regions and in contact with the sidewalls of the trenches and with the second region. Fifth regions of the first conductivity type can be formed in the second split semiconductor regions and in contact with the sidewalls of the trenches and with the third regions. First control electrodes can be formed on the sidewalls of the trenches in the first split semiconductor regions and can extend from the first regions to the fourth regions with a first insulator film interposed therebetween. Second control electrodes can be formed on the sidewalls of the trenches in the second split semiconductor regions and can extend from the first regions to the fifth regions with a second insulator film interposed therebetween. First main electrodes can be formed on the fourth regions and second main electrodes can be formed on the fifth regions.

Sixth regions having a lower dopant concentration than the first regions can be formed between the first and second regions and between the first and third regions. The first and second control electrodes can be connected electrically or insulated electrically. The semiconductor regions can be formed in a semiconductor substrate of the second conductivity type. Each of the first and second split semiconductor regions can be plural in number. The first and second split semiconductor regions can be formed adjacently to each other. The trench width between adjacent split semiconductor regions of different types can be greater than the trench width between adjacent split semiconductor regions of the same type. The first and second main electrodes can be electrically connected with the second and third regions, respectively.

A conductor can be formed inside of each of the control electrodes, with the conductor reaching into the first region via an interlayer dielectric film. A seventh region of the second conductivity type can be formed in the bottom surface of each trench and in contact with the second and third regions and with the conductor.

Another aspect of the present invention is a semiconductor device that includes the bidirectional semiconductor device described above and a control circuit for controlling the bidirectional device formed on the same semiconductor substrate.

Another aspect of the present invention is a method of manufacturing the device described above. The method can comprise the following steps. A semiconductor region of a first conductivity type is formed. Thereafter, a diffusion region of a second conductivity type can be formed in the semiconductor layer. Thereafter, trenches can be formed from the surface of the diffusion region to form first and second split semiconductor regions surrounded by the trenches. First regions of the first conductivity type can be formed from the bottom surface of each trench by diffusion such that the first regions are connected with the semiconductor region. Second regions of the first conductivity type can be formed within the first split semiconductor regions from the diffusion region, and with the second regions surrounded by the trenches and contacting the sidewalls of the trenches. Similarly, third regions of the first conductivity type within the second split semiconductor region from the diffusion region, and with the third regions surrounded by the trenches and contacting the sidewalls of the trenches. First control electrodes can be formed on the sidewall of the trenches in the first split semiconductor regions such that the first control electrodes extend from the first regions to the second regions with a dielectric film interposed therebetween. Second control electrodes can be formed on the sidewalls of the trenches in the second split semiconductor regions such that the second control electrodes extend from the first regions to the third regions with a dielectric film interposed therebetween. First main electrodes can be formed on the fourth regions and second main electrodes can be formed on the fifth regions.

According to another aspect of the manufacturing method, the trenches can be formed from the surface of the semiconductor region to form the first and second split semiconductor regions surrounded by the trenches. The diffusion region of the second conductivity type can be formed in the surface of the semiconductor region to form second and third regions of the second conductivity type in the first and second split semiconductor regions, respectively, with the second and third regions in contact with the sidewalls of the trenches. The first regions of the first conductivity type can be formed from the bottom surfaces of the trenches by diffusion such that the first regions are connected with the semiconductor region. Fourth regions of the first conductivity type can be formed within the first split semiconductor regions from the second region, and surrounded by the trenches such that the fourth regions are in contact with the sidewalls of the trenches. Fifth regions of the first conductivity type can be formed within the second split semiconductor region from the third regions, and surrounded by the trenches such that the fifth regions are in contact with the sidewalls of the trenches. The first control electrodes can be formed on the sidewalls of the trenches in the first split semiconductor regions such that the first control electrodes extend from the first regions to the fourth regions with a dielectric film interposed therebetween. The second control electrodes can be formed on the sidewalls of the trenches in the second split semiconductor regions such that the second control electrodes extend from the first regions to the fifth regions with a dielectric film interposed therebetween. The first main electrodes can be formed on the fourth regions and the second main electrodes can be formed on the fifth regions.

The trenches can reach into the semiconductor region and the first regions can be formed within the semiconductor region. The first region can be connected with the diffusion region or the second and third regions. An interlayer dielectric film can be formed between the first and second control electrodes. Openings can be formed in the interlayer dielectric film such that the openings reach into the first regions, and the openings can be filled with a conductor.

Fourth or sixth regions of the second conductivity type can be formed in the bottom surfaces of the trench such that the fourth or sixth regions are adjacent to the first regions and in contact with the diffusion region or the second and third regions. Each of the first and second split semiconductor regions can be plural in number.

Each trench between the first and second split semiconductor regions is herein referred to as the first trench. The trench between the first split semiconductor regions and the trench between the second split semiconductor regions are herein referred to as the second trenches. The first trenches can be set wider than the second trenches. That is, the trenches between the first and second split semiconductor regions can be made wider than the trenches between the first split semiconductor regions and the trenches between the second split semiconductor regions.

DETAILED DESCRIPTION

The present description associates the first conductivity type with the n type, while associating the second conductivity type as the p type. These types, however, can be interchanged.

FIGS. 1A-1Cschematically illustrate a first embodiment of a semiconductor device according to the present invention. In this embodiment, a bidirectional LMOSFET (bidirectional lateral MOSFET) is taken as an example. This bidirectional LMOSFET is similar to a TLPM (trench lateral power MOSFET) in structure. An n-well region2is formed on a p-type semiconductor substrate1. Trenches3are formed in the n-well region2. Then, n-drain regions4are formed under the bottom surfaces3aof the trenches. A p-type offset region5is formed in the surface of the n-well region2.

A gate insulator film6is formed on the inner wall of each trench3. Gate electrodes7are formed over the sidewalls3bof the trenches with the gate insulator film formed therebetween. First n-source regions9and second n-source regions10are selectively formed on the surface of the p-type offset region5surrounded by the trenches3such that the n-source regions9and10are in contact with the trenches3. The first n-source regions9and the second n-source regions10are formed alternately with the intervening trenches3therebetween. The upper sides of the gate electrodes7and the inside of each trench3are filled with an interlayer dielectric film8, thus achieving planarization. The interlayer dielectric film8acan be formed over the entire surface, such as illustrated inFIGS. 2A-2C, and then contact holes can be formed therethrough. First source electrodes11and second source electrodes12are formed over the first n-source regions9and the second n-source regions10, respectively. The first source electrodes11are connected by first source interconnects13. The second source electrodes12are connected by second source interconnects14. The gate electrodes7are connected with gate pads (not shown) via gate interconnects.

The n-drain regions4formed in the bottoms of the trenches as described previously mitigates the electric field, and a high breakdown voltage of about 30 V can be secured. Furthermore, as the gate electrodes7and n-drain regions4are formed in the bottoms of the trenches3, a high breakdown voltage can be maintained along the trenches3. Consequently, the space between the first n-source regions9and second n-source regions10at their surfaces can be reduced. Hence, the cells can be miniaturized. As a result, the ON voltage can be lowered.

The use of the p-type semiconductor substrate1described above makes it possible to place the substrate1at ground potential. Consequently, a CMOS circuit (not shown) or the like can be easily formed on the substrate1. The n-type extended n-drain regions4formed in the bottoms of the trenches are formed in spaced relation to each other. The n-drain regions4also can be formed in contact with each other.

Alternatively, the configuration shown inFIGS. 2A-2Ccan be adopted.FIG. 2Ashows the configuration in which the n-well region2also functions as the n-drain region4ofFIG. 1C.FIGS. 2A and 2Bshow the configuration in which the semiconductor substrate is of the n type. InFIG. 2B, the semiconductor substrate1also functions as the n-drain regions4ofFIG. 1C. InFIG. 2C, further n-drain regions4can be added to the structure ofFIG. 2B. WhileFIG. 1Chas the gate electrodes7formed in laterally spaced relationship within each trench3, the embodiment ofFIGS. 2A-2Ccan have the gate electrodes7integrated into one.

FIG. 3is an equivalent circuit diagram of the bidirectional LMOSFET ofFIG. 1. The operation of this bidirectional LDMOSFET50is as follows. When a higher voltage is applied to a second source terminal S2than to a first source terminal S1, and a higher voltage is applied to a gate terminal G than to the second source terminal S2, a channel is formed in the side surface of the p-type offset region5surrounded by the first n-source region9, the second n-source region10, and the n-drain regions4ofFIG. 1. Here, the electrical current flows from the second source terminal S2to the first source terminal S1. When a higher voltage is applied to the first source terminal S1than to the second source terminal S2, and a higher voltage is applied to the gate terminal G than to the first source terminal S1, a channel is formed in the side surface of the p-type offset region5surrounded by the first n-source region9, the second n-source region10, and the n-drain region4. Here, the electrical current flows from the first source terminal S1to the second source terminal S2. In this way, electrical currents can be made to flow in two directions. Thus, a bidirectional LMOSFET is accomplished.

On the other hand, the electrical current of the bidirectional LMOSFET can be cut off by setting the potential at the gate terminal G equal to the potential at the lower potential side of the first and second source terminals S1and S2or placing the gate terminal G at ground potential to annihilate the channel formed in the p-type offset region5.

FIGS. 4A-4Bschematic illustrate a second embodiment of a semiconductor device according to the present invention. The differences between the first and second embodiments are that in the second embodiment the p-contact regions15and16surrounded by first and second n-source regions9and10, respectively, are formed in the surface of the p-type offset region5, and that the p-contact regions15and16are formed over the first n-source region9and the second n-source region10, respectively. The operation is the same as already described in connection withFIG. 3.

In the second embodiment, the potential at the p-type offset region5is stabilized by forming the p-contact regions15and16. Also, the safely operating region of the bidirectional LMOSFET is widened. With respect to this bidirectional LMOSFET, parasitic diodes are incorporated by forming the p-contact regions15and16. An operation mode in which the device acts as a bidirectional IGBT is also present. Therefore, even where the gate voltage (a voltage at the gate electrodes7) is lower than the voltage at the source electrodes at the higher potential side, a main current can be made to flow between the first source electrode11and the second source electrode12. The second embodiment is the same as the first embodiment in the other respects.

FIGS. 5A-5Cschematically illustrate a third embodiment of a semiconductor device according to the present invention. In this embodiment, a bidirectional LMOSFET is taken as an example. An n-well region2is formed on a p-type semiconductor substrate1. Trenches33are formed in the n-well region2. Then, n-source regions34are formed under the bottom surfaces33aof the trenches. A p-type offset region35is formed in the surface of the n-well region2.

A gate insulator film36is formed on the inner wall of each trench33. Gate electrodes37are formed over the sidewalls33bof the trenches with the gate insulator film36formed therebetween. First n-drain regions39and second n-drain regions40are formed in the surfaces of the p-type offset region35surrounded by the trenches33such that the regions39and40are in contact with the trenches33. The first n-drain regions39and the second n-drain regions40are formed alternately with the intervening trenches33therebetween. The upper sides of the gate electrodes37and the inside of each trench33are filled with an interlayer dielectric film38, thus achieving planarization. Contact holes are formed in the interlayer dielectric film38. First drain electrodes41and second drain electrodes42are formed on the first n-drain regions39and the second n-drain regions40, respectively. The surfaces of the n-source regions34are exposed. Pick-up electrodes45are loaded. Where the n-source region is split into plural parts, the pick-up electrodes45act to produce an equipotential state. Furthermore, a given potential can be obtained by applying a control voltage. For example, when the device is OFF, the electrical current between drain terminals D1and D2can be cut off by applying ground potential. The first drain electrodes41are connected by a first drain interconnect43. The second drain electrodes42are connected by a second drain interconnect44. The gate electrodes37are connected with gate pads (not shown) via gate interconnects.

The n-source regions34are formed in the bottoms of the trenches and coated with the interlayer dielectric film38. This mitigates the electric field. A high breakdown voltage of about 30 V can be secured. Furthermore, as mentioned previously, the gate electrodes37and the p-type offset regions35are formed in the trenches. Thus, high breakdown voltage is maintained along the sidewalls33bof the trenches. Consequently, the space between the first n-drain regions39and the second n-drain regions40at their surfaces can be reduced. Hence, the cells can be miniaturized. As a result, the ON voltage can be lowered.

The use of the p-type semiconductor substrate1as described above makes it possible to place the substrate1at ground potential. Consequently, a CMOS circuit (not shown) or the like can be easily formed on the substrate1. Although the n-source regions34formed in the bottoms of the trenches are formed in spaced relation to each other, they can be formed in contact with each other.

FIG. 6is an equivalent circuit diagram of the bidirectional LMOSFET ofFIGS. 5A-5C. The operation of this bidirectional LMOSFET60is as follows. When a higher voltage is applied to a second drain terminal D2than to a first drain terminal D1, and a higher voltage is applied to a gate terminal G than to the first drain terminal D1, a channel is formed in the side surface of the p-type offset region35surrounded by the first n-drain region39, the second n-drain region40, and the n-source regions34shown inFIGS. 5A-5C. In this state, the electrical current flows from the second drain terminal D2to the first drain terminal D1. When a higher voltage is applied to the first drain terminal D1than to the second drain terminal D2, and a higher voltage is applied to the gate terminal G than to the second drain terminal D2, a channel is formed in the side surface of the p-type offset region35surrounded by the first n-drain region39, the second n-drain region40, and the n-source region34. In this state, the electrical current flows from the first drain terminal D1to the second drain terminal D2. Thus, a bidirectional LMOSFET is accomplished. The bidirectional LMOSFET can be cut off by setting the potential at the gate terminal G equal to the potential at the lower potential side of the first and second drain terminals D1and D2to annihilate the channel formed in the p-type offset region35.

FIGS. 7A-7Cschematically illustrate a fourth embodiment of a semiconductor device according to the present invention. In this embodiment, a bidirectional LMOSFET is taken as an example. The differences between the third and fourth embodiments are that in the fourth embodiment p-base pick-up regions46are formed adjacent to n-source regions34located under the bottom surfaces33aof the trenches and that the pick-up electrodes45are formed in contact with the n-source regions34and the p-base pick-up regions46. In this way, the p-base pick-up regions46are formed. The p-base pick-up regions46and the n-source regions34are shorted by the pick-up electrodes45. This stabilizes the potential at the p-type offset regions35and widens the safely operating region of the bidirectional LMOSFET. The fourth embodiment is the same with the third embodiment in the other respects.

FIG. 8is a layout diagram of main portions of another embodiment of a semiconductor device according to the present invention. Here, a power1C installed in a battery system is taken as an example. This power1C includes a semiconductor substrate91to which a bidirectional LMOSFET50according to the present invention, a drive-and-protect circuit portion51, and a residual amount circuit portion52are formed. The drive-and-protect circuit portion51and residual amount circuit portion52detect the voltage of battery cells92, a charging current flowing into the battery cells92from a charger (not shown), and a discharging current flowing out into a load (such as a mobile device) from the battery cells92by a resistor93, control the bidirectional LMOSFET50to be in a normal state, and transmit a signal for turning OFF the bidirectional LMOSFET50to the LMOFET50in an abnormal case, such as overcharging or overdischarging. The drive-and-protect circuit portion51incorporates a charge pump circuit53and can apply a voltage higher than the voltages at the first and second source terminals S1and S2of the bidirectional LMOSFET50to the gate terminal G. A control terminal is used to specify the amount of charge remaining in the battery cells92from outside.

FIGS. 9A-9Cschematically illustrate cross section of main portions of a semiconductor device ofFIGS. 1A-1Cto illustrate a sequence of method steps of fabricating or manufacturing the device according to the present invention. Here, an n-well region2can be formed on a p-type semiconductor substrate1, and a p-type offset region5having a surface concentration of 1×1017cm−3and a diffusion depth of 1 μm can be formed thereafter. Using an oxide film as a mask, trenches3having a width of 1.5 μm are formed in the n-well region2. Then, n-drain regions4having a surface concentration of 1×1018cm−3and a diffusion depth of 1 μm are formed in the bottom surfaces3aof the trenches3from the windows of the trenches3by ion implantation and thermal treatment (thermal drive step). SeeFIG. 9A. The trenches3can be formed after or before forming the well region2and p-type offset region5.

Referring toFIG. 9A, ions (not shown) for adjusting the threshold value can be implanted at a tilt angle of 45 degrees into a channel formation location in the sidewall3bof each trench to form a diffusion layer having a surface concentration of 7×1016cm−3and a diffusion depth of 0.3 μm. Then, the channel formation location can be cleaned. Thereafter, a gate insulator film6(such as gate oxide film) can be formed on the inner wall of each trench. Doped polysilicon is deposited to a thickness of 0.3 μm on the gate insulator film6to form the gate electrodes7, which can be formed by anisotropic etching.

Referring to FIG.,9C, a first n-source region9and a second n-source region10can be formed on the surface of the p-type offset region5. An oxide film can be deposited as an interlayer dielectric film8to fill each trench therewith. The surface of the interlayer dielectric film8can then be planarized by etchback. Subsequently, ions can be implanted into the first and the second n-source regions9,10to reduce the contact resistance. A first source electrode11and a second source electrode12can be formed thereafter, from aluminum or other material, on the first and the second n-source regions9and10, respectively. Then, first and second source interconnects (not shown) can be formed.

FIGS. 10A-10Cschematically illustrate cross-sections of the main portions of a semiconductor device ofFIGS. 4A-4Bto illustrate a sequence of method steps of fabricating or manufacturing the device according to the present invention. The method here is only different from the method explained withFIGS. 9A-9Cin that p-contact regions15and16are also formed (seeFIG. 10C), and that the first and second source electrodes11and12, respectively, are in contact with the p-contact regions15and16, respectively.

FIGS. 11A-11Cschematically illustrate cross sections of the main portions of a semiconductor device ofFIGS. 5A-5Cto illustrate a sequence of method steps of fabricating or manufacturing the device according to the present invention. Here, an n-well region2can be formed on a p-type semiconductor substrate1. Using an oxide film (not shown) as a mask, trenches33having a width of 3 μm can be formed in the n-well region2. Then, n-source regions34having a surface concentration of 1×1018cm−3and a diffusion depth of 1 μm can be formed in the bottom surfaces33aof the trenches from the windows of the trenches33by ion implantation and thermal treatment (thermal drive step). Then, the mask of oxide film is removed. Subsequently, p-type offset regions35having a surface concentration of 1×1017cm−3and a diffusion depth of 1 μm can be formed in the portions of the semiconductor regions61split by the trenches33such that the offset regions35are in contact with the n-drain regions34. SeeFIG. 11A.

Referring toFIG. 11B, ions (not shown) for adjusting the threshold value can be implanted at a tilt angle of 45 degrees into a channel formation location in the sidewall33bof each trench to form a diffusion layer having a surface concentration of 7×1016cm−3and a diffusion depth of 0.3 μm. Then, the channel formation location can be cleaned. Thereafter, a gate insulator film36can be formed on the inner wall of each trench. Doped polysilicon can be deposited to a thickness of 0.3 μm on the gate insulator film36to form gate electrodes37, which can be formed by anisotropic etching.

Referring toFIG. 11C, a first n-drain region39and a second n-drain region40can be formed on the surface of each p-type offset region35. An oxide film can be deposited as an interlayer dielectric film38. The wide inside of each trench, however, is not filled with the interlayer dielectric film38by this step. The interlayer dielectric film38in the bottoms of the trenches33can be etched away by etchback to expose the surfaces of the n-source regions34. Subsequently, a barrier metal (not shown) can be deposited onto the bottom surface of each trench33. Specifically, pick-up electrodes45made of tungsten can be buried, and planarized. Then, ions can be implanted into the first and second drain regions39,40to reduce the contact resistance. First and second drain electrodes41and42, respectively, then can be formed from aluminum on the first and second n-drain regions39,40. At the same time, an aluminum film can be formed on the pick-up electrodes45. Subsequently, first and second drain interconnects (not shown) can be formed.

FIGS. 12A-12Cschematically illustrate cross sections of the main portions of a semiconductor device according toFIGS. 7A-7Cto illustrate a sequence of method steps of fabricating the device according to the present invention. The differences with the method sequence illustrated inFIGS. 11A-11Care that p-base pick-up regions46are formed in the bottoms of the trenches inFIG. 12Aand that pick-up electrodes45and the p-base pick-up regions46are in contact with each other inFIG. 12C.

FIGS. 13A-13Cschematically illustrate cross-sections of the main portions ofFIGS. 1A-1Cand CMOSes formed on the same semiconductor substrate to illustrate a method of fabricating a semiconductor device according to the present invention. The CMOSes are fundamental devices for forming the drive-and-protect circuit and residual amount circuit ofFIGS. 7A-7C.

Referring toFIG. 13A, an n-well region72can be formed on a p-type semiconductor substrate71. Using an oxide film (not shown) as a mask, trenches73having a width of 1.5 μm can be formed in the n-well region72. P-well regions76also can be formed. Then, n-drain regions74having a surface concentration of 1×1017cm−3and a diffusion depth of 1 μm can be formed in the bottom surfaces73aof the trenches73from the windows of the trenches73by ion implantation and thermal treatment (thermal drive step). Then, the mask of oxide film can be removed, and p-type offset regions75having a surface concentration of 1×1017cm−3and a diffusion depth of 1 μm can be formed.

Referring toFIG. 13B, device isolation on the surface can be provided by a LOCOS technique. Then, ions (not shown) for adjusting the threshold value can be implanted at a tilt angle of 45 degrees into channel formation locations in the CMOS portion and in the trench sidewalls73bto form a diffusion layer having a surface concentration of 7×1016cm−3and a diffusion depth of 0.3 μm. Then, the channel formation locations can be cleaned. A gate insulator film79can be formed on the inner wall of each trench. Doped polysilicon is deposited to a thickness of 0.3 μm on the gate insulator film79to form gate electrodes80, which can be formed in the CMOS portion and in the trenches by anisotropic etching.

Referring toFIG. 13C, a first n-source region81and a second n-source region82can be formed on the surface of each p-type offset region75. Source/drain regions83and84can be formed in the CMOS portion. An oxide film can be deposited as an interlayer dielectric film87to fill each trench therewith. Subsequently, the surface of the interlayer dielectric film87can be planarized by etchback. Contact holes can be formed in the interlayer dielectric film87. Plug ions can be implanted into the openings to reduce the contact resistance. First and second source electrodes85and86, respectively, can be formed from aluminum on the first and second n-source regions81and82, respectively. Source/drain electrodes88and89can be formed on the source/drain regions83and84, respectively, of the CMOS portion.

A semiconductor device of another embodiment of the invention that is different from the semiconductor device of the invention described thus far and includes even a gate interconnect structure will now be described. Gate interconnects and source electrodes can be fabricated from metal film at the same time. What are placed immediately over source regions and connected via contact holes are herein taken as source electrodes, whereas the other locations are taken as gate interconnects.

FIGS. 14 to 17schematically illustrate main portions including the gate interconnect structure according to a semiconductor device according to the present invention. The hidden portions are indicated by the dotted lines. An interlayer dielectric film208ais omitted inFIG. 14.

Only the differences between the embodiments ofFIGS. 1A-1CandFIGS. 14-17will be described. InFIGS. 1A-1C, a single first n-source region9and a single second n-source region10are alternately arranged. In the present embodiment, plural first n-source regions209are formed adjacently and plural second n-source regions210are formed adjacently. Moreover, the p-type offset regions205are not in contact with the n-drain regions204. In the same way as inFIGS. 4A and 4B, p-contact regions215and216are formed in each source region. The gate interconnect structure is shown here, although not shown inFIGS. 1A-1C.

Where the p-type offset regions205are not in contact with the n-drain regions204, the breakdown voltage can be made higher than in the case where the regions205are in contact with the regions204. The ON resistance can be lowered. However, higher accuracy is required during manufacturing because the width of the p-type offset (the width of the space between the n-well region202and source region209) is small.

As shown inFIGS. 14 to 17, a first source electrode211and a first source interconnect213connected with the first source electrode211can be formed simultaneously from a metal film. The first source electrode211is connected with the first n-source regions209via contact holes217formed in an interlayer dielectric film208a. Similarly, second source electrodes212and a second source interconnect214connected with the second source electrodes212can be formed from a metal film at the same time. The second source electrodes212are connected with the second n-source regions210via contact holes217formed in the interlayer dielectric film208a. The spaces between the adjacent first n-source regions209and between the second n-source regions210are filled with gate electrodes207formed with a gate insulator film206interposed therebetween. The first n-source regions209and the second n-source regions210are located opposite each other with the interlayer dielectric film208interposed between them. The current capacity can be increased by enlarging the outer periphery203aof each trench and arranging the first n-source regions209and the second n-source regions210in large quantities alternately.

Polysilicon forming the gate electrode207forms elongated trenches203bprotruding like capes from the outer periphery203aof each trench in which the n-source regions209and210are formed. A polysilicon interconnect218is formed via the gate insulator film206formed on the inner wall of each trench203b. The polysilicon interconnect218is also formed on the gate insulator film206formed on a p-type semiconductor substrate201. The polysilicon interconnect218and a gate interconnect219of a metal film are connected via contact holes217formed in the interlayer dielectric film208a.

In this way, in the semiconductor device according to the invention, all portions of the gate electrode207can be connected by the polysilicon (gate electrode207) deposited on the entire region of the sidewalls of the outer peripheries203aof the trenches so that the gate electrode207is singular. A semiconductor device that uses only one gate electrode in this way and to which the present invention is applied is shown inFIG. 8.

FIGS. 18A-18Cschematically illustrate the bidirectional LMOSFET and drive-and-protect circuit portion ofFIG. 8. These figures illustrate the conditions of the circuits during when battery cells are overcharging.

InFIG. 18A, when a mobile device (not shown), i.e., a load, is connected with the battery cells92ofFIG. 8and being charged, an ON signal is applied to the gate terminal G to turn ON right and left n-channel MOSFETs. A charging current I1flows into the battery cells92from right to left via the bidirectional LMOSFET50. At this time, a discharging current I2is supplied to the load from the battery cells92. That is, cells92are being discharged while being charged.

InFIG. 18B, when the battery cells92are overcharged, an OFF signal is applied to the gate terminal G to turn OFF the right and left n-channel MOSFETs. Under this condition, the load and battery cells92are isolated in terms of electric circuit. The charging current I1no longer flows into the battery cells92to stop overcharging. At the same time, the discharging current I2is not supplied from the battery cells92into the load. During this overcharging period, if the plug of the battery charger ofFIG. 8is removed, no current is supplied to the load at all. Consequently, the load is made inoperative.

To avoid this, as shown inFIG. 18C, an ON signal is again supplied to the gate terminal G to turn on the bidirectional LMOSFET50, thus supplying the discharging current I2from the battery cells92to the load. However, since an ON signal is delivered from the drive-and-protect circuit51after detecting that the voltage of the battery cells92has reached a normal voltage, a time delay occurs. During this time, no current is supplied from the battery cells92to the load. That is, an instantaneous break takes place.

To solve this problem, a bidirectional LMOSFET in which each of the right and left n-channel MOSFETs is provided with a gate electrode can be used.FIG. 19schematically illustrates an equivalent circuit diagram of the bidirectional LMOSFET having the two gate electrodes. This circuit is similar toFIG. 6. The differences with the configuration ofFIG. 6are as follows. The embodiment ofFIG. 19has two separate gate electrodes, each with a first gate terminal G1or a second gate terminal G2. Their respective n-channel MOSFETs331and332can be operated separately. Parasitic diodes333and334in the n-channel MOSFETs are used for operation. An operation mode using the bidirectional LMOSFET300having the two gate electrodes follows next.

FIGS. 20A-20Cschematically illustrate the circuit corresponding toFIGS. 18A-18C, showing the conditions of the circuit during when battery cells are overcharging. InFIG. 20A, an ON signal is supplied to the first and second gate terminals G1, G2from the drive-and-protect circuit51to turn ON the right and left n-channel MOSFETs331and332. The charging current I1flows into the battery cells92. At this time, the discharging current I2is being supplied from the battery cells92to the load. That is, the cells92are being discharged while being charged.

InFIG. 20B, when the battery cells92are overcharged, an OFF signal is supplied to the first gate terminal G1to cut off the charging current I1. At this time, the ON signal is kept supplied to the second gate terminal G2. As such, if the charging current I1is cut off, the discharging current I2flows into the load through the parasitic diodes333and n-channel MOSFET332. Hence, the aforementioned instantaneous break does not take place.

InFIG. 20C, when the battery cells92return to the normal voltage, an ON signal is again supplied to the first gate terminal G1to turn ON the left n-channel MOSFET331. Under this state, the discharging current I2is supplied to the load via the right and left n-channel MOSFETs331,332. Thus, normal operation is resumed. The electrical current to the load is supplied without interruption by using the bidirectional LMOSFET300having the two gate electrodes in this way.

The configuration of a semiconductor device having two gate electrodes follows next.FIGS. 21-25schematically illustrate cross sections of the main portions of another embodiment of a semiconductor device according to the present invention. The hidden portions are indicated by the dotted lines. InFIG. 21, the interlayer dielectric film308ais omitted. There are plural islands341and342within each trench, the islands being pillar-like remaining portions of the trench. In this diagram, there are6islands (device cells)341acting as MOSFETs. Regions309and310are formed on the islands341. There are two islands342forming gate interconnects. In each island341, a p-type offset region305, n-source regions309,310, and source electrodes311,312are formed.

The differences with the configuration ofFIGS. 14-17are as follows. First gate electrode307aand second gate electrode307beach having a gate electrode surrounded by the interlayer dielectric film308are independent of each other. The gate electrodes307aand307bare isolated from polysilicon307on the sidewalls of the outer peripheries303aof the trenches. Their gate electrodes307aand307bare connected with first gate interconnect319and second gate interconnect320of a metal via polysilicon interconnects318.

The polysilicon307deposited on the outer periphery303aof each trench is isolated from the first gate electrode307aand the second gate electrode307bby the interlayer dielectric film308in this way. Therefore, the space W1between the island341forming the first n-source region309and the island341forming the second n-source region310is set large enough that the space is not plugged up by the polysilicon for forming the gate electrodes. On the other hand, the space Wg1between the islands341forming the first and second n-source regions309and310, respectively, is set small enough that the space is completely plugged up by the polysilicon forming the gate electrodes. The space Wg2between the island342forming the polysilicon interconnects318for connecting the gate electrodes307aand307bwith the metal gate interconnects319and320and the island341forming the n-source regions309and310is set equal to the space Wg1such that the space Wg2is plugged up by the polysilicon.

For example, where the thickness of the polysilicon forming the gate electrodes is set to 0.3 μm, the space W1is set approximately equal to 1 μm. The spaces Wg1and Wg2are set approximately equal to 0.5 μm. To planarize the surface, it is desired to set the space W1equal to or less than the width of the island341forming the source region.

The advantages already described in connection withFIGS. 20A-20Care obtained by forming the independent first gate electrode307aand second gate electrode307bin this way.

FIGS. 26A-29Cschematically illustrate cross sections of the main portions of a semiconductor device ofFIGS. 22-24to illustrate the sequence of method steps of fabricating the device according to the present invention.FIGS. 26A,27A,28A, and29A are cross-sectional views of portions corresponding toFIG. 22.FIGS. 26B,27B,28B, and29B are cross-sectional views of portions corresponding toFIG. 23.FIGS. 26C,27C,28C, and29C are cross-sectional views of portions corresponding toFIG. 24.

InFIGS. 26A-26C, an n-well region302having a surface concentration of 5×1016cm−3and a depth of about 4 μm, for example, can be formed on the surface of a p-type semiconductor substrate301. Trenches303reaching into the n-well region302can be formed from the surface to a depth of about 2 μm like meshes. Pillar-like islands (remaining trench portions)341and342can be formed. The islands341can form first and second p-type offset regions and first and second n-source regions in a later process step. The islands342can form polysilicon interconnects318that connect the first and second gate electrodes and the first and second gate interconnects in a later process step.

The space Wg1between the islands341and the space Wg2between the islands341and342can be equally set to about 0.5 μm. As a result, the polysilicon is not separated by etchback (patterning of the polysilicon) of the polysilicon. The spaces are plugged up with the polysilicon. The space W1of the islands341and342to the sidewalls of the outer peripheries303aof the trenches and the space W1between the islands341forming the first and second source regions309,310can be set equal to or greater than 1 μm. Thus, the polysilicon can be completely separated by etchback of the polysilicon.

InFIGS. 27A-27C, a gate insulator film306is formed. N-drain regions304having a high concentration of more than 1×1017cm−3or more are formed in the n-well region302in the bottoms of the trenches to give a breakdown voltage of about 30 V to 50 V. A p-type offset region305can be formed remotely from the n-drain regions304. In some cases, the offset region305can be connected. Then, polysilicon, which forms first, second gate electrodes307a,307b, and polysilicon interconnect318, is deposited to a thickness of about 0.3 μm over the entire surface. The spaces between the islands341and the spaces between the islands341and342are completely plugged up with the polysilicon. Then, patterning is done.

InFIGS. 28A-28C, first and second n-source regions309and310having a high concentration of more than 1×1020cm−3or more can be formed, using the first and second gate electrodes307aand307bas a mask. Heavily doped p-contact regions316extending through the first and second source regions309and310into the p-type offset regions305can be formed. An interlayer dielectric film308acan be formed on the surface.

InFIGS. 29A-29C, contact holes317can be formed in the interlayer dielectric film308a. First and second source electrodes311,312of a metal, first and second source interconnects313,314formed simultaneously with the first and second source electrodes311,312, and first and second gate interconnects319,320of a metal can be formed. Through the contact holes317, the first and second source electrodes311,312can be connected with first and second n-source regions309,310and with p-contact regions315,316, and the first and second gate interconnects319,320can be connected with polysilicon interconnects318formed simultaneously with the first and second gate electrodes307aand307b.

Where the thickness of the polysilicon of the gate electrodes and other components is set to about 0.3 μm, the space W1is preferably set equal to or greater than 1 μm. To planarize the surface, the space W1is preferably set to below the width of the islands. Furthermore, the spaces Wg1and Wg2can be preferably equally set to below 0.5 μm.

According to the present invention, the trenches can be formed in a semiconductor substrate and gate electrodes can be formed on the sidewalls of the trenches. A drain region can be formed under the bottom surface of each trench. A dielectric film can be formed over the drain region. First and second source regions can be formed in the semiconductor region surrounded by the trenches. As a result, the breakdown voltage of the bidirectional device can be increased, and the ON voltage can be reduced. The safely operating region of the bidirectional device can be made wider. Additionally, the breakdown voltage of the bidirectional device can be increased and the ON voltage can be reduced by forming trenches in a semiconductor substrate, forming gate electrodes on the sidewalls of the trenches, forming floating source/drain regions under the bottom surfaces of the trenches, forming a dielectric film over the source regions, and forming first and second drain/source regions in the semiconductor regions surrounded by the trenches. Moreover, the safely operating region of the bidirectional device can be made wider by forming source/drain regions and base pick-up regions under the bottom surfaces of the trenches and forming metal electrodes over them.

Given the disclosure of the present invention, one versed in the art would appreciate that there may be other embodiments and modifications within the scope and spirit of the present invention. Accordingly, all modifications and equivalents attainable by one versed in the art from the present disclosure within the scope and spirit of the present invention are to be included as further embodiments of the present invention. The scope of the present invention accordingly is to be defined as set forth in the appended claims.

The disclosures of the priority applications, JP 2004-038698 and 2003-038602, in their entirety, including the drawings, claims, and the specifications thereof, are incorporated herein by reference.