Method for manufacturing a semiconductor storage device including a division film

In a method for manufacturing a memory, a first stacked body is formed by stacking a first insulating film and a first sacrificial film. A first columnar body including a first semiconductor portion extending in the first stacked body in the first direction and a charge trapping film provided on an outer peripheral surface of the first semiconductor portion is formed. A second columnar body provided in a second direction of the first columnar body and including a second semiconductor portion stretching in the first stacked body in the first direction and a charge trapping film on an outer peripheral surface of the second semiconductor portion is formed. A second insulating film is formed above the first stacked body. A third columnar body including a third semiconductor portion provided on both the first columnar body and the second columnar body and stretching in the second insulating film in the first direction and a first gate insulating film provided on an outer peripheral surface of the third semiconductor portion is formed. A first division insulating film extending in the first direction and a third direction intersecting the first direction and the second direction and dividing the third semiconductor portion of the third columnar body in the second direction is formed.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2021-036506, filed Mar. 8, 2021, the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to a semiconductor storage device and a method for manufacturing the same.

BACKGROUND

A semiconductor storage device, such as a NAND flash memory, may have a three-dimensional memory cell array in which a plurality of memory cell arrays are arranged three-dimensionally. Select gates are provided in such a three-dimensional memory cell array to select memory strings. However, a memory cell below a slit that divides the select gates is useless because the memory cell cannot store data.

DETAILED DESCRIPTION

At least one embodiment provides a semiconductor storage device and a method for manufacturing the semiconductor storage device capable of reducing waste of a memory cell array and further miniaturizing the memory cell array.

In general, according to at least one embodiment, a method for manufacturing a semiconductor storage device includes: forming a first stacked body by alternately stacking a first insulating film and a first sacrificial film in a first direction. The method includes forming a first columnar body including a first semiconductor portion stretching in the first direction in the first stacked body and a charge trapping film provided on an outer peripheral surface of the first semiconductor portion. The method includes forming a second columnar body provided in a second direction intersecting the first direction of the first columnar body and including a second semiconductor portion stretching in the first stacked body in the first direction and a charge trapping film on an outer peripheral surface of the second semiconductor portion. The method includes forming a second insulating film above the first stacked body. The method includes forming a third columnar body including a third semiconductor portion provided on both the first columnar body and the second columnar body and stretching in the second insulating film in the first direction and a first gate insulating film provided on an outer peripheral surface of the third semiconductor portion. The method includes forming a first division insulating film extending in the first direction and a third direction intersecting the first direction and the second direction and dividing the third semiconductor portion of the third columnar body in the second direction.

Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. The embodiments are not limited to the present disclosure. In the following embodiments, a vertical direction of a semiconductor substrate indicates a relative direction when a surface on which a semiconductor element is provided is set to face up, and thus, the direction may be different from the vertical direction according to the gravitational acceleration. The drawings are schematic or conceptual, and thus, the ratio of each portion is not always the same as the actual one. In the specification and the drawings, the same components as those described above with respect to the existing drawings are denoted by the same reference numerals, and detailed description thereof will be omitted as appropriate.

First Embodiment

FIG.1Ais a schematic perspective view illustrating a configuration example of a semiconductor storage device100aaccording to a first embodiment.FIG.1Bis a schematic plan view illustrating a configuration example of a second stacked body2. The semiconductor storage device100aaccording to the embodiment is a non-volatile memory having a memory cell having a three-dimensional structure. A stacking direction of the second stacked body2is set as a Z direction, a direction intersecting the Z direction, for example, one orthogonal direction is set as a Y direction, and a direction orthogonal to the Z direction and the Y direction is set as an X direction.

As illustrated inFIG.1A, the semiconductor storage device100aincludes a wiring structure provided above a first stacked body1, a second stacked body2, a third stacked body3, a base portion4, and a second stacked body2. The wiring structure includes, for example, contacts VY and CH and a plurality of bit lines BL.

The first stacked body1includes a first insulating film11and a first conductive film12which are provided above the base portion4and are alternately stacked along the Z direction. For example, an insulator such as silicon oxide (SiO2) is used for the first insulating film11. For example, a conductive metal such as tungsten (W) is used for the first conductive film12. The first insulating film11insulates the first conductive films12adjacent to the top and bottom in the Z direction. The number of layers of the first insulating film11and the first conductive film12may be any number. An insulating film4gis provided between the first stacked body1and a base semiconductor portion43.

Although not illustrated inFIG.1A, a columnar body CL1is provided in the first stacked body1to stretch in the Z direction. A memory cell MC is provided corresponding to the intersection of the columnar body CL1and the first conductive film12.

The second stacked body2is provided above the first stacked body1. The third stacked body3is provided between the first stacked body1and the second stacked body2. A columnar body CL2penetrates the second stacked body2and is provided with a drain-side select gate SGDO. Although not illustrated inFIG.1A, a columnar body CL3penetrates the third stacked body3and is provided with a drain-side select gate SGD. The two columnar bodies CL2and CL3are provided corresponding to each columnar body CL1and are continuous on the corresponding columnar body CL1. Therefore, the columnar body CL3is connected on the first columnar body CL1, and the columnar body CL2is connected on the columnar body CL3. The drain-side select gates SGDO and SGD are configured so that the corresponding columnar body CL1(memory string) can be selectively connected to the bit line BL. More detailed configurations of the second and third stacked bodies2and3and the drain-side select gates SGDO and SGD will be described later.

The base portion4is provided below the first stacked body1and includes a substrate40, a base insulating film41, a base conductive film42, and a base semiconductor portion43. The substrate40has a first surface and a second surface that are substantially perpendicular to the Z direction, which is the stacking direction. The base insulating film41is provided on the first surface of the substrate40. The base conductive film42is provided on the base insulating film41. The base semiconductor portion43is provided on the base conductive film42. The substrate40is configured with a semiconductor substrate, and may be, for example, a p-type silicon substrate. For example, an element division region40iis provided on the surface region of the substrate40. The element division region40iis, for example, an insulating region containing silicon oxide, and an active area aa is partitioned on the surface region of the substrate40. The source and drain regions of a transistor Tr are provided in the active area aa. The transistor Tr configures a peripheral circuit of the non-volatile memory. The base insulating film41contains, for example, a silicon oxide and insulates the transistor Tr. A wiring41ais provided in the base insulating film41. The wiring41ais a wiring electrically connected to the transistor Tr. For example, a conductive metal such as tungsten is used for the base conductive film42. For example, a semiconductor material such as n-type silicon is used for the base semiconductor portion43. Undoped silicon may be used for a portion of the base semiconductor portion43. The base conductive film42and the base semiconductor portion43integrally function as a common source line BSL of the memory cell array.

Some conductive films14of the first stacked body1close to the base portion4are used for the source-side select gate SGS. A word line WL is provided between the source-side select gate SGS and the drain-side select gates SGDO and SGD.

The memory cell MC is connected in series between the source-side select gate SGS and the drain-side select gates SGDO and SGD. The structure in which the source-side select gate SGS, the memory cell MC, and the drain-side select gates SGDO and SGD are connected in series is called a memory string or a NAND string. The memory string is connected to a wiring BL via the contacts CH and VY, for example, as described later. The contacts CH and VY are provided on each columnar body CL2and are connected between the columnar body CL2and the bit line BL. The wiring BL is provided above the second stacked body2and stretches in the Y direction. The drain-side select gate SGDO provided in the columnar body CL2can selectively connect the columnar body CL1to the bit line BL.

In some cases, the drain-side select gates SGDO and SGD may indicate the gate electrode of the drain-side select transistor or the drain-side select transistor itself.

As illustrated inFIG.1B, a slit ST stretches in the X direction in a plan view seen from the Z direction. The slit ST penetrates the second stacked body2, the third stacked body3, and the first stacked body1from the upper end of the second stacked body2through the base portion4in the Z direction and reaches a buried source line BSL. The slit ST is filled with an insulating material such as a silicon oxide film. Accordingly, the slit ST electrically divides the first to third stacked bodies1to3for each block BLOCK described later. Therefore, hereinafter, in some cases, the slit ST may also be referred to as a division insulating film60. In some cases, the slit ST may also be configured with an insulating film (not illustrated) provided on the inner wall thereof and a conductive film that is electrically insulated from the stacked bodies1to3by the insulating film and is electrically connected to the buried source line BSL buried in the slit ST. Here, the slit ST is also used as a wiring for connecting the buried source line BSL while electrically dividing the stacked bodies1to3for each block BLOCK.

On the other hand, a first division insulating film50stretches in the X direction substantially parallel to the division insulating film60in a plan view seen from the Z direction. The first division insulating film50is a shallow slit that penetrates from the upper end to the lower end of the stacked body2in the Z direction, but does not reach the stacked bodies land3. That is, the first division insulating film50penetrates the stacked body2provided with the drain-side select gate SGDO in the Z direction, but does not penetrate the stacked bodies1and3below the stacked body2. An insulating material such as silicon oxide is buried in the first division insulating film50. Accordingly, the first division insulating film50divides the drain-side select gate SGDO provided in the second stacked body2in units (hereinafter, also referred to as fingers) finer than the block BLOCK.

As illustrated inFIG.1B, in a plan view seen from the Z direction, the first stacked body1, the second stacked body2, and the third stacked body3include a staircase portion2sand a memory cell array2m. In the staircase portion2s, the memory cell array2mis interposed between or surrounded by the staircase portion2s. The slit ST is provided from the staircase portion2sat one end of the stacked bodies1to3to the staircase portion2sat the other end of the stacked body over the memory cell array2m. The portion of the stacked bodies1to3interposed between the slits ST is called a block BLOCK. The block configures, for example, the smallest unit of data erasure. As described above, the block BLOCK is further partitioned in finer units by the first division insulating film50. The on/off state of the drain-side select gate SGDO can be controlled in units (fingers) partitioned by the first division insulating film50. The finger is a unit at the time of writing and reading data. By selecting the drain-side select gate SGDO corresponding to one finger in the block, the data of the memory cell corresponding to the finger can be read or written at a time. The layout of the memory cell array2mand the staircase portion2sis not limited thereto, and any layout may be designed.

FIGS.2A and2Bare schematic cross-sectional views illustrating a memory cell having a three-dimensional structure in the first stacked body according to the first embodiment, and each of the plurality of columnar bodies CL1is provided in a memory hole MH provided in the first stacked body1. The memory hole MH penetrates the first stacked body1from the upper end of the first stacked body1along the Z direction and straddle the substrate40. Therefore, a plurality of the memory cells MC are provided corresponding to the intersections of the first conductive film12and the columnar body CL1in the first stacked body1. Each of the plurality of columnar bodies CL1includes a first insulator column101stretching in the first stacked body1in the stacking direction of the first stacked body1, a semiconductor portion102provided on an outer periphery of the first insulator column101, and a charge trapping film103provided on an outer periphery of the semiconductor portion102. The semiconductor portion102is electrically connected to the base semiconductor portion43of the base portion4. It is noted that the charge trapping film103includes a cover insulating film103a, a charge trapping portion103b, and a tunnel insulating film103cfor the plurality of memory cells MC.

As illustrated inFIG.2B, the shape of the memory hole MH in an XY plane is substantially circular. In other words, the cross section in the direction substantially perpendicular to the stacking direction of the columnar body CL1is substantially circular. A block insulating film12aconfiguring a portion of the charge trapping film103may be provided between the first insulating film11and the first conductive film12. The block insulating film12ais, for example, a silicon oxide film or a metal oxide film. The metal oxide film may be made of, for example, aluminum oxide. A barrier film12bbmay be provided between the first insulating film11and the first conductive film12and between the first conductive film12and the charge trapping film103. When the first conductive film12is made of tungsten, the barrier film12bbmay be, for example, a stacked structure film of titanium nitride (TiN) and titanium (Ti). The block insulating film12aprevents back tunneling of charges from the first conductive film12to the charge trapping film103side. The barrier film12bbimproves the adhesion between the first conductive film12and the block insulating film12a.

The shape of the semiconductor portion102may be, for example, a cylindrical shape having a bottom. The semiconductor portion102contains, for example, silicon. The silicon may be, for example, polysilicon obtained by crystallizing amorphous silicon. The semiconductor portion102is made of, for example, undoped silicon. The semiconductor portion102may be p-type silicon. The semiconductor portion102functions as a channel region of the memory cell MC and the source-side select gate SGS.

In the charge trapping film103, a portion other than the block insulating film12ais provided between the inner wall of the memory hole MH and the semiconductor portion102. The shape of the charge trapping film103is, for example, a cylindrical shape. The plurality of memory cells MC have a storage area between the semiconductor portion102and the first conductive film12serving as the word line WL and are stacked in the Z direction. The charge trapping film103includes, for example, a cover insulating film103a, a charge trapping portion103b, and a tunnel insulating film103c. Each of the semiconductor portion102, the charge trapping portion103b, and the tunnel insulating film103cextends in the Z direction.

The cover insulating film103ais provided between the first insulating film11and the charge trapping portion103b. The cover insulating film103acontains, for example, silicon oxide. The cover insulating film103aprotects the charge trapping portion103bfrom being etched in the replacing process of the first conductive film12in the manufacturing process of the semiconductor storage device described later. The cover insulating film103amay be removed from between the first conductive film12and the charge trapping film103in the replacing process. For example, the block insulating film12ais provided between the first conductive film12and the charge trapping portion103b. When the replacing process is not performed in the formation of the first conductive film12, the cover insulating film103amay not be provided.

The charge trapping portion103bis provided between the block insulating film12aand the tunnel insulating film103cand between the cover insulating film103aand the tunnel insulating film103c. The charge trapping portion103bcontains, for example, silicon nitride (SiN) and has a trap site that traps charges in the film. The portion of the charge trapping portion103binterposed between the first conductive film12serving as the word line WL and the semiconductor portion102configures the storage area of the memory cell MC. A threshold voltage of the memory cell MC changes depending on the existence or absence of electric charges in the storage area or the amount of electric charges trapped in the storage area. Therefore, the memory cell MC stores the information.

The tunnel insulating film103cis provided between the semiconductor portion102and the charge trapping portion103b. The tunnel insulating film103ccontains, for example, silicon oxide, or silicon oxide and silicon nitride. The tunnel insulating film103cis a potential barrier between the semiconductor portion102and the charge trapping portion103b. For example, when electrons are implanted from the semiconductor portion102into the storage area (writing operation) and when holes are injected from the semiconductor portion102into the storage area (erasing operation), the electrons and the holes pass through (tunneling) the potential barrier of the tunnel insulating film103c, respectively.

As described above, the charge trapping film103includes the cover insulating film103a, the charge trapping portion103b, and the tunnel insulating film103c. Therefore, the charge trapping film103is configured with a stacked film of a silicon oxide film, a silicon nitride film, and a silicon oxide film. The first insulator column101buries the internal space of the cylindrical semiconductor portion102. The shape of the first insulator column101is, for example, a columnar shape. The first insulator column101contains, for example, silicon oxide and has an insulating property.

Next, the configuration of the drain-side select gates SGDO and SGD will be described.

FIG.3Ais a schematic plan view illustrating a configuration example of the drain-side select gate SGDO.FIG.3Bis a schematic plan view of a region3B inFIG.3A.

The columnar bodies CL2are arranged two-dimensionally in a plan view seen from the stacking direction (Z direction) of the second stacked body2. As described above, the columnar body CL2is provided correspondingly on the columnar body CL1. Therefore, in a plan view seen from the Z direction, the columnar body CL2overlaps the columnar body CL1and has the same two-dimensional arrangement as the columnar body CL1. It is noted that, inFIG.3A, the columnar bodies CL2are arranged in a 12-row staggered arrangement in the block BLOCK in the Y direction, but the number of columnar bodies CL2in the block BLOCK is not particularly limited and may be any number.

The division insulating film60(deep slit ST) electrically divides the stacked bodies1to3for each block BLOCK. The division insulating film60is buried in the deep slit ST.

The plurality of first division insulating films50are provided between two adjacent division insulating films60to be substantially parallel to the division insulating films60and electrically divide second conductive films22of the second stacked body2illustrated inFIG.3C. In a plan view seen from the Z direction, the plurality of first division insulating films50and the plurality of second conductive films22of the second stacked body2are alternately arranged in a striped shape. The configuration of the second stacked body2will be described later with reference toFIGS.3C and3D.

The columnar body CL2is originally formed as an active area having a substantially oblate shape, a substantially elliptical shape, or a substantially rectangular shape having a major axis or a minor axis in an inclined direction inclined in the X and Y directions. The active area is divided by the first division insulating film50to form a pair of two columnar bodies CL2. Hereinafter, the columnar body CL2having a substantially oblate shape, a substantially elliptical shape, or a substantially rectangular shape is referred to as an initial columnar body CL2i.

The first division insulating film50skewers the initial columnar body CL2iin the X direction in a plan view seen from the Z direction, and the initial columnar body CL2iis divided into two. Accordingly, the initial columnar body CL2iis divided into two. That is, in the middle of the manufacturing process, the initial columnar body CL2ihas a substantially oblate shape, a substantially elliptical shape, or a substantially rectangular shape and is divided into two by the formation of the first division insulating film50to form a pair (CL2aand CL2b) of the columnar bodies CL2. Hereinafter, the initial columnar body CL2idivided by the first division insulating film50is also referred to as a pair of the columnar bodies CL2aand CL2b. Therefore, in the finished product, each pair of the columnar bodies CL2aand CL2bhas the shape of a portion (both end portions) of the initial columnar body CL2idivided by the first division insulating film50.

The second conductive film22of the second stacked body2illustrated inFIG.3Cis provided between the adjacent first division insulating films50and provided between a plurality of the initial columnar bodies CL2iadjacent to each other in an inclined direction with respect to the X or Y direction. Accordingly, the second conductive film22and the first division insulating film50of the second stacked body2are alternately arranged in a striped shape in a plan view seen from the Z direction. The second conductive film22covers a portion of the outer periphery of the columnar body CL2.

The contact CH illustrated inFIG.3Bis provided on each columnar body CL2, and the contact VY is provided on the contact CH. The contact VY is connected to bit lines BL1to BL4stretching in the Y direction. Accordingly, the data from each memory string is read out via the columnar body CL2, the contacts CH and VY, and the bit lines BL1to BL4.

In a plan view seen from the Z direction, the contact CH is, for example, a substantially elliptical shape having a major axis in the X direction orthogonal to the stretching direction of the bit line BL. In a plan view seen from the Z direction, the contact VY may be substantially circular, but the contact VY may be substantially elliptical. Here, the major axis of the contact VY may be in the same direction (X direction) as the major axis of the contact CH. Accordingly, since the contact VY spreads in the X direction, the bit line BL can be reliably connected by the contact VY even if the bit line BL is slightly deviated in the X direction due to the lithography.

FIG.3Cis a schematic cross-sectional view taken along line A-A inFIG.3B.FIG.3Dis a schematic cross-sectional view taken along line B-B inFIG.3B. The second stacked body2includes a second insulating film21and a second conductive film22stacked in the Z direction. The columnar body CL2is provided in a hole SH2of the second stacked body2, penetrates the second stacked body2from the upper end of the second stacked body2along the Z direction up to the upper surface of the third stacked body3.

The columnar body CL2includes a second insulator column201, a semiconductor portion202provided on an outer periphery of the second insulator column201, a first gate insulating film203provided on an outer periphery of the semiconductor portion202, an impurity layer204provided on an upper portion of the semiconductor portion202. For example, silicon oxide is used for the second insulator column201. The semiconductor portion202functions as a channel region of the drain-side select gate SGDO. For example, undoped silicon is used for the semiconductor portion202. A silicon oxide film may be used for the first gate insulating film203, or a stacked film (ONO film) of a silicon oxide film, a silicon nitride film, and a silicon oxide film may be used. The impurity layer204may be, for example, an n-type impurity diffusion layer introduced into the semiconductor portion202. The columnar body CL2configures the drain-side select gate SGDO as the first select gate portion. The drain-side select gate SGDO electrically connects the columnar body CL3and the bit line BL via the channel formed in the semiconductor portion202by using the second conductive film22as a gate electrode. In the second conductive film22, the drain-side select gate SGDO selectively connects a specific memory cell string in the same block to the bit line BL by the first division insulating film50.

The columnar body CL3is provided in a hole SH1below the columnar body CL2. The third stacked body3includes a third insulating film31and a third conductive film32stacked in the Z direction. The columnar body CL3includes a third insulator column301, a semiconductor portion302provided on the outer periphery of the third insulator column301, and a second gate insulating film303provided on the outer periphery of the semiconductor portion302. Silicon oxide is used for the third insulator column301. The semiconductor portion302functions as a channel region of the drain-side select gate SGD. For example, silicon may be used for the semiconductor portion302, and for example, undoped silicon may be used. For example, a silicon oxide film may be used for the second gate insulating film303, or a stacked film (ONO film) of a silicon oxide film, a silicon nitride film, and a silicon oxide film may be used. The drain-side select gate SGD as the second select gate portion is controlled for each block BLOCK, and the drain-side select gate SGD in the same block BLOCK is controlled to be on or off simultaneously. Accordingly, it is possible to prevent the cell current in the selected block from leaking to another non-selected block (off-leakage).

The drain-side select gates SGDO and SGD are connected in series between the memory string and the bit line BL. When both the drain-side select gate SGDO and SGD are in the on state, the memory string is electrically connected to the bit line BL. Here, the drain-side select gate SGD connects the columnar body CL1(memory string) to the drain-side select gate SGDO (columnar body CL2) in the selected block BLOCK. The drain-side select gate SGDO connects the columnar body CL1(memory string) to the bit line BL in the selected division (finger).

The drain-side select gate SGDO is provided corresponding to the contact portion between the second conductive film22of the second stacked body2and the columnar body CL2. For example, the two columnar bodies CL2illustrated inFIG.3Care in contact with the second conductive film22on one side surface in the Y direction. On the other hand, on the other side surface in the Y direction, the first division insulating film50is buried between the columnar body CL2and the second stacked body2. Therefore, the columnar body CL2is in contact with the first division insulating film50on the other side surface in the Y direction. That is, the drain-side select gate SGDO is provided on one side surface side of the columnar body CL2in the Y direction and is configured with the columnar body CL2and the second conductive film22. A plurality of the drain-side select gates SGDO sharing the same second conductive film22are connected to different bit lines BL (refer toFIG.3B). Accordingly, it is possible to prevent data from the plurality of memory cells MC from being read out from the same bit line BL at the same timing (to prevent contamination).

As illustrated inFIG.3B, in a plan view seen from the Z direction, the first division insulating film50skewers the initial columnar body CL2iin the X direction and divides the initial columnar body CL2i. Although the first division insulating film50overlaps a portion (central portion) of the initial columnar body CL2i, the first division insulating film50does not overlap the whole. Therefore, the columnar bodies CL2remain as channels of the drain-side select gate SGDO on both sides of the first division insulating film50, and the drain-side select gate SGD can function normally. Accordingly, the columnar body CL1below the drain-side select gate SGD can be normally selected by the drain-side select gate SGD as a memory string. As a result, the dummy memory cells are not increased.

When the drain-side select gate SGDO does not function due to the division insulating film, the memory cell of the columnar body CL1located below the division insulating film cannot be used for storing data and becomes a dummy memory cell. This wastes the memory cell array and hinders the miniaturization of the memory cell array2m.

On the other hand, according to at least one embodiment, although the first division insulating film50partially overlaps the initial columnar body CL2i, the columnar body CL2can be effectively used as the drain-side select gate SGDO. Therefore, the first division insulating film50can increase the data capacity of the memory cell array2mand miniaturize the memory cell array2mwithout increasing the dummy memory cell.

FIG.4is an enlarged schematic plan view of a region4inFIG.3B.FIG.4illustrates a case whereFIG.3Dis seen in a plan view seen from the Z direction.FIG.4illustrates the pair of two adjacent columnar bodies CL2aand CL2b. The pair of columnar bodies CL2aand CL2bare integrated as the initial columnar body CL2ibefore the formation of the first division insulating film50. Then, the first division insulating film50divides the initial columnar body CL2iinto the pair of two columnar bodies CL2aand CL2band electrically divides the second conductive film22corresponding to each of the columnar bodies CL2aand CL2b. As illustrated inFIG.4, each of the pair of columnar bodies CL2aand CL2bis divided by the first division insulating film50and has a shape of both end portions such as a substantially oblate shape, a substantially elliptical shape, or a substantially rectangular shape. As illustrated by a virtual line203VR, when both ends of an outer edge of a gate insulating film203aof the columnar body CL2aare virtually stretched toward the columnar body CL2bvia the first division insulating film50, the virtual line203VR is connected to both ends of an outer edge of a gate insulating film203bof the columnar body CL2b. Here, the outer edge of the columnar body CL2a, the outer edge of the columnar body CL2b, and the virtual line203VR configure the same substantially oblate, elliptical, or rectangular shape as that of the initial columnar body CL2i.

As described above, in the embodiment, the first division insulating film50divides the initial columnar body CL2ito configure a pair of columnar bodies CL2aand CL2b. In the columnar bodies CL2aand CL2b, a region other than the region facing the first division insulating film50faces the second conductive film22via the first gate insulating film203as a channel region of the drain-side select gate SGDO. Accordingly, the channel width of the drain-side select gate SGDO (the facing area between the columnar bodies CL2aand CL2band the second conductive film22) can be increased, and the drain-side select gate SGDO can allow a sufficient current from the selected memory cell MC to flow. The semiconductor portion202and the first gate insulating film203do not exist in the region other than the channel region facing the first division insulating film50. Therefore, it is possible to prevent erroneous writing of data to the first gate insulating film203, occurrence of off-leakage, and generation of electron traps.

Next, the wiring structure (bit line BL and contacts CH and VY) provided above the second stacked body2will be described in detail.

As illustrated inFIGS.3A and3B, the plurality of bit lines BL stretching in the Y direction are provided above the second stacked body2. Specifically, the semiconductor storage device100aincludes the second conductive film22(SGD) and the plurality of bit lines BL stretching in a substantially orthogonal direction (Y direction) with respect to the stretching direction (X direction) of the first division insulating film50in a plan view seen from the stacking direction of the second stacked body2.

As illustrated inFIGS.3B to3D, the contacts CH and VY and the bit line BL are provided above the columnar body CL2. That is, the semiconductor storage device100aincludes the contacts CH and VY electrically connected to the semiconductor portion202and the bit lines BL electrically connected to the contacts CH and VY, which are provided above the columnar body CL2. For example, a low resistance metal material such as titanium (Ti), titanium nitride (TiN), or tungsten (W) is used for the contact CH. For example, a low resistance metal material such as titanium nitride or tungsten is used for the contact VY. For example, a low resistance metal material such as tungsten or copper is used the bit line BL.

As illustrated inFIG.3B, the columnar body CL2aand a columnar body CL2aaare in common contact with the second conductive film22as a drain-side select gate SGDO. On the other hand, the columnar body CL2ais connected to a bit line BL3, but the columnar body CL2aais connected to another bit line BL. That is, the two drain-side select gates SGDO corresponding to the columnar bodies CL2aand CL2aasharing the drain-side select gate SGDO are connected to different bit lines BL, respectively. Therefore, it is possible to prevent data contamination in the bit line BL.

As described above, according to the embodiment, the first division insulating film50skewers the initial columnar body CL2iin the X direction, and the initial columnar body CL2iis divided into the pair of two columnar bodies CL2aand CL2b. The first division insulating film50electrically insulates the adjacent columnar bodies CL2aand CL2b. Although the first division insulating film50overlaps a portion of the central portion of the initial columnar body CL2i, the first division insulating film50does not overlap the columnar bodies CL2aand CL2bon both sides thereof. Therefore, the columnar bodies CL2aand CL2bfunction as the two different drain-side select gates SGDO. Therefore, the columnar body CL1below the columnar bodies CL2aand CL2bcan function as a memory string and does not increase the dummy memory cell. Accordingly, the cell region in the block BLOCK can be effectively used, which leads to miniaturization of the memory cell array2m.

According to at least one embodiment, the pair of columnar bodies CL2aand CL2bdoes not have the semiconductor portion202and the first gate insulating film203at the portion which is in contact with the first division insulating film50. On the other hand, the columnar bodies CL2aand CL2bhave a semiconductor portion202in other regions and face the second conductive film22via a first gate insulating film20. Therefore, while widening the channel width of the drain-side select gate SGDO, it is possible to prevent erroneous writing of data to the first gate insulating film203, the occurrence of off-leakage, and the generation of electron traps.

Next, a method for manufacturing the semiconductor storage device100aaccording to at least one embodiment will be described.FIGS.5A to12are plan views or cross-sectional views illustrating an example of the method for manufacturing the semiconductor storage device100aaccording to the first embodiment.

First, a first stacked body1ain which the first insulating film11and a first sacrificial film12bare alternately stacked is formed on the base portion4including the substrate40. For example, silicon oxide (SiO2) is used for the first insulating film11, and for example, silicon nitride (SiN) is used for the first sacrificial film12b. Next, a plurality of the memory holes MH of the first stacked body1aare formed in the first stacked body1afrom above the first stacked body1aby using a lithography technique, an etching technique, or the like. Next, in the memory hole MH, the first insulator column101, the semiconductor portion102provided on the outer periphery of the first insulator column101, and the charge trapping film103provided on the outer periphery of the semiconductor portion102are formed, and the columnar body CL1is formed.

Next, as illustrated inFIGS.5A and5B, a third insulating film31and a third sacrificial film32aare alternately stacked on the first stacked body1, and an interlayer insulating film33is further stacked to form a third stacked body3a.FIG.5Bcorresponds to a cross section taken along line C-C ofFIG.5A. For example, silicon oxide is used for the third insulating film31, and for example, silicon nitride is used for the third sacrificial film32a. For example, silicon oxide or silicon carbon nitride (SiCN) is used for the interlayer insulating film33. The interlayer insulating film33functions as an etching stopper layer in the formation of the hole SH2of the second stacked body2, which is a process described later.

Next, a plurality of holes SH1are formed in the third stacked body3a. Next, as illustrated inFIG.5B, the second gate insulating film303is formed on the inner wall of the hole SH1, the semiconductor portion302is formed inside the second gate insulating film303, and the third insulator column301is filled inside the semiconductor portion302. For example, a silicon oxide film or an ONO film is used for the second gate insulating film303. For example, silicon is used for the semiconductor portion302. For example, a silicon oxide film is used for the third insulator column301.

Next, the upper portion of the third insulator column301is etched back to bury the material of the semiconductor portion302thereon. Accordingly, the columnar body CL3illustrated inFIG.5Bis formed in the hole SH1. When the third stacked body3aand the columnar body CL3are omitted, the processes illustrated inFIGS.5A and5Bare also omitted.

Next, as illustrated inFIG.6, the second insulating film21and a second sacrificial film22aare alternately stacked on the third stacked body3ato form a second stacked body2a. For example, silicon oxide is used for the second insulating film21, and for example, silicon nitride is used for the second sacrificial film22a.FIG.6corresponds to a cross section taken along line C-C ofFIG.5A.

Next, as illustrated inFIGS.7A and7B, the hole SH2is formed in the second stacked body2afrom above the second stacked body2aby using a lithography technique, an etching technique, or the like.FIG.7Bcorresponds to a cross section taken along line D-D ofFIG.7A. Here, the hole SH2is formed up to the interlayer insulating film33which is the etching stopper of the third stacked body3a. In the region where the columnar body CL3is provided, the hole SH2is formed up to the semiconductor portion302. As illustrated inFIG.7A, the hole SH2is formed in a substantially oblate shape, a substantially elliptical shape, or a substantially rectangular shape having a major axis or a minor axis in a direction inclined with respect to the X and Y directions in a plan view seen from the Z direction.

Next, the first gate insulating film203is formed on the inner wall of the hole SH2, the semiconductor portion202is formed inside the first gate insulating film203to cover the first gate insulating film203, and the second insulator column201is buried inside the semiconductor portion202. For example, silicon is used for the semiconductor portion202. The silicon may be, for example, polysilicon obtained by crystallizing amorphous silicon. The silicon may be, for example, undoped silicon and may be, for example, p-type silicon. The first gate insulating film203may be a silicon oxide film, or may be a stacked film (ONO film) of a silicon oxide film, a silicon nitride film, and a silicon oxide film. Accordingly, the columnar bodies CL2are formed on the two adjacent columnar bodies CL3(and the two adjacent columnar bodies CL1) to correspond to the two adjacent columnar bodies CL3(and the two adjacent columnar bodies CL1). That is, the hole SH2bridges the two columnar bodies CL3that are adjacent to each other in an inclined direction with respect to the X or Y direction.

Next, as illustrated inFIGS.8A and8B, the slit ST penetrating the first stacked body1a, the second stacked body2a, and the third stacked body3ais formed by using a lithography technique, a reactive ion etching (RIE) method, or the like.FIG.8Bcorresponds to across section taken along line E-E ofFIG.8A. The first sacrificial film12bof the first stacked body1a, the second sacrificial film22aof the second stacked body2a, and the third sacrificial film32aof the third stacked body3aare removed with a phosphoric acid solution or the like via the slit ST. Then, a first space, a second space, and third space are formed between the first insulating films11, between the second insulating films21, and between the third insulating films31, respectively. Tungsten (W) is further buried in the first to third spaces by using titanium nitride (TiN), which is a conductive metal, as a barrier metal. The conductive metal buried between the first insulating films11functions as the first conductive film12. The conductive metal buried between the second insulating films21functions as the second conductive film22, and the conductive metal buried between the third insulating films31functions as the third conductive film32. By doing so, a process of burying the first conductive film12, the second conductive film22, and the third conductive film32in the space from which the first sacrificial film12b, the second sacrificial film22a, and the third sacrificial film32aare removed is called a replacing process.

The surfaces of the second conductive film22and the third conductive film32may be covered with a cover insulating film (not illustrated) in order to prevent the diffusion of the second conductive film22and the third conductive film32. For example, silicon oxide is used for the cover insulating film.

After the above replacing process, the slit ST is filled with an insulating film such as silicon oxide to form the division insulating film60. Accordingly, the block BLOCK interposed between the division insulating films60is partitioned. An insulating film made of silicon oxide or the like may be formed on the slit ST, and a conductive material may be buried inside the slit ST. Accordingly, the slit ST may be used as wiring while functioning as the division insulating film60.

Next, as illustrated inFIGS.9A to9C, the columnar body CL2and the second stacked body2are etched to divide the initial columnar body CL2iat the substantially center thereof in the X direction by using a lithography technique and an etching technique. An insulating film is buried in the slit to form the first division insulating film50. Accordingly, the first division insulating film50is formed to divide the initial columnar body CL2iat the substantially center thereof in the X direction. That is, as illustrated inFIG.9A, in a planar shape of the hole SH2, the initial columnar body CL2iis divided so that the first division insulating film50passes the substantially center of the initial columnar body CL2i. It is preferable that the left and right areas of the columnar body CL2iafter the division are substantially equal. For example, silicon oxide is used for the first division insulating film50. It is noted thatFIG.9Billustrates a cross section along the F-F line ofFIG.9A, andFIG.9Cillustrates a cross section along the G-G line ofFIG.9A.

Therefore, the initial columnar body CL2iis divided into two columnar bodies CL2aand CL2bwith the first division insulating film50interposed therebetween. Accordingly, a pair of the columnar bodies CL2aand CL2bis formed. The pair of columnar bodies CL2aand CL2bhas the shape of both end portions of a substantially oblate or substantially ellipse divided by the first division insulating film50in a plan view seen from the Z direction.

Next, as illustrated inFIG.10, an n-type impurity is introduced into the semiconductor portion202by using a lithography technique and a doping technique to form an n-type impurity layer204on the upper portion of the semiconductor portion202. The impurity layer204is formed to reach the columnar body CL2and is electrically connected to the semiconductor portion202.

Next, as illustrated inFIG.11, an interlayer insulating film68is formed on the upper surface of the second stacked body2. For example, silicon oxide is used for the interlayer insulating film68. Next, the interlayer insulating film68on the impurity layer204is processed by using a lithography technique and an etching technique to form a contact hole at the position of the contact CH. The contact hole may be formed to a depth reaching the upper surface of the impurity layer204and may be formed in a substantially oblate shape or a substantially elliptical shape in a plan view seen from the Z direction. Next, the contact hole is filled with titanium (Ti), titanium nitride (TiN) or tungsten (W), and polishing by a chemical mechanical polishing (CMP) method is performed. Accordingly, as illustrated inFIG.11, the contact CH is formed.

Next, as illustrated inFIG.12, an interlayer insulating film69is formed on the upper surface of the interlayer insulating film68. For example, silicon oxide is used for the interlayer insulating film69. The interlayer insulating film68and the interlayer insulating film69form an interlayer insulating film70. Next, a contact hole is formed in the interlayer insulating film69on the contact CH by using a lithography technique and an etching technique. The contact hole may be formed to a depth reaching the upper surface of the contact CH and may be formed in a substantially circular shape or a substantially elliptical shape in a plan view seen from the Z direction. Next, the contact hole is filled with titanium nitride or tungsten, and polishing by the CMP method is performed. Accordingly, as illustrated inFIG.12, the contact VY is formed.

Next, as illustrated inFIG.3C, a plurality of bit lines BL are provided above the contact VY to be electrically connected to the contact VY. Accordingly, the bit line BL and the columnar body CL2are electrically connected via the contacts CH and VY. The bit line BL stretches in a direction (Y direction) substantially orthogonal to the stretching direction of the second conductive film22and the first division insulating film50in a plan view seen from the Z direction. By the above-mentioned processes, the semiconductor storage device100aillustrated inFIGS.3C to3Dis obtained.

As described above, according to the embodiment, the first division insulating film50is formed to skewer the initial columnar body CL2iin the X direction in a plan view seen from the Z direction and is divided into a pair of the two columnar bodies CL2aand CL2b. Although the first division insulating film50overlaps a portion of the central portion of the initial columnar body CL2i, the first division insulating film50does not overlap the columnar bodies CL2aand CL2bon both sides thereof. The columnar bodies CL2aand CL2bcan function as two different drain-side select gates SGDO, and the columnar body CL1below the columnar bodies CL2aand CL2bcan function as a memory string. Accordingly, the first division insulating film50does not increase the number of dummy memory cells and enables the cell region in the block BLOCK to be effectively used. As a result, waste of the memory cell array can be reduced, and the memory cell array2mcan be further miniaturized.

According to the embodiment, in the columnar bodies CL2aand CL2b, the region other than the region facing the first division insulating film50faces the second conductive film22via the first gate insulating film203as the channel region of the drain-side select gate SGDO. Accordingly, the channel width of the drain-side select gate SGDO can be increased, and the drain-side select gate SGDO can allow a sufficient current from the selected memory cell MC to flow. The semiconductor portion202and the first gate insulating film203do not exist in the region facing the first division insulating film50other than the channel region. Therefore, it is possible to prevent erroneous writing of data to the first gate insulating film203, the occurrence of off-leakage, and the generation of electron traps. Therefore, the controllability of the drain-side select gate SGDO is improved.

Second Embodiment

FIG.13Ais a schematic plan view of the second stacked body according to the second embodiment as seen from the Z direction.FIG.13Bis a schematic plan view of the region13B inFIG.13A.

The second embodiment is similar to the first embodiment in that a conductive layer BW and the second insulating film21are alternately arranged in a striped shape in a plan view seen from the Z direction. However, in the second embodiment, the conductive layer BW skewers the active area in the X direction, and an initial first semiconductor column AAi is divided into two. Accordingly, the initial first semiconductor column AAi is divided into two first semiconductor columns AA1and AA2. That is, in the middle of the manufacturing process, the initial first semiconductor column AAi has a substantially oblate shape, a substantially elliptical shape, or a substantially rectangular shape and is divided into two by the formation of the conductive layer BW to form a pair of the first semiconductor columns AA1and AA2. For example, a conductive metal such as tungsten (W) is used for the conductive layer BW. On the other hand, the second insulating film21is provided between the adjacent conductive layers BW and is provided between the two first semiconductor columns AA that are adjacent to each other in an inclined direction with respect to the X or Y direction. For example, an insulating material such as silicon oxide is used for the second insulating film21. As described above, in the second embodiment, the conductive layer BW (drain-side select gate SGD) is provided between the paired first semiconductor columns AA1and AA2. Other configurations of the planar layout of the second embodiment may be the same as the corresponding configuration of the planar layout of the first embodiment.

FIG.13Cis a schematic cross-sectional view taken along line H-H ofFIG.3B.FIG.13Dis a schematic plan view taken along line I-I ofFIG.13B. In the second embodiment, the second conductive film22is not provided, and the second insulating film21is provided instead of the second stacked body. As the gate electrode of the drain-side select gate SGDO, the conductive layer BW is provided instead of the second conductive film22. The conductive layer BW faces the first semiconductor columns AA1and AA2via the gate insulating film203and functions as a gate electrode of the drain-side select gate SGD. For example, a silicon oxide film or an ONO film is used for the gate insulating film203.

The pair of first semiconductor columns AA1and AA2is provided in the hole SH2provided in the second insulating film21and penetrates the second insulating film21from the upper end of the second insulating film21along the Z direction up to the upper surface of the columnar body CL3. The first semiconductor columns AA1and AA2function as channel regions of the drain-side select gate SGDO.

In the second embodiment, the drain-side select gate SGDO is configured with the conductive layer BW and the first semiconductor column AA1(or AA2). For example, the two first semiconductor columns AA1and AA2inFIG.13Cface the conductive layer BW via the gate insulating film203on one side surface in the Y direction. The conductive layer BW is buried between the first semiconductor columns AA1and AA2and the second insulating film21. On the other hand, the second insulating film21is in contact with the first semiconductor columns AA1and AA2on the other side surface of the first semiconductor columns AA1and AA2in the Y direction. Therefore, the drain-side select gate SGDO is provided on one side surface side of the first semiconductor columns AA1and AA2in the Y direction, respectively. The drain-side select gate SGDO is provided in a facing region of the first semiconductor columns AA1and AA2and the conductive layer BW.

In the second embodiment, the conductive layer BW skewers the initial first semiconductor column AAi in the X direction, and the initial first semiconductor column AAi is divided into a pair of the first semiconductor columns AA1and AA2. Therefore, the conductive layer BW overlaps the central portion of the initial first semiconductor column AAi, but the conductive layer BW does not overlap as a whole. Therefore, as illustrated inFIG.13D, the first semiconductor columns AA1and AA2remain as channels of the drain-side select gate SGD on both sides of the conductive layer BW. The conductive layer BW does not almost reach the two columnar bodies CL3and the two columnar bodies CL1directly under the first semiconductor columns AA1and AA2. Therefore, the first semiconductor columns AA1and AA2can function as a portion of two different drain-side select gates SGDO. The columnar body CL1below each of the first semiconductor columns AA1and AA2effectively functions as a memory string. Accordingly, the conductive layer BW does not increase the number of dummy memory cells and enables the cell region in the block BLOCK to be effectively used.

Other configurations of the second embodiment may be the same as the corresponding configurations of the first embodiment. Therefore, according to the second embodiment, it is also possible to obtain effects other than those of the first embodiment.

Next, a method for manufacturing a semiconductor storage device100baccording to the second embodiment will be described.

FIGS.14to17are schematic cross-sectional views or schematic plan views illustrating an example of the method for manufacturing the semiconductor storage device100baccording to the second embodiment.

First, similarly to the first embodiment, the first stacked body1a, the columnar body CL1, the stacked body3a,and the columnar body CL3are formed.

Next, as illustrated inFIG.14, the second insulating film21is formed above the stacked body3a. The thickness of the second insulating film21in the Z direction may be, for example, about the same thickness as the second stacked body2of the first embodiment.

Next, as illustrated inFIGS.15A and15B, the hole SH2is formed in the second insulating film21by using a lithography technique, an etching technique, or the like.FIG.15Bcorresponds to the cross section taken along line J-J ofFIG.15A. The hole SH is formed up to the interlayer insulating film33which is the etching stopper layer of the stacked body3a. In the region where the columnar body CL3is provided, the hole SH2is formed up to the semiconductor portion302. After the hole SH2is formed, the initial first semiconductor column AAi is formed in the hole SH2. As illustrated inFIG.15A, the initial first semiconductor column AAi is formed in a substantially oblate shape, a substantially elliptical shape, or a substantially rectangular shape having a major axis or a minor axis in a direction inclined with respect to the X and Y directions in a plan view seen from the Z direction.

Next, as described with reference toFIGS.9A and9B, the slit ST is formed, and the replacing process is executed. Here, the first sacrificial film12bof the first stacked body1ais replaced with the first conductive film12, and the sacrificial film32aof the stacked body3ais replaced with the conductive film32. In the second embodiment, since the second stacked body2is not provided, the replacing process is not performed in the second insulating film21. In the second embodiment, the replacing process may be performed before the formation of the insulating film21.

Next, as illustrated inFIGS.16A to16C, the initial first semiconductor column AAi and the second insulating film21are etched to form the slit to divide the initial first semiconductor column AAi at the substantially center thereof in the X direction by using a lithography technique and an etching technique.FIG.16Billustrates a cross section taken along line K-K inFIG.16A, andFIG.16Cillustrates a cross section taken along line L-L inFIG.16A. The gate insulating film203is formed on the inner wall of the slit, and a material for the conductive layer BW is further buried inside the gate insulating film203. Accordingly, the conductive layer BW is formed to divide the initial first semiconductor column AAi at the substantially center thereof in the X direction. The conductive layer BW is electrically insulated from the first semiconductor columns AA1and AA2by the gate insulating film203. Therefore, as illustrated inFIG.16A, in the planar shape of the hole SH2, the initial first semiconductor column AAi is divided so that the conductive layer BW passes the substantially center of the initial first semiconductor column AAi. It is noted that it is preferable that the left and right areas of the initial first semiconductor column AAi after the division are substantially equal.

Therefore, the initial first semiconductor column AAi is divided into the two first semiconductor columns AA1and AA2with the conductive layer BW interposed between the two first semiconductor columns AA1and AA2. The pair of first semiconductor columns AA1and AA2has the shapes of both end portions of a substantially oblate or a substantially ellipse divided by the conductive layer BW in a plan view seen from the Z direction.

Next, the conductive layer BW is etched back by using an etching technique to form a groove on the conductive layer BW. An insulating film (for example, a silicon oxide film)25is buried in the groove. Accordingly, the structures illustrated inFIGS.16A to16Care obtained.

Next, as illustrated inFIG.17, n-type impurities are introduced into the first semiconductor columns AA1and AA2by using a lithography technique and a doping technique, and an n-type impurity layer204is formed above the first semiconductor columns AA1and AA2. Accordingly, the impurity layer204is electrically connected to the first semiconductor columns AA1and AA2.

Next, as described with reference toFIGS.11and12, a wiring structure (contacts CH and VY and bit lines BL) is formed. Accordingly, the semiconductor storage device100baccording to the second embodiment illustrated inFIGS.13Ato13D are obtained.

According to the second embodiment, the conductive layer BW skewers the initial first semiconductor column AAi in the X direction, and the initial first semiconductor column AAi is divided. Although the conductive layer BW overlaps a portion of the central portion of the initial first semiconductor column AAi, the conductive layer BW does not overlap the first semiconductor columns AA1and AA2on both sides thereof. The first semiconductor columns AA1and AA2can function as channel portions of the two different drain-side select gates SGDO. The columnar body CL1below the first semiconductor columns AA1and AA2can function as a memory string. Accordingly, the conductive layer BW does not increase the number of dummy memory cells and enables the cell region in the block BLOCK to be effectively used. As a result, according to the second embodiment, it is possible to obtain the same effect as the first embodiment.

Third Embodiment

FIG.18is a schematic plan view illustrating a configuration example of a semiconductor storage device100caccording to the third embodiment.

In the third embodiment, a plurality of the conductive films22in the same block BLOCK and adjacent to each other in the Y direction are electrically connected. Other configurations of the third embodiment may be the same as the configurations of the first embodiment.

In some cases, in order to read out a plurality of data from the same block BLOCK simultaneously, the plurality of second conductive films22of the semiconductor storage device100carranged in the Y direction may be electrically connected to each other. For example, inFIG.18, a second conductive film22_1of a drain-side select gate SGD1and a second conductive film22_2of a drain-side select gate SGD2adjacent to the drain-side select gate SGD1are connected by a connection line C1. A second conductive film22_3of a drain-side select gate SGD3and a second conductive film22_4of a drain-side select gate SGD4adjacent to the drain-side select gate SGD3are connected by a connection line C2. A second conductive film22_5of a drain-side select gate SGD5, a second conductive film22_6of a drain-side select gate SGD6adjacent to the drain-side select gate SGD5, and a second conductive film22_0of the drain-side select gate SGD0on the opposite side of the second conductive film22_6are electrically connected by a connection line C3.

Although not illustrated, the connection lines C1to C3may be configured with a contact plug provided in the staircase portion2sand connected to each of the second conductive films22_0to22_6and a wiring layer above the contact plug. Alternatively, the connection lines C1to C3may be implemented by omitting the first division insulating film50in the staircase portion2sand bringing the plurality of second conductive films into direct contact with each other.

Therefore, by connecting the plurality of second conductive films22and driving the plurality of second conductive films22simultaneously, it is possible to readout a large amount of data at one time. On the other hand, when a plurality of data are simultaneously transmitted to the same bit line BL, data contamination occurs.

In contrast, in at least one embodiment, the four bit lines BL1to BL4are provided correspondingly to one active area Aa (a pair of the adjacent columnar bodies CL2). That is, the columnar body CL2and the bit line BL are provided at a ratio of 1:2. A plurality of the active areas Aa arranged in the stretching direction (Y direction) of the bit line BL share the bit line BL. Therefore, for example, the active areas Aa arranged in the Y direction in the upper stage ofFIG.18correspond to the four bit lines BL1to BL4. The data from the four drain-side select transistors configured with columnar bodies CL2A to CL2D arranged in the upper stage can be read out without contamination via the bit lines BL1, BL4, BL2, and BL3, respectively. That is, the four columnar bodies CL2A to CL2D corresponding to the second conductive films22_1and22_2connected by the connection line C1can simultaneously output data to the bit lines BL1, BL4, BL2, and BL3, respectively.

Similarly, the four columnar bodies CL2in the upper stage corresponding to the second conductive films22_3and22_4can simultaneously output data to the bit lines BL1, BL4, BL2, and BL3, respectively. Similarly, the four columnar bodies CL2in the upper stage corresponding to the second conductive films22_5,22_6, and22_0can simultaneously output data to the bit lines BL1, BL4, BL2, and BL3, respectively. The second conductive films22_1and22_2, the second conductive films22_3and22_4, and the second conductive films22_5,22_5, and22_0are driven at timings different from each other. Since the second conductive films22_5and22_0are conductive films at the end of the block BLOCK, the second conductive films22_5and22_0correspond to one columnar body CL2in the upper stage, respectively.

Similarly, the active areas Aa arranged in the Y direction in the second and subsequent stages also correspond to four bit lines BL, respectively. Therefore, the data from the drain-side select transistors configured with the columnar bodies arranged in the second and subsequent stages can also be read out without contamination via different bit lines BL.

A ratio between the number of columnar bodies CL2and the number of bit lines BL may be 1:n (n is an integer of 3 or more). Here, a ratio between the number of active areas Aa and the number of bit lines BL is 1:2×n. The number of the second conductive films22connected to each other (driven simultaneously) is also n, and thus, the number of data read simultaneously can be further increased.

In a plan view seen from the Z direction, the contact VY may be a substantially circular shape, but may be a substantially elliptical shape having a major axis in the X direction. Accordingly, since the contact VY spreads in the X direction, the bit line BL can be reliably connected by the contact VY even if the bit line BL is slightly deviated in the X direction due to the lithography. However, as long as the contact VY can connect between the contact CH and the bit line BL, the direction of the major axis of the contact VY is not particularly limited. The direction of the major axis of the contact CH is not particularly limited.

Other configurations and manufacturing methods of the third embodiment may be the same as those of the first embodiment. Accordingly, according to the third embodiment, it is also possible to obtain the effects of the first embodiment. The third embodiment may be applied to the second embodiment.

Fourth Embodiment

FIGS.19A and19Bare a plan view and a cross-sectional view illustrating a configuration example of a semiconductor storage device100daccording to the fourth embodiment.FIG.19Bis a schematic cross-sectional view taken along line N-N ofFIG.19A.

In the fourth embodiment, as illustrated inFIG.19B, the contact CH bridges above the pair of columnar bodies CL2aand CL2b. That is, the contact CH is provided above each of the impurity layers204of the columnar bodies CL2aand CL2band connects each of the impurity layers204. Accordingly, the semiconductor portions202of the columnar bodies CL2aand CL2bare electrically connected. In other words, the contact CH is commonly electrically connected to the semiconductor portions202of the columnar bodies CL2aand CL2bover the pair of columnar bodies CL2aand CL2bformed by dividing each active area Aa and the first division insulating film50. The impurity layer204may be a diffusion layer formed by introducing the implant technology, but instead of the diffusion layer, a doped polysilicon formed by burying polysilicon doped with impurities may be used.

One contact VY is provided on each contact CH. Each contact CH is connected to one bit line BL via the contact VY.

According to the fourth embodiment, the contact CH is provided corresponding to two adjacent columnar bodies CL2(one active area Aa). Accordingly, the number of contacts CH and VY can be reduced to about half the number of columnar bodies CL2. As the number of contacts CH decreases, the layout area of the contacts CH can be increased. As the number of contacts VY decreases, the density of contacts VY decreases. Accordingly, the lithography and etching processes in forming the contact VY are facilitated.

As illustrated inFIG.19A, contacts CH are provided for each pair of the columnar bodies CL2(active area Aa). For example, a pair of columnar bodies CL2A and CL2B is provided below a contact CH1. A pair of columnar bodies CL2C and CL2D is provided below a contact CH2. A pair of columnar bodies CL2E and CL2F is provided below a contact CH3. A pair of columnar bodies CL2G and CL2H is provided below a contact CH4. InFIG.19A, the columnar bodies CL2A to CL2H are below the contacts CH1to CH4, and outer shapes thereof do not appear. Contacts VY1to VY4are provided on the contacts CH1to CH4, and the contacts CH1to CH4are connected to the bit lines BL1, BL3, BL2, and BL4, respectively.

Also in the fourth embodiment, the four bit lines BL1to BL4are provided with respect to one active area Aa (a pair of the adjacent columnar bodies CL2). That is, the columnar body CL2and the bit line BL are provided at a ratio of 1:2. On the other hand, the two active areas Aa adjacent in the stretching direction (Y direction) of the bit line BL are deviated by a half pitch in the X direction and share the two bit lines BL. Therefore, for example, the pair of columnar bodies CL2A and CL2B inFIG.19Acorrespond to the four bit lines BL1to BL4. The pair of columnar bodies CL2C and CL2D adjacent to the pair of columnar bodies CL2A and CL2B share only the bit lines BL3and BL4among the bit lines BL1to BL4together with the pair of columnar bodies CL2A and CL2B. Since the pair of columnar bodies CL2E and CL2F adjacent to the pair of columnar bodies CL2C and CL2D deviate by one pitch in the X direction with respect to the pair of columnar bodies CL2A and CL2B, the pair of columnar bodies CL2E and CL2F share the bit lines BL1to BL4together with the pair of columnar bodies CL2A and CL2B. As described above, in the fourth embodiment, the active areas Aa adjacent to each other in the Y direction share two bit lines. The active areas Aa intermittently adjacent in the Y direction share four bit lines BL.

The contacts VY1to VY4are provided on the contacts CH1to CH4, respectively, and the contacts CH1to CH4are connected to the bit lines BL1, BL3, BL2, and BL4, respectively.

In the fourth embodiment, the second conductive film22_1of the drain-side select gate SGD1and the second conductive film22_3of the drain-side select gate SGD3are connected by the connection line C1. The second conductive film22_0of the drain-side select gate SGD0, the second conductive film22_2of the drain-side select gate SGD2, and the second conductive film22_4of the drain-side select gate SGD4are electrically connected by the connection line C2.

When the second conductive films22_1and22_3are driven, the four columnar bodies CL2B, CL2C, CL2F, and CL2G corresponding to the second conductive films can simultaneously output data to the bit lines BL1, BL3, BL2, and BL4, respectively. When the second conductive films22_0,22_2, and22_4are driven, the four columnar bodies CL2A, CL2D, CL2E, and CL2H corresponding to the second conductive films22_0,22_2, and22_4can simultaneously output data to the bit lines BL1, BL3, BL2, and BL4, respectively. Therefore, the data from the four drain-side select transistors can be read out without contamination via the bit lines BL1, BL4, BL2, and BL3, respectively.

As illustrated inFIG.19B, the pair of columnar bodies CL2A and CL2B share the contact CH, but the two drain-side select gates SGDO corresponding to the columnar bodies CL2A and CL2B allow different second conductive films22to operates as gate electrodes. Therefore, data contamination between the two drain-side select gates SGDO corresponding to the columnar bodies CL2A and CL2B is also prevented.

The ratio between the number of columnar bodies CL2and the number of bit lines BL may be 1:n (n is an integer of 3 or more). Here, the ratio between the number of contacts CH and the number of bit lines BL is 1:2×n. Thereby, similarly to the third embodiment, it is possible to increase the number of data that are read simultaneously.

In the fourth embodiment, the layout of the contacts CH and VY is different from that of the first embodiment, and the contact CH is provided corresponding to the active area Aa. Accordingly, the layout area of the contact CH can be increased, and the density of the contact VY can be reduced. Accordingly, the lithography and etching processes in forming the contact VY are facilitated.

Other configurations and manufacturing methods of the fourth embodiment may be the same as those of the first embodiment. According to the fourth embodiment, it is also possible to obtain the effects of the first embodiment. The fourth embodiment may be applied to the second embodiment.

FIG.20is a block diagram illustrating a configuration example of a semiconductor storage device to which any of the above embodiments is applied. A semiconductor storage device100is a NAND flash memory capable of non-volatilely storing data and is controlled by an external memory controller1002. Communication between the semiconductor storage device100and the memory controller1002supports, for example, the NAND interface standard.

As illustrated inFIG.20, the semiconductor storage device100includes, for example, a memory cell array MCA, a command register1011, an address register1012, a sequencer1013, a driver module1014, a row decoder module1015, and a sense amplifier module1016.

The memory cell array MCA includes a plurality of blocks BLK(0) to BLK(n) (n is an integer of 1 or more). The block BLK is a set of the plurality of memory cells capable of non-volatilely storing data and is used, for example, as an erase unit of data. The plurality of bit lines and the plurality of word lines are provided in the memory cell array MCA. Each memory cell is associated with, for example, one bit line and one word line. The detailed configuration of the memory cell array MCA will be described later.

The command register1011stores a command CMD received by the semiconductor storage device100from the memory controller1002. The command CMD includes, for example, an instruction for causing the sequencer1013to execute a read operation, a write operation, an erase operation, and the like.

The address register1012stores address information ADD received by the semiconductor storage device100from the memory controller1002. The address information ADD includes, for example, a block address BAdd, a page address PAdd, and a column address CAdd. For example, a block address BA, a page address CAD, and a column address CAdd are used to select the block BLK, the word line, and the bit line, respectively.

The sequencer1013controls the overall operations of the semiconductor storage device100. For example, the sequencer1013controls the driver module1014, the row decoder module1015, the sense amplifier module1016, and the like based on the command CMD stored in the command register1011to execute a read operation, a write operation, an erase operation, and the like.

The driver module1014generates voltages used in the read operation, the write operation, the erase operation, and the like. Then, the driver module1014applies a generated voltage to the signal line corresponding to the selected word line based on, for example, the page address PAdd stored in the address register1012.

The row decoder module1015includes a plurality of row decoders RD. The row decoder RD selects one block BLK in the corresponding memory cell array MCA based on the block address BAdd stored in the address register1012. Then, the row decoder RD transfers, for example, the voltage applied to the signal line corresponding to the selected word line to the selected word line in the selected block BLK.

In the write operation, the sense amplifier module1016applies a desired voltage to each bit line according to write data DAT received from a memory controller200. In the read operation, the sense amplifier module1016determines the data stored in the memory cell based on the voltage of the bit line and transfers the determination result to the memory controller200as read data DAT.

The semiconductor storage device100and the memory controller200described above may configure one semiconductor device by combining the semiconductor storage device100and the memory controller200. As such a semiconductor device, exemplified are a memory card such as an SDTM card, a solid state drive (SSD), and the like.

FIG.21is a circuit diagram illustrating an example of the circuit configuration of the memory cell array MCA. One block BLK out of the plurality of blocks BLK in the memory cell array MCA is extracted. As illustrated inFIG.21, the block BLK includes a plurality of string units SU(0) to SU(k) (k is an integer of 1 or more).

Each string unit SU includes a plurality of NAND strings NS associated with bit lines BL(0) to BL(m) (m is an integer of 1 or more). Each NAND string NS includes, for example, memory cell transistors MT(0) to MT(15), and select transistors ST(1) and ST(2). A memory cell transistor MT includes a control gate and a charge storage layer and stores data in a non-volatile manner. Each of the select transistors ST(1) and ST(2) is used to select the string unit SU during various operations.

In each of the NAND strings NS, the memory cell transistors MT(0) to MT(15) are connected in series. The drain of the select transistor ST(1) is connected to the associated bit line BL, and the source of the select transistor ST(1) is connected to one end of the memory cell transistors MT(0) to MT(15) connected in series. The drain of the select transistor ST(2) is connected to the other end of the memory cell transistors MT(0) to MT(15) connected in series. The source of the select transistor ST(2) is connected to a source line SL.

In the same block BLK, the control gates of the memory cell transistors MT(0) to MT(15) are commonly connected to word lines WL(0) to WL(7), respectively. The gates of the respective select transistors ST(1) in the string units SU(0) to SU(k) are commonly connected to select gate lines SGD(0) to SGD(k), respectively. The gate of the select transistor ST(2) is commonly connected to select gate lines SGS.

In the circuit configuration of the memory cell array10described above, the bit line BL is shared by the NAND strings NS to which the same column address is assigned in each string unit SU. The source line SL is shared among, for example, the plurality of blocks BLK.

A set of the plurality of memory cell transistors MT connected to the common word line WL in one string unit SU is referred to as, for example, a cell unit CU. For example, the storage capacity of the cell unit CU including the memory cell transistor MT, each of which stores 1-bit data, is defined as “1 page data”. The cell unit CU may have a storage capacity of two-page data or more depending on the number of bits of data stored in the memory cell transistor MT.

The memory cell array MCA in the semiconductor storage device100according to at least one embodiment is not limited to the circuit configuration described above. For example, the number of memory cell transistors MT and the select transistors ST(1) and ST(2) in each NAND string NS may be any number. The number of string units SU in each block BLK may be any number.