Sense amplifiers and semiconductor memory devices for reducing power consumption and methods for operating the same

In a sense amplifier, a current amplifier outputs a first and a second voltage signal in response to a first control signal. The first and second voltage signals are output based on a detected current difference between a pair of input/output lines. A voltage amplifier generates a third and a fourth voltage signal based on a detected voltage difference between the first and second voltage signals. The third and a fourth voltage signals are generated in response to a second control signal. A first latch circuit latches the third and fourth voltage signals, and outputs a first output signal in response to the second control signal. A second latch circuit latches the first and second voltage signals and outputs a second output signal in response to a third control signal. An output circuit performs a logic operation on the first output signal and the second output signal, and outputs a result of the logic operation as a resultant signal.

PRIORITY STATEMENT

This U.S. patent application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2007-0006737, filed on Jan. 22, 2007, in the (Korean Intellectual Property Office (KIPO), the entire contents of which is incorporated herein by reference.

BACKGROUND

Description of the Related Art

Sizes of conventional semiconductor memory devices may increase as technology develops. As such, lengths of data lines for inputting and outputting data of the semiconductor memory device may also increase, causing an increase in resistance and/or power consumption.

In a conventional read operation, loss generated in a signal output from a memory cell array may correspond to length of a data I/O line. To counteract such losses, conventional semiconductor memory devices may include an I/O sense amplifier for amplifying a data signal output from the memory cell array and outputting an amplified data signal to the outside of the semiconductor memory device.

Conventionally, a pair of bit lines may be connected to the memory cell and the data signal stored in the memory cell may be amplified and output by the bit line sense amplifier. However, because the level of an output signal of the bit line sense amplifier is relatively small, the output signal is amplified again before being output by the I/O sense amplifier at an end of the I/O data line. As a result, conventional semiconductor memory devices may consume a relatively large amount of power in the I/O sense amplifier.

SUMMARY

Example embodiments relate to semiconductor devices, for example, input/output sense amplifiers, which m.-ay reduce power consumption. According to at least one example embodiment, I/O sense amplifiers may reduce unnecessary power consumption by selectively changing an operating mode of the I/O sense amplifier according to the length of the I/O sense amplifier of a memory cell during the data read of a semiconductor memory device, and methods of operating I/O sense amplifiers.

In at least one example embodiment of an input/output sense amplifier, a current amplifier may detect a current difference between a pair of input/output lines, amplify the detected current difference, and output voltage signals in response to a first control signal. A voltage amplifier may detect and amplify a voltage difference between output signals of the current amplifier in response to a second control signal. A first latch circuit may latch output signals from the voltage amplifier and output a first output signal in response to the second control signal. A second latch circuit may latch output signals of the current amplifier and output a second output signal in response to a third control signal. An output circuit may receive and perform a logical operation of the first output signal and the second output signal and output a result of the operation. The voltage amplifier may be a current mirror type voltage amplifier.

According to at least some example embodiments, each of the first latch circuit and the second latch circuit may be a cross-coupling-type latch circuit. The second control signal and the third control signal may be selectively enabled based on a row address signal. The second control signal may be generated based on a first row address signal. The first row address signal may address word lines in a group located a first distance (e.g., relatively far) from the input/output sense amplifier when the word lines are grouped into at least two groups. The third control signal may be generated based on a second row address signal. The second row address signal may address word lines in a group located a second distance (e.g., relatively close) to the input/output sense amplifier when the word lines are grouped into at least two groups. The first distance may be greater than the second distance.

According to at least some example embodiments, the output circuit may logically multiply the first output signal and the second output signal and output a multiplied signal. The first latch circuit and the second latch circuit may be pre-charged to a first voltage level. The first output signal and the second output signal may swing to a given or desired (e.g., CMOS) voltage level.

In at least one example embodiment of a semiconductor memory device, a memory cell array may be configured to store data. An input/output sense amplifier may amplify a data signal received through a pair of input/output lines. Within the input/output sense amplifier, a current amplifier may be configured to detect a current difference between the input/output lines, amplify a detected current difference, and output voltage signals in response to a first control signal. A voltage amplifier may detect and amplify a voltage difference between output signals of the current amplifier in response to a second control signal. A first latch circuit may latch output signals of the voltage amplifier and output a first output signal in response to the second control signal. A second latch circuit may latch output signals of the current amplifier and output a second output signal in response to a third control signal. An output circuit may receive and perform a logical operation of the first output signal and the second output signal and output a result of the operation.

In at least one example embodiment of a method of operating an input/output sense amplifier, a current difference between a pair of input/output lines may be detected, and the detected current difference may be amplified. Voltage signals may be output in response to a first control signal using a current amplifier. A voltage difference between output signals of the current amplifier may be detected and amplified in response to a second control signal using a voltage amplifier. A first output signal may be output based on output signals of the voltage amplifier in response to the second control signal using a first latch circuit. A second output signal may be output based on output signals of the current amplifier in response to a third control signal using a second latch circuit. A logic operation may be performed on the first output signal and the second output signal and the result may be output using an output circuit.

According to at least some example embodiments, the first output signal may maintain a power voltage level when the second control signal is disabled and the second output signal may maintain the power voltage level when the third control signal is disabled. The second control signal may be generated based on a first row address signal. The first row address signal may address word lines in a group located a first distance (e.g., relatively far) from the input/output sense amplifier when the word lines are grouped into at least two groups. The third control signal may be generated based on a second row address signal. The second row address signal may address word lines in a group located a second distance (e.g., relatively close) to the input/output sense amplifier when the word lines are grouped into at least two groups.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

Various example embodiments of the present invention will now be described more fully with reference to the accompanying drawings in which some example embodiments of the invention are shown. In the drawings, the thicknesses of layers and regions are exaggerated for clarity.

Detailed illustrative embodiments of the present invention are disclosed herein. However, specific structural and functional details disclosed herein are merely representative for purposes of describing example embodiments of the present invention. This invention may, however, may be embodied in many alternate forms and should not be construed as limited to only the embodiments set forth herein.

Accordingly, while example embodiments of the invention are capable of various modifications and alternative forms, embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that there is no intent to limit example embodiments of the invention to the particular forms disclosed, but on the contrary, example embodiments of the invention are to cover all modifications, equivalents, and alternatives falling within the scope of the invention. Like numbers refer to like elements throughout the description of the figures.

FIG. 1schematically illustrates an example configuration of a semiconductor memory device according to an example embodiment.FIG. 2schematically illustrates an example configuration of the memory cell array ofFIG. 1. Referring toFIGS. 1 and 2, a semiconductor memory device100may include a plurality of memory cell arrays110, a row decoder circuit120, a column decoder circuit130and a plurality of input/output (I/O) sense amplifiers140.

The memory cell array110may include a memory cell111, a bit line sense amplifier112and a column selection circuit113. During a read operation of the semiconductor memory device100, the memory cell111may output data stored at the memory cell111in response to selection of a word line based on a row address signal.

The bit line sense amplifier112may amplify a data signal received from the memory cell111through a pair of bit lines (BL/BLB) to first voltage level. In response to a column selection signal (CSL), the column select circuit113may output the data signal amplified by the bit line sense amplifier112.

The row decoder circuit120may decode a row address signal and output a word line selection signal to enable one or more of the word lines of the semiconductor memory device100. The column decoder circuit130may decode a column address signal and output the CSL to select one or more of the bit lines of the memory cell arrays110.

The I/O sense amplifier140may receive a data signal output from the memory cell arrays110through a pair of local I/O lines (IO/IOB) and a pair of global I/O lines (DIO/DIOB). The I/O sense amplifier140may convert the received data signal to a first (e.g., CMOS) voltage level and output the resultant signal.

FIG. 3schematically illustrates an example configuration of the I/O sense amplifier140.FIG. 4is a more detailed circuit diagram of the I/O sense amplifier140. Referring toFIGS. 1 through 4, the I/O sense amplifier140may include a current amplifier210, a voltage amplifier220, a first latch circuit230, a second latch circuit240and an output circuit250.

The current amplifier210may include a first current amplifier switching circuit including first and second transistors (e.g., PMOS transistors) P1and P2and a second current amplifier switching circuit including first through third transistors (e.g., NMOS transistors) N1, N2and N3. The first transistor P1may be connected between I/O line DIO and output node Q1, and the second transistors P2may be connected between I/O line DIOB and output node Q2. The gate terminal of the first transistor P1may be connected to the output node Q2, and the gate terminal of the second transistor P2may be connected to the output node Q1.

The first transistor N1may be connected between the first node Q1and a third node Q3. The gate terminal and the source terminal of the first NMOS transistor N1may be connected to each other. The second transistor N2may be connected between the second node Q2and the third node Q3. The gate terminal and the source terminal of the second transistor N2may be connected to each other. The third transistor N3may be connected between the third node Q3and a ground terminal Vss and may be enabled in response to a first control signal CON1.

In example operation, the current amplifier210may detect a current level of the global I/O lines DIO and DIOB output from a selected one of the memory cell arrays110in the semiconductor memory device100. The current amplifier210may convert the current of the global I/O lines DIO and DIOB to a desired voltage level in response to the first control signal CON1. The current amplifier210may amplify and output the converted voltage. The first control signal CON1may be generated based on a read command from the semiconductor memory device100.

The voltage amplifier220may include a first voltage amplifier switching circuit including third through fourth transistors (e.g., PMOS transistors) P3and P4and a second voltage amplifier switching circuit including fourth through sixth transistors (e.g., NMOS transistors) N4, N5and N6.

The third transistor P3may be connected between a power port or supply voltage Vdd and a fourth node Q4. The fourth transistor P4may be connected between the supply voltage Vdd and a fifth node Q5. The gate terminals of the third and fourth transistors P4and P5may be connected to the fourth node Q4.

The fourth transistor N4may be connected between the fourth node Q4and a sixth node Q6. The fourth transistor N4may operate in response to an output voltage V2of the first node Q1. The fifth transistor N5may be connected between the fifth node Q5and the sixth node Q6and may operate in response to an output voltage V1of the second node Q2. The sixth transistor N6may be connected between the sixth node Q6and a ground terminal Vss and may operate in response to a second control signal CON2.

In example operation, the voltage amplifier220may detect output voltages V1and V2of the current amplifier210, amplify and output a difference between the detected output voltages V1and V2of the current amplifier210in response to the second control signal CON2. The voltage amplifier220may be a differential amplifier, for example, a current mirror-type amplifier. The second control signal CON2may be generated based on a first row address signal and a read command. The first row address signal may address word lines in a group located relatively far from the l/O sense amplifier140when the word lines are grouped into at least two groups. For example, the first row address signal may select one or more of the word lines of the first group of the word lines shown inFIG. 1.

The first latch circuit230may include fifth through sixth transistors (e.g., PMOS transistors) P5and P6and seventh through tenth transistors (e.g., NMOS transistors) N7, N8, N9, N10and N11. The fifth transistor P5may be connected between the supply voltage Vdd and the seventh node Q7. The sixth transistor P6may be connected between the supply voltage Vdd and the eighth node Q8.

The ninth transistor N9may operate in response to an output voltage V4of the fourth node Q4. The tenth transistor N10may operate in response to an output voltage V3of the fifth node Q5. The eleventh transistor N11may be connected between the ninth node Q9and the ground terminal Vss and enabled in response to the second control signal CON2.

In example operation, the first latch circuit230may detect output signals V3and V4of the voltage amplifier220and may convert the voltage level of the output signal Vout1to a first (e.g., CMOS) voltage level in response to the second control signal CON2. The first latch circuit230may output the converted output signal Vout1. The first latch circuit230may include a pre-charge circuit (not shown) and may maintain an output signal Vout1at a desired level, for example, a high logic level or “1” during a disable operation.

The seventh transistor P7may be connected between the supply voltage Vdd and a tenth node Q10. The eighth transistor P8may be connected between the supply voltage Vdd and an eleventh node Q11. The twelfth transistor N12and the fourteenth transistor N14may be connected in series between the tenth node Q10and the twelfth node Q12. The thirteenth transistor N13and the fifteenth transistor N15may be connected in series between the eleventh node Q11and the twelfth node Q12.

The gate terminals of the seventh transistor P7and the twelfth transistor N12may be connected to the eleventh node Q11. The gate terminals of the eighth transistor P8and the thirteenth transistor N13may be connected to the tenth node Q10.

The fourteenth transistor N14may be operated in response to the output voltage V2of the first node Q1. The fifteenth transistor N15may be operated in response to the output voltage V1of the second node Q2. The sixteenth transistor N16may be connected between the twelfth node Q12and the ground terminal Vss and enabled in response to a third control signal CON3.

In example operation, the second latch circuit240may detect output signals V1and V2of the current amplifier210and may convert the voltage levels of the output signals V1and V2of the current amplifier210to a first (e.g., CMOS) voltage level in response to the third control signal. The second latch circuit240may output the converted voltage level as output signal Vout2. The second latch circuit240may include a pre-charge circuit (not shown) and may maintain the output signal Vout2at a desired level, for example, a logic high level or “1”, during a disable operation. The first and second latch circuits230and240may be embodied as a cross-coupling-type latch circuit.

The third control signal CON3may be generated based on a second row address signal and a read command. The second row address signal may address word lines in a group located relatively close to the I/O sense amplifier140when the word lines are grouped into at least two groups. For example, the second row address signal may select any one of the word lines of the second group of the word lines shown inFIG. 1.

The output circuit250may receive, logically multiply, and output the output signals Vout1and Vout2from the first and second latch circuits230and240, respectively. The output circuit250may include a NAND gate251and an inverter252. When the level of the output signals change based on operations of the first and second latch circuits230and240, the output circuit250may operate based on the converted value.

Referring toFIGS. 1 through 4, in operation of the I/O sense amplifier according to at least some example embodiments, when the semiconductor memory device100performs a read operation, the I/O sense amplifier140may receive data output from the memory cell array110of the semiconductor memory device100through the global I/O lines DIO/DIOB. The received data signal may be converted to voltage levels V1and V2in response to the first control signal CON1by detecting the difference in the current of the data signal received through the current amplifier210. The converted data signal may be output. A read signal of the semiconductor memory device100may be used as the first control signal CON1.

When the data signal is output, the I/O sense amplifier140may amplify and output an output voltage in response to control signals CON2and CON3generated based on the row address, or convert the output voltage to a first (e.g., CMOS) voltage level through the latch, and output the converted voltage.

When the row address is the first row address signal for reading data from a memory cell array located relatively far from the I/O sense amplifier140, the I/O sense amplifier140may amplify the output voltage of the current amplifier210through the voltage amplifier220. The output signal amplified by the voltage amplifier220may be input to the first latch circuit230, amplified to the CMOS voltage level based on the second control signal CON2, and output as the first output signal Vout1.

Conversely, when the row address is the second row address signal for reading data from a memory cell array located relatively close to the I/O sense amplifier140, the I/O sense amplifier140may disable the voltage amplifier220and the first latch circuit230and may enable the second latch circuit240to convert the output voltages V1and V2amplified by the current amplifier210to the CMOS voltage level and output the converted output voltage.

The I/O sense amplifier140may logically multiply and output the first and second output signals Vout1and Vout2through the output circuit250. Thus, the semiconductor memory device may control operation of the I/O sense amplifier140based on the row address signal. For example, because the operation of the I/O sense amplifier140is controlled based on the length of the I/O data lines IO/IOB connected to the I/O sense amplifier140, unnecessary power consumption may be reduced.

FIG. 5is a circuit diagram of a conventional I/O sense amplifier showing an effect in comparison with example embodiments. Referring toFIG. 5, a conventional I/O sense amplifier300may include a current amplifier310, a voltage amplifier320and a latch circuit330. Because the structure and operation of the I/O sense amplifier300are the same as those of the I/O sense amplifier140ofFIG. 4, the descriptions thereof will be omitted herein for the sake of brevity.

The I/O sense amplifier300may operate in response to a control signal CON. The control signal CON may be generated in response to a read command of the semiconductor memory device100. In this example, all of the current amplifier310, the voltage amplifier320and the latch circuit330may operate simultaneously or concurrently in response to the control signal CON. Thus, even when data located close to the I/O sense amplifier300is received, all the elements of the I/O sense amplifier300may operate so that power is consumed continuously.

By contrast, in the I/O sense amplifier140ofFIG. 4according to at least one example embodiment, the voltage amplifier220and the first latch circuit230may selectively operate according to the row address of the semiconductor memory device100. Thus, power consumption may be less than that of the conventional I/O sense amplifier300.

As described above, according to example embodiments, I/O sense amplifiers and operating methods of the I/O sense amplifier, may have reduced power consumption because the operating mode of the I/O sense amplifier may be selectively changed.

While example embodiments have been particularly shown and described with reference to example embodiments shown in the drawings, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the appended claims.