System and method of calibrating power-on gating window for a time-to-digital converter (TDC) of a digital phase locked loop (DPLL)

A system and method are disclosed related to calibrating a power-on gating window for a time-to-digital converter (TDC) of a digital phase locked loop (DPLL). The gating window is calibrated to ensure proper operation of the DPLL, while at the same time operating the TDC in a power efficient manner. In particular, the technique entails setting the width of the TDC gating window to a default value; operating the DPLL until the control loop is substantially locked; decreasing the width of the TDC gating window by a predetermined amount, while monitoring the phase error signal generated by the phase error device of the DPLL; determining the current width of the TDC gating window at substantially a time when the phase error arrives at or crosses a predetermined threshold; and increasing the current width of the TDC gating window by a predetermined amount to build in a margin of error for the operating width of the TDC gating window.

BACKGROUND

The present disclosure relates generally to phase locked loops (PLL), and in particular, to a system and method of calibrating a power-on gating window for a time-to-digital converter (TDC) of a digital phase locked loop (DPLL).

Communication devices typically include a local oscillator (LO) for synchronously transmitting and receiving signals to and from other remote communication devices. Often these signals are sent or received via defined frequency channels. For selecting a particular frequency channel, the frequency of the LO is typically changed in order to properly transmit or receive the signal via the selected channel. Often a phase locked loop (PLL), such as a digital PLL (DPLL), is used to perform the change in the LO frequency.

A typical DPLL includes several digital devices, such as an input accumulator, a phase error summing device, a low pass filter (LPF) (often referred to as a “loop filter”), a digital controlled oscillator (DCO), a DCO accumulator including a latch, a time-to-digital converter (TDC), a feedback phase summing device, and other digital devices. The input accumulator generates an input phase signal. The phase error summing device generates a phase error signal indicative of a phase difference between the input phase signal and a feedback phase signal. The loop filter generates a control signal for the DCO by filtering the phase error signal. The DCO generates an output signal having a phase related to the input phase signal when the DPLL is locked. The DCO accumulator including the latch generates a signal indicative of a coarse measurement of the phase of the output signal of the DCO. The TDC generates a signal indicative of a fine measurement of the phase of the output signal of the DCO. And, the feedback summing devices sums the coarse and fine phase signals to generate the feedback phase signal.

The TDC typically comprises a chain of delay elements (e.g., inverters), a plurality of D flip-flops, and a decoder. An output clock from or derived from the output signal of the DCO is applied to the input of the chain of delay elements. The delay elements are coupled to the data input of respective D flip-flops. A reference clock is applied to the clock inputs of the D flip-flops. The Q-outputs of the D flip-flops are coupled to inputs of a decoder, such as a thermometer-to-binary decoder. The inverted reference clock is applied to the clock input of the decoder. And, the outputs of the decoder generates a binary output representing the fractional phase of the phase difference between the output clock and the reference clock.

Typically, the frequency of the output is substantially higher than the frequency of the reference clock, e.g., by a factor of 10 or more. Generally, a phase measurement takes place when an edge of the reference clock arrives. Between adjacent edges of the reference clock, the output clock is still being applied to the chain of delay elements. This causes the delay elements to needlessly consume substantial amount of power during times when a phase measurement is not being performed. Accordingly, power-on gating for the TDC has been developed to apply the output clock to the chain of delay elements only a relatively small window around the edge of the reference clock. However, due to variations in manufacturing processes, environment temperatures, and power supply voltages, the proper size for the gating window for operational and power consumption purposes is generally difficult to ascertain.

SUMMARY

A system and method are disclosed related to calibrating a power-on gating window for a time-to-digital converter (TDC) of a digital phase locked loop (DPLL). The gating window is calibrated to ensure proper operation of the DPLL, while at the same time operating the TDC in a power efficient manner. In particular, the technique entails setting the width of the TDC gating window to a default value; operating the DPLL until the control loop is substantially locked; decreasing the width of the TDC gating window by a predetermined amount, while monitoring the phase error signal generated by the phase error device of the DPLL; determining the current width of the TDC gating window at substantially a time when the phase error arrives at or crosses a predetermined threshold; and increasing the current width of the TDC gating window by a predetermined amount to build in a margin of error for the operating width of the TDC gating window.

Another aspect of the disclosure relates to an apparatus comprising a control unit adapted to receive a phase error signal from a phase error device of a phase locked loop (PLL), such as a digital PLL (DPLL), and set the width of a gated clock signal for a time-to-digital (TDC) converter to an operating value based on the phase error signal. In another aspect, the control unit is adapted to set the width of the gated clock signal to a default value, monitor the phase error signal from the phase error device, and decrease the width of the gated clock signal until the phase error signal arrives substantially at or crosses a predetermined threshold. In yet another aspect, the control unit is further adapted to increase the width of the gated clock signal at the time when the phase error signal arrives substantially at or crosses the predetermined threshold in order to provide a margin of error to the operating value of the width of the gated clock signal.

In another aspect of the disclosure, the control unit comprises a first generator adapted to generate a first gating signal, and a second generator adapted to generate a second gating signal, wherein the first and second gating signals include respective edges that control the width of the gated clock signal. In yet another aspect, the control unit comprises logic adapted to generate the gated clock signal from the first and second gating signals and an output clock signal having a phase related to the phase of the output of the DPLL. In still another aspect, the first generator comprises a first chain of delay elements with respective outputs coupled to inputs of a first multiplexer, and wherein the first chain of delay elements is adapted to receive a raw reference clock. In another aspect, the second generator comprises a second chain of delay elements with respective outputs coupled to inputs of a second multiplexer, and wherein the second chain of delay elements is coupled to an output of the first chain of delay elements.

In another aspect of the disclosure, the control unit further comprises a controller adapted to generate a first select signal to cause the first multiplexer to select one of the output signals of the first chain of delay elements as the first gating signal. Similarly, in another aspect, the controller is adapted to generate a second select signal to cause the second multiplexer to select one of the output signals of the first chain of delay elements as the second gating signal. In yet another aspect, the control unit further comprises a first programmable counter adapted to generate the first select signal in response to the controller, and a second programmable counter adapted to generate the second select signal in response to the controller.

The apparatus discussed above may be used in a digital phase locked loop (DPLL). In this regard, the apparatus further comprises a filter adapted to generate an oscillator control signal based on the phase error signal; an oscillator adapted to generate an output signal based on the oscillator control signal, wherein a phase of the gated clock signal is related to a phase of the output signal; a first accumulator adapted to generate a first feedback phase signal related to a coarse phase measurement of the output signal, wherein the TDC generates a second feedback phase signal related to a fine phase measurement of the output signal; a summing device adapted to generate an overall feedback phase signal by combining the first and second feedback phase signals; and a second accumulator adapted to generate an input phase signal, wherein the phase error signal generated by the phase error device is related to a difference between the input phase signal and the overall feedback phase signal.

Other aspects, advantages and novel features of the present disclosure will become apparent from the following detailed description of the disclosure when considered in conjunction with the accompanying drawings.

DETAILED DESCRIPTION

FIG. 1illustrates a schematic/block diagram of an exemplary digital phase locked loop (DPLL)100in accordance with an aspect of the disclosure. In summary, the DPLL provides a technique for calibrating the power-on gating window of a time-to-digital converter (TDC) to achieve proper operation of the DPLL, while at the same time operating the TDC in a power efficient manner. In particular, the technique involves setting the power-on gating window to a default value, operating the DPLL until the control loop is substantially locked, decrementing the power-on gating window while monitoring the phase error signal from the phase error summing device, selecting the current power-on window substantially when the phase error crosses a predetermined threshold, and applying a margin of error to the current power-on window.

More specifically, the DPLL comprises an input accumulator102, a first (phase error) summing device104, a low pass filter (LPF) or loop filter106, a digital controlled oscillator (DCO)108, a frequency divider110, a clock control unit112, a DCO accumulator114including a latch116, a time-to-digital converter (TDC)118, and a second (feedback phase) summing device120.

The input accumulator102receives a PLL input and a reference clock REF2, and generates an input phase signal. In essence, the input accumulator102comprises a counter that counts periods of the reference clock REF2by a number dictated by the PLL input. For example, if the PLL input is 10, then the counter counts by 10 (e.g., 0, 10, 20, 30, etc.). The PLL input is related to the ratio of the frequency of the DCO output to the frequency of the reference clock REF2. For example, if the frequency of the reference clock REF is 100 MHz and the PLL input is 10, then the frequency of the DCO output (when the loop is locked) may be at approximately 1 GHz.

The first (phase error) summing device104receives the input phase signal from the input accumulator102, and a feedback phase signal from the second (feedback phase) summing device120, and generates a phase error signal related to the phase difference between the input phase signal and the feedback phase signal. For timing and error correction purposes, the first summing device104may receive the reference clock REF2. For example, the first summing device104may generate the phase error signal one (1) clock period of the reference clock REF2after it has received the phase signals from the input accumulator102and the second summing device120. Since the frequency, i.e., the clock period, of the REF2clock may be programmed, the first summing device104receives the reference clock REF2for the purpose of setting the proper delay for outputting the phase error signal.

The LPF or loop filter106filters the phase error signal from the first summing device104to generate a frequency control signal for the DCO108. The transfer function of the loop filter106may be dependent on the frequency of the reference clock REF2. Accordingly, the loop filter106also receives the reference clock REF2to inform it of the current frequency of the reference clock REF2. The loop filter106uses this information to adjust its transfer function in accordance with the current frequency of the reference clock REF2.

The DCO110receives the frequency control signal from the loop filter106and the reference clock REF2, and generates the PLL output signal that has a specified phase relationship with the input phase signal when the control loop is locked. Optionally, the frequency divider110may be provided to divide the frequency of the output signal of the DCO108to generate an output clock with reduced frequency to better facilitate processing. The DCO accumulator114generates a signal indicative of a coarse measurement of the phase of the output clock, which is related to the phase of the PLL output signal. In essence, the DCO accumulator114comprises a counter that incrementally counts periods of the output clock. The latch116outputs the coarse phase information in response to a triggering edge of the reference clock REF2.

As discussed in more detail below, the clock control unit112receives the output clock from the frequency divider110and a raw reference clock REF0, and generates the reference clock REF2for the various components of the DPLL and a gated clock for the TDC118. The gated RF clock includes one or more periods of the RF clock signal timely situated on both sides of each triggering edge of the reference clock REF2. The clock control unit112further performs a calibration procedure to determine the width (power-on gating window) of the output clock to ensure proper operation of the DPLL100, while at the same time operating the TDC118in a power efficient manner. In particular, the technique involves setting the power-on gating window to a default value, operating the DPLL100until the control loop is substantially locked, decrementing the power-on gating window while monitoring the phase error signal from the first summing device104, selecting the current power-on window substantially when the phase error signal crosses a predetermined threshold, and applying a margin of error to the current power-on window.

The TDC118generates a signal indicative of a fine measurement of the phase of the output clock, which, as previously discussed, is related to the phase of the PLL output signal. In particular, the TDC118comprises a chain of delay elements that receives the gated clock. The outputs of the delay elements are respectively coupled to the data inputs of D flip-flops. The D flip-flops are clocked by the reference clock REF2. The Q-outputs of the D flip-flops are coupled to a thermometer-to-binary decoder, which generates a signal indicative of the fractional difference between the phase of the RF clock and the reference clock REF2. The power consumption of the TDC118is related to the width of the power-on gating window. Thus, the wider the power-on gating window, the more power the TDC consumes. Conversely, the narrower the power-on gating window, the less power the TDC consumes. Again, as discussed above, the clock control unit112calibrates the width of the power-on gating window to ensure proper operation of the DPLL100, while operating the TDC118in a power efficient manner.

The second summing device120receives the coarse and fine phase signals respectively from the latch116and the TDC118, and generates the feedback phase signal related to the phase of the PLL output signal. For timing and error correction purposes, the second summing device120may receive the reference clock REF2. For example, the second summing device120may generate the feedback phase signal one (1) clock period of the reference clock REF2after it has received the phase information from the latch116and the TDC118. Since the frequency, i.e., the clock period, of the reference clock REF2may be programmable, the second summing device120receives the reference clock REF2to inform it of the current frequency of the reference clock REF2. The second summing device120uses this information to select the proper delay for outputting the feedback phase signal.

FIG. 2illustrates a schematic/block diagram of an exemplary clock control unit200in accordance with another aspect of the disclosure. The clock control unit200is merely one example of a detailed implementation of the clock control unit112previously discussed. In particular, the clock control unit200includes circuitry to generating a gated clock for the TDC118. The clock control unit200further includes circuitry for calibrating the width of the gated clock so as to ensure proper operation of the DPLL100, as well as operate the TDC118in a power efficient manner. Additionally, the same circuitry also produces the reference clock REF2used by many of the components of the DPLL100as previously discussed.

More specifically, the clock control unit200comprises a first chain of delay elements202, a first multiplexer (MUX)204, a second chain of delay elements206, a second MUX208, an inverter210, first and second AND gates212and214, a TDC gating calibration controller216, a first programmable counter218, and a second programmable counter220. The first chain of delay elements202includes an input adapted to receive the raw reference clock REF0. The outputs of the delay elements of the chain202are respectively coupled to inputs of the first MUX204. The second chain of delay elements206is respectively coupled to the output of the first chain of delay elements202either directly or by way of one or more delay elements. The outputs of the delay elements of the chain206are respectively coupled to inputs of the second MUX206.

In response to a selection signal received from the first programmable counter218, the first MUX204selects one of the clock signals from the output of one of the delay elements of the chain202to generate a first gating clock REF1. As discussed in more detail below, an edge (e.g., the rising edge) of the first gating clock REF1defines the beginning of the power-on gating window. Additionally, in response to a selection signal received from the second programmable counter220, the second MUX208selects one of the clock signals from the output of one of the delay elements of the chain206to generate a second gating clock REF3. As discussed in more detail below, an edge (e.g., the rising edge) of the second gating clock REF3defines the end of the power-on gating window. The reference clock REF2for the DPLL may be generated by a delay element between the first and second chains of delay elements202and206. The reference clock REF2may be selected so that its triggering edge lies substantially half way between the edge of the first gating clock REF1and the edge of the second gating clock REF3.

The output of the first MUX204is coupled to an input of the AND gate212, and the output of the second MUX208is coupled to the other input of the AND gate212via the inverter210. The AND gate212produces at its output an ENABLE signal that defines the width of the power-on gating window. For example, the ENABLE signal includes a rising edge that defines the beginning of the power-on gating window, and a falling edge that defines the end of the power-on gating window. The output of the AND gate212is coupled to an input of the AND gate214. The other input of the AND gate214is adapted to receive the output clock from the divider110, or directly from the DCO108is a divider is not used. The ENABLE signal, in essence, gates the output clock so that the gated clock is generated at the output of the AND gate214.

FIG. 3illustrates a timing diagram of exemplary signals generated within the exemplary clock control unit200in accordance with another aspect of the disclosure. The top signal illustrated is the first gating clock REF1, the middle signal illustrated is the reference clock REF2for the DPLL, and the lower signal illustrated is the second gating clock REF3. As the diagram shows, based on the selection implemented by the first MUX204, the timing of the first gating clock REF1may be selectively delayed to define the start of the power-on gating window. In this example, the start of the power-on gating signal is set by the rising edge of the first gating clock REF1. Similarly, based on the selection implemented by the second MUX208, the timing of the second gating clock REF3may be selectively delayed to define the end of the power-on gating window. In this example, the end of the power-on gating signal is set by the rising edge of the second gating clock REF3.

Also, as noted in the diagram, the triggering edge (e.g., the rising edge) of the reference clock REF2may be configured to lie substantially half way between the edge of the first gating clock REF1and the edge of the second gating clock REF2. Additionally noted in the diagram, the maximum gating occurs when the first gating clock REF1is delayed the least, and the second gating clock REF3is delayed the most. Similarly, the minimum gating occurs when the first gating clock REF1is delayed the most, and the second gating clock REF3is delayed the least.

FIG. 4illustrates a flow diagram of an exemplary method400of calibrating a power-on gating window for an exemplary time-to-digital converter (TDC) of the exemplary DPLL in accordance with another aspect of the disclosure. The width of the power-on gating window of the TDC118may be calibrated by the TDC gating controller216per method400. According to the method400, the controller216sets the power-on gating window to a default value (block402). For example, the controller216may set the gating window to the widest gating window provided by the gating clocks REF1and REF3. This may be accomplished by the controller216sending a control signal causing the first programmable counter218to generate a select signal that instructs the first MUX204to select the output of the first delay element (most left delay element) of the chain202, and sending a control signal causing the second programmable counter220to generate a select signal that instructs the second MUX204to select the output of the last delay element (most right delay element) of the chain206.

Then the DPLL100is operated until the control loop is substantially locked (block404). Then, the controller216causes the width of the power-on gating window to decrease by a predetermined amount (block406). This may be accomplished by the controller216sending a control signal causing the first programmable counter218to generate a select signal that instructs the first MUX204to select the output of the next (e.g., the second) delay element of the chain202, and sending a control signal causing the second programmable counter220to generate a select signal that instructs the second MUX204to select the output of the previous (e.g., second to last) delay element of the chain206.

The controller216then monitors the phase error signal generated by the first summing device104(block408). The controller216then compares the phase error with a predetermined threshold (block410). If the controller216determines that the phase error is lower than (e.g., has crossed) the predetermined threshold, then the controller repeats blocks406,408, and410. On the other hand, if the controller216determines that the phase error is greater than the predetermined threshold, the controller216then determines the current width of the TDC gating window (block412). Then, the controller216increases the current width of the TDC gating window to apply a predetermined margin of error (block414). In this manner, the TDC gating window is wide enough to ensure proper operation of the DPLL, and narrow enough to operate the TDC in the power efficient manner. Although, in this example, the clock control unit200included its own calibration controller216, it shall be understood that the controller216may be situated external to the DPLL100, such as a part of a test equipment for calibrating the power-on gating window in a test facility.

FIG. 5illustrates a schematic/block diagram of an exemplary time-to-digital converter (TDC)500in accordance with another aspect of the disclosure. The TDC500is one exemplary detailed implementation of the TDC118previously discussed. In summary, TDC500compares the phase of the gated clock against the phase of the reference clock REF2, and provides the detected phase difference with multiple bits of resolution.

The TDC500includes N delay elements502-1through502-N, D flip-flops504-1through504-N, an inverter506, and a thermometer-to-binary decoder508. Delay elements502-1through502-N are coupled in series, with delay element502-1receiving the gated clock. Each delay element may be implemented with inverters and/or other types of logic elements to obtain the desired delay resolution. Delay elements502-1through502-N may provide a total delay of approximately one output clock cycle. For example, if the output clock frequency is 2 GHz, then one period of the output clock is 500 picoseconds (ps), and each delay element may provide a delay of approximately 500/N ps.

The D flip-flops504-1through504-N have their D inputs coupled to the delay elements502-1through502-N, respectively, and their clock inputs receiving the reference clock REF2. Each D flip-flop samples the input of an associated delay element and provides the sampled output to converter508. The number of D flip-flops at logic high versus the number of D flip-flops at logic low is indicative of the phase difference between the gated clock and the reference clock REF2. This phase difference may have a resolution of 1/N output clock cycle. The inverter506receives the reference clock REF2and provides an inverted reference clock REF2to the decoder508. The decoder508receives the N outputs from D flip-flops504-1through504-N, converts these N outputs to a binary value when triggered by an edge of the inverted reference clock REF2, and provides the binary value as the TDC output.

FIG. 6illustrates a timing diagram of exemplary signals generated within the exemplary time-to-digital converter (TDC) in accordance with another aspect of the disclosure. The output clock and the ENABLE signal are shown at the top of the diagram for reference. The gated clock is shown below the ENABLE signal. The N delayed signals D1through DNfrom delay elements502-1through502-N, respectively, are shown below the gated clock. The D1through DNsignals are latched by the leading edge of the reference clock REF2, which occurs during the power-on gating window defined by the ENABLE. The N latched signals d1through dNfrom D flip-flops504-1through504-N, respectively, are provided to decoder508.

As shown inFIG. 6, the functionality of TDC500is not affected by gating on/off the output clock because the phase information of oscillator108is only needed for a short period of time. The gated clock and the D1through DNsignals are valid for a duration of time around each leading edge of the reference clock REF2. In general, the gated clock may be valid for any number of output clock cycles prior to the leading edge of the reference clock REF2and for any number of output clock cycles after the leading edge, depending on the calibration procedure previously discussed. However, it may be desirable to minimize the number of clock cycles in the gated clock in order to reduce power consumption. The ENABLE signal may be generated to pass only one or two output clock cycles. In one design, the ENABLE signal may pass approximately one output clock cycle prior to the leading edge and approximately one output clock cycle after the leading edge of the reference clock REF2, as dictated by the calibration procedure. By dynamically controlling TDC500and enabling the TDC only when necessary, a large portion (e.g., 90%) of the power may be saved for TDC500.

FIG. 7illustrates a block diagram of an exemplary communication device700, such as a transceiver, in accordance with another aspect of the disclosure. In summary, the transceiver700serves as one exemplary application of the DPLL previously discussed. In particular, the transceiver700includes a DPLL that provides TDC gating for power consumption purposes. The DPLL may further include a device, such as the clock control unit previously discussed, that is capable of calibrating the width of the power-on gating window in order to ensure proper operation of the DPLL, and at the same time, operate the TDC in a power efficient manner as previously discussed.

More specifically, the transceiver700comprises an antenna702, a transmit/receive (TX/RX) isolation device704, a receiver706, a local oscillator (LO)708including a DPLL as previously discussed, and a transmitter712. The antenna702serves to receive radio frequency (RF) signals from one or more remote communication devices via a wireless medium, and to transmit RF signals to one or more remote communication devices via the wireless medium. The TX/RX isolation device704serves to route the received signal to the receiver706, and route the transmit signal to the antenna702while substantially isolating the input of the receiver706from the transmit signal. The receiver706serves to down convert the received RF signal to an intermediate frequency (IF) or baseband signal. The transmitter712serves to up convert an IF or baseband outbound signal to an RF signal. The local oscillator (LO)708including the DPLL as discussed above provides a received local oscillating source LORfor the receiver706so it can perform its down converting function. Similarly, the local oscillator (LO)708provides a transmit local oscillating source LOTfor the transmitter712so it can perform its up converting function. Although the transceiver700is used to exemplify one application of the DPLL, it shall be understood that the DPLL may be used in other applications, such as in a receiver, transmitter, clock and data recovery circuit, etc.