Switch mode voltage rectifier, RF energy conversion and wireless power supplies

Embodiments of the present invention provide cross-coupled rectifiers that use near zero-threshold transistors in a switching topology, but provide a topology that avoids reverse conduction problems. Importantly, preferred embodiment rectifiers of the invention only provide a slightly increased on-resistance in each branch, while providing both very high operating efficiency and very low turn-on voltage. An embodiment of the invention is a voltage rectifier for the conversion of RF energy into DC voltage with a turn-on threshold voltages approaching 0V.

FIELD

A field of the invention is voltage rectifiers. Another field of the invention is RF energy conversion. Example applications of the invention include wireless sensors, wireless power supplies and wireless energy harvesting. Preferred particular applications of the invention include UHF RFID tags and wirelessly powered biomedical implant devices.

BACKGROUND

As wireless biomedical implant devices advance to smaller sizes with higher processing power, the issue of power supply becomes a critical design hurdle. Designers for biomedical devices have turned their attention to sensors that are powered by RF energy that is implanted on or within the skin. The most popular power transfer technique is inductive coupling (near-field) because attenuation in tissue is reduced in comparison to RF (far-field) traveling waves and antenna efficiency is independent of wavelength. Unfortunately, as device (antenna) size decreases power collected by the device falls off in proportion to the mutual inductance squared or R4where R is the radius of the antenna coil. For this reason it is important that the low RF energy levels collected by the antenna are efficiently converted to DC power to operate the implant.

Similarly, efficient energy conversion is important to RFID tags. A highly efficient RFID tag can be powered at a further distance from a reader, for example. Alternatively, a highly efficient RFID tag can be more readily powered by a reader when the tag is embedded in an article or medium that attenuates or absorbs RF energy.

The voltage rectifier is a critical element that affects efficiency of power conversion from AC RF energy to DC energy required for a device such as a medical implant or an RFID tag. Conventional rectifies used in wirelessly powered devices such as UHF RFIDs, micro-sensors and biomedical implants are unfortunately extremely inefficient at low input levels. The inefficiency arises from the threshold voltage (Vth) of devices used within the rectifier, which are generally standard CMOS transistors. If the peak-to-peak RF input voltage swing is below the Vthof the devices used, the rectifier will never turn on and no DC output will be produced. This region is known as the “dead zone” and generally leads to reduced read ranges for wireless devices. See, e.g., S. Mandal and R. Sarpeshkar, “Low-Power CMOS Rectifier Design for RFID Applications,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 54, no. 6. In the case of biomedical implants, by setting the minimum power required for rectifier function, the dead zone will limit the minimum achievable implant size. Low threshold (Vthtypically ˜|0.4V|) Schottky diodes have been used to reduce the dead zone but the threshold of a Schottky diode still presents a significant dead zone due to a threshold that does not approach zero, as reported in U. Karthaus and M. Fisher, “Fully integrated passive UHF RFID transponder IC with 16.7-μW minimum RF input power,” IEEE J. Solid-State Circuits, vol 38, no. 10 pp. 1602-1608, October 2003.

J. Yi, W.-H. Ki; C.-Y. Tsui, “Analysis and Design Strategy of UHF Micro-Power CMOS Rectifiers for Micro-Sensor and RFID Applications,” IEEE Trans. Circuits Syst. 1, Reg. Papers, vol. 54, no. 1, pp. 153-166, January 2007, discloses a charge pump rectifier design that uses advanced process CMOS low or near zero threshold transistors. The charge pump design was reported to achieve a rectifier efficiency of 26.5% at an input power of −11.12 dBm for UHF micro sensor applications. A limitation of the charge pump diode design is that the rectifier's loss over the RF cycle is dependent upon the load.

CMOS coupled designs have advantages over the charge pump diode designs, but artisans have avoided low and near zero threshold transistors because of losses caused by device reverse conduction around zero crossings of the input RF signal.FIG. 1illustrates a cross-coupled bridge rectifier that uses optimized low threshold transistors from “S. Mandal, R. Sarpeshkar, ”Low-Power CMOS Rectifier Design for RFID Applications,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 54, no. 6, As the output voltage increases, a DC offset voltage builds up at the devices gates (between VinRF and ground or VoutDC), this causes the devices to remain on during zero crossings in the RF input cycle leading to reverse conduction and power loss. The threshold voltage of the devices used is set to an optimal value where reverse conduction is minimized and switch on resistance is minimized at the target output voltage. This leads to peak efficiency at a single target output value.

SUMMARY OF THE INVENTION

Embodiments of the present invention provide cross-coupled rectifiers that use near zero-threshold transistors in a switching topology, but provide a topology that avoids reverse conduction problems. Importantly, preferred embodiment rectifiers of the invention only provide a slightly increased on-resistance in each branch, while providing both very high operating efficiency and very low turn-on voltage. An embodiment of the invention is a voltage rectifier for the conversion of RF energy into DC voltage with a turn-on threshold voltages approaching 0V.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Embodiments of the present invention provide cross-coupled rectifiers that use near zero-threshold transistors, but provide a topology that avoids the reverse conduction problem that would arise if such transistors would be used in the topology ofFIG. 1. Importantly, preferred embodiment rectifiers of the invention only provide a slightly increased on-resistance in each branch, while providing both very high operating efficiency and very low turn-on voltage. An embodiment of the invention is a voltage rectifier for the conversion of RF energy into DC voltage with a turn-on threshold voltages approaching 0V. State of the art devices require some minimum voltage application to activate the devices, typically a few hundred millivolts, rendering them insensitive to very small input values. Preferred embodiment voltage rectifiers provide response to very low power RF signals, and have many applications. An example application is a sensing device to monitor very small input values and act upon them, well below the current voltage threshold required by conventional devices.

In general, voltage rectifiers of the invention have application in a device or circuit that responds to RF power, and additional specific applications include very low cost RFID devices and/or increased RFID sensing ranges, bio-medical implants, and devices that can scavenge ambient RF radiation, converting it into DC power to be used as a power source for a portable device such as a wireless (battery based) device.

Preferred embodiment rectifiers of the invention use silicon on insulator near zero-threshold transistors. Alternative near zero-threshold transistors that can be used in the invention include near zero-threshold triple well CMOS transistors and programmable threshold devices.

Unlike theFIG. 1rectifier, embodiments of the invention provide both near zero turn-on voltage with high efficiency. TheFIG. 1design relics on thresholds that raise turn-on voltage to preserve efficiency after turn-on, a compromise which is avoided by rectifiers of the invention.

The CMOS gate cross-connected bridge rectifier stage ofFIG. 1uses low threshold (typically ˜|0.4V|) CMOS devices to maintain efficiency at the expense of higher turn on voltage. InFIG. 1, as VinRF+−VinRF−increases beyond the device threshold, M3and M2will switch on allowing current to flow into the load while M1and M4will remain off. Continuing through the cycle as VinRF+−VinRF−drops below the device threshold M3and M2will turn off and no current will flow to the output until VinRF+−VinRF−becomes more negative then −Vth, at which point M1and M4turn on rectifying the negative half of the incoming RF signal. If the amplitude of VinRFnever achieves a value greater then Vth, Vout DC will be 0V. As a DC voltage develops across the load, the entire structure begins to float, creating a DC offset in the VinRFwaveforms. If the gate to drain voltage exceeds Vth, a channel is formed and current flows to ground, because CMOS devices are symmetric the drain and source have essentially flipped. The low threshold devices are chosen to limit leakage to a small portion of the RF cycle, because leakage can harm efficiency.

Preferred embodiments of the invention will now be discussed with respect to the drawings. The drawings may include schematic representations, which will be understood by artisans in view of the general knowledge in the art and the description that follows. Features may be exaggerated in the drawings for emphasis, and features may not be to scale.

An embodiment of the invention is a CMOS gate cross-connected bridge rectifier10that is shown inFIG. 2A. The rectifier10, rectifies very low input voltages using near zero-threshold transistors M1-M4in a cross-coupled switching arrangement along with near zero-threshold blocking transistors M1.1-M4.1. The CMOS rectifier10ofFIG. 2Ahas a near zero turn on voltage and also efficiently converts very low power RF signals to DC energy. The rectifier10is in a typical application, such as in an RFID connected, connected with terminals12VinRF+−VinRF−directly to an antenna14to receive input RF energy such as from a reader16. Artisans will appreciate that the reader16is frequently distant from the antenna14and can be isolated from the antenna14of the RFID devices by attenuating materials. A load18of the RFID device can be, for example, sensors and circuitry. In other applications, the load18can be biomedical implants and the reader16can both communicate with the load18and provide instructions for operations of the load. Many other applications will be apparent to artisans, and the rectifier10has general applicability in the field of RF powered devices.

Preferred embodiment rectifiers10in accordance withFIG. 2Ause near zero-threshold/native PMOS and NMOS devices to rectify input voltages which approach 0 V. The near zero threshold transistors M1-M4are operated in a switching mode rather than a conventional diode connected configuration to minimize the input voltage necessary to develop a given output voltage. The blocking transistors M1.1-M4.1significantly suppresses shoot through current loss that would otherwise be significant, but the near zero blocking transistors do not add significant threshold M1.1-M4.1and therefore keep turn on voltage near zero. The rectifier10thus provides near zero turn-on voltage of native CMOS devices, the fast turn-on (output vs. input voltage) inherent to switching mode rectifiers and suffers very little from the shoot through leakage often associated with switch mode rectifiers.

Since the rectifier10uses near zero-threshold devices the turn on input voltage at which RF input signals can be converted to useful DC energy to drive the load18is very small. The rectifier10has an architecture not limited by the need to first turn-on to achieve a near zero-threshold state like semi-active threshold canceling rectifier designs. Suppression of leakage current while retaining the low turn-on levels of the near zero-threshold design is achieved with the near zero-threshold blocking transistors M1.1-M4.1. The cross coupled switch includes PMOS near zero-threshold switching transistors MI, M3, and PMOS near zero-threshold blocking transistors M2.1and M4.1, as well as NMOS zero-threshold switching transistors M2, M4, and PMOS near zero-threshold blocking transistors M1.1and M3.1.

During operation after turn-on, branches2and3(through devices M2and M2.1, and M3and M3.1respectively) will be on simultaneously for a portion of the RF cycle while branches1and4are turned off. Next, the roles will be reversed,1and4will be on while2and3will be off. Focusing on the portion of time when1and4should be on, VinRF−−VinRF+must be greater than VinRF+−VoutDCfor energy to flow into the load18. If on the other hand, M1and M4turn on while VinRF−−VinRF+<VoutDCenergy will instead leak from the higher potential load to the lower potential RF inputs and eventually to ground. Referring back toFIG. 1the DC potential at VinRF−and VinRF+is ˜(½)VoutDCas the output drops equally across the devices between the output and the RF inputs (M2, M4) and the devices between the RF inputs and ground (M1, M3). Thus VinRF−−VinRF+can only be greater than VoutDCif VinRF+<0V and VinRF−>V outDCunder all other conditions branches1and4should be completely switched off. Similarly, it can be shown that branches2and3should only conduct when VinRF−<0V and VinRF+>V outDC.

Reverse current blocking operation can be understood by considering branch1and the function of at M1.1when VinRF+−VinRF−=0 and VinRF+, VinRF−>0. The gate to source voltage VGSof M1.1will be >0, thereby turning off M1.1, which stops any current flow through M1to ground. As the overall DC offset level rises M1.1will turn off harder further decreasing leakage current. Thus, as DC offset rises so does the blocking effect of M1.1, which is opposite to the case of theFIG. 1topology, where M1will turn on more strongly as DC offset rises thereby increasing leakage current. Looking to branch4, M4.1will only conduct when VinRF−>V outDC, this ensures no reverse conduction through branch4is possible. Branches2and3perform in an analogous manner. Suppression of reverse current is excellent with low turn on voltage. A penalty of elevated on resistance occurs because there are two devices in series in each conduction path. Specifically, on resistance is increased because the sources of M1.1and M3.1(M2.1and M4.1) (through the load) are connected to ground when their respective current paths are active. Thus, with reference to M1.1VGS=VinRF+which is smaller than VGSof M1inFIG. 1, which is VinRF−−VinRF+. Since the current through the devices is proportional to VGS, the branches in the rectifier10ofFIG. 2Awill turn on less strongly for a given input amplitude than theFIG. 1design. The near zero threshold devices helps keep on resistance down, but theFIG. 2Adevice provides an overall performance improvement even with an increase in on-resistance compared to theFIG. 1device.

Artisans will appreciate that if all of the NMOS transistors are switched for PMOS and vice versa inFIG. 2A, the rectifier will work the same way, except the polarity of the output will be reversed. This embodiment is shown inFIG. 2B, with like elements being labeled as they are inFIG. 2A. Also, in many applications, there will not be a true ground, and ground can float as represented inFIG. 2C. Thus, “ground” as used herein also encompasses the floating ground represented inFIG. 2C.

Simulations were conducted and demonstrated the performance benefits of the rectifier10ofFIG. 2A.FIG. 3shows simulated DC output voltage and power conversion efficiency versus RF input amplitude for single stage rectifiers at 100 MHz into a 30 kΩ load. For the classic design (FIG. 1) and a modified version of theFIG. 1design that uses near zero-threshold transistors, efficiency peaks take place when VoutDCis approximately equal to Vthof the devices used and very little leakage occurs. The benefits of the new design are evident from the simulations, which show that enhanced performance at low input levels provided by the intrinsic devices is retained while the loss at higher input due to reverse leakage is reduced. The effect of the additional on resistance from transistors M1.1-M4.1has only a very minor effect on the performance. At an input RF amplitude of ˜0.55V, the output voltage of the classic design with standard devices exceeds the output voltage of the efficiency enhanced design.FIG. 3shows that the power conversion efficiency (PCE) of theFIG. 1rectifier and its modified version (with near zero-threshold transistors) exceeds that of theFIG. 2Adesigns at their peak values, but the PCE of theFIG. 2Adesign continues to increase as RF input voltage increases while theFIG. 1rectifier and its modified version drops substantially after peaking. Peaks for theFIG. 1and modifiedFIG. 1rectifiers occur at levels where the trade off between output voltage (power) and reverse leakage current is optimal. At these input levels, there is very little reverse leakage and thus the loss due to on resistance is the dominant factor impacting PCE. However, DC offset and reverse current flow then take over and impede efficiency for theFIG. 1and modifiedFIG. 1rectifier. It is also interesting that theFIG. 1and modifiedFIG. 1rectifier are consuming more input power (lower input impedance) at these input voltages than theFIG. 2Adesign. Specifically, far the input voltages (˜100 mV and ˜400 mV) inFIG. 3, the PCE of theFIG. 1and modifiedFIG. 1rectifier peak above the PCE of theFIG. 2Arectifier. Those corresponding peaks inFIG. 4chart do not reach above the PCE of theFIG. 2Arectifier at their respective input powers (˜−22 dBm and −11 dBm). This means that the input impedance of theFIG. 1rectifier and modifiedFIG. 1rectifier is lower than that of theFIG. 2design so a given input voltage occurs at a larger input power. This results inFIG. 2Arectifier having superior efficiency across all input power levels as depicted inFIG. 4. The difference in leakage can be observed by plotting the current through M1(IM1) versus time for the three cases, as shown inFIG. 5, which shows simulated time domain waveforms of the current through transistor M1for single stage rectifiers. The 100 MHz input power was adjusted to achieve equal output voltage (1V) across a 30 kΩ load. TheFIG. 2Arectifier exhibits very low leakage (current into ground or positive current given the polarity of IM1inFIG. 1andFIG. 2A) and thus the rectifier is able to provide the same output power with lower on current. The input power was set in the simulation to insure that the output voltage would be ˜1V for each case. Since the load resistance is the same for each case, the power delivered by each design is equivalent. The simulation shows that theFIG. 2Arectifier greatly reduces reverse conduction leakage (positive current) compared to theFIG. 1design with low threshold transistors or the modifiedFIG. 1design having near zero transistors.

FIG. 6shows a multi-stage rectifier design of the invention that includes a series of n rectifiers101-10nthat are constructed in accordance withFIG. 2A. The multiple rectifiers101-10ncan be used to raise the voltage at the load because later stages float on the DC voltage produced by the earlier stage. The multi-stage rectifier design ofFIG. 6incurs an efficiency penalty compared to the single stage design ofFIG. 2A. However, theFIG. 6design would have significantly higher efficiency than a cascade of theFIG. 1rectifiers. The improved efficiency is particularly important in microwave frequency applications, for example. High frequency signals have shorter wavelengths and thus efficient antenna designs can be physically smaller, which is essential when attempting to scale down the size of a biomedical implant. On the other hand, signal attenuation in biological tissue increases with frequency and the rectifier efficiency and choice of RF wavelength are therefore important.

For the multi-stage rectifier, input impedance can be important to match an antenna to the rectifier. Optimal impedance is dependent on antenna design. The capacitive component of the rectifier input impedance can be absorbed into the capacitor which is used to resonate with the coil antenna. Thus for matching, the imaginary part of Yin can be ignored and only the real part is of importance. For an ideal coil/capacitor combination the real part of Yin is zero, but for realistic micro coils a value on the order of 0.1 mS in the 100 MHz frequency range is typical. This indicates that the parallel input resistance (1/real(Yin)) of the rectifier be on the order of 10 kΩ for maximum power transfer. Coupling capacitors of stages 2-n should be selected to be sufficiently larger than the parasitic capacitance of the transistors to ensure that the RF swing at the input of each stage is not significantly reduced from VinRF. The constraint on making the capacitors too large is that MIM capacitors eat up chip space. Simulations showed that a value of ˜150 fF was optimum for efficiency. The size of the transistors used affects the optimum value of capacitance for efficiency. The coupling capacitors should have a capacitance that is larger than the parasitic capacitance of the transistors in the rectifier.

In a particular design, the number of stages and transistor width affect maximum power conversion efficiency at a predetermined desired power output and input resistance. As the number of stages increases, the amount of loss for a given input power will increase because the number of switching transistors has increased. On the other hand, the ratio VoutDCto VinRFwill increase because of the charge pumping through the stages. Meanwhile, Zin, will decrease because of the higher loss and the additional parallel paths connected to the input. With respect to device size, larger devices have more parasitic capacitance which contributes to switching losses. On the other hand larger W/L devices will have smaller on resistance which will improve efficiency. In the experiments and simulations, PMOS and NMOS devices were sized for equal on resistance WP=2WNand each stage was sized uniformly. Generally, PCE decreases with the number of stages, but device width increases have an effect that is dependent upon the number of stages.

A three stage rectifier structure according toFIGS. 2 and 6has been fabricated and tested. The experimental structure ofFIG. 6was fabricated in Peregrine's silicon on sapphire (SOS) 0.25 um CMOS process in an active area of 88 μm×.74 μm. The particular process used to form the near zero-threshold transistors will determine the value of the near zero-threshold of the devices. In the experimental structure, the native/near-zero threshold devices had a threshold of about 50 mV. In addition, a multi-stage structure for theFIG. 1rectifier and aFIG. 1modified rectifier (having near zero-threshold transistors) were also fabricated and tested in different areas of the same die.FIG. 7shows the measured DC output voltage versus RF input voltage from the fabricated three-stage rectifiers at 100 MHz. The experimentally measured data highlights the fact that the rectifier ofFIG. 2Ais clearly superior across all input and output voltages and provides a particular advantage at lower output voltages. In general, theFIG. 6rectifier provides the best performance across all input levels including the target 1V output. The design based uponFIG. 1with low threshold devices achieves a slightly higher VoutDCat VinRF0.5V than theFIG. 2A & 6rectifier. At this point, theFIG. 1exhibits very little leakage and the lower on resistance of the branches slightly improves performance, but performance of theFIGS. 2A and 6rectifier is better at the target 1V output and there is also a much lower turn-on voltage.

TheFIG. 1rectifier with Vth=400 mV achieves the target VoutDC=1V at Vin=0.45V. The modified rectifier achieves the target 1V it at 0.79V, and theFIG. 2Arectifier achieves it at 0.42V. More impressive is the great improvement in PCE as shown inFIGS. 3 and 4. For PCE at the target 1V output, theFIG. 1with Vth=400 mV achieves a simulated PCE of 59.6%, theFIG. 1modified rectifier achieves a simulated PCE of 31.76% and the FIG.2A/6rectifier achieves simulated PCT of 71.5%.

The chip was tested on a microprobe station. The differential input signal was supplied by a 4-port vector network analyzer, which has the ability to send true differential signals while simultaneously measuring balanced S-parameters. This permitted measurement of the differential input impedance of the rectifier across power and frequency. The differential input impedance of the rectifier varies with frequency and to a lesser extent input power. To ensure that the input voltage could be accurately measured, a 100Ω resistor was included on chip across the differential input. The output was measured using a multimeter across a 1 MΩ load used to simulate a μW biomedical implant chip (1 μW at 1V). The load resistor was approximately 1.1 MΩ such that the combined impedance of the multimeter (input impedance 10 MΩ) and the load resistor was 1 MΩ. Measured results match quite well with simulations. A discrepancy at low input powers is due to the fact that the output voltage and the differential S-parameters were hard to accurately measure at such low levels given the limitations of the test equipment used. At higher input powers the simulation slightly over-predicts the PCE, which can be attributed to deficiencies in the compact models used. From simulations, peak PCE is expected to occur for theFIG. 2Arectifier when the devices are operating very close to breakdown.

FIG. 8shows power conversion efficiencies (some of the data is simulated as circuits were not fabricated for theFIG. 1and modifiedFIG. 1circuits without the shunt 100Ω input resistor). Generally, theFIGS. 2A and 6rectifier provide high efficiency over a wide power range, while the rectifies ofFIG. 1and a modified version with the near zero-threshold transistors is efficient in a very limited input power range. In real world applications, input power range can vary significantly, so theFIG. 2AandFIG. 6rectifier provides superior performance. TheFIG. 2AandFIG. 6design also maintained a ˜1V output at input frequencies as high as 10 GHZ, though PCE starts to suffer after 1 GHZ due to switching losses that occur at higher frequencies.