DMA engine for fetching words in reverse order

Presented herein is a direct memory access engine for providing data words in the reverse order. The data words are fetched in batches comprising a predetermined number of data words starting from the last data word and proceeding to the first data word. The batches are stored in a local buffer. The contents of the local buffer are transmitted in reverse order.

FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

BACKGROUND OF THE INVENTION

The MPEG-2 standard uses video packets comprising any number of macroblocks to confine bit errors. Frames are represented by a set of macroblocks. The macroblocks are grouped into a data structure known as a video packet. In MPEG-2, all macroblock rows start with a new video packet. During the decoding of a video packet, if an error is encountered, the video decoder can simply drop the remaining macroblocks that followed the bit error. In this manner, only a small amount of information is lost as a result of the bit error.

MPEG-4 Part 2 also uses video packets to confine bit errors. The video data is transmitted as a video elementary stream. The portions of the video elementary stream that are at the video packet level and lower are encoded with a variable length code. In MPEG-4 Part 2, the video packet is defined such that the video packet can be decoded in a forward order, or the reverse order. Accordingly, after encountering an error, the video decoder can go to the end of the video packet, and start decoding in the reverse order, until the same error, or another error is encountered. In this manner, a greater portion of the video packet is recovered and reconstructed, in spite of encountering error(s).

To take advantage of the foregoing feature, the video decoder needs to be able to receive and decode the video bitstream in reverse order in real-time. During the decoding, the video elementary stream is stored in a memory known as the compressed data buffer in the forward order, along with a table that indicates the starting addresses of each video packet. The video decoder receives and decodes the video elementary stream by accessing the compressed data buffer. Upon encountering an error, the video decoder can receive the video packet at the ending address of the video packet and moving in the reverse order.

Receiving the video packet in reverse order can be made possible by manipulating the memory access. For example, the video decoder can sequentially access data words in reverse order. After accessing each data word, the video decoder can use logic to reverse the bit order of the data word. However, the foregoing adds significant operations to the video decoder and makes accessing and decoding in the reverse order difficult to perform in real-time.

Further limitations and disadvantages of conventional and traditional systems will become apparent to one of skill in the art through comparison of such systems with the invention as set forth in the remainder of the present application with reference to the drawings.

BRIEF SUMMARY OF THE INVENTION

Presented herein is a direct memory access engine for fetching words in reverse order. In one embodiment, there is presented a method for providing a plurality of sequential data words. The method includes receiving a command to provide the plurality of sequential data words, wherein the plurality of sequential data words comprises a first data word and a last data word, and one or more data words between the first data word and the last data word, fetching a sequential portion of the sequential data words, said sequential portion comprising a first intermediate word, the last word, and one or more data words between the intermediate word and the last word, storing the sequential portion, transmitting at least a portion of the last data word, and transmitting at least a portion of the intermediate data words after transmitting at least the portion of the last data word.

In another embodiment, there is presented a system for providing a plurality of sequential data words. The system comprises a state logic machine, a memory controller, a local buffer, and a port. The state logic machine receives a command to provide the plurality of sequential of sequential data words, wherein the plurality of sequential data words comprises a first data word and a last data word, and one or more data words between the first data word and the last data word. The memory controller fetches a sequential portion of the sequential data words, said sequential portion comprising a first intermediate word, the last word, and one or more data words between the intermediate word and the last word. The local buffer stores the sequential portion. The port transmits at least a portion of the last data word and transmits at least a portion of the intermediate data words after transmitting at least the portion of the last data word.

In another embodiment, there is presented a system for decoding a video packet. The system comprises a compressed data buffer, a video decoder, and a direct memory access engine. The compressed data buffer comprises a plurality of sequential data words. The plurality of sequential data words store a video packet. The video decoder decodes the video packet. The direct memory access engine provides the video packet to the video decoder and comprises a state logic machine, a memory controller, a local buffer, and a port. The state logic machine receives a command to provide the plurality of sequential data words and a control signal indicating reverse order from the video decoder, wherein the plurality of sequential data words comprises a first data word and a last data word, and one or more data words between the first data word and the last data word. The memory controller fetches a sequential portion of the sequential data words, said sequential portion comprising a first intermediate word, the last word, and one or more data words between the intermediate word and the last word. The local buffer stores the sequential portion. The port transmits at least a portion of the last data word and transmits at least a portion of the intermediate data words after transmitting at least the portion of the last data word.

These and other advantages and novel features of the present invention, as well as details of illustrated embodiments thereof, will be more fully understood from he following description and drawings.

DETAILED DESCRIPTION OF THE INVENTION

Referring now toFIG. 1, there is illustrated a block diagram describing MPEG formatting of video data305. The video data305comprises a series of frames310. Each frame comprises two dimensional grids of luminance Y, chroma red Cr, and chroma blue Cb pixels. The two-dimensional grids are divided into 8×8 blocks335, where four blocks335of luminance pixels Y are associated with a block335of chroma red Cr, and a block335of chroma blue Cb pixels. The four blocks of luminance pixels Y, the block of chroma red Cr, and the chroma blue Cb form a data structure known as a macroblock337. The macroblock337also includes additional parameters, including motion vectors.

The macroblocks337representing a frame are grouped into different video packets340. The video packet340includes the macroblocks337in the video packet340, as well as additional parameters describing the video packet. Each of the video packets340forming the frame form the data portion of a picture structure345. The picture345includes the video packets340as well as additional parameters. The pictures are then grouped together as a group of pictures350. The group of pictures350also includes additional parameters. Groups of pictures350are then stored, forming what is known as a video elementary stream355. The video elementary stream355is then packetized to form a packetized elementary sequence. Each packet is then associated with a transport header, forming what are known as transport packets. The transport packets can be multiplexed with other transport packets carrying other content, such as another video elementary stream355or an audio elementary stream. The multiplexed transport packets from what is known as a transport stream. The transport stream is transmitted over a communication medium for decoding and presentation.

The foregoing provides the data words505(x) . . .505(n) as a set of 32 bit words starting from the last portion of505(n) and proceeding sequentially to the first portion of505(x). The bits forming the 32-bit words can be reversed with respect to one another, in any number of ways. For example, the MPEG video decoder445can include logic that reverses the 32 bits of each word. Alternatively, the DMA engine510can include additional circuitry550that causes the 32 bits of each word611to be provided to the MPEG video decoder445in the reverse order.

Referring now toFIG. 2, there is illustrated a block diagram of an exemplary decoder400for decoding compressed video data, configured in accordance with an embodiment of the present invention. A processor, that may include a CPU490, reads a stream of transport packets (a transport stream) into a transport stream buffer432within an SDRAM430.

The data is output from the transport stream presentation buffer432and is then passed to a data transport processor435. The data transport processor then demultiplexes the MPEG transport stream into its PES constituents and passes the audio transport stream to an audio decoder460or SPDIF Generator470and the video transport stream to a video transport processor440.

The video transport processor440converts the video transport stream into a video elementary stream and provides the video elementary stream to an MPEG video decoder445that decodes the video. The video elementary stream355is stored in a compressed data buffer (CDB)447. The MPEG video decoder445accesses the compressed data buffer (CDB) to receive the video elementary stream355. The video elementary stream355is decoded by the MPEG video decoder445resulting in the reconstructed video data305.

The audio data is sent to the output blocks and the video data305is sent to a display engine450. The display engine450is responsible for and operable to scale the video picture, render the graphics, and construct the complete display among other functions. Once the display is ready to be presented, it is passed to a video encoder455where it is converted to analog video using an internal digital to analog converter (DAC). The digital audio is converted to analog in the audio digital to analog converter (DAC)465.

Referring now toFIG. 3, there is illustrated a block diagram describing an exemplary compressed data buffer447. The compressed data buffer447includes any number of data words505(1) . . .505(m). The data words can have any width. In an exemplary case, for example, the data words can comprise 256 bit jumbo words (words).

The compressed data buffer447stores the video elementary stream355. The video elementary stream355comprises any number of video packets340. The video packets340further comprise a video packet header and any number of macroblocks337. The compressed data buffer447also stores a start code table507. The start code table507associates each video packet340with its starting address in the compressed data buffer447. Alternatively the video packet340can be first scanned forward, without evacuating data from memory, then number of bytes/bits can be counted, and then returned using the DMA engine.

The MPEG video decoder445receives the video packets340from the video elementary stream355and decodes the video packets340. The video packet340is received and decoded by the MPEG video decoder445starting from the word505(x) storing the beginning of the video packet340, and proceeding to the word505(n) storing the end of the video packet340.

A direct memory access (DMA) engine510facilitates receipt of the video packets340by the MPEG video decoder445. Alternatively, a processor can facilitate receipt of the video packets340. Accordingly, DMA engine510shall be interpreted to also include a processor that is operable to fetch video packets from memory. The MPEG video decoder445receives a video packet340by looking up the starting address and the ending address of a video packet340in the start code table507. The MPEG video decoder445can then command the DMA engine510to fetch the words505(x) . . .505(n) that store the video packet340. Responsive thereto, the DMA engine510fetches and provides the words505(x) . . .505(n) that store the video packet340.

The DMA engine510provides the words505(x) . . .505(n) to an extractor515within the MPEG video decoder445in a serial manner, beginning with word505(x) and proceeding to the last word505(n). The MPEG decoder445decodes the video packet340, in a serial manner, beginning decoding with the first word505(x) and proceeding to the last word505(n). The extractor515and the DMA engine510operate in conjunction with each other, such that the words505are provided to the MPEG video decoder445at a dynamic rate that is in substantial relationship to the rate that the MPEG video decoder445is decoding the words505.

In MPEG-4 PART 2, the video packet340is defined such that the video packet340can be decoded in a forward order, or the reverse order. Accordingly, if the MPEG video decoder445encounters an error, the video decoder can go to the end of the video packet340, and start decoding in the reverse order. For example, if the MPEG video decoder445decodes the video packet340beginning with the first word505(x), and encounters an error in word505(x+5), the MPEG video decoder445can start decoding the video packet340from word505(n) and decode in the reverse order, e.g., word505(n−1),505(n−2) . . . , etc.

Upon detecting an error, the MPEG video decoder445transmits a command to the DMA engine510to fetch the words storing the video packet340, e.g., words510(x) . . .510(n), along with a reverse order signal. Responsive thereto, the DMA engine510provides the words510(x) . . .510(n) in the reverse order to the MPEG video decoder445.

Referring now toFIG. 4, there is illustrated a block diagram describing an exemplary DMA engine510in accordance with an embodiment of the present invention. The DMA engine510comprises a state logic machine605, a local buffer610, and a memory controller620. The local buffer610can comprise any amount of memory with any width of data words. For example, in an exemplary case, the memory can comprise 128 32-bit words611(0) . . .611(127).

The state logic machine605receives a command to fetch data words in an address range, e.g.,505(x)-510(n) from the MPEG video decoder445. The command can be accompanied by a control signal indicating that the data words in the address range are to be provided to the MPEG video decoder445in the reverse order, e.g.,505(n),505(n−1) . . .505(x).

Responsive to receiving a command to fetch the data words510(x)-510(n) in the reverse order, the state logic machine605commands the memory controller620to retrieve a batch comprising a the last predetermined number of data words505in the provided address range, and store the predetermined number of data words in the local buffer610. The predetermined number of data words in the batch is less than or equal to the capacity of the local buffer610. For example, in an exemplary embodiment, where the local buffer610comprises 128 32-bit words, the batch of data words505can include the last 16 words in the provided address range, e.g., data words505(n−15) . . .505(n).

After the batch of data words505(n−15) . . .505(n) is stored in the local buffer610, the state logic machine605causes the contents of the local buffer610to be provided to the MPEG video decoder445beginning with word611(127), and proceeding sequentially to word611(0). After the contents of the local buffer610, e.g., words611(127) . . .611(0), are provided to the MPEG video decoder445, the state logic machine605commands the memory controller620to fetch another batch comprising the predetermined number of words, e.g., data words505(n−31) . . .505(n−16), that precede the most recently fetched data words, e.g., data words505(n−15) . . .505(n). The data words505(n−15) . . .505(n) are stored in the local buffer610and provided to the MPEG decoder445.

The foregoing is repeated until the next predetermined number of data words comprises the first data word in the address range, e.g., data word505(x). Where a batch comprises the first data word in the address range, e.g., data word505(x), the state logic machine605truncates that portion of the predetermined number of data words that precedes the first data word505(x), and commands the memory controller620to fetch the truncated batch comprising the first data word505(x) and all data words505(x+1),505(x+2) . . . , following the first data word505(x) that have not been previously transmitted to the MPEG video decoder445.

The foregoing provides the data words505(x) . . .505(n) as a set of 32 bit words starting from the last portion of505(n) and proceeding sequentially to the first portion of505(x). The bits forming the 32-bit words can be reversed with respect to one another, in any number of ways. For example, the MPEG video decoder445can include logic that reverses the 32 bits of each word. Alternatively, the DMA engine510can include additional circuitry that causes the 32 bits of each word611to be provided to the MPEG video decoder445in the reverse order.

Referring now toFIG. 5, there is illustrated a flow diagram for providing a video packet in a reverse order. At705, the state logic machine605receives a command to fetch data words in an address range, e.g.,505(x)-510(n), from the MPEG video decoder445, accompanied by a control signal indicating that the data words in the address range are to be provided to the MPEG video decoder445in the reverse order, e.g.,505(n),505(n−1) . . .505(x).

Responsive to receiving the command, the state logic machine605determines (706) if a predetermined number of words comprises the first word,505(x). Where the predetermined number of words comprises the first data word in the address range, e.g., data word505(x), the state logic machine605truncates that portion of the predetermined number of data words that precedes the first data word505(x) and commands (708) the memory controller620to fetch (709) the truncated batch comprising the first data word505(x) and all data words505(x+1),505(x+2) . . . , following the first data word505(x) that have not been previously transmitted to the MPEG video decoder445. Where during706, the state logic machine605determines that the predetermined number of words does not comprise the first word,505(x), the state logic machine605commands (710) the memory controller620to fetch (715) a batch comprising the last predetermined number of data words505in the provided address range.

The fetched data words505are stored (720) in the local buffer610. After the data words are stored in the local buffer610, the state logic machine605causes the contents of the local buffer610to be provided (725) via port560to the MPEG video decoder445beginning with word611(127), and proceeding sequentially to word611(0). After the contents of the local buffer610, e.g., words611(127) . . .611(0), are provided to the MPEG video decoder445, a determination (730) is made whether the first data word, data word505(x) has been provided to the MPEG video decoder445. If the first data word has not been provided to the MPEG video decoder at730, the next batch if prepared at735, and705-730are repeated. If the first data word has been provided to the MPEG video decoder at730, the process is completed.