Semiconductor device with nanostructures aligned with grating coupler and manufacturing method thereof

A semiconductor device includes a photonic die and an optical die. The photonic die includes a grating coupler and an optical device. The optical device is connected to the grating coupler to receive radiation of predetermined wavelength incident on the grating coupler. The optical die is disposed over the photonic die and includes a substrate with optical nanostructures. Positions and shapes of the optical nanostructures are such to perform an optical transformation on the incident radiation of predetermined wavelength when the incident radiation passes through an area of the substrate where the optical nanostructures are located. The optical nanostructures overlie the grating coupler so that the incident radiation of predetermined wavelength crosses the optical die where the optical nanostructures are located before reaching the grating coupler.

BACKGROUND

Semiconductor devices and integrated circuits used in a variety of electronic apparatus, such as cell phones and other mobile electronic equipment, are typically manufactured on a single semiconductor wafer. The dies of the wafer may be processed and packaged with other semiconductor devices or dies at the wafer level, and various technologies and applications have been developed for wafer level packaging. Integration of multiple semiconductor devices has become a challenge in the field.

DETAILED DESCRIPTION

FIG. 1AtoFIG. 1Dare schematic cross-sectional views illustrating a manufacturing process of an optical die100according to some embodiments of the disclosure. InFIG. 1A, a substrate102is provided. In some embodiments, the substrate102may be in wafer form, and multiple optical dies100may be simultaneously fabricated. For example, different die unit regions U1of the substrate102correspond to different optical dies100. While inFIG. 1Ais illustrated a single die unit region U1, the disclosure does not limit the number of die unit regions U1included in the substrate102.

The material of the substrate102is not particularly limited, and may be, for example, a material capable of transmitting radiation of at least one wavelength of interest. For example, a transmittance of the substrate102at the wavelength of interest may be 50% or more, such as 85% or more. For example, the transmittance of the substrate102may be in the range from 50% to 99%. In some embodiments, the wavelength of interest may fall in any useful region of the electromagnetic spectrum, such as in the ultraviolet (e.g., below 400 nm) and its sub-ranges such as the UV-A range, (e.g., between 315 nm to 400 nm) or the UV-B range (e.g., between 234 nm to 315 nm), in the visible (e.g., between 400 nm to 750 nm), or in the infrared (e.g., between 750 nm up to about 1 mm) and its sub-ranges such as infrared-A (e.g., up to 1400 nm), infrared-B (between 1400 nm to 3000 nm), and infrared-C (e.g., between 3000 nm to 1 mm). In some embodiments, the wavelength of interest may be more than a single wavelength, and such multiple individual wavelengths may fall in one or more of the above ranges. For example, the wavelength of interest may fall in the infrared-B and/or infrared-C range, and a material such as silicon may be used for the substrate102. In some embodiments, the material of the substrate102includes one or more semiconductor materials, which may be elemental semiconductor materials, compound semiconductor materials, or semiconductor alloys. In some examples, the elemental semiconductor may include Si or Ge, and the compound semiconductor materials and the semiconductor alloys may respectively include SiGe, SiC, SiGeC, a III-V semiconductor, or a II-VI semiconductor. The III-V semiconductor includes materials such as GaN, GaP, GaAs, AlN, AlP, AlAs, InN, InP, InAs, GaNP, GaNAs, GaPAs, AlNP, AlNAs, AlPAs, InNP, InNAs, InPAs, GaAlNP, GaAlNAs, GaAlPAs, GaInNP, GaInNAs, GaInPAs, InAlNP, InAlNAs, or InAlPAs. The II-VI semiconductor include materials such as CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, HgS, HgSe, HgTe, CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, CdZnS, CdZnSe, CdZnTe, CdHgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, HgZnTe, CdZnSeS, CdZnSeTe, CdZnSTe, CdHgSeS, CdHgSeTe, CdHgSTe, HgZnSeS, HgZnSeTe, or HgZnSTe. In some alternative embodiments, the material of the substrate102includes a dielectric material. For example, the substrate102may be an inorganic substrate, including silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, siliconcarbooxynitride, a combination thereof, or the like. In some embodiments, organic dielectrics (e.g., polymers such as polyimide, epoxy resin, acrylic resin, phenol resin, benzocyclobutene (BCB), polybenzoxazole (PBO), a combination thereof, or the like) may also be selected for the substrate102. In some embodiments, the material of the substrate102may be selected based on its refractive index at the wavelength of interest. For example, the refractive index of the material of the substrate102may be greater than 1 or 1.5, such as greater than 2 or even greater than 3.

In some embodiments, a bonding layer103is formed on a surface102aof the substrate102. The bonding layer103may include an inorganic material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, siliconcarbooxynitride, a combination thereof, or the like. In some embodiments, the inorganic material can include a silicate, such as tetraethylorthosilicate (TEOS) oxide, or plasma enhanced TEOS (PETEOS) oxide. In some embodiments, the bonding layer103may be formed according to any suitable technique, such as by sputtering, spin-coating, or the like. For example, the bonding layer103may be formed by PVD, CVD, ALD, or the like.

InFIG. 1B, a patterned mask104is formed on a surface102bof the substrate102opposite to the surface102awhere the bonding layer103has been formed. In some embodiments, the patterned mask104includes a positive or a negative photoresist, and is formed, for example, through a sequence of deposition (e.g., spin on), exposure, and development steps. In some embodiments, the patterned mask104is patterned to form a plurality of patterning microstructures106. The patterning microstructures106may be formed in a selected region of the patterned mask104, and portions of the substrate102are exposed by gaps existing in between adjacent patterning microstructures106.

InFIG. 1C, the pattern of the patterning microstructures106is transferred to the substrate102, from the side of the surface102b. For example, one or more etching steps may be performed to remove exposed portions of the substrate102in between the patterning microstructures106. The etching may be any acceptable etch process, such as wet or dry etching, a reactive ion etch (RIE), neutral beam etch (NBE), the like, or a combination thereof. The etching may be anisotropic. In some embodiments, the etch is performed so that optical nanostructures108are formed on the side of the surface102bof the substrate102, protruding from a bulk substrate layer S102of the substrate102. That is, the etching conditions may be selected so that the bulk substrate layer S102of the substrate102remains underneath an optical layer O102in which the optical nanostructures108are formed. For example, the optical nanostructures108may be defined by forming blind holes in the substrate102.

Referring toFIG. 1CandFIG. 1D, the photoresist mask104is removed, for example via ashing or stripping, to expose again the surface102bof the substrate102. After removal of the photoresist mask104, the optical dies100may still be in wafer form, corresponding to different die unit regions U1of the substrate102. As illustrated inFIG. 1D, an optical die100includes an optically active area109in which the optical nanostructures108are located. The optical nanostructures108may be formed so that radiation incident on the optically active area109undergoes a desired optical transformation. For example, the optical nanostructures108of the optically active area109may be formed such that radiation incident on the optically active area109from the side of the surface102bis focused upon passing through the optical die100. That is, the optically active area109may have a lensing effect on incident radiation of selected wavelength, so that the optically active area109may act as a lens of a certain focal length for the incident radiation. While lensing has been described as an example, the disclosure is not limited thereto, and other optical effects or combinations thereof may be implemented by tuning the position and the shape of the optical nanostructures108to define the pattern of the optically active area109. For example, the optically active area109may have a lensing effect, a polarizing effect (e.g., half-wave, quarter-wave, full-wave, multi-order, zero-order, etc.), a filtering effect (e.g., monochromatic or polychromatic, long-pass, band-pass, short-pass, etc.), a combination thereof, or the like.

The pattern formed by the optical nanostructures108(and, hence, the optical transformation effect on the incident radiation) may be determined by tuning the formation conditions of the optical nanostructures108, such as the pattern of the patterning microstructures106, the type of etching performed, the etchant mixture used, and so on. For example, changes in the pattern of the optical nanostructures108may be realized by tuning the etching depth through control of the reaction time, thus determining the height H108of the optical nanostructures108(or, equivalently, the height of the optical layer O102). In some embodiments, the height H108of the optical nanostructures108may be in the range from about 50 nanometers to a few micrometers (e.g., up to about 10 micrometers). In some embodiments, the height H108of the optical nanostructures108may be selected according to the dielectric constant of the material constituting the optical layer O102in which the optical nanostructures108are formed. As a way of example and not of limitation, when the optical layer O102is made of silicon, the height H108of the optical nanostructures108may be 1 micrometer or less, for example down to 50 nanometers or even less as long as the desired optical effect can be achieved; when the optical layer O102is made of silicon nitride, the height H108of the optical nanostructures108may be in the range from about 1 micrometer to about 3.5 micrometers; and when the optical layer O102is made of oxide (e.g., silicon oxide), the height H108of the optical nanostructures108may be in the range from about 3 micrometers to about 5 micrometers. Other structural parameters of the pattern of optical nanostructures108may also be varied, such as the distance D108or the pitch P108between adjacent optical nanostructures108. The distance D108may be the distance separating facing sidewalls S108of adjacent optical nanostructures108, while the pitch P108may be the distance between corresponding sidewalls S108of adjacent optical nanostructures108. In some embodiments, the distance D108and the pitch P108may be selected so that the optical nanostructures108form a photonic crystal structure, for selecting or otherwise transforming the incident radiation.

In some embodiments, the shape of the optical nanostructures108can also be selected according to the application requirements, as shown in the examples illustrated in the insets ofFIG. 1D. For example, the optical nanostructures108A have substantially straight sidewalls S108(e.g., perpendicular with respect to the surface of the bulk substrate layer S102), resulting in a rectangular profile. In some embodiments, the optical nanostructures108A may be square or rectangular pillars, or elongated cuboids (depending on the aspect ratio of the side surfaces). In some alternative embodiments, the sidewalls S108may be tapered with respect to the top surface T108, as illustrated for the optical nanostructures108B. The tapering angle α is not particularly limited. In some embodiments, the tapering angle α may be greater than 90 degrees, such as up to 125 or 150 degrees. For example, the optical nanostructures108B may have the shape of truncated pyramids or cones, or may be elongated trapezoidal prisms. In some alternative embodiments, the top surface T108of the optical nanostructures108may be as small as to substantially coincide with a shared edge or corner between adjacent or opposite sidewalls S108, as illustrated, for example, for the optical nanostructures108C. In some embodiments, the optical nanostructures108C may have the shape of cones, pyramids, or elongated triangular prisms. In some alternative embodiments, the top surface T108may be rounded, as illustrated for the optical nanostructures108D. The sidewalls S108may be substantially straight (as for the optical nanostructures108D), tapered (as for the optical nanostructures108B,108C), bell-shaped (as illustrated for the optical nanostructures108E), or of any other suitable profile. In some embodiments, individual optical nanostructures108formed in the optically active area109may have different shapes with respect to each other, so that in the optically active area109may be included any suitable combination of the optical nanostructures108A-108E. It will be apparent that the shapes discussed above for the optical nanostructures108A-108E are non-limiting examples, and that other shapes for the optical nanostructures108are contemplated within the scope of the disclosure. Based on the above, the optical nanostructures108may be considered columnar formations formed in the optical layer O102, in at least some embodiments protruding from the bulk substrate layer S102of the substrate102.

FIG. 2AtoFIG. 2Nare schematic cross-sectional views illustrating structures formed during a manufacturing process of a semiconductor device SD10according to some embodiments of the disclosure. InFIG. 2A, a substrate110is provided. In some embodiments, the substrate110is a semiconductor-on-insulator wafer, including a bulk semiconductor layer122, an insulator layer124, and a front semiconductor layer126sequentially stacked. In some embodiments, the thickness T122of the bulk semiconductor layer122is larger than the thickness T126of the front semiconductor layer126, so as to facilitate handling of the substrate110. Both thicknesses T122and T126are measured along a stacking direction of the layers. The bulk semiconductor layer122and the front semiconductor layer126independently include one or more semiconductor materials, which may be elemental semiconductor materials, compound semiconductor materials, or semiconductor alloys, as described above for the substrate102(illustrated inFIG. 1A). In some embodiments, the bulk semiconductor layer122and the front semiconductor layer126include the same material.

The insulator layer124separates the front semiconductor layer126from the bulk semiconductor layer122. The insulator layer124has a first surface124iin contact with the bulk semiconductor layer122and a second surface124iiopposite to the first surface124ifacing the front semiconductor layer126. In some embodiments, the second surface124iiis in contact with the front semiconductor layer126. In some embodiments, the insulator layer124includes dielectric materials. For example, the insulator layer124may include an oxide such as silicon oxide, and may be referred to as a buried oxide layer (BOX). In some embodiments, the substrate110may be prepared according to any one of a number of suitable approaches. For example, oxygen ions may be implanted in a semiconductor wafer, followed by an annealing step to repair damages which the implantation stage may have caused. Alternatively, a first semiconductor wafer may be bonded to an oxidized surface of a second semiconductor wafer. The first semiconductor wafer may be subsequently thinned to the desired thickness, for example through a sequence of grinding and polishing steps. Alternative processes, for example involving combinations of wafer bonding, splitting, and/or ion implantation are also possible, and are contemplated within the scope of the disclosure.

In some embodiments, the substrate110is in wafer form. That is, different regions of the wafer may correspond to different device unit regions U2, so that multiple device unit regions U2may be simultaneously manufactured from the same wafer. In the drawings, an individual device unit region U2is shown for illustration purposes, however, multiple device unit regions U2may be formed in the substrate110, and processed together with wafer-level technology.

Referring toFIG. 2AandFIG. 2B, the front semiconductor layer126is patterned to form several devices, such as at least one grating coupler132, one or more waveguide patterns134, and one or more optical devices136(e.g. modulators, detectors, multiplexers, demultiplexers, etc.). One or more ion implantation processes may also be performed in one or more regions of the front semiconductor layer126to form the optical devices136. Inactive portions of the front semiconductor layer126may also remain on the insulator layer124, separated from the devices132,134,136.

InFIG. 2C, one or more insulating materials (e.g., oxides) are disposed on the patterned front semiconductor layer126to blanketly cover the patterned front semiconductor layer126. In some embodiments, the grating coupler132, the waveguide pattern(s)134, and the optical device(s)136are buried underneath the dielectric layer140. In some embodiments, the dielectric layer140includes an oxide such as silicon oxide.

InFIG. 2D, through-semiconductor holes150are formed in the bulk semiconductor layer122, extending through the dielectric layer140and the insulator layer124. In some embodiments, the through-semiconductor holes150are blind holes, penetrating in the bulk semiconductor layer122for less than its total thickness T122. Through-semiconductor vias (TSVs)160are formed in the through-semiconductor holes150, for example through one or more deposition and/or plating steps. In some embodiments, the TSVs160may be formed by filling the through-semiconductor holes150with a conductive material, for example including cobalt (Co), tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), aluminum (Al), zirconium (Zr), hafnium (Hf), a combination thereof, or other suitable metallic materials. In some embodiments, the conductive material may be disposed after forming optional barrier layers, seed layers, liner layers, etc. That is, the TSVs160may optionally include one or more barrier layers, seed layers, and/or liner layers, etc. A planarization step may be performed after the through-semiconductor holes150are filled with conductive material, so that ends160aof the TSVs160may be substantially coplanar with the top surface of the dielectric layer140. Opposite ends160bof the TSVs160are buried within the bulk semiconductor layer122.

InFIG. 2E, an interconnection structure170is formed over the dielectric layer140. In some embodiments, the interconnection structure170includes the patterned conductive traces172connecting the TSVs160and the optical device(s)136to the bonding pads174, and a dielectric layer176in which the patterned conductive traces172and the bonding pads174are embedded. The bonding pads174are entrenched in the dielectric layer176and exposed at a top surface176tof the dielectric layer176. Even though the dielectric layer176is shown as a single layer, in practice it may comprise a plurality of stacked dielectric layers. In some embodiments, the patterned conductive traces172are arranged in one or more metallization tiers alternately stacked with dielectric layers of the dielectric layer176. For example, the patterned conductive traces172may contact the optical device(s)136or the ends160aof the TSVs160exposed by the dielectric layer140. In some embodiments, patterned conductive traces172of different metallization tiers may extend through the dielectric layers176and140to establish electrical interconnections between the optical devices136. In some embodiments, the grating coupler132is connected to an optical device136by at least one waveguide pattern134, so that light incident on the grating coupler132is transmitted to and processed by the optical device136. The optical device(s)136may be configured to generate electric signals upon detection of the electromagnetic radiation received from the grating coupler132. The interconnection structure170may then connect the optical device136to other devices (not shown) which have been formed at the same or different level than the grating coupler132and the waveguide pattern(s)134. In some embodiments, the interconnected devices (e.g., the grating coupler132and the optical device(s)136) included in the substrate110may be referred to as a photonic integrated circuit (PIC), and the substrate110with the interconnection structure170may be referred to as a photonic die. In some embodiments, a material of the dielectric layer176includes inorganic materials such as oxides, nitrides, carbides, or a combination thereof. For example, the dielectric layer176may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbonitride, or a combination thereof. The dielectric layer176may be formed by suitable fabrication techniques such as spin-on coating, sputtering (e.g., CVD, ALD, PVD, etc.), or the like. In some embodiments, materials of the patterned conductive traces172and the bonding pads174independently include cobalt (Co), tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), aluminum (Al), zirconium (Zr), hafnium (Hf), a combination thereof, or other suitable metallic materials. The patterned conductive traces172may be formed by, for example, electroplating, deposition, and/or photolithography and etching. In some embodiments, the interconnection structure170is formed by sequential CVD and (dual) damascene processes. In some embodiments, the number of metallization tiers and dielectric layers in the interconnection structure170may be adjusted depending on the routing requirements. In some embodiments, the bonding pads174may be formed by forming trenches in the dielectric layer176exposing the patterned conductive traces172at their bottom, and subsequently filling the trenches with conductive materials.

InFIG. 2F, the interconnection structure170is patterned to form a recess180overlying the grating coupler132. That is, a portion of the interconnection structure170is removed, for example via one or more etching processes, to expose the dielectric layer140in an area overlying and around the grating coupler132. The depth of the recess180may be controlled in various manners, for example by adjusting the timing of the etching process, exploiting etching selectivity between the material of the dielectric layer140and the dielectric layer176, or any other suitable method. In some alternative embodiments, the recess180may further extend through the dielectric layer140, to expose the grating coupler132. Referring toFIG. 2FandFIG. 2G, an insulating material is disposed in the recess180to form a filler layer185. The insulating material of the filler layer185is not particularly limited, and may be selected, for example, on the basis of its refractive index and the refractive index of the material of the dielectric layer140. In some embodiments, the filler layer185includes an inorganic material, such as an oxide, a nitride, a carbide, or the like. In some embodiments, the filler layer185includes silicon oxide. In some embodiments, the filler layer185and the portion of dielectric layer140overlying the grating coupler132include the same material. In some embodiments, the filler layer185and the portion of dielectric layer140overlying the grating coupler includes different materials, optionally with matching refractive index to achieve desired optical effects on the incident radiation. In some embodiments, the filler layer185is at least as thick as the interconnection structure170. That is, the filler layer185may include a single layer of equal or greater thickness than the combined thickness of the dielectric layers constituting the dielectric layer176of the interconnection structure170. In some embodiments, replacement of the portion of the interconnection structure170(and, possibly, part or all of the dielectric layer140) with the filler layer185over the grating coupler132may reduce or eliminate the number of optical interfaces encountered by the incident radiation. The insulating material of the filler layer185may be formed according to any suitable process, such as sputtering (e.g., CVD, PVD, ALD), or the like. In some embodiments, a planarization process (e.g., grinding, chemical mechanical planarization, a combination thereof, or the like) is performed after the insulating material is disposed in the recess180. Following planarization, the top surface185tof the filler layer185, the top surface176tof the dielectric layer176and the top surfaces174tof the bonding pads174are substantially coplanar (e.g., located at the same level height along the stacking direction of the dielectric layers140,176), to provide an appropriate active surface AS1for hybrid bonding.

InFIG. 2H, one or more semiconductor dies190are provided on the active surface AS1. In some embodiments, one or more semiconductor dies190may be disposed in a single device unit region U2, according to design requirements. The semiconductor dies190may be of the same type or perform the same function, but the disclosure is not limited thereto. In some alternative embodiments, the semiconductor dies190disposed in a same device unit region U2may be different from each other, or perform different functions. Briefly, a semiconductor die190may include a semiconductor substrate192in which active and/or passive devices are formed, conductive traces194interconnecting the active and/or passive devices with each other and with the bonding pads196, and a dielectric layer198in which the conductive traces194and the bonding pads196are embedded. In some embodiments, top surfaces196tof the bonding pads196and the top surface198tof the dielectric layer198are part of the active surface AS2of a semiconductor die190.

In some embodiments, the semiconductor dies190are bonded to the dielectric layer176and the bonding pads174, for example through a hybrid bonding process. In some embodiments, the semiconductor dies190are picked-and-placed onto the active surface AS1such that the active surfaces AS2of the semiconductor dies190are in contact with the active surface AS1. Furthermore, the bonding pads196of the semiconductor dies190are substantially aligned and in direct contact with corresponding bonding pads174and the dielectric layers198are directly in contact with at least a portion of the dielectric layer176. In some embodiments, the footprint of a semiconductor die190(or the combined footprints of the semiconductor dies190of a device unit region U2) is smaller than a span of the device unit region U2. That is, even after placement of the semiconductor dies190, portions of the dielectric layer176within a device unit region U2may be left exposed. Similarly, the semiconductor dies190may leave exposed the filling layer185overlying the grating coupler132. That is, the semiconductor dies190may be disposed on the dielectric layer176without covering the filled recess180. In some embodiments, to facilitate the hybrid bonding of the semiconductor dies190, surface preparation for the surfaces to be bonded (i.e. the active surfaces AS1and the active surfaces AS2) may be performed. The surface preparation may include surface cleaning and activation, for example.

After cleaning the active surfaces AS1and AS2, activation of the bonding surfaces of the dielectric layers198and176may be performed for development of high bonding strength. For example, plasma activation may be performed to treat the top surfaces176tand198tof the dielectric layers176and198. After the activated top surfaces198tand176tof the dielectric layers198and176are in contact with each other, a hybrid bonding step is performed. The hybrid bonding step may include a thermal treatment process for dielectric bonding and a thermal annealing process for conductor bonding. In some embodiments, the temperature of the thermal annealing process for conductor bonding is higher than the temperature of the thermal treatment process for dielectric bonding. After performing the thermal annealing process for conductor bonding, the dielectric layer176is bonded to the overlying dielectric layers198, and the bonding pads196are bonded to the underlying bonding pads174. It will be apparent that while hybrid bonding has been described to connect the semiconductor dies190to the photonic integrated circuits, alternative connection schemes are also possible, with corresponding adaptations to the bonding interface. For example, the semiconductor dies190may be flip-chip bonded to the photonic integrated circuits, with the connection established through C4 bumps, and the structure of the interconnection structure170may be adapted accordingly. In some embodiments, the semiconductor dies190receive and process the electrical signals generated by the photonic integrated circuits upon detection of incident radiation. In some embodiments, the semiconductor dies190may be referred to as electronic dies, and the interconnected devices formed therein may be referred as electronic integrated circuits.

Referring toFIG. 21, in some embodiments, a filling process is performed to form an encapsulant200over the dielectric layer176and the filling layer185to encapsulate the semiconductor dies190. In some embodiments, the encapsulant200may be formed so as to fill gaps between the semiconductor dies190over the dielectric layer176. In some embodiments, the encapsulant200may initially cover the rear surfaces190rof the semiconductor die190. In some embodiments, a material of the encapsulant200includes inorganic materials such as silicon oxide, silicon nitride, or the like. For example, the encapsulant200may include silicon oxide. The material of the encapsulant200may be selected taking into account the refractive index of the filler layer185and the portion of the dielectric layer140over the grating coupler132. In some embodiments, the encapsulant200includes the same material as the filler layer185and the dielectric layer140. In some embodiments, the encapsulant200may be formed by suitable processes, such as sputtering (e.g., CVD, PVD, ALD), or the like. In some embodiments, the thickness of the encapsulant200is adjusted through one or more planarization processes (e.g., grinding, CMP, or the like) so that the top surface200tof the encapsulant200becomes substantially coplanar with the rear surfaces190rof the semiconductor dies190. By doing so, the semiconductor dies190are exposed by the encapsulant200. In some embodiments, portions of the semiconductor dies190may also be removed during the planarization process.

In some embodiments, a bonding layer210is formed on the encapsulant200and the rear surfaces190rof the semiconductor dies190. The bonding layer210may be blanketly formed over the encapsulant200and the semiconductor dies190, and also extend in an area overlying the grating coupler132. In some embodiments, a material of the bonding layer210may be selected from the same materials listed above for the bonding layer103(illustrated, e.g., inFIG. 1D). The bonding layer210may be formed by spin-coating, sputtering, or any other suitable process.

InFIG. 2J, the optical wafer ofFIG. 1Dis bonded to the structure ofFIG. 21. For example, the optical wafer ofFIG. 1Dis disposed with the bonding layer103contacting the bonding layer210, and an annealing step is performed so that the material of the bonding layers103and210react together to form Si—Si, Si—O, and/or other suitable bonds. In some embodiments, the optical wafer is disposed with the optical active areas109of the individual die unit regions U1overlying the grating couplers132formed in the device unit regions U2. That is, the wafer including the optical dies100is disposed so that the optical dies100are aligned with corresponding device units U2, and the optical nanostructures108vertically overlap with the grating coupler132. By doing so, the optically active areas109may transform (e.g., focus, polarize, filter, etc.) incident radiation before it reaches the grating coupler132and is processed by the optical device(s)136. By selecting the pattern of the optical nanostructures108, the incident radiation may be conveniently manipulated by the optical die100(e.g., a single optical die100) without having to stack multiple optical components on the path to the grating coupler132. Therefore, alignment issues from the use of multiple optics may be avoided, the manufacturing process may be simplified, and the product yield may be increased.

InFIG. 2K, the system is overturned and the bulk semiconductor layer122is thinned from the opposite side with respect to the insulator layer124until the buried ends160bof the TSVs160are exposed. In some embodiments, the substrate102of the optical die100may have sufficient thickness to allow easy handling and further processing of the reconstructed wafer. In some alternative embodiments, an auxiliary carrier (not shown) may be temporarily bonded on the side of the optical wafer to facilitate handling, if needed. The thinning of the bulk semiconductor layer122may involve one or more etching processes, a chemical mechanical planarization process, grinding, or the like.

InFIG. 2L, after the TSVs160are exposed, an interconnection structure220is formed on the bulk semiconductor layer122. The interconnection structure220includes conductive traces222and a dielectric layer224. In some embodiments, the conductive traces222establish electrical contact with one or more of the TSVs160. For example, some of the conductive traces222may interconnect some of the TSVs160with each other. In some embodiments, the dielectric layer224includes openings exposing portions of the conductive traces222. The number of dielectric layers224and conductive traces222may be selected according to routing requirements, and multiple interconnection tiers may be stacked over each other if required. In some embodiments, a material of the dielectric layer224includes polyimide, epoxy resin, acrylic resin, phenol resin, benzocyclobutene (BCB), polybenzooxazole (PBO), combinations thereof, or other suitable dielectric materials. The dielectric layer224may be formed by suitable fabrication techniques such as spin-on coating, lamination, or the like. In some embodiments, materials of the conductive traces222include cobalt (Co), tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), aluminum (Al), zirconium (Zr), hafnium (Hf), a combination thereof, or other suitable metallic materials. The conductive traces222may be formed by, for example, electroplating, deposition, and/or photolithography and etching.

In some embodiments, under-bump metallurgies232may be optionally formed in the openings of the dielectric layer224, contacting the conductive traces222at the bottom of the openings. In some embodiments, the under-bump metallurgies232may partially extend on the dielectric layer224around the openings. In some embodiments, a material of the under-bump metallurgies232includes copper, nickel, tin, palladium, gold, titanium, aluminum, or alloys thereof. In some embodiments, multiple layers of conductive material are stacked over each other to form the under-bump metallurgies232. In some embodiments, the under-bump metallurgies232are formed by a plating process. The plating process is, for example, electro-plating, electroless-plating, immersion plating, or the like.

In some embodiments, conductive terminals234are formed on the under-bump metallurgies232or on the exposed portions of the conductive traces222(for example, if formation of the under-bump metallurgies232is skipped). In some embodiments, the conductive terminals234include solder balls, ball grid array (BGA) connectors, metal pillars, controlled collapse chip connection (C4) bumps, micro bumps, bumps formed via electroless nickel-electroless palladium-immersion gold technique (ENEPIG), a combination thereof (e.g., a metal pillar with a solder ball attached), or the like. Referring toFIG. 2MandFIG. 2N, the wafer including multiple device unit regions U2is singulated, for example by cutting along cutting lines SC with a laser saw or a mechanical saw, to produce a plurality of semiconductor packages SD10. In the case of wafer-scale devices, cutting may be performed, for example to trim the edges of the wafer-scale device.

In view of the above, the semiconductor device SD10includes the optical die100capable of transforming incident radiation by way of the optically active area109before the radiation reaches the grating coupler132and is transmitted to the optical device(s)136. For example, referring toFIG. 2O, in some embodiments incident radiation R0passes through the optically active area109and undergoes an optical transformation (lensing, polarization, filtering, etc.), so that the transformed radiation R1is actually incident on the grating coupler132. In some embodiments, the pattern of the optical nanostructures108in the optically active area109is selected to achieve desired transformation of the incident radiation. In some embodiments, by transforming the incident radiation with the optical nanostructures108rather than one or more optics (e.g., lenses, filters, etc.), integration of optical functions can be simplified and the overall thickness of the semiconductor device SD10can be reduced. In some embodiments, the optical nanostructures108may be conveniently formed by etching the optical die100, possibly avoiding process failures encountered when convex or concave optics (e.g., lenses or the like) have to be formed.

In some embodiments, as illustrated inFIG. 2P, a semiconductor device SD10may be disposed on a circuit substrate240and connected to the circuit substrate240through the conductive terminals234, to be integrated in a larger semiconductor device SD12. In some embodiments, the circuit substrate240may be a printed circuit board, or the like.

In the following, several other optical dies and semiconductor devices will be described. Unless otherwise specified, materials and processes described above for the semiconductor device SD10may be applied to the other optical dies and semiconductor devices of the disclosure.

FIG. 3AandFIG. 3Bare schematic cross-sectional views illustrating a manufacturing process of an optical die250according to some embodiments of the disclosure. In some embodiments, the structure illustrated inFIG. 3Amay be obtained following a similar process as previously described with reference toFIG. 1AtoFIG. 1D. Briefly, the bonding layer253is formed on a side252aof the substrate252, and the substrate252is patterned at a side252bopposite with respect to the bonding layer253to form the optical nanostructures258in the optically active area259of the optical layer O252. Then, a filling layer260is formed on the side252bof the substrate where the optical nanostructures258are located. The filling layer260fills the interstices between the optical nanostructures258, and may initially blanketly cover the side252b, extending also outside the optically active area259. In some embodiments, the filling layer260includes a material having a different refractive index with respect to the material of the substrate252of which the optical nanostructures258are made. In some embodiments, the material of the filling layer260is selected so as to tune the effect of the optical nanostructures258on the incident radiation. For example, the filling layer260may include an inorganic material, such as an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), silicon oxynitride, or a combination thereof. In some alternative embodiments, the filling layer260includes an organic polymer such as polyimide, or the like. The filling layer260may be formed according to any suitable method, such as spin-coating, sputtering, or the like.

InFIG. 3B, a planarization process (e.g., grinding, CMP, or the like) is performed to remove excess material of the filling layer260from the substrate252. For example, the filling layer260may be removed until the substrate252is exposed again and an optical filler262remains in the interstices of the optical nanostructures258. In some embodiments, the optical filler262may be confined within the optically active area259. At the stage illustrated inFIG. 3B, the optical dies250may still be in wafer form, corresponding to different die unit regions U3of the optical wafer.

InFIG. 4is illustrated a cross-sectional view of a semiconductor device SD14according to some embodiments of the disclosure. The semiconductor device SD14may be obtained following a similar process as previously described for the semiconductor device SD10ofFIG. 2N. In some embodiments, the optical dies250including the optical filler262are included in the semiconductor devices SD14in place of the optical dies100of the semiconductor devices SD10. For example, the wafer ofFIG. 3Bincluding the optical dies250may be bonded to the wafer including the photonic dies110and the semiconductor dies190(illustrated, e.g., inFIG. 21), by fusion bonding of the bonding layers253and210. The optical dies250are bonded to the photonic dies110ensuring overlap between the optically active areas259and the grating couplers132, so that a desired optical transformation may be applied to the incident radiation during usage of the semiconductor device SD14. In some embodiments, by including the optical filler262, the optical transformation of the incident radiation effected may be further tuned or controlled.

FIG. 5AtoFIG. 5Care schematic cross-sectional views illustrating a manufacturing process of an optical die270according to some embodiments of the disclosure. In some embodiments, a bulk substrate272is provided, similar to the substrate102ofFIG. 1A. The bonding layer273is formed on the side272aof the bulk substrate272, and on an opposite side272bof the bulk substrate272is formed the optical layer280. In some embodiments, the material of the optical layer280and of the bulk substrate272may be independently selected from the options listed above for the substrate102ofFIG. 1A. In some embodiments, the material of the optical layer280is different from the material of the bulk substrate272, for example to facilitate patterning of the optical layer280or to tune the optical properties of the optical dies270. That is, the substrate of the optical dies270may be a composite substrate290, including the bulk substrate272(e.g., a bulk substrate layer) and an optical layer280of different materials. In some embodiments, the material of the optical layer280may be easier to pattern than the material of the bulk substrate272, or may have a sufficiently different refractive index to form an optical interface with the bulk substrate272, so as to manipulate incident radiation in a desired manner.

InFIG. 5B, a pattered mask300is provided on the optical layer280, employing similar materials and methods as previously described for the patterned mask104ofFIG. 1B. In some embodiments, the patterned mask300is patterned to form a plurality of patterning microstructures302. The patterning microstructures302may be formed in a selected region of the patterned mask300, and portions of the optical layer280are exposed by gaps existing in between adjacent patterning microstructures302.

Referring toFIG. 5BandFIG. 5C, the pattern of the patterning microstructures302is transferred to the optical layer280. For example, one or more etching steps may be performed to remove exposed portions of the optical layer280in between the patterning microstructures302. The etching may be any acceptable etch process, such as wet or dry etching, a reactive ion etch (RIE), neutral beam etch (NBE), the like, or a combination thereof. The etching may be anisotropic. In some embodiments, the etch is performed so that optical nanostructures282are formed from the optical layer280in an optically active area284. For example, the optical nanostructures282may be obtained by forming a plurality of through holes in the optical layer280, so that the bulk substrate272is exposed in between adjacent optical nanostructures282. The shapes and positions of the optical nanostructures282may be selected according to the desired optical transformation, as previously described for the optical nanostructures108ofFIG. 1D. After patterning of the optical layer280, the patterned mask300is removed, for example via stripping or ashing. At the stage illustrated inFIG. 5C, the optical dies270may still be in wafer form, corresponding to different die unit regions U4of the optical wafer.

InFIG. 6is illustrated a cross-sectional view of a semiconductor device SD16according to some embodiments of the disclosure. The semiconductor device SD16may be obtained following a similar process as previously descry ibed for the semiconductor device SD10ofFIG. 2N. In some embodiments, the optical dies270having the composite substrate290are included in the semiconductor devices SD16in place of the optical dies100of the semiconductor devices SD10. For example, the wafer including the optical dies270may be bonded to the wafer (illustrated, e.g., inFIG. 21) including the photonic dies110and the semiconductor dies190, by fusion bonding of the bonding layers273and210. The optical dies270are bonded to the photonic dies110ensuring overlap between the optically active areas284and the grating couplers132, so that a desired optical transformation may be applied to the incident radiation during usage of the semiconductor device SD16. In some embodiments, by including the composite substrate290, the optical nanostructures282may be easily formed, and/or the optical transformation of the incident radiation may be further tuned or controlled.

FIG. 7is a schematic cross-sectional view of an optical die310according to some embodiments of the disclosure. In some embodiment, the optical die310includes the substrate312. The substrate312has an optical layer O312protruding from a bulk substrate layer S312, as previously described for the substrate102ofFIG. 1D. In the optical layer O312, the optical nanostructures314are formed in the optically active area316. In some embodiments, the bonding layer318is formed on the same side312aof the optical layer O312, extending on the optical layer O312and in between the optical nanostructures314. That is, the bonding layer318may also act as optical filler, similar to what was previously described for the optical filler262ofFIG. 4. In some embodiments, the optical dies310may be manufactured in wafer form, corresponding to different die unit regions U5of the optical wafer.

InFIG. 8A, the wafer including the optical dies310is bonded to the wafer including the photonic dies110and the semiconductor (electronic) dies190, by fusion bonding of the bonding layers318and210. The optical dies310are disposed on the corresponding device unit regions U6with the optical nanostructures314closer to the bonding layer210. That is, in the structure ofFIG. 8A, the optical layer O312is interposed between the photonic die110and the bulk substrate layer S312of the optical die310. Referring toFIG. 8AandFIG. 8B, in some embodiments the optical dies310are thinned by removing partially or completely the bulk substrate layer S312, for example via grinding, CMP, or similar processes. In some embodiments, the optical dies310are thinned until the portions of bonding layer318disposed between the optical nanostructures314are exposed. In some embodiments, the semiconductor device SD18ofFIG. 8Cmay be obtained after thinning of the optical dies310, for example through similar process steps as previously described with reference toFIG. 2KtoFIG. 2N. In some embodiments, removal of the bulk substrate layer S312may further reduce the thickness of the semiconductor devices SD18.

FIG. 9AtoFIG. 9Care schematic cross-sectional views of structures produced during a manufacturing method of a semiconductor device SD20according to some embodiments of the disclosure. In some embodiments, the structure illustrated inFIG. 9Amay be obtained following a similar process as previously described with reference toFIG. 2AtoFIG. 21, omitting the formation of the bonding layer210illustrated inFIG. 21. Rather, the material of the substrate322of the optical die320is directly deposited or grown (e.g., epitaxial growth) on the encapsulant200and the rear surfaces190rof the semiconductor dies190. In some embodiments, the substrate322is formed so as to blanketly cover the device unit regions U7. The material of the substrate322is not particularly limited, and may be selected, for example, as previously described for the material of the substrate102ofFIG. 1A.

InFIG. 9B, a pattered mask330is provided on the substrate322, employing similar materials and methods as previously described for the patterned mask104ofFIG. 1B. In some embodiments, the patterned mask330is patterned to form a plurality of patterning microstructures332. The patterning microstructures332are formed in a region of the patterned mask330overlying the grating coupler132. Portions of the substrate322are exposed by gaps existing in between adjacent patterning microstructures332. Referring toFIG. 9BandFIG. 9C, the pattern of the patterning microstructures332is transferred to the substrate322, thus forming the optical layer O322. For example, one or more etching steps may be performed to remove exposed portions of the substrate322in between the patterning microstructures332. The etching may be any acceptable etch process, such as wet or dry etching, a reactive ion etch (RIE), neutral beam etch (NBE), the like, or a combination thereof. The etching may be anisotropic. In some embodiments, the etch is performed so that optical nanostructures324are formed from the substrate322in an optically active area326overlapping the grating coupler132. For example, the optical nanostructures324may be obtained by forming a plurality of through holes in the substrate322, so that the encapsulant200is exposed in between adjacent optical nanostructures324. In such cases, the thickness of the optical layer O322coincides with the thickness of the originally grown substrate322, however, the disclosure is not limited thereto. In some alternative embodiments, the thickness of the optical layer O322may be only a portion of the thickness of the substrate322. The shapes and patterns of the optical nanostructures324may be selected according to the desired optical transformation, as previously described for the optical nanostructures108ofFIG. 1D. After patterning of the optical layer O322, the patterned mask330is removed, for example via stripping or ashing. In some embodiments, the semiconductor device SD20ofFIG. 9Cmay be obtained after removal of the patterned mask330, for example through similar process steps as previously described with reference toFIG. 2KtoFIG. 2N. In some embodiments, by forming the optical dies320directly on the encapsulated semiconductor dies190, the optical dies320may be integrated without additional fusion bonding steps or requiring formation of bonding layers such as the bonding layers210and103ofFIG. 2N. Therefore, the manufacturing process may be simplified and, possibly, the thermal load of the manufacturing process may be reduced. In some embodiments, the semiconductor devices SD20may also be of reduced thickness, as the optical dies320may include only the optical layer O322, without a bulk substrate layer (such as the bulk substrate layer S102ofFIG. 1D).

FIG. 10AtoFIG. 10Eare schematic cross-sectional views of structures formed during manufacturing of optical dies340according to some embodiments of the disclosure. InFIG. 10Ais illustrated a substrate342. The substrate342may be formed from similar materials as listed above for the substrate102ofFIG. 1A. In some embodiments, the substrate342includes a semiconductor material, and has devices344formed on at least one side342a. The devices344may be active devices (e.g., transistors, diodes, etc.) or passive devices (e.g., capacitors, resistors, inductors, etc.) and may be formed according to any suitable process. In some embodiments, the devices344are formed in a device region345of the substrate342within each die unit region U8, while another region of the substrate342adjacent to the device region345may be free of devices.

InFIG. 10B, an interconnection structure350is formed on the side of342aof the substrate342where the devices344are formed. The interconnection structure350includes the patterned conductive traces352interconnecting the devices344to each other and to the bonding pads354formed at an outer side of the interconnection structure350, and the dielectric layer356in which the patterned conductive traces352and the bonding pads354are embedded. Materials and processes to form the interconnection structure350may be similar to the ones previously described for the interconnection structure170.

InFIG. 10C, the interconnection structure350is patterned to form a recess360exposing a region of the substrate342beside the device region345. For example, the region exposed by the recess360may be free of devices344. Referring toFIG. 10CandFIG. 10D, a filler layer365is formed on the substrate342in the recess360, for example to reduce the number of optical interfaces encountered by radiation travelling through the interconnection structure350. The filler layer365may be formed with similar materials and processes as previously described for the filler layer185ofFIG. 2G.

InFIG. 10E, a side342bof the substrate342opposite with respect to the interconnection structure350is patterned to form optical nanostructures346, following similar processes as previously described with reference toFIG. 1BtoFIG. 1D. In the optical dies340, the optically active areas348in which the optical nanostructures346are formed correspond to regions of the substrate342overlying the filler layers365. As such, in some embodiments the optical dies340include a device layer D342in which the devices344are formed and an optical layer O342in which the optical nanostructures346are formed, and the device layer D342and the optical layer O342are disposed at opposite sides of the bulk substrate layer S342. At the stage illustrated inFIG. 10E, the optical dies340may still be in wafer form, corresponding to different die unit regions U8of the optical wafer. It should be noted that while inFIG. 10AtoFIG. 10Ethe optical nanostructures346were formed after the devices344and the interconnection structure350, the disclosure is not limited thereto, and the order of the process steps may be swapped according to production requirements.

FIG. 11AtoFIG. 11Fare schematic cross-sectional views illustrating structures formed during a manufacturing process of a semiconductor device SD22according to some embodiments of the disclosure. The structure illustrated inFIG. 11Amay be formed following a similar process as previously described with reference toFIG. 2AtoFIG. 2H. In some embodiments, after the semiconductor dies190are bonded to the photonic dies110, some of the bonding pads174are left exposed. For example, fewer semiconductor dies190may be bonded within a device unit region U9, so that connection of further components to the interconnection structure170may be possible.

InFIG. 11B, the encapsulant370is formed over the interconnection structure170and the filler layer185, with similar materials and processes as previously described for the encapsulant200. The encapsulant370may be formed through a sequence of deposition and planarization steps, so as to laterally wrap the semiconductor dies190. Rear surfaces190rof the semiconductor dies190may be at the same level height as the top surface370tof the encapsulant370. The encapsulant370may initially cover the bonding pads174left exposed after bonding of the semiconductor dies190. In some embodiments, through holes375are formed extending for the entire thickness of the encapsulant370to expose the bonding pads174at their bottom, for example via one or more etching step. One or more auxiliary masks (not shown) may be employed to define the regions of the encapsulant370to be patterned. Referring toFIG. 11BandFIG. 11C, the through holes375are filled with conductive material to form through insulator vias (TIVs)380, providing electrical connection the optical device(s)136and the TSVs160of the photonic dies110via the bonding pads174. The conductive material of the TIVs380may be a metallic material, for example including cobalt (Co), tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), aluminum (Al), zirconium (Zr), hafnium (Hf), a combination thereof. In some embodiments, seed layers, barrier layers, or the like may be optionally formed before filling the through holes375with the conductive material. In some embodiments, the conductive material of the TIVs380may be provided via plating and/or other suitable deposition processes.

InFIG. 11D, an interconnection structure390is formed on the encapsulated semiconductor die190and the TIVs380, with similar materials and processes as previously described for the interconnection structure170. The interconnection structure390includes the patterned conductive traces392, the bonding pads394and the dielectric layer396in which the patterned conductive traces392and the bonding pads394are embedded. The patterned conducive traces392establish electrical connection between the TIVs380and the bonding pads394. A portion of the interconnection structure390overlying the grating coupler132is removed to form the filler layer400, with similar material and processes as previously described for the filler layer185.

InFIG. 11E, the wafer including the optical dies340is hybrid-bonded to the wafer including the photonic dies110and the electronic dies190. More specifically, the bonding pads354are bonded to the bonding pads394, the dielectric layer356is bonded to the dielectric layer396, and the filler layer365is bonded to the filler layer400. That is, the interconnection structure350may act as a bonding layer for the optical wafer. The optical dies340are disposed so that the optically active areas348overlies the grating couplers132, to perform a desired optical transformation on incident radiation. After bonding, the devices344of the optical dies340are also connected to the photonic dies110and the electronic dies190, via the TIVs380. That is, functional circuitry may also be included in the optical die340. In some embodiments, the semiconductor device SD22ofFIG. 11Fmay be obtained after bonding of the optical die340, for example through similar process steps as previously described with reference toFIG. 2KtoFIG. 2N. While in the present embodiment the connection between the optical die340and the photonic die110or the electronic die190is established by the TIVs380, the disclosure is not limited thereto. In some alternative embodiments, semiconductor dies having TSVs formed therethrough may be included to establish electrical connection to the devices344of the optical die340. Similarly, while in the present embodiment the devices344and the optical nanostructures346are formed at opposite sides of the substrate342, the disclosure is not limited thereto. In some alternative embodiments, the optical nanostructures346and the devices344may be formed on a same side of the substrate342. For example, the optical nanostructures346may be formed on the side of the substrate342which is disposed closer to the photonic dies110, so that the optical layer O342and the device layer D342coincide. In such cases, the filler layer365may also fill the interstices between the optical nanostructures346.

FIG. 12is a schematic cross-sectional view of a semiconductor device SD24according to some embodiments of the disclosure. The semiconductor device SD24ofFIG. 12has a similar structure and may be formed following a similar manufacturing process as previously described for the semiconductor device SD10ofFIG. 2N. In the semiconductor device SD24, the optical die410may have a smaller span than the photonic die110. For example, the optical die410may be disposed in a region overlying the grating coupler132so as to be able to optically transform incident radiation, while leaving exposed at least portions (if not the entirety) of the rear surfaces190rof the semiconductor dies190. For example, the optical dies410having the bonding layer413and the optical nanostructures414may be singulated (e.g., at the stage illustrated inFIG. 1D) before being bonded to the wafer including the photonic dies110, and may be disposed on the wafer including the photonic dies110, for example with a pick-and-place step. Alignment marks may be formed, for example on the bonding layer418, to ensure correct alignment of the optically active areas416formed in the substrate412with the grating couplers132during placement of the optical dies410. The bonding layers413and418may then be bonded together. The bonding layer418may be originally blanketly formed over the wafer including the photonic dies110(as illustrated, e.g., inFIG. 21), and portions left exposed after bonding of the optical dies410may be selectively removed. In some embodiments, heat exchangers (not shown) may be disposed on or over the exposed portions of the rear surfaces190rof the semiconductor dies190, so that heat generated during usage of the semiconductor devices SD24may be efficiently dissipated.

FIG. 13is a schematic cross-sectional view of a semiconductor device SD26according to some embodiments of the disclosure. The semiconductor device SD26ofFIG. 13has a similar structure and may be formed following a similar manufacturing process as previously described for the semiconductor device SD10ofFIG. 2N. In some embodiments, the optical die420included in the semiconductor device SD26is disposed at a same level as the semiconductor die(s)190. For example, optical dies420may be disposed on the interconnection structure170beside the semiconductor dies190, so as to cover the filler layers185. In particular, the optical dies420are disposed so that the optical nanostructures424formed in the optical layer O422of the substrate422overlie the grating couplers132. In some embodiments, a bonding layer423is formed on the side of the substrate422closer to the interconnection structure170, so that the optical dies420are (fusion) bonded to the filler layers185and, possibly, the dielectric layer176. The encapsulant200is then formed, laterally wrapping the semiconductor dies190and the optical dies420. In some embodiments, the material of the encapsulant200may also be deposited in the optically active area426of the optical die420, filling the spaces in between the optical nanostructures424as previously described for the optical filler262ofFIG. 4. In some embodiments, by embedding the optical die420in the encapsulant200, the thickness of the semiconductor device SD26may be reduced. Furthermore, the rear surfaces190rof the semiconductor dies190are exposed, so that heat dissipation (for example, with auxiliary heat exchangers) may be facilitated.

FIG. 14is a schematic cross-sectional view of a semiconductor device SD28according to some embodiments of the disclosure. The semiconductor device SD28ofFIG. 14has a similar structure and may be formed following a similar manufacturing process as previously described for the semiconductor device SD10ofFIG. 2N. In some embodiments, the optical dies430included in the semiconductor devices SD28have similar structures to the optical dies340ofFIG. 11F. For example, the optical dies430include optical nanostructures434formed in an optically active area436of the optical layer O432of the substrate432, and devices438formed outside of the optically active area436in a device layer432. In some embodiments, the optical layer O432may be disposed at an opposite side of the bulk substrate layer S432with respect to the device layer D432. In some alternative embodiments, the optical layer O432and the device layer D432may coincide or anyway be formed at a same side of the bulk substrate layer S432. In some embodiments, the interconnection structure440of the optical die430is (hybrid) bonded to the interconnection structure170, thus acting as a bonding layer. More particularly, the bonding pads444are bonded to the bonding pads174, the dielectric layer446is bonded to the dielectric layer176, and the filler layer450is bonded to the filler layer185. The patterned conductive traces442establish electrical connection between the bonding pads444and the devices438. In some embodiments, when devices438of the optical die430are integrated in the circuitry of the semiconductor device SD28, the photonic die110can serve as an optical routing platform, for example including only passive devices, thus avoiding the risk of process failure encountered when manufacturing active devices. In some embodiments, the encapsulant200laterally wraps the semiconductor dies190and the optical die430. In some embodiments, the material of the encapsulant200may also be deposited in the optically active area436of the optical die430, filling the spaces in between the optical nanostructures434as previously described for the optical filler262ofFIG. 4. In some embodiments, by embedding the optical die430in the encapsulant200, the thickness of the semiconductor device SD28may be reduced. Furthermore, the rear surfaces190rof the semiconductor dies190are exposed, so that heat dissipation (for example, with auxiliary heat exchangers) may be facilitated. In some embodiments, the semiconductor dies190may be omitted. For example, the functions performed by the semiconductor die190may be performed instead by the devices438of the optical die430. For example, the optically active area436of the optical die430performs the desired transformation on the incident radiation, while the devices438elaborate the signals received from the photonic die110. Therefore, the number of components to be integrated may be reduced and the manufacturing process may be simplified.

Based on the above, in some embodiments, by including in a semiconductor device an optical die having optical nanostructures formed in an optically active area, radiation incident on a photonic die may be optically transformed. In some embodiments, use of the optical nanostructures allows increased flexibility in the configuration of the optical die, and may reduce the number of components required as multiple optical effect may be achieved by a single array of optical nanostructures. Furthermore, the optical nanostructures may be realized without significant increase in the complexity of the manufacturing process, thus containing production costs and times. The possibility of forming functional devices in the optical dies further increase the flexibility (in terms of configuration and possible applications) of the semiconductor devices of the disclosure.

In some embodiments, features of the semiconductor devices SD10-SD28may be combined as required. For example, an optical filler such as the optical filler262ofFIG. 4may be applied to the optical dies270ofFIG. 5C, 320ofFIG. 9C, 340ofFIG. 11F, 410ofFIG. 12, 420ofFIG. 13, or430ofFIG. 14, filling the interstices between the optical nanostructures282,324,346,414,424, or434. In some other embodiments, the bonding layer273of the optical dies270, the filler layer365of the optical dies340, or even the encapsulant200may also function as optical filler, as described for the bonding layer318ofFIG. 7. In some embodiments, any one of the optical dies disclosed may have a composite substrate as the optical die270ofFIG. 5C. For example, an additional layer of a different material may be deposited on the substrate322ofFIG. 9A, and the optical layer O322may be formed from the additional layer alone or from multiple ones (e.g., all) of the deposited layers. In some embodiments, the optical layers O342,0412,0422,0432of the optical dies340ofFIG. 11F, 410ofFIG. 12, 420ofFIGS. 13, and 430ofFIG. 14may be formed of different materials than the rest of the corresponding substrates342,412,422,432. In some embodiments, any one of the optical dies disclosed may leave the semiconductor dies190exposed, as illustrated for the optical die410ofFIG. 12, 420ofFIG. 13, or430ofFIG. 14.

In accordance with some embodiments of the disclosure, a semiconductor device includes a photonic die and an optical die. The photonic die includes a grating coupler and an optical device. The optical device is connected to the grating coupler to receive radiation of predetermined wavelength incident on the grating coupler. The optical die is disposed over the photonic die and includes a substrate having optical nanostructures formed therein. Positions and shapes of the optical nanostructures are such to perform an optical transformation on the incident radiation of predetermined wavelength when the incident radiation passes through an area of the substrate where the optical nanostructures are located. The optical nanostructures overlie the grating coupler so that the incident radiation of predetermined wavelength crosses the optical die where the optical nanostructures are located before reaching the grating coupler.

In accordance with some embodiments of the disclosure, a semiconductor device includes a first dielectric layer, a grating coupler, an optical device, a first interconnection structure, a first filler layer, a first die, an encapsulant, and an optical layer. The first dielectric layer extends on a bulk semiconductor layer. The grating coupler and the optical device are disposed beside each other on the first dielectric layer. The grating coupler is configured to transmit incident radiation of at least one wavelength to the optical device. The optical device is configured to produce an electronic signal based on the incident radiation received from the grating coupler. The first interconnection structure extends over the optical device at an opposite side with respect to the first dielectric layer and is electrically connected to the optical device. The first filler layer extends over the grating coupler at an opposite side with respect to the first dielectric layer and at a same level height over the bulk semiconductor layer as the first interconnection structure. The first die is disposed on the first interconnection structure and is electrically connected to the optical device by the first interconnection structure so as to receive the electronic signal generated by the optical device. The encapsulant extends on the first interconnection structure to encapsulate the first die. The optical layer includes a pattern of columnar nanostructures. The pattern of columnar nanostructures is disposed over the first filler layer at an opposite side of the first filler layer with respect to the grating coupler. The pattern of columnar nanostructures is configured to perform an optical transformation on the incident radiation before the incident radiation reaches the grating coupler.

In accordance with some embodiments of the disclosure, a manufacturing method of a semiconductor device includes the following steps. A front semiconductor layer of a semiconductor-on-insulator substrate is patterned to form at least one grating coupler and at least one optical device connected to the grating coupler. An optical die is provided over the grating coupler. The optical die includes an optically active area in which nanostructures are located. The nanostructures are positioned and shaped so that an optical transformation is performed on incident radiation of predetermined wavelength when the incident radiation passes through the optically active area. The nanostructures overlie the grating coupler so that the incident radiation of predetermined wavelength crosses the optically active area before reaching the grating coupler.