Demodulator for simultaneous multi-node receiving and the method thereof

The present invention relates to a demodulator for simultaneous multi-node receiving and a method therof; and, more particularly, a demodulator in a wireless communication system for receiving signals from multi nodes simultaneously and a method thereof.In accordance with the aspect of the present invention, there is provided a demodulator for simultaneous multi-node receiving which comprises: a clock generator for generating a pair of CW signals and a pair of demodulating modules, wherein the demodulating modules comprise a mixer for multiplying received signals and one of the CW signals, an integrator for integrating multiplied signal and data operating unit for calculating variation result of integrated signal at every certain symbol duration and deciding output data in accordance with the variation result.

TECHNICAL FIELD

The present invention relates to a demodulator for simultaneous multi-node receiving and a method therof; and, more particularly, a demodulator in a wireless communication system for receiving signals from multi nodes simultaneously and a method thereof.

BACKGROUND ART

FIG. 1is a block diagram describing a node signal receiving device in a RF system in prior art. As shown inFIG. 1, the node signal receiving device in a RF system comprises a digital demodulating block for performing ASK demodulation through SQR(Square Root) signal conversion that squares negative data of I channel node signal and Q channel node signal and transforms squared data to negative data and a decoding block for detecting edge position information by using the integration of demodulated signal and decoding said demodulated signal by using detected edge position information. Meanwhile, the digital demodulating block comprises a phase shifter for shifting phase of the node signal whose signal level is lower than the other between the node signals of I channel and Q channel outputted from ADC(Analog to Digital Converter), a signal converter for performing SQR signal conversion onto phase-shifted node signal and the node signal which has higher signal level, and a adder for adding converted node signal of I channel and converted node signal of Q channel.

Furthermore, the decoding block comprises an edge information detector for detecting edge position information of a demodulated signal, a correlator for performing signal correlation onto the demodulated signal by using detected edge position information and a bit data decider for deciding bit data by using signal correlation result.

DISCLOSURE OF INVENTION

Technical Problem

The node signal receiving device in a RF system of prior art inverts the phase of the node signal whose signal level is lower than the other between the node signals of I channel and Q channel, performs SQR signal conversion onto phase-inverted signal and the node signal which has higher signal level, adding converted node signal of I channel and converted node signal of Q channel and transmits added signals to decoding block. Through the above process the node signal receiving device receives signals from nodes.

When many nodes send signals simultaneously, however, some node signals have a higher signal level in I channel and the others have a higher signal level in Q channel because every node has a different phase.

It is, therefore, the node signal receiving method in the prior art has a technical problem that RF system should repeat the protocol defined in the system until only one node respond to the RF system.

Technical Solution

In accordance with the aspect of the present invention, there is provided a demodulator for simultaneous multi-node receiving, which comprises: a clock generator for generating a pair of CW signals and a pair of demodulating modules, wherein the demodulating modules comprise a mixer for multiplying received signals and one of the CW signals, an integrator for integrating multiplied signal and data operating unit for calculating variation result of integrated signal at every certain symbol duration and deciding output data in accordance with the variation result.

In accordance with another aspect of the present invention, there is provided a method for simultaneous multi-node receiving comprises the steps of: a) mixing a CW signal and received signals, b) integrating mixed signal and c) storing integrated signal value and deciding data according to the calculation of variation result of the integrated signal value at every certain symbol duration.

Advantageous Effects

According to the present invention, a signal receiving time of entire nodes could be reduced because simultaneous receiving of multi-nodes signals is available via distinguishing node signals even when more than two nodes respond to the demodulator simultaneously. Furthermore, as more than one data from different nodes can be demodulated simultaneously, data modulating speed can be increased.

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, the best mode of embodiments of the present invention will be described in detail with reference to the attached drawings.

FIG. 2is a block diagram showing a demodulator for simultaneous multi-node receiving in accordance with the present invention.

As shown inFIG. 2, the demodulator for simultaneous multi-node receiving in accordance with the present invention comprises: a clock generator210, a phase shifter220, and a pair of demodulating modules10,20comprising a mixer110,120, an integrator310,320and a data operating unit410,420.

Clock generator210generates a pair of CW signals. the pair of CW signals has same frequency with received signals.

Phase shifter220shifts the phase of one of the CW signals by 90°

Mixers110,120mix one of the CW signals with the received signals(e.g. ASK signal) which are transmitted from nodes and output mixed signal. Meanwhile, there is 90° phase difference between the pair of CW signals that are inputted into mixer-1110and mixer-2120. That is, CW-1signal which is generated in clock generator210is inputted directly into mixer-1110and CW-2signal which is generated in clock generator210and shifted its phase by 90° along phase shifter220is inputted into mixer-2120. The bit data of the received signals inputted in mixer110,120is encoded in one of encoding method such as FM0, Miller, and Manchester coding.

Integrators310,320integrate mixed signals. Integrated values integrated from the integrators are affected most by the received signals which have the least difference in phase with inputted reference signal, inputted CW signal. Integrations of integrators310,320are performed at every half data symbol duration(½ symbol duration).

Data operating unit410stores the integrated values that are integrated from integrators310,320, and deciding output data according to the variation result of the intergrated signal value at every certain symbol duration. Data operating unit410comprises control unit411, symbol boundary detector418, buffer-1412, comparator-1413, buffer-2414, buffer-3415, comparator-2416and data decider417.

Symbol boundary detector418detects a half of a data symbol duration.

Integrator310stores integrated values in buffer-1412at every ½ symbol duration, buffers412,414,415store data at every ½ symbol duration.

Comparator-1413compares the present integrated value of integrator310with the previous integrated value stored in buffer-1412, decides a sign—a plus or a minus—according to the result of comparison of integrated values, and outputs the sign at every ½ symbol duration.

Comparator-2416compares the present sign of comparator-1413with the previous sign of comparator-1stored in buffer-3415(that is, sign of comparator-1outputted1symbol duration before) at every 1 symbol duration.

Control unit411controls operations of integrator310, comparators414,415, and buffers413,415,416at every ½ data symbol duration which is detected by symbol boundary detector418. Furthermore, control unit411comprises state machine (not illustrated) that decides data comparison time of comparator-1413and comparator-2416.

Data decider417decides data according to either the result of comparator-1413or the result of comparator-2416. Data decider417also decides either the result of comprator-1or the result of comparator-2on the basis of the encoding methods of the received signals. In case bit data of received signals are encoded in FM0, data decider417outputs ‘0’ when two signs, the present sign of comparator-1and the previous sign of comparator-1outputted1symbol duration before, are identical according to comparison result of comparator-2, outputs ‘1’ when two signs are different.

In case, bit data of received signals are encoded in Miller code, data decider417outputs ‘1’ when two signs, the present sign of comparator-1and the previous sign of comparator-1outputted 1 symbol duration before, are identical according to comparison result of comparator-2while data decider417outputs ‘0’ when the said two signs are different.

In case, bit data of received signals are encoded in Manchester code, data decider417may outputs ‘1’ when the present sign of comparator-1is ‘+’, outputs ‘0’ when the present sign of comparator-1is ‘−’. On the other hand, data decider417may outputs ‘1’ when the present sign of comparator-1is ‘−’, outputs ‘0’ when the present sign of comparator-1is ‘+’.

FIG. 3andFIG. 4are block diagrams showing demodulators for simultaneous multi-node receiving in accordance with the embodiments of the present invention. The demodulators inFIG. 3andFIG. 4further comprise Analog to Digtal Converters(ADC).

Hereinafter, a demodulator for simultaneous multi-node receiving in accordance with the embodiment of the present invention will be disclosed in detail with reference to the attached drawings,FIG. 5toFIG. 9.

FIG. 5is a graph showing carrier wave of response signals when node A, node B and node C respond simultaneously. The response signals of node A, B and C are encoded in FM0and modulated in ASK modulation method.

As shown inFIG. 5, carrier signal of node A(Node A) has the same phase with CW-1signal generated in clock generator210, carrier signal of node B(Node B) has the same phase with CW-2signal shifted its phase by 90° along phase shifter220, and carrier signal of node C(Node C) has less phase difference with CW-1compared with CW-2. Furthermore, the amplitudes of carrier signals of three nodes are identical. According to the above assumptions, signal IIinputted integrator-1310is described in Math Formula 1 and signal I2inputted integrator-2320is described in Math Formula 2.
I1=(NodeA+NodeC)×CW1[Math Formula 1]
I2=(NodeB+NodeC)×CW2[Math Formula 2]

FIG. 5is a graph showing integrated value of Integrator1received signal I1.

As shown inFIG. 5, because the phase difference between the carrier signal of node C(Node C) and the CW-1signal is bigger than the phase difference between the carrier signal of node A(Node A) and the CW-1signal, the integrated value of (Node C * CW-1) signal is less than that of (Node A * CW-1) signal.

FIG. 7is a graph showing eigen functions of FM0encoding andFIG. 8is a state diagram of FM0encoded signal.

As shown inFIG. 7, a signal level of FM0encoded signal is changed at the starting point of every symbol. If data is ‘0’, signal level is further changed at midpoint of every symbol.

Because FM0encoded signal has features mentioned above, the demodulator of the present invention compares variation result of the integrated values at every ½ symbol duration. Because the demodulator in prior art distinguishes signals by the variation of symbol level, it is not able to detect the exact data if multi nodes respond simultaneously. To overcome the above problem, the demodulator of the present invention compares the variation result of integrated value at every ½ symbol duration.

FIG. 9is a graph showing signals of integrator and state machine in accordance with the embodiment of the present invention.

To describe the mechanism of state machine, we assume that node A transmits data ‘0 0 1 0’ and node C transmits data ‘1 0 0 0’. Furthermore, we assume that 100% ASK modulation and N_Carrier(Number of carriers per symbol) =16. We clarify that the present invention is not limited to above ASK modulation index nor N_Carrier number.

As shown inFIG. 9, after signals of node A and node C are inputted, the state machine(not illustrated) comprised in control unit411circulates its value with 1 symbol duration.

If the value of state machine is ‘0’, comparator-1413compares the present integrated value of integrator-1310with the previous integrated value stored in buffer-1412, and stores comparison result as a sign. Because the present integrated value of the first symbol is higher, ‘+’ sign is stored in buffer-2414.

Then, comparator-1413compares the present integrated value of integrator-1310with the previous integrated value stored in buffer-1412when the value of the state machine becomes ‘0’ again. According to a comparison result, ‘+’ sign is stored in buffer-2414. The sign stored in buffer-2414is transmitted to buffer-3415whenever the value of the state machine is changed, that is, at every ½ symbol duration.

Comparator-2416compares the present sign of comparator-1414with the previous sign of comparator-1414stored in buffer-3415at present.

According to comparison result, data decider417decodes received data as ‘0’ because two signs are identical.

When the value of the state machine becomes ‘0’ again after repeating the above steps, comparator-2416compares two signs again, and data decider417decodes received data as ‘1’ because two signs are different(the present sign of comparator-1is ‘−’ and the 1 symbol previous sign of comparator-1is ‘+’).

Data operating unit-1410decodes the signal of node A through repeating the above steps.

As described above, the demodulator of the present invention is able to distinguish the signal which has the biggest integrated value and decode the signal through comparing variation of integrated value at boundaries of symbols when many signals are received because many nodes responded simultaneously.

Similarly, the signal of node B is decoded by integrator-2320and data operating unit-2420. It is, therefore, the demodulator of the present invention is able to distinguish simultaneously received signals and decode the signals.

FIG. 10is a flow chart describing a method for simultaneous multi-node receiving in accordance with the present invention.

As shown inFIG. 10, a method for simultaneous multi-node receiving in accordance with an embodiment of the present invention comprises steps of mixing, integrating and data operating.

Mixer110receives a CW signal and received signals and mixes two signals.

Integrator310integrates mixed signals mixed in mixer110.

Comparator-1414compares the present integrated value with the previous integrated value(S102), and decides a sign and stores the sign(S103) at every ½ symbol duration.

Comparator-2416compares the present sign of Comparator-1with the 1 symbol previous sign of comparator-1at every 1 symbol duration(S104).

According to the comparison result of comparator-2416, data decider417decides and outputs data as ‘0’ if the two signs of comparator-2are identical(S106). On the other hand, if the two signs of comparator-2are not identical, data decider417decides and outputs data as ‘1’(S107).

The above steps are performed until the received signal ends at every ½ symbol duration detected by symbol boundary detector418(S108).

Furthermore, the method in accordance with the present invention further comprises steps of comparing the present integrated value with the previous integrated value at every certain symbol duration, and deciding output data according to the comparison result of the above comparing step. The comparing and deciding steps are performed at every ½ symbol duration detected in symbol boundary detection step.

For instance, the demodulator of the present invention may comprise 4 demodulating module and 2 more phase shifters(one for shifting 180 degrees and the other for shifting 270 degrees).

Furthermore, a multiplexer(mux) may be added to data operating units410,420. The first input of the multiplexer is the output of comparator-1413and the second input of the multiplexer is the output of comparator-2416. The multiplexer outputs either the first input or the second input to data decider417according to the encoding method of the received signals.