Printed circuit board and method of manufacturing the same

The present disclosure relates to a printed circuit board and a method of manufacturing the same. The printed circuit board includes: an insulating layer; a plurality of pads disposed on the insulating layer; and a plurality of insulating walls that are disposed on the insulating layer and cover side surfaces of the plurality of pads, respectively, but are not disposed on upper surfaces of the plurality of pads. The plurality of insulating walls are disposed to be spaced apart from each other on the first insulating layer.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application claims benefit of priority to Korean Patent Application No. 10-2021-0165240 filed on Nov. 26, 2021 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

TECHNICAL FIELD

The present disclosure relates to a printed circuit board, and more particularly, to a printed circuit board in which an electronic component may be mounted and/or embedded, and a method of manufacturing the same.

BACKGROUND

In general, a high-performance semiconductor die has used a flip-chip mounting manner for high-density mounting. In this case, in accordance with miniaturization and performance improvements of semiconductors, an interval between connection terminals for flip-chip mounting has also been continuously decreased. Accordingly, an opening size and precision of a solder resist of a board, the degree of difficulty in forming solder bumps, the degree of difficulty of a bridge short-circuit in solder bonding of the semiconductor die, and the like, has continuously increased.

SUMMARY

An aspect of the present disclosure may provide a printed circuit board capable of being easily manufactured, and a method of manufacturing the same.

An aspect of the present disclosure may also provide a printed circuit board in which a bridge short-circuit risk may be decreased, and a method of manufacturing the same.

An aspect of the present disclosure may also provide a printed circuit board in which reliability may be provided, and a method of manufacturing the same.

According to an aspect of the present disclosure, a printed circuit board in which a structure in which side surfaces of pads provided for mounting a flip-chip die are surrounded by insulating walls is formed, such that a bridge short-circuit risk or the like is decreased at the time of assembling the flip-chip die and reliability is improved may be provided.

According to an aspect of the present disclosure, a printed circuit board may include: an insulating layer; a plurality of pads disposed on the insulating layer; and a plurality of insulating walls disposed on the insulating layer and cover side surfaces of the plurality of pads, respectively, but are not disposed on upper surfaces of the plurality of pads. The plurality of insulating walls are disposed to be spaced apart from each other on the first insulating layer.

According to another aspect of the present disclosure, a printed circuit board may include: a plurality of pads; and an insulating layer covering a lower surface and a side surface of each of the plurality of pads and having a recess disposed between at least a portion of the plurality of pads. An upper surface of the insulating layer is disposed on substantially the same level as an upper surface of each of the plurality of pads or is disposed on a level above the upper surface of each of the plurality of pads.

According to another aspect of the present disclosure, a method of manufacturing a printed circuit board may include: forming a plurality of pads and conductive patterns on a carrier substrate; forming an insulating layer on the carrier substrate, the insulating layer embedding at least portions of each of the plurality of pads and the conductive patterns therein; removing the carrier substrate; and forming a recess in the insulating layer by removing the conductive patterns.

According to another aspect of the present disclosure, a printed circuit board may include: an insulating layer including a plurality of rings spaced apart from each other and protruding from a surface of the insulating layer; and a plurality of pads respectively disposed in the plurality of rings.

According to another aspect of the present disclosure, a method of manufacturing a printed circuit board may include forming pads and conductive patterns spaced apart from each other on a carrier substrate; forming an insulating layer on the carrier substrate to fill spaces between the pads and the conductive patterns and covering the pads and the conductive patterns; removing the carrier substrate; and removing the conductive patterns so as to form a plurality of ring provided by the insulating layer which the pads are respectively disposed in.

DETAILED DESCRIPTION

Hereinafter, exemplary embodiments in the present disclosure will be described with reference to the accompanying drawings. In the accompanying drawings, shapes, sizes, and the like, of components may be exaggerated or shortened for clarity.

Herein, a lower side, a lower portion, a lower surface, and the like, are used to refer to a downward direction in relation to cross sections of the drawings for convenience, while an upper side, an upper portion, an upper surface, and the like, are used to refer to an opposite direction to the downward direction. However, these directions are defined for convenience of explanation, and the claims are not particularly limited by the directions defined as described above, and concepts of upper and lower portions may be exchanged with each other.

The term “an exemplary embodiment” used herein does not refer to the same exemplary embodiment, and is provided to emphasize a particular feature or characteristic different from that of another exemplary embodiment. However, exemplary embodiments provided herein are considered to be able to be implemented by being combined in whole or in part one with one another. For example, one element described in a particular exemplary embodiment, even if it is not described in another exemplary embodiment, may be understood as a description related to another exemplary embodiment, unless an opposite or contradictory description is provided therein.

Terms used herein are used only in order to describe an exemplary embodiment rather than limiting the present disclosure. In this case, singular forms include plural forms unless interpreted otherwise in context.

Electronic Device

Referring toFIG.1, an electronic device1000may accommodate a mainboard1010therein. The mainboard1010may include chip related components1020, network related components1030, other components1040, and the like, physically or electrically connected thereto. These components may be connected to others to be described below to form various signal lines1090.

Depending on a type of the electronic device1000, the electronic device1000may include other components that may or may not be physically or electrically connected to the mainboard1010. These other electronic components may include, for example, a camera1050, an antenna1060, a display1070, a battery1080, or the like. These other electronic components are not limited thereto, and may be an audio codec, a video codec, a power amplifier, a compass, an accelerometer, a gyroscope, a speaker, a mass storage unit (for example, a hard disk drive), a compact disk (CD) drive, a digital versatile disk (DVD) drive, or the like. These other electronic components may also include other electronic components used for various purposes depending on a type of electronic device1000, or the like.

FIG.2is a schematic perspective view illustrating an example of an electronic device.

Referring toFIG.2, an electronic device may be, for example, a smartphone1100. A motherboard1110may be accommodated in the smartphone1100, and various components1120may be physically or electrically connected to the motherboard1110. In addition, other components that may or may not be physically or electrically connected to the motherboard1110, such as a camera module1130and/or a speaker1140, may be accommodated in the smartphone1100. Some of the components1120may be the chip related components, for example, a component package1121, but are not limited thereto. The component package1121may have a form of a printed circuit board on which an electronic component including an active component and/or a passive component are surface-mounted. Alternatively, the component package1121may have a form of a printed circuit board in which an active component and/or a passive component are embedded. Meanwhile, the electronic device is not necessarily limited to the smartphone1100, but may be other electronic devices as described above.

Printed Circuit Board

FIG.3is a schematic cross-sectional view illustrating an example of a printed circuit board.

FIG.4is a schematic plan view illustrating the printed circuit board ofFIG.3.

Referring toFIGS.3and4, a printed circuit board100A according to an exemplary embodiment may include an insulating layer111, a plurality of pads121disposed on the insulating layer111, and a plurality of insulating walls131that cover side surfaces of the plurality of pads121, respectively, but are not disposed on upper surfaces of the plurality of pads121. As a non-restrictive example, the printed circuit board100A according to an exemplary embodiment may be used as a package substrate on which a flip-chip die is to be mounted, and the plurality of pads121may be provided as bumps for mounting the flip-chip die.

Herein, “insulating wall” may be used as a term distinguished from “insulating layer”. For example, the insulating layer may simply refer to a layer having insulating properties regardless of its shape. On the other hand, the insulating wall may refer to an insulating layer having a shape for surrounding at least a part of a side surface of a certain target component. That is, the insulating layer may have a more comprehensive meaning than the insulating wall, and the insulating wall may have a more subordinate meaning than the insulating layer. That is, if necessary, the insulating layer may include the insulating wall. In this respect, in cross section and/or in plan view, the insulating wall may have a smaller area than the insulating layer. In addition, a plurality of insulating walls may exist on the same level, and in this case, respective insulating walls may exist independently of each other on the same level.

Herein, cross section may refer to a cross-sectional shape of a target when the target is vertically cut in first and second directions, a cross-sectional shape of the target when the target is vertically cut in first and third directions, or a cross-sectional shape of the target when the target is viewed from side.

Herein, plan view may refer to a shape of the target in plan view when the target is horizontally cut in the second and third directions or a shape of the target in plan view when the target is viewed from the top or the bottom.

Herein, a first direction may refer to a stacked direction or a thickness direction, a second direction may refer to a width direction, and a third direction may refer to a length direction.

Meanwhile, as described above, in general, the high-performance semiconductor die has used the flip-chip mounting manner for high-density mounting. In this case, in accordance with miniaturization and performance improvement of semiconductors, an interval between connection terminals for flip-chip mounting has also continuously decreased. Accordingly, an opening size and its precision of a solder resist of a board, the degree of difficulty in forming solder bumps, the degree of difficulty of a bridge short-circuit in solder bonding of the semiconductor die, and the like, has continuously increased.

In this regard, in order to make a pitch of flip-chip connection bumps of the board finer, a structure in which a small amount of solder is used by forming copper posts on the board and underfills, non-conductive films (NCFs), non-conductive pastes (NCPs), and the like, are easily applied by securing an interval between the semiconductor die and the board has been studied.

Meanwhile, the board having such copper posts may be manufactured by forming a seed layer on a surface of the board on which the solder resist is formed, using chemical copper plating, sputtering, or the like, performing a photolithography process such as exposure, development, and peeling using a dry film, and then performing an etching process on the seed layer.

However, in this case, there may be a difficulty in securing close adhesion of the seed layer formed on the solder resist in a manufacturing process, and there may be a restriction in a design rule for realizing a fine pitch of the bumps, for example, the necessity to open a fine solder resist, a difficulty in reducing a diameter of the copper posts due to a solder resist size and an exposure matching tolerance of the copper posts, and a bridge short-circuit risk or the like at the time of assembling the semiconductor die having the fine pitch of the bumps.

On the other hand, in the printed circuit board100A according to an exemplary embodiment, a structure in which the side surfaces of the plurality of pads121provided for mounting the flip-chip die are approximately surrounded by the plurality of insulating walls131may be formed, such that the bridge short-circuit risk or the like at the time of assembling the flip-chip die may be decreased, and reliability may be improved. For example, the structure according to an exemplary embodiment may be basically a structure in which the side surfaces of the plurality of pads121provided as the bumps for mounting the flip-chip die are surrounded by the plurality of insulating walls131, respectively. Therefore, solders or the like may not be attached to the side surfaces of the plurality of pads121, and the bridge short-circuit risk may thus be decreased.

In addition, in the printed circuit board100A according to an exemplary embodiment, the seed layer does not need to be formed on the solder resist unlike the board having the copper posts, and a solder resist opening of bump connection parts may be changed by a recess formation process, and thus, a restriction in a design rule may also be solved. In addition, the plurality of pads121may be formed on a metal layer of a carrier substrate, and resultantly, very excellent height uniformity may be realized. In addition, since a roughness shape may be transferred from a metal pattern subjected to roughening treatment to a surface of the insulating layer111subjected to an etching process in an initial manufacturing operation, the surface of the insulating layer111may have high close adhesion with a molding and/or an underfill when the printed circuit board is applied to a package structure later, and may realize high reliability. In addition, roughening treatment may also be performed on the plurality of insulating walls131, and stable close adhesion may thus be secured.

Meanwhile, in the printed circuit board100A according to an exemplary embodiment, the plurality of insulating walls131may cover the side surfaces of the plurality of pads121, respectively, but may not be disposed on the upper surfaces of the plurality of pads121. In this respect, each of the plurality of insulating walls131may be in direct contact with the side surface of each of the plurality of pads121, but may be spaced apart from the upper surface of each of the plurality of pads121. Accordingly, connection terminals of the flip-chip die may be more stably put on the pads121in mounting the flip-chip die, and bonding areas with connection members such as solders may be increased, such that close adhesion and reliability may be improved.

In this respect, each the plurality of insulating walls131may have each of a plurality of cavities131rin which each of the plurality of pads121is disposed, and each of the plurality of cavities131rmay entirely open the upper surface of each of the plurality of pads121. In addition, in cross section, a width of each of the plurality of cavities131rmay be substantially constant.

Herein, “substantially constant” may be a concept including a process error or a position deviation occurring in a manufacturing process, an error at the time of performing measurement, and the like. For example, the meaning that the width of the cavity of the insulating wall is substantially constant may be that there is little deviation in the width of the cavity, for example, little deviation between widths at the uppermost side and the lowermost side of the same insulating wall because the side surface of the insulating wall has an approximately vertical shape in cross section.

Meanwhile, in the printed circuit board100A according to an exemplary embodiment, each of the plurality of pads121may have an approximately circular shape in plan view. In addition, each of the plurality of insulating walls131surrounding the plurality of pads121may have an approximately circular ring shape. However, each of the plurality of pads121and the plurality of insulating walls131is not limited thereto. For example, each of the plurality of pads121may have various shapes such as a quadrangular shape and an elliptical shape, and each of the plurality of insulating walls131may have the corresponding various shapes such as a quadrangular ring shape and an elliptical ring shape.

Meanwhile, in the printed circuit board100A according to an exemplary embodiment, the plurality of insulating walls131may be integrated with the insulating layer111without a boundary line therebetween. For example, the plurality of insulating walls131may be a single component integrated with the insulating layer111. Accordingly, the plurality of insulating walls131may include the same insulating material as the insulating layer111. As such, the plurality of insulating walls131are not additionally formed using a separate material, and may be formed by a recess forming process or the like in the insulating layer111, and a restriction in a design rule may thus be effectively solved.

In this respect, the insulating layer111may include the plurality of insulating walls131, and the insulating layer111including the plurality of insulating walls131may cover lower surfaces and the side surfaces of the pads121.

Meanwhile, in the printed circuit board100A according to an exemplary embodiment, the plurality of insulating walls131may be disposed to be spaced apart from each other on the insulating layer111, and accordingly, a bridge short-circuit risk may be more effectively decreased. In plan view, each of the plurality of insulating walls131may continuously surround the side surface of each of the plurality of pads121, which may be preferable in terms of the decrease in the bridge short-circuit risk, but the present disclosure is not limited thereto.

Meanwhile, in the printed circuit board100A according to an exemplary embodiment, a recess R may exist between the plurality of insulating walls131and/or around the plurality of insulating walls131. The recess R may be a single continuous recess R. The plurality of pads121may not be disposed in the recess R. The recess R may be disposed on substantially the same level as the plurality of pads121. It may be determined in the first direction whether or not components are disposed on substantially the same level. The plurality of insulating walls131may have ring shapes continuously surrounding the plurality of pads121independently through the recess R, which may be preferable in decreasing the bridge short-circuit risk.

Meanwhile, in the printed circuit board100A according to an exemplary embodiment, a height of each of the plurality of insulating walls131on the insulating layer111may be greater than that of each of the plurality of pads121. As described above, when the insulating layer111includes the plurality of insulating walls131as the component integrated therewith, an upper surface of the insulating layer111may be disposed on a level above the upper surface of each of the plurality of pads121. A height difference (h2−h1) between these upper surfaces may be about 2 μm to 4 μm, but is not limited thereto. In this case, connection terminals may be stably put on the plurality of pads121at the time of mounting the flip-chip die. In addition, when solders are disposed on the plurality of pads121, an effect of suppressing overflow of the solders may be expected.

Components of the printed circuit board100A according to an exemplary embodiment will hereinafter be described in more detail with reference toFIGS.3and4.

The insulating layer111may include an insulating material. The insulating material may include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a material including an inorganic filler, an organic filler, and/or a glass fiber (or a glass cloth and/or a glass fabric) together with the thermosetting resin and the thermoplastic resin. The insulating material may be, for example, Ajinomoto Build-up Film (ABF), prepreg (PPG), resin coated copper (RCC), or the like, but is not limited thereto, and may be other polymer materials.

Each of the pads121may include a metal material. The metal material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The pads121may perform various functions depending on their designs. For example, the pads121may include ground pads, power pads, signal pads, and the like. Here, the signal pads may include pads for connection of various signals such as data signals except for ground, power, or the like. The pad121may include an electroplating layer (or electrolytic copper), but may not include an electroless plating layer (chemical copper) if necessary.

Each of the insulating walls131may include an insulating material. The insulating material may include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a material including an inorganic filler, an organic filler, and/or a glass fiber (or a glass cloth and/or a glass fabric) together with the thermosetting resin and the thermoplastic resin. The insulating material may be, for example, ABF, PPG, RCC, or the like, but is not limited thereto, and may also be other polymer materials. The insulating wall131may include the same insulating material as the insulating layer111, and the insulating wall131and the insulating layer111may be an integrated single and identical component without a boundary line therebetween.

FIG.5is a schematic cross-sectional view illustrating another example of a printed circuit board.

Referring toFIG.5, a printed circuit board100B according to another exemplary embodiment may include an insulating layer111, a plurality of pads121disposed on the insulating layer111, and a plurality of insulating walls131that cover side surfaces of the plurality of pads121, respectively, but are not disposed on upper surfaces of the plurality of pads121. As a non-restrictive example, the printed circuit board100B according to another exemplary embodiment may be used as a package substrate on which a flip-chip die is to be mounted, and the plurality of pads121may be provided as bumps for mounting the flip-chip die.

Meanwhile, in the printed circuit board100B according to another exemplary embodiment, a height of each of the plurality of insulating walls131on the insulating layer111may be substantially the same as a height of each of the plurality of pads121. As described above, when the insulating layer111includes the plurality of insulating walls131as the component integrated therewith, an upper surface of the insulating layer111may be disposed on substantially the same level as the upper surface of each of the plurality of pads121. For example, there may be little height difference (h2−h1) between these upper surfaces. For example, in a manufacturing process to be described later, a metal layer of a carrier substrate may include a copper (Cu) layer and a barrier layer including a metal having an etching property different from that of the copper layer, such as nickel (Ni) or titanium (Ti). In this case, when the metal layer is etched after detachment, the barrier layer may be etched after the copper (Cu) layer is etched. As a result, when the copper (Cu) layer is etched, the barrier layer may protect the plurality of pads121. Therefore, surfaces of the plurality of pads121may be substantially unaffected by the etching, and thus, a step portion may not be substantially generated. Therefore, if necessary, the surfaces of the plurality of pads121may be implemented to be substantially coplanar with surfaces of the plurality of insulating walls131.

Herein, “substantially the same height”, “disposed on substantially the same level, and/or “substantially coplanar with” may be concepts including a process error or a position deviation occurring in a manufacturing process, an error at the time of performing measurement, and the like. For example, the meaning that the upper surface of the insulating layer is disposed on substantially the same level as the upper surface of the pad may be that the upper surface of the insulating layer and the upper surface of the pad are disposed at approximately the same position in the first direction within a range including a slight error.

Other contents, for example, the contents described in the above-described printed circuit board100A may be applied to the printed circuit board100B according to another exemplary embodiment as long as they are not contradictory, and a description of overlapping contents will be omitted.

FIG.6is a schematic cross-sectional view illustrating another example of a printed circuit board.

FIG.7is a schematic cross-sectional view illustrating another example of a printed circuit board.

Referring toFIGS.6and7, each of printed circuit boards100C and100D according to other exemplary embodiments may include an insulating layer111, a plurality of pads121disposed on the insulating layer111, a plurality of insulating walls131that cover side surfaces of the plurality of pads121, respectively, but are not disposed on upper surfaces of the plurality of pads121, and a surface treatment layer190disposed on a surface of at least one of the plurality of pads121. As a non-restrictive example, each of the printed circuit boards100C and100D according to other exemplary embodiments may be used as a package substrate on which a flip-chip die is to be mounted, and the plurality of pads121may be provided as bumps for mounting the flip-chip die.

Meanwhile, each of the printed circuit boards100C and100D according to other exemplary embodiments may further include the surface treatment layer190, through which the flip-chip die may be more effectively mounted. The surface treatment layer190may be formed by, for example, electrolytic gold plating, electroless gold plating, organic solderability preservative (OSP) or electroless tin plating, electroless silver plating, electroless nickel plating/substituted gold plating, direct immersion gold (DIG) plating, hot air solder leveling (HASL), or the like. In this respect, the surface treatment layer190may include at least one of a nickel (Ni) layer191and a gold (Au) layer192, but is not limited thereto. As a non-restrictive example, the surface treatment layer190may include a nickel (Ni) layer191disposed on the surface of the pad121and a gold (Au) layer192disposed on a surface of the nickel (Ni) layer191, but is not limited thereto.

Meanwhile, in the printed circuit board100C according to another exemplary embodiment, an upper surface of the uppermost layer of the surface treatment layer190may be disposed on substantially the same level as an upper surface of the insulating wall131, and in the printed circuit board100D according to another exemplary embodiment, an upper surface of the uppermost layer of the surface treatment layer190may be disposed on a level above an upper surface of the insulating wall131, but the present disclosure is not limited thereto.

Other contents, for example, the contents described in the above-described printed circuit boards100A and100B may be applied to the printed circuit boards100C and100D according to other exemplary embodiments as long as they are not contradictory, and a description of overlapping contents will be omitted.

FIG.8is a schematic cross-sectional view illustrating another example of a printed circuit board.

Referring toFIG.8, a printed circuit board100E according to another exemplary embodiment may include a first insulating layer111, first pads121and second pads122disposed on an upper surface of the first insulating layer111, first insulating walls131disposed on the upper surface of the first insulating layer111and covering side surfaces of the first pads121, and second insulating walls132disposed on the upper surface of the first insulating layer111and covering side surfaces of the second pads122.

The printed circuit board100E according to another exemplary embodiment may further include a first wiring layer141disposed on a lower surface of the first insulating layer111, first connection vias151penetrating through the first insulating layer111and electrically connecting the first pads121to at least portions of the first wiring layer141, and/or second connection vias152penetrating through the first insulating layer111and electrically connecting the second pads122to at least other portions of the first wiring layer141, if necessary.

The printed circuit board100E according to another exemplary embodiment may further include a second insulating layer112disposed on the lower surface of the first insulating layer111and embedding at least portions of the first wiring layer141therein, a second wiring layer142disposed on a lower surface of the second insulating layer112, and/or a first via layer161penetrating through the second insulating layer112and electrically connecting at least portions of each of the first wiring layer141and the second wiring layer142to each other, if necessary.

The printed circuit board100E according to another exemplary embodiment may further include a third insulating layer113disposed on the lower surface of the second insulating layer112and embedding at least portions of the second wiring layer142therein, a third wiring layer143disposed on a lower surface of the third insulating layer113, and/or a second via layer162penetrating through the third insulating layer113and electrically connecting at least portions of each of the second wiring layer142and the third wiring layer143to each other, if necessary.

The printed circuit board100E according to another exemplary embodiment may further include a first passivation layer171disposed on the second insulating walls132and having first openings171hexposing at least portion of surfaces of the second pads122and/or a second passivation layer172disposed on the lower surface of the third insulating layer113and having second openings172hexposing at least portions of a surface of the third wiring layer143, if necessary. In one example, the first passivation layer171may be disposed on portions of upper surfaces of the second pads122.

Meanwhile, in the printed circuit board100E according to another exemplary embodiment, a structure in which the side surfaces of the pads121provided for mounting the flip-chip die are approximately surrounded by the first insulating walls131may be formed, such that the bridge short-circuit risk or the like at the time of assembling the flip-chip die may be decreased, and reliability may be improved. For example, the structure according to another exemplary embodiment may be basically a structure in which the side surfaces of the first pads121provided as the bumps for mounting the flip-chip die are surrounded by the first insulating walls131, respectively. Therefore, solders or the like may not be attached to the side surfaces of the first pads121, and the bridge short-circuit risk may thus be decreased. Similarly, a structure in which the side surfaces of the second pads122provided for assembling a package such as a board-on-board are approximately surrounded by the second insulating walls132may be formed, such that reliability or the like may be improved.

Meanwhile, in the printed circuit board100E according to another exemplary embodiment, as can be seen from a process to be described above, the seed layer does not need to be formed on the solder resist unlike the board having the copper posts, and a solder resist opening of bump connection parts may be changed by a recess formation process, and thus, a restriction in a design rule may also be solved. In addition, the first pads121and the second pads122may be formed on a metal layer of a carrier substrate, and resultantly, very excellent height uniformity may be realized. In addition, since a roughness shape may be transferred from a metal pattern subjected to roughening treatment to a surface of the first insulating layer111subjected to an etching process in an initial manufacturing operation, the surface of the first insulating layer111may have high close adhesion with a molding and/or an underfill when the printed circuit board is applied to a package structure later, and may realize high reliability. In addition, roughening treatment may also be performed on the first insulating walls131and the second insulating walls132, and stable close adhesion may thus be secured.

Meanwhile, in the printed circuit board100E according to another exemplary embodiment, the first insulating walls131may cover the side surfaces of the first pads121, but may not be disposed on upper surfaces of the first pads121. In addition, the second insulating walls132may cover the side surfaces of the second pads122but not be disposed on upper surfaces of the second pads122. Accordingly, connection terminals of the flip-chip die may be more stably put on the first pads121in mounting the flip-chip die, and bonding areas with connection members such as solders may be increased, such that close adhesion and reliability may be improved.

In this respect, the first insulating walls131and the second insulating walls132may have, respectively, first cavities131rin which the first pads121are disposed and second cavities132rin which the second pads122are disposed. The first cavity131rmay entirely open the upper surface of the first pad121, and the second cavity132rmay entirely open the upper surface of the second pad122. In addition, in cross section, a width of such a first cavity131rmay be substantially constant, and a width of such a second cavity132rmay be substantially constant.

Meanwhile, in the printed circuit board100E according to another exemplary embodiment, the first insulating walls131and the second insulating walls132may be integrated with the first insulating layer111without boundary lines therebetween. For example, the first insulating walls131and the second insulating walls132may be a single component integrated with the first insulating layer111. Accordingly, the first insulating walls131and the second insulating walls132may include the same insulating material as the first insulating layer111. As such, the first insulating walls131and the second insulating walls132are not additionally formed using a separate material, and may be formed by a recess forming process to be described later in the insulating layer111, and a restriction in a design rule may thus be effectively solved.

Meanwhile, in the printed circuit board100E according to another exemplary embodiment, a plurality of first pads121and a plurality of second pads122may be respectively disposed. In addition, a plurality of first insulating walls131and second insulating walls132surrounding the plurality of first pads121and the plurality of second pads122, respectively, may also be disposed. For example, each of the first insulating walls131may cover the side surface of each of the first pads121, but may not be disposed on the upper surface of each of the first pads121. In addition, each of the second insulating walls132may cover the side surface of each of the second pads122, but may not be disposed on the upper surface of each of the second pads122. The first insulating walls131may be disposed to be spaced apart from each other and the second insulating walls132may be disposed to be spaced apart from each other, and a bridge short risk may be more effectively decreased. In a plan view, each of the first insulating walls131may continuously surround the side surface of each of the first pads121and each of the second insulating walls132may continuously surround the side surface of each of the second pads122, which may be preferable in terms of the decrease in the bridge short risk, but the present disclosure is not necessarily limited thereto.

Meanwhile, in the printed circuit board100E according to another exemplary embodiment, a recess R may exist between the first insulating walls131and/or between the first insulating wall131and the second insulating wall132. The recess R between the first insulating walls131and/or between the first insulating wall131and the second insulating wall132may be a single continuous recess R. The first pads121and/or the second pads122may not be disposed in the recess R. The first insulating walls131and the second insulating walls132may have ring shapes continuously surrounding the first pads121and the second pads122independently through the recess R, which may be more preferable in decreasing the bridge short-circuit risk.

Meanwhile, in the printed circuit board100E according to another exemplary embodiment, the first pads121and the first insulating walls131surrounding the first pads121may be disposed in a center region on the first insulating layer111, and the second pads122and the second insulating walls132surrounding the second pads122may be disposed in a side region on the first insulating layer111. The first pads121may be used as a bump for mounting the flip-chip die, and the second pad122may be used as bumps for connection of the board-on-board. In this respect, the second pad122may be greater than the first pad121. For example, in cross section, a width of the second pad122may be greater than that of the first pad121.

Herein, the center region may be an inner region in which an electronic component such as a flip-chip die is disposed, and the side region may be an outer region in which connection members such as solder ball joints for connection of the board-on-board are disposed. Here, the inner region and the outer side may be determined in plan view.

Meanwhile, in the printed circuit board100E according to another exemplary embodiment, a height of the first insulating wall131may be greater than that of the upper surface of the first pad121. In addition, a height of the second insulating wall132may be higher than that of the upper surface of the second pad122. In this case, connection terminals may be stably put on the first pads121at the time of mounting the flip-chip die. In addition, when solders are disposed as the connection members on the first pads121and/or the second pads122, an effect of suppressing overflow of the solders may be expected. However, the present disclosure is not limited thereto, and as described above, when an etching barrier layer is used in a process, such a height difference, that is, a step portion may not substantially exist.

Meanwhile, in the printed circuit board100E according to another exemplary embodiment, each of the first connection via151and the second connection via152may have a tapered shape of which a width of an upper surface is smaller than that of a lower surface in cross section. For example, the first connection via151may have a smaller width in a surface thereof connected to the first pad121than a surface thereof connected to at least a portion of the first wiring layer141. The second connection via152may have a smaller width in a surface thereof connected to the second pad122than a surface thereof connected to at least other portion of the first wiring layer141. Accordingly, a restriction in a design rule may be further solved. For example, diameters, for example, widths in cross section, of the first pad121and the second pad122each connected to the first connection via151and the second connection via152may be further decreased.

Meanwhile, in the printed circuit board100E according to another exemplary embodiment, the first insulating layer111and the second insulating layer112may include different insulating materials. For example, the first insulating layer111may include a material on which a semi additive process (SAP) may be performed, such as an insulating material that does not include a glass fiber, so as to be advantageous in forming a fine circuit. Specifically, the first insulating layer111may include ABF, but is not limited thereto. On the other hand, the second insulating layer112may include a material having a high modulus, such as an insulating material including a glass fiber, so as to be advantageous in controlling warpage. Specifically, the second insulating layer112may include an insulating material of PPG or RCC, but is not limited thereto. Similarly, the third insulating layer113, which is the outermost layer on an opposite side, may include the same insulating material as the first insulating layer111, and when the number of second insulating layers112is plural, the respective layers may include the same insulating material, but are not limited thereto.

Herein, the same insulating material may refer to the same type of insulating material as well as the completely same insulating material. Accordingly, compositions of the insulating materials may be substantially the same as each other, but specific composition ratios of these compositions may be slightly different from each other.

Components of the printed circuit board100E according to another exemplary embodiment will hereinafter be described in more detail with reference toFIG.8.

Each of the first to third insulating layers111,112, and113may include an insulating material. The insulating material may include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a material including an inorganic filler, an organic filler, and/or a glass fiber (or a glass cloth and/or a glass fabric) together with the thermosetting resin and the thermoplastic resin. The insulating material may be, for example, ABF, PPG, RCC, or the like, but is not limited thereto, and may also be other polymer materials. As a non-restrictive example, each of the first insulating layer111and the third insulating layer113may include ABF, and the second insulating layer112may include PPG, but the present disclosure is not limited thereto. The first insulating layer111and the third insulating layer113may be the outermost insulating layers, and the second insulating layer112may be an internal build-up layer. The second insulating layer112corresponding to the build-up layer may be a single layer as illustrated inFIG.8, but may be a plurality of layers unlikeFIG.8, and the specific number of layers in the second insulating layer112is not particularly limited.

Each of the first and second pads121and122may include a metal material. The metal material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The first and second pads121and122may perform various functions depending on their designs. For example, the first and second pads121and122may include ground pads, power pads, signal pads, and the like. Here, the signal pads may include pads for connection of various signals such as data signals except for ground, power, or the like. The number of each of first and second pads121and122is not particularly limited, and may be plural. Each of the first and second pads121and122may include an electroplating layer (or electrolytic copper), but may not include an electroless plating layer (chemical copper) if necessary. For example, the number of metal layers of each of the first and second pads121and122may be smaller than the number of metal layers of each of the first to third wiring layers141,142and143.

Each of the first and second insulating walls131and132may include an insulating material. The insulating material may include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a material including an inorganic filler, an organic filler, and/or a glass fiber (or a glass cloth and/or a glass fabric) together with the thermosetting resin and the thermoplastic resin. The insulating material may be, for example, ABF, PPG, RCC, or the like, but is not limited thereto, and may also be other polymer materials. The number of each of first and second insulating walls131and132is not particularly limited, and may be plural. The first and second insulating walls131and132may include the same insulating material as the insulating layer111, and the first and second insulating walls131and132and the insulating layer111may be an integrated single and identical component without boundary lines therebetween.

Each of the first to third wiring layers141,142, and143may include a metal material. The metal material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The first to third wiring layers141,142, and143may perform various functions depending on designs of corresponding layers. For example, the first to third wiring layers141,142, and143may include ground patterns, power patterns, signal patterns, and the like. Here, the signal patterns may include various signals except for the ground patterns, the power patterns, and the like, such as data signals. Each of these patterns may include a line pattern, a plane pattern, and/or a pad pattern. The second wiring layer142formed on the second insulating layer112, which is the build-up layer, may be a single layer as illustrated inFIG.8, but may be a plurality of layers unlikeFIG.8, and the specific number of layers in the second wiring layer142is not particularly limited. Each of the first to third wiring layers141,142, and143may include an electroless plating layer (chemical copper) and an electroplating layer (or electrolytic copper).

Each of the first and second connection vias151and152may include a metal material. The metal material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The first and second connection vias151and152may perform various functions depending on designs thereof. The first and second connection vias151and152may include connection vias for signal connection, connection vias for ground connection, connection vias for power connection, and the like. The first and second connection vias151and152may have shapes tapered in the same direction as connection vias of the first and second via layers161and162. Each of the first and second connection vias151and152may be entirely filled with a metal material, or the metal material may be formed along a wall surface of each of via holes. The number of each of first and second connection vias151and152is not particularly limited, and may be plural. The first and second connection vias151and152may have a stack via relationship or a staggered via relationship with the connection vias of the first and second via layers161and162, respectively. Each of the first and second connection vias151and152may include an electroless plating layer (chemical copper) and an electroplating layer (or electrolytic copper).

Each of the first and second via layers161and162may include a metal material. The metal material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The first and second via layers161and162may perform various functions depending on designs of corresponding layers. The first and second via layers161and162may include connection vias for signal connection, connection vias for ground connection, connection vias for power connection, and the like. The first and second via layers161and162may include connection vias having shapes tapered in the same direction. For example, each of the connection vias of the first and second via layers161and162may have a tapered shape of which a width of an upper surface is narrower than a width of a lower surface in cross section. Each of the connection vias of the first and second via layers161and162may be completely filled with a metal material, or the metal material may be formed along a wall surface of each of via holes. The connection vias of the first and second via layers161and162may have a stack via relationship or a staggered via relationship with each other. The second via layer162formed in the second insulating layer112, which is the build-up layer, may be a single layer as illustrated inFIG.8, but may be a plurality of layers unlikeFIG.8, and the specific number of layers in the second via layer162is not particularly limited. Each of the first and second via layers161and162may include an electroless plating layer (chemical copper) and an electroplating layer (or electrolytic copper). The second via layer162may be formed by the same plating process as the third wiring layer143to be integrated with the third wiring layer143without a boundary line therebetween. The first via layer161may be formed by the same plating process as the second wiring layer142to be integrated with the second wiring layer142without a boundary line therebetween.

Each of the first and second passivation layers171and172may include a known solder resist layer. However, each of the first and second passivation layers171and172is not limited thereto, and may also include, for example, ABF including a thermosetting resin and an inorganic filler. The first and second passivation layers171and172may be disposed on the outermost sides of the printed circuit board100E to protect patterns and the like inside the printed circuit board100E from external impact. The first and second passivation layers171and172may have one or more first and second openings171hand172h,respectively. For example, the first passivation layer171may have one or more first openings171hexposing at least portions of the surfaces of the second pads122. In addition, the second passivation layer172may have one or more second openings172hexposing at least portions of the surface of the third wiring layer143. Surface treatment layers including a nickel (Ni) layer and/or a gold (Au) layer may be formed on the surfaces exposed through the first and second openings171hand172h.

Other contents, for example, the contents described in the above-described printed circuit boards100A,100B,100C, and100D may be applied to the printed circuit board100E according to another exemplary embodiment as long as they are not contradictory, and a description of overlapping contents will be omitted.

FIGS.9A to9Hare schematic cross-sectional views illustrating an example of processes of manufacturing the printed circuit board ofFIG.8.

Referring toFIG.9A, a carrier substrate500having metal layers510formed on one surface or both surfaces thereof may be prepared, and first and second pads121and122and conductive patterns125may be formed on the metal layers510of the carrier substrate500. The carrier substrate500may be a copper clad laminate (CCL) or the like, but is not limited thereto. In addition, various carrier substrates that may be used as a detachment carrier may be used as the carrier substrate500without being particularly limited. The metal layer510may include a copper (Cu) layer such as copper foil, but is not limited thereto, and may further include another metal layer. A release layer for easy detachment may be disposed between the metal layer510and the carrier substrate500. The first and second pads121and122and the conductive patterns125may be formed by a plating process such as an additive process (AP), a semi-AP (SAP), a modified SAP (MSAP), or tenting (TT) using the metal layer510as a seed layer.

Referring toFIG.9B, first insulating layers111embedding at least portions of each of the first and second pads121and122and the conductive patterns125therein may be formed on the metal layers510of the carrier substrate500. The first insulating layer111may be formed by laminating an unhardened layer including the above-described insulating material and then hardening the unhardened layer. Alternatively, the first insulating layer111may be formed by applying the above-described insulating material and then hardening the insulating material. The insulating material may fill gaps between adjacent patterns among the first and second pads121and122and the conductive patterns125and cover the first and second pads121and122and the conductive patterns125. Thereafter, via holes may be formed in the first insulating layers111using a laser drill or the like, and a plating process such as an AP, an SAP, an MSAP, or TT may be performed on the first insulating layers111to form first wiring layers141and first and second connection vias151and152.

Referring toFIG.9C, second insulating layers112embedding at least portions of the first wiring layers141therein may be formed on the first insulating layers111. The second insulating layer112may be formed by laminating an unhardened layer including the above-described insulating material and then hardening the unhardened layer. Alternatively, the second insulating layer112may be formed by applying the above-described insulating material and then hardening the insulating material. Thereafter, via holes may be formed in the second insulating layers112using a laser drill or the like, and a plating process such as an AP, an SAP, an MSAP, or TT may be performed on the second insulating layers112to form second wiring layers142and first via layers161. Thereafter, third insulating layers113embedding at least portions of the second wiring layers142therein may be formed on the second insulating layers112. The third insulating layer113may be formed by laminating an unhardened layer including the above-described insulating material and then hardening the unhardened layer. Alternatively, the third insulating layer113may be formed by applying the above-described insulating material and then hardening the insulating material. Thereafter, via holes may be formed in the third insulating layers113using a laser drill or the like, and a plating process such as an AP, an SAP, an MSAP, or TT may be performed on the third insulating layers113to form third wiring layers143and second via layers162.

Referring toFIG.9D, the carrier substrate500may be removed. For example, the carrier substrate500and the metal layer510may be separated from each other. The release layer may be used to separate the carrier substrate500and the metal layer510from, but is not limited thereto.

Referring toFIG.9E, the metal layer510may be removed. The metal layer510may be removed using, for example, a seed etching process. In this case, a seed layer of the third wiring layer143may also be removed together with the metal layer510. In a process of removing the metal layer510, surfaces of the first and second pads121and122may also be partially removed by etching, and resultantly, each of the surfaces of the first and second pads121and122may have a step portion from a surface of the first insulating layer111.

However, if necessary, the metal layer510may include a copper (Cu) layer and a barrier layer including a metal having an etching property different from that of the copper layer, such as nickel (Ni) or titanium (Ti). In this case, when the metal layer510is etched, the barrier layer may be etched after the copper (Cu) layer is etched. As a result, when the copper (Cu) layer is etched, the barrier layer may protect the first and second pads121and122, and thus, the surfaces of the first and second pads121and122may be substantially unaffected by the etching. Therefore, the step portion may not be substantially generated.

Referring toFIG.9F, first and second passivation layers171and172may be formed. First and second openings171hand172hmay be formed by patterning the first and second passivation layers171and172. The first and second passivation layers171and172may be formed by, for example, a method of forming solder resist layers and then performing patterning using a photolithography process or the like so as to have the first and second openings171hand172h,respectively, but are not limited thereto.

Referring toFIG.9G, a first dry film521may be disposed on the first insulating layer111and the first passivation layer171. In addition, a second dry film522may be disposed on the second passivation layer172. Thereafter, exposing parts521pexposing the conductive patterns125may be formed by patterning the first dry film521by a photolithography process such as exposure and development.

Referring toFIG.9H, the conductive patterns125may be removed. For example, the conductive patterns125selectively exposed through the exposing parts521pmay be removed by an etching process. When the conductive patterns125are removed, a recess R may be formed. First and second insulating walls131and132covering side surfaces of the first and second pads121and122may be formed on the first insulating layer111by the recess R. Thereafter, the first and second dry films521and522may be removed. In this case, for example, a known stripper may be used.

If necessary, a surface treatment layer may be further formed on the first and second pads121and122. The surface treatment layer may be formed by, for example, electrolytic gold plating, electroless gold plating, OSP or electroless tin plating, electroless silver plating, electroless nickel plating/substituted gold plating, DIG plating, HASL, or the like. The surface treatment layer may include at least one of a nickel (Ni) layer and a gold (Au) layer, but is not limited thereto.

The printed circuit board100E according to another exemplary embodiment described above may be manufactured through the series of processes described above, but this is only one manufacturing example, and the printed circuit board100E according to another exemplary embodiment described above may also be manufactured by processes different from the processes described above.

Other contents, for example, the contents described in the above-described printed circuit boards100A,100B,100C,100D, and100E may be applied to processes of manufacturing the printed circuit board ofFIG.8as long as they are not contradictory, and a description of overlapping contents will be omitted.

FIG.10is a schematic cross-sectional view illustrating a modified example of the printed circuit board ofFIG.8.

Referring toFIG.10, a printed circuit board100F according to a modified example may have a package structure in which an electronic component210is surface-mounted and disposed on the above-described printed circuit board100E and a separate wiring board220is then disposed on the electronic component210in a board-on-board form. For example, the printed circuit board100F according to a modified example may be different from the above-described printed circuit board100E in that it further includes the electronic component210disposed on the first insulating layer111and including connection terminals212electrically connected to the first pads121through first connection members231and the wiring board220disposed on the electronic component210and including connection pads222electrically connected to the second pads122through second connection members232. The printed circuit board100F according to a modified example may further include a molding material240molding a space between the first insulating layer111and the wiring board220and/or electrical connection metal250connected to the third wiring layer143, if necessary. The above-described printed circuit board100E may be used as a package substrate on which a flip-chip die or the like is to be mounted.

The electronic components210may be various types of active components and/or passive components. For example, the electronic component210may include various types of integrated circuit (IC) dies211such as a flip-chip die. Alternatively, the electronic component210may include a chip-type passive component such as a chip capacitor such as a multilayer ceramic capacitor (MLCC) or a chip inductor such as a power inductor (PI). Alternatively, the electronic component210may include a silicon capacitor. As such, a type of the electronic component210is not particularly limited. The electronic component210may include the connection terminals212including a metal material such as copper (Cu) or aluminum (Al). The electronic component210may be surface-mounted in a face-down form through the connection terminals212. The electronic component210may have a front surface on which the connection terminals212are disposed and a back surface on which the connection terminals212are not disposed.

The wiring board220may be an interposer substrate for connection with another package or a package substrate on which another semiconductor die or the like is to be directly mounted. The wiring board220may include an insulating layer221, connection pads222and223disposed on both sides of the insulating layer221, through vias224penetrating through the insulating layer221and electrically connecting the connection pads222and223to each other, and passivation layers225and226disposed on both sides of the insulating layer221and covering at least portions of the connection pads222and223. However, this is only an example, and insulating layers, wiring layers, and via layers constituting the wiring board220may also be further disposed in various forms.

The insulating layer221may include an insulating material. The insulating material may include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a material including an inorganic filler, an organic filler, and/or a glass fiber (or a glass cloth and/or a glass fabric) together with the thermosetting resin and the thermoplastic resin. The insulating material may be, for example, ABF, PPG, RCC, or the like, but is not limited thereto, and may also be other polymer materials.

Each of the connection pads222and223may include a metal material. The metal material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The connection pads222and223may perform various functions depending on their designs. For example, the connection pads222and223may include ground pads, power pads, signal pads, and the like. Here, the signal pads may include pads for connection of various signals such as data signals except for ground, power, or the like. The number of each of connection pads222and223is not particularly limited, and may be plural.

Each of the through vias224may include a metal material. The metal material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The through vias224may perform various functions depending on their designs. The through vias224may include through vias for signal connection, through vias for ground connection, through vias for power connection, and the like. Each of the through vias224may have various shapes such as an hourglass shape and a cylindrical shape.

Each of the passivation layers225and226may include a known solder resist layer. However, each of the passivation layers225and226is not limited thereto, and may include, for example, ABF, including a thermosetting resin and an inorganic filler. Each of the passivation layers225and226may have one or more openings. A surface treatment layer including a nickel (Ni) layer and/or a gold (Au) layer may be formed on surfaces of the connection pads222and223exposed through these openings.

Each of the first and second connection members231and232may include a low melting metal having a lower melting point than copper (Cu), such as tin (Sn) or alloys including tin (Sn). For example, each of the first and second connection members231and232may include a solder. For example, each of the first and second connection members231and232may have a solder ball joint shape. The numbers, intervals, disposition forms, and the like, of first and second connection members231and232are not particularly limited.

The molding material240may mold the electronic component210, the first and second connection members231and232, and the like, to protect the electronic component210, the first and second connection members231and232, and the like. The molding material240may include an epoxy resin or the like, but is not particularly limited thereto, and may include other known materials.

The electrical connection metals250may physically or electrically externally connect the printed circuit board100F For example, the printed circuit board100F may be a ball grid array (BGA)-type package board. Each of the electrical connection metals250may include a low melting metal having a lower melting point than copper (Cu), such as tin (Sn) or alloys including tin (Sn). For example, each of the electrical connection metals250may include a solder, but this is only an example, and a material of each of the electrical connection metals250is not particularly limited thereto. Each of the electrical connection metals250may be a land, a ball, a pin, or the like. The electrical connection metals250may be formed as a multilayer or single layer structure. When the electrical connection metals250formed as a multilayer structure, the electrical connection metals250may include a copper (Cu) pillar and a solder. When the electrical connection metals250are formed as a single layer structure, the electrical connection metals250may include a tin-silver solder or copper (Cu). However, this is only an example, and the electrical connection metals250are not limited thereto. The number, an interval, a disposition form, and the like, of electrical connection metals250are not particularly limited, but may be sufficiently modified depending on design particulars.

Other contents, for example, the contents described in the above-described printed circuit boards100A,100B,100C,100D, and100E may be applied to the printed circuit board100F according to a modified example as long as they are not contradictory, and a description of overlapping contents will be omitted.

FIG.11is a schematic cross-sectional view illustrating another modified example of the printed circuit board ofFIG.8.

Referring toFIG.11, a printed circuit board100G according to another modified example may have a package structure in which an electronic component210is surface-mounted and disposed on a separate wiring board320and the above-described printed circuit board100E is then disposed on the electronic component210in a board-on-board form. For example, the printed circuit board100G according to another modified example may be different from the above-described printed circuit board100E in that it further includes the wiring board320disposed on the first insulating layer111and including connection pads P1and P2disposed in a center region and a side region thereof and the electronic component210disposed between the first insulating layer111and the wiring board320and having a front surface on which connection terminals212are disposed and a back surface opposing the front surface. The connection pads P1and P2of the wiring board320may be electrically connected to the connection terminals212of the electronic component210and the second pads122through first and second connection members231and232, respectively. The printed circuit board100G according to another modified example may further include a molding material240molding a space between the first insulating layer111and the wiring board320and/or electrical connection metal250connected to the wiring layer325, if necessary. In addition, the printed circuit board100G according to another modified example may further include conductive members260connecting the first pads121and the back surface of the electronic component210to each other. The above-described printed circuit board100E may be used as an upper substrate having a heat dissipation function. Here, the upper board may be an interposer substrate for connection with another package or a package substrate on which another semiconductor die or the like is to be directly mounted.

The wiring board320may be a package board on which the electronic component210is to be mounted. The wiring board320may include a plurality of insulating layers321and322, a plurality of wiring layers323,324, and325, a plurality of via layers326and327, and a plurality of passivation layers328and329. The plurality of insulating layers321and322, the plurality of wiring layers323,324, and325, and the plurality of via layers326and327constituting the wiring board320may be disposed in various forms. For example, the wiring board320may have a form of a substrate having a core or have a form of a coreless substrate.

Each of the insulating layers321and322may include an insulating material. The insulating material may include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a material including an inorganic filler, an organic filler, and/or a glass fiber (or a glass cloth and/or a glass fabric) together with the thermosetting resin and the thermoplastic resin. The insulating material may be, for example, ABF, PPG, RCC, or the like, but is not limited thereto, and may also be other polymer materials.

Each of the wiring layers323,324, and325may include a metal material. The metal material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The wiring layers323,324, and325may perform various functions depending on their designs. For example, the wiring layers323,324, and325may include ground patterns, power patterns, signal patterns, and the like. Here, the signal patterns may include various signals except for the ground patterns, the power patterns, and the like, such as data signals. Each of these patterns may include a line pattern, a plane pattern, and/or a pad pattern. The number of each of connection pads P1and P2is not particularly limited, and may be plural.

Each of the via layers326and327may include a metal material. The metal material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The via layers326and327may perform various functions depending on designs of corresponding layers. The via layers326and327may include connection vias for signal connection, connection vias for ground connection, connection vias for power connection, and the like. The via layers326and327may include connection vias having shapes tapered in the same direction. Each of the connection vias of the via layers326and327may be completely filled with a metal material, or the metal material may be formed along a wall surface of each of via holes. The connection vias of the via layers326and327may have a stack via relationship or a staggered via relationship with each other.

Each of the passivation layers328and329may include a known solder resist layer. However, each of the passivation layers328and329is not limited thereto, and may include, for example, ABF, including a thermosetting resin and an inorganic filler. Each of the passivation layers328and329may have one or more openings. A surface treatment layer including a nickel (Ni) layer and/or a gold (Au) layer may be formed on at least portions of surfaces of the outermost wiring layers323and325exposed through these openings.

The conductive members260may effectively transfer heat generated from the back surface of the electronic component210to an upper board. The conductive members260may include various types of thermally conductive pastes and/or thermally conductive resins, and specific materials of the conductive members260are not particularly limited.

Other contents, for example, the contents described in the above-described printed circuit boards100A,100B,100C,100D,100E, and100F may be applied to the printed circuit board100G according to another modified example as long as they are not contradictory, and a description of overlapping contents will be omitted.

FIG.12is a schematic cross-sectional view illustrating another example of a printed circuit board.

Referring toFIG.12, a printed circuit board100H according to another exemplary embodiment may include a first insulating layer111, first pads121and second pads122disposed on an upper surface of the first insulating layer111, first insulating walls131disposed on the upper surface of the first insulating layer111and covering side surfaces of the first pads121, and second insulating walls132disposed on the upper surface of the first insulating layer111and covering side surfaces of the second pads122.

The printed circuit board100H according to another exemplary embodiment may further include a first wiring layer141disposed on a lower surface of the first insulating layer111, first connection vias151penetrating through the first insulating layer111and electrically connecting the first pads121to at least portions of the first wiring layer141, and/or second connection vias152penetrating through the first insulating layer111and electrically connecting the second pads122to at least other portions of the first wiring layer141, if necessary.

The printed circuit board100H according to another exemplary embodiment may further include a second insulating layer112disposed on the lower surface of the first insulating layer111and embedding at least portions of the first wiring layer141therein, a second wiring layer142disposed on a lower surface of the second insulating layer112, and/or a first via layer161penetrating through the second insulating layer112and electrically connecting at least portions of each of the first wiring layer141and the second wiring layer142to each other, if necessary.

The printed circuit board100H according to another exemplary embodiment may further include a third insulating layer113disposed on the lower surface of the second insulating layer112and embedding at least portions of the second wiring layer142therein, a third wiring layer143disposed on a lower surface of the third insulating layer113, and/or a second via layer162penetrating through the third insulating layer113and electrically connecting at least portions of each of the second wiring layer142and the third wiring layer143to each other, if necessary.

The printed circuit board100H according to another exemplary embodiment may further include a first passivation layer171disposed on the second insulating walls132and having first openings171hexposing at least portion of surfaces of the second pads122and/or a second passivation layer172disposed on the lower surface of the third insulating layer113and having second openings172hexposing at least portions of a surface of the third wiring layer143, if necessary.

Meanwhile, in the printed circuit board100H according to another exemplary embodiment, a recess R may exist between the first insulating walls131and/or between the first insulating wall131and the second insulating wall132, and at least portions of the first passivation layer171may extend to at least portions of the recess R. For example, the first passivation layer171may cover at least portions of wall surfaces and at least portions of a bottom surface of the recess R. For example, the first passivation layer171may extend from an upper surface of the second insulating wall132to cover a side surface of the second insulating wall132so that the first passivation layer171may be in contact with the first insulating layer111. Therefore, close adhesion of the first passivation layer171may be further secured, and reliability may be further improved.

Other contents, for example, the contents described in the above-described printed circuit boards100A,100B,100C,100D,100E,100F, and100G may be applied to the printed circuit board100H according to another exemplary embodiment as long as they are not contradictory, and a description of overlapping contents will be omitted.

FIGS.13A to13Hare schematic cross-sectional views illustrating an example of processes of manufacturing the printed circuit board ofFIG.12.

Referring toFIG.13A, a carrier substrate500having metal layers510formed on one surface or both surfaces thereof may be prepared, and first and second pads121and122and conductive patterns125may be formed on the metal layers510of the carrier substrate500.

Referring toFIG.13B, first insulating layers111embedding at least portions of each of the first and second pads121and122and the conductive patterns125therein may be formed on the metal layers510of the carrier substrate500. Thereafter, first wiring layers141and first and second connection vias151and152may be formed.

Referring toFIG.13C, second insulating layers112embedding at least portions of the first wiring layers141therein may be formed on the first insulating layers111. Thereafter, second wiring layers142and first via layers161may be formed. Thereafter, third insulating layers113embedding at least portions of the second wiring layers142therein may be formed on the second insulating layers112. Thereafter, third wiring layers143and second via layers162may be formed.

Referring toFIG.13D, the carrier substrate500may be removed. For example, the carrier substrate500and the metal layer510may be separated from each other.

Referring toFIG.13E, a first dry film521may be disposed on the metal layer510. In addition, a second dry film522may be disposed on the third insulating layer113. Thereafter, exposing parts521pexposing the metal layer510disposed on the conductive patterns125may be formed by patterning the first dry film521by a photolithography process such as exposure and development.

Referring toFIG.13F, the conductive patterns125may be removed. For example, the conductive patterns125and the metal layer510selectively exposed through the exposing parts521pmay be removed by an etching process. When the conductive patterns125are removed, a recess R may be formed. First and second insulating walls131and132covering side surfaces of the first and second pads121and122may be formed on the first insulating layer111by the recess R. Thereafter, the first and second dry films521and522may be removed.

Referring toFIG.13G, the metal layer510may be removed. The metal layer510may be removed using, for example, a seed etching process. In this case, a seed layer of the third wiring layer143may also be removed together with the metal layer510.

Referring toFIG.13H, first and second passivation layers171and172may be formed. At least portions of the first passivation layer171may also be formed in at least portions of a region from which the conductive patterns125are removed, that is, the recess R. First and second openings171hand172hmay be formed by patterning the first and second passivation layers171and172.

The printed circuit board100H according to another exemplary embodiment described above may be manufactured through the series of processes described above, but this is only one manufacturing example, and the printed circuit board100H according to another exemplary embodiment described above may also be manufactured by processes different from the processes described above.

Other contents, for example, the contents described in the above-described printed circuit boards100A,100B,100C,100D,100E,100F,100F, and100H and the contents described in the example of the processes of manufacturing the printed circuit board described above may be applied to the processes of manufacturing the printed circuit board ofFIG.12as long as they are not contradictory, and a description of overlapping contents will be omitted.

FIG.14is a schematic cross-sectional view illustrating a modified example of the printed circuit board ofFIG.12.

Referring toFIG.14, a printed circuit board100I according to a modified example may have a package structure in which an electronic component210is surface-mounted and disposed on the above-described printed circuit board100H and a separate wiring board220is then disposed on the electronic component210in a board-on-board form. For example, the printed circuit board100I according to a modified example may be different from the above-described printed circuit board100H in that it further includes the electronic component210disposed on the first insulating layer111and including connection terminals212electrically connected to the first pads121through first connection members231and the wiring board220disposed on the electronic component210and including connection pads222electrically connected to the second pads122through second connection members232. The printed circuit board100I according to a modified example may further include a molding material240molding a space between the first insulating layer111and the wiring board220and/or electrical connection metal250connected to the third wiring layer143, if necessary. The above-described printed circuit board100H may be used as a package substrate on which a flip-chip die or the like is to be mounted.

Other contents, for example, the contents described in the above-described printed circuit boards100A,100B,100C,100D,100E,100F,100G, and100H may be applied to the printed circuit board100I according to a modified example as long as they are not contradictory, and a description of overlapping contents will be omitted.

FIG.15is a schematic cross-sectional view illustrating another modified example of the printed circuit board ofFIG.12.

Referring toFIG.15, a printed circuit board100J according to another modified example may have a package structure in which an electronic component210is surface-mounted and disposed on a separate wiring board320and the above-described printed circuit board100H is then disposed on the electronic component210in a board-on-board form. For example, the printed circuit board100J according to another modified example may be different from the above-described printed circuit board100H in that it further includes the wiring board320disposed on the first insulating layer111and including connection pads P1and P2disposed in a center region and a side region thereof and the electronic component210disposed between the first insulating layer111and the wiring board320and having a front surface on which connection terminals212are disposed and a back surface opposing the front surface. The connection pads P1and P2of the wiring board320may be electrically connected to the connection terminals212of the electronic component210and the second pads122through first and second connection members231and232, respectively. The printed circuit board100J according to a modified example may further include a molding material240molding a space between the first insulating layer111and the wiring board320and/or electrical connection metal250connected to the wiring layer325, if necessary. In addition, the printed circuit board100J according to another modified example may further include conductive members260connecting the first pads121and the back surface of the electronic component210to each other. The above-described printed circuit board100H may be used as an upper substrate having a heat dissipation function. Here, the upper board may be an interposer substrate for connection with another package or a package substrate on which another semiconductor die or the like is to be directly mounted.

Other contents, for example, the contents described in the above-described printed circuit boards100A,100B,100C,100D,100E,100G,100H, and100I may be applied to the printed circuit board100J according to another modified example as long as they are not contradictory, and a description of overlapping contents will be omitted.

FIG.16is a schematic cross-sectional view illustrating another example of a printed circuit board.

Referring toFIG.16, a printed circuit board100K according to another exemplary embodiment may include a first insulating layer111, first pads121disposed on an upper surface of the first insulating layer111, and first insulating walls131disposed on the upper surface of the first insulating layer111and covering side surfaces of the first pads121.

The printed circuit board100K according to another exemplary embodiment may further include a first wiring layer141disposed on a lower surface of the first insulating layer111and/or first connection vias151penetrating through the first insulating layer111and electrically connecting the first pads121to at least portions of the first wiring layer141, if necessary.

The printed circuit board100K according to another exemplary embodiment may further include a second insulating layer112disposed on the lower surface of the first insulating layer111and embedding at least portions of the first wiring layer141therein, a second wiring layer142disposed on a lower surface of the second insulating layer112, and/or a first via layer161penetrating through the second insulating layer112and electrically connecting at least portions of each of the first wiring layer141and the second wiring layer142to each other, if necessary.

The printed circuit board100K according to another exemplary embodiment may further include a third insulating layer113disposed on the lower surface of the second insulating layer112and embedding at least portions of the second wiring layer142therein, a third wiring layer143disposed on a lower surface of the third insulating layer113, and/or a second via layer162penetrating through the third insulating layer113and electrically connecting at least portions of each of the second wiring layer142and the third wiring layer143to each other, if necessary.

The printed circuit board100K according to another exemplary embodiment may further include a second passivation layer172disposed on the lower surface of the third insulating layer113and having second openings172hexposing at least portions of a surface of the third wiring layer143, if necessary.

Meanwhile, in the printed circuit board100K according to another exemplary embodiment, the second pads122may be omitted on the first insulating layer111. In addition, the second insulating walls132surrounding the second pads122may also be omitted. In addition, the second connection vias152connected to the second pads122may also be omitted. In addition, the first passivation layer171may also be omitted. As such, the printed circuit board100K according to another exemplary embodiment may have only a center region for mounting a flip-chip die, and components of a side region for a board-on-board structure may be omitted.

Other contents, for example, the contents described in the above-described printed circuit boards100A,100B,100C,100D,100E,100F,100G,100H,100I, and100J may be applied to the printed circuit board100K according to another exemplary embodiment as long as they are not contradictory, and a description of overlapping contents will be omitted.

FIGS.17A to17Hare schematic cross-sectional views illustrating an example of processes of manufacturing the printed circuit board ofFIG.16.

Referring toFIG.17A, a carrier substrate500having metal layers510formed on one surface or both surfaces thereof may be prepared, and first pads121and conductive patterns125may be formed on the metal layers510of the carrier substrate500.

Referring toFIG.17B, first insulating layers111embedding at least portions of each of the first pads121and the conductive patterns125therein may be formed on the metal layers510of the carrier substrate500. Thereafter, first wiring layers141and first via layers151may be formed.

Referring toFIG.17C, second insulating layers112embedding at least portions of the first wiring layers141therein may be formed on the first insulating layers111. Thereafter, second wiring layers142and first via layers161may be formed. Thereafter, third insulating layers113embedding at least portions of the second wiring layers142therein may be formed on the second insulating layers112. Thereafter, third wiring layers143and second via layers162may be formed.

Referring toFIG.17D, the carrier substrate500may be removed. For example, the carrier substrate500and the metal layer510may be separated from each other.

Referring toFIG.17E, the metal layer510may be removed. The metal layer510may be removed using, for example, a seed etching process. In this case, a seed layer of the third wiring layer143may also be removed together with the metal layer510.

Referring toFIG.17F, a second passivation layer172may be formed. Second openings172hmay be formed by patterning the second passivation layer172. The second passivation layer172may be formed by, for example, a method of forming a solder resist layer and then performing patterning using a photolithography process or the like so as to have the second openings172h,but is not limited thereto.

Referring toFIG.17G, a first dry film521may be disposed on the first insulating layer111. In addition, a second dry film522may be disposed on the second passivation layer172. Thereafter, exposing parts521pexposing the conductive patterns125may be formed by patterning the first dry film521by a photolithography process such as exposure and development.

Referring toFIG.17H, the conductive patterns125may be removed. For example, the conductive patterns125selectively exposed through the exposing parts521pmay be removed by an etching process. When the conductive patterns125are removed, a recess R may be formed. First and second insulating walls131and132covering side surfaces of the first and second pads121and122may be formed on the first insulating layer111by the recess R. Thereafter, the first and second dry films521and522may be removed.

The printed circuit board100K according to another exemplary embodiment described above may be manufactured through the series of processes described above, but this is only one manufacturing example, and the printed circuit board100K according to another exemplary embodiment described above may also be manufactured by processes different from the processes described above.

Other contents, for example, the contents described in the above-described printed circuit boards100A,100B,100C,100D,100E,100F,100G,100H,100I,100J, and100K and the contents described in the examples of the processes of manufacturing the printed circuit boards described above may be applied to the processes of manufacturing the printed circuit board ofFIG.16as long as they are not contradictory, and a description of overlapping contents will be omitted.

FIG.18is a schematic cross-sectional view illustrating a modified example of the printed circuit board ofFIG.16.

Referring toFIG.18, a printed circuit board100L according to a modified example may have a package structure in which an electronic component210are surface-mounted and disposed on the above-described printed circuit board100K. For example, the printed circuit board100L according to a modified example may be different from the above-described printed circuit board100K in that it further includes the electronic component210disposed on the first insulating layer111and connection terminal212electrically connected to the first pads121through first connection members231. The printed circuit board100L according to a modified example may further include an underfill280filling a space between the first insulating layer111and the electronic component210and/or electrical connection metal250connected to the third wiring layer143, if necessary. The above-described printed circuit board100K may be used as a package substrate on which only a flip-chip die or the like is to be mounted regardless of a board-on-board.

The underfill280may fix the electronic component210onto the first insulating layer111. The underfill280may protect the connection terminals212, the first connection members231, and the first insulating wall131by embedding the connection terminals212, the first connection members231, and the first insulating wall131therein. The underfill280may include an adhesive component such as an epoxy resin, but is not limited thereto, and may include other known materials.

Other contents, for example, the contents described in the above-described printed circuit boards100A,100B,100C,100D,100E,100F,100G,100H,100I,100J, and100K may be applied to the printed circuit board100L according to a modified example as long as they are not contradictory, and a description of overlapping contents will be omitted.

FIGS.19to22are schematic plan views illustrating various shapes of a plurality of pads and a plurality of insulating walls.

Referring toFIG.19, in plan view, a plurality of first pads121may be disposed in a center region, and a plurality of second pads122may be disposed in a side region surrounding the center region. The plurality of first pads121may be surrounded by a plurality of first insulating walls131, respectively. The plurality of second pads122may be surrounded by a plurality of second insulating walls132, respectively. The plurality of first insulating walls131may have first cavities131rin which the first pads121are disposed, respectively. The plurality of second insulating walls132may have second cavities132rin which the second pads122are disposed, respectively. A single recess R continuous as a whole may exist between the plurality of first insulating walls131and the plurality of second insulating walls132. Each of the plurality of first pads121and the plurality of second pads122may have a circular shape. Each of the plurality of first insulating walls131and the plurality of second insulating walls132may have a circular ring shape. Each of the plurality of second pads122may have a greater area than each of the plurality of first pads121. For example, each of the plurality of second pads122may have a greater diameter than each of the plurality of first pads121.

Referring toFIG.20, in plan view, at least one of the plurality of first pads121may have a shape in which a length thereof in any one direction is greater than a length thereof in another direction perpendicular to any one direction. The first insulating wall131surrounding such a first pad121may also have a ring shape in which a length thereof in any one direction is greater than a length thereof in another direction perpendicular to any one direction. As such, a design in which circular pads and elongated pads are mixed with each other may be applied according to a connection manner of a semiconductor die. That is, various designs may be applied. An elongated pad shape may increase a contact area to improve reliability.

Referring toFIG.21, in plan view, at least one of the plurality of second pads122may have a shape in which a length thereof in any one direction is greater than a length thereof in another direction perpendicular to any one direction. The second insulating wall132surrounding such a second pad122may also have a ring shape in which a length thereof in any one direction is greater than a length thereof in another direction perpendicular to any one direction. As such, a design in which circular pads and elongated pads are mixed with each other may be applied according to a connection manner of a board-on-board. That is, various designs may be applied. An elongated pad shape may increase a contact area to improve reliability.

Referring toFIG.22, in plan view, at least one of the plurality of first pads121may have a shape in which a length thereof in any one direction is greater than a length thereof in another direction perpendicular to any one direction. The first insulating wall131surrounding such a first pad121may also have a ring shape in which a length thereof in any one direction is greater than a length thereof in another direction perpendicular to any one direction. At least one of the plurality of second pads122may have a shape in which a length thereof in any one direction is greater than a length thereof in another direction perpendicular to any one direction. The second insulating wall132surrounding such a second pad122may also have a ring shape in which a length thereof in any one direction is greater than a length thereof in another direction perpendicular to any one direction. As such, a design in which circular pads and elongated pads are variously mixed with each other may be applied. That is, various designs may be applied. An elongated pad shape may increase a contact area to improve reliability.

As set forth above, according to an exemplary embodiment in the present disclosure, a printed circuit board capable of being easily manufactured, and a method of manufacturing the same may be provided.

In addition, a printed circuit board in which a bridge short-circuit risk may be decreased, and a method of manufacturing the same may be provided.

In addition, a printed circuit board in which reliability may be provided, and a method of manufacturing the same may be provided.