Highly integrated asymmetric digital subscriber line (ADSL) circuit

An asymmetric digital subscriber line (ADSL) transceiver chip is provided that includes a single integrated circuit (IC) substrate to host the circuit and an analog front-end (AFE) configured to receive and transmit analog signals. The AFE has a dynamic range greater than about 85dB and the received analog signals have bandwidths of about 2 mega-hertz. The ADSL chip also includes a digital signal processor (DSP) configured for digital processing and including bypass capacitors configured to provide switching charge. The AFE and the DSP are formed on the single IC substrate.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to communications, and more specifically to a highly integrated asymmetric digital subscriber line (ADSL) circuit chip for communications.

2. Background Art

An ADSL is used for data communications between a central office and customer processing equipment (CPE). At the CPE, an ADSL transceiver transmits and receives ADSL data to and from the central office. Conventional ADSL transceivers are configured on at least two separate semiconductor integrated circuits (IC). More specifically, one IC is usually dedicated to analog processing and the other IC is usually dedicated to digital processing. It would be preferable to combine these two chips into one chip to reduce part count, reduce cost, and improve electrical performance.

BRIEF SUMMARY OF THE INVENTION

The present invention is a single ADSL transceiver chip that includes an analog front-end (AFE) and a digital signal processor (DSP) on the same substrate. A line driver for the ADSL transceiver can be located on a separate substrate. In a preferred embodiment of the invention, the transceiver chip can be implemented in a low voltage complementary metal-oxide semiconductor (CMOS) process that could be, for example, a low voltage CMOS process.

It is highly advantageous to build the analog front-end and the DSP on a single integrated IC because it allows for reduced manufacturing part count, reduced assembly time and reduced costs. The line driver substrates typically require a high voltage semiconductor process (e.g. 18 volts peak-to-peak) in certain applications, because of the need for a sufficient level of voltage to drive the ADSL line. Therefore, the line driver can be formed on a separate substrate.

The AFE and the DSP do not require a high-voltage process, such as the process required by the line driver semiconductor process noted above. For example, the AFE and DSP in the present invention can operate, for example, at about 3.3 volts peak-to-peak, which facilitates their placement on the same substrate and the creation of additional significant economies.

DETAILED DESCRIPTION OF THE INVENTION

The following detailed description of the accompanying drawings illustrates exemplary embodiments consistent with the present invention. Other inventions are possible, and modifications may be made to the embodiments within the spirit and scope of the invention. Therefore, the following detailed description is not meant to limit the invention. Rather, the scope of the invention is defined by the appended claims.

It would be apparent to one of skill in the art that the present invention, as described below, may be implemented in many different embodiments of hardware, software, firmware and/or the entities illustrated in the figures. Any actual software code with the specialized control hardware to implement the present invention, is not limiting of the present invention. Thus, the operation and behavior of the present invention will be described with the understanding that modifications and variations of the embodiments are possible, given the level detail presented herein.

FIG. 1illustrates an exemplary ADSL transceiver100according to embodiments of the present invention. The ADSL transceiver100operates at the CPE, and transmits/receives data to/from the central office over an ADSL line101. The transceiver100includes a line driver substrate102and an ADSL transceiver chip110substrate. The line driver substrate102includes a hybrid circuit104that separates the transmit data from the receive data.

In the preferred embodiment, as illustrated inFIG.2, transmit data202is sent from the CPE to the central office and occupies an exemplary bandwidth of about 25 kilo hertz (kHz) to 138 kHz. Receive data204, received from the central office, occupies a bandwidth from about 138 kHz to 1.1 mega hertz (MHz). In other words, the receive data204has a total signal bandwidth of about 1 MHz. In terms of signal quality, the present invention can achieve a dynamic range of about 90 dB while operating at the high, roughly 1 MHz, bandwidths. the frequency difference between the transmit data202and the receive data204allows for the transmit and receive data to occupy the same transmission line. The hybrid circuit104can include a transmit filter with a passband for transmit data and a receive filter having a passband for the receive data204.

The AFE105includes an analog-to-digital (A/D) converter106and a digital-to-analog (D/A) converter108. The A/D converter106receives analog data111from the hybrid circuit104that was received over the ADSL line101. The A/D converter106samples the received data111, and generates a quantized digital signal114representative of the received data111. The digital signal114is then sent to the DSP112for further processing. For transmissions, the D/A converter108receives the digital data116from the DSP112that is meant to be transmitted to the central office over the ADSL line101. The D/A converter108converts the digital data116to an analog signal118that is transmitted to the central office over the ADSL line101.

High signal bandwidth and dynamic range requirements, such as those in the present invention, typically make integration of AFEs and DSPs prohibitive. In the instant invention, however, the inventors have managed to achieve the ultimate in AFE and DSP integration—designing the transceiver chip110to include an AFE105and a DSP112on the same IC substrate.

In a preferred embodiment of the present invention, the transceiver chip110is a CMOS process, although the present invention is not limited to CMOS. The process can include, for example, a low voltage CMOS implementation. It is highly advantageous to build the AFE105and the DSP112on a single IC chip because it allows for significant economies such as reduced manufacturing part count, reduced assembly time, and reduced costs. The line driver substrate102, on the other hand, requires a high voltage semiconductor process (e.g. 18 volts peak-to-peak) in some applications because of the need for adequate voltage to drive the ADSL line101.

The AFE105and the DSP112, however, do not require the high-voltage process needed to power the line driver substrate102. Consequently, the AFE105and the DSP112can be designed using, for example, a 0.18 micron device design process, which in-part, permits their placement on the same IC substrate. That is, because of the selection of the 0.18 micron design process, the transceiver chip110can be manufactured to have a core device that runs off 1.8 volts and input/output (I/O) devices that run off about 3.3 v peak-to-peak. These relatively low core device and I/O device voltage levels contribute to the ability to integrate the AFE105and the DSP112on the same IC substrate, thus facilitating the significant economies, such as those noted above. Numerous other inventive techniques, however, enable the inventors of the instant invention to overcome the challenges of forming the AFE105and the DSP112on the same substrate.

One particular challenge to integrating the AFE105and the DSP112on the same IC substrate, especially under the high bandwidth and dynamic range constraints of the present invention, is reducing digital noise. Digital noise can occur as a result of the activity and operation of the digital circuitry (within the DSP112) and their corresponding voltage values, which can swing from zero to their core supply levels. Since the digital circuits are coupled to the same substrate as the analog circuits, the digital noise can couple to the analog circuits and create an impairment in the transceiver chip's analog performance. For example, digital noise can easily erode the system's dynamic range performance.

FIG. 3illustrates a technique for isolating digital noise associated with forming the AFE105and the DSP112on the same IC. InFIG. 3, at least one bypass capacitor (cap)300is connected to the power supplies of random access memories, such as the memory block304, and other typically noisy standard cell substrate areas. In the example ofFIG. 3, the bypass cap300is connected between a Vdd terminal301and a ground (Gnd) terminal302of the memory block304.

The bypass cap300performs as miniature local battery providing impulse current for operation of the DSP112. That is, when components within the DSP112require AC surge current, for example, the surge current can be extracted from the bypass cap300. That is, this surge current is drawn from the bypass cap300instead of being drawn from “off-chip.” As understood in the art, current and voltages that are received off-chip have to run off the chip's pad rings and associated bond wires, which creates paths for energy coupling to the digital circuitry. In the instant invention, this energy coupling is reduced through use of the bypass cap300.

FIG. 4Ais an illustration of an exemplary metallic shield400for protecting sensitive internal electrical paths of the AFE105. The AFE105is constructed in a manner where some of its internal electrical paths are more sensitive than others to analog circuit noise. Analog circuits inherently produce noise, especially when the analog outputs are swinging in voltage from rail-to-rail. The shield400is provided for forming a shield around these sensitive paths to isolate any electrical noise and reduce the probability of the noise coupling to the sensitive electrical paths. More specifically, the shield400is provided to prevent this undesirable electrical energy from coupling into analog signal paths such as the exemplary analog signal lines402and404or clock paths.

In the exemplary embodiment ofFIG. 4A, the shield400is constructed in the form of a coaxial metallic tube-like workpiece, or container, for shielding the path created by differential signal lines402and404. The differential signal lines402and404can be used to connect, for example, to a low noise amplifier406, or some other component within the AFE105. A connection408is established to connect the metallic shield400to ground.

FIG. 4Billustrates a side view of the exemplary shield400shown inFIG. 4A. InFIG. 4B, selected electrical paths, such as the signal lines402and404, are shielded by a metallic layer410, and a metallic layer412on an opposite side of the layer410. The shield400also includes thin metallic layers414and416that are connected between the layers410and412, as shown, using standard inter layer metal connections418, also known as VIAs. A bore419, or interior portion of the shield400, is provided as a pathway through which the signal lines402and404may pass. The metal components of the shield400may be created using any suitable conductive and/or metallic material.

FIG. 4Cis a top view of the metallic shield400, illustrating an exemplary disposition of the inter layer metal connections418between the layers410and412. As previously noted, the metallic layer400is used to shield selected electrical paths of the AFE105from the effects of noise coupling. Differential inputs lines are illustrated inFIGS. 4A–4Bfor purposes of illustration only. In practice, the shield400can be applied to any number and/or type of sensitive electrical paths within the AFE105.

FIG. 5Aillustrates another technique used to create an environment where the AFE105and the DSP112can be formed on the single IC substrate110. In the exemplary embodiment shown inFIG. 5A, the entire AFE105is physically surrounded by an isolation moat500to separate the AFE105from the DSP112. The isolation moat500is formed of a plurality of digital gates. The digital gates are arrayed as concentric rectangular structures, housing the AFE105in their center in order to absorb digital noise created by operation of the DSP112.FIG. 5Bprovides a more detailed view of the isolation moat500.

As shown inFIG. 5B, the exemplary isolation moat500is formed of P-well conductors502and N-well conductors504alternately disposed and implanted within the IC substrate110. Positioning in this manner enables the P-wells502and the N-wells504to electrically separate the analog and digital portions of the IC substrate110. The P-wells and N-wells are typically interconnected using a three terminal device, such as a diode (not shown). InFIG. 5B, the substrate110is formed of a p-type layer, although the present invention is not limited to such an implementation. In the embodiment ofFIG. 5B, the P-wells502are connected to ground and the N-wells504are connected to Vdd. During operation of the isolation moat500, the P-wells502and N-wells504electrically cooperate to prevent digital noise, created by operation of the DSP112, from interfering with operation of the AFE105. Any noise is absorbed within the P-wells502and the N-wells504.

Noise that can potentially interfere with the AFE105can also be created by the very act of passing logic signals from the digital side to the analog side of the ADSL transceiver100. For example, when a logic control signal is passed from the digital side to the analog side, its actual signal transmission line can become a conduit of digital noise. The present invention, therefore, includes a mechanism to reproduce signals produced by the DSP112before these signals are used within the AFE105.

FIG. 6shows a buffer section600to buffer or reproduce the digital data116, or logic signals, passed from the DSP112to the AFE105. The buffers600are connected to quiet analog power supplies602to minimize the possibility of additional noise being created through the buffering process. In the exemplary embodiment ofFIG. 6, the buffer600is implemented using an inverter. However, the buffer600can be implemented using any suitable device. In this manner, the digital data116produced by the DSP112is reproduced on the analog supplies602and converted into quieter signals before being used in the AFE105.

FIG. 7is an illustration of a technique of the present invention to reduce crosstalk between the AFE105and the DSP112. InFIG. 7, the IC substrate110includes a padring700. As known, padrings are components where electrical, timing, and logical features of the IC are integrated. In the exemplary embodiment ofFIG. 7, the padring700includes power supply padring breaks702and704to divide the padring700into multiple disjointed sections. The multiple disjointed padring sections, including a digital section706and an analog section708, help isolate power supplies within the AFE105and the DSP112in order to reduce crosstalk between digital and analog padring portions of the IC substrate110.

In the present invention, the digital section706is configured to handle the processing of full-scale digital signals and the analog section708is configured to handle analog signals. Since pads707, within the digital section706, can experience full voltage swings from ground to Vdd, the padring breaks702and704, prevent voltages from capacitively coupling to the analog section708.

Next, as illustrated in the exemplary embodiments ofFIGS. 5A and 7, the AFE105is physically located at a corner of the IC110for maximum isolation from noisy portions of the IC and from the DSP112. While the embodiments ofFIGS. 5A and 7show the AFE105in a particular corner of the IC110, the AFE105can be positioned in any suitable location to provide an adequate level of physical isolation from noise generated by the DSP112.

FIG. 8further illustrates the transceiver chip110, and further defines additional details of the AFE105and the DSP112. In addition to the A/D converter106, the AFE105also includes a receive programmable gain amplifier (PGA)802in the receive path, and a transmit PGA804in the transmit path. One embodiment of the PGAs802and804is further described in U.S. patent application Ser. No. 10/208,042, entitled System and Method for a Programmable Gain Amplifier, filed Jul. 31, 2002 and U.S. patent application Ser. No. 10/208,044, entitled System and Method for a Start-Up Circuit for a Differential CMOS Amplifier, filed Jul. 31, 2002, which are incorporated by reference herein in their entirety.

The receive PGA802is connected to the input of the A/D converter106, and the transmit PGA804is connected to the output of the D/A converter108. The AFE105also includes a crystal oscillator806that drives the A/D converter106. One embodiment of the A/D converter106is further described in U.S. patent application Ser. No. 10/043,229, entitled, Gain Scaling for Higher Signal-To-Noise Ratios in Multistage, Multi-Bit Delta Sigma Modulators, filed Jan. 14, 2002, which is incorporated by reference herein in it's entirety.FIG. 9illustrates the interface between the A/D converter106and the DSP112.FIG. 10illustrates an analog modulator that is one embodiment of the A/D converter106, where y1, y2, y3, and y4are the outputs.

The DSP112includes an AFE digi-mux808and a digital core812. The digi-mux808performs digital control, digital input/output (I/O) multiplexer (mux) control, sigma-delta decimation, and sigma-delta interpolation. The digital core812processes the digital signals received from/transmitted to the digi-mux808.

FIG. 11illustrates an exemplary transmit path through the AFE digi-mux808and the digital core812. In this example, the receive path through the AFE digi-mux808and the digital core812is a recombination and decimation filter for the A/D converter106that converts 4 bits at 64 MHz to 16 bits at 4 MHz, with a signal bandwidth of 25 kHz to 1.1 MHz.

The present invention has been described above with the aid of functional building blocks illustrating the performance of specified functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed. Any such alternate boundaries are thus within the scope and spirit of the claimed invention. One skilled in the art will recognize that these functional building blocks can be implemented by analog and/or digital circuits, discrete components, application specific integrated circuits, firmware, processors executing appropriate software and the like or any combination thereof Thus, the breadth and scope of the present invention should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.