Techniques for reducing read voltage threshold calibration in non-volatile memory

A non-volatile memory includes a plurality of cells each individually capable of storing multiple bits of data including bits of multiple physical pages including at least a first page and a second page. A controller of the non-volatile memory determines a first calibration interval for a first read voltage threshold defining a bit value in the first page and a different second calibration interval for a second read voltage threshold defining a bit value in the second page. The second calibration interval has a shorter duration than the first calibration interval. The controller calibrates the first and second read voltage thresholds for the plurality of memory cells in the non-volatile memory based on the determined first and second calibration intervals.

BACKGROUND OF THE INVENTION

This disclosure relates to data processing and data storage, and more specifically, to calibration of one or more read voltage thresholds for a unit of data storage in a non-volatile memory system. Still more particularly, the disclosure relates to techniques for reducing the overhead of a read voltage threshold calibration in a non-volatile memory system.

NAND flash memory is an electrically programmable and erasable non-volatile memory technology that stores one or more bits of data per memory cell as a charge on the floating gate of a transistor or a similar charge trap structure. The amount of charge on the floating gate modulates the threshold voltage of the transistor. By applying a proper read voltage and measuring the amount of current, the programmed threshold voltage of the memory cell can be determined and thus the stored information can be detected. Memories storing one, two, three and four bits per cell are respectively referred to in the art as Single Level Cell (SLC), Multi-Level Cell (MLC), Three Level Cell (TLC), and Quad Level Cell (QLC) memories. In a typical implementation, a NAND flash memory array is organized in blocks (also referred to as “erase blocks”) of physical memory, each of which includes multiple physical pages each in turn containing a multiplicity of memory cells. By virtue of the arrangement of the word and bit lines utilized to access memory cells, flash memory arrays have generally been programmed on a page basis, but erased on a block basis.

In multi-level (i.e., MLC, TLC and QLC) NAND flash memory, information is stored by programming the memory cells to various quantized threshold voltage levels according to the device's programming algorithm, which maps the binary bit values to discrete threshold voltage levels. In response to a page read command, the binary bit values are retrieved by applying appropriate read voltages that divide the programmed threshold voltage window into discrete regimes and by then applying a reverse mapping between the detected threshold voltage levels and the corresponding binary bit values. Over the lifetime of a multi-level NAND flash memory device, the distributions of programmed threshold voltage generally become degraded due to the effects of wear on the memory cells. Consequently, it is generally desirable to adapt or calibrate the read voltage thresholds defining the various bit values over time to compensate for the effects of wear and to extend the useful life of the NAND memory device.

BRIEF SUMMARY

In conventional NAND flash memory devices, each page is calibrated on the same iterative schedule. For example, a conventional controller of a NAND flash memory device may walk through all pages of the NAND flash memory device within a time period of one to two weeks. The present application recognizes that while this calibration frequency may provide satisfactory error rates for older flash technologies, newer non-volatile technologies, such as 3D TLC or QLC NAND flash, can require more frequent calibration, particularly when operating in elevated temperature environments. For example, in some cases, to maintain acceptable error rates, some non-volatile memory technologies may require read voltage thresholds to be calibrated on the order of hours or days rather than weeks.

As one specific example, consider the calibration of a 3D TLC NAND flash memory, where the read voltage threshold of each wordline is separately calibrated. Assuming 192 wordlines, seven read voltage thresholds (to define the eight possible cell states of TLC NAND), and three reads per read voltage threshold calibration, approximately 4,000 pages would have to be read for each calibration (e.g., 192×7×3≈4,000). Assuming that each read takes 100 microseconds, one calibration might take 0.4 second. If the 3D TLC NAND flash memory includes 100,000 blocks and each block is sequentially calibrated once per day, the calibration would take 40,000 seconds, which at about 11 hours would consume almost half the total internal bandwidth doing only calibrations. Obviously, for storage devices including a larger number of blocks, calibration of all blocks within the desired time frame would become impossible.

In view of foregoing, the present application recognizes that it would be useful and desirable to reduce the number of reads required to perform read voltage threshold calibrations while still performing calibration frequently enough to obtain acceptable bit error rates. The present application accordingly presents techniques that can be selectively applied to reduce the number of reads performed for read voltage threshold calibration.

In one exemplary embodiment, a non-volatile memory includes a plurality of cells each individually capable of storing multiple bits of data including bits of multiple physical pages including at least a first page and a second page. A controller of the non-volatile memory determines a first calibration interval for a first read voltage threshold defining a bit value in the first page and a different second calibration interval for a second read voltage threshold defining a bit value in the second page. The second calibration interval has a shorter duration than the first calibration interval. The controller calibrates the first and second read voltage thresholds for the plurality of memory cells in the non-volatile memory based on the determined first and second calibration intervals. In some embodiments, the controller can determine the second calibration interval based on relative probabilities of read failures of the lower page and upper page due to data retention effects.

In some embodiments, the number of reads performed in connection with read voltage threshold calibration can alternatively or additionally be reduced by calibrating read voltage thresholds for pages in a page group based on reading only a subset of pages in that page group.

In some embodiments, the number of reads performed in connection with read voltage threshold calibration can alternatively or additionally be reduced by deferring calibration of a read voltage threshold for at least a selected page of a page group when a bit error rate of the selected page does not satisfy a calibration threshold.

DETAILED DESCRIPTION

With reference to the figures and with particular reference toFIG. 1A, there is illustrated a high level block diagram of an exemplary data processing environment100including a data storage system120having a non-volatile memory array as described further herein. As shown, data processing environment100includes one or more hosts, such as a processor system102having one or more processors104that process instructions and data. A processor system102may additionally include local storage106(e.g., dynamic random access memory (DRAM) or disks) that may store program code, operands and/or execution results of the processing performed by processor(s)104. In various embodiments, a processor system102can be, for example, a mobile computing device (such as a smartphone or tablet), a laptop or desktop personal computer system, a server computer system (such as one of the POWER series of servers available from International Business Machines Corporation), or a mainframe computer system. A processor system102can also be an embedded processor system using various processors such as ARM, POWER, Intel x86, or any other processor combined with memory caches, memory controllers, local storage, I/O bus hubs, etc.

Each processor system102further includes an input/output (I/O) adapter108that is coupled directly (i.e., without any intervening device) or indirectly (i.e., through at least one intermediate device) to a data storage system120via an I/O channel110. In some embodiments, data storage system120may be integral to a processor system102. In various embodiments, I/O channel110may employ any one or a combination of known or future developed communication protocols, including, for example, Fibre Channel (FC), FC over Ethernet (FCoE), Internet Small Computer System Interface (iSCSI), InfiniBand, Transport Control Protocol/Internet Protocol (TCP/IP), Peripheral Component Interconnect Express (PCIe), etc. I/O requests communicated via I/O channel110include read requests by which a processor system102requests data from data storage system120and write requests by which a processor system102requests storage of data in data storage system120.

Although not required, in the illustrated embodiment, data storage system120includes multiple interface cards122through which data storage system120receives and responds to I/O requests of hosts via I/O channels110. Each interface card122is coupled to each of multiple Redundant Array of Inexpensive Disks (RAID) controllers124in order to facilitate fault tolerance and load balancing. Each of RAID controllers124is in turn coupled (e.g., by a PCIe bus) to non-volatile storage media, which in the illustrated example include multiple flash cards126bearing NAND flash memory. In other embodiments, alternative and/or additional non-volatile storage devices can be employed.

In the depicted embodiment, the operation of data storage system120is managed by redundant system management controllers (SMCs)123, which are coupled to interface cards122and RAID controllers124. In various embodiments, system management controller123can be implemented utilizing hardware or hardware executing firmware and/or software.

FIG. 1Bdepicts a more detailed block diagram of an exemplary embodiment of a flash card126of data storage system120ofFIG. 1A. Flash card126includes a gateway130that serves as an interface between flash card126and RAID controllers124. Gateway130is coupled to a general-purpose processor (GPP)132, which can be configured (e.g., by program code) to perform pre-processing on requests received by gateway130and/or to schedule servicing of the requests by flash card126. GPP132is coupled to a GPP memory134(e.g., Dynamic Random Access Memory (DRAM)) that can conveniently buffer data created, referenced and/or modified by GPP132in the course of its processing or data flowing through the gateway130destined for one or more of the flash controllers140.

Gateway130is further coupled to multiple flash controllers140, each of which controls a respective NAND flash memory system150. Flash controllers140can be implemented, for example, by an Application Specific Integrated Circuit (ASIC) and/or a Field Programmable Gate Array (FPGA) and/or a microprocessor, and each have an associated flash controller memory142(e.g., DRAM). In embodiments in which flash controllers140are implemented with an FPGA, GPP132may program and configure flash controllers140during start-up of data storage system120. After startup, in general operation flash controllers140receive read and write requests from gateway130that request to read data stored in NAND flash memory system150and/or to store data in NAND flash memory system150. Flash controllers140service these requests, for example, by accessing NAND flash memory system150to read or write the requested data from or into NAND flash memory system150or by accessing a memory cache (not illustrated) associated with NAND flash memory system150.

Flash controllers140implement a flash translation layer (FTL) that provides logical-to-physical address translation to enable access to specific memory locations within NAND flash memory systems150. In general, a request received by flash controller140from a host device, such as a processor system102, contains the logical block address (LBA) at which the data is to be accessed (read or written) and, if a write request, the write data to be stored to data storage system120. The request may also specify the amount (or size) of the data to be accessed. Other information may also be communicated depending on the protocol and features supported by data storage system120. The flash translation layer translates LBAs received from a RAID controller124into physical addresses assigned to corresponding physical location in NAND flash memory systems150. Flash controllers140may perform address translation and/or store mappings between logical and physical addresses in a logical-to-physical translation data structure, such as a logical-to-physical translation table (LPT), which may conveniently be stored in flash controller memory142.

NAND flash memory systems150may take many forms in various embodiments. In the embodiment shown inFIG. 1B, each NAND flash memory system150includes multiple (e.g.,32) individually addressable NAND flash memory storage devices152. In the illustrated example, the flash memory storage devices152take the form of a board-mounted flash memory modules, for example, Multi-Level Cell (MLC), Three Level Cell (TLC), or Quad Level Cell (QLC) NAND flash memory modules. The effective storage capacity provided by flash memory storage devices152can be increased through the implementation of data compression, for example, by flash controllers140and/or high level controllers, such as GPPs132, RAID controllers124or SMCs123.

Referring now toFIG. 2, there is depicted a block diagram of an exemplary flash memory module200that can be utilized to implement any of the NAND flash memory storage devices152ofFIG. 1B. Flash memory module200includes one or more memory die, each implementing at least one memory array202formed of a two-dimensional or three-dimensional array of NAND flash memory cells. As indicated inFIG. 2, the memory cells within memory array202are physically arranged in multiple blocks204, each in turn including multiple physical pages206. As discussed below, these pages can be grouped in page groups, which can each be formed, for example, of all the pages coupled to a common wordline, of all pages in one or more layers in a 3D NAND flash, of a set of pages in one or more layers, or generally of pages with similar characteristics.

As is known to those skilled in the art, NAND flash memory, such as that employed in memory array202, must be erased prior to being programmed. Further, NAND flash memory can be (but is not required to be) constrained by its construction such that the smallest granule of storage that can be erased is a block204and the smallest granule of storage that can be accessed by a read or write request is fixed at the size of a single physical page206. It should be appreciated in this regard that the LBAs provided by host devices correspond to logical pages within a logical address space, where each logical page typically has a size of 4 kilobytes (kB). Physical pages206, in contrast, typically have a larger size, for example, 16 kB, and can thus host multiple logical pages.

Flash memory module200further includes a row decoder210through which word lines of memory array202can be addressed and a column decoder212through which bit lines of memory array202can be addressed. In addition, flash memory module200includes read/write circuitry214that enables the memory cells of a physical page206to be programmed or read in parallel. Flash controller200additionally includes control circuitry205that provides chip-level control of operation of memory array202, including read and write accesses made to physical pages206in memory array202, erasure of blocks204, and the amplitude, duration and polarity of related voltages applied to memory array202.

Having described the general physical structure of one exemplary embodiment of a data storage system120, certain operational aspects of data storage system120are now described with reference toFIG. 3, which is a high level flow diagram of the flash management functions and data structures employed by a GPP132and/or flash controller140in accordance with one embodiment.

Data storage system120does not generally allow external devices (e.g., hosts) to directly address and/or access the physical memory locations within NAND flash memory systems150. Instead, data storage system120is generally configured to present to host devices one or more logical volumes each having a contiguous logical address space, thus allowing host devices to read and write data to and from logical block addresses (LBAs) within the logical address space while permitting one or more of the various levels of controllers (e.g., system management controller123, RAID controllers124, flash controllers140and GPP132) to control where the data that is associated with the various LBAs actually resides in the physical memory locations comprising NAND flash memory systems150. In this manner, performance and longevity of NAND flash memory systems150can be intelligently managed and optimized. In the illustrated embodiment, each flash controller140performs logical-to-physical address translation for an associated set of LBAs using a logical-to-physical address translation data structure, such as logical-to-physical translation (LPT) table300, which can be stored, for example, in the associated flash controller memory142. It should be noted that the logical address supplied to flash controller(s)140may be different from the logical address originally supplied to data storage system120, since various components within data storage system120may perform address translation operations between the external devices and the flash controller(s)140.

Flash management code running on the GPP132tracks erased blocks of NAND flash memory system150that are ready to be used in ready-to-use (RTU) queues306, which may be stored, for example, in GPP memory134. In the depicted embodiment, flash management code running on the GPP132maintains one RTU queue306per channel or plane (i.e., per data bus), and an identifier of each erased block that is to be reused is enqueued in the RTU queue306corresponding to its channel or plane. A build block stripes function320performed by flash management code running on the GPP132constructs new block stripes for storing data and associated parity information from the erased blocks enqueued in RTU queues306. The new block stripes are then queued to the flash controller140for data placement. Block stripes are preferably formed of blocks residing in different channels, meaning that build block stripes function320can conveniently construct a block stripe by drawing each block of the new block stripe from a different RTU queue306. In general, build block stripes function320attempts to construct stripes from blocks of approximately equal health (i.e., expected remaining useful life).

In response to write request received from a host, such as a processor system102, a data placement function310of flash controller140determines by reference to LPT table300whether the target LBA(s) indicated in the write request is/are currently mapped to physical memory page(s) in NAND flash memory system150and, if so, changes the status of each data page currently associated with a target LBA to indicate that the associated data is no longer valid. In addition, data placement function310allocates a page stripe if necessary to store the write data of the write request and any non-updated data (i.e., for write requests smaller than a logical page, the remaining valid data from a previous write to the same logical address which is not being overwritten and which must be handled in a read-modify-write manner) from an existing page stripe, if any, targeted by the write request, and/or stores the write data of the write request and any non-updated (i.e., still valid) data from an existing page stripe, if any, targeted by the write request to an already allocated page stripe which has free space left. The page stripe may be allocated from either a block stripe already allocated to hold data or from a new block stripe built by build block stripes function320. In a preferred embodiment, the page stripe allocation can be based on the health of the blocks available for allocation and the “heat” (i.e., estimated or measured write access frequency) of the LBA of the write data. Data placement function310then writes the write data, associated metadata (e.g., cyclic redundancy code (CRC) and error correcting code (ECC) values), and parity information for the page stripe in the allocated page stripe. Flash controller140also updates LPT table300to associate the physical page(s) utilized to store the write data with the LBA(s) indicated by the host device. Thereafter, flash controller140can access the data to service host read requests by reference to LPT table300as further illustrated inFIG. 3.

Once all pages in a block stripe have been written, flash controller140places the block stripe into one of occupied block queues302, which flash management code running on the GPP132utilizes to facilitate garbage collection. As noted above, through the write process, pages are invalidated, and therefore portions of the NAND flash memory system150become unused. The associated flash controller140(and/or GPP132) eventually needs to reclaim this space through garbage collection performed by a garbage collector312. Garbage collector312selects particular block stripes for garbage collection based on a number of factors including, for example, the health of the blocks204within the block stripes and how much of the data within the erase blocks204is invalid. In the illustrated example, garbage collection is performed on entire block stripes, and flash management code running on GPP132logs the block stripes ready to be recycled in a relocation queue304, which can conveniently be implemented in the associated flash controller memory142or GPP memory134.

The flash management functions performed by GPP132or flash controller140additionally include a relocation function314that relocates the data held in block stripes enqueued in relocation queue304. To relocate such data, relocation function314issues relocation write requests to data placement function310to request that the valid data of the old block stripe be written to a new block stripe in NAND flash memory system150. In addition, relocation function314updates LPT table300to remove the current association between the logical and physical addresses of the data. Once all remaining valid data has been moved from the old block stripe, the old block stripe is passed to dissolve block stripes function316, which decomposes the old block stripe into its constituent blocks204, thus disassociating the blocks204. Each of the blocks204formerly forming the dissolved block stripe is then erased under the direction of flash controller140and/or the control circuitry205of the relevant flash memory module200, and a corresponding program/erase (P/E) cycle count334for each erased block is incremented. Based on the health metrics of each erased block204(e.g., bit error rate (BER) metrics, uncorrectable errors, P/E cycle count, etc.), each erased block204is either retired (i.e., withdrawn from use) by a block retirement function318among the flash management functions executed on GPP132, or alternatively, prepared for reuse by placing the block204on the appropriate ready-to-use (RTU) queue306in the associated GPP memory134.

As further shown inFIG. 3, the flash management functions executed on GPP132and/or flash controller140additionally include a background health checker330. Background health checker330, which operates independently of the read and write requests of hosts such as processor systems102, continuously determines one or more block health metrics332for blocks belonging to block stripes recorded in occupied block queues302. Based on the one or more of the block health metrics332, background health checker330places block stripes on relocation queue304for handling by relocation function314. Key block health metrics332preferably monitored and recorded by background health checker relate to the bit error rate (BER) metrics observed for valid blocks and physical pages, and may include, for example, the worst page BER of each block, the mean page BER of each block, the rates of change of the worst page BER and mean page BER of each block, etc. In order to obtain the most accurate health estimate possible, health can be determined from an analysis of valid and invalid data, thereby ensuring that blocks containing almost entirely invalid data are fully analyzed to determine overall block health.

As described in greater detail below, one function of GPP132and/or flash controller140that can be incorporated within background health checker330or that can be separately implemented is the periodic adaptation (calibration) of read voltage thresholds336utilized to decode the data bits stored within the memory cells of memory arrays202. These read voltage thresholds336, which can be individually defined to any desired level of granularity (e.g., per-page, per page group within a block, per block, etc.), are preferably selected to improve one or more bit error metrics. As further depicted inFIG. 3, GPP132and/or flash controller140preferably track additional statistics to facilitate intelligent adaptation of read voltage thresholds336. These additional statistics can include, for example, P/E cycle counts334identifying a number of program/erase cycles to which each block has been subjected and read counts338indicating a number of times a given memory unit (e.g., page, page group and/or block) has been read since being programmed. In addition, these statistics can include calibration triggers340, such as per-memory unit counters indicating an elapsed amount of time since read voltage thresholds of that memory unit were adapted and/or per-block counters indicating a number of program/erase cycles that each block has been subjected to since the read voltage thresholds for that block were last adapted.

Referring now toFIGS. 4A-4B, there is depicted initial and subsequent programmed threshold voltage distributions (VTH) for an exemplary multi-level cell (MLC) NAND flash memory. As shown inFIG. 4A, when a block204of a NAND flash memory storage device152is first put into service, each of the four voltage distributions400a,400b,400cand400d, respectively representing bit values 11, 10, 00 and 01, is tight and well defined. Consequently, the bit values of the various memory cells can be decoded with little or no error by application of initial read voltage thresholds VA402a, VB402band VC402c.

Through use, the memory cells within block204will be damaged by, among other things, the voltage stress associated with program/erase (P/E) cycling. As a result of this damage, the distribution of memory cell voltages will no longer reflect the tight distributions shown inFIG. 4A, but will instead be characterized by broader and/or shifted voltage distributions406a,406b,406c,406dshown inFIG. 4B. Because of the degradation of the voltage distributions, bit values can be erroneously decoded if read voltage thresholds VA402a, VB402band VC402ccontinue to be applied, and the bit error rate (BER) for reads to the block will consequently increase.

To reduce the BER for the block, GPP132and/or flash controller140periodically adapts (calibrates) the read voltage thresholds for one or more individual memory units (e.g., a page, page groups and/or a block) either negatively (not illustrated) or positively (as shown explicitly inFIG. 4B). For example, inFIG. 4Bread voltage thresholds VA402a, VB402band VC402care each shifted positively by an individually determined offset ΔA, ΔB or ΔC selected to reduce and/or minimize the BER. Thus, in the example ofFIG. 4B, read voltage thresholds VA402a, VB402band VC402care replaced by read voltage thresholds VA+ΔA404a, VB+ΔB404band VC+ΔC404c, respectively. The signs and magnitudes of the read voltage threshold offsets selected by GPP132and/or flash controller140can and will vary over the lifetime of the block based on various environmental factors (e.g., temperature) and use factors (e.g., read disturbs, write disturbs, erase disturbs, data retention effects, etc.).

AlthoughFIGS. 4A-4Billustrate the calibration of the three read voltage thresholds utilized to define the four possible bit value combinations represented by the charge stored on the floating gate of an MLC flash memory cell, it will be appreciated that the same principles are applicable to other types of non-volatile memories, including TLC and QLC NAND flash. For example,FIG. 5is a graph illustrating the seven read threshold voltages defining the eight possible bit value combinations that can be represented by the charge stored on the floating gate of an exemplary TLC NAND flash memory cell. Like the read voltage thresholds employed in MLC NAND flash, the seven read voltage thresholds of the TLC NAND flash are subject to repeated calibration and positive or negative adaptation during use.

In the art, the least significant bit value of a TLC NAND flash cell is said to form a portion of a “lower page,” the next least significant bit forms a portion of the “upper page,” and the most significant bit forms a portion of the “extra page.” For QLC, this tripartite division of page types is augmented by a fourth bit of data within an “additional page.”FIG. 5illustrates the various read voltage thresholds utilized to distinguish the different possible bit values of the various pages in one embodiment of TLC NAND flash memory. For example, a single read voltage threshold Lp0is utilized to distinguish between the two possible least significant bit (i.e., lower page) values, with a voltage less than Lp0representing a 0 and a voltage greater than Lp0representing a 1. Two read voltage thresholds, Up0and Up1, are further utilized to distinguish between the two possible middle bit (i.e., upper page) values, with a voltage between Up0and Up1representing a 1 and a voltage less than Up0or greater than Up1representing a 0. Finally, four read voltage thresholds Xp0-Xp3are utilized to distinguish between the two possible most significant bit (i.e., extra page) values, with a 0 being represented by a voltage less than Xp0or between Xp1and Xp2or greater than Xp3and a 1 being represented by a voltage between Xp0and Xp1or between Xp2and Xp3. Of course, in other embodiments, different assignments between bit values and read voltage thresholds are possible.

The present application appreciates that the probability of a read error in a page due to data retention effects has a direct relationship to the number of read voltage thresholds utilized to distinguish between the bit values on that page. Thus, if there are N cells per page and the probabilities of an error occurring in a single cell of an additional, extra, upper, and lower page due to data retention effects are given by pa, px, pu, and pl, respectively, then it necessarily follows that Npa>Npx>Npu>Npl. Consequently, in accordance with at least one embodiment, instead of implementing a single calibration interval at which all blocks are recalibrated, multiple different calibration intervals are employed so that pages having a greater probability of failing due to data retention effects are recalibrated more frequently than those that are less likely to fail due to data retention effects. As a result, fewer calibration reads need be performed overall, reducing the total calibration overhead and the associated consumption of power and throughput.

Referring now toFIG. 6, there is depicted a high level logical flowchart of an exemplary process for configuring calibration intervals for different pages based on the pages' relative probabilities of failure due to data retention effects. The process ofFIG. 6can be performed by a controller, such as a GPP132and/or flash controller140. For example, in one embodiment, which will hereafter be assumed, the process is performed by the GPP132of each flash card126through execution of program instructions stored within its associated GPP memory134.

The process ofFIG. 6begins at block600and then proceeds to block602, which illustrates GPP132configuring a calibration interval for lower pages. In at least some preferred embodiments, the calibration interval C1for lower pages is initially configured based on device characterization data, which indicate a data retention period after which tunneling effects will cause the charge on the floating gates of the cells to decrease to the point that an unacceptably high bit error rate (e.g., a bit error rate sufficient to cause a page read failure or a percentage thereof) will be observed. In subsequent reconfigurations, if any, the lower page calibration interval can additionally be configured based on environmental data (e.g., temperature, humidity, etc.) and/or operational data, such as block health metrics332and/or P/E cycle counts334. It should be appreciated that the lower page calibration interval C1for lower pages can be expressed in either chronological time (e.g., second, minutes, hours, and/or days) and/or wear (e.g., P/E cycles).

At block604, GPP132additionally configures calibration intervals of upper pages, extra pages, and/or additional pages (depending on the number of page types supported by the implemented memory devices) based on the lower page calibration interval and relative probability of failure due to data retention effects. For example, in one exemplary implementation, GPP132configures the calibration interval of the upper pages, extra pages, and/or additional pages at a rate directly proportional to the various page types' relative probabilities of failure. If the probabilities of read failure of additional pages, extra pages, upper pages, and lower pages are represented by pa, px, pu, and pl, respectively, then frequency of calibrations of the additional pages Cacan be given by Cl×pa/pl(since additional pages have higher probability of read failures, they have to be calibrated more frequently). Equivalently, the frequency can be inverted to calculate the time interval between calibrations, in which case the time interval between calibrations of the additional pages could be given by Ca=Cl×pl/pa. Similarly for other page types, the calibration interval Cxof the extra pages could be given by Cx=Cl×pl/px, and the calibration interval Cuof the upper pages could be given by Cu=Cl×pl/pu. As noted above, in some embodiments, the probabilities are further directly related to the number of read voltage thresholds per page type, meaning that in these embodiments the additional page calibration interval Cawould have a duration one-eighth that of lower page calibration interval Cl, extra page calibration interval Cxwould have a duration one-fourth that of lower page calibration interval C1, and upper page calibration interval Cuwould have a duration one-half that of lower page calibration interval C1.

Following blocks602and604, GPP132determines at block606whether or not the calibration intervals of the various page types should be reconfigured. For example, GPP132may determine to reconfigure the calibration intervals based on the elapse of time, an average number of P/E cycles across all of its blocks, and/or environmental data, such as temperature. If GPP132determines at block606not to reconfigure the calibration intervals, the process iterates at block606. If, however, GPP132determines to reconfigure the calibration intervals at block606, the process ofFIG. 6returns to blocks602-604, which have been described.

With reference now toFIG. 7, there is depicted a high level logical flowchart of an exemplary process for adapting (calibrating) read voltage thresholds of a non-volatile memory in accordance with one embodiment. The exemplary process, which is preferably performed by a controller, such as a GPP132and/or flash controller140, can be incorporated within background health checker330or can be separately implemented. In various embodiments, the read voltage thresholds can be individually defined for a memory unit at any desired level of granularity (e.g., per-page, per page group within a block, per block, etc.). For ease of understanding, the following description assumes that each page group within a block is formed of pages that are of the same page type (e.g., lower pages, upper pages, extra pages, or additional pages) and that share a common set of read voltage threshold(s)336.

The process ofFIG. 7begins at block700and then proceeds to block702, which illustrates the controller selecting a next block204of memory for read voltage threshold calibration. The controller additionally selects a next page group from the selected block at block704. At block706, the controller determines whether or not the calibration interval for the page type of the pages forming the currently selected page group has elapsed. The controller may make the determination depicted at block706, for example, by reference to per-page group counters within calibration triggers340indicating an elapsed amount of time since read voltage thresholds of that page group were most recently adapted and/or per-page group counters within calibration triggers340indicating a number of P/E cycles that the block has been subjected to since the read voltage thresholds for that page group were last adapted.

In response to a negative determination at block706, read threshold calibration is not performed for the selected page group, and the process returns to block704. If, however, the controller determines at block706that the calibration interval for the page type of the pages forming the currently selected page group has elapsed, the process proceeds in some embodiments directly to block710(while omitting optional block708) and, in other embodiments, proceeds to block710through optional block708.

Block708shows that, in some embodiments, the controller does not perform a calibration read of each page in the selected page group, but instead decreases the number of calibration reads performed to calibrate the read voltage threshold(s) of the selected page group by performing calibration read(s) of, at most, only a smaller representative subset of sample page(s). Accordingly, in embodiments including optional block708, controller selects zero or more sample pages in the selected page group that will be read to calibrate the read voltage threshold(s) for all pages in the selected page group. When fewer sample pages are selected than pages are present in a page group, then the optimal threshold voltages found for these selected one or more pages are used to determine the read voltage thresholds for the entire page group. The determined read voltage thresholds for the page group will later be applied on read operations for any page in the page group even though the page was not used in the calibration process. This sampling comes at the cost of a potential increase in the BER for pages that have not been read during the calibration process. This potential increase in the BER is acceptable as the BER will be below the calibration threshold.

In some embodiments, the controller determines how many and/or which sample page(s) to select at block708utilizing a random or pseudo-random selection. In other embodiments, the controller may make an informed selection of how many and/or which sample page(s) to represent the page group, for example, based on characterization data and/or operational data. For example, in one embodiment, the controller may determine how many and which pages will be read from the selected page group based on bit error rates (BERs) recorded as part of block health metrics332. In some cases, the controller may determine based on operational statistics and/or characterization data that certain page groups have low BERs and may therefore select zero sample pages at block708. In this extreme case, calibration of the read threshold voltage(s) of the selected page group is deferred until a subsequent iteration of the process shown inFIG. 7.

Following block708, if implemented, the controller adapts the read voltage threshold(s) of the page group as indicated by the calibration reads, as shown at block710. One embodiment of this adaptation process is described further below with reference toFIG. 8. Following block710, the controller determines at block712whether or not all page groups of the selected block have been processed. If not, the process ofFIG. 7returns to block704and selects the next page group for calibration, which has been described earlier. If, however, controller determines at block712that all page groups in the currently selected block have been processed, the process returns to block702, where the controller selects a next block of non-volatile memory for read voltage threshold calibration.

In some embodiments of the process ofFIG. 7, the range and number of candidate offset values employed for page reads made during the course of calibration at block710can be static and can be determined, for example, based on characterization data for the memory. In alternative embodiments such as that disclosed inFIG. 8, the range and/or number of candidate offset values represented in an offset set can instead be determined by the controller dynamically based on bit error rate (BER) feedback.

With reference now toFIG. 8, there is illustrated a high level logical flowchart of an exemplary process for dynamically adapting read voltage threshold values for a page based on bit error rate feedback. The process illustrated inFIG. 8can be utilized to implement, for example, the process shown at block710ofFIG. 7.

The process ofFIG. 8begins at block800and then proceeds to block802, which illustrates the controller selecting a first or next page of the page group for processing. If optional block708ofFIG. 7is implemented, the page selected at block802is selected from among only the sample pages identified at block708. In alternative embodiments in which block708is omitted, the controller selects from among all pages in the page group at block802. At block804, the controller reads the selected page of the selected page group utilizing the current read voltage threshold(s) for that page, which corresponds to use of a read voltage offset set of {0}.

Following block804, the process ofFIG. 8proceeds in some embodiments to optional block806, which illustrates the controller determining if the BER obtained by reading the selected page satisfies (e.g., exceeds) a calibration threshold (e.g., a BER corresponding to a page read failure or a percentage thereof). If not, controller may determine that no further reads of the selected page are required for calibration, and the process passes to block816, which is described below. If, on the other hand, the controller determines at block806that the BER obtained by reading the selected page with a current read voltage threshold(s) satisfies the calibration threshold, or if optional block806is omitted, the process passes to block807.

Block807depicts the controller twice reading the current page utilizing read voltage threshold(s) shifted positively and negatively by an initial offset set {±Δ}, where A represents an increment of voltage change. The controller then determines at block808whether or not the read voltage threshold offset resulting in the optimal BER for the page was found utilizing the initial offset set. For example, the controller can determine that the optimal BER has been found if reading the page utilizing the offsets −Δ and +Δ results in greater or equal BERs than utilizing an initial offset of 0. In another embodiment, the controller can determine that the optimal BER has been found if reading the page utilizing the offsets −Δ and +Δ would not reduce the BER more than some configured tolerance BER, which can be given, for example, as an absolute number (certain number of bit errors are tolerated for the given page), or as a percentage of the BER. There can also be additional limitations when the tolerance BER can be applied, for example only in early life, or under low BER values. In response to a determination at block808that the offset providing the optimal BER has been successfully identified, the process proceeds from block808to block814, which is described below. However, in response to a determination at block808that reading data from the memory unit utilizing the current offset set did not definitively identify the offset providing the optimal BER for the page, the process proceeds from block808to block810.

Block810illustrates the controller creating a new offset set to test by utilizing the offset in the previous offset set that provided the lowest BER as the end value of new offset range and by selecting a number of additional offsets and/or offset multipliers. In some embodiments, the range and/or number of offsets selected for inclusion in the new offset set at block810can be determined based on the BER slope observed for the different values in the previous offset set. For example, in some embodiments, at block810the controller employs three offsets in the offset set, but varies a multiplier by which the base offset (Δ) is multiplied based on the BER slope. In other embodiments, both the number of offsets in the new set of offsets and the offset multiplier are varied. In general, the controller may utilize more offsets and/or use larger offset multiplier(s) if the BER slope is relatively large and utilize fewer offsets and/or smaller offset multiplier(s) if the BER slope is relatively small. As one example, assuming that testing utilizing the initial offset set revealed that the offset of −Δ provided the lowest BER, at block810the controller may create a new offset set {-Δ, −2Δ, −3Δ}. In some embodiments, the offset multiplier is varied based on the number of offset sets evaluated until that point at block810. For example, offset multiplier(s) may be larger for the first offset set generated at block810, and the offset multiplier(s) may get reduced for each offset set generated at block810. Such embodiments have the advantage of the improved confidence that the calibration process would terminate successfully in a certain number of steps, even for blocks or technologies that have unstable/unpredictable BER slopes.

At block812, the controller reads data from the memory unit utilizing the read voltage threshold offsets in the updated offset set and notes the BER obtained through the use of each offset. The controller then determines at block808whether or not the offset resulting in the optimal BER for the memory unit was found utilizing the updated offset set. If not, the process returns to block810and following blocks, which have been described. In so doing, the controller incrementally approaches the optimal or near optimal offset that results in the optimal BER for the page. If the controller instead determines at block808that it has found the offset that results in the optimal BER for the page, the controller records the read voltage threshold(s) providing the optimal BER for the page (block814).

The process passes from block814to block816, which illustrates the controller determining if all relevant pages of the page group have been processed. If not, the process returns to block802, which has been described. If, however, all relevant pages of the page group have been processed, the controller determines and records in read voltage thresholds336the new read voltage thresholds to be employed to read from page in the page group during the next calibration interval (block818). In cases in which a calibration read was performed to only a single sample page, the read voltage threshold(s) recorded at block814may be stored in read voltage thresholds336at block818. In cases in which multiple pages were subject to calibration read(s), the controller may determine the per-page group read voltage threshold(s) by taking an average or weighted average of the read voltage thresholds recorded at block814for the individual pages. Following block818, the process ofFIG. 8ends at block820.

In some embodiments, it may be useful and desirable to track the read voltage threshold336for each page group using a combination of multiple parameters. For example, in one embodiment, read voltage thresholds336may be specified by applying an offset to the default read voltage threshold, where the offset comprises a “base” component (Vbase) that tracks a permanent deviation from the default read voltage threshold (e.g., due to P/E cycling) and a “temporary” component (Vtemp) that tracks temporary changes of read voltage thresholds (e.g., due to data retention or read disturb effects).

With reference now toFIGS. 9A-9D, the reduction in page reads made in connection with read voltage threshold calibration according to the various disclosed techniques is illustrated. As indicated above, a controller may employ a single one of the disclosed techniques to reduce the number of calibration reads or may employ multiple of the disclosed techniques in combination. Further, the controller may dynamically adapt which of the disclosed technique(s) is employed, for example, characterization data, block health metrics332, P/E cycle counts, a number of page read failures, etc.

Each ofFIGS. 9A-9Dillustrates an exemplary block900of non-volatile memory comprising a plurality of page groups902numbered 1, 2, 3, 4, 5, 6, 7, 8, . . . . Each of these page groups, in turn, includes a multiplicity of physical pages of storage.

FIG. 9Aillustrates the calibration reads performed in connection with read voltage threshold calibration of block900in an embodiment omitting optional blocks708and806. Specifically,FIG. 9Ashows that when the calibration interval for a page group902elapses, the page group902is calibrated utilizing three or more (denoted as 3+) calibration reads to each page904in the page group902. It should be noted that in this embodiment, the overall number of page reads performed in connection with read voltage threshold calibration are still reduced as compared to prior art systems because page groups902formed of upper pages, extra pages, and additional pages are calibrated less frequently than page groups formed of lower pages

FIG. 9Bdepicts the reductions of calibration reads performed in connection with read voltage threshold calibration of block900in an embodiment including optional block708, but omitting optional block806. In this example, based on the decision made in block706the controller selects zero sample pages to read from (i.e., does not calibrate) page groups that execution statistics and/or characterization data indicate are unlikely to need calibration. At block708, the controller selects two sample pages from page groups that are indicated at block706as suitable for calibration by execution statistics and/or page type and/or characterization data indicating a higher variability among page BERs. At block708, the controller also selects a single sample page to read from each other page group. Utilizing these settings, during the course of a sequence of read voltage threshold calibration, the controller will perform no calibration read to pages within page groups 1 and 8, will perform three or more calibration reads to a single sample page in each of page groups 2-3 and 5-6, and will perform three or more calibration reads to two sample pages in each of page groups 4 and 7.

FIG. 9Cillustrates the calibration reads performed in connection with read voltage threshold calibration of block900in an embodiment omitting optional block708and including optional block806. For simplicity, this example shows an embodiment in which the controller selects all page groups for calibration at block706, so all reductions in calibration reads are made by block806only. In this example, the controller tests each page904with a single read utilizing the current read voltage threshold(s) prior to proceeding to additional calibration reads. As a result, during the course of a sequence of read voltage threshold calibration, the controller may perform only a single calibration read to each page904in page groups 1-3, 5-6, and 8 and perform three or more calibration reads to each page in page groups 4 and 7.

Finally,FIG. 9Ddepicts the calibration reads performed in connection with read voltage threshold calibration of block900in an embodiment including both optional blocks708and806. In this example, the controller greatly reduces the number of calibration reads by employing execution statistics and/or characterization data at block706, by implementing page sampling at block708, and by testing the bit error rate obtained from calibration reads against a calibration threshold at block806. As shown, during the course of a sequence of read voltage threshold calibration, the controller may perform no calibration read to pages within page groups 1 and 8, perform a single calibration read to a single page in each of page groups 2-3 and 5-6, and perform three or more calibration reads to one page in each of page groups 4 and 7.

As has been described, in at least one embodiment, a non-volatile memory includes a plurality of cells each individually capable of storing multiple bits of data including bits of multiple physical pages including at least a first page and a second page. A controller of the non-volatile memory determines a first calibration interval for a first read voltage threshold defining a bit value in the first page and a different second calibration interval for a second read voltage threshold defining a bit value in the second page. The second calibration interval has a shorter duration than the first calibration interval. The controller calibrates the first and second read voltage thresholds for the plurality of memory cells in the non-volatile memory based on the determined first and second calibration intervals.

While the present invention has been particularly shown as described with reference to one or more preferred embodiments, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention. For example, although aspects have been described with respect to a data storage system including a flash controller that directs certain functions, it should be understood that present invention may alternatively be implemented as a program product including a storage device storing program code that can be processed by a processor to perform such functions or cause such functions to be performed. As employed herein, a “storage device” is specifically defined to include only statutory articles of manufacture and to exclude signal media per se, transitory propagating signals per se, and energy per se.

In addition, although embodiments have been described that include use of a NAND flash memory, it should be appreciated that embodiments of the present invention can also be used with any other type of non-volatile random access memory (NVRAM).