Semiconductor memory device and method of operating semiconductor memory device

A semiconductor memory device includes a memory cell array and an on-die error correction code (ECC) engine. The on-die ECC engine, during a write operation, generates a second main data by encoding a first main data with a random binary code, performs an ECC encoding on the second main data to generate a parity data and stores the second main data and the parity data in a target page in the memory cell array. The on-die ECC engine, during a read operation, reads the second main data and the parity data from the target page, performs an ECC decoding on the second main data based on the parity data to generate a syndrome in parallel with generating the first main data by encoding the second main data with the random binary code and corrects at least one error bit in the first main data based on the syndrome.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2022-0144414, filed on Nov. 2, 2022, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety.

BACKGROUND

The present disclosure relates to memories, and more particularly to a semiconductor memory device and a method of operating a semiconductor memory device.

Semiconductor memory devices may be classified into non-volatile memory devices, such as flash memory devices, and volatile memory devices such as dynamic random access memories (DRAMs). High-speed operation and cost efficiency of DRAMs make it possible for DRAMs to be used for system memories. Due to the continuing shrink in integrated circuit (IC) dimensions resulting, at least in part, from the scaling of IC fabrication design rules of DRAMs, capacitance of a capacitor included in a memory cell will decrease, and thus noise may occur according to a format of data stored in a memory core.

SUMMARY

Some example embodiments provide a semiconductor memory device capable of enhancing operating characteristics and reducing a size of logic.

Some example embodiments provide a method of operating a semiconductor memory device, capable of enhancing operating characteristics and reducing a size of logic.

According to some example embodiments, a semiconductor memory device includes a memory cell array, an on-die error correction code (ECC) engine and a control logic circuit. The on-die ECC engine, during a write operation, may generate a second main data by scrambling (i.e., encoding) a first main data received from an external device with a random binary code received from the control logic circuit, perform an ECC encoding on the second main data to generate a parity data, and store the second main data and the parity data in a target page in the memory cell array. The on-die ECC engine, during a read operation, may read the second main data and the parity data from the target page, perform an ECC decoding on the second main data based on the parity data to generate a syndrome in parallel with generating the first main data by scrambling the second main data with random binary code, and correct at least one error bit in the first main data based on the syndrome.

According to some example embodiments, a semiconductor memory device includes a memory cell array, an on-die error correction code (ECC) engine and a control logic circuit. The on-die ECC engine, during a write operation, may generate a scrambled main data by scrambling (i.e., encoding) a main data received from an external device with a random binary code received from the control logic circuit, perform an ECC encoding on the scrambled main data to generate a parity data, and store the scrambled main data and the parity data in a target page in the memory cell array. The on-die ECC engine, during a read operation, reads the scrambled main data and the parity data from the target page, performs an ECC decoding on the scrambled main data based on the parity data to generate a syndrome in parallel with generating the main data by scrambling the scrambled main data with random binary code and corrects at least one error bit in the main data based on the syndrome.

According to some example embodiments, in a method of operating a semiconductor memory device that includes a memory cell array including a plurality of memory cells coupled to a plurality of word-lines and a plurality of bit-lines and an on-die error correction code (ECC) engine, a second main data is generated, by the on-die ECC engine, by scrambling (i.e., encoding) a first main data with a random binary code, the second main data and a parity data generated based on the first main data are stored in a target page in the memory cell array, an ECC decoding is performed, by the on-die ECC engine, on the second main data read from the target page based on the parity data read from the target page to generate a syndrome in parallel with generating the first main data by scrambling (i.e., encoding) the second main data with a random binary code, and at least one error bit in the first main data is corrected based on the syndrome by the on-die ECC engine.

Accordingly, the semiconductor memory device according to example embodiments, generates the first main data by scrambling (i.e., encoding) the second main data with the random binary code in parallel with generating a syndrome by performing an ECC decoding on the second main data read from the memory cell array and corrects at least one error bit in the first main data based on the syndrome. Because the semiconductor memory device does not perform data scrambling (i.e., encoding) after performing the ECC decoding, the data scrambling does not need extra time. Therefore, the semiconductor memory device according to aspects of the present inventive concept may reduce latency associated with the read operation while reducing pattern noise that occurs when fixed data patterns are repeated and may reduce a size of logic circuitry associated with the data scrambling.

DETAILED DESCRIPTION

Various example embodiments of the present disclosure will be described more fully hereinafter with reference to the accompanying drawings. Like reference numerals may refer to like elements throughout the accompanying drawings.

FIG.1is a block diagram illustrating a memory system according to example embodiments of the present disclosure.

Referring toFIG.1, a memory system20may include a memory controller100(e.g., an external device) and a semiconductor memory device200.

The memory controller100may control the overall operation of the memory system20. The memory controller100may control the overall data exchange between an external host and the semiconductor memory device200. For example, the memory controller100may write data in the semiconductor memory device200or read data from the semiconductor memory device200in response to a request from the host. In addition, the memory controller100may issue operation commands to the semiconductor memory device200for controlling the semiconductor memory device200.

In example embodiments, the semiconductor memory device200is a memory device including a plurality of dynamic (volatile) memory cells such as a dynamic random access memory (DRAM), or a graphic double data rate 7 (GDDR7) synchronous DRAM (SDRAM).

The memory controller100, in one or more embodiments, may be configured to transmit a clock signal CLK, a command CMD, and an address (signal) ADDR to the semiconductor memory device200, and to exchange a first main data MD1with the semiconductor memory device200.

The memory controller100may include a central processing unit (CPU)110and a data scrambler (i.e., encoder)125.

The CPU110may control overall operation of the memory controller100and the data scrambler125may generate the first main data MD1by scrambling (i.e., encoding) an original main data based on a user data with a random binary code.

The semiconductor memory device200may include a memory cell array310that stores a second main data corresponding to the first main data MD1, an on-die error correction code (ECC) engine400and a control logic circuit210. In one or more embodiments, the CPU110may be configured to determine whether the on-die ECC engine400is operating normally based on a severity signal (or other indicator) which may be generated in a test mode of the semiconductor memory device200. The memory cell array310may include a plurality of sub-array blocks arranged in a first direction and a second direction, the second direction intersecting with the first direction (not explicitly shown, but implied).

The on-die ECC engine400, during a write operation, may generate the second main data by scrambling the first main data MD1with a random binary code received from the control logic circuit210, may perform an ECC encoding on the second main data to generate a parity data, and may store the second main data and the parity data in a target page in the memory cell array310.

The on-die ECC engine400, during a read operation, may read the second main data and the parity data from the target page, perform an ECC decoding on the second main data based on the parity data to generate a syndrome in parallel with generating the first main data MD1by scrambling the second main data with a random binary code, and may correct at least one error bit in the first main data MD1based on the syndrome.

Each of the first main data MD1and the second main data may include a plurality of data bits, and the plurality of data bits may be divided into a plurality of sub-data units. The first main data MD1may include a plurality of first sub-data units and the second main data may include a plurality of second sub-data units.

The semiconductor memory device200may perform a burst operation. Herein, the “burst operation” refers to an operation of writing or reading a large amount of data by sequentially increasing or decreasing an initial address provided from the memory controller100. A basic unit of the burst operation may be referred to a burst length BL. In example embodiments, the burst length BL may refer to the number of operations of continuously reading or writing data by sequentially increasing or decreasing an initial address.

FIG.2illustrates a first main data MD1corresponding to the plurality of burst lengths in the memory system ofFIG.1, according to some example embodiments.

Referring toFIG.2, the first main data MD1corresponding to the plurality of burst lengths may be input to/output from the semiconductor memory device200(seeFIG.1). The first main data MD1may include a plurality of first sub-data units SDU11, SDU12, SDU13, . . . , SDU1t(where t is a natural number equal to or greater than 8), each of the first sub-data units corresponding to each of the plurality of burst lengths. The burst length is assumed to be 32 inFIG.2, although embodiments of the invention are not limited to a specific burst length. The second main data, corresponding to the first main data MD1corresponding to the plurality of burst lengths, may be stored in the memory cell array310of the semiconductor memory device200(seeFIG.1).

FIG.3is a block diagram illustrating at least a portion of the exemplary memory controller100shown inFIG.1, according to some example embodiments.

Referring toFIG.3, the memory controller100may include the CPU110, a data buffer120, the data scrambler125, a (system) ECC engine130, a command buffer180and an address buffer190. The ECC engine130may include a parity generator140, a buffer145, a memory150configured to store a second ECC (ECC2)155, and an ECC decoder160.

The CPU110may receive a request REQ and data DTA from the host (external to the memory controller100), and may provide the data DTA to the data buffer120and the parity generator140.

The data buffer120may buffer the data DTA to provide an original main data MD to the data scrambler125.

The data scrambler125may generate the first main data MD1based on data bits of the original main data MD combined with a random binary code RBC and may provide the first main data MD1to the parity generator140and the semiconductor memory device200(seeFIG.1).

The parity generator140is connected to the memory150, may perform an ECC encoding on the first main data MD1using the second ECC155to generate a parity data PRTc, and may store the parity data PRTc in the buffer145.

The ECC decoder160, during a read operation of the semiconductor memory device200, may receive the first main data MD1from the semiconductor memory device200, may perform an ECC decoding on the first main data MD1by using the second ECC (ECC2)155and the system parity data PRTc, and may provide a corrected main data C_MD1to the CPU110. The CPU110may provide the corrected main data C_MD1to the host.

The command buffer180may store the command CMD corresponding to the request REQ and may transmit the command CMD to the semiconductor memory device200(seeFIG.1) under control of the CPU110. The address buffer190may store the address ADDR and may transmit the address ADDR to the semiconductor memory device200(seeFIG.1) under control of the CPU110.

FIG.4is a block diagram illustrating at least a portion of the exemplary ECC decoder160in the memory controller100ofFIG.3, according to example embodiments.

Referring toFIG.4, the ECC decoder160may include a check bit generator161, a syndrome generator163and a data corrector165.

The check bit generator161may receive the first main data MD1, and may generate check bits CHBc corresponding to the first main data MD1using the second ECC155.

The syndrome generator163may compare the parity data PRTc and the check bits CHBc bit by bit to generate a syndrome data SDRc indicating whether the first main data MD1includes at least one error bit and indicating a position of the at least one error bit in the first main data MD1stream.

The data corrector165may receive the first main data MD1and may correct the error bit(s) in the first main data MD1based, at least in part, on the syndrome data SDRc to output the corrected main data C_MD1.

FIG.5is a block diagram illustrating at least a portion of the exemplary semiconductor memory device200in the illustrative memory system20ofFIG.1, according to example embodiments.

Referring toFIG.5, the semiconductor memory device200may include the control logic circuit210, an address register220, a bank control logic230, a refresh counter245, a row address (RA) multiplexer240, a column address (CA) latch250, a row decoder260, a column decoder270, the memory cell array310, a sense amplifier unit285, an input/output (I/O) gating circuit290, the on-die ECC engine400and a data I/O buffer295.

The memory cell array310may include first through eighth bank arrays310a-310h, although embodiments of the present inventive concept are not limited to this or any specific number of bank arrays. The row decoder260may include first through eighth bank row decoders260a˜260hrespectively coupled to the first through eighth bank arrays310a-310h, the column decoder270may include first through eighth bank column decoders270a˜270hrespectively coupled to the first through eighth bank arrays310a-310h, and the sense amplifier unit285may include first through eighth bank sense amplifiers285a˜285hrespectively coupled to the first through eighth bank arrays310a-310h.

The first through eighth bank arrays310a-310h, the first through eighth bank row decoders260a˜260h, the first through eighth bank column decoders270a˜270hand first through eighth bank sense amplifiers285a˜285hmay form first through eighth banks. Each of the first through eighth bank arrays310a-310hmay include a plurality of volatile memory cells MC, the memory cells MC being preferably formed at unique intersections of a plurality of word-lines WL and a plurality of bit-line BTL.

The address register220may receive the address ADDR, including a bank address BANK_ADDR, a row address ROW_ADDR and a column address COL_ADDR, from the memory controller100. The address register220may provide the received bank address BANK_ADDR to the bank control logic230, may provide the received row address ROW_ADDR to the row address multiplexer240, and may provide the received column address COL_ADDR to the column address latch250.

The bank control logic230may generate bank control signals in response to the bank address BANK_ADDR. One of the first through eighth bank row decoders260a˜260hcorresponding to the bank address BANK_ADDR may be activated in response to receipt of the corresponding one of the bank control signals, and one of the first through eighth bank column decoders270a˜270hcorresponding to the bank address BANK_ADDR may be activated in response to receipt of the corresponding one of the bank control signals.

The row address multiplexer240may receive the row address ROW_ADDR from the address register220, and may receive a refresh row address REF_ADDR from the refresh control circuit385. The row address multiplexer240selectively may output the row address ROW_ADDR or the refresh row address REF_ADDR as a row address RA. The row address RA that is output from the row address multiplexer240may be applied to the first through eighth bank row decoders260a˜260h.

The refresh counter245may sequentially increase or decrease the refresh row address REF_ADDR under control of the control logic circuit210.

The control logic circuit210may be configured to receive the command CMD supplied from the memory controller100(seeFIG.1). When the command CMD from the memory controller100corresponds to an auto refresh command or a self-refresh entry command, the control logic circuit210may control the refresh counter245to output the refresh row address REF_ADDR sequentially.

The activated one of the first through eighth bank row decoders260a˜260h, by the bank control logic230, may decode the row address RA that is output from the row address multiplexer240, and may activate a word-line corresponding to the row address RA. For example, the activated row decoder may apply a word-line driving voltage to the word-line corresponding to the row address RA.

The column address latch250may receive the column address COL_ADDR from the address register220, and may at least temporarily store the received column address COL_ADDR. In some embodiments, in a burst mode, the column address latch250may generate column address COL_ADDR′ that increments from the received column address COL_ADDR. The column address latch250may apply the temporarily stored or generated column address COL_ADDR′ to the first through eighth bank column decoders270a˜270h.

The activated one of the first through eighth column decoders270a˜270hmay, in turn, activate a sense amplifier corresponding to the bank address BANK_ADDR and the column address COL_ADDR′ through the I/O gating circuit290.

The I/O gating circuit290may include circuitry for gating input/output data, and may further include input data mask logic, read data latches for storing data that is output from the first through eighth bank arrays310a˜310h, and write drivers for writing data to the first through eighth bank arrays310a˜310h.

A codeword CW read from a selected bank array of the first through eighth bank arrays310a˜310hmay be sensed by a corresponding one of the first through eighth sense amplifiers285a˜285hcoupled to the selected bank array from which the data is to be read, and may be stored in corresponding read data latches in the I/O gating circuit290. The codeword CW stored in the read data latches may be provided to the on-die ECC engine400. The on-die ECC engine400may generate the first main data MD1by performing ECC decoding on the codeword CW and the first main data MD1may be transmitted to the memory controller100via the data I/O buffer295after ECC decoding is performed on the codeword CW by the on-die ECC engine400.

The first main data MD1to be written in one bank array of the first through eighth bank arrays310a-310hmay be provided to the data I/O buffer295from the memory controller100, and may be provided to the on-die ECC engine400from the data I/O buffer295. The on-die ECC engine400may generate the second main data based on the first main data MD1, may generate parity data based on the second main data and may provide the I/O gating circuit290with the codeword CW including the second the main data and the parity data to the I/O gating circuit290. The I/O gating circuit290may write the codeword CW in a sub-page of a target page in one bank array through the write drivers in the I/O gating circuit290.

The data I/O buffer295may provide the first main data MD1from the memory controller100to the on-die ECC engine400during a write operation of the semiconductor memory device200, and may provide the first main data MD1provided from the on-die ECC engine400to the memory controller100during the read operation of the semiconductor memory device200.

The on-die ECC engine400, during the write operation, may generate the second main data by scrambling (i.e., encoding) the first main data MD1with a random binary code RBC received from the control logic circuit210, may perform an ECC encoding on the second main data to generate the parity data, and may store the second main data and the parity data in a target page in the memory cell array310.

The on-die ECC engine400, during the read operation, may read the second main data and the parity data from the target page, perform an ECC decoding on the second main data based on the parity data to generate the syndrome in parallel with generating the first main data MD1by scrambling the second main data with random binary code RBC, and may correct at least one error bit in the first main data MD1based at least in part on the syndrome.

The control logic circuit210may control one or more operations of the semiconductor memory device200. For example, the control logic circuit210may generate control signals for the semiconductor memory device200in order to perform a write operation, a read operation and operation in a test mode. The control logic circuit210may include a command decoder211configured to decode the command CMD received from the memory controller100and mode register212that sets an operation mode of the semiconductor memory device200. The random binary code RBC may be set in the mode register212by the memory controller100and the control logic circuit210may provide the on-die ECC engine400with the random binary code RBC set in the mode register212.

For example, the command decoder211may generate the control signals corresponding to the command CMD by decoding a write enable signal, a row address strobe signal, a column address strobe signal, a chip select signal, etc.

The control logic circuit210may generate a first control signal CTL1to control the I/O gating circuit290and a second control signal CTL2to control the on-die ECC engine400by decoding the command CMD supplied to the control logic circuit210.

FIG.6illustrates an example of at least a portion of the first bank array310ain the semiconductor memory device ofFIG.5, according to example embodiments.

Referring toFIG.6, the first bank array310amay include a plurality of word-lines WL0˜WLm−1 (where m is an even number equal to or greater than two), a plurality of bit-lines BTL0˜BTLn−1 (where n is an even number equal to or greater than two), and a plurality of memory cells MCs disposed at intersections between the word-lines WL0˜WLm−1 and the bit-lines BTL0˜BTLn−1.

The word-lines WL0˜WLm−1 may extend in a first direction D1(e.g., row or horizontal) and the bit-lines BTL0˜BTLn−1 may extend in a second direction D2(e.g., column or vertical direction). It is to be appreciated that embodiments of the present inventive concept are not limited to any specific orientation of the word-lines and bit-lines.

Each of the memory cells MCs includes an access (cell) transistor coupled to one of the word-lines WL0˜WLm−1 and one of the bit-lines BTL0˜BTLn−1, and a storage (cell) capacitor coupled to the cell transistor. That is, each of the memory cells MCs has a DRAM cell structure.

In addition, the memory cells MCs may have a different arrangement depending on whether the memory cells MCs are coupled to an even word-line (for example, WL0) or an odd word-line (for example, WL1). That is, a bit-line coupled to adjacent memory cells may be different depending on whether a word-line selected by an access address is an even word-line or an odd word-line.

FIG.7is a block diagram illustrating at least a portion of the example on-die ECC engine400in the semiconductor memory device200ofFIG.5, according to example embodiments.

Referring toFIG.7, the on-die ECC engine400may include a first data scrambler (encoder)410, a write first-in, first-out (FIFO) register420, a second data scrambler (encoder)430, a read FIFO register425, a multiplexer427, an encoding/decoding logic440, a data corrector470, and a buffer circuit490.

The buffer circuit490may include a plurality of buffers, for example buffers491,492,493and494. Each of the buffers491,492,493and494may be non-inverting buffers, although inverting buffers are similarly contemplated. The buffers491,492,493and494may be controlled by a buffer control signal BCTL.

The first data scrambler410may generate a second main data MD2by scrambling (i.e., encoding) the first main data MD1with the random binary code RBC during the write operation and may store the second main data MD2in the write FIFO register420. The second main data MD2stored in the write FIFO register420may be stored in the target page of the memory cell array310(seeFIG.5) through the buffer491.

The multiplexer427may provide the encoding/decoding logic440with the second main data output MD2from the first data scrambler410during the write operation and may provide the encoding/decoding logic440with the second main data MD2read from the target page through the buffer492, in response to a selection signal S Sl.

The second data scrambler430may receive the second main data MD2from the buffer492, may generate the first main data MD1by scrambling (i.e., encoding) the second main data MD2with the random binary code RBC, during the read operation, and may provide the first main data MD1for storage in the read FIFO register425. The read FIFO register425may provide the first main data MD1to the data corrector470. The first main data MD1generated by the second data scrambler430may be referred to as a third main data. Because the third main data may be generated by scrambling the first main data MD1with the random binary code RBC and the scrambling corresponds to an XOR operation, the third main data may correspond to the first main data MD1.

The encoding/decoding logic440, during the write operation, may receive the second main data MD2from the multiplexer427, may generate a parity data PRT by performing an ECC encoding on the second main data MD2, and may provide the parity data PRT to the target page of the memory cell array310(seeFIG.5) through the buffer493. The encoding/decoding logic440, during the read operation, may receive the second main data MD2from the multiplexer427, may receive the parity data PRT from the buffer494, may generate a syndrome SDR by performing an ECC decoding on the second main data MD2and the parity data PRT and may provide the syndrome SDR to the data corrector470.

During the read operation, the encoding/decoding logic440may generate the syndrome SDR by performing the ECC decoding on the second main data MD2and the parity data PRT and may provide the syndrome SDR to the data corrector470in parallel with the second data scrambler430generating the first main data MD1by scrambling the second main data MD2with the random binary code RBC, and providing the first main data MD1for storage in the read FIFO register425.

The data corrector470, during the read operation, may receive the first main data MD1from the read FIFO register425and may output a corrected data C_MD1by correcting at least one error bit in the first main data MD1based on the syndrome SDR.

The buffer control signal BCTL and the selection signal SS1inFIG.7may be included in the second control signal CTL2inFIG.5.

FIG.8illustrates examples of the first main data, the second main data and the random binary code RBC in the example on-die ECC engine400shown inFIG.7, according to example embodiments.

Referring toFIG.8, the first main data MD1may include a plurality of first sub-data units SDU11, SDU12, . . . , SDU1t, and each of the plurality of first sub-data units SDU11, SDU12, . . . , SDU1tmay include first data bits. For example, the first sub-data unit SDU11may include first data bits DQ11˜DQ18. Hereinafter, for convenience of explanation, it may be assumed that the each of the plurality of first sub-data units SDU11, SDU12, . . . , SDU1tincludes the first data bits DQ11˜DQ18.

The second main data MD2may include a plurality of second sub-data units SDU21, SDU22, . . . , SDU2tand each of the plurality of second sub data units SDU21, SDU22, . . . , SDU2tmay include second data bits. For example, the second sub-data unit SDU21may include second data bits DQ21˜DQ28. Hereinafter, for convenience of explanation, it may be assumed that the each of the plurality of second sub-data units SDU21, SDU22, . . . , SDU2tincludes the second data bits DQ21˜DQ28.

The random binary code RBC may include a plurality of code bits CB1, CB2, . . . , CBt corresponding to a number of each of the plurality of first sub-data units SDU11, SDU12, . . . , SDU1tand the plurality of second sub-data units SDU21, SDU22, . . . , SDU2t. Each of the plurality of code bits CB1, CB2, . . . , CBt may have one of a first logic level (i.e., a logic high level or “1”) and a second logic level (i.e., a logic low level or “0”) randomly.

Accordingly, the first data scrambler410inFIG.7may generate the second main data MD2including the second sub-data units SDU21, SDU22, . . . , SDU2tby scrambling the first data bits DQ11˜DQ18of each of the first sub-data units SDU11, SDU12, . . . , SDU1twith a corresponding code bit of the plurality of code bits CB1, CB2, . . . , CBt. The second data scrambler430inFIG.7may generate the first main data MD1including the first sub-data units SDU11, SDU12, . . . , SDU1tby scrambling the second data bits DQ21˜DQ28of each of the second sub-data units SDU21, SDU22, . . . , SDU2twith a corresponding code bit of the plurality of code bits CB1, CB2, . . . , CBt.

FIG.9Ais a circuit diagram illustrating an example of the first data scrambler410in the illustrative on-die ECC engine400ofFIG.7, according to example embodiments.

Referring toFIG.9A, the first data scrambler410may include a plurality of XOR gates411,412,413,414,415,416,417and418. Each of the plurality of XOR gates411,412,413,414,415,416,417and418may generate a corresponding one of the second data bits DQ21, DQ22, DQ23, DQ24, DQ25, DQ26, DQ27and DQ28, respectively, of each of the second sub-data units SDU21, SDU22, . . . , SDU2tby performing an XOR operation on a respective one of the first data bits DQ11, DQ12, DQ13, DQ14, DQ15, DQ16, DQ17and DQ18of each of the first sub-data units SDU11, SDU12, . . . , SDU1tand a corresponding code bit of the plurality of code bits CB1, CB2, . . . , CBt of the random binary code RBC.

When the corresponding code bit of the plurality of code bits CB1, CB2, . . . , CBt has a first logic level, a corresponding one of the first data bits DQ11, DQ12, DQ13, DQ14, DQ15, DQ16, DQ17and DQ18is inverted and is provided as a corresponding one of the second data bits DQ21, DQ22, DQ23, DQ24, DQ25, DQ26, DQ27and DQ28. When the corresponding code bit of the plurality of code bits CB1, CB2, . . . , CBt has a second logic level, a corresponding one of the first data bits DQ11, DQ12, DQ13, DQ14, DQ15, DQ16, DQ17and DQ18is maintained (i.e., is non-inverted) and is provided as a corresponding one of the second data bits DQ21, DQ22, DQ23, DQ24, DQ25, DQ26, DQ27and DQ28.

FIG.9Bis a circuit diagram illustrating an example of the second data scrambler430in the on-die ECC engine400ofFIG.7, according to example embodiments.

Referring toFIG.9B, the second data scrambler430, like the first data scrambler410, may include a plurality of XOR gates431,432,433,434,435,436,437and438. Each of the plurality of XOR gates431,432,433,434,435,436,437and438may generate a corresponding one of the first data bits DQ11, DQ12, DQ13, DQ14, DQ15, DQ16, DQ17and DQ18, respectively, of each of the first sub-data units SDU11, SDU12, . . . , SDU1tby performing an XOR operation on respective one of the second data bits DQ21, DQ22, DQ23, DQ24, DQ25, DQ26, DQ27and DQ28of each of the second sub-data units SDU21, SDU22, . . . , SDU2tand a corresponding code bit of the plurality of code bits CB1, CB2, . . . , CBt of the random binary code RBC.

When the corresponding code bit of the plurality of code bits CB1, CB2, . . . , CBt has a first logic level, a corresponding one of the second data bits DQ21, DQ22, DQ23, DQ24, DQ25, DQ26, DQ27and DQ28is inverted and is provided as a corresponding one of the first data bits DQ11, DQ12, DQ13, DQ14, DQ15, DQ16, DQ17and DQ18. When the corresponding code bit of the plurality of code bits CB1, CB2, . . . , CBt has a second logic level, a corresponding one of the second data bits DQ21, DQ22, DQ23, DQ24, DQ25, DQ26, DQ27and DQ28is maintained (i.e., is non-inverted) and is provided as a corresponding one of the first data bits DQ11, DQ12, DQ13, DQ14, DQ15, DQ16, DQ17and DQ18.

Each of the second sub-data units SDU21, SDU22, . . . , SDU2tmay be stored in a same sub-array block from among the plurality of sub-array blocks in the memory cell array310(seeFIG.5). Therefore, a same code bit (for example, the code bit CB1) may be applied to the first data bits DQ11, DQ12, DQ13, DQ14, DQ15, DQ16, DQ17and DQ18of the first sub-data unit SDU11and to second data bits DQ21, DQ22, DQ23, DQ24, DQ25, DQ26, DQ27and DQ28of the second sub-data unit SDU21.

FIG.10illustrates an example of the encoding/decoding logic440in the on-die ECC engine400ofFIG.7, according to example embodiments.

Referring toFIG.10the encoding/decoding logic440may include a parity generator441, a check bit generator443, a syndrome generator450and a memory445. The memory445may store a first ECC (ECC1)447.

The parity generator441may be connected to the memory445and may generate the parity data PRT based on the second main data MD2using an array of exclusive OR gates.

The check bit generator443may be connected to the memory445and may generate check bits CHB based on the second main data MD2using the first ECC447during the read operation.

The syndrome generator450may generate the syndrome data SDR based on the check bits CHB, based on the second main data MD2, and the parity data PRT from the buffer494(seeFIG.7) during the read operation. The syndrome generator450may generate the syndrome SDR based on whether each of the check bits CHB matches a corresponding one of the bits of the parity data PRT.

The syndrome SDR may include a plurality of syndrome bits and each of the plurality of syndrome bits may indicate whether each of the check bits CHB matches a corresponding one of the bits of the parity data PRT. Therefore, the syndrome SDR may indicate a position of the error bit and a number of the error bit.

FIG.11illustrates an example of the data corrector470in the on-die ECC engine400ofFIG.7, according to example embodiments.

Referring toFIG.11, the data corrector470may include a syndrome decoder471, a bit inverter473and a selection circuit475which may be implemented by a multiplexer.

The syndrome decoder471may decode the syndrome SDR supplied thereto and generate a decoding signal DS and a second selection signal SS2. The decoding signal DS may indicate a position of the at least one error and the second selection signal SS2may have a logic level indicative of a number of the at least one error bit. The bit inverter473may invert the at least one error bit in response to the decoding signal DS. The selection circuit475may select one of the first main data MD1and an output of the bit inverter473to provide the corrected main data C_MD1in response to the second selection signal SS2.

FIG.12illustrates an example of the first bank array310ain the semiconductor memory device200ofFIG.5, according to example embodiments.

Referring toFIG.12, in the first bank array310a, I sub-array blocks SCB may be disposed in the first direction D1, and J sub-array blocks SCB may be disposed in the second direction D2substantially perpendicular to the first direction D1. I and J represent a number of the sub-array blocks SCB in the first direction D1and the second direction D2, respectively, and are natural numbers greater than two. Embodiments of the inventive concept are not limited to any specific number for I and J, and furthermore I and J need not be the same number (although they can be).

A plurality of bit-lines, a plurality of word-lines and a plurality of memory cells connected to the bit-lines and the word-lines are disposed in each of the sub-array blocks SCB.

I+1 sub word-line driver regions SWB may be disposed between the sub-array blocks SCB in the first direction D1as well on each side of each of the sub-array blocks SCB in the first direction D1. Sub word-line drivers may be disposed in the sub word-line driver regions SWB. J+1 bit-line sense amplifier regions BLSAB may be disposed, for example between the sub-array blocks SCB in the second direction D2and above and below each of the sub-array blocks SCB in the second direction D2. Bit-line sense amplifiers to sense data stored in the memory cells may be disposed in the bit-line sense amplifier regions BLSAB.

A plurality of sub word-line drivers may be provided in each of the sub word-line driver regions SWB. One sub word-line driver region SWB may be associated with two sub-array blocks SCB adjacent to the sub word-line driver region SWB in the first direction D1.

A plurality of conjunction regions CONJ may be disposed adjacent the sub word-line driver regions SWB and the bit-line sense amplifier regions BLSAB. A voltage generator may be disposed in each of the conjunction regions CONJ. A portion390in the first bank array310amay be described in further detail with reference toFIG.13below.

FIG.13illustrates a portion390of the first bank array310ainFIG.12, according to example embodiments.

Referring toFIGS.12and13, the portion390of the first bank array310aincludes the sub-array block SCB, two bit-line sense amplifier regions BLSAB1and BLSAB2, two of the sub word-line driver regions SWB and four of the conjunction regions CONJ.

The sub-array block SCB includes a plurality of word-lines WL1˜WL4, extending in the first direction D1, and a plurality of bit-line pairs BTL1˜BTLB1and BTL2˜BTLB2, extending in the second direction D2. The direction D1may be perpendicular to the direction D2. The sub-array block SCB includes a plurality of memory cells MCs disposed at intersections of the word-lines WL1˜WL4and the bit-line pairs BTL1˜BTLB1and BTL2˜BTLB2.

With reference toFIG.13, the sub word-line driver regions SWB include a plurality of sub word-line drivers SWDs551,552,553and554that respectively drive the word-lines WL1˜WL4. The sub word-line drivers551and552may be disposed in the sub word-line driver region SWB, which is leftward (in this example), with respect to the sub-array block SCB. In addition, the sub word-line drivers553and554may be disposed in the sub word-line driver region SWB, which is rightward (in this example), with respect to the sub-array block SCB.

The bit-line sense amplifier regions BLSAB1and BLSAB2include a bit-line sense amplifier BLSA560and a bit-line sense amplifier563, respectively, coupled to corresponding bit-line pairs BTL1˜BTLB1and BTL2˜BTLB2, and respective local sense amplifier (LSA) circuits570and573. The bit-line sense amplifier560may sense and amplify a voltage difference between the bit-line pair BTL1and BTLB1to provide an amplified voltage difference to a local I/O line pair LIO1and LIOB1. The bit-line sense amplifier563may sense and amplify a voltage difference between the bit-line pair BTL2and BTLB2to provide the amplified voltage difference to a local I/O line pair LIO2and LIOB2.

The local sense amplifier circuit570may control connection between the local I/O line pair LIO1and LIOB1and a global I/O line pair GIO1and GIOB1. Similarly, the local sense amplifier circuit573may control connection between the local I/O line pair LIO2and LIOB2and a global I/O line pair GIO2and GIOB2.

As illustrated inFIG.13, the bit-line sense amplifier560and the bit-line sense amplifier563may be alternately disposed at an upper portion and a lower portion of the sub-array block SCB. The conjunction regions CONJ are disposed adjacent to the bit-line sense amplifier regions BLSAB1and BLSAB2and the sub word-line driver regions SWB. The conjunction regions CONJ are also disposed at each corner of the sub-array block SCB inFIG.13. A plurality of voltage generators (VG)s510,520,530and540may be disposed in the conjunction regions CONJ. It is to be appreciated that the locations of the bit-line sense amplifiers560,563and the conjunction regions CONJ shown inFIG.13are merely illustrative, and that other arrangements are similarly contemplated in accordance with embodiments of the inventive concept.

FIG.14illustrates a portion of the semiconductor memory device200ofFIG.5for explaining a write operation of a normal mode, according to one or more embodiments.

InFIG.14, the control logic circuit210, the first bank array310a, the I/O gating circuit290and the on-die ECC engine400are illustrated.

Referring toFIG.14, the first bank array310aincludes a normal cell region NCA and a redundancy cell region RCA.

The normal cell region NCA includes a plurality of first memory blocks MB0˜MB15, i.e.,311˜313, and the redundancy cell region RCA includes at least a second memory block314. The first memory blocks311˜313may be memory blocks that determine or are used to determine a memory capacity of the semiconductor memory device200. The second memory block314may be configured for ECC and/or redundancy repair. Since the second memory block314for ECC and/or redundancy repair is used for ECC, data line repair and block repair to repair “failed” cells generated in the first memory blocks311˜313, the second memory block314is also referred to as an EDB block. Each of the first memory blocks311˜313includes memory cells coupled to a word-line WL and bit-lines BTL and the second memory block314includes memory cells coupled to word-line WL and redundancy bit-lines RBTL. The redundancy cell region RCA may be referred to as a parity cell region.

The I/O gating circuit290includes a plurality of switching circuits291a˜291drespectively connected to the first memory blocks311˜313and the second memory block314. Each of at least a subset of the switching circuits291a˜291dmay be implemented using a multiplexer (MUX), as shown.

The on-die ECC engine400may be connected to the switching circuits291a˜291dthrough first data lines GIO and second data lines EDBIO. The control logic circuit210may receive the command CMD and the address ADDR and may decode the command CMD to generate the first control signal CTL1for controlling the switching circuits291a˜291dand the second control signal CTL2for controlling the on-die ECC engine400. In addition, the control logic circuit210may provide the random binary code RBC to the on-die ECC engine400.

When the command CMD is a write command, the control logic circuit210provides the second control signal CTL2to the on-die ECC engine400. The on-die ECC engine400generates the second main data MD2by scrambling the first main data MD1with the random binary code RBC in response to the second control signal CTL2, generates the parity data PRT by performing an ECC encoding on the second main data MD2and provides the I/O gating circuit290with the codeword CW including the second main data MD2and the parity data PRT.

The control logic circuit210provides the first control signal CTL1to the I/O gating circuit290such that the codeword CW is to be stored in a sub-page of the target page in the first bank array310a.

FIG.15illustrates a portion of the semiconductor memory device200ofFIG.5for explaining a read operation. Description repeated withFIG.14will be omitted.

Referring toFIG.15, when the command CMD is a read command to designate a read operation, the control logic circuit210provides the first control signal CTL1to the I/O gating circuit290such that a (read) codeword RCW, which includes the second main data MD2and the parity data PRT, stored in the sub-page of the target page in the first bank array310ais provided to the on-die ECC engine400.

The on-die ECC engine400performs an ECC decoding on the second main data MD2based on the parity data PRT in parallel with generating the first main data MD1by scrambling the second main data MD2with the random binary code RBC, and corrects at least one error bit (if present) in the first main data MD1to output the corrected main data C_MD1.

FIG.16illustrates that the semiconductor memory device ofFIG.5performs a write operation.

Referring toFIGS.5,7,11and16, when the command CMD is a write command, the first data scrambler410generates the second main data MD2by scrambling the first main data MD1with the random binary code RBC, the parity generator441generates the parity data PRT by performing an ECC encoding on the second main data MD2, as a reference numeral581indicates, and the I/O gating circuit290stores the second main data MD2and the parity data PRT in a target page TPG of the first bank array310a, as a reference numeral583indicates. For example, each of the first main data MD1and the second main data MD2may include 256-bit data bits and the parity data PRT may include 16-bit parity bits.

FIG.17illustrates at least a portion of an exemplary write operation performed by the semiconductor memory device200ofFIG.5, according to one or more embodiments.

Referring toFIGS.3,7and17, when the command CMD is a write command, the encoding/decoding logic440receives the codeword RCW, which may include the second main data MD2and the parity data PRT read from the target page TPG of the first bank array310aas a reference numeral591indicates, generates the first main data MD1by scrambling (e.g., using the second data scrambler430) the second main data MD2with the random binary code RBC in parallel with generating the syndrome SDR by performing an ECC decoding on the second main data MD2based on the parity data PRT and by providing the syndrome SDR to the data corrector470, as a reference numeral592indicates, and provides the first main data MD1to the data corrector470. For example, the syndrome SDR may include 16-bit of syndrome bits.

The data corrector470corrects at least one error bit in the first main data MD1(if present) based on the syndrome to output the corrected main data C_MD1.

FIG.18is a block diagram illustrating at least a portion of an example of a memory system20a, according to example embodiments.

Referring toFIG.18, the memory system20amay include a memory controller100aand a semiconductor memory device200a.

The memory controller100atransmits a command CMD, and an address (signal) ADDR to the semiconductor memory device200aand exchanges a main data MD with the semiconductor memory device200a.

The memory controller100amay include a CPU110and an ECC engine130.

The CPU110may control overall operation of the memory controller100and may generate the main data without scrambling user data.

The ECC engine130may correct error bits in the main data MD received from the semiconductor memory device200a.

The semiconductor memory device200aincludes a memory cell array310that stores a scrambled main data corresponding to the main data MD, an on-die ECC engine400aand a control logic circuit210. The memory cell array310may include a plurality of sub-array blocks arranged in a first direction and a second direction, the second direction intersecting with the first direction (e.g., the second direction may be orthogonal to the first direction); for example, consistent with the illustrative arrangement of the first bank array310ashown inFIG.6.

The on-die ECC engine400a, during a write operation, may generate the scrambled main data by scrambling the main data MD with a random binary code received from the control logic circuit210, may perform an ECC encoding on the scrambled main data to generate a parity data and may store the scrambled main data and the parity data in a target page in the memory cell array310.

The on-die ECC engine400a, during a read operation, may read the scrambled main data and the parity data from the target page, perform an ECC decoding on the scrambled main data based on the parity data to generate a syndrome in parallel with generating the main data MD by scrambling the scrambled main data with random binary code, may correct at least one error bit in the main data MD based on the syndrome and may transmit the corrected main data to the memory controller100a.

Each of the main data MD and the scrambled main data may include a plurality of data bits, and the plurality of data bits may be divided into a plurality of sub-data units. The main data MD may include a plurality of first sub-data units and the scrambled main data may include a plurality of second sub-data units.

FIG.19is a block diagram illustrating an example of the on-die ECC engine400ain the memory system ofFIG.18, according to example embodiments.

Referring toFIG.19, the on-die ECC engine400amay include a first data scrambler410a, a write FIFO register420a, a second data scrambler430a, a read FIFO register425a, a multiplexer427, an encoding/decoding logic440a, a data corrector470a, and a buffer circuit490.

The buffer circuit490may include buffers491,492,493and494. The buffers491,492,493and494may be controlled by a buffer control signal BCTL. The buffers491,492,493,494may be inverting or non-inverting buffers.

The first data scrambler410amay generate a scrambled main data SMD by scrambling (i.e., encoding) the main data MD with the random binary code RBC during the write operation and may store the scrambled main data SMD in the write FIFO register420a. The scrambled main data SMD stored in the write FIFO register420amay be stored in the target page of the memory cell array310(seeFIG.18) through the buffer491.

The multiplexer427may provide the encoding/decoding logic440awith the second main data output MD2from the first data scrambler410aduring the write operation and may provide the encoding/decoding logic440awith the scrambled main data SMD read from the target page through the buffer492, in response to a selection signal SS1.

The second data scrambler430amay receive the scrambled main data SMD from the buffer492, may generate the main data MD by scrambling (i.e., encoding) the scrambled main data SMD with the random binary code RBC, during the read operation, and may provide the main data MD for storage in the read FIFO register425a. The read FIFO register425amay provide the main data MD to the data corrector470a.

The encoding/decoding logic440a, during the write operation, may receive the scrambled main data SMD from the multiplexer427, may generate a parity data PRT1by performing an ECC encoding on the scrambled main data SMD, and may provide the parity data PRT1to the target page of the memory cell array310(seeFIG.18) through the buffer493. The encoding/decoding logic440a, during the read operation, may receive the scrambled main data SMD from the multiplexer427, may receive the parity data PRT1from the buffer494, may generate a syndrome SDR1by performing an ECC decoding on the scrambled main data SMD and the parity data PRT1, and may provide the syndrome SDR1to the data corrector470a.

During the read operation, the encoding/decoding logic440amay generate the syndrome SDR1by performing the ECC decoding on the scrambled main data SMD and the parity data PRT1and may provide the syndrome SDR1to the data corrector470ain parallel with the second data scrambler430agenerating the main data MD by scrambling the scrambled main data SMD with the random binary code RBC, and providing the main data MD for storage in the read FIFO register425a.

The data corrector470a, during the read operation, may receive the main data MD from the read FIFO register425aand may output a corrected data C_MD by correcting at least one error bit in the main data MD (if present) based on the syndrome SDR1.

FIG.20is a circuit diagram illustrating an example of the second data scrambler430ain the on-die ECC engine440aofFIG.19, according to example embodiments.

Referring toFIG.20, the second data scrambler430amay include a plurality of XOR gates431a,432a,433a,434a,435a,436a,437aand438a. Each of the plurality of XOR gates431a,432a,433a,434a,435a,436a,437aand438amay generate each of first data bits DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, DQ7and DQ8, respectively, of each of the first sub-data units of the main data MD by performing an XOR operation on respective one of second data bits SDQ1, SDQ2, SDQ3, SDQ4, SDQ5, SDQ6, SDQ7and SDQ8of each of the second sub-data units and a corresponding code bit of the plurality of code bits CB1, CB2, . . . , CBt of the random binary code RBC.

When the corresponding code bit of the plurality of code bits CB1, CB2, . . . , CBt has a first logic level, a corresponding one of the second data bits SDQ1, SDQ2, SDQ3, SDQ4, SDQ5, SDQ6, SDQ7and SDQ8is inverted and is provided as a corresponding one of the first data bits DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, DQ7and DQ8. When the corresponding code bit of the plurality of code bits CB1, CB2, . . . , CBt has a second logic level, a corresponding one of the second data bits SDQ1, SDQ2, SDQ3, SDQ4, SDQ5, SDQ6, SDQ7and SDQ8is maintained (i.e., is non-inverted) and is provided as a corresponding one of the first data bits DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, DQ7and DQ8.

Each of the second sub-data units of the scrambled main data SMD may be stored in a same sub-array block from among the plurality of sub-array blocks in the memory cell array310(seeFIG.18). Therefore, a same code bit (for example, the code bit CB1) may be applied to the first data bits DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, DQ7and DQ8of the first sub-data unit and to the second data bits SDQ1, SDQ2, SDQ3, SDQ4, SDQ5, SDQ6, SDQ7and SDQ8of the second sub-data unit.

FIG.21illustrates an example of the encoding/decoding logic440ain the on-die ECC engine400aofFIG.19, according to example embodiments.

Referring toFIG.21, the encoding/decoding logic440amay include a parity generator441a, a check bit generator443a, a syndrome generator450aand a memory445. The memory445may store a first ECC (ECC1)447.

The parity generator441amay be connected to the memory445and may generate the parity data PRT1based on the scrambled main data SMD using an array of exclusive OR gates.

The check bit generator443amay be connected to the memory445and may generate check bits CHB1based on the scrambled main data SMD using the first ECC447during the read operation.

The syndrome generator450amay generate the syndrome data SDR1based on the check bits CHB1, which is based on the scrambled main data SMD and the parity data PRT1from the buffer494(seeFIG.19) during the read operation. The syndrome generator450amay generate the syndrome SDR1based on whether each of the check bits CHB1matches a corresponding one of the bits of the parity data PRT1.

The syndrome SDR1may include a plurality of syndrome bits and each of the plurality of syndrome bits may indicate whether each of the check bits CHB1matches a corresponding one of the bits of the parity data PRT1. Therefore, the syndrome SDR1may indicate a position of the error bit and a number of the error bit.

FIG.22illustrates an example of the data corrector470ain the on-die ECC engine400aofFIG.19, according to example embodiments.

Referring toFIG.22, the data corrector470amay include a syndrome decoder471a, a bit inverter473a, which may be implemented using an XOR gate, and a selection circuit475a, which may be implemented by a multiplexer.

The syndrome decoder471amay decode the syndrome SDR1to generate a decoding signal DS1and a second selection signal SS2. The decoding signal DS1may indicate a position of the at least one error bit and the second selection signal SS2may have a logic level depending on a number of the at least one error bit. The bit inverter473amay invert the at least one error bit in response to the decoding signal DS1. The selection circuit475amay select one of the main data MD and an output of the bit inverter473ato provide the corrected main data C_MD in response to the second selection signal SS2.

FIG.23is a flow chart illustrating at least a portion of an example method of operating a semiconductor memory device, according to example embodiments.

Referring toFIGS.1through17and23, in a method of operating a semiconductor memory device200that includes a memory cell array310, an on-die ECC engine400and a control logic circuit210, the semiconductor memory device200may receive a write command and a first main data MD1from a memory controller100(operation S110).

A first data scrambler410in the on-die ECC engine400may generate a second main data MD2by scrambling (i.e., encoding) the first main data MD1based on a random binary code RBC (operation S120).

An encoding/decoding logic440in the on-die ECC engine400may generate a parity data PRT by performing an ECC encoding on the second main data MD2(operation S130).

An I/O gating circuit290may store the second main data MD2and the parity data PRT in a target page of the memory cell array310(operation S140).

The on-die ECC engine400may read the second main data MD2and the parity data PRT from the target page of the memory cell array310in response to a read command from the memory controller100(operation S150).

The encoding/decoding logic440in the on-die ECC engine400generates the first main data MD1by scrambling the second main data MD2with the random binary code RBC in parallel with generating a syndrome SDR by performing an ECC decoding on the second main data MD2based on the parity data PRT (operation S160).

A data corrector470in the on-die ECC engine400corrects at least one error bit in the first main data MD1based on the syndrome SDR (operation S170).

The data I/O buffer295transmits the corrected first main data C_MD1to the memory controller100(operation S180).

Therefore, in the semiconductor memory device and the method of operating the semiconductor memory device, the on-die ECC engine may generate the first main data by scrambling the second main data with the random binary code in parallel with generating a syndrome by performing an ECC decoding on the second main data read from the memory cell array and may correct at least one error bit in the first main data based on the syndrome. Because the on-die ECC engine does not perform data scrambling after performing the ECC decoding, the data scrambling does not need extra time. Therefore, the on-die ECC engine may reduce latency associated with the read operation while reducing pattern noise that occurs when fixed data patterns are repeated and may reduce a size of logic associated with the data scrambling.

FIG.24is a block diagram illustrating at least a portion of an example of memory module600, according to example embodiments.

Referring toFIG.24, the memory module600includes a register clock driver (RCD)690disposed (or mounted) in a circuit board601, a plurality of semiconductor memory devices201a˜201e,202a˜202e,203a˜203e, and204a˜204e, a plurality of data buffers641645and651655, module resistance units660and670, a serial presence detection (SPD) chip680, and a power management integrated circuit (PMIC)685.

By way of example only and without limitation, the circuit board601which is a printed circuit board may extend in a first direction D1, perpendicular to a second direction D2, between a first edge portion (e.g., right side)603and a second edge portion (e.g., left side)605. The first edge portion603and the second edge portion605may extend in the second direction D2.

The RCD690may be disposed on a center of the circuit board601. The plurality of semiconductor memory devices201a˜201e,202a˜202e,203a˜203e, and204a˜204emay be arranged in a plurality of rows between the RCD690and the first edge portion603and between the RCD690and the second edge portion605.

In this case, the semiconductor memory devices201a˜201eand202a˜202emay be arranged along a plurality of rows between the RCD690and the first edge portion603. The semiconductor memory devices203a˜203e, and204a˜204emay be arranged along a plurality of rows between the RCD690and the second edge portion605. A portion of the semiconductor memory devices201a˜201eand202a˜202emay be an ECC memory device. The ECC memory device may perform an ECC encoding operation to generate parity bits about data to be written at memory cells of the plurality of semiconductor memory devices201a˜201e,202a˜202e,203a˜203e, and204a˜204e, and an ECC decoding operation to correct an error that may be present in the data read from the memory cells.

Each of the plurality of semiconductor memory devices201a˜201e,202a˜202e,203a˜203e, and204a˜204emay be coupled to a corresponding one of the data buffers641645and651655through a data transmission line for receiving/transmitting a first main data MD1.

Each of the plurality of semiconductor memory devices201a˜201e,202a˜202e,203a˜203e, and204a˜204emay employ the semiconductor memory device200ofFIG.5. Therefore, each of the plurality of semiconductor memory devices201a˜201e,202a˜202e,203a˜203e, and204a˜204eincludes a memory cell array, a control logic circuit and an on-die ECC engine. The on-die ECC engine may include a first data scrambler and a second data scrambler.

The RCD690may provide a command/address signal (e.g., CA) to the semiconductor memory devices201a˜201ethrough a command/address transmission line661and may provide a command/address signal to the semiconductor memory devices202a˜202ethrough a command/address transmission line663. In addition, the RCD690may provide a command/address signal to the semiconductor memory devices203a˜203ethrough a command/address transmission line671and may provide a command/address signal to the semiconductor memory devices204a˜204ethrough a command/address transmission line673.

The command/address transmission lines661and663may be connected in common to the module resistance unit660adjacent to the first edge portion603, and the command/address transmission lines671and673may be connected in common to the module resistance unit670adjacent to the second edge portion605. Each of the module resistance units660and670may include a termination resistor Rtt/2 connected to a termination voltage Vtt. In this case, an arrangement of the module resistance units660and670may reduce the number of the module resistance units, thus reducing an area where termination resistors are disposed.

The SPD chip680may be adjacent to the RCD690and the PMIC685may be disposed between the semiconductor memory device203eand the second edge portion605. The PMIC685may generate a power supply voltage VDD based on the input voltage VIN and may provide the power supply voltage VDD to the semiconductor memory devices201a˜201e,202a˜202e,203a˜203e, and204a˜204e.

The SPD chip680may be a programmable read only memory (e.g., EEPROM). The SPD chip680may include device information DI of the memory module600. In example embodiments, the SPD chip680may include the device information DI, which may comprise information relating to, for example, a module form, a module configuration, a storage capacity, a module type, an execution environment, or the like of the memory module600.

When a memory system including the memory module600is booted up, a host may read the device information DI from the SPD chip680and may recognize the memory module600based on the device information DI. The host may control the memory module600based on the device information DI from the SPD chip680. For example, the host may recognize a type of the semiconductor memory devices201a˜201e,202a˜202e,203a˜203e, and204a˜204eincluded in the memory module600based on the device information DI from the SPD chip680.

In example embodiments, the SPD chip680may communicate with the host through a serial bus. For example, the host may exchange a signal with the SPD chip680through the serial bus. The SPD chip680may also communicate with the RCD690through the serial bus.

FIG.25is a block diagram illustrating at least a portion of an example semiconductor memory device800, according to example embodiments.

Referring toFIG.25, the semiconductor memory device800may include at least one buffer die810and a plurality of memory dies820-1to820-pproviding a soft error analyzing and correcting function in a stacked chip structure. Here, p is an integer greater than three. It is to be appreciated that embodiments of the inventive concept are not limited to any specific number of memory dies in the semiconductor memory device800.

The plurality of memory dies820-1to820-pmay be stacked on the at least one buffer die810and convey data through a plurality of through silicon via (TSV) lines.

Each of the memory dies820-1to820-pmay include a cell core821including a plurality of memory cells, a cell core ECC engine824which generates transmission parity data based on transmission data to be sent to the at least one buffer die810, and a control logic circuit (CLC)823. The cell core ECC engine824may employ the on-die ECC engine400ofFIG.7. The control logic circuit823may include a mode register in which a random binary code is set.

The at least one buffer die810may include a via ECC engine812which may be configured to correct a transmission error using the transmission parity data when a transmission error is detected from the transmission data received through the TSV lines and generates error-corrected data.

The semiconductor memory device800may be a stack chip type memory device or a stacked memory device which conveys data and control signals through the TSV lines. The TSV lines may be also called ‘through electrodes’.

A data TSV line group832, which may be formed at one memory die820-p, may include TSV lines L1, L2to Lp, and a parity TSV line group834may include TSV lines L10to Lq.

The TSV lines L1, L2to Lp of the data TSV line group832and the parity TSV lines L10to Lq of the parity TSV line group834may be connected to micro bumps MCB which are correspondingly formed among the memory dies820-1to820-p.

Each of the memory dies820-1to820-pmay include DRAM cells each including at least one access transistor and one storage capacitor.

The semiconductor memory device800may have a three-dimensional (3D) chip structure or a 2.5D chip structure to communicate with an external memory controller through a data bus B10. The at least one buffer die810may be connected with the memory controller through the data bus B10.

The via ECC engine812may be configured to determine whether a transmission error occurs at the transmission data received through the data TSV line group832, based on the transmission parity data received through the parity TSV line group834. When a transmission error is detected, the via ECC engine812may correct the transmission error on the transmission data using the transmission parity data. When the transmission error is uncorrectable, the via ECC engine812may output information (e.g., an error flag or other notification) indicating the occurrence of an uncorrectable data error.

FIG.26is a diagram illustrating at least a portion of an example semiconductor package900including the stacked memory device, according to example embodiments.

Referring toFIG.26, the semiconductor package900may include one or more stacked memory devices910and a graphic processing unit (GPU)920. The GPU920may include a memory controller (CONT)925.

The stacked memory devices910and the GPU920may be mounted on an interposer930, and the interposer on which the stacked memory devices910and the GPU920are mounted may be mounted on a package substrate940. The package substrate940may be mounted on solder balls950. The memory controller925may employ the illustrative memory controller100shown inFIG.1.

Each of the stacked memory devices910may be implemented in various forms, and may be a memory device in a high bandwidth memory (HBM) form in which a plurality of layers are stacked. Accordingly, each of the stacked memory devices910may include at least one buffer die and a plurality of memory dies. Each of the memory dies may include a memory cell array, an on-die ECC engine and a control logic circuit.

The plurality of stacked memory devices910may be mounted on the interposer930, and the GPU920may communicate with the plurality of stacked memory devices910. For example, each of the stacked memory devices910and the GPU920may include a physical region, and communication may be performed between the stacked memory devices910and the GPU920through the physical regions.

As mentioned above, according to example embodiments, the semiconductor memory device may generate the first main data by scrambling the second main data with the random binary code in parallel with generating a syndrome by performing an ECC decoding on the second main data read from the memory cell array and may correct at least one error bit in the first main data based on the syndrome. Because the semiconductor memory device, in one or more embodiments, does not perform data scrambling after performing the ECC decoding, the data scrambling does not need extra time. Therefore, the semiconductor memory device may reduce latency associated with a read operation while reducing pattern noise that occurs when fixed data patterns are repeated and may also reduce a size of logic associated with the data scrambling.

Aspects of the present disclosure may be applied to systems using semiconductor memory devices that employ an on-die ECC engine and a plurality of volatile memory cells. For example, aspects of the present disclosure may be applied to systems such as a smart phone, a navigation system, a notebook computer, a desk top computer and a game console that use the semiconductor memory device as a working memory.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and/or groups thereof. Spatially descriptive terms such as “above,” “below,” “upper” and “lower” may be used herein to indicate a position of elements, structures or features relative to one another as illustrated in the figures, rather than absolute positioning. Thus, the semiconductor device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and the spatially relative descriptions used herein may be interpreted accordingly.

It will also be understood that when an element such as a layer, region or substrate is referred to as being “atop,” “above,” “on” or “over” another element, it is broadly intended that the element be in direct contact with the other element or intervening elements can also be present. In contrast, when an element is referred to as being “directly on” or “directly over” another element, it is intended that there are no intervening elements present. Likewise, it should be appreciated that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements can be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.