Nano vacuum tube

A semiconductor device includes a tube-like structure comprising a plurality of dielectric layers and conductor layers that are disposed on top of one another; a conductor tip integrally formed with a cap conductor layer that is disposed on a top surface of the tube-like structure, wherein the conductor tip extends to a central hole of the tube-like structure; and at least one photodetector formed within a bottom portion of the tube-like structure.

BACKGROUND

Integrated circuits (IC's) typically include a large number of components, for example, transistors, resistors, capacitors, interconnection lines, etc. In accordance with each generation of technology nodes, each component of the IC may be formed as a respective structure on a chip (e.g., planer MOSFET's and FinFETs). In other words, each IC may have a respective surface configuration defined by its respective components. In general, a scanning electron microscopy (SEM) and an atomic force microscopy (AFM) are used to provide respective surface configurations of the plural components of the IC (i.e., a surface topography of the IC) so as to examine whether each of the components is properly fabricated during each of various fabrication stages.

The AFM typically relies on repulsive forces between a specimen substrate and an AFM probe tip to detect surface variations over the specimen substrate so as to reconstruct a respective topography of the specimen substrate using the surface variations. On the other hand, the SEM typically uses an electron beam to scan across a specimen substrate and one or more detectors to collect intensity variations of electrons scattered back from the specimen substrate so as to reconstruct a respective topography of the specimen substrate using the intensity variations of scattered-back electrons.

However, as the technology nodes continue to decrease in size, the SEM and AFM may each encounter various issues such as, for example, the AFM's low throughput (due to a limited number of AFM probe tips), possibilities to damage a specimen (due to the necessary contact of the AFM probe tip with the specimen), and the SEM's low throughput (due to a limited number of electron beams). Thus, conventional techniques to provide an IC's surface topography are not entirely satisfactory.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

The present disclosure provides various embodiments of a semiconductor device that can be used to reconstruct a surface topography of an integrated circuit (IC). Further, the disclosed semiconductor device can be made by complementary metal oxide semiconductor (CMOS)-compatible fabrication techniques, which allows a plurality of such semiconductor devices to be formed as an array such that the low throughput issue that the above-mentioned conventional techniques are facing can be advantageously avoided. In some embodiments, the disclosed semiconductor device includes a conductor tip formed within a tube, and plural photodetectors formed around a bottom surface of the tube. More particularly, in some embodiments, the conductor tip is configured to emit a plurality of electrons onto a specimen's surface (e.g., a fully or partially fabricated IC's surface), and the plural photodetectors are each configured to collect corresponding second electrons that are back scattered from the surface along some respective directions. As such, a relatively accurate surface topography of the specimen may be reconstructed using the disclosed semiconductor device.

FIGS. 1A-1Cillustrate a flowchart of a method100to form a semiconductor device according to one or more embodiments of the present disclosure. It is noted that the method100is merely an example, and is not intended to limit the present disclosure. In some embodiments, the semiconductor device is, at least part of, a topography reconstruction device. As employed by the present disclosure, the topography reconstruction device refers to any device/circuit/equipment that can provide a functionality of reconstructing a topography of a specimen. It is noted that the method ofFIG. 1does not produce a completed topography reconstruction device. A completed topography reconstruction device may be fabricated using complementary metal-oxide-semiconductor (CMOS) technology processing. Accordingly, it is understood that additional operations may be provided before, during, and after the method100ofFIGS. 1A-1C, and that some other operations may only be briefly described herein.

Referring toFIG. 1A, in some embodiments, the method100starts with operation102in which a semiconductor substrate overlaid by a first sacrificial layer is provided. The method100continues to operation104in which a semiconductor layer is formed over the first sacrificial layer. The method100continues to operation106in which a lower portion of the semiconductor layer is doped with a first type of dopant. The method100continues to operation108in which an upper portion of the semiconductor layer is doped with a second type of dopant. In some embodiments, the first type has an opposite polarity to the second type, e.g., a p-type and an n-type. Further, in some embodiments, the upper portion is in contact with the lower portion such that a p-n junction is formed in the semiconductor layer. The method100continues to operation110in which plural photodetectors are formed on the first sacrificial layer. In some embodiments, the plural photodetectors are formed by patterning the semiconductor layer such that each photodetector is formed as a p-n junction diode that respectively includes part of the lower portion of the semiconductor layer and part of the upper portion of the semiconductor layer. Further, in some embodiments, the plural photodetectors are formed as a ring-like structure when viewed from the top. The method100continues to operation112in which a bottom dielectric layer is formed over the plural photodetectors. In some embodiments, the bottom dielectric layer may be further planarized by a polishing process (e.g., a chemical mechanical polishing (CMP) process). The method100continues to operation114in which a bottom conductor layer is formed over the bottom dielectric layer.

Referring toFIG. 1B, the method100continues to operation116in which one or more pairs of an intermediate dielectric layer and an intermediate conductor layer are formed over the bottom conductor layer. More specifically, in some embodiments, a respective intermediate dielectric layer of a first pair is formed over the bottom conductor layer and a respective intermediate conductor layer of the first pair is formed over the respective intermediate dielectric layer of the first pair and so on. Such one or more pairs of intermediate dielectric and conductor layers are disposed on top of one another. The method100continues to operation118in which a top dielectric layer is formed over a top one of the one or more intermediate conductor layer and a top conductor layer is formed over the top dielectric layer. The method100continues to operation120in which a shallow trench is formed to extend through the top conductor layer. The method100continues to operation122in which a deep trench is formed to extend through the one or more pairs of intermediate conductor and dielectric layers, the bottom conductor layer, and the bottom dielectric layer. In some embodiments, the deep trench further extends downwardly from a central portion of the shallow trench so as to expose a top surface of the first sacrificial layer. The method100continues to operation124in which a second sacrificial layer is deposited to refill the deep and shallow trenches so as to form a concave cusp on a top surface of the second sacrificial layer. In some embodiments, the second sacrificial layer is formed of a substantially similar material as the first sacrificial layer such that in operation124, the first and second sacrificial layers may be integrally formed as a one-piece structure. The method100continues to operation126in which the top surface of the second sacrificial layer, at least part of, is recessed to further extend the concave cusp downwardly.

Referring toFIG. 1C, the method100continues to operation128in which a cap conductor layer is deposited to refill the concave cusp so as to form a conductor tip in the concave cusp. The method100continues to operation130in which the semiconductor substrate is removed. The method100continues to operation132in which the first and second sacrificial layers are removed. In some embodiments, after the first and second sacrificial layers are removed, the deep trench and at least part of the shallow trench are exposed such that the conductor tip is exposed within the deep trench.

In some embodiments, operations of the method100may be associated with cross-sectional views of a semiconductor device200at various fabrication stages as shown inFIGS. 2A, 2B, 2C, 2D, 2E, 2F, 2G, 2H, 21, 2J, 2K, 2L, 2M, 2N, 2O, and 2P, respectively. In some embodiments, the semiconductor device200may be a topography reconstruction device. The semiconductor device200may be included in a microprocessor, memory cell, and/or other integrated circuit (IC). Also,FIGS. 2A through 2Pare simplified for a better understanding of the concepts of the present disclosure. For example, although the figures illustrate the topography reconstruction device200, it is understood the IC may comprise a number of other devices comprising resistors, capacitors, inductors, fuses, etc., which are not shown inFIGS. 2A through 2P, for purposes of clarity of illustration.

Corresponding to operation102ofFIG. 1A,FIG. 2Ais a cross-sectional view of the topography reconstruction device200including a substrate202overlaid by a first sacrificial layer204at one of the various stages of fabrication, according to some embodiments. In some embodiments, the substrate202includes a silicon substrate. Alternatively, the substrate202may include other elementary semiconductor material such as, for example, germanium. The substrate202may also include a compound semiconductor such as silicon carbide, gallium arsenic, indium arsenide, and indium phosphide. The substrate202may include an alloy semiconductor such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, and gallium indium phosphide. In one embodiment, the substrate202includes an epitaxial layer. For example, the substrate may have an epitaxial layer overlying a bulk semiconductor. Furthermore, the substrate202may include a semiconductor-on-insulator (SOI) structure. For example, the substrate may include a buried oxide (BOX) layer formed by a process such as separation by implanted oxygen (SIMOX) or other suitable technique, such as wafer bonding and grinding.

In some embodiments, the first sacrificial layer204may be formed of silicon oxide. The first sacrificial layer204may be formed using one or more deposition techniques such as, for example, a chemical vapor deposition (CVD) technique, a physical vapor deposition (PVD) technique, an atomic layer deposition (ALD) technique, or other suitable technique. In some embodiments, the first sacrificial layer204may be used as a sacrificial/dummy layer that will be removed in a later process, which will be discussed in further detail below.

Corresponding to operation104ofFIG. 1A,FIG. 2Bis a cross-sectional view of the topography reconstruction device200including a semiconductor layer206formed over the first sacrificial layer204at one of the various stages of fabrication, according to some embodiments. In some embodiments, the semiconductor layer206is formed of crystalline silicon. Alternatively, the semiconductor layer1206may be formed of crystalline germanium, and/or III-V compound semiconductor materials (e.g., InAs, GaAs, GaN, InP, GaP, etc.). In some embodiments, the semiconductor layer206is formed using an epitaxial growth method, such as molecular beam epitaxy (MBE) or metalorganic vapor phase epitaxy (MOVPE). In some embodiments, the semiconductor layer206may be formed using one or more deposition techniques such as, for example, a CVD technique, a PVD technique, an ALD technique, or other suitable technique.

Corresponding to operation106ofFIG. 1A,FIG. 2Cis a cross-sectional view of the topography reconstruction device200including a lower portion208of the semiconductor layer206which is doped by a first doping process209at one of the various stages of fabrication, according to some embodiments. The first doping process209may include an ion implantation process that is generally used to incorporate a plurality of dopants into a semiconductor substrate. In the illustrated embodiment ofFIG. 2C, the plurality of dopants, implanted by the first doping process209, may include p-type dopants, e.g., boron, BF2, and/or a combination thereof, and such dopants are implanted into the lower portion208of the semiconductor layer206.

Corresponding to operation108ofFIG. 1A,FIG. 2Dis a cross-sectional view of the topography reconstruction device200including a higher portion210of the semiconductor layer206which is doped by a second doping process211at one of the various stages of fabrication, according to some embodiments. The second doping process211may also include the ion implantation process that incorporates a plurality of dopants into a semiconductor substrate. In the illustrated embodiment ofFIG. 2D, the plurality of dopants, implanted by the second doping process211, may include n-type dopants, e.g., phosphorus, arsenic, and/or a combination thereof, and such dopants are implanted into the higher portion210of the semiconductor layer206.

In some embodiments, the lower portion208and the higher portion210may be in direct contact with each other such that the lower and higher portions (208and210) may form a p-n junction in the semiconductor layer206. Although in the illustrated embodiments ofFIGS. 2C and 2D, the lower portion208is doped with p-type dopants and the higher portion210is doped with n-type dopants, it is understood that polarities of dopants (i.e., n- or p-type) implanted into the lower and upper portions (208and210), respectively, may be reversed while remaining within the scope of the present disclosure.

Corresponding to operation110ofFIG. 1A,FIG. 2Eis a cross-sectional view of the topography reconstruction device200including one or more photodetectors220which are formed at one of the various stages of fabrication, according to some embodiments. As shown, each of the one or more photodetectors220is formed by a portion of the lower portion208and a portion of the higher portion210. As such, the photodetector220may include a p-n junction diode. In some embodiments, the one or more photodetectors220may be formed as a ring-like structure when viewed from the top, which will be illustrated inFIG. 3. Thus, it can be understood that the cross-sectional view shown in the illustrated embodiment ofFIG. 2Eincludes two discrete photodetectors220spaced from each other.

In some embodiments, the one or more photodetectors220may be formed by at least some of the following process steps: forming a patterned mask layer over the semiconductor layer206(FIG. 2D) that includes a corresponding pattern (e.g., openings) aligned with respective positions of the to-be formed photodetectors220; performing one or more dry/wet etching processes to etch the semiconductor layer206using the patterned mask layer as a mask; and removing the patterned mask layer.

Corresponding to operation112ofFIG. 1A,FIG. 2Fis a cross-sectional view of the topography reconstruction device200including a bottom dielectric layer222overlaying the photodetectors220at one of the various stages of fabrication, according to some embodiments. The bottom dielectric layer222includes a material that is at least one of: a low dielectric constant (low-k) material, other suitable dielectric material, or a combination thereof.

The low-k material may include: silicon nitride (SiN), fluorinated silica glass (FSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), carbon doped silicon oxide (SiOxCy), Black Diamond® (Applied Materials of Santa Clara, Calif.), Xerogel, Aerogel, amorphous fluorinated carbon, Parylene, BCB (bis-benzocyclobutenes), SiLK (Dow Chemical, Midland, Mich.), polyimide, and/or other future developed low-k dielectric materials. Since the material of the bottom dielectric layer222will be used by other dielectric layers formed subsequently, for ease of discussion, the material is herein referred to as “material D.”

In some embodiments, the bottom dielectric layer222is formed over the photodetectors222and the first sacrificial layer204by using one or more deposition techniques such as, for example, a CVD technique, a PVD technique, an ALD technique, or other suitable technique. And in some embodiments, a polishing process (e.g., a CMP process) may be performed to planarize the bottom dielectric layer222.

Corresponding to operation114ofFIG. 1A,FIG. 2Gis a cross-sectional view of the topography reconstruction device200including a bottom conductor layer224overlaying the bottom dielectric layer222at one of the various stages of fabrication, according to some embodiments. In some embodiments, the bottom conductor layer224is formed of a metal material such as, for example, copper (Cu).

In some other embodiments, the bottom conductor layer224may include other suitable metal materials (e.g., gold (Au), cobalt (Co), silver (Ag), etc.) and/or conductive materials (e.g., polysilicon) while remaining within the scope of the present disclosure. Similarly, since the material of the bottom conductor layer224will be used by other conductive structures/layers formed subsequently, for ease of discussion, the material is herein referred to as “material M.” In some embodiments, the bottom conductor layer224may be formed by using a CVD technique, a PVD technique, a E-gun technique, a sputtering technique, and/or other suitable techniques to deposit the material M over the bottom dielectric layer222.

Corresponding to operation116ofFIG. 1B,FIG. 2His a cross-sectional view of the topography reconstruction device200including one or more pairs226of intermediate dielectric layer226-1and intermediate conductor layer226-2at one of the various stages of fabrication, according to some embodiments. In some embodiments, the intermediate dielectric layer226-1is formed of the “material D,” and the intermediate conductor layer226-2is formed of the “material M.” Although only one pair226of such intermediate layers are formed over the bottom conductor layer224, it is understood that additional pair(s), each substantially similar to the pair226(i.e., a lower layer is a dielectric layer226-1and an upper layer is a conductor layer226-2), can be formed over the first pair226.

In some embodiments, the intermediate dielectric layer226-1may be formed by using a CVD technique, a PVD technique, and/or other suitable techniques to deposit the material D over the bottom conductor layer224, and the intermediate conductor layer226-2may be subsequently formed by using a CVD technique, a PVD technique, a E-gun technique, a sputtering technique, and/or other suitable techniques to deposit the material M over the intermediate dielectric layer226-1. When there are more additional pairs of intermediate dielectric and conductor layers formed over the pair226, each of the additional pairs may be formed using the above-described approach.

Corresponding to operation118ofFIG. 1B,FIG. 2Iis a cross-sectional view of the topography reconstruction device200including a top dielectric layer228overlaying the pair226and a top conductor layer230overlaying the top dielectric layer228at one of the various stages of fabrication, according to some embodiments. In some embodiments, the top dielectric layer228is formed of the “material D,” and the top conductor layer230is formed of the “material M.” In some embodiments, the top dielectric layer228may be formed by using a CVD technique, a PVD technique, and/or other suitable techniques to deposit the material D over the pair226, and the top conductor layer230may be subsequently formed by using a CVD technique, a PVD technique, a E-gun technique, a sputtering technique, and/or other suitable techniques to deposit the material M over the top dielectric layer228.

Corresponding to operation120ofFIG. 1B,FIG. 2Jis a cross-sectional view of the topography reconstruction device200including a shallow trench231which is formed at one of the various stages of fabrication, according to some embodiments. As shown, the shallow trench231is formed in the top conductor layer230, and more specifically, the shallow trench231extends through the top conductor layer230. Accordingly, a portion of a top surface229of the top dielectric layer228may be exposed.

In some embodiments, the shallow trench231may, be formed by at least some of the following process steps: forming a patterned mask layer over the top conductor layer230(FIG. 2I) that includes a corresponding pattern (e.g., an opening) aligned with a respective position of the to-be formed shallow trench231; performing one or more dry/wet etching processes to etch the top conductor layer230using the patterned mask layer as a mask; and removing the patterned mask layer.

Corresponding to operation122ofFIG. 1B,FIG. 2Kis a cross-sectional view of the topography reconstruction device200including a deep trench233which is formed at one of the various stages of fabrication, according to some embodiments. As shown, the deep trench233is formed to further extend the shallow trench231downwardly, and more specifically, the deep trench233extends through the top dielectric layer228, the one or more pairs226, the bottom conductor layer224, and the bottom dielectric layer222. Accordingly, after the deep trench233is formed, respective sidewalls of the top dielectric layer228, the one or more pairs226, the bottom conductor layer224, and the bottom dielectric layer222, and a portion of a top surface205of the first sacrificial layer204may be respectively exposed.

Further, as shown inFIG. 2K, the deep trench233may be formed to be surrounded by the ring-like photodetectors220, in accordance with some embodiments. As such, in some embodiments, the deep trench233may be formed as hollow cylinder with a curvilinear cross-section (e.g., a circle).

In some embodiments, the deep trench233may be formed by at least some of the following process steps: forming a patterned mask layer over the top dielectric layer228and the top conductor layer230(FIG. 2J) that includes a corresponding pattern (e.g., an opening) aligned with a respective position of the to-be formed deep trench233; performing one or more dry/wet etching processes to, respectively or concurrently, etch the top dielectric layer228, the one or more pairs226, the bottom conductor layer224, and the bottom dielectric layer222using the patterned mask layer as a mask; and removing the patterned mask layer.

Corresponding to operation124ofFIG. 1B,FIG. 2Lis a cross-sectional view of the topography reconstruction device200including a second sacrificial layer234at one of the various stages of fabrication, according to some embodiments. As shown, the second sacrificial layer234is formed to refill the deep trench233and the shallow trench231, and overlay the top conductor layer230.

Due to a substantially high aspect ratio (a ratio of a depth233-2of the deep trench233to a width (or diameter)233-1of the deep trench233) of the deep trench233, when the deep trench233is refilled with the second sacrificial layer234, a concave cusp236may be formed at a central portion of a top surface235of the second sacrificial layer234, according to some embodiments. In some embodiments, the width233-1may range between about 10 nanometers (nm) to about 30 nm, and the depth233-2may range between about 40 nm to about 100 nm. Also, as mentioned above with respect toFIG. 2K, the deep trench233is formed as hollow cylinder with a curvilinear cross-section. As such, after the deep trench233is refilled by the second sacrificial layer234, a lower portion234′ of the second sacrificial layer234that is defined by the diameter233-1and the depth233-2may be formed as a cylinder-like structure with a curvilinear cross-section.

In some embodiments, the second sacrificial layer234may be formed of a material that is substantially similar to the material of the first sacrificial layer204, i.e., silicon oxide. As such, after the second sacrificial layer234is formed, the first and second sacrificial layers (204and234) may be integrally formed as a one-piece structure. In some embodiments, the second sacrificial layer234may be formed using one or more deposition techniques such as, for example, a CVD technique, a PVD technique, an ALD technique, or other suitable technique. In some embodiments, such a one-piece structure formed by the first and second sacrificial layers (204and234) may be used as a sacrificial/dummy layer that will be removed in a later process, which will be discussed in further detail below.

Corresponding to operation126ofFIG. 1B,FIG. 2Mis a cross-sectional view of the topography reconstruction device200including a further extended concave cusp236′ at one of the various stages of fabrication, according to some embodiments. In some embodiments, the further extended concave cusp236′, or simply the concave cusp236′, may be formed by performing one or more dry/wet etching process on the top surface235of the second sacrificial layer234. As such, the concave cusp236′ may further extend downwardly (i.e., toward the top surface205). In some embodiments, when the further extended cusp236′ is formed, a top surface231of the top conductor layer230may be exposed as well.

Corresponding to operation128ofFIG. 1C,FIG. 2Nis a cross-sectional view of the topography reconstruction device200including a cap conductor layer240which is formed at one of the various stages of fabrication, according to some embodiments. As shown, the cap conductor layer240is formed to overlay the top conductor layer230and the second sacrificial layer234, which allows the cap conductor layer240to refill the concave cusp236′. In other words, after the concave cusp236′ is refilled by, at least part of, the cap conductor layer240, a conductor tip241that is formed of the same material as the cap conductor layer240may be formed. In a further embodiment, since the cap conductor layer240is formed to have a substantially conformal thickness, another concave cusp243may be formed on a top surface240′ of the cap conductor layer240after the formation of the cap conductor layer240.

In some embodiments, the cap conductor layer240is formed of a different metal material than the “material M.” In some embodiments, the cap conductor layer240may be formed of a metal material that has at least some of the following characteristics: a low potential barrier, and a high melting point. In a non-limiting example, the cap conductor layer240may be formed of tungsten (W). In some embodiments, the cap conductor layer240may be formed by using a CVD technique, a PVD technique, a E-gun technique, a sputtering technique, and/or other suitable techniques to deposit the above-described metal material (e.g., W) over the top conductor layer230and the second sacrificial layer234.

Corresponding to operation130ofFIG. 1C,FIG. 2Ois a cross-sectional view of the topography reconstruction device200after the substrate202(shown in dotted line) is removed at one of the various stages of fabrication, according to some embodiments. In some embodiments, the substrate202may be removed by at least some of the following processes: rotating the topography reconstruction device200upside down; and performing a polishing process (e.g., a CMP process)251on the substrate202until a backside surface204′ of the first sacrificial layer204is exposed; and performing one or more cleaning processes.

Corresponding to operation132ofFIG. 1C,FIG. 2Pis a cross-sectional view of the topography reconstruction device200after the first and second sacrificial layers204and234(shown in dotted line) are concurrently removed at one of the various stages of fabrication, according to some embodiments. As mentioned above, in some embodiments, the first and second sacrificial layers204and234are formed of a same material (e.g., silicon oxide), in which case, the first and second sacrificial layers204and234are integrally formed as a one-piece structure. Accordingly, in some embodiments, such a one-piece structure (formed by the first and second sacrificial layers204and234) may be concurrently removed (e.g., selectively etched) using one or more acid solutions, for example, diluted hydrofluoric acid (HF), while remaining other layers/structures (e.g.,220,222,224,226,228,230,240, and241) intact.

In some embodiments, after the removal of the first and second sacrificial layers204and234, a hollow space252that was occupied by the second sacrificial layer234is formed. More specifically, as mentioned above with respect toFIG. 2L, the lower portion234-1of the second sacrificial layer234is formed of a cylinder-like structure such that a corresponding portion of the hollow space252may be formed as a hollow cylinder-like space, and, in some embodiments, the conductor tip241is formed within such a hollow cylinder-like space252(e.g., a central hole of the semiconductor device200). When viewed from the bottom, the conductor tip241may be surrounded by a tube that is at least formed by the bottom dielectric layer222, the bottom conductor layer224, the one or more pairs of intermediate dielectric and intermediate conductor layers226, the top dielectric layer228, and the top conductor layer230. Further, in some embodiments, the photodetectors220are formed as a ring-like structure in the bottom dielectric layer222, as mentioned above. As such, when viewed form the bottom, the photodetectors220, which are exposed at a respective bottom surface222′ of the tube, may surround the conductor tip241as a ring. For purposes of clarity, the above-described tube and the conductor tip241(which is part of the cap conductor layer240) are collectively referred to herein as the topography reconstruction device200.

FIG. 3illustrates some exemplary configurations300and310of the photodetectors220, when viewed from the top, in accordance with various embodiments. In the above discussions of the photodetectors220, in some embodiments, the photodetectors220may be formed as a ring-like structure. In300, the photodetectors220may be formed as a continuous ring-like structure, and in310, the photodetectors220may be each formed as a respective segment (e.g.,220-1,220-2,220-3,220-4, etc.) of a ring-like structure.

Although the illustrated embodiment310shows that each photodetector (i.e.,2201-1,220-2,220-3, and220-4) constitutes a quadrant of a respective ring-like structure, it is understood that the photodetectors220may be each formed as any shape of a circular sector (e.g., a sextant, an octant, etc.) of a respective ring-like structure while remaining within the scope of the present disclosure. In some embodiments, forming each of the photodetectors220as a discrete circular sector, as shown in310, may provide various advantages when using the topography reconstruction device200as part of a topography reconstruction circuit, which will be discussed in further detail below.

FIG. 4illustrates a block diagram of an exemplary topography reconstruction circuit400, in accordance with various embodiments. As shown, the topography reconstruction circuit400includes a substrate402having an array404of a plurality of topography reconstruction device200made by the above-discussed method (FIGS. 1A-1C), a voltage/current (VC) generation unit406, and a control unit410. Thus, for purposes of discussion, the following embodiment of the topography reconstruction circuit400will be described in conjunction with the method inFIGS. 1A-1C, and corresponding cross-sectional views of the topography reconstruction device200in2A-2P.

In some embodiments, each of the topography reconstruction device200of the array404is coupled to the VC generation unit406, and configured to receive a voltage signal and a current signal from the VC generation unit406. More specifically, the VC generation unit406is configured to provide a high voltage signal to the respective conductor tip241(through the cap conductor layer240) of each of the topography reconstruction device200, and provide a current signal to flow through the respective bottom conductor layer224and the one or more intermediate conductor layers226-2.

When such a high voltage signal is applied to the conductor tip241, due to the characteristics of W (tungsten) and other metal materials having similar characteristics as discussed above, one or more electrons (e.g.,421) may be emitted from the conductor tip241. Moreover, when the current signal flows through the bottom conductor layer224and the one or more intermediate conductor layers226-2. Such a multi-layer of conductors (i.e.,224, and plural226-2) may function as an electron aperture that can focus (i.e., guide) the electron421emitted from the conductor tip421, which allows the electron421to travel along a direction substantially perpendicular to a respective surface of a to-be examined specimen420(e.g., an IC). As such, once the topography reconstruction devices200are disposed at respective positions on the substrate402, an electron emitted from each topography reconstruction devices200can be well guided and won't interfere with electrons emitted from other topography reconstruction devices200.

In some embodiments, once the electrons421are emitted from respective topography reconstruction devices200, the electrons421may hit the top surface of the specimen420, and based on a respective topography of the specimen420, plural electrons423(typically referred to as “second electrons”) may be back-scattered from the specimen420. In some embodiments, such back-scatter electrons423can be collected by the respective photodetectors220of the topography reconstruction devices200. When each topography reconstruction devices200collects a respective portion of the back-scattered electrons423, the topography reconstruction device200may provide the respective portion of the electrons423to the control unit410as a respective input signal. In some embodiments, the control unit410may use one or more commercially available image processing tools, for example, Mountain Map from Digital Surf (Besancon, France), 3D GUI form Applied Materials (Santa Clara, Calif.) etc., to reconstruct a respective surface topography of the specimen420.

As mentioned above with respect to310ofFIG. 3, the photodetectors220of each topography reconstruction devices200may be formed as respective segments of a ring-like structure. When the photodetector220is formed as a discrete segment, each of the photodetectors220may individually collect a respective portion of the back-scattered electrons423, which may in turn increase a resolution of the reconstructed surface topography of the specimen420. Moreover, because of the individual collection of the back-scattered electrons423, a three-dimensional (3D) reconstructed surface topography of the specimen420may be enabled. For example, when the top surface of the specimen420has features formed at two respective levels, each of which is vertically spaced from each other (hereinafter a “lower level” and a “higher level”). As such, each discrete segment of the photodetector220may receive different portions of the back-scattered electrons423from the lower level and higher level, respectively. In particular, the portion of the back-scattered electrons423from the lower level may be detected by one of the discrete segments as a weaker signal, and the portion of the back-scattered electrons423from the higher level may be detected by the one of the discrete segments as a stronger signal. Since each discrete segment are laterally disposed in respective positions, each discrete segment may detect respective stronger and weaker signals, which enables a reconstruction on the 3D surface topography of the specimen420.

In an embodiment, a semiconductor device includes a tube-like structure comprising a plurality of dielectric layers and conductor layers that are disposed on top of one another; a conductor tip integrally formed with a cap conductor layer that is disposed on a top surface of the tube-like structure, wherein the conductor tip extends to a central hole of the tube-like structure; and at least one photodetector formed within a bottom portion of the tube-like structure.

In another embodiment, a method for forming a semiconductor device includes providing a substrate overlaid by a first sacrificial layer; forming one or more photodetectors in a bottom dielectric layer that is disposed over the first sacrificial layer; forming a shallow trench in a cap conductor layer that is disposed on a plurality of intermediate dielectric and conductor layers over the bottom dielectric layer; forming a deep trench coupled to the shallow trench, wherein the deep trench extends through the plurality of intermediate dielectric and conductor layers and the bottom dielectric layer; and refilling the shallow and deep trenches with a second sacrificial layer so as to form a concave cusp on a top surface of the second sacrificial layer.

Yet in another embodiment, a method of forming a semiconductor device includes: providing a substrate overlaid by a first sacrificial layer; forming a plurality of photodetectors in a bottom dielectric layer, wherein the bottom dielectric layer is disposed over the first sacrificial layer; forming a top conductor layer that is disposed on a plurality of intermediate dielectric and conductor layers over the bottom dielectric layer; forming a shallow trench in the top conductor layer; forming a deep trench coupled to the shallow trench, wherein the deep trench extends through the plurality of intermediate dielectric and conductor layers and the bottom dielectric layer; refilling the shallow and deep trenches with a second sacrificial layer so as to form a concave cusp on a top surface of the second sacrificial layer; etching the second sacrificial layer to further extend the concave cusp; refilling the concave cusp with a cap conductor layer so as to form a conductor tip in the concave cusp; removing the substrate; and removing the first and second sacrificial layers to expose the deep trench and part of the shallow trench so as to cause the conductor tip to be in the deep trench.