Image display apparatus and control method therefor

A display apparatus may include an input terminal configured to receive an analog video signal; a tuner configured to receive a broadcast signal; a rear multiplexer configured to multiplex at least two of the analog video signal and an output signal of the tuner; an analog digital converter configured to convert the output signal of the rear multiplexer into a digital signal; and a decoder configured to decode the digital signal. The tuner may include an analog broadcast tuner outputting an analog broadcast video signal and an analog broadcast audio signal; a broadcast tuner; a digital broadcast tuner outputting a digital broadcast signal; and a front multiplexer multiplexing at least two of the analog broadcast video signal and the analog broadcast audio signal and the digital broadcast signal.

TECHNICAL FIELD

Embodiments of the disclosure relate to an analog front end and a display apparatus, and more specifically, to an analog front end, a method of operating the analog front end, and a display apparatus including an analog front end input apparatus capable of processing various input signals and broadcast signals used in a digital television system.

BACKGROUND ART

In general, an image display apparatus is an apparatus capable of displaying image data of various formats by having a display panel.

The image display apparatus may receive content data from various content sources such as a broadcasting station, an Internet server, a video playback device, a game device, and/or a portable terminal. In addition, the image display apparatus may restore (or decode) an image frame from the content data and display the restored image frame on the display panel.

A cable connecting the image display apparatus and the content source is composed of a signal line and ground, and the content data is transmitted to the image display apparatus through the signal line. At this time, a signal level of the content source and a signal level of the image display apparatus may be different, and the difference between these signal levels is calibrated in a clamping circuit of an analog front end for processing the content source of the image display apparatus.

In addition, a broadcast signal is converted to an intermediate frequency signal (intermediate frequency signal, if) in the form of a differential signal (differential signal) by a tuner of the image display apparatus, the intermediate frequency signal is transmitted to the analog front end for differential signal processing.

In particular, a digital television among the image display apparatuses, unlike conventional televisions using analog signals, may receive video and audio using digital signals. In addition, since a digital television broadcast signal uses digitally compressed and modulated data, a user can watch a broadcast through a television receiver or set-top box designed for the digital television. These digital televisions have several advantages over the conventional televisions, and the most important of them is that a bandwidth occupied by the broadcasting channel can be reduced. In addition, the digital television is capable of multicasting (for example, simultaneously broadcasting a plurality of broadcast programs on one channel).

However, the number of content sources connected to the image display apparatus is increasing due to a variety of types of the content sources.

As a result, the number of the cables connecting each of the image display apparatus and the content sources and the number of connection terminals of the cables are increasing. In addition, the number of analog-to-digital converters that convert the analog signals from the cables into the digital signals is also increasing along with the increase in the number of the connection terminals of the cables.

DISCLOSURE

Technical Problem

One aspect of the disclosed embodiment is to provide a display apparatus capable of minimizing the number of analog-to-digital converters that convert analog signals from cables into digital signals.

Another aspect of the disclosed embodiment is to provide a display apparatus including an analog front end, an analog front end operation method, and the analog front end capable of simultaneously processing various input signals and broadcast signals input to the display apparatus.

Technical Solution

In accordance with an aspect of the disclosure, a display apparatus includes: an input terminal configured to receive an analog video signal; a tuner configured to receive a broadcast signal; a rear multiplexer configured to multiplex at least two of the analog video signal and an output signal of the tuner; an analog-digital converter configured to convert the output signal of the rear multiplexer into a digital signal; a decoder configured to decode the digital signal. The tuner may include an analog broadcast tuner outputting an analog broadcast video signal and an analog broadcast audio signal; a digital broadcast tuner outputting a digital broadcast signal; and a front multiplexer multiplexing at least two of the analog broadcast video signal, the analog broadcast audio signal and the digital broadcast signal.

The display apparatus may further include a clamping/biasing circuit configured to clamp or bias the output signal of the rear multiplexer, according to the analog video signal and the output signal of the tuner.

The clamping/biasing circuit may clamp or bias the output signal of the rear multiplexer according to the analog video signal or the output signal of the tuner when the analog video signal or the analog broadcast video signal is outputted from the rear multiplexer.

The clamping/biasing circuit may bias the output signal (the digital broadcast signal) of the rear multiplexer according to the output signal of the tuner when the digital broadcast signal is outputted from the rear multiplexer.

The front multiplexer may multiplex the analog broadcast video signal and the digital broadcast signal to output a front multiplexed signal, the analog-digital converter may convert the front multiplexed signal into a digital output signal, and the display apparatus may further comprise a digital clamping circuit configured to clamp the digital output signal of the analog-digital converter.

The analog-digital converter may convert the analog broadcast audio signal into a digital output signal, and the display apparatus may further comprise a variable gain amplifier configured to amplify the digital output signal of the analog-digital converter and a gain controller configured to control an amplification factor of the variable gain amplifier.

The tuner may further comprise a variable gain amplifier configured to amplify a digital output signal and a gain controller configured to control an amplification factor of the variable gain amplifier.

The front multiplexer may multiplex the analog broadcast video signal and the digital broadcast signal, and the tuner may further comprise a satellite broadcast tuner configured to output a satellite broadcast signal and another front multiplexer configured to multiplex the analog broadcast audio signal and the satellite broadcast signal.

The tuner may further comprise: a first frequency shifter configured to output a frequency shift audio signal by changing a frequency of the analog broadcast audio signal and a signal synthesizer configured to synthesize the frequency shifted audio signal and the analog broadcast video signal, and the front multiplexer may multiplex the output signal of the signal synthesizer and the digital broadcast signal.

The signal synthesizer may include: a first filter configured to extract the frequency shifted audio signal from the output signal of the signal synthesizer, a second frequency shifter configured to restore the analog broadcast audio signal by changing the frequency shifted audio signal, and a second filter configured to extract the analog broadcast video signal from the output signal of the signal synthesizer.

In accordance with an aspect of the disclosure, an analog front end includes: an analog-to-digital converter configured to convert differential analog signals to a digital code in response to a sampling clock signal, a fractional-N phase locked loop configured to a clock signal as an input signal, and a first selector configured to output one of the clock signal and the output clock signal of the fractional-N phase locked loop as the sampling clock signal in response to a first selection signal.

The analog front end may further comprise a demodulator configured to demodulate the digital code in response to the sampling clock signal.

The analog front end may further comprise a first frequency divider configured to divide a frequency of the output clock signal of the first selector at a first division ratio, a second frequency divider configured to divide a frequency of the clock signal of the first frequency divider at a second division ratio, and a second selector configured to output one of the output clock signal if the first selector and the output clock signal of the second frequency divider as the sampling signal in response to a second selection signal. An aspect of the disclosed embodiment is to provide a display apparatus enable to minimize the number of analog-to-digital converters configured to convert analog signals into digital signals.

In accordance with an aspect of the disclosure, a controlling method of a display apparatus may comprise: first multiplexing at least two of an analog broadcast video signal, an analog broadcast audio signal, and a digital broadcast signal received through a tuner; second multiplexing at least two of an analog video signal, and a first multiplexed signal received through an input terminal; converting a second multiplexing signal into a digital signal; and decoding the digital signal.

The method may further comprise clamping or biasing the second multiplexed signal according to the analog video signal or an output signal of the tuner.

The clamping or biasing the second multiplexed signal may include the clamping of the second multiplexed signal according to the analog video signal or the output signal of the tuner when the second multiplexed signal includes the analog video signal or the analog broadcast video signal.

The clamping or biasing the second multiplexed signal may include the biasing of the second multiplexed signal when the second multiplexed signal includes the digital broadcast signal.

The first multiplexing may include multiplexing the analog broadcast video signal and the digital broadcast signal, and the method may further comprise clamping the digital signal.

Advantageous Effects

Another aspect of the disclosed embodiment is to provide a display apparatus including an analog front end, an analog front end operation method, and the analog front end capable of simultaneously processing various input signals and broadcast signals input to the display apparatus.

BEST MODE

In the following description, like reference numerals refer to like elements throughout the specification. This specification does not describe all elements of the embodiments, and in the technical field to which the present invention pertains, there is no overlap between the general contents or the embodiments. Terms such as “unit,” “module,” “member,” and “block” may be embodied as hardware or software. According to embodiments, a plurality of “units,” “modules,” “members,” or “blocks” may be implemented as a single component or a single “unit,” “module,” “member,” or “block” may include a plurality of components.

In all specifications, it will be understood that when an element is referred to as being “connected” to another element, it can be directly or indirectly connected to the other element, wherein the indirect connection includes “connection via a wireless communication network.”

Throughout the specification, when one member is positioned “on” another member, this includes not only the case where one member abuts another member, but also the case where another member exists between the two members.

The terms first, second, etc. are used to distinguish one component from another component, and the component is not limited by the terms described above.

An expression used in the singular form encompasses the expression of the plural form, unless it has a clearly different meaning in the context.

The reference numerals used in operations are used for descriptive convenience and are not intended to describe the order of operations and the operations may be performed in a different order unless otherwise stated.

FIG. 1shows a display apparatus and a content source according to an embodiment.

As shown inFIG. 1, a display apparatus100may receive a video signal and an audio signal from various content sources1-5, and output video and audio corresponding to the video signal and the audio signal.

For example, the display apparatus100may receive television broadcast content from a broadcast receiving antenna1. The television broadcast content may include a video signal and an audio signal, and the broadcast receiving antenna1may receive the video signal and the audio signal transmitted wirelessly from a transmission tower. At this time, the video signal and the audio signal may be analog signals or digital signals.

For wireless communication (terrestrial broadcast transmission and reception), the television broadcast content may be encoded. Here, “coding” may include compressing video content and audio content to be transmitted, and may include, for example, Moving Picture Experts Group (MPEG), High Efficiency Video Coding (HEVC), and the like. The display apparatus100may receive a video signal and an audio signal from the broadcast receiving antenna1, and output video and audio corresponding to the video signal and the audio signal.

The display apparatus100may receive the television broadcast content from a wired cable television operator through a wired cable2. The display apparatus100may receive a video signal and an audio signal of the television broadcast content through the wired cable2and output video and audio corresponding to the video signal and the audio signal.

The display apparatus100may receive the television broadcast content from a satellite antenna3. The satellite antenna3may receive video signals and audio signals transmitted wirelessly from satellites. The display apparatus100may receive a video signal and an audio signal from the satellite antenna3and output video and audio corresponding to the video signal and the audio signal.

The display apparatus100may receive video content from a video playback apparatus4through a cable.

The video play apparatus4can store various video contents such as video, drama, and sports, or can play various video contents recorded on a recording medium, and can transmit video signals and audio signals of the video content to the display apparatus100through the cable. The display apparatus100may receive a video signal and an audio signal from the video play apparatus4through the cable, and output video and audio corresponding to the video signal and the audio signal.

The display apparatus100may receive game content from a game device5. The game device5generates (renders) an image according to a user input through an input device5aof the game device5, and sequentially transfers a plurality of generated images (video content) to the display apparatus100. Specifically, the game device5may transmit a video signal and an audio signal of the video content to the display apparatus100through the cable. The display apparatus100may receive a video signal and an audio signal from the game device5through the cable, and output video and audio corresponding to the video signal and the audio signal.

As such, the display apparatus100may receive video signals and audio data from the various content sources1-5, and decode images (multiple image frames) from the video signals, and displays the images.

The display apparatus100may include input terminals and tuners for receiving a video signal and an audio signal from the various content sources1-5. The input terminals and the tuners are connected to the content sources1-5described above, and can receive video and audio signals from the content sources1-5. In addition, the input terminals and the tuners may have various forms according to the format of a video signal and an audio signal.

The display apparatus100is not limited to a television, and the display apparatus100may be implemented in various forms such as a monitor, display terminal, portable terminal, laptop computer, projector, and billboard.

Hereinafter, the configuration and operation of the display apparatus100will be described.

FIG. 2shows a configuration of a display apparatus according to an embodiment.FIG. 3shows a configuration of an image processor included in a display apparatus according to an embodiment.

As shown inFIG. 2, the display apparatus100includes an input110for receiving the user input, a content receiver120for receiving content data from the content sources1-5; an image processor130for processing the image data included in the content data received by the content receiver120, an image display140for displaying the image processed by the image processor130, an audio outputter150for outputting sound processed by the image processor130, a controller160for controlling the operation of the content receiver120, the image processor130, the image display140and the audio outputter150

The input110may include input buttons111for receiving the user input. For example, the input110includes a power button for turning on or off the display apparatus100, a channel selection button for selecting broadcast content displayed on the display apparatus100, and sound of the sound output by the display apparatus100, a sound control button for adjusting the volume, a source selection button for selecting the content source, and the like.

Each of the input buttons111may receive the user input and output an electrical signal corresponding to the user input to the controller160.

These input buttons111may be implemented by various input means such as a push switch, a touch switch, a dial, a slide switch, and a toggle switch.

The content receiver120may include input terminals121and a tuner122for receiving content data from the content sources1-5.

The input terminals121may receive a video signal and an audio signal from the video play apparatus4or the game device5through the cable. In other words, the display apparatus100may receive a video signal and an audio signal from the video play apparatus4or the game device5through the input terminals121.

The input terminals121include, for example, a component (YPbPr/RGB) terminal, a composite (composite video blanking and sync, CVBS) terminal, an audio terminal, a High Definition Multimedia Interface (HDMI) terminal, an Ethernet (Ethernet) terminal, a Universal Serial Bus (USB) terminal, and the like.

The tuner122tunes broadcast signals from the broadcast receiving antenna1, the wired cable2or the satellite antenna3. In other words, the tuner122may extract a broadcast signal of a channel selected by the user from among the broadcast signals. For example, the tuner122may pass a broadcast signal having a frequency corresponding to a channel selected by the user among the plurality of broadcast signals received through the broadcast receiving antenna1and block a broadcast signal having a different frequency.

When a channel is selected by the user, the controller160transmits a channel selection signal to the tuner122, and the tuner122may extract the signal of the channel selected by the user among the plurality of broadcast signals according to the channel selection signal of the controller160.

The tuner122may include an analog broadcast tuner for extracting a broadcast signal of a specific channel among analog broadcast signals, a digital broadcast tuner for extracting a broadcast signal of a specific channel among digital broadcast signals, and a satellite broadcast tuner for selecting a specific channel broadcast signal among phase satellite broadcast signals.

As such, the content receiver120may receive a video signal and an audio signal from the content sources1-5through the input terminals121and/or the tuner122, and output the video and audio signals received through the input terminals121and/or the tuner122to the image processor130.

In addition, the content receiver120may detect the reception of a video signal and an audio signal through the input terminals121and/or the tuner122, and transmit a content detection signal to the controller160according to the detection result.

The user may select any one content source from among the content sources1-5connected to the display apparatus100through the input110. In addition, the user can select a channel of broadcast content through the input110, and in response to the user's channel selection, the controller160may output a channel selection signal to the content receiver120. In response to the channel selection signal, the content receiver120may output the broadcast signal of the selected channel to the image processor130.

The image processor130may process video and audio signals received from the content receiver120and generate image data and sound data. In addition, the image processor130may output image data to the image display140and audio data to the audio outputter150.

When the content source is selected by the user, the controller160transmits a content selection signal to the image processor130, and the image processor130receives video signals and audio signals received from the content receiver120according to the content selection signal of the controller160of which either video signal or audio signal can be selected.

In addition, the image processor130may decode a video signal into an image (multiple image frame data), and decode an audio signal into sound.

As shown inFIG. 2, the image processor130may structurally include a graphics processor131and a graphics memory132.

The graphics memory132may store programs and data for image processing. For example, the graphics memory132may store programs and data for decoding an image.

The graphics memory132may include a non-volatile memory, such as Read Only Memory (ROM) for storing data for a long period of time, Erasable Programmable Read Only Memory (EPROM), Electrically Erasable Programmable Read Only Memory (EEPROM) and a volatile memory such as Static Random Access Memory (S-RAM) and Dynamic Random Access Memory (D-RAM) for temporarily storing data.

The graphics processor131may perform image processing. For example, the graphics processor131may decode an image according to the programs and the data stored in the graphics memory132. In addition, the graphics processor131may temporarily store image data in the graphics memory132and retrieve the image data from the graphics memory132.

The graphics processor131includes an operation circuit (Arithmetic logic unit, ALU) for performing logical operations and arithmetic operations, and a memory circuit (for example, a register) for storing data and the graphics processor131, and a control circuit for controlling the operations.

In addition, the image processor130may functionally include an analog front end (analog front end, AFE)136, a video decoder137, and an audio decoder138as shown inFIG. 3.

The analog front end136may convert analog signals (video signals and audio signals) output from the content receiver120into digital signals.

Because a digital signal has a short transmission distance, it is common that an analog signal is used to transmit a signal or data a long distance. In the case of a video signal and an audio signal transmitted from the content sources1-5, an analog signal is also used to transmit a signal or data a long distance. In addition, due to advances in digital signal processing technology, it is advantageous to use digital signals for signal processing (e.g., video signal processing and/or sound signal processing).

For this reason, the content receiver120may receive an analog type video signal and an audio signal, and the image processor130may process a digital type video signal and an audio signal. In addition, the image processor130includes the analog front end136that converts analog-type video and audio signals into digital-type video and audio signals.

The analog front end136may include an analog-to-digital converter (ADC) and a multiplexer (MUX) and a filter for converting an analog signal to a digital signal. The specific configuration and operation of the analog front end136is described in more detail below.

The video decoder137may generate an image by reconstructing an image from analog image information included in a video signal, or by decoding digital image information included in the video signal. For example, the video decoder137may reconstruct an image from the analog image information included in the video signal received through a composite terminal or a component terminal. In addition, the video decoder137may decode digital image information included in a video signal using digital image compression algorithms such as Moving Picture Experts Group (MPEG)-2, MPEG4-4, High Efficiency Video Coding (HEVC), and the like.

The audio decoder138may restore sound from analog sound information included in an audio signal, or may generate sound data by decoding digital sound information included in the audio signal. The audio decoder138may restore sound from the analog sound information included in the audio signal received through the audio terminal. In addition, the audio decoder138may decode the digital image information included in the audio signal using digital audio compression algorithms such as Advanced Audio Coding (AAC), High-Efficiency Advanced Audio Coding (HE-AAC), and the like.

Back toFIG. 2, the image display140includes a display panel142for visually displaying an image, and a display driver141for driving the display panel142.

The display panel142may generate an image according to image data received from the display driver141and output the image.

The display panel142may include a pixel that is a unit for displaying an image. Each pixel may receive an electrical signal representing image data and output an optical signal corresponding to the received electrical signal. As such, one image may be displayed on the display panel142by combining optical signals output from a plurality of pixels.

The display panel142may use a liquid crystal display (LCD) panel, a light emitting diode (LED) panel, an organic light emitting diode (OLED), a plasma display panel (PDP), a field emission display (FED) panel, and the like. However, the display panel142is not limited thereto, and the display panel142may use various display means capable of visually displaying an image corresponding to image data.

The display driver141receives image data from the image processor130and drives the display panel142to display the image corresponding to the received image data.

Specifically, the display driver141transmits an electrical signal corresponding to image frame data to each of a plurality of pixels constituting the display panel142. In particular, the display driver141may transmit electrical signals to each pixel in various ways in order to transmit electrical signals to all pixels constituting the display panel142within a short period of time.

As such, when the display driver141transmits an electrical signal corresponding to image data to each pixel constituting the display panel142, each of the pixels outputs an optical signal corresponding to the received electrical signal, and the optical signal output from each of the pixels is combined to display one image on the display panel142.

The audio outputter150includes an audio amplifier151for amplifying sound and a speaker152for acoustically outputting the amplified sound.

The audio amplifier151may amplify an electrical acoustic signal processed by the image processor130. The audio amplifier151may include a vacuum tube or a transistor for amplifying the electrical sound signal.

The speaker152may convert the electrical sound signal output by the audio amplifier151into acoustic sound. For example, the speaker152may include a thin film that vibrates according to an electrical acoustic signal, and sound (sound waves) may be generated by the vibration of the thin film.

The controller160may control the content receiver120, the image processor130, the image display140and the audio outputter150according to the user input and/or the operating state of the display apparatus100. For example, when a content source is selected, the controller160may control the image processor130to perform image processing on the content from the selected content source. In addition, when a broadcast channel is selected, the controller160may control the content receiver120to receive the broadcast signal of the selected channel.

The controller160may include a microcontroller161that generates a control signal according to the user input and/or the operating state of the display apparatus100.

The microcontroller161includes an arithmetic circuit (ALU) that performs logical operations and arithmetic operations, and a memory circuit (S-RAM, D-RAM, etc.) that stores the calculated data, and stores in Non-volatile memory such as and ROM, IPROM, IPROM, flash memory, and the like.

The microcontroller161may generate a content selection signal for selecting a content source according to the user input, and may transmit the content selection signal to the image processor130. In response to the content selection signal, the image processor130may select one of a video signal and an audio signal output from the content receiver120, and decode the selected video signal and audio signal.

The microcontroller161may generate a channel selection signal for selecting a broadcast channel according to the user input, and may transmit the channel selection signal to the content receiver120. In response to the channel selection signal, the content receiver120may control the tuner122to extract a signal of a channel selected by the user among a plurality of broadcast signals.

The microcontroller161may generate an image adjustment signal for adjusting the brightness, contrast, sharpness, color, etc. of the image according to the user input, and may transmit the image adjustment signal to the image display140. In response to the image adjustment signal, the image display140may adjust the brightness, contrast, sharpness, and color of the image displayed by the display panel142.

In addition, the microcontroller161may generate a volume control signal for adjusting the volume of the sound according to the user input, and may transmit the volume control signal to the audio outputter150. In response to the volume control signal, the audio outputter150may adjust the volume of the sound output from the speaker152.

In this way, the display apparatus100may receive content from the various content sources1-5through the various input terminals121and the tuner122, and receive an image based on the received content, display image and output sound.

In addition, the display apparatus100includes the analog front end136for converting analog signals (video signals and audio signals) received through the input terminals121and the tuner122into digital signals. The analog front end136may include a plurality of the analog-to-digital converters.

The conventional analog front end includes a number of the analog-to-digital converters equal to the sum of the number of the input terminals and the number of outputs of the tuner. Therefore, the number of the analog-to-digital converters is increased each time a new input terminal is added.

In order to minimize the number of the analog-to-digital converters, the analog-to-digital converter included in the display apparatus100according to an embodiment may selectively receive analog video signals and audio signals selectively from a plurality of the input terminals121and the tuner122. For example, the plurality of input terminals121and the tuner122are connected to one or more of the analog-to-digital converters, and a video signal and an audio signal output from any one of the plurality of input terminals121and the tuner122according to the user input may be provided to the analog-to-digital converter.

Hereinafter, the structures of the content receiver120and the image processor130for minimizing the number of the analog-to-digital converters are described.

FIG. 4shows an example of a content receiver included in a display apparatus according to an embodiment.

Referring toFIG. 4, the content receiver120includes the input terminals121and the tuner122.

The input terminals121may include a first component terminal201, a second component terminal202, a third component terminal203, and a composite terminal204.

The first component terminal201, the second component terminal202, and the third component terminal203may receive image information representing one image. In other words, one image is obtained and formed by combining the image information received through the first component terminal201, the image information received through the second component terminal202and the image information received through the third component terminal203.

For example, the first component terminal201, the second component terminal202and the third component terminal203may receive an RGB signal.

The first component terminal201may receive red image information R, the second component terminal202may receive green image information G, and the third component terminal203may receive blue image information B.

Also, as another example, the first component terminal201, the second component terminal202, and the third component terminal203may receive YPbPr component video signals COM_Y, COM_Pb, and COM_Pr. The first component terminal201receives brightness or luminance (Y) of the image, the second component terminal202receives a difference Pb between blue brightness of the image and the overall brightness of the image, and the third component terminal203may receive a difference Pr between red brightness of the image and the total brightness of the image.

A combination COM_Pr of Y component video signal COM_Y and Pb component video signal COM_Pb and Pr component video signal received through the first component terminal201, the second component terminal202and the third component terminal203may form a one image.

The YPbPr component video signals COM_Y, COM_Pb, and COM_Pr received through the first component terminal201, the second component terminal202, and the third component terminal203may each include analog image information. An AC component (signal component whose frequency is not ‘0’) and a DC component (signal component whose frequency is ‘0’) of the YPbPr component video signals COM_Y, COM_Pb, and COM_Pr may each include image information. Also, each of the YPbPr component video signals COM_Y, COM_Pb, and COM_Pr may be single-ended signals.

The YPbPr component video signals COM_Y, COM_Pb, and COM_Pr received through the first component terminal201, the second component terminal202, and the third component terminal203may be output to the image processor130.

The composite terminal204may receive image information representing one image by itself. In other words, one image may be formed by the image information received through the composite terminal204.

For example, a composite video signal (Composite Video Blanking and Sync, CVBS) COM_CVBS may be received through the composite terminal204. The composite video signal COM_CVBS includes a luminance signal representing brightness and a color signal representing color, and an image can be reconstructed only from the composite video signal COM_CVBS.

The composite video signal COM_CVBS received through the composite terminal204may include analog image information. In other words, the magnitude (magnitude) of the composite video signal COM_CVBS may include image information. Each of the AC component and the DC component of the composite video signal COM_CVBS may include image information. Also, the composite video signal COM_CVBS may be a single-ended signal.

The composite video signal COM_CVBS received through the composite terminal204may be output to the image processor130.

The tuner122may include an analog broadcast tuner205, an analog broadcast demodulator206, a digital broadcast tuner207, and a satellite broadcast tuner208. In addition, the analog broadcast tuner205, the analog broadcast demodulator206, the digital broadcast tuner207, and the satellite broadcast tuner208may be integrally manufactured.

The analog broadcast tuner205may receive an analog broadcast signal from the broadcast receiving antenna1or the wired cable2, and extract a broadcast signal of a channel selected by the user from among the analog broadcast signals. For example, the analog broadcast tuner205may include a filter that passes a broadcast signal having a frequency corresponding to a selected channel and blocks the broadcast signals of other frequencies.

In addition, the analog broadcast tuner205may convert the extracted broadcast signal into an analog broadcast signal of an intermediate frequency (IF). For example, the analog broadcast tuner205may include a mixer that lowers the frequency of the broadcast signal to an intermediate frequency.

The analog broadcast demodulator206can demodulate an analog intermediate frequency broadcast signal. For example, the analog broadcast demodulator206may demodulate an analog intermediate frequency broadcast signal and output an analog broadcast video signal Tuner_CVBS and an analog broadcast audio signal SIF.

The analog broadcast video signal Tuner_CVBS may be a signal in CVBS format. In other words, the analog broadcast video signal Tuner_CVBS includes a luminance signal indicating brightness and a color signal indicating color, and an image can be restored from only the analog broadcast video signal Tuner_CVBS.

The analog broadcast video signal Tuner_CVBS may include analog video information and may be a single-ended signal. In addition, the AC component and the DC component of the analog broadcast video signal Tuner_CVBS may each include video information. For example, the analog broadcast video signal Tuner_CVBS may be a signal having a bandwidth of approximately 6 MHz (mega-hertz) from ‘0’ (direct current).

The analog broadcast audio signal SIF may be a sound intermediate frequency (SIF) signal. The analog broadcast audio signal SIF may include analog sound information. In addition, the analog broadcast audio signal SIF may be a single-ended signal, and the AC component and the DC component may each include sound information.

The digital broadcast tuner207may receive a digital broadcast signal from the broadcast receiving antenna1or the wired cable2, and extract a broadcast signal of a channel selected by the user from among the digital broadcast signals. For example, the digital broadcast tuner207may include a filter that passes a broadcast signal having a frequency corresponding to a selected channel and blocks the broadcast signals of other frequencies.

In addition, the digital broadcast tuner207may convert the extracted broadcast signal into an intermediate frequency broadcast signal. For example, the digital broadcast tuner207may include a mixer that lowers the frequency of the broadcast signal to an intermediate frequency.

A digital intermediate frequency signal (Digital Intermediate Frequency, DIF) (hereinafter referred to as ‘digital intermediate frequency signal’) has a form of an analog signal, but may include digital image information. Specifically, when the digital intermediate frequency signal DIF is converted to a baseband signal and the baseband signal is demodulated, digital image information having ‘0’ and ‘1’ may be restored.

The digital intermediate frequency signal DIF of the digital broadcast signal may be a differential signal. For example, the digital intermediate frequency signal DIF may include a positive digital intermediate frequency signal DIF_P and a negative digital intermediate frequency signal DIF_N.

In addition, only the AC component of the digital intermediate frequency signal DIF includes image information, and the DC component of the digital intermediate frequency signal DIF may not include image information. For example, the digital intermediate frequency signal DIF may be a signal having a bandwidth of about 6 MHz (mega-hertz) around 5 MHz (mega-hertz).

The satellite broadcast tuner208may receive a satellite digital broadcast signal from the satellite antenna3and extract a broadcast signal of a channel selected by the user from among the satellite digital broadcast signals. For example, the satellite broadcast tuner208may include a filter that passes a broadcast signal having a frequency corresponding to a selected channel and blocks the broadcast signals of other frequencies.

In addition, the satellite broadcast tuner208may convert the extracted broadcast signal into a baseband broadcast signal. For example, the satellite broadcast tuner208may include a mixer that lowers the frequency of the broadcast signal to baseband.

As such, the satellite broadcast tuner208does not use an intermediate frequency signal, unlike the digital broadcast tuner207, and can directly convert the broadcast signal to a baseband signal.

This is because the frequency band per channel of the satellite TV broadcast signal is wider than the frequency band per channel of the digital TV broadcast signal. For example, a frequency band per channel of a digital TV broadcast signal may be approximately 6 MHz (mega-hertz). In contrast, the frequency band per channel of the satellite TV broadcast signal may be approximately 45 MHz (mega-hertz).

As described above, it is difficult to process a signal of a broadcast signal due to a wide frequency band per channel of the satellite TV broadcast signal. Accordingly, the satellite broadcast tuner208may convert the extracted broadcast signal into a signal having a bandwidth of approximately 45 MHz (mega-hertz) with ‘0’ as the center frequency.

As a result, the satellite broadcast tuner208can output a signal having a bandwidth (positive frequency) of 22.5 MHz (mega-hertz). On the other hand, in order to output a signal having a different 22.5 MHz (mega-hertz) bandwidth (negative frequency), the satellite broadcast tuner208may output an I (imaginary) signal and a Q (quadratic) signal. In other words, the tuner122has an I signal ZIF_I having a bandwidth of 22.5 MHz (mega-hertz) (hereinafter referred to as ‘zero intermediate frequency I signal’) and a Q signal ZIF_Q (hereinafter referred to as ‘zero intermediate frequency Q’).

The zero intermediate frequency I signal ZIF_I and the zero intermediate frequency Q signal ZIF_Q have a form of an analog signal, but may include digital image information. Specifically, when demodulating the zero intermediate frequency I signal ZIF_I and the zero intermediate frequency Q signal ZIF_Q, digital image information having ‘0’ and ‘1’ may be restored.

The zero intermediate frequency I signal ZIF_I and the zero intermediate frequency Q signal ZIF_Q may be differential signals. For example, the zero intermediate frequency I signal ZIF_I may include a positive zero intermediate frequency I signal ZIF_I P and a negative zero intermediate frequency I signal ZIF_I N. The zero intermediate frequency Q signal ZIF_Q may include a positive zero intermediate frequency Q signal ZIF_Q_P and a negative zero intermediate frequency Q signal ZIF_Q_N.

In addition, the zero intermediate frequency I signal ZIF_I and the zero intermediate frequency Q signal ZIF_Q each contain only the AC component image information, and the DC component may not include image information.

The tuner122receives an analog broadcast signal, a digital broadcast signal and/or a satellite digital broadcast signal, and outputs the analog broadcast video signal Tuner_CVBS, the analog broadcast audio signal SIF, the digital intermediate frequency signal DIF, the zero intermediate frequency I signal ZIF_I and/or the zero intermediate frequency Q signal ZIF_Q.

As such, the content receiver120may receive image information from the various content sources1-5and output video signals and/or audio signals in various formats. For example, the content receiver120may output three of the YPbPr component video signals COM_Y, COM_Pb, and COM_Pr, the composite video signal COM_CVBS, the analog broadcast video signal Tuner_CVBS, the analog broadcast audio signal SIF, and the digital intermediate frequency signals DIF_P and DIF_N, the zero intermediate frequency I signals ZIF_I_P and ZIF_I_N, and the zero intermediate frequency Q signals ZIF_Q_P and ZIF_Q_N.

However, the video signal and/or audio signal output from the content receiver120is not limited thereto, and may further include a video signal received through the HDMI terminal and a video signal received through the USB terminal.

FIG. 5shows an example of an image processor receiving a signal from the content receiver shown inFIG. 4.

The image processor130may receive a plurality of signals output from the content receiver120shown inFIG. 4and process the received plurality of signals.

As shown inFIG. 5, the image processor130includes the analog front end136that converts signals (video signals and audio signals) outputted from the content receiver120into digital signals (or digital codes), and a CVBS decoder381/a digital broadcast demodulator382/a YPbPr decoder383/a SIF decoder384to process the digital signals.

The analog front end136includes a first analog-to-digital converter371, a second analog-to-digital converter372, and a third analog-to-digital converter373.

The first analog-to-digital converter371, the second analog-to-digital converter372, and the third analog-to-digital converter373each have a positive input terminal IN_P to which a positive signal is input and a negative input terminal IN_N to which a negative signal is input, and includes an output terminal OUT for outputting a digital code corresponding to the difference between the positive signal and the negative signal.

To process three or more of the input signals COM_Y, COM_Pb, COM_Pr, COM_CVBS, Tuner_CVBS, SIF, DIF, ZIF_I, and ZIF_Q by the three analog-to-digital converters371,372, and373, the input signals COM_Y, COM_Pb, COM_Pr, COM_CVBS, Tuner CVBS, SIF, DIF, ZIF_I, and ZIF_Q may be appropriately distributed to the first, second, and third analog-to-digital converters371,372, and373. For example, three of the YPbPr component video signals COM_Y, COM_Pb, and COM_Pr are distributed to the first, second, and third analog-to-digital converters371,372, and373, respectively. The digital broadcast signals DIF, ZIF_I, and ZIF_Q are also distributed to the first, second, and third analog-to-digital converters371,372,373, respectively. The remaining signals COM_CVBS, Tuner CVBS, and SIF may be appropriately distributed to the first, second, and third analog-to-digital converters371,372, and373.

In addition, the analog front end136may include a plurality of multiplexers so that the analog-to-digital converters371,372, and373can process a plurality of input signals.

For example, the analog front end136includes a first multiplexer301, a second multiplexer302, a third multiplexer303, a fourth multiplexer304and a fifth multiplexer305.

The first multiplexer301may be a 4*1 multiplexer that receives four signals and outputs one signal. The first multiplexer301may output any one of the positive digital intermediate frequency signal DIF_P, the Y component video signal COM_Y, the composite video signal COM_CVBS, and the analog broadcast video signal Tuner_CVBS according to the content selection signal of the controller160.

The positive digital intermediate frequency signal DIF_P, the Y component video signal COM_Y, the composite video signal COM_CVBS, and the analog broadcast video signal Tuner_CVBS can be input to the first multiplexer301through an input capacitor C. The input signals DIF_N, COM_Y, COM_CVBS, and Tuner_CVBS of the first multiplexer301may be AC coupled, the DC components of the input signals DIF_N, COM_Y, COM_CVBS, and Tuner_CVBS of the first multiplexer301may be removed and the AC components may be input to the first multiplexer301.

The first multiplexer301may output any one of the positive digital intermediate frequency signal DIF_N, the Y component video signal COM_Y, the composite video signal COM_CVBS, and the analog broadcast video signal Tuner_CVBS according to the content selection signal of the controller160to the positive input terminal IN_P of the first analog-to-digital converter371. For example, when digital TV broadcasting is selected, the first multiplexer301outputs the positive digital intermediate frequency signal DIF_P. When the content source of the component terminals201,202, and203is selected, the first multiplexer301may output the Y component video signal COM_Y. In addition, when the content source of the composite terminal204is selected, the first multiplexer301outputs the composite video signal COM_CVBS, and when analog TV broadcasting is selected, the first multiplexer301may output the analog broadcasting video signal Tuner_CVBS.

The second multiplexer302may be a 2×1 multiplexer that receives two signals and outputs one signal. The second multiplexer302may output one of the negative digital intermediate frequency signal DIF_N and a ‘ground signal’ according to the content selection signal of the controller160.

Any one of the two inputs of the second multiplexer302may be connected to the ‘ground signal’ through a resistor R, and the negative digital intermediate frequency signal DIF_N may be input to the other of the two inputs of the second multiplexer302through the input capacitor C.

The second multiplexer302may output one of the negative digital intermediate frequency signal DIF_N and the ‘ground signal’ according to the content selection signal of the controller160to the negative input terminal IN_N of the first analog-to-digital converter371. The Y component video signal COM_Y, the composite video signal COM_CVBS, and the analog broadcast video signal Tuner_CVBS are single-ended signals. In other words, the Y component video signal COM_Y, the composite video signal COM_CVBS, and the analog broadcast video signal Tuner_CVBS may be transmitted through a single signal line. Accordingly, when the content source of the component terminals201,202, and203or the content source of the composite terminal204or analog TV broadcasting is selected, the second multiplexer302may output the ‘ground signal.’ When digital TV broadcasting is selected, the second multiplexer302may output the negative digital intermediate frequency signal DIF_N.

If necessary, the second multiplexer302may be omitted. For example, the second multiplexer302may be replaced with a switch that passes or blocks the negative digital intermediate frequency signal DIF_N. For example, when digital TV broadcasting is selected, the switch is closed (turned on) to pass the negative digital intermediate frequency signal DIF_N, and when the digital TV broadcasting is not selected, the switch may be opened (turned off) to block the negative digital intermediate frequency signal DIF_N.

The output of the first multiplexer301and the output of the second multiplexer302may be respectively connected to the output of a first clamping/biasing circuit331. The first clamping/biasing circuit331may be a circuit in which a clamping circuit for clamping a signal and a biasing circuit for direct-biasing a signal are integrated.

The Y component video signal COM_Y, the composite video signal COM_CVBS, and the analog broadcast video signal Tuner_CVBS are single-ended signals, and may include video information in both the AC components and the DC components. The DC components of the Y component video signal COM_Y, the composite video signal COM_CVBS, and the analog broadcast video signal Tuner_CVBS are removed by AC coupling. Accordingly, the first clamping/biasing circuit331to restore the DC component of the signals COM_Y, COM_CVBS, and Tuner_CVBS, the Y component video signal COM_Y output from the content receiver120or the composite video signal COM_CVBS or the output of the first multiplexer301may be clamped according to the analog broadcast video signal Tuner_CVBS.

On the other hand, the positive digital intermediate frequency signal DIF_P and the negative digital intermediate frequency signal DIF_N are differential signals, and only the AC component may include image information. The DC component of the positive digital intermediate frequency signal DIF_P and the negative digital intermediate frequency signal DIF_N may be removed by AC coupling. The DC component of the differential signal does not need to be restored, but the differential signal may be distorted by removing the DC component.

The first clamping/biasing circuit331may output a biasing voltage having a predetermined size to prevent distortion of the positive digital intermediate frequency signal DIF_P and the negative digital intermediate frequency signal DIF_N. In other words, when the digital intermediate frequency signals DIF_P and DIF_N are output from the first and second multiplexers301and302, the first clamping/biasing circuit331may distort the outputs of the first and second multiplexers301and302with a predetermined biasing voltage.

As such, the first clamping/biasing circuit331clamps the output of the first multiplexer301or biases the output of the first and second multiplexers301and302depending on the Y component video signal COM_Y, the composite video signal COM_CVBS or the analog broadcast video signal Tuner_CVBS.

The output of the first multiplexer301and the output of the second multiplexer302may be input to a first buffer341. The first buffer341removes the noise of the output of the first multiplexer301and the output of the second multiplexer302, and amplifies the current so that the first analog-to-digital converter371smoothly performs analog-to-digital conversion.

The first analog-to-digital converter371receives the output of the first multiplexer301and the output of the second multiplexer302through the first buffer341, and converts the difference (analog signal) between the output of the first multiplexer301and the output of the second multiplexer302into a digital signal (digital code).

The output of the first analog-to-digital converter371may be input to the CVBS decoder381that decodes a CVBS type signal, the digital broadcast demodulator382that demodulates a digital TV broadcast signal, and the YPbPr decoder383that decodes a YPbPb component video signal.

One of the CVBS decoder381, the digital broadcast demodulator382, and the YPbPr decoder383may be activated according to the content selection signal of the controller160. For example, when digital TV broadcasting is selected, the digital broadcast demodulator382demodulates the output of the first analog-to-digital converter371, and when the composite terminal is selected, the CVBS decoder381may decode the output of the first analog-to-digital converter371. In addition, when the component terminal is selected, the YPbPr decoder383decodes the output of the first analog-to-digital converter371, and when analog TV broadcasting is selected, the CVBS decoder381may decode the output of the first analog-to-digital converter371.

The third multiplexer303may be a 2×1 multiplexer that receives two signals and outputs one signal. The third multiplexer303may output one of the positive zero intermediate frequency I signal ZIF_I_P and the Pb component video signal COM_Pb according to the content selection signal of the controller160.

The positive zero intermediate frequency I signal ZIF_I_P and the Pb component video signal COM_Pb may be AC coupled through the input capacitor C and be input to the third multiplexer303.

The third multiplexer303may output either the positive zero intermediate frequency I signal ZIF_I_P or the Pb component video signal COM Pb to the positive input terminal IN_P of the second analog-to-digital converter372according to the content selection signal of the controller160. For example, when satellite digital TV broadcasting is selected, the third multiplexer303outputs the positive zero intermediate frequency I signal ZIF_I_P, and when the component terminal is selected, the third multiplexer303displays the Pb component video signal COM_Pb.

The fourth multiplexer304may be a 2×1 multiplexer that receives two signals and outputs one signal. The fourth multiplexer304may output one of the negative zero intermediate frequency I signal ZIF_I_N and the ‘ground signal’ according to the content selection signal of the controller160.

Any one of the two inputs of the fourth multiplexer304may be connected to the ‘ground signal’ through the resistor R, and the negative zero intermediate frequency I signal ZIF_I_N may be input through the input capacitor C.

The fourth multiplexer304may select one of the negative zero intermediate frequency I signal ZIF_I_N and the ‘ground signal’ according to the content selection signal of the controller160as the negative input terminal INN of the second analog-to-digital converter372. Since the Pb component video signal COM_Pb is a single-ended signal, when the content source of the component terminals201,202, and203is selected, the fourth multiplexer304may output the ‘ground signal.’ In addition, when satellite digital TV broadcasting is selected, the fourth multiplexer304may output the negative zero intermediate frequency I signal ZIF_I_N.

If necessary, the fourth multiplexer304may be omitted. For example, the fourth multiplexer304may be replaced with a switch that passes or blocks the negative zero intermediate frequency I signal ZIF_I_N. For example, if satellite digital TV broadcasting is selected, the switch is closed (turned on) to pass the negative zero intermediate frequency I signal ZIF_I_N, and if satellite digital TV broadcasting is not selected, the switch may be opened (turned off) to block the negative zero intermediate frequency I signal ZIF_I_N.

The output of the third multiplexer303and the output of the fourth multiplexer304may be connected to a second clamping/biasing circuit332. The second clamping/biasing circuit332may clamp or bias the output of the third multiplexer303and the output of the fourth multiplexer304.

When the Pb component video signal COM_Pb is output from the third multiplexer303, to restore the DC component of the Pb component video signal COM_Pb, the second clamping/biasing circuit332may clamp the output of the third multiplexer303according to the Pb component video signal COM_Pb output from the content receiver120.

When the zero intermediate frequency I signals ZIF_I_P and ZIF_I_N are output from the third and fourth multiplexers303and304, the second clamping/biasing circuit332to prevent distortion of the zero intermediate frequency I signals ZIF_I_P and ZIF_I_N may bias the outputs of the third and fourth multiplexers303and304. For example, the second clamping/biasing circuit332may output a biasing voltage of a predetermined size.

As such, the second clamping/biasing circuit332clamps the outputs of the third multiplexer303according to the Pb component video signal COM_Pb, or biases the outputs of the third and fourth multiplexers303and304.

The output of the third multiplexer303and the output of the fourth multiplexer304may be input to a second buffer342. The output currents of the third multiplexer303and the fourth multiplexer304may be amplified by the second buffer342.

The second analog-to-digital converter372receives the output of the third multiplexer303and the output of the fourth multiplexer304passing through the second buffer342, and converts the difference between the output of the first multiplexer301and the output of the second multiplexer302(analog signal) into a digital signal (digital code).

The output of the second analog-to-digital converter372may be input to the digital broadcast demodulator382for demodulating the digital TV broadcast signal and the YPbPr decoder383for decoding the YPbPb component video signal.

One of the digital broadcast demodulator382and the YPbPr decoder383may be activated according to the content selection signal of the controller160. For example, when satellite digital TV broadcasting is selected, the digital broadcast demodulator382demodulates the output of the second analog-to-digital converter372, and when the component terminal is selected, the YPbPr decoder383can decode the output of the second analog-to-digital converter372.

The fifth multiplexer305may be a 6*2 multiplexer that receives six signals and outputs two signals. The fifth multiplexer305may multiplex a pair of the positive zero intermediate frequency Q signal ZIF_Q_P and the negative zero intermediate frequency Q signal ZIF_Q_N, a pair of Pr component of the third component terminal203and the ‘ground signal,’ and a pair of the analog broadcast audio signal SIF and the ‘ground signal’ according to the content selection signal of the controller160. In other words, the fifth multiplexer305may output any one pair of signals among the three pairs of input signals.

Since the zero intermediate frequency Q signals ZIF_Q_P and ZIF_Q N are differential signals, the positive zero intermediate frequency Q signal ZIF_Q_P and the negative zero intermediate frequency Q signal ZIF_Q_N can form a pair of signals.

The positive zero intermediate frequency Q signal ZIF_Q_P and the negative zero intermediate frequency Q signal ZIF_Q_N may be AC coupled through the input capacitor C, respectively, and be input to the fifth multiplexer305. Further, the positive zero intermediate frequency Q signal ZIF_Q_P and the negative zero intermediate frequency Q signal ZIF_Q_N may be DC-biased by a first biasing circuit351before being input to the fifth multiplexer305, respectively.

The first biasing circuit351outputs a biasing voltage having a predetermined size to prevent distortion of the positive zero intermediate frequency Q signal ZIF_Q_P and the negative zero intermediate frequency Q signal ZIF_Q_N due to AC coupling. In other words, the first biasing circuit351may bias the AC coupled zero intermediate frequency Q signal ZIF_Q.

The positive zero intermediate frequency Q signal ZIF_Q_P and the negative zero intermediate frequency Q signal ZIF_Q N biased by the first biasing circuit351may be input to a third buffer343, and the output of the third buffer343may be input to the fifth multiplexer305.

Since the Pr component video signal COM_Pr is a single-ended signal, the Pr component video signal COM_Pr may form a signal pair with the ‘ground signal.’

The Pr component video signal COM_Pr and the ‘ground signal’ may be AC coupled through the input capacitor C, respectively, and be input to the fifth multiplexer305. Further, the Pr component video signal COM_Pr and the ‘ground signal’ may be clamped by a third clamping/biasing circuit333before being input to the fifth multiplexer305, respectively.

To recover the omission of the DC component of the Pr component video signal COM_Pr by AC coupling, the third clamping/biasing circuit333may clamp the AC coupled Pr component video signal COM_Pr according to the size of the Pr component video signal COM_Pr output from the content receiver120.

The Pr component video signal COM Pr and the ‘ground’ signal may be input to a fourth buffer344and the output of the fourth buffer344may be input to the fifth multiplexer305.

Since the analog broadcast audio signal SIF is a single-ended signal, the analog broadcast audio signal SIF can form a signal pair with the ‘ground signal.’

The analog broadcast audio signal SIF and the ‘ground signal’ may be AC-coupled through the input capacitor C, respectively, and be input to the fifth multiplexer305. Also, the analog broadcast audio signal SIF and the ‘ground signal’ may be biased by a second biasing circuit352before being input to the fifth multiplexer305, respectively.

The second biasing circuit352may output a biasing voltage of a predetermined size to prevent distortion of the analog broadcast audio signal SIF. In other words, the second biasing circuit352may bias the analog broadcast audio signal SIF.

The analog broadcast audio signal SIF and the ‘ground signal’ may be input to an analog programmable gain amplifier circuit361. The analog PGA circuit361amplifies the input signal and outputs the amplified signal, and the amplification factor of the analog PGA circuit361may be changed according to the gain control signal of a gain controller362. The gain controller362may adjust the amplification factor of the analog PGA circuit361according to the size of the analog broadcast audio signal SIF.

The analog broadcast audio signal SIF amplified by the analog PGA circuit361may be input to the fifth multiplexer305.

The fifth multiplexer305may output any one pair of a pair of the zero intermediate frequency Q signals ZIF_Q_P and ZIF_Q_N and a pair of the Pr component video signals (COM_Pr, and a pair of the analog broadcast audio signals SIF into the positive/negative input terminals IN_P and IN_N of the third analog-to-digital converter373. For example, when satellite digital TV broadcasting is selected, the fifth multiplexer305outputs a pair of the zero intermediate frequency Q signals ZIF_Q_P and ZIF_Q_N, and when the content source of the component terminals201,202, and203is selected, the fifth multiplexer305may output a pair of the Pr component video signals COM_Pr. In addition, when analog TV broadcasting is selected, the fifth multiplexer305may output a pair of the analog broadcasting audio signals SIF.

The third analog-to-digital converter373may receive the output of the fifth multiplexer305and convert the output of the fifth multiplexer305into a digital signal (digital code).

The output of the third analog-to-digital converter373may be connected to the digital broadcast demodulator382that demodulates a digital TV broadcast signal, the YPbPr decoder383that decodes a YPbPb component video signal, and the SIF decoder384that decodes the analog broadcast audio signal SIF.

One of the digital broadcast demodulator382, the YPbPr decoder383, and the SIF decoder384may be activated according to the content selection signal of the controller160. For example, when satellite digital TV broadcasting is selected, the digital broadcast demodulator382demodulates the output of the third analog-to-digital converter373, and when the component terminal is selected, the YPbPr decoder383may decode the output of the third analog-to-digital converter373. Also, if analog TV broadcasting is selected, the SIF decoder384can decode the output of the third analog-to-digital converter373.

As described above, the analog front end136may be input to the YPbPr component video signals COM_Y, COM_Pb, and COM_Pr, the composite video signal COM_CVBS, the analog broadcast video signal Tuner CVBS, the analog broadcast audio signal SIF, the digital intermediate frequency signals DIF_P and DIF_N, the zero intermediate frequency I signals ZIF_I_P and ZIF_I_N and the zero intermediate frequency Q signals ZIF_Q_P and ZIF_Q_N. In other words, nine signals may be input to the analog front end136.

Each of the signals can be AC coupled with the analog front end136and can be clamped or biased by a clamping/biasing circuit.

The analog front end136may include three analog-to-digital converters. The YPbPr component video signals COM_Y, COM_Pb, and COM_Pr are distributed to three analog-to-digital converters, and the digital intermediate frequency signals DIF_P and DIF_N, the zero intermediate frequency I signals ZIF_I_P and ZIF_I_N and the zero intermediate frequency Q signals ZIF_Q_P and ZIF_Q_N may be distributed, respectively. In addition, the composite video signal COM_CVBS, the analog broadcast video signal Tuner_CVBS, and the analog broadcast audio signal SIF may be distributed to the three analog-to-digital converters, respectively.

Any one of the signals distributed to the respective analog-to-digital converters may be selected by the multiplexer, and the signal selected by the multiplexer may be converted into a digital signal (digital code) by the analog-to-digital converter.

In addition, the YPbPr component video signals COM_Y, COM_Pb, and COM_Pr, the composite video signal COM_CVBS, and the analog broadcast video signal Tuner_CVBS are single-ended signals, and include video information in both the AC and DC components. Since each of the signals is AC coupled with the analog front end136, clamping is required for the YPbPr component video signals COM_Y, COM_Pb, and COM_Pr, the composite video signal COM_CVBS, and the analog broadcast video signal Tuner CVBS. In addition, the clamping voltage value required for each of the signals COM_Y, COM_Pb, COM_Pr, COM_CVBS, and Tuner CVBS changes according to the size of each of the signals COM_Y, COM_Pb, COM_Pr, COM_CVBS, and Tuner_CVBS.

Therefore, the YPbPr component video signals COM_Y, COM_Pb, and COM_Pr, the composite video signal COM_CVBS, the YPbPr component video signals COM_Y, COM_Pb, and COM_Pr and the analog broadcast video signal Tuner_CVBS are difficult to convert to a digital signal.

Moreover, the digital intermediate frequency signals DIF_P and DIF_N, the zero intermediate frequency I signals ZIF_I_P and ZIF_I_N and the zero intermediate frequency Q signals ZIF_Q_P and ZIF_Q_N include image information only in the AC component.

Therefore, there is significant difficulty in converting all the signals COM_Y, COM_Pb, COM_Pr, COM_CVBS, Tuner_CVBS, SIF, DIF, ZIF_I, and ZIF_Q into digital signals using one analog-to-digital converter. For example, it is difficult to convert the YPbPr component video signals COM_Y, COM_Pb, and COM_Pr, the composite video signal COM_CVBS and the digital intermediate frequency signals DIF_P and DIF_N into digital signals using one analog-to-digital converter. To overcome this, a clamping/biasing circuit can be provided. By selectively clamping or biasing the AC coupled signal by the clamping/biasing circuit, the single-ended signal and the differential signal can be multiplexed by a single multiplexer.

For example, AC coupled YPbPr component video signals COM_Y, COM_Pb, and COM_Pr, the composite video signal COM_CVBS and the digital intermediate frequency signals DIF_P and DIF_N are multiplexed by a single multiplexer and selectively clamped or biased by the clamping/biasing circuit. The clamped or biased signal can be converted to a digital signal by one analog-to-digital converter.

The distribution of signals to the three analog-to-digital converters described above is only one embodiment, and is not limited thereto. For example, the Y component video signal COM_Y, the Pb component video signal COM_Pb, and the Pr component video signal COM_Pr are distributed to the first analog-to-digital converter371, the second analog-to-digital converter372and the third analog-to-digital converter373, respectively, and the remaining signals are sufficient if the signals are distributed to the first analog-to-digital converter371, the second analog-to-digital converter372and the third analog-to-digital converter373.

FIG. 6shows another example of an image processor receiving a signal from the content receiver shown inFIG. 4.

As shown inFIG. 6, the image processor130includes the analog front end136that converts analog signals (video signals and audio signals) output from the content receiver120into digital signals, and the CVBS decoder381/the digital broadcast demodulator382/the YPbPr decoder383/the SIF decoder384that processes the digital signals.

The analog front end136includes the first analog-to-digital converter371, the second analog-to-digital converter372, and the third analog-to-digital converter373. In addition, the analog front end136includes the first multiplexer301, the second multiplexer302, the third multiplexer303, the fourth multiplexer304, a sixth multiplexer306and a seventh multiplexer307.

The first analog-to-digital converter371and the second analog-to-digital converter372may be the same as those shown inFIG. 5. Also, the first multiplexer301, the second multiplexer302, the third multiplexer303, and the fourth multiplexer304may be the same as those illustrated inFIG. 5.

The sixth multiplexer306may be a 3×1 multiplexer that receives three signals and outputs one signal. The sixth multiplexer306may output any one of the positive zero intermediate frequency Q signal ZIF_Q_P, the analog broadcast audio signal SIF, and the Pr component video signal COM_Pr according to the content selection signal of the controller160.

The positive zero intermediate frequency Q signal ZIF_Q_P, the analog broadcast audio signal SIF, and the Pr component video signal COM_Pr may be input to the sixth multiplexer306through the input capacitor C.

The sixth multiplexer306may output any one of the positive zero intermediate frequency Q signal ZIF_Q_P, the analog broadcast audio signal SIF, and the Pr component video signal COM_Pr according to the content selection signal of the controller160to the positive input terminal IN_P of the third analog-to-digital converter373. For example, when satellite digital TV broadcasting is selected, the sixth multiplexer306outputs the positive zero intermediate frequency Q signal ZIF_Q_P, and when analog broadcasting is selected, the sixth multiplexer306receives the analog broadcast audio signal SIF. Also, when the component terminal is selected, the sixth multiplexer306may output the Pr component video signal COM_Pr.

The seventh multiplexer307may be a 2*1 multiplexer that receives two signals and outputs one signal. The seventh multiplexer307may multiplex the negative zero intermediate frequency Q signal ZIF_Q_N and the ‘ground signal’ of the satellite broadcast tuner208according to the content selection signal of the controller160.

Any one of the two inputs of the seventh multiplexer307may be connected to the ‘ground signal’ through the resistor R, and the other of the two inputs of the seventh multiplexer307may be input the negative zero intermediate frequency Q signal ZIF_Q_N via the input capacitor C.

According to the content selection signal of the controller160, the seventh multiplexer307may output one of the negative zero intermediate frequency Q signal ZIF_Q_N and the ‘ground signal’ to the negative input terminal IN_N of the third analog-to-digital converter373. Since the Pr component video signal COM_Pr is a single-ended signal, when the component terminal is selected, the seventh multiplexer307may output the ‘ground signal.’ Also, when satellite digital TV broadcasting is selected, the seventh multiplexer307may output the negative zero intermediate frequency Q signal ZIF_Q_N.

The output of the sixth multiplexer306and the output of the seventh multiplexer307may be respectively connected to the output of a fourth clamping/biasing circuit334. The fourth clamping/biasing circuit334may clamp or bias the output of the sixth multiplexer306and the output of the seventh multiplexer307.

When the Pr component video signal COM_Pr is output from the sixth multiplexer306, to restore the DC component of the Pr component video signal COM_Pr, the fourth clamping/biasing circuit334may clamp the output of the sixth multiplexer306according to the Pr component video signal COM_Pr output from the content receiver120. For example, the fourth clamping/biasing circuit334may output a biasing voltage of a predetermined size.

As such, the fourth clamping/biasing circuit334clamps the output of the seventh multiplexer307according to the Pr component video signal COM_Pr, or biases the outputs of the sixth and seventh multiplexers306and307.

The output of the sixth multiplexer306and the output of the seventh multiplexer307may be input to a fifth buffer345. The output currents of the sixth multiplexer306and the seventh multiplexer307may be amplified by the fifth buffer345.

The third analog-to-digital converter373receives the output of the sixth multiplexer306and the output of the seventh multiplexer307passing through the fifth buffer345, and converts the difference between the output of the sixth multiplexer306and the outputs of the seventh multiplexer307(analog signal) into a digital signal (digital code).

The output of the third analog-to-digital converter373may be input to the digital broadcast demodulator382for demodulating a digital TV broadcast signal, the YPbPr decoder383for decoding a YPbPb component video signal, and the SIF decoder384for decoding the analog broadcast audio signal SIF. One of the digital broadcast demodulator382, the YPbPr decoder383, and the analog broadcast audio signal SIF may be activated according to the content selection signal of the controller160.

A digital PGA circuit363may be provided between the output of the third analog-to-digital converter373and the input of the SIF decoder384. The digital PGA circuit363can amplify the analog broadcast audio signal SIF in digital form output from the third analog-to-digital converter373, and the gain controller362may adjust the amplification factor of the digital PGA circuit363.

As such, because the digital PGA circuit363is provided between the output of the third analog-to-digital converter373and the input of the SIF decoder384, the analog PGA circuit361shown inFIG. 5may be removed. As a result, the input circuit of the third analog-to-digital converter373can be simplified as shown inFIG. 6.

The method of removing the analog PGA circuit361shown inFIG. 5is not limited to the circuit shown inFIG. 5.

FIG. 7shows another example of a content receiver included in a display apparatus according to an embodiment.FIG. 8shows an example of an image processer that receives a signal from the content receiver shown inFIG. 7.

As shown inFIG. 7, the content receiver120may include the analog PGA circuit361.

The content receiver120includes the input terminals121and the tuner122.

The input terminals121may include the first component terminal201, the second component terminal202, the third component terminal203, and the composite terminal204, and the tuner122may include the analog broadcast tuner205, the analog broadcast demodulator206, the digital broadcast tuner207, and the satellite broadcast tuner208.

The first component terminal201, the second component terminal202, the third component terminal203, the composite terminal204, the analog broadcast tuner205, the analog broadcast demodulator206, the digital broadcast tuner207and the satellite broadcast tuner208may be the same as those shown inFIG. 4.

Compared with the content receiver120shown inFIG. 4, the content receiver120shown inFIG. 7may further include the analog PGA circuit361provided at the output of the analog broadcast demodulator206.

The analog PGA circuit361may amplify the analog broadcast audio signal SIF output from the analog broadcast demodulator206.

Also, the amplification factor of the analog PGA circuit361may be changed according to the gain control signal of the gain controller362. In other words, the analog broadcast audio signal SIF of the content receiver120can be amplified by the analog PGA circuit361, and the amplification factor of the analog PGA circuit361can be controlled by the gain controller362of the image processor130.

Also, as shown inFIG. 8, the image processor130may include the analog front end136, the CVBS decoder381, the digital broadcast demodulator382, the YPbPr decoder383, and the SIF decoder384. The analog front end136, the CVBS decoder381, the digital broadcast demodulator382, the YPbPr decoder383, and the SIF decoder384shown inFIG. 8may be the same as those shown inFIG. 6.

Compared to the image processor130illustrated inFIG. 6, the image processor130illustrated inFIG. 8may not include a digital PGA circuit. Since the content receiver120includes an analog PGA circuit that amplifies the analog broadcast audio signal SIF, the digital PGA circuit of the image processor130can be removed.

FIG. 9shows another example of a content receiver included in a display apparatus according to an embodiment.FIG. 10shows an example of an image processer receiving a signal from the content receiver shown inFIG. 9.

Referring toFIG. 9, the content receiver120includes the input terminals121and the tuner122.

The input terminals121may include a first component/composite terminal201a, the second component terminal202and the third component terminal203.

The first component/composite terminal201amay receive the Y component video signal COM_Y or the composite video signal COM_CVBS. In other words, the Y component video signal COM_Y and the composite video signal COM_CVBS can both share the first component/composite terminal201a, and the Y component output terminal or the composite output terminal of the content sources1-5may be connected to the first component/composite terminal201a.

Further, the second component terminal202receives the Pb component video signal COM_Pb, and the third component terminal203may receive the Pr component video signal COM_Pr.

The YPbPr component video signals COM_Y, COM_Pb, and COM_Pr and the composite video signal COM_CVBS may include analog video information.

The tuner122may include the analog broadcast tuner205, the analog broadcast demodulator206, the digital broadcast tuner207, the satellite broadcast tuner208, and an eighth multiplexer308.

The analog broadcast tuner205may receive an analog broadcast signal from the broadcast receiving antenna1or the wired cable2, and extract a broadcast signal of a channel selected by the user from among the analog broadcast signals. In addition, the analog broadcast tuner205may convert a broadcast signal into an analog broadcast signal of an intermediate frequency.

The analog broadcast demodulator206demodulates an analog intermediate frequency broadcast signal, and analog broadcast video signals CVBS_P and CVBS_N and the analog broadcast audio signal SIF can be output.

The analog broadcast video signals CVBS_P and CVBS_N may be CVBS format signals or differential signals. For example, the analog broadcast video signals CVBS_P and CVBS_N may include the positive analog broadcast video signals CVBS_P and the negative analog broadcast video signals CVBS_N. The analog broadcast video signals CVBS_P and CVBS_N may include analog video information.

The analog broadcast audio signal SIF may be a voice intermediate frequency signal or a single-ended signal.

The digital broadcast tuner207may receive a digital broadcast signal from the broadcast receiving antenna1or the wired cable2, and extract a broadcast signal of a channel selected by the user from among the digital broadcast signals. Also, the digital broadcast tuner207may convert a digital broadcast signal into a medium frequency broadcast signal.

The digital broadcast tuner207outputs the digital intermediate frequency signal DIF, and the digital intermediate frequency signal DIF may be a differential signal. The digital intermediate frequency signal DIF may include the positive digital intermediate frequency signal DIF_P and the negative digital intermediate frequency signal DIF_N.

The digital intermediate frequency signal DIF has the form of an analog signal, but may include digital image information.

The satellite broadcast tuner208may receive a satellite digital broadcast signal from the satellite reception antenna3and extract a broadcast signal of a channel selected by the user from the satellite digital broadcast signal. In addition, the satellite broadcast tuner208may convert the extracted broadcast signal into a baseband broadcast signal.

The satellite broadcast tuner208outputs the zero intermediate frequency I signal ZIF_I and the zero intermediate frequency Q signal ZIF_Q, and the zero intermediate frequency I signal ZIF_I and the zero intermediate frequency Q signal ZIF_Q may be differential signals, respectively. The zero intermediate frequency I signal ZIF_I may include the positive zero intermediate frequency I signal ZIF_I_P and the negative zero intermediate frequency I signal ZIF_I_N, and the zero intermediate frequency Q signal ZIF_Q may include the positive zero intermediate frequency Q signal ZIF_Q_P and the negative zero intermediate frequency Q signal ZIF_Q_N.

The eighth multiplexer308may be a 4×2 multiplexer that receives four signals and outputs two signals. The eighth multiplexer308may multiplex the positive and negative analog broadcast video signals CVBS_P and CVBS_N and the positive and negative digital intermediate frequency signals DIF_P and DIF_N according to the content selection signal of the controller160.

The eighth multiplexer308receives the positive and negative analog broadcast video signals CVBS_P and CVBS_N and the positive and negative digital intermediate frequency signals DIF_P and DIF_N, and the eighth multiplexer308may output any one of the positive and negative analog broadcast video signals CVBS_P and CVBS_N and the positive and negative digital intermediate frequency signals DIF_P and DIF_N according to the content selection signal of the controller160. For example, when analog TV broadcasting is selected, the eighth multiplexer308outputs the positive and negative analog broadcasting video signals CVBS_P and CVBS_N, and when digital TV broadcasting is selected, the eighth multiplexer308outputs the positive and negative digital intermediate frequency signals DIF_P and DIF_N.

As described above, the content receiver120outputs the Pb component video signal COM_Pb, the Pr component video signal COM_Pr, the analog broadcast audio signal SIF, the zero intermediate frequency I signal ZIF_I, and the zero intermediate frequency Q signal ZIF_Q. In addition, the content receiver120may further output one of the Y component video signal COM_Y and the composite video signal COM_CVBS (hereinafter referred to as ‘Y component/composite video signal’), and one of the analog broadcast video signals CVBS_P and CVBS_N and the digital intermediate frequency signals DIF_P and DIF_N (hereinafter referred to as a “video/digital broadcast signal”) may be further output.

In other words, the content receiver120can output a total of seven signals. The content receiver120illustrated inFIG. 9may output two fewer signals as compared to the content receiver120illustrated inFIG. 4.

Referring toFIG. 10, the image processor130includes the analog front end136that converts signals output from the content receiver120into digital signals (or digital codes) and the CVBS decoder381/the digital broadcast demodulator382/the YPbPr decoder383/the SIF decoder384.

The analog front end136includes the first analog-to-digital converter371, the second analog-to-digital converter372, the third analog-to-digital converter373, a ninth multiplexer309, a tenth multiplexer310, the third multiplexer303, the fourth multiplexer304, the sixth multiplexer306and the seventh multiplexer307.

The first analog-to-digital converter371, the second analog-to-digital converter372, the third analog-to-digital converter373, the third multiplexer303, the fourth multiplexer304, the sixth multiplexer306and the seventh multiplexer307may be the same as those shown inFIG. 6.

The ninth multiplexer309may be a 2×1 multiplexer that receives two signals and outputs one signal. The ninth multiplexer309may multiplex the Y component/composite video signal COM_Y/COM_CVBS and the positive video/digital broadcast signal DIF_P/CVBS_P according to the content selection signal of the controller160.

The Y component/composite video signal COM_Y/COM_CVBS and the positive video/digital broadcast signal DIF_P/CVBS_P may be input to the ninth multiplexer309via the input capacitor C.

The ninth multiplexer309may output any one of the Y component/composite video signal COM_Y/COM_CVBS and the positive video/digital broadcast signal DIF_P/CVBS_P according to the content selection signal of the controller160into the positive input terminal IN_P of the first analog-to-digital converter371. For example, when a component terminal or a composite terminal is selected, the ninth multiplexer309outputs the Y component/composite video signal COM_Y/COM_CVBS, and when analog TV broadcasting or digital TV broadcasting is selected, the ninth multiplexer309may output the positive video/digital broadcasting signal DIF_P/CVBS_P.

The tenth multiplexer310may be a 2×1 multiplexer that receives two signals and outputs one signal. The tenth multiplexer310may multiplex the negative video/digital broadcast signal DIF_N/CVBS_N and the ‘ground signal’ according to the content selection signal of the controller160.

Any one of the two inputs of the tenth multiplexer310may be connected to the ‘ground signal’ through the resistor R. The negative video/digital broadcast signal DIF_N/CVBS_N may be input to the other of the two inputs of the tenth multiplexer310through the input capacitor C.

The tenth multiplexer310may output any one of the negative video/digital broadcast signal DIF_N/CVBS_N and the ‘ground signal’ according to the content selection signal of the controller160to the negative input terminal IN_N of the first analog-to-digital converter371. Since the Y component/composite video signal COM_Y/COM_CVBS is a single-ended signal, when the component terminal or the composite terminal is selected, the tenth multiplexer310may output the ‘ground signal.’ Also, when analog TV broadcasting or digital TV broadcasting is selected, the tenth multiplexer310may output the negative video/digital broadcasting signal DIF_N/CVBS_N.

The output of the ninth multiplexer309and the output of the tenth multiplexer310may be respectively connected to the output of a fifth clamping/biasing circuit335. The fifth clamping/biasing circuit335may clamp or bias the output of the ninth multiplexer309and the output of the tenth multiplexer310.

When the Y component/composite video signal COM_Y/COM_CVBS is output from the ninth multiplexer309, to restore the DC component of the Y component/composite video signal COM_Y/COM_CVBS, the fifth clamping/biasing circuit335may clamp the output of the ninth multiplexer309according to the Y component/composite video signal COM_Y/COM_CVBS output from the content receiver120.

When the video/digital broadcast signals DIF_P/CVBS_P and DIF_N/CVBS_N are output from the ninth and tenth multiplexers309and310, the fifth clamping/biasing circuit335may bias the output of the ninth and tenth multiplexers309and310. For example, the fifth clamping/biasing circuit335may output a biasing voltage having a predetermined size.

As such, the fifth clamping/biasing circuit335clamps the output of the ninth multiplexer309according to the Y component/composite video signal COM_Y/COM_CVBS, or biases the outputs of the ninth and tenth multiplexers309and310.

The output of the ninth multiplexer309and the output of the tenth multiplexer310may be input to a sixth buffer346. The output currents of the ninth multiplexer309and the tenth multiplexer310may be amplified by the sixth buffer346.

The first analog-to-digital converter371receives the output of the ninth multiplexer309and the output of the tenth multiplexer310passing through the sixth buffer346, and the difference (analog signal) between the output of the ninth multiplexer309and the output of the tenth multiplexer310may be converted into a digital signal (digital code).

The output of the first analog-to-digital converter371may be input to the CVBS decoder381for decoding a CVBS type signal, the digital broadcast demodulator382that demodulates a digital TV broadcast signal, and the YPbPr decoder383for decoding the YPbPb component video signal. One of the CVBS decoder381, the digital broadcast demodulator382, and the YPbPr decoder383may be activated according to the content selection signal of the controller160.

A digital clamping circuit364may be provided between the output of the first analog-to-digital converter371and the input of the CVBS decoder381. The digital clamping circuit364may restore the DC component of the digitized analog broadcast video signals CVBS_P and CVBS_N. As described above, the analog broadcast video signal includes analog video information, and includes video information in both the AC component and the DC component. In the process of converting an analog broadcast video signal to a differential signal, the DC components may be lost. The digital clamping circuit364may restore the DC component of the analog broadcast video signals CVBS_P and CVBS_N lost in the process of converting them into differential signals.

The content receiver120includes a multiplexer for multiplexing the analog broadcast video signals CVBS_P and CVBS_N and the digital intermediate frequency signals DIF_P and DIF_N, and therefore the number of input signals to the analog front end136is reduced, and the number of inputs of the multiplexer connected to the first analog-to-digital converter371is reduced.

In the content receiver120, the analog broadcast video signals CVBS_P and CVBS_N and the digital intermediate frequency signals DIF_P and DIF_N are not limited to multiplexing. For example, the analog broadcast video signals CVBS_P and CVBS_N and the zero intermediate frequency I signals ZIF_I_P and ZIF_I_N are multiplexed, or the analog broadcast video signals CVBS_P and CVBS_N and the zero intermediate frequency Q signals ZIF_Q_P and ZIF_Q_N can be multiplexed

In addition, the method of reducing the number of inputs of the multiplexer is not limited to the circuits shown inFIGS. 9 and 10.

FIG. 11shows another example of a content receiver included in a display apparatus according to an embodiment.FIG. 12shows an example of an image processor receiving a signal from the content receiver shown inFIG. 11.

As shown inFIG. 11, the content receiver120includes the input terminals121and the tuner122.

The input terminals121include the first component/composite terminal201a, the second component terminal202, and the third component terminal203, and the tuner122includes the analog broadcast tuner205, the analog broadcast demodulator206, the digital broadcast tuner207, the satellite broadcast tuner208and an eleventh multiplexer311.

The first component/composite terminal201a, the second component terminal202, the third component terminal203, the analog broadcast tuner205, the analog broadcast demodulator206, the digital broadcast tuner207, and the satellite broadcast tuner208shown inFIG. 11may be the same as those shown inFIG. 9. Compared with the content receiver120shown inFIG. 9, the tuner122shown inFIG. 11may include the eleventh multiplexer311multiplexing the analog broadcast video signal Tuner_CVBS and the positive digital intermediate frequency signal DIF_P.

The eleventh multiplexer311may be a 2×1 multiplexer that receives two signals and outputs one signal. The eleventh multiplexer311may receive the analog broadcast video signal Tuner_CVBS and the positive digital intermediate frequency signal DIF_P, and outputs any one of the analog broadcast video signal Tuner_CVBS and the positive digital intermediate frequency signal DIF_P (hereinafter referred to as ‘video/digital broadcast signal DIF P/Tuner CVBS’) according to the content selection signal of the controller160. For example, when analog TV broadcasting is selected, the eleventh multiplexer311may output the analog broadcasting video signal Tuner CVBS, and when digital TV broadcasting is selected, the eleventh multiplexer311may output the positive digital intermediate frequency signal DIF_P.

In addition, as shown inFIG. 12, the image processor130includes the analog front end136, and the analog front end136includes the first analog-digital converter371and the second analog-digital converter372, the third analog-to-digital converter373, a twelfth multiplexer312, a thirteenth multiplexer313, the third multiplexer303, the fourth multiplexer304, the sixth multiplexer306, and the seventh multiplexer307.

The first analog-to-digital converter371, the second analog-to-digital converter372, the third analog-to-digital converter373, the third multiplexer303, the fourth multiplexer304, the sixth multiplexer306and the seventh multiplexer307may be the same as that shown inFIG. 10.

The twelfth multiplexer312may be a 2×1 multiplexer that receives two signals and outputs one signal. The twelfth multiplexer312may multiplex the Y component/composite video signal COM_Y/COM_CVBS and the video/digital broadcast signal DIF_P/Tuner_CVBS according to the content selection signal of the controller160.

The Y component/composite video signal COM_Y/COM_CVBS and the video/digital broadcast signal DIF_P/Tuner_CVBS may be input to the twelfth multiplexer312through the input capacitor C.

The twelfth multiplexer312may output any one of the Y component/composite video signal COM_Y/COM_CVBS and the video/digital broadcast signal DIF_P/Tuner_CVBS according to the content selection signal of the controller160into the positive input terminal IN_P of the first analog-to-digital converter371. For example, when a component terminal or a composite terminal is selected, the twelfth multiplexer312outputs the Y component/composite video signal COM_Y/COM_CVBS, and when analog TV broadcasting or digital TV broadcasting is selected, the twelfth multiplexer312may output the positive video/digital broadcasting signal DIF_P/Tuner_CVBS.

The thirteenth multiplexer313may be a 2×1 multiplexer that receives two signals and outputs one signal. The thirteenth multiplexer313may multiplex the negative digital intermediate frequency signal DIF_N and the ‘ground signal’ according to the content selection signal of the controller160.

The thirteenth multiplexer313may output any one of the negative digital intermediate frequency signal DIF_N and the ‘ground signal’ according to the content selection signal of the controller160to the negative input terminal IN_N of the first analog-to-digital converter371. Since the Y component/composite video signal COM_Y/COM_CVBS is a single-ended signal, when the component terminal or composite terminal is selected, the thirteenth multiplexer313may output the ‘ground signal.’ Since the analog broadcast video signal Tuner_CVBS is also a single-ended signal, when the analog TV broadcast is selected, the thirteenth multiplexer313may output the ‘ground signal.’ Also, when digital TV broadcasting is selected, the thirteenth multiplexer313may output the negative digital intermediate frequency signal DIF_N.

The output of the twelfth multiplexer312and the output of the thirteenth multiplexer313may be connected to the output of a sixth clamping/biasing circuit336, respectively. The sixth clamping/biasing circuit336may clamp or bias the output of the twelfth multiplexer312and the output of the thirteenth multiplexer313.

When the Y component/composite video signal COM_Y/COM_CVBS is output from the twelfth multiplexer312, to restore the DC component of the Y component/composite video signal COM_Y/COM_CVBS, the sixth clamping/biasing circuit336may clamp the output of the twelfth multiplexer312according to the Y component/composite video signal COM_Y/COM_CVBS output from the content receiver120.

When the analog broadcast video signal Tuner_CVBS is output from the twelfth multiplexer312, to restore the DC component of the analog broadcast video signal Tuner_CVBS, the sixth clamping/biasing circuit336may clamp the output of the twelfth multiplexer312according to the analog broadcast video signal Tuner_CVBS output from the content receiver120.

Also, when the digital intermediate frequency signals DIF_P and DIF_N are output from the twelfth and thirteenth multiplexers312and313, the sixth clamping/biasing circuit336may bias the output of the twelfth multiplexer312.

As such, the sixth clamping/biasing circuit336clamps the Y component/composite video signal COM_Y/COM_CVBS and the analog broadcast video signal Tuner_CVBS, or biases the positive and negative digital intermediate frequency signals DIF_P and DIF_N.

The output of the twelfth multiplexer312and the output of the thirteenth multiplexer313may be input to a seventh buffer347. The output currents of the twelfth multiplexer312and the thirteenth multiplexer313may be amplified by the seventh buffer347.

The first analog-to-digital converter371receives the output of the twelfth multiplexer312and the thirteenth multiplexer313passing through the seventh buffer347, and converts the difference between the output of the twelfth multiplexer312and the outputs of the thirteenth multiplexer313(analog signal) can be converted into a digital signal (digital code).

The digital clamping circuit may be removed between the output of the first analog-to-digital converter371and the input of the CVBS decoder381. Since the analog broadcast video signal Tuner_CVBS is clamped by the sixth clamping/biasing circuit336, a separate digital clamping circuit is not required.

As such, the content receiver120includes a multiplexer that multiplexes the analog broadcast video signal Tuner_CVBS and the digital intermediate frequency signal DIF. Therefore, the number of input signals to the analog front end136is reduced, and the number of inputs of the multiplexer connected to the first analog-to-digital converter371may be reduced.

The composite video signal COM_CVBS and the Y component video signal COM_Y are not limited to sharing one input terminal. For example, the composite video signal COM_CVBS and the Pb component video signal COM_Pb can share one input terminal, or the composite video signal COM_CVBS and the Pr component video signal COM_Pr can share one input terminal.

In addition, the analog broadcast video signal Tuner_CVBS and the positive digital intermediate frequency signal DIF_P are not limited to being multiplexed in the content receiver120. The analog broadcast video signal Tuner_CVBS and the negative digital intermediate frequency signal DIF_N may be multiplexed. In addition, the analog broadcast video signal Tuner_CVBS and any one of the zero intermediate frequency signals ZIF_I_P, ZIF_I_N, ZIF_Q_P, and ZIF_Q_N may be multiplexed.

FIG. 13shows another example of a content receiver included in a display apparatus according to an embodiment.FIG. 14shows an example of an image processor that receives a signal from the content receiver shown inFIG. 13.

Referring toFIG. 13, the content receiver120includes the input terminals121and the tuner122.

The input terminals121may include the first component/composite terminal201a, the second component terminal202and the third component terminal203, and the tuner122may include the analog broadcast tuner205, the analog broadcast demodulator206, the digital broadcast tuner207, the satellite broadcast tuner208, a fourteenth multiplexer314and a fifteenth multiplexer315.

The first component/composite terminal201a, the second component terminal202, the third component terminal203, the analog broadcast tuner205, the digital broadcast tuner207, and the satellite broadcast tuner208shown inFIG. 13may be the same as those shown inFIG. 9.

The analog broadcast demodulator206may demodulate the analog intermediate frequency broadcast signal and output video signals CVBS_P and CVBS_N and audio signals SIF_P and SIF_N. The analog broadcast video signals CVBS_P and CVB_N and the analog broadcast audio signals SIF_P and SIF_N may be differential signals. For example, the analog broadcast video signals CVBS_P and CVBS_N include the positive analog broadcast video signal CVBS_P and the negative analog broadcast video signal CVBS_N, and the analog broadcast audio signals SIF_P and SIF_N may include the positive analog broadcast audio signal SIF_P and the negative analog broadcast audio signal SIF_N.

The fourteenth multiplexer314may be a 4×2 multiplexer that receives four signals and outputs two signals. The fourteenth multiplexer314may multiplex the positive and negative zero intermediate frequency Q signals ZIF_Q_P and ZIF_Q_N and the positive and negative analog broadcast audio signals SIF_P and SIF_N according to the content selection signal of the controller160.

The fourteenth multiplexer314receives the positive and negative zero intermediate frequency Q signals ZIF_Q_P and ZIF_Q_N and the positive and negative analog broadcast audio signals SIF_P and SIF_N, and outputs any one of the positive and negative zero intermediate frequency Q signals ZIF_Q_P and ZIF_Q_N and the positive and negative analog broadcast audio signals SIF_P and SIF_N depending on the content selection signal of the controller160. For example, when satellite digital TV broadcasting is selected, the fourteenth multiplexer314outputs the positive and negative zero intermediate frequency Q signals ZIF_Q_P and ZIF_Q_N, and when analog broadcast is selected, the fourteenth multiplexer314may output the positive and negative analog broadcast audio signals SIF_P and SIF_N.

The fifteenth multiplexer315may be a 4×2 multiplexer that receives four signals and outputs two signals. The fifteenth multiplexer315may multiplex the positive and negative analog broadcast video signals CVBS_P and CVBS_N and the positive and negative digital intermediate frequency signals DIF_P and DIF_N according to the content selection signal of the controller160.

The fifteenth multiplexer315receives the positive and negative analog broadcast video signals CVBS_P and CVBS_N and the positive and negative digital intermediate frequency signals DIF_P and DIF_N, and outputs one of the positive and negative analog broadcast video signals CVBS_P and CVBS_N and the positive and negative digital intermediate frequency signals DIF_P and DIF_N according to the content selection signal of the controller160. For example, when analog TV broadcasting is selected, the fifteenth multiplexer315outputs the positive and negative analog broadcasting video signals CVBS_P and CVBS_N, and when digital TV broadcasting is selected, the fifteenth multiplexer315may output the positive and negative digital intermediate frequency signals DIF_P and DIF_N.

As described above, the content receiver120may output any one of the Y component video signal COM_Y and the composite video signal COM_CVBS (hereinafter referred to as ‘Y component/composite video signal’), and the Pb component video signal COM_Pb, the Pr component video signal COM_Pr and the zero intermediate frequency I signal ZIF_I. In addition, the content receiver120may further output any one of the zero intermediate frequency Q signals ZIF_Q_P and ZIF_Q_N and the analog broadcast audio signals SIF_P and SIF_N (hereinafter referred to as ‘satellite/audio broadcast signal’), and the analog broadcast video signals CVBS_P and CVBS_N, and the digital intermediate frequency signals DIF_P and DIF_N (hereinafter referred to as ‘video/digital broadcast signals’).

In other words, the content receiver120can output a total of six signals. The content receiver120illustrated inFIG. 13may output three fewer signals than the content receiver120illustrated inFIG. 4.

Referring toFIG. 14, the image processor130includes the analog front end136and the CVBS decoder381/the digital broadcast demodulator382/the YPbPr decoder383/the SIF decoder384that processes digital signals.

The first analog-to-digital converter371, the second analog-to-digital converter372, the third analog-to-digital converter373, the third multiplexer303and the fourth multiplexer304may be the same as those shown inFIG. 6. In addition, a sixteenth multiplexer316, a seventeenth multiplexer317, a seventh clamping/biasing circuit337and an eighth buffer348are respectively the ninth multiplexer309and the tenth multiplexer may be the same with the ninth multiplexer309, the tenth multiplexer310, the sixth clamping/biasing circuit336and the seventh buffer347shown inFIG. 10respectively.

An eighteenth multiplexer318may be a 2×1 multiplexer that receives two signals and outputs one signal. The eighteenth multiplexer318may multiplex the positive satellite/audio broadcast signal ZIF_Q_P/SIF_P and the Pr component video signal COM_Pr according to the content selection signal of the controller160.

The positive satellite/audio broadcast signal ZIF_Q_P/SIF_P and the Pr component video signal COM_Pr may be input to the eighteenth multiplexer318via the input capacitor C.

The eighteenth multiplexer318outputs any one of the positive satellite/audio broadcast signal ZIF_Q_P/SIF_P and the Pr component video signal COM_Pr according to the content selection signal of the controller160to the positive input terminal IN_P of the third analog-to-digital converter373. For example, when the satellite digital broadcasting and/or analog broadcasting is selected, the eighteenth multiplexer318outputs the positive satellite/audio broadcasting signal ZIF_Q_P/SIF_P, and when the component terminal is selected, the eighteenth multiplexer318may multiplex Pr The component video signal COM_Pr.

A nineteenth multiplexer319may be a 2×1 multiplexer that receives two signals and outputs one signal. The eighteenth multiplexer318may multiplex the negative satellite/audio broadcast signal ZIF_Q_N/SIF_N and the ‘ground signal’ according to the content selection signal of the controller160.

Any one of the two inputs of the nineteenth multiplexer319may be connected to the ‘ground signal’ through the resistor R, and the other of the two inputs of the nineteenth multiplexer319may be connected to the negative satellite/audio broadcast signal ZIF_Q_N/SIF_N through the input capacitor C.

The nineteenth multiplexer319may output any one of the negative satellite/audio broadcast signal ZIF_Q_N/SIF_N and the ‘ground signal’ according to the content selection signal of the controller160to the negative input terminal IN_N of the third analog-to-digital converter373. For example, when satellite digital broadcasting and/or analog broadcasting is selected, the nineteenth multiplexer319outputs the negative satellite/audio broadcasting signal ZIF_Q_N/SIF_N, and when the component terminal is selected, the nineteenth multiplexer319may output the ‘ground signal.’

The output of the eighteenth multiplexer318and the output of the nineteenth multiplexer319are clamped by an eighth clamping/biasing circuit338, and the output currents of the eighteenth multiplexer318and the nineteenth multiplexer319may be amplified by a ninth buffer349.

The output of the eighteenth multiplexer318and the output of the nineteenth multiplexer319may be connected to the output of the eighth clamping/biasing circuit338, respectively. The eighth clamping/biasing circuit338may clamp or bias the output of the eighteenth multiplexer318and the output of the nineteenth multiplexer319.

The output of the eighteenth multiplexer318and the output of the nineteenth multiplexer319may be connected to the output of the eighth clamping/biasing circuit338, respectively. The eighth clamping/biasing circuit338may clamp or bias the output of the eighteenth multiplexer318and the output of the nineteenth multiplexer319.

When the positive satellite/audio broadcast signal ZIF_Q_P/SIF_P is output from the eighteenth multiplexer318, the eighth clamping/biasing circuit338may bias the output of the eighteenth multiplexer318.

When the Pr component video signal COM Pr is output from the eighteenth multiplexer318, to restore the DC component of the Pr component video signal COM_Pr, the eighth clamping/biasing circuit338may clamp the output of the eighteenth multiplexer318according to the Pr component video signal COM Pr output from the content receiver120.

In addition, when the negative satellite/audio broadcast signal ZIF_Q N/SIF_N is output from the nineteenth multiplexer319, the eighth clamping/biasing circuit338may bias the output of the nineteenth multiplexer319.

As such, the eighth clamping/biasing circuit338may clamp the Pr component video signal COM_Pr or bias the positive and negative satellite/audio broadcasting signals ZIF_Q_P/SIF_P and ZIF_Q_N/SIF_N.

The output of the eighteenth multiplexer318and the output of the nineteenth multiplexer319may be input to the ninth buffer349. The output currents of the eighteenth multiplexer318and the nineteenth multiplexer319may be amplified by the ninth buffer349.

The third analog-to-digital converter373receives the output of the eighteenth multiplexer318and the output of the nineteenth multiplexer319passing through the ninth buffer349, and converts the difference (analog signal) between the output of the eighteenth multiplexer318and the output of the nineteenth multiplexer319into a digital signal (digital code).

As described above, the content receiver120includes a multiplexer for multiplexing the analog broadcast video signal Tuner_CVBS and the digital intermediate frequency signal DIF and a multiplexer for multiplexing the zero intermediate frequency Q signal ZIF_Q, so that the number of signals that are input to the analog front end136can be reduced.

In the content receiver120, the analog broadcast video signals CVBS_P and CVBS_N and the digital intermediate frequency signals DIF_P and DIF_N are not limited to multiplexing. For example, the analog broadcast video signals CVBS_P and CVBS_N and the zero intermediate frequency I signals ZIF_I_P and ZIF_I_N are multiplexed, or the analog broadcast video signals CVBS_P and CVBS_N and the zero intermediate frequency Q signals ZIF_Q_P and ZIF_Q_N are multiplexed.

In addition, the analog broadcast audio signals SIF_P and SIF_N and the zero intermediate frequency Q signals ZIF_Q_P and ZIF_Q_N are not limited to being multiplexed in the content receiver120. For example, the analog broadcast audio signals SIF_P and SIF_N and the zero intermediate frequency I signals ZIF_I_P and ZIF_I_N are multiplexed, or the analog broadcast audio signals SIF_P and SIF_N and the digital intermediate frequency signals DIF_P and DIF_N are multiplexed.

FIG. 15shows another example of a content receiver included in a display apparatus according to an embodiment.FIG. 16shows an example of an image processor receiving a signal from the content receiver shown inFIG. 15.

Referring toFIG. 15, the content receiver120includes the input terminals121and the tuner122.

The input terminals121includes the first component/composite terminal201a, the second component terminal202, and the third component terminal203, and the tuner122includes the analog broadcast tuner205, the analog broadcast demodulator206, the digital broadcast tuner207, the satellite broadcast tuner208, a first frequency shifter209, a signal synthesizer210and a twentieth multiplexer320.

The first component/composite terminal201a, the second component terminal202, the third component terminal203, the analog broadcast tuner205, the digital broadcast tuner207, and the satellite broadcast tuner208shown inFIG. 15may be the same as those shown inFIG. 9.

The analog broadcast demodulator206may demodulate the analog intermediate frequency broadcast signal and output the analog broadcast video signals CVBS_P and CVBS_N and the analog broadcast audio signals SIF_P and SIF_N. The analog broadcast video signals CVBS_P and CVBS_N and the analog broadcast audio signals SIF_P and SIF_N may be differential signals. For example, the analog broadcast video signals CVBS_P and CVBS_N include the positive analog broadcast video signal CVBS_P and the negative analog broadcast video signal CVBS_N, and the analog broadcast audio signals SIF_P and SIF_N may include the positive analog broadcast audio signal SIF_P and the negative analog broadcast audio signal SIF_N.

The first frequency shifter209may change the frequencies of the analog broadcast audio signals SIF_P and SIF_N. The bandwidth of the analog broadcast signal is approximately 6 MHz (mega-hertz), and the analog broadcast signal having a bandwidth of 6 MHz may include both a video signal and an audio signal. Also, the frequency of the video signal and the frequency of the audio signal may be adjacent to each other.

The first frequency shifter209changes the frequency of the analog broadcast audio signals SIF_P and SIF_N in order to clearly distinguish the frequencies of the analog broadcast video signals CVBS_P and CVBS_N and the analog broadcast audio signals SIF_P and SIF N. For example, the first frequency shifter209may increase the frequencies of the analog broadcast audio signals SIF_P and SIF_N.

The signal synthesizer210may synthesize the analog broadcast video signals CVBS_P and CVBS_N and frequency-shifted analog broadcast audio signals SIF_P and SIF_N, and output video/audio signals CVBS_SIF_P and CVBS_SIF_N. Since the frequency of the analog broadcast audio signals SIF_P and SIF_N is changed by the first frequency shifter209, in the video/audio signals CVBS_SIF_P and CVBS_SIF_N, the analog broadcast video signals CVBS_P and CVBS_N and the analog broadcast audio signals SIF_P and SIF_N can be clearly distinguished by frequency.

The twentieth multiplexer320may be a 4×2 multiplexer that receives four signals and outputs two signals. The twentieth multiplexer320may multiplex the positive and negative video/audio signals CVBS_SIF_P and CVBS_SIF_N and the positive and negative digital intermediate frequency signals DIF_P and DIF_N according to the content selection signal of the controller160.

The twentieth multiplexer320receives the positive and negative video/audio signals CVBS_SIF_P and CVBS_SIF_N and the positive and negative digital intermediate frequency signals DIF_P and DIF_N, and outputs any one of the positive and negative video/audio signals CVBS_SIF_P and CVBS_SIF_N and the positive and negative digital intermediate frequency signals DIF_P and DIF_N according to the content selection signal of the controller160. For example, when analog TV broadcasting is selected, the twentieth multiplexer320outputs the positive and negative video/audio signals CVBS_SIF_P and CVBS_SIF_N, and when digital TV broadcasting is selected, the twentieth multiplexer320may output the positive and negative digital intermediate frequency signals DIF_P and DIF_N.

As such, the content receiver120may output the Y component video signal COM_Y and any of the composite video signal COM_CVBS (hereinafter referred to as ‘Y component/composite video signal’), the Pb component video signal COM_Pb, the Pr component video signal COM_Pr, the zero intermediate frequency I signal ZIF_I, and the zero intermediate frequency Q signal ZIF_Q. In addition, the content receiver120may output the video/audio signal CVBS_SIF_P and CVBS_SIF_N and any one of the digital intermediate frequency signals DIF_P and DIF_N (hereinafter referred to as ‘analog/digital broadcast signal DIF/CVBS_SIF’).

In other words, the content receiver120can output a total of six signals. The content receiver120illustrated inFIG. 15may output two fewer signals compared to the content receiver120illustrated inFIG. 4.

The analog front end136includes the first analog-to-digital converter371, the second analog-to-digital converter372, the third analog-to-digital converter373, a twenty-first multiplexer321, a twenty-second multiplexer322, the third multiplexer303, the fourth multiplexer304, a twenty-third multiplexer323and a twenty-fourth multiplexer324.

The first analog-to-digital converter371, the second analog-to-digital converter372, the third analog-to-digital converter373, the third multiplexer303and the fourth multiplexer304are the same as those shown inFIG. 6.

The twenty-first multiplexer321may be a 2×1 multiplexer that receives two signals and outputs one signal. The twenty-first multiplexer321may multiplex the Y component/composite video signal COM_Y/COM_CVBS and the positive analog/digital broadcast signal DIF_P/CVBS_SIF_P according to the content selection signal of the controller160. For example, when a component terminal or a composite terminal is selected, the twenty-first multiplexer321outputs the Y component/composite video signal COM_Y/COM_CVBS to the positive input terminal IN_P of the first analog-to-digital converter371, and when analog broadcasting or digital broadcasting is selected, the sixteenth multiplexer316may output the positive analog/digital broadcasting signal DIF_P/CVBS_SIF_P to the positive input terminal IN_P of the first analog-to-digital converter371.

The twenty-second multiplexer322may be a 2×1 multiplexer that receives two signals and outputs one signal. The twenty-second multiplexer322may multiplex the negative analog/digital broadcast signal DIF_N/CVBS_SIF_N and the ‘ground signal’ according to the content selection signal of the controller160. When the component terminal or the composite terminal is selected, the twenty-second multiplexer322outputs the ‘ground signal’ (the signal of ‘0’) to the negative input terminal IN_N of the first analog-to-digital converter371. When analog broadcasting or digital broadcasting is selected, the twenty-second multiplexer322may output the negative analog/digital broadcasting signal DIF_N/CVBS_SIF_N to the negative input terminal IN_N of the first analog-to-digital converter371.

The output of the twenty-first multiplexer321and the output of the twenty-second multiplexer322may be connected to the output of a ninth clamping/biasing circuit339, respectively. The ninth clamping/biasing circuit339may clamp or bias the output of the twenty-first multiplexer321and the output of the twenty-second multiplexer322.

When the Y component/composite video signal COM_Y/COM_CVBS is output from the twenty-first multiplexer321, to restore the DC component of the Y component/composite video signal COM_Y/COM_CVBS, the ninth clamping/biasing circuit339may clamp the output of the twenty-first multiplexer321according to the Y component/composite video signal COM_Y/COM_CVBS output from the content receiver120.

When the positive and negative analog/digital broadcast signals DIF_P/CVBS_SIF_P and DIF_N/CVBS_SIF_N are output from the twenty-first and the twenty-second multiplexers321and322, the ninth clamping/biasing circuit339may bias the output of the twenty-first multiplexer321.

As such, the ninth clamping/biasing circuit339can clamp the Y component/composite video signal COM_Y/COM_CVBS, or bias the positive and negative analog/digital broadcast signals DIF_P/CVBS_SIF_P and DIF_N/CVBS_SIF_N.

The output of the twenty-first multiplexer321and the output of the twenty-second multiplexer322may be input to a tenth buffer349a. The output currents of the twenty-first multiplexer321and the twenty-second multiplexer322may be amplified by the tenth buffer349a.

The first analog-to-digital converter371receives the output of the twenty-first multiplexer321and the output of the twenty-second multiplexer322passing through the tenth buffer349a, and the difference (analog signal) between the output of the twenty-first multiplexer321and the output of the twenty-second multiplexer322may be converted into a digital signal (digital code).

The output of the first analog-to-digital converter371may be input to the SIF decoder384, the CVBS decoder381, the digital broadcast demodulator382, and the YPbPr decoder383.

A digital high-pass filter365, a second frequency shifter367, and the digital PGA circuit363may be provided between the output of the first analog-to-digital converter371and the input of the SIF decoder384.

The digital high-pass filter365may extract the audio signal SIF from the video/audio signals CVBS_SIF_P and CVBS_SIF_N output from the first analog-to-digital converter371. For example, the digital high-pass filter365can pass the high-frequency audio signal SIF and block the low-frequency video signal Tuner_CVBS.

The second frequency shifter367may restore the frequency of the audio signal SIF to the original frequency band. For example, the second frequency shifter367may restore the frequency of the audio signal SIF to a frequency before being changed by the first frequency shifter209.

The digital PGA circuit363may amplify the audio signal SIF according to the gain control signal of the gain controller362.

A digital low-pass filter366and the digital clamping circuit364may be provided between the output of the first analog-to-digital converter371and the input of the CVBS decoder381.

The digital low-pass filter366may extract the video signal Tuner_CVBS from the video/audio signals CVBS_SIF_P and CVBS_SIF_N output from the first analog-to-digital converter371. For example, the digital high-pass filter365may pass the low-frequency video signal Tuner_CVBS and block the high-frequency audio signal SIF.

The digital clamping circuit364may restore the DC component of the digitized analog broadcast video signals CVBS_P and CVBS_N. The digital clamping circuit364may clamp the output of the digital low-pass filter366according to the video/audio signals CVBS_SIF_P and CVBS_SIF_N output from the content receiver120.

The twenty-third multiplexer323may be a 2×1 multiplexer that receives two signals and outputs one signal. The twenty-third multiplexer323may multiplex the positive zero intermediate frequency Q signal ZIF_Q_P and the Pr component video signal COM_Pr according to the content selection signal of the controller160. When satellite digital broadcasting is selected, the twenty-third multiplexer323outputs the positive zero intermediate frequency Q signal ZIF_Q_P to the positive input terminal IN_P of the third analog-to-digital converter373. When the component terminal is selected, the twenty-third multiplexer323may output the Pr component video signal COM_Pr to the positive input terminal IN_P of the third analog-to-digital converter373.

The twenty-third multiplexer323may be a 2×1 multiplexer that receives two signals and outputs one signal. The twenty-third multiplexer323may multiplex the positive zero intermediate frequency Q signal ZIF_Q_P and the Pr component video signal COM_Pr according to the content selection signal of the controller160. When satellite digital broadcasting is selected, the twenty-third multiplexer323outputs the positive zero intermediate frequency Q signal ZIF_Q_P to the positive input terminal IN_P of the third analog-to-digital converter373, and when the component terminal is selected, the twenty-third multiplexer323may output the Pr component video signal COM_Pr to the positive input terminal IN_P of the third analog-to-digital converter373.

The twenty-fourth multiplexer324may be a 2×1 multiplexer that receives two signals and outputs one signal. The twenty-fourth multiplexer324may multiplex the negative zero intermediate frequency Q signal ZIF_Q_N and the ‘ground signal’ according to the content selection signal of the controller160. When satellite digital broadcasting is selected, the twenty-third multiplexer323outputs the negative zero intermediate frequency Q signal ZIF_Q_N to the negative input terminal IN_N of the third analog-to-digital converter373, and when the component terminal is selected, the twenty-third multiplexer323may output the ‘ground signal’ to the negative input terminal INN of the third analog-to-digital converter373.

The output of the twenty-third multiplexer323and the output of the twenty-fourth multiplexer324may be connected to the output of a tenth clamping/biasing circuit339a, respectively. The tenth clamping/biasing circuit339amay clamp or bias the output of the twenty-third multiplexer323and the output of the twenty-fourth multiplexer324.

When the Pr component video signal COM_Pr is output from the twenty-third multiplexer323, to restore the DC component of the Pr component video signal COM_Pr, the tenth clamping/biasing circuit339amay clamp the output of the twenty-third multiplexer323according to the Pr component video signal COM_Pr output from the content receiver120.

When the positive and negative zero intermediate frequency Q signals ZIF_Q_P and ZIF_Q_N are output from the twenty-third and twenty-fourth multiplexers323and324, the tenth clamping/biasing circuit339amay bias the outputs of the twenty-third and twenty-fourth multiplexers323and324.

As such, the tenth clamping/biasing circuit339amay clamp the Pr component video signal COM_Pr or bias the positive and negative zero intermediate frequency Q signals ZIF_Q_P and ZIF_Q_N.

The output of the twenty-third multiplexer323and the output of the twenty-fourth multiplexer324may be input to an eleventh buffer349b. The output currents of the twenty-third multiplexer323and the twenty-fourth multiplexer324may be amplified by the eleventh buffer349b.

The third analog-to-digital converter373receives the output of the twenty-third multiplexer323and the output of the twenty-fourth multiplexer324passing through the eleventh buffer349b. The difference (analog signal) between the output of the twenty-third multiplexer323and the output of the twenty-fourth multiplexer324may be converted into a digital signal (digital code).

The output of the third analog-to-digital converter373may be input to the digital broadcast demodulator382and the YPbPr decoder383.

In this way, the content receiver120synthesizes the analog broadcast video signal and the analog broadcast audio signal, therefore the number of input signals to the analog front end136may be reduced.

However, the content receiver120is not limited to multiplexing of the video/audio signals CVBS_SIF_P and CVBS_SIF_N and the digital intermediate frequency signals DIF_P and DIF_N. For example, the video/audio signals CVBS_SIF_P and CVBS_SIF_N and the zero intermediate frequency I signals ZIF_I_P and ZIF_I_N may be multiplexed, or the video/audio signals CVBS_SIF_P and CVBS_SIF_N and the zero intermediate frequency Q signals ZIF_Q_P and ZIF_Q_N may be multiplexed.

As described above, by multiplexing the input signals using an appropriate multiplexer, the number of analog-to-digital converters included in the analog front end can be minimized, and the number of signal lines between the content receiver and the analog front end can be minimized.

Meanwhile, the disclosed embodiments may be implemented in the form of a recording medium that stores instructions executable by a computer. The instructions may be stored in the form of a program code, and when executed by a processor, may generate program modules to perform operations of the disclosed embodiments. The recording medium may be embodied as a computer-readable recording medium.

The computer-readable recording medium includes all kinds of recording media storing instructions that can be read by a computer. For example, there may be read only memory (ROM), random access memory (RAM), a magnetic tape, a magnetic disk, flash memory, and an optical data storage device.

As described above, the disclosed embodiments have been described with reference to the accompanying drawings. Those of ordinary skill in the art to which the posted embodiments belong will understand that they may be practiced in different forms from the disclosed embodiments without changing the technical spirit or essential features of the posted embodiments. The disclosed embodiments are illustrative and should not be construed as limiting.