Stacking arrangement for integration of multiple integrated circuits

A stacked integrated circuit (IC) system including a substrate, a contour support, and a first and second IC dies. The contour support including a first support frame attached to the substrate defining a first lateral contact surface substantially orthogonal to the substrate, a support plate on the first support frame substantially parallel to the substrate, and a second support frame on the support plate defining a second lateral contact surface substantially orthogonal to the substrate, with the first and second lateral contact surfaces laterally offset from each other. The first integrated circuit die with a side abutting the first lateral contact surface, the second integrated circuit die with a side abutting the second lateral contact surface such that at least a portion of the support plate is between the first and second integrated circuit dies.

TECHNICAL FIELD

This disclosure relates to a stacking arrangement for multiple integrated circuits within a system.

BACKGROUND

Three-dimensional integrated circuits are employed in applications in which space is an important design factor. As the demand for more functionality in less space increases, so does the demand for three-dimensional packaging. In addition to the benefit of reducing space, these designs may also realize higher speeds because interconnects between circuit components may be shorter.

SUMMARY

In some examples, the disclosure describes a stacked integrated circuit system that includes a substrate defining a substrate major surface; a contour support including: a first support frame attached to the substrate major surface and defining a plurality of first lateral contact surfaces substantially orthogonal to the substrate major surface; a second support frame defining a plurality of second lateral contact surfaces substantially orthogonal to the substrate major surface, where the second support frame is on the first support frame and the second support frame is from the substrate major surface than the first support frame; a first plurality of integrated circuit dies attached to the substrate major surface, where each respective integrated circuit die of the first plurality of integrated circuit dies defines a first die major surface substantially parallel to the substrate major surface and has at least one side that abuts at least one lateral contact surface of the plurality of first lateral contact surfaces; and a second plurality of integrated circuit dies, where each respective integrated circuit die of the second plurality of integrated circuit dies defines a second die major surface substantially parallel to the substrate major surface and has at least one side that abuts at least one lateral contact surface of the plurality of second lateral contact surfaces, and for each integrated circuit die of the first plurality of integrated circuit dies, at least a portion of the integrated circuit die lies between the substrate major surface and an integrated circuit die of the second plurality of integrated circuit dies.

In another example, the disclosure describes a stacked integrated circuit system that includes a substrate defining a substrate major surface; a contour support including a first support frame attached to the substrate major surface and defining a plurality of first lateral contact surfaces substantially orthogonal to the substrate major surface, a second support frame defining a plurality of second lateral contact surfaces substantially orthogonal to the substrate major surface, with the second support frame on the first support frame and the second support frame is farther from the substrate major surface than the first support frame; a first plurality of integrated circuit dies attached to the substrate major surface, where each respective integrated circuit die of the first plurality of integrated circuit dies defines a first die major surface substantially parallel to the substrate major surface and has at least one side that abuts at least one lateral contact surface of the plurality of first lateral contact surfaces; and a second plurality of integrated circuit dies, where each respective integrated circuit die of the second plurality of integrated circuit dies defines a second die major surface substantially parallel to the substrate major surface and has at least one side that abuts at least one lateral contact surface of the plurality of second lateral contact surfaces and for each integrated circuit die of the first plurality of integrated circuit dies, at least a portion of the integrated circuit die lies between the substrate major surface and an integrated circuit die of the second plurality of integrated circuit dies.

In another example, the discloser describes a method that includes forming a contour support having a first support frame having a first lateral contact surface, a support plate having a support plate major surface, where the first support frame is attached to the support plate major surface with the first lateral contact surface substantially orthogonal to the support plate major surface, and a second support frame having a second lateral contact surface, where the second support frame is attached to the support plate on a side opposite to the support plate major surface with the second lateral contact surface substantially orthogonal to the support plate major surface and the second lateral contact surface is set back from the first lateral contact surface measured in a lateral direction substantially parallel to the support plate major surface. The method also including attaching the first support frame to a major surface of a substrate, attaching a first integrated circuit die to the major surface of the substrate such that a side of the first integrated circuit die abuts the first lateral contact surface, and attaching a second integrated circuit die to the support plate, where a side of the second integrated circuit die abuts the second lateral contact surface and a portion of the support plate is between at least a portion of the first integrated circuit die and at least a portion of second integrated circuit die.

DETAILED DESCRIPTION

The disclosure generally describes an integrated circuit package that includes a contour support that facilitates a dense stacking arrangement of multiple IC dies. In some integrated circuit (IC) systems, IC dies may be vertically stacked in order to increase the density or number of IC dies contained in the system. When IC dies are stacked, electrical connections that extend vertically may be used to supply electrical signals, including power, ground, input/output (I/O), and the like to each IC die in the stack. Additionally, in some examples, IC dies may generate heat, be sensitive to electromagnet (EM) fields (e.g., memory dies), or be sensitive to mechanical shocks and vibration. In some applications, a method for stacking integrated circuits of substantially the same size may be important, for example, creating a memory module of multiple memory dies in a relatively small space to increase the data storage capacity in a system. Such stacked IC systems may be useful as portable storage devices and/or solid state recorders.

A contour support as described herein may include at least two support frames. The support frames may be substantially planar, each including a respective major surface that is substantially parallel to a major surface of a substrate to which the contour support is attached. Each of the support frames also may define at least one lateral contact surface that is oriented substantially orthogonal (e.g., orthogonal or nearly orthogonal) to the substrate major surface. The support frames may be stacked in a direction orthogonal to the substrate major surface. The lateral contact surfaces may be configured to contact a side of a respective IC die, and may be offset from each other in a direction parallel to the substrate major surface. In this way, the contour support may define a lateral offset of the IC dies in the stacked IC arrangement with a star-step like configuration.

In some examples, the contour support also may include at least one support plate that is substantially planar in shape and extends parallel to the substrate major surface. A portion of the support plate may be between a first IC die and a second IC die in the direction orthogonal to the substrate major surface. The support plate may perform one or more functions, including, for example, mechanical support, EM shielding, heat sinking, electrical interconnection between IC dies, or the like. In some examples, the contour support may include multiple support plates, each respective support plate being between two respective IC dies. In some examples, the support plates may form a multitier, comb-like pattern with the IC dies. At least some of the IC dies may be attached to a corresponding support plate to create the sacked IC system.

FIGS. 1A and 1Bare conceptual and schematic diagrams illustrating a top view (FIG. 1A) and side view (FIG. 1B) of an example stacked integrated circuit (IC) system10including two IC dies16A and16B stacked in a single direction lateral offset configuration. In the example shown inFIGS. 1A and 1B, stacked IC system10includes a substrate12, a contour support14, and a first IC die16A and a second IC die16B (collectively, “IC dies16”).

Substrate12is substantially planar and defines a substrate major surface13on which contour support14and IC die16A are attached. Substrate12may be formed with any properties or materials suitable for the particular application for which stacked IC system10is intended. In some examples, substrate12may be a semiconductor device, may be a printed board (PB), or another device including electrical interconnects for electrically interconnecting IC dies16to an external device. In some examples, substrate12may be formed of material(s) with particular thermal properties such that substrate12helps dissipate heat generated by components of stacked IC system10, such as IC dies16. As another example, substrate12may be configured to help shield IC dies16from EM interference (e.g., radio frequency interference) or may include one or more termination resistors that may reflect electrical signals that may cause interference.

Substrate12may include a plurality of interconnect elements. Interconnect elements of substrate12may include, for example, substrate bond pads18, vias, traces, passive circuit elements (e.g., passive resistors, inductors, and capacitors), active circuit elements, metal layers, or other conductive elements positioned on or within substrate12. The plurality of interconnect elements, e.g., substrate bond pads18and the like, may be defined by any suitable electrically conductive material which facilitates electrical communication, such as tungsten, molybdenum, copper, aluminum, silver, gold, or the like. The plurality of interconnect elements of substrate12may be configured to transmit electrical signals throughout stacked IC system10including for example, between IC dies16, between IC dies16and other components of the system10, or between IC dies16and other components to which substrate12connects.

In some examples, passive elements configured to condition electrical signals within the stacked IC system10may be positioned within substrate12. For example, substrate12may be formed to include one or more passive resistors, inductors, capacitors, or any combination thereof, which are configured to manipulate signals such that the signals are satisfactory for a subsequent stage of processing. As an example, resistive elements within substrate12may be used to pull unused logic circuit inputs to particular states and to achieve particular impedance effects.

Substrate12, including any interconnect elements (e.g., substrate bond pads18), may be formed using any suitable technique. For example, substrate12may be formed using any suitable semiconductor processing technique in which interconnect elements are formed as part of the back end-of-line (BEOL) processing part of a semiconductor fabrication step. Additionally, in examples in which substrate12includes semiconductor components such as transistors, the semiconductor components may be formed using semiconductor processing techniques (e.g., as part of front-end-of-line (FEOL) processing).

IC stacked system10includes first IC die16A having a first die major surface27A and a second IC die16B having a second die major surface27B, which are aligned substantially parallel to substrate major surface13.

IC dies16of slacked IC system10may, in some examples, be configured for various signal processing tasks, which may be specific to the application for which IC stacked system10is used. Accordingly, the type of IC dies16included in system10may vary depending on the intended application. For example, IC dies16may include one or more die configured for one or more of processing (e.g., co-processor or microprocessor die), memory (e.g., random access memory (RAM) or non-volatile memory (NVM)), power conditioning, ambient monitoring (e.g., temperature and/or health monitoring), sensing, encryption, optics-photonics, or the like.

In some examples, the first IC die16A may contain a first plurality of IC bond pads20(only one IC bond pad20is labeled inFIG. 1Afor clarity) along first die major surface27A. Similarly, second IC die16B may contain a second plurality of IC bond pads22(only one IC bond pad22is labeled inFIG. 1Afor clarity) along second die major surface27B (collectively referred to as IC bond pads20,22). IC bond pads20,22may be used to establish electrical connections between IC dies16and other components throughout the stacked IC system10depending on the desired application for the system. For example, as shown inFIG. 1A, a wire bond24may be used to electrically connect a IC bond pad of first plurality of IC bond pads20to a corresponding substrate bond pad of plurality of substrate bond pads18. Similarly, wire bond24may be used to establish electrical connections between a IC bond pad of firm plurality of IC bond pads20and a IC bond pad of second plurality of IC bond pads22of between a IC bond pad of second plurality of IC bond pads22and a substrate bond pad of plurality of substrate bond pads18. Electrically connecting respective IC bond pads of first or second plurality of IC bond pads20or22with respective substrate bond pads of plurality of substrate bond pads18may be useful in some cases to connect IC dies16, for example, to a common ground, power source, or signal connection.

WhileFIGS. 1A and 1Bonly illustrate electrical connections between respective substrate bond pads of plurality of substrate bond pads18and respective IC bond pads of first and second plurality of IC bond pads20,22being made using wire bonding24, other forms of electrical connection may be utilized to connect two or more corresponding bond pads of plurality of substrate bond pads18, first plurality of IC bond pads20, or second plurality of IC bond pads22. Such examples of the electrical connections may include, for example an electrically conductive resin, a solder, a conductive metal or metal alloy, or the like. Similarly, plurality of substrate bond pads18, first plurality of IC bond pads20, and second plurality of IC bond pads22may also be electrically connected to other components in the stacked IC system10or other components in which system10is incorporated.

In the example shown inFIGS. 1A and 1B, plurality of substrate bond pads18, first plurality of IC bond pads20, and second plurality of IC bond pads22are positioned on the respective surfaces of corresponding IC dies16and substrate12. In other examples, IC dies16, substrate12, or both may include bond pads on multiple surfaces that may aid in forming electrical addition connections between IC dies16and other components in stacked IC system10(e.g., direct electrical connection between IC die16B and support plate26).

The plurality of substrate bond pads18, first plurality of IC bond pads20, and second plurality of IC bond pads22may be defined using any suitable technique, including BEOL semiconductor processing techniques, and may be formed of any suitable electrically conductive material.

In the example shown inFIG. 1A, respective bond pads of plurality of substrate bond pads18, first plurality of IC bond pads20, and second plurality of IC bond pads22are electrically connected by a respective wire of wires24. Wires24(e.g., aluminum, copper, gold wires) can be electrically and mechanically connected to respective bond pads of plurality of substrate bond pads18, first plurality of IC bond pads20, and second plurality of IC bond pads22using any suitable technique. For example, wires24may be wedge bonded, ball bonded, soldered, or the like to respective bond pads of plurality of substrate bond pads18, first plurality of IC bond pads20, and second plurality of IC bond pads22.

In some examples, the first and second IC dies16A and16B may be rectangular in shape and may be the same size. In other examples, IC dies16may be non-rectangular in shape and/or may differ in size. IC dies16may be processed to be substantially planar (e.g., planar or nearly planar), and incorporated into contour support14so that each major surface27A and27B is substantially parallel to substrate major surface13.

In some examples, IC dies16may include a die that is not inherently configured for stacking in an IC system, e.g., that do not include through-vias extending completely through the thickness of the die (measured in the direction orthogonal to the surface13of substrate12in the example shown inFIG. 1B). In this way, the IC dies16need not be custom made to be incorporated into system10and, instead, may be third party dies and selectively incorporated based on a particular application for which system10is intended. Contour support14may facilitate stacking IC dies16, including IC dies16that may not be configured for stacking in an IC system.

As shown inFIG. 1B, contour support14includes a first support frame15A, a support plate26, and a second support frame15B. First support frame15A attaches to the substrate major surface13and defines a first lateral contact surface28A that is substantially orthogonal (e.g., orthogonal or nearly orthogonal) to substrate major surface13. Support plate26is on top of first support frame15A and may be substantially planar in shape defining a support plate major surface29that may be aligned over and substantially parallel to substrate major surface13so that support plate26defines a gap sized to receive IC die16A. Second support frame15B is on top of support plate26and defines a second lateral contact surface28B that is substantially orthogonal (e.g., orthogonal or nearly orthogonal) to substrate major surface13. First and second lateral contact surfaces28A and28B are arranged such that the lateral contact surfaces28A and28B are laterally offset from one another in a direction substantially parallel to substrate major surface13. The lateral offset between first and second lateral contact surfaces28A and28B may facilitate stacking of IC dies16in a staggered arrangement when incorporated into IC system10.

First IC die26A attaches to the substrate major surface13within the gap between support plate26and substrate12with a side of first IC die26A abutting first lateral contact surface28A and a portion of first die major surface27A covered by support plate26. The second IC die16B may be attached to support plate26on the side opposite to first IC die16, with a side of second IC die26B abutting second lateral contact surface28B. As used herein “abut” and “abutting” may indicate physical contact between at least part of one surface with at least part of another surface.

In some examples, IC dies16may be mechanically coupled to the adjacent support plate26and/or substrate12(e.g., IC die16A coupled to substrate12and support plate26) via an adhesive. The adhesive (not shown) may include any suitable adhesive material configured to mechanically couple IC dies16to the adjacent support plate26or substrate12in stacked IC system10. For example, the adhesive may comprise an SU-8 adhesive, a benzocyclobutene (BCB) adhesive, or another adhesive that utilizes free-radical, non-condensation-based organic reactions (e.g., an adhesive that does not include ions, water, alcohols, or corrosives). The adhesive may be applied to IC dies16using any suitable adhesive bonding technique. In other examples, IC system10may include another type of wafer bond to mechanically couple IC dies16to corresponding a support plate26or substrate12. For example, in some examples, thermal compression bonding (e.g., copper-to-copper thermal compression bonding or oxide bonding) may be utilized to mechanically couple IC die16A to substrate12in stacked IC system10.

As shown inFIGS. 1A and 1B, contour support14is configured to mechanically contact each of IC dies16such that each IC die16A and16B has at least one side perpendicular to substrate surface13that abuts a portion of contour support14. Contour support14may be configured so that the first and second IC dies16A,16B are stacked to form a lateral offset in at least one direction creating, for example, a stair-step style stacking. Support plate26may also be laterally offset from the first IC die16A so that support plate26partially covers first major surface27A of IC die16A leaving a portion of major surface27A exposed. The exposed surface of IC die16A may include the first plurality of IC bond pads20allowing for wire bonding24of bond pads from first plurality of IC bond pads20to other components in stacked IC system10.

In some examples, contour support14may be a formed as a single unitary structure including first and second support frames15and support plate26. In some such examples, the entire contour support14may be formed prior to inserting and attaching IC dies16. In other examples, first support frame15A, support plate26, and second support frame15B of contour support14may be distinct physical components assembled sequentially with corresponding IC dies16in a step-wise manner as describe in More detail below with respect toFIGS. 4-7. In other examples, contour support14may be formed using a combination of these or other techniques.

Contour support14may be formed with any properties or materials suitable for lire particular application for which stacked IC system10is intended. For example, contour support14, including at least one of first and second support frames15and support plate26, may include a material that provides mechanical support to contour support14, provides shielding to IC dies16from charged particles, provides magnetic shielding to IC dies16, provides thermal conductivity for conducting heat from IC dies16, provides electrical interconnections within or between IC dies16, is a getter for water or other gases or liquids, or the like. The materials front which each of first support frame15A, second support frame15B, and support plate26may be independently selected to be the same or different depending on the properties desired for each of first support frame15A, second support frame15B, and support plate26.

In some examples, at least one of first support frame15A, second support frame15B, or support plate26may include an electrically insulating material, such as an electrically insulating ceramic material. Example ceramic materials from which contour support14may be formed include, but are not limited to, alumina (Al2O3), aluminum nitride (AlN), beryllium oxide (BeO), and silicon carbide (SiC).

In some examples, at least one of first support frame15A, second support frame15B, or and support plate26may include materials that provide structural support and rigidity to stacked IC system10. Improving the rigidity of stacked IC system10may allow a plurality of IC dies16to be stacked within a single stacked arrangement without incurring mechanical failure under normal operating conditions. Materials that may enhance such mechanical features of the system10may include, for example, aluminum, anodized aluminum, brass, stainless steels, perforated circuit board material, or the like.

In some examples, at least one of first support frame15A, second support frame15B, or support plate26may include a thermally conductive material to help dissipate heat generated by components of stacked IC system10during operation, e.g., IC dies16. In such examples, the thermally conductive materials may be included in support frames15, support plate26, or both so that support frames15, support plate26, or both transfer heat generated by IC dies16to another area of system10, such as, for example, substrate13or a heat sink (not shown) attached to contour support14. Thermally conductive materials that may be useful for dissipating heat include, for example, aluminum, anodized aluminum, brass, copper, silver, gold, alloys including alloys of nickel, iron, and cobalt, or the like. In some examples the thermally conductive materials may have a thermal conductivity in excess of about 10 to 100 watts per meter kelvin (W/(m·K)).

In some examples, the thermally conductive materials of contour support14may reduce mechanical stresses in stacked IC system10resulting from coefficient of thermal expansion (CTE) mismatches that of the components of stacked IC system10. For example, mechanical stress generated by thermal expansion and CTE mismatches between support plate26and IC dies16could lead to physical deformation and cause premature failure. In some examples, the thermally conductive materials included in contour support14may be selected so that the thermally conductive materials possess good CTE compatibility with adjacent components so that any mechanical stress generated as a result of CTE mismatches is within tolerable limits.

In some examples, at least one of first support frame15A, second support frame15B, or support plate26may be configured to help shield IC dies16from EM interference (e.g., radio frequency interference) or may include one or more termination resistors that may reflect electrical signals that may cause interference. In some examples, at least one of first support frame15A, second support frame15B, or support plate26may include materials that have EM shielding properties including, for example, nickel/iron, nickel/iron/molybdenum, alloys of nickel/iron or nickel/iron/molybdenum, or the like.

In some examples, at least one of first support frame15A, second support frame15B, or support plate26may include a ferromagnetic material that shields at least one of IC dies16from external magnetic fields. For example, one or more of IC dies16may include magnetoresistive random access memory (MRAM) or another type of IC die sensitive to magnetic fields. By including at least one of first support frame15A, second support frame15B, or support plate26including a ferromagnetic material, IC system10may be less sensitive to external magnetic fields.

In this way, contour support14may provide mechanical support and arrangement of IC dies16and, in some examples, may provide additional functionality to stacked IC system10.

In some examples, slacked IC system10may be incorporated into a larger system using any suitable technique. For example, stacked IC system10may be incorporated into an IC package (not shown), which may provide protection of stacked IC system10contained therein against environmental contaminants. For example, the IC package may hermetically enclose stacked IC system10. Additionally or alternatively, the IC package may aid in dissipating heat generated by stacked IC system10enclosed therein or improve the EM shielding for system10. In some examples, the IC package may also facilitate mounting of stacked IC system10onto a printed board, e.g., using solder balls, conductive pins, solder columns, and the like. In other examples, stacked IC system10may be directly mechanically and electrically connected to a printed board, without being disposed in an IC package.

Stacked IC system10may be packaged in any suitable manner using any suitable packaging technique known in the art. For example, slacked IC system10may be packaged in a package including an electrically conductive material such as aluminum silicon carbide (AlSiC), copper tungsten (CuW), copper molybdenum (CuMo), a nickel cobalt ferrous alloy (e.g., an alloy provided under the trademark Kovar®, made available by Carpenter Technology Corporation of Reading Pa.), or the like. As another example, stacked IC system10may be packaged in a package including an electrically insulating ceramic material, such as aluminum oxide, aluminum nitride (AlN), beryllium oxide (BeO), and silicon carbide (SiC). In some examples, stacked IC system10may be packaged in a package including materials that are thermally conductive or include a polymeric material, such as a polytetratluoroethylene (PTFE)/ceramic based laminate (e.g., Rogers RO2800 laminate, which is made commercially available by Rogers Corporation of Rogers, Conn.) or fluoropolymer materials (e.g., fluoropolymers made commercially available by W.L. Gore and Associates of Newark, Del.), FR-4, BT-Epoxy, or polyimide.

FIGS. 1A, 1Bdepict an arrangement where IC dies16are assembled in contour support14so that the dies16are laterally offset from one another in one direction. In some examples, contour support14may be configured so that IC dies16are laterally offset in more than one direction. For example, in some examples IC dies16may be laterally offset in two or three directions. Such configurations may be obtained by using, for example, IC dies16of different sizes, where the dies16are stacked outward from the substrate surface13in the order of largest to smallest dies. Such configurations may allow for two or three perimeter surfaces of the larger IC dies16to be exposed when the subsequent smaller dies are incorporated into contour support14.

In another example, IC dies16may be the same size and laterally offset in two directions. For example,FIGS. 2A and 2Billustrate a conceptual and schematic top (FIG. 2A) view and a conceptual and schematic side view (FIG. 2B) of an example IC system30that includes multiple stacked arrangements of IC dies34A,34B,34C,34D (collectively, “IC stacks34”) attached to a substrate major surface33of substrate32. For purposes of clarity, IC stacks34are described in reference to IC stack34A. The descriptions provided, however, are intended to apply to any of IC stacks34of system30.

As shown inFIG. 2B, IC stack34A includes a plurality of IC dies38A-38D (collectively, “IC dies38”) assembled with a contour support36. Contour support36includes a plurality of support frames55A-55D (collectively, “support frames55”) and a plurality of support plates54A-54C (collectively, “support plates54”) stacked in an alternating arrangement orthogonally from substrate major surface33. Each support plate of support plates54is substantially planar in shape and includes a respective support plate major surface of support plate major surfaces59A-59C aligned above and substantially parallel to substrate major surface33.

Similarly, each IC die of IC dies38includes a corresponding die major surface of die major surfaces58A-58D (e.g., IC die38D includes die major surface58D) aligned substantially parallel to substrate major surface33. Support plates54are configured in a staggered arrangement with support frames55providing space between adjacent plates54to receive a corresponding IC die of IC dies38. For example, in IC stack34A, the support plates54and IC dies38are arranged such that first IC die38A is attached to substrate32and first support plate54A is attached to first die major surface58A of IC die38A. Second IC die38B is attached to first support plate major surface89A of first support plate54A, and second support plate54B is attached to second die major surface58B of second IC die38B. Third IC die38C is attached to second support plate major surface89B of second support plate54B with third support plate54C attached to third die major surface58C of third IC die38C. Further fourth IC die38D is attached to third support plate major surface89C of third support plate54C. While only four IC dies38are illustrated inFIGS. 2A and 2B, IC stack34A may contain more or fewer IC dies38depending on the intended purpose for IC system30.

In some examples, each support frame54has at least one respective lateral contact surface56A-56D (collectively, “lateral contact surfaces56”) aligned substantially orthogonal (e.g., orthogonal or nearly orthogonal) to substrate surface33and configured to physically pair with a corresponding IC die of IC dies38so that each respective IC die of IC dies38has at least one side that abuts a respective lateral contact surface of lateral contact surfaces56. For example, support frame55A includes first lateral contact surface56A that abuts one side of first IC die38A. As shown inFIG. 2A, IC dies38may be positioned adjacent to contour support36so IC dies38are laterally offset from one another in at least two directions (e.g., the x-axis and y-axis directions as shown). In some examples, the lateral offset of adjacent IC dies38may be substantially uniform and repetitive across the entire IC stack34A (e.g., a consistent displacement in an x-direction and a y-direction as shown inFIG. 2A). In other examples, the lateral offset may be non-uniform or non-repetitive within IC stack34A.

In some examples, support plates54may also be laterally offset with respect to one of the adjacent IC dies38. For example, in stack34A, first and second IC dies38A and38B are positioned on (e.g., attached to) opposite sides of first support plate54A. Respective edges of second IC die38B and first support plate54A are laterally aligned and latterly offset from an edge of first IC die38A in both the x-axis and y-axis directions; however, the edges of second IC die38B and first support plate54A are not laterally offset with respect to each other in the x-axis and y-axis directions. In this manner, first support plate54A partially covers first IC die38A leaving first IC die major surface58A partially exposed along two perimeter portions of IC first die38A.

In some examples, the exposed portions of the topsides of IC dies38may contain a plurality of IC bond pads42, which may be used to form electrical connections (e.g., via wires50) between IC dies38and other components in IC system30. For example, as shown inFIG. 2A, first IC die38A includes a plurality of first IC bond pads42A (only one IC bond pad is labeled inFIG. 2Afor clarity). Wires50may be used to form electrical connections between respective IC bond pads of first IC bond pads42A and another component in system30including, for example, a corresponding substrate bond pad40located on substrate major surface33or a corresponding IC bond pad of another IC she in IC stack34A, e.g., IC bond pad42B of second IC die38B. In some examples, IC dies38may also be electrically connected to other components in IC stack34, system30, or other components in which system30is incorporated.

In some examples, contour support36may define a mounting aperture52extending substantially through contour support36. In some examples, mounting aperture52also may extend through substrate32. Mounting aperture52may be aligned so that it extends substantially orthogonally (e.g., orthogonally or nearly orthogonally) to the surface of substrate32. Mounting aperture52may be placed anywhere in contour support36such that the mounting aperture52does not physically interfere with the stacking arrangements of IC dies38. Additionally, mounting aperture52may be of any shape, including, for example, a cylindrical or polygonal tube. In some examples, mounting aperture52may receive a mounting post (not shown) that facilitates mounting one or more IC systems30within a single device. In some examples, mounting aperture52may also allow for additional components to be attached and secured to IC stacks34such as a compression plate mounted to the topside contour support36that secures IC stacks34and/or the IC dies38within IC stacks34.

In some examples, mounting aperture52may contain or be coated with a thermally conductive material to provide a low thermal impedance, thermally conductive path through IC stacks34. In some such examples, IC stack34may be configured to allow heat to flow from IC dies38, through corresponding support plates54to the mounting aperture52. In some examples, a heat sink or other device designed to assist in cooling IC system30may then be attached to mounting aperture52, thereby further dissipating heat originating from IC dies38.

AlthoughFIGS. 1A-2Bhave illustrated examples in which IC dies are located on one side of a contour support, in other examples, a stacked IC system may include a plurality of IC dies in each of a plurality of tiers. In at least one of the tiers, the respective plurality of IC dies may substantially surround (e.g., surround or nearly surround) a respective support frame. By including a plurality of IC dies around a support frame, the density of IC dies may be further increased compared to the examples shown inFIGS. 1A-2B.FIGS. 3A and 3Billustrate another example of an IC system60in accordance with the disclosure. In particular,FIGS. 3A and 3Bare conceptual and schematic top (FIG. 3A) and side (FIG. 3B) views of an example stacked IC system60that includes a substrate70having a substrate major surface71, a contour support72including a plurality of support frames87and a plurality of support plates84arranged to create multiple tiers86A-86D (collectively, “tiers86”). Each tier or tiers86includes a respective support frame of support flames87and a respective plurality of IC dies. For example, system60includes a first tier86A that includes a first support frame87A and a first plurality of IC dies62A-62D, a second tier86B that includes a second support frame87B and a second plurality of IC dies64A-64D, a third tier86C that includes a third support frame87C and a third plurality of IC dies66A-66D, and a fourth tier86D that includes a fourth support frame87D and a fourth plurality of IC dies68A-68D.

In some examples, tiers86may be in the shape of a plane and aligned substantially parallel to the surface of substrate70. Tiers86may be stacked, in some examples, in a square-pyramidal configuration with each successive tier farther away from substrate70and sequentially smaller in lateral extent than the previous tier. In some such examples, a corresponding stack of IC dies (e.g., dies62C,64C,66C, and68C (collectively IC dies62C-68C)) may be stacked and arranged so adjacent dies (e.g., dies62C and64C) are laterally offset in at least one direction (e.g., two directions as shown inFIG. 3A) with each successively stacked die farther away from substrate70and closer toward the center of contour support72defined by a mounting aperture82. The stacking arrangement may be repeated for each set of corresponding stacked IC dies (e.g., IC dies62A-68A, IC dies62B-68B, and IC dies62D-68D) creating a high density packing of IC dies, which may be useful in a variety of applications.

In the example shown inFIGS. 3A and 3B, each tier86includes four IC dies (e.g., first plurality of IC dies62A-62D) and a portion of contour support72(e.g., support frame87A). Each support frame87includes a plurality of lateral contact surfaces aligned substantially orthogonal (e.g., orthogonal or nearly orthogonal) to substrate major surface71. For example, as best shown inFIG. 5A, first support frame87A contains a first plurality of lateral contact surfaces88A-88H (collectively, “lateral contact surfaces88”). Lateral contact surfaces88may be configured to physically pair with a corresponding IC dies of the first plurality of IC dies62A-62D so that at least two sides of each IC die62A-62D abut at least two lateral contact surfaces88. For example, to sides of IC die62C abut lateral contact surfaces88A and88B.

In some examples, contour support72includes a plurality of support plates84A-84D (collectively support plates84) that are substantially planar in shape and extend laterally outward from the center portion of contour support72defined by mounting aperture82. Support plates84may be positioned substantially parallel to one another and configured in a staggered arrangement with corresponding support frames87separating adjacent support plates84. For example, as shown inFIGS. 3A and 3B, stacked IC stack60is configured with tier86A, which includes first support frame87A and first plurality of IC dies62, attached to substrate major surface71, with support plate84A attached to the topside of tier86A; with tier86B attached to the topside of support plate84A; with support plate84B attached to the topside of tier86B; with tier86C attached to the topside of support plate84B; with support plate84C attached to the topside of tier86C; with tier86D attached to the topside of support plate84C; and with support plate84D attached to the topside of tier86D. While only four tiers86are illustrated inFIGS. 3A and 3B, stacked IC system60may contain more or fewer tiers86depending on the intended purpose for system60. Additionally, each tier86may contain more or fewer IC dies62,64,66, and68resulting in different stacking arrangements, e.g., trigonal-pyramidal, hexagonal-pyramidal, or the like.

In some examples, IC dies within a respective tier of tiers86may be configured to perform similar functions including, for example, memory storage, processing, or the like. In other examples, IC dies with a respective tier of tiers86may be configured to perform different functions. Similarly, in some examples, each tier of tiers86may include IC dies configured to perform similar functions, such that all IC dies62,64,66, and68in stacked IC system60perform the same function, or at least one tier of tiers86may include IC dies configured to perform different functions that at least one other tier of tiers86. For example, tier86A may include IC dies62that are dedicated to performing system operations while tiers86B-86D include IC dies64,66, and68dedicated to memory storage.

In some examples, each tier of tiers86can have a substantially similar thickness (measured in a direction substantially perpendicular to substrate major surface71), while in other examples, at least two tiers of tiers86have different thicknesses. The thickness of each tier86can be selected based on various factors, such as the thickness of the plurality of IC dies (e.g., IC dies62) to be incorporated in the corresponding tier (e.g., tier84A). In some examples, the thickness of the tiers86may be thicker than the corresponding IC dies62,64,66,68to allow for the corresponding dies to be inserted and attached to contour support72during manufacturing of stacked system60.

In some examples, support plates84may partially cover the topside of the corresponding IC tier86to which support plate84attaches. For example, as shown inFIG. 3A, support plate84D partially covers tier86D, leaving two perimeter portions on the respective major surfaces of each IC die of IC dies68A-68D partially exposed.

In some examples, the partially exposed major surfaces of IC dies62,64,66, and68may contain a plurality of IC bond pads, e.g., IC bond pad76A of IC die62C, that may be used to form electrical connections, e.g., using wires78, between respective IC dies of IC dies62,64,66, and68and other components in system60. For example, as shown inFIG. 3A, IC bond pad76A of third IC die62C may be electrically connected to a corresponding substrate bond pad74located on the substrate major surface71using a wire78. IC dies62,64,66, and68may also be electrically connected to other components in stacked IC system60or other components in which system60is incorporated.

In some examples, support plates84may include at least one electrically conductive trace80. For example, support plates84may include a ceramic, a polymer, a plastic, a semiconductor, or the like, which may include at least one electrically conductive trace80. In some examples, at least one electrical trace80may be used to make an electrical connection between a first IC die and a second IC die of IC dies62,64,66, or68. For example, as shown inFIG. 3A, a respective electrical trace of electrical traces80may be used to electrically connect IC dies68B and68C (e.g., respective bond pads on IC dies68B and68C) to one another. In some such examples, the electrical trace of electrical traces80may be attached to corresponding IC bond pads76B and76C of IC dies68B and68C that are covered by support plate84D. Additionally or alternatively, electrical traces80may be configured to transmit electrical signals between two or more IC bond pads of a single IC die (e.g., IC bond pads76D and76E of IC die68A as shown inFIG. 3A), two or more IC dies of different tiers (e.g., between IC dies66C and68C of tiers86C and86D respectively using support plate84C—not illustrated), or the like.

The plurality of electrical traces80may be formed in support plates84using any applicable technique including, for example, forming traces80as part of the fabrication of support plates84. For example, a plurality of metal layers may be deposited onto a dielectric material using planar copper dual damascene interconnect technology; tungsten polished local interconnect technology, or planarized subtractive aluminum interconnect technology; or printed, plated, or the like on a dielectric material; or some combination of these techniques during formation of support plates84. The traces80may be defined by any suitable electrically conductive material which facilitates electrical communication, such as tungsten, molybdenum, copper, aluminum, silver, or gold. The electrical connections between traces80and covered bond pads76of IC dies62,64,66, and68may be establish using any suitable means including, for example, brazing, soldering, or the like.

In some examples, each of support plates84may perform a similar function (e.g., electrical interconnection, mechanical support, radiation shielding, magnetic shielding, thermal conductivity, EM shielding, or any other function described herein) and may include a similar construction, aside from dimensional differences used to form the stepped structure described herein. In other examples, at least one of support plates84may include a different function than at least one other of support plates84and, accordingly, may include a different construction to accomplish the different purpose. In some examples, the purpose of each support plate of support plates84may be affected by the function of the adjacent IC dies of IC dies62,64,66, and68. For example, if a tier of IC dies (e.g., tier86A) includes MRAM dies, the adjacent support plate (e.g., support plate84A) may include a ferromagnetic material, which provides magnetic shielding to the MRAM dies. As another example, if a tier of IC dies (e.g., tier86C) includes a plurality of processors, an adjacent support plate (e.g., support plates84B and/or84C) may provide electrical interconnection, thermal conductivity, or both. Other examples are contemplated by the disclosure and will be apparent based on the description.

The thickness of support plates84also may be selected based on various factors including, for example, to facilitate the best shape or configuration of wires78that electrically connect the IC dies62,64,66, and68to other components in stacked IC system60. For example, incorporating a thicker support plate84may provide a greater separation distance between two wires78attached to adjacent tiers86(e.g., tiers86A and86B), which may prevent accidental contact or transmission of signal noise through electromagnetic coupling or interference. Additionally, a thicker support plate84may help reduce the possibility of a short circuit (e.g., conductive portions of wires78contacting each other) or an undesirable electrical connection between two or more stacked tiers86. As other examples, thicker support plates84may provide greater mechanical support, EM, magnetic, or radiation shielding, heat transfer, or the like. However, thicker support plates84also may result in a larger stacked IC system60.

In some examples, contour support72may define mounting aperture82, which extends substantially through contour support72and substrate70. Mounting aperture82may be aligned so that it extends substantially orthogonally (e.g., orthogonally or nearly orthogonally) to substrate major surface71. Mounting aperture82may be placed anywhere within contour support72so that mounting aperture82does not physically interfere with the stacking arrangements of plurality of IC dies62,64,66, and68. For example, mounting aperture82may be formed at the center of contour support72. In some examples, a component may extend through mounting aperture82to provide a thermal pathway for dissipating heat from stacked IC system60, to exert a compressive force on stacked IC system60in the direction substantially orthogonal (e.g., orthogonal or warty orthogonal) to substrate major surface71, or both.

In some examples stacked IC system60may include more or fewer IC dies62,64,66, and68than those illustrated inFIGS. 3A and 3B. For example, stacked IC system60may include a power of two (2n) number of IC dies, including for example, 28=256 dies, 29=512 dies, 210=1024 dies, or the like. Such pluralities of IC dies may be useful in certain applications such as in memory device applications. In some examples, IC dies62,64,66,68may be substantially the same size while in other examples the sizes of IC dies may vary.

Stacked IC system60may be formed using any one of a variety of techniques. In some examples, stacked IC system60may be formed is a sequential fashion on a tier-by-tier basis. For example,FIGS. 4-7are conceptual and schematic diagrams illustrating an example of a sequential build for forming stacked IC system60, withFIGS. 4A-7Ashowing conceptual and schematic top views andFIGS. 4B-7Bshowing conceptual and schematic side views of stacked IC system60at various stages of assembly. As shown inFIGS. 4A and 4B, stacked IC system60may be formed by first attaching first support frame87A of contour support72to substrate major surface71. First support frame87A includes a plurality of first lateral contact surfaces88A-88H that are substantially perpendicular (e.g., perpendicular or nearly perpendicular) to substrate major surface71. In some examples, first support frame87A may be prefabricated separately from substrate70and attached to substrate70via any applicable technique including, for example, an adhesive. Optional mounting aperture82, may be formed in sequence with the construction of stacked IC system60or alternatively may be etched or machined through contour support72and substrate70after contour support72has been substantially formed.

FIGS. 5A and 5Bshow IC dies62A-62D assembled on and attached to substrate major surface71. IC dies62A-62D include respective first die major surfaces63A-63D aligned substantially parallel to substrate major surface71. As shown, each IC die62is aligned so that two sides of each die abut respective lateral contact surfaces of the first lateral contact surfaces88of first support frame87A (e.g., two sides of IC die62A abut first lateral contact surfaces88E and88F, respectively). The combination of IC dies62and first support frame87A shown inFIGS. 5A and 5Bform first IC tier86A. Once the IC dies62have been incorporated into stacked IC system60, any desired electrical connections between the IC dies62and substrate70may be formed via, for example, wires78between IC bond pads, e.g.,76A, and substrate bond pads74located on first die major surfaces63and substrate major surface71, respectively. While for clarity purposes, only IC die62C is shown in FIGS.5A and5B as being electrically connected to substrate bond pads74, all IC dies62,64,66, and68incorporated into stacked system60may include such connections. IC dies62may be attached to substrate major surface71, e.g., using an adhesive, such as an epoxy.

FIGS. 6A and 6Bshow first support plate84A of contour support72being assembled on stacked IC system60. First support plate84A has a first support plate major surface85A aligned substantially parallel to substrate major surface71. As shown inFIG. 6A, in some examples, first support plate84A may partially cover each of IC dies62, but may leave respective portions of first die major surfaces63A-63D of IC dies62exposed. For example, first support plate84A may be sized to leave at least some IC bond pads76of IC dies62exposed. In some examples first support plate84A may be prefabricated and attached to tier86A using, for example, any adhesive available from a variety of suppliers that is compatible with stacked IC system60. In other examples, the support plate84A may be fabricated directly on the topside of tier86A using for example, mechanical attachment including fixturing such as with screws or other mechanical fasteners, bonding including chemical bonding or physical/mechanical bonding, a hybrid the techniques, or the like.

In some examples, first support plate84A may include at least one electrical trace80that electrically connects one or more IC dies62that are covered by first support plate84A using, for example, IC bond pads76F and76G of IC die62C. In some examples, the at least one electrical trace80may also be used to electrically connect IC dies of adjacent tiers, for example, one or more of IC dies62of tier86A may be electrically connected to one of more IC dies64of tier86B, which attaches to first support plate major surface85A. In some such examples, IC dies64may include a plurality of IC bond pads located on the lower surface of dies64(not shown) that attach to first support plate major surface85A and electrically communicate with electrical traces80in first support plate84A.

FIGS. 7A and 7Bshow stacked IC system60with the addition of second support frame87B including a plurality of second lateral contact surfaces89(only surfaces89A and89B are labeled) substantially perpendicular to substrate major surface71. IC dies64may be incorporated in second tier86B such that each IC die64A-64D is placed on first support plate major surface85A with two sides of each IC die64A-64D abutting respective second lateral contact surfaces89(e.g., respective sides of IC die64C abut second lateral contact surfaces89A and89B). The entire process with respect toFIGS. 4-7may then be continued until stacked IC system60contains the desired number of IC tiers86.

WhileFIGS. 4-7illustrate stacked IC system60being assembled on a tier-by-tier basis, system60may be formed using any applicable technique. For example, in some examples, stacked IC system60may be assembled by first forming contour support72including plurality of support frames87and plurality of support plates84. As described above, in some examples, support frames87and support plates84may be integrally formed as a unitary structure. In this manner, adjacent support plates84may define gaps for receiving the corresponding IC dies62,64,66, and68. The IC dies62,64,66, and68may then be inserted into the gaps and attached to corresponding support plates84using any applicable technique including, for example, backfilling of an adhesive, melting of an adhesive preform, ultraviolet (UV) curing of an adhesive, or the like.

FIG. 8is a flow diagram illustrating an example technique that may be used to form a stacked IC system of the disclosure, such as, for example, stacked IC system60ofFIGS. 3A and 3B. While the technique shown inFIG. 8is described with respect to stacked IC system60, in other examples, the technique may be used to form other stacked IC systems that include different configurations.

The technique illustrated inFIG. 8includes forming a contour support72including a first support frame87A, a support plate84A, and a second support frame87B (90). Support plate84A may include a lower support plate major surface83(FIG. 6B), and first support frame87A may be attached to lower support plate major surface83. First support frame74A may include at least one lateral contact surface, e.g.,88A, aligned substantially orthogonal (e.g., orthogonal or nearly orthogonal) to lower support plate major surface83. Second support frame87B may be attached to the opposite side of support plate84A from first support frame87A (e.g., second support frame87B attaches to first support plate major surface85A). Second support frame87B may include at least one second lateral contact surface, e.g.,89A, aligned substantially orthogonal to lower support plate major surface83. As discussed above, in some examples, contour support72may be formed in unison with the assembly of IC dies62,64,66, and68on a tier-by-tier basis. In other examples, contour support72may be formed as a unitary structure prior to incorporating IC dies62,64,66, and68in stacked IC system60.

The technique ofFIG. 8also may include attaching first support frame87A to substrate major surface71(92). In some examples, first support frame87A may be attached to substrate major surface71using an adhesive, solder, or another joining technique.

The technique ofFIG. 8further may include attaching at least a first IC die (e.g., one or more of IC dies62) to substrate major surface71(94). In some examples, as described above with respect toFIGS. 4-7, the at least a first IC die may be attached to substrate major surface71before support plate84A is attached to first support frame87A and the at least a first IC die. In other examples, support plate84A may be integral with first support frame87A or attached to first support frame87A before the at least a first IC die is attached to substrate major surface71, such that the at least a first IC die is inserted between substrate major surface71and support plate84A. At least one side of the at least a first IC die may abut a respective lateral contact surface of first support frame87A, such that first support frame87A affects the lateral positioning of the at least a first IC die. The at least a first IC die may be attached to substrate major surface71, support plate84A, or both using, for example, an adhesive.

The technique ofFIG. 8further may include attaching at least a second IC die (e.g., one or more of IC dies64) to support plate84A (94). The at least a second IC die may be attached to a side of support plate84A opposite of the at least a first IC die. At least one side (e.g., perimeter side) of the at least a second IC die may abut a respective lateral contact surface of second lateral contact surfaces89of second support frame87B, such that second support frame87B affects the lateral positioning of the at least a second IC die, and at least one side of the at least a second IC die is laterally offset from at least one side of the at least a first IC die. The at least a second IC die may be attached to support plate84A using, for example, an adhesive.