Information processing apparatus, memory controller, and memory control method

An information processing apparatus includes: a memory device configured to store data; an arithmetic processor configured to issue a request to be transmitted to the memory device; and a memory controller including: a buffer configured to store one or more unselected requests that are issued by the arithmetic processing processor and are not selected; a history register configured to hold one or more addresses for one or more transmitted requests that have been transmitted to the memory device; and a selection unit configured to select, from the one or more unselected requests stored in the buffer, a target request to be transmitted to the memory device based on the one or more addresses stored in the history register and transmit the target request to the memory device.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2015-101267, filed on May 18, 2015, the entire contents of which are incorporated herein by reference.

FIELD

The embodiment discussed herein is related to an information processing apparatus, a memory controller, and a memory control method.

BACKGROUND

With the advances in the fractionalization of manufacturing processes of processors included in information processing apparatuses such as high performance computers (HPCs), servers, personal computers (PCs), and mobile phones, and the computation speed per processor has been improved. This involves desire to increase the capacity and band of a main memory.

SUMMARY

According to an aspect of the embodiments, an information processing apparatus includes: a memory device configured to store data; an arithmetic processor configured to issue a request to be transmitted to the memory device; and a memory controller including: a buffer configured to store one or more unselected requests that are issued by the arithmetic processing processor and are not selected; a history register configured to hold one or more addresses for one or more transmitted requests that have been transmitted to the memory device; and a selection unit configured to select, from the one or more unselected requests stored in the buffer, a target request to be transmitted to the memory device based on the one or more addresses stored in the history register and transmit the target request to the memory device.

DESCRIPTION OF EMBODIMENT

For example, a dynamic random access memory (DRAM) in the form of a HMC including a memory controller incorporated therein is provided as a memory device usable instead of a dual inline memory module (DIMM).

The HMC has packaging density that has been improved by using a DRAM stacking technology, and a large capacity has thus been achieved. The HMC includes a plurality of memory controllers incorporated therein, and data is transferred in a wide band by high-speed serial communication to an interface between a central processing unit (CPU) and memory in the HMC.

The HMC includes a plurality of (for example, two, four, or eight) interfaces (I/Fs) connected to a host and a plurality of quadrants respectively assigned to the I/Fs based on addresses. Each quadrant includes a plurality of vaults, and each vault includes a vault controller and a plurality of memory banks. For example, the vault is a unit memory including a plurality of memory banks and a vault controller. The memory banks are a plurality of stacked memories connected using through silicon vias (TSVs), and the vault controller is a memory controller that controls the memory banks.

The I/Fs of the HMC each include an input buffer that stores packets received from the host. After the packets are each transmitted from the input buffer to the corresponding vault controller, as many token packets as the transmitted packets are transferred to the host. The host includes a token register and transmits, to the HMC, packets, the number of which is within the register value of the token register. The host subtracts the number of transmitted packets from the value of the token register and adds, to the value of the token register, the number of packets indicated by the token packets transferred from the HMC.

History information regarding noncontinuous access based on noncontinuous addresses of pieces of data accessed by a processor is stored, and future noncontinuous access is predicted based on the history information regarding the addresses of the pieces of data accessed in the past. For example, a read address is output based on predicting noncontinuous access, and data corresponding to the read address is read from the memory.

For example, in a case where an input-output device having issued a memory read request tends to access continuous memory areas, data in a memory area contiguous with a memory area designated in accordance with the memory read request is, in advance, read out in addition to data in the designated memory area.

For example, consider a case where packets each including a request from the host to the HMC are transmitted. If all of the I/Fs of the HMC are connected to the host, the packets are each distributed (transmitted), based on the address for the request, to a corresponding one of the I/Fs that directly belongs to the quadrant including a memory bank to be accessed. For example, only some of the I/Fs are connected to the host, the packets are transmitted to the connected I/Fs, and memory banks of the respective designated addresses are accessed through a switch in the HMC.

If the addresses of the memories to be accessed are evenly distributed to the plurality of vaults, the input buffer is not filled with the packets. For example, if one quadrant, one vault, or one memory bank in one vault is repeatedly accessed, the process speed is decreased, and free space of the input buffer is reduced. The host is thus no longer able to transmit a packet, and the throughput may be deteriorated.

FIG. 1illustrates an example of an information processing apparatus.

An information processing apparatus101includes a processor201, a memory controller301, and a HMC401. The information processing apparatus101may be a computer such as a server or a PC.

The processor201issues requests to the HMC401. The processor201may be, for example, a CPU.

The memory controller301receives the requests from the processor201and transmits the received requests to the HMC401in order in accordance with a predetermined rule.

The memory controller301includes a first-in first-out (FIFO)311, a request controller321, a request selector331, a request issuance history register341, a token register351, a link master361, and a link slave371.

The FIFO311stores a request queue in which the requests issued by the processor201are arranged in order of issuance. The FIFO311may be, for example, a shift register. The FIFO311includes flip-flops312-m(m ranges from 0 to 7). The FIFO311may be an example of a buffer.

The flip-flops312-mare connected in series. The flip-flops312-mstore the requests. The flip-flops312-1to312-7each output the corresponding stored request to a corresponding one of the flip-flops312-0to312-6subsequent thereto. The flip-flops312-meach output the corresponding stored request to the request selector331. The request output to the request selector331includes information indicating what number (a queue number) the request is in the request queue, for example, information indicating which one of the flip-flops312-mstores the request. Hereinafter, the request stored in the corresponding flip-flop312-mmay be denoted by Qm.

The request controller321controls reading and writing of data from and to requests stored in the flip-flops312-mand shifting of the requests. The request controller321receives an issued request from the request selector331and shifts one or more requests in the FIFO311based on information included in the issued request, the information indicating which one of requests (a queue number) in the request queue is selected, the information, for example, indicating the flip-flop312-mthat stores the selected request. For example, the request controller321holds one or more requests older than the selected request and shifts one or more requests more recent than the selected request by one.

The request selector331selects, from the request queue, one of the requests that is to be issued. The request selector331transmits the request to a link master361.

The request issuance history register341stores a predetermined number of most recent requests in order of selection (output) performed by the request selector331. For example, the request issuance history register341stores addresses for the predetermined number of most recent requests in order of selection performed by the request selector331.

The token register351stores the number of packets transmittable by the memory controller301. The number of packets transmittable by the memory controller301may be, for example, the number of packets receivable by the HMC401. The token register351receives the number of transmitted packets from the link master361and subtracts the number of transmitted packets from the number of transmittable packets. The token register351receives token packets from the link slave371and adds the number of packets indicated by the token packets to the number of transmittable packets.

The link master361generates a packet in such a manner as to add a header and a cyclic redundancy check code to the request received from the request selector331and transmits the packet to the HMC401. The link master361generates a packet related to the received request and transmits the packet to the HMC401. For example, if the request is a read command for requesting readout of data, a packet including the read command is generated and transmitted. For example, if the request is a write command for requesting writing of data, and if the data to be written is large, the written data is divided into pieces of data, and a plurality of packets are generated and transmitted, the plurality of packets being a packet including the write command and at least one of the pieces of divided written data and at least one packet including the remaining one or more pieces of divided written data. The link master361notifies the token register351of the number of transmitted packets (the number of packets).

The link slave371receives each token packet from the HMC401and transmits the token packet to the token register351. The link slave371receives a response including data read out from the HMC401and transmits the response to the processor201.

The HMC401is a memory device that stores data. The HMC401reads or writes data in response to the received request.

FIG. 2illustrates an example of a HMC. The HMC401includes link interface controllers411-i(i ranges from 1 to 4), a switch421, and quadrants431-i.

The link interface controllers411-iare connected to the switch421. When communicating with the quadrants431-i, the link interface controllers411-iperform the communication through the switch421.

Each link interface controller411-iincludes a link slave412-i, an input buffer413-i, and a link master414-i.

The switch421connects the link interface controllers411-iand the quadrants431-ito each other. Communication is performed between any one of the link interface controllers411-iand any one of the quadrants431-ithrough the switch421. The switch421may be, for example, a crossbar switch.

Each quadrant431-iincludes vaults432-i-j(j ranges from 1 to 4). The quadrant431-imay be a group of the vaults432-i-j, the group being associated with the corresponding link interface controller411-i. The link interface controllers411-1to411-4are respectively associated with the quadrants431-1to431-4. Each quadrant431-iassociated with a corresponding one of the link interface controllers411-imay be referred to as the quadrant431-idirectly belonging to the link interface controller411-i. Each link interface controller411-iaccesses the corresponding quadrant431-idirectly belonging thereto faster than a quadrant431-ithat does not directly belong to the link interface controller411-i. The quadrant431-imay be an example of the memory group. Hereinafter, the vaults432-1-1to432-4-4may be respectively referred to as vaults0to15.

Each vault432-i-jincludes a vault controller433-i-jand a memory bank group434-i-j. Each vault432-i-jis assigned an address (vault address). The vault432-i-jmay be an example of a memory unit.

The vault controller433-i-jcontrols the memory bank group434-i-j. For example, the vault controller433-i-jcontrols reading and writing of data from and to a memory bank in the memory bank group434-i-j.

The memory bank group434-i-jis a group of memory banks. The memory bank group434-i-jmay have 16 memory banks0to15.

FIG. 3illustrates an example of a request issuance history register. The request issuance history register341includes FIFOs342and345, a vault address counter344, and a bank address counter347.

The FIFO342stores, in order of output, addresses (hereinafter, issued-request vault addresses) of the respective vaults432-i-jincluded in the most recent requests output by the request selector331. The FIFO342includes flip-flops343-n(n ranges from 0 to 14). For example, the FIFO342stores 15 issued-request vault addresses.

The flip-flop343-14receives a request output from the request selector331and stores therein the issued-request vault address included in the received request. After the request selector331outputs the request, the flip-flops343-1to343-14each output an issued-request vault address stored therein to a corresponding one of the flip-flops343-0to343-13subsequent thereto. The flip-flops343-0to343-13store therein the issued-request vault addresses input from the flip-flops343-1to343-14prior thereto. As described above, when the request selector331issues a new request, pieces of data (issued-request vault addresses) in the FIFO342are shifted, and the FIFO342stores therein the 15 most recent issued-request vault addresses in order of the issuance. The number of the flip-flops343-nis not limited to 15 and may be any number. The flip-flops343-ntransmit the stored issued-request vault addresses to the vault address counter344.

The vault address counter344receives the issued-request vault addresses input from the flip-flops343-nand counts the addresses of each of the vaults0to15indicated by the issued-request vault addresses. The vault address counter344outputs, to the request selector331, the count of the addresses of each of the vaults0to15as the number of requests to the corresponding one of the vaults0to15.

The FIFO345, in order of issuance, stores therein the addresses of the memory banks included in the most recent requests issued by the request selector331(hereinafter, issued-request bank addresses). The FIFO345includes flip-flops346-n(n ranges from 0 to 14). For example, the FIFO342stores therein 15 issued-request bank addresses.

The flip-flop346-14receives a request issued by the request selector331and stores therein the issued-request bank address included in the received request. After the request selector331issues the request, the flip-flops346-1to346-14each output the issued-request bank address stored therein to a corresponding one of the flip-flops346-0to346-13subsequent thereto. The flip-flops346-0to346-13store therein the issued-request bank addresses input from the flip-flops346-1to346-14prior thereto. As described above, when the request selector331issues a new request, pieces of data in the FIFO345(issued-request bank addresses) are shifted, and the FIFO345stores therein the 15 most recent issued-request bank addresses in order of the issuance. The number of the flip-flops346-nis not limited to 15 and may be any number. The flip-flops346-ntransmit the stored issued-request bank addresses to the bank address counter347.

The bank address counter347receives the issued-request bank addresses input from the flip-flops346-nand counts the addresses of each of the memory banks0to15indicated by the issued-request bank addresses. The bank address counter347outputs, to the request selector331, the count of the addresses of each of the banks0to15as the number of requests to the corresponding one of the banks0to15.

FIG. 4illustrates an example of a request selector. The request selector331includes a token threshold register332, a comparator333, a request selection circuit334, and selectors335and336.

The token threshold register332stores therein a threshold. A value may be set in advance as the threshold.

The comparator333compares the value stored in the token register351, for example, the number of packets transmittable by the memory controller301with the threshold stored in the token threshold register332and transmits a comparison result to the selector336. For example, if the value stored in the token register351is equal to or higher than the threshold, the comparison result may be L (=0). If the value stored in the token register351is lower than the threshold, the comparison result may be H (=1).

The request selection circuit334calculates a weighting of each of requests Q0to Q7based on the vault address and the bank address included in the corresponding request and based on the number of requests to each of the vaults0to15and the number of requests to each of the banks0to15that are input from the request issuance history register341. For example, the weighting may be expressed in nine bits.

The weightings of requests may be calculated in the following manner, for example. The request selection circuit334judges whether the requests stored in the request issuance history register341include a request having been transmitted to a quadrant431ithat is the same as the quadrant431ito which a request is to be transmitted. The quadrant431ito which the request is to be transmitted may be judged based on the vault address. Whether the requests stored in the request issuance history register341include a request having been transmitted to a specific quadrant431imay be judged based on the number of requests to the corresponding one of the vaults0to15. For example, if the number of requests to the vault0is equal to or higher than 1, it may be judged that the requests stored in the request issuance history register341include a request having been transmitted to the quadrant431-1. If the requests stored in the request issuance history register341include a request having been transmitted to a quadrant431ithat is the same as the quadrant431ito which a request is to be transmitted, the request selection circuit334sets the most significant bit of the weighting to 1. If the requests stored in the request issuance history register341do not include a request having been transmitted to a quadrant431ithat is the same as the quadrant431ito which a request is to be transmitted, the request selection circuit334sets the most significant bit of the weighting to 0. The most significant bit of the weighting of a request indicates whether at least one of requests stored in a command issuance history register has been transmitted to the quadrant431ito which the weighting target request is to be transmitted. For example, the weighting of a request may be expressed in 12 bits, and the number of times at least one of the requests stored in the command issuance history register has been transmitted to the quadrant to which the weighting target request is to be transmitted may be set in the higher first to fourth bits in the weighting (the lower ninth to 12th bits).

The request selection circuit334sets, in the lower fifth to eighth bits of the weighting of a request, the number of requests having been transmitted to the vault having the same address as the vault address of the request. The lower fifth to eighth bits of the weighting of a request indicate the number of times at least one of the requests stored in the command issuance history register has been transmitted to the vault432-i-jto which the weighting target request is to be transmitted.

The request selection circuit334sets, in the lower first to fourth bits of the weighting, the number of requests having been transmitted to the bank having the same address as the bank address of the request.

The request selection circuit334selects the request that has the lowest weighting. Accordingly, a request to be transmitted to the quadrant to which at least one of the requests stored in the command issuance history register has been transmitted least frequently is selected, or a request to be transmitted to a quadrant to which a request has not been transmitted is selected. If there are multiple requests to be transmitted to the quadrant to which at least one of the requests has been transmitted least frequently or multiple requests to be transmitted to a quadrant to which a request has not been transmitted, one of the requests that is to be transmitted to the vault432i-jto which at least one of the requests stored in the command issuance history register has been transmitted least frequently is selected. If there are multiple requests to be transmitted to the vault432-i-jto which at least one of the requests stored in the command issuance history register has been transmitted least frequently, one of the requests that is to be transmitted to the memory bank to which at least one of the requests stored in the command issuance history register has been transmitted least frequently is selected.

The request selection circuit334transmits a selection signal indicating the selected request to the selector335.

The number of requests to a vault and the number of requests to a memory bank that are each expressed in four bits are used as the weighting, but whether the same vault is present and whether the same memory bank is present may each be expressed in one bit. This may lead to circuit scale reduction.

The selector335receives the requests Q0to Q7and the selection signal. The selector335selects one of the requests Q0to Q7that is indicated by the received selection signal and outputs the request to the selector336.

Based on the comparison result, the selector336selects the request Q0or the request output from the selector335and outputs the selected request. If the comparison result is L, for example, if the value stored in the token register351is equal to or higher than the threshold, the selector336selects and outputs the request Q0. If the comparison result is H, for example, if the value stored in the token register351is lower than the threshold, the selector336selects and outputs the request output from the selector335. The output request may also be referred to as an issued request.

FIG. 5illustrates an example of a request selection process. In Operation S501, the comparator333compares the value stored in the token register351, for example, the number of packets transmittable by the memory controller301with the threshold stored in the token threshold register332and transmits the comparison result to the selector336. If the value stored in the token register351is equal to or higher than the threshold, the control proceeds to Operation S502. If the value stored in the token register351is lower than the threshold, the control proceeds to Operation S503.

In Operation S502, the selector336selects the first request Q0in the request queue and outputs the request Q0to the link master361.

In Operation S503, the request selection circuit334calculates the weightings of the requests Q0to Q7based on the addresses for the requests Q0to Q7, the number of requests to each of the vaults0to f in the history, and the number of requests to each of the memory banks0to f in the history.

In Operation S504, the request selection circuit334outputs a selection signal indicating a request corresponding to the lowest weighting to the selector335. The selector335selects one of the requests Q0to Q7that is indicated by the selection signal and outputs the selected request to the selector336.

In Operation S505, the selector336selects the request input from the selector335and outputs the request to the link master361. The link master361generates a packet including the request and transmits the packet to the HMC401.

FIG. 6illustrates an example of a timing chart of a memory controller. In Cycle C1, requests Q0to Q5in the request queue stored in the FIFO311are respectively requests R0to R5. The processor201issues a request R6. The value stored in the token register351is equal to or higher than the threshold, a comparison result indicating whether the value stored in the token register351is equal to or higher than the threshold is not asserted, and the first request R0is selected and output.

In Cycle C2, the processor201issues a request R7. The requests R0to R5stored in the FIFO311are shifted by one. Accordingly, the request R0is deleted, and the requests Q0to Q5are respectively the requests R1to R4. The request R6is stored at the end of the request queue, and the request Q5is the request R6. The comparison result is not asserted, and the first request R1is selected and output.

In Cycle C3, the requests R1to R6stored in the FIFO311are shifted by one. Accordingly, the request R1is deleted, and the requests Q0to Q5are respectively the requests R2to R6. The request R7is stored at the end of the request queue, and Q5is the request R7. The value stored in the token register351becomes lower than the threshold, and the comparison result is asserted. The request selection circuit334selects and outputs the request Q3that is the request R5.

In Cycle C4, among the requests R2to R7stored in the FIFO311, the requests R2to R4prior to (older than) the request R5selected in Cycle C3are held, and the requests R6and R7subsequent to (more recent than) the request R5are shifted by one. Accordingly, the request R1is deleted, and the requests Q0to Q4are respectively the requests R2to R4, R6, and R7. The comparison result has been asserted. The request selection circuit334selects and outputs the request Q3that is the request R6.

In Cycle C5, the processor201issues a request R8. Among the requests R2to R4, R6, and R7stored in the FIFO311, the requests R2to R4prior to the request R6selected in Cycle C4are held, and the request R7subsequent to the request R6is shifted by one. Accordingly, the request R6is deleted, and the requests Q0to Q3are respectively the requests R2to R4, and R7. The value stored in the token register351becomes equal to or higher than the threshold, the comparison result is negated, and the request R2is selected and output.

In Cycle C6, the requests R2to R4and R7stored in the FIFO311are shifted by one. Accordingly, the request R2is deleted, and the requests Q0to Q2are respectively the requests R3, R4, and R7. The request R8is stored at the end of the request queue, and the request Q3is thus the request R8. The comparison result is not asserted, and the first request R3is selected and output.

With the information processing apparatus, a request to be transmitted to a quadrant, a vault, or a memory bank to which at least one of requests in the past has been transmitted less frequently is selected based on the history of the addresses for the requests, and the request is transmitted. Accordingly, access events to be made to the same quadrant, the same vault, or the same memory bank are distributed, and the throughput may be enhanced.