Reloadable word recognizer for logic analyzer

A test and measurement instrument such as a Logic Analyzer, or the like, has at least one Reloadable Word Recognizer whose reference value can be loaded by a trigger machine with a current acquired data sample while data is being acquired. In a second embodiment useful for performing memory testing, the reloadable word recognizer is used in cooperation with two conventional word recognizers. In a third embodiment, a delay unit is employed to provide delayed input data words as reference words. In a fourth embodiment, an offset register and adder are used to modify the input data words before storing them. A fifth embodiment provides for substantially immediate use of base addresses of relocatable subroutines and stack-based variables recovered from a data stream acquired from a system under test.

FIELD OF THE INVENTION

The subject invention generally concerns the field of word recognizers for use in test and measurement instruments, such as logic analyzers, and the like, and specifically concerns word recognizer that may be reloaded during an acquisition of data.

BACKGROUND OF THE INVENTION

A logic analyzer is a test and measurement instrument having multiple input channels for acquiring digital data words for processing and display. Logic analyzers contain Word Recognizers, which are programmed with a reference value for comparison with incoming acquired data. Because the user wishes to trigger on a condition in which the reference value matches the value of the incoming data, the “reference value” of the Word Recognizer is preprogrammed before data acquisition is begun, and is not changed while data is being acquired. It is noted that Word Recognizers also have the ability to mask, or disable selected channels, which allow these channels to be ignored while comparing the acquired data and reference data.

However, currently available Word Recognizers cannot provide a solution to the following problem. In a Random Access Memory (RAM) diagnostic routine, a data pattern is written to all locations of the RAM, and then the data is read from each of the locations. The routine then reports the results (i.e. whether the RAM passed the check) and the process is repeated with the next pattern. If an error is detected, it is unknown whether the problem occurred when the data was written to the RAM, or when the data was read from the RAM. Because the RAM has been overwritten, the RAM cannot be examined to determine if it contains the correct value. One would like to write a trigger program to verify that data written to the RAM is the same as what is read back from the RAM and to trigger the Logic Analyzer when the data is not the same. With current logic analyzers this is not possible because the data pattern is changing, which means it is not possible to preprogram the “Reference Value” of the Word Recognizer with a meaningful value.

SUMMARY OF THE INVENTION

The subject invention concerns a test and measurement instrument such as a logic analyzer, or the like, having at least one Reloadable Word Recognizer whose reference value can be loaded by a trigger machine with a current acquired data sample while data is being acquired. In a second embodiment useful for performing memory testing, the reloadable word recognizer is used in cooperation with two conventional word recognizers. In a third embodiment, a delay unit is employed to provide delayed input data words as reference words. In a fourth embodiment, an offset register and adder are used to modify the data words before storing them. A fifth embodiment provides for substantially immediate use of base addresses of relocatable subroutines and stack-based variables recovered from a data stream acquired from a system under test.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Referring toFIG. 1, those portions of a logic analyzer that are pertinent to the subject invention are shown and generally designated100. An Input Channels block110includes acquisition circuitry for acquiring digital data from a circuit under test via a plurality of input data channels. The data acquired from the user's system is presented to an Event Circuit120. Event Circuit120contains Word Recognizers, Range Recognizers, Transition Detectors, etc. For purposes of explanation of the subject invention, only the Word Recognizers will be discussed below.

An output signal of Event Circuit120is applied to a Trigger Machine (or Trigger Circuit)130. Trigger Circuit130determines when to trigger, store, etc, and when to load a Reloadable Word Recognizer (to be described below with reference toFIG. 2) with a current data sample. When appropriate, Trigger Circuit130generates a Reload Signal for application to Event Circuit120. A Delay block140delays the incoming data to match the delay through Event Circuit120and Trigger Circuit130. This is necessary so that data is time-aligned with the output signal of Trigger Circuit130to ensure proper data storage or proper reloading of the Word Recognizer. Trigger machine circuitry for performing further functions is represented by block190.

FIG. 2shows a block diagram of at least some of the elements, generally designated200, which reside within Event Circuit120ofFIG. 1. The elements200include a first Word Recognizer comparison unit (Word REC1)210, a second Word Recognizer comparison unit (Word REC2)220, a preprogrammable reference block215, and a reprogammable reference block225. Word REC1210is a conventional Word Recognizer comparison unit as known from the prior art. As such, incoming data received via Input Channels block110are compared against a value preprogrammed and stored in reference block215. A predetermined “Reference Value” is loaded into reference block215before a data acquisition is begun. Thereafter, this preprogrammed reference value remains unchanged during the entire data acquisition. The output of Word Rec1210is the result of a comparison between its preprogrammed reference value and the incoming data.

In contrast, Word Rec2220is a reloadable Word Recognizer. Like Word Rec1210, Word REC2220compares incoming data against a value held in its respective Reference Block225. However, the respective “Reference Value” of each of reference blocks215and225is different from the other, except for cases where the data values coincidentally happen to be the same.

Operation of the subject invention is described with reference toFIGS. 1 and 2. In operation, incoming data is delayed in delay unit140while Trigger Circuit130evaluates the result of the comparison of reference data and current sample data within Event circuit120. If the results match the criteria that the Trigger Circuit is programmed for, then a reload strobe signal is generated and applied to Event circuit120. This reload strobe will cause the delayed incoming data to be loaded into Reference block225. The Reloadable Word Recognizer comparison unit, Word Rec2220, can be reloaded as often as desired during an acquisition.

With respect to the problem set forth above with respect to the RAM diagnostics routine, such problem is solved by use of another embodiment300of the subject invention, employing a Reloadable Word Recognizer320with associated Reference Block325and two conventional Word Recognizers310and350, as shown inFIG. 3. Similarly numbered elements ofFIGS. 2 and 3serve the same function and need not be described again. A conventional Word Recognizer (WR0)310with associated Reference Block315is preprogrammed to generate a “match” signal when a “write data to memory” operation occurs at a specific RAM address. Another conventional Word Recognizer (WR1)350with associated Reference Block355is preprogrammed to generate a “match” signal when a “read data from memory” operation occurs from this same address. Only the data channels (in contrast to address channels) are enabled on Reloadable Word Recognizer (RWR)320. A “trigger program” (i.e., a program for triggering the logic analyzer) running on Trigger machine130generates a Reload Strobe when the result of a comparison within word recognizer WR0310is true (i.e., matches). The trigger program wilt-produce produces a trigger signal when the result of a comparison within word recognizer WR1350is true AND when the result of a comparison within word recognizer RWR320is false.

In operation, when a write to specified RAM address occurs, the output of word recognizer WR0310becomes true and causes Reloadable Word Recognizer320to be loaded with the data value that was written to this specific RAM address. Later, when a read from memory operation occurs from this same address the output of word recognizer WR1350becomes true. If the output of Reloadable Word Recognizer RWR320is true, then nothing happens until the next read or write operation to this address. When the output of Reloadable Word Recognizer RWR320goes false, trigger machine130triggers. Note that as long as all outputs of the word recognizers are true, then Reloadable Word Recognizer RWR320can be reloaded with a new value over and over again.

There are two enhancements to the above-described invention that are deemed to lie within the bounds of the invention.FIG. 4shows one enhancement400with all of the elements410,420,430,440,490that correspond respectively to elements110,120,130,140190ofFIG. 1and further includes a Multiplexer (MUX)450positioned between Delay Circuit440and Event Circuit420. Channels could be “swizzled” before becoming a reference value. This allows addressing information present on the data bus to be mapped over to address channels for comparison purposes.

The second enhancement500is shown inFIG. 5that includes all of the elements510,520,530,540,590that correspond respectively to elements110,120,130,140190ofFIG. 1and further includes an offset register570and adder unit560, which reside between Delay Circuit540and Event Circuit520. The value n (any integer number) in offset register570is loaded before data is acquired, and is added to the delayed data before being reloaded as the reference value. This enhancement is quite useful. For example, assume that the value stored in the offset register is equal to5. In that case, one may track every 5th line in a subroutine. Moreover, if one changes the address of a subroutine, the delayed data value has the new base address information when the reload operation occurs.

FIG. 6shows a simplified block diagram of a front end of a logic analyzer600according to yet another embodiment of the invention. A Probe610acquires digital data words from a system under test, and applies them to a conventional data pipeline having a plurality of flip-flop (F/F) circuits, explicitly represented by flip-flops620a,620b,620cand implicitly represented by a dotted line. The pipeline ultimately provides the acquired data to a memory630. A Clock State Machine640provides clock signals to the pipeline flip-flops via a clock delay chain comprising a plurality of delay stages, represented by delay stages650a,650b.

A Word Recognizer Reload State Machine660monitors the pipeline bus for the occurrence of a predetermined data word. Upon detection of the predetermined data word at the output of flip-flop620b, Word Recognizer Reload State Machine660acquires a reference word and loads it into a Reloadable Base/Offset Word Recognizer670. In this way, Reloadable Base/Offset Word Recognizer670can use the new reference word substantially immediately (i.e., as early as the next clock cycle). Reloadable Base/Offset Word Recognizer670applies data word detection signals to Trigger Machine680in the conventional fashion. The combination of Word Recognizer Reload State Machine660and Reloadable Base/Offset Word Recognizer670produces a “real time” “hardware” relocation of all word recognizer values.

It is important to note that the arrangement ofFIG. 6is particularly useful when attempting to track relocatable code elements such as subroutines and stack-based variables. This has heretofore been a vexing problem because one knows only the relative addresses of the variables and code until the stack frame is built and the code is loaded at run time. In operation, Word Recognizer Reload State Machine660searches for code that allocates and relocates software routines (i.e., a reload address/data pattern). When found, a new base displacement is acquired from the pipeline and supplied to Reloadable Base/Offset Word Recognizer670. Thus, the base address, just found by the Reload State Machine660, and an offset, taken from the compiler, combine in the base-offset word recognizer670to form an absolute address immediately available for use in tracking the relocatable code of the system under test. Proper sizing of the number of stages in the data shift register pipeline620guarantees time-alignment of the base-offset word recognizer search and the data being searched which results in zero-latency between the reload and search.

Although a hardware environment was used to describe the subject invention, one skilled in the art will realize that the hardware maybe performed by software, or by a combination of hardware and software, and all such modifications are deemed to lie within the scope of the following claims.