SEMICONDUCTOR PACKAGE

The reliability of stacked semiconductor packages may be improved via a semiconductor package including a first semiconductor chip including through silicon vias (TSVs) with respective upper conductive pads electrically connected to the TSVs, a second semiconductor chip on the first semiconductor chip with lower conductive pads on a lower surface of the second semiconductor chip, conductive bumps between the upper conductive pads and the lower conductive pads, and an interlayer adhesive layer between the first semiconductor chip and the second semiconductor chip. An interlayer space is between the first semiconductor chip and the second semiconductor chip and overlaps the first semiconductor chip and the second semiconductor chip in a vertical direction. The encapsulant extends into the interlayer space.

CROSS-REFERENCE TO RELATED APPLICATION

BACKGROUND

The inventive concept relates to a semiconductor package.

With the development of the electronics industry and increasing user demand, electronic devices are more compact and lighter, and semiconductor packages used in the electronic devices are required to be compact and light or less weight and have high performance and large capacity. To realize a smaller size, less weight, high performance, and large capacity, semiconductor chips including through silicon vias (TSVs) and a semiconductor package in which the semiconductor chips are stacked are being continuously researched and developed. In the semiconductor package in which the semiconductor chips are stacked, the reliability of the stacked semiconductor chips is required.

SUMMARY

The inventive concept relates to a semiconductor package in which reliability between stacked semiconductor chips is improved.

The objective of the inventive concept is not limited to the above described ones, and other objectives that are not mentioned will be clearly understood by those skilled in the art from the following description.

A semiconductor package includes a first semiconductor chip including through silicon vias (TSVs), where respective upper conductive pads are electrically connected to the TSVs and are on an upper surface of the first semiconductor chip, a second semiconductor chip on the first semiconductor chip, with lower conductive pads are on a lower surface of the second semiconductor chip, conductive bumps between the upper conductive pads and the lower conductive pads, an interlayer adhesive layer between the first semiconductor chip and the second semiconductor chip, and an encapsulant on a side surface of the second semiconductor chip. An interlayer space is between the first semiconductor chip and the second semiconductor chip and overlaps the first semiconductor chip and the second semiconductor chip in a vertical direction that is perpendicular to the upper and lower surfaces of both the first semiconductor chip and the second semiconductor chip. The encapsulant extends into the interlayer space.

A semiconductor package includes a plurality of semiconductor chips including through silicon vias (TSVs), where the plurality of semiconductor chips are stacked on one another, conductive pads on upper surfaces of the plurality of semiconductor chips and lower surfaces of the plurality of semiconductor chips, conductive bumps electrically connected to the conductive pads, an interlayer adhesive layer between the plurality of semiconductor chips, and an encapsulant on side surfaces of the plurality of semiconductor chips. The interlayer adhesive layer is in a first portion of an interlayer space that is between adjacent semiconductor chips among the plurality of semiconductor chips. The interlayer space overlaps the adjacent semiconductor chips in a vertical direction that is perpendicular to a direction in which the plurality of semiconductor chips are stacked. The encapsulant extends into the interlayer space.

A semiconductor package includes a plurality of semiconductor chips including through silicon vias (TSVs), conductive pads on upper surfaces of the plurality of semiconductor chips and lower surfaces of the plurality of semiconductor chips, conductive bumps electrically connected to the conductive pads, an interlayer adhesive layer between the plurality of semiconductor chips, an encapsulant on side surfaces of the plurality of semiconductor chips, and an upper semiconductor chip on the plurality of semiconductor chips, electrically connected to the plurality of semiconductor chips, and having a thickness greater than a thickness of each of the semiconductor chips. An interlayer space is between two adjacent semiconductor chips among the plurality of semiconductor chips and overlaps the two adjacent semiconductor chips in a vertical direction that is perpendicular to the plurality of stacked semiconductor chips. The interlayer adhesive layer is in a first portion of the interlayer space, and the encapsulant extends into a corner of the interlayer space and is in a second portion of the interlayer space that is free of the interlayer adhesive layer.

DETAILED DESCRIPTION

Embodiments of the inventive concept are provided to fully explain the inventive concept to those of ordinary skill in the art, the following embodiments may be modified in many different forms, and the scope of the inventive concept is not limited to the following embodiments. Rather, these embodiments are provided so that the inventive concept will be thorough and complete, and will fully convey the concept of the inventive concept to those of skilled in the art.

After a front-end process where circuits are formed on a wafer, semiconductor chips undergo a back-end process consisting of a packaging process and a test. Although micro electric circuits are integrated on a semiconductor chip, it may be difficult to perform the role of a semiconductor by the semiconductor chip alone. A packaging process connects a chip electrically to the outside so that the chip may function properly and protect the chip from the external environment. In addition, packaging allows efficient dissipation of heat emitted by semiconductors.

A semiconductor package may perform roles including mechanical protection, electrical connection, mechanical connection, and thermal dissipation. In other words, semiconductor chips may be wrapped with a packaging material, such as an epoxy molding compound (EMC), to be protected from external mechanical and chemical impacts. The packaging may physically or electrically connect the semiconductor chips to a system to supply power to operate the semiconductor chips. In addition, the packaging ensures input and output of signals to allow the semiconductor chips to perform desired functions, and allows dissipation of heat generated during operation of semiconductor products.

Methods of packaging semiconductors may be classified into conventional packaging where a packaging process is applied to individual chips separated from a wafer, and wafer-level packaging (WLP) where part or all of the process is carried out at the wafer level and subsequently a wafer is cut into single pieces.

The early packaging technology is a lead frame method that connects chips to pads by using gold wires. However, with the improvement in the device performance, a lead frame structure has faced its limit, and accordingly, a fine-pitch ball grid array (FB GA) based on a micropatterned substrate is applied. The conventional packaging may stack a number of chips in a package and thus may be mainly applied to NAND or mobile dynamic random access memory (DRAM) putting emphasis on high capacity.

In order to meet requirements of memory products, the conventional packaging as an existing traditional method has been developed, and at the same time, the WLP as a new method is introduced. The WLP is technology suitable for realizing high-performance products and packaging in approximately the same size as the chip is possible. Therefore, the size of finished semiconductor products may be reduced or minimized, and the cost may be reduced because materials, such as substrates or wires, are not included. The WLP process may be utilized for products, such as high bandwidth memory (HBM) or computing DRAM, which requires high capacity and/or high density. HBM is a 3D-type memory semiconductor in which several DRAMs are vertically connected. A plurality of semiconductor chips may be cumulatively stacked in a semiconductor package including HBM. Since it is necessary to improve the reliability of the stacked semiconductor chips, a semiconductor package1according to the inventive concept is described in detail with reference to the following drawings.

FIG.1is a side cross-sectional view for explaining the semiconductor package1according to some embodiments.

Referring toFIG.1, the semiconductor package1may include a plurality of semiconductor chips stacked in a vertical direction (a Z-axis direction). For example, the semiconductor package1may include a lower semiconductor chip100, a first semiconductor chip200, a second semiconductor chip210, a third semiconductor chip220, and an upper semiconductor chip300, which are stacked in the vertical direction.

For example, a horizontal cross-sectional area of the lower semiconductor chip100may be greater than a horizontal cross-sectional area of each of the first to third semiconductor chips200,210, and220and/or the upper semiconductor chip300. The horizontal cross-sectional areas of the first to third semiconductor chips200,210, and220and the upper semiconductor chip300may be substantially the same, according to some embodiments. As illustrated inFIG.1, the first to third semiconductor chips200,210, and220and the upper semiconductor chip300may overlap the lower semiconductor chip100in the vertical direction.

In some embodiments, the lower semiconductor chip100, the first to third semiconductor chips200,210, and220, and the upper semiconductor chip300may be the same type of semiconductor chip. For example, the lower semiconductor chip100, the first to third semiconductor chips200,210, and220, and the upper semiconductor chip300may each be a memory semiconductor chip. The memory semiconductor chip may be, for example, a volatile memory semiconductor chip, such as DRAM or static random access memory (SRAM), or a non-volatile memory semiconductor chip, such as phase-change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FeRAM), or resistive random access memory (RRAM).

In some embodiments, the lower semiconductor chip100, the first to third semiconductor chips200,210, and220, and the upper semiconductor chip300may include different types of semiconductor chips. For example, some semiconductor chips among the lower semiconductor chip100, the first to third semiconductor chips200,210, and220, and the upper semiconductor chip300may each be a logic chip, and other semiconductor chips among the lower semiconductor chip100, the first to third semiconductor chips200,210, and220, and the upper semiconductor chip300may each be a memory chip. For example, the logic chip include a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, and/or an application processor (AP) chip.

In some embodiments, the lower semiconductor chip100, the first to third semiconductor chips200,210, and220, and the upper semiconductor chip300may be realized based on HBM or a hybrid memory cube (HMC) standard. In this case, the lower semiconductor chip100arranged lowermost may function as a buffer die, and the first to third semiconductor chips200,210, and220and the upper semiconductor chip300may function as a core die. For example, the buffer die may also be referred to as an interface die, a base die, a logic die, a master die, and the like, and the core die may also be referred to as a memory die, a slave die, or the like. AlthoughFIG.1illustrates that four core dies are included in the semiconductor package1, the number of core dies may vary. For example, the semiconductor package1may include four core dies, eight core dies, twelve core dies, or sixteen core dies.

The lower semiconductor chip100may include a lower semiconductor substrate101, a semiconductor device layer (not shown), and through silicon vias (TSVs)105.

The lower semiconductor substrate101may include, for example, silicon (Si). In some embodiments, the lower semiconductor substrate101may include a semiconductor element, such as germanium (Ge), or a compound semiconductor, such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and/or indium phosphide (InP). The lower semiconductor substrate101may include a conductive region, for example, an impurity-doped well or an impurity-doped structure. In addition, the lower semiconductor substrate101may have various device isolation structures, such as a shallow trench isolation (STI) structure.

The semiconductor device layer (not shown) may be arranged on a lower surface of the lower semiconductor chip100. The semiconductor device layer may include various types of individual devices and an interlayer insulating film (not shown). The individual devices may include various microelectronic devices, for example, a metal-oxide-semiconductor field effect transistor (MOSFET), such as a complementary metal-insulator-semiconductor (CMOS) transistor, an image sensor, such as system large scale integration (LSI), flash memory, DRAM, SRAM, electrically erasable programmable read-only memory (EEPROM), PRAM, MRAM, RRAM, or a CMOS imaging sensor (CIS), a micro-electro-mechanical system (MEMS), an active device, or a passive device. The individual devices may be electrically connected to the conductive region of the lower semiconductor substrate101. The semiconductor device layer may further include a conductive wiring or conductive plug that electrically connects at least two of the individual devices to each other or the individual devices to the conductive region of the lower semiconductor substrate101.

The TSVs105may at least partially penetrate the lower semiconductor substrate101, and may further at least partially penetrate the semiconductor device layer (not shown). The TSVs105may be configured to electrically connect to each other upper conductive pads107disposed on an upper surface of the lower semiconductor chip100and lower conductive pads108disposed on a lower surface opposite to the upper surface of the lower semiconductor chip100. The TSVs105may include a pillar-shaped buried conductive layer and a cylindrical conductive barrier film surrounding a sidewall of the buried conductive layer. The buried conductive layer may include at least one material of copper (Cu), tungsten (W), nickel (Ni), and/or cobalt (Co). The conductive barrier film may include at least one material of Ti, TiN, Ta, TaN, Ru, Co, Mn, WN, Ni, and/or NiB. A via insulating film may be arranged between the lower semiconductor substrate101and the TSVs105. The via insulating film may include an oxide film, a nitride film, a carbide film, a polymer film, or a combination thereof.

The lower conductive pads108may be provided on the lower surface of the lower semiconductor chip100. For example, the lower conductive pads108may be disposed on the semiconductor device layer (not shown), and may be electrically connected to the TSVs105. The lower conductive pads108may include at least one of aluminum (Al), Cu, Ni, W, platinum (Pt), and/or gold (Au).

Conductive bumps106may be provided on the lower conductive pads108. The conductive bumps106may be disposed on a lowermost surface of the semiconductor package1, and may be bumps for mounting the semiconductor package1on an external substrate or an interposer. The conductive bumps106may receive, from the outside, at least one of a control signal, a power signal, or a ground signal, each for operation of the lower semiconductor chip100, the first to third semiconductor chips200,210, and220, and the upper semiconductor chip300. The conductive bumps106may receive, from the outside, a data signal to be stored in the lower semiconductor chip100, the first to third semiconductor chips200,210, and220, and the upper semiconductor chip300. The conductive bumps106may be utilized as an electrical path for providing, to the outside, data stored in the lower semiconductor chip100, the first to third semiconductor chips200,210, and220, and the upper semiconductor chip300.

The upper conductive pads107may be provided on the upper surface of the lower semiconductor chip100. The upper conductive pads107may include at least one of Al, Cu, Ni, W, Pt, and/or Au.

The first semiconductor chip200may be disposed on the upper surface of the lower semiconductor chip100. The lower semiconductor chip100and the first semiconductor chip200may be electrically connected to each other via conductive bumps206. An interlayer adhesive layer202surrounding the conductive bumps206may be arranged between the lower semiconductor chip100and the first semiconductor chip200. The interlayer adhesive layer202may include, for example, a non-conductive film (NCF), a non-conductive paste (NCP), an insulating polymer, and/or an epoxy resin.

The first semiconductor chip200may include a first semiconductor substrate201, a semiconductor device layer (not shown), TSVs205, upper conductive pads207, and lower conductive pads208. The first semiconductor substrate201, the semiconductor device layer (not shown), the TSVs205, the upper conductive pads207, and the lower conductive pads208included in the first semiconductor chip200may have characteristics substantially the same as or similar to those of the lower semiconductor substrate101, the semiconductor device layer (not shown), the TSVs105, the upper conductive pads107, and the lower conductive pads108of the lower semiconductor chip100, respectively, and thus, detailed descriptions of the first semiconductor chip200are omitted.

The second semiconductor chip210may be mounted on the first semiconductor chip200, and may include a second semiconductor substrate211, a semiconductor device layer (not shown), TSVs215, upper conductive pads217, and lower conductive pads218. The first semiconductor chip200and the second semiconductor chip210may be electrically connected to each other via conductive bumps216, and an interlayer adhesive layer212surrounding the conductive bumps216may be arranged between the first semiconductor chip200and the second semiconductor chip210. The second semiconductor substrate211, the semiconductor device layer (not shown), the TSVs215, the upper conductive pads217, and the lower conductive pads218of the second semiconductor chip210may have characteristics substantially similar to those of the lower semiconductor substrate101, the semiconductor device layer (not shown), the TSVs105, the upper conductive pads107, and the lower conductive pads108of the lower semiconductor chip100, and thus, detailed descriptions of the second semiconductor chip210are omitted.

The third semiconductor chip220may be mounted on the second semiconductor chip210, and may include a third semiconductor substrate221, a semiconductor device layer (not shown), TSVs225, upper conductive pads227, and lower conductive pads228. The second semiconductor chip210and the third semiconductor chip220may be electrically connected to each other via conductive bumps226, and an interlayer adhesive layer222surrounding the conductive bump226may be arranged between the second semiconductor chip210and the third semiconductor chip220. The third semiconductor substrate221, the semiconductor device layer (not shown), the TSVs225, the upper conductive pads227, and the lower conductive pads228of the third semiconductor chip220may have characteristics similar to those of the lower semiconductor substrate101, the semiconductor device layer (not shown), the TSVs105, the upper conductive pads107, and the lower conductive pads108of the lower semiconductor chip100, and thus, detailed descriptions of the third semiconductor chip220are omitted.

The upper semiconductor chip300may be mounted on the third semiconductor chip220, and may include an upper semiconductor substrate301, a semiconductor device layer (not shown), and lower conductive pads308. The third semiconductor chip220and the upper semiconductor chip300may be electrically connected to each other via conductive bumps306, and an interlayer adhesive layer302surrounding the conductive bumps306may be arranged between the third semiconductor chip220and the upper semiconductor chip300. A thickness of the upper semiconductor chip300in the vertical direction (the Z-axis direction) may be greater than a thickness of each of the lower semiconductor chip100and the first to third semiconductor chips200,210, and220in the vertical direction. The upper semiconductor substrate301, the semiconductor device layer (not shown), and the lower conductive pads308of the upper semiconductor chip300have characteristics similar to those of the first to third semiconductor chips200,210, and220, the first to third semiconductor substrates201,211, and221, the semiconductor device layers (not shown), the TSVs205,215, and225, the upper conductive pads207,217, and227, and the lower conductive pads208,218, and228, except that the upper semiconductor chip300does not include TSVs and upper conductive pads, and thus, detailed descriptions of the upper semiconductor chip300are omitted.

The semiconductor package1may include an encapsulant400in contact with sidewalls of the first to third semiconductor chips200,210, and220and the upper semiconductor chip300and in contact with the upper surface of the lower semiconductor chip100. The encapsulant400may cover or overlap a portion of the upper surface of the lower semiconductor chip100protruding from a sidewall of the first semiconductor chip200in a horizontal direction (an X-axis direction and/or a Y-axis direction), and may surround the sidewalls of the first to third semiconductor chips200,210, and220and the upper semiconductor chip300. In some embodiments, a sidewall of the lower semiconductor chip100and a sidewall of the encapsulant400may be aligned with each other in the vertical direction (the Z-axis direction).

In some embodiments, the encapsulant400may include an insulating polymer or an epoxy resin. The encapsulant400may include an EMC.

The semiconductor package1of the inventive concept may include more semiconductor chips than the lower semiconductor chip100, the first to third semiconductor chips200,210, and220, and the upper semiconductor chip300, which are semiconductor chips included in the semiconductor package1. The number of semiconductor chips included in the semiconductor package1of the inventive concept is not limited by this specification.

FIG.2is a cross-sectional view when AA′ plane ofFIG.1is viewed in a −Z-axis direction.

FIG.3is a side cross-sectional view showing enlarged B portion ofFIG.1according to some embodiments.

Referring toFIGS.2and3, the interlayer adhesive layer202may be arranged between the lower semiconductor chip100and the first semiconductor chip200as described above. In an interlayer space203arranged between the lower semiconductor chip100and the first semiconductor chip200and overlapping the lower semiconductor chip100and the first semiconductor chip200in the vertical direction (the Z-axis direction), the interlayer adhesive layer202may fill a portion of the interlayer space203, and the encapsulant400may extend into the interlayer space203.

An X-Y plane shape of the interlayer space203may be the same as an X-Y plane shape of the first semiconductor chip200. When the X-Y plane shape of the first semiconductor chip200is a quadrangle, the X-Y plane shape of the first semiconductor chip200has four vertices, and thus, the X-Y plane shape of the interlayer space203may also have four vertices. When viewed in an X-axis direction or a Y-axis direction, the four vertices may be observed as an edge of the interlayer space203, the edge extending in the Z-axis direction. Herein, a portion including the vertices of the X-Y plane shape of the interlayer space203or the edge of the interlayer space203extending in the Z-axis direction described above is hereinafter referred to as a corner204of the interlayer space203. In some embodiments, as shown inFIG.2, when a shape of the first semiconductor chip200is a quadrangle, a shape of the interlayer space203may also be a quadrangle.FIG.2is a view of AA′ cross-section in the −Z-axis direction, and the corner204is shown as four corners204a,204b,204c, and204dof the quadrangle inFIG.2.

The interlayer adhesive layer202arranged in the interlayer space203may fill a portion of the periphery of the corner204of the interlayer space203. Referring toFIG.1, the interlayer adhesive layer202may be in contact with the entire lower surface of the first semiconductor chip200. In contrast, the interlayer adhesive layer202may not be in contact with a portion of the lower surface of the lower semiconductor chip100, in a portion where the corner204of the interlayer space203is arranged in the lower semiconductor chip100. The interlayer adhesive layer202may surround the upper conductive pads107, the conductive bumps206, and the lower conductive pads208. In some embodiments, the interlayer adhesive layer202may surround the upper conductive pads107, the conductive bumps206, and the lower conductive pads208, which are arranged in the interlayer space203between the lower semiconductor chip100and the first semiconductor chip200. In other words, the interlayer adhesive layer202may be formed so that the encapsulant400is not in contact with the upper conductive pads107, the conductive bumps206, and the lower conductive pads208.

The encapsulant400may extend into the interlayer space203. In some embodiments, a portion of the encapsulant400may be apart from the lower surface of the first semiconductor chip200and may extend into the interlayer space203. In some embodiments, a portion of the encapsulant400may be apart from the lower surface of the first semiconductor chip200, and the interlayer adhesive layer202may be arranged between the encapsulant400and the lower surface of the first semiconductor chip200. In some embodiments, the encapsulant400may extend into the corner204of interlayer space203. The encapsulant400may fill a space where the interlayer adhesive layer202in the interlayer space203is not arranged in a portion where the corner204is arranged. In other words, the encapsulant extends into a corner of the interlayer space and is in a portion of the interlayer space that is free of the interlayer adhesive layer. In some embodiments, the encapsulant400may be in contact with a boundary of the interlayer adhesive layer202in the interlayer space203. The encapsulant400may extend into the interlayer space203while not being in contact with the upper conductive pads107, the conductive bumps206, and the lower conductive pads208.

A distance c from the corner204to the upper conductive pad107, the conductive bump206, and the lower conductive pad208may be greater than a distance a from the corner204ato the encapsulant400extending furthest into the interlayer space203.

The distance a from the corner204to the encapsulant400extending furthest into the interlayer space203may be at least about 50 μm and not more than about 1,600 μm. In some embodiments, referring toFIG.2, the distance a from the corner204ato the encapsulant400extending furthest in the X-axis direction into the interlayer space203may be at least about 50 μm and not more than about 1,600 μm. In addition, the distance b from the corner204ato the encapsulant400extending furthest in the Y-axis direction into the interlayer space203may be at least about 50 μm and not more than about 1,600 μm.

The numerical range described as not more than about 1,600 μm is a numeral range for the encapsulant400not to be in contact with the upper conductive pads107, the conductive bumps206, and the lower conductive pads208.

Referring toFIGS.1to3, the interlayer adhesive layer212may be arranged between the first semiconductor chip200and the second semiconductor chip210. In an interlayer space213arranged between the first semiconductor chip200and the second semiconductor chip210and overlapping the first semiconductor chip200and the second semiconductor chip210in the vertical direction (the Z-axis direction), the interlayer adhesive layer212may fill a portion of the interlayer space213, and the encapsulant400may extend into the interlayer space213.

An X-Y plane shape of the interlayer space213may be the same as an X-Y plane shape of the first semiconductor chip200or the second semiconductor chip210. When the X-Y plane shape of the first semiconductor chip200or the second semiconductor chip210is a quadrangle, the X-Y plane shape of the first semiconductor chip200or the second semiconductor chip210has four vertices, and thus, the X-Y plane shape of the interlayer space213may also have four vertices. When viewed in the X-axis direction or the Y-axis direction, the four vertices may be observed as an edge of the interlayer space213, the edge extending in the Z-axis direction. Herein, a portion including the vertices of the X-Y plane shape of the interlayer space213or the edge of the interlayer space213extending in the Z-axis direction described above is hereinafter referred to as a corner214of the interlayer space213. In some embodiments, when a shape of the first semiconductor chip200or the second semiconductor chip210is a quadrangle, a shape of the interlayer space213may also be a quadrangle.

The interlayer adhesive layer212arranged in the interlayer space213may fill a portion of the periphery of the corner214of the interlayer space213. Referring toFIG.1, the interlayer adhesive layer212may be in contact with the entire lower surface of the second semiconductor chip210. In contrast, the interlayer adhesive layer212may not be in contact with a portion of the lower surface of the first semiconductor chip200, in a portion where the corner214of the interlayer space213is arranged in the first semiconductor chip200. The interlayer adhesive layer212may surround the upper conductive pads207, the conductive bumps216, and the lower conductive pads218. In some embodiments, the interlayer adhesive layer212may surround the upper conductive pads207, the conductive bumps216, and the lower conductive pads218, which are arranged in the interlayer space213between the first semiconductor chip200and the second semiconductor chip210. In other words, the interlayer adhesive layer212may be formed so that the encapsulant400is not in contact with the upper conductive pads207, the conductive bumps216, and the lower conductive pads218.

The encapsulant400may extend into the interlayer space213. In some embodiments, a portion of the encapsulant400may be apart from the lower surface of the second semiconductor chip210and may extend into the interlayer space213. In some embodiments, a portion of the encapsulant400may be apart from the lower surface of the second semiconductor chip210, and the interlayer adhesive layer212may be arranged between the encapsulant400and the lower surface of the second semiconductor chip210. In some embodiments, the encapsulant400may extend into the corner214of the interlayer space213. The encapsulant400may fill or partially fill a space where the interlayer adhesive layer212in the interlayer space213is not arranged in a portion where the corner214is arranged. In some embodiments, the encapsulant400may be in contact with a boundary of the interlayer adhesive layer212in the interlayer space213. The encapsulant400may extend into the interlayer space213while not being in contact with the upper conductive pads207, the conductive bumps216, and the lower conductive pads218.

A distance219from the corner214to the encapsulant400extending furthest into the interlayer space213may be at least about 50 μm and not more than about 1,600 μm. Detailed descriptions of numerical values are the same as described above, and thus, redundant descriptions thereof are omitted.

The interlayer adhesive layer222may be arranged between the second semiconductor chip210and the third semiconductor chip220. In an interlayer space223arranged between the second semiconductor chip210and the third semiconductor chip220and overlapping the second semiconductor chip210and the third semiconductor chip220in the vertical direction (the Z-axis direction), the interlayer adhesive layer222may fill or partially fill a portion of the interlayer space223, and the encapsulant400may extend into the interlayer space223.

An X-Y plane shape of the interlayer space223may be the same as an X-Y plane shape of the second semiconductor chip210or the third semiconductor chip220. When the X-Y plane shape of the second semiconductor chip210or the third semiconductor chip220is a quadrangle, the X-Y plane shape of the second semiconductor chip210or the third semiconductor chip220has four vertices, and thus, the X-Y plane shape of the interlayer space223may also have four vertices. When viewed in the X-axis direction or the Y-axis direction, the four vertices may be observed as an edge of the interlayer space223, the edge extending in the Z-axis direction. Herein, a portion including the vertices of the X-Y plane shape of the interlayer space223or the edge of the interlayer space223extending in the Z-axis direction described above is hereinafter referred to as a corner224of the interlayer space223. In some embodiments, when a shape of the second semiconductor chip210or the third semiconductor chip220is a quadrangle, a shape of the interlayer space223may also be a quadrangle.

The interlayer adhesive layer222arranged in the interlayer space223may fill or partially fill a portion of the periphery of the corner224of the interlayer space223. Referring toFIG.1, the interlayer adhesive layer222may be in contact with the entire lower surface of the third semiconductor chip220. In contrast, the interlayer adhesive layer222may not be in contact with a portion of the lower surface of the second semiconductor chip210, in a portion where the corner224of the interlayer space223is arranged in the second semiconductor chip210. The interlayer adhesive layer222may surround the upper conductive pads217, the conductive bumps226, and the lower conductive pads228. In some embodiments, the interlayer adhesive layer222may surround the upper conductive pads217, the conductive bumps226, and the lower conductive pads228, which are arranged in the interlayer space223between the second semiconductor chip210and the third semiconductor chip220. In other words, the interlayer adhesive layer222may be formed so that the encapsulant400is not in contact with the upper conductive pads217, the conductive bumps226, and the lower conductive pads228.

The encapsulant400may extend into the interlayer space223. In some embodiments, a portion of the encapsulant400may be apart from the lower surface of the third semiconductor chip220and may extend into the interlayer space223. In some embodiments, a portion of the encapsulant400may be apart from the lower surface of the third semiconductor chip220, and the interlayer adhesive layer222may be arranged between the encapsulant400and the lower surface of the third semiconductor chip220. In some embodiments, the encapsulant400may extend into the corner224of the interlayer space223. The encapsulant400may fill or partially fill a space where the interlayer adhesive layer222in the interlayer space223is not arranged in a portion where the corner224is arranged. In some embodiments, the encapsulant400may be in contact with a boundary of the interlayer adhesive layer222in the interlayer space223. The encapsulant400may extend into the interlayer space223while not being in contact with the upper conductive pads217, the conductive bumps226, and the lower conductive pads228.

A distance229from the corner224to the encapsulant400extending furthest into the interlayer space223may be at least about 50 μm and not more than about 1,600 μm. Detailed descriptions of numerical values are the same as described above, and thus, redundant descriptions thereof are omitted.

The interlayer adhesive layer302may be arranged between the third semiconductor chip220and the upper semiconductor chip300. In an interlayer space303arranged between the third semiconductor chip220and the upper semiconductor chip300and overlapping the third semiconductor chip220and the upper semiconductor chip300in the vertical direction (the Z-axis direction), the interlayer adhesive layer302may fill or partially fill a portion of the interlayer space303, and the encapsulant400may extend into the interlayer space303.

An X-Y plane shape of the interlayer space303may be the same as an X-Y plane shape of the third semiconductor chip220or the upper semiconductor chip300. When the X-Y plane shape of the third semiconductor chip220or the upper semiconductor chip300is a quadrangle, the X-Y plane shape of the third semiconductor chip220or the upper semiconductor chip300has four vertices, and thus, the X-Y plane shape of the interlayer space303may also have four vertices. When viewed in the X-axis direction or the Y-axis direction, the four vertices may be observed as an edge of the interlayer space303, the edge extending in the Z-axis direction. Herein, a portion including the vertices of the X-Y plane shape of the interlayer space303or the edge of the interlayer space303extending in the Z-axis direction described above is hereinafter referred to as a corner304of the interlayer space303. In some embodiments, when a shape of the third semiconductor chip220or the upper semiconductor chip300is a quadrangle, a shape of the interlayer space303may also be a quadrangle.

The interlayer adhesive layer302arranged in the interlayer space303may fill or partially fill a portion of the periphery of the corner304of the interlayer space303. Referring toFIG.1, the interlayer adhesive layer302may be in contact with the entire lower surface of the upper semiconductor chip300. In contrast, the interlayer adhesive layer302may not be in contact with a portion of the lower surface of the third semiconductor chip220, in a portion where the corner304of the interlayer space303is arranged in the third semiconductor chip220. The interlayer adhesive layer302may surround the upper conductive pads227, the conductive bumps306, and the lower conductive pads308. In some embodiments, the interlayer adhesive layer302may surround the upper conductive pads227, the conductive bumps306, and the lower conductive pads308, which are arranged in the interlayer space303between the third semiconductor chip220and the upper semiconductor chip300. In other words, the interlayer adhesive layer302may be formed so that the encapsulant400is not in contact with the upper conductive pads227, the conductive bumps306, and the lower conductive pads308.

The encapsulant400may extend from the outside of the interlayer space303into the interlayer space303. In some embodiments, a portion of the encapsulant400may be apart from the lower surface of the upper semiconductor chip300and may extend into the interlayer space303. In some embodiments, a portion of the encapsulant400may be apart from the lower surface of the upper semiconductor chip300, and the interlayer adhesive layer302may be arranged between the encapsulant400and the lower surface of the upper semiconductor chip300. In some embodiments, the encapsulant400may fill or partially fill a space where the interlayer adhesive layer302in the interlayer space303is not arranged in a portion where the corner304is arranged. In some embodiments, the encapsulant400may be in contact with a side surface of the interlayer adhesive layer302, which is not in contact with the third semiconductor chip220and the upper semiconductor chip300. The encapsulant400may extend into the interlayer space303while not being contact with the upper conductive pads227, the conductive bumps306, and the lower conductive pads308.

A distance309from the corner304to the encapsulant400extending furthest into the interlayer space303may be at least about 50 μm and not more than about 1,600 μm. Detailed descriptions of numerical values are the same as described above, and thus, redundant descriptions thereof are omitted.

Adhesion of the encapsulant400to the lower semiconductor chip100, the first to third semiconductor chips200,210, and220, and the upper semiconductor chip300may be greater than adhesion of the interlayer adhesive layers202,212,222, and302to the lower semiconductor chip100, the first to third semiconductor chips200,210, and220, and the upper semiconductor chip300. The encapsulant400extends into the interlayer spaces203,213,223, and303and fills or partially fills portions of interlayer spaces203,213,223, and303, and due to the adhesion of the encapsulant400to the lower semiconductor chip100, the first to third semiconductor chips200,210, and220, and the upper semiconductor chip300, the reliability of the semiconductor package1in which the lower semiconductor chip100, the first to third semiconductor chips200,210, and220, and the upper semiconductor chip300are stacked may be improved.

FIG.4is a side cross-sectional view showing enlarged B portion ofFIG.1according to some embodiments.FIG.5is a side cross-sectional view showing an enlarged portion of a semiconductor package according to some embodiments.

Referring toFIG.4, the interlayer adhesive layer202may not be in contact with a portion of a corner portion of the lower surface of the first semiconductor chip200. The encapsulant400may be in contact with each of a portion of the lower surface of the first semiconductor chip200and a portion of the upper surface of the lower semiconductor chip100.

In the case ofFIG.4, like a case ofFIG.3, the distance c from the corner204to the upper conductive pad107, the conductive bump206, and the lower conductive pad208may be greater than the distance a from the corner204to the encapsulant400extending furthest into the interlayer space203. A distance209from the corner204to the encapsulant400extending furthest into the interlayer space203may be at least about 50 μm and not more than about 1,600 μm.

Referring toFIG.5, a shape of the interlayer adhesive layer202at a portion other than the corner204may extend laterally from the interlayer space203. Referring toFIG.2, the interlayer adhesive layer202may extend outward based on a perimeter of the interlayer space203formed along the corners204a,204b,204c, and204dof the interlayer space203. The extended interlayer adhesive layer202may be in contact with the encapsulant400surrounding the lower semiconductor chip100and the first semiconductor chip200.

Descriptions of the interlayer adhesive layer202may be applied to other interlayer adhesive layers212,222,232, and302, and descriptions of the encapsulant400may be applied to all interlayer spaces203,213,223,303. Redundant descriptions thereof are omitted.

FIGS.6A to6Fare cross-sectional views showing a method of manufacturing the semiconductor package1, according to some embodiments. Hereinafter, referring toFIGS.6A to6F, a method of manufacturing the semiconductor package1according to some embodiments is described.

Referring toFIG.6A, the TSVs205may be formed by etching the lower surface of the first semiconductor substrate201having an upper surface and a lower surface in the Z-axis direction. In some embodiments, the forming of the TSVs205by etching the portion of the lower surface of the first semiconductor substrate201may include etching the portion of the lower surface of the first semiconductor substrate201by using a dry etching process. The first semiconductor substrate201may include a first semiconductor device layer (not shown). The lower conductive pads208may be formed on the lower surface of the first semiconductor substrate201and be electrically connected to the TSVs205, and the conductive bumps206may be formed on the lower conductive pads208.

Referring toFIG.6B, a portion of the TSVs205may be exposed by removing a portion of the first semiconductor substrate201of the first semiconductor chip200. As a result of removing a portion of the upper surface of the first semiconductor substrate201, the TSVs205may penetrate the first semiconductor substrate201. In order to expose the TSVs205, a portion of the upper surface of the first semiconductor substrate201may be removed by using a chemical mechanical polishing (CMP) process, an etch-back process, or a combination thereof. The upper conductive pads207electrically connected to the exposed TSVs205may be formed on the upper surface of the first semiconductor substrate201.

The interlayer adhesive layer202for stacking on the lower semiconductor chip100previously prepared may be formed on the lower surface of the first semiconductor substrate201. The interlayer adhesive layer202may include, for example, an NCF, an NCP, an insulating polymer, or an epoxy resin.

The first semiconductor chip200may be disposed on the lower semiconductor chip100, which is previously prepared, including the TSVs105formed to penetrate at least a portion of the lower semiconductor substrate101, the upper conductive pads107, the lower conductive pads108, and the conductive bumps106.

Referring toFIG.6C, the first semiconductor chip200may be stacked on the lower semiconductor chip100while the upper conductive pads107and the conductive bumps206are electrically connected to each other. The stacking of the first semiconductor chip200includes thermocompression bonding.

In the stacking process, the interlayer adhesive layer202may fill or partially fill a portion of the interlayer space203as described above with reference toFIGS.1to3. The interlayer adhesive layer202may fill or partially fill a portion of the periphery of the corner204of the interlayer space203. The interlayer adhesive layer202may be in contact with the lower surface of the first semiconductor chip200. In contrast, the interlayer adhesive layer202may not be in contact with a portion of the upper surface of the lower semiconductor chip100, in a portion where the corner204of the interlayer space203is arranged in the lower semiconductor chip100.

Referring toFIG.6D, the second semiconductor chip210may be formed via the same process that forms the first semiconductor chip200. The second semiconductor chip210may be stacked on the first semiconductor chip200as described above with reference toFIG.6C. Redundant descriptions thereof are omitted.

Referring toFIG.6E, the third semiconductor chip220may be formed via the same process that forms the first semiconductor chip200, and the third semiconductor chip220may be stacked on the second semiconductor chip210. Redundant descriptions thereof are omitted.

The upper semiconductor chip300may have characteristics similar to those of the lower semiconductor chip100and the first to third semiconductor chips200,210, and220, except that the upper semiconductor chip300does not include TSVs. The upper semiconductor chip300may be stacked on the third semiconductor chip220while the upper conductive pads227and the conductive bumps306are electrically connected to each other. Redundant descriptions of the upper semiconductor chip300are omitted.

Referring toFIG.6F, the encapsulant400may be formed to be in contact with sidewalls of the first to third semiconductor chips200,210, and220and the upper semiconductor chip300and in contact with the upper surface of the lower semiconductor chip100. The encapsulant400may extend into the interlayer space203between the lower semiconductor chip100and the first semiconductor chip200, the interlayer space213between the first semiconductor chip200and the second semiconductor chip210, the interlayer space223between the second semiconductor chip210and the third semiconductor chip220, and the interlayer space303between the third semiconductor chip220and the upper semiconductor chip300. In addition, the encapsulant400may extend into each of the interlayer spaces203,213,223,303to occupy a space not occupied by the interlayer adhesive layers202,212,222, and302in the interlayer spaces203,213,223,303. Redundant descriptions of the encapsulant400and the interlayer adhesive layers202,212,222,302are omitted.