PACKAGE SUBSTRATE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME

A package substrate including a glass substrate having a first surface and a second surface opposite thereto, and including a plurality of through holes extending from the second surface to the first surface of the glass substrate, a plurality of wiring patterns each including a through electrode positioned in the plurality of through holes and a via pad extending from the through electrode to cover a portion of the second surface of the glass substrate, a seed layer arranged between the glass substrate and the plurality of wiring patterns, and including a first surface coplanar with the first surface of the glass substrate, wherein the through electrode of each of the plurality of wiring patterns includes a first surface coplanar with the first surface of the glass substrate.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based on and claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2023-0082131, filed on Jun. 26, 2023 in the Korean Intellectual Property office, the disclosure of which is incorporated by reference herein in its entirety.

BACKGROUND

Aspects of the inventive concept relate to a package substrate and a semiconductor package including the package substrate, and more particularly, to a package substrate including a glass substrate and a semiconductor package including the package substrate.

Due to advancements in the electronic industry, demand for high functionality, high speed, and miniaturization of electronic components has increased. According to this trend, there is an increasing need for miniaturization and multi-functionalization of semiconductor chips used in electronic components. In addition, in the field of semiconductor packages, the size thereof is miniaturized based on small semiconductor chips. In addition, due to demand for improved performance and form factor reduction of the semiconductor packages, the semiconductor package structure is moving toward a multi-chip integrated structure. In this case, the multi-chip integration may mean integration of chips manufactured in different processes in a single semiconductor package together.

SUMMARY

Aspects of the inventive concept provide a package substrate having improved design degree of freedom and a semiconductor package including the package substrate.

Aspects of the inventive concept provide a package substrate having improved characteristics of signal integrity (SI) and power integrity (PI) characteristics and a semiconductor package including the package substrate.

In addition, the issues to be solved in accordance with aspects of the inventive concept are not limited to those mentioned above, and other issues may be clearly understood by those of ordinary skill in the art from the following descriptions.

According to an aspect of the inventive concept, there is provided a package substrate including a glass substrate including a first surface and a second surface opposite thereto, and including a plurality of through holes extending from the second surface to the first surface of the glass substrate, a plurality of wiring patterns each including a through electrode positioned in the plurality of through holes and a via pad extending from the through electrode to cover a portion of the second surface of the glass substrate, a seed layer arranged between the glass substrate and the plurality of wiring patterns, and including a first surface coplanar with the first surface of the glass substrate, wherein the through electrode of each of the plurality of wiring patterns includes a first surface coplanar with the first surface of the glass substrate.

According to another aspect of the inventive concept, there is provided a semiconductor package including a package substrate, and at least one semiconductor chip arranged on the package substrate, wherein the package substrate includes a glass substrate including a first surface and a second surface opposite thereto, and including a plurality of through holes extending from the second surface to the first surface of the glass substrate, a plurality of wiring patterns respectively positioned in the plurality of through holes, the plurality of wiring patterns each including a through electrode including a first surface coplanar with the first surface of the glass substrate and a via pad extending from the through electrode to cover a portion of the second surface of the glass substrate, a seed layer arranged between the glass substrate and the plurality of wiring patterns, and including a first surface coplanar with the first surface of the glass substrate, and a first redistribution structure arranged on at least one surface of the first surface and the second surface of the glass substrate, wherein the through electrode of each of the plurality of wiring patterns includes a first surface coplanar with the first surface of the glass substrate.

According to another aspect of the inventive concept, there is provided a semiconductor package including a package substrate, at least one semiconductor chip arranged on the package substrate, and an external connection terminal arranged on the package substrate, and disposed apart from the at least one semiconductor chip with the package substrate therebetween, wherein the package substrate includes a glass substrate including a first surface and a second surface opposite thereto, and including a plurality of through holes including a horizontal width decreasing and extending from the second surface to the first surface of the glass substrate, a plurality of wiring patterns respectively positioned in the plurality of through holes, the plurality of wiring patterns each including a through electrode including a first surface coplanar with the first surface of the glass substrate and a via pad extending from the through electrode to cover a portion of the second surface of the glass substrate, a seed layer arranged between the glass substrate and the wiring patterns, and including a first surface coplanar with the first surface of the glass substrate, a first redistribution structure including a plurality of redistribution vias, a redistribution insulating layer, and a plurality of redistribution line patterns, and arranged on the first surface of the glass substrate, and a second redistribution structure arranged on the second surface of the glass substrate, and including a plurality of redistribution vias, a redistribution insulating layer, and a plurality of redistribution line patterns, wherein the plurality of redistribution vias of the first redistribution structure have a horizontal width less than a horizontal width of each of the plurality of through holes, and contact the first surface of the through electrode of the plurality of wiring patterns.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Because various changes can be applied to the embodiments and accordingly, the embodiments can have various types, some embodiments are illustrated in the drawings and detailed descriptions thereof are provided. However, the various changes are not intended to limit the embodiments to particular disclosure forms.

FIG.1is a schematic cross-sectional view of a package substrate10according to an embodiment.FIG.2is an enlarged cross-sectional view of region II inFIG.1.

Referring toFIGS.1and2, the package substrate10may include a glass substrate100, a plurality of wiring patterns200, and a seed layer300.

The glass substrate100of the package substrate10may include a first surface100_S1and a second surface100_S2opposite thereto. Hereinafter, unless specifically defined, a direction in parallel with the first surface100_S1of the glass substrate100may be defined as a horizontal direction D1, and a direction perpendicular to the first surface100_S1may be defined as a vertical direction D2.

In some embodiments, the glass substrate100may include or may be formed of an inorganic material, glass, or ceramic. In general, glass may have good characteristics in terms of smoothness, thermal expansion coefficient, surface hardness, etc. For example, glass may have good smoothness and may be easily made wide and flat. In addition, glass may have a low thermal expansion coefficient of 9.0*10−6° C., and a high hardness of about 6 H to about 7 H. In some embodiments, the glass used in the glass substrate100may, as a reinforced glass having increased tensile strength, may have high rigidity.

The glass substrate100may have a rectangular flat plate (e.g., planar) shape. The glass substrate100may have a thickness (i.e., in the vertical direction D2) of about 50 μm to about 1500 μm. However, the thickness of the glass substrate100is not limited thereto.

The glass substrate100may include a plurality of through holes110extending from the second surface100_S2to the first surface100_S1. Each of a plurality of through holes110may have a narrower horizontal width W_110(i.e., in the horizontal direction D1) toward the first surface100_S1of the glass substrate100. Each of the plurality of through holes110may have a horizontal width W_110on the first surface100_S1of the glass substrate100that is less than the horizontal width W_110on the second surface100_S2of the glass substrate100.

In some embodiments, the sidewall110_S of the glass substrate100defining the plurality of through holes110may have an inclination. For example, the sidewall110_S of the glass substrate100defining the plurality of through holes110may be inclined at an acute angle with respect to the first surface100_S1of the glass substrate100.

Each of the plurality of wiring patterns200of the package substrate10may include a through electrode210and a via pad220. For reference, because the plurality of wiring patterns200have a structure penetrating the glass substrate100, the plurality of wiring patterns200may be referred to as a through glass via (TGV).

The through electrode210and the via pad220may be formed together. For example, the through electrode210and the via pad220may be formed together by using an electro-plating process using the seed layer300. Although the through electrode210and the via pad220are distinguished by a dashed line inFIGS.1and2, they may actually have the form of one-body integrally combined. For example, in some embodiments, the through electrode210and the via pad220may not be distinguished as individual components, but may be treated as one component.

In some embodiments, the plurality of wiring patterns200may be arranged apart from each other in the horizontal direction D1. In the plurality of wiring patterns200, a separation distance D_200between vertical axes of two adjacent wiring patterns200may be about 100 μm to about 200 μm. The separation distance D_200of the vertical axes of the two wiring patterns200may vary according to the thickness of the glass substrate100.

In some embodiments, the plurality of wiring patterns200may include first wiring patterns201and second wiring patterns202. Although not illustrated, a via pad221of the first wiring pattern201may extend along the second surface100_S2of the glass substrate100, and may be connected to the via pad222of the second wiring pattern202. For example, the via pad221of the first wiring pattern201and the via pad222of the second wiring pattern202may be integrally combined. The via pad221of the first wiring pattern201and the via pad222of the second wiring pattern202may be formed as one-body, depending on the shape of the mask.

In some embodiments, the plurality of wiring patterns200may include a metal, a conductive metal oxide, a conductive metal nitride, etc. For example, the plurality of wiring patterns200may include or may be formed of copper (Cu), tungsten (W), aluminum (Al), nickel (Ni), cobalt (Co), titanium (Ti), titanium nitride (TiN), etc. The plurality of wiring patterns200may be formed by, for example, using an electroplating process. However, the embodiment is not limited thereto, the plurality of wiring patterns200may be formed by using other processes, such as electroless plating, deposition, and sputtering.

The through electrode210of each of the plurality of wiring patterns200may be positioned in each of the plurality of through holes110. A first surface200_S1of the through electrode210may be coplanar with the first surface100_S1of the glass substrate100. For example, the first surface200_S1of the through electrode210may not be covered by the seed layer300.

In some embodiments, the through electrode210may have, for example, a cylindrical shape penetrating the glass substrate100. However, the shape of the through electrode210is not limited thereto. For example, according to some embodiments, the through electrode210may also have an elliptical pillar or polygonal pillar shape.

A horizontal width of the through electrode210may correspond to the horizontal width W_110of each of the plurality of through holes110. For example, the through electrode210may have a shape in which the horizontal width thereof decreases toward the first surface100_S1of the glass substrate100, like the plurality of through holes110. For example, the horizontal width of the through electrode210may be greater on the second surface100_S2of the glass substrate100than that on the first surface100_S1of the glass substrate100.

The via pad220of each of the plurality of wiring patterns200may extend from the through electrode210to cover a portion of the second surface100_S2of the glass substrate100. For example, because a horizontal width of the via pad220is greater than that of each of the plurality of through holes110, the via pad220may cover a portion of the second surface100_S2of the glass substrate100. For example, although the horizontal width of the through electrode210increases even toward the second surface100_S2of the glass substrate100, the horizontal width of the via pad220may be greater than the maximum horizontal width of the through electrode210.

In some embodiments, the via pad220may have a circular or rectangular flat plate (e.g., planar) shape. Accordingly, a cross-section of the via pad220may have, for example, a rectangular shape elongated in the horizontal direction D1.

The seed layer300of the package substrate10may be arranged between the glass substrate100and each of the plurality of wiring patterns200. The seed layer300may comprise a first portion (e.g., protrusion portion) and a second portion. The protrusion portion P_300of the seed layer300may located between the via pad220and the second surface100_S2of the glass substrate100. The second portion of the seed layer300extends from the protrusion portion P_300to100_S1of the glass substrate100along the sidewall110_S of the glass substrate100.

For example, the seed layer300may extend along the protrusion portion P_300between the via pad220and the second surface100_S2of the glass substrate100, and may extend along the sidewall110_S of the glass substrate100defining each of the plurality of through holes110from the protrusion portion P_300and the first surface100_S1of the glass substrate100. In some embodiments, the seed layer300may conformally extend along a portion of the second surface100_S2of the glass substrate100and the sidewall110_S of the glass substrate100, which defines each of the plurality of through holes110.

The seed layer300may include a first surface300_S1coplanar with the first surface100_S1of the glass substrate100. For example, in the process of removing portions of the glass substrate100, the through electrode210, and the seed layer300, the first surface100_S1of the glass substrate100, the first surface200_S1of the through electrode210, and the first surface300_S1of the seed layer300may be coplanar with each other.

In some embodiments, a side surface P_300S of the protrusion portion P_300may be coplanar with a side surface220S of each via pad220of the plurality of wiring patterns200. In the process of forming the via pad220, a portion of the via pad220and a portion of the protrusion portion P_300of the seed layer300may be removed in the same shape, so that the side surface220S of the via pad220may be coplanar with the side surface P_300S of the protrusion portion P_300of the seed layer300.

In some embodiments, the seed layer300may include or may be for the of a metal, such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), nickel (Ni), magnesium (Mg), rhenium (Rc), beryllium (Be), gallium (Ga), and ruthenium (Ru), or an alloy thereof, but is not limited thereto.

In some embodiments, the seed layer300may be formed by using a deposition process, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), and physical vapor deposition (PVD). When the wiring pattern200is electroplated on the glass substrate100, the seed layer300may help the wiring pattern200, especially the through electrode210of the wiring pattern200, completely fill the inside of the plurality of through holes110of the glass substrate100.

FIG.3is a schematic cross-sectional view of a package substrate10aaccording to an embodiment.

Referring toFIG.3, the package substrate10amay include the glass substrate100, the plurality of wiring patterns200, the seed layer300, and a second redistribution structure700a.

Hereinafter, duplicate descriptions of the package substrate10aofFIG.3and the package substrate10ofFIG.1are omitted, and differences thereof are given. The package substrate10aofFIG.3may be different from the package substrate10ofFIG.1with respect to the second redistribution structure700a, and all, except for this difference, may be substantially the same.

The second redistribution structure700aof the package substrate10amay be on the second surface100_S2of the glass substrate100. The second redistribution structure700amay include a plurality of redistribution vias740, a plurality of redistribution line patterns720, and a redistribution insulating layer760.

Although the redistribution insulating layer760is illustrated as one layer inFIG.3, the redistribution insulating layer760may include a plurality of layers. When the redistribution insulating layer760includes a plurality of layers, the plurality of redistribution line patterns720may be arranged on at least one of an upper surface and a lower surface of each layer of the redistribution insulating layer760.

The plurality of redistribution vias740may penetrate the redistribution insulating layer760, and may contact and be connected to some of the plurality of redistribution line patterns720. In some embodiments, at least some of the plurality of redistribution line patterns720may be formed in one body together with some of the plurality of redistribution vias740. For example, a redistribution line pattern720and the redistribution via740contacting an upper surface of the redistribution line pattern720may be formed as one body.

The redistribution insulating layer760may surround the plurality of redistribution line patterns720and the plurality of redistribution vias740. In some embodiments, the redistribution insulating layer760may surround the side surface220S of the via pad220of the plurality of wiring patterns200, the side surface (P_300inFIG.2) of the protrusion portion (P_300inFIG.2) of the seed layer300, and a portion of the second surface100_S2of the glass substrate100.

The plurality of redistribution line patterns720and the plurality of redistribution vias740may be electrically connected to the via pad220. In some embodiments, at least some of the plurality of redistribution vias740may be in contact with the via pad220of each of the plurality of wiring patterns200. It will be understood that when an element is referred to as being “connected” or “coupled” to or “on” another element, it can be directly connected or coupled to or on the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, or as “contacting,” “in contact with,” or “contact” another element, there are no intervening elements present at the point of contact.

In some embodiments, each of the plurality of redistribution vias740may have a tapered shape, in which a horizontal width thereof decreases as the redistribution vias740extend along the vertical direction D2. For example, the plurality of redistribution vias740may have a greater horizontal width away from the glass substrate100. However, the plurality of redistribution vias740are not limited thereto, and may have a narrower horizontal width toward the glass substrate100.

Among the plurality of redistribution line patterns720, the redistribution line pattern720arranged on a surface exposed to the outside of the second redistribution structure700amay be referred to as a redistribution pad750a. A semiconductor chip may be mounted on the redistribution pad750a. The redistribution pad750amay be surrounded by a passivation layer760aon the redistribution insulating layer760.

The redistribution line pattern720and the redistribution via740may include or may be formed of, for example, a metal, such as Cu, Al, W, Ti, Ta, In, Mo, Mn, Co, Sn, Ni, Mg, Re, Be, Ga, and Ru, or an alloy thereof, but are not limited thereto. The redistribution insulating layer760may be formed from, for example, photo imageable dielectric (PID) or photosensitive polyimide (PSPI).

A plurality of external connection terminals800aof the package substrate10amay be on the first surface100_S1of the glass substrate100. The plurality of external connection terminals800amay be disposed apart from the second redistribution structure700awith the glass substrate100therebetween. The plurality of external connection terminals800amay cover a portion of the first surface100_S1of the glass substrate100, the first surface200_S1of the through electrode210of the plurality of wiring patterns200, and the first surface300_S1of the seed layer300.

The plurality of external connection terminals800amay be configured to electrically and physically connect the package substrate10ato the external device, and may be configured to transmit an electrical signal between the package substrate10aand the external device. The plurality of external connection terminals800amay be formed from solder balls or solder bumps.

FIG.4is a schematic cross-sectional view of a package substrate10baccording to an embodiment.

Referring toFIG.4, the package substrate10bmay include the glass substrate100, the plurality of wiring patterns200, the seed layer300, and a first redistribution structure700b.

Hereinafter, duplicate descriptions of the package substrate10bofFIG.4and the package substrate10aofFIG.3are omitted, and differences thereof are given. The package substrate10bofFIG.4may be different from the package substrate10aofFIG.3with respect to the first redistribution structure700band a plurality of external connection terminals800b, and all, except for these differences, may be substantially the same.

The first redistribution structure700bof the package substrate10bmay be on the first surface100_S1of the glass substrate100. The first redistribution structure700bmay include the plurality of redistribution vias740, the plurality of redistribution line patterns720, and the redistribution insulating layer760.

Some of the plurality of redistribution vias740may be in contact with the through electrode210of the plurality of wiring patterns200. In some embodiments, some of the plurality of redistribution vias740may be in contact with the first surface200_S1of the through electrode210.

A horizontal width W_740of some of the plurality of redistribution vias740may be less than the horizontal width W_110of each of the plurality of through holes110of the glass substrate100. The horizontal width W_740of the redistribution via740in contact with the first surface200_S1of the through electrode210among the plurality of redistribution vias740may be less than the horizontal width W_110of each of the plurality of through holes110.

In some embodiments, when the horizontal width W_110of each of the plurality of through holes110decreases toward the first surface100_S1of the glass substrate100, the horizontal width W_740of some redistribution vias740among the plurality of redistribution vias740may be less than a minimum horizontal width of the horizontal width W_110of each of the plurality of through holes110.

The redistribution insulating layer760surrounding the plurality of redistribution vias740and the plurality of redistribution line patterns720may cover a portion of the first surface200_S1of the through electrode210of each of the plurality of wiring patterns200. A region of the first surface200_S1of the through electrode210, which does not contact the redistribution via740, may be covered by the redistribution insulating layer760. The redistribution insulating layer760may cover a portion of the first surface200_S1of the through electrode210, the first surface100_S1of the glass substrate100, and the first surface300_S1of the seed layer300.

The redistribution line pattern720arranged on a surface exposed to the outside of the first redistribution structure700bamong the plurality of redistribution line patterns720may be referred to as a redistribution pad750b. A semiconductor chip may be mounted in the redistribution pad750b. The redistribution pad750bmay be surrounded by a passivation layer760bon the redistribution insulating layer760.

Each of the plurality of external connection terminals800bof package substrates10bmay be on the via pad220of each of the plurality of wiring patterns200. For example, the plurality of external connection terminals800bmay be disposed apart from the second surface100_S2of the glass substrate100in the vertical direction D2with the via pad220therebetween. The plurality of external connection terminals800bmay be configured to transmit an electrical signal between the package substrate10band an external device. The plurality of external connection terminals800bmay be formed from solder balls or solder bumps.

FIG.5is a schematic cross-sectional view of a package substrate10caccording to an embodiment.

Referring toFIG.5, the package substrate10cmay include the glass substrate100, the plurality of wiring patterns200, the seed layer300, and the second redistribution structure700a.

Hereinafter, duplicate descriptions of the package substrate10cofFIG.5and the package substrate10ofFIG.1are omitted, and differences thereof are given. The package substrate10cofFIG.5may be different from the package substrate10ofFIG.1with respect to the first redistribution structure700band the second redistribution structure700a, and all, except for these differences, may be substantially the same.

The first redistribution structure700bof the package substrate10cmay be on the first surface100_S1of the glass substrate100. The second redistribution structure700aof the package substrate10cmay be on the second surface100_S2of the glass substrate100. The first redistribution structure700bmay be electrically connected to the second redistribution structure700avia the plurality of wiring patterns200of the glass substrate100.

Each of the first redistribution structure700band the second redistribution structure700amay include the plurality of redistribution vias740, the plurality of redistribution line patterns720, and the redistribution insulating layer760. The first redistribution structure700bmay be substantially the same as the first redistribution structure700binFIG.4. The second redistribution structure700amay be substantially the same as the second redistribution structure700ainFIG.3.

FIG.6is a schematic cross-sectional view of a semiconductor package1000aaccording to an embodiment.FIG.7is a schematic cross-sectional view of a semiconductor package1000baccording to an embodiment.FIG.8is a schematic cross-sectional view of a semiconductor package1000caccording to an embodiment.

Referring toFIGS.6through8, the semiconductor packages1000a,1000b, and1000cmay include the package substrates10a,10b, and10c, respectively, and at least one semiconductor chip20. InFIGS.6through8, there may be differences in respect of the package substrates10a,10b, and10c, and the remaining configurations, except for the differences, may be substantially the same.

The semiconductor packages1000a,1000b, and1000cofFIGS.6through8may represent semiconductor packages including the package substrates10a,10b, and10cofFIGS.3through5, respectively. The semiconductor package1000aofFIG.6may include the package substrate10aofFIG.3. The semiconductor package1000bofFIG.7may include the package substrate10bofFIG.4. The semiconductor package1000cofFIG.8may include the package substrate10cofFIG.5. Descriptions of the package substrates10a,10b, and10care duplicative of those described above, and are omitted.

At least one semiconductor chip20may include a semiconductor substrate510including an active surface and an inactive surface opposite to each other, a plurality of chip pads520arranged on the active surface of the semiconductor chip20, and a passivation layer530surrounding the plurality of chip pads520.

The semiconductor chip20may be arranged on the package substrates10a,10b, and10c. The semiconductor chip20may be arranged on the redistribution pad750aof the first redistribution structure700aor the redistribution pad750bof the second redistribution structure700bof the package substrates10a,10b, and10c. InFIG.8, it is illustrated that the semiconductor chip20is arranged on the second redistribution structure700a, but the embodiment is not limited thereto, and the semiconductor chip20may be arranged on the first redistribution structure700b.

In an example embodiment, the semiconductor chip20may have a face down arrangement, in which the active surface thereof faces the package substrates10a,10b, and10c, and may be arranged on the package substrates10a,10b, and10c. In this case, a plurality of chip connection terminals900may be arranged between the plurality of chip pads520of the semiconductor chip20and some of the redistribution pads750aand750bof the package substrate10a,10b, and10c, respectively. The plurality of chip connection terminals900may include, for example, solder balls or bumps, but are not limited thereto. The semiconductor chip20may be electrically connected to the package substrates10a,10b, and10cvia the plurality of chip connection terminals900. In addition, the semiconductor chip20may be combined with the package substrates10a,10b, and10cby using a hybrid bonding process.

In an embodiment, an underfill layer910may be arranged between the passivation layer530of the semiconductor chip20and passivation layers760aand760bof the package substrates10a,10b, and10c. The underfill layer910may surround the plurality of chip connection terminals900. The underfill layer910may include, for example, epoxy resin formed by using a capillary underfill method.

InFIGS.6through8, two semiconductor chips20are illustrated as arranged on the package substrates10a,10b, and10c, but the embodiment is not limited thereto, and the number of the semiconductor chips may be one or three or more. In addition, although it is illustrated that two semiconductor chips20are arranged in parallel with each other in the horizontal direction D1on the package substrates10a,10b, and10c, the embodiment is not limited thereto, and at least two semiconductor chips20may be stacked in the vertical direction D2.

In an example embodiment, the semiconductor chip20may include a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, or an application processor (AP) chip.

According to another example embodiment, the semiconductor chip20may include, for example, a memory semiconductor chip. The memory semiconductor chip may include, for example, a non-volatile memory semiconductor chip, such as flash memory, phase change random access memory (RAM) (PRAM), magnetic RAM (MRAM), ferroelectric RAM (FeRAM), or resistive RAM (RRAM). The flash memory may include, for example, an NAND flash memory, or a V-NAND flash memory. In an embodiment, the semiconductor chip20may include a volatile memory semiconductor chip, such as dynamic RAM (DRAM) and static RAM (SRAM).

The semiconductor substrate510may include, for example, a Group IV semiconductor, such as silicon (Si) and germanium (Ge), a Group IV-IV compound semiconductor, such as silicon-germanium (SiGe) and silicon carbide (SiC), or a Group III-V semiconductor, such as gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). The semiconductor substrate510may include a conductive region, for example, a well doped with impurities. The semiconductor substrate510may have various device isolation structures such as a shallow trench isolation (STI) structure.

A semiconductor device including a plurality of individual devices of various types may be formed on the active surface of the semiconductor substrate510. The plurality of individual devices may include various microelectronic devices, for example, a metal-oxide-semiconductor field effect transistor (MOSFET) such as a complementary metal-oxide-semiconductor (CMOS) transistor, an image sensor, such as system large scale integration (LSI) and a CMOS imaging sensor (CIS), a micro electro-mechanical system (MEMS), an active element, a passive element, etc.

The plurality of individual devices may be electrically connected to the conductive region of the semiconductor substrate510. A semiconductor device may further include a conductive wiring or a conductive plug, which electrically connects at least two of the plurality of individual elements to each other, or connects the plurality of individual devices to the conductive region of the semiconductor substrate510. In addition, each of the plurality of individual devices may be electrically isolated from another adjacent individual devices by an insulating layer.

FIG.9is a schematic cross-sectional view of a semiconductor package1000daccording to an embodiment.

Referring toFIG.9, the semiconductor package1000dmay include a package substrate10dand at least one semiconductor chip20. The semiconductor package1000dofFIG.9may be different from the semiconductor package1000cofFIG.8with respect to a buried semiconductor chip400, and the remaining configuration thereof, except for the buried semiconductor chip400, may be substantially the same. Hereinafter, duplicate descriptions of the semiconductor package1000dgiven with reference toFIG.9and the semiconductor package1000cgiven with reference toFIG.8are omitted, and differences thereof are mainly described.

The package substrate10dof the semiconductor package1000dmay include the glass substrate100, the plurality of wiring patterns200, the seed layer300, and the second redistribution structure700a. In some embodiments, the semiconductor package1000dmay include at least one of the first redistribution structure700band the second redistribution structure700a. However, hereinafter, a case in which both the first redistribution structure700band the second redistribution structure700aare included is mainly described.

The glass substrate100of the package substrate10dmay include the plurality of through holes110and a cavity120. The plurality of through holes110and the cavity120may extend from the first surface100_S1of the glass substrate100to the second surface100_S2. The horizontal width W_110of each of the plurality of through holes110may decrease along the vertical direction D2. For example, as illustrated inFIG.9, the horizontal width W_110of each of the plurality of through holes110may decrease as the through holes110extend toward the first surface100_S1of the glass substrate100along the vertical direction D2. The plurality of through holes110may include the plurality of through holes110described above.

The cavity120of the glass substrate100may have a structure penetrating the glass substrate100. A horizontal cross-sectional area of the cavity120may have a rectangular shape, but is not limited thereto. For example, the horizontal cross-section of the cavity120may have a polygonal shape other than a circular shape, an elliptical shape, or a rectangular shape, in response to shapes of components arranged in the cavity120.

The plurality of wiring patterns200and the seed layer300of the semiconductor package1000dmay be substantially the same as the plurality of wiring patterns200and the seed layer300inFIG.1.

The first redistribution structure700band the second redistribution structure700aof the semiconductor package1000dmay be arranged on the first surface100_S1and the second surface100_S2of the glass substrate100, respectively. At least one of the first redistribution structure700band the second redistribution structure700amay be electrically connected to the buried semiconductor chip400to be described below. Except for that, the first redistribution structure700band the second redistribution structure700amay be substantially the same as the first redistribution structure700band the second redistribution structure700ainFIG.5.

The buried semiconductor chip400may be arranged inside the cavity120of the glass substrate100. The buried semiconductor chip400may include a semiconductor substrate410and a plurality of chip pads420. In some embodiments, the buried semiconductor chip400may further include a through electrode (not illustrated).

The glass substrate100including the buried semiconductor chip400may have a structure in which the glass substrate100is arranged in the first redistribution structure700band the second redistribution structure700a. For example, the redistribution insulating layer760of each of the first redistribution structure700band the second redistribution structure700amay cover the first and second surfaces100_S1and100_S2of the glass substrate100, and may also cover the upper and lower surfaces of the buried semiconductor chip400.

The redistribution line pattern720or the redistribution via740of the first redistribution structure700bmay be arranged on the plurality of chip pads420of the buried semiconductor chip400. For example, the buried semiconductor chip400may be electrically connected to at least one semiconductor chip20arranged on the second redistribution structure700a, via the second redistribution structure700a. However, the embodiment is not limited thereto, and, although not illustrated, the redistribution line pattern720or the redistribution via740of the first redistribution structure700bmay be arranged on the plurality of chip pads420of the buried semiconductor chip400.

In some embodiments, when the buried semiconductor chip400includes a through electrode, the first redistribution structure700bmay be electrically connected to the second redistribution structure700avia the buried semiconductor chip400.

In some embodiments, the buried semiconductor chip400may include a Si bridge electrically connecting at least two semiconductor chips20arranged on the package substrate10d. In some embodiments, the buried semiconductor chip400may include a Si capacitor, an inductor, an integrated power device (IPD), etc.

Due to the buried semiconductor chip400, the length in the horizontal direction D1and/or the thickness in the vertical direction D2of the semiconductor package1000dmay decrease.

FIGS.10through15are cross-sectional views illustrating a manufacturing method of a semiconductor package according to a process sequence, according to embodiments.

The manufacturing method of the package substrate10may include forming the plurality of through holes110in the glass substrate100, depositing a seed layer P300on one surface of the glass substrate100, forming a conductive structure P200, exposing a portion of the conductive structure P200to the outside by removing a portion of the glass substrate100and the seed layer P300, and removing portions of the conductive structure P200and the seed layer300. Hereinafter, a semiconductor manufacturing method is described in detail with reference toFIGS.10through15.

Referring toFIG.10, the plurality of through holes110may be formed in the glass substrate100. The plurality of through holes110may extend from the second surface100_S2to the first surface100_S1of the glass substrate100along the vertical direction D2. In this case, the plurality of through holes110may not completely penetrate the glass substrate100. For example, the bottom defining the plurality of through holes110may be disposed apart from the first surface100_S1of the glass substrate100by a certain distance H_MA.

In some embodiments, the plurality of through holes110may be formed from the second surface100_S2of the glass substrate100, and accordingly, the horizontal width of the plurality of through holes110may decrease toward the first surface100_S1of the glass substrate100. For example, the sidewall110_S of the glass substrate100defining the plurality of through holes110may be inclined so that a separation distance between the sidewalls110_S of the glass substrate100defining the plurality of through holes110decreases toward the first surface100_S1of the glass substrate100as the through holes110extend along the vertical direction D2.

In some embodiments, the process of forming the plurality of through holes110may be performed by using a wet etching or dry etching process, and thus, there may be no crack on the sidewalls110_S of the glass substrate100defining the plurality of through holes110.

Referring toFIG.11, the seed layer P300may be formed on the second surface100_S2of the glass substrate100. In some embodiments, the seed layer P300may be formed conformal on the second surface100_S2of the glass substrate100and inside the plurality of through holes110(e.g., along the side walls and the bottom of the glass substrate100defining the plurality of through holes110). In some embodiments, the seed layer P300may be formed by using a deposition process, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), and physical vapor deposition (PVD). Accordingly, the seed layer P300may be formed to have a constant thickness on the sidewalls110_S and the bottom of the glass substrate100defining the plurality of through holes110.

In some embodiments, the seed layer P300may include or may be formed of a metal, such as Cu, Al, W, Ti, Ta, In, Mo, Mn, Co, Sn, Ni, Mg, Re, Be, Ga, and Ru, or an alloy thereof, but is not limited thereto.

Referring toFIG.12, the conductive structure P200may be formed to fill the plurality of through holes110and cover the second surface100_S2of the glass substrate100. The conductive structure P200may be formed by using an electroplating process using the seed layer P300as a medium.

Referring toFIG.13, by removing portions of the glass substrate100and the seed layer P300, a first surface P200_S1of the conductive structure P200may be exposed to the outside. When a lower portion of the glass substrate100is removed by using an etching process or a grinding process, a portion formed on the bottom of the seed layer P300defining the plurality of through holes110may be removed together. Accordingly, the first surface P200_S1of the conductive structure P200covered by the seed layer P300may be exposed to the outside. In addition, the first surface300_S1of the seed layer300, from which the bottom portion thereof has been removed, may be exposed to the outside. In this case, the first surface300_S1of the seed layer300, from which the bottom portion thereof has been removed, the first surface P200_S1of the conductive structure P200, and the first surface100_S1of the glass substrate100may be coplanar with each other.

Referring toFIGS.14and15, a plurality of wiring patterns200and the seed layer300may be formed by removing portions of the conductive structure P200and the seed layer P300. In some embodiments, a mask PM may be formed on the upper surface of the conductive structure P200, an etching process may be performed thereon, and the conductive structure P200and the seed layer P300, which are not covered by the mask PM, may be removed.

A portion of the conductive structure P200may be removed, and the conductive structure P200may become the plurality of wiring patterns200including the through electrode210filling the plurality of through holes110and the via pad220covering a portion of the second surface100_S2of the glass substrate100. In some embodiments, the conductive structure P200and the seed layer P300may be removed by using the same mask PM, and thus, the side surface (220S inFIG.2) of each of the plurality of wiring patterns200and the side surface (P_300S inFIG.2) of the seed layer300may be coplanar with each other.

While aspects of the inventive concept have been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.