Nonvolatile semiconductor memory with stabilized level shift circuit

A nonvolatile semiconductor memory including a memory matrix having a plurality of memory cells with nonvolatile memory elements and arranged in the form of a matrix, a selecting circuit for selecting a desired memory cell from the memory matrix, and a read-out circuit for reading out the information stored in the selected memory cell. The read-out circuit includes a sense amplifier and an output buffer. The sensed amplifier includes an inverter having a load element to which a supply voltage is applied and a selected memory cell acting as a driver element. The output buffer includes a level shift circuit for shifting the level of an output signal voltage from the sense amplifier with the level shift circuit including a stabilizing circuit for stabilizing the level of the shifted signal voltage during fluctuations in the supply voltage. An output driver circuit is provided for receiving the shifted signal voltage from the level shift circuit.

BACKGROUND OF THE INVENTION 
The present invention relates to a read only memory (which will be shortly 
referred to as "ROM"), and particularly to a read-out circuit thereof. 
More particularly, the present invention relates to a memory equipped with 
a read-out circuit of the type, in which the memorized data of the memory 
cell of the ROM are read out by detecting whether or not any current flows 
through that memory cell. 
A ROM is divided into (1) an ultraviolet light erasable ROM (which will be 
shortly referred to as "EPROM": Erasable Programmable ROM), (2) an 
electrically alterable ROM (which will be shortly referred to as "EAROM": 
Electrically Alterable ROM), and (3) a PROM (Programmable ROM) such as a 
fuse ROM or a mask ROM (Mask Programmable ROM). 
In a known EAROM, for example, MNOS (structure) type insulated-gate field 
effect transistors (which will be shortly referred to as "MNOS Tr.") are 
arranged in the form of a matrix. In this MNOS Tr., electrons and holes 
are injected by the tunnel effect into the trap at the interface between 
two kinds of insulating layers (i.e., an Si.sub.3 N.sub.4 layer and an 
SiO.sub.2 layer) through an SiO.sub.2 layer which is made thinner than the 
Si side. The MNOS Tr. according to the prior art is shown in section in 
FIG. 1. In this Figure: reference numeral 11 indicates a silicon (Si) 
substrate of N-type conductivity; numerals 12 and 13 indicate diffusion 
layers of P.sup.+ -type conductivity forming the source and drain regions; 
numeral 14 indicates an SiO.sub.2 layer; numeral 15 indicates an Si.sub.3 
N.sub.4 layer; and numeral 16 indicates a gate electrode. By applying a 
positive writing voltage (about +25 V) to the gate electrode of the MNOS 
Tr. having the construction thus far described, the electrons are injected 
into the trap by the tunnel effect so that the threshold voltage of the 
MNOS Tr. can be lowered (e.g., to about +1 V) to establish the written 
state (i.e., the conductive state of the MNOS Tr., which will be shortly 
referred to as "1" state). In order to eliminate this trap of the 
electrons, the inverse operations are effected by impressing a negative 
erasing voltage (at about -25 V) upon the gate electrode so that the 
threshold voltage of the MNOS Tr. can be raised (e.g., to about -8 V) to 
establish the erased state (i.e., the nonconductive state of the MNOS Tr., 
which will be shortly referred to as "0" state). In order to detect the 
difference between the two "0" and "1" states, a reading voltage at about 
-6 V is impressed upon the gate electrode of the MNOS Tr. so that whether 
or not any current flows between the source and drain can be sensed. 
In a known EPROM, on the other hand, floating-gate type insulated-gate 
field effect transistors (which will be shortly referred to as "FAMOS 
Tr.") are arranged in the form of a matrix. A representative of this FAMOS 
Tr. is shown in FIG. 2. In this Figure: numeral 21 indicates an N type Si 
substrate; numerals 22 and 23 indicate P.sup.+ -type diffusion layers 
forming the source and drain regions; numeral 24 indicates an SiO.sub.2 
layer; and numeral 25 indicates a floating gate made of polycrystalline 
Si. In the FAMOS Tr. having the construction thus far described, electrons 
are injected into the floating gate by effecting the avalanche effect 
phenomena between the drain and the substrate when a high voltage is 
impressed between the source and drain so that the writing operation in 
the "1" state can be effected. In case the reading operation is to be 
effected, a conductive state is established between the source and drain, 
when a voltage is impressed inbetween, because an inversion layer is 
formed inbetween if the floating gate is negatively charged. In other 
words, the "0" and "1 " states can be judged in accordance with whether 
the floating gate is negatively charged. The erasure of stored information 
is accomplished by the exposure of an ultraviolet light to discharge the 
electrons from the floating gate. 
Although the foregoing description is directed to the EAROM and EPROM by 
way of example, a variety of other ROMs are known in the art. 
The aforementioned MNOS Tr. and FAMOS Tr. are exemplified by a P channel 
type element but can naturally be exemplified by an N channel type element 
(although the polarity of the voltage to be impressed is inverted). 
A read-out circuit having such charactersitics as are suitable for the ROMs 
thus far described is desired. 
SUMMARY OF THE INVENTION 
In order to stabilize the read-out circuit of the ROMs for the fluctuations 
in the supply voltage, the present invention is featured by the following 
points: 
(1) A variable load resistance source follower is connected at the next 
step of a sense amplifier to effect stabilization for the fluctuations in 
the supply voltage; and 
(2) For the sense amplifier itself, a switching MOS Tr. and a pull-up MOS 
Tr. have their gate voltages stabilized.

DESCRIPTION OF THE PREFERRED EMBODIMENTS 
A read-out circuit for the ROMs is shown in FIG. 3. 
The following description is limited to the case, in which the ROMs are 
composed of N channel elements and in which a reading supply voltage 
V.sub.cc is at 5 V whereas a voltage V.sub.ss is at a grounded level. In 
FIG. 3, reference numeral 31 indicates a decoder; numeral 32 indicates an 
output buffer; letters T.sub.1 and T.sub.2 indicate enhancement mode 
insulated-gate field effect transistors of N channel type (which has a 
threshold voltge, e.g., at 2.5 V); and letter T.sub.3 indicates a 
depletion mode insulated-gate field effect transistor of N channel type 
(which has a threshold voltage, e.g., -3 V). A sense amplifier is 
fundamentally an inverter circuit which uses an element M.sub.1 (e.g., 
MNOS Tr.) of a memory cell as a driver and an insulated-gate transistor 
T.sub.3 (which will be shortly referred to as "MOS Tr.") as a load. 
However, since a mere inverter cannot accomplish the high speed operation 
due to the large stray capacitance of a data line (corresponding to a node 
N.sub.2 in the Figure), the following modification is added. First of all, 
the enhancement mode switching MOS Tr. T.sub.1 is introduced to separate 
the node N.sub.2 from a node N.sub.1. More specifically, if the MOS Tr. 
T.sub.3 charges up the nodes N.sub.1 and N.sub.2 until the latter node 
N.sub.2 is charged to a preset voltage, the MOS Tr. T.sub.1 is cut off, 
and thereafter it is sufficient to charge only the node N.sub.1 so that 
the charging rate can be raised. As a result, when the memory cell is at 
its nonconductive state, the node N.sub.1 reaches the voltage level of 5 V 
at a relatively high rate. On the contrary, when the memory cell is at its 
conductive state, the potentials of the nodes N.sub.1 and N.sub.2 take 
such levels as are determined by the sizes of the enhancement mode MOS Tr. 
T.sub.1 and the transistor M.sub.1 constituting the memory cell and by the 
gate voltage. At this time, the charges stored at the nodes N.sub.1 and 
N.sub.2 are extracted through the transistor M.sub.1 of the memory cell. 
For this operation, it is sufficient to slightly (about 0.3 V) vary the 
potential at the node N.sub.2 having a higher stray capacitance. This can 
lead to the remarkable speed-up in comparison with the simple inverter 
having no switching MOS Tr. T.sub.1. On the other hand, the MOS Tr. 
T.sub.2 is a pull-up device for preventing the potential at the node 
N.sub.2 from being excessively lowered. 
As has been described with reference to FIG. 3, the read-out circuit of 
FIG. 3 has such characteristics as are suitable for the ROM LSI but has 
its maximum drawback that it is weak for the fluctuations in the supply 
voltage. More specifically, if the supply voltage V.sub.cc is raised to a 
higher level than 5 V, the potentials at all the nodes of the sense 
amplifier are also raised so that the potentials (at the both "1" and "0" 
levels) at the output node N.sub.1 of the sense amplifier are also raised. 
As a result, if the voltage V.sub.cc becomes higher than a preset level, 
the inverter circuit of the output buffer 32 at the next step becomes 
inoperative thereby to cause an erroneous operation. These phenomena are 
illustrated in FIG. 4. In FIG. 4: reference letter N.sub.10 indicates the 
change in the "0" level voltage at the node N.sub.1 ; letter N.sub.11 
indicates the change in the "1" level voltage at the node N.sub.1 ; letter 
N.sub.20 indicates the change in the "0" level voltage at the node N.sub.2 
; and letter N.sub.21 indicates the change in the "1" level voltage at the 
node N.sub.2. In case the design is so made that the inverter circuit at 
the next step operates without fail at V.sub.cc =5 V, it is considerably 
difficult that the operation is ensured for the voltage V.sub.cc exceeding 
7 V. 
The present invention will now be described in detail in connection with 
the embodiments thereof. 
A read-out circuit for the ROMs exemplifying the present invention is shown 
in FIG. 5. 
The ROM read-out circuit according to the present invention is basically 
composed of the following four units: a sense amplifier 51; a level shift 
circuit 52 for shifting the level of the signal voltage to be generated by 
the sense amplifier; a waveform restoring circuit 53; and a driver circuit 
54. The three units of the level shift circuit 52, the waveform restoring 
circuit 53 and the driver circuit 54 can be deemed as an output buffer. 
In FIG. 5: reference letters T.sub.1, T.sub.2, T.sub.4, T.sub.5, T.sub.7, 
T.sub.8, T.sub.9, T.sub.11 and T.sub.12 indicate N channel type 
enhancement mode MOS Trs.; letters T.sub.3, T.sub.6 and T.sub.10 indicate 
N channel type depletion mode MOS Trs.; letters V.sub.cc indicate the 
terminal to which the reading supply voltage is applied; letters V.sub.ss 
indicate a ground input terminal; letters OUT indicate an output terminal; 
letter M.sub.1 indicate an element (such as the MNOS Tr. or FAMOS Tr. of N 
channel type); and numeral 55 indicates a decoder. 
First of all, the level shifter (or level shift circuit) 52 will be 
described in the following. Since it is difficult to amplify (or restore 
the waveform of) the output of the sense amplifier 51 because this output 
fluctuates between 5 V and 2.4 V, that level shifter 52 has a conversion 
function to lower the level. The signal after the level shift can be 
amplified and waveform-restored merely through the inverter circuit. The 
level shifter is composed of a usual source follower (having MOS Trs. 
T.sub.4 and T.sub.5), as shown in the Figures by way of example only. By 
means of the circuit composed of the MOS Trs. T.sub.6 and T.sub.7, the 
load transistor T.sub.4 of the source follower has its gate supplied with 
a voltage varying with the supply voltage thereby to impart a supply 
voltage dependence to an effective load resistance so that a stabilized 
source follower can be manufactured. In the circuit according to the 
present invention, under the normal operating condition with the supply 
voltage at 5 V, the output level (having a signal voltage swing of 5 V to 
2.4 V) of the sense amplifier is lowered by about 2 V and converted into a 
signal having a voltage swing of 2.2 V to 0.4 V so that the inverter 
circuits 501, 502 and 503 of the next waveform restoring circuit 53 can be 
amplified. Even with the fluctuations in the supply voltage, the output 
voltage of the source follower is substantially invariable to realize the 
stable operations. 
As a result, the the waveform restoring circuit merely has the inverter 
circuits arranged. 
The driver circuit 54 is a driver circuit which is composed of the MOS Trs. 
T.sub.11 and T.sub.12 in a similar manner to a usual memory while using a 
push-pull amplifier. 
The stabilization of the sense amplifier will be described in the 
following. 
According to the present embodiment, as shown in FIG. 5, the gate voltages 
of the transistors T.sub.1 and T.sub.2 are controlled by a constant 
voltage generation circuit which is composed of the MOS Trs. T.sub.8, 
T.sub.9 and T.sub.10. The output voltages (N.sub.4 and N.sub.5) of the 
constant voltage generation circuit have substantially no dependency upon 
the changes in the supply voltage V.sub.cc, which are larger than 5 V, and 
are held at a constant level so that the dependence of the output voltage 
of the sense amplifier upon the supply voltage is minimized to further 
stabilize the operations of the source follower at the next step. 
The dependencies of the respective node voltages upon the supply voltage 
(V.sub.cc) are illustrated in FIG. 6. In this Figure: letter N.sub.10 
indicates the "0" level voltage at the node N.sub.1 ; letter N.sub.11 
indicates the "1" level voltage at the node N.sub.1 ; letters N.sub.4, 
N.sub.5 and N.sub.6 indicate the voltages at the nodes N.sub.4, N.sub.5 
and N.sub.6, respectively; letter N.sub.30 indicates the "0" level voltage 
at the node N.sub.3 ; and letter N.sub.31 indicates the "1" level voltage 
at the node N.sub.3. As is apparent from FIG. 6, the voltage of the output 
(N.sub.3) of the level shifter is hardly dependent upon the supply voltage 
V.sub.cc so that the waveform restoring inverter circuit at the next step 
can be operated without fail. 
As has been described hereinbefore, according to the present invention, the 
sense amplifier including the source follower can be stabilized as a whole 
in its operation during the fluctuations in the supply voltage so that the 
ROM read-out circuit having a wide margin of operation can be 
manufactured. In comparison with the circuit according to the prior art, 
the circuit according to the present invention has a spare circuit added 
thereto for the one step of the source follower. However, it is well known 
that the source follower circuit has such a low input impedance as to have 
little delay time. As a result, the circuit of the present invention has 
its operation speed prevented from being delayed more than the circuit 
shown in FIG. 3. The circuit of the present invention can rather enjoy the 
higher operation speed than the circuit of the prior art by presetting the 
gate voltages of the transistors T.sub.1 and T.sub.2 of the sense 
amplifier at the most proper levels. FIG. 7 illustrates the results, which 
are plotted in contours from the changes in the operation speed of the 
present sense amplifier such that the gate voltage of the transistor 
T.sub.1 is taken along the abscissa whereas the gate voltage of the 
transistor T.sub.2 is taken along the ordinate. From the Figure, it is 
found that the gate voltages of the transistors T.sub.1 and T.sub.2 can be 
the most properly preset at about 2.5 V while making a difference of about 
0.3 V inbetween and that the circuit of the present invention can be 
raised in its operation speed by a level higher than 20 ns in comparison 
with the conventional circuit (in which the transistors T.sub.1 and 
T.sub.2 are held at the same gate voltage). 
The following description is directed to another embodiment in which the 
read-out circuit according to the present invention is applied to such an 
EAROM of the type shown in FIG. 8A as has been disclosed in a Japanese 
Laid-Open Patent Publication No. 54-57875 laid open on May 5, 1979 
corresponding to the pending U.S. patent application Ser. No. 949,244 and 
as has its memory cell composed of a memory element (MNOS Tr.) and a 
switching element (MOS Tr.). Here, let it be assumed that the MNOS Tr. to 
be used is an N channel element and that, as illustrated by the transfer 
characteristics of FIG. 8B, the threshold voltage is changed by about +2 
V(V.sub.tho) by impressing the writing voltage (higher than +20 V) upon 
the gate electrode whereas the threshold voltage is changed by about -7 V 
(V.sub.thl) by impressing the erasing voltage (higher than -20 V) upon the 
gate electrode. As a result, if the gate electrode of the MNOS Tr. is 
preset at the ground potential, the reading operation of the stored 
information can be effected by rendering the switching MOS Tr, conductive 
and nonconductive. In other words, the reading voltage applied to the gate 
electrode of the MNOS Tr. is at 0 V. 
In the Figure: numeral 81 indicates an Si body of P-type conductivity; 
numerals 82, 83 and 84 indicate impurity regions of N.sup.+ -type 
conductivity; numeral 85 indicates a remarkably thin SiO.sub.2 layer; 
numeral 86 indicates an Si.sub.3 N.sub.4 ; numeral 88 indicates a gate 
insulating layer; and numerals 87 and 89 indicate gate electrodes made of 
polycrystalline silicon (polu Si). 
FIG. 9 shows a block diagram of the EAROM circuit which uses the memory 
cell of FIG. 8A (composed of: an MNOS Tr. 801; a switching MOS Tr. 802; a 
bit line connected with a write inhibition voltage generator 803; a data 
line 804; a writing word line 805; and an addressing word line 806). The 
pins are divided into the following five kinds: 
(1): (Three) Power Supply Input Pins 
V.sub.ss : Ground Potential Terminal; 
V.sub.cc : Power Supply Input Terminal for supplying all the circuits with 
the supply voltage (e.g., +5 V); 
V.sub.p : Programming Voltage (i.e., Write or Erase Voltage, e.g., +25 V) 
Supply Terminal; 
Incidentally, the circuit can be exemplified in accordance with its system 
by a single power supply system in which all the circuits are operated by 
a programming power supply. 
(2) Address Input Pins A.sub.xl to A.sub.xn and A.sub.yl to A.sub.yn : 
Terminals at which an addressing signal for designating the address of a 
memory matrix and the number of which is dependent upon the size of the 
matrix: 
(3) Data Output Pin DOUT: Terminals for generating data in reading mode; 
(4) Data Input Pin DIN: Terminals at which data are received; 
Incidentally, the pins (3) and (4) can be replaced by a common pin as in 
most cases. 
(5) Mode Control Input Pin C.sub.l to C.sub.n : Terminals for feeding such 
a mode control signal to a selective control circuit 903 as can control 
the chip under any of the three modes, i.e., the reading, writing and 
erasing modes. 
The control function such as the chip select may be added, if necessary. 
The number of the pins is dependent upon the number of the control 
functions. 
First of all, the reading operation will be described. In the reading mode, 
one of the switching transistors 802 is selected by means of an address 
buffer 91, a column address decoder 92 and a row address decoder 93. In 
this meanwhile, a writing pulse generator 94, a write inhibition voltage 
generator 95 and an erasing pulse generator 96 are left inoperative so 
that the outputs of the respective pulse voltage generators 94, 95 and 96 
are grounded to the earth. In this state, whether or not any current flows 
through the memory cell selected is detected and generated as the data 
through a column select switch 901 and a sense amplifier 97. 
In the writing mode, the address buffer 91 and the decoders 92 and 93 are 
operated in a similar manner to that in the reading mode. The write pulse 
generator 94 receives the signal from the decoder 93 so that the writing 
voltage pulses (e.g., those having the writing voltage of +25 V and the 
pulse length of 100 .mu.s) at the high voltage V.sub.p are generated on 
the gate line 805 of the one MNOS Tr. selected. Then, the write inhibition 
voltage generator (or storage holding voltage generator) 95 supplies the 
N.sup.+ -type impurity regions of all the MNOS Trs. of the memory cell 
with a write inhibition voltage (or storage holding voltage) V.sub.i 
(e.g., +20 V) which is slightly lower than the programming voltage 
V.sub.p. In case the writing mode is designated by the data input signal 
(for example, for the input signal of "0"), the data line of the memory 
cell selected is lowered to the ground potential because it is derived of 
its current by the input buffer. As a result, the writing operation of the 
memory cell selected is accomplished. Since, in the case of the data input 
at the level "1", the input buffer extracts no current, the memory cell 
selected is also supplied with the write inhibition voltage so that the 
writing operation is not effected. 
In the erasing mode, all the decoders 92 and 93, the write pulse generator 
94 and the write inhibition voltage generator 95 are left inoperative so 
that the erasing voltage pulses at a level V.sub.E (having an erasing 
voltage of +25 V and a pulse length of 10 ms, for example) are generated 
by the erasing pulse generator 96 and impressed upon a memory well (or a 
well diffused region in which the memory cells are provided) or the 
semiconductor body. As a result, all the bits are erased together. 
If an erasing function is desired for each word line, it is sufficient that 
the decoder 93 and the write pulse generator 94 are operated inversely of 
the writing operation and that only the memory gate line 805 selected is 
grounded to the earth while all the other memory gate lines being supplied 
with the same voltage V.sub.E as that of the well. 
FIG. 10 shows an example, in which the read-out circuit according to the 
present invention is applied to the EAROM shown in FIG. 9. In FIG. 10: 
letters E.sub.1 to E.sub.15 indicate N channel type enhancement mode MOS 
Trs.; letters D.sub.1 to D.sub.8 indicate N channel depletion mode MOS 
Trs.; and letter E.sub.13 indicates a switching element (or element) which 
is made responsive to a writing signal r for separating the memory matrix 
and the sense amplifier. Moreover, the output driver circuit push-pull 
driver is so designed that no substrate bias effect results by providing 
the load MOS Tr. E.sub.7 in the P-type well diffused region separated from 
the other circuits (provided that the N-type Si body is used to provide 
the memory matrix and the peripheral circuits in the respective P-type 
wells thereby to constitute the LSI structure). Thus, the present 
invention can enjoy the following effects: (1) the rise time of the signal 
is shortened; and (2) the high level of the output signal is raised. 
The symbols used in FIGS. 3 to 10 will be summarized in the following: 
T.sub.1, T.sub.2, T.sub.4, T.sub.5, T.sub.7, T.sub.8, T.sub.9, T.sub.11 and 
T.sub.12 --Enhancement Mode MOS Trs.; T.sub.3, T.sub.6, T.sub.10, and 
D.sub.1 to D.sub.8 --Depletion Mode MOS Trs.; 51--Sense Amplifier; 
52--Level Shifter; 53--Waveform Restoring Circuit; 54--Driver Circuit; 
55--Decoder; M.sub.1 --Memory Cell; 81--P-Type Si Body; 82, 83 and 
84--N-Type Diffusion Regions; 85--Si.sub.3 N.sub.4 Layer; 86--SiO.sub.2 
Layer; 87--Gate Electrode of MNOS Tr.; 88--SiO.sub.2 Layer; 89--Gate 
Electrode of MOS Tr. (or Switching Transistor); 801--MNOS Tr.; 
806--Addressing Word Line (or Row Address Line for Read-out and Write); 
805--Writing Word Line (or Writing Voltage Impressing Line); 803--Common 
Line (or Bit Line Connected with Write Inhibition Voltage Generator); 
802--MOS Tr.; 91--Address Buffer; 92--Y Decoder (or Column Address 
Decoder); 94--Writing Pulse Generator; 95--Write Inhibition Voltage 
Generator (or Storage Holding Voltage Generator); 96--Erasing Pulse 
Generator; 97--Sense Amplifier; 98--Output Buffer; 99--Input Buffer; 
901--Y Switch (Column Select Switch); 902--Memory Matrix; and 903--Control 
Circuit (or Write, Erasure and Read-out Selecting Circuit).