Clock signal and supply voltage variation tracking

Embodiments disclosed herein provide an apparatus comprising a clock generation circuit configured to generate a first signal for a first time period and a second signal for a second time period, a charge pump circuit coupled to the clock generation circuit and configured to generate a first voltage and a second voltage based, at least in part, on the first time period and the second time period, and a comparison circuit coupled to the charge pump circuit, the comparison circuit configured to compare a difference between the first voltage and the second voltage with a threshold value and generate an active tracking enablement signal in response to determining that the difference between the first and second voltages exceeds the threshold value.

BACKGROUND

Many synchronous semiconductor memories, such as dynamic random access memory (“DRAM”), operate using an input supply voltage and input system clock signal. When the system clock enters into the memory, the clock signal is typically delayed by the internal components of the memory. In order to compensate for the inherent delay in the memory, the memory must synchronize the internal, delayed clock signal with the system clock. Memories typically employ a clock circuit such as a delay locked loop (“DLL”) or a phase locked loop (“PLL”). The clock circuit adjusts the timing of internal clock relative to the external clock to account for the internal delay of the memory and ensures that the internal clock of the memory has a timing relative to the external clock so that memory operations, such providing data, receiving data, and receiving commands and address information, is in phase with the external clock of the system. Additionally, typical memories also include a duty cycle correction circuit (“DCC”) for generating an internal clock signal with a duty cycle of approximately 50%.

In ideal systems, where the external clock signal and the supply voltage are constant in time, a phase detector in the DLL compares the internal clock phase with the external clock phase in order to determine the proper phase delay to apply in providing the internal clock. In the ideal situation, the DLL could discontinue comparing the internal and external clock cycles once a lock is achieved and continue to apply the determined delay in order to lock the internal and external clocks. The process of comparison and determining the necessary delay is typically known as “tracking.” However, external clocks are not ideal clocks because the frequency and duty cycle of the external clock are subject to change over time. Moreover, the magnitude of the supply voltage may also vary over time, causing circuit performance of circuits in the memory to vary as well. The result of these variations is that a determined delay which achieved a lock at one point in time may be insufficient or excessive to achieve a lock at a later point in time.

One way to compensate for the variations in the external clock is to leave DLL tracking on at all times. This method ensures that the internal and external clocks are always locked but is costly in terms of power consumption. Another approach would be to periodically enable DLL tracking based on the activity of the device. For example, DLL tracking may be enabled only when a read event occurs in the device. Periodic DLL tracking represents a lower power alternative to tracking all of the time, but this type of tracking is largely speculative and may enable DLL tracking when no tracking is needed or may fail to enable tracking even when the external clock or system power supply is particularly volatile.

DETAILED DESCRIPTION

Certain details are set forth below to provide a sufficient understanding of embodiments of the invention. However, it will be clear to one skilled in the art that embodiments of the invention may be practiced without these particular details. Moreover, the particular embodiments of the present invention described herein are provided by way of example and should not be used to limit the scope of the invention to these particular embodiments. In other instances, well-known circuits, control signals, timing protocols, and software operations have not been shown in detail in order to avoid unnecessarily obscuring the invention.

Embodiments of the disclosed circuits disclose low power DLL and/or DCC tracking circuits that monitor the signal clock and supply voltage for variations, for example, clock frequency, duty cycle, and/or supply voltage variations, and enable DLL and DCC tracking based on the variations. Enabling DLL and/or DCC tracking means that a DLL circuit and/or a DCC circuit is actively monitoring and modifying the clock signal in order to correct for phase and/or duty cycle distortion.

Embodiments of the present invention will now be described in detail with respect to the several drawings.FIG. 1illustrates an apparatus100(e.g., an integrated circuit, a memory device, a memory system, an electronic device or system, a smart phone, a tablet, a computer, a server, etc.) according to an embodiment of the disclosure. Apparatus100includes a DLL tracking enablement circuit, generally designated100, in accordance with an embodiment of the present invention. The DLL tracking enablement circuit100generally includes a clock generation circuit102, a charge pump104, and a comparison circuit106.

In the embodiment ofFIG. 1, the clock generation circuit102includes a non-overlapping clock generator110. The non-overlapping clock generator110is an electronic circuit that receives a single clock signal as an input and outputs two discrete clock signals that are non-overlapping. That is, the output signals of the non-overlapping clock generator110do not have the same clock level (i.e., a high clock level, or a low clock level) at the same time. In various embodiments, the non-overlapping clock generator110receives the system clock, XCLK108, as an input clock signal. The non-overlapping clock generator110outputs two non-overlapping clock signals, CLKA112and CLKB114. An example non-overlapping clock generator is discussed in further detail below with respect toFIG. 6.

The charge pump104is an electronic circuit that outputs two signals, SensA124and SensB126, which depend on the input clock signals, CLKA112and CLKB114, and variations in a supply voltage116. The charge pump104includes two parallel charging circuits, one for each of the non-overlapping clock signals CLKA112and CLKB114. Each charging circuit includes a pass gate (e.g., pass gate118A or118B), a first capacitor (e.g., capacitor120A or120B), and a second capacitor (e.g., capacitor122A or122B). The first capacitor120and the second capacitor122of a charging circuit may be coupled as capacitor divider circuit. A supply voltage116is provided to each charging circuit. The supply voltage116may be the supply voltage for a memory, such as a DRAM. The pass gates118A and118B may be, for example, transistors that act as switches with CLKA112and CLKB114providing the control signals, respectively. The charging circuits are active when the respective non-overlapping clock signal CLKA112and CLKB114is at a high clock level. In various embodiments, the capacitors120A and120B have the same capacitance. Similarly, the capacitors122A and122B may have the same capacitance. Various embodiments may include greater or fewer capacitors. For each charging circuit, the supply voltage116is provided to a pass gate (i.e., pass gate118A or pass gate118B), which is coupled to a first capacitor (i.e., capacitor120A or capacitor120B). Capacitors120A and120B may each be coupled to a second capacitor (i.e., capacitors122A and122B, respectively), which may then be fed to ground.

When CLKA112is at a high clock level, the charging circuit including capacitors120A and122A is active, and the pass gate118A forms a closed switch which allows current to flow from the supply voltage116and charge the capacitors120A and122A. As the capacitors charge, an output voltage signal SensA124is generated by the charging circuit. The output voltage signal SensA124is proportional to the supply voltage116during the time that the charging circuit is active. Similarly, when CLKB114is at a high clock level, the charging circuit including capacitors120B and122B is active, and the pass gate118B forms a closed switch which allows current to flow from the supply voltage116, charging the capacitors120B and122B. As the capacitors charge, an output voltage signal SensB126is generated by the charging circuit. The output voltage signal SensB126is proportional to the supply voltage116during the time that the charging circuit is active. As previously discussed, CLKA112and CLKB114are non-overlapping clock signals. As a result, SensA124and SensB126represent signals that are proportional to the supply voltage116taken over non-overlapping time periods. Accordingly, if the supply voltage116varies between the time period during which SensA124is generated and the time period during which SensB126is generated, that variation will be manifested as a voltage differential between SensA124and SensB126.

In the embodiment ofFIG. 1, the comparison circuit106receives as inputs SensA124and SensB126. The comparison circuit106is configured to determine a voltage difference between the input signals, and compare the voltage difference to a threshold value in order to determine whether DLL tracking should be enabled. In the embodiment ofFIG. 1, the comparison circuit106includes a sense amplifier128, comparators134A and134B, a NOR gate138and an inverter140. The sense amplifier128may be any type of sense amplifier capable of proportionally amplifying the voltages of SensA124and SensB126relative to one another. The sense amplifier128may output two amplified voltage signals VAH130and VBH132, which are proportional to SensA124and SensB126, respectively.

The comparators134A and134B may be any comparison circuits capable of determining a difference between two voltages (e.g., VAH130and VBH132) and determining whether the difference between the two voltages exceeds a predetermined threshold value. The comparators134A and134B may include static or adaptive hysteresis which may encourage or discourage the enablement or disablement of DLL tracking depending on past states of the comparator. As will be appreciated by one skilled in the art, in embodiments in which comparators134A and134B have adaptive hysteresis, a hysteresis control signal136may be used to control the hysteresis. For example, hysteresis control signal136may provide an analog or digital weighting factor which can favor or disfavor the activation or deactivation of tracking enablement142by altering the threshold value. In the embodiment ofFIG. 1, the comparison circuit106includes two comparators134A and134B. The comparators134A and134B may each receive as inputs VAH130and VBH132. One of the comparators (e.g., comparator134A) may compare the voltage difference of VAH130subtracted from VBH132with the threshold value. If the comparator134A determines that the difference between VBH132and VAH130is greater than the threshold value, then the comparator134A may output a signal indicating that DLL tracking should be enabled. The second comparator (e.g., comparator134B) may compare the voltage difference of VBH132subtracted from VAH130with the threshold value. If comparator134B determines that the difference between VAH130and VBH132is greater than the threshold value, then the comparator134B outputs a signal indicating that DLL tracking should be enabled. By comparing the differences between VAH130and VBH132with two parallel comparators as described above, the comparison circuit106can ensure that DLL tracking is enabled in the event of a positive or negative voltage variation exceeding the threshold value. An example comparator circuit is discussed in more detail below with respect toFIG. 8.

The NOR gate138and the inverter140are used to provide a tracking enable signal142that may be used to enable tracking in response to receiving a signal indicating that the one of the differences between the signals VAH130and VBH132exceeds the threshold value. Accordingly, DLL tracking is enabled when the comparison circuit106determines that the supply voltage116has drifted a sufficient (greater than the threshold value) amount over a certain time period determined by CLKA112and CLKB114. When tracking enable signal142is active, DLL tracking is enabled and actively monitors and modifies the clock signal in order to account for phase variations in the input clock signal. Tracking enable signal142may be provided to, for example, a DLL control circuit which may provide control information to the DLL and manage the delay applied to an input clock signal.

FIG. 2is a functional block diagram of a DLL tracking enablement circuit according to an embodiment of the invention, generally designated200, based on clock frequency variations. The DLL tracking enablement circuit200may generally include a clock generation circuit202, a charge pump204, and a comparison circuit206.

The clock generation circuit202may include a frequency divider244and a non-overlapping clock generator210. The clock generation circuit202receives a clock signal XCLK208, which may be, for example, the external system clock of a DRAM device. In various embodiments, XCLK208may be implemented in similar ways as XCLK108as described above with respect toFIG. 1. The frequency divider244is an electronic circuit that receives XCLK208as an input and outputs a periodic clock signal to the non-overlapping clock generator210. In various embodiments, the clock signal output by the frequency divider244has a frequency that is less than the frequency of XCLK208. In various embodiments, the frequency divider244may be, for example, a configurable 2Ndivider. In general, the frequency divider244may be any integer divider, and may include a duty cycle correction circuit if the frequency divider244divides XCLK208by an odd integer. The non-overlapping clock generator210may be implemented in the same manner as the non-overlapping clock generator110as described above with respect toFIG. 1. The non-overlapping clock generator210receives the frequency divided clock signal from the frequency divider244and generates non-overlapping clock signals CLKA212and CLKB214. A sample non-overlapping clock generation circuit is discussed in further detail below with respect toFIG. 6.

In the embodiment ofFIG. 2, the frequency divider244reduces the frequency of XCLK208. Accordingly, a single clock cycle output by the frequency divider244corresponds to an integer multiple of XCLK208clock cycles. As noted above, the exact frequency of clock cycles of XCLK208may vary with time. Such variations are included in the clock cycle output by the frequency divider244. Therefore, CLKA212and CLKB214generated by the non-overlapping clock generator210represent the time for multiple cycles of XCLK208taken at different points in time. For example, one cycle of CLKA212may represent the time that passed during 2Ncycles of XCLK208beginning at a time t1. Similarly, one cycle of CLKB214may represent the time that passed during 2Ncycles of XCLK208beginning at time t2. Because CLKA212and CLKB214represent the same number of cycles of XCLK208and the frequency of XCLK208is variable with time, the periods of CLKA212and CLKB214may be different. That is, CLKA212and CLKB214have different periods because the frequency of XCLK208may have changed between and/or during the times that divider244generated the divided clock signal.

The charge pump204is an electronic circuit for providing two comparable signals whose voltages depend on CLKA212and CLKB214. The charge pump204receives CLKA212and CLKB214as input signals and outputs two signals SensA224and SensB226with voltages proportional to the periods of CLKA212and CLKB214, respectively. In various embodiments, charge pump204includes two charging circuits. Each charging circuit includes a constant current source216coupled to a pass gate (i.e., pass gate218A or218B). The pass gates218A and218B may be coupled to capacitors220A and220B, respectively. Capacitors220A and220B may be coupled to capacitors222A and222B, respectively, which are coupled to ground. Output signals SensA224and SensB226may be generated between capacitors220A and222A and between capacitors220B and222B, respectively.

Each charging circuit generates an output signal (e.g., SensA224or SensB226) during the time period that the respective input signal (e.g., CLKA212or CLKB214) has a high clock level. When CLKA212has a high clock level, the pass gate218A allows current to flow from the constant current source216through the charging circuit. During the time that CLKA212has a high clock level, the capacitor220A will accumulate charge and develop a voltage differential according to the relationship

V=l·tC,
where l is the constant current provided by the constant current source216, t is the time period during which CLKA212has a high clock level, and C is the capacitance of the capacitor220A. As one skilled in the art will appreciate, the output signal SensA224will have a voltage proportional to the voltage across the capacitor220A, which is proportional to the time period, t, during which CLKA212has a high clock level. Accordingly, the voltage of the output signal SensA224is also proportional to the time period during which CLKA212has a high clock level. The second charging circuit, which includes the constant current source216, the pass gate218B, and the capacitors220B and222B, operates in an analogous manner to the first charging circuit. Accordingly, the output signal SensB226is proportional to the time period during which the input clock signal CLKB214has a high clock level. As noted above, CLKA212and CLKB214may be active for different lengths of time if the frequency of XCLK208changes between or during the sample times over which CLKA212and CLKB214were generated by the frequency divider244. Therefore, a change in the clock frequency of XCLK208between or during the sample times of CLKA212and CLKB214is proportionally reflected as a voltage difference between SensA224and SensB226.

The comparison circuit206is an electronic circuit that amplifies and compares the differences between SensA224and SensB226with a threshold value. The comparison circuit206generally includes a sense amplifier228, comparators234A and234B, NOR gate238and inverter240. In various embodiments, comparison circuit206may be substantially the same as comparison circuit106, as described above with respect toFIG. 1. The sense amplifier228receives SensA224and SensB226as input signals, proportionally amplifies the voltages of the received signals, and outputs signals VAH230and VBH232. An example sense amplifier circuit is discussed below with respect toFIG. 7.

The comparators234A and234B may compare the differences between VAH230and VBH232with a threshold value and outputs a respective signal indicative of whether the difference exceeds the threshold value. For example, one of the comparators (e.g., comparator234A) compares the voltage difference of VAH230subtracted from VBH232with a threshold value. If the comparator234A determines that the difference between VBH232and VAH230is greater than the threshold value, then comparator234A may output a signal indicating that DLL tracking should be enabled. The second comparator (e.g., comparator234B) compares the voltage difference of VBH232subtracted from VAH230with the threshold value. Similarly, if the comparator234B determines that the difference between VAH230and VBH232is greater than the threshold value, then the comparator234B outputs a signal indicating that DLL tracking should be enabled. By comparing the differences between VAH230and VBH232with two parallel comparators as described above, the comparison circuit206ensures that DLL tracking is enabled in the event of an increased or decreased clock frequency variation exceeding the threshold value.

The comparators234A and234B may include static or adaptive hysteresis which may encourage or discourage the enablement of DLL tracking depending on past states of the comparator. In various embodiments in which comparators234A and234B have adaptive hysteresis, a hysteresis control signal236may be used to control the hysteresis, as will be appreciated by one skilled in the art. An example comparator circuit implementing static hysteresis is discussed in more detail below with respect toFIG. 8.

The NOR gate238and the inverter240are used to provide tracking enable signal242that may be used to enable tracking in response to receiving a signal from one of the comparators (234A or234B) indicating that the one of the differences between signals VAH230or VBH232exceeds the threshold value. Accordingly, DLL tracking is enabled when the comparison circuit106determines that the clock frequency of XCLK208has drifted a sufficient (greater than the threshold value) amount over a certain time period, as determined by CLKA212and CLKB214, and the tracking enable signal242is active.

The embodiment ofFIG. 2may be modified in order to monitor both voltage variations (as described with respect to the embodiment ofFIG. 1) and clock frequency variations. In order to monitor both voltage variations and clock frequency variations, the constant current source216may be replaced with the supply voltage of the memory, such as supply voltage116inFIG. 1. In such embodiments, the current of the supply voltage depends upon the variable voltage of the supply. In this embodiment, it is possible for a change in supply voltage and a change in clock frequency to offset each other, in which case DLL tracking would not be enabled.

FIG. 3is a functional block diagram of a DCC tracking enablement circuit according to an embodiment of the invention, generally designated300. The DCC tracking enablement circuit300generally includes a clock generation circuit302, a charge pump304, and a comparison circuit306.

The clock generation circuit302includes a frequency divider344, an AND gate338, and an AND gate340. The clock generation circuit302receives a clock signal XCLK308and a clock signal XCLKF310. In various embodiments, XCLK308may be the system clock and XCLKF310may be the same as XCLK308, but with a phase delay relative to XCLK308. In certain embodiments, XCLK308and XCLKF310may be complimentary signals. However, as will be appreciated by one skilled in the art, overlap may exist as a result of duty cycle variation in the input clock signals XCLK308and XCLKF310. XCLK308and XCLKF310are provided to the frequency divider344. The frequency divider344may be any frequency divider or counter circuit capable of receiving a periodic signal as an input and outputting a periodic signal having a reduced frequency. In various embodiments, the frequency divider344may be implemented in a similar manner to frequency divider244as discussed above with respect toFIG. 2. The output of the frequency divider344defines the time period over which duty cycle variation is being sampled. The AND gate338receives as inputs XCLK308and the output of the frequency divider344. The AND gate338generates an output signal CLKH314which has a high clock level when, during the sample period defined by the output of the frequency divider344, XCLK308has a high clock level. Accordingly, the time during which CLKH has a high clock level is proportional to the duty cycle of XCLK308during the sample period. The AND gate340receives as inputs XCLKF310and the output of the frequency divider344. The AND gate340outputs a signal CLKL316that has a high clock level when, during the sample period defined by the output of the frequency divider344, CLKF has a high clock level. When XCLK308and XCLKF310are complimentary signals, CLKL316is proportional to the time during the sample period that XCLK308has a low clock level (i.e. the compliment of the duty cycle of XCLK308). In other words, either CLKH or CLKL will be active during the sample period, but CLKH and CLKL are not active at the same time.

The charge pump304includes a current source316, pass gates318A and318B, and capacitors320A,320B,322A and322B. In various embodiments, the charge pump304may be implemented in a similar manner as charge pumps104and204as described above with respect toFIGS. 1 and 2. However, because CLKH and CLKL are proportional to the duty cycle of XCLK308, the time during which the two charging circuits of the charge pump304are active is also proportional to the duty cycle of XCLK308. The charge pump304outputs two signals, SensH324and SensL326, which have voltages that are proportional to the high clock level portion and the low clock level portion of XCLK308during the sample time, respectively.

The comparison circuit306receives as inputs SensH324and SensL326and generally includes a sense amplifier328and a comparator334. The comparison circuit306may be implemented in a similar manner as comparison circuits106and206as described above with respect toFIGS. 1 and 2. Sense amplifier328may proportionally amplify SensH324and SensL326to generate VAH330and VBH332. Comparator334may compare a difference between VAH330and VBH332with a threshold value and output an active or inactive tracking enable signal342having a logic level indicative of whether the difference between VAH330and VBH332exceeds a threshold value. The comparator334may include static or adaptive hysteresis, which may be controlled by hysteresis control signal336. As will be appreciated by those skilled in the art, a determination by the comparator334that the difference between VAH330and VBH332exceeds a threshold value indicates that the duty cycle of XCLK308has departed from the ideal 50% by more than a threshold value, and therefore a DCC correction circuit should be enabled to correct for the duty cycle variation. The tracking enable signal342may be provided, for example, to a DCC control circuit capable of managing a duty cycle correction applied to an input clock signal.

FIG. 4is a functional block diagram of a combination DLL and DCC tracking enablement circuit according to an embodiment of the invention, generally designated400. The DLL and DCC tracking enablement circuit400includes clock generation circuits402and414, charge pumps404and416, and comparison circuits406and418. The DLL and DCC tracking enablement circuit400receives a clock signal, XCLK408, and a clock signal, XCLKF412as inputs. The DLL and DCC tracking enablement circuit400outputs a DLL tracking enable signal410and a DCC tracking enable signal420. The clock generation circuit402may be implemented in the same manner as clock generation circuit102or202as described above with respect toFIGS. 1 and 2, respectively. Clock generation circuit414may be implemented in the same manner as clock generation circuit302as described above with respect toFIG. 3. Charge pumps404and416may be implemented in the same manner as charge pumps104,204, and304as described above with respect toFIGS. 1-3. Comparison circuits406and418may be implemented in the same manner as comparison circuits106,206, and306as described above with respect toFIGS. 1-3. The DLL and DCC tracking enablement circuit400provides a customizable composite circuit for determining whether to enable DLL and/or DCC tracking. The embodiment ofFIG. 4recognizes that it may be desirable to have different voltage comparison threshold values or different frequency dividers between the DLL tracking enablement circuit and the DCC tracking enablement circuit. Accordingly, the embodiment ofFIG. 4provides a parallel configuration which allows for customized circuit components between the DLL tracking enablement circuit and the DCC tracking enablement circuit.

FIG. 5is a schematic diagram of an example 2Nfrequency divider circuit according to an embodiment of the invention, generally designated500. The frequency divider circuit500may be used in a DLL and/or DCC tracking enablement circuit. Frequency divider circuit500generally includes a number, N, of D flip-flops504which are linked together in serial such that the inverted output of one D flip-flop504provides the clock signal of the following D flip-flop504. The output of each D flip-flop504has a frequency equal to the frequency of the input clock divided by a power of two. In certain embodiments, the frequency divider500has a division period of less than 256 cycles (i.e., a 28division). In various embodiments, frequency divider500may be implemented as frequency divider244or344as described above with respect toFIGS. 2 and 3. Other frequency divider circuits are possible without departing from the scope of the present disclosure.

FIG. 6is a schematic diagram of a non-overlapping clock generation circuit according to an embodiment of the invention, generally designated600. The non-overlapping clock generation circuit may be used in a DLL and/or DCC tracking enablement circuit. As will be appreciated by one skilled in the art, the clock generation circuit600generally receives a periodic clock signal XCLK602and generates two non-overlapping clock signals CLKA604and CLKB606using NAND gates and inverters with feedback. In various embodiments, clock generator600may be implemented as non-overlapping clock generators110and210as discussed above. Clock generator600represents an example clock generator. Those skilled in the art will recognize that other possible non-overlapping clock generation circuits may be used without departing from the scope of this disclosure.

FIG. 7is a schematic diagram of a sense amplifier according to an embodiment of the invention, generally designated700. The sense amplifier700may be used in a DLL and/or DCC tracking enablement circuit. In various embodiments, sense amplifier700may be implemented as sense amplifier128,228, and/or328, as described above with respect toFIGS. 1-3. As will be appreciated by one skilled in the art, sense amplifier700receives two input signals SensA702and SensB704, proportionally amplifies each input signal through two identical amplifier circuits, and outputs two output signals VAH706and VBH708. SensA702may be implemented as SensA124,224, and/or SensH324, as discussed above with respect toFIGS. 1-3. Similarly, SensB704may be implemented as SensB126,226, and/or SensL326, as discussed above with respect toFIGS. 1-3. VAH706may be implemented as VAH130,230, and/or330, as discussed above with respect toFIGS. 1-3. Similarly, VBH708may be implemented as VAH132,232, and/or332, as discussed above with respect toFIGS. 1-3. The sense amplifier700represents an example sense amplifier. Those skilled in the art will recognize that other possible sense amplifiers may be used without departing from the scope of this disclosure.

FIG. 8is a schematic diagram of a comparator circuit according to an embodiment of the invention, generally designated800. The comparator circuit800may be used in a DLL and/or DCC tracking enablement circuit. In various embodiments, comparator800may be implemented as one or more of comparators134A,134B,234A,234B, or334. As shown inFIG. 8, comparator800may be a differential comparator having two pairs of transistors808and810. As will be appreciated by one skilled in the art, by varying the relative strengths of transistor pairs808and810, a static hysteresis may be applied to the comparator800. The comparator compares the difference between the input signals VAH802and VBH804to a predetermined threshold value and outputs a tracking enable signal806if the comparator800determines that the difference between VAH802and VBH804exceeds the threshold value. In other embodiments, the comparator800may include a feedback loop and/or a hysteresis control signal which allow for adaptive hysteresis capabilities. By using adaptive hysteresis, the comparator800may reduce the frequency with which tracking is enabled and therefore reduce the power consumed by a DLL, a DCC correction circuit, or both. The comparator800represents an example comparator. Those skilled in the art will recognize that other possible comparators may be used without departing from the scope of this disclosure.

FIG. 9is a block diagram of a memory, according to an embodiment of the invention. The memory900may include an array902of memory cells, which may be, for example, volatile memory cells (e.g., dynamic random-access memory (DRAM) memory cells, static random-access memory (SRAM) memory cells), non-volatile memory cells (e.g., flash memory cells), or some other types of memory cells. The memory900includes a command decoder906that may receive memory commands through a command bus908and provide (e.g., generate) corresponding control signals within the memory900to carry out various memory operations. For example, the command decoder906may respond to memory commands provided to the command bus908to perform various operations on the memory array902. In particular, the command decoder906may be used to provide internal control signals to read data from and write data to the memory array902. Row and column address signals may be provided (e.g., applied) to an address latch910in the memory900through an address bus920. The address latch910may then provide (e.g., output) a separate column address and a separate row address.

The address latch910may provide row and column addresses to a row address decoder922and a column address decoder928, respectively. The column address decoder928may select bit lines extending through the array902corresponding to respective column addresses. The row address decoder922may be connected to a word line driver924that activates respective rows of memory cells in the array902corresponding to received row addresses. The selected data line (e.g., a bit line or bit lines) corresponding to a received column address may be coupled to a read/write circuitry930to provide read data to an output data buffer934via an input-output data path940. Write data may be provided to the memory array902through an input data buffer944and the memory array read/write circuitry930.

The memory900may include a clock generator916that includes a delay circuit914. The delay circuit914provides an output clock signal OUT912signal that may be used for clocking circuitry of the memory900. The delay circuit914may include one or more tracking enablement circuits917, which can be activated by a tracking enable signal918, according to embodiments of the invention. For example, the delay circuit914may include a tracking enablement circuit917in accordance with any of the previously described embodiments with reference toFIGS. 1-4.

Those of ordinary skill would further appreciate that the various illustrative logical blocks, configurations, modules, circuits, and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software executed by a processor, or combinations of both. Various illustrative components, blocks, configurations, modules, circuits, and steps have been described above generally in terms of their functionality. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

In the embodiment ofFIGS. 1-4, the variation of frequency and/or the duty cycle of the input clock signal108,208,308,310,408or412are translated into the variation of signal voltage level of the output signals SENSA, SENSB, SENSH or SENSL. The signal voltage level is stored in the capacitors122A,122B,222A,222B,322A,322B as signal information based on a corresponding time period of the input clock signal108,208,308,310,408or412. The signal information stored in the capacitors may also include the variation of supply voltage level of the power supply voltage source VPERI116,216or316. The comparison circuit106,206,306,406,418inFIGS. 1-4is coupled to the capacitors as storage elements and configured to provide a control signal. The control signal may include a tracking enable signal142,242,342,410, and/or420. Those skilled in the art will appreciate that the comparison circuit106,206,306,406,418may be constructed of a logic circuit though the comparison circuit inFIG. 7orFIG. 8is constructed by an analogue circuit.

The embodiment may include steps of monitoring a signal information, such as a variation of supply voltage of the power source, a variation of a frequency and/or a duty cycle of input clock signal, detecting whether the signal information exceeds a predetermined value, and providing a tracking enable signal enabling a tracking enablement circuit, such as a DLL tracking circuit and a duty cycle tracking circuit, if the signal information exceeds the predetermined value.

The comparison circuit may be called a control circuit which can provide a control signal based on two signal information. The control signal can include an active tracking enablement signal enabling an active tracking circuit such as a DLL tracking circuit and a duty cycle tracking circuit. One of the two signal information may be information obtained by monitoring a status such as the voltage source, the frequency or the duty cycle of the input clock signal. The other of the two signal information may be reference information such as a predetermined value or an average value obtained during a predetermined period. Moreover, in the embodiment ofFIGS. 1 and 2, the comparison circuit106,206includes the two comparators134A and134B,234A and234B, respectively, however, those skilled in the art will appreciate that the comparison circuit106,206may be constructed of single comparator with hysteresis control, respectively, like the comparison circuit306inFIG. 3.