Parallel DSP demodulation for wideband software-defined radios

A demodulator, suitable for use in a communication system and in a modem, has a block polyphase circuit with circuit blocks for different signal processing functions, particularly filtering, delay, and frequency conversion. The circuit blocks are arranged for parallel processing of different portions of an input sequence of signals. Signals of the input sequence to be filtered are divided among the blocks by a demultiplexer for processing at a clock frequency lower than a clock frequency of the input signal sequence. Signals outputted by groups of the circuit blocks are summed to produce an output signal of the group. Output signals of all of the groups are multiplexed to provide an output signal sequence such that the repetition frequency of the outputted signals may be higher, lower, or equal to that of the input signal sequence. This enables use of programmable circuitry operative at reduced clock rates.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to construction of demodulation circuitry suitable for use in communication systems and modems with operation at high signal sample rates and, more particularly, to a construction with parallel signal-processing channels for increased bandwidth, and wherein components of the channels are programmable for handling various signal formats.

2. Brief Description of Related Developments

Communication systems are widely used in many situations including communication between persons, as in cellular telephony, and between various forms of equipment, such as between a satellite and a ground station. Various data formats and protocols have evolved to facilitate communication in differing situations. Communication may involve multiple access technologies such as CDMA (code division multiple access), TDMA (time division multiple access), FDMA (frequency division multiple access), modulation technologies such as PSK (phase shift keying), QAM (quadrature amplitude modulation), and FEC (forward error correction) such as Reed Solomon coding, convolutional encoding, and turbo coding, by way of example.

In high-speed communication systems, digital circuitry is generally employed for processing the communicated signals. There is concern that the digital circuitry should be able to function with sufficient speed to handle the high data rates associated with high-speed communication systems.

There is an interest in programmable modems. Programmability and flexibility of a modem can be achieved by digital modems implemented by use of digital hardware such as field programmable gate arrays (FPGAs) and digital signal processors (DSPs). A modem, constructed for use in a communication system, has a modulation section that prepares a signal for transmission to a distant site, and a demodulation section for reception of an incoming signal. Of particular interest herein is a modem, or other communication device, that can handle signals formatted with different ones of the above-noted multiple access technologies, as well as signals having anyone of several forms of modulation from the above-noted modulation technologies.

Industry today, for both commercial and military applications, is requiring modem hardware that is reconfigurable (programmable) by use of software. By way of example, it would be desirable that a telephone operating in the United States would have the capability to operate in Europe upon a reconfiguration of the software. The technology is known in the industry as software-defined radios, and requires that the hardware be programmable. Digital programmable signal-processing devices such as FPGAs and DSPs are employed in the programmable wireless communications technology. These devices provide great flexibility and programmability, but their use, in the prior art, is at the expense of reduced processing speed, as compared to an application-specific integrated circuit (ASIC) by way of example.

To attain increased hardware flexibility, it is necessary to increase the rate of signal processing. By way of example, an increased rate of signal processing would allow for the transmission and the reception of multiple frequency channels, as in a frequency-division multiplex system, and would allow for digital frequency hopping in frequency-hopping spread spectrum systems, thereby eliminating the need for expensive and bulky synthesizers. Higher signal-processing rates allow for increased signal-transmission rates. It is noted that presently available A/D (analog-to-digital) and D/A (digital-to-analog) converters can operate at rates higher than 1000 million samples per second. In contrast, presently available digital signal processing and generation is accomplished at a much slower rate in a digital signal-processing device such as the FPGA. The most common digital signal processing operation is FIR (finite impulse response) filtering, which appears in modulators and demodulators in the form of various processing functions such as decimation, interpolation, pulse shaping, matched filtering, and equalization, by way of example. Known realizations (implementations) of FIR filters result in filters operable only at reduced signal-processing speed when constructed in FPGAs and DSPs due to the speed limitations of these devices.

By way of example in the construction of a demodulation section of a modem employing digital signal processing, an analog-to-digital converter is employed to convert the incoming analog signal to a digitally formatted signal prior to the implementation of the digital signal processing. The digital signal processing involves various forms of filtering, by way of example, and is accomplished generally by use of computational type circuitry such as field programmable gate arrays (FPGAs) and digital signal processors (DSPs). Circuitry employed for conversion from analog signal format to digital signal format is able to operate at a bit rate that is significantly faster than the bit rate for computational circuitry such as the FPGAs and the DSPs. Therefore, at the present time, the limitation on the digital processing speed of a communication channel is in the nature of the construction of a digital filter that has been implemented by an FPGA or a DSP. While an ASIC may be employed to accomplish a filter function at a higher bit rate than an FPGA or a DSP, the ASIC is designed for a specific signal format or modulation, while the FPGA or the DSP have the advantage of being programmable to be adapted readily for a variety of signal formats and modulations. Thus, the digital signal processing circuitry presently available in FPGAs and DSPs introduce a disadvantageous limitation on the maximum bit rate for digital signal processing, such as the filtering of a signal in a demodulator.

SUMMARY OF THE INVENTION

The aforementioned disadvantage is overcome and other benefits are provided by a demodulator constructed of programmable circuitry, including a DSP or a FPGA, so as to obtain the feature of being adaptable to handle various forms of multiple access technologies and various forms of modulation technologies, and wherein various components of the demodulator are implemented in a parallel form of construction. To accomplish the parallel digital signal processing, the demodulator comprises filters constructed as block polyphase filters for performing filtering operations, and the demodulator further comprises circuitry performing the functions of digital down conversion (from a carrier or intermediate frequency to baseband), digital phase shift, carrier phase and frequency recovery, timing recovery, despreading (direct sequence of frequency hopped) for multiple access, and possibly other circuits providing signal processing functions. Each of these circuits is constructed in a parallel channel form of construction, wherein the parallel channels operate concurrently at a relatively low sample rate for performing digital signal processing on a succession of samples of an input signal.

The design of the demodulator is based on digital signal processing with various functions, preferably all functions, implemented in parallel. This form of construction can be implemented in programmable devices such as an FPGA, or DSP, or other parallel or array processor. Due to the parallel nature of the design, parallel or array processors are more suited than sequential, single arithmetic-logic unit general-purpose processors.

In the implementation of the invention, an input sequence of input signal samples is initially demultiplexed to provide sequences of samples to respective ones of the down conversion channels, with the resulting baseband signals being applied to corresponding channels of the block polyphase filter. At the conclusion of the signal processing associated with the respective channels of the block polyphase filter, the output sequences of samples of the respective channels are multiplexed to provide a single output sample sequence from the filter at the relatively high sample rate of the input sample sequence. Alternatively, the output sample rate can be reduced by decimation or increased by interpolation since the block polyphase construction of filter can readily produce either decimation or interpolation.

In the implementation of the demodulator, the input signal, which may have an analog format, is digitized to provide a digital format. The preferred embodiment of the invention is described with reference to a digital signal processing of a succession of digitized input signal samples. Such processing can be described readily in terms of the mathematics of a Z transformation of the input signal samples for describing operation of a block polyphase filter. The implementation of the filter is accomplished in the time domain.

The block polyphase filter comprises plural groups of filters operated concurrently, wherein the filter groups are arranged in a parallel array between a set of input signals and a set of output signals. Each of the filter groups is composed of a set of filter blocks, each of the filter blocks being a polyphase component of the block polyphase filter. The filter blocks are operated concurrently, and are arranged in a parallel array between the set of input signals and the set of output signals. The filter blocks in all of the filter groups operate at a common clock frequency.

To enable the filter to accommodate a high sampling rate, wherein multiple ones of the input signals arrive in succession within a single period of the clock, the succession of input signals is demultiplexed so that, within each filter group, one input signal is applied to each filter block within one clock period. By way of example, if six input signals, in a sequence of the input signals, appear within one period of the clock, the block polyphase filter is constructed of six filter blocks within each filter group. Thus, by demultiplexing the sequence of the input signals, the rate of application of the signals to respective ones of the filter blocks is reduced to one-sixth of the original rate, and is equal to the clock rate for the processing of signals within a filter block.

The block polyphase filter may have a form of construction wherein there are more filter groups than the number of filter blocks within a filter group, this providing for a succession of output signals at a rate which is greater than the input-signal rate. Alternatively, the block polyphase filter may have a form of construction wherein the number of a the filter groups is equal to the number of filter blocks within a filter group, this providing for a succession of output signals at a rate which is equal to the input-signal rate. As a further alternative, the block polyphase filter may have a form of construction wherein the number of filter groups is less than the number of filter blocks within a filter group, this providing for a succession of output signals at a rate which is lower than the input-signal rate. In the situation of the filter providing for an increased output rate of signals, the filter is providing a function of interpolation, and in the situation of the filter providing for a decreased output rate of signals, the filter is providing a function of decimation.

The characteristics of the individual filter blocks and the filter groups are obtained by a mathematical derivation employing a summation of mathematical terms including the impulse response of the filter, as will be described in detail hereinafter, and leading to a matrix formulation wherein the terms of the matrix are the z transform representations of the filter functions provided by the filter blocks in a filter group. A feature of the matrix is that the arrangement of the terms in successive rows of the matrix is obtained as a permutation of the terms of the first row. Furthermore, the terms located below the diagonal of the matrix also include a delay factor equal to the period of the clock. The multiplication of each row of the matrix by the column of the input signals (in the z-transform notation) involves a summation of products to give an output signal from one filter group. The resulting output signals of the respective filter groups may be multiplexed to provide a succession of the output signals.

The ability of the individual filter blocks of the block polyphase filter to operate at a reduced clock rate permits construction of the respective blocks from a DSP or FPGA which is readily programmed to provide a specific signal processing function. This overcomes the need to employ circuitry, such as an ASIC, especially adapted for high-frequency operation, which circuitry would have little or no programmability. Also, use of the set of channels associated with the demultiplexed sequence of input signal samples presents the opportunity for digital down-conversion, in frequency, in accordance with a feature of the invention, whereby the signal processing associated with digital down-conversion can be accomplished at reduced clock rates permitting the use of FPGAs and DSPs.

The demodulator employs the foregoing block polyphase filters and the digital down conversion in conjunction with other demodulator components such as digital phase shift circuitry, numerically controlled oscillators, timing correction circuitry that includes fractional delay/interpolation filters, as well as circuitry providing detection of timing error and carrier phase error. In addition to the block polyphase filters and the digital down conversion circuitry, which are implemented in the parallel mode of construction, other ones of the demodulator components are also implemented in the parallel mode of construction to attain the benefits of the invention. By storing various programs for use in the programmable circuitry (DSP and FPGA) of the demodulator, the demodulator attains the versatility to handle the various multiple-access and modulation technologies described above, while providing the capability to handle signals of higher clock rates and higher bandwidth. It is noted that the invention, in terms of the feature of the parallel mode of construction, can be built as an ASIC to attain a faster signal processing speed, but without the benefit of the programmability provided by the programmable circuitry of a DSP or FPGA. The invention can be implemented also in other programmable devices such as multi-node or parallel or vector (array) processors that contain multiple processing units (such as multipliers and accumulators).

Identically labeled elements appearing in different ones of the figures refer to the same element but may not be referenced in the description for all figures.

DETAILED DESCRIPTION OF THE INVENTION

The ensuing description begins by showing the basic components of a communication system and of a modem. This is followed by further detail in the construction of a demodulator for use in either the communication system or in the modem. The description of the demodulator then continues with detail in: 1. Construction of block polyphase filters; 2. Digital Down-Conversion and Carrier NCO; and 3. Fractional Delay (or interpolation) Filter and Timing NCO.

FIG. 1shows a basic communication system20, wherein information, provided by a source22, is communicated by a communication channel24to be outputted by a transducer26. The information source22, along with a source encoder28, a channel encoder30and a digital modulator32are located on a transmit side34of the communication channel24. The output transducer26, along with a digital demodulator36, a channel decoder38and a source decoder40are located on a receive side42of the communication channel24.

The information provided by the source22is encoded first by the source encoder28and then by the channel encoder30, the encoding being followed by digital modulation in the modulator32preparatory to transmission via the communication channel24. Signals received from the communication channel24undergo digital demodulation at the demodulator36, the demodulation being followed by decoding in the channel decoder38and by further decoding in the source decoder40, whereupon the decoded signals are applied to the output transducer26. The channel encoder30and the digital modulator32are employed with other equipment, such as carrier up-conversion and filtering, employed in the transmission of signals. The demodulation of the digital demodulator36is accomplished with carrier down-conversion and filtering (to be described hereinafter, but not shown inFIG. 1) employed in the reception of signals.

The description of the communication system20presents a one-way communication of data from the information source22to the output transducer26. For two-way communication via outgoing and incoming communication channels, a first modem and a second modem, each having both modulation and demodulation sections as provided by a modem44, would be employed. The modem44is indicated inFIG. 1by means of a dashed line enclosing components of the modem44, these components including the channel encoder30and the digital modulator32for the transmission of signals, and the digital demodulator36and the channel decoder38for the reception of signals. To implement the two-way communication, the modulation section of the first modem would be connected to the transmit side of the outgoing communication channel for transmission of an outgoing signal, and the demodulation section of the second modem would be connected to the receive side of the outgoing communication channel for reception of the outgoing signal. The demodulation section of the first modem would receive a signal on the receive side of an incoming communication channel, which signal is transmitted by the modulation section of the second modem into the transmit side of the incoming communication channel. This description of the demodulation operation of the modem44is a simplified description, and a more detailed description of the demodulator36will be provided hereinafter with reference toFIGS. 2-4. Generally speaking, the modem44provides the functions of the channel encoder/decoder and of the digital modulation/demodulation.

The present invention may be employed for construction of components of a modem, such as the modem44, as well as for construction of components of a communication system, such as the system20. In the practice of the invention, the utilization of programmable circuitry, such as an FPGA or a DSP, is useful in situations wherein a communications device is required to switch rapidly between multiple modes of communication, and this applies equally to use of the demodulator36in the construction of a modem as well as to the construction of a communication system. By way of example, the invention is particularly useful in time-division multiplexing or burst-like communication in which each burst or time slot requires specific characteristics of a modem or communication system, which characteristics differ from a previous time slot or from a subsequent time slot. The specific characteristics are readily attained by the programmable circuitry employed with the invention.

The information source22, by way of example, may be a computer generating digital data (images, video and speech), a video camera converting optical signals to analog electrical signals, or a microphone converting sonic signals to analog electrical signals. The source encoder28operates to convert the analog or digital data signals of the information source22into a bit stream. Also, the source encoder28performs data compression, and outputs a sequence of binary digits to the channel encoder30. The channel encoder30operates to introduce, in a controlled manner, redundancy in a binary information sequence of the bit stream, which redundancy can be used at a receiver to overcome effects of noise and interference which may be encountered in the transmission of a signal through the communication channel24. The added redundancy serves to increase the reliability of the received data.

Examples of codes provided by channel encoders include convolutional codes (decoding using the Viterbi algorithm), Turbo codes, and interleaving for channels with burst errors. The binary sequence outputted by the channel encoder30is applied to the digital modulator, which serves as the interface to the communication channel24. The primary purpose of the digital modulator32is to map the binary information sequence (data bits) into signal waveforms. The digital modulator32performs a shaping of a signal pulse in the time or frequency domain, as well as providing modulation of a carrier. In the case wherein the communication channel is characterized by radiation of the signal into the atmosphere, coupling of a signal from the communication channel24to the demodulator36may be via an antenna (not shown inFIG. 1, but shown inFIG. 2). Generally speaking, the communication channel24is the physical medium that is used to send a signal from a transmitter, located at the transmit side34of the communication channel24, to a receiver, located at the receive side42of the communication channel24. In the case of wireless transmission, the communication channel24may be the atmosphere (free space). Such physical medium, in the case of telephone channels, may include wire lines, optical fiber cables, and wireless (microwave radio).

InFIG. 1, at the receive side42, the demodulator36processes the signal received via the communication channel24, which signal may have been corrupted, and reduces the signal into a sequence of numbers that represent estimates of the transmitted data. The sequence of numbers is passed to the channel decoder38. The channel decoder38reconstructs the original information sequence from knowledge of the codes used by the channel encoder30and the redundancy contained in the received data. Since the demodulator36employs an oscillator that operates independently of a transmitter of the signal, carrier phase and frequency recovery and symbol timing recovery are needed, and circuitry providing these functions will be described below.

The encoding circuitry and the modulation circuitry provide for a variety of signaling formats, in addition to the aforementioned convolutional encoding and Turbo coding, such as CDMA, TDMA, PSK, QAM, and Reed Solomon coding. More specifically, such circuitry provides data processing or formatting for error correction and phase ambiguity resolution for multiuser (TDMA, FDMA and CDMA), spread spectrum by direct sequence (DS) or frequency hopped (FH), and modulation/signaling (PSK, QAM, MSK). The demodulation circuitry and the decoding circuitry provide the inverse of the foregoing encoding and demodulation circuits to recover the information outputted by the source22. While the modulation circuitry and the encoding circuitry, as well as the demodulation and decoding circuitry, may comprise a set of ASICs of which an individual ASIC may provide a specific form of the signal formatting, a preferred embodiment of the invention is constructed of programmable circuitry such as a DSP or a FPGA operative with any one of several programs which may be selected to provide the desired signal formatting. Limited programming may be provided in the ASIC if additional circuitry for the additional functions is built into the ASIC.

Digital processing is readily accomplished in the FPGA. The use of the FPGA is preferred in the construction of the invention because it enables one piece of equipment to be employed for handling any one of several possible signal formatting options. Alternatively, a DSP may be employed for a reduced throughput speed but increased programming capability. An ASIC may also be employed for maximum throughput speed in the situation wherein only a single format is anticipated, or also in any of a plurality of formats if the ASIC is constructed with the additional circuitry required for carrying forth the additional formats.

FIG. 2shows utilization of an antenna46for coupling electromagnetic signals from the communication channel24to the demodulator36ofFIG. 1. InFIG. 2, the signal received by the antenna46is processed by analog down-conversion circuitry48providing for a frequency down-conversion from RF to IF. The received signal at IF is then converted from analog format to digital format by an analog-to-digital converter (ADC)50. The digitized received signal outputted by the converter50, on a single signal channel, is processed by a demultiplexer52to apply the signal via a set of parallel channels to the demodulator36.

FIG. 3shows a simplified view of the digital demodulator36constructed of the parallel signal channels, a more detailed view being provided byFIG. 4. InFIG. 3, the input signal to the demodulator36is provided as a set of parallel signal channels by the demultiplexer52(as described with reference toFIG. 2), the input signal being applied to digital down-conversion circuitry54of the demodulator36. The down-conversion circuitry54includes multipliers56that operate to translate the input signal from an intermediate frequency to baseband and to output the inphase (I) component of the baseband signal. Further multipliers58of the down-conversion circuitry54translate the input signal from the intermediate frequency to baseband for outputting the quadrature (Q) component of the baseband signal. A numerically controlled oscillator (NCO)60provides carrier reference signals for operation of the multipliers56and58, wherein a cosine phase reference signal is provided to the inphase multipliers56and a sine phase reference signal is applied to the quadrature multipliers58. The carrier frequency outputted by the carrier NCO60is established by a control signal, applied via line62, from a carrier recovery loop64(shown inFIG. 4).

The demodulator36further comprises parallel-channel digital filtering circuitry66and68, parallel-channel interpolation circuitry70and72including circuitry with a Farrow structure, and a numerically controlled oscillator (NCO)74providing timing reference signals for operation of the interpolation circuitry70and72. The filtering circuitry66and68provides functions including matched filtering and equalization. The filtering circuitry66receives M inphase signal channels from the multipliers56, where M is the number of the inphase channels. The filtering circuitry68receives M quadrature signal channels from the multipliers58, where M is the number of the quadrature channels. The number of channels N outputted by the filtering circuitry66,68may differ from the number of input channels, as in the case, by way of example, where a filter performs decimation and N is less than M. Signals outputted from the filtering circuitry66and68are applied respectively to the interpolation circuitry70and72. By way of an alternative arrangement of the components, as shown inFIG. 4, the fractional interpolation circuitry70,72may precede various functions of the filtering circuitry66,68. As shown inFIG. 3, the timing NCO74provides complex time reference signals for operation of the interpolation circuitry70and72including portions of the circuitry, wherein the inphase reference is provided to the inphase interpolation circuitry70and the quadrature reference is applied to the quadrature interpolation circuitry72. The set of timing signals outputted by the timing NCO74is established by a control signal, applied via line76, from a timing recovery loop78(shown inFIG. 4). Output signals of the demodulator36are applied to the channel decoder38, as indicated inFIGS. 1,2and4.

FIG. 4shows further detail in the construction of the demodulator36, components of the demodulator36being shown to the right of a dashed line80. Further components including the previously described analog-to-digital converter50and the demultiplexer52are shown to the left of the line80. Also shown to the left of the line80are a phase locked loop (PLL)82and a program memory84. The PLL82provides timing signals for operation of the A/D converter50and the demultiplexer52based on reference timing signals that are applied to the PLL82from line76of the timing recovery loop78. In accordance with a feature of the invention, the components of the demodulator36, shown to the right of the line80, can be fabricated on an FPGA of programmable circuitry so as to accommodate various signal formats, as described above. Various programs may be stored in the program memory84to be applied to various ones of the demodulator components shown to the right of the line80. A specific one of the stored programs, to be employed for operation of the demodulator36, may be selected by a user of communication equipment having the demodulator36.

With fabrication of the equipment by an FPGA, all digital processing can be accomplished in the FPGA. The use of the FPGA is preferred in the construction of the invention because it enables one piece of equipment to be employed for handling any one of several possible formatting options. Alternatively, a DSP may be employed for a reduced throughput speed but increased programming capability. An ASIC may also be employed for maximum throughput speed in the situation wherein only a single format is anticipated, or also in any of a plurality of formats if the ASIC is constructed with the additional circuitry required for carrying forth the additional formats. In the cases of the FPGA and the DSP, optional coding and modulation may be provided for by including in memories of the FPGA and of the DSP instructions for the optional coding and modulation.

By way of example in the operation of the demodulator36,FIG. 4shows the demultiplexer52converting a sequence of input signal samples, received from the A/D converter50, into a set of eight parallel channels of samples of input signals collectively carrying the input signal samples. Each channel operates at a reduced sample rate, in this example, of only one-eighth of the sample frequency of the signal outputted by the A/D converter50. The use of the eight parallel channels enables the down-conversion circuitry54and the following components of the demodulator36to function at a lower clock rate with four inphase signal channels and four quadrature signal channels, in accordance with a feature of the invention.

The demodulator36may include also, by way of example, a low pass filter86with decimation by a factor of2, and a further filter88providing a higher value of decimation. The filters86and88have inphase and quadrature sections, and are arranged serially between the down-conversion circuitry54and the fractional delay of the interpolation circuitry70,72(indicated by a single block inFIG. 4). The fractional delay of the interpolation circuitry70,72is followed by the filtering circuitry66,68(indicated by a single block inFIG. 4) providing matched filter and equalization functions, followed by further signal processing in a circuit90providing the function of signal de-spreading and in a circuit92providing the function of symbol-rate integrate and dump. The de-spread circuit90is employed for direct-sequence spread spectrum signal waveforms. The integrate-and-dump operation of circuit92can be implemented as a filter. Output signals of the integrate-and-dump circuit92are applied to circuitry100providing the functions of timing error detection and loop filtering of the timing recovery loop78, and are applied also to circuitry102providing the functions of phase error detection and loop filtering of the carrier recovery loop64. Output signals of the integrate-and-dump circuit92are applied also, via an offset switch104to another component of a communication system such as the channel decoder38ofFIG. 1.

With respect to the operation of the carrier recovery loop64and the timing recovery loop78, the carrier NCO60includes a register106to receive a phase offset to aid in the acquisition of carrier phase. Also, a summer108is connected between the carrier NCO60and the loop filter of the circuitry102to add a frequency offset to the output of the loop filter of the circuitry102to give a command on line62for acquiring the carrier frequency. A corresponding register110is provided in the timing NCO74to facilitate a closing of the timing loop to null the timing error. A pseudo-noise (PN) generator112provides timing signals, in response to a strobing from the timing NCO74, which also serves as a controller, to operate the de-spread circuit90. The PN generator112generates the code required for despreading a direct sequence spread spectrum signal, and is controlled by the NCO74because it is required to be synchronized with the code on the incoming signal. A symbol-strobe generator114provides timing signals, in response to a strobing from the timing NCO74, to operate the integrate-and-dump circuit92. The controller/timing NCO74applies timing and/or strobe signals to the filter88, the fractional delay of the interpolation circuitry70,72and the filtering circuitry66,68. In the operation of the phase recovery loop64, the circuitry102detects a phase error in the output signals of the integrate-and-dump circuit92, and outputs a signal to the carrier NCO60commanding an adjustment of frequency to null the phase error. A nominal value of frequency for the carrier NCO60is input at116. In similar fashion, in the operation of the timing recovery loop78, the circuitry100detects a timing error in the output signals of the integrate-and-dump circuit92, and outputs a signal to the timing NCO74commanding an adjustment in the timing of strobe signals to null the timing error.

Block Polyphase Filter Construction

FIGS. 5-8show, in block diagrammatic form, four manifestations of filters constructed in the block polyphase form of the invention. This form of construction may be employed for constructing the filters in the circuitry66,68ofFIGS. 3-4as well as the filters86,88ofFIG. 4. Each of the filters ofFIGS. 5-8is described in terms of a filter function represented in Z-transform notation as G(z) wherein a subscript i (i is an integer), as an Gi(z), identifies a polyphase component of the filter. As will be explained subsequently, the filter function is expressed as a mathematical series of which individual terms of the series are identified with the respective ones of the filter components. The filters differ in terms of the ratio of the number of input terminals to the number of output terminals in each of the filters. Thus,FIG. 5shows a filter having two input terminals and six output terminals, and provides a function of interpolation by a factor of three, with a resulting increase in the sample rate by a factor of three.FIG. 6shows a filter having six input terminals and six output terminals, and provides a function of parallel processing without a change in the sample rate.FIG. 7shows a filter having six input terminals and three output terminals, and provides a function of decimation by a factor of two, with a resulting decrease in the sample rate by a factor of two.FIG. 8shows a filter having six input terminals and two output terminals, and provides a function of decimation by a factor of three, with a resulting decrease in the sample rate by a factor of three.

The operation of a filter having the form of the filter ofFIG. 6, wherein the number of input terminals is equal to the number of output terminals, is expressed mathematically by a matrix equation, presented inFIG. 9, for any number of input terminals, wherein each of a plurality of outputs of the filter is obtained by a combination of all of the inputs of the filter multiplied by designated coefficients, as set forth in the matrix equation. Also included in the diagrams ofFIGS. 5-8, as well as in the equation ofFIG. 9, is a delay factor z−1that represents a delay of one period of the clock which drives the filter.FIG. 10shows the matrix equation ofFIG. 9for the case of the six input terminals and the six output terminals of the filter ofFIG. 6.FIG. 11shows the matrix equation for the filter ofFIG. 5, which is derived from the equation ofFIG. 10by deletion of the second column, the third column, the fifth column and the sixth column of the matrix ofFIG. 10.FIG. 12shows the matrix equation for the filter ofFIG. 7, which matrix equation is derived from the equation ofFIG. 10by deletion of the second row, the fourth row, and the sixth row of the matrix ofFIG. 10.FIG. 13shows the matrix equation for the filter ofFIG. 8, which matrix equation is derived from the equation ofFIG. 10by deletion of the second row, the third row, the fifth row and the sixth row of the matrix ofFIG. 10.

In the filter ofFIG. 5the two input lines represent the two input signal channels and are indicated at118, and the filter ofFIG. 6is shown to have six input lines for six input channels, indicated at120. The signals for the input lines118and120may be provided by a demultiplexer, such as the demultiplexer52ofFIGS. 2-4, or alternatively, by the output lines of a preceding filter, as in the case of the low pass filter88ofFIG. 4which receives its set of input signals from the corresponding set of output signals of the low pass filter86.

In the filter ofFIG. 5the six output lines represent six output channels and are indicated at122, and in the filter ofFIG. 6the six output lines representing six output channels are indicated at124. The signals outputted by the output lines122and124may be applied to a multiplexer or, alternatively, may be applied to the input lines of a following filter. To facilitate visualization of the operation of the filters ofFIGS. 5-8, inFIG. 6a demultiplexer126is shown in phantom to demonstrate how the signals for successive ones of the six input lines120can be obtained from a single sequence of the signals applied to the demultiplexer126by a single line128. Also, a multiplexer130is shown in phantom to demonstrate how the signals from successive ones of the six output lines124can be multiplexed onto a single line132for communication to a further component of a signal processing device, by way of example. The operations of the demultiplexer126, the multiplexer130, and individual blocks134of the filter136ofFIG. 6are controlled by timing signals such as the timing signals provided by the timing NCO74ofFIG. 4. Thereby, the operations of the individual filter blocks134ofFIG. 6can be conducted in parallel to give an effective rate of operation to the overall filter136which is much greater than the rate of operation of any one of the filter blocks134.

By way of example in the operation of the demultiplexer126inFIG. 6, in the first set of six signals appearing in the serially supplied signals at line128, the first signal, x(6n−5), is applied to the filter block134identified as G5(z) in the first set of six blocks134as well as to other blocks in further ones of the sets of six blocks134, the second signal, x(6n−4), is applied to the filter block identified as G4(z) as well as to other blocks in further ones of the sets of six blocks134, with the process continuing in similar fashion until the sixth of the signals is applied to the block identified as G0(z) in the first set of six blocks134. The seventh signal of the input series of signals at line128is applied by the demultiplexer126to the same blocks134which received the first signal, and the eighth signal of the input series is applied to the same blocks134which received the second signal, with the process continuing in this fashion. Thereby, each of the filter blocks134in any one set of the six blocks receives only specific ones of the signals of the input sequence on line128and, in this example wherein there are only six filter blocks134in any one of the six sets of the filter blocks, the signals are received at the individual filter blocks134at a rate which is only one-six of the rate at which signals are received via line128at the demultiplexer126.

With reference toFIG. 9, the mathematical description of the operation of a block polyphase (matrix) altering operation is presented in the z-domain by a matrix equation wherein the column matrix on the left side of the equation represents a set of output signals of the filtering operation, and the column matrix on the right side of the equation represents a set of input signals to the filtering operation. In the center square matrix, G0(z), G1(z), . . . are the polyphase components of the filter G(z); X0, X1, . . . are the demultiplexed channels of the input signal X(z); and Y0, Y1, . . . are the demultiplexed channels of the output signal Y(z). The input signal X(z) is given, in the time domain, by xk(n)=x(Mn−k) for K=0, . . . , M−1. The output signal Y(z) is given, in the time domain, by Yk(n)=y(Mn−k) for K=0, . . . , M−1. The terms in successive rows of the matrix are presented as a permutation of the order of the terms appearing in the first row of the matrix. Terms of the matrix appearing below the diagonal of the matrix have the additional delay factor z−1.

For the case of a filter function represented by the six terms, G0(z) through G5(z), appearing inFIG. 6, the first set of the six filter blocks134correspond to the terms in the first row of the matrix, with the six terms being multiplied by their corresponding input signals and being summed together at a summer138to give the corresponding output signal component, identified inFIG. 6in the representation of the time domain. It is readily verified by inspection that the second set of six blocks134corresponds to the terms of the second row of the matrix, with similar relationships being found between the subsequent sets of six blocks134of the filter functions and the subsequent rows of the matrix as is portrayed inFIG. 10.

With reference again toFIG. 5, there are twelve filter blocks134of which the first six filter blocks constitute a first set of the filter blocks and wherein the next six filter blocks constitute a second set of the filter blocks. The two sets of six filter blocks134have polyphase components of the filter G(z), and may be FIR or IIR (infinite impulse response). The polyphase components are identified as G0(z) through G5(z). The blocks134are arranged in groups of two blocks, each group of two blocks being coupled to a summer138for combining the signals outputted by the two blocks of the group. Upon inspection of the matrix equation ofFIGS. 10 and 11, the arrangement of the filter components inFIG. 5is obtained by use of the first input signal X0(z) and the fourth input signal X3(Z), with the remaining four input signals being zeroed. The filter ofFIG. 5may be employed as a 2-to-6 pulse-shaping filter, by way of example, namely that the pulse-shaping filter converts a two channel input signal set to a six channel output signal set. This provides interpolation by a factor of 3. Each of the filter blocks134is a polyphase component of the filter G(z). For the FIR case, the coefficient of the polyphase components (in the time domain) Gi(n) are related to the filter coefficients {h0, h1, . . . , hL} as will be described below.

By way of example in the operation of the filter ofFIG. 5as a pulse shaping filter, input signal of the filter is at the symbol rate, and is interpolated or up-sampled by a factor of preferably 3, which factor provides for proper pulse shaping. Thus, by way of example, if the symbol rate is 200 Msym/s (million symbols per second), the sample rate (after up-sampling by a factor of 3) is 600 Ms/s (million samples per second). With use of the block polyphase (parallel) filter implementation for the pulse-shaping operation, the clock frequency of a digital signal processing device employing the pulse-shaping may be 100 MHz. The rate of the input of the pulse-shaping filter is 2 times 100 which gives 200 Msym/s, and the rate of the output is at 6 times 100 which gives 600 Ms/s.

By way of example in the operation of the filter ofFIG. 6, as an equalization filter, and by way of comparison with the foregoing operation of the filter ofFIG. 5, the filter ofFIG. 6does not change the sample rate between input and output signal channels. However, assuming that the filter would still be running at the clock frequency of the signal processing device (100 MHz in the foregoing example), the filter is effectively processing 600 Ms/s in view of the six input channels and the six output channels of the filter.

The filter136ofFIG. 6is an example of parallel polyphase filter that may be used as an equalization filter for the filtering circuitry66,68ofFIGS. 3-4, and does not change the sample rate. In other words, the input to the filter136ofFIG. 6is 6 times 100 MHz (or 600 Msps) and the output is also 6 times 100 MHz (or 600 Msps). This filter may have FIR or IIR construction, and can be generalized for M-input, N-output and used generally in a high-speed filtering operation. In digital programmable demodulator circuitry, as shown inFIG. 4, this filtering approach is used to decimate, as shown inFIGS. 7-8, by an integer factor by dropping output lines of the filter.

For examples of decimation, reference is made to the filters ofFIGS. 7 and 8. The filter ofFIG. 7employs the same six inputs and as does the filter ofFIG. 6, but provides three outputs to accomplish decimation by a factor of 2. The filter ofFIG. 8employs the same six inputs and as does the filter ofFIG. 6, but provides two outputs to accomplish decimation by a factor of 3. As mentioned above, with reference to the use of the program memory84(FIG. 4) with the components of the demodulator36, the embodiments of the filters shown inFIGS. 5-8can be constructed in programmable format by use of an FPGA or a DSP, in which case the interconnections of the various gates and logic elements, as well as implementation of specific values of filter coefficients can be stored in the memory84. Thereupon, the memory84can be addressed as may be desired for implementing various filter functions for processing signals of various modulations and codes.

A mathematical derivation of the implementation of the block polyphase filters, disclosed above, is presented now. A finite impulse response (FIR) filter is described by the difference equation (relating the input to the output)

or, equivalently, in the z-domain by Y(z)=H(z)X(z), where H(z) is the system function, namely, the z transform of the impulse response h(n), defined as

The impulse response of the FIR system is h(n) for n=0, 1, . . . , K−1, where x(n) and y(n) are respectively the discrete time input and output samples. The samples at the input and the output are separated by a sample time Ts=1/fs. The delay in the filtering operation uses that same sample, Ts. The number representation (namely, fixed point or floating point) of the input samples, output samples, and filter coefficients depends on the application and the required system performance.

An FIR system can be implemented in either a direct form, cascade form, frequency sampling, or lattice realization. The system may be realized also by means of the discrete Fourier transform (DFT), possibly based on the fast Fourier transform (FFT) algorithms. That direct-form realization follows immediately from the non-recursive difference equation (1), and is illustrated inFIG. 14. This is used as an illustrative example. Other realizations can be used instead of using equations derived from Equation (1).FIG. 14shows the direct-form realization of a finite-impulse response (FIR) discrete-time system or filter. The filter coefficients h(n), or equivalently the system transfer function, determine the characteristics of the system, for example, whether the system have a low-pass or high-pass characteristic.

This is a K-tap FIR filter or system described by the filter coefficients h. Generally, a discrete-time system is illustrated pictorially as shown inFIG. 15.FIG. 15presents an FIR filter (or system) represented as a block with input and output discrete-time signals. The term FIR implies that the output is generated from the input using Equation (1). In the block ofFIG. 15, the legend FIR Filter could be marked as H(z), H(w) where w is radian frequency, or h(n) indicating that the system is described by that particular transfer function or impulse response function. These are all different representations of the same system, and the use of one representation over the other in the block ofFIG. 15does not imply a particular realization (or implementation) technique.

An infinite impulse response (IIR) filter or system is described by the difference equation

where the system function namely, the z transform of the impulse response h(n), is defined as

The system is described by the system function H(z) or by the time-domain taps, a(k) and b(k). Just as in the case of the FIR system, there are several types of structures or realizations, including direct-form structures, cascade-form structures, lattice structures, and lattice-ladder structures. As shown in Equation (4), the filter coefficients b(k) for k=0, 1, . . . , K−1, define the zeros in the system and the filter coefficients a(k) for k=0, 1, . . . , L, define the poles (feedback) in the system.

With respect to an IIR system, the term IIR implies that the output is generated from the input. This may be part of a larger system implying that the output, is related to the input by Equation (3) without indicating the particular time realization (or implementation) approach.

The polyphase filter realization is obtained as follows. An FIR or IIR system can be implemented or realized using the polyphase components. That is, a filter or system can be expanded as the sum of sub-filters known as polyphase components. This expansion is useful in decimation and interpolation operations. For the case of an FIR system, Equation (2) can be expanded as follows:

Where Hi(z) are the polyphase components of the filter H(z). The FIR filtering operation using the expansion of Equation (6) is represented in the block diagram shown inFIGS. 16 and 17. A combining of the input-output relationship of Equation (1) in the z-domain with Equation (6) produces

in which the delays are combined with the input signal instead of the filter components as shown in FIGS.16and17. The embodiments ofFIGS. 16 and 17are equivalent and their block diagrams show the polyphase realizations of FIR systems using M filter components. The filtering operation is represented as the sum of M filter components each having K/M non-zero coefficients separated by M−1 zeros. For simplicity, it may be assumed that K is an integer multiple of M (h can be padded with zeros if K is not an integer multiple of M).

Each of the blocks ofFIGS. 16 and 17represent a filter or system that is defined by the difference equation presented in Equations (1) and (2), and can be realized in any structure as discussed above. The order (or number of taps) of each of the polyphase sub-filters is K/M where K is the number of taps in the original filter h(n) and M is the expansion factor.

It is noted that the filter components shown in Equation (9) are an interpolated version (by interpolation factor of M) of the polyphase filter components presented in Equation (10). The non-zero coefficients in Equation (9) are separated by M−1 zeros, which are identified in the z-domain by the expression zMinstead of z.

In the process of decimation, in a sequence of samples outputted by a filter, some of the samples may be deleted (down-sampling). There is no loss of information in the decimation process if the signal is band-limited, and the resulting sample rate, after the decimation, satisfies the Shannon sampling theorem, wherein the sampling rate must be higher than twice the maximum frequency content of the signal. These operations are generally illustrated in a diagram as shown inFIG. 18, wherein the filtering (independent of the method of implementation of the decimation) is running at the sample rate with sample time of Ts=1/fsalthough samples are discarded by the down-sampling operation and are not needed. The operation denoted by the down arrow and letter D is the operation of down-sampling or reducing the sampling rate by a factor of D. For example, if the sample time for x(n) and y(n) is Ts=1/fs, then the sample time for z(n) is D×Ts=1/(fs/D). This operation is a taking of one sample out of D samples as defined by the following equation:
y′(m)=y(Dm)

As an example, let y(n)={0.1, 0.2, 0.3, 0.4, 0.5, 0.6} for n=0, 1, 2, 3, 4, 5, and let D=2, then y′(m)={0.1, 0.3, 0.5}; for m=0, 1, 2, since y′(m)=y(2m) for all m=−0, 1, 2, (or y′(0)=y(0), y′(1)=y(2), and y′(2)=y(4)). These samples and their indices do not in the show the sample rate (namely, time step between samples), but it is understood that if the samples in y are separated by Ts, the samples in y′ are separated by 2Ts. The filtering process (independently of the filter realization) is processing input samples at the high sample rate of 1/Tsalthough samples are discarded by the down-sampling operation that immediately follows the filtering. Such wasteful processing is recovered by use of the polyphase filter realization.

Digital Down-Conversion and Carrier NCO

FIGS. 19-20present graphs of a signal processing operation, useful in understanding the digital down-conversion and operation of the carrier NCO. Samples of a signal are shown being processed through a 2-phase (2-channel) demodulator. These results are not specific to any block of the demodulator36described above, but can be thought of as the input to the demodulator36. Filtered (pulse-shaped) symbols for BPSK modulation with a pattern of 1, 0, 1, 0, 1, 0, are shown in the graph ofFIG. 19. In this example, each symbol is represented by 4 samples; thus the sample rate is 4 times the symbol rate. The samples (indicated by x-o points) are displayed on top of the symbol pattern shown in dashed line. The demodulator signal processing operates on x-o samples at the sample rate (or 4 times the symbol rate). If one assumes a 2-phase parallel demodulator with an FPGA clock rate of 125 MHz, the processing rate is 250 Msps (2 samples per clock in a 2-phase or 2-channel demodulator), and the symbol rate is 250/4 or 67.5 Msymbols/second (4 samples per symbol). The following graphical representation, inFIG. 20, is a set of three graphs showing a clock waveform in the first graph, and presenting the de-multiplexing of the samples of the signal onto the two processing channels, shown as phase1and phase2in the second and the third graphs.

FIG. 21shows further detail in the construction of the digital down-conversion circuitry54, previously described with reference toFIGS. 3 and 4. In particular,FIG. 21shows individual ones of the multipliers56and58, and identifies the reference signals applied to respective ones of the multipliers56,58by the carrier NCO60. Digital down-conversion is achieved by multiplying the input real signal with a cosine reference signal and sine reference signal. The multiply by the cosine function produces the in-phase (I) component, and the multiply by the sine function produces the quadrature (Q) component. This is in a sense digital mixing of the input signal, wherein the input signal is assumed real and has a center frequency of fIF. The sine and cosine references are samples generated by the carrier NCO60in digital format. This is shown in the figure for a 4-phase (or 4-channel) parallel case in which the input signal is denoted IF_l, IF_2, IF_3, and IF_4and the output (I and Q) signals are denoted Iout_l, Iout_2, Iout_3, Iout_4, Qout_l, Qout_2, Qout_3, and Qout_4.

FIG. 22shows further detail in the construction of the carrier NCO60, previously described with reference toFIGS. 3 and 4. The NCO60receives two input control signals, shown at the left of the figure, namely, a signal designating a nominal value of the frequency outputted by the NCO60, and a signal designating a frequency adjustment. On the right side of the figure are shown the reference signals, previously identified inFIG. 21, which are outputted to the multipliers56,58of the down-conversion circuitry54. The NCO60includes sin/cos look-up tables (LUT)140(or alternatively, the sine/cosine functions can be generated using parallel CORDICs phased appropriately) which output the reference signals at142.

The Nominal Frequency is the input command into the carrier (NCO)60, and it is equal to fIF×2nco—width/fs, where fIFis the center frequency of the input signal, nco_width is the number of bits in the NCO register and fsis the sampling rate. The second input to the NCO60, which is added to the Nominal Frequency at summer144, is the Frequency Adjust command, which is the feedback error outputted by the carrier loop filter102(shown inFIG. 4). Therefore, the NCO60can also provide phase error correction, which correction can be disabled by setting the Frequency Adjust to 0.

The carrier NCO60includes an accumulator section146that feeds into a roll-over adjustment section148. The output of the accumulator and roll-over adjustment, provided by the sections146and148, is scaled to match the format expected for addressing the sin/cos LUT140. The carrier NCO60can be used in conjunction with the digital down conversion54to down convert a signal from IF to baseband and to correct for carrier phase error fed into the carrier NCO60via the Frequency Adjust command.

In the accumulator section146, the sum of the frequency commands, as outputted by the summer144, is applied via scale factor elements150to respective ones of parallel channels152, four of the channels152being shown by way of example in this embodiment of the invention. A feedback signal154from one of the channels152, the fourth channel for the MSB (most significant bit) in the roll-over section148, is summed to the scaled frequency commands by summers156in respective ones of the channels152, the summing being accomplished with a negative input from the scale factor elements150. Output signals of the summers156in the respective channels152are applied via delay elements158(providing a delay of one clock period) to further summers160in the roll-over section148. A portion of the MSB signal is drawn off by scale-factor element162and combined with the signals in the respective channels via the further summers160to provide the roll-over adjustment signal. The presence of the delay elements158along with the feedback signal154enable the signals from the summers156to increase in a ramp fashion. Registers in the summers160of the roll-over section148dump excess bits when the maximum value of the summer is reached, this establishing an upper bound of the NCO register width. Also, scaling elements164provide a further limit on the magnitude of signals output by the roll-over section148so as to avoid exceeding the address width of the LUTs140.

By way of alternative embodiment, the carrier NCO60can be used also with a digital phase shift block to correct for carrier phase and frequency errors. In this case, the input signal would be at baseband (complex signal with I and Q components) and the digital down-conversion block would be replaced by a digital phase shift block. The digital phase shift is similar to the digital down conversion except that its input is at baseband instead of real input at IF. The input baseband signal is a complex signal consisting of I and Q components. The digital phase shift block performs a complex multiply of the input signal with the sin and cos samples generated by the carrier NCO. That is the output of the digital phase shift is computed as Iout=I×cos−Q×sin and Qout=I×sin+Q×cos. This operation is performed in parallel. If I and Q at the input are de-multiplexed into 4 each, then the NCO must generate 4 sin and 4 cos samples per clock and perform the following operations at each clock:Iout_1=I_1×cos_1−Q_1×sin_1;Qout_1=I_1×sin_1+Q_1×cos_1Iout_2=I_2×cos_2−Q_2×sin_2;Qout_2=I_2×sin_2+Q_2×cos_2Iout_3=I_3×cos_3−Q_3×sin_3;Qout_3=I_3×sin_3+Q_3×cos_3Iout_4=I_4×cos_4−Q_4×sin_4;Qout_4=I_4×sin_4+Q_4×cos_4

As an example, and with reference to the graphs ofFIGS. 23-27, let the sample rate, fs, be 500 Msps, the clock rate be 125 MHz (or ¼ fs), and the input command frequency, fIF, be 20 MHz. The set of graphs displayed inFIG. 23show the four signals at the output of the roll-over adjustment. The plots show the individual signals for multiple cycles or a total of 100 clocks (at the clock rate of 125 MHz). This shows that the four signals ramp up to the maximum value that can be represented by the NCO register (which is of width nco_width of 32 in this example), then roll-over or wrap around near zero and ramp up again. The four signals ramp up at the same rate, however, they do have a phase offset relative to one another. This can be observed in the compressed graph ofFIG. 24that displays the signals on one graph showing the difference between the four outputs for a few clock periods only.

The signals shown inFIGS. 23-24are scaled (converted to addresses in the range 0 to table_length−1). In this example, a LUT140has512elements (or an adr_width of 9 bits).FIG. 25shows the individual outputs of the cosine look-up table for multiple cycles andFIG. 26shows individual outputs of the sine look-up table for multiple cycles.FIG. 27shows the sine function (dashed line), and cosine function (solid line) when merging (or multiplexing) the 4-phase NCO outputs ofFIGS. 25-26. In the actual design the samples remain de-multiplexed or in parallel and are used to multiply the IF or baseband input signal. This particular example shows an NCO that is clocked at 125 MHz but generates sin/cos samples at 500 Msps (or 4 sine and 4 cosine samples per clock period at the 125 MHz clock).

Fractional Delay Filter and Timing NCO

FIG. 28provides an example of the input and output samples of the parallel fractional interpolation circuitry70,72ofFIGS. 3-4that also can provide the functions of a fractional decimation filter or fractional delay filter. Also shown inFIG. 28are time offsets, Mu, which time offsets are shown also inFIG. 4to serve as commands from the timing NCO74to the circuitry70,72for implementing a delay which is only a fraction of a sample. Accordingly, it is useful to studyFIG. 28for facilitating a description of the timing NCO74and the fractional-delay interpolation circuitry70,72.

InFIG. 28, the input and output samples of a signal applied to the fractional-delay interpolation circuitry70,72are shown serially in time and interleaved on the same time-axis.1,2,3,4are the input channel numbers, and1′,2′,3′,4′ are the output channel numbers for a 4-input, 4-output fractional decimation example. Thus, all the samples marked with1are input to one channel (or phase) and all the samples marked1′ are output from the one channel (or phase) and so on. Associated with each output channel or phase is a fractional value, Mu, equal to the temporal distance away from the input samples. That is, Mu_l is the distance from the location of the desired sample position1′ to the nearest available input sample, in this case,1; and Mu_2is the distance from the location of the desired output location2′ to the nearest available sample, in this case,3.

For a linear interpolation, the sample at desired position1′ is generated using the available samples1and2and the factor Mu_l (which is associated with channel1). The sample at desired position2′ is generated using the available samples3and4and the factor Mu_2(associated with channel2), and so on. It is noted that generating a desired output at any channel i′ may require input samples from more than one channel. For example, generating the output1′ requires the input samples1and2which are present at the input channels1and2. Due to this interleaving of samples, buffering is required at the input of the parallel Farrow structure. This buffering is shown in the block diagrams accompanying the ensuing description. The timing NCO serves as a counter that generates the fractional values Mu_l, Mu_2, Mu_3and Mu_4. As noted above, the foregoing description applies for a linear interpolation. Alternatively, for a higher order interpolation, more samples are employed. For example, with reference toFIG. 28, in the generation of the desired output sample2′, use would be made of the available input samples1′,2′ and3′ (preceding the output sample2′), and the available input sample4(following the output sample2′).

The Farrow structure is employed in the construction of the fractional-delay interpolation circuitry70,72because it is a relatively simple and efficient way of implementing an interpolation function. The Farrow structure can either be a linear, piece-wise parabolic, cubic, or other form of interpolator. The Farrow structure has been used in the literature to perform decimation (or re-sampling) with a fractional factor. By way of example, Farrow structures are shown in L. Erup, F. M. Gardner, and R. A. Harris, “Interpolation in Digital Modems—Part II: Implementation and Performance”, IEEE Transactions on Communications, Vol. 41, No. 6, June 1993, at pages 1001-1002 (hereinafter referred to as “Erup”). It is noted that the teachings of the Farrow structure in the existing literature are limited to a non-parallel single channel case. In this invention, the Farrow structure is implemented in parallel so as to achieve higher processing rates using low FPGA clock speeds (e.g. processing rate of 500 Msps using a 4-phase design running at 125 MHz). Other realizations for fractional decimation can also be used. The Farrow structure is the preferred method for its simplicity.

For example, assume that the sample rate at the input of the Farrow structure is 500 Msps. To decimate to 100 Msps requires decimation by the integer factor of 5, which simply means picking one sample, say the first, out of every five samples. However, to decimate down to 200 Msps from 500 Msps implies that one has to decimate by the non-integer factor of 2.5. This requires generation of samples that are not available in the input sample stream. Such extra samples are generated by interpolation of adjacent samples. The number of samples used in the interpolation depends on the interpolation order. For example, a linear interpolator uses the adjacent samples next to the position of the required output sample.

With reference toFIG. 29, the circuitry of the timing NCO74resembles a portion of the carrier NCO60described above with reference toFIG. 22, and operates in similar fashion. To facilitate a description of the timing NCO74, the same reference numerals, except for the inclusion of the letter “A”, as are employed inFIG. 22are employed also inFIG. 29for corresponding components.

InFIG. 29, the NCO74receives two input control signals, shown at the left of the figure, namely, a signal designating a nominal value of the frequency of timing signals outputted by the NCO74, and a signal designating a frequency adjustment for timing error correction provided on line76by the error detection and filtering circuitry100. The frequency adjustment signal is added to the nominal frequency at a summer144A. On the right side of the figure are shown the time reference signals166, previously described with reference toFIG. 4, which are outputted to the fractional-delay interpolation circuitry70,72, as described above with reference toFIG. 4.

The timing NCO74includes an accumulator section146A that feeds into a roll-over adjustment section148A. The output of the accumulator and roll-over adjustment, provided by the sections146A and148A, is scaled to provide a desired range of timing correction signals. In the accumulator section146A, the sum of the frequency commands, as outputted by the summer144A, is applied via scale factor elements150A to respective ones of parallel channels152A, four of the channels152A being shown by way of example in this embodiment of the invention. A feedback signal154A from one of the channels152A, the fourth channel for the MSB in the roll-over section148A, is summed to the scaled frequency commands by summers156A in respective ones of the channels152A, the summing being accomplished with a negative input from the scale factor elements150A.

Output signals of the summers156A in the respective channels152A are applied via delay elements158A to further summers160A in the roll-over section148A. A portion of the MSB signal is drawn off by scale-factor element162A and combined with the signals in the respective channels via the further summers160A to provide the roll-over adjustment signal. The presence of the delay elements158A along with the feedback signal154A enable the signals from the summers156A to increase, in a ramp fashion. Registers in the summers160A of the roll-over section148A dump excess bits when the maximum value of the summer is reached, this establishing an upper bound of the NCO register width.

InFIG. 30there is shown a form of roll-over adjustment circuitry148B for use in providing the function of the roll-over circuitry148A ofFIG. 29. Comparison of the two circuits shows the channels152A at the left side of the figure, and shows the time reference signals166outputted at the right side of the figure. For each of the channels152A there are provided a bit splitter168, an exclusive-OR gate170, and a bit combiner172. In each of the channels152, the bit splitter168separates the most significant-bit and the next most significant bit from the other bits of the digital signal. The next-most significant bit is applied to the gate170in its respective channel, along with the most significant bit of the fourth channel to produce the gate output signal. In each of the channels, the gate output signal is combined, by the respective bit combiner172, with the remaining bits of the bit splitter168to provide the respective time reference signal166.

FIG. 31shows the Farrow construction of the fractional-delay interpolation circuitry70,72. At the lower left portion of the figure, there are shown the time reference signals166provided by the timing NCO74and described previously with reference toFIGS. 3,4,29and30. In the upper left portion of the figure are shown signals associated with the filter88, described with reference toFIG. 4. On the right side of the figure are shown signals outputted to the filtering circuitry66,68, and referred to above with reference toFIG. 4. The output signals are shown provided in four channels, each channel having a Farrow sub-block174, to be described with reference toFIG. 32. The signals inputted from the timing NCO74are processed respectively in separate channels, wherein the signal in each channel is processed by a Mu Formatter176, to be described with reference toFIG. 33.

InFIG. 31, signal samples and a strobe signal from the filter88are applied to parallel-input shift registers178and180, wherein the signal samples are applied directly to the first of the shift registers178and are applied via scalers182to the second of the shift registers180. The scalers introduce a scale factor of ½. Signals outputted by each of the shift registers178,180are applied to the four. Farrow sub-blocks174via a corresponding set of four vector multiplexers184. The first of the multiplexers184is operated with a Mu coefficient supplied by the first of the formatters176, with the second, the third and the fourth of the multiplexers184being operated respectively with Mu coefficients supplied by the second, the third and the fourth of the formatters176, as indicated in the figure. In similar fashion, the first, the second, the third and the fourth of the formatters176provide Mu coefficients respectively to the first, the second, the third and the fourth of the Farrow sub-blocks174.

It is noted that the filter88at the input to the Farrow circuitry ofFIG. 31, and also the filtering circuitry66,68at the output of the Farrow circuitry are constructed in the block polyphase format. Herein, by way of example, there are four signal channels in the block polyphase construction. The use of the four Mu formatters176in conjunction with the corresponding sets of four vector multiplexers184and four Farrow sub-blocks174enable the four channel processing of the signals of the filter88to be carried forward for processing in four parallel channels of the Farrow circuitry, whereupon the output signals of the Farrow circuitry are presented in four parallel channels to the to the filtering circuitry66,68. By comparing the signal flow paths of the Farrow circuitry ofFIG. 31(including the descriptions to be provided forFIGS. 32 and 33) with the description of the Farrow operation presented the above-noted article by Erup, it is observed that the circuitry ofFIG. 31accomplishes the Farrow operation in the block polyphase construction.

InFIG. 32, the circuitry of one of the Farrow sub-blocks174ofFIG. 31is disclosed, the circuitry being the same for each of the Farrow sub-blocks174. InFIG. 32the Farrow sub-block174comprises a set of summers188,190,192,194,196,198,200and202, and two multipliers204and206. Seven input signals are applied to the Farrow sub-block174, these signals being identified also inFIG. 31, these signals including six signals from the vector multiplexer184and one signal from the Mu Formatter176. The summers188-202serve to combine signals by addition wherein, in some cases indicated by a minus sign, subtraction is performed. The summer188combines the first two signals, and the summer190combines the first two signals with the signal I_1. The summer192combines the output of the188with the third input signal, and the summer194combines the output of the summer190with the third input signal and the signal I_2. The summer196combines the output of the summer192with the fourth input signal, and the summer198combines the output of the summer194with the fourth input signal. The multiplier204multiplies the output of the summer196by the Mu factor to produce a product which is summed by the summer200with the output of the summer198. The output of the summer200is multiplied with the Mu factor by the multiplier206, which product is summed with the signal I_2by the summer202to provide an output sample for the filtering circuitry66,68.

FIG. 33shows operation of one of the Mu Formatters176for converting a timing signal on line166to a Mu signal suitable for operation of the vector multiplexer184and a Mu coefficient for operation of the Farrow sub-block174. The same circuitry is employed in each of the Mu Formatters176. The Mu formatter176includes a bit splitter208and a summer210. The bit splitter208receives the time reference signal on line166and outputs the three most significant bits of the time reference signal to one of the vector multiplexers184. The remaining bits are subtracted from a reference signal at the summer210, with the resulting difference being the Mu coefficient for one of the Farrow sub-blocks174.

It is to be understood that the above described embodiments of the invention are illustrative only, and that modifications thereof may occur to those skilled in the art. Accordingly, this invention is not to be regarded as limited to the embodiments disclosed herein, but is to be limited only as defined by the appended claims.