Memory device and method for fabricating the same

Provided is a memory device including a stack structure, a plurality of first cap layers, and a plurality of second cap layers. The stack structure is located on a substrate. The stack structure includes a plurality of first conductive layers and a plurality of dielectric layers. The first conductive layers and the dielectric layers are stacked alternately. The first cap layers are located on sidewalls of the first conductive layers respectively. The second cap layers are located on sidewalls of the dielectric layers respectively.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a semiconductor device and a method for fabricating the same, and particularly relates to a memory device and a method for fabricating the same.

2. Description of Related Art

With the continuous development of science and technology, the demands to the storage capability also increase as the electronic products continue to improve. To improve the storage capability, memory devices become smaller and have a greater integrity. Thus, the industries now highly focus on three-dimensional memory devices.

However, as the integrity of the three-dimensional memory devices increases, the surface force (e.g., a capillary force, a friction force, and an adhesive force) may significantly influence the stability of the structure of the three-dimensional memory devices due to a high surface-area-to-volume ratio. The influence is particularly significant to the devices having a high aspect ratio. Thus, how to develop a memory device and a method for fabricating the same to prevent the device structure having a high aspect ratio from being bent or collapsing is becoming an issue to work on.

SUMMARY OF THE INVENTION

The invention provides a memory device having cap layers and a method for fabricating the same capable of preventing a device structure having a high aspect ratio from being bent or collapsing.

The invention provides a memory device including a stack structure, a plurality of first cap layers, and a plurality of second cap layers. The stack structure is located on a substrate. The stack structure includes a plurality of first conductive layers and a plurality of dielectric layers alternately stacked with respect to each other. The first cap layers are respectively located on sidewalls of the first conductive layers. The second cap layers are respectively located on sidewalls of the dielectric layers.

According to an embodiment of the invention, a material of the first cap layers is the same as a material of the second cap layers.

According to an embodiment of the invention, a material of the first cap layers is different from a material of the second cap layers.

According to an embodiment of the invention, a material of the first cap layers and a material of the second cap layers include a nitrogen-containing material.

According to an embodiment of the invention, the nitrogen-containing material includes silicon nitride, silicon oxynitride, or a combination thereof.

According to an embodiment of the invention, the memory device further includes a second conductive layer and a charge storage layer. The second conductive layer covers the stack structure. The charge storage layer is located between the stack structure and the second conductive layer. The first cap layers are respectively located between the first conductive layers and the charge storage layer. The second cap layers are respectively located between the dielectric layers and the charge storage layer.

According to an embodiment of the invention, a material of the first cap layers is the same as a portion of materials of the charge storage layer. A material of the second cap layers is different from a portion of the materials of the charge storage layer.

According to an embodiment of the invention, one of the first conductive layers and the second conductive layer is a plurality of gate layers. The other of the first conductive layers and the second conductive layer is a plurality of channel layers.

The invention provides a memory device including a stack structure, a second conductive layer, and a charge storage structure. The stack structure is located on a substrate. The stack structure includes a plurality of first conductive layers and a plurality of dielectric layers alternately stacked with respect to each other. The second conductive layer covers the stack structure. The charge storage structure is located between the stack structure and the second conductive layer. The charge storage structure includes a plurality of first parts and a plurality of second parts. The first parts are located on sidewalls of the first conductive layers. The second parts are located on sidewalls of the dielectric layers. Structures of the first parts at least partially differ from structures of the second parts.

According to an embodiment of the invention, the first parts include silicon nitride/silicon oxide/silicon nitride/silicon oxide.

According to an embodiment of the invention, the second parts include silicon oxynitride/silicon oxide/silicon nitride/silicon oxide.

The invention provides a method for fabricating a memory device, and the method including steps as follows. A stack structure is formed on a substrate. The stack structure includes a plurality of first conductive layers and a plurality of dielectric layers. The first conductive layers and the dielectric layers are alternately stacked with respect to each other. A plurality of first cap layers are respectively formed on sidewalls of the first conductive layers, and a plurality of second cap layers are respectively formed on sidewalls of the dielectric layers.

According to an embodiment of the invention, a process for respectively forming the first cap layers on the sidewalls of the first conductive layers and respectively forming the second cap layers on the sidewalls of the dielectric layers includes performing a surface treatment process.

According to an embodiment of the invention, the surface treatment process includes a nitridation process, an oxynitridation process, or a combination thereof.

According to an embodiment of the invention, the nitridation process includes a plasma process, a chemical vapor deposition process, a physical vapor deposition process, or a combination thereof.

According to an embodiment of the invention, a material of the first cap layers is different from a material of the second cap layers.

According to an embodiment of the invention, a material of the first cap layers and a material of the second cap layers include a nitrogen-containing material.

According to an embodiment of the invention, the nitrogen-containing material includes silicon nitride, silicon oxynitride, or a combination thereof.

According to an embodiment of the invention, the memory device for fabricating the same further includes steps as follows. A second conductive layer is formed on surfaces of the stack structure, the first cap layers, and the second cap layers. The second conductive layer covers the stack structure. A charge storage layer is formed between the stack structure and the second conductive layer.

According to an embodiment of the invention, one of the first conductive layers and the second conductive layer is a plurality of gate layers. The other of the first conductive layers and the second conductive layer is a plurality of channel layers.

Based on above, the first cap layers and the second cap layers are used in the invention to respectively cover the sidewalls of the first conductive layers and the dielectric layers. Since the materials of the first cap layers and the second cap layers are a nitrogen-containing material that is stiffer, the first cap layers and the second cap layers may facilitate the stiffness of the whole stack structure of the invention, so as to prevent the stack structure having a high aspect ratio from being bent or collapsing.

DESCRIPTION OF THE EMBODIMENTS

FIGS. 1A to 1Fare cross-sectional views illustrating a method for fabricating a memory device according to an embodiment of the invention.

Referring toFIG. 1A, first of all, a substrate100is provided. The substrate100may be a semiconductor substrate, a semiconductor compound substrate, or a semiconductor over insulator (SOI) substrate, for example. The semiconductor is IVA group atoms, such as silicon or germanium, for example. The semiconductor compound is formed of IVA group atoms, such as silicon carbide or silicon germanium, or formed of IIIA group atoms and VA group atoms, such as gallium arsenide, for example.

Then, a stack layer102is formed on the substrate100. The stack layer102includes a plurality of conductive layers104and a plurality of dielectric layers106. The conductive layers104and the dielectric layers106are alternately stacked with respect to each other. In an embodiment, a material of the conductive layers104may be doped polysilicon, undoped polysilicon, or a combination thereof, for example, and a method of forming the conductive layers104may include performing a chemical vapor deposition process. A thickness of the conductive layers104may be in a range from 100 nm to 500 nm, for example. A material of the dielectric layers106may be silicon oxide, silicon nitride, or a combination thereof, for example, and a method of forming the dielectric layers106may include performing a chemical vapor deposition process. A thickness of the dielectric layers106may be in a range from 100 nm to 500 nm, for example. Even thoughFIG. 1Aonly illustrates twelve conductive layers104and twelve dielectric layers106, the invention is not limited thereto. In other embodiments, the number of the conductive layers104may be 8, 16, 32, or more, for example. Similarly, one of the dielectric layers106is disposed between two adjacent conductive layers104. Thus, the number of the dielectric layers106may also be 8, 16, 32, or more, for example.

Then, referring toFIGS. 1A and 1B, a mask layer108and a patterned mask layer110are sequentially formed on the stack layer102. In an embodiment, the mask layer108may be an advanced patterning film (APF). A material of the advanced patterning film may include a carbon-containing material, and the carbon-containing material may be amorphous carbon, for example. A material of the patterned mask layer110may be a positive photoresist material or a negative photoresist material, for example. The patterned mask layer110may be formed by performing a photolithography process.

Referring toFIGS. 1B and 1C, using the patterned mask layer110as a mask, an etching process is performed on the mask layer108to remove a portion of the mask layer108, thereby forming a patterned mask layer108a. Then, using the patterned mask layer108aas a mask, an etching process is performed on the stack layer102to remove a portion of the conductive layers104and a portion of the dielectric layers106to form a plurality of openings10and a plurality of stack structures102a. In an embodiment, the openings10expose a surface of the substrate100. The stacked structures102aextend along a first direction D1(i.e., a direction perpendicular to the paper), and the stack structures102aand the openings10are alternately arranged along a second direction D2. In an embodiment, the first direction D1differs from the second direction D2, and the first and second directions D1and D2are perpendicular to each other. When performing the etching process, the patterned mask110may be worn out. Thus, the patterned mask layer108amay remain on the stack structures102a(as shown inFIG. 1C). In this embodiment, an aspect ratio (H1/W1) of the stack structures102amay be in a range from 10 to 50. A width W2of the openings10may be less than 150 nm.

Referring toFIG. 1D, a surface treatment process112is performed, so as to form first cap layers114or second cap layers116on sidewalls of conductive layers104ain the openings10respectively. In an embodiment, when performing the surface treatment process112, the second cap layers116or the first cap layers114may be simultaneously and respectively formed on sidewalls of dielectric layers106ain the openings10respectively. Besides, in another embodiment, when performing the surface treatment process112, third cap layers117may be simultaneously and respectively formed on the surface of the substrate100at a bottom part of the openings10. The surface treatment process112includes a nitridation process, an oxynitridation process, or a combination thereof. The nitridation process may be a plasma process, a chemical vapor deposition process, a physical vapor deposition process, or a combination thereof. In an embodiment, the surface treatment process112is an N2plasma treatment, where a nitrogen-containing gas at a flow rate from 10 sccm to 500 sccm is introduced into a high-vacuum chamber to perform a plasma process under a reaction chamber temperature in a range from 20° C. to 70° C. In this embodiment, the nitrogen-containing gas may be N2, NH3or a combination thereof, for example. However, the invention is not limited thereto. It is not departed from the spirit of the invention as long as the stack structures102aare not removed or only a limited portion of the stack structures102ais removed and cap layers are formed on the sidewalls of the stack structures102ain the surface treatment process. In an embodiment, materials of the first cap layers114, the second cap layers116, and the third cap layers117may be the same or different. The materials of the first cap layers114, the second cap layers116, and the third cap layers117include a nitrogen-containing material, and the nitrogen-containing material may be silicon nitride, silicon oxynitride, or a combination thereof, for example. In an embodiment, the conductive layers104amay be polysilicon, the dielectric layers106amay be silicon nitride, the first cap layers114may be silicon nitride, the second cap layers116may be silicon oxynitride, and the third cap layers117may be silicon nitride. A thickness of the first cap layers114may be 1 nm to 5 nm, for example. A thickness of the second cap layers116may be 1 nm to 5 nm, for example. A thickness of the third cap layers117may be 1 nm to 5 nm, for example.

Referring toFIGS. 1D to 1E, the patterned mask layer108ais removed. Then, a charge storage layer118is formed on the stack structures102a, the first cap layers114, the second cap layers116and the third cap layers117. In an embodiment, the charge storage layer118is conformally formed on surfaces of the stack structures102a, the first cap layers114, the second cap layers116and the third cap layers117. In an embodiment, the charge storage layer118may be a composite layer formed of oxide/nitride/oxide (ONO). The composite layer may include three or more layers, for example. However, the invention is not limited thereto. A method of forming the charge storage layer118may include performing a chemical vapor deposition process, for example.

It should be noted that, since the first cap layers114and the second cap layers116are respectively formed on the sidewalls of the first conductive layers104aand the dielectric layers106abefore the patterned mask layer108ais removed, the first and second cap layers114and116may reinforce a strength of the whole stack structures102a. Thus, when the mask layer108ais removed, an influence of a surface force (e.g., a capillary force, a friction force, and an adhesive force) on the stack structures102ain this process is reduced, thereby maintaining a stability of the stack structures102a.

Then, referring toFIGS. 1E and 1F, a conducive layer120is formed on the charge storage layer118. In an embodiment, the conductive layer120is conformally formed on the charge storage layer118. However, the invention is not limited thereto. In other embodiments, the conductive layer120may also fill the openings10. A material of the conductive layer120may be doped polysilicon, undoped polysilicon, or a combination thereof, for example, and a method of forming the conductive layer120may include performing a chemical vapor deposition process. A thickness of the conductive layer120may be in a range from 10 nm to 20 nm, for example. A subsequent process may include steps such as a step of further patterning the conductive layer120. However, details in this respect are not described in the following.

Referring toFIG. 1F, the invention provides the memory device including the stack structures102a, the charge storage layer118, the conductive layer120, the first cap layers114, and the second cap layers116. The stack structures102aare located on the substrate100. The stack structures102ainclude the conductive layers104aand the dielectric layers106a. The conductive layers104aand the conductive layers106aare alternately stacked with respect to each other. In an embodiment, the conductive layers104amay be a gate layer (also referred to as a word line), for example, and the conductive layer120may be a channel layer (also referred to as a bit line), for example. However, the invention is not limited thereto. In other embodiments, the conductive layers104amay also be a channel layer (also referred to as a bit line), for example, and the conductive layer120may be a gate layer (also referred to as a word line). The first cap layers114are located on the sidewalls of the conductive layers104a. The second cap layers116are located on the sidewalls of the dielectric layers106a. The charge storage layer118is located on the surfaces of the stack structures102a, the first cap layers114, and the second cap layers116. The second conductive layer120is located on the charge storage layer118. In an embodiment, the first cap layers114and a portion of the charge storage layer118covering the first cap layers114may be referred to as first parts P1. The second cap layers116and a portion of the charge storage layer118covering the second cap layers116may be referred to as second parts P2. A structure of the first parts P1and a structure of the second parts P2are at least partially different. In an embodiment, the structure of the first parts P1may be formed of silicon nitride114/silicon oxide118a/silicon nitride118b/silicon oxide118c(in an extending direction from the surface of the stack structures102atoward the charge storage layer118), for example, while the structure of the second parts P2may be formed of silicon oxynitride116/silicon oxide118a/silicon nitride118b/silicon oxide118c, for example. However, the invention is not limited thereto. Compared with the dielectric layers106a, the materials of the first cap layers114and the second cap layers116are stiffer. The Young's Module thereof may be in a range from 220 GPa to 270 GPa, for example. Thus, the first cap layers114and the second cap layers116may facilitate a stiffness of the whole stack structures102a, so as to reduce the influence of the surface force (e.g., a capillary force, a friction force, and an adhesive force), thereby preventing the stack structure having a high aspect ratio from being bent or collapsing.

Also, under a circumstance that one of the conductive layers104ais a word line, and the conductive layer120is a bit line, in an erase operation, since the first cap layers114on the surfaces of the conductive layers104ahave a certain thickness, the first cap layers114may prevent gate injection of electrons into the charge storage layer118, so as to improve the window in the erase operation.

In view of the foregoing, the first cap layers and the second cap layers are used in the invention to respectively cover the sidewalls of the first conductive layers and the dielectric layers. Since the materials (e.g., the nitrogen-containing material) of the first cap layers and the second cap layers are stiffer, the first cap layers and the second cap layers may facilitate the stiffness of the whole stack structure of the invention, so as to reduce the influence of the surface force (e.g., a capillary force, a friction force, and an adhesive force), thereby preventing the stack structure having a high aspect ratio from being bent or collapsing. Moreover, the first cap layer on the surface of the conductive layer may also prevent gate injection of electrons into the charge storage layer, so as to improve the window in the erase operation.