Delay locked loop for controlling delay time using shifter and adder and clock delaying method

A delay locked loop that controls a delay time period by using a shifter and an adder includes a master delay locked loop and a slave delay locked loop. The master delay locked loop outputs a first digital value corresponding to one clock cycle of a first input clock signal. The slave delay locked loop receives the first digital value and delays a second input clock signal for a time period smaller than the one clock cycle of the first input clock signal. The slave delay locked loop includes a shifter, an operator, and a variable delay circuit. The shifter shifts the first digital value to generate a second digital value. The operator adds or subtracts an offset value to or from the second digital value to generate a third digital value, wherein the offset value varies according to a process, a voltage, and a temperature (PVT). The variable delay circuit delays the second input clock signal for a time period corresponding to the third digital value.

CROSS-REFERENCE TO RELATED PATENT APPLICATION

This application claims the benefit of Korean Patent Application No. 10-2007-0016792, filed on Feb. 16, 2007, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

BACKGROUND OF THE INVENTION

1. Technical Field

The present disclosure relates to a delay locked loop and, more particularly to a delay locked loop that controls a delay time period by using a shifter and an adder.

2. Discussion of Related Art

Delay locked loops (DLLs) remove a skew between an external clock signal input to an internal circuit and an internal clock signal used in the internal circuit. DLLs detect a difference between phases of the external clock signal and the internal clock signal and compensate for the detected phase difference, thereby removing a skew between the external clock signal and the internal clock signal.

SUMMARY OF THE INVENTION

Exemplary embodiments of the present invention provide a delay locked loop that controls a delay time period by using a shifter and an adder.

According to an exemplary embodiment of the present invention, there is provided a delay locked loop including: a master delay locked loop that outputs a first digital value corresponding to one clock cycle of a first input clock signal; and a slave delay locked loop that receives the first digital value and delays a second input clock signal for a time period smaller than the one clock cycle of the first input clock signal, wherein the slave delay locked loop includes: a shifter that shifts the first digital value to generate a second digital value; an operator that adds or subtracts an offset value to or from the second digital value to generate a third digital value, wherein the offset value varies according to a process, a voltage, and a temperature (PVT); and a variable delay circuit that delays the second input clock signal for a time period corresponding to the third digital value.

The shifter may shift bits included in the first digital value to the right.

The variable delay circuit may include a plurality of unit delay units serially connected to one another, each having a unit delay time period. The second input clock signal may be transmitted to some or all of the unit delay units, so as to be delayed for a time period corresponding to the third digital value.

Each of the unit delay units may include a buffer and a multiplexer. The buffers of the unit delay units may be serially connected to one another, the multiplexers of the unit delay units may be serially connected to one another, and the multiplexer of each of the unit delay units may select one of an output signal of a corresponding buffer and an output signal of a multiplexer immediately before it.

The delay locked loop may further include a decoder that receives the third digital value and generates selection signals in order to select some unit delay units to which the second input clock signal is to be transmitted from the plurality of unit delay units.

In a half-detection mode, the master delay locked loop may output a first digital value corresponding to half of one clock cycle of the first input clock signal.

The delay locked loop may further include a shift control unit that sets a shift value of the shifter in response to a half-detection mode signal that indicates the half-detection mode.

According to an exemplary embodiment of the present invention, there is provided a delay locked loop comprising: a master delay locked loop that detects a value corresponding to one clock cycle of a first input clock signal; and a slave delay locked loop that receives the value corresponding to one clock cycle of the first input clock signal and delays a second input clock signal for a time period smaller than the one clock cycle of the first input clock signal, wherein the slave delay locked loop includes: a shifter that divides the value corresponding to one clock cycle of the first input clock signal by a predetermined shift value to generate a second digital value; an operator that adds or subtracts an offset value to or from the second digital value to generate a third digital value, wherein the offset value varies according to a process, a voltage, and a temperature (PVT); and a variable delay circuit delaying the second input clock signal for a time period corresponding to the third digital value.

According to an exemplary embodiment of the present invention, there is provided a delay locked loop including: a shifter that shifts a first digital value corresponding to one clock cycle of a first input clock signal to generate a second digital value; an operator that adds or subtracts an offset value to or from the second digital value to generate a third digital value, wherein the offset value varies according to a process, a voltage, and a temperature (PVT); and a variable delay circuit that delays the second input clock signal for a time period corresponding to the third digital value.

The shift value may be a natural number greater than 1.

According to an exemplary embodiment of the present invention, there is provided a clock delaying method including the operations of: detecting a first digital value corresponding to one clock cycle of a first input clock signal; and receiving the first digital value and delaying a second input clock signal for a time period smaller than one clock cycle of the first input clock signal, wherein the operation of delaying the second input clock signal includes the sub-operations of: shifting the first digital value to generate a second digital value; adding or subtracting an offset value to or from the second digital value to generate a third digital value, wherein the offset value varies according to a process, a voltage, and a temperature (PVT); and delaying the second input clock signal for a time period corresponding to the third digital value.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

The attached drawings for illustrating exemplary embodiments of the present invention are referred to in order to gain a sufficient understanding of the present invention, the merits thereof, and the objectives accomplished by the implementation of exemplary embodiments of the present invention.

Hereinafter, the present invention will be described in detail by explaining exemplary embodiments of the present invention with reference to the attached drawings, wherein like reference numerals denote like elements.

FIG. 1is a block diagram of a delay locked loop (DLL) according to an exemplary embodiment of the present invention. Referring toFIG. 1, the DLL100includes a master DLL110and a slave DLL130.

The master DLL110detects a first digital value CNTA corresponding to one clock cycle of a first input clock signal CLK. The master DLL110may include a variable delay circuit112, a decoder114, a delay control circuit116, and a phase detector118.

The variable delay circuit112delays the first input clock signal CLK for a predetermined period of time to generate a first delay clock signal DCLK. The phase detector118detects a difference between phases of the first input clock signal CLK and the first delay clock signal DCLK to generate a lead signal LEAD or a lag signal LAG. For example, when the phase of the first input clock signal CLK is ahead of the phase of the first delay clock signal DCLK, the lead signal LEAD may be generated, and when the phase of the first input clock signal CLK is behind that of the first delay clock signal DCLK, the lag signal LAG may be generated. In response to the lead signal LEAD or the lag signal LAG, the delay control circuit116and the decoder114control the first delay clock signal DCLK and the first input clock signal CLK to have a phase difference corresponding to one clock cycle. More specifically, the delay control circuit116outputs a first digital value CNTA corresponding to one clock cycle of the first input clock signal CLK, and the decoder114decodes the first digital value CNTA to output a first decoded value set SEL1fed to the variable delay circuit112. The variable delay circuit112delays the first input clock signal CLK for a period of time corresponding to the first decoded value set SEL1.

The slave delay locked loop130delays a second input clock signal IN for a time period shorter than one clock cycle of the first input clock signal CLK. The slave delay locked loop130includes a shifter136, an operator138, and a variable delay circuit132.

The shifter136shifts the first digital value CNTA to generate a second digital value CNTB. The shifter136can shift the bits of the first digital value CNTA to the right. Depending on the number of bits by which the shifter136shifts the bits included in the first digital value CNTA, a ratio of the first digital value CNTA to the second digital value CNTB varies. For example, when the shifter136shifts the bits included in the first digital value CNTA by one bit and the first digital value CNTA corresponding to one clock cycle of the first input clock signal CLK is ‘1000’, the second digital value CNTB is ‘0100’. Accordingly, the second digital value CNTB is half of the first digital value CNTA. Also, when the shifter136shifts the bits included in the first digital value CNTA by two bits and the first digital value CNTA corresponding to one clock cycle of the first input clock signal CLK is ‘1000’, the second digital value CNTB is ‘0010’. Accordingly, the second digital value CNTB is a quarter of the first digital value CNTA. Thus, the second digital value CNTB corresponds to a time period obtained by dividing one clock cycle of the first input clock signal CLK by a multiple of an integer. In other words, the second digital value CNTB corresponds to a time period shorter than one clock cycle of the first input clock signal CLK.

The operator138may be an adder/subtractor, and adds or subtracts a received offset value OFV, which varies according to a process, a voltage, and a temperature (PVT), to or from the second digital value CNTB and outputs a result of the addition or subtraction as a third digital value CNTC. Accordingly, the DLL100can compensate for the received offset value OFV. In other words, the third digital value CNTC output from the operator138is a value on which compensation according to PVT has been performed.

A decoder134decodes the third digital value CNTC to output a second decoded value set SEL2fed to the variable delay circuit132. The variable delay circuit132delays a second input clock signal IN for a period of time corresponding to the second decoded value set SEL2to output an output clock signal OUT. Alternatively, if the decoder134is omitted, the variable delay circuit132delays the second input clock signal IN for a time period corresponding to the third digital value CNTC and outputs the output clock signal OUT.

FIG. 2is a circuit diagram of the variable delay circuit132or112included in the DLL100illustrated inFIG. 1.

Referring toFIG. 2, the variable delay circuit132may include a plurality of unit delay units DU1through DUn. The unit delay units DU1through DUn are serially connected to one another and each has a unit delay time period. The second input clock signal IN is transmitted to some of the unit delay units DU1through DUn and delayed for the time period corresponding to the third digital value CNTC. For example, transmission of the second input clock signal IN to only the first five unit delay units DU1through DU5is illustrated inFIG. 2. Accordingly, the variable delay circuit132delays the second input clock signal IN five times longer than the unit delay time period.

Each of the unit delay units DU1through DUn may include a buffer and a multiplexer. The buffers BUF1through BUFn of the unit delay units DU1through DUn are serially connected to one another, and the multiplexers MUX1through MUXn thereof may also be serially connected to one another. Each of the multiplexers MUX1through MUXn may select either an output signal of a corresponding buffer or an output signal of a multiplexer immediately preceding the subject multiplexer and output the selected signal. For example, the multiplexer MUX5of the fifth unit delay unit DU5selects an output signal of a corresponding buffer BUF5, and the multiplexers MUX1through MUX4of the first through fourth unit delay units DU1through DU4select output signals of multiplexers immediately preceding the respective multiplexers. Accordingly, the second input clock signal IN can be transmitted to only the five unit delay units DU1through DU5.

Referring back toFIG. 1, the DLL100may optionally include the decoder134. Referring toFIG. 2, the decoder134decodes the third digital value CNTC and generates selection signals SEL1through SELn in order to select some unit delay units, for example, the unit delay units DU1through DU5, to which the second input clock signal IN is transmitted, from the unit delay units DU1through DUn. For example, the selection signals SEL1through SEL5for selecting the unit delay units, for example, the unit delay units DU1through DU5, to which the second input clock signal IN is transmitted may be generated as ‘1’ and, thus, the corresponding multiplexers MUX1through MUX5can select the output signal of the multiplexers right before the corresponding multiplexers. Meanwhile, the other selection signals, for example, the n-th selection signal SELn, may be generated as ‘0’, and thus corresponding multiplexers, for example, the multiplexer MUXn, select the output signals of the corresponding buffers, for example, the buffer BUFn.

FIGS. 3A and 3Bare timing diagrams for explaining a normal mode, in which the DLL100ofFIG. 1delays an input clock signal for one cycle, and a half-detection mode, in which the DLL100ofFIG. 1delays the input clock signal for half of one cycle.

FIGS. 4A and 4Bare timing diagrams for explaining operations of the DLL100shown inFIG. 1to remove a difference between phases of the input clock signal and an output clock signal in the normal mode and the half-detection mode, respectively.

FIGS. 5A and 5Bare tables showing digital values in the normal mode and the half-detection mode, respectively, of the DLL100ofFIG. 1.

The normal mode in which the DLL100delays the input clock signal for one cycle, and the half-detection mode, in which the DLL100delays the input clock signal for a half of one cycle, will now be described with reference toFIGS. 1 through 5B.

In the normal mode, the master DLL110outputs a first digital value CNTA corresponding to one clock cycle tck of the first input clock signal CLK. On the other hand, in the half-detection mode, the master DLL110outputs a first digital value CNTA corresponding to half of one clock cycle, that is, tck/2, of the first input clock signal CLK.FIG. 3Aillustrates the normal mode in which the master DLL110generates the first delay clock signal DCLK by delaying the first input clock signal CLK for one clock cycle tck.FIG. 3Billustrates the half-detection mode in which the master DLL110generates the first delay clock signal DCLK by delaying the first input clock signal CLK for half of one clock cycle, tck/2.

In the normal mode and the half-detection mode, the phase detector118detects a difference between phases of the first input clock signal CLK and the first delay clock signal DCLK to generate the lead signal LEAD or the lag signal LAG.FIG. 4Aillustrates detection of the difference between the phases of the first input clock signal CLK and the first delay clock signal DCLK in the normal mode.FIG. 4Billustrates detection of the difference between the phases of the first input clock signal CLK and the first delay clock signal DCLK in the half-detection mode. LOCK TARGET shown inFIGS. 4A,4B,5A and5B indicates a target phase of the first delay clock signal DCLK.

Referring toFIG. 5A, in the normal mode, the second input clock signal IN is delayed for a time period “one clock cycle tck of first input clock signal CLK±offset value OFFSET”. Referring toFIG. 5B, in the half-detection mode, the second input clock signal IN is delayed for a time period “2*half of one clock cycle, tck/2, of first input clock signal CLK±offset value OFFSET”.

Referring back toFIG. 1, the DLL100may include a shift control unit135. The shift control unit135sets a shift value of the shifter136in response to a half-detection mode signal HD that indicates the half detection mode and a shift signal SHV. The half-detection mode signal HD is also fed to the phase detector118.

FIG. 6is a block diagram of a DLL600having a master DLL610and a slave DLL630that can be compared with the exemplary embodiment of the present invention shown inFIG. 1and the variable delay circuit612, the decoder614, the delay control circuit616, the phase detector618, the variable delay circuit632, and the decoder634correspond to the like elements shown inFIG. 1and need not be described again. Signal CNT1corresponds to signal CNTA and signal CNT2corresponds to signal CNTC ofFIG. 1.

The DLL600determines a delay time period for the second input clock signal IN by multiplying a digital value CNT1corresponding to one clock cycle of the first input clock signal CLK by a delay factor less than 1 based on received signal DPV. The DLL600performs the multiplication by using a multiplier638. The multiplier638, however, occupies a large area of the DLL600. Also, the DLL600cannot compensate for an offset change depending on PVT.

On the other hand, the DLL100according to the exemplary embodiment of the present invention illustrated inFIG. 1can compensate for the offset change depending on PVT by using the adder/subtractor operator138. In addition, the DLL100determines a delay time period for the second input clock signal IN by using the shifter136. The shifter136and the adder/subtractor operator138occupy smaller areas of the DLL100than the multiplier638of the DLL600. Therefore, the size of the DLL100is smaller than that of the DLL600.

A clock delaying method according to an exemplary embodiment of the present invention includes the operations of detecting a first digital value corresponding to one clock cycle of a first input clock signal, receiving the first digital value, and delaying a second input clock signal for a time period less than the one clock cycle of the first input clock signal.

The operation of delaying the second input clock signal includes a shifting sub-operation, an adding/subtracting operation, and a variable delaying operation. In the shifting operation, the first digital value is shifted to generate a second digital value. In the adding/subtracting operation, an offset value OFV that varies according to PVT is added to or subtracted from the second digital value to generate a third digital value. In the variable delaying operation, the second input clock signal is delayed for the time period corresponding to the third digital value.

The clock delaying method according to an exemplary embodiment of the present invention has the same technical spirit as the DLL100, and the operations thereof correspond to the components of the DLL100shown inFIG. 1. Thus, the clock delaying method according to the exemplary embodiment of the present invention can be easily understood by one of ordinary skill in the art from the description of the DLL100, therefore, a detailed description thereof will be omitted here.

As described above, a DLL according to an exemplary embodiment of the present invention controls a delay time period by using a shifter. Thus, the DLL ofFIG. 1has a smaller size than DLLs that control delay time periods by using multipliers. Moreover, the DLL according to an exemplary embodiment of the present invention controls a delay time period by using an adder or subtractor. Thus, the DLL according to an exemplary embodiment of the present invention can determine a delay time period in which an offset value that changes according to PVT is reflected.