Apparatuses and methods to assign a logical thread to a physical thread

Methods and apparatuses relating to assigning a logical thread to a physical thread. In one embodiment, an apparatus includes a data storage device that stores code that when executed by a hardware processor causes the hardware processor to perform the following: translating an instruction into a translated instruction, assigning a logical thread for the translated instruction, and providing a thread map hint for the translated instruction; and a hardware scheduler to assign a physical thread of the hardware processor to execute the logical thread based on the thread map hint.

TECHNICAL FIELD

The disclosure relates generally to electronics, and, more specifically, an embodiment of the disclosure relates to assigning a logical thread to a physical thread of a processor.

BACKGROUND

A processor, or set of processors, executes instructions from an instruction set, e.g., the instruction set architecture (ISA). Instructions (e.g., code) to be executed may be separated into multiple threads for execution by various processor resources. Multiple threads may be executed in parallel. Further, a processor may utilize out-of-order execution to execute instructions, e.g., as the input(s) for such instructions are made available. Thus, an instruction that appears later in program order (e.g., in code sequence) may be executed before an instruction appearing earlier in program order.

DETAILED DESCRIPTION

A (e.g., hardware) processor, or set of processors, executes instructions from an instruction set, e.g., the instruction set architecture (ISA). The instruction set is the part of the computer architecture related to programming, and generally includes the native data types, instructions, register architecture, addressing modes, memory architecture, interrupt and exception handling, and external input and output (I/O). It should be noted that the term instruction herein may refer to a macro-instruction, e.g., an instruction that is provided to the processor for execution, or to a micro-instruction, e.g., an instruction that results from a processor's decode unit (decoder) decoding macro-instructions. A processor (e.g., having one or more cores to decode and/or execute instructions) may operate on data, for example, in performing arithmetic, logic, or other functions.

Instructions may be separated into different threads (e.g., threads of execution). A thread may generally refer to the smallest sequence (e.g., stream) of instructions that may be managed together, e.g., by a scheduler, for execution. In one embodiment, a thread may be a sequence (e.g., stream) of instructions that are managed independently for execution. In one embodiment, a thread may be a sequence (e.g., stream) of instructions having a data dependency with instruction(s) in a different thread(s). A scheduler may be a hardware scheduler of a processor to schedule execution of instructions on a core of the processor. One embodiment of this disclosure includes a system to schedule execution of instructions on a processor, e.g., a physical thread thereof. A system to schedule execution of instructions on a processor may include hardware, software, firmware, or any combination thereof. A logical thread may generally refer to the thread that is visible from (e.g., managed by) the code. A physical thread may generally refer to the physical components of a processor that execute the logical thread.

One embodiment of this disclosure includes scheduling (e.g., pre-scheduling before run time) an instruction(s) for execution and/or assigning logical threads (LTs) for an instruction(s). Scheduling (e.g., pre-scheduling) may occur at or after translation time, for example, for code translated from one format to another format. A (e.g., dynamic) binary translator may be utilized to translate code (e.g., an instruction) from one format to another format. A binary translator may translate code (e.g., an instruction) from a guest format to a host format. A binary translator may translate an instruction of a first ISA into an instruction of a second ISA. A binary translator may translate (e.g., an x86 format) macro-instruction(s) into micro-instruction(s). An instruction may translate into a plurality of translated instructions, e.g., a one-to-one correspondence is not required in one embodiment. Multiple instructions may translate into one translated instruction or a number of translated instructions that is less than the number of multiple (e.g., untranslated) instructions, e.g., a one-to-one correspondence is not required in one embodiment. A binary translator may translate a software instruction (e.g., in binary code) into a hardware instruction (e.g., in binary code), for example, for execution on a hardware processor. A (e.g., dynamic) binary translator may include hardware, software, firmware, or any combination thereof.

A dynamic binary translator may translate one instruction (e.g., in source binary code complying with the architecture of a source processor (source architecture)) into a translated instruction (e.g., into target binary code complying with the architecture of a target processor (target architecture)). The dynamic binary translation process may take place during execution of the source binary code (e.g., at run time).

A (e.g., dynamic) binary translator may schedule (e.g., schedule before run time) an instruction and/or assign a logical thread for the instruction. A (e.g., dynamic) binary translator may provide a thread map hint (e.g., field) for an (e.g., translated) instruction. A (e.g., hardware) scheduler may assign a physical thread of a (e.g., hardware) processor to execute the logical thread based on the thread map hint.

In certain embodiments after translation and static code scheduling, a binary translator (e.g., a dynamic binary translator (DBT)) assigns instructions from the code into logical threads (LTs). Instructions may be assigned to a particular logical thread according to a variety of policies. For example, instructions that may be executed as a single block (e.g., stream) of instructions placed into the same logical thread, e.g., see the discussion of FIGS.3A-3C below. For example, instructions in a basic block (e.g., a block of instructions with a single entry point and a single exit point, such as, but not limited to, a sequence of non-branch instructions that ends with a single branch instruction) may be placed in the same logical thread. In one embodiment, the branch at the end of a basic block may jump back to the beginning of the block (e.g., a single-block loop) and the instructions within the block may be (a), (b), (c), and (d), where (d) is the branch instruction that jumps back to (a). When this block of instructions is executed in-order on a processor, the execution order may be (a)(b)(c)(d) then (a)(b)(c)(d), etc. A thread assignment policy of this disclosure may include assigning all instructions [(a)(b)(c)] except for the branch into a single (e.g., rotating) logical thread (e.g., LT1) and assigning the branch instruction (d) into a single (e.g., fixed) logical thread (e.g., LT4) along with a thread map hint to indicate (e.g., to the scheduler) to rotate the physical thread used to execute the non-branch instructions [(a)(b)(c)] on their next execution. In this embodiment, each iteration of the non-branch instructions [(a)(b)(c)] of the loop may be assigned to a different physical thread, e.g., so that the scheduler may execute instructions from different iterations of the loop in parallel. In one embodiment, different iterations of non-branch instructions may be independent of one another for parallel (e.g., concurrent) execution (e.g., on different physical threads). In one embodiment, different iterations of the same instruction(s) may be given a thread map hint to indicate parallel (e.g., concurrent) execution on separate physical threads (e.g., to assign a different physical thread for each iteration of the same instruction(s)).

Certain scheduling decisions may be made (e.g., once) statically (e.g., at translation time in a DBT) which may be more desirable (e.g., power efficient) than making these scheduling decisions repeatedly in a (e.g., hardware) scheduler, for example, (e.g., separately) scheduling each instruction inside of a thread for execution. Scheduler (e.g., hardware scheduler) may be utilized to (e.g., only) make scheduling decisions for certain instructions (e.g., code segments), for example, for instructions where static (e.g., translation time) prediction of their behavior is difficult or unknown (e.g., instructions that depend from a different thread such as, but not limited to, branch instructions). Binary translator (e.g., a software binary translator) assigned threads may have more visibility into future and/or previous instructions than a (e.g., hardware) scheduler. Binary translator (e.g., a software binary translator) may detect critical path instructions and optimize (e.g., logical) thread assignment to prioritize these critical instructions. In one embodiment, a critical path instruction is a load from memory where multiple (e.g., subsequent in program order) instructions are to use the value from that load from memory. A binary translator may prioritize (e.g., mark for the earliest execution possible) that critical memory load. Binary translator (e.g., a software binary translator) may detect dependence instructions (e.g., chains) feeding control flow instructions to prioritize the dependence instructions. Binary translator (e.g., a software binary translator) may not utilize (e.g., require) collection (e.g., offline) of traces to perform (e.g., logical) thread assignment. In one embodiment, by not utilizing traces, thread assignments are not tied to a single input (e.g., not input sensitive) and/or a programmer may not need to perform the extra step of tracing and compilers may not need to be modified and programs recompiled to support a trace-based solution. In an embodiment where a dynamic binary translator is utilized, the (e.g., logical) thread assignment may be adapted at run time to improve performance, for example, where static techniques have no or limited visibility into run time behavior. Certain embodiments of this disclosure are optimized for observed run time behavior. Certain embodiments of this disclosure may dynamically adapt the assignment of a logical thread to a physical thread based on behavior observed (e.g., by a dynamic binary translator) at run time.

In one embodiment, a (e.g., dynamic) binary translator and a (e.g., hardware) scheduler cooperate to translate (e.g., each) logical threads into (e.g., each) physical threads. For example, for different executions of the same stream of instructions (e.g., code), a same instruction may use different physical threads for each execution even though the instructions were statically assigned to logical threads. This may be useful for eliminating false ordering constraints, for example, that may arise from a pure software thread assignment (e.g., where instructions (e.g., loop) may have the same physical thread assignment in each iteration of executing the instructions (e.g., loop)). This may lead to no or minimal instruction level parallelism (ILP) across loop iterations.

FIG. 1illustrates a system100to assign a logical thread to a physical thread according to embodiments of the disclosure. Depicted processor102includes a core104and optionally a second core104A. A processor may include one or more cores. A (e.g., each) core may include one or more physical threads (PTs), e.g., to execute an instruction or a thread of instructions. A physical thread may generally refer to a (e.g., smallest) sequence (e.g., stream) of instructions that may be managed (e.g., independently) by physical resources of a processor. For example, a single core104may support the execution of one physical thread, two physical threads, or any plurality of physical threads (e.g., as illustrated by PT0. . . PTninFIGS. 1 and 2, where n may be any positive integer). Scheduler106may be a part of processor102(e.g., as depicted) or a separate component (e.g., hardware component).

Code (e.g., binary code)108may be translated (e.g., by dynamic binary translator (DBT)110) from a first (e.g., untranslated) format to a second (e.g., translated) format. DBT110may be in hardware, software, firmware, or a combination thereof. In one embodiment, an instruction stream (e.g., translated instruction stream112) may be output from DBT110and include a logical thread assignment (e.g., logical thread designation114) and/or a thread map hint116, for example, as a field in an (e.g., translated) instruction. Each instruction in an instruction stream may include a respective logical thread assignment (e.g., logical thread designation114) and/or a thread map hint116. A logical thread designation may indicate the particular logical thread that a translated instruction(s) is assigned. Assigning may refer to being a member of a thread of execution. Scheduler106may assign a physical thread (e.g., PT0. . . PTninFIG. 1) of the processor102for the execution of the translated instruction, for example, based on a logical thread assignment (e.g., logical thread designation114) and/or a thread map hint116, e.g., as a field in an (e.g., translated) instruction or thread. Dotted line extending between core104and scheduler106is an optional data path that may provide an indication to the scheduler106, for example, that a physical thread is available to execute a (e.g., logical) thread. A single headed arrow herein may not be limited to one-way communication, for example, it may indicate two-way communication (e.g., both to and from that component).

FIG. 2illustrates a system200to assign a logical thread to a physical thread according to embodiments of the disclosure. Depicted processor202includes a core204and optionally a second core204A. A processor may include one or more cores. A (e.g., each) core may include one or more physical threads (PTs), e.g., to execute an instruction or a thread of instructions. A physical thread may generally refer to a (e.g., smallest) sequence (e.g., stream) of instructions that may be managed (e.g., independently) by physical resources of a processor. For example, a single core204may support the execution of one physical thread, two physical threads, or any plurality of physical threads (e.g., as illustrated by PT0. . . PTninFIGS. 1 and 2, where n may be any positive integer). Scheduler206may be a part of processor202(e.g., as depicted) or a separate component (e.g., hardware component).

Code (e.g., binary code)208may be compiled (e.g., by a compiler218), for example, code208may be source code (e.g., written in a programming or source language) and compiler may translate the source code into another computer language (e.g., the target machine language). Compiler may output a compiled instruction (e.g., as instruction stream220). Compiler or other component may output a logical thread assignment (e.g., logical thread designation224), for example, as a field in an (e.g., compiled) instruction or thread. A logical thread designation may indicate the particular logical thread that a translated instruction(s) is assigned. Assigning may refer to being a member of a thread of execution.

Each instruction in an instruction stream may include a respective logical thread assignment (e.g., logical thread designation214). An instruction (e.g., of instruction stream220) may be output to the processor202, e.g., a front end226of the processor202. Front end226may fetch and prepare instructions to be used by other components of processor202. Processor may include a dynamic binary translator (DBT) as a separate component (not shown) or as a component of front end226, e.g., as depicted inFIG. 2. Front end226may include a decoder228(e.g., an instruction decoder to decode an instruction into the control signals (e.g., micro-instructions) to control the execution of the instruction). Decoder may output decoded code (e.g., a decoded instruction) to a binary translator (e.g., DBT210of processor202). Binary translator (e.g., DBT210) may translate an instruction (e.g., from instruction stream220) from a first (e.g., untranslated) format to a second (e.g., translated) format. In one embodiment, an instruction stream (e.g., translated, decoded instruction stream212) may be output from DBT210and may include a logical thread assignment (e.g., logical thread designation214) and/or a thread map hint216. A logical thread designation may indicate the particular logical thread that a translated instruction(s) is assigned. Assigning may refer to being a member of a thread of execution.

Each instruction in an instruction stream may include a respective logical thread assignment (e.g., logical thread designation214) and/or a thread map hint216, for example, as a field in an (e.g., compiled and decoded) instruction. Logical thread assignment output from a compiler (e.g., as logical thread designation224) and from a DBT (e.g., as logical thread designation214) may be the same or different, for example, if the DBT may perform a logical thread assignment. Scheduler206may assign a physical thread (e.g., PT0. . . PTninFIG. 2) of the processor202for the execution of the translated instruction, for example, based on a logical thread assignment (e.g., logical thread designation214) and/or a thread map hint216, e.g., as a field in an (e.g., translated) instruction or thread. Dotted line extending between core204and scheduler206is an optional data path that may provide an indication to the scheduler206that a physical thread is available to execute a (e.g., logical) thread. A single headed arrow herein may not be limited to one-way communication, for example, it may indicate two-way communication (e.g., both to and from that component). Although a cache is not depicted in certain of the Figures, a cache (e.g., an instruction and/or data cache), may be utilized.

An instruction may be assigned to a logical thread (LT) by a (e.g., dynamic) binary translator.FIGS. 3A-3Cillustrate flow diagrams of threads of multiple instructions according to embodiments of the disclosure. A thread may include a plurality of instructions. Each ofFIGS. 3A-3Cinclude six (e.g., logical) threads (T1-T6) and each thread may include one or more instructions. Instructions A-D inFIG. 1are assigned to thread T1. In one embodiment, a hardware scheduler may be an out-of-order scheduler and it may include a small window of less than all of the instructions in a thread, for example, an out-of-order scheduler inFIG. 3Amay schedule instructions A-D at a given instant, e.g., but not schedule the other instructions. In one embodiment, a hardware scheduler (e.g., in-order or out-of-order scheduler) may only check each head instruction of logical threads of multiple instructions (e.g., to schedule execution of those instructions and/or their logical threads), for example, a scheduler inFIG. 3Bmay schedule head instructions A-D at a given instant, e.g., scheduling instructions A-D and/or their threads (T1-T4, respectively). In one embodiment, a hardware scheduler may be an out-of-order scheduler and it may include a large window of all of the instructions in a thread, for example, an out-of-order scheduler inFIG. 3Cmay schedule instructions of any of threads T1-T6at a given instant. In one embodiment, an in-order (e.g., execution engine) processor executes instructions (e.g., micro-instructions) out of the source program order (e.g., in the order the machine code instructions are presented to the in-order processor).

FIG. 4Ais a block diagram of static thread assignment according to embodiments of the disclosure. A system (e.g., a compiler or a DBT) may perform static logical thread assignment. For example,FIG. 4Aschematically illustrates four instructions of a block loop with one of the instructions (the lower left, non-shaded box) being a branch. Certain embodiments of this disclosure may allow a system (e.g., via a DBT) to include a thread map hint for each or all instructions. For example, a thread map hint that indicates a rotating logical instruction (or thread) may be provided for the three shaded box instructions. For example, a thread map hint may indicate execution on a fixed (e.g., non-rotating) logical instruction (or thread).FIG. 4Bis a block diagram of dynamic thread assignment according to embodiments of the disclosure. A system (e.g., a scheduler) may receive the thread map hints (e.g., rotating or fixed logical threads from Figure A) and then assign a different (e.g., rotating) physical thread of a processor for an instruction(s) whose corresponding thread map hint indicates it is a rotating logical instruction (or thread) and/or assign a same physical thread (e.g., PT0) of a processor for an instruction(s) whose corresponding thread map hint indicates it is a static logical instruction (or thread).

FIG. 5Ais a block diagram of thread mapping before a thread map hint according to embodiments of the disclosure. Thread mapping may indicate the physical threads that are to execute a logical thread. A scheduler may perform thread mapping, e.g., based on a thread map hint.FIG. 5Aillustrates an example of logical threads being assigned to be executed by (e.g., mapped to a single) physical thread (PT).FIG. 5Bis a block diagram of dynamic thread mapping after a thread map hint according to embodiments of the disclosure. A system (e.g., a scheduler) may receive a thread map hint (e.g., from a DBT) and then assign a physical thread of a processor to execute the logical thread based on the thread map hint. For example, a thread map hint for LT0and LT1inFIG. 5Bmay indicate (e.g., to the scheduler) that those logical threads are fixed, e.g., relative to the mapping to PT2and PT5, respectively, inFIG. 5A. DBT may include a thread map hint when it detects (e.g., during the running of the source or untranslated code) a branch, such as, but not limited to, a loop, a split, or a join. For example, a thread map hint for LT2and LT3inFIG. 5Bmay indicate (e.g., to the scheduler) that those logical threads are non-fixed (e.g., rotating), for example, relative to their mapping inFIG. 5A. Depicted rotation inFIG. 5Bmaps LT2to PT3(instead of PT2as inFIG. 5A) and maps LT3to PT6(instead of PT5as inFIG. 5A). Rotating may include a physical thread being assigned to the next (e.g., adjacent) physical thread or any available physical thread (e.g., available to the scheduler at assignment time). Non-fixed (e.g., rotating) threads may be scheduled for concurrent execution with other non-fixed threads on their respective PTs. Fixed threads may be scheduled for sequential instruction, e.g., on the same PT.

FIG. 6illustrates a flow diagram600of assigning a logical thread to a physical thread according to embodiments of the disclosure. Depicted flow diagram includes translating an instruction into a translated instruction602, assigning a logical thread for the translated instruction604, providing a thread map hint for the translated instruction606, and assigning a physical thread of a hardware processor to execute the logical thread based on the thread map hint608.

In one embodiment, the use of a DBT allows the (e.g., logical to physical) thread assignment to be adapted at run time to improve performance. Static techniques may have limited visibility into run time behavior. Certain embodiments herein may dynamically optimize for observed run time behavior. For example, certain embodiments may dynamically adapt based on phases observed at run time. In one embodiment, a (e.g., dynamic) binary translator and a scheduler may cooperate to translate logical threads into physical threads. For different executions of the same code, the same instructions of that code may use different physical threads of a processor even though the instructions were originally assigned to logical threads statically in the code. This may remove false ordering constraints that may arise from a pure software thread assignment (e.g., where instructions in loops would always have the same physical thread assignment and restricting instruction level parallelism (ILP) for repetitive iterations).

In one embodiment, for example, inFIGS. 4A-5B, instructions (or threads including the instructions) may include a thread map hint (e.g., from a DBT) such that rotating logical thread (LT) (e.g., shaded boxes inFIG. 4A) receive a different physical thread (PT) at runtime (e.g., denoted by patterned boxes inFIG. 4B). Certain embodiments herein utilize fixed physical threads, e.g., to guaranty certain execution properties and/or ordering constraints (e.g., so that certain instructions, such as stores, do not execute speculatively).

In one embodiment, a processor utilizes hardware (e.g., a hardware scheduler) and software (e.g., a software DBT) co-designed thread assignment (e.g., assigning code to physical threads) (e.g., micro-threads) to simplify the hardware selection logic. The proposed design may achieve the benefits of out-of-order (e.g., instruction or thread execution) without the complexity of an out-of-order execution engine, etc. In one embodiment, a processor utilizes software (e.g., DBT software) assigned micro threads that capture a wide variety of characteristics, e.g., in comparison to a dependence chain based approach. In one embodiment, a hardware and software co-designed microprocessor that utilizes a dynamic binary translator (DBT). This DBT based approach may include benefits compared to compile time based approaches (e.g., as discussed below).

In one embodiment, after translation and static code scheduling, the software (e.g., DBT) assigns logical threads (LTs), which may be assigned using a variety of policies, such as, but not limited to, those discussed herein. Certain embodiments leverage DBT static (e.g., translation time) code scheduling (e.g., pre-scheduling). Certain scheduling decisions may be easier to make statically (e.g., at translation time) than dynamically (e.g., at run time). Statically made scheduling decisions may be more power efficient, for example, intra-basic block scheduling (e.g., scheduling within a block or thread, such as, but not limited to, within a block T1-T6inFIGS. 3A-3C). In one embodiment, hardware (e.g., hardware scheduler) may (e.g., only) make (e.g., dynamic) scheduling decisions for code segments where static (e.g., translation time) prediction of behavior is unknown or more difficult (e.g., across basic blocks, as illustrated by the transitions between blocks T1-T6inFIGS. 3A-3C). Software assigned threads may be desired over (e.g., pure) hardware assigned threads, for example, the software may have more visibility into future and previous instructions (e.g., run time behavior). Software may detect critical path instructions and optimize (e.g., logical) thread assignment to prioritize these instructions. Software may detect dependence chains feeding control flow instructions to prioritize them.

Certain embodiments using a DBT do not use (e.g., require) offline collection of traces to perform a software thread assignment. By avoiding the use of traces, the thread assignments may not be tied to a single input (e.g., not be input sensitive). In certain embodiments, a programmer may not perform an extra step of tracing and/or compilers may not be modified and programs recompiled to support a trace-based solution. In certain embodiments using a DBT, the thread assignment may be adapted at run time to improve performance. Static techniques may have limited visibility into run time behavior. Certain embodiments may optimize performance of the assignment of code to physical threads for an observed run time behavior. Certain embodiments may dynamically adapt based on phases observed at run time.

Software (e.g., software DBT) and hardware (e.g., a hardware scheduler) may cooperate to translate logical threads (LTs) into physical threads (PTs). That is, for different executions of the same code, a processor may use different PTs. This may be useful, for example, for eliminating false ordering constraints that may arise from a pure software thread assignment (e.g., instructions in loops may always have the same physical thread assignment leading to little instruction level parallelism (ILP) across loop iterations). For example,FIGS. 4A-4Bdemonstrate that for a single basic block loop shown schematically inFIG. 4Aas four instructions (e.g., the four boxes indicating four instructions) and those marked with rotating LTs (shaded boxes) receive a different PT at runtime (denoted by the hatched boxes inFIG. 4B). A software and hardware co-designed processor may utilize fixed threads for enabling certain execution properties (e.g., certain instructions, such as stores, not being executed speculatively). For example,FIGS. 4A-4Billustrate that for the single basic block loop shown on the left that the instruction marked with fixed LT (empty box) may receive the same PT at runtime for all its invocations (denoted by the empty box inFIG. 4B).

In certain embodiments, software (e.g., a software DBT) may provide thread map hints to the hardware (e.g., hardware scheduler) to influence the logical thread to physical thread mapping. For example,FIGS. 5A-5Billustrate a sample state for the LT to PT mapping where after a thread map hint is provided from software (e.g., on a branch instruction), the processor may transition to the new mapping shown inFIG. 5B. In this embodiment, both rotating LTs map to different PTs, but the fixed LTs map to the same PTs. Instructions within a thread may be required to execute in-order with respect to other instructions in the same thread, e.g., in an in-order execution unit (engine) of a processor. This embodiment may simplify the hardware scheduler (e.g., selection logic) where it may select from head (e.g., beginning) instructions of each of multiple threads. This embodiment may allow the scheduler to leverage important properties, such as, but not limited to, in-order execution guarantees within threads which may allow further hardware simplifications (e.g., scoreboard structures for dependency tracking may be eliminated in favor of enforcing the correct ordering using fixed threads).

In certain embodiments, instructions may be ready for execution (e.g., for selection by a scheduler for execution) from a head of a thread when their dependencies are satisfied. Dependencies may be considered satisfied when a (e.g., hardware) scoreboarding component detects that producer instructions have issued or an in-order thread may ensure the instructions are ready. For example, if two instructions in the same thread have a one cycle dependence edge between them and the dependent instructions has no other producers, the scoreboarding mechanism may not be utilized.

In one embodiment, an apparatus includes a hardware binary translator to: translate an instruction into a translated instruction, assign a logical thread for the translated instruction, and provide a thread map hint for the translated instruction, and a hardware scheduler to assign a physical thread of a hardware processor to execute the logical thread based on the thread map hint from the hardware binary translator. The instruction may be software binary code and the translated instruction may be hardware binary code. The hardware scheduler may assign a different physical thread for an additional instance of the translated instruction based on the thread map hint. The hardware scheduler may assign the physical thread for an additional instance of the translated instruction based on the thread map hint. The hardware scheduler may only check each head instruction of logical threads of multiple instructions to schedule execution of the logical threads. The hardware binary translator may add the thread map hint as a field of the translated instruction.

In another embodiment, an apparatus includes a data storage device that stores code that when executed by a hardware processor causes the hardware processor to perform the following: translating an instruction into a translated instruction, assigning a logical thread for the translated instruction, and providing a thread map hint for the translated instruction, and a hardware scheduler to assign a physical thread of the hardware processor to execute the logical thread based on the thread map hint. The instruction may be software binary code and the translated instruction may be hardware binary code. The data storage device may further store code that when executed by the hardware processor causes the hardware processor to perform the following: assigning a different physical thread for an additional instance of the translated instruction based on the thread map hint. The data storage device may further store code that when executed by the hardware processor causes the hardware processor to perform the following: assigning the physical thread for an additional instance of the translated instruction based on the thread map hint. The hardware scheduler may only check each head instruction of logical threads of multiple instructions to schedule execution of the logical threads. The data storage device may further store code that when executed by the hardware processor causes the hardware processor to perform the following: adding the thread map hint as a field of the translated instruction.

In yet another embodiment, a method includes translating an instruction into a translated instruction, assigning a logical thread for the translated instruction, providing a thread map hint for the translated instruction, and assigning a physical thread of a hardware processor to execute the logical thread based on the thread map hint. The instruction may be software binary code and the translated instruction may be hardware binary code. The method may include assigning a different physical thread for an additional instance of the translated instruction based on the thread map hint. The method may include assigning the physical thread for an additional instance of the translated instruction based on the thread map hint. The method may include only checking each head instruction of logical threads of multiple instructions to schedule execution of the logical threads. The providing the thread map hint for the translated instruction comprises adding the thread map hint as a field of the translated instruction.

In another embodiment, an apparatus includes a hardware processor to execute a plurality of physical threads, and a data storage device that stores code that when executed by the hardware processor causes the hardware processor to perform the following: translating an instruction into a translated instruction, assigning a logical thread for the translated instruction, providing a thread map hint for the translated instruction, and assigning a physical thread of the hardware processor to execute the logical thread based on the thread map hint. The instruction may be software binary code and the translated instruction may be hardware binary code. The data storage device may further store code that when executed by the hardware processor causes the hardware processor to perform the following: assigning a different physical thread for an additional instance of the translated instruction based on the thread map hint. The data storage device may further store code that when executed by the hardware processor causes the hardware processor to perform the following: assigning the physical thread for an additional instance of the translated instruction based on the thread map hint. The data storage device may further store code that when executed by the hardware processor causes the hardware processor to perform the following: only checking each head instruction of logical threads of multiple instructions to schedule execution of the logical threads. The data storage device may further store code that when executed by the hardware processor causes the hardware processor to perform the following: wherein the providing the thread map hint for the translated instruction comprises adding the thread map hint as a field of the translated instruction.

In yet another embodiment, an apparatus includes means to translate an instruction into a translated instruction, means to assign a logical thread for the translated instruction, means to provide a thread map hint for the translated instruction, and means to assign a physical thread of a hardware processor to execute the logical thread based on the thread map hint. A hardware binary translator may only provide a thread map hint for each head logical thread of blocks of multiple logical threads. A data storage device may further store code that when executed by the hardware processor causes the hardware processor to perform the following: only providing a thread map hint for each head logical thread of blocks of multiple logical threads. A method may include only providing a thread map hint for each head logical thread of blocks of multiple logical threads. A data storage device may further store code that when executed by the hardware processor causes the hardware processor to perform the following: only providing a thread map hint for each head logical thread of blocks of multiple logical threads. An apparatus to assign a logical thread to a physical thread may be as described in the detailed description. A method for assigning a logical thread to a physical thread may be as described in the detailed description.

Exemplary Core Architectures

In-Order and Out-of-Order Core Block Diagram

InFIG. 7A, a processor pipeline700includes a fetch stage702, a length decode stage704, a decode stage706, an allocation stage708, a renaming stage710, a scheduling (also known as a dispatch or issue) stage712, a register read/memory read stage714, an execute stage716, a write back/memory write stage718, an exception handling stage722, and a commit stage724.

FIG. 7Bshows processor core790including a front end unit730coupled to an execution engine unit750, and both are coupled to a memory unit770. The core790may be a reduced instruction set computing (RISC) core, a complex instruction set computing (CISC) core, a very long instruction word (VLIW) core, or a hybrid or alternative core type. As yet another option, the core790may be a special-purpose core, such as, for example, a network or communication core, compression engine, coprocessor core, general purpose computing graphics processing unit (GPGPU) core, graphics core, or the like.

The front end unit730includes a branch prediction unit732coupled to an instruction cache unit734, which is coupled to an instruction translation lookaside buffer (TLB)736, which is coupled to an instruction fetch unit738, which is coupled to a decode unit740. The decode unit740(or decoder or decoder unit) may decode instructions (e.g., macro-instructions), and generate as an output one or more micro-operations, micro-code entry points, micro-instructions, other instructions, or other control signals, which are decoded from, or which otherwise reflect, or are derived from, the original instructions. The decode unit740may be implemented using various different mechanisms. Examples of suitable mechanisms include, but are not limited to, look-up tables, hardware implementations, programmable logic arrays (PLAs), microcode read only memories (ROMs), etc. In one embodiment, the core790includes a microcode ROM or other medium that stores microcode for certain macroinstructions (e.g., in decode unit740or otherwise within the front end unit730). The decode unit740is coupled to a rename/allocator unit752in the execution engine unit750.

The execution engine unit750includes the rename/allocator unit752coupled to a retirement unit754and a set of one or more scheduler unit(s)756. The scheduler unit(s)756represents any number of different schedulers, including reservations stations, central instruction window, etc. The scheduler unit(s)756is coupled to the physical register file(s) unit(s)758. Each of the physical register file(s) units758represents one or more physical register files, different ones of which store one or more different data types, such as scalar integer, scalar floating point, packed integer, packed floating point, vector integer, vector floating point, status (e.g., an instruction pointer that is the address of the next instruction to be executed), etc. In one embodiment, the physical register file(s) unit758comprises a vector registers unit, a write mask registers unit, and a scalar registers unit. These register units may provide architectural vector registers, vector mask registers, and general purpose registers. The physical register file(s) unit(s)758is overlapped by the retirement unit754to illustrate various ways in which register renaming and out-of-order execution may be implemented (e.g., using a reorder buffer(s) and a retirement register file(s); using a future file(s), a history buffer(s), and a retirement register file(s); using a register maps and a pool of registers; etc.). The retirement unit754and the physical register file(s) unit(s)758are coupled to the execution cluster(s)760. The execution cluster(s)760includes a set of one or more execution units762and a set of one or more memory access units764. The execution units762may perform various operations (e.g., shifts, addition, subtraction, multiplication) and on various types of data (e.g., scalar floating point, packed integer, packed floating point, vector integer, vector floating point). While some embodiments may include a number of execution units dedicated to specific functions or sets of functions, other embodiments may include only one execution unit or multiple execution units that all perform all functions. The scheduler unit(s)756, physical register file(s) unit(s)758, and execution cluster(s)760are shown as being possibly plural because certain embodiments create separate pipelines for certain types of data/operations (e.g., a scalar integer pipeline, a scalar floating point/packed integer/packed floating point/vector integer/vector floating point pipeline, and/or a memory access pipeline that each have their own scheduler unit, physical register file(s) unit, and/or execution cluster—and in the case of a separate memory access pipeline, certain embodiments are implemented in which only the execution cluster of this pipeline has the memory access unit(s)764). It should also be understood that where separate pipelines are used, one or more of these pipelines may be out-of-order issue/execution and the rest in-order.

The set of memory access units764is coupled to the memory unit770, which includes a data TLB unit772coupled to a data cache unit774coupled to a level 2 (L2) cache unit776. In one exemplary embodiment, the memory access units764may include a load unit, a store address unit, and a store data unit, each of which is coupled to the data TLB unit772in the memory unit770. The instruction cache unit734is further coupled to a level 2 (L2) cache unit776in the memory unit770. The L2 cache unit776is coupled to one or more other levels of cache and eventually to a main memory.

By way of example, the exemplary register renaming, out-of-order issue/execution core architecture may implement the pipeline700as follows: 1) the instruction fetch738performs the fetch and length decoding stages702and704; 2) the decode unit740performs the decode stage706; 3) the rename/allocator unit752performs the allocation stage708and renaming stage710; 4) the scheduler unit(s)756performs the schedule stage712; 5) the physical register file(s) unit(s)758and the memory unit770perform the register read/memory read stage714; the execution cluster760perform the execute stage716; 6) the memory unit770and the physical register file(s) unit(s)758perform the write back/memory write stage718; 7) various units may be involved in the exception handling stage722; and 8) the retirement unit754and the physical register file(s) unit(s)758perform the commit stage724.

Specific Exemplary in-Order Core Architecture

FIG. 8Ais a block diagram of a single processor core, along with its connection to the on-die interconnect network802and with its local subset of the Level 2 (L2) cache804, according to embodiments of the disclosure. In one embodiment, an instruction decode unit800supports the x86 instruction set with a packed data instruction set extension. An L1 cache806allows low-latency accesses to cache memory into the scalar and vector units. While in one embodiment (to simplify the design), a scalar unit808and a vector unit810use separate register sets (respectively, scalar registers812and vector registers814) and data transferred between them is written to memory and then read back in from a level 1 (L1) cache806, alternative embodiments of the disclosure may use a different approach (e.g., use a single register set or include a communication path that allow data to be transferred between the two register files without being written and read back).

FIG. 8Bis an expanded view of part of the processor core inFIG. 8Aaccording to embodiments of the disclosure.FIG. 8Bincludes an L1 data cache806A part of the L1 cache804, as well as more detail regarding the vector unit810and the vector registers814. Specifically, the vector unit810is a 16-wide vector processing unit (VPU) (see the 16-wide ALU 828), which executes one or more of integer, single-precision float, and double-precision float instructions. The VPU supports swizzling the register inputs with swizzle unit820, numeric conversion with numeric convert units822A-B, and replication with replication unit824on the memory input. Write mask registers826allow predicating resulting vector writes.

FIG. 9is a block diagram of a processor900that may have more than one core, may have an integrated memory controller, and may have integrated graphics according to embodiments of the disclosure. The solid lined boxes inFIG. 9illustrate a processor900with a single core902A, a system agent910, a set of one or more bus controller units916, while the optional addition of the dashed lined boxes illustrates an alternative processor900with multiple cores902A-N, a set of one or more integrated memory controller unit(s)914in the system agent unit910, and special purpose logic908.

The memory hierarchy includes one or more levels of cache within the cores, a set or one or more shared cache units906, and external memory (not shown) coupled to the set of integrated memory controller units914. The set of shared cache units906may include one or more mid-level caches, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, a last level cache (LLC), and/or combinations thereof. While in one embodiment a ring based interconnect unit912interconnects the integrated graphics logic908, the set of shared cache units906, and the system agent unit910/integrated memory controller unit(s)914, alternative embodiments may use any number of well-known techniques for interconnecting such units. In one embodiment, coherency is maintained between one or more cache units906and cores902-A-N.

In some embodiments, one or more of the cores902A-N are capable of multithreading. The system agent910includes those components coordinating and operating cores902A-N. The system agent unit910may include for example a power control unit (PCU) and a display unit. The PCU may be or include logic and components needed for regulating the power state of the cores902A-N and the integrated graphics logic908. The display unit is for driving one or more externally connected displays.

Exemplary Computer Architectures

Referring now toFIG. 10, shown is a block diagram of a system1000in accordance with one embodiment of the present disclosure. The system1000may include one or more processors1010,1015, which are coupled to a controller hub1020. In one embodiment the controller hub1020includes a graphics memory controller hub (GMCH)1090and an Input/Output Hub (IOH)1050(which may be on separate chips); the GMCH1090includes memory and graphics controllers to which are coupled memory1040and a coprocessor1045; the IOH1050is couples input/output (I/O) devices1060to the GMCH1090. Alternatively, one or both of the memory and graphics controllers are integrated within the processor (as described herein), the memory1040and the coprocessor1045are coupled directly to the processor1010, and the controller hub1020in a single chip with the IOH1050. Memory1040may include a module to store code that when executed causes a processor to perform any method of this disclosure. Memory1040may include a binary translator module1040A, for example, to store code that when executed causes a processor to translate an instruction into a translated instruction, assign a logical thread for the translated instruction, provide a thread map hint for the translated instruction, or any combination thereof. Memory1040may include a scheduler module1040B, for example, to store code that when executed causes a processor to assign a physical thread of a hardware processor to execute a logical thread based on a thread map hint.

The optional nature of additional processors1015is denoted inFIG. 10with broken lines. Each processor1010,1015may include one or more of the processing cores described herein and may be some version of the processor900.

The memory1040may be, for example, dynamic random access memory (DRAM), phase change memory (PCM), or a combination of the two. For at least one embodiment, the controller hub1020communicates with the processor(s)1010,1015via a multi-drop bus, such as a frontside bus (FSB), point-to-point interface such as QuickPath Interconnect (QPI), or similar connection1095.

In one embodiment, the coprocessor1045is a special-purpose processor, such as, for example, a high-throughput MIC processor, a network or communication processor, compression engine, graphics processor, GPGPU, embedded processor, or the like. In one embodiment, controller hub1020may include an integrated graphics accelerator.

There can be a variety of differences between the physical resources1010,1015in terms of a spectrum of metrics of merit including architectural, microarchitectural, thermal, power consumption characteristics, and the like.

In one embodiment, the processor1010executes instructions that control data processing operations of a general type. Embedded within the instructions may be coprocessor instructions. The processor1010recognizes these coprocessor instructions as being of a type that should be executed by the attached coprocessor1045. Accordingly, the processor1010issues these coprocessor instructions (or control signals representing coprocessor instructions) on a coprocessor bus or other interconnect, to coprocessor1045. Coprocessor(s)1045accept and execute the received coprocessor instructions.

Referring now toFIG. 11, shown is a block diagram of a first more specific exemplary system1100in accordance with an embodiment of the present disclosure. As shown inFIG. 11, multiprocessor system1100is a point-to-point interconnect system, and includes a first processor1170and a second processor1180coupled via a point-to-point interconnect1150. Each of processors1170and1180may be some version of the processor900. In one embodiment of the disclosure, processors1170and1180are respectively processors1010and1015, while coprocessor1138is coprocessor1045. In another embodiment, processors1170and1180are respectively processor1010coprocessor1045.

Processors1170and1180are shown including integrated memory controller (IMC) units1172and1182, respectively. Processor1170also includes as part of its bus controller units point-to-point (P-P) interfaces1176and1178; similarly, second processor1180includes P-P interfaces1186and1188. Processors1170,1180may exchange information via a point-to-point (P-P) interface1150using P-P interface circuits1178,1188. As shown inFIG. 11, IMCs1172and1182couple the processors to respective memories, namely a memory1132and a memory1134, which may be portions of main memory locally attached to the respective processors.

Processors1170,1180may each exchange information with a chipset1190via individual P-P interfaces1152,1154using point to point interface circuits1176,1194,1186,1198. Chipset1190may optionally exchange information with the coprocessor1138via a high-performance interface1139. In one embodiment, the coprocessor1138is a special-purpose processor, such as, for example, a high-throughput MIC processor, a network or communication processor, compression engine, graphics processor, GPGPU, embedded processor, or the like.

Chipset1190may be coupled to a first bus1116via an interface1196. In one embodiment, first bus1116may be a Peripheral Component Interconnect (PCI) bus, or a bus such as a PCI Express bus or another third generation I/O interconnect bus, although the scope of the present disclosure is not so limited.

As shown inFIG. 11, various I/O devices1114may be coupled to first bus1116, along with a bus bridge1118which couples first bus1116to a second bus1120. In one embodiment, one or more additional processor(s)1115, such as coprocessors, high-throughput MIC processors, GPGPU's, accelerators (such as, e.g., graphics accelerators or digital signal processing (DSP) units), field programmable gate arrays, or any other processor, are coupled to first bus1116. In one embodiment, second bus1120may be a low pin count (LPC) bus. Various devices may be coupled to a second bus1120including, for example, a keyboard and/or mouse1122, communication devices1127and a storage unit1128such as a disk drive or other mass storage device which may include instructions/code and data1130, in one embodiment. Further, an audio I/O1124may be coupled to the second bus1120. Note that other architectures are possible. For example, instead of the point-to-point architecture ofFIG. 11, a system may implement a multi-drop bus or other such architecture.

Referring now toFIG. 12, shown is a block diagram of a second more specific exemplary system1200in accordance with an embodiment of the present disclosure. Like elements inFIGS. 11 and 12bear like reference numerals, and certain aspects ofFIG. 11have been omitted fromFIG. 12in order to avoid obscuring other aspects ofFIG. 12.

FIG. 12illustrates that the processors1170,1180may include integrated memory and I/O control logic (“CL”)1172and1182, respectively. Thus, the CL1172,1182include integrated memory controller units and include I/O control logic.FIG. 12illustrates that not only are the memories1132,1134coupled to the CL1172,1182, but also that I/O devices1214are also coupled to the control logic1172,1182. Legacy I/O devices1215are coupled to the chipset1190.

Referring now toFIG. 13, shown is a block diagram of a SoC1300in accordance with an embodiment of the present disclosure. Similar elements inFIG. 9bear like reference numerals. Also, dashed lined boxes are optional features on more advanced SoCs. InFIG. 13, an interconnect unit(s)1302is coupled to: an application processor1310which includes a set of one or more cores202A-N and shared cache unit(s)906; a system agent unit910; a bus controller unit(s)916; an integrated memory controller unit(s)914; a set or one or more coprocessors1320which may include integrated graphics logic, an image processor, an audio processor, and a video processor; an static random access memory (SRAM) unit1330; a direct memory access (DMA) unit1332; and a display unit1340for coupling to one or more external displays. In one embodiment, the coprocessor(s)1320include a special-purpose processor, such as, for example, a network or communication processor, compression engine, GPGPU, a high-throughput MIC processor, embedded processor, or the like.

FIG. 14is a block diagram contrasting the use of a software instruction converter to convert binary instructions in a source instruction set to binary instructions in a target instruction set according to embodiments of the disclosure. In the illustrated embodiment, the instruction converter is a software instruction converter, although alternatively the instruction converter may be implemented in software, firmware, hardware, or various combinations thereof.FIG. 14shows a program in a high level language1402may be compiled using an x86 compiler1404to generate x86 binary code1406that may be natively executed by a processor with at least one x86 instruction set core1416. The processor with at least one x86 instruction set core1416represents any processor that can perform substantially the same functions as an Intel processor with at least one x86 instruction set core by compatibly executing or otherwise processing (1) a substantial portion of the instruction set of the Intel x86 instruction set core or (2) object code versions of applications or other software targeted to run on an Intel processor with at least one x86 instruction set core, in order to achieve substantially the same result as an Intel processor with at least one x86 instruction set core. The x86 compiler1404represents a compiler that is operable to generate x86 binary code1406(e.g., object code) that can, with or without additional linkage processing, be executed on the processor with at least one x86 instruction set core1416. Similarly,FIG. 14shows the program in the high level language1402may be compiled using an alternative instruction set compiler1408to generate alternative instruction set binary code1410that may be natively executed by a processor without at least one x86 instruction set core1414(e.g., a processor with cores that execute the MIPS instruction set of MIPS Technologies of Sunnyvale, Calif. and/or that execute the ARM instruction set of ARM Holdings of Sunnyvale, Calif.). The instruction converter1412is used to convert the x86 binary code1406into code that may be natively executed by the processor without an x86 instruction set core1414. This converted code is not likely to be the same as the alternative instruction set binary code1410because an instruction converter capable of this is difficult to make; however, the converted code will accomplish the general operation and be made up of instructions from the alternative instruction set. Thus, the instruction converter1412represents software, firmware, hardware, or a combination thereof that, through emulation, simulation or any other process, allows a processor or other electronic device that does not have an x86 instruction set processor or core to execute the x86 binary code1406.