Nonvolatile memory device and programming method thereof

A programming method is for programming a nonvolatile memory device including a plurality of strings disposed perpendicular to a substrate and connected between bitlines and a common source line. The programming method includes setting up the common source line to a predetermined voltage, floating the setup common source line, performing a program operation on memory cells connected to a selected wordline, and performing a verify operation on the memory cells.

CROSS-REFERENCE TO RELATED APPLICATIONS

A claim of priority under 35 USC §119 is made to Korean Patent Application No. 10-2014-0012170, filed on Feb. 3, 2014, the entirety of which is hereby incorporated by reference.

BACKGROUND

Embodiments of the present disclosure relate to nonvolatile memory devices and programming methods thereof.

In general, semiconductor memory devices are classified as either volatile semiconductor memory devices or nonvolatile semiconductor memory devices. In contrast to volatile memory device, nonvolatile memory devices can retain their stored data even when their power supplies are interrupted. Data stored in a nonvolatile memory device may be permanent or reprogrammed according to memory fabrication technology. Nonvolatile memory devices are used for program and microcode storage in a wide variety of applications in the computer, avionics, telecommunications, and consumer electronics industries.

SUMMARY

The present disclosure provides a nonvolatile memory device and a programming method thereof.

Embodiments of the disclosure provide a programming method of a nonvolatile memory device including a plurality of strings disposed perpendicular to a substrate between bitlines and a common source line. In some embodiments, the programming method may include setting up the common source line to a predetermined voltage, floating the setup common source line, performing a program operation on memory cells connected to a selected wordline, and performing a verify operation on the memory cells.

Embodiments of the disclosure provide a nonvolatile memory device. In some embodiments, the nonvolatile memory device may include a memory cell array including a plurality of memory blocks including a plurality of strings disposed perpendicular to a substrate and coupled between bitlines and a common source line, an address decoder configured to select any one of the memory blocks in response to an address, an input/output circuit configured to store data to be programmed into memory cells connected to a selected one of wordlines of the selected memory block during a program operation or store data read from memory cells connected to the selected wordline during a verify operation, a common source line driver configured to float the common source line after setting up the common source line to a predetermined voltage, and a control logic configured to control the address decoder, the input/output circuit, and the common source line driver during the program operation and the verify operation.

Embodiments of the disclosure provide a storage device. In some embodiments, the storage device may include at least one nonvolatile memory device including a plurality of memory blocks each including a plurality of strings formed in a direction perpendicular to a substrate and connected between bit lines and a common source line and a memory controller configured to control the at least one nonvolatile memory device, wherein the common source line is set to a predetermined voltage and then is floated in a program operation.

DETAILED DESCRIPTION

FIG. 1illustrates a nonvolatile memory device100according to an exemplary embodiment of the inventive concept. As illustrated, the nonvolatile memory device100includes a memory cell array110, an address decoder120, an input/output (I/O) circuit130, a control logic140, and a CSL driver150.

The nonvolatile memory device100may be a NAND flash memory, a vertical NAND (VNAND), a NOR flash memory, a resistive random access memory (RRAM), a phase-change random access memory (PRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FRAM), a spin transfer torque random access memory (STT-RAM) or the like. In addition, the nonvolatile memory device100may be implemented using a three-dimensional (3D) array structure. The inventive concept may be applied to not only a flash memory device in which a charge storage layer includes a conductive floating gate but also a charge trap flash (CTF) memory device in which a charge storage layer includes an insulating layer. For the brevity of description, the nonvolatile memory device100will be referred to as a vertical NAND flash memory device (VNAND).

The memory cell array110includes a plurality of memory blocks BLK1to BLKz (z being an integer equal to or greater than 2). Each of the memory blocks BLK1to BLKz is connected to the address decoder120through wordlines WLs, at least one string selection line SSL, and at least one ground selection line GSL and is connected to the I/O circuit130through bitlines BLs. The wordlines WLs may be implemented in the form of stacked plates.

Each of the memory blocks BLK1to BLKz includes a plurality of three-dimensional strings arranged in a first direction and a second direction (differing from the first direction) on a substrate and arranged in a third direction (perpendicular to a plane formed in the first direction and the second direction). Each of the strings includes at least one selection transistors, a plurality of memory cells, and at least one ground selection transistors which are coupled in series between a bitline and a common source line CSL. Each of the memory cells may store at least one bit. In some embodiments, at least one dummy cell may be included between at least one string selection transistor and a plurality of memory cells. In other embodiments, at least one dummy cell may be included between a plurality of memory cells and at least one ground selection transistor.

The address decoder120may select one of the memory blocks BLK1to BLKz in response to an address. The address decoder120is connected to the memory cell array through wordlines WLs, at least one string selection line SSL, and at least one ground selection line GSL. The address decoder120selects the wordlines WLs, the string selection line SSL, and the ground selection line GSL using a decoded row address. The address decoder120may decode a column address among input addresses. The decoded column address may be transferred to the I/O circuit130. In some embodiments, the address decoder120may include a row decoder, a column decoder, an address buffer, and the like.

The I/O circuit130is connected to the memory cell array110through bitlines BLs. The I/O circuit130may be implemented to receive the decoded column address from the address decoder120. The I/O circuit130may select the bitlines BLs using the decoded column address.

The I/O circuit130receives data from an external entity (e.g., memory controller) and stores the received data in the memory cell array110. The I/O circuit130may read data from the memory cell array110and output the read data to an external entity. The I/O circuit130may read data from a first region of the memory cell array110and store the read data in a second region of the memory cell array110. For example, the I/O circuit130may be implemented to perform a copyback operation.

The control logic140controls the overall operation (program/read/erase operations, etc.) of the nonvolatile memory device100. The control logic140may operate in response to externally input control signals or command.

In some embodiments, the control logic140may generate a CSL control signal SCSL to control the CSL driver150. The CSL control signal SCSL may be generated based on environmental information such as a temperature, an operating mode, the number of program loops, time, and the like.

The CSL driver150may be supplied with a CSL voltage Vcs1and supply a voltage corresponding to the CSL voltage Vcs1to a common source line CSL. The CSL driver150may float the CSL in response to the CSL control signal SCSL. For example, the CSL control signal SCSL be provided to the CSL driver150to float the CSL after setting up a CSL level to a predetermined value during a program operation. In addition, the CSL control signal SCSL may be provided to the CSL driver150to float the CSL when predetermined time has passed after setting up the CSL level to a predetermined value during a program operation.

A general nonvolatile memory device is maintained at a CSL setup state to enhance boosting efficiency during a program operation. However, the level of bitlines may rise due to coupling between the CSL and bitlines. Thus, incremental step pulse programming (ISPP) effect may be reduced to decrease program speed.

In the meantime, according to the above-described nonvolatile memory device100, a CSL is set up and then floated during a program operation to prevent coupling between the CSL and bitlines. Thus, program speed of the nonvolatile memory device100may be improved as compared to that of a conventional nonvolatile memory device. Moreover, the CSL is floated during the program operation to reduce consumption of power supplied to the CSL.

FIG. 2illustrates an example of a memory block BLK inFIG. 1. Referring toFIG. 2, four sub-blocks are formed on a substrate111. Each of the sub-blocks is formed by stacking at least one ground selection line GSL, a plurality of wordlines WLs, and at least one string selection line SSL in the form of a plate between wordline cuts on the substrate111. The at least one string selection line SSL is divided into string selection line cuts. A wall-shaped common source line CSL may be formed inside each wordline cut.

In some embodiments, at least one dummy wordline may be stacked in the form of a plate between a ground selection line GSL and wordlines WLs or at least one dummy wordline may be stacked in the form of a plate between wordlines WLs and a string selection line SSL.

Although not shown in this figure, each wordline cut includes a common source line CSL. In some embodiments, a common source line included in each wordline cut is commonly connected. A pillar connected to a bitline penetrates at least one ground selection line GSL, a plurality of wordlines WLs, and at least one string selection line SSL to form a string.

As shown inFIG. 2, a target between wordline cuts is a sub-block. However, the inventive concept is not limited thereto. In the inventive concept, a target between a wordline cut and a string selection line cut is named a sub-block.

A block BLK according to an embodiment of the inventive concept may be implemented using a structure in which two wordlines are merged into one, i.e., a merged wordline structure.

FIG. 3illustrates a portion of a cross-sectional view of the memory block BLK inFIG. 2. As illustrated, the memory block BLK is formed in a direction perpendicular to the substrate111. An n+ doped region112is formed on the substrate111.

Gate electrode layers113and insulating layers114are alternately deposited on the substrate111. In some embodiments, an information storage layer115may be formed on side surfaces of the gate electrode layers113and the insulating layers114.

The gate electrode layer113may be connected to a ground selection line GSL, a plurality of wordlines WL1to WL8, and a string selection line SSL.

The information storage layer115may include a tunnel insulating layer, a charge storage layer, and a block insulating layer. The tunnel insulating layer may act as an insulating layer in which charges may travel due to tunneling effect. The charge storage layer may include an insulating layer to trap charges. The charge storage layer may be made of, for example, nitride (SiN) or metal oxide (aluminum oxide or hafnium oxide). The blocking insulating layer may act as an insulating layer between the gate electrode layer and the charge storage layer. The blocking insulating layer may be made of silicon oxide. The tunnel insulating layer, the charge storage layer, and the blocking insulating layer may be made of an insulating layer having an oxide-nitride-oxide (ONO) structure.

A pillar116may be formed by vertically patterning the gate electrode layer113and the insulating layer114.

The pillar116is coupled between a bitline and the substrate111through the gate electrode layer113and the insulating layer114. The inside of the pillar116may be a filling dielectric pattern117which is made of an insulating material such as silicon oxide or an air gap. The outside of the pillar116may be a vertical active pattern118which includes a channel semiconductor. In some embodiments, the vertical active pattern118may be made of p-type silicon. A certain single memory cell included in a string may include a charge dielectric pattern117, a vertical active pattern118, the charge storage layer115, and the gate electrode layer113that are sequentially disposed from the inside of the pillar116.

Common source lines CSL extend on the n+ doped regions112. The common source line CSL may be included in the form of a well inside a wordline cut.

FIG. 4is an exemplary equivalent circuit diagram of the memory block BLK inFIG. 2. As illustrated, cell strings CS11to CS33are coupled between bitlines BL1to BL3and a common source line CSL. Each of the cell strings (e.g., CS11) may include a ground selection transistor GST, a plurality of memory cells MC1to MC8, and a string selection transistor SST. For the convenience of description, let it be assumed that the number of memory cells included in a string is eight. However, the number of memory cells included in a string according to the inventive concept is not limited thereto.

The string selection transistor SST is connected to a string selection line SSL. The string selection line SSL is divided into first to third string selection lines SSL1to SSL3. InFIG. 4, three string selection lines SSL1to SSL3connected to a single bitline are shown. However, the inventive concept is not limited thereto. The memory block BLK according to the inventive concept may include at least two string selection lines corresponding to a single bitline.

The ground selection transistor GST is connected to a ground selection line GSL. Ground selection lines GSL of respective cell strings are connected. The string selection transistor SST is connected to a bitline BL, and the ground selection transistor GST is connected to a common source line CSL.

The memory cells MC1to MC8may be connected to corresponding wordlines WL1to WL8, respectively. A set of memory cells connected to a single wordline and programmed at the same time is referred to as a page. A memory block BLK1includes a plurality of pages. A plurality of pages may be connected to a single wordline. Referring toFIG. 4, a wordline (e.g., WL4) is commonly connected to three pages from the common source line CSL.

Each memory cell may store one a single bit of data or two or more bits of data. A memory cell for storing a single bit of data is referred to as a single-level cell (SLC) or a single-bit cell. A memory cell for storing two or more bits of data is referred to as a multi-level cell (MLC) or a multi-bit cell. In case of a two-bit MLC, two pages of data are stored in a single physical page. Thus, two pages of data may be stored in a memory cell connected to the fourth wordline WL4.

On the other hand, the nonvolatile memory device100may be implemented using a charge trap flash (CTF) memory device. In this case, charges trapped to a programmed CTF memory device may be redistributed and lost, i.e., initial verify shift (IVS) occurs with the lapse of time. A reprogramming operation may be performed to overcome such distribution degradation.

The memory block BLK inFIG. 4has a structure in which a ground selection line GSL is shared. However, the inventive concept need not be limited thereto. The ground selection line GSL of the inventive concept may be implemented with a divided structure, similarly to a string selection line.

FIG. 5illustrates another embodiment of the equivalent circuit diagram of the memory block BLK inFIG. 2. As illustrated, a memory block BLKa includes divided ground selection lines GSL1, GSL2, and GSL3as compared to the memory block BLK inFIG. 4. The number of the divided ground selection lines GSL1to GSL3shown inFIG. 5is three. However, the inventive concept is not limited thereto. The memory block BLKa of the inventive concept may include at least two ground selection lines.

In the memory blocks shown inFIGS. 2 to 5, a string is formed between a substrate111and a bitline. However, a structure of the string of the inventive concept is not limited thereto. The string of the inventive concept may include a first string formed between a bitline and a substrate and a second string formed between the substrate and a common source line.

FIG. 6illustrates a memory block according to another exemplary embodiment of the inventive concept. As illustrated, a string may be formed between a bitline BL and a common source line CSL and may include first memory cells formed vertically between the bitline BL and a substrate and second memory cells formed vertically between the substrate and the common source line CSL.

In some embodiments, each of strings may be at least two pillars.

In some embodiments, a memory block BLKb may be implemented using a PBiCS (Pipe—Shaped Bit Cost Scalable) structure.

FIG. 7illustrates a CSL driver150according to an exemplary embodiment of the inventive concept. As illustrated, the CSL driver150may include transistors MT1to MT3and a depletion transistor DT.

A first transistor MT1may transfer a CSL voltage Vcs1to a node ND in response to an enable signal EN1. The node ND is connected to a common source line CSL via a depletion transistor DT. In some embodiments, a body of the first transistor MT1may be connected to a drain terminal of the first transistor MT1, as shown inFIG. 7. A second transistor MT2may cut off transfer of the CSL voltage Vcs1to the common source line in response to a CSL control signal SCSL to float the common source line CSL. A third transistor MT3may connect the common source line CSL to a ground terminal GND in response to an enable signal EN2. The depletion transistor DT may be coupled between the node ND and the common source line CSL, may include a gate terminal to be applied with a gate voltage VG, and may float the common source line CSL when a voltage of the common source line CSL is equal to or greater than a predetermined value or float the common source line CSL when a voltage of the node ND is equal to or greater than a predetermined value.

The CSL driver150may supply the CSL voltage Vcs1to the common source line CSL in response to the first enable signal EN1, may ground the common source line CSL to the ground terminal GND, and may float the common source line CSL in response to the second enable signal EN2.

The CSL driver150shown inFIG. 7is merely exemplary, and the CSL driver150according to the inventive concept may be implemented using various structures.

FIG. 8illustrates CSL level control during a program operation of a nonvolatile memory device100according to an exemplary embodiment of the inventive concept. Referring toFIGS. 1 to 8, as a program loop is executed, the CSL level control may be performed as follows. A common source line CSL is floated during initial program loops1and2. At this point, the level of the common source line CSL may be 0 volt. However, the level of the common source line CSL need not be limited thereto.

There may be a memory cell on which a program operation is completed while passing through the initial program loops1and2. Accordingly, memory cells to be program-inhibited may increase during the next program loop. Thus, the level of the common source line CSL increases to a predetermined value due to bitline coupling even when the common source line CSL is floated during a bitline setup operation before applying program pulses Vpgm of respective program loops3,4, and5. The common source line CSL may be grounded to a ground terminal GND before applying verify pulses C and F of the respective program loops3,4, and5. The verify pulse C is a coarse verify pulse, and the verify pulse F is a fine verify pulse. The verify operation of the inventive concept is not limited thereto, and the coarse verify pulse C may not be applied or may be selectively applied.

As program loops1,2,3,4, and5are much executed, program-completed memory cells may increase rapidly and thus memory cells to be program-inhibited may increase rapidly. As a result, an influence on bitline coupling may increase. Accordingly, the level of the common source line CSL may be made higher than that of the previous program loops3,4, and5due to coupling during bitline setting operations of the next program loops6and7. Thereafter, the common source line CSL may be connected to the ground terminal GND to be discharged before applying verify pulses C and F of the respective program loops6and7.

In the CSL control of the nonvolatile memory device100according to an embodiment of the inventive concept, the common source line CSL may be floated before applying a program pulse Vpgm and may be discharged before applying verify pulses C and F.

On the other hand, a nonvolatile memory device according to an embodiment of the inventive concept may be implemented to sense the level of a common source line CSL such that floating of the common source line CSL may be controlled.

FIG. 9illustrates a nonvolatile memory device100aaccording to another embodiment of the inventive concept. As illustrated, the nonvolatile memory device100aincludes a memory cell array110, an address decoder120, an input/output (I/O) circuit130, a control logic140a, a CSL driver150, and a CSL level detector152. The nonvolatile memory device110afurther includes the CSL level detector152, as compared to the nonvolatile memory device100shown inFIG. 1.

The CSL level detector152detects the level of a common source line CSL. The control logic140amay generate a CSL control signal SCSL to decide whether or not to float the common source line CSL using the detected level of the common source line CSL. For example, when the level of the common source line CSL is equal to or greater than a predetermined value during a program operation, a CSL control signal SCSL may be generated to float the common source line.

On the other hand, a nonvolatile memory device according to an embodiment of the inventive concept may be implemented to control floating of a common source line CSL based on a temperature of a memory cell array.

FIG. 10illustrates a nonvolatile memory device100baccording to another embodiment of the inventive concept. As illustrated, the nonvolatile memory device100bincludes a memory cell array110, an address decoder120, an input/output circuit130, a control logic140b, a CSL driver150, a CSL level detector, and a temperature sensor154. The nonvolatile memory device110bfurther includes the temperature sensor154, as compared to the nonvolatile memory device100shown inFIG. 9.

The temperature sensor154senses a temperature of the memory cell array110to output a corresponding value. The control logic140bmay generate a CSL control signal SCSL to determine whether a common source line CSL is floated, based on a value corresponding to the level of the common source line CSL output from the CSL level detector140and a temperature value output from the temperature sensor154. For example, when the level of the common source line CSL is equal to or greater than a predetermined value and a temperature of the memory cell array110is equal to or greater than a predetermined value during a program operation, the CSL control signal SCSL may be generated to float the common source line CSL. To put it another way, the level of the common source line CSL output from the CSL level detector142may be compensated according to the temperature of the memory cell array110.

FIG. 11illustrates a first embodiment of a programming method of a nonvolatile memory device according to the inventive concept. Referring toFIGS. 1 to 11, a programming method of a nonvolatile memory device will now be described. A common source line CSL is set up to a predetermined value. The predetermined value may be 0 volt, as shown inFIG. 7(S110). The setup common source line CSL is floated (S120). A program operation is executed by applying a program pulse to a selected wordline (S130). A verify operation is executed to whether the program operation is properly executed (S140).

According to the above-described programming method, a program operation may be performed after floating a common source line CSL of a predetermined value.

On the other hand, the programming method may further include determining whether the common source line CSL is floated.

FIG. 12illustrates a second embodiment of a programming method of a nonvolatile memory device according to the inventive concept. Referring toFIG. 12, the programming method may further include determining whether a common source line CSL need to be floated (S115), as compared to the programming method described with reference toFIG. 11. If the common source line CSL need not be floated, the flow proceeds to S130.

The determination on whether the common source line CSL need to be floated may be made depending on environmental information such as the number of program loops, the level of the common source line CSL, a temperature of a memory cell array, and the like.

The above-described programming method may include determining whether a common source line CSL is floated.

FIG. 13illustrates a third embodiment of a programming method of a nonvolatile memory device according to the inventive concept. Referring toFIGS. 1 to 10andFIG. 13, a programming method of a nonvolatile memory device will now be described.

Channels of selected strings and unselected strings will be setup (S210). Charges included in a channel may be discharged to a ground terminal GND during the setup operation of the channels. Data to be programmed may be set up to an I/O circuit130(seeFIG. 1). A plurality of page buffers included in the I/O circuit130receives the data to be programmed and performs a dumping operation on input data, if necessary (S220). Then a program loop may be executed. The program loop is executed from S230to S280and may be repeated by applying a program pulse Vpgm to a predetermined value when a program operation, as a result of the verify operation, is not completed.

The steps of the program loop will now be described. Bitlines BLs and a common source line CSL may be set up. For example, bitlines connected to a memory cell to be programmed may be set up to 0 volt, and a bitline connected to a memory cell to be program-inhibited may be set up to a power supply voltage VDD. The common source line CSL may be set up to a predetermined value, e.g., 0 volt (S230).

The common source line CSL may be floated. The floating of the common source line CSL may be done by default or optionally (S235). A program operation is executed by applying a program pulse Vpgm, i.e., program voltage to a selected wordline and applying a program pass voltage to unselected wordlines (S240).

Charges of the wordlines WLs may be discharged to execute a verify operation (S250). In some embodiments, a discharge operation of the common source line CSL may be executed in step-type or lamp-type. A recovery operation may be performed on the bitlines BLs (S2170). A verify operation may be executed by applying verify pulses C and F to verify whether programmed memory cells connected to the selected wordline are properly programmed (S280).

InFIG. 13, a discharge operation of the common source line CSL is executed following a discharge operation of the wordlines WLs. However, the program operation of the inventive concept is not limited thereto. The discharge operation of the wordlines WLs may be executed following the discharge operation of the common source line CSL.

FIG. 14illustrates a fourth embodiment of a programming method of a nonvolatile memory device according to the inventive concept. Referring toFIGS. 1 to 10andFIG. 14, a programming method of a nonvolatile memory device is different in S250aand S250bfrom the programming method described with reference toFIG. 13. In the programming method according to this embodiment, wordlines WLs are discharges (S260a) after a common source line CSL is discharged (S250a).

FIG. 15is a block diagram of a storage device10according to an exemplary embodiment of the inventive concept. As illustrated, the storage device10includes at least one nonvolatile memory device12and a memory controller14to control the nonvolatile memory device12. The storage device10may be a storage medium such as a memory card (e.g., CF, SD, microSD, etc.) and a USB storage device.

The nonvolatile memory device12may be implemented using the nonvolatile memory devices100,100a, and100bdescribed with reference toFIGS. 1 to 14.

The memory controller14controls read, write, and erase operation of the nonvolatile memory device12in response to a host request. The memory controller14includes at least one central processing unit (CPU)14-1, a random access memory (RAM)14-2, an error correction code (ECC) circuit14-3, a host interface14-5, and a nonvolatile memory (NVM) interface14-6.

The CPU14-1may control the overall operation (e.g., read, write, file system management, bad page management, etc.) of the nonvolatile memory device12. The RAM14-2operates according to control of the CPU14-1and may be used as a work memory, a buffer memory, and a cache memory. When the RAM14-2is used as a work memory, data processed by the CPU14-1is temporarily stored. When the RAM14-2is used as a buffer memory, it buffers data to be transferred from a host to the nonvolatile memory device and/or transferred from the nonvolatile memory device12to the host. When the RAM14-2is used as a cache memory, it enables a low-speed nonvolatile memory device12to operate at high speed.

The ECC circuit14-3generates an error correction code (ECC) to correct a fail bit or an error bit of data received from the nonvolatile memory device12. The ECC circuit14-3performs error correction encoding on data provided to the nonvolatile memory device12to generate data to which a parity bit is added. The parity bit may be stored in the nonvolatile memory device12. The ECC circuit14-3may perform error correction decoding on data output from the nonvolatile memory device12. The ECC circuit14-3may correct an error using a parity. The ECC circuit14-3may correct an error using coded modulation such as low density parity check (LDPC) code, BCH code, turbo code, Reed-Solomon code, convolution code, recursive systematic code (RSC), trellis-coded modulation (TCM), block coded modulation (BCM).

The memory controller14exchanges data with a host via the host interface14-5and exchanges data with the nonvolatile memory device12via the NVM interface14-6. The host interface14-5may be connected to the host via a parallel AT attachment bus (PATA), a serial AT attachment bus (SATA), SCSI, USB, PCIe, a NAND interface.

In some embodiments, the memory controller14may accommodate a wireless communication function (e.g., WiFi).

As described above, a nonvolatile memory device according to an embodiment of the inventive concept starts a CSL level control method for improving a program distribution. In general, a common source line (CSL) is set up to a constant level during a program operation for improving program inhibit boosting efficiency. However, in a 3D-NAND structure with high CSL capacitance, CSL setup time increases and thus the CSL level may be set up even during a program period. This may have an influence on program characteristics due to coupling between the CSL and a bitline (BL). The nonvolatile memory device may control the CSL level during a program period to mitigate the above side effect.

A nonvolatile memory device according to the inventive concept may float a common source line (CSL) after setting up the level of the CSL. Thus, coupling between the CSL and a bitline may be minimized to prevent reduction of incremental step pulse programming (ISPP) effect. For example, the CSL may be automatically floated after being set up to a predetermined voltage or the CSL may be set up after predetermined time has elapsed.

The inventive concept may be applied to a solid-state drive (SSD).

FIG. 16illustrates an application example of an SSD1000according to the inventive concept. As illustrated, the SSD1000includes a plurality of nonvolatile memory devices1100and an SSD controller1200.

The nonvolatile memory devices1100may be implemented to optionally receive an external high voltage Vpp. Each of the nonvolatile memory devices1100may be implemented to execute a program operation after floating a common source line CSL, as described with reference toFIGS. 1 to 14. The SSD controller1200is connected to the nonvolatile memory devices1100vias a plurality of channels CH1to CHi (i being an integer equal to or greater than 2). The SSD controller1200includes at least one processor1210, a buffer memory1220, an error correction code (ECC) circuit1230, a host interface1250, and a nonvolatile memory interface1260.

The buffer memory1220may temporarily store data required to drive the memory controller1200. The buffer memory1220may include a plurality of memory lines to store data or a command. The memory lines may be mapped to cache lines by various methods. The ECC circuit1230may calculate an ECC value of data to be programmed during a write operation, correct an error of data read during a read operation based on the ECC value, and correct an error of restored data from the nonvolatile memory device1100during a data restore operation. Although not shown, the SSD controller1200may further include a code memory storing code data required to drive the memory controller1200. The code memory may be implemented using a nonvolatile memory device.

The host interface1250may provide an interface function with an external device. The host interface1250may be a NAND flash interface. The host interface1250may be implemented using various interfaces, other than the NAND flash interface. The nonvolatile memory interface1260may provide an interface function with the nonvolatile memory device1100.

The SSD1000executes a program operation after floating a common source line CSL. Thus, bitline coupling may be minimized to expect improvement in program speed.

The inventive concept may be applied to an embedded multimedia card (eMMC), a moviNAND flash memory, and an iNAND flash memory.

FIG. 17illustrates an application example of an eMMC2000according to the inventive concept. As illustrated, the eMMC2000may include at least one NAND flash memory device2100and a controller2200.

The NAND flash memory device2100may be implemented to execute a program operation such that a common source line CSL is controlled to minimize coupling between the common source line CSL and a bitline, as described with reference toFIGS. 1 to 14. The controller2200is connected to the NAND flash memory device2100through a plurality of channels. The controller2200includes at least one control core2210, a host interface2250, and a NAND interface2260. The at least one control core2210controls the overall operation of the eMMC2000. The host interface2250performs host interfacing with the controller2210. The NAND interface2260performs interfacing between the NAND flash memory device2100and the controller2200. In some embodiments, the host interface2250may be a parallel interface (e.g., MMC interface). In other embodiments, the host interface2250may be a serial interface (e.g., UHS-II or UFS interface). In other embodiments, the host interface2250may be a NAND interface.

The eMMC2000receives power supply voltages Vcc and Vccq from a host. A first power supply voltage Vcc (e.g., 3.3 volts) is supplied to the NAND flash memory device1100and the NAND interface1230, and a second power supply voltage Vccq (e.g., 1.8 volts/3.3 volts) is supplied to the controller1200. In some embodiments, the eMMC1000may optionally receive an external high voltage Vpp.

In order to improve program speed, the eMMC2000may control whether the common source line CSL is floated.

The inventive concept may be applied to a universal flash storage (UFS).

FIG. 18illustrates an application example of a UFS system3000according to the inventive concept. As illustrated, the UFS system3000may include a UFS host3100, UFS devices3200and3300, an embedded UFS device3300, and a removable UFS card3400. The UFS3100may be an application processor for a mobile device. The UFS host3100, the UFS devices3200and3300, the embedded UFS device3300, and the removable UFS card3400may communicate with external devices by means of a UFS protocol, respectively. At least one of the UFS devices3200and3300, the embedded UFS device3300, and the removable UFS card3400may be implemented using the storage device10shown inFIG. 15.

The embedded UFS device3300and the removable UFS card3400may communicate with each other by means of another protocol, other than the UFS protocol. The UFS host3100and the removable UFS card3400may communicate with each other by means of various card protocols (e.g., UFDs, MMC, secure digital (SD), mini SD, micro SD, etc.).

The inventive concept may be applied to a mobile device.

FIG. 19illustrates an application example of a mobile device4000according to the inventive concept. As illustrated, the mobile device4000may include an application processor4100, a communication module4200, a display/touch module4300, a storage device4400, and a mobile RAM4500.

The application processor4100controls the overall operation of the mobile device4000. The communication module4200may be implemented to control wired/wireless communication with an external entity. The display/touch module4300may be implemented to display data processed by the application processor4100or receive data from a touch panel. The storage device4400may be implemented to store user data. The storage device4400may be an eMMC, an SSD or a UFS device. The storage device4400may be implemented to control a common source line CSL to improve program speed. The mobile RAM4500may be implemented to temporarily store data required during a processing operation of the mobile device4000.

The mobile device4000includes the storage device4400to improve program speed, contriving improvement in system performance.

A memory system or a storage device according to an embodiment of the inventive concept may be packaged according to any of various packaging technologies. For example, the memory system or the storage device may be packaged by one of PoP (Package on Package), Ball grid arrays (BGAs), Chip scale packages (CSPs), Plastic Leaded Chip Carrier (PLCC), Plastic Dual In-Line Package (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP), Small Outline (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package (WFP), and Wafer-Level Processed Stack Package (WSP).

According to the above-described nonvolatile memory device and a programming method thereof, a common source line is floated after being set up to a predetermined voltage. Thus, coupling between a bitline and the common source line is reduced to improve program speed.

While the present disclosure has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure as defined by the following claims. For example, it is possible to adjust the driving capability of a sub word line driver or adjust the slope of level of applied driving signals by changing, adding, or removing the circuit configuration or arrangement in the drawings without departing from the technical spirit of the present disclosure in other cases.