Multiple clock domain tracing

An integrated circuit with multiple clock domain tracing capability includes a debug module including a global time stamp counter for counting pulses of a reference clock signal to provide a global time stamp, a first granularity counter for counting pulses of a first clock signal to provide a first granularity count, a second granularity counter for counting pulses of a second clock signal to provide a second granularity count and a trace cache buffer for selectively storing in a first partition the global time stamp, the first granularity count, and first data synchronous to the first clock signal, and for selectively storing in a second partition the global time stamp, the second granularity count, and second data synchronous to the second clock signal.

Related subject matter is found in a copending patent application entitled “Correlating Traces in a Computing System”, U.S. patent application Ser. No. 13/328,512, filed Dec. 16, 2011, by Ryan D. Bedwell et al; and in a copending patent application entitled “Multiple Clock Domain Debug Capability”, U.S. patent application Ser. No. 13/587,631, filed Aug. 16, 2012, by Scott P. Nixon et al.

FIELD

This disclosure relates generally to data processors, and more specifically to data processors capable of storing trace data.

BACKGROUND

Consumers continue to demand computer systems with higher performance and lower cost. To address these challenges, integrated circuits are designed as systems on chips (“SoCs”) and include an increasing number of modules, such as central processing units (“CPUs”), advanced processing units (“APUs”), graphics processing units (“GPUs”), memory sub-systems, system controllers, and complex peripheral functions. At the same time, gaining visibility into the operation of the system and determining that the system is operating as desired is increasingly difficult. The complexity and cost of finding and eliminating functional “bugs” provide significant challenges. Also, generating, storing, and analyzing the data required to determine if the defects are generally within the system, within a specific module, or between a set of modules present a significant challenge.

In the following description, the use of the same reference numerals in different drawings indicates similar or identical items. Unless otherwise noted, the word “coupled” and its associated verb forms include both direct connection and indirect electrical connection by means known in the art, and unless otherwise noted any description of direct connection implies alternate embodiments using suitable forms of indirect electrical connection as well.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

FIG. 1illustrates in block diagram form a microprocessor100with tracing capability known in the prior art. Microprocessor100generally includes a CPU core110, a trace generation unit120, and a trace buffer140. Trace generation unit120includes interface logic122, a test access port (“TAP”) controller124, a functional block126labeled “TRIGGER, SEQUENCER, AND COUNTERS”, and a trace packet generator130. Trace packet generator130includes a trace control132and a first-in, first-out buffer (“FIFO”)134.

CPU core110transmits and receives a variety of signals relevant to its operational state that are externally visible, such as addresses, data, control signals, interrupt and exception signals, and the like. Interface logic122has an input for receiving selected signals from CPU core110, and an output. TAP controller124has a bidirectional port for transmitting and receiving a set of input and/or output signals, and provides various control signals, not shown inFIG. 1, to configure and control the operation of trace generation unit120. Functional block126has an input connected to the output of interface logic122, and an output for providing an enable signal labeled “TRACE ENABLE”. Trace packet generator130has an input connected to the output of interface logic122, and an output for providing trace packets. Trace buffer140has an input connected to the output of trace packet generator130.

In operation, CPU core110executes instructions corresponding to one or more programs. CPU core110also provides a debug data stream that includes debug data that is generated by CPU core110while executing (or as a result of executing) instructions corresponding to one or more programs.

Trace generation unit120handles interfacing and communication with CPU core110, system test, and starting and stopping the generation of debug records. In particular, interface logic122manages communications between the receive circuits and transmit circuits of CPU core110and trace generation unit120. Interface logic122provides triggers to functional block126and also provides a debug data stream received from CPU CORE110to trace packet generator130.

For certain test standards, such as the Institute of Electrical and Electronic Engineers (“IEEE”) standard 1149.1, TAP controller124defines a common boundary scan test interface, to support the operation of on-chip and off-chip system testing. For compatible devices, an internal state machine drives the operation of TAP controller124. Instruction registers define the system-level testing protocol and data registers store the data structures under test by TAP controller124. TAP controller124controls the operation of trace generation unit120by providing test clocks for synchronizing the internal state machine, test data input and test data output for exchanging debug data between functional units and system test logic, and a reset signal for initializing the internal state machine of TAP controller124.

Functional block126initiates tracing in response to triggers and controls complex sequences and state changes of tracing operations as defined by certain trigger inputs and the tracing protocol. Also, functional block126provides counters for counting events.

Trace packet generator130stores information from CPU core110in response to an activation of TRACE ENABLE. This information includes values of input/output (“I/O”) signals, routing signal values, debug data, and the like. Also trace generation unit120stores debug data as a function of a specific configuration and a specific operating mode of CPU core110.

In particular, trace control132generates control signals to manage starting and stopping of trace packet generator130and to select the operation protocol of trace packet generator130. FIFO134collects and organizes debug data, by storing the debug data in the order the debug data was received. Likewise, FIFO134provides the debug data to trace buffer140in the order the debug data was received.

Trace buffer140stores the debug data, including data that represents certain activities of CPU core110, and data that includes other system information gathered during tracing. System resources access trace buffer140to analyze the debug data.

Because trace generation unit120and trace buffer140are dedicated to CPU core110, they can be located physically close to CPU core110on a common integrated circuit die. Trace generation unit120, trace buffer140, and CPU core110also operate within a single clock domain. In this example they are capable of performing adequate tracing of microprocessor100. However as the complexity and size of CPU core110increase, and microprocessor100is expanded to include multiple modules such as other CPUs or sub-portions of a CPU, GPUs, and the like with tracing capability located in remote parts of microprocessor100and having their own separate clock domains, trace generation unit120becomes insufficient to generate adequate trace data.

FIG. 2illustrates in block diagram form a portion of another microprocessor200with tracing capability known in the prior art. Microprocessor200generally includes a clock generator210, a circuit220labeled “CIRCUIT 1”, a circuit230labeled “CIRCUIT 2”, a multiplexor240, a trace cache buffer250, and a debug controller260.

Clock generator210has an output connected to an input of circuit220for providing a clock signal labeled “CLK1”, an output connected to an input of circuit230for providing a clock signal labeled “CLK2”, and an output connected to an input terminal of trace cache buffer250for providing a signal labeled “TRACE CLOCK”. Circuit220has an output connected to an input of multiplexor240over a bus labeled “DATA1”. Circuit230has an output connected to an input of multiplexor240over a bus labeled “DATA2”. Multiplexor240has an input connected to an output of debug controller260for receiving a signal labeled “SELECT” and an output connected to an input of trace cache buffer250over a bus. Trace cache buffer250has an input connected to an output of debug controller260for receiving a signal labeled “ENABLE”, an input for receiving the TRACE CLOCK, and an output for providing trace data. Debug controller260has an input for receiving a set of signals labeled “TRIGGERS”.

In operation, clock generator210provides clock signal CLK1 to circuit220, and clock signal CLK2 to circuit230. Also, clock generator210provides clock signal TRACE CLOCK to trace cache buffer250and debug controller260. Circuit220executes local logic functions based on timing edges provided by clock signal CLK1. In response, circuit220provides DATA1, where DATA1 includes debug data that reflect results of the activity of circuit220.

Likewise, circuit230executes local logic functions based on timing edges provided by clock signal CLK2. In response, circuit230provides DATA2, where DATA2 includes debug data that reflect results of the activity of circuit230. Circuit220and circuit230each initiate internal tracing sequences and each circuit controls the state changes of tracing operations as defined by certain trigger inputs and the tracing protocol.

In response to system TRIGGERS, debug controller260generates signal ENABLE to manage when trace cache buffer250collects trace records. Also, debug controller260provides signal SELECT to instruct multiplexor240when to provide either DATA1 or DATA2 to trace cache buffer250.

Trace cache buffer250stores debug data, including data that represents certain activities of circuit220and circuit230, such as certain values of input/output (“I/O”) signals, routing signal values, debug data values, and the like. Trace cache buffer250stores each trace entry synchronous with timing edges provided by the TRACE CLOCK. System resources access trace cache buffer250to analyze the debug data.

However, while microprocessor200captures traces synchronously with clock signal TRACE CLOCK, data may arrive at the input to trace cache buffer250in an unknown phase with respect to its own clock. For smaller, lower speed microprocessors, it may be possible to generate clock signal TRACE CLOCK in a way to ensure that the data is captured properly. However for larger microprocessors, the skew between clock signal CLK1 or clock signal CLK2 and clock signal TRACE CLOCK is unknown, and at certain points in time, trace cache buffer250may capture erroneous trace data while it is making a transition. Moreover, trace cache buffer250can store data from only one source at a time, whereas information from both circuit220and circuit230may be relevant to debugging the operation of microprocessor200.

FIG. 3illustrates in block diagram form an integrated circuit300with tracing capability according to some embodiments. Integrated circuit300generally includes a functional block310and a debug module320. Functional block310includes a circuit312labeled “CIRCUIT 1” and a circuit314labeled “CIRCUIT 2”. Debug module320includes a global time stamp counter (“TSC”)330, a functional block340, a functional block350, a trace cache buffer360, and a debug state machine (“DSM”)370. Global TSC330has an input for receiving a clock labeled “REFCLK” and an output connected to an input port of a synchronization (“SYNC”) latch346for conducting a set of least significant bits labeled “N LSBs”.

Functional block340includes a granularity counter342, a SYNC latch344, and a SYNC latch346. Granularity counter342has an input connected to an output of circuit312for receiving a signal labeled “CLK1” and an input labeled “RST” connected to an output of SYNC latch344for receiving a reset signal. SYNC latch344has an input for receiving REFCLK, and an input for receiving CLK1. SYNC latch346has an input for receiving CLK1.

Functional block350includes a granularity counter352, a SYNC latch354, and a SYNC latch356. Granularity counter352has an input connected to an output of circuit314for receiving a signal labeled “CLKN” and an input labeled “RST” connected to an output of SYNC latch354for receiving a reset signal. SYNC latch354has an input for receiving REFCLK, and an input for receiving CLKN. SYNC latch356has an input port for receiving the N LSBs of the global time stamp, and an input for receiving CLKN.

Trace cache buffer360includes a partition362, a partition364, a SYNC latch366, and a SYNC latch368. Partition362includes a number of storage locations for storing trace records, each having fields labeled “GLOBAL TSC”, “SS_CLKCnt”, and “DATA”. The GLOBAL TSC fields have an input port connected to an output of SYNC latch346. The SS_CLKCnt fields have an input connected to an output of granularity counter342. The DATA fields have an input connected to an output of circuit312for receiving DATA1. Partition362has an output for providing an output labeled “TRACE DATA OUT”.

Partition364includes a number of storage locations for storing trace records each having fields labeled “GLOBAL TSC”, “SS_CLKCnt”, and “DATA”. The GLOBAL TSC fields have an input connected to an output of SYNC latch356over a bus. The SS_CLKCnt fields have an input connected to an output of granularity counter352. The DATA fields have an input connected to an output of circuit314for receiving DATAN. Partition364has an input connected to an output of SYNC latch368and output for providing TRACE DATA OUT.

SYNC latch366has an input connected to an output of DSM370for receiving a signal labeled “DbgWrEn1” and an input for receiving a trigger signal labeled “TCLK”. SYNC latch368has an input connected to an output of DSM370for receiving a signal labeled “DbgWrEnN” and an input for receiving TCLK.

In operation, functional block310includes a certain number of circuit blocks, such as representative circuits312and314. Each circuit provides a source synchronous data stream. Each one of the source synchronous data streams includes a clock signal and corresponding data. For each one of the source synchronous data streams, a circuit sources the associated clock signal to provide a tight timing reference for the associated data. For integrated circuit300each circuit, including circuit312and circuit314, generally sources a clock that is asynchronous to all other source synchronous clocks.

For debug module320, circuit312provides a source synchronous clock CLK1 and associated source synchronous DATA1. Also, circuit314provides a source synchronous CLKN, and associated source synchronous DATAN. A global clock source provides a global reference clock REFCLK, and global TSC330counts pulses of REFCLK to form a global time stamp including a certain number of least significant bits (N LSBs). REFCLK is lower in frequency than CLK1 or CLKN by a ratio of 1:2 or less.

For functional block340, granularity counter342counts pulses of CLK1 to provide a granularity count to the SS_CLKCnt field of the selected record in partition362. Also, SYNC latch344synchronizes REFCLK with CLK1 to reset granularity counter342. Since REFCLK is asynchronous to CLK1, SYNC latch344provides a stable glitch-free transfer of REFCLK to the RST input of granularity counter342. During the time period just before SYNC latch344resets granularity counter342, the value in granularity counter342is stored as a portion of a trace record in the SS_CLKCnt location of the selected record of partition362. This trace record portion includes both a coarse, global time stamp and a finer granularity time stamp, to allow better correlation of traces between circuit312and circuit314. SYNC latch346synchronizes the N LSBs of global TSC330with CLK1 to provide a synchronized global time stamp value. Partition362stores this value in location GLOBAL TSC (N LSBs) of the selected record of partition362.

For functional block350, granularity counter352counts pulses of CLKN to provide a granularity count to location SS_CLKCnt of the selected record of partition364. Also, SYNC latch354synchronizes REFCLK with CLKN to reset granularity counter352. Since REFCLK is asynchronous to CLKN, SYNC latch354provides a stable glitch-free transfer of REFCLK to the RST input of granularity counter352. During the time period just before SYNC latch354resets granularity counter352, the value in granularity counter352is stored as a portion of a trace record in the SS_CLKCnt field of the selected trace record of partition364. This field represents the relationship between the CLKN clock frequency and the REFCLK clock frequency. SYNC latch356synchronizes the N LSBs output of global TSC330with CLKN to provide a synchronized global time stamp value. Partition364stores this value in the GLOBAL TSC field of the selected record of the selected record of partition364. Also, trace cache buffer360stores DATA1 synchronous with CLK1 in the DATA field in partition362and DATAN synchronous with CLKN in the DATA field in partition364.

DSM370provides a central location for the control of tracing and debug operations of integrated circuit300. Also, DSM370enables the storing of a source synchronous data stream, filters the rules that define how trace records are stored, starts and stops clocks that synchronize and store trace records, and provides a system debug mode interrupt based on certain results of the trace records.

To begin the debug process, certain registers store and provide TRIGGERS, or a sequence of TRIGGERS, over a bus to DSM370. Also, functional blocks such as CPUs, APUs, GPUs, memory sub-systems, system controllers, and complex peripheral functions, provide discrete TRIGGERS, or a sequence of discrete TRIGGERS, to DSM370. Functional block310provides source synchronous data streams to debug module320that each represent the operation of circuits within functional block310, including circuit312and circuit314. DSM370responds to selected TRIGGERS by providing selected enabling signals that include “DbgWrEn1” and “DbgWrEnN” to trace cache buffer360. Enabled by the selected enabling signals, trace cache buffer360stores the trace records and provides TRACE DATA OUT to system resources, not shown inFIG. 3.

In particular, DSM370provides enable signal DbgWrEn1 to SYNC latch366. SYNC latch366synchronizes DbgWrEn1 to clock signal TCLK. SYNC latch366further enables storing of an associated trace record, for a given rising edge of CLK1, in the selected location of partition362. Partition362includes separate locations for the synchronized global time stamp, the synchronized granularity count, and the synchronized source synchronous data stream, DATA1. The data record includes a corresponding timestamp value (including both a coarse, global time stamp and a finer granularity local time stamp) to provide correlation of the data in each location to a time value. Likewise, SYNC latch368synchronizes DbgWrEnN to TCLK. SYNC latch368further enables storing of an associated trace record, for a given rising edge of CLKN, in the corresponding location of partition364. Partition364includes separate locations for the synchronized global time stamp, the synchronized granularity count, and the synchronized source synchronous data stream, DATAN. The record includes a corresponding timestamp value to provide correlation of the data in each location to a time value.

By storing both a coarse, global time stamp and a fine local time stamp, debug module320allows the correlation of trace records from multiple circuits even though their own clocks have random phase and frequency with respect to each other. In addition, debug module320allows simultaneous storage of multiple trace data streams, which allow more sophisticated debug by storing data from multiple, interrelated functional circuits in response to a single trigger.

FIG. 4illustrates a flow chart of a method400for tracing according to some embodiments. Action box410includes receiving a first source synchronous data stream comprising a first clock signal and first data. Action box412includes receiving a second source synchronous data stream comprising a second clock signal and second data. Action box420includes counting pulses of a reference clock signal to form a global time stamp. Action box430includes counting pulses of the first clock signal to form a first granularity count. In some embodiments, this counting includes resetting the first granularity count in response to transitions of the reference clock signal. Action box432includes counting pulses of the second clock signal to form a second granularity count. In some embodiments, this counting includes resetting the second granularity count in response to transitions of the reference clock signal. Action box440includes storing in a first partition of a trace cache buffer the global time stamp, the first granularity count, and the first data in response to a first enable signal. In some embodiments, this storing includes synchronizing the first enable signal to a third clock signal to provide a synchronized first enable signal, and storing in the first partition of the trace cache buffer the global time stamp, the first granularity count, and the first data in response to the synchronized first enable signal. Action box442includes storing in a second partition of the trace cache buffer the global time stamp, the second granularity count, and the second data in response to a second enable signal. In some embodiments, this storing includes synchronizing the second enable signal to the third clock signal to provide a synchronized second enable signal, and storing in the second partition of the trace cache buffer the global time stamp, the second granularity count, and the second data in response to the synchronized second enable signal.

In some embodiments, method400further includes an action box450including outputting data from a selected one of the first and second partitions of the trace cache buffer, an action box460including latching the global time stamp in response to the first clock signal to provide a first latched global time stamp, and/or an action box470including selectively providing the first and second enable signals in response to a plurality of triggers. Moreover the actions of method400may also be implemented in different orders or in different combinations in various embodiments.

The tracing functions of the integrated circuit ofFIG. 3may be implemented with various combinations of hardware and software, and the software component may be stored in a computer readable storage medium for execution by at least one processor. Moreover the method illustrated inFIG. 4may also be governed by instructions that are stored in a computer readable storage medium and that are executed by at least one processor. Each of the operations shown inFIG. 4may correspond to instructions stored in a non-transitory computer memory or computer readable storage medium. In various embodiments, the non-transitory computer readable storage medium includes a magnetic or optical disk storage device, solid state storage devices such as Flash memory, or other non-volatile memory device or devices. The computer readable instructions stored on the non-transitory computer readable storage medium may be in source code, assembly language code, object code, or other instruction format that is interpreted and/or executable by one or more processors.

Moreover, integrated circuit300may be described or represented by a computer accessible data structure in the form of a database or other data structure which can be read by a program and used, directly or indirectly, to fabricate integrated circuit300. For example, this data structure may be a behavioral-level description or register-transfer level (RTL) description of the hardware functionality in a high level design language (HDL) such as Verilog or VHDL. The description may be read by a synthesis tool which may synthesize the description to produce a netlist comprising a list of gates from a synthesis library. The netlist comprises a set of gates which also represent the functionality of the hardware comprising integrated circuit300. The netlist may then be placed and routed to produce a data set describing geometric shapes to be applied to masks. The masks may then be used in various semiconductor fabrication steps to produce a integrated circuit300. Alternatively, the database on the computer accessible storage medium may be the netlist (with or without the synthesis library) or the data set, as desired, or Graphic Data System (GDS) II data.

While particular embodiments have been described, modifications to these embodiments will be apparent to those skilled in the art. For example, the traced circuits in functional block310can be formed by a variety of elements including a GPU, a CPU core, an APU, a memory sub-system, a system controller (a “north bridge” or a “south bridge”), complex peripheral functions, and so on, and sub-circuits of each of them. Also, in some embodiments, integrated circuit300could include a certain number of functional blocks, where a functional block could include a certain set of GPUs, CPU cores, APUs, memory sub-systems, system controllers, complex peripheral functions, and so on. For example, in one embodiment, functional block310could include a CPU core, an APU, and a Universal Serial Bus (“USB”) controller, and another functional block could include a memory sub-system and a bus arbitration module.

In the illustrated embodiment, functional block310of integrated circuit300provides CLK1 and CLKN to debug module320, and the system provides a REFCLK to debug module320having a frequency of 1:2 or less with respect to the lowest operating frequency of each of CLK1 and CLKN, but the precise ratio used could vary in different embodiments. Also, CLK1 and CLKN could run at faster or slower frequencies with respect to each other, and could be substantially asynchronous to each other.

In the illustrated embodiment, partition362and partition364include three separate fields, namely GLOBAL TSC, SS_CLKCnt, and DATA, but any number of fields could be implemented in any number of ways, and any one of these fields could store other selected data using the higher or lower frequency CLK1 or CLKN clocks.

The illustrated embodiment shows SYNC latch344, SYNC latch346, SYNC latch354, and SYNC latch356, but debug module320could bypass one or more of these synchronization latches depending on a particular relationship between CLK1, CLKN, and REFCLK.

Accordingly, it is intended by the appended claims to cover all modifications of the disclosed embodiments that fall within the scope of the disclosed embodiments.