Method and system for interfacing a plurality of memory devices using an MMC/SD protocol

A method for establishing an interface between a host and a plurality of memory devices of a system that utilizes a Multimedia Card (MMC) or Digital (SD) protocol according to an interleaving scheme. A host sequentially transmits a first sequence of commands and data to a system bus in order to allow a first memory device among the memory devices to perform a first operation. The host then transmits a second sequence of commands and data to the system bus to allow a second memory device among the memory devices to perform a second operation after transmitting the first sequence of commands and data.

CROSS-REFERENCE TO RELATED PATENT APPLICATIONS

This application claims the benefit of Korean Patent Application No. 10-2007-0018905, filed on Feb. 26, 2007, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a system having a plurality of memory devices. More particularly, the present invention relates to a method for establishing an interface between a host and a plurality of memory devices of a system that utilizes a Multimedia Card (MMC) or Secure Digital (SD) protocol according to an interleaving scheme.

2. Discussion of Related Art

With advancements in storage media technology, various types of memory have recently been manufactured as auxiliary storage for portable electronic devices such as mobile phones and digital cameras. Examples of these types of memories include compact flash, Multimedia Cards (MMC), Smart Media Cards (SMC), and Secure Digital (SD) cards. Because these memory devices are small and light, they are suitable as data storage in portable electronics.

Generally, memory devices are coupled to a host (e.g., a computer) via a system bus. The memory devices and the host use a predetermined communication protocol (e.g. MMC or SD) to establish data communication therebetween.FIG. 1is a diagram illustrating a conventional interface system between host10and a plurality of memory devices20-1through20-nthat utilizes a general MMC or SD protocol. Host10is connected to memory devices20-1through20-nvia system bus30and may be individually controlled by host10. The memory devices20-1through20-nand the host10communicate using a predetermined protocol stored in host10. In a system using MMC or SD card specifications, the operating mode of each of the memory devices20-1through20-nmay include a card identification mode and a data transfer mode.

In the card identification mode, host10may request each of the memory devices20-1through20-nto provide a card identification number (CID number). If a memory device card (e.g. first memory device20-1) among the memory devices20-1through20-nsuccessfully responds to the request from host10, host10then allocates a Relative Card Address (RCA) to the first memory device20-1. If the RCA is allocated to first memory device20-1, the first memory device20-1enters the data transfer mode. In the data transfer mode, first memory device20-1may be in various states, such as a stand-by state, a transfer state, a sending data state, a receiving data state, and a programming state.

In general, in a system that utilizes the MMC or SD protocol, only a memory device among the memory devices20-1through20-nthat enters the transfer state performs an operation (e.g., a write operation) in response to operating commands (write commands, etc.) received from host10. For example, the memory devices other than the first memory device20-1are in the stand-by state when first memory device20-1is in a program busy state. That is, host10does not transmit commands or data necessary to perform the write operation to any one of the memory devices other than memory device20-1until the end of the busy time of the write operation performed by first memory device20-1. In addition, if host10checks whether the busy time ends by using a polling method, the process increases the load on host10. Accordingly, there is a need for a method and system for allowing the host to rapidly and efficiently establish an interface with each of the memory devices.

SUMMARY OF THE INVENTION

Exemplary embodiments of the present invention are directed to a method and system for rapidly and efficiently establishing an interface between a host and a plurality of memory devices that use a Multimedia Card (MMC) or Secure Digital (SD) protocol using an interleaving scheme. In an exemplary embodiment, the method transmitting a first sequence including a first selection command to select only a first memory device, a first command for determining a total number of first data blocks to be transmitted, a second command to perform write operation, and a plurality of first data blocks; and transmitting a second sequence including a second selection command to select only a second memory device, the first command for determining a total number of second data blocks to be transmitted, the second command, and a plurality of second data blocks after transmitting the first sequence during a program busy time of the first memory device.

The first and second memory devices are in a disconnected state, a stand-by state, a transfer state, or a data receiving state before the plurality of second data blocks are received, respectively, and the first and second memory devices are in either the data receiving state or the disconnect state until the total number of the first data blocks and the total number of the second data blocks is received from the host after receiving the plurality of second data blocks in response to the first or second selection command, respectively.

DESCRIPTION OF EMBODIMENTS

The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention, however, may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, like numbers refer to like elements throughout. It will be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.

FIG. 2is a block diagram of an interface system200between a host210and a plurality of memory devices220-1through220-n(where n is a natural number) using a Multimedia Card (MMC) or Secure Digital (SD) protocol. Interface system200includes host210connected to system bus30and memory devices220-1through220-nalso connected to system bus30. The interface established between host210and each of the memory devices220-1through220-nvia system bus30is in accordance with a predetermined communications protocol. Memory devices220-1through220-nmay all use the MMC or SD protocol or may be a combination of memory devices that use the MMC or SD protocol. Similarly, system bus30may also utilize the MMC or SD interface protocol.

Host210may be a memory device controller such as an MMC or SD controller that includes application unit212, host driver214, and host controller216. Application unit212may be a user application program such as, for example, an MP3player or electronic memo pad. Host driver214may transmit a command to host controller216such as a read or write operation which is requested by the application program. Host controller216may transmit the command received from host driver214to the memory devices220-1through220-nvia system bus30based on the predetermined communication protocol such as, for example, the MMC or SD protocol.

Host210may be a memory device controller such as an MMC/SD controller that includes application unit212, host driver214, and host controller216. Application unit212may be a user application program such as, for example, an MP3 player or electronic memo pad. Host driver214may transmit a command to host controller216such as a read or write operation which is requested by the application program. Host controller216may transmit the command received from host driver214to the memory devices220-1through220-nvia system bus30based on the predetermined communication protocol such as, for example, the MMC/SD protocol.

Host210sequentially transmits a first sequence of commands and data to system bus30to allow first memory device220-1to perform a first operation. After transmitting the first sequence of the commands and data, the host210sequentially transmits a second sequence of commands and data to system bus30to allow a second memory device220-2to perform a second operation. The first and second operations may be write operations with the first and second sequence of commands having various formats. Host210transmits the second sequence of commands and data to system bus30during a program busy time in which first memory device220-1conducts a programming operation.

FIGS. 3 through 6are timing diagrams where memory devices220-1through220-nare multimedia cards (MMCs) and are initialized by host210to enter the stand-by state before performing the write operation.FIG. 3illustrates a predefined write operation of a system that uses the MMC or SD protocol in accordance with an embodiment of the present invention. The first sequence of the commands and data may be first selection command CMD7#1, first command CMD23, second command CMD25, and first data B1through B4based on first command CMD23. The second sequence of commands and data may be second selection command CMD7#2, first command CMD23, second command CMD25, and second data D1through D4based on first command CMD23. These commands may be defined in relation to a memory card according to particular MMC specifications. For example, CMD7may include a relative address (e.g., address #1) of a selected memory card. Only a memory card among a plurality of memory cards in a stand-by state, which corresponds to the comparative address #1 contained in command CMD7can be switched to a transfer state. In this manner, the first selection command CMD7#1may instruct only the first memory device220-1(e.g., a first multimedia card MMC1) to be selected among the memory devices220-1through220-n. Similarly, second selection command CMD7#2may instruct only the second memory device220-2(e.g., a second multimedia card MMC2) to be selected among the memory devices220-1through220-n.

First command CMD23determines the data size (the total number of data blocks) to be transmitted. Second command CMD25instructs the write operation to be performed on the data, the size of which is determined according to the first command CMD23. In particular, the first multimedia card MMC1(first memory device220-1) is selected in response to the first selection command CMD7#1where only the first multimedia card MMC1is switched from the stand-by state to the transfer state. Since the programming of an MMC is performed in page units, first command CMD23instructs the total number of data blocks to be transmitted based on the capacity of a page buffer included in each of the multimedia cards220-1through220-n. For example, if the page buffer included in the MMC is 2 Kbytes, first command CMD23instructs four 512-byte data blocks, e.g., the first data B1through B4, to be transmitted.

The second command CMD25instructs the write operation to be performed using data B1through B4associated with the predetermined 4 blocks. First multimedia card MMC1is switched from the transfer state to the “receiving data” state in response to first command CMD23and second command CMD25. First multimedia card MMC1temporarily stores a data block (e.g., data B1=512 bytes) received from host210in a page buffer (not shown) or an internal RAM (not shown). The length of time required to temporarily store the data block is referred to as a “buffer busy time.” It is assumed that the starting address of the data block B1is arranged with respect to the starting location of a page of a non-volatile memory core (NAND core) included in first memory device220-1.

The first multimedia card220-1performs programming when the page buffer is filled with received data blocks (e.g., the data B1through B4) or when an address for the write operation is identical to the last address of the page of the non-volatile memory core. The length of time required for the programming operation is referred to as a “programming busy time.” Generally, the programming busy time is longer than the buffer busy time. For example, if the capacity of the page buffer is 2 Kbytes and transmission of the four 512-byte data blocks B1through B4to first multimedia card MMC1(first memory device220-1) via system bus30is completed, then the first multimedia card MMC1executes the programming operation. Thus, the first multimedia card MMC1is in a programming state. During the programming busy time in which first multimedia card MMC1(first memory device220-1) performs the programming operation, host210outputs the second sequence of commands and data to system bus30in order to perform a write operation on the second multimedia card MMC2(second memory device220-2). The second multimedia card MMC2(second memory device220-2) is switched from the stand-by state to the transfer state in response to the second selection command CMD7#2. The first multimedia card MMC1(first memory device220-1) is switched from the programming state to a disconnected state in response to the second selection command CMD7#2. When the first multimedia card MMC1completes the write operation, it returns to the stand-by state. In this manner, host210of system200is capable of improving overall system performance by overlapping the program busy time of the first multimedia card MMC1(first memory device220-1) with a time required to transmit the second sequence of commands and data in order to perform a write operation on the second multimedia card MMC2(second memory device220-2) by using an interleaving scheme. Host210is capable of recognizing a plurality of physical multimedia cards (physical memory devices) as one logical device using the above interleaving scheme.

As shown inFIG. 3, host210must use each of the CMD7#1, CMD23, and CMD25commands three times in order to instruct the predefined write operation to be performed on first multimedia card MMC1(first memory device220-1) having a 2 Kbyte page buffer by using a total of 12 data blocks.FIG. 4is a second timing diagram of an open-ended write operation of a system that uses the MMC or SD protocol. In the open-ended write operation, host210ofFIG. 2utilizes CMD25and CMD12as write commands. The first sequence of commands and data may include a first selection command CMD7#1, a command CMD25that instructs the write operation to be performed, first data B1through B4transmitted from host210(shown inFIG. 2) and a stop command CMD12that discontinues transmission of the first data B1through B4. The second sequence of commands and data may include a second selection command CMD7#2, command CMD25which instructs the write operation to be performed, second data D1through D4transmitted from host210, and a stop command CMD12that discontinues transmission of second data D1through D4.

In the open ended write operation, command CMD25instructs the write operation to be performed using data blocks transmitted from host210until receipt of stop command CMD12which discontinues the transmission of data blocks from host210. Since four data blocks are transmitted after command CMD25and the stop command CMD12is transmitted from host210to system bus30, the write operation can be performed as described above with reference toFIG. 3. Host210must use each of the commands CMD7#1, CMD25, and CMD12three times to instruct the open-ended write operation to be performed on the first multimedia card MMC1(first memory device220-1) having a 2 Kbyte page buffer by using a total of 12 data blocks (e.g., data blocks B1through B12).

FIG. 5is a third timing diagram of a predefined write operation for a system that uses the MMC or SD protocol. The first sequence of commands and data may include first selection command CMD7#1, first command CMD23for determining the size of the data to be transmitted for the predefined write operation, second command CMD25, and first data B1through B4transmitted from host210. The second sequence of commands and data may include second selection command CMD7#2, first command CMD23, second command CMD25, and second data D1through D4transmitted from host210. For example, first command CMD23included in the first sequence of commands and data may instruct a total of 12 data blocks (e.g., data blocks B1through B12) to be transmitted to first multimedia card MMC1(first memory device220-1) having a 2 Kbytes page buffer where one data block is 512bytes long. First multimedia card MMC1(first memory device220-1) is switched from the stand-by state to the transfer state in response to first selection command CMD7#1. First multimedia card MMC1is then switched from the transfer state to the “receiving data” state in response to first command CMD23and second command CMD25. Host210transmits the four 512-byte data B1through B4to first memory card220-1and then transmits the second selection command CMD7#2 to system bus30.

First multimedia card MMC1(first memory device220-1) is switched from the “receiving data” state to the disconnected state and the second multimedia card MMC2(second memory device220-2) is switched from the stand-by state to the transfer state in response to the second selection command CMD7#2 output to system30. Second multimedia card MMC2(second memory device220-2) is switched from the transfer state to the “receiving data” state in response to the first command CMD23and second command CMD25included in the second sequence of commands and data. Host210may transmit first selection command CMD7#1 to system bus30after transmission of the second data D1through D4. In this case, first multimedia card MMC1(first memory device220-1) is switched from the disconnected state to the “receiving data” state. The second multimedia card MMC2(second memory device220-2) is switched from the “receiving data” state to the disconnected state in response to the first selection command CMD7#1 transmitted to system bus30after transmission of the second data D1through D4. In this manner, the first multimedia card MMC1and the second multimedia card MMC2are in either the “receiving data” state or the disconnected state until the total number of data blocks (e.g., a total of 12 data blocks) is received from host210associated with performance of the predefined write operation (as differentiated from general MMC or SD card specifications). For example, first multimedia card MMC1(first memory device220-1) is switched from the “receiving data” state to the disconnected state and vice versa until receiving all the total of the12data blocks (data B1through B12) from host210in response to the first or second selection commands CMD7#1 or CMD7#2.

FIG. 5illustrates another timing diagram of a predefined write operation of a system that uses the MMC or SD protocol. Host210first uses each of the commands CMD7#1, CMD23, and CMD25only once and then uses command CMD7#1twice in order to instruct the predefined write operation to be performed on the first multimedia card MMC1(first memory device220-1) having the 2 Kbyte page buffer by using a total of 12 blocks (data B1through B12). Thus, the total number of commands that host210uses in order to perform the predefined write operation illustrated inFIG. 5is less than the number of commands required to perform the predefined write operation illustrated inFIG. 3.

FIG. 6is a fourth timing diagram of an open-ended write operation of a system that uses the MMC or SD protocol. The first sequence of commands and data may include first selection command CMD7#1, first command CMD25that instructs the open-ended write operation to be performed, and first data B1through B4transmitted from host210. The second sequence of commands and data may include second selection command CMD7#2, first command CMD25, and second data D1through D4transmitted from host210. Host210transmits first selection command CMD7#1 to system bus30after transmitting the second data D1through D4. A state change associated with first multimedia card MMC1(first memory device220-1) or second multimedia card MMC2(second memory device220-2) occurs as described above with reference toFIG. 5which is different from the general MMC or SD card specifications. In order to perform the open-ended write operation illustrated inFIG. 6, host210first uses both the first selection command CMD7#1 and the second command CMD25associated with the first multimedia card MMC1(first memory device220-1) and the second multimedia card MMC2(second memory device220-2). After transmitting the second data D1through D4, host210alternately uses the first selection command CMD7#1 and second selection command CMD7#2 to transmit data blocks B5through B12or D5through D12to the first or second memory device220-1or220-2. Host210transmits a stop command CMD12to system bus30after transmitting the last of the data blocks B9through B12or D9through D12from the transmitted12data blocks B1through B12or D1through D12.

FIG. 7is a state diagram700of memory devices that use the MMC or SD protocol according to the timing diagrams illustrated inFIGS. 5 and 6where command CMD7may be the first or second selection command CMD7#1 or CMD7#2. First and second blocks710and720indicated by a dotted line are added to and a dotted arrow730is canceled from the state diagram of memory devices using an MMC or SD protocol according to the general MMC or SD card specifications. That is, first and second multimedia cards MMC1or MMC2are either in the “receiving data” state or the disconnected state until the total number of data blocks (e.g., a total of 12data blocks) associated with the write operation illustrated inFIGS. 5 and 6are received from host210. Host210may perform a read operation by alternately selecting the first and second multimedia cards MMC1and MMC2to read the sequence of data blocks transmitted for the write operation illustrated inFIG. 5or6. Unlike the general MMC or SD card specifications, the first or second multimedia cards MMC1or MMC2are not switched from the sending data state to the stand-by state in response to selection command CMD7(CMD7#1 or CMD7#2). Reference arrow730ofFIG. 7is canceled from the state diagram of memory devices using the MMC or SD protocol according to the general MMC or SD card specifications. In addition, unlike the general MMC or SD card specifications, first multimedia card MMC1is in the “sending data” state and second multimedia card MMC2is in the disconnected state in response to selection command CMD7(CMD7#1 or CMD7#2).

FIG. 8is a block diagram of an interface system800disposed between host810and a plurality of memory devices utilizing the MMC or SD protocol. For convenience of explanation,FIG. 8illustrates only two memory devices830and840among the plurality of the memory devices and utilizes the MMC or SD protocol. System800includes host810, system bus820, first transmission line822, second transmission line824, first memory device830, and second memory device840. Host810includes host driver812and host controller814. Host driver812and host controller814operate similarly to host driver214and host controller216shown inFIG. 2. System buses820include clock bus CLK, data bus DATA, and command bus CMD. First memory device830includes first controller832and first memory core834. Second memory device840includes second controller842and second memory core844. First and second memory devices830and840are connected to host810via system bus820and receives clock signal CLK, data Data, and command signal CMD from host810via system bus820. First controller832enables or disables in response to first enable signal CEO1received from host810via first transmission line822. First controller832provides first memory core834with clock signal CLK, data Data, and command signal CMD received from host810in response to first enable signal CEO1. The second controller842may operate the same as first controller832.

First controller832includes a first input/output (I/O) control logic circuit (not shown) that controls clock signal CLK, data Data, and command signal CMD for transmission to first memory core834in response to first enable signal CEO1. First I/O control logic circuit may be separate from first memory device830. Similarly, second controller842may include a second I/O control logic circuit having the same operation of the first I/O control logic circuit and may be separate from second memory device840.

FIG. 9is another timing diagram of a predefined write operation of the interface system800illustrated inFIG. 8. Host810transmits a first sequence of commands (not shown) to system bus820in order to switch both the first memory device830and the second memory device840from the stand-by state to the transfer state. For example, the first sequence of the commands may include a first enable signal CEO1and the first selection command CMD7#1at a first level (high), and a second enable signal CEO2and the second selection command CMD7#2also at the first level. Alternatively, first enable signal CEO1may be at a high level and second enable signal CEO2may be at a low level.

In order to perform the predefined write operation, both the first and second memory devices830and840are in the transfer state. The second sequence of commands and data may include first enable command CEO1, first command CMD23, second command CMD25, and first data (data blocks B1through B4). First enable command CEO1is transmitted to first memory device830via first transmission line822to only enable first memory device830. First command CMD23may be a command for determining the size of the data to be transmitted when the write operation is performed and second command CMD25may initiate the write operation to be performed. The third sequence of commands and data may be a second enable command CEO2, first command CMD23, second command CMD25, and second data (data blocks D1through D4). The system800illustrated inFIG. 8uses the first enable signal CEO1or second enable signal CEO2instead of the first selection command CMD7#1or second selection command CMD7#2illustrated inFIG. 5.

After transmitting the second data blocks D1through D4, host810transmits the other data blocks B5through B12or D5through D12to first memory device830or the second memory device840by alternately using the first enable signal CEO1and the second enable signal CEO2. Accordingly, the number of times that command CMD7is utilized to perform the write operation is reduced and all the memory devices of system800are in the transfer state. Thus, there is no need to determine whether a command error occurs.

FIG. 10is another timing diagram of an open-ended write operation of system800illustrated inFIG. 8. A first enable signal CEO1or second enable signal CEO2is used in place of first selection command CMD7#1or second selection command CMD7#2. As inFIG. 9, it is assumed that both the first memory device830and second memory device840are in the transfer state to perform the open-ended write operation illustrated inFIG. 10. The second sequence of commands and data may include the first enable command CEO1, first data (data blocks B1through B4), and first command CMD25that instructs the open-ended write operation to be performed. The third sequence of commands and data may include second enable command CEO2, second data (data blocks D1through D4), and first command CMD25that instructs the write operation to be performed. Host810transmits data blocks B5through B12or D5through D12to first memory device830or second memory device840by alternately using the first enable signal CEO1and the second enable signal CEO2.

In an erase operation, the interface between a host and a plurality of memory devices is established by using the interleaving scheme as described above with reference toFIGS. 3 and 4. For example, during a busy time in which first memory device220-1among the memory devices220-1through220-nis performing the erasing operation, host210transmits to the system bus30a sequence of predetermined commands necessary for the second memory device220-2to perform the erasing operation. The sequence of the predetermined commands, such as commands CMD7, CMD35, CMD36and CMD38are defined in the MMC or SD card specifications.

As described above, in a method and system for establishing an interface between a host and a plurality of semiconductor devices that use an MMC or SD protocol according to the present invention, the interface may be rapidly performed using the interleaving scheme. In addition, a reduced number of commands are necessary to perform the write operation.

Although the present invention has been described in connection with the embodiment of the present invention illustrated in the accompanying drawings, it is not limited thereto. It will be apparent to those skilled in the art that various substitutions, modifications and changes may be made thereto without departing from the scope and spirit of the invention. For example, the present invention may be embodied as computer readable code in a computer readable medium where the computer readable medium may be any recording medium capable of storing data and read by a computer system.