Transmitting apparatus with source termination

In one embodiment, an apparatus for transmitting a signal with an improved termination is disclosed. The apparatus includes a driver to generate a differential mode signal superimposed on a common mode signal at a differential driver output of the driver. The differential driver output includes a first driver output and a second driver output. The apparatus also includes a termination circuit coupled between the first driver output and the second driver output. The termination circuit includes a capacitor connected to a node. The termination circuit also includes a first resistor and a first inductive element coupled in series between the first driver output and the node. In addition, the termination circuit includes a second resistor and a second inductive element coupled in series between the second driver output and the node.

BACKGROUND

1. Field of the Disclosure

This disclosure pertains in general to data communications, and more specifically to signal integrity on a chip to chip communication.

2. Description of the Related Art

Video and audio data are typically transferred from one device to another across using communication links. In an advanced protocol such as the high definition multimedia interface (HDMI) or the mobile high definition link (MHL), one device may communicate with another using a common mode signal superimposed on a differential mode signal. The common mode signal may generate Electromagnetic Interference (EMI). To suppress the EMI and properly terminate the output of a transmitting device, a common mode choke may be employed between the two devices. However, the common mode choke may degrade the signal quality from the transmitting device.

SUMMARY

Embodiments of the present disclosure relate to a transmitting apparatus with an improved source termination for a chip to chip communication in a manner that properly terminates an output of the transmitter, maintains the signal quality, and reduces EMI.

In one embodiment, an apparatus for transmitting a signal with an improved termination is disclosed. The apparatus includes a driver to generate a differential mode signal superimposed on a common mode signal at a differential driver output of the driver. The differential driver output includes a first driver output and a second driver output. The apparatus also includes a termination circuit coupled between the first driver output and the second driver output. The termination circuit includes a capacitor connected to a node. The termination circuit also includes a first resistor and a first inductive element coupled in series between the first driver output and the node. In addition, the termination circuit includes a second resistor and a second inductive element coupled in series between the second driver output and the node. The first inductive element and second inductive element causes peaking in the differential mode signal at the differential driver output.

In one embodiment, the apparatus further includes a first switch coupled in series with the first resistor and the first inductive element between the first driver output and the node. The apparatus also includes a second switch coupled in series with the second resistor and the second inductive element between the second driver output and the node.

In one embodiment, the first switch and second switch are closed when the apparatus is communicating through a first communication protocol. The first switch and the second switch are open when the apparatus is communicating through a second communication protocol.

DETAILED DESCRIPTION

The Figures (FIG.) and the following description relate to various embodiments by way of illustration only. It should be noted that from the following discussion, alternative embodiments of the structures and methods disclosed herein will be readily recognized as viable alternatives that may be employed without departing from the principles discussed herein. Reference will now be made in detail to several embodiments, examples of which are illustrated in the accompanying figures. It is noted that wherever practicable similar or like reference numbers may be used in the figures and may indicate similar or like functionality.

As used herein, the term directly connected means that two components are directly connected to each other without any intervening components. The term coupled means that two components may be directly connected to each other or that intervening components may be located between two components.

Embodiments of the present disclosure include a transmitter with a termination circuit that does not degrade signal quality. The transmitter communicates with a receiver through a differential signal including a differential mode signal and a common mode signal. The termination circuit ensures signal integrity of signals produced from the transmitter in a chip to chip communication. In addition, the termination circuit enables a proper termination to reduce unwanted interference from one device to another.

FIG. 1is a high-level block diagram of a system100for data communications, according to one embodiment. The system100includes a source device110communicating with a sink device115through one or more communication media (e.g., one or more interface cables120,150,180). Source device110transmits multimedia data streams (e.g., audio/video streams) to the sink device115and also exchanges control data with the sink device115through the interface cables120,150,180. In one embodiment, source device110and/or sink device115may be repeater devices.

Source device110includes physical communication ports112,142,172for coupling to the interface cables120,150,180. Sink device115also includes physical communication ports117,147,177for coupling to the interface cables120,150,180. Signals exchanged between the source device110and the sink device115across the interface cables120,150,180pass through the physical communication ports.

Source device110and sink device115exchange data using various protocols. In one embodiment, interface cable150represents a Mobile High-Definition Link (MHL) cable. The MHL cable150supports differential signals transmitted via data0+ line151, data0− line152, data1+ line153, data1− line154, data2+ line155and data2− line156. In some embodiments of MHL, there may only be a single pair of differential data lines (e.g.,151and152). Embedded common mode clocks are transmitted through the differential data lines. The MHL cable150may further include a control bus (CBUS)159, power160and ground161. The CBUS159carries control information such as discovery data, configuration data and remote control commands.

In one embodiment, interface cable120represents a High Definition Multimedia Interface (HDMI) cable. The HDMI cable120supports differential signals transmitted via data0+ line121, data0− line122, data1+ line123, data1− line124, data2+ line125, and data2− line126. The HDMI cable120may further include differential clock lines clock+127and clock−128; Consumer Electronics Control (CEC) control bus129; Display Data Channel (DDC) bus130; power131, ground132; hot plug detect133; and four shield lines134for the differential signals. In some embodiments, the sink device115may utilize the CEC control bus129for the transmission of closed loop feedback control data to source device110.

In one embodiment, a representation of the source device110, the sink device115, or components within the source device110or sink device115may be stored as data in a non-transitory computer-readable medium (e.g. hard disk drive, flash drive, optical drive). These representations may be behavioral level, register transfer level, logic component level, transistor level and layout geometry-level descriptions.

FIG. 2Ais a block diagram of a source device110A, according to one embodiment. The source device110A includes a transmitter integrated circuit (TXIC)230A, a termination circuit215A, a common mode choke circuit220and a port250. A positive output pin Vop1of the TXIC230A is coupled to a positive input pin Vip2of the common mode choke circuit220via a connection212. In addition, a negative output pin Von1of the TXIC230A is coupled to the negative input pin Vin2of the common mode choke circuit220via a connection214. The termination circuit215A is coupled between the positive output pin Vop1and the negative output pin Von1of the TXIC230A. In addition, a positive output pin Vop2of the common mode choke circuit220is coupled to a positive input pin Vip3of the port250via a connection222. Moreover, a negative output pin Von2of the common mode choke circuit220is coupled to a negative input pin Vin3of the port250via a connection224. Together these circuits form a source device110A that complies with EMI regulations and maintains good signal quality.

The TXIC230A includes a transmitter driver (TX driver)210that drives a differential signal onto the driver outputs Vop and Von that includes a differential mode signal and a common mode signal. The differential mode signal typically operates at a higher frequency than the common mode signal. In one embodiment that uses MHL, the differential mode signal operates at 3 GHz and represents data for a multimedia stream. The common mode signal is a clock that operates at 75 MHz. In another embodiment that uses HDMI, the differential mode signal can represent one data stream (e.g. Ethernet data) while the common mode signal represents another data stream (e.g. audio data). In one embodiment, the TX driver210includes a differential driver to generate the differential mode signal and a common mode driver to generate the common mode signal. A positive output pin Vop TX of the TX driver210is coupled to the positive output pin Vop1of the TXIC230A to transmit a positive signal of the differential signal. Similarly, a negative output pin Von TX of the TX driver210is coupled to the negative output pin Von1of the TXIC230A to transmit a negative signal of the differential signal.

As illustrated inFIG. 2A, the common mode choke circuit220is coupled between the differential outputs Vop1and Von1of the TX driver210. The common mode choke circuit220suppresses common mode noise generated from the TXIC230A. In one embodiment, the common mode choke circuit220is formed with a transformer. The transformer may be configured such that magnetic fluxes generated from the common mode signal by the TX driver210are added together. Hence, the common mode choke circuit220acts as an inductor to suppress the common mode noise at a high frequency and passes the common mode signal at a low frequency. The transformer is also configured such that magnetic fluxes generated from the differential signal by the TX driver210are cancelled with each other. Hence, the common mode choke circuit220passes the differential mode signal without substantial loss.

In one embodiment, the port250provides a physical interface to mate with an interface cable120as described herein with respect toFIG. 1. For a HDMI protocol, the port250may be the port112ofFIG. 1. For a MHL protocol, the port250may be the port142ofFIG. 1.

In one embodiment, an electrostatic discharge (ESD) protection circuit (not shown) may be implemented between the common mode choke circuit220and the port250to alleviate a sudden flow of electricity between the TXIC230A and the port250.

The termination circuit215A enables a proper termination to guarantee adequate signal quality and reduce the EMI from the TXIC230A. In one embodiment, the termination circuit215A includes passive components such as a first resistor R1, a second resistor R2, a first inductor L1, a second inductor L2and a capacitor C1. In the source device110A, the passive components are implemented external to the TXIC230A on a printed circuit board (PCB).

In one embodiment, the first resistor R1and the first inductor L1are coupled in series between the positive output pin Vop1of the TXIC230A and a common node Ncm. For example, one end of the first resistor R1is coupled to the positive output pin Vop1, and another end of the first resistor R1is coupled to one end of the first inductor L1. Additionally, another end of the first inductor L1is coupled to the common node Ncm. Alternatively, the first resistor R1and the inductor L1may be swapped. In addition, the second resistor R2and the second inductor L2are coupled in series between the negative output Von1of the TXIC230A and the common node Ncm. The configuration of the second resistor R2, the second inductor L2, and the negative output pin Von1are substantially similar to the configuration of the first resistor R1, the first inductor L1, and the positive output pin Vop1. Additionally, a capacitor C1is coupled between the common node Ncm and ground232to suppress a common mode peaking in the common mode signal.

In this configuration, the first resistor R1and the second resistor R2provide a termination impedance to the common mode signal. The capacitor C1removes an unwanted peaking of the common mode signal generated due to the common mode choke circuit220as described in details herein with respect toFIG. 4A.

Referring toFIG. 2B, illustrated is an impedance plot of a termination circuit for the common mode signal versus frequency, according to one embodiment. As illustrated inFIG. 2B, the common mode impedance294of the termination circuit215A becomes Z2(e.g., approximately 50 Ohm) at the common mode operating frequency fcm, because both the inductive elements L1and L2become substantially shorted. The common mode impedance294increases as the frequency increases, because the impedance of each of the inductive elements L1and L2increases. For example, values for the inductive elements L1and L2can be chosen such that at three times the frequency of the common mode operating frequency fcm, the common mode impedance294becomes Z3(e.g., approximately 100 Ohm). The value for the capacitor C1is chosen such that the capacitor C1does not introduce a significant impedance at the common mode operating frequency fcm.

In one embodiment, the value for capacitor C1can be selected to obtain a common mode impedance294with the following equation:

In equation 1, impedance of 0.1 Ohm is targeted to ensure that the common node Ncm is substantially close to ground at a common mode operating frequency fcm. As the capacitance of the capacitor C1becomes larger, the common node Ncm becomes closer to ground.

Without inductors L1and L2, the resistors R1, R2and capacitor C1would have the negative side effect of reducing the size of the data eye for the differential mode signal. To address this problem, the first inductor L1and the second inductor L2are placed in series with the resistors R1and R2. The first inductor L1and second inductor L2present high impedance to the differential mode signal and generate a differential mode peaking, as described in details with respect toFIG. 4B. For the differential mode signal, the common node Ncm becomes virtual ground, therefore the capacitor C1becomes ineffective.

The inductive values for L1and L2can be selected to obtain the common mode impedance294with the following equation:

In equation 2, each of the resistance of the resistors R1and R2is targeted for the impedance of each of the inductive elements L1and L2to ensure that the inductive elements L1and L2do not increase the common mode impedance294at the third harmonic of the common mode operating frequency fcm. The inductance of each of the inductive elements L1and L2are chosen such that the inductive elements L1and L2add substantially no impedance to the common mode impedance294at the third harmonic of the common mode operating frequency fcm. Moreover, the inductance of each of the inductive elements L1and L2are chosen such that the inductive elements L1and L2add a large impedance to the differential impedance292at the differential mode operating frequency Fdm.

As illustrated inFIG. 2C, the differential impedance292of the termination circuit215A becomes Z4(e.g., 1500 Ohm) at the differential mode operating frequency Fdm, because each of the inductive elements L1and L2contributes large impedance. In this configuration, the termination circuit215A presents high impedance to a differential mode signal to improve an eye opening (i.e., signal quality) at the differential mode operating frequency Fdm, as described herein in detail with respect toFIG. 4B. In one embodiment, R1is 50 Ohm, R2is 50 Ohm, L1is 20 nH, L2is 20 nH, and C1is 100 nF

FIG. 2Dillustrates an insertion loss S21plot of the differential mode signal in the termination circuit215A, according to one embodiment. The plot inFIG. 2Dincludes a channel loss plot296, a termination circuit loss plot298, and a target insertion loss plot299. Together, these plots illustrate one example aspect of determining values of the inductive elements L1and L2in the termination circuit215A.

In one approach, the values of the inductive elements L1and L2are determined such that the target insertion loss plot299retains approximately a flat region below a frequency fx. The frequency fx is determined by when the insertion loss S21of a channel without the termination circuit215A is close to S1. The channel loss plot296approximates a resistive loss due to the connections212,222,214and224to the port250. The insertion loss S21of the channel drops in a substantially linear manner as depicted by the channel loss plot296. For example, if the channel loss plot296at the differential mode operating frequency Fdm is −10 dB, the frequency fx (e.g., ˜600 MHz) can be determined such that the channel loss plot296is approximately −1.78 dB.

An insertion loss S21of the termination circuit215A improves as illustrated in the termination circuit loss plot298, because the termination circuit215A includes the inductive elements L1and L2, and the resistors R1and R2. In one aspect, the values of the resistors R1and R2are predetermined (e.g., 50 Ohm each). Therefore, the values of the inductive elements L1and L2can be chosen such that the insertion loss S21of the termination circuit loss plot298is close to S1at the frequency fx.

The target insertion loss plot299is an insertion loss S21of the channel including the termination circuit215A. Therefore, the channel loss plot296is combined with the termination circuit loss plot298to produce the target insertion loss plot299as inFIG. 2D. Hence, the target insertion loss plot299becomes substantially flat below the frequency fx. Below the frequency fx, the summation of the channel loss plot296and the termination circuit loss plot298becomes S2. For example, S2is substantially equal to −3.52 dB, or between −3 dB and −4 dB. In addition, the target insertion loss plot299tracks the channel loss plot296above the frequency fx, because the channel loss dominates the total loss in this region.

In one approach, assuming the resistance of each of the resistors R1and R2is 50 ohm, the inductance of each of the inductive elements L1and L2can be determined using the following equation:

L=14×π×fx⁢x2⁡(150)2-(100)21-x2,(eq3)
where x is an insertion loss S21of the termination circuit215A at the frequency fx. For example, an insertion loss x corresponding to −1.78 dB at the frequency fx of 600 MHz leads to a L value of approximately 16.63 nH.

Turning toFIG. 3, illustrated is a positive signal310A and a negative signal310B of the differential signal (collectively herein referred to as a differential signal310) transmitted from the positive output pin Vop1and the negative output Von1of the TXIC230A respectively. As illustrated, the differential signal310includes a common mode signal330superimposed on a differential mode positive signal320A and a differential mode negative signal320B (generally herein referred to as a differential mode signal320). The common mode signal330is obtained by averaging the positive signal310A and the negative signal310B of the differential signal310. The differential mode signal320is obtained by comparing the positive signal310A to the negative signal310B. As illustrated inFIG. 3, a frequency of the differential mode signal320is higher than a frequency of the common mode signal330.

FIG. 4Ais an illustration of the common mode signal330with various termination configurations at the output pins Vop1and Von1of the TXIC230A and the output pins Vop3and Von3of the port250. In case a capacitor C1is omitted from the termination circuit215A, a common mode signal410at the output pins Vop1and Von1of the TXIC230A includes a peaking415, because the common mode choke circuit220fails to respond to a very sharp transition (e.g., 1 ns). The peaking415of the common mode signal410introduces an undesired EMI. A common mode signal420at the output pins Vop3and Von3of the port250is substantially similar to the common mode signal410at the output pins Vop1and Von1of the TXIC230A, because the common mode signal410operates at a relatively low frequency (e.g., 75 MHz).

Implementing the capacitor C1alleviates the peaking415in a common mode signal430at the output pins Vop1and Von1of the TXIC230A. Hence, the common mode signal430at the output pins Vop1and Von1of the TXIC230A becomes substantially similar to a square wave. Similarly, the peaking425in the common mode signal440at the output pins Vop3and Von3of the port250is alleviated.

FIG. 4Bis an illustration of the differential mode signal320with various termination configurations at the output pins Vop1and Von1of the TXIC230A and the output pins Vop3and Von3of the port250. As illustrated inFIG. 4B, a differential mode signal450at the output pins Vop1and Von1of the TXIC230A is substantially close to a square wave. However, without the first inductor L1and the second inductor L2from the termination circuit215A, the differential mode signal460at the output pins Vop3and Von3of the port250is damped, because the differential mode signal450operates at a high frequency (e.g., 3 GHz). As a result, parasitic capacitances associated with the common mode choke circuit220, port250and connections212,222,214and224become significant and slow the response at the output pins Vop3and Von3of the port250. Damping of the differential mode signal460reduces the data eye of the differential mode signal at the sink device115.

Implementing the first inductor L1and the second inductor L2introduces a peaking475in a differential mode signal470at the output pins Vop1and Von1of the TXIC230A. The peaking475causes the rising edge of the differential mode signal470to temporarily rise past a target differential voltage (for logic value 1) of the differential mode signal470before settling at the target differential voltage. The peaking475causes the falling edge of the differential mode signal470to temporarily fall below a target differential voltage (for logic value 0) of the differential mode signal470before settling at the target differential voltage. The peaking475in the differential mode signal470does not cause EMI issues, because the magnetic field caused by the peaking475is cancelled out. The differential mode signal480at the output pins Vop3and Von3of the port250substantially similar to a square wave. The change in shape of the differential mode signal480is due to parasitic capacitances within the source device110A.

Referring toFIG. 5, illustrated is a block diagram of the source device110B with a TXIC230B including a first switch SW1and a second switch SW2for enabling the termination, according to one embodiment. The source device110B is configured similar to the source device110A ofFIG. 2A. Also, the termination circuit215B of the source device110B is similar to the termination circuit215A of the source device110A. The differences include the first switch SW1and the second switch SW2being embedded in the TXIC230B. The first switch SW1and the second switch SW2enable a connection between the differential output pins Vop1and Vop2, and the termination circuit215B.

In the TXIC230B, the first switch SW1, the first resistor R1and the first inductor L1are coupled in series between the positive output pin Vop1of the TXIC230B and the common node Ncm. In one embodiment, one end of the first switch SW1is coupled in series to the first resistor R1and the first inductor L1through a first termination pin Vtp of the TXIC230B. Additionally, another end of the first switch SW1is coupled to the positive output pin Vop1of the TXIC230B. Additionally, the second switch SW2, the second resistor R2and the second inductor L2are coupled in series between the negative output pin Von1of the TXIC230B and the common node Ncm. In addition, one end of the second switch SW2is coupled to the second resistor R2and the second inductor L2through a second termination pin Vtn of the TXIC230B. Moreover, another end of the second switch SW2is coupled to the negative output pin Von1of the TXIC230B.

FIG. 6is an illustration of a block diagram of a source device110C with a TXIC230C including the first switch SW1, the second switch SW2, the first resistor R1and the second resistor R2, according to one embodiment. The source device110C is configured similar to the source device110B ofFIG. 5. The differences include the first resistor R1and the second resistor R2being embedded in the TXIC230C. As a result, off-chip components of the termination circuit215C include the first inductor L1, the second inductor L2and the capacitor C1. The source device110C saves area used for implementing the first resistor R1and the second resistor R2off-chip.

In the TXIC230C, the first switch SW1and the first resistor R1are coupled in series to the first inductor L1through a first termination pin Vtp of the TXIC230C. For example, one end of the first switch SW1is coupled to a positive output pin Vop1and another end of the first switch SW1is coupled to one end of the first resistor R1. Additionally, another end of the first resistor R1is coupled to the first termination pin Vtp of the TXIC230C. Alternatively, the first switch SW1and the first resistor R1may be swapped. In addition, the second switch SW2and the second resistor R2are coupled in series to the second inductor L2through a second termination pin Vtn of the TXIC230C. The configuration of the second switch SW2, the second resistor R2, the negative output pin Von1and the second termination pin Vtn of the TXIC230C are similar to the configuration of the first switch SW1, the first resistor R1, the positive output pin Vop1and the first termination pin Vtp of the TXIC230C.

Turning toFIG. 7, illustrated is a block diagram of a source device110D with a TXIC230D including the first switch SW1, the second switch SW2, the first resistor R1, the second resistor R2, the first inductor L1and the second inductor L2, according to one embodiment. The source device110D is configured similar to the source device110C ofFIG. 6. The differences include the first inductor L1and the second inductor L2being embedded in the TXIC230D. As a result, an off-chip component of the termination circuit215D includes the capacitor C1. The source device110D saves area used for implementing the first inductor L1and the second inductor L2off-chip. The first inductor L1and the second inductor L2may be implemented with on-chip spiral inductors or bonding wires that are lengthened until they have a substantial amount of inductance.

In the TXIC230D, the first switch SW1, the first resistor R1, and the first inductor L1are coupled in series to the common node Ncm through a termination pin Vt of the TXIC230D. For example, one end of the first switch SW1is coupled to a positive output pin Vop1and another end of the first switch SW1is coupled to one end of the first resistor R1. Additionally, another end of the first resistor R1is couple to one end of an inductor L1, and another end of the inductor L1is coupled to the termination pin Vt of the TXIC230D. Alternatively, the first switch SW1, the first resistor R1, and the first inductor L1may be swapped. In addition, the second switch SW2, the second resistor R2, and the second inductor L2are coupled in series to the common node Ncm through the termination pin Vp of the TXIC230D. The configuration of the second switch SW2, the second resistor R2, the second inductor L2, and the negative output pin Von1of the TXIC230D are similar to the configuration of the first switch SW1, the first resistor R1, the first inductor L1, and the positive output pin Vop1of the TXIC230D.

FIG. 8is an illustration of a block diagram of a source device110E with a TXIC230E including all passive components of the termination circuit215E, according to one embodiment. The source device110E is configured similar to the source device110D ofFIG. 7. The differences include the capacitor C1embedded in the TXIC230E. Hence, the termination pin Vt of TXIC230D ofFIG. 7is omitted. The source device110E saves area used for implementing the capacitor C1off-chip, and additional termination pins employed in the TXIC230B-D.

FIG. 9is an illustration of a source device110F, according to one embodiment. The source device110F illustrated inFIG. 9is a detailed implementation of the source device110D ofFIG. 7that includes connections to a transmitter die940and a package of the TXIC230F. The transmitter die940is a silicon wafer with core circuitries implemented on the transmitter die940. The connections between the transmitter die940and the package of the TXIC230F may be implemented with bonding wires.

The transmitter die940includes the TX driver210implemented on any fabrication process or technologies. The transmitter die940also includes the first switch SW1, the second switch SW2, the first resistor R1and the second resistor R2. The positive output pin Vop TX of the TX driver210is coupled to a bond pad911, and the negative output pin Von TX of the TX driver210is coupled to a bond pad917. The transmitter die940also includes the first switch SW1and the first resistor R1coupled to the positive output pin Vop TX of the TX driver210. Additionally, the transmitter die940includes the second switch SW2and the second resistor R2coupled to the negative output pin Von TX of the TX driver210.

A bond pad913allows the first switch SW1and the first resistor R1to be coupled to a termination pin Vt of the TXIC230F through a lengthened bonding wire991serving as the first inductor L1. In addition, a bond pad915allows the second switch SW2and the second resistor R2to be coupled to the termination pin Vt of the TXIC230F through a lengthened bonding wire993serving as the second inductor L2. The bonding wires991and993are lengthened such that they have a substantial amount of inductance (e.g., >1.5 nH) in accordance with the equation for inductance described above.

Similarly, a bond pad911allows the positive output pin Vop TX of the TX driver210to be coupled to the positive output pin Vop1of the TXIC230F through a short bonding wire901having substantially no inductance. In addition, the bond pad917allows the negative output pin Von TX of the TX driver210to be coupled to the negative output pin Von1of the TXIC230F through a short bonding wire903having substantially no inductance.

In this embodiment, the termination circuit215F employs the capacitor C1as an external component. The capacitor C1is coupled between the common node Ncm and ground. The common node Ncm is coupled to the first inductor L1and the second inductor L2through a termination pin Vt of the TXIC230F.

Beneficially, the disclosed configuration provides an optimal termination of an output of the transmitter while decreasing EMI and maintaining signal quality.

Upon reading this disclosure, those of skill in the art will appreciate still additional alternative designs for an apparatus with improved source termination. Thus, while particular embodiments and applications of the present disclosure have been illustrated and described, it is to be understood that the embodiments are not limited to the precise construction and components disclosed herein and that various modifications, changes and variations which will be apparent to those skilled in the art may be made in the arrangement, operation and details of the method and apparatus of the present disclosure disclosed herein without departing from the spirit and scope of the disclosure as defined in the appended claims.