Semiconductor device and manufacturing method thereof

A semiconductor device having an EMI shield layer and/or EMI shielding wires, and a manufacturing method thereof, are provided. In an example embodiment, the semiconductor device includes a semiconductor die, an EMI shield layer shielding the semiconductor die, and an encapsulating portion encapsulating the EMI shield layer. In another example embodiment, the semiconductor device further includes EMI shielding wires extending from the EMI shield layer and shielding the semiconductor die.

BACKGROUND

Embodiments of the present disclosure provide a semiconductor device and a manufacturing method thereof.

Recent electronic devices, such as smartphones, laptop computers, and tablet computers, include multiple wireless semiconductor devices to be equipped with wireless communication functions. The wireless semiconductor devices generate electromagnetic noise due to clock frequencies of built-in integrated circuits and a high data transmission speed. In order to suppress the electromagnetic noise, a substrate-level “metal shield” method has conventionally been used. However, the substrate-level “metal shield” method involves a complex manufacturing process that may result in low productivity and poor yield. Moreover, the complex manufacturing process may impede miniaturization and slimming of an electronic device employing the same.

BRIEF SUMMARY

Semiconductor devices including a semiconductor die and/or an encapsulating portion treated with EMI shielding are substantially shown in and/or described in connection with at least one of the figures, and are set forth more completely in the claims.

Various advantages, aspects and novel features of the present disclosure, as well as details of various illustrated example supporting embodiments, will be more fully understood from the following description and drawings.

DETAILED DESCRIPTION

As utilized herein, “and/or” means any one or more of the items in the list joined by “and/or”. As an example, “x and/or y” means any element of the three-element set {(x), (y), (x, y)}. That is, “x and/or y” means “one or both of x and y.” As another example, “x, y, and/or z” means any element of the seven-element set {(x), (y), (z), (x, y), (x, z), (y, z), (x, y, z)}. That is, “x, y, and/or z” means “one or more of x, y, and z.” As utilized herein, the terms “e.g.,” and “for example” set off lists of one or more non-limiting examples, instances, or illustrations.

The terminology used herein is for the purpose of describing particular examples only and is not intended to be limiting of the disclosure. As used herein, the singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “includes,” “comprising,” “including,” “has,” “have,” “having,” and the like when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, for example, a first element, a first component or a first section discussed below could be termed a second element, a second component or a second section without departing from the teachings of the present disclosure. Similarly, various spatial terms, such as “upper,” “lower,” “side,” “top,” “bottom,” and the like, may be used in distinguishing one element from another element in a relative manner. It should be understood, however, that components may be oriented in different manners, for example a semiconductor device may be turned sideways so that its “top” surface is facing horizontally and its “side” surface is facing vertically, without departing from the teachings of the present disclosure.

Referring toFIGS. 1A and 1B, cross-sectional views of a semiconductor device100are provided in accordance with various example embodiments of the present disclosure. As illustrated, the semiconductor device100may include semiconductor dies110A and110B, an EMI shield layer120, a substrate130, and an encapsulating portion150. In addition, the semiconductor device100may further include external interconnection structures160.

Each of the semiconductor dies110A and110B may have a substantially planar first surface111, a substantially planar second surface112opposite to the first surface111, and third surfaces113formed between the first surface111and the second112. In addition, each of the semiconductor dies110A and110B may include at least one or more contact pads114(e.g., bonding pads or redistribution pads) formed on the second surface112, and at least one or more internal interconnection structures115connected to the internal contact pads114. Substantially, the first surface111may include a top surface of each of the semiconductor dies110A and110B, the second surface112may include a bottom surface of each of the semiconductor dies110A and110B, and the third surface may include one or more of the four side surfaces of each of the semiconductor dies110A and110B.

The semiconductor device100is shown with two semiconductor dies110A and110B inFIGS. 1A and 1B. However, the semiconductor device100, in some embodiments, may include a single semiconductor die or more than two semiconductor dies.

Examples of the internal interconnection structures115may include, but are not limited to, various types of structures, such as micro bumps, metal pillars, solder bumps, or solder balls, that electrically bond the semiconductor dies110A and110B to the substrate130. In an example, the internal interconnection structures115may include copper pillars having solder bumps or solder caps115athat are bonded to the substrate130by reflowing or thermal compression. The internal interconnection structures115may have, but are not limited to, a pitch of approximately 20-50 micrometers (μm) and/or a pitch of approximately 90-100 μm.

Meanwhile, the semiconductor dies110A and110B may include integrated circuit dies separated from a semiconductor wafer and examples thereof may include, but are not limited to, electric circuits, such as digital signal processors (DSPs), microprocessors, network processors, power management processors, audio processors, RF circuits, wireless baseband system-on-chip (SoC) processors, sensors, and application specific integrated circuits (ASICs).

The EMI shield layer120may include a substantially planar first conductive layer121that shields the first surfaces111of the semiconductor dies110A and110B, and substantially planar second conductive layers122that shield the third surfaces113of the semiconductor dies110A and110B. In this manner, the first conductive layer121and the second conductive layers122may provide a EMI shield layer120having a cap shape that shields top surfaces and four side surfaces of the semiconductor dies110A and110B. In addition, when the semiconductor device100includes the first semiconductor die110A horizontally spaced from the second semiconductor die110B, the EMI shield layer120may fill a gap between the first and second semiconductor dies110A and110B. In particular, the second conductive layer122of the EMI shield layer120may be configured such that second conductive layer122is inserted into a region between third surfaces113of the first and second semiconductor dies110A and110B.

The EMI shield layer120may prevent electromagnetic waves generated from the semiconductor dies110A and110B from being radiated to the outside. Moreover, the EMI shield layer120may prevent externally applied electromagnetic waves from entering the semiconductor dies110A and110B. Throughout the detailed description, such functions of the EMI shield layer120may be referred to as EMI shielding.

To enable shielding of electromagnetic waves, the EMI shield layer120may be formed using various conductive materials. Examples of suitable conductive materials for the EMI shield layer120may include, but are not limited to, copper (Cu), nickel (Ni), gold (Au), silver (Ag), platinum (Pt), cobalt (Co), titanium (Ti), chromium (Cr), zirconium (Zr), molybdenum (Mo), ruthenium (Ru), hafnium (Hf), tungsten (W), rhenium (Re), graphite, or carbon black. In some embodiments, the EMI shield layer120may further include metal particles and a binder for binding metal particles internal to the EMI shield layer. In other embodiments, the EMI shield layer120may further include metal particles and a binder for attaching the metal particles to surfaces of the semiconductor dies110A and110B.

In addition, the EMI shield layer120may include a conductive polymer, such as polyacetylene, poylaniline, polypyrrole, polythiophene or poly-sulfur-nitride, doped with a metal or metal oxide. Further, the EMI shield layer120may comprise conductive ink having a conductive material such as carbon black, graphite, and silver.

A thickness of the EMI shield layer120may be in a range of, for example, approximately 0.1 μm to approximately 1000 μm, preferably 1 μm to 100 μm, and more preferably 3 μm to 30 μm, but aspects of the present disclosure are not limited thereto. When the thickness of the EMI shield layer120is smaller than 0.1 μm, EMI shielding efficiency of the EMI shield layer120may be smaller than a desired, threshold value, and when the thickness of the EMI shield layer120is greater than 1000 μm, a time required for forming the EMI shield layer120may be extended beyond an economically viable time frame.

In addition, the EMI shield layer120may be formed, for example, by various non-sputtering processes such as spin coating, spraying, printing, laminating, and/or a combination thereof, but are not limited thereto. As used herein, the term “non-sputtered” and related words and phrases are used to distinguish a layer that has been formed via a sputtering process from a layer such as, for example, EMI shield layer120that has been formed via spin coating, spraying, printing, laminating, and/or a combination of such processes. Such non-sputtered layers may possess various advantages over sputtered layers. For example, in comparison to sputtered layers, non-sputtered layers may yield higher UPH (units per hour), lower operational cost, lower tool cost, and better control of the thickness of formed layers, especially along sidewalls.

As described above, the EMI shield layer120is not formed on a surface of the encapsulating portion150but is instead directly formed on surfaces of the semiconductor dies110A and110B (e.g., silicon dies). As such, the semiconductor device100, according to various embodiments of the present disclosure, may exhibit improved EMI shielding efficiency. In particular, if the EMI shield layer120were formed on the external surface of the encapsulating portion150, the EMI shield layer120would be spaced a predetermined gap apart from the semiconductor dies110A and110B. Such spacing may allow the electromagnetic waves to be radiated from the semiconductor dies110A,110B to the outside or to enter the inside through the gap to the semiconductor dies110A,110B. However, with the EMI shield layer120directly formed on the surfaces of the semiconductor dies110A and110B, there is no gap between the EMI shield layer120and each of the semiconductor dies110A and110B. As such, the EMI shield layer120may considerably suppress the electromagnetic waves from being radiated from the semiconductor dies110A,110B to the outside or considerably suppress the electromagnetic waves from entering the semiconductor dies110A,110B from the outside.

Moreover, each of the semiconductor dies110A and110B may further include a ground circuit pattern116connected to the contact pads114. The ground circuit pattern116may be directly electrically connected to the EMI shield layer120(seeFIG. 1B.). The contact pads114may be electrically connected to the internal interconnection structures115. In addition, the internal interconnection structures115may be electrically connected to an upper circuit pattern132of the substrate130. The contact pads114, the internal interconnection structures115, and the upper circuit pattern132of the substrate130, may be electrically connected to the ground circuit pattern116, and may provide structures for grounding. Therefore, the EMI shield layer120may be grounded and more efficiently prevent electromagnetic waves from being radiated or induced. In some embodiments, some internal interconnection structures115may be used as ground bumps, some internal interconnection structures115may be used as signal bumps, and some internal interconnection structures115may be used as power bumps. In such embodiments, the ground circuit pattern116may be electrically connected to internal interconnection structures115used as ground bumps.

The substrate130may comprise a mechanical support structure for the semiconductor dies110A and110B, and/or passive devices. To this end, the substrate130may include a dielectric layer131and an upper circuit pattern (e.g., conductive traces)132formed on a top surface of the dielectric layer131. The upper circuit pattern132may be electrically connected to the internal interconnection structures115of each of the semiconductor dies110A and110B. The substrate130may further include a lower circuit pattern133electrically connected to an external circuit board formed on a bottom surface of the dielectric layer131. In particular, the substrate130may further include a plurality of circuit patterns134and vias135between the upper circuit pattern132and the lower circuit pattern133. Further, the plurality of circuit patterns134and vias135may be electrically connected to the upper circuit pattern132and/or the lower circuit pattern133. Examples of the substrate130may include, but are not limited to, a rigid printed circuit board, a flexible printed circuit board, a circuit board having a core, a coreless circuit board and a build-up circuit board.

Further, an underfill140may further fill a region between each of the semiconductor dies110A and110B and the substrate130. The underfill140may protect the internal interconnection structures115and may mechanically connect the semiconductor dies110A and110B to the substrate130. The underfill140may be applied to the semiconductor dies110A and110B and/or the substrate130before the semiconductor dies110A and110B and the substrate130are electrically connected. In some embodiments, the underfill140may fill a gap between each of the semiconductor dies110A and110B and the substrate130via capillary action after the semiconductor dies110A and110B and the substrate130are electrically connected. Additionally, the underfill140may comprise a non-conductive paste with or without an organic or inorganic filler.

The underfill140is configured such that the underfill140substantially adheres to the EMI shield layer120. In particular, the underfill140may adhere to bottom and side surfaces of the second conductive layers122formed on the third surfaces of the semiconductor dies110A and110B. For embodiments in which the EMI shield layer120is formed by spin-coating, spraying, and/or printing, the EMI shield layer120may have a very rough, porous surface, compared to surfaces of the semiconductor dies110A and110B. Specifically, the EMI shield layer120may exhibit a much higher roughness than the semiconductor dies110A and110B. Therefore, since the underfill140having relatively high roughness is directly adhered to the EMI shield layer120, adhesion between the underfill140and the EMI shield layer120is improved. Moreover, mechanical adhesion between the EMI shield layer120/the semiconductor dies110A and110B and the substrate130may be improved by the underfill140.

In some embodiments, the underfill140may not be provided. If a filler size of the encapsulating portion150(described in more detail below) is smaller than a size of the gap between a semiconductor dies110A,110B and the substrate130, an encapsulating material may sufficiently inject into and fill the gap. In such embodiments, the underfill140may not be provided.

The encapsulating portion150(e.g., an encapsulating member or an encapsulant) may encapsulate the EMI shield layer120, the underfill140, and the substrate130. The encapsulating portion150may protect the EMI shield layer120, the underfill140, and the substrate130from external circumstances. Examples of the encapsulating portion150as well as other encapsulating portions described herein may include, but are not limited to, an epoxy mold compound, an epoxy mold resin, and so on. The encapsulating portion150may entirely encapsulate the EMI shield layer120on the substrate130. In some embodiments, the encapsulating portion150may expose a portion of the EMI shield layer120. For example, the encapsulating portion150may not be formed on the first conductive layer121of the EMI shield layer120. As such, the first conductive layer121of the EMI shield layer120may be directly exposed to the outside. More specifically, a top surface of the first conductive layer121of the EMI shield layer120may be coplanar with a top surface of the encapsulating portion150. In such embodiment, the semiconductor dies110A and110B may have more increased heat radiating performance.

If the encapsulating portion150entirely encapsulates the EMI shield layer120, high adhesion between the encapsulating portion150and the EMI shield layer120may result. As such, interfacial delamination between the encapsulating portion150and the EMI shield layer120may be eliminated. In particular, since the roughness of the EMI shield layer120is high, as described above, the adhesion demonstrated between the encapsulating portion150and the EMI shield layer120is further increased. Moreover, if the encapsulating portion150entirely encapsulates the EMI shield layer120, the encapsulating portion150may protect the EMI shield layer120from external physical and chemical shocks.

Examples of the external interconnection structures160may include, but are not limited to, metal pillars, solder bumps, solder balls, bumps or lands. The external interconnection structures160may include bumps having a size of approximately 100-200 μm or bumps/pillars having a size of approximately 20-100 μm. When solder bumps are used in the external interconnection structures160, the external interconnection structures160may include one or more solder metals melted at a lower temperature than other metals and may provide physical and electrical bonding between the external interconnection structures160and an external circuit board or another device during melting and cooling processes. Examples of the external interconnection structures160may include, but are not limited to, a ball grid array (BGA) and/or a land grid array (LGA). While solder balls used in the external interconnection structures160are illustrated, the external interconnection structures160may include various types of structures.

As described above, according to various embodiments of the present disclosure, the EMI shield layer120is directly formed on the first surface111(e.g., top surface) and/or the third surface113(e.g., side surface) of the semiconductor dies110A and110B. Such forming of the EMI shield layer120may improve the productivity and yield of the EMI shield layer120and may provide the semiconductor device100with improved EMI shielding efficiency. In addition, since the EMI shield layer120is embedded into the encapsulating portion150, the semiconductor device100may be safely protected from external circumstances. Furthermore, such forming of the EMI shield layer120may aid in miniaturizing and slimming of the semiconductor device100.

Referring toFIGS. 2A and 2B, cross-sectional views of a semiconductor device200according to various example embodiments of the present disclosure are illustrated. As illustrated, the semiconductor device200may be formed in a similar manner to the semiconductor device100. However, the semiconductor device200may include internal interconnection structures215comprising conductive balls that connect the semiconductor dies110A and110B to the substrate130. In comparison, the internal interconnection structures115of the semiconductor device100illustrated inFIGS. 1A and 1Binclude conductive pillars having solders (e.g., copper pillars).

The internal interconnection structures215, such as solder balls, may electrically connect the semiconductor dies110A and110B to the substrate130by mass reflowing, which may improve the productivity of the semiconductor device200. In addition, the interconnection structures215, such as solder balls, may be formed in a more simplified manner than other internal interconnection structures such as conductive pillars. As such, the interconnection structures215may be formed at low cost than the interconnection structures115, thus reducing manufacturing costs of the semiconductor device200in comparison to the semiconductor device100.

FIGS. 3A and 3Bdepicts cross-sectional views of a semiconductor device300and a semiconductor die110having an EMI shield layer320according to various example embodiments of the present disclosure.FIG. 3Cprovides a plan view of the EMI shield layer320and wires370.

As illustrated inFIGS. 3A-3C, the semiconductor device300, according to various example embodiments of the present disclosure, may include a semiconductor die110, an EMI shield layer320formed only on first surfaces111(e.g., top surfaces) of the semiconductor die110, and a plurality of EMI shielding wires370electrically connecting the EMI shield layer320to the substrate130. In particular, the EMI shield layer320may be formed only on the first surface111of the semiconductor die110but not on third surfaces113of the semiconductor die110. Therefore, the encapsulating portion150may be directly adhered to the EMI shield layer320formed on the first surface111of the semiconductor die110and to the third surfaces113of the semiconductor die110.

In addition, the EMI shielding wires370may electrically connect the EMI shield layer320to a ground circuit pattern332of the substrate130. In particular, the EMI shielding wires370may be substantially parallel with the third surfaces113of the semiconductor dies110. To this end, first ends of the EMI shielding wires370may be ball-bonded (or stitch-bonded) to the EMI shield layer320and second ends of the EMI shielding wires370may be stitch-bonded (or ball-bonded) to the ground circuit pattern332.

A planar shape of the EMI shield layer320may be, but is not limited to, a generally rectangular shape having four sides. A planar shape of the ground circuit pattern332of the substrate130may also be a generally rectangular shape having four sides. The EMI shielding wires370may be arranged at a constant pitch along the four sides of the EMI shield layer320. Each of the EMI shielding wires370may electrically connect one side of the EMI shield layer320to a corresponding side of the ground circuit pattern332.

The EMI shielding wires370may be spaced a predetermined distance apart from the third surfaces113of the semiconductor dies110and may shield the semiconductor die110. The distance or pitch between the EMI shielding wires370may vary according to wavelength range of electromagnetic waves to be shielded. For example, the shorter the wavelength of electromagnetic waves to be shielded, the smaller the distance or pitch between the EMI shielding wires370. Examples of materials, from which to construct the EMI shielding wires370, may include, but are not limited to, various metals, such as gold (Au), silver (Ag), copper (Cu), or aluminum (Al).

The encapsulating portion150may encapsulate and protect the semiconductor die110, the EMI shield layer320, and the EMI shielding wires370on the substrate130from external physical and chemical circumstances. In turn, the EMI shield layer320and the EMI shielding wires370may inductively shield the semiconductor die110from electromagnetic waves.

As described above, according to various embodiments of the present disclosure, the EMI shield layer320and EMI shielding wires370form a Faraday cage around the semiconductor die110. Such Faraday cage may prevent electromagnetic waves generated from the semiconductor die110from being radiated to the outside. Moreover, the Faraday cage may prevent external electromagnetic waves from entering and interfering with the semiconductor die110.

Referring toFIGS. 4A and 4B, a cross-sectional view and a side view of a semiconductor device400according to various example embodiments of the present disclosure are illustrated. As illustrated inFIGS. 4A and 4B, the semiconductor device400may include a semiconductor die110, a substrate130, an encapsulating portion450, and an EMI shield layer420. The encapsulating portion450may include a first region451encapsulating roughly the first surface111of the semiconductor die110and a second region452encapsulating roughly third surfaces113of the semiconductor dies110.

The EMI shield layer420may shield the first region451of the encapsulating portion450and at least a portion of the second region452. As illustrated, the EMI shield layer420may shield the second region452of the encapsulating portion450, but aspects of the present disclosure are not limited thereto. Rather, the EMI shield layer420may shield the first region451of the encapsulating portion450.

The substrate130may further include an antenna pattern434formed on a top surface thereof. If the antenna pattern434is encapsulated by the EMI shield layer420, the EMI shield layer would prevent or substantially reduce the antenna pattern434from functioning as an antenna. Therefore, the antenna pattern434, as shown, may be exposed from the EMI shield layer420and/or the encapsulating portion450.

To this end, the EMI shield layer420may be formed on, for example, the second region452of the encapsulating portion450, but not formed on, for example, the antenna pattern434. An insulation layer435may be interposed between the EMI shield layer420and the antenna pattern434. Alternatively, the EMI shield layer420and the antenna pattern434may be spaced a predetermined distance apart from each other. In addition, the EMI shield layer420may be electrically connected to the ground circuit pattern432formed on the substrate130. Since the EMI shield layer420is formed on a region spaced apart from the antenna pattern434(e.g., the second region452of the encapsulating portion450), the EMI shield layer420may efficiently shield electromagnetic waves from semiconductor die110while not impeding the operation of the antenna pattern434formed on the substrate130.

Referring toFIG. 5, a cross-sectional view of a semiconductor device500according to various example embodiments of the present disclosure is illustrated. As illustrated inFIG. 5, the semiconductor device500may include a semiconductor die110, a substrate130, a first encapsulating portion551encapsulating the semiconductor die110, an EMI shield layer520formed on the first encapsulating portion551, EMI shielding wires570connecting the EMI shield layer520to the substrate130, and a second encapsulating portion552encapsulating the first encapsulating portion551, the EMI shield layer520, and the EMI shielding wires570.

The first encapsulating portion551may encapsulate a first surface111and third surfaces113of the semiconductor die110. A first region551aof the first encapsulating portion551may encapsulate the first surfaces111of the semiconductor die110. The second region551bof the first encapsulating portion551may encapsulate the third surface113of the encapsulating portion551.

The EMI shield layer520may be formed on the first region551aof the first encapsulating portion551. In particular, the EMI shield layer520may be formed on the first region551aof the first encapsulating portion551corresponding to the first surface111of the semiconductor die110. The first region551aof the first encapsulating portion551may be formed to be substantially planar. The EMI shield layer520may also be formed to have a substantially planar plate.

The EMI shielding wires570may electrically connect the EMI shield layer520to the ground circuit pattern332provided on the substrate130. In an example, the EMI shielding wires570may be formed to be substantially parallel with the second region551bof the first encapsulating portion551. In addition, the EMI shielding wires570may be spaced a predetermined distance apart from the second region551bof the first encapsulating portion551. In particular, the EMI shielding wires570may be formed to shield the first encapsulating portion551(e.g., third surfaces of the semiconductor dies110).

The second encapsulating portion552may encapsulate the first encapsulating portion551, the EMI shield layer520, and the EMI shielding wires570. Examples of the second encapsulating portion552may include, but are not limited to, the same or different material from that of the first encapsulating portion551. In some embodiments, the second encapsulating portion552may have a smaller modulus than the first encapsulating portion551. Therefore, the second encapsulating portion552may efficiently absorb or relieve external shocks, compared to the first encapsulating portion551.

As described above, the semiconductor dies110is encapsulated by the first encapsulating portion551. The EMI shield layer520is formed on a surface of the first encapsulating portion551, thereby protecting the semiconductor die110from external circumstances. The EMI shield layer520may further provide the semiconductor device500with improved EMI shielding efficiency. Since the semiconductor die110is encapsulated by both the first encapsulating portion551and the plurality of EMI shielding wires570, the semiconductor device500has improved EMI shielding efficiency.

In some embodiments, the second encapsulating portion552may be omitted. In such embodiments, the EMI shield layer520and the EMI shielding wires570may be exposed to the outside. Further, a portion of the first encapsulating portion551not covered by the EMI shield layer520, a portion of the substrate130not covered by the first encapsulating portion552, and the passive device may be exposed to the outside. However, the EMI shield layer520and EMI shielding wires570still form a Faraday cage around the semiconductor die110. As described above, the Faraday cage may prevent electromagnetic waves generated from the semiconductor die110from being radiated to the outside and may prevent external electromagnetic waves from entering and interfering with the semiconductor die110.

Referring toFIG. 6, a flowchart of a manufacturing method of a semiconductor device according to various example embodiments of the present disclosure is illustrated. As illustrated, the manufacturing method may include a wafer bumping step (S1) of forming interconnection structures on a front side of a wafer (e.g., second surfaces of semiconductor dies) and a wafer mount tape laminating step (S2) of laminating a wafer mount tape on a back side (e.g., a first surface) of the wafer. The method may further include a wafer dicing step (S3) of separating the wafer into individual semiconductor dies along street lines, and a bump protecting tape laminating step (S4) of laminating a bump protecting tape on the front side of the wafer.

The method may also include a wafer mount tape peeling-off step (S5) of peeling off the wafer mount tape from the wafer, and an edge cutting step (S6) of cutting the edge of the bump protecting tape and removing the same. Further yet, the method may include an EMI shield layer spin-coating step (S7) of spin-coating an EMI shield layer on the back side of the wafer, and a curing or sintering step (S8) of curing or sintering the coated EMI shield layer.

The method may further include a wafer mount tape laminating step (S9) of laminating the cured or sintered wafer mount tape on the back side of the wafer, and a bump protecting tape peeling-off step (S10) of peeling off the bump protecting tape from the front side of the wafer. Moreover, the method may include a dicing step (S11) of separating from the wafer into individual semiconductor dies or a plurality of semiconductor dies, and a die picking-up step (S12) of picking up the separated semiconductor dies using a pickup tool. The method may also include a die attaching step (S13) of attaching the semiconductor dies to a substrate.

Referring toFIGS. 7A-7M, cross-sectional views sequentially illustrating process steps of a manufacturing method of a semiconductor device according to various example embodiments of the present disclosure are illustrated. In particular, the manufacturing method is described in reference to the semiconductor device100,FIGS. 1A, 1B, 6, and 7A-7M.

As illustrated inFIG. 7A, in the wafer bumping step (S1), a plurality of internal interconnection structures115are formed on the front side of a wafer110W. In particular, the plurality of internal interconnection structures115may be formed on front sides (e.g., second surfaces112) of individual semiconductor dies110that are formed on the wafer110W. Examples of the various types of internal interconnection structures115may include, but are not limited to, micro bumps, metal pillars, solder bumps, solder balls, etc.

As illustrated inFIG. 7B, in the wafer mount tape laminating step (S2), a wafer mount tape601may be mounted on a back side of the wafer110W. In particular, the wafer mount tape601may be mounted on first surfaces111of the semiconductor dies110that are formed on the wafer110W. Although not illustrated, the wafer mount tape601may supported by a substantially circular mount ring. More specifically, the back side of the wafer110W may be temporarily adhered to the wafer mount tape601supported by the circular mount ring.

As illustrated inFIG. 7C, in the wafer dicing step (S3), the individual semiconductor dies110may be separated along the street lines formed on the wafer110W using a dicing tool602such as, for example, a diamond blade, diamond wheel, or a laser beam. Therefore, the individual semiconductor dies110formed on the wafer110W may be spaced a predetermined distance apart from each other due to such wafer dicing. Moreover, the wafer dicing may maintain the individual semiconductor dies110in a state in which the semiconductor dies110are still adhered to the wafer mount tape601.

As illustrated inFIG. 7D, in the bump protecting tape laminating step (S4), a bump protecting tape603may be laminated on the wafer110W including the plurality of semiconductor dies110spaced apart from each other. In particular, the bump protecting tape603may be temporarily adhered to the front side of the wafer110W. The internal interconnection structures115formed on the front side of the wafer110W may be protected by the bump protecting tape603during a manufacturing process.

As illustrated inFIG. 7E, in the wafer mount tape peeling-off step (S5), the wafer mount tape601adhered to the back side of the wafer110W may be peeled off. Accordingly, the back side of the wafer110W may be exposed to the outside. In particular, the wafer mount peeling-off step may expose the first surface111and the third surface113of each of the separated individual plurality of semiconductor dies110to the outside. However, the wafer mount tape peeling-off step may maintain the semiconductor dies110or the front side (e.g. second surface112) of the wafer110W in a state in which the semiconductor dies110remain adhered to the bump protecting tape603.

As illustrated inFIG. 7F, in the edge cutting step (S6), an edge cutting tool604may cut a circumferential edge of the bump protecting tape603corresponding to that of the wafer110W. In this manner, the excess bump protecting tape603that extends beyond the circumferential edge of the wafer110is thus removed by the edge cutting tool604. Accordingly, the wafer110W and the bump protecting tape603may have the same planar shape after the edge cutting step (S6).

As illustrated inFIG. 7G, in the EMI shield layer spin-coating step (S7), the wafer110W may be mounted via the bump protecting tape603on a spin coating apparatus605. The EMI shield layer120may then be spin-coated on the back side of the wafer110W by a coating tool606. Accordingly, spin coating apparatus602may coat the EMI shield layer120not only on the top surface (e.g., the first surfaces111) of the semiconductor dies110but also on side surfaces (e.g., the third surfaces113) of the semiconductor dies110. To this end, the spin coating apparatus605may use a highly-viscous coating solution or slurry that includes metal particles, a binder for binding the metal particles, and a solvent. After the highly viscous slurry for the EMI shield layer120is coated on the back side of the wafer110W, the spin coating apparatus605may rotate the wafer110W at a high speed, so that the EMI shield layer120is uniformly distributed on the first and third surfaces111and113of the semiconductor dies110. In some embodiments, the EMI shield layer120may be formed from, for example, a conductive polymer, a conductive ink, or a conductive paste.

As illustrated inFIG. 7H, in the curing or sintering step (S8), the EMI shield layer120formed on the back side of the wafer110W may be cured and/or sintered by heat and/or light. For example, when the EMI shield layer120is made of a heat-curable material, heat may be applied to the EMI shield layer120, and/or when the EMI shield layer120is made of a photo-curable material, light may be applied to the EMI shield layer120. The solution contained in the slurry may be completely volatilized and removed by the curing and/or sintering process. As a result, only the conductive metal or the conductive polymer and the binder may remain in the EMI shield layer120.

As illustrated inFIG. 7I, in the wafer mount tape laminating step (S9), a wafer mount tape607may again be laminated on a surface of the cured and/or sintered EMI shield layer120.

As illustrated inFIG. 7J, in the bump protecting tape peeling-off step (S10), the bump protecting tape603adhered to the front side (e.g., the second surfaces112) of the wafer110W may be peeled-off. Accordingly, the front side of the wafer110W and the internal interconnection structures115may be exposed to the outside.

As illustrated inFIG. 7K, in the dicing step (S11), the individual semiconductor dies110or the plurality of semiconductor dies110are separated from the wafer110W by a dicing tool608, such as a diamond wheel or a laser beam. The dicing tool608may saw the EMI shield layer120formed between each of the semiconductor dies110and its adjacent semiconductor die110. Accordingly, single semiconductor die(s)110may be separated or groups of semiconductor dies may be separated from the wafer110W. A width of the dicing tool608may be smaller than a thickness or width of the EMI shield layer120formed in a gap between each of the semiconductor dies110and its adjacent semiconductor die110. As such, the EMI shield layer120may remain on the side surfaces (e.g., the third surfaces113) of the semiconductor dies110even after the dicing. The thickness of the EMI shield layer120remaining on the third surfaces113of the semiconductor dies110may be in the range of, for example, approximately 0.1 μm to approximately 1000 μm, or in the more narrow range of 1 μm to 100 μm, or in the even more narrow range of 10 μm to 30 μm, but aspects of the present disclosure are not limited thereto.

As illustrated inFIG. 7L, in the die pickup step (S12), an eject pin610may upwardly push a pertinent semiconductor die110. A pickup tool609may pick up and remove the pertinent semiconductor die110from the wafer mount tape607. The pickup tool609may further move the pertinent semiconductor die110to a predetermined position.

As illustrated inFIG. 7M, in the die attaching step (S13), the pickup tool609may transfer good-quality semiconductor dies110having the EMI shield layer120to a rectangular substrate130or separate wafer tray. The semiconductor dies110placed on the substrate130may be electrically connected to the substrate130by mass reflowing or thermal compression. Thereafter, an underfilling step, an encapsulating step, and an external interconnection structure forming step are sequentially performed.

As described above, the manufacturing method of the semiconductor device100according to the example embodiment of the present disclosure allows the semiconductor dies110having the EMI shield layer120to be rapidly mass-produced at low costs in large scales. Therefore, according to the embodiment of the present disclosure, the semiconductor dies110having the EMI shield layer120may be produced at low costs in high yield/high productivity. Moreover, since the EMI shield layer120is directly formed on surfaces of the semiconductor dies110, the semiconductor device100may have high EMI shielding efficiency with improved miniaturization and slimness. Further, since the EMI shield layer120is embedded into the encapsulating portion150, the semiconductor device100may be protected from external circumstances.

Referring toFIGS. 8A-8J, cross-sectional views sequentially illustrating process steps of a manufacturing method of a semiconductor device according to various example embodiments of the present disclosure are illustrated. In particular, the manufacturing method is described with reference to the semiconductor device300,FIGS. 3A-3C, andFIGS. 8A-8J.

As illustrated inFIG. 8A, a bump protecting tape603may be laminated on a front side (e.g., second surfaces112) of a bumped wafer110W. The back side (e.g., first surfaces111) of the wafer110W may remain exposed to the outside.

As illustrated inFIG. 8B, an edge cutting tool604may cut a region of the bump protecting tape603corresponding to a circumferential edge of the wafer110W. As such, the bump protecting tape603extending beyond the circumferential edge of the wafer110W may be removed by an edge cutting tool604. After such cutting and removing, the wafer110W and the bump protecting tape603may have substantially the same planar shape.

As illustrated inFIG. 8C, the wafer110W may be mounted on a spin coating apparatus605. In particular, the wafer110wmay be adhered to the spin coating apparatus605via the bump protecting tape603. A slurry for forming an EMI shield layer320may then be spin-coated on the back side of the wafer110W. In addition to the spin coating, the EMI shield layer320may also be formed by spraying, printing, and/or laminating.

In yet other embodiments, the EMI shield layer320may be formed using a conductive foil321such as a copper foil. In particular, in such embodiments, a conductive foil321having a copper layer322and an adhesive layer323may be rolled or vacuum laminated on the back side of the wafer110W as shown inFIG. 11. In some embodiments, the copper layer322may have a thickness of at least 12 μm and the adhesive layer323may have a thickness of at least 10 μm, thus resulting in the copper foil321having a thickness of at least 22 μm.

Since the wafer110W has not been diced before the spin coating or laminating of the EMI shield layer320, a gap is not created between each of the semiconductor dies110and its adjacent semiconductor die110as in the method ofFIGS. 7A-7M. As such, the spin-coating apparatus605in the method ofFIGS. 8A-8Jdoes not form the EMI shield layer320between adjacent semiconductor die110, but only on the back side of the wafer110W.

As illustrated inFIG. 8D, the spin-coated EMI shield layer320may be cured and/or sintered by heat and/or light. A wafer mount tape607may then be laminated on a surface of the cured and/or sintered EMI shield layer320as illustrated inFIG. 8E. As illustrated inFIG. 8F, the bump protecting tape603may be peeled off and removed. Accordingly, the front side of the wafer110W may be exposed to the outside.

As illustrated inFIG. 8G, dicing may be performed by a dicing tool608, such as a diamond wheel or a laser beam, along street lines provided on the wafer110W. The plurality of semiconductor dies110formed on the wafer110W may be separated by performing the dicing individually or by groups. As a result, third surfaces113of the plurality of semiconductor dies110may be directly exposed to the outside. In particular, the third surfaces113of the plurality of semiconductor dies110may directly exposed to the outside while EMI shield layer320shields the first surfaces111of the plurality of semiconductor dies110.

As illustrated inFIG. 8H, the separated individual or groups of semiconductor dies110are picked up from the wafer110W by operations of the pickup tool609and the eject pin610. As illustrated inFIG. 8I, the semiconductor dies110may be placed on the substrate130. In this manner, the EMI shield layer320may be formed only on top surfaces (e.g., first surfaces111) of the semiconductor dies110. After the semiconductor dies110are picked up and placed on the substrate130, internal interconnection structures115of the semiconductor dies110may be electrically connected to the substrate130by mass reflowing or thermal compression.

As illustrated inFIG. 8J, a wire bonder611may electrically connect the EMI shield layer320formed on the semiconductor dies110to a ground circuit pattern of the substrate130via EMI shielding wires370. In particular, the wire bonder611may surround the semiconductor dies110with a plurality of EMI shielding wires370. Therefore, the top surfaces (e.g., the first surfaces111) of the semiconductor dies110may be shielded from electromagnetic waves by the EMI shield layer32. The side surfaces (e.g., third surfaces113) of the semiconductor dies110may shielded from electromagnetic waves by the EMI shielding wires370.

FIGS. 9A-9Cdepict cross-sectional views sequentially illustrating process steps of a manufacturing method of a semiconductor device according to various example embodiments of the present disclosure. In particular, the manufacturing method is described with reference to the semiconductor device400,FIGS. 4A-4B, andFIGS. 9A-9C.

As illustrated inFIG. 9A, the semiconductor die110placed on the substrate130may be encapsulated by the encapsulating portion450of the semiconductor device400. Moreover, an antenna pattern434of the substrate130may be exposed to the outside. The encapsulating portion450may be divided into a first region451that encapsulates the first surface111of the semiconductor die110and a second region452that encapsulates the third surfaces113of the semiconductor die110. The antenna pattern434may be exposed and may protrude to the outside through the second region452of the encapsulating portion450.

As illustrated inFIG. 9B, a printer612may print the EMI shield layer420using an EMI shielding material such as conductive ink. In particular, the printer612may print the EMI shield layer420only on the second region452of the encapsulating portion450and electrically disconnected from the antenna pattern434. Further, the EMI shield layer420may be electrically connected to a ground circuit pattern432.

As illustrated inFIG. 9C, a flash lamp613may sinter and/or cure the printed EMI shield layer420. In particular, the flash lamp613may include a Xenon lamp and a reflector that photo-sinter the EMI shield layer420by intense pulsed light (IPL). In an example embodiment, the flash lamp613may radiate the EMI shield layer420with pulsed light for approximately 0.1 μs to approximately 100 μs. The pulsed light may sinter metal particles or metal oxide particles contained in the conductive ink to form the EMI shield layer420.

Referring toFIGS. 10A-10D, cross-sectional views sequentially illustrating process steps of a manufacturing method of a semiconductor device according to various embodiments of the present disclosure are illustrated. The manufacturing method is described with reference to the semiconductor device500,FIG. 5, andFIGS. 10A-10D.

As illustrated inFIG. 10A, a first encapsulating portion551may encapsulate the semiconductor dies110. Further, a printer612may print an EMI shielding material on a surface of the first encapsulating portion551to form an EMI shield layer520. In particular, a first region551aof the first encapsulating portion551may be formed on first surfaces111of the semiconductor dies110, a second region551bof the first encapsulating portion551may be formed on third surfaces113of the semiconductor dies110, and the EMI shield layer520having a predetermined thickness may be printed on the first region551aof the first encapsulating portion551without forming the EMI shield layer520on the second region551bof the first encapsulating portion551. As shown, the second region551bof the first encapsulating portion551may be interposed between first and second semiconductor dies110. In particular, the second region551bof the first encapsulating portion551may be inserted into a region between the third surfaces113of the first and second semiconductor dies110.

As illustrated inFIG. 10B, a flash lamp613may be photo-sinter the EMI shield layer520formed on the first region551awith radiated light. In particular, the EMI shield layer520may be formed in a liquid or gel phase. The radiated light from flash lamp613may convert the liquid or gel phase EMI shield layer520into a solid phase, rigidly cured on the first encapsulating portion551.

As illustrated inFIG. 10C, a dicing tool608may separate the first semiconductor die110from the second semiconductor die110. In particular, such separating may result in the separated EMI shield layer520and the second region551bof the first encapsulating portion551being coplanar.

After such separating, the first semiconductor die110, including the first encapsulating portion551and the EMI shield layer520, may be electrically connected to a substrate130by mass reflowing or thermal compression as illustrated inFIG. 10D. A wire bonder611may form a plurality of EMI shielding wires570in vicinity of the first encapsulating portion551. In particular, the wire bonder611may bond first ends of the EMI shielding wires570to the EMI shield layer520and second ends of the EMI shielding wires570to a ground circuit pattern332of a substrate130.

Thereafter, the first encapsulating portion551, the EMI shield layer520, and the EMI shielding wires570may be encapsulated by the second encapsulating portion552, and a plurality of external interconnection structures160may be formed on a bottom surface of the substrate130. As described above, some embodiments may omit the second encapsulating portion552. In such embodiments, the semiconductor device may be sold with the EMI shield layer520and the EMI shielding wires570exposed.

While the semiconductor device of the present disclosure and the manufacturing thereof have been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure as defined by the following claims.