A pre-converter is connected with AC power line voltage and provides DC voltage across a pair of DC terminals. A current-limiting inductor, a self-oscillating parallel-resonant inverter, and a periodically activated FET switch are series-connected with one another across the DC terminals. The inverter provides a high-frequency (e.g., 20-30 kHz) substantially sinusoidal output voltage across its output terminals. Each of plural rapid-start fluorescent lamps is connected across the output terminals by way of a current-limiting capacitor. The magnitude of the resulting lamp current depends on the RMS magnitude of the output voltage. In turn, for a given load condition, this RMS magnitude depends on the average magnitude of the unidirectional current drawn by the inverter from the DC terminals; which average magnitude is determined by the ON/OFF duty-cycle of the FET switch. The FET switch is turned ON/OFF at twice the frequency of the inverter's output voltage. By adjusting the ON/OFF-ratio, the average magnitude of the unidirectional current supplied to the inverter is correspondingly adjusted, thereby resulting in a corresponding adjustment in the magnitude of the lamp current.

FIELD OF THE INVENTION 
Instant invention relates to parallel-resonant inverter ballasts for gas 
discharge lamps, particularly of a kind that permits adjustment of lamp 
current magnitude. 
SUMMARY OF THE INVENTION 
Objects of the Invention 
An object of the present invention is that of providing cost-effective 
electronic ballasts for gas discharge lamps. 
Another object is that of providing cost-effective dimmable electronic 
ballasts for gas discharge lamps. 
This, as well as other objects and advantages of the present invention will 
become apparent from the following description. 
Brief Description 
A pre-converter is connected with the AC power line voltage of an ordinary 
electric utility power line and provides a DC voltage across a pair of DC 
terminals. 
A current-limiting inductor, a self-oscillating parallel-resonant inverter, 
and a periodically activated FET switch are series-connected with one 
another to form a series-combination; which series-combination is 
connected across the DC terminals. 
The inverter provides a high-frequency (e.g., 20-30 kHz) substantially 
sinusoidal output voltage across its output terminals. Each of plural 
rapid-start fluorescent lamps is connected across the output terminals by 
way of a current-limiting capacitor. 
The magnitude of the resulting lamp current depends on the RMS magnitude of 
the output voltage. In turn, for a given load condition, this RMS 
magnitude depends on the average magnitude of the unidirectional current 
drawn by the series-combination (and thus by the inverter) from the DC 
terminals; which average magnitude is determined by the ON/OFF duty-cycle 
of the periodically activated FET switch. 
The FET switch is turned ON/OFF at twice the frequency of the inverter's 
output voltage. By adjusting the ON/OFF-ratio, the average magnitude of 
the unidirectional current supplied to the inverter is correspondingly 
adjusted, thereby resulting in a corresponding adjustment in the magnitude 
of the lamp current. 
Cathode heating voltages for the rapid-start fluorescent lamps are obtained 
by way of auxiliary windings on the current-limiting inductor, thereby 
providing for cathode heating voltages appropriate for lamp dimming 
purposes.

DESCRIPTION OF THE FIRST EMBODIMENT 
Details of Construction of First Embodiment 
FIG. 1 shows an AC power supply S, which in reality is an ordinary 120 
Volt/60 Hz electric utility power line. 
One terminal of power supply S is grounded and also directly connected to a 
junction J between two energy-storing capacitors C1 and C2. The other 
terminal of power supply S is connected to the anode of a rectifier R1 and 
to the cathode of a rectifier R2. Rectifier R1 has its cathode connected 
to one terminal of C1--the other terminal of C1 being connected to 
junction J. Rectifier R2 has its anode connected to one terminal of 
C2--the other terminal of C2 being connected to junction J. 
An inductor means IM has two equal but separate windings W1 and W2:W1 is 
connected between the cathode of rectifier R1 and a junction B+ between 
the collectors of two transistors Q1a and Q1b; W2 is connected between the 
anode of R2 and a junction B- between the emitters of two transistors Q2a 
and Q2b. 
A Zener diode Z is connected between junction B+ and junction B-. 
Transistor Q1a is connected with its emitter to a junction Ja, as is also 
the collector of transistor Q2a. Transistor Q1b is connected with its 
emitter to a junction Jb, as is also the collector of transistor Q2b. 
A center-tapped inductor L is connected between inverter output terminals 
Oa and Ob. Connected in parallel with L is a capacitor C. The center-tap 
on inductor L, which is referred-to as inverter reference terminal IRT, is 
grounded. 
Primary winding PW1 of saturable current-transformer SCT1 is connected 
between junction Jb and output terminal Ob. Primary winding PW2 of 
saturable current-transformer SCT2 is connected between junction Ja and 
output terminal Oa. 
One secondary winding SW1a of transformer SCT1 is connected between the 
base and the emitter of transistor Q1a; another secondary winding SW1b of 
transformer SCT1 is connected between the base and the emitter of 
transistor Q1b. 
One secondary winding SW2a of transformer SCT2 is connected between the 
base and the emitter of transistor Q2a; another secondary winding SW2b of 
transformer SCT2 is connected between the base and the emitter of 
transistor Q2b. 
A series-combination of a ballasting capacitor CB and a gas discharge lamp 
GDL constitutes a load LD; which load is connected across output terminals 
Oa and Ob. 
Details of Operation of First Embodiment 
The operation of the full-bridge inverter circuit of FIG. 1 may be 
explained as follows. 
Source S provides 120 Volt/60 Hz voltage to the voltage-doubling and 
rectifying/filtering circuit consisting of R1, R2, C1 and C2. A 
substantially constant DC voltage of about 320 Volt magnitude then results 
at the output of this circuit, with the positive side of this DC voltage 
being present at the cathode of R1 and the negative side being present at 
the anode of R2. 
This substantially constant-magnitude DC voltage is applied by way of 
inductor means IM and its two windings W1 and W2, poled as indicated, to 
the DC power input terminals B+ and B- of the full-bridge inverter circuit 
comprising transistors Q1a, Q1b, Q2a and Q2b. 
This inverter circuit is made to self-oscillate by way of positive current 
feedback provided by saturable current-transformers SCT1 and SCT2, poled 
as indicated. Thus, the magnitude of the current provided to any given 
transistor's base-emitter junction is proportional to the magnitude of the 
current flowing between output terminals Oa and Ob. 
The frequency of inverter oscillation is determined by a combination of the 
saturation characteristics of the saturable current-transformers and the 
natural resonance frequency of the parallel L-C circuit (as combined with 
any tuning effects caused by the load connected thereacross). 
The saturation characteristics of the saturable current-transformers are 
substantially identical to one another and so chosen that, when there is 
no load connected across output terminals Oa and Ob, the waveform of the 
output voltage is as indicated in FIG. 2a; which waveform is made up of 
sinusoidal half-waves of voltage, indicated by HW1 and HW2, interconnected 
with periods of zero-magnitude voltage, indicated by ZM1 and ZM2. This 
waveform is achieved by making the time-length of the saturation-time 
required for the saturable current-transformers to reach saturation longer 
than the time-length of one of the sinusoidal half-waves of voltage. The 
degree to which the time-length of the saturation-time is longer than the 
time-length of one of the sinusoidal half-waves of voltage corresponds to 
the time-length of the periods of zero-magnitude voltage. 
In FIG. 2a, each of the sinusoidal half-waves of voltage represents the 
natural interaction between L and C as fed from a substantially constant 
current source. 
In combination, the two separate but equal windings W1 and W2 of inductor 
means IM provide for a total inductance that is large enough so that the 
current flowing through the two windings and into the inverter remains 
substantially constant during a complete time-period of one cycle of the 
inverter's oscillation. 
That is, the DC current flowing into the B+ junction and out of the B- 
junction is substantially constant during the interval between point X and 
point Y in FIG. 2a. Thus, whenever the L-C parallel circuit is connected 
between B+ and B---which it is during the complete time-length of each of 
the sinusoidal half-waves of voltage--it is indeed fed from a 
substantially constant current source. 
When a load impedance having a net component of capacitive reactance (such 
as does LD) is connected across the inverter's output terminals Oa and Ob, 
capacitive reactance is in effect added to the L-C parallel circuit; which 
results in the time-lengthening of the sinusoidal half-waves of 
voltage--as indicated by FIG. 2b. The more capacitance added this way, the 
more time-lengthening results. 
On the other hand, when a load impedance having a net component of 
inductive reactance is connected between Oa and Ob, the result would be a 
time-shortening of the sinusoidal half-waves of voltage. 
By having two different load impedances connected between Oa and Ob, and by 
having these two load impedances be of conjugate nature, there will be no 
net effect on the length of the period of the sinusoidal half-waves. For 
instance, by having another gas discharge lamp like GDL connected in 
series with an inductor having a reactance of the same absolute magnitude 
as that of CB, and by connecting this series-combination in parallel with 
load LD, the total net load impedance would be resistive and would cause 
no net shortening or lengthening of the sinusoidal half-waves of voltage. 
By making the time-length of the saturation-time of the saturable 
current-transformers substantially equal to the time-length of one of the 
sinusoidal half-waves of voltage, the resulting output voltage will be as 
illustrated in FIG. 2c; which indicates that the net inversion frequency 
will now be the same as the natural resonance frequency of the L-C 
parallel circuit (as combined with whatever load impedance might be 
connected between Oa and Ob). 
By making the time-length of the saturation-time of the saturable 
current-transformers shorter than the time-length of one of the sinusoidal 
half-waves of voltage, the resulting output voltage will be as illustrated 
in FIG. 2d; which indicates that the net inversion frequency will now be 
higher then the natural resonance frequency of the L-C circuit (as 
combined with whatever load impedance might be connected between Oa and 
Ob). 
Additional Comments re Initial Embodiment 
(a) As long as the time-length of the saturation-time of the saturable 
current-transformers remains equal to or longer than the time-length of 
one of the sinusoidal half-waves of voltage, the net inversion frequency 
will not be affected by the addition or removal of a load impedance, such 
as LD of FIG. 1, regardless of the magnitude of the net reactive impedance 
thereby added to or subtracted from the L-C parallel circuit. 
(b) The magnitude of the Zener voltage of Zener diode Z is chosen such as 
to be somewhat higher than the maximum magnitude of the peak voltage of 
the sinusoidal half-waves of voltage present across the inverter's output 
terminals Oa and Ob. That way, the Zener diode will not interfere with 
normal operation of the inverter; yet, it will prevent the magnitude of 
the peak voltages of the sinusoidal half-waves from substantially 
exceeding the normally occurring maximum magnitudes. Without the Zener 
diode, for various transient reasons (such as due to the sudden removal of 
a load) the magnitude of the peak voltages of the sinusoidal half-waves 
would occasionally become substantially larger than the normally occurring 
maximum magnitudes; and that would either cause transistor destruction, or 
it would necessitate the use of very special transistors of exceptionally 
high voltage capabilities. 
(c) Inductor L is center-tapped; which, in effect, provides for a 
center-tap between the inverter's output terminals Oa and Ob. This 
center-tap is grounded. In many applications, particularly in the case of 
fluorescent lamp ballasts, it is very valuable to have the output 
referenced to ground. 
(d) Inductor L may be integrally combined with a center-tapped 
auto-transformer; in which case the output voltage can readily be provided 
at any desired magnitude, while maintaining a ground-connected center-tap. 
(e) Inductor means IM may consist of two entirely independent 
inductors--with one inductor located in each leg of the power supply. In 
fact, it is even acceptable under some circumstances to use but a single 
inductor in just one leg of the power supply; in which case, however, it 
would not be possible to connect the output's center-tap with the power 
supply's center-tap. 
(f) It is not necessary to power the inverter of FIG. 1 from a voltage 
doubler. However, doing so provides for the advantage in many situations 
of being able to reference the center-tap of the inverter's output with 
one of the legs of the power line. 
(g) The inverter of FIG. 1 must be triggered into oscillation. This 
triggering may be accomplished by way of providing a special trigger 
winding on each of the feedback current-transformers, and then to 
discharge a capacitor through these trigger windings. This may be done 
automatically with an arrangement consisting of a capacitor-resistor 
combination connected between B+ and B-, and a Diac for discharging the 
capacitor through the trigger windings. 
(h) Finally, it is noted that the average absolute magnitude of the AC 
voltage appearing between inverter output terminals Oa and Ob must be 
substantially equal to the magnitude of the DC voltage provided from 
across the two series-connected energy-storing capacitors C1 and C2. 
Or, stated differently, in the circuit of FIG. 1, if the inverter's AC 
output voltage as provided between terminals Oa and Ob were to be 
rectified in a full-wave rectifier, the average magnitude of the DC 
voltage obtained from this full-wave rectifier would have to be 
substantially equal to the magnitude of the DC voltage supplied from the 
DC output of the rectifier/filter combination consisting of R1, R2, C1 and 
C2. 
This relationship would have to exist substantially regardless of the 
nature of the load connected between the inverter's output terminals. 
(i) Although the full-bridge inverter circuit of FIG. 1 may be designed to 
invert at any one of a wide range of frequencies, in the preferred 
embodiment the inversion frequency is approximately 30 kHz. Thus, the 
time-length of the interval between point X and point Y of FIG. 2a is 
about 33 micro-seconds. 
(j) The waveforms of FIG. 2 depict the voltage present between output 
terminals Oa and Ob under different operating conditions. Of course, the 
voltage present between Oa and inverter reference terminal IRT is equal to 
half the voltage present between terminals Oa and Ob. 
(k) Due to the balanced nature of the inverter and its DC power supply, 
with reference to any one of the terminals of filter capacitors C1 and C2, 
any high frequency voltage present at inverter reference terminal 
IRT--even if it were not connected with ground--would have negligible 
magnitude. 
(l) The primary windings of saturable current transformers SCT1 and SCT2 
have fewer turns than do the secondary windings. Typically, the 
transistors operate with a 1:4 primary-to-secondary turns ratio; which 
corresponds to a forced current gain of four. At that turns ratio, the 
magnitude of the voltage developing across the primary winding of each of 
the saturable current transformers is only one fourth of the magnitude of 
the base-emitter voltage; which, of course, is only about 0.8 Volt. 
In other words, the magnitude of the voltage developing across the primary 
winding of each staturable transformer is only about 0.2 Volt; which, of 
course, represents a magnitude that is totally negligible in comparisn 
with the magnitude of the voltage developing between output terminals Oa 
and Ob. 
Thus, the voltage at terminal Ob is substantially equal to the voltage at 
terminal Jb; and the voltage at terminal 0a is substantially equal to the 
voltage at terminal Ja. 
DESCRIPTION OF THE SECOND EMBODIMENT 
Details of Construction of Second Embodiment 
FIG. 3, which consists of FIGS. 3A and 3B, which should be viewed together, 
is a schematic diagram of the second embodiment of the invention. 
In FIG. 3, an ordinary electric utility power line is represented by a 
source S, whose source terminals ST1 and ST2 are connected with a pair of 
power input terminals PIT1 and PIT2 of a bridge rectifier BR; which bridge 
rectifier BR has two DC output terminals DC- and DC+. A high-frequency 
filtering capacitor HFFC is connected between the DC- terminal and the DC+ 
terminal. 
A first winding Le1 of energy-storing inductor Le is connected between the 
DC+ terminal and a DC+ bus; which DC+ bus is connected with a B+ bus by 
way of a high-speed rectifier HSR1. A second winding Le2 of energy-storing 
inductor Le is connected between the DC- terminal and a DC- bus; which DC- 
bus is connected directly with a B- bus. 1B- bus. Windings Le1 and Le2 are 
two mutually coupled windings wound on a single magnetic structure. 
A pre-converter PCIC is an integrated circuit (Motorola MC 34262) and has 
eight terminals 1-8. Terminal 8 is connected with an A+ bus; which A+ bus 
is also connected with the cathode of a diode Dp1, whose anode is 
connected with a tap T on winding Le2. A resistor Rp1 is connected between 
tap T and terminal 5 of PCIC. A filter capacitor FCp1 is connected between 
the A+ bus and the DC- bus; and a filter capacitor FCp2 is connected 
between the B- bus and the B+ bus. 
A resistor Rn2 is connected between the DC+ bus and a terminal 3 of the 
PCIC; while a resistor Rn3 and a capacitor Cp2 are parallel-connected 
between terminal 3 and the DC- bus. 
A capacitor Cp3 is connected between terminal 2 of the PCIC and the A+ bus; 
while terminal 6 is connected with the DC- bus. A resistor Rp4 is 
connected between the B+ bus and terminal 1; and a resistor Rp4 is 
connected between terminal 1 and the B- bus. Terminal 4 is connected with 
the DC- bus via a resistor Rp6. 
A field effect transistor FETp is connected: (i) with its source terminal 
to terminal 4 of the PCIC, (ii) with its drain terminal to the DC+ bus, 
and (iii) with its gate terminal to terminal 7 of the PCIC. 
The B+ bus is connected with a BI+ bus via a first winding EIw1 of an 
energy-storing inductor EI; while the B- bus is connected with a BI- bus 
via a second winding EIw2 of energy-storing inductor EI. Windings EIw1 and 
EIw2 are two mutually coupled windings on a single magnetic structure. 
Each of field effect transistors FET1a and FET2a is connected with its 
drain terminal to the BI+ bus; and each of field effect transistors FET1b 
and FET2b is connected with its source terminal to the BI- bus. The source 
terminals of transistors FET1a and FET1b are connected with junctions J1 
and J2, respectively; as are also the drain terminals of transistors FET1b 
and FET2b, as well as an AC1 bus and an AC2 bus, all respectively. 
A tank inductor TI is connected between junction J1 and J2; which tank 
inductor has four auxiliary windings coupled thereto: AW1a, AW1b, AW2a, 
and AW2b; which windings are connected between the gate and source 
terminals of transistors FET1a, FET1b, FET2a, and FET2b, all respectively. 
A first tank capacitor TCab is connected between the BI- bus and the BI+ 
bus; while a second tank capacitor TC12 is connected between junctions J1 
and J2 (i.e., between the AC1 bus and the AC2 bus). A series-combination 
SC of a first current-limiting capacitor CLCx and a first instant-start 
fluorescent lamp ISFLx is connected between the AC1 bus and the AC2 bus. 
A resistor Rt1 is connected between the BI+ bus and a junction Jt; a 
capacitor Ct1 is connected between junction Jt and the BI- bus; and a Diac 
Dt1 is connected between junction Jt and the anode of a diode Dt2, whose 
cathode is connected with the gate terminal of transistor FET2b. 
Details of Operation of Second Embodiment 
The operation of the second embodiment of FIG. 3 may best be understood by 
making reference to the voltage and current waveforms of FIG. 4; wherein: 
Waveform (a) represents the high-frequency voltage existing between the AC1 
bus and the AC2 bus under a condition of no load (i.e., with fluorescent 
lamp ISFLx removed); 
Waveform (b) represents the high-frequency voltage existing between Earth 
Ground and the AC1 bus under no-load condition; 
Waveform (c) represents the high-frequency voltage existing between Earth 
Ground and the AC2 bus under no-load condition; 
Waveform (d) represents the voltage existing between the BI- bus and the 
gate of transistor FET1b (i.e., the gate-source drive voltage of 
transistor FET1b) under no-load condition; 
Waveform (e) represents the voltage existing between the BI- bus and the 
BI+ bus under no-load condition; 
Waveform (f) represents the current flowing through transistor FET1b under 
no-load condition; 
Waveform (g) represents the AC voltage existing between the B- bus (or the 
B+ bus) and junction J1 (or J2) under a condition of no load; which is to 
say: disregarding any DC voltage component, waveform (d) represents the 
actual voltage existing between the B- bus (or the B+ bus) and junction J1 
(or J2) under no-load condition; 
Waveform (h) represents the voltage existing between the B- bus and the BI- 
bus under no-load condition; 
Waveform (i) represents the current flowing between the B- bus and the BI- 
bus (or: between the BI+ bus and the B+ bus) under no-load condition; 
Waveform (j) represents the high-frequency voltage existing between the AC1 
bus and the AC2 bus under a condition of part load (i.e., with fluorescent 
lamp ISFLx connected and functioning); 
Waveform (k) represents the high-frequency voltage existing between Earth 
Ground and the AC1 bus under part-load condition; 
Waveform (l) represents the high-frequency voltage existing between Earth 
Ground and the AC2 bus under part-load condition; 
Waveform (m) represents the voltage existing between the BI- bus and the 
gate of transistor FET1b (i.e., the gate-source drive voltage of 
transistor FET1b) under part-load condition; 
Waveform (n) represents the voltage existing between the BI- bus and the 
BI+ bus under part-load condition 
Waveform (o) represents the current flowing through transistor FET1b under 
part-load condition; 
Waveform (p) represents the AC voltage existing between the B- bus (or the 
B+ bus) and junction J1 (or J2) under part-load condition; which is to 
say: disregarding any DC voltage component, waveform (p) represents the 
actual voltage existing between the B- bus (or the B+ bus) and junction J1 
(or J2) under part-load condition; 
Waveform (q) represents the current flowing between the B- bus and the BI- 
bus (or: between the BI+ bus and the B+ bus) under part-load condition; 
Waveform (r) represents the full-wave-rectified power line voltage existing 
between the DC- terminal and the DC+ terminal under part-load condition; 
Waveform (s) represents the voltage existing between the DC+ terminal and 
the DC+ bus under part-load condition; 
Waveform (t) represents the voltage existing between the DC- terminal and 
the DC- bus under part-load condition; 
With reference to the waveforms of FIG. 4, the operation of the embodiment 
of FIG. 3 may now be described as follows. 
As illustrated by waveform (r), full-wave rectification of the AC power 
line voltage from source S results in a pulsating (i.e., unfiltered) 
unidirectional voltage existing between the DC- terminal and the DC+ 
terminal. This unfiltered unidirectional voltage is supplied to a 
pre-converter circuit; which, except for using a split winding on its 
energy-storing inductor L, functions in a substantially ordinary manner, 
thereby to provide a filtered and regulated DC supply voltage between the 
B- bus and the B+ bus. {The complete assembly between the power line input 
terminals (PIT1, PIT2) and the DC supply voltage output terminals (i.e., 
the B- bus and the B+ bus) is referred-to as the Pre-Converter Circuit.} 
The fact that energy-storing inductor L has two windings provides for two 
auxiliary benefits. 
One auxiliary benefit is that of causing less electromagnetic interference 
(EMI) to be conducted from the Pre-Converter Circuit to the power line 
conductors; which benefit results for the reason that--just like any 
ordinary two-winding EMI choke--the split-winding energy-storing inductor 
L provides both common-mode and differential-mode attentuation of the EMI 
signals (unintentionally) generated in the Pre-Converter Circuit (and/or 
in the Bridge Inverter Circuit). 
The other auxiliary benefit is that of maintaining symmetry of voltages and 
currents with respect to each of the power line supply terminals (ST1, 
ST2) (as well as with respect to earth ground); which symmetry facilitates 
the provision of a balanced AC output voltage from the AC output terminals 
of the Bridge Inverter Circuit (i.e., the AC1 bus and the AC2 bus). 
As a consequence of the split-winding feature, the voltage existing between 
the DC+ terminal and the DC+ bus will be as shown by waveform (s), and the 
voltage existing between the DC- terminal and the DC- bus will be as shown 
by waveform (t). The sum of these two voltages would be equal to the 
voltage that would exist across the winding of an ordinary single-winding 
energy-storing inductor as used in an ordinary pre-converter circuit. 
The filtered and regulated DC supply voltage from the Pre-Converter Circuit 
(which exists between the B- bus and the B+ bus) is provided to the Bridge 
Inverter Circuit, where it is applied between the BI+ bus and the BI- bus 
by way of windings EIw2 and EIw2, respectively. 
Windings EIw1 and EIw2 are wound on a single magnetic structure (e.g., 
ferrite core) in a mutually coupled manner. Thus, they constitute a single 
energy-storing inductive entity; and, except for voltage and current 
symmetry considerations, the two windings could just as well have been 
combined into a single winding. 
With the DC supply voltage applied between the BI- bus and the BI+ bus, the 
Bridge Inverter Circuit is triggered into self-oscillation, with the 
triggering being effected by elements Ri1, Ri2, Ct1, Dt1 and Dt2. 
After triggering, the basic bridge inverter per se (i.e., the circuit 
assembly consisting of principal elements FET1a, FET1b, FET2a, FET2b, and 
TI) will self-oscillate by way of the positive feedback provided via the 
auxiliary windings on tank-inductor TI (i.e., auxiliary windings AW1a, 
AW1b, AW2a and AW2b). 
Although the average magnitude of the DC voltage present between the BI- 
bus and the BI+ bus must be equal to that of the DC supply voltage (as 
provided between the B-bus and the B+ bus), the instantaneous magnitude of 
this DC voltage will vary in synchronism with the oscillations of the 
bridge inverter. 
The effect of tank-capacitors TCa and TC12 is that of making the waveform 
of the alternating voltage provided between the bridge inverter's output 
terminals (i.e., J1 and J2) sinusoidal, with the frequency of oscillation 
being determined by the resonant interaction between these tank-capacitors 
and tank-inductor TI. 
With the fluorescent lamp (ISFLx) non-connected (i.e., when supplying no 
output power), some of the voltage and current waveforms associated with 
the self-oscillating Bridge Inverter Circuit are as shown by waveforms (a) 
through (i) of FIG. 4. 
In particular, it is noted that the high-frequency voltage existing between 
Earth Ground and the AC1 bus is equal in magnitude but opposite in phase 
as compared with the high-frequency voltage existing between Earth Ground 
and the AC2 bus. 
Also, it is noted that the alternating voltage existing between the B- bus 
and junction J1 is equal to the high-frequency voltage existing between 
Earth Ground and the AC1 bus. Of course, the alternating voltage existing 
between the B+ bus and junction J1 is substantially identical to the 
alternating voltage existing between the B- bus and junction J1. 
Since the voltage existing between the AC1 bus and the AC2 bus is 
sinusoidal {see waveforms (a) and (j)}, and since this sinusoidal voltage 
is the same as that existing across tank-inductor TI, the waveform of each 
of the gate-source drive voltages provided from auxiliary windings AW1a, 
AW1b, AW2a and AW2b will also be sinusoidal {see waveforms (d) and (m)}. 
While it is unusual in a power-handling inverter to operate FET's with a 
sinusoidal gate-source drive voltage (as opposed to the usual squarewave 
gate-source drive voltage), such may indeed be done without incurring 
excessive power losses while at the same time averting damage to the 
FET's. 
To minimize switching power losses, it is necessary that the peak magnitude 
of the sinusoidal gate-source drive voltage be significantly higher than 
the magnitude merely required to cause the FET to fully enter its 
ON-state; which means that the peak magnitude of a sinusoidal gate-source 
drive voltage must be significantly higher than the peak magnitude of a 
squarewave gate-source drive voltage (which is what is conventionally used 
for driving FET's in a power-handling inverter). In particular, in the 
Bridge Inverter Circuit of FIG. 3, the peak magnitude of the sinusoidal 
drive voltage provided to the gate-source inputs of each of the FET's is 
about 40 Volt; which is higher by a factor of four at compared with the 
peak magnitude required when a squarewave gate-source drive voltage is 
used. 
While a peak voltage of 40 Volt is higher than the peak gate-source voltage 
normally considered permissible for power FET's, is indeed acceptable 
(i.e., without incurring damaging effects) with certain types of FET's, 
such as FET's of type IRF 721 from International Rectifier Corporation, El 
Segundo, Calif. With a sinusoidal drive voltage of 40 Volt peak magnitude, 
total power dissipation in the FET's in the Bridge Inverter Circuit was 
indeed acceptably low. 
With the fluorescent lamp (ISFLx) connected (i.e., when supplying a 
moderate amount of output power), some of the voltage and current 
waveforms associated with the self-oscillating Bridge Inverter Circuit of 
FIG. 3 are as shown by waveforms (j) through (q) of FIG. 4. 
It is noted that the frequency of the all the waveforms associated with the 
partially loaded condition is substantially lower than that of the no-load 
condition. This is so for the reason that, when the lamp is connected and 
operating, the voltage across it is very small (only about 150 Volt RMS) 
compared with the magnitude of the voltage present across the 
lamp-capacitor series-combination (about 500 Volt RMS); which means that 
this series-combination constitutes substantial additional capacitive 
loading on the inverter's basic tank-circuit (i.e., tank-inductor TI as 
combined with tank-capacitors TCa and TC12), thereby reducing the natural 
resonance frequency. 
Additional Comments re Second Embodiment 
(aa) In some situations, to provide for affirmative triggering of the 
Bridge Inverter Circuit of FIG. 3, a resistor may be connected between the 
BI+ bus and junction J1. 
(ab) In most situations, tank-capacitor TC12 may safely be eliminated; in 
which case tank-capacitor TCa should be increased in capacitance 
sufficiently to compensate for any undesirable increase in (no-load) 
oscillating frequency due to the removal of TC12. 
(ac) As is the case with any ordinary electric utility power line, the 
power line conductors are electrically connected with earth ground, either 
directly or by way of a low-resistance path. In case of the circuit 
arrangement of FIG. 3, this connection is indicated by one of the power 
line conductors having electrical connection with Earth Ground. 
(ad) With reference to waveform (a) of FIG. 4, as well as with reference to 
waveform (d), it is noted that the waveform of the inverter output voltage 
under no-load condition is sinusoidal except for a small portion of the 
total wave cycle. More particularly, during a very brief period at or near 
each cross-over point of the voltage wave, instead of having the usual 
slope associated with a sinusoidal wave, the wave has a notably steeper 
slope. 
This slope-steepening is due to the fact that, during this very brief 
period, none of the four transistors is fully in its ON-state; which means 
that tank-capacitor TCab is, during this very brief period, at least 
partly disconnected from tank-inductor TI; which, in turn, causes the 
voltage across tank-conductor TI to rise at a higher rate; which higher 
rate is now limited by tank-capacitor TC12 only, as opposed to being 
limited by both tank-capacitors TC12 and TCab. 
Of course, the slope-steepening effect on the waveform of the inverter's 
output voltage is directly reflected in the waveform of the gate-source 
drive voltage of each FET. 
As indicated by waveforms (j) and (m), the slope-steepening effect is less 
pronounced under loaded conditions. 
(ae) Since the fluorescent lamp (ISFLx) is ballasted by way of a capacitor, 
the slope-steepening effect referred-to in section (ad) above has the 
effect of causing an added spike or pulse in the instantaneous magnitude 
of the current provided to the fluorescent lamp; which spike or pulse 
occurs at or near each absolute-magnitude-peak of the otherwise 
substantially sinusoidal lamp current. 
(af) With reference to FIG. 3, it should be understood that additional 
lamp-capacitor series-combinations may be connected between the AC1 bus 
and the AC2 bus (i.e., across the AC rails). However, the more such 
series-combinations so connected, the lower will be the frequency of 
oscillation of the inverter and thus the lower will be the frequency of 
the AC voltage provided between the AC1 bus and the AC2 bus; which 
correspondingly results in a lower magnitude of the current delivered 
through the series capacitors (i.e., the ballasting capacitors) to each 
lamp. 
(ag) It is emphasized that waveforms (b), (c), (k) and (l) of FIG. 4 
represent the waveforms of the high-frequency componets of the actual 
voltages existing between Earth Ground and the AC1/AC2 buses under no-load 
and part-load condittions. However, it is important to realize that the 
waveforms of these actual voltages also include low-frequency components; 
which low-frequency components are not shown in the waveforms of FIG. 4. 
In situations where the presence of such low-frequency components are found 
to be of concern with respect to passing the U.L. shock-hazard safety 
requirements (e.g., the so-called U.L Pin Test), it is noted that a 
high-pass filter (e.g., in the form a low-frequency blocking capacitor in 
series-connection with each of the AC1/AC2 buses) will mitigate such 
shock-hazard possibilites. 
DESCRIPTION OF AN ALTERNATIVE SECOND EMBODIMENT 
Details of Construction of Alternative Second Embodiment 
FIG. 5, which consists of FIGS. 5A and 5B, which should be viewed together 
is a schematic diagram of an alternative second embodiment of the present 
invention. 
The arrangement of FIG. 5 is identical to that of FIG. 3 except for the 
following modifications. 
Tank capacitor TC12 has been removed. 
Elements Ri1, Ri2, Ct1, Dt1 and Dt2 have been removed. 
A resistor R1a is connected between the drain terminal and the gate 
terminal of transistor FET1a; a resistor R2b is connected between the 
drain terminal and the gate terminal of transistor FET2b. 
Zener diodes Z1a, Z1b, Z2a, Z2b are interposed between windings AW1a, AW1b, 
AW2a, AW2b and the gate terminals of transistors FET1a, FET1b, FET2a, 
FET2b, all respectively and in each case with the cathode of the Zener 
diode being connected with its associated gate terminal. 
Winding EIw2 of inductor EI has been relocated such as to be connected 
directly in series with winding EIw1, thereby having both these windings 
series-connected between the B+ bus and the BI+ bus, thereby also leaving 
the B- bus connected directly with the BI- bus. The mid-point of the 
series-combined windings EIw1 and EIw2 is identified as center-tap EIct. 
A resistor Rc1 has been inserted in series with the AC1 bus in such manner 
that whatever current flows from the AC1 bus must flow through resistor 
Rc1. Parallel-connected with resistor Rc1 is the primary winding CTp of a 
control transformer CT, whose secondary winding CTs is connected between 
the B- bus and the cathode of a diode Dc1, whose anode is connected with 
the B- bus by way of a capacitor Cc1. 
An auxiliary winding AWc on tank inductor TI is connected with one of its 
terminals to the B- bus; the other one of its terminals being connected 
with the drain terminal of a field effect transistor FETc through a 
tank-capacitor TCc. 
The source terminal of transistor FETc is connected with the B- bus; and 
the gate terminal of transistor FETc is connected with output terminal 
OTc2 of inverter Ic2 of a HEX Inverter HEXI. Input terminal ITc2 of 
inverter Ic2 is connected with output terminal OTc1 of inverter Ic1 of HEX 
inverter HEXI. Input terminal ITc1 of inverter Ic1 is connected with 
output terminal OTc2 of inverter Ic2 by way of a feedback capacitor Cc2. 
A resistor Rc2 is connected between output terminal OTc1 and the cathode of 
a diode Dc2; a resistor Rc3 is connected between the A+ bus and input 
terminal ITc1 of inverter Ic1; while a resistor Rc4 is connected between 
input terminal ITc1 of inverter Ic1 and the anode of diode Dc1. Details of 
Operation of Alternative Second Embodiment 
The operation of the alternative second embodiment of FIG. 5--to the extent 
that it differs from the operation of the second embodiment of FIG. 3--may 
best be understood by making reference to the voltage and/or current 
waveforms of FIG. 6; wherein: 
Waveform (aa) represents the high-frequency voltage existing between the 
AC1 bus and the AC2 bus under a condition of less-than-full load (i.e., 
with fewer than all intended lamp-capacitor series-combinations--one of 
which would be SCx--connected between the AC1/AC2 buses). 
Waveform (ab) represents the high-frequency current flowing through lamp 
ISFLx under the condition of less-than-full load. 
Waveform (ac) represents the high-frequency voltage existing between the 
AC1 bus and the AC2 bus under a condition of full load (i.e., with all 
intended lamp-capacitor series-combinations connected between the AC1/AC2 
buses). 
Waveform (ad) represents the high-frequency current flowing through lamp 
ISFLx under the condition of full load. 
Waveform (ae) represents the voltage present between the BI- bus and the 
drain terminal of transistor FET1b under a condition of less-than-full 
load. 
Waveform (af) represents the voltage present between the BI- bus and the 
drain terminal of transistor FET1b under a condition of full load. 
Now, with reference to the waveforms of FIGS. 4 and 6, the operation of the 
embodiment of FIG. 5 may be described as follows. 
The Zener voltage of each of the Zener diodes (Z1a, Z1b, Z2a, Z2b) has been 
chosen such as to be slightly higher in magnitude than that of the gate 
voltage at which each of the transistors (FET1a, FET1b, FET2a, FET2b) 
starts conducting current between its source and drain. As a result, each 
transistor switches OFF a brief period later than it would have switched 
OFF without the Zener diodes; which, as compared with the arrangement of 
FIG. 3, leads to a reduction in the duration of the short period of time 
during which none of the transistors conduct. 
As a bottom-line result--comparing exemplary waveform (a) of FIG. 4 with 
exemplary waveform (aa) of FIG. 6--the degree of slope-steepening at the 
cross-over points of the inverter's otherwise sinusoidal output voltage 
has been minimized; which, in turn, leads to a lamp current with better 
crest-factor as compared with the lamp current crest-factor associated 
with the arrangement of FIG. 3. 
Also as a result of the Zener diodes, the bridge inverter can be biased 
(e.g., with resistors R1a and R2b) so as to cause two of the transistors 
to conduct, thereby to cause the inverter to self-start and thereby to 
eliminate the need for the Diac-type trigger circuit of FIG. 3. 
Now, with particular reference to FIG. 5 (the part showing the Bridge 
Inverter Circuit) and waveforms (aa) & (ab) versus waveforms (ac) & (ad) 
of FIG. 6, prior to the fluorescent lamps having ignited, transistor FETc 
exists in its ON-state; which is to say that it exists in its fully 
conductive state. This is so because no current flows through resistor 
Rc1; which means that no negative voltage is present at the anode of diode 
Dc1; which means that input terminal ITc1 of inverter Ic1 will (via 
resistor Rc3) be pulled to a potential sufficiently positive to cause the 
two series-connected inverters IC1 and IC2 (via regenerative action 
resulting from the positive feedback supplied via capacitor Cc2) to enter 
a state whereby output terminal OTc2 goes positive all the way to the 
level of the A+ bus, thereby causing transistor FETc to enter its 
ON-state. Thereafter, until the lamps ignite, input terminal ITc1 remains 
positive to a degree sufficient to maintain output terminal OTc2 positive. 
With transistor FETc in its ON-state, tank capacitor TCc is in effect 
connected in parallel with tank-capacitors TCa and TC12, thereby causing 
the natural oscillating frequency of the bridge inverter to be lower by a 
substantial factor compared with what it would be with transistor FETc in 
its OFF-state. 
As soon as the lamps ignite, current will flow through resistor Rc1; which 
will give rise to a negative voltage developing at the anode of diode Dc1; 
which, if that negative voltage be of sufficient magnitude, will cause the 
magnitude of the voltage present at input terminal ITc1 to decrease in 
magnitude sufficiently to cause the two series-connected inverters IC1 and 
IC2 (again via regenerative action) to cause the magnitude of the voltage 
at output terminal OTc2 to fall to a level sufficiently low to render 
transistor FETc nonconductive. 
In fact, when all lamps are connected and in operation, the magnitude of 
the negative voltage developed at the anode of diode Dc1 is just 
sufficient to cause the two series-connected inverters (Ic1, IC2) to 
regenerate, thereby to cause transistor FETc to enter its OFF-state, 
thereby to remove tank-capacitor TCc from the tank-inductor, thereby to 
cause the frequency of the inverter's AC output voltage (i.e., the AC 
voltage provided between the AC1 bus and the AC2 bus) to increase 
substantially; which, if the magnitude of this AC output voltage were to 
have remained the same, would have cuased the magnitude of the lamp 
current to increase in proportion to the increase in frequency. 
However, by action of diode Dc2 and resistor Rc2, the magnitude of the DC 
supply voltage will decrease simultaneously with the increase in frequency 
of the inverter's AC output voltage. This is so because output terminal 
OTc1 assumes a potential obverse to that of output terminal OTc2; which 
means that: (i) whenever transistor FETc is in its ON-state, output 
terminal OTc1 is at a potential close to that of the B- bus; which means 
that resistor Rc2 is in effect parallel-connected with resistor Rp5; which 
therefore causes the magnitude of the DC supply voltage to be regulated to 
a level substantially higher than the level to which it would be regulated 
without resistor Rc2 being so parallel-connected; and (ii) whenever 
transistor FETc is in its OFF-state, output terminal OTc1 is at a 
potential close to that of the A+ bus; which means that resistor Rc2 is 
now not parallel-connected with resistor Rp5; which means that the 
magnitude of the DC supply voltage be regulated at a level substantially 
lower than the level to which it be regulated when transistor FETc is in 
its ON-state. 
Thus, as illustrated by the waveforms of FIG. 6: (i) whenever less than 
full load current is being drawn from the AC1 bus, the AC output voltage 
(i.e., the AC voltage provided between the AC1 bus and the AC2 bus) will 
have a relatively high RMS magnitude and a relatively low frequency; and 
(ii) whenever full load current is being drawn from the AC1 bus, the AC 
output voltage will have a relatively low RMS magnitude and a relatively 
high frequency. 
Thus, if one or more lamps were to be removed during normal operation--such 
as would occur during an ordinary re-lamping procedure--the AC output 
voltage would increase in RMS magnitude but would decrease in frequency, 
thereby keeping the remaining lamp(s) properly powered. Yet, upon 
replacing all lamps (thereby re-establishing full load), the AC voltage 
would decrease in RMS magnitude while at the same time increasing in 
frequency. 
An important reason for reducing the RMS magnitude of the AC output voltage 
when the ballast is operating at full power level is that of efficiency. 
For given sizes and/or ratings of components, the pre-converter (as well 
as the inverter) operates at higher efficiency when the magnitude of the 
DC supply voltage is lower. More particularly, the efficiency of the 
pre-converter increases with a reduction in the ratio between the absolute 
magnitude of the DC supply voltage and the peak absolute magnitude of the 
AC power line voltage. 
For instance, with a given set of component parts, delivering 60 Watt of DC 
power at a DC rail voltage of about 350 Volt requires about 1.0 Watt more 
from a 120 Volt/60 Hz power line than delivering the same amount of DC 
power at a DC rail voltage of only 230 Volt. 
Additional Comments re Alternative Second Embodiment 
(aa) The reason associated with removing tank-capacitor TC12 from the 
embodiment of FIG. 5 relates to two things: 
1. The removal of tank-capacitor TC12 (even if the capacitance of 
tank-capacitor TCa were to be increased to provide for compensation in 
oscillating frequency) simply represents an economic advantage; and 
2. The removal of tank-capacitor TC12 permits easier triggering of the 
inverter, thereby (in cases where the inverter circuit is provided with 
its DC supply voltage from a more-or-less ordinary pre-converter, such as 
is indeed the case in the embodiment of FIG. 5) permitting the removal of 
the trigger circuit consisting of elements Rt1, Ct1, Dt1 and Dt2 in 
exchange for a simpler trigger means connected in circuit between the 
pre-converter circuit and the gate-source terminals of transistor FET1b 
(or transistor FET2b), thereby taking advantage of the start of 
oscillations of transistor FETp to trigger the inverter circuit into 
self-oscillation. 
For instance, triggering of the inverter circuit could be accomplished by 
way of an auxiliary winding on energy-storing inductor Le; which auxiliary 
winding would be coupled between the gate-source terminals of transistor 
FET1b by way of a resistor. 
(ab) The frequency of operation of the inverter circuit of FIG. 3 is about 
22 kHz when fully loaded. Yet, improved efficiency and/or reduced inductor 
sizes would result if it were possible to operate at higher frequencies 
when fully loaded. However, due to certain optical and/or electrical 
interference problems associated with certain commonly used in-building 
electronic control and communications systems (including particularly TV 
remote controls), it is important not to have electronic ballasts operate 
in the frequency range between 34 and 40 kHz (hereinafter the "forbidden 
frequency band"). 
In the embodiment of FIG. 5, due to the removal of tank-capacitor TC12, the 
frequency of operation of the inverter circuit is well in excess of 40 kHz 
when unloaded or partly loaded; yet, at about 32 kHz, it is safely under 
34 kHz when fully loaded. 
With a loaded operating frequency of 32 kHz, energy-storing inductor EI and 
tank-inductor TI can be substantially smaller and lighter-of-weight as 
compared with what would otherwise be required to attain a given 
efficiency level. Or, conversely, at given sizes and weights for the 
inductor elements, the operating efficiency would be substantially 
improved. 
More particularly, the embodiment of FIG. 5 is characterized by operating 
above the forbidden frequency band during no-load and/or part-load 
conditions, while operating below the forbidden frequency band during 
fully loaded conditions. 
In this connection, it is observed that presently available electronic 
ballasts of the so-called parallel-resonant type operate at frequencies of 
about 22 kHz when fully loaded. 
(ac) It should be understood than many of the advantages associated with 
the full-bridge inverter circuit embodiments of FIGS. 3 and 5 may be 
attained as well with half-bridge and/or so-called parallel push-pull 
embodiments. 
(ad) In ordinary electronic ballasts of the half-bridge parallel-resonant 
type--such as sold by Electronic Ballast Technology (EBT), Inc. of 
Torrance, Calif.--the peak magnitude of the voltage existing across each 
of the two inverter transistors is higher than (or at least as high as) 
half of the magnitude of the inverter's DC supply voltage multiplied by pi 
(i.e., 3.14). Thus, with a DC supply voltage of (say) 200 Volt, the peak 
magnitude of the voltage across one of the inverter transistors would 
usually be higher than (but would be at least as high as) 314 Volt. 
In electronic ballasts of the push-pull parallel-resonant type--such as 
sold by Triad-Utrad (a unit of MagneTek, Inc. of Los Angeles, Calif.)--the 
peak magnitude of the voltage existing across each of the two inverter 
transistors is normally higher than (but is at least as high as) the 
magnitude of the inverter's DC supply voltage multiplied by pi (i.e., 
3.14). Thus, with a DC supply voltage of (say) 200 Volt, the peak 
magnitude of the voltage across one of the inverter transistors would be 
at least 628 Volt. 
In an electronic ballast built in accordance with the circuit arrangement 
of FIG. 1 herein, and as long as operating with the waveforms marked (a), 
(b) or (c) of FIG. 2 herein, the peak magnitude of the voltage across each 
one of the four inverter transistors will be higher than (or at least as 
high as) half of the magnitude of the inverter's DC supply voltage 
multiplied by pi (i.e., 3.14). Thus, with a DC supply voltage of (say) 200 
Volt, the peak magnitude of the voltage across one of the inverter 
transistors in the circuit of FIG. 1--when operating with waveforms 
(a)-(c)--would be at least 314 Volt. 
In an electronic ballast built in accordance with the circuit arrangement 
of FIG. 1 herein, and as long as operating with the waveform marked (d) of 
FIG. 2 herein, the peak magnitude of the voltage across each one of the 
four inverter transistors will be lower than half of the magnitude of the 
inverter's DC supply voltage multiplied by pi (i.e., 3.14). Thus, with a 
DC supply voltage of (say) 200 Volt, the peak magnitude of the voltage 
across one of the inverter transistors in the circuit of FIG. 1--when 
operating with waveform (d)--would be less than 314 Volt. 
In an electronic ballast built in accordance with the circuit arrangement 
of FIGS. 3 or 5 herein, the peak magnitude of the voltage across each one 
of the four inverter transistors will be lower than half of the magnitude 
of the inverter's DC supply voltage multiplied by pi (i.e., 3.14). Thus, 
with a DC supply voltage of (say) 200 Volt, the peak magnitude of the 
voltage across one of the inverter transistors in the circuit of FIG. 3 
(or FIG. 5) would be less than 314 Volt. 
In an electronic ballast built in accordance with the principles of the 
circuit arrangements of FIGS. 3 or 5 herein--even if using a half-bridge 
configuration instead of the illustrated full-bridge configuration--the 
peak magnitude of the voltage across each one of the two half-bridge 
inverter transistors would be lower than half of the magnitude of the 
inverter's DC supply voltage multiplied by pi (i.e., 3.14). Thus, with a 
DC supply voltage of (say) 200 Volt, the peak magnitude of the voltage 
across one of the two half-bridge inverter transistors would then be less 
than 314 Volt. 
In an electronic ballast built in accordance with the principles of the 
circuit arrangements of FIGS. 3 or 5 herein--even if using a push-pull 
configuration instead of the illustrated full-bridge configuration--the 
peak magnitude of the voltage across each one of the two push-pull 
inverter transistors would be lower than the magnitude of the inverter's 
DC supply voltage multiplied by pi (i.e., 3.14). Thus, with a DC supply 
voltage of (say) 200 Volt, the peak magnitude of the voltage across one of 
the two push-pull inverter transistors would then be less than 628 Volt. 
(ae) The reason why--for a given circuit topography and a given magnitude 
of DC supply voltage--the peak magnitude of the voltage existing across 
each transistor in the inverters of ordinary parallel-resonant-type 
electronic ballasts is higher than the peak magnitude of the voltage 
existing across each transistor in the inverter of an electronic ballast 
based on the parallel-resonant principles of the embodiments of FIGS. 3 
and 5 herein is a result of the following basic difference: in the 
inverters of ordinary parallel-resonant electronic ballasts, no provision 
has been provided whereby--at least for a very brief period--none of the 
inverter's switching transistors is permitted to exists in its switched-ON 
or conductive state. 
That is, in ordinary parallel-resonant electronic ballasts, usual practice 
is for one transistor to be switched OFF only after its obverse transistor 
has been switched ON {thereby having a situation where--for a brief period 
each half-cycle--both of two obverse (i.e., alternatingly switched) 
transistors are ON at the same time}; whereas, in the inverter circuit of 
FIGS. 3 and 5, provisions are made whereby one of the transistor is indeed 
switched OFF a short period before its obverse transistor has been 
switched ON, thereby providing for a situation where--at least for a very 
brief period of time--not one of a pair of obverse transistors (e.g., 
FET1b and FET2a) exists in a state of being switched ON. 
(af) With reference to FIGS. 3 and 5, in some cases it may be non-feasible 
to provide between inverter output terminals J1 and J2 an AC voltage of 
the exact RMS magnitude required to exist between the AC1 bus and the AC2 
bus for proper lamp ignition and operation. In such cases, an 
auto-transformer approach may be used to increase or decrease the RMS 
magnitude of the AC voltage provided between the AC1/AC2 buses. That is, 
tank-inductor TI may be integrally combined with an auto-transformer 
without having to add a separate transformer means. 
(ag) In the bridge inverter circuits of FIGS. 3 and 5, the drive voltage 
provided between the gate-source terminals of each of transistors FET1a, 
FET1b, FET2a and FET2b--see waveform (d) of FIG. 4--is of substantially 
sinusoidal waveform and of a peak magnitude substantially higher than 
what's just required to cause each transistor to enter its fully 
conductive state. 
Typically, the magnitude of the gate-source voltage required for causing a 
field effect transistor (such as FET1a, FET1b, FET2a and FET2b) to enter 
is full-conduction state (i.e., its full-ON state) is no higher than about 
10 Volt; which means that if a squarewave-shaped drive voltage had been 
used for driving these FET's, its peak magnitude would not have had to be 
higher than about 10 Volt. However, since the FET's in the bridge inverter 
circuit arrangements of FIGS. 3 and 5 are provided with a substantially 
sinusoidally-shaped drive voltage, it is clear that the peak magnitude of 
this drive voltage has to be higher than 10 Volt. 
In different implementations of the circuits of FIG. 3, sinusoidally-shaped 
base-source drive voltages of peak magnitudes from as low as 20 Volt to as 
high as 40 Volt have been successfully used. Except for possible long term 
detrimental consequences with respect to FET operating life, the higher 
peak magnitudes are preferable because of correspondingly (though not 
proportionally) better switching efficiency and correspondingly (though 
not proportionally) lower lamp current crest factor. 
With respect to the arrangement of FIG. 3, and with further reference to 
waveform (ab) of FIG. 6, the magnitude of the bumps or pulses present at 
or near the peaks of each wave-crest of the lamp current diminishes with 
increased magnitude of gate-source drive voltage, thereby correspondingly 
resulting in an improved (i.e., reduced) lamp current crest factor. 
Also with reference to FIG. 3 and waveform (ab) of FIG. 6, another way of 
reducing the magnitude of the bumps or pulses present at or near the peaks 
of each wave-crest of the lamp current--thereby to improve the 
crest-factor (though not necessarily the switching efficiency)--is that of 
placing a resistor in series with the input to each gate of each FET. 
(ah) To facilitate triggering of the bridge inverter of FIG. 3, a resistor 
Ri1 is connected between the BI+ bus and junction J1. 
(ai) With reference to FIG. 3, to stop continued triggering action after 
the inverter has attained self-sustaining oscillation, the anode of a 
diode may be connected with junction Jt and the cathode of the same diode 
may be connected with the drain terminal of transistor FET2b. 
(aj) With reference to FIG. 5, so as to cause only a small drop in the 
magnitude of the current flowing through resistor Rc1 to cause transistor 
FETc to enter its switched-ON state, conventional hysteresis prevention 
measures may be used. 
(ak) With reference to FIG. 5, the Zener diodes (Z1a, Z1b, Z2a, Z2b) 
provide for an effect quite similar to that of placing a resistor in 
series with each gate of each FET {as discussed in section (ag) above}; 
which is to say that they provide for a reduction in the cross-over 
distortion associated with waveform (a) of FIG. 4, reducing it to a level 
such as indicated by waveform (aa) of FIG. 6. 
(al) In FIG. 5, to permit more leeway in the specifications required of the 
FET's and the Zener diodes, it is advantageous to bias each of transistors 
FET1a and FET2b, not only with a single resistor from gate to drain, but 
also with a resistor from gate to source; which is to say: biasing each of 
those two transistors by way of a voltage divider. 
(am) To protect against electric shock hazard, which otherwise might result 
due to low-frequency power line voltage being present between Earth Ground 
and either the AC1 bus and/or the AC2 bus, a low-frequency blocking 
capacitor may be interposed in series with each of the AC1 bus and the AC2 
bus. 
(an) The ballasting arrangements of FIGS. 3 and 5 may effectively be used 
for Rapid-Start ("R.S.") fluorescent lamps as well; in which case 
low-voltage cathode heating power would be provided by way of auxiliary 
windings on tank-inductor TI. 
To meet the so-called U.L. Pin Test without resorting to using an output 
(or power line) isolation transformer or an active Ground-Fault ("G.F.") 
prevention means, R.S. fluorescent lamps may be parallel-powered from the 
AC output rails (i.e., from the AC1/AC2 buses)--with each R.S. lamp being 
series-connected with a ballast capacitor to form an R.S. Lamp-Capacitor 
series-combination, and with each such series-combination being connected 
directly between the AC buses. Then, as long as the RMS magnitude of the 
AC output voltage (i.e., the AC voltage provided between the AC buses) is 
not much higher than what is required for proper rapid-starting of a 
single R.S. fluorescent lamp, shock-hazard-safe operation will result even 
in the absence of power line isolation transformer or G.F. prevention 
means. 
(ao) Although tank-capacitor TCab is not connected directly in parallel 
across tank-inductor TI, it nevertheless functions as a parallel-connected 
tank-capacitor, thereby making the Bridge Inverter Circuit of FIG. 3 (and 
that of FIG. 5 as well) a parallel-resonant inverter or ballast circuit. 
This is so for the reason that--by way of the alternatingly switched 
bridge transistors--tank-capacitor TCab is commutated in such manner as to 
interact with the tank-inductor as if it were parallel-connected 
therewith. 
(ap) In the Bridge Inverter Circuit of FIGS. 3 and 5, the exact value of 
the inductance of inductor EI is not highly critical to the efficient 
operation of the inverter. Yet, the higher the value of this inductance, 
the lower the amount of high-frequency ripple current that has to be 
handled by filter capacitor FCp2. 
With reference to waveform (q) of FIG. 4, under a partly loaded condition, 
the current flowing through the windings of inductor EI is of a relatively 
high unidirectional magnitude with but a modest amount of high-frequency 
ripple. 
(aq) With reference to the Bridge Inverter Circuits of FIGS. 3 and 5, 
instead of connecting each auxiliary winding on tank-inductor TI (e.g., 
AW1b) directly across the gate-source terminals of transistor FET1b, it 
may in some cases (such as when necessary to limit the peak magnitude of 
the voltage provided across the gate-source terminals) be preferable to 
connect the auxiliary winding thereacross by way of a resistor, while at 
the same time connecting a pair of series-connected back-to-back Zener 
diodes across the gate-source terminals. That way, even when supplied by a 
sinusoidal voltage from the auxiliary winding, the drive voltage presented 
to the gate-source terminals will be closer to a squarewave. 
(ar) With reference to FIGS. 3 and 5, it is emphasized that 
series-combination SCx is merely representative of a plurality of such 
series-combinations which may all be parallel-connected with each other 
between the AC1 bus and the AC2 bus (i.e., across the AC rails). 
(as) With reference to FIG. 5, in situations where Rapid-Start fluorescent 
lamps are to be powered from the Bridge Inverter Circuit, cathode heating 
voltage may advantageously be obtained by way of a small transformer 
having its primary winding connected in parallel with tank-capacitor TCc, 
and each of its secondary windings connected with a cathode. That way, 
cathode heating power would be provided only until all lamps had ignited. 
Thereafter, as soon as tank-capacitor TCc is switched out by way of 
transistor FETc, cathode power would cease to be provided, thereby 
providing for a situation of extra high ballast efficacy factor. 
(at) With referene to FIG. 5, in situations where control of light output 
is desired, the ON/OFF control of transistor FETc can be effectuated by 
way of an external control means istead of by the automatic action shown. 
Thus, for instance, resistor Rc4 may be removed; and control of HEXI--and 
thereby transistor FETc--may be effectuated by an external battery and 
switch. 
Or, the gate terminal of FETc may be removed from HEXI's terminal OTc2 and 
connected instead to an external battery by way of a switch. 
Alternatively, additional tank-capacitors may be switched in/out by way of 
additional transistors--with each additional tank-capacitor being switched 
in/out by its own transistor; and with each tank-capacitor/transistor 
combination being parallel-connected across winding AWc. 
Thus, by switching in/out additional tank-capacitors, the amount of power 
delivered to the gas discharge lamps powered by the parallel-resonant-type 
electronic ballast of FIG. 5 may be controlled over a relatively wide 
range; something which is not possible to accomplish with ordinary 
parallel-resonant-type electronic ballasts. 
Also, the amount of powered delivered to the gas discharge lamps may be 
controlled to an additional degree by controlling the magnitude of the DC 
supply voltage; which can be effectuated by controlling the magnitude of 
the resistance placed in parallel with resistor Rp5. 
In this connection it is important to note that only gas discharge lamps 
with externally heated cathodes (e.g., Rapid-Start fluorescent lamps) are 
suitable for wide-range control of lamp power. 
(au) With reference to section (at) above, it is noted that in situations 
where electrical isolation from the powewr line is desired, external lamp 
power control can be effectuated with one or more tank-capacitors being 
switched in/out across a separate auxiliary winding (e.g., a winding 
labeled AWi) on tank-inductor TI. 
(av) With respect to current flowing through an ordinary transistor, 
forward current is defined as the current flowing between the source 
terminal and the drain terminal in case of a field-effect transistor, or 
between the emitter terminal and the collector terminal in a bi-polar 
transistor, without flowing through any built-in commutating diode or 
diode-junction. Thus, whereas the magnitude of any reverse current which 
might flow through a transistor (e.g., through a built-in commutating 
diode) can not be controlled by way of the transistor's control terminals, 
the magnitude of the forward current can be controlled by application of a 
controllable voltage (in case of FET's) or current (in case of bi-polar 
transistors) to the transistor's control input terminals (i.e., the 
gate-source terminals of a FET or the base-emitter terminals of a bi-polar 
transistor). 
(aw) The term "substantially sinusoidal waveform" is to be understood to 
apply to a waveform where, with respect to a purely sinusoidal waveform, 
the total harmonic distortion is no higher than 20%. 
This definition notwithstanding, the total harmonic distortion of the 
various substantially sinusoidal waveforms associated with the inverter 
circuits of FIGS. 3 and 5 {e.g., waveforms (a) through (d), (g), (i), (j) 
through (m), (p), (q), (aa) and (ac) of FIGS. 4 and 6} is actually only 
about 10% or less. 
(ax) In the inverter circuits of FIGS. 3 and 5, and as indicated by 
waveform (ae) and (af), a periodically pulsed unidirectional voltage 
exists across each field-effect transistor (e.g. FET1a); with each 
individual voltage pulse being equal to a complete half-cycle of a 
substantially sinusoidal voltage; with each such half-cycle being defined 
as having its beginning and its end at a cross-over point; with a 
cross-over point being defined as a point at which the instantaneous 
magnitude of the substantially sinusoidal voltage reverses polarity. 
(ay) Even though not expressly so indicated, the fluorescent lamps of FIGS. 
3 and 5 are disconnectable. 
(az) With reference to waveforms (ad) and (ac) of FIG. 6, the current 
flowing through fluoresent lamp ISFLx (i.e., the lamp current) has a 
waveform which is composed of two principal components: (i) a 
substantially sinusoidal wave component of relatively large magnitude; and 
(ii) a squarewave component of relatively small magnitude. 
The squarewave component is characterized as having cross-over points 
(i.e., phasing) displaced by about one quarter period (i.e., by about 90 
degrees) from the cross-over points of the sinusoidal wave component. 
The peak-to-peak magnitude of the squarewave component is equal to the 
height of the voltage-step occurring at the crest of the lamp current 
waveform. 
(ba) Inductor EI (i.e., the inverter's feed inductor) may be located in 
series with either conductor connecting the bridge inverter to the source 
of DC supply voltage. However, to minimize EMI, as well as to minimize 
electric shock hazard associated with the inverter's output terminals 
(i.e., the AC1.AC2 buses), the feed inductor should be split, as indicated 
in FIG. 3. 
(bb) In ordinary parallel-resonant-type electronic ballasts, the peak 
magnitude of the voltage existing across each transistor in the ballast's 
inverter is larger than pi times half of the magnitude of the DC voltage 
supplying the inverter, where pi is equal to 3.14. 
In fact, in a parallel-resonant-type electronic ballast of the kind 
presently available in the U.S. market, such peak magnitudes were measured 
to exceed 3.4 times the magnitude of the DC supply voltage. 
(bc) With reference to FIG. 5, it is noted that the complete inverter 
circuit used for converting the DC supply voltage (i.e., the DC voltage 
provided between the B- bus and the B+ bus) to the the substantially 
sinusoidal AC output voltage (i.e., the voltage provided between junctions 
J1 and J2) consists of only 13 individual components, namely: EI, TI, 
TCab, FET1a, FET1b, FET2a, FET2b, Z1a, Z1b, Z2a, Z2b, R1a and R2b. 
DESCRIPTION OF A YET-OTHER ALTERNATIVE EMBODIMENT 
Details of Construction of Yet-other Alternative Embodiment 
FIG. 7, which consists of FIGS. 7A and 7B, which should be viewed together 
schematically illustrates a yet-other alternative embodiment of the 
invention. 
In FIG. 7, bridge rectifier BR is connected with power line source S and 
provides a non-filtered full-wave-rectified power line voltage voltage 
between the DC- terminal and the DC+ terminal; across which two terminals 
is connected high-frequency filter capacitor HFFC. 
The DC- terminal is connected with the B- bus. 
An energy-storing inductor Lx is connected between the DC+ terminal and an 
auxiliary junction AJx1. The drain terminal of a field effect transistor 
FETx is connected with another auxiliary junction AJx2; the source 
terminal of transistor FETx is connected with the B- bus by way of a 
current-sensing resistor Rx1; and the gate terminal of transistor FETx is 
connected with terminal. 7 of pre-converter IC PCIC, whose terminal 4 is 
connected with the source terminal of transistor FETx. 
Otherwise, the terminals of pre-converter IC PCIC are connected as follows: 
terminal 6 is connected directly with the DC- bus; terminal 3 is connected 
with the B- bus by way of a capacitor Cx1, which is parallel-connected 
with a resistor Rx2; terminal 3 is also connected with the DC+ terminal by 
way of a resistor Rx3; terminal 2 is connected with terminal 8 by way of a 
capacitor Cx2; terminal 8 is connected with the B- bus by way of a filter 
capacitor Cx3; terminal 5 is connected by way of a resistor Rx4 to the 
anode of a diode Dx1, whose cathode is connected with terminal 8; and 
terminal 1 is connected directly with the cathode of a diode Dx2 as well 
as with the cathode of a diode Dx3. 
An auxiliary winding AWx1 on inductor Lx is connected between the B- bus 
and the anode of diode Dx1. 
The anode of a high-speed rectifier HSRx is connected with junction AJx2; 
while the cathode of this rectifier is connected with the B+ bus. Another 
auxiliary winding AWx2 on inductor Lx is connected between the B+ bus and 
the cathode of a diode Dx4, whose anode is connected with the B+ bus by 
way of a filter capacitor Cx4. A resistor Rx5 is connected between the 
anode of diode Dx4 and the anode of diode Dx2; which anode is connected 
with the B- bus by way of a resistor Rx6. A resistor Rx7 is connected 
between the B+ bus and the anode of diode Dx3; which anode is connected to 
the B- bus by way of a resistor Rx8. 
A main DC filter capacitor FCx is connected between the B- bus and the B+ 
bus. 
A capacitor Cx5 is connected between the B+ bus and the gate terminal of a 
field effect transistor FETx1, whose source terminal is connected with the 
B- bus, and whose drain terminal is connected with the anode of diode Dx2. 
A zener diode Zx is connected with its cathode to the gate terminal of 
transistor FETx1 and with its anode to the B- bus. A resistor Rx9 is 
connected in parallel with Zener diode Zx. 
Auxiliary junctions AJx1 and AJx2 (which are found on the part of FIG. 7 
labeled Pre-Converter Circuit) are connected with the terminals of an 
auxiliary winding AWy wound on a main transformer MTy (which main 
transformer MTy is found on the part of FIG. 7 labeled Bridge Inverter 
Circuit). 
Otherwise, while the B- bus is connected directly with a BIy- bus, an 
inductor Ly is connected between the B+ bus and a BIy+ bus. A capacitor Cy 
is connected between the BIy- bus and the BIy+ bus. A field effect 
transistor FETy1a is connected with its drain terminal with the BIy+ bus 
and with its source terminal to a junction Jy1; while a field effect 
transistor FETy1b is connected with its drain terminal to junction Jy1 and 
with its source terminal to the BIy- bus. Similarly, a field effect 
transistor FETy2a is connected with its drain terminal with the BIy+ bus 
and with its source terminal to a junction Jy2; while a field effect 
transistor FETy2b is connected with its drain terminal to junction Jy2 and 
with its source terminal to the BIy- bus. 
A primary winding PWy on main transformer MTy is connected between 
junctions Jy1 and Jy2; and a secondary winding SWy is connected between a 
pair of AC rails ACy1 and ACy2; across which AC rails are connected a 
number of lamp-ballast series-combinations SCy1, SCy2: series-combination 
SCy1 consisting of ballast capacitor BCy1 series-connected with 
instant-start fluorescent lamp FLy1; series-combination SCy2 consisting of 
ballast capacitor BCy2 series-connected with instant-start fluorescent 
lamp FLy2. 
Main transformer MTy has four feedback windings FWy1a, FWy1b, FWy2a, FWy2b; 
one terminal of each being connected with the source terminal of 
transistors FETy1a, FETy1b, FETy2a, FETy2b; the other one terminal of each 
being connected with the anode of each of Zener diodes Zy1a, Zy1b, Zy2a, 
Zy2b; whose cathodes are connected with the gate terminals of transistors 
FETy1a, FETy1b, FETy2a, FETy2b, all respectively. 
Details of Operation of Yet-other Alternative Embodiment 
With reference to FIG. 7, the operation of the yet-other alternative 
embodiment is described and explained as follows. 
The operation of the Pre-Converter Circuit of FIG. 7 is substantially 
conventional except that, during normal steady-state operation, the 
absolute magnitude of the DC rail voltage (i.e., the absolute magnitude of 
the DC voltage present between the B- bus and the B+ bus) is regulated so 
as to be higher by a given predetermined amount than the peak absolute 
magnitude of the AC power line voltage provided at the AC input terminals 
to bridge rectifier BR. Thus, as the magnitude of the AC power line 
voltage changes, the magnitude of the DC rail voltage changes accordingly. 
That is, during normal steady-state operation, the Pre-Converter Circuit is 
arranged to regulate in such manner as to maintain substantially constant 
the difference between the magnitude of the DC rail voltage and the peak 
magnitude of the power line voltage; which contrasts with the usual 
practice of maintaining the magnitude of the DC rail voltage itself 
constant, substantially irrespective of changes in the magnitude of the AC 
power line voltage. 
{For additional explanation with respect to how a conventional 
pre-converter circuit operates, particular reference is made to FIG. 19 
(and associated explanations) of a published report from Motorola Inc. 
entitled Motorola Semiconductor Technical Data and pertaining to 
Motorola's Power Factor Controller MC34262.} 
During normal steady-state operation of the Pre-Converter Circuit, 
transistor FETx1 is non-conductive; and regulation derives from the 
magnitude of the DC voltage existing across resistor Rx6; which magnitude, 
in turn, is a direct measure of the difference between the magnitude of 
the DC voltage present at the B+ bus and the magnitude of the DC voltage 
present across capacitor Cx4; which latter magnitude is a direct measure 
of the peak magnitude of the pulsating voltage present between the DC- 
terminal and the DC+ terminal; which, in turn, is a direct measure of the 
peak magnitude of the AC power line voltage applied to the AC input 
terminals of bridge rectifier BR. 
The polarity of, and the number of turns on, auxiliary winding AWx2 are 
arranged so that the instantaneous absolute magnitude of the DC voltage 
developing across filter capacitor Cx4 is equal to that of the DC voltage 
present between the DC- and the DC+ terminals. Thus, with the polarity of 
the DC voltage across capacitor Cx4 arranged as shown in FIG. 7, the 
magnitude of the DC voltage present at the anode of diode Dx4 is equal to 
the difference between the magnitude of the DC rail voltage (as present 
between the B- bus and the B+ bus) and the magnitude of the unfiltered 
full-wave-rectified AC power line voltage (as present between the DC- and 
DC+ terminals). 
That is, via a first feedback path going through diode Dx2, the 
Pre-Converter Circuit functions to regulate the absolute magnitude of the 
DC rail voltage to be higher than the peak absolute magnitude of the AC 
power line voltage by a certain differential amount. 
However, as a safety feature, irrespective of the difference between the 
magnitude of the DC rail voltage and the peak magnitude of the AC power 
line voltage, by way of a second feedback path going through diode Dx3, 
the magnitude of the DC rail voltage is absolutely prevented from 
exceeding a certain maximum level; which certain maximum level is 
determined by the magnitude of the DC voltage present across resistor Rx8. 
That is, pre-converter IC PCIC controls the magnitude of the DC rail 
voltage to be higher than the peak magnitude of the AC power line voltage 
by a certain differential amount, but nevertheless prevents the magnitude 
of the DC rail voltage from ever exceeding a certain maximum level (which, 
for instance, could occur if the peak magnitude of the AC power line 
voltage were to be higher than normally would be the case). 
When the AC power line voltage is initially connected with the AC input 
terminals of bridge rectifier BR, the magnitude of the DC rail voltage 
increases rapidly (i.e., within half a cycle of the AC power line voltage) 
to an initial relatively high level. This increase in the magnitude of the 
DC rail voltage causes the magnitude of the DC voltage at the gate 
terminal of transistor FETx1 to increase to the point of being limited by 
the Zener voltage of Zener diode Zx, thereby causing transistor FETx1 to 
become conductive. With transistor FETx1 conductive, said first feedback 
path is disrupted, thereby--as long a transistor FETx1 remains conductive, 
and regardless of the magnitude of the AC power line voltage--causing the 
magnitude of the DC rail voltage to be regulated to its maximum level; 
which maximum level is reached within a few half-cycles of the AC power 
line voltage. 
However, after a brief period (e.g., about 100 milliseconds), by action of 
leakage resistor Rx9, the magnitude of the DC voltage at the gate terminal 
of transistor FETx1 diminishes to a level where transistor FETx1 ceases to 
be conductive, whereafter the first feedback path is restored and the 
magnitude of the DC rail voltage reverts to whatever level is dictated 
thereby. 
The Bridge Inverter Circuit of FIG. 7 operates substantially like that of 
FIG. 5, except as follows. 
The Bridge Inverter Circuit of FIG. 7: (i) uses an isolation transformer in 
the output stage; and (ii) is triggered into self-oscillation by having 
the current flowing through energy-storing inductor Lx of the 
Pre-Converter Circuit also flow through auxiliary winding AWy, which 
consists of one or a few turns coupled with the other windings of main 
transformer MTy. 
On initial power-up, the magnitude of the DC rail voltage rapidly (e.g., 
within a few half-cycle of the AC power line voltage) reaches its 
predetermined maximum level; which maximum level is sufficiently high to 
cause fluorescent lamps FLy1, FLy2 to ignite properly; which they will do 
within about 100 milliseconds; whereafter the magnitude of the DC rail 
voltage will diminish to a point of being just a small amount (e.g., 20 
Volt) higher than the peak magnitude of the AC power line voltage. 
Additional Comments re yet-other Alternative Embodiment 
(bd) During ordinary steady-state operation, the peak magnitude of the 
substantially sinusoidal voltage applied between the gate and source 
terminals of each of transistors FETy1a, FETy1b, FETy2a, FETy2b is not 
higher than 20 Volt; which is within the normal steady-state rating for 
FET power devices. 
(be) With each of the power FET's of the Bridge Inverter Circuit of FIG. 7 
having a threshold voltage of about 4.2 Volt, the Zener voltage of the 
gate-connected Zener diodes should be about 3 Volt. 
The purpose of the gate-connected Zener diodes is that of making the 
waveform of the voltage generated by the Bridge Inverter Circuit closer to 
perfectly sinusoidal, thereby to improve the crest factor of the resulting 
lamp current. The preferred Zener voltage is that which provides for 
minimum lamp current crest factor. 
(bf) The voltage and current waveforms associated with the preferred 
embodiment of FIG. 7 are basically the same as those associated with the 
embodiments of FIGS. 3 and 5. 
More particularly, with respect to the Bridge Inverter Circuit of FIG. 7: 
1. The alternating component of the voltage present at junction Jy1 (or at 
junction Jy2)--as referenced to the B- bus (or to the B+ bus)--is 
substantially of sinusoidal waveform, as is the AC voltage present between 
junctions Jy1 and Jy2. That is, the AC voltage present at junction Jy1 (or 
between junctions Jy1 and Jy2) has a waveform like that of Waveform (aa) 
FIG. 6. 
2. The voltage present at the BIy+ bus--as referenced to the B- bus--is 
like Waveform (r) of FIG. 4. 
3. The voltage present at the drain terminal of transistor FET1yb (or 
FETy2b)--as reference to the B- bus--has a waveform like Waveform (ae) of 
FIG. 6. 
4. The waveform of the current flowing through inductor Ly is as 
illustrated by Waveforms (h) and (i) of FIG. 4. 
5. The current flowing through one of the fluorescent lamps has a waveform 
like Waveforms (ab) or (ad) of FIG. 6. 
(bg) It is noted that Waveforms (ab) and (ad) of FIG. 6 consists of a pure 
sinewave to which is added a squarewave (of substantially lower magnitude) 
whose phasing--as referenced to the squarewave's fundamental component--is 
displaced by 90 degrees. 
(bh) A field effect transistor is usually controlled by application of a 
squarewave-shaped drive voltage between its gate and source terminals; 
which is in sharp contrast with the roughly sinusoidally-shaped drive 
voltage applied between the gate-source terminals of the field effect 
transistors in the bridge inverter circuits of the present invention. 
Note: Compared with a pure sinewave, the total harmonic distortion of a 
squarewave is 50%. 
(bi) Tank-capacitor C and tank-inductor L of FIG. 1 are parallel-connected 
and represents an LC tank circuit having a natural resonance frequency. 
FIGS. 3, 5 and 7 similarly each includes an LC tank circuit. In the Bridge 
Inverter Circuit of FIG. 7, the tank-inductor is represented by the 
effective shunt inductance of transformer MTy; and, prior to lamp 
ignition, the tank-capacitor is capacitor Cy. After lamp ignition, ballast 
capacitors BCy1, BCy2 effectively add to the tank capacitor. 
(bj) As for instance indicated by Waveforms (a) and (e) of FIG. 4, for a 
very brief period each half-cycle {at or near the cross-over points of the 
substantially sinusoidal waveform represented by Waveform (a)}, none of 
the four field effect transistors of the Bridge Inverter Circuit (e.g., 
the one illustrated by FIG. 7) conducts; which is to say, during these 
brief periods, the inductive current flowing through the feed inductor 
(e.g., Ly of FIG. 7) has no place to flow except into the tank-capacitor 
(e.g., Cy of FIG. 7). 
(bk) Each of the Bridge Inverter Circuits of FIGS. 3, 5 and 7 is a 
so-called self-oscillating inverter; which is to say, each inverter is 
made to self-oscillate by providing the periodic drive voltage required 
for operating each of the field effect transistors via positive feedback 
derived from the inverter's output. 
DESCRIPTION OF THE PREFERRED EMBODIMENT 
Details of Construction of Preferred Embodiment 
The presently preferred embodiment of the invention is schematically 
illustrated by FIG. 8. 
In FIG. 8, DC voltages are provided between the B- bus and the B+ bus, as 
well as betwee the B- bus and the A+ bus, from some suitable DC source, 
such as from the Pre-Converter Circuit of FIG. 5. A filter capacitor FCz 
is connected between the B- bus and the B+ bus. 
Otherwise, the inverter/ballast circuit of FIG. 8 is substantially 
identical to the Bridge Inverter Circuit of FIG. 7, except for the 
following differences. 
(i) Rapid-Start fluorescent lamps FLz1 and FLz2 are used instead of 
Instant-Start fluorescent lamps FLy1 and FLy2; and the resulting 
lamp-capacitor series-combinations are therefore identified as SCz1 and 
SCz2, respectively. 
(ii) Current-limiting inductor Lz is used in lieu of current-limiting 
inductor Ly; which current-limiting inductor Lz has three auxiliary 
cathode heater windings CHW; which windings are connected with the 
thermionic cathodes of Rapid-Start fluorescent lamps FLz1 and FLz2 in the 
usual manner. 
(iii) Auxiliary winding AWy has been removed, without expressly providing 
for another means to trigger the inverter into self-oscillation. 
(iv) A high-speed rectifier HSRz is connected with its cathode to the B+ 
bus and with its anode to the BIy- bus. 
(v) A field effect transistor FETz is connected with its source terminal to 
the B- bus and with its drain terminal to the BIy- bus. 
(vi) An auxiliary winding AWz on main transformer MTy has a center-tap 
connected with the B-bus and its other two terminals connected with the 
anodes of diodes Dz1 and Dz2, whose cathodes are connected to an input 
terminal ITz of a dimming controller DCz; which dimming controller DCz 
also has an output terminal OTz connected with the gate terminal of field 
effect transistor FETz, a negative DC supply terminal DCz-connected with 
the B- bus, a positive DC supply terminal DCz+ terminal connected with the 
A+ bus, and a dimming-control input terminal DCIT. 
Details of Operation of Preferred Embodiment 
The operation of the inverter/ballast circuit of FIG. 8, to the extent it 
is different from that of the Bridge Inverter Circuit of FIG. 7, may best 
be understood with reference to the waveforms of FIG. 9; wherein: 
Waveform (a) shows a synchronizing voltage signal provided to input 
terminals ITz of dimming controller DCz; 
Waveform (b) shows the constant-magnitude DC voltage provided to the gate 
terminal of field effect transistor FETz under a condition of being 
maintained in a state of continuous conduction; 
Waveform (c) shows the constant-magnitude DC voltage present at the B+ bus 
as referenced to the BIy- bus under the condition wherein field effect 
transistor FETz is being maintained in a state of continuous conduction; 
Waveform (d) shows the current flowing through current-limiting inductor Lz 
under the condition corresponding to Waveform (b); 
Waveform (e) shows the voltage present at the BIy+ bus as referenced to the 
BIy- bus under the condition corresponding to Waveform (b); 
Waveform (f) shows the voltage present between AC rails ACy1 and ACy2 under 
the condition corresponding to Waveform (b); 
Waveform (g) shows the lamp current flowing through one of the fluorescent 
lamps (FLz1 or FLz2) under the condition corresponding to Waveform (b); 
Waveform (h) shows the voltage provided to the gate terminal of field 
effect transistor FETz under a condition wherein this transistor is 
rendered non-conductive for about one sixth of the total duration of each 
complete switching cycle; 
Waveform (i) shows the voltage present at the B+ bus as referenced to the 
BIy- bus under the condition corresponding to Waveform (h); 
Waveform (j) shows the current flowing through current-limiting inductor Lz 
under the condition corresponding to Waveform (h); 
Waveform (k) shows the voltage present at the BIy+ bus as referenced to the 
BIy- bus under the condition corresponding to Waveform (h); 
Waveform (l) shows the voltage present between AC rails ACy1 and ACy2 under 
the condition corresponding to Waveform (h); 
Waveform (m) shows the lamp current flowing through one of the fluorescent 
lamps (FLz1 or FLz2) under the condition corresponding to Waveform (h); 
Waveform (n) shows the voltage provided to the gate terminal of field 
effect transistor FETz under a condition wherein this transistor is 
rendered non-conductive for about one third of the total duration of each 
complete switching cycle; 
Waveform (o) shows the voltage present at the B+ bus as referenced to the 
BIy- bus under the condition corresponding to Waveform (n); 
Waveform (p) shows the current flowing through current-limiting inductor Lz 
under the condition corresponding to Waveform (n); 
Waveform (q) shows the voltage present at the BIy+ bus as referenced to the 
BIy- bus under the condition corresponding to Waveform (n); 
Waveform (r) shows the voltage present between AC rails ACy1 and ACy2 under 
the condition corresponding to Waveform (n); 
Waveform (s) shows the lamp current flowing through one of the fluorescent 
lamps under the condition corresponding to Waveform (n); 
Waveform (t) shows the voltage provided to the gate terminal of field 
effect transistor FETz under a condition wherein this transistor is 
rendered non-conductive for about one half of the total duration of each 
complete switching cycle; 
Waveform (u) shows the voltage present at the B+ bus as referenced to the 
BIy- bus under the condition corresponding to Waveform (t); 
Waveform (v) shows the current flowing through current-limiting inductor Lz 
under the condition corresponding to Waveform (t); 
Waveform (w) shows the voltage present at the BIy+ bus as referenced to the 
BIy- bus under the condition corresponding to Waveform (t); 
Waveform (x) shows the voltage present between AC rails ACy1 and ACy2 under 
the condition corresponding to Waveform (t) ; and 
Waveform (y) shows the lamp current flowing through one of the fluorescent 
lamps under the condition corresponding to Waveform (t). 
Now, with reference to the waveforms of FIG. 9, the operation of the 
inverter/ballast arrangement of FIG. 8 may be explained as follows. 
The Bridge Inverter Circuit of FIG. 8 (which is intended to be provided 
with DC voltages from a Pre-Converter Circuit such as that of FIG. 5) is 
shown without any particular means for triggering it into self-sustaining 
oscillations. However, any one of several different conventional 
triggering means may be used. Or, as indeed indicated in FIG. 7, 
triggering may be effectuated via its Pre-Converter Circuit. 
Once triggered, the Bridge Inverter Circuit of FIG. 8 will, via positive 
feedback, continue to oscillate as long a unidirectional current is 
supplied to its BIy-/BIy+ bus terminals. That is, the Bridge Inverter 
Circuit of FIG. 8 will continue self-sustaining oscillations as long as a 
unidirectional current flows through its feed inductor Lz. 
On initial power up, dimming controller DCz provides for its output 
terminal OTz to be at the level of the DC voltage provided from the A+ 
bus; which level is such as to cause transistor FETz to assume a state of 
being fully conductive, thereby causing the full DC voltage developed by 
the Pre-Converter Circuit to be applied between the BIy- bus and the B+ 
bus; which, in turn, permits the Bridge Inverter Circuit of FIG. 8 to be 
triggered into self-sustaining oscillations. 
Thus, when initially provided with its DC supply voltage, the Bridge 
Inverter Circuit of FIG. 8 will function in a manner substantially 
identical to that of the Bridge Inverter Circuit of FIG. 7 and therefore 
generates voltages and currents having waveforms as shown by Waveforms (a) 
through (g) of FIG. 9; which waveforms are substantially identical to 
those of FIG. 6. 
{Note, however, that some of the details of the waveforms of FIG. 6 have 
been omitted in the waveforms of FIG. 9.} 
The synchronizing signal voltage provided to input terminal ITz of dimming 
control DCz--which voltage is illustrated by Waveform (a) of FIG. 9--will 
cause the magnitude of the control signal provided from output terminal 
OTz to alternate abruptly between: (i) being substantially equal to the DC 
voltage on the A+ terminal, and (ii) being substantially equal to the DC 
voltage on the DC- bus. Thus, field effect transistor FETz will be 
switched between ON and OFF in a corresponding manner. 
In other words, dimming controller DCz acts like a high-gain inverting 
amplifier with respect to the synchronizing voltage signal received at its 
input terminal ITz, causing--as the magnitude of this synchronizing 
voltage signal moves below or above a certain voltage threshold level--the 
output signal at output terminal OTz to switch abruptly between being at 
the potential of the DCz+ terminal or the DCx- terminal, 
and--correspondingly--to cause FETz to switch abruptly between being in 
its ON-state and being in its OFF-state. The certain voltage threshold 
level is determined by the magnitude of the dimming control voltage 
provided at dimming control input terminal DCIT. 
With reference to FIG. 9, the overall function of dimming controller DCz is 
such as to cause field effect transistor FETz to switch ON and OFF is a 
manner that: (i) is Synchronous with (but not necessarily in phase with) 
the switching ON and OFF of transistors FETy1a, FETy1b, FETy2a, FETy2b; 
(ii) has an ON/OFF-ratio (or duty-cycle) controllable by the magnitude of 
the dimming control voltage provided at dimming control input terminal 
DCIT {see Waveforms (h), (n), (t)}; and (iii) gives rise to a 
corresponding ON/OFF-switching of the DC voltage driving the current 
flowing through feed inductor Lz and thereby through the bridge inverter 
{see Waveforms (i), (o), (u) for an illustration of this 
now-periodically-interrupted DC voltage}. 
As a direct consequence of the now-periodically-interrupted of the DC 
voltage provided between the BIy- bus and the B+ bus (which indeed is the 
DC voltage driving the current flowing through feed inductor Lz), the 
average magnitude of the current flowing through feed inductor Lz will be 
affected. 
More particularly, the average magnitude of the current driven through feed 
inductor Lz will be proportional to the average magnitude of the DC supply 
voltage present between the BIy- bus and the B+ bus; and, as long as the 
inductance of feed inductor Lz is sufficiently large, the magnitude of the 
current flowing through feed inductor Lz will stay substantially constant 
during the complete duration of a complete cycle of the 
now-periodically-interrupted DC supply voltage {see waveforms (i), (o), 
(u) of FIG. 9}. 
In practice, some degree of modulation of the current flowing through feed 
inductor Lz is permissible without causing significant ill effects; and, 
in reality, it is cost-effective to have the current flowing through feed 
inductor Lz have a modest degree of magnitude variations, such as indeed 
indicated by Waveforms (j), (p), (v) of FIG. 9. 
As a direct result of reducing the average magnitude of the current forced 
through feed inductor Lz, corresponding reductions result with respect to 
the magnitudes of: (i) the voltage present at the BIy+ bus as referenced 
to the BIy- bus {see Waveforms (k), (q), (w); (ii) the voltage present 
between AC rails ACy1 and ACy2 {see Waveforms (l), (r), (x)}; and (iii) 
the lamp current flowing through each of fluorescent lamps FLz1, FLz2 {see 
Waveforms (m), (s), (y)}. 
Of course, when dimming Rapid-Start fluorescent lamps over a substantial 
range, it is important to maintain proper cathode heating as the magnitude 
of the lamp current is reduced. However, if cathode heating had been 
accomplished by way of auxiliary windings on main transformer MTy (which 
indeed is the usual practice), the magnitude of the cathode heating 
voltage would have diminished in proportion with diminished magnitude of 
lamp current; which is exactly opposite of what's actually desirable; and 
which explains why dimmable parallel-resonant-type ballasts have not been 
feasible. 
{Note: It is not known how to control the frequency in parallel-resonant 
ballasts to a degree sufficient to result in wide-range dimming capability 
while at the same time maintaining an acceptably low lamp current crest 
factor.} 
In the invention represented by FIG. 8, cathode heating is accomplished via 
auxiliary windings on feed inductor Lz. Since the RMS magnitude of the 
alternating voltage provided by these auxiliary windings actually 
increases as the magnitude of the lamp current is diminished, the result 
is that the externally provided cathode heating power increases as the 
internal cathode heating power (as resulting from the lamp current itself) 
diminishes; which is indeed a desirable result. 
In fact, the RMS magnitude of the voltage present across feed inductor Lz 
(which, of course, is proportional to the RMS magnitude of the cathode 
heating voltage provided by cathode heating windings CHW) is the square 
root of the sum of the squares of the RMS magnitudes of: (i) the 
alternating voltage component of the voltage present between the BIy-bus 
and the BIy+ bus {see Waveforms (k), (q) and (w) of FIG. 9}; and (ii) the 
alternating voltage component of the voltage present between the BIy- bus 
and the B+ bus {see Waveforms (i), (o) and (u) of FIG. 9}. 
Additional Comments re Preferred Embodiment 
(bl) Depending on the degree of light output control desired, the RMS 
magnitude of the cathode heating voltage provided from the auxiliary 
windings on feed inductor Lz may increase more than necessary as lamp 
current is reduced. To compensate for such an effect, a compensating 
component of cathode heating voltage may be added to the component 
obtained from each of the auxiliary windings on feed inductor Lz; which 
compensating component may be obtained from an added winding on main 
transformer MTy--with one such added winding series-connected with each 
one of the auxiliary windings on feed inductor Lz. 
(bm) In one desirable mode of operation of the circuit of FIG. 8, to permit 
proper starting of the fluorescent lamps even in a fully dimmed state, 
upon initial power-up, operation of dimming control DCz can readily be 
arranged in such manner as to start out in a mode that would provide for 
maximum dimming, yet providing for a lamp voltage high enough to cause 
lamp ignition. Thereafter, if a less-than-maximum degree of dimming be 
desired, the percentage of OFF-time associated with transistor FETz would 
automatically be reduced to some pre-determined degree, thereby 
correspondingly increasing the RMS magnitude of the AC rail voltage (i.e., 
the high-frequency AC voltage present between AC rails CAy1 and ACy2) and 
thereby the RMS magnitude of the lamp current. 
In other words, as a person possessing ordinary skill in the art most 
pertinent hereto would readily know how to do, a starting procedure can be 
provided for by which the lamps are always ignited in a condition of 
maximum degree of dimming, but thereafter automatically caused to increase 
light output to an adjustably desired pre-set level. 
Otherwise, in a more usual mode of operation, the lamps are started in 
their maximum light output state. In this case, to provide for proper 
rapid-starting of the lamps, the RMS magnitude of the AC rail voltage is 
initially at its maximum (which implies that transistor FETz initially 
operates in a mode of minimum OFF-time); whereafter it is reduced to 
attain the desired level of light output. 
{Of course, the primary-to-secondary voltage transformation ratio 
associated with main transformer MTy would have to be different in case of 
rapid-starting the fluorescent lamps in a mode of maximum light output 
versus rapid-starting them in a mode of minimum light output.} 
(bn) With reference to the circuit of FIG. 8, in the preferred mode of 
operation, lamps FLz1/FLz2 are the type of fluorescent lamps (e.g., 
Sylvania's Octron lamps) which can be properly operated either in an 
instant-start mode or in a rapid-start mode; and the circuit is arranged 
to properly operate in one mode or the other, depending on the magnitude 
of the dimming control voltage provided to dimming control input terminal 
DCIT. 
More particularly: 
With the magnitude of the dimming control voltage set for maximum light 
output, the lamps will be instant-started, while the RMS magnitude of the 
cathode heating voltage provided to the lamps' cathodes will be very 
low--far too low to provide adequate amount of cathode heating to permit 
rapid-starting. Because of the very low amount of cathode heating power 
then provided, extra high lamp luminous efficacy results during operation 
under full light output. 
With the the magnitude of the dimming control voltage set for minimum light 
output, the lamps will be rapid-started--the RMS magnitude of the cathode 
heating voltage now provided to the lamps' cathodes being high enough to 
permit rapid-starting as well as operation at a lamp current substantially 
lower than what is required to provide for adequate cathode self-heating 
(which actually occurs as long as the RMS magnitude of the lamp current is 
close to what's required for full lamp light output). 
Thus: 
(1) In a first mode, by providing an AC rail voltage of magnitude high 
enough to cause lamp instant-starting, while at the same time providing a 
very low level of externally-supplied cathode heating power, proper lamp 
instant-starting occurs and high luminous effciacy results; whereas 
(1) In a second mode, by providing an AC rail voltage of magnitude high 
enough to permit proper lamp rapid-starting, while at the same time 
providing a sufficiently high level of externally-supplied cathode heating 
power, proper lamp rapid-starting occurs even a substantially reduced 
light output levels. 
Stated differently, in its preferred implementaion, the circuit of FIG. 8 
represents a fluorescent lamp lighting arrangement that: (i) permits 
plural fluorescent lamps to be operated in parallel-connected 
configuration; (ii) provides for these parallel-connected fluorescent 
lamps to be properly instant-started under a condition where a relatively 
high level of light output is desired; (iii) provides for these 
parallel-connected lamps to be properly rapid-started under a condition 
where a relatively low level of light output is desired; (iv) permits 
these parallel-connected lamps to be properly ignited under any of various 
different levels of resulting light output levels; (v) permits the light 
output from these parallel-connected lamps to be controlled over a 
relatively wide range; and (vi) providing for minimal externally-supplied 
cathode heating power in an instant-start mode, where desired light output 
level is relatively high; and (vii) provides for the amount of externally 
supplied cathode heating power to be increased in a gradual manner as the 
magnitufe of the lamp starting voltage is decreased in a gradual manner, 
thereby to provide for the lamp starting process to change in a gradual 
manner from being of a substantially pure instant-start type (then 
providing a relatively high level of light output) to being of a 
substantially pure rapid-start type (then providing a relatively low level 
of light output). 
(bo) In the circuit of FIG. 8, since one of transistor pairs FETy1a & 
FETy2b and FETy1b & FETy2a is always conducting, capacitor Cy is always 
connected in parallel with the primary winding of main transformer MTy. 
Thus, capacitor Cy is a tank capacitor to the tank-inductor represented by 
the primary winding of main transformer MTy; which, at no load, means that 
the natural resonance frequency of this parallel-combination of tank 
capacitor Cy and the tank-inductor represented by this primary winding is 
determined entirely by the capacitance of Cy and the inductance of this 
tank inductor. 
In approximation, the inverter oscillating frequency is equal to the 
natural resonance frequency of this parallel-combination of Cy and the 
tank inductor of the primary winding of main transformer MTy. 
(bp) With reference to the circuit arrangement of FIG. 8, since the 
magnitude of the unidirectional current supplied to the bridge inverter 
can be regulated over a wide range by controlling the ON-time of 
transistor FETz, by sensing the magnitude of the lamp current and by 
providing a measure of this magnitude to dimming control input terminals 
DCIT of dimming control DCz, it is a simple matter to compensate for any 
changes in the magnitude of the lamp current that might occur as a result 
of changes in the magnitude of the DC supply voltage provided between the 
B- bus and the B+ bus. Thus, if this DC supply voltage were to be provided 
from a non-regulated DC source, the magnitude of the lamp current could 
nevertheless be maintained constant irrespective of changes in the 
magnitude of the DC supply voltage. 
(bp) The inductance of feed inductor Lz should be at least so large that 
the magnitude of the feed current flowing through it will not change to a 
substantial degree--even if the magnitude of the DC supply voltage were to 
change abruptly to zero--during a period of time equal to half the 
duration of the fundamental frequency of the AC voltage provided at AC 
rail terminals ACy1 and ACy2. 
(bq) In the circuit arrangement of FIG. 8, the alternating voltage present 
across feed inductor Lz has an instantaneous magnitude equal to the 
difference between: (i) the instantaneous magnitude of the voltage between 
the BIy- bus and the BIy+ bus, and (ii) the instantaneous magnitude of the 
voltage between the BIy- bus and the B+ bus. 
Thus, when transistor FETz is maintained in a continuous ON-state, this 
alternating voltage is simply equal to the alternating component of the 
voltage present between the BIy- bus and the BIy+ bus, as illustrated by 
Waveform (e) of FIG. 9. 
When transistor FETz is switched OFF for a very brief period in the middle 
of each unidirectional (sinusoidally-shaped) pulse of the voltage between 
the BIy- bus and the BIy+ bus, the voltage present across feed inductor Lz 
will have a waveform equal to that of Waveform (e) except that, right in 
the middle of each sinusoidally-shaped voltage pulse, the instantaneous 
magnitude of the waveform drops by an amount equal to the magnitude of the 
DC supply voltage. 
When transistor FETz is switched OFF for longer periods, the magnitude of 
the sinusoidally-shaped voltage pulses drops in proportion to the ratio 
between the duration of the OFF period versus the duration of the total 
ON-plus-OFF period. Nevertheless, during the time-interval that transistor 
FETz is in its OFF-state, the instantaneous magnitude of each 
sinusoidally-shaped voltage pulse will be reduced by the magnitude of the 
DC supply voltage. 
(br) The magnitude of the current flowing through feed inductor Lz depends 
on three factors: (i) the magnitude of the DC supply voltage (i.e., the DC 
voltage provided between the B- bus and the B+ bus), (ii) the ON-OFF ratio 
of transistor FETz, and (iii) the loading presented to AC rails ACy1/ACy2. 
By controlling the ON-OFF ratio, which may be effectuated by controlling 
the magnitude of the voltage presented to dimming control input terminal 
DCIT (as referenced to the B- bus), changes in the magnitude of the DC 
supply voltage as well as changes in loading can readily be compensated 
for. More particularly, controlling the ON-OFF ratio changes the magnitude 
of the high-frequency AC voltage provided between AC rails ACy1 and ACy2. 
More particularly, the magnitude of the AC rail voltage (i.e., the AC 
voltage present across AC rails ACy1/AVy2) is directly proportional to the 
product of: (i) the magnitude of the DC supply voltage, and (ii) the ratio 
between the duration of the ON-period of FETz (the ON-duration) and the 
sum of the ON-duration and the OFF-duration (i.e., the duration of the 
OFF-period of FETz). 
It is noted that, except for very low inductance values, the magnitude of 
the average current flowing through feed inductor Lz is substantially 
independent of the magnitude of its inductance. 
(bs) In an actual prototype electronic ballast built in accordance with the 
circuit arrangement illustrated by FIG. 8, the RMS magnitude of the 
voltage provided at the output of each of cathode heating windings CHW on 
feed inductor Lz increased by a factor of two as light output from lamps 
FLz1/FLz2 was reduced--by way of reducing the ON-versus-OFF ratio of 
transistor FETz--from full normal light output to a small fraction of full 
normal light output. 
(bt) In the circuit arrangement of FIG. 8, the voltage existing between the 
BIy- bus and the B+ bus is unidirectional and has an average magnitude 
equal to that of the unidirectional voltage existing between the BIy- bus 
and the BIy+ bus. 
The unidirectional voltage existing between the BIy- bus and the B+ bus 
consists of a continuous train of rectangularly-shaped unidirectinal 
voltage pulses; whereas the unidirectional voltage existing between the 
BIt- bus and the BIy+ bus consists of a continuous train of 
sinusoidally-shaped unidirectional voltage pulses. 
The peak magnitude of the rectangularly-shaped voltage pulses is 
substantially equal to the magnitude of the DC supply voltage; whereas the 
peak magnitude of the sinusoidally-shaped voltage pulses is substantially 
equal to pi (i.e., 3.14) times half the average magnitude of the 
unidirectional voltage existing between the BIy- bus and the B+ bus. 
As long as transistor FETz periodically conducts, the voltage existing 
between the BIy- bus and the B+ bus alternates abruptly between having 
zero magnitude and having a magnitude substantially equal to that of the 
DC supply voltage. 
(bu) By using a pre-converter circuit, such as the type illustrated in FIG. 
3, for providing the DC supply voltage between the B- bus and the B+ bus 
of FIG. 8, the absolute magnitude of this DC supply voltage will (by 
necessity) be higher than the absolute peak magnitude of the power line 
voltage to which the pre-converter circuit is connected. 
As long as transistor FETz is periodically switched OFF, the average 
magnitude of the unidirectional voltage present between the BIy- bus and 
the B+ bus is lower than that of the DC supply voltage. 
(bv) Instant-starting of a fluorescent lamp is defined as causing the lamp 
to ignite prior to having caused the lamp cathodes to become thermionic to 
any significant degree. 
Rapid-starting of a fluorescent lamp is defined as causing the lamp to 
ignite only after having caused the lamp cathodes to become thermionic to 
a significant degree. 
Typically, instant-starting a fluorescent lamp requires a lamp voltage of 
RMS magnitude two-to-three times higher than that required for 
rapid-starting the same lamp. 
A fluorescent lamp may be either instant-started or rapid-started. However, 
a lamp designed only to be rapid-started will suffer severe reduction in 
useful lamp life if routinely instant-started. 
To accomplish proper instant-starting of a fluorescent lamp, the magnitude 
of the voltage provided across the lamp terminals should be high enough to 
cause the lamp to completely ignite within about 50 milli-seconds. 
(Ignition is completed only after the magnitude of the voltage across the 
lamp and the magnitude of the lamp current have both ceased to change.) 
To accomplish proper rapid-starting of a fluorescent lamp, the voltage 
provided across the lamp terminals should be of just sufficient magnitude 
to cause the lamp to fully ignite immediately after its cathodes have 
reached a temperature high enough to provide for thermionic emission 
sufficient to support the lamp current resulting after ignition is 
completed. (Ignition is completed only after the magnitude of the voltage 
across the lamp and the magnitude of the lamp current have both ceased to 
change.) 
The fluorescent lamps used in an initial embodiment of the circuit 
arrangement of FIG. 8 were 48"/T-8/F32 so-called Octron lamps from 
Sylvania; which lamps are designed to be properly ignited either in an 
instant-start manner or in a rapid-start manner. For proper instant-start 
ignition, a lamp voltage of at least 500 Volt RMS is required; whereas for 
proper rapid-starting, a lamp voltage of about 250 Volt RMS is typically 
required. After ignition, the lamp operating voltage assumes a magnitude 
of about 150 Volt RMS.