Pre-programmed integrated circuit including programmable logic

A system for providing a pre-programmed integrated circuit including programmable logic, and method for providing same. The system includes: nonvolatile memory capable of having first data stored therein and an integrated circuit coupled with the nonvolatile memory. The first data is associated with a predetermined design, and the integrated circuit includes programmable logic having a user region and a reserved region. The integrated circuit is configured to obtain the first data from the nonvolatile memory for instantiation of the predetermined design in the reserved region.

FIELD OF THE INVENTION

The invention relates to integrated circuit devices (ICs). More particularly, the invention relates to a pre-programmed integrated circuit including programmable logic.

BACKGROUND OF THE INVENTION

Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.

Another type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (PLAs) and Programmable Array Logic (PAL) devices. In CPLDs, configuration data is typically stored on-chip in nonvolatile memory. In some CPLDs, configuration data is stored on-chip in nonvolatile memory, then downloaded to volatile memory as part of an initial configuration (programming) sequence.

Some FPGAs, such as the Virtex™ FPGA family, available from Xilinx, Inc. of San Jose, Calif., can be programmed to incorporate blocks with pre-designed functionalities, i.e., “cores.” A core can include a predetermined set of configuration bits that program the FPGA to perform one or more functions. Alternatively, a core can include source code or schematics that describe the logic and connectivity of a design. Typical cores can provide, but are not limited to, digital signal processing (DSP) functions, memories, storage elements, and math functions. Some cores include an optimally floorplanned layout targeted to a specific family of FPGAs. Cores can also be parameterizable, i.e., allowing the user to enter parameters to activate or change certain core functionality.

Conventionally, cores have been targeted to a lowest common denominator for deployment across FPGAs of a family. This in part has been due to not knowing where in the FPGA programmable circuitry (“FPGA fabric”) a user may instantiate a core. Additionally, one or more cores may be part of an overall user design, and thus integration and verification of such overall design includes each core used therein. Furthermore, because one or more cores may be part of the overall user design, each of such cores may be recompiled each time a user's design is changed. This recompilation may lead to variation in behavior, which may lead to issues with design convergence.

To avoid complexity associated with system level designs involving instantiation of a user design including one or more cores in FPGA fabric, Application Specific Standard Products (ASSPs) have been used with FPGAs. Basically, the ASSP takes the place of the core in the user design. Use of an ASSP may save time with respect to system integration and verification issues, as customer off-the-shelf (COTS) ASSPs having known functional and timing compliance may be “black boxed.”

However, use of ASSPs means having to use a widely accepted design protocol, as ASSPs conventionally are not made for an industry known design protocol if such is not widely accepted. Furthermore, ASSPs may not support optional features of such widely accepted protocols. Lastly, use of an ASSP means that the ASSP has to be interfaced with other ICs on a circuit board including the FPGA, and use of such ASSP takes up circuit board space and thermal budget.

Still others have incorporated FPGA hardware into an Application Specific Integrated Circuit (ASIC). However, such an FPGA-ASIC hybrid has conventionally been too costly in some applications due to developmental costs of the FPGA-ASIC hybrid. Additionally, FPGA-ASIC hybrids may have too long a time-to-market delay when compared with using COTS ASSPs and FPGAs in combination.

Lastly, a Programmable System-on-Chip (PSOC) may be used. A PSOC is an ASSP with fixed functionality integration of one or more interfaces together with a programmable fabric region. However, such fixed function interfaces limit application of PSoCs.

SUMMARY OF THE INVENTION

One or more aspects of the invention generally relate to a pre-programmed integrated circuit including programmable logic.

An aspect of the invention relates generally to a system including: nonvolatile memory capable of having first data stored therein and an integrated circuit coupled with the nonvolatile memory. The first data is associated with a predetermined design, and the integrated circuit includes programmable logic having a user region and a reserved region. The integrated circuit is configured to obtain the first data from the nonvolatile memory for instantiation of the predetermined design in the reserved region.

Another aspect relates generally to a method of providing a system. The method includes: coupling nonvolatile memory with an integrated circuit, where the integrated circuit has programmable logic that is partitioned into a user region and a reserved region; and preloading first data associated with a predetermined design in the nonvolatile memory.

DETAILED DESCRIPTION OF THE DRAWINGS

In the following description, numerous specific details are set forth to provide a more thorough description of the specific embodiments of the invention. It should be apparent, however, to one skilled in the art, that the invention may be practiced without all the specific details given below. In other instances, well known features have not been described in detail so as not to obscure the invention. For ease of illustration, the same number labels are used in different diagrams to refer to the same items; however, in alternative embodiments the items may be different.

As noted above, advanced FPGAs can include several different types of programmable logic blocks in the array. For example,FIG. 1illustrates an FPGA architecture100that includes a large number of different programmable tiles including multi-gigabit transceivers (MGTs101), configurable logic blocks (CLBs102), random access memory blocks (BRAMs103), input/output blocks (IOBs104), configuration and clocking logic (CONFIG/CLOCKS105), digital signal processing blocks (DSPs106), specialized input/output blocks (I/O107) (e.g., configuration ports and clock ports), and other programmable logic108such as digital clock managers, analog-to-digital converters, system monitoring logic, and so forth. Some FPGAs also include dedicated processor blocks (PROC110).

For example, a CLB102can include a configurable logic element (CLE112) that can be programmed to implement user logic plus a single programmable interconnect element (INT111). A BRAM103can include a BRAM logic element (BRL113) in addition to one or more programmable interconnect elements. Typically, the number of interconnect elements included in a tile depends on the height of the tile. In the pictured embodiment, a BRAM tile has the same height as four CLBs, but other numbers (e.g., five) can also be used. A DSP tile106can include a DSP logic element (DSPL114) in addition to an appropriate number of programmable interconnect elements. An IOB104can include, for example, two instances of an input/output logic element (IOL115) in addition to one instance of the programmable interconnect element (INT111). As will be clear to those of skill in the art, the actual I/O pads connected, for example, to the I/O logic element115are manufactured using metal layered above the various illustrated logic blocks, and typically are not confined to the area of the input/output logic element115.

In the pictured embodiment, a columnar area near the center of the die (shown shaded inFIG. 1) is used for configuration, clock, and other control logic. Horizontal areas109extending from this column are used to distribute the clocks and configuration signals across the breadth of the FPGA.

Some FPGAs utilizing the architecture illustrated inFIG. 1include additional logic blocks that disrupt the regular columnar structure making up a large part of the FPGA. The additional logic blocks can be programmable blocks and/or dedicated logic. For example, the processor block PROC110spans several columns of CLBs and BRAMs.

Note thatFIG. 1is intended to illustrate only an exemplary FPGA architecture. For example, the numbers of logic blocks in a column, the relative width of the columns, the number and order of columns, the types of logic blocks included in the columns, the relative sizes of the logic blocks, and the interconnect/logic implementations included at the top ofFIG. 1are purely exemplary. For example, in an actual FPGA more than one adjacent column of CLBs is typically included wherever the CLBs appear, to facilitate the efficient implementation of user logic, but the number of adjacent CLB columns varies with the overall size of the FPGA.

An IC product is described where an FPGA semiconductor die (“die”) and a flash memory die are coupled with one another. In another example, the flash memory die and the FPGA die may be in a same IC package. Alternatively, an array of flash memory may be integrated in the FPGA die. Thus, either an integrated die or a stacked die package may be used.

FIG. 2is a block diagram depicting an exemplary embodiment of stacked die package200. Stacked die package200is an IC that includes flash memory die201and FPGA die202coupled to one another. In another example, a flash memory package may be stacked with a packaged FPGA, where the packaged FPGA may include contacts or an interface for the flash memory. Flash memory die201is preloaded with at least one configuration bit stream core (“core”)210. Such preloading may be done by a manufacturer of stacked die package200. Alternatively, such preloading may be done by an intermediary in the supply chain between the manufacturer of stacked die package200and an end user thereof. By “preloading,” “preloaded,” or “preload,” it is generally meant loading of at least one core in nonvolatile memory for instantiation in a reserved region as described herein.

A flash memory may be used as such nonvolatile memory; however, other types of nonvolatile memory may be used instead of flash memory. Some details regarding stacked die package200, such as pin-outs, wire bonding or other die-to-die coupling, are not described for purposes of clarity.

FIG. 3is a block diagram depicting an exemplary embodiment of an integrated circuit die300. Integrated circuit die300may include programmable logic and flash memory array301having a memory interface313. A core310, and optionally a core311, are preloaded in flash memory array301of integrated circuit300. In some examples, integrated circuit die300may be an FPGA, such as FPGA100.FIG. 3is just a block diagram representing an integrated circuit including a user area303and reserved area302, sizes, shapes, and locations of such areas, e.g., areas302and303, may be different from what is illustratively shown inFIG. 3.

Integrated circuit300further includes programmable logic320, a reserved region302of which is reversed for instantiation of cores310and311. Examples of programmable logic320are described with reference to FPGA100ofFIG. 1. For purposes of clarity and not limitation, the following description is in terms of integrated circuit dies300even though much of such description may be applied to stacked die package200as shall be apparent.

The instantiation of core310, and optionally core311, provides a boundary interface312instantiated in reserved region302. Even though both of cores310and311may be instantiated in reserved region302, for purposes of clarity only core310is described as being instantiated in reserved region302.

An unreserved or user programmable region (“user region”)303of programmable logic may be used to instantiate a user design333. By having boundary interface312be predetermined or otherwise predictable, user design333may be configured a priori for coupling to a core310instantiated in reversed area302. For example, reserved region302and user region303may generally be mutually exclusive.

Thus generally as part of or after a power on cycle, programming information stored in flash memory, such as core310, may be used to program a reserved region302of programmable logic320leaving the rest of programmable logic320, such as for example user region303, unprogrammed.

With respect to an end user, reserved region302may thus appear as part of a set of preexisting features of integrated circuit die300. Thus, FPGA may be preprogrammed with core310for instantiation in reserved region302to provide a protocol compliant interface. For example, such a protocol compliant interface may be a peripheral component interconnect (“PCI”) interface or form thereof may be instantiated in reserved region302responsive to a core310. Other types of protocol compliant interfaces may be used. Another example for core310may be a signal processing macro which may include one or more DSP blocks of integrated circuit300, as well as other resources of programmable logic320.

Furthermore, a core310may be in part field programmed responsive to user selection from a set of optional parameters. For example, data width of a bus associated with boundary interface312may be set by a user responsive to a user selected input parameter of core310. For example, depth of first-in/first-out buffers interfaced with a serial transceiver, such as an MGT, may be field programmable parameter of core310for a signal processing macro with a programmable data width. Other types of field selectable parameters for boundary interface312may be used and may depend on the protocol of the protocol compliant interface being instantiated.

By specifying resources to use in programmable logic320of reversed region302, as well as specific locations within reserved region302, higher performance than that conventionally available with a conventional core, may be obtained. Because of the predictability of the instantiation of core310, core310may be highly optimized for performance, including reliable timing.

Furthermore, because of the flexibility in the instantiation of core310, core310may include customized features. For example, a protocol, such as a communication or interface protocol, may have optional features which are not part of a standard set of protocol features owing to any of a variety of factors. However, because core310may be customized to a user's request, core310may include functionality associated with one or more optional features of a protocol as well as standard features thereof.

From users point of view, it should be appreciated that reversed region302which may be preprogrammed, namely programmed with a manufacturers preloaded core310, may not be visible to a user. In fact a user may be masked off from being able to write to reserved region302. However, the interface, such as boundary interface312provides wrapper logic allowing core310to predictably be coupled to after instantiation in reserve region30.

Thus, user design333for instantiation in user region303may be designed with a prior knowledge of boundary interface312. Furthermore, in addition to possibly the pins or points of contact to boundary interface312, configuration attributes associated with boundary interface312may be predictable, including timing, control signaling, latency, and other configuration attributes.

By preloading core310in nonvolatile memory, such as flash memory array301, as part of delivering an integrated circuit product, such as integrated circuit300or an FPGA (e.g., FPGA100ofFIG. 1), the integrated circuit product may appear more like an ASSP. In other words, a user may only focus on user region303for instantiation of user design333and implementation issues previously associated with inclusion of a core in such user design may be generally reduced to a fixed set of parameters. For example, circuitry for a protocol, as well as timing closure associated with such circuitry, may no longer concern a user due to predictability of core310. By freeing a user from having to deal with many design issues previously associated with inclusion of a core in a user design, time to market for such user design may be reduced.

For example, core310may have well defined functions that have a high demand in an industry, such as protocols like PCI Express or Gigabit Ethernet. However, less popular functions for these protocols or less popular protocols, which were previously unavailable due to insufficient demand, may now be included. By having cores supply popular protocols with or without optional features or supply less popular protocols for instantiation in programmable logic circuitry, FPGAs may be configured responsive to a user's input without having to have an extensively stratified inventory of FPGA platforms to support such user input. Rather, such user input may be supported by having a variety of cores from which to select.

In addition to reducing burden for system level verification timing closures and integration by providing a core310with reliable predictability, it should further be appreciated that core310being apart from a configuration bitstream used to provide user design333need not be recompiled each time user design333is revised. In other words, boundary interface312with respect to a user design333is generally a static interface subject a core310capable of user selectable parameterization. But once all user parametric input is loaded, it should still be understood that boundary interface312is predictable.

Thus if a user changes user design333, not only is recompilation time reduced by not having to recompile cores310, but verification of software behavior is enhanced as changes which may affect performance or other issues may be more readily isolated to user design333. Furthermore, if a protocol were to change, it should be appreciated that core310may be updated in contrast to immutable hardware. Moreover, if a problem was later discovered with core310, core310may be updated with a patch or fix in contrast to immutable hardware. Thus, the ability to provide an upgrade or update path which may be instantiated in programmable circuitry has advantages over predetermined functions that are not changeable owing to instantiation in hardware. Core310with a patch or a fix may entirely replace a previously loaded core310without such patch or fix. Alternatively, rather than entirely replacing core310, configuration data patches or fixes may be incrementally written to nonvolatile memory for a previously loaded core310.

Memory interface313may be tailored circuitry for loading core310into flash memory array301, as well as for configuring reserved region302with core310. FPGAs available from Xilinx, Inc. of San Jose, Calif., include an internal configuration interface, namely an Internal Configuration Access Port (ICAP), which may be used for internal configuration, namely configuration of reserved region302. Thus, partial configurability of integrated circuit300may be used for configuring or reconfiguring reserved region302. Furthermore, by using an ICAP, reserved region302whether prior to instantiation and operation of user design333or dynamically while operating user design333, may be configured or reconfigured.

FIG. 4is a flow diagram depicting an exemplary embodiment of an IC provisioning and use flow400. At401, nonvolatile memory with an integrated circuit including programmable logic, such as integrated circuit300, is provided. Such nonvolatile memory, as previously described, may be flash memory array301. As previously mentioned, integrated circuit300is described for purposes of clarity and not limitation as stacked die package200may be used instead of integrated circuit300. Furthermore, though the example of an FPGA is used, it should be appreciated that any integrated circuit with programmable logic in accordance with the description herein may be used.

The remainder of flow400is described with simultaneous reference toFIGS. 3 and 4.

At402, core310for instantiation in reserved region302of programmable logic circuitry320is developed and tested. As core310is developed and tested at402for reserved region302, the specific locations in reserved region302may be called out. Core310may therefore call out particular traces and particular circuitry, even down to a gate level, located within reserved region302. It should be understood that a manufacturer of an integrated circuit, such as an FPGA or other integrated circuit, may have a more highly developed understanding of the circuitry in reserved region302. Using this more adept understanding, core310may call out specific gates, specific lines, and other circuitry for a “bottom-up” design flow.

Because of this highly detailed and integrated relationship between programmable circuitry of reserved region302and core310, performance and reliance of core310may be greater than that of a conventional core. Furthermore, a user may request particular features to be included, and thus a core310may include either or both popular functions or less popular functions as requested by a user. Though it is possible to design cores to cover any possible function, economies of scale for development of such cores may be problematic. Accordingly, features may be included in cores if a use threshold is met, though such use threshold need not be set as high as to be limited to only required features of a standard.

At403, the core developed and tested at402may be preloaded into flash memory array301. Memory interface313, which may be included as part of integrated circuit300, may facilitate the coupling of core310for instantiation in reserved region302. Alternatively, memory interface312may be provided in part using programmable logic circuitry.

In addition to the ability to relatively easily change programming of cores for providing to customers with different requested functions, an FPGA vendor may have a wide selection of possible features without having a stratified inventory of parts as previously described, and further may have more available FPGAs to use as those with reserved region regional defects may be used. An FPGA manufacturer may have a platform of FPGAs which perform various functions subject to which cores are loaded into nonvolatile memory of such FPGAs. To some extent, different functionalities may be provided which may appear as customized integrated circuits for customers.

Because there may be design problems in a hardware functional blocks of such FPGAs, such design problems, which were fixed using generally available spare gates, may now be fixed using spare gates in a reserved region302. For example, an MGT is presently used in conjunction with a calibration block. This calibration block was added to correct a design problem and was previously supplied as a configuration bitstream core or other data stored in nonvolatile memory, such as a flash memory, to be incorporated in user design333. However, now such a calibration block may be a core, such as core311, which is stored in flash memory array301. Thus, the user no longer has to be aware of additional circuitry to fix a design, because core311may be instantiated in programmable logic of reserved region302without affecting predictability of boundary interface312. Thus, fixes or patches may be preprogrammed into flash memory array301of integrated circuit300such that they are transparent to a user.

Additionally, there may be circuit defects in one or both of reserved region302and user region303which are identified during a testing phase of integrated circuit300. However, because core310may be configured to avoid such defects, defective routes or memory cells may be bypassed by selecting functionally equivalent working alternatives in calling out circuitry resources for instantiation of core310in reserved region302. Thus, a die with some defects may still be used if those defects for example occur within reserve region302and each core to be instantiated in such region302does not use those defective circuits. Such one or more defects in the programmable logic, e.g., reserved region302, may not be noticeable by a user, and bypassing such one or more defects may increase semiconductor die yield.

After preloading core310in flash memory array301, which is accessible by programmable logic circuitry320of reserved region302at403, at404a manufacturer may specify an allocated user region303of programmable logic circuitry320. User region may be for instantiation of one or more user designs333. The allocated user region303may be associated with boundary interface312for predictably coupling with an instantiated core310in reserved region302. One or more user designs333may be instantiated before or after instantiation of core310.

At405, a configuration interface, which may form part of memory interface313, may be used to instantiate core310in user region302. Optionally, at406a user may field program core310with parametric input, provided core310is configured to receive such parametric input. At407, integrated circuit300may be partially configured or reconfigured by instantiating a user design333in user region303.

Thus it should be appreciated that by affectively black boxing cores for use by a user where a predictable boundary interface is provided, customers may be able to design circuits for instantiation in such an FPGA more readily. Furthermore, a user may select a preprogrammed offering from an FPGA manufacturer which more closely matches their user design or their intended user design. Value added features or protocol optional features may be included in such cores by a manufacturer, even though such value added or optional features are not presently widely used.

Moreover, time to market for the user may be reduced as a user may focus on instantiating its user design333in a user region303with coupling to boundary interface312. Thus, run time and system integration issues for a user are significantly reduced because what amounts to the preprogrammed reserved region is presented to a user as a black box, though optionally with customizable features, a predictable boundary interface312.