Semiconductor structure with concave blocking dielectric sidewall and method of making thereof by isotropically etching the blocking dielectric layer

A first blocking dielectric layer is formed in a memory opening through a stack of an alternating plurality of material layers and insulator layers. A spacer with a bottom opening is formed over the first blocking dielectric layer by deposition of a conformal material layer and an anisotropic etch. A horizontal portion of the first blocking dielectric layer at a bottom of the memory opening can be etched by an isotropic etch process that minimizes overetch into the substrate. An optional additional blocking dielectric layer, at least one charge storage element, a tunneling dielectric, and a semiconductor channel can be sequentially formed in the memory opening to provide a three-dimensional memory stack.

FIELD

The present disclosure relates generally to the field of three-dimensional structures, and specifically to three-dimensional memory structures including memory films, and methods of manufacturing the same.

BACKGROUND

Three-dimensional memory devices can store multiple bits in a single memory stack structure. A memory film is employed in three-dimensional memory devices to store electrical charges. The memory film needs to provide a tunneling path for electrical charges on the front side, and to prevent leakage of stored electrical charges through the backside.

SUMMARY

According to an aspect of the present disclosure, a method of fabricating a memory device is provided. A stack including an alternating plurality of material layers and insulator layers is formed over a substrate. A memory opening extending through the stack is formed. A first blocking dielectric layer is formed in the memory opening and over the stack. A contiguous material layer is formed over the first blocking dielectric layer. A spacer is formed by anisotropically etching the contiguous material layer. A top surface of a horizontal portion of the first blocking dielectric layer is physically exposed within an opening in the spacer. The horizontal portion of the first blocking dielectric layer is etched at a bottom of the memory opening through the opening in the spacer. A top semiconductor surface of the substrate is physically exposed at a bottom of the memory opening. A set of material layers is formed on the top semiconductor surface of the substrate. The set of material layers comprise a memory material layer, a tunneling dielectric layer, and a semiconductor channel.

According to another aspect of the present disclosure, a semiconductor structure is provided, which comprises a stack including an alternating plurality of electrically conductive layers and insulator layers located over a semiconductor substrate, a memory opening extending through the stack, and a first blocking dielectric layer. The first blocking dielectric layer is located in the memory opening, vertically extends contiguously through the alternating plurality of electrically conductive layers and insulator layers, comprises a dielectric metal oxide having a dielectric constant greater than 7.9, and contacts a sidewall of the memory opening and a first surface of the semiconductor substrate. The first blocking dielectric layer comprises a planar bottommost surface and a concave inner sidewall that adjoins an inner periphery of the planar bottommost surface. The semiconductor structure further comprises an additional blocking dielectric layer located inside of the first blocking dielectric layer and contacting at least a portion of an inner sidewall of the first blocking dielectric layer, a memory material layer contacting an inner sidewall of the additional blocking dielectric layer and a top surface of a horizontal portion of the additional blocking dielectric layer, and a semiconductor channel laterally surrounded by the memory material layer and electrically contacting a second surface of the semiconductor substrate.

DETAILED DESCRIPTION

As discussed above, the present disclosure is directed to three-dimensional memory structures including memory films, and methods of manufacturing the same, the various aspects of which are described below. The embodiments of the disclosure can be employed to form various structures including a multilevel metal interconnect structure, a non-limiting example of which includes semiconductor devices such as three-dimensional monolithic memory array devices comprising a plurality of NAND memory strings. The drawings are not drawn to scale. Multiple instances of an element may be duplicated where a single instance of the element is illustrated, unless absence of duplication of elements is expressly described or clearly indicated otherwise. Ordinals such as “first,” “second,” and “third” are employed merely to identify similar elements, and different ordinals may be employed across the specification and the claims of the instant disclosure. As used herein, a first element located “on” a second element can be located on the exterior side of a surface of the second element or on the interior side of the second element. As used herein, a first element is located “directly on” a second element if there exist a physical contact between a surface of the first element and a surface of the second element.

Referring toFIG. 1, an exemplary structure according to an embodiment of the present disclosure is illustrated, which can be employed, for example, to fabricate a device structure containing vertical NAND memory devices. The exemplary structure includes a substrate, which can be a semiconductor substrate. The substrate can include a substrate semiconductor layer9. The substrate semiconductor layer9is a semiconductor material layer, and can include at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. The substrate can have a major surface7, which can be, for example, a topmost surface of the substrate semiconductor layer9. The major surface7can be a semiconductor surface. In one embodiment, the major surface7can be a single crystalline semiconductor surface.

As used herein, a “semiconductor material” refers to a material having electrical conductivity in the range from 1.0×10−6S/cm to 1.0×105S/cm, and is capable of producing a doped material having electrical resistivity in a range from 1.0 S/cm to 1.0×105S/cm upon suitable doping with an electrical dopant. As used herein, an “electrical dopant” refers to a p-type dopant that adds a hole to a valence band within a band structure, or an n-type dopant that adds an electron to a conduction band within a band structure. As used herein, a “conductive material” refers to a material having electrical conductivity greater than 1.0×105S/cm. As used herein, an “insulator material” or a “dielectric material” refers to a material having electrical conductivity less than 1.0×10−6S/cm. All measurements for electrical conductivities are made at the standard condition. Optionally, at least one doped well (not expressly shown) can be formed within the substrate semiconductor layer9.

At least one semiconductor device for a peripheral circuitry can be formed on a portion of the substrate semiconductor layer9. The at least one semiconductor device can include, for example, field effect transistors. For example, at least one shallow trench isolation structure120can be formed by etching portions of the substrate semiconductor layer9and depositing a dielectric material therein. A gate dielectric layer, at least one gate conductor layer, and a gate cap dielectric layer can be formed over the substrate semiconductor layer9, and can be subsequently patterned to form at least one gate structure (150,152,154,158), each of which can include a gate dielectric150, at least one gate electrode (152,154), and a gate cap dielectric. A gate electrode (152,154) may include a stack of a first gate electrode portion152and a second gate electrode portion154. At least one gate spacer156can be formed around the at least one gate structure (150,152,154,158) by depositing and anisotropically etching a conformal dielectric layer. Active regions130can be formed in upper portions of the substrate semiconductor layer9, for example, by introducing electrical dopants employing the at least one gate structure (150,152,154,158) as masking structures. Additional masks may be employed as needed. The active region130can include source regions and drain regions of field effect transistors. A first dielectric liner161and a second dielectric liner162can be optionally formed. Each of the first and second dielectric liners (161,162) can comprise a silicon oxide layer, a silicon nitride layer, and/or a dielectric metal oxide layer. In an illustrative example, the first dielectric liner161can be a silicon oxide layer, and the second dielectric liner162can be a silicon nitride layer. In one embodiment, the substrate can comprise a silicon substrate. The least one semiconductor device for the peripheral circuitry can contain a driver circuit for memory devices to be subsequently formed, which can include at least one NAND device.

A dielectric material such as silicon oxide can be deposited over the at least one semiconductor device, and can be subsequently planarized to form a planarization dielectric layer170. In one embodiment the planarized top surface of the planarization dielectric layer170can be coplanar with a top surface of the dielectric liners (161,162). Subsequently, the planarization dielectric layer170and the dielectric liners (161,162) can be removed from an area to physically expose a top surface of the substrate semiconductor layer9.

An option semiconductor material layer10can be formed on the top surface of the substrate semiconductor layer9by deposition of a single crystalline semiconductor material, for example, by selective epitaxy. The deposited semiconductor material can be the same as, or can be different from, the semiconductor material of the substrate semiconductor layer9. The deposited semiconductor material can be any material that can be employed for the semiconductor substrate layer9as described above. The single crystalline semiconductor material of the semiconductor material layer10can be in epitaxial alignment with the single crystalline structure of the substrate semiconductor layer9. Portions of the deposited semiconductor material located above the top surface of the planarization dielectric layer170can be removed, for example, by chemical mechanical planarization (CMP). In this case, the semiconductor material layer10can have a top surface that is coplanar with the top surface of the planarization dielectric layer170.

Optionally, a dielectric pad layer12can be formed above the semiconductor material layer10and the planarization dielectric layer170. The dielectric pad layer12can be, for example, silicon oxide layer. The thickness of the dielectric pad layer12can be in a range from 3 nm to 30 nm, although lesser and greater thicknesses can also be employed.

At least one optional shallow trench can be formed through the dielectric pad layer12and an upper portion of the semiconductor material layer10. The pattern of the at least one shallow trench can be selected such that lower select gate electrodes can be subsequently formed therein. For example, a lower select gate device level may be fabricated as described in U.S. patent application Ser. No. 14/133,979, filed on Dec. 19, 2013, U.S. patent application Ser. No. 14/225,116, filed on Mar. 25, 2014, and/or U.S. patent application Ser. No. 14/225,176, filed on Mar. 25, 2014, all of which are incorporated herein by reference.

A lower select gate structure20can be formed in each of the at least one shallow trench, for example, by forming a gate dielectric layer and at least one conductive material layer, and removing portions of the gate dielectric layer and the at least one conductive material layer from above the top surface of the dielectric pad layer12, for example, by chemical mechanical planarization. Each lower select gate structure20can include a gate dielectric22and a gate electrode (24,26). In one embodiment, each gate electrode (24,26) can include a metallic liner24and a conductive material portion26. The metallic liner24can include, for example, TiN, TaN, WN, or a combination thereof. The conductive material portion26can include, for example, W, Al, Cu, or combinations thereof. At least one optional shallow trench isolation structure (not shown) and/or at least one deep trench isolation structure (not shown) may be employed to provide electrical isolation among various semiconductor devices that are present, or are to be subsequently formed, on the substrate.

A dielectric cap layer31can be optionally formed. The dielectric cap layer31includes a dielectric material, and can be formed directly on top surfaces of the gate electrodes (24,26). Exemplary materials that can be employed for the dielectric cap layer31include, but are not limited to, silicon oxide, a dielectric metal oxide, and silicon nitride (in case the material of second material layers to be subsequently formed is not silicon nitride). The dielectric cap layer31provides electrical isolation for the gate electrodes (24,26).

A stack including an alternating plurality of first material layers and second material layers can be formed over the substrate (9,10). For example, the alternating plurality of first material layers and second material layers can be formed on the top surface of the dielectric cap layer31. In one embodiment, the first material layers can be insulator layers32, and the stack can include an alternating plurality of insulator layers32and material layers (i.e., the second material layers). As used herein, an alternating plurality of first elements and second elements refers to a structure in which instances of the first elements and instances of the second elements alternate. Each instance of the first elements that is not an end element of the alternating plurality is adjoined by two instances of the second elements on both sides, and each instance of the second elements that is not an end element of the alternating plurality is adjoined by two instances of the first elements on both ends. The first elements may have the same thickness thereamongst, or may have different thicknesses. The second elements may have the same thickness thereamongst, or may have different thicknesses. The alternating plurality of first material layers and second material layers may begin with an instance of the first material layers or with an instance of the second material layers, and may end with an instance of the first material layers or with an instance of the second material layers. In one embodiment, an instance of the first elements and an instance of the second elements may form a unit that is repeated with periodicity within the alternating plurality.

Each first material layer includes a first material, and each second material layer includes a second material that is different from the first material. In one embodiment, each first material layer can be an insulator layer32, and each second material layer can be a sacrificial material layer. In this case, the stack can include an alternating plurality of insulator layers32and sacrificial material layers42.

The stack of the alternating plurality is herein referred to as an alternating stack (32,42). In one embodiment, the alternating stack (32,42) can include insulator layers32composed of the first material, and sacrificial material layers42composed of a second material different from that of insulator layers32. The first material of the insulator layers32can be at least one electrically insulating material. As such, each insulator layer32can be an electrically insulating material layer. Electrically insulating materials that can be employed for the insulator layers32include, but are not limited to silicon oxide (including doped or undoped silicate glass), silicon nitride, silicon oxynitride, organosilicate glass (OSG), spin-on dielectric materials, dielectric metal oxides that are commonly known as high dielectric constant (high-k) dielectric oxides (e.g., aluminum oxide, hafnium oxide, etc.) and silicates thereof, dielectric metal oxynitrides and silicates thereof, and organic insulating materials. In one embodiment, the first material of the insulator layers32can be silicon oxide.

In one embodiment, the insulator layers32can include silicon oxide, and sacrificial material layers can include silicon nitride sacrificial material layers. The first material of the insulator layers32can be deposited, for example, by chemical vapor deposition (CVD). For example, if silicon oxide is employed for the insulator layers32, tetraethyl orthosilicate (TEOS) can be employed as the precursor material for the CVD process. The second material of the sacrificial material layers42can be formed, for example, CVD or atomic layer deposition (ALD).

The sacrificial material layers42can be suitably patterned so that conductive material portions to be subsequently formed by replacement of the sacrificial material layers42can function as electrically conductive electrodes, such as the control gate electrodes of the monolithic three-dimensional NAND string memory devices to be subsequently formed. The sacrificial material layers42may comprise a portion having a strip shape extending substantially parallel to the major surface7of the substrate.

Optionally, an insulating cap layer70can be formed over the alternating stack (32,42). The insulating cap layer70includes a dielectric material that is different from the material of the sacrificial material layers42. In one embodiment, the insulating cap layer70can include a dielectric material that can be employed for the insulator layers32as described above. The insulating cap layer70can have a greater thickness than each of the insulator layers32. The insulating cap layer70can be deposited, for example, by chemical vapor deposition. In one embodiment, the insulating cap layer70can be a silicon oxide layer.

Subsequently, a lithographic material stack (not shown) including at least a photoresist layer can be formed over the insulating cap layer70and the alternating stack (32,42), and can be lithographically patterned to form openings therein. The pattern in the lithographic material stack can be transferred through the insulating cap layer70and through entirety of the alternating stack (32,42) by at least one anisotropic etch that employs the patterned lithographic material stack as an etch mask. Portions of the alternating stack (32,42) underlying the openings in the patterned lithographic material stack are etched to form memory openings49. In other words, the transfer of the pattern in the patterned lithographic material stack through the alternating stack (32,42) forms the memory openings49that extend through the alternating stack (32,42). The chemistry of the anisotropic etch process employed to etch through the materials of the alternating stack (32,42) can alternate to optimize etching of the first and second materials in the alternating stack (32,42). The anisotropic etch can be, for example, a series of reactive ion etches. Optionally, the dielectric cap layer31may be used as an etch stop layer between the alternating stack (32,42) and the substrate. The sidewalls of the memory openings49can be substantially vertical, or can be tapered. The patterned lithographic material stack can be subsequently removed, for example, by ashing.

The memory openings49are formed through the dielectric cap layer31and the dielectric pad layer12so that the memory openings49extend from the top surface of the alternating stack (32,42) to the top surface of the semiconductor material layer10within the substrate between the lower select gate electrodes (24,26). In one embodiment, an overetch into the semiconductor material layer10may be optionally performed after the top surface of the semiconductor material layer10is physically exposed at a bottom of each memory opening49. The overetch may be performed prior to, or after, removal of the lithographic material stack. In other words, the recessed surfaces of the semiconductor material layer10may be vertically offset from the unrecessed top surfaces of the semiconductor material layer10by a recess depth. The recess depth can be, for example, in a range from 1 nm to 50 nm, although lesser and greater recess depths can also be employed. The overetch is optional, and may be omitted. If the overetch is not performed, the bottom surface of each memory opening49can be coplanar with the topmost surface of the semiconductor material layer10. Each of the memory openings49can include a sidewall (or a plurality of sidewalls) that extends substantially perpendicular to the topmost surface of the substrate. The region in which the array of memory openings49is formed is herein referred to as a device region. The substrate semiconductor layer9and the semiconductor material layer10collectively constitutes a substrate (9,10), which can be a semiconductor substrate. Alternatively, the optional semiconductor material layer10can be omitted, and the memory openings49can extend to the top surface of the substrate semiconductor layer9.

A memory stack structure can be formed in each of the memory opening employing various embodiments of the present disclosure.FIGS. 2A-2Fillustrate sequential vertical cross-sectional views of a memory opening within the exemplary structure during formation of a first exemplary memory stack structure according to a first embodiment of the present disclosure. Formation of the first exemplary memory stack structure can be performed within each of the memory openings49in the exemplary structure illustrated inFIG. 1.

Referring toFIG. 2A, a memory opening49is illustrated in a magnified view. The memory opening49extends through the insulating cap layer70, the alternating stack (32,42), the dielectric cap layer31, the dielectric pad layer12, and optionally into an upper portion of the semiconductor material layer10. The recess depth of the bottom surface of each memory opening with respect to the top surface of the semiconductor material layer10is herein referred to as first recess depth. The first recess depth can be in a range from 0 nm to 30 nm, although greater recess depths can also be employed. Optionally, the sacrificial material layers42can be laterally recessed partially to form lateral recesses (not shown), for example, by an isotropic etch.

A first blocking dielectric layer501and a second blocking dielectric layer503L can be sequentially deposited in each memory opening49. Each of the first blocking dielectric layer501and the second blocking dielectric layer503L can be a continuous material layer.

In one embodiment, the first blocking dielectric layer501can be deposited on the sidewalls of each memory opening49by a conformal deposition method. The first blocking dielectric layer501includes a dielectric material, which can be a dielectric metal oxide. As used herein, a dielectric metal oxide refers to a dielectric material that includes at least one metallic element and at least oxygen. The dielectric metal oxide may consist essentially of the at least one metallic element and oxygen, or may consist essentially of the at least one metallic element, oxygen, and at least one non-metallic element such as nitrogen. In one embodiment, the first blocking dielectric layer501can include a dielectric metal oxide having a dielectric constant greater than 7.9, i.e., having a dielectric constant greater than the dielectric constant of silicon nitride.

Non-limiting examples of dielectric metal oxides include aluminum oxide (Al2O3), hafnium oxide (HfO2), lanthanum oxide (LaO2), yttrium oxide (Y2O3), tantalum oxide (Ta2O5), silicates thereof, nitrogen-doped compounds thereof, alloys thereof, and stacks thereof. The first blocking dielectric layer501can be deposited, for example, by chemical vapor deposition (CVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), liquid source misted chemical deposition, or a combination thereof. The thickness of the first blocking dielectric layer501can be in a range from 1 nm to 6 nm, although lesser and greater thicknesses can also be employed. In one embodiment, the first blocking dielectric layer501includes aluminum oxide.

The second blocking dielectric layer503L is a contiguous material layer that is formed over the first blocking dielectric layer501. In one embodiment, the second blocking dielectric layer503L includes a dielectric material that is different from the dielectric material of the first blocking dielectric layer501. In one embodiment, the dielectric material of the second blocking dielectric layer503L can be silicon oxide, silicon nitride, or silicon oxynitride. The second blocking dielectric layer503L can be deposited, for example, by chemical vapor deposition (CVD) or atomic layer deposition (ALD). The thickness of the second blocking dielectric layer503L can be in a range from 1 nm to 6 nm, although lesser and greater thicknesses can also be employed. In one embodiment, the second blocking dielectric layer503L includes silicon oxide. A cavity49′ is present within each portion of the memory opening49that is not filled with the first and second blocking dielectric layers (501,503L).

Referring toFIG. 2B, an anisotropic etch can be performed to remove horizontal portions of the second blocking dielectric layer503L. The chemistry of the anisotropic etch can be selective to the material of the first blocking dielectric layer501, i.e., not remove the material of the first blocking dielectric layer501in any substantial quantity while etching the material of the second blocking dielectric layer503L. An opening is formed through a horizontal portion of the second blocking dielectric layer503L at a bottom of the cavity49′ in each memory opening. Each remaining vertical portion of the second blocking dielectric layer503L within each memory opening constitutes a spacer503. Each spacer503can be homeomorphic to a torus. As used herein, an element is homeomorphic to a geometrical shape if the shape of the element can be mapped to the geometrical shape by continuous deformation without creation or destruction of any hole. A top surface of a horizontal portion of the first blocking dielectric layer501is physically exposed at a bottom of the cavity49′ in each memory opening. Each spacer503comprises a dielectric material, and contacts an inner sidewall of the first blocking dielectric layer501.

Referring toFIG. 2C, physically exposed horizontal portions of the first blocking dielectric layer501can be selectively etched by an isotropic etch process using the spacer503as a mask. The portion of the first blocking dielectric layer501overlying the alternating stack (32,42) can be removed during the isotropic etch process. Further, a horizontal portion of the first blocking dielectric layer501at a bottom of the cavity49′ in each memory opening can be etched through the opening in the spacer503. The spacer503is present on the vertical portion of the first blocking dielectric layer501within each memory opening during the isotropic etching of physically exposed portions of the first blocking dielectric layer501. Specifically, a horizontal portion of the first blocking dielectric layer501can be etched at a bottom of each memory opening through the opening in the spacer503. Etching of the horizontal portion of the first blocking dielectric layer501forms a peripheral undercut cavity49P by removing a peripheral portion of the first blocking dielectric layer501underneath the spacer503. The isotropic etch process can be a wet etch process or an isotropic dry etch process. The chemistry of the isotropic etch process can be selected so that the isotropic etch removes the material of the first blocking dielectric layer501selective to the material of the spacer503. The material of the first blocking dielectric layer501is etched isotropically during the isotropic etch process. The top surface503aof the spacer503may be sloped and terminate in an outer tip portion which may or may not extend above the top of the stack after removal of the first blocking dielectric501depending on the etching conditions. Thus, in some configurations of the embodiments of the present disclosure, the spacers503may have an angular profile with a spike portion optionally protruding above the adjacent layers, as shown by the inset in dashed lines inFIG. 2C.

A portion of the first blocking dielectric layer501remains within each memory opening. Each remaining first blocking dielectric layer501can be topologically homeomorphic to a torus. A concave sidewall501asurface is formed on the bottommost portion of the inner surface of the first blocking dielectric layer501because the material of the first blocking dielectric layer501is isotropically removed from a closed shape edge at which the inner surface of the spacer503adjoins the bottom surface of the spacer503. A top semiconductor surface of the substrate (9,10) is physically exposed at a bottom of each memory opening.

Referring toFIG. 2D, a set (504,505L,601) of material layers can be subsequently formed on each physically exposed top semiconductor surface of the substrate (9,10), on the inner sidewall of each spacer503, and over the alternating stack (32,42) and the insulating cap layer70. In one embodiment, the set of material layers can comprise a memory material layer504, a tunneling dielectric layer505L, and an optional first semiconductor channel layer601.

In one embodiment, the memory material layer504can be a charge trapping material including a dielectric charge trapping material, which can be, for example, silicon nitride. Alternatively, the memory material layer504can include a conductive material such as doped polysilicon or a metallic material that is patterned into multiple electrically isolated portions (i.e., floating gates), for example, by being formed within lateral recesses (not shown) into sacrificial material layers42that may be formed prior to formation of the first blocking dielectric layer501. In one embodiment, the memory material layer504includes a silicon nitride layer.

The memory material layer504can be formed as a single memory material layer of homogeneous composition, or can include a stack of multiple memory material layers. The multiple memory material layers, if employed, can comprise a plurality of spaced-apart floating gate material layers that contain conductive materials (e.g., metal such as tungsten, molybdenum, tantalum, titanium, platinum, ruthenium, and alloys thereof, or a metal silicide such as tungsten silicide, molybdenum silicide, tantalum silicide, titanium silicide, nickel silicide, cobalt silicide, or a combination thereof) and/or semiconductor materials (e.g., polycrystalline or amorphous semiconductor material including at least one elemental semiconductor element or at least one compound semiconductor material). Alternatively or additionally, the memory material layer504may comprise an insulating charge trapping material, such as one or more silicon nitride segments. Alternatively, the memory material layer504may comprise conductive nanoparticles such as metal nanoparticles, which can be, for example, ruthenium nanoparticles. The memory material layer504can be formed, for example, by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or any suitable deposition technique for storing electrical charges therein. The thickness of the memory material layer504can be in a range from 2 nm to 20 nm, although lesser and greater thicknesses can also be employed.

The optional first semiconductor channel layer601includes a semiconductor material such as at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the first semiconductor channel layer601includes amorphous silicon or polysilicon. The first semiconductor channel layer601can be formed by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD). The thickness of the first semiconductor channel layer601can be in a range from 2 nm to 10 nm, although lesser and greater thicknesses can also be employed.

The memory material layer504can be deposited in, and fill, the peripheral undercut cavity49P within each memory opening. In one embodiment, a bottommost surface of the memory material layer504can be coplanar with a bottom surface of the first blocking dielectric layer501within a respective memory opening. In one embodiment, the memory material layer504can comprise a charge trapping material or a floating gate material. The bottommost surface of each spacer503contacts an annular horizontal surface of the memory material layer504. Thus, each spacer503comprises a dielectric material, contacts an inner sidewall of the first blocking dielectric layer501in the same memory opening, and contacts an annular horizontal surface of the memory material layer504.

Referring toFIG. 2E, the optional first semiconductor channel layer601, the tunneling dielectric layer505L, and the memory material layer504are sequentially anisotropically etched employing at least one anisotropic etch process. The portions of the first semiconductor channel layer601, the tunneling dielectric layer505L, and the memory material layer504located above the top surface of the insulating cap layer70can be removed by the at least one anisotropic etch process. Further, the portions of the first semiconductor channel layer601, the tunneling dielectric layer505L, and the memory material layer504at a bottom of each cavity49′ can be removed to form openings in remaining portions thereof. Each of the first semiconductor channel layer601, the tunneling dielectric layer505L, and the memory material layer504can be etched by anisotropic etch process.

A vertical portion of the first semiconductor channel layer601remains in each memory opening. Each remaining portion of the tunneling dielectric layer505L constitutes a tunneling dielectric505. A vertical portion of the memory material layer504remains in each memory opening. In one embodiment, the memory material layer504can be a contiguous layer, i.e., can be a charge storage layer. A surface of the semiconductor material layer10(or a top surface of the substrate semiconductor layer9in case the semiconductor material layer10is not present) can be physically exposed underneath the opening through the first semiconductor channel layer601, the tunneling dielectric505, and the memory material layer504. A tunneling dielectric505is embedded within a memory material layer504. The memory material layer504can comprise a charge trapping material or a floating gate material. Within each memory opening, a first blocking dielectric layer501, a spacer503, memory material layer504, and a tunneling dielectric505collectively constitutes a memory film50.

In one embodiment, the first semiconductor channel layer601, the tunneling dielectric505, and the memory material layer504can have vertically coincident sidewalls. As used herein, a first surface is “vertically coincident” with a second surface if there exists a vertical plane including both the first surface and the second surface. Such a vertical plane may, or may not, have a horizontal curvature, but does not include any curvature along the vertical direction, i.e., extends straight up and down.

Referring toFIG. 2F, a second semiconductor channel layer602can be deposited directly on the semiconductor surface of the semiconductor material layer10in the substrate (9,10), and directly on the first semiconductor channel layer601. The second semiconductor channel layer602includes a semiconductor material such as at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the second semiconductor channel layer602includes amorphous silicon or polysilicon. The second semiconductor channel layer602can be formed by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD). The thickness of the second semiconductor channel layer602can be in a range from 2 nm to 10 nm, although lesser and greater thicknesses can also be employed. The second semiconductor channel layer602may partially fill the cavity49′ in each memory opening, or may fully fill the cavity in each memory opening.

In case the cavity49′ in each memory opening is not completely filled by the second semiconductor channel layer602, a dielectric material can be deposited in the cavity49′ to fill any remaining portion of the cavity49′ within each memory opening. The dielectric material can be deposited by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD), or by a self-planarizing deposition process such as spin coating. Portions of the dielectric material deposited above the top surface of the insulating cap layer70can be removed by a recess etch or a planarization process. Further, the remaining portion of the deposited dielectric material after the planarization process can be vertically recessed below the top surface of the insulating cap layer70by a recess etch. The remaining portion of the dielectric material after the recess process constitutes a dielectric core62. The dielectric core62includes a dielectric material such as silicon oxide or organosilicate glass.

The horizontal portion of the second semiconductor channel layer602located above the top surface of the insulating cap layer70can be removed by a planarization process, which can employ a recess etch or chemical mechanical planarization (CMP). A vertical portion of the second semiconductor channel layer602remains within each memory opening.

Each adjoining pair of a first semiconductor channel layer601and a second semiconductor channel layer602collectively constitute a semiconductor channel60through which electrical current can flow when a vertical NAND device including the semiconductor channel60is turned on. A tunneling dielectric505is embedded within each memory material layer504, and laterally surrounds a portion of the semiconductor channel60. Each memory film50can store electrical charges with a macroscopic retention time. As used herein, a macroscopic retention time refers to a retention time suitable for operation of a memory device as a permanent memory device such as a retention time in excess of 24 hours.

Drain regions63can be formed by depositing a doped semiconductor material within each recessed region above the dielectric cores62. The doped semiconductor material can be, for example, doped polysilicon. Excess portions of the deposited semiconductor material can be removed from above the top surface of the insulating cap layer70, for example, by chemical mechanical planarization (CMP) or a recess etch to form the drain regions63.

Within each memory opening, the bottommost surface of the first blocking dielectric layer501contacts a surface of the substrate (9,10), which is herein referred to as a first surface10aof the substrate (9,10). The semiconductor channel60contacts another surface of the substrate (9,10), which is herein referred to as a second surface10bof the substrate (9,10). Further, the memory material layer504contacts a surface of the semiconductor substrate (9,10), which is herein referred to as third surface10cof the semiconductor substrate (9,10). An outer periphery of the third surface adjoins the first surface, and an inner periphery of the third surface adjoins the second surface.

The structure ofFIG. 2Fis a first exemplary memory stack structure, which comprises a first blocking dielectric layer501vertically extending at least from a bottommost layer (e.g., the bottommost sacrificial material layer42) of the stack (32,42) to a topmost layer (e.g., the topmost sacrificial material layer42) of the stack, comprising a dielectric metal oxide having a dielectric constant greater than 7.9, and contacting a sidewall of the memory opening and a first surface of the semiconductor substrate (9,10). The first blocking dielectric layer501comprises a planar bottommost surface and a concave inner sidewall501athat adjoins an inner periphery of the planar bottommost surface. In case the spacer503comprises a dielectric material, the spacer503can be an additional blocking dielectric layer located inside of the first blocking dielectric layer501and contacting at least a portion of an inner sidewall of the first blocking dielectric layer501. A memory material layer504contacts an inner sidewall of the additional blocking dielectric layer (i.e., the spacer503) and a top surface of a horizontal portion of the additional blocking dielectric layer (i.e., the spacer503). A semiconductor channel60is laterally surrounded by the memory material layer504and contacts a second surface of the semiconductor substrate (9,10).

FIGS. 3A-3Dillustrate sequential vertical cross-sectional views of a memory opening within the exemplary structure during formation of a second exemplary memory stack structure within the memory opening according to a second embodiment of the present disclosure. The second exemplary memory stack structure ofFIG. 3Acan be derived from the first exemplary memory stack structure illustrated inFIG. 2Cby depositing an additional blocking dielectric layer507directly on the substrate (9,10) and in the peripheral undercut cavity49P (SeeFIG. 2C) prior to forming the set (504,505L,601; SeeFIG. 2D) of material layers.

The additional blocking dielectric layer507can be formed by conformal deposition of a dielectric material such as silicon oxide, silicon oxynitride, silicon nitride, or a high-k dielectric metal oxide. The additional blocking dielectric layer507can include the same material as, or a different material from, the material of the spacer503. In one embodiment, the additional blocking dielectric layer507can be a silicon oxide layer. The additional blocking dielectric layer507can be deposited, for example, by chemical vapor deposition or atomic layer deposition. The additional blocking dielectric layer507is deposited on an inner sidewall of the spacer503. The peripheral undercut cavity49P (SeeFIG. 2C) within each memory opening can be filled with the additional blocking dielectric layer507. In one embodiment, a bottommost surface of the additional blocking dielectric layer507can be located within a horizontal plane including the bottommost surface of the first blocking dielectric layer501.

Referring toFIG. 3B, the processing steps ofFIG. 2Dare performed to deposit a set of material layers including, for example, a memory material layer504, a tunneling dielectric layer505L, and an optional first semiconductor channel layer601.

Referring toFIG. 3C, the processing steps ofFIG. 2Eare performed to remove horizontal portion of the optional first semiconductor channel layer601, the tunneling dielectric layer505L, and the memory material layer504employing at least one anisotropic etch process. Further, horizontal portions of the additional blocking dielectric layer507are removed by the at least one anisotropic etch, and each portion of the semiconductor substrate (9,10) underlying a cavity49′ can be vertically recessed. Within each memory opening, a memory film50is formed, which comprises, from outside to inside, a first blocking dielectric layer501, a spacer503(which is a second blocking dielectric layer), an additional blocking dielectric layer507, a memory material layer504, and a tunneling dielectric505.

Referring toFIG. 3D, the processing steps ofFIG. 2Fcan be performed to form a semiconductor channel60, a dielectric core62, and a drain region63. The first blocking dielectric layer501contacts a first surface of the semiconductor substrate (9,10). The first surface of the semiconductor substrate (9,10) can contact an annular bottom surface of the first blocking dielectric layer501. The semiconductor channel contacts a second surface of the semiconductor substrate (9,10), which can include a substantially vertical sidewall and a horizontal semiconductor surface adjoining a bottom periphery of the vertical sidewall. The additional blocking dielectric layer507can have a homogeneous material composition throughout the entirety thereof. The additional blocking dielectric layer507contacts a third surface of the semiconductor substrate (9,10). An outer periphery of the third surface adjoins the first surface, and an inner periphery of the third surface adjoins the second surface. The spacer503comprises a dielectric material, contacts an inner sidewall of the first blocking dielectric layer501, and contacts an outer sidewall of the additional blocking dielectric layer507.

The second exemplary memory stack structure comprises a first blocking dielectric layer501vertically extending at least from the bottommost layer of the stack (32,42) to a topmost layer of the stack, comprising a dielectric metal oxide having a dielectric constant greater than 7.9, and contacting a sidewall of the memory opening and a first surface of the semiconductor substrate (9,10). The first blocking dielectric layer501comprises a planar bottommost surface and a concave inner sidewall that adjoins an inner periphery of the planar bottommost surface. The additional blocking dielectric layer507is located inside of the first blocking dielectric layer501, and contacts at least a portion of an inner sidewall of the first blocking dielectric layer501, which is the concave portion of the inner sidewall of the first blocking dielectric layer501. The memory material layer504contacts an inner sidewall of the additional blocking dielectric layer507and a top surface of a horizontal portion of the additional blocking dielectric layer507. The semiconductor channel60is laterally surrounded by the memory material layer504and contacts a second surface of the semiconductor substrate (9,10). The additional blocking dielectric layer507contacts a third surface of the semiconductor substrate (9,10). The third surface comprises a horizontal surface that is coplanar with the first surface of the semiconductor substrate (9,10) that contacts the bottommost surface of the first blocking dielectric layer501. Further, the inner periphery of the third surface is adjoined to an upper periphery of a sidewall of the second surface of the semiconductor substrate (9,10), which is in contact with the semiconductor channel60.

Referring toFIGS. 4A-4D, sequential vertical cross-sectional views of a memory opening within the exemplary structure are shown during formation of a third exemplary memory stack structure within the memory opening according to a third embodiment of the present disclosure. The third exemplary memory stack structure ofFIG. 4Acan be derived from the first exemplary memory stack structure illustrated inFIG. 2Cby removing the spacer503selective to the first blocking dielectric layer501and the semiconductor material of the semiconductor material layer10(or the semiconductor material directly underneath the cavity49′). Optionally, an anneal may be performed prior to removal of the spacer503to crystallize the dielectric material of the first blocking dielectric layer501. For example, the first blocking dielectric layer501may be deposited in an amorphous form (for example, as amorphous aluminum oxide), and may be annealed to form a crystalline high-k dielectric metal oxide prior to removal of the spacer503. The spacer503can be removed employing an isotropic etch process that is selective to the dielectric material of the first blocking dielectric layer501.

Referring toFIG. 4B, an additional blocking dielectric layer507and a set (504,505L,601) of material layers can be subsequently formed on each physically exposed top semiconductor surface of the substrate (9,10), on each sidewalls of the first blocking dielectric layer501, and over the alternating stack (32,42) and the insulating cap layer70. In one embodiment, the set of material layers can comprise a memory material layer504, a tunneling dielectric layer505L, and an optional first semiconductor channel layer601.

The additional blocking dielectric layer507can be deposited on a sidewall of the first blocking dielectric layer501and the top semiconductor surface of the substrate (9,10). In one embodiment, the bottommost surface of the additional blocking dielectric layer507can be formed within a horizontal plane including the bottommost surface of the first blocking dielectric layer501. In one embodiment, the additional blocking dielectric layer507can be formed by conformal deposition of a dielectric material. The additional blocking dielectric layer507can have the same composition and thickness as in the second embodiment. The processing steps ofFIG. 2Dcan be performed to form the set (504,505L,601) of material layers.

Referring toFIG. 4C, the processing steps ofFIG. 2Eare performed to remove horizontal portion of the optional first semiconductor channel layer601, the tunneling dielectric layer505L, and the memory material layer504employing at least one anisotropic etch process. Further, horizontal portions of the additional blocking dielectric layer507are removed by the at least one anisotropic etch, and each portion of the semiconductor substrate (9,10) underlying a cavity49′ can be vertically recessed. Within each memory opening, a memory film50is formed, which comprises, from outside to inside, a first blocking dielectric layer501, an additional blocking dielectric layer507, a memory material layer504, and a tunneling dielectric505.

Referring toFIG. 4D, the processing steps ofFIG. 2Fcan be performed to form a semiconductor channel60, a dielectric core62, and a drain region63. The first blocking dielectric layer501contacts a first surface of the semiconductor substrate (9,10). The first surface of the semiconductor substrate (9,10) can contact an annular bottom surface of the first blocking dielectric layer501. The semiconductor channel contacts a second surface of the semiconductor substrate (9,10), which can include a substantially vertical sidewall and a horizontal semiconductor surface adjoining a bottom periphery of the vertical sidewall. The additional blocking dielectric layer507can have a homogeneous material composition throughout the entirety thereof. The additional blocking dielectric layer507contacts a third surface of the semiconductor substrate (9,10). An outer periphery of the third surface adjoins the first surface, and an inner periphery of the third surface adjoins the second surface.

The third exemplary memory stack structure comprises a first blocking dielectric layer501vertically extending at least from the bottommost layer of the stack (32,42) to a topmost layer of the stack, comprising a dielectric metal oxide having a dielectric constant greater than 7.9, and contacting a sidewall of the memory opening and a first surface of the semiconductor substrate (9,10). The first blocking dielectric layer501comprises a planar bottommost surface and a concave inner sidewall that adjoins an inner periphery of the planar bottommost surface. The additional blocking dielectric layer507is located inside of the first blocking dielectric layer501, and contacts at least a portion of an inner sidewall of the first blocking dielectric layer501, which comprises the concave portion of the inner sidewall of the first blocking dielectric layer501and a vertical portion of the inner sidewall of the first blocking dielectric layer501. The memory material layer504contacts an inner sidewall of the additional blocking dielectric layer507and a top surface of a horizontal portion of the additional blocking dielectric layer507. The semiconductor channel60is laterally surrounded by the memory material layer504and contacts a second surface of the semiconductor substrate (9,10). The additional blocking dielectric layer507contacts a third surface of the semiconductor substrate (9,10). The third surface comprises a horizontal surface that is coplanar with the first surface of the semiconductor substrate (9,10) that contacts the bottommost surface of the first blocking dielectric layer501. Further, the inner periphery of the third surface is adjoined to an upper periphery of a sidewall of the second surface of the semiconductor substrate (9,10), which is in contact with the semiconductor channel60. The additional blocking dielectric layer507can contact the entirety of an inner sidewall of the first blocking dielectric layer501.

Referring toFIGS. 5A-5F, sequential vertical cross-sectional views of a memory opening within the exemplary structure are shown during formation of a fourth exemplary memory stack structure within the memory opening according to a fourth embodiment of the present disclosure. The fourth exemplary memory stack structure ofFIG. 5Acan be formed by depositing a stack of a first blocking dielectric layer501and a semiconductor material layer513L into a memory opening49provided in the exemplary structure ofFIG. 1. The first blocking dielectric layer501can have the same composition and thickness as in the first through third embodiments. The semiconductor material layer513L comprises a semiconductor material that may be converted into a dielectric material by oxidation, nitridation, or a combination thereof. For example, the semiconductor material layer513L can include silicon, a silicon-germanium alloy, and/or a silicon-carbon alloy that can be converted into silicon oxide, silicon nitride, silicon oxynitride, an oxide of an alloy of silicon and at least one of germanium and carbon, a nitride of an alloy of silicon and at least one of germanium and carbon, or an oxynitride of an alloy of silicon and at least one of germanium and carbon. The semiconductor material layer513L can be deposited by a conformal deposition method such as chemical vapor deposition or atomic layer deposition. The thickness of the semiconductor material layer513L can be in a range from 0.6 nm to 6 nm, although lesser and greater thicknesses can also be employed.

Referring toFIG. 5B, an anisotropic etch can be performed to remove horizontal portions of the semiconductor material layer513L. The chemistry of the anisotropic etch can be selective to the material of the first blocking dielectric layer501, i.e., not remove the material of the first blocking dielectric layer501in any substantial quantity while etching the material of the semiconductor material layer513L. An opening is formed through a horizontal portion of semiconductor material layer513L at a bottom of the cavity49′ in each memory opening. Each remaining vertical portion of the semiconductor material layer513L within each memory opening constitutes a spacer513. Each spacer513can be homeomorphic to a torus. A top surface of a horizontal portion of the first blocking dielectric layer501is physically exposed at a bottom of the cavity49′ in each memory opening. Each spacer513comprises a semiconductor material, and contacts an inner sidewall of the first blocking dielectric layer501.

Referring toFIG. 5C, physically exposed horizontal portions of the first blocking dielectric layer501can be selectively etched by an isotropic etch process using the spacer513as a mask. The portion of the first blocking dielectric layer501overlying the alternating stack (32,42) can be removed during the isotropic etch process. Further, a horizontal portion of the first blocking dielectric layer501at a bottom of the cavity49′ in each memory opening can be etched through the opening in the spacer513. The spacer513is present on the vertical portion of the first blocking dielectric layer501within each memory opening during the isotropic etching of physically exposed portions of the first blocking dielectric layer501. Specifically, a horizontal portion of the first blocking dielectric layer501can be etched at a bottom of each memory opening through the opening in the spacer513. Etching of the horizontal portion of the first blocking dielectric layer501forms a peripheral undercut cavity49P by removing a peripheral portion of the first blocking dielectric layer501underneath the spacer513. The isotropic etch process can be a wet etch process or an isotropic dry etch process. The chemistry of the isotropic etch process can be selected so that the isotropic etch removes the material of the first blocking dielectric layer501selective to the material of the spacer513. The material of the first blocking dielectric layer501is etched isotropically during the isotropic etch process. A top semiconductor surface of the substrate (9,10) is physically exposed at the bottom of each memory opening.

A portion of the first blocking dielectric layer501remains within each memory opening. Each remaining first blocking dielectric layer501can be topologically homeomorphic to a torus. A concave surface is formed on the bottommost portion of the inner surface of the first blocking dielectric layer501because the material of the first blocking dielectric layer501is isotropically removed from a closed shape edge at which the inner surface of the spacer503adjoins the bottom surface of the spacer513. A top semiconductor surface of the substrate (9,10) is physically exposed at a bottom of each memory opening.

Referring toFIG. 5D, an additional blocking dielectric layer523can be formed directly on the substrate (9,10) and on the inner sidewall of the first blocking dielectric layer501by simultaneous conversion of the spacer513into a first dielectric material portion523A and a surface portion of the substrate (9,10) located directly underneath the cavity49′ into a second dielectric material portion523B. The conversion process can comprise a thermal oxidation process, a plasma oxidation process, a thermal nitridation process, a plasma nitridation process, a thermal oxynitridation process, and/or a plasma oxynitridation process. The first dielectric material portion523A comprises a dielectric compound of the semiconductor material of the spacer513and at least one element selected from oxygen and nitrogen. In one embodiment, the first dielectric material portion523A can comprise a dielectric oxide of at least one semiconductor element, a dielectric nitride of at least one semiconductor element, and/or a dielectric oxynitride of at least one semiconductor element. In one embodiment, the first dielectric material portion523A can comprise a dielectric oxide including a compound of at least one semiconductor element in the semiconductor material of the spacer513and oxygen. For example, if the spacer513is a silicon spacer (e.g., polysilicon or amorphous silicon), and the substrate10is a silicon substrate then portions523A and523B both comprise silicon oxide.

The duration of the conversion process can be selected such that the outer periphery of the first dielectric material portion523A is adjoined to an inner periphery of a bottom portion of the second dielectric material portion523B. Thus, the additional blocking dielectric layer523can be formed as an integral structure, i.e., a structure consisting of a single contiguous region. The first dielectric material portion523A and the second dielectric material portion523B can have the same material composition if the semiconductor material of the spacer513has the same composition as the semiconductor material of the semiconductor material layer10, or can have different material compositions if the semiconductor material of the spacer513has a different composition than the semiconductor material of the semiconductor material layer10.

The additional blocking dielectric layer523can be formed in, and fill, the peripheral undercut cavity49P within each memory opening. In one embodiment, a bottommost surface of the additional blocking dielectric layer523can be further recessed than the bottom surface of the first blocking dielectric layer501within a respective memory opening. A convex surface523cof the additional blocking dielectric layer523contacts a concave sidewall501asurface of the first blocking dielectric layer501. Further, another convex surface of the additional blocking dielectric layer523contacts a concave surface10dof the semiconductor substrate (9,10).

Referring toFIG. 5E, a set (504,505L,601) of material layers can be subsequently formed on the inner sidewall and the top surface of the additional blocking dielectric layer523and over the alternating stack (32,42) and the insulating cap layer70. In one embodiment, the set of material layers can comprise a memory material layer504, a tunneling dielectric layer505L, and an optional first semiconductor channel layer601. The same processing steps can be employed to form the set (504,505L,601) of material layers as in the first embodiment.

Referring toFIG. 5F, the processing steps ofFIG. 2Ecan be performed to form a memory film50, which includes the first blocking dielectric layer501, the additional blocking dielectric layer523, the memory material layer504, and the tunneling dielectric505.

Referring toFIG. 5G, a semiconductor channel60including a first semiconductor channel layer601and a second semiconductor channel layer can be formed as in the first embodiment. Further, a dielectric core62and a drain region63can be formed as in the first embodiment.

The structure ofFIG. 5Gis a fourth exemplary memory stack structure, which comprises a first blocking dielectric layer501vertically extending at least from a bottommost layer (e.g., the bottommost sacrificial material layer42) of the stack (32,42) to a topmost layer (e.g., the topmost sacrificial material layer42) of the stack, comprising a dielectric metal oxide having a dielectric constant greater than 7.9, and contacting a sidewall of the memory opening and a first surface of the semiconductor substrate (9,10). The first blocking dielectric layer501comprises a planar bottommost surface and a concave inner sidewall that adjoins an inner periphery of the planar bottommost surface. The additional blocking dielectric layer523is located inside of the first blocking dielectric layer501and contacts at least a portion of an inner sidewall of the first blocking dielectric layer501. A memory material layer504contacts an inner sidewall of the additional blocking dielectric layer523and a top surface of a horizontal portion of the additional blocking dielectric layer523. A semiconductor channel60is laterally surrounded by the memory material layer504and contacts a second surface of the semiconductor substrate (9,10).

The additional blocking dielectric layer523can have a first dielectric material portion523A having a first composition and a second dielectric material portion523B having a second composition that is the same as or different from the first composition. A bottom surface of the second dielectric material portion523B can be located below the horizontal plane including the bottom surface of the first blocking dielectric layer501, and the top surface of the second dielectric material portion523B can be located above the horizontal plane including the bottom surface of the first blocking dielectric layer501. The tip of the horizontal portion of the first blocking dielectric layer501protrudes into the sidewall of the horizontal part of the additional blocking dielectric layer523between the portions523A and523B. The additional blocking dielectric layer523can contact a third surface of the semiconductor substrate (9,10). The outer periphery of the third surface adjoins the first surface and the inner periphery of the third surface adjoins the second surface.

Referring toFIGS. 6A-6F, sequential vertical cross-sectional views of a memory opening within the exemplary structure are shown during formation of a fifth exemplary memory stack structure within the memory opening according to a fifth embodiment of the present disclosure. The fifth exemplary memory stack structure ofFIG. 6Acan be the same as the fourth exemplary memory stack structure ofFIG. 5C.

Referring toFIG. 6B, the processing steps ofFIG. 5Dcan be performed to form a disposable dielectric layer533. The disposable dielectric layer533of the fifth embodiment can be identical to the additional blocking dielectric layer523of the fourth embodiment except that the disposable dielectric layer533is formed as a disposable (e.g., sacrificial) structure, i.e., a temporary structure to be subsequently removed. Thus, the disposable dielectric layer533can be formed by simultaneously converting the spacer513into a first dielectric material portion523A and a surface portion of the substrate (9,10) located underneath the top semiconductor surface of the substrate (9,10) directly underneath a cavity49′ into a second dielectric material portion523B. The disposable dielectric layer533comprises the first dielectric material portion523A and the second dielectric material portion523B.

Referring toFIG. 6C, the disposable dielectric layer533can be removed selective to the first blocking dielectric layer501and the semiconductor material of the substrate (9,10). In one embodiment, the layer533can be removed employing an isotropic etch chemistry that is selective to the first blocking dielectric layer501and the semiconductor material of the semiconductor material layer10. An undercut region can be formed underneath the bottommost surface of the first blocking dielectric layer501.

Referring toFIG. 6D, an additional blocking dielectric layer514can be deposited by a conformal deposition method. The additional blocking dielectric layer514can be deposited on a sidewall of the first blocking dielectric layer501and a top surface of a remaining portion of the substrate (9,10) that remains after conversion of the surface portion of the substrate into a portion of the disposable dielectric layer533at the processing step ofFIG. 6B. The additional blocking dielectric layer514can include silicon oxide, silicon nitride, a silicon oxynitride, or a combination thereof. In one embodiment, the additional blocking dielectric layer514includes silicon oxide. The thickness of the additional blocking dielectric layer514can be in a range from 1 nm to 12 nm, although lesser and greater thicknesses can also be employed. The additional blocking dielectric layer514can contact a peripheral portion of the bottommost surface of the first blocking dielectric layer501. A bottommost surface of the additional blocking dielectric layer514can be formed below a horizontal plane including a bottommost surface of the first blocking dielectric layer501. The tip of the horizontal portion of the first blocking dielectric layer501protrudes into the sidewall of the horizontal part of the additional blocking dielectric layer514. In one embodiment, the additional blocking dielectric layer501can have a homogeneous material composition throughout the entirety thereof.

Subsequently, a set (504,505L,601) of material layers can be subsequently formed on the inner sidewall and the top surface of the additional blocking dielectric layer514and over the alternating stack (32,42) and the insulating cap layer70. In one embodiment, the set of material layers can comprise a memory material layer504, a tunneling dielectric layer505L, and an optional first semiconductor channel layer601. The same processing steps can be employed to form the set (504,505L,601) of material layers as in the first embodiment.

Referring toFIG. 6E, the processing steps ofFIG. 2Ecan be performed to form a memory film50, which includes the first blocking dielectric layer501, the additional blocking dielectric layer514, the memory material layer504, and the tunneling dielectric505.

Referring toFIG. 6F, a semiconductor channel60including a first semiconductor channel layer601and a second semiconductor channel layer602can be formed as in the first embodiment. Further, a dielectric core62and a drain region63can be formed as in the first embodiment.

The structure ofFIG. 6Fis a fifth exemplary memory stack structure, which comprises a first blocking dielectric layer501vertically extending at least from a bottommost layer (e.g., the bottommost sacrificial material layer42) of the stack (32,42) to a topmost layer (e.g., the topmost sacrificial material layer42) of the stack, comprising a dielectric metal oxide having a dielectric constant greater than 7.9, and contacting a sidewall of the memory opening and a first surface of the semiconductor substrate (9,10). The first blocking dielectric layer501comprises a planar bottommost surface and a concave inner sidewall that adjoins an inner periphery of the planar bottommost surface. The additional blocking dielectric layer514is located inside of the first blocking dielectric layer501and contacts at least a portion of an inner sidewall of the first blocking dielectric layer501. A memory material layer504contacts an inner sidewall of the additional blocking dielectric layer514and a top surface of a horizontal portion of the additional blocking dielectric layer514. A semiconductor channel60is laterally surrounded by the memory material layer504and contacts a second surface of the semiconductor substrate (9,10).

A bottom surface of the additional blocking dielectric layer514can be located below the horizontal plane including the bottom surface of the first blocking dielectric layer501, and the top surface of the additional blocking dielectric layer514can be located above the horizontal plane including the bottom surface of the first blocking dielectric layer501. The additional blocking dielectric layer514can contact a third surface of the semiconductor substrate (9,10). The outer periphery of the third surface adjoins the first surface and the inner periphery of the third surface adjoins the second surface.

Referring toFIGS. 7A-7D, sequential vertical cross-sectional views of a memory opening within the exemplary structure are shown during formation of a sixth exemplary memory stack structure within the memory opening according to a sixth embodiment of the present disclosure.

The sixth exemplary memory stack structure ofFIG. 7Acan be formed by depositing a stack of a first blocking dielectric layer501and a dielectric nitride layer515L into a memory opening49provided in the exemplary structure ofFIG. 1. The first blocking dielectric layer501can have the same composition and thickness as in the first through fifth embodiments. The dielectric nitride layer515L comprises a dielectric nitride such as silicon nitride. The dielectric nitride layer515L can be deposited by a conformal deposition method such as chemical vapor deposition. The thickness of the dielectric nitride layer515L can be in a range from 0.6 nm to 6 nm, although lesser and greater thicknesses can also be employed.

Referring toFIG. 7B, an anisotropic etch can be performed to remove horizontal portions of the dielectric nitride layer515L. The chemistry of the anisotropic etch can be selective to the material of the first blocking dielectric layer501, i.e., not remove the material of the first blocking dielectric layer501in any substantial quantity while etching the material of the dielectric nitride layer515L. An opening is formed through a horizontal portion of the dielectric nitride layer515L at a bottom of the cavity49′ in each memory opening. Each remaining vertical portion of the dielectric nitride layer515L within each memory opening constitutes a spacer515. Each spacer515can be homeomorphic to a torus. A top surface of a horizontal portion of the first blocking dielectric layer501is physically exposed at a bottom of the cavity49′ in each memory opening. Each spacer515comprises a dielectric nitride (which can be a nitride of a semiconductor element such as silicon nitride), and contacts an inner sidewall of the first blocking dielectric layer501.

Referring toFIG. 7C, physically exposed horizontal portions of the first blocking dielectric layer501can be etched by an isotropic etch process. The portion of the first blocking dielectric layer501overlying the alternating stack (32,42) can be removed during the isotropic etch process. Further, a horizontal portion of the first blocking dielectric layer501at a bottom of the cavity49′ in each memory opening can be etched through the opening in the spacer515. The spacer515is present on the vertical portion of the first blocking dielectric layer501within each memory opening during the isotropic etching of physically exposed portions of the first blocking dielectric layer501. Specifically, a horizontal portion of the first blocking dielectric layer501can be etched at a bottom of each memory opening through the opening in the spacer515. Etching of the horizontal portion of the first blocking dielectric layer501forms a peripheral undercut cavity49P by removing a peripheral portion of the first blocking dielectric layer501underneath the spacer515. The isotropic etch process can be a wet etch process or an isotropic dry etch process. The chemistry of the isotropic etch process can be selected so that the isotropic etch removes the material of the first blocking dielectric layer501selective to the material of the spacer515, such as a HF wet etch. The material of the first blocking dielectric layer501is etched isotropically during the isotropic etch process. A top semiconductor surface of the substrate (9,10) is physically exposed at the bottom of each memory opening.

A portion of the first blocking dielectric layer501remains within each memory opening. Each remaining first blocking dielectric layer501can be topologically homeomorphic to a torus. A concave surface is formed on the bottommost portion of the inner surface of the first blocking dielectric layer501because the material of the first blocking dielectric layer501is isotropically removed from a closed shape edge at which the inner surface of the spacer503adjoins the bottom surface of the spacer515. A top semiconductor surface of the substrate (9,10) is physically exposed at a bottom of each memory opening.

Referring toFIG. 7D, an additional blocking dielectric layer523can be formed directly on the substrate (9,10) and on the inner sidewall of the first blocking dielectric layer501by simultaneous oxidation of the spacer515into a first dielectric material portion525A and a surface portion of the substrate (9,10) located underneath the top semiconductor surface of the substrate (9,10) directly underneath the cavity49′ into a second dielectric material portion525B. The oxidation process is a conversion process that employs a thermal oxidation process and/or a plasma oxidation process. In one embodiment, the first dielectric material portion525A comprises silicon oxide or silicon oxynitride, and the second dielectric material portion525B comprises silicon oxide.

The duration of the oxidation process can be selected such that the outer periphery of the first dielectric material portion525A is adjoined to an inner periphery of a bottom portion of the second dielectric material portion525B. Thus, the additional blocking dielectric layer525can be formed as an integral structure, i.e., a structure consisting of a single contiguous region. The first dielectric material portion525A and the second dielectric material portion525B can have the same material composition if the dielectric nitride of the spacer515is silicon nitride as formed, and is completely oxidized to become silicon oxide, and if the semiconductor material of the semiconductor material layer10comprises silicon. Alternately, the first dielectric material portion525A and the second dielectric material portion525B can have can have different material compositions if the semiconductor material of the semiconductor material layer10comprises a material other than silicon or if the oxidation process converts the spacer515into a first dielectric material portion525A that includes silicon oxynitride. Thus, the first dielectric material portion525A can comprise a dielectric oxide or a dielectric oxynitride, and is formed by oxidation of the dielectric nitride.

The additional blocking dielectric layer525can be formed in, and fill, the peripheral undercut cavity49P within each memory opening. In one embodiment, a bottommost surface of the additional blocking dielectric layer525can be further recessed than the bottom surface of the first blocking dielectric layer501within a respective memory opening. A convex surface of the additional blocking dielectric layer525contacts a concave surface of the first blocking dielectric layer501. Further, another convex surface of the additional blocking dielectric layer525contacts a concave surface of the semiconductor substrate (9,10).

Referring toFIG. 7E, a set (504,505L,601) of material layers can be subsequently formed on the inner sidewall and the top surface of the additional blocking dielectric layer525and over the alternating stack (32,42) and the insulating cap layer70. In one embodiment, the set of material layers can comprise a memory material layer504, a tunneling dielectric layer505L, and an optional first semiconductor channel layer601. The same processing steps can be employed to form the set (504,505L,601) of material layers as in the first embodiment.

Referring toFIG. 7F, the processing steps ofFIG. 2Ecan be performed to form a memory film50, which includes the first blocking dielectric layer501, the additional blocking dielectric layer525, the memory material layer504, and the tunneling dielectric505.

Referring toFIG. 7G, a semiconductor channel60including a first semiconductor channel layer601and a second semiconductor channel layer can be formed as in the first embodiment. Further, a dielectric core62and a drain region63can be formed as in the first embodiment.

The structure ofFIG. 7Gis a sixth exemplary memory stack structure, which comprises a first blocking dielectric layer501vertically extending at least from a bottommost layer (e.g., the bottommost sacrificial material layer42) of the stack (32,42) to a topmost layer (e.g., the topmost sacrificial material layer42) of the stack, comprising a dielectric metal oxide having a dielectric constant greater than 7.9, and contacting a sidewall of the memory opening and a first surface of the semiconductor substrate (9,10). The first blocking dielectric layer501comprises a planar bottommost surface and a concave inner sidewall that adjoins an inner periphery of the planar bottommost surface. The additional blocking dielectric layer525is located inside of the first blocking dielectric layer501and contacts at least a portion of an inner sidewall of the first blocking dielectric layer501. A memory material layer504contacts an inner sidewall of the additional blocking dielectric layer525and a top surface of a horizontal portion of the additional blocking dielectric layer525. A semiconductor channel60is laterally surrounded by the memory material layer504and contacts a second surface of the semiconductor substrate (9,10).

The additional blocking dielectric layer525can have a first dielectric material portion525A having a first composition and a second dielectric material portion525B having a second composition, which can be the same as, or can be different from, the first composition. A bottom surface of the second dielectric material portion525B can be located below the horizontal plane including the bottom surface of the first blocking dielectric layer501, and the top surface of the second dielectric material portion525B can be located above the horizontal plane including the bottom surface of the first blocking dielectric layer501. The additional blocking dielectric layer525can contact a third surface of the semiconductor substrate (9,10). The outer periphery of the third surface adjoins the first surface and the inner periphery of the third surface adjoins the second surface. In one embodiment, the first dielectric material portion525A can comprise a dielectric oxynitride including a compound of at least one semiconductor element, oxygen, and nitrogen.

The embodiments of the present disclosure may have the following non-limiting advantages. By etching the high-k (e.g., aluminum oxide) first blocking dielectric layer501prior to forming the memory material layer504, the first blocking dielectric layer501is selectively etched inside the memory opening49without etching or attacking the memory material layer, the tunnel dielectric or first the channel layer. This improves device performance. Since there is no need to etch layer501during the anisotropic memory film50etch at the bottom of the memory opening (e.g., as shown inFIG. 2E), the etch time may be decreased, which may result in less etching damage to the first semiconductor channel layer601, which improves carrier mobility and cell current. Furthermore, the bottom memory profile after the anisotropic etch (e.g., the etch inFIG. 2E) may be more rectangular than triangular or truncated cone in shape, which increases contact area between channel60and the substrate10, thus improving cell current and lower select gate transistor resistance. Finally, since layer501, such as an aluminum oxide layer, is etched prior to deposition of the memory material layer504and other layers, layer501may have a lower crystallization state than after deposition of these overlying layers because the deposition of additional layers may cause layer501to crystallize. For example, as-deposited layer501may be amorphous or partially polycrystalline aluminum oxide layer, which is easier to etch using a wet etching process, such as HF or hot phosphoric acid wet etch, than polycrystalline aluminum oxide. Thus, layer501is preferably deposited in wholly or partially amorphous state.

Referring toFIG. 8, the exemplary structure is illustrated after formation of memory stack structures55, each of which includes a memory film50and a semiconductor channel (601,602). The memory stack structures55can be a set of first exemplary memory stack structures according to the first embodiment, a set of second exemplary memory stack structures according to the second embodiment, a set of third exemplary memory stack structures according to the third embodiment, a set of fourth exemplary memory stack structures according to the fourth embodiment, a set of fifth exemplary memory stack structures according to the fifth embodiment, or a set of sixth exemplary memory stack structures according to the sixth embodiment.

Referring toFIG. 9, at least one dielectric cap layer (71,72) can be optionally formed over the planarization dielectric layer70. In one embodiment, the at least one dielectric cap layer (71,72) can include a first dielectric cap layer71and a second dielectric cap layer72. In one embodiment, the first and second dielectric cap layers (71,72) can include dielectric materials such as silicon oxide, a dielectric metal oxide, and/or silicon nitride.

Optionally, a portion of the alternating stack (32,42) can be removed, for example, by applying and patterning a photoresist layer with an opening and by transferring the pattern of the opening through the alternating stack (32,42) employing an etch such as an anisotropic etch. An optional trench extending through the entire thickness of the alternating stack (32,42) can be formed. Subsequently, the trench can be filled with an optional dielectric material such as silicon oxide. Excess portions of the dielectric material can be removed from above the top surface of the at least one dielectric cap layer (71,72) by a planarization process such as chemical mechanical planarization and/or a recess etch. The top surfaces of the at least one dielectric cap layer (71,72) can be employed as a stopping surface during the planarization. The remaining dielectric material in the trench constitutes a dielectric material portion64.

Referring toFIGS. 10A and 10B, a stepped cavity can be formed within a contact region, which can straddle the dielectric material portion64and a portion of the alternating stack (32,42). Alternatively, the dielectric material portion64may be omitted and the stepped cavity may be formed directly in the stack (32,42). The stepped cavity can have various stepped surfaces such that the horizontal cross-sectional shape of the stepped cavity changes in steps as a function of the vertical distance from the top surface of the substrate (9,10). In one embodiment, the stepped cavity can be formed by repetitively performing a set of processing steps. The set of processing steps can include, for example, an etch process of a first type that vertically increases the depth of a cavity by one or more levels, and an etch process of a second type that laterally expands the area to be vertically etched in a subsequent etch process of the first type. As used herein, a “level” of a structure including alternating plurality is defined as the relative position of a pair of a first material layer and a second material layer within the structure.

At least one dielectric support pillar7P may be optionally formed through the retro-stepped dielectric material portion65and/or through the alternating stack (32,42). In one embodiment, the at least one dielectric support pillar7P can be formed in a contact region300, which is located adjacent to a device region100. The at least one dielectric support pillar7P can be formed, for example, by forming an opening extending through the retro-stepped dielectric material portion65and/or through the alternating stack (32,42) and at least to the top surface of the substrate (9,10), and by filling the opening with a dielectric material that is resistant to the etch chemistry to be employed to remove the sacrificial material layers42. In one embodiment, the at least one dielectric support pillar can include silicon oxide and/or a dielectric metal oxide such as aluminum oxide. In one embodiment, the portion of the dielectric material that is deposited over the at least one dielectric cap layer (71,72) concurrently with deposition of the at least one dielectric support pillar7P can be present over the at least one dielectric cap layer (71,72) as a dielectric pillar material layer73. The dielectric pillar material layer73and the at least one dielectric support pillar7P can be formed as a single contiguous structure of integral construction, i.e., without any material interface therebetween. In another embodiment, the portion of the dielectric material that is deposited over the at least one dielectric cap layer (71,72) concurrently with deposition of the at least one dielectric support pillar7P can be removed, for example, by chemical mechanical planarization or a recess etch. In this case, the dielectric pillar material layer73is not present, and the top surface of the at least one dielectric cap layer (71,72) can be physically exposed.

A photoresist layer (not shown) can be applied over the alternating stack (32,42) and/or the retro-stepped dielectric material portion65, and optionally over the and lithographically patterned to form at least one backside contact trench79in an area in which formation of a backside contact via structure is desired. The pattern in the photoresist layer can be transferred through the alternating stack (32,42) and/or the retro-stepped dielectric material portion65employing an anisotropic etch to form the at least one backside contact trench79, which extends at least to the top surface of the substrate (9,10). In one embodiment, the at least one backside contact trench79can include a source contact opening in which a source contact via structure can be subsequently formed. If desired, a source region (not shown) may be formed by implantation of dopant atoms into a portion of the semiconductor material layer10through the backside contact trench79.

An etchant that selectively etches the second material of the sacrificial material layers42with respect to the first material of the insulator layers32can be introduced into the at least one backside contact trench79, for example, employing an etch process. Backside recesses43are formed in volumes from which the sacrificial material layers42are removed. The removal of the second material of the sacrificial material layers42can be selective to the first material of the insulator layers32, the material of the at least one dielectric support pillar7P, the material of the retro-stepped dielectric material portion65, the semiconductor material of the semiconductor material layer10, and the material of the outermost layer of the memory films50. In one embodiment, the sacrificial material layers42can include silicon nitride, and the materials of the insulator layers32, the at least one dielectric support pillar7P, and the retro-stepped dielectric material portion65can be selected from silicon oxide and dielectric metal oxides. In another embodiment, the sacrificial material layers42can include a semiconductor material such as polysilicon, and the materials of the insulator layers32, the at least one dielectric support pillar7P, and the retro-stepped dielectric material portion65can be selected from silicon oxide, silicon nitride, and dielectric metal oxides. In this case, the depth of the at least one backside contact trench79can be modified so that the bottommost surface of the at least one backside contact trench79is located within the dielectric pad layer12, i.e., to avoid physical exposure of the top surface of the semiconductor substrate layer10.

Each of the plurality of backside recesses43can extend substantially parallel to the top surface of the substrate (9,10). A backside recess43can be vertically bounded by a top surface of an underlying insulator layer32and a bottom surface of an overlying insulator layer32. In one embodiment, each backside recess43can have a uniform height throughout.

Referring toFIG. 11, a conductive material can be deposited in the plurality of backside recesses43, on sidewalls of the at least one the backside contact trench79, and over the top surface of the dielectric pillar material layer73(or the topmost layer of the exemplary structure in case the dielectric pillar material layer73is not employed). As used herein, a conductive material refers to an electrically conductive material. The conductive material can be deposited by a conformal deposition method, which can be, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), electroless plating, electroplating, or a combination thereof. The conductive material can be an elemental metal, an intermetallic alloy of at least two elemental metals, a conductive nitride of at least one elemental metal, a conductive metal oxide, a conductive doped semiconductor material, a conductive metal-semiconductor alloy such as a metal silicide, alloys thereof, and combinations or stacks thereof. Non-limiting exemplary conductive materials that can be deposited in the plurality of backside recesses43include tungsten, tungsten nitride, titanium, titanium nitride, tantalum, and tantalum nitride. In one embodiment, the conductive material can comprise a metal such as tungsten and/or metal nitride. In one embodiment, the conductive material for filling the plurality of backside recesses43can be selected from tungsten and a combination of titanium nitride and tungsten. In one embodiment, the conductive material can be deposited by chemical vapor deposition.

A plurality of electrically conductive layers46is present in the plurality of backside recesses43, and a contiguous conductive material layer46L can be formed on the sidewalls of each backside contact trench79and over the dielectric pillar material layer73(or the topmost layer of the exemplary structure in case the dielectric pillar material layer73is not employed). Thus, at least a portion of each sacrificial material layer42can be replaced with an electrically conductive layer46, which is a conductive material portion.

Referring toFIGS. 12A and 12B, the deposited conductive material is etched back from the sidewalls of each backside contact trench79and from above the dielectric pillar material layer73(or the topmost layer of the exemplary structure in case the dielectric pillar material layer73is not employed), for example, by an isotropic etch. Each remaining portion of the deposited conductive material in the backside recesses43constitutes an electrically conductive layer46. Each electrically conductive layer46can be a conductive line structure.

Each electrically conductive layer46can function as a combination of a plurality of control gate electrodes and a word line electrically connecting, i.e., electrically shorting, the plurality of control gate electrodes. The plurality of control gate electrodes within each electrically conductive layer46can include control gate electrodes located at the same level for the vertical memory devices including the memory stack structures55. In other words, each electrically conductive layer46can be a word line that functions as a common control gate electrode for the plurality of vertical memory devices.

An insulating spacer74can be formed on the sidewalls of the backside contact trench79by deposition of a contiguous dielectric material layer and an anisotropic etch of its horizontal portions. The insulating spacer74includes a dielectric material, which can comprise, for example, silicon oxide, silicon nitride, a dielectric metal oxide, a dielectric metal oxynitride, or a combination thereof. The thickness of the insulating spacer74, as measured at a bottom portion thereof, can be in a range from 1 nm to 50 nm, although lesser and greater thicknesses can also be employed. In one embodiment, the thickness of the insulating spacer74can be in a range from 3 nm to 10 nm.

A photoresist layer (not shown) can be applied over the topmost layer of the exemplary structure (which can be, for example, the dielectric pillar material layer73) and in the cavity laterally surrounded by the insulating spacer74, and is lithographically patterned to form various openings in a peripheral device region. The locations and the shapes of the various openings are selected to correspond to electrical nodes of the semiconductor devices to be electrically contacted by contact via structures. An anisotropic etch is performed to etch through the various layers overlying the electrical nodes of the semiconductor devices. For example, at least one gate via cavity can be formed such that the bottom surface of each gate via cavity is a surface of a gate electrode (152,154), and at least one active region via cavity can be formed such that the bottom surface of each active region via cavity is a surface of an active region130. In one embodiment, different types of via cavities can be formed separately employing multiple combinations of photoresist layers and anisotropic etch processes. The vertical extent of each gate via cavity, as measured from the top surface of the dielectric pillar material layer73to the bottom surface of the gate via cavity, can be less than the vertical distance between the top surface of the dielectric pillar material layer73and the topmost surface of the alternating plurality (32,46) of the insulator layers32and the electrically conductive layers46. The photoresist layer can be subsequently removed, for example, by ashing.

Another photoresist layer (not shown) can be applied over the exemplary structure, and can be lithographically patterned to form openings within a contact region in which formation of contact via structures for the electrically conductive layers46is desired. Via cavities can be formed through the retro-stepped dielectric material portion65by transfer of the pattern of the opening by an anisotropic etch. Each via cavity can vertically extend to a top surface of a respective electrically conductive layer46.

The cavity laterally surrounded by the insulating spacer74and the various via cavities in the peripheral device region are filled with a conductive material to form various contact via structures. For example, a backside contact via structure76can be formed in the cavity surrounded by the insulating spacer74, a gate contact via structure8G is formed in each gate via cavity, and an active region via structure8A is formed in each active region via cavity. Further, control gate contact via structures8C can be formed within each contact via cavity that extends to a top surface of the electrically conductive layers46. Similarly, drain contact via structures88can be formed to provide electrical contact to the drain regions63.

Subsequently, a line-level dielectric layer90can be formed over the dielectric pillar material layer73, and various conductive line structures92can be formed in the line-level dielectric layer90to provide electrical contact to the various contact via structures (76,8G,8A,88,8C). A subset of the electrically conductive layers46can function as control gate electrodes for the memory stack structures55in the device region. Optionally, at least one subset of the electrically conductive layers46can be employed as at least one drain select gate electrode and/or at least one source select gate electrode.

The exemplary structure is a multilevel structure including a stack (32,46) of an alternating plurality of electrically conductive layers46and insulator layers32located over a semiconductor substrate including the semiconductor material layer10. An array of memory stack structures55can be located within memory openings through the stack (32,46).

In one embodiment, the device located on the semiconductor substrate can include a vertical NAND device located in the device region100, and at least one of the electrically conductive layers46in the stack (32,46) can comprise, or can be electrically connected to, a word line of the NAND device. The device region100can include a plurality of semiconductor channels (601,602). At least one end portion of each of the plurality of semiconductor channels (601,602) extends substantially perpendicular to a top surface of the semiconductor substrate. The device region100further includes a plurality of charge storage regions located within each memory layer50. Each charge storage region is located adjacent to a respective one of the plurality of semiconductor channels (601,602). The device region100further includes a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate (9,10). The plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level. The plurality of electrically conductive layers46in the stack (32,46) can be in electrical contact with, or can comprise, the plurality of control gate electrodes, and extends from the device region100to a contact region300including a plurality of electrically conductive contact via structures.

In case the exemplary structure includes a three-dimensional NAND device, a stack (32,46) of an alternating plurality of word lines46and insulator layers32can be located over a semiconductor substrate. Each of the word lines46and insulator layers32is located at different levels that are vertically spaced from a top surface of the semiconductor substrate by different distances. An array of memory stack structures55is embedded within the stack (32,46). Each memory stack structure55comprises a semiconductor channel (601,602) and at least one charge storage region located adjacent to the semiconductor channel (601,602). At least one end portion of the semiconductor channel (601,602) extends substantially perpendicular to the top surface of the semiconductor substrate through the stack (32,46).

In a non-limiting illustrative example, the insulator layers32can comprise silicon oxide layers, the plurality of word lines46can comprise tungsten or a combination of titanium nitride and tungsten, the at least one charge storage region can comprises a tunneling dielectric, a blocking dielectric layer, and either a plurality of floating gates or a charge trapping layer located between the tunneling dielectric layer and the blocking dielectric layer. An end portion of each of the plurality of word lines46in a device region can comprise a control gate electrode located adjacent to the at least one charge storage region. A plurality of contact via structures contacting the word lines46can be located in a contact region300. The plurality of word lines46extends from the device region100to the contact region300. The backside contact via structure76can be a source line that extends through a dielectric insulated trench, i.e., the backside contact trench79filled with the dielectric spacer74and the backside contact via structure76, in the stack to electrically contact the source region (not shown). The source region can be in contact with the horizontal portion of the semiconductor channel in an upper portion of the semiconductor material layer10. A drain line, as embodied as a conductive line structure92that contacts a drain contact via structure88, electrically contacts an upper portion of the semiconductor channel (601,602). As used herein, a first element “electrically contacts” a second element if the first element is electrically shorted to the second element. An array of drain regions63contacts a respective semiconductor channel (601,602) within the array of memory stack structures55. A top surface of the dielectric material layer, i.e., the insulating cap layer70, can be coplanar with top surfaces of the drain regions63.