Semiconductor device package and method of the same

The invention proposes a semiconductor device package structure, comprising a substrate, an adhesive layer and a die. The substrate has electrical through-holes to inter-connect a first and second wiring circuit on a top surface and a bottom surface of the substrate respectively, wherein a contact conductive bump is formed on the first wiring circuit. The under-fill adhesive layer is formed on the top surface and the first wiring circuit of the substrate except the area of the die. The die has a bump structure on the bonding pads of the die, wherein the bump structure of the die is electrically connected to the contact conductive bump of the first wiring circuit of the substrate.

TECHNICAL FIELD

The invention relates to a semiconductor device package, and more particularly to a semiconductor device package with dual substrates having die embedded therein.

BACKGROUND

In the field of semiconductor devices, the device density is increased and the device dimension is reduced, continuously. The demand for the packaging or interconnecting techniques in such high density devices is also increased to fit the situation mentioned above. Conventionally, in the flip-chip attachment method, an array of solder bumps is formed on the surface of the die after the re-distribution layer be formed. The formation of the solder bumps may be carried out by using a solder composite material through a solder mask for producing a desired pattern of solder bumps. The function of chip package includes power distribution, signal distribution, heat dissipation, protection and support, and so on. As a semiconductor become more complicated, the traditional package technique, for example lead frame package, flex package, rigid package technique, can't meet the demand of producing smaller chip with high density elements on the chip. The trend of package technique is toward ball grid array (BGA), flip chip ball grid array (FC-BGA), chip scale package (CSP), wafer level package (WLP) today.

Image sensors have become widely used in digital still cameras, cellular phones, automobile, and other applications. The technology used to manufacture image sensors, and in particular CMOS image sensors, has continued to advance at great pace. For example, the demands of higher resolution and lower power consumption have encouraged the further miniaturization and integration of the image sensor. In a large number of image sensors, a photodiode structure called a pinned or a buried photodiode is used because of its low noise performance. In this photodiode structure, a P+ layer is implanted at or below the surface of the photodiode adjacent to a transfer gate. An N− layer is implanted deeper into the silicon substrate. This is the buried layer that stores charge away from the surface region, and thus, away from defects at the surface of the silicon substrate. The purpose of the P+ layer is to provide a photodiode with increased storage capacitance and to passivate the defects on the photodiode surface.

Various structures using flip-chip mounting of an image sensor chip have been developed in an attempt to simplify the construction of image sensor packages. U.S. Pat. No. 6,144,507 discloses an image sensor chip mounted directly to a printed circuit board (PCB). An image sensor chip is mounted in flip-chip fashion over an aperture within the PCB, and a transparent cover is either attached directly to the active surface of the chip or bonded to the side of the PCB opposite that to which the image sensor chip is attached and over the aperture. Although these methods eliminate the difficulties associated with wire bonding, however, the PCB's is very large with respect to the size of the image sensor chip and the transparent cover.

U.S. Pat. No. 5,786,589 disclosed the features of bonding a TAB sheet to a glass substrate and bonding an image sensor chip to the TAB tape with a conductive film. This design requires a specialized substrate attachment technique due to the TAB-type connection leads. Moreover, the conductive film risks interference with sensing circuitry on the image sensor chip and requires the formation of dummy leads or dam structures to compensate for this problem.

U.S. Pat. No. 6,885,107 disclosed conventional type image sensor package. It employed a BGA package which includes a plurality of ball under the substrate and the die is exposed outside of the substrate. In accordance with the present invention, image sensor packaging having the above-described and other beneficial characteristics and methods for fabrication thereof are provided. An image sensor chip is flip-chip mounted to conductive traces on a first surface of a transparent substrate. The active surface of the image sensor chip is protected from contamination after mounting by depositing a bead of sealant around the periphery of the image sensor chip between the active surface of the image sensor chip and the first surface of the substrate, thus eliminating any need for additional damming structures or spacing frames as used in the prior art. Discrete conductive elements such solder balls or columns are attached to ends of the conductive traces which form an array pattern, the discrete conductive elements extending transversely from the conductive traces on the first surface to a substantially common plane at a level beyond a back surface of the image sensor chip. The resulting structure comprises a board-over-chip (BOC) package arrangement. Thus, the thickness of the substrate is unlikely to be scaled down due to the structure has ball high and extruding die receiving structure which limits the scale of the package shrinkage.

The prior arts suffer complicated processes to form the image package and the package structure is unable to be scaled down. Further, these prior arts only disclosed single chip package, no multiple chip structure is illustrated. Therefore, based-on the shortcomings of there prior arts, the present invention provide a semiconductor device package manufactured by simpler processes, with better reliability.

SUMMARY OF THE INVENTION

An objective of the invention is to provide a semiconductor device package structure.

Another objective of the invention is to provide a single or multiple chips package with dual substrate having pre-formed through holes and die receiving opening.

Yet another object of the invention is to provide semiconductor chips package with dual substrate having die opening window to improve the reliability and shrinking the device size.

The further object of the invention is to provide an image sensor package with dual substrates which have lower and upper wiring patterns by copper clad laminated (CCL) and E-plating Cu/Au or Cu/Ni/Au metal for increasing electrical conductivity.

According to an aspect of the invention, it proposes a semiconductor device package structure, comprising a substrate, an adhesive layer and a die. The substrate has electrical through-holes to inter-connect a first wiring circuit on a top surface of the substrate and a second wiring circuit on a bottom surface of the substrate, wherein a contact conductive bump is formed on the first wiring circuit except the electrical through-holes area. The adhesive layer is formed on the top surface and the first wiring circuit of the substrate. The die has a bump structure on the bonding pads of the die (no re-distribution layer needed), wherein the bump structure of the die is electrically connected to the contact conductive bump of the first wiring circuit of the substrate. Especially, the adhesive layer is formed only under the die for adhering the die and the substrate.

In an aspect, a second contact conductive bump is formed on the second wiring circuit of the substrate.

In another aspect, the package structure further comprises a cover layer on said top surface of the substrate and a bottom surface of the die.

In yet another aspect, the package structure further comprises a second substrate with a die receiving opening and a third wiring circuit on a top surface of the second substrate and a fourth wiring circuit on a bottom surface of the second substrate, wherein a second contact conductive bump is formed on the third wiring circuit of the second substrate except the electrical through-holes area; and a re-distribution layer structure on the top surface of the second substrate to electrically connect to the fourth wiring circuit of the second substrate.

In one aspect, the package structure further comprises a dielectric layer on the die and the second substrate with an opening for via formed therein; a cover layer on the dielectric layer and the re-distribution layer.

In another aspect, the package structure further comprises a passive component and an active component electrically connected to the re-distribution layer.

In yet another aspect, the package structure further comprises a third substrate with a second die receiving opening and a fifth wiring circuit on a top surface of the third substrate and a sixth wiring circuit on a bottom surface of the third substrate, wherein a second contact conductive bump is formed on the sixth wiring circuit except the electrical through-holes area; a second die with a second bump structure on bonding pads of the second die, wherein the second bump structure of the second die is electrically connected to the second contact conductive bump of the sixth wiring circuit of the third substrate. A cover layer may be formed on/to cover the second die and the third substrate.

According to an aspect of the invention, it proposes a semiconductor device package structure, comprising a first and second substrate, a first and second adhesive layer and a die. The first substrate has a die receiving opening and a first wiring circuit on a top surface of the substrate and a second wiring circuit on a bottom surface of the substrate, wherein a contact conductive bump is formed on the second wiring circuit. The die has a bump structure on the bonding pads of the die. The first adhesive layer is formed on the bottom surface of the first substrate and the die, and filled into the gap between the die and the first substrate for adhering the die and the first substrate. The second substrate has a die opening window and a third wiring circuit on a top surface of the second substrate and a fourth wiring circuit on a bottom surface of the second substrate, wherein a contact conductive bump is formed on the fourth wiring circuit. The bump structure of the die is electrically connected to the contact conductive bump of the fourth wiring circuit of the second substrate. The second adhesive layer is formed under the second substrate except the die opening window for adhering the die and the second substrate.

In one aspect, the size of the die opening window of the second substrate is smaller than that of the die receiving opening of the first substrate. The die is a MEMS sensor device, for example image sensor chip, a navigate sensor chip, a pressure sensor chip, a CDR sensor (fluidic sensor) chip, a voice sensor chip, or a biochip sensor.

According to an aspect of the invention, it proposes a method for forming a semiconductor device package, comprising: preparing a first substrate and a second substrate, wherein the first substrate includes a wiring circuit and an aligning mark disposed on a top surface thereof and a contact conductive bump is formed on the wiring circuit; opening a die opening window through the second substrate by using a laser or punching method; preparing an adhesive material; attaching the second substrate to the first substrate by the adhesive material such that the adhesive material is disposed between a top surface of the first substrate and a bottom surface of the second substrate to directly attach the second substrate onto the first substrate excluding the contact conductive bump area; aligning a die with a bump structure on the bonding pads of the die by using the aligning mark and attaching the die onto said contact conductive bump with force by said adhesive material such that the bump structure of the die is electrically connected to the contact conductive bump of the wiring circuit of the first substrate; forming a dielectric layer on a top surface of the second substrate and the die and pushing the dielectric layer into a gap between a side wall of the die and a side wall of the die opening window; opening a plurality of via openings in the dielectric layer; and forming a redistribution layer in the plurality of via openings and on the dielectric layer.

DETAILED DESCRIPTION

FIG. 1illustrates a cross-sectional view of a semiconductor device package structure according to the first embodiment of the invention. As shown inFIG. 1, the semiconductor device package includes a substrate100, an adhesive layer106and a die110. The substrate100includes a wiring pattern101formed on a top surface of the substrate100and a wiring pattern102formed on a bottom surface of the first substrate100. A connecting conductive through holes103may be formed for penetrating through the substrate100connected to the wiring pattern101,102for electrical connection. The conductive through holes103may be made of copper and formed by an electro-plating process. Contact conductive bump104,107is formed on the wiring circuit101, and contact conductive bump105is formed on the wiring circuit102, respectively, excluding area of the electrical through-holes103. The die110has conductive (such as Al or Au) bonding pads111(I/O pads) formed thereon. The die110has a conductive bump112formed on the bonding pads111, and the die110faces down to make the conductive bump112electrically connect to the contact the conductive bump107(to wiring circuit101) of the substrate100. The die110is disposed on the substrate100. The thickness of the die110is around 50˜250 um (microns). Materials of the contact conductive bump104,107,112include solder bump, solder ball or gold bump or stud bump. The adhesive layer106is formed on the top surface of the substrate100and the wiring circuit101of the substrate100, wherein the adhesive layer106is formed between the die110and the substrate100to adhere a top surface (active area surface; in another application, it also can be the non-active area surface by using the TSV technology to extend the bump structure on the backside of die) of the die110and the top surface of the substrate100. Moreover, no adhesive layer is formed on area of the top surface of the substrate100outside area of die size (except the area of the die). The adhesive layer106is formed only under the die110for adhering the die110and the substrate100. Thus, the adhesive layer106is “under-fill” adhesive layer (under the die110). The adhesive layer106is formed on the substrate100by a dry film at high vacuum, pressure condition. The size of the “under-fill” adhesive layer may be controlled. Then, a photo-lithography process is performed to open the “bump” area on the substrate100for exposing the adhesive layer106. The adhesive layer106is cured at temperature 150° C. under pressure, final curing at 180° C., with elastic properties. Next, solder bump is re-flowing for soldering join the “bump” between die and substrate. In this embodiment, no RDL is needed in bare chip package structure.

The conductive through holes103may be filled with conductive material, such as metal, alloy. In one example, they are formed with copper by Electro-plating technology. Preferably, material of the substrate100is organic substrate likes epoxy type FR5, BT, PCB. Preferably, the organic substrate with high glass transition temperature (Tg) are epoxy type FR5 or BT (Bismaleitnide triazine) type substrate, the above materials can be easy to form the circuit pattern and inter-connecting through holes. The Cu metal (CTE around 16) can be used also. The glass, ceramic, silicon can be used as the substrate. The adhesion material106is preferably to form of polymer with silicone rubber based elastic materials. It is because that the CTE (X/Y direction) of the epoxy type organic substrate (FR5/BT) is around 14-17 and the CTE in Z direction is about 30-60, it can reduce the die shift issue and thermal stress during the temperature curing of the adhesion material. In one embodiment of the invention, the material of the wiring layers101,102include Cu, Cu/Ni/Au alloy or Cu/Au alloy; the thickness of the wiring layers is from 5 urn to 25 um (it also can be thicker than 25 um if necessary). The CCL (copper clad laminated) is formed by lamination also as seed metal layers, and the Cu/Au or Cu/Ni/Au alloy is formed by electroplating; exploiting the electro-plating process to form the wiring layers with enough thickness and better mechanical properties to withstand CTE mismatching during temperature cycling and mechanical bending. The conductive pads can be Au or Cu/Au or Al or combination thereof. All of the conductive through holes may be formed by CNC or laser drilling.

In one embodiment, the semiconductor device package structure further comprises a cover layer120is formed on the top surface of the substrate100and the bottom surface of the die110to cover the die110and the substrate100, shown inFIG. 2, In another embodiment, the contact conductive bump105may be replaced by solder balls121, shown inFIG. 3. The cover layer120is formed by a bonding process. The cover layer120is a dry film with high/low filler layer for easy to form the sharp structure and protect the die.

In one embodiment, based-on theFIG. 2, the semiconductor device package structure further comprises a second substrate130disposed between the cover layer120and the substrate100, shown inFIG. 4. The second substrate130includes a wiring pattern131formed on a top surface of the second substrate130and a wiring pattern132formed on a bottom surface of the second substrate130. In one embodiment, the wiring pattern101,102may be pre-formed on the first substrate100. In one embodiment, the wiring pattern131,132may be pre-formed on the second substrate130. The second substrate130has a die receiving opening for receiving a die/chip110. The die110is disposed within the die receiving opening of the second substrate130. The thickness of the die110is from around 50 um to 250 um. The second substrate130is formed on the first substrate100via an adhesive layer140. The thickness of the first substrate100and the second substrate130is from 50 um to 100 um (it also can be thicker than 100 um or thinner than 50 um if necessary). The adhesive layer140(can be the same materials of adhesive layer106) is formed on the top surface of the substrate100and the wiring circuit101of the substrate100, wherein the adhesive layer140is formed between the die110/the second substrate130and the substrate100to adhere a top surface (active area surface) of the die110/the second substrate130and the top surface of the subs Irate100. The thickness of the adhesive layer140is from 30 um to 100 um. As the same, a photo-lithography process is performed to open the “bump” area on the first substrate100for exposing the adhesive layer140. The wiring pattern132is connected to the wiring pattern101(through conductive bump104). In this embodiment, the cover layer120is formed on the top surface of the second substrate130and the bottom surface of the die110to cover the die110and the second substrate130, shown inFIG. 4. In one embodiment, material of the cover layer120may be filled the gap between the die110and the second substrate130. Weight of the gap is smaller than 200 um (it also can be greater than 200 um if necessary).

In one embodiment, based-on theFIG. 4, the semiconductor device package structure further comprises a dielectric layer150, a redistributed metal layer (RDL)151and via152, shown inFIG. 5. The dielectric layer150is formed on the top surface of the second substrate130and the bottom surface of the die110to cover the die110and the second substrate130. A photo-lithography process is performed to open the “via” area on the second substrate130for exposing the contact pads of second substrate130. In one embodiment, the RDL151and via152may be formed in the continuous process. The dielectric layer150is formed on the die110and the second substrate130with openings for via152formed therein, it prefers as thin as possible for the dielectric layer150for better reliability concerning. The redistributed metal layer (RDL)151is formed on via152and the dielectric layer150for coupling to via152. The dielectric layer150fills into the gap between the die110and the second substrate130in this application. The cover layer120covers the dielectric layer150and the RDL151.

The detailed structure of layer-by-layer indicated by number122may be referred toFIG. 6. It is shown that the inter-connecting between the first substrate100and the second substrate130is through the conductive bump104and133respectively.

In one embodiment, based-on theFIG. 5, the stacked semiconductor device package structure may be achieved by performing a duplicating manufacturing process, shown inFIG. 7. In the stacked chips package structure, it includes multiple chips package (MCP), MCP1and MCP2, wherein MCP2may include dice/chip210placed on the second substrate200, and MCP1may include dice/chip110placed on the first substrate100. The cover layer120is the top layer of the package structure.

FIG. 8illustrates a cross-sectional view of a first substrate, a second substrate and a die before connection according to one embodiment of the invention. The processes of forming the image package of the present invention includes preparing a first substrate100and a second substrate130(preferably organic substrate FR4/FR5/BT raw material) and the first substrate100has wiring circuit101,102formed on a top surface and a bottom surface of the first substrate100, respectively. The wiring pattern131,132are formed on a top surface and a bottom surface of the second substrate130, respectively. The layers101,102,131and132of the substrates may be formed by E-plating with Cu/Ni/Au. The connecting conductive through holes103may be formed by passing through the first substrate100, in the same concept, the connecting through holes (not shown in drawing) may be formed by passing through the second substrate130. The second substrate130has a pre-formed die receiving opening with the size larger than die size plus around 100 um-200 um per side by laser cutting or mechanical punching (multiple dice puncher). The second substrate130is attached (adhesion film) on the first substrate100via the adhesive layer140, and inter-connecting through the bump structure.

The next step is to set the die110into the die receiving opening of the second substrate130by picking, aligning and placing the die110into the die open area of the second substrate130and on the adhesive layer140, by die/substrate placement and alignment tool. The alignment mark101ais for the die110aligning. For aligning, conductive bump112on the die110aligns to conductive bump107under the die110, and conductive bump133on the second substrate133aligns to conductive hump104under the second substrate130. The next step is panel bonding process to press the die/the second substrate under the vacuum, pressure and temperature conditions to be bonded to the first substrate. Subsequently, the dielectric layer150is formed on the top surface of the second substrate130and the bottom surface of the die110and fill into the gap between the die130and the second substrate130, and then opening the “via” area on the second substrate130. The redistributed metal layer (RDL)151is formed on via152and the dielectric layer150for coupling to via152. Finally, the cover layer120is formed to cover the dielectric layer150and the RDL151.

According to the above mentioned package structure, a method for forming a semiconductor device package could be comprising the following steps: preparing the carrier tools (glass tool) with an alignment mark; setting the bottom substrate with wiring circuits on both site, and an adhesive layer on the top surface of the bottom substrate, then aligning the bottom substrate on the carrier tools with alignment mark matching; followed-by setting the top substrate with wiring circuit on both site, and die open area, then aligning and placing the top substrate on the adhesive layer of the bottom substrate; aligning and placing (flip chip) a die with metallization bump structure into the die open area and attached on the adhesive layer of the bottom substrate; a panel bonding machine with one process step to bond the bottom substrate with adhesive layer, the top substrate and die together with carrier tools together under high vacuum, high temperature and pressure on panel conditions to adhere the top, bottom substrate and die together and re-flowing (increase the temperature to eutectic-point) the metallization bump for electrical inter-connecting between the bottom substrate, the top substrate and the die. The bonding process conditions are described as follows:

Putting the “panel” (substrates and chips) and tools (glass carriers) into the chamber—on the bottom stage—“with hot plate function” of the panel bonder machine;

Turning on the vacuum till at least 10−2torr;

Setting the up stage pressure on “panel+tools” at least 100 kg; (it will depends on the panel size)

Fixing the up stage at a pre-determined position;

Increasing the temperature to 120˜180° C. for few minutes; (to adhere the substrates and chips by the adhesive layer)

Increasing the temperature to 250˜300° C. for about 1 (or few) minute “re-flow at eutectic point”, then decreasing the temperature to 50˜80° C. for few minutes by cooling water as profile;

Releasing the vacuum and purge N2air at the same time;

Releasing the up stage from “panel+tools”;

Opening the chamber and removing the “Panel and Tools”, then

Separating the tools to complete the panel bonding process.

The method further comprises bonding a cover layer film on the top surface of the top substrate and the bottom of the die under the vacuum, high temperature and pressure condition. The method further comprises forming solder bump, solder ball or gold bump on the bottom surface of wiring circuit of the bottom substrate. The method further comprises forming a metal re-distribution layer on top surface of the top substrate. The method further comprises surface mounting the passive and/or active components on the metal re-distribution layer (RDL).

In one embodiment, based-on the aforementionedFIG. 5, after the RDL151is formed, an active device (IC)170and/or a passive component160is also attached (SMT) on the die110and the second substrate130, wherein contact conductive bump161is electrically connected to the RDL151, thermal pad151aand the passive component160, and contact conductive bump171is electrically connected to the RDL151, thermal pad151aand active device170, shown inFIG. 9. The passive component160could be such as a capacitor or a resistor. A further die formed by WL-CSP, CSP, BGA, Flip Chips, can also be mounted on RIX,151of the second substrate130.

In one embodiment, based-on the aforementionedFIG. 5, after the RDL151is formed, a third substrate500and a die210are placed on the die110and the second substrate130, wherein contact conductive bump212on the die210is electrically connected to contact conductive bump134(or via152) on the second substrate130, and the third substrate500has wiring circuit501,502formed on a top surface and a bottom surface of the third substrate500, respectively, shown inFIG. 10. The cover layer120is formed on the die210and the third substrate500to cover the die210and the third substrate500and fill into the gap between the die210and the third substrate500.

The package structure for MEMS sensor device includes a first substrate300, a sensor die/chip310, an adhesive layer304, another adhesive layer323and a second substrate320, shown inFIG. 11. The first substrate300includes a wiring pattern301on a top surface of the first substrate300and a wiring pattern302on a bottom surface of the first substrate300. A contact conductive bump303may be formed on the wiring pattern302of the first substrate300. The first substrate300has a die receiving opening for receiving the sensor die/chip310which has a sensing array311formed thereon. The sensor die310has conductive (such as Al or Au) pads312(I/O pads) formed thereon. The sensor die310is disposed within the die receiving opening of the first substrate300. In one embodiment, the sensor chip310is an image sensor chip, a navigate sensor chip, a pressure sensor chip, a CDR sensor (fluidic sensor) chip, a voice sensor chip, or a bio-chip sensor. The second substrate320is formed on the first substrate300, with die opening window for exposing the sensing array311, a wiring pattern321formed on a top surface of the second substrate320and a wiring pattern322formed on a bottom surface of the second substrate320. Contact conductive bump324is formed on the wiring circuit322for coupling to the conductive bump313of die310. The size of die opening window of the second substrate320is smaller than that of the die receiving opening of the first substrate300. The adhesive layer304is formed on the bottom surface of the first substrate300and the wiring circuit302of the first substrate300, and filled into the gap wherein the sensor chip310and the first substrate300to adhere the sensor chip310and the first substrate300. The adhesive layer323is formed/filled under the second substrate320, except the die opening window. Thus, no adhesive layer is formed on the area of the contact conductive bump312,324and the die opening window. Thus, the adhesive layer323is “under-fill” adhesive layer (under the second substrate320). A photo-lithography process and a developing process are performed to open the “bump” area on the first substrate300for exposing the contact conductive bump303.

In one embodiment, a material of the first, second, third or more substrate includes BT, FR4, FR5, PT, ceramic, glass, silicon or metal.

The advantages of the invention includes (i) using solder/stud bump structure for inter-connecting between substrate and die with better reliability due to CTE mismatching issue between die and substrate; (ii) using adhesive layer as under-fill function to protect the die and improve the reliability; (iii) simple process and better yield for built the bump structure except the electrical through-holes area instead of re-filling material into through-hole for inter-connecting between substrates and die/chips; (iv) using the simple panel bonding method, it can avoid the die/chip tilt in Z-direction that may cause the performance issue of sensor chip. It also shows the chip last process to avoid the chip damage issue.

The System in Package structure and panel process are simple than conventional image package which fails to disclose the multi-chip and dual substrates structure. The thickness of the device package is easy to be controlled and die shift issue will be eliminated during process. The substrate is pre-prepared with pre-formed die opening window, inter-connecting through holes; the size of die receiving opening window is equal to die size plus around >100 um-200 um per side; it can be used as stress buffer releasing area by filling the adhesive elastic core paste materials to absorb the thermal stress due to the CTE between silicon die and substrate (FR5/BT) is difference, additionally, it can fill the elastic dielectric materials to the gap between die edge and side wall of the substrate to absorb the mechanical bending and/or thermal stress due to the CTE mismatch. The packaging throughput will be increased (manufacturing cycle time was reduced) due to apply the simple build up layers on top the surface and bottom site of the substrates at the same time. The die and substrates (both second and first substrates) be bonded together (both mechanical adhesion and electrical inter-connecting) by using panel bonding process. The reliability for both package and board level is better than ever, especially, for the board level temperature cycling test, it was due to the CTE of substrate and PCB mother board are identical, hence, no thermal mechanical stress be applied on the solder humps/balls; for the board level mechanical bending test, it was due to bottom side of substrate to support the mechanical strength allowing absorb the stress generated at top side die area and boundary area.

The foregoing descriptions are preferred embodiments of the present invention. As is understood by a person skilled in the art, the aforementioned preferred embodiments of the present invention are illustrative of the present invention rather than limiting the present invention. The present invention is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims, the scope of which should be accorded the broadest interpretation so as to encompass all such modifications and similar structures.