Display substrate, manufacturing method thereof and display device

A display substrate, a manufacturing method thereof and a display device are provided. The display substrate includes a base substrate, a pixel defining layer and at least one photo spacer. The pixel defining layer is disposed on the base substrate and includes a plurality of openings, the at least one photo spacer is disposed on a side of the pixel defining layer away from the base substrate. A distance from any point at a bottom of the at least one photo spacer contacting the pixel defining layer to an upper edge of a side wall of the plurality of openings is greater than or equal to 5 μm.

TECHNICAL FIELD

An embodiment of the present disclosure relates to a display substrate, a manufacturing method thereof and a display device.

BACKGROUND

An Organic Light Emitting Diode (OLED) display panel has a series of advantages such as self-luminescence, high contrast, high definition, wide viewing angle, low power consumption, fast response speed, and low manufacturing cost, has become one of the key development directions of a new generation of display panels, and then has received more and more attention.

An organic light-emitting layer and other functional layers of the OLED display panel are usually prepared by evaporation and other methods through a fine metal mask (FMM). In the preparation process, the FMM is usually located at a certain distance from a display substrate, to prevent the FMM from scratching functional structures on the display substrate.

SUMMARY

At least one embodiment of the present disclosure provides a display substrate, the display substrate comprises: a base substrate; a pixel defining layer, disposed on the base substrate and including a plurality of openings; and at least one photo spacer, disposed on a side of the pixel defining layer away from the base substrate, and a distance from any point at a bottom of the at least one photo spacer contacting the pixel defining layer to an upper edge of a side wall of the plurality of openings is greater than or equal to 5 μm.

For example, the display substrate provided by at least one embodiment of the present disclosure further comprises a pixel circuit structure disposed between the base substrate and the pixel defining layer and including a first signal line and a second signal line which are parallel to each other, and a first orthographic projection of the at least one photo spacer on the base substrate is located between a second orthographic projection of the first signal line on the base substrate and a third orthographic projection of the second signal line on the base substrate.

For example, in the display substrate provided by at least one embodiment of the present disclosure, the first signal line is a light-emitting control signal line, and the second signal line is a reset signal line.

For example, in the display substrate provided by at least one embodiment of the present disclosure, a distance from a center of the first orthographic projection to a central axis of the second orthographic projection is greater than a distance from the center of the first orthographic projection to a central axis of the third orthographic projection.

For example, in the display substrate provided by at least one embodiment of the present disclosure, the at least one photo spacer includes a plurality of photo spacers arranged in a plurality of rows and a plurality of columns; the pixel circuit structure includes a plurality of pixel circuits arranged in a plurality of rows and a plurality of columns; each row of pixel circuits share one light-emitting control signal line and one reset signal line; and orthographic projections of one row of photo spacers is located between an orthographic projection of the light-emitting control signal line of one row of pixel circuits on the base substrate and an orthographic projection of the reset signal line of a next row of pixel circuits on the base substrate.

For example, in the display substrate provided by at least one embodiment of the present disclosure, in each row of pixel circuits, every four adjacent pixel circuits are correspondingly provided with one photo spacer.

For example, in the display substrate provided by at least one embodiment of the present disclosure, the at least one photo spacer includes a plurality of photo spacers arranged in a plurality of rows and a plurality of columns; and a plurality of photo spacers disposed in an odd row and a plurality of photo spacers disposed in an even row are shifted ½ pitch.

For example, in the display substrate provided by at least one embodiment of the present disclosure, the plurality of openings include a first opening for a blue subpixel, a second opening for a red subpixel, and a third opening for a green subpixel; and sizes of the first opening, the second opening and the third opening are reduced gradually.

For example, in the display substrate provided by at least one embodiment of the present disclosure, by taking one blue subpixel, one red subpixel and two green subpixels as one repeat unit, the display substrate comprises a plurality of repeat units arranged in a plurality of rows and a plurality of columns; each repeat unit is correspondingly provided with one photo spacer; in each repeat unit, the third openings of the two green subpixels are arranged along a row direction; the first opening of the blue subpixel and the third opening of the red subpixel are arranged along a column direction; and the photo spacer is surrounded by the third openings of the two green subpixels, the first opening of the blue subpixel, and the third opening of the red subpixel.

For example, in the display substrate provided by at least one embodiment of the present disclosure, a connecting line of centers of the third openings of the two green subpixels in each repeat unit runs through the photo spacer, and the connecting line is parallel to a length direction of the photo spacer.

For example, in the display substrate provided by at least one embodiment of the present disclosure, the length direction of the photo spacer is a horizontal display direction of the display substrate.

For example, in the display substrate provided by at least one embodiment of the present disclosure, an orthographic projection of the photo spacer on the base substrate is overlapped with an orthographic projection of a region in which a pixel circuit of the red subpixel is located on the base substrate.

For example, in the display substrate provided by at least one embodiment of the present disclosure, a height of the at least one photo spacer is 0.8 μm-1.5 μm.

For example, in the display substrate provided by at least one embodiment of the present disclosure, a shape of an orthographic projection of the at least one photo spacer on the base substrate is rectangle.

For example, in the display substrate provided by at least one embodiment of the present disclosure, a length of the rectangle is 20 μm-30 μm, and a width of the rectangle is 10 μm-16 μm.

For example, in the display substrate provided by at least one embodiment of the present disclosure, a material of the at least one photo spacer is polyimide.

At least one embodiment of the present disclosure provides a display substrate, the display substrate comprises: a base substrate; a pixel circuit structure, disposed on the base substrate and including a first signal line and a second signal line which are parallel to each other; a pixel defining layer, disposed on a side of the pixel circuit structure away from the base substrate and including a plurality of openings; and at least one photo spacer, disposed on a side of the pixel defining layer away from the base substrate, a first orthographic projection of the at least one photo spacer on the base substrate is located between a second orthographic projection of the first signal line on the base substrate and a third orthographic projection of the second signal line on the base substrate.

For example, in the display substrate provided by at least one embodiment of the present disclosure, the first signal line is a light-emitting control signal line, and the second signal line is a reset signal line.

For example, in the display substrate provided by at least one embodiment of the present disclosure, the pixel circuit structure also includes a power line, the power line includes a plurality of first portions and a plurality of second portions which are alternately connected; the plurality of first portions are parallel to each other, and an extension direction of the plurality of first portions is identical with an extension direction of the first signal line and the second signal line, an extension direction of the second portion is intersected with the extension direction of the first portion; and an orthographic projection of the first portion on the base substrate is partially overlapped with the first orthographic projection; and an orthographic projection of the second portion on the base substrate is partially overlapped with the first orthographic projection.

For example, in the display substrate provided by at least one embodiment of the present disclosure, the pixel circuit structure also includes a data line, an extension direction of the data line is perpendicular to the extension direction of the first signal line and the second signal line; and an orthographic projection of the data line on the base substrate is not overlapped with the first orthographic projection.

At least one embodiment of the present disclosure provides a display substrate, the display substrate comprises: a base substrate; a pixel defining layer, disposed on the base substrate and including a plurality of openings; and at least one photo spacer, disposed on a side of the pixel defining layer away from the base substrate, the plurality of openings include a first opening, a second opening and a third opening, and sizes of the first opening, the second opening and the third opening are reduced gradually; in a first direction, the first opening and the second opening are respectively disposed on two sides of the at least one photo spacer; and in a second direction perpendicular to the first direction, the third openings are disposed on two sides of the at least one photo spacer.

For example, in the display substrate provided by at least one embodiment of the present disclosure, a blue light-emitting layer is disposed in the first opening; a red light-emitting layer is disposed in the second opening; and a green light-emitting layer is disposed in the third opening.

For example, in the display substrate provided by at least one embodiment of the present disclosure, a shape of the first opening is a first square, a shape of the second opening is a second square, and a side length of the first square is greater than a side length of the second square; a shape of the third opening is rectangle, a long side of the rectangle is parallel to the side length of the first square of the first opening which is adjacent to the third opening, and a short side of the rectangle is parallel to the side length of the second square of the second opening which is adjacent to the third opening.

At least one embodiment of the present disclosure provides a display device, the display device comprises the display substrate as any mentioned above.

At least one embodiment of the present disclosure provides a method for manufacturing a display substrate, the method comprises: providing a base substrate; forming a pixel defining layer on the base substrate, the pixel defining layer including a plurality of openings; and forming at least one photo spacer on a side of the pixel defining layer away from the base substrate, a distance from any point at a bottom of the at least one photo spacer contacting the pixel defining layer to a side wall of an upper surface of the plurality of openings is greater than or equal to 5 μm.

For example, in the method for manufacturing a display substrate provided by at least one embodiment of the present disclosure, the forming the at least one photo spacer on a side of the pixel defining layer away from the base substrate includes: positioning a forming position of the at least one photo spacer, so that the distance from any point at the bottom of the formed at least one photo spacer contacting the pixel defining layer to the side wall of the upper surface of the plurality of openings is greater than or equal to 5 μm.

For example, the method for manufacturing a display substrate provided by at least one embodiment of the present disclosure further comprises: forming a pixel circuit structure between the base substrate and the pixel defining layer, the pixel circuit structure including a first signal line and a second signal line which are parallel to each other, the positioning the forming position of the at least one photo spacer includes: positioning positions of the first signal line and the second signal line; and positioning the forming position of the at least one photo spacer by taking the positions of the first signal line and the second signal line as reference, so that a first orthographic projection of the formed at least one photo spacer on the base substrate is located between a second orthographic projection of the first signal line on the base substrate and a third orthographic projection of the second signal line on the base substrate.

For example, in the method for manufacturing a display substrate provided by at least one embodiment of the present disclosure, the first signal line is a light-emitting control signal line, and the second signal line is a reset signal line.

For example, in the method for manufacturing a display substrate provided by at least one embodiment of the present disclosure, a material of the at least one photo spacer is polyimide; and the forming the at least one photo spacer includes: forming a polyimide material layer on a side of the pixel defining layer away from the base substrate; and forming the at least one photo spacer by performing exposure and development on the polyimide material layer via a mask.

DETAILED DESCRIPTION

In the manufacturing process of the display substrate, functional layers such as an organic light-emitting layer are usually formed by evaporation and other means through an FMM. At this point, the FMM is usually locates at a certain distance from a display substrate to prevent the FMM from scratching functional layers on the display substrate. However, in the manufacturing process, a middle portion of the display substrate or the FMM will sink due to the reasons such as gravity, so that the distance between the display substrate and the FMM becomes smaller, and even the display substrate will contact the FMM. At this point, a photo spacer (PS) may be disposed on the display substrate to support the FMM, so as to prevent the FMM from contacting functional structures on the display substrate and scratching the functional structures on the display substrate. At this point, the setting position of the photo space, the structure of the photo space, and the like will affect the support effect of the photo space, and meanwhile, will affect the evaporation uniformity of evaporation material in the subsequent evaporation process.

At least one embodiment of the present disclosure provides a display substrate, a manufacturing method thereof and a display device. The display substrate comprises a base substrate, a pixel defining layer (PDL) and at least one photo spacer. The pixel defining layer is disposed on the base substrate and includes a plurality of openings. Each opening defines a light-emitting region of one subpixel. The at least one photo spacer is disposed at a side of the pixel defining layer away from the base substrate. On a surface at a side of the pixel defining layer away from the base substrate, a distance from any point at the bottom of the at least one photo spacer contacting the pixel defining layer to boundaries of the plurality of openings directly adjacent to the photo spacer is greater than or equal to 5 μm.

In the manufacturing process of the above display substrate, the photo spacer can support the FMM and isolate the FMM from the display substrate, so as to prevent the FMM from scratching the functional layers on the display substrate. In addition, a distance between the photo spacer and a boundary of the opening of the pixel defining layer is greater than or equal to 5 μm. As a deformed portion of the FMM or the display substrate when recessed is mainly located at a portion supported by the photo spacer and a portion away from the photo spacer is less deformed and more uniform, the bottom of the opening of the pixel defining layer is basically parallel to the FMM, and a big change in the parallel relationship between the bottom of the opening of the pixel defining layer and the FMM, due to the deformation such as the recession of the FMM or the display substrate between adjacent photo spacers, will not occur. Thus, a material evaporated to the openings of the pixel defining layer through the FMM is more uniform, and then the quality of the display substrate is improved.

Description will be given below to the display substrate, the manufacturing method thereof and the display device provided by some embodiments of the present disclosure with reference to several specific embodiments.

At least one embodiment of the present disclosure provides a display substrate.FIG.1Ais a schematic plan view of the display substrate. As shown inFIG.1A, the display substrate comprises a base substrate101, a pixel defining layer and at least one photo spacer402. The pixel defining layer is disposed on the base substrate101and includes a plurality of openings401. Light-emitting layers and the like for light-emitting elements are formed in the plurality of openings401. At least one photo spacer402is disposed on a side of the pixel defining layer away from the base substrate101. A distance D from any point at the bottom of the at least one photo spacer402contacting the pixel defining layer to upper edges (that is, edges on a side of side walls of the plurality of openings401away from the base substrate101, or edges of the plurality of openings401on a surface of the pixel defining layer contacting the photo spacer402) of the side walls of the plurality of openings401is greater than or equal to 5 μm.

For instance, as shown inFIG.1A, the plurality of openings include a first opening4011, a second opening4012and third opening4013with different sizes. The shortest distance D between the photo spacer402and the boundaries of the openings directly adjacent to the photo spacer, that is, the shortest distance D between any point at the bottom of the photo spacer402contacting the pixel defining layer and the boundaries of the plurality of openings401directly adjacent to the photo spacer, is greater than or equal to 5 μm.

For instance, in some embodiments, the display substrate includes a plurality of subpixels that can emit light of different colors (such as red, blue and green). As light-emitting layers that can emit light of different colors have different light-emitting efficiency and service life, the light-emitting layers that can emit light of different colors may be respectively formed in the openings with different sizes, so as to form the plurality of subpixels that can emit light of different colors. For instance, light-emitting layers of subpixels with low light-emitting efficiency or light-emitting layers of subpixels with a small number of openings are formed in openings with large size, and light-emitting layers of subpixels with high light-emitting efficiency or light-emitting layers of subpixels with a large number of openings are formed in openings with small size, so as to balance the light-emitting brightness of the subpixels of different colors.

For instance, in one example, a blue light-emitting layer, a red light-emitting layer and a green light-emitting layer may be respectively formed in the first opening4011, the second opening4012and the third opening4013whose opening sizes sequentially decrease. Thus, the first opening4011is configured to form blue subpixel; the second opening4012is configured to form red subpixel; and the third opening4013is configured to form green subpixel, so as to balance the light-emitting brightness of the subpixels of different colors.

For instance, the photo spacer102is surrounded by the first opening4011, the second opening4012and two third openings4013. For instance, in some examples, as shown inFIG.1A, in a first direction D1(namely the vertical direction inFIG.1A), the first opening4011and the second opening4012are respectively on two sides of the photo spacer402; and in a second direction D2perpendicular to the first direction D1(namely the horizontal direction inFIG.1A), the third openings4013are respectively on two sides of the photo spacer402.

For instance, a shape of the first opening4011is a first square; a shape of the second opening4012is a second square; and a side length of the first square is greater than a side length of the second square. A shape of the third opening4013is rectangle; a long side of the rectangle is parallel to the side length of the first square of the adjacent first opening4011; and a short side of the rectangle is parallel to the side length of the second square of the adjacent second opening4012. For instance, in other embodiments, the shape of the first opening4011may also be replaced by a first circle; the shape of the second opening4012may also be replaced by a second circle; and the shape of third opening4013may also be replaced by an ellipse. At this point, a diameter of the first circle is greater than a diameter of the second circle; a straight line where a major axis of the ellipse is located runs through centers of two second openings4012adjacent to the ellipse; and a straight line where a short axis of the ellipse is located runs through centers of two first openings4011adjacent to the ellipse. Thus, distances from the photo spacer402to the plurality of openings, that is, the first opening4011, the second opening4012and the third openings4013, are substantially the same, so that the photo spacer has sufficient and uniform support function to the FMM on peripheries of the openings, and then materials evaporated to the openings via the FMM are more uniform.

It should be noted that the above opening401will be usually designed to be regular shape such as quadrangle, pentagon, hexagon, circle or ellipse. However, in actual manufacturing process, the shape of the formed opening401will generally deviate from the above designed regular shape. For instance, angles of the above regular shape may become rounded corners, so the shape of the opening401may be rounded corner pattern. In addition, the shape of the actually formed opening401may also have other changes to the designed shape. For instance, the shape of an effective light-emitting region that is designed to be rectangular may become approximately elliptical in actual manufacturing process. At this point, the above square or rectangle may become a rounded square or a rounded rectangle.

For instance, taking the first opening4011, the second opening4012and the two third openings4013as one repeat unit, each repeat unit may be correspondingly provided with two photo spacers. At this point, each photo spacer is disposed between every two adjacent third openings4013on the display substrate, and a plurality of photo spacers are uniformly arranged as an array with a plurality of rows and a plurality of columns on the display substrate.

For instance, as shown inFIG.1A, in each repeat unit, shapes of the two third openings4013are in mirror symmetry; a connecting line of centers of the two third openings4013runs through the photo spacer402between the two third openings; and a connecting line of apex angles of the two third openings4013closest to the photo spacer402also runs through the photo spacer402between the two third openings. For instance, a connecting line of a center of the first opening4011and a center of the second opening4012runs through the photo spacer402, for example, runs through a center of the photo spacer402, that is to say, the center of the first opening4011, the center of the second opening4012, and the center of the photo spacer402are located in one straight line. For instance, a length direction of the photo spacer402is parallel to a direction of the connecting line of the centers of the two third openings4013, and a width direction of the photo spacer402is parallel to a direction of the connecting line of the center of the first opening4011and the center of the second opening4012.

In some embodiments, each repeat unit may also be correspondingly provided with one photo spacer. At this point, as shown inFIG.1B, the photo spacer402may be disposed between the two third openings4013of each repeat unit, and the plurality of photo spacers402are uniformly distributed on the display substrate in a staggered form. For instance, a photo spacer in an odd row and a photo spacer in an even row deviates ½ pitch, and one pitch refers to a distance between two adjacent photo spacers in each row of photo spacers. Or every two repeat units may also be correspondingly provided with one photo spacer. At this point, each photo spacer may be disposed between two third openings4013of repeat units spaced from each other. Or every four repeat units (the four repeat units are, for example, arranged in a 2×2 array) may also be correspondingly provided with one photo spacer. At this point, each photo spacer may be disposed between two third openings4013of repeat units at the same position in every four repeat units. In the above arrangement, the photo spacers can all show sufficient and uniform support effect.

For instance, the display substrate further comprises a pixel circuit structure which is disposed between the base substrate and the pixel defining layer. The pixel circuit structure includes first signal lines (e.g., EM lines as shown inFIG.1A, with more details given later) and second signal lines (e.g., RST lines as shown inFIG.1A, with more details given later) which are parallel to each other. A first orthographic projection of the at least one photo spacer402on the base substrate is located between a second orthographic projection of the first signal line on the base substrate and a third orthographic projection of the second signal line on the base substrate, that is, the first orthographic projection falls within the range defined by the second orthographic projection and the third orthographic projection.

For instance, in some examples, a distance from a center of the first orthographic projection to a central axis (e.g., EM0line as shown inFIG.1A) of the second orthographic projection is greater than a distance from the center of the first orthographic projection to a central axis (e.g., RST0line as shown inFIG.1A) of the third orthographic projection, that is, the at least one photo spacer402is closer to the second signal line between the first signal line and the second signal line.

For instance, the pixel circuit structure of the display substrate includes a pixel circuit for driving a plurality of subpixels to emit light, e.g., a 2T1C (namely including two thin-film transistors (TFTs) T and one storage capacitor C) pixel circuit, a 3T1C (namely including three thin-film transistors T and one storage capacitor C) pixel circuit, or a 7T1C (namely including seven thin-film transistors T and one storage capacitor C) pixel circuit. Two parallel signal lines in the driving circuit may be implemented as the above first signal line and the above second signal line. Description will be given below by taking the 7T1C driving circuit as an example.

For instance,FIG.2Ais a circuit diagram of a 7T1C pixel circuit. As shown inFIG.2A, the pixel circuit includes a driving circuit122, a data write circuit126, a compensation circuit128, a storage circuit127, a first light-emitting control circuit123, a second light-emitting control circuit124and a reset circuit12.

For instance, the driving circuit122includes a control terminal131, a first terminal132and a second terminal133and is configured to control the driving current flowing across a light-emitting element120; the control terminal131of the driving circuit122is connected with a first node N1; the first terminal132of the driving circuit122is connected with a second node N2; and the second terminal133of the driving circuit122is connected with a third node N3.

For instance, the data write circuit126includes a control terminal, a first terminal and a second terminal; the control terminal is configured to receive a first scanning signal; the first terminal is configured to receive a data signal; and the second terminal is connected with the first terminal132(the second node N2) of the driving circuit122and is configured to write the data signal into the first terminal132of the driving circuit122in response to a first scanning signal Ga1. For instance, the first terminal of the data write circuit126is connected with a data line12to receive the data signal, and the control terminal is connected with a scanning line11to receive the first scanning signal Ga1.

For instance, in the data write phase, the data write circuit126may be switched on in response to the first scanning signal Ga1, so as to write the data signal into the first terminal132(the second node N2) of the driving circuit122and store the data signal into the storage circuit127, thereby generating the driving current for driving the light-emitting element120to emit light according to the data signal in, for example, a light-emitting phase.

For instance, the compensation circuit128includes a control terminal, a first terminal and a second terminal; the control terminal is configured to receive a second scanning signal Ga2; the first terminal and the second terminal are respectively electrically connected with the control terminal131and the second terminal133of the driving circuit122; and the compensation circuit is configured to perform threshold compensation on the driving circuit120in response to the second scanning signal.

For instance, the storage circuit127is electrically connected with the control terminal131of the driving circuit122and a first voltage terminal VDD and is configured to store the data signal written by the data write circuit126. For instance, in a data write and compensation phase, the compensation circuit128may be switched on in response to the second scanning signal Ga2and then may store the data signal written by the data write circuit126into the storage circuit127. For instance, in the data write and compensation phase, the compensation circuit128may also be electrically connected with the control terminal131and the second terminal133of the driving circuit122, so that relevant information of a threshold voltage of the driving circuit122may also be correspondingly stored in the storage circuit. Thus, the driving circuit122may be controlled by utilization of the stored data signal and the threshold voltage in, for example, the light-emitting phase, so that an output of the driving circuit122can be compensated.

For instance, the first light-emitting control circuit123is connected with the first terminal132(the second node N2) of the driving circuit122and the first voltage terminal VDD and is configured to apply the first supply voltage of the first voltage terminal VDD to the first terminal132of the driving circuit122in response to a first light-emitting control signal. For instance, as shown inFIG.2A, the first light-emitting control circuit123is connected with a first light-emitting control terminal EM1, the first voltage terminal VDD and the second node N2.

For instance, the second light-emitting control circuit124is connected with a second light-emitting control terminal EM2, a first terminal510of the light-emitting element120, and the second terminal132of the driving circuit122, and is configured to apply the driving current to the light-emitting element120in response to a second light-emitting control signal.

For instance, in the light-emitting phase, the second light-emitting control circuit124is switched on in response to the second light-emitting control signal provided by the second light-emitting control terminal EM2, so that the driving circuit122can apply the driving current to the light-emitting element120through the second light-emitting control circuit124to allow the light-emitting element to emit light. In the non-light-emitting phase, the second light-emitting control circuit124is switched off in response to the second light-emitting control signal, so as to avoid the current from flowing across the light-emitting element120to drive the light-emitting element to emit light, and then the contrast of corresponding display device can be improved.

Moreover, for instance, in an initialization phase, the second light-emitting control circuit124may also be switched on in response to the second light-emitting control signal, so as to be combined with a reset circuit to perform the reset operation on the driving circuit122and the light-emitting element120.

For instance, the second light-emitting control signal EM2and the first light-emitting control signal EM1may be the same or different. For example, both may be connected to the same or different signal output terminals.

For instance, a reset circuit129is connected with a reset voltage terminal Vinit and a first terminal134(a fourth node N4) of the light-emitting element120and is configured to apply a reset voltage to the first terminal134of the light-emitting element120in response to a reset signal. In some other examples, as shown inFIG.2A, the reset signal may also be applied to the control terminal131of the driving circuit, namely the first node N1. For instance, the reset signal is the second scanning signal and may also be other signals synchronous with the second scanning signal. No limitation will be given here in the embodiment of the present disclosure. For instance, as shown inFIG.2A, the reset circuit129is respectively connected with the first terminal134of the light-emitting element120, the reset voltage terminal Vinit and a reset control terminal Rst (a reset control line). For instance, in the initialization phase, the reset circuit129may be switched on in response to the reset signal, so as to apply the reset voltage to the first terminal134of the light-emitting element120and the first node N1, thereby performing reset operation on the driving circuit122, the compensation circuit128and the light-emitting element120, and finally eliminating the effect of the previous light-emitting phase.

For instance, the light-emitting element120includes the first terminal134and a second terminal135; the first terminal134of the light-emitting element120is configured to receive the driving current from the second terminal133of the driving circuit122; and the second terminal135of the light-emitting element120is configured to be connected with a second voltage terminal VSS. For instance, in one example, as shown inFIG.2A, the first terminal134of the light-emitting element120may be connected to the third node N3through the second light-emitting control circuit124. The embodiment of the present disclosure includes but not limited to this case. For instance, the light-emitting element120may be various types of OLEDs, e.g., top-emission, bottom-emission or double-sided emission, and may emit red light, green light, blue light, white light, etc. A first electrode and a second electrode of the OLED are respectively taken as the first terminal134and the second terminal135of the light-emitting element. No limitation will be given to the specific structure of the light-emitting element in the embodiment of the present disclosure.

It should be noted that in the description of the embodiment of the present disclosure, the first node N1, the second node N2, the third node N3and the fourth node N4are not necessarily actual components but indicate the junctions of related circuit connections in the circuit diagram.

It should be noted that in the description of the embodiment of the present disclosure, a symbol Vd not only may indicate a data signal terminal but also may indicate a level of the data signal. Similarly, symbols Ga1and Ga2not only may indicate the first scanning signal and the second scanning signal but also may indicate the first scanning signal terminal and the second scanning signal terminal; Rst not only may indicate a reset control terminal but also may indicate a reset signal; a symbol Vinit not only may indicate the reset voltage terminal but also may indicate the reset voltage; a symbol VDD not only may indicate the first voltage terminal but also may indicate the first supply voltage; and a symbol VSS not only may indicate the second voltage terminal but also may indicate the second supply voltage. The following embodiments are the same with the embodiment, so no further description will be given here.

FIG.2Bis a circuit diagram of a specific implementation example of the pixel circuit as shown inFIG.2A. As shown inFIG.2B, the pixel circuit includes: first to seventh transistors T1, T2, T3, T4, T5, T6and T7and a storage capacitor Cst. For instance, the first transistor T1is used as a driving transistor, and the other second to seventh transistors are used as switching transistors.

For instance, as shown inFIG.2B, the driving circuit122may be implemented as the first transistor T1. A gate electrode of the first transistor T1is taken as the control terminal131of the driving circuit122and is connected with the first node N1; a first electrode of the first transistor T1is taken as the first terminal132of the driving circuit122and is connected with the second node N2; and a second electrode of the first transistor T1is taken as the second terminal133of the driving circuit122and is connected with the third node N3.

For instance, as shown inFIG.2B, the data write circuit126may be implemented as the second transistor T2. A gate electrode of the second transistor T2is connected with the first scanning line (the first scanning signal terminal Ga1) to receive the first scanning signal; a first electrode of the second transistor T2is connected with the data line (the data signal terminal Vd) to receive the data signal; and a second electrode of the second transistor T2is connected with the first terminal132of the driving circuit122(the second node N2). For instance, the second transistor T2is a P-type transistor. For example, an active layer is a low-temperature doped polysilicon TFT.

For instance, as shown inFIG.2B, the compensation circuit128may be implemented as the third transistor T3. A gate electrode of the third transistor T3is configured to be connected with the second scanning line (the second scanning signal terminal Ga2) to receive the second scanning signal; a first electrode of the third transistor T3is connected with the control terminal131of the driving circuit122(the first node N1); and a second electrode of the third transistor T3is connected with the second terminal133of the driving circuit122(the third node N3).

For instance, as shown inFIG.2B, the storage circuit127may be implemented as the storage capacitor Cst. The storage capacitor Cst includes a first capacitor electrode Ca and a second capacitor electrode Cb. The first capacitor electrode Ca is connected with the first voltage terminal VDD. The second capacitor electrode Cb is connected with the control terminal131of the driving circuit122.

For instance, as shown inFIG.2B, the first light-emitting control circuit123may be implemented as the fourth transistor T4. A gate electrode of the fourth transistor T4is connected with the first light-emitting control line (the first light-emitting control terminal EM1) to receive the first light-emitting control signal; a first electrode of the fourth transistor T4is connected with the first voltage terminal VDD to receive the first supply voltage; and a second electrode of the fourth transistor T4is connected with the first terminal132of the driving circuit122(the second node N2).

For instance, the light-emitting element120may be implemented as an OLED; the first electrode134(an anode here) of the light-emitting element120is connected with the fourth node N4and is configured to receive the driving current from the second terminal133of the driving circuit122through the second light-emitting control circuit124; and the second electrode135(a cathode here) of the light-emitting element120is configured to be connected with the second voltage terminal VSS to receive the second supply voltage. For instance, the second voltage terminal may be grounded, that is, VSS may be 0V.

For instance, the second light-emitting control circuit124may be implemented as the fifth transistor T5. A gate electrode of the fifth transistor T5is connected with the second light-emitting control line (the second light-emitting control terminal EM2) to receive the second light-emitting control signal; a first electrode of the fifth transistor T5is connected with the second terminal133of the driving circuit122(the third node N3); and a second electrode of the fifth transistor T5is connected with the first terminal134of the light-emitting element120(the fourth node N4).

For instance, the reset circuit129may include a first reset circuit and a second reset circuit. The first reset circuit is configured to apply a first reset voltage Vini1to the first node N1in response to a first reset signal Rst1. The second reset circuit is configured to apply a second reset voltage Vini2to the fourth node N4in response to a second reset signal Rst2. For instance, as shown inFIG.2B, the first reset circuit is implemented as the sixth transistor T6, and the second reset circuit is implemented as the seventh transistor T7. A gate electrode of the sixth transistor T6is configured to be connected with the first reset control terminal Rst1to receive the first reset signal Rst1; a first electrode of the sixth transistor T6is connected with the first reset voltage terminal Vinit1to receive the first reset voltage Vinit1; and a second electrode of the sixth transistor T6is configured to be connected with the first node N1. A gate electrode of the seventh transistor T7is configured to be connected with the second reset control terminal Rst2to receive the second reset signal Rst2; a first electrode of the seventh transistor T7is connected with the second reset voltage terminal Vinit2to receive the second reset voltage Vinit2; and a second electrode of the seventh transistor T7is configured to be connected with the fourth node N4.

It should be noted that the transistors adopted in the embodiment of the present disclosure may all be thin-film transistors or field-effect transistors (FETs) or other switching elements with the same characteristics. Description is given in the embodiment of the present disclosure by taking the TFT as an example. A source electrode and a drain electrode of the transistor adopted here may be symmetrical in structure, so the source electrode and the drain electrode have no difference in structure. In the embodiment of the present disclosure, in order to distinguish two electrodes except the gate electrode of the transistor, one electrode is directly described as the first electrode and the other electrode is directly described as the second electrode.

For instance, as shown inFIG.1A, the first signal line is the light-emitting control line EM and is configured to transmit the first light-emitting control signal and the second light-emitting control signal; and the second signal line is the reset control line RST and is configured to transmit the first reset signal Rst1and the second reset signal Rst2. Thus, a first orthographic projection of the photo spacer402on the base substrate101is located between a second orthographic projection of the light-emitting control line EM on the base substrate101and a third orthographic projection of the reset control line RST on the base substrate101, for example, being closer to the third orthographic projection.

For instance, inFIG.1A, a reset voltage line VT is disposed between the light-emitting control line EM and the reset control line RST and is configured to transmit the first reset voltage Vinit1and the second reset voltage Vinit2. For instance, an orthographic projection of the photo spacer402on the base substrate101is partially overlapped with an orthographic projection of the above reset voltage line VT on the base substrate101.

The layout of the above pixel circuit will be described in detail below.

FIG.3is a schematic plan view of a display substrate provided by at least one embodiment of the present disclosure. The display substrate comprises a base substrate101, and a plurality of subpixels100are disposed on the base substrate101and are arranged in an array on the base substrate101along a row direction (namely a transverse direction in the figure) and a column direction (namely a longitudinal direction in the figure). The column direction of the subpixel array is set to be a first direction D1, and the row direction is a second direction D2. The first direction DD1is intersected with the second direction D2, for example, in orthogonal intersection with the second direction D2.FIG.3illustratively shows pixel circuits of directly adjacent four subpixels (that is, a first subpixel100a, a second subpixel100b, a third subpixel100cand a fourth subpixel100d) in one row of subpixel circuits, and dotted frames show regions in which the pixel circuits of the subpixels are located. The embodiment of the present disclosure is not limited to the layout.

FIG.4Ashows a semiconductor layer102and a first conductive layer (a gate layer)201of transistors T1-T7in the four subpixels100corresponding toFIG.3.FIG.4Balso shows a second conductive layer202on the basis ofFIG.4A.FIG.4Calso shows a third conductive layer203on the basis ofFIG.4B.FIG.4Dalso shows a fourth conductive layer204on the basis ofFIG.4C. It should be noted that the figure only illustratively shows corresponding structures of four adjacent subpixels in one row of subpixels, but should not be construed as the limitation of the present disclosure. The semiconductor layer102, the first conductive layer201, the second conductive layer202, the third conductive layer203and the fourth conductive layer204are sequentially disposed on the base substrate101, so as to form the structure of the display substrate as shown inFIG.3.

For convenient description, Tng, Tns, Tnd and Tna are used to respectively indicate a gate electrode, a first electrode, a second electrode and an active layer of the nth transistor Tn in the following description, wherein n is 1-7.

It should be noted that “arranged in the same layer” in the present disclosure indicates that two (or more than two) structures are structures formed by the same deposition process and patterned by the same patterning process, and materials thereof may be the same or different. The “integral structure” in the present disclosure indicates that two (or more than two) structures are connected structures formed by the same deposition process and patterned by the same patterning process, and the materials thereof may be the same or different.

For instance, as shown inFIG.4A, the first conductive layer201includes a gate electrode of each transistor and some scanning lines and control lines. InFIG.4A, a large dotted frame shows a region in which a pixel circuit of each subpixel100is located, and small dotted frames show gate electrodes T1g-T7gof the first to seventh transistors T1-T7in one subpixel100.

The semiconductor layer102includes active layers T1a-T7aof the first to seventh transistors T1-T7. As shown inFIG.3A, the active layers T1a-T7aof the first to seventh transistors T1-T7are integrally connected structures. For instance, the semiconductor layers20in each column of subpixels are integrally connected structures, and the semiconductor layers in two adjacent columns of subpixels are spaced from each other.

For instance, as shown inFIG.4A, the first conductive layer104includes the gate electrodes T1g-T7gof the first to seventh transistors T1-T7. For instance, the third transistor T3and the sixth transistor T6adopt double-gate structure, so as to improve the gate control ability of the transistor and reduce the leak current.

For instance, the first conductive layer104also includes a plurality of scanning lines210, a plurality of reset control lines220/RST, and a plurality of light-emitting control lines230/EM which are insulated from each other. For instance, each row of subpixels are respectively and correspondingly connected with one scanning line210, one reset control line220/RST and one light-emitting control line230/EM.

The scanning line210is electrically connected with the gate electrode of the second transistor T2in one corresponding row of subpixels (or be an integral structure) to provide the first scanning signal Ga1; the reset control line220/RST is electrically connected with the gate electrode of the sixth transistor T6in one corresponding row of subpixels to provide the first reset signal Rst1; and the light-emitting control line230/EM is electrically connected with the gate electrode of the fourth transistor T4in one corresponding row of subpixels to provide the first light-emitting control signal EM1.

For instance, as shown inFIG.4A, the scanning line210is also electrically connected with the gate electrode of the third transistor T3to provide the second scanning signal Ga2; and the light-emitting control line230/EM is also electrically connected with the gate electrode of the fifth transistor T5to provide the second light-emitting control signal EM2, that is, the first light-emitting control signal EM1and the second light-emitting control signal EM2are the same signal.

For instance, as shown inFIG.4A, the gate electrode of the seventh transistor T7in this row of subpixels is electrically connected with a corresponding reset control line220/RST of the next row of subpixels to receive the second reset signal Rst2.

For instance, as shown inFIG.4A, a line of the row direction that divides the pixel circuit region of the subpixel may be the reset control line220/RST or the light-emitting control line230/EM.

For instance, as shown inFIG.4A, the display substrate20adopts self-aligned process and utilizes the first conductive layer201as a mask for conduction treatment (e.g., doped treatment) on the semiconductor layer102, so that a portion of the semiconductor layer102not covered by the first conductive layer201is conducted, and then portions of the active layer of the transistor, disposed on two sides of a channel region, are conducted to respectively form the first electrode and the second electrode of the transistor.

For instance, as shown inFIG.4B, the second conductive layer202includes a first capacitor electrode Ca of the first to seventh transistors T1-T7. The first capacitor electrode Ca is overlapped with the gate electrode T1gof the first transistor T1in a direction perpendicular to the base substrate101to form a storage capacitor Cst, that is, the gate electrode T1gof the first transistor T1serves as a second capacitor electrode Cb of the storage capacitor Cst. For instance, the first capacitor electrode Ca includes a through hole301. The through hole301exposes at least one portion of the gate electrode T1gof the first transistor T1, so as to make the gate electrode T1geasily to be connected with other structures.

For instance, the second conductive layer202may also include a plurality of reset voltage lines240/VT. The plurality of reset voltage lines240/VT are connected with a plurality of rows of subpixels in one-to-one correspondence relationship. The reset voltage line240/VT is electrically connected with the first electrode of the sixth transistor T6in one corresponding row of subpixels to provide the first reset voltage Vinit1.

For instance, as shown inFIG.4B, the first electrode of the seventh transistor T7in this row of subpixels is electrically connected with the reset voltage line240/VT corresponding to the next row of subpixels to receive the second reset voltage Vinit2.

For instance, as shown inFIG.4B, the second conductive layer202may also include a shielding electrode221. The shielding electrode221is overlapped with the first electrode T2sof the second transistor T2in the direction perpendicular to the base substrate101so as to protect a signal in the first electrode T2sof the second transistor T2from being interfered by other signals. As the first electrode T2sof the second transistor T2is configured to receive a data signal Vd and the data signal Vd determines the display grayscale of the subpixel, the shielding electrode221improves the stability of the data signal and then improves the display performance.

For instance, as shown inFIG.4C, the third conductive layer203includes a plurality of first power lines250extended along the first direction D1. For instance, the plurality of first power lines250are electrically connected with a plurality of columns of subpixels in one-to-one correspondence to provide the first supply voltage VDD. The first power line250is electrically connected with the first capacitor electrode Ca in one corresponding column of subpixels through a through hole302and is electrically connected with the first electrode of the fourth transistor T4through a through hole303. For instance, the first power line250is also electrically connected with the shielding electrode221through a through hole304, so that the shielding electrode221has fixed potential, and then the shielding capability of the shielding electrode is improved.

For instance, the third conductive layer203also includes a plurality of data lines12. The plurality of data lines12are electrically connected with the plurality of columns of subpixels in one-to-one correspondence to provide the data signal. For instance, the data line12is electrically connected with the first electrode T2sof the second transistor T2in one corresponding column of subpixels through a through hole305to provide the data signal.

For instance, as shown inFIG.4C, the third conductive layer203also includes a first connecting electrode231. One terminal of the first connecting electrode231is electrically connected with the gate electrode T1gof the first transistor T1, namely the second capacitor electrode Cb, through the through hole301, and the other terminal is electrically connected with the first electrode of the third transistor T3, so that the second capacitor electrode Cb is electrically connected with the first electrode T3sof the third transistor T3.

For instance, as shown inFIG.4C, the third conductive layer203also includes a second connecting electrode232. Two terminals of the second connecting electrodes232are respectively electrically connected with the first electrode T6sof the sixth transistor T6and the reset voltage line240/VT, so that the first electrode T6sof the sixth transistor T6may receive the first reset voltage Vinit1from the reset voltage line240/VT.

For instance, as shown inFIG.4C, the third conductive layer203also includes a third connecting electrode233. The third connecting electrode233is electrically connected with the second electrode T5dof the fifth transistor T5and is configured to allow the second electrode T5dof the fifth transistor T5to be electrically connected with the first electrode134of the light-emitting element, which will be explained in detail later.

For instance, as shown inFIG.4D, the fourth conductive layer204includes a second power line260. The second power line260is extended along the second direction D2and configured to electrically connect the plurality of first power lines240to form a meshed power line structure. This structure helps to reduce the resistance on the power line so as to reduce the voltage drop of the power line, and helps to uniformly transmit the first supply voltage to the subpixels of the display substrate.

For instance, the fourth conductive layer204also includes a plurality of third power lines270. The third power lines270are extended along the first direction D1and are electrically connected with the plurality of first power lines250in one-to-one correspondence. As shown inFIG.3D, the third power line270and a corresponding first power line250are overlapped with each other in the direction perpendicular to the base substrate101and electrically connected with each other through a through hole306. For instance, one through hole306is respectively and correspondingly formed for each subpixel, so that each third power line270and a corresponding first power line250form a parallel structure, thereby helping to reduce the resistance of the power line.

For instance, the second power line260and the third power line270are electrically connected with each other to form an integral structure, so the plurality of first power lines250, the plurality of second power lines260, and the plurality of third power lines270form a meshed power line structure.

For instance, the fourth conductive layer204also includes a fourth connecting electrode234insulated from the third power line270. The fourth connecting electrode234is electrically connected with the third connecting electrode233through a through hole307, so as to allow the second electrode T5dof the fifth transistor T5to be electrically connected with the first electrode134of the light-emitting element.

FIG.4Ealso shows a fifth conductive layer205on the basis ofFIG.4D. The fifth conductive layer205includes the first electrode134of the light-emitting element120. As shown inFIG.4E, the second power lines260are not overlapped in the direction perpendicular to the base substrate101. This setting can avoid the first electrode134of the light-emitting element from being uneven due to overlapping with the second power line260. The light-emitting layer of the light-emitting element120is directly formed on the first electrode134and an effective light-emitting region (opening region) is formed. The flatness of the first electrode134will directly affect the light-emitting efficiency of the light-emitting layer and then affect the light-emitting performance of the light-emitting element120.

For instance, the second power line260may be a curved structure so as to be adapted to a pattern of the first electrode134. For instance, two adjacent second power lines260define one row of subpixels100. For instance, as shown inFIG.4, the second power line260includes first portions261and second portions262which are alternately connected. The extension directions of the first portions261are parallel to each other and parallel to the second direction D2, and the extension directions of the second portions262are intersected with both the first direction D1and the second direction D2. For instance, each column of subpixels respectively correspond to one first portion261.

FIG.4Eshows first electrodes134a,134b,134cand134dof four adjacent subpixels, and subsequently, a pixel defining layer is formed on the first electrodes134a,134b,134cand134d. Moreover, a plurality of openings in the pixel defining layer respectively expose these first electrodes. Corresponding toFIG.1A, the first opening4011exposes the first electrode134c. At this point, a shape of the first opening4011may be the same with or similar to a shape of the first electrode134c, and a size of the first opening4011may be slightly smaller than a size of the first electrode134c, so an orthographic projection of the first opening4011on the base substrate101is completely located within an orthographic projection of the first electrode134con the base substrate101. Correspondingly, the second opening4012exposes the first electrode134a; a shape of the second opening4012may be the same with or similar to a shape of the first electrode134a; and a size of the second opening4012may be slightly smaller than a size of the first electrode134a, so an orthographic projection of the second opening4012on the base substrate101is completely located within an orthographic projection of the first electrode134aon the base substrate101. The shape of the two third openings4013may be respectively the same with or similar to the shape of the first electrode134band the shape of the first electrode134d, and the size of the two third openings4013may be slightly smaller than the sizes of the first electrode134band the first electrode134d, so that orthographic projections of the two third openings4013are respectively and completely located within orthographic projections of the first electrode134band the first electrode134don the base substrate101.

For instance, the light-emitting layer and the second electrode are respectively formed on the first electrodes134a,134b,134cand134d, so as to form light-emitting elements of a first subpixel100a, a second subpixel100b, a third subpixel100cand a fourth subpixel100d. The first subpixel100a, the second subpixel100b, the third subpixel100cand the fourth subpixel100dform a repeat unit of the display substrate.

For instance, in each repeat unit, a color of light emitted by a light-emitting element of the second subpixel100bis the same with a color of light emitted by a light-emitting element of the fourth subpixel100d, that is to say, the second subpixel100band the fourth subpixel100dare subpixels of the same color. For instance, the second subpixel100band the fourth subpixel100dare subpixels of sensitive color. When the display substrate adopts RGB display mode, the above sensitive color is green, namely both the second subpixel100band the fourth subpixel100dare green subpixels. For instance, the first subpixel100amay be a red subpixel and the third subpixel100cmay be a blue subpixel.

For instance, four subpixels in each repeat unit may form two virtual pixels. The first subpixel100aand the third subpixel100cin the repeat unit are respectively shared by the two virtual pixels. Subpixels in a plurality of repeat units form a pixel array. In a row direction of the pixel array, a density of the subpixels is 1.5 times a density of the virtual pixels. In a column direction of the pixel array, a density of the subpixels is 1.5 times a density of the virtual pixels. For instance, the second subpixel100band the fourth subpixel100drespectively belong to two virtual pixels.

It should be noted that firstly, as the first subpixel100aand the third subpixel100care shared by two adjacent virtual pixels, a boundary of each virtual pixel is not also very clear, so a shape of each virtual pixel is not limited in the embodiment of the present disclosure; and secondly, a division of the virtual pixel is relevant to the driving mode, and the specific dividing mode of the virtual pixel may be determined according to actual driving mode. No specific limitation will be given here in the present disclosure.

For instance, a shape and a size of a plurality of opening regions corresponding to the subpixels100may change according to the light-emitting efficiency, the service life and the like of the light-emitting layers that emits light of different colors. For instance, an opening region corresponding to a light-emitting layer with relatively short light-emitting service life may be set to be large, so as to improve the light-emitting stability. For instance, sizes of openings of the blue subpixel, the red subpixel and the green subpixel may be sequentially reduced. As the opening region is disposed on the first electrode134, correspondingly, as shown inFIG.4, areas of the first electrodes134a,121b,121cand121dof the first subpixel100a, the second subpixel100b, the third subpixel100cand the fourth subpixel100dare sequentially reduced.

For instance, two adjacent rows of repeat units are arranged to be shifted ½ pitch along a row direction, and the pitch indicates a distance between centers of two first subpixels100ain two repeat units adjacent to each other along the row direction. It should be noted that the pitch may also indicate a distance between centers of two third subpixels100cin two repeat units adjacent to each other along the row direction. The above center may be the geometric center of the subpixel. Of course, the embodiment of the present disclosure includes but not limited thereto. Two adjacent rows of repeat units may also be shifted other distances, or not shifted.

For instance, in two adjacent rows of repeat units, the first subpixel and the third subpixel in two adjacent repeat units along the column direction are exchanged in position, and the second subpixel and the fourth subpixel correspond to each other in position.

For instance, the first subpixels and the third subpixels are alternately arranged in a row or a column along the row and column directions, and the second subpixels and the fourth subpixels are arranged in a row or a column along the row and column directions. The rows formed by the first subpixels and the third subpixels and the rows formed by the second subpixels and the fourth subpixels are alternately arranged in the column direction. The columns formed by the first subpixels and the third subpixels and the columns formed by the second subpixels and the fourth subpixels are alternately arranged in the row direction. In a matrix formed by the first subpixels and the third subpixels, two first subpixels and two third subpixels that are distributed in two rows and two columns to form a 2*2 matrix respectively cover vertexes of one virtual rectangle, and one second subpixel or one fourth subpixel are located within the virtual rectangle, wherein two first subpixels cover two vertex angles on one diagonal of the virtual rectangle, and two third subpixels cover two vertex angles on the other diagonal of the virtual rectangle.

For instance, as shown inFIG.4E, the first electrodes134of the subpixels are electrically connected with the fourth connecting electrodes234by using through holes308, so that the second electrode T5dof the fifth transistor T5is electrically connected with the first electrode134of the light-emitting element120.

As shown inFIG.4E, a position of the at least one photo spacer402subsequently formed on the pixel defining layer is as shown by a dotted frame. At this point, a first orthographic projection of the photo spacer402on the base substrate is not overlapped with orthographic projections of the first electrodes134a,134b,134cand134don the base substrate, and the shortest distance between the photo spacer402and boundaries of the first opening4011, the second opening4012and the third openings4013directly adjacent to the photo spacer is all greater than or equal to 5 μm.

For instance, in some examples, each repeat unit is correspondingly provided with one photo spacer. The photo spacer is disposed between the third openings4013of two green subpixels (namely the second subpixel100band the fourth subpixel100d) in each repeat unit, and no photo spacer is disposed between the third openings4013of two green subpixels in two adjacent repeat units. At this point, a ratio of the number of the photo spacers on the display substrate to the number of the green subpixels is 1:2.

For instance, in each repeat unit, a connecting line of centers of the third openings4013of the two green subpixels runs through the photo spacer402between the third openings4013, and the connecting line is parallel to a length direction of the photo spacer402. For instance, when a shape of the photo spacer402is rectangle, the length direction is an extension direction of a long side of the rectangle.

For instance, the length direction of the photo spacer402is a horizontal display direction of the display substrate, namely a horizontal direction of an image viewed by human eyes when the display substrate displays. At this point, as the green subpixels are disposed on both sides of the photo spacer402in the horizontal direction, when the viewer views the display substrate respectively from two sides, subpixels that may be shielded by the photo spacer402are the same subpixels, so no color shift phenomenon will occur when the viewer views from different sides of the display substrate.

For instance, an orthographic projection of the first portion261of the second power line on the base substrate is partially overlapped with the first orthographic projection of the photo spacer402on the base substrate, and an orthographic projection of the second portion262of the second power line on the base substrate is also partially overlapped with the first orthographic projection of the photo spacer402on the base substrate. For instance, an orthographic projection of the third power line270on the base substrate is also partially overlapped with the first orthographic projection of the photo spacer402on the base substrate. At this point, the photo spacer402is formed at a position where the first portion261and the second portion262of the second power line and the third power line270are intersected with each other.

For instance, an orthographic projection of each data line12on the base substrate is not overlapped with the first orthographic projection of the photo spacer402on the base substrate. For instance, the photo spacer402is formed between two adjacent data lines12, that is, between a data line of the column of pixel circuits and a data line of the next column of pixel circuits. For instance, inFIG.4E, the data line12disposed on the left of the second opening4012is the data line of the column of pixel circuits, and the data line12disposed on the right of the second opening4012is the data line of the next column of pixel circuits.

For instance, at least one photo spacer402is disposed between the light-emitting control line230/EM (used for driving the fourth thin-film transistor T4and the fourth thin-film transistor T5of the row of pixel circuits) of the row of pixel circuits (e.g., one row of pixel circuit as shown inFIGS.4A and4B) and the reset control line220/RST (used for driving the seventh thin-film transistor T7of the row of pixel circuits and the sixth thin-film transistor T6of the next row of pixel circuits) of the next row of pixel circuits, and is closer to the reset control line220/RST.

For instance, the reset voltage line240/VT (electrically connected with the first electrode of the seventh thin-film transistor T7of the row of pixel circuits and the first electrode of the sixth thin-film transistor T6of the next row of pixel circuits) of the next row of pixel circuits is also disposed between the above light-emitting control line230/EM and the above reset control line220/RST. At this point, a orthographic projection of at least one photo spacer402on the base substrate101is partially overlapped with an orthographic projection of the reset voltage line240/VT on the base substrate101.

For instance, when the first subpixel100a, the second subpixel100b, the third subpixel100cand the fourth subpixel100dform a repeat unit of the display substrate, each repeat unit may be correspondingly provided with two photo spacers402. At this point, there is one photo spacer402between every adjacent second subpixel100band fourth subpixel100d, and a plurality of photo spacers402on the display substrate are uniformly arranged as an array with a plurality of rows and a plurality of columns Thus, the plurality of photo spacers402arranged in an array can isolate the display substrate from the FMM at a plurality of positions of the display substrate, so as to prevent the FMM from contacting the display substrate and scratching the display substrate.

In some embodiments, each repeat unit may also be correspondingly provided with one photo spacer, namely a case as shown inFIGS.1A,1B and4E. At this point, the plurality of photo spacers402are uniformly distributed on the display substrate in a staggered form. For instance, a photo spacer disposed in the odd row and a photo spacer disposed in the even row are shifted ½ pitch, and one pitch refers to a distance of two adjacent photo spacers in each row of photo spacers. Or every two repeat units may also be correspondingly provided with one photo spacer. Or every four repeat units (the four repeat units are, for example, arranged in a 2×2 array) may also be correspondingly provided with one photo spacer. In the above arrangement, the photo spacers can show sufficient and uniform support effect.

For instance, in the examples as shown inFIG.3andFIGS.4A-4F, each repeat unit is correspondingly provided with one photo spacer. At this point, a ratio of the number of the photo spacers402on the display substrate to the total number of the subpixels is roughly 1:4. For instance, in each repeat unit, an orthographic projection of the photo spacer402on the base substrate is overlapped with an orthographic projection of a region where a pixel circuit of a red subpixel (namely a region of a pixel circuit of the subpixel100aas shown by a dotted frame) is located on the base substrate. At this point, a ratio of the number of the photo spacers402on the display substrate to the number of the red subpixels is roughly 1:1. It should be noted that the above proportional relationship is defined according to a central region of a display region. As for a portion of an edge region, considering the design of a peripheral structure or redundant pixels, in some positions, the photo spacer may not be disposed, or a position and the number of the photo spacer may be adjusted, or a position and the number of subpixels may be adjusted. Thus, the above proportional relationship may fluctuate, for example, may fluctuate within 10%.

For instance, as shown inFIG.4E, a shape of the orthographic projection of the photo spacer402on the base substrate101may be rectangle. As shown inFIG.5, a length L of the rectangle may be 20 μm-30 μm, for example, 22 μm, 25 μm or 28 μm, and a width W of the rectangle may be 10 μm-16 μm, for example, 12 μm or 15 μm. At this point, a center O of the first orthographic projection of the photo spacer402on the base substrate101is a center of the rectangle.

For instance, in other examples, a shape of the first orthographic projection of the photo spacer402on the base substrate101may also be circle, ellipse, triangle or other polygons. At this point, the center O of the first orthographic projection of the photo spacer402on the base substrate101is a center of the circle or the ellipse or the center of gravity of the triangle or other polygons. Of course, in some examples, the shape of the first orthographic projection of the photo spacer402on the base substrate101may also be an irregular pattern. At this point, the center O of the first orthographic projection of the photo spacer402on the base substrate101is the center of gravity of the irregular pattern.

For instance, in some embodiments, a height of the photo spacer402may be 0.8 μm-1.5 μm, for example, 1 μm or 1.2 μm. Thus, the photo spacer402can sufficiently isolate the FMM from the display substrate to prevent the FMM from contacting the display substrate and scratching the display substrate.

For instance, a material of the photo spacer402may be polyimide (PI). As PI is a photosensitive material and may be taken as a photoresist material, in the manufacturing process, the photo spacer402may be directly formed by exposure process and development process.

FIG.4Fis a schematic cross-sectional view of the display substrate inFIG.4Ealong A-A′. As shown inFIG.4F, the semiconductor layer102, a first insulating layer103, the first conductive layer201, a second insulating layer104, the second conductive layer202, a third insulating layer105, the third conductive layer203, a fourth insulating layer106, the fourth conductive layer204, a fifth insulating layer107, and the fifth conductive layer205are sequentially disposed on the base substrate101to form a structure of the display substrate as shown inFIG.4E.

For instance, as shown inFIG.4F, the display substrate further comprises a pixel defining layer430disposed on the first electrode134aof the light-emitting element120. An opening401(namely a second opening4012in the cross-sectional view) is formed in the pixel defining layer430to define a light-emitting region of one subpixel. A light-emitting layer136is formed in the opening401, and a second electrode135is formed on the light-emitting layer136to form the light-emitting element120. For instance, the second electrode135is a common electrode and is arranged in the display substrate in an entire surface manner.

As shown inFIG.4F, the photo spacer402is disposed on the pixel defining layer, and the first orthographic projection of the photo spacer402on the base substrate101is located between the second orthographic projection of the light-emitting control line230/EM on the base substrate101and the third orthographic projection of the reset control line220/RST on the base substrate101, and is closer to the third orthographic projection. The reset voltage line240/VT is disposed between the light-emitting control line230/EM and the reset control line220/RST, and the orthographic projection of the photo spacer402on the base substrate101is overlapped with the orthographic projection of the reset voltage line240/VT on the base substrate101. In addition, the first orthographic projection of the photo spacer402on the base substrate101is not overlapped with the orthographic projection of the first electrode134aon the base substrate101, and the shortest distance D between the photo spacer402and the boundary of the opening401(the second opening4012) directly adjacent to the photo spacer is all greater than or equal to 5 μm.

For instance, in the above display substrate, the base substrate101may be a rigid substrate such as a glass substrate or a silicon substrate and may also be made from flexible materials with superior heat resistance and durability, e.g., polyimide (PI), polycarbonate (PC), polyethylene terephthalate (PET), polyethylene, polyacrylate, polyarylate, polyetherimide, polyethersulfone, polyethylene terephthalate (PET), polyethylene (PE), polypropylene (PP), polysulfone (PSF), polymethyl methacrylate (PMMA), cellulose triacetate (TAC), cyclic olefin polymer (COP) and cyclic olefin copolymer (COC).

For instance, the material of the semiconductor layer102includes but not limited to silica-base materials (amorphous silicon (a-Si), polysilicon (p-Si), etc.), metal oxide semiconductors (indium gallium zinc oxide (IGZO), zinc oxide (ZnO), aluminum-doped zinc oxide (AZO), indium zinc tin oxide (IZTO), etc.) and organic materials (hexathiophene, polythiophene, etc.).

For instance, the materials of the first to fourth conductive layers may include gold (Au), silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), magnesium (Mg), tungsten (W) and alloy materials composed of the above metals; or conductive metal oxide materials such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), aluminum-doped zinc oxide (AZO), etc.

For instance, the light-emitting element120is a top-emission structure; the first electrode134has reflectivity; and the second electrode135has transmittance or semi-transmittance. For instance, the first electrode134takes a material with high work function as an anode, for example, being an ITO/Ag/ITO stack structure; and the second electrode135takes a material with low work function, for example, semi-transmissive metal or metal alloy material, e.g., Ag/Mg alloy material, as a cathode.

For instance, the first insulating layer103, the second insulating layer104and the third insulating layer105are, for example, inorganic insulating layers, e.g., oxide, nitride or oxynitride of silicon such as silicon oxide, silicon nitride and silicon oxynitride, or insulating materials including metal oxynitride such as aluminum oxide and titanium nitride. For instance, the fourth insulating layer106, the fifth insulating layer107and a pixel defining layer108include organic insulating materials, e.g., organic insulating materials such as PI, acrylate, epoxy resin or PMMA. For instance, the fourth insulating layer106and the fifth insulating layer107are planarization layers. For instance, one inorganic insulating layer, for example, a passivation layer, e.g., oxide, nitride or oxynitride of silicon such as silicon oxide, silicon nitride or silicon oxynitride, or insulating materials including metal oxynitride such as aluminum oxide or titanium nitride, may also be disposed between the fourth insulating layer106and the third conductive layer.

In the manufacturing process of the above display substrate, as the first orthographic projection of the photo spacer402on the base substrate101is located between the second orthographic projection of the first signal line on the base substrate101and the third orthographic projection of the second signal line on the base substrate101, that is, the first orthographic projection of the photo spacer402on the base substrate101does not exceed the range defined by the second orthographic projection of the first signal line on the base substrate101and the third orthographic projection of the second signal line on the base substrate101. Therefore, in the process of manufacturing the photo spacer402, positions of the first signal line and the second signal line may be taken as reference to precisely position a forming position of the photo spacer402.

For instance, in some embodiments, a distance from a center O of the first orthographic projection of the photo spacer402on the base substrate101to a central axis EM0of the second orthographic projection of the first signal line (e.g., the light-emitting control line EM) on the base substrate101is greater than a distance from the center O of the first orthographic projection to a central axis RST0of the third orthographic projection of the second signal line (e.g., the reset control line RST) on the base substrate101. At this point, the photo spacer402is closer to the second signal line relative to the first signal line and the second signal line. As the relative position of the pixel circuit and the plurality of openings in the pixel defining layer is determined, when the photo spacer402is closer to the second signal line, a distance between any point at the bottom of the photo spacer402contacting the pixel defining layer and side walls of upper surfaces of the plurality of openings401can be guaranteed to be greater than or equal to 5 μm, and a distance between the photo spacer402and the plurality of openings401is closer or basically the same.

At least one embodiment of the present disclosure provides a display device, which comprises any foregoing display substrates. The display device may be: any product or component with display function such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital album or a navigator.

At least one embodiment of the present disclosure provides a method for manufacturing a display substrate. As shown inFIG.6, the method comprises steps S101-S103.

S101: providing a base substrate.

For instance, as shown inFIG.7, the provided base substrate101may be various types of substrates such as a glass substrate or a silicon substrate. No limitation will be given here in the embodiment of the present disclosure.

For instance, a stack layer (not shown in the figure) of a barrier layer and a buffer layer may be formed on the base substrate101, so as to prevent impurities in the base substrate101from entering functional layers to be formed subsequently such as the pixel circuit structure.

For instance, the pixel circuit structure is formed on the stack layer of the barrier layer and the buffer layer and includes a pixel circuit for driving the display panel to display. As described above, the pixel circuit may be a 2T1C driving circuit, a 3T1C driving circuit, a 7T1C driving circuit, etc. The type and the forming method of the driving circuit are not limited in the embodiment of the present disclosure.

For instance,FIG.7is a schematic partial cross-sectional view of the display substrate in the manufacturing process. With reference toFIGS.4A-4EandFIG.7, forming pixel circuit structure includes forming a plurality of thin-film transistors, a storage capacitor, and the first electrode134aof the light-emitting element120on the stack layer of the barrier layer and the buffer layer. The manufacturing method of the pixel circuit structure will be described in detail below. For instance, the manufacturing method of the pixel circuit structure includes steps S11-S22.

S11: forming a semiconductor material layer on the base substrate, and performing a patterning process on the semiconductor material layer to form a semiconductor layer102as shown inFIG.4A. The semiconductor layer102includes active layers T1a-T7aand doped region patterns (namely corresponding to source regions and drain regions of the first to seventh transistors T1-T7) of the first to seventh transistors T1-T7in each subpixel region. Moreover, active layer patterns and the doped region patterns of the transistors in the same pixel region are integrally arranged.

It should be noted that the active layer may include an integrally formed low-temperature polysilicon layer, and a source region and a drain region therein may be subjected to a conductive treatment by using doping and the like, to realize the electrical connection between the structures. That is to say, the active semiconductor layer of the transistor of each subpixel is an overall pattern formed by p-type silicon, and the transistor in the same pixel region includes the doped region pattern (namely the source region and the drain region) and the active layer pattern, and the active layers of different transistors are spaced from each other by a doped structure.

S12: forming the first insulating layer103(for example, may be a transparent layer), e.g., a gate insulation layer, on the semiconductor layer102, and forming a plurality of first insulating layer through holes in the first insulating layer for connecting to a pattern of a subsequently formed third conductive layer203. For instance, corresponding first insulating layer through holes, for example, a through hole402, a through hole405, a through hole303, a through hole305and the like that run through the first insulating layer, are respectively formed in the first insulating layer at positions corresponding to the source region and the drain region in the semiconductor layer, that is, the first insulating layer through holes are respectively overlapped with the source region and the drain region in the semiconductor layer, so that the source region and the drain region can be electrically connected with structures such as a data line12in the third conductive layer, a first power line250, a first connecting electrode231, a second connecting electrode232, and a third connecting electrode233.

S13: forming a first conductive material layer on the first insulating layer, and performing a patterning process on the first conductive material layer, to form the first conductive layer201as shown inFIG.4A, namely form a scanning line210, a reset control line220and a light-emitting control line230which are insulated from each other and extended along the second direction. For instance, as for one row of pixel circuits, the reset control line220, the scanning line210and the light-emitting control line230correspondingly connected with the pixel circuits are sequentially arranged along the first direction.

For instance, the first conductive layer201also includes the gate electrodes T1g-T7gof the first to seventh transistors T1-T7. For instance, the gate electrode T6gof the sixth transistor T6and the reset control line220are an integral structure, namely a portion of the reset control line220is taken as the gate electrode T6gof the sixth transistor T6; the gate electrode T2gof the second transistor T2and the scanning line210are an integral structure, namely a portion of the scanning line210is taken as the gate electrode T2gof the second transistor T2; the gate electrode T4gof the fourth transistor T4and the gate electrode T5gof the fifth transistor T5are both an integral structure with the light-emitting control line230, namely a portion of the light-emitting control line230is taken as the gate electrode T4gof the fourth transistor T4and the gate electrode T5gof the fifth transistor T5; and the gate electrode T7gof the seventh transistor T7and the reset control line220corresponding to the next row of pixel circuits are an integral structure. For instance, both the sixth transistor T6and the third transistor T3are a double-gate structure. Two gate electrodes T6gof the sixth transistor T6are both a portion of the reset control line220. One gate electrode of the third transistor T3is a portion of the scanning line210, and the other gate electrode of the third transistor T3is a portion which is integrally connected with the scanning line210and protruded towards the reset control line220.

For instance, portions of the semiconductor layer102, that are overlapped with the first conductive layer201in a direction perpendicular to the base substrate, define the active layers (channel regions) T1a-T7aof the first to seventh transistors T1-T7.

For instance, in the D1direction, the gate electrode of the second transistor (e.g., the data write transistor) T2, the gate electrode of the third transistor (e.g., a threshold compensation transistor) T3, the gate electrode of the sixth transistor (e.g., the first reset transistor) T6, and the gate electrode of the seventh transistor (e.g., the second reset transistor) T7are all disposed at a first side of the gate electrode of the first transistor (e.g., the driving transistor) T1, and the gate electrode of the fourth transistor (e.g., the first light-emitting control transistor) T4and the gate electrode of the fifth transistor (e.g., the second light-emitting control transistor) T5are both disposed at a second side of the gate electrode of the first transistor T1. In a plane parallel to the base substrate, the first side of the gate electrode of the first transistor T1in the same pixel region may be an upper side of the gate electrode of the first transistor T1, and the second side of the gate electrode of the first transistor T1may be a lower side of the gate electrode of the first transistor T1. As for the lower side, for example, a side of the display substrate used for bonding an integrated chip (IC) is the lower side of the display substrate. The lower side of the gate electrode of the first transistor T1is a side of the gate electrode of the first transistor T1closer to the integrated chip. The upper side is an opposite side of the lower side, for example, is a side of the gate electrode of the first transistor T1farther away from the IC.

For instance, in the D2direction, both the gate electrode of the second transistor T2and the gate electrode of the fourth transistor T4are disposed on a third side of the gate electrode of the first transistor T1, and a first gate electrode (a gate electrode that is integral with the scanning line210) of the third transistor T3, the gate electrode of the fifth transistor T5, and the gate electrode of the seventh transistor T7are all disposed at a fourth side of the gate electrode of the first transistor T1. For instance, the third side and the fourth side of the gate electrode of the first transistor T1in the same pixel region (a region in which the pixel circuit is located) are two opposite sides of the gate electrode of the first transistor T1in the D2direction. For instance, the third side of the gate electrode of the first transistor T1in the same pixel region (the region in which the pixel circuit is located) may be the left side of the gate electrode of the first transistor T1, and the fourth side of the gate electrode of the first transistor T1may be the right side of the gate electrode of the first transistor T1. The left side and the right side are, for example, in the same pixel region (the region in which the pixel circuit is located); the data line is on the left side of the first power line250; and the first power line250is on the right side of the data line.

S14: as shown inFIG.4A, performing conduction treatment (e.g., doping treatment) on the semiconductor layer102by adoption of the first conductive layer201as a mask by self-aligned process, so that a portion of the semiconductor layer102, not covered by the first conductive layer201, are conducted, and then a portion of the semiconductor layer102, disposed on two sides of the active layer of the transistor, are conducted to respectively form the source regions or the drain regions of the first to seventh transistors T1-T7, namely the first electrodes (T1s-T7s) and the second electrodes (T1d-T2d) of the first to seventh transistors T1-T7.

S15: forming a second insulating layer104(for example, may be a transparent layer), e.g., a second gate insulation layer, on the first conductive layer201, and at least forming a second insulating layer through hole corresponding to the first insulating layer through hole in the second insulating layer. For instance, through holes at least running through the first insulating layer and the second insulating layer correspondingly at least include a through hole402, a through hole405, a through hole303, a through hole305, etc.

S16: forming a second conductive material layer on the second insulating layer104, and performing a patterning process on the second conductive material layer to form the second conductive layer202as shown inFIG.4B, namely form a shielding electrode221, a first capacitor electrode Ca, and the reset voltage line240extended along the first direction, which are insulated from each other.

For instance, the shielding electrode221is overlapped with the first electrode T2sof the second transistor T2in the direction perpendicular to the base substrate101, so as to protect a signal in the first electrode T2sof the second transistor T2from being interfered by other signals.

For instance, the first capacitor electrode Ca is at least partially overlapped with the gate electrode T1gof the first transistor T1in the direction perpendicular to the base substrate101. A through hole301is also formed in the first capacitor electrode Ca by the patterning process. The through hole301exposes at least one portion of the gate electrode T1gof the first transistor T1.

S17: forming a third insulating layer105on the second conductive layer202. The third insulating layer, for example, may be an interlayer insulating layer. A through hole that is connected with the subsequently formed third conductive layer is formed in the third insulating layer. At least a portion of the through holes, for example, a through hole402, a through hole405, a through hole303and a through hole305, correspond to the first insulating layer through holes and the second insulating layer through holes in position, and meanwhile, run through the first insulating layer, the second insulating layer and the third insulating layer.

S18: forming a third conductive material layer on the third insulating layer105, and performing a patterning process on the third conductive material layer to form the third conductive layer203as shown inFIG.4C, namely form the data line12, the first power line250, the first connecting electrode231, the second connecting electrode232, and the third connecting electrode233that are insulated from each other. The data line12and the first power line250are extended along the first direction D1.

For instance, as shown inFIG.4C, the data line12is overlapped with the first electrode T2sof the second transistor T2in the direction perpendicular to the base substrate101and is electrically connected with the first electrode T2sof the second transistor T2through the through hole305. The through hole305, for example, runs through the first insulating layer103, the second insulating layer104and the third insulating layer105.

For instance, as shown inFIG.4CandFIG.7, the first power line250is overlapped with the shielding electrode221in the direction perpendicular to the base substrate101and is electrically connected with the shielding electrode221through the through hole304. For instance, the through hole304runs through the third insulating layer105.

For instance, as shown inFIG.4C, the first power line250is electrically connected with the first capacitor electrode Ca in one corresponding column of subpixels through the through hole302and is electrically connected with the first electrode T4sof the fourth transistor T4through the through hole303. For instance, the through hole302runs through the third insulating layer105, and the through hole303runs through the first insulating layer103, the second insulating layer104and the third insulating layer105.

For instance, as shown inFIG.4CandFIG.7, one terminal of the first connecting electrode231is electrically connected with the gate electrode T1gof the first transistor T1, namely the second capacitor electrode Cb, through the through hole301in the first capacitor electrode Ca and the through hole401in the insulating layer, and the other terminal is electrically connected with the first electrode of the third transistor T3through the through hole402, so that the second capacitor electrode Cb is electrically connected with the first electrode T3sof the third transistor T3. For instance, the through hole401runs through the second insulating layer104and the third insulating layer105, and the through hole402runs through the first insulating layer103, the second insulating layer104and the third insulating layer105.

For instance, as shown inFIG.4C, one terminal of the second connecting electrode232is electrically connected with the reset voltage line through the through hole403, and the other terminal is electrically connected with the sixth transistor T6through the through hole404, so that the first electrode T6sof the sixth transistor T6can receive the first reset voltage Vinit1from the reset voltage line240. For instance, the through hole403runs through the third insulating layer105, and the through hole404runs through the first insulating layer103, the second insulating layer104and the third insulating layer105.

For instance, as shown inFIG.4CandFIG.7, the third connecting electrode233is electrically connected with the second electrode T5dof the fifth transistor T5through the through hole405, and is configured to electrically connect the second electrode T5dof the fifth transistor T5and the first electrode134of the light-emitting element. For instance, the through hole405runs through the first insulating layer103, the second insulating layer104and the third insulating layer105.

S19: forming a fourth insulating layer106on the third conductive layer203, and forming a through hole that is configured to be connected with a subsequently formed fourth conductive layer in the fourth insulating layer. In some embodiments, for example, the fourth insulating layer106includes a first planarization layer. In some other embodiments, for example, the fourth insulating layer106includes two layers of a passivation layer and a first planarization layer, and the through hole formed in the fourth insulating layer need to run through the two layers of the passivation layer and the first planarization layer. For instance, the first planarization layer is disposed on a side of the passivation layer away from the third conductive layer.

S20: forming a fourth conductive material layer on the fourth insulating layer106, and performing a patterning process on the fourth conductive material layer to form a fourth conductive layer204as shown inFIG.4D, namely form a second power line260, a third power line270and a fourth connecting electrode234. The second power line260and the third power line270are connected with each other and are insulated from the fourth connecting electrode234.

For instance, as shown inFIG.4D, a plurality of third power lines270are extended along the first direction D1and are respectively electrically connected with a plurality of first power lines250via through holes306in one-to-one correspondence. For instance, each third power line270and corresponding first power line250are overlapped with each other in the direction perpendicular to the base substrate101. For instance, the through hole306runs through the fourth insulating layer106.

For instance, as shown inFIG.4D, the fourth connecting electrode234and the third connecting electrode233are overlapped with each other in the direction perpendicular to the base substrate101, and the fourth connecting electrode234is electrically connected with the third connecting electrode233via a through hole307running through the fourth insulating layer106.

S21: for instance, as shown inFIG.7, the manufacturing method of the display substrate may further comprise forming a fifth insulating layer107on the fourth conductive layer204and forming a through hole for being connected with a subsequently formed fifth conductive layer in the fifth insulating layer107. For instance, the fifth insulating layer107may be a second planarization layer. The fifth insulating layer through hole, for example, is used for connecting the drain electrode of the first transistor and the first electrode of the light-emitting element. The fifth insulating layer through hole and the drain electrode of the first transistor may be overlapped and may also be not overlapped. When not overlapped, a connecting line may be additionally arranged in the third conductive layer for connection. The connection mode is relevant to a position and a shape of the subpixel arrangement structure, for example, the first electrode.

S22: forming a fifth conductive material layer on the fifth insulating layer107, and performing a patterning process on the fifth conductive material layer to form a fifth conductive layer205, namely form a plurality of first electrodes134(134aas shown in the figure) used for forming the light-emitting elements and insulated from each other.

For instance, each first electrode134includes a main portion141and a connecting portion142; the main portion141is mainly configured to drive the light-emitting layer to emit light; and the connecting portion142is mainly configured to be electrically connected with the pixel circuit.

For instance, as shown inFIG.7, the connecting portion142is electrically connected with the fourth connecting electrode234through a through hole308in the fifth insulating layer107. For instance, in a direction parallel to a plane of the base substrate101, the through hole308is farther away from the main portion141of the first electrode134, namely the opening401of the subpixel, compared with the through hole307, that is, an orthographic projection of the through hole308on the base substrate101is farther away from an orthographic projection of the opening401on the base substrate compared with an orthographic projection of the through hole307on the base substrate101.

For instance, as shown inFIG.7, the manufacturing method of the display substrate may further comprise: forming a pixel defining layer108on the fifth conductive layer205, forming the opening401in the pixel defining layer108corresponding to the main portion141of each first electrode134, at least forming the light-emitting layer136in the opening401, and forming the second electrode135on the light-emitting layer.

For instance, materials of the semiconductor material layer include but not limited to silica-base materials (amorphous silicon a-Si, polycrystalline silicon p-Si, etc.), metal oxide semiconductors (IGZO, ZnO, AZO, IZTO, etc.), and organic materials (hexathiophene, polythiophene, etc.).

For instance, materials of the first conductive material layer, the second conductive material layer, the third conductive material layer, the fourth conductive material layer, the fifth conductive material layer, and the second electrode may include Au, Ag, Cu, Al, Mo, Mg, W and alloy materials composed of the above metals; or transparent metal oxide conductive materials such as ITO, IZO, ZnO, AZO, etc.

For instance, the first insulating layer103, the second insulating layer104, the third insulating layer105, the fourth insulating layer106and the fifth insulating layer107are, for example, inorganic insulating layers, e.g., oxide, nitride or oxynitride of silicon such as silicon oxide, silicon nitride or silicon oxynitride, or insulating materials including metal oxynitride such as aluminum oxide or titanium nitride. For instance, a portion of the insulating layers, e.g., the first planarization layer and the second planarization, may also be an organic material such as polyimide, acrylate, epoxy resin or PMMA. No limitation will be given here in the embodiment of the present disclosure. For instance, the fourth insulating layer106and the fifth insulating layer107may include a planarization layer.

For instance, the above patterning process may adopt the conventional photolithography process, for example, including photoresist coating, exposure, development, drying, etching, etc.

S102: forming a pixel defining layer on the base substrate.

For instance, as shown inFIG.7, after the above pixel circuit structure is formed, a pixel defining layer403is formed by a patterning process. The pixel defining layer403includes a plurality of openings401, and each opening401exposes the first electrode134and is configured to form the light-emitting element120of one subpixel.

For instance, one patterning process includes a plurality of steps such as photoresist coating, exposure, development and etching. When the patterned material is a photoresist material, one patterning process may only include steps of exposure and development.

For instance, a material of the pixel defining layer403may be polyimide. As polyimide may be taken as a photoresist material, the pixel defining layer provided with the plurality of openings may be formed by coating a polyimide material layer on the pixel circuit structure and then performing exposure and development on the polyimide material layer.

S103: forming at least one photo spacer on a side of the pixel defining layer away from the base substrate.

For instance, the forming the at least one photo spacer includes forming a plurality of photo spacers arranged in an array. Each photo spacer has similar forming position.

For instance, a forming position of the photo spacer is positioned at first, and then the photo spacer is formed at this position, so that distances D between any point at the bottom of the formed photo spacer contacting the pixel defining layer and side walls of upper surfaces of the plurality of openings is greater than or equal to 5 μm.

For instance, the forming position of the photo spacer may be positioned by using a plurality of methods. For instance, in one example, the forming position of the photo spacer may be positioned through a position of the plurality of openings in the pixel defining layer. Thus, the photo spacer is formed between the plurality of openings, and the distances D between any point at the bottom of the formed photo spacer contacting the pixel defining layer and the side walls of the upper surfaces of the plurality of openings is greater than or equal to 5 μm.

For instance, in one example, the pixel circuit structure formed on the display substrate includes a first signal line and a second signal line which are parallel to each other. At this point, positions of the first signal line and the second signal line may be positioned, and then the forming position of the photo spacer is positioned by taking the position of the first signal line and the second signal line as reference, so the first orthographic projection of the formed photo spacer on the base substrate is located between a second orthographic projection of the first signal line on the base substrate and a third orthographic projection of the second signal line on the base substrate.

For instance, in the manufacturing process, the position of the first signal line and the second signal line may be scanned by adoption of an optical detection device, and subsequently, the forming position of the photo spacer is set by taking the position of the first signal line and the second signal line as reference, and then a position of a mask used for forming the photo spacer is set, so that the photo spacer formed by utilization of the mask is disposed at the above set position.

For instance, as described above, the first signal line may be the light-emitting control signal line230/EM, and the second signal line may be the reset signal line220/RST.

For instance, after positioning, a distance from a center of the first orthographic projection of the photo spacer on the base substrate to a central axis of the second orthographic projection of the first signal line on the base substrate is greater than a distance from the center of the first orthographic projection to a central axis of the third orthographic projection of the second signal line on the base substrate, namely the photo spacer is closer to the second signal line between the first signal line and the second signal line.

For instance, a material of the photo spacer may be polyimide. As polyimide may be taken as photoresist material, at this point, as shown inFIG.7, forming the photo spacer402includes: forming a polyimide material layer on a side of the pixel defining layer403away from the base substrate101, and forming the photo spacer402by performing exposure and development on the polyimide material layer via a mask. For instance, when a required height H of the photo spacer is 0.8 μm-1.5 μm, a forming thickness of the polyimide material layer is 0.8 μm-1.5 μm, e.g., 1 μm or 1.2 μm.

For instance, the material of the photo spacer may be the same with the material of the pixel defining layer. For instance, the photo spacer may be integrally formed with the pixel defining layer. For instance, the photo spacer and the pixel defining layer are formed by one patterning process via a halftone mask.

It should be noted that each subpixel includes a pixel circuit structure and a light-emitting element, and a portion of the light-emitting element disposed in an opening of the pixel defining layer is an actual light-emitting region. In the embodiment of the present disclosure, in the overlapping relationship between the photo spacer and the pixel circuit structure, for example, the positional relationship with the signal lines is described by taking the pixel circuit region which is a region as shown by the dotted frame inFIG.4Bas an example, and the positional relationship between the photo spacer and the first electrode of the subpixel or the opening of the pixel defining layer is described by taking a actual position and a coverage region of the first electrode or the opening of the pixel defining layer as an example.

For instance, as shown inFIG.4, a shape of the orthographic projection of the photo spacer402on the base substrate101is rectangle. A length L of the rectangle may be 20 μm-30 μm, e.g., 22 μm, 25 μm or 28 μm. A width D of the rectangle may be 10 μm-16 μm, e.g., 12 μm or 15 μm. For instance, in other embodiments, the shape of the first orthographic projection of the photo spacer402on the base substrate101may also be circle, ellipse, triangle or other polygons. The specific shape of the photo spacer402is not limited in the embodiment of the present disclosure.

For instance, as shown inFIG.7, after the photo spacer402is formed, the light-emitting layer136may be formed in the plurality of openings401of the pixel defining layer403through a mask420(such as an FMM) by methods such as inkjet printing or evaporation. The light-emitting layer136at least covers the opening of the pixel defining layer and may also cover a portion of a surface of the pixel defining layer away from the base substrate, to ensure that the light-emitting layer disposed in the opening is more uniform and more reliable. In the process of arranging the mask420, a setting distance between the photo spacer402and the mask420tends to be close. Due to the reasons such as gravity, the photo spacer420may contact a central portion of the mask420. At this point, the photo spacer402may have the function of supporting the mask420, so as to avoid the mask420from scratching the functional structures that have been formed on the display substrate.

As shown inFIG.8, after the light-emitting layer136is formed, a second electrode135is formed on the light-emitting layer136by methods such as sputtering. For instance, the second electrode135may be entirely formed on the display substrate in an entire surface manner. Subsequently, an encapsulation layer410is formed on the second electrode135to encapsulate and protect the display substrate.

For instance, the encapsulation layer410may include a plurality of encapsulation sublayers, e.g., stack layers of a plurality of inorganic insulating sublayers and organic insulating sublayers. For instance, a material of the inorganic encapsulation sublayer includes an inorganic material such as silicon oxide, silicon nitride or silicon oxynitride, and a material of the organic encapsulation sublayer includes an organic material such as resin or polyimide. Wherein, the inorganic insulating sublayer may be formed by methods such as deposition, and the organic encapsulation sublayer may be formed by methods such as coating.

For instance, other structures such as a transparent cover plate may also be covered on the display substrate. Other structures of the display substrate are not specifically limited in the embodiment of the present disclosure.

In the process of manufacturing the display substrate in the manufacturing method provided by the embodiment of the present disclosure, due to designs of a position, a shape, a size and the like of the photo spacer, the photo spacer can have full supporting function on the mask (such as the FMM) arranged thereon, so as to avoid the mask from scratching other functional structures that have been formed on the display substrate. Therefore, the display substrate obtained by utilization of the manufacturing method has better reliability.

The following statements should be noted:

(2) For the purpose of clarity only, in accompanying drawings for illustrating the embodiment(s) of the present disclosure, the thickness and size of a layer or a structure may be enlarged, that is, the accompanying drawings are not drawn according to the actual scale. However, it should understood that, in the case in which a component or element such as a layer, film, region, substrate or the like is referred to be “on” or “under” another component or element, it may be directly on or under the another component or element or a component or element is interposed therebetween.

(3) In case of no conflict, features in one embodiment or in different embodiments can be combined to obtain a new embodiment.

What are described above is related to the specific embodiments of the disclosure only and not limitative to the scope of the disclosure. The protection scope of the disclosure shall be based on the protection scope of the claims.