SEMICONDUCTOR PACKAGE DEVICE

Disclosed is a semiconductor package device comprising a lower redistribution substrate, a first semiconductor chip on the lower redistribution substrate, vertical structures on the lower redistribution substrate, and a first molding member on the lower redistribution substrate and on the first semiconductor chip and the vertical structures. The vertical structure includes a first post having a first diameter, a second post on the first post and having a second diameter, and a bonding pad on the second post opposite the first post and having a third diameter. The first, second, and third diameters are different from each other. The third diameter is greater than the second diameter.

CROSS-REFERENCE TO RELATED APPLICATION

This U.S. nonprovisional application claims priority under 35 U.S.C § 119 to Korean Patent Application No. 10-2021-0158914 filed on Nov. 17, 2021 in the Korean Intellectual Property Office, the disclosure of which is hereby incorporated by reference in its entirety.

BACKGROUND

The present inventive concepts relate to a semiconductor package device.

A semiconductor package is provided to implement an integrated circuit chip to qualify for use in electronic products. A semiconductor package is typically configured such that a semiconductor chip is mounted on a printed circuit board and bonding wires or bumps are used to electrically connect the semiconductor chip to the printed circuit board. With the development of electronics industry, various studies have been conducted to improve reliability and durability of semiconductor packages.

SUMMARY

Some embodiments of the present inventive concepts provide a semiconductor package device having the degree of freedom of wiring design and fine pitches.

According to some embodiments of the present inventive concepts, a semiconductor package device may comprise: a lower redistribution substrate; a first semiconductor chip on the lower redistribution substrate; a plurality of vertical structures on the lower redistribution substrate; and a first molding member on the lower redistribution substrate, the first molding member on the first semiconductor chip and the vertical structures. The vertical structure may include: a first post having a first diameter; a second post on the first post and having a second diameter; and a bonding pad on the second post opposite the first post and having a third diameter. The first, second, and third diameters may be different from each other. The third diameter may be greater than the second diameter.

According to some embodiments of the present inventive concepts, a semiconductor package device may comprise: a redistribution substrate; a semiconductor chip on the redistribution substrate; a plurality of vertical structures on the redistribution substrate; and a molding member on the redistribution substrate, the semiconductor chip, and the vertical structures. The vertical structure may include: a first post having a first diameter; a second post on the first post and having a second diameter; and a bonding pad on the second post opposite the first post and having a third diameter. The first, second, and third diameters may be different from each other. The molding member may be in contact with an edge portion of a bottom surface of the bonding pad.

According to some embodiments of the present inventive concepts, a semiconductor package device may comprise: a first semiconductor package; and a second semiconductor package on the first semiconductor package. The first semiconductor package may include: a redistribution substrate; a first semiconductor chip on the redistribution substrate, the first semiconductor chip including a chip pad on a surface of the first semiconductor chip, the surface facing the redistribution substrate; a plurality of vertical structures on the redistribution substrate and spaced apart from a lateral surface of the first semiconductor chip; a first molding member on a top surface of the first semiconductor chip, the lateral surface of the first semiconductor chip, and a top surface of each of the vertical structures; and a plurality of first connection terminals below the redistribution substrate. Each of the vertical structures may include a first post, a second post on the first post, and a bonding pad on the second post. Each of the first post, the second post, and the bonding pad may have a cylindrical shape. The second semiconductor package may include: a package substrate; a second semiconductor chip on the package substrate; a second molding member on the package substrate and the second semiconductor chip; a metal pad in a lower portion of the package substrate; and a second connection terminal between the bonding pad and the metal pad. A diameter of the second post may be about 5 μm to about 10 μm less than a diameter of the bonding pad. The vertical structures may be spaced apart from each other along a first direction parallel to a top surface of the redistribution substrate. The second posts may be spaced apart a first distance from each other along the first direction. The bonding pads may be spaced apart a second distance from each other along the first direction. The first distance may be less than the second distance.

DETAILED DESCRIPTION OF EMBODIMENTS

The following will now describe a semiconductor package device according to the present inventive concepts with reference to accompanying drawings.

FIG.1illustrates a cross-sectional view showing a semiconductor package device according to some embodiments of the present inventive concepts.FIG.2illustrates a plan view showing a first semiconductor package ofFIG.1.FIG.3illustrates an enlarged view showing section aa ofFIG.1.

Referring toFIG.1, a semiconductor package device1according to the present inventive concepts may include a first semiconductor package100and a second semiconductor package200on the first semiconductor package100. The semiconductor package device1may have a package-on-package structure.

The first semiconductor package100may include a lower redistribution substrate140, a first semiconductor chip120, a plurality of vertical structures110, a first molding member130, under-bump patterns150, and first connection terminals160.

The lower redistribution substrate140may include a first dielectric layer141and first redistribution patterns142in the first dielectric layer141. Although the first dielectric layer141is illustrated as a single layer, the first dielectric layer141may be formed of a plurality of dielectric layers. The first dielectric layer141may be formed of photo-imageable dielectric (PID). The first dielectric layer141may include, for example, a photosensitive polymer. The photosensitive polymer may include one or more of polyimide, polybenzoxazole, benzocyclobutene, and epoxy. The first redistribution patterns142may each include a first wire portion143and a first via portion144. The first wire portion143and the first via portion144may be integrally formed into a single unitary piece.

The first semiconductor chip120may be on the lower redistribution substrate140. The first semiconductor chip120may be, for example, a logic chip. The first semiconductor chip120may include first chip pads122electrically connected to the first redistribution patterns142. The first chip pad122may be in contact with the first via portion144. The first semiconductor chip120may be connected to the first redistribution patterns142without separate connection terminals (e.g., bumps or solder balls). While the first connection terminals160may be on a region that vertically overlap the first semiconductor chip120, the first connection terminals160may be on a region that does not vertically overlap the first semiconductor chip120. In this case, the first semiconductor package100ofFIG.1may be a fan-out semiconductor package formed in a chip-first process.

The vertical structures110may be on the lower redistribution substrate140while surrounding the first semiconductor chip120. Each of the vertical structures110may include a first post112, a second post114, and a bonding pad116.

Referring toFIGS.1and2, the first post112, the second post114, and the bonding pad116may each have a cylindrical shape. When viewed in plan, each of the first post112, the second post114, and the bonding pad116may have a circular shape or an almost circular shape. However, it should be understood that different shapes may be used; for example, each of the first post112, the second post114, and the bonding pad116may have a tetragonal pillar shape or any other polygonal pillar shape.

The first post112may include a seed pattern112aand a metal pattern112b.The seed pattern112amay be in contact with the first via portion144of an uppermost one of the first redistribution patterns142. The metal pattern112bmay be on the seed pattern112a.The seed pattern112aand the metal pattern112bmay include the same metallic material. For example, the seed pattern112aand the metal pattern112bmay include copper.

The second post114may be on the first post112. The second post114may extend in a vertical direction. The second post114may be in contact with a top surface of the first post112. The second post114may include the same metallic material as that of the first post112. For example, the second post114may include copper.

The bonding pad116may be on on the second post114. The bonding pad116may extend in a vertical direction. That is, the bonding pad116may be on a top surface or side of the second post114that is opposite the first post112. The bonding pad116may include a first metal layer117in contact with a top surface of the second post114and a second metal layer118in contact with a top surface of the first metal layer117. The first and second metal layers117and118may include different metallic materials from each other. For example, the first metal layer117may include nickel (Ni), and the second metal layer118may include gold (Au).

Referring toFIGS.1and3, the first post112, the second post114, and the bonding pad116may respectively have a first diameter W1, a second diameter W2, and a third diameter W3. The first, second, and third diameters W1, W2, and W3may be different from one another.

The first diameter W1may be greater than the second diameter W2and the third diameter W3. The second diameter W2may be less than the third diameter W3.

For example, the third diameter W3may range from about 50 μm to about 60 μm, and the second diameter W2may range from about 40 μm to about 55 μm. A difference between the third diameter W3and the second diameter W2may be substantially the same as a thickness of the seed pattern112a.For example, when the thickness of the seed pattern112ais in a range of about 5 μm to about 10 μm, the difference between the third diameter W3and the second diameter W2may be in a range of about 5 μm to about 10 μm.

The vertical structures110may be spaced apart from each other. The second posts114may be spaced apart at a first distance A1from each other along a first direction D1parallel to a top surface of the lower redistribution substrate140and along a second direction D2that intersects the first direction D1and is parallel to the top surface of the lower redistribution substrate140. The bonding pads116may be spaced apart at a second distance A2from each other along the first direction D1and the second direction D2.

The first distance A1may be greater the second distance A2. For example, the first distance A1may range from about 65 μm to about 90 μm, and the second distance A2may range from about 60 μm to about 80 μm.

The first post112, the second post114, the first metal layer117, and the second metal layer118may respectively have vertical thicknesses of heights, including a first height H1, a second height H2, a third height H3, and a fourth height H4that are measured in a third direction D3perpendicular to the top surface of the lower redistribution substrate140.

The first height H1may be less than the second height H2. The first height H1may range from about 30 μm to about 40 μm, and the second height H2may range from about 70 μm to about 80 μm. The third height H3may range from about 5 μm to about 8 μm. The fourth height H4may range from about 0.1 μm to about 0.7 μm.

According to the present inventive concepts, as the first post112has a diameter greater than that of the second post114, there may be an increase in the degree of freedom in designing the second post114and the first redistribution pattern142. For example, the second post114may not vertically overlap the first redistribution patterns142in contact with the first post112, and may be at any location on the first post112. In particular, the second post114may be on an arbitrary position on the top surface of the first post112, and thus there may be an increase in the degree of freedom of wiring. For example, the second post114may be offset from a center of the top surface of the first post112. In some embodiments, the second post114is offset from the center of the top surface of the first post112in a direction away from the semiconductor chip120.

Referring back toFIG.1, the first molding member130may be on the lower redistribution substrate140. The first molding member130may be on top and lateral surfaces of the first semiconductor chip120, lateral surfaces of the vertical structures110, and the top surface of the lower redistribution substrate140. The first molding member130may include a dielectric material. The first molding member130may include a thermosetting resin such as epoxy resins, a thermoplastic resin such as polyimide, or a resin (e.g., Ajinomoto build-up film (ABF), a flame retardant 4 (FR-4), bismaleimide triazine (BT), epoxy molding compound (EMC)) including a reinforcement member such as inorganic fillers. The first molding member130may include, for example, an Ajinomoto build-up film (ABF).

The first molding member130may have a pad opening, and the pad opening may expose a top surface of the second metal layer118.

The first molding member130may be on a lateral surface of the first post112, a portion of the top surface of the first post112, a lateral surface of the second post114, top and lateral surfaces of the bonding pad116, and an edge portion of a bottom surface of the bonding pad116.

The under-bump patterns150may be on a bottom surface of the first dielectric layer141and may be connected to the first redistribution patterns142. The under-bump patterns150may include, for example, copper.

The first connection terminals160may be below the under-bump patterns150. The first connection terminals160may be solders or bumps. The first connection terminals160may be electrically connected through the under-bump patterns150to the first redistribution patterns142.

The second semiconductor package200may be on the first molding member130. The second semiconductor package200may include a package substrate210, a second semiconductor chip220, and a second molding member230. The second molding member230may include, for example, an epoxy molding compound (EMC). The package substrate210may be a printed circuit board. The package substrate210may include metal pads211aand211bon opposite surfaces thereof.

The second semiconductor chip220may be a memory chip, such as DRAM or NAND Flash. The second semiconductor chip220may be of the same type as or different type from the first semiconductor chip120. The second semiconductor chip220may include a second chip pad222on one surface that is wire-bonded to the metal pad211bof the package substrate210.

One or more second connection terminals240may be between the first semiconductor package100and the second semiconductor package200. The second connection terminal240may be in contact with the metal pad211aand the bonding pad116. The first semiconductor package100and the second semiconductor package200may be electrically connected to each other through the second connection terminal240.

FIGS.4to13illustrate cross-sectional views showing a method of fabricating a semiconductor package device according to some embodiments of the present inventive concepts.

Referring toFIG.4, a carrier500and an adhesion layer400may be provided. The adhesion layer400may include, for example, a polyimide tape.

A seed layer CFS may be attached to the adhesion layer400. The seed layer CFS may be, for example, a copper foil. The seed layer CFS may have a thickness of about 5 μm to about 10 μm.

Referring toFIG.5, a first photomask pattern PM1may be formed on the seed layer CFS. The first photomask pattern PM1may include a plurality of openings. The first photomask pattern PM1may be formed by coating, exposing, and developing a photoresist layer.

Referring toFIG.6, an electroplating process may be performed in which the seed layer CFS is used as an electrode to from a metal pattern112bin the opening ofFIG.5. After the metal pattern112bis formed, the first photomask pattern PM1may be removed.

Referring toFIG.7, a second photomask pattern PM2may be formed to partially expose a top surface of the metal pattern112b.The second photomask pattern PM2may include an opening that defines a space in which are formed a second post114and a bonding pad116which will be discussed below. The second photomask pattern PM2may be formed by a method substantially the same as that used for forming the first photomask pattern PM1.

Referring toFIG.8, an electroplating process may be performed in which the seed layer CFS is used as an electrode to form a second post114in the opening ofFIG.7. The second post114may be formed to have a top surface lower than that of the second photomask pattern PM2. The second post114may be formed by a method substantially the same as that used for forming the first post112.

Referring toFIG.9, an electroplating process may be performed in which the seed layer CFS is used as an electrode to form a bonding pad116on the second post114.

A first metal layer117may be formed on the second post114, and then a second metal layer118may be formed on the first metal layer117.

The bonding pad116may be adjusted to have a top surface at a level substantially the same as that of the top surface of the second photomask pattern PM2. According to some embodiments, the top surface of the bonding pad116may be located at a level lower or higher than that of the top surface of the second photomask pattern PM2. After the bonding pad116is formed, the second photomask pattern PM2may be removed.

Referring toFIG.10, the bonding pad116may be used as an etching mask to perform an etching process. The etching process may remove portions of the seed layer CFS (e.g., copper foil) that are not vertically overlapped the metal patterns112b.The seed layer CFS may be partially etched to form a seed pattern112a.The seed pattern112aand the metal pattern112bmay constitute a first post112.

The etching process may be, for example, selective wet etching. The etching process may be performed to etch a lateral surface of the second post114. Therefore, a second diameter W2, or a diameter of the second post114, may become less than a third diameter W3, or a diameter of the bonding pad116.

According to the present inventive concepts, when the seed layer CFS, or copper foil, is partially removed, the bonding pad116may be used as an etching mask without additionally forming a separate photomask pattern as an etching mask, with the result that it may be possible to reduce processing steps. In addition, because the lateral surface of the second post114is etched during the etching process, it may be possible to form the second post114having a small diameter. As a result, a semiconductor package device may be achieved to include fine-pitched vertical structures.

Referring toFIG.11, a first semiconductor chip120may be attached to the adhesion layer400. The first semiconductor chip120may be adhered to allow its first chip pad122to face the adhesion layer400.

Referring toFIG.12, a first molding member130may be formed on the adhesion layer400. The first molding member130may be on (e.g., may cover) the first semiconductor chip120and the vertical structures110. The first molding member130may be on (e.g., may cover) a lateral surface and a portion of a top surface of the first post112, a lateral surface of the second post114, and a top surface, a lateral surface, and a portion of a bottom surface of the bonding pad116. After the first molding member130is formed, the adhesion layer400and the carrier500may be removed.

Referring toFIG.13, a lower redistribution substrate140may be formed on an active surface of the first semiconductor chip120. The lower redistribution substrate140may include a first dielectric layer141and first redistribution patterns142in the first dielectric layer141. The first dielectric layer141may have a structure in which a plurality of photo-imageable dielectric layers are stacked. The photo-imageable dielectric layers may be formed by a coating process such as spin coating or slit coating, a photo-patterning process, and a curing process. The first redistribution patterns142may be formed by, for example, an electroplating process and a patterning process. A first wire portion143and a first via portion144may be integrally formed into a single unitary piece.

Under-bump patterns150may be formed below the first dielectric layer141. The under-bump patterns150may be formed by, for example, an electroplating process and a patterning process. First connection terminals160may be formed below the under-bump patterns150. A laser drilling process or other etching process may be performed to form a pad opening that exposes an uppermost surface of the bonding pad116, or a top surface of the second metal layer118. Through the processes discussed above, a first semiconductor package100may be formed.

Referring back toFIG.1, a second semiconductor package200may be attached to the first semiconductor package100. For example, a second connection terminal240may contact the top surface of the bonding pad116, and an annealing process may be performed. As a result, a semiconductor package device1may be fabricated.

FIG.14illustrates a cross-sectional view showing a semiconductor package device according to some embodiments of the present inventive concepts. There will be omission of explanation repetitive to that disclosed inFIGS.1to3, except the following description.

Referring toFIG.14, the first semiconductor package100may further include an upper redistribution substrate300. The upper redistribution substrate300may be on the first molding member130. The upper redistribution substrate300may include a second dielectric layer301and second redistribution patterns302. The second redistribution patterns302may each include a second wire portion303and a second via portion304, which second wire and via portions303and304are integrally connected into a single unitary piece.

The pad opening may be filled with a metal via MV, and the metal via MV may be in contact with the top surface of the bonding pad116and with the second via portion304of a lowermost one of the second redistribution patterns302. Therefore, the first semiconductor package100and the second semiconductor package200may be electrically connected to each other.

An upper connection pattern250may be on an upper portion of the second dielectric layer301. The upper connection pattern250may be connected to the second redistribution patterns302. The second connection terminal240may be in contact with the upper connection pattern250.

A semiconductor package device according to the present inventive concepts may include a first post and a second post on the first post. The first post may have a diameter greater than that of the second post, and the second post may be on an arbitrary position on a top surface of the first post, which may result in an increase in the degree of freedom of wiring design.

In addition, in fabricating the semiconductor package device according to the present inventive concepts, a seed layer may be first formed, the first and second posts and a bonding pad may be formed, and then an etching process may be performed to from a vertical structure. In this step, the bonding pad may be used as an etching mask, and in this case it may be possible to reduce processing steps. Moreover, a lateral surface of the second post may be etched during the etching process, and thus the second post may be formed to have a small diameter. As a result, the semiconductor package device may be achieved to include fine-pitched vertical structures.

The present inventive concepts are not intended to be limited by the above-described embodiments and the accompanying drawings, but are intended to be limited by the appended claims. Accordingly, various forms of substitution, modification, and alteration may be made by those skilled in the art without departing from the scope defined by the following claims.