Semiconductor package device and method of manufacturing the same

A semiconductor package device includes a first interconnection structure, a non-silicon interposer and a first die. The first interconnection structure has a first pitch. The non-silicon interposer surrounds the first interconnection structure. The non-silicon interposer includes a second interconnection structure having a second pitch. The second pitch is larger than the first pitch. The first die is above the first interconnection structure and is electrically connected to the first interconnection structure.

BACKGROUND

1. Technical Field

The present disclosure relates generally to a semiconductor package device and a method of manufacturing the same. More particularly, the present disclosure relates to a semiconductor package device including a stacking structure and a method of manufacturing the same.

2. Description of the Related Art

In comparable three-dimensional semiconductor packages, there is a bridge in an interposer (e.g., a through silicon via (TSV) interposer) to provide electrical interconnection (e.g., via a redistribution layer (RDL)) between two dies (such as an application-specific integrated circuit (ASIC) and a high bandwidth memory (HBM)). However, fine pitch (e.g., smaller than 1 micrometer (μm)) interconnection exists in a small portion of the interposer (e.g., the area between the two dies). Most of the regions of the interposer are designed for interconnection with relatively great pitch (e.g., greater than 1 μm). However, it may take great cost to use the TSV interposer to provide electrical interconnection between the two dies.

SUMMARY

In one or more embodiments, a semiconductor package device includes a first interconnection structure, a non-silicon interposer and a first die. The first interconnection structure has a first pitch. The non-silicon interposer surrounds the first interconnection structure. The non-silicon interposer includes a second interconnection structure having a second pitch. The second pitch is larger than the first pitch. The first die is above the first interconnection structure and is electrically connected to the first interconnection structure.

In one or more embodiments, a semiconductor system includes a fan-out semiconductor package device. The fan-out semiconductor package device includes a first interconnection structure having a first pitch, a non-silicon interposer surrounding the first interconnection structure and having a second interconnection structure with a second pitch, a first die electrically connected to the fan-out semiconductor package, and a second die electrically connected to the first die through the fan-out semiconductor package.

In one or more embodiments, a method of manufacturing a semiconductor package device includes providing a carrier and a release film, disposing a first interconnection structure and a silicon base on the carrier, disposing a non-silicon interposer over the first interconnection structure, disposing a second interconnection structure over the first interconnection structure and the non-silicon interposer, connecting a first die to the second interconnection structure, and connecting a second die to the second interconnection structure.

DETAILED DESCRIPTION

FIG. 1illustrates a cross-sectional view of a semiconductor package device1in accordance with some embodiments of the present disclosure. The semiconductor package device1includes a substrate10, electronic components11a,11band an interconnection component12.

The substrate10may be a flexible substrate or a rigid substrate, depending upon the specific application. In some embodiments, the substrate10includes a plurality of electrical traces disposed therein. In some embodiments, an external contact layer is also formed or disposed on the substrate10. In some embodiments, the external contact layer includes a ball grid array (BGA). In other embodiments, the external contact layer includes an array such as, but not limited to, a land grid array (LGA) or an array of pins (PGA). In some embodiments, the external contact layer includes solder balls10b, which are used and are composed of lead or are lead free (e.g., including such materials as alloys of gold and tin solder or silver and tin solder).

Electronic components11a,11bare disposed over the substrate10. Each of the electronic components11a,11bincludes a plurality of semiconductor devices, such as, but not limited to, transistors, capacitors and resistors interconnected together by a die interconnection structure into functional circuits to thereby form an integrated circuit. As will be understood to those skilled in the art, the device side of the semiconductor die includes an active portion including integrated circuitry and interconnections. The electronic components11a,11bmay be any suitable integrated circuit device including, but not limited to, a microprocessor (e.g., single or multi-core), a memory device, a chipset, a graphics device, or an application-specific integrated circuit (ASIC) according to several different embodiments. In some embodiments, the electronic component11ais a high bandwidth memory (HBM) and the electronic component11bis an ASIC.

Each of the electronic components11a,11bincludes a plurality of electrical contacts11p1,11p2to provide electrical connections between the electronic components11a,11band other electronic components. In some embodiments, the electrical contacts11p1,11p2and the active sides of the electronic components11a,11bare covered or encapsulated by an underfill11f. In some embodiments, the underfill11fincludes an epoxy resin, a molding compound (e.g., an epoxy molding compound or other molding compound), a polyimide, a phenolic compound or material, a material including a silicone dispersed therein, or a combination thereof.

The interconnection component12is disposed between the electronic components11a,11band the substrate10to provide electrical connections therebetween. In some embodiments, the interconnection component12is a fan-out structure. The interconnection component12includes a first interconnection layer14, a second interconnection layer13, a passivation layer15and electrical contacts16.

The first interconnection layer14includes electrical contacts (such as micro-pads) to which the electronic components11a,11bare electrically connected. In some embodiments, the first interconnection layer14is a dielectric layer or a non-silicon interposer (e.g., an organic interposer) and includes a plurality of conductive connections14m1,14m2embedded therein. In some embodiments, the conductive connection14m2is referred to as a second interconnection structure, and the conductive connection14m1is referred to as a second interconnection structure or a third interconnection structure. The first interconnection layer14covers or encapsulates the second interconnection layer13. For example, the first interconnection layer14is disposed on and adjacent to the second interconnection layer13.

The second interconnection layer13(e.g., also referred to as a first interconnection structure) includes a plurality of conductive connections (or a redistribution layer (RDL))13mtherein. A portion of the conductive connections14m1of the first interconnection layer14is electrically connected to the conductive connections13mof the second interconnection layer13. For example, the conductive connections14m1that are electrically connected to the electronic components11a,11bare electrically connected to the conductive connections13mof the second interconnection layer13. The second interconnection layer13provides interconnections between the electronic components11aand11b. For example, the second interconnection layer13can serve as a bridge between the electronic components11aand11b.

In some embodiments, the pitch (e.g., the line width and line space (L/S)) of the conductive connection13mof the second interconnection layer13is less than that of the conductive connections14m1,14m2of the first interconnection layer14. For example, the conductive connection13mof the second interconnection layer13is a fine-pitch interconnection or fine line (e.g., less than about 1 micrometer (μm)), and the conductive connections14m1,14m2of the first interconnection layer14are coarse-pitch interconnections or coarse lines (e.g., greater than about 1 μm). In some embodiments, a thickness D1of the second interconnection layer13is in a range from about 10 μm to about 20 μm. In some embodiments, a density of the second interconnection layer13is larger than a density of the conductive connections14m1,14m2. In some embodiments, a top surface of the conductive connection14m1is substantially coplanar with a top surface of the conductive connection14m2. In some embodiments, a diameter of the conductive connection14m1is less than a diameter of the conductive connection14m2.

In comparable semiconductor package devices, an interposer (e.g., a through silicon via (TSV) interposer) is used to provide electrical interconnections between two dies. However, fine-pitch interconnection may be used in a small portion of the interposer (e.g., the area between two dies). Most of the regions of the interposer are designed for interconnection with relatively great pitch. Therefore, it may take great cost to use the TSV interposer to provide electrical interconnections. In accordance with some embodiments, the fine-pitch interconnection (e.g., the conductive connection13mof the second interconnection layer13) is provided at a predetermined area (e.g., the area between the electronic components11aand11b), and the remaining area is provided with coarse-pitch interconnections (e.g., the conductive connections14m1,14m2). For example, the fine-pitch interconnection structure is embedded within the coarse-pitch interconnection structure. Therefore, it is unnecessary to use a TSV interposer to provide interconnections between two dies, which would reduce the thickness of the semiconductor package device and the manufacturing cost.

The first interconnection layer14and the second interconnection layer13are disposed on the passivation layer15. The passivation layer15encapsulates or covers a portion of the first interconnection layer14and the second interconnection layer13and exposes conductive contacts of the first interconnection layer14and the second interconnection layer13. In some embodiments, the passivation layer15includes silicon oxide, silicon nitride, gallium oxide, aluminum oxide, scandium oxide, zirconium oxide, lanthanum oxide or hafnium oxide.

A conductive layer16u(e.g., under bump metallurgy (UBM)) contacts the exposed portions of the conductive contacts of the first interconnection layer14and the second interconnection layer13. The electrical contacts16electrically contact the conductive layer16u. The first interconnection layer14and the second interconnection layer13are electrically connected to the substrate10through electrical contacts16(such as Controlled Collapse Chip Connection (C4) pads). In some embodiments, the electrical contacts16can be covered or encapsulated by an underfill16f.

FIG. 2Aillustrates a cross-sectional view of a semiconductor package device2A in accordance with some embodiments of the present disclosure. The semiconductor package device2A includes a substrate20, electronic components21a,21band an interconnection component22.

The substrate20may be a flexible substrate or a rigid substrate, depending upon the specific application. In some embodiments, the substrate20includes a plurality of electrical traces disposed therein. In some embodiments, an external contact layer is also formed or disposed on the substrate20. In some embodiments, the external contact layer includes a BGA. In other embodiments, the external contact layer includes an array, such as, but not limited to, an LGA or a PGA. In some embodiments, the external contact layer includes solder balls20b, which are used and are composed of lead or are lead free (e.g., including such materials as alloys of gold and tin solder or silver and tin solder).

Electronic components21a,21bare disposed over the substrate20. Each of the electronic components21a,21bincludes a plurality of semiconductor devices, such as, but not limited to, transistors, capacitors and resistors interconnected together by a die interconnection structure into functional circuits to thereby form an integrated circuit. As will be understood to those skilled in the art, the device side of the semiconductor die includes an active portion including integrated circuitry and interconnections. The electronic components21a,21bmay be any suitable integrated circuit device including, but not limited to, a microprocessor (e.g., single or multi-core), a memory device, a chipset, a graphics device, or an ASIC according to several different embodiments. In some embodiments, the electronic component21ais an HBM and the electronic component21bis an ASIC.

Each of the electronic components21a,21bincludes a plurality of electrical contacts21p1,21p2to provide electrical connections between the electronic components21a,21band other electronic components. In some embodiments, the electronic components21a,21bare covered or encapsulated by a package body24b. In some embodiments, the package body24bincludes an epoxy resin including filler therein, a molding compound (e.g., an epoxy molding compound or other molding compound), a polyimide, a phenolic compound or material, a material including a silicone dispersed therein, or a combination thereof.

The interconnection component22is disposed between the electronic components21a,21band the substrate20to provide electrical connections therebetween. In some embodiments, the interconnection component22is a fan-out structure. The interconnection component22includes an interconnection layer23, a package body24a, a passivation layer25, a dielectric layer27and electrical contacts26.

The package body24aincludes a plurality of conductive connections24m1,24m2embedded therein. In some embodiments, the conductive connection24m2is referred to as a second interconnection structure, and the conductive connection24m1is referred to as a third interconnection structure. The package body24acovers or encapsulates the interconnection layer23. For example, the package body24ais disposed on and adjacent to the interconnection layer23. The dielectric layer27is disposed on the package body24aand includes electrical contacts (such as micro-pads) to which the electronic components21a,21bare electrically connected.

The interconnection layer23(e.g., also referred to as a first interconnection structure) is disposed on a silicon layer23s. The interconnection layer23includes a plurality of conductive connections23mtherein. A portion of the conductive connections24m1is electrically connected to the conductive connection23mof the interconnection layer23. For example, the conductive connections24m1that are electrically connected to the electronic components21a,21bare electrically connected to the conductive connection23mof the interconnection layer23. The interconnection layer23provides interconnections between the electronic components21aand21b. For example, the interconnection layer23can serve as a bridge between the electronic components21aand21b.

In some embodiments, the pitch (e.g., the L/S) of the conductive connection23mof the interconnection layer23is less than that of the conductive connections24m1,24m2embedded within the package body24a. For example, the conductive connection23mof the interconnection layer23is a fine-pitch interconnection or fine line (e.g., less than about 1 μm), and the conductive connections24m1,24m2within the package body24aare coarse-pitch interconnections or coarse lines (e.g., greater than about 1 μm).

In comparable semiconductor package devices, an interposer (e.g., a TSV interposer) is used to provide electrical interconnections between two dies. However, fine-pitch interconnection is used in a small portion of the interposer (e.g., the area between the two dies). Most of the regions of the interposer are designed for interconnection with relatively great pitch. Therefore, it may take great cost to use the TSV interposer to provide electrical interconnections. In accordance with some embodiments, the fine-pitch interconnection (e.g., the conductive connection23mof the interconnection layer23) is provided at a predetermined area (e.g., the area between the electronic components21aand21b), and the remaining area is provided with coarse-pitch interconnection (e.g., the conductive connections24m1,24m2). For example, the fine-pitch interconnection structure is embedded within the coarse-pitch interconnection structure. Therefore, it is unnecessary to use a TSV interposer to provide interconnections between the two dies, which would reduce the thickness of the semiconductor package device and the manufacturing cost.

The package body24aand the silicon layer23sare disposed on the passivation layer25. The passivation layer25encapsulates or covers a portion of the package body24aand the silicon layer23sand exposes the conductive connections24m2and the silicon layer23s. In some embodiments, the passivation layer25includes silicon oxide, silicon nitride, gallium oxide, aluminum oxide, scandium oxide, zirconium oxide, lanthanum oxide or hafnium oxide.

A conductive layer26u(e.g., UBM) contacts the exposed portions of the conductive connections24m2and the silicon layer23s. The electrical contacts26electrically contact the conductive layer26u. The conductive connections24m2and the silicon layer23sare electrically connected to the substrate20through electrical contacts26(such as C4 pads). In some embodiments, the electrical contacts26can be covered or encapsulated by an underfill26f.

FIG. 2Billustrates a cross-sectional view of a semiconductor package device2B in accordance with some embodiments of the present disclosure. The semiconductor package device2B is similar to the semiconductor package device2A except that inFIG. 2B, the interconnection layer23is replaced by a plurality of metal pillars29.

The metal pillars29are electrically connected to the electronic components21a,21bthrough conductive contacts within the dielectric layer27. The metal pillars29provide interconnections between the electronic components21aand21b. For example, the conductive pillars29can serve as a bridge between the electronic components21aand21b. In some embodiments, the pitch (e.g., the L/S) of the metal pillar29is less than the conductive connection24m2embedded within the package body24a. In some embodiments, the metal pillars29include copper studs.

FIGS. 3A, 3B, 3C, 3D, 3E, 3F, 3G and 3Hillustrate cross-sectional views of a semiconductor structure fabricated at various stages, in accordance with some embodiments of the present disclosure. Various figures have been simplified for a better understanding of the aspects of the present disclosure.

Referring toFIG. 3A, a carrier30′ is provided. In some embodiments, the carrier30′ may be a glass carrier or any other type of suitable carrier. An interconnection layer33is disposed over the carrier30′. In some embodiments, the interconnection layer33is attached to the carrier30′ through an adhesive layer (or a release film)30aon the carrier30′. In some embodiments, the interconnection layer33does not completely cover the carrier30′. For example, the interconnection layer33covers a portion of the carrier30′ and exposes another portion of the carrier30′.

The interconnection layer33includes a plurality of conductive connections therein. In some embodiments, the conductive connections of the interconnection layer33are fine-pitch interconnections or fine lines (e.g., less than about 1 μm). The interconnection layer33includes a silicon layer33sdisposed thereon. In some embodiments, a metal layer33mis disposed between the interconnection layer33and the carrier30′. The metal layer33mmay include, for example, titanium (Ti), copper (Cu), tin-silver (SnAg) or other suitable metals or alloys.

Referring toFIG. 3B, the silicon layer33sis removed from the interconnection layer33. In some embodiments, the silicon layer33scan be removed by etching or by other suitable processes.

A dielectric layer34is formed or disposed on the interconnection layer33and the portion of the carrier30′ exposed from the interconnection layer33. The dielectric layer34includes a plurality of openings34h1,34h2to expose a portion of the interconnection layer33and a portion of the carrier30′ (or adhesive layer30a). For example, the opening34h1exposes the conductive connections of the interconnection layer33. In some embodiments, the dielectric layer34is formed by bumping or by other suitable processes.

Referring toFIG. 3C, a seed layer34sis formed or disposed on the dielectric layer34and within the openings34h1,34h2. For example, the seed layer34sis formed or disposed on a top surface of the dielectric layer34and sidewalls of each opening34h1,34h2. In some embodiments, the seed layer34sis formed of Ti, Cu or other suitable metals or alloys.

Referring toFIG. 3D, conductive materials are formed or disposed within the openings34h1,34h2to form conductive connections (or conductive pillars)34m1,34m2. The conductive connection34m1electrically connects to the conductive connection of the interconnection layer33that is exposed from the dielectric layer34. In some embodiments, the conductive connections34m1,34m2are formed by electroplating or by other suitable techniques. In some embodiments, the conductive connections34m1,34m2are coarse-pitch interconnections or coarse lines (e.g., less than about 1 μm).

Referring toFIG. 3E, the seed layer34sis removed from the top surface of the dielectric layer34. In some embodiments, the seed layer34sis removed by etching or by other suitable processes.

Referring toFIG. 3F, electronic components31a,31bare formed or disposed on the dielectric layer34and electrically connected to the conductive connections34m1,34m2. Each of the electronic components31a,31bincludes a plurality of electrical contacts31p1,31p2to provide electrical connections between the electronic components31a,31band conductive connections34m1,34m2. The electronic components31a,31bmay be any suitable integrated circuit device including, but not limited to, a microprocessor (e.g., single or multi-core), a memory device, a chipset, a graphics device, or an ASIC according to several different embodiments. In some embodiments, the electronic component31ais an HBM and the electronic component31bis an ASIC.

An underfill31fis formed or disposed to cover or encapsulate the active side of the electronic components31a,31band electrical contacts31p1,31p2, and then a reflow process may be carried out. A package body38is then formed or disposed to cover or encapsulate the electronic components31a,31b. In some embodiments, the package body38includes an epoxy resin including fillers, a molding compound (e.g., an epoxy molding compound or other molding compound), a polyimide, a phenolic compound or material, a material including a silicone dispersed therein, or a combination thereof.

Referring toFIG. 3G, a portion of the package body38is removed so that a backside of each electronic component31a,31bis exposed from the package body38. In some embodiments, the package body38can be removed by grinding, etching or by other suitable processes. The carrier30′ is then removed from the dielectric layer34and the interconnection layer33to expose the conductive connections34m2and the interconnection layer33.

Referring toFIG. 3H, a passivation layer35is formed or disposed to cover a portion of the dielectric layer34and the interconnection layer33and to expose the conductive connections34m2and the conductive connections of the interconnection layer33.

A conductive layer36u(e.g., UBM) is formed or disposed to contact the exposed portion of the conductive connections34m2and the conductive connections of the interconnection layer33. Electrical contacts36(e.g., a C4 pad) are formed or disposed on the conductive layer36u. The electrical contact36is then formed or disposed on a substrate30to form the semiconductor package device1as shown inFIG. 1.

FIGS. 4A, 4B, 4C, 4D, 4E and 4Fillustrate cross-sectional views of a semiconductor structure fabricated at various stages, in accordance with some embodiments of the present disclosure. Various figures have been simplified for a better understanding of the aspects of the present disclosure.

Referring toFIG. 4A, a carrier40′ is provided. In some embodiments, the carrier40′ may be a glass carrier or any other suitable carrier. An interconnection layer43is disposed over the carrier40′. In some embodiments, the interconnection layer43is attached to the carrier40′ through an adhesive layer (or release film)40aon the carrier40′. In some embodiments, the interconnection layer43does not completely cover the carrier40′. For example, the interconnection layer43covers a portion of the carrier40′ and exposes another portion of the carrier40′.

The interconnection layer43includes a plurality of conductive connections43mtherein. In some embodiments, the conductive connections43mof the interconnection layer43are fine-pitch interconnections or fine lines (e.g., less than about 1 μm). In some embodiments, a silicon layer43sis disposed between the interconnection layer43and the carrier40′.

Conductive connections (or conductive pillars)44m1,44m2are formed or disposed on the carrier40′ and the interconnection layer43. The conductive connection44m1electrically connects to the conductive connection43mof the interconnection layer43.

Referring toFIG. 4B, a package body44ais formed or disposed to cover or encapsulate the interconnection layer43and conductive connections44m1,44m2. In some embodiments, the package body44aincludes an epoxy resin including fillers, a molding compound (e.g., an epoxy molding compound or other molding compound), a polyimide, a phenolic compound or material, a material including a silicone dispersed therein, or a combination thereof.

A portion of the package body44ais then removed to expose the conductive connections44m1,44m2. For example, after a portion of the package body44ais removed, the conductive connections44m1,44m2are substantially coplanar with or higher than a top surface of the package body44a.

Referring toFIG. 4C, a dielectric layer47is formed or disposed on the interconnection layer43and the package body44a. The dielectric layer includes electrical contacts (such as an RDL or micro-pads) to electrically connect the conductive connections44m1,44m2to electronic components formed during the subsequent operations.

Referring toFIG. 4D, electronic components41a,41bare formed or disposed on the dielectric layer47and electrically connected to the electrical contacts of the dielectric layer47. Each of the electronic components41a,41bincludes a plurality of electrical contacts41p1,41p2to provide electrical connections between the electronic components41a,41band the electrical contacts of the dielectric layer47. The electronic components41a,41bmay be any suitable integrated circuit device including, but not limited to, a microprocessor (e.g., single or multi-core), a memory device, a chipset, a graphics device, or an ASIC according to several different embodiments. In some embodiments, the electronic component41ais an HBM and the electronic component41bis an ASIC.

A package body44bis formed or disposed on the package body44ato cover or encapsulate the electronic components41a,41b. In some embodiments, the package body44bincludes an epoxy resin including fillers, a molding compound (e.g., an epoxy molding compound or other molding compound), a polyimide, a phenolic compound or material, a material including a silicone dispersed therein, or a combination thereof. Then a reflow process may be carried out.

Referring toFIG. 4E, the carrier40′ is then removed from the package body44aand the silicon layer43sto expose the conductive connections44m2and the silicon layer43s.

Referring toFIG. 4F, a passivation layer45is formed or disposed to cover a portion of the package body44aand the silicon layer43sand to expose a portion of the conductive connections44m2and silicon layer43s. Conductive layer46u(e.g., UBM) is formed or disposed to contact the exposed portion of the conductive connections44m2and the silicon layer43s. Electrical contacts46(e.g., a C4 pad) are formed or disposed on the conductive layer46u. The electrical contact46is then formed or disposed on a substrate40to form the semiconductor package device2A as shown inFIG. 2A.

In the description of some embodiments, a component provided “on” or “over” another component can encompass cases where the former component is directly on (e.g., in physical contact with) the latter component, as well as cases where one or more intervening components are located between the former component and the latter component.