System for predictive processor component suspension and method thereof

An instruction cycle is determined from instructions stored in a cache, where the instruction cycle represents the sequence of instructions predicted to be executed by the processing device that are resident in the cache. The duration of the instruction cycle is estimated and one or more components of the processing device that are not expected to be used during the instruction cycle may be suspended for a portion or all of the duration. The components may be suspended by, for example, clock gating or by isolating the components from one or more power domains.

FIELD OF THE DISCLOSURE

The present disclosure is related generally to power saving in processing devices more specifically to suspending specific components of processing devices.

BACKGROUND

Pipelined processing often provides improved performance due to the ability to process multiple instructions at various components of a pipeline simultaneously. Performance further may be enhanced using branch prediction techniques whereby a branch prediction unit of a processing device predicts whether a branch presented by an upcoming change of flow (COF) instruction is taken. If the branch is predicted to be taken, the instructions following the branch may be preloaded into the instruction cache of the processing device, and also may be executed in whole or in part before the COF instruction is resolved. However, in the event of a misprediction, the pipeline typically is flushed and any results of the execution of the instructions associated with the misprediction are discarded. Thus, misprediction often results in considerable power consumption by the processor as well as wasted processing cycles.

Regardless of the effectiveness of a processor's branch prediction, it will be appreciated that the fetching and execution of instructions by the pipelined processing device may not involve or require the use of one or more components of the processing device. To illustrate, the execution of an instruction representing an integer operation typically does not require the use of a floating point unit (FPU) of the processing device. The processing device therefore often unnecessarily consumes power while maintaining certain components in an enabled status even though an  upcoming instruction stream does not require the use of the certain components. Accordingly, a system and method to reduce the power consumption of a processing device and reduce the penalty associated with mispredicted branches would be advantageous.

DETAILED DESCRIPTION OF THE DRAWINGS

FIGS. 1-5illustrate exemplary systems and techniques for dynamically suspending processor components so as to reduce the power consumption of a processing device. In at least one embodiment, an instruction cycle is determined from the instructions stored in a cache, where the instruction cycle represents the sequence of instructions predicted to be executed by the processing device that are resident in the cache. The duration of the instruction cycle is estimated and one or more components of the processing device that are not expected to be used during the instruction cycle may be suspended for a portion or all of the duration. The components may be suspended by, for example, clock gating or by isolating the components from one or more power domains.

Referring now toFIG. 1, an exemplary processing system100is illustrated in accordance with at least one embodiment of the present disclosure. The processing system100includes a processing device, such as processor102, coupled to one or more peripheral components, such as, for example, a master bus interface unit104, a memory controller (MC)106, and a system memory108. The processor102includes an instruction pipeline110having, for example, an instruction cache112, a prefetch module114, a decode module116, an address calculation module118, and an execution module120. The execution module120may include, for example, an integer unit122, a floating point unit (FPU)124, a multimedia extension (MMX) unit126, and the like. The processor102further may include a suspend controller130, a decode cache132, a level two (L2) cache134, and a bus controller (BC)136as an interface between the components of the processor102and the peripheral components.

Based on branch prediction information or other prefetch information, the prefetch module114fetches identified instructions from the instruction cache112or from system memory108and provides the instructions to the decode module116. The decode module116, in one embodiment, partially or fully decodes the prefetched instructions and stores the instructions in the decode cache132and/or the L2 cache134. Instructions in the decode cache132and/or instructions directly fetched from the instruction cache112then may be provided to the address calculation module118and the execution module120for execution in accordance with the program flow.

As discussed in greater detail with reference toFIG. 2, the decode module116, in one embodiment, determines certain program flow characteristics associated with an instruction provided by the prefetch module114and provides representations of these program flow characteristics to the decode cache132for storage with the corresponding decoded instruction. The program flow characteristics may include, but are not limited to, a change of flow characteristic (i.e., whether the instruction may result in a branch), an indication of those processor components expected to be used to execute the instruction or that are expected to be used as a result of the execution of the instruction, as well as branch prediction characteristics if the instruction is a COF instruction, such as whether the branch is predicted to be taken, the number of times the instruction is expected to be taken before the prediction is  complemented, and a number of times the given COF instruction has been resolved correctly before the complement prediction is realized.

Based on the instructions in the decode cache132and the associated program flow characteristics, the suspend controller130, in one embodiment, may estimate a duration before an instruction not resident in the decode cache132is expected to be requested. The suspend controller130may identify those components of the processor102that are expected to be unused during the estimated duration and then suspend one or more of the identified components for a portion or all of the duration so as to reduce the power consumed by the processor102during the duration. Similarly, the suspend controller130may identify one or more peripheral components expected to be unused during the duration and suspend one or more of these peripheral components for some or all of the duration. As discussed below, the additional power consumption involved in shutting down and restarting processor components or peripheral components may be considered when determining whether to suspend a particular component.

In at least one embodiment, the one or more processor components are suspended by isolating the one or more processor components from their corresponding power domains by shutting down the corresponding power domains. To illustrate, the prefetch module114may be associated with a power domain140, the integer unit122may be associated with a power domain142, the FPU124may be associated with a power domain144, the MMX unit126may be associated with a power domain146, the L2 cache134may be associated with a power domain148, and the system memory108may be associated with a power domain150. The suspend controller130therefore may disconnect one or more of the components114,122,124,126,134from the corresponding power domains140-148by, for example, providing an asserted suspend signal to one or more switch units160-168interposed between the components114,122,124,126,134and the power supply line(s) of the power domains140-148. Likewise, a deasserted suspend signal may be supplied to reconnect a component to the corresponding power domain. To illustrate, in response to a determination that the MMX unit126is expected to be unused for a particular instruction cycle, the suspend controller130may provide an asserted suspend signal to the switch unit166to disconnect the MMX unit126from the power domain146.  As the instruction cycle comes to a conclusion, the suspend controller130may provide a deasserted suspend signal to the switch unit166to reconnect the MMX unit126to the power domain146. Similarly, the suspend controller130may provide an asserted signal to the switch unit170via, for example, the BC136, MBIU104and the MC106to disconnect the system memory108from the power domain150in response to a determination that the system memory108is expected to be unused. The switch units160-170may comprise, any of a variety of suitable switching mechanisms, such as, for example, a transistor.

AlthoughFIG. 1illustrates a one-to-one correspondence between power domains and processor components for ease of illustration, it will be appreciated that multiple components may be associated with one power domain and/or multiple power domains may be associated with one component. In those instances wherein it is expected that all of the components associated with a particular power domain will be unused during a particular instruction cycle, the components may be suspended by isolating the power domain from its power source. Alternately, processor components and peripheral components may be suspended using other techniques, such as clock gating, without departing from the spirit or the scope of the present disclosure.

Referring now toFIG. 2, an exemplary implementation of the decode module116, decode cache132and suspend controller130is illustrated in accordance with at least one embodiment of the present disclosure. In one embodiment, the decode module116makes use of a program flow criteria table202to determine program flow criteria associated with instructions that the decode module116stores in the decode cache132. In the illustrated example, the table202includes a plurality of entries for at least a subset of the instruction types compatible with the processor102. Each entry may have a prefix/opcode field204to identify the particular instruction type and a one or more fields to indicate whether a corresponding processor or peripheral component is expected to be used during, or as a result of, the execution of an instruction having the corresponding instruction type. For example, the fields could include a memory field206, an integer field208, an FPU field210, and an MMX field212to indicate if an instruction having a particular instruction type is expected to use system memory108, integer unit124, FPU124, or MMX unit126,  respectively. In addition, each entry may include a COF field213to indicate whether the instruction type is a potential COF instruction.

Upon reciept of an instruction from the prefetch module114, the decode module116decodes the instruction to the appropriate extent and uses an identifier, such as the instruction's opcode or prefix, to identify the corresponding instruction-type entry in the table202. Using the values in the fields of the entry of the tabel202, the decode module116populates an entry of the decode cache132with the at least partially decoced instruction (stored in field214) and the appropriate program flow information. The program flow fields of the decode cache132may include: a linear instruction pointer (LIP) field216to provide an index; a COF field218to indicate whether the instruction is a COF instruction and fields218-226to indicate whether the instruction is expected to use the system memory108, integer unit124, FPU124, or MMX unit126, respectively. The entries of the decode cache132further may include: a predicted field228to indicate whether a COF instruction is predicted to be taken; a prediction count field230to indicate the number of times the COF instruction is predicted to be taken before the prediction is complemented; a prediction index field232to indicate the number of times the COF instruction has been resolved correctly by the execution module120before the compliment prediction is realized; and a target field234to indicate the target of a COF instruction. The decode module116may determine the appropriate value for each of these fields using information from the table202as well as branch prediction information provided by the branch prediction logic associated with, for example, the prefetch module114.

The suspend controller130, in one embodiment, analyzes the decode cache132to identify one or more instruction cycles, each of which represents a sequence of instructions, resident in the decode cache132, that is expected to be executed in turn by the execution module120, where the termination of the instruction cycle includes the request for an instruction not resident in the decode cache132. Note that the sequence of instructions may include multiple occurrences of one or more instructions should the decode cache132include instructions that form a loop within the decode cache132. To illustrate using the example ofFIG. 2, an exemplary instruction cycle starting at LIP1would include: {LIP1,2,3,4,5,6,7,2,3,4,5,6,7,2,3,4,5,6,7,8,9,10}. It will be appreciated that the sequence of instructions at LIP2-7is repeated three times due to: the value ‘1’ in the COF field218and the prediction field228which indicate that the instruction at LIP7is a COF instruction and is predicted to be taken; the value ‘2’ in the target field234which indicates that the instruction will branch to the instruction at LIP2; and the value ‘2’ in the prediction count field230indicating that the branch to the instruction at LIP2will repeat twice.

After identifying the expected instruction cycle(s), the suspend controller may determine the duration of processing time expected to be taken if the processor102does actually execute instructions as predicted in an instruction cycle. In one embodiment, the duration is determined on the basis of clock cycles. The suspend controller130may arrive at the total number of clock cycles for the instruction cycle using, for example, an average number of clock cycles per instruction. To illustrate, for a predetermined average of, for example, 2.4 clock cycles per instruction, the suspend module130could determine that an instruction cycle having a sequence of thirty instructions would take 72 clock cycles (i.e., 2.4 clock cycles/instruction×30 instructions). Alternatively, the suspend controller130could determine the number of clock cycles used by the processor102to execute each of the instructions of the instruction cycle based on their instruction types to arrive at the total number of clock cycles for the instruction cycle.

The suspend controller130may identify those components that are expected to be unused during the execution of the instruction cycle using, for example, the fields220-226of the entrys of the decode cache132corresponding to the instructions in the instruction cycle. To illustrate, the instruction at LIP2has a value of ‘1’ in fields220and224, indicating that the system memory108and the FPU124is used to execute the instruction, whereas none of the instructions in the exemplary instruction cycle provided above have a value of ‘1’ in the fields222or226, indicating that neither the integer unit122nor the MMX unit126are expected to be used during the execution of the instructions of the exemplary instruction cycle. Based on the expected duration of the instruction cycle and the components expected to be unused during the execution of the instruction cycle, the suspend controller130may suspend the appropriate processor components and peripheral components by providing, for example, asserted suspend signals to the appropriate switching units (FIG. 1).

Referring now toFIG. 3, an exemplary method300to identify and suspend processor and peripheral components is illustrated in accordance with at least one embodiment of the present disclosure. The method300initates at step302, wherein the duration of an identified instruction cycle in the decode cache132is determined. As noted above, the duration may be represented by a number of clock cycles expected to be used during an execution of the sequence of instructions of the instruction cycle.

At step304, the suspend controller130identifies one or more components that may be suspended for part or all of the predicted duration. However, it will be appreciated that there may be power and clock cycles wasted in shutting down and then restarting certain components. For example, certain components may require initialization upon start up that may requires tens, hundreds or thousands of clock cycles and more than neglible power. Accordingly, at step306the suspend controller130makes a determination of whether there is a power savings advantage to suspending a particular component in view of the power and time costs of suspending the particular component. This evaluation may take into consideration the power saved while the component is suspended and the power consumed to shut down and then restart the component. For example, if an instruction cycle is predicted to be 100 clock cycles long and a particular component can be shut down for 90 of those cycles (assuming a 10 cycle reinitialization period) at a power savings of 0.001 milliwatt (mW) per cycle, or a total power savings of 0.1 mW for the instruction cycle, the suspend controller130may elect to forgo suspending the component if the shut down power cost is close to or more than 0.1 mW.

In another embodiment, the relative value of suspending a component may be determined based a comparison of the expected duration with one or more thresholds. For example, if the duration is less than a certain threshold (e.g., 100 clock cycles), the suspend controller may elect to forgo suspending the component. Alternatively, the type of suspend operation utilzed by the suspend controller130may be determined based on a comparison of the predicted comparison to one or more thresholds. To illustrate, if the duration is less than a first threshold (e.g., 50 clock cycles), no suspend operation is perfomed. If the duration is greater than the first threshold but less than a second theshold (e.g., 200 clock cycles), a clock-gating  suspend operation may be performed. If the duration is greater than the second threshold, a suspend operation that isolates the component from its power domain may be performed. By having multiple tiers of suspend operations, the power savings/shutdown cost balance may be tailored to the particular instruction cycle based on its expected duration. It will be appreciated that the thresholds may be set relative to the specific component of the processing device to be suspended. For example, if a simple component, such as a multiplexer or adder is to be suspended, the clock-gating threshold may be set relatively low (e.g., a couple of clock cycles), whereas suspending a more complex component, such as a FPU, is to be suspended, the clock-gating threshold may be set relatively high (e.g., hundreds or thousands of clock cycles).

If it is determined to be advantageous to suspend the component for at least a portion of the duration, the suspend controller130suspends the component for the identified portion of the duration at step308. At the execution of the identified portion of the duration concludes, the suspend controller130reinitializes and/or restarts the component unless the component is identified as being unecessary for the next instruction cycle, in which case the suspend controller may maintain the component in suspended state. If multiple components are identified as suspendable, the suspend controller130may repeat steps306and308for each identified component at step310.

Referring now toFIG. 4, an exemplary method400is illustrated. Method400initates at step402wherein a plurality of instructions are received. One or more components of a processor that are expected to be unused during an execution of a sequence of the instructions from the plurality of instructions are identified at step404. At step406, one or more of the identified components are suspending during an execution of at least a portion of the sequence of instructions by the processor.

Referring now toFIG. 5, an exemplary method500is illustrated. Method500initates at step502wherein a plurality of decoded instructions are stored in a cache. One or more components of a processor that are expected to be unused during an execution of a sequence of the instructions from the plurality of instructions are identified at step504. At step506, a duration before an instruction not in the sequence of instructions is requested for execution by the processor is estimated. At  step508, at least one of the one or more identified one or more components of the processor is suspended, based on the estimated duration, during an execution of at least a portion of the sequence of instructions.