Clock gating cell with low power and integrated circuit including the same

In an integrated circuit including a clock gating cell based on a set-reset (SR) latch, the clock gating cell includes a first 2-input logic gate configured to receive a clock input and a first signal, and generate a second signal, a first inverter configured to receive the second signal, and generate a clock output, and a 4-input logic gate including a 4-input keeping logic gate configured to generate the SR latch by being cross-coupled to the first 2-input logic gate and keep a level of the first signal.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based on and claims priority under 35 U.S.C. § 119 to Korean Patent Applications No. 10-2020-0042978, filed on Apr. 8, 2020, and No. 10-2020-0135523, filed on Oct. 19, 2020, in the Korean Intellectual Property Office, the disclosures of which are incorporated by reference herein in their entirety.

BACKGROUND

The inventive concepts relate to a clock gating cell, and more particularly, to a clock gating cell having low power and an integrated circuit including the clock gating cell.

An integrated circuit configured to process a digital signal may operate in synchronization with a clock signal. For example, an integrated circuit may include a digital circuit configured to generate an output signal by processing an input signal in response to a rising edge and/or a falling edge of a clock signal, and when an edge of the clock signal does not occur, an operation of the digital circuit may stop. Clock gating may refer to stopping or resuming the operation of the digital circuit by selectively providing a clock signal, and by performing the clock gating, power consumption by the digital circuit may be reduced.

The integrated circuit may include a clock gating circuit, that is, a clock gating cell that selectively outputs a clock signal in response to a control signal. The clock gating cell may be required to stop and resume supply of a clock signal to reduce or prevent malfunction of a digital circuit which receives the clock signal, and at the same time, may also be required to have high efficiency, for example, a reduced area and low power consumption.

SUMMARY

Some example embodiments of the inventive concepts provide a clock gating cell configured to perform clock gating with a reduced area and lower power consumption and an integrated circuit including the clock gating cell.

According to some example embodiments of the inventive concepts, in an integrated circuit including a clock gating cell based on a set-reset (SR) latch, the clock gating cell includes a first 2-input logic gate configured to receive a clock input and a first signal, and generate a second signal, a first inverter configured to receive the second signal, and generate a clock output, and a 4-input logic gate including a 4-input keeping logic gate configured to generate the SR latch by being cross-coupled to the first 2-input logic gate and keep a level of the first signal, a second 2-input logic gate configured to receive the clock input and an inverted enable input, and generate the first signal, and a first transistor connected to a ground node, the first transistor configured to receive the second signal, and generate a discharge path shared by the 4-input keeping logic gate and the second 2-input logic gate.

According to some example embodiments of the inventive concepts, a clock gating cell based on the SR latch includes a first NAND gate configured to receive a first signal and a clock input and generate a second signal, a first inverter configured to receive the second signal and generate a clock output; and an OR-AND-INVERTER (OAI) gate configured to provide a second NAND gate, the second NAND gate configured to generate the first signal, and generate the SR latch by being cross-coupled to the first NAND gate, wherein the OAI gate includes an input logic gate configured to generate the first signal based on an inverted enable input and the clock input, an input keeping logic gate configured to keep a level of the first signal based on the first signal, the second signal, the clock input, and an inverted first signal, and a first n-channel Field Effect Transistor (NFET) connected between a first node and a ground node, the first NFET configured to generate a discharge path, and the first node being shared by the input keeping logic gate and the input logic gate.

According to some example embodiments of the inventive concepts, a clock gating cell based on the SR latch includes a first NAND gate configured to receive a first signal and a clock input, and generate a second signal, a first inverter configured to receive the second signal, and generate a clock output, and an OR-AND-INVERTER (OAI) gate configured to provide a second NAND gate, the second NAND gate configured to generate the first signal, and generate the SR latch by being cross-coupled to the first NAND gate, wherein the OAI gate includes an input logic gate configured to generate the first signal based on an inverted enable input and the clock input, and an input keeping logic gate configured to keep a level of the first signal based on the first signal, the second signal, the clock input, and an inverted first signal, wherein the input keeping logic gate includes a second inverter configured to receive the first signal, and generate the inverted first signal by using the second signal.

DETAILED DESCRIPTION

In the present specification, logic ‘1’ may correspond to a high voltage, for example, a power voltage VDD or a voltage close to the positive supply voltage, and may be referred to as a high level or an active state, while logic ‘0’ may correspond to a ground potential or a voltage close to the ground potential, and may be referred to as a low level or an inactive state. In addition, in the present specification, the ground node may refer to a node to which the ground potential (or a negative supply voltage) is applied. In the specification, transistors may have an arbitrary structure providing complementary transistors (for example, an n-channel transistor and a p-channel transistor), and as non-limited examples, may be implemented as a Planar Field Effect Transistor (PFET), a Fin Field Effect Transistor (FinFET), a Gate All Around Field Effect (GAAFET), a Vertical Field Effect Transistor (VFET), and the like.

FIGS. 1A and 1Bare diagrams of examples of clock gating cells10aand10baccording to example embodiments of the inventive concepts. In some example embodiments, the clock gating cells10aand10bmay be included in an integrated circuit manufactured according to a semiconductor process, and may also be referred to as a clock gating circuit or an integrated clock gating cell.

Referring toFIG. 1A, the clock gating cell10amay receive a clock input C_IN and an inverted enable input /E_IN, and may generate a clock output C_OUT. According to the inverted enable input /E_IN, the clock output C_OUT may vibrate with the clock input C_IN or may be kept at a constant voltage level. For example, the clock gating cell10amay be in an enable state in response to the inverted enable input /E_IN of a first level, and may generate the clock output C_OUT vibrating according to the clock input C_IN in the enable state. In addition, the clock gating cell10amay be in a disable state in response to the inverted enable input /E_IN at a second level, and may generate the clock output C_OUT at a constant level (for example, logic ‘1’ or logic ‘0’) in the disable state. In the present specification, it may be defined that the clock gating cell10ain the enable state supplies the clock output C_OUT and the clock gating cell10ain the disable state stops supply of the clock output C_OUT.

To reduce or prevent malfunction of a digital circuit receiving the clock output C_OUT, the clock gating cell10amay stop or resume supply of the clock output C_OUT in synchronization with the clock input C_IN. In some example embodiments, the clock gating cell10amay stop or resume supply of the clock output C_OUT in response to a rising edge of the clock input C_IN, and may supply the clock output C_OUT to a digital circuit that operates in response to a positive edge of the clock output C_OUT, for example, a positive edge triggered flip-flop. In addition, the clock gating cell10amay stop or resume providing the clock output C_OUT in response to a falling edge of the clock input C_IN, and may provide the clock output C_OUT to a digital circuit that operates in response to a falling edge of the clock output C_OUT, for example, a negative edge triggered flip-flop. The clock gating cell10amay include a set-reset (SR) latch structure, and may latch the inverted enable input /E_IN according to the clock input C_IN. As shown inFIG. 1A, the clock gating cell10amay include a first 2-input logic gate G11a, a 4-input logic gate12a, and/or an inverter G14a.

The first 2-input logic gate G11amay receive the clock input C_IN and a first signal S1, and may generate a second signal S2by performing a logical operation on the clock input C_IN and the first signal S1. The first 2-input logic gate G11amay form (or generate) the SR latch by being cross-coupled with a 4-input keeping logic gate G12a, which is provided by the 4-input logic gate12a, through a first node ND11and a second node ND21. The first node ND11may be defined as a node by which the first signal S1is generated or output, and the second node ND21may be defined as a node by which the second signal S2is generated or output. In some example embodiments, the first 2-input logic gate G11aand/or the 4-input keeping logic gate G12amay be implemented as NAND gates and/or NOR gates. The second signal S2generated by the first 2-input logic gate G11amay be provided to the inverter G14a, and the inverter G14amay generate the clock output C_OUT by inverting the second signal S2.

The 4-input logic gate12amay receive the inverted enable input /E_IN, the clock input C_IN, the second signal S2, and/or an internal signal INT, and may generate the first signal S1by performing a logical operation according to the inverted enable input /E_IN, the clock input C_IN, the second input S2, and/or the internal signal INT. The internal signal INT may be a signal generated by an internal node of the first 2-input logic gate G11a. For example, the internal signal INT may be a signal generated by inverting the first signal S1by the first 2-input logic gate G11a. The 4-input keeping logic gate G12amay form (or generate) or block a charge path or a discharge path to keep a level of the first signal S1.

AlthoughFIG. 1Ashows that the 4-input logic gate12aincludes the 4-input keeping logic gate G12aand a second 2-input logic gate G13a, an equivalent circuit of the 4-input logic gate12a, and the 4-input logic gate12amay provide the same functions as the 4-input keeping logic gate G12aand the second 2-input logic gate G13awhich are connected to each other as shown inFIG. 1Aand receive input signals. For example, in the 4-input logic gate12a, the 4-input keeping logic gate G12aand the second 2-input logic gate G13amay share at least one component, for example, at least one transistor, and may be not separated from each other. In addition, according to some example embodiments, the logic gates may receive different numbers of inputs, and accordingly, may be differently referred.

In some example embodiments, the 4-input keeping logic gate G12amay be a NAND gate, the second 2-input logic gate G13amay be an OR gate, and accordingly, the 4-input logic gate12amay be an OR-AND-INVERTER (OAI) gate. In addition, in some example embodiments, the 4-input keeping logic gate G12amay be a NOR gate, the second 2-input logic gate G13amay be an AND gate, and accordingly, the 4-input logic gate12amay be an OAI gate.

As shown inFIG. 1A, a circuit that vibrates according to vibration of the clock input C_IN in the disable state (for example, an inverter configured to generate an inverted clock input) may be omitted from the clock gating cell10a, and accordingly, the clock gating cell10amay have reduced power consumption in the disable state. Through a configuration of the clock gating cell10aaccording to the inventive concepts, the number of transistors receiving the clock input C_IN may be reduced, and due to a reduced input capacitance of the clock input C_IN, not only power consumption by the clock input C_IN but also delay of the clock input C_IN may be reduced.

The 4-input logic gate12aaccording to an example embodiment may include a shared transistor STR. The shared transistor STR may be connected to a third node ND31to which the 4-input keeping logic gate G12aand the second 2-input logic gate G13aare connected. The shared transistor STR may receive the second signal S2from the first 2-input logic gate G11a, and may be controlled by the second signal S2. The shared transistor STR may form (or generate) or block a discharge path between the third node ND31and the ground node, which is shared by the 4-input keeping logic gate G12aand the second 2-input logic gate G13a, in response to the second signal S2. For example, the shared transistor STR may form (or generate) or block the discharge path by activating or deactivating pull-down of the 4-input keeping logic gate G12aand the second 2-input logic gate G13a. Accordingly, in the clock gating cell10a, as the discharge path is formed through one sharing transistor STR, power consumption may be reduced, and dynamic power consumption may be reduced by reducing the number of transistors. Detailed example embodiments ofFIG. 1Awill be described in detail with reference toFIGS. 2 through 5.

Referring toFIG. 1B, the clock gating cell10bmay include a first 2-input logic gate G11b, a 3-input logic gate12b, and an inverter G14b. Hereinafter, descriptions that are the same as those of the clock gating cell10ainFIG. 1Aare omitted. The 3-input logic gate12bmay include a 3-input keeping logic gate G12b, a second 2-input logic gate G13b, and/or a third 2-input logic gate G16b. The 3-input logic gate12bmay receive the inverted enable input /E_IN, the clock input C_IN, and/or the second signal, and may generate the first signal S1by performing a logical operation according to the inverted enable input /E_IN, the clock input C_IN, and/or the second signal S2. The 3-input keeping logic gate G12bmay form (or generate) or block a charge path or a discharge path to keep the level of the first signal S1. The third 2-input logic gate G16bmay receive the first signal S1and/or the second signal S2and generate a third signal S3, and may provide the third signal S3to the 3-input keeping logic gate G12b. As an example embodiment, the third 2-input logic gate G16bmay generate the third signal S3, which is inverted from the first signal S1, by using the second signal S2. The clock gating cell10baccording to the inventive concepts may reduce power consumption by inverting the first signal S1by using the second signal S2instead of a power voltage.

AlthoughFIG. 1Bshows that the 3-input logic gate12bincludes the 3-input keeping logic gate G12b, the second 2-input logic G13b, and/or the third 2-input logic gate G16b,FIG. 1Bshows an equivalent circuit of the 3-input logic gate12b, and/or the 3-input logic gate12bmay provide the same functions as the 3-input keeping logic gate G12b, the second 2-input logic gate G13b, and/or the third 2-input logic gate G16bthat are connected to one another as shown inFIG. 1Band receive the input signals. For example, in the 3-input logic gate12b, the 3-input keeping logic gate G12b, the second two-input logic gate G13b, and/or the third 2-input logic gate G16bmay share at least one component, for example, at least one transistor, and may be not separated from one another.

As shown inFIG. 1B, a circuit that vibrates according to vibration of the clock input C_IN in the disable state (for example, an inverter configured to generate an inverted clock input) may be omitted from the clock gating cell10b, and accordingly, the clock gating cell10bmay have reduced power consumption in the disable state. Through a configuration of the clock gating cell10baccording to the inventive concepts, the number of transistors receiving the clock input C_IN may be reduced, and due to a reduced input capacitance of the clock input C_IN, not only power consumption by the clock input C_IN but also delay of the clock input C_IN may be reduced.

In some example embodiments, characteristics of the configurations of the clock gating cell10ainFIG. 1Aand the clock gating cell10binFIG. 1Bmay be implemented to be merged with each other. As an example embodiment, a clock gating cell may include the shared transistor STR shown inFIG. 1Aand the third 2-input logic gate G16bshown inFIG. 1B.

FIG. 2is a circuit diagram of examples of the clock gating cell10ashown inFIG. 1A. Hereinafter, among descriptions ofFIG. 2, descriptions that are the same as those ofFIG. 1Aare omitted.

Referring toFIG. 2, a clock gating cell20amay include a first NAND gate G21a, an OAI gate22a, an inverter G24a, and/or a NOR gate G25a. The first NAND gate G21amay correspond to the first 2-input logic gate G11ashown inFIG. 1A, and the OAI gate22amay correspond to the 4-input logic gate12ashown inFIG. 1A. The OAI gate22amay include a 4-input keeping logic gate G22aand/or a second two-input logic gate G23a.

The OAI gate22amay include a first n-channel Field Effect Transistor (NFET) N21athrough a fourth NFET N24aand/or a first p-channel Field Effect Transistor (PFET) P21athrough a fourth PFET P24a, which receive the inverted enable input /E_IN, the clock input C_IN, the second signal S2, and/or an inverted first signal /S1. The first NFET N21ashown inFIG. 2may correspond to the shared transistor STR shown inFIG. 1A. The first NAND gate G21amay include a fifth NFT N25athrough a seventh NFET N27a, a fifth PFET P25a, and/or a sixth PFET P26a, which receive the first signal S1and the clock input C_IN.

The NOR gate G25amay receive a clock enable E and/or a test enable SE, and may generate the inverted enable input /E_IN and provide the inverted enable input /E_IN to the OAI gate22a. In some example embodiments, unlike inFIG. 2, the clock gating cell20amay directly receive the inverted enable input /E_IN from outside as the NOR gate G25ais omitted. Furthermore, in some example embodiments, unlike inFIG. 2, the clock gating cell20amay include an inverter, which generates the inverted enable input /E_IN from the enable input, instead of the NOR gate G25a.

The 4-input keeping logic gate G22a, which includes a second NAND gate, may perform an operation of the NAND gate, and may form (or generate) an SR latch (or an SR NAND latch) by providing the second NAND gate to the first NAND gate G21a. For example, the first NAND gate G21aand the 4-input keeping logic gate G22amay be cross-coupled through a first node ND11aand a second node ND21a. The first NAND gate G21a, when the first signal S1is logic ‘1’, may generate the second signal S2dependent on the clock input C_IN, and when the first signal S1is logic ‘0’, may generate the second signal S2that is logic ‘1’, regardless of the clock input C_IN. The OAI gate22amay generate the first signal S1by performing an operation on the inverted enable input /E_IN, the clock input C_IN, the second signal S2, and/or the inverted first signal /S1. The first NAND gate G21amay generate the second signal S2by performing a NAND operation on the first signal S1and/or the clock input C_IN. The inverter G24amay generate the clock output C_OUT by inverting the second signal S2.

To describe a connection structure of the second 2-input logic gate G23ain detail, the first PFET P21amay receive the clock input C_IN through a gate thereof and/or may be connected to the power voltage VDD through a source thereof. The second PFET P22amay be connected to a drain of the first PFET P21athrough a source thereof, and/or may receive the inverted enable input /E_IN through a gate thereof. The second NFET N22amay receive the inverted enable input /E_IN through a gate thereof, and/or may be connected to a drain of the second PFET P22aat the first node ND11athrough a drain thereof.

To describe a connection structure of the 4-input keeping logic gate G22ain detail, the third PFET P23amay be connected to the second node ND21athrough a gate thereof and receive the second signal S2, and/or may be connected to the power voltage VDD through a source thereof. The third NFET N23amay receive the inverted first signal /S1through a gate thereof, and/or may be connected to a source of the fourth NFET N24athrough a drain thereof. The fourth NFET N24amay receive the clock input C_IN through a gate thereof, and/or may be connected to a drain of the third PFET P23aat the first node ND11athrough a drain thereof. The fourth PFET P24amay be connected to the first node ND11athrough a gate thereof and/or receive the first signal S1, may be connected to the power voltage VDD through a source thereof, and/or may be connected to the gate of the third NFET N23athrough a drain thereof. The first NFET N21amay be connected, through a drain thereof, to a third node ND31ato which a pull-down logic of the second 2-input logic gate G23a(for example, the second NFET N22a) and/or a pull-down logic of the 4-input keeping logic gate G22a(for example, the third NFET N23a) are connected in common, may be connected to the second node ND21athrough a gate thereof and receive the second signal S2, and/or may be connected to the ground node through a source thereof. The first NFET N21a, in response to the second signal S2, may form (or generate) or block a discharge path between the third node ND31aand the ground node, which is shared by the second 2-input logic gate G23aand the 4-input keeping logic gate G22a. The third PFET P23a, in response to the second signal S2, may keep a high level of the first signal S1by using the power voltage VDD, and/or the fourth PFET P24a, in response to the first signal S1, may keep a high level of the inverted first signal /S1by using the power voltage VDD. In addition, when the first NFET N21ais activated (for example, when the second signal S2is logic ‘1’), the third NFET N23aand/or the fourth NFET N24amay keep the low level of the first signal S1, respectively in response to the inverted first signal /S1and/or the clock input C_IN.

To describe a connection structure of the first NAND gate G21ain detail, the first PFET P25amay receive the first signal S1through a gate thereof, and/or may be connected to the power voltage VDD through a source thereof. A sixth PFET P26amay receive the clock input C_IN through a gate thereof, may be connected to the power voltage VDD through the source thereof, and/or may be connected to a drain of the fifth PFET P25aat a second node ND21athrough a drain thereof. The fifth PFET P25aand the sixth PFET P26amay be connected in parallel to each other and construct a pull-up logic of the first NAND gate G21a. The fifth NFET N25amay receive the first signal S1through a gate thereof, and/or may be connected to a ground node through a source thereof. The sixth NFET N26amay receive the first signal S1through a gate thereof, and/or may be connected to the ground node through a source thereof. The fifth NFET N25aand the sixth NFET N26amay be connected in parallel to each other, and may construct a pull-down logic of the first NAND gate G21a. The number of transistors (e.g., the fifth PFET P25aand the sixth PFET P26a) constructing the pull-up logic of the first NAND gate G21ais identical (or equal to) to the number of transistors (e.g., the fifth NFET N25aand the sixth NFET N26a) constructing the pull-down logic, and thus, a pull-up strength and a pull-down strength may be equal to each other. The seventh NFET N27amay receive the clock input C_IN through a gate thereof, may be connected to the second node ND21athrough a drain thereof, and/or may be connected to the drains of the fifth NFET N25aand the sixth NFET N26athrough a source thereof.

FIG. 3is a timing diagram of an example of an operation of the clock gating cell20ashown inFIG. 2. The timing diagram shown inFIG. 3shows signals according to time in the clock gating cell20ashown inFIG. 2. For convenience of understanding, in the timing diagram shown inFIG. 3, propagation delay may be ignored, and among descriptions ofFIG. 3, descriptions that are the same as those ofFIGS. 1A, 1B, and 2are omitted.

Referring toFIG. 3, the clock input C_IN may vibrate in a cycle T_CLK. Before a time point t31, the clock enable E and/or the test enable SE may be logic ‘1’, and accordingly, the inverted enable input /E_IN may be logic ‘0’, and the clock gating cell20amay be in an enable state. Due to the 4-input keeping logic gate G22a, the first signal S1may be logic ‘1’, the second signal S2may be identical (or equal to) to an inverted version of the clock input C_IN, and consequentially, the clock output C_OUT may be identical (or equal to) to the clock input (e.g., a delayed version of the clock input C_IN).

At the time point t31, the clock enable E and the test enable SE may be shifted to logic ‘0’, and accordingly, the inverted enable input E_IN may be shifted to logic ‘1’, and the clock gating cell20amay enter a disable state. As the clock input C_IN is logic ‘1’, the first signal S1may be kept as logic ‘1’, and the second signal S2and the clock signal C_OUT may be kept as logic ‘0’ and logic ‘1’, respectively. Next, at a time point t32, a falling edge of the clock input C_IN may occur, and accordingly, by the first NAND gate G21a, the second signal S2and the clock output C_OUT may be respectively shifted to logic ‘1’ and logic ‘0’. In addition, by the second two-input logic gate G22a, the first signal S1may be shifted to logic ‘1’, and accordingly, by the first NAND gate G21a, the second signal S2may be kept as logic ‘1’ regardless of the clock input C_IN. Consequentially, the clock output C_OUT may be kept as logic ‘0’ in the disable state of the clock gating cell20a.

At a time point t33, the clock enable E and/or the test enable SE may be shifted to logic ‘1’, and accordingly, the inverted enable input /E_IN may be shifted to logic ‘0’ and the clock gating cell20amay enter the enable state. As the clock input C_IN and the second signal S2are logic ‘1’, the first signal S1may be kept at logic ‘0’, and accordingly, the second signal S2and the clock output C_OUT may also be kept at logic ‘1’ and logic ‘0’, respectively. Next, at a time point t34, a falling edge of the clock input C_IN may occur, and accordingly, by the second two-input logic gate G22a, the first signal S1may be shifted to logic ‘1’. However, as the clock input C_IN is logic ‘0’, the second signal S2and the clock output C_OUT may respectively maintain logic ‘1’ and logic ‘0’. Next, at a time point t35, a rising edge of the clock signal C_IN may occur at a time point t35, and as the first signal S1is logic ‘1’, the second signal S2and the clock output C_OUT may be respectively shifted to logic ‘0’ and logic ‘1’.

At a time point t36, the clock enable E and the test enable SE may be shifted to logic ‘0’, and accordingly, the inverted enable input /E_IN may be shifted to logic ‘1’ and the clock gating cell20amay enter the disable state. As the second signal S2is logic ‘1’, by the second 2-input logic gate G23a, the first signal S1may be shifted to logic ‘0’, and accordingly, the second signal S2and the clock output C_OUT may be respectively kept at logic ‘1’ and logic ‘0’, regardless of the clock input C_IN.

At a time point t37, the clock enable E and/or the test enable SE may be shifted to logic ‘1’, and accordingly, the inverted enable input /E_IN may be shifted to logic ‘0’ and the clock gating cell20amay enter the enable state. Although the first signal S1may be shifted to logic ‘1’ by the OAI gate22a, as the clock input C_IN is logic ‘0’, the second signal S2and the clock output C_OUT may be respectively kept at logic ‘1’ and logic ‘0’. Next, at a time point t38, a rising edge of the clock input C_IN may occur, and the second signal S2and the clock output C_OUT may be respectively shifted to logic ‘0’ and logic ‘1’.

As described above, power consumption in a section keeping a low level of the first signal S1may be efficiently reduced by using a discharge path formed through the first NFET N21ainFIG. 2, and the quality of the second signal S2may be improved through the first NAND gate G21a(seeFIG. 2) implemented to have the pull-up strength and the pull-down strength that are equal to each other.

FIGS. 4 and 5are circuit diagrams of examples of a clock gating cell20band a clock gating cell20caccording to example embodiments of the inventive concepts. Hereinafter, among descriptions ofFIGS. 4 and 5, descriptions that are the same as those ofFIG. 2are omitted.

Referring toFIG. 4, the clock gating cell20bmay include a first NAND gate G21b, an OAI gate22b, a first inverter G24b, and/or a NOR gate G25b. The OAI gate22bmay include a 4-input keeping logic gate G22band/or a second 2-input logic gate G23b.

The OAI gate22bmay include a first NFET N21bthrough a fourth NFET N24band/or a first PFET P21bthrough a third PFET P23b, which receive the inverted enable input /E_IN, the clock input C_IN, the second signal S2, and/or the inverted first signal /S1, and/or may include a second inverter IVTb which receives the first signal S1and generates the inverted first signal /S1. The first NAND gate G21bmay include a fifth NFET N25b, a fourth PFET P24b, and/or a fifth PFET P25b, which receive the inverted first signal /S1, the clock input C_IN, and/or the first signal S1. Here, the first NAND gate G21bmay also be referred to as a 3-input logic gate.

To describe a connection structure of the four-input keeping logic gate G22bin detail, the third PFET P23bmay be connected to a second node ND21bthrough a gate thereof and receive the second signal S2, and/or may be connected to the power voltage VDD through a source thereof. The third NFET N23bmay receive the inverted first signal /S1through a gate thereof, and/or may be connected to a source of the fourth NFET N24bthrough a drain thereof. The fourth NFET N24bmay receive the clock input C_IN through a gate thereof, and/or may be connected to a drain of the third PFET P23bat a first node ND11bthrough a drain thereof. An input of the second inverter IVTb may be connected to the first node ND11band receive the first signal S1, and/or may output the inverted first signal /S1to the first NAND gate G21b.

To describe a connection structure of the first NAND gate G21bin detail, the fifth NFET N25bmay receive the clock input C_IN through a gate thereof, may receive the inverted first signal /S1through a drain thereof, and/or may be connected to a second node ND21bthrough a source thereof. The fourth PFET P24bmay be connected to the power voltage VDD through a source thereof, may be connected to the first node ND11bthrough a gate thereof and receive the first signal S1, and/or may be connected to the second node ND21bthrough a drain thereof. The fifth PFET P25bmay be connected to the power voltage VDD through a source thereof, may receive the clock input C_IN through a gate thereof, and/or may be connected to the second node ND21bthrough a drain thereof. The fourth PFET P24band the fifth PFET P25bmay be connected in parallel to each other.

Referring toFIG. 5, the clock gating cell20cmay include a first NAND gate G21c, an OAI gate22c, a first inverter G24c, and/or a NOR gate G25c. The OAI gate22cmay include a 4-input keeping logic gate G22cand/or a second 2-input logic gate G23c.

The OAI gate22cmay include a first NFET N21cthrough a fourth NFET N24cand/or a first PFET P21cthrough a third PFET P23cwhich receive the inverted enable input /E_IN, the second signal S2, and/or the inverted first signal /S1, and may include a second inverter IVTc which receives the first signal S1and generates the inverted first signal /S1. The first NAND gate G21cmay include a NAND gate NANDc.

To describe a connection structure of the 4-input keeping logic gate G22cin detail, a third PFET P23cmay receive the second signal S2through a gate thereof, and/or may be connected to the power voltage VDD through a source thereof. The third NFET N23cmay receive the inverted first signal /S1through a gate thereof, and/or may be connected to a source of the fourth NFET N24cthrough a drain thereof. The fourth NFET N24cmay receive the clock input C_IN through a gate thereof, and/or may be connected to a drain of the third PFET P23cat a first node ND11cof through a drain thereof. An input of the second inverter IVTc may be connected to the first node ND11cand receive the first signal S1, and/or may provide the inverted first signal /S1to the gate of the third NFET N23c.

To describe a connection structure of the first NAND gate G21cin detail, the NAND gate NANDc may receive the clock input C_IN and/or the first signal S1and generate the second signal S2. The NAND gate NANDc may be connected to the first inverter G24cthrough the second node ND21c.

The clock gating cells20a,20b, and20cshown inFIGS. 2, 4, and 5are merely example embodiments and are not limited thereto, and the clock gating cell may be implemented by variously arranging transistors and logic gates to include a structure to which the inventive concepts are reflected.

FIGS. 6A and 6Bare circuit diagrams of examples of the clock gating cell10bshown inFIG. 1B. Hereinafter, among descriptions ofFIGS. 6A and 6B, descriptions that are the same as those ofFIG. 1Bare omitted.

Referring toFIG. 6A, a clock gating cell30amay include a first NAND gate G31a, an OAI gate32a, an inverter G34a, and/or a NOR gate G35a. The first NAND gate G31amay correspond to the first 2-input logic gate G11bshown inFIG. 1B, and/or the OAI gate32amay correspond to the 3-input logic gate12bshown inFIG. 1B. The OAI gate32amay include a 3-input keeping logic gate G32a, a first 2-input logic gate G33a, and/or a third 2-input logic gate G36a.

The first 2-input logic gate G33amay include a first NFET N31a, a second NFET N32a, a first PFET P31a, and/or a second PFET P32a, which receive the clock input C_IN, the inverted enable input /E_IN, and/or the second signal S2. The 3-input keeping logic gate G32amay include a third NFET N33a, a fourth NFET N34a, and/or a third PFET P33a, which respectively receive the inverted first signal /S1, the clock input C_IN, and/or the second signal S2. The third 2-input logic gate G36amay include a fifth NFET N35aand/or a fourth PFET P34a, which receive the first signal S1. In addition, the fourth PFET P34amay receive the second signal S2through a source thereof. The first NAND gate G31amay include a NAND gate NANDa, which receives the first signal S1and/or the clock input C_IN and generates the second signal S2. The NAND gate NANDa may be connected to the inverter G34athrough a second node ND22a.

To describe a connection structure of the second 2-input logic gate G33ain detail, the first PFET P31amay receive the clock input C_IN through a gate thereof, and/or may be connected to the power voltage VDD through a source thereof. The second PFET P32amay be connected to a drain of the first PFET P31athrough a source thereof, and/or may receive the inverted enable input /E_IN through a gate thereof. The second NFET N32amay receive the inverted enable input /E_IN through a gate thereof, and/or may be connected to a drain of the second PFET P32aat a first node ND12athrough a drain thereof. The first NFET N31amay be connected to the second node ND22athrough a gate thereof and receive the second signal S2, may be connected to a source of the second NFET N32athrough a drain thereof, and/or may be connected to the ground node through a source thereof. The first NFET N31amay form (or generate) or block a discharge path of the second 2-input logic gate G33ain response to the second signal S2.

To describe a connection structure of the 3-input keeping logic gate G32ain detail, the third PFET P33amay be connected to the second node ND22athrough a gate thereof and/or receive the second signal S2, and/or may be connected to the power voltage VDD through a source thereof. The third NFET N33amay receive the inverted first signal /S1through a gate thereof, and/or may be connected to a source of the fourth NFET N34athrough a drain thereof. The fourth NFET N34amay receive the clock input C_IN through a gate thereof, and/or may be connected to a drain of the third PFET P33aat the first node ND12athrough a drain thereof. The third NFET N33amay form (or generate) or block a discharge path of the 3-input keeping logic gate G32ain response to the inverted first signal /S1.

To describe a connection structure of the third 2-input logic gate G36ain detail, the fourth PFET P34amay receive the first signal S1through a gate thereof, and/or may be connected to the second node ND22athrough a source thereof and receive the second signal S2. The fifth NFET N35amay receive the first signal S1through a gate thereof, may be connected to a drain of the fourth PFET P34athrough a drain thereof, and/or may be connected to the ground node through a source thereof. The third 2-input logic gate G36amay receive the first signal S1and invert the first signal S1, and may provide the inverted first signal /S1to the third NFET N33a. The third 2-input logic gate G36amay perform an inverting operation on the first signal S1by using the second signal S2, and accordingly, as the inverting operation may be performed when the second signal S2is a high level, power may be efficiently consumed by reducing inverting operations. The third 2-input logic gate G36amay be referred to as an inverter.

Referring toFIG. 6B, compared toFIG. 6A, the second 2-input logic gate G33aand the 3-input keeping logic gate G32amay share a mutual discharge path for the first signal. In detail, a source of the third NFET N33amay be connected to the drain of the first NFET N31athrough the third node ND32aand the first NFET N31amay form (or generate) or block a shared discharge path in response to the second signal S2.

FIGS. 7 through 9are circuit diagrams of examples of a clock gating cell30b, a clock gating cell30c, and a clock gating cell30daccording to example embodiments of the inventive concepts. Hereinafter, among descriptions ofFIGS. 7 through 9, descriptions that are the same as those ofFIGS. 6A and 6Bare omitted.

Referring toFIG. 7, a clock gating cell30bmay include a first NAND gate G31b, an OAI gate32b, an inverter G34b, and/or a NOR gate G35b. The OAI gate32bmay include a 3-input keeping logic gate G32b, a second 2-input logic gate G33b, and/or a third 2-input logic gate G36b.

The third 2-input logic gate G36bmay include a fourth PFET P34b. The fourth PFET P34bmay be connected to a first node ND12bthrough a gate thereof and receive the first signal S1, and/or may be connected to a second node ND22bthrough a source thereof and receive the second signal S2.

The first NAND gate G31bmay include a fifth PFET P35b, a sixth PFET P36b, and/or a fifth NFET N35bthrough a seventh NFET N37b, which receive the first signal S1and/or the clock input C_IN. The fifth PFET P35bmay receive the first signal S1through a gate thereof, and/or may be connected to the power voltage VDD through a source thereof. The sixth PFET P36bmay receive the clock input C_IN through a gate thereof, may be connected to the power voltage VDD through a source thereof, and/or may be connected to a drain of the fifth PFET P35bat the second node ND22bthrough a drain thereof. The fifth PFET P35band the sixth PFET P36bmay be connected in parallel to each other and construct a pull-up logic of the first NAND gate G31b. The fifth NFET N35bmay receive the first signal S1through a gate thereof, and/or may be connected to the ground node through a source thereof. The sixth NFET N36bmay receive the first signal S1through a gate thereof, and/or may be connected to the ground node through a source thereof. The fifth NFET N35band the sixth NFET N36bmay be connected in parallel to each other, and may construct a pull-down logic of the first NAND gate G31b. The number of transistors (e.g. the fifth PFET P35band the sixth PFET P36b) constructing the pull-up logic of the first NAND gate G31bis identical (or equal to) to the number of transistors (that is, the fifth NFET N35band the sixth NFET N26a) constructing the pull-down logic, and thus, a pull-up strength and a pull-down strength may be equal to each other. The seventh NFET N37bmay receive the clock input C_IN through a gate thereof, may be connected to the second node ND22bthrough a drain thereof, and/or may be connected to drains of the fifth NFET N35band/or the sixth NFET N36bthrough a source thereof.

To describe a connection structure of the third 2-input logic gate G36ain detail, the fourth PFET P34cmay be connected to a first node ND12cthrough a gate thereof and receive the first signal S1, and/or may be connected to a second node ND22cthrough a source thereof and receive the second signal S2. The fifth NFET N35cmay be connected to the first node ND12cthrough a gate thereof and receive the first signal S1, may be connected to the ground node through a source thereof, and/or may be connected to a drain of the fourth PFET P34cthrough a drain thereof. The third 2-input logic gate G36cmay invert the first signal S1by using the second signal S2, and may provide the inverted first signal S1to the first NAND gate G31and the second 2-input logic gate G33c. The third 2-input logic gate G36may also be referred to as an inverter.

To describe a connection structure of the first NAND gate G31cin detail, the sixth NFET N36cmay receive the clock input C_IN through a gate thereof, may receive the inverted first signal /S1through a drain thereof, and/or may be connected to the second node ND22cthrough a source thereof. The fifth PFET P36cmay be connected to the power voltage VDD through a source thereof, may receive the first signal S1through a gate thereof, and/or may be connected to the second node ND22cthrough a drain thereof. The sixth PFET P36cmay be connected to the power voltage VDD through a source thereof, may receive the clock input C_IN through a gate thereof, and/or may be connected to the second node ND22cthrough a drain thereof. The fifth PFET P35cand the sixth PFET P36cmay be connected in parallel to each other.

Referring toFIG. 9, a clock gating cell30dmay include a first NAND gate G31d, an OAI gate32d, an inverter G34d, and/or a NOR gate G35d. The OAI gate32dmay include a 2-input keeping logic gate G32d, a second 2-input logic gate G33d, and/or a third 2-input logic gate G36d.

Compared toFIG. 7, the 2-input keeping logic gate G32dmay include a third PFET P33dand/or a third NFET N33d, the third 2-input logic gate G36dmay include a fourth PFET P34dand/or a fourth NFET N34d, and/or the first NAND gate G31dmay include a fifth NFET N35d, a sixth NFET N36d, a fifth PFET P35d, and/or a sixth PFET P36d.

To describe a connection structure of the 2-input keeping logic gate G32din detail, the third PFET P33dmay be connected to the second node ND22dthrough a gate thereof and receive the second signal S2, and/or may be connected to the power voltage VDD through a source thereof. The third NFET N33dmay receive the inverted first signal /S1through a gate thereof, may be connected to a drain of the third PFET P33dthrough a drain thereof, and/or may be connected to a drain of the fifth NFET N35dthrough a source thereof.

To describe a connection structure of the third 2-input logic gate G36din detail, the fourth PFET P34dmay be connected to a first node ND12dthrough a gate thereof and receive the first signal S1, and/or may be connected to the second node ND22dthrough a source thereof and receive the second signal S2. The fifth NFET N34dmay be connected to the first node ND12dthrough a gate thereof and receive the first signal S1, may be connected to the ground node through a source thereof, and/or may be connected to a drain of the fourth PFET P34dthrough a drain thereof. The third 2-input logic gate G36dmay invert the first signal S1by using the second signal S2and provide the inverted first signal /S1to the 2-input keeping logic gate G32d. The third 2-input logic gate G36dmay also be referred to as an inverter.

To describe a connection structure of the first NAND gate G31din detail, the fifth PFET P35dmay be connected to the first node ND12dthrough a gate thereof and receive the first signal S1, may be connected to the power voltage VDD through a source thereof, and/or may be connected to the second node ND22dthrough a drain thereof. The sixth PFET P36dmay receive the clock input C_IN through a gate thereof, may be connected to the power voltage VDD through a source thereof, and/or may be connected to the second node ND22dthrough a drain thereof. The fifth PFET P35dand the sixth PFET P36dmay be connected in parallel to each other. The fifth NFET P35dmay receive the clock input C_IN through a gate thereof, may be connected to the ground node through a source thereof, and/or may be connected to a source of the third NFET N33dthrough a drain thereof. The sixth NFET N36dmay be connected to the first node ND12through a gate thereof and receive the first signal S1, may be connected to the drain of the fifth NFET N35dthrough a source thereof, and/or may be connected to the second node ND22dthrough a drain thereof. The 2-input keeping logic gate G32dand the first NAND gate G31dmay share a discharge path for the first signal S1and the second signal S2. The fifth NFET N35dmay form (or generate) or block the shared discharge path, in response to the clock input C_IN.

The clock gating cells30a,30b,30c, and30dshown inFIGS. 6A through 9are merely example embodiments and are not limited thereto, and the clock gating cell may be implemented by variously arranging transistors and logic gates to include a structure to which the inventive concepts are reflected.

FIG. 10is a block diagram of an example of an integrated circuit100including a clock gating cell according to an example embodiment of the inventive concepts. In some example embodiments, the clock gating cell described above with reference to the drawings may be included in an integrated circuit configured to process a digital signal.

As shown inFIG. 10, the integrated circuit100may include a first clock gating cell CGC1, a second clock gating cell CGC2, a power controller PC, a first combination logic block CL1, a second combination logic block CL2, and/or a plurality of flip-flops (e.g., a first positive edge triggered flip-flop PF1, a second positive edge triggered flip-flop PF2, a first negative edge triggered flip-flop NF1, and/or a second negative edge triggered flip-flop NF2).

The power controller PC may control power of the integrated circuit100, and/or may generate a first clock enable E1and/or a second clock enable E2. For example, the power controller PC may generate the first clock enable E1that is deactivated to reduce power consumption by a digital circuit including at least one first positive edge triggered flip-flop PF1, the first combination logic block CL1, and/or at least one second positive edge triggered flip-flop PF2. In addition, the power controller PC may generate the second clock enable E2that is deactivated to reduce power consumption by a digital circuit including at least one first negative edge triggered flip-flop NF1, the second combination logic block CL2, and/or at least one second negative edge triggered flip-flop NF2.

The first clock gating cell CGC1may receive the clock input C_IN, and may stop or resume supply of a clock output C_OUT1based on the first clock enable E1. In addition, the second clock gating cell CGC2may receive the clock input C_IN, and may stop or resume providing a second clock output C_OUT2based on the second clock enable E2.

FIG. 11is a flowchart of a method of manufacturing an integrated circuit, according to an example embodiment of the inventive concepts. In detail, the flowchart shown in FIG.11shows a method of manufacturing an integrated circuit IC (e.g., the integrated circuit100inFIG. 10) including the clock gating cell described above.

In some example embodiments, the clock gating cell may be defined as a standard cell. The standard cell, which is a unit of a layout included in the integrated circuit IC, may be simply referred to as a cell. The integrated circuit IC may include a plurality of various standard cells, and each (or one or more) of the standard cells may provide an intrinsic function. The standard cells may have a structure obeying predetermined (or alternately given) rules based on a semiconductor process for manufacturing the integrated circuit IC, for example, may have a constant length or multiples thereof in a certain direction on a plane that is perpendicular to a direction in which layers are stacked.

A standard cell library (or a cell library) D2may include information regarding the standard cells, for example, function information, characteristic information, layout information, and the like, and may also include information regarding the clock gating cell. As described above with reference to the drawings, the clock gating cell defined by the standard cell library D2may provide high efficiency such as a reduced area and low power consumption, as well as high operation reliability.

In operation S10, a logic synthesis operation may be performed to generate a netlist D3from RTL data D1. For example, a semiconductor design tool (e.g., a logic synthesis tool) may generate a bitstream or a netlist D3including the netlist by performing logic synthesis with reference to the standard cell library D2from the RTL data D1subscribed with a hardware description language (HDL) such as VHSIC hardware description language (VHDL), Verilog, etc. The standard cell library D2may include information regarding performance of the clock gating cell, and in a logic synthesis process, the standard cells may be included in the integrated circuit IC with reference to the information.

In operation S20, a place & routing (P&R) operation may be performed to generate layout data D4from the netlist D3. As shown inFIG. 11, the P&R operation S20may include a plurality of operations S21, S22, and/or S23. In operation S21, an operation to arrange the standard cells may be performed. For example, a semiconductor design tool (e.g., a P&R tool) may arrange a plurality of standard cells by referring to the standard cell library D2from the netlist D3. For example, the semiconductor design tool may arrange a layout of a clock gating cell defined by the netlist D3, with reference to the standard cell library D2. In operation S22, an operation to generate interconnections may be performed. The interconnection may electrically connect an output pin to an input pin of the standard cell, and may include, for example, at least one via and/or at least one conductive pattern. In operation S23, the layout data D4may be generated. The layout data D4may have, for example a format like GDSII, and may include geometric information regarding the standard cells and interconnections.

Optical Proximity Correction (OPC) may be performed in operation S30. OPC may refer to an operation for forming a desired pattern shape by calibrating distortion such as refraction caused due to characteristics of light in photolithography included in a semiconductor process for manufacturing the integrated circuit IC, and a pattern on a mask may be determined by applying OPC to the layout data D4. In some example embodiments, a layout of the integrated circuit IC may be limitedly changed in operation S30, and in operation S30, the limited change in the integrated circuit IC is a post-processing to improve or optimize a structure of the integrated circuit IC, and may be referred to as design polishing.

In operation S40, manufacturing of a mask may be performed. For example, as OPC is applied to the layout data D4, patterns on the mask may be defined to form patterns on a plurality of layers, and at least one mask (or a photomask) may be manufactured for forming patterns on the plurality of layers.

In operation S50, fabrication of the integrated circuit IC may be performed. For example, the integrated circuit IC may be fabricated by patterning a plurality of layers by using the at least one mask manufactured in operation S40. As shown inFIG. 11, operation S50may include operations S51and/or S52. In operation S51, a front-end-of-line (FEOL) process may be performed. In processes of manufacturing the integrated circuit IC, the FEOL may refer to a process of forming individual devices, for example, a transistor, a capacitor, a resistor, and the like on a substrate. For example, the FEOL may include planarizing and cleaning a wafer, forming a trench, forming a well, forming a gate line, forming a source and/or a drain. In operation S52, a back-end-of-line (BEOL) process may be performed. In processes of manufacturing the integrated circuit IC, the BEOL may refer to a process of mutually connecting individual devices, for example, a transistor, a capacitor, a resistor, and the like. For example, the BEOL may include silicidation on a gate region, a source region, and/or a drain region, adding a dielectric, planarizing, forming a hole, adding a metal layer, forming a via, forming a passivation layer, and the like. Next, the integrated circuit IC may be packaged in a semiconductor package and may be used as a component of various applications. As described above, the integrated circuit IC may have high performance and efficiency due to extraordinary characteristics of the clock gating cell, and consequentially, the performance and efficiency of an application including the integrated circuit IC may be improved.