Random code generator with non-volatile memory

A random code generator includes a differential cell array, a power supply circuit, a first selecting circuit and a current judgment circuit. The power supply circuit receives an enrolling signal and a feedback signal. The first selecting circuit receives a first selecting signal. When the enrolling signal is activated and an enrollment is performed on the first differential cell, the power supply circuit provides an enrolling voltage, and the enrolling voltage is transmitted to a first storage element and a second storage element of the first differential cell through the first selecting circuit. Consequently, the cell current is generated. When a magnitude of the cell current is higher than a specified current value, the current judgment circuit activates the feedback signal, so that the power supply circuit stops providing the enrolling voltage.

FIELD OF THE INVENTION

The present invention relates to a random code generator, and more particularly to a random code generator with a non-volatile memory.

BACKGROUND OF THE INVENTION

A physically unclonable function (PUF) technology is a novel method for protecting the data of a semiconductor chip by giving it a unclonable code. That is, the use of the PUF technology can prevent the data of the semiconductor chip from being stolen or cloned. In accordance with the PUF technology, the semiconductor chip is capable of providing a random code. This random code is used as a unique identity code (ID code) of the semiconductor chip to achieve the protecting function.

Generally, the PUF technology acquires the unique random code of the semiconductor chip according to the manufacturing variation of the semiconductor chip. This manufacturing variation includes the semiconductor process variation. That is, even if the PUF semiconductor chip is produced by a precise manufacturing process, the random code cannot be duplicated. Consequently, the PUF semiconductor chip is suitably used in the applications with high security requirements.

Moreover, U.S. Pat. No. 9,613,714 disclosed a one time programming memory cell and a memory array for a PUF technology and an associated random code generating method. In this literature, a one time programmable memory cell and a memory array are manufactured according to the semiconductor process variation. After the program cycle, the unique random code is generated.

SUMMARY OF THE INVENTION

An embodiment of the present invention provides a random code generator. The random code generator includes a differential cell array, a power supply circuit, a first selecting circuit and a current judgment circuit. The differential cell array includes plural differential cells. A first differential cell of the plural differential cells includes a first select transistor, a first storage element and a second storage element. A first source/drain terminal of the first select transistor is connected with a first source line. A gate terminal of the first select transistor is connected with a first word line. The first storage element is connected between a second source/drain terminal of the first select transistor and a first sub-control line of a first control line pair. The second storage element is connected between the second source/drain terminal of the first select transistor and a second sub-control line of the first control line pair. The power supply circuit receives an enrolling signal and a feedback signal. The first selecting circuit receives a first selecting signal. The first selecting circuit is connected with an output terminal of the power supply circuit and the first differential cell. The current judgment circuit is used for detecting a cell current from the output terminal of the power supply circuit. When the enrolling signal is activated and an enrollment is performed on the first differential cell, the power supply circuit provides an enrolling voltage, and the enrolling voltage is transmitted to the first storage element and the second storage element of the first differential cell through the first selecting circuit. Consequently, the cell current is generated. When a magnitude of the cell current is higher than a specified current value, the current judgment circuit activates the feedback signal, so that the power supply circuit stops providing the enrolling voltage.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

FIG. 1is a schematic circuit diagram illustrating a random code generator according to a first embodiment of the present invention. As shown inFIG. 1, the random code generator comprises a differential cell array, an enrolling circuit130and a reading circuit150.

The differential cell array comprises plural differential cells. For succinctness, only two differential cells110and120are shown in the drawing.

The differential cell110comprises a select transistor Ms1and two storage elements112and114. The gate terminal of the select transistor Ms1is connected with a word line WL1. The first source/drain terminal of the select transistor Ms1is connected with a source line SL1. A first terminal of the storage element112is connected with the second source/drain terminal of the select transistor Ms1. A second terminal of the storage element112is connected with a sub-control line La1of a first control line pair. A first terminal of the storage element114is connected with the second source/drain terminal of the select transistor Ms1. A second terminal of the storage element114is connected with a sub-control line La2of the first control line pair.

The differential cell120comprises a select transistor Ms2and two storage elements122and124. The gate terminal of the select transistor Ms2is connected with a word line WL1. The first source/drain terminal of the select transistor Ms2is connected with a source line SL2. A first terminal of the storage element122is connected with the second source/drain terminal of the select transistor Ms2. A second terminal of the storage element122is connected with a sub-control line La3of a second control line pair. A first terminal of the storage element124is connected with the second source/drain terminal of the select transistor Ms2. A second terminal of the storage element124is connected with a sub-control line La4of the second control line pair.

The enrolling circuit130comprises a selecting circuit132, a power supply circuit139and a current judgment circuit138.

The current judgment circuit138comprises a current detector134and a comparator135. The current detector134is used for detecting a cell current of a selected cell and generating a corresponding detection voltage Vs. The comparator135receives the detection voltage Vs and a reference voltage Vref, and generates a feedback signal Sfb.

Generally, the detection voltage Vs from the current detector134is in direct proportion to the cell current. That is, as the cell current increases, the detection voltage Vs increases. Whereas, as the cell current decreases, the detection voltage Vs decreases. If the detection voltage Vs is higher than the reference voltage Vref, the comparator135activates the feedback signal Sfb.

The selecting circuit132is connected with the power supply circuit139and the sub-control lines La1, La2, La3and La4of all control line pairs of the differential cell array. The selecting circuit132determines a selected control line pair according to a selecting signal Ss1. In addition, an enrolling voltage Vp from the power supply circuit139is transmitted to the selected control line pair through the selecting circuit132.

The power supply circuit139receives an enrolling signal Enroll and the feedback signal Sfb. During an enrolling cycle, the enrolling voltage Vp from the power supply circuit139is transmitted to the selected differential cell through the selecting circuit132and the selected control line pair. When the feedback signal Sfb is activated, the power supply circuit139stops providing the enrolling voltage Vp to the selected differential cell.

The reading circuit150comprises a selecting current152and a current comparator154. During a reading cycle, the selecting current152connects the selected control line pair to the current comparator154according to a selecting signal Ss2. According to two reading currents from the selected differential cell, the current comparator154generates an output data Do. The output data Do is used as one bit of a random code. In an embodiment, the selecting currents132and152are multiplexers.

In an embodiment, the storage elements112and114of the differential cell110and the storage elements122and124of the differential cell120are resistive storage elements or floating gate transistors. The example of the resistive storage element includes but is not limited to a magnetoresistive random-access memory (MRAM), a phase change random-access memory (PCRAM) or a resistive random-access memory (ReRAM).

Generally, before a high voltage is received by the resistive storage element, the resistive storage element is in a high resistance state. After the resistive storage element receives a high voltage, the resistive storage element is changed to a low resistance state. Hereinafter, the operating principles of the random code generator will be illustrated by taking the resistive storage elements R112and R114as the examples of the storage elements.

FIG. 2Ais a schematic circuit diagram illustrating the operations of the random code generator according to the first embodiment of the present invention during an enrolling cycle.FIG. 2Bis a schematic circuit diagram illustrating associated signals of the random code generator as shown inFIG. 2A.

In case that the random code generator intends to perform an enrollment on the differential cell110, the selecting circuit132determines a selected control line pair (La1, La2) according to the selecting signal Ss1. Consequently, the power supply circuit139is connected with the selected control line pair (La1, La2) through the selecting circuit132. When the word line WL1is activated, the select transistor Ms1is turned on. Consequently, the differential cell110is the selected cell. Meanwhile, the selected cell is enrolled by the enrolling circuit130.

Please refer toFIG. 2B. The time period between the time point ta and the time point td is an enrolling cycle Tenroll. For example, the enrolling cycle Tenroll is 1 μs. During the enrolling cycle Tenroll, the enrolling signal Enroll is in a high level state.

At the time point ta, the enrolling signal Enroll is activated. Meanwhile, the enrolling cycle is started. The enrolling voltage Vp from the power supply circuit139is transmitted to the selected control line pair (La1, La2) through the selecting circuit132. Since the select transistor Ms1is turned on and the source line SL1is connected with a ground terminal, the resistive storage elements R112and R114receive the enrolling voltage Vp simultaneously. Since both of the resistive storage elements R112and R114are in the high resistance state, the two currents I112and I114generated by the resistive storage elements R112and R114are very low. In addition, a cell current Icell generated by the differential cell110is equal to the sum of the two currents I112and I114. That is, Icell=I112+I114.

Due to the semiconductor process variation, a small difference between the two resistive storage elements R112and R114exists. Consequently, the time points for changing the storage states of the resistive storage elements R112and R114are different.

For example, at the time point tb, the storage state of the resistive storage element R112stats to be changed. Consequently, the resistance of the resistive storage element R112starts to be decreased and the current I112is gradually increased. Since the storage state of the resistive storage element R114is not changed at this moment, the resistance of the resistive storage element R114is very high and the current I114is very low. Meanwhile, the cell current Icell is gradually increased.

As mentioned above, the detection voltage Vs from the current detector134is in direct proportion to the cell current Icell. At the time point tc, the storage state of the resistive storage element R112is changed to the low resistance state. According to the cell current Icell, the current detector134generates the corresponding detection voltage Vs. Since the detection voltage Vs is higher than the reference voltage Vref, the comparator135activates the feedback signal Sfb. Consequently, the power supply circuit139stops providing the enrolling voltage Vp.

When the power supply circuit139stops providing the enrolling voltage Vp, the cell current Icell is no longer generated by the differential cell110. Meanwhile, the enrollment of the differential cell110is completed.

Due to the semiconductor process variation, it is unable to predict which of the two resistive storage elements R112and R114of the selected differential cell has the changed storage state during the enrollment of the random code generator. Consequently, the random code generator of the present invention generates an unclonable code according to the PUF technology.

FIG. 2Cis a schematic circuit diagram illustrating the operations of the random code generator according to the first embodiment of the present invention during a reading cycle. In case that the random code generator performs a reading action on the differential cell110, the control line pair (La1, La2) is determined as the selected control line pair according to the selecting signal Ss2. In addition, the sub-control lines La1and La2of the selected control line pair are connected with two input terminals of the current comparator154by the selecting current152. When the word line WL1is activated, the select transistor Ms1is turned on. Consequently, the differential cell110is the selected cell. Meanwhile, the selected cell is read by the reading circuit150.

Please refer toFIG. 2Cagain. During the reading cycle, the source line SL1receives a reading voltage Vread (e.g., 0.5V). Consequently, the resistive storage elements R112and R114generate the read currents Ir112and Ir114, respectively. After the enrollment, the resistive storage element R112is in the low resistance state, and the resistive storage element R114is in the high resistance state. Consequently, the read current Ir112is higher than the read current Ir114. According to the read currents Ir12and Ir14from the sub-control lines La1and La2of the selected control line pair, the current comparator154generates the output data Do. For example, the output data Do has a logic value “1”. The logic value “1” of the output data Do can be used as one bit of the random code.

On the other hand, if the resistive storage element R112is in the high resistance state, and the resistive storage element R114is in the low resistance state after the enrollment, the current comparator154generates the output data Do having a logic value “0” during the reading cycle. The logic value “0” of the output data Do can be used as one bit of the random code.

By using the above method, the random code generator may perform enrollment on plural differential cells of the differential cell array. After the reading action is performed on the plural differential cells, plural bits of a random code are obtained. For example, the random code generator performs enrollment on 8 differential cells. After the reading action is performed on the 8 differential cells, a one-byte random code is obtained.

FIG. 3is a schematic circuit diagram illustrating a random code generator according to a second embodiment of the present invention. In comparison with the first embodiment, the components connected with the selecting circuit332of the enrolling circuit330are distinguished. For brevity, only the connecting relationships about the selecting circuit332will be described as follows.

The selecting circuit332of the enrolling circuit330is connected with the power supply circuit139and all source lines SL1and SL2of the differential cell array. The selecting circuit332determines a selected source line according to the selecting signal Ss1. In addition, an enrolling voltage Vp from the power supply circuit139is transmitted to the selected source line through the selecting circuit332.

In an embodiment, the storage elements112and114of the differential cell110and the storage elements122and124of the differential cell120are resistive storage elements or floating gate transistors. The example of the resistive storage element includes but is not limited to a magnetoresistive random-access memory (MRAM), a phase change random-access memory (PCRAM) or a resistive random-access memory (ReRAM).

Generally, after the floating gate transistor is produced, no hot carriers (e.g., electrons) are stored in the floating gate of the floating gate transistor. Consequently, the floating gate transistor is turned off, and the floating gate transistor is in a high resistance state. After the hot carriers (e.g., electrons) are injected into the floating gate of the floating gate transistor, the floating gate transistor is turned on, and the floating gate transistor is in a low resistance state. Hereinafter, the operating principles of the random code generator will be illustrated by taking the P-type floating gate transistors Mp122and Mp124as the examples of the storage elements.

FIG. 4Ais a schematic circuit diagram illustrating the operations of the random code generator according to the second embodiment of the present invention during an enrolling cycle.FIG. 4Bis a schematic circuit diagram illustrating associated signals of the random code generator as shown inFIG. 4A.

In case that the random code generator intends to perform an enrollment on the differential cell120, the selecting circuit332determines the source line SL2as the selected source line according to the selecting signal Ss1. Consequently, the power supply circuit139is connected with the selected source line SL2through the selecting circuit332. When the word line WL1is activated, the select transistor Ms2is turned on. Consequently, the differential cell120is the selected cell. Meanwhile, the selected cell is enrolled by the enrolling circuit330.

Please refer toFIG. 4B. The time period between the time point t1and the time point t4is an enrolling cycle Tenroll. For example, the enrolling cycle Tenroll is 110 μs. During the enrolling cycle Tenroll, the enrolling signal Enroll is in a high level state.

At the time point t1, the enrolling signal Enroll is activated. Meanwhile, the enrolling cycle is started. The enrolling voltage Vp from the power supply circuit139is transmitted to the selected source line SL2through the selecting circuit332. Since the select transistor Ms2is turned on and the control line pair (La3, La4) is connected with the ground terminal, the P-type floating gate transistor Mp122and Mp124receive the enrolling voltage Vp simultaneously. Since both of the P-type floating gate transistors Mp122and Mp124are in the high resistance state, the two currents I122and I124generated by the P-type floating gate transistors Mp122and Mp124are very low. In addition, a cell current Icell generated by the differential cell120is equal to the sum of the two currents I122and I124. That is, Icell=I122+I124.

Due to the semiconductor process variation, a small difference between the two P-type floating gate transistors Mp122and Mp124exists. Consequently, the time points for changing the storage states of the P-type floating gate transistor Mp122and Mp124are different.

For example, at the time point t2, the storage state of the P-type floating gate transistor Mp124stats to be changed. Meanwhile, electrons are injected into the floating gate of the P-type floating gate transistor Mp124through a channel region of the P-type floating gate transistor Mp124. Consequently, the resistance of the P-type floating gate transistor Mp124starts to be decreased and the current I124is gradually increased. Since no electrons are injected into the floating gate of the P-type floating gate transistor Mp122at this moment, the resistance of the P-type floating gate transistor Mp122is very high and the current I122is very low. Meanwhile, the cell current Icell is gradually increased.

At the time point t3, a great number of electrons have been injected into the floating gate of the P-type floating gate transistor Mp124, the P-type floating gate transistor Mp124is turned on and the storage state of the P-type floating gate transistor Mp124is changed to the low resistance state. According to the cell current Icell, the current detector134generates the corresponding detection voltage Vs. Since the detection voltage Vs is higher than the reference voltage Vref, the comparator135activates the feedback signal Sfb. Consequently, the power supply circuit139stops providing the enrolling voltage Vp.

When the power supply circuit139stops providing the enrolling voltage Vp, the cell current Icell is no longer generated by the differential cell110. Meanwhile, the enrollment of the differential cell120is completed.

Due to the semiconductor process variation, it is unable to realize which of the two P-type floating gate transistors Mp122and Mp124of the selected differential cell has the changed storage state during the enrollment of the random code generator. Consequently, the random code generator of the present invention generates the random code according to the PUF technology.

FIG. 4Cis a schematic circuit diagram illustrating the operations of the random code generator according to the second embodiment of the present invention during a reading cycle. In case that the random code generator performs a reading action on the differential cell120, the control line pair (La3, La4) is determined as the selected control line pair according to the selecting signal Ss2. In addition, the sub-control lines La3and La4of the selected control line pair are connected with two input terminals of the current comparator154by the selecting current152. When the word line WL1is activated, the select transistor Ms2is turned on. Consequently, the differential cell120is the selected cell. Meanwhile, the selected cell is read by the reading circuit150.

Please refer toFIG. 4Cagain. During the reading cycle, the source line SL2receives a reading voltage Vread (e.g., 1.0V). Consequently, the P-type floating gate transistors Mp122and Mp124generate the read currents Ir122and Ir124, respectively. After the enrollment, the P-type floating gate transistors Mp124is in the low resistance state, and the P-type floating gate transistors Mp122is in the high resistance state. Consequently, the read current Ir124is higher than the read current Ir122. According to the read currents Ir122and Ir124from the sub-control lines La3and La4of the selected control line pair, the current comparator154generates the output data Do. For example, the output data Do has a logic value “0”. The logic value “0” of the output data Do can be used as one bit of the random code.

On the other hand, if the P-type floating gate transistors Mp124is in the high resistance state, and the P-type floating gate transistors Mp122is in the low resistance state after the enrollment, the current comparator154generates the output data Do having a logic value “1” during the reading cycle. The logic value “1” of the output data Do can be used as one bit of the random code.

FIG. 5is a schematic circuit diagram illustrating an exemplary enrolling circuit of the random code generator according to an embodiment of the present invention. The enrolling circuit500comprises a selecting circuit520, a power supply circuit510and a current judgment circuit530.

The power supply circuit510comprises a power source512, an operational amplifier (OP)514, and two transistors M1, M2. The power source512includes a voltage output terminal connected to a positive input terminal of the operational amplifier514. Moreover, an enabling terminal EN of the power source512receives the enrolling signal Enroll and a feedback terminal of the power source512receives a feedback signal Sfb. When the enrolling signal Enroll is in the high level state, the power source512is enabled to generate the enrolling voltage Vp to the positive input terminal of the operational amplifier514. Furthermore, when the feedback signal Sfb is activated, the power source512stops providing the enrolling voltage Vp. For example, when the feedback signal Sfb is activated, the voltage output terminal of the power source512provides a ground voltage (0V) to the positive input terminal of the operational amplifier514.

The source terminal of the transistor M1receives a power voltage Vd. The gate terminal and the drain terminal of the transistor M1are connected with each other. The drain terminal of the transistor M2is connected with the drain terminal of the transistor M1. The gate terminal of the transistor M2is connected with an output terminal of the operational amplifier514. A source terminal of the transistor M2is connected with a negative input terminal of the operational amplifier514. The source terminal of the transistor M2is used as an output terminal of the power supply circuit510, and connected with the selecting circuit520.

The current judgment circuit530comprises a transistor M3, a comparator532and a resistor R. The gate terminal of the transistor M3is connected with the gate terminal of the transistor M1of the power supply circuit510. The source terminal of the transistor M3receives the power voltage Vd. The drain terminal of the transistor M3is connected to the node “a”. The gate terminal of the resistor R is connected between the node “a” and the ground terminal. The positive input terminal of the comparator532is connected with the node “a”. The negative input terminal of the comparator532receives the reference voltage Vref. The output terminal of the comparator532generates the feedback signal Sfb.

For example, the selecting circuit520is a multiplexer. In case that the selecting circuit520is applied to the random code generator of the first embodiment, the enrolling voltage Vp from the power supply circuit510is transmitted to the selected control line pair through the selecting circuit520according to the selecting signal Ss1. In case that the selecting circuit520is applied to the random code generator of the second embodiment, the enrolling voltage Vp from the power supply circuit510is transmitted to the selected source line through the selecting circuit520according to the selecting signal Ss1.

During the enrolling cycle, the enrolling signal Enroll is in the high level state. Consequently, the enrolling voltage Vp is outputted from the power source512. Moreover, the feedback signal Sfb is in the low level state that means the feedback signal Sfb is not activated. Consequently, the positive input terminal of the operational amplifier514to receive the enrolling voltage Vp, and the enrolling voltage Vp is outputted from the output terminal of the power supply circuit510. When the selecting circuit520is connected with the selected cell, the output terminal of the power supply circuit510generates the cell current Icell.

Moreover, the transistors M1and M3are connected with each other to form a current mirror. Consequently, the transistor M3generates a mirror current Icell′. The mirror current Icell′ flows through the resistor R. As the cell current Icell increases, the mirror current Icell′ also increases. Consequently, the detected voltage Vs at the node “a” increases. When the detected voltage Vs at the node “a” reaches the reference voltage vref, the comparator532activates the feedback signal Sfb. Meanwhile, the power supply circuit510stops providing the enrolling voltage Vp to the selected differential cell, and the enrollment is completed.

From the above descriptions, the present invention provides a random code generator. During the enrollment, the unpredictable storage state is generated according to the small difference between the two storage elements of the differential cell. Consequently, during the reading cycle, the storage state of the differential cell is verified and used as one bit of the random code.