DECODER SIDE MOTION INFORMATION DERIVATION

Implementations of the disclosure provide a video processing method for motion information derivation. The video processing method may include determining, by a video decoder, that one or more motion related parameters for a video block in a video frame of a video are not signaled in a bitstream. The video processing method may further include determining, by the video decoder, the one or more motion related parameters for the video block by applying a coding matching technique.

TECHNICAL FIELD

This application is related to video coding and compression. More specifically, this application relates to video processing apparatuses and methods for motion information derivation on a video decoder side.

BACKGROUND

Digital video is supported by a variety of electronic devices, such as digital televisions, laptop or desktop computers, tablet computers, digital cameras, digital recording devices, digital media players, video gaming consoles, smart phones, video teleconferencing devices, video streaming devices, etc. The electronic devices transmit and receive or otherwise communicate digital video data across a communication network, and/or store the digital video data on a storage device. Due to a limited bandwidth capacity of the communication network and limited memory resources of the storage device, video coding may be used to compress the video data according to one or more video coding standards before it is communicated or stored. For example, video coding standards include Versatile Video Coding (VVC), Joint Exploration test Model (JEM), High-Efficiency Video Coding (HEVC/H.265), Advanced Video Coding (AVC/H.264), Moving Picture Expert Group (MPEG) coding, or the like. Video coding generally utilizes prediction methods (e.g., inter-prediction, intra-prediction, or the like) that take advantage of redundancy inherent in the video data. Video coding aims to compress video data into a form that uses a lower bit rate, while avoiding or minimizing degradations to video quality.

SUMMARY

Implementations of the present disclosure provide a video processing method for motion information derivation. The video processing method may include determining, by a video decoder, that one or more motion related parameters for a video block in a video frame are not signaled in a bitstream. The video processing method may further include determining, by the video decoder, the one or more motion related parameters for the video block by applying a coding matching technique. The coding matching technique is a template matching technique or a bilateral matching technique.

Implementations of the present disclosure also provide a video decoder apparatus for motion information derivation. The video decoder apparatus may include a memory configured to store a bitstream and a processor coupled to the memory. The processor may be configured to determine that one or more motion related parameters for a video block in a video frame are not signaled in the bitstream. The processor may further be configured to determine the one or more motion related parameters for the video block by applying a coding matching technique. The coding matching technique is a template matching technique or a bilateral matching technique.

Implementations of the present disclosure also provide a non-transitory computer-readable storage medium having storing a bitstream to be decoded by a video processing method. The video processing method may include determining that one or more motion related parameters for a video block in a video frame are not signaled in the bitstream. The video processing method may further include determining the one or more motion related parameters for the video block by applying a coding matching technique. The coding matching technique is a template matching technique or a bilateral matching technique.

Implementations of the present disclosure also provide a video processing method for encoding motion information. The video processing method may include receiving, by a video encoder, a video block in a video frame. The video processing method may include determining, by the video encoder, not to signal one or more motion related parameters for the video block in a bitstream. The video processing method may include generating, by the video encoder, at least one syntax element to indicate that the one or more motion related parameters for the video block are to be predicted. The video processing method may further include including, by the video encoder, the at least one syntax element in the bitstream to independently determine the one or more motion related parameters.

Alternatively, the one or more motion related parameters include one or more motion vector differences (MVDs) for the video block.

Alternatively, generating the at least one syntax element includes: for each of the one or more MVDs, encoding the MVD using a binarization and splitting method; and generating a set of syntax elements based on the encoding of the MVD.

Alternatively, for each of the one or more MVDs, encoding the MVD using the binarization and splitting method includes: binarizing an absolute value of the MVD into a bit plane; dividing the bit plane into a set of most significant bins (MSBs), a set of derived most significant bins (d-MSBs), and a set of least significant bins (LSBs); and generating a reduced absolute value for the MVD using the set of MSBs and the set of LSBs.

Alternatively, for each of the one or more MVDs, generating the set of syntax elements based on the encoding of the MVD includes: generating a first syntax element for indicating whether MVD prediction is to be applied on the video decoder; generating a second syntax element for signaling the reduced absolute value of the MVD to the video decoder; generating a third syntax element for signaling a length of the set of d-MSBs to the video decoder; and generating a fourth syntax element for signaling a position where the set of d-MSBs starts in the bit plane to the video decoder.

Alternatively, the one or more motion related parameters include one or more reference indices for the video block.

Alternatively, generating the at least one syntax element includes: generating a syntax element for indicating whether reference index derivation is to be applied on the video decoder.

Alternatively, the video block is coded using a uni-prediction scheme or a bi-prediction scheme by the video encoder.

Implementations of the present disclosure also provide a video encoder apparatus for encoding motion information. The video encoder apparatus may include a memory configured to store a bitstream and a processor coupled to the memory. The processor may be configured to receive a video block in a video frame. The processor may be configured to determine not to signal one or more motion related parameters for the video block in a bitstream. The processor may be configured to generate at least one syntax element to indicate that the one or more motion related parameters for the video block are to be predicted. The processor may be configured to include the at least one syntax element in the bitstream to independently determine the one or more motion related parameters.

Implementations of the present disclosure also provide a non-transitory computer-readable storage medium having stored therein a bitstream and instructions which, when executed by a processor of a video encoder, cause the processor to perform a video processing method for encoding motion information. The video processing method may include receiving a video block in a video frame. The video processing method may include determining not to signal one or more motion related parameters for the video block in a bitstream. The video processing method may include generating, by the video encoder, at least one syntax element to indicate that the one or more motion related parameters for the video block are to be predicted. The video processing method may further include including the at least one syntax element in the bitstream to independently determine the one or more motion related parameters.

It is to be understood that both the foregoing general description and the following detailed description are examples only and are not restrictive of the present disclosure.

DETAILED DESCRIPTION

Reference will now be made in detail to specific implementations, examples of which are illustrated in the accompanying drawings. In the following detailed description, numerous non-limiting specific details are set forth in order to assist in understanding the subject matter presented herein. But it will be apparent to one of ordinary skill in the art that various alternatives may be used without departing from the scope of claims and the subject matter may be practiced without these specific details. For example, it will be apparent to one of ordinary skill in the art that the subject matter presented herein can be implemented on many types of electronic devices with digital video capabilities.

It should be illustrated that the terms “first,” “second,” and the like used in the description, claims of the present disclosure, and the accompanying drawings are used to distinguish objects, and not used to describe any specific order or sequence. It should be understood that the data used in this way may be interchanged under an appropriate condition, such that the embodiments of the present disclosure described herein may be implemented in orders besides those shown in the accompanying drawings or described in the present disclosure.

FIG.1is a block diagram illustrating an exemplary system10for encoding and decoding video blocks in parallel in accordance with some implementations of the present disclosure. As shown inFIG.1, the system10includes a source device12that generates and encodes video data to be decoded at a later time by a destination device14. The source device12and the destination device14may include any of a wide variety of electronic devices, including desktop or laptop computers, tablet computers, smart phones, set-top boxes, digital televisions, cameras, display devices, digital media players, video gaming consoles, video streaming device, or the like. In some implementations, the source device12and the destination device14are equipped with wireless communication capabilities.

In some implementations, the destination device14may receive the encoded video data to be decoded via a link16. The link16may include any type of communication medium or device capable of forwarding the encoded video data from the source device12to the destination device14. In one example, the link16may include a communication medium to enable the source device12to transmit the encoded video data directly to the destination device14in real time. The encoded video data may be modulated according to a communication standard, such as a wireless communication protocol, and transmitted to the destination device14. The communication medium may include any wireless or wired communication medium, such as a Radio Frequency (RF) spectrum or one or more physical transmission lines. The communication medium may form part of a packet-based network, such as a local area network, a wide-area network, or a global network such as the Internet. The communication medium may include routers, switches, base stations, or any other equipment that may be useful to facilitate communication from the source device12to the destination device14.

In some other implementations, the encoded video data may be transmitted from an output interface22to a storage device32. Subsequently, the encoded video data in the storage device32may be accessed by the destination device14via an input interface28. The storage device32may include any of a variety of distributed or locally accessed data storage media such as a hard drive, Blu-ray discs, Digital Versatile Disks (DVDs), Compact Disc Read-Only Memories (CD-ROMs), flash memory, volatile or non-volatile memory, or any other suitable digital storage media for storing the encoded video data. In a further example, the storage device32may correspond to a file server or another intermediate storage device that may store the encoded video data generated by the source device12. The destination device14may access the stored video data from the storage device32via streaming or downloading. The file server may be any type of computer capable of storing the encoded video data and transmitting the encoded video data to the destination device14. Exemplary file servers include a web server (e.g., for a website), a File Transfer Protocol (FTP) server, Network Attached Storage (NAS) devices, or a local disk drive. The destination device14may access the encoded video data through any standard data connection, including a wireless channel (e.g., a Wireless Fidelity (Wi-Fi) connection), a wired connection (e.g., Digital Subscriber Line (DSL), cable modem, etc.), or any combination thereof that is suitable for accessing encoded video data stored on a file server. The transmission of the encoded video data from the storage device32may be a streaming transmission, a download transmission, or a combination of both.

As shown inFIG.1, the source device12includes a video source18, a video encoder20, and the output interface22. The video source18may include a source such as a video capturing device, e.g., a video camera, a video archive containing previously captured video, a video feeding interface to receive video data from a video content provider, and/or a computer graphics system for generating computer graphics data as the source video, or a combination of such sources. As one example, if the video source18is a video camera of a security surveillance system, the source device12and the destination device14may include camera phones or video phones. However, the implementations described in the present disclosure may be applicable to video coding in general, and may be applied to wireless and/or wired applications.

The captured, pre-captured, or computer-generated video may be encoded by the video encoder20. The encoded video data may be transmitted directly to the destination device14via the output interface22of the source device12. The encoded video data may also (or alternatively) be stored onto the storage device32for later access by the destination device14or other devices, for decoding and/or playback. The output interface22may further include a modem and/or a transmitter.

The destination device14includes the input interface28, a video decoder30, and a display device34. The input interface28may include a receiver and/or a modem and receive the encoded video data over the link16. The encoded video data communicated over the link16, or provided on the storage device32, may include a variety of syntax elements generated by the video encoder20for use by the video decoder30in decoding the video data. Such syntax elements may be included within the encoded video data transmitted on a communication medium, stored on a storage medium, or stored on a file server.

In some implementations, the destination device14may include the display device34, which can be an integrated display device and an external display device that is configured to communicate with the destination device14. The display device34displays the decoded video data for a user, and may include any of a variety of display devices such as a Liquid Crystal Display (LCD), a plasma display, an Organic Light Emitting Diode (OLED) display, or another type of display device.

The video encoder20and the video decoder30may operate according to proprietary or industry standards, such as VVC, HEVC, MPEG-4, Part 10, AVC, or extensions of such standards. It should be understood that the present disclosure is not limited to a specific video encoding/decoding standard and may be applicable to other video encoding/decoding standards. It is generally contemplated that the video encoder20of the source device12may be configured to encode video data according to any of these current or future standards. Similarly, it is also generally contemplated that the video decoder30of the destination device14may be configured to decode video data according to any of these current or future standards.

The video encoder20and the video decoder30each may be implemented as any of a variety of suitable encoder and/or decoder circuitry, such as one or more microprocessors, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs), discrete logic, software, hardware, firmware or any combinations thereof. When implemented partially in software, an electronic device may store instructions for the software in a suitable, non-transitory computer-readable medium and execute the instructions in hardware using one or more processors to perform the video encoding/decoding operations disclosed in the present disclosure. Each of the video encoder20and the video decoder30may be included in one or more encoders or decoders, either of which may be integrated as part of a combined encoder/decoder (CODEC) in a respective device.

FIG.2is a block diagram illustrating an exemplary video encoder20in accordance with some implementations described in the present application. The video encoder20may perform intra and inter predictive coding of video blocks within video frames. Intra predictive coding relies on spatial prediction to reduce or remove spatial redundancy in video data within a given video frame or picture. Inter predictive coding relies on temporal prediction to reduce or remove temporal redundancy in video data within adjacent video frames or pictures of a video sequence. It should be noted that the term “frame” may be used as synonyms for the term “image” or “picture” in the field of video coding.

As shown inFIG.2, the video encoder20includes a video data memory40, a prediction processing unit41, a Decoded Picture Buffer (DPB)64, a summer50, a transform processing unit52, a quantization unit54, and an entropy encoding unit56. The prediction processing unit41further includes a motion estimation unit42, a motion compensation unit44, a partition unit45, an intra prediction processing unit46, and an intra Block Copy (BC) unit48. In some implementations, the video encoder20also includes an inverse quantization unit58, an inverse transform processing unit60, and a summer62for video block reconstruction. An in-loop filter63, such as a deblocking filter, may be positioned between the summer62and the DPB64to filter block boundaries to remove block artifacts from reconstructed video data. Another in-loop filter, such as an SAO filter and/or Adaptive in-Loop Filter (ALF), may also be used in addition to the deblocking filter to filter an output of the summer62. In some examples, the in-loop filters may be omitted, and the decoded video block may be directly provided by the summer62to the DPB64. The video encoder20may take the form of a fixed or programmable hardware unit or may be divided among one or more of the illustrated fixed or programmable hardware units.

The video data memory40may store video data to be encoded by the components of the video encoder20. The video data in the video data memory40may be obtained, for example, from the video source18as shown inFIG.1. The DPB64is a buffer that stores reference video data (for example, reference frames or pictures) for use in encoding video data by the video encoder20(e.g., in intra or inter predictive coding modes). The video data memory40and the DPB64may be formed by any of a variety of memory devices. In various examples, the video data memory40may be on-chip with other components of the video encoder20, or off-chip relative to those components.

As shown inFIG.2, after receiving the video data, the partition unit45within the prediction processing unit41partitions the video data into video blocks. This partitioning may also include partitioning a video frame into slices, tiles (for example, sets of video blocks), or other larger Coding Units (CUs) according to predefined splitting structures such as a Quad-Tree (QT) structure associated with the video data. The video frame is or may be regarded as a two-dimensional array or matrix of samples with sample values. A sample in the array may also be referred to as a pixel or a pel. A number of samples in horizontal and vertical directions (or axes) of the array or picture define a size and/or a resolution of the video frame. The video frame may be divided into multiple video blocks by, for example, using QT partitioning. The video block again is or may be regarded as a two-dimensional array or matrix of samples with sample values, although of smaller dimension than the video frame. A number of samples in horizontal and vertical directions (or axes) of the video block define a size of the video block. The video block may further be partitioned into one or more block partitions or sub-blocks (which may form again blocks) by, for example, iteratively using QT partitioning, Binary-Tree (BT) partitioning, Triple-Tree (TT) partitioning or any combination thereof. It should be noted that the term “block” or “video block” as used herein may be a portion, in particular a rectangular (square or non-square) portion, of a frame or a picture. With reference to, for example, HEVC and VVC, the block or video block may be or correspond to a Coding Tree Unit (CTU), a CU, a Prediction Unit (PU), or a Transform Unit (TU), and/or may be or correspond to a corresponding block, e.g., a Coding Tree Block (CTB), a Coding Block (CB), a Prediction Block (PB), or a Transform Block (TB). Alternatively or additionally, the block or video block may be or correspond to a sub-block of a CTB, a CB, a PB, a TB, etc.

The prediction processing unit41may select one of a plurality of possible predictive coding modes, such as one of a plurality of intra predictive coding modes or one of a plurality of inter predictive coding modes, for the current video block based on error results (e.g., coding rate and the level of distortion). The prediction processing unit41may provide the resulting intra or inter prediction coded block (e.g., a predictive block) to the summer50to generate a residual block and to the summer62to reconstruct the encoded block for use as part of a reference frame subsequently. The prediction processing unit41also provides syntax elements, such as motion vectors, intra-mode indicators, partition information, and other such syntax information to the entropy encoding unit56.

In order to select an appropriate intra predictive coding mode for the current video block, the intra prediction processing unit46within the prediction processing unit41may perform intra predictive coding of the current video block relative to one or more neighbor blocks in the same frame as the current block to be coded to provide spatial prediction. The motion estimation unit42and the motion compensation unit44within the prediction processing unit41perform inter predictive coding of the current video block relative to one or more predictive blocks in one or more reference frames to provide temporal prediction. The video encoder20may perform multiple coding passes, e.g., to select an appropriate coding mode for each block of video data.

In some implementations, the motion estimation unit42determines the inter prediction mode for a current video frame by generating a motion vector, which indicates the displacement of a video block within the current video frame relative to a predictive block within a reference frame, according to a predetermined pattern within a sequence of video frames. Motion estimation, performed by the motion estimation unit42, may be a process of generating motion vectors, which may estimate motion for video blocks. A motion vector, for example, may indicate the displacement of a video block within a current video frame or picture relative to a predictive block within a reference frame. The predetermined pattern may designate video frames in the sequence as P frames or B frames. The intra BC unit48may determine vectors, e.g., block vectors, for intra BC coding in a manner similar to the determination of motion vectors by the motion estimation unit42for inter prediction, or may utilize the motion estimation unit42to determine the block vectors.

A predictive block for the video block may be or may correspond to a block or a reference block of a reference frame that is deemed as closely matching the video block to be coded in terms of pixel difference, which may be determined by Sum of Absolute Difference (SAD), Sum of Square Difference (SSD), or other difference metrics. In some implementations, the video encoder20may calculate values for sub-integer pixel positions of reference frames stored in the DPB64. For example, the video encoder20may interpolate values of one-quarter pixel positions, one-eighth pixel positions, or other fractional pixel positions of the reference frame. Therefore, the motion estimation unit42may perform a motion search relative to the full pixel positions and fractional pixel positions and output a motion vector with fractional pixel precision.

The motion estimation unit42calculates a motion vector for a video block in an inter prediction coded frame by comparing the position of the video block to the position of a predictive block of a reference frame selected from a first reference frame list (List 0) or a second reference frame list (List 1), each of which identifies one or more reference frames stored in the DPB64. The motion estimation unit42sends the calculated motion vector to the motion compensation unit44and then to the entropy encoding unit56.

Motion compensation, performed by the motion compensation unit44, may involve fetching or generating the predictive block based on the motion vector determined by the motion estimation unit42. Upon receiving the motion vector for the current video block, the motion compensation unit44may locate a predictive block to which the motion vector points in one of the reference frame lists, retrieve the predictive block from the DPB64, and forward the predictive block to the summer50. The summer50then forms a residual block of pixel difference values by subtracting pixel values of the predictive block provided by the motion compensation unit44from the pixel values of the current video block being coded. The pixel difference values forming the residual block may include luma or chroma component differences or both. The motion compensation unit44may also generate syntax elements associated with the video blocks of a video frame for use by the video decoder30in decoding the video blocks of the video frame. The syntax elements may include, for example, syntax elements defining the motion vector used to identify the predictive block, any flags indicating the prediction mode, or any other syntax information described herein. It is noted that the motion estimation unit42and the motion compensation unit44may be integrated together, which are illustrated separately for conceptual purposes inFIG.2.

In some implementations, the intra BC unit48may generate vectors and fetch predictive blocks in a manner similar to that described above in connection with the motion estimation unit42and the motion compensation unit44, but with the predictive blocks being in the same frame as the current block being coded and with the vectors being referred to as block vectors as opposed to motion vectors. In particular, the intra BC unit48may determine an intra-prediction mode to use to encode a current block. In some examples, the intra BC unit48may encode a current block using various intra-prediction modes, e.g., during separate encoding passes, and test their performance through rate-distortion analysis. Next, the intra BC unit48may select, among the various tested intra-prediction modes, an appropriate intra-prediction mode to use and generate an intra-mode indicator accordingly. For example, the intra BC unit48may calculate rate-distortion values using a rate-distortion analysis for the various tested intra-prediction modes, and select the intra-prediction mode having the best rate-distortion characteristics among the tested modes as the appropriate intra-prediction mode to use. Rate-distortion analysis generally determines an amount of distortion (or error) between an encoded block and an original, unencoded block that was encoded to produce the encoded block, as well as a bitrate (i.e., a number of bits) used to produce the encoded block. Intra BC unit48may calculate ratios from the distortions and rates for the various encoded blocks to determine which intra-prediction mode exhibits the best rate-distortion value for the block.

In other examples, the intra BC unit48may use the motion estimation unit42and the motion compensation unit44, in whole or in part, to perform such functions for Intra BC prediction according to the implementations described herein. In either case, for intra block copy, a predictive block may be a block that is deemed as closely matching the block to be coded, in terms of pixel difference, which may be determined by SAD, SSD, or other difference metrics, and identification of the predictive block may include calculation of values for sub-integer pixel positions.

Whether the predictive block is from the same frame according to intra prediction, or from a different frame according to inter prediction, the video encoder20may form a residual block by subtracting pixel values of the predictive block from the pixel values of the current video block being coded, forming pixel difference values. The pixel difference values forming the residual block may include both luma and chroma component differences.

The intra prediction processing unit46may intra-predict a current video block, as an alternative to the inter-prediction performed by the motion estimation unit42and the motion compensation unit44, or the intra block copy prediction performed by the intra BC unit48, as described above. In particular, the intra prediction processing unit46may determine an intra prediction mode to use to encode a current block. For example, the intra prediction processing unit46may encode a current block using various intra prediction modes, e.g., during separate encoding passes, and the intra prediction processing unit46(or a mode selection unit, in some examples) may select an appropriate intra prediction mode to use from the tested intra prediction modes. The intra prediction processing unit46may provide information indicative of the selected intra-prediction mode for the block to the entropy encoding unit56. The entropy encoding unit56may encode the information indicating the selected intra-prediction mode in a bitstream.

After the prediction processing unit41determines the predictive block for the current video block via either inter prediction or intra prediction, the summer50forms a residual block by subtracting the predictive block from the current video block. The residual video data in the residual block may be included in one or more TUs and is provided to the transform processing unit52. The transform processing unit52transforms the residual video data into transform coefficients using a transform, such as a Discrete Cosine Transform (DCT) or a conceptually similar transform.

The transform processing unit52may send the resulting transform coefficients to the quantization unit54. The quantization unit54quantizes the transform coefficients to further reduce the bit rate. The quantization process may also reduce the bit depth associated with some or all of the coefficients. The degree of quantization may be modified by adjusting a quantization parameter. In some examples, the quantization unit54may then perform a scan of a matrix including the quantized transform coefficients. Alternatively, the entropy encoding unit56may perform the scan.

Following quantization, the entropy encoding unit56may use an entropy encoding technique to encode the quantized transform coefficients into a video bitstream, e.g., using Context Adaptive Variable Length Coding (CAVLC), Context Adaptive Binary Arithmetic Coding (CABAC), Syntax-based context-adaptive Binary Arithmetic Coding (SBAC), Probability Interval Partitioning Entropy (PIPE) coding, or another entropy encoding methodology or technique. The encoded bitstream may then be transmitted to the video decoder30as shown inFIG.1or archived in the storage device32as shown inFIG.1for later transmission to or retrieval by the video decoder30. The entropy encoding unit56may also use an entropy encoding technique to encode the motion vectors and the other syntax elements for the current video frame being coded.

The inverse quantization unit58and the inverse transform processing unit60apply inverse quantization and inverse transformation, respectively, to reconstruct the residual block in the pixel domain for generating a reference block for prediction of other video blocks. A reconstructed residual block may be generated thereof. As noted above, the motion compensation unit44may generate a motion compensated predictive block from one or more reference blocks of the frames stored in the DPB64. The motion compensation unit44may also apply one or more interpolation filters to the predictive block to calculate sub-integer pixel values for use in motion estimation.

The summer62adds the reconstructed residual block to the motion compensated predictive block produced by the motion compensation unit44to produce a reference block for storage in the DPB64. The reference block may then be used by the intra BC unit48, the motion estimation unit42, and the motion compensation unit44as a predictive block to inter predict another video block in a subsequent video frame.

FIG.3is a block diagram illustrating an exemplary video decoder30in accordance with some implementations of the present application. The video decoder30includes a video data memory79, an entropy decoding unit80, a prediction processing unit81, an inverse quantization unit86, an inverse transform processing unit88, a summer90, and a DPB92. The prediction processing unit81further includes a motion compensation unit82, an intra prediction unit84, and an intra BC unit85. The video decoder30may perform a decoding process generally reciprocal to the encoding process described above with respect to the video encoder20in connection withFIG.2. For example, the motion compensation unit82may generate prediction data based on motion vectors received from the entropy decoding unit80, while the intra prediction unit84may generate prediction data based on intra-prediction mode indicators received from the entropy decoding unit80.

In some examples, a unit of the video decoder30may be tasked to perform the implementations of the present application. Also, in some examples, the implementations of the present disclosure may be divided among one or more of the units of the video decoder30. For example, the intra BC unit85may perform the implementations of the present application, alone, or in combination with other units of the video decoder30, such as the motion compensation unit82, the intra prediction unit84, and the entropy decoding unit80. In some examples, the video decoder30may not include the intra BC unit85and the functionality of intra BC unit85may be performed by other components of the prediction processing unit81, such as the motion compensation unit82.

The video data memory79may store video data, such as an encoded video bitstream, to be decoded by the other components of the video decoder30. The video data stored in the video data memory79may be obtained, for example, from the storage device32, from a local video source, such as a camera, via wired or wireless network communication of video data, or by accessing physical data storage media (e.g., a flash drive or hard disk). The video data memory79may include a Coded Picture Buffer (CPB) that stores encoded video data from an encoded video bitstream. The DPB92of the video decoder30stores reference video data for use in decoding video data by the video decoder30(e.g., in intra or inter predictive coding modes). The video data memory79and the DPB92may be formed by any of a variety of memory devices, such as dynamic random access memory (DRAM), including Synchronous DRAM (SDRAM), Magneto-resistive RAM (MRAM), Resistive RAM (RRAM), or other types of memory devices. For illustrative purpose, the video data memory79and the DPB92are depicted as two distinct components of the video decoder30inFIG.3. But it will be apparent to one skilled in the art that the video data memory79and the DPB92may be provided by the same memory device or separate memory devices. In some examples, the video data memory79may be on-chip with other components of the video decoder30, or off-chip relative to those components.

During the decoding process, the video decoder30receives an encoded video bitstream that represents video blocks of an encoded video frame and associated syntax elements. The video decoder30may receive the syntax elements at the video frame level and/or the video block level. The entropy decoding unit80of the video decoder30may use an entropy decoding technique to decode the bitstream to obtain quantized coefficients, motion vectors or intra-prediction mode indicators, and other syntax elements. The entropy decoding unit80then forwards the motion vectors or intra-prediction mode indicators and other syntax elements to the prediction processing unit81.

When the video frame is coded as an intra predictive coded (e.g., I) frame or for intra coded predictive blocks in other types of frames, the intra prediction unit84of the prediction processing unit81may generate prediction data for a video block of the current video frame based on a signaled intra prediction mode and reference data from previously decoded blocks of the current frame.

When the video frame is coded as an inter-predictive coded (i.e., B or P) frame, the motion compensation unit82of the prediction processing unit81produces one or more predictive blocks for a video block of the current video frame based on the motion vectors and other syntax elements received from the entropy decoding unit80. Each of the predictive blocks may be produced from a reference frame within one of the reference frame lists. The video decoder30may construct the reference frame lists, e.g., List 0 and List 1, using default construction techniques based on reference frames stored in the DPB92.

In some examples, when the video block is coded according to the intra BC mode described herein, the intra BC unit85of the prediction processing unit81produces predictive blocks for the current video block based on block vectors and other syntax elements received from the entropy decoding unit80. The predictive blocks may be within a reconstructed region of the same picture as the current video block processed by the video encoder20.

The motion compensation unit82and/or the intra BC unit85determines prediction information for a video block of the current video frame by parsing the motion vectors and other syntax elements, and then uses the prediction information to produce the predictive blocks for the current video block being decoded. For example, the motion compensation unit82uses some of the received syntax elements to determine a prediction mode (e.g., intra or inter prediction) used to code video blocks of the video frame, an inter prediction frame type (e.g., B or P), construction information for one or more of the reference frame lists for the frame, motion vectors for each inter predictive encoded video block of the frame, inter prediction status for each inter predictive coded video block of the frame, and other information to decode the video blocks in the current video frame.

Similarly, the intra BC unit85may use some of the received syntax elements, e.g., a flag, to determine that the current video block was predicted using the intra BC mode, construction information of which video blocks of the frame are within the reconstructed region and should be stored in the DPB92, block vectors for each intra BC predicted video block of the frame, intra BC prediction status for each intra BC predicted video block of the frame, and other information to decode the video blocks in the current video frame.

The motion compensation unit82may also perform interpolation using the interpolation filters as used by the video encoder20during encoding of the video blocks to calculate interpolated values for sub-integer pixels of reference blocks. In this case, the motion compensation unit82may determine the interpolation filters used by the video encoder20from the received syntax elements and use the interpolation filters to produce predictive blocks.

The inverse quantization unit86inversely quantizes the quantized transform coefficients provided in the bitstream and decoded by the entropy decoding unit80using the same quantization parameter calculated by the video encoder20for each video block in the video frame to determine a degree of quantization. The inverse transform processing unit88applies an inverse transform, e.g., an inverse DCT, an inverse integer transform, or a conceptually similar inverse transform process, to the transform coefficients in order to reconstruct the residual blocks in the pixel domain.

After the motion compensation unit82or the intra BC unit85generates the predictive block for the current video block based on the vectors and other syntax elements, the summer90reconstructs a decoded video block for the current video block by summing the residual block from the inverse transform processing unit88and a corresponding predictive block generated by the motion compensation unit82and the intra BC unit85. The decoded video block may also be referred to as a reconstructed block for the current video block. An in-loop filter91such as a deblocking filter, SAO filter, and/or ALF may be positioned between the summer90and the DPB92to further process the decoded video block. In some examples, the in-loop filter91may be omitted, and the decoded video block may be directly provided by the summer90to the DPB92. The decoded video blocks in a given frame are then stored in the DPB92, which stores reference frames used for subsequent motion compensation of next video blocks. The DPB92, or a memory device separate from the DPB92, may also store decoded video for later presentation on a display device, such as the display device34ofFIG.1.

In a typical video coding process (e.g., including a video encoding process and a video decoding process), a video sequence typically includes an ordered set of frames or pictures. Each frame may include three sample arrays, denoted SL, SCb, and SCr. SL is a two-dimensional array of luma samples. SCb is a two-dimensional array of Cb chroma samples. SCr is a two-dimensional array of Cr chroma samples. In other instances, a frame may be monochrome and therefore includes only one two-dimensional array of luma samples.

As shown inFIG.4A, the video encoder20(or more specifically the partition unit45) generates an encoded representation of a frame by first partitioning the frame into a set of CTUs. A video frame may include an integer number of CTUs arranged consecutively in a raster scan order from left to right and from top to bottom. Each CTU is a largest logical coding unit and the width and height of the CTU are signaled by the video encoder20in a sequence parameter set, such that all the CTUs in a video sequence have the same size being one of 128×128, 64×64, 32×32, and 16×16. But it should be noted that a CTU in the present disclosure is not necessarily limited to a particular size. As shown inFIG.4B, each CTU may include one CTB of luma samples, two corresponding coding tree blocks of chroma samples, and syntax elements used to code the samples of the coding tree blocks. The syntax elements describe properties of different types of units of a coded block of pixels and how the video sequence can be reconstructed at the video decoder30, including inter or intra prediction, intra prediction mode, motion vectors, and other parameters. In monochrome pictures or pictures having three separate color planes, a CTU may include a single coding tree block and syntax elements used to code the samples of the coding tree block. A coding tree block may be an N×N block of samples.

To achieve a better performance, the video encoder20may recursively perform tree partitioning such as binary-tree partitioning, ternary-tree partitioning, quad-tree partitioning or a combination thereof on the coding tree blocks of the CTU and divide the CTU into smaller CUs. As depicted inFIG.4C, the 64×64 CTU400is first divided into four smaller CUs, each having a block size of 32×32. Among the four smaller CUs, CU410and CU420are each divided into four CUs of 16×16 by block size. The two 16×16 CUs430and440are each further divided into four CUs of 8×8 by block size.FIG.4Ddepicts a quad-tree data structure illustrating the end result of the partition process of the CTU400as depicted inFIG.4C, each leaf node of the quad-tree corresponding to one CU of a respective size ranging from 32×32 to 8×8. Like the CTU depicted inFIG.4B, each CU may include a CB of luma samples and two corresponding coding blocks of chroma samples of a frame of the same size, and syntax elements used to code the samples of the coding blocks. In monochrome pictures or pictures having three separate colour planes, a CU may include a single coding block and syntax structures used to code the samples of the coding block. It should be noted that the quad-tree partitioning depicted inFIGS.4C and4Dis only for illustrative purposes and one CTU can be split into CUs to adapt to varying local characteristics based on quad/ternary/binary-tree partitions. In the multi-type tree structure, one CTU is partitioned by a quad-tree structure and each quad-tree leaf CU can be further partitioned by a binary and ternary tree structure. As shown inFIG.4E, there are multiple possible partitioning types of a coding block having a width W and a height H, i.e., quaternary partitioning, vertical binary partitioning, horizontal binary partitioning, vertical ternary partitioning, vertical extended ternary partitioning, horizontal ternary partitioning, and horizontal extended ternary partitioning.

In some implementations, the video encoder20may further partition a coding block of a CU into one or more M×N PBs. A PB may include a rectangular (square or non-square) block of samples on which the same prediction, inter or intra, is applied. A PU of a CU may include a PB of luma samples, two corresponding PBs of chroma samples, and syntax elements used to predict the PBs. In monochrome pictures or pictures having three separate color planes, a PU may include a single PB and syntax structures used to predict the PB. The video encoder20may generate predictive luma, Cb, and Cr blocks for luma, Cb, and Cr PBs of each PU of the CU.

The video encoder20may use intra prediction or inter prediction to generate the predictive blocks for a PU. If the video encoder20uses intra prediction to generate the predictive blocks of a PU, the video encoder20may generate the predictive blocks of the PU based on decoded samples of the frame associated with the PU. If the video encoder20uses inter prediction to generate the predictive blocks of a PU, the video encoder20may generate the predictive blocks of the PU based on decoded samples of one or more frames other than the frame associated with the PU.

Furthermore, as illustrated inFIG.4C, the video encoder20may use quad-tree partitioning to decompose the luma, Cb, and Cr residual blocks of a CU into one or more luma, Cb, and Cr transform blocks respectively. A transform block may include a rectangular (square or non-square) block of samples on which the same transform is applied. A TU of a CU may include a transform block of luma samples, two corresponding transform blocks of chroma samples, and syntax elements used to transform the transform block samples. Thus, each TU of a CU may be associated with a luma transform block, a Cb transform block, and a Cr transform block. In some examples, the luma transform block associated with the TU may be a sub-block of the CU's luma residual block. The Cb transform block may be a sub-block of the CU's Cb residual block. The Cr transform block may be a sub-block of the CU's Cr residual block. In monochrome pictures or pictures having three separate color planes, a TU may include a single transform block and syntax structures used to transform the samples of the transform block.

The video encoder20may apply one or more transforms to a luma transform block of a TU to generate a luma coefficient block for the TU. A coefficient block may be a two-dimensional array of transform coefficients. A transform coefficient may be a scalar quantity. The video encoder20may apply one or more transforms to a Cb transform block of a TU to generate a Cb coefficient block for the TU. The video encoder20may apply one or more transforms to a Cr transform block of a TU to generate a Cr coefficient block for the TU.

After generating a coefficient block (e.g., a luma coefficient block, a Cb coefficient block, or a Cr coefficient block), the video encoder20may quantize the coefficient block. Quantization generally refers to a process in which transform coefficients are quantized to possibly reduce the amount of data used to represent the transform coefficients, providing further compression. After the video encoder20quantizes a coefficient block, the video encoder20may apply an entropy encoding technique to encode syntax elements indicating the quantized transform coefficients. For example, the video encoder20may perform CABAC on the syntax elements indicating the quantized transform coefficients. Finally, the video encoder20may output a bitstream that includes a sequence of bits that form a representation of coded frames and associated data, which is either saved in the storage device32or transmitted to the destination device14.

After receiving a bitstream generated by the video encoder20, the video decoder30may parse the bitstream to obtain syntax elements from the bitstream. The video decoder30may reconstruct the frames of the video data based at least in part on the syntax elements obtained from the bitstream. The process of reconstructing the video data is generally reciprocal to the encoding process performed by the video encoder20. For example, the video decoder30may perform inverse transforms on the coefficient blocks associated with TUs of a current CU to reconstruct residual blocks associated with the TUs of the current CU. The video decoder30also reconstructs the coding blocks of the current CU by adding the samples of the predictive blocks for PUs of the current CU to corresponding samples of the transform blocks of the TUs of the current CU. After reconstructing the coding blocks for each CU of a frame, video decoder30may reconstruct the frame.

As noted above, video coding achieves video compression using primarily two modes, i.e., intra-frame prediction (or intra-prediction) and inter-frame prediction (or inter-prediction). It is noted that intra block copy (IBC) could be regarded as either intra-frame prediction or a third mode. Between the two modes, inter-frame prediction contributes more to the coding efficiency than intra-frame prediction because of the use of motion vectors for predicting a current video block from a reference video block.

But with the ever-improving video data capturing technology and more refined video block size for preserving details in the video data, the amount of data required for representing motion vectors for a current frame also increases substantially. One way of overcoming this challenge is to benefit from the fact that not only a group of neighboring CUs in both the spatial and temporal domains have similar video data for predicting purpose but the motion vectors between these neighboring CUs are also similar. Therefore, it is possible to use the motion information of spatially neighboring CUs and/or temporally co-located CUs as an approximation of the motion information (e.g., motion vector) of a current CU by exploring their spatial and temporal correlation, which is also referred to as “Motion Vector Predictor (MVP)” of the current CU.

Instead of encoding an actual motion vector of the current CU into the video bitstream (e.g., the actual motion vector being determined by the motion estimation unit42as described above in connection withFIG.2), the motion vector predictor of the current CU is subtracted from the actual motion vector of the current CU to produce a Motion Vector Difference (MVD) for the current CU. By doing so, there is no need to encode the motion vector determined by the motion estimation unit42for each CU of a frame into the video bitstream, and the amount of data used for representing motion information in the video bitstream can be significantly decreased.

Like the process of choosing a predictive block in a reference frame during inter-frame prediction of a code block, a set of rules can be adopted by both the video encoder20and the video decoder30for constructing a motion vector candidate list (also known as a “merge list”) for a current CU using those potential candidate motion vectors associated with spatially neighboring CUs and/or temporally co-located CUs of the current CU and then selecting one member from the motion vector candidate list as a motion vector predictor for the current CU. By doing so, there is no need to transmit the motion vector candidate list itself from the video encoder20to the video decoder30, and an index of the selected motion vector predictor within the motion vector candidate list is sufficient for the video encoder20and the video decoder30to use the same motion vector predictor within the motion vector candidate list for encoding and decoding the current CU. Thus, only the index of the selected motion vector predictor needs to be sent from the video encoder20to the video decoder30.

FIG.5Aillustrates exemplary decoder side motion vector refinement (DMVR) in accordance with some implementations of the present disclosure. To increase the accuracy of the motion vectors (MVs) of a merge mode, a bilateral matching (BM) based decoder side motion vector refinement is applied in VVC. In a bi-prediction scheme, refined MVs are searched around initial MVs in a first reference frame list (List 0) or a second reference frame list (List 1). Then, bilateral matching can be used to calculate a distortion (e.g., a distance) between two reference blocks that are in the reference frame lists L0 and L1, respectively.

For example, as illustrated inFIG.5A, an initial MV pair for a video block502in a video frame is denoted as (MV0, MV1), and a candidate MV pair for video block502is denoted as (MV0′, MV1′). A first reference block504from a first reference frame in List 0 and a second reference block506from a second reference frame in List 1 can be determined for video block502based on the candidate MV pair (MV0′, MV1′). Then, a matching cost (e.g., an SAD) between first reference block504and second reference block506for the candidate MV pair (MV0′, MV1′) can be determined. By performing similar operations, a plurality of matching costs for all the candidate MV pairs around the initial MV pair can be calculated, respectively. As a result, a candidate MV pair with a minimal matching cost among the plurality of matching costs can be selected to be a refined MV pair for video block502and used to generate corresponding predictive blocks for video block502. The refined MV pair can be used to generate the inter prediction samples, and can also be used in temporal motion vector prediction for coding future pictures.

In DMVR, the search points for the candidate MV pairs are surrounding the initial MV pair, and corresponding MV offsets follow an MV difference mirroring rule. For example, each candidate MV pair follows the following two equations:

In the above equations (1) and (2), MV_offset (e.g., MVdiffinFIG.5A) represents a refinement offset between an initial MV and a candidate MV in the first reference frame, whereas a refinement offset between an initial MV and a candidate MV in the second reference frame is −MV_offset (e.g., −MVdiffinFIG.5A). A refinement search range is two integer luma samples from the initial MV. The searching process may include an integer sample offset search stage and a fractional sample refinement stage.

FIG.5Billustrates a template matching (TM) technique performed on a search area around an initial motion vector in accordance with some implementations of the present disclosure. The template matching technique is a decoder-side MV derivation method configured to refine motion information of a current video block (e.g., a current CU) by finding the closest match between a template in a current video frame and a reference region in a reference frame. For example, as illustrated inFIG.5B, a template can include a top neighboring block and/or a left neighbouring block of the current CU in the current video frame. A reference region of the template may have the same size as the template and may include a first reference block and/or a second reference block determined by a motion vector candidate from a reference frame. For example, a reference region shown inFIG.5Bincludes a first reference block520A and/or a second reference block520B determined by an initial motion vector (denoted as initial MV) of the current CU from the reference frame. The motion vector candidate can be within a [−8, +8]-pel search range (e.g., a refined motion vector can be searched around the initial motion vector of the current CU within a [−8, +8]-pel search range). The template matching technique in JVET-J0021 is used with the following modifications: (a) a search step size is determined based on an adaptive motion vector resolution (AMVR) mode; and (b) the template matching technique can be cascaded with a bilateral matching process in merge modes.

In an advanced motion vector prediction (AMVP) mode, a motion vector predictor (MVP) candidate can be determined based on a template matching error, such that the MVP candidate which has the minimum difference between the template and a corresponding reference region can be selected. Then, the template matching technique can be performed for this MVP candidate for MV refinement. For example, the template matching technique can refine this MVP candidate by starting from full-pel MVD precision (or 4-pel for 4-pel AMVR mode) within a [−8, +8]-pel search range using an iterative diamond search. The MVP candidate may be further refined by using cross search with full-pel MVD precision (or 4-pel for 4-pel AMVR mode), followed sequentially by half-pel and quarter-pel ones depending on the AMVR mode as specified in the following Table 1. This search process ensures that the MVP candidate keeps the same MV precision as indicated by the AMVR mode after the template matching process.

In the merge mode, a similar search method can be applied to a merge candidate indicated by a merge index. As Table 1 shows, template matching may perform all the way down to ⅛-pel MVD precision or skipping those beyond half-pel MVD precision, depending on whether an alternative interpolation filter is used according to merged motion information. In some examples, the alternative interpolation filter is used when AMVR is of half-pel mode. Besides, when a template matching mode is enabled, the template matching may work as an independent process or an extra MV refinement process between block-based and subblock-based bilateral matching methods, depending on whether the bilateral matching can be enabled or not according to its enabling condition check.

Consistent with some implementations of the present disclosure, coding efficiency of inter-prediction can be improved from various aspects. In one aspect, the accuracy of inter-prediction can be improved with more advanced prediction modes, such as an affine motion model, a combine intra and inter prediction, a geometry partitioning mode, and so on. In another aspect, the motion information (e.g., especially motion vectors) can be refined at the decoder side without signaling additional overheads. This kind of improvement profits from the template matching technique and the bilateral matching technique. In yet another aspect, more efficient coding methods for the motion information can be utilized. For example, advanced motion vector prediction techniques (such as Subblock-based Temporal Motion Vector Prediction (SbTMVP) and History-based Motion Vector Prediction (HMVP) techniques) can reduce the overhead of motion vectors. Also, the AMVR technique can achieve a better trade-off between motion vector accuracy and motion compensation efficiency by applying different motion vector resolutions for different CUs.

Although the motion information can be coded with better predictors in the advanced motion vector prediction techniques, there are still some syntax elements needed to be signaled, like MVDs and reference indices. However, coding of the MVDs and the reference indices are less investigated in existing technologies. Since the motion vectors can be refined at the decoder side using DMVR techniques, it is also appealing to predict the MVDs and/or the reference indices at the decoder side with the template matching technique or the bilateral matching technique.

Consistent with some implementations of the present disclosure, a video processing method and apparatus are disclosed herein for decoder side motion information prediction with the template or bilateral matching technique, so that one or more motion related parameters for a video block in a video frame of a video can be derived on the decoder side. By way of examples, the one or more motion related parameters may include one or more reference indices, one or more MVDs for the video block, and/or any other motion related parameters. By exploiting the template matching technique or the bilateral matching technique, the video processing method and apparatus disclosed herein can reduce the signaling overhead of the one or more motion related parameters. Therefore, the coding efficiency of the motion information can be improved.

For example, with respect to the merge mode, only a merge flag and a merge index need to be signaled. As a result, less bits are signaled in the merge mode with the sacrificing of prediction quality when compared with existing designs of the AMVP mode. On the contrary, in the existing designs of the AMVP mode, various parameters are needed to be signaled for each video block, including an inter prediction direction (e.g., uni-prediction or bi-prediction), an AMVP index used to identify a motion vector predictor, one or more reference indices used to identify one or more reference frames, and one or more MVDs. However, the video processing method and apparatus disclosed herein can save the bits produced from the signaling of the one or more reference indices and/or the one or more MVDs by deriving or predicting the one or more reference indices and/or the one or more MVDs on the decoder side.

Besides, the video processing method and apparatus disclosed herein assume that samples in a current video block (e.g., a current prediction unit (PU)) share similar motion information with samples of a neighboring block. That is, the more accurate the derived motion information is, the smaller cost of the template or bilateral matching technique has.

In some implementations, the video processing method and apparatus disclosed herein may perform an MVD prediction on the decoder side using a coding matching technique. The coding matching technique can be the template matching technique or the bilateral matching technique. Depending on the inter prediction direction of the video block, either the template matching technique or the bilateral matching technique can be selected to perform the MVD prediction. For example, when the video block is coded with uni-prediction using the AMVP mode, the template matching technique can be applied to derive an MVD for the video block as described below in more details. In another example, when the video block is coded with bi-prediction using the AMVP mode, the bilateral matching technique disclosed herein can be applied to derive one or more MVDs for the video block as described below in more details.

In some implementations, the video processing method and apparatus disclosed herein may perform a reference index derivation on the decoder side, such that the one or more reference indices associated with the video block do not need to be signaled to the video decoder. Depending on the inter prediction direction of the video block, either the template matching technique or the bilateral matching technique can be selected to perform the reference index derivation. For example, when the video block is coded with uni-prediction using the AMVP mode, the template matching technique disclosed herein can be applied to derive a reference index for the video block as described below in more detail. In another example, when the video block is coded with bi-prediction using the AMVP mode, the bilateral matching technique disclosed herein can be applied to derive one or more reference indices for the video block as described below in more detail.

FIG.6Ais a block diagram illustrating an exemplary encoder side coding process600in accordance with some implementations of the present disclosure. In some implementations, encoder side coding process600can be performed by prediction processing unit41of video encoder20. In some implementations, encoder side coding process600may be performed by a processor (e.g., a processor1320as shown inFIG.13) on the encoder side. For illustration purpose only, the following description ofFIG.6Ais provided with respect to the processor on the encoder side. By the execution of encoder side coding process600, one or more motion related parameters associated with a video block do not need to be signaled to video decoder30, such that the one or more motion related parameters can be derived on the decoder side. For illustration purpose only,FIG.6Ais described herein by taking one or more MVDs and/or one or more reference indices as examples of the one or more motion related parameters. It is contemplated that the description provided herein is also applied to other examples of the one or more motion related parameters, which is not limited herein. In some implementations, encoder side coding process600may include an MVD coding602and a syntax element generation608.

In inter-prediction, a motion vector is used to indicate a relative location of a reference block in a reference frame for the video block in the current video frame. To improve the coding efficiency of the motion vector, the AMVP technique can be utilized to indicate a motion vector predictor for the motion vector with an AMVP index. Then, an MVD can be calculated to be a difference between the motion vector and the motion vector predictor (e.g., MVD=the motion vector−the motion vector predictor). In an existing design of the AMVP technique, the AMVP index and the MVD (rather than the motion vector) are signaled from video encoder20to video decoder30.

In the VVC standard and ECM, the MVD is coded by: (a) dividing the MVD into two parts including a sign of the MVD (denoted as a syntax element “mvd_sign_flag”) and an absolute value of the MVD (denoted as a syntax element “abs_mvd_minus2”); and (b) coding the sign of the MVD and the absolute value of the MVD separately. The sign of MVD is coded with a bypass mode while the absolute value of MVD can be coded as described in the following Table 2.

It is noted that, in the existing design of the AMVP mode, if the MVD is greater than 1, the syntax element “abs_mvd_minus2” for the absolute value of the MVD is signaled with the Exponential-Golomb (EG) code. For each bin of “abs_mvd_minus2,” the bypass mode is utilized to encode the bin, whereas the bypass mode is usually less effective. Consistent with some implementations of the present disclosure, the coding efficiency of the syntax element “abs_mvd_minus2” for the absolute value of the MVD may be improved by utilizing an efficient binarization method and context modeling described below in more detail.

In ECM, template matching is utilized to improve the coding efficiency of the merge mode and the motion vector prediction. For example, template matching is utilized to reorder the merge candidates and the AMVP candidates. Besides, in VVC, bilateral matching is utilized in the DMVR technique to refine the motion vectors in bi-prediction. Inspired by the above mentioned techniques, MVD coding602disclosed herein is applied to predict the absolute value of the MVD (abs_mvd_minus2) through a coding matching technique such as the template or bilateral matching technique. To achieve the prediction of the absolute value of the MVD through the coding matching technique, (a) a binarization method of the absolute value of the MVD (abs_mvd_minus2) and (b) a splitting of a bit plane of the absolute value of the MVD on the encoder side are disclosed herein. For example, MVD coding602described herein may include an absolute value binarization604and a bit plane splitting606for the MVD associated with the video block.

To begin with MVD coding602for the video block, the processor on the encoder side may perform absolute value binarization604to binarize the absolute value of the MVD into a bit plane. In some implementations, the bit plane of the absolute value (abs_mvd_minus2) can be a direct binary representation of the absolute value rather than an EG code corresponding to the absolute value. The absolute value (abs_mvd_minus2) can be represented with a maximum of Q bits, where Q is a positive integer. For example, as illustrated inFIG.7, a binary representation of abs_mvd_minus2=29 is (0000, . . . , 0000, 0001, 1101) since 29=1×24+1×23+1×22+0×21+1×20.

Next, the processor on the encoder side may perform bit plane splitting606to divide the bit plane of the absolute value into a set of most significant bins (MSBs), a set of derived most significant bins (d-MSBs), and a set of least significant bins (LSBs). For example, as illustrated inFIG.7, the bit plane of abs_mvd_minus2=29 is split into a set of MSBs (0000, . . . , 0000), a set of d-MSBs (0001), and a set of LSBs (1101).

Rather than transmitting the absolute value of the MVD to the video decoder directly, the processor may generate a reduced absolute value (denoted as “reduced_abs_mvd_minus2”) based on the splitting of the absolute value and then transmit the reduced absolute value to video decoder30. For example, the processor may generate the reduced absolute value by setting the set of d-MSBs to be all zeros. The reduced absolute value can be coded with EG code directly and transmitted to video decoder30. That is, the set of d-MSBs may not be transmitted to video decoder30, and only the set of MSBs and the set of LSBs may be signaled to video decoder30through the bitstream. Since the reduced absolute value is smaller than the absolute value, less bits are used to transmit the reduced absolute value so that the signaling overhead can be reduced. In some examples, the set of MSBs are all zeros. In this case, only the set of LSBs are transmitted to video decoder30, and the signaling overhead can be further reduced. On the decoder side, the set of d-MSBs can be derived as described below in more detail with reference toFIG.6B, so that the set of d-MSBs derived on the decoder side and the reduced absolute value received from video encoder20can be used to reconstruct the absolute value of the MVD on the decoder side.

Some considerations regarding the splitting of the bit plane are disclosed herein. For example, as described below with reference toFIG.6B, when deriving the set of d-MSBs on the decoder side, the number of motion vector candidates to be checked on the decoder side is exponential to a length of the d-MSBs. Therefore, if the length of the d-MSBs increases, more bits can be saved in the signaling but more motion vector candidates need to be checked on the decoder side, which may increase the computation complexity on the decoder side. In another example, a position where the d-MSBs start in the bit plane has an influence on the prediction accuracy of a matching cost when checking a particular motion vector candidate. If the d-MSBs locates at lower-order bits in the bit plane, the difference on the matching costs among the motion vector candidates can be smaller, which can make it more difficult to discriminate the motion vector candidates, and vice versa. In some implementations, the length of the d-MSBs and the position where the d-MSBs start in the bit plane can be set to be a fixed pattern (e.g., a fixed length, a fixed position, etc.). In some other implementations, the length of the d-MSBs and the position where the d-MSBs start in the bit plane can be indicated in the slice header as described in the following Table

With respect to syntax element generation608, the processor on the encoder side may generate one or more syntax elements and may signal the one or more syntax elements to video decoder30, so that the one or more syntax elements can be used for performing MVD prediction and/or reference index derivation on the decoder side.

For example, a syntax element “mvd_derivation_flag” can be generated and signaled for each video block to indicate whether MVD prediction is applied to the video block. If “mvd_derivation_flag” is true, then the MVD prediction is applied to the video block, leading to one or more MVDs of the video block to be derived on the decoder side. For example, for each MVD to be derived, a set of d-MSBs for an absolute value “abs_mvd_minus2” of the MVD is to be derived on the decoder side (rather than being signaled to video decoder30). If “mvd_derivation_flag” is false, then the MVD prediction is not applied to the video block. In this case, the one or more MVDs of the video block are not derived on the decoder side. For example, for each MVD, the absolute value “abs_mvd_minus2” of the MVD is coded with EG code and signaled to video decoder30. The following Table 4 is provided to describe some exemplary syntax elements of the MVD prediction disclosed herein.

In another example, a syntax element “derive_ref_idx_flag” can be generated and signaled for each video block to indicate whether reference index derivation is applied to the video block. If “derive_ref_idx_flag” is true, then the reference index derivation is applied. In this case, one or more reference indices associated with the video block are derived on the decoder side (rather than being signaled to video decoder30). If “derive_ref_idx_flag” is false, then the reference index derivation is not applied to the video block. In this case, the one or more reference indices associated with the video block are signaled to video decoder30. The following Table 5 is provided to describe some exemplary syntax elements of the reference index derivation.

The italicized portions of the above table indicate that the portions are deleted.

FIG.6Bis a block diagram illustrating an exemplary decoder side derivation process610in accordance with some implementations of the present disclosure. In some implementations, decoder side derivation process610can be performed by prediction processing unit81of video decoder30. In some implementations, decoder side derivation process610may be performed by a processor (e.g., a processor1320as shown inFIG.13) at the decoder side. For illustration purpose only, the following description ofFIG.6Bis provided with respect to the processor. In some implementations, decoder side derivation process610may include at least one of: (a) a syntax element analysis612; or (b) a motion related parameter derivation614for determining one or more motion related parameters on the decoder side. In some examples, the one or more motion related parameters may include one or more MVDs and/or one or more reference indices for a video block from a video frame. Motion related parameter derivation614may include at least one of: (a) an MVD prediction618for deriving the one or more MVDs; or (b) a reference index derivation620for deriving the one or more reference indices.

With respect to syntax element analysis612, the processor on the decoder side may receive one or more syntax elements for the video block from video encoder20. The processor may determine whether one or more motion related parameters for the video block are signaled in a bitstream from video encoder20based on the one or more syntax elements. Responsive to determining that the one or more motion related parameters being signaled in the bitstream, the processor may obtain the one or more motion related parameters through the bitstream. Otherwise (e.g., responsive to determining that the one or more motion related parameters being not signaled in the bitstream), the processor may perform motion related parameter derivation614to determine the one or more motion related parameters using a coding matching technique. The coding matching technique can be a template matching technique or a bilateral matching technique, depending on whether the video block is coded with a uni-prediction scheme or a bi-prediction scheme.

For example, if a syntax element “mvd_derivation_flag” received from video encoder20is true, then one or more sets of d-MSBs for the one or more MVDs associated with the video block are not signaled in the bitstream. In this case, absolute values of the one or more MVDs (or, the one or more sets of d-MSBs) can be derived on the decoder side as described below in more detail. Otherwise (e.g., if the syntax element “mvd_derivation_flag” is false), the absolute values of the one or more MVDs (or, the one or more sets of d-MSBs) can be obtained through the bitstream.

In another example, if a syntax element “derive_ref_idx_flag” received from video encoder20is true, then one or more reference indices associated with the video block are not signaled in the bitstream. In this case, the one or more reference indices associated with the video block can be derived on the decoder side as described below in more detail. Otherwise (e.g., if the syntax element “derive_ref_idx_flag” is false), the one or more reference indices associated with the video block can be obtained through the bitstream.

An overview of motion related parameter derivation614is provided herein. Initially, the processor may determine a plurality of parameter candidates for the one or more motion related parameters based on syntax elements received through the bitstream. Each parameter candidate may include one or more values for the one or more motion related parameters, respectively. The processor may determine a plurality of matching costs associated with the plurality of parameter candidates, respectively. Then, the processor may derive the one or more motion related parameters based on a parameter candidate associated with a minimum matching cost among the plurality of matching costs.

In some implementations, the video block is coded using the uni-prediction scheme, and correspondingly, the processor may apply the template matching technique to determine the one or more motion related parameters. Specifically, the processor may apply the template matching technique to determine the plurality of matching costs associated with the plurality of parameter candidates, respectively. For example, the processor may determine a template for the video block from the video frame. An exemplary template is illustrated inFIG.8, which includes at least one of reconstructed samples located on a top region above the video block or reconstructed samples located on a left region of the video block. Then, for each parameter candidate from the plurality of parameter candidates, the processor may determine a reference region associated with the parameter candidate and determine a matching cost between the reference region and the template. As a result, the processor may determine a plurality of matching costs for the plurality of parameter candidates, respectively. The processor may derive the one or more motion related parameters based on a parameter candidate associated with the minimum matching cost among the plurality of matching costs.

For example, the one or more motion related parameters may include an MVD associated with the video block. An exemplary process to apply the template matching technique to determine the MVD is described below in more detail. In another example, the one or more motion related parameters may include a reference index associated with the video block. An exemplary process to apply the template matching technique to determine the reference index is described below in more detail.

In some other implementations, the video block is coded using the bi-prediction scheme, and correspondingly, the processor may apply the bilateral matching technique to determine the one or more motion related parameters. Specifically, the processor may apply the bilateral matching technique to determine the plurality of matching costs associated with the plurality of parameter candidates, respectively. For example, for each parameter candidate from the plurality of parameter candidates, the processor may derive one or more reference blocks associated with the parameter candidate and determine a matching cost for the parameter candidate based on the one or more reference blocks. As a result, the processor may determine a plurality of matching costs for the plurality of parameter candidates, respectively. The processor may derive the one or more motion related parameters based on a parameter candidate associated with the minimum matching cost among the plurality of matching costs.

For example, the one or more motion related parameters may include one or more MVDs associated with the video block. An exemplary process to apply the bilateral matching technique to determine the one or more MVDs is described below in more detail. In another example, the one or more motion related parameters may include one or more reference indices associated with the video block. An exemplary process to apply the bilateral matching technique to determine the one or more reference indices is described below in more detail.

It is noted that, in ECM, the template matching technique can be applied in the merge and AMVP candidate derivation. Therefore, MVD prediction618with the template matching technique is not enabled in these cases, and any existing coding method of the absolute value (abs_mvd_minus2) can still be applied. However, if the template matching technique is not enabled in the merge and AMVP candidate derivation, MVD prediction618with the template matching technique can be applied for the prediction of the MVD (e.g., for the prediction of a set of d-MSBs or an absolute value “abs_mvd_minus2” of the MVD).

In the following, MVD prediction618and reference index derivation620are described with respect to (a) a first exemplary case where the video block is coded using the uni-prediction scheme and (b) a second exemplary case where the video block is coded using the bi-prediction scheme. In the first exemplary case, the processor may perform MVD prediction618to determine an MVD for the video block using the template matching technique. To begin with MVD prediction618, the processor may determine a template for the video block from the video frame, which may include at least one of reconstructed samples located on a top region above the video block or reconstructed samples located on a left region of the video block.

Next, the processor may determine a plurality of MVD candidates for the video block (e.g., each MVD candidate being considered as an example of a parameter candidate described above). In some implementations, each MVD candidate may include an absolute value candidate of the MVD. The processor may determine a plurality of absolute value candidates for the MVD as the plurality of MVD candidates for the video block, respectively. Specifically, the processor may obtain a syntax element “sh_derived_msb_length” (shown in Table 3 above) from the bitstream, where the syntax element “sh_derived_msb_length” is used to indicate a length of a set of d-MSBs associated with a bit plane of an absolute value of the MVD. The processor may determine a plurality of potential combinations for the set of d-MSBs based on the length of the set of d-MSBs. Then, the processor may determine the plurality of absolute value candidates for the MVD based on (a) a set of MSBs received from video encoder20, (b) a set of LSBs received from video encoder20, and (c) the plurality of potential combinations of the set of d-MSBs, respectively. The set of MSBs and the set of LSBs may be obtained based on a syntax element “reduced_abs_mvd_minus2,” which indicates a reduced absolute value of the MVD and is received from video encoder20.

Then, for each MVD candidate (e.g., each absolute value candidate of the MVD), the processor may determine a motion vector candidate for the video block based on the MVD candidate, a sign of the MVD candidate, and a motion vector predictor for the video block. For example, the sign of MVD candidate can be the same as the sign of the MVD, which can be received through the bitstream from video encoder20. The motion vector predictor can be indicated by an AMVP index received through the bitstream from video encoder20. The processor may generate a motion vector candidate for the video block as follows: the motion vector candidate=(the sign of the MVD) (the absolute value candidate of the MVD)+the motion vector predictor.

Subsequently, for each MVD candidate, the processor may determine a reference region associated with the MVD candidate based on the template, a reference index of a reference frame for the video block, and the motion vector candidate corresponding to the MVD candidate. For example, the reference region associated with the MVD candidate may have the same size as the template, and may include one or more reference blocks determined from the reference frame based on the motion vector candidate. In some implementations, the reference index used to identify the reference frame can be received through the bitstream from video encoder20. In some other implementations, the reference index can be derived on the decoder side as described below in more detail.

Further, for each MVD candidate (e.g., each absolute value candidate of the MVD), the processor may determine a matching cost between the reference region corresponding to the MVD candidate and the template. For example, the matching cost can be a difference metric (e.g., a distance measurement) such as a Mean Square Error (MSE), an SAD, an SSD, etc., between the reference region and the template. As a result, a plurality of matching costs can be determined for the plurality of MVD candidates, respectively. For example, the processor may determine a plurality of matching costs for the plurality of absolute value candidates, respectively.

Then, the processor may derive the MVD for the video block based on an MVD candidate that is associated with the minimum matching cost among the plurality of matching costs. For example, the processor may derive the absolute value of the MVD to be an absolute value candidate of the MVD that is associated with the minimum matching cost among the plurality of matching costs. The processor may determine the MVD for the video block based on the derived absolute value of the MVD and the sign of the MVD received from video encoder20. In some implementations, the processor may further generate a motion vector for the video block to be a sum of the MVD derived on the decoder side and the motion vector predictor indicated by the AMVP index received from video encoder20.

For example, assuming that the set of MSBs and the set of LSBs received from video encoder20are (0000 . . . 0000) and (1101), respectively, and the set of d-MSBs to be derived includes 4 bins. 16 potential combinations for the set of d-MSBs, which includes all the possible combinations of the 4 bins, can be obtained as follows: (0000), (0001), (0010), (0011), (0100), (0101), (0110), (0111), (1000), (1001), (1010), (1011), (1100), (1101), (1110), and (1111). Therefore, 16 absolute value candidates (e.g., 16 possible values of the absolute value “abs_mvd_minus2”) can be obtained as follows: 13 (with a binarized form of 0000 . . . 0000, 0000, 1101), 29 (0000 . . . 0000, 0001, 1101), 45 (0000 . . . 0000, 0010, 1101), 61 (0000 . . . 0000, 0011, 1101), 77 (0000 . . . 0000, 0100, 1101), 93 (0000 . . . 0000, 0101, 1101), 109 (0000 . . . 0000, 0110, 1101), 125 (0000 . . . 0000, 0111, 1101), 141 (0000 . . . 0000, 1000, 1101), 157 (0000 . . . 0000, 1001, 1101), 173 (0000 . . . 0000, 1010, 1101), 189 (0000 . . . 0000, 1011, 1101), 205 (0000 . . . 0000, 1100, 1101), 221 (0000 . . . 0000, 1101, 1101), 237 (0000 . . . 0000, 1110, 1101), and 253 (0000 . . . 0000, 1111, 1101). Then, 16 motion vector candidates can be generated for the video block based on the 16 absolute value candidates, respectively, with each motion vector candidate corresponding to an absolute value candidate and calculated as follows: the motion vector candidate=(the sign of the MVD) (the corresponding absolute value candidate)+the motion vector predictor. For each motion vector candidate, a reference region of the template can be determined, and a distance between the reference region and the template can be calculated as a matching cost for the motion vector candidate. As a result, 16 matching costs can be obtained for the 16 motion vector candidates (also for the 16 absolute value candidates as well). An absolute value candidate with the smallest matching cost among the 16 matching costs can be selected as the absolute value for the MVD. That is, the set of d-MSBs can be determined from the absolute value candidate having the smallest matching cost. Then, the motion vector of the video block can be determined as follows: the motion vector of the video block=(the sign of the MVD) (the absolute value candidate with the minimal matching cost)+the motion vector predictor.

Also in the first exemplary case where the video block is coded using the uni-prediction scheme, the processor on the decoder side may perform reference index derivation620to determine a reference index for the video block using the template matching technique, so that the bits for signaling the reference index can be saved. It is contemplated that, given the same motion vector, different reference indices may indicate different reference regions for a template of the video block. Thus, a reference index which is associated with an optimal reference region (correspondingly, associated with a minimal matching cost) can be selected as the derived reference index for the video block.

To begin with reference index derivation620, the processor may determine a template for the video block from the video frame, which may include at least one of reconstructed samples located on a top region above the video block or reconstructed samples located on a left region of the video block. Next, the processor may determine a plurality of reference index candidates for the video block (e.g., each reference index candidate being considered as an example of a parameter candidate described above). For example, video encoder20and video decoder30may jointly pre-determine all the potential reference indices for each video block, and the plurality of reference index candidates can include all the potential reference indices for the video block.

The processor may also determine a motion vector for the video block based on an MVD of the video block and a motion vector predictor for the video block. For example, the MVD of the video block can be received through the bitstream from video encoder20. Alternatively, the MVD of the video block may be derived as described herein. The motion vector predictor can be indicated by an AMVP index received through the bitstream from video encoder20. The processor may generate a motion vector for the video block as follows: the motion vector=the MVD+the motion vector predictor.

Given the motion vector and the template for the video block, the processor may determine a respective reference region corresponding to each reference index candidate. For example, for each reference index candidate, the processor may determine a reference region based on the template, the motion vector of the video block, and the reference index candidate. That is, the reference region associated with the reference index candidate may have the same size as the template. The reference region may include one or more reference blocks from a reference frame identified by the reference index candidate, with the one or more reference blocks being determined based on the motion vector of the video block.

Further, for each reference index candidate, the processor may determine a matching cost between the reference region and the template. For example, the matching cost can be a difference metric such as an MSE, an SAD, an SSD, etc., between the reference region and the template. As a result, a plurality of matching costs can be determined for the plurality of reference index candidates, respectively. Subsequently, the processor may derive the reference index for the video block to be a reference index candidate that is associated with the minimum matching cost among the plurality of matching costs.

For example, assuming that there are N reference index candidates, including r0, r1, . . . , rN-1. Based on the motion vector and the template of the video block, a total of N reference regions of the template can be obtained for the N reference index candidates, respectively. A reference region which has the smallest matching cost (e.g., the smallest distance to the template) can be selected as an optimal reference region. A reference index candidate corresponding to the optimal reference region (also corresponding to the smallest matching cost) can be selected to be the reference index for the video block.

In the second exemplary case where the video block is coded using the bi-prediction scheme, the processor may perform MVD prediction618to determine one or more MVDs for the video block using the bilateral matching technique. It is contemplated that bilateral matching may include a process of determining motion vectors that result in the minimum difference between two matched reference blocks in two directions. This second exemplary case with respect to MVD prediction618is described below in a first exemplary sub-case and a second exemplary sub-case, respectively.

In the first exemplary sub-case of MVD prediction618under the bi-prediction scheme, the one or more MVDs to be derived on the decoder side may include a first MVD of a first motion vector to be derived on the decoder side for a first direction, whereas a second MVD of a second motion vector for a second direction may be signaled from video encoder20to video decoder30. The first MVD can be associated with a first reference frame list, and the second MVD can be associated with a second reference frame list. The first reference frame list can be List 0, and the second reference frame list can be List 1. Alternatively, the first reference frame list can be List 1, and the second reference frame list can be List 0.

For example, assuming that the first MVD of List 0 needs to be predicted on the decoder side, whereas the second MVD (e.g., an absolute value “abs_mvd_minus2” of the second MVD) of List 1 can be coded with EG code and received from video encoder20. Then, a first set of d-MSBs from an absolute value (“abs_mvd_minus2”) of the first MVD can be derived on the decoder side. All the potential values for the first set of d-MSBs can be checked with the bilateral matching technique, and a potential value of the first set of d-MSBs which leads to the minimum matching cost can be selected for the derivation of the first MVD on the decoder side.

Detailed operations for the first exemplary sub-case are described herein. Initially, the processor may determine a plurality of first MVD candidates for the first MVD (e.g., each first MVD candidate being considered as an example of a parameter candidate described above). For example, each first MVD candidate may include an absolute value candidate of the first MVD. The processor may determine a plurality of absolute value candidates for the first MVD as the plurality of first MVD candidates for the video block, respectively, by performing operations like those described above.

Then, for each first MVD candidate (e.g., each absolute value candidate of the first MVD), the processor may determine a first motion vector candidate for the video block based on the first MVD candidate, a sign of the first MVD candidate, and a first motion vector predictor for the video block. For example, the sign of the first MVD candidate can be the same as the sign of the first MVD, which can be received through the bitstream from video encoder20. The first motion vector predictor can be indicated by a first AMVP index received through the bitstream from video encoder20. The processor may generate a first motion vector candidate for the video block as follows: the first motion vector candidate=(the sign of the first MVD) (the absolute value candidate of the first MVD)+the first motion vector predictor.

Next, for each first MVD candidate, the processor may derive a first reference block based on the first motion vector candidate. For example, the processor may determine the first reference block from a first reference frame based on (a) the first motion vector candidate for the video block and (b) a first reference index used to identify the first reference frame in the first reference frame list. In some examples, the first reference index can be received from video encoder20. In some other examples, the first reference index can be derived as disclosed herein. Additionally, the processor may derive a second reference block from a second reference frame based on (a) a second motion vector for the video block and (b) a second reference index which is used to identify the second reference frame in the second reference frame list. The second motion vector can be determined based on the second MVD of the video block and a second motion vector predictor which are signaled from video encoder20. In some examples, the second reference index can be received from video encoder20. In some other examples, the second reference index can be derived as disclosed herein.

Further, for each first MVD candidate (e.g., each absolute value candidate of the first MVD), the processor may determine a matching cost based on the first reference block and the second reference block. For example, the matching cost can be a distance metric such as an MSE, an SAD, an SSD, etc., between the first and second reference blocks. As a result, a plurality of matching costs can be determined for the plurality of first MVD candidates, respectively. For example, a plurality of matching costs can be determined for the plurality of absolute value candidates of the first MVD by performing operations like those described above.

Subsequently, the processor may derive the first MVD for the video block based on a first MVD candidate associated with the minimum matching cost among the plurality of matching costs. For example, the processor may derive an absolute value of the first MVD to be an absolute value candidate of the first MVD that is associated with the minimum matching cost among the plurality of matching costs. The processor may determine the first MVD for the video block based on the absolute value of the first MVD and a sign of the first MVD received from video encoder20.

In some implementations, the processor may further generate the first motion vector for the video block to be a sum of the first MVD derived on the decoder side and the first motion vector predictor indicated by the first AMVP index received from video encoder20. For example, the first motion vector for the video block=the first MVD derived on the decoder side+the first motion vector predictor.

In the second exemplary sub-case of MVD prediction618under the bi-prediction scheme, the one or more MVDs to be derived on the decoder side may include a pair of MVDs, including (a) the first MVD for the first motion vector associated with the first reference frame list and (b) the second MVD for the second motion vector associated with the second reference frame list. That is, both the first MVD and the second MVD can be derived on the decoder side (e.g., the first and second MVDs can be predicted jointly on the decoder side). For example, both the first set of d-MSBs for the absolute value of the first MVD (denoted as d-MSBs_1) and a second set of d-MSBs for the absolute value of the second MVD (denoted as d-MSBs_2) can be derived jointly on the decoder side. All the potential values for the pair of the first set of d-MSBs and the second set of d-MSBs (d-MSBs_1, d-MSBs_2) can be checked with the bilateral matching technique, and a potential value for the pair (d-MSBs_1, d-MSBs_2) which leads to the minimum matching cost can be selected for the derivation of the first MVD and the second MVD on the decoder side. Detailed operations for the second exemplary sub-case are described herein. Initially, the processor may determine a plurality of pairs of first MVD candidates for the first MVD and second MVD candidates for the second MVD. Specifically, by performing operations like those described above, the processor may determine a plurality of first MVD candidates for the first MVD, respectively. The processor may also determine a plurality of second MVD candidates for the second MVD, respectively. The processor may determine a plurality of pairs of the first MVD candidates and the second MVD candidates, with each pair including a first MVD candidate and a second MVD candidate and being considered as an example of a parameter candidate described above.

For example, each first MVD candidate may include an absolute value candidate of the first MVD, and each second MVD candidate may include an absolute value candidate of the second MVD. By performing operations like those described above, the processor may determine a plurality of absolute value candidates for the first MVD and a plurality of absolute value candidates for the second MVD, respectively. The processor may determine a plurality of pairs of absolute value candidates of the first MVD and the second MVD, with each pair including an absolute value candidate of the first MVD and an absolute value candidate of the second MVD. In a further example, a first set of d-MSBs to be derived for the first MVD (d-MSBs_1) may include N1 bins, and a second set of d-MSBs to be derived for the second MVD (d-MSBs_2) may include N2 bins, where N1 and N2 are positive integers. Then, the plurality of pairs of absolute value candidates of the first MVD and the second MVD may include N1*N2 pairs, with each pair (e.g., a joint pair of d-MSBs (d-MSBs_1, d-MSBs_2)) including a first potential value for the first set of d-MSBs and a second potential value for the second set of d-MSBs.

Then, for each pair of the first MVD candidates and the second MVD candidates (e.g., each pair of the absolute value candidates of the first MVD and the second MVD), the processor may determine a first motion vector candidate for the video block based on the first MVD candidate in the pair, a sign of the first MVD candidate in the pair, and a first motion vector predictor for the video block. For example, the sign of the first MVD candidate can be the same as the sign of the first MVD, which can be received through the bitstream from video encoder20. The first motion vector predictor can be indicated by a first AMVP index received through the bitstream from video encoder20. The processor may generate the first motion vector candidate for the video block as follows: the first motion vector candidate=(the sign of the first MVD) (the absolute value candidate of the first MVD)+the first motion vector predictor. Also, the processor may determine a second motion vector candidate for the video block based on the second MVD candidate in the pair, a sign of the second MVD candidate in the pair, and a second motion vector predictor for the video block. For example, the sign of the second MVD candidate can be the same as the sign of the second MVD, which can be received through the bitstream from video encoder20. The second motion vector predictor can be indicated by a second AMVP index received through the bitstream from video encoder20. The processor may generate the second motion vector candidate for the video block as follows: the second motion vector candidate=(the sign of the second MVD) (the absolute value candidate of the second MVD)+the second motion vector predictor.

Next, for each pair of the first MVD candidates and the second MVD candidates, the processor may derive the first reference block and the second reference block associated with the first MVD candidate and the second MVD candidate in the pair, respectively. For example, the processor may determine the first reference block from a first reference frame based on (a) the first motion vector candidate determined based on the first MVD candidate and (b) a first reference index used to identify the first reference frame in the first reference frame list. The processor may also determine the second reference block from a second reference frame based on (a) the second motion vector candidate determined based on the second MVD candidate and (b) a second reference index used to identify the second reference frame in the second reference frame list. In some examples, the first and second reference indices can be received from video encoder20. In some other examples, the first and second reference indices can be derived as disclosed herein.

Further, for each pair of the first MVD candidates and the second MVD candidates (e.g., each pair of the absolute value candidates of the first MVD and the second MVD), the processor may determine a matching cost based on the first reference block and the second reference block. For example, the matching cost can be a distance metric such as an MSE, an SAD, an SSD, etc., between the first and second reference blocks. As a result, a plurality of matching costs can be determined for the plurality of pairs of the first MVD candidates and the second MVD candidates, respectively. For example, a plurality of matching costs can be determined for the plurality of pairs of absolute value candidates of the first MVD and the second MVD, respectively.

Subsequently, the processor may derive the first MVD and the second MVD for the video block based on a pair of the first MVD candidates and the second MVD candidates that is associated with the minimum matching cost among the plurality of matching costs. For example, the processor may derive an absolute value of the first MVD and an absolute value of the second MVD based on a corresponding pair of absolute value candidates of the first MVD and the second MVD that is associated with the minimum matching cost. The processor may determine the first MVD for the video block based on the absolute value of the first MVD derived on the decoder side and the sign of the first MVD received from video encoder20. The processor may also determine the second MVD for the video block based on the absolute value of the second MVD derived on the decoder side and the sign of the second MVD received from video encoder20.

In some implementations, the processor may further generate the first motion vector for the video block to be a sum of the first MVD derived on the decoder side and the first motion vector predictor indicated by the first AMVP index received from video encoder20. The processor may also generate the second motion vector for the video block to be a sum of the second MVD derived on the decoder side and the second motion vector predictor indicated by the second AMVP index received from video encoder20.

Additionally or alternatively, in the second exemplary case where the video block is coded using the bi-prediction scheme, the processor on the decoder side may perform reference index derivation620to determine one or more reference indices for the video block using the bilateral matching technique. The second exemplary case with respect to reference index derivation620is also described below in a first exemplary sub-case and a second exemplary sub-case, respectively.

In the first exemplary sub-case of reference index derivation620under the bi-prediction scheme, the one or more reference indices to be derived on the decoder side may include a first reference index used to identify a first reference frame in the first reference frame list, whereas a second reference index used to identify a second reference frame in the second reference frame list can be signaled from video encoder20. If symmetric MVD is used, a reference index of List 0 can be treated as the first reference index to be derived on the decoder side. In some implementations, the reference index of List 0 can be set as a default reference index to be derived. Alternatively, it can be indicated at an SPS or a slice header whether the reference index of List 0 or a reference index of List 1 is to be derived on the decoder side. Once the reference index to be derived on the decoder side is determined, it would not be signaled from video encoder20to video decoder30.

For example, assuming that the first reference index to be predicted on the decoder side is the reference index of List 0, whereas the second reference index which is the reference index of List 1 can be signaled to video decoder30. For each potential value of the first reference index, a first reference block can be obtained based on a first motion vector of the video block and the potential value of the first reference index. A second reference block can be obtained based on a second motion vector of the video block and the second reference index. A distance between the first and second reference blocks can be used as a matching cost for the potential value of the first reference index. As a result, a plurality of matching costs can be determined for a plurality of potential values for the first reference index, respectively. A potential value of the first reference index which leads to the minimum matching cost can be selected as a derived value for the first reference index on the decoder side.

Detailed operations for the first exemplary sub-case are described herein. Initially, the processor may determine a plurality of reference index candidates for the first reference index (e.g., each reference index candidate being considered as an example of a parameter candidate described above). For example, video encoder20and video decoder30may jointly pre-determine all the potential values for the first reference index for each video block, and the plurality of reference index candidates for the first reference index can include all the pre-determined potential values of the first reference index.

Next, the processor may determine a first motion vector for the video block based on a first MVD of the video block and a first motion vector predictor for the video block. For example, the first MVD of the video block can be received through the bitstream from video encoder20. Alternatively, the first MVD of the video block may be derived as described herein. The first motion vector predictor can be indicated by a first AMVP index received through the bitstream from video encoder20. The processor may generate the first motion vector for the video block as follows: the first motion vector=the first MVD+the first motion vector predictor. Similarly, the processor may determine a second motion vector for the video block based on a second MVD of the video block and a second motion vector predictor for the video block. For example, the second MVD of the video block can be received through the bitstream from video encoder20. Alternatively, the second MVD of the video block may be derived as described herein. The second motion vector predictor can be indicated by a second AMVP index received through the bitstream from video encoder20. The processor may generate the second motion vector for the video block as follows: the second motion vector=the second MVD+the second motion vector predictor.

Then, for each reference index candidate of the first reference index, the processor may derive a first reference block based on the first motion vector. For example, the processor may determine the first reference block from a first reference frame based on (a) the first motion vector for the video block and (b) the reference index candidate of the first reference index, where the reference index candidate of the first reference index can be used to identify the first reference frame in the first reference frame list. Additionally, the processor may derive a second reference block from a second reference frame based on (a) the second motion vector for the video block and (b) a second reference index which is used to identify the second reference frame in the second reference frame list. In this case, the second reference index of the video block can be signaled from video encoder20.

Further, for each reference index candidate of the first reference index, the processor may determine a matching cost between the first and second reference blocks. For example, the matching cost can be a difference metric such as an MSE, an SAD, an SSD, etc., between the first and second reference blocks. As a result, a plurality of matching costs can be determined for the plurality of reference index candidates of the first reference index, respectively. Then, the processor may derive the first reference index for the video block to be a reference index candidate of the first reference index that is associated with the minimum matching cost among the plurality of matching costs.

In the second exemplary sub-case of reference index derivation620under the bi-prediction scheme, the one or more reference indices to be derived on the decoder side may include both the first reference index and the second reference index. In this case, both the first reference index and the second reference index can be derived on the decoder side (e.g., not signaled from video encoder20). That is, the first reference index and the second reference index may be predicted jointly on the decoder side.

For example, for each pair of potential values of the first reference index and the second reference index, a first reference block can be obtained based on (a) a first motion vector of the video block and (b) a potential value of the first reference index included in the pair; a second reference block can be obtained based on (a) a second motion vector of the video block and (b) a potential value of the second reference index included in the pair; and a distance between the first and second reference blocks can be used as a matching cost for the pair of potential values of the first reference index and the second reference index. As a result, a plurality of matching costs can be determined for a plurality of pairs of potential values of the first reference index and the second reference index, respectively. A pair of potential values of the first reference index and the second reference index which leads to the minimum matching cost can be selected as a derived value for the first reference index and a derived value for the second reference index on the decoder side, respectively.

Detailed operations for the second exemplary sub-case are described herein. Initially, the processor may determine a plurality of pairs of reference index candidates for the first reference index and the second reference index (e.g., each pair of reference index candidates being considered as an example of a parameter candidate described above). For example, video encoder20and video decoder30may jointly pre-determine M1 potential values for the first reference index and M2 potential values for the second reference index for each video block, where M1 and M2 are positive integers. Then, the plurality of pairs of reference index candidates for the first reference index and the second reference index can include M1*M2 pairs of potential values for the first reference index and the second reference index.

Next, by performing operations like those described above for the first exemplary sub-case of reference index derivation620under the bi-prediction scheme, the processor may determine a first motion vector for the video block based on a first MVD of the video block and a first motion vector predictor for the video block. The processor may also determine a second motion vector for the video block based on a second MVD of the video block and a second motion vector predictor for the video block.

Then, for each pair of reference index candidates of the first reference index and the second reference index, the processor may derive a first reference block and a second reference block based on the corresponding pair of reference index candidates. For example, the processor may determine the first reference block from a first reference frame based on (a) the first motion vector for the video block and (b) the reference index candidate of the first reference index included in the pair. The reference index candidate of the first reference index can be used to identify the first reference frame in the first reference frame list. The processor may also determine the second reference block from a second reference frame based on (a) the second motion vector for the video block and (b) the reference index candidate of the second reference index included in the pair. The reference index candidate of the second reference index can be used to identify the second reference frame in the second reference frame list.

Further, for each pair of reference index candidates of the first reference index and the second reference index, the processor may determine a matching cost between the first and second reference blocks. For example, the matching cost can be a difference metric between the first and second reference blocks. As a result, a plurality of matching costs can be determined for the plurality of pairs of reference index candidates of the first reference index and the second reference index, respectively.

Subsequently, the processor may derive the first reference index and the second reference index for the video block based on a pair of reference index candidates of the first reference index and the second reference index that is associated with the minimum matching cost among the plurality of matching costs. For example, the processor may derive the first reference index to be a reference index candidate of the first reference index which is included in the pair associated with the minimum matching cost. The processor may derive the second reference index to be a reference index candidate of the second reference index which is included in the pair associated with the minimum matching cost.

Consistent with some implementations of the present disclosure, MVD prediction618and reference index derivation620can be performed jointly on the decoder side. Taking the video block being coded using the uni-prediction scheme as an example, the one or more motion related parameters to be derived on the decoder side may include an MVD of the video block and a reference index used to identify a reference frame for the video block. In this case, the prediction of the MVD and the reference index can be performed jointly on the decoder side using the template matching technique.

To begin with, the processor may firstly determine a plurality of pairs of MVD candidates and reference index candidates for the video block, with each pair including an MVD candidate and a reference index candidate. For example, the processor may determine that there may be N MVD candidates and M reference index candidates for the video block, so that the plurality of pairs of MVD candidates and reference index candidates for the video block can be N*M pairs. N and M are positive integers.

Next, for each pair of MVD candidates and reference index candidates, the processor may determine a reference region associated with the pair. For example, the processor may determine a motion vector candidate for the video block based on the MVD candidate included in the pair and a motion vector predictor indicated by an AMVP index. The processor may determine a reference region based on the template, the reference index candidate included in the pair, and the motion vector candidate for the video block.

Further, for each pair of MVD candidates and reference index candidates, the processor may determine a matching cost between the template of the video block and the reference region corresponding to the pair. For example, the matching cost can be a difference metric (e.g., a distance measurement) between the reference region and the template. As a result, a plurality of matching costs can be determined for the plurality of pairs of MVD candidates and reference index candidates, respectively.

Subsequently, the processor may derive the MVD and the reference index for the video block based on a pair of MVD candidates and reference index candidates that is associated with the minimum matching cost among the plurality of matching costs. For example, the processor may derive the MVD to be a MVD candidate included in the pair that is associated with the minimum matching cost. The processor may also derive the reference index to be a reference index candidate included in the pair that is associated with the minimum matching cost.

It is contemplated that when the video block is coded using the bi-prediction scheme, similar operations may be performed for predicting or deriving the MVD and the reference index jointly on the decoder side using the bilateral matching technique. The similar descriptions will not be repeated herein.

FIG.7is an illustration of an exemplary bit plane for an absolute value of an MVD in accordance with some implementations of the present disclosure.FIG.8is an illustration of an exemplary template for a video block coded using a uni-prediction scheme in accordance with some implementations of the present disclosure.FIGS.7-8are described above with reference toFIGS.6A-6B, and the similar description will not be repeated herein.

FIG.9is a flow chart of an exemplary method900for motion information derivation in accordance with some implementations of the present disclosure. Method900may be implemented by a processor associated with video decoder30, and may include steps902-904as described below. Some of the steps may be optional to perform the disclosure provided herein. Further, some of the steps may be performed simultaneously, or in a different order than shown inFIG.9.

In step902, the processor may determine that one or more motion related parameters for a video block in a video frame of a video are not signaled in a bitstream from a video encoder. For example, the processor may determine that the one or more motion related parameters are to be derived on the decoder side based on one or more syntax elements received from the video encoder. In some implementations, the one or more motion related parameters may include at least one of an MVD of the video block or a reference index for the video block.

In step904, the processor may determine the one or more motion related parameters for the video block by applying a coding matching technique. The coding matching technique is a template matching technique or a bilateral matching technique. An exemplary implementation of step904is described below in more detail with reference toFIG.10.

FIG.10is a flow chart of an exemplary method1000for determining one or more motion related parameters for a video block by applying a coding matching technique in accordance with some implementations of the present disclosure. Method1000may be implemented by a processor associated with video decoder30, and may include steps1002-1006as described below. Some of the steps may be optional to perform the disclosure provided herein. Further, some of the steps may be performed simultaneously, or in a different order than shown inFIG.10.

In step1002, the processor may determine a plurality of parameter candidates for the one or more motion related parameters. Each parameter candidate may include one or more values for the one or more motion related parameters, respectively.

In step1004, the processor may determine a plurality of matching costs associated with the plurality of parameter candidates, respectively. An exemplary implementation of step1004is described below in more detail with reference toFIG.11.

In step1006, the processor may derive the one or more motion related parameters based on a parameter candidate associated with a minimum matching cost among the plurality of matching costs.

FIG.11is a flow chart of an exemplary method1100for determining a plurality of matching costs associated with a plurality of parameter candidates, respectively, in accordance with some implementations of the present disclosure. Method1100may be implemented by a processor associated with video decoder30, and may include steps1102-1108as described below. Some of the steps may be optional to perform the disclosure provided herein. Further, some of the steps may be performed simultaneously, or in a different order than shown inFIG.11.

In step1102, the processor may determine whether a coding matching technique applied to derive one or more motion related parameters on the decoder side is a template matching technique or a bilateral matching technique. Responsive to the template matching technique being applied, method1100may proceed to step1104. Responsive to the bilateral matching technique being applied, method1100may proceed to step1108. For example, if a video block of a video frame is coded using a uni-prediction scheme, the template matching technique is applied. If the video block is coded using a bi-prediction scheme, the bilateral matching technique is applied.

In step1104, the processor may determine a template for the video block from the video frame.

In step1108, for each parameter candidate from the plurality of parameter candidates, the processor may derive one or more reference blocks associated with the parameter candidate and determine a matching cost for the parameter candidate based on the one or more reference blocks.

FIG.12is a flow chart of an exemplary method1200for encoding motion information in accordance with some implementations of the present disclosure. Method1200may be implemented by a processor associated with video encoder20, and may include steps1202-1208as described below. Some of the steps may be optional to perform the disclosure provided herein. Further, some of the steps may be performed simultaneously, or in a different order than shown inFIG.12.

In step1202, the processor may receive a video block in a video frame of a video.

In step1204, the processor may determine not to signal one or more motion related parameters for the video block in a bitstream to a video decoder.

In step1206, the processor may generate at least one syntax element to indicate that the one or more motion related parameters for the video block are to be predicted by the video decoder.

In step1208, the processor may include the at least one syntax element in the bitstream for the video decoder to independently determine the one or more motion parameters.

Consistent with some implementations of the present disclosure, the one or more motion related parameters may include one or more MVDs for the video block. For each of the one or more MVDs, the processor may encode the MVD using a binarization and splitting method. The binarization and splitting method may include absolute value binarization604and bit plane splitting606described above with reference toFIG.6A. For example, by performing operations like those described above with reference toFIG.6A, the processor may binarize an absolute value of the MVD into a bit plane, and divide the bit plane into a set of MSBs, a set of d-MSBs, and a set of LSBs. The processor may generate a reduced absolute value for the MVD using the set of MSBs and the set of LSBs.

For each of the one or more MVDs, the processor may also generate a set of syntax elements based on the encoding of the MVD. The bitstream may include the set of syntax elements. For example, the processor may generate a first syntax element (e.g., “mvd_derivation_flag” in Table 4 above) for indicating whether MVD prediction618is to be applied on video decoder30. The processor may also generate a second syntax element (e.g., “reduced_abs_mvd_minus2” in Table 4 above) for signaling the reduced absolute value of the MVD to video decoder30. The processor may also generate a third syntax element (e.g., “sh_derived_msb_length” in Table 3 above) for signaling a length of the set of d-MSBs to video decoder30. The processor may also generate a fourth syntax element (e.g., “sh_derived_msb_pos” in Table 3 above) for signaling a position where the set of d-MSBs starts in the bit plane to video decoder30. The processor may include the first, second, third, and fourth syntax elements into the bitstream.

In some implementations, the video block is coded using a uni-prediction scheme by the video encoder, and then the one or more MVDs may include an MVD only. The processor may perform operations like those described herein to encode the MVD and to generate the bitstream based on the encoding of the MVD.

In some other implementations, the video block is coded using a bi-prediction scheme by the video encoder, and then the one or more MVDs may include a first MVD and a second MVD. If both the first and second MVDs are not signaled to video decoder30(e.g., both the first and second MVDs are to be derived on video decoder30), the processor may perform operations like those described herein to (a) encode the first MVD to generate a first set of syntax elements and to (b) encode the second MVD to generate a second set of syntax elements, respectively. The processor may include the first set of syntax elements and the second set of syntax elements into the bitstream. In this case, the first and second MVDs can be jointly predicted on the decoder side. Alternatively, if only one of the first and second MVDs is not signaled to video decoder30(e.g., only one of the first and second MVDs is to be derived on video decoder30), the processor may perform operations like those described herein to encode the one of the first and second MVDs to generate a set of syntax elements. The processor may include the set of syntax elements into the bitstream, so that the one of the first and second MVDs is predicted on the decoder side. In this case, the other one of the first and second MVDs can be signaled to video decoder30, rather than being derived on the decoder side using MVD prediction618.

Consistent with some implementations of the present disclosure, the one or more motion related parameters may include one or more reference indices for the video block. The processor may generate a syntax element (e.g., “derive_ref_idx_flag” in Table 5 above) for indicating whether reference index derivation620is to be applied on video decoder30. The processor may include the syntax element (“derive_ref_idx_flag”) into the bitstream.

In some implementations, the video block is coded using a uni-prediction scheme, and then the one or more reference indices may include a reference index only. The processor may perform operations like those described herein to generate and include the syntax element (e.g., “derive_ref_idx_flag”) for the reference index into the bitstream.

In some other implementations, the video block is coded using a bi-prediction scheme, and then the one or more reference indices may include a first reference index and a second reference index. In a first scenario, both the first and second reference indices are not signaled to video decoder30(e.g., both the first and second reference indices are to be derived on video decoder30). In a second scenario, only one of the first and second reference indices is not signaled to video decoder30(e.g., only one of the first and second reference indices is to be derived on video decoder30). In either scenario, the processor may perform operations like those described herein to generate and include the syntax element (“derive_ref_idx_flag”) into the bitstream.

FIG.13shows a computing environment1310coupled with a user interface1350, according to some implementations of the present disclosure. The computing environment1310can be part of a data processing server. Consistent with the present disclosure, video encoder20and video decoder30can be implemented using the computing environment1310. The computing environment1310includes a processor1320, a memory1330, and an Input/Output (I/O) interface1340.

The processor1320typically controls overall operations of the computing environment1310, such as the operations associated with display, data acquisition, data communications, and image processing. The processor1320may include one or more processors to execute instructions to perform all or some of the steps in the above-described methods. Moreover, the processor1320may include one or more modules that facilitate the interaction between the processor1320and other components. The processor1320may be a Central Processing Unit (CPU), a microprocessor, a single chip machine, a Graphical Processing Unit (GPU), or the like.

The memory1330is configured to store various types of data to support the operation of the computing environment1310. The memory1330may include predetermined software1332. Examples of such data includes instructions for any applications or methods operated on the computing environment1310, video datasets, image data, etc. The memory1330may be implemented by using any type of volatile or non-volatile memory devices, or a combination thereof, such as a Static Random Access Memory (SRAM), an Electrically Erasable Programmable Read-Only Memory (EEPROM), an Erasable Programmable Read-Only Memory (EPROM), a Programmable Read-Only Memory (PROM), a Read-Only Memory (ROM), a magnetic memory, a flash memory, a magnetic or optical disk.

The I/O interface1340provides an interface between the processor1320and peripheral interface modules, such as a keyboard, a click wheel, buttons, or the like. The buttons may include but are not limited to, a home button, a start scan button, and a stop scan button. The I/O interface1340can be coupled with an encoder and decoder.

In some implementations, there is also provided a non-transitory computer-readable storage medium including a plurality of programs, for example, in the memory1330, executable by the processor1320in the computing environment1310, for performing the above-described methods. Alternatively, the non-transitory computer-readable storage medium may have stored therein a bitstream or a data stream including encoded video information (for example, video information including one or more syntax elements) generated by an encoder (for example, video encoder20inFIG.2) using, for example, the encoding method described above for use by a decoder (for example, video decoder30inFIG.3) in decoding video data. The non-transitory computer-readable storage medium may be, for example, a ROM, a Random Access Memory (RAM), a CD-ROM, a magnetic tape, a floppy disc, an optical data storage device or the like.

In some implementations, there is also provided a computing device including one or more processors (for example, the processor1320); and the non-transitory computer-readable storage medium or the memory1330having stored therein a plurality of programs executable by the one or more processors, wherein the one or more processors, upon execution of the plurality of programs, are configured to perform the above-described methods.

In some implementations, there is also provided a computer program product including a plurality of programs, for example, in the memory1330, executable by the processor1320in the computing environment1310, for performing the above-described methods. For example, the computer program product may include the non-transitory computer-readable storage medium.

In some implementations, the computing environment1310may be implemented with one or more ASICs, DSPs, Digital Signal Processing Devices (DSPDs), Programmable Logic Devices (PLDs), FPGAs, GPUs, controllers, micro-controllers, microprocessors, or other electronic components, for performing the above methods.

The description of the present disclosure has been presented for purposes of illustration and is not intended to be exhaustive or limited to the present disclosure. Many modifications, variations, and alternative implementations will be apparent to those of ordinary skill in the art having the benefit of the teachings presented in the foregoing descriptions and the associated drawings.

Unless specifically stated otherwise, an order of steps of the method according to the present disclosure is only intended to be illustrative, and the steps of the method according to the present disclosure are not limited to the order specifically described above, but may be changed according to practical conditions. In addition, at least one of the steps of the method according to the present disclosure may be adjusted, combined or deleted according to practical requirements.

The examples were chosen and described in order to explain the principles of the disclosure and to enable others skilled in the art to understand the disclosure for various implementations and to best utilize the underlying principles and various implementations with various modifications as are suited to the particular use contemplated. Therefore, it is to be understood that the scope of the disclosure is not to be limited to the specific examples of the implementations disclosed and that modifications and other implementations are intended to be included within the scope of the present disclosure.