SEMICONDUCTOR PACKAGE

A semiconductor package includes a lower chip. A chip stacked structure is arranged on the lower chip. The chip stacked structure includes a plurality of upper chips. An underfill layer is disposed between the lower chip and the chip stacked structure and between the plurality of upper chips. A molding layer surrounds the underfill layer and the chip stacked structure. The lower chip has at least one lower trench positioned on an upper surface of the lower chip. At least one of the plurality of upper chips has at least one upper trench on an upper surface of the at least one of the plurality of upper chips.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2022-0170052, filed on Dec. 7, 2022 in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference in its entirety herein.

1. TECHNICAL FIELD

The present disclosure relates to a semiconductor package, and more particularly, to a semiconductor package including a plurality of chips, which are stacked.

2. DISCUSSION OF RELATED ART

Electronic components mounted on electronic products have become increasingly miniaturized and lightweight as the electronic industry has advanced. For example, semiconductor packages mounted on electronic components are being developed to process high-capacity data while having a relatively small volume. Therefore, a semiconductor package including a plurality of chips that are stacked on each other has been proposed.

SUMMARY

Embodiments of the present disclosure provide a semiconductor package capable of strengthening an adhesion strength of a plurality of chips while relieving stress applied to the plurality of chips.

According to an embodiment of the present disclosure, a semiconductor package includes a lower chip. A chip stacked structure is arranged on the lower chip. The chip stacked structure includes a plurality of upper chips. An underfill layer is disposed between the lower chip and the chip stacked structure and between the plurality of upper chips. A molding layer surrounds the underfill layer and the chip stacked structure. The lower chip has at least one lower trench positioned on an upper surface of the lower chip. At least one of the plurality of upper chips has at least one upper trench on an upper surface of the at least one of the plurality of upper chips.

According to an embodiment of the present disclosure, a semiconductor package includes a lower chip. A chip stacked structure is arranged on the lower chip. The chip stacked structure comprises a plurality of upper chips. An underfill layer is disposed between the lower chip and the chip stacked structure and between the plurality of upper chips. A molding layer surrounds the underfill layer and the chip stacked structure. The lower chip has at least one lower trench positioned on an upper surface of the lower chip. A portion of the at least one lower trench overlaps the molding layer in a vertical direction, and a remaining portion of the at least one lower trench overlaps the underfill layer in the vertical direction. The portion of the at least one lower trench overlapping the molding layer in the vertical direction is filled with the molding layer, and the remaining portion of the at least one lower trench overlapping the underfill layer in the vertical direction is filled with the underfill layer.

According to an embodiment of the present disclosure, a semiconductor package includes a package substrate. A redistribution structure is arranged on the package substrate. A sub-semiconductor package is arranged on the redistribution structure. A semiconductor chip is arranged on the redistribution structure and spaced apart from the sub-semiconductor package in a horizontal direction. The sub-semiconductor package comprises a lower chip and a chip stacked structure arranged on the lower chip. The chip stacked structure comprises a plurality of upper chips. An underfill layer is disposed between the lower chip and the chip stacked structure and between the plurality of upper chips. A molding layer surrounds the underfill layer and the chip stacked structure. The lower chip has at least one lower trench positioned on an upper surface of the lower chip. At least one of the plurality of upper chips has at least one upper trench positioned on an upper surface of the at least one of the plurality of upper chips.

DETAILED DESCRIPTION OF EMBODIMENTS

Hereinafter, embodiments of the present disclosure are described in detail with reference to the accompanying drawings. Like components are denoted by like reference numerals throughout the specification, and repeated descriptions thereof may be omitted for economy of description.

FIG.1Ais a plan view illustrating a semiconductor package100according to an embodiment.FIG.1Bis a cross-sectional view of the semiconductor package100taken along a line A-A′ ofFIG.1A.FIG.1Cis an enlarged cross-sectional view of a region EX ofFIG.1B.

Referring toFIGS.1A to1C, the semiconductor package100may include a lower chip110, a chip stacked structure120, an underfill layer130, and a molding layer140.

Hereinafter, unless otherwise specially defined, a direction parallel to an upper surface of the lower chip110is defined as a first horizontal direction, a direction perpendicular to the upper surface of the lower chip110is defined as a vertical direction, and a direction perpendicular to the first horizontal direction and the vertical direction is defined as a second horizontal direction.

In an embodiment, the lower chip110may be, for example, a buffer chip controlling a high bandwidth memory (HBM) dynamic random access memory (DRAM) chip. The lower chip110may include a plurality of through electrodes TSV, a plurality of lower pads Lp, and a plurality of upper pads Up.

In an embodiment, the lower chip110may include a group IV semiconductor such as silicon (Si) or germanium (Ge), a group IV-IV compound semiconductor such as silicon-germanium (SiGe) or silicon carbide (SiC), or group III-V compound semiconductor such as gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP). However, embodiments of the present disclosure are not necessarily limited thereto. The lower chip110may include a conductive region, for example, a well doped with impurities or a structure doped with impurities. The lower chip110may have various device isolation structures, such as a shallow trench isolation (STI) structure.

The lower chip110may have an active surface and an inactive surface opposite to the active surface. Various types of a plurality of individual devices may be formed on the active surface. For example, in an embodiment the plurality of individual devices may include metal-oxide-semiconductor field effect transistors such as complementary metal-insulator-semiconductor transistors (CMOS) or the like, image sensors such as system large scale integration (LSI), CMOS imaging sensors (CIS) or the like, micro-electro-mechanical systems (MEMS), active elements, passive elements, or the like. However, embodiments of the present disclosure are not necessarily limited thereto.

The lower chip110may have a lower trench Tr1on the upper surface thereof. In an embodiment, the lower trench Tr1may be a single trench having a serpentine shape in a plan view. For example, the lower trench Tr1may be a single trench positioned on the upper surface of the lower chip110and having a serpentine shape extending along an edge of the upper surface of the lower chip110.

In an embodiment, the lower trench Tr1may have a quadrangular cross section. For example, the lower trench Tr1may have a quadrangular shape in a cross section perpendicular to the second horizontal direction.

In an embodiment, the lower trench Tr1may overlap the underfill layer130and the molding layer140in the vertical direction. For example, a boundary line where the underfill layer130and the molding layer140come into direct contact with each other may be positioned between both side surfaces (e.g., lateral side surfaces) of the lower trench Tr1. Accordingly, based on the boundary line, an inner region of the lower trench Tr1which is in direct contact with the underfill layer130in the vertical direction, may be filled with the underfill layer130, and an outer region of the lower trench Tr1, which is in direct contact with the molding layer140in the vertical direction, may be filled with the molding layer140.

In an embodiment, a first horizontal length La1and a second horizontal length Lb1of the lower trench Tr1may each be in a range of about 1 μm to about 100 μm. However, embodiments of the present disclosure are not necessarily limited thereto. The first horizontal length La1and the second horizontal length Lb1may vary according to a horizontal area or vertical length of the lower chip110.

In an embodiment, a vertical length L1of the lower trench Tr1may be in a range of about 1 μm to about 500 μm. However, embodiments of the present disclosure are not necessarily limited thereto. The vertical length L1may vary according to the horizontal area or vertical length of the lower chip110.

Each of the plurality of through electrodes TSV may pass through the lower chip110and extend in the vertical direction. The plurality of through electrodes TSV may be spaced apart from each other in the first horizontal direction. The plurality of through electrodes TSV may electrically connect the plurality of upper pads Up and the plurality of lower pads Lp to each other, respectively.

The plurality of lower pads Lp may be arranged on a lower surface of the lower chip110. In an embodiment, the plurality of lower pads Lp may be arranged to respectively overlap the plurality of through electrodes TSV corresponding thereto in the vertical direction. The plurality of lower pads Lp may be respectively connected to (e.g., directly connected thereto in the vertical direction) the plurality of through electrodes TSV corresponding thereto.

The plurality of upper pads Up may be arranged on the upper surface of the lower chip110. In an embodiment, the plurality of upper pads Up may be arranged to respectively overlap the plurality of through electrodes TSV corresponding thereto and the plurality of lower pads Lp corresponding thereto in the vertical direction. The plurality of upper pads Up may be respectively connected to (e.g., directly connected thereto in the vertical direction) the plurality of through electrodes TSV corresponding thereto.

A plurality of first connection terminals SB1may respectively be arranged on the plurality of lower pads Lp of the lower chip110. In an embodiment, each of the plurality of first connection terminals SB1may be, for example, a solder ball or a solder bump. Each of the plurality of first connection terminals SB1may include a solder material. In an embodiment, the solder material may include, for example, tin (Sn), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), silver (Ag), zinc (Zn), lead (Pb), and/or an alloy thereof. The lower chip110may be electrically connected to an external device (e.g., a redistribution structure600(refer toFIG.6) through the plurality of first connection terminals SB1.

The chip stacked structure120may be arranged on the lower chip110(e.g., in the vertical direction). In an embodiment, the chip stacked structure120may include first to fourth upper chips120_1,120_2,120_3, and120_4, which are sequentially stacked (e.g., in the vertical direction). However, embodiments of the present disclosure are not necessarily limited thereto and the number of upper chips of the chip stacked structure120may vary. First horizontal lengths of the first to fourth upper chips120_1,120_2,120_3, and120_4may be substantially the same or similar to each other. In an embodiment, a vertical length of the fourth upper chip120_4, which is positioned at the uppermost end, may be greater than a vertical length of each of the first to third upper chips120_1,120_2, and120_3.

In an embodiment, the first horizontal length of each of the first to fourth upper chips120_1,120_2,120_3, and120_4may be less than the first horizontal length of the lower chip110.

In an embodiment, each of the first to fourth upper chips120_1,120_2,120_3, and120_4may be a volatile memory semiconductor chip, such as a DRAM or static random access memory (SRAM) chip, or a non-volatile memory chip, such as a phase-change random access memory (PRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FeRAM), or resistive random access memory (ReRAM) chip. However, embodiments of the present disclosure are not necessarily limited thereto.

In an embodiment, each of the first to fourth upper chips120_1,120_2,120_3, and120_4may be a DRAM chip, and the chip stacked structure120may configure HBM. However, embodiments of the present disclosure are not necessarily limited thereto.

AlthoughFIG.1Billustrates that the chip stacked structure120includes four upper chips, such as the first to fourth upper chips120_1,120_2,120_3, and120_4, embodiments of the present disclosure are not necessarily limited thereto. For example, in an embodiment, the chip stacked structure120may also include multiples of 4, for example, 8, 12, or 16 upper chips.

Each of the first to third upper chips120_1,120_2, and120_3may include the plurality of through electrodes TSV, the plurality of lower pads Lp, and the plurality of upper pads Up. The fourth upper chip120_4may include only the plurality of lower pads Lp and may not include the plurality of through electrodes TSV and the plurality of upper pads Up.

In an embodiment, each of the first to fourth upper chips120_1,120_2,120_3, and120_4may include a semiconductor material substantially the same as or similar to that of the lower chip110. Also, each of the first to fourth upper chips120_1,120_2,120_3, and120_4may have a structure substantially the same as or similar to that of the lower chip110.

The first to third upper chips120_1,120_2, and120_3may respectively have first to third upper trenches Tr2_1, Tr2_2, and Tr2_3on upper surfaces thereof. For example, the first upper chip120_1may have the first upper trench Tr2_1on the upper surface thereof, the second upper chip120_2may have the second upper trench Tr2_2on the upper surface thereof, and the third upper chip120_3may have the third upper trench Tr2_3on the upper surface thereof. In an embodiment, some of the first to third upper trenches Tr2_1, Tr2_2, and Tr2_3may be omitted. For example, the second upper trench Tr2_2and the third upper trench Tr2_3may be omitted on the second upper chip120_2and third upper chip120_3, respectively, and only the first upper trench Tr2_1may be present on the upper surface of the first upper chip120_1.

In an embodiment, each of the first to third upper trenches Tr2_1, Tr2_2, and Tr2_3may have a serpentine shape in a plan view. For example, the first to third upper trenches Tr2_1, Tr2_2, and Tr2_3may respectively be positioned on the upper surfaces of the first to third upper chips120_1,120_2, and120_3, and may have a serpentine shape extending along edges of the upper surfaces of the first to third upper chips120_1,120_2, and120_3, respectively.

In an embodiment, each of the first to third upper trenches Tr2_1, Tr2_2, and Tr2_3may have a quadrangular cross section. For example, each of the first to third upper trenches Tr2_1, Tr2_2, and Tr2_3may have a quadrangular shape in a cross section perpendicular to the second horizontal direction.

In an embodiment, each of the first to third upper trenches Tr2_1, Tr2_2, and Tr2_3may overlap the underfill layer130in the vertical direction. Accordingly, the first to third upper trenches Tr2_1, Tr2_2, and Tr2_3may be filled with the underfill layer130.

In an embodiment, a first horizontal length La2and a second horizontal length Lb2of each of the first to third upper trenches Tr2_1, Tr2_2, and Tr2_3may be in a range of about 1 μm to about 100 μm. For example, in an embodiment, within the range of about 1 μm to about 100 μm, the first horizontal length La2and the second horizontal length Lb2of each of the first to third upper trenches Tr2_1, Tr2_2, and Tr2_3may be equal to each other or different from each other. For example, in an embodiment the first horizontal length La2and the second horizontal length Lb2of the first upper trench Tr2_1may be different from the first horizontal length La2and the second horizontal length Lb2of the second upper trench Tr2_2, respectively. However, embodiments of the present disclosure are not necessarily limited thereto.

In an embodiment, vertical lengths L2_1, L2_2, and L2_3of the first to third upper trenches Tr2_1, Tr2_2, and Tr2_3may be in a range of about 1 μm to about 500 μm. For example, in an embodiment within the range of about 1 μm to about 500 μm, the vertical lengths L2_1, L2_2, and L2_3of the first to third upper trenches Tr2_1, Tr2_2, and Tr2_3may be equal to each other or different from each other. For example, in an embodiment the vertical length L2_1of the first upper trench Tr2_1may be different from the vertical length L2_2of the second upper trench Tr2_2, and may be substantially equal to the vertical length L2_3of the third upper trench Tr2_3. However, embodiments of the present disclosure are not necessarily limited thereto.

The plurality of through electrodes TSV may extend in the vertical direction through the first to third upper chips120_1,120_2, and120_3. For example, the plurality of through electrodes TSV may extend in the vertical direction through an entirety of the thicknesses of each of the first to third upper chips120_1,120_2, and120_3. The plurality of through electrodes TSV may be substantially the same as or similar to the plurality of through electrodes TSV included in the lower chip110.

The plurality of lower pads Lp may be arranged on (e.g., directly thereon in the vertical direction) a lower surface of each of the first to fourth upper chips120_1,120_2,120_3, and120_4. The plurality of lower pads Lp may be substantially the same as or similar to the plurality of lower pads Lp included in the lower chip110.

The plurality of upper pads Up may be arranged on (e.g., directly thereon in the vertical direction) the upper surface of each of the first to third upper chips120_1,120_2, and120_3. The plurality of upper pads Up may be substantially the same as or similar to the plurality of upper pads Up included in the lower chip110.

In an embodiment, a plurality of second connection terminals SB2may be disposed between the first to fourth upper chips120_1,120_2,120_3, and120_4and between the first upper chip120_1and the lower chip110. For example, the plurality of second connection terminals SB2disposed between the first fourth upper chips120_1,120_2,120_3, and120_4and between the first upper chip120_1and the lower chip110may have an upper surface directly contacting a lower pad Lp and a lower surface directly contacting an upper pad Up. The plurality of second connection terminals SB2may include materials substantially the same as or similar to those of the plurality of first connection terminals SB1. The first to fourth upper chips120_1,120_2,120_3, and120_4and the lower chip110may be electrically connected to each other through the plurality of second connection terminals SB2.

The underfill layer130may be disposed between the first to fourth upper chips120_1,120_2,120_3, and120_4and between the first upper chip120_1and the lower chip110. The underfill layer130may surround the plurality of second connection terminals SB2, the plurality of lower pads Lp and the plurality of upper pads Up of the first to third upper chips120_1,120_2, and120_3, the plurality of lower pads Lp of the fourth upper chip1204, and the plurality of upper pads Up of the lower chip110.

In an embodiment, the underfill layer130may extend in the first horizontal direction beyond lateral edges of the upper surface of each of the first to fourth upper chips120_1,120_2,120_3, and120_4. For example, the first horizontal length of the underfill layer130may be greater than the first horizontal length of each of the first to fourth upper chips120_1,120_2,120_3, and120_4. Accordingly, the underfill layer130may completely cover the upper surface of each of the first to third upper chips120_1,120_2, and120_3and completely fill the first to third upper trenches Tr2_1, Tr2_2, and Tr2_3.

In an embodiment, the underfill layer130may include a BPA epoxy resin, a BPF epoxy resin, an aliphatic epoxy resin, a cycloaliphatic epoxy resin, or the like. However, embodiments of the present disclosure are not necessarily limited thereto.

The molding layer140may be arranged on the lower chip110and may surround the chip stacked structure120and the underfill layer130. In an embodiment as shown inFIG.1B, an upper surface of the molding layer140may be coplanar with the upper surface of the fourth upper chip120_4of the chip stacked structure120(e.g., in the vertical direction). However, embodiments of the present disclosure are not necessarily limited thereto. For example, in an embodiment the upper surface of the molding layer140may also be positioned at a higher vertical level than the upper surface of the fourth upper chip120_4of the chip stacked structure120. For example, the molding layer140may completely cover the upper surface of the fourth upper chip120_4.

In an embodiment, the molding layer140may include an epoxy molding compound (EMC), an Ajinomoto Build-up Film (ABF), FR-4, bismaleimide triazine (BT), or the like. However, embodiments of the present disclosure are not necessarily limited thereto.

The semiconductor package100according to an embodiment may include the lower trench Tr1positioned on the upper surface of the lower chip110and the first to third upper trenches Tr2_1, Tr2_2, and Tr2_3respectively positioned on the upper surfaces of the first to third upper chips120_1,120_2, and120_3. Due to the inclusion of the lower trench Tr1and the first to third upper trenches Tr2_1, Tr2_2, and Tr2_3, thermo-mechanical stress applied to the upper surface of the lower chip110and the upper surface of each of the first to third upper chips120_1,120_2, and120_3may be reduced.

Also, the underfill layer130may fill the first to third upper trenches Tr2_1, Tr2_2, and Tr2_3, and the underfill layer130and the molding layer140may together fill the lower trench Tr1. Accordingly, an area in which each of the first to third upper chips120_1,120_2, and120_3and the underfill layer130directly contact each other and an area in which the lower chip110, the underfill layer130and the molding layer140directly contact each other may be increased. Accordingly, an adhesion strength between each of the first to third upper chips120_1,120_2, and120_3and the underfill layer130and an adhesion strength between the lower chip110, the underfill layer130, and the molding layer140may be increased.

FIGS.2A and2Bare enlarged cross-sectional views of a region corresponding to the region EX ofFIG.1B. In particular,FIG.2Ais an enlarged cross-sectional view of a semiconductor package100a, andFIG.2Bis an enlarged cross-sectional view of a semiconductor package100b. Each configuration of the semiconductor package100ashown inFIG.2Aand each configuration of the semiconductor package100bshown inFIG.2Bare similar to each configuration of the semiconductor package100described with reference toFIGS.1A to1C, and thus differences thereof are mainly described for economy of description.

Referring toFIG.2A, in an embodiment the semiconductor package100amay include a lower chip110ahaving a lower trench Tr1aon an upper surface thereof and first to third upper chips120_1a,120_2a, and120_3arespectively having first to third upper trenches Tr2_1a, Tr2_2a, and Tr2_3aon upper surfaces thereof.

In an embodiment, the lower trench Tr1aand the first to third upper trenches Tr2_1a, Tr2_2a, and Tr2_3amay each have a triangular cross section instead of the quadrangular cross section shown in an embodiment ofFIG.1C. For example, the lower trench Tr1aand the first to third upper trenches Tr2_1a, Tr2_2a, and Tr2_3amay each have a triangular shape in a cross section perpendicular to the second horizontal direction.

Referring toFIG.2B, in an embodiment the semiconductor package100bmay include a lower chip110bhaving a lower trench Tr1bon an upper surface thereof and first to third upper chips120_1b,120_2b, and120_3brespectively having first to third upper trenches Tr2_1b, Tr2_2b, and Tr2_3bon upper surfaces thereof.

In an embodiment, the lower trench Tr1band the first to third upper trenches Tr2_1b, Tr2_2b, and Tr2_3bmay each have a U-shaped cross section instead of the quadrangular cross section shown in an embodiment ofFIG.1C. For example, the lower trench Tr1band the first to third upper trenches Tr2_1b, Tr2_2b, and Tr2_3bmay each have a U shape in a cross section perpendicular to the second horizontal direction.

Although the lower trench Tr1and the first to third upper trenches Tr2_1, Tr2_2, and Tr2_3shown inFIG.1C, the lower trench Tr1aand the first to third upper trenches Tr2_1a, Tr2_2a, and Tr2_3ashown inFIG.2A, and the lower trench Tr1band the first to third upper trenches Tr2_1b, Tr2_2b, and Tr2_3bshown inFIG.2Bare all illustrated as having the same cross sections, embodiments of the present disclosure are not necessarily limited thereto. For example, in an embodiment the lower trench Tr1may have a quadrangular cross section, the first upper trench Tr2_1and the second upper trench Tr2_2may each have a triangular cross section, and the third upper trench Tr2_3may have a U-shaped cross section. In some other embodiments, the lower trench Tr1band the first to third upper trenches Tr2_1b, Tr2_2b, and Tr2_3bmay include the quadrangular cross section, the triangular cross section and/or the U-shaped cross section in various other arrangements.

FIG.3Ais a plan view illustrating a semiconductor package200according to an embodiment.FIG.3Bis a cross-sectional view of the semiconductor package200taken along a line B-B′ ofFIG.3A.FIG.3Cis an enlarged cross-sectional view of a region EX ofFIG.3B.

Each configuration of the semiconductor package200shown inFIGS.3A to3Cis similar to each configuration of the semiconductor package100described with reference toFIGS.1A to1C, and thus differences thereof are mainly described for economy of description.

Referring toFIGS.3A to3C, the semiconductor package200may include a lower chip210, a chip stacked structure220, an underfill layer230, and a molding layer240.

The lower chip210may include the plurality of through electrodes TSV, the plurality of lower pads Lp, and the plurality of upper pads Up.

The lower chip210may have a plurality of first lower trenches Tr1_1and a plurality of second lower trenches Tr1_2positioned on an upper surface thereof. In an embodiment, the plurality of first lower trenches Tr1_1and the plurality of second lower trenches Tr1_2may each have a circular shape in a plan view and a semi-circular shape in a cross section. In an embodiment, the plurality of first lower trenches Tr1_1may be arranged on the upper surface of the lower chip210to be spaced apart from each other along an edge of the upper surface of the lower chip210, and the plurality of second lower trenches Tr1_2may respectively be arranged inside the plurality of first lower trenches Tr1_1on the upper surface of the lower chip210to be spaced apart from each other and the plurality of first lower trenches Tr1_1along the edge of the upper surface of the lower chip210. For example, the plurality of first lower trenches Tr1_1and the plurality of second lower trenches Tr1_2may form a plurality of lower trenches that are arranged in two rows (e.g., extending along the first and second horizontal directions) along the edge of the upper surface of the lower chip in a plan view.

In an embodiment, the plurality of first lower trenches Tr1_1may overlap the underfill layer230and the molding layer240in the vertical direction. For example, a boundary line where the underfill layer230and the molding layer240come into direct contact with each other may be positioned between both lateral side surfaces of the plurality of first lower trenches Tr1_1. Accordingly, based on the boundary line, an inner region of each of the plurality of first lower trenches Tr1_1, which is in direct contact with the underfill layer230in the vertical direction, may be filled with the underfill layer230, and an outer region of each of the plurality of first lower trenches Tr1_1, which is in direct contact with the molding layer240in the vertical direction, may be filled with the molding layer240.

In an embodiment, the plurality of second lower trenches Tr1_2may each overlap the underfill layer130in the vertical direction. Accordingly, each of the plurality of second lower trenches Tr1_2may be filled with the underfill layer230.

In an embodiment, a first horizontal length and a second horizontal length of each of the plurality of first lower trenches Tr1_1may be substantially equal to the first horizontal length La1and the second horizontal length Lb1of each of the plurality of second lower trenches Tr1_2. However, embodiments of the present disclosure are not necessarily limited thereto.

In an embodiment, the first horizontal length La1and the second horizontal length Lb1may each be in a range of about 1 μm to about 100 μm.

In an embodiment, a vertical length L1_1of each of the plurality of first lower trenches Tr1_1may be substantially equal to a vertical length L1_2of each of the plurality of second lower trenches Tr1_2. However, embodiments of the present disclosure are not necessarily limited thereto.

In an embodiment, the vertical lengths L1_1and L1_2may each be in a range of about 1 μm to about 500 μm.

The plurality of first connection terminals SB1may respectively be arranged on the plurality of lower pads Lp of the lower chip210.

The chip stacked structure220may be arranged on the lower chip210(e.g., in the vertical direction). In an embodiment, the chip stacked structure220may include first to fourth upper chips220_1,220_2,220_3, and220_4, which are sequentially stacked (e.g., in the vertical direction). However, embodiments of the present disclosure are not necessarily limited thereto and the number of the upper chips of the chip stacked structure220may vary. Each of the first to third upper chips220_1,220_2, and220_3may include the plurality of through electrodes TSV, the plurality of lower pads Lp, and the plurality of upper pads Up. The fourth upper chip220_4may include only the plurality of lower pads Lp and may not include the plurality of through electrodes TSV and the plurality of upper pads Up.

The first to third upper chips220_1,220_2, and220_3may respectively have a plurality of first upper trenches to a plurality of third upper trenches Tr2_1, Tr2_2, and Tr2_3positioned on upper surfaces thereof. For example, the first upper chip220_1may have the plurality of first upper trenches Tr2_1positioned on the upper surface thereof, the second upper chip220_2may have the plurality of second upper trenches Tr2_2positioned on the upper surface thereof, and the third upper chip220_3may have the plurality of third upper trenches Tr2_3positioned on the upper surface thereof. In an embodiment, some of the first to third upper trenches Tr2_1, Tr2_2, and Tr2_3may be omitted. For example, the second upper trench Tr2_2and the third upper trench Tr2_3may be omitted, and only the plurality of first upper trenches Tr2_1may be present on the upper surface of the first upper chip220_1.

In an embodiment, the plurality of first upper trenches to the plurality of third upper trenches Tr2_1, Tr2_2, and Tr2_3may each have a circular shape in a plan view and a semi-circular shape in a cross section. In an embodiment, the plurality of first upper trenches to the plurality of third upper trenches Tr2_1, Tr2_2, and Tr2_3may respectively be arranged on the upper surfaces of the first to third upper chips220_1,220_2, and220_3to be spaced apart from each other along edges of the upper surfaces of the first to third upper chips220_1,220_2, and220_3. For example, the plurality of second upper trenches Tr2_2may be arranged on the upper surface of the second upper chip220_2to be spaced apart from each other along the edge of the upper surface of the second upper chip220_2.

In an embodiment, each of the plurality of first upper trenches to the plurality of third upper trenches Tr2_1, Tr2_2, and Tr2_3may overlap the underfill layer230in the vertical direction. Accordingly, each of the plurality of first upper trenches to the plurality of third upper trenches Tr2_1, Tr2_2, and Tr2_3may be filled with the underfill layer230.

In an embodiment, a first horizontal length and a second horizontal length of each of the plurality of first upper trenches Tr2_1, a first horizontal length and a second horizontal length of each of the plurality of second upper trenches Tr2_2, and a first horizontal length and a second horizontal length of each of the plurality of third upper trenches Tr2_3may be substantially equal to each other. However, embodiments of the present disclosure are not necessarily limited thereto.

In an embodiment, the first horizontal length and the second horizontal length of each of the plurality of first upper trenches to the plurality of third upper trenches Tr2_1, Tr2_2, and Tr2_3may each be in a range of about 1 m to about 100 μm.

In an embodiment, a vertical length L2_1of each of the plurality of first upper trenches Tr2_1, a vertical length L2_2of each of the plurality of second upper trenches Tr2_2, and a vertical length L2_3of each of the plurality of third upper trenches Tr2_3may be substantially equal to each other. However, embodiments of the present disclosure are not necessarily limited thereto.

In an embodiment, the vertical lengths L2_1, L2_2, and L2_3may each be in a range of about 1 μm to about 500 μm.

The plurality of second connection terminals SB2may be disposed between the first to fourth upper chips220_1,220_2,220_3, and220_4and between the first upper chip220_1and the lower chip210. For example, the plurality of second connection terminals SB2disposed between the first fourth upper chips220_1,220_2,220_3, and220_4and between the first upper chip220_1and the lower chip210may have an upper surface directly contacting a lower pad Lp and a lower surface directly contacting an upper pad Up.

The underfill layer230may be disposed between the first to fourth upper chips220_1,220_2,220_3, and220_4and between the first upper chip2201and the lower chip210.

The molding layer240may be arranged on the lower chip210and may surround the chip stacked structure220and the underfill layer230.

The semiconductor package200according to an embodiment may include the plurality of first lower trenches Tr1_1and the plurality of second lower trenches Tr1_2positioned on the upper surface of the lower chip210and the first to third upper trenches Tr2_1, Tr2_2, and Tr2_3respectively positioned on the upper surfaces of the first to third upper chips220_1,220_2, and220_3. Due to the plurality of first lower trenches Tr1_1, the plurality of second lower trenches Tr1_2, and the first to third upper trenches Tr2_1, Tr2_2, and Tr2_3, thermo-mechanical stress applied to the upper surface of the lower chip210and the upper surface of each of the first to third upper chips220_1,220_2, and220_3may be reduced.

Also, the underfill layer230may fill the plurality of second lower trenches Tr1_2and the first to third upper trenches Tr2_1, Tr2_2, and Tr2_3, and the underfill layer230and the molding layer240may together fill the plurality of first lower trenches Tr1_1. Accordingly, an area in which each of the lower chip210and the first to third upper chips220_1,220_2, and220_3directly contact the underfill layer230and an area in which the lower chip210, the underfill layer230, and the molding layer240directly contact each other may be increased. Accordingly, an adhesion strength between each of the lower chip210and the first to third upper chips220_1,220_2, and220_3and the underfill layer230and an adhesion strength between the lower chip210, the underfill layer230, and the molding layer240may be increased.

FIGS.4A and4Bare plan views respectively illustrating semiconductor package200aand200baccording to an embodiment. Each configuration of the semiconductor packages200aand200bshown inFIGS.4A and4Bis similar to each configuration of the semiconductor package200described with reference toFIGS.3A to3C, and thus differences thereof are mainly described for economy of description.

Referring toFIG.4A, the semiconductor package200amay include a lower chip210ahaving a plurality of first lower trenches Tr1_1aand a plurality of second lower trenches Tr1_2apositioned on an upper surface thereof and a chip stacked structure220ahaving a plurality of upper trenches Tr2apositioned on an upper surface of each of stacked upper layers.

In an embodiment, the plurality of first lower trenches Tr1_1amay each have an elliptical shape in a plan view, and the plurality of second lower trenches Tr1_2aand the plurality of upper trenches Tr2amay each have a circular shape in a plan view.

Referring toFIG.4B, the semiconductor package200bmay have a lower chip210bhaving a plurality of first lower trenches Tr1_1band a plurality of second lower trenches Tr1_2band a chip stacked structure220bhaving a plurality of upper trenches Tr2bpositioned on an upper surface of each of stacked upper chips.

In an embodiment, the plurality of first lower trenches Tr1_1band the plurality of second lower trenches Tr1_2bmay each have a circular shape in a plan view, and the plurality of upper trenches Tr2bmay each have an elliptical shape in a plan view.

FIG.5Ais a plan view illustrating a semiconductor package300according to an embodiment.FIG.5Bis a cross-sectional view of the semiconductor package300taken along a line C-C′ ofFIG.5A.FIG.5Cis an enlarged cross-sectional of a region EX ofFIG.5B. Each configuration of the semiconductor package300shown inFIGS.5A to5Cis similar to each configuration of the semiconductor package100described with reference toFIGS.1A to1C, and thus differences thereof are mainly described for economy of description.

Referring toFIGS.5A to5C, the semiconductor package300may include a lower chip310, a chip stacked structure320, an underfill layer330, and a molding layer340.

The lower chip310may include the plurality of through electrodes TSV, the plurality of lower pads Lp, and the plurality of upper pads Up.

The lower chip310may have the lower trench Tr1positioned on an upper surface thereof. In an embodiment, the lower trench Tr1may be a single trench having a serpentine shape in a plan view. For example, the lower trench Tr1may be a single trench positioned on the upper surface of the lower chip310and having a serpentine shape extending along an edge of the upper surface of the lower chip310.

In an embodiment, the lower trench Tr1may have a quadrangular cross section. For example, the lower trench Tr1may have a quadrangular shape in a cross section perpendicular to the second horizontal direction.

In an embodiment, the lower trench Tr1may overlap the underfill layer330and the molding layer340in the vertical direction. For example, a boundary line where the underfill layer330and the molding layer340come into direct contact with each other may be positioned between both lateral side surfaces of the lower trench Tr1. Accordingly, based on the boundary line, an inner region of the lower trench Tr1which is in direct contact with the underfill layer330in the vertical direction may be filled with the underfill layer330, and an outer region of the lower trench Tr1which is in direct contact with the molding layer340may be filled with the molding layer340.

The plurality of first connection terminals SB1may respectively disposed on the plurality of lower pads Lp of the lower chip310.

The chip stacked structure320may be arranged on the lower chip310. In an embodiment, the chip stacked structure320may include first to fourth upper chips320_1,320_2,320_3, and320_4, which are sequentially stacked (e.g., in the vertical direction). However, embodiments of the present disclosure are not necessarily limited thereto and the number of the upper chips of the chip stacked structure320may vary. Each of the first to third upper chips320_1,320_2, and320_3may include the plurality of through electrodes TSV, the plurality of lower pads Lp, and the plurality of upper pads Up. The fourth upper chip320_4may include only the plurality of lower pads Lp and may not include the plurality of through electrodes TSV and the plurality of upper pads Up.

The first to third upper chips320_1,320_2, and320_3may respectively have a plurality of first upper trenches to a plurality of third upper trenches Tr2_1, Tr2_2, and Tr2_3positioned on upper surfaces thereof. For example, the first upper chip320_1may have the plurality of first upper trenches Tr2_1positioned on the upper surface thereof, the second upper chip320_2may have the plurality of second upper trenches Tr2_2positioned on the upper surface thereof, and the third upper chip3203may have the plurality of third upper trenches Tr2_3positioned on the upper surface thereof. In an embodiment, some of the first to third upper trenches Tr2_1, Tr2_2, and Tr2_3may be omitted. For example, in an embodiment the second upper trench Tr2_2and the third upper trench Tr2_3may be omitted, and only the plurality of first upper trenches Tr2_1may be positioned on the upper surface of the first upper chip320_1.

In an embodiment, the plurality of first upper trenches to the plurality of third upper trenches Tr2_1, Tr2_2, and Tr2_3may each have a circular shape in a plan view and a semi-circular shape in a cross section. In an embodiment, the plurality of first upper trenches to the plurality of third upper trenches Tr2_1, Tr2_2, and Tr2_3may respectively be arranged on the upper surfaces of the first to third upper chips320_1,320_2, and320_3to be spaced apart from each other along sides of the upper surfaces of the first to third upper chips320_1,320_2, and320_3. For example, the plurality of second upper trenches Tr2_2may be arranged on the upper surface of the second upper chip320_2to be spaced apart from each other along the edge of the upper surface of the second upper chip320_2.

In an embodiment, each of the plurality of first upper trenches to the plurality of third upper trenches Tr2_1, Tr2_2, and Tr2_3may overlap the underfill layer330in the vertical direction. Accordingly, each of the plurality of first upper trenches to the plurality of third upper trenches Tr2_1, Tr2_2, and Tr2_3may be filled with the underfill layer330.

The shape of the lower trench Tr1and the shapes of the plurality of first upper trenches to the plurality of third upper trenches Tr2_1, Tr2_2, and Tr2_3are not necessarily limited to those shown inFIGS.5A to5C. For example, unlike embodiments shown inFIGS.5A to5C, the lower trench Tr1may include a plurality of trenches each having a circular shape in a plan view, and each of the first to third upper trenches Tr2_1, Tr2_2, and Tr2_3may include a single trench having a serpentine shape in a plan view.

The plurality of second connection terminals SB2may be disposed between the first to fourth upper chips320_1,320_2,320_3, and320_4and between the first upper chip320_1and the lower chip310. For example, the plurality of second connection terminals SB2disposed between the first fourth upper chips320_1,320_2,320_3, and320_4and between the first upper chip320_1and the lower chip310may have an upper surface directly contacting a lower pad Lp and a lower surface directly contacting an upper pad Up.

The underfill layer330may be between the first to fourth upper chips320_1,320_2,320_3, and320_4and between the first upper chip320_1and the lower chip310.

The molding layer340may be arranged on the lower chip310and may surround the chip stacked structure320and the underfill layer330.

The semiconductor package300according to an embodiment may include the lower trench Tr1positioned on the upper surface of the lower chip310and the first to third upper trenches Tr2_1, Tr2_2, and Tr2_3respectively positioned on the upper surfaces of the first to third upper chips320_1,320_2, and320_3. Due to the lower trench Tr1and the first to third upper trenches Tr2_1, Tr2_2, and Tr2_3, thermo-mechanical stress applied to the upper surface of the lower chip310and the upper surface of each of the first to third upper chips320_1,320_2, and320_3may be reduced.

Also, the underfill layer330may fill the first to third upper trenches Tr2_1, Tr2_2, and Tr2_3, and the underfill layer330and the molding layer340may together fill the lower trench Tr1. Accordingly, an area in which each of the first to third upper chips320_1,320_2, and320_3directly contact the underfill layer330and an area in which the lower chip310, the underfill layer330, and the molding layer340directly contact each other may be increased. Accordingly, an adhesion strength between each of the first to third upper chips320_1,320_2, and320_3and the underfill layer330and an adhesion strength between the lower chip310, the underfill layer330, and the molding layer340may be increased.

FIG.6is a cross-sectional view illustrating a semiconductor package1000according to an embodiment.

Referring toFIG.6, the semiconductor package1000may include the semiconductor package100, a semiconductor chip400, a molding layer500, the redistribution structure600, and a package substrate700.FIG.6illustrates that the semiconductor package1000includes the semiconductor package100described with reference toFIGS.1A to1C. However, embodiments of the present disclosure are not necessarily limited thereto. For example, the semiconductor package1000may also include any one of the semiconductor packages100a,100b,200,200a,200b, and300described with reference toFIGS.2A to5C.

FIG.6illustrates that the semiconductor package1000includes one semiconductor package100. However, embodiments of the present disclosure are not necessarily limited thereto. For example, the semiconductor package1000may include one or more semiconductor packages100. Also, the semiconductor package1000may include a plurality of semiconductor packages selected from among the semiconductor packages100,100a,100b,200,200a,200b, and300described with reference toFIGS.1A to5C. For example, in an embodiment in which the semiconductor package1000includes two semiconductor packages, a first semiconductor package may be the semiconductor package100described with reference toFIGS.1A to1C, and a second semiconductor package may be the semiconductor package200described with reference toFIGS.3A to3C.

In an embodiment, the package substrate700may be a printed circuit board. For example, the package substrate700may be a multi-layer printed circuit board. However, embodiments of the present disclosure are not necessarily limited thereto.

In an embodiment, the package substrate700may include a substrate base. The substrate base may include a single base layer or a structure in which a plurality of base layers are stacked. In an embodiment, the substrate base may include at least one material selected from a phenol resin, an epoxy resin, and polyimide. The substrate base may include, for example, at least one material selected from among frame retardant 4 (FR4), tetrafunctional epoxy, polyphenylene ether, epoxy/polyphenylene oxide, bismaleimide triazine (BT), thermount, cyanate ester, polyimide, and liquid crystal polymer. However, embodiments of the present disclosure are not necessarily limited thereto.

The redistribution structure600may be arranged on the package substrate700. The redistribution structure600may be a substrate on which the semiconductor package100and the semiconductor chip400are mounted. In an embodiment, the redistribution structure600may be a redistribution interposer. In an embodiment, the redistribution structure600may include a redistribution insulating layer610and a redistribution pattern620.

The redistribution insulating layer610may cover the redistribution pattern620. The redistribution insulating layer610may include a plurality of insulating layers stacked in a vertical direction or may include a single insulating layer. In an embodiment, the redistribution insulating layer610may include, for example, a photo imageable dielectric (PID) or photosensitive polyimide (PSPI). However, embodiments of the present disclosure are not necessarily limited thereto.

The redistribution pattern620may include a plurality of redistribution lines621each extending in the first horizontal direction and a plurality of redistribution vias623extending at least partially through the redistribution insulating layer610. The plurality of redistribution lines621may extend in a horizontal direction along at least one surface among upper and lower surfaces of each of insulating layers configuring the redistribution insulating layer610. In an embodiment, at least some of the plurality of redistribution lines621may be positioned at a different vertical level from the remaining redistribution lines of the plurality of redistribution lines621. The plurality of redistribution vias623may electrically connect the plurality of redistribution lines621located at different vertical levels to each other.

A first connection terminal SBP may be disposed between the package substrate700and the redistribution structure600(e.g., in the vertical direction). The first connection terminal SBP may physically and electrically connect the package substrate700and the redistribution structure600to each other. In an embodiment, the first connection terminal SBP may include, for example, solder.

The semiconductor chip400may be arranged on the redistribution structure600. In an embodiment, the semiconductor chip400may be a memory chip or a logic chip. The memory chip may include, for example, a volatile memory chip such as a DRAM or SRAM chip, or a non-volatile memory chip such as a PRAM, MRAM, FeRAM, or RRAM chip. Also, the logic chip may include, for example, a microprocessor, an analog device, or a digital signal processor. However, embodiments of the present disclosure are not necessarily limited thereto.

The semiconductor chip400may include a semiconductor substrate410and a chip pad420. The semiconductor substrate410may include a semiconductor material. The semiconductor substrate410may include a conductive region, for example, a well doped with impurities. The semiconductor substrate410may have various device isolation structures, such as an STI structure.

A second connection terminal BP may be disposed between the semiconductor chip400and the redistribution structure600. The second connection terminal BP may be in direct contact with the chip pad420of the semiconductor chip400and the redistribution structure600and may physically and electrically connect the semiconductor chip400and the redistribution structure600to each other. In an embodiment, the second connection terminal BP may include a material substantially the same as or similar to that of the first connection terminal SBP.

The molding layer500may be arranged on the redistribution structure600and may cover at least a portion of the semiconductor chip400and at least a portion of the semiconductor package100. The molding layer500may include a material substantially the same as or similar to that of the molding layer140described with reference toFIGS.1A to1C.

FIGS.7A and7Bare cross-sectional views illustrating a method of manufacturing the semiconductor package100according to embodiments of the present disclosure.

Referring toFIG.7A, firstly, the lower chip110having the lower trench Tr1positioned on the upper surface thereof may be provided. The chip stacked structure120including the first to third upper chips120_1,120_2,120_3respectively having first to third upper trenches Tr2_1, Tr2_2, and Tr2_3on upper surfaces thereof and the fourth upper chip120_4may then be mounted on the lower chip110. An underfill process may then be performed, and an underfill material layer130P may be filled between the lower chip110and the first upper chip120_1and between the first to fourth upper chips120_1,120_2,120_3, and120_4. In a process in which the underfill material layer130P is filled, the first to third upper trenches Tr2_1, Tr2_2, and Tr2_3may be filled with the underfill material layer130P.

Referring toFIG.7B, a thermal bonding process may be performed on a resultant product ofFIG.7A. Accordingly, the underfill layer130may be formed by melting underfill material layers130P ofFIG.7Ainto one body. In a process in which the underfill layer130is formed, a partial region of the lower trench Tr1may be filled with the underfill layer130.

The molding layer140may then be formed in a resultant product ofFIG.7B. In an embodiment, a remaining region of the lower trench Tr1may be filled with the molding layer140. The semiconductor package100shown inFIGS.1A to1Cmay be manufactured by forming the molding layer140on the lower chip110to surround the underfill layer130and the chip stacked structure120.

While the present disclosure has been particularly shown and described with reference to non-limiting embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure.