Asynchronous low dropout regulator

A low dropout regulator that produces an output includes a comparison circuit, configured to compare a signal representative of the output and a reference signal to produce a comparison result. The low dropout regulator also includes a loop controller, coupled to the comparison circuit, configured to generate an output circuit control signal based at least in part on the comparison result. The low dropout regulator also includes an output circuit, comprising two or more output stages, configured to adjust a number of active output stages of the two or more output stages based on the output circuit control signal.

BACKGROUND

1. Technical Field

The techniques described herein relate generally to low dropout regulators.

2. Discussion of the Related Art

Low dropout regulators are used in integrated circuits as a way to regulate an output voltage. Low dropout regulators are often designed to produce a regulated output voltage even in conditions where the output voltage approaches the supply voltage.

SUMMARY

Some embodiments relate to a low dropout regulator that produces an output, comprising: a comparison circuit, configured to compare a signal representative of the output and a reference signal to produce a comparison result; a loop controller, coupled to the comparison circuit, configured to generate an output circuit control signal based at least in part on the comparison result; and an output circuit, comprising two or more output stages, configured to adjust a number of active output stages of the two or more output stages based on the output circuit control signal.

The comparison circuit may be coupled to the loop controller through a pulse generator and the pulse generator may be configured to generate a pulse in response to a change in the comparison result.

The loop controller may be configured to generate the output circuit control signal based on the pulse.

The low dropout regulator may further comprise two or more buffer amplifiers, coupled between the loop controller and the output circuit.

The pulse generator may be configured to generate a first type of pulse if the output is greater than the reference signal.

The pulse generator may be configured to generate a second type of pulse if the output is less than the reference signal.

The loop controller may be configured to enable at least one output stage of the two or more output stages when the output is less than the reference signal.

The loop controller may be configured to disable at least one output stage of the two or more output stages when the output is greater than the reference signal.

The low dropout regulator may further comprise a timer check circuit, configured to compare a running time to a first reference time to produce a time check signal.

The loop controller may be further configured to generate the output circuit control signal based on the time check signal.

The time check signal may be generated when the running time exceeds the first reference time.

The running time may begin when the output circuit adjusts the number of active output stages.

The running time may being when a previous comparison result changed state.

The low dropout regulator may further comprise a second comparison circuit, configured to compare a signal representative of the output and a second reference signal to produce a second comparison result.

The loop controller may be further coupled to the second comparison circuit and configured to generate the output circuit control signal based at least in part on the comparison result and the second comparison result.

The low dropout regulator of claim may further comprise a second pulse generator, coupled between the second comparison circuit and the pulse generator, configured to generate a second pulse in response to a change in the second comparison result.

Some embodiments relate to a system, comprising: a load circuit comprising a plurality of sub-circuits; a first low dropout regulator coupled to a first terminal of the load circuit, configured to provide a first output of the first low dropout regulator to the first terminal; and a second low dropout regulator coupled to a second terminal of the load circuit, configured to provide a second output of the second low dropout regulator to the second terminal,

wherein the first low dropout regulator is configured to send a first indication of a change of level of the first output to the second low dropout regulator.

The second low dropout regulator may be configured to provide the second output based on the first indication.

The second low dropout regulator may be configured to send a second indication of a change of level of the second output voltage to the first low dropout regulator.

The first low dropout regulator may be configured to provide the first output based on the second indication.

The foregoing summary is provided by way of illustration and is not intended to be limiting.

DETAILED DESCRIPTION

An integrated low dropout (ILDO) regulator may be an important part of many integrated circuit solutions. ILDO regulators ideally provide an controllable output voltage level that can approach the supply voltage level while maintaining low fluctuation and noise. ILDO regulators may adjust their output in response to a change in the load circuit impedance, such that a constant or near-constant power, voltage, or current is provided at the output. However, typical ILDO regulators require advanced notice of change in loading conditions, indicating that the load impedance will change at a specific point in time, to provide suitable output regulation. Such ILDO regulators with advanced notification systems may not provide sufficient control when the load circuit needs a rapid adjustment in supplied current, voltage, or power from the ILDO regulator. Additionally, if the advanced notification signal is missed or delayed, the ILDO regulator may not provide the correct output voltage, current, or power level and the load circuit may receive an insufficient voltage, current, or power level, or one that is too high. Typical ILDO regulators often are synchronized to a clock cycle, which may introduce unnecessary delays in changing the supplied output voltage or current as the ILDO regulator may have to wait for a clock edge before adjusting its output voltage, current, or power level. Described herein is an ILDO regulator with an asynchronous control system capable of rapidly adjusting to changes in load circuit impedance.

Prior to discussing such control systems, the presence of parasitics in circuitry associated with an ILDO regulator will be discussed.FIG. 1shows a circuit board100including package components110and off-package components140. The package components110may comprise an integrated low dropout (ILDO) regulator120coupled to a load circuit130. The ILDO regulator120may provide its output to the load circuit130. The off-package components140may have parasitic inductances, capacitances, and/or resistances as well as an external power management integrated circuit (PMIC). For example, off-package inductors may have parasitic capacitance between the winding turns of the inductors. In another example, off-package capacitors may have parasitic resistance at various frequencies. Additionally, the package components110may have parasitic inductance, capacitance, and/or resistance through similar mechanisms, as well as couplings between the package and non-package components. Any or all of the parasitic effects described herein may vary over time. Additionally, the impedance of the load circuit130may vary over time. For example, if the load circuit130is coupled to another circuit, the reflected impedance from the coupling may change over time, changing the impedance of the load circuit130seen by the ILDO regulator120. In another example, the impedance of the load circuit130may vary due to time-varying parasitic effects within the load circuit130. In some embodiments, the ILDO regulator120may be designed to provide a power, voltage, or current output to the load circuit130in a way that mitigates the parasitic effects and the variance in load impedance. It should be appreciated that the off-package components140shown inFIG. 1are merely an example, and in some embodiments no off-package components may be used. In some embodiments, no on-chip package components may be used other than the ILDO regulator120and the load circuit130.

The load circuit130may be any circuit receiving power, current, or voltage from the ILDO regulator120. The impedance of the load circuit130may vary over time due to a number of effects, such as a variation in the size of the load or the variation in parasitics. Accordingly, in some embodiments the ILDO regulator120may adapt to the variations in the impedance of the load circuit as well as the parasitics of the package components110and off-package components140, as will be described in further detail below.

FIG. 2Ashows an embodiment of an ILDO regulator200. The ILDO regulator200may comprise a control circuit260and a switch circuit250. The control circuit260may receive a feedback signal VFB and a reference signal VREF1at the comparator210. VFB may be a signal indicating a voltage level at the output of the ILDO regulator200. For example, VFB may be the output voltage of the ILDO regulator200in some embodiments. In other embodiments, VFB may be a scaled representation of the output voltage of the ILDO regulator200. In other embodiments, the feedback signal provided to the comparator210may be representative of a current or power provided to the load circuit. VREF1may be a reference voltage, which may be preset in a memory of the system, set by a user of the system, or established through any suitable means. In other embodiments, the reference signal may be a reference current or power. The comparator210may compare the feedback and reference signals and output a COMP signal indicating a change of state between the two signals. For example, if VFB is initially lower than VREF1and then becomes higher than VREF1, comparator210may generate a first COMP signal indicative of the change of state of VFB. Alternatively, if VFB is initially higher than VREF1and then becomes lower than VREF1, comparator210may generate a second COMP signal, indicative of the change of state of VFB, different from the first COMP signal. For example, the first COMP signal may be a pulse with a first shape, duration and/or magnitude, and the second COMP signal may be a pulse with a second shape, duration and/or magnitude. In some embodiments, the first COMP signal and second COMP signal may be different and may indicate the which state VFB is in relative to VREF1(e.g., VFB fell below VREF1or VFB rose above VREF1). While the examples given herein are in terms of voltage comparison, it should be appreciated that current or power could be compared instead of voltage. The change in level of VFB relative to VREF1may be used to determine a change a level of the output voltage provided by the ILDO regulator200to the load circuit. Accordingly, the ILDO regulator200may adjust its output voltage to compensate for the change in level of VFB relative to VREF1.

The output COMP of the comparator210may be sent to the pulse generator220. The output COMP may cause the pulse generator220to generate a pulse, which may be sent to the loop controller230. The pulse generator220may be any circuit suitable for generating a signal representative of the state change detected by the comparator210. In some embodiments, the pulse generator220may generate a first pulse type if the output COMP of the comparator210indicates that VFB has changed state to be above VREF1and may generate a second pulse type if the output COMP of the comparator210indicates that VFB has changed state to be below VREF1. In some embodiments, the pulse generator220may generate the same pulse for any change of state detected by the comparator210. In such embodiments, the comparator210may be connected to the loop controller230as well as the pulse generator220, so that when the loop controller230receives a pulse from the pulse generator220, it may receive the COMP signal produced by the comparator210to indicate the level of VFB relative to VREF1. It should be appreciated that in some embodiments no pulse generator220may be used, and the output of the comparator210may be passed to the loop controller230. In such embodiments, a level of the COMP signal may indicate the level of VFB relative to VREF1, and the loop controller230may respond to the change in state of the COMP signal by using the level of the COMP signal to make a determination of a number of switches in the switch circuit250to enable or disable, as will be explained in further detail below.

The loop controller230may receive the signal PULSE from the pulse generator220and/or the signal COMP from the comparator210, and make a determination of a number of switches in the switch circuit250to enable or disable. In some embodiments where the loop controller230receives just the signal PULSE from the pulse generator220, the signal PULSE may correspond to the state of the output COMP of the comparator210. PULSE may correspond to a first pulse shape, magnitude and/or duration when COMP is at a first level and may correspond to a second pulse shape, magnitude and/or duration when COMP is at a second level. In some embodiments where the loop controller receives both the signal PULSE and the output COMP, PULSE may be the same pulse shape regardless of the level of COMP, and the loop controller230may adjust the number of enabled switches in the switch circuit250based on the level of COMP when the signal PULSE is received. In some embodiments where the loop controller230receives COMP and not PULSE, the loop controller230may adjust the number of enabled switches in the switch circuit250when the signal COMP changes levels. The number of enabled switches in the switch circuit250may correspond to the level of the output voltage VOUT of the ILDO regulator200. For example, if the loop controller230receives an indication that the feedback voltage VFB is low relative to VREF1, the loop controller230may generate a signal to enable more switches in the switch circuit250than are currently enabled, so as to increase the output voltage of the ILDO regulator200. In such an example, if there are currently five switches enabled in the switch circuit250, and the loop controller230receives and indication that VFB is low relative to VREF1, the loop controller230may generate a signal to enable a sixth switch in the switch circuit250. Alternatively, the loop controller230may receive an indication of the magnitude of the difference between VFB and VREF1and may enable a proportional number of switches in the switch circuit250. In another example, if the loop controller230receives an indication that the feedback voltage VFB is high relative to VREF1, the loop controller230may generate a signal to disable additional switches in the switch circuit250, so as to decrease the output voltage of the ILDO regulator200. InFIG. 2A, N switches are shown in the switch circuit250, where N is any positive integer greater than one. The loop controller230may be any controller suitable for determining a number of switches in the switch circuit250to enable and generating a signal to enable the switches, such as a field programmable gate array (FPGA), a microprocessor, or a hardware logic circuit.

The signal from the loop controller230may be passed through the optional buffer circuit240before reaching the switch circuit250. The buffer circuit240may include N buffer amplifiers, with each buffer amplifier connected from the loop controller230to a corresponding switch of the switch circuit250. Thus, each buffer amplifier of the buffer circuit240may provide a separate signal path between the loop controller230to each switch of the switch circuit250. The buffer circuit240may adjust the impedance level seen by the output of the loop controller230and the input of the switch circuit250, to drive the switches of the switching circuit250.

The switch circuit250may include N switches, controlled by the loop controller230, providing a conduction path between a high reference voltage VIN and the output VOUT of the ILDO regulator200. The high reference voltage VIN may be provided through any known voltage source, such as a power supply or a battery. The output VOUT of the ILDO regulator200may be connected to the load circuit as shown inFIG. 1.

FIG. 2Bshows an example of the buffer circuit240and the switch circuit250. In this example, N may be equal to 3, though any positive integer greater than or equal to 2 may be used. The loop controller230provides three output signals, one for each of the switches in the switch circuit250. The output signals from the loop controller230may go through buffer amplifiers in the buffer circuit240, before being connected to the control terminals (e.g., gates) of switches in the switch circuit250. The switches in the switch circuit250may be connected in parallel, such that turning on more switches produces a higher output voltage or current at VOUT, and turning off more switches produces a lower output voltage or current at VOUT. It should be appreciated that the configuration of buffer amplifiers and switch connections shown is merely one example, and any suitable implementation that allows for the control by the loop controller230of switches within the switch circuit250may be used.

In some embodiments, it may be desirable to provide multiple reference voltages, such that the loop controller may adjust the output voltage relative to the multiple reference voltages. Such embodiments may allow the output voltage to be kept within a range determined by the multiple reference voltage levels, or within multiple ranges determined by the multiple reference voltage levels.FIG. 3shows another embodiment of an ILDO regulator300comprising a first branch330and a second branch340. The second branch340of the ILDO regulator300may comprise a second comparator310and a second pulse generator320. The second comparator310may receive as inputs the feedback voltage VFB as well as a second reference voltage VREF2. VREF2may be the same reference voltage or a different reference voltage as VREF1. The comparator310may compare the VFB and VREF2signals and indicate a change of state between the two signals through the signal COMP2. For example, if VFB is initially lower than VREF2and then becomes higher than VREF2, comparator310may generate a signal COMP2indicative of the change of state. Alternatively, if VFB is initially higher than VREF2and then becomes lower than VREF2, comparator310may generate a signal COMP2indicative of the change of state. The output COMP2of the comparator310may go to the pulse generator320or the loop controller230.

The change in state detected and outputted by the comparator310may cause the pulse generator320to generate a pulse PULSE2, which may be sent to the loop controller230. The pulse generator320may be any circuit suitable for generating a signal representative of the state change detected by the comparator310. In some embodiments, the pulse generator320may generate a first pulse type if the comparator310detects that VFB has changed state to be above VREF2and may generate a second pulse type if the comparator310detects that VFB has changed state to be below VREF2. In some embodiments, the pulse generator320may generate a pulse or signal PULSE2periodically unless the comparator310detects a change in state of VFB relative to VREF2. In some embodiments, the pulse generator320may generate the same pulse for any change of state detected by the comparator310. It should be appreciated that in some embodiments no pulse generator320may be used, and the output COMP2of the comparator310may be passed to the loop controller230. In some embodiments, the pulse generator320may be used and the output COMP2of the comparator310may be passed to the loop controller230as well. In such an embodiment, the loop controller230may use the outputs of the comparators210and310in conjunction with the outputs of the pulse generators220and320to determine the priorities of the controllers if two state changes are detected. For example, if VFB begins below VREF1and VREF2but then rises rapidly to exceed both VREF1and VREF2, with VREF2>VREF1in this example, the loop controller230may determine that it should handle the event generated by the second branch340, that is the second comparator310and the second pulse generator320, since handling the event on the second branch340will inherently satisfy the event on the first branch330due to the relationship between the two reference voltages.

While two branches330and340are shown inFIG. 3, a branch being a signal chain receiving a signal indicative of the output voltage, a threshold, and generating an event detection signal that is sent to the loop controller230, it should be appreciated that any number of branches may be used. The signal indicative of the output voltage may be a voltage or current signal, with or without scaling. For example three branches with three thresholds may be used, or four branches with four thresholds may be used. Additionally, a single branch may use multiple thresholds if a suitable comparator is used. It should be appreciated that in some embodiments, a single comparator may be used with two thresholds VREF1and VREF2, rather than two comparators. The output of the comparator may be a tristate signal indicating the level of VFB relative to the two references or the comparator may have two outputs, each output indicating the level of VFB relative to one of the two references.

The ILDO regulator300with two branches may be used to monitor the output voltage VOUT and keep it within predetermined bounds. For example, VREF1may be set to be a lower bound voltage, and VREF2may be set to be an upper bound voltage. If VOUT, which is intended to be between VREF1and VREF2during operation of the system, increases due to various parasitic or loading effects, such that VFB exceeds the upper bound voltage VREF2, the comparator310will trigger an event, and send a signal indicating the change of state to the loop controller230and/or the pulse generator320. If the comparator310sends a signal to the pulse generator320, the pulse generator320will subsequently generate and send a pulse to the loop controller230corresponding to the change of state of the comparator310. The loop controller230will subsequently decrease the number of active switches in the switch circuit250to lower the output voltage VOUT. The number of switches deactivated may be a fixed amount (e.g., the loop controller disables one additional switch for each event) or may be a proportional amount (e.g., the loop controller disables a number of switches proportional to how much larger VOUT is than the reference voltage). If VOUT decreases due to various parasitic or loading effects such that VFB falls under the lower bound voltage VREF1, the comparator210will trigger an event, and send a signal indicating the change of state to the loop controller230and/or the pulse generator220. If the comparator210sends a signal to the pulse generator220, the pulse generator220will subsequently generate and send a pulse to the loop controller230corresponding to the change of state of the comparator210. The loop controller230will subsequently increase the number of active switches in the switch circuit250to increase the output voltage VOUT. The number of switches activated may be a fixed amount (e.g., the loop controller enables one additional switch for each event) or may be a proportional amount (e.g., the loop controller enables a number of switches proportional to how much smaller VOUT is than the reference voltage).

In some embodiments, it may be desirable to control the output voltage relative to a timing reference. If the output voltage stays at a fixed level for a time longer than a reference time, it may be desirable to adjust the output voltage level to provide fine control over the output voltage level. For example, if the desired output voltage level is 0.70V, and the output voltage level stays at 0.69V for longer than a predetermined amount of time, it may be desirable to increase the output voltage level even if the resulting level would be above 0.70V, so that the average output voltage over an extended period of time approaches 0.70V.

FIG. 4shows a single branch ILDO regulator400additionally comprising a timer check circuit410. The timer check circuit410may comprise a time comparison circuit and a running timer. In some embodiments, the running timer may be separate from the timer check circuit410and the timer check circuit410may receive a timing signal from the running timer. When the comparator210detects an event based on the relative values of the feedback voltage VFB and the reference voltage VREF1, the comparator210may send a signal indicative of the event to the timer check circuit410and to at least one of the pulse generator220and the loop controller230. The timer check circuit410may compare the value of a running timer at the time the event from the comparator210is received to a threshold time T1. The running timer may be any suitable time keeping circuit, such as an oscillator, a clock input, or a counter. The threshold time may be a preset time to regulate the action taken by the loop controller230. Additionally, the timer check circuit410may also or alternatively receive the feedback voltage VFB from the comparator210or directly from the input to the ILDO regulator400. In some embodiments, the timer check circuit may be used to prevent the output voltage VOUT from remaining at a single level for longer than a determined period of time. For example, it may be acceptable for the output voltage to be slightly above or slightly below the desired output voltage for a short period of time, but undesirable for the output voltage to remain at that level. Accordingly, if the timer check circuit410detects that VFB is at a constant undesired level for a time that exceeds the threshold T1, then the timer check circuit410may trigger the loop controller230to correspondingly adjust the number of active switches in the switch circuit250, even though the comparator has not caused an event. The time based control may allow for finer control of the output voltage VOUT in the system by using the voltage level based comparison to make changes to the output voltage and then readjusting the voltage level over time based on the timer control.

FIG. 5shows a double branch ILDO regulator500, with each branch having a timer check circuit. When the comparator310detects an event based on the relative values of the feedback voltage VFB and the reference voltage VREF2, the comparator may send a signal indicative of the event to the timer check circuit510and to at least one of the pulse generator320and the loop controller230. The timer check circuit510may compare the value of a running timer at the time the event from the comparator310is received to a threshold time T2. The running timer may be any suitable time keeping mechanism, such as an oscillator, a clock input, or a counter. The threshold time may be a preset time to regulate the action taken by the loop controller230, as described above. Additionally, the timer check circuit510may also or alternatively receive the feedback voltage VFB from the comparator310or directly from the input to the ILDO regulator500. However, with multiple timer check circuits intervals may be set to regulate the action taken by the loop controller230. For example, if T1is less than T2, then in the case that the running timer reaches T1with VOUT at an undesirable level, the loop controller230may set the number of active switches in a first configuration. If the running timer reaches a time between T1and T2with VOUT at an undesirable level, the loop controller230may set the number of active switches in a second configuration. While two separate timer check circuits410and510are shown inFIG. 5, it should be appreciated that the two timer check circuits could be implemented as a single time with multiple inputs and thresholds. Additionally, it should be appreciated that while two branches are shown inFIG. 5, any number of branches and timer check circuits may be used to provide finer control of the output voltage VOUT.

In some embodiments the load circuit at the output of the ILDO regulator may comprise a mesh circuit. In such instances, the providing the output of the ILDO regulator to one end of the mesh circuit may cause an uneven power, voltage, or current distribution across the load circuit. Described herein is a system with multiple ILDO regulators to provide power, voltage, or current at multiple points across the load circuit, wherein the ILDO regulators can communicate to maintain the stability of the system or otherwise improve control of the system.

FIG. 6shows a system600comprising a first ILDO regulator620and a second ILDO regulator630coupled across a load circuit610. In embodiments where the load circuit610is equivalent to a resistive mesh, if a single ILDO regulator is used and connected to one side of the load circuit610, the mesh may cause the voltage from the ILDO regulator to be unevenly dissipated across the load circuit610, resulting in inefficient operation and high power loss. Accordingly, the system600uses a first ILDO regulator620on a first side of the load circuit610and a second ILDO regulator630on a second side of the load circuit610. By providing equal voltage on separate sides of the load circuit610, the voltage dissipation across the mesh may be reduced, and a more even power consumption may be achieved. However, if the first ILDO regulator620and the second ILDO regulator630provide voltage to the mesh independently, the output voltages may dampen each other if they are not adjusted in a synchronous manner.

FIG. 7shows a system700with the first and second ILDOs620and630coupled across the load circuit610. The load circuit610comprises N (unrelated to the number of switches in the ILDO switching circuit) sub-circuits arranged in a mesh network, with N being a positive integer greater than or equal to one. Each of the sub-circuits710,720, and730may act as a sub-circuit within the load circuit610coupled to the first and second ILDOs620and630, but the resistances between each of the sub-circuits710,720, and730may cause uneven power to be dissipated across them if the first ILDO regulator620and the second ILDO regulator630operate independently. Accordingly, the first ILDO regulator620and the second ILDO regulator630may exchange control signals over a communication channel. For example, in a unilateral embodiment, the loop controller of the first ILDO regulator620may receive signals from the comparator, pulse generator, and/or the timer check circuit of the second ILDO regulator630. Thus, if the second ILDO regulator630detects an event on the second side of the load circuit610that does not occur on the first side of the load circuit610, the first ILDO regulator620may be notified and the loop controller of the first ILDO regulator620may change the number of active switches to adjust the output voltage of the first ILDO regulator620and prevent a damping effect from occurring through uneven voltage applied to the load circuit610. In another bidirectional embodiment, both ILDOs620and630may communicate event information to each other based on their timer check circuit, pulse generator, and/or comparators signals to maintain synchronized voltage output to the load circuit610. While two ILDOs are shown inFIGS. 6 and 7, it should be appreciated that any number of ILDOs may be applied to the load circuit and synchronized.