Method of manufacturing semiconductor device

A method of manufacturing a semiconductor device includes: forming a metal film containing Al on a surface of a substrate product including a substrate and a nitride semiconductor layer on the substrate, the metal film covering a via hole forming predetermined region, and the surface of the substrate product being located on the nitride semiconductor layer side, forming an etching mask having an opening for exposing the via hole forming predetermined region on a back surface of the substrate product, the back surface of the substrate product being located on the substrate side, and forming a via hole in the substrate product by reactive ion etching, the via hole reaching the surface from the back surface and exposing the metal film. In the forming of the via hole, a reaction gas containing fluorine is used during a period at least including a termination of etching.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims the priority benefit of Japanese Application No. JP2018-140011 filed on Jul. 26, 2018, the entire contents of which are incorporated herein by references.

TECHNICAL FIELD

The present disclosure relates to a method of manufacturing a semiconductor device.

BACKGROUND

Japanese Unexamined Patent Publication No. 2009-212103 discloses a method of manufacturing a semiconductor device. In such a method of manufacturing a semiconductor device, openings reaching a surface of an insulating substrate are formed in a GaN layer and an n-type AlGaN layer. A Ni layer connected to a source electrode is formed in the opening as a conductive etching stopper. A via hole reaching the Ni layer from a back surface of the insulating substrate is formed in the insulating substrate. In addition, a via wire is formed in the via hole.

When a semiconductor device having a nitride semiconductor layer is manufactured on a substrate, a via hole penetrating through the substrate and the nitride semiconductor layer may be formed. In this case, a metal film is first formed as an etching stopper on the nitride semiconductor layer. Subsequently, a via hole is formed from the back surface of the substrate to the metal film by reactive ion etching (RIE). In the RIE for the nitride semiconductor layer, for example, chlorine-based gas is used as reaction gas. As a material of the metal film, Ni having sufficient etching resistance against chlorine plasma can be used. However, the Ni film has a disadvantage of high electrical resistance. In many cases, the metal film is conducted through a back electrode and the via hole. Therefore, it is preferable that the electrical resistance of the metal film is low.

SUMMARY

A method of manufacturing a semiconductor device according to an embodiment of the present disclosure includes forming a metal film containing Al on a surface of a substrate product including a substrate and a nitride semiconductor layer provided on the substrate, the metal film covering a via hole forming predetermined region in the substrate product, and the surface of the substrate product being located on the nitride semiconductor layer side; forming an etching mask having an opening for exposing the via hole forming predetermined region on a back surface of the substrate product, the back surface of the substrate product being located on the substrate side; and forming a via hole in the substrate product by reactive ion etching, the via hole reaching the surface from the back surface and exposing the metal film. In the forming the via hole, a reaction gas containing fluorine is used during a period at least including a termination of etching.

DETAILED DESCRIPTION

Specific examples of a method of manufacturing a semiconductor device according to an embodiment of the present disclosure will be described below with reference to the drawings. Further, it is to be understood that the present disclosure is not limited to these examples but is defined by the scope of the claims and includes all modifications within the meaning and scope equivalent to the claims. In the following description, the same elements are denoted by the same reference numerals in the description of the drawings, and redundant explanations are omitted.

FIG. 1is a plan view showing a transistor1A as a semiconductor device according to one embodiment of the present disclosure.FIG. 2is a cross-sectional view taken along the line II-II of the transistor1A shown inFIG. 1.FIG. 3is a cross-sectional view taken along the line III-III of the transistor1A shown inFIG. 1. For the sake of explanation, insulating films31and32are omitted inFIG. 1.

As shown inFIGS. 1 and 2, a transistor1A according to the present embodiment includes a substrate3, a nitride semiconductor layer10provided on the substrate3, a source electrode21, a drain electrode22, and a gate electrode23. The source electrode21, the drain electrode22and the gate electrode23are provided on the nitride semiconductor layer10. The substrate3is a substrate for crystal growth and has a flat surface. The substrate3may be, for example, a SiC substrate. The thickness of the substrate3is, for example, in the range of 75 μm to 150 μm, and in one example, 100 μm. The thickness of the nitride semiconductor layer10is, for example, in the range of 0.5 μm to 3.0 μm, and in one example, 1.0 μm.

The transistor1A according to the present embodiment is a high electron mobility transistor (HEMT). That is, the nitride semiconductor layer10has at least a channel layer12and an electron supply layer (barrier layer)13. A two-dimensional electron gas (2DEG) is generated at an interface between the channel layer12and the electron supply layer13, and a channel region is formed. The channel layer12is a layer epitaxially grown on a surface of the substrate3. A buffer layer11may be interposed between the channel layer12and the substrate3. A region in the channel layer12and near the interface between the electron supply layer13and the channel layer12functions as the channel region. The buffer layer11is, for example, an AlN layer. A thickness of the buffer layer11is, for example, 20 nm. The channel layer12is, for example, a GaN layer. A thickness of the channel layer12is, for example, 1 μm. The electron supply layer13is a layer epitaxially grown on the channel layer12. A thickness of the electron supply layer13is, for example, 20 nm. The electron supply layer13is, for example, an AlGaN layer, an InAlN layer, or an InAlGaN layer. In an example, the electron supply layer13is made of Al0.25Ga0.75N. The electron supply layer13may be n-type. Further, the nitride semiconductor layer10may further have a cap layer (not shown) on the electron supply layer13. In this case, a thickness of the cap layer is, for example, 5 nm. The cap layer is, for example, a GaN layer, and may be an n-type.

As shown inFIG. 1, the nitride semiconductor layer10has an active region10aand an inactive region10b. The active region10ais a region operating as a transistor. The inactive region10bis a region electrically inactivated by injecting ions such as argon (Ar) and protons (H) into the nitride semiconductor layer10, for example. The inactive region10bsurrounds the active region10a, and is provided for electrical separation between the transistors1A adjacent to each other and for limiting an operating region of the transistor1A.

The source electrode21and the drain electrode22are provided on the active region10aof the nitride semiconductor layer10and are in contact with the active region10a. In the present embodiment, three source electrodes21and two drain electrodes22are provided on one active region10a. The source electrode21and the drain electrode22are aligned along a direction D1, and each have an elongated shape in which a direction D2that intersects (e.g., orthogonal to) the direction D1is a longitudinal direction. As shown inFIG. 2, the source electrode21includes an ohmic metal layer21aprovided on the active region10aand a wiring layer21bprovided on the ohmic metal layer21a. Similarly, the drain electrode22includes an ohmic metal layer22aprovided on the active region10aand a wiring layer22bprovided on the ohmic metal layer22a. The ohmic metal layers21aand22aare formed by alloying a laminated structure of a first layer, which is a titanium (Ti) layer or a tantalum (Ta) layer, and a second layer, which is an aluminum (Al) layer, by a heat treatment. The Al layer before the heat treatment may be sandwiched by the Ti layer or the Ta layer in a thickness direction of the nitride semiconductor layer10. A thickness of the Ti layer or the Ta layer is in the range of 5 nm to 20 nm, for example, 10 nm in one embodiment. A thickness of the Al layer is in the range of 50 nm to 1000 nm, for example, 500 nm in one embodiment. The wiring layers21band22bare conductive metal layers having small electric resistance. The wiring layers21band22bare formed by, for example, Au plating and have a thickness of, for example, 5 μm.

The source electrode21and the drain electrode22may be in contact with the electron supply layer13or may be in contact with the cap layer provided on the electron supply layer13. Alternatively, the source electrode21and the drain electrode22are provided on the channel layer12exposed by removing a part of the electron supply layer13, and are in contact with the vicinity of the interface between the electron supply layer13and the channel layer12.

The gate electrode23is provided on the active region10aof the nitride semiconductor layer10. The gate electrode23is positioned between the source electrode21and the drain electrode22in the direction D1. The gate electrode23extends linearly with the direction D2as the longitudinal direction. In one example, the gate electrode23has a laminated structure of, for example, a nickel (Ni) layer, a palladium (Pd) layer, and a gold (Au) layer. A thickness of the Ni layer is, for example, 100 nm, a thickness of the Pd layer is, for example, 50 nm, and a thickness of the Au layer is, for example, 500 nm. In addition, in another example, the gate electrode23has a laminated structure of, for example, a Ni layer, a platinum (Pt) layer, and a Au layer. A thickness of the Ni layer is, for example, 20 nm, a thickness of the Pt layer is, for example, 20 nm, and a thickness of the Au layer is, for example, 600 nm. The Ni layer is in Schottky contact with the nitride semiconductor layer10.

As shown inFIG. 2, the transistor1A further includes insulating films31and32and a back electrode24. The insulating films31and32protect the nitride semiconductor layer10, the source electrode21, the drain electrode22, and the gate electrode23. The back electrode24is a metal film provided on a back surface3bof the substrate3. The back electrode24is made of a metal such as gold (Au).

The insulating film31is provided on the nitride semiconductor layer10and is in contact with the nitride semiconductor layer10, and covers a surface10cof the nitride semiconductor layer10exposed from the source electrode21, the drain electrode22, and the gate electrode23. A gate opening exposing the nitride semiconductor layer10is provided in the insulating film31, and a portion of the gate electrode23is embedded in the gate opening. The gate electrode23is in contact with the nitride semiconductor layer10through the gate opening. A length (gate length) of the gate opening in the direction D1is, for example, 0.5 μm. The insulating film31is, for example, an insulating Si compound film, and is a SiN film in one example. A thickness of the insulating film31is, for example, 100 nm.

The insulating film31has an opening on the ohmic metal layer21aof the source electrode21, and the wiring layer21bof the source electrode21is provided on the opening. The wiring layer21bis in contact with the ohmic metal layer21athrough the opening. The insulating film31also has an opening on the ohmic metal layer22aof the drain electrode22, and the wiring layer22bof the drain electrode22is provided on the opening. The wiring layer22bis in contact with the ohmic metal layer22athrough the opening.

The insulating film32is provided on the insulating film31and is in contact with the insulating film31. The insulating film32covers the source electrode21, the drain electrode22, the gate electrode23, and the insulating film31. The insulating film32is, for example, an insulating Si compound film, and is a SiN film in one example. A thickness of the insulating film32is, for example, 100 nm.

As shown inFIG. 1, the transistor1A further includes a source pad25, a drain pad26, and a gate pad27. The source pad25, the drain pad26, and the gate pad27are provided on the inactive region10bof the nitride semiconductor layer10. The source pad25and the gate pad27are provided on one side of the active region10ain the direction D2, and the drain pad26is provided on the other side of the active region10ain the direction D2. Therefore, the active region10ais positioned between the source pad25and the gate pad27, and between the drain pad26and the gate pad27. The source pad25, the drain pad26, and the gate pad27are integrally connected to the source electrode21, the drain electrode22, and the gate electrode23extending from the active region10ato the inactive region10b, respectively. As a result, the pads25to27and the electrodes21to23are electrically connected to each other, respectively. The drain pad26and the gate pad27provide a region for wire bonding with external circuits.

As shown inFIG. 3, the source pad25includes a lower layer25aprovided on the inactive region10band in contact with the inactive region10b, and an upper layer25bprovided on the lower layer25a. The lower layer25ais made of a metal including aluminum (Al). In one example, the lower layer25ahas the same configuration as that of the ohmic metal layer21aof the source electrode21. That is, the lower layer25ais embedded in an opening31aformed in the insulating film31, and is formed by alloying a laminated structure of a first layer, which is a Ti layer or a Ta layer, and a second layer, which is an Al layer, by a heat treatment. The Al layer before the heat treatment may be sandwiched by the Ti layer or the Ta layer in a thickness direction of the nitride semiconductor layer10. A thickness of the Ti layer or the Ta layer, and the Al layer is the same as that of the ohmic metal layer21aof the source electrode21. The upper layer25bis a conductive metal layer having small electric resistance. The upper layer25bis formed by, for example, Au plating, and a thickness thereof is the same as that of the wiring layer21bof the source electrode21. Further, a constituent material of the drain pad26is the same as that of the upper layer25b. A constituent material of the gate pad27is the same as that of the gate electrode23.

A via hole4is formed in the substrate3and the nitride semiconductor layer10. The via hole4penetrates from the back surface3bof the substrate3to the surface10cof the nitride semiconductor layer10. The via hole4is formed immediately below the source pad25, and as seen from the thickness direction of the substrate3and the nitride semiconductor layer10, the via hole4and the source pad25are overlapped with each other. A lower surface of the lower layer25aof the source pad25is exposed from the substrate3via the via hole4. As shown inFIG. 1, a planar shape of the via hole4is, for example, rectangular, circular, elliptical, or oblong.

A conductive film24ais formed in the via hole4. The conductive film24ais provided on an inner surface of the via hole4and a lower surface of the lower layer25a, and is in contact with the lower layer25a. The conductive film24ais made of the same material as that of the back electrode24, and is connected to the back electrode24in the via hole4on the back surface3bside. The conductive film24aelectrically connects the back electrode24and the source pad25to each other.

A method of manufacturing the transistor1A according to the present embodiment having the above configuration will be described.FIGS. 4A to 5Care cross-sectional views showing a process of manufacturing the transistor1A and show cross sections corresponding toFIG. 3.

First, as shown inFIG. 4A, the buffer layer11, the channel layer12, and the electron supply layer13are grown on a main surface of the substrate3to form the nitride semiconductor layer10. The growth is performed, for example, by metal organic chemical vapor deposition (MOCVD). Thereby, an epitaxial substrate2as a substrate product including the substrate3and the nitride semiconductor layer10is formed. Next, a resist mask is formed on the region of the nitride semiconductor layer10serving as the active region10a(seeFIG. 1), and ions (e.g., Ar ions) are implanted into the region of the nitride semiconductor layer10exposed from the resist mask to form the inactive region10b(seeFIG. 1) around the active region10a. Thereafter, the whole of the epitaxial substrate2is covered with the insulating film31.

Subsequently, openings31aare formed in the insulating film31corresponding to the source electrode21, the drain electrode22, and the source pad25, and the openings31aare buried with the ohmic metal layers21aand22a(seeFIG. 2) and the lower layer25aof the source pad25. In this case, the lower layer25acompletely covers a via hole forming predetermined region2a. In one example, a process of forming the lower layer25aincludes a process of forming a first layer25a1made of Ti or Ta on the surface of the epitaxial substrate2, a process of forming a second layer25a2made of Al on the first layer25a1, a process of forming a third layer25a3made of Ti or Ta on the second layer25a2, and a process of alloying the first layer25a1, the second layer25a2, and the third layer25a3by heat treatment. The ohmic metal layers21aand22aare also formed in the same manner. The ohmic metal layers21aand22aand the lower layer25aare formed by depositing a corresponding metal on the respective regions by, for example, vacuum deposition.

Thereafter, a gate opening is formed in the insulating film31, and the gate opening is closed by the gate electrode23. Through the above processes, the source electrode21, the drain electrode22, the lower layer25a, and the gate electrode23are formed on the epitaxial substrate2, and the epitaxial substrate2of which surface other than the electrode, the pad, and the metal is covered with the insulating film31is obtained. An edge of each of the electrodes21and22, the lower layer25a, and the gate electrode23may be mounted on the insulating film31. The wiring layers21band22band the upper layer25bare formed on the ohmic metal layers21aand22aand the lower layer25a, respectively. At the same time, the drain pad26and the gate pad27are formed. Next, an insulating film32covering the source electrode21, the drain electrode22and the insulating film31is formed. The formation of the wiring layers21band22b, the upper layer25b, the drain pad26, and the gate pad27are performed by, for example, a plating method. The insulating films31and32are formed by, for example, chemical vapor deposition (CVD).

Next, as shown inFIG. 4B, the surface of the epitaxial substrate2on the nitride semiconductor layer10side (that is, the insulating film32) and a supporting substrate42(e.g., a glass substrate) are adhered to each other through a wax41. In addition, an etching mask43having an opening43ain the via hole forming predetermined region2ais formed on the back surface of the epitaxial substrate2(that is, the back surface3bof the substrate3). The etching mask43is made of, for example, a material including at least one of Ni and Cu, and is made of Ni in one embodiment. Specifically, first, nickel (Ni) is deposited on the back surface3band a resist is coated thereon. A resist pattern having an opening is formed in a portion on the via hole forming predetermined region2a. A Ni film is etched through the opening. Thus, the etching mask43made of Ni and having the opening43ais formed. Thereafter, the resist is removed.

Subsequently, as shown inFIG. 4C, the substrate3in the via hole forming predetermined region2ais selectively etched from the back surface3bside through the opening43aof the etching mask43. The etching is reactive ion etching (RIE), which is a type of plasma etching, and uses reaction gas containing fluorine. In one example, the reaction gas is a mixed gas of SF6and O2. When the substrate3is a SiC substrate, a chemical etching reaction (formation of silicon fluoride, SiFx, and carbon dioxide (CO2)) occurs due to fluorine and oxygen plasma. The RF power is, for example, 400 W. The etching is terminated in a step in which the substrate3remains slightly (i.e., just before the substrate3is completely removed). Further, the etching may be terminated in a step in which the substrate3is completely removed and the nitride semiconductor layer10is exposed.

Subsequently, as shown inFIG. 5A, the nitride semiconductor layer10is etched to expose the lower layer25a. In such a process, the nitride semiconductor layer10is etched by RIE using the reaction gas containing fluorine (e.g., mixed gas of SF6and O2), until the termination of the etching, continuing from the previous process, However, the RF power is set lower than the previous process. In one example, the RF power of the present process is 100 W. The RF power is changed by temporarily stopping the etching. In addition, the pressure or the like may be adjusted, if necessary. In the etching in the step, a sputter effect due to ions contained in the reaction gas (e.g., S ions) becomes dominant. Thus, the via hole4is formed to reach the surface from the back surface of the epitaxial substrate2, and the lower layer25ais exposed through the via hole4. Further, in order to improve throughput, the nitride semiconductor layer10may be formed to have a thickness of 2 μm or less, for example.

Here, as shown in FIG.5B1, as a result of the etching, a film25ccontaining aluminum fluoride AlFxand aluminum oxide AlOxis formed on the exposed surface of the lower layer25a(in particular, on the surface of the second layer25a2). Since the film25chas high resistance to sputter, the progress of etching is substantially stopped. Table 1 below shows XPS analysis results of the exposed surface of the lower layer25a. As shown in Table 1, there are many oxygen atoms and fluorine atoms in addition to aluminum atoms on the exposed surface, and AlFxand AlOxare formed on the exposed surface.

The lower layer25afunctions as an etch stopper for the nitride semiconductor layer10.FIG. 6is a graph showing a relationship between the etch selectivity ratio between GaN and Al, which are nitride semiconductors, and RF power when a mixed gas of SF6and O2is used as a reaction gas. A horizontal axis represents a RF power (unit: W), and a vertical axis represents an etch selectivity ratio (GaN/Al). Further, a SF6gas flow rate was 75 sccm, a O2gas flow rate was 25 sccm, and the furnace pressure was 1 Pa.

As the RF power is reduced, the etch rate decreases with GaN and Al, but since a decrease rate of GaN exceeds the decrease rate of Al, the etch selectivity ratio between GaN and Al gradually increases. In addition, in a region with low RF power (e.g., below 150 W), the etch selectivity ratio between GaN and Al increases significantly. This is because when the RF power is small, AlFxand AlOxgenerated on the exposed surface of the lower layer25abecome hard to be removed. In particular, when the RF power is 100 W, the etch selectivity ratio between GaN and Al exceeds 10. In the experiment, the etching (sputtering) rate of GaN was about 20 nm/min, and the etching (sputtering) rate of Al was about 2 nm/min. Therefore, the lower layer25acontaining Al can function well as an etching stopper for the nitride semiconductor layer10.

FIG. 7is a graph showing a relationship between the etch selectivity ratio between SiC and Al and RF power when mixed gas of SF6and O2is used as a reaction gas. A horizontal axis represents a RF power (unit: W), and a vertical axis represents an etch selectivity ratio (SiC/Al). The flow rates of SF6gas and O2gas and the furnace pressure are the same as inFIG. 6. As shown inFIG. 7, also in the case of SiC and Al, as the RF power is reduced, the etching rate decreases, but the etch selectivity ratio between SiC and Al gradually increases. In addition, when the RF power is 200 W, the etch selectivity ratio is close to 20, and when the RF power is 150 W, the etch selectivity ratio reaches 40. This means that the etching (sputtering) rate of SiC is much faster than the etching (sputtering) rate of GaN and Al. Therefore, even if the etching conditions for the substrate3are continuously maintained with respect to the nitride semiconductor layer10and the lower layer25a, over etching of the lower layer25ais less likely to occur.

The film25c(AlFx, AlOx) is insulative. In order to lower electric resistance between the conductive film24aand the lower layer25ato be described later, the film25cis removed after the via hole4is formed. For example, the film25ccan be removed by exposing the lower layer25aexposed in the via hole4to plasma containing inert gas such as argon gas. After such a process, the etching mask43is removed.

Subsequently, as shown inFIG. 5C, the back electrode24is formed on the back surface3bof the substrate3. At the same time, a conductive film24ain contact with the lower layer25ais formed in the via hole4(on the inner surface of the via hole4and the exposed surface of the lower layer25a). In such a process, the back electrode24and the conductive film24aare formed by Au plating, for example. Through the above processes, the transistor1A according to the present embodiment is manufactured.

The effects obtained by the present embodiment described above will be described together with conventional problems.FIG. 11Ashows a state in which a nitride semiconductor layer102is formed on a SiC substrate101. The nitride semiconductor layer102has, for example, a GaN layer and an AlGaN layer in this order from the SiC substrate101side. In addition, a Ni film103as an etch stopper is provided on an upper surface of the nitride semiconductor layer102. Further, on a back surface of the SiC substrate101, an etching mask104having an opening104ain a via hole forming predetermined region is provided.

FIG. 11Bshows a state in which RIE is applied to the structure shown inFIG. 11Afrom the back surface side of the SiC substrate101. A via hole105is formed by the RIE. After the via hole105is formed, the etching mask104is removed. As reaction gas for the RIE, fluorine-based gas such as SF6is used for the SiC substrate101, and chlorine-based gas such as SiCl4is used for the nitride semiconductor layer102. Thereafter, as shown inFIG. 11C, a back electrode106is formed on the back surface of the substrate101and inside the via hole105(on an inner surface of the via hole105and on the Ni film103). The back electrode106electrically conducts between the back surface side of the SiC substrate101and the Ni film103through the via hole105.

Generally, the chlorine-based gas such as SiCl4is used for the RIE of the nitride semiconductor layer. For example, when etching GaN using SiCl4gas, GaN is decomposed into gallium chloride (GaCl2) and nitrogen (N2) by a chemical etching process. In addition, in such etching, Ni having high resistance to the chlorine-based gas is used as a material of an etching stopper. Further, Ni is changed to nickel chloride (NiCl2) by irradiation with chlorine plasma, but a boiling point of NiCl2is 1000° C. or more and has sufficient resistance to the irradiation with chlorine plasmas. However, Ni has a disadvantage of high electrical resistance. As shown inFIG. 11C, when the Ni film103is in contact with the back electrode106and functions as a conductive film, the electrical resistance of the Ni film103may prevent the transistor from improving its electrical characteristics.

Therefore, in the present embodiment, a metal film (lower layer25a) containing Al rather than the Ni film is used as the etching stopper. The lower layer25ahas good conductivity by mainly containing Al. Therefore, the electrical resistance between the conductive film24aand the upper layer25bcan be suppressed to be low and the electrical characteristics of the transistor1A can be improved. In addition, it is possible to preferably make the metal film containing Al to function as the etching stopper for the nitride semiconductor layer10by using a gas containing fluorine as the reaction gas for the RIE. Thus, according to the present embodiment, the electrical resistance of the metal film as the etching stopper can be reduced.

In the present embodiment, when the substrate3is the SiC substrate, at least a portion of the substrate3in the via hole forming predetermined region2amay be etched using the reaction gas containing fluorine in the process of forming the via hole4. SiC is efficiently etched by a chemical etching process using the reaction gas containing fluorine. Therefore, the throughput may be further improved.

In the present embodiment, the etching mask may include at least one of Ni and Cu. Since Ni and Cu have high etching resistance to fluorine-based gas, it is possible to sufficiently protect the substrate3except for the via hole forming predetermined region2a.

In the present embodiment, the reaction gas containing fluorine may be a mixed gas of SF6and O2. As described above, in the RIE of the nitride semiconductor layer10using the reaction gas containing fluorine, the nitride semiconductor layer10is mainly removed by the effect of sputter etching. SF6containing S (sulfur) atoms having relatively large mass is contained in the reaction gas, so that the sputter etching can be performed more effectively.

As in the present embodiment, after the process of forming the via hole4, a process of exposing the lower layer25aexposed in the via hole4to the plasma containing inert gas and a process of forming the conductive film24ain contact with the lower layer25ain the via hole4may be further performed. Thus, the insulating film25ccan be removed, and the lower layer25aand the conductive film24acan be conducted with low resistance.

In the present embodiment, the process of forming the lower layer25amay include a process of forming a first layer25a1made of Ti or Ta on the surface of the epitaxial substrate2, a process of forming a second layer25a2made of Al on the first layer25a1, and a process of alloying the first layer25a1and the second layer25a2. As a result, since the lower layer25aas the etching stopper can be formed in the same process as the ohmic metal layers21aand22a, only a process for forming the etching stopper is unnecessary and the number of processes can be reduced.

First Modified Example

FIGS. 8A to 8Care cross-sectional views showing a manufacturing process according to a first modified example of the embodiment. In the present modified example, as shown inFIG. 8A, the substrate3in the via hole forming predetermined region2ais selectively etched from the back surface3bside through the opening43aof the etching mask43. In addition, the etching is terminated in a step in which the substrate3remains slightly (i.e., just before the substrate3is completely removed). The process is the same as the process shown inFIG. 4Cof the embodiment.

Next, as shown inFIG. 8B, the nitride semiconductor layer10in the via hole forming predetermined region2ais etched through the opening43aof the etching mask43. In such a process, the reaction gas is changed from the reaction gas containing fluorine in the previous process (e.g., mixed gas of SF6and O2) to a reaction gas containing chlorine (e.g., example, Cl2gas), and the nitride semiconductor layer10is etched by RIE. The RF power is, for example, 50 W. In addition, the etching is terminated in a step in which the nitride semiconductor layer10remains slightly (i.e., just before the nitride semiconductor layer10is completely removed). At this time, the termination of the etching can be determined by plasma emission derived from Al. That is, a remaining part of the substrate3is first etched by the etching gas containing chlorine, and the light emitted by Al contained in the AlN buffer layer11is then detected. If the etching continues, the Al emission disappears when the etching of the AlN buffer layer11is terminated. At this time, the etching has already reached the GaN channel layer12, and if the etching continues, the emission of Al is detected again when the etching of the GaN channel layer12is terminated, that is, when the AlGaN barrier layer13is exposed. When the second emission of Al is detected, the etching is stopped.

Subsequently, the reaction gas is changed again from the reaction gas containing chlorine (e.g., Cl2gas) to the reaction gas containing fluorine (e.g., mixed gas of SF6and O2), and the remaining part of the nitride semiconductor layer10is etched. The reaction gas containing fluorine is used during the period including the termination of the etching, particularly, to etch the AlGaN barrier layer13. The RF power is, for example, 100 W. Through such a process, as shown inFIG. 8C, the via hole4is formed to reach the surface from the back surface of the epitaxial substrate2, and the lower layer25ais exposed through the via hole4. Thereafter, the transistor1A is manufactured through the processes shown inFIGS. 5B and 5Cof the embodiment.

In the present modified example, a portion of the nitride semiconductor layer10in the via hole forming predetermined region2amay be etched using the reaction gas containing chlorine, and thereafter, the remaining portion of the nitride semiconductor layer10in the via hole forming predetermined region2amay be etched using the reaction gas containing fluorine. In this case, the nitride semiconductor layer10can be efficiently etched by a chemical etching process. Therefore, the throughput may be further improved. In addition, the function of the lower layer25aas the etching stopper can be exerted satisfactorily by changing the reaction gas to the gas containing fluorine during the period including the termination of the etching. When the nitride semiconductor layer10has a thickness of, for example, 1 μm or more, the method of the present modified example is particularly effective.

Second Modified Example

FIG. 9is a plan view showing a transistor1B as a semiconductor device according to a second modified example of the embodiment.FIG. 10is a cross-sectional view taken along the line X-X of the transistor1B shown inFIG. 9. Further, for the sake of explanation, the insulating films31and32are omitted inFIG. 9.

A difference between the present modified example and the embodiment is the formation position of the via hole. In the embodiment, the via hole4is formed in the inactive region10bimmediately below the source pad25, whereas in the present modified example, the via hole4is formed in the active region10aimmediately below the source electrode21. In addition, the conductive film24aprovided inside the via hole4is not in contact with the source pad25but is in contact with the ohmic metal layer21aof the source electrode21. Such a structure is referred to as an island source via-hall (ISV) structure. In such a structure, the source pad25shown inFIG. 1is not necessary. Further, other configurations except for the formation position of the via hole and the presence or absence of the source pad25are the same as in the embodiment.

When a transistor1B of the present modified example is manufactured, the ohmic metal layer21acan be used as the etching stopper. Since the structure of the ohmic metal layer21ais the same as that of the lower layer25aof the embodiment, the ohmic metal layer21acan function as the etching stopper when the via hole4is formed by RIE. Further, the method of forming the via hole4is the same as that of the embodiment.

According to the present modified example, since the ohmic metal layer21acontaining Al is used as the etching stopper, it is not necessary to separately form the etching stopper, and the process can be shortened. In a case where a layer functioning as the etching stopper is formed separately from the ohmic metal layer21a, the etching stopper needs to be formed outside the ohmic metal layer21a. In the present modified example, however, it is not necessary to form the etching stopper outside the ohmic metal layer21a, which contributes to the reduction of the via hole4. An edge region in contact with the gate electrode functions exclusively as the ohmic metal layer21a. Therefore, the via hole4can be formed in the source electrode of the transistor in accordance with the arrangement of the electrode of the conventional transistor.

The method of manufacturing a semiconductor device according to the present disclosure is not limited to the embodiments described above, and various other variations are possible. For example, the embodiments and modified example described above may be combined with each other in accordance with the necessary purposes and effects. In addition, in the embodiments described, SF6is illustrated as the reaction gas containing fluorine, but the reaction gas containing fluorine is not limited to thereto, and for example, CF4, NF3and the like can be used.