Method and apparatus for demodulating a wireless signal

A demodulator for a Bluetooth receiver includes an oversampling module configured to oversample input symbols a first plurality of times to generate a first plurality of oversampled input symbols. A correlating module is configured to correlate a second plurality of adjacent samples of the first plurality of oversampled input symbols with corresponding symbols in a predetermined enhanced data rate (EDR) sync word. Based on the correlation, the correlating module is configured to selectively generate a sync signal indicating that EDR sync has occurred. The second plurality of adjacent samples comprises more samples than one and less than all of the first plurality of oversampled input symbols.

FIELD

The present disclosure relates to wireless receivers, and more particularly to demodulation in Bluetooth wireless receivers.

BACKGROUND

Bluetooth devices provide connectivity for voice and data between wireless devices.FIG. 1Aillustrates an example of a receiver14used in a Bluetooth device. The receiver14includes an antenna20that is connected to a front end module24. The antenna20and the front end module24receive analog radio frequency (RF) signals. The analog RF signals output by the front end module24are input to a low noise amplifier28, which amplifies the analog RF signals. A mixer32receives the analog RF signals output by the low noise amplifier28and an output of an oscillator36. The mixer32converts the analog RF signals to baseband signals.

Further signal conditioning may be performed on the baseband signals. A filter40receives an output of the mixer32. A first variable gain amplifier (VGA)44receives an output of the filter40. A filter46receives an output of the VGA44. A second VGA48receives an output of the filter46. An analog to digital converter (ADC)52converts the filtered analog signal to a digital signal. A demodulation module54receives the digital signal from the ADC52and demodulates the digital signal to recover data bits. The demodulation module54may include a square-root-raised-cosine (SRRC) filter (not shown) that is matched to an SRRC filter in a Bluetooth transmitter (not shown).

When operating in a basic data rate (BDR) mode, a symbol rate of the digital signal output by the ADC52is 1 MHz with each symbol including one bit. When operating in enhanced data rate (EDR) modes, the symbol rate is 1 MHz, however each symbol represents two or three bits to provide 2 MHz or 3 MHz data rates, respectively.

FIG. 1Billustrates a BDR packet format, andFIG. 1Cillustrates an EDR packet format. InFIG. 1B, the BDR packet begins with an access code and header. The access code is used for synchronization, DC-offset compensation, and identification of packets in a physical channel. Access codes are also used in paging, inquiry, and park operations in a Bluetooth system. The header includes link control information that includes packet type and link type. The link type determines the format of the payload that follows the access code and header. The payload may include user information and control information.

The user information may include data or voice or a combination of the two. The payload may also include control data used for device identity and provide real-time clock information. The payload may also include additional data for error discovery and recovery such as the cyclic redundancy check (CRC) and forward error correction (FEC) information.

The BDR packet inFIG. 1Bis transmitted with Gaussian frequency shift keying (GFSK) modulation. The EDR packet inFIG. 1Cchanges from GFSK modulation to differential phase shift keying (DPSK) after the packet header. As a result, additional timing and control information is required for synchronizing to the new modulation format. The EDR packet uses the same access code and header definitions as the BDR packet, including the modulation format.

Following the header, the EDR packet includes a guard period that allows a receiver time to prepare for the change in modulation to DPSK. The guard time is followed by a synchronization sequence that includes a reference symbol and multiple DPSK symbols. This sequence is required for synchronizing the symbol timing and phase for one of the two modulation types used in the EDR packet. The payload in the EDR packet may include user information and control information based on the type of packet transmitted.

The EDR mode for the 2 Mb/s data rate uses differential-encoded quadrature phase shift keying (DQPSK). The DQPSK signal can be demodulated without estimating the carrier phase. Instead, the phase of a first symbol is compared to the phase of a second symbol. The amount of phase shift is used to estimate the received data.

The EDR mode for the 3 Mb/s data rate uses 8-ary differential encoded phase shift keying (8-DPSK). The further increase in the data rate is achieved through the addition of four more constellation points for each symbol. The total of eight constellation points allows a transmission rate of three bits per symbol. This type of modulation has many of the same benefits as DQPSK including non-coherent demodulation.

Referring back toFIG. 1A, the demodulation module54typically uses a Square Root Raised Cosine (SRRCC) filter (not shown) for pulse shaping at the transmitter. The SRRC filter (not shown) in the demodulation module54is matched to the SRRC filter used in the transmitter. The SRRC filter cancels intersymbol interference (ISI) at an optimum 1 MHz sampling phase. The demodulation module54typically identifies a sync word and performs differential detection. However, the performance or sensitivity of the differential detection approach used by the receiver is limited by incorrect sampling phase selection at power levels around sensitivity. Decision errors after a post slicer may also occur due to in-band noise.

FIG. 2illustrates an EDR sync word detection module100. An oversampling module101oversamples each symbol of an input signal T times and stores the oversampled signal in a FIFO buffer102. For example T=8 inFIG. 2. A register104stores a predetermined EDR sync word. The EDR sync word detection module100includes a plurality of difference modules108and a plurality of multiplier modules112. A first symbol of the predetermined EDR sync word is multiplied by a constant k in one of the multiplier modules112-1. For example only, k=0.75, although other values may be used. An output of the multiplier module112-1is input to one of the difference modules108-1. One of the samples (e.g., D0) of one of the symbols of the input signal is also input to the difference module108-1. An output of the difference module108-1is input to a summing module118.

Likewise, second and third symbols of the predetermined EDR sync word are multiplied by a constant k in the multiplier modules112-2and112-3, respectively. Outputs of the multiplier module112-2and112-3are input to other ones of the difference modules108-2and108-3, respectively. Other samples (e.g., D8 and D16) of other symbols of the input signal are also input to the difference modules108-2and108-3, respectively. Outputs of the difference modules108-2and108-3are also input to the summing module118. Additional symbols of the input signal are compared to other symbols of the predetermined EDR sync word.

The summing module118sums the differences generated by the difference modules108and outputs the sum to a comparing module120. The comparing module120compares the sum to an EDR sync threshold and selectively generates an EDR sync found signal based on the comparison. For example, the comparing module120may generate the EDR sync found signal when the sum of the differences is less than the EDR sync threshold.

FIG. 3illustrates a conventional differential detection module. Oversampled data symbols are received in FIFO buffer150. A first symbol such as D0 is input to a first input of the multiplier152. A second symbol such as D8 is input to a conjugate module154, which provides a conjugate of the second symbol to a second input of the multiplier152. An output of the multiplier152is output to a delay module158, a coordinate rotation digital computer (cordic) module162, a delay module166and a delay module170. A frequency offset compensation module174receives an output of the delay module170. An output of the frequency offset compensation module174is input to a slicer module178, which outputs the data bits.

SUMMARY

A demodulator for a Bluetooth receiver includes an oversampling module configured to oversample input symbols a first plurality of times to generate a first plurality of oversampled input symbols. A correlating module is configured to correlate a second plurality of adjacent samples of the first plurality of oversampled input symbols with corresponding symbols in a predetermined enhanced data rate (EDR) sync word. Based on the correlation, the correlating module is configured to selectively generate a sync signal indicating that EDR sync has occurred. The second plurality of adjacent samples comprises more samples than one and less than all of the first plurality of oversampled input symbols.

A demodulator for a Bluetooth receiver includes a differential detection module configured to perform differential detection on a first symbol and a second symbol. The second symbol occurs prior to the first symbol. The differential detection module generates a phase estimate for the first symbol. A symbol replacement module is configured to generate a third symbol based on the phase estimate and the second symbol and to replace the first symbol based on (i) the third symbol and (ii) the first symbol.

A method of performing demodulation in a Bluetooth receiver includes performing differential detection on a first symbol and a second symbol, wherein the second symbol occurs prior to the first symbol; generating a phase estimate for the first symbol; generating a third symbol based on the phase estimate and the second symbol; and replacing the first symbol based on (i) the third symbol and (ii) the first symbol.

A method for performing demodulation for a Bluetooth receiver includes oversampling input symbols a first plurality of times to generate a first plurality of oversampled input symbols; and correlating a second plurality of adjacent samples of the first plurality of oversampled input symbols with corresponding symbols in a predetermined enhanced data rate (EDR) sync word; and based on the correlation, selectively generating a sync signal indicating that EDR sync has occurred. The second plurality of adjacent samples comprises more samples than one and less than all of the first plurality of oversampled input symbols.

DESCRIPTION

In the foregoing description,FIGS. 4A-5relate to an EDR sync word detection module of the demodulation module according to an implementation of the present disclosure.FIGS. 6-7relate to differential detection module of the demodulation module according to an implementation of the present disclosure.

EDR Sync Word Detection Module

The EDR sync word detection module shown inFIG. 2determines a phase having a minimum distance from the known EDR sync word. The selected phase identified by the EDR sync word detection module is then used during differential detection and/or other processing. High noise on an element of this input vector may cause an erroneous minimum distance calculation with respect to a correct sampling phase.

As described above, the EDR sync word detection module shown inFIG. 2uses one sample for each oversampled symbol when correlating the input signal to the EDR sync word. As will be described further below, an EDR sync word detection module according to an implementation of the present disclosure uses N adjacent samples for each oversampled symbol when correlating the input signal to the EDR sync word, where N is greater than one and less than four. Averaging using N samples from consecutive sampling phases improves the minimum distance detection. Note that averaging on more than N consecutive sampling phases tends to degrade performance since other phases have large effects of ISI (only the optimal phase and phases close to the optimal phase are relatively ISI free).

FIG. 4Aillustrates an example of a demodulation module190which, in one implementation, includes an EDR sync word detection module200and a differential detection module201.

FIG. 4Billustrates an example of the EDR sync word detection module200according to an implementation of the present disclosure. An oversampling module202receives symbols at a symbol rate and oversamples the symbols at an oversampling rate. In some examples, the oversampling rate is T times where T is an integer. In some examples, T=8, the symbol rate is 1 MHz and the oversampling rate is 8 MHz. Therefore there are T samples of each of the symbols in the oversampled input signal. The oversampled input signal is output to a buffer204such as a FIFO buffer.

A correlation module206selects N adjacent samples of the T samples for each of the symbols, where N is greater than one and less than four. In some examples, N=3. The correlation module206generates differences between the N samples of the symbols and corresponding bits in a predetermined EDR sync word. The correlation module206sums the differences and generates average differences for the symbols. The correlation module206generates a sum of the average differences for the symbols, and compares the sum of the average differences to a predetermined threshold (e.g., an EDR sync threshold). If the sum is less than the EDR sync threshold, the correlation module206generates a signal (e.g., an EDR sync found signal) indicating that an EDR sync has been found. Otherwise, the symbols of the input signal are shifted by one symbol in the buffer204and the process is repeated for the next symbol until an EDR sync is found. A delay module208may be used to provide a1sample delay before declaring the EDR sync has been found.

FIG. 4Cillustrates a more detailed example of the EDR sync word detection module200. The oversampling module202oversamples each symbol of an input signal T times. A register207stores a predetermined EDR sync word. The EDR sync word detection module200includes a plurality of multiplier modules212and a plurality of difference modules216-1,216-2, . . . (collectively difference modules216) each including N difference modules216-11,216-12, . . . , and216-1N, where N is an integer greater than 1. In some examples, N=3.

A first symbol of the predetermined EDR sync word is multiplied by a constant k in one of the multiplier modules212-1. For example k=0.75, although other values may be used. An output of the multiplier module212-1is input to each of the N difference modules216-11,216-12, . . . , and216-1N in the difference module216-1. N of the samples (e.g., D0, D1, and D2) of one of the symbols of the input signal are also input to the difference module216-1. An output of the difference module216-1is input to a summing module224-1. A dividing module228-1divides the output of the summing module224-1by D, where D is a number such as an integer. In some examples, D=4.

A second bit of the predetermined EDR sync word is multiplied by a constant k in one of the multiplier modules212-2. An output of the multiplier module212-2is input to each of the N difference modules216-21,216-22, . . . , and216-2N in the difference module216-2. N of the samples (e.g., D8, D9, and D10) of one of the symbols of the input signal are also input to the difference module216-2. An output of the difference module216-2is input to a summing module224-2. A dividing module228-2divides the output of the summing module224-2by D, where D is a number such as an integer.

Other bits of the predetermined EDR sync word are handled in a similar manner.

Outputs of the dividing modules228-1,228-2, . . . are input to a summing module232. The summing module232sums the averaged differences and outputs the sum to a comparing module236. The comparing module236compares the sum to an EDR sync threshold and selectively generates an EDR sync found signal based on the comparison. For example, the comparing module236may generate the EDR sync found signal when the sum of the differences is less than the EDR sync threshold.

The EDR sync word detection module ofFIG. 2finds the phase having the minimum distance from the known EDR sync word. High noise on an element of this input vector may cause erroneous minimum distance (with respect to a correct sampling phase). Averaging on N points using consecutive sampling phases as shown inFIG. 4Bimproves the minimum distance detection. Note that averaging on more than N consecutive sampling phases may result in degradation in performance since other phases have large effects of151(only an optimal phase and phases close to it are relatively ISI free).

Referring now toFIG. 5, a method of finding a minimum distance to the predetermined EDR sync word is shown. At300, symbols of the EDR sync signal are oversampled T times. At304, a plurality of adjacent samples of each of the symbols are subtracted from corresponding bits of a predetermined EDR sync word. At308, an average of the differences is generated. At312, the averages are summed. At316, control determines whether or not the sum is less than an EDR sync threshold. If not, control continues with the next symbol at317. Otherwise, control delays1sample at318and declares the EDR sync was found at320.

Differential Detection Module

At the transmitter, the transmitted signal

S⁡(n)=ⅇj⁡(∑i⁢θ⁡(n))+j⁢⁢θ0
passes through a square root raised cosine (SRRC) filter. Successive symbols are equal to a sum of the initial phase θ0and the rotation from a subsequent phase. Therefore, for the first three symbol periods, s[0]=θ0, s[1]=θ0+θ[1], and s[2]=s[1]+θ[2]. θ[1] is the information carrying part in s[1] that includes bits b1and b2for DQPSK and bits b1, b2and b3for D8PSK. θ[2] is the information carrying part in s[2] that includes bits b3and b4for DQPSK and bits b4, b5and b6for D8PSK.

At the receiver, the received signal is

r⁡[n]=ⅇj⁡(θ0+∑n⁢θn).
When performing differential detection, the current signal is multiplied by the past symbols or r[n]r*[n−8]≈ejθ[n]. For example only, the variable n does not correspond to integration at the signal rate such as 1 MHz. Rather, the variable n may correspond to integration at a higher rate such as the sampling rate (which may be 8 MHz). In one implementation, r[n]=s[n]+z0[n], where z0[n] is the noise in the first symbol, and r[n−8]=s[n−8]+z1[n], where z1[n] represents noise in the past symbols. It would be desirable to significantly reduce or cancel z1[n].

At the transmitter, the signal sent by the transmitter in four succeeding periods is θ0, θ0+s1, θ+s1+s2, and θ0+s1+s2+s3, where s1, s2, and s3respectively correspond to the first symbol, the second symbol, and the third symbol. At the receiver, the signal received by the receiver is θ0+n0, θ0+s1+n1, θ0+s1+s2+n2, and θ0+s1+s2+s3+n3, where n1, n2, and n3respectively correspond to the first noise value, the second noise value, and the third noise value. Using differential detection (subtracting the current sample from the prior sample) starting after the second period, we have s1+n1−n0, s2+n2−n1, and s3+n3−n2.

A slicer module is used on the received symbol s1+n1−n0to generate an estimated symbol ŝ1. Based on the estimated phase output by the slicer module and the second symbol, a clean reconstruction of the phase of the second transmitted symbol θ0+ŝ1is generated. If the clean reconstruction of the phase of the second transmitted symbol value θ0+ŝ1, is used instead of θ+s1+n1in the next differential detection calculation, the noise term n1is eliminated—which results in s2+n2rather than s2+n2−n1.

The slicer module is used on the received symbol s2+n2to generate an estimated symbol ŝ2. Based on the output of the slicer module, a clean reconstruction of the phase of the second transmitted symbol θ0+ŝ2is generated. If the clean reconstruction of the phase of the second transmitted symbol value θ0+ŝ2is used in the next differential detection calculation, the noise term n2is eliminated—which results in s3+n3rather than s3+n3−n2. Assuming that the symbol estimate output by the slicer module is correct, there will be approximately 3 dB improvement in sensitivity. However, when an incorrect symbol estimate is output by the slicer, error propagation occurs which lowers the estimated improvement to around 2 dB.

The symbol at the output of the differential detecting module at time t is:
y(t)=x(t)+n(t),
where x(t) is the actual transmitted phase and n(t) is noise.

At time t+1, x(t) is rotated by phase p(t), so:
x(t+1)=x(t)ei*p(t).

Therefore, the symbol at the output of the differential detecting module is:
y(t+1)=x(t)ei*p(t)+n(t+1).

According to the present disclosure, noise averaging is performed for y(t) and y(t+1) assuming that the estimate on phase p(t) is correct. Therefore:
Yave=y(t+1)+y(t)ei*p(t)
Yave=x(t+1)+½(n(t)+n(t+1)ei*p(t)).
The noise term ½(n(t)+n(t+1)ei*p(t)has variance reduced by half since n is assumed to be independent.

The noise averaging is continued progressively as the phase estimates are generated on the complete EDR portion of the packet. A forgetting factor is used to reduce error propagation in case of incorrect phase estimate. In one implementation,
Yave=y(t+1)+nave—ff*y(t)ei*p(t).

FIG. 6illustrates a differential detection module201according to one embodiment of the present disclosure. Data symbols are oversampled and stored in buffer490. The differential detection module201includes a differential calculating module495configured to perform differential detection on the symbols and to generate data bits. In addition, the differential calculating module495generates a phase estimate. A reconstruction module500generates a replacement symbol based on the phase estimate and the second symbol. The reconstruction module500adjusts the first symbol and the replacement symbol by weighting factors. The reconstruction module500generates a sum of the adjusted first symbol and the adjusted replacement symbol and replaces the first symbol with the sum. As described above, the reconstruction module500reduces noise by reducing or eliminating noise components.

More particularly, the differential calculating module495inputs a first sample D0 of a first symbol to a multiplier502. A first sample D8 of a second symbol is output to a conjugate module504, which provides a conjugate of the second symbol to a second input of the multiplier502. While samples for D0 and D8 are used in this example with 8 times oversampling, other sampling rates can be used. More generally, samples D0 and DN are used for sampling at N times the signal rate. An output of the multiplier502is output to a delay module508that provides delay, a coordinate rotation digital computer (cordic) module512that performs a cordic function, and delay modules516and520that also provide delays. A frequency offset compensation module524receives an output of the delay module520and performs frequency offset compensation. An output of the frequency offset compensation module174is input to a slicer module528, which slices the output of the delay module520and outputs the data bits.

In addition to outputting the data bits, the slicer module528also performs phase slicing and outputs a phase estimate p(t). The phase estimate is output to a rotating module534, which rotates the phase estimate by ei*p(t). The rotating module534uses the phase estimate generated by the slicer module528to rotate the second symbol (formerly sample D8—now at sample D11 due to delays) by the phase estimate to generate a replacement symbol. The effect is to reduce one of the noise components, as described above.

The replacement symbol and the first symbol at time t+1 may be averaged or factored to provide noise averaging. Note that the buffer sample D3 is updated due to a delay in the data path from the buffer490to the slicer module528. Therefore, the first symbol reaches D3 in the buffer490when the replacement symbol based on the phase estimate and the second symbol is ready.

Referring back toFIG. 6, the replacement symbol is generated by the second symbol at time t rotated by the phase estimate in the reconstruction module500. Therefore, the rotation caused by the phase estimate ei*p(t)is multiplied in multiplying module536by symbol D11, which corresponds to the second symbol at D8 after three sample delays. An output of the multiplying module536is input to one input of a multiplying module542. Another input of the multiplying module542receives a first factor, such as a forgetting factor M_edr_nave_ff. The sample D3 is divided by 2 by a dividing module560, which has an output connected to a one input of a summing module562. The other input of the summing module562receives an output of the multiplying module542. The output of the summing module562is used to update the first symbol D3.

FIG. 7illustrates an example of a method600for performing differential detection according to one implementation of the present disclosure. At604, differential detection is performed and the data bits and the phase estimate are generated. At606, a replacement symbol is generated based on the second symbol and the phase estimate. At610, the replacement symbol is multiplied by a first factor. In some examples, the first factor is a forgetting factor as described above. At616, the first symbol is divided by two (or multiplied by a second factor). At620, control sums the first symbol divided by 2 is added to the replacement symbol multiplied by the first factor. At624, the first symbol is replaced by the sum.

The apparatuses and methods described herein may be partially or fully implemented by one or more computer programs executed by one or more processors. The computer programs include processor-executable instructions that are stored on at least one non-transitory tangible computer readable medium. The computer programs may also include and/or rely on stored data. Non-limiting examples of the non-transitory tangible computer readable medium include nonvolatile memory, volatile memory, magnetic storage, and optical storage.