D.C-D.C. converter for converting an unstabilized D.C.-voltage to three stabilized D.C.-voltages

A DC-DC converter converts an incoming unstabilized D.C. voltage to three stabilized output D.C. voltages. The converter contains two chopper stages (1, 2) with associated transformers, rectifiers (3, 4, 17a, 17b) and smoothing filters (5, 6, 18). The two chopper stages give a first and a second pulse-formed output voltage (U.sub.a and U.sub.b) which are regulated by shifting the leading edge of the pulses in the first output voltage (U.sub.a), while the second output voltage (U.sub.b) is regulated by shifting the trailing edge of the pulses. Two output voltages (U.sub.1, U.sub.2) are obtained after recitfying and smoothing. The third output voltage is obtained by connecting in parallel the outputs of two full-wave rectifiers (17a, 17b) which are magnetically coupled to the outputs of the two chopper steps, and by connecting a smoothing filter (18) to the common output of both full wave rectifiers. Regulation of the third output voltage (U.sub.3) is obtained by varying the phase position (o) between the first and the second chopper output voltage (U.sub.a , U.sub.b).

FIELD OF INVENTION 
The present invention relates to a D.C. converter for converting an 
unstablized incoming D.C. voltage to three stablized output D.C.voltages 
with the use of two chopper circuits. Such a converter can be used as the 
power source for a current supply to electronic equipment, especially 
airborn equipment where there is a demand for low weight and volume. 
BACKGROUND 
In power supply units with a high power output which is to be distributed 
to several loads, it is known in the art to utilize a D.C.-A.C. converter 
and to provide the converter with a transformer having a plurality of 
secondary windings, rectifiers and series regulators being connected to 
the secondary windings, as in U.S. Pat. No. 4,024,451, for example. Series 
regulation of the output voltages results in relatively high losses, and 
thereby lower efficiency, as well as in the limiting of power capacity. To 
avoid this, three separate converters must be used for higher power level, 
which of course increases the weight of the power supply unit. 
SUMMARY OF INVENTION 
An object of the present invention is to provide a D.C. converter of the 
kind mentioned above, which has as few component parts as is possible with 
respect to the number of obtained output voltages. 
In accordance with the invention, there are employed two chopper stages 
with associated transformers, rectifiers and smoothing filters, to provide 
three independent D.C. voltage outputs with output power of the same order 
of magnitude. After rectifying and smoothing, the two chopper stages give 
a first and a second output voltage which is regulated by shifting the 
leading edge of the pulses in the first pulse-formed output voltage, while 
the second output voltage is regulated by shifting the trailing edge of 
the pulses in the second pulse-formed output voltage. A third output 
voltage is obtained by connecting the first and the second pulse-formed 
output voltages in parallel after rectifying and before smoothing. This 
output voltage can be kept constant and dependent on the other two output 
voltages, providing that both the first and the second output voltages 
work with overlapping in the respective controlled edge. Regulation of the 
third output voltage is obtained by varying the phase position between the 
first and the second chopper output voltage.

DETAILED DESCRIPTION 
The incoming unstabilized D.C. voltage is denoted as Udc in the block 
diagram according to FIG. 1. The converter of the invention contains two 
chopper stages 1 and 2, which receive the D.C. voltage Udc and 
conventionally convert this voltage to a square-wave pulse train with a 
given frequency f.sub.O. For this purpose the chopper circuit 1 is 
controlled by a clock circuit 15, which sends control pulses with the 
frequency f.sub.O to the chopper stage 1 via a pulse width modulator 11 
and a logic circuit 13. After rectification in a rectifier 3, a 
pulse-formed output voltage Uol (illustrated in FIG. 3) is obtained, and 
the output D.C. voltage U.sub.1 is obtained after smoothing in a lowpass 
filter 5. The voltage U.sub.1 is compared with a reference voltage Url in 
a comparison circuit 7, and the difference voltage is transmitted via an 
amplifier 9 to the control input of the pulse width modulator 11, for 
varying the pulse width of the control pulse sent to the chopper step 1, 
in response to the magnitude of the difference signal from the comparator 
7. In this arrangement the pulse width is varied with the aid of the logic 
circuit 13 by varying the leading flank of the control pulses, while the 
trailing flank position is fixed. The frequency f.sub.o is constant for 
the whole time, and is determined by the clock circuit 15. 
Control pulses are sent to the chopper stage 2 in a similar manner from the 
clock circuit 15 via a phase shifter 16, a pulse width modulator 12 and a 
logical circuit 14. After the pulse-formed output voltage from the chopper 
step 2 has been rectified in a rectifier 4, a pulsing D.C. voltage 
U.sub.02 is obtained, which is smoothed in a lowpass filter 6 to give an 
output D.C. voltage U.sub.2. This is compared with a reference voltage 
U.sub.r2 in a comparator 8, and the difference voltage thus obtained is 
supplied to the pulse width modulator 12 via an amplifier 10. The control 
pulses to the chopper step 2 are pulse width regulated with the aid of the 
pulse width regulator 12 and the logical circuit 14, so that the trailing 
edge is varied in response to the value of the difference voltage from the 
comparator 8, as will be seen from the time chart in FIG. 3, where the 
indicating arrows denote, for the respective chopper step, which flank of 
the obtained output voltage U.sub.01, U.sub.02 is varied in the pulse 
width regulation process. A given phase shift .phi. between the 
pulse-formed output voltages U.sub.01 and U.sub.02 is furthermore obtained 
with the aid of a phase shifting circuit 16. 
The two pulse-formed output voltages from the chopper stages 1 and 2 each 
feed a half-wave rectifier 17a and 17b. The two D.C. voltages are 
connected in parallel, and together form the voltage U.sub.03, which is 
smoothed in a following lowpass filter 18 so that the output voltage 
U.sub.3 is obtained. A comparison circuit 19 is connected to the output of 
the smoothing filter for comparing the output voltage U.sub.3 with a 
reference voltage U.sub.r3, a difference voltage being obtained across the 
output of the comparison circuit, the output being connected to an 
amplifier 20. The output of the amplifier 20 is connected to a control 
input of the phase-shifting circuit 16 for phase-shifting, in response to 
the magnitude of the amplified difference signal, the clock pulses which 
are supplied to the phase-shifting circuit 16 from the clock circuit 15. 
As will be seen from FIG. 3, the pulse width of the rectified output 
voltage U.sub.03 will be varied by varying the phase angle .phi. in 
response to the difference signal from the comparison circuit 19. The mean 
value of the output voltage U.sub. 03 may thus be varied and regulation of 
the third output voltage U.sub.3 from the DC-DC converter is obtained. 
This regulation of the output voltage U.sub.3 does not affect the 
regulation of the two other output voltages U.sub.1 and U.sub.2, since 
only the trailing and the leading edges of both rectified output voltages 
U.sub.01, U.sub.02 are varied, which does not affect the output voltage 
U.sub.03. A condition is, however, that the phase relationship of U.sub.01 
and U.sub.02 is such that both these voltages overlap each other at the 
respective controlled edge. The following applies for the output voltages 
U.sub.1, U.sub.2 and U.sub.3 in the case where the lowpass filters 5, 6, 
18 are formed as LC-filters: 
##EQU1## 
where the time intervals tp.sub.1 and tp.sub.2 are varied with the aid of 
shifting the respective trailing and leading edges of the voltage pulses 
during each period. The logic circuits 13 and 14 may possibly be 
implemented such that the trailing or leading edge of only one pulse is 
varied, or that the variation is performed only during definite periods so 
that, for example the trailing (or the leading) edge for each fourth pulse 
is varied. The time interval t.sub.p3 is varied by the phase angle between 
the pulses in the output voltages U.sub.01 and U.sub.02 being varied. 
FIG. 2 more closely illustrates the transformer stage in the two chopper 
stages 1 and 2, as well as the connection to the following rectifiers. The 
blocks 1a and 2a are included in the respective chopper stage, and 
symbolize the conventional circuits performing the switching of the 
incoming D.C. voltage Udc, for obtaining the pulse-formed primary voltages 
U.sub.a and U.sub.b (according to FIG. 3) across the respective primary 
winding. The rectifiers 3 and 4 are constructed as rectifiers of a kind 
known per se, each containing two secondary winding parts s.sub.1, s.sub.2 
and s.sub.3, s.sub.4, respectively, with associated diodes D1, D2 and D3, 
D4. The rectifiers 17a and 17b are each built up from two full-wave 
rectifiers connected in parallel, of which one contains the secondary 
winding parts s.sub.5, s.sub.6 and diodes D5, D6 while the others contain 
the secondary winding parts s.sub.7, s.sub.8 and diodes D7, D8. The 
connection in parallel of the full-wave rectifiers 17a, 17b to the chopper 
stages 1 and 2, respectively, results in that the chopper steps 1 and 2 
share the load current to the commonly supplied output voltage U.sub.3. 
The three output voltages U.sub.1, U.sub.2 and U.sub.3, as well as the 
loads, can be dimensioned independent by from each other and may be 
expanded to an optimum number of output voltages. 
Three independent D.C. outputs are obtained with the proposed D.C.-D.C. 
converter. The three D.C. voltages over these outputs can be regulated 
independent by of each other with the aid of only two chopper stages and 
two transformers together with the associated control circuits.