Semiconductor device

A semiconductor device is provided. The semiconductor device includes a substrate including a first region and a second region, a first gate structure extending in a first direction on the first region of the substrate, the first gate structure including a first gate insulation film and a first work function film disposed on the first gate insulation film, and a second gate structure extending in the first direction on the second region of the substrate, the second gate structure including a second gate insulation film and a second work function film disposed on the second gate insulation film, wherein a first thickness of the first work function film in a second direction intersecting the first direction is different from a second thickness of the second work function film in the second direction, and wherein a first height of the first work function film in a third direction perpendicular to the first and second directions is different from a second height of the second work function film in the third direction.

This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2020-0045834, filed on Apr. 16, 2020, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

BACKGROUND

1. Technical Field

The present disclosure relates to a semiconductor device.

2. Description of the Related Art

Recently, with rapid spread of information media, functions of semiconductor devices have also been dramatically developed. In semiconductor products, low cost in manufacture and/or operation is beneficial for securement of competitiveness, and high integration of products is beneficial for miniaturization of products. For high integration, semiconductor devices are being scaled down.

On the other hand, as a pitch size decreases, it is beneficial to reduce capacitance between elements/signal lines and to secure electrical stability between contacts in semiconductor devices.

SUMMARY

Aspects of the present disclosure provide a semiconductor device capable of effectively controlling threshold voltages (Vt) of transistors in different regions, by differently forming thicknesses and heights of work function films of gate structures of transistors each disposed in different regions.

According to an exemplary embodiment of the present disclosure, there is provided a semiconductor device comprising a substrate including a first region and a second region, a first gate structure extending in a first direction on the first region of the substrate, the first gate structure including a first gate insulation film and a first work function film disposed on the first gate insulation film, and a second gate structure extending in the first direction on the second region of the substrate, the second gate structure including a second gate insulation film and a second work function film disposed on the second gate insulation film, wherein a first thickness of the first work function film in a second direction intersecting the first direction is different from a second thickness of the second work function film in the second direction, and wherein a first height of the first work function film in a third direction perpendicular to the first and second directions is different from a second height of the second work function film in the third direction.

According to an exemplary embodiment of the present disclosure, there is provided a semiconductor device comprising a substrate including a first region and a second region, a first gate structure extending in a first direction on the first region of the substrate, the first gate structure including a first work function film and a first filling conductive film disposed inside a first recess defined by the first work function film, and a second gate structure extending in the first direction on the second region of the substrate, the second gate structure including a second work function film and a second filling conductive film disposed inside a second recess defined by the second work function film, wherein a first width of the first filling conductive film disposed inside the first recess in a second direction intersecting the first direction is different from a second width of the second filling conductive film disposed inside the second recess in the second direction, and wherein a first height of the first work function film in a third direction perpendicular to the first and second directions is different from a second height of the second work function film in the third direction.

According to an exemplary embodiment of the present disclosure, there is provided a semiconductor device comprising a substrate including an NMOS region and a PMOS region, a first active pattern extending in a first direction on the NMOS region of the substrate, a first gate structure extending in a second direction intersecting the first direction on the first active pattern of the NMOS region, the first gate structure including a first gate insulation film, a first work function film conformally formed on the first gate insulation film, and a first filling conductive film disposed on the first work function film, a second active pattern extending in the first direction on the PMOS region of the substrate, a second gate structure extending in the second direction on the second active pattern of the PMOS region, the second gate structure including a second gate insulation film, a second work function film conformally formed on the second gate insulation film, and a second filling conductive film disposed on the second work function film, a first source/drain region disposed on at least one side of the first gate structure, and a second source/drain region disposed on at least one side of the second gate structure, wherein a first thickness of the first work function film in the first direction is smaller than a second thickness of the second work function film in the first direction, and wherein a first height of the first work function film in a third direction perpendicular to the first and second directions is smaller than a second height of the second work function film in the third direction.

DETAILED DESCRIPTION OF THE EMBODIMENTS

In the drawings of the semiconductor device according to some embodiments, although a fin-type transistor FinFET including a channel region of a fin-type pattern shape, and a transistor including a nanowire or a nanosheet are shown as an example, the present disclosure is not limited thereto. The semiconductor device according to some embodiments may, of course, include a tunneling FET or a three-dimensional (3D) transistor. The semiconductor device according to some embodiments may, of course, include a planar transistor. The semiconductor device according to some embodiments may, of course, include a bipolar junction transistor, a lateral diffusion metal oxide semiconductor (LDMOS) or the like.

Semiconductor devices according to some embodiments of the present disclosure will be described below with reference toFIGS. 1 to 3.

FIG. 1is a schematic plan view for explaining a semiconductor device according to some embodiments of the present disclosure.FIG. 2is a cross-sectional view taken along lines A-A′ and B-B′ ofFIG. 1.FIG. 3is a cross-sectional view taken along lines C-C′ and D-D′ ofFIG. 1.

Referring toFIGS. 1 to 3, the semiconductor device according to some embodiments of the present disclosure includes a substrate100, first and second active patterns101and102, a field insulation film105, a first gate structure110, a second gate structure120, a first source/drain region131, a second source/drain region132and an interlayer insulation film140.

The substrate100may be disposed over a first region I and a second region II. For example, the substrate100may include a first region I and a second region II. The first region I may be, for example, an NMOS region. The second region II may be, for example, a PMOS region. However, the present disclosure is not limited thereto. For example, in some other embodiments, both the first region I and the second region II may be NMOS regions. Also, in some other embodiments, both the first region I and the second region II may be PMOS regions. For example, NMOS regions may include NMOS transistors and may not include PMOS transistors, and PMOS regions may include PMOS transistors and may not include NMOS transistors.

The substrate100may be bulk silicon or SOI (silicon-on-insulator). Alternatively, the substrate100may be a silicon substrate or may include another material, for example, germanium, silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide or gallium antimonide. However, the present disclosure is not limited thereto.

The first active pattern101may extend in a first direction DR1on the substrate100of the first region I. The second active pattern102may extend in the first direction DR1on the substrate100of the second region II.

Each of the first active pattern101and the second active pattern102may be disposed to protrude from the substrate100. Each of the first active pattern101and the second active pattern102may be a part of the substrate100, and may include an epitaxial layer grown from the substrate100. Each of the first active pattern101and the second active pattern102may be defined by the field insulation film105.

The field insulation film105may be disposed on the substrate100. The field insulation film105may be disposed on side walls of each of the first active pattern101and the second active pattern102. Each of the first active pattern101and the second active pattern102may protrude upward from the upper surface of the field insulation film105. The field insulation film105may include, for example, an oxide film, a nitride film, an oxynitride film or a combination film thereof.

The first gate structure110may be disposed on the first active pattern101and the field insulation film105over the substrate100in the first region I. The first gate structure110may extend in a second direction DR2intersecting the first direction DR1. The first gate structure110may have a first width GW1in the first direction DR1.

The first gate structure110may include a first gate spacer111, a first gate insulation film112, a first work function film113, a first filling conductive film114and a first capping pattern115.

The first gate spacer111may form both side walls of the first gate structure110in the first direction DR1. The first gate spacer111may extend in the second direction DR2. The first gate spacer111may define a first gate trench GT1.

The first gate insulation film112may be conformally disposed along the side walls and bottom surface of the first gate trench GT1. The first gate insulation film112may be disposed along the profile of the first active pattern101protruding upward from the field insulation film105and an upper surface of the field insulation film105. Although it is not shown, an interface film may be further disposed along the profile of the first active pattern101protruding upward from the field insulation film105. In this case, the first gate insulation film112may be disposed on the interface film. For example, the interface film may be formed between the first gate insulation film112and the field insulation film105. For example, the interface film may be formed between the first gate insulation film112and the first active pattern101.

The first gate insulation film112may include silicon oxide, silicon oxynitride, silicon nitride or a high-dielectric constant material having a higher dielectric constant than silicon oxide. The high-dielectric constant material may include, for example, one or more of hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide or lead zinc niobate.

The first work function film113may be disposed on the first gate insulation film112inside the first gate trench GT1. The first work function film113may be conformally arranged/formed along/on the first gate insulation film112formed on the bottom surface and side walls of the first gate trench GT1.

For example, the upper surface of the first work function film113may be formed to be lower than the upper surface of the first gate insulation film112. For example, upper ends of the first gate insulation film112and the first work function film113formed on a side wall of the first gate trench GT1may be at different vertical levels from each other. For example, an upper end of the first gate insulation film112formed on the side wall of the first gate trench GT1may be at a higher vertical level than an upper end of the first work function film113formed on the sidewall of the first gate trench GT1. However, the present disclosure is not limited thereto. For example, in some other embodiments, the upper surface of the first work function film113may be formed on the same plane as the upper surface of the first gate insulation film112. For example, in certain embodiments, the upper ends of the first work function film113and the first gate insulation film112formed on a sidewall of the first gate trench GT1may be at the same vertical level.

The first work function film113may have a first thickness t1in the first direction DR1. For example, the first work function film113formed on the sidewall of the first gate trench GT1may have the first thickness t1in the first direction DR1. The first work function film113may have a first height h1in a third direction DR3perpendicular to the first and second directions DR1and DR2. For example, the first work function film113formed on a sidewall of the first gate trench GT1may have the first height h1in the third direction DR3. For example, heights in the present disclosure may be vertical lengths of corresponding elements.

The first work function film113may include, for example, at least one of TiN, TaN, and a combination thereof.

AlthoughFIG. 2shows that the first work function film113is formed of a single film, the present disclosure is not limited thereto. For example, in some other embodiments, the first work function film113may be formed of multi-films, e.g., multilayers of films. In a case that the first work function film113is the multi-films, a TiN layer may be formed to be in contact with the first gate insulation film112, and a TaN layer may be formed on the TiN layer to be in contact with the TiN layer.

It will be understood that when an element is referred to as being “connected,” “coupled to” or “on” another element, it can be directly connected/coupled to/on the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, or as “contacting” or “in contact with” another element, there are no intervening elements present.

The first filling conductive film114may be disposed on the first gate insulation film112and the first work function film113inside the first gate trench GT1. For example, the first filling conductive film114may contact the first work function film113at a bottom and on a lower sidewall of the first gate trench GT1, and may contact the first gate insulation film112on an upper sidewall of the first gate trench GT1. The first filling conductive film114may include a first lower conductive film114_1and a first upper conductive film114_2.

For example, the upper surface of the first filling conductive film114may be formed on the same plane as the upper surface of the first gate insulation film112. For example, the upper surface of the first filling conductive film114may be at the same vertical level as the upper end of the first gate insulation film112. However, the present disclosure is not limited thereto. For example, vertical levels described in the present disclosure may be distances in the third direction DR3from a plane parallel to the substrate100(e.g., from a top or bottom surface of the substrate100.)

The first filling conductive film114may completely fill a first recess R1defined by the first work function film113. For example, the upper surface of the first filling conductive film114may be at a higher vertical level than the upper end of the first work function film113formed on the sidewall of the first gate trench GT1. The first filling conductive film114disposed inside the first recess R1may have a first width FW1in the first direction DR1.

The first lower conductive film114_1may be conformally disposed along the first gate insulation film112and the first work function film113inside the first gate trench GT1. The first lower conductive film114_1may be in contact with each of the first gate insulation film112and the first work function film113.

The first lower conductive film114_1may include a material that adjusts a threshold voltage of the semiconductor device, for example, TiA1C.

The first upper conductive film114_2may be disposed on the first lower conductive film114_1inside the first gate trench GT1. The first upper conductive film114_2may be disposed to completely fill a region surrounded by the first lower conductive film114_1. For example, the top surfaces of the first lower and upper conductive films114_1and114_2may be coplanar.

Although the first upper conductive film114_2may include, for example, tungsten (W), aluminum (Al), cobalt (Co), and the like, the present disclosure is not limited thereto.

The first capping pattern115may fill the remaining parts inside the first gate trench GT1. For example, the first capping pattern115may be formed on the first gate insulation film112and the first filling conductive film114inside the first gate trench GT1. The upper surface of the first capping pattern115may be formed on the same plane as the upper surface of the first gate spacer111. For example, the upper surface of the first capping pattern115and the upper surface of the first gate spacer111may be coplanar and may be disposed at the same vertical level.

The first capping pattern115may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiCN), silicon carbide oxynitride (SiOCN), and combinations thereof.

The second gate structure120may be disposed on the second active pattern102and the field insulation film105over the substrate100of the second region II. The second gate structure120may extend in the second direction DR2. The second gate structure120may have a second width GW2in the first direction DR1. For example, the second width GW2of the second gate structure120in the first direction DR1may be the same as the first width GW1of the first gate structure110in the first direction DR1. However, the present disclosure is not limited thereto.

The second gate structure120may include a second gate spacer121, a second gate insulation film122, a second work function film123, a second lower conductive film124_1, a second upper conductive film124_2and a second capping pattern125.

Each of the second gate spacer121, the second gate insulation film122, the second lower conductive film124_1, the second upper conductive film124_2and the second capping pattern125may have a structure similar to or the same as corresponding one of the first gate spacer111, the first gate insulation film112, the first lower conductive film114_1, the first upper conductive film114_2, and the first capping pattern115. Therefore, each of the second gate spacer121, the second gate insulation film122, the second lower conductive film124_1, the second upper conductive film124_2, and the second capping pattern125will not be specifically explained.

The second work function film123may be disposed on the second gate insulation film122inside the second gate trench GT2. The second work function film123may be conformally disposed along the second gate insulation film122.

For example, the upper surface of the second work function film123may be formed to be lower than the upper surface of the second gate insulation film122. For example, upper ends of the second gate insulation film122and the second work function film123formed on a side wall of the second gate trench GT2may be in different vertical levels from each other. For example, an upper end of the second gate insulation film122formed on the side wall of the second gate trench GT2may be at a higher vertical level than an upper end of the second work function film123formed on the sidewall of the second gate trench GT2. However, the present disclosure is not limited thereto. For example, in some other embodiments, the upper surface of the second work function film123may be formed on the same plane as the upper surface of the second gate insulation film122. For example, in certain embodiments, the upper ends of the second work function film123and the second gate insulation film122formed on a sidewall of the second gate trench GT2may be coplanar and at the same vertical level.

The second work function film123may have a second thickness t2in the first direction DR1. For example, the second work function film123formed on the sidewall of the second gate trench GT2may have the second thickness t2in the first direction DR1. The second thickness t2of the second work function film123in the first direction DR1may be different from the first thickness t1of the first work function film113in the first direction DR1. For example, the second thickness t2of the second work function film123in the first direction DR1may be greater than the first thickness t1of the first work function film113in the first direction DR1.

The second work function film123may have a second height h2in the third direction DR3. For example, the second work function film123formed on a sidewall of the second gate trench GT2may have the second height h2in the third direction DR3. The second height h2of the second work function film123in the third direction DR3may be different from the first height h1of the first work function film113in the third direction DR3. For example, the second height of the second work function film123in the third direction DR3may be greater than the first height h1of the first work function film113in the third direction DR3.

The second work function film123may include, for example, at least one of TiN, TaN, and a combination thereof.

AlthoughFIG. 2shows that the second work function film123is formed of a single film, the present disclosure is not limited thereto. For example, in some other embodiments, the second work function film123may be formed of multi-films, e.g., multilayers of films. When the second work function film123is the multi-films, a TiN layer may be formed to be in contact with the second gate insulation film122, and a TaN layer may be formed on the TiN layer to be in contact with the TiN layer.

The second filling conductive film124may be disposed on the second gate insulation film122and the second work function film123inside the second gate trench GT2. For example, the second filling conductive film124may contact the second work function film123at a bottom and on a lower sidewall of the second gate trench GT2, and may contact the second gate insulation film122on an upper sidewall of the second gate trench GT2.

The second filling conductive film124may completely fill a second recess R2defined by the second work function film123. For example, an upper surface of the second filling conductive film124may be at a higher vertical level than the upper end of the second work function film123formed on the sidewall of the second gate trench GT2. The second filling conductive film124disposed inside the second recess R2may have a second width FW2in the first direction DR1. The second width FW2of the second filling conductive film124in the first direction DR1may be different from the first width FW1of the first filling conductive film114in the first direction DR1. For example, the second width FW2of the second filling conductive film124in the first direction DR1may be smaller than the first width FW1of the first filling conductive film114in the first direction DR1.

The first source/drain region131may be disposed at least on one side of the first gate structure110in the first region I. For example, the first source/drain region131may be formed on both sides of the first gate structure110in the first region I. A second source/drain region132may be disposed on at least one side of the second gate structure120in the second region II. For example, the second source/drain region132may be formed on both sides of the second gate structure120in the second region II.

The interlayer insulation film140may be disposed on the field insulation film105. The interlayer insulation film140may be formed/disposed to cover sidewalls of the first gate structure110, sidewalls of the second gate structure120, the first source/drain region131and the second source/drain region132.

The semiconductor device according to some embodiments of the present disclosure may effectively adjust Vt in different regions, by differently forming thicknesses and heights of the first work function film113of the first gate structure110and the second work function film123of the second gate structure120disposed in different regions from each other.

Hereinafter, the semiconductor device according to some other embodiments of the present disclosure will be described with reference toFIG. 4. Differences from the semiconductor device shown inFIGS. 2 and 3will be mainly described.

FIG. 4is a cross-sectional view for explaining the semiconductor device according to some other embodiments of the present disclosure.

Referring toFIG. 4, in the semiconductor device according to some other embodiments of the present disclosure, a third height h3in the third direction DR3of a first work function film213of a first gate structure210may be higher than a fourth height h4in the third direction DR3of a second work function film223of a second gate structure220.

The first thickness t1in the first direction DR1of the first work function film213of the first gate structure210may be smaller than the second thickness t2in the first direction DR1of the second work function film223of the second gate structure220. For example, the first and second thicknesses t1and t2may be thicknesses of the first and second work function films213and223formed on the respective sidewalls of the first and second gate trenches GT1and GT2.

The first filling conductive film214may include a first lower conductive film214_1, and a first upper conductive film214_2disposed on the first lower conductive film214_1. The second filling conductive film224may include a second lower conductive film224_1, and a second upper conductive film224_2disposed on the second lower conductive film224_1.

The first filling conductive film214may completely fill a third recess R3defined by the first work function film213. For example, an upper surface of the first filling conductive film214may be at a higher vertical level than an upper end of the first work function film213formed on the sidewall of the first gate trench GT1. The second filling conductive film224may completely fill a fourth recess R4defined by the second work function film223. For example, an upper surface of the second filling conductive film224may be at a higher vertical level than an upper end of the second work function film223formed on the sidewall of the second gate trench GT2.

A first width FW1in the first direction DR1of the first filling conductive film214disposed inside the third recess R3may be greater than a second width FW2in the first direction DR1of the second filling conductive film224disposed inside the fourth recess R4.

Hereinafter, a semiconductor device according to some other embodiments of the present disclosure will be described with reference toFIG. 5. Differences from the semiconductor device shown inFIGS. 2 and 3will be mainly described.

FIG. 5is a cross-sectional view for explaining a semiconductor device according to some other embodiments of the present disclosure.

Referring toFIG. 5, in the semiconductor device according to some other embodiments of the present disclosure, a first height h1in the third direction DR3of a first work function film313of a first gate structure310may be smaller than the second height h2in the third direction DR3of a second work function film323of a second gate structure320. For example, the first and second heights h1and h2of the first and second work function films313and323may be heights of portions of the work function films313and323formed on the respective sidewalls of the first and second gate trenches GT1and GT2.

A third thickness t3in the first direction DR1of the first work function film313of the first gate structure310may be greater than a fourth thickness t4in the first direction DR1of the second work function film323of the second gate structure320. For example, the third and fourth thicknesses t3and t4may be thicknesses of the third and fourth work function films313and323formed on the respective sidewalls of the first and second gate trenches GT1and GT2.

The first filling conductive film314may include a first lower conductive film314_1, and a first upper conductive film314_2disposed on the first lower conductive film314_1. The second filling conductive film324may include a second lower conductive film324_1, and a second upper conductive film324_2disposed on the second lower conductive film324_1.

The first filling conductive film314may completely fill a fifth recess R5defined by the first work function film313. The second filling conductive film324may completely fill a sixth recess R6defined by the second work function film323. For example, an upper surface of the first filling conductive film314may be at a higher vertical level than an upper end of the first work function film313formed on the sidewall of the first gate trench GT1. For example, an upper surface of the second filling conductive film324may be at a higher vertical level than an upper end of the second work function film323formed on the sidewall of the second gate trench GT2.

A third width FW3in the first direction DR1of the first filling conductive film314disposed inside the fifth recess R5may be smaller than a fourth width FW4in the first direction DR1of the second filling conductive film324disposed inside the sixth recess R6.

Hereinafter, a semiconductor device according to some other embodiments of the present disclosure will be described with reference toFIGS. 6 and 7. Differences from the semiconductor device shown inFIGS. 1 to 3will be mainly described.

FIG. 6is a schematic plan view for explaining the semiconductor device according to some other embodiments of the present disclosure.FIG. 7is a cross-sectional view taken along lines E-E′ and B-B′ ofFIG. 6.

Referring toFIGS. 6 and 7, in the semiconductor device according to some other embodiments of the present disclosure, both the first region I and the second region II may be NMOS regions, or both the first region I and the second region II may be PMOS regions.

A third width GW3of a first gate structure410in the first direction DR1is greater than a second width GW2of the second gate structure120in the first direction DR1.

A first height h1in the third direction DR3of a first work function film413of the first gate structure410may be smaller than a second height h2in the third direction DR3of the second work function film123of the second gate structure120. For example, the first and second heights h1and h2of the first and second work function films413and123may be heights of portions of the work function films413and123formed on the respective sidewalls of a third gate trench GT3and the second gate trench GT2as shown inFIG. 7.

The first thickness t1in the first direction DR1of the first work function film413of the first gate structure410may be smaller than the second thickness t2in the first direction DR1of the second work function film123of the second gate structure120. For example, the first and second thicknesses t1and t2may be thicknesses of the first and second work function films413and123formed on the respective sidewalls of the third gate trench GT3and the second gate trench GT2.

The first gate insulation film112, the first work function film413, and the first filling conductive film414may be disposed inside a third gate trench GT3defined by the first gate spacer111. For example, sidewalls of the third gate trench GT3may be defined by the first gate spacer111and bottom of the third gate trench GT3may be defined by the first active pattern101in a channel area and by the field insulation film105in areas other than a channel area.

The first filling conductive film414may include a first lower conductive film414_1, and a first upper conductive film414_2disposed on the first lower conductive film414_1. The first filling conductive film414may completely fill a seventh recess R7defined by the first work function film413. For example, an upper surface of the first filling conductive film414may be at a higher vertical level than an upper end of the first work function film413formed on the sidewall of the third gate trench GT3. For example, the upper surface of the first filling conductive film414may be at the same vertical level as an upper end of the first gate insulation film112formed on the sidewall of the third gate trench GT3as shown inFIG. 7.

A fifth width FW5in the first direction DR1of the first filling conductive film414disposed inside the seventh recess R7may be greater than the second width FW2in the first direction DR1of the second filling conductive film124disposed inside the second recess R2.

Hereinafter, a semiconductor device according to some other embodiments of the present disclosure will be described with reference toFIG. 8. Differences from the semiconductor device shown inFIGS. 1 to 3 and 5will be mainly described.

FIG. 8is a cross-sectional view for explaining a semiconductor device according to some other embodiments of the present disclosure.

Referring toFIG. 8, in the semiconductor device according to some other embodiments of the present disclosure, both the first region I and the second region II may be NMOS regions, or both the first region I and the second region II may be PMOS regions.

A third width GW3of a first gate structure510in the first direction DR1may be greater than the second width GW2of the second gate structure320in the first direction DR1.

A first height h1in the third direction DR3of a first work function film513of the first gate structure510may be smaller than a second height h2in the third direction DR3of the second work function film323of the second gate structure320. For example, the first and second heights h1and h2of the first and second work function films513and323may be heights of portions of the work function films513and323formed on the respective sidewalls of a third gate trench GT3and the second gate trench GT2as shown inFIG. 8.

A third thickness t3in the first direction DR1of the first work function film513of the first gate structure510may be greater than a fourth thickness t4in the first direction DR1of the second work function film323of the second gate structure320. For example, the third and fourth thicknesses t3and t4may be thicknesses of the first and second work function films513and323formed on the respective sidewalls of the third gate trench GT3and the second gate trench GT2as shown inFIG. 8.

The first gate insulation film112, the first work function film513, and the first filling conductive film514may be disposed inside a third gate trench GT3defined by the first gate spacer111. For example, sidewalls of the third gate trench GT3may be defined by the first gate spacers111and bottom of the third gate trench GT3may be defined by the first active pattern101in a channel area as shown inFIG. 8.

The first filling conductive film514may include a first lower conductive film514_1, and a first upper conductive film514_2disposed on the first lower conductive film514_1. The first filling conductive film514may completely fill an eighth recess R8defined by the first work function film513. For example, an upper surface of the first filling conductive film514may be at a higher vertical level than an upper end of the first work function film513formed on the sidewall of the third gate trench GT3.

A sixth width FW6in the first direction DR1of the first filling conductive film514disposed inside the eighth recess R8may be greater than the fourth width FW4in the first direction DR1of the second filling conductive film324disposed inside the sixth recess R6.

Hereinafter, a semiconductor device according to some other embodiments of the present disclosure will be described with reference toFIG. 9. Differences from the semiconductor device shown inFIGS. 1 to 4will be mainly described.

FIG. 9is a cross-sectional view for explaining a semiconductor device according to some other embodiments of the present disclosure.

Referring toFIG. 9, in the semiconductor device according to some other embodiments of the present disclosure, both the first region I and the second region II may be NMOS regions or both the first region I and the second region II may be PMOS regions.

A third width GW3of a first gate structure610in the first direction DR1may be greater than a second width GW2of the second gate structure220in the first direction DR1.

A third height h3in the third direction DR3of a first work function film613of the first gate structure610may be higher than a fourth height h4in the third direction DR3of the second work function film223of the second gate structure220. For example, the third and fourth heights h3and h4of the first and second work function films613and223may be heights of portions of the work function films613and223formed on the respective sidewalls of a third gate trench GT3and the second gate trench GT2as shown inFIG. 9.

The first thickness t1in the first direction DR1of the first work function film613of the first gate structure610may be smaller than the second thickness t2in the first direction DR1of the second work function film223of the second gate structure220. For example, the first and second thicknesses t1and t2may be thicknesses of the first and second work function films613and223formed on the respective sidewalls of the third gate trench GT3and the second gate trench GT2as shown inFIG. 9.

The first gate insulation film112, the first work function film613and the first filling conductive film614may be disposed inside the third gate trench GT3defined by the first gate spacer111. For example, sidewalls of the third gate trench GT3may be defined by the first gate spacers111and bottom of the third gate trench GT3may be defined by the first active pattern101in a channel area as shown inFIG. 9.

The first filling conductive film614may include a first lower conductive film614_1, and a first upper conductive film614_2disposed on the first lower conductive film614_1. The first filling conductive film614may completely fill a ninth recess R9defined by the first work function film613. For example, an upper surface of the first filling conductive film614may be at a higher vertical level than an upper end of the first work function film613formed on the sidewall of the third gate trench GT3as shown inFIG. 9.

A fifth width FW5in the first direction DR1of a first filling conductive film614disposed inside the ninth recess R9may be greater than a second width FW2in the first direction DR1of the second filling conductive film224disposed inside the fourth recess R4.

Hereinafter, a semiconductor device according to some other embodiments of the present disclosure will be described with reference toFIGS. 10 and 11. Differences from the semiconductor device shown inFIGS. 1 to 3will be mainly described.

FIGS. 10 and 11are cross-sectional views for explaining a semiconductor device according to some other embodiments of the present disclosure.

Referring toFIGS. 10 and 11, the semiconductor device according to some other embodiments of the present disclosure may include an MBCFET™ (Multi-Bridge Channel Field Effect Transistor).

For example, the semiconductor device according to some embodiments of the present disclosure may include a plurality of nanowires sequentially stacked on a substrate100to be spaced apart from each other in the third direction DR3.

First to third nanowires751,752and753may be sequentially stacked on the substrate100of the first region I to be spaced apart from each other in the third direction DR3. Fourth to sixth nanowires754,755and756may be sequentially stacked on the substrate100of the second region II to be spaced apart from each other in the third direction DR3. Each of the first to sixth nanowires751,752,753,754,755and756may extend in the first direction DR1.

The first gate structure710may surround each of the first to third nanowires751,752and753, e.g., in a cross-sectional view as shown inFIG. 11. The first gate structure710may include a first gate spacer711, a first gate insulation film712, a first work function film713, a first filling conductive film714and a first capping pattern715. The first filling conductive film714may include a first lower conductive film714_1and a first upper conductive film714_2.

The second gate structure720may surround each of the fourth to sixth nanowires754,755and756, e.g., in a cross-sectional view as shown inFIG. 11. The second gate structure720may include a second gate spacer721, a second gate insulation film722, a second work function film723, a second filling conductive film724and a second capping pattern725. The second filling conductive film724may include a second lower conductive film724_1and a second upper conductive film724_2.

A fourth width GW4of the first gate structure710in the first direction DR1may be the same as a fifth width GW5of the second gate structure720in the first direction DR1.

A first source/drain region731may be disposed on at least one side of each of the first to third nanowires751,752and753. For example, a pair of first source/drain regions731may be formed on both sides of the first to third nanowires751,752and753. A second source/drain region732may be disposed on at least one side of each of the fourth to sixth nanowires754,755and756. For example, a pair of second source/drain regions732may be formed on both sides of the fourth to sixth nanowires754,755and756.

An interlayer insulation film740may be disposed to cover sidewalls of the first gate structure710, sidewalls of the second gate structure720, the first source/drain region731and the second source/drain region732.

A semiconductor device according to some other embodiments of the present disclosure will be described below with reference toFIG. 12. Differences from the semiconductor device shown inFIGS. 1 to 3 and 10will be mainly described.

FIG. 12is a cross-sectional view for explaining a semiconductor device according to some other embodiments of the present disclosure.

Referring toFIG. 12, a semiconductor device according to some other embodiments of the present disclosure may include an MBCFET™ (Multi-Bridge Channel Field Effect Transistor).

First to third nanowires851,852and853may be sequentially stacked on the substrate100of the first region I to be spaced apart from each other in the third direction DR3. Each of the first to third nanowires851,852and853may extend in the first direction DR1.

Lengths of each of the first to third nanowires851,852and853in the first direction DR1may be greater than lengths of each of the fourth to sixth nanowires754,755and756in the first direction DR1. For example, the lengths of the first to third nanowires851,852and853in the first direction DR1may be greater than respective lengths of the fourth to sixth nanowires754,755and756in the first direction DR1.

The first gate structure810may surround each of the first to third nanowires851,852and853. The first gate structure810may include a first gate spacer711, a first gate insulation film712, a first work function film813, a first filling conductive film814and a first capping pattern715. The first filling conductive film814may include a first lower conductive film814_1and a first upper conductive film814_2.

A sixth width GW6of the first gate structure810in the first direction DR1may be greater than a fifth width GW5of the second gate structure720in the first direction DR1.

A method for fabricating a semiconductor device according to some embodiments of the present disclosure will be described below with reference toFIGS. 2 and 13 to 23.

FIGS. 13 to 23are intermediate stage diagrams for explaining the method for fabricating the semiconductor device according to some embodiments of the present disclosure.

Referring toFIG. 13, a first dummy gate161is formed on the substrate100of the first region I, and a second dummy gate162may be formed on the substrate100of the second region II. Each of the first dummy gate161and the second dummy gate162may extend in the second direction DR2.

Subsequently, a first gate spacer111is formed along both side walls of the first dummy gate161, and a second gate spacer121may be formed along both side walls of the second dummy gate162.

Referring toFIG. 14, the substrate100of the first region I may be etched, using the first dummy gate161and the first gate spacer111as a mask. Also, the substrate100of the second region II may be etched, using the second dummy gate162and the second gate spacer121as a mask.

Next, a first source/drain region131is formed in a region in which the substrate100of the first region I is etched, and a second source/drain region132may be formed in a region in which the substrate100of the second region II is etched.

Referring toFIG. 15, an interlayer insulation film140is formed to cover the first dummy gate161, the first gate spacer111, the second dummy gate162and the second gate spacer121.

Next, a planarization process (e.g., a CMP process) may be performed to expose the upper surfaces of each of the first dummy gate161and the second dummy gate162.

Next, the first dummy gate161may be removed to form a first gate trench GT1between the first gate spacers111, and the second dummy gate162may be removed to form a second gate trench GT2between the second gate spacers121.

Referring toFIG. 16, the first gate insulation film112and the first work function film113may be sequentially formed along the upper surface of the interlayer insulation film140, the upper surface of the first gate spacer111, and the side walls and bottom surface of the first gate trench GT1.

Further, the second gate insulation film122and the second work function films123may be sequentially formed along the upper surface of the interlayer insulation film140, the upper surface of the second gate spacer121, and the side walls and the bottom surface of the second gate trench GT2.

In this case, the thickness of the second work function film123in the first direction DR1may be formed to be larger than the thickness of the first work function film113in the first direction DR1. For example, the thickness of the second work function film123in the first direction DR1on a sidewall of the second gate spacer121may be formed to be larger than the thickness of the first work function film113in the first direction DR1on a sidewall of the first gate spacer111.

Referring toFIG. 17, in the first region I, the first gate insulation film112and the first work function film113formed on the upper surface of the interlayer insulation film140and the upper surface of the first gate spacer111may be removed. In this case, at least a part of the upper side wall of the first gate trench GT1may be exposed. In addition, at least a part of an upper side wall of the first gate insulation film112may be exposed. For example, the upper surface of the first work function film113is formed to be lower than the upper surface of the first gate insulation film112, and the upper surface of the first gate insulation film112may be formed to be lower than the upper surface of the first gate spacer111, e.g., on the sidewalls of the first gate trench GT1.

In the second region II, the second gate insulation film122and the second work function film123formed on the upper surface of the interlayer insulation film140and the upper surface of the second gate spacer121may be removed. In this case, at least a part of the upper side wall of the second gate trench GT2may be exposed. In addition, at least a part of the upper side wall of the second gate insulation film122may be exposed. For example, the upper surface of the second work function film123is formed to be lower than the upper surface of the second gate insulation film122, and the upper surface of the second gate insulation film122may be formed to be lower than the upper surface of the second gate spacer121, e.g., on the sidewalls of the second gate trench GT2.

Referring toFIG. 18, a protective film170may be formed to fill each of the remaining region of the first gate trench GT1and the remaining region of the second gate trench GT2. The protective film170may include, for example, SOH.

Subsequently, a photoresist pattern180may be formed to cover the interlayer insulation film140, the second gate spacer121and the protective film170of the second region II.

Referring toFIG. 19, a part of the protective film170formed in the first region I may be etched. The upper surface of the etched protective film170may be formed to be lower than the upper surface of the first work function film113.

Referring toFIG. 20, a part of the first work function film113formed in the first region I may be etched. The upper surface of the etched first work function film113may be formed on the same plane as the upper surface of the protective film170.

Referring toFIG. 21, the protective film170formed in the first region I may be completely removed.

Referring toFIG. 22, the photoresist pattern180and the protective film170formed in the second region II may be removed.

Referring toFIG. 23, in the first region I, a first lower conductive film114_1may be conformally formed on the upper surface of the interlayer insulation film140and the upper surface of the first gate spacer111, and inside the first gate trench GT1. For example, the first lower conductive film114_1may be conformally formed on the first work function film113and on the first gate insulation film112inside the first gate trench GT1. In the second region II, a second lower conductive film124_1may be conformally formed on the upper surface of the interlayer insulation film140and the upper surface of the second gate spacer121, and inside the second gate trench GT2. For example, the second lower conductive film124_1may be conformally formed on the second work function film123and on the second gate insulation film122inside the second gate trench GT2.

Next, a first upper conductive film114_2may be formed on the first lower conductive film114_1. The first upper conductive film114_2may be formed to completely fill the remaining region of the first gate trench GT1. A second upper conductive film124_2may be formed on the second lower conductive film124_1. The second upper conductive film124_2may be formed to completely fill the remaining region of the second gate trench GT2.

Referring toFIG. 2, the first upper conductive film114_2, the second upper conductive film124_2, the first lower conductive film114_1and the second lower conductive film124_1may be etched to expose the upper surface of the interlayer insulation film140, the upper surface of the first gate spacer111and the upper surface of the second gate spacer121. In this case, a part of the first upper conductive film114_2and a part of the first lower conductive film114_1formed inside the first gate trench GT1may be etched. For example, the first lower and upper conductive films114_1and114_2may be etched for the upper surfaces of the first lower and upper conductive films114_1and114_2and the upper end of the first gate insulation film112formed on sidewalls of the first gate trench GT1to be coplanar. In addition, a part of the second upper conductive film124_2and a part of the second lower conductive film124_1formed inside the second gate trench GT2may be etched. For example, the second lower and upper conductive films124_1and124_2may be etched for the upper surfaces of the second lower and upper conductive films124_1and124_2and the upper end of the second gate insulation film122formed on sidewalls of the second gate trench GT2to be coplanar.

Next, a first capping pattern115is formed in the remaining region of the first gate trench GT1, and a second capping pattern125may be formed in the remaining region of the second gate trench GT2. A semiconductor device shown inFIG. 2may be fabricated through such a process.