Semiconductor devices including a conductive pattern contacting a channel pattern and methods of manufacturing the same

A semiconductor device includes a plurality of insulation patterns and a plurality of gates alternately and repeatedly stacked on a substrate, a channel pattern extending through the gates in a first direction substantially perpendicular to a top surface of the substrate, a semiconductor pattern between the channel pattern and the substrate, and a conductive pattern between the channel pattern and the semiconductor pattern. The conductive pattern electrically connects the channel pattern to the semiconductor pattern. The conductive pattern contacts a bottom edge of the channel pattern and an upper surface of the semiconductor pattern.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 USC §119 to Korean Patent Application No. 10-2015-0127841, filed on Sep. 9, 2015 in the Korean Intellectual Property Office (KIPO), the contents of which are herein incorporated by reference in their entirety.

BACKGROUND

Example embodiments relate to semiconductor devices and methods of manufacturing the same. More particularly, example embodiments relate to vertical type memory devices and methods of manufacturing the same.

2. Description of the Related Art

In a vertical type memory device, a vertical channel pattern and a substrate may be electrically connected to each other. However, as an aspect ratio of the vertical channel pattern increases, an electrical connection between the vertical channel pattern and the substrate may be more difficult.

SUMMARY

Example embodiments provide a semiconductor device having good electrical characteristics.

Example embodiments provide a method of manufacturing a semiconductor device having good electrical characteristics.

According to example embodiments, a semiconductor device includes a substrate; a plurality of insulation patterns and a plurality of gates alternately and repeatedly stacked on the substrate; a channel pattern extending through the gates in a first direction substantially perpendicular to a top surface of the substrate; a semiconductor pattern between the channel pattern and the semiconductor pattern; and a conductive pattern between the channel pattern and the semiconductor pattern. The conductive pattern electrically connects the channel pattern to the semiconductor pattern. The conductive pattern may contact a bottom edge of the channel pattern and an upper surface of the semiconductor pattern.

In example embodiments, the conductive pattern may include polysilicon

In example embodiments, the conductive pattern may contact the bottom edge of the channel pattern.

In example embodiments, the conductive pattern may directly contact the bottom edge and a lower sidewall of the channel pattern.

In example embodiments, an insulation structure may be formed between the channel pattern and the semiconductor pattern. The insulation structure may contact an inner sidewall of the conductive pattern.

In example embodiments, a data storage structure may be between the channel pattern and the gates. The data storage structure may include a tunnel insulation pattern, a charge storage pattern and a blocking pattern.

In example embodiments, the insulation structure may include materials that are the same as materials in the data storage structure.

In example embodiments, the insulation structure may include a first pattern, a second pattern and a third pattern on the semiconductor pattern. The first, second, and third patterns may have materials that are the same as materials in the blocking pattern, the charge storage pattern and the tunnel insulation pattern, respectively.

In example embodiments, the data storage structure may extend along a sidewall of the channel pattern, and the data storage structure may have a hollow cylindrical shape.

In example embodiments, the data storage structure may be spaced apart from an upper surface of the semiconductor pattern.

In example embodiments, the conductive pattern may contact the bottom edge of the channel pattern, a lower sidewall of the channel pattern, and a bottom of the data storage structure.

In example embodiments, the insulation structure may include a plurality of stacked patterns, and at least one of the stacked patterns may protrude from a different one of the stacked patterns in a lateral direction.

In example embodiments, a width of each of the stacked patterns of the insulation pattern may be smaller than a width of a bottom of the channel pattern.

In example embodiments, a lower gate may surround a sidewall of the semiconductor pattern, and the lower gate may extend in a direction parallel to the top surface of the substrate.

According to example embodiments, a semiconductor device includes a substrate; a plurality of gates on the substrate, and the gates being spaced apart from each other and the substrate in a first direction substantially perpendicular to a top surface of the substrate; a channel structure extending through the gates in the first direction, the channel structure being spaced apart from the top surface of the substrate, and the channel structure including a channel pattern and a data storage structure extending along a sidewall of the channel pattern; and a conductive pattern between the channel pattern and the substrate. The conductive pattern electrically connects the channel pattern to the substrate. The conductive pattern may contact a bottom edge of the channel pattern and the top surface of the substrate.

In example embodiments, an insulation structure may be between the channel pattern and the semiconductor pattern, and the insulation structure may contact an inner sidewall of the conductive pattern.

In example embodiments, the insulation structure may include stacked patterns, and the stacked patterns may include materials that are the same as materials in the data storage structure.

In example embodiments, a bottom of the data storage structure may be above a bottom of the channel pattern.

In example embodiments, the semiconductor device may further include a semiconductor pattern between the substrate and the conductive pattern, and a lower gate surrounding a sidewall of the semiconductor pattern. The lower gate may extend in a direction parallel to the top surface of the substrate.

According to example embodiments, there is provided a method of manufacturing a semiconductor device. The method includes: forming a structure on a substrate, where the structure includes a first mold structure, a lower sacrificial pattern, and a second mold structure sequentially stacked, and the structure defines a channel hole therethrough that exposes the substrate; forming a semiconductor pattern in a lower portion of the channel hole, the semiconductor pattern contacting the substrate; sequentially forming a preliminary data storage structure and a channel pattern in the channel hole; removing the lower sacrificial pattern to form a first gap exposing the preliminary data storage structure; forming a data storage structure on the sidewall of the channel pattern and an insulation structure on a bottom of the channel pattern, where the forming the data storage structure and the forming the insulation structure include partially etching the preliminary storage structure through the first gap until a sidewall of the channel structure is exposed; and forming a conductive pattern along a sidewall of the insulation structure; and forming a first gate and a plurality of second gates on the substrate. The conductive pattern electrically connects the channel pattern to the semiconductor pattern. The first gate surrounds the semiconductor pattern and extends in a second direction substantially parallel to a top surface of the substrate may be formed. Each of the second gates may surround the data storage structure, and may extend in the second direction.

In example embodiments, an upper surface of the semiconductor pattern may be formed between an upper surface of the lower sacrificial pattern and a lower surface of the lower sacrificial pattern.

In example embodiments, the forming the semiconductor pattern may forming the semiconductor pattern as a single crystal semiconductor using an epitaxial growth process.

In example embodiments, the lower sacrificial pattern may include a material having an etching selectivity with respect to the first mold structure, the second mold structure, the semiconductor pattern, and the channel pattern.

In example embodiments, the lower sacrificial pattern may include one of doped silicon oxide and silicon-germanium.

In example embodiments, the removing the lower sacrificial pattern may include forming a first opening through the first mold structure, the lower sacrificial pattern, and the second mold structure. The removing the lower sacrificial pattern may further include isotropically etching the sacrificial pattern exposed by the first opening may be isotropically etched to form the first gap.

In example embodiments, the forming the conductive pattern may include: conformally forming a conductive layer along inner walls of the first opening and the first gap, and isotropically and partially etching the conductive layer such that the conductive layer remains on the sidewall of the insulation structure.

In example embodiments, after forming the conductive pattern, a second insulation pattern may be further formed to fill the first gap.

In example embodiments, each of the first and second mold structures may include a first insulation layer and a first sacrificial layer alternately and repeatedly stacked, and the first sacrificial layer may have an etching selectivity with respect to the first insulation layer.

In example embodiments, the forming the first gate and the second gates may include forming a second gap and third gaps by removing the first sacrificial layers in the first and second mold structures, forming the first gate in the second gap, and forming the second gates in the third gaps, respectively. The second gap may be in the first mold structure. The third gaps may be in the second mold structure.

According to example embodiments, there is provided a method of manufacturing a semiconductor device. The method may include forming a structure on a substrate. The structure may include a lower sacrificial pattern and a mold structure sequentially stacked, and may define a channel hole therethrough exposing the substrate. The method may further include sequentially forming a preliminary data storage structure and a channel pattern in the channel hole; removing the lower sacrificial pattern to form a first gap exposing the preliminary data storage structure; forming a data storage structure on a sidewall of the channel pattern and an insulation structure on a bottom of the channel pattern; forming a conductive pattern on a sidewall of the insulation structure; and forming a plurality of gates. The forming the data storage structure and the insulation structure may include partially etching the preliminary data storage structure through the first gap. The conductive pattern may electrically connect the channel pattern to the substrate. A plurality of gates may be formed. Each of the gates may surround the data storage structure, and may extend in a second direction substantially parallel to a top surface of the substrate.

In example embodiments, a bottom of the channel pattern may be below an upper surface of the lower sacrificial pattern.

In example embodiments, the lower sacrificial pattern directly may contact the substrate.

In example embodiments, the lower sacrificial pattern may include a material having an etching selectivity with respect to the mold structure, the channel pattern and the substrate.

In example embodiments, when the lower sacrificial pattern is removed, a first opening may be formed through the mold structure and the lower sacrificial pattern. The sacrificial pattern exposed by the first opening may be isotropically etched to form a first gap.

In example embodiments, when the conductive pattern is formed, a conductive layer may be conformally formed along inner walls of the first opening and the first gap. The conductive layer may be isotropically and partially etched such that the conductive layer remains on the sidewall of the insulation structure.

In example embodiments, the partially etching the preliminary data storage structure may be performed using an isotropic etching process.

According to example embodiments, a semiconductor device includes a substrate; a channel pattern on the substrate, the channel pattern extending in a first direction that is vertical to a top surface of the substrate; a conductive pattern between the substrate and an edge part of a bottom surface of the channel pattern, the conductive pattern being electrically connected to the channel pattern through the edge part of the bottom surface of the channel pattern; a data storage structure surrounding the channel pattern; and a plurality of gates surrounding the data storage structure. The plurality of gates are spaced apart from each other in the first direction above the substrate.

In example embodiments, an insulation structure may be between the substrate and a center part of the bottom surface of the channel pattern. The conductive pattern may surround the insulation structure.

In example embodiments, the insulating structure may include a first pattern, a second pattern, and a third pattern sequentially stacked on top of each other and surrounded by the conductive pattern. A width of the second pattern may be different than a width of the first and third patterns.

In example embodiments, the data storage structure may include a tunnel insulating pattern, a charge storage pattern, and a blocking pattern. The first to third patterns may include the same materials as the blocking pattern, the charge storage pattern, and the tunnel insulating pattern, respectively.

In example embodiments, the semiconductor device may include a semiconductor pattern on the substrate. The conductive pattern may be on top of the semiconductor pattern, and the conductive pattern may electrically connect the channel pattern to the semiconductor pattern.

According to example embodiments, the semiconductor pattern and the channel pattern may be spaced apart from each other in the first direction, and may electrically connected to each other by the connection structure. Thus, an open failure between the semiconductor pattern and the channel pattern may decrease.

DESCRIPTION OF EXAMPLE EMBODIMENTS

FIGS. 1, 2A, 2B and 3are cross-sectional views, a perspective view and a plan view illustrating a vertical type semiconductor device in accordance with example embodiments. Each ofFIGS. 4, 5 and 6is a cross-sectional view illustrating a vertical type semiconductor device in accordance with example embodiments.

Particularly,FIG. 1is a cross-sectional view taken along a line I-I′ inFIG. 3.FIG. 2Ais an enlarged cross-sectional view of a portion “A” inFIG. 1, andFIG. 2Bis a partial cutaway perspective view a portion “B” inFIG. 2A.FIG. 3illustrates a layout of channel structures. Each ofFIGS. 4 to 6illustrates an enlarged cross-sectional view of a portion “A” inFIG. 1.

In all figures in this specification, a direction substantially perpendicular to a top surface of a substrate is referred to as a first direction, and two directions substantially parallel to the top surface of the substrate and substantially perpendicular to each other are referred to as a second direction and a third direction, respectively. Additionally, a direction indicated by an arrow in the figures and a reverse direction thereto are considered as the same direction.

Referring toFIGS. 1, 2A, 2B and 3, insulating interlayers and gates may be alternately and repeatedly formed on a substrate100. A channel pattern146amay extend in the first direction. A semiconductor pattern130may be formed on the substrate100, and may be formed under the channel pattern146a. A connection structure171may be formed between the semiconductor pattern130and the channel pattern146a, and may electrically connect the semiconductor pattern130with the channel pattern146a. The connection structure171may include a conductive pattern170acontacting a bottom edge of the channel pattern146aand contacting an upper surface of the semiconductor pattern130.

The substrate100may include a semiconductor material, e.g., silicon, germanium, etc. or a semiconductor on insulator (e.g., silicon on silicon dioxide).

The semiconductor pattern130may have a pillar shape. In example embodiments, the semiconductor pattern130may include single crystalline material, e.g., single crystalline silicon. Alternatively, the semiconductor pattern130may include a polycrystalline material such as polysilicon. The semiconductor pattern130may be doped with impurities or may be non-doped.

The upper surface of the semiconductor pattern130may have various shapes.

In example embodiments, the upper surface of the semiconductor pattern130may be substantially flat. In this case, the upper surface of the semiconductor pattern130may have substantially the same height, regardless of positions thereof, as shown inFIGS. 2A and 2B.

In example embodiments, the upper surface of the semiconductor pattern130may include a protruding portion. For example, a central portion of the semiconductor pattern130may protrude from an edge portion of the semiconductor pattern130, as shown inFIG. 4.

In example embodiments, the upper surface of the semiconductor pattern130may have different heights according to positions thereof. For example, the upper surface of the semiconductor pattern130may have a slope, as shown inFIG. 5.

In example embodiments, the channel pattern146amay have a cup shape, and a bottom of the channel pattern146amay contact the connection pattern171. A filling insulation pattern148amay be formed on the channel pattern146ato fill an inner space formed by the channel pattern146ahaving the cup shape. In example embodiments, the channel pattern146amay include polysilicon, and the filling insulation pattern148amay include silicon oxide, but example embodiments are not limited thereto. The channel pattern146amay be doped with impurities.

In example embodiments, the channel pattern146amay have a pillar shape. In this case, the filling insulation pattern148amay not be formed on the channel pattern146a.

The bottom of the channel pattern146amay overlap the upper surface of the semiconductor pattern130. A width of the bottom of the channel pattern146amay be less than a width of the upper surface of the semiconductor pattern130.

A data storage structure145may be disposed along an outer sidewall of the channel pattern146a. The data storage structure145may include a tunnel insulation pattern144b, a charge storage pattern142band a first blocking pattern140c. Each of the tunnel insulation pattern144b, the charge storage pattern142band the first blocking pattern140cmay have a hollow cylindrical shape.

In example embodiments, the tunnel insulation pattern144bmay include an oxide, e.g., silicon oxide. The charge storage pattern142bmay include a nitride, e.g., silicon nitride. The first blocking pattern140cmay include an oxide, e.g., silicon oxide.

The data storage structure145may be spaced apart from the upper surface of the semiconductor pattern130. A bottom of the data storage structure145may be higher than the bottom of the channel pattern130.

The connection structure171may be formed between the semiconductor pattern130and the channel pattern146ain the first direction. Thus, the semiconductor pattern130, the connection structure171and the channel pattern146amay be sequentially stacked, and may form a channel structure having a pillar shape. The semiconductor pattern130and the channel pattern146amay be electrically connected to the substrate100.

The connection structure171may include the conductive pattern170aand an insulation structure165. The insulation structure165may contact an inner sidewall of the conductive pattern170a, and may be formed between the channel pattern146aand the semiconductor pattern130.

The conductive pattern170amay have a hollow cylindrical shape, and may contact the bottom edge of the channel pattern146aand the upper surface of the semiconductor pattern130. The insulation structure165may contact a central bottom of the channel pattern146aand the upper surface of the semiconductor pattern130.

In example embodiments, the conductive pattern170amay include doped polysilicon. The channel pattern146aand the semiconductor pattern130may be electrically connected to each other by the conductive pattern170a. The insulation structure165may be formed on the semiconductor pattern130, and may support the bottom of the channel pattern146a.

According to the shape of the upper surface of the semiconductor pattern130, the shape of a bottom of each of the insulation structure165and the channel pattern146amay change.

In example embodiments, the bottoms of the insulation structure165and the channel pattern146amay be substantially flat, as shown inFIGS. 2A and 2B.

In example embodiments, central bottoms of the insulation structure165and the channel pattern146amay protrude from bottom edges of the insulation structure165and the channel pattern146a, respectively, as shown inFIG. 3.

In example embodiments, the bottoms of the insulation structure165and the channel pattern146amay have a slope, as shown inFIG. 4.

The insulation structure165may include materials that are the same as or substantially the same as materials included in the data storage structure145. In example embodiments, the insulation structure165may include a first pattern160a, a second pattern162and a third pattern164sequentially stacked. The first pattern160amay include a material the same as or substantially the same as a material of the first blocking pattern140c, the second pattern162may include a material the same as or substantially the same as a material of the charge storage pattern142b, and the third pattern164may include a material the same as or substantially the same as a material of the tunnel insulation pattern144b.

A sidewall of the insulation structure165may be uneven along the first direction, and may have concave and convex portions. In example embodiments, at least one of the first, second and third patterns160a,162and164included in the insulation structure165may laterally protrude from the others. For example, the second pattern162may laterally protrude from the first and third patterns160aand164. For example, at least one of the first and third patterns160aand164may laterally protrude from the second pattern162.

The first, second and third patterns160a,162and164may not laterally protrude from the bottom edge of the channel pattern146a. That is, a width of each of the first, second and third patterns160a,162and164may be less than the width of the bottom of the channel pattern146a.

The conductive pattern170amay cover a sidewall of the insulation structure165. The conductive pattern170amay fill a space defined by the sidewall of the insulation structure165, the upper surface of the semiconductor pattern130and the bottom of the channel pattern146a.

In example embodiments, the conductive pattern170amay contact the bottom edge of the channel pattern146a, and may have a hollow cylindrical shape. In this case, a width the connection structure171may be less than the width of the upper surface of the semiconductor pattern130.

In example embodiments, the conductive pattern170amay contact the bottom edge of the channel pattern146aand a lower sidewall of the channel pattern146a.

In example embodiments, the conductive pattern170amay contact the bottom edge of the channel pattern146a, a lower sidewall of the channel pattern146a, the bottom of the data storage structure145and the upper surface of the semiconductor pattern130, as shown inFIG. 6.

The gates may include a first gate176aand a plurality of second gates176b.

The first gate176amay serve as a ground selection line (GSL). The semiconductor pattern130may be formed through the first gate176a.

In example embodiments, one first gate176amay surround the semiconductor pattern130. In example embodiments, a plurality of first gates176amay be formed to be spaced apart from each other in the first direction, and each of the first gates176amay surround the semiconductor pattern130.

Each of the second gates176bmay serve as a word line or a string selection line (SSL). The channel pattern146amay be formed through the second gates176b.

In example embodiments, one SSL or a plurality of SSLs may be formed on the channel pattern146a. A plurality of word lines may be formed between the GSL and the SSL.

A first distance in the first direction between the first and second gates176aand176bmay be greater than a second distance in the first direction between the second gates176b.

In example embodiments, the first and second gates176aand176bmay include a metal having a low resistance, e.g., tungsten, titanium, tantalum, platinum, etc., and/or a metal nitride, e.g., titanium nitride, tantalum nitride, etc. The first and second gates176aand176bmay include the same as or substantially the same material.

The first and second gates176aand176bmay be arranged in the third direction, and may extend in the second direction surrounding a plurality of channel structures.

In example embodiments, a second blocking layer174may be formed between the first gate176aand the semiconductor pattern130and between the second gate176band the data storage structure145. The second blocking layer174may include a metal oxide having a dielectric constant higher than a dielectric constant of the first blocking pattern140c. The second blocking layer174may cover surfaces of the first and second gates176aand176b, and may extend in the first direction.

The insulating interlayer may include a plurality of first insulation patterns110aand a second insulation pattern172a.

In example embodiments, each of the first insulation patterns110amay be formed between the second gates176b. A stacked structure including the first insulation pattern110a, the second insulation pattern172aand the first insulation pattern110amay be formed between the first and second gates176aand176b. After forming the first insulation patterns110a, the second insulation pattern172amay be formed by an additional deposition process. However, the second insulation pattern172amay include a material the same as or substantially the same as a material of each of the first insulation patterns110a. The first and second insulation patterns110aand172amay include, e.g., silicon oxide. The first and second insulation patterns110aand172amay be formed by a plasma enhanced CVD process, a high density plasma CVD process, etc.

The first insulation pattern110amay be formed between the first gate176aand the substrate100.

The first and second gates176aand176bextending in the second direction may be divided by a first opening extending in the second direction. A third insulation pattern178may be formed a sidewall of the first opening. The third insulation pattern178may include, e.g., silicon oxide.

A second opening may be defined by the third insulation pattern178, and a conductive pattern180may be formed to fill the second opening. The conductive pattern180may include a metal having a low resistance, e.g., tungsten, titanium, tantalum, platinum, etc., and/or a metal nitride, e.g., titanium nitride, tantalum nitride, etc.

The conductive pattern180may serve as a common source line (CSL). An impurity region may be formed at an upper portion of the substrate100contacting the conductive pattern180.

A pad150may be formed on the filling insulation pattern148a, the channel pattern146aand the data storage structure145. A bit line contact plug (not shown) may be formed on the pad150, and a bit line (not shown) may be formed on the bit line contact plug.

In the vertical type semiconductor device, the semiconductor pattern130and the channel pattern146amay be electrically connected to each other by the connection structure171. Thus, even though the number of the second gates stacked on the channel pattern146amay increase, the possibility of not connection between the semiconductor pattern130and the channel pattern146amay decrease.

FIGS. 7 to 21are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with example embodiments.

Particularly,FIGS. 12 to 16are enlarged cross-sectional views of a portion of the semiconductor device.

Referring toFIG. 7, a first mold structure111, a lower sacrificial layer112and a second mold structure113may be sequentially formed on a substrate100.

The substrate100may include a semiconductor material, for example, silicon and/or germanium, or a semiconductor on insulator.

In example embodiments, a first insulation layer110may be formed on the substrate100, and a first sacrificial layer120and a first insulation layer110may be alternately formed on the first insulation layer110to form the first mold structure111. In example embodiments, a plurality of first sacrificial layers120and/or a plurality of first insulation layers110may be alternately formed. In example embodiments, an uppermost layer of the first mold structure111may be the first insulation layer110. The number of the first sacrificial layers120in the first direction may be same as the number of first gates in the first direction subsequently formed. When a cell string includes one GSL, one first sacrificial layer120may be formed on the first insulation layer110, as shown inFIG. 7.

In example embodiments, the first insulation layer110and the first sacrificial layer120may be formed by a chemical vapor deposition (CVD) process, a plasma enhanced chemical vapor deposition (PE-CVD) process, an atomic layer deposition (ALD) process, etc. One of the first insulation layers110directly contacting the substrate100may be formed by a thermal oxidation process. In example embodiments, the first insulation layer110directly contacting the substrate100may have a thickness different from each of thicknesses of other first insulation layers110.

In example embodiments, the first insulation layer110may be formed of silicon oxide. For example, the first insulation layer110may include plasma enhanced tetra-ethyl orthosilicate (PE-TEOS), high density plasma (HDP) oxide, or plasma enhanced oxide (PEOX). In example embodiments, the first sacrificial layer120may have an etching selectivity with respect to the first insulation layer110. The first sacrificial layers120may be formed of, e.g., silicon nitride.

The lower sacrificial layer112may be formed on the first mold structure111. The lower sacrificial layer112may include a material having an etching selectivity with respect to the first and second mold structures111and113, a channel pattern146a(refer toFIG. 10) and a semiconductor pattern130(refer toFIG. 8) subsequently formed. That is, the lower sacrificial layer112may include a material having an etching selectivity with respect to oxide and nitride included in the first and second mold structures111and113. Also, the lower sacrificial layer112may include a material having an etching selectivity with respect to silicon included in the channel pattern146aand the semiconductor pattern130.

In example embodiments, the lower sacrificial layer112may be formed of silicon oxide having an etch rate higher than an etch rate of the first insulation layer110. That is, the lower sacrificial layer112may be formed of silicon oxide having a high etch rate with respect to an etchant including hydrofluoric acid in a wet etch process.

In example embodiments, the lower sacrificial layer112may be formed of a material different from a material of the first insulation layer110. Alternatively, the lower sacrificial layer112may be formed of a material the same as or substantially the same as a material of the first insulation layer110, however, the material may be further doped with impurities. Alternatively, the lower sacrificial layer112may be formed of a material doped with impurities that is the same as or substantially the same as the material of the first insulation layer110, however, a doping concentration of the lower sacrificial layer112may be higher than a doping concentration of the first insulation layer110. Alternatively, the lower sacrificial layer112may be formed using a material the same as or substantially the same as the material of the first insulation layer110, however, may be deposited at a relatively low temperature so as to have porous therein, and thus may have an etch rate higher than that of the first insulation layer110.

In example embodiments, when the semiconductor pattern130includes silicon, the lower sacrificial layer112may include, e.g., silicon germanium.

In example embodiments, the lower sacrificial layer112may be formed to have a thickness greater than a sum of thicknesses of a blocking layer140(refer toFIG. 9), a charge storage layer142(refer toFIG. 9), a tunnel insulation layer144(refer toFIG. 9) and a channel layer146(refer toFIG. 9) subsequently formed.

A plurality of first insulation layers110and a plurality of first sacrificial layers120may be alternately and repeatedly formed on the lower sacrificial layer112, so that the second mold structure113may be formed. The number of the first sacrificial layers120in the second mold structure113may be the same as or substantially the same as the number of second gates subsequently formed. That is, the number of the first sacrificial layers120in the second mold structure113may be the same as or substantially the same as a sum of the numbers of word lines and string selection lines (SSL) in a cell string.

Referring toFIG. 8, an upper insulation layer124may be formed on the second mold structure113. In example embodiments, the upper insulation layer124may be formed by a CVD process, a PECVD process, an ALD process, etc. In example embodiments, the upper insulation layer124may be formed of silicon oxide. Alternatively, the upper insulation layer124may not be formed.

A plurality of holes126may be formed through the upper insulation layer124, the first insulation layer110, the first sacrificial layer120and the lower sacrificial layer112to expose a top surface of the substrate100. The semiconductor pattern130may be formed to fill a lower portion of each of the holes126.

In example embodiments, a hard mask (not shown) may be formed on the upper insulation layer124, and the upper insulation layer124, the first insulation layer110, the first sacrificial layer120and the lower sacrificial layer112may be anisotropically etched using the hard mask as an etching mask to form the holes126.

In example embodiments, the holes126may be arranged in the second and the third directions to define a hole array.

The semiconductor pattern130may be formed by a selective epitaxial growth (SEG) process using the exposed top surface of the substrate100as a seed. Thus, the semiconductor pattern130may include single crystalline silicon or single crystalline germanium according to the material of the substrate100. Alternatively, an amorphous silicon layer may be formed to partially fill the holes126, and a laser epitaxial growth (LEG) process or a solid phase epitaxy (SPE) process may be performed on the amorphous silicon layer to form the semiconductor pattern130.

In example embodiments, an upper surface of the semiconductor pattern130may be formed between an upper surface and a lower surface of the lower sacrificial layer112. The semiconductor pattern130may have a pillar shape. The upper surface of the semiconductor pattern130may have various shapes according to the SEG process.

In example embodiments, the upper surface of the semiconductor pattern130may be substantially flat.

In example embodiments, the upper surface of the semiconductor pattern130may have a protruding portion. For example, a center portion of the semiconductor pattern130may protrude from an edge portion of the semiconductor pattern130. In this case, the vertical semiconductor device ofFIG. 3may be manufactured by subsequent processes.

In example embodiments, the upper surface of the semiconductor pattern130may have a slope. In this case, the vertical semiconductor device ofFIG. 4may be manufactured by subsequent processes.

Referring toFIG. 9, the blocking layer140, the charge storage layer142, the tunnel insulation layer144and the channel layer146may be sequentially and conformally formed on an inner sidewall of the holes126, the upper surface of the semiconductor pattern130and the upper insulation layer124. A filling insulation layer148may be formed on the channel layer146to sufficiently fill the holes126.

In example embodiments, the blocking layer140may be formed of an oxide, e.g., silicon oxide, the charge storage layer142may be formed of a nitride, e.g., silicon nitride, and the tunnel insulation layer144may be formed of an oxide, e.g., silicon oxide. A structure including the blocking layer140, the charge storage layer142and the tunnel insulation layer144may serve as a charge storage layer.

In example embodiments, the channel layer146may be formed of, e.g., doped polysilicon or undoped polysilicon. A bottom of the channel layer146may be lower than the upper surface of the lower sacrificial layer112.

In example embodiments, the filling insulation layer148may be formed of, e.g., silicon oxide.

Referring toFIG. 10, the filling insulation layer148, the channel layer146, the tunnel insulation layer144, the charge storage layer142and the blocking layer140on the upper insulation layer124may be removed by an etch back process or a chemical mechanical polishing (CMP) process. The filling insulation layer148, the channel layer146, the tunnel insulation layer144, the charge storage layer142and the blocking layer140in an upper portion of the hole126may be partially removed to form a recess. A pad layer may be formed to fill the recess, and may be planarized to form a pad150. In example embodiments, the pad150may be formed of, e.g., doped polysilicon or undoped polysilicon.

Thus, a first preliminary blocking pattern140a, a preliminary charge storage pattern142a, a preliminary tunnel insulation pattern144a, the channel pattern146aand a filling insulation pattern148amay be formed in each of the holes126. The first preliminary blocking pattern140amay contact the upper surface of the semiconductor pattern130.

A first opening152may be formed through the upper insulation layer124, the second mold structure113, the lower sacrificial layer112and the first mold structure111to expose a top surface of the substrate100.

In example embodiments, a hard mask (not shown) may be formed on the upper insulation layer124and the pad150, and the upper insulation layer124, the second mold structure113, the lower sacrificial layer112and the first mold structure111may be anisotropically etched using the hard mask as an etching mask to form the first opening152.

In example embodiments, the first opening152may extend in the second direction, and a plurality of first openings152may be formed to be arranged in the third direction. Thus, a first sacrificial pattern120a, a first insulation pattern110aand a lower sacrificial pattern112amay be formed from the first sacrificial layer120, the first insulation layer110and the lower sacrificial layer112, respectively.

Referring toFIG. 11, the lower sacrificial pattern112aexposed by a sidewall of the first opening152may be selectively etched to form a first gap154.

The lower sacrificial pattern112amay be removed by an isotropic etching process, e.g., a wet etching, an isotropic dry etching, etc. When the lower sacrificial pattern112aincludes silicon oxide, the first gap154may be formed by the wet etching process using an etchant including hydrofluoric acid. A portion of the first preliminary blocking pattern140amay be exposed by the first gap154.

Hereinafter, it will be described with reference toFIGS. 12 to 16, which are enlarged views of the portion “A” ofFIG. 1.

Referring toFIG. 12, the first preliminary blocking pattern140aexposed by the first gap154may be selectively etched by an isotropic etching process, e.g., a wet etching, an isotropic dry etching, etc. In example embodiments, the first preliminary blocking pattern140aexposed by the first gap154may be selectively etched by the wet etching process using an etchant including hydrofluoric acid.

The first preliminary blocking pattern140amay be separated into a second preliminary blocking pattern140bextending in the first direction and a first preliminary pattern160on the semiconductor pattern130by the etching process. A portion of the preliminary charge storage pattern142amay be exposed by the first gap154.

During the etching process, a portion of the first insulation pattern110aexposed by the first gap154and a sidewall of the first opening152may be etched, so that a width in the first direction of the first gap154and a width in the third direction of a portion of the first opening152may slightly increase.

Referring toFIG. 13, the preliminary charge storage pattern142aexposed by the first gap154may be selectively etched by an isotropic etching process, e.g., a wet etching, an isotropic dry etching, etc. In example embodiments, the first preliminary charge storage pattern142aexposed by the first gap154may be selectively etched by the wet etching process using an etchant including sulfuric acid or phosphoric acid.

The first preliminary charge storage pattern142amay be separated into a charge storage pattern142bextending in the first direction and a second pattern162on the first preliminary pattern160by the etching process. A portion of the preliminary tunnel insulation pattern144amay be exposed by the first gap154. A width of the second pattern162may be smaller than a width of a bottom of the channel pattern146a.

During the etching process, a portion of the first sacrificial pattern120aexposed by the first opening152may be etched, so that a width in the third direction of a portion of the first opening152may slightly increase.

Referring toFIG. 14, a preliminary tunnel insulation pattern144aexposed by the first gap154may be selectively etched by an isotropic etching process, e.g., a wet etching, an isotropic dry etching, etc. In example embodiments, the first preliminary tunnel insulation pattern144aexposed by the first gap154may be selectively etched by the wet etching process using an etchant including hydrofluoric acid.

The preliminary tunnel insulation pattern144amay be separated into a tunnel insulation pattern144bextending in the first direction and a third pattern164on the second pattern162by the etching process. A width of the third pattern164may be smaller than a width of the bottom of the channel pattern146a, so that the bottom of the channel pattern146amay cover an upper surface of the third pattern164.

During the etching process, the second preliminary blocking pattern140band the first preliminary pattern160may be partially etched to form a first blocking pattern140cand a first pattern160a, respectively. A width of the first pattern160amay be smaller than the width of the bottom of the channel pattern146a.

Thus, an insulation structure165including the first, second and third patterns160a,162and164sequentially stacked may be formed on the semiconductor pattern130. The insulation structure165may be formed under the channel pattern146ato support the channel pattern146a, and may have a pillar shape.

In example embodiments, a sidewall of the insulation structure165may be uneven along the first direction, and may have concave and convex portions. That is, at least one of the first, second and third patterns160a,162and164may protrude from the others in a lateral direction. For example, the second pattern162may protrude from the first and third patterns160a,162and164in the lateral direction.

In example embodiments, a sidewall of the insulation structure165may not be uneven. That is, the first, second and third patterns160a,162and164may not protrude from the others in a lateral direction.

During the etching process, the first insulation pattern110aexposed by the first gap154and a sidewall of the first insulation pattern110aexposed by the first opening152may be partially etched, so that a width in the first direction of the first gap154and a width in the third direction of the first opening152may slightly increase.

Referring toFIG. 15, a conductive layer170may be conformally formed on a sidewall and a bottom of the first opening152, an inner wall of the gap154, the upper insulation layer124(refer toFIG. 11) and an upper surface of the pad150(refer toFIG. 11). The conductive layer170may include doped polysilicon or undoped polysilicon. The conductive layer170may be formed by an ALD process or a CVD process.

The conductive layer170may cover a sidewall of the insulation structure165. The conductive layer170may sufficiently fill a groove defined by a bottom of the channel pattern146a, a sidewall of the insulation structure165and the upper surface of the semiconductor pattern130. The groove may have a bended shape.

In example embodiments, the conductive layer170on the sidewall and the bottom of the first opening152may have a first thickness. However, the conductive layer170filling the groove may have a second thickness greater than the first thickness.

Referring toFIG. 16, the conductive layer170on the sidewall and the bottom of the first opening152, the inner wall of the first gap154, the upper insulation layer124(refer toFIG. 11) and the pad150(refer toFIG. 11) may be isotropically etched by e.g., a wet etching process or an isotropic dry etching process, and a portion of the conductive layer170in the groove may remain to form a conductive pattern170a. In example embodiments, the conductive layer170may be removed by the amount of the first thickness through the isotropic etching process.

The conductive pattern170amay cover a sidewall of the insulation structure165. The conductive pattern170amay contact a bottom edge of the channel pattern146aand the upper surface of the semiconductor pattern130, and may have a hollow cylindrical shape. Thus, the semiconductor pattern130and the channel pattern146amay be electrically connected with each other by the conductive pattern170a.

That is, a connection structure171including the insulation structure165and the conductive pattern170amay be formed between the semiconductor pattern130and the channel pattern146a. The semiconductor pattern130and the channel pattern146amay be spaced apart from each other in the first direction.

In example embodiments, the conductive pattern170amay be conformally formed in the groove, on the sidewall of the channel pattern146a, and on the first gap154by the isotropic etching process, as shown inFIG. 6.

Referring toFIG. 17, a second insulation layer172may be formed on the sidewall and the bottom of the first opening152, the upper insulation layer124to fill the first gap154. The second insulation layer172may include silicon oxide. In example embodiments, the second insulation layer172may be formed of a material the same as or substantially the same as a material of the first insulation pattern110a.

The second insulation layer172may be formed by an ALD process or a CVD process.

Referring toFIG. 18, the second insulation layer172on the sidewall and the bottom of the first opening152, the upper insulation layer124and the pad150may be isotropically etched by e.g., a wet etching process or an isotropic dry etching process. Thus, a second insulation pattern172amay be formed in the first gap154.

Referring toFIG. 19, the first sacrificial pattern120amay be removed to form a second gap156. Sidewalls of the first blocking pattern140cand the semiconductor pattern130may be partially exposed by the second gap156. In example embodiments, the first sacrificial pattern120amay be isotropically etched by, e.g., a wet etching process or an isotropic dry etching process. For example, the first sacrificial pattern120aexposed by the first opening152may be removed by the wet etching process using an etchant including sulfuric acid or phosphoric acid.

Referring toFIG. 20, a second blocking layer174may be formed on the sidewall of the first blocking pattern140c, the sidewall of the semiconductor pattern130, an inner wall of the second gap156, the first insulation pattern110a, the upper insulation layer124, the pad150and the substrate100. A first gate176aand second gates176bmay be formed on the second blocking layer174to fill the second gaps156, respectively.

In order to form the first and second gates176aand176b, a gate electrode layer may be formed on the second blocking layer174to fill the second gap156. The gate electrode layer may be formed of a metal and/or a metal nitride. In example embodiments, the gate electrode layer may be formed of a metal having a low electric resistance, e.g., tungsten, titanium, tantalum, platinum, etc., and a metal nitride, e.g., titanium nitride, tantalum nitride, etc. The gate electrode layer may be partially etched to form the first and second gates176aand176bin the second gaps156, respectively. In example embodiments, the first electrode layer may be partially etched by a wet etching process.

The first gate176amay be formed on the sidewall of the semiconductor pattern130, and may serve as a GSL. The second gates176bmay be formed on the sidewall of the channel pattern146a, and may serve as word lines or SSLs.

In example embodiments, each of the first and second gates176aand176bmay partially fill the second gap156. Thus, the sidewall of the first opening152may be uneven along the first direction due to the first and second gates176aand176b. In example embodiments, each of the first and second gates176aand176bmay sufficiently fill the second gap156.

Referring toFIG. 21, a third insulation layer may be formed on the second blocking layer174along the bottom and the sidewall of the first opening152. The third insulation layer on the bottom of the first opening152may be anisotropically etched to form a third insulation pattern178exposing the top surface of the substrate100. Also, the first opening152may be transformed to a second opening (not shown) by the third insulation pattern178. Impurities may be doped into the substrate100exposed by the second opening, so that an impurity region may be formed. A conductive pattern180may be formed to fill the second opening. The conductive pattern180may serve as a CSL.

Particularly, a conductive layer may be formed to fill the second opening, and may be planarized until a top surface of the second blocking layer174may be exposed to form a conductive pattern179. The conductive layer may be formed of a metal and/or a metal nitride. In example embodiments, the conductive layer may include a metal having a low resistance, e.g., tungsten, titanium, tantalum, platinum, etc, and/or a metal nitride, e.g., titanium nitride, tantalum nitride, etc.

A bit line contact (not shown) and a bit line (not shown) may be formed on the pad150, and may be electrically connected to the pad150. Thus, the vertical semiconductor device may be manufactured.

FIG. 22is a vertical cross-sectional view illustrating a vertical memory device in accordance with example embodiments, andFIG. 23is an enlarged cross-sectional view of a portion “C” of the vertical memory device semiconductor inFIG. 22. The vertical memory device may be the same as or substantially the same as the vertical memory device ofFIGS. 1, 2A, 2B and 3, except for the semiconductor pattern.

Referring toFIGS. 22 and 23, a channel pattern146amay be formed to be spaced apart from a substrate100in the first direction. A connection structure211may be formed between the substrate100and a channel pattern146a, and may be electrically connected to the substrate100and the channel pattern146a. A plurality of gates232may surround the channel pattern146a, and may extend in the second direction. A data storage structure145including a tunnel insulation pattern144b, a charge storage pattern142band a first blocking pattern140cmay be formed between the channel pattern146aand the gate232. The tunnel insulation pattern144b, the charge storage pattern142band the first blocking pattern140cmay be sequentially stacked on the channel pattern146a.

The channel pattern146amay be the same as or substantially the same as the channel pattern illustrated with reference toFIGS. 1, 2A, 2B and 3. However, no semiconductor pattern may be formed under the channel pattern146a, so that a bottom of the channel pattern146amay be substantially flat. A filling insulation pattern148amay be formed on the channel pattern146ato fill an inner space formed by the channel pattern146a.

The data storage structure145may cover the sidewall of the channel pattern146a. The data storage structure145may be the same as or substantially the same as the data storage structure illustrated with reference toFIGS. 1, 2A, 2B and 3.

The connection structure211may be formed between the substrate100and the channel pattern146ain the first direction.

The connection structure211may include a conductive pattern210and an insulation structure205. The conductive pattern210may have a hollow cylindrical shape, and may contact a bottom edge of the channel pattern146aand the substrate100. The insulation structure205may contact an inner sidewall of the conductive pattern210, a central bottom of the channel pattern146aand the substrate100. This, the connection structure211may have a pillar shape.

The substrate100and the channel pattern146amay be electrically connected to each other via the conductive pattern210.

The insulation structure205may include materials the same as or substantially the same as materials included in the data storage structure145. In example embodiments, the insulation structure205may include a first pattern200aincluding the same material as that of the first blocking pattern140c, a second pattern202including the same material as that of the charge storage pattern142b, and a third pattern204including the same material as that of the tunnel insulation pattern144b, and the first, second and third patterns200a,202and204may be sequentially stacked.

A sidewall of the insulation structure205may be uneven along the first direction, and may have concave and convex portions. That is, at least one of the first, second and third patterns200a,202and204may protrude from the others in a lateral direction. For example, the first and third patterns200aand204may protrude from the second pattern202in the lateral direction. Alternatively, the second pattern202may protrude from the first and third patterns200aand204in the lateral direction, as shown inFIG. 1, where the second pattern162protrudes from the first and third patterns160aand164.

The first to third channel patterns200a,202and204may not protrude from a bottom edge of the channel pattern146ain the lateral direction. That is, a width of each of the first, second and third pattern200a,202and204may be smaller than a width of the bottom of the channel pattern146a.

The conductive pattern210may fill a recess defined by the sidewall of the insulation structure205, the top surface of the substrate100and the bottom of the channel pattern146a.

Each of the gates232may serve as a GSL, a word line, or a SSL. In example embodiments, at least one gate232at a lowermost level may serve as the GSL, and at least one gate232at an uppermost level may serve as the SSL. Ones of the gates232between the GSL and SSL may serve as the word lines.

A second blocking layer230covering sidewalls and a bottom of the gate232may be further formed.

A plurality of insulation patterns110aand220may be formed between the substrate100and the gate232at the lowermost level and between neighboring ones of the gates232.

In example embodiments, a plurality of first insulation patterns110amay be formed between the gates232, respectively. A stacked structure including a second insulation pattern220and a first insulation pattern110amay be formed between the substrate100and the gate232at the lowermost level. After forming the first insulation patterns110a, the second insulation pattern220may be formed by a deposition process. However, the second insulation pattern220may include a material the same as or substantially the same as a material of the first insulation patterns110a. The first and second insulation patterns110aand220may include, e.g., silicon oxide.

A first distance in the first direction between the substrate100and the gate232at the lowermost level may be greater than a second distance in the first direction between the gates232.

A third insulation pattern240and a conductive pattern242may be further formed, and may be the same as or substantially the same as or similar to the third insulation pattern and the conductive pattern, respectively, illustrated with reference toFIGS. 1, 2A, 2B and 3.

A bit line contact (not shown) and a bit line (not shown) may be further formed on the pad150, and the bit line contact and the bit line may be electrically connected to the pad150.

FIGS. 24 to 31are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with example embodiments. Particularly,FIGS. 28 to 30are enlarged cross-sectional views.

Referring toFIG. 24, a lower sacrificial layer112may be formed on a substrate100. A first insulation layer110and a first sacrificial layer120may be alternately and repeatedly formed on the lower sacrificial layer112, and so that a mold structure may be formed.

The lower sacrificial layer112may be formed directly on the substrate100.

The lower sacrificial layer112may include a material having an etching selectivity with respect to the mold structure and a channel pattern subsequently formed. That is, the lower sacrificial layer112may include a material having an etching selectivity with respect to oxide and nitride in the mold structure and silicon included in the channel pattern subsequently formed.

In example embodiments, the lower sacrificial layer112may be formed of silicon oxide having an etch rate higher than an etch rate of the first insulation layer110. In example embodiments, when the substrate100includes single crystalline silicon, the lower sacrificial layer112may be formed of silicon germanium. Alternatively, the lower sacrificial layer112may be formed of a material the same as or substantially the same as or similar to a material of the lower sacrificial layer illustrated with reference toFIG. 7.

In example embodiments, the lower sacrificial layer112may be formed to have a thickness greater than a sum of thicknesses of a blocking layer, a charge storage layer, a tunnel insulation layer and a channel layer subsequently formed.

The number of the first sacrificial layers120in the mold structure may be the same as or substantially the same as the number of gates in a cell string.

In example embodiments, the first insulation layer110may be formed of, e.g., silicon oxide. In example embodiments, the first sacrificial layer120may be formed of a material having an etching selectivity with respect to the first insulation layer110. For example, the first sacrificial layer120may be formed of, e.g., silicon nitride.

Referring toFIG. 25, an upper insulation layer124may be formed on the mold structure. A plurality of holes126may be formed through the upper insulation layer124, the first insulation layer110, the first sacrificial layer120and the lower sacrificial layer112to expose a top surface of the substrate100. During an etching process for forming the holes126, preferably, the top surface of the substrate100may not be over-etched. A blocking layer140, a charge storage layer142, a tunnel insulation layer144and a channel layer146may be sequentially formed on inner walls of the holes126, the top surface of the substrate100and an upper surface of the upper insulation layer124. A filling insulation layer148may be formed on the channel layer146to fill each of the holes126.

Processes may be the same as or substantially the same as or similar to the processes illustrated with reference toFIGS. 8 and 9may be performed. However, after forming the holes126, no semiconductor pattern may be formed in each of the holes126.

Referring toFIG. 26, the filling insulation layer148, the channel layer146, the tunnel insulation layer144, the charge storage layer142and the blocking layer140on the upper insulation layer124may be removed. The filling insulation layer148, the channel layer146, the tunnel insulation layer144, the charge storage layer142and the blocking layer140formed in an upper portion of the holes126may be partially removed to form a recess. A pad layer may be formed to fill the recess, and planarized until the upper surface of the upper insulation may be exposed to form a pad150.

Thus, a first preliminary blocking pattern140a, a preliminary charge storage pattern142a, a preliminary tunnel insulation pattern144a, a channel pattern146aand a filling insulation pattern148amay be formed in each of the holes126. The first preliminary blocking pattern140amay contact the top surface of the substrate100.

A first opening152may be formed through the upper insulation layer124, the mold structure and the lower sacrificial layer112to expose a top surface of the substrate100.

Processes may be the same as or substantially the same as or similar to the processes illustrated with reference toFIG. 10may be performed.

Referring toFIG. 27, the lower sacrificial pattern112aexposed by a sidewall of the first opening152may be selectively removed to form a first gap154a.

The lower sacrificial pattern112amay be removed by an isotropic etching process, e.g., wet etching, isotropic dry etching, etc. When the lower sacrificial pattern112aincludes silicon oxide, the first gap154amay be formed by the wet etching process using an etchant including hydrofluoric acid. Portions of the first preliminary blocking pattern140aand the substrate100may be exposed by the first gap154a.

Hereinafter, it will be described with reference toFIGS. 28 to 30, which are enlarged views of a portion “D” ofFIG. 27.

Referring toFIG. 28, the first preliminary blocking pattern140aexposed by the first gap154amay be selectively etched by an isotropic etching process, e.g., a wet etching, an isotropic dry etching, etc.

When the etching process is performed, the first preliminary blocking pattern140amay be divided into a second preliminary blocking layer140bextending in the first direction and a first preliminary pattern200on the substrate100. The preliminary charge storage pattern142amay be partially exposed by the first gap154a.

Referring toFIG. 29, the preliminary charge storage pattern142aexposed by the first gap154amay be partially etched by anisotropic etching process, e.g., a wet etching, an isotropic dry etching, etc.

Thus, the preliminary charge storage pattern142amay be divided into a charge storage pattern142bextending in the first direction and a second pattern202on the first preliminary pattern200. A width of the second pattern202may be controlled by the etching process. The preliminary tunnel insulation pattern144amay be partially exposed by the first gap154a.

Referring toFIG. 30, the preliminary tunnel insulation pattern144aexposed by the first gap154amay be selectively etched by anisotropic etching process, e.g., a wet etching, an isotropic dry etching, etc.

Thus, the preliminary tunnel insulation pattern144amay be divided into a tunnel insulation pattern144bextending in the first direction and a third pattern204on the second pattern202. The channel pattern146amay be partially exposed by the first gap154a.

During the etching process, the second preliminary blocking pattern140band the first preliminary pattern200may be partially etched to form a first blocking pattern140cand a first pattern200a, respectively.

Thus, an insulation structure205including the first, second and third patterns200a,202and204sequentially stacked may be formed on the substrate100. The insulation structure205may be formed under the channel pattern146ato support the channel pattern146a, and may have a pillar shape.

In example embodiments, a sidewall of the insulation structure205may be uneven along the first direction, and may have concave and convex portions. That is, at least one of the first, second and third patterns200a,202and204may protrude from the others in a lateral direction.

Referring toFIG. 31, a conductive layer may be formed on a sidewall and a bottom of the first opening152, an inner wall of the first gap154a, the upper insulation layer124(refer toFIG. 27) and a top surface of the pad150(refer toFIG. 27).

The conductive layer on the sidewall and the bottom of the first opening152, the inner wall of the first gap154a, the upper insulation layer124(refer toFIG. 27) and the pad150(refer toFIG. 27) may be isotropically etched by e.g., a wet etching process or an isotropic dry etching process, and the conductive layer in a groove defined by a bottom of the channel pattern146a, a sidewall of the insulation structure205and the top surface of the substrate100may remain to form a conductive pattern210.

Processes may be the same as or substantially the same as or similar to the processes illustrated with reference toFIGS. 15 and 16may be performed.

Then, processes the same as or substantially the same as or similar to the processes illustrated with reference toFIGS. 17 to 21may be performed, so that the semiconductor device shown inFIGS. 22 and 23may be manufactured.

The above semiconductor device may be applied to various types of systems, e.g., computing system.

FIG. 32is a block diagram illustrating a system in accordance with example embodiments.

Referring toFIG. 32, a data processing system400may include a central processing unit (CPU)420connected to a system bus405, a random access memory (RAM)430, a user interface440, a modem450such as a baseband chipset, and a memory system410. The memory system410may include a memory device412and a memory controller411. The memory device412may include one of the above semiconductor devices in accordance with example embodiments. The memory device412may stably store data processed by the CPU420and/or inputting data. The memory controller411may control the memory device412. The memory device412and the memory controller411may be coupled with each other, so that the memory system410may serve as a memory card or a solid state disk (SSD), etc. If the data processing system400is a mobile device, the system400may further include a battery for supplying voltage. In example embodiments, the data processing system400may further include, e.g., an application chipset, a camera image processor, a mobile DRAM.

It should be understood that example embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each device or method according to example embodiments should typically be considered as available for other similar features or aspects in other devices or methods according to example embodiments. While example embodiments have been particularly shown and described, it will be understood by one of ordinary skill in the art that variations in form and detail may be made therein without departing from the spirit and scope of the claims.