Laterally diffused metal oxide semiconductor field-effect transistor and manufacturing method therefor

A laterally diffused metal oxide semiconductor field-effect transistor, comprising a substrate (110), a source electrode (150), a drain electrode (140), a body region (160), and a well region on the substrate, the well region comprising: an insertion-type well (122) having P-type doping, being arranged below the drain electrode and being connected to the drain electrode; N wells (124), arranged on two sides of the insertion-type well; and P wells (126), arranged next to the N wells and being connected to the N wells; the source electrode and the body region are arranged in the P well.

FIELD OF THE INVENTION

The present disclosure relates to semiconductor processes, and more particularly relates to a laterally diffused metal oxide semiconductor field-effect transistor, and a manufacturing method of the laterally diffused metal oxide semiconductor field-effect transistor.

BACKGROUND OF THE INVENTION

A basic structure using reduced surface field (RESURF) principle consists of a low-doped P-type substrate and a low-doped N-type epitaxial layer. A P well is formed on the epitaxial layer and N+, P+are implanted into the P well, such that a transverse P-well/N-epi (P well/N-type epitaxial layer) junction and a longitudinal P-sub/N-epi (P-type substrate/N-type epitaxial layer) junction are formed. Due to a higher doping concentration at both ends of the transverse junction, the breakdown voltage of the transverse junction is lower than that of the longitudinal junction. The basic principle of RESURF is to enable the epitaxial layer to be completely depleted before the transverse junction reaches the critical avalanche breakdown field by using the interaction of the transverse junction and the longitudinal junction. By reasonably optimizing the device parameters, the breakdown of the device occurs in the longitudinal junction, thereby playing a role in reducing the surface field.

In the conventional RESURF structure, a low-doped deep well is easily to be depleted, thus the breakdown is prone to occur on a surface of a drain region, and the on-resistance is high, thereby affecting the reliability and product application.

SUMMARY OF THE INVENTION

Accordingly, in view of the problem of being high on-resistance and easy to breakdown in the conventional RESURF structure mentioned in the background art, it is necessary to provide a laterally diffused metal oxide semiconductor field-effect transistor with a low on-resistance and improved breakdown characteristics.

A laterally diffused metal oxide semiconductor field-effect transistor includes a substrate, a source, a drain, a body region, and a well region on the substrate. The well region includes: an inserting type well having a P-doping type, wherein the inserting type well is disposed below the drain and is in contact with the drain; an N well disposed on both sides of the inserting type well; and a P well disposed adjacent to the N well and in contact with the N well; wherein the source and the body region are disposed in the P well.

A method of manufacturing a laterally diffused metal oxide semiconductor field-effect transistor includes the steps of: providing a substrate; forming an N well implantation window on the substrate by lithography, and implanting N-type ions into the substrate through the N well implantation window; wherein the N well implantation window is separated by a photoresist covered on the substrate to preserve a position for an inserting type well; performing a thermal drive-in to form an N well; implanting P-type ions into the substrate and performing the thermal drive-in, thus forming the inserting type well inserted into the N well, and a P well formed adjacent to the N well and in contact with the N well; forming an active region and a field oxide; and forming a source and a drain; wherein the drain is formed above the inserting type well, and is in contact with the inserting type well.

Another method of manufacturing a laterally diffused metal oxide semiconductor field-effect transistor includes the steps of: providing a substrate; forming a first N well implantation window on the substrate by lithography, and implanting N-type ions into the substrate through the first N well implantation window; wherein the first N well implantation window is separated by a photoresist covered on the substrate to preserve a position for a first inserting type well; performing a thermal drive-in to form a first N well; implanting P-type ions into the substrate and performing the thermal drive-in, thus forming the first inserting type well inserted into the first N well, and a first P well formed adjacent to the first N well and in contact with the first N well; forming a first epitaxial layer on the substrate; performing lithography and implanting N-type ions into the first epitaxial layer, thus forming a second N well in contact with the first N well above the first N well after performing the thermal drive-in; implanting P-type ions into the second N well and performing the thermal drive-in, thus forming a second inserting type well inserted into the second N well, and a second P well formed adjacent to the second N well; wherein the second inserting type well is formed above the first inserting type well and is in contact with the first inserting type well, the second P well is formed above the first P well and is in contact with the first P well; forming an active region and a field oxide; and forming a source and a drain; wherein the drain is formed above the second inserting type well, and is in contact with the second inserting type well.

The aforementioned laterally diffused metal oxide semiconductor field-effect transistor forms a triple RESURF structure by an inserting type well, which helps to increase the doping concentration of the N well and reduce the on-resistance of the device, and helps to improve the breakdown characteristics of the device.

DETAILED DESCRIPTION OF THE EMBODIMENTS

The present disclosure provides a laterally diffused metal oxide semiconductor field-effect transistor having a reduced surface field (RESURF) structure, which includes a substrate, a source, a drain, a body region, and a well region on the substrate. The well region specifically includes an N well, a P well, and an inserting type well inserted into the N well. The inserting type well has a doping type of P-type, which is disposed below the drain and is in contact with the drain and the substrate. The N well is disposed on both sides of the inserting type well. The P well is disposed adjacent to the N well and is in contact with the N well. The source and the body region are disposed in the P well.

FIG. 1is a schematic view of a laterally diffused metal oxide semiconductor field-effect transistor (LDMOS) having a RESURF structure according to an embodiment, which is a left-right symmetric structure. The LDMOS includes a substrate110, a well region on the substrate, a drain140, a source150, a body region160, a field oxide region170, and a polysilicon structure180. The substrate is P-type doped, the drain140is N-type doped, the source150is N-type doped, and the body region160is P-type doped. The well region includes a P-type doped inserting type well122, an N well124serving as a drift region, and a P well126serving as a channel region. The field oxide region170is disposed on a surface of the N well124of the drift region, and the drain140is sandwiched by the two field oxide regions170. The polysilicon structure180is composed of a polysilicon gate and a field portion, which is extended from a surface of the field oxide region170to a surface of the source150.

Referring toFIG. 1, the P well126is inserted into the N well124by splitting the N well124to a certain width below a drain terminal N+junction of the existing structure, so as to form a triple RESURF structure, such that the inserting type well122, the N well124, the P well126, and the substrate110are depleted from each other, and the breakdown point is transferred to the device body, thus the device can be longitudinally breakdown.

In one embodiment, a width of the inserting type well122is 10% to 40% of a width of the active region of the drain.

The width of the inserting type well122cannot be too wide, and it is necessary to ensure that the N-well124at both sides below the drain140are still in contact with the drain140(i.e., the width of the inserting type well122is at least less than that of the drain140), such that a concentration of the N well124of the drift region can be improved compared with the prior art, which helps to the reduction of the on-resistance. This is because when an additional charge is added to the depletion region, the charge density of the opposite type will be increased correspondingly so as to meet the requirements of the charge balance.

The inserting type well122cannot be too narrow. The inserting type well122of a certain width can effectively control the order of the occurrence of the breakdown in the device body. If the width is too narrow, the inserting type well122has less influence on the depletion region of the N well124at both sides, and the breakdown position is close to the breakdown position when the N well124of the drift region is not provided with the inserting type well122in the prior art, such that the insertion of the inserting type well122is less effective for the adjustment of the breakdown.

When the drain140is externally coupled to a higher potential and depleted to the drain140, the inserting type well122is depleted with the N well124of the drift region at both sides, until a depletion layer formed on the N-well124at both sides is gradually expanded to be overlapped in the P well126. The potential lines on both sides are coupled to each other, and then depleted to the substrate110from top to bottom, such that the electric field peak is weakened, thereby effectively improving the breakdown voltage.

In the illustrated embodiment shown inFIG. 1, the drain140is an N+ drain, the source150is an N+ source, and the body region160is a P+ region.

FIG. 2is a schematic view of a laterally diffused metal-oxide-semiconductor field-effect transistor having a RESURF structure according to another embodiment. The difference compared to the embodiment shown inFIG. 1lies in that, the well region is composed of a high voltage well configured to cooperate with a high voltage device and a low voltage well configured to cooperate with a low voltage device. In other words, LDMOS includes a substrate210, a first well region on the substrate and a second well region on the first well region, a drain240, a source250, a body region260, a filed oxide region270, and a polysilicon structure280. The first well region includes a P-type doped first inserting type well222, a first N well224, and a first P well226. The second well region includes a second inserting type well232, a second N well234, and a third P well236. The second inserting type well232, the second N well234, and the third P well236are in contact with the first inserting type well222, the first N well224, and the first P well226, respectively. The first N well224and the second N well234cooperatively serve as a drift region. The drain250and the body region260are disposed in the second P well236.

In the embodiment shown inFIG. 2, the LDMOS further includes a floating layer P well235disposed in the second N well234and below the field oxide region270. A doping concentration of the floating layer P well235is lower than that of the second N well234, which can slow down the concentration gradient and improve the device withstand voltage.

In order to ensure that there is still a higher concentration of N-type impurities when the drift region is depleted to the active region (DTO) of the drain240, it is necessary to ensure that an N+ between the N well (including the first N well224and the second N well234) and the inserting type well (including the first inserting type well222and the second inserting type well232) still has a certain effective width, at least 30% of the active region of the drain240. Thus, widths of the first inserting type well222and the second inserting type well232should be less than or equal to 40% of a width of the active region of the drain240. In an embodiment where the active region has a width of 10 μm, the aforementioned effective width is at least 3 μm, i.e., widths of the first inserting type well222and the second inserting type well232are less than or equal to 2 μm.

In the illustrated embodiment shown inFIG. 2, the drain240is an N+ drain, the source250is an N+ source, and the body region260is a P+ region.

The present disclosure further provides a method of manufacturing a lateral diffusion metal oxide semiconductor field effect transistor having a RESURF structure for forming the LDMOS ofFIG. 1.FIG. 3is a flow chart of a method according to one embodiment including the following steps:

In step S310, a substrate is provided.

In the illustrated embodiment, a P-type doped silicon substrate is provided.

In step S320, an N well implantation window is formed by lithography, and N-type ions are implanted into the substrate through the implantation window.

Since a P well is to be inserted into an N well, a photoresist is formed at a position to be inserted, preserving the position for subsequent formation of an inserting type well. An initial oxidation can be carried out prior to lithography.

In step S330, the N well is formed by a thermal drive-in.

The oxidation of the N well is performed simultaneously with the thermal drive-in, thus an oxide layer is formed on a surface of the N well. The oxide layer can provide a self-aligned implanting structure for a P implantation in step S340, saving a piece of lithography mask. It should be noted that the photoresist is also to be removed prior to performing the next step.

In step S340, P-type ions are implanted and the thermal drive-in is performed, such that an inserting type well inserted into the N well and a P well adjacent to the N well are formed.

The formed inserting type well is sandwiched by the N well, and the P well is formed at an outer side of the N well and is in contact with the N well.

In step S350, an active region and a field oxide are formed.

In the illustrated embodiment, after forming the active region and the field oxide, a gate oxide and a polysilicon gate are generated.

In step S360, a source and a drain are formed.

The drain is formed above the inserting type well and is in contact with the inserting type well.

The present disclosure further provides another method of manufacturing a lateral diffusion metal oxide semiconductor field effect transistor having a RESURF structure for forming the LDMOS ofFIG. 2.FIG. 4is a flow chart of a method according to one embodiment including the following steps:

In step S410, a substrate is provided.

In step S420, a first N well implantation window is formed by lithography, and N-type ions are implanted into the substrate through the first N well implantation window.

In step S430, a first N well is formed by a thermal drive-in.

The oxidation of the first N well is performed simultaneously with the thermal drive-in, thus an oxide layer is formed on a surface of the first N well. The photoresist is also to be removed prior to performing the next step.

In step S440, P-type ions are implanted and the thermal drive-in is performed, such that a first inserting type well inserted into the first N well and a first P well adjacent to the first N well are formed.

In step S450, an epitaxial layer is formed on the substrate.

The excess oxide layer is removed before forming the epitaxial layer.

In step S460, lithography is performed and N-type ions are implanted into the epitaxial layer, thus a second N well in contact with the first N well is formed after performing the thermal drive-in.

The photoresist pattern is the same as that in step S420. The implanted N-type ions are drove downwardly by thermal drive-in to be in contact with the first N well. The oxidation of the second N well is performed simultaneously with the thermal drive-in, thus an oxide layer is formed on a surface of the second N well. The oxide layer serves as a self-aligned implanting structure. The photoresist is also to be removed prior to performing the next step.

In step S470, P-type ions are implanted and the thermal drive-in is performed, thus a second inserting type well inserted into the second N well and a second P well formed adjacent to the second N well are formed.

In step S480, an active region and a field oxide are formed.

In the illustrated embodiment, after forming the active region and the field oxide, a gate oxide and a polysilicon gate are generated.

In step S490, a source and a drain are formed.

The drain is formed above the second inserting type well and is in contact with the second inserting type well.

Although the description is illustrated and described herein with reference to certain embodiments, the description is not intended to be limited to the details shown. Modifications may be made in the details within the scope and range equivalents of the claims.