Three-dimensional memory device containing a shared word line driver across different tiers and methods for making the same

A semiconductor structure includes a peripheral circuit, a first three-dimensional memory array overlying the peripheral circuit and including a first alternating stack of first insulating layers and first electrically conductive layers containing first word lines and first select lines, and first memory stack structures vertically extending through the first alternating stack, and a second three-dimensional memory array overlying the first three-dimensional memory array and including a second alternating stack of second insulating layers and second electrically conductive layers containing second word lines and second select lines, and second memory stack structures vertically extending through the second alternating stack. The peripheral circuit includes a first word line driver circuit having first word line driver output nodes electrically connected to at least some of the first word lines and at least some of the second word lines, and each first word line is electrically connected to a respective second word line.

FIELD

The present disclosure relates generally to the field of semiconductor devices, and particular to multi-tier three-dimensional memory arrays sharing a word line driver across different tiers, and methods for making the same.

BACKGROUND

SUMMARY

According to one embodiment, a semiconductor structure comprises a first peripheral circuit comprising field effect transistors and dielectric material layers embedding metal interconnect structures, a first three-dimensional memory array overlying the first peripheral circuit and including a first alternating stack of first insulating layers and first electrically conductive layers comprising first word lines and first select lines, and first memory stack structures vertically extending through the first alternating stack, and a second three-dimensional memory array overlying the first three-dimensional memory array and including a second alternating stack of second insulating layers and second electrically conductive layers comprising second word lines and second select lines, and second memory stack structures vertically extending through the second alternating stack. The first peripheral circuit comprises a first word line driver circuit having first word line driver output nodes electrically connected to at least some of the first word lines and at least some of the second word lines, and each first word line is electrically connected to a respective second word line.

According to another embodiment, a method of forming a bonded assembly comprises providing a first semiconductor die comprising a first peripheral circuit comprising field effect transistors and dielectric material layers embedding metal interconnect structures, a first three-dimensional memory array overlying the first peripheral circuit and including a first alternating stack of first insulating layers and first electrically conductive layers comprising first word lines and first select lines, and first memory stack structures vertically extending through the first alternating stack, providing a second semiconductor die comprising a second three-dimensional memory array overlying the first three-dimensional memory array and including a second alternating stack of second insulating layers and second electrically conductive layers comprising second word lines and second select lines, and second memory stack structures vertically extending through the second alternating stack, and bonding the first semiconductor die to the second semiconductor die to form the bonded assembly. The first peripheral circuit comprises a first word line driver circuit having first word line driver output nodes electrically connected to at least some of the first word lines and at least some of the second word lines, and each first word line is electrically connected to a respective second word line.

According to another embodiment, a bonded assembly comprises a first semiconductor die comprising a first three-dimensional memory array including a first alternating stack of first insulating layers and first electrically conductive layers comprising first word lines and first select lines, and first memory stack structures vertically extending through the first alternating stack, a second semiconductor die comprising a second three-dimensional memory array including a second alternating stack of second insulating layers and second electrically conductive layers comprising second word lines and second select lines, and second memory stack structures vertically extending through the second alternating stack, and a third semiconductor die comprising a peripheral circuit containing a word line driver circuit comprising word line driver output nodes electrically connected to the first word lines and electrically connected to the second word lines. Each of the first word lines is electrically connected to a respective one of the second word lines.

According to another embodiment, a method of making bonded assembly comprises providing a first semiconductor die comprising a first three-dimensional memory array including a first alternating stack of first insulating layers and first electrically conductive layers comprising first word lines and first select lines, and first memory stack structures vertically extending through the first alternating stack, providing a second semiconductor die comprising a second three-dimensional memory array including a second alternating stack of second insulating layers and second electrically conductive layers comprising second word lines and second select lines, and second memory stack structures vertically extending through the second alternating stack, providing a third semiconductor die comprising a peripheral circuit containing a word line driver circuit comprising word line driver output nodes, and bonding the first, the second and the third semiconductor dies such that the word line driver output nodes are electrically connected to the first word lines and electrically connected to the second word lines, and each of the first word lines is electrically connected to a respective one of the second word lines.

DETAILED DESCRIPTION

As discussed above, the embodiments of the present disclosure are directed to multi-tier three-dimensional memory devices sharing one or more word line drivers between different tiers and methods for making the same, the various aspects of which are described herein in detail.

As used herein, a first surface and a second surface are “vertically coincident” with each other if the second surface overlies or underlies the first surface and there exists a vertical plane or a substantially vertical plane that includes the first surface and the second surface. A substantially vertical plane is a plane that extends straight along a direction that deviates from a vertical direction by an angle less than 5 degrees. A vertical plane or a substantially vertical plane is straight along a vertical direction or a substantially vertical direction, and may, or may not, include a curvature along a direction that is perpendicular to the vertical direction or the substantially vertical direction.

As used herein, a “memory level” or a “memory array level” refers to the level corresponding to a general region between a first horizontal plane (i.e., a plane parallel to the top surface of the substrate) including topmost surfaces of an array of memory elements and a second horizontal plane including bottommost surfaces of the array of memory elements. As used herein, a “through-stack” element refers to an element that vertically extends through a memory level.

The various three-dimensional memory devices of the present disclosure include a three-dimensional NAND string memory device, and may be fabricated using the various embodiments described herein. The three-dimensional NAND string is located in A three-dimensional array of NAND strings located over the substrate. At least one memory cell in the first device level of the three-dimensional array of NAND strings is located over another memory cell in the second device level of the three-dimensional array of NAND strings.

Generally, a semiconductor package (or a “package”) refers to a unit semiconductor device that may be attached to a circuit board through a set of pins or solder balls. A semiconductor package may include a semiconductor chip (or a “chip”) or a plurality of semiconductor chips that are bonded throughout, for example, by flip-chip bonding or another chip-to-chip bonding. A package or a chip may include a single semiconductor die (or a “die”) or a plurality of semiconductor dies. A die is the smallest unit that may independently execute external commands or report status. Typically, a package or a chip with multiple dies is capable of simultaneously executing as many number of external commands as the total number of dies therein. Each die includes one or more planes. Identical concurrent operations may be executed in each plane within a same die, although there may be some restrictions. In case a die is a memory die, i.e., a die including memory elements, concurrent read operations, concurrent write operations, or concurrent erase operations may be performed in each plane within a same memory die. In a memory die, each plane contains a number of memory blocks (or “blocks”), which are the smallest unit that may be erased by in a single erase operation. Each memory block contains a number of pages, which are the smallest units that may be selected for programming. A page is also the smallest unit that may be selected to a read operation.

Referring toFIG. 1, a first exemplary structure according to a first embodiment of the present disclosure is illustrated, which can be employed, for example, to fabricate a three-dimensional memory die including a three-dimensional array of memory elements such as a three-dimensional array of NAND memory elements or a three-dimensional array of NOR memory elements. While the present disclosure is described employing a three-dimensional array of NAND memory elements, embodiments of the present disclosure can be employed to form a three-dimensional array of NOR memory elements, or other types of three-dimensional memory elements.

The first exemplary structure includes a first semiconductor die901. The first semiconductor die901includes a first substrate, which includes a substrate semiconductor layer712. In one embodiment, the first substrate may be a bulk semiconductor substrate such as a commercially available silicon wafer having a diameter in a range from 150 mm to 450 mm and a thickness in a range from 600 microns to 1 mm, or may be a semiconductor-on-insulator (e.g., silicon on insulator, SOI) substrate that includes the semiconductor material layer as a top semiconductor layer overlying a buried oxide layer. The substrate semiconductor layer712may comprise a doped well in an upper part of the silicon wafer, an epitaxial silicon layer formed on a silicon wafer or a silicon layer of the SOI substrate, for example. Optionally, deep trenches can be formed through an upper portion of the first substrate, and a combination of a substrate insulating spacer732and an laterally-isolated through-substrate via structure734can be formed within each deep trench. The depth of each deep trench may be in a range from 1 micron to 20 microns, such as from 2 microns to 10 microns, and the maximum lateral dimension of each deep trench may be in a range from 1 micron to 20 microns, such as from 2 microns to 10 microns, although lesser and greater depths and maximum lateral dimensions can be employed for the deep trenches. Each deep trench may have a horizontal cross-sectional shape of a circle, an ellipse, a rectangle, a rounded rectangle, or a generally curvilinear two-dimensional closed shape. A conformal insulating material layer including an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, and/or a dielectric metal oxide can be deposited in the deep trenches by a conformal deposition process. At least one conductive fill material such as at least one metallic material and/or a heavily doped semiconductor material can be deposited in remaining volumes of the deep trenches after formation of the conformal insulating material layer. Excess portions of the conformal insulating material layer and the at least one metallic material can be removed from above the horizontal plane including the top surface of the first substrate by a planarization process such as a chemical mechanical planarization process. Each remaining portion of the conformal insulating material layer constitutes a substrate insulating spacer732, and each remaining portion of the at least one conductive material constitutes a laterally-isolated through-substrate via structure734. Each contiguous combination of a substrate insulating spacer732and a laterally-isolated through-substrate via structure734constitutes a through-substrate connection structure730.

A semiconductor circuit configured to control operation of multiple three-dimensional memory arrays can be formed on a top surface of the substrate semiconductor layer712. The semiconductor circuit comprises a first peripheral circuit720configured to control operation of the multiple three-dimensional memory arrays. The first peripheral circuit720can comprise complementary metal oxide semiconductor (CMOS) transistors. The first peripheral circuit720can comprise first proximal metal interconnect structures780embedded within first proximal dielectric material layers760.

According to an aspect of the present disclosure, the first peripheral circuit720comprises first word line driver circuit720W, a first select line driver circuit720S, and a first bit line driver circuit720B. The first word line driver circuit720W includes word line switching transistors722and output nodes724. The output nodes724may comprise source and/or drain electrodes which are electrically connected to the respective source and/or drain regions of the word line switching transistors722. The output nodes are configured to be subsequently electrically connected to a first subset of the first electrically conductive layers (e.g., first word lines which function as first control gate electrodes) in a first three-dimensional memory array and to be subsequently electrically connected to a first subset of the second electrically conductive layers (e.g., second word lines which function as second control gate electrodes) in a second three-dimensional memory array which is bonded to the first three-dimensional memory array. As used herein, a word line refers to an electrically conductive line that can activate or deactivate access to a selected memory cell. A word line driver refers to a driver configured to drive a word line. A word line driver output node refers to an output node of a word line driver.

In one embodiment, the first select line driver circuit720S can comprise first select line driver output nodes (e.g., source and/or drain electrodes of driver circuit transistors) that are configured to be electrically connected to a second subset of the first electrically conductive layers (e.g., source side and/or drain side select gate electrodes) of the first three-dimensional memory array and to be electrically isolated from each of the second electrically conductive layers of the second three-dimensional memory array. As used herein, a select line refers to an electrically conductive line that can activate or deactivate access to a block of memory cells. A select line driver refers to a driver configured to drive a select line. A select line driver output node refers to an output node of a select line driver.

In one embodiment, the first select line driver output nodes may include first source-side select line driver output nodes that are configured to be electrically connected to source-side select lines (i.e., source-side select gate electrodes) of the first electrically conductive layers of the first three-dimensional memory array to be subsequently formed. As used herein, a source-side select line refers to an electrically conductive line that can activate or deactivate access to a block of memory cells from a source side. A source-side select line driver refers to a driver configured to drive a source-side select line. A source-side select line driver output node refers to an output node of a source-side select line driver.

In one embodiment, the first select line driver output nodes may also include first drain-side select line driver output nodes that are configured to be electrically connected to drain-side select lines of the first electrically conductive layers of the first three-dimensional memory array to be subsequently formed. As used herein, a drain-side select line refers to an electrically conductive line that can activate or deactivate access to a block of memory cells from a drain-side. A drain-side select line driver refers to a driver configured to drive a drain-side select line. A drain-side select line driver output node refers to an output node of a drain-side select line driver.

In one embodiment, the first bit line driver circuit720B includes sense amplifiers and other peripheral circuit components. In one embodiment, the first bit line driver circuit720B has first bit line driver output nodes (e.g., source and/or drain electrodes of sense amplifier transistors) configured to be electrically connected to, and to drive, first bit lines in the first three-dimensional memory array to be subsequently formed. In another embodiment, the first bit line driver circuit720B has first bit line driver output nodes configured to be electrically connected to, and to drive, a first subset of the first bit lines in the first three-dimensional memory array to be subsequently formed, and a first subset of the second bit lines in a second three-dimensional memory array to be subsequently provided. As used herein, a bit line refers to an electrically conductive line that is electrically connected to a drain and can activate or deactivate a channel of a vertical NAND string. A bit line driver refers to a driver configured to drive a bit line. A bit line driver output node refers to an output node of a bit line driver.

Referring toFIG. 2, a semiconductor material layer912can be formed over the first proximal dielectric material layers760. In one embodiment, the semiconductor material layer912can be formed by depositing a semiconductor material such as silicon, a silicon-germanium alloy, or a compound semiconductor material. For example, the semiconductor material layer912can include a polysilicon layer. An alternating stack of insulating layers32and sacrificial material layers42is formed over the top surface of the semiconductor material layer912. In one embodiment, the alternating stack (32,42) can include insulating layers32composed of a first material, and sacrificial material layers42composed of a second material that is different from the first material and can be subsequently removed selective to the first material. Insulating materials that can be employed for the insulating layers32include, but are not limited to, silicon oxide (including doped or undoped silicate glass), silicon nitride, silicon oxynitride, organosilicate glass (OSG), spin-on dielectric materials, dielectric metal oxides that are commonly known as high dielectric constant (high-k) dielectric oxides (e.g., aluminum oxide, hafnium oxide, etc.) and silicates thereof, dielectric metal oxynitrides and silicates thereof, and organic insulating materials. In one embodiment, the first material of the insulating layers32can be silicon oxide.

The second material of the sacrificial material layers42is a sacrificial material that can be removed selective to the first material of the insulating layers32. As used herein, a removal of a first material is “selective to” a second material if the removal process removes the first material at a rate that is at least twice the rate of removal of the second material. The ratio of the rate of removal of the first material to the rate of removal of the second material is herein referred to as a “selectivity” of the removal process for the first material with respect to the second material. The sacrificial material layers42may comprise an insulating material, a semiconductor material, or a conductive material. The second material of the sacrificial material layers42can be subsequently replaced with electrically conductive electrodes which can function, for example, as control gate electrodes of a vertical NAND device. Non-limiting examples of the second material include silicon nitride, an amorphous semiconductor material (such as amorphous silicon), and a polycrystalline semiconductor material (such as polysilicon). In one embodiment, the sacrificial material layers42can be spacer material layers that comprise silicon nitride or a semiconductor material including at least one of silicon and germanium.

In one embodiment, the insulating layers32can include silicon oxide, and sacrificial material layers42can include silicon nitride. The first material of the insulating layers32can be deposited, for example, by chemical vapor deposition (CVD). For example, if silicon oxide is employed for the insulating layers32, tetraethyl orthosilicate (TEOS) can be employed as the precursor material for the CVD process. The second material of the sacrificial material layers42can be formed, for example, CVD or atomic layer deposition (ALD). The thicknesses of the insulating layers32and the sacrificial material layers42can be in a range from 20 nm to 50 nm, although lesser and greater thicknesses can be employed for each insulating layer32and for each sacrificial material layer42. The number of repetitions of the pairs of an insulating layer32and a sacrificial material layer (e.g., a control gate electrode or a sacrificial material layer)42can be in a range from 2 to 1,024, and typically from 8 to 256, although a greater number of repetitions can also be employed.

While the present disclosure is described employing an embodiment in which the spacer material layers are sacrificial material layers42that are subsequently replaced with electrically conductive layers, embodiments are expressly contemplated herein in which electrically conductive layers are formed in lieu of the sacrificial material layers42. In this case, subsequently processing steps for replacing the sacrificial material layers42with electrically conductive layers can be omitted.

The alternating stack (32,42) can be patterned to form stepped surfaces at least one side. As used herein, “stepped surfaces” refer to a set of surfaces that include at least two horizontal surfaces and at least two vertical surfaces such that each horizontal surface is adjoined to a bottom edge of a respective vertical surface, and a top edge of each vertical surface is adjoined to an edge of a respective horizontal surface. A stepped cavity is formed within the volume from which portions of the alternating stack (32,42) are removed through formation of the stepped surfaces. A “stepped cavity” refers to a cavity having stepped surfaces. Optionally, a non-stepped cavity may be formed on an opposite side of the stepped cavity. As used herein, a non-stepped cavity refers to a cavity without stepped surfaces. Thus, a non-stepped cavity can include straight sidewalls that vertically extend from a bottommost surface of the alternating stack (32,42) to a topmost surface of the alternating stack (32,42).

Each sacrificial material layer42other than a topmost sacrificial material layer42within the alternating stack (32,42) laterally extends farther than any overlying sacrificial material layer42within the alternating stack (32,42) in a connection (i.e., staircase or terrace) region200. The connection region200includes stepped surfaces of the alternating stack (32,42) that continuously extend from a bottommost layer within the alternating stack (32,42) to a topmost layer within the alternating stack (32,42). Each of the sacrificial material layers42has a respective lateral extent. The sacrificial material layers42can have different lateral extents along a horizontal direction. In one embodiment, the lateral extents of the sacrificial material layers42can increase with a respective vertical distance from the top surface of the semiconductor material layer912. Each of the insulating layers32has a respective lateral extent. The insulating layers32can have different lateral extents along the horizontal direction. In one embodiment, the lateral extents of the insulating layers32can increase with a respective vertical distance from the top surface of the semiconductor material layer912.

A stepped dielectric material portion65can be formed in the stepped cavity by deposition of a dielectric material therein. For example, a dielectric material such as silicon oxide can be deposited in the stepped cavity. Excess portions of the deposited dielectric material can be removed from above the top surface of the alternating stack (32,42), for example, by chemical mechanical planarization (CMP). The remaining portion of the deposited dielectric material filling the stepped cavity constitutes the stepped dielectric material portion65. If silicon oxide is employed for the stepped dielectric material portion65, the silicon oxide of the stepped dielectric material portion65may, or may not, be doped with dopants such as B, P, and/or F. A non-stepped dielectric material portion165can be formed in the non-stepped cavity concurrently with formation of the stepped dielectric material portion65.

Referring toFIG. 3, a lithographic material stack (not shown) including at least a photoresist layer can be formed over the alternating stack (32,42) and the stepped dielectric material portion65, and can be lithographically patterned to form openings therein. The openings include a set of openings formed over a memory array region100and a second set of openings formed over a connection region200that is adjacent to the stepped surfaces. The memory array region100and the connection region200are located within the area in which each layer of the alternating stack (32,42) is present. The memory array region100can be laterally spaced from a peripheral region300by the connection region200. In other words, the connection region200can be located between the memory array region100and the peripheral region300.

The pattern in the lithographic material stack can be transferred through the alternating stack (32,42) or the stepped dielectric material portion65, and through the alternating stack (32,42) by at least one anisotropic etch that employs the patterned lithographic material stack as an etch mask. Portions of the alternating stack (32,42) underlying the openings in the patterned lithographic material stack are etched to form memory openings49. As used herein, a “memory opening” refers to a structure in which memory elements, such as a memory stack structure, is subsequently formed. The memory openings49are formed through each layer of the alternating stack (32,42) in the memory array region100. Optionally, support openings (not shown) can be formed in addition to the memory openings49. In this case, a support pillar structure (not shown) including a dielectric material or a same set of materials as a memory opening fill structure can be subsequently formed within each support opening.

The chemistry of the anisotropic etch process employed to etch through the materials of the alternating stack (32,42) can alternate to optimize etching of the and second materials in the alternating stack (32,42). The anisotropic etch can be, for example, a series of reactive ion etches. The sidewalls of the memory openings49can be substantially vertical, or can be tapered. The patterned lithographic material stack can be subsequently removed, for example, by ashing. The memory openings49can extend from the top surface of the alternating stack (32,42) to at least the horizontal plane including the topmost surface of the semiconductor material layer912. The lithographic mask stack can be subsequently removed, for example, by ashing. Each of the memory openings49may include a sidewall (or a plurality of sidewalls) that extends substantially perpendicular to the topmost surface of the semiconductor material layer912. A two-dimensional array of memory openings49can be formed in the memory array region100.

FIGS. 4A-4Hillustrate structural changes in a memory opening49, which is one of the memory openings49in the first exemplary structure ofFIG. 3. Referring toFIG. 4A, a memory opening49in the exemplary device structure ofFIG. 3is illustrated. The memory opening49extends through the alternating stack (32,42), and optionally into an upper portion of the semiconductor material layer912. The recess depth of the bottom surface of each memory opening49with respect to the top surface of the semiconductor material layer912can be in a range from 0 nm to 30 nm, although greater recess depths can also be employed. Optionally, the sacrificial material layers42can be laterally recessed partially to form lateral recesses (not shown), for example, by an isotropic etch.

Referring toFIG. 4B, an optional pedestal channel portion (e.g., an epitaxial pedestal)11can be formed at the bottom portion of each memory opening49, for example, by selective epitaxy. Each pedestal channel portion11may comprise a single crystalline semiconductor material in epitaxial alignment with the single crystalline semiconductor material of the semiconductor material layer912in case the semiconductor material layer912is single crystalline. In one embodiment, the pedestal channel portion11can be doped with electrical dopants of the same conductivity type as the semiconductor material layer912.

Referring toFIG. 4C, a stack of layers including a blocking dielectric layer52, a charge storage layer54, a tunneling dielectric layer56, and an optional semiconductor channel layer601can be sequentially deposited in the memory openings49.

Referring toFIG. 4D, the optional semiconductor channel layer601, the tunneling dielectric layer56, the charge storage layer54, the blocking dielectric layer52are sequentially anisotropically etched employing at least one anisotropic etch process. The portions of the semiconductor channel layer601, the tunneling dielectric layer56, the charge storage layer54, and the blocking dielectric layer52located above the top surface of the alternating stack (32,42) can be removed by the at least one anisotropic etch process. Further, the horizontal portions of the semiconductor channel layer601, the tunneling dielectric layer56, the charge storage layer54, and the blocking dielectric layer52at a bottom of each memory cavity49′ can be removed to form openings in remaining portions thereof. Each of the semiconductor channel layer601, the tunneling dielectric layer56, the charge storage layer54, and the blocking dielectric layer52can be etched by a respective anisotropic etch process employing a respective etch chemistry, which may, or may not, be the same for the various material layers.

Each remaining portion of the semiconductor channel layer601can have a tubular configuration. The charge storage layer54can comprise a charge trapping material or a floating gate material. In one embodiment, each charge storage layer54can include a vertical stack of charge storage regions that store electrical charges upon programming. In one embodiment, the charge storage layer54can be a charge storage layer in which each portion adjacent to the sacrificial material layers42constitutes a charge storage region.

A surface of the pedestal channel portion11(or a surface of the semiconductor material layer912in case the pedestal channel portions11are not employed) can be physically exposed underneath the opening through the semiconductor channel layer601, the tunneling dielectric layer56, the charge storage layer54, and the blocking dielectric layer52. Optionally, the physically exposed semiconductor surface at the bottom of each memory cavity49′ can be vertically recessed so that the recessed semiconductor surface underneath the memory cavity49′ is vertically offset from the topmost surface of the pedestal channel portion11(or of the semiconductor material layer912in case pedestal channel portions11are not employed) by a recess distance. A tunneling dielectric layer56is located over the charge storage layer54. A set of a blocking dielectric layer52, a charge storage layer54, and a tunneling dielectric layer56in a memory opening49constitutes a memory film50, which includes a plurality of charge storage regions (comprising the charge storage layer54) that are insulated from surrounding materials by the blocking dielectric layer52and the tunneling dielectric layer56. In one embodiment, the semiconductor channel layer601, the tunneling dielectric layer56, the charge storage layer54, and the blocking dielectric layer52can have vertically coincident sidewalls.

Referring toFIG. 4E, a second semiconductor channel layer602can be deposited directly on the semiconductor surface of the pedestal channel portion11or the semiconductor material layer912if the pedestal channel portion11is omitted, and directly on the semiconductor channel layer601. The second semiconductor channel layer602may partially fill the memory cavity49′ in each memory opening, or may fully fill the cavity in each memory opening. The materials of the semiconductor channel layer601and the second semiconductor channel layer602are collectively referred to as a semiconductor channel material. In other words, the semiconductor channel material is a set of all semiconductor material in the semiconductor channel layer601and the second semiconductor channel layer602.

Referring toFIG. 4F, in case the memory cavity49′ in each memory opening is not completely filled by the second semiconductor channel layer602, a dielectric core layer62L can be deposited in the memory cavity49′ to fill any remaining portion of the memory cavity49′ within each memory opening. The dielectric core layer62L includes a dielectric material such as silicon oxide or organosilicate glass. The dielectric core layer62L can be deposited by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD), or by a self-planarizing deposition process such as spin coating.

Referring toFIG. 4G, the horizontal portion of the dielectric core layer62L can be removed, for example, by a recess etch from above the top surface of the alternating stack (32,42). Each remaining portion of the dielectric core layer62L constitutes a dielectric core62. Further, the horizontal portion of the second semiconductor channel layer602located above the top surface of the alternating stack (32,42) can be removed by a planarization process, which can employ a recess etch or chemical mechanical planarization (CMP).

Each adjoining pair of a semiconductor channel layer601and a second semiconductor channel layer602can collectively form a vertical semiconductor channel60through which electrical current can flow when a vertical NAND device including the vertical semiconductor channel60is turned on. A tunneling dielectric layer56is surrounded by a charge storage layer54, and laterally surrounds a portion of the vertical semiconductor channel60. Each adjoining set of a blocking dielectric layer52, a charge storage layer54, and a tunneling dielectric layer56collectively constitute a memory film50, which can store electrical charges with a macroscopic retention time. In some embodiments, a blocking dielectric layer52may not be present in the memory film50at this step, and a blocking dielectric layer may be subsequently formed after formation of backside recesses. As used herein, a macroscopic retention time refers to a retention time suitable for operation of a memory device as a permanent memory device such as a retention time in excess of 24 hours.

Referring toFIG. 4H, the top surface of each dielectric core62can be further recessed within each memory opening, for example, by a recess etch to a depth that is located between the top surface of the alternating stack (32,42) and the bottom surface of the alternating stack (32,42). Drain regions63can be formed by depositing a doped semiconductor material within each recessed region above the dielectric cores62. The drain regions63can have a doping of a second conductivity type that is the opposite of the conductivity type. For example, if the conductivity type is p-type, the second conductivity type is n-type, and vice versa. The dopant concentration in the drain regions63can be in a range from 5.0×1019/cm3to 2.0×1021/cm3, although lesser and greater dopant concentrations can also be employed. The doped semiconductor material can be, for example, doped polysilicon. Excess portions of the deposited semiconductor material can be removed from above the top surface of the alternating stack (32,42), for example, by chemical mechanical planarization (CMP) or a recess etch to form the drain regions63.

Each combination of a memory film50and a vertical semiconductor channel60within a memory opening49constitutes a memory stack structure55. The memory stack structure55is a combination of a semiconductor channel, a tunneling dielectric layer, a plurality of memory elements comprising portions of the charge storage layer54, and an optional blocking dielectric layer52. Each combination of a pedestal channel portion11(if present), a memory stack structure55, a dielectric core62, and a drain region63within a memory opening49is herein referred to as a memory opening fill structure58.

Referring toFIG. 5, the first exemplary structure is illustrated after formation of memory opening fill structures58within the memory openings49. An instance of a memory opening fill structure58can be formed within each memory opening49of the structure ofFIG. 3. Each memory stack structure55includes a vertical semiconductor channel60, which may comprise multiple semiconductor channel layers (601,602) or a single semiconductor channel layer602, and a memory film50. The memory film50may comprise a tunneling dielectric layer56laterally surrounding the vertical semiconductor channel60and a vertical stack of charge storage regions (comprising portions of a charge storage layer54) laterally surrounding the tunneling dielectric layer56and an optional blocking dielectric layer52. While the present disclosure is described employing the illustrated configuration for the memory stack structure, the methods of the present disclosure can be applied to alternative memory stack structures including different layer stacks or structures for the memory film50and/or for the vertical semiconductor channel60.

Generally, the memory openings49vertically extending through each layer within the alternating stack (32,42). Memory opening fill structures58are located in the memory openings49. Each memory opening fill structure58comprises a respective vertical semiconductor channel60and a respective memory film50. A three-dimensional array of memory elements is provided, which comprises portions of the memory films50. For example, the three-dimensional array of memory elements can comprise portions of the charge storage layer54that are located at levels of the sacrificial material layers42. In one embodiment, each memory elements can include a cylindrical portion of a respective charge storage layer54that contacts a respective sacrificial material layer42. The semiconductor material layer912can comprise a semiconductor material layer912in electrical contact with a bottom end of each of the vertical semiconductor channels60.

Referring toFIG. 6, a photoresist layer (not shown) can be applied over the alternating stack (32,42), the stepped dielectric material portion65, and the non-stepped dielectric material portion165, and is lithographically patterned to form openings in areas between clusters of memory opening fill structures58. The pattern in the photoresist layer can be transferred through the alternating stack (32,42) and/or the stepped dielectric material portion65employing an anisotropic etch to form backside trenches79, which vertically extend from the top surface of the alternating stack (32,420) at least to the top surface of the semiconductor material layer912. In one embodiment, the backside trenches79may be laterally elongated along a horizontal direction.

Referring toFIG. 7, an etchant that selectively etches the second material of the sacrificial material layers42with respect to the first material of the insulating layers32can be introduced into the backside trenches79, for example, employing an etch process. Backside recesses are formed in volumes from which the sacrificial material layers42are removed. The removal of the second material of the sacrificial material layers42can be selective to the first material of the insulating layers32, the material of the stepped dielectric material portion65and the non-stepped dielectric material portion165, the semiconductor material of the semiconductor material layer912, and the material of the outermost layer of the memory films50. In one embodiment, the sacrificial material layers42can include silicon nitride, and the materials of the insulating layers32, the stepped dielectric material portion65, and the non-stepped dielectric material portion165can be selected from silicon oxide and dielectric metal oxides.

The etch process that removes the second material selective to the first material and the outermost layer of the memory films50can be a wet etch process employing a wet etch solution, or can be a gas phase (dry) etch process in which the etchant is introduced in a vapor phase into the backside trenches79. For example, if the sacrificial material layers42include silicon nitride, the etch process can be a wet etch process in which the first exemplary structure is immersed within a wet etch tank including phosphoric acid, which etches silicon nitride selective to silicon oxide, silicon, and various other materials employed in the art. The stepped dielectric material portion65and the memory opening fill structures58provide structural support while the backside recesses are present within volumes previously occupied by the sacrificial material layers42.

Each backside recess can be a laterally extending cavity having a lateral dimension that is greater than the vertical extent of the cavity. In other words, the lateral dimension of each backside recess can be greater than the height of the backside recess. A plurality of backside recesses can be formed in the volumes from which the second material of the sacrificial material layers42is removed. The memory openings in which the memory stack structures55are formed are herein referred to as front side openings or front side cavities in contrast with the backside recesses. In one embodiment, the memory array region100comprises an array of monolithic three-dimensional NAND strings having a plurality of device levels disposed above the semiconductor material layer912. In this case, each backside recess can define a space for receiving a respective word line of the array of monolithic three-dimensional NAND strings.

Each of the plurality of backside recesses can extend substantially parallel to the top surface of the semiconductor material layer912. A backside recess can be vertically bounded by a top surface of an underlying insulating layer32and a bottom surface of an overlying insulating layer32. In one embodiment, each backside recess can have a uniform height throughout. Physically exposed surface portions of the optional pedestal channel portions11and the semiconductor material layer912can be converted into dielectric material portions by thermal conversion and/or plasma conversion of the semiconductor materials into dielectric materials. For example, thermal conversion and/or plasma conversion can be employed to convert a surface portion of each pedestal channel portion11into a tubular dielectric spacer, and to convert each physically exposed surface portion of the semiconductor material layer912into a planar dielectric portion.

A backside blocking dielectric layer (not shown) can be optionally formed. At least one metallic material can be deposited in the backside recesses by at least one conformal deposition process. For example, a combination of a metallic barrier layer and a metallic fill material can be deposited in the backside recesses. The metallic barrier layer includes an electrically conductive metallic material that can function as a diffusion barrier layer and/or adhesion promotion layer for the metallic fill material. The metallic barrier layer can include a conductive metallic nitride material such as TiN, TaN, WN, or a stack thereof, or can include a conductive metallic carbide material such as TiC, TaC, WC, or a stack thereof. The metal fill material is deposited in remaining volumes of backside recesses, on the sidewalls of the at least one the backside trench79, and over the top surface of the topmost insulating layer32. The metallic fill material can be deposited by a conformal deposition method, which can be, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), electroless plating, electroplating, or a combination thereof. In one embodiment, the metallic fill material layer can consist essentially of at least one elemental metal. The at least one elemental metal of the metallic fill material layer can be selected, for example, from tungsten, cobalt, ruthenium, titanium, and tantalum.

Portions of the at least one conductive material deposited at peripheral regions of the backside trenches79or above the topmost insulating layer32can be removed by an isotropic etch back process. Each remaining portion of the deposited metallic material in the backside recesses constitutes an electrically conductive layer46. Each electrically conductive layer46can be a conductive line structure. Thus, the sacrificial material layers42are replaced with the electrically conductive layers46, and an alternating stack of the insulating layers32and the electrically conductive layers46is formed.

Each electrically conductive layer46can function as a combination of a plurality of control gate electrodes located at a same level and a word line electrically interconnecting, i.e., electrically shorting, the plurality of control gate electrodes located at the same level. The plurality of control gate electrodes within each electrically conductive layer46are the control gate electrodes for the vertical memory devices including the memory stack structures55. In other words, each electrically conductive layer46can be a word line that functions as a common control gate electrode for the plurality of vertical memory devices.

A conformal insulating material layer including an insulating material can be deposited in the backside trenches79, and can be anisotropically etched to form insulating spacers74. The insulating spacers74include insulating spacers74that are formed at peripheral portions of the backside trenches79. The insulating spacers74include an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, and/or a dielectric metal oxide. The insulating spacers74may have a lateral thickness in a range from 10 nm to 100 nm, such as from 20 nm to 50 nm, although lesser and greater lateral thicknesses may also be employed. Source regions (not shown) may be formed at the bottom of each backside trench79by implantation of dopants of a second conductivity type, which is the opposite of the conductivity type. For example, if the conductivity type is p-type, the second conductivity type is n-type, and vice versa.

At least one conductive material can be deposited in remaining volumes of the backside trenches79. The at least one conductive material can include, for example, a combination of a metallic barrier layer and a metallic fill material. The metallic barrier layer includes an electrically conductive metallic material that can function as a diffusion barrier layer and/or adhesion promotion layer for the metallic fill material. The metallic barrier layer can include a conductive metallic nitride material such as TiN, TaN, WN, or a stack thereof, or can include a conductive metallic carbide material such as TiC, TaC, WC, or a stack thereof. The metallic fill material can be deposited by a conformal deposition method, which can be, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), electroless plating, electroplating, or a combination thereof. In one embodiment, the metallic fill material layer can consist essentially of at least one elemental metal. The at least one elemental metal of the metallic fill material layer can be selected, for example, from tungsten, cobalt, ruthenium, titanium, and tantalum. Excess portions of the at least one conductive material can be removed from above the horizontal plane including the top surface of the alternating stack (32,46) by a planarization process such as a chemical mechanical planarization process. Each remaining portion of the at least one conductive material filling a backside trench79constitutes a backside contact via structure76, which can contact a top surface of a respective source region embedded in the semiconductor material layer912.

Alternatively, at least one dielectric material, such as silicon oxide, may be conformally deposited in the backside trenches79by a conformal deposition process. Each portion of the deposited dielectric material that fills a backside trench79constitutes a backside trench fill structure. In this case, each backside trench fill structure may fill the entire volume of a backside trench79and may consist essentially of at least one dielectric material. In this alternative embodiment, a horizontal source line (e.g., direct strap contact) may contact an side of the lower portion of the semiconductor channel60.

Referring toFIG. 8, a contact-level dielectric layer70can be deposited over the alternating stack (32,46), the stepped dielectric material portion65, and the non-stepped dielectric material portion165. The contact-level dielectric layer70includes a dielectric material such as silicon oxide. The thickness of the contact-level dielectric layer70can be in a range from 100 nm to 600 nm, although lesser and greater thicknesses can also be employed.

Various via cavities can be applied through the contact-level dielectric layer70and underlying dielectric material portions such as the stepped dielectric material portion65, the non-stepped dielectric material portion165, upper portions of the first proximal dielectric material layers760, and optionally through the first alternating stack of the first insulating layers32and the first electrically conductive layers46(which function as word lines and select lines).

In case some contact via cavities are formed through the first alternating stack (32,46), insulating liners81may be formed on physically exposed sidewalls of the first alternating stack (32,46), for example, by conformally depositing and anisotropically etching a continuous insulating liner layer such as a silicon oxide liner layer. At least one conductive material can be deposited in the various contact via cavities. The at least one conductive material can include, for example, a combination of a metallic barrier layer and a metallic fill material. Excess portions of the at least one conductive material can be removed from above the horizontal plane including the top surface of the contact-level dielectric layer70. Remaining portions of the at least one conductive material filling the contact via cavities constitute various contact via structures (88,82,84).

The contact via structures (88,82,84) can include drain contact via structures88contacting a respective drain region63, optional through-stack contact via structures82vertically extending through the alternating stack (32,46), and through-dielectric contact via structures84that vertically extends through the stepped dielectric material portion65or through the non-stepped dielectric material portion165. The through-stack contact via structures82and the through-dielectric contact via structures84can contact a respective one of the first proximal metal interconnect structures780that are embedded within the first proximal dielectric material layers760.

Referring toFIG. 9, first distal dielectric material layers90are formed over the contact-level dielectric layer70. Bit lines92and distal metal interconnect structures94are formed in the first distal dielectric material layers90. First metal bonding pads98are formed in the topmost layer of the first distal dielectric material layers90.

The memory stack structures55extending through the first alternating stack of first insulating layers32and the first electrically conductive layers46are herein referred to as first memory stack structures55. Each first memory stack structure55comprises a respective first vertical semiconductor channel60and a respective first vertical stack of memory elements (such as a memory film50including portions of a charge storage layer54located at levels of the first electrically conductive layers46).

The first three-dimensional memory array comprises first bit lines92. The first bit lines92are electrically connected to a first end of a respective subset of the first vertical semiconductor channels60. For example, each of the first bit lines92can contact top surfaces of a respective subset of the drain contact via structures88. The first peripheral circuit720comprises a first bit line driver circuit720B having first bit line driver output nodes electrically connected to a first subset of the first bit lines92. Generally, a first semiconductor die901can be provided, which comprises a first three-dimensional memory array including a first alternating stack of first insulating layers32and first electrically conductive layers46and first memory stack structures55vertically extending through the first alternating stack (32,46), a first peripheral circuit720comprising a first word line driver circuit720W, and first dielectric material layers (760,90) embedding first metal interconnect structures (780,92) and first metal bonding pads98.

Referring toFIG. 10, a second semiconductor die902can be provided, which can be derived from the first semiconductor die901by changing the pattern of the metal bonding pads98. Specifically, the pattern of second metal bonding pads98in the second semiconductor die902can be a mirror image pattern of the pattern of the first metal bonding pads98in the first semiconductor die901.

The second semiconductor die902comprises a second three-dimensional memory array including a second alternating stack of second insulating layers32and second electrically conductive layers46and second memory stack structures55vertically extending through the second alternating stack (32,46). The second semiconductor die902comprises a second peripheral circuit720including a second word line driver circuit720W, second select line driver circuit720S and second bit line driver circuit720B, and second dielectric material layers (760,90) embedding second proximal metal interconnect structures780and second metal bonding pads98.

According to an aspect of the present disclosure, the second word line driver circuit720W comprises second word line switching transistors and output nodes that are configured to be subsequently electrically connected to a second subset of the first electrically conductive layers46(e.g., word lines) in the first three-dimensional memory array in the first semiconductor die901, and electrically connected to a second subset of the second electrically conductive layers46in the second three-dimensional memory array in the second semiconductor die902.

In one embodiment, the second select line driver circuit720S output nodes may include second source-side select line driver output nodes that are electrically connected to source-side select lines among the second electrically conductive layers46of the second three-dimensional memory array. In one embodiment, the second select line driver circuit720S output nodes may also include second drain-side select line driver output nodes that are electrically connected to drain-side select lines among the second electrically conductive layers46of the second three-dimensional memory array.

In one embodiment, the second bit line driver circuit720B has second bit line driver output nodes configured to be electrically connected to, and to drive, a second subset of the first bit lines in the first three-dimensional memory array in the first semiconductor die901and a second subset of the second bit lines in the second three-dimensional memory array in the second semiconductor die902. In this embodiment, the bit lines92of the first and second semiconductor die (901,902) are electrically connected to each other. In an alternative embodiment, the second bit line driver circuit720B may second bit line driver output nodes configured to be electrically connected to, and to drive, only the second bit lines in the second three-dimensional memory array in the second semiconductor die902. In this alternative embodiment, the bit lines92of the first and second semiconductor die (901,902) are not electrically connected to each other.

The second semiconductor die902can be aligned to the first semiconductor die901, and can be subsequently boned to each other. Generally, a plurality of first semiconductor dies901can be provided within a first wafer, and a plurality of second semiconductor dies902can be provided within a second wafer. The plurality of first semiconductor dies901can be bonded to the plurality of second semiconductor dies902by wafer-to-wafer bonding. Specifically, each set of second metal bonding pads98within a second semiconductor die902can be bonded to a respective set of first metal bonding pads98in a first semiconductor die901that is bonded to the second semiconductor die902.

The first peripheral circuit720comprises a first word line driver circuit720W having first word line driver output nodes electrically connected to a first subset of the first electrically conductive layers46and electrically connected to a first subset of the second electrically conductive layers46through a first subset of mating pairs of the first metal bonding pads98and the second metal bonding pads98. The second peripheral circuit720comprises a second word line driver circuit720W having second word line driver output nodes electrically connected to a second subset of the first electrically conductive layers46through a second subset of the mating pairs of the first metal bonding pads98and the second metal bonding pads98and electrically connected to a second subset of the second electrically conductive layers46.

Referring toFIG. 11, the first substrate712or the second substrate712may be thinned. For example, the backside of the second substrate712can be thinned, for example, by grinding, polishing, an anisotropic etch process, and/or an isotropic etch process. In one embodiment, the second substrate712can be thinned until surfaces of the laterally-isolated through-substrate via structures734are physically exposed. The through-substrate connection structures730can vertically extend through the thinned second substrate712. Each through-substrate connection structure730can include a laterally-isolated through-substrate via structure734and a substrate insulating spacer732.

Referring toFIG. 12, a second backside dielectric material layer790can be formed on the backside of the second substrate712, and second backside bonding pads798can be formed in the second backside dielectric material layer790. Each second backside bonding pads798can be formed directly on a respective one of the laterally-isolated through-substrate via structure734. A handle substrate600can be attached to the second semiconductor die902.

Referring toFIG. 13, the backside of the first substrate712can be thinned, for example, by grinding, polishing, an anisotropic etch process, and/or an isotropic etch process. For example, the first substrate712can be thinned until surfaces of the laterally-isolated through-substrate via structures734are physically exposed. The through-substrate connection structures730can vertically extend through the thinned first substrate712. Each through-substrate connection structure730can include a laterally-isolated through-substrate via structure734and a substrate insulating spacer732. A first backside dielectric material layer790can be formed on the backside of the first substrate712, and first backside bonding pads798can be formed in the first backside dielectric material layer790. Each first backside bonding pads798can be formed directly on a respective one of the laterally-isolated through-substrate via structure734.

Referring toFIGS. 14, 15 and 16A, the handle substrate600can be detached from the second substrate902.

Generally, the first metal bonding pads98and/or the first backside bonding pads798of the first semiconductor die901may be employed for bonding, and the second metal bonding pads98or the second backside bonding pads798of the second semiconductor die902may be employed for bonding. Thus, the first stepped surfaces of the first alternating stack (32,46) that contact the first retro-stepped dielectric material portion65of the first semiconductor die901may be oriented toward, or away from, the second semiconductor die902, and the second stepped surfaces of the second alternating stack (32,46) that contact the second retro-stepped dielectric material portion65of the second semiconductor die902may be oriented toward, or away from, the first semiconductor die901.

Referring toFIG. 16B, an alternative configuration of the first exemplary structure can be derived from the configuration ofFIG. 16Aby not electrically connecting the respective bit lines92of the bonded semiconductor die (901,902). In the configuration ofFIG. 16B, the bit lines92of each semiconductor die (901,902) are electrically connected to and are driven by the bit line driver circuit720B on the same respective semiconductor die (901,902).

As shown inFIG. 16B, the respective word lines46W in each semiconductor die (901,902) are electrically connected to each other through contact via structures86and bonding pads98. One set of word lines46W (e.g., the word lines closer to the drain-side select lines46D) in both semiconductor dies (901,902) are electrically connected to the word line driver circuit720W in the first semiconductor die901, as shown by the lower dashed circle and arrow. Another set of word lines46W (e.g., the word lines closer to the source-side select lines46S) in both semiconductor dies (901,902) are electrically connected to the word line driver circuit720W in the second semiconductor die902, as shown by the upper dashed circle and arrow.

Thus, “n” effective word lines in the two semiconductor die (901,902) are split into n/2 word line parts46W located in the first semiconductor die901and n/2 word line parts46W located in the second semiconductor die902. However, the respective word lines parts (e.g., word lines46W having the same number counting from the source-side select line in each die) are electrically connected to each other and are driven by the same word line switching transistor of the word line driver circuit720W in one of the two semiconductor die. Thus, each word line driver circuit720W of each semiconductor die effectively drives n/2 word lines due to the electrical connection of the respective word lines. This reduces the total area of the word line driver circuits720W in half compared to having n word lines in one semiconductor die being driven separately by a word line driver circuit in the same semiconductor die. Furthermore, this permits the peripheral region300to be increased (e.g., doubled). The word line effective length becomes double (i.e., each effective word line has a first part46W in the first semiconductor die901and the second part46W in the first semiconductor die902electrically connected together by the contact via structure96). This causes the page size to also double in size. The number of planes may also be reduced (e.g., by half).

In a split select line driver configuration shown inFIG. 16A, the select lines (46S,46D) in one semiconductor die may be electrically connected to the select line driver circuit720S in the same semiconductor die. Thus, the select lines (e.g., source-side select lines46S and drain-side select lines46D) in each semiconductor die (901,902) are separately electrically connected to the select line driver circuit720S in their respective semiconductor die. In this configuration, each select line driver circuit720S includes output nodes that are configured to be electrically connected to the select lines of the second three-dimensional memory array in the same semiconductor die, and to be electrically isolated from each of the electrically conductive layers of the three-dimensional memory array in the other semiconductor die.

In a non-split select line driver configuration shown inFIG. 16B, the select lines (46S,46D) in one semiconductor die may be electrically connected to the select line driver circuit720S in the same semiconductor die or in the other semiconductor die. The connections may be configured to optimize the speed of the device.

Referring toFIG. 17, a first alternative embodiment of the first exemplary structure is illustrated, in which a bonded assembly comprises a first semiconductor die901, a second semiconductor die902, and a third semiconductor die. The word line drivers of the peripheral circuits720can be interconnected across the bonding interfaces of the semiconductor dies (901,902,903) through mating pairs of bonding pads (98,798). For example, first word line drivers720W of the first peripheral circuit720in the first semiconductor die901drive a first subset of first word lines (which are a first subset of the first electrically conductive layers46) in the first semiconductor die901, a first subset of second word lines (which are a first subset of the second electrically conductive layers46) in the second semiconductor die902, and a first subset of third word lines (which are a first subset of the third electrically conductive layers46) in the third semiconductor die903. Second word line drivers720W of the second peripheral circuit720in the second semiconductor die902drive a second subset of the first word lines (which are the first subset of the first electrically conductive layers46) in the first semiconductor die901, a second subset of the second word lines (which are the first subset of the second electrically conductive layers46) in the second semiconductor die902, and a second subset of third word lines (which are the first subset of the third electrically conductive layers46) in the third semiconductor die903. Third word line drivers720W of the third peripheral circuit720in the third semiconductor die903drives a third subset of the first word lines (which are the first subset of the first electrically conductive layers46) in the first semiconductor die901, a third subset of the second word lines (which are the first subset of the second electrically conductive layers46) in the second semiconductor die902, and a third subset of third word lines (which are the first subset of the third electrically conductive layers46) in the third semiconductor die903. Generally, an output node of a word line driver circuit720W can be connected to a first word line in the first semiconductor die901, a second word line in the second semiconductor die902, and a third word line in the third semiconductor die903. Thus, the total footprint for the word line driver circuit can be reduced through sharing of word line driver output nodes across the multiple semiconductor dies (901,902,903).

In one embodiment, each peripheral circuit720of a semiconductor die (901,902, or903) can comprise select line drivers720S having a respective set of select line driver output nodes that are electrically connected to select-level electrically conductive layers (which are a subset of the electrically conductive layers46) within the same semiconductor die (901,902, or903), and is electrically isolated from all select-level electrically conductive layers in different semiconductor dies in a split select line driver configuration. Alternatively, the above described non-split select line driver configuration may be used instead, in which select line drivers720S having a respective set of select line driver output nodes that are electrically connected to select-level electrically conductive layers (which are a subset of the electrically conductive layers46) within the same semiconductor die and within other semiconductor dies (901,902, or903). Each set of select line driver output nodes may include source-side select line driver output nodes that are electrically connected to source-side select lines, and drain-side select line driver output nodes that are electrically connected to drain-side select lines.

Each peripheral circuit720of a semiconductor die (901,902, or903) can comprise a respective bit line driver circuit720B having a respective set of bit line driver output nodes configured to be electrically connected to, and to drive, a respective subset of the bit lines92in the first three-dimensional memory array in the first semiconductor die901, a respective subset of the bit lines in the second three-dimensional memory array in the second semiconductor die902, and a respective subset of the bit lines in the third three-dimensional memory array in the third semiconductor die903. In this case, each bit line driver output node may be connected to a bit line in the first semiconductor die901, a bit line in the second semiconductor die902, and a bit line in the third semiconductor die903. Thus, the total footprint for the bit line driver circuit720B can be reduced through sharing of bit line driver output nodes across the multiple semiconductor dies (901,902,903). Alternatively, each bit line driver circuit720B may be electrically connected to only bit lines92located in the same semiconductor die as the respective bit line driver circuit720B.

Referring toFIG. 18, a second alternative embodiment of the first exemplary structure is illustrated, which can be derived by modifying the first exemplary structure ofFIGS. 14-16or the first alternative embodiment of the first exemplary structure ofFIG. 17to bond four or more semiconductor dies (901,902,903,904). The word line drivers720W of each peripheral circuit720and/or the bit line drivers720B of each peripheral circuit720can be shared among four or more semiconductor dies (901,902,903,904). Generally, if N semiconductor dies including a respective three-dimensional memory array and a respective peripheral circuit720are vertically stacked and bonded to each other, then each word line driver circuit720W in each respective one of N semiconductor die can drive 1/N times the total number of first word lines in the first semiconductor die901, 1/N times the total number of second word lines in the second semiconductor die902, and so on up to 1/N times the total number of N-th word lines in the N-th semiconductor die. Alternatively or additionally, if N semiconductor dies including a respective three-dimensional memory array and a respective peripheral circuit720are vertically stacked and bonded to each other, each bit line driver circuit720B in each respective one of N semiconductor die can drive 1/N times the total number of first bit lines in the first semiconductor die901, 1/N times the total number of second bit lines in the second semiconductor die902, and so on up to 1/N times the total number of N-th bit lines in the N-th semiconductor die.

Referring toFIGS. 19 and 20, a third alternative configuration of the first exemplary structure can be derived from any configuration of the first exemplary structure described above such that bit lines92between a bonded pair of semiconductor dies (901,902) are directly bonded to each other across the bonding interface. Thus, a bit line92within a first semiconductor die901may be bonded to a bit line92within a second semiconductor die902. In one embodiment, each bit line92within the first semiconductor die901may be bonded to a respective bit line92within the second semiconductor die902. Thus, in this alternative embodiment, extra bonding pads between respective bit lines are omitted.

Referring toFIGS. 21 and 22A, a fourth alternative configuration of the first exemplary structure can be derived from the third alternative configuration of the first exemplary structure by omitting formation of one or more peripheral circuits720. In this case, one or more of the bonded semiconductor dies may include a memory die800that does not include a peripheral circuit720. Optionally, one or more substrate semiconductor layer712may be omitted or removed. The allocation of drive load across remaining peripheral circuits720can be adjusted to accommodate omission of one or more peripheral circuits720. For example, if the bonded assembly includes N semiconductor dies (901,800) and if M peripheral circuits720(in which M is less than N) are present within the bonded assembly, then each word line driver circuit720W within a peripheral circuit720may be configured to drive 1/M times the total number of word lines within each semiconductor die simultaneously. N word lines from the N semiconductor dies can be connected to a same word line driver output node of a word line driver circuit720W. Alternatively or additionally, each bit line driver circuit720B within a peripheral circuit720may be configured to drive 1/M times the total number of bit lines92within each semiconductor die simultaneously. N bit lines from the N semiconductor dies can be connected to a same bit line driver output node of a bit line driver circuit720B. In this configuration, the select lines (e.g., source-side select lines46S or (“SGS”) and drain-side select lines46D (“SGD”)) in each semiconductor die (800,901) are electrically connected to the select line driver circuit720S separately.

In the configuration ofFIGS. 21 and 22A, the bit lines92of both semiconductor die (800,901) are bonded directly to each other without using intermediate bonding pads98. The bit lines92of the semiconductor die901are electrically connected to the bit line driver circuit720B of the same semiconductor die901. The bit lines92of the memory die800are electrically connected to the bit line driver circuit720B of the semiconductor die901through the respective bonded bit lines92of the semiconductor die901.

Referring toFIG. 22B, a fifth alternative configuration of the first exemplary structure can be derived from the fourth alternative configuration of the first exemplary structure by adding bonding pads98between the bit lines92of the bonded semiconductor die (800,901). In the configuration ofFIG. 22B, the bonding pads98of each respective semiconductor die (800,901) are bonded to each other to electrically connect the respective bit lines92of both semiconductor die (800,901) to each other and to the bit line driver circuit720B of the semiconductor die901.

As shown inFIG. 22B, the respective word lines46W in each semiconductor die (800,901) are electrically connected to each other through contact via structures86and bonding pads98and are connected in common to the same word line driver circuit720W. In contrast, the select lines (e.g., source-side select lines46S or (“SGS”) and drain-side select lines46D (“SGD”)) in each semiconductor die (800,901) are electrically connected to the select line driver circuit720S separately.

Thus, “n” effective word lines in the two semiconductor die (800,901) are split into n/2 word line parts46W located in the memory die800and n/2 word line parts46W located in the first semiconductor die901. However, the respective word lines e.g., word lines46W having the same number counting from the source-side select line in each die) are electrically connected to each other and are driven by the output node724(e.g., source or drain electrode) of the same word line switching transistor722of the word line driver circuit720W. Thus, the word line driver circuit effectively drives n/2 word lines due to the electrical connection of the respective word lines. This reduces the total area of the word line driver circuit720W in half compared to having n word lines in one semiconductor die being driven separately by a word line driver circuit in the same semiconductor die.

While the embodiments ofFIGS. 1 to 22Billustrate bonded assemblies of two or more semiconductor die, the sixth alternative configuration of the first exemplary structure shown inFIGS. 23A and 23Bincludes both the first peripheral circuit720and both the first three-dimensional memory array102and the second three-dimensional memory array104located in the same semiconductor die1000.

The semiconductor die1000can be derived from the first semiconductor die901ofFIG. 9by depositing a second three-dimensional memory array directly on a top surface of the distal dielectric material layers90of the first exemplary structure ofFIG. 9. In other words, the second three-dimensional memory array104provided in the second semiconductor die902inFIG. 10is deposited layer by layer directly on the top surface of the distal dielectric material layers90instead of bonding the second semiconductor die902to the first semiconductor die901.

Generally, a peripheral circuit720comprising field effect transistors722and dielectric material layers760embedding metal interconnect structures780on a top surface of a semiconductor substrate712. A first three-dimensional memory array102can be formed layer by layer over the peripheral circuit720. The first three-dimensional memory array102includes a first alternating stack of first insulating layers32and first electrically conductive layers46of first word lines and first select lines, and first memory stack structures55vertically extending through the first alternating stack (32,46) can be formed by deposition and patterning of material portions over the peripheral circuit720. A second three-dimensional memory array104is formed layer by layer over the first three-dimensional memory array102. The second three-dimensional memory array104includes a second alternating stack of second insulating layers32and second electrically conductive layers46of second word lines and second select lines, and second memory stack structures55vertically extending through the second alternating stack (32,46) can be formed. Word line driver output nodes724of the peripheral circuit720are electrically connected to the first word lines of first electrically conductive layers46and to a second word lines of the second electrically conductive layers46.

In one embodiment, a first retro-stepped dielectric material portion65A can be formed such that the first retro-stepped dielectric material portion65A contacts first stepped surfaces of the first alternating stack of the first insulating layers32and the first electrically conductive layers46. First contact via structures (such as the through-dielectric contact via structures84) can vertically extend through the first retro-stepped dielectric material portion65A directly on a respective one of the first electrically conductive layers46within the first alternating stack (32,46). A second retro-stepped dielectric material portion65B can be formed the second retro-stepped dielectric material portion65B contacts second stepped surfaces of the second alternating stack of the second insulating layer32and the second electrically conductive layers46. Second contact via structures (such as the through-dielectric contact via structures84) can be formed through the second retro-stepped dielectric material portion65B directly on a respective one of the second electrically conductive layers46.

Referring toFIGS. 1-23Band according to the first embodiment of the present disclosure, a semiconductor structure includes a first peripheral circuit720comprising field effect transistors722and dielectric material layers760embedding metal interconnect structures780. As shown inFIGS. 16A, 16B, 20, 22A, 22B and 23B, a first three-dimensional memory array102overlies the first peripheral circuit720and includes a first alternating stack of first insulating layers32and first electrically conductive layers46comprising first word lines46W and first select lines (46S,46D), and first memory stack structures55vertically extending through the first alternating stack. A second three-dimensional memory array104overlies the first three-dimensional memory array102and includes a second alternating stack of second insulating layers32and second electrically conductive layers46comprising second word lines46W and second select lines (46S,46D), and second memory stack structures55vertically extending through the second alternating stack. The first peripheral circuit720comprises a first word line driver circuit720W having first word line driver output nodes724electrically connected to at least some of the first word lines46W and at least some of the second word lines46W, and wherein each first word line is electrically connected to a respective second word line.

In one embodiment, each first word line driver output node724within a subset of the first word line driver output nodes is electrically connected to a respective word line switching transistor722, is electrically connected to a respective first word line46W, and is electrically connected to a respective second word line46W.

In one embodiment, the first peripheral circuit720further comprises a first select line driver circuit720S comprising first select line driver output nodes electrically connected to the first select lines (46S,46D) in the first array102and not electrically connected to any of the second electrically conductive layers46in the second array104, and second selective line driver output nodes electrically connected to the second select lines (46S,46D in the second array104, and not electrically connected to any of the first electrically conductive layers46in the first array102. The first select line driver output nodes comprise source-side select line driver output nodes electrically connected to source-side select lines46S of the first select lines and drain-side select line driver output nodes electrically connected to drain-side select lines46D of the first select lines in the first array102.

In one embodiment, each of the first memory stack structures55comprises a respective first vertical semiconductor channel60and a respective first vertical stack of memory elements in the second memory film50, and each of the second memory stack structures55comprises a respective second vertical semiconductor channel60and a respective second vertical stack of memory elements in the second memory film50. The first three-dimensional memory array102further comprises first bit lines92electrically connected to a first end of a respective subset of the first vertical semiconductor channels60, and the second three-dimensional memory array104further comprises second bit lines92electrically connected to a first end of a respective subset of the second vertical semiconductor channels60. The first peripheral circuit720further comprises a first bit line driver circuit720B having first bit line driver output nodes electrically connected to a respective one of the first bit lines92and to a respective one of the second bit lines92.

In one embodiment, the first peripheral circuit720and the first three-dimensional memory array102are located in a first semiconductor die901, and the second three-dimensional memory array104is located in a second semiconductor die (800,902) which is bonded to the first semiconductor die901. The first semiconductor die901further comprises first dielectric material layers760embedding first metal interconnect structures780and first metal bonding pads98, and the second semiconductor die (800,902) further comprises second dielectric material layers780embedding second metal interconnect structures760and second metal bonding pads98which are bonded to respective first metal bonding pads98.

In the configuration shown inFIGS. 21 to 22B, the first word line driver output nodes724of the first word line driver circuit720W are electrically connected all of the first word lines46W of the first semiconductor die901and to all of the second word lines46of the second semiconductor die (800,902) through a subset of mating pairs of the first metal bonding pads98and the second metal bonding pads98.

In contrast, in the configuration shown inFIGS. 14 to 20, the second semiconductor die902further comprises a second peripheral circuit720comprising a second word line driver circuit720W having second word line driver output nodes724. The first word line driver output nodes of the first word line driver circuit are electrically connected to a first subset of the first word lines46W in the first semiconductor die901and to a first subset of the second word lines46W in the second semiconductor die902through a first subset of mating pairs of the first metal bonding pads and the second metal bonding pads98. The second word line driver output nodes724of the second word line driver circuit720W are electrically connected to a second subset of the second word lines46W in the second semiconductor die902and to a second subset of the first word lines46W through a second subset of mating pairs of the first metal bonding pads and the second metal bonding pads98.

In the configuration shown inFIGS. 14 to 20, the first peripheral circuit720further comprises a first select line driver circuit720S comprising first select line driver output nodes electrically connected to the first select lines (46S,46D) in the first semiconductor due901and not electrically connected to any of the second electrically conductive layers46in the second semiconductor die902. The second peripheral circuit720further comprises a second select line driver circuit720S comprising second select line driver output nodes electrically connected to the second select lines (46S,46D) in the second semiconductor die902and not electrically connected to any of the first electrically conductive layers46in the first semiconductor die901.

In one embodiment, the first three-dimensional memory array102comprises first bit lines92electrically connected to a first end of a respective subset of the first vertical semiconductor channels60, and the second three-dimensional memory array104comprises second bit lines92electrically connected to a first end of a respective subset of the second vertical semiconductor channels60and electrically connected to the respective first bit lines. The first peripheral circuit further comprises a first bit line driver circuit720B having first bit line driver output nodes electrically connected to a first subset of the first bit lines and to a first subset of the second bit lines, and the second peripheral circuit further comprises a second bit line driver circuit720B having second bit line driver output nodes electrically connected to a second subset of the first bit lines and to a second subset of the second bit lines. In the embodiment shown inFIGS. 20 and 22A, each one of the second bit lines is bonded to a respective one of the first bit lines by metal-to-metal bonding.

In the embodiment ofFIG. 18, the structure further comprises a third semiconductor die903comprising a third three-dimensional memory array including a third alternating stack of third insulating layers and third electrically conductive layers comprising third word lines and third select lines, and third memory stack structures vertically extending through the third alternating stack, a third peripheral circuit comprising a third word line driver circuit, and third dielectric material layers embedding third metal interconnect structures and third metal bonding pads. The first word line driver output nodes724are electrically connected to at least some of the third word lines.

Referring toFIG. 24, a first semiconductor die801according to a second embodiment of the present disclosure can be derived from the first semiconductor die901described with reference toFIG. 9by employing a first handle substrate610in lieu of a combination a first substrate including a substrate semiconductor layer712, a first peripheral circuit720, and first proximal dielectric material layers760embedding first proximal metal interconnect structures780. In this case, the through-stack contact via structures82and the through-dielectric contact via structures84can be omitted. The first semiconductor die801may be a memory die.

Generally, a first semiconductor die801comprising a first three-dimensional memory array102is provided. The first three-dimensional memory array102includes a first alternating stack of first insulating layers32and first electrically conductive layers46comprising word lines and select lines, and first memory stack structures55vertically extending through the first alternating stack (32,46). Each of the first memory stack structures55comprises a respective first vertical semiconductor channel60and a respective first vertical stack of memory elements in a memory film50. The first three-dimensional memory array102can comprise first bit lines92electrically connected to a first end of a respective subset of the first vertical semiconductor channels60.

Referring toFIG. 25, a logic die700can be provided, which can be derived from the first semiconductor die901illustrated inFIG. 1by modifying design layouts for the through-substrate connection structures730and by forming metal bonding pads778within a topmost layer of the proximal dielectric material layers760. The pattern of the through-substrate connection structures730and the pattern of the metal bonding pads778can be selected to facilitate bonding with other semiconductor dies (such as the first semiconductor die801) in subsequent processing steps.

The peripheral circuit720can comprise complementary metal oxide semiconductor (CMOS) transistors722. The peripheral circuit720can comprise proximal metal interconnect structures780embedded within the proximal dielectric material layers760. According to an aspect of the present disclosure, the peripheral circuit720comprises first word line driver circuit720W containing word line driver output nodes724that are configured to be subsequently electrically connected to a first subset of the first electrically conductive layers (i.e., first word lines) in the first three-dimensional memory array102ofFIG. 23and to be subsequently electrically connected to a first subset of the second electrically conductive layers (i.e., second word lines) in a second three-dimensional memory array104to be described below.

In one embodiment, the peripheral circuit720can comprise first select line driver circuit720S containing select line driver output nodes that are configured to be electrically connected to a subset of the first electrically conductive layers (i.e., first select lines) of the first three-dimensional memory array and to be electrically isolated from each of the second electrically conductive layers of the second three-dimensional memory array.

In one embodiment, the first select line driver output nodes may include first source-side select line driver output nodes that are configured to be electrically connected to source-side select lines of the first electrically conductive layers of the first three-dimensional memory array102. In one embodiment, the first select line driver output nodes may include first drain-side select line driver output nodes that are configured to be electrically connected to drain-side select lines of the first electrically conductive layers of the first three-dimensional memory array102.

In one embodiment, the peripheral circuit720can comprise a first bit line driver circuit720B having first bit line driver output nodes configured to be electrically connected to, and to drive, a first subset of the first bit lines92in the first three-dimensional memory array102, and a second bit line driver circuit having second bit line driver output nodes configured to be electrically connected to, and to drive, a first subset of the second bit lines92in a second three-dimensional memory array104.

A second handling substrate620can be attached to the front surface of the logic die700.

Referring toFIG. 26, the substrate semiconductor layer712of the logic die700may be thinned. For example, the backside of the substrate semiconductor layer712of the logic die700can be thinned, for example, by grinding, polishing, an anisotropic etch process, and/or an isotropic etch process. In one embodiment, the backside of the substrate semiconductor layer712of the logic die700can be thinned until surfaces of the laterally-isolated through-substrate via structures734are physically exposed. The through-substrate connection structures730can vertically extend through the thinned substrate semiconductor layer712of the logic die700. Each through-substrate connection structure730can include a laterally-isolated through-substrate via structure734and a substrate insulating spacer732. A backside dielectric material layer790can be formed on the backside of the substrate semiconductor layer712of the logic die700, and backside bonding pads798can be formed in the backside dielectric material layer790. Each backside bonding pads798can be formed directly on a respective one of the laterally-isolated through-substrate via structure734.

Subsequently, the logic die700can be bonded to the first semiconductor die801, for example, by bonding the first metal bonding pads98of the first semiconductor die801to the backside bonding pads798of the logic die700.

Referring toFIG. 27A, the second handle substrate620can be detached from the logic die700. A second semiconductor die802can be provided, which can be manufactured in the same manner as the first semiconductor die801illustrated inFIG. 23with modifications in the pattern of the metal bonding pads98. Specifically, the pattern of the second metal bonding pads98in the second semiconductor die802can be a mirror image pattern of the pattern of the metal bonding pads778of the logic die.

The second semiconductor die802can be bonded to the logic die700, thereby forming a bonded assembly of the first semiconductor die801, the second semiconductor die802, and the logic die700(which is a third semiconductor die). Generally, wafer-to-wafer bonding may be employed. For example, a wafer including a plurality of first semiconductor dies801can be bonded to a wafer including a plurality of logic dies700. Subsequently, a wafer including a plurality of second semiconductor dies802can be bonded to the wafer including the plurality of logic dies700.

The first handle substrate610and any handle substrate (not illustrated) that may be employed to provide mechanical support to the second semiconductor die802up to the processing step of bonding with the logic die700can be subsequently removed.

Referring toFIG. 27B, the contact via structures82may extend through the word line driver circuit720W. The contact via structures82electrically connect the word line driver nodes to the respective bonding pads (778,798) of the logic die700.

Referring toFIGS. 24-27Band the second embodiment of the present disclosure, a bonded assembly comprises a first semiconductor die801comprising a first three-dimensional memory array102including a first alternating stack of first insulating layers32and first electrically conductive layers46comprising first word lines46W and first select lines (46S,46D), and first memory stack structures55vertically extending through the first alternating stack, a second semiconductor die802comprising a second three-dimensional memory array104including a second alternating stack of second insulating layers32and second electrically conductive layers46comprising second word lines46W and second select lines (46S,46D), and second memory stack structures55vertically extending through the second alternating stack, and a third semiconductor die700comprising a peripheral circuit720containing a word line driver circuit720W comprising word line driver output nodes724electrically connected to the first word lines46W and electrically connected to the second word lines46W. Each of the first word lines is electrically connected to a respective one of the second word lines.

In one embodiment, each word line switching transistor722of the word line driver circuit720W is electrically connected to a respective word line driver output node724. The respective word line driver output node724is electrically connected a respective first word line46W and is electrically connected to a respective second word line46W. The respective first word line46W is electrically connected to the respective second word line46W.

In one embodiment, the peripheral circuit further comprises a select line driver circuit720S. The select line driver circuit comprises source-side select line driver output nodes electrically connected to source-side select lines46S of the first select lines, and drain-side select line driver output nodes electrically connected to drain-side select lines46D of the first select lines.

In one embodiment, the first semiconductor die801comprises first metal bonding pads98embedded in first dielectric material layers90, the second semiconductor die802comprises second metal bonding pads98embedded in second dielectric material layers90, and the third semiconductor die700comprises third metal bonding pads798embedded in third dielectric material layers760. In one embodiment, electrical connections between the first semiconductor die, the second semiconductor die, and the third semiconductor die are provided by metal-to-metal bonding between the first metal bonding pads, the second metal bonding pads, and the third metal bonding pads.

In one embodiment, each of the first memory stack structures55comprises a respective first vertical semiconductor channel60and a respective first vertical stack of memory elements in a memory film50, each of the second memory stack structures55comprises a respective second vertical semiconductor channel60and a respective second vertical stack of memory elements in a memory film50, the first three-dimensional memory array102further comprises first bit lines92electrically connected to a first end of a respective subset of the first vertical semiconductor channels. the second three-dimensional memory array104comprises second bit lines92electrically connected to a first end of a respective subset of the second vertical semiconductor channels, and the peripheral circuit720further comprises a bit line driver circuit720B comprising bit line driver output nodes which are electrically connected to a respective one of the first or the second bit lines92.

The various embodiments of the present disclosure can be employed to provide a vertical stack of multiple three-dimensional memory arrays (102,104) that share a peripheral circuit720. A word line driver output node of the peripheral circuit720can drive multiple electrically connected word lines46W within the multiple three-dimensional memory arrays (102,104). For example, a word line driver output node724of the peripheral circuit720can drive a first word line46W in a first three-dimensional memory array102and a second word line46W in a second three-dimensional memory array104which is electrically connected to the first word line. The total area occupied by the word line driver circuit720W portion of the peripheral circuit720can be reduced by the word line driver circuit720W between electrically connected word lines46W that are vertically separated from each other in the multiple three-dimensional memory arrays (102,104).