SEMICONDUCTOR APPARATUS

Provided is a semiconductor apparatus comprising: an emitter region having a first conductivity type provided on a front surface of a semiconductor substrate; a first gate trench part and a second gate trench part in contact with the emitter region; a first emitter non-contact trench part and a second emitter non-contact trench part out of contact with the emitter region; a gate pad for setting the first gate trench part, the second gate trench part, the first emitter non-contact trench part, and the second emitter non-contact trench part to gate potential; and a diode having an anode connected to the gate pad and a cathode connected to the first emitter non-contact trench part and the second emitter non-contact trench part, wherein the first gate trench part, the first emitter non-contact trench part, the second gate trench part, and the second emitter non-contact trench part are adjacently arranged in order.

No. 2020-086231 filed in JP on May 15, 2020.

BACKGROUND

1. Technical Field

The present invention relates to a semiconductor apparatus.

2. Related Art

Patent Document 1 describes “Provided is a semiconductor apparatus that suppresses current for charging gate-emitter capacitor without going through a gate resistor and has improved controllability of dV/dt due to the gate resistor.”

PRIOR ART DOCUMENT

Patent Document

DESCRIPTION OF EXEMPLARY EMBODIMENTS

Hereinafter, the present invention will be described through embodiments of the invention, but the following embodiments do not limit the claimed invention. Moreover, not all combinations of features described in the embodiments are necessary to solutions of the invention.

As used herein, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as “upper”, and the other side “lower”. Moreover, out of two principal surfaces of a substrate, a layer, or other members, one surface is referred to as the “upper surface”, and the other surface the “lower surface”. “Upper” and “lower” directions are not limited to the direction of gravity, or a direction in which a semiconductor apparatus is mounted.

In this specification, technical matters may be described using orthogonal coordinate axes of an X axis, a Y axis, and a Z axis. The orthogonal coordinate axes merely specify relative positions of components, and do not limit a specific direction. For example, the Z axis direction is not limited to the height direction with respect to the ground, that is, the direction of gravity. In this specification, a surface parallel to a front surface of the semiconductor substrate represents an XY surface, and a direction that forms a right-handed system with the X axis and the Y axis and is the depth direction of the semiconductor substrate represents the Z axis Note that, as used herein, a case where the semiconductor substrate is viewed in the Z axis direction may be referred to as a “planar view”.

Each embodiment example shows an example where a first conductivity type is N type and a second conductivity type is P type. However, the first conductivity type may be P type and the second conductivity type may be N type. In this case, conductivity types of substrates, layers, regions, or the like in each embodiment example are of opposite polarity.

In this specification, it is meant that an electron or a hole is respectively a majority carrier in a layer or region labeled n or p. Moreover, a layer or region with + and − attached to n and p means to respectively have doping concentrations higher and lower than that of a layer or region without them attached; and a layer or region with ++ attached means to have a doping concentration higher than that of a layer or region with + attached, and a layer or region with −− attached means to have a doping concentration lower than that of a layer or region with − attached.

As used herein, a doping concentration refers to a concentration of a donor or an acceptorized dopant. Therefore, the unit is/cm3. A unit system herein is the SI unit system unless otherwise noted. Although a unit of length may be indicated in cm, calculations may be carried out after conversion to meters (m).

As used herein, concentration difference (that is, a net doping concentration) between a donor and an acceptor may be referred to as a doping concentration. In this case, the doping concentration can be measured by capacitance-voltage method (CV method), SR method, or the like. Moreover, a chemical concentration of the donor and the acceptor may also be a doping concentration. In this case, the doping concentration can be measured by SIMS method. Unless otherwise limited, any of the above may be used as a doping concentration. Unless otherwise limited, a peak value of doping concentration distribution in a doping region may be a doping concentration in said doping region. Each concentration herein may be a value at room temperature. As the value at room temperature, a value at 300K (Kelvin) (about 26.9 degrees C.) for example may be used.

FIG. 1Ais an example of a top view of a semiconductor apparatus100. The semiconductor apparatus100is a semiconductor chip according to an embodiment example. The semiconductor apparatus100in this example is an insulated gate bipolar transistor (IGBT). However, the semiconductor apparatus100is not limited to the IGBT, and may also be a vertical metal-oxide-semiconductor field effect transistor (VMOSFET) or a RC (reverse conducting)-IGBT.

A semiconductor substrate10may be a silicon substrate, a silicon carbide substrate, or a nitride semiconductor substrate such as gallium nitride or the like. The semiconductor substrate10in this example is a silicon substrate.

The semiconductor apparatus100includes, on the upper surface of the semiconductor substrate10, an edge termination structure part90, a gate pad50, a gate runner140going around inside the edge termination structure part90, an active region95provided inside the gate runner, and a gate metal layer145going around the outermost part of the active region95. The semiconductor apparatus100further includes a diode110having an anode connected to the gate pad50. The diode110in this example is provided adjacent to the gate pad50, but a position where the diode110is provided is not limited to this position.

The semiconductor apparatus100includes, on the upper surface of the semiconductor substrate10, the edge termination structure part90, the gate pad50, the gate runner140going around inside the edge termination structure part90, and the active region95provided inside the gate runner140. The semiconductor apparatus100further includes, on the outermost part of the active region95, the gate metal layer145going around the upper surface of the active region95.

The edge termination structure part90relaxes electric field concentration on the upper surface side of the semiconductor substrate10. The edge termination structure part90has a structure of, for example, a guard ring, a field plate, a RESURF, and a combination thereof.

The gate pad50is electrically connected to the diode110. The gate pad50is formed of material containing metal. At least a partial region of the gate pad50may be formed of aluminum, aluminum-silicon alloy, or aluminum-silicon-copper alloy. An emitter electrode52and the gate pad50may have, in a layer underlying a region formed of aluminum or the like, barrier metal formed of titanium, titanium compound, or the like.

In the diode110, a cathode electrode112described later is extended to be connected to the gate metal layer145. However, the cathode electrode112and the gate metal layer145may be integrally molded.

In this example, a gate trench part40and an emitter non-contact trench part130are arranged in the X direction. In particular, in this example, the gate trench part40and the emitter non-contact trench part130have an arrangement ratio of 1:1, and are alternately arranged.

The gate trench part40is electrically connected to the gate runner140. On the other hand, the emitter non-contact trench part130is electrically connected to the gate metal layer.

On a front surface of the semiconductor substrate10, the gate runner140goes around inside the gate pad50and the diode110and outside the active region95and the gate metal layer145. That is, the gate runner140may be provided between the gate pad50and a plurality of trench parts. The gate runner140is electrically connected to the gate pad50. The gate runner140in this example is formed of polysilicon.

The gate metal layer145goes around inside the gate runner140. On the front surface of the semiconductor substrate10, the gate metal layer145goes around the outermost part of the active region95. The gate metal layer145may be a wiring layer formed of metal.

FIG. 1Bis an example of a cross-sectional view of the semiconductor apparatus100. The semiconductor apparatus100in this example includes an N+ type emitter region12provided on the front surface of a semiconductor substrate10. Further, the semiconductor apparatus100includes four trench parts arranged in the X axis direction.

The semiconductor apparatus100includes two gate trench parts40, two emitter non-contact trench parts130, an emitter electrode52, an interlayer dielectric film38, and a contact hole54. The semiconductor apparatus100further includes a mesa part62between the gate trench part40and the emitter non-contact trench part130.

The semiconductor substrate10includes therein a P+ type collector region22, an N− type drift region18laminated above the collector region22, a P− type base region14provided above the drift region18, a P+ type contact region15provided above the base region14, and an N+ type emitter region12provided above the base region14. In the semiconductor substrate, the base region14may be provided in contact with and below the emitter region12, and the drift region18may be provided in contact with and below the base region14. However, when the semiconductor apparatus100is a VMOSFET, the collector region22may be omitted.

In the semiconductor apparatus100of this example, the base region14is in contact with the drift region18. In an IGBT device, in order to improve Injection Enhancement effect of a carrier, an N type storage region having a doping concentration higher than that of the drift region18may be provided between the base region14and the drift region, but in this example, no storage region is provided. This allows gate voltage to rise gently, and can avoid excessive electric field concentration, overcurrent density, and a high switching loss in the mesa part62.

The semiconductor apparatus100includes, in order from the negative side to the positive side in the X axis direction, the emitter non-contact trench part130out of contact with the emitter region12, the gate trench part40in contact with the emitter region12, and the emitter non-contact trench part130, and the gate trench part40. These trench parts are, in order from the negative side in the X axis direction to the positive side in the X axis direction, an example of a first emitter non-contact trench part130, a first gate trench part40, a second emitter non-contact trench part130, and a second gate trench part40.

The semiconductor apparatus100includes a gate terminal G for setting the two gate trench parts40and the two emitter non-contact trench parts130to gate potential Vg. The gate terminal G is a terminal for externally connecting the semiconductor apparatus100, and the gate pad50is an example of the gate terminal G. However, the gate terminal G only needs to be an external connection terminal, and is not limited to a pad.

The semiconductor apparatus100includes the emitter electrode52above the trench parts. The emitter electrode52is set to emitter potential Ve. The emitter potential Vemay be set to ground potential.

On the front surface of the semiconductor substrate10, the emitter region12is extended from the gate trench part40provided on the most negative side of the X axis, to a direction of the adjacent emitter non-contact trench part130on the positive side of the X axis. The emitter region12is terminated without reaching said emitter non-contact trench part130.

On the front surface of the semiconductor substrate, the emitter region12is extended from the gate trench part40arranged in the third position from the negative side of the X axis, to a direction of the adjacent emitter non-contact trench part130on the negative side of the X axis. The emitter region12is terminated without reaching said emitter non-contact trench part130.

On the front surface of the semiconductor substrate, the emitter region12is extended from the gate trench part40arranged in the third position from the negative side of the X axis, to the direction of the adjacent emitter non-contact trench part130on the positive side of the X axis. The emitter region12is terminated without reaching said emitter non-contact trench part130.

The interlayer dielectric film38insulates conductive parts inside the different trench parts and the emitter electrode52. The interlayer dielectric film38may cover the upper part of each trench part. The contact hole54is provided so as to penetrate the interlayer dielectric film38.

The gate trench part40includes a gate dielectric film42and a gate conductive part44. The gate conductive part44is electrically connected to the gate pad50, and is set to the gate potential Vg. The gate potential Vgmay be potential higher than the emitter potential Ve. In the mesa part62, an NPN structure is formed in a region in contact with the gate dielectric film42, by the emitter region12, the base region14, and the drift region18. Therefore, when the gate conductive part44is set to the gate potential Vg, an N type channel is formed in the base region14and operates as a transistor.

The emitter non-contact trench part130includes an emitter non-contact trench dielectric film132and an emitter non-contact trench conductive part134. The emitter non-contact trench conductive part134is also electrically connected to the gate pad50, and is set to the gate potential Vg. However, the emitter non-contact trench part130is out of contact with the emitter region12. On the front surface of the semiconductor substrate10, the emitter non-contact trench part130is in contact with the base region14or the contact region15. Therefore, in the mesa part62, even if the emitter non-contact trench conductive part134is set to the gate potential Vg, no channel is formed around the emitter non-contact trench part130or operates as a transistor.

FIG. 2Ashows an example of a cross-sectional view of a semiconductor apparatus200. The semiconductor apparatus200is a part of the semiconductor apparatus100.

The semiconductor apparatus200includes three trench parts arranged in the X axis direction: an emitter non-contact trench part130, a gate trench part40, and an emitter non-contact trench part130.

The semiconductor apparatus200includes diodes110between the emitter non-contact trench parts130and a gate terminal G. The diodes between the emitter non-contact trench parts130and the gate terminal G may be the same or different diodes.

FIG. 2Bshows an example of an equivalent circuit diagram of the semiconductor apparatus200. In this example, a diode110is provided between a gate capacitor of an emitter non-contact trench part130and a gate terminal G.

The emitter non-contact trench part130is equivalent to a diode including a gate capacitor to be charged and a parasitic capacitor. The gate capacitor to be charged of the emitter non-contact trench part130is electrically connected to a cathode of the diode110. An anode of the diode110is electrically connected to the gate terminal G.

The diode110prevents current from flowing back from the gate capacitor of the emitter non-contact trench part130to the gate terminal G. This improves, in operation at the time of switching on of an IGBT, a charging speed of the emitter non-contact trench part130. Therefore, potential of a mesa part62can be quickly increased, and operation of the entire semiconductor apparatus100is accelerated. This reduces a time rate of change dVC/dt in emitter-collector voltage of the IGBT and a switching-on power loss.

In this example, voltage between gate capacitors of the emitter non-contact trench part130is set to VG1, and voltage around the parasitic capacitor of the emitter non-contact trench part130is set to VG2.

FIG. 2Cshows current and voltage waveforms at the time of switching of the semiconductor apparatus200. Emitter-collector voltage VC, emitter-collector current IC, and potential VGof a gate conductive part44are shown.

VG2is higher than VG1from a start of driving, since presence of a diode110prevents a carrier from flowing back to a gate terminal G. This accelerates a start of switching-on operation, and causes the VCand the ICto perform stable start-up operation with less vibration. Therefore, a switching-on power loss expressed as a product of the VCand the ICis reduced.

FIG. 3Ashows an example of a cross-sectional view of a semiconductor apparatus300according to a comparative example 1. The semiconductor apparatus300includes three trench parts arranged in the X axis direction: a dummy trench part30, a gate trench part40, and a dummy trench part30.

The semiconductor apparatus300includes, in a semiconductor substrate10, a mesa part60between the dummy trench part30and the gate trench part40. The dummy trench part30in this example is in contact with a contact region15, but the dummy trench part30may be in contact with an emitter region12.

The dummy trench part30includes a dummy dielectric film32and a dummy conductive part34. The dummy conductive part34is electrically connected to an emitter terminal E, and is set to emitter potential Ve. Since no gate voltage is applied to the dummy trench part30, no channel is formed in a region of the mesa part60in contact with the dummy trench part30.

FIG. 3Bshows an example of an equivalent circuit diagram of the semiconductor apparatus300according to the comparative example 1. The example inFIG. 2Band this example are different in connection relationship between the gate terminal G and the emitter terminal E, and the gate capacitor and the parasitic capacitor of the dummy trench part30, and in presence/absence of the diode110between the gate terminal G and the gate capacitor of the dummy trench part30.

FIG. 3Cshows an example of current and voltage waveforms at the time of switching of the semiconductor apparatus300according to the comparative example 1. In the semiconductor apparatus300, since it can be driven even without increasing potential of the dummy conductive part34to the gate potential Vg, switching-on start timing is accelerated. On the other hand, inclination of emitter-collector voltage VCand amplitude of emitter-collector current ICis increased. This increases a switching-on power loss.

FIG. 4Ashows an example of a cross-sectional view of a semiconductor apparatus400according to a comparative example 2. The semiconductor apparatus400includes an emitter non-contact trench part130, a gate trench part40, and an emitter non-contact trench part130, arranged from the negative side in the X axis direction to the positive side in the X axis direction. The semiconductor apparatus400in this example is different from the semiconductor apparatus100in that it has no diode110connected between a gate terminal G and an emitter non-contact trench conductive part134.

FIG. 4Bshows an example of an equivalent circuit diagram of the semiconductor apparatus400according to the comparative example 2. In order to drive the semiconductor apparatus400, three gate capacitors: a gate capacitor of the gate trench part40and gate capacitors of the two emitter non-contact trench parts130are charged.

FIG. 4Cshows an example of current and voltage waveforms at the time of switching of the semiconductor apparatus400according to the comparative example 2. In the semiconductor apparatus400, since it is driven after the three gate capacitors are charged, rise of potential VGof a gate conductive part44is delayed compared to those in the semiconductor apparatus200and the semiconductor apparatus300. Moreover, switching-on start timing corresponding to timing when emitter-collector voltage VCstarts to drop is also delayed.

That is, in the semiconductor apparatus100, the potential VGof the gate conductive part44rises more quickly and the switching-on start timing is earlier than that in the semiconductor apparatus400where the emitter non-contact trench part130is provided without providing a diode110, and a switching-on power loss can be smaller than that in the semiconductor apparatus300.

FIG. 5shows another example of the cross-sectional view of the semiconductor apparatus100. The diode110may be a float diode formed on the same chip as the semiconductor apparatus100and having a PN junction of the diode110formed above an oxide film117.

The diode110includes a second conductivity type well region11provided above the drift region18, the oxide film117covering the upper surface of the well region11, and an N type cathode diffusion region113and a P type anode diffusion region115that are formed above the oxide film. The cathode diffusion region113may be connected to the cathode electrode112via a contact hole or the like, and the anode diffusion region115may be connected to an anode electrode114via a contact hole or the like. In this example, the anode diffusion region115and the anode electrode114constitute an anode of the diode110, and the cathode diffusion region113and the cathode electrode112constitute a cathode of the diode110.

The oxide film117has thickness equal to or greater than a predetermined threshold value. Giving thickness to the oxide film117can reduce parasitic capacitance between the cathode diffusion region113and the anode diffusion region115, and the well region11. Moreover, providing a thick oxide film can suppress generation of leak current from the well region11.

As an example, the oxide film117may be a LOCOS oxide film provided by forming a recess on the semiconductor substrate10. Making the oxide film117a LOCOS oxide film can facilitate giving thickness to the oxide film117and can flatten its surface, so that flexibility in design can be improved.

FIG. 6Ashows an example of a top view of the diode110. The diode110includes a PN junction portion embedded in an interlayer dielectric film38. A PN junction is formed between the cathode diffusion region113and the anode diffusion region115.

FIG. 6Bshows another example of a cross-sectional view of the diode110. In this example, the anode diffusion region115is formed above the cathode diffusion region113. That is, the PN junction of the diode110is joined in the vertical direction.

FIG. 7Ashows yet another example of the cross-sectional view of the diode110. The diode110in this example includes three cathode diffusion regions113and three anode diffusion regions115.

In this example, from the negative side in the X axis direction to the positive side in the X axis direction, the anode diffusion region115provided in the first position and the cathode diffusion region113provided in the second position are electrically connected via a contact hole or the like and a connection part119or the like. Likewise, from the negative side in the X axis direction to the positive side in the X axis direction, the anode diffusion region115provided in the second position and the cathode diffusion region113provided in the third position are electrically connected via the connection part119.

In this example, shown is an example of a three-stage diode110where the number of PN junctions is three, but the number of stages is not limited to three. Depending on a desired capacitance provided to the emitter non-contact trench part130, the number of stages may be two, or may be increased to even more.

FIG. 7Bshows another example of the top view of the diode110. This example is an example in planar view of the diode110inFIG. 7A.

As in this example, the connection part119may be provided so as to be narrower than the cathode diffusion region113and the anode diffusion region115. On the contrary, it may be provided so as to be wider than the cathode diffusion region113and the anode diffusion region115.

FIG. 8shows an example of an enlarged view of the upper surface of the semiconductor apparatus100. This example is an example of an enlarged view of a region B inFIG. 1A.

In this example, the diode110is provided adjacent to the gate pad50. The anode electrode114of the diode110in this example is electrically connected to the gate pad50. On the other hand, the cathode electrode112of the diode110in this example is extended to the active region95, and is electrically connected to the gate metal layer145.

The diode110may be a Zener diode. The diode110can be designed as a Zener diode by increasing doping concentrations of the anode diffusion region115and the cathode diffusion region113of the diode110. The Zener diode can provide a better rectification characteristic for reverse current.

The gate runner140is provided so as to overlap the gate pad50. The gate runner140is electrically connected to the gate pad50through a contact hole59, and is set to the gate potential Vg.

The gate trench part40is provided so as to overlap the gate runner140in planar view. The gate trench part40is electrically connected to the gate runner140through a contact hole56. The gate conductive part44of the gate trench part40is set to the gate potential Vg.

The emitter non-contact trench part130is provided so as to overlap the gate metal layer145in planar view. The emitter non-contact trench part is electrically connected to the gate metal layer145through a contact hole58. The emitter non-contact trench conductive part134of the emitter non-contact trench part130is set to the gate potential Vg. That is, the emitter non-contact trench part130is connected to the gate pad50via the diode110.

FIG. 9Ashows another example of the top view of the semiconductor apparatus100. In this example, the gate runner140includes two layers: an outer peripheral gate runner142and an inner peripheral gate runner144. Moreover, the gate pad50is connected to the gate metal layer145.

The outer peripheral gate runner142is electrically connected to the gate pad50. As an example, the outer peripheral gate runner142is formed of a P type semiconductor. The outer peripheral gate runner142is an example of an anode peripheral region.

As an example, the inner peripheral gate runner144is formed of an N type semiconductor. The inner peripheral gate runner144is an example of a cathode peripheral region. That is, in this example, a PN junction is formed between the outer peripheral gate runner142and the inner peripheral gate runner144in the gate runner140. In this case, the diode110is provided in the gate runner140, an anode of the diode110includes the outer peripheral gate runner142, and a cathode of the diode110includes the inner peripheral gate runner144.

The emitter non-contact trench part130is electrically connected to the inner peripheral gate runner140. That is, the emitter non-contact trench part130is electrically connected to the gate pad50via the diode110.

The gate trench part40is electrically connected to the gate metal layer145. That is, the gate trench part40is electrically connected to the gate pad50via the gate metal layer145.

FIG. 9Bshows another example of the enlarged view of the upper surface of the semiconductor apparatus100. This example is an example of an enlarged view of a region C inFIG. 9A.

The outer peripheral gate runner142is electrically connected to the gate pad50and the gate metal layer145via the contact hole59. The gate runner140and the gate metal layer145is set to the gate potential Vg.

The inner peripheral gate runner144forms a PN junction with the outer peripheral gate runner142. The inner peripheral gate runner144in this example is formed of N type polysilicon, and the inner peripheral gate runner144is integrally formed with at least one emitter non-contact trench conductive part134of a plurality of emitter non-contact trench parts130. That is, the emitter non-contact trench conductive part134in this example is formed of N type polysilicon.

FIG. 9Cshows an example of a cross-sectional view in an extending direction of a trench part of the semiconductor apparatus100. In this example, the emitter non-contact trench conductive part134of the emitter non-contact trench part130and the inner peripheral gate runner144of the diode110are integrally formed.

The emitter non-contact trench conductive part134rides on the upper part of the oxide film117, and goes around the periphery of the active region95as the inner peripheral gate runner144. Further, the outer peripheral gate runner142going around outside the inner peripheral gate runner144constitutes a PN junction with the inner peripheral gate runner144.

The interlayer dielectric film38covers the upper parts of the outer peripheral gate runner142, the inner peripheral gate runner144, and the emitter non-contact trench part130. The contact hole59is provided inside the interlayer dielectric film38above the outer peripheral gate runner142, and electrically connects the gate pad50, the gate metal layer145, and the outer peripheral gate runner142.

FIG. 10Ashows an example of a cross-sectional view of a semiconductor apparatus500. The semiconductor apparatus500includes three trench parts. The semiconductor apparatus500in this example includes, from the negative side to the positive side in the X axis direction, an emitter non-contact trench part130, a gate trench part40, and a dummy trench part30.

FIG. 10Bshows an example of a diagram of equipotential lines in the cross-sectional view of the semiconductor apparatus500. In this example, shown is an example where, when the semiconductor apparatus500is an IGBT device, gate resistance is 5Ω), gate voltage is 12.7 [V], and emitter-collector voltage is 409 [V].

In the emitter non-contact trench part130, as potential of a gate conductive part of the gate trench part40is increased, voltage of the emitter non-contact trench conductive part134is also increased. Therefore, equipotential lines in a mesa part62are extended between the emitter non-contact trench part130and the gate trench part40. While the potential of the gate conductive part is increased, the equipotential lines remain extended between the trenches, and potential of the mesa part62is increased.

On the other hand, a dummy conductive part34of the dummy trench part30has emitter potential Ve. For example, when VEis ground potential, even if the potential of the gate conductive part44of the gate trench part40is increased, the emitter potential Vedoes not change from the ground potential before and after the increase.

Therefore, in a mesa part60between the dummy trench part30and the gate trench part40, equipotential lines are extended in a direction substantially parallel to the depth direction of the semiconductor apparatus500. In the vicinity of the dummy trench part30, the emitter potential Veis fixed near the ground potential from the front surface of the semiconductor substrate10to the bottom of the dummy trench part30. Therefore, in the mesa part60, a lateral electric field is generated, and potential increase becomes slow. This causes a delay of turn-on end time in the mesa part60around the dummy trench part30.

FIG. 10Cshows an example of a contour diagram of a current value in the cross-sectional view of the semiconductor apparatus500. In this example again, shown is an example where, when the semiconductor apparatus500is an IGBT device, gate resistance is 5Ω), gate voltage is 12.7 [V], and emitter-collector voltage is 409 [V]. In the figure, a range where the current value has a value equal to or greater than a certain threshold value is filled in black.

In the mesa part62between the emitter non-contact trench part130and the gate trench part40, as the potential is increased, the current value is also increased spreading to the mesa part62. In the mesa part62, the current is also increased spreading entirely inside the mesa part62.

On the other hand, in a second mesa part60of the dummy trench part30and the gate trench part40, a region where current flows is concentrated in the vicinity of the gate trench part40where a channel is formed in a base region14. Therefore, the current flowing through the mesa part60is more likely to cause current concentration than the current flowing through the mesa part62, and the biased current not only destabilizes switching-on operation but also increases switching-on power loss.

FIGS. 11A to 13Bshow graphs at the time of turn-on operation when gate input waveforms are the same.

FIG. 11Ashows an example of current and voltage waveforms at the time of switching of the semiconductor apparatus500. In this example, shown is a graph where, when the semiconductor apparatus500is an IGBT device, gate resistance is set to 1×RG [Ω], wherein the RG [Ω] is an arbitrary resistance value.

Emitter-collector voltage VC, emitter-collector current IC, and potential VGof the gate conductive part44are shown. In this example, the emitter-collector voltage VCis sharply reduced, and the emitter-collector current ICalso sharply rises. Since a power loss PCper unit time at the time of switching is given by a product of the VCand the IC, it contributes greatly to an amount of change in the absolute value of the PC.

FIG. 11Bshows an example of a graph of a power loss per unit time at the time of switching of the semiconductor apparatus500. The larger an area surrounded by a straight line of PC=0 [W] and a curve drawn by the PCis, the greater a value of the power loss is.

FIG. 12Ashows another example of the current and voltage waveforms at the time of switching of the semiconductor apparatus300. In this example, shown is a graph, where, when the semiconductor apparatus300is an IGBT device, gate resistance is set to 1×RG [Ω], wherein the RG [Ω] shown inFIG. 12Ais the same resistance value as the RG [Ω] shown inFIG. 11A.

In this example, emitter-collector voltage VCis sharply reduced, but as it approaches a value of 0V, it gets gently reduced and time required for the turn-on operation becomes longer. This is because the mesa part between the gate trench part40and the dummy trench part30has a lateral electric field, and the dummy conductive part34of the dummy trench part30has the emitter potential Ve, so that operation of lowering potential of the entire mesa part becomes slow.

Moreover, in this example, turn-on start timing is early, emitter-collector current ICis operating current, and the emitter-collector current ICis also large. Therefore, a power loss PCper unit time at the time of turn-on is larger.

FIG. 12Bshows an example of a graph of a power loss per unit time at the time of switching of the semiconductor apparatus300. In this example, since the emitter-collector voltage VCis more gently decreased than that in the example of the semiconductor apparatus500, a value of the PCis more slowly decreased and switching time is longer. Therefore, an integrated value over time of the PCis also greater than that in the example of the semiconductor apparatus500.

FIG. 13Ashows another example of the current and voltage waveforms at the time of switching of the semiconductor apparatus200. In this example, shown is a graph where, when the semiconductor apparatus300is an IGBT device, gate resistance is set to 1×RG [Ω], wherein the RG [Ω] shown inFIG. 13Ais the same resistance value as the RGs [Ω] shown inFIGS. 11A and 12A.

In this example, the VCis stably and linearly reduced to complete the switching-on operation. Since the VCis slowly decreased, switching time is increased, and a power loss PCat the time of turn-on is larger. However, the maximum value of dV/dt can be significantly reduced.

FIG. 13Bshows an example of a graph of power loss per unit time at the time of switching of the semiconductor apparatus200. In the graph ofFIG. 13B, an integrated value over time of the absolute value of the PCis greater than that in the example of the semiconductor apparatus300.

FIG. 14shows an example of a graph of switching losses of the semiconductor apparatus200, the semiconductor apparatus300, and the semiconductor apparatus500. In this example, shown is a graph where the horizontal axis represents the maximum value of dV/dt [a.u.] (arbitrary unit) and the vertical axis represents an on-state power loss Eon [J] at the time of switching.

The semiconductor apparatus200includes the gate trench part40and the emitter non-contact trench part130. That is, a ratio of the dummy trench part30and the emitter non-contact trench part130included in the semiconductor apparatus200is 0:1. The semiconductor apparatus300includes the dummy trench part30and the emitter non-contact trench part130at a ratio of 1:0. The semiconductor apparatus500includes the dummy trench part30and the emitter non-contact trench part130at a ratio of 1:1. Magnitudes of the switching losses of the semiconductor apparatus300and the semiconductor apparatus500are larger than that of the semiconductor apparatus200. In particular, this is noticeable on the side where dV/dt [a.u.] is higher.

In the mesa part60between the dummy trench part30and the gate trench part40, operating waveform is steep and turn-on end time is delayed. Therefore, when the emitter non-contact trench part130and the dummy trench part30coexist, the higher a ratio of a dummy gate is, the larger a turn-on power loss is. As an example the semiconductor apparatus100includes the gate trench part40and the emitter non-contact trench part130at a ratio of 1:1, and includes no dummy trench part30. When the semiconductor apparatus100includes all of the gate trench part40, the emitter non-contact trench part130, and the dummy trench part30, it includes the dummy trench part30and the emitter non-contact trench part130at a ratio of x:1, where x may be a value smaller than 1.

FIG. 15shows an example of a cross-sectional view of a semiconductor apparatus600according to a comparative example. The semiconductor apparatus600includes an N type storage region71between an N− type drift region18and a P− type base region14provided above the drift region18. The storage region71has a doping concentration higher than that of the drift region18.

FIG. 16shows an example of a cross-sectional view of a semiconductor apparatus700according to a comparative example. The semiconductor apparatus700includes an N− type storage region72between an N− type drift region18and a P− type base region14provided above the drift region18. The storage region72has a doping concentration higher than that of the drift region18.

The semiconductor apparatus700in this example is different from the semiconductor apparatus500in that it includes the storage region72having a doping concentration different from that of the storage region71. The storage region72has a doping concentration lower than that of the storage region71.

FIG. 17shows an example of a graph of switching losses of the semiconductor apparatus200, the semiconductor apparatus600, and the semiconductor apparatus700. In this example, shown is a graph where the horizontal axis represents the maximum value of dV/dt [a.u.] and the vertical axis represents an on-state power loss Eon [J] at the time of switching. This example shows a graph at room temperature RT (25 degrees C.).

The semiconductor apparatus200is the semiconductor apparatus200shown inFIG. 2B, and includes no N type storage region. The semiconductor apparatus600is the semiconductor apparatus600shown inFIG. 15. Moreover, the semiconductor apparatus700is the semiconductor apparatus700shown inFIG. 16. The semiconductor apparatus600and the semiconductor apparatus700include respectively the storage region71and the storage region72having different doping concentrations.

FIG. 18shows an example of a graph of a doping concentration of a storage region and a switching loss. In this example, shown is a graph where the horizontal axis represents the doping concentration [a.u.] of the storage region, the vertical axis represents the maximum value of dV/dt [a.u.], and gate resistance Rgis 1×RG [Ω], 2× RG [Ω], or 3× RG [Ω].

As the doping concentration [a.u.] of the storage region becomes higher, the maximum value of dV/dt [a.u.] is increased. Moreover, as the gate resistance Rgis lower, the maximum value of dV/dt [a.u.] is significantly increased.

FIG. 19Ashows an example of current and voltage waveforms at the time of switching of the semiconductor apparatus600or the semiconductor apparatus700. Emitter-collector voltage VC, emitter-collector current IC, and potential VGof the gate conductive part44are shown. In this example, shown is a graph where, when the semiconductor apparatus600or the semiconductor apparatus700is an IGBT device including respectively the storage region71or the storage region72, gate resistance is set to 2×RG [Ω], wherein the RG [Ω] is an arbitrary resistance value.

FIG. 19Bshows an example of a graph of an on-state power loss PC[W] per unit time at the time of switching of the semiconductor apparatus600or the semiconductor apparatus700. In this example, shown is a graph where, when the semiconductor apparatus600or the semiconductor apparatus700is an IGBT device including respectively the storage region71or the storage region72, gate resistance is set to 2× RG [Ω], wherein the RG [Ω] is the same value as the resistance value RG [Ω] inFIG. 19A.

FIG. 19Cshows a reverse recovery characteristic (diode anode voltage Va [V]) of the diode110at the time of switching of the semiconductor apparatus600or the semiconductor apparatus700. In this example, shown is a graph where, when the diode110connected to the semiconductor apparatus600or the semiconductor apparatus700is an FWD (Free Wheeling Diode) device, gate resistance is set to 2×RG [Ω], wherein the RG [Ω] is the same value as the resistance value RG [Ω] inFIG. 19A.

FIG. 20Ashows another example of the current and voltage waveforms at the time of switching of the semiconductor apparatus200. Emitter-collector voltage VC, emitter-collector current IC, and potential VGof the gate conductive part44are shown. In this example, shown is a graph where, when the semiconductor apparatus200is an IGBT device including no storage region, gate resistance is set to 2×RG [Ω], wherein the RG [Ω] is an arbitrary resistance value, and is the same value as the resistance value RG [Ω] shown inFIG. 19A.

FIG. 20Bshows an example of a graph of an on-state power loss PC[W] per unit time at the time of switching of the semiconductor apparatus200. In this example, shown is a graph where, when the semiconductor apparatus200is an IGBT device including no storage region, gate resistance is set to 2×RG [Ω], wherein the RG [Ω] is the resistance value inFIG. 20A.

FIG. 20Cshows a reverse recovery characteristic (diode anode voltage Va [V]) of the diode110at the time of switching of the semiconductor apparatus200. In this example, shown is a graph where, when the diode110connected to the semiconductor apparatus200is an FWD device, gate resistance is set to 2×RG [Ω], wherein the RG [Ω] is the same value as the resistance value RG [Ω] inFIG. 20A.

FIG. 21Ashows another example of the current and voltage waveforms at the time of switching of the semiconductor apparatus200. Emitter-collector voltage VC, emitter-collector current IC, and potential VGof the gate conductive part44are shown. In this example, shown is a graph where, when the semiconductor apparatus200is an IGBT device including no storage region, gate resistance is set to 1×RG [Ω], wherein the RG [Ω] is an arbitrary resistance value, and is the same value as the resistance value RG [Ω] shown inFIG. 19A.

FIG. 21Bshows another example of the graph of the on-state power loss PC[W] per unit time at the time of switching of the semiconductor apparatus200. In this example, shown is a graph where, when the semiconductor apparatus200is an IGBT device including no storage region, gate resistance is set to 1×RG [Ω], wherein the RG [Ω] is the resistance value inFIG. 21A.

FIG. 21Cshows the reverse recovery characteristic (diode anode voltage Va [V]) of the diode110at the time of switching of the semiconductor apparatus200. In this example, shown is a graph where, when the diode110connected to the semiconductor apparatus200is an FWD device, gate resistance is set to 1×RG [Ω], wherein the RG [Ω] is the same value as the resistance value RG [Ω] inFIG. 21A.

As shown above, the gate resistance of the semiconductor apparatus inFIGS. 20A to 20Cis 2×RG [Ω], and the gate resistance of the semiconductor apparatus inFIGS. 21A to 21Cis 1×RG [Ω]. That is, the semiconductor apparatus inFIGS. 20A to 20Cand the semiconductor apparatus inFIGS. 21A to 21Care different in their values of gate resistance Rg.

InFIGS. 19A and 20A, the semiconductor apparatus600including the storage region71or the semiconductor apparatus700including the storage region72has a switching speed higher than that of the semiconductor apparatus200including no storage region. Moreover, inFIGS. 19B and 20B, the semiconductor apparatus600including the storage region71or the semiconductor apparatus700including the storage region72has an on-state power loss Eon [J] smaller than that of the semiconductor apparatus200including no storage region.

For the on-state power loss Eon [J] at the time of turn-on of the IGBT device, the larger an area surrounded by a straight line of PC=0 [W] and a curve drawn by the PC[W], which is shown in each ofFIGS. 19B and 20B, is, the greater a value of the on-state power loss is.FIGS. 19B and 20B, where the gate resistances Rgare the same, have these areas almost the same.

Reverse recovery characteristics will be compared below for a case where the diodes110shown inFIGS. 19C and 20Care an FWD device.

InFIG. 19Cwhere the storage region71or the storage region72is included, the storage region71or the storage region72, and the drift region18are in serial contact with each other, and resistance of this portion is reduced. This accelerates a voltage drop immediately after the IGBT device is turned on, and increases the maximum value of dV/dt [a.u.].

InFIG. 20Cwhere no storage region is included, the voltage drop immediately after the IGBT device is turned on becomes gentle, and the maximum value of dV/dt [a.u.] is not increased. Therefore, without storage region included, the increase in the maximum value of dV/dt [a.u.] at the time of turn-on of the IGBT device is suppressed, and the on-state power loss Eon [J] is improved.

In order to obtain the same maximum value of dV/dt [a.u.] as when there is a storage region, when there is no storage region, the gate resistance Rgmay be lowered as shown inFIG. 21C. Lowering the gate resistance Rgshortens switching time as shown inFIG. 21A, and can reduce the on-state power loss Eon [J] as shown inFIG. 21B.

EXPLANATION OF REFERENCES