Method for manufacturing a transistor

A method for manufacturing a transistor is disclosed, which is capable of improving matching characteristics of regions within a transistor or among transistors on a wafer, from wafer-to-wafer, or from lot-to-lot. The method includes forming a photoresist pattern on a semiconductor substrate including an isolation layer, forming a drift region by implanting first and second dopant ions using the photoresist pattern as a mask, forming a gate oxide layer on the semiconductor substrate, forming a poly gate on the gate oxide layer, forming source and drain regions a predetermined distance from the poly gate, and forming a silicide layer on the above structure.

This application claims the benefit of Korean Patent Application No. 10-2007-0138833, filed on Dec. 27, 2007, which is hereby incorporated by reference as if fully set forth herein.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method for manufacturing a transistor, and more particularly, to a method for manufacturing a transistor capable of improving matching among transistors (e.g., on a wafer, from wafer-to-wafer, and/or from lot-to-lot) or among structures in a transistor.

2. Discussion of the Related Art

In a general driving circuit for a flat panel display such as an LCD, a PDP and an OLED which are recently growing in the market, a high-voltage device and a low-voltage device are integrated in one chip. Such a circuit is called a high-voltage integrated circuit. In order to design the high-voltage integrated circuit, models of a high-voltage metal oxide semiconductor (MOS) transistor and a low-voltage complementary MOS (CMOS) circuit transistor are useful.

FIG. 1AtoFIG. 1Dare sectional views showing the processes for forming a general drain-extended MOS (DEMOS) transistor.

Referring toFIG. 1A, active regions (for example, p-wells; not shown) are defined on a semiconductor substrate10. After a barrier oxide layer35and a nitride layer (not shown) are vapor-deposited on the active regions, an isolation layer (not shown) is formed by shallow trench isolation (STI) to separate the respective active regions.

Next, a photoresist pattern40is formed by performing photolithography, and a drift region45is formed by performing a lightly doped drain (LDD) implantation using the photoresist pattern as a mask.

As shown inFIG. 1B, next, post-ion implant cleaning and annealing are performed, thereby activating cohesion between the implanted dopants and silicon atoms.

A gate oxide layer50is grown on the semiconductor substrate10. Polysilicon is deposited (e.g., by vapor-depositing) on the gate oxide layer50. A poly gate60is formed through photolithography and etching processes.

After this, spacers70are formed on sidewalls of the poly gate60. Source and drain regions80are formed a predetermined distance from the poly gate60by ion implantation.

As shown inFIG. 1C, an oxide and/or a nitride is vapor-deposited on the whole surface of the resultant structure, and a photoresist pattern is formed on the oxide and/or nitride through photolithography using a non-silicide mask to expose parts of the oxide and/or nitride excluding a silicide region that will be formed later. In addition, a silicide barrier layer90is formed by etching the oxide or nitride by using the photoresist pattern as a mask.

Next, as shown inFIG. 1D, the photoresist pattern is removed and a silicide is vapor-deposited on the whole surface of the resultant structure. Additionally, a thermal processing and annealing are performed to form a silicide layer95.

However, when the drift region formed by LDD implantation is used in the general DEMOS transistor, matching characteristics may deteriorate when the device size is increased. Furthermore, in the case of a device used in an electrostatic discharge (ESD) circuit, a non-silicide process including a non-silicide masking operation generally improves the ESD characteristics.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a method for manufacturing a transistor that is capable of improving matching characteristics among transistors.

To achieve these objects and other advantages and in accordance with the purpose(s) of the invention, as embodied and broadly described herein, a method for manufacturing a transistor comprises forming a photoresist pattern on a semiconductor substrate including an isolation layer, forming a drift region by implanting first and second dopant ions using the photoresist pattern as a mask, forming a gate oxide layer on the semiconductor substrate, forming a poly gate on the gate oxide layer, forming source and drain regions a predetermined distance from the poly gate, and forming a silicide layer on the above structure.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 2AtoFIG. 2Dare cross-sectional views illustrating exemplary processes of manufacturing a DEMOS transistor according to embodiments of the present invention.

Referring toFIG. 2A, the DEMOS transistor comprises a plurality of active regions (for example, p-wells; not shown) defined on a semiconductor substrate100. A barrier oxide layer350and a nitride layer (not shown) are deposited on the active region200(e.g., by chemical vapor deposition, or CVD). Then, an isolation layer (not shown) by shallow trench isolation (STI). The STI layer separates the active regions of the substrate.

A photoresist pattern400is formed using photolithography, and a drift region450is formed by ion implantation using the photoresist pattern as a mask. In general, conditions for forming drift region450are similar to or the same as those for forming a lightly doped drain (LDD) region. During the formation of the drift region450, two ion implantations are performed. Boron ions are implanted at a higher dose or density than phosphorus ions, but at a relatively low energy (e.g., very shallow in a surface of the substrate100). The phosphorus ions, implanted at a lower dose or density than the boron ions, are implanted at a relatively high energy (e.g., relatively deep into the substrate).

As shown inFIG. 2B, next, post-ion implant wafer cleaning and annealing are performed. For example, the photoresist pattern400is removed by ashing in a plasma formed from oxygen gas, and the wafer may be wet cleaned with an organic and/or basic cleaning solution to remove residual photoresist. Annealing is generally performed at a temperature and for a length of time sufficient to activate the dopant ions implanted into the wafer, and optionally repair any incidental damage to the wafer resulting from ion implantation. In one embodiment, annealing may improve cohesion between the implanted dopant ions and silicon atoms.

Additionally, a gate oxide layer500is grown on the semiconductor substrate100. In the above process, the shallowly implanted high-density boron ions are diffused while being oxidized. Therefore, the surface of the semiconductor substrate100into which the boron and phosphorous ions are implanted may be oxidized at a higher rate than those areas covered by the photoresist pattern400, and gate oxide500is thicker in the implanted regions. The difference in thickness between the implanted regions and the masked regions can be from 5 to 100 Å, or any range therein (e.g., 10-50 Å). The phosphorus ions form the drift region450.

Next, as shown inFIG. 2C, a silicon layer is deposited (e.g., by CVD, which may be plasma-assisted or plasma-enhanced) on the gate oxide layer500. The silicon layer is then annealed to crystallize the silicon and form a polysilicon layer. Afterward, a poly gate600is formed by photolithography and etching processes.

Spacers700are formed on sidewalls of the poly gate600, and source and drain regions800aand800bare formed at a predetermined distance from the poly gate600. In one embodiment, source and drain regions800aand800bare formed by double ion implantation. During this double ion implantation, the thickly formed part of the gate oxide layer500performs a self-aligning function, thereby improving the matching characteristics of the implant regions in the transistor, among transistors on the wafer, from wafer-to-wafer, and/or from lot-to-lot. In addition, since the thick part of the gate oxide layer500increases the length of the drift region450, a device capable of functioning as a laterally diffused MOS (LDMOS) transistor can be achieved. As a result, the size of the device can be reduced.

Next, as shown inFIG. 2D, a metal is deposited (e.g., by sputtering or CVD) on the whole surface of the wafer, and thermal processing and annealing are performed to form a silicide layer950.

As apparent from the above description, in accordance with the method for manufacturing a transistor according to any of the above-described embodiments of the present invention, the length of a drift region can be increased by growing a relatively thick gate oxide in implanted regions, thereby achieving a device functioning as an LDMOS transistor. Consequently, the device size can be reduced. In addition, since the thickened gate oxide layer is capable of self-alignment during source and drain implantation, the matching characteristics among transistors can be enhanced.