Trench MOSFET and method for fabricating the same

The present disclosure relates to a trench MOSFET and a method for fabricating the same. The method comprises: providing a substrate with an epitaxy layer; forming a trench in the epitaxy layer; forming a first insulating layer, a first gate, a second insulating layer, and a second gate successively in the trench by deposition and etching; forming a well and a source region at both sides of the trench by ion implantation, and forming a trench-type contact and a metal plug. By forming the first gate and the second gate which are separated from each other, the first insulating layer between a lower portion of the first gate and the epitaxy layer has a thickness larger than that of the second insulating layer between the second gate and the well and the source region. The two separate gates are connected with each other by the metal plug. The resultant MOSFET has an increased breakdown voltage and stable performance while its manufacturer cost is lowered because the manufacturer process is simplified.

RELATED APPLICATIONS

This application claims the benefit of Chinese Patent Application No. 201310378544.7, filed on Aug. 27, 2013, which is incorporated herein by reference in its entirety.

TECHNICAL FIELD

The present disclosure generally relates to the field of semiconductor manufacture processes, and more specifically, to a trench MOSFET and a method for fabricating the same.

BACKGROUND

The performance of a metal-oxide-semiconductor field effect transistor (MOSFET) is evaluated in terms of its response speed, on-off current ratio, threshold voltage, and the like. To increase the response speed and the on-off current ratio and decrease the threshold voltage of the MOSFET, the MOSFET should have a gate oxide layer with a decreased thickness. However, the thinner the gate oxide layer is, the more easily the gate oxide layer is broken down by charge accumulated at a gate electrode when a gate voltage is relatively high, resulting in failure of the MOSFET.

To increase a breakdown voltage of the MOSFET while maintaining a relatively high response speed, a relatively large on-off current ratio and a relatively low threshold voltage, the charge accumulating at the gate should be eliminated to avoid breakdown of the gate oxide layer.

A conventional MOSFET typically exhibits a large gate-drain capacitance Cgd because a gate oxide layer below a gate has a small thickness. Consequently, a large amount of electric charge may be easily accumulated on the gate electrode of the device to break down the gate oxide layer, and hence the performance of withstanding high voltage of the MOSFET is poor. As an improved prior art, there is provided a MOSFET structure as shown inFIG. 1, in which the MOSFET is formed in an N− epitaxy layer1on N+ substrate2. The bottom of the N+ substrate2is covered with a metal stack of Ti/Ni/Ag as a drain metal8. A trench3extends into the N− epitaxy layer1from an upper surface of the N− epitaxy layer1. A lower portion of the inner surface of the trench3is covered with a first insulating layer4, and an upper portion of the inner surface of the trench3is covered with a second insulating layer5, as a gate oxide layer. The first insulating layer4has a thickness larger than that of the second insulating layer5. A polysilicon protection electrode6is formed at an upper portion of the inner surface of the trench3, with a side wall surrounded by the second insulating layer5and a bottom contacting the first insulating layer4. A gate7is formed in the trench3and surrounded by the polysilicon protection electrode6. A lower portion of the gate7is located below the polysilicon protection electrode6and surrounded by the first insulating layer4. An upper portion of the gate7is adjacent to the polysilicon protection electrode6and surrounded by the second insulating layer5. That is, the protection polysilicon electrode6is located between the gate7and an upper portion of the inner surface of the trench3. In this structure, the polysilicon protection electrode6is added between the gate7and the N− epitaxy layer1which is used as a drain. The protection electrode is connected to a source, and thus is an actual source of the device.

This structure is proposed for converting a gate-drain capacitance Cgd into a gate-source capacitance Cgs and a drain-source capacitance Cds, so that an effect of the gate-drain capacitance Cgd on the device is reduced and a breakdown voltage of the device is improved. However, the gate7and the polysilicon protection electrode6should be well insulated in this structure, which means many difficulties in the process. Consequently, the device has variable breakdown voltage and poor reliability, and the manufacture process for the structure includes complex steps, resulting in increased manufacture cost.

SUMMARY

One object of the present disclosure is to provide a trench MOSFET and a method for fabricating the same. The resultant MOSFET has an increased breakdown voltage while maintaining a low threshold voltage, a large on-off current ratio and a high response speed. The method is simplified for providing a reproducible MOSFET with a stable performance, and leads to reduced manufacture cost.

According to one aspect of the present disclosure, there is provided a method for fabricating a trench MOSFET, comprising:

providing a substrate having a body of a first conductivity type and an epitaxy layer of the first conductivity type on the body;

forming a trench by etching the epitaxy layer;

depositing a first insulating layer and a first polysilicon layer successively on the epitaxy layer, the first polysilicon layer filling the trench;

forming a first gate in the trench by etching the first polysilicon layer;

etching off an exposed portion of the first insulating layer, and depositing a second insulating layer and a second polysilicon layer successively, the second polysilicon layer filling the trench;

forming a second gate in the trench by etching the second polysilicon layer;

forming a well of a second conductivity type by performing a first ion implanting after etching off an exposed portion of the second insulting layer to expose the epitaxy layer;

forming a source region of the first conductivity type by performing a second ion implanting at the surface of the well;

depositing a third insulating layer on the source region and over the trench;

forming a gate opening and a source opening by etching, the gate opening extending through the third insulating layer, the second gate, the second insulating layer and into the first gate, and the source opening extending through the third insulating layer, the source region and into the well; and

forming metal plugs by filling a metal layer in the gate opening and in the source opening.

Preferably, the method further comprises forming a gate metal and a source metal by extending the metal plugs above the third insulating layer when the metal plugs are formed.

Preferably, the method further comprises depositing a drain metal on a back surface of the body after forming the gate metal and the source metal.

Preferably, the third insulating layer is an oxide layer.

Preferably, the metal plugs, the gate metal, the source metal and the drain metal are each made of aluminum alloy or copper, and are lined with a barrier metal stack of Ti/TiN, Co/TiN or Ta/TiN.

Preferably, the epitaxy layer has a doping concentration smaller than that of the body.

Preferably, the method further comprises depositing a hard mask layer on the epitaxy layer before forming the trench; and forming an etching opening by etching the hard mask layer.

Preferably, the hard mask layer is an oxide layer having a thickness of about 0.1 micrometer to about 1 micrometer.

Preferably, the etching opening has a width of about 0.5 micrometer to about 5 micrometers.

Preferably, the trench has a depth of about 0.5 micrometer to about 50 micrometers.

Preferably, the first insulating layer is an oxide layer having a thickness of about 0.1 micrometer to about 2 micrometers.

Preferably, a sum of a thickness of the first polysilicon layer and a thickness of the first insulating layer is larger than one half of a width of the trench.

Preferably, an upper surface of the first gate is about 0.1 micrometer to about 1 micrometer below an upper surface of the epitaxy layer.

Preferably, the second insulating layer has a thickness smaller than that of the first insulating layer.

Preferably, the second insulating layer is an oxide layer.

Preferably, an upper surface of the second gate is about 0 micrometer to about 0.1 micrometer below an upper surface of the epitaxy layer.

Accordingly, there is provided a trench MOSFET fabricated by the above method, comprising:

a substrate having a body of a first conductivity type and an epitaxy layer of the first conductivity type on the body;

a trench extending into the epitaxy layer from an upper surface of the epitaxy layer;

a first insulating layer at a lower portion of an inner surface of the trench;

a first gate in the trench and having a lower portion surrounded by the first insulating layer;

a second insulating layer at an upper portion of the inner surface of the trench and covering the first gate, the first insulating layer and the second insulating layer together surrounding the first gate;

a second gate at an upper portion of the trench and surrounded by the second insulating layer, the second gate having an upper surface below an upper surface of the epitaxy layer;

a well of the second conductivity type at a surface portion of the epitaxy layer at both sides of the trench;

a source region of the first conductivity type at a surface portion of the well at both sides of the trench;

a third insulating layer at the top surface of the source region and over the trench;

a gate opening extending through the third insulating layer, the second gate, the second insulating layer and into the first gate;

a source opening extending through the third insulating layer, the source region and into the first gate; and

metal plugs in the gate opening and in the source opening.

The present disclosure can advantageously provide the following beneficial effects over the prior art:

1. in the trench MOSFET and the method for fabricating the same, the first gate and the second gate are formed as being separated from each other so that the first insulating layer between a lower portion of the first gate and the epitaxy layer has a large thickness, and the second insulating layer between the second gate and the well and the source region has a small thickness; two separate gates are connected with each other by metal plugs; thus, the MOSFET has a small gate-drain capacitance and avoids failure due to the breakdown of the gate oxide layer by the charge accumulated on the gate when a large voltage is applied to the MOSFET; consequently, the MOSFET has a high breakdown voltage while maintaining a low threshold voltage, a large on-off current ratio and a high response speed;

2. it is not critical whether the first gate and the second gate are well insulated or not; the process can be repeated and the resultant MOSFET has a stable breakdown voltage; the method is simplified with less steps, and will not increase manufacture cost while the breakdown voltage of the MOSFET is improved.

DESCRIPTION OF EMBODIMENTS

Reference will now be made in detail to particular embodiments of the disclosure, examples of which are illustrated in the accompanying drawings. While the disclosure will be described in conjunction with the preferred embodiments, it will be understood that they are not intended to limit the disclosure to these embodiments. On the contrary, the disclosure is intended to cover alternatives, modifications and equivalents that may be included within the spirit and scope of the disclosure as defined by the appended claims.

Furthermore, in the following detailed description of the preferred embodiments according to the present disclosure, numerous specific details are shown in conjunction with attached drawings. For simplicity and clarity of illustration, elements illustrated in the attached drawings are not necessarily drawn to scale. It will be understood that the dimensions of the elements are not intended to limit the disclosure.

FIG. 2illustrates a flow chart of a method for fabricating a trench MOSFET according to an embodiment of the present disclosure. As shown inFIG. 2, the present disclosure relates to a method for fabricating a trench MOSFET, comprising the following steps:

step S01: providing a substrate having a body of a first conductivity type and an epitaxy layer of the first conductivity type on the body;

step S02: forming a trench by etching the epitaxy layer;

step S03: depositing a first insulating layer and a first polysilicon layer successively on the epitaxy layer, the first polysilicon layer completely filling the trench;

step S04: forming a first gate in the trench by etching the first polysilicon layer;

step S05: etching off an exposed portion of the first insulating layer, and depositing a second insulating layer and a second polysilicon layer successively, the second polysilicon layer completely filling the trench;

step S06: forming a second gate in the trench by etching the second polysilicon layer;

step S07: forming a well of a second conductivity type by performing a first ion implanting after etching off an exposed portion of the second insulting layer to expose the epitaxy layer;

step S08: forming a source region of the first conductivity type by performing a second ion implanting at the surface of the well;

step S09: depositing a third insulating layer on the source region and over the trench;

step S10: forming a gate opening and a source opening by etching, the gate opening extending through the third insulating layer, the second gate, the second insulating layer and into the first gate, and the source opening extending through the third insulating layer, the source region and into the well; and

step S11: forming metal plugs by filling a metal layer in the gate opening and in the source opening.

FIGS. 3 to 14illustrate schematic diagrams of example structures in various stages of a method for fabricating a trench MOSFET according to an embodiment of the present disclosure. Referring toFIG. 2and in connection withFIGS. 3 to 14, the method for fabricating the trench MOSFET according to the present disclosure will be depicted in details.

In step S01, there is provided a substrate having a body11of a first conductivity type and an epitaxy layer12of the first conductivity type on the body, as shown inFIG. 3.

In the present embodiment, the first conductivity type is of N type. The body11is a heavily-doped N-type substrate, and the epitaxy layer12is a lightly-doped N-type epitaxy layer. That is, the epitaxy layer12has a doping concentration smaller than that of the body11.

This step further includes depositing a hard mask layer13on the epitaxy layer11and forming an etching opening01by etching the hard mask layer13, as shown inFIG. 4.

The hard mask layer13is an oxide layer formed by thermal oxidation, atmospheric pressure chemical vapor deposition, or low pressure chemical vapor deposition. The hard mask layer13has a thickness of about 0.1 micrometer to about 1 micrometer.

A photoresist layer is applied over the hard mask layer13, and then is subjected to lithography to expose a portion of the hard mask layer. The exposed portion of the hard mask layer13is etched off and then the photoresist layer is also removed, so that an etching opening01is formed in the hard mask layer13. The etching opening01has a width of about 0.5 micrometer to about 5 micrometers. The etching opening01exposes a portion of the epitaxy layer12.

In step S02, a trench02is formed by etching the epitaxy layer12, as shown inFIG. 5.

The epitaxy layer12is etched through the etching opening01in the hard mask layer13, so as to form a trench02. Then, the hard mask layer13is removed. The trench02extends into the epitaxy layer12from an upper surface of the epitaxy layer12. The trench02has a bottom above a boundary between the body11and the epitaxy layer12. Preferably, the trench02has a depth in the range of about 0.5 micrometer to about 50 micrometers.

In step S03, a first insulating layer14and a first polysilicon layer15are deposited successively on the epitaxy layer12. The first polysilicon layer15completely fills the trench, as shown inFIG. 6.

The first insulating layer14is a dielectric layer having a large thickness. In this embodiment, the first insulating layer14is an oxide layer (for example, silicon dioxide) having a thickness of about 0.1 micrometer to about 2 micrometers.

A sum of a thickness of the first polysilicon layer15and a thickness of the first insulating layer14is larger than one half of a width of the trench02, so that the first polysilicon layer15completely fills the whole trench.

In step S04, the portion of the first polysilicon layer15outside the trench02is firstly etched off, and a portion of the first polysilicon layer15inside the trench is then etched back, so as to form a first gate15′ in the trench02, as shown inFIG. 7.

The first gate15′ is formed by completely removing the portion of the portion of the first polysilicon layer15on the epitaxy layer12and by etching a portion of the polysilicon layer15in the trench02. The first insulating layer14functions as a gate oxide layer. The first gate15′ has an upper surface which is about 0.1 micrometer to about 1 micrometer below an upper surface of the epitaxy layer12.

In step S05, an exposed portion of the first insulating layer14is etched off, and a second insulating layer16and a second polysilicon layer17are deposited successively. The second polysilicon layer17completely fills the trench, as shown inFIG. 8.

The portion of the first insulating layer14on the epitaxy layer12is firstly completely removed, and then an exposed portion of the first insulating layer14on a side wall of the trench02is etched off. A second insulating layer16is deposited on an upper portion of the side wall of the trench02, on an upper portion of the side wall of the first gate15′, and on an upper surface of the first gate15. The second insulating layer16contacts the first insulating layer14.

The second insulating layer16is a gate oxide layer and has a thickness smaller than that of the first insulating layer14.

Next, a second polysilicon layer17is deposited to completely fill the trench.

In step S06, the portion of the second polysilicon layer17outside the trench02is firstly etched off, and a portion of the second polysilicon layer17inside the trench is then etched back, so as to form a second gate17′ in the trench02, as shown inFIG. 9.

The portion of the second polysilicon layer17on the second insulating layer16is completely etched off. To ensure that the portion of the second polysilicon layer17outside the trench is completely removed, the second gate17has an upper surface which is at least 0.1 micrometer below the upper surface of the epitaxy layer12. Consequently, the portion of the second polysilicon outside the trench are completely removed.

In step S07, an exposed portion of the second insulating layer16is etched off to expose an upper surface of the epitaxy layer12. A well18of a second conductivity type is formed at a surface portion of the epitaxy layer12on both sides of the trench by performing a first ion implanting, as shown inFIG. 10.

After the first ion implanting, the method further includes performing thermal diffusion for the well18at the surface portion of the epitaxy layer12. The first ion implanting is performed by using a P-type dopant to form a P-type well.

In step S08, a source region19of the first conductivity type is formed by performing a second ion implanting at the surface portion of the well18, as shown inFIG. 11.

In this embodiment, the first conductivity is of an N type. A photoresist is applied over a surface of the well18and a surface of the second gate17′. The photoresist is subjected to lithography to expose the well18. The second ion implanting is performed at an exposed surface portion of the well by using an N-type dopant, followed by thermal diffusion. An N-type source region19is thus formed at a surface portion of the well18.

In step S09, a third insulating layer20is deposited on the source region19and over the trench, as shown inFIG. 12.

In this embodiment, the third insulating layer20is an oxide layer (for example, silicon dioxide), or is made of other materials well known in the field.

In step S10, a gate opening03and a source opening04are formed by etching. The gate opening03extends through the third insulating layer20, the second gate17′, the second insulating layer16and into the first gate15′, and the source opening04extends through the third insulating layer20, the source region19and into the well18, as shown inFIG. 13.

A photoresist layer is applied over the third insulating layer20. The photoresist layer is subjected to exposure and development to expose portions of the third insulating layer20on the source region19and over the trench. The exposed portions of the third insulating layer16, the second gate17′, the second insulating layer16and the first gate15′ are etched to form the gate opening03, and the exposed portions of the third insulating layer20, the source region19and the well18are etched to form the source opening04.

In step S11, metal plugs05,06are formed by filling a metal layer in the gate opening03and in the source opening04, respectively, as shown inFIG. 14.

Optionally, this step further includes extending the metal plugs05,06above the third insulating layer to form a gate metal21and a source metal22, and forming a drain metal23by depositing a metal layer at a back surface of the body11.

The metal plugs05,06are formed by depositing a metal layer in the gate opening03and in the source opening. In this embodiment, the metal layer thus deposited extends above the third insulating layer20to form a gate metal21and a source metal22. In other embodiments, the gate metal21and the source metal22can also be formed above the metal plugs05and06, respectively, in separate steps. The drain metal23is deposited on the back surface of the body11.

The meal materials in the metal plugs05and06, in the gate metal21, in the source metal22and in the drain metal23may be each made of aluminum alloy or copper or of other metals well known by one skilled person, and may be lined with a barrier metal stack of Ti/TiN, Co/TiN or Ta/TiN.

In the present disclosure, the first gate15′ and the second gate17′ are formed as being separated from each other so that the first insulating layer14between a lower portion of the first gate15′ and the epitaxy layer12has a large thickness, and the second insulating layer16between the second gate17′ and the well18and the source region19has a small thickness; two separate gates are connected with each other by the metal plug05; thus, the MOSFET has a small gate-drain capacitance and avoids failure due to the breakdown of the gate oxide layer by the charge accumulated on the gate when a large voltage is applied to the MOSFET; consequently, the MOSFET has a high breakdown voltage while maintaining a low threshold voltage, a large on-off current ratio and a high response speed;

Accordingly, there is provided a trench MOSFET fabricated by the above method, as shown inFIG. 14, comprising:

a substrate having a body11of a first conductivity type and an epitaxy layer12of the first conductivity type on the body11;

a trench extending into the epitaxy layer12from an upper surface of the epitaxy layer12;

a first insulating layer14at a lower portion of an inner surface of the trench;

a first gate15′ in the trench and adjacent to the first insulating layer14, the first gate15′ having a lower portion surrounded by the first insulating layer14;

a second insulating layer16at an upper portion of the inner surface of the trench and covering the first gate15′, the first insulating layer14and the second insulating layer16together surrounding the first gate;

a second gate17′ at an upper portion of the trench, between the upper portion of the inner surface of the trench and the portion of the second insulating layer at the upper portion of the outer surface of the first gate15′, the second gate17′ having an upper surface below an upper surface of the epitaxy layer12;

a well18of the second conductivity type at a surface portion of the epitaxy layer12at both sides of the trench;

a source region19of the first conductivity type at a surface portion of the well18at both sides of the trench;

a third insulating layer20at the top surface of the source region19and over the trench, the second insulating layer16and the third insulating layer20together surrounding the second gate;

a gate opening extending through the third insulating layer20, the second gate17′, the second insulating layer16and into the first gate15′;

a source opening extending through the third insulating layer20, the source region19and into the first gate18; and

metal plugs05and06in the gate opening and in the source opening.

a gate metal21on the third insulating layer20and connected to the metal plug05;

a drain metal22on the third insulating layer20and connected to the metal plug06;

a drain metal23on a back surface of the body11.

To sum up, in the trench MOSFET and the method for fabricating the same, the first gate and the second gate are formed as being separated from each other so that the first insulating layer between a lower portion of the first gate and the epitaxy layer has a large thickness, and the second insulating layer between the second gate and the well and the source region has a small thickness; two separate gates are connected with each other by metal plugs; thus, the MOSFET has a small gate-drain capacitance and avoids failure due to the breakdown of the gate oxide layer by the charge accumulated on the gate when a large voltage is applied to the MOSFET; consequently, the MOSFET has a high breakdown voltage while maintaining a low threshold voltage, a large on-off current ratio and a high response speed; it is not critical whether the first gate and the second gate are well insulated or not; the process can be repeated and the resultant MOSFET has a stable breakdown voltage; the method is simplified with less steps, and will not increase manufacture cost while the breakdown voltage of the MOSFET is improved.

The embodiments were chosen and described in order to best explain the principles of the disclosure and its practical applications, to thereby enable others skilled in the art to best utilize the disclosure. The disclosure is intended to cover alternatives, modifications and equivalents that may be included within the spirit and scope of the disclosure as defined by the appended claims.