Contact punch through mitigation in SOI substrate

A method of forming a contact to mitigate punch through in SOI substrates is disclosed. The method may include providing an active region in SOI substrate isolated from another region in the SOI substrate by a shallow trench isolation (STI), the active region having a silicided source/drain region adjacent the STI. A spacer may be formed at an edge of the silicided source/drain region adjacent to the STI. A contact etch stop layer (CESL) may be deposited over the spacer and a dielectric layer over the CESL. A contact opening may be formed to the source/drain region through the CESL and the dielectric layer. A portion of the contact opening is positioned over the spacer such that the spacer prevents punch through into the STI. A contact may then be formed in the contact opening.

BACKGROUND

The present disclosure relates to semiconductor device fabrication, and more specifically, to methods of mitigating contact punch through in a semiconductor-on-insulator (SOI) substrate. Semiconductor-on-insulator technology (SOI) typically refers to the use of a layered semiconductor-insulator-semiconductor substrate in place of a more conventional semiconductor substrate (bulk substrate) in semiconductor manufacturing, especially microelectronics. SOI-based devices differ from conventional silicon-built devices in that the semiconductor junction is above an electrical insulator, typically silicon dioxide or (less commonly) sapphire. The choice of insulator depends largely on intended application, with sapphire being used for radiation-sensitive applications and silicon oxide preferred for improved performance and diminished short channel effects in microelectronics devices. The precise thickness of the insulating layer and topmost semiconductor-on-insulator (SOI) layer also vary widely with the intended application. SOI substrates are commonly used to form a large variety of devices such as: static random access memory (SRAM), clock synchronized RAM (CSRAM), logic devices, etc.

During formation of semiconductor devices, electrical contacts are formed through dielectric layers to electrically interconnect desired components with other components, e.g., source, drain or gates of a transistor. Each component is positioned within a selected layer within the semiconductor device that is covered by a dielectric. Typically, the contacts are formed by patterning a mask over the dielectric layer and etching to form an opening in the dielectric to the desired component therebelow. The opening is then filled with a liner and a conductor to form the contact. One challenge relative to forming contacts using SOI substrates is ensuring the contact opening does not extend into the layer below, which is referred to as “punch through.” Punch through leads to the contact being in the wrong location and possibly making the device non-functional. Consequently, punch through can cause problems with yield during fabrication and/or performance degradation of the final device. The challenge of controlling punch through is magnified with smaller semiconductor devices, especially with current technology that is now creating wires smaller than 32 nanometers (nm). One approach to address punch through with SOI substrates is to control the etch selectivity of whatever etching technique is employed. This approach however is not always effective because, for example, it is difficult to effectively detect end points of the etching for the small contacts.

One type of punch through is referred to as “edge punch through” and refers to over-etching into a divot or recess next to a shallow trench isolation (STI) at the boundary of different regions of the substrate, e.g., between an active region and another region. STI is a form of isolation in which a trench is etched into the substrate and filled with an insulating material such as oxide, to isolate one region of the substrate from an adjacent region of the substrate. One or more transistors of a given polarity may be disposed within an area isolated by STI. Edge punch through can cause direct shorts to the underlying substrate.

SUMMARY

A first aspect of the disclosure is directed to a method of forming a contact, the method including: providing an active region in a semiconductor-on-insulator (SOI) substrate isolated from another region in the SOI substrate by a shallow trench isolation (STI), the active region having a silicided source/drain region adjacent the STI; forming a spacer at an edge of the silicided source/drain region adjacent to the STI; depositing a contact etch stop layer (CESL) over the spacer: forming a dielectric layer over the CESL; forming a contact opening to the silicided source/drain region through the CESL and the dielectric layer, wherein a portion of the contact opening is positioned over the spacer such that the spacer prevents punch through into the STI; and forming a contact in the contact opening.

A second aspect of the disclosure includes a method of forming a contact, the method including: providing an active region in a semiconductor-on-insulator (SOI) substrate isolated from another region in the SOI substrate by a shallow trench isolation (STI), the active region having a silicided source/drain region adjacent the STI; forming a spacer at an edge of the silicided source/drain region adjacent to the STI by: depositing a spacer material over the silicided source/drain region and the STI, anisotropically etching the spacer material, creating the spacer, and performing a post-etch clean; depositing a contact etch stop layer (CESL) over the spacer; forming a dielectric layer over the CESL; forming a contact opening to the source/drain region through the CESL and the dielectric layer, wherein a portion of the contact opening is positioned over the spacer such that the spacer prevents punch through into the STI; depositing a liner in the contact opening; depositing a conductor in the contact opening; and planarizing the conductor forming a contact in the contact opening.

A third aspect of the disclosure related to a semiconductor structure, including: a semiconductor-on-insulator (SOI) substrate; a shallow trench isolation (STI) isolating a silicided source/drain region in an active region of the SOI substrate from another region of the SOI substrate, the silicided source/drain region adjacent to the STI; a spacer at an edge of the silicided source/drain region adjacent to the STI; and a contact to the silicided source/drain region, wherein at least a portion of the contact lands over the spacer.

The foregoing and other features of the disclosure will be apparent from the following more particular description of embodiments of the disclosure.

DETAILED DESCRIPTION

Referring to the drawings,FIG. 1shows a cross-sectional view of an initial structure100for a method of forming a contact180(FIG. 6) according to embodiments of the disclosure. At this stage, initial structure100is provided including an active region102in a semiconductor-on-insulator (SOI) substrate104isolated from another region in SOI substrate104by a shallow trench isolation (STI)110. As illustrated, active region102includes a silicided source/drain region112adjacent STI110. The other region may include any region over STI110or beyond STI110that includes devices requiring isolation from active region102. Initial structure100may be provided using any now known or later developed semiconductor fabrication techniques.

SOI substrate104may include a semiconductor substrate114, an insulator layer116and a semiconductor-on-insulator (SOI) layer118. Semiconductor substrate114and SOI layer118may include but are not limited to silicon, germanium, silicon germanium, silicon carbide, and those consisting essentially of one or more III-V compound semiconductors having a composition defined by the formula Alx1GaX2InX3AsY1PY2NY3SbY4, where X1, X2, X3, Y1, Y2, Y3, and Y4 represent relative proportions, each greater than or equal to zero and X1+X2+X3+Y1+Y2+Y3+Y4=1 (1 being the total relative mole quantity). Other suitable substrates include II-VI compound semiconductors having a composition ZnA1CdA2SeB1TeB2, where A1, A2, B1, and B2 are relative proportions each greater than or equal to zero and A1+A2+B1+B2=1 (1 being a total mole quantity). Furthermore, a portion or entirety of each layer may be strained. For example. SOI layer118(and/or epi layer thereover) may be strained.

Insulator layer116may include any now known or later developed dielectric used for SOI layers, such as but not limited to silicon dioxide or sapphire. As noted, the choice of insulator depends largely on intended, application, with sapphire being used for radiation-sensitive applications and silicon oxide preferred for improved performance and diminished short channel effects in microelectronics devices. The precise thickness of insulator layer116and topmost SOI layer118also vary widely with the intended application.

Active region102may include any region of SOI substrate104in which active devices are employed. In the instant example, a transistor120including silicided source/drain region112is formed in active region102. Transistor120may otherwise include a channel region122in SOI layer118between source/drain regions124,126. Raised source/drain regions128,130may be formed over source/drain regions124,126, e.g., by epitaxial growth of silicon germanium. As understood, regions124,126,128,130may be doped, e.g., by ion implanting or in-situ as formed. As also known, a dopant element introduced into semiconductor can establish either p-type (acceptors) or n-type (donors) conductivity. Common dopants in silicon: for p-type—boron (B), indium (In); and for n-type—phosphorous (P) arsenic (As), antimony (Sb). Dopants are of two types—“donors” and “acceptors.” N type implants are donors and P type are acceptors.

Transistor120may also include a gate132including one or more gate dielectric layers134, including but not limited to: hafnium silicate (HfSiO), hafnium oxide (HfO2), zirconium silicate (ZrSiOx), zirconium oxide (ZrO2), silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), high-k material or any combination of these materials. Gate132may also include a conductive body136(e.g., a metal such as copper or tungsten, or polysilicon), a silicide cap138and a spacer140thereabout. Spacer140may include any now known or later developed spacer material such as silicon nitride.

Silicide cap138on gate132and a silicide142of silicided source/drain region112may be formed using any now known or later developed technique, e.g., performing an in-situ pre-clean, depositing a metal such as titanium, nickel, cobalt, etc., annealing to have the metal react with silicon, and removing unreacted metal.

Initial structure100may be formed using any now known or later developed semiconductor fabrication techniques including by not limited to photolithography (and/or as sidewall image transfer (SIT)). In lithography (or “photolithography”), a radiation sensitive “resist” coating is formed. e.g., deposited, over one or more layers which are to be treated, in some manner, such as to be selectively doped and/or to have a pattern transferred thereto. The resist, which is sometimes referred to as a photoresist, is itself first patterned by exposing it to radiation, where the radiation (selectively) passes through an intervening mask or template containing the pattern. As a result, the exposed or unexposed areas of the resist coating become more or less soluble, depending on the type of photoresist used. A developer is then used to remove the more soluble areas of the resist leaving a patterned resist. The patterned resist can then serve as a mask for the underlying layers which can then be selectively treated, such as to receive dopants and/or to undergo etching, for example.

Where materials are deposited, “depositing” may include any now known or later developed techniques appropriate for the material to be deposited including but not limited to: chemical vapor deposition (CVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), semi-atmosphere CVD (SACVD) and high density plasma CVD (HDPCVD), rapid thermal CVD (RTCVD), ultra-high vacuum CVD (UHVCVD), limited reaction processing CVD (LRPCVD), metalorganic CVD (MOCVD), sputtering deposition, ion beam deposition, electron beam deposition, laser assisted deposition, thermal oxidation, thermal nitridation, spin-on methods, physical vapor deposition (PVD), atomic layer deposition (ALD), chemical oxidation, molecular beam epitaxy (MBE), plating, evaporation.

Etching generally refers to the removal of material from a substrate (or structures formed on the substrate), and is often performed with a mask in place so that material may selectively be removed from certain areas of the substrate, while leaving the material unaffected, in other areas of the substrate. There are generally two categories of etching, (i) wet etch and (ii) dry etch. Wet etch is performed with a solvent (such as an acid) which may be chosen for its ability to selectively dissolve a given material (such as oxide), while, leaving another material (such as polysilicon) relatively intact. This ability to selectively etch given materials is fundamental to many semiconductor fabrication processes. A wet etch will generally etch a homogeneous material (e.g., oxide) isotropically, but a wet etch may also etch single-crystal materials (e.g. silicon wafers) anisotropically. Dry etch may be performed using a plasma. Plasma systems can operate in several modes by adjusting the parameters of the plasma. Ordinary plasma etching produces energetic free radicals, neutrally charged, that react at the surface of the wafer. Since neutral particles attack the wafer from all angles, this process is isotropic. Ion milling, or sputter etching, bombards the wafer with energetic ions of noble gases which approach the wafer approximately from one direction, and therefore this process is highly anisotropic. Reactive-ion etching (RIE) operates under conditions intermediate between sputter and plasma etching and may be used to produce deep, narrow features, such as STI trenches.

With further regard to the method of forming a contact according to embodiments of the disclosure, STI110may include a trench150etched into SOI substrate104(e.g., by RIE) and filled with an insulating material152such as silicon oxide, to isolate active region102of SOI substrate104from an adjacent region (over and to right of STI110) of the substrate. Part of a dummy gate154is shown over STI110, and may be provided as part of initial structure100.

At this stage in conventional processing, a contact etch stop layer (CESL) would be formed over initial structure100followed by an interlayer dielectric layer over the CESL. A contact opening mask would then be formed and used to etch a contact opening156(shown in phantom) to silicided source/drain region112. At least a portion of the contact opening frequently overlaps an edge146between active region102, and more particularly, silicided source/drain region112, and STI110, causing the contact opening to exhibit “edge punch through” relative to STI110. As noted, when the contact is eventually formed, the edge punch through can create direct shorts to SOI substrate104, which at the very least negatively impacts performance and can render the device inoperative. It is noted that while edge146is shown as a clean line between STI110and silicided source/drain region112, some residue. e.g., oxide and/or nitride, from earlier processing may exist. This residue, however, does not provide any meaningful structure or impact the contact opening forming.

In contrast to conventional processing, as shown inFIGS. 2 and 3, embodiments of the disclosure include forming a spacer160(FIG. 3) at edge146of active region102, and in particular, silicided source/drain region112, adjacent to STI110. Spacer160may also be referred to as a wing spacer. In one embodiment, spacer160forming may include depositing a spacer material162(FIG. 2) over silicided source/drain region112and STI110. Spacer material162may include any now known or later developed spacer material such as silicon nitride. The thickness of spacer material162may vary depending on technology node employed, but in one example may have a thickness of approximately 10 to approximately 20 nanometers. In another example, spacer material162may have a thickness of approximately 15 nanometers.FIG. 3shows anisotropically etching spacer material162, creating spacer160. As also shown inFIG. 3, a post-etch cleaning may also be performed. As shown inFIG. 3, spacer160covers and protects edge146between silicided source/drain region112and STI110, mitigating punch through as will be described.FIG. 3also shows additional spacers166formed around silicide cap138formed by spacer material162, but this is not necessary in all instances.

FIG. 4shows depositing a contact etch stop layer (CESL)170over spacer160. CESL170may include any now known or later developed etch stop material such as silicon nitride. In one embodiment. CESL170includes a stress therein, e.g., compressive or tensile, so as to impart a strain to at least part of active region102, in a known fashion.

FIG. 5shows forming a dielectric layer174over CESL170. e.g., by deposition. Dielectric layer174may include may include any interlevel or intralevel dielectric material including inorganic dielectric materials, organic dielectric materials, or combinations thereof. Suitable dielectric materials include but are not limited to: carbon-doped silicon dioxide materials; fluorinated silicate glass (FSG); organic polymeric thermoset materials; silicon oxycarbide; SiCOH dielectrics; fluorine doped silicon oxide; spin-on glasses; silsesquioxanes, including hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ) and mixtures or copolymers of HSQ and MSQ; benzocyclobutene (BCB)-based polymer dielectrics, and any silicon-containing low-k dielectric. Examples of spin-on low-k films with SiCOH-type composition using silsesquioxane chemistry include HOSP™ (available from Honeywell). JSR 5109 and 5108 (available from Japan Synthetic Rubber), Zirkon™ (available from Shipley Microelectronics, a division of Rohm and Haas), and porous low-k (ELk) materials (available from Applied Materials). Examples of carbon-doped silicon dioxide materials, or organosilanes, include Black Diamond™ (available from Applied Materials) and Coral™ (available from Lam Research). An example of an HSQ material is FOx™ (available from Dow Corning).

FIG. 5also shows forming a contact opening176to silicided source/drain region112through CESL170and dielectric layer174. Contact opening176may be formed using photolithography. i.e., with a mask178(in phantom) which can be removed in a conventional manner once opening176is formed. As illustrated, a portion of contact opening176is positioned over spacer160such that the spacer prevents punch through into STI110. In this fashion, spacer160accommodates mis-alignment of contact opening176with silicided source/drain region112or oversizing of contact opening176, and prevents punch through into STI110.

FIG. 6shows forming a contact180in contact opening176. Contact180forming may include depositing a liner182in contact opening176, then depositing a conductor182in contact opening176and planarizing the conductor. Liner182may include any conventional liner material such as ruthenium; however, other refractory metals such as tantalum (Ta), titanium (Ti), tungsten (W), iridium (Ir), rhodium (Rh) and platinum (Pt), etc., or mixtures of thereof, may also be employed. Conductor182may include, for example, copper or tungsten. The planarizing can be carried out using any now known or later developed technique such as but not limited to chemical mechanical planarization (CMP).FIG. 6also shows, in phantom, conventional forming of back-end-of-line (BEOL) interconnects190to contact180.

It is emphasized that method of forming contact180may include any variety of intermediate steps not described herein but understood with those with skill on the art.

FIG. 6shows a semiconductor structure200according to embodiments of the disclosure. Semiconductor structure200includes SOI substrate104with STI110isolating silicided source/drain region112in active region102of the SOI substrate from another region (over STI and beyond to right) of the SOI substrate. Silicided source/drain region112is adjacent to STI110, and has edge146therewith. Spacer160is positioned at edge146of silicided source/drain region112adjacent to STI110, and prevents edge punch through as described herein. Spacer may include, for example, silicon nitride. Semiconductor structure200also includes contact180to silicided source/drain region112. Silicided source/drain region180may include raised source/drain regions128,130(FIG. 1), extending adjacent gate132. As shown, at least a portion of contact180lands over spacer160—the rest lands on silicided source/drain region112. CESL170is adjacent spacer160and over STI110, and dielectric layer174is over CESL170. A dummy gate154may be provided over STI110. Spacer160may have a thickness of, for example, approximately 10 to approximately 20 nanometers, but may vary depending on the technology node. In another example, spacer160may have a thickness of approximately 15 nanometers, but in any event has a thickness such that no gap exists therebelow.

The methods of forming a contact herein provide a cost effective manner of mitigating edge punch through with no additional masks and with minor additional processing involved. The additional processing steps do not significantly increase processing time.