SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF

A memory circuit includes an array including a plurality of memory cells arranged across a plurality of columns and a plurality of voltage control circuits, each of the plurality of voltage control circuits operatively coupled to the memory cells of a corresponding one of the plurality of columns. Each of the plurality of voltage control circuits includes a first portion configured to provide a first voltage drop in coupling a supply voltage to the memory cells of the corresponding column and a second portion configured to provide a second voltage drop in coupling the supply voltage to the memory cells of the corresponding column. The first voltage drop is substantially smaller than the second voltage drop.

BACKGROUND

DETAILED DESCRIPTION

A traditional memory device can suffer from write ability issues (e.g., weak write issues due to fighting of a P-type transistor and an N-type transistor). The write ability could be improved using, for example, negative bit lines, which however, consume large area and energy. As disclosed herein, by implementing a voltage control circuit (e.g., SPVD) to supply a voltage drop, the write margin and noise margin of the memory device can be improved, thereby allowing for improved stability and reliability of the memory device operations.

Techniques disclosed herein are related to a voltage control circuit for a memory device. The memory device can include an array including memory cells arranged across columns, and the voltage control circuit can be coupled to one or more of the memory cells of a corresponding one of the columns. In various embodiments, the voltage control circuit may supply the coupled memory cells with an intentional voltage drop based on a self-power voltage drop (SPVD) scheme. With the intentional voltage drop, a write margin of the coupled memory cells can be advantageously increased. The voltage control circuit can include a first portion (e.g., a weak header) configured to provide a first voltage drop in coupling a supply voltage to the corresponding memory cells, and a second portion (e.g., a strong header) configured to provide a second voltage drop in coupling the supply voltage to the corresponding memory cells. In various embodiments, the first voltage drop can be substantially larger than the second voltage drop. In various embodiments, the second portion (e.g., the strong header) can be selectively deactivated (e.g., when the memory cells are selected to be written), which causes the selected memory cells to receive (or otherwise operate) under a relatively low supply voltage. As disclosed herein, this improves the write ability of the memory device. The voltage drop (e.g., CVDD IR drop) can be selectively provided when a write contention current occurs at a weak writability cell, such that a larger IR drop occurs at the P-type transistor of the cell to suppress the strength the P-type transistor, thereby helping the write margin. For example, the voltage drop can be provided when a severe write contention happens at the worst writability cell. Further, while sharing a retention header, a weak header of the voltage control circuit can hold a static noise margin (SNM) for those un-selected cells without requiring an overhead area. This provides area/energy efficient solutions over a conventional memory device. In some embodiments, the techniques disclosed herein can improve an area efficiency up to <1% due to simple logic and timing control, in comparison to a negative bit line scheme (e.g., >3%).

FIG.1illustrates a block diagram of an example memory device100, in accordance with some embodiments. The memory device100includes a memory controller105and a memory array120. The memory array120may include a plurality of storage circuits or memory cells125arranged in two- or three-dimensional arrays. Each memory cell125may be coupled to a corresponding word line WL and a corresponding bit line BL. The memory controller105may write data to or read data from the memory array120according to electrical signals through word lines WL and bit lines BL. In other embodiments, the memory device100includes more, fewer, or different components than shown inFIG.1.

The memory array120is a hardware component that stores data. In one aspect, the memory array120is embodied as a semiconductor memory device. The memory array120includes a plurality of storage circuits or memory cells125. The memory array120includes word lines WL0, WL1. . . . WLJ, each extending in a first direction (e.g., X-direction) and bit lines BL0, BL1. . . . BLK, each extending in a second direction (e.g., Y-direction). The word lines WL and the bit lines BL may be conductive metals or conductive rails. In one configuration, each memory cell125is coupled to a corresponding word line WL and a corresponding bit line BL, and can be operated according to voltages or currents through the corresponding word line WL and the corresponding bit line BL. In some embodiments, each bit line includes bit lines BL, BLB coupled to one or more memory cells125of a group of memory cells125disposed along the second direction (e.g., Y-direction). The bit lines BL, BLB may receive and/or provide differential signals. Each memory cell125may include a volatile memory, a non-volatile memory, or a combination of them. In some embodiments, each memory cell125is embodied as a static random access memory (SRAM) cell or other type of memory cell. In some embodiments, the memory array120includes additional lines (e.g., select lines, reference lines, reference control lines, power rails, etc.).

The memory controller105is a hardware component that controls operations of the memory array120. In some embodiments, the memory controller105includes a bit line controller112, a word line controller114, and a timing controller110. The bit line controller112, the word line controller114, and the timing controller110may be embodied as logic circuits, analog circuits, or a combination thereof. In one configuration, the word line controller114is a circuit that provides a voltage or current through one or more word lines WL of the memory array120, and the bit line controller112is a circuit that provides or senses a voltage or current through one or more bit lines BL of the memory array120. In one configuration, the timing controller110is a circuit that provides control signals or clock signals to synchronize operations of the bit line controller112and the word line controller114. In some embodiments, the timing controller110is embodied as or includes a processor and a non-transitory computer readable medium storing instructions when executed by the processor cause the processor to execute one or more functions of the timing controller110or the memory controller105described herein. The bit line controller112may be coupled to bit lines BL of the memory array120, and the word line controller114may be coupled to word lines WL of the memory array120. In some embodiments, the memory controller105includes more, fewer, or different components than shown inFIG.1.

In some embodiments, the timing controller110may generate control signals to coordinate operations of the bit line controller112and the word line controller114. In some embodiments, to write data at a memory cell125, the timing controller110may cause the word line controller114to apply a voltage or current to the memory cell125through a word line WL coupled to the memory cell125and cause the bit line controller112to apply a voltage or current corresponding to data to be stored to the memory cell125through a bit line BL coupled to the memory cell125. In some embodiments, to read data from a memory cell125, the timing controller110may cause the word line controller114to apply a voltage or current to the memory cell125through a word line WL coupled to the memory cell125and cause the bit line controller112to sense a voltage or current corresponding to data stored by the memory cell125through a bit line BL coupled to the memory cell125.

FIG.2illustrates a schematic diagram of an example memory cell125, in accordance with some embodiments. In some embodiments, the memory cell125includes N-type transistors N1, N2, N3, N4and P-type transistors P1, P2. The N-type transistors N1, N2, N3, N4may be N-type metal-oxide-semiconductor field-effect transistors (MOSFET) or N-type fin field-effect transistors (FinFET). The P-type transistors P1, P2may be P-type MOSFET or P-type FinFET. These components may operate together to store a bit. In some embodiments, the memory cell125includes more, fewer, or different components than shown inFIG.2.

In some embodiments, the N-type transistors N3, N4include gate electrodes coupled to a word line WL. In some embodiments, a drain electrode of the N-type transistor N3is coupled to a bit line BL, and a source electrode of the N-type transistor N3is coupled to a port Q. In some embodiments, a drain electrode of the N-type transistor N4is coupled to a bit line BLB, and a source electrode of the N-type transistor N4is coupled to a port QB. In some aspects, the N-type transistors N3, N4operate as electrical switches. The N-type transistors N3, N4may allow the bit line BL to electrically couple to or decouple from the port Q and allow the bit line BLB to electrically couple to or decouple from the port QB, according to a voltage applied to the word line WL. For example, according to a supply voltage VDD (e.g., 1V) corresponding to a high state (e.g., logic value ‘1’) applied to the word line WL, the N-type transistor N3is enabled to electrically couple the bit line BL to the port Q and the N-type transistor N4is enabled to electrically couple the bit line BLB to the port QB. For another example, according to a ground voltage VSS (e.g., 0V) corresponding to a low state (e.g., logic value ‘0’) applied to the word line WL, the N-type transistor N3is disabled to electrically decouple the bit line BL from the port Q and the N-type transistor N4is disabled to electrically decouple the bit line BLB from the port QB.

In some embodiments, the N-type transistor N1includes a source electrode coupled to a first supply voltage rail supplying the ground voltage VSS or 0V, a gate electrode coupled to the port QB, and a drain electrode coupled to the port Q. In some embodiments, the P-type transistor P1includes a source electrode coupled to a second supply voltage rail supplying the supply voltage CVDD, a gate electrode coupled to the port QB, and a drain electrode coupled to the port Q. In some embodiments, the N-type transistor N2includes a source electrode coupled to the first supply voltage rail supplying the ground voltage VSS or 0V, a gate electrode coupled to the port Q, and a drain electrode coupled to the port QB. In some embodiments, the P-type transistor P2includes a source electrode coupled to the second supply voltage rail supplying the supply voltage CVDD, a gate electrode coupled to the port Q, and a drain electrode coupled to the port QB.

In some embodiments, the N-type transistor N1and the P-type transistor P1operate as an inverter, and the N-type transistor N2and the P-type transistor P2operate as an inverter, such that two inverters form cross-coupled inverters. In one aspect, the cross-coupled inverters may sense and amplify a difference in voltages at the ports Q, QB. When writing data, the cross-coupled inverters may sense voltages at the ports Q, QB provided through the N-type transistors N3, N4and amplify a difference in voltages at the bit lines BL, BLB. For example, the cross-coupled inverters sense a voltage 0.5 V at the port Q and a voltage 0.4V at the port QB, and amplify a difference in the voltages at the ports Q, QB through a positive feedback (or a regenerative feedback) such that the voltage at the port Q becomes the supply voltage VDD (e.g., 1V) and the voltage at the port QB becomes the ground voltage VSS (e.g., 0V). The amplified voltages at the ports Q, QB may be provided to the bit lines BL, BLB through the N-type transistors N3, N4, respectively for reading.

As shown, the source electrode of the P-type transistor P1and the source electrode of the P-type transistor P2can be coupled to a voltage control circuit200(e.g., SPVD) to receive the supply voltage CVDD. The voltage control circuit200can provide the supply voltage CVDD (e.g., with a voltage drop) to the P-type transistors P1and/or P2. In some embodiments, the voltage control circuit200can supply the supply voltage CVDD with a voltage drop to the P-type transistors P1and/or P2, when a write contention current occurs, thereby suppressing the strength the corresponding P-type transistor and improving the write margin.

FIG.3illustrates a partial view30of an example memory device, in accordance with some embodiments. More specifically, the partial view30may be a column of a plurality of columns of the memory array120, in which a voltage control circuit300is operatively coupled to a plurality of memory cells (e.g.,125-1,125-2, . . .125-N) of the column. The plurality of memory cells125-1,125-2, . . .125-N may be substantially similar to or incorporate features of the memory cell125inFIG.2. The voltage control circuit300may be substantially similar to or incorporate features of the voltage control circuit200,300. Although a single column of the memory array120is depicted, the memory device can include a plurality of voltage control circuits300, each of which is operatively coupled to the memory cells of a corresponding one of the plurality of columns of the memory array120. The voltage control circuit300can provide a supply voltage CVDD (e.g., with a voltage drop) to the memory cells (e.g.,125-1,125-2, . . .125-N).

The voltage control circuit300includes a first portion301configured to provide a first voltage drop in coupling the supply voltage CVDD to the memory cells (e.g.,125-1,125-2, . . .125-N). The voltage control circuit300includes a second portion302configured to provide a second voltage drop in coupling the supply voltage CVDD to the memory cells (e.g.,125-1,125-2, . . .125-N). In some embodiments, the first voltage drop is substantially smaller than the second voltage drop. In some embodiments, the first portion301is associated with (e.g., coupled to) a first resistance, and the second portion302is associated with (e.g., coupled to) a second resistance. That is, the first resistance can be substantially smaller than the second resistance, such that a voltage drop (e.g., IR drop) associated with the CVDD of the first portion301is substantially smaller than that of the second portion302.

In some embodiments, the first portion301can be configured to selectively couple the supply voltage CVDD to each of the memory cells (e.g.,125-1,125-2, . . .125-N) while the second portion can be configured to couple the supply voltage CVDD to each of the first memory cells (e.g.,125-1,125-2, . . .125-N). For example, the first portion301can be configured to selectively couple the supply voltage CVDD to each of the memory cells (e.g.,125-1,125-2, . . .125-N) while the second portion can be configured to always couple the supply voltage CVDD to each of the first memory cells (e.g.,125-1,125-2, . . .125-N). In some embodiments, the second portion302can be activated, while the first portion301can be selectively deactivated in response to the corresponding column being selected. For example, the second portion302can be always activated, while the first portion301can be selectively deactivated in response to the corresponding column being selected. For examples, each first portion301of a first set of voltage control circuits300coupled to a first set of columns of the memory array120can be deactivated, while each first portion301of a second set of voltage control circuits300coupled to a second set of columns of the memory array120can be activated.

In some embodiments, the first portion301may include a P-type transistor gated based on a logic combination of a first control signal and a second control signal. In some embodiments, the first control signal may be a write data signal WC and the second control signal may be a precharge signal WT. In some embodiments, the first control signal may be a write enable signal YW (not shown) and a bit write enable signal BWE (not shown).

FIG.4illustrates a partial view40of an example memory device, in accordance with some embodiments. More specifically, the partial view40may be a column of a plurality of columns of the memory array120, in which a voltage control circuit400is operatively coupled to a plurality of memory cells of the column. The voltage control circuit400may be substantially similar to or incorporate features of the voltage control circuit200,300. Although a single column of the memory array120is depicted, the memory device can include a plurality of voltage control circuits400, each of which is operatively coupled to the memory cells of a corresponding one of the plurality of columns of the memory array120. Alternatively or additionally (e.g., as opposed to the voltage control circuit300ofFIG.3), the voltage control circuit400can be disposed between a first row401and a second row402of the corresponding column.

It should be noted that the voltage control circuits can be arranged in various ways, and that shown in the disclosure is merely a non-limiting example. For example, as shown inFIG.5, a memory array can include both the voltage control circuit300(coupled at a bottom portion of the column) and the voltage control circuit400(coupled between a first row and a second row) in a same column. For example, the arrangement of voltage control circuits in a first column may be different from the arrangement of voltage control circuits in a second column.

FIG.5illustrates a partial view50of an example memory device, in accordance with some embodiments. More specifically, the partial view50may be a first column501and a second column502of a plurality of columns of the memory array120, in which voltage control circuits500,505,510,515are operatively coupled to a plurality of memory cells of the respective column. The voltage control circuits500,505,510,515may be substantially similar to or incorporate features of the voltage control circuit200,300. As shown, the voltage control circuits500,505can be operably coupled to the first column501, and the voltage control circuits510,515can be operably coupled to the second column502. Likewise, one or more of a plurality of voltage control circuits can be operatively coupled to the memory cells of a corresponding one of the plurality of columns.

FIGS.6A,6B,6C, and6Dillustrate partial views61,63,65, and67of example memory devices, respectively, in accordance with some embodiments. More specifically, each of the partial views61,63,65,67may be a column of a plurality of columns of the memory array120, in which each of voltage control circuits610,630,650,670is operatively coupled to a plurality of memory cells of the corresponding column, respectively. The voltage control circuits610,630,650,670may be substantially similar to or incorporate features of the voltage control circuit200,300. As shown, the voltage control circuit610includes a first portion611and a second portion612; the voltage control circuit630includes a first portion631and a second portion632; the voltage control circuit650includes a first portion651and a second portion652; the voltage control circuit670includes a first portion671and a second portion672. The first portions611,631,651,671may be substantially similar to or incorporate features of the first portion301. The second portions612,632,652,672may be substantially similar to or incorporate features of the second portion302.

Referring toFIG.6A, the second portion612can include a plurality of P-type transistors serially coupled to each other. For example, the second portion612can include a plurality of P-type transistors stacked to one another. Each gate electrode of the stacked P-type transistors can be connected to a ground voltage VSS, while a source/drain end of the serially coupled P-type transistors is connected to a power supply voltage VDD. Although the second portion612shows three P-type transistors, the second portion612can include any number of P-type transistors.

Referring toFIG.6B, the second portion632can include a diode-connected transistor. For example, the second portion632can include a diode-connected N-type transistor. For example, the second portion632can include a diode-connected P-type transistor. A source/drain end of the diode-connected transistor is connected to a power supply voltage VDD.

Referring toFIG.6C, the second portion652can include an N-type transistor gated by a fixed voltage. A source/drain end of the transistor gated by a fixed voltage is connected to a power supply voltage VDD.

Referring toFIG.6D, the second portion672can include a P-type transistor gated by a fixed voltage. A source/drain end of the transistor gated by a fixed voltage is connected to a power supply voltage VDD.

In some embodiments, although not depicted, a second portion (e.g.,302) of a voltage control circuit (e.g.,200) can include any combination of a P-type transistor, an N-type transistor, a diode, etc. and/or any connection with VSS/VDD. A non-limiting example may be the second portion including at least one of: a P-type transistor gated by a fixed voltage or connected to a plurality of P-type transistors, or an N-type transistor gated by a fixed voltage or connected to a diode.

FIG.7Aillustrates a partial view70of an example memory device, in accordance with some embodiments. More specifically, the partial view70may be a column of a plurality of columns of the memory array120, in which a voltage control circuit700is operatively coupled to a plurality of memory cells of the column. The voltage control circuit700may be substantially similar to or incorporate features of the voltage control circuit200,300,610, etc. The voltage control circuit700can include a first portion711and a second portion712that includes at least one transistor. In some embodiments, the second portion712is gated by a write data signal WC and a precharge signal WT while connected to a power supply voltage VDD.

FIG.7Billustrates an example waveform750associated with an example memory device, in accordance with some embodiments. More specifically, the waveform750is associated with a first state of the memory cells shown in the partial view70. When at least one of the memory cells in the partial view70is selected to be written (e.g., when the corresponding row is activated), one of the first control signal (e.g., WT) or the second control signal (e.g., WC) is asserted to a logic high and the other of the first control signal or the second control signal is asserted to a logic low, thereby deactivating the first portion711. For example, as shown in FIG.7B, the precharge signal WT is asserted to a logic low (e.g., 0), which asserts the bit line BLB, and the write data signal WC is asserted to a logic high (e.g., 1), which asserts the bit line BL, thereby deactivating the first portion711. That is, for the selected memory cell to operate in a write operation, the first portion711can be deactivated by the first control signal and the second control signal. The deactivation of the first portion711can decouple a supply voltage from the memory cells in the corresponding column.

Although not depicted, when the memory cell is in a second state (e.g., selected to be read), both the first control signal (e.g., WT) and the second control signal (e.g., WC) are asserted to a logic high, thereby activating the first portion811. For example, both the precharge signal WT and the write data signal WC are asserted to a logic high (e.g., 1), which assert the bit lines BL, BLB, thereby activating the first portion711. That is, for the selected memory cell to operate in a read operation, the first portion711can be selectively activated by the first control signal and the second control signal. The activation of the first portion711can couple a supply voltage to each of the memory cells in the corresponding column.

FIG.8Aillustrates a partial view80of an example memory device, in accordance with some embodiments. More specifically, the partial view80may be a column of a plurality of columns of the memory array120, in which a voltage control circuit800is operatively coupled to a plurality of memory cells of the column. The voltage control circuit800may be substantially similar to or incorporate features of the voltage control circuit200,300,610,630,650, etc. The voltage control circuit800can include a first portion811and a second portion812that includes at least one transistor. In some embodiments, the second portion812includes a first transistor connected to a diode and a second transistor gated by a fixed voltage.

FIG.8Billustrates an example waveform850associated with an example memory device, in accordance with some embodiments. More specifically, the waveform850is associated with a first state of the memory cells shown in the partial view70. When at least one of the memory cells in the partial view80is selected to be written (e.g., when the corresponding row is activated), one of the first control signal (e.g., WT) or the second control signal (e.g., WC) is asserted to a logic high and the other of the first control signal or the second control signal is asserted to a logic low, thereby deactivating the first portion811. For example, as shown inFIG.8B, the precharge signal WT is asserted to a logic low (e.g., 0), which asserts the bit line BLB, and the write data signal WC is asserted to a logic high (e.g., 1), which asserts the bit line BL, thereby deactivating the first portion811. That is, for the selected memory cell to operate in a write operation, the first portion811can be deactivated by the first control signal and the second control signal. The deactivation of the first portion811can decouple a supply voltage from the memory cells in the corresponding column.

In some embodiments, the precharge signal WT and the write data signal WC can be asserted according to the bias signal Vbias, such that the precharge signal WT or the write data signal WC is asserted to a logic high when the bias signal Vbias is asserted to a logic high.

Although not depicted, when the memory cell is in a second state (e.g., selected to be read), both the first control signal (e.g., WT) and the second control signal (e.g., WC) are asserted to a logic high, thereby activating the first portion811. For example, both the precharge signal WT and the write data signal WC are asserted to a logic high (e.g., 1), which assert the bit lines BL, BLB, thereby activating the first portion811. That is, for the selected memory cell to operate in a read operation, the first portion811can be selectively activated by the first control signal and the second control signal. The activation of the first portion811can couple a supply voltage to each of the memory cells in the corresponding column.

FIG.9Aillustrates a partial view90of an example memory device, in accordance with some embodiments. More specifically, the partial view90may be columns of the memory array120. A first column91includes a voltage control circuit910that includes a first portion911and a second portion912. The voltage control circuit910is coupled to memory cells of the first column91and provides a supply voltage CVDD [0]. A second column92includes a voltage control circuit920that includes a first portion921and a second portion922. The voltage control circuit920is coupled to memory cells of the second column92and provides a supply voltage CVDD [1]. The voltage control circuits910,920may be substantially similar to or incorporate features of the voltage control circuit200,300.

In some embodiments, the first portions911,921may include a P-type transistor gated based on a logic combination of a first control signal WT and a second control signal WC. As shown inFIG.9A, the first portion911of the first column91includes a P-type transistor915gated based on a logic combination of a first control signal WT[0] and a second control signal WC[0]; and the first portion921of the second column92includes a P-type transistor925gated based on a logic combination of a first control signal WT[1] and a second control signal WC[1].

The first and second columns91,92of the memory device can be controlled by a column-based pulse (e.g., the first control signal WT, second control signal WC). As shown inFIG.9A, the first portion911of the first column91can receive the first control signal WT[0] with a logic high and the second control signal WC[0] with a logic low, thereby deactivating (e.g., turning off) the P-type transistor915, while the second portion912of the first column91provides the supply voltage CVDD[0] with a voltage drop (IR drop). In the second column92, the first portion921can receive the first control signal WT[1] with a logic high and the second control signal WC[1] with a logic high, thereby activating (e.g., turning on) the P-type transistor925. The first portion921and the second portion912of the second column92provide the supply voltage CVDD[1].

Although not depicted, in some embodiments, both of the first portion911and the first portion921can be deactivated/activated based on the control signals (e.g., WT[0], WC[0], WT[1], WC[1], etc.).

FIG.9Billustrates a partial view95of an example memory device, in accordance with some embodiments. The partial view95may be the partial view90, in which a logic circuit950is additionally coupled to the first portions911,921. The logic circuit950can receive a third signal and a fourth signal. In some embodiments, the third signal may be a write enable signal YW (or YWB). In some embodiments, the fourth signal may be a logic combination of a bit write enable signal BWE and a data input signal D (or a data input bar signal DB). In some embodiments, the memory device can include or operatively couple with a data input (DIN) to receive the data input signal D and/or the data input bar signal DB. Based on a logic combination of the third signal and the fourth signal, each of the first portions911,921can receive corresponding first and second control signals WC and WT.

FIG.10is a flow chart of an example method1000for operating an example memory device (e.g., memory device100), in accordance with some embodiments. In some embodiments, the method1000is performed by a controller (e.g., memory controller105). In some embodiments, the method1000is performed by other entities. In some embodiments, the method1000is performed to write data at a selected memory cell. In some examples, the method1000includes more, fewer, or different steps than shown inFIG.10. In some examples, the method1000can be performed in a different order than shown inFIG.10.

In a brief over view, the method1000can start with operation1010of selecting, based on a first logic combination of a first control signal and a second control signal, one of a plurality of columns of a memory array to write, wherein the column includes a plurality of memory cells. The method1000can continue to operation1020of deactivating, based on the first logic combination, a first portion of a voltage control circuit corresponding to the column, wherein the first portion of the voltage control circuit is configured to provide a first voltage drop in coupling a supply voltage to each of the memory cells. The method1000can continue to operation1030of keeping a second portion of the voltage control circuit activated, wherein the second portion of the voltage control circuit is configured to provide a second voltage drop in coupling the supply voltage to each of the memory cells.

At operation1010, a controller (e.g., memory controller105) can select, based on a first logic combination of a first control signal (e.g., first control signal WT) and a second control signal (e.g., first control signal WC), one of a plurality of columns of a memory array (e.g., memory array120) to write, wherein the column includes a plurality of memory cells (e.g., memory cell125). In some examples, the controller can control a memory cell to be read when one of the first control signal or the second control signal is asserted to a logic high and the other of the first control signal or the second control signal is asserted to a logic low. In some examples, the controller can control a memory cell to be written when both of the first control signal and the second control signal are asserted to a logic high, thereby activating the first portion.

At operation1020, the controller can deactivate, based on the first logic combination, a first portion (e.g., first portion301) of a voltage control circuit (e.g., voltage control circuit200) corresponding to the column, wherein the first portion of the voltage control circuit is configured to provide a first voltage drop in coupling a supply voltage (e.g., CVDD) to each of the memory cells.

At operation1030, the controller can maintain a second portion (e.g., second portion302) of the voltage control circuit activated, wherein the second portion of the voltage control circuit is configured to provide a second voltage drop in coupling the supply voltage to each of the memory cells.

In some embodiments, at any of operations1010,1020,1030, the controller can deselect, based on a second logic combination of the first control signal and the second control signal, the columns to write, and activate, based on the second logic combination, the first portion of the voltage control circuit, while keeping the second portion of the voltage control circuit activated.

In some embodiments, at any of operations1010,1020,1030, the column can further include a first bit line and a second bit line that are coupled to ground through a first write driver and a second write driver, and the first write driver and the second write driver are activated/deactivated by the first control signal and the second control signal, respectively.

In one aspect of the present disclosure, a memory circuit is disclosed. The memory circuit includes an array including a plurality of memory cells arranged across a plurality of columns; and a plurality of voltage control circuits, each of the plurality of voltage control circuits operatively coupled to the memory cells of a corresponding one of the plurality of columns; wherein each of the plurality of voltage control circuits includes: a first portion configured to provide a first voltage drop in coupling a supply voltage to the memory cells of the corresponding column; and a second portion configured to provide a second voltage drop in coupling the supply voltage to the memory cells of the corresponding column; wherein the first voltage drop is substantially smaller than the second voltage drop.

In another aspect of the present disclosure, a memory circuit is disclosed. The memory circuit includes a plurality of first memory cells arranged along a first column; and a first voltage control circuit coupled to each of the first memory cells and including a first portion and a second portion, wherein the first portion is configured to selectively couple a supply voltage to each of the first memory cells while the second portion is configured to couple the supply voltage to each of the first memory cells. The first portion is associated with a first resistance and the second portion is associated with a second resistance. The first resistance is substantially smaller than the second resistance.

In yet another aspect of the present disclosure, a method for operating a memory circuit is disclosed. The method includes selecting, based on a first logic combination of a first control signal and a second control signal, one of a plurality of columns of a memory array to write, wherein the column includes a plurality of memory cells; deactivating, based on the first logic combination, a first portion of a voltage control circuit corresponding to the column, wherein the first portion of the voltage control circuit is configured to provide a first voltage drop in coupling a supply voltage to each of the memory cells; and keeping a second portion of the voltage control circuit activated, wherein the second portion of the voltage control circuit is configured to provide a second voltage drop in coupling couple the supply voltage to each of the memory cells. The first voltage drop is substantially smaller than the second voltage drop.

As used herein, the terms “about” and “approximately” generally indicates the value of a given quantity that can vary based on a particular technology node associated with the subject semiconductor device. Based on the particular technology node, the term “about” can indicate a value of a given quantity that varies within, for example, 10-30% of the value (e.g., +10%, ±20%, or ±30% of the value).