Method of making MOSFET integrated with schottky diode with simplified one-time top-contact trench etching

Method for fabricating MOSFET integrated with Schottky diode (MOSFET/SKY) is disclosed. Gate trench is formed in an epitaxial layer overlaying semiconductor substrate, gate material is deposited therein. Body, source, dielectric regions are successively formed upon epitaxial layer and the gate trench. Top contact trench (TCT) is etched with vertical side walls defining Schottky diode cross-sectional width SDCW through dielectric and source region defining source-contact depth (SCD); and partially into body region by total body-contact depth (TBCD). A heavily-doped embedded body implant region (EBIR) of body-contact depth (BCD)<TBCD is created into side walls of TCT and beneath SCD. An embedded Shannon implant region (ESIR) is created into sub-contact trench zone (SCTZ) beneath TCT floor. A metal layer is formed in contact with ESIR, body and source region. The metal layer also fills TCT and covers dielectric region thus completing the MOSFET/SKY with only one-time etching of its TCT.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a Continuation-in-Part (CIP) of a commonly owned pending US application entitled “Integrated MOSFET Device and Method with Reduced Kelvin Contact Impedance and Breakdown Voltage”, by Ji Pan with application Ser. No. 13/306,067, filing date Nov. 29, 2011, by now published on Mar. 22, 2012 with publication number US20120068262, whose content, hereinafter referred to as APOM063, is herein incorporated by reference for any and all purposes.

In addition, this application is related to the following US patent documents whose contents are herein also incorporated by reference for any and all purposes:[A] Entitled “Power MOS Device” with application Ser. No. 11/056,346 filed on Feb. 11, 2005 and issued on Oct. 23, 2007 as U.S. Pat. No. 7,285,822, hereinafter referred to as ALPHP004.[B] Entitled “MOS DEVICE WITH INTEGRATED SCHOTTKY DIODE IN ACTIVE REGION CONTACT TRENCH” with application Ser. No. 12/005,146 filed on Dec. 21, 2007 and issued on Jan. 10, 2012 as U.S. Pat. No. 8,093,651, hereinafter referred to as ALPHP005.[C] Entitled “MOS DEVICE WITH SCHOTTKY BARRIER CONTROLLING LAYER” with application Ser. No. 12/005,166 filed on Dec. 21, 2007, hereinafter referred to as ALPHP008.[D] Entitled “MOS DEVICE WITH LOW INJECTION DIODE” with application Ser. No. 12/005,130 filed on Dec. 21, 2007, hereinafter referred to as ALPHP009.

FIELD OF INVENTION

This invention relates generally to the field of semiconductor device structure. More specifically, the present invention is directed to a manufacturing method to form a MOSFET device integrated with a Schottky Diode (MOSFET/SKY).

BACKGROUND OF THE INVENTION

ALPHP004 disclosed a semiconductor MOSFET device, with associated manufacturing method, having a gate trench extending through its source and body into its drain, a gate disposed in the gate trench, a source body contact trench having a trench wall and an anti-punch through implant that is disposed along the trench wall. Corresponding to the existence of gate trench and source body contact trench, two contact etchings may be required for device manufacturing.

ALPHP005 disclosed a semiconductor MOSFET device, with associated manufacturing method, formed on a semiconductor substrate. The device comprises a drain, an epitaxial layer overlaying the drain, and an active region. The active region comprises, inter alia, a gate trench extending into the epitaxial layer and an active region contact trench extending through the MOSFET source and at least part of the MOSFET body into the drain. As illustrated inFIG. 4O(first contact etch) andFIG. 4R(second contact etch) with accompanying descriptive text in the ALPHP005 specification, two contact etchings are required for device manufacturing.

ALPHP008 disclosed a MOS device with integrated Schottky barrier controlling layer and ALPHP009 disclosed a MOS device with integrated low injection diode.

Thus, while the structure of a MOSFET device integrated with a Schottky Diode (MOSFET/SKY) is known in the art, the present invention is directed to its manufacturing method that is simplified and that also produces devices with more consistent device performance. More specifically, to those skilled in the art, it is not uncommon to see substantial trench geometrical tolerances around +/−10% resulting from contact etching. Multiple contact etching steps, in addition to complicating the manufacturing process, will compound thus aggravating the already substantial trench geometrical tolerances from a single contact etching. Therefore, the present invention deals with making an MOSFET/SKY with simplified one-time top-contact trench etching.

DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS

The description above and below plus the drawings contained herein merely focus on one or more currently preferred embodiments of the present invention and also describe some exemplary optional features and/or alternative embodiments. The description and drawings are presented for the purpose of illustration and, as such, are not limitations of the present invention. Thus, those of ordinary skill in the art would readily recognize variations, modifications, and alternatives. Such variations, modifications and alternatives should be understood to be also within the scope of the present invention.

FIG. 1illustrates a plane cross sectional view of a MOSFET integrated with Schottky diode (MOSFET/SKY)5. To facilitate description of spatial, structural relationships within the device, an X-Y-Z Cartesian coordinate system with the X-Y plane parallel to the major semiconductor chip plane is employed. The MOSFET/SKY5includes a drain that is formed on the back of an N+-type semiconductor substrate (SC ST)103. The drain region extends into an epitaxial layer (EPIL)104of N−-type semiconductor that overlays SCST103. Gate trenches such as111,113, and115are etched in EPIL104. A gate oxide layer121is formed inside the gate trenches. Gates131,133and135are disposed inside gate trenches111,113and115, respectively, and are insulated from the EPIL104by the gate oxide layer121. The gates131,133and135are made of a conductive material such as polycrystalline silicon (poly) and the gate oxide layer121is made of an insulating material such as thermal oxide. Specifically, gate trench111is located in a gate contact region while gate trenches113and115are located in an active device region.

Source regions150b-150dare embedded in body regions140b-140d, respectively. The source regions extend downward from the top surface of the body into the body itself. While body regions are implanted along the side surfaces of all gate trenches, source regions are only implanted next to active gate trenches. In this illustrated example, gates such as133have a gate top surface that extends substantially above the top surface of the body where the source is embedded. Such a configuration guarantees the overlap of the gate and the source, allowing the source region to be shallower than the source region of a device with a recessed gate, and increases device efficiency and performance. The amount by which the gate poly top surface extends above the source-body junction may vary for different embodiments. In some embodiments, the gates of the device do not extend above the top surface of the source-body region.

During operation, the drain region and the body regions together act as a diode, referred to as the body diode. A dielectric material layer160is disposed over the gate to insulate the gate from source-body contact. The dielectric material forms insulating regions such as160a-160con top of the gates as well as on top of the body and source regions. Appropriate dielectric materials include thermal oxide, low temperature oxide (LTO), boro-phospho-silicate glass (BPSG), etc.

A number of contact trenches such as112aare formed between the active gate trenches near the source and body regions. These trenches are referred to as active region contact trenches since the trenches are adjacent to the device's active region that is formed by the source and body regions. For example, the contact trench112aextends through the source and into the body, forming source regions150b-150cand body regions140b-140cadjacent to the trench. In contrast, a gate contact trench117, which is formed on top of gate131, is not located next to an active region, and therefore is not an active region contact trench. Trench117is referred to as a gate contact trench or gate runner contact trench since a metal layer172aconnected to the gate signal is deposited within the gate contact trench117. Gate signal is fed to active gates133and135through interconnections between gate trenches111,113and115in the third dimension (not shown). Metal layer172ais separated from metal layer172b, which connects to source and body regions through contact trench112ato supply a power source. In the example shown, the active region contact trench and gate contact trench have approximately the same depth. Notice the existence of contact barrier layers642at the undersides of the metal layers172aand172b. For those skilled in the art, these contact barrier layers can be made of Ti/TiN and function to make better and more reliable electrical contact at their respective metal-to-semiconductor interfaces.

In the example shown, regions such as170b-170cwithin the body and along the walls of the active region contact trench are heavily doped with P type material to form P+-type regions referred to as body contact implant regions. These body contact implants are included to ensure that Ohmic contact is formed between the body and the source metal therefore the source and the body have the same potential. Also, within the gate131and along the walls of the gate contact trench117are another heavily doped P+-type regions170ato achieve an Ohmic contact.

A conductive material is disposed in the contact trench112aas well as the gate contact trench117to form contact electrodes. At the interface between the contact trench112aand the EPIL104is an embedded P− type Shannon-implant region (ESIR)720a. Also, at the interface between the gate contact trench117and the gate131is another embedded P− type Shannon-implant region (ESIR)720b. While the ESIR720bdoes not provide significant electrical function, for those skilled in the art a Schottky diode652, in parallel with the body diode, is formed in the active region along the path of contact trench112a-ESIR720a-EPIL104. The Schottky diode652reduces the body diode's forward voltage drop and minimizes the stored charge, making the MOSFET more efficient. A single metal that is capable of simultaneously forming a Schottky contact to the N−drain (EPIL104) and forming good Ohmic contact to the P+body and N+source is used to fill the contact trench112aas well as the gate contact trench117. Metals such as titanium (Ti), platinum (Pt), palladium (Pd), tungsten (W) or any other appropriate material may be used. In some embodiments, metal layer172is made of aluminum (Al) or made of a Ti/TiN/Al stack.

FIG. 2A-FIG.2H illustrate process steps under the present invention for making the MOSFET/SKY device ofFIG. 1.FIG. 2Aillustrates the result of the following steps:a) Formation, in an epitaxial layer (EPIL)104overlaying a semiconductor substrate (SCST)103, of gate trenches111,113and115. Formation of a gate oxide layer121then deposition of gate materials131,133and135respectively inside the gate trenches111,113and115.b) Formation of body regions140a,140b,140c,140dand140e, in the EPIL104. Formation, with ion implantation, of source regions150a,150b,150cand150datop the body regions140b,140cand140d. Formation of an oxide layer362then formation of a dielectric material layer160atop the oxide layer362and above the gate trenches111,113and115and the source regions150a,150bc, and150d.
As a general remark about device dimensional control for ion implantation, it is a process step wherein the implantation thickness/depth is decided by implant energy and its following drive-in thermal budget. As an example for the creation of source regions150a,150bcand150d, a heavy dose of arsenic (As) ions could be implanted into a semiconductor silicon surface. Next, a source drive-in step makes the As ions diffuse inside the silicon with a depth around 0.2˜0.5 micron. For a more detailed breakdown and illustration of the above steps, reference can be made toFIG. 3AthroughFIG. 3Nand their accompanying descriptions of APOM063.

FIG. 2Billustrates the result of the following step:c) Anisotropically etching top contact trenches (TCT)700aand700bof equal top contact trench depth (TCTD) such that:c1) TCT700agoes through the dielectric material layer160and the source region150bc. Consequently the source region150bcis separated into source regions150band150ceach with a source-contact depth (SCD). Additionally, the dielectric material layer160is separated into insulating regions160a,160b, and160c.c2) TCT700agoes partially into the body regions140b,140cby a predetermined total body-contact depth (TBCD).
In addition, the vertical side walls of the TCT700adefine a Schottky diode cross-sectional width (SDCW), to be presently described in more detail.

FIG. 2CthroughFIG. 2Gillustrate the following steps:d1) Creation, into the side walls of TCT700aand700band beneath the SCD, a number of heavily-doped embedded body implant regions (EBIR)710a,710bof body-contact depth (BCD)<TBCD.d2) Creation, into a sub-contact trench zone (SCTZ) beneath the floor of TCT700aand700b, a number of embedded Shannon implant regions (ESIR)720a,720b.
Wherein,FIG. 2CthroughFIG. 2Fillustrate the following step:d11) Implantation of the heavily-doped EBIR710a,710bwhile keeping the SCTZ essentially free of any concomitant body-contact implantation.

FIG. 2Cillustrates the following step:d111) Formation of a lower spacer sub-layer (LSSL)620of horizontal wall thickness (HWTLS) atop the side walls of TCT700aand700band of vertical wall thickness (VWTLS) atop the bottom floor of TCT700aand700band atop the insulating regions160a,160b, and160c. Where VWTLSessentially equals to HWTLS.

FIG. 2Dillustrates the following steps:d112) Formation of an upper spacer sub-layer (USSL)622atop the (LSSL)620. The USSL622has a horizontal wall thickness (HWTUS) atop the side walls of the TCT (700aand700b). The USSL622has a lower vertical wall thickness (LVWTUS) atop the bottom floor of the TCT and has an upper vertical wall thickness (UVWTUS) atop the dielectric material layer160. It is important to point out that, while UVWTUSis essentially equal to HWTUS, LVWTUSis made much bigger than HWTUS.d113) Furthermore, selecting the LSSL material and the USSL material such that:the LSSL620would allow a through-transmission of a later body-implant beam while the USSL622would, with a sufficiently large layer thickness, block a through-transmission of the later body-implant beam; and the LSSL620acts as an etch-stop for a later USSL-etching step.
In one particular embodiment that satisfies the above steps, the LSSL material is silicon nitride and the USSL material is high density plasma deposited silicon oxide (HDPSO) that, owing to its deposition process, automatically satisfies the criterion LVWTUS>>HWTUS. As a more specific example on device geometry, VWTLScan be from 100 to 500 Angstrom, UVWTUScan be less than 0.1 micron while LVWTUScan be from 0.3 to 0.4 micron.

FIG. 2Eillustrates the following step:d114) Implanting, through a combined wall thickness of HWTUS+HWTLSnear the bottom of the top contact trenches (TCT)700aand700b, a number of heavily-doped embedded body implant regions (EBIR)710aand710b. Meanwhile, owing to the relationship LVWTUS>>HWTUS, the sub-contact trench zone (SCTZ) beneath the floor of TCT700ais kept essentially free of any concomitant body-contact implantation.
The associated implantation beams are illustrated as body-implant beams616oriented, for aiming at the EBIR710aand710b, at a planetary body-implant tilt angle (BITA) with respect to the Z-axis. In one embodiment the planetary BITA is from 15 to 30 degrees and the EBIR710aand710bare in the form of P+ type pockets located on silicon sidewalls of the TCT700aand700band are formed by implanting heavy boron beams. The P+ type pockets will then diffuse into the silicon with some thermal activation drive-in.

As an important remark, the P+ type EBIR710aand710bcannot be allowed to concomitantly reach thus bridging and electrically shorted to the SCTZ. Otherwise, an additional, thus undesirable, etching step of the TCT would be required to remove the bridging P+ type EBIR. In one practical example illustrating the significance of this remark, the implantation dosage of boron ions for the heavily-doped EBIR710ais about 1×e15 cm−2to form a resulting P+ type body contact. However, the implantation dosage of boron ions for the later ESIR720ais, for controlling leakage current through its Schottky barrier, only about 1×e12 cm−2that is three orders of magnitude lower than 1×e15 cm−2. Therefore, the SCTZ beneath the floor of TCT700ashould be kept essentially free of any significant concomitant body-contact implantation. Recall from the description ofFIG. 2Dthat LVWTUS>>HWTUS. While the combined thicknesses of the upper and lower extreme boundaries (HWTUSand HWTLS) is not enough to block the body-implant beams616from concomitantly implanting into the lower corner areas of the TCT700aand the SCTZ, the thick LVWTUSmade of HDP is, as illustrated, sufficient to block the body-implant beams616from concomitantly implanting into the lower corner areas of the TCT700aand the SCTZ. In a preferred embodiment, the ratio LVWTUS/HWTUSshould be higher than 3/1.

FIG. 2Fillustrates the following step:d115) Successively removing the USSL622with an USSL-etching step and removing the LSSL620with a LSSL-etching step.
While only the HDP is needed to block the body-implant beams616from reaching the SCTZ as just described above, the LSSL620is still needed as it functions as an etching stop for the USSL-etching. In a particular embodiment, LSSL620is made of silicon nitride.

FIG. 2Gillustrates the following step:d21) Simultaneously implanting the P− type ESIR720ainto the SCTZ and the P− type ESIR720binto the gate131.
The associated implantation beams are illustrated as Shannon-implant beam720oriented, for aiming at the ESIR720aand720b, at a planetary Shannon-implant tilt angle (SITA) with respect to the Z-axis. In one embodiment the planetary SITA is from 7 to 15 degrees and the ESIR720aand720bare in the form of P− type pockets located beneath the bottom floors of the TCT700aand700band the ESIR720ais formed by lightly implanting boron beams into the N− type EPIL104. The P− type pockets will then diffuse into the silicon with some thermal activation drive-in.

FIG. 2Hillustrates the formation of a metal layer640in contact, via a contact barrier layer642, with the ESIR (720a,720b), the heavily-doped EBIR (710a,710b), the body regions (140b,140c) and the source regions (150b,150c). Furthermore, the metal layer640fills the TCT (700a,700b) and covers the insulating regions (160a,160b,160c). A desired MOSFET integrated with Schottky diode (MOSFET/SKY)5is thus formed, with only one-time etching of its TCT700a,700b, wherein an integrated Schottky diode652, illustratively delineated with a dashed border, is structured as a serial connection of the metal layer640, the ESIR720aand the EPIL104. Thus, the vertical side walls of the TCT700adefine a Schottky diode cross-sectional width (SDCW). Notice that the metal layer640is patterned into segments separately contacting the active MOSFET and the gate131. Additionally, the P+ type EBIR710bin the gate131now turns into a gate contact electrode.

The steps for forming the metal layer640itself are known to those skilled in the art and comprise depositing titanium/titanium nitride (Ti/TiN), forming a titanium silicide and filling the metal layer. An upward, vertical cross sectioning of the Schottky diode652would successively go through the following material layers:1. N+ type silicon SCST103.2. N− type silicon EPIL104.3. P− type silicon ESIR720a.4. Silicide.5. Titanium nitride TiN.6. Metal (aluminum, copper, etc.).
In the above, a Schottky barrier (of the Schottky diode652) is formed between layers 4 and 3.

While the description above contains many specificities, these specificities should not be construed as accordingly limiting the scope of the present invention but as merely providing illustrations of numerous presently preferred embodiments of this invention. Throughout the description and drawings, numerous exemplary embodiments were given with reference to specific configurations. It will be appreciated by those of ordinary skill in the art that the present invention can be embodied in numerous other specific forms and those of ordinary skill in the art would be able to practice such other embodiments without undue experimentation. The scope of the present invention, for the purpose of the present patent document, is hence not limited merely to the specific exemplary embodiments of the foregoing description, but rather is indicated by the following claims. Any and all modifications that come within the meaning and range of equivalents within the claims are intended to be considered as being embraced within the spirit and scope of the present invention.