Three-dimensional memory device including discrete charge storage elements and methods of forming the same

An alternating stack of disposable material layers and silicon nitride layers is formed over a substrate. Memory openings are formed through the alternating stack, and memory opening fill structures are formed in the memory openings, wherein each of the memory opening fill structures comprises a charge storage material layer, a tunneling dielectric layer, and a vertical semiconductor channel Laterally-extending cavities are formed by removing the disposable material layers selective to the silicon nitride layers and the memory opening fill structures. Insulating layers comprising silicon oxide are formed by oxidizing surface portions of the silicon nitride layers and portions of the charge storage material layers that are proximal to the laterally-extending cavities. Remaining portions of the charge storage material layers form vertical stacks of discrete charge storage elements. Remaining portions of the silicon nitride layers are replaced with electrically conductive layers.

FIELD

The present disclosure relates generally to the field of semiconductor devices, and particularly to a three-dimensional memory device including discrete charge storage elements and methods of manufacturing the same.

BACKGROUND

SUMMARY

According to an aspect of the present disclosure, a three-dimensional memory device is provided, which comprises: an alternating stack of insulating layers and electrically conductive layers located over a substrate; memory openings vertically extending through the alternating stack; and memory opening fill structures located in the memory openings, wherein: each of the memory opening fill structures comprises a vertical semiconductor channel and a memory film; and the memory film comprises a tunneling dielectric layer and a vertical stack of discrete charge storage elements that are vertically spaced apart from each other by lateral protrusion portions of a subset of the insulating layers.

According to another aspect of the present disclosure, a method of forming a three-dimensional memory device is provided, which comprises: forming an alternating stack of disposable material layers and silicon nitride layers over a substrate; forming memory openings through the alternating stack; forming memory opening fill structures in the memory openings, wherein each of the memory opening fill structures comprises a charge storage material layer, a tunneling dielectric layer, and a vertical semiconductor channel; forming laterally-extending cavities by removing the disposable material layers selective to the silicon nitride layers and the memory opening fill structures; and forming insulating layers comprising silicon oxide by performing an oxidation process that oxidizes surface portions of the silicon nitride layers and portions of the charge storage material layers that are proximal to the laterally-extending cavities, wherein remaining portions of the charge storage material layers form a vertical stack of discrete charge storage elements in each of the memory opening fill structures; and replacing remaining portions of the silicon nitride layers with replacement material portions that comprise electrically conductive layers.

According to an aspect of the present disclosure, a method of forming a three-dimensional memory device is provided, which comprises: forming an alternating stack of insulating layers and spacer material layers over a substrate, wherein the spacer material layers are formed as, or are subsequently replaced with, electrically conductive layer; forming a memory opening through the alternating stack; forming annular lateral recesses at levels of the insulating layers by laterally recessing sidewalls of the insulating layers relative to sidewalls of the spacer material layers around the memory opening; forming a vertical stack of discrete metal portions in the annular lateral recesses; forming a semiconductor material layer on the vertical stack of the metal portions; forming a vertical stack of metal-semiconductor alloy portions by reacting the vertical stack of metal portions with portions of the semiconductor material layer located at levels of the insulating layers; removing the vertical stack of metal-semiconductor alloy portions selective to unreacted portions of the semiconductor material layer, wherein unreacted portions of the semiconductor material layer remain at levels of the spacer material layers and comprise a vertical stack of discrete semiconductor material portions; and forming a tunneling dielectric layer and a vertical semiconductor channel in the memory opening.

According to another aspect of the present disclosure, a three-dimensional memory device is provided, which comprises: an alternating stack of insulating layers and electrically conductive layers located over a substrate; a memory opening vertically extending through the alternating stack, wherein the memory opening has laterally-protruding portions that extend outward at each level of the insulating layers; and a memory opening fill structure located in the memory opening and comprising, from outside to inside, a blocking dielectric layer, charge storage structures comprising a vertical stack of discrete semiconductor material portions and at least one silicon nitride material portion in contact with the vertical stack, a tunneling dielectric layer in contact with the charge storage structures, and a vertical semiconductor channel.

According to yet another aspect of the present disclosure, a three-dimensional memory device is provided, which comprises: an alternating stack of insulating layers and electrically conductive layers located over a substrate; a memory opening vertically extending through the alternating stack, wherein the memory opening has laterally-protruding portions that extend outward at levels of the insulating layers; and a memory opening fill structure located in the memory opening and comprising, from outside to inside, a blocking dielectric layer, a vertical stack of discrete charge storage material portions, a tunneling dielectric layer, and a vertical semiconductor channel, wherein each charge storage material portion comprises a tubular portion located at a level of a respective one of the electrically material layers, an upper flange portion laterally extending outward from an upper end of an outer sidewall of the tubular portion, and a lower flange portion laterally extending outward from a lower end of the outer sidewall of the tubular portion.

According to still another aspect of the present disclosure, a method of forming a three-dimensional memory device is provided, which comprises: forming an alternating stack of insulating layers and spacer material layers over a substrate, wherein the spacer material layers are formed as, or are subsequently replaced with, electrically conductive layer; forming a memory opening through the alternating stack; forming annular lateral recesses at levels of the insulating layers by laterally recessing sidewalls of the insulating layers relative to sidewalls of the spacer material layers around the memory opening; forming a vertical stack of discrete metal portions in the annular lateral recesses; forming a semiconductor material layer on the vertical stack of the metal portions; removing the vertical stack of discrete metal portions and portions of the semiconductor material layer that are adjacent to the vertical stack of discrete metal portions, wherein remaining portions of the semiconductor material layer comprise a vertical stack of semiconductor material portions, and each of the semiconductor material portions comprises a tubular portion, an upper flange portion laterally extending outward from an upper end of an outer sidewall of the tubular portion, and a lower flange portion laterally extending outward from a lower end of the outer sidewall of the tubular portion; and forming a tunneling dielectric layer and a vertical semiconductor channel in the memory opening.

According to another aspect of the present disclosure, a three-dimensional memory device is provided, which comprises: an alternating stack of insulating layers and electrically conductive layers located over a substrate; a memory opening vertically extending through the alternating stack, wherein the memory opening has laterally-protruding portions that extend outward at levels of the insulating layers; and a memory opening fill structure located in the memory opening and comprising, from outside to inside, a blocking dielectric layer, a vertical stack of charge storage material portions, a tunneling dielectric layer, and a vertical semiconductor channel, and a vertical stack of discrete annular insulating material portions located at the levels of the insulating layers between the blocking dielectric layer and the tunneling dielectric layer.

DETAILED DESCRIPTION

As discussed above, the present disclosure is directed to a three-dimensional memory device including discrete charge storage elements and methods of manufacturing the same, the various aspects of which are described below. The embodiments of the disclosure can be employed to form various structures including a multilevel memory structure, non-limiting examples of which include semiconductor devices such as three-dimensional monolithic memory array devices comprising a plurality of NAND memory strings.

As used herein, a first surface and a second surface are “vertically coincident” with each other if the second surface overlies or underlies the first surface and there exists a vertical plane or a substantially vertical plane that includes the first surface and the second surface. A substantially vertical plane is a plane that extends straight along a direction that deviates from a vertical direction by an angle less than 5 degrees. A vertical plane or a substantially vertical plane is straight along a vertical direction or a substantially vertical direction, and may, or may not, include a curvature along a direction that is perpendicular to the vertical direction or the substantially vertical direction.

Referring toFIG.1, a first exemplary structure according to an embodiment of the present disclosure is illustrated, which can be employed, for example, to fabricate a device structure containing vertical NAND memory devices. The first exemplary structure includes a substrate (9,10), which can be a semiconductor substrate. The substrate can include a lower substrate semiconductor layer9and an optional upper substrate semiconductor layer10. The lower substrate semiconductor layer9maybe a semiconductor wafer or a semiconductor material layer, and can include at least one elemental semiconductor material (e.g., single crystal silicon wafer or layer), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. The substrate can have a major surface7, which can be, for example, a topmost surface of the lower substrate semiconductor layer9. The major surface7can be a semiconductor surface. In one embodiment, the major surface7can be a single crystalline semiconductor surface, such as a single crystalline semiconductor surface.

At least one semiconductor device700for a peripheral circuitry can be formed on a portion of the lower substrate semiconductor layer9. The at least one semiconductor device can include, for example, field effect transistors. For example, at least one shallow trench isolation structure720can be formed by etching portions of the lower substrate semiconductor layer9and depositing a dielectric material therein. A gate dielectric layer, at least one gate conductor layer, and a gate cap dielectric layer can be formed over the lower substrate semiconductor layer9, and can be subsequently patterned to form at least one gate structure (750,752,754,758), each of which can include a gate dielectric750, a gate electrode (752,754), and a gate cap dielectric758. The gate electrode (752,754) may include a stack of a first gate electrode portion752and a second gate electrode portion754. At least one gate spacer756can be formed around the at least one gate structure (750,752,754,758) by depositing and anisotropically etching a dielectric liner. Active regions730can be formed in upper portions of the lower substrate semiconductor layer9, for example, by introducing electrical dopants employing the at least one gate structure (750,752,754,758) as masking structures. Additional masks may be employed as needed. The active region730can include source regions and drain regions of field effect transistors. A first dielectric liner761and a second dielectric liner762can be optionally formed. Each of the first and second dielectric liners (761,762) can comprise a silicon oxide layer, a silicon nitride layer, and/or a dielectric metal oxide layer. As used herein, silicon oxide includes silicon dioxide as well as non-stoichiometric silicon oxides having more or less than two oxygen atoms for each silicon atoms. Silicon dioxide is preferred. In an illustrative example, the first dielectric liner761can be a silicon oxide layer, and the second dielectric liner762can be a silicon nitride layer. The least one semiconductor device for the peripheral circuitry can contain a driver circuit for memory devices to be subsequently formed, which can include at least one NAND device.

A dielectric material such as silicon oxide can be deposited over the at least one semiconductor device, and can be subsequently planarized to form a planarization dielectric layer770. In one embodiment the planarized top surface of the planarization dielectric layer770can be coplanar with a top surface of the dielectric liners (761,762). Subsequently, the planarization dielectric layer770and the dielectric liners (761,762) can be removed from an area to physically expose a top surface of the lower substrate semiconductor layer9. As used herein, a surface is “physically exposed” if the surface is in physical contact with vacuum, or a gas phase material (such as air).

The optional upper substrate semiconductor layer10, if present, can be formed on the top surface of the lower substrate semiconductor layer9prior to, or after, formation of the at least one semiconductor device700by deposition of a single crystalline semiconductor material, for example, by selective epitaxy. The deposited semiconductor material can be the same as, or can be different from, the semiconductor material of the lower substrate semiconductor layer9. The deposited semiconductor material can be any material that can be employed for the lower substrate semiconductor layer9as described above. The single crystalline semiconductor material of the upper substrate semiconductor layer10can be in epitaxial alignment with the single crystalline structure of the lower substrate semiconductor layer9. Portions of the deposited semiconductor material located above the top surface of the planarization dielectric layer770can be removed, for example, by chemical mechanical planarization (CMP). In this case, the upper substrate semiconductor layer10can have a top surface that is coplanar with the top surface of the planarization dielectric layer770.

The region (i.e., area) of the at least one semiconductor device700is herein referred to as a peripheral device region200. The region in which a memory array is subsequently formed is herein referred to as a memory array region100. A staircase region300for subsequently forming stepped terraces of electrically conductive layers can be provided between the memory array region100and the peripheral device region200.

In one alternative embodiment, the peripheral device region200may be located under the memory array region100in a CMOS under array configuration. In another alternative embodiment, the peripheral device region200may be located on a separate substrate which is subsequently bonded to the memory array region100.

Referring toFIG.2, a stack of an alternating plurality of insulating layers32and spacer material layers (which can be sacrificial material layers42) is formed over the top surface of the substrate (9,10). As used herein, a “material layer” refers to a layer including a material throughout the entirety thereof. As used herein, an alternating plurality of first elements and second elements refers to a structure in which instances of the first elements and instances of the second elements alternate. Each instance of the first elements that is not an end element of the alternating plurality is adjoined by two instances of the second elements on both sides, and each instance of the second elements that is not an end element of the alternating plurality is adjoined by two instances of the first elements on both ends. The first elements may have the same thickness thereamongst, or may have different thicknesses. The second elements may have the same thickness thereamongst, or may have different thicknesses. The alternating plurality of insulating layers32and spacer material layers may begin with a bottommost insulating layer32or with a bottommost spacer material layer, and may end with a topmost insulating layer32or with a topmost spacer material layer. In one embodiment, an instance of the first elements and an instance of the second elements may form a unit that is repeated with periodicity within the alternating plurality.

Generally, the spacer material layers may be formed as, or may be subsequently replaced with, electrically conductive layers. In case the spacer material layers are subsequently replaced with the electrically conductive layers, the spacer material layers are formed as sacrificial material layers42. Alternatively, if the spacer material layers are formed as electrically conductive layers, replacement of the spacer material layers with other material layers is unnecessary. While the present disclosure is described employing an embodiment in which the spacer material layers are formed as sacrificial material layers42that are subsequently replaced with electrically conductive layers, embodiments are expressly contemplated herein in which the sacrificial material layers are formed as electrically conductive layers. In such cases, processing steps for replacing the sacrificial material layers42with electrically conductive layers are omitted.

The stack of the alternating plurality of the insulating layers32and the spacer material layers (such as the sacrificial material layers42) is herein referred to as an alternating stack (32,42). Insulating materials that can be employed for the insulating layers32include, but are not limited to, silicon oxide (including doped or undoped silicate glass), silicon nitride, silicon oxynitride, organosilicate glass (OSG), spin-on dielectric materials, dielectric metal oxides that are commonly known as high dielectric constant (high-k) dielectric oxides (e.g., aluminum oxide, hafnium oxide, etc.) and silicates thereof, dielectric metal oxynitrides and silicates thereof, and organic insulating materials. In one embodiment, the insulating material of the insulating layers32can be silicon oxide.

In one embodiment, the insulating layers32can include silicon oxide, and sacrificial material layers can include silicon nitride sacrificial material layers. The insulating material of the insulating layers32can be deposited, for example, by plasma enhanced chemical vapor deposition (PECVD). For example, if silicon oxide is employed for the insulating layers32, tetraethyl orthosilicate (TEOS) can be employed as the precursor material for the PECVD process. The spacer material of the sacrificial material layers42can be formed, for example, by thermal CVD or atomic layer deposition (ALD).

The sacrificial material layers42can be suitably patterned so that conductive material portions to be subsequently formed by replacement of the sacrificial material layers42can function as electrically conductive electrodes, such as the control gate electrodes of the monolithic three-dimensional NAND string memory devices to be subsequently formed. The sacrificial material layers42may comprise a portion having a strip shape extending substantially parallel to the major surface7of the substrate.

The thicknesses of the insulating layers32and the sacrificial material layers42can be in a range from 20 nm to 50 nm, although lesser and greater thicknesses can be employed for each insulating layer32and for each sacrificial material layer42. The number of repetitions of the pairs of an insulating layer32and a sacrificial material layer (e.g., a control gate electrode or a sacrificial material layer)42can be in a range from 2 to 1,024, and typically from 8 to 256, although a greater number of repetitions can also be employed. The top and bottom gate electrodes in the stack may function as the select gate electrodes. In one embodiment, each sacrificial material layer42in the alternating stack (32,42) can have a uniform thickness that is substantially invariant within each respective sacrificial material layer42. Optionally, an insulating cap layer70can be formed over the alternating stack (32,42). The insulating cap layer70includes a dielectric material that is different from the material of the sacrificial material layers42. In one embodiment, the insulating cap layer70can include a dielectric material that can be employed for the insulating layers32as described above. The insulating cap layer70can have a greater thickness than each of the insulating layers32. The insulating cap layer70can be deposited, for example, by chemical vapor deposition. In one embodiment, the insulating cap layer70can be a silicon oxide layer.

Each sacrificial material layer42other than a topmost sacrificial material layer42within the alternating stack (32,42) laterally extends farther than any overlying sacrificial material layer42within the alternating stack (32,42) in the terrace region. The terrace region includes stepped surfaces of the alternating stack (32,42) that continuously extend from a bottommost layer within the alternating stack (32,42) to a topmost layer within the alternating stack (32,42).

Each vertical step of the stepped surfaces can have the height of one or more pairs of an insulating layer32and a sacrificial material layer. In one embodiment, each vertical step can have the height of a single pair of an insulating layer32and a sacrificial material layer42. In another embodiment, multiple “columns” of staircases can be formed along a first horizontal direction hd1such that each vertical step has the height of a plurality of pairs of an insulating layer32and a sacrificial material layer42, and the number of columns can be at least the number of the plurality of pairs. Each column of staircase can be vertically offset among one another such that each of the sacrificial material layers42has a physically exposed top surface in a respective column of staircases. In the illustrative example, two columns of staircases are formed for each block of memory stack structures to be subsequently formed such that one column of staircases provide physically exposed top surfaces for odd-numbered sacrificial material layers42(as counted from the bottom) and another column of staircases provide physically exposed top surfaces for even-numbered sacrificial material layers (as counted from the bottom). Configurations employing three, four, or more columns of staircases with a respective set of vertical offsets among the physically exposed surfaces of the sacrificial material layers42may also be employed. Each sacrificial material layer42has a greater lateral extent, at least along one direction, than any overlying sacrificial material layers42such that each physically exposed surface of any sacrificial material layer42does not have an overhang. In one embodiment, the vertical steps within each column of staircases may be arranged along the first horizontal direction hd1, and the columns of staircases may be arranged along a second horizontal direction hd2that is perpendicular to the first horizontal direction hd1. In one embodiment, the first horizontal direction hd1may be perpendicular to the boundary between the memory array region100and the staircase region300.

Optionally, drain select level isolation structures72(FIG.4A) can be formed through the insulating cap layer70and a subset of the sacrificial material layers42located at drain select levels. The drain select level isolation structures72can be formed, for example, by forming drain select level isolation trenches and filling the drain select level isolation trenches with a dielectric material such as silicon oxide. Excess portions of the dielectric material can be removed from above the top surface of the insulating cap layer70.

Referring toFIGS.4A and4B, a lithographic material stack (not shown) including at least a photoresist layer can be formed over the insulating cap layer70and the retro-stepped dielectric material portion65, and can be lithographically patterned to form openings therein. The openings include a first set of openings formed over the memory array region100and a second set of openings formed over the staircase region300. The pattern in the lithographic material stack can be transferred through the insulating cap layer70or the retro-stepped dielectric material portion65, and through the alternating stack (32,42) by at least one anisotropic etch that employs the patterned lithographic material stack as an etch mask. Portions of the alternating stack (32,42) underlying the openings in the patterned lithographic material stack are etched to form memory openings49and support openings19. As used herein, a “memory opening” refers to a structure in which memory elements, such as a memory stack structure, is subsequently formed. As used herein, a “support opening” refers to a structure in which a support structure (such as a support pillar structure) that mechanically supports other elements is subsequently formed. The memory openings49are formed through the insulating cap layer70and the entirety of the alternating stack (32,42) in the memory array region100. The support openings19are formed through the retro-stepped dielectric material portion65and the portion of the alternating stack (32,42) that underlie the stepped surfaces in the staircase region300.

The memory openings49extend through the entirety of the alternating stack (32,42). The support openings19extend through a subset of layers within the alternating stack (32,42). The chemistry of the anisotropic etch process employed to etch through the materials of the alternating stack (32,42) can alternate to optimize etching of the materials in the alternating stack (32,42). The anisotropic etch can be, for example, a series of reactive ion etches. The sidewalls of the memory openings49and the support openings19can be substantially vertical, or can be tapered. The patterned lithographic material stack can be subsequently removed, for example, by ashing.

The memory openings49and the support openings19can extend from the top surface of the alternating stack (32,42) to at least the horizontal plane including the topmost surface of the upper substrate semiconductor layer10. In one embodiment, an overetch into the upper substrate semiconductor layer10may be optionally performed after the top surface of the upper substrate semiconductor layer10is physically exposed at a bottom of each memory opening49and each support opening19. The overetch may be performed prior to, or after, removal of the lithographic material stack. In other words, the recessed surfaces of the upper substrate semiconductor layer10may be vertically offset from the un-recessed top surfaces of the upper substrate semiconductor layer10by a recess depth. The recess depth can be, for example, in a range from 1 nm to 50 nm, although lesser and greater recess depths can also be employed. The overetch is optional, and may be omitted. If the overetch is not performed, the bottom surfaces of the memory openings49and the support openings19can be coplanar with the topmost surface of the upper substrate semiconductor layer10.

Each of the memory openings49and the support openings19may include a sidewall (or a plurality of sidewalls) that extends substantially perpendicular to the topmost surface of the substrate. A two-dimensional array of memory openings49can be formed in the memory array region100. A two-dimensional array of support openings19can be formed in the staircase region300. The lower substrate semiconductor layer9and the upper substrate semiconductor layer10collectively constitutes a substrate (9,10), which can be a semiconductor substrate. Alternatively, the upper substrate semiconductor layer10may be omitted, and the memory openings49and the support openings19can be extend to a top surface of the lower substrate semiconductor layer9.

FIGS.5A-5Pillustrate structural changes in a memory opening49during formation of a first exemplary memory opening fill structure. The same structural change occurs simultaneously in each of the other memory openings49and in each of the support openings19.

Referring toFIG.5A, a memory opening49in the exemplary device structure ofFIGS.4A and4Bis illustrated. The memory opening49extends through the insulating cap layer70, the alternating stack (32,42), and optionally into an upper portion of the upper substrate semiconductor layer10. At this processing step, each support opening19can extend through the retro-stepped dielectric material portion65, a subset of layers in the alternating stack (32,42), and optionally through the upper portion of the upper substrate semiconductor layer10. The recess depth of the bottom surface of each memory opening with respect to the top surface of the upper substrate semiconductor layer10can be in a range from 0 nm to 30 nm, although greater recess depths can also be employed. Optionally, the sacrificial material layers42can be laterally recessed partially to form lateral recesses (not shown), for example, by an isotropic etch.

Referring toFIG.5B, an optional pedestal channel portion (e.g., an epitaxial pedestal)11can be formed at the bottom portion of each memory opening49and each support openings19, for example, by selective epitaxy. Each pedestal channel portion11comprises a single crystalline semiconductor material in epitaxial alignment with the single crystalline semiconductor material of the upper substrate semiconductor layer10. In one embodiment, the top surface of each pedestal channel portion11can be formed above a horizontal plane including the top surface of a bottommost sacrificial material layer42. In this case, a source select gate electrode can be subsequently formed by replacing the bottommost sacrificial material layer42with a conductive material layer. The pedestal channel portion11can be a portion of a transistor channel that extends between a source region to be subsequently formed in the substrate (9,10) and a drain region to be subsequently formed in an upper portion of the memory opening49. A memory cavity49′ (FIG.5D) is present in the unfilled portion of the memory opening49above the pedestal channel portion11. In one embodiment, the pedestal channel portion11can comprise single crystalline silicon. In one embodiment, the pedestal channel portion11can have a doping of the first conductivity type, which is the same as the conductivity type of the upper substrate semiconductor layer10that the pedestal channel portion contacts. If an upper substrate semiconductor layer10is not present, the pedestal channel portion11can be formed directly on the lower substrate semiconductor layer9, which can have a doping of the first conductivity type.

Referring toFIG.5C, annular lateral recesses149can be formed at levels of the insulating layers32that are not masked by the pedestal channel portion11. An additional annular lateral recess can be formed at the level of the insulating cap layer70around the memory opening49. The annular lateral recesses149can be formed by laterally recessing sidewalls of the insulating layers32relative to sidewalls of the spacer material layers (such as the sacrificial material layers42) around the memory opening49. An isotropic etch process that etches the material of the insulating layers32selective to the material of the spacer material layers can be performed to laterally recess the physically exposed sidewalls of the insulating layers32relative to sidewalls of the spacer material layers (such as the sacrificial material layers). In one embodiment, the physically exposed surfaces of the insulating cap layer70may be isotropically recessed concurrently with formation of the annular lateral recesses149. In an illustrative example, the insulating layers32include silicon oxide, the spacer material layers42include silicon nitride or a semiconductor material (such as polysilicon), and the isotropic etch process comprises a wet etch process employing dilute hydrofluoric acid.

The duration of the isotropic etch process can be selected such that the lateral recess distance of the annular lateral recesses149can be in a range from 5 nm to 100 nm, such as from 10 nm to 50 nm, although lesser and greater lateral recess distances can also be employed. The lateral recess distance refers to the lateral distance between a recessed sidewall of an insulating layer32relative to a sidewall of an immediately overlying spacer material layer (such as an immediately overlying sacrificial material layer42) or relative to a sidewall of an immediately underlying spacer material layer. Each annular lateral recess149can have a volume of an annular cylinder, and is a portion of the memory opening49. Thus, the memory opening49includes a vertical stack of annular lateral recesses149provided at levels of the insulating layers32.

Referring toFIG.5D, a blocking dielectric layer52can be conformally deposited on physically exposed surfaces of the insulating layers32and the spacer material layers (such as the sacrificial material layers42). The blocking dielectric layer52can be deposited on the sidewalls of the insulating layers32, annular horizontal surfaces of the insulating layers32overlying or underlying a respective one of the annular lateral recesses149, sidewalls of the sacrificial material layers42, a bottom surface of the memory opening49(which may be a top surface of a pedestal channel portion11or a top surface of the upper substrate semiconductor layer10if a pedestal channel portion is not employed), and physically exposed surfaces of the insulating cap layer70.

The blocking dielectric layer52can include a single dielectric material layer or a stack of a plurality of dielectric material layers. In one embodiment, the blocking dielectric layer can include a dielectric metal oxide layer consisting essentially of a dielectric metal oxide. As used herein, a dielectric metal oxide refers to a dielectric material that includes at least one metallic element and at least oxygen. The dielectric metal oxide may consist essentially of the at least one metallic element and oxygen, or may consist essentially of the at least one metallic element, oxygen, and at least one non-metallic element such as nitrogen. In one embodiment, the blocking dielectric layer52can include a dielectric metal oxide having a dielectric constant greater than 7.9, i.e., having a dielectric constant greater than the dielectric constant of silicon nitride.

Non-limiting examples of dielectric metal oxides include aluminum oxide (Al2O3), hafnium oxide (HfO2), lanthanum oxide (LaO2), yttrium oxide (Y2O3), tantalum oxide (Ta2O5), silicates thereof, nitrogen-doped compounds thereof, alloys thereof, and stacks thereof. The dielectric metal oxide layer can be deposited, for example, by chemical vapor deposition (CVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), liquid source misted chemical deposition, or a combination thereof. The thickness of the dielectric metal oxide layer can be in a range from 1 nm to 20 nm, although lesser and greater thicknesses can also be employed. The dielectric metal oxide layer can subsequently function as a dielectric material portion that blocks leakage of stored electrical charges to control gate electrodes. In one embodiment, the blocking dielectric layer52includes aluminum oxide. In one embodiment, the blocking dielectric layer52can include multiple dielectric metal oxide layers having different material compositions.

Alternatively or additionally, the blocking dielectric layer52can include a dielectric semiconductor compound such as silicon oxide, silicon oxynitride, silicon nitride, or a combination thereof. In one embodiment, the blocking dielectric layer52can include silicon oxide. In this case, the dielectric semiconductor compound of the blocking dielectric layer52can be formed by a conformal deposition method such as low pressure chemical vapor deposition, atomic layer deposition, or a combination thereof. The thickness of the dielectric semiconductor compound can be in a range from 1 nm to 20 nm, although lesser and greater thicknesses can also be employed.

The blocking dielectric layer52has a laterally-undulating vertical cross-sectional profile, and comprises laterally-protruding portions that laterally extend into the annular lateral recesses149. The laterally-protruding portions of the blocking dielectric layer52can be located at the levels of the insulating layers32. Outer sidewalls of the laterally-protruding portions of the blocking dielectric layer52contact sidewalls of the insulating layers32, and annular horizontal surfaces of the laterally-protruding portions of the blocking dielectric layer52contact annular horizontal surfaces of the spacer material layers (such as the sacrificial material layers42).

Referring toFIG.5E, a metal layer66L can be conformally deposited on the inner sidewalls of the blocking dielectric layer. The metal layer66L can include any metal that can form a metal-semiconductor alloy such as a metal silicide. In one embodiment, the metal layer66L can include at least one transition metal that can form a metal silicide. For example, the metal layer66L can include tungsten, titanium, cobalt, molybdenum, platinum, nickel, and/or any other transition metal that forms a metal silicide upon reaction with silicon. The metal layer66L can be deposited by a conformal deposition method such as a chemical vapor deposition process or an atomic layer deposition process. The thickness of the metal layer66L can be in a range from 2 nm to 20 nm, such as from 4 nm to 10 nm, although lesser and greater thicknesses can also be employed. The thickness of the metal layer66L may be less than, equal to, or greater than one half of the thickness of each insulating layer32. Thus, the annular lateral recesses149may, or may not, have unfilled volumes after formation of the metal layer66L.

Referring toFIG.5F, an optional patterning film47can be anisotropically deposited to cover the insulating cap layer70and the topmost laterally-protruding portion of the metal layer66L that overlies the topmost spacer material layer (such as the topmost sacrificial material layer42). The patterning film47is deposited with high directionality, and thus, has a significantly greater thickness above the insulating cap layer70than at the bottom horizontal surface of the memory opening49(which may be the top surface of the pedestal channel portion11). The patterning film47may be a film including amorphous carbon as a predominant component. For example, Advanced Patterning Film™ by Applied Materials Inc.™ may be employed for the patterning film47. Alternatively, the patterning film47can be omitted.

Portions of the metal layer located66L outside the annular lateral recesses149can be anisotropically etched by performing an anisotropic etch process. The anisotropic etch process can employ an etch chemistry that etches the material of the metal layer66L selective to the patterning film47(if present), selective to the material of the spacer material layers42, and selective to the material of the blocking dielectric layer52and/or to the material of the pedestal channel portion11. The anisotropic etch process can employ a reactive ion etch process. Remaining portions of the metal layer66L comprise the vertical stack of discrete metal portions66. The discrete metal portions66can be formed within a respective one of the annular lateral recesses149of the memory opening49. Thus, the vertical stack of discrete metal portions66can be formed in the annular lateral recesses149. The vertical stack of discrete metal portions66is formed directly on portions of an inner sidewall of the blocking dielectric layer52located at levels of the insulating layers32.

The discrete metal portions66may have a C-shaped (e.g., clam shaped) vertical cross-sectional profile having vertical portion connecting two horizontal portions if the thickness of the metal layer66L is less than one half of the thickness of each insulating layer32, or may have a rectangular vertical cross-sectional profile if the thickness of the metal layer66L is greater than one half of the thickness of each insulating layer32. In one embodiment, the discrete metal portion66can comprise, and/or can consist essentially of, tungsten, titanium, cobalt, molybdenum, platinum, nickel, and/or any other transition metal that forms a metal silicide upon reaction with silicon.

Referring toFIG.5G, the patterning film47(if present) can be subsequently removed, for example, by ashing. If the patterning film47is omitted, then the discrete metal portion66at the level of the insulating cap layer70is also not present because it would be removed during the anisotropic etch process shown inFIG.5F.

Referring toFIG.5H, a semiconductor material layer54L can be conformally deposited on the physically exposed surfaces of the vertical stack of the metal portions66and on the physically exposed surfaces of the blocking dielectric layer52. The semiconductor material layer54L includes a semiconductor material that can form a metal-semiconductor alloy with the material of the metal portions66. For example, the semiconductor material layer54L can include silicon and/or germanium. In one embodiment, the semiconductor material layer54L can include amorphous silicon, polysilicon, germanium, and/or a silicon-germanium alloy. The thickness of the semiconductor material layer54L can be selected such that the entirety of the vertical stack of discrete metal portions66can react with the semiconductor material of the semiconductor material layer54L during a subsequent anneal process. In one embodiment, the semiconductor material layer54L can have a thickness in a range from 2 nm to 20 nm, such as from 4 nm to 10 nm, although lesser and greater thicknesses can also be employed.

Referring toFIG.5J, an anisotropic etch process can be performed to remove horizontal portions of the semiconductor material layer54L and the metal layer66L (if present) that overlie the insulating cap layer70, and to remove a horizontal portion of the semiconductor material layer54L located at the bottom of the memory opening49(such as the horizontal portion of the semiconductor material layer54L located above the pedestal channel portion11).

Referring toFIG.5J, a thermal anneal process is performed at an elevated temperature that induces formation of a metal-semiconductor alloy between the material of the metal portions66and the material of the semiconductor material layer54L. The elevated temperature may be in a range from 400 degrees Celsius to 1,000 degrees Celsius, although lower and higher temperatures may also be employed depending on the composition of the metal-semiconductor alloy. It is not necessary to form a low-resistance phase metal-semiconductor alloy as required for typical semiconductor applications in this case. Even high-resistance intermediate phase metal-semiconductor alloys formed at a relatively low temperature are sufficient provided that such metal-semiconductor alloys can be subsequently removed selective to unreacted portions of the semiconductor material layer54L in a selective etch process. Generally, the thickness of the metal layer66L and the thickness of the semiconductor material layer54L can be selected to ensure that the entire volume of the metal portions66react with the semiconductor material layer54L to form metal-semiconductor alloy portions67. A vertical stack of metal-semiconductor alloy portions67can be formed by reacting the vertical stack of metal portions66with portions of the semiconductor material layer54L located at levels of the insulating layers32. Unreacted portions of the semiconductor material layer54L remain at each level of the sacrificial material layers42located over the top surface of the pedestal channel portion11. The set of unreacted portions of the semiconductor material layer54L in the memory opening49comprise a vertical stack of semiconductor material portions54S.

Referring toFIG.5K, a selective isotropic etch process that etches the material of the metal-semiconductor alloy portions67selective to the material of the semiconductor material portions54S can be performed. The vertical stack of metal-semiconductor alloy portions67is removed selective to unreacted portions of the semiconductor material layer54L, i.e., the vertical stack of semiconductor material portions54S. The vertical stack of semiconductor material portions54S remain at levels of the spacer material layers (such as the sacrificial material layers42). In one embodiment, each semiconductor portion54S can have a have a tubular shape. As used herein, a “tubular” element refers to an element having an inner cylindrical sidewall, an outer cylindrical sidewall, and a substantially uniform thickness between the inner sidewall and the outer sidewall. The vertical stack of semiconductor material portions54S can be subsequently employed as a vertical stack of charge storage elements, which can function as floating gates of a NAND string. Portions of the inner sidewall of the blocking dielectric layer52are physically exposed after removal of the vertical stack of metal-semiconductor alloy portions67.

Referring toFIG.5L, a tunneling dielectric layer56can be deposited employing a conformal deposition process such as a chemical vapor deposition process. The tunneling dielectric layer56includes a dielectric material through which charge tunneling can be performed under suitable electrical bias conditions. The tunneling dielectric layer56can be formed directly on the portions of the inner sidewall of the blocking dielectric layer52that are physically exposed and located at the levels of the insulating layers32. The tunneling dielectric layer56can be formed directly on the vertical stack of discrete cylindrical semiconductor material portions54S. The charge tunneling may be performed through hot-carrier injection or by Fowler-Nordheim tunneling induced charge transfer depending on the mode of operation of the monolithic three-dimensional NAND string memory device to be formed. The tunneling dielectric layer56can include silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxides (such as aluminum oxide and hafnium oxide), dielectric metal oxynitride, dielectric metal silicates, alloys thereof, and/or combinations thereof. In one embodiment, the tunneling dielectric layer56can include a stack of a first silicon oxide layer, a silicon oxynitride layer, and a second silicon oxide layer, which is commonly known as an ONO stack. In one embodiment, the tunneling dielectric layer56can include a silicon oxide layer that is substantially free of carbon or a silicon oxynitride layer that is substantially free of carbon. The thickness of the tunneling dielectric layer56can be in a range from 2 nm to 20 nm, although lesser and greater thicknesses can also be employed.

An optional first semiconductor channel layer601can be subsequently deposited on the tunneling dielectric layer56by a conformal deposition process. The first semiconductor channel layer601includes a semiconductor material such as at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the first semiconductor channel layer601includes amorphous silicon or polysilicon. The first semiconductor channel layer601can be formed by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD). The thickness of the first semiconductor channel layer601can be in a range from 2 nm to 10 nm, although lesser and greater thicknesses can also be employed.

Referring toFIG.5M, an optional patterning film77can be anisotropically deposited to cover the insulating cap layer70and the topmost portion of the first semiconductor channel layer601that overlies the topmost spacer material layer (such as the topmost sacrificial material layer42). The patterning film77is deposited with high directionality, and thus, has a significantly greater thickness above the insulating cap layer70than at the bottom horizontal surface of the memory opening49(which may be the top surface of the pedestal channel portion11). The patterning film77may be a film including amorphous carbon as a predominant component. For example, Advanced Patterning Film™ by Applied Materials Inc.™ may be employed for the patterning film77. Alternatively, the patterning film77may be omitted.

An anisotropic etch process can be performed to remove the horizontal bottom portions of the first semiconductor channel layer601, the tunneling dielectric layer56, and the blocking dielectric layer52located over the pedestal channel portion11(or located above the upper substrate semiconductor layer10in case a pedestal channel portion is not present) at the bottom of each memory opening49. A center portion of the top surface of the pedestal channel portion11can be vertically recessed by the anisotropic etch process. In case a pedestal channel portion11is not present in the memory opening49, a portion of the horizontal surface of the upper substrate semiconductor layer10can be vertically recessed underneath the memory opening49. If present, the patterning film77can be subsequently removed, for example, by ashing.

A surface of the pedestal channel portion11(or a surface of the upper substrate semiconductor layer10in case the pedestal channel portions11are not employed) can be physically exposed underneath the opening through the first semiconductor channel layer601, the tunneling dielectric layer56, and the blocking dielectric layer52. Optionally, the physically exposed semiconductor surface at the bottom of each memory cavity49′ can be vertically recessed so that the recessed semiconductor surface underneath the memory cavity49′ is vertically offset from the topmost surface of the pedestal channel portion11(or of the upper substrate semiconductor layer10in case pedestal channel portions11are not employed) by a recess distance. The vertical stack of semiconductor material portions54S function as discrete charge storage elements that are floating gates. A set of the blocking dielectric layer52, the vertical stack of semiconductor material portions54S, and the tunneling dielectric layer56in a memory opening49constitutes a memory film50. In one embodiment, the first semiconductor channel layer601, the tunneling dielectric layer56, and the blocking dielectric layer52can have vertically coincident sidewalls.

Referring toFIG.5N, a second semiconductor channel layer602can be deposited directly on the semiconductor surface of the pedestal channel portion11or the upper substrate semiconductor layer10if the pedestal channel portion11is omitted, and directly on the first semiconductor channel layer601(if present). The second semiconductor channel layer602includes a semiconductor material such as at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the second semiconductor channel layer602includes amorphous silicon or polysilicon. The second semiconductor channel layer602can be formed by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD). The thickness of the second semiconductor channel layer602can be in a range from 2 nm to 10 nm, although lesser and greater thicknesses can also be employed. The second semiconductor channel layer602may partially fill the memory cavity49′ in each memory opening, or may fully fill the cavity in each memory opening.

The materials of the first semiconductor channel layer601and the second semiconductor channel layer602are collectively referred to as a semiconductor channel material. In other words, the semiconductor channel material is a set of all semiconductor material in the first semiconductor channel layer601and the second semiconductor channel layer602. The combination of the blocking dielectric layer52, the tunneling dielectric layer56, the first semiconductor channel layer601, and the second semiconductor channel layer602can completely fill the volumes of the annular lateral recesses provided at the levels of the insulating layers32.

Referring toFIG.5O, in case the memory cavity49′ in each memory opening is not completely filled by the second semiconductor channel layer602, a dielectric core layer can be deposited in the memory cavity49′ to fill any remaining portion of the memory cavity49′ within each memory opening. The dielectric core layer includes a dielectric material such as silicon oxide or organosilicate glass. The dielectric core layer can be deposited by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD), or by a self-planarizing deposition process such as spin coating. The horizontal portion of the dielectric core layer can be removed, for example, by a recess etch from above the top surface of the second semiconductor channel layer602. Further, the material of the dielectric core layer can be vertically recessed selective to the semiconductor material of the second semiconductor channel layer602into each memory opening49down to a depth between a first horizontal plane including the top surface of the insulating cap layer70and a second horizontal plane including the bottom surface of the insulating cap layer70. Each remaining portion of the dielectric core layer constitutes a dielectric core62.

Referring toFIG.5P, a doped semiconductor material having a doping of a second conductivity type can be deposited within each recessed region above the dielectric cores62. The second conductivity type is the opposite of the first conductivity type. For example, if the first conductivity type is p-type, the second conductivity type is n-type, and vice versa. The dopant concentration of the doped semiconductor material can be in a range from 5.0×1018/cm3to 2.0×1021/cm3, although lesser and greater dopant concentrations can also be employed. The doped semiconductor material can be, for example, doped polysilicon.

Excess portions of the deposited semiconductor material can be removed from above the top surface of the insulating cap layer70, for example, by chemical mechanical planarization (CMP) or a recess etch. Each remaining portion of the semiconductor material having a doping of the second conductively type comprises a doped semiconductor region having a p-n junction at an interface with the vertical semiconductor channel60. In one embodiment, the doped semiconductor region is employed as a drain region63for a vertical NAND string. The horizontal portion of the second semiconductor channel layer602located above the top surface of the insulating cap layer70can be concurrently removed by a planarization process. Each remaining portion of the second semiconductor channel layer602can be located entirety within a memory opening49or entirely within a support opening19.

Each remaining portion of the doped semiconductor material having a doping of the second conductivity type constitutes a drain region63. Each adjoining pair of the optional first semiconductor channel layer601and the second semiconductor channel layer602can collectively form a vertical semiconductor channel60through which electrical current can flow when a vertical NAND device including the vertical semiconductor channel60is turned on. A tunneling dielectric layer56is surrounded by a vertical stack of semiconductor material portions54S, and laterally surrounds a portion of the vertical semiconductor channel60. Each adjoining set of a tunneling dielectric layer56, a vertical stack of semiconductor material portions54S, and a blocking dielectric layer52collectively constitute a memory film50, which includes a vertical stack of memory elements that can store a respective data bit with a macroscopic retention time. As used herein, a macroscopic retention time refers to a retention time suitable for operation of a memory device as a permanent memory device such as a retention time in excess of 24 hours.

Each combination of a memory film50and a vertical semiconductor channel60within a memory opening49constitutes a memory stack structure55. The memory stack structure55is a combination of a semiconductor channel60, a tunneling dielectric layer56, a plurality of memory elements comprising a vertical stack of discrete (i.e., vertically separated from each other) semiconductor material portions54S, and a blocking dielectric layer52. Each combination of a pedestal channel portion11(if present), a memory stack structure55, a dielectric core62, and a drain region63within a memory opening49is herein referred to as a memory opening fill structure58. Each combination of a pedestal channel portion11(if present), a memory film50, a vertical semiconductor channel60, a dielectric core62, and a drain region63within each support opening19fills the respective support openings19, and constitutes a support pillar structure.

FIGS.5Q and5Rillustrate an alternative configuration of the first exemplary memory opening fill structure. Referring toFIG.5Q, the alternative configuration of the first exemplary memory opening fill structure can be derived from the structure illustrated inFIG.5Kby filling the annular lateral recesses149with a dielectric fill material. Specifically, a dielectric fill material such as undoped silicate glass or a doped silicate glass can be deposited in the remaining volumes of the annular lateral recesses149after removal of the vertical stack of metal-semiconductor alloy portions67. In one embodiment, the dielectric fill material may have a higher etch rate than the material of the blocking dielectric layer52. For example, the dielectric fill material may include borosilicate glass, which can provide an etch rate in dilute hydrofluoric acid than the etch rate of undoped silicate glass by a factor in a range from 100 to 10,000.

Portions of the dielectric fill material can be removed from outside the annular lateral recesses149by etching back the dielectric fill material. An isotropic etch process or an anisotropic etch process may be employed. The chemistry of the etch process employed to etch the dielectric fill material can be selective to the material of the semiconductor material portions54S and the material of the blocking dielectric layer52. Remaining portions of the dielectric fill material filling the annular lateral recesses149comprise a vertical stack of annular insulating material portions57. In case an anisotropic etch process is employed to pattern the annular insulating material portions57, inner sidewalls of the annular insulating material portions57may be vertically coincident with inner sidewalls of the semiconductor material portions54S.

Referring toFIG.5R, the processing steps ofFIGS.5L-5Pcan be performed to provide an alternative configuration of the second exemplary memory opening fill structure58. In this case, the tunneling dielectric layer56can be formed directly on the vertical stack of annular insulating material portions57. The memory film50can comprise the blocking dielectric layer52, the vertical stack of semiconductor material portions54S, the vertical stack of annular insulating material portions57(which can contact the vertical stack of semiconductor material portions54S), and the tunneling dielectric layer56.

FIGS.6A-6Jare sequential schematic vertical cross-sectional views of a memory opening within the first exemplary structure during formation of a second exemplary memory opening fill structure according to an embodiment of the present disclosure. The second exemplary memory opening fill structure can be formed within each memory opening49in lieu of the first exemplary memory opening fill structure.

Referring toFIG.6A, a memory opening49is illustrated during formation of the second exemplary memory opening fill structures in which the metal layer self-segregates into the annular lateral recesses149during an anneal. Specifically, the structure illustrated inFIG.6Acan be derived from the structure illustrated inFIG.5Dby conformally depositing a metal layer166L on the inner sidewalls of the blocking dielectric layer52. The metal layer166L can include any metal that can spontaneously segregate into the annular lateral recesses149in a subsequent anneal process. For example, the metal layer166L can include, and/or consist essentially of, cobalt.

Referring toFIG.6B, a thermal anneal process is performed at an elevated temperature to induce thermal migration of the metal layer166L into the annular lateral recesses149. The metal layer166L self-segregates into the vertical stack of discrete metal portions166during the thermal anneal process in order to reduce the total surface area. The elevated temperature of the thermal anneal process can be in a range from 300 degrees Celsius to 1,000 degrees Celsius, although lower and higher temperatures may also be employed depending on the composition of the metal layer166L. The thickness of the metal layer166L as deposited at the processing steps ofFIG.6Acan be selected such that the discrete metal portions166are confined within a respective one of the annular lateral recesses149, and are not in direct contact with each other (i.e., vertically separated from each other). Inner sidewalls of the blocking dielectric layer52can be physically exposed at each level of the spacer material layers (such as the sacrificial material layers42).

Referring toFIG.6C, the processing steps ofFIG.5Hcan be performed to form a semiconductor material layer54L. The semiconductor material layer54L can be conformally deposited over the physically exposed surfaces of the blocking dielectric layer52and the discrete metal portions166, each of which may have an annular configuration.

Referring toFIG.6D, a thermal anneal process is performed at an elevated temperature that induces formation of a metal-semiconductor alloy between the material of the metal portions166and the material of the semiconductor material layer54L. The elevated temperature may be in a range from 400 degrees Celsius to 1,000 degrees Celsius, although lower and higher temperatures may also be employed depending on the composition of the metal-semiconductor alloy. Generally, the thickness of the metal layer166L and the thickness of the semiconductor material layer54L can be selected to ensure that the entire volume of the metal portions166react with the semiconductor material layer54L to form metal-semiconductor alloy portions167. A vertical stack of metal-semiconductor alloy portions167can be formed by reacting the vertical stack of metal portions166with portions of the semiconductor material layer54L located at levels of the insulating layers32. Unreacted portions of the semiconductor material layer54L remain at each level of the sacrificial material layers42located over the top surface of the pedestal channel portion11. The set of unreacted portions of the semiconductor material layer54L in the memory opening49comprise a vertical stack of semiconductor material portions54S.

Referring toFIG.6E, a selective isotropic etch process that etches the material of the metal-semiconductor alloy portions167selective to the material of the semiconductor material portions54S can be performed. The vertical stack of metal-semiconductor alloy portions167is removed selective to unreacted portions of the semiconductor material layer54L, i.e., the vertical stack of semiconductor material portions54S. The vertical stack of semiconductor material portions54S remain at levels of the spacer material layers (such as the sacrificial material layers42). In one embodiment, each semiconductor portion54S can have a have a tubular shape. The vertical stack of semiconductor material portions54S can be subsequently employed as a vertical stack of charge storage elements, which can function as floating gates of a NAND string. Portions of the inner sidewall of the blocking dielectric layer52are physically exposed after removal of the vertical stack of metal-semiconductor alloy portions167.

Referring toFIG.6F, the processing steps ofFIG.5Lcan be performed to form a tunneling dielectric layer56and a first semiconductor channel layer601.

Referring toFIG.6G, the processing steps ofFIG.5Mcan be performed to deposit an optional patterning film77, and to anisotropically etch horizontal bottom portions of the first semiconductor channel layer601, the tunneling dielectric layer56, and the blocking dielectric layer52located over the pedestal channel portion11(or located above the upper substrate semiconductor layer10in case a pedestal channel portion is not present) at the bottom of each memory opening49. A center portion of the top surface of the pedestal channel portion11can be vertically recessed by the anisotropic etch process. In case a pedestal channel portion11is not present in the memory opening49, a portion of the horizontal surface of the upper substrate semiconductor layer10can be vertically recessed underneath the memory opening49. The patterning film77(if present) can be subsequently removed, for example, by ashing.

Referring toFIG.6H, the processing steps ofFIG.5Ncan be performed to form a second semiconductor channel layer602. The materials of the first semiconductor channel layer601and the second semiconductor channel layer602are collectively referred to as a semiconductor channel material. The combination of the blocking dielectric layer52, the tunneling dielectric layer56, the first semiconductor channel layer601, and the second semiconductor channel layer602can completely fill the volumes of the annular lateral recesses provided at the levels of the insulating layers32.

Referring toFIG.6I, the processing steps ofFIG.5Ocan be performed to form a dielectric core62in each memory opening49.

Referring toFIG.6J, the processing steps ofFIG.5Pcan be performed to form a doped semiconductor portion such as a drain region63at an upper portion of each memory opening49. Each adjoining pair of a first semiconductor channel layer601(if present) and a second semiconductor channel layer602can collectively form a vertical semiconductor channel60through which electrical current can flow when a vertical NAND device including the vertical semiconductor channel60is turned on. A tunneling dielectric layer56is surrounded by a vertical stack of semiconductor material portions54S, and laterally surrounds a portion of the vertical semiconductor channel60. Each adjoining set of a tunneling dielectric layer56, a vertical stack of semiconductor material portions54S, and a blocking dielectric layer52collectively constitute a memory film50, which includes a vertical stack of memory elements that can store a respective data bit with a macroscopic retention time.

Each combination of a memory film50and a vertical semiconductor channel60within a memory opening49constitutes a memory stack structure55. The memory stack structure55is a combination of a semiconductor channel60, a tunneling dielectric layer56, a plurality of memory elements comprising a vertical stack of semiconductor material portions54S, and a blocking dielectric layer52. Each combination of a pedestal channel portion11(if present), a memory stack structure55, a dielectric core62, and a drain region63within a memory opening49is herein referred to as a memory opening fill structure58. Each combination of a pedestal channel portion11(if present), a memory film50, a vertical semiconductor channel60, a dielectric core62, and a drain region63within each support opening19fills the respective support openings19, and constitutes a support pillar structure.

FIGS.6K and6Lillustrate an alternative configuration of the second exemplary memory opening fill structure. Referring toFIG.6K, the alternative configuration of the first exemplary memory opening fill structure can be derived from the structure illustrated inFIG.6Eby filling the annular lateral recesses149with a dielectric fill material. Specifically, a dielectric fill material such as undoped silicate glass or a doped silicate glass can be deposited in the remaining volumes of the annular lateral recesses149after removal of the vertical stack of metal-semiconductor alloy portions67. In one embodiment, the dielectric fill material may have a higher etch rate than the material of the blocking dielectric layer52. For example, the dielectric fill material may include borosilicate glass, which can provide an etch rate in dilute hydrofluoric acid than the etch rate of undoped silicate glass by a factor in a range from 100 to 10,000.

Portions of the dielectric fill material can be removed from outside the annular lateral recesses149by etching back the dielectric fill material. An isotropic etch process or an anisotropic etch process may be employed. The chemistry of the etch process employed to etch the dielectric fill material can be selective to the material of the semiconductor material portions54S and the material of the blocking dielectric layer52. Remaining portions of the dielectric fill material filling the annular lateral recesses149comprise a vertical stack of annular insulating material portions57. In case an anisotropic etch process is employed to pattern the annular insulating material portions57, inner sidewalls of the annular insulating material portions57may be vertically coincident with inner sidewalls of the semiconductor material portions54S.

Referring toFIG.6L, the processing steps ofFIGS.6F-6Jcan be performed to provide an alternative configuration of the second exemplary memory opening fill structure58. In this case, the tunneling dielectric layer56can be formed directly on the vertical stack of annular insulating material portions57. The memory film50can comprise the blocking dielectric layer52, the vertical stack of semiconductor material portions54S, the vertical stack of annular insulating material portions57(which can contact the vertical stack of semiconductor material portions54S), and the tunneling dielectric layer56.

FIGS.7A-7Nare sequential schematic vertical cross-sectional views of a memory opening within the first exemplary structure during formation of a third exemplary memory opening fill structure containing a hybrid charge storage structures containing a continuous charge storage dielectric layer and discrete floating gates, according to an embodiment of the present disclosure. The third exemplary memory opening fill structure can be formed within each memory opening49in lieu of the first or second exemplary memory opening fill structure described above.

Referring toFIG.7A, a memory opening49is illustrated after formation of annular lateral recesses149at levels of the insulating layers32. The first exemplary structure ofFIG.7Amay be the same as the first exemplary structure illustrated inFIG.5C.

Referring toFIG.7B, the processing steps ofFIG.5Dcan be performed to form a blocking dielectric layer52. Subsequently, a continuous charge storage dielectric layer, such as a silicon nitride layer53, can be deposited on the physically exposed surfaces of the blocking dielectric layer52by a conformal deposition process such as a chemical vapor deposition process or an atomic layer deposition process. The silicon nitride layer53can have a thickness in a range from 1 nm to 8 nm, such as from 2 nm to 6 nm, although lesser and greater thicknesses can also be employed. The silicon nitride layer53vertically extends through layers of the alternating stack (32,42), and contacts an outer sidewall of each discrete tubular semiconductor material portion54S within the vertical stack of discrete tubular semiconductor material portions54S. The silicon nitride layer53can be in contact with the inner sidewall of the blocking dielectric layer52.

Referring toFIG.7C, the processing steps ofFIG.5Ecan be performed to form a metal layer66L directly on the silicon nitride layer53.

Referring toFIG.7D, the processing steps ofFIG.5Fcan optionally be performed to anisotropically deposit an optional patterning film47, and to anisotropically etch portions of the metal layer66L that are not masked by the patterning film47. Remaining portions of the metal layer66L after the anisotropic etch process include a vertical stack of discrete metal portions66. Alternatively, if the metal layer66L comprised cobalt, then it may be self-segregated into discrete metal portions66by an anneal as described with respect toFIG.6Babove.

Referring toFIG.7E, the patterning film47(if present) can be subsequently removed, for example, by ashing.

Referring toFIG.7F, the processing steps ofFIG.5Hcan be performed to conformally deposit a semiconductor material layer54L.

Referring toFIG.7G, the processing steps ofFIG.5Ican be performed to anisotropically etch horizontal portions of the semiconductor material layer54L and the metal layer66L that overlie the insulating cap layer70, and to remove a horizontal portion of the semiconductor material layer54L located at the bottom of the memory opening49(such as the horizontal portion of the semiconductor material layer54L located above the pedestal channel portion11).

Referring toFIG.7H, the processing steps ofFIG.5Jcan be performed. Specifically, a thermal anneal process is performed at an elevated temperature that induces formation of a metal-semiconductor alloy between the material of the metal portions66and the material of the semiconductor material layer54L. Generally, the thickness of the metal layer66L and the thickness of the semiconductor material layer54L can be selected to ensure that the entire volume of the metal portions66react with the semiconductor material layer54L to form metal-semiconductor alloy portions67. A vertical stack of metal-semiconductor alloy portions67can be formed by reacting the vertical stack of metal portions66with portions of the semiconductor material layer54L located at levels of the insulating layers32. Unreacted portions of the semiconductor material layer54L remain at each level of the sacrificial material layers42located over the top surface of the pedestal channel portion11. The set of unreacted portions of the semiconductor material layer54L in the memory opening49comprise a vertical stack of semiconductor material portions54S.

Referring toFIG.7I, the processing steps of5K can be performed. Specifically, a selective isotropic etch process that etches the material of the metal-semiconductor alloy portions67selective to the material of the semiconductor material portions54S can be performed. The vertical stack of metal-semiconductor alloy portions67is removed selective to unreacted portions of the semiconductor material layer54L, i.e., the vertical stack of semiconductor material portions54S. The vertical stack of semiconductor material portions54S remain at levels of the spacer material layers (such as the sacrificial material layers42). In one embodiment, each semiconductor portion54S can have a have a tubular shape. The vertical stack of semiconductor material portions54S can be subsequently employed as a vertical stack of charge storage elements, which can function as floating gates of a NAND string. Portions of the inner sidewall of the silicon nitride layer53are physically exposed after removal of the vertical stack of metal-semiconductor alloy portions67.

Referring toFIG.7J, the processing steps ofFIG.5Lcan be performed to form the tunneling dielectric layer56and the optional first semiconductor channel layer601.

Referring toFIG.7K, the processing steps ofFIG.5Mcan optionally be performed to anisotropically deposit a patterning film77over the insulating cap layer70and the topmost portion of the first semiconductor channel layer601that overlies the topmost spacer material layer (such as the topmost sacrificial material layer42). An anisotropic etch process can be performed to remove the horizontal bottom portions of the first semiconductor channel layer601, the tunneling dielectric layer56, the silicon nitride layer53, and the blocking dielectric layer52located over the pedestal channel portion11(or located above the upper substrate semiconductor layer10in case a pedestal channel portion is not present) at the bottom of each memory opening49. A center portion of the top surface of the pedestal channel portion11can be vertically recessed by the anisotropic etch process. In case a pedestal channel portion11is not present in the memory opening49, a portion of the horizontal surface of the upper substrate semiconductor layer10can be vertically recessed underneath the memory opening49. The patterning film77can be subsequently removed, for example, by ashing.

A surface of the pedestal channel portion11(or a surface of the upper substrate semiconductor layer10in case the pedestal channel portions11are not employed) can be physically exposed underneath the opening through the first semiconductor channel layer601, the tunneling dielectric layer56, and the blocking dielectric layer52. Optionally, the physically exposed semiconductor surface at the bottom of each memory cavity49′ can be vertically recessed so that the recessed semiconductor surface underneath the memory cavity49′ is vertically offset from the topmost surface of the pedestal channel portion11(or of the upper substrate semiconductor layer10in case pedestal channel portions11are not employed) by a recess distance. The vertical stack of semiconductor material portions54S function as discrete charge storage elements that are floating gates. The continuous silicon nitride layer53functions as an additional charge storage material portion that continuously extends through each layer of the alternating stack (32,42) located above the horizontal plane including the top surface of the pedestal channel portion11. The combination of the silicon nitride layer53and the vertical stack of semiconductor material portions54S constitute a composite charge storage structure including charge storage elements at each level of the spacer material layers (such as the sacrificial material layers42). A set of the blocking dielectric layer52, the silicon nitride layer53, the vertical stack of semiconductor material portions54S, and the tunneling dielectric layer56in a memory opening49constitutes a memory film50. In one embodiment, the first semiconductor channel layer601, the tunneling dielectric layer56, the silicon nitride layer53, and the blocking dielectric layer52can have vertically coincident sidewalls.

Referring toFIG.7L, the processing steps ofFIG.5Ncan be performed to deposit a second semiconductor channel layer602directly on the semiconductor surface of the pedestal channel portion11or the upper substrate semiconductor layer10if the pedestal channel portion11is omitted, and directly on the first semiconductor channel layer601. The combination of the blocking dielectric layer52, the silicon nitride layer53, the tunneling dielectric layer56, the first semiconductor channel layer601, and the second semiconductor channel layer602can completely fill the volumes of the annular lateral recesses provided at the levels of the insulating layers32.

Referring toFIG.7M, the processing steps of50can be performed a dielectric core62in each memory opening49.

Referring toFIG.7N, the processing steps ofFIG.5Pcan be performed to form a doped semiconductor material portion such as a drain region63. Each adjoining pair of a first semiconductor channel layer601and a second semiconductor channel layer602can collectively form a vertical semiconductor channel60through which electrical current can flow when a vertical NAND device including the vertical semiconductor channel60is turned on. Each combination of a memory film50and a vertical semiconductor channel60within a memory opening49constitutes a memory stack structure55. The memory stack structure55is a combination of a semiconductor channel60, a tunneling dielectric layer56, a plurality of memory elements comprising a vertical stack of semiconductor material portions54S and portions of the silicon nitride layer53located at the levels of the spacer material layers42, and a blocking dielectric layer52. Each combination of a pedestal channel portion11(if present), a memory stack structure55, a dielectric core62, and a drain region63within a memory opening49is herein referred to as a memory opening fill structure58. Each combination of a pedestal channel portion11(if present), a memory film50, a vertical semiconductor channel60, a dielectric core62, and a drain region63within each support opening19fills the respective support openings19, and constitutes a support pillar structure.

In one embodiment, the tunneling dielectric layer56has a laterally-undulating vertical cross-sectional profile, and comprises laterally-protruding portions located at levels of the insulating layers32and contacting horizontal annular surfaces of the blocking dielectric layer52and overlying or underlying portions of the spacer material layers (such as the sacrificial material layers42) that are proximal to the vertical stack of discrete tubular semiconductor material portions54S.

FIGS.7O and7Pillustrate an alternative configuration of the third exemplary memory opening fill structure. Referring toFIG.7O, the alternative configuration of the third exemplary memory opening fill structure can be derived from the structure illustrated inFIG.7Iby filling the annular lateral recesses149with a dielectric fill material. Specifically, a dielectric fill material such as undoped silicate glass or a doped silicate glass can be deposited in the remaining volumes of the annular lateral recesses149after removal of the vertical stack of metal-semiconductor alloy portions67. In one embodiment, the dielectric fill material may have a higher etch rate than the material of the blocking dielectric layer52. For example, the dielectric fill material may include borosilicate glass, which can provide an etch rate in dilute hydrofluoric acid than the etch rate of undoped silicate glass by a factor in a range from 100 to 10,000.

Portions of the dielectric fill material can be removed from outside the annular lateral recesses149by etching back the dielectric fill material. An isotropic etch process or an anisotropic etch process may be employed. The chemistry of the etch process employed to etch the dielectric fill material can be selective to the material of the semiconductor material portions54S and the material of the blocking dielectric layer52. Remaining portions of the dielectric fill material filling the annular lateral recesses149comprise a vertical stack of annular insulating material portions57. In case an anisotropic etch process is employed to pattern the annular insulating material portions57, inner sidewalls of the annular insulating material portions57may be vertically coincident with inner sidewalls of the semiconductor material portions54S.

Referring toFIG.7P, the processing steps ofFIGS.7J-7Ncan be performed to provide an alternative configuration of the third exemplary memory opening fill structure58. In this case, the tunneling dielectric layer56can be formed directly on the vertical stack of annular insulating material portions57. The memory film50can comprise the blocking dielectric layer52, the silicon nitride layer53, the vertical stack of semiconductor material portions54S, the vertical stack of annular insulating material portions57(which can contact the vertical stack of semiconductor material portions54S), and the tunneling dielectric layer56.

The memory opening fill structure ofFIG.7Pcomprises a vertical stack of annular insulating material portions57located at each level of the insulating layers32between the blocking dielectric layer52and the tunneling dielectric layer56. The tunneling dielectric layer56comprises a straight outer sidewall contacting each annular insulating material portion57within the vertical stack of annular insulating material portions57and contacting the vertical stack of discrete tubular semiconductor material portions54S.

In the third exemplary memory opening fill structure58ofFIG.7Nand the alternative embodiment ofFIG.7P, all surfaces of the vertical stack of discrete tubular semiconductor material portions54S are in contact with a surface of the silicon nitride liner53or a surface of the tunneling dielectric layer56.

The combination of the silicon nitride layer53and the vertical stack of discrete tubular semiconductor material portions54S constitutes charge storage structures (53,54S). Generally, the charge storage structures (53,54S) comprises a vertical stack of discrete tubular semiconductor material portions54S and at least one continuous silicon nitride material portion in contact with the vertical stack of discrete tubular semiconductor material portions54S. In one embodiment, the at least one silicon nitride material portion comprises a silicon nitride layer53vertically extending through layers of the alternating stack (32,42) and contacting an outer sidewall of each discrete tubular semiconductor material portion54S within the vertical stack of discrete tubular semiconductor material portions54S. In one embodiment shown inFIG.7N, at the level of the insulating layers32, the silicon nitride layer53is in contact with an inner sidewall of the blocking dielectric layer52and the outer sidewall of the tunneling dielectric layer56. In one embodiment, all surfaces of the vertical stack of discrete tubular semiconductor material portions54S can be in contact with a surface of the silicon nitride liner53or a surface of the tunneling dielectric layer56.

FIGS.8A-8Fare sequential schematic vertical cross-sectional views of a memory opening within the first exemplary structure during formation of a fourth exemplary memory opening fill structure containing discrete charge storage dielectric portions according to an embodiment of the present disclosure. The fourth exemplary memory opening fill structure can be formed within each memory opening49in lieu of the first, second, or third exemplary memory opening fill structure described above.

Referring toFIG.8A, the structure for forming a fourth exemplary memory opening fill structure can be derived from the structure ofFIG.5K, the structure ofFIG.6E, or the structure ofFIG.7Iby nitriding the vertical stack of semiconductor material portions54S. The vertical stack of semiconductor material portions54S is at least partially converted into a vertical stack of silicon nitride material portions54N, which may be a vertical stack of discrete tubular silicon nitride material portions54N. In one embodiment, if the vertical stack of semiconductor material portions54S completely converted into a vertical stack of silicon nitride material portions54N, then each silicon nitride material portion54N may have a graded silicon-to-nitrogen ratio with a lower ratio at the inner portion facing the memory opening49than at the outer portion facing the spacer material layers42. In one embodiment, the thickness of each silicon nitride material portion54N can be in a range from 3 nm to 30 nm, such as from 5 nm to 15 nm, although lesser and greater thicknesses can also be employed.

Referring toFIG.8B, the processing steps ofFIG.5Lcan be performed to form the blocking dielectric layer52and an optional first semiconductor channel layer601.

Referring toFIG.8C, the processing steps ofFIG.5Mcan be performed to optionally deposit a patterning film77, and to anisotropically etch horizontal bottom portions of the first semiconductor channel layer601(if present), the tunneling dielectric layer56, and the blocking dielectric layer52located over the pedestal channel portion11(or located above the upper substrate semiconductor layer10in case a pedestal channel portion is not present) at the bottom of each memory opening49. A center portion of the top surface of the pedestal channel portion11can be vertically recessed by the anisotropic etch process. In case a pedestal channel portion11is not present in the memory opening49, a portion of the horizontal surface of the upper substrate semiconductor layer10can be vertically recessed underneath the memory opening49. The patterning film77can be subsequently removed, for example, by ashing.

Referring toFIG.8D, the processing steps ofFIG.5Ncan be performed to form a second semiconductor channel layer602. The materials of the first semiconductor channel layer601and the second semiconductor channel layer602are collectively referred to as a semiconductor channel material. The combination of the blocking dielectric layer52, the tunneling dielectric layer56, the first semiconductor channel layer601, and the second semiconductor channel layer602can completely fill the volumes of the annular lateral recesses provided at the levels of the insulating layers32.

Referring toFIG.8E, the processing steps ofFIG.5Ocan be performed to form a dielectric core62in each memory opening49.

Referring toFIG.8F, the processing steps ofFIG.5Pcan be performed to form a doped semiconductor portion such as a drain region63at an upper portion of each memory opening49. Each adjoining pair of a first semiconductor channel layer601and a second semiconductor channel layer602can collectively form a vertical semiconductor channel60through which electrical current can flow when a vertical NAND device including the vertical semiconductor channel60is turned on. A tunneling dielectric layer56is surrounded by a vertical stack of silicon nitride material portions54N, and laterally surrounds a portion of the vertical semiconductor channel60. Each adjoining set of a tunneling dielectric layer56, a vertical stack of silicon nitride material portions54N, and a blocking dielectric layer52collectively constitute a memory film50, which includes a vertical stack of memory elements that can store a respective data bit with a macroscopic retention time.

Each combination of a memory film50and a vertical semiconductor channel60within a memory opening49constitutes a memory stack structure55. The memory stack structure55is a combination of a semiconductor channel60, a tunneling dielectric layer56, a plurality of memory elements comprising a vertical stack of silicon nitride material portions54N, and a blocking dielectric layer52. Each combination of a pedestal channel portion11(if present), a memory stack structure55, a dielectric core62, and a drain region63within a memory opening49is herein referred to as a memory opening fill structure58. Each combination of a pedestal channel portion11(if present), a memory film50, a vertical semiconductor channel60, a dielectric core62, and a drain region63within each support opening19fills the respective support openings19, and constitutes a support pillar structure.

FIGS.8G and8Hillustrate an alternative configuration of the fourth exemplary memory opening fill structure. Referring toFIG.8G, the alternative configuration of the fourth exemplary memory opening fill structure can be derived from the structure illustrated inFIG.8Aby filling the annular lateral recesses149with a dielectric fill material. Specifically, a dielectric fill material such as undoped silicate glass or a doped silicate glass can be deposited in the remaining volumes of the annular lateral recesses149after removal of the vertical stack of metal-semiconductor alloy portions67. In one embodiment, the dielectric fill material may have a higher etch rate than the material of the blocking dielectric layer52. For example, the dielectric fill material may include borosilicate glass, which can provide an etch rate in dilute hydrofluoric acid than the etch rate of undoped silicate glass by a factor in a range from 100 to 10,000.

Portions of the dielectric fill material can be removed from outside the annular lateral recesses149by etching back the dielectric fill material. An isotropic etch process or an anisotropic etch process may be employed. The chemistry of the etch process employed to etch the dielectric fill material can be selective to the material of the silicon nitride material portions54N and the material of the blocking dielectric layer52. Remaining portions of the dielectric fill material filling the annular lateral recesses149comprise a vertical stack of annular insulating material portions57. In case an anisotropic etch process is employed to pattern the annular insulating material portions57, inner sidewalls of the annular insulating material portions57may be vertically coincident with inner sidewalls of the silicon nitride material portions54N.

Referring toFIG.8H, the processing steps ofFIGS.8B-8Fcan be performed to provide an alternative configuration of the first exemplary memory opening fill structure58. In this case, the tunneling dielectric layer56can be formed directly on the vertical stack of annular insulating material portions57. The memory film50can comprise the blocking dielectric layer52, the vertical stack of silicon nitride material portions54N, the vertical stack of annular insulating material portions57(which can contact the vertical stack of silicon nitride material portions54N), and the tunneling dielectric layer56.

FIGS.9A-9Fare sequential schematic vertical cross-sectional views of a memory opening within the first exemplary structure during formation of a fifth exemplary memory opening fill structure containing hybrid charge storage structures including discrete dielectric charge storage portions and floating gates, according to an embodiment of the present disclosure. The fifth exemplary memory opening fill structure can be formed within each memory opening49in lieu of the first, second, third, or fourth exemplary memory opening fill structure described above.

Referring toFIG.9A, the structure for forming a fifth exemplary memory opening fill structure can be derived from the structure ofFIG.5K, the structure ofFIG.6E, or the structure ofFIG.7Iby partially nitriding the vertical stack of semiconductor material portions54S. A vertical stack of composite charge storage structures (54S,54N) can be formed by converting surface portions of the vertical stack of discrete tubular semiconductor material portions54S into silicon nitride material portions54N. Each of the composite charge storage structures (54S,54N) comprises a respective semiconductor material portion54S which is a remaining portion of a respective one of the discrete tubular semiconductor material portions54S and a respective silicon nitride material portion54N which is formed by nitridation of a surface portion of the respective one of the discrete tubular semiconductor material portions54S. In one embodiment, each silicon nitride material portion54N comprises an interfacial region located in proximity to a respective one of the semiconductor material portions54S and having a graded silicon-to-nitrogen ratio with decreases from portion54N toward portion54S. The thickness of each semiconductor material portion54S can be in a range from 1 nm to 30 nm, such as from 2 nm to 20 nm, although lesser and greater thicknesses can also be employed. The thickness of each silicon nitride material portion54N can be in a range from 1 nm to 30 nm, such as from 2 nm to 20 nm, although lesser and greater thicknesses can also be employed. The thickness of each composite charge storage structure (54S,54N) can be in a range from 3 nm to 30 nm, such as from 5 nm to 15 nm, although lesser and greater thicknesses can also be employed.

Referring toFIG.9B, the processing steps ofFIG.5Lcan be performed to form the blocking dielectric layer52and optionally the first semiconductor channel layer601.

Referring toFIG.9C, the processing steps ofFIG.5Mcan be performed to deposit a patterning film77, and to anisotropically etch horizontal bottom portions of the first semiconductor channel layer601, the tunneling dielectric layer56, and the blocking dielectric layer52located over the pedestal channel portion11(or located above the upper substrate semiconductor layer10in case a pedestal channel portion is not present) at the bottom of each memory opening49. A center portion of the top surface of the pedestal channel portion11can be vertically recessed by the anisotropic etch process. In case a pedestal channel portion11is not present in the memory opening49, a portion of the horizontal surface of the upper substrate semiconductor layer10can be vertically recessed underneath the memory opening49. The patterning film77can be subsequently removed, for example, by ashing.

Referring toFIG.9D, the processing steps ofFIG.5Ncan be performed to form a second semiconductor channel layer602. The materials of the first semiconductor channel layer601and the second semiconductor channel layer602are collectively referred to as a semiconductor channel material. The combination of the blocking dielectric layer52, the tunneling dielectric layer56, the first semiconductor channel layer601, and the second semiconductor channel layer602can completely fill the volumes of the annular lateral recesses provided at the levels of the insulating layers32.

Referring toFIG.9E, the processing steps ofFIG.5Ocan be performed to form a dielectric core62in each memory opening49.

Referring toFIG.9F, the processing steps ofFIG.5Pcan be performed to form a doped semiconductor portion such as a drain region63at an upper portion of each memory opening49. Each adjoining pair of a first semiconductor channel layer601and a second semiconductor channel layer602can collectively form a vertical semiconductor channel60through which electrical current can flow when a vertical NAND device including the vertical semiconductor channel60is turned on. A tunneling dielectric layer56is surrounded by a vertical stack of composite charge storage structures (54S,54N), and laterally surrounds a portion of the vertical semiconductor channel60. Each adjoining set of a tunneling dielectric layer56, a vertical stack of composite charge storage structures (54S,54N), and a blocking dielectric layer52collectively constitute a memory film50, which includes a vertical stack of memory elements that can store a respective data bit with a macroscopic retention time.

Each combination of a memory film50and a vertical semiconductor channel60within a memory opening49constitutes a memory stack structure55. The memory stack structure55is a combination of a semiconductor channel60, a tunneling dielectric layer56, a plurality of memory elements comprising a vertical stack of composite charge storage structures (54S,54N), and a blocking dielectric layer52. Each combination of a pedestal channel portion11(if present), a memory stack structure55, a dielectric core62, and a drain region63within a memory opening49is herein referred to as a memory opening fill structure58. Each combination of a pedestal channel portion11(if present), a memory film50, a vertical semiconductor channel60, a dielectric core62, and a drain region63within each support opening19fills the respective support openings19, and constitutes a support pillar structure.

FIGS.9G and9Hillustrate an alternative configuration of the fourth exemplary memory opening fill structure. Referring toFIG.9G, the alternative configuration of the fourth exemplary memory opening fill structure can be derived from the structure illustrated inFIG.9Aby filling the annular lateral recesses149with a dielectric fill material. Specifically, a dielectric fill material such as undoped silicate glass or a doped silicate glass can be deposited in the remaining volumes of the annular lateral recesses149after removal of the vertical stack of metal-semiconductor alloy portions67. In one embodiment, the dielectric fill material may have a higher etch rate than the material of the blocking dielectric layer52. For example, the dielectric fill material may include borosilicate glass, which can provide an etch rate in dilute hydrofluoric acid than the etch rate of undoped silicate glass by a factor in a range from 100 to 10,000.

Portions of the dielectric fill material can be removed from outside the annular lateral recesses149by etching back the dielectric fill material. An isotropic etch process or an anisotropic etch process may be employed. The chemistry of the etch process employed to etch the dielectric fill material can be selective to the material of the composite charge storage structures (54S,54N) and the material of the blocking dielectric layer52. Remaining portions of the dielectric fill material filling the annular lateral recesses149comprise a vertical stack of annular insulating material portions57. In case an anisotropic etch process is employed to pattern the annular insulating material portions57, inner sidewalls of the annular insulating material portions57may be vertically coincident with inner sidewalls of the composite charge storage structures (54S,54N).

Referring toFIG.9H, the processing steps ofFIGS.9B-9Fcan be performed to provide an alternative configuration of the first exemplary memory opening fill structure58. In this case, the tunneling dielectric layer56can be formed directly on the vertical stack of annular insulating material portions57. The memory film50can comprise the blocking dielectric layer52, the vertical stack of composite charge storage structures (54S,54N), the vertical stack of annular insulating material portions57(which can contact the vertical stack of composite charge storage structures (54S,54N)), and the tunneling dielectric layer56.

FIGS.10A-10Mare sequential schematic vertical cross-sectional views of a memory opening within the first exemplary structure during formation of a sixth exemplary memory opening fill structure containing floating gates with flange portions according to an embodiment of the present disclosure. The sixth exemplary memory opening fill structure can be formed within each memory opening49in lieu of the first, second, third, fourth, or fifth exemplary memory opening fill structure described above.

Referring toFIG.10A, a structure for forming a sixth exemplary memory opening fill structure is illustrated, which may be the same as the structure ofFIG.5D.

Referring toFIG.10B, a metal layer66L can be conformally deposited on the inner sidewalls of the blocking dielectric layer. The metal layer66L can include any metal that can form a metal-semiconductor alloy such as a metal silicide. In one embodiment, the metal layer66L can include at least one transition metal that can form a metal silicide. For example, the metal layer66L can include tungsten, titanium, cobalt, molybdenum, platinum, nickel, and/or any other transition metal that forms a metal silicide upon reaction with silicon. The metal layer66L can be deposited by a conformal deposition method such as a chemical vapor deposition process or an atomic layer deposition process. The thickness of the metal layer66L may be greater than one half of the thickness of each insulating layer32. In one embodiment, the metal layer fills an entire volume of each cavity in the annular lateral recesses149. In one embodiment, the thickness of the metal layer66L over sidewalls of the spacer material layers (such as the sacrificial material layers42) can be in a range from 10 nm to 50, such as from 20 nm to 25 nm, although lesser and greater thicknesses can also be employed.

Referring toFIG.10C, an optional anisotropic deposition process, such as a physical vapor deposition process (e.g., sputtering), may be optionally performed to deposit additional portions of the metal on horizontal surfaces of the metal layer66L. Horizontal portions of the metal layer66L can be thickened. The anisotropic metal deposition process increases the thickness of horizontal portions of the metal layer66L so that removal of horizontal portions of a semiconductor material layer through formation of metal-semiconductor alloy portions is facilitated at a subsequent processing step. Alternatively, the step ofFIG.10Cmay be omitted.

Referring toFIG.10D, an isotropic etch process such as a wet etch process can be performed to thin the metal layer66L (i.e., to partially recess the metal layer66L). Alternatively, if the metal layer66L comprises cobalt, then the metal layer66L may self-segregate during an anneal as described above to form the structure shown inFIG.10D. Remaining portions of the metal layer66L include vertical stack of discrete metal portions66.

The discrete metal portions66can be formed within but not completely filling a respective one of the annular lateral recesses149of the memory opening49. Each discrete metal portion66within the vertical stack of discrete metal portions66comprises an inner sidewall that is laterally offset outward from portions of an inner sidewall of the blocking dielectric layer52located at levels of the spacer material layers (such as the sacrificial material layers42).

Thus, the vertical stack of discrete metal portions66can be formed in the annular lateral recesses149. The vertical stack of discrete metal portions66is formed directly on portions of an inner sidewall of the blocking dielectric layer52located at levels of the insulating layers32.

The discrete metal portions66may have a respective tubular shape. Each discrete metal portion66can have an inner sidewall that is laterally offset outward from sidewalls of the spacer material layers (such as the sacrificial material layers42). In one embodiment, the discrete metal portion66can comprise, and/or can consist essentially of, tungsten, titanium, cobalt, molybdenum, platinum, nickel, and/or any other transition metal that forms a metal silicide upon reaction with silicon. In one embodiment, the discrete metal portions66can have a thickness in a range from 2 nm to 20 nm, such as from 4 nm to 10 nm, although lesser and greater thicknesses can also be employed. Horizontal remaining portions of the metal layer66L may be present over the top surface of the pedestal channel portion11and over the top surface of the insulating cap layer70.

Referring toFIG.10E, a semiconductor material layer54L can be conformally deposited on the physically exposed surfaces of the vertical stack of the metal portions66and on the physically exposed surfaces of the blocking dielectric layer52. The semiconductor material layer54L includes a semiconductor material that can form a metal-semiconductor alloy with the material of the metal portions66. For example, the semiconductor material layer54L can include silicon and/or germanium. In one embodiment, the semiconductor material layer54L can include amorphous silicon, polysilicon, germanium, and/or a silicon-germanium alloy. The thickness of the semiconductor material layer54L can be selected such that the entirety of the vertical stack of discrete metal portions66can react with the semiconductor material of the semiconductor material layer54L during a subsequent anneal process. In one embodiment, the semiconductor material layer54L can have a thickness in a range from 2 nm to 20 nm, such as from 4 nm to 10 nm, although lesser and greater thicknesses can also be employed.

Referring toFIG.10F, a thermal anneal process is performed at an elevated temperature that induces formation of a metal-semiconductor alloy between the material of the metal portions66and the material of the semiconductor material layer ML. The elevated temperature may be in a range from 400 degrees Celsius to 1,000 degrees Celsius, although lower and higher temperatures may also be employed depending on the composition of the metal-semiconductor alloy. It is not necessary to form a low-resistance phase metal-semiconductor alloy as required for typical semiconductor applications in this case. Even high-resistance intermediate phase metal-semiconductor alloys formed at a relatively low temperature is sufficient provided that such metal-semiconductor alloys can be subsequently removed selective to unreacted portions of the semiconductor material layer54L in a selective etch process. Generally, the thickness of the discrete metal portions66and the thickness of the semiconductor material layer54L can be selected to ensure that the entire volume of the metal portions66react with the semiconductor material layer54L to form metal-semiconductor alloy portions67. A vertical stack of metal-semiconductor alloy portions67can be formed by reacting the vertical stack of metal portions66with portions of the semiconductor material layer54L located at levels of the insulating layers32. Unreacted portions of the semiconductor material layer54L remain at each level of the sacrificial material layers42located over the top surface of the pedestal channel portion11. The set of unreacted portions of the semiconductor material layer54L in the memory opening49comprise a vertical stack of semiconductor material portions54S.

In one embodiment, the metal-semiconductor alloy portions67can be laterally offset outward from a cylindrical vertical plane including sidewalls of the spacer material layers (such as the sacrificial material layers42) around the memory opening49, while parts of the semiconductor material portions54S protrude into the recesses149. Specifically, each of the semiconductor material portions54S comprises a tubular portion54T, an upper flange portion54U laterally extending outward into the recess149from an upper end of an outer sidewall of the tubular portion54T, and a lower flange portion54F laterally extending outward into the recess149from a lower end of the outer sidewall of the tubular portion54T.

Referring toFIG.10G, a selective isotropic etch process that etches the material of the metal-semiconductor alloy portions67selective to the material of the semiconductor material portions54S can be performed. The vertical stack of metal-semiconductor alloy portions67is removed selective to unreacted portions of the semiconductor material layer54L, i.e., the vertical stack of semiconductor material portions54S. The vertical stack of semiconductor material portions54S remain at levels of the spacer material layers (such as the sacrificial material layers42) and extends partially into the recesses149. In one embodiment, each of the semiconductor material portions54S comprises a tubular portion54T, an upper flange portion54U, and a lower flange portion54F. The upper flange portion54U and the lower flange portion54F of each semiconductor material portion54S are located in the recess149and provide increased charge trapping volume in additional to the charge trapping volume provided by the tubular portion54T. Thus, the thickness of the spacer material layers (such as the sacrificial material layers42) can be reduced relative to conventional NAND devices in which charge storage elements do not include flange portions. The vertical stack of discrete semiconductor material portions54S can be subsequently employed as a vertical stack of charge storage elements, which can function as floating gates of a NAND string. Portions of the inner sidewall of the blocking dielectric layer52are physically exposed after removal of the vertical stack of metal-semiconductor alloy portions67. The vertical stack of discrete metal portions66and portions of the semiconductor material layer54L that are adjacent to the vertical stack of discrete metal portions66are removed in the form of a vertical stack of metal-semiconductor alloy portions67.

Referring toFIG.10H, a tunneling dielectric layer56can be deposited employing a conformal deposition process such as a chemical vapor deposition process, as described in the previous embodiments. The tunneling dielectric layer56can be formed directly on the portions of the inner sidewall of the blocking dielectric layer52that are physically exposed and located at the levels of the insulating layers32. The tunneling dielectric layer56can also be formed directly on the vertical stack of discrete cylindrical semiconductor material portions54S. The combination of the blocking dielectric layer52, the vertical stack of semiconductor material portions54S, and the tunneling dielectric layer56constitutes a memory film50.

Referring toFIG.10I, the processing steps ofFIG.5Lcan be performed to form the optional first semiconductor channel layer601on the tunneling dielectric layer56.

Referring toFIG.10J, the processing steps ofFIG.5Mcan optionally be performed to deposit an optional patterning film77. An anisotropic etch process can be performed to remove the horizontal bottom portions of the first semiconductor channel layer601(if present), the tunneling dielectric layer56, and the blocking dielectric layer52located over the pedestal channel portion11(or located above the upper substrate semiconductor layer10in case a pedestal channel portion is not present) at the bottom of each memory opening49. A set of the blocking dielectric layer52, the vertical stack of semiconductor material portions54S, and the tunneling dielectric layer56in a memory opening49constitutes a memory film50. In one embodiment, the first semiconductor channel layer601, the tunneling dielectric layer56, and the blocking dielectric layer52can have vertically coincident sidewalls. The patterning film77(if present) can be subsequently removed, for example, by ashing.

Referring toFIG.10K, the processing steps ofFIG.5Ncan be performed to deposit a second semiconductor channel layer602. The materials of the first semiconductor channel layer601and the second semiconductor channel layer602are collectively referred to as a semiconductor channel material. In other words, the semiconductor channel material is a set of all semiconductor material in the first semiconductor channel layer601and the second semiconductor channel layer602. The combination of flange portions of the semiconductor material portions54S, the blocking dielectric layer52, the tunneling dielectric layer56, the first semiconductor channel layer601, and the second semiconductor channel layer602can completely fill the volumes of the annular lateral recesses149provided at the levels of the insulating layers32.

Referring toFIG.10L, the processing steps ofFIG.5Ocan be performed to form a dielectric core62.

Referring toFIG.10M, the processing steps ofFIG.5Pcan be performed to form a doped semiconductor material portion such as a drain region63. Each adjoining set of a tunneling dielectric layer56, a vertical stack of semiconductor material portions54S, and a blocking dielectric layer52collectively constitute a memory film50, which includes a vertical stack of memory elements that can store a respective data bit with a macroscopic retention time. Each combination of a memory film50and a vertical semiconductor channel60within a memory opening49constitutes a memory stack structure55. The memory stack structure55is a combination of a semiconductor channel60, a tunneling dielectric layer56, a plurality of memory elements comprising a vertical stack of semiconductor material portions54S, and a blocking dielectric layer52. Each combination of a pedestal channel portion11(if present), a memory stack structure55, a dielectric core62, and a drain region63within a memory opening49is herein referred to as a memory opening fill structure58. Each combination of a pedestal channel portion11(if present), a memory film50, a vertical semiconductor channel60, a dielectric core62, and a drain region63within each support opening19fills the respective support openings19, and constitutes a support pillar structure.

FIGS.10N and10Oillustrate an alternative configuration of the first exemplary memory opening fill structure. Referring toFIG.10N, the alternative configuration of the first exemplary memory opening fill structure can be derived from the structure illustrated inFIG.10Gby filling the annular lateral recesses149with a dielectric fill material. Specifically, a dielectric fill material such as undoped silicate glass or a doped silicate glass can be deposited in the remaining volumes of the annular lateral recesses149after removal of the vertical stack of metal-semiconductor alloy portions67. In one embodiment, the dielectric fill material may have a higher etch rate than the material of the blocking dielectric layer52. For example, the dielectric fill material may include borosilicate glass, which can provide an etch rate in dilute hydrofluoric acid than the etch rate of undoped silicate glass by a factor in a range from 100 to 10,000.

Portions of the dielectric fill material can be removed from outside the annular lateral recesses149by etching back the dielectric fill material. An isotropic etch process or an anisotropic etch process may be employed. The chemistry of the etch process employed to etch the dielectric fill material can be selective to the material of the semiconductor material portions54S and the material of the blocking dielectric layer52. Remaining portions of the dielectric fill material filling the annular lateral recesses149comprise a vertical stack of annular insulating material portions57. In case an anisotropic etch process is employed to pattern the annular insulating material portions57, inner sidewalls of the annular insulating material portions57may be vertically coincident with inner sidewalls of the semiconductor material portions54S.

Referring toFIG.10O, the processing steps ofFIGS.10H-10Mcan be performed to provide an alternative configuration of the second exemplary memory opening fill structure58. In this case, the tunneling dielectric layer56can be formed directly on the vertical stack of annular insulating material portions57. The memory film50can comprise the blocking dielectric layer52, the vertical stack of semiconductor material portions54S, the vertical stack of annular insulating material portions57(which can contact the vertical stack of semiconductor material portions54S), and the tunneling dielectric layer56.

FIGS.11A-11Gare sequential schematic vertical cross-sectional views of a memory opening within the first exemplary structure during formation of a seventh exemplary memory opening fill structure containing discrete dielectric charge storage elements with flange portions according to an embodiment of the present disclosure. The seventh exemplary memory opening fill structure can be formed within each memory opening49in lieu of the first, second, third, fourth, fifth, or sixth exemplary memory opening fill structure described above.

Referring toFIG.11A, the structure for forming a seventh exemplary memory opening fill structure can be derived from the structure ofFIG.10Gby nitriding the vertical stack of semiconductor material portions54S. The vertical stack of semiconductor material portions54S is fully converted into a vertical stack of silicon nitride material portions54N. Each of the silicon nitride material portions54N comprises a tubular portion54T, an upper flange portion54U laterally extending into the recess149outward from an upper end of an outer sidewall of the tubular portion54T, and a lower flange portion54F laterally extending into the recess149outward from a lower end of the outer sidewall of the tubular portion54T. In one embodiment, each silicon nitride material portion54N has a graded silicon-to-nitrogen ratio, as described with respect toFIG.8Aabove. In one embodiment, the thickness of the tubular portion54T of each silicon nitride material portion54N can be in a range from 3 nm to 30 nm, such as from 5 nm to 15 nm, although lesser and greater thicknesses can also be employed. In one embodiment, the tubular portion54T, the upper flange portion54U, and the lower flange portion54F can have substantially the same thickness.

The vertical stack of silicon nitride material portions54N is located at levels of the spacer material layers (such as the sacrificial material layers42). In one embodiment, each of the silicon nitride material portions54N comprises a tubular portion54T, an upper flange portion54U, and a lower flange portion54F. The upper flange portion54U and the lower flange portion54F of each silicon nitride material portion54N provide increased charge trapping volume in additional to the charge trapping volume provided by the tubular portion54T. Thus, the thickness of the spacer material layers (such as the sacrificial material layers42) can be reduced relative to conventional NAND devices in which charge storage elements do not include flange portions. The vertical stack of discrete silicon nitride material portions54N can be subsequently employed as a vertical stack of charge storage elements, which can function as floating gates of a NAND string. Portions of the inner sidewall of the blocking dielectric layer52are physically exposed after removal of the vertical stack of metal-semiconductor alloy portions67.

Referring toFIG.11B, the processing steps ofFIG.10Hcan be performed to form a tunneling dielectric layer56.

Referring toFIG.11C, the processing steps ofFIG.10Ican be performed to form a first semiconductor channel layer601.

Referring toFIG.11D, the processing steps ofFIG.10Jcan optionally be performed to deposit the optional patterning film77, and to anisotropically etch horizontal bottom portions of the first semiconductor channel layer601(if present), the tunneling dielectric layer56, and the blocking dielectric layer52located over the pedestal channel portion11(or located above the upper substrate semiconductor layer10in case a pedestal channel portion is not present) at the bottom of each memory opening49. A center portion of the top surface of the pedestal channel portion11can be vertically recessed by the anisotropic etch process. In case a pedestal channel portion11is not present in the memory opening49, a portion of the horizontal surface of the upper substrate semiconductor layer10can be vertically recessed underneath the memory opening49. The patterning film77(if present) can be subsequently removed, for example, by ashing.

Referring toFIG.11E, the processing steps ofFIG.10Kcan be performed to form a second semiconductor channel layer602. The materials of the first semiconductor channel layer601and the second semiconductor channel layer602are collectively referred to as a semiconductor channel material. The combination of the blocking dielectric layer52, the tunneling dielectric layer56, the first semiconductor channel layer601, and the second semiconductor channel layer602can completely fill the volumes of the annular lateral recesses provided at the levels of the insulating layers32.

Referring toFIG.11F, the processing steps ofFIG.10Lcan be performed to form a dielectric core62in each memory opening49.

Referring toFIG.11G, the processing steps ofFIG.10Mcan be performed to form a doped semiconductor portion such as a drain region63at an upper portion of each memory opening49. Each adjoining pair of a first semiconductor channel layer601and a second semiconductor channel layer602can collectively form a vertical semiconductor channel60through which electrical current can flow when a vertical NAND device including the vertical semiconductor channel60is turned on. A tunneling dielectric layer56is surrounded by a vertical stack of silicon nitride material portions54N, and laterally surrounds a portion of the vertical semiconductor channel60. Each adjoining set of a tunneling dielectric layer56, a vertical stack of silicon nitride material portions54N, and a blocking dielectric layer52collectively constitute a memory film50, which includes a vertical stack of memory elements that can store a respective data bit with a macroscopic retention time.

Each combination of a memory film50and a vertical semiconductor channel60within a memory opening49constitutes a memory stack structure55. The memory stack structure55is a combination of a semiconductor channel60, a tunneling dielectric layer56, a plurality of memory elements comprising a vertical stack of silicon nitride material portions54N, and a blocking dielectric layer52. Each combination of a pedestal channel portion11(if present), a memory stack structure55, a dielectric core62, and a drain region63within a memory opening49is herein referred to as a memory opening fill structure58. Each combination of a pedestal channel portion11(if present), a memory film50, a vertical semiconductor channel60, a dielectric core62, and a drain region63within each support opening19fills the respective support openings19, and constitutes a support pillar structure.

FIGS.11H and11Iillustrate an alternative configuration of the fourth exemplary memory opening fill structure. Referring toFIG.11H, the alternative configuration of the seventh exemplary memory opening fill structure can be derived from the structure illustrated inFIG.10Gby filling the annular lateral recesses149with a dielectric fill material. The processing steps ofFIG.10Ncan be employed to form a vertical stack of annular insulating material portions57in unfilled volumes of the annular lateral recesses of each memory opening49.

Referring toFIG.11I, the processing steps ofFIGS.10H-10Mcan be performed to provide an alternative configuration of the first exemplary memory opening fill structure58. In this case, the tunneling dielectric layer56can be formed directly on the vertical stack of annular insulating material portions57. The memory film50can comprise the blocking dielectric layer52, the vertical stack of silicon nitride material portions54N, the vertical stack of annular insulating material portions57(which can contact the vertical stack of silicon nitride material portions54N), and the tunneling dielectric layer56.

FIGS.12A-12Gare sequential schematic vertical cross-sectional views of a memory opening within the first exemplary structure during formation of an eighth exemplary memory opening fill structure containing hybrid discrete charge storage structures including discrete dielectric charge storage portions and floating gates with flange portions, according to an embodiment of the present disclosure. The eighth exemplary memory opening fill structure can be formed within each memory opening49in lieu of the first, second, third, fourth, fifth, sixth, or seventh exemplary memory opening fill structure described above.

Referring toFIG.12A, the structure for forming the eight exemplary memory opening fill structure can be derived from the structure ofFIG.10Gby partially nitriding the vertical stack of semiconductor material portions54S. Surface portions of the semiconductor material portions54S that are physically exposed to the memory cavity49′ are converted into silicon nitride material portions54N, while underlying portions of the semiconductor material portions54S that contact the blocking dielectric layer52remain as semiconductor material portions54S. Thus, a vertical stack of silicon nitride material portions54N is formed by the nitridation process, and the remaining vertical stack of semiconductor material portions54S has a lesser volume than the vertical stack of semiconductor material portions54S provided at the processing steps ofFIG.10G. A vertical stack of composite charge storage structures (54S,54N) can be formed by converting surface portions of the vertical stack of discrete semiconductor material portions54S into the silicon nitride material portions54N. In one embodiment, each silicon nitride material portion54N comprises an interfacial region located in proximity to a respective one of the discrete semiconductor material portions54S and having a graded silicon-to-nitrogen ratio, as described above. Each of the composite charge storage structures (54S,54N) comprises a respective semiconductor material portion54S (which is a remaining portion of a respective one of the discrete semiconductor material portions54S as provided at the processing steps ofFIG.10G) and a respective silicon nitride material portion54N which is formed by nitridation of a surface portion of the respective one of the discrete semiconductor material portions54S.

Each of the composite charge storage structures (54S,54N) comprises a tubular portion54T, an upper flange portion54U laterally extending outward into the recess149from an upper end of an outer sidewall of the tubular portion54T, and a lower flange portion54F laterally extending outward into the recess149from a lower end of the outer sidewall of the tubular portion54T. Each semiconductor material portion54S includes a respective tubular portion, a respective upper flange portion, and a respective lower flange portion. Each silicon nitride material portion54N includes a respective tubular portion, a respective upper flange portion, and a respective lower flange portion. The thickness of the tubular portion of each semiconductor material portion54S can be in a range from 1 nm to 30 nm, such as from 2 nm to 20 nm, although lesser and greater thicknesses can also be employed. The thickness of the tubular portion of each silicon nitride material portion54N can be in a range from 1 nm to 30 nm, such as from 2 nm to 20 nm, although lesser and greater thicknesses can also be employed. The thickness of each tubular portion of composite charge storage structure (54S,54N) can be in a range from 3 nm to 30 nm, such as from 5 nm to 15 nm, although lesser and greater thicknesses can also be employed. The thickness of a tubular portion of a composite charge storage structure (54S,54N) can be formed between an inner cylindrical sidewall and an outer cylindrical sidewall of the respective composite charge storage structure (54S,54N).

The vertical stack composite charge storage structures (54S,54N) is located at levels of the spacer material layers (such as the sacrificial material layers42) and partially protrudes into the recesses149. In one embodiment, each of the composite charge storage structures (54S,54N) comprises a tubular portion54T, an upper flange portion54U, and a lower flange portion54F. The upper flange portion54U and the lower flange portion54F of each composite charge storage structure (54S,54N) provide increased charge trapping volume in additional to the charge trapping volume provided by the tubular portion54T. Thus, the thickness of the spacer material layers (such as the sacrificial material layers42) can be reduced relative to conventional NAND devices in which charge storage elements do not include flange portions. The vertical stack of composite charge storage structures (54S,54N) can be subsequently employed as a vertical stack of charge storage elements, which can function as hybrid floating gates and charge trapping dielectric elements of a NAND string. Portions of the inner sidewall of the blocking dielectric layer52are physically exposed after removal of the vertical stack of metal-semiconductor alloy portions67.

Referring toFIG.12B, the processing steps ofFIG.10Hcan be performed to form a tunneling dielectric layer56.

Referring toFIG.12C, the processing steps ofFIG.10Ican be performed to form the optional first semiconductor channel layer601.

Referring toFIG.12D, the processing steps ofFIG.10Jcan optionally be performed to deposit the optional patterning film77, and to anisotropically etch horizontal bottom portions of the first semiconductor channel layer601(if present), the tunneling dielectric layer56, and the blocking dielectric layer52located over the pedestal channel portion11(or located above the upper substrate semiconductor layer10in case a pedestal channel portion is not present) at the bottom of each memory opening49. A center portion of the top surface of the pedestal channel portion11can be vertically recessed by the anisotropic etch process. In case a pedestal channel portion11is not present in the memory opening49, a portion of the horizontal surface of the upper substrate semiconductor layer10can be vertically recessed underneath the memory opening49. The patterning film77can be subsequently removed, for example, by ashing.

Referring toFIG.12E, the processing steps ofFIG.10Kcan be performed to form a second semiconductor channel layer602. The materials of the first semiconductor channel layer601and the second semiconductor channel layer602are collectively referred to as a semiconductor channel material. The combination of the blocking dielectric layer52, the tunneling dielectric layer56, the first semiconductor channel layer601, and the second semiconductor channel layer602can completely fill the volumes of the annular lateral recesses provided at the levels of the insulating layers32.

Referring toFIG.12F, the processing steps ofFIG.10Lcan be performed to form a dielectric core62in each memory opening49.

Referring toFIG.12G, the processing steps ofFIG.10Mcan be performed to form a doped semiconductor portion such as a drain region63at an upper portion of each memory opening49. Each adjoining pair of a first semiconductor channel layer601and a second semiconductor channel layer602can collectively form a vertical semiconductor channel60through which electrical current can flow when a vertical NAND device including the vertical semiconductor channel60is turned on. A tunneling dielectric layer56is surrounded by a vertical stack of composite charge storage structures (54S,54N), and laterally surrounds a portion of the vertical semiconductor channel60. Each adjoining set of a tunneling dielectric layer56, a vertical stack of composite charge storage structures (54S,54N), and a blocking dielectric layer52collectively constitute a memory film50, which includes a vertical stack of memory elements that can store a respective data bit with a macroscopic retention time.

Each combination of a memory film50and a vertical semiconductor channel60within a memory opening49constitutes a memory stack structure55. The memory stack structure55is a combination of a semiconductor channel60, a tunneling dielectric layer56, a plurality of memory elements comprising a vertical stack of composite charge storage structures (54S,54N), and a blocking dielectric layer52. Each combination of a pedestal channel portion11(if present), a memory stack structure55, a dielectric core62, and a drain region63within a memory opening49is herein referred to as a memory opening fill structure58. Each combination of a pedestal channel portion11(if present), a memory film50, a vertical semiconductor channel60, a dielectric core62, and a drain region63within each support opening19fills the respective support openings19, and constitutes a support pillar structure.

FIGS.12H and12Iillustrate an alternative configuration of the fourth exemplary memory opening fill structure. Referring toFIG.12H, the alternative configuration of the fourth exemplary memory opening fill structure can be derived from the structure illustrated inFIG.10Gby filling the annular lateral recesses149with a dielectric fill material. The processing steps ofFIG.10Ncan be employed to form a vertical stack of annular insulating material portions57in unfilled volumes of the annular lateral recesses of each memory opening49.

Referring toFIG.12I, the processing steps ofFIGS.10H-10Mcan be performed to provide an alternative configuration of the first exemplary memory opening fill structure58. In this case, the tunneling dielectric layer56can be formed directly on the vertical stack of annular insulating material portions57. The memory film50can comprise the blocking dielectric layer52, the vertical stack of composite charge storage structures (54S,54N), the vertical stack of annular insulating material portions57(which can contact the vertical stack of silicon nitride material portions54N), and the tunneling dielectric layer56.

Referring toFIG.13, the first exemplary structure is illustrated after formation of memory opening fill structures58and support pillar structure20within the memory openings49and the support openings19, respectively. An instance of a memory opening fill structure58can be formed within each memory opening49of the structure ofFIGS.4A and4B. An instance of the support pillar structure20can be formed within each support opening19of the structure ofFIGS.4A and4B.

Each memory stack structure55includes a vertical semiconductor channel60, which may comprise multiple semiconductor channel layers (601,602), and a memory film50. The memory film50may comprise a tunneling dielectric layer56laterally surrounding the vertical semiconductor channel60, a vertical stack of charge storage regions (comprising a charge storage layer54) laterally surrounding the tunneling dielectric layer56, and an optional blocking dielectric layer52. While the present disclosure is described employing the illustrated configuration for the memory stack structure, the methods of the present disclosure can be applied to alternative memory stack structures including different layer stacks or structures for the memory film50and/or for the vertical semiconductor channel60.

Referring toFIGS.14A and14B, a contact-level dielectric layer73can be formed over the alternating stack (32,42) of insulating layer32and sacrificial material layers42, and over the memory stack structures55and the support pillar structures20. The contact-level dielectric layer73includes a dielectric material that is different from the dielectric material of the sacrificial material layers42. For example, the contact-level dielectric layer73can include silicon oxide. The contact-level dielectric layer73can have a thickness in a range from 50 nm to 500 nm, although lesser and greater thicknesses can also be employed.

A photoresist layer (not shown) can be applied over the contact-level dielectric layer73, and is lithographically patterned to form openings in areas between clusters of memory stack structures55. The pattern in the photoresist layer can be transferred through the contact-level dielectric layer73, the alternating stack (32,42) and/or the retro-stepped dielectric material portion65employing an anisotropic etch to form backside trenches79, which vertically extend from the top surface of the contact-level dielectric layer73at least to the top surface of the substrate (9,10), and laterally extend through the memory array region100and the staircase region300.

In one embodiment, the backside trenches79can laterally extend along a first horizontal direction hd1and can be laterally spaced apart among one another along a second horizontal direction hd2that is perpendicular to the first horizontal direction hd1. The memory stack structures55can be arranged in rows that extend along the first horizontal direction hd1. The drain select level isolation structures72can laterally extend along the first horizontal direction hd1. Each backside trench79can have a uniform width that is invariant along the lengthwise direction (i.e., along the first horizontal direction hd1). Each drain select level isolation structure72can have a uniform vertical cross-sectional profile along vertical planes that are perpendicular to the first horizontal direction hd1that is invariant with translation along the first horizontal direction hd1. Multiple rows of memory stack structures55can be located between a neighboring pair of a backside trench79and a drain select level isolation structure72, or between a neighboring pair of drain select level isolation structures72. In one embodiment, the backside trenches79can include a source contact opening in which a source contact via structure can be subsequently formed. The photoresist layer can be removed, for example, by ashing.

Dopants of the second conductivity type can be implanted into portions of the upper substrate semiconductor layer10that underlie the backside trenches79to form source regions61. The atomic concentration of the dopants of the second conductivity type in the source regions61can be in a range from 5.0×1018/cm3to 2.0×1021/cm3, although lesser and greater atomic concentrations can also be employed. Surface portions of the upper substrate semiconductor layer10that extend between each source region61and adjacent memory opening fill structures58comprise horizontal semiconductor channels59.

Referring toFIG.15, an etchant that selectively etches the spacer material of the sacrificial material layers42with respect to the insulating material of the insulating layers32can be introduced into the backside trenches79, for example, employing an etch process. Backside recesses43are formed in volumes from which the sacrificial material layers42are removed. The removal of the spacer material of the sacrificial material layers42can be selective to the insulating material of the insulating layers32, the material of the retro-stepped dielectric material portion65, the semiconductor material of the upper substrate semiconductor layer10, and the material of the outermost layer of the memory films50. In one embodiment, the sacrificial material layers42can include silicon nitride, and the materials of the insulating layers32and the retro-stepped dielectric material portion65can be selected from silicon oxide and dielectric metal oxides.

Each of the plurality of backside recesses43can extend substantially parallel to the top surface of the substrate (9,10). A backside recess43can be vertically bounded by a top surface of an underlying insulating layer32and a bottom surface of an overlying insulating layer32. In one embodiment, each backside recess43can have a uniform height throughout.

Referring toFIGS.16A and16B, physically exposed surface portions of the optional pedestal channel portions11and the upper substrate semiconductor layer10can be converted into dielectric material portions by thermal conversion and/or plasma conversion of the semiconductor materials into dielectric materials. For example, thermal conversion and/or plasma conversion can be employed to convert a surface portion of each pedestal channel portion11into a tubular dielectric spacer116, and to convert each physically exposed surface portion of the upper substrate semiconductor layer10into a planar dielectric portion (not illustrated). In one embodiment, each tubular dielectric spacer116can be topologically homeomorphic to a torus, i.e., generally ring-shaped. As used herein, an element is topologically homeomorphic to a torus if the shape of the element can be continuously stretched without destroying a hole or forming a new hole into the shape of a torus. The tubular dielectric spacers116include a dielectric material that includes the same semiconductor element as the pedestal channel portions11and additionally includes at least one non-metallic element such as oxygen and/or nitrogen such that the material of the tubular dielectric spacers116is a dielectric material. In one embodiment, the tubular dielectric spacers116can include a dielectric oxide, a dielectric nitride, or a dielectric oxynitride of the semiconductor material of the pedestal channel portions11. Dopants in the drain regions63, the source regions61, and the semiconductor channels60can be activated during the anneal process that forms the planar dielectric portions and the tubular dielectric spacers116. Alternatively, an additional anneal process may be performed to active the electrical dopants in the drain regions63, the source regions61, and the semiconductor channels60.

A backside blocking dielectric layer44can be optionally formed. The backside blocking dielectric layer44, if present, comprises a dielectric material that functions as a control gate dielectric for the control gates to be subsequently formed in the backside recesses43. In case the blocking dielectric layer52is present within each memory opening, the backside blocking dielectric layer44is optional. In case the blocking dielectric layer52is omitted, the backside blocking dielectric layer44is present.

The backside blocking dielectric layer44can be formed in the backside recesses43and on a sidewall of the backside trench79. The backside blocking dielectric layer44can be formed directly on horizontal surfaces of the insulating layers32and sidewalls of the memory stack structures55within the backside recesses43. If the backside blocking dielectric layer44is formed, formation of the tubular dielectric spacers116and the planar dielectric portion prior to formation of the backside blocking dielectric layer44is optional. In one embodiment, the backside blocking dielectric layer44can be formed by a conformal deposition process such as atomic layer deposition (ALD) or low pressure chemical vapor deposition (LPCVD). The backside blocking dielectric layer44can consist essentially of aluminum oxide. The thickness of the backside blocking dielectric layer44can be in a range from 1 nm to 15 nm, such as 2 to 6 nm, although lesser and greater thicknesses can also be employed.

The dielectric material of the backside blocking dielectric layer44can be a dielectric metal oxide such as aluminum oxide, a dielectric oxide of at least one transition metal element, a dielectric oxide of at least one Lanthanide element, a dielectric oxide of a combination of aluminum, at least one transition metal element, and/or at least one Lanthanide element. Alternatively or additionally, the backside blocking dielectric layer44can include a silicon oxide layer. The backside blocking dielectric layer44can be deposited by a conformal deposition method such as low pressure chemical vapor deposition or atomic layer deposition. The backside blocking dielectric layer44is formed on the sidewalls of the backside trenches79, horizontal surfaces and sidewalls of the insulating layers32, the portions of the sidewall surfaces of the memory stack structures55that are physically exposed to the backside recesses43, and a top surface of the planar dielectric portion. A backside cavity is present within the portion of each backside trench79that is not filled with the backside blocking dielectric layer44.

At least one metallic material can be deposited in the backside recesses43. For example, a combination of a metallic barrier layer and a metallic fill material can be deposited in the backside recesses43. The metallic barrier layer includes an electrically conductive metallic material that can function as a diffusion barrier layer and/or adhesion promotion layer for a metallic fill material to be subsequently deposited. The metallic barrier layer can include a conductive metallic nitride material such as TiN, TaN, WN, MoN, or a stack thereof, or can include a conductive metallic carbide material such as TiC, TaC, WC, or a stack thereof. In one embodiment, the metallic barrier layer can be deposited by a conformal deposition process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). The thickness of the metallic barrier layer can be in a range from 2 nm to 8 nm, such as from 3 nm to 6 nm, although lesser and greater thicknesses can also be employed. In one embodiment, the metallic barrier layer can consist essentially of a conductive metal nitride such as TiN. The metallic fill material can be deposited by a conformal deposition method, which can be, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), electroless plating, electroplating, or a combination thereof. In one embodiment, the metallic fill material layer can consist essentially of at least one elemental metal. The at least one elemental metal of the metallic fill material layer can be selected, for example, from tungsten, molybdenum, cobalt, ruthenium, titanium, and tantalum. In one embodiment, the metallic fill material layer can consist essentially of a single elemental metal. In one embodiment, the metallic fill material layer can be deposited employing a fluorine-containing precursor gas such as WF6. In one embodiment, the metallic fill material layer can be a tungsten layer including a residual level of fluorine atoms as impurities. The metallic fill material layer is spaced from the insulating layers32and the memory stack structures55by the metallic barrier layer, which can block diffusion of fluorine atoms therethrough.

A plurality of electrically conductive layers46can be formed in the plurality of backside recesses43, and a continuous electrically conductive material layer (not shown) can be formed on the sidewalls of each backside trench79and over the contact-level dielectric layer73. Each electrically conductive layer46includes a portion of the metallic barrier layer46A and a portion of the metallic fill material layer46B that are located between a vertically neighboring pair of dielectric material layers such as a pair of insulating layers32. The continuous electrically conductive material layer includes a continuous portion of the at least one conductive material that is located in the backside trenches79or above the contact-level dielectric layer73.

Each sacrificial material layer42can be replaced with an electrically conductive layer46. A backside cavity is present in the portion of each backside trench79that is not filled with the backside blocking dielectric layer44and the continuous electrically conductive material layer. A tubular dielectric spacer116laterally surrounds a pedestal channel portion11. A bottommost electrically conductive layer46laterally surrounds each tubular dielectric spacer116upon formation of the electrically conductive layers46.

The deposited metallic material of the continuous electrically conductive material layer is etched back from the sidewalls of each backside trench79and from above the contact-level dielectric layer73, for example, by an isotropic wet etch, an anisotropic dry etch, or a combination thereof. Each remaining portion of the deposited metallic material in the backside recesses43constitutes an electrically conductive layer46. Each electrically conductive layer46can be a conductive line structure. Thus, the sacrificial material layers42are replaced with the electrically conductive layers46.

Each electrically conductive layer46can function as a combination of a plurality of control gate electrodes located at a same level and a word line electrically interconnecting, i.e., electrically shorting, the plurality of control gate electrodes located at the same level. The plurality of control gate electrodes within each electrically conductive layer46are the control gate electrodes for the vertical memory devices including the memory stack structures55. In other words, each electrically conductive layer46can be a word line that functions as a common control gate electrode for the plurality of vertical memory devices.

In one embodiment, the removal of the continuous electrically conductive material layer can be selective to the material of the backside blocking dielectric layer44. In this case, a horizontal portion of the backside blocking dielectric layer44can be present at the bottom of each backside trench79. In another embodiment, the removal of the continuous electrically conductive material layer may not be selective to the material of the backside blocking dielectric layer44or, the backside blocking dielectric layer44may not be employed. The planar dielectric portions can be removed during removal of the continuous electrically conductive material layer. A backside cavity is present within each backside trench79.

Referring toFIG.17, an insulating material layer can be formed in the backside trenches79and over the contact-level dielectric layer73by a conformal deposition process. Exemplary conformal deposition processes include, but are not limited to, chemical vapor deposition and atomic layer deposition. The insulating material layer includes an insulating material such as silicon oxide, silicon nitride, a dielectric metal oxide, an organosilicate glass, or a combination thereof. In one embodiment, the insulating material layer can include silicon oxide. The insulating material layer can be formed, for example, by low pressure chemical vapor deposition (LPCVD) or atomic layer deposition (ALD). The thickness of the insulating material layer can be in a range from 1.5 nm to 60 nm, although lesser and greater thicknesses can also be employed.

If a backside blocking dielectric layer44is present, the insulating material layer can be formed directly on surfaces of the backside blocking dielectric layer44and directly on the sidewalls of the electrically conductive layers46. If a backside blocking dielectric layer44is not employed, the insulating material layer can be formed directly on sidewalls of the insulating layers32and directly on sidewalls of the electrically conductive layers46.

An anisotropic etch is performed to remove horizontal portions of the insulating material layer from above the contact-level dielectric layer73and at the bottom of each backside trench79. Each remaining portion of the insulating material layer constitutes an insulating spacer74. A backside cavity is present within a volume surrounded by each insulating spacer74. A top surface of the upper substrate semiconductor layer10can be physically exposed at the bottom of each backside trench79.

An upper portion of the upper substrate semiconductor layer10that extends between the source region61and the plurality of pedestal channel portions11constitutes a horizontal semiconductor channel59for a plurality of field effect transistors. The horizontal semiconductor channel59is connected to multiple vertical semiconductor channels60through respective pedestal channel portions11. The horizontal semiconductor channel59contacts the source region61and the plurality of pedestal channel portions11. A bottommost electrically conductive layer46provided upon formation of the electrically conductive layers46within the alternating stack (32,46) can comprise a select gate electrode for the field effect transistors. Each source region61is formed in an upper portion of the substrate (9,10). Semiconductor channels (59,11,60) extend between each source region61and a respective set of drain regions63. The semiconductor channels (59,11,60) include the vertical semiconductor channels60of the memory stack structures55.

A backside contact via structure76can be formed within each backside cavity. Each contact via structure76can fill a respective backside cavity. The contact via structures76can be formed by depositing at least one conductive material in the remaining unfilled volume (i.e., the backside cavity) of the backside trench79. For example, the at least one conductive material can include a conductive liner76A and a conductive fill material portion76B. The conductive liner76A can include a conductive metallic liner such as TiN, TaN, WN, WC, TiC, TaC, MoN, an alloy thereof, or a stack thereof. The thickness of the conductive liner76A can be in a range from 3 nm to 30 nm, although lesser and greater thicknesses can also be employed. The conductive fill material portion76B can include a metal or a metallic alloy. For example, the conductive fill material portion76B can include W, Mo, Cu, Al, Co, Ru, Ni, an alloy thereof, or a stack thereof.

In an alternative embodiment, the contact via structure76may be omitted and a horizontal source line may contact a side of a bottom portion of the vertical semiconductor channel60.

The at least one conductive material can be planarized employing the contact-level dielectric layer73overlying the alternating stack (32,46) as a stopping layer. If chemical mechanical planarization (CMP) process is employed, the contact-level dielectric layer73can be employed as a CMP stopping layer. Each remaining continuous portion of the at least one conductive material in the backside trenches79constitutes a backside contact via structure76.

The backside contact via structure76extends through the alternating stack (32,46), and contacts a top surface of the source region61. If a backside blocking dielectric layer44is employed, the backside contact via structure76can contact a sidewall of the backside blocking dielectric layer44.

Referring toFIGS.18A and18B, additional contact via structures (88,86,8P) can be formed through the contact-level dielectric layer73, and optionally through the retro-stepped dielectric material portion65. For example, drain contact via structures88can be formed through the contact-level dielectric layer73on each drain region63. Word line contact via structures86can be formed on the electrically conductive layers46through the contact-level dielectric layer73, and through the retro-stepped dielectric material portion65. Peripheral device contact via structures8P can be formed through the retro-stepped dielectric material portion65directly on respective nodes of the peripheral devices.

The first exemplary structures can include a three-dimensional memory device. In one embodiment, the three-dimensional memory device comprises a monolithic three-dimensional NAND memory device. The electrically conductive layers46can comprise, or can be electrically connected to, a respective word line of the monolithic three-dimensional NAND memory device. The substrate (9,10) can comprise a silicon substrate. The vertical NAND memory device can comprise an array of monolithic three-dimensional NAND strings over the silicon substrate. The silicon substrate can contain an integrated circuit comprising a driver circuit (comprising a subset of the least one semiconductor device700) for the memory device located thereon. Alternatively, the driver circuit may be formed on a separate substrate and then bonded to the memory device. The electrically conductive layers46can comprise a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate (9,10), e.g., between a pair of backside trenches79. The plurality of control gate electrodes comprises at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level. The array of monolithic three-dimensional NAND strings can comprise: a plurality of semiconductor channels (59,11,60), wherein at least one end portion60of each of the plurality of semiconductor channels (59,11,60) extends substantially perpendicular to a top surface of the substrate (9,10) and comprising a respective one of the vertical semiconductor channels60, and a plurality of charge storage elements. Each charge storage element can be located adjacent to a respective one of the plurality of semiconductor channels (59,11,60).

FIG.19Ais a magnified view of a memory opening in the first exemplary structure ofFIGS.18A and18Bin case a first exemplary memory opening fill structure or a second exemplary memory opening fill structure is present in the memory opening according to an embodiment of the present disclosure. In this case, each charge storage element may comprise a semiconductor material portion54S, which may have a tubular configuration. The tunneling dielectric layer56is in direct contact with the blocking dielectric layer52at levels of the insulating layers32.

FIG.19Bis a magnified view of a memory opening in the first exemplary structure ofFIGS.18A and18Bin case an alternative configuration of the first exemplary memory opening fill structure or the second exemplary memory opening fill structure is present in the memory opening according to an embodiment of the present disclosure. In this case, each charge storage element may comprise a semiconductor material portion54S, which may have a tubular configuration. The tunneling dielectric layer56is in direct contact with inner sidewalls of the annular insulating material portions57at levels of the insulating layers32.

FIG.20Ais a magnified view of a memory opening in the first exemplary structure ofFIGS.18A and18Bin case a third exemplary memory opening fill structure is present in the memory opening according to an embodiment of the present disclosure. In this case, each charge storage element may comprise a combination of a semiconductor material portion54S (which may have a tubular configuration) and a portion of a silicon nitride layer53located at the level of the semiconductor material portion54S. The tunneling dielectric layer56is in direct contact with the blocking dielectric layer52at levels of the insulating layers32.

FIG.20Bis a magnified view of a memory opening in the first exemplary structure ofFIGS.18A and18Bin case an alternative configuration of the third exemplary memory opening fill structure is present in the memory opening according to an embodiment of the present disclosure. In this case, each charge storage element may comprise a combination of a semiconductor material portion54S (which may have a tubular configuration) and a portion of a silicon nitride layer53located at the level of the semiconductor material portion54S. The tunneling dielectric layer56is in direct contact with inner sidewalls of the annular insulating material portions57at levels of the insulating layers32.

FIG.21Ais a magnified view of a memory opening in the first exemplary structure ofFIGS.18A and18Bin case a fourth exemplary memory opening fill structure is present in the memory opening according to an embodiment of the present disclosure. In this case, each charge storage element may comprise a discrete silicon nitride material portion54N, which may have a tubular configuration. The tunneling dielectric layer56is in direct contact with the blocking dielectric layer52at levels of the insulating layers32.

FIG.21Bis a magnified view of a memory opening in the first exemplary structure ofFIGS.18A and18Bin case an alternative configuration of the fourth exemplary memory opening fill structure is present in the memory opening according to an embodiment of the present disclosure. In this case, each charge storage element may comprise a silicon nitride material portion54N, which may have a tubular configuration. The tunneling dielectric layer56is in direct contact with inner sidewalls of the annular insulating material portions57at levels of the insulating layers32.

FIG.22Ais a magnified view of a memory opening in the first exemplary structure ofFIGS.18A and18Bin case a fifth exemplary memory opening fill structure is present in the memory opening according to an embodiment of the present disclosure. In this case, each charge storage element may comprise a discrete, composite charge storage structure (54S,54N), which may have a tubular configuration. Each composite charge storage structure (54S,54N) can include a stack of a semiconductor material portion54S and a silicon nitride material portion54N. The tunneling dielectric layer56is in direct contact with the blocking dielectric layer52at levels of the insulating layers32.

FIG.22Bis a magnified view of a memory opening in the first exemplary structure ofFIGS.18A and18Bin case an alternative configuration of the fifth exemplary memory opening fill structure is present in the memory opening according to an embodiment of the present disclosure. In this case, each charge storage element may comprise a composite charge storage structure (54S,54N), which may have a tubular configuration. Each composite charge storage structure (54S,54N) can include a stack of a semiconductor material portion54S and a silicon nitride material portion54N. The tunneling dielectric layer56is in direct contact with inner sidewalls of the annular insulating material portions57at levels of the insulating layers32.

FIG.23Ais a magnified view of a memory opening in the first exemplary structure ofFIGS.18A and18Bin case a sixth exemplary memory opening fill structure is present in the memory opening according to an embodiment of the present disclosure. In this case, each charge storage element may comprise a discrete semiconductor material portion54S, which may have a tubular portion54T, an upper flange portion54U, and a lower flange portion54F. The tunneling dielectric layer56is in direct contact with the blocking dielectric layer52at levels of the insulating layers32.

FIG.23Bis a magnified view of a memory opening in the first exemplary structure ofFIGS.18A and18Bin case an alternative configuration of the sixth exemplary memory opening fill structure is present in the memory opening according to an embodiment of the present disclosure. In this case, each charge storage element may comprise a semiconductor material portion54S, which may have a tubular portion54T, an upper flange portion54U, and a lower flange portion54F. The tunneling dielectric layer56is in direct contact with inner sidewalls of the annular insulating material portions57at levels of the insulating layers32.

FIG.24Ais a magnified view of a memory opening in the first exemplary structure ofFIGS.18A and18Bin case a seventh exemplary memory opening fill structure is present in the memory opening according to an embodiment of the present disclosure. In this case, each charge storage element may comprise a discrete silicon nitride material portion54N, which may have a tubular portion54T, an upper flange portion54U, and a lower flange portion54F. The tunneling dielectric layer56is in direct contact with the blocking dielectric layer52at levels of the insulating layers32.

FIG.24Bis a magnified view of a memory opening in the first exemplary structure ofFIGS.18A and18Bin case an alternative configuration of the seventh exemplary memory opening fill structure is present in the memory opening according to an embodiment of the present disclosure. In this case, each charge storage element may comprise a silicon nitride material portion54N, which may have a tubular portion54T, an upper flange portion54U, and a lower flange portion54F. The tunneling dielectric layer56is in direct contact with inner sidewalls of the annular insulating material portions57at levels of the insulating layers32.

FIG.25Ais a magnified view of a memory opening in the first exemplary structure ofFIGS.18A and18Bin case a eighth exemplary memory opening fill structure is present in the memory opening according to an embodiment of the present disclosure. In this case, each charge storage element may comprise a discrete composite charge storage structure (54S,54N), which includes a stack of a semiconductor material portion54S and a silicon nitride material portion54N. Each composite charge storage structure (54S,54N) may have a tubular portion54T, an upper flange portion54U, and a lower flange portion54F. The tunneling dielectric layer56is in direct contact with the blocking dielectric layer52at levels of the insulating layers32.

FIG.25Bis a magnified view of a memory opening in the first exemplary structure ofFIGS.18A and18Bin case an alternative configuration of the eighth exemplary memory opening fill structure is present in the memory opening according to an embodiment of the present disclosure. In this case, each charge storage element may comprise a composite charge storage structure (54S,54N), which includes a stack of a semiconductor material portion54S and a silicon nitride material portion54N. Each composite charge storage structure (54S,54N) may have a tubular portion54T, an upper flange portion54U, and a lower flange portion54F. The tunneling dielectric layer56is in direct contact with inner sidewalls of the annular insulating material portions57at levels of the insulating layers32.

Referring to all drawings and according to various embodiments of the present disclosure, a three-dimensional memory device is provided, which comprises: an alternating stack of insulating layers32and electrically conductive layers46located over a substrate (9,10); a memory opening49vertically extending through the alternating stack (32,46), wherein the memory opening49has laterally-protruding portions (such as the annular lateral recesses149) that extend outward at each level of the insulating layers32; and a memory opening fill structure58located in the memory opening49and comprising, from outside to inside, a blocking dielectric layer52, charge storage structures {(54S,54N) or (54S,52)} comprising a vertical stack of discrete semiconductor material portions54S and at least one silicon nitride material portion (54N or53) in contact with the vertical stack54S, a tunneling dielectric layer56in contact with the charge storage structures {(54S,54N) or (54S,52)}, and a vertical semiconductor channel60.

In one embodiment, the at least one silicon nitride material portion54N comprises a vertical stack of discrete silicon nitride material portions54N in contact with a respective discrete semiconductor material portion54S within the vertical stack of discrete semiconductor material portions54S.

In one embodiment, each discrete silicon nitride material portion54N within the vertical stack of discrete silicon nitride material portions54N is in contact with the tunneling dielectric layer56; and each discrete semiconductor material portion54S within the vertical stack of discrete semiconductor material portions54S is not in contact with the tunneling dielectric layer56, and is spaced from the tunneling dielectric layer56by the vertical stack of discrete silicon nitride material portions54N.

In one embodiment, each silicon nitride material portion54N comprises a tubular portion54T having a uniform thickness between an inner sidewall and an outer sidewall, an upper flange portion54U extending outward from an upper periphery of the inner sidewall of the tubular portion54T, and a lower flange portion54F extending outward from a lower periphery of the inner sidewall of the tubular portion54T.

In one embodiment, each silicon nitride material portion54N comprises an interfacial region located in proximity to a respective one of the discrete semiconductor material portions54S and having a graded silicon-to-nitrogen ratio.

In one embodiment, the at least one silicon nitride material portion comprises a silicon nitride layer53vertically extending through layers of the alternating stack (32,46) and contacting an outer sidewall of each discrete semiconductor material portion54S within the vertical stack of discrete semiconductor material portions54S. In one embodiment, the silicon nitride layer53is in contact with an inner sidewall of the blocking dielectric layer52and an outer sidewall of the tunneling dielectric layer56. In one embodiment, all surfaces of the vertical stack of discrete semiconductor material portions54S are in contact with a surface of the silicon nitride liner53or a surface of the tunneling dielectric layer56.

In one embodiment, the tunneling dielectric layer56has a laterally-undulating vertical cross-sectional profile, and comprises laterally-protruding portions located at levels of the insulating layers32and contacting horizontal annular surfaces of the blocking dielectric layer52and overlying or underlying portions of the electrically conductive layers46that are proximal to the vertical stack of discrete semiconductor material portions54S.

In one embodiment, the memory opening fill structure58comprises a vertical stack of annular insulating material portions57located at each level of the insulating layers32between the blocking dielectric layer52and the tunneling dielectric layer56; and the tunneling dielectric layer56comprises a straight outer sidewall contacting each annular insulating material portion57within the vertical stack of annular insulating material portions57and contacting the vertical stack of discrete semiconductor material portions54S.

According to another aspect of the present disclosure, a three-dimensional memory device is provided, which comprises: an alternating stack of insulating layers32and electrically conductive layers46located over a substrate (9,10); a memory opening49vertically extending through the alternating stack (32,46), wherein the memory opening49has laterally-protruding portions (such as the annular lateral recesses149) that extend outward at levels of the insulating layers32; and a memory opening fill structure58located in the memory opening49and comprising, from outside to inside, a blocking dielectric layer52, a vertical stack of discrete charge storage material portions {54S,54N, (54S,54N)}, a tunneling dielectric layer56, and a vertical semiconductor channel60, wherein each charge storage material portion {54S,54N, (54S,54N)} comprises a tubular portion54T located at a level of a respective one of the electrically material layers46, an upper flange portion54U laterally extending outward from an upper end of an outer sidewall of the tubular portion54T, and a lower flange portion54F laterally extending outward from a lower end of the outer sidewall of the tubular portion54T.

In one embodiment, each charge storage material portion comprises a respective semiconductor material portion54S. In one embodiment, each charge storage material portion comprises a respective silicon nitride material portion54N. In one embodiment, each charge storage material portion comprises a respective stack of a semiconductor material portion54S and a silicon nitride material portion54N. In one embodiment, the semiconductor material portion54S of each charge storage material portion (54S,54N) does not contact the tunneling dielectric layer56, and is spaced from the tunneling dielectric layer56by a respective one of the silicon nitride material portions54N.

In one embodiment, the upper flange portion54U contacts a horizontal top surface of the blocking dielectric layer52; and the lower flange portion54F comprises a horizontal bottom surface of the blocking dielectric layer52.

In one embodiment, the blocking dielectric layer52have a laterally-undulating vertical cross-sectional profile; first tubular portions of the blocking dielectric layer52located at levels of the insulating layers32are laterally offset outward from second tubular portions of the blocking dielectric layer52located at levels of the electrically conductive layers46; and the first tubular portions of the blocking dielectric layer52are not in contact with (i.e., not in direct contact with) the vertical stack of charge storage material portions54.

In one embodiment, the vertical semiconductor channel60comprises: a tubular portion that vertically extends through a plurality of electrically conductive material layers46within the alternating stack (32,46); and laterally-protruding portions that protrude outward from the tubular portion at the levels of the insulating layers32(as illustrated, for example, inFIGS.19A,20A,21A,22A,23A,24A, and25A).

In one embodiment, the memory opening fill structure58comprises a vertical stack of annular insulating material portions57located at the levels of the insulating layers32between the blocking dielectric layer52and the tunneling dielectric layer56; and the tunneling dielectric layer56comprises a straight outer sidewall contacting each annular insulating material portion57within the vertical stack of annular insulating material portions57and contacting the vertical stack of charge storage material portions {54S,54N, (54S,54N)} (as illustrated inFIGS.19B,20B,21B,22B,23B,24B, and25B).

In one embodiment, the memory opening fill structure58comprises a doped semiconductor material portion (such as a drain region63) that overlies the vertical semiconductor channel60and forms a p-n junction at an interface with the vertical semiconductor channel60.

The various embodiments of the present disclosure can be employed to provide a vertical stack of discrete charge storage elements providing reduced charge leakage across vertical levels and/or increased charge storage capacity through use of flange portions for each charge storage element. The various embodiments of the present disclosure can facilitate device scaling along the vertical direction in a three-dimensional NAND memory device or other vertical memory devices.

Referring toFIG.26, a second exemplary structure according to a second embodiment of the present disclosure can be derived from the first exemplary structure ofFIG.1by forming an alternating stack of disposable material layers31and silicon nitride layers41. The disposable material layers31include a material that can be removed selective to the silicon nitride layers41and the upper substrate semiconductor layer10. For example, the disposable material layer31may include undoped silicate glass (i.e., silicon oxide) doped silicate glass (such as borosilicate glass), organosilicate glass, amorous carbon, or a silicon-germanium alloy including germanium at an atomic concentration greater than 15% (such as from 15% to 99%). In one embodiment, the disposable material layers31can include doped or undoped silicon oxide. The silicon nitride layers41can consist essentially of silicon nitride.

The disposable material layers31can be deposited by chemical vapor deposition, and can have a thickness in a range from 1.5 nm to 10 nm, such as from 3 nm to 6 nm, although lesser and greater thicknesses may also be employed. The silicon nitride layers41can be deposited by chemical vapor deposition, and can have a thickness in a range from 6 nm to 40 nm, although lesser and greater thicknesses may also be employed. The sum of the thickness of a disposable material layer31and a silicon nitride layer41can be less than the sum of the thickness of an insulating layer32and a sacrificial material layer42in the first exemplary structure. Further, the silicon nitride layers41may be thicker than the disposable material layers31. In one embodiment, a ratio of the thickness of a silicon nitride layer41to the thickness of a disposable material layer31can be in a range from 1.5 to 10, such as from 2 to 5, although lesser and greater ratios may also be employed. Generally, a lesser thickness for the disposable material layers31is preferable as long as the material of the disposable material layers31can be subsequently removed by a lateral isotropic etch process selective to the silicon nitride layers41. An insulating cap layer70can be deposited in the same manner as in the processing steps ofFIG.2.

Referring toFIG.27, the processing steps ofFIG.3can be performed to form stepped surfaces with any needed changes in view of the changes in the material compositions and thicknesses of the alternating stack of the disposable material layers31and the silicon nitride layers41relative to the alternating stack of the insulating layers32and the sacrificial material layers42in the first exemplary structure. A dielectric material can be deposited and planarized over the stepped surfaces to form a retro-stepped dielectric material portion64. The retro-stepped dielectric material portion64can include a dielectric material that provides a higher etch resistance to an etchant to be subsequently employed to remove the disposable material layers31. For example, if the disposable material layers31include a doped silicate glass or organosilicate glass, the retro-stepped dielectric material portion64can include silicon oxycarbide (e.g., carbon-doped silicate glass), which provides a significantly higher etch resistance to hydrofluoric acid than silicon oxide disposable material layers31.

Referring toFIGS.28A and28B, the processing steps ofFIGS.4A and4Bcan be performed with any needed changes to form memory openings49and support openings19in view of the changes in the material compositions and thicknesses of the alternating stack of the disposable material layers31and the silicon nitride layers41relative to the alternating stack of the insulating layers32and the sacrificial material layers42in the first exemplary structure.

Referring toFIG.28C, support pillar structures20are formed in the support openings19. Each support pillar structure20comprises a dielectric (i.e., insulating) material at least in its outer surface. In other embodiment, the entire support pillar structure20may be formed from a dielectric material. For example, each support pillar structure20may comprise a silicon nitride liner22deposited into the support opening19surrounding a silicon oxide core24deposited over the silicon nitride liner22. The silicon nitride liner22and the silicon oxide core24may be planarized by chemical mechanical planarization (i.e., polishing) such that their top surface is even with the top surface of the insulating cap layer70. The memory opening49may be covered with a sacrificial mask (e.g., photoresist) or filled with a sacrificial fill material (e.g., amorphous silicon) during the deposition of the silicon nitride liner22and the silicon oxide core24, and which may be removed after deposition of the silicon nitride liner22and the silicon oxide core24. Alternatively, the silicon nitride liner22and the silicon oxide core24may be deposited into the memory openings49and the support openings19followed by masking the support openings19and removing the silicon nitride liner22and the silicon oxide core24located in the memory openings49by etching.

FIGS.29A-29Hare sequential schematic vertical cross-sectional views of a memory opening49within the second exemplary structure during formation of a memory stack structure55, an optional dielectric core62, and a drain region63therein according to an embodiment of the present disclosure.

FIG.29Aillustrates a memory opening49at the processing steps ofFIG.28C.

Referring toFIG.29B, the processing steps ofFIG.5Bcan be performed to form a pedestal channel portion11in each memory opening49. Alternatively, the pedestal channel portion11may be omitted if a lateral source contact structure (e.g., direct strap contact) will be formed in contact with a side of the vertical semiconductor channel60in a subsequent step as will be described below with respect to the third embodiment.

Referring toFIG.29C, a stack of layers including a semiconductor liner151L, a charge storage material layer154L, a tunneling dielectric layer56, and an optional first semiconductor channel layer601can be sequentially deposited in the memory openings49.

The semiconductor liner151L can include a semiconductor material such as amorphous silicon, polysilicon, or a silicon-germanium alloy. The semiconductor liner151L includes a different material than the material of the disposable material layers31. In case the disposable material layers31include a silicon-germanium alloy, the semiconductor liner151L can include amorphous silicon or polysilicon so that the semiconductor liner151L functions as an etch stop structure. In case the disposable material layers31include undoped silicate glass, a doped silicate glass, or organosilicate glass, the semiconductor liner151L can include amorphous silicon, polysilicon, or a silicon-germanium alloy. The semiconductor liner151L may have a thickness in a range from 1 nm to 6 nm, such as from 2 nm to 4 nm, although lesser and greater thicknesses may also be employed.

Subsequently, the charge storage material layer154L can be formed. In one embodiment, the charge storage material layer154L can be a continuous layer that is deposited by a conformal deposition process. In one embodiment, the charge storage material layer154L can include a silicon nitride layer having a uniform thickness throughout. The thickness of the charge storage material layer154L can be in a range from 3 nm to 8 nm, although lesser and greater thicknesses may also be employed.

The optional first semiconductor channel layer601includes a semiconductor material such as at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the first semiconductor channel layer601includes amorphous silicon or polysilicon. The first semiconductor channel layer601can be formed by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD). The thickness of the first semiconductor channel layer601can be in a range from 2 nm to 10 nm, although lesser and greater thicknesses can also be employed. A memory cavity49′ is formed in the volume of each memory opening49that is not filled with the deposited material layers (52,54,56,601). In an alternative embodiment, a sacrificial cover material layer may be employed in lieu of the first semiconductor channel layer601. In this case, the sacrificial cover material layer can include any cover material that can protect the charge storage material layer154L during a subsequent anisotropic etch process.

Referring toFIG.29D, the optional first semiconductor channel layer601, the tunneling dielectric layer56, the charge storage material layer154L, the semiconductor liner151L are sequentially anisotropically etched employing at least one anisotropic etch process. The portions of the first semiconductor channel layer601, the tunneling dielectric layer56, the charge storage material layer154L, and the semiconductor liner151L located above the top surface of the insulating cap layer70can be removed by the at least one anisotropic etch process. Further, the horizontal portions of the first semiconductor channel layer601, the tunneling dielectric layer56, the charge storage material layer154L, and the semiconductor liner151L at a bottom of each memory cavity49′ can be removed to form openings in remaining portions thereof. Each of the first semiconductor channel layer601, the tunneling dielectric layer56, the charge storage material layer154L, and the semiconductor liner151L can be etched by a respective anisotropic etch process employing a respective etch chemistry, which may, or may not, be the same for the various material layers.

Each remaining portion of the first semiconductor channel layer601can have a tubular configuration. In one embodiment, the charge storage material layer154L can be a charge storage layer in which each portion adjacent to the silicon nitride layers41constitutes a charge storage region.

A surface of the pedestal channel portion11(or a surface of the upper substrate semiconductor layer10in case the pedestal channel portions11are not employed) can be physically exposed underneath the opening through the first semiconductor channel layer601, the tunneling dielectric layer56, the charge storage material layer154L, and the semiconductor liner151L. Optionally, the physically exposed semiconductor surface at the bottom of each memory cavity49′ can be vertically recessed so that the recessed semiconductor surface underneath the memory cavity49′ is vertically offset from the topmost surface of the pedestal channel portion11(or of the upper substrate semiconductor layer10in case pedestal channel portions11are not employed) by a recess distance. A tunneling dielectric layer56is located over the charge storage material layer154L. A set of a semiconductor liner151L, a charge storage material layer154L, and a tunneling dielectric layer56in a memory opening49constitutes a memory film50, which includes a plurality of charge storage regions (as embodied as the charge storage material layer154L) that are insulated from surrounding materials by the semiconductor liner151L and the tunneling dielectric layer56. In one embodiment, the first semiconductor channel layer601, the tunneling dielectric layer56, the charge storage material layer154L, and the semiconductor liner151L can have vertically coincident sidewalls. In case a sacrificial cover material layer is employed in lieu of the first semiconductor channel layer601, the sacrificial cover material layer can be removed selective to the charge storage material layer154L.

Referring toFIG.29E, a second semiconductor channel layer602can be deposited directly on the semiconductor surface of the pedestal channel portion11or the upper substrate semiconductor layer10if the pedestal channel portion11is omitted, and directly on the first semiconductor channel layer601. The second semiconductor channel layer602includes a semiconductor material such as at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the second semiconductor channel layer602includes amorphous silicon or polysilicon. The second semiconductor channel layer602can be formed by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD). The thickness of the second semiconductor channel layer602can be in a range from 2 nm to 10 nm, although lesser and greater thicknesses can also be employed. The second semiconductor channel layer602may partially fill the memory cavity49′ in each memory opening, or may fully fill the cavity in each memory opening.

The materials of the first semiconductor channel layer601and the second semiconductor channel layer602are collectively referred to as a semiconductor channel material. In other words, the semiconductor channel material is a set of all semiconductor material in the first semiconductor channel layer601and the second semiconductor channel layer602.

Referring toFIG.29F, in case the memory cavity49′ in each memory opening is not completely filled by the second semiconductor channel layer602, a dielectric core layer62L can be deposited in the memory cavity49′ to fill any remaining portion of the memory cavity49′ within each memory opening. The dielectric core layer62L includes a dielectric material such as silicon oxide or organosilicate glass. The dielectric core layer62L can be deposited by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD), or by a self-planarizing deposition process such as spin coating.

Referring toFIG.29G, the horizontal portion of the dielectric core layer62L can be removed, for example, by a recess etch from above the top surface of the insulating cap layer70. The dielectric core layer62L can be vertically recessed until top surfaces of remaining portions of the dielectric core layer62L are recessed below the horizontal plane including the top surface of the insulating cap layer70. Each remaining portion of the dielectric core layer62L constitutes a dielectric core62.

Referring toFIG.29H, a doped semiconductor material having a doping of a second conductivity type can be deposited to form a recess region overlying the dielectric core62. The second conductivity type that is the opposite of the first conductivity type. For example, if the first conductivity type is p-type, the second conductivity type is n-type, and vice versa. The dopant concentration in the doped semiconductor material can be in a range from 5.0×1018/cm3to 2.0×1021/cm3, although lesser and greater dopant concentrations can also be employed. The doped semiconductor material can be, for example, doped polysilicon.

Excess portions of the deposited semiconductor material and horizontal portions of the second semiconductor channel layer602can be removed from above the top surface of the insulating cap layer70, for example, by chemical mechanical planarization (CMP). Each remaining portion of the doped semiconductor material having a doping of the second conductivity type constitutes a drain region63. Each remaining portion of the second semiconductor channel layer602can be located entirety within a memory opening49. Each adjoining pair of a first semiconductor channel layer601(if present) and a second semiconductor channel layer602can collectively form a vertical semiconductor channel60through which electrical current can flow when a vertical NAND device including the vertical semiconductor channel60is turned on. A tunneling dielectric layer56is surrounded by a charge storage material layer154L, and laterally surrounds a portion of the vertical semiconductor channel60. The semiconductor liner151L laterally surrounds and contacts the charge storage material layer154L. Each adjoining set of a semiconductor liner151L, a charge storage material layer154L, and a tunneling dielectric layer56collectively constitute a memory film50.

Each combination of a memory film50and a vertical semiconductor channel60within a memory opening49constitutes a memory stack structure55. Each combination of a pedestal channel portion11(if present), a memory stack structure55, a dielectric core62, and a drain region63within a memory opening49is herein referred to as a memory opening fill structure58.

Referring toFIG.30, the second exemplary structure is illustrated after formation of memory opening fill structures58and support pillar structure20within the memory openings49and the support openings19, respectively. An instance of a memory opening fill structure58can be formed within each memory opening49. An instance of the support pillar structure20can be formed within each support opening19.

Each memory stack structure55includes a vertical semiconductor channel60, which may comprise multiple semiconductor channel layers (601,602) or a single semiconductor channel layer602, and a memory film50. The memory film50may comprise a tunneling dielectric layer56laterally surrounding the vertical semiconductor channel60and a vertical stack of charge storage regions laterally surrounding the tunneling dielectric layer56(as embodied as charge storage material layer154L) and an optional semiconductor liner151L. While the present disclosure is described employing the illustrated configuration for the memory stack structure, the methods of the present disclosure can be applied to alternative memory stack structures including different layer stacks or structures for the memory film50and/or for the vertical semiconductor channel60.

Referring toFIGS.31A and31B, a contact-level dielectric layer73can be formed over the alternating stack (31,41) of disposable material layer31and silicon nitride layers41, and over the memory stack structures55and the support pillar structures20. The contact-level dielectric layer73includes a dielectric material that is different from the dielectric material of the silicon nitride layers41. For example, the contact-level dielectric layer73can include carbon-doped silicon oxide (i.e., silicon oxycarbide). The contact-level dielectric layer73can have a thickness in a range from 50 nm to 500 nm, although lesser and greater thicknesses can also be employed.

A photoresist layer (not shown) can be applied over the contact-level dielectric layer73, and is lithographically patterned to form openings in areas between clusters of memory stack structures55. The pattern in the photoresist layer can be transferred through the contact-level dielectric layer73, the alternating stack (31,41) and/or the retro-stepped dielectric material portion65employing an anisotropic etch to form backside trenches79, which vertically extend from the top surface of the contact-level dielectric layer73at least to the top surface of the substrate (9,10), and laterally extend through the memory array region100and the contact region300.

In one embodiment, the backside trenches79can laterally extend along a first horizontal direction hd1(e.g., word line direction) and can be laterally spaced apart from each other along a second horizontal direction hd2(e.g., bit line direction) that is perpendicular to the first horizontal direction hd1. The memory stack structures55can be arranged in rows that extend along the first horizontal direction hd1. The drain select level isolation structures72can laterally extend along the first horizontal direction hd1. Each backside trench79can have a uniform width that is invariant along the lengthwise direction (i.e., along the first horizontal direction hd1). Each drain select level isolation structure72can have a uniform vertical cross-sectional profile along vertical planes that are perpendicular to the first horizontal direction hd1that is invariant with translation along the first horizontal direction hd1. Multiple rows of memory stack structures55can be located between a neighboring pair of a backside trench79and a drain select level isolation structure72, or between a neighboring pair of drain select level isolation structures72. In one embodiment, the backside trenches79can include a source contact opening in which a source contact via structure can be subsequently formed. The photoresist layer can be removed, for example, by ashing.

An optional source region61can be formed at a surface portion of the upper substrate semiconductor layer10under each backside trench79by implantation of electrical dopants into physically exposed surface portions of the upper substrate semiconductor layer10. Each source region61is formed in a surface portion of the substrate (9,10) that underlies a respective backside trench79. An upper portion of the upper substrate semiconductor layer10that extends between the source region61and the plurality of pedestal channel portions11constitutes a horizontal semiconductor channel59for a plurality of field effect transistors. The horizontal semiconductor channel59is connected to multiple vertical semiconductor channels60through respective pedestal channel portions11. The horizontal semiconductor channel59contacts the source region61and the plurality of pedestal channel portions11. Semiconductor channels (59,11,60) extend between each source region61and a respective set of drain regions63. The semiconductor channels (59,11,60) include the vertical semiconductor channels60of the memory stack structures55. Alternatively, a horizontal direct strap contact may be formed instead of the source region61as will be described below with respect to the third embodiment.

Referring toFIGS.32and33A, laterally-extending cavities33can be formed by removal of the disposable material layers31selective to the silicon nitride layers41. An isotropic etch process can be employed to remove the disposable material layers31selective to the silicon nitride layers41. In case the disposable material layers31include undoped silicate glass, a doped silicate glass, or organosilicate glass, a wet etch process employing hydrofluoric acid may be employed. In this case, the retro-stepped dielectric material portion64and the contact-level dielectric layer73can include carbon doped silicate glass to minimize collateral etching. In case the disposable material layers31include a silicon-germanium alloy, an etchant employing a mixture of dilute hydrofluoric acid and hydrogen peroxide may be employed for the isotropic etch process. Generally, the laterally-extending cavities33can be formed by removing the disposable material layers31selective to the silicon nitride layers41and the memory opening fill structures58.

Referring toFIG.33B, an oxidation process can be performed to oxidize portions of the semiconductor liner151L within each memory opening fill structure58that are physically exposed to the laterally-extending cavities33. Portions of the semiconductor liners151L that are proximal to the laterally-extending cavities33are oxidized to form annular semiconductor oxide portions251, which may be annular silicon oxide portions. A vertical stack of annular semiconductor oxide portions251can be formed in each memory opening fill structure58by oxidation of the physically exposed portions of the semiconductor liners151L. A semiconductor oxide liner253can be formed by oxidation of physically exposed surface portions of the upper substrate semiconductor layer10and the pedestal channel portions11. Each semiconductor liner151L can be converted into a vertical stack of annular semiconductor oxide portions251and a vertical stack of semiconductor portions151. The duration of the oxidation process that forms the vertical stacks of annular semiconductor oxide portions251can be selected such that each vertical stack of annular semiconductor oxide portions251contacts a respective charge storage material layer154L.

Referring toFIG.33C, a selective isotropic etch process can be performed to etch the annular semiconductor oxide portions251selective to the materials of the silicon nitride layers41, the charges storage material layers154L, and the vertical stacks of semiconductor portions151. For example, a wet etch process employing dilute hydrofluoric acid can be performed to remove the annular semiconductor oxide portions251. A cylindrical surface segment of an outer sidewall of a charge storage material layer154L can be physically exposed at each level of the laterally-extending cavities33. Tapered and/or concave surfaces of the semiconductor portions151can be physically exposed to the laterally-extending cavities33. Each laterally-extending cavity33can have planar portion having a uniform height and vertically-protruding annular portions that laterally surround a respective one of the memory opening fill structures58. The vertically-protruding annular portions can have a greater height than the planar portion, and can be vertically bounded by tapered and/or concave surfaces of the semiconductor portions151. Thus, referring toFIGS.33B and33C, each semiconductor liner151L can be divided into a vertical stack of semiconductor portions151by removing portions of the semiconductor liners151L from around the laterally-extending cavities33, for example, by oxidation and removal of portions of the oxidized semiconductor liner151L that are proximal to the laterally-extending cavities33.

Referring toFIG.33D, an oxidation process can be performed to oxidize proximal segments of the charge storage material layer154L, proximal segments of the vertical stack of semiconductor portions151, and proximal portions of the silicon nitride layers41. The oxidation process may include a radical oxidation process in which atomic oxygen radicals are employed to provide a higher oxidation rate relative to the oxidation rates of wet or dry thermal oxidation processes. Exemplary radical oxidation processes include in-situ steam generation (ISSG) oxidation, ozone oxidation, and plasma oxidation. For example, the in-situ steam generation oxidation process utilizes oxygen and hydroxyl radicals generated through chemical reactions of hydrogen and oxygen. The in-situ steam generation oxidation process can be performed at low pressures to achieve a sufficiently long radical lifetime. A high volume of oxygen and hydrogen can be employed to reduce the chemical residence time. The reactants can be heated at the physically exposed surfaces of the charge storage material layer154L, the vertical stack of semiconductor portions151, and the silicon nitride layers41to convert surface portions of the charge storage material layer154L, the vertical stack of semiconductor portions151, and the silicon nitride layers41into a semiconductor oxide material, such as silicon oxide. The silicon nitride liner22is oxidized at the same time. This oxidation helps prevent or reduce etching of the oxidized silicon nitride liner22during a subsequent phosphoric acid etching step.

The oxidation process converts surface portions of the silicon nitride layers41into silicon oxide portions that are incorporated into insulating layers132. In one embodiment, the charge storage material layers154L comprise, and/or consists essentially of, silicon nitride, the oxidation process can convert physically exposed portions of the charge storage material layers154L into silicon oxide portions that are incorporated into insulating layers132. The unoxidized portion of each charge storage material layer154L constitutes a vertical stack of charge storage elements (e.g., discrete, vertically separated silicon nitride segments)154. In one embodiment, surface regions of the vertical stacks of semiconductor portions151that are physically exposed to the laterally-extending cavities33are oxidized during the oxidation process, and are incorporated into the insulating layers132.

An insulating layer132including silicon oxide can be formed within each laterally-extending cavity33. A subset of the insulating layers132is formed within laterally-extending cavities33that adjoin a pair of charge storage elements154. Each such insulating layer132comprises a respective lateral protrusion portion LPP incorporating an oxidized portion of a respective one of the charge storage material layers154L, and a respective upper lobe portion ULP and a respective lower lobe portion LLP that incorporate a respective oxidized surface region of the vertical stacks of semiconductor portions151.

Further, each insulating layer132that is formed between a vertically neighboring pair of silicon nitride layers41comprises an upper horizontally-extending portion formed by oxidation of an upper silicon nitride layer41within the vertically neighboring pair and a lower horizontally-extending portion formed by oxidation of a lower silicon nitride layer41within the vertically neighboring pair. In one embodiment, the oxidation process can be continued until the upper horizontally-extending portion adjoins the lower horizontally-extending portion at a horizontal seam132S.

Generally, insulating layers132comprising silicon oxide can be formed by performing an oxidation process that oxidizes surface portions of the silicon nitride layers41and portions of the charge storage material layers154L that are proximal to the laterally-extending cavities33. Remaining portions of the charge storage material layers154L form a vertical stack of discrete charge storage elements154in each of the memory opening fill structures58. In one embodiment, each memory film50comprises a tunneling dielectric layer56and a vertical stack of discrete charge storage elements154that are vertically spaced apart from each other by lateral protrusion portions LPP of a subset of the insulating layers132.

For the subset of the insulating layers132that are formed above the horizontal plane including the top surfaces of the pedestal channel portions11, each of the subset of the insulating layers132comprises an upper lobe portion ULP that contacts an outer sidewall of one of the discrete charge storage elements154, and a lower lobe portion LLP that contacts an outer sidewall of another of the discrete charge storage elements154. In one embodiment, each of the subset of the insulating layers132comprises a uniform thickness region having a respective uniform thickness and adjoined to the upper lobe portion ULP and to the lower lobe portion LLP, the upper lobe portion ULP protrudes upward above a horizontal plane including a top surface of the uniform thickness region, and the lower lobe portion LLP protrudes downward below a horizontal plane including a bottom surface of the uniform thickness region.

In one embodiment, the vertical stack of discrete charge storage elements154comprises, and/or consists essentially of, silicon nitride, the lateral protrusion portion LPP of each of the subset of the insulating layers132comprises silicon oxynitride at interfacial regions near the vertical stack of discrete charge storage elements154such that atomic concentration of nitrogen atoms decreases with a distance from the interfaces with the vertical stack of discrete charge storage elements154.

In one embodiment, the upper lobe portions ULP and the lower lobe portions LLP of the subset of insulating layers132can be formed by oxidation of a nitrogen-free semiconductor material (i.e., the material of the semiconductor liner151L), and can be free of nitrogen atoms or comprises nitrogen atoms at an average atomic concentration less than 10% of an average atomic concentration of nitrogen atomic within the lateral protrusion portions LPP. For example, the atomic concentration of nitrogen atoms in the upper lobe portions ULP and the lower lobe portions LLP of the subset of insulating layers132may be less than 1 part per million in atomic concentration.

In one embodiment, the insulating layers132comprise a respective horizontal seam132S that does not contact any of the memory opening fill structures58. In one embodiment, the insulating layers132comprise silicon oxide that is free of carbon atoms or comprise carbon atoms at an atomic concentration less than 1 part per million.

In one embodiment, each of the subset of the insulating layers132comprises silicon oxide and has a uniform thickness region having a respective uniform thickness, an upper surface portion of the uniform thickness region is doped nitrogen atoms such that atomic concentration of nitrogen atoms increases with a vertical distance from the substrate (9,10) (due to the interfacial atomic concentration gradient of nitrogen atoms at an interface with unoxidized portions of an overlying silicon nitride layer42), and a lower surface portion of the uniform thickness region is doped with nitrogen atomic such that atomic concentration of nitrogen atoms decreases with the vertical distance from the substrate (9,10) (due to the interfacial atomic concentration gradient of nitrogen atoms at an interface with unoxidized portions of an underlying silicon nitride layer42).

Within each memory opening fill structure58, the tunneling dielectric layer56has a straight outer sidewall that vertically extends through levels of the subset of the insulating layers132, the lateral protrusion portions LPP of a subset of the insulating layers132contacts the straight outer sidewall of the tunneling dielectric layer56. The lateral protruding portions LPP of the subset of the insulating layers132can have convex surfaces that contact a respective concave surface of the vertical stack of discrete charge storage elements154.

Referring toFIG.34, an etch process (such as an anisotropic etch process or an isotropic etch process) can be performed to remove silicon oxide portions that are located at peripheral portions of the backside trenches79. Sidewalls of the silicon nitride layers41can be physically exposed around each backside trench70.

Referring toFIGS.35and36A, backside recesses43can be formed by removing the remaining portions of the silicon nitride layers41selective to the insulating layers132. An etchant that selectively etches the second material of the silicon nitride layers41with respect to the silicon oxide material of the insulating layers132can be introduced into the backside trenches79, for example, employing an etch process. Backside recesses43are formed in volumes from which the silicon nitride layers41are removed. The removal of the second material of the silicon nitride layers41can be selective to the silicon oxide material of the insulating layers132, the material of the retro-stepped dielectric material portion65, the semiconductor material of the upper substrate semiconductor layer10, the material of the semiconductor portions151and the material of the oxidized silicon nitride liner22.

In one embodiment, the etch process can be a wet etch process in which the second exemplary structure is immersed within a wet etch tank including phosphoric acid, which etches silicon nitride selective to silicon oxide, silicon, and various other materials employed in the art. The support pillar structure20, the retro-stepped dielectric material portion64, and the memory opening fill structures58provide structural support while the backside recesses43are present within volumes previously occupied by the silicon nitride layers41. Thus, the oxidation of the silicon nitride liner22at the step ofFIG.33Dhelps prevent or reduce etching of the oxidized silicon nitride liner22during the above described phosphoric acid etching step.

Each backside recess43can be a laterally extending cavity having a lateral dimension that is greater than the vertical extent of the cavity. In other words, the lateral dimension of each backside recess43can be greater than the height of the backside recess43. A plurality of backside recesses43can be formed in the volumes from which the second material of the silicon nitride layers41is removed. The memory openings in which the memory opening fill structures58are formed are herein referred to as front side openings or front side cavities in contrast with the backside recesses43. In one embodiment, the memory array region100comprises an array of monolithic three-dimensional NAND strings having a plurality of device levels disposed above the substrate (9,10). In this case, each backside recess43can define a space for receiving a respective word line of the array of monolithic three-dimensional NAND strings. Each of the plurality of backside recesses43can extend substantially parallel to the top surface of the substrate (9,10). A backside recess43can be vertically bounded by a top surface of an underlying insulating layer132and a bottom surface of an overlying insulating layer132.

Referring toFIG.36B, an oxidation process (such as a thermal oxidation process or a plasma oxidation process) can be performed to oxide physically exposed portions of the semiconductor portions151and to oxidize physically exposed surface portions of the optional pedestal channel portions11. The oxidation process converts a surface portion of each pedestal channel portion11into a tubular dielectric spacer116, and converts physically exposed segments of the semiconductor portions151into a vertical stack of discrete semiconductor oxide portions152, such as silicon oxide portions. Within each memory opening fill structure58, a remaining segment of the semiconductor portions151may include an annular horizontal semiconductor portion253that contacts an annular top surface of a pedestal channel portion11. Generally, a vertical stack of discrete semiconductor oxide portions152can be formed by oxidizing a vertical stack of semiconductor portions151within each memory opening fill structure58.

In one embodiment, each tubular dielectric spacer116can be topologically homeomorphic to a torus, i.e., generally ring-shaped. As used herein, an element is topologically homeomorphic to a torus if the shape of the element can be continuously stretched without destroying a hole or forming a new hole into the shape of a torus. The tubular dielectric spacers116include a dielectric material that includes the same semiconductor element as the pedestal channel portions11and additionally includes oxygen atoms. The lateral thickness of the semiconductor oxide portions152may be in a range from 2 nm to 12 nm, such as from 4 nm to 8 nm, although lesser and greater thicknesses may also be employed.

Referring toFIG.36C, a backside blocking dielectric layer44can be optionally formed. The backside blocking dielectric layer44, if present, comprises a dielectric material that functions as a control gate dielectric for the control gates to be subsequently formed in the backside recesses43. The backside blocking dielectric layer44can be formed on the physically exposed surface of the semiconductor oxide portions152and the insulating layers132. In one embodiment, the backside blocking dielectric layer44can be formed by a conformal deposition process such as atomic layer deposition (ALD). The backside blocking dielectric layer44can consist essentially of aluminum oxide. The thickness of the backside blocking dielectric layer44can be in a range from 1 nm to 15 nm, such as 2 to 6 nm, although lesser and greater thicknesses can also be employed.

The dielectric material of the backside blocking dielectric layer44can comprise, and/or can consist essentially of, a dielectric metal oxide such as aluminum oxide, a dielectric oxide of at least one transition metal element, a dielectric oxide of at least one Lanthanide element, a dielectric oxide of a combination of aluminum, at least one transition metal element, and/or at least one Lanthanide element. Alternatively or additionally, the backside blocking dielectric layer44can include a silicon oxide layer. The backside blocking dielectric layer44can be deposited by a conformal deposition method such as chemical vapor deposition or atomic layer deposition. A backside cavity is present within the portion of each backside trench79that is not filled with the backside blocking dielectric layer44.

Referring toFIGS.36D,37A and37B, a metallic barrier layer46A can be deposited in the backside recesses43. The metallic barrier layer46A includes an electrically conductive metallic material that can function as a diffusion barrier layer and/or adhesion promotion layer for a metallic fill material to be subsequently deposited. The metallic barrier layer46A can include a conductive metallic nitride material such as TiN, TaN, WN, or a stack thereof, or can include a conductive metallic carbide material such as TiC, TaC, WC, or a stack thereof. In one embodiment, the metallic barrier layer46A can be deposited by a conformal deposition process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). The thickness of the metallic barrier layer46A can be in a range from 2 nm to 8 nm, such as from 3 nm to 6 nm, although lesser and greater thicknesses can also be employed. In one embodiment, the metallic barrier layer46A can consist essentially of a conductive metal nitride such as TiN.

A metal fill material is deposited in the plurality of backside recesses43, on the sidewalls of the at least one the backside trench79, and over the top surface of the contact level dielectric layer73to form a metallic fill material layer46B. The metallic fill material can be deposited by a conformal deposition method, which can be, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), electroless plating, electroplating, or a combination thereof. In one embodiment, the metallic fill material layer46B can consist essentially of at least one elemental metal. The at least one elemental metal of the metallic fill material layer46B can be selected, for example, from tungsten, cobalt, ruthenium, titanium, and tantalum. In one embodiment, the metallic fill material layer46B can consist essentially of a single elemental metal. In one embodiment, the metallic fill material layer46B can be deposited employing a fluorine-containing precursor gas such as WF6. In one embodiment, the metallic fill material layer46B can be a tungsten layer including a residual level of fluorine atoms as impurities. The metallic fill material layer46B is spaced from the insulating layers132and the memory stack structures55by the metallic barrier layer46A, which is a metallic barrier layer that blocks diffusion of fluorine atoms therethrough.

A plurality of electrically conductive layers46can be formed in the plurality of backside recesses43, and a continuous metallic material layer can be formed on the sidewalls of each backside trench79and over the contact level dielectric layer73. Each electrically conductive layer46includes a portion of the metallic barrier layer46A and a portion of the metallic fill material layer46B that are located between a vertically neighboring pair of dielectric material layers such as a pair of insulating layers132. The continuous metallic material layer includes a continuous portion of the metallic barrier layer46A and a continuous portion of the metallic fill material layer46B that are located in the backside trenches79or above the contact level dielectric layer73.

Each silicon nitride layer41can be replaced with an electrically conductive layer46. A backside cavity is present in the portion of each backside trench79that is not filled with the backside blocking dielectric layer44and the continuous metallic material layer. An optional tubular dielectric spacer116laterally surrounds the optional pedestal channel portion11. A bottommost electrically conductive layer46laterally surrounds each tubular dielectric spacer116upon formation of the electrically conductive layers46.

The deposited metallic material of the continuous electrically conductive material layer is etched back from the sidewalls of each backside trench79and from above the contact level dielectric layer73, for example, by an isotropic wet etch, an anisotropic dry etch, or a combination thereof. Each remaining portion of the deposited metallic material in the backside recesses43constitutes an electrically conductive layer46. Each electrically conductive layer46can be a conductive line structure. Thus, the silicon nitride layers41are replaced with the electrically conductive layers46.

Each electrically conductive layer46can function as a combination of a plurality of control gate electrodes located at a same level and a word line electrically interconnecting, i.e., electrically shorting, the plurality of control gate electrodes located at the same level. The plurality of control gate electrodes within each electrically conductive layer46are the control gate electrodes for the vertical memory devices including the memory stack structures55. In other words, each electrically conductive layer46can be a word line that functions as a common control gate electrode for the plurality of vertical memory devices.

In one embodiment, the removal of the continuous electrically conductive material layer can be selective to the material of the backside blocking dielectric layer44. In this case, a horizontal portion of the backside blocking dielectric layer44can be present at the bottom of each backside trench79. In another embodiment, the removal of the continuous electrically conductive material layer may not be selective to the material of the backside blocking dielectric layer44or, the backside blocking dielectric layer44may not be employed.

In one embodiment, each of the memory opening fill structures58comprise a vertical stack of semiconductor oxide portions152that contact an outer sidewall of a respective one of the discrete charge storage elements154. The upper lobe portions ULP and the lower lobe portions LLP of the insulating layers132contact a respective one of the semiconductor oxide portions152. Backside blocking dielectric layers44can be located between, and can contact, a respective one of the electrically conductive layers46and a respective one of the semiconductor oxide portions152.

Referring toFIG.38, an insulating material layer can be formed in the backside trenches79and over the contact level dielectric layer73by a conformal deposition process. Exemplary conformal deposition processes include, but are not limited to, chemical vapor deposition and atomic layer deposition. The insulating material layer includes an insulating material such as silicon oxide, silicon nitride, a dielectric metal oxide, an organosilicate glass, or a combination thereof. In one embodiment, the insulating material layer can include silicon oxide. The insulating material layer can be formed, for example, by low pressure chemical vapor deposition (LPCVD) or atomic layer deposition (ALD). The thickness of the insulating material layer can be in a range from 1.5 nm to 60 nm, although lesser and greater thicknesses can also be employed.

An anisotropic etch is performed to remove horizontal portions of the insulating material layer from above the contact level dielectric layer73and at the bottom of each backside trench79. Each remaining portion of the insulating material layer constitutes an insulating spacer74. A backside cavity is present within a volume surrounded by each insulating spacer74. A top surface of a source region61can be physically exposed at the bottom of each backside trench79.

A backside contact via structure76can be formed within each backside cavity. Each contact via structure76can fill a respective cavity. The contact via structures76can be formed by depositing at least one conductive material in the remaining unfilled volume (i.e., the backside cavity) of the backside trench79. For example, the at least one conductive material can include a conductive liner76A and a conductive fill material portion76B. The conductive liner76A can include a conductive metallic liner such as TiN, TaN, WN, TiC, TaC, WC, an alloy thereof, or a stack thereof. The thickness of the conductive liner76A can be in a range from 3 nm to 30 nm, although lesser and greater thicknesses can also be employed. The conductive fill material portion76B can include a metal or a metallic alloy. For example, the conductive fill material portion76B can include W, Cu, Al, Co, Ru, Ni, an alloy thereof, or a stack thereof.

The at least one conductive material can be planarized employing the contact level dielectric layer73overlying the alternating stack (32,46) as a stopping layer. If chemical mechanical planarization (CMP) process is employed, the contact level dielectric layer73can be employed as a CMP stopping layer. Each remaining continuous portion of the at least one conductive material in the backside trenches79constitutes a backside contact via structure76.

The backside contact via structure76extends through the alternating stack (32,46), and contacts a top surface of the source region61. If a backside blocking dielectric layer44is employed, the backside contact via structure76can contact a sidewall of the backside blocking dielectric layer44.

Alternatively, at least one dielectric material, such as silicon oxide, may be conformally deposited in the backside trenches79by a conformal deposition process. Each portion of the deposited dielectric material that fills a backside trench79constitutes a backside trench fill structure. In this case, each backside trench fill structure may fill the entire volume of a backside trench79and may consist essentially of at least one dielectric material. In the third embodiment described below, the source region61may be omitted, and a lateral source contact structure (e.g., direct strap contact) may contact an side of the lower portion of the semiconductor channel60.

Referring toFIGS.39A and39B, additional contact via structures (88,86,8P) can be formed through the contact level dielectric layer73, and optionally through the retro-stepped dielectric material portion65. For example, drain contact via structures88can be formed through the contact level dielectric layer73on each drain region63. Word line contact via structures86can be formed on the electrically conductive layers46through the contact level dielectric layer73, and through the retro-stepped dielectric material portion65. Peripheral device contact via structures8P can be formed through the retro-stepped dielectric material portion65directly on respective nodes of the peripheral devices.

The method employed to form the second exemplary structure can be applied to other semiconductor structures such as a third semiconductor structure of the third embodiment illustrated inFIG.40. In the third exemplary structure, semiconductor devices700may be formed over an entire area of a semiconductor die, and metal interconnect structures780embedded within interconnect-level dielectric material layers760can be formed over the semiconductor devices.

Source-level material layers110including at least source contact layer can be formed over the interconnect-level dielectric material layers, and at least one alternating stack of insulating layers132and electrically conductive layers46can be formed above the source-level material layers110. Intermediate-level dielectric material layers such as a first insulating cap layer170, an inter-level dielectric material layer180, and a second insulating cap layer270can be formed as needed. A first retro-stepped dielectric material portion164and a second retro-stepped dielectric material portion264may be formed, which can include the same type of dielectric material as the retro-stepped dielectric material portion64described above. Dielectric pillar portions584may be optionally formed through the alternating stacks of insulating layers132and electrically conductive layers46. A via-level dielectric layer280can be formed above the contact-level dielectric layer73, and various contact via structures (88,86) can be formed. Through-memory-level connection via structures488can be formed through the retro-stepped dielectric material potions (164,264) or through the dielectric pillar structures584. A line-level dielectric layer290can be formed above the via-level dielectric layer280, and metal line structures (96,98) can be formed in the line-level dielectric layer290. In one embodiment, the metal line structures (96,98) can include bit lines98that contact a respective one of the drain contact via structures88and interconnection metal lines96that contact the word line contact via structures86or the through-memory-level connection via structures488.

In the third embodiment, a sacrificial source layer is formed below the lower most disposable material layer31and the pedestal channel portions and the source regions61are omitted11. Instead, the backside trenches79are extend down by etching to expose the sacrificial source layer at the step shown inFIG.34. The sacrificial source layer is then removed through the backside trenches79by selective etching to form a source cavity. The memory film50exposed in the source cavity is removed by selective etching to expose a sidewall of the vertical semiconductor channel60. A doped semiconductor direct strap contact is then formed in the source cavity in contact with the exposed sidewall of the vertical semiconductor channel60.

Referring to all drawings and according to various embodiments of the present disclosure, a three-dimensional memory device is provided, which comprises: an alternating stack of insulating layers132and electrically conductive layers46located over a substrate (9,10); memory openings49vertically extending through the alternating stack (132,46); and memory opening fill structures58located in the memory openings49, wherein: each of the memory opening fill structures58comprises a vertical semiconductor channel60and a memory film50; and the memory film50comprises a tunneling dielectric layer56and a vertical stack of discrete charge storage elements154that are vertically spaced apart from each other by lateral protrusion portions LPP of a subset of the insulating layers132.