Voltage keeping scheme for low-leakage memory devices

The present invention facilitates memory device operation by mitigating power consumption during suspend modes of operation, also referred to as sleep/data retention modes. This is accomplished by employing one or more gate-sinking voltage keeper components that operate as leakage current sinks during the suspend mode of operation instead of gate-sourcing voltage keeper components that operate as leakage current sources during the suspend mode of operation, on a circuit node whose voltage level is maintained by a sinking voltage regulator. As a result, less leakage current is required to be dissipated/sunk by a voltage regulator and/or other circuit paths or components of the memory device. Thus, relatively less power is consumed.

FIELD OF THE INVENTION

The present invention relates generally to the field of semiconductor devices, and more particularly, to a low voltage maintenance scheme for low-leakage memory devices.

BACKGROUND OF THE INVENTION

Portable electronic devices, including cellular phones, personal digital assistants, digital audio players, digital cameras, and the like, increasingly demand higher performance, smaller sizes, and lower power/energy consumption. As a result, circuit components and devices that comprise these portable electronic devices also need higher performance, smaller sizes, and lower power/energy consumption.

One component typically associated with portable electronic devices is a static random access memory (SRAM), which is a memory device that can store or maintain information with little or no power. This type of memory contrasts with dynamic random access memory (DRAM), commonly used in desktop computer systems, that loses stored information without frequent refresh cycles.

Wireless devices can be especially prone to low energy consumption concerns. Many next generation wireless systems employ combined RF-analog-digital systems on a single chip in order to reduce power consumption. Wireless devices, as well as other electronic devices, usually include a suspend/standby mode in which a device is not completely turned off, but is in a “sleep/data retention state” or a low power consumption data retention state. It is important that the memory devices maintain the integrity of stored information during these standby modes.

One problem encountered in SRAM devices is that of leakage during low power or standby/suspend modes. SRAM devices can employ one or more transistors as “voltage keepers” that hold selected control and data access lines (e.g., word line, bit line, and the like) as well as array VSS (VSSA) lines to desired voltage levels during suspend mode, in order to reduce array leakage. However, these voltage keeper transistors themselves can add leakage during suspend mode due to direct gate tunneling leakage of the transistors.

SUMMARY OF THE INVENTION

The present invention facilitates memory device operation by mitigating power consumption during suspend modes, also referred to as sleep/data retention modes. This is accomplished by employing one or more gate-sinking voltage keeper components that operate as leakage current sinks during suspend mode instead of gate-sourcing voltage keeper components that operate as leakage current sources, on a circuit node whose voltage level is maintained by a sinking voltage regulator. As a result, less current is required to be dissipated/sunk by a voltage regulator and/or other circuit paths or components of the memory device. Thus, relatively less power is consumed.

A gate-sinking component is referred to herein as a component whose gate tunneling leakage is of a sinking type (i.e., flowing out of the control gate terminal) during the suspend mode. A gate-sourcing component, on the other hand, is referred to herein as a component whose gate tunneling leakage is of a sourcing type (i.e., flowing into the control gate terminal) during the suspend mode. A sinking voltage regulator is referred to herein as a voltage regulator whose output voltage is clamped to a reference voltage level by sinking away the current (the net of all other current) flowing into the output node. A sourcing voltage regulator, on the other hand, is referred to herein as a voltage regulator whose output voltage is clamped to a reference voltage level by sourcing with the current (the net of all other current) flowing out of the output node. A sinking voltage is referred to herein as a voltage generated by a sinking voltage regulator. A sourcing voltage, on the other hand, is referred to herein as a voltage generated by a sourcing voltage regulator.

PMOS based gate-sinking voltage keeper components are employed in place of NMOS based gate-sourcing voltage keeper components on a circuit node whose voltage level is maintained by a sinking voltage regulator. NMOS based gate-sourcing voltage keeper components tend to generate/source leakage current during the suspend mode as a result of gate tunneling leakage current. PMOS based gate-sinking voltage keeper components, on the other hand, operate as leakage current sinks during the suspend mode and thus sink just a portion of leakage current generated by an associated memory array, and hence do not add leakage.

DETAILED DESCRIPTION OF THE INVENTION

The present invention will now be described with respect to the accompanying drawings in which like numbered elements represent like parts. The figures provided herewith and the accompanying description of the figures are merely provided for illustrative purposes. One of ordinary skill in the art should realize, based on the instant description, other implementations and methods for fabricating the devices and structures illustrated in the figures and in the following description.

The present invention provides systems and methods that can reduce power consumption for memory devices when operating in a suspend or sleep/data retention mode. Power reduction is accomplished by employing one or more gate-sinking components that operate as leakage current sinks instead of gate-sourcing components that operate as leakage current sources during the suspend mode, on a circuit node whose voltage level is maintained by a sinking voltage regulator. Additional power reduction may be accomplished by employing one or more gate-sourcing components that operate as leakage current sources instead of gate-sinking components that operate as leakage current sinks during the suspend mode, on a circuit node whose voltage level is maintained by a sourcing voltage regulator. As a result, a total amount of current generated by a memory device in suspend mode can be reduced and, therefore, power consumption of the memory device can be reduced.

A gate-sinking component is referred to herein as a component whose gate tunneling leakage is of a sinking type (i.e., flowing out of the control gate terminal) during the suspend mode. A gate-sourcing component, on the other hand, is referred to herein as a component whose gate tunneling leakage is of a sourcing type (i.e., flowing into the control gate terminal) during the suspend mode. A sinking voltage regulator is referred to herein as a voltage regulator whose output voltage is clamped to a reference voltage level by sinking away the current (the net of all other current) flowing into the output node. A sourcing voltage regulator, on the other hand, is referred to herein as a voltage regulator whose output voltage is clamped to a reference voltage level by sourcing with the current (the net of all other current) flowing out of the output node. A sinking voltage is referred to herein as a voltage generated by a sinking voltage regulator. A sourcing voltage, on the other hand, is referred to herein as a voltage generated by a sourcing voltage regulator.

Generally, a memory array is supplied with a retention voltage, which is smaller than the normal operation voltage, across the array in order to maintain data during the suspend mode. As a result, an amount of leakage current is generated by the memory array. The retention voltage is typically achieved by raising an array VSS (VSSA) input to a sinking suspend voltage level and optionally lowering an array VDD (VDDA) input to a sourcing suspend voltage level. To further reduce the array leakage, either or both of the word line (WL) and the bit line (BL) can be biased at the sinking suspend voltage as well during suspend mode. NMOS based gate-sourcing voltage keeper components operate as leakage current sources during the suspend mode and thus add to the leakage current generated by the memory array. Instead, the present invention employs PMOS based gate-sinking voltage keeper components that operate as leakage current sinks during the suspend mode and thus reduce the amount of leakage current present.

Beginning withFIG. 1, a state diagram100depicting various operational modes for a memory device in accordance with an aspect of the present invention is shown. The diagram100illustrates three basic states of operation, an off mode102, a normal operation mode104, and a suspend mode106.

The off mode102of operation is simply a state in which no power is supplied to the memory device nor consumed by the memory device. If the memory device is non-volatile, the device can maintain stored data for a period of time without power. Otherwise, such as in the case of a static random access memory (SRAM), all stored data is erased. The normal mode104of operation is a state in which data is written to and read from the device. In this state, the device is fully powered and active.

The suspend mode106of operation is a reduced power or low power consumption state in which the memory device is neither operational nor off. In the suspend mode106, a reduced amount of power is supplied to the memory device. However, the device can change from suspend mode106to normal operation mode104substantially quicker than can the device change from off mode102to the normal operation mode104. While in the suspend mode106, the device is operable to maintain its data without loss. Additionally, the power consumption of the device in the suspend mode106, although not zero, is substantially less than that of the normal operation mode104.

FIG. 2is a schematic illustrating a portion of a memory device200operable in a suspend mode. The device200is described generally and particularly with regard to suspend mode operation. The memory device200includes row periphery circuitry202, an array component204, and a sinking voltage regulator206.

The row periphery circuitry202facilitates selecting various lines of the array component204, for example, selectively activating word lines. The circuitry202includes a first gate-sourcing voltage keeper component208, comprised of an NMOS transistor, that controllably supplies a sinking suspend voltage during a suspend mode/state of operation. During other modes or states, the first gate-sourcing voltage keeper component208isolates the circuitry202from the sinking suspend voltage. The first gate-sourcing voltage keeper component208is controlled by a signal RET that is generally asserted (high) during a suspend mode and de-asserted (e.g., goes low) otherwise. It is noted that this description generally assumes that an asserted signal activates a device while a de-asserted signal turns such a device off. However, the present invention contemplates variations in which the opposite condition holds, and such variations are contemplated by the present invention.

The array component204comprises a second gate-sourcing voltage keeper component210, a footer switch212, and a memory array214. The memory array214includes inputs for a word line voltage (WL), an array VSS input (VSSA), and an array VDD input (VDDA). The VSSA is biased to a VSS supply voltage and the VDDA is biased to a VDD supply voltage during normal mode operation. During suspend mode, the VSSA is biased to a sinking supply voltage and optionally the VDDA is biased to a sourcing supply voltage. The second gate-sourcing voltage keeper component210, like the first gate-sourcing voltage keeper component208, controllably supplies the sinking suspend voltage during suspend mode/state of operation to the memory array214and also comprises an NMOS transistor. During other modes or states of operation, the second gate-sourcing voltage keeper component210at least partially isolates the memory array214from the sinking suspend voltage. Typically, the second gate-sourcing voltage keeper component210supplies the sinking suspend voltage to the VSSA of the memory array214whereas the first gate-sourcing voltage keeper component208supplies the sinking suspend voltage to the WL's (word lines) of the memory array214. The second gate-sourcing voltage keeper component210is also controlled by the signal RET that is generally asserted during a suspend mode and de-asserted otherwise.

The footer switch212controllably supplies the VSS supply voltage to the VSSA input of the memory array214. The footer switch212comprises an NMOS transistor and is controlled by a signal RETB, which is the complement of the signal RET, such that the signal RETB is de-asserted during the suspend mode and asserted otherwise.

The sinking voltage regulator206generates and supplies the sinking source voltage at least during the suspend mode of operation. The sinking suspend voltage is supplied to the first gate-sourcing voltage keeper component208and the second gate-sourcing voltage keeper component210such that the memory array214can receive the sinking suspend voltage during the suspend mode of operation. Additionally, the sinking voltage regulator206can operate to sink leakage current generated by the memory array214.

In a typical application, the suspend mode requires that the voltage applied to the VDDA input be kept at normal voltage level (e.g., 1.3V) while the voltage applied to the array nwell input (VNWA) be raised to a higher voltage (e.g., 1.8V). The RET signal raises from about 0V to a normal voltage level (e.g., 1.3V) and the RETB signal drops from a normal voltage level to about 0V. The VSSA input and word line are raised to the sinking suspend voltage generated by the sinking voltage regulator206(e.g., about 0.8V). A bit line (BL) typically floats to a voltage level close to the sinking suspend voltage.

During the suspend mode, the memory array214generates an amount of leakage current (i.e., operates as a leakage current source, referencing to the sinking voltage node). The first gate-sourcing voltage keeper component208and the second gate-sourcing voltage keeper component210also generate leakage current during the suspend mode operation by way of sourcing gate leakage into the NMOS transistors. The total leakage current generated by the leakage current sources during the suspend mode of operation is dissipated by one or more leakage current sinks present in the device (e.g., the sinking voltage regulator). This dissipated leakage current translates into undesirable power consumption that can result in shortening battery life, loss of data, excess thermal energy, and the like.

FIG. 3is a schematic diagram illustrating a memory device portion300in accordance with an aspect of the present invention. The device300is described generally and particularly with regard to the suspend mode of operation. The device300consumes relatively less power than the similar memory device200ofFIG. 2because the memory device300employs gate-sinking voltage keeper components that operate as leakage current sinks instead of gate-sourcing voltage keeper components that act as leakage current sources during the suspend mode of operation. The memory device300includes row periphery circuitry302, an array component304, and a voltage regulator306.

The row periphery circuitry302, as with the circuitry202ofFIG. 2, facilitates selecting various control lines of the array component304. The circuitry302includes a first gate-sinking voltage keeper component308, comprised of a PMOS transistor instead of an NMOS transistor that controllably supplies a sinking suspend voltage during the suspend mode of operation. During other modes or states, the first gate-sinking voltage keeper component308isolates the circuitry302from the suspend voltage. The first gate-sinking voltage keeper component308is controlled by a signal RETB that is generally asserted (low signal) during a suspend mode of operation and de-asserted otherwise (high signal), which is opposite the control of the first gate-sourcing voltage keeper component208ofFIG. 2.

The array component304comprises a second gate-sinking voltage keeper component310, a footer switch312, and a memory array314. The memory array314includes inputs for a word line voltage (WL), an array VSS voltage (VSSA), and an array VDD voltage (VDDA). Additionally, the second gate-sinking voltage keeper component310controllably supplies the sinking suspend voltage during the suspend mode of operation to the memory array314and comprises a PMOS transistor. During other modes or states of operation, the second gate-sinking voltage keeper component310at least partially isolates the memory array314from the sinking suspend voltage. Typically, the second gate-sinking voltage keeper component310supplies the sinking suspend voltage to the VSSA input of the memory array314whereas the first gate-sinking voltage keeper component308supplies the suspend voltage to the WL's (word lines) of the memory array314. The second gate-sinking voltage keeper component310is also controlled by the signal RETB that is generally asserted during a suspend mode of operation and de-asserted otherwise.

The footer switch312controllably supplies a VSS voltage to the memory array314, particularly to the VSSA input of the memory array314at least during normal mode. The footer switch312comprises an NMOS transistor and is controlled by the signal RETB and is de-asserted (low) during the suspend mode of operation and asserted otherwise. It is noted that the signal RET, which is the complement of RETB, can be present and employed elsewhere in the device300.

The sinking voltage regulator306generates and supplies the sinking suspend voltage at least during the suspend mode of operation. The sinking suspend voltage is supplied to the first gate-sinking voltage keeper component308and the second gate-sinking voltage keeper component310such that the memory array314can receive the sinking suspend voltage during the suspend mode of operation. Additionally, the sinking voltage regulator306can operate to sink leakage current generated by the memory array314. Furthermore, the sinking voltage regulator306can be a low-dropout voltage regulator (LDO).

In a typical application, the suspend mode of operation requires that the voltage applied to the VDDA input be kept at a normal voltage level (e.g., about 1.0 to 1.3V) while the array nwell supply input (VNWA) be raised to a higher voltage level (e.g., 1.8V). The RET signal raises from about 0V to a normal voltage level (e.g., about 1.0 to 1.3V) and the RETB signal drops from a normal voltage level to about 0V. The VSSA input and word line rise to the sinking suspend voltage generated by the sinking voltage regulator306(e.g., about 0.3 to 0.8V or 0.7 to 0.4 V below the normal mode voltage). A bit line (BL) typically floats to a voltage level close to the suspend voltage. One or more additional gate-sinking voltage keeper components can also be employed that controllably connect bit lines of the memory array314to the sinking suspend voltage regulator306.

The memory array314generates an amount of leakage current (i.e., operates as a leakage current source) during the suspend mode of operation, which is generally due to data retention purposes. The first gate-sinking voltage keeper component308and the second gate-sinking voltage keeper component310, in contrast with the similar gate-sourcing voltage keeper components ofFIG. 2, operate as leakage current sinks instead of sources during the suspend mode of operation by way of sinking gate leakage from the PMOS transistors. Thus, the total leakage current generated is reduced. As a result, the amount of leakage current dissipated can be substantially reduced when compared with the device200ofFIG. 2. Similarly, undesirable power consumption, relative to that by device200ofFIG. 2, can be reduced.

FIG. 4is a block diagram illustrating current leakage for a memory device400during a suspend mode of operation. The diagram illustrates sourcing and sinking of leakage current through the memory device400and its circuit paths, wherein the memory device400employs gate-sinking voltage keeper components that operate as leakage current sources during the suspend mode of operation. As a result, additional and undesirable power is consumed from these voltage keeper components.

The memory device400is comprised of a sinking voltage regulator402, sourcing leakage device/circuit paths404, and sinking leakage device/circuit paths406. The voltage regulator402operates at least during the suspend mode of operation to generate a sinking suspend voltage for raising an array VSS (VSSA) input of a memory array to the sinking suspend voltage. It is appreciated that the sinking voltage regulator402can supply the sinking suspend voltage to more than one memory array and still be in accordance with the present invention.

Sourcing leakage current410is generated by the sourcing leakage device/circuit paths404during the suspend mode of operation. Generally, the leakage current is substantially generated by the memory array, across which is supplied with a retention voltage in order to maintain data during the suspend mode of operation, and one or more gate-sourcing voltage keeper components. However, because NMOS type gate-sourcing voltage keeper components contribute source leakage current, the total source leakage410is larger than merely the array leakage contribution. Sinking leakage current414is generated by the sinking leakage device/circuit paths406during the suspend mode of operation. Generally, the sinking leakage current414is substantially less than the sourcing leakage current410. It is appreciated that the amount of source leakage current and sink leakage current are substantially equal in order to properly balance and control leakage current. Thus, the sinking voltage regulator402sinks extra sourcing leakage current412not sunk by the sinking leakage device/circuit paths406and clamps the sinking suspend voltage to a desired level (e.g., 0.8 V).

Turning now toFIG. 5, another block diagram illustrating leakage current for a memory device500during the suspend mode of operation in accordance with an aspect of the present invention is shown. The diagram illustrates sourcing and sinking of leakage current through the memory device500and its circuit paths, wherein the memory device500employs gate-sinking voltage keeper components that operate as leakage current sinks instead of gate-sourcing voltage keeper components that operate as leakage current sources during the suspend mode of operation. As a result, less power is consumed by the device500than the device400ofFIG. 4.

The memory device500operates in a similar manner to that of the memory device400ofFIG. 4, except that the memory device500employs gate-sinking voltage keeper components that operate as leakage current sinks instead of gate-sourcing voltage keeper components that operate as leakage current sources during the suspend mode of operation. For brevity, some discussion of the memory device500is omitted.

The memory device500is comprised of a sinking voltage regulator502, sourcing leakage device/circuit paths504, and sinking leakage device/circuit paths506. Sourcing leakage current510is generated by the sourcing leakage device/circuit paths504during the suspend mode of operation. Generally, the leakage current510is substantially generated by the memory array, across which is supplied with a retention voltage in order to maintain data during the suspend mode of operation. This sourcing leakage current510is relatively less than the leakage current410generated inFIG. 4because the gate-sinking voltage keeper components operate as sinks instead of sources, and thus do not contribute to the source leakage510inFIG. 5.

Sinking leakage current514is generated by the sinking leakage device/circuit paths506during the suspend mode of operation, which includes the gate-sinking voltage keeper components. Generally, the sinking leakage current514is less than the sourcing leakage current510. Again, it is appreciated that the amount of source leakage current and sink leakage current are substantially equal in order to properly balance and control leakage current. Thus, the sinking voltage regulator502sinks extra sourcing current512not sunk by the sinking leakage device/circuit paths506and clamps the reference voltage to a desired level (e.g., 0.8 V). The amount of extra sourcing leakage current512sunk by the voltage regulator502is substantially less than that of the extra sourcing leakage current412ofFIG. 4because the sinking voltage keepers divert leakage that would otherwise go to the regulator and because the total mount of source leakage current is reduced. Accordingly, the memory device500consumes relatively less power than the memory device400ofFIG. 4.

FIG. 6is a diagram illustrating a detailed view of an exemplary gate-sourcing voltage keeper component601and an exemplary gate-sinking voltage keeper component602in accordance with an aspect of the present invention. For this view, the gate-sourcing voltage keeper component601is part of a first memory device and the gate-sinking voltage keeper component602is part of a second memory device. The first and second memory devices are similar in operation but for their respective voltage keeper components. The gate-sourcing voltage keeper component601is comprised of an NMOS transistor whereas the gate-sinking voltage keeper component602is comprised of a PMOS transistor.

Beginning with the gate-sourcing voltage keeper component601, a RET signal, referred to as a retention signal, is supplied/connected to a gate of the NMOS transistor. A drain of the NMOS transistor is electrically connected to an array VSS (VSSA) and a source is biased to a sinking suspend or reference voltage supplied by a voltage regulator (not shown). During normal mode or normal operation, the RET signal is de-asserted and remains low (e.g., about 0V). The VSSA voltage is biased to a normal mode supply voltage (e.g., about 0V) and is isolated from the voltage regulator and the suspend voltage.

During the suspend mode of operation, the RET signal is asserted and remains high (e.g., about 1.3V). The array VSS voltage (VSSA) is biased to the suspend voltage through the gate-sourcing voltage keeper component601and is isolated from the normal supply voltage. However, gate tunneling occurs, thereby generating gate sourcing leakage current as shown inFIG. 7because of several factors such as the suspend voltage, temperature, and the like. This gate sourcing circuit combined with array leakage current resulting in a substantial amount of source leakage current. This source leakage current can cause excessive thermal energy to be generated and raises the suspend voltage above a desired value. Additionally, this source leakage current results in excessive power consumption.

Turning now to the gate-sinking voltage keeper component602, a RETB signal, referred to as a complement of the retention signal, is supplied/connected to a gate of the PMOS transistor. A source of the PMOS transistor is electrically connected to an array VSS (VSSA) input and a drain is biased to a sinking suspend voltage supplied by a voltage regulator (not shown). During normal mode or normal operation, the RETB signal is de-asserted and remains high (e.g., about 1.3 V). The VSSA input is biased to a normal mode supply voltage (e.g., about 0 V) and is isolated from the voltage regulator and the sinking suspend voltage.

During the suspend mode of operation, the RETB signal is asserted and remains low (e.g., about 0 V). The VSSA input is biased to the sinking suspend voltage through the gate-sinking voltage keeper component602and is isolated from the normal supply voltage. However, gate tunneling occurs generating gate sinking leakage current as shown inFIG. 7. This gate sinking reduces the amount of source leakage current that would otherwise need to be sunk. Further, since the PMOS device does not contribute to source leakage, the total amount of source leakage is effectively reduced. This reduced amount of source leakage current can result in substantial power savings.

FIG. 8is a block diagram illustrating a memory device800that mitigates power consumption during a suspend mode of operation in accordance with an aspect of the present invention. The device800includes a suspend mode controller802, a memory array804, a gate-sinking voltage keeper component806, a sinking suspend voltage regulator808, a gate-sourcing voltage keeper component810, and a sourcing suspend voltage regulator812. The memory device800can be employed in a portable device such as a personal digital assistant, cellular phone, digital audio player, digital media player, and the like. Additionally, the memory device can be an SRAM, or other type memory device.

The controller802handles suspend mode operations for the memory device800. The controller802can comprise at least a portion of a power management system internal and/or external to the memory device800. The controller802can be operable to control other modes of operation (e.g., normal mode). The controller802generates control signals that are received by the gate-sinking voltage keeper component806and the gate-sourcing voltage keeper component810. Generally, the controller802de-asserts the suspend control signal during normal mode and asserts the suspend control signal during the suspend mode of operation.

Upon the control signal being asserted, the gate-sinking voltage keeper component806supplies a sinking suspend voltage generated and regulated by the sinking suspend voltage regulator808to the memory array804, while the gate-sourcing voltage keeper component810supplies a sourcing suspend voltage generated and regulated by the sourcing suspend voltage regulator812to the memory array804. Upon the control signal being de-asserted, the gate-sinking voltage keeper component806isolates the memory array804from the sinking suspend voltage regulator808, while the gate-sourcing voltage keeper component810isolates the memory array804from the sourcing suspend voltage regulator812. During the suspend mode of operation, the gate-sinking voltage keeper component806sinks at least a portion of leakage current generated/sourced by the memory array804. As a result, less leakage current needs to be sunk by other devices/paths (e.g., the suspend voltage regulator) thereby consuming less power (standby power) than other memory devices that employ gate-sourcing voltage keeper components that operate as sources during the suspend mode of operation.

A sourcing suspend voltage regulator812operates similar to the sinking suspend voltage regulator808, but generates and supplies a sourcing suspend voltage to the memory array804. A gate-sourcing voltage keeper component810can be employed to controllably provide the sourcing suspend voltage to the memory array804.

In view of the foregoing structural and functional features described supra, methodologies in accordance with various aspects of the present invention will be better appreciated with reference toFIGS. 1–8. While, for purposes of simplicity of explanation, the methodologies ofFIGS. 9–10are depicted and described as executing serially, it is to be understood and appreciated that the present invention is not limited by the illustrated order, as some aspects could, in accordance with the present invention, occur in different orders and/or concurrently with other aspects from that depicted and described herein. Moreover, not all illustrated features may be required to implement a methodology in accordance with an aspect the present invention.

Turning now toFIG. 9, a flow diagram illustrating a method900of operating a memory device in a suspend mode of operation in accordance with an aspect of the present invention is provided. The method900mitigates leakage current generated by the device during the suspend mode of operation by employing one or more voltage keeper components to sink at least a portion of leakage current generated by a memory array and/or other components of the memory device.

The method900begins at block902wherein a controller generates a suspend mode control signal. The control signal is typically de-asserted (e.g., low) during the suspend mode of operation. However, in alternate aspects of the invention, the control signal can be asserted (e.g., high) during the suspend mode of operation. Generally, a control signal is asserted when the signal activates a device, and is de-asserted when the signal operates to de-activate, or turn off, a device. Additionally, it is appreciated that alternate configurations may be employed, and such alternatives are contemplated by the present invention. At block904, a sinking suspend mode voltage is generated by a voltage regulator. This voltage is generally higher than the standard VSS voltage employed by the device and is selected to provide sufficient voltage across the array to enable resumption of normal mode and maintain data.

Continuing on, a VSSA input of a memory array is disconnected or isolated from a normal mode voltage (VSS) at block906. Generally, a footer is provided with the control signal and isolates the voltage supply input of the array from the normal mode supply voltage on the control signal being asserted. At block908, a gate-sinking voltage keeper component connects the sinking suspend voltage to the memory array in response to the control signal. Typically, the sinking suspend voltage is supplied to one or more control and/or power lines including a word line and the VSS supply (VSSA) of the array.

During the suspend mode of operation, the memory array generates/sources leakage current at block910. The leakage current results from pathways/devices within the array that are directly or indirectly connected to a suspend supply voltage. At block912, at least a portion of the generated leakage current is sunk or dissipated by the gate-sinking voltage keeper components. A remaining portion of the generated leakage current is sunk at block914, typically by circuitry within the voltage regulator.

FIG. 10is a flow diagram illustrating a method1000of operating a memory device in accordance with an aspect of the present invention. This method1000serves to illustrate transitions to and from suspend mode and associated operations performed in accordance with the present invention. Portions of the method1000are specific to the modes of operation, but can be performed in any suitable order.

Beginning at block1002, VSSA input of a memory array is biased to a normal VSS voltage and a VDDA input is biased to a normal VDD voltage. Continuing at block1004, the VSSA input and a word line are isolated from a suspend mode voltage by one or more voltage keeper components.

A suspend mode of operation is initiated at block1006by a power management system and/or controller. Subsequently, the VSSA input of the memory array is isolated from the normal array mode voltage and is biased to a suspend mode voltage by a first gate-sinking voltage keeper component and the supply voltage input is biased to a sinking suspend voltage at block1008. The word line of the memory array is also biased to the sinking suspend voltage by a second gate-sinking voltage keeper component at block1010. The memory array generates an amount of leakage current during the suspend mode of operation at block1012. The first gate-sinking voltage keeper component and the second gate-sinking voltage keeper component sink at least a portion of the generated leakage current at block1014. On exiting the suspend mode of operation, the method1000returns to block1002.

Although the invention has been shown and described with respect to a certain aspect or various aspects, it is obvious that equivalent alterations and modifications will occur to others skilled in the art upon the reading and understanding of this specification and the annexed drawings. In particular regard to the various functions performed by the above described components (assemblies, devices, circuits, etc.), the terms (including a reference to a “means”) used to describe such components are intended to correspond, unless otherwise indicated, to any component which performs the specified function of the described component (i.e., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary embodiments of the invention. In addition, while a particular feature of the invention may have been disclosed with respect to only one of several aspects of the invention, such feature may be combined with one or more other features of the other aspects as may be desired and advantageous for any given or particular application. Furthermore, to the extent that the term “includes” is used in either the detailed description or the claims, such term is intended to be inclusive in a manner similar to the term “comprising.”