Integrated circuit package system with integral inner lead and paddle

An integrated circuit package system is provided including forming a paddle, an outer lead, and an inner lead between the paddle and the outer lead; forming a non-vertical paddle edge of the paddle and a non-vertical lead edge of the inner lead facing the non-vertical paddle edge; and encapsulating an integrated circuit die over the paddle.

TECHNICAL FIELD

The present invention relates generally to integrated circuit package system, and more particularly to an integrated circuit package system having multiple rows of leads.

BACKGROUND ART

Increased miniaturization of components, greater packaging density of integrated circuits (“ICs”), higher performance, and lower cost are ongoing goals of the computer industry. As new generations of IC products are released, the number of devices used to fabricate them tends to decrease due to advances in technology. Simultaneously, the functionality of these products increases.

Semiconductor package structures continue to advance toward miniaturization and thinning to increase the density of the components that are packaged therein while decreasing the sizes of the products that are made therefrom. This is in response to continually increasing demands on information and communication apparatus for ever-reduced sizes, thicknesses, and costs, along with ever-increasing performance.

These increasing requirements for miniaturization are particularly noteworthy, for example, in portable information and communication devices such as cellular phones, hands-free cellular phone headsets, personal data assistants (“PDA's”), camcorders, notebook personal computers, and so forth. All of these devices continue to be made smaller and thinner to improve their portability. Accordingly, large scale IC (“LSI”) packages that are incorporated into these devices are required to be made smaller and thinner, and the package configurations that house and protect them are required to be made smaller and thinner as well.

Many conventional semiconductor die (or “chip”) packages are of the type where a semiconductor die is molded into a package with a resin, such as an epoxy molding compound. The packages have a lead frame whose out leads are projected from the package body, to provide a path for signal transfer between the die and external devices. Other conventional package configurations have contact terminals or pads formed directly on the surface of the package.

Such a conventional semiconductor package is fabricated through the following processes: a die-bonding process (mounting the semiconductor die onto the paddle of a lead frame), a wire-bonding process (electrically connecting the semiconductor die on the paddle to inner leads using lead frame wires), a molding process (encapsulating a predetermined portion of the assembly, containing the die, inner leads and lead frame wires, with an epoxy resin to form a package body), and a trimming process (completing each assembly as individual, independent packages).

The semiconductor packages, thus manufactured, are then mounted by matching and soldering the external leads or contact pads thereof to a matching pattern on a circuit board, to thereby enable power and signal input/output (“I/O”) operations between the semiconductor devices in the packages and the circuit board.

An exemplary semiconductor package, well known in the electronics industry, is the quad flat no-lead package (“QFN”). QFN packages typically comprise a lead frame, such as a conductive sheet stamped and etched, with a semiconductor die having a multitude of bond pads mounted to the top side of the lead frame. Wire bonds electrically connect the bond pads, of the semiconductor die, to a series of conductive lead fingers on the top side of the lead frame. Typically, the semiconductor die and the wire bonds are encapsulated within a molding compound.

In order to reduce manufacturing costs, the electronics industry is increasing the usage of QFN packages. In the manufacturing process, many obstacles must be overcome to deliver extremely small packages with increased number of input/output (I/O) in high volume.

One such obstacle is mold flash covering some of the inner lead contacts and preventing a reliable printed circuit board connection. This situation may be caused by debris on the mold bottom chase under the lead fingers or the clamping pressure on one end of a half etched lead causes the other end to lift. Another possibility is that the lead fingers may be bent or lifted prior to the molding step. The result of these issues is that the finished package may be missing some of the contact pads necessary to connect it to the printed circuit board.

Still thinner, smaller, higher I/O, and lighter package designs and mounting/connecting configurations have been adopted in response to continuing requirements for further miniaturization. At the same time, users are demanding semiconductor packages that are more reliable under increasingly severe operating conditions.

Thus, a need still remains for an integrated circuit package system providing low cost manufacturing, improved yield, higher pin count, and thinner height for the integrated circuits. In view of the ever-increasing need to save costs and improve efficiencies, it is more and more critical that answers be found to these problems.

DISCLOSURE OF THE INVENTION

The present invention provides an integrated circuit package system including forming a paddle, an outer lead, and an inner lead between the paddle and the outer lead; forming a non-vertical paddle edge of the paddle and a non-vertical lead edge of the inner lead facing the non-vertical paddle edge; and encapsulating an integrated circuit die over the paddle.

BEST MODE FOR CARRYING OUT THE INVENTION

In the following description, numerous specific details are given to provide a thorough understanding of the invention. However, it will be apparent that the invention may be practiced without these specific details. In order to avoid obscuring the present invention, some well-known circuits, system configurations, and process steps are not disclosed in detail. Likewise, the drawings showing embodiments of the system are semi-diagrammatic and not to scale and, particularly, some of the dimensions are for the clarity of presentation and are shown greatly exaggerated in the drawing FIGs. In addition, where multiple embodiments are disclosed and described having some features in common, for clarity and ease of illustration, description, and comprehension thereof, similar and like features one to another will ordinarily be described with like reference numerals.

For expository purposes, the term “horizontal” as used herein is defined as a plane parallel to the plane or surface of the integrated circuit, regardless of its orientation. The term “vertical” refers to a direction perpendicular to the horizontal as just defined. Terms, such as “above”, “below”, “bottom”, “top”, “side” (as in “sidewall”), “higher”, “lower”, “upper”, “over”, and “under”, are defined with respect to the horizontal plane. The term “on” means there is direct contact among elements. The term “processing” as used herein includes deposition of material, patterning, exposure, development, etching, cleaning, molding, and/or removal of the material or as required in forming a described structure. The term “system” as used herein means and refers to the method and to the apparatus of the present invention in accordance with the context in which the term is used.

Referring now toFIG. 1, therein is shown a bottom view of an integrated circuit package system100in an embodiment of the present invention. The bottom view depicts multiple rows of leads102around a paddle104, such as a die-attach paddle. The leads102include rows inner leads106, rows of outer leads108, and rows of middle leads110between the rows of the inner leads106and the outer leads108.

An encapsulation112, such as an epoxy mold compound, surrounds the paddle104, the inner leads106, and the middle leads110. The encapsulation112also partially surrounds the outer leads108. The encapsulation112exposes the leads102and the paddle104for further connections.

For illustrative purposes, the encapsulation112is shown exposing the paddle104, although it is understood that the paddle104may not be exposed. Also for illustrative purposes, the inner leads106are shown offset or staggered from the middle leads110, although it is understood that the inner leads106and the middle leads110may not be staggered. Further for illustrative purposes, the outer leads108are shown offset or staggered from the middle leads110, although it is understood that the outer leads108and the middle leads110may not be staggered.

Referring now toFIG. 2, therein is shown is a cross-sectional view of the integrated circuit package system100along a line2-2ofFIG. 1. The cross-sectional view depicts an integrated circuit die202mounted over the paddle104with an adhesive204, such as a die-attach adhesive. The integrated circuit die202has a non-active side206and an active side208having circuitry fabricated thereon. Interconnects210, such as bond wires, connect the active side208with the inner leads106, the middle leads110, and the outer leads108. The encapsulation112covers the integrated circuit die202and the interconnects210. The encapsulation112partially covers the inner leads106, the middle leads110, and the outer leads108.

The paddle104has non-vertical paddle edges212, such as curved or sloped edges, with a first side214of the paddle104facing the integrated circuit die202and a second side216of the paddle104are not the same dimension. The second side216is opposite the first side214and is exposed by the encapsulation112.

The paddle104may serve multiple functions. The paddle104may function as a heat sink or heat spreader for the integrated circuit die202providing a thermal dissipation path to ambient. The paddle104may be connected to an electrical ground and may function as an electromagnetic interference (EMI) shield.

Each of the inner leads106has a non-vertical lead edge218, such as a curved or a sloped edge, and the non-vertical lead edge faces the paddle104and the non-vertical paddle edges212. The edge of the inner leads106opposite the non-vertical lead edge218is a substantially vertical edge extending from a non-exposed side220of the inner leads106to an exposed side222. The non-exposed side220of the inner leads106and the exposed side222of the inner leads106are not the same dimension. The non-vertical lead edge218is further away from the paddle near the non-exposed side220at the top of the inner leads106, and is closer to the paddle near the exposed side222at the bottom of the inner leads106.

For illustrative purposes, the active side208is shown facing away from the paddle104, although it is understood that the integrated circuit die202may have the active side208facing the paddle104, such as a flip chip. Also for illustrative purposes, the integrated circuit die202is shown smaller than the paddle104, although it is understood that the integrated circuit die202may overhang the paddle104.

Referring now toFIG. 3, therein is shown is a bottom view of an integrated circuit package system300in an alternative embodiment of the present invention. The bottom view depicts multiple rows of leads302around a paddle304, such as a die-attach paddle. The leads302include rows inner leads306, rows of outer leads308, and rows of middle leads310between the rows of the inner leads306and the outer leads308.

An encapsulation312, such as an epoxy mold compound, surrounds the paddle304, the inner leads306, and the middle leads310. The encapsulation312also partially surrounds the outer leads308. The encapsulation312exposes the leads302and the paddle304. External interconnects314, such as solder balls, connect to the inner leads306, the outer leads308, and the middle leads310.

For illustrative purposes, the encapsulation312is shown exposing the paddle304, although it is understood that the paddle304may not be exposed. Also for illustrative purposes, the inner leads306are shown offset or staggered from the middle leads310, although it is understood that the inner leads306and the middle leads310may not be staggered. Further for illustrative purposes, the outer leads308are shown offset or staggered from the middle leads310, although it is understood that the outer leads308and the middle leads310may not be staggered.

Referring now toFIG. 4, therein is shown a cross-sectional view of the integrated circuit package system300along a line4-4ofFIG. 3. The cross-sectional view depicts an integrated circuit die402mounted over the paddle304with an adhesive404, such as a die-attach adhesive. The integrated circuit die402has a non-active side406and an active side408having circuitry fabricated thereon. Interconnects410, such as bond wires, connect the active side408with the inner leads306, the middle leads310, and the outer leads308. The encapsulation312covers the integrated circuit die402and the interconnects410. The encapsulation312partially covers the inner leads306, the middle leads310, and the outer leads308.

The paddle304has non-vertical paddle edges412, such as a curved or sloped edges, with a first side414of the paddle304facing the integrated circuit die402and a second side416of the paddle304are not the same dimension. The second side416is opposite the first side414and is exposed by the encapsulation312.

The paddle304may serve multiple functions. The paddle304may function as a heat sink or heat spreader for the integrated circuit die402providing a thermal dissipation path to ambient. The paddle304may be connected to an electrical ground and may function as an electromagnetic interference (EMI) shield.

Each of the inner leads306has a non-vertical lead edge418, such as a curved or a sloped edge, facing the paddle304and the non-vertical paddle edges412. A non-exposed side420of the inner leads306and an exposed side422of the inner leads306are not the same dimension. The external interconnects314attach to the exposed side422of the inner leads306. The external interconnects314attach to the outer leads308and the middle leads310at the same as the exposed side422of the inner leads306.

For illustrative purposes, the active side408is shown facing away from the paddle304, although it is understood that the integrated circuit die402may have the active side408facing the paddle304, such as a flip chip. Also for illustrative purposes, the integrated circuit die402is shown smaller than the paddle304, although it is understood that the integrated circuit die402may overhang the paddle304. Further for illustrative purposes, the external interconnects314are shown attached to the leads302, although it is understood that the external interconnects314may not attach to the leads302, such as pre-plated finish the leads302or solder dip the leads302.

Referring now toFIG. 5, therein is shown a bottom view of an integrated circuit package system500in another alternative embodiment of the present invention. The bottom view depicts multiple rows of leads502around a paddle504, such as a die-attach paddle. The leads502include rows inner leads506, rows of outer leads508, rows of first middle leads510, and rows of second middle leads511.

The first middle leads510and the second middle leads511are between the rows of the inner leads506and the outer leads508. The rows of the first middle leads510are between the rows of the second middle leads511and the rows of the inner leads506. The rows of the second middle leads511are between the rows of the outer leads508and the rows of the first middle leads510.

An encapsulation512, such as an epoxy mold compound, surrounds the paddle504, the inner leads506, the first middle leads510, and the second middle leads511. The encapsulation512also partially surrounds the outer leads508. The encapsulation512exposes the leads502and the paddle504for further connections.

For illustrative purposes, the encapsulation512is shown exposing the paddle504, although it is understood that the paddle504may not be exposed. Also for illustrative purposes, the inner leads506are shown offset or staggered from the first middle leads510, although it is understood that the inner leads506and the first middle leads510may not be staggered. Further for illustrative purposes, the outer leads508are shown offset or staggered from the second middle leads511, although it is understood that the outer leads508and the second middle leads511may not be staggered. Yet further for illustrative purposes, the first middle leads510are shown as offset or staggered from the second middle leads511, although it is understood that the first middle leads510and the second middle leads511may not be staggered.

Referring now toFIG. 6, therein is shown a top view of a portion a lead frame600of the integrated circuit package system500ofFIG. 5. The lead frame600includes tie bars602connected to the paddle504and a dam bar604. The lead frame600also includes the inner leads506the outer leads508, the first middle leads510, and the second middle leads511. The top view depicts the inner leads506and the first middle leads510integral to the paddle504. The outer leads508and the second middle leads511are integral to the dam bar604of the lead frame600.

Each of the inner leads506has an inner lead tip606and an inner lead body608, wherein the inner lead body608is wider than the inner lead tip606. The inner leads506extend from the paddle504with the inner lead tip606extending from the paddle504. The inner lead tip606includes an inner lead protrusion610. The inner lead body608is exposed from the encapsulation512ofFIG. 5for further connections.

Each of the first middle leads510has a first lead tip612and a first lead body614, wherein the first lead body614is wider than the first lead tip612. The first middle leads510extend from the paddle504with the first lead tip612extending from the paddle504. The first lead tip612includes a first lead protrusion616. The first lead body614is exposed from the encapsulation512for further connections.

Each of the second middle leads511has a second lead tip618and a second lead body620, wherein the second lead body620is wider than the second lead tip618. The second middle leads511extend from the dam bar604towards the paddle504with the second lead tip618extending from the dam bar604. The second lead body620is exposed from the encapsulation512for further connections. The outer leads508extend from the dam bar604towards the paddle504.

For illustrative purposes, the lead frame600is shown having four rows of the leads502, although it is understood that the lead frame600may have a different number of rows of the leads502. Also for illustrative purposes, the inner lead tip606, the first lead tip612, and the second lead tip618are shown as substantially linear, although it is understood that the inner lead tip606, the first lead tip612, and the second lead tip618for each of the inner leads506, the first middle leads510, and the second middle leads511, respectively, may not be linear, such as curved or have angled segments. Further for illustrative purposes, the inner leads506and the first middle leads510are shown extending from the paddle504, although it is understood that the leads502extending from the paddle504may be different, such as the second middle leads511extending from the paddle504.

Referring now toFIG. 7, therein is shown a top view of a portion a lead frame700of the integrated circuit package system100ofFIG. 1. The lead frame700includes tie bars702connected to the paddle104. The lead frame700also includes the inner leads106the outer leads108, and the middle leads110. The top view depicts the inner leads106integral to the paddle104. The outer leads108and the middle leads110are integral to the dam bar (not shown) of the lead frame700.

Each of the inner leads106has an inner lead tip704and an inner lead body706, wherein the inner lead body706is wider than the inner lead tip704. The inner leads106extend from the paddle104with the inner lead tip704extending from the paddle104. The inner lead tip704includes an inner lead protrusion708. The inner lead body706is exposed from the encapsulation112ofFIG. 5for further connections.

Each of the middle leads110has a middle lead tip710and a middle lead body712, wherein the middle lead body712is wider than the middle lead tip710. The middle leads110extend from the dam bar towards the paddle104with the middle lead tip710extending from the dam bar. The middle lead body712is exposed from the encapsulation112for further connections.

Each of the outer leads108has an outer lead tip714and an outer lead body716, wherein the outer lead body716is wider than the outer lead tip714. The outer leads108extend from the dam bar towards the paddle104with the outer lead body716extending from the dam bar. The outer lead body716is exposed from the encapsulation112for further connections.

For illustrative purposes, the lead frame700is shown having three rows of the leads102, although it is understood that the lead frame700may have a different number of rows of the leads102. Also for illustrative purposes, the inner lead tip704, the outer lead tip714, and the middle lead tip710are shown as substantially linear, although it is understood that the inner lead tip704, the outer lead tip714, and the middle lead tip710for each of the inner leads106, the outer leads108, and the middle leads110, respectively, may not be linear, such as curved or have angled segments. Further for illustrative purposes, the inner leads106are shown extending from the paddle104, although it is understood that the leads102extending from the paddle104may be different, such as the middle leads110extending from the paddle104.

Referring now toFIG. 8, therein is shown a cross-sectional view of the integrated circuit package system100having the lead frame700along a line8-8ofFIG. 7in a molding phase. The cross-sectional view depicts the integrated circuit die202over the paddle104. The interconnects210connect the integrated circuit die202with the inner leads106, the middle leads110, and the outer leads108. The encapsulation112covers the integrated circuit die202and the interconnects210. The encapsulation112partially covers the inner leads106, the middle leads110, and the outer leads108with the inner lead protrusion708exposed. The inner lead protrusion708maintains a planar surface802of the inner leads106mitigating or eliminating mold flashes of the inner leads106.

Referring now toFIG. 9, therein is shown a cross-sectional view of the integrated circuit package system100having the lead frame700along a line8-8ofFIG. 7in an alternative molding phase. The interconnects210connect the integrated circuit die202with the inner leads106, the middle leads110, and the outer leads108. The encapsulation112covers the integrated circuit die202and the interconnects210. The encapsulation112partially covers the inner leads106, the middle leads110, and the outer leads108. The encapsulation112also covers the inner lead protrusion708. The encapsulation112may be formed a number of different processes, such as utilizing bottom molding chase having cavities or trenches for covering the inner lead protrusion708. The inner lead protrusion708maintains the planar surface802of the inner leads106mitigating or eliminating mold flashes of the inner leads106.

Referring now toFIG. 10, therein is shown the structure ofFIG. 9in a phase for removing the inner lead protrusion708. The structure ofFIG. 9may undergo a grinding process with a grinding wheel1002for removing the inner lead protrusion708from each of the inner leads106and electrically isolating the inner leads106from the paddle104. The removal of the inner lead protrusion708forms the non-vertical paddle edges212and the non-vertical lead edge218, wherein the non-vertical paddle edges212and the non-vertical lead edge218are characterized in being formed from grinding of the inner lead protrusion708in the inner leads106integral with the paddle104to form the non-vertical lead edge218facing the non-vertical paddle edges212. The grinding process leaves the inner leads106, the outer leads108, and the middle leads110exposed. The grinding process may occur before or after singulation of the integrated circuit package system100.

Referring now toFIG. 11, therein is shown the structure ofFIG. 9in an alternative phase for removing the inner lead protrusion708. The structure ofFIG. 9may undergo a lasing process with a laser1102for removing the inner lead protrusion708from each of the inner leads106and electrically isolating the inner leads106from the paddle104. The removal of the inner lead protrusion708forms the non-vertical paddle edges212and the non-vertical lead edge218, wherein the non-vertical paddle edges212and the non-vertical lead edge218are characterized in being formed from lasing of the inner lead protrusion708in the inner leads106integral with the paddle104to form the non-vertical lead edge218facing the non-vertical paddle edges212. The lasing process leaves the inner leads106, the outer leads108, and the middle leads110exposed. The lasing process may occur before or after singulation of the integrated circuit package system100.

Referring now toFIG. 12, therein is shown the structure ofFIG. 9in another alternative phase for removing the inner lead protrusion708. The structure ofFIG. 9may undergo an etching process with a mask1202and chemical etch. The mask1202has holes1204exposing the inner lead protrusion708for etching. The etching process electrically isolates the inner leads106from the paddle104. The removal of the inner lead protrusion708forms the non-vertical paddle edges212and the non-vertical lead edge218, wherein the non-vertical paddle edges212and the non-vertical lead edge218are characterized in being formed from etching of the inner lead protrusion708in the inner leads106integral with the paddle104to form the non-vertical lead edge218facing the non-vertical paddle edges212. The etching process leaves the inner leads106, the outer leads108, and the middle leads110exposed with the mask1202removed. The etching process may occur before or after singulation of the integrated circuit package system100.

Referring now toFIG. 13, therein is shown a flow chart of an integrated circuit package system1300for manufacture of the integrated circuit package system100in an embodiment of the present invention. The system1300includes forming a paddle, an outer lead, and an inner lead between the paddle and the outer lead in a block1302; forming a non-vertical paddle edge of the paddle and a non-vertical lead edge of the inner lead facing the non-vertical paddle edge in a block1304; and encapsulating an integrated circuit die over the paddle in a block1306.

Yet other important aspects of the embodiments include that it valuably supports and services the historical trend of reducing costs, simplifying systems, and increasing performance.

These and other valuable aspects of the embodiments consequently further the state of the technology to at least the next level.

Thus, it has been discovered that the integrated circuit package system of the present invention furnishes important and heretofore unknown and unavailable solutions, capabilities, and functional aspects for improving reliability in systems. The resulting processes and configurations are straightforward, cost-effective, uncomplicated, highly versatile, and effective, can be implemented by adapting known technologies, and are thus readily suited for efficiently and economically manufacturing integrated circuit package system.