Electronic device including silicon carbide diode dies

An electronic device may include an elongated dielectric substrate having opposing first and second ends, a plurality of conductive pads longitudinally spaced apart along the elongated dielectric substrate, and a plurality of silicon carbide (SiC) (e.g., PiN) diode dies. Each SiC die may have bottom and top diode terminals and may be mounted on a respective conductive pad with the bottom diode terminal in contact therewith. The electronic device may further include at least one internal wirebond between the corresponding conductive pad of one SiC diode die and the top diode terminal of a next SiC diode die, a first external lead electrically coupled to the top diode terminal of a first SiC die and extending longitudinally outwardly from the first end, and a second external lead electrically coupled to the corresponding contact pad of a last SiC diode die and extending longitudinally outwardly from the second end.

BACKGROUND

Voltage multipliers are used to create a relatively high DC voltage from an AC power source. Such devices are used in a variety of applications ranging from particle accelerators to more commonplace electronic devices such as photocopiers.

One particular application in which particle accelerators are used is for nuclear-based borehole logging measurements in hydrocarbon resource wells (e.g., oil or natural gas wells). One such miniature, borehole-size particle accelerator is a neutron generator which utilizes the fusion of deuterium and tritium ion at high (100 keV) energies. This device irradiates the formation with 14 MeV neutrons which can be reflected and/or attenuated and, when measured, provide an indication of the hydrogen content of the formation; alternately, the stimulated gamma radiation response from the formation can be measured to provide, among other, an elemental composition of the formation.

SUMMARY

An electronic device is provided herein which may include an elongated dielectric substrate having opposing first and second ends, a plurality of conductive pads longitudinally spaced apart along at least one surface of the elongated dielectric substrate, and a plurality of silicon carbide (SiC) diode (e.g., PiN diode) dies (a.k.a., junctions). Each SiC die has opposing bottom and top terminals (e.g., anode and cathode) and may be mounted on a respective conductive pad with the bottom (e.g., the cathode) diode terminal in contact therewith. The electronic device may further include at least one internal wirebond between the corresponding conductive pad of one SiC diode die and the top diode terminal of a next SiC diode die, a first external lead electrically coupled to the top terminal of a first SiC die and extending longitudinally outwardly from the first end of the elongated substrate, and a second external lead electrically coupled to the corresponding contact pad of a last SiC diode die and extending longitudinally outwardly from the second end of the elongated substrate. By way of example, a conductive termination pad may also be positioned on the substrate and coupled to first external lead, and a wirebond may be coupled between the conductive termination pad and the top terminal of the first SiC die.

A related voltage multiplier circuit converts a first AC voltage to a second, higher DC voltage. The voltage multiplier circuit may include an input to receive the first voltage and an output to output the second voltage, and a plurality of capacitors and high voltage diodes (such as the electronic device described briefly above) electrically connected in an alternating fashion between the input and the output.

A related method is for making a high voltage diode. The method may include forming a plurality of conductive pads longitudinally spaced apart along an elongated dielectric substrate, where the elongated dielectric substrate having opposing first and second ends. The method may further include mounting a plurality of SiC diode (e.g., PiN) dies on respective conductive pads, with each SiC die having bottom and top diode terminals and being mounted on a respective conductive pad with the bottom diode terminal in electrical contact therewith. The method may further include positioning at least one internal wirebond between the corresponding conductive pad of one SiC diode die and the top diode terminal of a next SiC diode die. The method may also include electrically coupling a first external lead to the top diode terminal of a first SiC die and extending longitudinally outwardly from the first end of the elongated substrate, and electrically coupling a second external lead to the corresponding contact pad of a last SiC diode die and extending longitudinally outwardly from the second end of the elongated substrate.

DETAILED DESCRIPTION

The present description is made with reference to the accompanying drawings, in which example embodiments are shown. However, many different embodiments may be used, and thus the description should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete. Like numbers refer to like elements throughout, and prime and multiple prime notation are used to indicate similar elements in different embodiments.

Referring initially toFIGS. 1-3, an electronic device30which may be used as a high voltage rectifier diode is first described. By way of background, high voltage (HV) diodes (a.k.a. rectifiers) are a component of voltage multipliers, such as Cockcroft-Walton voltage multipliers (a.k.a., HV ladders). High voltage diodes used in such applications may be silicon-based, a material which has a relatively small band-gap, and are axial-leaded. At elevated temperatures (e.g., >175° C.), Si diodes will begin to fail by conducting current in a reverse bias mode, leading to a thermal runaway condition (with the self-induced heating).

Silicon carbide SiC has been identified as a material suitable for making PiN junction diodes for relatively high temperature (e.g., >200° C.) applications, given its large band gap (e.g., 3.1 eV compared to 1.1 eV for Si diodes). Additional advantageous properties of SiC include chemical stability, high temperature endurance and radiation hardness. Single SiC dies (a.k.a., junctions) may also be produced to withstand high voltage hold off to a few kilovolts.

Generally speaking, the present disclosure relates to an electronic device30, which illustratively includes a plurality or array of SiC diode dies31a,31bconnected in series, such as in a multi-chip module (MCM) style configuration on an insulating or dielectric (e.g., ceramic) substrate to provide a high temperature, high voltage diode. However, it should be noted that other components than the SiC diode dies31a,31bmay also be included within the electronic device30in some embodiments, such as an inductor(s) (e.g., a serpentine trace), which may help reduce an overall parasitic, junction, or other capacitance, or other components, for example. The dielectric substrate32is elongated and has opposing first and second ends33a,33b, and a plurality of conductive pads or landings34a,34blongitudinally spaced apart along the elongated dielectric substrate. The conductive pads34a,34bmay comprise metallization pads on the ceramic substrate32, for example. Each SiC diode die31has bottom (generally the cathode) and top (generally the anode) terminals35,36(seeFIG. 3) and is mounted on a respective conductive pad34a,34bwith the bottom diode terminal in contact therewith.

The electronic device30further illustratively includes one or more internal wirebonds37connected or coupled between the corresponding conductive pad34aof the SiC diode die31aand the top diode terminal36of the next SiC diode die31bin the series of diode dies. Multiple wirebonds may be used in some embodiments to provide redundancy, if desired. The wirebond lengths and shapes may be selected to provide large enough “loops” to avoid shorting on the edges of the diode dies31a,31b, etc., while at the same time keeping angles as shallow as possible so as to not protrude and thereby increase the physical size of the device. A wirebonding machine may be programmed to provide the desired wire layouts, or they may be created manually in some embodiments. In the illustrated example, the series includes the two diode dies31a,31b, but in other embodiments additional diode dies may be connected in the series in a similar fashion. That is, the design is scalable by adding more SiC diode dies31to increase the overall voltage rating of the diode as desired. Moreover, other diode die types may be used in different embodiment, such as gallium arsenide (GaAs) dies, for example.

A first external lead38ais electrically coupled to the top diode terminal36aof the first SiC die31bin the series by way of a conductive termination pad40and a wirebond41. More particularly, the first external lead38amay connected to the termination pad40by conductive solder42, conductive paste, spot welding, etc., and the first external lead extends longitudinally outwardly from the first end33aof the elongated substrate32. A second external lead38bis electrically coupled to the corresponding contact pad34bof a last SiC diode die31bin the series, and the second external lead extends longitudinally outwardly from the second end33bof the elongated dielectric substrate32. As such, the first and second external leads38a,38bare radial or axial leads, which may allow for relatively easy connectivity of the electronic device30to other circuit components.

By way of example, the wirebonds37,41are wires which may range from about 0.5 to 10 mils in diameter, whereas the first and second external leads may be larger, e.g., 20 mil diameter. Thus, the conductive pads40,34ballow for intermediate connection points from the first and second external leads38a,38bto respective dies31a,31b, as the relatively small top (e.g., anode) terminals36may be more appropriate for the smaller wirebonds to avoid potential shorting problems. The termination pad40is sized so that there is room for both the wirebond(s)41and the first external lead38ato be connected thereto.

To help protect the first and second leads38a,38b, these leads may optionally be routed through respective passageways or vias39a,39bthrough the substrate32. In the example ofFIG. 2, a dielectric encapsulant80surrounds the elongated dielectric substrate32, conductive pads34a,34b, the SiC diode dies31a,31b, and the internal wirebond37(as well as portions of the first and second leads38a,38b). The encapsulant80may advantageously help protect the electronic device30, particularly the wirebonds, and help prevent electrical or mechanical failures of the various wirebonds or terminals, as will be discussed further below. In an embodiment shown inFIG. 4, a dielectric coating81′ may similarly be used on the SiC diode dies and the internal wirebond37′. In still another embodiment shown inFIG. 5, the electronic device30″ may further include a casing82″ (e.g., glass) surrounding the elongated dielectric substrate32″ and defining a vacuum therein to provide mechanical and/or electrical protection. It should be noted that variations of the substrate32″ shape may be used to accommodate features such as the casing82″, or other components such as axial leads, an encapsulant, etc., in various embodiments. For example, a disc or flange may be incorporated perpendicular and at the end of the substrate32″ to provide support to the casing82″. Similarly, the substrate may be shaped longitudinally into a through/channel to protect one or more wirebonds and to contain any potting/encapsulant.

For comparison purposes, it is helpful to understand how a silicon HV diode is manufactured. There are several steps in the manufacturing process, but only those pertinent to this discussion are provided herein. The HV silicon diode includes several (e.g., 1 to 2 dozen) dies stacked end to end (e.g., cathode to anode), with leaded terminations at each end of the overall assembly. For example, a 10 kV HV diode is approximately 0.5 inches long×0.125 inch diameter. The die stack is manufactured from a stack of large diameter (e.g., 3 inches) pure silicon wafers (about 0.25 mm thick). Boron (powder), the dopant, is spread on each wafer surface and is thus sandwiched between each silicon wafer making up the stack. The whole stacked wafer assembly is then baked in a high temperature furnace to allow the dopant to diffuse into the silicon to create the desired diode semiconductor properties. Following this, the processed stack of wafers is then diced (e.g., with a thin-blade diamond saw) into the individual HV diode bodies (about 1 mm2) and subsequently (acid) cleaned before lead attachment and encapsulation.

Aside from the intrinsic semiconductor properties of the silicon HV diodes, suitable high voltage performance in the form of high bulk dielectric breakdown voltage (i.e., electrical hold off) and good surface creep or tracking resistance may be an issue. Generally, tracking is a consideration given that upwards of 1000 volts may be applied across each approximately 0.25 mm thin die. Any contaminants from the cutting operation (e.g., cutting fluid residue and smearing of the cutting blade), as well as impurities and residual voids in the encapsulant, may adversely affect diode HV performance by increasing HV leakage currents around the body.

With traditional silicon diodes, to achieve a higher voltage rating, more silicon dies (i.e., wafers) are added in the stack. However, the cutting becomes difficult beyond certain thickness or height-to-area aspect ratios. Furthermore, for axial-leaded diodes, mechanical (i.e., bending) stresses also place a structural restriction on the number of dies that may be used in a stack. As far as current carrying performance, increasing the die size (i.e., area) will increase its ability to pass higher currents. However, intrinsic defects in the bulk silicon wafer will increase the bulk reverse bias leakage current (which are responsible for thermal run away, as previously mentioned) for a given high voltage, in effect lowering the high voltage rating. This probability for such bulk HV leakage defects increases with die termination area. By extension to the whole diode stack, the probability for high voltage leakage therefore increases commensurately with the number of dies in the stack. It should be noted that one faulty/poor die in the stack may increase the stresses on the other dies, leading to a manufacturing reject of the whole assembly. That is, there may be no way to screen the individual junctions prior to assembly with silicon-based rectifiers. However, this is not the case for the above-described Sic diode die configuration. Rather, individual dies may be tested under points and thus screened for performance prior to integration.

However, the above-described SiC die array HV diode described above advantageously helps circumvent many of the above Si diode shortcomings. Several advantages may be realized when individual dies are arranged in a series array as described above. For example, the individual SiC diode dies31may be screened for performance (e.g., HV bulk leakage) prior to integration into the electronic device30. Also, the die cutting operation is less likely to introduce problems, since a thinner (e.g., single) wafer is used. One example SiC diode die is a 2 kV PiN die which has an approximate thickness of 0.25 mm, although other dies with different voltage ratings or dimensions may also be used.

Additionally, with the SiC diode dies31spaced apart along the substrate32, there is less “cross-heating”. That is, the SiC diode die31assembly arrangement on the substrate32in effect increases the surface-to-volume ratio, and thus the overall heat dissipation. Another way to look at this is that each die31a,31bis in direct contact with the substrate32, rather than being isolated by virtue of being in contact with other dies. As noted above, a conventional stacked silicon die arrangement is less tolerant of poorly performing individual dies (i.e., with increased bulk HV leakage currents), as they may unnecessarily heat up and thermally stress the adjoining dies. The substrate32may also be configured for enhanced heat dissipation (e.g., through the use of relatively high thermal conductivity Aluminum Nitride over Alumina).

The electronic device30may advantageously provide for enhanced mechanical integrity and high voltage creep management. For example, through-hole attachment of the radial leads38a,38bthrough the passageways39a,39bin the substrate32may improve mechanical integrity and reduce space-consuming lead bending to interconnected components. With respect to the wire bonding, the integrity of the wire bonds is a consideration given the relatively small dimensions of the wire used (e.g., on the order of a few thousandths of an inch). By way of example, gold, aluminum, or other suitable wires may be used, depending on the material compatibility with the SiC die terminations, which are “jumpered” from one die face (anode) to a “landing” (i.e., the conductive pads34a,34b) on the dielectric substrate32. Even a slight force applied to the wires may cause a failure by breakage of the wire or its attachment (i.e., bond) point. The above-described encapsulants or coatings may advantageously help protect against such breakage. The encapsulant may advantageously be selected to match the coefficient of thermal expansion (CTE) of the wire bonded assembly, or alternately, be sufficiently soft/pliable so as to not mechanically stress the wire interconnects. Example encapsulant materials include SIFEL® brand potting gels. Other example materials may include dielectric gels, pottings with additives to raise the material CTE (e.g., Boron-Nitride filled Dow Corning Sylgard® 182, and conformal coatings (e.g., polyimide, chemical vapor deposited polyp-xylylene) polymers, etc.). The dielectric substrate can also be shaped so as to protect the wirebond (e.g., the wires may be recessed in a channel or trough).

The geometry of the substrate32and packaging of the electronic device30may also advantageously be configured to provide desired HV creep performance. Referring additionally toFIG. 6, path lengthening techniques may be applied, including shaping the substrate32′″ to incorporate surface features such as pillars60′″ and/or trenches61′″ between the conductive pads34a′″,34b′″. Other geometries may also be used, such as corrugations, grooves, etc. Generally speaking, the linear spacing between the SiC diode dies31may be in a range of about 0.5 to 2 mm, although other spacings may be used. Similarly, the linear path distance along the surface features may be roughly 1:1 with the linear distance between the SiC diode dies31. So, for example, if two SiC diode dies31are linearly spaced 1 mm apart, the trench61′″ may have a depth of 0.5 mm, and the pillar60′″ may have a height of approximately 0.5 mm, although other relationships may be used in different embodiments.

In another example embodiment of the electronic device130described now with reference toFIG. 10, both sides (i.e., top and bottom sides) of a substrate132may have SiC diode dies131a-131bmounted thereon. In the illustrated example, a solid filled (a.k.a. blind) via140is used to interconnect conductive pads134a1,134a2so that the anode of the die131bmay be connected to the conductive pad134a2(and thus the cathode of the die131aon the opposite side of the substrate132) by wirebond137as shown. A wirebond141is connected to the anode of the die141, and the conductive pad134bhas a lead138connected thereto. The via140may be a solder or braze filled hole about 0.5 mm in diameter, for example. This configuration may help increase the separation for high voltage tracking between the SiC diode dies131a-131bwhile reducing package size. That is, the package size may be reduced through an appropriate spacing of one or more SiC dies on different sides of the substrate132. For example, a zigzag layout of conductive pads may be used on each side of the substrate132. In some embodiments, internal conductive traces may be used in the ceramic substrate132(e.g., HTCC or LTCC) instead of, or in addition to, the straight-through via140shown inFIG. 10.

A layered (i.e., multi-layer) Low Temperature Co-fired Ceramic (LTCC) or High Temperature Co-fired Ceramic (HTTC) insulating substrate approach may be used in the above-described embodiments, for example. Adequate cleanliness (i.e., surface preparation) is a consideration, particularly as the SiC diode die31spacing is reduced. As the overall diode voltage rating increases, the medium surrounding the diode (and dies) should desirably be more insulating to reduce arcing/flashover. While a conformal coating as discussed above may be beneficial in this regard, given that relatively small dimensions of SiC diode dies31may be used in the electronic device30(e.g., less than 1 mm), the appropriate electrically insulating coating may be selected to conform well to the features or geometries of the diode array. Moreover, such coatings may also be selected to match the CTE of the wire bonding and the application process to be mechanically compatible for the given implementation.

With respect to encapsulants or coatings, it is desirable that voids be avoided if possible, or kept away from the wirebonds (or SiC diode dies) to the extent such voids are created during the encapsulating or coating process. More particularly, during high voltage operation, if the wire bonds are surrounded by gas (e.g., air), the ejection of electrons into free space as a result of the localized corona effect may cause positively charged ions to sputter-erode the relatively thin wires and cause an electrical open circuit, which would cause a catastrophic failure of the device. Thus, even when encapsulants or coatings are used, any voids in these materials will entrap atmospheric air during the conformal application process, which may still allow the corona effect to occur in isolated regions despite the presence of the encapsulant or coating. Accordingly, the wettability/surface tension of the encapsulants or coatings to be used may be a consideration in certain embodiments. Vacuum potting techniques may also be used to help prevent the formation of such voids.

Turning additionally toFIG. 7, raised (e.g., promontory) features, such as a die pillar mounts65″″, may be formed on the substrate32″″ upon which the conductive pads and SiC diode die may be positioned or located. Such features may advantageously help increase the path length for HV creep. In some embodiments, the SiC diode dies and/or conductive pads may be positioned as close to the edges of the pillar mounts65″″ as possible to help prevent the collection of any encapsulant voids at these locations, for example.

For instances were voids are difficult to avoid, consideration may be given to performing the encapsulating process in an insulating (and chemically inert) gaseous atmosphere (e.g., SF6), such that any resulting voids do not contain moist air, for example, provided the encapsulant curing is compatible with such atmosphere.

In some embodiments, the die termination may be configured to not unnecessarily expose the anode electrode terminals35of the opposing die faces to HV tracking (e.g., through retracted edge termination as shown inFIG. 3). A conductive epoxy may be used to attach the SiC diode dies to the respective conductive pads, and it should be carefully applied so as to not cover/contact the sides of the die and lead to electrical tracking. In another advantageous configuration, a cup-shaped cavity or trench may formed in the substrate32in which the SiC diode dies31are recessed to provide additional mechanical protection to the diode assembly, and optionally to better confine/contain the encapsulant, such as for an insulating liquid (oil), for example. In still another embodiment, the SiC diode dies may be mounted on separate substrates, and the substrates positioned one on top of the other so that the SiC diode dies are interdigitated without the use of problematic wirebonds (e.g., corona and or robustness problems).

In accordance with another configuration, the SiC diode dies31may be staggered in a non-axial (e.g., zigzag or offset) configuration so that more dies may fit within a relatively short substrate32length while maintaining desired linear spacing between the dies. Furthermore, it should be noted that other first and second lead configurations may be used besides the axial wire bond leads noted above (e.g., nail head leads, etc.).

Turning now toFIG. 8, a two stage Cockcroft-Walton voltage multiplier70which advantageously incorporates the electronic device30(or variants thereof) described above converts a first AC voltage into a second, higher DC voltage. The Cockcroft-Walton voltage multiplier70illustratively includes an AC voltage drive source71, two series capacitor banks72,73, and a diode matrix75which interconnects the capacitors. Capacitors C1and C3define the AC capacitive bank72, and capacitors C2and C4define the DC capacitive bank73. Diodes D1through D4are high voltage rectifiers, and in particular each of the diodes D1-D4may comprise a respective electronic device30as described above. On positive peaks of the source voltage, diodes D1and D3conduct and D2and D4are reverse biased (off). At this time, capacitors C1and C3are charged. On negative voltage peaks D1and D3are off and D2and D4conduct, charging C2and C4. The voltage drive source71has an impedance associated therewith, which is represented by a resistor76, and the load for the voltage drive source is represented by a load resistor77. Other voltage multiplier configurations which incorporate the electronic device30as high voltage rectifier diodes may also be used, such as a Villard cascade voltage multiplier, charge pumps, etc. As noted above, such devices may be incorporated in power supplies for wellbore logging tools, such as described in U.S. Pat. No. 5,191,517 to Stephenson, which is assigned to the present Assignee and is hereby incorporated herein in its entirety by reference.

One benefit of the electronic device30is that it advantageously allows for more compact high voltage power supplies with respect to silicon diode approaches. The scalability of the above-described configurations allows for the use of very high voltage diodes, which may translate to fewer stages in the Cockcroft-Walton voltage multiplier70, or higher output voltage in the same size package. Given the diode high voltage rating is to match or exceed the stage voltage, the higher the voltage rating of the diodes used, the fewer the number of stages of the HV ladder that will achieve a given high voltage.

A related method for making a high voltage diode, such as the electronic device30, is now described with reference to the flow diagram90ofFIG. 9. The method illustratively includes forming a plurality of conductive pads34a,34b(Block91) longitudinally spaced apart along an elongated dielectric substrate32, where the elongated dielectric substrate has opposing first and second ends33a,33b. The method further includes mounting a plurality of SiC diode dies31a,31bon respective conductive pads34a,34b, at Block92, with each SiC die having bottom and top diode terminals35,36and being mounted on a respective conductive pad with the bottom diode terminal in contact therewith. The method further includes positioning an internal wirebond(s)37between the corresponding conductive pad34aof the SiC diode die31aand the top diode terminal36of a next SiC diode die31b, at Block93. The method also includes electrically coupling a first external lead38ato the top diode terminal36of the SiC diode die31aand extending longitudinally outwardly from the first end38aof the elongated substrate32, at Block94, and electrically coupling a second external lead38bto the corresponding contact pad34bof the SiC diode die31band extending longitudinally outwardly from the second end33bof the elongated substrate, at Block95, which illustratively concludes the method ofFIG. 9(Block96). Additional method aspects will be understood from the description provided above.