Method and apparatus for monitoring and controlling the thermal environment and operating conditions of an integrated circuit

Logic included in an IC monitors values of parameters that may affect operation of the IC, such as, for example, supply voltage (VDD), junction temperature (TJUNC) and the frequency of a ring oscillator on the IC. In response to the monitored values, the logic in the IC changes, if necessary, one or more parameters such as VDD, processor frequency (FCLK), and/or cooling level to control the performance of the IC. Thus, the IC monitors its own environment and operating conditions and takes appropriate steps to control its environment and operating conditions to achieve certain goals.

BACKGROUND OF THE INVENTION

The performance of an integrated circuit (IC) typically depends on several parameters that influence the speed at which the IC operates. Three such parameters of the IC are its supply voltage, operating temperature, and the thickness of the transistor-gate oxides. Variations in these parameters from respective nominal values may affect the delay time of signals that propagate within the IC, and thus, may vary the operating speed of the IC from a nominal speed. For example, if the voltage supply is lower than the nominal value, logic gates within the IC may operate more slowly because the rise times between logic0and logic1are longer due to the lower drive signal strength. Similarly, as the temperature of the IC decreases, logic circuits within the IC operate more quickly due to the increased mobility of carriers in the transistors. In addition, the thinner the gate-oxides, the faster the transistors, and thus, the faster the logic circuits of the IC. Conversely, the higher the supply voltage, the more quickly the logic gates operate, and the higher the temperature or the thicker the gate-oxides, the more slowly the logic gates operate.

Because these parameters may vary, the IC manufacturer typically accommodates these variations by predicting a best-case scenario and a worst-case scenario and designing the IC for a nominal case that is between the best- and worst-case scenarios. In a best-case scenario, the voltage supply is at its highest rated level, the IC operates at its lowest rated temperature, and the manufacturing process parameters (e.g., gate-oxide thickness) have their “fastest” values, such that the IC operates at its highest speed. Conversely, in the worst-case scenario, the voltage supply is at its lowest rated level, the temperature of the IC is at its highest rated value, and the manufacturing-process parameters have their “slowest” values, such that the IC operates at its slowest speed. By predicting the worst-case parameter values, an engineer can typically design an IC to operate adequately even under worst-case conditions.

However, it is becoming more difficult to design an IC to operate properly over the wide range of worst-case and best-case conditions, and soon may not be feasible. As ICs become increasingly dense (i.e., more transistors per unit area), there is more available area in which to include new forms of compensation circuitry. Supply voltage and temperature are currently controlled by circuits or devices that are external to the IC. IC process characteristics are typically universally ignored, except at the time of the original manufacturing tests.

Accordingly, a need exists for a way to more accurately compensate for the affect that parameter variations have on the operation of an IC.

SUMMARY OF THE INVENTION

The invention provides a method and an apparatus for monitoring and controlling environmental and operating conditions of an-integrated circuit (IC) in which the apparatus is located. Supply voltage measurement logic of the apparatus measures the supply voltage of the IC. Process speed measurement logic of the apparatus measures the process speed of the IC. Temperature measurement logic of the apparatus measures the temperature of the IC. Processing logic of the apparatus receives respective indications of the supply voltage, the process speed and the temperature from the measurement logic and processes the indications to generate a supply voltage control signal, a process speed control signal, and a temperature control signal. Supply voltage control logic of the apparatus controls the supply voltage of the IC in response to receiving the supply voltage control signal from the processing logic. Process speed control logic of the apparatus controls the process speed of the IC in response to receiving the process speed control signal from the processing logic. Temperature control logic of the apparatus controls the temperature of the IC in response to receiving the temperature control signal from the processing logic.

The method involves using supply voltage measurement logic, process speed measurement logic and the temperature measurement logic on the IC to measure the supply voltage, the process speed and the temperature of the IC, respectively. Indications of the supply voltage, the process speed and the temperature are received in processing logic of the IC and processed by the processing logic to generate a supply voltage control signal, a process speed control signal, and a temperature control signal. Supply voltage control logic on the IC is used to control the supply voltage of the IC in response to receiving the supply voltage control signal in the supply voltage control logic from the processing logic. Process speed control logic on the IC is used to control the process speed of the IC in response to receiving the process speed control signal in the process speed control logic from the processing logic. Temperature control logic on the IC is used to control the temperature of the IC in response to receiving the temperature control signal in the temperature control logic from the processing logic.

These and other features and advantages of the invention will become apparent from the following description, drawings and claims.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

In accordance with the invention, logic is included in an IC that monitors values of parameters that may affect operation of the IC, such as, for example, supply voltage (VDD), junction temperature (TJUNC) and the frequency of a ring oscillator on the IC. In response to the monitored values, the logic in the IC changes, if necessary, one or more parameters such as VDD, processor frequency (FCLK), and/or cooling level to control the performance of the IC. Thus, the IC monitors its own environment and operating conditions and takes appropriate steps to control its environment and operating conditions to achieve certain goals.

In accordance with the preferred embodiment of the invention, the logic of the invention measures one or more of the aforementioned parameters and performs a set of prioritized algorithms that adjust one or more of the parameters in accordance with preselected priorities. From highest to lowest, the priorities may be, for example, to: (1) maintain operation of the IC within limits so as to prevent the IC from being damaged (top-level priorities), (2) maintain proper functionality of the IC (medium-level priorities), and (3) optimize energy use and operating speed of the IC according to need thermal environment and operational demand (low-level priorities).

Preferably, the IC includes fuzzy logic that executes the prioritized algorithms of the invention. The prioritized algorithms use fuzzy parameters that are classified as INPUTS or CONTROLS. The INPUTS are values representing the state of the various environmental variables that affect the IC. The CONTROLS are values that can be modified by the IC in order to continually improve the performance and energy efficiency of the IC. Thus, as the IC becomes aware of its own process speed and of its own voltage and thermal environment, the fuzzy parameter values are updated to optimize performance and energy consumption.

FIG. 1is an illustration that depicts the typical parameters that will be varied to perform certain tasks in order to achieve the priorities (1)-(3). Each parameter is defined by a set of “fuzzy” variables. The fuzzy variables shown inFIG. 1are merely examples of suitable variables that may be used to define the parameter limits and ranges. For example, the supply voltage, VDD, is an INPUT and a CONTROL parameter defined by two limits and a fuzzy variable range, namely, “MAXIMUM”, “NORMAL” and “MINIMUM”. The values of MAXIMUM and MINIMUM correspond to the maximum and minimum limits, respectively, of VDD. The value of NORMAL corresponds to a value of VDDor range of VDDvalues in between the MAXIMUM and MINIMUM values.

As indicated above, maintaining the level of VDDbelow the maximum VDDlevel is a top-level priority. Maintaining the level of VDDabove the minimum VDDlevel is a medium-level priority. As described below in detail, the fuzzy logic reads the value of VDDand causes certain tasks to be performed in order to control the value of VDD. For example, if the value of VDDis above the MAXIMUM value, the fuzzy logic causes certain tasks to be performed (e.g., lowering the IC, power supply level) in order to lower the value of VDDto a value that is below the value of MAXIMUM.

The junction temperature, TJUNC, is an INPUT parameter defined by an upper limit and three fuzzy variable ranges, namely, MAXIMUM, HOT, NORMAL, and COLD. The junction temperature is measured by a thermal diode, which is a known device included today in many IC packages. The value of MAXIMUM corresponds to the maximum value for TJUNC. The variable HOT corresponds to some range of values between the values of MAXIMUM and NORMAL. The variable NORMAL corresponds to some range of values between the values of HOT and COLD. The variable COLD corresponds to any temperature below the NORMAL range.

As indicated above, maintaining TJUNCat a temperature below the maximum TJUNClevel, MAXIMUM, is another top-level priority. The fuzzy logic reads the TJUNCvariable values and, if necessary, causes certain tasks to be performed to increase or decrease TJUNC. As described below in detail, TJUNCcan be increased or decreased by increasing or decreasing, respectively, either the frequency FCLKor the IC power supply level. For example, if the fuzzy logic determines that the value of TJUNCis greater than the TJUNCMAXIMUM value, the fuzzy logic will cause the IC to decrease the frequency FCLKand/or the power supply level until the fuzzy logic determines that the value of TJUNCis no longer above the TJUNCMAXIMUM.

Processor demand is another parameter that is measured and evaluated by the fuzzy logic to determine whether some action needs to be taken by the IC. This parameter corresponds to the types and quantities of processing demands that are placed on the IC microprocessor. As indicated above, the lower-level priorities relate to optimizing operational speed and energy consumption. These goals are achieved, in part, by monitoring processor demand, and as demand dictates, varying FCLKto vary the speed at which the IC microprocessor executes instructions. However, varying FCLKhas an effect on the amount of energy that is consumed by the IC. Therefore, as described below in detail, several factors are taken into consideration when determining whether and by how much to vary FCLK.

The processor-demand INPUT variable illustrated inFIG. 1may be defined by three fuzzy variable ranges and a limit, such as, for example, HIGH, NORMAL, LOW and NONE. The HIGH variable may correspond to processing tasks that have the highest priority, such as operating system (OS) scheduling tasks. The NORMAL variable may correspond to functional mode processing tasks associated with execution of an application computer program. The LOW variable may correspond to lower priority processing tasks, such as segments of an application program that have no execution time limit. The values of these variables are measured and the frequency of the IC microprocessor clock, FCLK, is adjusted, if necessary, to optimize performance and energy consumption.

The CONTROL parameter FCLKis illustrated inFIG. 1as being defined by two limits and two fuzzy variable ranges, namely, MAXIMUM, HIGH, LOW, and MINIMUM. The MAXIMUM FCLKvariable may correspond to the maximum clock frequency of the IC microprocessor. The MINIMUM FCLKvariable may correspond to the minimum clock frequency of the IC microprocessor. The HIGH FCLKvariable may correspond to an FCLKvalue that is less than FCLKMAXIMUM and greater than FCLKMINIMUM. The LOW FCLKvariable may correspond to an FCLKvalue that is less than FCLKHIGH and greater than FCLKMINIMUM. As indicated above, the fuzzy logic will measure the values of these variables and determine the proper course of action based on the values in order to optimize performance and energy consumption.

The cooling fan CONTROL parameter shown inFIG. 1corresponds to the case in which a cooling fan is available for use to cool the IC. As indicated above, the junction temperature, TJUNC, can be varied by varying FCLKand/or the IC power supply level. If a cooling fan is available, operation of the cooling fan may be controlled in conjunction with, or in lieu of, controlling the FCLKor the power supply in order to control TJUNC. The cooling fan CONTROL settings are listed inFIG. 1as HIGH, MEDIUM, LOW and OFF. The HIGH value corresponds to the highest setting of the fan. The LOW value corresponds to the lowest setting of the fan. The MEDIUM value corresponds to a setting in between HIGH and LOW. The OFF value corresponds to the fan being in the off setting.

As described below in detail, the value of the cooling fan CONTROL parameter may be read by the fuzzy logic, which will then cause one or more tasks to be performed. For example, if TJUNCis at TJUNCHOT and the cooling fan is set to LOW, then the fuzzy logic may cause the cooling fan setting to be increased to MEDIUM. In addition to changing the cooling fan setting, the fuzzy logic may cause the power supply to be slightly decreased, e.g., to a level that causes VDDto be decreased to a NORMAL value at the lower end of the NORMAL range.

All of these fuzzy variable values may be varied before, after or during execution of the prioritization algorithm in order to improve performance and optimize energy consumption. Some fuzzy variable values will typically be application-specific, and thus will need to have suitable values for a particular application. For example, the types of processing tasks that are of NORMAL and LOW priority will typically be defined for each application. Similarly, a processing task that is defined as being of LOW priority prior to run-time may be redefined at run-time as being of NORMAL priority. As another example, if, during the execution of an application program by the IC, the fuzzy logic determines that the initial value of the FCLKHIGH is too low, the value of FCLKHIGH can be increased by the fuzzy logic during execution of the program.

FIG. 2illustrates a flow chart that represents certain tasks performed by a prioritized algorithm using parameters shown inFIG. 1to achieve priorities (1)-(3). Likewise,FIG. 3illustrates a flow chart that represents certain tasks performed by a prioritized algorithm using parameters shown inFIG. 1to achieve priorities (1)-(3). The tasks shown inFIGS. 2 and 3will typically be performed in parallel by one or more processors of the IC.FIGS. 2 and 3both show the performance of top-level priority tasks, medium-level priority tasks and lower-level priority tasks.

As stated above, the top-level priority is to maintain operation of the IC within limits so as to prevent the IC from being damaged. In accordance with this exemplary embodiment of the invention, the top-level priority is accomplished by maintaining the supply voltage VDDbelow VDDMAXIMUM and by maintaining the junction temperature TJUNCbelow its TJUNCMAXIMUM. The parameters VDDand FCLKwill typically be initialized at the start of execution the algorithm, as indicated by blocks2and11inFIGS. 2 and 3, respectively. These initial values may be nominal values, i.e., in the middle of the operating range.

A determination is made at block3(FIG. 2) as to whether the value of VDDis greater than VDDMAXIMUM. If so, one or more parameters are varied to decrease VDD, as indicated by block4. As stated above, VDDwill typically be decreased by decreasing the power supply setting for the IC, as described in detail below with reference toFIG. 4. Because it is a top priority to ensure that VDDis not above the maximum VDDlimit, the process then returns to block3to determine whether VDDhas been increased above the maximum VDDlimit.

With reference toFIG. 3, a determination is made at block12as to whether the value of TJUNCis greater than TJUNCMAXIMUM. If so, FCLKis decreased in order to decrease TJUNC, as indicated by block13. The manner in which this may be accomplished is described below with reference toFIG. 6. However, as stated above, a cooling fan may also be used to control TJUNC, as described below in detail with reference toFIG. 5.

The process then returns to block12(FIG. 3) in order to determine whether TJUNCis above TUNCMAXIMUM. If the results of the decisions represented by blocks3and12are that VDDis not greater than the maximum VDDlimit and that TJUNCis not greater than the maximum TJUNClimit, then the parallel processes proceed to blocks5and14inFIGS. 2 and 3, respectively. Blocks5and14represent medium-level priority tasks, which are also performed in parallel. The purpose of performing the medium-level priority tasks is to maintain proper functionality of the IC by maintaining VDDabove a minimum VDDlimit, and by maintaining the microprocessor clock frequency, FCLK, below a maximum reference clock frequency. Of course, if VDDis too low, the IC will not operate properly. Likewise, if FCLKis too low, the IC will not operate properly. The manner in which the real-time FCLKvalue may be measured and, if deemed appropriate, varied is described below with reference toFIG. 6.

If a determination is made at block5(FIG. 2) that VDDis not greater than the minimum VDDlimit, then the power supply level is increased, thereby causing VDDto be increased, as indicated by block6(FIG. 2). The process then returns to the block3(FIG. 2) to determine whether VDDis above VDDMAXIMUM. If a determination is made at block14(FIG. 3) that FCLKis not less than FCLKMAXIMUM, then one or more parameters are varied to decrease FCLK, as indicated by block15(FIG. 3). The process then returns to block12(FIG. 3) to determine whether TJUNCis greater than the TJUNCMAXIMUM.

It should be noted from the above description of blocks36in FIG.2and12-14inFIG. 3that the tasks associated with the medium-level priorities are not taken into account until the top-level priority tasks have been performed. In addition, as described above, while the medium-level priority, tasks are being performed, the top-level priority tasks are also being performed. Once the top-level and medium-level priority tasks have been performed, lower-level priority tasks are performed. In addition, while the lower-level priority tasks are being performed, the top-level and medium-level priority tasks are also being performed, as described below in more detail.

The main purpose of the lower-level priorities is to optimize performance and energy consumption. Blocks7-11shown inFIG. 2represent lower-level priority tasks that are accomplished by either increasing or decreasing VDDbased on the measured difference between the frequency, FREF, of the IC reference clock, CLKREF, and the frequency, FROSC, of a ring oscillator output signal, CLKROSC. Because the ring oscillator is located on the IC, the frequency of the ring oscillator is proportional to the operation speed of the IC. Thus, by measuring the frequency of the ring oscillator, and comparing the frequency of the ring oscillator with CLKREF, which is fixed, a measure of the operational speed of the IC is obtained. A circuit for measuring the difference between the frequency of CLKREFand the frequency of the ring oscillator output signal is described below with reference toFIG. 4.

With reference again toFIG. 2, a decision is made as to whether the frequency of the ring oscillator output signal is greater than or equal to the frequency of CLKREF, as indicated by block7. If so, the power supply level is decreased in order to decrease VDD, as indicated by block8. If not, a decision is made by block9as to whether the frequency of the ring oscillator output signal is less than CLKREF. If not, the process returns to block7. If so, the power supply level is increased in order to increase VDD, as indicated by block11. The process then returns to block3to ensure that the top-level priorities continue to be met.

Prior to describing the lower-level priority tasks shown inFIG. 3, the manner in which the difference between the frequency FREFof CLKREFand the frequency FROSCof the ring oscillator output signal is measured will be described with reference toFIG. 4.FIG. 4illustrates a block diagram of a feedback-based, delay-stabilization circuit40of an IC30that forces the IC30toward or to its nominal operating point. The circuit40monitors the frequency (FROSC) of a signal output from a ring oscillator41and adjusts the power supply51in response to a change in the frequency (FROSC) of the signal output from the ring oscillator41in order to control VDDand/or TJUNC. Thus, the circuit40shown inFIG. 4can be used to accomplish the lower-level priority tasks represented by blocks7-11inFIG. 2.

The circuit40includes the ring oscillator41, one or more frequency dividers42and44, a phase-frequency detector (PFD)45, a low-pass filter (LPF)46, a biasing block47, a signal combining block48, and a clamp49, all of which are described below in greater detail. The circuit40is disclosed in U.S. Pat. No. 6,930,521B2, issued on Aug. 16, 2005, which is incorporated herein by reference herein in its entirety.

As stated above, because the ring oscillator41is disposed on the IC30, the frequency FROSCof the signal output from the ring oscillator41is proportional to the operating speed of the IC30. The ring oscillator41is designed such that its output signal has a nominal value when the IC30is operating at its nominal operating point, i.e., when the parameters such as supply voltage, temperature, and gate-oxide thickness are all at their nominal values. However, if these operating parameters are, on average, skewed toward a best-case operating condition, then the frequency of the signal output from the ring oscillator41is higher than the nominal value, which indicates that the IC30is operating “faster” than nominal. Conversely, if these parameters are, on average, skewed toward a worst-case operating condition, then the frequency of the signal output from the ring oscillator41is lower than the nominal value, which indicates that the IC30is operating “slower” than nominal. Therefore, the frequency of the signal output from the ring oscillator41provides a noninvasive measurement of the operating point of the IC30.

As the operating point of the IC30fluctuates due to changes in the operating parameters, the frequency FROSCof the signal output from the ring oscillator41changes, thus tracking the fluctuations in the operating point. For example, if TJUNCrises or VDDfalls, then the frequency FROSCof the oscillator signal will decrease, thus indicating the slower operation of the IC30. Conversely, if TJUNCfalls or VDDrises, then the frequency FROSCof the oscillator signal will increase, thus indicating the faster operation of the IC30. The feedback circuit40controls the supply voltage to the IC30so as to drive the frequency FROSCof the signal output from the ring oscillator41toward its nominal value, thereby causing the IC30to be driven toward its nominal operating point.

Specifically, a reference clock generator53, which is external to the IC30, generates a CLKREFsignal having a frequency FREFthat is close to the nominal frequency of the ring oscillator41. Alternatively, if the generator53does not generate the reference clock having the nominal frequency of the oscillator41, then one or both of the frequency dividers42and44may be programmed so that the generator53effectively generates the reference clock having the nominal frequency. For example, if the nominal frequency is 100 MHz, but the generator53generates a 200 MHz reference clock, then the divider44can be programmed to divide the frequency of the reference clock by two in order to obtain the nominal frequency of 100 MHz.

The outputs of the ring oscillator41and the reference-clock generator53(possibly divided by the frequency dividers42and44) are fed into the PFD45, which generates a binary up/down voltage error signal that signifies which of the two frequencies is higher. The LPF46smoothens the voltage error signal to set the bandwidth of the feedback loop formed by the circuit40and the power supply51. The resulting filtered signal is then typically input to a biasing block47that limits and/or otherwise adjusts the error signal. For example, the error signal, if left unbiased, may cause the power supply51to provide a supply voltage VDDthat is higher than what the IC30can tolerate. Circuitry within the biasing block47limits the supply voltage to an acceptable level. In addition, the biasing block47may be used to manipulate the error signal to a magnitude-based error signal or a percentage-based error signal.

The biased error signal is input to a signal combiner48, which combines the error signal with the supply voltage output from the power supply51. If the error signal is a magnitude-based error signal, then the two inputs to the combiner48are summed, as is shown inFIG. 4. If the error signal is a percentage-based error signal, the combiner48will be replaced with a multiplier (not shown) that multiplies the two inputs together.

Once the supply voltage VDDoutput from the power supply51has been adjusted to a level that results in nominal operation of the IC30, the frequency of the signal output from the ring oscillator41will have the nominal value, i.e., the same frequency as CLKREF, thus stabilizing the IC30at its nominal operating point.

It should be noted that the circuit40shown inFIG. 4and described above is one example of a circuit that is suitable for performing the lower-level priority tasks shown inFIG. 2. Other circuit configurations can be used to perform these tasks, as will be understood by persons skilled in the art in view of the description provided herein.

While the lower-level priority tasks represented by blocks7-11inFIG. 2are being performed, the lower-level priority tasks represented by blocks16-24inFIG. 3preferably are also being performed, i.e., the processes are performed in parallel. Blocks16-24shown inFIG. 3represent lower-level priority tasks that are accomplished by either increasing or decreasing the internal processor clock, FCLK, in order to optimize performance and energy consumption. The internal processor clock FCLKgenerally is derived by using one or more frequency dividers (not shown) to divide FREFinto a lower frequency. The manner in which FCLKis increased and decreased is described below with reference toFIG. 6.

A determination is made at block16as to whether processor demand is HIGH, LOW to NORMAL or NONE. If a determination is made that processor demand is HIGH, e.g., that a number of critical processing tasks or a large number of normal tasks are waiting to be performed, then FCLKis increased; as indicated by block17. The process then returns to block12to ensure that the top-level and medium-level priorities continue to be met. If a determination is made at block16that demand is NONE, i.e., that no tasks are waiting to be performed, the IC switches itself to a power-save mode. In the power save mode, FCLKis decreased to a minimum acceptable level such that the IC conserves power. The process then returns to block16.

If a determination is made at block16that processor demand is between LOW and NORMAL, e.g., non-critical processing tasks are waiting to be executed, then the process proceeds to block19. At block19, a determination is made as to whether the value of TJUNCis HOT, COLD or NORMAL. If it is determined that the value of TJUNCis between NORMAL and HOT, the process returns to block12. If it is determined that the value of TJUNCis COLD, then FCLKis increased, as indicated by block21. The process then returns to block12. If the value of TJUNCis not less than HOT, then the process returns to block16. If a determination is made at block19that the value of TJUNCis HOT, then FCLKis decreased, as indicated by block22. A determination is then made as to whether FCLKis greater than FCLKMINIMUM, as indicated by block23. If so, the process returns to block12. If not, FCLKis increased, as indicated by block24. The process then returns to block12.

The above description of blocks16-24demonstrates that a tradeoff exists between processing speed, i.e., FCLK, and power consumption. The goal of the lower-level priority tasks is to increase FCLKwhen processor demand is high and to decrease FCLKin order to reduce power consumption when processor demand decreases. The top-level and medium-level priorities are also taken into consideration as the lower-level priorities are being considered to ensure that increasing FCLKdoes not result in an increase in TJUNCabove TJUNCMAXIMUM (blocks12and13), or in an increase in FCLKabove FCLKMAXIMUM (blocks14and15).

As indicated above with reference toFIG. 1, the value of TJUNCcan also be reduced by using some type of cooling system, such as a cooling fan, for example.FIG. 5illustrates a flow chart that represents an algorithm that can be performed either separate from or in conjunction with the portion of the algorithm represented by blocks16-24inFIG. 3. As shown inFIG. 5, at the beginning of execution of the algorithm the cooling system is set to some initial setting, as indicated by block61. The initial setting will typically be some nominal setting that has been determined to by a suitable setting for most conditions, e.g., low. A determination is made at block62as to whether the value of TJUNCis HOT, COLD or NORMAL. If the value of TJUNCis in the HOT range, the cooling system is set to HIGH, as indicated by block63. The process then returns to block62.

If the value of TJUNCis determined at block62to be in the NORMAL range, the process proceeds to block68at which a determination is made as to whether the process speed is FAST, SLOW or NORMAL. The process speed is a variable that is dependent on the value of VDD. As described above with reference toFIG. 4, the ring oscillator41outputs a signal having a frequency FROSCthat is proportional to the operating, or process, speed of the IC. Because the power supply is varied in order to vary the frequency of the signal that is output from the ring oscillator41, the value of VDDis proportional to the process speed and can be used in a straightforward manner to determine the process speed of the IC.

If it is determined at block68that the process speed is FAST, the cooling system is set to HIGH, as indicated by block69. The process then returns to block62. If it is determined at block68that the process speed is SLOW, then the cooling system is set to MEDIUM, as indicated by block71. The process then returns to block62. It is determined at block68that the process speed is NORMAL, then the cooling system is set to MEDIUM to HIGH, as indicated by block72. T he process then returns to block62.

If the value of TJUNCis determined at block62to be in the COLD range, the process proceeds to block64at which a determination is made as to whether the process speed is FAST, SLOW or NORMAL. If it is determined at block64that the process speed is FAST, the cooling system is set to MEDIUM to LOW, as indicated by block66. The process then returns to block62. If it is determined at block64that the process speed is SLOW, then the cooling system is set to OFF, as indicated by block67. The process then returns to block62. It is determined at block64that the process speed is NORMAL, then the cooling system is set to LOW, as indicated by block65. The process then returns to block62.

FIG. 6illustrates a block diagram of an IC100having a fuzzy logic unit110for performing the algorithms of the invention described above with reference toFIGS. 2-5. The components101-106may be identical to components41-46, respectively, shown inFIG. 4. The output of the LPF106is a lowpass-filtered signal having an analog value that corresponds to the difference between the frequency of the signal output from the ring oscillator101and the frequency of the reference clock signal CLKREF. The signal output from the LPF106is converted by an analog-to-digital converter (ADC)107into a multi-bit digital signal having a digital value that corresponds to the difference between the frequency of the signal output from the ring oscillator101and the frequency of the reference clock signal CLKREF. The fuzzy logic unit110processes this signal and generates a multi-bit digital signal having a value that, when converted into an analog signal, corresponds to a level to which the power supply109is to be set in order to cause VDDto be adjusted to a value that will cause the difference between the frequencies of the ring oscillator output signal to be driven toward zero. The fuzzy logic unit110also processes the signal output from ADC107to obtain an indication of process speed, which is used by the fuzzy logic unit110to perform the algorithm described above with reference toFIG. 5.

The digital signal108is converted by a digital-to-analog converter (DAC)109into an analog signal that is output to the power supply109to set the level of the power supply109. The power supply109then outputs the corresponding reference voltage signal VDDto the IC100. The current level of VDDis sensed at some location on the IC100by an ADC113, which converts the analog voltage signal into a multi-bit digital signal that is processed by the fuzzy logic unit110to perform the tasks described above with reference toFIG. 2.

A thermal diode114measures the junction temperature TJUNCof the IC100and generates an analog voltage signal having a value that is proportional to the value of TJUNC. An ADC115converts the analog signal into a multi-bit digital signal that is received and processed by the fuzzy logic unit110to perform the tasks described above with reference toFIGS. 3 and 5. A stable reference voltage device116supplies the ADCs107,113and115and the DAC111with a stable reference voltage that does not vary with variations in process, temperature and/or supply voltage.

The fuzzy logic unit110processes the process speed and TJUNCvalues in accordance with an algorithm such as that described above with reference toFIG. 5and produces a multi-bit digital signal, which, when converted by DAC117into an analog voltage signal, corresponds to the setting of a cooling system118that will be used to cool the IC100.

The fuzzy logic unit110receives an indication of the processor demand from the microprocessor core logic119of the IC100. The indication may be, for example, a two-bit signal with00corresponding to no demand,01corresponding to low demand,10corresponding to normal demand, and11corresponding to high demand. The fuzzy logic unit110processes the processor demand indication along with the TJUNCvalue received from ADC115in accordance with the algorithms described above with reference toFIGS. 3 and 5.

The fuzzy logic unit110processes the TJUNCvalue and processor demand indication in the manner described above with reference toFIG. 3to obtain a speed indication of how much, if any, to vary FCLK. This indication is output to a phase-locked loop (PLL)121, which varies the frequency of a reference clock signal provided to the PLL121to generate FCLK. InFIG. 6, two clock signals are shown for exemplary purposes, namely, FCLK1, which is used by the application specific logic122of the IC100that performs application tasks, and FCLK2, which is used by the microprocessor core logic119.

It should be noted that the invention has been described above with reference to exemplary embodiments and that the invention is not limited to the exemplary embodiments described herein. The invention is not limited to using the parameters and fuzzy variables described above with reference toFIG. 1. In addition, the invention is not limited to the prioritization algorithms described above with reference toFIGS. 2,3and5, or to the logic configuration described above with reference toFIGS. 4 and 6. Those skilled in the art will understand, in view of the description provided herein, that many variations may be made to the embodiments described above with reference toFIGS. 1-6, and that all such variations are within the scope of the invention.