Display panel and display device including the same

Provided is display panel including a substrate including a pixel area and a pad area; and a first conductive line and a second conductive line stacked on the substrate, wherein the first conductive line includes a first part disposed on the pixel area and a second part disposed on the pad area and the second conductive line includes a first part disposed on the pixel area and a second part disposed on the pad area. The first part of the first conductive line and the first part of the second conductive line are parallel to each other and the second part of the first conductive line and the second part of the second conductive line are overlapped vertically.

CROSS-REFERENCE TO RELATED APPLICATIONS

This U.S. non-provisional patent application claims priority under 35 U.S.C. § 119 of Korean Patent Application Nos. 10-2015-0181839, filed on Dec. 18, 2015, and 10-2016-0081975, filed on Jun. 29, 2016, the entire contents of which are hereby incorporated by reference.

BACKGROUND

The present disclosure herein relates to a display panel and a display device including the same, and more particularly, to a Chip On Glass (COG) type display panel and a display device including the same.

The inventive concept relates to a liquid crystal display device, and more particularly, to a pattern formation of an input/output signal transmission pad in a COG mounting structure liquid crystal display device.

With the recent rapid development to information society, the need for flat panel display devices having excellent characteristics such as thin thickness, light weight, and low power consumption emerges, and since a liquid crystal display among them has excellent resolution, color display, and image quality, it is actively applied to a monitor of a notebook computer or a desktop computer.

In general, a liquid crystal display device is a device where two substrates with respective electrodes are disposed to allow surfaces with the two electrodes to face each other, and after a liquid crystal material is injected between the two substrates, liquid crystal molecules are moved by an electric field generated by applying voltage to the two electrodes in order to represent an image by a light transmittance changed according thereto.

Such a liquid crystal display device includes a liquid crystal panel where liquid crystal is injected between two substrates, a backlight disposed at a lower part of the liquid crystal panel and used as a light source, and a driving unit disposed at the outside of the liquid crystal panel and configured to drive the liquid crystal panel.

Herein, the driving unit includes a drive integrated circuit (IC) for applying signals to wires of the liquid crystal panel, and according to a method of packaging the drive IC in the liquid crystal panel, there are chip on glass (COG), tape carrier package (TCP), and chip on file (COF).

A COG method among them is a method for directly adhering a driving IC to an array substrate of a liquid crystal display device in order to directly connect an output electrode of the drive IC to a wire pad on the array substrate. Thus, the COG method has a simple structure so that manufacturing processes are simple and manufacturing costs are less.

SUMMARY

The present disclosure provides a display panel having a minimized area that a pad occupies and a display device including the same.

An embodiment of the inventive concept provides a display panel including: a substrate including a pixel area and a pad area; and a first conductive line and a second conductive line stacked on the substrate, wherein the first conductive line includes a first part disposed on the pixel area and a second part disposed on the pad area and the second conductive line includes a first part disposed on the pixel area and a second part disposed on the pad area, wherein the first part of the first conductive line and the first part of the second conductive line are parallel to each other; and the second part of the first conductive line and the second part of the second conductive line are overlapped vertically.

In an embodiment, a length of the second part of the first conductive line may be different from a length of the second part of the second conductive line.

In an embodiment, a length of the second part of the second conductive line may be shorter than a length of the second part of the first conductive line.

In an embodiment, the display panel may further include: a first pad disposed on an end part of the second part of the first conductive line and electrically connected to the first conductive line; and a second pad disposed on an end part of the second part of the second conductive line and electrically connected to the second conductive line, wherein the first pad and the second pad may be arranged in a line.

In an embodiment, the first conductive line may further include a third part disposed on the pad area and disposed between the first part and the second part; the second conductive line may further include a third part disposed on the pad area of the substrate and disposed between the first part and the second part; and the third part of the first conductive line and the third part of the second conductive line may not be overlapped vertically.

In an embodiment of the inventive concept, a display panel includes: a substrate including a pixel area and a pad area; a first conductive line and a second conductive line stacked on the pixel area of the substrate and extending in one direction on the pad area; a first pad disposed on the pad area of the substrate and disposed on an end part of the first conductive line; and a second pad disposed on the pad area of the substrate and disposed on an end part of the second conductive line, wherein the first pad and the second pad are arranged along the one direction.

In an embodiment, the first conductive line may include a first part disposed on the pad area; the second conductive line may include a second part disposed on the pad area; and the first part of the first conductive line and the second part of the second conductive line may be overlapped vertically.

In an embodiment, a length of the first part of the first conductive line may be different from a length of the second part of the second conductive line.

In an embodiment, the display panel may further include: a third conductive line disposed on the pixel area of the substrate and extending in the one direction on the pad area, wherein the third conductive line may include a third part disposed on the pad area; and a third pad disposed on the pad area and disposed on an end part of the third part of the third conductive line, wherein the third part of the third conductive line may not be overlapped vertical to the first part of the first conductive line and the second part of the second conductive line, and the third pad may be arranged in the one direction along the first pad and the second pad.

In an embodiment, an upper surface of the first pad may be disposed in a different level than an upper surface of the second pad.

In an embodiment, the upper surface of the first pad may be disposed in a lower level than the upper surface of the second pad.

In an embodiment, a thickness of the first pad may be identical to a thickness of the second pad.

In an embodiment, a thickness of the first pad may be different from a thickness of the second pad.

In an embodiment, a thickness of the first pad may be thicker than a thickness of the second pad.

In an embodiment of the inventive concept, a display device includes: a display panel including a substrate including a pixel area and pad area, a first conductive line and a second conductive line stacked on the substrate, and a first pad disposed on the pad area of the substrate and electrically connected to the first conductive line and a second pad disposed on the pad area of the substrate and electrically connected to the second conductive line; and a driving circuit mounted on the pad area of the substrate and electrically connected to the first conductive line and the second conductive line, wherein the first pad and the second pad are arranged in a line.

In an embodiment, the first conductive line may include a first part disposed on the pad area of the substrate; the second conductive line may include a second part disposed on the pad area of the substrate; and the first part may be overlapped vertical to the second part.

In an embodiment, the first conductive line may include a first part disposed on the pad area of the substrate; the second conductive line may include a second part disposed on the pad area of the substrate; and the first part may not be overlapped vertical to the second part.

In an embodiment, the display device may further include: a first bump disposed on one surface of the driving circuit and contacting the first pad; and a second bump disposed on the one surface of the driving circuit and contacting the second pad.

In an embodiment, a maximum thickness of the first bump may be thicker than a maximum thickness of the second bump.

DETAILED DESCRIPTION

The terms used in this specification are used only for explaining specific embodiments while not limiting the present invention. The terms of a singular form may include plural forms unless referred to the contrary. The meaning of “include,” “comprise,” “including,” or “comprising,” specifies a property, a region, a fixed number, a step, a process, an element and/or a component but does not exclude other properties, regions, fixed numbers, steps, processes, elements and/or components.

Additionally, embodiments described in this specification will be described with plan views sectional views, that is, ideal exemplary views of the inventive concept. In the drawings, the thicknesses of a layer and an area are exaggerated for effective description. Accordingly, shapes of the exemplary views may be modified according to manufacturing techniques and/or allowable errors. Therefore, the embodiments of the inventive concept are not limited to the specific shape illustrated in the exemplary views, but may include other shapes that may be created according to manufacturing processes. For example, an etched region illustrated as a rectangle may have rounded or curved features. Areas exemplified in the drawings have general properties, and are used to illustrate a specific shape of a semiconductor package region. Thus, this should not be construed as limited to the scope of the inventive concept.

FIG. 1is a plan view illustrating a part of a display device including a display panel according to an embodiment of the inventive concept.FIG. 2is a sectional view taken along a line I-I′ ofFIG. 1.FIG. 3is a plan view illustrating first to fifth conductive lines shown inFIG. 2.

Referring toFIGS. 1 and 2, a display device1may include a display panel10and a driving circuit200mounted on the display panel10. The display panel10may include a substrate100, conductive lines111,113,115,117, and119, and pads121,123,125,127, and129.

The substrate100may include a pixel area PXR and a pad area PR around the pixel area PXR. The substrate100may be a glass substrate or a plastic substrate including Polyethylen terephthalate (PET), Polyethylen naphthalate (PEN), or Polyimide.

A first conductive line111, a second conductive line113, a third conductive line115, a fourth conductive line117, and a fifth conductive line119may be sequentially stacked on the substrate100. The first conductive line111may be electrically connected to a first lower capacitor electrode (not shown). The second conductive line113may be disposed on the first conductive line111. The second conductive line113may be electrically connected to an upper capacitor electrode (not shown). The third conductive line115may be disposed on the second conductive line113. For example, the third conductive line115may correspond to a gate line or a data line. When the third conductive line115corresponds to a gate line, it may contact a gate electrode (not shown) of a thin film transistor for switching a pixel. When the third conductive line115corresponds to a data line, it may contact a source electrode (not shown) and a drain electrode (not shown) of a thin film transistor. The fourth conductive line117may be electrically connected to the third conductive line115in the pixel area PXR of the substrate100. For example, the fourth conductive lien117may correspond to a light blocking line for blocking light to a thin film transistor. The fifth conductive line119may be electrically connected to the fourth conductive line115in the pixel area PXR of the substrate100. For example, the fifth conductive line119may correspond to a reflective line for reflecting light provided to a panel.

From the plan view, the first to fifth conductive lines111,113,115,117, and119may be arranged in a first direction X and extend in a second direction Y intersecting the first direction X. The first conductive line111may include first to third parts PA1, PB1, and PC1. The second conductive line113may include first to third parts PA2, PB2, and PC2. The third conductive line115may include first to third parts PA3, PB3, and PC3. The fourth conductive line117may include first to third parts PA4, PB4, and PC4. Then, the fifth conductive line119may include first to third parts PA5, PB5, and PC5.

The first parts PA1, PA2, PA3, PA4, and PA5of the first to fifth conductive lines111,113,115,117, and119may be disposed on the pixel area PXR of the substrate100. The first parts PA1, PA2, PA3, PA4, and PA5of the first to fifth conductive lines111,113,115,117, and119may be parallel to each other. The second parts PB1, PB2, PB3, PB4, and PB5and the third parts PC1, PC2, PC3, PC4, and PC5of the first to fifth conductive lines111,113,115,117, and119may be disposed on the pad area PR of the substrate100.

In more detail, referring toFIGS. 1 and 3, the second part PB1of the first conductive line111may be disposed between the first part PA1and the third part PC1of the first conductive line111. The second part PB2of the second conductive line113may be disposed between the first part PA2and the third part PC2of the second conductive line113. The second part PB3of the third conductive line115may be disposed between the first part PA3and the third part PC3of the third conductive line115. The second part PB4of the fourth conductive line117may be disposed between the first part PA4and the third part PC4of the fourth conductive line117. Then, the second part PB5of the fifth conductive line119may be disposed between the first part PA5and the third part PC5of the fifth conductive line119.

From the plan view, the second parts PB1, PB2, PB3, PB4, and PB5of the first to fifth conductive lines111,113,115,117, and119may not be overlapped vertical to each other, and the third parts PC1, PC2, PC3, PC4, and PC5of the first to fifth conductive lines111,113,115,117, and119may be overlapped vertical to each other.

The third parts PC1, PC2, PC3, PC4, and PC5of the first to fifth conductive lines111,113,115,117, and119may have different lengths. As shown inFIG. 2, the lengths of the third parts PC1, PC2, PC3, PC4, and PC5of the first to fifth conductive lines111,113,115,117, and119may become shorter as they are progressively away from the upper surface of the substrate100.

In more detail, the third part PC2of the second conductive line113may be shorter than the third part PC1of the first conductive line111, the third part PC3of the third conductive line115may be shorter than the third part PC2of the second conductive line113, the third part PC4of the fourth conductive line117may be shorter than the third part PC3of the third conductive line115, and the third part PC5of the fifth conductive line119may be shorter than the third part PC4of the fourth conductive line117.

The pads121,123,125,127, and129may be disposed on one end parts of the first to fifth conductive lines111,113,115,117, and119. In more detail, the first pad121electrically connected to the first conductive line111may be disposed on one end part of the third part PC1of the first conductive line111and the second pad123electrically connected to the second conducive line113may be disposed on one end part of the third part PC2of the second conductive line113. The third pad125electrically connected to the third conductive line115may be disposed on one end part of the third part PC3of the third conductive line115and the fourth pad127electrically connected to the fourth conducive line117may be disposed on one end part of the third part PC4of the fourth conductive line117. Then, the fifth pad129electrically connected to the fifth conductive line119may be disposed on one end part of the third part PC5of the fifth conductive line119.

From the plan view, the first to fifth pads121,123,125,127, and129may be arranged along the second direction Y. For example, from the plan view, the first to fifth pads121,123,125,127, and129may be arranged in a line on the third part PC1of the first conductive line111.

Upper surfaces of the first to fifth pads121,123,125,127, and129that directly contact first to fifth bumps221,223,225,227, and229may be disposed in different levels. In more detail, the upper surface of the first pad121may be disposed lower than the upper surface of the second pad123, the upper surface of the second pad123may be disposed lower than the upper surface of the third pad125, the upper surface of the third pad125may be disposed lower than the upper surface of the fourth pad127, and the upper surface of the fourth pad127may be disposed lower than the upper surface of the fifth pad129. In one example, the thicknesses of the first to fifth pads121,123,125,127, and129may be identical to each other.

The first to fifth pads121,123,125,127, and129may include a metallic material (for example, Cu).

In one example, a plurality of conductive lines is disposed to be overlapped vertical to each other on the pad area PR of the substrate100, so that pads may be disposed in a line on the respective one end parts of the conductive lines. Accordingly, a larger number of pads may be disposed in a limited area.

A first interlayer insulation layer ILD1may be disposed between the first conductive line111and the second conductive line113. The first interlayer insulation layer ILD1may cover an upper surface of the first conductive line111and expose the upper surface of the first pad121. A second interlayer insulation layer ILD2may be disposed between the second conductive line113and the third conductive line115. The second interlayer insulation layer ILD2may cover an upper surface of the second conductive line113and a part of an upper surface of the first interlayer insulation layer ILD1and expose the upper surface of the second pad123. A third interlayer insulation layer ILD3may be disposed between the third conductive line115and the fourth conductive line117. The third interlayer insulation layer ILD3may cover an upper surface of the third conductive line115and a part of an upper surface of the second interlayer insulation layer ILD2and expose the upper surface of the third pad125. A fourth interlayer insulation layer ILD4may be disposed between the fourth conductive line117and the fifth conductive line119. The fourth interlayer insulation layer ILD4may cover an upper surface of the fourth conductive line117and a part of an upper surface of the third interlayer insulation layer ILD3and expose the upper surface of the fourth pad127. Then, a fifth interlayer insulation layer ILD5may be disposed on the fifth conductive line119in order to cover an upper surface of the fifth conductive line119and a part of an upper surface of the fourth interlayer insulation layer ILD4. The fifth interlayer insulation layer ILD5may expose the upper surface of the fifth pad129.

The first to fifth interlayer insulation layers ILD1, ILD2, ILD3, ILD4, and ILD5, for example, may include a silicon oxide layer or a silicon nitride layer.

The driving circuit200may be disposed on the pad area PR of the substrate100. The first to fifth bumps221,223,225,227, and229disposed one surface of the driving circuit200may be disposed in correspondence to the first to fifth pads121,123,125,127, and129. In more detail, the first bump221may contact the upper surface of the first pad121and the second bump223may contact the upper surface of the second pad123. The third bump225may contact the upper surface of the third pad125, the fourth bump227may contact the upper surface of the fourth pad127, and the fifth bump229may contact the upper surface of the fifth pad129.

One surfaces of the first to fifth bumps221,223,225,227, and229contacting one surface of the driving circuit200may be disposed in the same level, and other surfaces of the first to fifth bumps221,223,225,227, and229facing the one surfaces of the first to fifth bumps221,223,225,227, and229may be disposed in different levels.

In one example, the first to fifth bumps221,223,225,227, and229may have different thicknesses. In more detail, the maximum thickness T1of the first bump221may be thicker than the maximum thickness T2of the second bump223, and the maximum thickness T2of the second bump223may be thicker than the maximum thickness T3of the third bump225. Then, the maximum thickness T3of the third bump225may be thicker than the maximum thickness T4of the fourth bump227, and the maximum thickness T4of the fourth bump227may be thicker than the maximum thickness T5of the fifth bump229.

The first to fifth bumps221,223,225,227, and229may include a metallic material (for example, In, Sn, and Pb).

FIG. 4is a sectional view taken along a line I-I′ ofFIG. 1according to embodiments of the inventive concept. For concise description, like reference numerals refer to like components in a display device including the display panel described with reference toFIGS. 1 to 3, and overlapping descriptions are omitted.

Referring toFIG. 4, the thicknesses of the first to fifth pads121,123,125,127, and129may be different from each other. For example, a thickness t1of the first pad121may be thicker than a thickness t2of the second pad123, a thickness t2of the second pad123may be thicker than a thickness t3of the third pad125, a thickness t3of the third pad125may be thicker than a thickness t4of the fourth pad127, and a thickness t4of the fourth pad127may be thicker than a thickness t5of the fifth pad129.

In more detail, the first pad121may include five conductive layers that are sequentially stacked on the first conductive line111. The second pad123may include four conductive layers that are sequentially stacked on the second conductive line113. The third pad125may include three conductive layers that are sequentially stacked on the third conductive line115. The fourth pad127may include two conductive layers that are sequentially stacked on the fourth conductive line117. Then, the fifth pad129may include a single conductive layer.

FIG. 5is a plan view illustrating a part of a display device including a display panel according to an embodiment of the inventive concept.FIG. 6is a plan view illustrating first to fifth conductive lines shown inFIG. 5. For concise description, like reference numerals refer to like components in a display device including the display panel described with reference toFIGS. 1 to 3, and overlapping descriptions are omitted.

Referring toFIGS. 5 and 6, from the plan view, the third parts PC1, PC2, and PC3of the first to third conductive lines111,113, and115and the third part PC5of the fifth conductive line119may be overlapped vertical to each other. Then, from the plan view, the third part PC4of the fourth conductive line117may not be overlapped vertical to the third parts PC1, PC2, and PC3of the first to third conductive lines111,113, and115and the third part PC5of the fifth conductive line119. In more detail, from the plan view, the third part PC4of the fourth conductive line117may be spaced in the first direction X away from the third parts PC1, PC2, and PC3of the first to third conductive lines111,113, and115and the third part PC5of the fifth conductive line119.

The first pad121may be disposed on the third part PC1of the first conductive line111, the second pad123may be disposed on the third part PC2of the second conductive line113, the third pad125may be disposed on the third part PC3of the third conductive line115, the fourth pad127may be disposed on the third part PC4of the fourth conductive line117, and the fifth pad129may be disposed on the third part PC5of the fifth conductive line119. From the plan view, the first to fifth pads121,123,125,127, and129may be arranged along the second direction Y. In one example, the first to fifth pads121,123,125,127, and129may be arranged in a line.

In one example, during AC drive, in order to minimize an electrical interference between overlapping conductive lines, at least one (for example, a fourth conductive line) of first to fifth conductive lines may be disposed not to overlap the remaining conductive lines (for example, the first conductive line, the second conductive line, the third conductive line, and the fifth conductive line).

According to an embodiment of the inventive concept, as a plurality of conductive lines are disposed to be overlapped vertical to each other on a pad are of a substrate, so that pads disposed on one end parts of the conductive lines may be arranged in a line. Accordingly, a larger number of pads may be disposed in a limited area.