LOW-K DIELECTRIC INNER SPACER FOR GATE ALL AROUND TRANSISTORS

Semiconductor devices and methods of forming the same include forming a stack of alternating channel layers and sacrificial layers. The sacrificial layers are recessed relative to the channel layers. Inner spacers are formed at ends of the sacrificial layers with a process that preferentially forms dielectric material on the sacrificial layers relative to the channel layers. Source and drain structures are formed at ends of the channel layers. The sacrificial layers are etched away to expose surfaces of the channel layers. A gate stack is formed on and around the channel layers.

BACKGROUND

Technical Field

The present invention generally relates to transistor fabrication and, more particularly, to the fabrication of gate all around nanosheet and nanowire transistors that make use of low-k dielectric inner spacers between vertically adjacent channels.

Description of the Related Art

Nanosheet transistor devices (such as, e.g., nanosheet gate all around field effect transistors (FETs) may make use of nitride-based dielectric inner spacers to improve yield and to reduce parasitic capacitance. However, such nitride structures may have an undesirably high dielectric constant and, furthermore, often suffer from capillary effects that cause the inner spacers to take on a crescent shape that undercuts too far into the channel.

SUMMARY

A method of forming a semiconductor device includes forming a stack of alternating channel layers and sacrificial layers. The sacrificial layers are recessed relative to the channel layers. Inner spacers are formed at ends of the sacrificial layers with a process that preferentially forms dielectric material on the sacrificial layers relative to the channel layers. Source and drain structures are formed at ends of the channel layers. The sacrificial layers are etched away to expose surfaces of the channel layers. A gate stack is formed on and around the channel layers.

A method of forming a semiconductor device includes forming a stack of alternating channel layers and sacrificial layers. The sacrificial layers are recessed relative to the channel layers. The sacrificial layers and channel layers are oxidized with a low partial pressure of oxygen to form inner spacers at ends of the sacrificial layers from silicon dioxide with a purity between about 95% and about 100%. Source and drain structures are formed at ends of the channel layers. The sacrificial layers are etched away to expose surfaces of the channel layers. A gate stack is formed on and around the channel layers.

A semiconductor device includes vertically stacked channel layers. Inner spacers are positioned between vertically adjacent channel layers. A gate stack is formed between and around the channel layers. An interface between each inner spacer and the gate stack is flat.

DETAILED DESCRIPTION

Embodiments of the present invention provide gate all around field effect transistors (FETs) that make use of low-k dielectric spacers formed from oxides, oxynitrides, or other appropriate dielectric materials. Furthermore, the interface between the inner spacers and the channel structure(s) has a relatively flat, straight surface that does not cut into the channel structure(s). These inner spacers are furthermore formed with a high degree of purity in their material composition.

To accomplish this, the low-k dielectric is thermally oxidized in a manner that selectively forms dielectric material on particular structures due to, e.g., favorable thermodynamics. In one specific embodiment, silicon germanium sacrificial layers are recessed and the low-k dielectric material is selectively formed on the recessed sacrificial layers, with relatively little low-k dielectric material being formed on the ends of the channel layers. This difference in rate of formation of the low-k dielectric layer makes it possible to subsequently expose the channel ends for source and drain formation without substantially damaging the inner spacers.

Referring now to the drawings in which like numerals represent the same or similar elements and initially toFIG. 1, a step in the formation of a FET is shown. A semiconductor substrate102is layered with alternating layers of channel material104and sacrificial material106. The semiconductor substrate102may be a bulk-semiconductor substrate. It should be understood that the stack of channel layers104and sacrificial layers106can be sectioned into device regions, although only one such device region is shown herein. It is specifically contemplated that the alternating layers of channel material104and sacrificial material106are formed as sheets of material. It should be understood that, although nanosheet structures are handled specifically herein, the present embodiments may be applied to create nanowire or other structures as well.

In one specific embodiment, it is contemplated that the layers of channel material104may have a thickness between about 5 nm and about 10 nm and that the layers of sacrificial material106may have a thickness between about 7 nm and about 15 nm. As used herein, the term “nanosheet” refers to a structure that has a ratio of its cross-sectional width to its cross-sectional height greater than about 2:1, whereas the term “nanowire” refers to a structure that has a ratio of its cross-sectional width to its cross-sectional height less than about 2:1.

In one example, the bulk-semiconductor substrate may be a silicon-containing material. Illustrative examples of silicon-containing materials suitable for the bulk-semiconductor substrate include, but are not limited to, silicon, silicon germanium, silicon germanium carbide, silicon carbide, polysilicon, epitaxial silicon, amorphous silicon, and multi-layers thereof. Although silicon is the predominantly used semiconductor material in wafer fabrication, alternative semiconductor materials can be employed, such as, but not limited to, germanium, gallium arsenide, gallium nitride, cadmium telluride, and zinc selenide. Although not depicted in the present figures, the semiconductor substrate102may also be a semiconductor on insulator (SOI) substrate.

It is specifically contemplated that the alternating layers104and106are formed from different materials. In one particular embodiment, the layers of channel material104may be formed from, e.g., a silicon-containing semiconductor, with silicon itself being specifically contemplated, and the layers of sacrificial material may be formed from a silicon germanium composite, with a germanium concentration of about 40%. In one particular embodiment, the layers of channel material104may be about 9 nm thick and the layers of sacrificial material may be about 12 nm thick, but it should be understood that other thicknesses may be used in accordance with design needs and fabrication process limitations.

The layers of channel material and sacrificial material104and106may be formed on the substrate102by any appropriate deposition process. For example, the alternating layers may be formed by alternating deposition processes including, e.g., chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or gas cluster ion beam (GCIB) deposition. CVD is a deposition process in which a deposited species is formed as a result of chemical reaction between gaseous reactants at greater than room temperature (e.g., from about 25° C. about 900° C.). The solid product of the reaction is deposited on the surface on which a film, coating, or layer of the solid product is to be formed. Variations of CVD processes include, but are not limited to, Atmospheric Pressure CVD (APCVD), Low Pressure CVD (LPCVD), Plasma Enhanced CVD (PECVD), and Metal-Organic CVD (MOCVD) and combinations thereof may also be employed. In alternative embodiments that use PVD, a sputtering apparatus may include direct-current diode systems, radio frequency sputtering, magnetron sputtering, or ionized metal plasma sputtering. In alternative embodiments that use ALD, chemical precursors react with the surface of a material one at a time to deposit a thin film on the surface. In alternative embodiments that use GCIB deposition, a high-pressure gas is allowed to expand in a vacuum, subsequently condensing into clusters. The clusters can be ionized and directed onto a surface, providing a highly anisotropic deposition.

Referring now toFIG. 2, a step in the formation of a FET is shown. A dummy gate202or other sacrificial structure is formed over the stack of alternating layers. It is specifically contemplated that the dummy gate202. It is specifically contemplated that the dummy gate202may be formed from any material that is selectively etchable with respect to the channel material and the sacrificial material.

After formation of the dummy gate202, the stack of alternating layers is etched down in regions not covered by the dummy gate202. This etch can be performed using an anisotropic etch such as reactive ion etching (RIE). The etch can be performed in a single etch that removes material from both the channel layers104and the sacrificial layers106or may, alternatively, be performed using alternating etching processes that selectively affect the channel layers104and the sacrificial layers106in turn. As used herein, the term “selective” in reference to a material removal process denotes that the rate of material removal for a first material is greater than the rate of removal for at least another material of the structure to which the material removal process is being applied.

RIE is a form of plasma etching in which during etching the surface to be etched is placed on a radio-frequency powered electrode. Moreover, during RIE the surface to be etched takes on a potential that accelerates the etching species extracted from plasma toward the surface, in which the chemical etching reaction is taking place in the direction normal to the surface. Other examples of anisotropic etching that can be used at this point of the present invention include ion beam etching, plasma etching or laser ablation.

Referring now toFIG. 3, a step in the formation of a FET is shown. The layers of sacrificial material106are etched back relative to the layers of channel material104using a selective isotropic etch such as a wet or dry chemical etch. In one particular embodiment, hydrochloric acid Standard Clean 1 (“SC1,” also known colloquially as an “RCA® clean”) may be used to selectively etch silicon germanium material while leaving silicon layers relatively unaffected. The etch produces recesses304that may in one particular embodiment be about 6 nm deep.

Referring now toFIG. 4, a step in the formation of a FET is shown. A dielectric layer404is selectively grown on the exposed portions of the recessed layers of sacrificial material302. It is specifically contemplated that an oxidation process may be used to form silicon dioxide. Formation of the dielectric material on the recessed silicon germanium is thermodynamically favored over formation of the dielectric material on the exposed portions of channel material104, with a growth ratio of about 7:1. Thus, for every nanometer of dielectric growth from the channel layers104, there will be seven nanometers of dielectric growth from the recessed sacrificial layers302, filling the recesses304and bringing the surfaces roughly into line.

The oxidation process condenses silicon out of the silicon germanium layers, resulting in an effective increase in the concentration of germanium in the recessed sacrificial layers106. In particular, in an environment having a low partial pressure of oxygen (e.g., about 0.076 Torr) the lower Gibbs free energy of silicon results in selective oxidation of the silicon in silicon germanium. At a given oxidation temperature, if the partial pressure of oxygen is high enough, germanium precipitates in the oxidation process and forms a mixture of silicon dioxide and germanium dioxide, which is physically and electrically unstable. If the partial pressure of oxygen is fixed below about 0.1 Torr and oxidation temperature is between about 400° C. and about 600° C., then the oxidation of the channel layers104can be avoided, as silicon oxidizes less at low temperatures. This results in the different rates of silicon dioxide formation on the surfaces of the channel layers104and the recessed sacrificial layers106.

Thus, in an embodiment where the sacrificial material starts with a germanium concentration of about 40%, after the condensation process the recessed sacrificial layers402may have a germanium concentration of about 60%. This advantageously increases the etch selectivity between the condensed layers of sacrificial material402and the layers of channel material104. The oxidation process smooths any crescent shape that may have been formed by previous steps, producing a flat interface.

It should be understood that the dielectric layer404can be formed with a very high degree of material purity in this process. In embodiments where the dielectric layer404is formed from silicon dioxide on a silicon germanium surface, the material of the dielectric layer404will be between 95% and 100% pure silicon dioxide if the germanium concentration in the recessed sacrificial layers302is about 40%. If the germanium concentration of the recessed sacrificial layers302is lower than 40%, then the material of the dielectric layer404will have be between about 99% and about 100% pure silicon dioxide. These purities are significantly higher than would otherwise be achievable.

Referring now toFIG. 5, an optional step in the formation of a FET is shown. The dielectric layer404may optionally be nitridated using, for example, a thermal or plasma nitridation process. The nitridation process may be used to, for example, alter the dielectric constant of the dielectric layer404. In an embodiment where the dielectric layer is formed from silicon dioxide (having a dielectric constant of about 3.9), nitridation will produce silicon oxynitride (having a dielectric constant of about 5). In one specific embodiment, the nitridation may be performed at a temperature of about 700° C. and a pressure of about 740 Torr. This nitridation process can be advantageous in some embodiments because silicon oxynitride is more stable than silicon dioxide in subsequent processes. If this optional step is used, then the silicon oxynitride will have a purity similar to that for silicon dioxide inner spacers as discussed above.

Referring now toFIG. 6, a step in the formation of a FET is shown. The dielectric layer404is etched back to expose the ends of the layers of channel material104. This process separates the dielectric layer404into inner spacers602, each in a separate recess304. Any appropriate selective etch may be used. In some embodiments, a timed, isotropic, wet or dry chemical etch, such as by dilute hydrofluoric acid, may be used to selectively remove material from the dielectric layers304while leaving the inner spacers602intact. In other embodiments, an anisotropic, directional etch may be used to remove dielectric material from the sides of the stack of layers without etching laterally into the inner spacers602.

Referring now toFIG. 7, a step in the formation of a FET is shown. Source and drain regions702are formed on respective exposed ends of layers of channel material104. It is specifically contemplated that the source and drain regions702may be formed by epitaxial growth, though it should be understood that other deposition processes may be employed instead. The source and drain regions702may be formed from, e.g., a doped semiconductor material such as p-type or n-type doped silicon, but it should be understood that any appropriately doped semiconductor material may be used instead. The material formed at the sides of each of the layers of channel material104merges together to form a single source/drain structure. Although these structures are shown as being rectangular in shape for simplicity, it should be understood that the source/drain structures702will take on a shape in accordance with the process of their formation and, in the case of epitaxial growth, in accordance with the crystal orientation.

The term “epitaxial growth” means the growth of a semiconductor material on a deposition surface of a semiconductor material, in which the semiconductor material being grown has substantially the same crystalline characteristics as the semiconductor material of the deposition surface. The term “epitaxial material” denotes a material that is formed using epitaxial growth. In some embodiments, when the chemical reactants are controlled and the system parameters set correctly, the depositing atoms arrive at the deposition surface with sufficient energy to move around on the surface and orient themselves to the crystal arrangement of the atoms of the deposition surface. Thus, in some examples, an epitaxial film deposited on a {100} crystal surface will take on a {100} orientation. In the present embodiments the epitaxial growth process may be selective to the channel material, such that no material is grown on the surfaces of the dummy gate202or the inner spacers602.

Source/drain epitaxy can be done by ultrahigh vacuum chemical vapor deposition (UHVCVD), rapid thermal chemical vapor deposition (RTCVD), metalorganic chemical vapor deposition (MOCVD), low-pressure chemical vapor deposition (LPCVD), limited reaction processing CVD (LRPCVD), molecular beam epitaxy (MBE), or any other appropriate process. Epitaxial materials may be grown from gaseous or liquid precursors. Epitaxial materials may be grown using vapor-phase epitaxy (VPE), molecular-beam epitaxy (MBE), liquid-phase epitaxy (LPE), or other suitable process. Epitaxial silicon, silicon germanium SiGe, and/or carbon-doped silicon (Si:C) silicon can be doped during deposition (in-situ doped) by adding dopants, n-type dopants (e.g., phosphorus or arsenic) or p-type dopants (e.g., boron or gallium), depending on the type of transistor. The dopant concentration in the source/drain can range from about 1×1019cm−3to about 2×1021cm−3, or preferably between 2×1020cm−3and 1×1021cm−3. When Si:C is epitaxially grown, the Si:C layer may include carbon in the range of 0.2 to 3.0%. When silicon germanium is epitaxially grown, the silicon germanium may have germanium content in the range of 5% to 80%, or preferably between 20% and 60%.

Referring now toFIG. 8, a step in forming a FET is shown. The dummy gate202is etched away. The recessed layers of condensed sacrificial material402are then also etched away, leaving the top and bottom surfaces of the layers of channel material104exposed in gap802. The layers of channel material104remain separated by inner spacers602and are supported by their ends. Any appropriate wet or dry chemical etch or etches may be used to remove the dummy gate202and the recessed layers of condensed sacrificial material402. One exemplary etch that may be used is a gaseous hydrochloric acid etch that selectively removes silicon germanium while leaving silicon channel layers relatively untouched.

Referring now toFIG. 9, a step in forming a FET is shown. A gate stack is formed from a gate dielectric902and a gate conductor904. The gate dielectric902may be formed by any conformal deposition process including, e.g., CVD or ALD and may include any appropriate dielectric material. At this stage, a passivating layer (not shown) may be deposited over the device and electrical contacts (not shown) may be formed to the source and drain structures702and to the gate conductor904.

It is specifically contemplated that the gate dielectric902may be formed from a high-k dielectric material, which is defined as a material having a dielectric constant k that is greater than the dielectric constant of silicon dioxide. Examples of high-k materials include but are not limited to metal oxides such as hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. The high-k dielectric material may further include dopants such as lanthanum and aluminum.

The gate conductor904may be, for example, a metal or metallic conductive material including, e.g., tungsten, nickel, titanium, molybdenum, tantalum, copper, platinum, silver, gold, ruthenium, iridium, rhenium, rhodium, and alloys thereof. The gate conductor may alternatively include a doped semiconductor material such as, e.g., doped polysilicon. When a combination of conductive elements is employed, an optional diffusion barrier material such as tantalum nitride or tungsten nitride may be formed between the conductive materials.

Referring now toFIG. 10, a method of forming a FET is shown. Block1002forms the layers of channel material104and the layers of sacrificial material106on a substrate102. The layers may be formed by, e.g., epitaxial growth or by any other appropriate deposition process. As noted above, it is specifically contemplated that the channel material may be silicon and that the sacrificial material may be silicon germanium with a germanium concentration of about 40%. Block1004forms dummy gate202by depositing a layer of dummy gate material (e.g., polysilicon) and using a photolithographic patterning process to define the dummy gate202and to etch away remaining dummy gate material. Block100-6then patterns the layers of channel material104and the layers of sacrificial material106using one or more anisotropic etches such as, e.g., an appropriate RIE.

Block1008recesses the layers of sacrificial material106relative to the layers of channel material104using a selective, isotropic etch. Block1010then forms dielectric layers404on exposed ends of the layers of channel material104and the recessed layers of the sacrificial material302using a formation process that favors deposition on the recessed layers of sacrificial material302(e.g., an oxidation process with a low partial pressure of oxygen). Thus, in embodiments that use silicon as the channel material and silicon germanium as the sacrificial material, deposition from surfaces of the sacrificial material may be accomplished at a rate about seven times greater than deposition from surfaces of the channel material. The dielectric layers404that result have a particularly sharp and flat interface with the recessed layers of sacrificial material302, avoiding the formation of interfaces with a crescent shape. Block1012optionally nitridates the dielectric layers404using, e.g., an ammonia anneal.

Block1014etches back the dielectric layers404to expose the ends of the layers of channel material104. Block1016then forms source and drain structures702in contact with the ends of the layers of channel material104by, for example, epitaxial growth with in situ doping. Block1018etches away the dummy gate202and block1020etches away the recessed layers of condensed sacrificial material402that resulted from forming the dielectric layers404. Block1022then forms a gate stack on the exposed surfaces of the layers of channel material104, for example by forming a high-k dielectric layer902and a gate conductor by any appropriate conformal deposition process (e.g., CVD). Block1024forms a passivating layer (not shown) over the gate stack and source/drain structures702. Block1026forms electrical contacts (not shown) to the source/drain structures702and the gate conductor904by etching holes through the passivating layer and depositing an appropriate conductive material.

Having described preferred embodiments of low-k dielectric inner spacer for gate all around transistors (which are intended to be illustrative and not limiting), it is noted that modifications and variations can be made by persons skilled in the art in light of the above teachings. It is therefore to be understood that changes may be made in the particular embodiments disclosed which are within the scope of the invention as outlined by the appended claims.