Electronic component

An electronic component includes: a capacitor body; first and second external electrodes disposed on a mounting surface of the capacitor body to be spaced apart from each other; and first and second connection terminals including an insulator, electrically connected to the first and second external electrodes, respectively, through land patterns each disposed on upper and lower surfaces thereof and electrically connected to each other, and having first and second bridge portions protruding so as to face each other in the length direction of the capacitor body, respectively.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application claims the benefit of priority to Korean Patent Application No. 10-2018-0046157 filed on Apr. 20, 2018 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

BACKGROUND

The present disclosure relates to an electronic component.

2. Description of Related Art

In recent electronic devices, as attempts to reduce the noise of equipment components has been ongoing, acoustic noise generated in a multilayer ceramic capacitor (MLCC) may become more prominent.

Since a dielectric material of a multilayer capacitor has piezoelectric properties, the multilayer ceramic capacitor may be synchronized with an applied voltage to thereby be deformed.

When a period of the applied voltage is within an audio frequency band, the displacement may become vibrations to thereby be transferred to a board through solders, and vibrations of the board may be experienced as sound. This sound, known as acoustic noise, is a problem in electronic devices.

The acoustic noise problem is that when an operating environment of a device is quiet, a user may experience acoustic noise as abnormal noise and may believe that a device is faulty, or when acoustic noise overlaps an audio output in a device having an audio circuit, quality of the device may be deteriorated.

Further, separately from acoustic noise recognized by the human ear, when piezoelectric vibrations of the multilayer capacitor are generated in a high frequency region of 20 kHz or more, the piezoelectric vibrations may cause malfunctioning of various sensors used in information technology (IT) and industrial/electric fields.

SUMMARY

An aspect of the present disclosure may provide an electronic component capable of decreasing acoustic noise in an audio frequency region of 20 kHz or less and high frequency vibrations of 20 kHz or more.

According to an aspect of the present disclosure, an electronic component may include: a capacitor body; first and second external electrodes disposed on a mounting surface of the capacitor body to be spaced apart from each other; and first and second connection terminals formed of an insulator, connected to the first and second external electrodes, respectively, through land patterns respectively formed on upper and lower surfaces thereof and electrically connected to each other, and having first and second bridge portions protruding so as to face each other in the length direction of the capacitor body, respectively.

The first connection terminal may include a first land pattern formed on a surface of the first connection terminal facing the first external electrode, a second land pattern formed on a surface thereof opposing the first land pattern, and a first conductive pattern formed on at least a portion of a surface thereof connecting the first and second land patterns to each other and electrically connecting the first and second land patterns to each other, and the second connection terminal may include a third land pattern formed on a surface of the second connection terminal facing the second external electrode, a fourth land pattern formed on a surface thereof opposing the third land pattern, and a second conductive pattern formed on at least a portion of a surface thereof connecting the third and fourth land patterns to each other and electrically connecting the third and fourth land patterns to each other.

At least one first and second cut portions may be formed in surfaces of the first and second connection terminals opposing each other in the length direction of the capacitor body, respectively.

Cut portions may be further formed in surfaces of the first and second connection terminals in the width direction of the capacitor body.

First and second solder accommodating portions may be provided on the first and second external electrodes toward the mounting surface of the capacitor body by the first and second cut portions, respectively.

The first connection terminal may include a first land pattern formed on a surface of the first connection terminal facing the first external electrode, a second land pattern formed on a surface thereof opposing the first land pattern, the first cut portion formed on a portion of the surface thereof connecting the first and second land patterns to each other, and a first conductive pattern formed on the first cut portion and electrically connecting the first and second land patterns to each other, and the second connection terminal may include a third land pattern formed on a surface of the second connection terminal facing the second external electrode, a fourth land pattern formed on a surface thereof opposing the third land pattern, the second cut portion formed on a portion of the surface thereof connecting the third and fourth land patterns to each other, and a second conductive pattern formed on the second cut portion and electrically connecting the third and fourth land patterns to each other.

The first conductive pattern may be formed on an entire surface of the first connection terminal connecting the first and second land patterns to each other or a portion of the surface including the first cut portion, and the second conductive pattern may be formed on an entire surface of the second connection terminal connecting the third and fourth land patterns to each other or a portion of the surface including the second cut portion.

The electronic component may further include plating layers formed on surfaces of the first and second external electrodes.

The capacitor body may include a plurality of dielectric layers and a plurality of first and second internal electrodes alternately disposed with respective dielectric layers interposed therebetween and has first and second surfaces opposing each other and third and fourth surfaces connected to the first and second surfaces and opposing each other, and one ends of the first and second internal electrodes may be exposed to the third and fourth surfaces of the capacitor body, respectively.

The first and second external electrodes may respectively include: first and second connection portions disposed on the third and fourth surfaces of the capacitor body, respectively, and first and second band portions extended from the first and second connection portions to portions of the first surface of the capacitor body and connected to the first and second connection terminals, respectively.

DETAILED DESCRIPTION

FIG. 1is a perspective view schematically illustrating an electronic component according to an exemplary embodiment in the present disclosure,FIG. 2is an exploded perspective view ofFIG. 1,FIGS. 3A and 3Bare plan views illustrating first and second internal electrodes of the electronic component according to the exemplary embodiment in the present disclosure, respectively, andFIG. 4is a cross-sectional view taken along line I-I′ ofFIG. 1.

Referring toFIGS. 1 through 4, an electronic component100according to the exemplary embodiment in the present disclosure may include a capacitor body110, first and second external electrodes131and132disposed on amounting surface of the capacitor body110to be spaced apart from each other, and first and second connection terminals141and142having first and second bridge portions143and144, respectively.

Hereinafter, directions of a capacitor body110will be defined in order to clearly describe exemplary embodiments in the present disclosure. X, Y, and Z illustrated in the accompanying drawings refer to a length direction, a width direction, and a thickness direction of the capacitor body110, respectively. Here, in the present exemplary embodiment, the thickness direction may be the same as a stacking direction in which dielectric layers are stacked.

The capacitor body110may be formed by stacking a plurality of dielectric layers111in the Z direction and sintering the stacked dielectric layers, and include the plurality of dielectric layers111and first and second internal electrodes121and122alternately disposed with respective dielectric layers111interposed therebetween in the Z direction.

In addition, covers112and113having a predetermined thickness may be formed on both sides of the capacitor body in the Z direction, respectively.

Here, respective adjacent dielectric layers111of the capacitor body110may be integrated with each other so that boundaries therebetween are not readily apparent.

The capacitor body110may have an approximately hexahedral shape. However, a shape of the capacitor body110is not limited thereto.

In the present disclosure, for convenience of explanation, both surfaces of the capacitor body110opposing each other in the Z direction may be defined first and second surfaces1and2, both surfaces of the capacitor body110connected to the first and second surfaces1and2and opposing each other in the X direction may be defined as third and fourth surfaces3and4, and both surfaces of the capacitor body110connected to the first and second surfaces1and2and the third and fourth surfaces3and4and opposing each other in the Y direction may be defined as fifth and sixth surfaces5and6. In the present exemplary embodiment, the first surface1of the capacitor body may be the mounting surface.

The dielectric layer111may contain a ceramic material having high permittivity, for example, a barium titanate (BaTiO3) based ceramic powder, or the like. However, the material of the dielectric layer is not limited thereto.

In addition, the dielectric layer111may further contain a ceramic additive, an organic solvent, a plasticizer, a binder, a dispersant, and the like, in addition to the ceramic powder. As the ceramic additive, for example, a transition metal oxide or carbide, a rare earth element, magnesium (Mg), aluminum (Al), or the like, may be used.

The first and second internal electrodes121and122, which are electrodes applied with different polarities, may be alternately disposed to face each other in the Z direction with respective dielectric layers111interposed, and one ends of the first and second internal electrodes121and122may be exposed to the third and fourth surfaces3and4of the capacitor body110, respectively.

Here, the first and second internal electrodes121and122may be electrically insulated from each other by the dielectric layer111disposed therebetween.

End portions of the first and second internal electrodes121and122alternately exposed to the third and fourth surfaces3and4of the capacitor body110as described above may be electrically connected to first and second external electrodes131and132disposed on the third and fourth surfaces3and4of the capacitor body110to be described below.

Here, the first and second internal electrodes121and122may be formed of a conductive metal, for example, a material such as nickel (Ni), a nickel (Ni) alloy, or the like. However, materials of the first and second internal electrodes121and122are not limited thereto.

According to the configuration as described above, when predetermined voltages are applied to the first and second external electrodes131and132, electric charges may be accumulated between the first and second internal electrodes121and122facing each other.

Here, capacitance of the electronic component100may be in proportion to an overlapping area between the first and second internal electrodes121and122overlapping each other in the Z direction.

The first and second external electrodes131and132may be disposed on the first surface1, the mounting surface, of the capacitor body110to be spaced apart from each other, provided with voltages having different polarities, respectively, and electrically connected to the exposed end portions of the first and second internal electrodes121and122, respectively.

If necessary, plating layers may be further formed on surfaces of the first and second external electrodes131and132as described above.

For example, the first and second external electrodes131and132may include first and second conductive layers, first and second nickel (Ni) plating layers formed on the first and second conductive layers, and first and second tin (Sn) plating layers formed on the first and second nickel (Ni) plating layers, respectively.

The first external electrode131may include a first connection portion131aand a first band portion131b.

The first connection portion131amay be a portion formed on the third surface3of the capacitor body110and electrically connected to the first internal electrode121, and the first band portion131bmay be a portion extended from the first connection portion131ato a portion of the first surface1, the mounting surface, of the capacitor body110to thereby be connected to the first connection terminal141.

Here, if necessary, the first band portion131bmay be further extended to portions of the second surface2and fifth and sixth surfaces5and6of the capacitor body110for the purpose of improving adhesion strength, or the like.

The second external electrode132may include a second connection portion132aand a second band portion132b.

The second connection portion132amay be a portion formed on the fourth surface4of the capacitor body110and electrically connected to the second internal electrode122, and the second band portion132bmay be a portion extended from the second connection portion132ato a portion of the first surface1, the mounting surface, of the capacitor body110to thereby be connected to the second connection terminal142.

Here, if necessary, the second band portion132bmay be further extended to portions of the second surface2and fifth and sixth surfaces5and6of the capacitor body110for the purpose of improving adhesion strength, or the like.

In the present exemplary embodiment, the first and second connection terminals141and142may be disposed to correspond to the first and second band portions131band132bof the first and second external electrodes131and132formed on the first surface1of the capacitor body110, respectively.

That is, the electronic component100is a structure in which a multilayer capacitor is adhered to small board-type first and second connection terminals141and142positioned to X-Y surfaces of the first and second external electrodes131and132to be spaced apart from each other, respectively.

The first and second connection terminals141and142may be formed of an insulator such as FR-4, F-PCB, a ceramic material, or the like.

Further, the first and second connection terminals may each have conductor land patterns1410and1420electrically connected to each other on upper and lower surfaces thereof so as to be connected to the first and second external electrodes131and132, respectively. The land patterns as described above may serve as a signal terminal and a ground (GND) terminal.

More specifically, the first connection terminal141according to the present exemplary embodiment may include a first land pattern1410aformed on a surface of the first connection terminal141facing the first external electrode131, a second land pattern1410bformed on a surface thereof opposing the first land pattern, and a first conductive pattern1410cformed on at least a portion of a surface thereof connecting the first and second land patterns1410aand1410bto each other.

Further, the second connection terminal142may include a third land pattern1420aformed on a surface of the second connection terminal142facing the second external electrode132, a fourth land pattern1420bformed on a surface thereof opposing the third land pattern1420a, and a second conductive pattern1420cformed on at least a portion of a surface thereof connecting the third and fourth land patterns1420aand1420bto each other.

Therefore, the land patterns1410aand1410bon the upper and lower surfaces of the first connection terminal141described above may be electrically connected to each other through the first conductive pattern1410c, and the land patterns1420aand1420bon the upper and lower surfaces of the second connection terminal142described above may be electrically connected to each other through the second conductive pattern1420c.

The first and second connection terminals141and142may have the first and second bridge portions143and144, respectively.

The first and second bridge portions143and144may be formed of an insulator and protrude so as to face each other in the X direction. The first and second bridge portions143and144may be formed of an insulator such as FR-4, F-PCB, a ceramic material, or the like. The first and second bridge portions143and144may have an elasticity.

Here, a conductor pattern or land pattern may be formed on portions of the first and second bridge portions143and144but is not entirely formed on the first and second bridge portions143and144.

Therefore, the first and second bridge portions143and144may be formed by easily cutting and separating connection terminals from a base substrate with respect to massive connection terminals having various patterns, thereby significantly decrease a lead time.

A plurality of connection terminals are manufactured on a single base substrate by printing and then separated into individual products to thereby be used. In this case, a bridge portion may be used as a cut portion for separating each of the connection terminals from the base substrate. Therefore, the connection terminal may be rapidly separated from the base substrate, such that an effect of shortening a manufacturing time at the time of manufacturing a final product may be expected.

Further, a width of the first and second bridge portions143and144in the Y direction may be narrower than that of the first and second connection terminals141and142in the Y direction.

Therefore, space portions may be provided at both sides of the first and second bridge portions143and144in the Y direction, and since these space portions may serve as solder accommodating portions in which a solder is accommodated at the time of mounting the electronic component on a board, a height of the solder may be decreased, and thus acoustic noise may be decreased.

FIG. 5is a perspective view schematically illustrating an electronic component according to another exemplary embodiment in the present disclosure, andFIG. 6is a cross-sectional view taken along line II-II′ ofFIG. 5.

Referring toFIGS. 5 and 6, first and second connection portions141′ and142′ according to another exemplary embodiment in the present disclosure may have at least one first and second cut portions141aand142a, respectively.

Therefore, first and second solder accommodating portions161and162may be provided on the first and second band portions131band132bof the first and second external electrodes131and132toward the first surface, the mounting surface, of the capacitor body110by the first and second cut portions141aand142a.

In the present exemplary embodiment, the first and second cut portions141aand142amay be formed on surfaces of the first and second connection portions141′ and142′ opposing each other in the X direction, respectively. Here, the first and second cut portions141aand142amay be formed to be curved.

Further, in the first connection terminal141′, a first conductive pattern may be formed on an entire surface of the first connection terminal141′ connecting the first and second land patterns1410aand1410bto each other or formed on a portion of the surface thereof, including the first cut portion141a, and in the second connection terminal142′, the second conductive pattern may be formed on the entire surface connecting the third and fourth land patterns1420aand1420bto each other or formed on a portion of the surface, including the second cut portion142a.

More specifically, the first connection terminal141′ according to the present exemplary embodiment may include a first land pattern1410aformed on a surface of the first connection terminal141′ facing the first external electrode131, a second land pattern1410bformed on a surface thereof opposing the first land pattern1410a, the first cut portion141aformed on a portion of the surface thereof connecting the first and second land patterns1410aand1410bto each other, and a first conductive pattern1410cformed on the first cut portion141aand electrically connecting the first and second land patterns to each other.

Further, the second connection terminal142′ may include a third land pattern1420aformed on a surface of the second connection terminal142′ facing the second external electrode132, a fourth land pattern1420bformed on a surface thereof opposing the third land pattern1420a, the second cut portion142aformed on a portion of the surface thereof connecting the third and fourth land patterns1420aand1420bto each other, and a second conductive pattern1420cformed on the second cut portion142aand electrically connecting the third and fourth land patterns1420aand1420bto each other.

That is, the first and second cut portions141aand142amay serve as solder pockets trapping molten solder, or the like, used at the time of mounting the electronic component according to the present exemplary embodiment on a board, or the like, and prevent the solder from being formed toward the upper surface of the capacitor body110to suppress vibrations of the capacitor body110from being transferred to the board. Therefore, acoustic noise may be decreased.

FIG. 7is a plan view illustrating another example of a connection terminal according to the present disclosure.

Referring toFIG. 7, in first and second connection terminals141″ and142″ according to another exemplary embodiment in the present disclosure, cut portions141b,141c,142b, and142cmay be further formed in both surfaces of the capacitor body110in the Y direction corresponding to the width direction.

Therefore, an adhesion area between connection terminals and external electrodes may be decreased as compared to the above-mentioned exemplary embodiment, but areas of solder accommodating portions may be further increased, such that formation of a solder fillet may be further suppressed at the time of mounting the electronic component on a board. Therefore, acoustic noise may be further decreased.

FIG. 8is a plan view illustrating another example of a connection terminal according to the present disclosure.

Referring toFIG. 8, in first and second connection terminals141′″ and142′″ according to another exemplary embodiment in the present disclosure, a plurality of cut portions1411,1412,1421, and1422may be formed in both surfaces of the capacitor body110in the X direction corresponding to the length direction.

Therefore, since formation of solder fillets at the time of mounting the electronic component on a board may be further suppressed by increasing an area of solder accommodating portions, acoustic noise may be further decreased.

Although a case in which two cut portions are formed in one surface of each of the connection terminals in the length direction is illustrated and described inFIG. 8, the cut portions are not limited thereto, and the number of cut portion may be changed depending on the purpose.

When voltages having different polarities are applied to the first and second external electrodes131and132formed on the electronic component in a state in which the electronic component100is mounted on a board, the capacitor body110may be expanded and contracted in the Z direction due to an inverse piezoelectric effect of the dielectric layers111, and both end portions of the first and second external electrodes131and132may be contracted and expanded as opposed to the expansion and the contraction of the capacitor body110in the Z direction due to a Poisson effect.

This contraction and expansion may generate vibrations. In addition, the vibrations may be transferred from the first and second external electrodes131and132to the board. Therefore, sound may be radiated from the board, which becomes the acoustic noise.

Here, solder formed between the first and second external electrodes131and132of the electronic component and first and second pads formed on one surface of the board may be formed toward the second surface2of the capacitor body110to have a predetermined height, such that the vibrations generated from the electronic component100may be significantly transferred to the board.

However, in the present exemplary embodiment, piezoelectric vibrations transferred to the board through the first and second external electrodes131and132of the electronic component may be absorbed due to elasticity of the first and second connection terminals141and142, such that acoustic noise may be decreased.

Further, first and second solder accommodating portions provided by the first and second cut portions141aand142aof the first and second connection terminals141and142, respectively, may serve as the solder pockets that may trap the solder on the first surface of the capacitor body110.

Therefore, a piezoelectric vibration transfer path of the electronic component100may be blocked, and the solder fillets and a maximum displacement point in the capacitor body110may be spaced apart from each other, such that an acoustic noise decreasing effect may be significantly improved as compared to an electronic component according to the related art.

According to the present exemplary embodiment, a vibration amount of the piezoelectric vibrations of the multilayer electronic component transferred to the board at an audio frequency within 20 kHz of the multilayer electronic component may be effectively suppressed by an acoustic noise decreasing structure described above.

Therefore, high frequency vibrations of the multilayer electronic component may be decreased to prevent malfunctions of sensors that may be caused by high frequency vibrations of 20 kHz or more of the electronic component in information technology (IT) or industry/electrical component fields, and accumulation of internal fatigue of the sensors due to vibrations for a long period of time may be suppressed.

As set forth above, according to exemplary embodiments in the present disclosure, there is an effect of decreasing acoustic noise of the multilayer electronic component in an audio frequency region of 20 kHz or less and a high-frequency vibration of 20 kHz or more.