Photonics chips and semiconductor products having angled optical fibers

The disclosed subject matter relates generally to photonic integrated circuit chips, semiconductor assemblies or packagings, and a method of forming the same. More particularly, the present disclosure relates to placement of optical fibers on a photonics chip, and a semiconductor assembly including the photonics chip.

FIELD OF THE INVENTION

The disclosed subject matter relates generally to integrated circuit chips and semiconductor products for photonics applications. More particularly, the present disclosure relates to photonics chips having optical fibers angled with respect to edges of the chips. The present disclosure also relates to semiconductor products having those photonic chips and a method of forming the same.

BACKGROUND

Silicon photonics is a platform for potentially revolutionary advances in the fields of telecommunications, data communications, medical technology, security, quantum computing, and sensing. Silicon photonics has the potential to realize small, highly integrated, photonics sub-systems that leverage off the decades of silicon fabrication experience, technology, and scalability to gain access to the full potential of the silicon platform, i.e. silicon photonics for high-speed signaling and sensing, and complimentary metal-oxide semiconductor (CMOS) electronics for subsequent logical operations and computations. Such multi-chip integration also allows for the bridging of different functional technologies, such as micro-electro-mechanical systems (MEMS), III-V materials, non-CMOS application-specific integrated circuits (ASIC), etc.

Electromagnetics waves (e.g., light waves) can be transmitted from an external laser source into a photonics chip via a transmission medium, such as an optical fiber or optical fiber arrays. The development of small, efficient optical transmission lines, such as optical fibers, has led to widespread use of optical communication in many applications requiring, long distance and/or high data rate communication (e.g, telecommunications). Fiber optic transmission lines provide low cost, compact, low electromagnetic interference, and high-speed data transmission over significant distances.

SUMMARY

In an aspect of the present disclosure, there is provided a photonics integrated circuit (PIC) chip including a substrate having four edges, grooves defined on the substrate, the grooves include at least one groove positioned at each of the four edges of the substrate, in which the grooves form an acute angle with the respective edges of the substrate, and at least one optical fiber positioned on at least one of the four edges of the substrate, in which the at least one optical fiber is in one of the grooves.

In another aspect of the present disclosure, there is provided a semiconductor product including a first PIC chip and a second PIC chip above the first PIC chip. The first PIC chip includes a substrate having four edges, grooves defined on the substrate, the grooves include at least one groove positioned at each of the four edges of the substrate, in which the grooves form an acute angle with the respective edges of the substrate, at least one optical fiber positioned on at least one of the four edges of the substrate, in which the at least one optical fiber is in the one of the grooves.

In yet another aspect of the present disclosure, there is provided a method of forming a semiconductor product, the method including forming a PIC chip, the PIC chip including a substrate having four edges, forming grooves on the substrate, the grooves include at least one groove positioned at each of the four edges of the substrate, in which the grooves form an acute angle with the respective edges of the substrate, and positioning at least one optical fiber on at least one of the four edges of the substrate, in which the at least one optical fiber is in one of the grooves.

DETAILED DESCRIPTION

Various illustrative embodiments of the present disclosure are described below. The embodiments disclosed herein are exemplary and not intended to be exhaustive or limiting to the present disclosure.

Referring toFIG.1, an example of an IC chip100for photonics application is shown. The IC chip100may be a photonics integrated circuit (PIC) chip. The PIC chip includes a substrate102having four edges102a,102b,102c,102d. The substrate102may have a single crystalline structure, and may include any semiconductor material, such as silicon, germanium, silicon germanium (SiGe), silicon carbide, and those consisting essentially of III-V compound semiconductors, such as GaAs, II-VI compound semiconductors such as ZnSe. The substrate102may have a top surface. The top surface of the substrate102may have a rectangular or a square shape. The top surface of the substrate102may be oriented along an equivalent crystal plane of {100}, and preferably, a crystal plane of (100).

In a single crystal semiconductor material, all lattice directions and lattice planes in a unit cell of a single crystal material can be described by a mathematical description known as a Miller Index. The notation [hkl] in the Miller Index defines a crystal direction or orientation, such as the [001], [100], [010], [110], and [111] directions in a cubic unit cell of single crystal silicon. The crystal planes or facets of a single crystal silicon unit cell are defined by the notation (hkl) in the Miller Index, which refers to a particular crystal plane or facet that is perpendicular to the [hkl] direction. For example, the crystal planes (100), (110), and (111) of the single crystal silicon unit cells are respectively perpendicular to the [100], [110], and [111] directions. Moreover, because the unit cells are periodic in a semiconductor crystal, there exist families or sets of equivalent crystal directions and planes. The notation <hkl> in the Miller Index therefore defines a family or set of equivalent crystal directions or orientations. For example, the <100> directions include the equivalent crystal directions of [100], [010], and [001]; the <110> directions include the equivalent crystal directions of [110], [011], [101], [−1−10], [0−1−1], [−10−1], [−110], [0−11], [−101], [1−10], [01−1], and [10−1]; and the <111> directions include the equivalent crystal directions of [111], [−111], [1−11], and [11−1]. Similarly, the notation {hkl} defines a family or set of equivalent crystal planes or facets that are respectively perpendicular to the <hkl> directions. For example, the {100} planes include the set of equivalent crystal planes that are respectively perpendicular to the <100> directions. Correspondingly, the term “equivalent crystal planes” as used herein may refer to a family of equivalent crystal planes or facets as defined by the Miller Indexes, as described hereinabove.

Grooves104,114,124,134are defined on the substrate102. For example, the grooves104,114,124,134may be recessed in the top surface of the substrate102. The grooves104,114,124,134include at least one groove positioned at each of the four edges102a,102b,102c,102dof the substrate102. As an example, the substrate102may have a first edge102a, a second edge102b, a third edge102c, and a fourth edge102d. The first edge102amay be positioned opposite to the third edge102c, while the second edge102bmay be positioned opposite to the fourth edge102d. The edges102a,102b,102c,102dof the substrate102may form a rectangular perimeter around the top surface of the substrate102. A first array108of grooves104may be positioned at the first edge102aof the substrate102. A second array118of grooves114may be positioned at the second edge102bof the substrate102. A third array128of grooves124may be positioned at the third edge102cof the substrate102. A fourth array138of grooves134may be positioned at the fourth edge102dof the substrate102.

The grooves104,114,124,134form an acute angle110,120,130,140with the respective edges102a,102b,102c,102dof the substrate102. In particular, each groove104,114,124,134may have a longitudinal axis, and the longitudinal axis of each groove104,114,124,134may form an acute angle with the respective edges102a,102b,102c,102dof the substrate102. In some embodiments, the grooves104,114,124,134may form an angle in the range of about 30 degrees to about 60 degrees with the respective edges102a,102b,102c,102dof the substrate. Preferably, the grooves104,114,124,134may form an angle of about 45 degrees with the respective edges102a,102b,102c,102dof the substrate. The grooves104,114,124,134may be aligned along an equivalent crystal direction of <110>. For example, the grooves104,114,124,134may be aligned along a crystal direction of [110], a crystal direction of [−110], or a crystal direction of [1−10].

As shown inFIG.1, the first array108of grooves104may form an acute angle110with the first edge102a, the second array118of grooves114may form an acute angle120with the second edge102b, the third array128of grooves124may form an acute angle130with the third edge102c, and the fourth array138of grooves134may form an acute angle140with the fourth edge102d. In an embodiment, the grooves104,114,124,134positioned at the respective edges102a,102b,102c,102dof the substrate102may be substantially parallel with each other.

The PIC chip100may also include at least one optical fiber positioned in at least one of the four edges of the substrate, in which the at least one optical fiber is in one of the grooves. For example, as shown inFIG.1, optical fibers106may be positioned at the first edge102a, optical fibers116may be positioned at the second edge102b, optical fibers126may be positioned at the third edge102c, and optical fibers136may be positioned at the fourth edge102d. The optical fibers106,116,126,136may be placed in, mounted on, or attached to their respective grooves104,114,124,134. The optical fibers106,116,126,136may form an acute angle with the respective edges102a,102b,102c,102dof the substrate102. Although not shown, the optical fibers may include a core surrounded by a cladding material having a refractive index lower than that of the core. Both the core and the cladding material may be transparent to the light, i.e., have very low loss of the light.

FIG.2is a simplified top-down view of the IC chip100shown inFIG.1and illustrates the relative positioning of the grooves104,114,124,134at the edges102a,102b,102c,102dof the substrate102. For simplicity, only the grooves104,114,124,134and the substrate102are illustrated. Preferably, the cores of the optical fibers positioned at an edge of the substrate may be offset from the cores of the optical fibers positioned at an opposite edge or an adjacent edge of the substrate. In the illustrative example shown inFIG.2, the grooves104at the first edge102amay be positioned offset from the grooves114at the adjacent second edge102bsuch that the longitudinal axis104L of each groove104does not align with the longitudinal axis114L of each groove114. In particular, the longitudinal axis104L of the grooves104may be positioned offset from the longitudinal axis114L of the grooves114by a lateral distance D1, D2, D3. Accordingly, the cores of the optical fibers106at the first edge102amay therefore be positioned offset from the cores of the optical fibers116at the adjacent second edge102b(i.e., no face-to-face alignment of the cores of the optical fibers106and116). Likewise, the grooves124at the third edge102cmay be positioned offset from the grooves134at the adjacent fourth edge102dsuch that the longitudinal axis124L of each groove124does not align with the longitudinal axis134L of each groove134. In particular, the longitudinal axis124L of the grooves124may be positioned offset from the longitudinal axis134L of the grooves134by a lateral distance D4, D5, D6. Accordingly, the cores of the optical fibers126may therefore be positioned offset from the cores of the optical fibers136.

Referring toFIG.1again, the PIC chip100may include various PIC devices formed above the substrate102. For example, the PIC chip100may include photonics devices132,144,146formed above the substrate102, and a logic device142formed above the substrate102. In the embodiment shown inFIG.1, the logic device142may be integrated into the first PIC chip100. Alternatively, as will be shown in subsequent drawings, the logic device142may be integrated into a different chip from the first PIC chip100.

Examples of the photonics devices may include, but are not limited to, a photodetector132, a laser144, and an optical modulator146. The photonics devices132,144,146may be optically coupled to the optical fibers by waveguides112. In some embodiments, the waveguides112may include bends. The logic device142may be electrically connected to the photonics devices132,144,146by interconnect structures (e.g., conductive lines122). The logic device142may be configured as a “driver” device for controlling the operation of the photonics devices132,144,146. Exemplary functions of a “driver” device for controlling the photonics devices may include optical signal read out, optical signal generation, optimization of photonics chip operation conditions, or data processing. As an example, the logic device142may send/receive electrical signals to/from the respective photonics device132,144,146connected thereto. In an embodiment, the logic device142may include a transistor such as, but is not limited to, planar field-effect transistor, fin-shaped field-effect transistor (FinFET), ferroelectric field-effect transistors (FeFET), CMOS transistor, and bi-polar junction transistor (BJT).

As shown inFIG.1, optical fiber126may be optically coupled to photodetector132via waveguide112. The optical fiber126may receive optical signals (i.e., electromagnetic waves such as light) from an external source, and then transmit the optical signals towards the waveguide112. The optical signals may be propagated along the wave guide112towards the photodetector132. The photodetector132may be electrically connected to the logic device142via conductive line122. The photodetector132may convert the optical signals into electrical signals, in which the electrical signals may be transmitted via conductive line122towards the logic device142.

Similarly, laser144may be electrically connected to the logic device142via conductive line122. The laser144may receive electrical signals (e.g., current input) from the logic device142via conductive line122. The laser144may convert the electrical signals into optical signals (e.g., light). Optical fiber136may be optically coupled to laser144via waveguide112. The optical signals may be propagated along the waveguide112towards the optical fiber136, and subsequently, transmitted out of the IC chip100via the optical fiber136.

Optical fibers positioned at different edges of the substrate102may be in optical communication with each other. For example, optical fiber106positioned on the first edge102aof the substrate102may be optically coupled to optical fiber116positioned on a second edge102bof the substrate102. As shown inFIG.1, optical fiber116may be optically coupled to optical fiber106via waveguide112. A portion of the waveguide112may pass through the optical modulator146. The optical modulator146may modify or alter the optical signal propagated within the waveguide112. For example, the optical modulator146may modify an incoming optical signal to produce a different outgoing optical signal by modulating the amplitude of the optical signal (i.e. light intensity).

For simplicity, not all optical fibers106,116,126,136inFIG.1are illustrated as being optically coupled to photonics devices or each other. However, it should be understood that the IC chip100may include additional photonics devices, and that all of the optical fibers106,116,126,136may be optically coupled to either the additional photonics devices or other optical fibers in the IC chip100. Furthermore, more than one optical fiber may be optically coupled to a single photonics device in the IC chip100. It should also be noted that the present disclosure contemplates embodiments where not all of the grooves in the substrate are filled with an optical fiber. In other words, it is possible for a groove in the substrate to be left unused (i.e., the groove does not have an optical fiber placed therein).

Advantageously, the positioning of at least one groove104,114,124,134at each of the four edges102a,102b,102c,102dof the substrate102may enable all four edges102a,102b,102c,102dof the substrate102to be utilized for the placement, attachment, or mounting of optical fibers106,116,126,136. The utilization of all four edges102a,102b,102c,102dof the substrate102for attachment of optical fibers may provide increased points of entry/exit for the transmission of optical signals into/from the IC chip100, thereby enabling the IC chip100to accommodate a larger number of distinct optical signals and achieve greater data density.

Referring toFIG.3, in which like reference numerals refer to like features inFIG.1, an example of a semiconductor product200for photonics application is shown. As used herein, the term “semiconductor product” may include a semiconductor “assembly” or a semiconductor “package”. The semiconductor product200may include the first IC chip100as described inFIG.1, and a second IC chip300. The second IC chip300may be positioned above the first IC chip100. In some embodiments, the second IC chip300may be bonded to the first IC chip by conductive bumps148. For simplicity and clarity, the second IC chip300is outlined by a rectangle inFIG.3so as not to obscure the illustration of the conductive bumps148positioned underneath the second IC chip300.

The second IC chip300may be electrically connected to the photonics devices132,144,146of the first IC chip100. In particular, the second IC chip300may include a logic device (not shown) that is electrically connected to the photonics devices132,144,146of the first IC chip100. The second IC chip300may be referred to as the “driver” chip described herein for controlling the operation of the photonics devices132,144,146. For example, the logic device (not shown) in the second IC chip300may send/receive electrical signals to/from the respective photonics device132,144,146connected thereto. In an embodiment, the logic device (not shown) in the second IC chip300may include a transistor such as, but is not limited to, planar field-effect transistor, fin-shaped field-effect transistor (FinFET), ferroelectric field-effect transistors (FeFET), CMOS transistor, and bi-polar junction transistor (BJT). In some embodiments, the first IC chip100may be a PIC chip while the second IC chip300may be an electronic integrated circuit (EIC) chip.

FIG.4illustrates a cross-sectional view of the semiconductor product200along the section line AA shown inFIG.3. Referring toFIG.4, the second IC chip300may be positioned above the first IC chip100. Various types of chip-to-chip interconnections (e.g., wire bonding, solder bumps, flip chip bonding, etc.) may be used to bond the first IC chip100with the second IC chip300. In an embodiment, the first IC chip100may be bonded to the second IC chip300by conductive bumps148. The first IC chip100and the second IC chip300may each have connection pads156,356. The conductive bumps148may be disposed on the connection pads156of the first IC chip100. The second IC chip300may be positioned above the first IC chip100by having the connection pads356of the second IC chip300vertically aligned with the conductive bumps148. The connection pads356of the second IC chip300may subsequently contact the conductive bumps148, and the conductive bumps148may be reflowed to complete the bonding process. An underfill material152may be inserted between the first IC chip100and the second IC chip300, e.g., by a capillary under-filling step.

The connection pads156of the first IC chip100may be in contact with interconnect structures154located in the back end of line (BEOL) portion of the first IC chip100. Similarly, the connection pads356of the second IC chip300may be in contact with interconnect structures354located in the BEOL portion of the second IC chip300. The second IC chip300may include a logic device342. As described herein, the first IC chip100may include photonics devices (not shown) formed above the substrate102of the first IC chip100. The logic device342may be electrically connected to the photonics devices (not shown) in the first IC chip100via the interconnect structures354of the second IC chip300, the conductive bumps148, and the interconnect structures154of the first IC chip100. Although not shown in the accompanying drawings, the semiconductor product200may be assembled on a laminate, a printed circuit board, or an interposer.

FIG.5illustrates a conventional wafer158′ obtained during the fabrication of semiconductor devices. The wafer158′ may have a crystallographic surface orientation along a (100) plane and include a notch160′ at its edge. The notch160′ may be aligned along an equivalent crystal direction of <110>. The wafer158′ may be diced to form IC chips or dies that have its edges being either parallel or perpendicular to the equivalent crystal direction of <110>.

FIGS.6,7A, and7Bshow a set of steps that may be used to create the IC chip and the semiconductor product as provided for in embodiments of the present disclosure.

As used herein, “deposition techniques” refer to the process of applying a material over another material (or the substrate). Exemplary techniques for deposition include, but are not limited to, spin-on coating, sputtering, chemical vapor deposition (CVD), physical vapor deposition (PVD), molecular beam deposition (MBD), pulsed laser deposition (PLD), liquid source misted chemical deposition (LSMCD), atomic layer deposition (ALD).

Additionally, “patterning techniques” include deposition of material or photoresist, patterning, exposure, development, etching, cleaning, and/or removal of the material or photoresist as required in forming a described pattern, structure, or opening. Examples of techniques for patterning include, but are not limited to, wet etch lithographic processes, dry etch lithographic processes, or direct patterning processes. Such techniques may use mask sets and mask layers.

FIG.6illustrates a wafer158obtained during the fabrication of semiconductor structures and devices, in accordance with the present disclosure. Examples of devices fabricated in the wafer158may include photonics devices (not shown) and logic devices (not shown). The wafer158may include a semiconductor material with a single crystalline structure. The wafer158may have a crystallographic surface orientation along a (100) plane, and may further include a notch160at its edge. Unlike the conventional wafer158′ shown inFIG.5, in the present disclosure, the wafer158may be rotated about a center axis perpendicular to its (100) crystal plane. The wafer158may be rotated in either a clockwise (not shown) or an anti-clockwise direction162. The wafer158may be rotated by an angle in the range of about 30 degrees to about 60 degrees, or preferably, an angle of about 45 degrees. In an example, the wafer158may be rotated such that its notch160may be aligned along an equivalent crystal direction of <110>.

The wafer158may be subsequently patterned using the patterning techniques described herein. For example, a photoresist layer (not shown) may be defined on a top surface of the wafer158. The top surface of the wafer158may be subsequently etched using an isotropic etch, or an anisotropic etch (i.e., directional etching) to form grooves on the top surface of the wafer158. In an embodiment, the top surface of the wafer158may be etched to define grooves that are aligned along the equivalent crystal direction of <110>.

In an embodiment, the wafer158may be preferably etched using an anisotropic etch, such as reactive ion etching, or plasma etching. The etching process may etch the semiconductor material in the wafer158along a direction perpendicular to the top surface of the wafer158. Additionally, the anisotropic etch may etch the semiconductor material at different etching rates along different crystallographic directions and planes. In other words, certain crystal plane orientations in the wafer158are more resistant to etching than other crystal plane orientations in the wafer158. In another embodiment, the wafer158may be etched using an isotropic etch (e.g., using a wet etching). In a wet etching process, a wet etchant selected from the group consisting of ammonia, tetramethylammonium hydroxide (TMAH), potassium hydroxide (KOH), ethylenediamine pyrocatechol (EDP), and a combination thereof may be used.

The wafer158may be subsequently diced to form numerous dies, such as the IC chip100. Each die diced from the wafer158, such as the IC chip100, may include a substrate102having four edges. Unlike the conventional wafer158′ shown inFIG.5, in the present disclosure, the wafer158may be diced such that the edges of the resulting IC chip100form an acute angle with respect to the equivalent crystal direction of <110>.

FIG.7AandFIG.7Billustrate various examples of grooves104,114,124,134formed on the substrate102of the IC chip. Referring toFIG.7AandFIG.7B, the substrate102has a first edge102a, a second edge102b, a third edge102c, and a fourth edge102d. A first array108of grooves104may be formed at the first edge102aof the substrate102. A second array118of grooves114may be formed at the second edge102bof the substrate102. A third array128of grooves124may be formed at the third edge102cof the substrate102. A fourth array138of grooves134may be formed at the fourth edge102dof the substrate102. Depending on design rules and requirements, each array of grooves may be spaced apart from the respective adjacent edges of the substrate102. For example, the first array108of grooves104may be spaced apart from adjacent edges102band102dby a distance D1. Similarly, the second array118may be spaced apart from adjacent edges102aand102cby the distance D1, the third array128may be spaced apart from adjacent edges102band102dby the distance D1, and the fourth array138may be spaced apart from adjacent edges102aand102cby the distance D1.

The wafer158shown inFIG.6may be etched to have the grooves104,114,124,134form an acute angle110,120,130,140with the respective edges102a,102b,102c,102dof the substrate102. In the embodiment shown inFIG.7A, the grooves104,114,124,134at the respective edges102a,102b,102c,102dof the substrate102may be substantially parallel with each other. In particular, the grooves104,114,124,134may form the same angles with their respective edges102a,102b,102c,102d, and the grooves104,114,124,134may be aligned along the same equivalent crystal direction (e.g., <110>). For example, grooves104form an acute angle110with edge102a, grooves114form an acute angle120with edge102b, grooves124form an acute angle130with edge102c, and grooves134form an acute angle140with edge102d, in which the angles110,120,130,140may have the same value.

In the embodiment shown inFIG.7B, the first array108of grooves104and the third array128of grooves124may be aligned along a different crystal direction from the second array118of grooves114and the fourth array138of grooves134. The grooves104,114,124,134may also form angles110,120,130,140with the edges102a,102b,102c,102dthat are of the same value. For example, the grooves104,124may be aligned along a crystal direction of [110] while the grooves114,134may be aligned along a crystal direction of [1−10]. The grooves104,114,124,134may also form an acute angle of about 45 degrees with the respective edges102a,102b,102c,102d. To form the embodiment shown inFIG.7B, the wafer158may be rotated twice and patterned twice. For example, the wafer158inFIG.6may be rotated a first time and then patterned to form the grooves104,124. Subsequently, the wafer158may be rotated a second time about an axis perpendicular to its top surface and then patterned to form the grooves114,134.

The embodiments shown inFIG.7AandFIG.7Bmay undergo further processing. For example, optical fibers may be attached to, mounted in, or placed on the grooves104,114,124,134. The IC chip100may include waveguides above the substrate102for alignment with the optical fibers in the grooves104,114,124,134. Although not shown, the optical fibers may include a core surrounded by a cladding material having a refractive index lower than that of the core. The optical fibers may have their cores aligned with the waveguides in the substrate102.

The grooves104,114,124,134described in the present disclosure may have various cross-sectional shapes.FIG.8A,FIG.8B, andFIG.8Cillustrate exemplary cross-sectional views of the groove114taken along section line BB shown inFIG.7A. Referring toFIG.8A, the groove114in the substrate102may have sides114a,114band a bottom edge114c. The sides114a,114bmay taper towards each other to meet at the bottom edge114c. The sides114a,114bmay be oriented along an equivalent crystal plane of {111}. The groove114shown inFIG.8Amay be referred to as a “V-groove” or a “V-shaped” groove. As an example, the V-groove114may be formed in a top surface102tof the substrate102, the top surface102tbeing oriented to an equivalent crystal plane of {100}, by performing an anisotropic etch. The etching reaction may proceed in an equivalent crystal direction of <100> and the etch rate may be slower when the etching front hits the equivalent crystal planes of {111}. In other words, the etch rate of the equivalent crystal plane of {100} may be faster than the etch rate of the equivalent crystal plane of {111}.

Referring toFIG.8B, the groove114may have sides114a,114band a bottom surface114c. The sides114a,114bmay taper towards each other to meet at the bottom surface114c. The sides114a,114bmay be oriented along equivalent crystal planes of {111} and the bottom surface114cmay be oriented along an equivalent crystal plane of {100}. Alternatively, in another embodiment (not shown), the sides114a,114bmay not taper towards each other, and instead, the sides114a,114bmay be substantially vertical. Referring toFIG.8C, the groove114may be formed with a concave surface114a. The concave surface114aof the groove114may be formed by performing a wet etch on the wafer158shown inFIG.6.

Throughout this disclosure, it is to be understood that if a method is described herein as involving a series of steps, the order of such steps as presented herein is not necessarily the only order in which such steps may be performed, and certain of the stated steps may possibly be omitted and/or certain other steps not described herein may possibly be added to the method. Furthermore, the terms “comprise”, “include”, “have”, and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or device that comprises a list of elements is not necessarily limited to those elements, but may include other elements not expressly listed or inherent to such process, method, article, or device. Occurrences of the phrase “in an embodiment” herein do not necessarily all refer to the same embodiment.

The descriptions of the various embodiments of the present disclosure have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein. Furthermore, there is no intention to be bound by any theory presented in the preceding background or the following detailed description. Additionally, the various tasks and processes described herein may be incorporated into a more comprehensive procedure or process having additional functionality not described in detail herein.

As will be readily apparent to those skilled in the art upon a complete reading of the present application, the disclosed semiconductor chips, products, and methods of forming the same may be employed in manufacturing a variety of different integrated circuit products and packaging modules, including, but not limited to, photonics modules, optical communication systems, etc.