Systems and methods for controlling brightness of cold-cathode fluorescent lamps with wide dimming range and adjustable minimum brightness

System and method for adjusting brightness of one or more cold-cathode fluorescent lamps. The system includes a voltage selector configured to receive a dimming voltage and a first threshold voltage and generate an output voltage. The output voltage is selected from a group consisting of the dimming voltage and the first threshold voltage. Additionally, the system includes an oscillator coupled to a first capacitor and configured to generate a ramp signal with the first capacitor, and a signal generator configured to receive the ramp signal and the output voltage and generate a first signal. The first signal corresponds to a lamp brightness level. Moreover, the system includes a brightness detector configured to receive the first signal and output a second signal. The second signal indicates whether the lamp brightness level is higher than a threshold brightness level.

1. CROSS-REFERENCES TO RELATED APPLICATIONS

This application claims priority to Chinese Patent Application No. 201010217991.0, filed Jun. 24, 2010, commonly assigned, incorporated by reference herein for all purposes.

2. BACKGROUND OF THE INVENTION

The present invention is directed to brightness control. More particularly, the invention provides brightness control systems and methods with wide dimming range and adjustable minimum brightness. Merely by way of example, the invention has been applied to controlling brightness of cold-cathode fluorescent lamps (CCFLs). But it would be recognized that the invention has a much broader range of applicability.

The brightness of cold-cathode fluorescent lamps (CCFLs) can be controlled by conventional burst dimming technology. For burst dimming, a DC voltage is often received by a control chip, which, in response, adjusts the duty cycle of a low-frequency signal within the chip. This low-frequency signal is used to control a gate driver, whose output is further processed to adjust the brightness of the CCFLs. Sometimes, one or more of these CCFLs have an open circuit, so the control chip may also include an open-loop-protection (OLP) component. The OLP component can turn off the output of the gate driver if the control chip determines the current that flows through one or more CCFLs falls below a predetermined threshold level. But if the brightness of a CCFL becomes too low, the control chip may mistakenly infer the CCFL has an open circuit. Hence, the control chip usually sets a fixed minimum brightness internally.

FIG. 1is a simplified diagram showing a conventional system for controlling brightness of one or more CCFLs. The system100includes a control chip102, a power stage104, a transformer106, a CCFL108, resistors109and114, and capacitors107,134and154. Additionally, the control chip102includes a voltage generator110, a voltage selector120, an oscillator130, a burst generator140, an error amplifier150, a gate driver160, a logic component170, an open-loop detector180, and a protection component190. Moreover, the control chip102also includes terminals112,122,132,152,162, and166.

As shown inFIG. 1, through the terminal112, the voltage generator110is coupled to the resistor114. The oscillator130and the burst generator140are coupled to the capacitor134through the terminal132. Additionally, the error amplifier150is coupled to the CCFL108and the resistor109through the terminal152. Moreover, the error amplifier150and the gate driver160are coupled to the capacitor154through the terminal166. Also, the gate driver160is coupled to the power stage104through the terminal162.

As an example, the control chip102regulates the start-up, normal operation, and protection of the system100. Specifically, the control chip102sends a drive signal164to the power stage104. The power stage104also receives a system input voltage (VIN) and generates a transformer input voltage, which is received by the transformer106. The transformer106, together with the capacitor107, supplies a lamp voltage to the CCFL108. The CCFL108is coupled to the resistor109, which converts the current that flows through the CCFL108into a sensing voltage158. The sensing voltage158is then received by the error amplifier150through the terminal152.

As shown inFIG. 1, the error amplifier150is a part of the control chip102, which also includes at least the voltage selector120. The voltage selector120receives a DRC voltage (VDRC) and a dimming voltage (VDIM). The DRC voltage is a predetermined voltage, and is generated by one or more components internal to the control chip102. In contrast, the dimming voltage can be adjusted and is supplied through the terminal122from one or more components that are external to the control chip102. The voltage selector120compares VDRCand VDIM, and uses the lower of the these two voltages as its output voltage Vburst.

Additionally, the oscillator130is a low frequency oscillator. The oscillator130, together with the capacitor134, generates a ramp signal136. The ramp signal136is received by the burst generator140, which also receives the voltage Vburst. The burst generator140compares the voltage Vburstand the ramp signal136, and generates a burst signal142(e.g., a pulse-width-modulation burst signal). The burst signal142is received by the error amplifier150. The error amplifier150processes the received burst signal142and the received sensing voltage158, and outputs a CMP signal156with the capacitor154. The CMP signal156is sent to the gate driver160.

As shown inFIG. 1, the control chip102also includes the logic component170, the open-loop detector180, and the protection component190. The logic component170outputs an ENA signal172to the open-loop detector180. The open-loop detector180also receives the sensing voltage158. If enabled by the ENA signal172, the open-loop detector180processes the sensing voltage158, determines whether the CCFL108has an open circuit, and sends an OLP signal182to the protection component190. In response, the protection component190outputs a signal192to the gate driver160.

The gate driver160then processes the received signals156and192and sends the drive signal164through the terminal162to the power stage104. If the OLP signal182indicates that the CCFL108has been determined to have an open circuit, the drive signal164would remain at the logic low level. Additionally, if the open-loop detector180is not enabled by the ENA signal172, the drive signal164is not affected by the signal192. For example, the drive signal164is generated based on the CMP signal156, not the signal192, if the ENA signal172is at the logic low level. Furthermore, the control chip102also includes the voltage generator110. The voltage generator110provides a reference voltage to the resistor114through the terminal112.

FIG. 2is a simplified diagram showing convention signal curves for the system100for controlling brightness of one or more CCFLs. Specifically, a curve210represents the ramp signal136as a function of time, and a curve220represents the dimming voltage as a function of time. Additionally, a curve230represents the burst signal142as a function of time, and a curve240represents the drive signal164as a function of time. Moreover, a curve250represents a function of lamp current as a function of time. The lamp current is the current that flows through the CCFL108. Alternatively, the curve250represents a function of the sensing voltage158as a function of time.

FIG. 3is a simplified conventional diagram showing duty cycle of the burst signal142as a function of the dimming voltage for the system100for controlling brightness of one or more CCFLs. As shown inFIG. 3, if the dimming voltage is smaller than a first threshold level (Vth1) but larger than or equal to zero, the duty cycle of the burst signal142remains at 100%.

If the dimming voltage is equal to or larger than the first threshold level (Vth1) but smaller than or equal to the DRC voltage, the duty cycle of the burst signal142decreases with the increasing VDIM, along a straight line310. As discussed above, the DRC voltage is a predetermined voltage that is generated by one or more components internal to the control chip102. As shown inFIG. 3, if the dimming voltage is equal to the DRC voltage, the duty cycle is equal to a minimum level (Dmin). Additionally, if the dimming voltage is larger than the DRC voltage, the duty cycle remains at the minimum level (Dmin).

Specifically, the DRC voltage is a constant that is larger than the first threshold level (Vth1) and smaller than a second threshold level (Vth2). As shown inFIG. 3, the second threshold level (Vth2) corresponds to the intersection between the horizontal axis for VDIMand the extension of the straight line310. Correspondingly, the minimum level (Dmin) is a constant that is lower than 100% but higher than zero.

Also, as shown inFIG. 1, the brightness of the CCFL109increases with the duty cycle of the burst signal142. If the duty cycle of the burst signal142is at 100%, the brightness of the CCFL109is at the maximum. If the duty cycle of the burst signal142is at the minimum level (Dmin), the brightness of the CCFL109is at the minimum.

In addition to the burst dimming technology as discussed above, the brightness of CCFLs can also be controlled by conventional analog dimming technology. For analog dimming, an external voltage is often received by a control chip, which, in response, converts the received external voltage into an internal DC voltage. For example, the internal DC voltage is used to adjust the lamp current that flows through the CCFLs. In another example, the lamp current is proportional to the internal DC voltage. Hence, the brightness of the CCFLs can be changed by adjusting the internal DC voltage, which is often controlled by the external voltage.

FIG. 4is a simplified diagram showing another conventional system for controlling brightness of one or more CCFLs. The system400includes a control chip402, a power stage404, a transformer406, a CCFL408, resistors409and414, and capacitors407and454. Additionally, the control chip402includes a voltage generator410, a voltage selector420, a level shifter430, an error amplifier450, a gate driver460, a logic component470, an open-loop detector480, and a protection component490. Moreover, the control chip102also includes terminals412,422,452,462, and466.

As shown inFIG. 4, through the terminal412, the voltage generator410is coupled to the resistor414. Additionally, the error amplifier450is coupled to the CCFL408and the resistor409through the terminal452. Moreover, the error amplifier450and the gate driver460are coupled to the capacitor454through the terminal466. Also, the gate driver460is coupled to the power stage404through the terminal462.

As an example, the control chip402regulates the start-up, normal operation, and protection of the system400. Specifically, the control chip402sends a drive signal464to the power stage404. The power stage404also receives a system input voltage (VIN) and generates a transformer input voltage, which is received by the transformer406. The transformer406, together with the capacitor407, supplies a lamp voltage to the CCFL408. The CCFL408is coupled to the resistor409, which converts the current that flows through the CCFL408into a sensing voltage458. The sensing voltage458is then received by the error amplifier450through the terminal452.

As shown inFIG. 4, the error amplifier450is a part of the control chip402, which also includes at least the voltage selector420and the level shifter430. The level shifter430receives a dimming voltage (VDIM) and converts the dimming voltage (VDIM) into a shifted voltage (Vsft). For example, the dimming voltage can be adjusted and is supplied through the terminal422from one or more components that are external to the control chip402. In another example, the shifted voltage is inversely proportional to the dimming voltage.

The shifted voltage (Vsft) is outputted to the voltage selector420, which also receives a DRC voltage (VDRC). The DRC voltage is a predetermined voltage, and is generated by one or more components internal to the control chip402. The voltage selector420compares VDRCand Vsft, and uses the higher of the these two voltages as its output voltage442(Vref). The output voltage442is received by the error amplifier450. The error amplifier450processes the received output voltage442and the received sensing voltage458, and outputs a CMP signal456with the capacitor454. The CMP signal456is sent to the gate driver460.

As shown inFIG. 4, the control chip402also includes the logic component470, the open-loop detector480, and the protection component490. The logic component470outputs an ENA signal472to the open-loop detector480. The open-loop detector480also receives the sensing voltage458. If enabled by the ENA signal472, the open-loop detector480processes the sensing voltage458, determines whether the CCFL408has an open circuit, and sends an OLP signal482to the protection component490. In response, the protection component490outputs a signal492to the gate driver460.

The gate driver460then processes the received signals456and492and sends the drive signal464through the terminal462to the power stage404. If the OLP signal482indicates that the CCFL408has been determined to have an open circuit, the drive signal464would remain at the logic low level. Additionally, if the open-loop detector180is not enabled by the ENA signal472, the drive signal464is not affected by the signal492. For example, the drive signal464is generated based on the CMP signal456, not the signal492, if the ENA signal472is at the logic low level. Furthermore, the control chip402also includes the voltage generator410. The voltage generator410provides a reference voltage to the resistor414through the terminal412.

FIG. 5is a simplified diagram showing convention signal curves for the system400for controlling brightness of one or more CCFLs. Specifically, a curve510represents the dimming voltage as a function of time. Additionally, a curve520represents the output voltage442as a function of time. Moreover, a curve530represents a function of lamp current as a function of time. The lamp current is the current that flows through the CCFL408. Alternatively, the curve530represents a function of the sensing voltage458as a function of time.

FIG. 6is a simplified conventional diagram showing the output voltage442of the voltage selector420as a function of the dimming voltage for the system400for controlling brightness of one or more CCFLs. As shown inFIG. 6, if the dimming voltage is smaller than a first threshold level (Vth1) but larger than or equal to zero, the output voltage442remains at a maximum voltage level (Vmax).

If the dimming voltage is equal to or larger than the first threshold level (Vth1) but smaller than or equal to the DRC voltage, the output voltage442decreases with the increasing VDIM, along a straight line610. As discussed above, the DRC voltage is a predetermined voltage that is generated by one or more components internal to the control chip402. As shown inFIG. 6, if the dimming voltage is equal to the DRC voltage, the output voltage442is equal to a minimum voltage level (Vmin). Additionally, if the dimming voltage is larger than the DRC voltage, the output voltage442remains at the minimum level (Vmin).

Specifically, the DRC voltage is a constant that is larger than the first threshold level (Vth1) and smaller than a second threshold level (Vth2). As shown inFIG. 6, the second threshold level (Vth2) corresponds to the intersection between the horizontal axis for VDIMand the extension of the straight line610. Correspondingly, the minimum level (Vmin) is a constant that is lower than Vmaxbut higher than zero.

Also, as shown inFIG. 4, the brightness of the CCFL409increases with the output voltage442. If the output voltage442is at Vmax, the brightness of the CCFL409is at the maximum. If the output voltage442is at Vminthe brightness of the CCFL409is at the minimum.

But the conventional burst dimming technology and the conventional analog dimming technology often do not provide a wide range of brightness for CCFLs. Hence it is highly desirable to improve the techniques for brightness control.

3. BRIEF SUMMARY OF THE INVENTION

The present invention is directed to brightness control. More particularly, the invention provides brightness control systems and methods with wide dimming range and adjustable minimum brightness. Merely by way of example, the invention has been applied to controlling brightness of cold-cathode fluorescent lamps (CCFLs). But it would be recognized that the invention has a much broader range of applicability.

According to one embodiment, a system for adjusting brightness of one or more cold-cathode fluorescent lamps includes a voltage selector configured to receive a dimming voltage and a first threshold voltage and generate an output voltage. The output voltage is selected from a group consisting of the dimming voltage and the first threshold voltage. Additionally, the system includes an oscillator coupled to a first capacitor and configured to generate a ramp signal with the first capacitor, and a signal generator configured to receive the ramp signal and the output voltage and generate a first signal. The first signal corresponds to a lamp brightness level. Moreover, the system includes a brightness detector configured to receive the first signal and output a second signal. The second signal indicates whether the lamp brightness level is higher than a threshold brightness level. Also, the system includes a logic component configured to output a third signal, an open-loop detector configured to receive at least the second signal and the third signal and generate a fourth signal in response to at least the second signal and the third signal, and a protection component configured to receive the fourth signal and generate a protection signal based on at least information associated with the fourth signal. Additionally, the system includes an error amplifier coupled to a second capacitor and configured to receive the first signal and a sensing voltage and to generate a fifth signal based on at least information associated with the first signal and the sensing voltage, and a gate driver configured to receive the protection signal and the fifth signal and generate a drive signal. For example, the open-loop detector is further configured to receive the sensing voltage, the sensing voltage being associated with a lamp current flowing through at least one cold-cathode fluorescent lamp, and process information associated with the second signal and the third signal. In another example, the open-loop detector is further configured to, if the second signal satisfies one or more predetermined first conditions and the third signal satisfies one or more predetermined second conditions, determine whether the cold-cathode fluorescent lamp is associated with an open circuit based on at least information associated with the sensing voltage and output the fourth signal indicating whether the cold-cathode fluorescent lamp is associated with the open circuit. In yet another example, the open-loop detector is further configured to, if the second signal does not satisfy the one or more predetermined first conditions, output the fourth signal regardless of the sensing voltage, the fourth signal indicating that the cold-cathode fluorescent lamp is not associated with the open circuit. In yet another example, the open-loop detector is further configured to, if the third signal does not satisfy the one or more predetermined second conditions, output the fourth signal regardless of the sensing voltage, the fourth signal indicating that the cold-cathode fluorescent lamp is not associated with the open circuit.

According to another embodiment, a method for adjusting brightness of one or more cold-cathode fluorescent lamps includes receiving a dimming voltage and a first threshold voltage. The dimming voltage is associated with a first magnitude, and the first threshold voltage is associated with a second magnitude. Additionally, the method includes generating an output voltage, the output voltage being selected from a group consisting of the dimming voltage and the first threshold voltage. Moreover, the method includes receiving the output voltage and a ramp signal, processing information associated with the output voltage and the ramp signal, and generating a first signal based on at least information associated with the output voltage and the ramp signal. The first signal corresponds to a lamp brightness level. Also, the method includes processing information associated with the first signal, and outputting a second signal based on at least information associated with the first signal. The second signal indicates whether the lamp brightness level is higher than a threshold brightness level. Additionally, the method includes receiving the second signal, a third signal, and a sensing voltage. The sensing voltage is associated with a lamp current flowing through at least one cold-cathode fluorescent lamp. Moreover, the method includes generating a fourth signal in response to at least the second signal and the third signal, receiving the first signal and the sensing voltage, generating a fifth signal based on at least information associated with the first signal and the sensing voltage, processing information associated with the fourth signal and the fifth signal, and generating a drive signal based on at least information associated with the fourth signal and the fifth signal. For example, the process for generating a fourth signal in response to at least the second signal and the third signal includes processing information associated with the second signal and the third signal. In another example, the process for generating a fourth signal in response to at least the second signal and the third signal includes, if the second signal satisfies one or more predetermined first conditions and the third signal satisfies one or more predetermined second conditions, determining whether the cold-cathode fluorescent lamp is associated with an open circuit based on at least information associated with the sensing voltage, and outputting the fourth signal indicating whether the cold-cathode fluorescent lamp is associated with the open circuit. In yet another example, the process for generating a fourth signal in response to at least the second signal and the third signal includes, if the second signal does not satisfy the one or more predetermined first conditions, outputting the fourth signal regardless of the sensing voltage, the fourth signal indicating that the cold-cathode fluorescent lamp is not associated with the open circuit. In yet another example, the process for generating a fourth signal in response to at least the second signal and the third signal includes, if the third signal does not satisfy the one or more predetermined second conditions, outputting the fourth signal regardless of the sensing voltage, the fourth signal indicating the cold-cathode fluorescent lamp is not associated with the open circuit.

According to yet another embodiment, a system for adjusting brightness of one or more cold-cathode fluorescent lamps includes a level shifter configured to receive a dimming voltage and generate a first output voltage based on at least information associated with the dimming voltage, and a voltage selector configured to receive the first output voltage and a first threshold voltage and generate a second output voltage. The second output voltage is selected from a group consisting of the first output voltage and the first threshold voltage, and the first threshold voltage corresponds to a lamp brightness level. Additionally, the system includes a brightness detector configured to receive the first threshold voltage and output a first signal, and the first signal indicates whether the lamp brightness level is higher than a threshold brightness level. Moreover, the system includes a logic component configured to output a second signal, and an open-loop detector configured to receive at least the first signal and the second signal and generate a third signal in response to at least the first signal and the second signal. Also, the system includes a protection component configured to receive the third signal and generate a protection signal based on at least information associated with the third signal, and an error amplifier coupled to a capacitor and configured to receive the second output voltage and a sensing voltage and to generate a fourth signal based on at least information associated with the second output voltage and the sensing voltage. Additionally, the system includes a gate driver configured to receive the protection signal and the fourth signal and generate a drive signal. For example, the open-loop detector is further configured to receive the sensing voltage, the sensing voltage being associated with a lamp current flowing through at least one cold-cathode fluorescent lamp, and process information associated with the first signal and the second signal. In another example, the open-loop detector is further configured to, if the first signal satisfies one or more predetermined first conditions and the second signal satisfies one or more predetermined second conditions, determine whether the cold-cathode fluorescent lamp is associated with an open circuit based on at least information associated with the sensing voltage and output the third signal indicating whether the cold-cathode fluorescent lamp is associated with the open circuit. In yet another example, the open-loop detector is further configured to, if the first signal does not satisfy the one or more predetermined first conditions, output the third signal regardless of the sensing voltage, the third signal indicating that the cold-cathode fluorescent lamp is not associated with the open circuit. In yet another example, the open-loop detector is further configured to, if the second signal does not satisfy the one or more predetermined second conditions, output the third signal regardless of the sensing voltage, the third signal indicating that the cold-cathode fluorescent lamp is not associated with the open circuit.

According to yet another embodiment, a method for adjusting brightness of one or more cold-cathode fluorescent lamps includes receiving a dimming voltage. The dimming voltage is associated with a first magnitude. Additionally, the method includes generating a first output voltage based on at least information associated with the dimming voltage, and receiving the first output voltage and a first threshold voltage. The first threshold voltage corresponds to a lamp brightness level and is associated with a second magnitude. Moreover, the method includes generating a second output voltage, the second output voltage being selected from a group consisting of the first output voltage and the first threshold voltage. Also, the method includes processing information associated with the first threshold voltage, and outputting a first signal based on at least information associated with the first threshold voltage. The first signal indicates whether the lamp brightness level is higher than a threshold brightness level. Additionally, the method includes receiving the first signal, a second signal, and a sensing voltage. The sensing voltage is associated with a lamp current flowing through at least one cold-cathode fluorescent lamp. Moreover, the method includes generating a third signal in response to at least the first signal and the second signal, receiving the second output voltage and a sensing voltage, generating a fourth signal based on at least information associated with the second output voltage and the sensing voltage, processing information associated with the third signal and the fourth signal, and generating a drive signal based on at least information associated with the third signal and the fourth signal. For example, the process for generating a third signal in response to at least the first signal and the second signal includes processing information associated with the first signal and the second signal. In another example, the process for generating a third signal in response to at least the first signal and the second signal includes, if the first signal satisfies one or more predetermined first conditions and the second signal satisfies one or more predetermined second conditions, determining whether the cold-cathode fluorescent lamp is associated with an open circuit based on at least information associated with the sensing voltage, and outputting the third signal indicating whether the cold-cathode fluorescent lamp is associated with the open circuit. In yet another example, the process for generating a third signal in response to at least the first signal and the second signal includes, if the first signal does not satisfy the one or more predetermined first conditions, outputting the third signal regardless of the sensing voltage, the third signal indicating that the cold-cathode fluorescent lamp is not associated with the open circuit. In yet another example, the process for generating a third signal in response to at least the first signal and the second signal includes, if the second signal does not satisfy the one or more predetermined second conditions, outputting the third signal regardless of the sensing voltage, the third signal indicating that the cold-cathode fluorescent lamp is not associated with the open circuit.

Many benefits are achieved by way of the present invention over conventional techniques. Certain embodiments of the present invention allow precise adjustment of minimum brightness for one or more CCFLs. For example, the minimum brightness is adjusted through one or more components that are external to the control chip. In another example, either the burst dimming technology or the analog dimming technology is used. Some embodiments of the present invention provide a wide range of brightness for one or more CCFLs. For example, with burst dimming technology, the brightness can range from 0% to 100% in terms of duty cycle of the burst signal.

Depending upon embodiment, one or more of these benefits may be achieved. These benefits and various additional objects, features and advantages of the present invention can be fully appreciated with reference to the detailed description and accompanying drawings that follow.

5. DETAILED DESCRIPTION OF THE INVENTION

The present invention is directed to brightness control. More particularly, the invention provides brightness control systems and methods with wide dimming range and adjustable minimum brightness. Merely by way of example, the invention has been applied to controlling brightness of cold-cathode fluorescent lamps (CCFLs). But it would be recognized that the invention has a much broader range of applicability.

FIG. 7is a simplified diagram showing a system for controlling brightness of one or more CCFLs according to one embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications.

For example, the system700includes a control chip702, a power stage704, a transformer706, a CCFL708, resistors709and714, and capacitors707,734and754. In another example, the control chip702includes a voltage generator710, a voltage selector720, an oscillator730, a burst generator740, a low brightness detector744, an error amplifier750, a gate driver760, a logic component770, an open-loop detector780, and a protection component790. In yet another example, the control chip702also includes terminals712,722,724,732,752,762, and766.

According to one embodiment, the voltage generator710, the voltage selector720, the oscillator730, the burst generator740, the error amplifier750, the gate driver760, the logic component770, and the protection component790are the same as the voltage generator110, the voltage selector120, the oscillator130, the burst generator140, the error amplifier150, the gate driver160, the logic component170, and the protection component190, respectively.

As shown inFIG. 7, through the terminal712, the voltage generator710is coupled to the resistor714according to one embodiment. In another embodiment, the oscillator730and the burst generator740are coupled to the capacitor734through the terminal732. For example, the oscillator730is a low frequency oscillator. In yet another embodiment, the error amplifier750is coupled to the CCFL708and the resistor709through the terminal752. In yet another embodiment, the error amplifier750and the gate driver760are coupled to the capacitor754through the terminal766. In yet another embodiment, the gate driver760is coupled to the power stage704through the terminal762.

As an example, the control chip702regulates the start-up, normal operation, and protection of the system700. In one embodiment, the control chip702sends a drive signal764to the power stage704. In another embodiment, the power stage704also receives a system input voltage (VIN) and generates a transformer input voltage, which is received by the transformer706. In yet another embodiment, the transformer706, together with the capacitor707, supplies a lamp voltage to the CCFL708. In yet another embodiment, the CCFL708is coupled to the resistor709, which converts the current that flows through the CCFL708into a sensing voltage758. In yet another embodiment, the sensing voltage758is then received by the error amplifier750through the terminal752.

As shown inFIG. 7, the error amplifier750is a part of the control chip702, which also includes at least the voltage selector720, according to an embodiment. For example, the voltage selector720receives a DRC voltage (VDRC) and a dimming voltage (VDIM). In one embodiment, the DRC voltage can be adjusted and is supplied through the terminal724by one or more components external to the control chip702. In another embodiment, the dimming voltage can be adjusted and is supplied through the terminal722from one or more components external to the control chip702. In response, the voltage selector720, for example, compares VDRCand VDIMand uses the lower of the these two voltages as its output voltage Vburst.

According to another embodiment, the oscillator730, together with the capacitor734, generates a ramp signal736. For example, the ramp signal736is received by the burst generator740, which also receives the voltage Vburst. In another example, the burst generator740compares the voltage Vburstand the ramp signal736, and generates a burst signal742. In yet another example, the burst signal742is a pulse-width-modulation burst signal.

In one embodiment, the burst signal742is received by the error amplifier750. For example, the error amplifier750processes the received burst signal742and the received sensing voltage758, and outputs a CMP signal756with the capacitor754. In another example, the CMP signal756is sent to the gate driver760. In another embodiment, the burst signal742is also received by the low brightness detector744. For example, the low brightness detector744processes the burst signal742and outputs a brightness signal746to the open-loop detector780.

According to one embodiment, the brightness signal746indicates whether the brightness of the CCFL708would be above a predetermined brightness threshold. For example, the burst signal742has a period T, which is equal to the sum of Tonand Toff. In another example, during Ton, the burst signal742is at the logic high level, and during Toff, the burst signal742is at the logic low level. In yet another example, the low brightness detector744processes the burst signal742, determines the length of Ton, and compares Tonand Tth. Tthis a time period that corresponds to the predetermined brightness threshold. According to another embodiment, if Ton>Tth, the lamp brightness is determined to be above the predetermined brightness threshold, and if Ton≦Tth, the lamp brightness is determined not to be above the predetermined brightness threshold.

As shown inFIG. 7, the control chip702also includes the logic component770, the open-loop detector780, and the protection component790according to one embodiment. For example, the logic component770outputs an ENA signal772to the open-loop detector780. In another example, the open-loop detector780also receives the brightness signal746and the sensing voltage758.

According to one embodiment, if the open-loop detector780is enabled by both the brightness signal746and the ENA signal772, the open-loop detector780processes the sensing voltage758, determines whether the CCFL708has an open circuit, and sends an OLP signal782to the protection component790. In response, the protection component790outputs a signal792to the gate driver760.

According to another embodiment, the gate driver760processes the received signals756and792and sends the drive signal764through the terminal762to the power stage704. For example, if the OLP signal782indicates that the CCFL708has been determined to have an open circuit, the drive signal764would remain at the logic low level. In another example, if the open-loop detector780is not enabled by both the brightness signal746and the ENA signal772, the drive signal764is not affected by the signal792. According to one embodiment, the drive signal764is generated based on the CMP signal756, not the signal792, if at least one of the brightness signal746and the ENA signal772is at the logic low level.

Also as shown inFIG. 7, the control chip702also includes the voltage generator710according to an embodiment. For example, the voltage generator710provides a reference voltage to the resistor714through the terminal712.

FIG. 8is a simplified diagram showing duty cycle of the burst signal742as a function of the dimming voltage for the system700for controlling brightness of one or more CCFLs according to one embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications.

For example, if the dimming voltage is smaller than a first threshold level (Vth1) but larger than or equal to zero, the duty cycle of the burst signal742remains at 100%. In another example, if the dimming voltage is equal to or larger than the first threshold level (Vth1) but smaller than or equal to the DRC voltage, the duty cycle of the burst signal742decreases with the increasing VDIM, along a straight line810.

As shown inFIG. 8, if the dimming voltage is equal to the DRC voltage, the duty cycle is equal to a minimum level (Dmin). In one embodiment, if the dimming voltage is larger than the DRC voltage, the duty cycle remains at the minimum level (Dmin). In another embodiment, the DRC voltage can be adjusted and is provided by one or more components external to the control chip102.

For example, the DRC voltage can be varied from the first threshold level (Vth1) to the second threshold level (Vth2). As shown inFIG. 8, the second threshold level (Vth2) corresponds to the intersection between the horizontal axis for VDIMand the extension of the straight line810. In another example, the minimum level (Dmin) decreases with the increasing DRC voltage, along the straight line810and/or its extension. In one embodiment, the minimum level (Dmin) can be varied from 100% to zero.

Also, as shown inFIG. 7, the brightness of the CCFL709increases with the duty cycle of the burst signal742according to one embodiment. For example, if the duty cycle of the burst signal742is at 100%, the brightness of the CCFL709is at the maximum. In another example, if the duty cycle of the burst signal742is at the minimum level (Dmin), the brightness of the CCFL709is at the minimum.

FIG. 9is a simplified diagram showing a combination of the voltage selector720, the oscillator730, the burst generator740, the low brightness detector744, and the open-loop detector780as part of the system700for controlling brightness of one or more CCFLs according to one embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. As shown inFIG. 9, the low brightness detector744, for example, includes a pulse generator910, a trigger counter920, a flip-flop930, and an NOT gate940. In another example, the pulse generator910receives the burst signal742and generates a trigger signal912. In yet another example, the trigger signal912is received by the trigger counter920, which in response generates a counter signal922. As shown inFIG. 9, the counter signal922is received by the flip-flop930. In one embodiment, the flip-flop930also receives at least the burst signal742and generates at least an output signal932. In another embodiment, the output signal932is received by the NOT940, which generates the brightness signal746.

FIG. 10is a simplified diagram showing signal curves for the low brightness detector744as part of the system700for controlling brightness of one or more CCFLs according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications.

For example, a curve1010represents the burst signal742as a function of time, and a curve1020represents the trigger signal912as a function of time. In another example, a curve1030represents the counter signal922as a function of time, and a curve1040represents the output signal932as a function of time. In yet another example, a curve1050represents the brightness signal746as a function of time.

As shown inFIGS. 9 and 10, the rising edges of the burst signal742is detected by the pulse generator910, which in response generates the trigger signal912according to an embodiment. For example, the trigger signal912includes multiple pulses, each of which corresponds to a rising edge of the burst signal742. In another example, the trigger signal912is received by the trigger counter920. In one embodiment, the trigger counter920detects the pluses of the trigger signal912, and in response, generates the counter signal922. In another embodiment, the counter signal922includes multiple pulses, each of which corresponds to one of the pulses of the trigger signal912. For example, the rising edges of the counter signal922is triggered by the rising edges of the trigger signal912, respectively. In another example, the pulse width of the counter signal922corresponds to the predetermined brightness threshold. In yet another example, the pulse width of the counter signal922is equal to Tth, and Tthis a time period that corresponds to the predetermined brightness threshold.

According to one embodiment, the flip-flop930is a D flip-flop, which may changes its output at falling edges of the clock input. For example, at each falling edge of the counter signal922, the output signal932becomes or remains to be the same as the burst signal742. As shown inFIG. 10, at a falling edge1032, the burst signal742is at the logic low level, so the output signal932remains at the logic low level. Also as shown inFIG. 10, at a falling edge1034, the burst signal742is at the logic high level, so the output signal932changes to the logic low level. According to another embodiment, the flip-flop930compares the pulse width of the counter signal922and the pulse width of the burst signal742and generates the output signal932. For example, if the pulse width of the burst signal742is smaller than the pulse width of the counter signal922, the output signal932is at the logic low level. In another example, if the pulse width of the burst signal742is larger than the pulse width of the counter signal922, the output signal932is at the logic high level.

According to yet another embodiment, the brightness signal746is inverted from the output signal932. For example, if the pulse width of the burst signal742is smaller than the pulse width of the counter signal922, the brightness signal746is at the logic high level. In another example, if the pulse width of the burst signal742is larger than the pulse width of the counter signal922, the brightness signal746is at the logic low level.

Returning toFIG. 9, the open-loop detector780includes, for example, a NOT gate950, an AND gate960, and a comparator970. In one embodiment, the NOT gate950receives the brightness signal746and generates a signal952. In another embodiment, the signal952is received by the AND gate960, which also receives the ENA signal772and outputs a signal962.

For example, the signal962is received by the comparator970as an enabling signal. In another example, the comparator970also receives the sensing voltage758and a threshold voltage972(Vtho), and outputs the OLP signal782. According to one embodiment, if the signal962is at the logic low level, the OLP signal782remains at the logic low level. According to another embodiment, if the signal962is at the logic high level, the OLP signal782is at the logic high level if the threshold voltage972is higher than the sensing voltage758and the OLP signal782is at the logic low level if the threshold voltage972is lower than the sensing voltage758. According to yet another embodiment, if the sensing voltage758is below the threshold voltage972, the CCFL708is determined to have an open circuit.

As discussed above and further emphasized here,FIGS. 7 and 8are merely examples, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. For example, the resistor714is replaced by a voltage divider that can provide the DRC voltage (VDRC) to the voltage selector720.

FIG. 11is a simplified diagram showing a system for controlling brightness of one or more CCFLs according to another embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications.

As shown inFIG. 11, the system1100includes the control chip702, the power stage704, the transformer706, the CCFL708, the resistor709, the capacitors707,734and754, and resistors1114and1116. For example, the control chip702includes the voltage generator710, the voltage selector720, the oscillator730, the burst generator740, the low brightness detector744, the error amplifier750, the gate driver760, the logic component770, the open-loop detector780, and the protection component790. In another example, the control chip702also includes the terminals712,722,724,732,752,762, and766.

In one embodiment, through the terminal712, the voltage generator710is coupled to the resistor1116, which is connected to the resistor1114. For example, the resistors1114and1116form a voltage divider, which provides the DRC voltage (VDRC) to the voltage selector720. In another example, the DRC voltage (VDRC) can be adjusted by changing the resistors1114and1116.

In another embodiment, the minimum level (Dmin) for the duty cycle of the burst signal742is determined as follows:

where R1is the resistance value of the resistor1114, and R2is the resistance value of the resistor1116. k is a constant that is independent of R1and R2. As shown by Equation 1, the minimum for the brightness of the CCFL708can be adjusted by changing the resistance values of resistors1114and1116.

FIG. 12is a simplified diagram showing a system for controlling brightness of one or more CCFLs according to yet another embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications.

For example, the system1200includes a control chip1202, a power stage1204, a transformer1206, a CCFL1208, resistors1209and1214, and capacitors1207and1254. In another example, the control chip1202includes a voltage generator1210, a voltage selector1220, a level shifter1230, a low brightness detector1244, an error amplifier1250, a gate driver1260, a logic component1270, an open-loop detector1280, and a protection component1290. In yet another example, the control chip1202also includes terminals1212,1222,1224,1252,1262, and1266.

According to one embodiment, the voltage generator1210, the voltage selector1220, the level shifter1230, the error amplifier1250, the gate driver1260, the logic component1270, and the protection component1290are the same as the voltage generator410, the voltage selector420, the level shifter430, the error amplifier450, the gate driver460, the logic component470, and a protection component490, respectively.

As shown inFIG. 12, through the terminal1212, the voltage generator1210is coupled to the resistor1214according to one embodiment. In yet another embodiment, the error amplifier1250is coupled to the CCFL1208and the resistor1209through the terminal1252. In yet another embodiment, the error amplifier1250and the gate driver1260are coupled to the capacitor1254through the terminal1266. In yet another embodiment, the gate driver1260is coupled to the power stage1204through the terminal1262.

As an example, the control chip1202regulates the start-up, normal operation, and protection of the system1200. In one embodiment, the control chip1202sends a drive signal1264to the power stage1204. In another embodiment, the power stage1204also receives a system input voltage (VIN) and generates a transformer input voltage, which is received by the transformer1206. In yet another embodiment, the transformer1206, together with the capacitor1207, supplies a lamp voltage to the CCFL1208. In yet another embodiment, the CCFL1208is coupled to the resistor1209, which converts the current that flows through the CCFL1208into a sensing voltage1258. In yet another embodiment, the sensing voltage1258is then received by the error amplifier1250through the terminal1252.

As shown inFIG. 12, the error amplifier1250is a part of the control chip1202, which also includes at least the voltage selector1220and the level shifter1230, according to an embodiment. For example, the level shifter1230receives a dimming voltage (VDIM) and converts the dimming voltage (VDIM) into a shifted voltage (Vsft). In another example, the dimming voltage can be adjusted and is supplied through the terminal1222from one or more components that are external to the control chip1202. In yet another example, the shifted voltage is inversely proportional to the dimming voltage.

According to another embodiment, the shifted voltage (Vsft) is outputted to the voltage selector1220, which also receives a DRC voltage (VDRC). For example, the DRC voltage can be adjusted and is supplied through the terminal1224by one or more components external to the control chip1202. In another example, the voltage selector1220compares VDRCand Vsft, and uses the higher of the these two voltages as its output voltage1242(Vref). In one embodiment, the output voltage1242is received by the error amplifier1250. In another embodiment, the error amplifier1250processes the received output voltage1242and the received sensing voltage1258, and outputs a CMP signal1256with the capacitor1254. In yet another embodiment, the CMP signal1256is sent to the gate driver1260.

According to yet another embodiment, the DRC voltage (VDRC) is also received by the low brightness detector1244. For example, the low brightness detector1244processes the DRC signal and outputs a brightness signal1246to the open-loop detector1280. In another example, the brightness signal1246indicates whether the brightness of the CCFL1208would be above a predetermined brightness threshold.

As shown inFIG. 12, the control chip1202also includes the logic component1270, the open-loop detector1280, and the protection component1290according to one embodiment. For example, the logic component1270outputs an ENA signal1272to the open-loop detector1280. In another example, the open-loop detector1280also receives the brightness signal1246and the sensing voltage1258.

According to one embodiment, if the open-loop detector1280is enabled by both the brightness signal1246and the ENA signal1272, the open-loop detector1280processes the sensing voltage1258, determines whether the CCFL1208has an open circuit, and sends an OLP signal1282to the protection component1290. In response, the protection component1290outputs a signal1292to the gate driver1260.

According to another embodiment, the gate driver1260processes the received signals1256and1292and sends the drive signal1264through the terminal1262to the power stage1204. For example, if the OLP signal1282indicates that the CCFL1208has been determined to have an open circuit, the drive signal1264would remain at the logic low level. In another example, if the open-loop detector1280is not enabled by both the brightness signal1246and the ENA signal1272, the drive signal1264is not affected by the signal1292. According to one embodiment, the drive signal1264is generated based on the CMP signal756, not the signal792, if at least one of the brightness signal1246and the ENA signal1272is at the logic low level.

Also as shown inFIG. 12, the control chip1202also includes the voltage generator1210according to an embodiment. For example, the voltage generator1210provides a reference voltage to the resistor1214through the terminal1212.

FIG. 13is a simplified diagram showing the output voltage1242of the voltage selector1220as a function of the dimming voltage for the system1200for controlling brightness of one or more CCFLs according to one embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications.

For example, if the dimming voltage is smaller than a first threshold level (Vth1) but larger than or equal to zero, the output voltage1242remains at a maximum voltage level (Vmax). In another example, if the dimming voltage is equal to or larger than the first threshold level (Vth1) but smaller than or equal to the DRC voltage, the output voltage1242decreases with the increasing VDIM, along a straight line1310.

In one embodiment, if the dimming voltage is equal to the DRC voltage, the output voltage1242is equal to a minimum voltage level (Vmin). In another embodiment, if the dimming voltage is larger than the DRC voltage, the output voltage442remains at the minimum level (Vmin).

For example, the DRC voltage can be varied from the first threshold level (Vth1) to the second threshold level (Vth2). As shown inFIG. 13, the second threshold level (Vth2) corresponds to the intersection between the horizontal axis for VDIMand the extension of the straight line1310. In another example, the minimum level (Vmin) decreases with the increasing DRC voltage, along the straight line1310and/or its extension. In one embodiment, the minimum level (Vmin) can be varied from Vmaxto zero.

FIG. 14is a simplified diagram showing a combination of the voltage selector1220, the level shifter1230, the low brightness detector1244, and the open-loop detector1280as part of the system1200for controlling brightness of one or more CCFLs according to one embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications.

As shown inFIG. 14, the low brightness detector1244, for example, includes a comparator1420. In one embodiment, the comparator1420receives a threshold voltage1422(Vthb) and the DRC voltage and outputs the brightness signal1246to the open-loop detector1280. For example, the threshold voltage1422(Vthb) corresponds to the predetermined brightness threshold. In another example, if the threshold voltage1422is higher than the DRC voltage, the brightness signal1246is at the logic high level. In yet another example, if the threshold voltage1422is lower than the DRC voltage, the brightness signal1246is at the logic low level.

According to one embodiment, the open-loop detector1280includes a NOT gate1450, an AND gate1460, and a comparator1470. For example, the NOT gate1450receives the brightness signal1246and generates a signal1452. In another example, the signal1452is at the logic high level if the threshold voltage1422is lower than the DRC voltage. In yet another example, the signal1452is at the logic low level if the threshold voltage1422is higher than the DRC voltage.

According to another embodiment, the signal1452is received by the AND gate1460, which also receives the ENA signal1272and outputs a signal1462. For example, the signal1462is received by the comparator1470as an enabling signal. In another example, the comparator1470also receives the sensing voltage1258and a threshold voltage1472(Vtho), and outputs the OLP signal1282. In one embodiment, if the signal1462is at the logic low level, the OLP signal1282remains at the logic low level. In another embodiment, if the signal1462is at the logic high level, the OLP signal1282is at the logic high level if the threshold voltage1472is higher than the sensing voltage1258and the OLP signal1282is at the logic low level if the threshold voltage1472is lower than the sensing voltage1258. In yet another embodiment, if the sensing voltage1258is below the threshold voltage1472, the CCFL1208is determined to have an open circuit.

As discussed above and further emphasized here,FIGS. 12 and 13are merely examples, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. For example, the resistor1214is replaced by a voltage divider that can provide the DRC voltage (VDRC) to the voltage selector1220and the low brightness detector1244.

FIG. 15is a simplified diagram showing a system for controlling brightness of one or more CCFLs according to yet another embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications.

As shown inFIG. 15, the system1500includes the control chip1202, the power stage1204, the transformer1206, the CCFL1208, the resistor1209, the capacitors1207and1254, and resistors1514and1516. For example, the control chip1202includes the voltage generator1210, the voltage selector1220, the level shifter1230, the low brightness detector1244, the error amplifier1250, the gate driver1260, the logic component1270, the open-loop detector1280, and the protection component1290. In another example, the control chip1202also includes terminals1212,1222,1224,1252,1262, and1266.

In one embodiment, through the terminal1212, the voltage generator1210is coupled to the resistor1516, which is connected to the resistor1514. For example, the resistors1514and1516form a voltage divider, which provides the DRC voltage (VDRC) to the voltage selector1220and the low brightness detector1244. In another example, the DRC voltage (VDRC) can be adjusted by changing the resistors1514and1516.

In another embodiment, the minimum level (Dmin) for the duty cycle of the burst signal742is determined as follows:

where R3is the resistance value of the resistor1514, and R4is the resistance value of the resistor1516. j is a constant that is independent of R3and R4. As shown by Equation 2, the minimum of the brightness for the CCFL1208can be adjusted by changing the resistance values of resistors1514and1516, if the maximum of the brightness for the CCFL1208remains constant.

As discussed above and further emphasized here,FIGS. 7,11,12, and15are merely examples, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. For example, the CCFL708is replaced by multiple CCFLs. In another example, the CCFL1208is replaced by multiple CCFLs.

According to another embodiment, a system for adjusting brightness of one or more cold-cathode fluorescent lamps includes a voltage selector configured to receive a dimming voltage and a first threshold voltage and generate an output voltage. The output voltage is selected from a group consisting of the dimming voltage and the first threshold voltage. Additionally, the system includes an oscillator coupled to a first capacitor and configured to generate a ramp signal with the first capacitor, and a signal generator configured to receive the ramp signal and the output voltage and generate a first signal. The first signal corresponds to a lamp brightness level. Moreover, the system includes a brightness detector configured to receive the first signal and output a second signal. The second signal indicates whether the lamp brightness level is higher than a threshold brightness level. Also, the system includes a logic component configured to output a third signal, an open-loop detector configured to receive at least the second signal and the third signal and generate a fourth signal in response to at least the second signal and the third signal, and a protection component configured to receive the fourth signal and generate a protection signal based on at least information associated with the fourth signal. Additionally, the system includes an error amplifier coupled to a second capacitor and configured to receive the first signal and a sensing voltage and to generate a fifth signal based on at least information associated with the first signal and the sensing voltage, and a gate driver configured to receive the protection signal and the fifth signal and generate a drive signal. For example, the open-loop detector is further configured to receive the sensing voltage, the sensing voltage being associated with a lamp current flowing through at least one cold-cathode fluorescent lamp, and process information associated with the second signal and the third signal. In another example, the open-loop detector is further configured to, if the second signal satisfies one or more predetermined first conditions and the third signal satisfies one or more predetermined second conditions, determine whether the cold-cathode fluorescent lamp is associated with an open circuit based on at least information associated with the sensing voltage and output the fourth signal indicating whether the cold-cathode fluorescent lamp is associated with the open circuit. In yet another example, the open-loop detector is further configured to, if the second signal does not satisfy the one or more predetermined first conditions, output the fourth signal regardless of the sensing voltage, the fourth signal indicating that the cold-cathode fluorescent lamp is not associated with the open circuit. In yet another example, the open-loop detector is further configured to, if the third signal does not satisfy the one or more predetermined second conditions, output the fourth signal regardless of the sensing voltage, the fourth signal indicating that the cold-cathode fluorescent lamp is not associated with the open circuit. For example, the system is implemented according toFIG. 7,FIG. 8,FIG. 9,FIG. 10, and/orFIG. 11.

In another example, the open-loop detector is further configured to, if the second signal indicates that the lamp brightness level is higher than the threshold brightness level and the third signal satisfies the one or more predetermined second conditions, determine whether the cold-cathode fluorescent lamp is associated with the open circuit based on at least information associated with the sensing voltage and output the fourth signal indicating whether the cold-cathode fluorescent lamp is associated with the open circuit. In yet another example, the open-loop detector is further configured to, if the second signal indicates that the lamp brightness level is not higher than the threshold brightness level, output the fourth signal indicating that the cold-cathode fluorescent lamp is not associated with the open circuit.

In yet another example, the first signal is associated with one or more first pulses, each of the one or more first pulses corresponding to a first pulse width. In yet another example, the brightness detector is further configured to process information associated with the first signal, and generate a counter signal based on at least information associated with the first signal, the counter signal including one or more second pulses, each of the one or more second pulses corresponding to a threshold pulse width. In yet another example, the brightness detector is further configured to process information associated with the first pulse width and the threshold pulse width, and output the second signal based on at least information associated with the first pulse width and the threshold pulse width.

In yet another example, the brightness detector is further configured to determine whether the first pulse width is larger than the threshold pulse width, the threshold pulse width corresponding to the threshold brightness level. In yet another example, the brightness detector is further configured to, if the first pulse width is determined to be larger than the threshold pulse width, output the second signal indicating that the lamp brightness level is higher than the threshold brightness level.

In yet another example, the brightness detector includes a pulse generator configured to receive the first signal and generate a trigger signal, a counter component configured to receive the trigger signal and generate a counter signal, and a flip-flop component configured to receive the counter signal and the first signal and generate an output signal. In yet another example, the brightness detector further includes a NOT gate configured to receive the output signal and generate the second signal, and if the second signal is at a logic low level, the second signal indicates the lamp brightness level is higher than the threshold brightness level.

In yet another example, the open-loop detector includes a NOT gate configured to receive the second signal and generates a sixth signal, an AND gate configured to receive the sixth signal and the third signal and generate a seventh signal, and a comparator configured to receive the seventh signal, the sensing voltage, and a second threshold voltage and generate the fourth signal. In yet another example, the comparator is configured to, if the seventh signal is at a logic high level, generate the fourth signal at a logic low level regardless of the sensing voltage and the second threshold voltage. In yet another example, the comparator is further configured to, if the seventh signal is at a logic high level, generate the fourth signal at a logic low level if the sensing voltage is higher than the second threshold voltage, and generate the fourth signal at a logic high level if the sensing voltage is lower than the second threshold voltage. In yet another example, if the fourth signal is at the logic low level, the fourth signal indicates that the cold-cathode fluorescent lamp is not associated with the open circuit, and if the fourth signal is at the logic high level, the fourth signal indicates that the cold-cathode fluorescent lamp is associated with the open circuit.

In yet another example, the voltage selector is further configured to select the dimming voltage as the output voltage if the dimming voltage is higher than the first threshold voltage, and select the first threshold voltage as the output voltage if the dimming voltage is lower than the first threshold voltage. In yet another example, the voltage selector, the oscillator, the signal generator, the brightness detector, the logic component, the open-loop detector, the protection component, the error amplifier, and the gate driver are all located on a chip. In yet another example, the system for adjusting brightness of one or more cold-cathode fluorescent lamps further includes a voltage generator located on the chip, the chip including at least a first terminal and a second terminal. In yet another example, the voltage generator is configured to output a reference voltage to a voltage divider through the first terminal, the voltage divider being located outside the chip. In yet another example, the voltage divider is configured to output the first threshold voltage to the voltage selector through the second terminal. In yet another example, the protection component and the gate driver are further configured, if the fourth signal indicates that the cold-cathode fluorescent lamp is associated with the open circuit, generate the drive signal at a logic low level regardless of the fifth signal.

According to yet another embodiment, a method for adjusting brightness of one or more cold-cathode fluorescent lamps includes receiving a dimming voltage and a first threshold voltage. The dimming voltage is associated with a first magnitude, and the first threshold voltage is associated with a second magnitude. Additionally, the method includes generating an output voltage, the output voltage being selected from a group consisting of the dimming voltage and the first threshold voltage. Moreover, the method includes receiving the output voltage and a ramp signal, processing information associated with the output voltage and the ramp signal, and generating a first signal based on at least information associated with the output voltage and the ramp signal. The first signal corresponds to a lamp brightness level. Also, the method includes processing information associated with the first signal, and outputting a second signal based on at least information associated with the first signal. The second signal indicates whether the lamp brightness level is higher than a threshold brightness level. Additionally, the method includes receiving the second signal, a third signal, and a sensing voltage. The sensing voltage is associated with a lamp current flowing through at least one cold-cathode fluorescent lamp. Moreover, the method includes generating a fourth signal in response to at least the second signal and the third signal, receiving the first signal and the sensing voltage, generating a fifth signal based on at least information associated with the first signal and the sensing voltage, processing information associated with the fourth signal and the fifth signal, and generating a drive signal based on at least information associated with the fourth signal and the fifth signal. For example, the process for generating a fourth signal in response to at least the second signal and the third signal includes processing information associated with the second signal and the third signal. In another example, the process for generating a fourth signal in response to at least the second signal and the third signal includes, if the second signal satisfies one or more predetermined first conditions and the third signal satisfies one or more predetermined second conditions, determining whether the cold-cathode fluorescent lamp is associated with an open circuit based on at least information associated with the sensing voltage, and outputting the fourth signal indicating whether the cold-cathode fluorescent lamp is associated with the open circuit. In yet another example, the process for generating a fourth signal in response to at least the second signal and the third signal includes, if the second signal does not satisfy the one or more predetermined first conditions, outputting the fourth signal regardless of the sensing voltage, the fourth signal indicating that the cold-cathode fluorescent lamp is not associated with the open circuit. In yet another example, the process for generating a fourth signal in response to at least the second signal and the third signal includes, if the third signal does not satisfy the one or more predetermined second conditions, outputting the fourth signal regardless of the sensing voltage, the fourth signal indicating the cold-cathode fluorescent lamp is not associated with the open circuit. For example, the method is implemented according toFIG. 7,FIG. 8,FIG. 9,FIG. 10, and/orFIG. 11. In another example, the method further includes adjusting the first magnitude associated with the dimming voltage. In yet another example, the method further includes adjusting the second magnitude associated with the first threshold voltage.

According to yet another embodiment, a system for adjusting brightness of one or more cold-cathode fluorescent lamps includes a level shifter configured to receive a dimming voltage and generate a first output voltage based on at least information associated with the dimming voltage, and a voltage selector configured to receive the first output voltage and a first threshold voltage and generate a second output voltage. The second output voltage is selected from a group consisting of the first output voltage and the first threshold voltage, and the first threshold voltage corresponds to a lamp brightness level. Additionally, the system includes a brightness detector configured to receive the first threshold voltage and output a first signal, and the first signal indicates whether the lamp brightness level is higher than a threshold brightness level. Moreover, the system includes a logic component configured to output a second signal, and an open-loop detector configured to receive at least the first signal and the second signal and generate a third signal in response to at least the first signal and the second signal. Also, the system includes a protection component configured to receive the third signal and generate a protection signal based on at least information associated with the third signal, and an error amplifier coupled to a capacitor and configured to receive the second output voltage and a sensing voltage and to generate a fourth signal based on at least information associated with the second output voltage and the sensing voltage. Additionally, the system includes a gate driver configured to receive the protection signal and the fourth signal and generate a drive signal. For example, the open-loop detector is further configured to receive the sensing voltage, the sensing voltage being associated with a lamp current flowing through at least one cold-cathode fluorescent lamp, and process information associated with the first signal and the second signal. In another example, the open-loop detector is further configured to, if the first signal satisfies one or more predetermined first conditions and the second signal satisfies one or more predetermined second conditions, determine whether the cold-cathode fluorescent lamp is associated with an open circuit based on at least information associated with the sensing voltage and output the third signal indicating whether the cold-cathode fluorescent lamp is associated with the open circuit. In yet another example, the open-loop detector is further configured to, if the first signal does not satisfy the one or more predetermined first conditions, output the third signal regardless of the sensing voltage, the third signal indicating that the cold-cathode fluorescent lamp is not associated with the open circuit. In yet another example, the open-loop detector is further configured to, if the second signal does not satisfy the one or more predetermined second conditions, output the third signal regardless of the sensing voltage, the third signal indicating that the cold-cathode fluorescent lamp is not associated with the open circuit. For example, the system is implemented according toFIG. 12,FIG. 13,FIG. 14, and/orFIG. 15.

In another example, the open-loop detector is further configured to, if the first signal indicates that the lamp brightness level is higher than the threshold brightness level and the second signal satisfies the one or more predetermined second conditions, determine whether the cold-cathode fluorescent lamp is associated with the open circuit based on at least information associated with the sensing voltage and output the third signal indicating whether the cold-cathode fluorescent lamp is associated with the open circuit. In yet another example, the open-loop detector is further configured to, if the first signal indicates that the lamp brightness level is not higher than the threshold brightness level, output the third signal indicating that the cold-cathode fluorescent lamp is not associated with the open circuit.

In yet another example, the brightness detector includes a comparator, and the comparator is configured to receive the first threshold voltage and a second threshold voltage and output the first signal based on at least information associated with the first threshold voltage and the second threshold voltage, the second threshold voltage corresponding to the threshold brightness level. In yet another example, if the first signal is at a logic low level, the first signal indicates the lamp brightness level is higher than the threshold brightness level.

In yet another example, the level shifter, the voltage selector, the brightness detector, the logic component, the open-loop detector, the protection component, the error amplifier, the gate driver are all located on a chip. In yet another example, the system further includes a voltage generator located on the chip, the chip including at least a first terminal and a second terminal. In yet another example, the voltage generator is configured to output a reference voltage to a voltage divider through the first terminal, the voltage divider being located outside the chip. In yet another example, the voltage divider is configured to output the first threshold voltage to the voltage selector through the second terminal.

According to yet another embodiment, a method for adjusting brightness of one or more cold-cathode fluorescent lamps includes receiving a dimming voltage. The dimming voltage is associated with a first magnitude. Additionally, the method includes generating a first output voltage based on at least information associated with the dimming voltage, and receiving the first output voltage and a first threshold voltage. The first threshold voltage corresponds to a lamp brightness level and is associated with a second magnitude. Moreover, the method includes generating a second output voltage, the second output voltage being selected from a group consisting of the first output voltage and the first threshold voltage. Also, the method includes processing information associated with the first threshold voltage, and outputting a first signal based on at least information associated with the first threshold voltage. The first signal indicates whether the lamp brightness level is higher than a threshold brightness level. Additionally, the method includes receiving the first signal, a second signal, and a sensing voltage. The sensing voltage is associated with a lamp current flowing through at least one cold-cathode fluorescent lamp. Moreover, the method includes generating a third signal in response to at least the first signal and the second signal, receiving the second output voltage and a sensing voltage, generating a fourth signal based on at least information associated with the second output voltage and the sensing voltage, processing information associated with the third signal and the fourth signal, and generating a drive signal based on at least information associated with the third signal and the fourth signal. For example, the process for generating a third signal in response to at least the first signal and the second signal includes processing information associated with the first signal and the second signal. In another example, the process for generating a third signal in response to at least the first signal and the second signal includes, if the first signal satisfies one or more predetermined first conditions and the second signal satisfies one or more predetermined second conditions, determining whether the cold-cathode fluorescent lamp is associated with an open circuit based on at least information associated with the sensing voltage, and outputting the third signal indicating whether the cold-cathode fluorescent lamp is associated with the open circuit. In yet another example, the process for generating a third signal in response to at least the first signal and the second signal includes, if the first signal does not satisfy the one or more predetermined first conditions, outputting the third signal regardless of the sensing voltage, the third signal indicating that the cold-cathode fluorescent lamp is not associated with the open circuit. In yet another example, the process for generating a third signal in response to at least the first signal and the second signal includes, if the second signal does not satisfy the one or more predetermined second conditions, outputting the third signal regardless of the sensing voltage, the third signal indicating that the cold-cathode fluorescent lamp is not associated with the open circuit. For example, the method is implemented according toFIG. 12,FIG. 13,FIG. 14, and/orFIG. 15. In another example, the method further includes adjusting the first magnitude associated with the dimming voltage. In yet another example, the method further includes adjusting the second magnitude associated with the first threshold voltage.