Parallel dispatching of multi-operation instructions in a multi-slice computer processor

Parallel dispatching of multi-operation instructions in a multi-slice computer processor, including: determining whether an instruction must be broken into a plurality of smaller operations; marking each of the smaller operations as instructions to be dispatched in parallel; determining whether each of the operations can be dispatched to distinct instruction issue queues during a same clock cycle; and responsive to determining that each of the operations can be dispatched to distinct instruction issue queues during the same clock cycle, dispatching each of the operations to distinct instruction issue queues during the same clock cycle.

BACKGROUND

Field of the Invention

The field of the invention is data processing, or, more specifically, methods, computer processors, and systems for parallel dispatching of multi-operation instructions.

Description of Related Art

Modern computer systems can include computer processors that support an instruction set that can include instructions that must be segmented into smaller operations. In order to support such instructions, computer processors can include dedicated registers that are utilized to store intermediate results of each of the smaller operations. Such dedicated registers may be expensive and space consuming.

SUMMARY

Methods, computer processors, and systems for parallel dispatching of multi-operation instructions in a multi-slice computer processor, including: determining whether an instruction must be broken into a plurality of smaller operations; marking each of the smaller operations as instructions to be dispatched in parallel; determining whether each of the operations can be dispatched to distinct instruction issue queues during a same clock cycle; and responsive to determining that each of the operations can be dispatched to distinct instruction issue queues during the same clock cycle, dispatching each of the operations to distinct instruction issue queues during the same clock cycle.

The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular descriptions of example embodiments of the invention as illustrated in the accompanying drawings wherein like reference numbers generally represent like parts of example embodiments of the invention.

DETAILED DESCRIPTION

Example methods, computer processors, and systems for parallel dispatching of multi-operation instructions in accordance with the present invention are described with reference to the accompanying drawings, beginning withFIG. 1.FIG. 1sets forth a block diagram of an example system configured for parallel dispatching of multi-operation instructions in a multi-slice computer processor according to embodiments of the present disclosure. The system ofFIG. 1includes an example of automated computing machinery in the form of a computer (152).

The computer (152) ofFIG. 1includes at least one computer processor (156) or ‘CPU’ as well as random access memory (168) (‘RAM’) which is connected through a high speed memory bus (166) and bus adapter (158) to processor (156) and to other components of the computer (152).

The example computer processor (156) ofFIG. 1may be implemented as a multi-slice processor. The term ‘multi-slice’ as used in this specification refers to a processor having a plurality of similar or identical sets of components, where each set may operate independently of all the other sets or in concert with the one or more of the other sets. The multi-slice processor (156) ofFIG. 1, for example, includes several execution slices (‘ES’) and several load/store slices (‘LSS’). Each execution slice may be configured to provide components that support execution of instructions: an issue queue, general purpose registers, a history buffer, an arithmetic logic unit (including a vector scalar unit, a floating point unit, and others), and the like. Each of the load/store slices may be configured with components that support data movement operations such as loading of data from cache or memory or storing data in cache or memory. In some embodiments, each of the load/store slices includes a data cache. The load/store slices are coupled to the execution slices through a results bus. In some embodiments, each execution slice may be associated with a single load/store slice to form a single processor slice. In some embodiments, multiple processor slices may be configured to operate together.

The example multi-slice processor (156) ofFIG. 1may also include, in addition to the execution and load/store slices, other processor components. In the system ofFIG. 1, the multi-slice processor (156) includes fetch logic, dispatch logic, and branch prediction logic. Further, although in some embodiments each load/store slice includes cache memory, the multi-slice processor (156) may also include cache accessible by any or all of the processor slices.

Although the multi-slice processor (156) in the example ofFIG. 1is shown to be coupled to RAM (168) through a front side bus (162), a bus adapter (158) and a high speed memory bus (166), readers of skill in the art will recognize that such configuration is only an example implementation. In fact, the multi-slice processor (156) may be coupled to other components of a computer system in a variety of configurations. For example, the multi-slice processor (156) in some embodiments may include a memory controller configured for direct coupling to a memory bus (166). In some embodiments, the multi-slice processor (156) may support direct peripheral connections, such as PCIe connections and the like.

Stored in RAM (168) in the example computer (152) is a data processing application (102), a module of computer program instructions that when executed by the multi-slice processor (156) may provide any number of data processing tasks. Examples of such data processing applications may include a word processing application, a spreadsheet application, a database management application, a media library application, a web server application, and so on as will occur to readers of skill in the art. Also stored in RAM (168) is an operating system (154). Operating systems useful in computers configured for reducing power consumption in a multi-slice computer processor according to embodiments of the present disclosure include UNIX™, Linux™, Microsoft Windows™, AIX®, IBM's z/OS™, and others as will occur to those of skill in the art. The operating system (154) and data processing application (102) in the example ofFIG. 1are shown in RAM (168), but many components of such software typically are stored in non-volatile memory also, such as, for example, on a disk drive (170).

For further explanation,FIG. 2sets forth a block diagram of a portion of a multi-slice processor, also referred to as a multi-slice computer processor, according to embodiments of the present disclosure. The multi-slice processor in the example ofFIG. 2includes a dispatch network (202). The dispatch network (202) includes logic configured to dispatch instructions for execution among execution slices.

The multi-slice processor in the example ofFIG. 2also includes a number of execution slices (204a,204b-204n). Each execution slice includes general purpose registers (206) and a history buffer (208). The general purpose registers and history buffer may sometimes be referred to as the mapping facility, as the registers are utilized for register renaming and support logical registers.

The general purpose registers (206) are configured to store the youngest instruction directed to a particular logical register and the result of the execution of the instruction. A logical register is an abstraction of a physical register that enables out-of-order execution of instructions that target the same physical register.

When a younger instruction directed to the same particular logical register is received, the entry in the general purpose register is moved to the history buffer. The history buffer (208) may be configured to store many instructions directed to the same logical register. That is, the general purpose register is generally configured to store a single, youngest instruction for each logical register while the history buffer may many, non-youngest instructions for each logical register.

Each execution slice (204) of the multi-slice processor ofFIG. 2also includes an execution reservation station (210). The execution reservation station (210) may be configured to issue instructions for execution. The execution reservation station (210) may include an issue queue. The issue queue may include an entry for each operand of an instruction. The execution reservation station may issue the operands for execution by an arithmetic logic unit (212) or to a load slice (222a,222b,222c) via the results bus (220).

The arithmetic logic unit depicted in the example ofFIG. 2may be composed of many components, such as add logic, multiply logic, floating point units, vector/scalar units, and so on. Once an arithmetic logic unit executes an operand, the result of the execution may be stored in the result buffer (214) or provided on the results bus (220) through a multiplexer (216).

The results bus may be configured in a variety of manners and be of composed in a variety of sizes. In some instances, each execution slice may be configured to provide results on a single bus line of the results bus (220). In a similar manner, each load/store slice may be configured to provide results on a single bus line of the results bus (220). In such a configuration, a multi-slice processor with four processor slices may have a results bus with eight bus lines—four bus lines assigned to each of the four load/store slices and four bus lines assigned to each of the four execution slices. Each of the execution slices may be configured to snoop results on any of the bus lines of the results bus.

The multi-slice processor in the example ofFIG. 2also includes a number of load/store slices (222a,222b-222n). Each load/store slice includes a queue (224), a multiplexer (228), a data cache (232), unaligned data logic (234) and formatting logic (226). The queue receives load and store operations to be carried out by the load/store slice (222).

The unaligned data logic (234) of each slice is coupled to the unaligned data logic of another slice through the unaligned data line (236). The unaligned data logic (234) enables data to be stored and retrieved across multiple load/store slices. The formatting logic (226) formats data into a form that may be returned on the results bus (220) to an execution slice as a result of a load instruction.

The multi-slice processor in the example ofFIG. 2may implement an architected register file using the general purpose registers (206), as each register may be used to hold a single entry in the architected register file. The multi-slice processor in the example ofFIG. 2may also implement a re-order buffer using the general purpose registers (206), as each register may be used to hold a single entry in the re-order buffer.

The multi-slice processor in the example ofFIG. 2may be configured for parallel dispatching of multi-operation instructions according to embodiments of the present disclosure by: determining whether an instruction must be broken into a plurality of smaller operations; breaking the instruction into a plurality of smaller operations; marking each of the smaller operations as instructions to be dispatched in parallel; marking the last operation as a terminating operation; designating, as a source register for the younger operation, a target register for the older operation; determining whether each of the operations can be dispatched to distinct instruction issue queues during a same clock cycle; dispatching each of the operations to distinct instruction issue queues during the same clock cycle in response to determining that each of the operations can be dispatched to distinct instruction issue queues during the same clock cycle; and dispatching each of the operations to distinct instruction issue queues during a subsequent clock cycle in response to determining that each of the operations cannot be dispatched to distinct instruction issue queues during the same clock cycle, as will be described in greater detail below.

For further explanation,FIG. 3sets forth a block diagram of logic within a multi-slice computer processor that is useful for parallel dispatching of multi-operation instructions according to embodiments of the present invention. The logic depicted inFIG. 3may reside, entirely or in part, above the dispatch network described above with reference toFIG. 2and may utilize the dispatch network to dispatch instructions to slices within the multi-slice computer processor.

The example depicted inFIG. 3includes a decoder (302) that is capable of decoding three instructions simultaneously and transmitting information needed to dispatch three instructions simultaneously to the dispatcher (322). In the example depicted inFIG. 3, decoder (302) that is capable of decoding three instructions simultaneously and transmitting information needed to dispatch three instructions simultaneously to the dispatcher (322) via three sets of hardware and data communications links between the decoder (302) and the dispatcher (322) which are labelled herein as OP0(304), OP1(306), and OP2(308). In the example depicted inFIG. 3, each set of data communications links between the decoder (302) and the dispatcher (322) includes a dispatch-in-parallel (310,314,318) signal line available to assert a dispatch-in-parallel signal for a particular instruction whose information is being sent from the decoder (302) to the dispatcher (322), as will be described in greater detail below. In addition, each set of data communications links between the decoder (302) and the dispatcher (322) includes a terminating operation (312,316,320) signal line available to assert a signal indicating whether an particular instruction is whose information is being sent from the decoder (302) to the dispatcher (322) is a terminating instruction in a sequence of instructions, as will be described in greater detail below.

The example method depicted inFIG. 3also includes a dispatcher (322) that includes three distinct slots, slot0(324), slot1(326), and slot2(328), for dispatching instructions to issues queues (338,340,342). The dispatcher (322) may issue instructions to issue queues (338,340,342) directly through a network of target/source steering multiplexers (344) that are used to select one or more target registers where an instruction to be issued to an instruction queue (338,340,342) should write data generated by executing the instruction, as well as one or more source registers where a particular instruction can find operands utilized during execution of the instruction. Given that the dispatcher (322) can dispatch three instructions in parallel, the target/source steering multiplexers (344) includes three slots, slot0(332), slot1(334), and slot2(336), that are linked to each instruction queue (338,340,342). The dispatcher (322) may also issue instructions to issue queues (338,340,342) indirectly through the use of a mapper (330) that is coupled to the network of target/source steering multiplexers (344). Readers will appreciate that because source registers and target registers are set prior to dispatching instructions into an execution queue, once an instruction is dispatched into an instruction queue, the source registers and target registers may not be repurposed for use by other instructions until the dispatched instructions have finished executing. Readers will further appreciate that although three paths are illustrated in the example depicted inFIG. 3, any plurality of paths are well within embodiments of the present disclosure.

For further explanation,FIG. 4sets forth a flow chart illustrating an example method for parallel dispatching of multi-operation instructions in a multi-slice computer processor (404) according to embodiments of the present disclosure. Although depicted in less detail, the multi-slice computer processor (404) depicted inFIG. 4may be similar to the multi-slice computer processors described with reference to the preceding figures, and components within the multi-slice computer processor (404) may also be similar to the components described above with reference to the preceding figures.

The example method depicted inFIG. 4includes determining (406) whether an instruction (402) must be broken into a plurality of smaller operations (412,416). Readers will appreciate that some instructions may be sufficiently complex that executing the instruction (402) may require the execution of a plurality of smaller operations (412,416) over the course of multiple clock cycles. For example, an instruction retrieve the contents from multiple registers, perform some sort of logical computation on the contents of each register, and write a value generated in response to the logical computation to another register may be broken into plurality of smaller operations (412,416) where a first operation retrieves the contents from multiple registers, a second operation performs the logical computation on the contents of each register, and a third operation writes a value generated in response to the logical computation to another register. Readers will appreciate that this example is for explanatory purposes only as the particular details of an instruction set will dictate whether the instruction set includes instructions (402) that must be broken into a plurality of smaller operations (412,416).

In the example method depicted inFIG. 4, determining (406) whether an instruction (402) must be broken into a plurality of smaller operations (412,416) may be carried out, for example, by an instruction decoder that is included as a component within the multi-slice computer processor (404). The instruction decoder may be embodied, for example, as a circuit or other piece computer logic configured to read the instruction (402) in from memory and send the component pieces of that instruction to the necessary destination. The instruction decoder may be configured to determine (406) whether an instruction (402) must be broken into a plurality of smaller operations (412,416), for example, by maintaining or otherwise accessing information that associates identifiers for instructions (e.g., an opcode) with information describing whether instructions with matching identifiers must be broken into a plurality of smaller operations, information that describes the number of smaller operations that instructions with matching identifiers must be broken into, information identifying which specific smaller operations that instructions with matching identifiers must be broken into, and so on.

The example method depicted inFIG. 4also includes breaking (410) the instruction (402) into a plurality of smaller operations (412,416). In the example method depicted inFIG. 4, breaking (410) the instruction (402) into a plurality of smaller operations (412,416) may be carried out in response to affirmatively (408) determining that the instruction (402) must be broken into a plurality of smaller operations (412,416). Breaking (410) the instruction (402) into a plurality of smaller operations (412,416) may be carried out, for example, by the instruction decoder mentioned above. In such an example, the instruction decoder may be configured to maintain or otherwise access information that associates identifiers for instructions (e.g., an opcode) with information describing which specific smaller operations that instructions with matching identifiers must be broken into. The instruction decoder may therefore break (410) the instruction (402) into a plurality of smaller operations (412,416) by creating the specific smaller operations that an instruction with an identifier that matches the identifier of the instruction (402) must be broken into. The instruction decoder may be configured to include one or more parameters contained in the instruction (402) such as, for example, an identification of one or more source registers, an identification of a target register, and so on, as parameters in one or more of the smaller operations (412,416).

The example method depicted inFIG. 4also includes marking (420) each of the smaller operations (412,416) as instructions to be dispatched in parallel. In the example method depicted inFIG. 4, each of the smaller operations (412,416) may include a dispatch-in-parallel signal (414,418) that can be asserted by the instruction decoder to signal that the smaller operations (412,416) do or do not need to be dispatched in parallel. The dispatch-in-parallel signal (414,418) may be embodied, for example, as a bit located at particular location within a collection of bits that is used to describe the smaller operation (412,416). Such a collection of bits may include bits at a particular location that identify an opcode for the smaller operation (412,416), bits at a particular location that identify the location of operands for the smaller operation (412,416), and so on. As such, marking (420) each of the smaller operations (412,416) as instructions to be dispatched in parallel may be carried out by setting the value of the bit that represents the dispatch-in-parallel signal (414,418) to a value that indicates that the smaller operations (412,416) are to be dispatched in parallel.

The example method depicted inFIG. 4also includes determining (422) whether each of the smaller operations (412,416) can be dispatched to distinct instruction issue queues (436,438) during a same clock cycle. In the example method depicted inFIG. 4, determining (422) whether each of the operations (412,416) can be dispatched to distinct instruction issue queues (436,438) during a same clock cycle may be carried out, for example, by an instruction dispatcher. The instruction dispatcher may be embodied, for example, as a circuit or other piece computer logic configured to load instructions into instruction issue queues (436,438) from which instructions are retrieved and executed by execution units. The instruction dispatcher may be configured to determine (422) whether each of the operations (412,416) can be dispatched to distinct instruction issue queues (436,438) during a same clock cycle, for example, by determining whether a sufficient number of issue queues (436,438) have an available slots such that each of the smaller operations (412,416) can be dispatched to distinct instruction issue queues (436,438) during a same clock cycle.

Consider an example in which a particular instruction (402) is broken into two smaller operations (412,416). In such an example, assume that the multi-slice computer processor (404) includes two instruction issue queues (436,438). When one or both of the instruction issue queues (436,438) do not have an available slot (i.e., an instruction has already been dispatched to the next slot in one or both queues), the instruction dispatcher may determining that each of the smaller operations (412,416) cannot (424) be dispatched to distinct instruction issue queues (436,438) during a same clock cycle. When both of the instruction issue queues (436,438) do have an available slot (i.e., an instruction has not already been dispatched to the next slot in either queue), the instruction dispatcher may affirmatively (426) determine that each of the smaller operations (412,416) can be dispatched to distinct instruction issue queues (436,438) during a same clock cycle.

Readers will appreciate that the multi-slice computer processor (404) may include multiple instruction issue queues (436,438) because the multi-slice computer processor (404) includes multiple slices. As such, the multi-slice computer processor (404) may also include multiple execution units, each of which executes instructions contained in a distinct instruction issue queue (436,438). For example, the execution unit within a first slice of the multi-slice computer processor (404) may retrieve and execute instructions contained in a first instruction issue queue (436) while the execution unit within a second slice of the multi-slice computer processor (404) may retrieve and execute instructions contained in a second instruction issue queue (438).

The example method depicted inFIG. 4also includes dispatching (430) each of the operations (432,434) to distinct instruction issue queues (436,438) during the same clock cycle. The multi-slice computer processor (404) depicted inFIG. 4may be configured to dispatch instructions into an instruction issue queue (436,438) for each slice of the multi-slice computer processor (404) every clock cycle. For example, during a single clock cycle, a first instruction may be dispatched to an instruction issue queue (436) for a first slice of the multi-slice computer processor (404), a second instruction may be dispatched to an instruction issue queue (438) for a second slice of the multi-slice computer processor (404), and so on. In the example method depicted inFIG. 4, dispatching (430) each of the operations (432,434) to distinct instruction issue queues (436,438) during the same clock cycle may be carried out in response to affirmatively (426) determining that each of the operations (432,434) can be dispatched to distinct instruction issue queues (436,438) during the same clock cycle.

The example method depicted inFIG. 4also includes dispatching (428) each of the operations (432,434) to distinct instruction issue queues (436,438) during a subsequent clock cycle. In the example method depicted inFIG. 4, dispatching (428) each of the operations (432,434) to distinct instruction issue queues (436,438) during a subsequent clock cycle may be carried out in response to determining that each of the operations (432,434) cannot (424) be dispatched to distinct instruction issue queues (436,438) during the same clock cycle.

Consider an example in which the multi-slice computer processor (404) retrieves a particular instruction (402), determines (406) that the instruction (402) must be broken into a plurality of smaller operations (412,416), and breaks (410) the instruction (402) into two smaller operations (412,416). In such an example, further assume that the multi-slice computer processor (404) determines (422) that each of the smaller operations (412,416) cannot (424) be dispatched to distinct instruction issue queues (436,438) during clock cycle0, because only one instruction issue queues (436) has an available slot. In such an example, the multi-slice computer processor (404) may dispatch (428) each of the operations (432,434) to distinct instruction issue queues (436,438) during a subsequent clock cycle by waiting until clock cycle1to dispatch (428) each of the operations (432,434) to distinct instruction issue queues (436,438). In such a way, even though one instruction issue queues (436) had an available slot during clock cycle0and the instruction dispatcher had two operations (432,434) available for dispatching, the multi-slice computer processor (404) may delay the dispatching of either operation (432,434) until clock cycle1so that the two operations (432,434) can be dispatched in parallel.

For further explanation,FIG. 5sets forth a flow chart illustrating an additional example method for parallel dispatching of multi-operation instructions in a multi-slice computer processor (404) according to embodiments of the present disclosure. The example method depicted inFIG. 5is similar to the example method depicted inFIG. 4, as the example method depicted inFIG. 5also includes determining (406) whether an instruction (402) must be broken into a plurality of smaller operations (412,416), breaking (410) the instruction (402) into a plurality of smaller operations (412,416), marking (420) each of the smaller operations (412,416) as instructions to be dispatched in parallel, determining (422) whether each of the smaller operations (412,416) can be dispatched to distinct instruction issue queues (436,438) during a same clock cycle, dispatching (430) each of the operations (432,434) to distinct instruction issue queues (436,438) during the same clock cycle in response to affirmatively (426) determining that each of the operations (432,434) can be dispatched to distinct instruction issue queues (436,438) during the same clock cycle, and dispatching (428) each of the operations (432,434) to distinct instruction issue queues (436,438) during a subsequent clock cycle in response to determining that each of the operations (432,434) cannot (424) be dispatched to distinct instruction issue queues (436,438) during the same clock cycle.

The example method depicted inFIG. 5also includes marking (502) the last operation as a terminating operation. As described above, an instruction (402) retrieved by the multi-slice computer processor (404) may be broken into a plurality of smaller operations (412,416). Such smaller operations (412,416) may need to be executed in a particular order to ensure proper execution of the instruction (402). Consider the example described above in which the multi-slice computer processor (404) supports an instruction set that includes an instruction to retrieve the contents from multiple registers, perform some sort of logical computation on the contents of each register, and write a value generated in response to the logical computation to another register may be broken into plurality of smaller operations (412,416). In such an example, a first operation may be executed that retrieves the contents from multiple registers, a second operation may subsequently be executed that performs the logical computation on the contents of each register, and a third operation may then be executed that writes a value generated in response to the logical computation to another register. In such an example, the last operation to be executed in the sequence may be marked (502) as the terminating operation.

In the example method depicted inFIG. 5, marking (502) the last operation as a terminating operation may be carried out, for example, through the use of one or more values contained in the smaller operation itself. The example method depicted inFIG. 5includes, as an example of a value contained in the smaller operation itself, a termination bit (506,512) in each smaller operation (412,416). Such a termination bit (506,512) may be embodied as a bit located at particular location within a collection of bits that is used to describe the smaller operation (412,416). The multi-slice computer processor (404) may be configured such that a termination bit (506,512) of a first value may be interpreted as an indication that the smaller operation (412,416) is a terminating operation while a termination bit (506,512) of a second value may be interpreted as an indication that the smaller operation (412,416) is not a terminating operation. In such an example, marking (502) the last operation as a terminating operation may be carried out be setting the value of the termination bit (506,512) in the smaller operation that is to be executed last to the appropriate value, and also setting the value of the termination bit (506,512) in each smaller operation that will not be executed last to the appropriate value. The multi-slice computer processor (404) may be able to identify the last operation within a sequence given that the instruction (402) will be broken into a known group of smaller operations (412,416) whose execution order may also be known and provided to the multi-slice computer processor (404).

In the example method depicted inFIG. 5, a younger operation can utilize results generated by an older operation. Readers will appreciate that the designation of smaller operations (412,416) as being ‘younger’ or ‘older’ is determined by the order in which the smaller operations (412,416) will execute. For example, if a first smaller operation (412) executes at a particular time and a second smaller operation (416) executes at a later time, the first smaller operation (412) is described as being ‘older’ than the second smaller operation (416). Consider the example described above in which the multi-slice computer processor (404) supports an instruction set that includes an instruction to retrieve the contents from multiple registers, perform some sort of logical computation on the contents of each register, and write a value generated in response to the logical computation to another register may be broken into plurality of smaller operations (412,416). In such an example, a first operation may be executed that retrieves the contents from multiple registers, a second operation may subsequently be executed that performs the logical computation on the contents of each register, and a third operation may then be executed that writes a value generated in response to the logical computation to another register. In this example, the first operation would be designated as the oldest operation while the third operation would be designated as the youngest operation. Readers will appreciate that this example also includes an example where a younger operation can utilize results generated by an older operation, as the second operation utilizes values that are retrieved from multiple registers by the first operation.

The method depicted inFIG. 5can include designating (504), as a location from which the younger operation is to retrieve source data, a location at which the multi-slice computer processor (404) is to place resultant data generated by executing the older operation. Designating (504), as a location from which the younger operation is to retrieve source data, a location at which the multi-slice computer processor (404) is to place resultant data generated by executing the older operation may be carried out, for example, through the use of one or more fields contained with the smaller operations (412,416) themselves. For example, the smaller operations (412,416) depicted inFIG. 5include a source location (508,510) field for identifying the location of one or more source operands for the smaller operations (412,416), as well as a target location (510,516) field for identifying the location where data generated by executing the smaller operations (412,416) should be placed. In such an example, designating (504), as a location from which the younger operation is to retrieve source data, a location at which the multi-slice computer processor (404) is to place resultant data generated by executing the older operation may be carried out by placing the same value (e.g., address, register number) in the source location (508,514) field for the younger operation and the target location (510,516) field for the older operation.

In the example method depicted inFIG. 5, the location from which the younger operation is to retrieve source data (which is also the location at which the multi-slice computer processor (404) is to place resultant data generated by executing the older operation) is available for use in executing instructions that do not need to be broken into a plurality of smaller operations. That is, unlike embodiments described in the description of related art section contained herein, the location from which the younger operation is to retrieve source data (which is also the location at which the multi-slice computer processor (404) is to place resultant data generated by executing the older operation) is not a dedicated register that is utilized to store intermediate results of each of the smaller operations.

For further explanation,FIG. 6sets forth a flow chart illustrating an additional example method for parallel dispatching of multi-operation instructions in a multi-slice computer processor (404) according to embodiments of the present disclosure. The example method depicted inFIG. 6is similar to the example method depicted inFIG. 4, as the example method depicted inFIG. 6also includes determining (406) whether an instruction (402) must be broken into a plurality of smaller operations (412,416), breaking (410) the instruction (402) into a plurality of smaller operations (412,416), marking (420) each of the smaller operations (412,416) as instructions to be dispatched in parallel, determining (422) whether each of the smaller operations (412,416) can be dispatched to distinct instruction issue queues (436,438) during a same clock cycle, dispatching (430) each of the operations (432,434) to distinct instruction issue queues (436,438) during the same clock cycle in response to affirmatively (426) determining that each of the operations (432,434) can be dispatched to distinct instruction issue queues (436,438) during the same clock cycle, and dispatching (428) each of the operations (432,434) to distinct instruction issue queues (436,438) during a subsequent clock cycle in response to determining that each of the operations (432,434) cannot (424) be dispatched to distinct instruction issue queues (436,438) during the same clock cycle.

In the example method depicted inFIG. 6, an older operation can modify a register utilized as a source operand by a younger operation. In an example where the younger operation needs the original contents of such a register, rather than the intermediate contents of such a register that would result from the older operation updating the contents of the register, the multi-slice computer processor may be configured to designate (602), as a value for the source operand utilized by the younger operation, contents of the register prior to the register being modified by the older operation.

The present invention may be a system, a method, a computer processor, and/or a computer program product. The computer program product may include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out aspects of the present invention.