Semiconductor device and method of fabricating the same, circuit board, and electronic instrument

A semiconductor device has: a semiconductor substrate having an integrated circuit and an electrode that is connected electrically to the integrated circuit; a resin layer formed on a surface of the semiconductor substrate on which the electrode is formed, but avoiding the electrode; and a wiring layer that is connected electrically to the electrode and has a land which is located on the resin layer. A penetrating hole that exposes the resin layer is formed in the land.

BACKGROUND OF THE INVENTION

The present invention relates to a semiconductor device, a method of fabrication of the semiconductor device, a circuit board, together with an electronic instrument.

When a semiconductor device has been mounted on a substrate, it is important to relieve the stresses applied to the electrical connective portions of both components. These stresses are caused by the difference in the coefficients of thermal expansion of the semiconductor chip and the substrate. Since this is not possible to relieve such stresses sufficiently in the prior art, this leads to destruction of the external terminals (solder balls) of the semiconductor device and breakage of the wiring. In particular, this is expected to improve the reliability of wafer-level chip scale packaging (CSP), used to create packages in wafer units.

BRIEF SUMMARY OF THE INVENTION

According to a first aspect of the present invention, there is provided a semiconductor device comprising:

a semiconductor substrate having an integrated circuit and an electrode that is connected electrically to the integrated circuit;

a resin layer formed on a surface of the semiconductor substrate on which the electrode is formed, avoiding the electrode; and

a wiring layer which is electrically connected to the electrode and has a land formed on the resin layer,

wherein a penetrating hole that exposes the resin layer is formed in the land.

According to a second aspect of the present invention, there is provided a circuit board on which is mounted the above-described semiconductor device.

According to a third aspect of the present invention, there is provided an electronic instrument having the above-described semiconductor device.

According to a fourth aspect of the present invention, there is provided a method of fabricating a semiconductor device, the method comprising:

forming a resin layer on a surface of a semiconductor substrate on which is formed an electrode that is connected electrically to an integrated circuit of the semiconductor substrate, avoiding the electrode; and

forming a wiring layer which is electrically connected to the electrode and has a land formed on the resin layer,

wherein a penetrating hole that exposes the resin layer is formed in the land.

DETAILED DESCRIPTION OF THE EMBODIMENT

Following embodiments improve the reliability of a semiconductor device by relieving stresses created in the semiconductor device.

(1) According to one embodiment of the present invention, there is provided a semiconductor device comprising:

a semiconductor substrate having an integrated circuit and an electrode that is connected electrically to the integrated circuit;

a resin layer formed on a surface of the semiconductor substrate on which the electrode is formed, avoiding the electrode; and

a wiring layer which is electrically connected to the electrode and has a land formed on the resin layer,

wherein a penetrating hole that exposes the resin layer is formed in the land.

This embodiment enables the formation of a penetrating hole that exposes the resin layer, in the land. Since the land can deform readily, this makes it possible to relieve the stresses generated in the semiconductor device. It is therefore possible to prevent faults such as breaking of the wiring layer or destruction of external terminals, enabling an improvement in the reliability of the semiconductor device.

(2) In this semiconductor device, the shape of the land in plan view may be substantially circular.

(3) In this semiconductor device, the penetrating hole may be an elongated hole.

(4) In this semiconductor device,

the penetrating hole may be an elongated hole extending along the outer edge portion of the land.

This makes it possible to form a penetrating hole that avoids the central portion of the land.

(5) In this semiconductor device, a plurality of the penetrating holes may be formed in the land.

This makes it even easier for the land to deform.

(6) In this semiconductor device, the penetrating holes may be arranged along the outer edge portion of the land.

Since this makes it easy for the central portion of the land to move in response to stresses, it enables effective relief of stresses.

(7) In this semiconductor device, the penetrating holes may be disposed with substantially equal distances between adjacent holes.

This facilitates deformation of the land in response to stresses applied in all directions in the plane of the land.

(8) In this semiconductor device, the land may be formed on an upper surface of the resin layer.

(9) In this semiconductor device, a plurality of the resin layers may be formed at different positions in plan view on the semiconductor substrate, and the land may be formed integrally with an upper surface and a side surface of one of the resin layers.

(10) In this semiconductor device, the penetrating hole may be formed in a portion of the land covering the side surface of the resin layer.

(11) In this semiconductor device, the side surface of the resin layer may be tapered.

This makes it easy to form a penetrating hole in a portion of the land covering the side surface of the resin layer.

(12) In this semiconductor device, the resin layer may have substantially a shape of conical frustum.

(13) This semiconductor device may further comprise:

a resist layer which is formed on a surface of the semiconductor substrate on which the electrode is formed, and has an aperture that causes at least part of the land to be exposed.

(14) In this semiconductor device, the shape of the aperture of the resist layer in plan view may be substantially circular.

(15) In this semiconductor device, the resist layer may fill at least part of the penetrating hole.

(16) In this semiconductor device, the resist layer may be formed to fill the penetrating hole, and part of an edge of the penetrating hole may be substantially in contact with an edge of the aperture of the resist layer.

(17) This semiconductor device may further comprise an external terminal provided on the land.

(18) This semiconductor device may further comprise a second resin layer that avoids an upper portion of the external terminal but covers at least a lower portion of the external terminal.

(19) In this semiconductor device, the semiconductor substrate may be a semiconductor chip.

(20) In this semiconductor device, the semiconductor substrate may be a semiconductor wafer.

(21) According to another embodiment of the present invention, there is provided a circuit board on which is mounted the above-described semiconductor device.

(22) According to further embodiment of the present invention, there is provided an electronic instrument comprising the above-described semiconductor device.

(23) According to still another embodiment of the present invention, there is provided a method of fabricating a semiconductor device, the method comprising:

forming a resin layer on a surface of a semiconductor substrate on which is formed an electrode that is connected electrically to an integrated circuit of the semiconductor substrate, avoiding the electrode; and

forming a wiring layer which is electrically connected to the electrode and has a land formed on the resin layer,

wherein a penetrating hole that exposes the resin layer is formed in the land.

In this embodiment, a penetrating hole that exposes the resin layer is formed in the land. Since this makes it easy for the land to deform, it is possible to relieve stresses generated in the semiconductor device. It is therefore possible to prevent faults such as breakage of the wiring layer or destruction of the external terminals, thus enabling an improvement in the reliability of the semiconductor device.

(24) In this method of fabricating a semiconductor device, the penetrating hole may be formed simultaneously with the wiring layer.

This makes it possible to fabricate the semiconductor device with fewer steps.

(25) In this method of fabricating a semiconductor device, a plurality of the penetrating holes may be formed in the land.

This makes it even easier for the land to deform.

(26) This method of fabricating a semiconductor device may further comprise:

forming a resist layer on a surface of the semiconductor substrate on which the electrode is formed, the resist layer having an aperture that causes at least part of the land to be exposed.

(27) This method of fabricating a semiconductor device may further comprise forming an external terminal on the land.

(28) This method of fabricating a semiconductor device may comprise:

forming a plurality of the resin layers at different positions in plan view on the semiconductor substrate;

providing a material of the wiring layer to cover at least the resin layer;

patterning a plated layer as a mask on the material of the wiring layer; and

forming the wiring layer and the penetrating hole by etching the material of the wiring layer and the plated layer in such a manner that portions of the material of the wiring layer that are covered by the plated layer remain.

Embodiments of the present invention are described below with reference to the accompanying figures. It should be noted, however, that the present invention is not limited to the embodiments below.

First Embodiment

A semiconductor device in accordance with a first embodiment of the present invention is shown inFIGS. 1to4.FIG. 1is a plan view of the semiconductor device,FIG. 2is a partial enlarged section taken along the line II—II ofFIG. 1, andFIG. 3is a partial enlarged section taken along the line III—III of FIG.1.FIG. 4is illustrative of the relationship between a land and a resist layer, with parts of the semiconductor device (such as the wiring layer and external terminals) omitted. Note that variant examples of this embodiment are shown inFIGS. 5to8. A semiconductor device1includes a semiconductor substrate10, a resin layer20, and a wiring layer30.

The semiconductor substrate10would usually be a silicon substrate, but the material thereof is not limited thereto. As shown inFIG. 1, the semiconductor substrate10could also be a semiconductor chip. The shape of the semiconductor chip would usually be a rectangular solid, but it could also be a cube or a sphere.

As a variant example, the semiconductor substrate10could be a semiconductor wafer. A semiconductor wafer is a collection of areas that become a plurality of semiconductor chips (see FIG.9).

As shown inFIG. 2one or more integrated circuits12are formed in the semiconductor substrate10. Each integrated circuit12could be formed on one surface side of the semiconductor substrate10. If there are semiconductor chips in the semiconductor substrate10, one integrated circuit12could be formed thereon. A plurality of electrodes14are formed for each integrated circuit12. One of the plurality of electrodes14is connected electrically to the integrated circuit12. The plurality of electrodes14could be arranged along two parallel sides of the semiconductor chip, as shown inFIG. 1, or they could be arranged at end portions along four sides, or arranged in a central portion thereof. A protective film (such as a passivation film)16is formed on a surface of the semiconductor substrate10(the surface on which the electrodes14are formed), avoiding the electrodes14themselves. The protective film16is an electrically insulating film. This protective film16is often formed of a non-organic material (such as SiN, SiO2, or MgO), but it could also be formed of an organic material (such as a polyimide resin).

The resin layer20is formed above the semiconductor substrate10(such as over the protective film16). The resin layer20is formed to avoid the electrodes14. In the example shown inFIG. 1, the resin layer20is formed in a central portion, avoiding the edge portions of the semiconductor chip. The resin layer20could also be formed in regions that include a plurality of external terminals50that are formed at positions that differ in the plane. The resin layer20could be a single layer or a plurality of layers.

The resin layer20could also have a stress relieving function. The resin layer20can be formed of one or more layers of a resin such as a polyimide resin, a silicone denatured polyimide resin, an epoxy resin, a silicone denatured epoxy resin, benzocyclobutene (BCB), or polybenzoxazole (PBO). The resin layer20is formed at least between the semiconductor substrate10and the external terminals50.

The wiring layer30is formed in a surface in which the electrodes14of the semiconductor substrate10are formed. The wiring layer30is connected electrically to one of the electrodes14and extends from the electrodes14above the resin layer20. In other words, part of the wiring layer30(such as a land) is formed above the resin layer20. The wiring layer30could be formed of one or a plurality of layers of any of: copper (Cu), chrome (Cr), titanium (Ti), nickel (Ni), titanium tungsten (TiW), gold (Au), aluminum (Al), nickel vanadium (NiV), and tungsten (W), by way of example. If the plurality of electrodes14is formed at edge portions of the semiconductor chip, the wiring layer30extends from the edge portions of the semiconductor chip to the central portion thereof.

The wiring layer30has a land32. A plurality of the lands32are formed in the semiconductor chip. Each land32is part of the wiring layer30, formed from at least one layer (a plurality of layers in the example shown in FIG.2). The wiring layer30includes the land32and a line which connects electrically the land32to one of the electrodes14. The land32and the line include electrically conductive layers. As shown inFIG. 4, each land32is wider than the lines of the wiring layer30. The width of the land32is widest in the direction crossing the direction of entry of the line into the wiring layer30. The shape of the land32in plan view could be circular. Alternatively, the shape of the land32in plan view could be elliptical or rectangular. The lands32are formed on an upper surface of the resin layer20. At least part of the line is also formed on the upper surface of the resin layer20. A plurality of the lands32could be formed on the upper surface of the resin layer20.

As shown inFIG. 3, a penetrating hole34is formed in the land32, exposing the resin layer20. This ensures that the land43can deform readily in response to stresses, in comparison with a configuration in which there is no penetrating hole34. In other words, it is possible to prevent breaking of the wiring layer30because stresses are relieved by the deformation of the land32. If the land32is formed of a plurality of layers, as shown inFIG. 3, the penetrating hole34penetrates all of those layers. The penetrating hole34could be formed at an end portion of the land32or it could be formed at a central portion thereof. As shown inFIG. 4, a plurality of the penetrating holes34could be formed in one land32. This makes it even easier for the land32to deform.

As shown inFIG. 4, the penetrating holes34could be elongated. In such a case, they could be elongated in the direction along the outer edge portion of the land32. Since this enables the formation of the penetrating hole34while avoiding the central portion of the land32, even if the elongated holes have been formed therein, it makes it possible to reserve a broad area for the provision of the external terminals50. The corners of the inner sides of the elongated holes could be formed as angular portions.

A plurality of the penetrating holes34could be arranged along the outer edge portion of the land32. In other words, a plurality of the penetrating holes34could be arranged along the outer periphery of the land32, at an edge portion of the land32. If the land32is circular, the plurality of penetrating holes34could be arranged on an imaginary circumference that is slightly smaller than the outline of the land32. Surrounding the central portion of the land32with a plurality of the penetrating holes34makes it possible for the central portion of the land32to move in response to stresses, thus enabling effective relief of those stresses.

The plurality of penetrating holes34could be disposed with the distances between adjacent holes being substantially equal. This makes it easy for the land32to deform with respect to stresses applied in all directions in the plane of the land. The plurality of penetrating holes34could be disposed at symmetrical positions in the land32. More specifically, the plurality of penetrating holes34could be disposed at positions that are point-symmetrical with respect to the center point (not shown in the figure) of the land32, or they could be disposed at positions that are line-symmetrical with respect to the center line (not shown in the figure) of the land32.

As shown in a variant example inFIG. 7, the corners of inner sides of penetrating holes36that are elongated holes could be rounded. Removing the angular portions on the land makes it possible to distribute any stress concentrations applied to the land32.

As shown in another variant example inFIG. 8, penetrating holes38could be round holes. A plurality of these round holes could be arranged along the outer edge portion of the land32. If the distances between adjacent round holes are substantially equal, the land32can deform readily in response to stresses applied in all directions in the plane of the land. Separately from the example shown inFIG. 8, a plurality of penetrating holes (round holes)38could be formed over the entire surface of the land32. In such a case too, the land32can deform easily in response to stresses.

The semiconductor device1further includes a resist layer (of, for example, solder resist)40. The resist layer40is formed on the surface of the semiconductor substrate10on which the electrodes14are formed, to cover part of the wiring layer30. The resist layer40has an aperture portion42that causes at least part of the land32to be exposed. As shown inFIG. 4, the resist layer40could also cover the outer peripheral edge portion of the land32. Alternatively, the resist layer40could cover only the lines of the wiring layer30, avoiding the land32.

The shape in plan view of the aperture portion42of the resist layer40could be circular, elliptical, or rectangular. The shape in plan view of the aperture portion42could be similar to that of the shape in plan view of the land32, except slightly smaller. If the resist layer40covers part of the land32, the resist layer40could fill part of the penetrating hole34.

As shown inFIG. 4, the resist layer40could fill the penetrating holes34. Since this brings the resist layer40into contact with the resin layer20within the penetrating holes34, it increases the adhesion therebetween. If the aperture portion42is circular, the contact surface between the land32and the external terminal50can also be made circular, making it possible to distribute any stress concentration on the external terminal50. Part of an edge of the penetrating holes34could be substantially in contact with an edge of the aperture portion42of the resist layer40. Since this ensures that part of an edge of the penetrating holes34are simply in contact with an edge of the aperture portion42and the penetrating holes34are not filled completely by the resist layer40, deformation of the land32is not affected by the resist layer40.

As shown inFIG. 4, a central portion of the land32(a region surrounded by the plurality of penetrating holes inFIG. 4) is connected at a plurality of locations to the edge portions of the land32. This therefore ensures that stresses are concentrated in the connective portions between the central portion and the edge portions of the land32, enabling the maintenance of connections in other locations if a break should occur in one place.

As shown in a variant example inFIG. 5, the resist layer40could fill part of the penetrating holes34. In the example shown inFIG. 5, each penetrating hole34is partially filled. For example, the configuration could be that each penetrating hole34substantially half-filled by the resist layer40, with the remaining half being exposed from an aperture portion44. Separately from the example shown inFIG. 5, the resist layer40could be formed to fill at least one of the plurality of penetrating holes34(but not all of them).

Alternately, the resist layer40may not fill the penetrating holes34at all, as shown in a variant example in FIG.6. In other words, the plurality of penetrating holes34could be exposed from an aperture portion46of the resist layer40. In such a case, the penetrating holes34could be substantially in contact with the inner periphery of the aperture portion46of the resist layer40.

The semiconductor device1further includes the external terminals50. The external terminals50are connected electrically to the wiring layer30. Each external terminal50could be formed on the land32. The external terminals50are of a metal that is electrically conductive (such as an alloy) and are designed to melt to provide electrical connections (such as solder). The external terminals50could be formed of either soft solder or hard solder. The external terminals50could be of a spherical shape, and they could be solder balls, by way of example.

The semiconductor device1further includes a second resin layer52that covers at least the lower end portions (root portions) of the external terminals50, avoiding the upper end portions thereof. The second resin layer52could also cover a central portion in the heightwise direction of each external terminal50. The second resin layer52also covers the periphery of each external terminal50. An upper edge portion of each external terminal50is exposed from the second resin layer52. The second resin layer52has an aperture, by way of example, and the upper end portion of each external terminal50is exposed from the second resin layer52through that aperture. The second resin layer52makes it possible to reinforce the connective state of the external terminals50with respect to the wiring layer30. This makes it possible to disperse stress concentrations. Note that the second resin layer52could be formed of the same material as the resin layer20or of a different material.

In this embodiment, each penetrating hole34that exposes the resin layer20is formed in the land32. Since this makes it easy for the land32to deform, it is possible to relieve stresses generated in the semiconductor device. It is therefore possible to prevent faults such as breaks in the wiring layer30or destruction of the external terminals50, improving the reliability of the semiconductor device. Since stresses are relieved by the configuration of the land32, a material with a low coefficient of elasticity can be used as the resin layer20, increasing the degree of freedom of selection of the component materials.

A method of fabricating a semiconductor device in accordance with the present invention includes the steps of forming the resin layer20on the surface of the semiconductor substrate10on which the electrodes14are formed, avoiding the electrodes14, and forming the wiring layer30in electrical contact with the electrodes14and having the lands32above the resin layer20. The penetrating holes34that expose the lands32are then formed. The plurality of penetrating holes34can be formed in each land32.

The penetrating holes34could be formed after the formation of the wiring layer30. In such a case, a photographic technique or the like could be applied in which a resist (not shown in the figure) that is patterned to form a mask and a portion exposed from the resist is etched to form each penetrating hole34. The penetrating holes34could also be formed simultaneously with the wiring layer30. In such a case, the above-mentioned photographic technique could be applied for patterning the wiring layer30and simultaneously forming the penetrating holes34. Alternatively, an electrically conductive material could be laid down by a plating method. If these can be formed simultaneously, it is possible to form the penetrating holes34simply with fewer fabrication steps. Note that the formation of the penetrating holes34could also be done by applying other known techniques (such as laser beams, ink jets, or printing).

Subsequently, a resist layer (of a material such as solder resist)40is then applied and a predetermined portion thereof (a portion comprising at least part of the land) is exposed by a photographic technique or by a laser. The external terminals50are then formed by printing with a material such as solder then applying a reflow process. The second resin layer52could then be provided over the entire surface of the semiconductor substrate10and apertures for at least the upper end portions of the external terminals50could be formed by ashing in a plasma or the like.

If the above-described process is performed with chips in the semiconductor wafer state, a semiconductor substrate11is cut along lines L surrounding each integrated circuit, by a blade60, as shown by way of example in FIG.9. This produces a plurality of the semiconductor devices1, cut from the semiconductor substrate11. This enables packaging in wafer units. Since the thus-obtained semiconductor device1has a package size that is substantially equal to that of the semiconductor chip, it can be classified as CSP. Note that other details are similar to those of the above-described semiconductor device.

A circuit board on which a semiconductor device is mounted is shown inFIG. 10. Awiring pattern72is formed on a circuit board (motherboard)70and the external terminals50are connected to the wiring pattern72. This makes is possible to efficiently relieve stresses generated by differences in the coefficient of thermal expansion between the circuit board70and the semiconductor substrate10.

Second Embodiment

A method of fabricating a semiconductor device in accordance with a second embodiment of the present invention is shown inFIGS. 11to15. In this embodiment, the shapes of the resin layer and the land differ from those described above. The details described with reference to the first embodiment can be applied to those of this embodiment, as far as possible.

The semiconductor substrate10is first prepared. The integrated circuit12, the electrodes14, and the protective film16are formed on the semiconductor substrate10. The semiconductor substrate10could be a semiconductor wafer. Since this would enable batch processing of the fabrication of semiconductor devices in the wafer state, it increases mass-productivity.FIG. 11shows the portion that will become one semiconductor chip, from the semiconductor wafer. Alternatively, the fabrication process described below could be performed after the semiconductor chip has been separated.

As shown inFIG. 11, a resin layer120is formed over the semiconductor substrate10(above the protective film16, by way of example). More specifically, a plurality of the resin layers120are formed at positions that differ in the plane of the semiconductor substrate10(the regions of the semiconductor wafer that will become the semiconductor chips). For example, the plurality of resin layers120could be formed to correspond to the regions of the external terminals50that are formed at different positions in the plane. In other words, each of the external terminals50could be disposed above one of the resin layers120. If each resin layer120is formed at the central position of the region that will become the semiconductor chip, it is possible to avoid the plurality of electrodes14formed at edge portions thereof. Note that other details of the resin layer120are similar to those of the resin layer described with reference to the first embodiment.

As shown inFIG. 12, each resin layer120has an upper surface122and a side surface124. The upper surface122of the resin layer120is preferably a flat surface. It is also preferable that the side surface124of the resin layer120is provided with a taper. More specifically, the side surface124of the resin layer120could be provided with a taper such that the surface area of the upper surface122is less than surface area of the lower surface (base surface) thereof on the semiconductor substrate10side. This facilitates the formation of penetrating holes134in portions of the side surface124of the resin layer120. The shape of the resin layer120in plan view could be circular. In the example shown in these figures, the resin layer120has a conical shape. The height of the resin layer120could be approximately 30 μm, by way of example.

The resin layer120can be formed by a photographic technique. In such a case, a photo-sensitive material such as a photopolymer can be used as the material of the resin layer120. The resin layer120is provided over the entire surface of the semiconductor substrate10, a mask is applied, and energy (in most cases, optical energy) is irradiated thereon. If the material of the resin layer120is of a positive type, the solubility of the portions that were irradiated is increased and those portions are removed by development. Conversely, if the material of the resin layer120is of a negative type, the solubility of the portions that were irradiated is decreased and those portions remain while other portions are removed by development. Since a photographic technique enables adjustment of factors such as the thickness and aperture size of the mask and the magnitude and angle of the energy irradiation, it makes it possible to apply the taper to the side surface124of the resin layer120.

A first layer80that is the material for a wiring layer130is then applied, as shown in FIG.13. The first layer80is formed to cover at least the plurality of resin layers120. In this case, the first layer80could be formed over the entire surface of the semiconductor substrate10(including each upper surface122and side surface124). The first layer80could be formed by a method such as sputtering.

A second layer82is patterned above the first layer80, as shown in FIG.14. The second layer82acts as a mask for the formation of the wiring layer130. In the example shown inFIG. 14, the second layer82is formed to overlay portions of the first layer80that will remain as the wiring layer130. The second layer82could be formed to have aperture portions. Each aperture portion of the second layer82forms a region in the wiring layer130for the formation of a penetrating hole134(see FIG.15B). This makes it possible to form wiring layer130having the penetrating holes134. The aperture portions of the second layer82could be formed in the side surface124of the resin layer120. Note that the second layer82could be formed by patterning a resist (not shown in the figure) previously then forming the aperture portions in that resist. That resist is peeled off after the formation of the second layer82

The second layer82could be formed of an electrically conductive material. In such a case, part of the second layer82could form part of the wiring layer130. The second layer82could be a plated layer formed by electroplating or a non-electrolytic plating method. Since this leaves part of the second layer82as a plated layer, there is no need to form another plated layer above the wiring layer130.

As shown inFIG. 15A, the first and second layers80and82etched (by wet etching, by way of example). This removes the portions of the first layer80that are exposed from the second layer82, leaving the portions thereof that are covered by the second layer82unetched. At least part of the second layer82is removed. The wiring layer130is then formed. As can be seen from the perspective view ofFIG. 15B, the wiring layer130has the penetrating holes134. The penetrating holes134could be formed in the side surface124of the resin layer120. The resin layer120is exposed within each penetrating hole134. With this embodiment of the invention, the wiring layer130has the first layer80. The wiring layer130could also have part of the second layer82as well.

A partial expanded view of a semiconductor device in accordance with this embodiment is shown inFIG. 16. Aplan view ofFIG. 16is shown inFIG. 17, with parts of the semiconductor device (such as the wiring layer and external terminals) omitted. The semiconductor device in accordance with this embodiment includes the semiconductor substrate10, the resin layer120, and the wiring layer130. In the example shown inFIG. 16, the semiconductor device further includes the resist layer40, the external terminals50, and the second resin layer52.

The wiring layer130has a land132. As shown inFIG. 17, the land132is formed integrally with the upper surface122and the side surface124of the resin layer120. The penetrating holes134are formed in the land132. The penetrating holes134could be formed in portions of the land132covering the side surface124of the resin layer120. Providing the side surface124of the resin layer120with a taper makes it easy to form the penetrating holes134. As a variant, the penetrating holes134could be formed in the upper surface of the resin layer120in the land132, or they could be formed integrally in the upper surface and the side surface of the resin layer120of the land132.

An aperture portion48of the resist layer40exposes the land132. As shown inFIG. 17, the aperture portion48could also expose parts of the upper surface122of the resin layer120in the land132. This would make it possible to form the external terminal50on a flat portion of the land132.

This embodiment achieves the effects described with reference to the first embodiment. All other details of this embodiment are equivalent to those described for the first embodiment.

Examples of electronic instruments having the semiconductor device in accordance with embodiments of the present invention are a notebook-sized personal computer1000shown inFIG. 18 and amobile phone2000shown in FIG.19.

The present invention is not limited to the above-described embodiments, and various modifications can be made. For example, the present invention includes various other configurations substantially the same as the configurations described in the embodiments (in function, method and effect, or in objective and effect, for example). The present invention also includes a configuration in which an unsubstantial portion in the described embodiments is replaced. The present invention also includes a configuration having the same effects as the configurations described in the embodiments, or a configuration able to achieve the same objective. Further, the present invention includes a configuration in which a publicly known technique is added to the configurations in the embodiments.