Sampling-based balanced detection system

A two-gate sampling system has been designed to perform sampled balanced detection of one or more input signal pairs. The present invention performs simultaneous sampling of both signals in each signal pair followed by digitization and combination of the sample pairs using software. By first sampling the signals and then combining the sampled into the corresponding balanced detected signal it is possible to avoid the bandwidth limitations and impedance problems introduced by traditional balanced detectors and electrical oscilloscopes. In particular, for optical sampling gates very high bandwidth sampling gates can be designed without any impedance issues and hence almost perfect balanced detection reconstruction can be performed for very high speed signals. Balanced detection is becoming more and more important as the new phase modulated optical data signals are introduced to the market, such as e.g. PSK, DPSK, QPSK and DQPSK. The present invention is well suited for analysis of these new types of signals.

TECHNICAL FIELD

The present invention relates to a sampling arrangement particularly well-suited for analysis of high speed data signals and, more particularly, to a sampling arrangement with two or more coupled sampling gates.

BACKGROUND OF THE INVENTION

Digital sampling is a technique used to visualize a time-varying waveform by capturing quasi-instantaneous snapshots of the waveform via, for example, a sampling gate. The gate is “opened” and “closed” by narrow pulses (strobes) in a pulse train that exhibit a well-defined repetitive behavior such that ultimately all parts of the waveform are sampled. The sampling implementation can either be real-time or equivalent-time, where real-time sampling refers to the case where the sampling rate is higher than twice the highest frequency content of the waveform under test (Nyquist sampling), while equivalent-time sampling uses an arbitrarily low sampling rate. However, equivalent-time sampling requires the measured waveform to be repetitive (in order to provide accurate signal reconstruction)—a fundamental limitation when compared to real-time sampling. The present invention is independent of the sampling rate, and hence, can be either real-time or equivalent-time sampling.

The recent advances in the field of optical communication with new, more complex, data modulation formats as a key technology has created a need for optical waveform characterization tools which are capable of extracting more information from the waveform than simply its power as a function of time.

In particular, many different modulation formats have been developed which use modulation of the phase of the optical carrier to encode the data to be transmitted. A few types of phase modulated signals have already been employed in commercial systems, such as differential phase shift keying (DPSK) and differential quaternary phase shift keying (DQPSK). For these differential modulation formats the data is encoded as the relative phase shift between consecutive symbols. In DPSK modulation schemes, for example, a π phase shift between bits represents a logical “1” and a zero phase shift represents a logical “0”. For DQPSK modulation, each symbol contains two bits of information by allowing four different relative phase changes between consecutive bits (e.g., 0, π/2, π and 3π/2).

FIG. 1is used to further clarify the concept of phase-encoded modulation formats such as phase-shift keying (PSK), differential phase-shift keying (DPSK), and QPSK and DQPSK as defined above. For each type of modulation, the optical phase and amplitude of the data signal are visualized in constellation diagrams showing the optical field amplitude as the radial distance from origin R and the optical field phase as the angle φ. InFIG. 1, the logical marks (ones) and spaces (zeros) are represented as either absolute phase and amplitude levels (for PSK and QPSK formats,FIGS. 1(a) and (b), respectively), or as phase and amplitude transitions for the differentially-coded phase and amplitude levels (for DPSK and DQPSK formats,FIGS. 1(c) and (d), respectively). For D/QPSK each symbol contains, as shown, two bits of information. Therefore, four different logical phase and amplitude combinations are used to represent the “symbols” in either of these modulation format types.

It is to be noted that the amplitude of the data signal is constant for each of these phase-encoded modulation techniques. Hence, if only the power of the incoming signal is “detected” using a conventional photodetector-based o/e conversion device, the phase information will be lost. To extract the phase information, the signal needs to be mixed with an optical reference signal which converts the phase information into amplitude information. For differentially-modulated signals, delay interferometers (DIs), such as Mach-Zehnder interferometers (MZIs), Michelson interferometers, or the like, are commonly used in which the signal itself serves as reference after being delayed one (or more) bit periods. For absolute phase encoded signals (e.g. PSK or QPSK), an independent reference signal is necessary to extract the phase information from each bit.

The DI is an interferometric structure where the incoming optical waveform is split up (preferably equally) into two paths and one path is delayed relative to the second path before recombining the two paths. The relative delay is coarsely set equal to an integer number of bit slots (most commonly one bit slot) and finely tuned to match a particular relative phase delay of the optical carrier. For example, in the DPSK case, the relative delay is a multiple of π in order to effectively translate the relative phase shifts between the symbols into a binary amplitude modulated signal. The DI has two output ports—a constructive interference port and a deconstructive interference port (the ‘destructive’ port outputting the complementary data of the ‘constructive’ port). In order to optimize a DPSK receiver in terms of signal sensitivity, both outputs from the DI are detected by a so-called “balanced detector” structure.

In order to recover the data embedded in an incoming DQPSK signal, the signal is first evenly split so as to applied as “equal power” inputs into two separate DIs with different relative optical phase delays (+π/4+n*π and −π/4+m*π, where n and m are integers) and each DI pair of outputs is thereafter detected by a balanced detector structure. By properly choosing the relative phase delays, two bits of information per symbol can be separated and represented as one bit per balanced detector output. The amplitude modulated output from each balanced detector is thereafter sampled (for example, digital sampling) in order to visualize each bit's corresponding eye-diagram.

A major concern when using balanced detection for optical to electrical (o/e) conversion followed by electrical digital sampling is the influence of the measurement system on the measured waveform, which is known to introduce measurement error. In particular, balanced detection and electrical sampling suffer from two major limitations: (1) limited measurement bandwidth (currently <50 GHz); and (2) significant impedance mismatch, resulting in distortion in the measured waveform. For high speed signal characterization (10 GSymbols/s, 40 GSymbols/s or higher), these effects can influence the measurement results to such an extent that the measured waveform is dominated by the measurement system impulse response, which is unacceptable when needing to recover such high speed data signals.

Thus, a need remains in the art for an arrangement capable of characterizing (visualizing) high symbol rate optical signals without being hampered by the measurement system bandwidth or the distortion due to ole conversion and related impedance matching issues.

SUMMARY OF THE INVENTION

The needs remaining in the prior art are addressed by the present invention, which relates to a sampling arrangement particularly well-suited for analysis of high speed data signals and, more particularly, to a sampling arrangement comprising two or more coupled sampling gates for recovering information from the phase-encoded modulated signals.

In accordance with the present invention, a sampling arrangement utilizes two (or more) separate sampling gates controlled by the same strobe frequency, fs, to acquire samples from two (or more) phase-encoded modulated signals. The lengths of the paths to the sampling gates are adjusted by tunable (or fixed) delay lines so as to enable precise, time-overlapped sampling of all input signals. Precise, temporally-overlapped sampling of all of the input signals is carried out within a time-delay means. Preferably, the time-delay means comprises at least one delay line for adjusting the path length of the propagating optical signal upstream from a corresponding sampling gate. Examples of suitable delay line arrangements include a “fixed” (e.g., factory-adjusted and set) delay line, a “set-and-forget” delay line and a “tunable” delay line.

Alternatively, this time-delay means comprises at least one delay line for adjusting at least one optical or electrical sampling signal generated by the strobe source and conveyed to the corresponding at least one sampling gate. In another embodiment, the time-delay means may comprise a combination of the two aforesaid time-delay means.

In particular, for the application of measuring the output signal pairs of one or more delay interferometers (DIs), as in the case of DPSK and DQPSK signals, the time-delay means is used to ensure that the time delay from the output of each DI to the two corresponding sampling gates are equal to within a fraction of the temporal resolution of the sampling gates. Hence, every pair of samples originating from the two outputs of each DI originates from the same time “slice” of the waveform under test. The acquired pairs of samples are then, after detection and analog-to-digital (A/D) conversion, combined in software to yield samples representing balanced detection of the sample pairs, which then can be displayed on a user interface, or otherwise made available for further analysis.

With this scheme, the need to perform balanced detection in hardware is avoided. In particular, when using optical sampling gates, the sampling gate bandwidth (inversely related to the temporal resolution) can be extremely high and impedance mismatch problems prevalent in electrical sampling applications are no longer an issue, since the sampling takes place in the optical domain.

In one embodiment of the present invention, the two sampling gates are used for more than one input signal pair, such as in the case for a DQPSK signal where after demodulation by two DIs the two output signal pairs are measured in order to present the eye-diagram of each bit in the 2 bits/Symbol DQPSK signal. By including, for example, optical switches before the two sampling gates, the DI output pairs can be measured by the sampling gates by switching in a predetermined fashion.

Another embodiment of the present invention includes a sampling gate to sample an external reference clock, which can be used to establish the time base for the acquired samples from the signal under test.

Other and further aspects and embodiments of the present invention will become apparent during the course of the following discussion and by reference to the accompanying drawings.

DETAILED DESCRIPTION

Prior to describing the details of the exemplary sampling arrangement of the present invention, a prior art arrangement for demodulating DPSK-encoded signals will be reviewed with reference toFIG. 2. The DPSK signal is demodulated using a delay interferometer (DI)10having a relative delay difference between the two interferometer arms. DI10is shown as comprising a first signal path12and a second path14. An incoming modulated DPSK signal passes through a splitter16such that an approximately equal power level of signal is directed into paths12and14. Second path14includes a delay element18, represented as a fixed amount of delay (25 ps in this example) and a variable amount of delay shown as Δφ). The phase shift is selected such that a delay of an integer number of bits (generally a single bit) is obtained. The original and the phase-shifted versions of the DPSK-encoded signal are thereafter recombined in a signal combiner20and split along two separate output paths22and24. As with splitter16, the output signals along paths22and24comprise half of the power of the combined original/phase-shifted signals.

At the two outputs from DI10, the phase information in the DPSK signal is converted into two amplitude modulated signal, a first “constructive interference” signal with power Pcalong a first output path22, and a second “destructive interference” signal (exhibiting the complementary information) at power Pdalong a second output path24

With traditional techniques, these two output signals would be applied as inputs to a balanced opto-electronic detector, which would subtract the one signal from the other and convert the difference into the electronic domain, ideally providing an electrical signal representing Pc-Pd. In the prior art arrangement ofFIG. 2, a pair of photodiodes21and23are used to provide this opto-electronic conversion. However, such o/e conversion techniques are limited in bandwidth and quality of impulse response. As a result, the electrical signal created after detection does not represent the ideal case, in particular for high speed signals.

In contrast, the present invention utilizes a sampling technique to individually measure the waveform on each DI output, in a manner to be described in detail hereinbelow. A software-embedded algorithm is then used to combine the samples in a manner which emulates the operation of an ideal balanced detector, performing the operation Pc-Pd, to create a sampled output waveform as shown in eye diagram34of FIG.3. For input signals other than DPSK (such as DQPSK), similar reasoning applies but instead of having only two output signals after a single DI, there can be more DI's each having two output signals which can be taken care of by embodiments of the present invention to be described below.

In a preferred embodiment of the present invention, the sampling of the two DI output signals is performed in the optical domain, so as to completely remove the influence of the bandwidth limitations inherent in optical-electronic conversion and provide a final result which can be very close to the targeted ideal result Pc-Pd. However, the sampling technique of the present invention is not limited to the optical domain; electrical sampling techniques may be used in suitable applications (for example, lower speed applications).

FIG. 3shows an embodiment of the present invention which utilizes the same incoming DPSK-encoded signal and demodulating arrangement including DI10as described above in association withFIG. 2. The embodiment ofFIG. 3may also be utilized if only one bit in a two-bits-per-symbol DQPSK signal is sampled. As will be described in detail below, a sampling arrangement40formed in accordance with the present invention is used in place of prior art o/e conversion arrangements to more accurately recover the data from the phase-encoded incoming signal. The “constructive” signal propagating along first output path22is shown as applied as an input to first signal port A1of arrangement40. Similarly, the “destructive” signal propagating along second output path24is applied as an input to second signal port A2.

It is to be understood that the technique of the present invention can be scaled to support a larger number of input ports, as will be discussed in detail below. Moreover, the input signals can be either optical or electrical. In its most general form, the present invention is a combination of performing sampling of pairs of input signals in hardware and using software algorithms to combine the created samples into a single output corresponding to balanced detection of the input signal pairs.

Referring back to the particular embodiment ofFIG. 3, such a result is shown as the simultaneous sampling of A1and A2and subsequent reconstruction of a sampled version of the power of A1-A2. At the core of the present invention are a pair of sampling gates42and44which are opened and closed by sampling signals, characterized by a sampling frequency fs, generated by a common strobe source46. The sampling signals may be either in the electrical domain or in the optical domain, depending on the domain of the signals arriving at ports A1and A2. However, the full benefits of this invention are most apparent when the signals to be tested are optical, in which case optical sampling is the preferred embodiment in order to eliminate all high speed electronics and o/c conversion. By digitally sampling the output waveform from the balanced detector structure, the corresponding electrical eye-diagram, showing logical binary amplitude levels corresponding to the phase transitions in the DPSK signal, can be visualized.

Optical sampling gates42and44may comprise any one of a wide variety of implementations using different nonlinear optical processes to create the gating functionality. Exemplary suitable components include, but are not limited to, four-wave mixing in fiber, sum-frequency generation in optical crystals and cross-phase modulation in fiber or semiconductor optical amplifiers. While strobe source46is illustrated as a single element, it is to be understood that separate strobe sources, having the same sampling frequency fsmay also be used, with each separate strobe source used to control a separate gate.

It should be noted that many sample gate types are polarization sensitive, that is, the efficiency of the sampling may be related to the state of polarization (SOP) of the light entering the sampling gate, and this efficiency may even be substantially “zero” for certain input SOPs. In particular, sampling gates based on four-wave mixing are particularly sensitive to the state of polarization. Consequently, if standard (i.e., non-polarization-maintaining) single-mode optical fiber is used throughout the apparatus, it may be desirable to insert polarization control means in each of optical signal paths22and24to optimize the SOP of the signals entering the associated sampling gates.

Alternatively, an arrangement described in commonly-owned U.S. Pat. No. 7,199,870 entitled “Polarization Independent Optical Sampling Arrangement”, issued Apr. 3, 2007, may be implemented to render the design polarization independent.

Alternatively, the fiber and all other optical components of the present invention may be polarization maintaining, with a polarization controller disposed before the input to a polarization-maintaining input fiber, upstream with respect to DI10, in order to optimize the light launched along one of the axes (e.g., a slow axis) of the PMF.

A key design parameter for the present invention is to facilitate alignment of the sampling times of gates42and44via strobe source46such that the two parts of the signal are synchronously sampled in order for combination in the software to be accurate. A delay line48is disposed at first input port A1and is used to adjust the distance (or time delay) from the input A1to sampling gate42, thereby adjusting the sampling time of gate42relative to the sampling time of gate44.FIG. 5will describe an example which highlights the condition for adjusting delay line48, In general, the operation of delay line48can be either adjustable or fixed, depending on the measurement application.

The output samples from the sampling gates42and44are digitized by analog-to-digital converters (A/D)50and52, respectively, and subsequently fed into a software processing and signal visualization system54. The main functionality of system54related to the present invention is to combine the acquired sample pairs for each measurement in order to provide balanced detection functionality. Furthermore, the software can be used to visualize each measured input signal pair as the corresponding balanced detected signal. Eye diagram28ofFIG. 3is the sampled output associated with the constructive port, eye diagram30is the sampled output associated with the destructive port and, most importantly, eye diagram34is the resultant DPSK sampled information eye diagram, where each of these diagrams was created by system54.

An alternative embodiment of the present invention allows for detection of the output samples from the sampling gates42and44using low bandwidth balanced receivers in order to perform the balanced detection in the hardware before digitizing the samples in an A/D converter.

It is to be understood that the present invention is independent of the particular method utilized to time stamp each sample. In particular, the technique of the present invention has been found to work for both real-time sampling and equivalent-time sampling, irrespective of the time-base design used for equivalent-time sampling.

FIG. 4illustrates an embodiment suitable for measurement of, for example, QPSK or DQPSK signals, which requires the generation of two sample pairs for proper demodulation. As before, the incoming phase-encoded signal is split along signal paths12and14by a power splitter16. In this case, however, the portion of the signal propagating along signal path14is thereafter applied as an input to a first DI10-1, and the remaining portion propagating along signal path12is applied as an input to a second DI10-2, as shown inFIG. 4. Each DI10includes a separate delay element18, illustrated as delay element18-1(associated with DI10-1) and delay element18-2(associated with DIO10-2). Delay elements18-1and18-2are shown as exhibiting the appropriate bit delays TS and phase relations Δφ1 and Δφ2 for demodulation of the input signal. In particular, for the case of DQPSK the phase relations can be, for example, Δφ1=+π/4 and Δφ2=−π/4, in order to separate each bit in the 2 bits/Symbol DQPSK data signal. By flipping the switches56and58in a predetermined manner, the outputs from each DI10-1and10-2can be measured separately, and with the present invention the corresponding balanced detected signals of each demodulated bit of the DQPSK signal can be visualized.

In this case, a set of four output signals have been created, a first signal pair A1and A2from DI10-1(similar to the embodiment ofFIG. 3, as discussed above) and a second signal pair B1and B2, from DI10-2. In order to most efficiently utilize the elements of sampling arrangement40, switches56and58are positioned at the entrance ports of arrangement40, in front of sampling gates42and44, in order to facilitate alternating sampling of the input signal pairs from DI's10-1and10-2, that is, first A1, A2and then B1, B2. As shown, a second delay line48-2, associated with input B1is included in the arrangement to provide the same synchronization activity as delay line48defined above and discussed in detail below.

FIG. 4also points out that o/e conversion of the signals can be performed before the sampling takes place. In this case, a photodiode or other o/e conversion element is disposed along each signal path, and is collectively illustrated as conversion component70inFIG. 4. In this case, sampling gates42and44will comprise electronic sampling gates. The positioning of o/e conversion component70is flexible and can be either directly after DIs10-1and10-2, or at any other point in front of sampling gates42and44. Additionally, delay lines48-1and48-2, as well as switches56and58can be either electrical or optical.

FIG. 5illustrates the critical timing required between sampling gates42and44in order to sample each part of the generated signal pairs at the correct matching times.FIG. 5is an extracted part of the embodiment ofFIG. 4. InFIG. 5, the signal is not split up until point A, corresponding to the output of the DI10-1. From this point on, it is critical that the difference in effective optical path length (i.e., time difference) from point A to the point where the signal is sampled be very close to equal in order to generate samples originating from the same time in the original signal. This is a condition in order to be able to combine the two samples in the software and emulate the balanced detection.

The timing condition can be expressed using the notations inFIG. 5as |(Tc-tc)−(Td-td)|<Δτ, where Tcis the propagation time for the “constructive” signal from point A to sampling gate42, tcis the propagation time for the sampling strobe pulse from strobe source46to sampling gate42, Tdis the propagation time for the “destructive” signal from point A to sampling gate44, tdis the propagation time for the sampling strobe pulse from strobe source46to sampling gate44, and Δτ represents the temporal resolution of sampling gates42and44. As alluded to above, delay line48-1plays a critical role to facilitate the fulfillment of this timing condition, in particular since the relative lengths of the output fibers corresponding to the “constructive” and “destructive” ports of commercially available delay interferometers are usually not accurately controlled or known. However, with precise control of this and every other component within sampling arrangement40, delay line48may be omitted, in particular for low-bandwidth sampling gate solutions with high (i.e., poor) Δτ. The timing condition applies to all input signal pairs within the system of the present invention (e.g., in the arrangement ofFIG. 4, a similar condition applies from point B to sampling gates42and44).

It has been pointed out that the present invention is independent on the time-base design used to synchronize the acquired samples into a replica of the original signal. However, it should be noted that the present invention is compatible with U.S. Pat. No. 7,327,302, by M. Westlund et al. on Feb. 5, 2008, assigned to the assignee of this application and hereby incorporated by reference.FIG. 6illustrates an embodiment of the present invention where an external reference signal source60is used to supply a gating control signal for the system, where the frequency fcof reference clock signal C is directly related to the frequency of the demodulated signals appearing at ports A1, A2, B1and B2. As shown, the reference clock output signal C from source60is sampled by a separate sampling gate62, using the same strobe source46. The generated clock samples are then digitized by an A/D converter64and applied as an input to software processing system54. With this input information, the timebase of the external clock can be determined by the embedded software algorithms. Since the frequency fcof the external clock is directly related to the frequency of the input signal bit rate, the time-base of the external clock can be directly transferred to the recovered output signal.

It is to be understood that other advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the claims appended hereto.