Microstructured surface with low work function

A horizontal multilayer junction-edge field emitter includes a plurality of vertically-stacked multilayer structures separated by isolation layers. Each multilayer structure is configured to produce a 2-dimensional electron gas at a junction between two layers within the structure. The emitter also includes an exposed surface intersecting the 2-dimensional electron gas of each of the plurality of vertically-stacked multilayer structures to form a plurality of effectively one-dimensional horizontal line sources of electron emission.

BACKGROUND

In solid-state physics, the work function defines the minimum energy required to remove an electron from a solid to a point immediately outside the surface of the solid. In other words, the work function is the amount of energy needed to move the electron from the highest filled Fermi level into the vacuum immediately outside the solid surface. This amount of energy is typically measured in electron volts, and as opposed to being a property of a bulk material itself, the work function is a characteristic property for a surface of the material.

SUMMARY

One embodiment relates to a horizontal multilayer junction-edge field emitter (HMJFE). The HMJFE includes a plurality of vertically-stacked multilayer structures, separated by isolation layers, each structure being configured to produce a 2-dimensional electron gas (2DEG) at a junction between two layers within the structure. The HMJFE includes an exposed surface intersecting the 2DEG of each of the plurality of vertically-stacked multilayer structures to form a plurality of effectively one-dimensional horizontal line sources of electron emission.

Another embodiment relates to a HMJFE. The HMJFE includes a first substrate including a first surface. The HMJFE includes a first plurality of vertically-stacked multilayer structures. The first plurality of vertically-stacked multilayer structures are separated by isolation layers, configured to produce a first 2DEG at a junction between two layers within the structure, and attached to the first surface. The HMJFE includes a second plurality of vertically-stacked multilayer structures. The second plurality of vertically-stacked multilayer structures are separated by isolation layers, configured to produce a second 2DEG at a junction between two layers within the structure, and attached to the first surface. The HMJFE includes a first anode attached to the first surface of the first substrate and configured to collect electrons emitted by the first 2DEG.

Another embodiment relates to a method of fabricating a HMJFE. The method includes disposing a first multilayer structure on a first substrate including a first surface, the first multilayer structure being configured to produce a first 2DEG at a junction between two layers within the first multilayer structure. The method includes disposing a first isolation layer on the first multilayer structure. The method includes disposing a second multilayer structure on the first isolation layer, the second multilayer structure configured to produce a second 2DEG at a junction between two layers within the second multilayer structure. The method includes disposing a first anode on the first surface of the first substrate, the first anode configured to collect electrons emitted by the first 2DEG.

Another embodiment relates to a vertical-emitting junction-edge field emitter structure (VEJFE). The VEJFE includes a plurality of vertical structures formed on a substrate, each vertical structure including at least two vertically oriented layers. Each vertical structure is configured to produce a 2DEG at a junction between two vertically-oriented layers of the vertical structure. Each vertical structure is truncated to expose an edge of the 2DEG.

Another embodiment relates to a method of fabricating a VEFJE structure. The method includes forming a plurality of vertical structures on a substrate, wherein forming each vertical structure includes positioning at least two vertically oriented layers adjacent to one another to create a junction between the two vertically oriented layers. The method includes truncating the plurality of vertical structures on an opposite side of the plurality of vertical structures from the substrate to expose an edge of the junction, the junction configured to produce a 2DEG.

DETAILED DESCRIPTION

In the following detailed description, reference is made to the accompanying drawings, which form a part hereof. In the drawings, similar symbols typically identify similar components, unless context dictates otherwise. The illustrative embodiments described in the detailed description, drawings, and claims are not meant to be limiting. Other embodiments may be utilized, and other changes may be made, without departing from the scope of the subject matter presented here.

Referring generally to the figures, various embodiments for microstructured surfaces having low work functions are shown and described. As discussed by Srisonphan, Jung, and Kim in their article,Metal-oxide-semiconductor field-effect transistor with a vacuum channel, Nature Nanotechnology, vol. 7, 504-508 (2012), electrons can be emitted from the 1-dimensional edge of a 2-dimensional electron gas with a low work function. For example, electrons may be emitted from an edge formed by the interfacial layer of an oxide or metal on a semiconductor. According to the disclosure herein, such emission may be achieved over a wide area by microstructuring the interfacial layer so that there are many edges in order to provide multiple emissions. As an example, lithographic masking techniques may be used when forming such an interface to create interfacial dots, holes, or lines at the surface to provide multiple electron emissions with low work functions.

Referring toFIG. 1A, a block diagram of a single horizontal multilayer junction-edge emitter structure100is shown, according to one embodiment. The structure100generally includes an emitting structure101comprised of multiple thin layers of various materials. These materials may include n- or p-type doped semiconductors, undoped (intrinsic) semiconductors, insulators such as silicon dioxide or silicon nitride, and metallic conductors. For example, in an embodiment, the structure101includes an n-type semiconductor layer102, an insulator layer104, and a p-type semiconductor layer106. In other embodiments, the structure includes the n-type semiconductor layer102in direct contact with the p-type semiconductor layer106. In another embodiment, the structure101includes the n-type semiconductor layer102, an intrinsic (undoped) semiconductor layer104, and a metal (e.g., aluminum) layer106. In some embodiments, a two-dimensional electron gas (2DEG)108can form at a junction (e.g., interfacial layer) between an oxide or metal on a semiconductor, or between two different semiconductors. For example, the 2DEG108can be formed at a junction of an n-type semiconductor102and an intrinsic semiconductor layer104or a junction between the p-type semiconductor106and the insulating layer104in the structure100.

In some embodiments, at least two of the non-insulating layers may be biased relative to each other by an external voltage source120, forming either a biased junction or a field effect device. In some embodiments, one or more layers may be atomically thin, e.g., a layer of graphene or molybdenum disulfide. In some embodiments, the 2DEG is confined to such an atomically thin layer. In other embodiments, a 2DEG may be formed between two layers comprising different insulators (e.g., ZnO/ZnMgO); in such embodiments, an electrical contact or tunnel junction may be provided to introduce electrons into, or remove electrons from, the 2DEG. Other configurations, without limitation, may be used to create a 2DEG.

The emitting structure101is truncated at surface116, exposing an effectively one-dimensional edge110of the generally planar 2DEG108. Such an exposed edge110of a 2DEG can emit electrons with a low work function compared to emission of electrons from a conventional material surface.

In some embodiments, structure100further includes an anode112spaced from the surface116and configured to capture electrons emitted from one-dimensional edge110. The anode112may be configured to be a constant distance from at least a portion of edge110, such that the electric field near edge110is uniform along edge110. The anode112may be biased relative to the 2DEG to increase or decrease field emission of electrons from the one-dimensional edge110.

In some embodiments, structure100may further include one or more grids located between the edge110and the anode112. These grids may be biased to alter the electric field distribution between edge110and anode112, and thereby control the rate and trajectory of electrons emitted from edge110.

Now referring toFIG. 1B, a block diagram of a horizontal junction multilevel structure130is shown. The structure130includes a multilevel emitter structure131, comprised of two or more individual emitter structures (100A,100B) separated by isolation layers118. In some embodiments, isolation layers118may be single layers of insulator (e.g., silicon dioxide, silicon nitride); however, other materials or structures (e.g., multilayers) may be included in layer118, e.g. a grounded conductive layer to limit electric field interactions between levels. In some embodiments, the multilevel emitter structure131is deposited on a substrate122. In some embodiments, individual emitter structures101A,101B may be biased by separate external voltage sources; in other embodiments, appropriate layers (e.g.,102A and102B,106A and106B) may be electrically connected, such that multiple layers of emitter structure130can be biased by a single external voltage source.

Similarly toFIG. 1A, the multilevel emitter structure131terminates at a surface116, exposing multiple one-dimensional edges110A,110B of 2DEGs formed in structures110A,110B; each such edge is an independent source of electron emission.

In some embodiments, the surface116may be formed by depositing materials forming multilevel emitter structure131over a limited area of substrate122, e.g., by deposition through a mask. In other embodiments, the surface116may be formed by depositing the materials forming emitter structure131over a larger area of substrate122, and then removing material, e.g. by an etching or milling process, to expose surface116. For example, a vertically-sided trench in a multilayer-coated area may be formed via focused ion beam milling (e.g., a trench or channel having a cross-section of 0.25×0.25 μm2, 0.5×0.5 μm2, 1×1 μm2, etc.).

The surface116may be straight or curved as viewed perpendicular to the substrate, and in some embodiments may form one or both walls of one or more channels or trenches through the deposited layers102-106. In other embodiments the surface116may form the inner wall of cylindrical or conical holes in layers102-106, or the outer wall of cylindrical or conical posts, or other geometric configurations.

A common anode112may be used to collect electrons emitted from edges110A and110B. In some embodiments a common voltage may be present between the anode112and all emitting structures101A,101B, etc.; in other embodiments the voltages between the anode112and each emitting structure may be separately regulated. In such embodiments, the separate voltage regulation may be used to maintain a desired current or current density from each emitting structure despite variation in separation between the emitting structures and the anode112; e.g., due to tilting of or irregularities in surface116or the surface of anode112.

In some embodiments, one or more grids may be located between the emitting structure131and anode112.

Now referring toFIGS. 2A-2C, various embodiments of arrangements of multilayer structures are shown. The multilayer structures may be similar to and may include features of the structure100illustrated inFIG. 1Aand/or the structure130illustrated inFIG. 1B. Arranging multilayer structures in relationship to one another and/or in relationship to anodes may facilitate controlling the trajectories of electron emission and for controlling collection of emitted electrons. Such arrangements may be repeated to provide a plurality of multilayer emitters and anodes.

As shown inFIG. 2A, structure200includes multilayer emitters204,208provided on substrate212. Multilayer emitters204,208include junctions (e.g., interfacial layers) at which a 2DEG can form. In some embodiments, multilayer emitters204,208are formed by being separately deposited over a limited area of substrate212, e.g., by deposition through a mask. In some embodiments, multilayer emitters204,208are initially formed by depositing materials over a larger surface area of substrate212, and then formed by removing material, e.g. by an etching or milling process, to expose surface206of multilayer emitter204and to expose surface210of multilayer emitter208. For example, a symmetric trench may be formed between multilayer emitters204,208by removing material.

Structure200includes anode216provided on substrate212. In some embodiments, anode216is provided on substrate212. For example, anode216may be provided on substrate212, after which multilayer emitters204,208are deposited on substrate212(e.g., by deposition through a mask); anode216may also be deposited on substrate212after material has been removed to form multilayer emitters204,208and expose surfaces206,210.

As shown inFIG. 2A, anode216includes surface218configured to capture electrons emitted from one-dimensional edges of 2DEGs formed along surface206of multilayer emitter204, and surface220configured to capture electrons emitted from one-dimensional edges of 2DEGs formed along surface210of multilayer emitter208. Surfaces218,220may be configured to be parallel to (e.g., at a constant distance from) at least a portion of surfaces206,210, respectively. In some embodiments, the anode216may be biased to increase or decrease field emission of electrons from the one-dimensional edges. In some embodiments, the distances between the surface206and the surface218, and between the surface210and the surface220, and/or the relative biases of the surfaces218,220, may be controlled or adjusted to manage field emission of electrons from the one-dimensional edges. In some embodiments, the etching/milling processes used to form the multilayer emitters204,208are controlled based on an expected or known bias of the anode216in order to set the field emission of electrons from the one-dimensional edges of the multilayer emitters204,208, such as to determine the distance between the surfaces206and218, the distance between the surfaces210and220, the orientation of the surface206relative to the surface218, and/or the orientation of the surface210relative to the surface210.

As shown inFIG. 2B, structure240includes multilayer emitters244,248provided on substrate252. Multilayer emitters244,248may be formed in a similar manner and may include similar features as multilayer emitters204,208shown inFIG. 2A. As shown inFIG. 2B, multilayer emitter244includes a first surface246from which electrons can be emitted towards anode256. Anode surface260of anode256is positioned to face first surface246of multilayer emitter244. Multilayer emitter248includes a second surface250from which electrons can be emitted towards anode264. Anode surface268of anode264is positioned to face second surface250of multilayer emitter248. Multilayer emitter248includes a third surface264, adjacent to which an insulator272is positioned. The insulator272is also positioned adjacent to the anode260, thus insulating the multilayer emitter248from the anode260, facilitating electron flow from the multilayer emitter248to the anode264. An insulator276is also positioned adjacent to the anode264and on an opposite side of the anode264from the anode surface268. A plurality of such structures combining anodes, insulators, and multilayer emitters may be provided along substrate252. For example, an insulator (not shown) may be positioned adjacent to an opposite side of the multilayer emitter244from the first surface246, and a multilayer emitter (not shown) may be positioned adjacent to the insulator276on an opposite side of the insulator276from the anode264.

As shown inFIG. 2C, structure280includes a first substrate282and a second substrate284spaced from the first substrate282. The first substrate282may be parallel to the second substrate284. A first multilayer emitter286and a second multilayer emitter288are disposed on a surface296of the second substrate284that faces the first substrate282. As shown inFIG. 2C, the multilayer emitters286,288do not contact the first substrate282. The multilayer emitters286,288are spaced apart from one another along the surface296of the substrate284such that a trench is formed between the substrates282,284and the multilayer emitters286,288. Electrons emitted from 2DEGs of multilayer emitters286,288may be emitted from surfaces290,292of multilayer emitters286,288. In some embodiments, surface290and/or surface292are formed to be oblique to the surface296of the substrate284. In some embodiments, surface290and/or surface292are formed to be perpendicular to the surface296of the substrate284.

As shown inFIG. 2C, an anode294is provided in the trench formed in the structure280. Surfaces of the anode294are positioned to face the surfaces290,292in order to collect emitted electrons. One or more alignment features, such as groove298, may be provided on substrate284and/or anode294to aid in positioning anode294relative to emitting surfaces290,292.

Now referring toFIG. 3, a flow diagram of a process300for fabricating a HMJFE structure is shown, according to one embodiment. The process300may include use of the components and materials discussed herein in regards toFIGS. 1A-2C. In alternative embodiments, fewer, additional, and/or different actions may be performed. Also, the use of a flow diagram is not meant to be limiting with respect to the order of actions performed. At302, a substrate is provided. At304, a first multilayer structure (e.g., a multilevel emitter structure) is disposed (e.g., stacked, attached, etc.) on the substrate. The first multilayer structure may include a plurality of layers, such as conducting layers, semiconductor layers, and/or insulator layers. The multi-layer structure may be deposited on the substrate in layers. A 2DEG can form at a junction between layers of the multilayer structure. At306, an isolation layer is stacked on the previous multilayer structure (e.g., stacked on the first multilayer structure), such as by deposition. At308, an additional multilayer structure is stacked on the isolation layer, such as by deposition. At310, it is determined if additional multilayer structures are required. If additional multilayer structures are required, then steps306-308may be repeated as necessary. Additional multilayer structures may also be disposed on the substrate instead of stacking on the existing multilayer structures.

If additional multilayer structures are not required, then at312, edges of 2DEGs of the HMJFE structure are exposed. In some embodiments, material is removed from the HMJFE, such as by an etching or milling process, to expose the edges. In some embodiments, the multi-layer structures were deposited through a mask over a limited area of the substrate. In various embodiments, the order of providing multilayer structures or layers thereof, along with exposing edges of 2DEGs of the HMJFE structure, may be modified as desired.

Vertical-emitting structures (e.g., structures emitting electrons in a direction perpendicular to a substrate) having a low work function may also be formed. Referring toFIG. 4, VEJFE structures (400a,400b, and400c) are shown, according to various embodiments. Each of structures400a,400b, and400cincludes a vertical structure (i.e., a structure extending upward from substrate408) comprised of core402which supports one or more vertically-oriented layers, e.g., layers404,406. At least one junction between layers is configured to support a 2DEG, similar to the 2DEG108at a junction between horizontal layers shown inFIG. 1A. For example, the vertically-oriented layers may include various combinations of conducting layers, semi-conductor layers, and/or insulating layers disposed adjacent to one another.

Structures400a,400b, and400cmay be deposited on a substrate408. The substrate408may be similar to the substrates122,212,252,282, or284discussed above with respect toFIGS. 1A-2C. Each of structures400a,400b, and400cmay include an anode or a grid. The anode can capture electrons emitted from the various exposed emitting edges of each of the structures400a,400b, and400c. The grid can control emission of the electrons from the various exposed emitting edges of each of the structures400a,400b, and400c.

In some embodiments, the anode or grid is provided as a conducting layer which is exposed near the exposed emitting edges of the structures400a,400b,400c. For example, a grid may extend to the truncated end of the vertical structure and be exposed by truncation in the same plane as the exposed emitted edge. Differential etching may also be used to expose the grid at a greater distance from the substrate408(e.g., further “above” the substrate408) than the exposed emitting edge. The grid may be provided on the outside of one or more of the structures400a,400b, and400c, and may act as a gate for electron emission. In some embodiments, the anode or grid is connected through a biasing layer in the substrate408that allows for biasing the anode or grid.

In one embodiment, structure400ais a cylindrical structure including doped semiconductor402a. In another embodiment, structure400bis a pyramid-shaped structure including doped semiconductor402b. In another embodiment, structure400cis a conical structure including doped semiconductor402c. An insulating layer can be deposited over the doped semiconductor layer. For example, insulators404a,404b, and404c, may each be formed over doped semiconductors402a,402b, and402c, respectively. A conducting layer may then be deposited over at least part of the insulating layer. For example, conductors406a,406b, and406c, may each be formed at least partially over insulators404a,404b, and404c, respectively. In various embodiments, the selection of doped semiconductor layers, conducting layers, and/or insulator layers may be interchanged for each of the structures400a,400b,400c. In some embodiments, one or more of the vertical structures are provided in a ridge shape (e.g., having a cross-section similar to structure400bbut extending in a direction normal to the plane ofFIG. 4).

In order to form effectively 1-dimensional electron emitters, the tops of the vertical structures (e.g.,400a,400b, and400c) may be exposed. For example, the tops of structures400a,400b, and400cmay be polished, ground, or otherwise machined to expose the edges of the doped semiconductor/insulator junctions within the structures. As a result, and depending on the shape of base structure (e.g., cylinder, pyramid, cone, etc.), a circular, linear, oval, etc., shaped emitting area with a low work function can be formed on the top of the vertical structure. A plurality of vertical structures (e.g., structures400a-c) may then be arranged in an array. In some embodiments, an anode or electrode grid is arranged over the tops of the vertical structures. The grid can control the emission of electrons from the exposed edges of the doped semiconductor/insulator junctions of the structures. The anodes can capture and, in some embodiments, control the emission of electrons from the exposed edges of the doped semiconductor/insulator junctions of the structures.

Referring toFIG. 5, a flow diagram of a process500for fabricating a VEJFE structure is shown, according to one embodiment. The process500may include use of the components and materials discussed herein in regards toFIG. 4. In alternative embodiments, fewer, additional, and/or different actions may be performed. Also, the use of a flow diagram is not meant to be limiting with respect to the order of actions performed. At502, a substrate is provided. At504-508, one or more vertical structures is formed on the substrate. Each vertical structure is formed by positioning at least two vertically oriented layers adjacent to one another. In various embodiments, the vertically oriented layers can be provided as a conducting layer, a semiconductor layer, and/or an insulating layer. Layers may be formed individually for each vertical structure, or may be formed by deposited a coating on a plurality of vertical structures. In one embodiment at least one of the vertical structures is in the shape of a cone. In another embodiment at least one of the vertical structures is in the shape of a pyramid. In another embodiment at least one of the vertical structures is in the shape of a cylinder. The vertical structures may be arranged in an array/grid pattern.

At506, a junction is created between two vertically oriented layers. A 2DEG is produced at the junction. At508, a determination is made as to whether additional vertical structures are required. If additional vertical structures are required, then the steps504-506may be repeated as necessary. If additional vertical structures are not required, then at510, the vertical structures are truncated on an opposite side of the vertical structures to expose an edge of the junction of each vertical structure. In some embodiments, vertical structures are individually truncated before additional vertical structures are provided. As such, the tops of one or more vertical structures are removed to expose each edge of each junction of each vertical structure. For example, the tops of the vertical structures may be polished, ground, or otherwise machined to expose the edges. In some embodiments, an electrode structure is provided as an anode or electrode grid and arranged over the tops of the vertical structures, and the anode or electrode grid is configured to control the emission of electrons from the exposed edges of the structures. In some embodiments, an electrode structure is formed as part of one or more individual vertical structures.

Although the figures may show a specific order of method steps, the order of the steps may differ from what is depicted. Also two or more steps may be performed concurrently or with partial concurrence. All such variations are within the scope of the disclosure. Likewise, software implementations could be accomplished with standard programming techniques with rule-based logic and other logic to accomplish the various connection steps, processing steps, comparison steps and decision steps.