Method and apparatus for verifying the installation of strapping devices on a circuit board assembly

An apparatus for verifying the installation of strapping devices on a circuit board assembly includes a plurality of strapping devices coupled to a plurality of configurable devices, an output port coupled to the plurality of strapping devices, and a plurality of input ports, coupled to the plurality of strapping devices with a corresponding first plurality of traces each having an associated pull-up resistor tied to a positive voltage level. The output port is adapted to output electrical signals of a first state at a first time and a second state at a second time to each of the plurality of strapping devices. The plurality of input ports receive the associated output signal from the plurality of strapping devices at each of the first time and the second time via the corresponding first plurality of traces, wherein unconfigured or malfunctioning ones of the plurality of strapping devices are identified.

BACKGROUND OF THE INVENTION 
1. Field of the Invention 
The present invention relates to the field of computer systems and, in 
particular, to a method and apparatus for verifying the installation of 
strapping devices on a circuit board assembly. 
2. Background Information 
Recognizing that "one size does not fit all" in the computer industry, many 
computer system manufacturers offer a wide variety of computer systems to 
satisfy a variety of markets and budgets. While such variety makes 
personal computers available to a wider spectrum of consumers, the same 
product variety adds complexity to the manufacturing process which, when 
left unaddressed, may well result in quality and efficiency problems. 
In an effort to improve efficiency and alleviate quality problems 
associated with the circuit board assembly process, many manufacturers 
have determined that it is more cost effective to settle on a few circuit 
board assembly "platforms". These platforms are essentially the same, or 
very similar, circuit board assemblies populated with similar components, 
wherein the operating characteristics of the circuit board assembly are 
determined by manually setting strapping devices to configure the 
configurable devices of the circuit board assembly. This manual setting of 
the strapping devices selectively configures a circuit board assembly 
"platform" into a particular genre of circuit board assembly (i.e., a 
circuit board assembly suitable for a particular use/product). In other 
words, the selective configuration of strapping devices configures an 
otherwise generic circuit board assembly with the "personality" 
characteristics (i.e., operating characteristics) commonly associated with 
a specific product. On, for example, computer system motherboards, 
strapping devices are often used to configure a clock source to supply a 
particular system bus clock frequency, or to indicate bus/core ratio 
(i.e., a the ratio of the bus clock frequency to the processor clock 
frequency) configuration information. Jumper blocks, dual-inline package 
(DIP) switches, double-pole single-throw (DPST) switches are but a few 
examples of strapping devices which are configured to select the operating 
configuration on a circuit board assembly. 
Although the concept of the selective configuration of a generic circuit 
board assembly with strapping devices has indeed improved some of the 
efficiency problems, it has not eliminated the quality concerns and, in 
fact, may have introduced new quality issues. For example, many of the 
prior art strapping devices are manually placed on the circuit board 
assembly in the manufacturing process, which is prone to human error. The 
misconfiguration of a circuit board assembly (i.e., the configuration of a 
strapping device which is inconsistent with the operating characteristics 
of a processor module) may well result in diminished performance or 
catastrophic failure for the consumer. 
Prior art test methods have not proven to be completely effective in 
verifying the installation and configuration of these strapping devices. 
An improved method and apparatus for the non-invasive testing of a circuit 
board assembly was disclosed the above identified copending parent 
application. However, many modem configurable devices incorporate internal 
pull-up or pull-down resistors on the configuration input coupled to the 
strapping device. The incorporation of the pull-up/pull-down resistors in 
these modern configurable devices may well result in a false determination 
that a strapping device is installed in either a "high" (i.e., a logic 1) 
configuration indicative of an internal pull-up resistor, or a "low" 
(i.e., logic 0) configuration indicative of an internal pull-down 
resistor. 
Thus a need exists for a method and apparatus for verifying the 
installation of strapping devices on a circuit board assembly wherein the 
strapping device is coupled to a configurable device having internal 
pull-up or pull-down resistors tied to the configuration input. 
SUMMARY OF THE INVENTION 
In accordance with the teachings of the present invention, a method and 
apparatus for verifying the installation of strapping devices on a circuit 
board assembly is presented. In one embodiment, an apparatus for verifying 
the installation of strapping devices on a circuit board assembly includes 
a plurality of strapping devices coupled to a plurality of configurable 
devices, an output port coupled to the plurality of strapping devices, and 
a plurality of input ports, coupled to the plurality of strapping devices 
with a corresponding first plurality of traces each having an associated 
pull-up resistor tied to a positive voltage level. The output port is 
adapted to output electrical signals of a first state at a first time and 
a second state at a second time to each of the plurality of strapping 
devices. The plurality of input ports receive the associated output signal 
from the plurality of strapping devices at each of the first time and the 
second time via the corresponding first plurality of traces, wherein 
unconfigured or malfunctioning ones of the plurality of strapping devices 
are identified. 
In one embodiment, the output port is a general purpose input/output port 
configured as an output port, while the plurality of input ports is a 
general purpose input/output port configured as an input port. The 
configurable device contains internal pull-up or pull-down resistors 
coupling the configurable device to the trace, such that without the 
teachings of the present invention, the testing of the strapping device 
might well result in an incorrect test result.

DETAILED DESCRIPTION 
In the following description, for purposes of explanation, specific 
numbers, materials and configurations are set forth in order to provide a 
thorough understanding of the present invention. However, it will be 
apparent to one skilled in the art that the present invention may be 
practiced without the specific details. In other instances, well known 
features are omitted or simplified in order not to obscure the present 
invention. Furthermore, for ease of understanding, certain method steps 
are delineated as separate steps, however, these separately delineated 
steps should not be construed as necessarily order dependent in their 
performance. 
Referring now to FIG. 1, a block diagram illustrating an exemplary computer 
system 10 incorporating the teachings of the present invention is shown. 
As depicted in FIG. 1, exemplary computer system 10 includes processor 14, 
cache memory 16, main memory 18, read-only memory 20, memory controller 
22, and processor bus 24 coupled to each other as depicted. Read-only 
memory 20 includes a set of basic input/output services (BIOS) (not shown) 
including start-up processes which, in one embodiment, verify the 
installation of strapping devices within computer system 10 using a method 
and apparatus as further described in FIGS. 2, 3 and 4. Additionally, 
computer system 10 includes an input and output (I/O) controller 26, a 
general purpose input and output (GPIO) device 36, a plurality of 
strapping devices 42, 43, 44, and 45 correspondingly coupled to a 
plurality of configurable devices 46, 47, 48 and 49 as shown, I/O bus 28, 
keyboard and cursor control device 30, display 32, and hard drive 34 
coupled to each other and the above enumerated elements as depicted. In 
one embodiment, elements 14-28 and 36-49 are disposed on a printed circuit 
board (e.g., motherboard) 12. 
In addition to the system BIOS, read-only memory 20 may also store system 
configuration information (not illustrated). The system configuration 
information is a summary listing of the operating configuration 
information for exemplary computer system 10. In particular, the system 
configuration information may contain such information as processor speed, 
bus/core ratio information, grade and access time for the main memory 18, 
and information relating to the desired settings for the plurality of 
strapping devices 42-45. 
However, the system configuration information need not be stored in 
read-only memory 20, but may be available in any other memory storage 
device. Except for verifying the installation of strapping device 42, 
elements 12-49 perform their respective conventional function as known in 
the art, and may be implemented in any of a number of conventional 
techniques known to those skilled in the art. In fact, exemplary computer 
system 10 is intended to represent a broad category of computer systems. 
Turning now to FIG. 2, a circuit diagram illustrating a circuit for 
verifying the installation of a strapping device, in accordance with the 
teachings of the present invention is shown. As depicted, the circuit 
includes general purpose input and output (GPIO) device 36 having a 
general purpose output 202 and a plurality of general purpose inputs 203, 
204, 206 and 208 (i.e., input ports) coupled to a corresponding plurality 
of strapping devices 42, 43, 44, and 45 with traces 213, 215, 217 and 219 
each having a pull-up resistor 212, 214, 216 and 218 tied to a positive 
voltage level. In addition to the plurality of general purpose inputs 
203-208, strapping devices 42-45 are also coupled to a plurality of 
configurable devices 46, 47, 48 and 49. In one embodiment, strapping 
devices 42-45 are coupled to configurable devices 46-49 via an input pin 
on each of configurable devices 46-49, wherein the input pin on each of 
the configurable devices 46-49 is tied to a positive logic level via an 
internal pull-up resistor 236-242. In one embodiment, the GPIO device 36 
is a National Semiconductor Super I/O.TM. Enhanced Sidewinder Lite, part 
number PC87307VUL/PC87308VUL commonly available from National 
Semiconductor in Sunnyvale, Calif. 
As depicted general purpose output 202 of GPIO device 36 is coupled to each 
of the strapping devices 42, 43, 44, and 45 with trace 210. In addition, 
strapping devices 42, 43, 44, and 45 are also coupled to the plurality of 
general purpose inputs 203, 204, 206 and 208 of GPIO device 36 via traces 
213, 215, 217 and 219, each of which having pull-up resistor 212, 214, 216 
and 218 tied to a positive voltage level (e.g., Vcc). 
The operation of the circuit of FIG. 2 will be illustrated with further 
reference to FIG. 4. The system begins, in step 402 with a request to 
verify the integrity and operating state of a strapping device 42-45 
received by GPIO device 36. In step 404, a first electrical signal at a 
positive potential (i.e., a logic `1`) is output on trace 210, by way of 
general purpose output 202, to each of the plurality of strapping devices 
42-45. While the general purpose output 202 outputs the first signal, the 
associated output of the plurality of strapping devices 42-45 is sampled 
via traces 213, 215, 217, 219, and by way of the plurality of input ports 
203, 204, 206 and 208. In step 406, the sampled associated output for each 
of the plurality of strapping devices 42-45 is analyzed to determine if 
any of the sampled associated output of the strapping devices is at ground 
potential (i.e., a logic level `0`). If so, in step 408, the system 
concludes that those strapping devices with a sampled associated output of 
a logic `0` are configured to assert a logic `0` to the corresponding 
configurable device. 
With continued reference to FIGS. 2 and 4, the method continues where, in 
step 410, a second electrical signal at ground potential (i.e., a logic 
`0`) is output on trace 210, by way of general purpose output 202, to each 
of the plurality of strapping devices 42-45. While the second electrical 
signal is output by way of general purpose output 202, the associated 
output of the plurality of strapping devices 42-45 is sampled via traces 
213, 215, 217, 219, and by way of the plurality of input ports 203, 204, 
206 and 208. In step 412, the sampled associated output from each of the 
plurality of strapping devices 42-45 is analyzed to determine if any of 
the output is at a ground potential (i.e., logic level `0`). For those 
strapping devices of the plurality of strapping devices 42-45 with a 
sampled associated output at ground potential, it is concluded, in step 
416, that the strapping device is configured to assert a positive 
potential (i.e., logic level `1`). 
Alternatively, for those strapping devices of the plurality of strapping 
devices 42-45 with a sampled associated of a positive potential, despite 
the second signal injected at ground potential, it is concluded that the 
sampled associated output of a positive potential is the result of the 
pull-up resistor (i.e., pull-up resistor 212, 214, 216 or 218) tied to a 
positive voltage level, in step 414. Thus, it is determined that those 
strapping devices with an associated output of a positive potential are 
not configured. 
Returning to steps 408 and 416 of FIG. 4, for each functional strapping 
device of the plurality of strapping devices 42-45 the system subsequently 
verifies, in step 418, that the strapping device 42-45 is appropriately 
configured by comparing the sampled associated output for each of the 
strapping devices with system configuration information (not shown). As 
alluded to earlier, the system configuration information may be maintained 
in a number of alternative memory locations such as, for example, 
non-volatile read-only memory 20, or hard drive 34 of exemplary computer 
system 10, or a remote memory or mass storage location (not shown) 
accessed via a network connection (not shown). 
Turning now to FIG. 3, a circuit diagram for verifying the integrity and 
operating configuration of a circuit board assembly is illustrated. In 
particular, the distinguishing difference between circuit 300 of FIG. 3 
and circuit 200 of FIG. 2 is that the configurable devices 46-49 of FIG. 3 
have pull-down resistors 310-316 tied to ground rather than the pull-up 
resistors 236-242 of FIG. 2. However, due to the addition of pullup 
resistors 212, 214, 216 and 218, the verification of the configuration of 
strapping devices 42-45 in accordance with the method steps of FIG. 4 is 
equally applicable to circuit 300 as to circuit 200, without regard to 
whether the configurable devices 46-49 contain pull-up resistors 236-242, 
pull-down resistors 310-316, or no internal pull-up/pull-down resistors at 
all, so long as the pull-up resistors chosen are sufficient to overcome 
the bias of the internal pull-down resistors of the configurable device. 
Thus, a method and apparatus for verifying the installation of strapping 
devices on a circuit board assembly has been described. While the method 
and apparatus of the present invention has been described in terms of the 
above illustrated embodiments, those skilled in the art will recognize 
that the invention is not limited to the embodiments described. For 
example, in step 404 of FIG. 4, rather than asserting a first signal at a 
positive potential, the general purpose output 202 may be allowed to 
simply float (i.e., no output), wherein associated output from each of the 
plurality of strapping devices is sampled and the process continues as 
depicted. Further, it is envisioned that the method illustrated in FIG. 4 
could be incorporated into the system start-up (i.e. boot) process 
controlled by the system BIOS or, alternatively, incorporated into a 
third-party software utility used to verify the integrity and operating 
configuration of a circuit board assembly. Thus, the present invention can 
be practiced with modification and alteration within the spirit and scope 
of the appended claims. Accordingly, the descriptions thereof are to be 
regarded as illustrative instead of restrictive on the present invention.