Operational amplifier and start-up circuit of operational amplifier

This application provides an operational amplifier and a start-up circuit of the operational amplifier. The start-up circuit has the advantages of having a simple structure and consuming less. The operational amplifier includes a multi-stage amplifier and a start-up circuit, where the start-up circuit includes a first start-up transistor and a second start-up transistor. A source of the first start-up transistor and a source of the second start-up transistor are connected to a tail bias node of a first-stage amplifier in the multi-stage amplifier, a gate of the first start-up transistor and a gate of the second start-up transistor are configured to connect to a first bias voltage Vb, and a drain of the first start-up transistor and a drain of the second start-up transistor are connected to input terminals of a second-stage or higher-stage amplifier.

TECHNICAL FIELD

This application relates to the field of electronic technologies, and in particular, to an operational amplifier and a start-up circuit of the operational amplifier.

BACKGROUND

As one of most basic modules in an analog integrated circuit, operational amplifiers (OPAs) are widely used in various analog circuits and digital-analog hybrid circuits. A radio frequency transceiver system is used as an example. Operational amplifiers are usually used in key modules, for example, a trans-impedance amplifier (TIA), a low-pass filter (LPF), a variable gain amplifier (VGA), an analog to digital converter (ADC), and a digital to analog converter (DAC). In a cascade link system, if pre-circuits or post-circuits of the key modules cannot provide a valid start-up signal, the operational amplifier may not be successfully started and may not operate in a normal amplification operation state. Therefore, an operational amplifier usually needs a start-up circuit to ensure self-start of the operational amplifier. The start-up circuit can provide a start-up current during a start-up process of the operational amplifier, to ensure that each transistor in the operational amplifier operates in a normal amplification operation state. Although in existing circuit designs, start-up circuits can have a plurality of topological structures, the industry has been searching for a start-up circuit with lower power consumption and simpler design.

SUMMARY

This application provides an operational amplifier and a start-up circuit of the operational amplifier. The start-up circuit has advantages of simple structure and low power consumption.

According to a first aspect, an operational amplifier is provided. The operational amplifier includes a multi-stage amplifier and a start-up circuit. The start-up circuit includes a first start-up transistor M16and a second start-up transistor M17, where a source of the first start-up transistor M16and a source of the second start-up transistor M17are connected to a tail bias node of a first-stage amplifier in the multi-stage amplifier, a gate of the first start-up transistor M16and a gate of the second start-up transistor M17are configured to connect to a first bias voltage Vb, and a drain of the first start-up transistor M16and a drain of the second start-up transistor M17are connected to input terminals of a second-stage or higher-stage amplifier.

In the operational amplifier provided in embodiments of this application, the start-up circuit included in the operational amplifier can quickly start the operational amplifier. A structure of the start-up circuit is simple, and no additional zero and pole are introduced. Therefore, bandwidth compensation does not need to be performed for the operational amplifier. This is conducive to a high-speed and high-gain design. In addition, the start-up circuit has a low operating current after the operational amplifier is started, and has an advantage of low power consumption.

With reference to the first aspect, in some possible implementations of the first aspect, the first bias voltage Vbis set, so that |VGS|>|Vth| when an input transistor pair of the first-stage amplifier is not turned on, and |VGS|<|Vth| after the operational amplifier is started, where VGSrepresents a gate-source voltage of each of the first start-up transistor M16and the second start-up transistor M17, and Vthrepresents a threshold voltage of each of the first start-up transistor M16and the second start-up transistor M17.

In some embodiments of this application, the first bias voltage Vb can be configured, so that after the start-up circuit of the operational amplifier is started. Therefore, in an ideal state, the operating current of the start-up circuit is zero. In this way, no additional direct current offset is introduced, performance of the operational amplifier is improved, and power consumption is reduced.

With reference to the first aspect, in some possible implementations of the first aspect, the tail bias node is a drain of a tail bias transistor M5of the first-stage amplifier.

With reference to the first aspect, in some possible implementations of the first aspect, the tail bias node is a terminal of a bias resistor of the first-stage amplifier.

With reference to the first aspect, in some possible implementations of the first aspect, the operational amplifier includes a three-stage amplifier, where the drain of the first start-up transistor M16is connected to a gate of a third input transistor M7of a second-stage amplifier, and the drain of the second start-up transistor M17is connected to a gate of a fourth input transistor M9of the second-stage amplifier.

With reference to the first aspect, in some possible implementations of the first aspect, the operational amplifier further includes a stability compensation circuit. The stability compensation circuit includes a first resistor R1, a second resistor R2, a first capacitor C1, and a second capacitor C2, where a first terminal of the first capacitor C1is connected to a drain of the third input transistor M7of the second-stage amplifier, a second terminal of the first capacitor C1is connected to a first terminal of the first resistor R1, and a second terminal of the first resistor R1is connected to a drain of a first input transistor M1of the first-stage amplifier; and a first terminal of the second capacitor C2is connected to a drain of the fourth input transistor M9of the second-stage amplifier, a second terminal of the second capacitor C2is connected to a first terminal of the second resistor R2, and a second terminal of the second resistor R2is connected to a drain of a second input transistor M2of the first-stage amplifier.

With reference to the first aspect, in some possible implementations of the first aspect, the operational amplifier further includes a common mode detection circuit. The common mode detection circuit includes: a first input terminal, configured to receive a first differential output voltage Voutp output by the operational amplifier; a second input terminal, configured to receive a second differential output voltage Voutn output by the operational amplifier; and an output terminal, configured to output a common mode output voltage VCM, where the common mode output voltage VCMis an average value of the first differential output voltage Voutp and the second differential output voltage Voutn.

With reference to the first aspect, in some possible implementations of the first aspect, the common mode detection circuit includes a third resistor R3and a fourth resistor R4, where a first terminal of the third resistor R3is connected to a first differential output terminal of the operational amplifier, a second terminal of the third resistor R3is connected to a first terminal of the fourth resistor R4, a second terminal of the fourth resistor R4is connected to a second differential output terminal of the operational amplifier, and the second terminal of the third resistor R3is an output terminal of the common mode detection circuit.

With reference to the first aspect, in some possible implementations of the first aspect, the operational amplifier further includes a common mode loop compensation circuit. The common mode loop compensation circuit includes a third capacitor C3and a fourth capacitor C4, where a first terminal of the third capacitor C3is connected to the first differential output terminal of the operational amplifier, a second terminal of the third capacitor C3is connected to a first terminal of the fourth capacitor C4, and a second terminal of the fourth capacitor C4is connected to the second differential output terminal of the operational amplifier.

With reference to the first aspect, in some possible implementations of the first aspect, the operational amplifier further includes a common mode negative feedback circuit. The common mode negative feedback circuit includes an error amplifier, where a first input terminal of the error amplifier is configured to receive a common mode reference voltage VCMREFof the operational amplifier, a second input terminal of the error amplifier is configured to receive the common mode output voltage VCMoutput by the common mode detection circuit, and an output terminal of the error amplifier is connected to a bias circuit of the operational amplifier.

According to a second aspect, a start-up circuit of an operational amplifier is provided. The operational amplifier includes a multi-stage amplifier. The start-up circuit includes a first start-up transistor M16and a second start-up transistor M17, where a source of the first start-up transistor M16and a source of the second start-up transistor M17are connected to a tail bias node of a first-stage amplifier in the multi-stage amplifier, a gate of the first start-up transistor M16and a gate of the second start-up transistor M17are configured to connect to a first bias voltage Vb, and a drain of the first start-up transistor M16and a drain of the second start-up transistor M17are connected to input terminals of a second-stage or higher-stage amplifier.

The start-up circuit provided in embodiments of this application can quickly start the operational amplifier. A structure of the start-up circuit is simple, and no additional zero and pole are introduced. Therefore, bandwidth compensation does not need to be performed for the operational amplifier. This is conducive to a high-speed and high-gain design. In addition, the start-up circuit has a low operating current after the operational amplifier is started, and has an advantage of low power consumption.

With reference to the second aspect, in some possible implementations of the second aspect, the first bias voltage Vbis set, so that |VGS|>|Vth| when an input transistor pair of the first-stage amplifier is not turned on, and

|VGS|<|Vth| after the operational amplifier is started, where VGSrepresents a gate-source voltage of each of the first start-up transistor M16and the second start-up transistor M17, and Vthrepresents a threshold voltage of each of the first start-up transistor M16and the second start-up transistor M17.

With reference to the second aspect, in some possible implementations of the second aspect, the tail bias node is a drain of a tail bias transistor M5of the first-stage amplifier.

With reference to the second aspect, in some possible implementations of the second aspect, the tail bias node is a terminal of a bias resistor of the first-stage amplifier.

With reference to the second aspect, in some possible implementations of the second aspect, the operational amplifier includes a three-stage amplifier, where the drain of the first start-up transistor M16is connected to a gate of a third input transistor M7of a second-stage amplifier, and the drain of the second start-up transistor M17is connected to a gate of a fourth input transistor M9of the second-stage amplifier.

With reference to the second aspect, in some possible implementations of the second aspect, the operational amplifier further includes:a stability compensation circuit, including a first resistor R1, a second resistor R2, a first capacitor C1, and a second capacitor C2, where a first terminal of the first capacitor C1is connected to a drain of the third input transistor M7of the second-stage amplifier, a second terminal of the first capacitor C1is connected to a first terminal of the first resistor R1, and a second terminal of the first resistor R1is connected to a drain of a first input transistor M1of the first-stage amplifier; and a first terminal of the second capacitor C2is connected to a drain of the fourth input transistor M9of the second-stage amplifier, a second terminal of the second capacitor C2is connected to a first terminal of the second resistor R2, and a second terminal of the second resistor R2is connected to a drain of a second input transistor M2of the first-stage amplifier.

With reference to the second aspect, in some possible implementations of the second aspect, the operational amplifier further includes a common mode detection circuit. The common mode detection circuit includes: a first input terminal, configured to receive a first differential output voltage Voutp output by the operational amplifier; a second input terminal, configured to receive a second differential output voltage Voutn output by the operational amplifier; and an output terminal, configured to output a common mode output voltage VCM, where the common mode output voltage VCMis an average value of the first differential output voltage Voutp and the second differential output voltage Voutn.

With reference to the second aspect, in some possible implementations of the second aspect, the common mode detection circuit includes a third resistor R3and a fourth resistor R4, where a first terminal of the third resistor R3is connected to a first differential output terminal of the operational amplifier, a second terminal of the third resistor R3is connected to a first terminal of the fourth resistor R4, a second terminal of the fourth resistor R4is connected to a second differential output terminal of the operational amplifier, and the second terminal of the third resistor R3is an output terminal of the common mode detection circuit.

With reference to the second aspect, in some possible implementations of the second aspect, the operational amplifier further includes a common mode loop compensation circuit. The common mode loop compensation circuit includes a third capacitor C3and a fourth capacitor C4, where a first terminal of the third capacitor C3is connected to the first differential output terminal of the operational amplifier, a second terminal of the third capacitor C3is connected to a first terminal of the fourth capacitor C4, and a second terminal of the fourth capacitor C4is connected to the second differential output terminal of the operational amplifier.

With reference to the second aspect, in some possible implementations of the second aspect, the operational amplifier further includes: a common mode negative feedback circuit. The common mode negative feedback circuit includes an error amplifier, where a first input terminal of the error amplifier is configured to receive a common mode reference voltage VCMREFof the operational amplifier, a second input terminal of the error amplifier is configured to receive the common mode output voltage VCMoutput by the common mode detection circuit, and an output terminal of the error amplifier is connected to a bias circuit of the operational amplifier.

According to a third aspect, a chip is provided. The chip includes the operational amplifier according to the first aspect or any possible implementation of the first aspect.

According to a fourth aspect, an electronic device is provided. The electronic device includes the operational amplifier according to the first aspect or any possible implementation of the first aspect.

DESCRIPTION OF EMBODIMENTS

Embodiments of this application provide an operational amplifier and a start-up circuit of the operational amplifier. The start-up circuit has advantages of simple circuit structure and low power consumption, and can quickly start the operational amplifier.

FIG.1is a schematic diagram of an application environment according to an embodiment of this application.FIG.1is a schematic diagram of link cascading in a radio frequency system. The radio frequency system is a receiver system, and includes a low-noise amplifier (LNA), a mixer, a trans-impedance amplifier (TIA), a low-pass filter (LPF), and an analog to digital converter (ADC). The operational amplifier in embodiments of this application may be disposed in modules inFIG.1, for example, the TIA, the LPF, a VGA, and the ADC. It should be noted thatFIG.1is merely used as an example to describe the application environment of the operational amplifier in embodiments of this application, and the operational amplifier may be widely used in various analog integrated circuits or digital-analog integrated circuits. For example, the operational amplifier may be used in a filter circuit, an amplification circuit, an operation circuit, a signal generation circuit, a signal conversion circuit, or a power supply.

After the operational amplifier is started, there are usually two stable states: a normal amplification operation state and an abnormal amplification operation state. The abnormal amplification operation state may refer to that an input voltage of the operational amplifier exceeds a normal input voltage range of the operational amplifier. The abnormal amplification operation state includes two cases: a low input bias and a high input bias. The low input bias refers to that the input voltage of the operational amplifier is lower than a lower limit of the normal input voltage range of the operational amplifier, and the high input bias refers to that the input voltage of the operational amplifier is higher than an upper limit of the normal input voltage range of the operational amplifier. When the operational amplifier is in the abnormal amplification operation state, operation performance of the operational amplifier in a circuit module or circuit system is affected. For example, in the abnormal amplification operation state, an input transistor pair of the operational amplifier may be in a sub-threshold region, and an operating current is much lower than an expected value. Consequently, various characteristic parameters of a circuit are affected, and the circuit is deviated from design indexes.

If a pre-circuit or post-circuit of a module in which the operational amplifier is located cannot provide a valid start-up signal, the operational amplifier cannot operate in the normal amplification operation state, but operates in the abnormal amplification operation state. To ensure that the operational amplifier operates in the normal amplification operation state after being started, the operational amplifier usually needs a start-up circuit to ensure self start-up of the operational amplifier. The start-up circuit can provide a start-up current during a start-up process of the operational amplifier, to ensure that each transistor in the operational amplifier operates in the normal amplification operation state.

In a conventional technology, there are various start-up circuits with different principles and topological structures. However, an existing start-up circuit has a deficiency. For example, because a large quantity of start-up loop stages are implemented during a start-up process of the start-up circuit, an additional stability compensation design is needed. Alternatively, the start-up circuit still operates after being started. Consequently, additional power consumption is consumed. In addition, the start-up circuit is complex in design and occupies a large chip area.

Therefore, embodiments of this application provide a start-up circuit, to quickly start the operational amplifier. A structure of the start-up circuit is simple, and performance of a main signal channel is not affected. In addition, the start-up circuit has a low operating current after the operational amplifier is started, and has an advantage of low power consumption. Refer toFIG.2toFIG.5. The following describes in detail an operational amplifier and a start-up circuit of the operational amplifier that are provided in embodiments of this application.

FIG.2is a schematic diagram of a structure of an operational amplifier200according to an embodiment of this application. The operational amplifier200may include a multi-stage amplifier, for example, the operational amplifier200may be a two-stage amplifier, a three-stage amplifier, or a higher-stage amplifier. InFIG.2, that the operational amplifier200is a two-stage amplifier is used as an example for description.

As shown inFIG.2, the operational amplifier200includes a first-stage amplifier, a second-stage amplifier, and a start-up circuit. An input terminal of the operational amplifier200may be a differential input terminal. An output terminal of the operational amplifier200may be a differential output terminal, or may be a single output terminal. This is not limited in this embodiment of this application. If input terminals of the operational amplifier200are differential intput terminals, the differential input terminals may be respectively referred to as a first differential input terminal Vinp and a second differential input terminal Vinn. Differential output terminals of the operational amplifier may be respectively referred to as a first differential output terminal Voutp and a second differential output terminal Voutn.

The first-stage amplifier includes a bias circuit, a tail bias circuit, and an input transistor pair (M1, M2). For ease of description, the transistor M1and the transistor M2may be referred to as a first input transistor M1and a second input transistor M2, or collectively referred to as an input transistor pair of the first-stage amplifier. Gates (g) of the input transistor pair (M1, M2) are respectively the differential input terminals (Vinp, Vinn) of the operational amplifier200. Sources (s) of the input transistor pair (M1, M2) are connected to the tail bias circuit, and drains (d) of the input transistor pair (M1, M2) are connected to the bias circuit. Drains (d) of the input transistor pair (M1, M2) are output terminals of the first-stage amplifier, and are connected to input terminals of the second-stage amplifier. The tail bias circuit and the bias circuit are configured to provide a bias current for the input transistor pair (M1, M2).

Still refer toFIG.2. The start-up circuit includes a first start-up transistor M16and a second start-up transistor M17, where the first start-up transistor M16and the second start-up transistor M17form a differential transistor pair. For ease of description, the transistor M16and the transistor M17may be collectively referred to as a start-up transistor pair. Sources (s) of the start-up transistor pair (M16, M17) are connected to a tail bias node P of the first-stage amplifier, gates (g) of the start-up transistor pair (M16, M17) are configured to connect to a first bias voltage Vb, and drains (d) of the start-up transistor pair (M16, M17) may be connected to the input terminals of the second-stage amplifier or input terminals of a higher-stage amplifier. As an example, the drains (d) of the start-up transistor pair (M16, M17) shown inFIG.2are connected to the input terminals of the second-stage amplifier.

The tail bias node P of the first-stage amplifier may refer to a node at which the tail bias circuit of the first-stage amplifier is connected to the sources(s) of the input transistor pair (M1, M2). For example, the tail bias circuit may include a tail bias transistor, and the tail bias node P may be a drain of the tail bias transistor of the first-stage amplifier. Alternatively, the tail bias circuit may include a bias resistor, and the tail bias node P is a terminal of the bias resistor of the first-stage amplifier. Alternatively, the tail bias node P may be the sources(s) of the input transistor pair (M1, M2). In some embodiments of this application, a voltage at the tail bias node P may be represented by Vp.

An input terminal of the second-stage or higher-stage amplifier may be a differential input terminal. For example, differential input terminals of the second-stage amplifier may include a first differential input terminal Vinp2and a second differential input terminal Vinn2. In some examples, the drains (d) of the start-up transistors M16and M17may be respectively connected to the two differential input terminals of the second-stage or higher-stage amplifier. As shown inFIG.2, the drain (d) of the first start-up transistor M16is connected to the first differential input terminal Vinp2of the second-stage amplifier, and the drain (d) of the second start-up transistor M17is connected to the second differential input terminal Vinn2of the second-stage amplifier.

In some examples, a connection manner of the sources (s) and the drains (d) of the start-up transistor pair (M16, M17) is the same as a connection manner of the sources (s) and the drains (d) of the input transistor pair (M1, M2) of the first-stage amplifier. To be specific, the sources (s) of the start-up transistor pair (M16, M17) are connected to a same node as the sources (s) of the input transistor pair (M1, M2), and the drains (d) of the start-up transistor pair (M16, M17) are connected to a same node as the drains (d) of the input transistor pair (M1, M2).

After the operational amplifier200is powered on, bias voltages in the circuit are first established, for example, the first bias voltage Vband bias voltages in the tail bias circuit and the bias circuit. After the bias voltages are established, the start-up transistors (M16, M17) are first turned on to generate an operating current and drive the second-stage amplifier of the operational amplifier to operate. After the second-stage amplifier is started, the input transistor pair (M1, M2) is driven by an external loop feedback to operate, so that the operational amplifier200enters a normal operation state, thereby completing start-up of the operational amplifier200.

In some examples, to successfully turn on the start-up transistors (M16, M17) after the operational amplifier200is powered on, the first bias voltage Vbis set, so that |VGS|>|Vth| before the operational amplifier200is started, where VGSrepresents a gate-source voltage of each of the start-up transistor pair (M16, M17), and Vthrepresents a threshold voltage of each of the start-up transistor pair (M16, M17). When |VGS|>|Vth| the start-up transistor pair (M16, M17) is in an on state. Therefore, after the operational amplifier200is powered on, the start-up transistor pair (M16, M17) is first turned on, and the operating current is generated, to start the operational amplifier. The gate-source voltage VGSof each of the start-up transistor pair (M16, M17) may be represented as VGS=Vb−Vp, where Vprepresents the voltage at the tail bias node P. After the start-up circuit is started, the first-stage amplifier normally operates, and the tail bias circuit provides a bias current for the input transistor pair (M1, M2). In this case, the voltage Vpat the tail bias node P increases, and a magnitude of the first bias voltage Vbremains unchanged. Therefore, the gate-source voltage VGS=Vb−Vpof each of the start-up transistor pair (M16, M17) decreases, so that the operating current of the start-up transistor pair (M16, M17) starts to decrease, and power consumption of the start-up circuit is also reduced.

In some examples, to reduce the operating current of the start-up transistors (M16, M17) after the operational amplifier200is started, the first bias voltage Vbis set, so that |VGS|<|Vth| after the operational amplifier200is started. If the first bias voltage Vbis reasonably set, |VGS|<|Vth| after the operational amplifier200is started (that is, after the operational amplifier200is in a normal amplification operation state). In this case, the start-up transistor pair (M16, M17) is in an off state. In an ideal state, the operating current of the start-up transistor pair (M16, M17) is zero, thereby reducing the power consumption of the start-up circuit.

A structure of the start-up circuit of the operational amplifier in embodiments of this application is simple, and can be implemented with only two transistors. After the operational amplifier200is started, because the gate-source voltage VGSof each of the start-up transistors (M16, M17) decreases, the operating current IDof the start-up circuit after the operational amplifier is started is small. This is conducive to implementing a circuit with low power consumption. For ease of description, Formula (1) shows an operating current formula of the transistors when the transistors operate in a saturation region.

IDrepresents an operating current, μ represents mobility of carriers, Coxrepresents a unit area capacitance of a gate oxide layer of a transistor, W represents a channel width of the transistor, L represents a channel length of the transistor, VGSrepresents a gate-source voltage of the transistor, and Vthrepresents a threshold voltage of the transistor.

It can be seen from Formula (1) that, as VGSdecreases, the operating current IDdecreases. If VGSis less than Vth, an operation state of a MOS transistor enters a cutoff region. In an ideal state, the operating current IDis zero.

In some examples, the first bias voltage Vbmay be set to be equal to a common mode reference voltage VCMREFof the operational amplifier200.

A loop of the start-up circuit in embodiments of this application is simple, and no additional zero and pole are introduced. Therefore, bandwidth compensation does not need to be performed for the operational amplifier. This is conducive to a high-speed and high-gain design.

The start-up circuit in some embodiments of this application uses a differential structure, and has a good differential characteristic. In addition, after the operational amplifier is started, the operating current of the start-up circuit decreases, or is even zero, so that no additional direct current offset (DC offset) is introduced. This is conducive to an advanced low-voltage process design.

Optionally, the start-up transistor pair (M16, M17) may be N-type metal-oxide-semiconductor (NMOS) transistors or P-type metal-oxide-semiconductor (PMOS) transistors. For example, a type of the start-up transistor pair (M16, M17) may be the same as a type of the input transistor pair (M1, M2) of the first-stage amplifier. If the input transistors (M1, M2) are NMOS transistors, the start-up transistors (M16, M17) are NMOS transistors. If the input transistors (M1, M2) are PMOS transistors, the start-up transistors (M16, M17) are PMOS transistors.

Optionally, the operational amplifier in some embodiments of this application may use a complementary metal oxide semiconductor (CMOS) process, or may use another integrated circuit process. For example, the operational amplifier may use a bipolar junction transistor (BJT) process or a silicon-on-insulator (SOI) process.

FIG.3is a schematic diagram of a structure of an operational amplifier300according to another embodiment of this application. A structure of the operational amplifier300inFIG.3is similar to the structure of the operational amplifier200inFIG.2, and a difference lies in that the drains of the start-up transistor pair (M16, M17) are respectively connected to two differential input terminals of a third-stage amplifier. To be specific, the drain of the first start-up transistor M16is connected to a first differential input terminal of the third-stage amplifier, and the drain (d) of the second start-up transistor M17is connected to a second differential input terminal of the third-stage amplifier.

Optionally, the start-up transistor pair (M16, M17) in one embodiment of this application may be alternatively replaced by a single transistor. For example,FIG.4is a schematic diagram of a structure of an operational amplifier400according to another embodiment of this application. As shown inFIG.4, a start-up circuit may include only a first start-up transistor M16, where a source of the first start-up transistor M16is configured to connect to a tail bias node P, a gate of the first start-up transistor M16is configured to connect to a first bias voltage Vb, and a drain of the first start-up transistor M16is configured to connect to an input terminal of a second-stage or higher-stage amplifier. The drain of the first start-up transistor M16inFIG.4is configured to connect to any one of two differential input terminals of the second-stage amplifier. In some examples, the drain of the first start-up transistor M16may be alternatively configured to connect to any one of two differential input terminals of the higher-stage amplifier.

FIG.5is a schematic diagram of a circuit structure of an operational amplifier500according to another embodiment of this application. The operational amplifier500inFIG.5is a two-stage amplifier. It should be understood that after limited deformation, a structure of the operational amplifier500is also applicable to a three-stage amplifier or a higher-stage amplifier. As shown inFIG.5, a first-stage amplifier circuit of the operational amplifier includes transistors M1, M2, M3, M4, and M5. The bias circuit of the first-stage amplifier inFIG.2toFIG.4may include the transistors M3and M4inFIG.5. The tail bias circuit of the first-stage amplifier inFIG.2toFIG.4may include the transistor M5inFIG.5. For ease of description, the transistors M3and M4may be referred to as bias transistors, and the transistor M5may be referred to as a tail bias transistor. A second-stage amplifier circuit of the operational amplifier includes transistors M6, M7, M8, and M9.

In the first-stage amplifier circuit, sources of the bias transistors M3and M4are connected to a power supply VDD, and drains of the bias transistors M3and M4are connected to drains of the input transistor pair (M1, M2). The transistor M7and the transistor M9are an input transistor pair of the second-stage amplifier. For ease of description, the transistor M7and the transistor M9may be referred to as a third input transistor M7and a fourth input transistor M9of the second-stage amplifier. A gate of the third input transistor M7is a first differential input terminal of the second-stage amplifier, and a gate of the fourth input transistor M9is a second differential input terminal of the second-stage amplifier. A drain of the third input transistor M7is a first differential output terminal of the second-stage amplifier, a drain of the fourth input transistor M9is a second differential output terminal of the second-stage amplifier, and the drains of the third input transistor M7and the fourth input transistor M9are also differential output terminals of the operational amplifier.

As shown inFIG.5, a start-up circuit includes a first start-up transistor M16and a second start-up transistor M17. Gates of the first start-up transistor M16and the second start-up transistor M17are configured to connect to a first bias voltage Vb. Sources of the first start-up transistor M16and the second start-up transistor M17are connected, and are connected to a drain of the tail bias transistor M5. A drain of the first start-up transistor M16is connected to the gate of the third input transistor M7of the second-stage amplifier, and a drain of the second start-up transistor M17is connected to the gate of the fourth input transistor M9of the second-stage amplifier. The drain of the third input transistor M7is a differential output terminal Voutp of the operational amplifier, and the drain of the fourth input transistor M9is a differential output terminal Voutn of the operational amplifier.

Optionally, the operational amplifier further includes a stability compensation circuit, and the stability compensation circuit may be used for frequency compensation of a fully differential amplifier. As shown inFIG.5, as an example, the stability compensation circuit includes a first resistor R1, a second resistor R2, a first capacitor C1, and a second capacitor C2. The drain of the third input transistor M7is connected to a first terminal of the first capacitor C1, a second terminal of the first capacitor C1is connected to a first terminal of the first resistor R1, and a second terminal of the first resistor R1is connected to a drain of a first input transistor M1of a first stage amplifier. The drain of the fourth input transistor M9is connected to a first terminal of the second capacitor C2, a second terminal of the second capacitor C2is connected to a first terminal of the second resistor R2, and a second terminal of the second resistor R2is connected to a drain of a second input transistor M2of the first-stage amplifier. A transistor M15is a current mirror bias circuit of the operational amplifier, and is configured to receive a bias current and generate a bias voltage for the operational amplifier. A transistor M12and a transistor M13are diode-connected and constitute a load of an error amplifier in a common mode negative feedback circuit.

Optionally, the operational amplifier further includes a common mode detection circuit, and the common mode detection circuit is configured to generate a common mode output voltage VCMof the operational amplifier. The common mode detection circuit includes: a first input terminal, configured to receive a first differential output voltage Voutp output by the operational amplifier; a second input terminal, configured to receive a second differential output voltage Voutn output by the operational amplifier; and an output terminal, configured to output the common mode output voltage VCM, where the common mode output voltage VCMis an average value of the first differential output voltage Voutp and the second differential output voltage Voutn, that is, VCM=(Voutp+Voutn)/2.

As shown inFIG.5, as an example, the common mode detection circuit includes a third resistor R3and a fourth resistor R4, where a first terminal of the third resistor R3is connected to a first differential output terminal Voutp of the operational amplifier, a second terminal of the third resistor R3is connected to a first terminal of the fourth resistor R4, a second terminal of the fourth resistor R4is connected to a second differential output terminal Voutn of the operational amplifier, and the second terminal of the third resistor R3is an output terminal of the common mode detection circuit.

Optionally, the operational amplifier further includes a common mode loop compensation circuit, and the common mode loop compensation circuit is configured to compensate for frequency of a common mode loop. As shown inFIG.5, as an example, the common mode loop compensation circuit includes a third capacitor C3and a fourth capacitor C4, where a first terminal of the third capacitor C3is connected to the first differential output terminal Voutp of the operational amplifier, a second terminal of the third capacitor C3is connected to a first terminal of the fourth capacitor C4, and a second terminal of the fourth capacitor C4is connected to the second differential output terminal Voutn of the operational amplifier. The second terminal of the third capacitor C3is connected to the output end of the common mode detection circuit. In other words, the second terminal of the third capacitor C3is connected to the second terminal of the third resistor R3.

Optionally, the operational amplifier further includes a common mode negative feedback circuit, where the common mode negative feedback circuit is configured to compare the common mode output voltage VCMwith a common mode reference voltage VCMREF, and adjust a bias circuit of the operational amplifier based on a comparison result, so that the common mode output voltage VCMis equal to the common mode reference voltage VCMREF. As shown inFIG.5, the common mode negative feedback circuit includes the error amplifier, a first input terminal of the error amplifier is configured to connect to the common mode reference voltage VCMREFof the operational amplifier, and a second input terminal of the error amplifier is configured to connect to the common mode output voltage VCMof the operational amplifier, that is, to connect to the second terminal of the third resistor R3. An output terminal of the error amplifier is connected to the bias circuit of the operational amplifier, to adjust the bias circuit of the operational amplifier.

As shown inFIG.5, as an example, the error amplifier includes transistors M10, M11, M12, M13, and M14. The transistor M10and the transistor M11are amplifier transistors, and the transistors M12, M13, and M14are bias transistors. Gates of the transistor M10and the transistor M11are differential input terminals of the error amplifier, and a drain of the transistor M10is an output terminal of the error amplifier. The gate of the transistor M10in the common mode negative feedback circuit is connected to the second terminal of the third resistor R3in the common mode detection circuit. The gate of the transistor M11in the common mode negative feedback circuit is configured to connect to the common mode reference voltage VCMREF.

It should be understood thatFIG.5is merely an example rather than a limitation of a specific circuit structure of the operational amplifier in embodiments of this application. For example, the stability compensation circuit, the common mode detection circuit, the common mode loop compensation circuit, or the common mode negative feedback circuit inFIG.5may also be implemented in another manner. This is not limited in this embodiment of this application.