SRAM devices and methods of fabricating the same

SRAM devices and methods of fabricating the same are disclosed, by which a process margin and a degree of device integration are enhanced by reducing the number of contact holes of an SRAM device unit cell using local interconnections. A disclosed example device includes first and second load elements; first and second drive transistors; a common gate electrode connected in one body to a gate electrode of the first load element and a gate electrode of the first drive transistor to apply a sync signal to the gate electrodes; the common gate electrode overlapping with a junction layer of the second load element and a junction layer region of the second drive transistor; the common gate electrode being electrically connected to an upper line via a plug in one contact hole.

FIELD OF THE DISCLOSURE

The present disclosure relates to SRAM devices and methods of fabricating the same, by which a process margin and degree of device integration are enhanced by reducing the number of contact holes of an SRAM device unit cell using local interconnection.

BACKGROUND

Generally, a unit cell of a static random access memory (hereinafter abbreviated “SRAM”) includes six transistors (6-Tr). More specifically, a unit cell typically includes two drive transistors, two access transistors, and two load elements.

A circuit and layout of a prior art 6-Tr SRAM unit cell will now be explained.FIG. 1is a circuit diagram of the prior art SRAM device unit cell.FIG. 2is a layout of the prior art SRAM device unit cell.

Referring toFIG. 1andFIG. 2, the SRAM device unit cell includes access transistors Q1(250) and Q3(260) having gates connected to a wordline WL and drains connected to positive and negative bitlines BL and/BL, respectively. The SRAM device unit cell also includes load elements Q5(210) and Q6(220) having their sources connected to a power voltage Vcc. The unit cell also includes a positive cell node N which is commonly connected to a drain of the load element Q5(210) and to the source of the access transistors Q1(250). The unit cell also has a negative cell node/N which is commonly connected to a drain of the load element Q6(220) and to the source of the access transistors Q3(260). The unit cell is further provided with drive transistors Q2(230) and Q4(240). The drive transistor Q2is connected to the drain of the load element Q5. The drive transistor Q4is connected to the drain of the load element Q6. The gates of the drive transistors Q2, Q4are respectively connected to the gates of the load elements Q5, Q6in a CMOS configuration. Further, the gates of the drive transistors Q2(230), Q4(240) are cross-linked to the positive and negative cell nodes N,/N, respectively.

The area enclosed by a dotted-line square inFIG. 2corresponds to the unit cell of the 6-Tr SRAM device. Each area enclosed by a solid line within the unit cell corresponds to an active area. Moreover, each hatched square indicates a contact hole206.

Referring toFIG. 2, a common gate electrode271is provided to apply a sync signal to the gates of the load element210and the drive transistor230. Upper metal lines (not shown in the drawing) are formed on an insulating inter layer covering the six transistors. Contact holes are formed in the insulating interlayer to connect the six transistors to the upper metal lines. Each of the contact holes206is filled with a conductive plug. In the unit cell of the SRAM device shown inFIG. 2, eight and half (8.5) contact holes are formed for the connections between the transistors and the metal lines.

Specifically, the 8.5 contact holes include 6.5 contact holes for connections to the junctions (source/drain) of the transistors and 2 contact holes for connection to the common gate electrodes of the transistors.

As the design rule is reduced due to the greatly increasing degree of integration in a semiconductor device, the unit cell area or size of the SRAM device is reduced as well. However, the unit cell of the 6-Tr SRAM device requires the 8.5 contact holes which occupy a considerable fixed area within the unit cell.

To keep up with the rapidly increasing degree of integration of the SRAM device, the number of contact holes required for the unit cell of the SRAM device must be lowered as the design rule is reduced.

A prior art method of reducing the number of the contact holes in the unit cell of the SRAM device will now be explained with reference toFIG. 3.FIG. 3is a cross-sectional view of the SRAM device unit cell inFIG. 2taken along cutting line A-A′.

Referring toFIG. 3, a field oxide layer202is provided in a field area to define an active area of a semiconductor substrate201. Gate electrodes203,204of a drive transistor and a load element are formed in the active areas of the substrate201. Sources S and drains D are provided to on opposite sides of the gate electrodes203,204.

A gate insulating layer (not shown in the drawing) is provided beneath each of the gate electrodes203,204. A spacer (not shown in the drawing) may be provided on each sidewall of the gate electrodes203,204.

A common gate electrode271is formed between the gate electrodes203,204to apply a sync signal to the gate electrodes203,204of the load element and the drive transistor.

An insulating layer205is formed on the substrate201including the common gate electrode271. An upper line (not shown in the drawing) is formed on the insulating interlayer205.

The source/drain S/D and the common gate electrode271are electrically connected to the upper line via respective plugs207. The plugs207fill contact holes206provided in the insulating interlayer205. The contact holes206are formed by selectively etching the insulating interlayer205to expose two junction layers (source or drain) of the two transistors and the common gate electrode271.

In the unit cell of the illustrated prior art SDRAM device, three contact holes are required for electrical connections between the upper line and the load element, the common gate electrode271and the drive transistor.

As shown inFIG. 2, the contact holes provided for the load element, the common gate electrode271, and the drive transistor are aligned on almost the same line. Since the contact holes are nearly aligned on the same straight line and are densely aggregated, the process margin is lowered due to the reduced design rule.

Moreover, as the number of contact holes required for the unit cell of the SRAM device is fixed at 8.5, it is difficult to increase the degree of integration of the semiconductor device.

DETAILED DESCRIPTION

FIG. 4is a diagram illustrating the layout of an example SRAM device unit cell constructed in accordance with the teachings of the present invention. Referring toFIG. 4, an example unit cell of the SRAM device includes six transistors. In particular, it includes a pair of load elements410,420, a pair of drive transistors430,440, and a pair of access transistors450,460aligned in a row.

In a central area of the unit cell, the load elements410,420and the drive transistors430,440are densely aggregated. The access transistors450,460are provided to one side of the drive transistors430,440. The gates of the access transistors450,460are connected to a wordline WL.

The gate electrodes411,431of the first lead element and the first drive transistor are connected in one body. A common gate electrode471is provided at one end to transfer a sync signal to the first load element410and the first drive transistor430upon receiving an electric signal from an upper line (not shown in the drawing). Of course, another common gate electrode (not shown in the drawing) for the second load element420and the second drive transistor440are provided to another unit cell.

One end of the common gate electrode pattern471of the first load element and the first drive transistor is overlapped with active areas, (i.e., source/drain regions), of the second load element420and the second drive transistor440. The common gate electrode pattern471can be formed of doped polysilicon.

A plurality of contact holes405for enabling electrical connections to upper lines are formed on the active areas and the gates such as the common gate electrodes and the like. The unit cell of the illustrated example SRAM device includes six and half (6.5) contact holes405. Specifically, there are two contact holes on the gate pattern of the transistors including the common gate electrode471, and four and one-half contact holes on the junction layers (source/drain regions) of the transistors. Thus, the total number (6.5) of contact holes in the illustrated example SRAM device is smaller than the total number (8.5) of contact holes in the prior art device described above.

Specifically, two contact holes are located on the gate pattern including the common gate electrode in both the example SRAM device ofFIG. 4and the prior art device described above. However, the example SRAM devices ofFIG. 4has four and one-half contact holes on the junction layers of the transistors, whereas the prior art SRAM device described above has six and one-half contact holes.

The reason why the number of contact holes on the junction layers in the is reduced by two in the example device ofFIG. 4as compared to the prior art device described inFIGS. 1-3will now be explained.

First, in the prior art, the contact holes are provided for electrical connections to the upper line of the junction layers of the first load element210, the common gate electrode271, and the first drive transistor230aligned on the same line. However, in the example device ofFIG. 4, one end of the common gate electrode pattern is overlapped with the junction layers of the second load element420and the second drive transistor440. Consequently, one contact hole is formed for the electrical connection to the upper line on one prescribed portion of the common gate electrode pattern. In other words, since the common gate electrode pattern ofFIG. 4overlaps with the second load element and the second drive transistor, only one contact (and, thus, one contact hole) is needed.

FIG. 5is a cross-sectional diagram of the example SRAM device unit cell ofFIG. 4taken along cutting line B-B′ ofFIG. 4. Referring toFIG. 5, a device isolation layer402is provided in a field area by STI (shallow trench isolation) or LOCOS (local oxidation of silicon) to define active areas in a semiconductor substrate401.

Gate electrodes421,441of the second load element and the second drive transistor are respectively formed on the active areas isolated by the device isolation layer402. Junction layers, (i.e., source/drain regions S/D), are formed in the substrate on opposite sides of the gate electrodes421,441.

A common gate electrode pattern471is formed on the substrate401above the device isolation layer402and portions of the junction layers of the second load element and the second drive transistor. The common gate electrode pattern471can be formed of doped polysilicon.

A salicide (self-aligned silicide) layer403is formed on the common gate electrode pattern411and the junction layers D of the second load element and the second drive transistor. In the illustrated example, the salicide layer403is formed of Ti-silicide, Co-silicide, Mo-silicide, or the like.

An insulating interlayer404is formed on the substrate401including on the salicide layer403.

A contact hole405is formed in the insulating interlayer404to expose the salicide layer403. A metal layer fills the contact hole405to form a conductive plug406. An upper line formed, for example, of Al, Cu, or the like, is formed on the insulating interlayer404and on the plug406. The contact hole405may be formed on any portion of the salicide layer403as long as the salicide layer403is exposed.

An example method of fabricating the above-described SRAM device unit cell will now be explained.FIGS. 6A to 6Dare cross-sectional views taken along cutting line B-B′ inFIG. 4and illustrate the method of fabricating the SRAM device at various points in time.

Referring toFIG. 6A, a device isolation layer402is formed in a field area of the semiconductor substrate401by STI (shallow trench isolation) or LOCOS (local oxidation of silicon) to define active areas in the semiconductor substrate401.

An oxide layer (not shown in the drawing) is grown on the active areas of the semiconductor substrate401by thermal oxidation to form a gate oxide layer (not shown in the drawing).

A conductor layer for forming gate electrodes is deposited on the oxide layer. In the illustrated example, the conductor layer is formed of heavily doped polysilicon.

The conductor layer and the oxide layer are selectively patterned to form a gate electrode421of a second load element, a common gate electrode471, and a gate electrode441of a second drive transistor.

Referring toFIG. 6B, heavy ion implantation is performed on the substrate401. Annealing is then performed on the substrate401to form junction layers, (i.e., sources S and drains D) in the active areas on opposite sides of the gate electrodes421,441.

Spacers may be formed on the sidewalls of the gate electrodes421,441prior to forming the sources S and drains D. Further, LDD (lightly doped drain) regions can be formed in the active areas on opposite sides of the gate electrodes421,441by light ion implantation.

After forming the junction layers (i.e., sources and drains), a low specific-resistance, high-melting-point metal layer is formed on the illustrated substrate401and on the gate electrode pattern471using Ti, Co, Ni, or the like.

Subsequently, annealing is performed on the substrate in an ambience of inert gas such as N2, He, or Ar by RTP (rapid thermal processing) or using a furnace. Accordingly, the high-melting-point metal layer on the gate electrodes and junction layers reacts with the silicon of the semiconductor substrate and the gate electrodes to turn into a silicide layer. In the illustrated example, the portions of the high-melting-point metal layer which fail to react with silicon are removed. After those portions of the high-melting-point metal layer have been removed, a salicide layer403is formed.

Alternatively, as shown inFIG. 6B, the salicide layer403, can be selectively formed on only the common gate electrode pattern471and the junction layers.

Referring toFIG. 6C, an insulating interlayer404is formed on the substrate401and on the salicide layer403. In the illustrated example, the insulating interlayer404is formed of oxide such as BPSG (borophosphorous silicate glass) or the like.

A prescribed portion of the insulating interlayer404is then etched to form a contact hole405. In the illustrated example, the contact hole405is formed to expose a portion of the salicide layer403. Dotted lines in the drawing indicate alternate contact holes405that can be formed on the salicide layer403.

Referring toFIG. 6D, the contact hole405is filled with a conductor metal layer to form a conductive plug406.

Subsequently, an upper line (not shown in the drawing) is formed on the insulating interlayer404in contact with the plug406.

Alternatively, the plug406and the upper line can be formed by a damascene process.

In the above-described SRAM device, the common gate electrode pattern471is formed on the area including: (a) the junction layer of the second load element and (b) the junction layer of the second drive transistor, and the salicide layer403is formed on the common gate electrode471and the corresponding junction layers.

The contact hole405exposing a portion of the salicide layer403can function as the contact holes for the junction layer of the second load element, for the junction layer of the second drive transistor, and for the common gate electrode of the prior art. Therefore, the example device ofFIG. 6Demploys only one contact hole instead of the three contact holes in the prior art. As a result, the above disclosed method can achieve a simplified process and a device size reduction by providing one contact hole for electrical connections with an upper line of a load element, a drive transistor, and a common gate electrode.

From the foregoing, persons of ordinary skill in the art will appreciate that SRAM devices and methods of fabricating the same have been disclosed, in which a process margin and the high degree of device integration are enhanced by reducing the number of contact holes in the SRAM device unit cell using local interconnections.

A disclosed example SRAM device includes first and second load elements; first and second drive transistors; a common gate electrode connected in one body to a gate electrode of the first load element and a gate electrode of the first drive transistor to apply a sync signal to the gate electrodes, the common gate electrode being overlapped with a junction layer of the second load element and a junction layer region of the second drive transistor, the common gate electrode being electrically connected to an upper line via one contact hole filled with a plug.

Preferably, the SRAM device further includes a silicide layer on the junction layer of the second load element, the junction layer region of the second drive transistor, and the common gate electrode.

More preferably, the contact hole is formed to expose a portion of the silicide layer.

A disclosed example method of fabricating an SRAM device having first and second load elements and first and second drive transistors, comprises: forming a device isolation layer on a semiconductor substrate to define active areas therein; forming gate electrodes of the second load element and the second drive transistor on the active areas isolated by the device isolation layer; forming a common gate electrode of the first load element and the first drive transistor on prescribed portions of the active areas and the device isolation layer; forming source/drain regions on opposite sides of each of the gate electrodes of the second load element and the second drive transistor; forming an insulating interlayer on the substrate including the gate electrodes and the common gate electrode; forming a contact hole in the insulating interlayer to expose a portion of the common gate electrode, and forming a plug filing the contact hole.

Preferably, the method further includes forming a silicide layer on the source/drain regions and the common gate electrode prior to forming the insulating layer.

Preferably, the contact hole is formed to expose a portion of the silicide layer.

A disclosed example SRAM device includes a semiconductor substrate having active areas defined by a device isolation layer; gate electrodes of a second load element and a second drive transistor on the active areas isolated by the device isolation layer; a common gate electrode of a first load element and a first drive transistor on portions of the active areas and the device isolation layer; source/drain regions on opposite sides of the gate electrodes of the second load element and the second drive transistor; an insulating interlayer on the gate electrodes and the common gate electrode; a contact hole in the insulating interlayer to expose a portion of the common gate electrode, and a plug in the contact hole.

Preferably, the SRAM device further includes a silicide layer on the source/drain regions and the common gate electrode.

Preferably, the contact hole is formed to expose a portion of the silicide layer.

From the foregoing, persons of ordinary skill in the art will readily appreciate that the disclosed methods achieve a simplified process and a device size reduction by providing one contact hole for electrical connections with an upper line of a load element, adrive transistor, and a common gate electrode.

It is noted that this patent claims priority from Korean Patent Application Serial Number P2003-0101390, which was filed on Dec. 31, 2003, and is hereby incorporated by reference in its entirety.