STACKED COMPLEMENTARY FIELD EFFECT TRANSISTORS

A CFET (complementary field effect transistor) structure including a first transistor disposed above a second transistor, a first source/drain region of the first transistor disposed above a second source/drain region of the second transistor, a first source/drain contact for the first source/drain region, and a second source drain contact for the second source drain region. The first source/drain contact is isolated from the second source/drain contact by an L-shaped isolation element including vertical and horizontal isolation elements.

BACKGROUND

The disclosure relates generally to stacked complementary field effect transistors (CFET). The disclosure relates particularly to stacked CFET having an upper FET contact passing through to a substrate, where the upper FET contact is isolated from the lower FET contact by an L-shaped combination of vertical and horizontal isolation elements.

Integrated circuit (IC) chips are formed on semiconductor wafers at increasingly smaller scale. In current technology nodes, transistor devices are constructed as three-dimensional (3D) field effect transistor (FET) structures. However, chipmakers face a myriad of challenges at 5 nm, 3 nm and beyond. Currently, chip scaling continues to slow as process complexities and costs escalate at each node.

Complex gate-all-around technology includes complementary FET (CFET) where nFET and pFET nanowires/nanosheets are vertically stacked on top of each other. Buried power rail architectures provide a possible path forward in downscaling chip designs.

SUMMARY

In one aspect a complementary field effect transistor (CFET) structure includes a first transistor disposed above a second transistor, a first source/drain region of the first transistor disposed above a second source/drain region of the second transistor, a first source/drain contact for the first source/drain region, and a second source drain contact for the second source drain region. The first source/drain contact is isolated from the second source/drain contact by an L-shaped combination of vertical and horizontal isolation elements.

In one aspect, a method of forming a complementary field effect transistor (CFET) device including forming stacked sets of field effect transistor channel elements, forming first source/drain regions for a first transistor, forming a vertical isolation region for the first source/drain region, and forming second source/drain regions for a second transistor above the vertical isolation region.

In one aspect, a CFET structure (complementary field effect transistor) including a first transistor disposed above a second transistor, a first source/drain contact for the first transistor, and a second source drain contact for the second transistor. The first source/drain contact is isolated from the second source/drain contact by vertical and horizontal isolation elements.

DETAILED DESCRIPTION

It is to be understood that aspects of the present invention will be described in terms of a given illustrative architecture; however, other architectures, structures, substrate materials, process features and steps can be varied within the scope of aspects of the present invention.

Deposition processes for the metal liners and sacrificial materials include, e.g., chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or gas cluster ion beam (GCIB) deposition. CVD is a deposition process in which a deposited species is formed as a result of chemical reaction between gaseous reactants at greater than room temperature (e.g., from about 25° C. about 900° C.). The solid product of the reaction is deposited on the surface on which a film, coating, or layer of the solid product is to be formed. Variations of CVD processes include, but are not limited to, Atmospheric Pressure CVD (APCVD), Low Pressure CVD (LPCVD), Plasma Enhanced CVD (PECVD), and Metal-Organic CVD (MOCVD) and combinations thereof may also be employed. In alternative embodiments that use PVD, a sputtering apparatus may include direct-current diode systems, radio frequency sputtering, magnetron sputtering, or ionized metal plasma sputtering. In alternative embodiments that use ALD, chemical precursors react with the surface of a material one at a time to deposit a thin film on the surface. In alternative embodiments that use GCIB deposition, a high-pressure gas is allowed to expand in a vacuum, subsequently condensing into clusters. The clusters can be ionized and directed onto a surface, providing a highly anisotropic deposition.

One of the processing complexities of CFETs that needs to be addressed at nodes beyond 5 nm is independently growing the nFET and pFET source/drain epitaxy while maintaining vertical integration and electrical disconnection. Using a conventional nanowire/nanosheet source/drain epitaxy process for CFETs forms superposed n-doped epitaxy and p-doped epitaxy, making it challenging to form independent upper and lower device source/drain region contacts to buried power rails and other buried connections having sufficient electrical isolation to prevent device shorting or other device reliability issues due to the close proximity of the upper and lower device source/drain (S/D) regions. Punching through the dielectric isolation layer separating upper and lower device source/drain epitaxial regions to form the buried power rail contact for the upper device tends to weaken the isolation layers effectiveness and gives rise to device electrical short circuits and other device reliability issues. Disclosed embodiments provide CFET structures and a method of forming CFETs with stacked S/D regions that maintain vertical integration and electrical disconnection of the nFET and pFET source/drain epitaxy while also having contacts passing through to buried power rail contact points.

Disclosed embodiments provide CFET structures including stacked and electrically isolated source/drain regions for CFET, where the formation of the via for the upper device contact is preceded by the formation of a vertical isolation element separating the epitaxial region of the lower device from the contact of the upper device. This process eliminated the need to punch through the upper/lower isolation layer with the inherent risk of weakening or otherwise reducing the effectiveness of the isolation layer between the upper and lower device epitaxial regions. This provides additional electrical isolation between the upper device contact and lower device contact while affording contacts from each device to buried power rails. Disclosed embodiments are described through examples embodying nanosheet field effect transistors. The invention should not be considered limited in any manner to the nanosheet structures of the examples.

Reference is now made to the figures. The figures provide schematic cross-sectional illustration of semiconductor devices at intermediate stages of fabrication, according to one or more embodiments of the invention. The figures provide a front cross-section (X) parallel to the nanosheet fins of the device, and side cross-section (Y), parallel to the gate structures of the device. The figures provide schematic representations of the devices of the invention and are not to be considered accurate or limiting with regards to device element scale.

FIG.1Aprovides a schematic plan view of a device100, according to an embodiment of the invention. As shown in the Figure, gate structures12, are disposed perpendicular to nanosheet stack14. Section lines X and Y indicate the viewpoints of the respective views ofFIGS.1B-17.

FIG.1Bprovides a schematic view of a device100according to an embodiment of the invention following the deposition, patterning, and selective removal of material leaving a stack of layers for the formation of nanosheet CFET devices. In an embodiment, the stack includes alternating layers of epitaxially grown silicon germanium (SiGe)140,150, and silicon130. Other materials having similar properties may be used in place of the SiGe and Si.

The terms “epitaxially growing and/or depositing” and “epitaxially grown and/or deposited” mean the growth of a semiconductor material on a deposition surface of a semiconductor material, in which the semiconductor material being grown has the same crystalline characteristics as the semiconductor material of the deposition surface. In an epitaxial deposition process, the chemical reactants provided by the source gases are controlled and the system parameters are set so that the depositing atoms arrive at the deposition surface of the semiconductor substrate with sufficient energy to move around on the surface and orient themselves to the crystal arrangement of the atoms of the deposition surface. Therefore, an epitaxial semiconductor material has the same crystalline characteristics as the deposition surface on which it is formed.

The nanosheet stack includes a bottom-most layer of a first semiconductor material, such as SiGe and a top-most layer of a second semiconductor material, such as Si. The nanosheet stack is depicted with ten layers (three SiGe layers and two Si layers forming a lower device, two SiGe layers and two Si layers forming an upper device, and a high Ge concertation, e.g., 50%-70% Ge, SiGe layer150, separating the upper and lower devices), however any number and combinations of layers can be used so long as the layers alternate between SiGe and Si to form lower and upper devices and include a high Ge concentration SiGe layer separating the lower and upper devices. The nanosheet stack is depicted with the layers being in the form of nanosheets, however the width of any given nanosheet layer can be varied so as to result in the form of a nanowire, a nanoellipse, a nanorod, etc. SiGe layers140,150, can be composed of, for instance, SiGe20-60, examples thereof including, but not limited to SiGe20, SiGe25, SiGe30. . . SiGe65.

Substrate110can be composed of any currently known or later developed semiconductor material, which may include without limitation, silicon, germanium, silicon carbide, and those consisting essentially of one or more III-V compound semiconductors having a composition defined by the formula AlX1GaX2InX3AsY1PY2NY3SbY4, where X1, X2, X3, Y1, Y2, Y3, and Y4 represent relative proportions, each greater than or equal to zero and X1+X2+X3+Y1+Y2+Y3+Y4=1 (1 being the total relative mole quantity). Other suitable substrates include II-VI compound semiconductors having a composition ZnA1CdA2SeB1TeB2, where A1, A2, B1, and B2 are relative proportions each greater than or equal to zero and A1+A2+B1+B2=1 (1 being a total mole quantity). An insulating layer120may be present on substrate110and, if present, is located between substrate110and the nanosheet stack. Insulating layer120can be, for example, a buried oxide layer (typically SiO2) or a bottom dielectric isolation layer formed early in the process (typically SiN, SiBCN, SiOCN, SiOC, or any combination of low-k materials). In an embodiment, the insulating layer120further comprises one or more buried power rails (not shown) or other contacts associated with device elements formed in lower layers of the device.

In an embodiment, each sacrificial semiconductor material layer140and150, is composed of a first semiconductor material which differs in composition from at least an upper portion of the semiconductor substrate110. In one embodiment, the upper portion of the semiconductor substrate110is composed of silicon, while each sacrificial semiconductor material layers140and150is composed of a silicon germanium alloy. In such an embodiment, the SiGe alloy that provides each sacrificial semiconductor material layer150has a germanium content that is greater than 50 atomic percent germanium. In one example, the SiGe alloy that provides each sacrificial semiconductor material layer150has a germanium content from 50 atomic percent germanium to 70 atomic percent germanium. In such an embodiment, the SiGe alloy that provides each sacrificial semiconductor material layer140has a germanium content that is less than 50 atomic percent germanium. In one example, the SiGe alloy that provides each sacrificial semiconductor material layer140has a germanium content from 20 atomic percent germanium to 40 atomic percent germanium. The first semiconductor material that provides each sacrificial semiconductor material layers140and150can be formed utilizing an epitaxial growth (or deposition process).

Each semiconductor channel material layer130, is composed of a second semiconductor material that has a different etch rate than the first semiconductor material of the sacrificial semiconductor material layers140and150and is also resistant to Ge condensation. The second semiconductor material of each semiconductor channel material layer130, may be the same as, or different from, the semiconductor material of at least the upper portion of the semiconductor substrate110. The second semiconductor material can be a SiGe alloy provided that the SiGe alloy has a germanium content that is less than 50 atomic percent germanium, and that the first semiconductor material is different from the second semiconductor material.

In one example, at least the upper portion of the semiconductor substrate110and each semiconductor channel material layer130is composed of Si or a III-V compound semiconductor, while each sacrificial semiconductor material layer140,150is composed of a silicon germanium alloy. The second semiconductor material of each semiconductor channel material layer130, can be formed utilizing an epitaxial growth (or deposition process).

Following deposition of the stack of layers130,140, and150, across the surface of the device die, the layers are patterned using a process such as lithographic masking, and selectively etched, yielding a pattern of device fins including stacks of upper and lower device nanosheets separated by sacrificial layers of semiconductor materials. Such stacks define the active regions of the devices.

FIG.2illustrates device100following the forming at least one dummy gate structure on the nanosheet stack. Three dummy gates are shown however any number of gates can be formed. Dummy gate structures can be formed by depositing a dummy gate material210over the nanosheet stack. The dummy gate material can be, for example, a thin layer of oxide, followed by polycrystalline silicon, amorphous silicon or microcrystal silicon. After that, a hardmask layer220is deposited over the dummy gate, followed by lithographic patterning, masking, and etching processes yielding the dummy gate fins of the Figure.

In an embodiment, hardmask220includes a nitride, oxide, an oxide-nitride bilayer, or another suitable material. In some embodiments, the hardmask220may include an oxide such as silicon oxide (SiO), a nitride such as silicon nitride (SiN), an oxynitride such as silicon oxynitride (SiON), combinations thereof, etc. In some embodiments, the hardmask220is a silicon nitride such as Si3N4.

FIG.3illustrates device100following selective removal of sacrificial layer150separating the upper and lower FET devices of the CFET. In an embodiment, the high Ge concentration SiGe of layer150may be selectively etched away without removal of sacrificial layers140, or channel layers130, due to the higher concentration of Ge of sacrificial layer150compared to sacrificial layers140, or channel layers130.

FIG.4illustrates device100following conformal deposition and selective etching of spacer materials to fill the void left by removal of layer150. Spacer material410further forms sidewall spacers along the sidewalls of dummy gate structure210, hardmask220, and sidewall of the nanosheet stack at S/D epi region. In an embodiment, spacer material410may be the same material as hardmask220, or may be different materials and may be comprised of any one or more of a variety of different insulative materials, such as Si3N4, SiBCN, SiNC, SiN, SiCO, SiO2, SiNOC, etc. In this embodiment, after conformal deposition, selective etching, such as anisotropic reactive ion etching, removes spacer material410from horizontal surfaces of the intermediate stage of the device100.

FIG.5illustrates device100after selective removal of spacer sidewall materials410from the vertical surfaces of the stack of nanosheets130-140. In an embodiment, anisotropic etching is used to selectively remove the vertical sidewall spacers from the nanosheet stacks. In an embodiment, following partial removal of spacer material410from the vertical surfaces of hardmask220, formation of a protective cap510, through deposition of a material such as SiC, or SiO2, upon the exposed vertical surfaces of hardmask220, provides protection against excessive removal of spacer materials410from the dummy gate210and hardmask220.

In an embodiment, formation of protective cap510includes: depositing a sacrificial material, such as OPL, over the wafer, followed by etching back the OPL to reveal the top portion of the gate spacer410, at sidewall of the hardmask220, while spacers at sidewalls of the nanosheet stack at S/D regions are still fully covered by OPL. After that, the exposed spacer410is selectively removed, followed by deposition of protective cap510, and anisotropic etching back. Removal of the sacrificial material (OPL) occurs, e.g., through an N2/H2 ash process. Finally, an anisotropic spacer etch process can be done to etch down the sidewall spacer at the nanosheet stack at S/D regions without pulling down the spacer410at gate sidewall which is under protective cap510.

FIG.6illustrates device100following recessing the nanosheet stack layers130,140, and spacer layer410, from between adjacent dummy gate structures, to form the S/D cavities for CFET devices.FIG.6further illustrates device100following formation of inner spacers between nanosheets of the respective FET devices. Portions of nanosheet stack layers130,140, and410, which are not underneath gate spacers410, and not underneath dummy gate210, are removed through etching. Etching generally refers to the removal of material from a substrate (or structures formed on the substrate) and is often performed with a mask in place so that material may selectively be removed from certain areas of the substrate, while leaving the material unaffected, in other areas of the substrate.

There are generally two categories of etching, (i) wet etch and (ii) dry etch. Wet etch is performed with a solvent (such as an acid) which may be chosen for its ability to selectively dissolve a given material (such as oxide), while, leaving another material (such as polysilicon) relatively intact. This ability to selectively etch given materials is fundamental to many semiconductor fabrication processes. A wet etch will generally etch a homogeneous material (e.g., oxide) isotropically, but a wet etch may also etch single-crystal materials (e.g. silicon wafers) anisotropically. Dry etch may be performed using a plasma. Plasma systems can operate in several modes by adjusting the parameters of the plasma. Ordinary plasma etching produces energetic free radicals, neutrally charged, that react at the surface of the wafer. Since neutral particles attack the wafer from all angles, this process is isotropic. Ion milling, or sputter etching, bombards the wafer with energetic ions of noble gases which approach the wafer approximately from one direction, and therefore this process is highly anisotropic. Reactive-ion etching (RIE) operates under conditions intermediate between sputter and plasma etching.

After generally etching the nanosheet stack between the dummy gate structures to the upper surface of the insulating layer120, a selective etching of SiGe layers140of the nanosheet stack removes portions which are underneath gate spacers410. Inner spacers610are then formed in etched-away portions, and thus are located under gate spacers410. Inner spacers610can be composed of any suitable dielectric material, for example Si3N4, SiBCN, SiNC, SiN, SiCO, SiO2, SiNOC, etc. The inner spacers are formed by a conformal dielectric liner deposition followed by isotropic etching back, so dielectric liner is removed everywhere except the regions pinched-off in those under spacer cavities.

FIG.7illustrates device100following epitaxial growth of source/drain regions710, for the lower FET device of the CFET. In an embodiment, pairs of epitaxial source/drain regions are formed on opposing sides of nanosheet stacks and dummy gate structures. In an embodiment, boron doped SiGe (SiGe:B) is epitaxially grown from exposed semiconductor surfaces (layer130). In an embodiment, deposition of a sacrificial material, such as OPL, covers the bottom nanosheet channel130sidewalls. A sacrificial spacer, such as a thin SiO2 or SiN, then covers the top nanosheet channel130sidewalls. The sacrificial material, such as OPL, can be removed by N2/H2 ash, followed by bottom S/D epitaxial710growth. After that, the sacrificial spacer can be removed from the top nanosheet channel130sidewalls. Growth of bottom S/D regions710includes overgrowth of the regions followed by recessing, patterning and selectively etching away unwanted epitaxial growth, leaving the final desired S/D region elements.

In the present embodiments, the source/drain regions710may be doped in situ by adding one or more dopant species to the epitaxial material. The dopant used will depend on the type of FET being formed, whether p-type or n-type. As used herein, “p-type” refers to the addition of impurities to an intrinsic semiconductor that creates deficiencies of valence electrons. In a silicon-containing semiconductor, examples of p-type dopants, i.e., impurities, include but are not limited to: boron, aluminum, gallium and indium. As used herein, “n-type” refers to the addition of impurities that contributes free electrons to an intrinsic semiconductor. In a silicon containing substrate, examples of n-type dopants, i.e., impurities, include but are not limited to antimony, arsenic and phosphorous. In an embodiment, the upper S/D regions of the device comprise n-type material and the lower regions comprise p-type materials. In an embodiment, the upper S/D regions comprise p-type materials and the lower regions comprise n-type materials.

FIG.8illustrates device100following deposition, and recess of a sacrificial spacer layer810, such as TiOx, (TiO2) around lower source/drains710. This can be achieved by a conformal deposition of sacrificial spacer810to pinch-off the gate-to-gate space or just overfill the sacrificial spacer material then followed by a CMP to a desired upper surface height for the sacrificial layer810.

FIG.9illustrates device100following deposition, CMP and recess of isolating layer910above sacrificial layer810. In an embodiment, isolation layer910constitutes a material such as SiO2, SiN, SiOC, and combinations of these.

FIG.10illustrates device100following selective masking of isolating layer910and sacrificial layer810with OPL1010and the subsequent removal of isolating layer910and sacrificial material810disposed to the left of lower S/D region710in cross-sectional view Y. OPL1010is subsequently removed through an ashing process.

FIG.11illustrates device100following deposition, CMP and recess of vertical isolating layer1110adjacent to sacrificial layer810and lower device S/D region710. In an embodiment, isolation layer1110constitutes a material such as SiO2, SiN, SiOC, and combinations of these, similar or identical to the materials used in forming isolating layer910. In an embodiment, this material is deposited upon the exposed surfaces of the device and selectively etched from all but the vertical surface of sacrificial material layer810, and isolation layer910.

FIG.12illustrates device100following deposition, CMP and recess of sacrificial material layer1210adjacent to vertical isolation layer1110. In an embodiment, a material such as that used for sacrificial material layer810, TiOx(TiO2), or similar is used.

FIG.13illustrates device100following epitaxial growth of pairs of upper device S/D regions1310. In an embodiment, epitaxial growth of phosphorous doped Si (Si:P) provides S/D regions for nFET devices of the CFET. S/D regions1310contact and are grown from nanosheet channel layers130of the upper FET device.

The disclosed example provides for the fabrication of a CFET device having an upper nFET and a lower pFET. In an embodiment, the CFET includes an upper pFET and a lower nFET. In this embodiment, the appropriate doping of the upper and lower S/D regions results in the desired pattern of nFET and pFET for the CFET device.

FIG.14illustrates device100following deposition and CMP of an interlayer dielectric (ILD) material1410, around and above the upper S/D epitaxy and the dummy gates and gate spacers410. The Figure illustrates the device after CMP removal of protective caps510, and hardmasks220from the dummy gate structures210, exposing the upper surfaces of dummy gate210materials. In an embodiment, ILD1410constitutes a material such as SiO2, SiN, SiOC, and combinations of these.

FIG.15illustrates device100following the removal of dummy gate210, sacrificial SiGe140, and formation of the high-k metal gate (HKMG) stack1510, and a protective gate dielectric cap1520. As shown in the Figure, a replacement metal gate structure has been formed in the void space created by removal of the dummy gate210, and sacrificial SiGe layers140. Gate structure1510includes gate dielectric and gate metal layers (not shown). The gate dielectric is generally a thin film and can be silicon oxide, silicon nitride, silicon oxynitride, boron nitride, SiOCN, SiBCN, SiOC, SiCN, high-k materials, or any combination of these materials. Examples of high-k materials include but are not limited to metal oxides such as hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. The high-k materials may further include dopants such as lanthanum, aluminum, magnesium. Gate dielectric can be deposited by CVD, ALD, or any other suitable technique. Metal gate can include any known metal gate material known to one skilled in the art, e.g., TiN, TiAl, TiC, TiAlC, tantalum (Ta) and tantalum nitride (TaN), W, Ru, Co, Al. Metal gate may be formed via known deposition techniques, such as atomic layer deposition, chemical vapor deposition, or physical vapor deposition. It should be appreciated that a chemical mechanical planarization (CMP) process can be applied to the top surface.

In an embodiment, the replacement metal gate includes work-function metal (WFM) layers, (e.g., titanium nitride, titanium aluminum nitride, titanium aluminum carbide, titanium aluminum carbon nitride, and tantalum nitride) and other appropriate metals and conducting metal layers (e.g., tungsten, cobalt, tantalum, aluminum, ruthenium, copper, metal carbides, and metal nitrides). After formation and CMP of the HKMG1510, the HKMG1510can be optionally recessed followed by a deposition and CMP of a gate dielectric cap material1520completes the replacement metal gate fabrication stage for the device.

FIG.16illustrates device100following the formation of contact vias1610from an upper ILD surface to the upper surface of sacrificial material layer810. The fabrication method utilizes selective etching, such as RIE in forming the via. The via exposes the sacrificial material layer810.

FIG.17illustrates device100following removal of ILD material1410from around upper device S/D epitaxy1310. As shown in cross-section Y of the Figure, the ILD material1410, has been removed, exposing upper device S/D region1310.

FIG.18illustrates device100following removal of the sacrificial material810from its position adjacent to lower device S/D regions710, as well as removal of sacrificial material1210. As shown in cross-section Y of the Figure, the sacrificial semiconductor materials810, and1210, have been removed, exposing vertical isolating layer1110, and isolating layer120. In this manner, formation of the contact trench for the upper device S/D region proceeds to the lower isolation layer120and contacts embedded therein, without the need for a potentially compromising punch through etching of isolation layer910between the upper and lower device S/D regions.

FIG.19illustrates device100following the deposition of a wraparound metal S/D contact1910in the S/D regions contact vias. In an embodiment, deposition of silicide liner such as Ti, Ni, Co, NiPt, followed by deposition of an adhesion metal liner, such as a thin layer of TiN, followed by deposition of a conductive metal such as Cu, Ag, Au, W, Co, Ru, or combinations thereof, forms the contact. The geometry of the contact reduces the contact resistance by increasing the silicide surface area between the contact and S/D epi with the S/D regions. As further shown in the Figure, contacts1910for the device S/D regions connect to buried power rails1920, disposed in isolating layer120through previously executed fabrication steps.

FIG.20depicts a fabrication process flowchart2000, according to an embodiment of the invention. As shown in flowchart2000, at block2010, nanosheet sets for the CFET devices are formed. Stacks of alternating nanosheet layers of differing semiconductor materials are epitaxially grown upon an underlying substrate, or upon an insulating layer disposed upon a substrate. The stacks include sacrificial layers and channel layers. The channel layers form the nanosheet channels of the upper and lower FETs of the CFET. The layers are patterned and etched to form fins upon the underlying substrate. Dummy gate structures including gate sidewall spacers are added atop and along the fins. The nanosheet layers are recessed to align with the dummy gate spacers and inner spacers between nanosheet channel layers are formed to isolate the gates from the S/D regions of the devices.

At block2020, S/D regions for the lower device are epitaxially grown upon the device in contact with the lower device nanosheet channel layers. The S/D regions are patterned and etched back to form the final lower device S/D regions in contact with the lower FET nanosheet channel layers. Prior to growing the lower S/D regions, the upper device semiconductor channels are shielded with a thin layer of sacrificial protective material thereby preventing epitaxial growth from the upper device semiconductor channels.

At block2030, a horizontal isolation layer is formed above the lower device S/D regions. This layer forms a portion of the eventual L-shaped isolation structure physically and electrically separating the upper device and lower device S/D contacts.

At block2040, a vertical isolation layer is formed adjacent to the lower S/D region and surrounding sacrificial material. Portions of the horizontal isolation layer and sacrificial layer are selectively etched away. The vertical isolation material is then conformally deposited and selectively etched leaving the vertical isolation element. The vertical isolation element is formed adjacent to the lower device S/D regions and the remaining sacrificial material layer.

The vertical isolation layer merges with the horizontal isolation layer above the lower device S/D region, forming an “L-shaped” isolation region between the upper and lower FET devices.

At block2050, upper device S/D regions are formed from the upper device semiconductor nanosheet channels and upon the horizontal isolation layer upper surface.

At block2060, the HKMG structure is formed as a replacement for the dummy gate structure between and adjacent to the upper and lower device S/D regions. In an embodiment, the dummy gate is removed, and a high-k layer is deposited followed by deposition of a work function metal and completed by deposition of a sacrificial protective cap upon the HKMG structure.

At block2070, independent source/drain contacts are formed for CFET device. Contact trenches are etched through protective dielectric material layers to expose the upper S/D regions and the sacrificial material disposed around the lower S/D regions of a first side of the devices. A first trench exposes the upper S/D region on one side of the devices, this trench extends through lower sacrificial material, exposing the upper surface of isolation layer120. A second trench exposes the sacrificial material adjacent to the lower S/D region on the same side of the devices. This sacrificial material is then removed exposing the lower S/D regions and the lower isolation layer. In an embodiment, a third common trench exposes the upper and lower S/D regions of the other side of the devices as well as the lower isolation layer. Contact metal is then disposed in the vias providing electrically independent contacts to each of the upper and lower S/D regions of the devices with buried contacts such as buried power rails for the devices.

The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and device fabrication steps according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more fabrication steps for manufacturing the specified device(s). In some alternative implementations, the functions noted in the blocks may occur out of the order noted in the Figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved.