Integrated circuit fuse with localized fusing point

An integrated circuit fuse includes a substantially bar-shaped central region and zones having electrical contacts. The central region includes a thinned zone forming a weak point facilitating fusing of the fuse by increasing the local current density as compared to standard fusing conditions. The thinned zone is preferably obtained by proximity optical effect between the fuse and adjacent dummy elements.

FIELD OF THE INVENTION
 The present invention relates to the field of integrated circuits, and,
 more particularly, to an integrated circuit fuse.
 BACKGROUND OF THE INVENTION
 Providing fuses in integrated circuits is a practice well-known to those
 skilled in the art, especially in the manufacture of MOS circuits. For
 example, it is standard practice to provide fuses to protect MOS
 transistor gates against the accumulation of electrostatic charges which
 appear during the manufacture of integrated circuits. These fuses are then
 disrupted or fused to release the gates of the transistors. As another
 example, providing redundant word lines or bit lines in large capacity
 memories also relies on the use of fuses. The defective or unnecessarily
 redundant lines are then isolated from the rest of the memory by fusing or
 disrupting the fuses. In general, integrated circuit fuses are designed to
 be disrupted by the application of a fusing voltage or current to enable
 the modification of the configuration of a circuit at a final stage of
 manufacture.
 A prior art fuse made by etching is of the type shown in FIG. 1. A fuse 1
 of this kind, with a very simple structure and a small space requirement,
 includes a small bar-shaped central region 2 that widens out at its ends
 to form two zones 3, 4 receiving a plurality of electrical contacts 5, 6.
 In general, as can be seen in FIG. 2 in a sectional view, the fuse 1 is
 buried in an integrated circuit 10 where it is sandwiched between a lower
 layer 11 and an upper layer 12 of oxide deposited on a silicon substrate
 13. The contacts 5, 6 take the form of metallized holes going through the
 oxide layer 12 to connect the zones 3, 4 to conductors 14, 15.
 Conventionally, the whole unit is made by the successive deposition of
 various layers of oxide, metal and/or polysilicon and by the etching of
 the layers by photolithography.
 In order that the current density in the fuse 1 and the efficiency of the
 fusing may be a maximum for a given fusing current, the width W of the
 central region 2 of the fuse is usually chosen to be equal to the
 technological minimum width W.sub.min permitted by the manufacturing
 technology of the integrated circuit 10. For example, at present, the
 technological minimum width W.sub.min of the MOS type integrated circuits
 is commonly about 0.25 micrometers with respect to the minimum width of a
 conductor, i.e., the minimum length of the gates of the MOS transistors.
 However, this precaution provides only a relative advantage, given that the
 technological minimum also determines the size of the other components
 present in the integrated circuit 10. This is particularly true with
 transistors, and their capacity to withstand high voltages or currents.
 Thus, in recent years, the reduction of the technological minimum width
 through the improvement of technologies has gone hand in hand with a
 reduction of the permissible fusing voltages and currents. For example,
 the maximum fusing voltages permitted in medium-scale integrated MOS
 circuits according to older technology were in the range of 5.5 to 6
 volts. For large-scale integrated circuits formed using current
 technology, the maximum fusing voltages are no more than 1.8 to 2 volts.
 Despite providing for a minimum width, a standard fuse does not, in
 statistical terms, provide a fusing efficiency equal to 100% under
 standard fusing conditions. In other words, when it is sought to
 simultaneously fuse or disrupt a set of fuses present in an integrated
 circuit by applying one or more fusing pulses of current or voltage, it
 frequently happens that non-disrupted fuses remain. These fuses have an
 electrical resistance which, although it is higher than their initial
 electrical resistance, cannot be compared to that of an open circuit. This
 drawback is reflected in the efficiency of manufacture of the integrated
 circuits, and becomes more of problem when several tens or even several
 hundreds of fuses are to be made in the same integrated circuit.
 The technological minimum width W.sub.min therefore, represents an obstacle
 in the search for a fuse having high fusing efficiency. It is well known
 in the field of photolithography that the technological minimum width
 W.sub.min is determined by various technological constraints. In
 particular, obtaining satisfactory reliability of the gates of the MOS
 transistors is determined by the technological minimum width W.sub.min.
 Furthermore, a phenomenon of diffraction and reflection of light during
 the isolation of the organic resin etching masks exists, and is known to
 those skilled in the art as the "proximity optical effect".
 Finally, another drawback of standard integrated circuit fuses is that they
 are not entirely reliable. A certain percentage of disrupted fuses have a
 tendency to regenerate for reasons as yet poorly explained. The
 regeneration of a fuse is expressed by the fact that its electrical
 insulation properties deteriorate, whereas they were initially
 satisfactory.
 SUMMARY OF THE INVENTION
 An object of the present invention is to provide an integrated circuit fuse
 capable of being more easily fused than a standard fuse when conducting an
 identical current.
 Another object of the present invention is to provide a fuse having a
 fusing efficiency greater than that of standard fuses along with improved
 reliability.
 Yet another object of the present invention is to provide an integrated
 circuit fuse having a width smaller than a technological minimum width,
 and a method for manufacturing such a fuse.
 These objects are achieved by providing an integrated circuit fuse
 including a substantially bar-shaped central region and zones including
 electrical contacts in which the central region has a thinned zone. A
 smaller width forms a weak point facilitating fusing of the fuse through
 an increase in the local current density in standard fusing conditions.
 The fuse is obtained by photolithography and includes at least one dummy
 element in the vicinity of the thinned zone. The thinning of the central
 region is obtained by optical proximity effect between at least one edge
 of the central region and one edge of the dummy element. Advantageously,
 the width of the thinned zone is smaller than a technological minimum
 width used for manufacturing the integrated circuit. The width of the
 central region outside the thinned zone is substantially equal to the
 technological minimum width.
 According to one embodiment, the thinned zone is substantially symmetrical
 with respect to the longitudinal axis of the central region, and is formed
 by two notches made in the edges of the central region.
 According to another embodiment, the fuse includes two dummy elements on
 each side of the thinned zone.
 According to yet another embodiment, the fuse is made out of polysilicon.
 According to another embodiment, the fuse includes oxide spacers that do
 not entirely overlap the edges of the thinned zone.
 According to another embodiment, the contacts are metallized holes going
 through an oxide layer covering the fuse to connect the zones of the fuse
 with the conductive elements.
 According to still yet another embodiment, the increase in the electrical
 resistance of the central region due to the thinned zone is negligible as
 compared with the total resistance of the fuse. The total resistance
 includes the resistance of access to the fuse. The access resistance
 includes the electrical resistance of conductive elements and the
 electrical resistance of the contacts.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
 FIG. 3 shows a top view of a fuse 20 according to the present invention. In
 its general shape, the fuse 20 has the appearance of the standard prior
 art fuse of FIG. 1. The fuse 20 thus includes a substantially bar-shaped
 central region 2. In this case, a length L is equal to three times its
 width W.sub.1 there for, and zones 3, 4 are respectively provided with
 contacts 5, 6. The fuse 20 is made by etching a thin layer of polysilicon,
 metal or alloy or is made by etching a thin layer formed by a stack of
 metals or alloys.
 According to the present invention, the central region 2 of the fuse 20 has
 a narrowed feature or thinned zone 21, with a width W.sub.2 therefor
 smaller than the average width W.sub.1 therefor of the central region. The
 width W.sub.2 therefor is, for example, equal to half the width W1 as
 shown in FIG. 3. The thinned zone 21 takes up a small part of the length L
 of the central region 2. For example, one-third of the length L is
 preferably positioned at mid-distance from the zones 3, 4.
 Advantageously, the thinned zone 21 has a high current density under
 standard conditions of fusing, e.g., for a given fusing current. This
 forms a weak point facilitating the fusing or disruption of the fuse. More
 particularly, the high concentration of current makes the fusing more
 quickly and more efficient. The fuse according to the present invention
 provides a higher fusing efficiency and a lower probability of
 regeneration than a standard fuse.
 The thinned zone 21 furthermore makes it possible to localize the breakdown
 point of the fuse and move it away from the zones 5, 6 where there is a
 larger quantity of conductive material. This feature of the invention is
 likely to contribute to obtaining a low probability of regeneration of the
 fuse and, therefore, to improving its reliability.
 Furthermore, the total electrical resistance Rt of the fuse is not
 significantly increased in comparison with a prior art fuse of the same
 size. That is, the same fusing current is obtained for a given fusing
 voltage, or vice versa. This advantage is based on the fact that the total
 resistance of the fuse is equal to the sum of the resistance of the
 central region 2, and a resistance of access to the fuse, which is not
 negligible. The total resistance of the fuse is primarily the measurable
 resistance from the external pads of an integrated circuit. As an example,
 the resistance of the central region of a fuse is conventionally about 1
 to 10 .OMEGA., depending on the shape of the fuse and the materials used.
 The access resistance, including the resistance of conductors leading to
 the fuse and the resistance of the contacts 5, 6, is about 11 .OMEGA..
 As shown in FIG. 4, the total electrical resistance Rt of the fuse 20 may
 be considered to be equal to the sum of the resistance values of five
 series-connected resistors Ra.sub.1, Ra.sub.2, R.sub.1, R.sub.2, R.sub.3
 crossed by a fusing current I.sub.0. The resistors R.sub.1, R.sub.3
 represent the resistance of the central region 2 on each side of the
 thinned zone 21 and, in this case, are substantially equal to the
 resistance R.sub.0 per unit of surface area of the material forming the
 fuse. The resistor R.sub.2 represents the resistance of the thinned zone
 21 and, in this case, it is substantially equal to 2R.sub.0. The resistors
 Ra.sub.1 and R.sub.2 represent the values of access resistance at the two
 ends of the fuse 20. The total resistance Rt of the fuse 20 is thus equal
 to:
EQU Ra.sub.1 +Ra.sub.2 +4R.sub.0,
 whereas the total resistance of a conventional fuse of the same shape and
 size is equal to:
EQU Ra.sub.1 +Ra.sub.2 +3R.sub.0.
 Since the resistance R.sub.0 is generally low as compared with the access
 resistance Ra, the ratio Ic/Vc between the fusing current Ic and the
 fusing voltage Vc is substantially not modified by providing the thinned
 zone 21. Furthermore, according to another feature of the invention, to
 reduce the width W.sub.2 of the thinned zone 21 below a technological
 minimum width W.sub.min takes advantage of the so-called proximity optical
 effect that is present when etching by photolithography. The way in which
 this phenomenon appears during an etching process will be discussed below.
 FIG. 5C is a partial view of an etching 30 with parallel edges having a
 width E.sub.1, made for example, in a polysilicon layer 31. FIG. 5A shows
 the initial pattern of this etching as designed by an integrated circuit
 designer. The references of FIG. 5C are preceded by the letter D in FIG.
 5A. In this example, it is assumed that the width DE.sub.1 of the etching
 D30 as drawn is chosen to be greater than a technological threshold
 SE.sub.min. This technological threshold represents the minimum space
 between two elements below which the proximity optical effect appears.
 The drawing step illustrated by FIG. 5A is followed by several standard
 steps, such as the making of an isolation mask for reproducing the initial
 pattern and the making of an etching mask. FIG. 5B shows the etching mask
 32 corresponding to the drawing of FIG. 5A. The mask 32 is obtained by
 depositing a layer of photosensitive resin on the polysilicon layer 31.
 This is followed by a step of isolating the resin by an isolation mask,
 and a step of removing the isolated resin by a solvent. Finally, the mask
 31 has an aperture 33 that reveals the polysilicon 31, whose width
 ME.sub.1 is equal to the width DE.sub.1 planned on the initial design.
 After the polysilicon etching step, which is generally a plasma etching
 step, the width E.sub.1 of the etched zone 30 (FIG. 5C) is, for its part,
 also equal to the planned width DE.sub.1. Typically, the etched zone shows
 the space between two lines of polysilicon.
 FIGS. 6A to 6C give a view, with the same references, of the same process
 steps. The planned width DE.sub.2 of the etching D30 is now chosen to be
 smaller than the technological threshold SE.sub.min. As can be seen in
 FIG. 6B, the result thereof is that the etching mask 32 has an aperture 33
 which is greater than planned. The width ME.sub.2 is greater than the
 width DE.sub.2 laid down in the drawing. Thus, in FIG. 6C, the etching 30
 also has a width E.sub.2 which is greater than that laid down in the
 design.
 As is well known to those skilled in the art, this increase in width is
 primarily due to the phenomena of refraction and reflection of light
 during the isolation of the etching mask and sets the limits of a given
 technology. Naturally, the proximity optical effect also appears when it
 is sought to obtain a narrow band of material by etching the surrounding
 material. This defines a technological threshold SW.sub.min in width of an
 element, below which the dimensions as laid down suffer from
 deterioration. Furthermore, in relation with other technological
 constraints, such as the reliability of the integrated circuits, the
 optical proximity effect also determines a technological minimum E.sub.min
 in etching width (minimum space between two elements), as well as a
 technological minimum width W.sub.min in the width of an element. The
 technological minimum W.sub.min, E.sub.min are generally smaller than the
 technological thresholds SW.sub.min, SE.sub.min and are obtained by design
 corrections directed at compensating for the proximity optical effect.
 Reference shall now be made to FIGS. 7 and 8 which illustrate a method
 according to the invention enabling the making of a fuse 20 with a thinned
 zone 21 having a width W.sub.2 smaller than the technological minimum
 width W.sub.min. FIG. 7 shows the drawing D20 of the fuse 20 according to
 the present invention and FIG. 8 shows the fuse 20 obtained after the
 etching of a layer of polysilicon, metal or alloy. The references of FIG.
 8 are preceded by the letter D in FIG. 7. According to the invention, the
 fuse D20 as drawn does not have a thin zone but, on each side of the
 central region D21, there are two dummy elements D22, D23 which are
 polygonal. Each dummy element D22, D23 has a respective edge D22-1, D23-1
 parallel to the central region D2 at a distance DE3 from this region. The
 distance DE.sub.3 is deliberately smaller than the technological threshold
 SE.sub.min described above. Furthermore, the width DW.sub.1 of the central
 region D2 is preferably chosen to obtain a fuse width equal to the
 technological minimum width W.sub.min.
 As can be seen in FIG. 8, the final result after etching is that the
 distance E.sub.3 between the edges 22-1, 23-1 of the dummy elements 22 and
 23 and the edges of the central region 2 is increased by the proximity
 optical effect so that a little material has been lost on the dummy
 elements 22, 23 and a little material on the edges of the central region 2
 facing the dummy elements. The removal of material from the edges of the
 central region 2 forms two symmetrical notches 21-1, 21-2 revealing the
 thinned zone 21 whose width W.sub.2 is smaller than the technological
 minimum width W.sub.min. By pushing back the boundaries imposed by the
 current technology, an even more appreciable increase is obtained in the
 density of the fusing current in the thinned zone and, therefore, the
 fusing efficiency and reliability of the fuse according to the invention.
 A description shall now be given with reference to FIG. 9 of another
 advantage of this embodiment of the invention, appearing when the fuse is
 made out of a plasma-etched polysilicon layer. It will be recalled that
 polysilicon, even when doped, has low conductivity so that it is necessary
 to provide for a step of silicide treatment in the presence of a metal
 such as titanium Ti, cobalt Co, tungsten W and tantalum Ta, etc. This step
 enables the deposition on the surface of polysilicon of a layer of
 silicide, for example, titanium silicide TiSi2, which greatly reduces the
 electrical resistivity of polysilicon.
 FIG. 9 gives a partial view of an integrated circuit 40 including the fuse
 40, seen in the sectional view along the axis BB' shown in FIG. 8. The
 thicknesses of the various elements are not shown to scale. The integrated
 circuit 40 conventionally includes a substrate 41, a first thick oxide
 layer 42, for example, with a thickness of 0.35 micrometers, an etched
 polysilicon layer forming the fuse 20, for example, with a thickness of
 0.2 micrometers, an etched oxide layer 43, a second layer 44 of thick
 oxide and a metallization layer 45 in which conductors are etched. The
 contacts 5, 6 represented by dashes are conventionally metallized holes
 connecting the fuse to the layer metallization 45 or any other
 metallization planned at a higher level. The etched oxide 43 forms oxide
 spacers 43-1, 43-2 covering the edges of the central region 2 and the thin
 part 21. Finally, the fuse 20 is covered with a silicide layer 46 enabling
 its electrical resistance to be reduced, as already indicated.
 As is well known to those skilled in the art, the spacers 43-1, 43-2 are
 not necessary for the making of the fuse and are provided by the fact that
 the fuse is made jointly with other elements of the integrated circuit 40,
 for example, with MOS transistors (not shown). However, the presence of
 the spacers 43-1, 43-2 on the edges of the fuse 20 has the negative effect
 of limiting the size of the silicide layer 46.
 Here, the advantage of the invention lies in the fact that the efficiency
 of the process of etching the oxide 43 is improved in the zones where the
 central region 2 is in the vicinity of the dummy elements 22, 23. This
 phenomenon, well known to those skilled in the art, is called the
 "localized charge effect." The result appears clearly when the spacers
 43-1, 43-2 present on the edges of the thinned zone 21 are compared, for
 example, with spacers 43-3, 43-4 present on the external edges 22-2, 23-2
 of the dummy elements 22, 23. It can be seen that the spacers 43-3, 43-4
 almost entirely cover the external edges of the dummy elements 22, 23,
 whereas the spacers 43-1, 43-2 only partially cover the edges of the
 thinned zone 21.
 Ultimately, the presence of the dummy elements 22, 23 assists the etching
 of the oxide 43 on the edges of the fuse and makes it possible to obtain a
 silicide layer 46 that is more extensive. Since the silicide layer 46 is
 wider, the electrical resistance of the fuse is smaller than that of a
 standard fuse of the same size. This advantage improves the
 current/voltage ratio of the fuse and is added to the other advantages of
 the invention to give high fusing efficiency and high reliability.
 The present invention can have various alternatives and embodiments,
 especially with regard to the size and shape of the fuse, the ratio
 between the length L and the width W.sub.1 of the central region 2, the
 positioning of the thinned zone 21, the width W.sub.2 of the thinned zone
 21, the layout of the fuse within an integrated circuit, and the materials
 and the technologies used for making the fuse, etc.
 In general, the present invention makes it possible, for an identical
 amount of space occupied by a fuse and under standard conditions of
 fusing, to obtain a higher current density and a greater fusing energy and
 also makes it possible to control the localization of the breakdown point
 of a fuse. The dummy elements arranged as described above is a
 complementary aspect of the invention making it possible to go beyond the
 limits dictated by the manufacturing technology. In the prior art, a
 polysilicon fuse according to the invention may have a thickness of 0.2
 micrometers for an average width of about 0.25 micrometers, and a fuse
 made of metal may have a thickness of 0.5 micrometers for a width of 0.4
 micrometers.