Optimizing grouping of instructions

Embodiments include optimizing the grouping of instructions in a microprocessor. Aspects include receiving a first clump of instructions from a streaming buffer, pre-decoding each of instructions for select information and sending the instructions to an instruction queue. Aspects further include storing initial grouping information for the instructions in a local register, wherein the initial grouping information is based on the select information. Aspects further include updating the initial group information stored in the local register when additional pre-decode information becomes available and grouping the instructions that are ready to be dispatched into a dispatch group based on the grouping information stored in the local register. Aspects further include dispatching the dispatch group to an issue unit.

BACKGROUND

The present invention generally relates to microprocessors, and more specifically, to optimizing the grouping of instructions in a microprocessor.

In modern microprocessors, all instructions need information to be decoded and relayed to the execution units. Throughout this process there are many areas that can cause performance degradation. One such area of performance loss is the grouping stage. Grouping is the process of determining which instructions can be dispatched together. In general, the overall performance of a microprocessor is directly impacted by the number of instructions that can be grouped together and dispatched on a given cycle. As a result, generating and implementing effective grouping rules as quickly and efficiently as possible is desired.

SUMMARY

Embodiments include a computer system for optimizing the grouping of instructions in a microprocessor. The computer system includes a server having a processor, the processor configured to perform a method. The method includes receiving a first clump having a plurality of instructions from a streaming buffer, pre-decoding each of the plurality of instructions in the first clump for a select information and sending the plurality of instructions to an instruction queue and storing one or more of the plurality of instructions in a local register and storing an initial grouping information for each of the plurality of instructions in a local register, wherein the initial grouping information is based on the select information. Based on receiving an indication from the instruction queue that one or more of the plurality of instructions is ready to be dispatched from the instruction queue, the method includes determining if an additional pre-decode information is available. Based on determining that the additional pre-decode information is not available, the method includes grouping the one or more of the plurality of instructions that are ready to be dispatched from the instruction queue into a dispatch group based on the initial grouping information stored in the local register. Based on determining that the additional pre-decode information is available, the method includes updating the initial group information stored in the local register based on the additional pre-decode information and grouping the one or more of the plurality of instructions that are ready to be dispatched from the instruction queue into the dispatch group based on the updated grouping information stored in the local register. The method further includes dispatching the dispatch group to an issue unit.

Embodiments also include a computer program product for optimizing the grouping of instructions in a microprocessor, the computer program product including a computer readable storage medium having computer readable program code embodied therewith, the computer readable program code configured to perform a method. The method includes receiving a first clump having a plurality of instructions from a streaming buffer, pre-decoding each of the plurality of instructions in the first clump for a select information and sending the plurality of instructions to an instruction queue and storing one or more of the plurality of instructions in a local register and storing an initial grouping information for each of the plurality of instructions in a local register, wherein the initial grouping information is based on the select information. Based on receiving an indication from the instruction queue that one or more of the plurality of instructions is ready to be dispatched from the instruction queue, the method includes determining if an additional pre-decode information is available. Based on determining that the additional pre-decode information is not available, the method includes grouping the one or more of the plurality of instructions that are ready to be dispatched from the instruction queue into a dispatch group based on the initial grouping information stored in the local register. Based on determining that the additional pre-decode information is available, the method includes updating the initial group information stored in the local register based on the additional pre-decode information and grouping the one or more of the plurality of instructions that are ready to be dispatched from the instruction queue into the dispatch group based on the updated grouping information stored in the local register. The method further includes dispatching the dispatch group to an issue unit.

Embodiments further include a method for optimizing the grouping of instructions in a microprocessor. The method includes receiving a first clump having a plurality of instructions from a streaming buffer, pre-decoding each of the plurality of instructions in the first clump for a select information and sending the plurality of instructions to an instruction queue and storing one or more of the plurality of instructions in a local register and storing an initial grouping information for each of the plurality of instructions in a local register, wherein the initial grouping information is based on the select information. Based on receiving an indication from the instruction queue that one or more of the plurality of instructions is ready to be dispatched from the instruction queue, the method includes determining if an additional pre-decode information is available. Based on determining that the additional pre-decode information is not available, the method includes grouping the one or more of the plurality of instructions that are ready to be dispatched from the instruction queue into a dispatch group based on the initial grouping information stored in the local register. Based on determining that the additional pre-decode information is available, the method includes updating the initial group information stored in the local register based on the additional pre-decode information and grouping the one or more of the plurality of instructions that are ready to be dispatched from the instruction queue into the dispatch group based on the updated grouping information stored in the local register. The method further includes dispatching the dispatch group to an issue unit.

DETAILED DESCRIPTION

Methods and systems for optimizing the grouping of instructions in a microprocessor are provided. In exemplary embodiments, raw data is received by a streaming buffer which parses the raw data into clumps of instructions. These clumps of instructions are then sent to both an instruction queue and to a pre-decode unit, which determines which instructions should be grouped before being dispatched to an issue unit of the microprocessor. In one embodiment, the clumps of instructions include up to six instructions and each dispatch group includes up to three instructions. In exemplary embodiments, the grouping of the instructions is preformed across the clumps of instructions provided by the streaming buffer. In other words, a dispatch group may include instructions that were received in different clumps of instructions.

In an embodiment with a maximum group size of three instructions, the pre-decode unit is configured to look ahead at the next two instructions and to determine if it is possible to group them together. However, it is possible that two or three instructions that can be grouped together will not be predecoded during the same cycle. For example, the instructions may be received from the streaming buffer in separate clumps. Accordingly, the pre-decode unit may make initial grouping decisions based on conservative assumptions and may revise these grouping decisions when additional instructions are received.

FIG. 1illustrates a block diagram of a computer system100for use in practicing the teachings herein. The methods described herein can be implemented in hardware, software (e.g., firmware), or a combination thereof. In an exemplary embodiment, the methods described herein are implemented in hardware, and may be part of the microprocessor of a special or general-purpose digital computer, such as a personal computer, workstation, minicomputer, or mainframe computer. The computer system100therefore includes general-purpose computer101.

In an exemplary embodiment, in terms of hardware architecture, as shown inFIG. 1, the computer101includes a processor105, memory110coupled to a memory controller115, and one or more input and/or output (I/O) devices140,145(or peripherals) that are communicatively coupled via a local input/output controller135. The input/output controller135can be, for example but not limited to, one or more buses or other wired or wireless connections, as is known in the art. The input/output controller135may have additional elements, which are omitted for simplicity, such as controllers, buffers (caches), drivers, repeaters, and receivers, to enable communications. Further, the local interface may include address, control, and/or data connections to enable appropriate communications among the aforementioned components.

The processor105is a hardware device for executing hardware instructions or software, particularly that stored in memory110. The processor105can be any custom made or commercially available processor, a central processing unit (CPU), an auxiliary processor among several processors associated with the computer101, a semiconductor based microprocessor (in the form of a microchip or chip set), a macroprocessor, or generally any device for executing instructions. The processor105includes a cache170, which may include, but is not limited to, an instruction cache to speed up executable instruction fetch, a data cache to speed up virtual-to-physical address translation for both executable instructions and data. The cache170may be organized as a hierarchy of more cache levels (L1, L2, etc.).

The instructions in memory110may include one or more separate programs, each of which comprises an ordered listing of executable instructions for implementing logical functions. In the example ofFIG. 1, the instructions in the memory110include a suitable operating system (OS)111. The operating system111essentially controls the execution of other computer programs and provides scheduling, input-output control, file and data management, memory management, and communication control and related services.

In an exemplary embodiment, a conventional keyboard150and mouse155can be coupled to the input/output controller135. Other output devices such as the I/O devices140,145may include input devices, for example but not limited to a printer, a scanner, microphone, and the like. Finally, the I/O devices140,145may further include devices that communicate both inputs and outputs, for instance but not limited to, a network interface card (NIC) or modulator/demodulator (for accessing other files, devices, systems, or a network), a radio frequency (RF) or other transceiver, a telephonic interface, a bridge, a router, and the like. The system100can further include a display controller125coupled to a display130. In an exemplary embodiment, the system100can further include a network interface160for coupling to a network165. The network165can be an IP-based network for communication between the computer101and any external server, client and the like via a broadband connection. The network165transmits and receives data between the computer101and external systems. In an exemplary embodiment, network165can be a managed IP network administered by a service provider. The network165may be implemented in a wireless fashion, e.g., using wireless protocols and technologies, such as WiFi, WiMax, etc. The network165can also be a packet-switched network such as a local area network, wide area network, metropolitan area network, Internet network, or other similar type of network environment. The network165may be a fixed wireless network, a wireless local area network (LAN), a wireless wide area network (WAN) a personal area network (PAN), a virtual private network (VPN), intranet or other suitable network system and includes equipment for receiving and transmitting signals.

If the computer101is a PC, workstation, intelligent device or the like, the instructions in the memory110may further include a basic input output system (BIOS) (omitted for simplicity). The BIOS is a set of essential routines that initialize and test hardware at startup, start the OS111, and support the transfer of data among the hardware devices. The BIOS is stored in ROM so that the BIOS can be executed when the computer101is activated. When the computer101is in operation, the processor105is configured to execute instructions stored within the memory110, to communicate data to and from the memory110, and to generally control operations of the computer101pursuant to the instructions.

Referring now toFIG. 2, a block diagram of a system200for optimizing the grouping of instructions in a microprocessor in accordance with an embodiment is shown. As illustrated, the system200includes a streaming buffer204which receives raw data from a cache202. In exemplary embodiments, the streaming buffer204forms clumps of instructions from the raw data received from the cache202. The size of the clumps of instructions may be determined based on a size of a pipeline, or communications link, between the streaming buffer204and an instruction queue208. Once the clumps are formed by the streaming buffer204, the clumps are sent to both instruction queue208and to a pre-decode unit206. In exemplary embodiments, the instruction queue208is configured to store the instructions until the instructions are ready to be grouped and dispatched to an issue unit216. In exemplary embodiments, the instructions are dispatched to an issue unit216in a dispatch group having a maximum number of instructions that may be based on the type of the issue unit216.

In exemplary embodiments, the pre-decode unit206interprets the instructions in the clump and generates initial grouping information that will be used to group the instructions. In exemplary embodiments, the pre-decode unit206utilizes hint registers210to store pre-decode logic and local registers212to store the grouping information. The local registers212are configured to store the grouping information for the instruction until the instructions are ready to be dispatched to the issue unit216. In exemplary embodiments, the local registers212are configured to store grouping information for instructions across more than one clump. For example, if a clump includes six instructions, the local registers212may be able to store grouping information for seven or more instructions. In exemplary embodiments, the grouping unit214interprets grouping rules stored in the hint registers210, updates the grouping information stored in the local registers212if possible, and dispatches the grouped instructions to one or more issue units216.

In exemplary embodiments, the initial grouping information created by the pre-decode unit206is speculative and is not always correct or complete. One reason that the initial grouping information is speculative is that there are many rules that determine grouping. In addition, for various reasons all of grouping rules may not be known during the pre-decode phase. For these reasons, the pre-decode unit206is configured to take a pessimistic view, or to assume worst case scenario, when creating the initial grouping information. In exemplary embodiments, the pessimistic view may include assuming that an instruction either ends a group or groups alone. For example, if an instruction is tagged as “ends a group” then no instruction may follow that instruction in the group in the same cycle. Likewise an instruction that is set as “groups alone” must be the only instruction in the group.

In exemplary embodiments, the initial grouping information created by the pre-decode unit206can updated or modified by the grouping unit214. Once instructions are available from the instruction queue, the grouping information stored in the local registers212can be re-written. For example, if initial grouping information assumed that an instruction ends a group and it turns out that the instruction does not end a group, the grouping can be updated.

In general, when instructions pass through the pre-decode unit206, it is impossible for the last and next to last instruction in a clump to get a full picture of their grouping scenario due to the fact that one (in the case of the next to last instruction) or more (in the case of the last instruction) subsequent instructions are unavailable. In exemplary embodiments, the initial grouping information for these instructions assumes the worst case scenario, i.e., no other instructions are available and we will potentially have empty slots in a dispatch group). At the same time, at least some of the grouping information for these instructions is stored in local registers212used by the pre-decode unit204for use later.

Once the next set of pre-decodes are available (i.e., after the next clump of instructions is received and processed by the pre-decode unit) it is possible to update the grouping information for the previous instructions. Accordingly, if an instruction was pre-decoded in the previous cycle with stringent grouping rules (i.e., must group alone), and was not consumed (i.e., grouped and dispatched to the issue unit216) during the last cycle, the current cycle will have this information and may update the grouping information. In addition, if it is determined that there are empty slots available in a previously calculated dispatch group, then the hint registers210can be rewritten with a new grouping rule to fill the available slots in the dispatch group.

In exemplary embodiments, during every processing cycle, the hint registers210are written with information from all of the instructions pre-decoded in the clump. In addition, the pre-decode unit206stores local data for at least the last two instructions in the clump in the local registers212. The data stored in the hint registers210and the local registers212is easily accessible by the pre-decode unit206, and is used to re-evaluate the previous cycle's grouping decisions. In exemplary embodiments, only a small amount of data may be stored for the second to last instruction while a larger amount is stored for the last instruction because the last instruction can have up to two instructions follow it in the next cycle.

In exemplary embodiments, the grouping rules can only restrict the number of instructions dispatched and if the last instruction of the previous cycle has two instructions following it then the grouping unit needs to know all of its restrictions. Even though information is stored for the last two instructions in a clump, these last two instructions may not be used in the next cycle's grouping rules. It is possible for all the instructions in a clump to be consumed in a single cycle. If for any reason the information in the hint registers210is no longer useful they can be overwritten. If the hint registers210are overwritten then the new information will be used for the grouping rules in the current cycle.

Referring now toFIG. 3, a flowchart diagram of a method300optimizing the grouping of instructions in a microprocessor in accordance with an embodiment is shown. As shown at block302, the method300includes receiving a clump having a plurality of instructions from a streaming buffer. Next, as shown at block304, the method300includes pre-decoding each of the plurality of instructions in the clump for select information. The method300also includes sending the plurality of instructions to an instruction queue, as shown at block306. Next, as shown at block308, the method300includes storing initial grouping information for each of the plurality of instructions in local registers. In exemplary embodiments, the initial grouping information for each of the plurality of instructions is based on worst case grouping scenario.

Continuing with reference toFIG. 3, the method300also includes receiving an indication from the instruction queue that one or more of the plurality of instructions is ready to be dispatched from the instruction queue, as shown at block310. Next, as shown at decision block312, the method300includes determining if additional pre-decode information is available. If additional pre-decode information is not available, the method300proceeds to block314and the one or more of the plurality of instructions that are ready to be dispatched from the instruction queue are grouped based on the initial grouping information. If additional pre-decode information is available, the method300proceeds to block316and updates the initial group information stored in the local register based on the additional pre-decode information. Next, as shown at decision block318, the method300includes grouping the one or more of the plurality of instructions that are ready to be dispatched from the instruction queue based on the updated grouping information stored in the local register. The method300also includes dispatching the grouped instruction to an issue unit, as shown at block320.

Referring now toFIG. 4, a flowchart diagram of a method400for optimizing the grouping of instructions in a microprocessor in accordance with an embodiment is shown. As shown at block402, the method400includes receiving a first clump having a first plurality of instructions from a streaming buffer during a first cycle of a microprocessor. Next, as shown at block404, the method400includes pre-decoding each of the plurality of instructions in the clump for select information. The method400also includes storing pre-decode logic in hint registers and storing initial grouping information for each of the plurality of instructions in local registers, as shown at block406. Next, as shown at block408, the method400includes receiving a second clump having a second plurality of instructions from the streaming buffer during a second cycle of a microprocessor. The method400also includes pre-decoding each of the plurality of instructions in the second clump, as shown at block410.

Next, as shown at block412, the method400includes updating the initial group information stored in the local registers based on the pre-decoding of the second clump. The method400also includes receiving an indication from an instruction queue that one or more of the first plurality of instructions and the second plurality of instructions stored in the local registers are ready to be dispatched, as shown at block414. Next, as shown at block416, the method400includes grouping the one or more of the first plurality of instructions and the second plurality of instruction that are ready to be dispatched based on the updated grouping information stored in the local registers. The method400also includes dispatching the grouped instruction to an issue unit, as shown at block418.