Radiation hardened differential output buffer

A radiation hardened differential output buffer is partitioned into multiple stages, each including at least one current source and a bridge circuit. Each stage receives substantially the same inputs at substantially the same time, and provides substantially the same output. The outputs of each stage are connected together. As a result, if one of the stages is disrupted by SEE, the disrupted stage does not contribute enough current to the output of the differential output buffer to disrupt the output signal.

FIELD

The present invention relates generally to differential output buffers, and more particularly, relates to a differential output buffer that has enhanced performance in total dose, dose rate, and single event effect environments.

BACKGROUND

Many digital communication designs include differential output buffers. Two common differential output buffers are Low-Voltage Differential Signaling (LVDS) and Differential Current Mode Logic (CML). A typical LVDS differential output buffer100is depicted inFIG. 1, while a typical CML differential output buffer200is depicted inFIG. 2.

The LVDS differential output buffer100is usually fabricated using four CMOS transistors102-108connected in a bridge formation as shown inFIG. 1. The differential output buffer100also includes a current source110. The differential output buffer100operates by steering current through a termination resistor112, which is typically 100 Ohms, located at a remote receiver114. For a logic-1, current flows from the current source110through the transistor104, through the termination resistor112, and to ground through the transistor106. For a logic-0, current flows from the current source110through the transistors102,108and the termination resistor112.

During steady-state conditions, the transistors102-108are either in saturation or cutoff, and current does not flow from the current source110to ground without going through the termination resistor112. While this provides for low-power operation at low frequencies, it limits the speed at which the transistors are able to switch.

The CML differential output buffer200is typically fabricated using two resistors202,204and two transistors206,208connected in a bridge formation as shown inFIG. 2. The transistors206,208may be CMOS transistors as depicted inFIG. 2, bipolar transistors, or any other suitable transistor type. The differential output buffer200also includes a current source210. For a logic-1, current travels though one of the resistors202,204, through a termination resistor212(typically 100 Ohms, located at a remote receiver114), through one of the transistors206,208, and into the current source210. For a logic-0, the current flows through the other resistor and transistor in the output buffer200.

The operation of the CML differential output buffer200is similar to the LVDS differential output buffer100, except the transistors206,208operate in the linear range. Because of this linear operation, there is a small current that flows from the current source to ground through both resistors202,204and transistors206,208in the CML differential output buffer200. By operating the transistors206,208in their linear range, the CML differential output buffer200can operate at very high frequencies.

A differential output buffer, such as the buffers depicted inFIGS. 1-2, may be used in applications in which the buffer is exposed to harsh environments, such as space and military applications. However, the current sources and transistors in the differential output buffers may be susceptible to Single Event Effects (SEE). SEE is a disturbance in an active semiconductor device caused by a single energetic particle. As semiconductor devices become smaller and smaller, transistor threshold voltages decrease. These lower thresholds reduce the charge per node needed to cause errors. As a result, the semiconductor devices become more and more susceptible to transient upsets.

One type of SEE is a single event upset (SEU). SEU is a radiation-induced error in a semiconductor device caused when charged particles lose energy by ionizing the medium through which they pass, leaving behind a wake of electron-hole pairs. The electron-hole pairs form a parasitic conduction path, which can cause a false transition on a node. The false transition, or glitch, can propagate through the semiconductor device and may ultimately result in the disturbance of a node containing state information, such as an output of a latch, register, or gate.

Typically, an SEU is caused by ionizing radiation components, such as neutrons, protons, and heavy ions. The ionizing radiation components are abundant in space and at commercial flight altitudes. Additionally, an SEU may be caused by alpha particles from the decay of trace concentrations of uranium and thorium present in some integrated circuit packaging. As another example, an SEU may be caused by detonating nuclear weapons. When a nuclear weapon is detonated, intense fluxes of gamma rays, x-rays, and other high energy particles are created, which may cause SEU.

Thus, it would be beneficial to harden a differential output buffer so that the buffer may be used in applications that are susceptible to SEE.

SUMMARY

A radiation hardened differential output buffer is described. In one example, the differential output buffer includes a plurality of stages designed to provide a substantially similar output signal upon receiving a substantially similar input signal. An output of each of the plurality of stages is electrically connected to provide an output of the differential output buffer. A radiation induced disruption in a single stage is unable to change the output of the differential output buffer. Due to the separation of stages, neither single nor double radiation induced disruptions can bridge across multiple stages. The differential output buffer also includes a drive circuit controlling the plurality of stages by providing the substantially similar input signals to each of the plurality of stages. As a result, the output of the differential output buffer remains unchanged if one of the stages is temporarily impacted by the Single Event Effect as no one stage contributes enough current to alter the state of the differential output buffer.

Each of the stages includes at least one current source and a bridge circuit. Preferably, each of the plurality of stages includes two current sources. In one example, the bridge circuit includes four transistors. In another example, the bridge circuit includes two transistors and two resistors.

The number of stages in the radiation hardened differential output buffer is selected based on an amount of current supplied by the at least one current source. The output of each of the stages is a differential current signal. The pre-drive circuit provides a complementary digital signal to each of the stages. The pre-drive circuit provides the complementary digital signal to the different drive stages at substantially the same time.

In another example, the differential output buffer includes a plurality of stages having two current sources connected to a transistor bridge circuit. Each of the plurality of stages is designed to provide a substantially similar differential current output signal upon receiving a substantially similar complementary digital input signal. An output of each of the plurality of stages is electrically connected to provide an output of the differential output buffer. The differential output buffer also includes a pre-drive circuit for providing the complementary digital input signal to each of the plurality of stages. A particle strike on one of the plurality of stages is unable to cause an erroneous signal at the output of the differential output buffer. Due to the separation of stages, neither single nor double radiation induced disruptions can bridge across multiple stages.

The number of stages included in the differential output buffer is selected based on an amount of current supplied by the at least one current source. The transistor bridge circuit includes two p-channel transistors and two n-channel transistors. The pre-drive circuit provides the complementary digital input signals to the stages at substantially the same time. The pre-drive circuit delays the input signals to the stages so that the input signals reach the stages at substantially the same time.

A method of hardening a differential output buffer against a Single Event Effect is also described. The method includes selecting a number of stages each having at least one current source and a bridge circuit; connecting an output of each of the stages to a node; and driving the stages with a digital signal. Each of the stages provides a current signal in response to the digital signal. An output of one of the stages is unable to disrupt a signal at the node. As a result, a current signal change caused by the Single Event Effect at one of the stages does not impact the differential output buffer.

The number of stages is selected based on an amount of current supplied by the at least one current source. Driving the stages with a digital signal includes controlling the operation of the stages. For example, controlling the stages may include delaying the digital signal so that the digital signal pre-drives each of the stages at substantially the same time.

These as well as other aspects and advantages will become apparent to those of ordinary skill in the art by reading the following detailed description, with reference where appropriate to the accompanying drawings. Further, it is understood that this summary is merely an example and is not intended to limit the scope of the invention as claimed.

DETAILED DESCRIPTION

Instead of using a steered current differential output buffer, such as the differential output buffers100,200depicted inFIGS. 1-2, a voltage steering scheme is used to harden a differential output buffer in total dose, dose rate, and SEE environments. The differential output buffer is more resilient to SEE than traditional LVDS and CML-style output buffers. One example of a steered voltage differential output buffer is depicted inFIG. 3.

FIG. 3is a circuit diagram of a hardened differential output buffer300. The differential output buffer300uses multiple current sources and pre-drive signals so that a single SEE strike affects only one of the current sources. This disruption to the single current source is not large enough to change the state of the output of the differential output buffer300. As a result, the differential output buffer300can be used in applications in which the differential output buffer300is exposed to harsh environments, such as space and military applications.

The differential output buffer300is partitioned into multiple stages302-308. Each of the stages302-308includes a similar number and arrangement of components. While the stages302-308may vary in some manner, the stages302-308are designed to provide substantially the same output upon receiving substantially the same input.

WhileFIG. 3depicts four stages, more or fewer than four stages may be used. The number of stages is selected so that a particle strike on one of the stages302-308is not enough to impact the output of the differential output buffer300. The amount of current supplied by the current sources may be used to select the appropriate number of stages.

As shown inFIG. 3, each of the stages302-308includes two current sources310,312. The first or top current source310is connected to node “w” of a transistor bridge. The second or bottom current source312is connected between ground and node “z” of the transistor bridge. Alternatively, just one current source may be used, either the top current source310like the differential output buffer100or the bottom current source312like the differential output buffer200.

Each of the current sources310,312provides a proportional amount of current. For example, if four stages are used, each current source310,312provides one fourth of the current supply for the differential output buffer300. Thus, if the current source for the differential output buffer300is 3.5 mA, each of the current sources310,312provides approximately 0.875 mA. As a result, the amount of current pushed to or pulled from the output by any current source310,312is limited.

The transistor bridge includes four transistors314-320. The transistors314-320are depicted inFIG. 3as switches to indicate that any transistor type, such as CMOS, bipolar, and so on, may be used in the stages302-308. Preferably, the first and second transistors314,316are p-channel transistors, while the third and fourth transistors318,320are n-channel transistors. Alternatively, the first and second transistors314,316are replaced with resistors like the differential output buffer200.

As depicted inFIG. 3, the first transistor314is connected between nodes “w” and “x” of the transistor bridge. The second transistor316is connected between nodes “w” and “y” of the transistor bridge. The third transistor318is connected between nodes “x” and “z” of the transistor bridge. The fourth transistor320is connected between nodes “y” and “z” of the transistor bridge.

A pre-drive circuit322drives or controls the stages302-308. The pre-drive circuit322provides each of the stages302-308with a complementary pair of digital signals. For example, if signal A is at a logic-1 level, signal Abar is designed to be at a logic-0 level; and if signal A is at a logic-0 level, signal Abar is designed to be at a logic-1 level. The number of complementary pairs depends on the number of stages used in the differential output buffer300. As an example,FIG. 3depicts four stages302-308, so the pre-drive circuit322provides four complementary pairs (i.e., A, Abar; B, Bbar; C, Cbar; and D, Dbar).

The complementary pair outputs from the pre-drive circuit322are designed to be at the same logic levels (i.e., A=B=C=D and Abar=Bbar=Cbar=Dbar), but with various delays based on the locations of each of the stages302-308. The delays may be created with any timer and/or delay circuit design. The delays are designed so that each of the stages302-308provides an output based on an input to the stages302-308at approximately the same time. Thus, the delay to the stage located the furthest away from the pre-drive circuit322is the shortest. Conversely, the delay to the stage located closest to the pre-drive circuit322is the longest. Preferably, the four stages302-308are positioned far enough away from each other to reduce the possibility of an SEE impacting more than one stage.

Each of the stages302-308provides a differential current output, OUTpand OUTn. The differential current outputs from each of the stages302-308are designed to be substantially the same. OUTpis connected to node “x” of the transistor bridge, while OUTnis connected to node “y” of the transistor bridge. The differential current outputs from the stages302-308may be electrically connected such that all the OUTpsignals are connected at a single circuit node “x” and all the OUTnsignals are connected at a single circuit node “y.” In this manner, the differential current outputs are effectively voted. Alternatively, the differential current outputs may be connected to voter circuitry, such as a comparator. As a result, if one of the stages is disrupted by an SEE, the disrupted stage does not contribute enough current to the output of the differential output buffer300to disrupt the differential current output signal.

A termination resistor may be connected between nodes “x” and “y” at a distance away from the stages302-308. The termination resistor is not shown inFIG. 3, but is substantially the same as the termination resistors112,212depicted inFIGS. 1 and 2, respectively.

The pre-drive circuit322controls the current flow through the stages302-308. For example, when the A, B, C, and D signals are at a logic-1, the A, B, C, and D switches may close, while the switches controlled by the complementary signals Abar, Bbar, Cbar, and Dbar are opened. In this configuration, current may flow from the current source310, through transistor314, through a termination resistor connected between nodes “x” and “y,” through transistor320, and through current source312to ground. Similarly, if the pre-drive circuit322provides a logic-0 level on the A, B, C, and D outputs, the A, B, C, and D switches may open, while the switches controlled by the complementary signals Abar, Bbar, Cbar, and Dbar are closed. In this configuration, current may flow from the current source310, through transistor316, through a termination resistor connected between nodes “x” and “y,” through transistor318, and through current source312to ground.

As one example, the hardened differential output buffer300may be used in LVDS-style and CML-style output buffers. As another example, the hardened differential output buffer300may be used in a SerDes system. The SerDes system includes a dedicated serializer/deserializer pair and may be used in high-speed communication applications. By including the hardened differential output buffer300in LVDS-style output buffers, CML-style output buffers, or the SerDes system, these devices may be operated in environments susceptible to SEE.

It should be understood that the illustrated embodiments are examples only and should not be taken as limiting the scope of the present invention. The claims should not be read as limited to the described order or elements unless stated to that effect. Therefore, all embodiments that come within the scope and spirit of the following claims and equivalents thereto are claimed as the invention.