Semiconductor structure and method of forming the same

A method of forming a semiconductor structure includes the following steps. A dielectric stack is formed on a bottom metal. A first mask layer is formed on the dielectric stack. The first mask layer has a plurality of first through holes, and a portion of the first through holes is in a central portion of the first mask layer. A second mask layer is formed on the first mask layer and in the first through holes. The second mask layer is patterned to form an opening between a central portion of the second mask layer covers the portion of the first through holes and is surrounded by the peripheral portion. The dielectric stack is etched below the first through holes the second through hole. A conductive layer is formed in the second through hole and on a top surface of the dielectric stack.

BACKGROUND

Technical Field

The present disclosure relates to a semiconductor structure and a method of forming the semiconductor structure.

Description of Related Art

With the rapid growth of electronic industry, the development of semiconductor devices has achieved high performance and miniaturization. Decoupling capacitors with small capacitance are needed for DRAM circuit design. In greater details, the decoupling capacitors can be built into chips to prevent voltage spikes in a power supply such as, for example, when the chip is initially powered or when various components of the chip are activated.

However, there is a risk to induce collapsed structure with a smaller array of the capacitors. It's because that smaller array of the capacitors are stood-alone during current fabrication method.

SUMMARY

According to one embodiment of the present disclosure, a method for forming a semiconductor structure includes the following steps. A method of forming a semiconductor structure includes the following steps. A dielectric stack is formed on a bottom metal. A first mask layer is formed on the dielectric stack. The first mask layer has a plurality of first through holes, and a portion of the first through holes is in a central portion of the first mask layer. A second mask layer is formed on the first mask layer and in the first through holes. The second mask layer is patterned to form an opening between a central portion of the second mask layer covers the portion of the first through holes and is surrounded by the peripheral portion. The dielectric stack is etched below the first through holes the second through hole. A conductive layer is formed in the second through hole and on a top surface of the dielectric stack.

In some embodiments of the present disclosure, the method of forming the semiconductor structure further includes forming a metal layer on a sidewall of the second through hole and the top surface of the dielectric stack before forming the conductive layer.

In some embodiments of the present disclosure, the method of forming the semiconductor structure further includes forming the metal layer on a bottom surface of the second through hole, such that the metal layer is in contact with the bottom metal.

In some embodiments of the present disclosure, the method of forming the semiconductor structure further includes etching the metal layer on the top surface of the dielectric stack to form a third through hole.

In some embodiments of the present disclosure, etching a portion of the metal layer is such that the third through hole directly connects to the second through hole.

In some embodiments of the present disclosure, the method of forming the semiconductor structure further includes forming a top electrode in the third through hole.

In some embodiments of the present disclosure, forming the top electrode in the third through hole is such that the top electrode electrically connects the conductive layer.

In some embodiments of the present disclosure, the method of forming the semiconductor structure further includes forming a first isolation on the dielectric stack before forming the first mask layer.

In some embodiments of the present disclosure, the method of forming the semiconductor structure further includes forming a second isolation layer on the first isolation layer, such that the metal layer is between the first isolation layer and the second isolation layer.

In some embodiments of the present disclosure, the method of forming the semiconductor structure further includes removing an oxide layer of the dielectric layer of the dielectric stack before forming the conductive layer.

In some embodiments of the present disclosure, the method of forming the semiconductor structure further includes forming a dielectric structure in the second through hole before forming the conductive layer, such that the conductive layer in the second through hole is surrounded by the dielectric structure.

In some embodiments of the present disclosure, the peripheral portion and the central portion of the second mask layer are made of photoresist materials.

In some embodiments of the present disclosure, patterning the second mask layer is such that the opening of the second mask layer directly connects the first through hole of the first mask layer.

In some embodiments of the present disclosure, patterning the second mask layer is such that a width of the opening of the second mask layer is larger than a width of the first through hole of the first mask layer.

In the aforementioned embodiments, since the second mask layer is patterned to form the opening between the central portion and the peripheral portion of the second mask layer, smaller array of capacitor (small-size capacitor) can be achieved. As a result, collapsed risk of the semiconductor structure can be avoided and the performance of the semiconductor structure can be improved.

DETAILED DESCRIPTION

FIG. 1AandFIG. 1Bare respectively a top view and a cross-sectional view of a semiconductor structure at one stage in accordance with one embodiment of the present disclosure.FIG. 1Bis taken along line1B-1B ofFIG. 1A. Referring toFIG. 1AandFIG. 1B, a dielectric stack110is formed on a bottom metal100. The dielectric stack110may include a plurality of nitride layers and a plurality of oxide layers alternately formed on the bottom metal100. In greater details, a first nitride layer112, a first oxide layer113, a second nitride layer114, and a second oxide layer115are formed in sequence on the bottom metal100. In some embodiments, the first nitride layer112is in contact with the bottom metal100. In some embodiments, the bottom metal100may serve as a bottom electrode of the semiconductor structure.

After the dielectric stack110is formed on the bottom metal100, a first isolation layer120is formed on the dielectric stack110. The first isolation layer120may be made of a nitride material. For example, the first isolation layer120is made of silicon nitride or other suitable dielectric materials. In some embodiments, the first isolation layer120is formed by chemical vapor deposition CVD, ALD, or other suitable process. In some embodiments, the first isolation layer120is made of same materials as the first nitride layer112and the second nitride layer114.

In some embodiments, a substrate is formed before forming the bottom metal100. The substrate may be a silicon substrate. Alternatively, the substrate may include another elementary semiconductor, such as germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GalnAs, GaInP, and/or GaInAsP; or combinations thereof.

FIG. 2AandFIG. 2Bare respectively a top view and a cross-sectional view of a semiconductor structure at one stage in accordance with one embodiment of the present disclosure.FIG. 2Bis taken along line2B-2B ofFIG. 2A. Referring toFIG. 2AandFIG. 2B, a first mask layer130is formed on the dielectric stack110. The first mask layer130has a plurality of first through holes132, and a portion of the first through holes132are located in a central portion of the first mask layer130. In other words, the first mask layer130is in contact with the first isolation layer120. The first through holes132expose the underlying first isolation layer120.

In some embodiments, the first mask layer130is made of a photoresist material or multilayer dielectrics. For example, the first mask layer130is made of a black photoresist material or multilayer dielectrics, such as oxide-nitride-oxide (ONO). In some embodiments, the method of forming the first mask layer130may include first forming a photoresist layer on the first isolation layer120and then patterning the photoresist layer with a photolithography process.

FIG. 3AandFIG. 3Bare respectively a top view and a cross-sectional view of a semiconductor structure at one stage in accordance with one embodiment of the present disclosure.FIG. 3Bis taken along line3B-3B ofFIG. 3A. Referring toFIG. 2A,FIG. 2B,FIG. 3AandFIG. 3B, after the first mask layer130is formed on the dielectric stack110, a second mask layer140is formed on the first mask layer130and in the first through holes132. In other words, the second mask layer140covers the first mask layer130and filled in the first through holes132.

After the second mask layer140is formed on the first mask layer130and in the first through holes132, the second mask layer140is patterned to form a first opening142between a central portion144and a peripheral portion146of the second mask layer140, such that the second mask layer140in the first through holes132below the first opening142is removed. As a result, a structure of the first mask layer130and the second mask layer140is beneficial to improve smaller size of a capacitor in following processes. By adjusting the size of the capacitor, the desired design of the semiconductor structure can be achieved.

In greater details, the central portion144of the second mask layer140covers the portion of the first through holes132in the central portion of the first mask layer130and is surrounded by the peripheral portion146. The central portion144of the second mask layer140is located correspondingly on the central portion of the first mask layer130. For example, the central portion144of the second mask layer140is at same vertical level as the central portion of the first mask layer130.

In some embodiments, patterning the second mask layer140is such that the first opening142of the second mask layer140directly connects the first through hole132of the first mask layer130. The first through holes132exposes the underlying first isolation layer120. In some embodiments, patterning the second mask layer140is such that a width W2of the first opening142of the second mask layer140is larger than a width W1of the first through hole132of the first mask layer130.

In some embodiments, as shown inFIG. 3B, the second mask layer140and the first mask layer130have a stepped profile. As shown inFIG. 3A, the second mask layer140has a hollow-shaped or donut-shaped pattern. In some other embodiments, the second mask layer140has a mesh-shaped pattern.

In some embodiments, the central portion144and the peripheral portion146of the second mask layer140are light shielding portions. In some embodiments, the central portion144and the peripheral portion146of the second mask layer140are made of photoresist materials or multilayer dielectrics. For example, the central portion144and the peripheral portion146of the second mask layer140are made of black photoresist materials or multilayer dielectrics, such as oxide-nitride-oxide (ONO).

FIG. 4AandFIG. 4Bare respectively a top view and a cross-sectional view of a semiconductor structure at one stage in accordance with one embodiment of the present disclosure.FIG. 4Bis taken along line4B-4B ofFIG. 4A. Referring toFIG. 3A,FIG. 3B,FIG. 4AandFIG. 4B, after the second mask layer140is patterned, the dielectric stack110is etched below the first through holes132to form a second through hole148. In greater details, the first isolation layer120and the dielectric stack110are etched using the first mask layer130and the second mask layer140as etch masks. The etching process deepens the first through hole132until reaching the bottom metal100so as to form the second through hole148. The bottom metal100is exposed through the second through hole148.

In some embodiments, after the first isolation layer120and the dielectric stack110are etched, the first mask layer130and the second mask layer140are removed.

In some embodiments, as shown inFIG. 3BandFIG. 4B, a depth of the second through hole148is larger than the first through hole132. In some embodiments, as shown inFIG. 3BandFIG. 4B, a width W3of the second through hole148is substantially same as the width W1of the first through hole132.

FIG. 5AandFIG. 5Bare respectively a top view and a cross-sectional view of a semiconductor structure at one stage in accordance with one embodiment of the present disclosure.FIG. 5Bis taken along line5B-5B ofFIG. 5A. Referring toFIG. 5AandFIG. 5B, after the second through hole148is formed, a metal layer150is formed on a sidewall and a bottom surface of the second through hole148and a top surface of the dielectric stack110. In other words, the metal layer150covers the bottom metal100and the first isolation layer120. In some embodiments, the metal layer150is in contact with the bottom metal100, the dielectric stack110, and the first isolation layer120.

FIG. 6AandFIG. 6Bare respectively a top view and a cross-sectional view of a semiconductor structure at one stage in accordance with one embodiment of the present disclosure.FIG. 6Bis taken along line6B-6B ofFIG. 6A. Referring toFIG. 6AandFIG. 6B, after the metal layer150is formed, a second isolation layer160is formed on the first isolation layer120, such that the metal layer150is between the first isolation layer120and the second isolation layer160. In other words, the second isolation layer160covers the metal layer150. The second isolation layer160is in contact with the metal layer150on the top surface of the dielectric stack110.

In some embodiments, the second isolation layer160may be made of a nitride material. For example, the second isolation layer160is made of silicon nitride or other suitable dielectric materials. In some embodiments, the second isolation layer160is formed by chemical vapor deposition CVD, ALD, or other suitable process. In some embodiments, the second isolation layer160is made of same materials as the first isolation layer120.

FIG. 7AandFIG. 7Bare respectively a top view and a cross-sectional view of a semiconductor structure at one stage in accordance with one embodiment of the present disclosure.FIG. 7Bis taken along line7B-7B ofFIG. 7A. Referring toFIG. 7AandFIG. 7B, after the second isolation layer160is formed, a third mask layer170is formed on the second isolation layer160. The third mask layer170has a second opening172which exposes the underlying second isolation layer160.

In some embodiments, the second opening172is aligned with the second through hole148. The second opening172and the second through hole148are separated by the second isolation layer160. In some embodiments, a width of the second opening172is larger than the width of the second through hole148.

In some embodiments, the third mask layer170has a lattice-shaped pattern. In some embodiments, the third mask layer170is made of a photoresist material or multilayer dielectrics. For example, the third mask layer170is made of a black photoresist material or multilayer dielectrics, such as oxide-nitride-oxide (ONO). In some embodiments, the method of forming the third mask layer170may include first forming a photoresist layer and then patterning the photoresist layer with a photolithography process.

FIG. 8AandFIG. 8Bare respectively a top view and a cross-sectional view of a semiconductor structure at one stage in accordance with one embodiment of the present disclosure.FIG. 8Bis taken along line8B-8B ofFIG. 8A. Referring toFIG. 8AandFIG. 8B, after the third mask layer170is formed, the metal layer150on the top surface of the dielectric stack110is etched to form a third through hole174. In greater details, the metal layer150and the second isolation layer160are etched using the third mask layer170as an etch mask. The etching process removes a portion of the metal layer150and the second isolation layer160, such that the third through hole174directly connects to the second through hole148. A bottom portion152of the metal layer150is exposed through the second through hole148.

In some embodiments, after the metal layer150and the second isolation layer160are etched, the third mask layer170is removed.

In some embodiments, a width W4of the third through hole174is larger than the width W3of the second through hole148. In some embodiments, a depth of the third through hole174is smaller than the depth of the second through hole148.

FIG. 9AandFIG. 9Bare respectively a top view and a cross-sectional view of a semiconductor structure at one stage in accordance with one embodiment of the present disclosure.FIG. 9Bis taken along line9B-9B ofFIG. 9A. Referring toFIG. 8A,FIG. 8B,FIG. 9AandFIG. 9B, after the third through hole174is formed, the first oxide layer135and the second oxide layer115of the dielectric stack110are removed to form a recess R. In some embodiments, the recess R directly connects to the third through hole174. The recess R and the second through hole148are separated apart by the metal layer150.

FIG. 10AandFIG. 10Bare respectively a top view and a cross-sectional view of a semiconductor structure at one stage in accordance with one embodiment of the present disclosure.FIG. 10Bis taken along line10B-10B ofFIG. 9A. Referring toFIG. 9A,FIG. 9B,FIG. 10AandFIG. 10B, after the first oxide layer135and the second oxide layer115of the dielectric stack110are removed, a dielectric structure180is formed in the recess R. In greater details, the dielectric structure180further formed on a top surface of the second isolation layer160. The dielectric structure180is in contact with the first nitride layer112, the second nitride layer114, the first isolation layer120, the metal layer150, and the second isolation layer160. In some embodiments, the dielectric structure180is formed in the second through hole148. In some embodiments, the dielectric structure180includes a high-k dielectric material and titanium nitride (TiN).

After the dielectric structure180is formed, a first conductive layer190is formed in the second through hole148and on the top surface of the dielectric stack110. The first conductive layer190is further formed on a top surface of the dielectric structure180. In some embodiments, the first conductive layer190in the second through hole148is surrounded by the dielectric structure180in the second through hole148. The metal layer150, the dielectric structure180, and the first conductive layer190in the second through hole148may serve as a capacitor.

In some embodiments, the first conductive layer190may be made of metal. In some embodiments, the first conductive layer190and the metal layer150are made of same materials.

After the first conductive layer190is formed, a top electrode200is formed in the third through hole174. In other words, the top electrode200is formed on the first conductive layer190. Stated differently, the top electrode200electrically connects to the first conductive layer190. In some embodiments, a bottom surface of the top electrode200is below to a bottom surface of the metal layer150. In some embodiments, the top electrode200is made of a polysilicon material.

After the top electrode200is formed, a second conductive layer210is formed on the top electrode200. In some embodiments, the second conductive layer210is in contact with the top electrode200. In some embodiments, the second conductive layer210is made of metal, such as tungsten.

In summary, because the second mask layer is patterned to form the opening between the central portion and the peripheral portion of the second mask layer, smaller array of capacitor (small-size capacitor) can be achieved. As a result, collapsed risk of the semiconductor structure can be avoided and the performance of the semiconductor structure can be improved.