Memory management table processing method, memory controller, and memory storage apparatus

A memory management table processing method for storing a plurality of entries belonging to a plurality of memory management tables into a buffer memory of a memory storage apparatus is provided, wherein each of the entries has at least one invalid bit. The present method includes following steps. An area corresponding to each of the memory management tables is configured in the buffer memory. Invalid bit information corresponding to each of the memory management tables is recorded. The invalid bit in each of the entries is removed according to the invalid bit information corresponding to each of the memory management tables, so as to generate a valid data stream corresponding to each of the entries. Each of the valid data streams is written into the corresponding area in the buffer memory. Accordingly, the storage space of the buffer memory can be efficiently utilized.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefit of Taiwan application serial no. 100120727, filed on Jun. 14, 2011. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of specification.

BACKGROUND

1. Technology Field

The present invention generally relates to a memory management table processing method, and more particularly, to a memory management table processing method for writing data streams belonging to a memory management table into a buffer memory and reading data streams belonging to the memory management table from the buffer memory, and a memory controller and a memory storage apparatus using the same.

2. Description of Related Art

Along with the widespread of digital cameras, cell phones, and MP3 in recently years, the consumers' demand to storage media has increased drastically. Rewritable non-volatile memory is one of the most adaptable storage media to portable electronic products (for example, cell phones, personal digital assistants (PDAs), and notebook computers) due to its many characteristics such as data non-volatility, low power consumption, small volume, non-mechanical structure, and high access speed. For example, a solid state drive (SSD) is a storage apparatus which uses a flash memory as its storage medium. Thus, in recent years, the flash memory industry has become a major part of the electronic industry.

A rewritable non-volatile memory module has a plurality of physical blocks, and each of the physical blocks has a plurality of physical pages. While writing data into a physical block, the data has to be written according to the sequence of the physical pages. In addition, a physical page containing data has to be erased before it is used for writing new data. In particular, each physical block is the smallest erasing unit, and each physical page is the smallest programming (i.e., writing) unit.

In order to improve the operation efficiency, a memory controller of a flash memory storage apparatus groups the physical blocks of a flash memory module into a data area, a free area, a system area, and a replacement area.

Physical blocks in the data area are used for storing data written by a host system. To be specific, a memory controller converts a logical access address accessed by the host system into a logical page of a logical block and maps the logical page of the logical block to a physical page of a physical block in the data area. Namely, in the management of a flash memory module, the physical blocks in the data area are considered used physical blocks (for example, already containing data written by a host system). Additionally, the memory controller records the mapping relationship between the logical blocks and the physical blocks in the data area in a logical block-physical block mapping table, wherein the logical pages of each logical block are sequentially mapped to the physical pages of the corresponding physical block.

Physical blocks in the free area are used for substituting the physical blocks in the data area. To be specific, a physical block already containing data has to be erased before it is used for writing new data, while a physical block in the free area is used for writing updated data and substituting the physical block originally mapped to a logical block. Accordingly, the physical blocks in the free area are either blank blocks or usable blocks (i.e., no data is recorded therein or data recorded therein is already marked as invalid data).

Physical blocks in the system area are used for recording system data, such as the manufacturer and model of the flash memory module, the number of physical blocks in the flash memory module, and the number of physical pages in each physical block.

Physical blocks in the replacement area are used for replacing damaged physical blocks. To be specific, if there are still normal physical blocks in the replacement area and a physical block in the data area is damaged, the memory management circuit selects a normal physical block from the replacement area to replace the damaged physical block.

In order to deal with complicated management operations while managing the flash memory module, the memory controller usually uses many memory management tables for recording information related to the physical blocks. In particular, during the operation of the flash memory storage apparatus, the memory management tables are temporarily stored in a buffer memory to be updated. These memory management tables may include a logical block-physical block mapping table, a free area physical block table, a replacement area physical block table, a system area physical block table, a bad block table, and an erasing count table, etc. Along with the increase in the complicacy of management logic, the number of memory management tables to be used by the memory controller also increases and accordingly more and more storage space in the buffer memory will be taken. However, since the buffer memory offers only a limited storage space, how to efficiently utilize the storage space of the buffer memory has become one of the major subjects in the industry.

SUMMARY

Accordingly, the present invention is directed to a memory management table processing method, a memory controller, and a memory storage apparatus, in which the storage space of a buffer memory can be efficiently utilized.

According to an exemplary embodiment of the present invention, a memory management table processing method for storing a plurality of entries belonging to a plurality of memory management tables into a buffer memory of a memory storage apparatus is provided, wherein each of the entries of the memory management tables has at least one invalid bit. The memory management table processing method includes configuring a plurality of areas in the buffer memory for storing the memory management tables, wherein each of the areas is corresponding to one of the memory management tables. The memory management table processing method also includes recording invalid bit information corresponding to each of the memory management tables, wherein the invalid bit information includes information of the invalid bit of each of the entries of the memory management tables. The memory management table processing method further includes removing at least one invalid bit data from each of the entries according to the invalid bit information to generate a plurality of valid data streams corresponding to the entries of the memory management tables. The memory management table processing method still includes writing each of the valid data streams into a corresponding one of the areas in the buffer memory.

According to an exemplary embodiment of the present invention, a memory controller for managing a rewritable non-volatile memory module is provided. The memory controller includes a memory management circuit, a host interface, a memory interface, a buffer memory, and a temporary data processing circuit. The host interface is configured to couple to a host system. The memory interface is coupled to the rewritable non-volatile memory module. The memory management circuit is coupled to the host interface and the memory interface. The buffer memory is configured to temporarily store data. The temporary data processing circuit is coupled to the memory management circuit and configured to store a plurality of entries belonging to a plurality of memory management tables into a buffer memory of a memory storage apparatus, wherein each of the entries of the memory management tables has at least one invalid bit. The temporary data processing circuit configures a plurality of areas in the buffer memory for storing the memory management tables, wherein each of the areas is corresponding to one of the memory management tables. Besides, the temporary data processing circuit records invalid bit information corresponding to each of the memory management tables, wherein the invalid bit information includes information of the invalid bit of each of the entries of the memory management tables. In addition, the temporary data processing circuit removes at least one invalid bit data from each of the entries according to the invalid bit information to generate a plurality of valid data streams corresponding to the entries of the memory management tables, and the temporary data processing circuit writes each of the valid data streams into a corresponding one of the areas in the buffer memory.

The invention provides a memory storage apparatus including a connector, a rewritable non-volatile memory module, and a memory controller. The connector is configured to couple to a host system. The rewritable non-volatile memory module is configured to store data. The memory controller is coupled to the connector and the rewritable non-volatile memory module and includes a memory management circuit, a host interface, a memory interface, a buffer memory, and a temporary data processing circuit. The host interface is coupled to the host system. The memory interface is coupled to the rewritable non-volatile memory module. The memory management circuit is coupled to the host interface and the memory interface. The buffer memory is configured to temporarily store data. The temporary data processing circuit is coupled to the memory management circuit and configured to store a plurality of entries belonging to a plurality of memory management tables into a buffer memory of the memory storage apparatus, wherein each of the entries of the memory management tables has at least one invalid bit. The temporary data processing circuit configures a plurality of areas in the buffer memory for storing the memory management tables, wherein each of the areas is corresponding to one of the memory management tables. Besides, the temporary data processing circuit records invalid bit information corresponding to each of the memory management tables, wherein the invalid bit information includes information of the invalid bit of each of the entries of the memory management tables. In addition, the temporary data processing circuit removes at least one invalid bit data from each of the entries according to the invalid bit information to generate a plurality of valid data streams corresponding to the entries of the memory management tables, and the temporary data processing circuit writes each of the valid data streams into a corresponding one of the areas in the buffer memory.

As described above, in the memory management table processing method, the memory controller, and the memory storage apparatus provided by the present invention, invalid bit data is removed from data streams corresponding to entries belonging to memory management tables before the data streams are written into the buffer memory, and the removed invalid bit data is restored after the data streams are read from the buffer memory. Thereby, the storage space of the buffer memory can be efficiently utilized.

These and other exemplary embodiments, features, aspects, and advantages of the invention will be described and become more apparent from the detailed description of exemplary embodiments when read in conjunction with accompanying drawings.

DESCRIPTION OF THE EMBODIMENTS

In order to improve the use efficiency of a buffer memory, the present invention provides a data processing method in which the storage space required for storing memory management tables is effectively reduced. As shown inFIG. 1, in the memory management table processing method, a plurality of areas for storing different memory management tables is configured in a buffer memory (S1), wherein each of the areas is corresponding to one of the memory management tables. In addition, in the memory management table processing method, invalid bit information corresponding to each of the memory management tables is recorded (S3), wherein the invalid bit information includes information of at least one invalid bit of each entry of the memory management tables. More, in the memory management table processing method, invalid bit data is removed from the entries of the memory management tables according to the invalid bit information, so as to generate valid data streams corresponding to the entries of the memory management tables (S5), and the valid data streams are respectively written into the corresponding areas in the buffer memory (S7). The present invention will be described in detail with reference to several exemplary embodiments and accompanying drawings.

Generally, a memory storage apparatus (also referred to as a memory storage system) includes a rewritable non-volatile memory module and a controller (also referred to as a control circuit). The memory storage apparatus is usually used with a host system so that the host system can write data into or read data from the memory storage apparatus.

FIG. 2Aillustrates a host system and a memory storage apparatus according to an exemplary embodiment of the present invention.

Referring toFIG. 2A, the host system1000includes a computer1100and an input/output (I/O) device1106. The computer1100includes a microprocessor1102, a random access memory (RAM)1104, a system bus1108, and a data transmission interface1110. The I/O device1106includes a mouse1202, a keyboard1204, a display1206, and a printer1208, as shown inFIG. 2B. However, the I/O device1106is not limited to the devices illustrated inFIG. 2Band may further include other devices.

In the present embodiment, a memory storage apparatus100is coupled to other components of the host system1000through the data transmission interface1110. Data can be written into or read from the memory storage apparatus100through the operations of the microprocessor1102, the RAM1104, and the I/O device1106. The memory storage apparatus100is a rewritable non-volatile memory storage apparatus, such as the flash drive1212, the memory card1214, or the solid state drive (SSD)1216illustrated inFIG. 2B.

Generally, the host system1000can be substantially any system that works with the memory storage apparatus100to store data. Even though the host system1000is described as a computer system in the present exemplary embodiment, in another exemplary embodiment of the invention, the host system1000may also be a digital camera, a video camera, a communication device, an audio player, or a video player. For example, if the host system is a digital camera (video camera)1310, the rewritable non-volatile memory storage apparatus is then a secure digital (SD) card1312, a multimedia card (MMC) card1314, a memory stick (MS)1316, a compact flash (CF) card1318, or an embedded storage device1320(as shown inFIG. 2C) used by the digital camera (video camera)1310. The embedded storage device1320includes an embedded MMC (eMMC). It should be mentioned that the eMMC is directly coupled to the motherboard of a host system.

FIG. 3is a schematic block diagram of a memory storage apparatus according to an exemplary embodiment of the present invention.

Referring toFIG. 3, the memory storage apparatus100includes a connector102, a memory controller104, and a rewritable non-volatile memory module106.

In the present exemplary embodiment, the connector102complies with the serial advanced technology attachment (SATA) standard. However, the invention is not limited thereto, and the connector102may also comply with the parallel advanced technology attachment (PATA) standard, the Institute of Electrical and Electronic Engineers (IEEE) 1394 standard, the peripheral component interconnect (PCI) express standard, the universal serial bus (USB) standard, the SD interface standard, the MS interface standard, the MMC interface standard, the CF interface standard, the integrated device electronics (IDE) standard or any other suitable standard.

The memory controller104executes a plurality of logic gates or control instructions implemented in a hardware form or a firmware form and performs various data operations on the rewritable non-volatile memory module106according to commands issued by the host system1000.

The rewritable non-volatile memory module106is coupled to the memory controller104and has a plurality of physical blocks for storing data written by the host system1000. In the present exemplary embodiment, each of the physical blocks has a plurality of physical pages, wherein the physical pages belonging to the same physical block can be individually written but have to be erased all together. Each physical block may be composed of 128 physical pages. However, the invention is not limited thereto, and each physical block may also be composed of 64, 256, or any other number of physical pages.

To be specific, each of the physical blocks is the smallest unit for erasing data. Namely, each of the physical blocks contains the least number of memory cells that are erased all together. Each of physical pages is the smallest unit for programming data. Namely, each of the physical pages is the smallest unit for reading and writing data. However, in another exemplary embodiment, the smallest unit for writing data may also be sector or any other unit. Each physical page usually includes a data bit area and a redundant bit area. The data bit area is used for storing user data, and the redundant bit area is used for storing system data (for example, error checking and correcting (ECC) codes).

In the present exemplary embodiment, the rewritable non-volatile memory module106is a multi level cell (MLC) NAND flash memory module. However, the present invention is not limited thereto, and the rewritable non-volatile memory module106may also be a single level cell (SLC) NAND flash memory module, any other flash memory module, or any other memory module having the same characteristics.

FIG. 4is a schematic block diagram of a memory controller according to an exemplary embodiment of the present invention.

Referring toFIG. 4, the memory controller104includes a memory management circuit202, a host interface204, a memory interface206, a temporary data processing circuit208, and a buffer memory210.

The memory management circuit202controls the overall operation of the memory controller104. To be specific, the memory management circuit202has a plurality of control instructions, and when the memory storage apparatus100is in operation, the control instructions are executed to perform various data operations, such as a writing operation, an erasing operation, a reading operation and so on.

In the present exemplary embodiment, the control instructions of the memory management circuit202are implemented in a firmware form. For example, the memory management circuit202has a microprocessor unit (not shown) and a read-only memory (ROM, not shown), and the control instructions are burnt into the ROM. When the memory storage apparatus100is in operation, the control instructions are executed by the microprocessor unit.

In another exemplary embodiment of the invention, the control instructions of the memory management circuit202may also be stored in a specific area of the rewritable non-volatile memory module106(for example, a system area exclusively used for storing system data in a memory module) as program codes. In addition, the memory management circuit202has a microprocessor unit (not shown), a ROM (not shown), and a RAM (not shown). In particular, the ROM has a driving code, and when the memory controller104is enabled, the microprocessor unit first executes the driving code to load these control instructions from the rewritable non-volatile memory module106into the RAM of the memory management circuit202, and then executes these control instructions. Moreover, in yet another exemplary embodiment of the present invention, the control instructions of the memory management circuit202may also be implemented in a hardware form.

The host interface204is coupled to the connector102and the memory management circuit202and configured to receive and identify commands and data from the host system1000. Namely, commands and data transmitted by the host system1000are transmitted to the memory management circuit202through the host interface204. In the present exemplary embodiment, the host interface204complies with the SATA standard. However, the invention is not limited thereto, and the host interface204may also comply with the PATA standard, the IEEE 1394 standard, the PCI express standard, the USB standard, the SD standard, the MS standard, the MMC standard, the CF standard, the IDE standard, or any other suitable data transmission standard.

The memory interface206is coupled to the memory management circuit202and configured to access the rewritable non-volatile memory module106. Namely, data to be written into the rewritable non-volatile memory module106is converted by the memory interface206into a format acceptable to the rewritable non-volatile memory module106.

The temporary data processing circuit208is coupled to the buffer memory210and the memory management circuit202. The temporary data processing circuit208stores data to be temporarily stored by the memory management circuit202into the buffer memory210and reads data to be read by the memory management circuit202from the buffer memory210.

The buffer memory210is coupled to the memory management circuit202and configured to temporarily store data and commands from the host system1000or data from the rewritable non-volatile memory module106. In particular, the temporary data processing circuit208temporarily stores memory management tables (for example, a logical block-physical block mapping table) used for managing the rewritable non-volatile memory module106into the buffer memory210.

In addition, in the present exemplary embodiment, the memory controller104may further includes a power management circuit212and an error checking and correcting (ECC) circuit214. The power management circuit212is coupled to the memory management circuit202and configured to manage the power supply of the memory storage apparatus100.

The ECC circuit214is coupled to the memory management circuit202and configured to execute an ECC procedure to ensure data accuracy. To be specific, when the memory management circuit202receives a write command from the host system1000, the ECC circuit214generates a corresponding ECC code for the data corresponding to the write command, and the memory management circuit202writes both the data corresponding to the write command and the corresponding ECC code into the rewritable non-volatile memory module106. Subsequently, when the memory management circuit202reads the data from the rewritable non-volatile memory module106, it also reads the ECC code corresponding to the data, and the ECC circuit214executes the ECC procedure on the data according to the ECC code.

FIG. 5andFIG. 6are diagrams of managing physical blocks of a rewritable non-volatile memory module according to an exemplary embodiment of the present invention.

Referring toFIG. 5, the rewritable non-volatile memory module106has physical blocks310(0)-310(R), and the memory management circuit202of the memory controller104logically groups the physical blocks310(0)-310-(R) into a data area502, a free area504, a system area506, and a replacement area508.

Physical blocks logically belonging to the data area502and the free area504are used for storing data from the host system1000. To be specific, the physical blocks in the data area502are considered physical blocks already containing data, and the physical blocks in the free area504are used for substituting the physical blocks in the data area502. Namely, when a write command and new data, which is used to update old data stored in a physical block of the data area502, are received from the host system1000, the memory management circuit202selects a physical block from the free area504and writes the new data into the selected physical block to substitute the physical block of the data area502.

Physical blocks logically belonging to the system area506are used for recording system data, such as the manufacturer and model of the rewritable non-volatile memory module, the number of physical blocks in the rewritable non-volatile memory module, and the number of physical pages in each physical block.

Physical blocks logically belonging to the replacement area508are used for replacing damaged physical blocks. To be specific, if there are still normal physical blocks in the replacement area508and a physical block in the data area502is damaged, the memory management circuit202selects a normal physical block from the replacement area508to replace the damaged physical block.

It should be mentioned that in the present exemplary embodiment, the memory management circuit202manages the rewritable non-volatile memory module106in units of each physical block. However, the present invention is not limited thereto, and in another exemplary embodiment, the memory management circuit202may also group the physical blocks into a plurality of physical units and manages the rewritable non-volatile memory module106in units of each physical unit. Each physical unit may be composed of a plurality of physical blocks in a single sub memory module or different sub memory modules.

Particularly, the numbers of physical blocks in the data area502, the free area504, the system area506, and the replacement area508vary with different memory specifications. In addition, it should be understood that during the operation of the memory storage apparatus100, the physical blocks associated with the data area502, the free area504, the system area506, and the replacement area508are dynamically changed. For example, when a physical block in the free area504is damaged and accordingly replaced by a physical block in the replacement area508, the physical block originally in the replacement area508is associated with the free area504.

Referring toFIG. 6, as described above, the physical blocks in the data area502and the free area504are alternatively used for storing data written by the host system1000. In the present exemplary embodiment, the memory management circuit202configures logical blocks510(0)-510(H) for mapping to foregoing physical blocks that are alternatively used for storing data, and the memory management circuit202maps logical pages in the logical blocks510(0)-510(H) to logical access addresses accessed by the host system1000to allow the host system1000to access data.

For example, the memory management circuit202initially maps the logical blocks510(0)-510(H) to the physical blocks in the data area502. To be specific, after the memory storage apparatus100is manufactured, the logical blocks510(0)-510(H) are respectively mapped to the physical blocks310(0)-310(D) in the data area502. Namely, one logical block is mapped to one physical block in the data area502. The memory management circuit202establishes a logical block-physical block mapping table to record the mapping relationship between the logical blocks and the physical blocks. Namely, the memory management circuit202converts a logical access address to be accessed by the host system1000into logical pages of the corresponding logical block and accesses data in the corresponding physical block based on the logical block-physical block mapping table.

As described above, when the memory management circuit202of the memory controller104manages the rewritable non-volatile memory module106, it uses many memory management tables, such as the logical block-physical block mapping table recording the mapping relationship between the logical blocks510(0)-510(H) and the physical blocks in the data area502, a free area physical block table recording the physical blocks in the free area504, a replacement area physical block table recording the physical blocks in the replacement area508, a system area physical block table recording the physical blocks in the system area506, a bad block table recording damaged physical blocks, and an erasing count table recording the number of times each physical block is erased.

Generally, before the memory storage apparatus100is turned off, the memory management circuit202stores the latest memory management tables back into the rewritable non-volatile memory module106. Besides, when the memory storage apparatus100is in operation, the memory management circuit202loads the memory management tables from the rewritable non-volatile memory module106, and the temporary data processing circuit208temporarily stores these memory management tables into the buffer memory210so that these memory management tables can be instantly updated.

It should be noted that each memory management table is composed of a plurality of entries, and each of the entries includes a plurality of bits. To be specific, a microprocessor unit of the memory management circuit202temporarily stores data into the buffer memory210and reads data from the buffer memory210in fixed unit. For example, data is accessed in unit of byte (i.e., 8 bits). Thus, each entry is design to have a fixed size. However, because different memory management tables may have different sizes, the memory management circuit202uses only some of the bits in each entry for storing valid data and fills up the other bits with invalid bit data (for example, ‘0’). Herein the bits in each entry that are not used for storing valid data are referred to as invalid bits. Thus, in the present exemplary embodiment, each entry contains at least one invalid bit and all the entries have the same data pattern in one memory management table. Namely, specific bits in each entry of a memory management table are invalid bits.

FIG. 7is a diagram illustrating memory management tables and corresponding areas in a buffer memory according to an exemplary embodiment of the present invention.

Referring toFIG. 7, herein it is assumed that the memory management circuit202manages the rewritable non-volatile memory module106by using a first memory management table600(for example, a logical block-physical block mapping table) and a second memory management table610(for example, a bad block table), and the first memory management table600and the second memory management table610are stored in the system area506of the rewritable non-volatile memory module106. However, in another exemplary embodiment of the present invention, the first memory management table600and the second memory management table610may also be stored in the data area502of the rewritable non-volatile memory module106. Additionally, even though two memory management tables are described in the present exemplary embodiment, the number of memory management tables is not limited in the present invention.

The first memory management table600and the second memory management table610respectively include a plurality of entries, and each of the entries is composed of a plurality of bits. The memory management circuit202records data on each bit. For example, the first memory management table600includes an entry601and an entry602, and the second memory management table610includes an entry611and an entry612. In particular, all the entries in the first memory management table600have the same number of bits and contain invalid bits at same positions. For example, both the entry601and the entry602have 8 bits, and the 0th, 4thand 6thbits thereof are invalid bits (as indicated inFIG. 7with diagonal lines). Both the entry611and the entry612have 8 bits, and the 1st, 3rd, 4th, and 6thbits thereof are invalid bits (as indicated inFIG. 7with diagonal lines). Even though each memory management table includes two entries in the present exemplary embodiment, the present invention is not limited thereto, and in another exemplary embodiment of the present invention, each memory management table may include more entries. Moreover, even though each entry has 8 bits (i.e., one byte) in the present exemplary embodiment, the size of each entry is not limited in the present invention. For example, an entry may also have two bytes, four bytes, or some other sizes.

In the present exemplary embodiment, the temporary data processing circuit208configures a first area630and a second area640respectively corresponding to the first memory management table600and the second memory management table610in the buffer memory210. In other words, the temporary data processing circuit208divides a portion of the buffer memory210into the first area630for the first memory management table600and the second area640for second memory management table610. And, the temporary data processing circuit208respectively records invalid bit information corresponding to the first memory management table600and invalid bit information corresponding to the second memory management table610, wherein the invalid bit information records the invalid bits in each entry of a memory management table.

In particular, when the memory management circuit202is about to load the first memory management table600into the buffer memory210, the temporary data processing circuit208writes the entries belonging to the first memory management table600into the first area630of the buffer memory210. Similarly, when the memory management circuit202is about to load the second memory management table610into the buffer memory210, the temporary data processing circuit208writes the entries belonging to the second memory management table610into the second area640of the buffer memory210. Namely, the first area630is used for storing only entries belonging to the first memory management table600, while the second area640is used for storing only entries belonging to the second memory management table610. It should be mentioned that in the present exemplary embodiment, two areas are configured in the buffer memory210for respectively storing the memory management tables. However, the present invention is not limited thereto, and in another exemplary embodiment of the present invention, more areas are configured when the number of memory management tables increases, or if there is only one memory management table, only one area is configured for storing the memory management table.

It should be mentioned that while writing the entries belonging to a memory management table into a buffer memory, it is a waste of the limited storage space of the buffer memory210if the invalid bits are written into the buffer memory. In the present exemplary embodiment, the temporary data processing circuit208first removes invalid bit data from each entry and then stores the entries without the invalid bit data (referred to as valid data streams thereinafter) into the buffer memory210, so as to avoid waste of the storage space of the buffer memory.

To be specific, the temporary data processing circuit208identifies the memory management table corresponding to a data stream to be temporarily stored into the buffer memory210and removes invalid bit data from the data stream according to the invalid bit information corresponding to the memory management table. After that, the temporary data processing circuit208writes the valid data stream without the invalid bit data into the buffer memory210.

Contrarily, while reading data from the buffer memory210, the temporary data processing circuit208first identifies the memory management table corresponding to a data stream and then restores the data stream into an original entry (by adding the invalid bit data back into the data stream) according to the invalid bit information corresponding to the memory management table. Thereafter, the temporary data processing circuit208sends the restored entry to the memory management circuit202.

FIG. 8is a diagram of processing a data stream of a memory management table according to an exemplary embodiment of the present invention. Herein it is assumed that only the entry601of the first memory management table600is accessed in the buffer memory210. However, this processing method is also applicable when other entries belonging to the first memory management table600or entries belonging to other memory management tables are accessed in the buffer memory210.

Referring toFIG. 8, when the entry601of the first memory management table600is to be stored into the buffer memory210, the memory management circuit202writes the entry601into the buffer memory210through the temporary data processing circuit208.

To be specific, the temporary data processing circuit208removes data on the 0th, 4thand 6thbits (i.e., the invalid bit data) from the entry601according to the invalid bit information corresponding to the first memory management table600, so as to generate a valid data stream803corresponding to the entry601of the first memory management table600and stores the valid data stream803into the first area630of the buffer memory210.

In addition, when the entry601of the first memory management table600is to be read from the buffer memory210, the memory management circuit202reads the entry601from the buffer memory210through the temporary data processing circuit208.

To be specific, the temporary data processing circuit208reads the valid data stream803and adds the corresponding invalid bit data into the valid data stream803according to the invalid bit information corresponding to the first memory management table600so as to restore the entry601of the first memory management table600. Thereafter, the temporary data processing circuit208sends the restored entry to the memory management circuit202.

As described above, the storage space for storing memory management tables in the buffer memory210can be effectively reduced by removing invalid bit data from data streams by using the temporary data processing circuit208. For example, in the present exemplary embodiment, each entry of the first memory management table600has 8 bits and 3 of which are invalid bits. Thus, 37.5% less storage space of the buffer memory210is used for storing the first memory management table600.

FIG. 9is a flowchart of writing a data stream corresponding to an entry belonging to a memory management table into a buffer memory according to an exemplary embodiment of the invention.

Referring toFIG. 9, first, in step S901, an entry is received from the memory management circuit202, and whether the received entry belongs to the first memory management table600or the second memory management table610is determined.

If the entry received from the memory management circuit202belongs to the first memory management table600, in step S903, the temporary data processing circuit208removes invalid bit data from the entry according to the invalid bit information corresponding to the first memory management table600, so as to generate a valid data stream. Besides, in step S905, the temporary data processing circuit208stores the valid data stream into the first area630corresponding to the first memory management table600.

If the entry received from the memory management circuit202belongs to the second memory management table610, in step S907, the temporary data processing circuit208removes invalid bit data from the entry according to the invalid bit information corresponding to the second memory management table610, so as to generate a valid data stream. Besides in step S909, the temporary data processing circuit208stores the valid data stream into the second area640corresponding to the second memory management table610.

FIG. 10is a flowchart of reading a data stream corresponding to an entry belonging to a memory management table from a buffer memory according to an exemplary embodiment of the invention.

Referring toFIG. 10, first, in step S1001, the temporary data processing circuit208determines whether the data stream to be read by the memory management circuit202belongs to the first memory management table600or the second memory management table610.

If the entry to be read by the memory management circuit202belongs to the first memory management table600, in step S1003, the temporary data processing circuit208reads the data stream from the first area630of the buffer memory210. Besides, in step S1005, the temporary data processing circuit208restores the data stream back into an original entry according to the invalid bit information corresponding to the first memory management table600. After that, in step S1007, the temporary data processing circuit208sends the restored entry to the memory management circuit202.

If the entry to be read by the memory management circuit202belongs to the second memory management table610, in step S1009, the temporary data processing circuit208reads the data stream from the second area640of the buffer memory210. Besides, in step S1011, the temporary data processing circuit208restores the data stream back into an original entry according to the invalid bit information corresponding to the second memory management table610. After that, step S1007is executed.

It should be mentioned that in the present exemplary embodiment, the memory management tables are stored in the buffer memory. However, the invention is not limited thereto, and in another exemplary embodiment of the invention, the memory management tables may also be stored in another memory (for example, a flash memory) in the same way.

In summary, exemplary embodiments of the invention provide a memory management table processing method, a memory controller, and a memory storage apparatus, in which while writing an entry belonging to a memory management table into a buffer memory, the memory management table corresponding to the entry is first determined, invalid bit data is then removed from the entry accordingly, and eventually, the entry is written into a specific area of the buffer memory. Thereby, the memory management table processing method, the memory controller, and the memory storage apparatus provided by exemplary embodiments of the invention can effectively reduce the storage space to be used in the buffer memory. The previously described exemplary embodiments of the present invention have the advantages aforementioned, wherein the advantages aforementioned not required in all versions of the invention.