High voltage circuits implemented using low voltage transistors

Transistors of low voltage specification are used to process information in a signal received at a high(er) voltage level. A protection circuit ensures that the cross terminal voltages do not exceed an allowed maximum voltage (e.g., 2.4 V for transistors of 1.8V specification). In an embodiment, the protection circuit contains a PMOS transistor which turns off if a protected cross terminal voltage exceeds such allowed maximum voltage. As a result, protection may be provided while consuming minimal power. The protection circuit may be employed in various types of circuits such as input buffers and logic gates. The protection circuits and the input buffers may potentially be implemented using transistors of a single voltage specification.

BACKGROUND OF INVENTION

1. Field of the Invention

The present invention relates to integrated circuits, and more specifically to high voltage circuits implemented using low voltage transistors of reduced number of voltage specifications.

2. Related Art

Integrated circuits are generally provided a supply voltage, and it is some times desirable that a high (compared to voltage specification of a transistor, as described below) voltage be provided for the supply voltage. For example, using a high supply voltage generally provides a correspondingly high signal to noise ratio (SNR), typically leading to less susceptibility to noise in processing input signals. Integrated circuits with high supply voltage may be referred to as high voltage circuits.

Transistors are characterized by associated ideal maximum permissible cross terminal voltages, and such voltages are generally referred to as the voltage specification for the corresponding transistors. For example, it is generally desirable to keep the ideal maximum cross terminal voltage of a 1.8V transistor below 1.8V, even though up to 2.4V is often applied across the terminals of the 1.8V transistor, in which case there is some exposure to reducing the life-time of the transistor, etc. The 2.4V limit may be referred to as allowed maximum voltage.

It is often desirable to implement high voltage circuits using transistors (“low voltage transistors”) of low(er) voltage specification. In general, using low voltage transistors provides benefits such as high throughput performance, reduced electrical power consumption, and high density (number of integrated circuits in a unit area). What is therefore needed is a method and apparatus to implement high voltage circuits using low voltage transistors.

DETAILED DESCRIPTION

An aspect of the present invention enables low voltage transistors (transistor of low voltage specification) to process input signals which can be at a high voltage level (higher than the voltage specification of the low voltage transistors) while reducing electrical power consumption. The low voltage transistors may operate with high voltage input signals by providing a protection circuit which ensures that the cross terminal voltages of the low voltage transistors do not exceed a corresponding allowed maximum voltage.

The electrical power consumption may be reduced since the protection circuit may be implemented using transistors which turn off while avoiding exposure of the low voltage transistors to higher than permissible voltage range. The transistors of the protection circuit may also be implemented using transistors of the same voltage specification as the low voltage transistors, thereby reducing the manufacturing complexities and costs.

The approaches of above may be used to implement various types of embodiments. Some example embodiments are described below.

In an embodiment operating as an input buffer receiving an input signal of a first/high voltage level, a first transistor of the second/low voltage specification is protected by a second transistor, with the drain terminal of the second transistor being connected to receive the high voltage input signal and the gate terminal of the second transistor being connected to a bias voltage. The source terminal of the second transistor may be connected to the drain terminal of the first transistor.

Due to such a topology, the second transistor is turned off in some situations to ensure that the low voltage first transistor is not exposed to cross terminal voltages exceeding a corresponding allowed maximum voltage limit. Thus, the second transistor operates as a protection circuit for the first transistor.

The protection circuit may further contain a third transistor with the gate terminal of the third transistor being connected to the bias voltage, and the source terminal of the third transistor being connected to the gate terminal of the first transistor. Due to such connections, the first transistor receives the input signal when the second transistor is off, but the first transistor is not exposed to excessive voltage levels.

An aspect of the present invention enables an input buffer to process input signals of different higher voltage levels merely by changing the supply voltage to the corresponding voltage level. Thus, in an embodiment requiring processing of two input signals of two different high (compared to the voltage specification of the transistors) voltage levels, one input buffer may be connected to a supply voltage equaling the first high voltage and the second input buffer may be connected to a supply voltage equaling the second high voltage, and both input buffers may be implemented using transistors of the same (low) voltage specification.

Such features of an input buffer may be implemented using eight transistors of the same low voltage specification, with four transistors being coupled to operate as an input buffer and the remaining four transistors operating as a protection circuit.

Another aspect of the present invention provides an input buffer and a core module implemented using transistors of a single voltage specification, but processing input signals of higher voltage levels. Due to the use of transistors of single voltage specification, the fabrication complexity and cost can be reduced.

Yet another aspect of the present invention enables implementation of logic gates, which also use transistors of lower voltage specification compared to the voltage of an input signal. A logic gate thus provided may operate on a first input signal which is at a reference voltage to represent one logic value and a first voltage level to represent another logic value. The logic gate may contain multiple transistors coupled to perform the logic operation using the first input, with the transistors being of a voltage specification of a second voltage level, wherein the second voltage level is less than the first voltage level. A protection circuit prevents voltages exceeding an allowed maximum voltage from being applied across any of the transistors.

The logic gate may be implemented in the form of a set of PMOS transistors and a set of NMOS transistors, and an embodiment of the protection circuit may contain a first NMOS transistor and a first PMOS transistor. The source terminal of each of the set of PMOS transistors may be coupled to a supply voltage and the source terminal of each of the set of NMOS terminals may be coupled to the reference voltage. The source terminal of the first PMOS transistor may be connected to the drain terminal of at least one of the set of PMOS transistors, and the source terminal of the first NMOS transistor may be connected to the drain terminal of at least one of the set of NMOS transistors.

The logic gate may further include a swing split circuit receiving the first input signal and generating a first swing signal and a second swing signal. Each swing signal may have a lower swing (voltage difference between high logic level and low logic level) compared to a swing of the first input signal. The first swing signal may be connected to the gate terminal of at least one of the set of PMOS transistors and the second swing signal may be connected to the gate terminal of at least one of the set of NMOS transistors.

2. Example Integrated Circuit

FIG. 1Ais a block diagram of an integrated circuit in which several aspects of the present invention may be implemented. Integrated circuit100is shown containing input buffer110, core module120, pre-driver140and output buffer150. Each block is described below in further detail.

Input buffer110may be implemented using transistors of a voltage specification, which is low compared to the voltage level of input signals received on bus111. In the description herein, the voltage level of the input signals is conveniently referred to as a high voltage level and the voltage specification of the transistors as a low voltage level.

Input buffer110receives an input signal on bus111and provides the received input signals on bus112with a desired voltage level consistent with the requirements of core module120. In general, the input signal contains information. The information can be digital (in which case logic level represented is usually of interest) or analog (in which case the changes can be continuous), even though the circuits are described substantially with respect to digital input signals.

Input buffer110also receives high voltage supply (HVDD) and low voltage supply (LVDD) respectively on paths101and102(path102shown as two different lines connecting to input buffers110and130respectively). The voltage level of each of HVDD101and LVDD102is with respect to a reference voltage (Vss) received on path103. In the present application, various embodiments are described assuming that the voltage level of HVDD101is greater than that of LVDD102.

Core module120and input buffer110may be implemented with transistors of same single voltage specification equaling LVDD102, thereby reducing manufacturing complexity and costs. The manner in which such an implementation may be attained is described in sections below in further detail.

Pre-driver140receives input signals from core module120with low voltage swing and generates output signals with desired strength to output buffer150. Pre-driver140may also be implemented with low voltage transistors. Logic gate (for example, NAND gate) can be used as a pre-driver). Output buffer150provides the output signals to external systems/components. The output signals can be of low or high voltage level. The details of an embodiment of pre-driver are described in a section below in further detail.

Input buffer110may be designed to receive input signals of any of multiple voltage levels (e.g., 3.3V, 2.5V, 1.8V, etc.) merely by changing the supply voltage HVDD101to the corresponding voltage level. As a result, the same integrated circuit can be used in different environments and/or the same circuit topology of input buffer can be easily used to design/fabricate additional integrated circuits for such different environments. Such a feature may be conveniently used in a scenario when an integrated circuit needs to process input signals of two different high voltages as described below with reference toFIG. 1B.

With reference toFIG. 1B, integrated circuit199is shown containing input buffer130apart from the components ofFIG. 1A. Integrated circuit199receives two input signals on paths111and133from respective external sources, each with different voltage swing. Input signal111is assumed to be changed with a voltage swing of HVDD101and input signal133is assumed to be changed with a voltage swing of another higher supply voltage HVDD2 received on path104.

Input buffer130receives input signal on path133of another high voltage level (i.e., different than input signal111) and generates a signal with a desired voltage level on path132for further processing in core module120. Input buffer130receives HVDD2on path104and also LVDD102. Input buffer130may be implemented similar to input buffer110.

In an embodiment, input buffers110and130are implemented with transistors of same voltage specification of transistors of voltage specification of core module120. Therefore, due to the use of transistors of a single voltage specification, the fabrication complexity and cost can be reduced.

In an alternative embodiment, input buffer110and core module120are implemented using transistors of same voltage specification and input buffer130with transistors of different voltage specification. Thus, integrated circuit199can be implemented using transistors of only two different voltage specifications, thereby leading to lower fabrication cost/complexity compared to embodiments using three different voltage specifications.

In addition, input buffers provide the received input signals to core module120(even if input signals are received at a voltage higher than LVDD102) with a voltage level of LVDD102without exposing the transistors in input buffers to voltage levels exceeding the corresponding allowed maximum voltages. An example embodiment of such an input buffer is described in sections below with reference toFIG. 2.

It may be helpful to first understand the details of a prior input buffer, which does not include one or more features of the present invention. Accordingly, prior input buffers are described below with reference toFIGS. 1C and 1D.

3. Prior Input Buffers

FIGS. 1C and 1Dare circuit diagrams, each illustrating the details of an embodiment of a prior input buffer. Input buffer180ofFIG. 1Cis shown containing NMOS transistors160and170, and PMOS transistor165. Each component is described below.

Transistors165and170together operate as an inverter. The source terminal of transistor165receives low voltage supply LVDD102and the source terminal of transistor170receives Vss103.

NMOS transistor160protects transistors165and170from receiving high voltage input. The drain terminal of transistor160receives input signal of high voltage level on path111and the gate terminal of transistor160is connected to receive bias voltage on path166. Transistor160turns off when input signal111is at high voltage level and causes the voltage on path167equaling (bias voltage166−threshold voltage (Vt) of transistor160), wherein ‘−’ represents a subtraction arithmetic operation. As a result, transistors165and170do not receive high voltage input. Transistor160turns on when input signal111is at low voltage level (representing logic 0) and thus same voltage would appear on path167.

With reference toFIG. 1D, input buffer190is shown containing all the components ofFIG. 1Cand PMOS transistor175. Transistor175ensures complete turn off of transistor165. Transistor175turns on if transistor165does not turn off completely, which causes the voltage on path167to be pulled to LVDD102. As a result, transistor165turns off completely.

One problem with the input buffers ofFIGS. 1C and 1Dis that lower (below which the input signal is deemed to represent a logic 0) and upper (above which the input signal is deemed to represent a logic 1) threshold voltage specifications may be hard to achieve. For example, the input buffers ofFIGS. 1C and 1Dmay violate lower and upper threshold voltages of standards such as JEDEC (available at http://www.jedec.org/).

The description is continued with reference to an embodiment of an input buffer according to various aspects of the present invention.

4. Input Buffer

FIG. 2is a block diagram illustrating the logical view of input buffer110in an embodiment of the present invention. Input buffer110is shown containing bus holder240and level shifter250. Bus holder240is further shown containing inverters210and220, and protection circuit230. Each component is described in further detail below.

Bus holder240holds the received input signal on path201and provides the same input signal on path235even if input signal on path201turns to an invalid level (after providing the input signal level). For example, if input signal on path201may transition to a high impedance (which is invalid logic level), bus holder240holds the previous logic level and provides the same on path235for further processing. By holding the logic level, the implementation of core module120may generally be simplified. Path201is contained in bus111ofFIG. 1.

As noted above, bus holder240is shown containing protection circuit230, in addition to inverters210and220. A pair of inverters can be coupled to operate as a bus holder, as is well known in the relevant arts. According to an aspect of the present invention, inverters210and220are implemented using transistors of a low voltage specification, and protection circuit230operates to ensure that such transistors are not exposed to voltages exceeding the corresponding allowed maximum voltage. Example implementation of bus holder240is described below with reference toFIG. 3in further detail.

Level shifter250changes/shifts the voltage level of the signal received on path235and provides the level shifted signal on path299. Path299is contained in bus112ofFIG. 1. In an embodiment, level shifter250provides the level shifted signal on path299with voltage levels equaling LVDD102and Vss103corresponding to the respective two logic levels. In an embodiment, level shifter250performs inverting operation and bus holder240also performs inverting operation, as a result, the output on path299represents the same logic level of input signal201but with a shift in the voltage level. Example embodiments of level shifter250are described in sections below in further detail. The description is continued with reference to an example implementation of input buffer110using transistors.

5. Details of Input Buffer

FIG. 3is a circuit diagram illustrating the details of input buffer110in an embodiment of the present invention. Input buffer110is shown containing PMOS transistors310,330,355,360,365and370, NMOS transistors320,340,345,350and375, and counter-leakage circuits380-1through380-4. Each component is described in detail below.

Transistors350and360together operate as inverter210, and transistors345and355together operate as inverter220. Transistors345and355may be implemented with small width/length (W/L) compared to transistors350and360since inverter220(in the feedback path) generally needs to provide a low drive strength. Transistors310,320,330and340together operate as protection circuit230. Transistors365,370and375form level shifter250. In an embodiment, all the transistors of input buffer110are of the same voltage specification, which is lower than the voltage level of the input signal received on path201.

The drain terminal of each transistor310and320is connected to receive an input signal of high voltage level on path201. The source terminal of transistor320is connected to the drain terminal of transistor345and the gate terminal of transistor350at a first node. The gate terminal of each of transistor320and transistor340is connected to receive a bias voltage BIASN on path324. The source terminal of each transistor345and350is connected to Vss103. The drain terminal of transistor350is connected to the source terminal of transistor340and the gate terminal of transistor345at a second node.

The drain terminal of transistor340is connected to the drain terminal of transistor330. The gate terminal of each transistor310and330is connected to receive a bias voltage BIASP on path313. The source terminal of transistor310is connected to the drain terminal of transistor355and the gate terminal of transistor360at a third node. The source terminal of transistor330is connected to the drain terminal of transistor360and the gate terminal of transistor355at a fourth node. The source terminal of each of transistor355and transistor360is connected to HVDD101.

The bulk terminal of each of transistor355, transistor360, transistor310and transistor330is connected to the corresponding source terminal. However, the bulk terminals of transistors310and330can be connected to HVDD101in alternative embodiments. The bulk terminals of transistors310and330are connected to nodes231and213respectively so as to improve Vt by eliminating the body effect. Body effect generally refers to the increase in Vt when the source terminal of a PMOS transistor is at lower voltage than that at substrate. An increase in Vt reduces the throughput performance, and therefore elimination of body effect is desirable.

The operation of each transistor is described below with reference to the manner in which each transistor is not exposed to cross terminal voltages exceeding an allowed maximum voltage in the case of both transitions (0 to 1, and 1 to 0). For illustration, it is assumed that the voltage level corresponding to logic 1 equals HVDD and logic 0 equals Vss.

It is helpful to first appreciate that transistors320,330,345and360are in an OFF state and transistors310,340,350and355are in an ON state when the input signal is at 1. Similarly, transistors320,330,345and360are in an ON state and transistors310,340,350and355are in an OFF state when input signal201is at logic 0. In addition, in the steady state of 1 on input signal, nodes223,232,213and231are respectively at voltage levels (BIASN−Vt of transistor320), Vss103, (BIASP+Vt of transistor330) and HVDD.

Similarly, in the steady state of 0 on the input signal, nodes223,232,213and231are respectively at voltage levels Vss103, (BIASN−Vt of transistor340), HVDD and (BIASP+Vt of transistor310). Both at the steady state and during the transitions, the transistors are not exposed to cross terminal voltages exceeding allowed maximum voltage, as described below briefly.

The description is continued with respect to state changes when the input signal transitions to 1, and the manner in which transistors (forming input buffer) may be protected by the protection circuit.

6. Protection when Input Signal Transitions to Logic 1

FIG. 4Ais a table illustrating the details of voltages at cross terminals of each of the transistors forming input buffer110when the input signal transitions to logic 1. The table is shown containing the voltages across only terminals that need to be protected, and the voltages across the remaining terminals are not shown in the interest of conciseness. The manner in which the transistors may be protected when input signal transitions to logic 1 is described below with reference toFIGS. 3 and 4A.

Transistor320turns off when input signal201transitions to logic 1 (HVDD) and voltage at node223reaches BIASN−Vt (of transistor320). Voltage at node223would have been at Vss when input signal was at logic 0, and raises from Vss to (BIASN−Vt of transistor320) since HVDD provided at drain terminal of transistor320causes current to flow through transistor320.

Even though the voltage at node223initially (responsive to input signal being at logic 0) is at Vss (which causes the drain to source voltage across transistor320to equal high voltage of HVDD), the voltage raises to (BIASN−Vt) within a short duration along with the transition of input signal to logic 1. As a result, the drain to source voltage across transistor320may not be exposed to high voltage.

Transistor345may be protected due to the turning off of transistor320. In particular, the drain to source voltage (Vds) across transistor345would not be greater than (BIASN−Vt of transistor320), and thus transistor345is protected as summarized in row410-1ofFIG. 4A. By appropriate choice of value for BIASN (and perhaps Vt), the range of voltages for input signals and/or the desired voltage specification for transistor345can be determined. The drain to gate voltage (Vdg) across transistor345would also not be greater than (BIASN−Vt of transistor320), and thus transistor345is protected as summarized in row410-2ofFIG. 4A(assuming Vss=0).

Transistor350is also protected from exposure to excessively high cross terminal voltages due to the turning off of transistor320. In particular, gate to source voltage (Vgs) and Vdg across transistor350would also not be exposed to a voltage greater than (BIASN−Vt) as summarized in rows410-3and410-4respectively ofFIG. 4A.

Transistor330turns off when input signal is at logic 1 and voltage at node231reaches HVDD. HVDD on path201causes current to flow through transistor310, which in turn causes the voltage at node231to raise/increase from BIASP+Vt (of transistor310). The increase in voltage at node231causes transistor310to be turned on and transistor360to be turned off.

Transistor360is protected due to turning off of transistor330. In particular, each of Vds and Vdg across transistor360would not be greater than (HVDD−BIASP−Vt of transistor330), and this transistor360is protected as summarized in rows410-5and410-6respectively ofFIG. 4A.

Transistor355is also protected due to turning off of transistor330. In particular, Vgs and Vdg across transistor355would not be exposed to a voltage greater than (HVDD−BIASP−Vt of transistor330) as summarized in rows410-7and410-8respectively ofFIG. 4A. By appropriate choice of value for BIASP, the range of voltages for input signals and/or the desired voltage specification for transistors355and360can be determined.

Therefore, it may be appreciated that transistors345and350are protected due to turning off of transistor320and transistors355and360are protected due to turning off of transistor330. In addition, as the transistors in the protection circuit are off during protection, power consumption may be reduced.

The description is continued with respect to state changes when the input signal transitions to 0, and the manner in which transistors (forming input buffer) may be protected by the protection circuit.

7. Protection when Input Signal Transitions to Logic 0

FIG. 4Bis a table illustrating the details of voltages at cross terminals of each of the transistors forming input buffer110when input signal is at logic 0. The table is shown containing the voltages across terminals that need to be protected, and the voltages across the remaining terminals are not shown in the interest of conciseness. The manner in which the transistors may be protected when input signal transitions to logic 0 is described below with reference toFIGS. 3 and 4B.

Transistor340turns off when input signal201is at logic 0 and the voltage on node232reaches Vss. In particular, transistor320is turned on when input signal transitions to logic 0 since gate terminal of transistor320is connected to BIASN. The turning on of transistor320turns off transistor350, which causes transistor340to be turned off since no current flows through transistor340.

Transistor345is protected due to turning off of transistor340. In particular, Vgs and Vdg of transistor345would not be exposed to a voltage greater than (BIAS−Vt of transistor340-Vss) as summarized in rows430-1and430-2respectively ofFIG. 4B.

Transistor350is also protected due to turning off of transistor340. In particular, Vdg and Vds of transistor350would not be exposed to a voltage greater than (BIASN−Vt of transistor340-Vss), and thus transistor350is protected as summarized in rows430-3and430-4respectively ofFIG. 4B.

Transistor310turns off when input signal transitions to logic 0 since the voltage at node231is pulled towards Vss (logic 0). However, when voltage on node231reaches BIASP+Vt, transistor310turns off and thus does not allow node231to go below (BIASP+Vt of transistor310).

Transistor360is protected due to turning off of transistor310. In particular, Vgs and Vdg of transistor360would not be exposed to a voltage greater than (HVDD−BIASP−Vt of transistor310) as summarized in rows430-5and430-6respectively ofFIG. 4B.

Transistor355is also protected due to turning off of transistor310. In particular, Vds and Vdg of transistor355would not be exposed to a voltage greater than (HVDD−BIASP−Vt of transistor310) as summarized in rows430-7and430-8respectively ofFIG. 4B.

Therefore, it may also be appreciated that transistors345and350are protected due to turning off of transistor340and transistors355and360are protected due to turning off of transistor310.

It may be noted that the voltage levels of BIASN and BIASP are chosen such that the voltage across terminals of transistors does not exceed the allowed maximum voltage. In an embodiment, the voltage level of each of BIASN and BIASP equals half of HVDD101. For example, assuming that HVDD equals 3.3V and all the transistors are of 1.8V specification, then BIASN and BIASP equals 1.65V, which is less than the allowed maximum voltage of 2.4V of a 1.8V transistors.

However, BIASN can be chosen to be slightly greater than half of HVDD and BIASP can be chosen slightly lesser than half of HVDD such that the voltage swing of first intermediate signal and second intermediate signal on paths366and235would be large. While transistors310,320,330and340operate as a protection circuit as described above, transistors345,350,355and360together continue to operate as an input buffer as described below.

8. Operation as Input Buffer

When input signal carries logic 1, transistor350is turned on since the voltage (BIASN−Vt) at node223(due to turning off of transistor320) is applied to gate terminal of transistor350. As a result, node232is pulled to Vss, which causes transistor345to be tuned off and transistor340to be turned on since gate terminal of transistor340is connected to BIASN (324). As a result, the voltage on path235equals Vss, which represents logic 0. Since transistor340is turned on, the voltage at node334also equals Vss representing logic 0.

A logic 1 on input signal201causes transistor310to be turned on, which turns off transistor360. The turning off of transistor360causes the voltage on node213to be reduced from HVDD and causes transistor330to be turned off. As a result, the voltage on node213equals (BIASP+Vt of transistor330). The voltage (BIASP+Vt) on node213represents logic 0.

Therefore, when the input signal transitions to logic 1, the voltages on paths235,333and366respectively equals Vss, Vss and (BIASP+Vt), and each represents logic 0.

When input signal transitions to logic 0, transistor320is turned on, which turns off transistor350. The turning off of transistor350causes transistor340to be turned off since no current flows through transistor340. As a result, the voltage at node232(on path235) equals (BIASN−Vt of transistor340), which represents logic 1.

Continuing with input signal is at logic 0, the voltage (BIASP+Vt) at node231(due to turning off of transistor310) turns on transistor360and causes the voltage at node213to be pulled to HVDD101. The voltage at node213turns off transistor355, which in turn turns on transistor360completely. The voltage on node213turns on transistor330. As a result, the voltage equaling HVDD101is provided at node213, which represents logic 1. Since transistor330is turned on and transistor340is turned off, the voltage at node334also equals HVDD.

Therefore, when input signal transitions to logic 0, the voltages on paths235,333and366respectively equals BIASN−Vt, HVDD and HVDD, and each represents logic 1.

It may be observed that the voltage at node334(provided as a third intermediate signal on path333) switches between HVDD and Vss. The output at node334can be used to operate bus holder240as a high voltage inverter. Similarly, the voltage at node232(provided as a second intermediate signal on path235) switches between BIASN−Vt and Vss. The output at node232can be used as an input to level shifter250since the change in voltage levels is less than that of at node334. Similarly, the voltage at node213(provided as first intermediate signal on path366) switches between HVDD and BIASP+Vt, which may be used as an input signal as described in sections below. The change in voltage levels is also small at node213and thus the output at node213can be used as a low voltage inverter output.

It may be appreciated that input buffer110may not require a charged device model (CDM) clamp since input signals are received on a drain terminal of a transistor instead of a gate terminal. In general, when inputs are received on gate terminals, a CDM clamp may be required in input buffers to protect gate terminals of transistors not to receive unwanted inputs through electrostatic discharge (ESD) strike, as is well known in the relevant arts.

It may be further noted that the voltages at nodes231,213,232and223may go lower or higher than the desired voltage due to several factors. Some of such factors include sub-threshold leakage through off transistors, drain to bulk reverse biased diode, noise coupling via parasitic capacitance typically present at nodes, etc.

As an illustration, voltage at node231may fall below BIASP+Vt if (current due to the sub-threshold leakage of transistor310+current due to drain to bulk reverse biased diode of transistor310+current due to noise coupled via parasitic capacitance at node231) is less than the current due to the sub-threshold leakage through transistor355. Otherwise the voltage at node231may go above BIASP+Vt. Such changes in voltage levels may cause undesirably high voltage levels to be presented across terminals of transistors, which may reduce the life time of transistors.

In general, it should be appreciated that the circuit topology ofFIG. 3can be used to process input signals of different voltages by using the corresponding supply voltage and by selecting the transistors of appropriate W/L ratios. Such processing can be performed using low voltage transistors, as also described above.

In addition, the approaches described above provide greater control over the upper and low thresholds of the input signals since the size (W/L ratio) of transistors360and350can be adjusted to attain desired lower and upper thresholds. Such a feature enables the circuit ofFIG. 3to be adapted to the requirements of standards such as JEDEC, noted above. Furthermore, since the upper/lower specifications are generally specified with reference to supply voltage (HVDD101), the circuit ofFIG. 3advantageously tracks variations in the supply voltage since transistor360, connected to HVDD, controls (in combination with transistor350) the threshold voltages.

Counter-leakage circuits380-1through380-4may prevent respective nodes231,213,223and232from going below or above the desired voltage level. The manner in which counter-leakage circuits may be implemented according to several aspects of the present invention is described in sections below. The description is continued with reference to level shifting of the voltage on path235.

Transistors370and375receive the second intermediate signal on path235on respective gate terminals. When voltage on path235equals (BIASN−Vt) (logic 1), transistor375is on and transistor370is off, and the output on path299equals Vss103. When voltage on path235equals Vss (logic 0), transistor375is off and transistor370is on, and the output on path299equals LVDD102. Therefore, the voltage on path299switches between LVDD and Vss as desirable for the operation of core module120.

Transistor365prevents leakage when transistor370is not completely turned off. As an illustration, when voltage (BIASN−Vt) on path235corresponding to logic 1 is below LVDD, then transistor370will not turn off completely. In such a case, voltage on path299is less than LVDD, which turns on transistor365. The turning on of transistor365connects gate terminals of transistors370and375to LVDD, which turns off transistor370completely. However, transistor365itself causes leakage of current from HVDD101when voltage on path235is greater than LVDD+Vt (of transistor365). Such leakage may be reduced according to various aspects of the present invention as described below with reference toFIG. 4C.

FIG. 4Cis a circuit diagram illustrating the details of level shifter in an embodiment of the present invention. The structure of level shifter400is similar to the structures described in a paper entitled as “A Static Power Saving TTL_to_CMOS Input buffer”, authors: Changsik Yoo, Minimum_Kyu Kim, and Wonchan kim, published in IEEE J. Solid State Circuits, Vol 30, pp. 616—620, No. 5, May 1995, which are intended to reduce static power consumption. However, level shifter400changes the voltage level of the second intermediate signal received on path235while reducing leakage current as described below in further detail.

Level shifter400is shown containing PMOS transistors450,480and490, and NMOS transistors460and470. The gate terminal of transistor470and source terminals of transistors480and490are connected to LVDD102, and the drain terminals of transistor450and the source terminal of transistor460are connected to Vss103. The operation of each component is described with reference to the two logic levels of signal received on path235.

When voltage level of signal235equals BIASN−Vt (representing logic 1), transistor450turns off and transistor460turns on. The turning on of transistor460pulls path299to Vss, which represents logic 0, as desired. The pull on path299turns on transistor490, which turns off transistor480.

Transistor470ensures that transistor450is turned off completely, which may otherwise cause leakage. Transistor470is turned on since the gate terminal of transistor470is connected to LVDD102. The voltage at node475equals (LVDD−Vt of transistor470). Since the gate terminal of transistor460receives BIASN−Vt and the source terminal receives LVDD−Vt, transistor450remains off.

When voltage level of signal235equals Vss (representing logic 0), transistors450and470turn on and transistor460turns off, which causes transistor480to be turned on. The turning on of transistor480provides LVDD on path299, as desirable. LVDD on path299turns off transistor490.

It may be noted that the voltage on path299switches between LVDD and Vss as desirable, even though the voltage on path235switches between BIASN−Vt and Vss. It may be further noted that the transistors that receive signal on path235are not connected to LVDD and thus leakage may be prevented. For example, transistor450which is connected to path235, is not connected to LVDD. The description is continued with reference to several embodiments of counter-leakage circuits.

FIG. 5is a circuit diagram of bus holder240illustrating the details of an embodiment of counter-leakage circuits380-1through380-4according to several aspects of the present invention. Counter-leakage circuits380-1through380-4are shown containing NMOS transistors510and520, PMOS transistors530and540respectively. As described above, each counter-leakage circuit380-1through380-4prevents the voltages at respective nodes231,213,223and232from rising above or falling below the desired voltage level. Each component is described below.

Transistor510, connected at node231, may prevent the voltage at node231from falling below (BIAS1−Vt of transistor510). The gate terminal of transistor510is connected to BIAS1(generally a fixed voltage connected to the gate terminal of transistors510and520) received on path501. Source terminal and drain terminal of transistor510are connected respectively to node231and HVDD101. Transistor510turns on when voltage at node231falls below (BIAS1−Vt of transistor510).

The turning on of transistor510causes the voltage at node231to equal (BIAS1−Vt) and thus prevents the voltage at node231from falling below BIAS1−Vt. As a result, any leakage in transistor310in an off state (which may cause the voltage at node231to go below (BIASP+Vt)) is countered by current flow through transistor510. Similarly, transistor520connected at node213limits the voltage not to fall below (BIAS1−Vt of transistor520).

Transistor530, connected at node223, may prevent the voltage at node223from rising above (BIAS2+Vt of transistor530). Gate terminal of transistor530is connected to BIAS2received on path502. Source terminal and drain terminal of transistor530are connected respectively to node223and Vss103. Transistor530turns on when voltage at node223rises above (BIAS2+Vt of transistor530).

The turning on of transistor530causes the voltage at node223to equal (BIAS2+Vt) and thus prevents the voltage at node223from rising above (BIAS2+Vt). As a result, any leakage in transistor320in an off state (which may cause the voltage at node223to go above (BIASN−Vt)) is countered by current flow through transistor530. Similarly, transistor540connected at node232limits the voltage from rising above (BIAS2+Vt of transistor540).

The voltage level of BIAS1501and BIAS2502are selected such that the voltage across terminals of transistors connected to corresponding nodes does not exceed the allowed maximum voltage level. For example, each of BIAS1and BIAS2does not exceed the maximum allowed gate to bulk voltage limit (e.g., 2.4V for 1.8V transistor) of the transistors. By limiting the voltage levels at nodes231,213,223, and232, counter-leakage circuits380-1through380-4may counter-leakage due to various factors as described above.

It may be noted that counter-leakage circuits380-1through380-4may consume substantially low power since the transistors in counter-leakage circuits are turned on only when the voltage at a corresponding node falls below or rises above the desired voltage level. The description is continued with reference to an alternative embodiment of counter-leakage circuit.

11. Alternative Embodiment of Counter-leakage Circuit

FIG. 6is a circuit diagram containing bus holder240illustrating an embodiment of counter-leakage circuits380-1through380-4according to several aspects of the present invention. Counter-leakage circuits380-1through380-4are shown containing PMOS transistors610and620, NMOS transistors630and640respectively. As described above, each counter-leakage circuit380-1through380-4prevents the voltage at respective nodes231,213,223and232from rising above or falling below the desired voltage level. Each component is described below.

Transistor610, connected at node231, may prevent the voltage at node231from falling below (BIASP+Vt). Gate terminal and source terminal of transistor610are connected to HVDD101and drain terminal is connected to node231. As a result, transistor610is permanently off. The sub-threshold leakage current through transistor610increases if voltage at node231decreases below (BIASP+Vt). By appropriate design (e.g., large W/L) of transistor610, the sub-threshold leakage can be made to be sufficiently large to ensure that the voltage at node231does not fall below (BIASP+Vt). Similarly, transistor620connected at node213may prevent the voltage at node213from falling below (BIASP+Vt).

Transistor630is connected at node223may prevent the voltage at node223from rising above (BIASN−Vt). Gate terminal and source terminal of transistor630are connected to Vss103and drain terminal is connected to node223. As a result, transistor630is permanently off. The sub-threshold leakage current through transistor630increases if voltage at node223rises above (BIASN−Vt). Due to the sub-threshold leakage, the voltage at node223may no be allowed to rise above (BIASN−Vt). Similarly transistor640connected at node232may prevent the voltage at node232from rising above (BIASN−Vt).

It may be noted that counter-leakage circuits380-1through380-4may consume substantially low power since the transistors in counter-leakage circuits are permanently turned off. The description is continued with reference to an alternative embodiment of counter-leakage circuit.

12. Alternative Embodiment of Counter-leakage Circuit

FIGS. 7 and 8are circuit diagrams together illustrating the details of counter-leakage circuits380-1through380-4in one embodiment. In particular,FIG. 7is a circuit diagram illustrating the details of counter-leakage circuit380-3andFIG. 8is a circuit diagram illustrating the details of counter-leakage circuit380-1.

PMOS transistor710receives the signal at node223on source terminal, and BIAS1voltage on gate terminal701(similar to BIAS1on path501). In an embodiment, BIAS1equals (BIASN−|vt| of transistor320), (wherein |x| represents the absolute value of x) which causes transistor710to be turned on when signal223is greater than or equal to (BIASN−Vt). Transistor710draws high current when turned on, and operates as a open switch otherwise.

Transistors720and730together operate as a current amplifier. Gate terminal of transistor730is connected to the drain terminal of transistor720. The source terminals of the two transistors are connected to Vss103. The drain terminals of transistors720and730are respectively connected to paths711and722. The drain and gate terminals of transistor720are shorted.

Transistor730is designed to be K times the size of transistor720. Transistor720generates a bias such that the current on path722is K times the current on path711when voltage at node223equals (BIASN−Vt), as described below.

When the voltage on node223is lesser than (BIASN−Vt), no (negligible amount of) current flows on path711. As a result, the voltage at node723is closer to Vss103, which turns off transistor730. Thus, low current is drawn on line722when the voltage on node223is less than (BIASN−Vt).

When the voltage on node223equals (BIASN−Vt), current flows on path711, which increases the voltage at node723. Transistor730is turned on as a result, and draws current on path722. As would be apparent to one skilled in the relevant arts, the larger size (K times) of transistor730would cause the current on path722to equal K times the current drawn on path711.

Therefore, counter-leakage circuit380-3draws from path722(and thus223) a large amount of current when PMOS transistor710conducts (i.e., when there is current on path711). The drawing of such a large amount of current enables the voltage on node223to be limited to the desired voltage level (BIASN−Vt) when voltage on node223rises above (BIASN−Vt). As a result, any leakage in transistor320in an off state (which may cause the voltage at node223to rise above (BIASN−Vt)) is countered by current flow through transistor730.

In addition, counter-leakage circuit380-3may not draw any current when PMOS transistor710does not conduct (when voltage on node223is less than (BIASN−Vt)). As a result, counter-leakage circuit380-3may not affect the voltage on node223when voltage level is less than (BIASN−Vt).

Furthermore, PMOS transistor710can be chosen to be of small size, thereby not providing substantial parasitic capacitance. In addition, transistors720and730may also provide low parasitic capacitance since both transistors720and730are implemented as NMOS transistors. Counter-leakage circuit380-3consumes substantially low power since counter-leakage circuit710draws current only when voltage on node223rises above (BIASN−Vt).

For conciseness, the similarity of components are described with reference toFIG. 7. Transistors810,820and830operate similar to transistors710,720and730ofFIG. 7. NMOS transistor810receives the signal at node231on source terminal, and BIAS2voltage on gate terminal801(similar to BIAS2on path502). In an embodiment, BIAS2equals (BIASP+|Vt| of transistor310), which causes transistor810to be turned on when signal231is less than or equal to (BIASP+Vt of transistor310).

Transistor810draws high current when turned on, and operates as a open switch otherwise. Transistors820and830operate as a current amplifier and draws more current when voltage on node231falls below (BIASP+Vt of transistor310). Therefore, counter-leakage circuit380-1prevents the voltage at node231from falling below (BIASP+Vt of transistor310). The description is continued with reference to another alternative embodiment of counter-leakage circuits380-1through380-4.

13. Another Alternative Embodiment of Counter-leakage Circuit

FIGS. 9 and 10are circuit diagrams together illustrating the details of counter-leakage circuits380-1through380-4in another embodiment. In particular,FIG. 9is a circuit diagram illustrating the details of counter-leakage circuit380-3andFIG. 10is a circuit diagram illustrating the details of counter-leakage circuit380-1.

For conciseness, only the details of counter-leakage circuits380-1and380-3are described herein. However, counter-leakage circuits380-2and380-4may also be implemented similar to380-1and380-3respectively. With reference toFIG. 9, counter-leakage circuit380-3is shown containing NMOS transistors910-1through910-N and920. Each component is described below.

Transistor920turns off counter-leakage circuit380-3according to a signal received on gate terminal922. Transistor920turns off when the voltage level on path922represents logic 0, and disables counter-leakage circuit380-3since Vss103is not connected to transistors910-1through910-N when transistor920is in an off state. Counter-leakage circuit380-3is operational when the voltage level on path922is at logic 1. The operation of counter-leakage circuit380-3is described below.

Each transistor910-1through910-N operates as a diode since the gate terminal is connected to the drain terminal. Each transistor910-1through910-N may be implemented with a small ratio of width to length (W/L). Each transistor910-1through910-N turns on when the voltage on drain terminal is greater than the sum of cutting voltage of corresponding transistor and the voltage on source terminal (of the corresponding transistor). Transistor910-N receives the voltage at node223on drain terminal. All transistors910-1through910-N turn on when the voltage on node223reaches the sum of the cutting voltages of transistors910-1through910-N.

Assuming that the cutting voltages of transistors910-1through910-N are equal (Vt), then each transistor910-1through910-N turns on when the voltage on node223equals N*Vt (wherein ‘*’ represents a multiplication operator). Since the structure of transistors910-1through910-N draws current when turned on, the voltage at node223may not change beyond (BIASN−Vt) by selecting transistors910-1through910-N such that N*Vt equals (BIASN−Vt of transistor320). Therefore, the voltage at node223may be controlled to be below (BIASN−Vt of transistor320) by appropriate choice of number of transistors (N) and cutting voltages.

With reference toFIG. 10, counter-leakage circuit380-1is shown containing PMOS transistors1010-1through1010-N and1020. Transistors1010-1through1010-N and1020operate similar to transistors910-1through910-N and920respectively. However, the drain terminal of transistor1010-N receives the voltage on node231and thus counter-leakage circuit380-1may not allow the voltage at node231to go beyond (BIASP+Vt of transistor310).

It may be noted that several embodiments of counter-leakage circuits380-1through380-4(described above with reference toFIGS. 5 to 10) may reduce leakage of current at several nodes in input buffer110. In addition, the circuits ofFIGS. 5 to 10may consume substantially low power since the transistors in the circuits are turned on only when the voltage at a node goes beyond the desired voltage level. Therefore, input buffer110may be provided with reduced leakage current and reduced power consumption.

However, it may be required to implement high voltage circuits performing several logic functions using low voltage transistors. The manner in which an inverter may be implemented is described below with reference toFIG. 11.

FIGS. 11,12and13are diagrams together illustrating the details of an inverter implemented using low voltage transistors operating at a high voltage in an embodiment of the present invention. In particular,FIG. 11is a block diagram illustrating the details of inverter1100,FIG. 12is a timing diagram illustrating the details of swing signals provided as input to the components in inverter1100, andFIG. 13is a circuit diagram corresponding to inverter1100ofFIG. 11.

With reference toFIG. 11, inverter1100is shown containing PMOS transistor1110, NMOS transistor1120, logic gate protection circuit1130and bus holder1180. Each component is described below.

Bus holder1180receives input signal on path1101and generates two signals on paths1181and1182, each with different voltage levels, but representing the same logic values. Input signal1101is a high voltage signal, which switches between HVDD and Vss. Bus holder1180is an example of a swing spilt circuit, which generates multiple output signals with different voltage swings (amount of change in the voltage levels). Bus holder1180may be implemented similar to bus holder240ofFIG. 2.

Transistors1110and1120together perform an inverting operation of the signal provided on gate terminals of both transistors1110and1120. The gate terminals of transistors1110and1120are connected to paths1181and1182respectively, but both receive the voltage level representing the same logic value.

Logic gate protection circuit1130operates to ensure that transistors1110and1120are not exposed to voltages exceeding the corresponding allowed maximum voltage. Example implementation of logic gate protection circuit1130is described below with reference toFIG. 13in further detail. The manner in which two swing signals on paths1181and1182may be generated is described below.

With reference toFIG. 12, wave forms1210,1230and1250respectively represent input signal1101, swing signal1181and another swing signal1182. It is assumed that Vss103equals ground voltage (0V). Input signal1210is shown changing between 0V and HVDD. For example, input signal1210is shown at 0V before time point1211and at HVDD at time point1211.

Swing signal1230is shown changing between 0V and V1. In an embodiment, V1equals half of HVDD. In an embodiment ofFIG. 3, the signal on path235(1182inFIG. 11) switches between Vss103and BIASN−Vt representing logic 0 and 1 respectively. For example, swing signal1230is shown at V1before time point1211and at 0V after time point1211.

Swing signal1250is shown changing between V2 and HVDD. In an embodiment, V2equals half of HVDD. The first intermediate signal on path366(1182inFIG. 11) may switch between (BIASP+Vt) and HVDD representing logic 0 and 1 respectively. For example, when input signal1101represents logic 0, then the voltage level of the signal on paths1181and1182respectively equals HVDD101and (BIASN−Vt), with both representing logic 1.

With reference toFIG. 13, inverter1100is shown containing PMOS transistor1340and NMOS transistor1350together operating as protection circuit1130, transistors1110and1120performing an inversion logic operation, and bus holder1180. In an embodiment, all the transistors of inverter1100are of the same voltage specification, which is lower than the voltage level of the input signal received on path1101.

The operation of each transistor is first described below with reference to the manner in which each transistor is not exposed to cross terminal voltages exceeding an allowed maximum voltage in the case of both transitions (0 to 1, and 1 to 0). The operation of transistors as an inverter is then described. For illustration, it is assumed that the voltage level corresponding to logic 1 equals HVDD and logic 0 equals Vss.

The description is continued with respect to state changes when input signal1101transitions to logic 0, and the manner in which transistors (forming inverter1100) may be protected by logic gate protection circuit1130.

Transistor1340is off when input signal1101is at logic 0 since the voltage level of the signal on path1181equals HVDD101, which turns off transistor1110. The turning off of transistor1110turns off transistor1340, and as a result the voltage on path1341equals (BIASP+Vt).

Transistor1110may be protected due to the turning off of transistor1340. In particular, Vds and Vdg of transistor1110would not be exposed to a voltage greater than (HVDD−BIASP−Vt of transistor1340).

The description is continued with respect to state changes when input signal1101transitions to logic 1, and the manner in which transistors (forming inverter1100) may be protected by logic gate protection circuit1130.

Transistor1350is off when input signal1101is at logic 1 since the voltage level of the signal on path1182equals Vss, which turns off transistor1120. The turning off of transistor1120turns off transistor1350, and as a result the voltage on path1352equals (BIASN−Vt of transistor1350).

Transistor1120may be protected due to the turning off of transistor1350. In particular, Vds and Vdg of transistor1120would not be exposed to a voltage greater than (BIASN−Vt of transistor1340-Vss).

Therefore, it may be appreciated that transistors1110and1120are protected due to turning off of transistors1340and1350respectively. While transistors1340and1350operate as a logic gate protection circuit as described above, transistors1110and1120together continue to operate as an inverter as described below.

15. Operation of an Inverter

When input signal1101is at logic 0, the voltage level of the signals on paths1181and1182equals HVDD101and (BIASP+Vt) respectively. The voltage level of the signal on path1182is enough to turn on transistor1120, which pulls path1352to Vss103. The turning on of transistor1120turns on transistor1350. As a result, the voltage on path1345equals Vss103. HVDD on path1181turns off transistor1110, which causes transistor1340to be turned off. As a result, the voltage on path1341equals (BIASP+Vt of transistor1340), which represents logic 0.

When input signal1101is at logic 1, the voltage level of the signals on paths1181and1182equals (BIASP+Vt) and Vss respectively. The voltage level of the signal on path1181is enough to turn on transistor1110, which pulls path1341to HVDD. The turning on of transistor1110turns on transistor1340. As a result, the voltage on path1345equals HVDD. Vss on path1182turns off transistor1120, which causes transistor1350to be turned off. As a result, the voltage on path1352equals (BIASN−Vt of transistor1350), which represents logic 1.

It may be noted that input signal1101is provided to bus holder1180before providing to transistors1110and1120. In an embodiment, bus holder1180performs an inversion operation on input signal1101and generates inverted signal of1101on paths1181and1182. Inverter1100performs inversion (inverting) operation on signals1181and1182according to an aspect of the present invention. Accordingly, the output on path1345represents the same logic level of signal on path1101. It may be noted that to generate an inverted signal of input signal, another inverter similar to inverter1100may be cascaded.

Therefore, inverter1100can be implemented using low voltage transistors operated in high voltage environment. However, the same structure of protection circuit1130may be used to protect the transistors in any other logic gate implemented using low voltage transistors in high voltage environment. An example embodiment of a NAND gate using protection circuit1130is described below with reference toFIG. 14.

FIG. 14is a circuit diagram illustrating the details of a NAND gate implemented using low voltage transistors in high voltage environment in an embodiment of the present invention. For illustration, a two input NAND gate is described, however, multiple number of input NAND gate can be implemented similarly. NAND gate1400is shown containing PMOS transistors1410and1420, NMOS transistors1430and1440, bus holders1450and1460, and protection circuit1130. Each component is described below.

Bus holder1450receives one input signal on path1401and generates swing signals for transistors1410and1430on respective paths1451and1453similar to bus holder1180. Similarly, bus holder1460receives another input signal on path1402and generates swing signals for transistors1420and1440on respective paths1462and1464.

Transistors1410,1420,1430and1440together operate generally as a NAND gate by receiving signals on respective gate terminals on paths1451,1462,1453and1464as is well known in relevant arts. NAND gate1400performs NAND operation on input signals1401and1402, and provides output with high voltage swing on path1445and with low voltage swing on paths1434and1412.

Protection circuit1130containing transistors1340and1350protects transistors1410,1420,1430and1440from avoiding exposure to high voltages, similar to as described above with reference toFIG. 13.

In particular, transistors1410and1420may be protected due to the turning off of transistor1340. For example, Vds and Vdg of transistors1410and1420would not be exposed to a voltage greater than (HVDD−BIASP−Vt of transistor1340) due to the turning off of transistor1340.

Similarly, transistors1430and1440may be protected due to the turning off of transistor1350. For example, Vds and Vdg of transistors1430and1440would not be exposed to a voltage greater than (BIASN−Vt of transistor1350-Vss) due to the turning off of transistor1350.

Therefore, it may be noted that protection circuit1130may be used in logic gates implemented using low voltage transistors and operated in high voltage environment such that protection circuit1130may protect low voltage transistors from being exposed to high voltages.

Protection circuit1130may also be used to implement any combinatorial logic using low voltage transistors and operated in high voltage environments such that protection circuit1130may protect low voltage transistors from being exposed to high voltages. In addition, the logic gates described above (and combinatorial logic containing such gates) can be used as pre-driver140.

Another aspect of the present invention provides enhanced hysteresis, which leads to better immunity (in the operation of a circuit) to noise in the corresponding input signal. Hysteresis provides positive feedback Schmitt trigger action on the input of certain circuits causing a dependence in circuit switching thresholds on the previous state of the circuits positive feedback loop. The circuits high and low threshold voltage will now exhibit “inertia” and the input will have to overcome this inertia by going beyond the required threshold (without hysteresis) in order to change the state of the positive feedback loop. This inertial property of the receiver is generally referred to as hysteresis. The desired response due to enhanced hysteresis is described below first.

FIG. 15is a timing diagram illustrating the desired response with enhanced hysteresis in one embodiment. Wave forms1510and1540respectively represents input signal received on path201and output signal provided on path299. Voltage levels (VIL and VIH)1520and1530respectively represent the higher and lower hysteresis threshold voltages, which determine the voltage level of output signal1540at any time point.

Output signal1540needs to change from a logic 0 to 1 if input signal1510rises above VIH1530. The corresponding transition is shown at time point1511. Output signal1540needs to change from logic 1 to 0 if input signal1510falls below VIL1520, and the corresponding transition is shown at time point1512.

A circuit exhibiting hysteresis should not transition the output values if the input signal fluctuates in the region between VIL1520and VIH1530. The fluctuations are usually due to noise and the absence of transitions indicates a high signal-to-noise-ratio (SNR). The absence of such transitions in output signal1540are shown in time durations1551-1552,1553-1512, and1555-1556.

The manner in which hysteresis may be implemented is described below with reference toFIG. 16.

18. Input Buffer Containing Hysteresis

FIG. 16is a circuit diagram of an input buffer illustrating the details of hysteresis in an embodiment of the present invention. Input buffer1600is shown containing all the components ofFIG. 3and resistor1610. Resistor1610enables input buffer1600to provide hysteresis and thereby attaining high signal to noise ratio.

Hysteresis can be introduced by increasing the sizes of transistors355and310to reduce VIL and increasing the sizes of transistors320and345to increase VIH. By increasing the sizes of transistors310and355, impedance of the path from node1612through transistors310and355decreases, as compared to impedance of resistor1610and thus the path containing transistors310and355controls the voltage at node1612(rather than resistor1610).

Since transistors310and355will be turned off when input signal201is at logic 0, even if the voltage level of input signal goes above VIL set by transistors310and355and below VIH, transistors310and355will remain turned off. Similarly, VIH is adjusted by increasing the sizes of transistors320and345.

In reality, output drivers that provide input signal201have an output impedance and these will compete with the pull up arm (comprising of transistors355and310) and pull down arm (comprising of transistors320and345) for the voltage at the drain terminals of transistors310and320.

The pull down arm of the driver (not shown) will compete with the pull up arm (transistors355and310) of input buffer1600and similarly the pull up of the driver (not shown) will compete with pull down arm (transistors320and345) for control of voltage at node1612.

If the output impedance is insufficient to provide the desired hysteresis, the deficiency can be filled by including resistor1610(either external or internal (like an nwell or poly resistor) which acts in series with the output impedance of the output driver. Increasing the resistance of resistor1610will increase the hysteresis of the circuit.

Thus, integrated circuits provided according to features described above may be implemented in various types of devices. An example device is described below in detail.

19. Example Device

FIG. 17is a block diagram illustrating an example device in which various aspects of the present invention can be implemented. Example device1700is shown containing input interface module1710, processing logic1720and output interface module1750. Each block is described below.

Input interface module1710may provide a suitable interface to receive input signals from various external sources. Examples of such external sources include other devices as well components such as keyboards, networks, etc. The signals may be received on path1711and provided in a suitable format on path1712(after any desired processing). Similarly, output interface module1750provides a suitable interface to transfer the signals received on path1725to external sources (e.g., other devices, display unit, networks, etc.).

Processing logic1720processes the signals received on path1712and provides the output signals to be transmitted to external device(s) on path1725. Processing logic1720may be implemented with low voltage transistors operating with a high voltage supply received on path1701. The voltage level of supply voltage1701is referred with reference to a reference voltage received on path1703. Processing logic1720can be implemented using the various techniques described above with reference to integrated circuit100ofFIG. 1.

While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. Thus, the breadth and scope of the present invention should not be limited by any of the above described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.