Package on package (POP) device comprising solder connections between integrated circuit device packages

Some features pertain to a package on package (PoP) device that includes a first package, a first solder interconnect coupled to the first integrated circuit package, and a second package coupled to the first package through the first solder interconnect. The second package includes a first die, a package interconnect comprising a first pad, where the first solder interconnect is coupled to the first pad of the package interconnect. The second package also includes a redistribution portion coupled to the first die and the package interconnect, an encapsulation layer at least partially encapsulating the first die and the package interconnect. The first pad may include a surface that has low roughness. The encapsulation layer may encapsulate the package interconnect such that the encapsulation layer encapsulates at least a portion of the first solder interconnect.

BACKGROUND

Field

Various features relate generally to a package on package (PoP) device, and more specifically to a package on package (PoP) device that includes solder connections between integrated circuit (IC) packages.

Background

FIG. 1illustrates a device100that includes a first package102and an interposer104. The first package102includes a first die120and a first package substrate122. The first package substrate122includes a plurality of pads124and a first pad126. The first package substrate122also includes a first dielectric layer123. The first package substrate122may also include a first solder resist layer127. The first solder resist layer127is located on the first dielectric layer123. The first solder resist layer127may also cover a portion of the first pad126. The first die120is coupled to the first package substrate122through a first plurality of solder balls128. Specifically, the first die120is coupled to the first plurality of pads124through the first plurality of solder balls128. A second plurality of solder balls130is coupled to the first package substrate122.

The interposer104includes a second pad146. The interposer104may be a package substrate of a second package (not shown). The interposer104also includes a second dielectric layer143. The interposer104may also include a second solder resist layer147. The second solder resist layer147is located on the second dielectric layer143. The second solder resist layer147may also cover a portion of the second pad146. The interposer104is coupled to the first package102through a first solder ball156. For example, the first solder ball156is coupled to the first pad126of the first package substrate122, and the second pad146of the interposer104. The solder ball156is located in a cavity of an encapsulation layer150of the first package102. The cavity of the encapsulation layer150in which the solder ball156is located in is formed by using a laser process (e.g., laser ablation).

As shown inFIG. 1, the first pad126has a surface that is in contact with the solder ball156. The surface of the first pad126that is in contact with the solder ball156has a relatively rough surface roughness. This is due to the fact that a laser is used to remove the encapsulation layer150over the first pad126. The result of this laser process (e.g., laser ablation) is an uneven surface (e.g., rough surface) on the first pad126. An uneven surface or rough surface on the first pad126can result in a weak joint, a poor joint and/or an open joint between the first pad126and the solder ball156. A weak joint or poor joint connection can result in poor and/or unreliable signal quality in the device100, which can cause poor performance in the device100.

Therefore, there is a need for a device (e.g., package on package (PoP) device) with strong and reliable joints to ensure better quality and/or performance signals between packages. Ideally, such a device will have a better form factor, be cheaper to fabricate, while at the same time meeting the needs and/or requirements of mobile and/or wearable devices.

SUMMARY

Various features relate generally to a package on package (PoP) device, and more specifically to a package on package (PoP) device that includes solder connections between integrated circuit (IC) packages.

One example provides a package on package (PoP) device that includes a first package, a first solder interconnect coupled to the first package, and a second package coupled to the first package through the first solder interconnect. The second package includes a first die, a package interconnect comprising a first pad, where the first solder interconnect is coupled to the first pad of the package interconnect, and a redistribution portion coupled to the first die and the package interconnect, and an encapsulation layer encapsulating the first die and the package interconnect.

Another example provides a package on package (PoP) device that includes a first package, a first solder interconnect coupled to the first package, and a second package coupled to the first package through the first solder interconnect. The second package includes a first die, means for interconnecting package portions coupled to the first solder interconnect, a redistribution portion coupled to the first die and the means for interconnecting package portions, and an encapsulation layer encapsulating the first die and the means for interconnecting package portions.

DETAILED DESCRIPTION

Overview

Some features pertain to a package on package (PoP) device that includes a first package, a first solder interconnect coupled to the first package, and a second package coupled to the first package through the first solder interconnect. The second package includes a first die, a package interconnect comprising a first pad, where the first solder interconnect is coupled to the first pad of the package interconnect. The second package also includes a redistribution portion coupled to the first die and the package interconnect, an encapsulation layer encapsulating the first die and the package interconnect. The first pad may include a surface that has low roughness. The encapsulation layer may encapsulate the package interconnect such that the encapsulation layer encapsulates at least a portion of the first solder interconnect. In some implementations, the encapsulation layer encapsulates the package interconnect such that the encapsulation layer encapsulates at least a portion of the first solder interconnect. In some implementations, the encapsulation layer encapsulates the package interconnect such that there is a cavity between the encapsulation layer and a portion of the first pad when the first solder interconnect is coupled to the first pad and the first package.

In some implementation, an interconnect is an element or component of a device (e.g., integrated device, integrated device package, die) and/or a base (e.g., package substrate, printed circuit board, interposer) that allows or facilitates an electrical connection between two points, elements and/or components. In some implementations, an interconnect may include a trace, a via, a pad, a pillar, a redistribution metal layer, and/or an under bump metallization (UBM) layer. In some implementations, an interconnect is an electrically conductive material that provides an electrical path for a signal (e.g., data signal, ground signal, power signal). An interconnect may include more than one element/component.

Exemplary Package on Package (PoP) Device Comprising Solder Connections

FIG. 2illustrates a package on package (PoP) device200that includes solder connections. The package on package (PoP) device200includes a first package202(e.g., first integrated circuit device package) and a second package204(e.g., second integrated circuit device package). The first package202is coupled to the second package204through at least one solder interconnect270(e.g., at least one solder ball).

The first package202(e.g., first integrated circuit device package) includes a first package substrate220, a first die230, and at least one wire bond290. A die (e.g., first die230) may be an integrated circuit (IC) that includes several transistors and/or other electronic components. The first die230may be a logic die and/or a memory die. The first die230is coupled to the first package substrate220. The at least one wire bond290is coupled to the first die230and the first package substrate220. The first package substrate220may include at least one dielectric layer, at least one solder resist layer, at least one via in the dielectric layer, and at least one pad. The first package202and the first package substrate220are described in further detail below inFIG. 3.

The second package204(e.g., second integrated circuit device package) includes a package interconnect210, a redistribution portion240, a second die250, an encapsulation layer260, and a solder ball280. The second package204may be a fan out wafer level package (FOWLP). The second die250may be a logic die and/or a memory die. The second die250is coupled to the redistribution portion240. The package interconnect210is coupled to the redistribution portion240. The redistribution portion240may be a fan out portion (e.g. for fanning or routing of signaling to and from devices with different I/O pitches). The encapsulation layer260at least partially encapsulates the second die250and the package interconnect210. The term “encapsulates” may mean to at least surround an object or component. When a material A encapsulates a material B, the material A may at least partially surround the material B. When the material A encapsulates the material B, the material A may be physically touching some or all portions of the material B. In some implementations, the material A may encapsulate material B without directly touching any part of the material B.

Different implementations may use a package interconnect (e.g., package interconnect210) with different designs and configurations. In some implementations, the package interconnect may be a means for interconnecting package portions. In some implementations, the package interconnect or means for interconnecting package portions may be a package interconnect from a group of package interconnects comprising a printed circuit board (PCB) bar, a preformed through substrate via (TSV) bar, and/or an in-situ plated metal interconnect (e.g., in-situ plated copper interconnect). In some implementations, the redistribution portion240may include at least one dielectric layer, and/or at least one redistribution layer. In some implementations, the redistribution portion240may also include at least one under bump metallization (UBM) layer. In some implementations, the selection of a particular package interconnect may depend on cost, design rule requirements, and overall height. For example, a plated metal interconnect or TSV bar may have finer design rules and a lower profile, but would be more expensive than a larger and thicker PCB bar. The package interconnect210will be further described below inFIG. 3.

As mentioned above, the first package202is coupled to the second package204through at least one solder interconnect270(e.g., at least one solder ball). As shown inFIG. 2, the first package202is coupled to the package interconnect210of the second package204through the at least one solder interconnect270. As will be further described below in at leastFIG. 3, the package interconnect210includes a pad (e.g., first pad330) that is coupled to the solder interconnect270. The pad (e.g., first pad330) that is coupled to the solder interconnect270, has a smooth surface (e.g., not rough relative to pad that has been exposed to laser).

The roughness of a surface can be expressed by the vertical deviations of the roughness profile of the surface from the mean line. For example, the roughness of a surface can be expressed by the amplitude parameters and/or variations of the surface from a mean flat surface and/or a mean line of the surface. In some implementations, the arithmetic average (Ra) of the absolute values of the amplitude of the vertical deviation of the roughness profile of the surface (e.g., pad surface) from a mean line is one example of quantifying roughness. In some implementations, the roughness of the surface of the pad that is coupled to the solder interconnect270has a Ravalue (surface roughness Ravalue) of about 1 micron (μm) or less. In some implementations, a low Ravalue and/or roughness provides more robust and/or reliable solder connections, thereby providing more robust and/or reliable signal and/or power transmission between connections in the package on package (PoP) device200.

In some implementations, a low Ravalue and/or roughness of the pad that is coupled to the solder interconnect270is possible because a laser is not used on the pad during the fabrication of the package on package (PoP) device200. As will be further described below in detail, a low Ravalue and/or roughness of the pad that is coupled to the solder interconnect270can be achieved by providing solder on the pad (e.g., first pad330) before forming the encapsulation layer260on the package interconnect210.

Different implementations may provide the solder on the pad prior to forming the encapsulation layer260differently. For example, the solder may be formed on the pad through a printing process (e.g., solder on pad (SOP), coined SOP). In another example, the solder may be provided as a solder ball on the pad. Various examples of providing solder on the pad will be described in further details below.

Different implementations may use different packages as the top package (e.g., first package202) in the package on package (PoP) device200. For example, the top package of the package on package (PoP) device200may be a package from a group of packages comprising a fan out wafer level package (FOWLP), a wire bond chip scale package (CSP), and/or a flip chip chip scale package (CSP). Examples of a package on package (PoP) devices with a different combination of packages are further illustrated and described inFIGS. 11-13.

FIG. 2illustrates a high level illustration of a package on package (PoP) device200that includes solder connections.FIG. 3illustrates a close up view of the package on package (PoP) device200ofFIG. 2.

As shown inFIG. 3, the package on package (PoP) device200includes the first package202(e.g., first integrated circuit device package) and the second package204(e.g., first integrated circuit device package). The first package202is coupled to the second package204through at least one solder interconnect270(e.g., at least one solder ball).

The first package202includes the first package substrate220and the first die230. The first die230may be coupled to the first package substrate220through an adhesive300. The first package substrate220includes a dielectric layer302, a first solder resist layer304, a second solder resist layer306, a first pad310, a first via312, and a second pad314. The wire bond290is coupled to the first die230and the first pad310. The first pad310is coupled to the first via312. The first via312traverses the dielectric layer302. The first via312is coupled to the second pad314. The second pad314is coupled to the solder interconnect270.

The second package204(e.g., second integrated circuit device package) includes the package interconnect210, the redistribution portion240(e.g., fan out portion), the second die250, the encapsulation layer260, and the solder ball280. The second die250is coupled to the redistribution portion240. The package interconnect210is coupled to the redistribution portion240. The encapsulation layer260at least partially encapsulates the second die250and the package interconnect210.

The package interconnect210includes a dielectric layer320, a first solder resist layer322, a second solder resist layer324, a first pad330, a first via332, and a second pad334. The first solder resist layer322and the second solder resist layer324may be optional. The second pad334is coupled to the first via332. The first via332may traverse the dielectric layer320. The first via332is coupled to the first pad330. The first pad330is coupled to the solder interconnect270. More specifically, a surface of the first pad330is coupled to the solder interconnect270.

In some implementations, the surface of the first pad330that is coupled to the solder interconnect270, has a smooth surface (e.g., not rough relative to pad that has been exposed to laser). In some implementations, the roughness of the surface of the first pad330that is coupled to the solder interconnect270has a Ravalue (surface roughness Ravalue) of about 1 micron (μm) or less. In some implementations, a low Ravalue and/or roughness provides more robust and/or reliable solder connections, thereby providing more a robust and/or reliable signal and/or power transmission between connections in the package on package (PoP) device200.

As shown inFIG. 3, the redistribution portion240includes a first dielectric layer340, a second dielectric layer342, a third dielectric layer344, a first redistribution layer350, a second redistribution layer352, an under bump metallization (UBM) layer354, and the solder ball280. The first redistribution layer350is coupled to the package interconnect210and the second die250. More specifically, the first redistribution layer350is coupled to the second pad334of the package interconnect210. The second redistribution layer352is coupled to the first redistribution layer350. The UBM layer354is coupled to the second redistribution layer352. The solder ball280is coupled to the UBM layer354. In some implementations, the UBM layer354may be optional. In such instances, the solder ball280may be directly coupled to the second redistribution layer352. It is noted that different implementations may have a different number of redistribution layers (e.g., one or more redistribution layers).

In some implementation, a redistribution layer (e.g.350,352), is a component that allows or facilitates an electrical connection between various points, elements and/or components. In some implementations, a redistribution layer (e.g.350,352) may include a trace, a via, and/or a pad. In some implementations, a redistribution layer (e.g.350,352) is an electrically conductive material that may provide an electrical path for a signal (e.g., data signal, ground signal, power signal). A redistribution layer (e.g.350,352) may include more than one element or component. A redistribution layer (e.g.350,352) may redistribute I/O pads of a die to other parts of the package.

In some implementations, the redistribution portion240is a part of the second package204that allows input/output (I/O) pads of a die (e.g., second die250) to be available (e.g., fan out) in other locations of the second package204. In some implementations, the first redistribution layer350and/or the second redistribution layer352redistribute the I/O pads of the second die250to other locations in the second package204.

The second die250may include a substrate portion360(e.g., silicon substrate), a pad362, a first passivation layer364, and a second passivation layer366. In some implementations, the pad362of the second die250is coupled to the first redistribution layer350of the redistribution portion240. The second die250may be configured to be electrically coupled to the package interconnect210through the redistribution portion240(e.g., through at least one redistribution layer of the redistribution portion240).

In some implementations, the first die230may be configured to be electrically coupled to the second die250through the wire bond290, the first package substrate220(e.g., interconnects in the first package substrate220), the solder interconnect270, the package interconnect210(e.g., pads, vias, traces of the package interconnect210), and the redistribution portion240(e.g., at least one redistribution layer of the redistribution portion240).

In some implementations, the first die230has a height of about 50 microns (μm) or less. In some implementations, the second die250has a height of about 150 microns (μm) or less. In some implementations, the package interconnect210has a height of about 150 microns (μm). However, the package interconnect210may have a height that is greater or less than 150 microns (μm). In some implementations, the redistribution portion240has a height of about 40 microns (μm) or less. The PoP device200may have an X-Y dimension (e.g., lateral area and/or footprint) of about 5 mm×5 mm to 20 mm×20 mm (millimeter). The pitch of interconnects in the package interconnect210may be about 200 microns (μm) or less, where a pitch is a center to center distance between two adjacent interconnects (e.g., two adjacent pads). For example, the package interconnect210may include two adjacent vias. In some implementations, the pitch of the two adjacent vias in the package interconnect210may be about 200 microns (μm) or less. It is noted that the above exemplary dimensions may also be applicable to other package on package (PoP) devices described in the present disclosure.

In some implementations, the height of the package on package (PoP) device may be defined along the Z-direction of the package on package (PoP) device, which is shown in the figures of the present disclosure. In some implementations, the Z-direction of the package on package (PoP) device may be defined along an axis between a top portion and a bottom portion of the package on package (PoP) device. The terms top and bottom may be arbitrarily assigned, however as an example, the top portion of the device package may be a portion comprising the first die and/or wire bond, while a bottom portion of the package on package (PoP) device may be a portion comprising a redistribution portion or a plurality of solder balls. In some implementations, the top portion of the package on package (PoP) device may be a back side of the package on package (PoP) device, and the bottom portion of the package on package (PoP) device may be a front side of the package on package (PoP) device. The front side of the package on package (PoP) device may be an active side of the package on package (PoP) device. A top portion may be a higher portion relative to a lower portion. A bottom portion may be a lower portion relative to a higher portion.

In some implementations, the first package202may include a second encapsulation layer (not shown) that at least partially encapsulates the first die230and the wire bond290.

Exemplary Sequence of Solder Coupling in a Package on Package (PoP) Device

FIG. 4illustrates an exemplary sequence of solder interconnect coupling in a package on package (PoP) device.FIG. 4will be described in the context of coupling two packages to form the package on package (PoP) device200ofFIGS. 2-3.

Stage1illustrates a state before the first package202(e.g., first integrated circuit device package) is coupled to the second package204(e.g., second integrated circuit device package). As shown at stage1, a solder interconnect400is coupled to the second pad314of the first package substrate220of the first package202.

Stage1also illustrates that a solder interconnect402is formed on the first pad330of the package interconnect210. The solder interconnect402is also formed on the first solder resist layer322. The encapsulation layer260encapsulates part of the solder interconnect402. The solder interconnect402may be a coined solder on pad (SOP). In some implementations, the solder interconnect402is formed on the first pad330through a printing process (e.g., screen printing process). In some implementations, the solder interconnect402is provided (e.g., formed) on the first pad330and then coined so that the solder interconnect402is relatively flat.

Stage2illustrates a state after the first package202is coupled to the second package204. As shown at stage2, the solder interconnect400is touching the solder interconnect402. In some implementations, the solder interconnect400has combined (e.g., mixed) with the solder interconnect402. In some implementations, the combination of the solder interconnect400and the solder interconnect402is represented as the solder interconnect270ofFIGS. 2-3.

Stage3illustrates a state after the solder interconnect400and the solder interconnect402have combined and set. In some implementations, the combination of the solder interconnect400and the solder interconnect402is represented as the solder interconnect270ofFIGS. 2-3. As shown at stage3, some or all of the solder interconnect402that was encapsulated by the encapsulation layer260has seeped out to combine with the solder interconnect400. The result of the solder interconnect402being seeped out has left a cavity410in the encapsulation layer260. The cavity410is located between the first pad330and the encapsulation layer260. The cavity410may also be located between the first solder resist layer322and the encapsulation layer260. As shown in stage3, the cavity410in the encapsulation layer260has at least part of the shape of the solder interconnect402prior to the coupling of the packages. Stage3also illustrates that the cavity in the encapsulation layer260in which the solder interconnect402is located has a non-U shape profile or non-V shape profile. In some implementations, the side walls of the cavity (e.g., cavity410) in which the solder interconnect402is located is non-linear.

Exemplary Sequence of Solder Coupling in a Package on Package (PoP) Device

FIG. 5illustrates another exemplary sequence of solder coupling in a package on package (PoP) device.FIG. 5is similar toFIG. 4, except thatFIG. 5illustrates a solder interconnect that is formed differently on the pad of the package interconnect.FIG. 5will be described in the context of coupling two packages to form the package on package (PoP) device200ofFIGS. 2-3.

Stage1illustrates a state before the first package202(e.g., first integrated circuit device package) is coupled to the second package204(e.g., second integrated circuit device package). As shown at stage1, a solder interconnect400is coupled to the second pad314of the first package substrate220of the first package202.

Stage1also illustrates that a solder interconnect500is formed on the first pad330of the package interconnect210. The solder interconnect500is also formed on the first solder resist layer322. The encapsulation layer260encapsulates part of the solder interconnect500. In some implementations, the solder interconnect500is provided in a similar manner as the solder interconnect402, except that the solder interconnect500is not coined to be flat.

Stage2illustrates a state after the first package202is coupled to the second package204. As shown at stage2, the solder interconnect400is touching the solder interconnect500. In some implementations, the solder interconnect400has combined (e.g., mixed) with the solder interconnect500. In some implementations, the combination of the solder interconnect400and the solder interconnect500is represented as the solder interconnect270ofFIGS. 2-3.

Stage3illustrates a state after the solder interconnect400and the solder interconnect500have combined and set. In some implementations, the combination of the solder interconnect400and the solder interconnect500is represented as the solder interconnect270ofFIGS. 2-3. As shown at stage3, some or all of the solder interconnect500that was encapsulated by the encapsulation layer260has seeped out to combine with the solder interconnect400. The result of the solder interconnect500being seeped out has left a cavity510in the encapsulation layer260. The cavity510is located between the first pad330and the encapsulation layer260. The cavity510may also be located between the first solder resist layer322and the encapsulation layer260. As shown in stage3, the cavity510in the encapsulation layer260has at least part of the shape of the solder interconnect500prior to the coupling of the packages. Stage3also illustrates that the cavity in the encapsulation layer260in which the solder interconnect500is located has a non-U shape profile or non-V shape profile. In some implementations, the side walls of the cavity (e.g., cavity510) in which the solder interconnect500is located is non-linear.

Exemplary Sequence of Solder Coupling in a Package on Package (PoP) Device

FIG. 6illustrates another exemplary sequence of solder interconnect coupling in a package on package (PoP) device.FIG. 6is similar toFIG. 4, except thatFIG. 6illustrates a solder that is formed differently on the pad of the package interconnect.FIG. 6will be described in the context of coupling two packages to form the package on package (PoP) device200ofFIGS. 2-3.

Stage1illustrates a state before the first package202(e.g., first integrated circuit device package) is coupled to the second package204(e.g., second integrated circuit device package). As shown at stage1, a solder interconnect400is coupled to the second pad314of the first package substrate220of the first package202.

Stage1also illustrates that a solder interconnect600is formed on the first pad330of the package interconnect210. The solder interconnect600is also formed on the first solder resist layer322. The encapsulation layer260encapsulates part of the solder interconnect600. In some implementations, the solder interconnect600is provided (e.g., formed) by dropping a preformed solder ball on the first pad330.

Stage2illustrates a state after the first package202is coupled to the second package204. As shown at stage2, the solder interconnect400is touching the solder interconnect600. In some implementations, the solder interconnect400has combined (e.g., mixed) with the solder interconnect600. In some implementations, the combination of the solder interconnect400and the solder interconnect600is represented as the solder interconnect270ofFIGS. 2-3.

Stage3illustrates a state after the solder interconnect400and the solder interconnect600have combined and set. In some implementations, the combination of the solder interconnect400and the solder interconnect600is represented as the solder interconnect270ofFIGS. 2-3. As shown at stage3, some or all of the solder interconnect600that was encapsulated by the encapsulation layer260has seeped out to combine with the solder interconnect400. The result of the solder interconnect600being seeped out has left a cavity610in the encapsulation layer260. The cavity610is located between the first pad330and the encapsulation layer260. The cavity610may also be located between the first solder resist layer322and the encapsulation layer260. As shown in stage3, the cavity610in the encapsulation layer260has at least part of the shape of the solder interconnect600prior to the coupling of the packages. Stage3also illustrates that the cavity in the encapsulation layer260in which the solder interconnect600is located has a non-U shape profile or non-V shape profile. In some implementations, the side walls of the cavity (e.g., cavity610) in which the solder interconnect600is located is non-linear.

Exemplary Solder Comprising Different Properties

In some implementations, a solder interconnect that couples two packages in a package on package (PoP) device may form two materials with different properties.FIG. 7illustrates a solder interconnect700that includes two materials with different properties. In some implementations, the solder interconnect700may represent the solder interconnect270. The solder interconnect700couples the second pad314of the first package202to the first pad330of the second package204. In some implementations, the solder interconnect700may represent the solder interconnect270ofFIGS. 2-3. As shown inFIG. 7, the solder interconnect700includes a first portion702, a second portion704, and a third portion706. The second portion704is coupled to the first pad330. The second portion704is coupled to the first portion702. The first portion702is coupled to the third portion706. The third portion706is coupled to the second pad314. The first portion702has a first property, the second portion704has a second property (e.g., second intermetallic discernability), and the third portion706has a third property (e.g., third intermetallic discernability). The first portion702may be solder interconnect, the second portion704may be a first intermetallic material, and the third portion706may be a second intermetallic material. The first intermetallic material and the second intermetallic material may be a solder copper intermetallic. In some implementations, the second portion704may be a thicker intermetallic material than the third portion706. This may be due to the fact that the second portion704of the solder interconnect700goes through two (2) reflow processes, while the third portion706of the solder interconnect700goes through one (1) reflow process. In some implementations, the second portion704may be at least about 1.5 times thicker than the third portion706.

Exemplary Sequence for Fabricating a Package on Package (PoP) Device Comprising Solder Connections

In some implementations, providing/fabricating a package on package (PoP) device that includes solder connections includes several processes.FIG. 8illustrates an exemplary sequence for providing/fabricating an package on package (PoP) device that includes solder connections. In some implementations, the sequence ofFIG. 8may be used to provide/fabricate the package on package (PoP) device ofFIGS. 2-3and/or other package on package (PoP) devices described in the present disclosure. However, for the purpose of simplification,FIG. 8will be described in the context of providing/fabricating the package on package (PoP) device ofFIG. 3.

It should be noted that the sequence ofFIG. 8may combine one or more stages in order to simplify and/or clarify the sequence for providing a package on package (PoP) device. In some implementations, the order of the processes may be changed or modified.

Stage1, as shown inFIG. 8A, illustrates a state after a die800is coupled (e.g., placed) to a carrier802. The die800may be identical and/or similar to the second die250ofFIG. 3. The die800may be a logic die and/or a memory die. The die800may include a substrate portion (e.g., silicon substrate), a pad, a first passivation layer, and a second passivation layer, as described for the second die250inFIG. 3.

Stage2illustrates a state after a package interconnect804is coupled (e.g., placed) to the carrier802. The package interconnect804may be identical and/or similar to the package interconnect210ofFIG. 3. The package interconnect804includes a first solder interconnect806and a first pad808. The first solder interconnect806is coupled to the first pad808. The first solder interconnect806may be solder on pad (SOP) (e.g., coined SOP). In some implementations, the first solder interconnect806is formed by using a printing process (e.g., screen printing process).

Stage3illustrates a state after an encapsulation layer810is formed on the die800and the package interconnect804. The encapsulation layer810is formed such that the encapsulation layer810at least partially encapsulates the die800and the package interconnect804. Stage3illustrates that the encapsulation layer810at least partially encapsulates the first solder interconnect806.

Stage4illustrates a state after the carrier802is removed from the die800, the package interconnect804, and the encapsulation layer810.

Stage5, as shown inFIG. 8B, illustrates a state after a first dielectric layer814and a first redistribution layer815are formed. The first dielectric layer814may be formed on a passivation layer of the die800and a solder resist layer of the package interconnect804. The first redistribution layer815is formed such that the first redistribution layer815is coupled to the pad812of the die800and the package interconnect804.

Stage6illustrates a state after a second dielectric layer816and a second redistribution layer817are formed. The second dielectric layer816may be formed on the first dielectric layer814. The second redistribution layer817is formed such that the second redistribution layer817is coupled to the first redistribution layer815.

Stage7illustrates a state after a third dielectric layer818and an under bump metallization (UBM) layer819are formed. The third dielectric layer818may be formed on the second dielectric layer816. The UBM layer819is formed such that the UBM layer819is coupled to the second redistribution layer817.

Stage8illustrates a state after a solder ball820is coupled to the UBM layer819. In some implementations, the UBM layer819is optional. In such instances, the solder ball820may be directly coupled to the second redistribution layer817.

Stage9, as shown inFIG. 8C, illustrates a state after the first solder interconnect806is exposed by removing portions of the encapsulation layer810. In some implementations, a laser process (e.g., laser ablation) is used to remove portions of the encapsulation layer810. Since the first solder interconnect806covers the first808pad on the package interconnect804, the laser process does not damage the first pad808or make the pad surface rougher, thus preserving the smoothness of the surface of the first pad808coupled to the first solder interconnect806. As shown at stage9, a cavity821is formed in the encapsulation layer810over the first solder interconnect806. Stage9in some implementations, illustrates a package830that includes the die800, the package interconnect804, the encapsulation layer810, and a redistribution portion840.

Stage10illustrates a state after the first package202is coupled to the package830through the solder the at least one solder interconnect270. The at least one solder interconnect270may include the first solder interconnect806. The first package202includes the first package substrate220, the first die230and the wire bond290. Stage10illustrates in some implementations, a package on package (PoP) device850that includes the first package202and the package830, where the package830includes the die800, the package interconnect804, the redistribution portion840, and the encapsulation layer810. The package interconnect804includes the first pad808and the first solder interconnect806, where the first pad808includes a surface coupled to the first solder interconnect806. The surface of the first pad808that is coupled to the first solder interconnect806has a surface roughness Ravalue that is about 1 micron (μm) or less.

Exemplary Sequence for Fabricating a Package on Package (PoP) Device Comprising Solder Connections

In some implementations, providing/fabricating a package on package (PoP) device that includes solder connections includes several processes.FIG. 9illustrates an exemplary sequence for providing/fabricating an package on package (PoP) device that includes solder connections. In some implementations, the sequence ofFIG. 9may be used to provide/fabricate the package on package (PoP) device ofFIGS. 2-3and/or other package on package (PoP) devices described in the present disclosure. However, for the purpose of simplification,FIG. 9will be described in the context of providing/fabricating the package on package (PoP) device ofFIG. 3.

It should be noted that the sequence ofFIG. 9may combine one or more stages in order to simplify and/or clarify the sequence for providing an package on package (PoP) device. In some implementations, the order of the processes may be changed or modified.

Stage1, as shown inFIG. 9A, illustrates a state after a die800is coupled (e.g., placed) to a carrier802. The die800may be identical and/or similar to the second die250ofFIG. 3. The die800may be a logic die and/or a memory die. The die800may include a substrate portion (e.g., silicon substrate), a pad, a first passivation layer, and a second passivation layer, as described for the second die250inFIG. 3

Stage2illustrates a state after a package interconnect804is coupled (e.g., placed) to the carrier802. The package interconnect804may be identical and/or similar to the package interconnect210ofFIG. 3. The package interconnect804includes a first solder interconnect906and a first pad808. The first solder interconnect906is coupled to the first pad808. The first solder interconnect906may be solder on pad (SOP) or a solder ball.

Stage3illustrates a state after an encapsulation layer810is formed on the die800and the package interconnect804. The encapsulation layer810is formed such that the encapsulation layer810at least partially encapsulates the die800and the package interconnect804. Stage3illustrates that the encapsulation layer810at least partially encapsulates the first solder interconnect906.

Stage4illustrates a state after the carrier802is removed from the die800, the package interconnect804, and the encapsulation layer810.

Stage5, as shown inFIG. 9B, illustrates a state after a first dielectric layer814and a first redistribution layer815are formed. The first dielectric layer814may be formed on a passivation layer of the die800and a solder resist layer of the package interconnect804. The first redistribution layer815is formed such that the first redistribution layer815is coupled to the pad812of the die800and the package interconnect804.

Stage6illustrates a state after a second dielectric layer816and a second redistribution layer817are formed. The second dielectric layer816may be formed on the first dielectric layer814. The second redistribution layer817is formed such that the second redistribution layer817is coupled to the first redistribution layer815.

Stage7illustrates a state after a third dielectric layer818and an under bump metallization (UBM) layer819are formed. The third dielectric layer818may be formed on the second dielectric layer816. The UBM layer819is formed such that the UBM layer819is coupled to the second redistribution layer817.

Stage8illustrates a state after a solder ball820is coupled to the UBM layer819. In some implementations, the UBM layer819is optional. In such instances, the solder ball820may be directly coupled to the second redistribution layer817.

Stage9, as shown inFIG. 9C, illustrates a state after a portion of the encapsulation layer810is removed. In some implementations, a grinding process may be used to remove portions of the encapsulation layer810.

Stage10illustrates a state after the first solder interconnect906is exposed by removing portions of the encapsulation layer810. In some implementations, a laser process (e.g., laser ablation) is used to remove portions of the encapsulation layer810. Since the first solder interconnect906covers the first pad808on the package interconnect804, the laser process does not damage the first pad808or make the pad surface rougher, thus preserving the smoothness of the surface of the first pad808coupled to the first solder interconnect906. As shown at stage10, a cavity821is formed in the encapsulation layer810over the first solder interconnect906. Stage9in some implementations, illustrates a package900that includes the die800, the package interconnect804, the encapsulation layer810, and a redistribution portion840.

Stage11illustrates a state after the first package202is coupled to the package900through the solder the at least one solder interconnect270. The at least one solder interconnect270may include the first solder interconnect906. The first package202includes the first package substrate220, the first die230and the wire bond290. Stage11illustrates in some implementations, a package on package (PoP) device910that includes the first package202and the package900, where the package900includes the die800, the package interconnect804, the redistribution portion840, and the encapsulation layer810. The package interconnect804includes the first pad808and the first solder interconnect906, where the first pad808includes a surface coupled to the first solder interconnect906. The surface of the first pad808that is coupled to the first solder interconnect906has a surface roughness Ravalue that is about 1 micron (μm) or less.

Exemplary Method for Fabricating a Package on Package (PoP) Device Comprising Solder Connections

In some implementations, providing/fabricating a package on package (PoP) device that includes solder connections includes several processes.FIG. 10illustrates an exemplary flow diagram of a method for providing/fabricating an package on package (PoP) device that includes solder connections. In some implementations, the method ofFIG. 10may be used to provide/fabricate the package on package (PoP) device ofFIGS. 2-3and/or other package on package (PoP) devices described in the present disclosure. However, for the purpose of simplification,FIG. 10will be described in the context of providing/fabricating the package on package (PoP) device ofFIG. 3.

It should be noted that the flow diagram ofFIG. 10may combine one or more processes in order to simplify and/or clarify the method for providing a package on package (PoP) device. In some implementations, the order of the processes may be changed or modified.

The method places (at1005) a die and a package interconnect on a carrier (e.g., carrier802). The die may be identical and/or similar to the second die250ofFIG. 3. The die may be a logic die and/or a memory die. The die may include a substrate portion (e.g., silicon substrate), a pad, a first passivation layer, and a second passivation layer, as described for the second die250inFIG. 3. The package interconnect may be identical and/or similar to the package interconnect210ofFIG. 3. The package interconnect includes a first pad (e.g., first pad808) and a first solder interconnect (e.g., first solder interconnect806). The first solder interconnect is coupled to the first pad. The first solder interconnect (e.g., first solder interconnect806) may be solder on pad (SOP) (e.g., coined SOP) or a solder ball.

The method forms (at1010) an encapsulation layer on the die and the package interconnect. The encapsulation layer (e.g., encapsulation layer810) is formed such that the encapsulation layer at least partially encapsulates the die (e.g., die800) and the package interconnect (e.g., package interconnect804). The encapsulation layer may also encapsulate the solder interconnect.

The method then removes (at1015) the carrier from the die, the package interconnect, and the encapsulation layer.

The method forms (at1020) a redistribution portion (e.g., redistribution portion840) on the die and the package interconnect. In some implementations, forming the redistribution portion includes forming a first dielectric layer, forming a first redistribution layer (e.g., first redistribution layer815), forming a second dielectric layer forming a second redistribution layer (e.g., second redistribution layer817), forming a third dielectric layer and/or forming an under bump metallization (UBM) layer (e.g., UBM layer819).

The method provides and couples (at1025) a solder ball (e.g., solder ball820) to the redistribution portion (e.g., coupling a solder ball to a UBM layer).

The method removes (at1030) a portion of the encapsulation layer. In some implementations, removing a portion of the encapsulation layer includes using a laser process (e.g., laser ablation) to remove portions of the encapsulation layer and expose the solder interconnect (e.g., solder interconnect) previously encapsulated by the encapsulation layer. In some implementations, removing a portion of the encapsulation layer may optionally include grinding a portion of the encapsulation layer.

The method couples (at1035) a first package (e.g., first package202) to the package interconnect to form a package on package (PoP) device. In some implementations, a solder ball (e.g., solder interconnect400) from the first package is coupled to the solder interconnect (e.g., first solder interconnect806) coupled to the pad of the package interconnect. The solder ball and the solder interconnect may form a solder interconnect (e.g., solder interconnect270). In some implementations, the surface of the pad that is coupled to the solder interconnect (e.g., first solder interconnect806) has a surface roughness Ravalue that is about 1 micron (μm) or less.

Exemplary Package on Package (PoP) Devices Comprising Solder Connections

As mentioned above, different implementations may use different packages as the top package in the package on package (PoP) device200. For example, the top package of a package on package (PoP) device may include a fan out wafer level package (FOWLP), a wire bond chip scale package, and/or a flip chip chip scale package. In some implementations, several top packages may be formed on a bottom package to form a package on package (PoP) device.FIGS. 11-13illustrate examples of different package on package (PoP) devices with different package combinations.

FIG. 11illustrates a package on package (PoP) device1100that includes a first package1102(e.g., first integrated circuit device package) and the second package204(e.g., second integrated circuit device package), where the first package1102is coupled to the second package204through at least one solder interconnect270.

The package on package (PoP) device1100is similar to the package on package (PoP) device200, except that the first package202has been replaced with the first package1102. The first package1102(e.g., first integrated circuit device package) includes a first package substrate1110and a first die1120. The first package substrate1110includes several metal layers. The first die1120may be a flip chip die.

FIG. 12illustrates a package on package (PoP) device1200that includes a first package1202(e.g., first integrated circuit device package) and the second package204(e.g., second integrated circuit device package), where the first package1202is coupled to the second package204through at least one solder interconnect270.

The package on package (PoP) device1200is similar to the package on package (PoP) device200, except that the first package202has been replaced with the first package1202. The first package1202(e.g., first integrated circuit device package) may be a fan out wafer level package (FOWLP) that includes a second redistribution portion1240, a first die1250, and a second encapsulation layer1260.

As shown inFIG. 12, the second redistribution portion1240of the first package1202, is coupled to the package interconnect210of the second package204, through at least one solder interconnect270. The at least one solder interconnect270may be coupled to a redistribution layer and/or a UBM layer of the second redistribution portion1240. The second redistribution portion1240is similar to the redistribution portion240, in that the second redistribution portion1240includes at least one redistribution layer, at least one dielectric layer and/or a UBM layer.

FIG. 13illustrates another package on package (PoP) device1300. The package on package (PoP) device1300is similar to the package on package (PoP) device200ofFIG. 2, except that the package on package (PoP) device1300includes more dies. The package on package (PoP) device1300includes a first package1302and a second package1304.

As shown inFIG. 13, the first package1302includes the first package substrate220, the first die230, a third die1330, the wire bond290(e.g., at least one wire bond), and the second wire bond1390. The first die230is coupled to the wire bond290. The third die1330is coupled to the second wire bond1390. The third die1330is coupled (e.g., mounted) on the first die230(e.g., through an adhesive). However, in some implementations, the third die1330may be co-planar to the first die230. That is, the third die1330may be coupled (e.g., mounted) on the first package substrate220. The wire bond290and the second wire bond1390are coupled to the first package substrate220in a similar manner. The second wire bond1390may be coupled to interconnects (e.g., vias, pads, traces) in the first package substrate220, which is coupled to a solder interconnect (e.g., solder interconnect270).

The second package1304includes the redistribution portion240, the second die250, the package interconnect210, a fourth die1350, the encapsulation layer260, and the solder ball280. The second die250and the fourth die1350are coupled to the redistribution portion240. The second die250and the fourth die1350may be co-planar to each other. The redistribution portion240may be a fan out portion. The encapsulation layer260at least partially encapsulates or surrounds the second die250and the fourth die1350.

In some implementations, the package on package (PoP) device1300may also include electronic components. Examples of electronic components include a radio frequency (RF) filter, a power amplifier and a passive device (e.g., capacitor, inductor). These electronic components may be located in the first package1302and/or the second package1304. These electronic components may be electrically coupled in the package on package (PoP) device1300in a similar manner as the dies. For example these electronic components may be electrically coupled through wire bond. These electronic components may be encapsulated by the encapsulation layer260. For example, any of the dies described in the package on package (PoP) device1300may be replaced by an electronic component. In a similar manner, it is noted that any of the package on package (PoP) devices described in the present disclosure may include at least one electronic component (e.g., radio frequency (RF) filter, power amplifier, passive device).

FIG. 13illustrates one example of a package on package (PoP) device that includes more than two dies. It is noted that any of the package on package (PoP) devices described in the present disclosure may be modified to include more than two dies. For example, the package on package (PoP) devices1100, and/or1200may be modified in a similar manner to include more than two dies and/or include at least one electronic component (e.g., radio frequency (RF) filter, power amplifier, passive device).

Exemplary Electronic Devices

FIG. 14illustrates various electronic devices that may be integrated with any of the aforementioned integrated device, semiconductor device, integrated circuit, die, interposer, package or package-on-package (PoP). For example, a mobile phone device1402, a laptop computer device1404, and a fixed location terminal device1406may include an integrated device1400as described herein. The integrated device1400may be, for example, any of the integrated circuits, dies, integrated devices, integrated device packages, integrated circuit devices, package-on-package devices described herein. The devices1402,1404,1406illustrated inFIG. 14are merely exemplary. Other electronic devices may also feature the integrated device1400including, but not limited to, a group of devices (e.g., electronic devices) that includes mobile devices, hand-held personal communication systems (PCS) units, portable data units such as personal digital assistants, global positioning system (GPS) enabled devices, navigation devices, set top boxes, music players, video players, entertainment units, fixed location data units such as meter reading equipment, communications devices, smartphones, tablet computers, computers, wearable devices, servers, routers, electronic devices implemented in automotive vehicles (e.g., autonomous vehicles), or any other device that stores or retrieves data or computer instructions, or any combination thereof.

One or more of the components, features, and/or functions illustrated inFIGS. 2, 3, 4, 5, 6, 7, 8A-8C, 9A-9C, 10, 11, 12, and/or13,14may be rearranged and/or combined into a single component, feature or function or embodied in several components, or functions. Additional elements, components, and/or functions may also be added without departing from the disclosure. It should also be noted thatFIGS. 2, 3, 4, 5, 6, 7, 8A-8C, 9A-9C, 10, 11, 12, 13 and/or 14and its corresponding description in the present disclosure is not limited to dies and/or ICs. In some implementations,FIGS. 2, 3, 4, 5, 6, 7, 8A-8C, 9A-9C, 10, 11, 12, 13 and/or 14and its corresponding description may be used to manufacture, create, provide, and/or produce integrated devices. In some implementations, a device may include a die, an integrated device, a die package, an integrated circuit (IC), an integrated device package, a wafer, a semiconductor device, a package on package (PoP) device, and/or an interposer.

The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any implementation or aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects of the disclosure. Likewise, the term “aspects” does not require that all aspects of the disclosure include the discussed feature, advantage or mode of operation. The term “coupled” is used herein to refer to the direct or indirect coupling between two objects. For example, if object A physically touches object B, and object B touches object C, then objects A and C may still be considered coupled to one another-even if they do not directly physically touch each other.