Ultrahigh vacuum deposition of silicon (Si-Ge) on HMIC substrates

The present invention presents a method in which semiconductor heterojunction and homojunction materials are selectively formed on silicon pedestals in an HMIC after the high temperature processing steps in fabricating the HMIC structure are completed.

FIELD OF THE INVENTION 
The present invention relates to a novel technique for application of 
epitaxial material to form necessary semiconductor interfaces and 
barriers. 
BACKGROUND OF THE INVENTION 
The present invention is related to U.S. Provisional Patent Applications 
Numbers 60/017,120 and 60/013,982 and U.S. Pat. No. 5,268,310 the 
disclosure of which are specifically incorporated herein by reference. The 
use of silicon as a material in microwave and of applications in the past 
had generally been discouraged. This is due to the fact that silicon has a 
greater electrical conductivity than other materials used in the industry, 
for example gallium arsenide. This conductivity results in power 
dissipation and heating effects at high frequencies. Accordingly, gallium 
arsenide has been the preferred material for fabrication of devices and 
integrated circuits and the microwave and rf industries. However, in the 
recent past, heterolithic microwave integrated circuits (HMIC) have been 
utilized to enable high frequency integrated circuits using silicon as the 
base material for the circuits. In HMIC applications, silicon pedestals 
are fabricated having glass material suitable for high frequency 
application disposed between the pedestals to form the electrical 
isolation between the pedestals and as the dielectric for signal lines on 
the integrated circuit. Examples of such HMIC structures are as disclosed 
above in the above U.S. Provisional Patent Applications, the disclosures 
of which are specifically incorporated by reference. 
While the above referenced patent applications enable reliable high yield 
and mass produced integrated circuits for applications at high frequency, 
there are certain drawbacks to fabrication of devices on the integrated 
circuits described above. To this end, it is often required to have a 
semiconductor homojunction and heterojunction barrier device fabricated at 
one or more of the silicon pedestal sites. This is generally done by 
epitaxial growth of suitably doped Si or Si--Ge on the n.sup.+ doped 
pedestals. During the processing at high temperature, the semiconductor 
homojunction and heterojunction doping profiles are often degraded. By way 
of example, the doping profile of an ideal Schottky barrier is as shown in 
FIG. 4. In the n.sup.- region, the material is lightly doped. A 
relatively sharp interface is achieved in the high doped substrate region 
as is shown. The degraded doping profile is as shown superposed on the 
ideal doping profile. While it is desired to have the silicon based 
HMIC's, it is none the less required to have a functional homojunction and 
heterojunction doping profile in many applications. Accordingly, there is 
a need to fabricate a doping profile at the pedestal/semiconductor barrier 
which is not degraded during the fabrication of the HMIC. 
SUMMARY OF THE INVENTION 
The present invention relates to a new process for fabricating HMIC 
structures having the required epitaxially grown layers on silicon 
pedestals. The present invention enables the fabrication of semiconductor 
material interfaces having the desired doping profiles without degradation 
during the processing. In order to effect this doping profile, the HMIC is 
fabricated having all of the high temperature processing steps completed 
prior to deposition of the epitaxial material on the selected surfaces of 
the silicon pedestals. In this way, the homojunctions and heterojunctions 
which are often required in HMIC structures are fabricated at a point in 
processing the HMIC where all deleterious temperature cycles and 
mechanically challenging steps as described in the above referenced patent 
applications have been completed. Thereby, junction performance is 
maintained in the HMIC structure. Furthermore, yield, performance and 
process simplicity are all improved. 
OBJECTS, FEATURES, AND ADVANTAGES 
It is an object of the present invention to have a heterolithic microwave 
integrated circuit where semiconductor heterojunction and homojunction 
barriers are formed without degradation due to deleterious temperature 
cycles and mechanically challenging processing steps. 
It is a feature of the present invention to have semiconductor 
heterojunction and homojunction barriers selectively formed on silicon 
pedestals in an HMIC after the high temperature processing steps in 
fabricating the HMIC structure are completed. 
It is an advantage of the present invention to have an improved yield, 
performance and process simplicity.

DETAILED DESCRIPTION OF THE INVENTION 
As stated above, the passive glass substrate of the HMIC is as shown in 
FIG. 1. This substrate has selectively fabricated silicon pedestals 101 
and glass material 102 disposed between the silicon pedestals 101. The 
passive glass substrate of FIG. 1 is fabricated as is disclosed in the 
above referenced patent applications to Boles, et al. In order to 
fabricate the eptiaxial layer of the present invention, a low temperature 
oxide for example SiO.sub.x or other material such as Si.sub.3 N.sub.4 is 
deposited on the top surface 103 of the substrate. Thereafter, windows 201 
are fabricated on the LTO or other suitable mask material. As is shown in 
FIG. 2, the LTO mask covers a portion of the top surface of the pedestals, 
as it is desired to have the epi-layer in a selected portion of the top 
surface of the pedestal, but not necessarily across the entire top surface 
of the pedestal. The removal of the selected portion of the oxide to form 
the windows is done by standard etching techniques. Thereafter, silicon is 
deposited by standard ultra-high vacuum chemical vapor deposition 
techniques across the top surface of the substrate, forming epitaxial 
silicon on the exposed portion of the pedestal, and polysilicon on all 
other portions. This deposition is pseudoselective in nature, as true 
selective deposition results in no deposition on the masking areas. 
However, the windows in the LTO mask where the top surface of the silicon 
pedestals is found, monocrystalline growth is realized, whereas elsewhere 
a polycrystalline growth is effected. This poly Si can be readily etched 
through standard technique. In order to etch the poly Si off of the top 
surface of the substrate, a protective layer of silicon nitride or other 
suitable low temperature oxide is deposited across the top surface. 
Thereafter, the polysilicon is etched off through standard etching 
techniques. Finally, a standard etching technique is used to remove the 
low temperature oxide or other suitable material in a manner that will not 
damage the epitaxially grown layer. 
The above description has focused primarily on the fabrication of 
semiconductor homojunctions, for example schottky barrier devices. 
Alternatively, heterojunctions can be fabricated through similar 
techniques to form devices such as bipolar junction transistors. The basic 
fabrication of semiconductor heterojunctions is as in the fabrication of 
homojunctions as described above. To this end, the silicon pedestals as 
desired or fabricated and glass is disposed between the pedestals as 
described above in relatively high temperature processing steps. 
Thereafter, the polishing of the substrate as is described in the above 
referenced patent applications is carried out. In order to fabricate the 
heterojunction, generally Si--Ge is utilized. To this end, for example an 
HBT can be fabricated. The pedestal can be the collector of the device. 
Alternatively, the collector can be formed epitaxially. In all cases an 
emitter and a base are formed thereafter through epitaxial processing 
steps as described above. To this end, the base is fabricated by epitaxial 
deposition of Si--Ge, whereas the emitter and collectors are fabricated 
through epitaxial deposition of silicon. Finally, in both the 
heterojunction and homojunction device fabrication, electrical contact to 
the device, passive and active devices as well as signal transmission 
lines and contact metallization are formed by standard techniques. 
The invention having been described in detail, it is clear that other 
materials as well as processing steps for the fabrication of selected 
epitaxial layers on HMIC pedestals is within the purview of one of 
ordinary skill in the art. To the extent that such variations in materials 
and processes are within the purview of the ordinary skilled artisan, such 
modifications and variations are deemed within the scope of the invention 
disclosed herein.