Replacement metal gate semiconductor device formation using low resistivity metals

Embodiments of the present invention relate to approaches for forming RMG FinFET semiconductor devices using a low-resistivity metal (e.g., W) as an alternate gap fill metal. Specifically, the semiconductor will typically comprise a set (e.g., one or more) of dielectric stacks formed over a substrate to create one or more trenches/channels (e.g., short/narrow and/or long/wide trenches/channels). A work function layer (e.g., TiN) will be provided over the substrate (e.g., in and around the trenches). A low-resistivity metal gate layer (e.g., W) may then be deposited (e.g., via chemical vapor deposition) and polished (e.g., via chemical-mechanical polishing). Thereafter, the gate metal layer and the work function layer may be etched after the polishing to provide a trench having the etched gate metal layer over the etched work function layer along a bottom surface thereof.

BACKGROUND

1. Technical Field

This invention relates generally to the field of semiconductors and, more particularly, to approaches for using low resistivity metals (e.g., tungsten (W)) for forming fin-type field effect transistor (FinFET) devices such as replacement metal gate (RMG) FinFET semiconductor devices.

2. Related Art

As the semiconductor industry attempts to utilize 22 nm technology, a transition from planar complimentary metal-oxide semiconductor (CMOS) transistors to a three-dimensional (3D) FinFET device architecture has been considered. Relative to planar transistors, FinFETs offer improved channel control and, therefore, reduced short channel effects. While the gate in a planar transistor sits above the device's channel, the gate of a FinFET typically “wraps” around the channel, providing electrostatic control from both sides. Moreover, a 3D structure introduces new parasitic capacitances and new critical dimensions that must be controlled to optimize performance. Such continuous scaling of CMOS devices requires a noble metal gap fill method in RMG CMOS device fabrication.

Conventional metal gap fill in RMG CMOSFET is typically performed using aluminum (Al) metal. However, uncontrolled Al diffusion into metal gate electrodes may result in metal work function (Vt) variability, causing device performance variation. Thus, tungsten (W) is considered to be used as an alternative gap fill metal. In this case, however, a low work function (WF) (<4.4 eV) of a metal gate electrode is needed for negative channel field effect transistor (NFET) Vt tuning prior to W. As devices scale down in dimensions, the gate length (Lg) of the devices shrinks as well (e.g., down to 20 nm). As such, the resistivity of such low WF metals may be too high to be used in small gate length devices.

SUMMARY

In general, embodiments of the present invention relate to approaches for forming RMG FinFET semiconductor devices using a low-resistivity metal (e.g., W) as an alternate gap fill metal. Specifically, the semiconductor will typically comprise a set (e.g., one or more) of dielectric stacks formed over a substrate to create one or more trenches/channels (e.g., short/narrow and/or long/wide trenches/channels). A work function layer (e.g., TiN) will be provided over the substrate (e.g., in and around the trenches). A low-resistivity metal gate layer (e.g., W) may then be deposited (e.g., via chemical vapor deposition) and polished (e.g., via chemical-mechanical polishing). Thereafter, the gate metal layer and the work function layer may be etched after the polishing to provide a trench having the etched gate metal layer over the etched work function layer along a bottom surface thereof.

A first aspect of the present invention provides a method of forming a semiconductor device, comprising: applying a metal layer over a work function layer of the semiconductor device; polishing the metal layer; and etching the metal layer and the work function layer after the polishing to provide a trench, the trench having the etched metal layer over the etched work function layer along a bottom surface of the trench.

A second aspect of the present invention provides a method of forming a semiconductor device, comprising: depositing a gate metal layer over a work function layer of the semiconductor device; polishing the gate metal layer; performing a first etching of the semiconductor device, the first etching comprising an etching of the gate metal layer and the work function layer; and performing a second etching of the semiconductor device, the second etching comprising an additional etching of the gate metal layer and the work function layer to create a trench in the semiconductor structure, the trench comprising the gate metal layer over the work function layer along a bottom surface of the trench.

A third aspect of the present invention provides a method of forming a FinFET semiconductor device, comprising: applying a gate metal layer over a work function layer of the semiconductor device; polishing the gate metal layer; performing a first etching of the semiconductor device, the first etching comprising an etching of the gate metal layer and the work function layer; and performing a second etching of the semiconductor device, the second etching comprising an additional etching of the gate metal layer and the work function layer to create a trench in the semiconductor structure, the trench comprising a first work function layer along a bottom surface of the trench, a first gate metal layer over a first work function layer, a second work function layer over the first gate metal layer, and a second gate metal layer over the second work function layer.

A fourth aspect of the present invention provides a device, comprising: a substrate; a set of gate stacks positioned on the substrate, the set of gate stacks forming at least one trench in the device; and the at least one trench having a first work function layer positioned on the substrate, a first gate metal layer positioned on the first work function layer, a second work function layer positioned on the first gate metal layer, and a second gate metal layer positioned on the second work function layer.

DETAILED DESCRIPTION

Illustrative embodiments will now be described more fully herein with reference to the accompanying drawings, in which embodiments are shown. This disclosure may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of this disclosure to those skilled in the art. In the description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments.

The terms “overlying” or “atop”, “positioned on” or “positioned atop”, “underlying”, “beneath” or “below” mean that a first element, such as a first structure (e.g., a first layer) is present on a second element, such as a second structure (e.g. a second layer) wherein intervening elements, such as an interface structure (e.g. interface layer) may be present between the first element and the second element.

As indicated above, embodiments of the present invention relate to approaches for forming RMG FinFET semiconductor devices using a low-resistivity metal (e.g., W) as an alternate gap fill metal. Specifically, the semiconductor will typically include a set (e.g., one or more) of dielectric stacks formed over a substrate to create one or more trenches/channels (e.g., short/narrow and/or long/wide trenches/channels). A work function layer (e.g., TiN) will be provided over the substrate (e.g., in and around the trenches). A low-resistivity metal gate layer (e.g., W) may then be deposited (e.g., via chemical vapor deposition) and polished (e.g., via chemical-mechanical polishing). Thereafter, the gate metal layer and the work function layer may be etched after the polishing to provide a trench having the etched gate metal layer over the etched work function layer along a bottom surface thereof.

A common way is to etch away the part of WF metals and replace the etched part with a low resistivity metal such as W (tungsten). The metal etching process should not attack high-k underneath WF metal. The metal thickness should be thick enough to fill out the gate trench hole so that the metal etching process cannot hit bottom metal near high-k during metal etch (because etching is done far away from the bottom). However, this is applicable for a short gate length area. For larger and longer devices there are thin metals on top of high-k. Thus, such larger and longer gate devices should be protected from WF metal etching. There are several approaches to protect larger and longer gate devices.

Referring now toFIGS. 1A-E, a previous approach for device fabrication is shown. As shown, a work function metal layer10may be applied over a substrate12and dielectric stacks14A-B (S1), over which a mask layer16may be provided (S2). The mask layer16may then be etched (S3), and the work function layer10(and remaining mask layer16) may be selectively removed (S4) to reveal trenches. Thereafter, a metal layer18may be applied to fill the trenches. Unfortunately, under the process of steps S1-S5, it may be difficult to apply hard mask or soft mask materials on a larger gate area. As such, an additional step may be needed to remove such mask materials after work function layer etching occurs.

Referring now toFIGS. 2A-D, another previous approach for device fabrication is shown. As shown, a work function metal layer20may be applied over a substrate22and dielectric stacks24A-B (P1), over which a blocking mask layer26may be provided (P2). The work function layer20may be removed around the mask (P2). The mask layer26may then be removed and a metal gate layer28may thereafter be applied (P3) to fill the remaining trenches. The metal gate layer28may then be etched to finish the device (P4). The process of steps P1-P4unfortunately requires an additional blocking mask which not only adds to overall fabrication costs, but also complicates lithography, mask design, alignment, and/or measurement.

Referring now toFIGS. 3A-D, an approach for forming/fabricating a semiconductor device/interconnect (device50) according to an embodiment of the present invention is shown. In general, device50includes a RMG FinFET device having a set of trenches/channels (e.g., short/narrow trenches62A-B, long/wide trench64, etc.). Regardless, the progression of forming device50is shown throughout steps A1-A4. As shown, in step A1, a work function layer52(e.g., TiN) is applied over substrate54and around dielectric stacks56A-B, and spacers58A-B. A (low resistivity) gate metal layer60(e.g., W) may then be deposited (e.g., via chemical vapor deposition) over work function layer52. In step A2, the gate metal layer60may be polished (e.g., via chemical mechanical polishing). In steps A3-A4, the gate metal layer60and the work function layer52may be etched (e.g., in an ion etch chamber) after the polishing to provide trenches62A-B and64. As shown, trench64has the etched gate metal layer60positioned over the etched work function layer52along a bottom surface of the trench64, while etched work function layer52remains along bottoms surfaces of trenches62A-B.

Referring now toFIGS. 4A-D, an approach for forming/fabricating a semiconductor device/interconnect (device70) according to an embodiment of the present invention is shown. In general, device70includes a RMG FinFET device having a set of trenches/channels (e.g., short/narrow trenches82A-B, long/wide trench84, etc.). Regardless, the progression of forming device70is shown throughout steps B1-B4. As shown, in step B1, a low resistivity gate metal layer80(e.g., W) is deposited over a work function layer72(e.g., TiN), which itself is applied over a substrate74, dielectric stacks76A-B, and spacers78A-B of device70. In step B2, the gate metal layer80is polished. In step B3-B4, multiple etchings of device70are performed. For example, in step B3, a first etching includes an etching of the gate metal layer80and the work function layer72. In step B4, a second etching, including an additional etching of the gate metal layer80and the work function layer72, is performed. This second etching results in the creation of trenches82A-B and84. Long trench84includes the gate metal layer80over the work function layer72along a bottom surface of the trench84, while short trenches82A-B include work function layer72along the bottom surfaces thereof.

Referring now toFIGS. 5A-B, an approach for forming/fabricating a semiconductor device/interconnect (device100) according to an embodiment of the present invention is shown. In general, device100includes a RMG FinFET device having a set of trenches/channels (e.g., short/narrow trenches112A-B, long/wide trench114, etc.). Regardless, the progression of forming device70is shown in steps C1-C2(and may be similar to steps A1-A4ofFIG. 3and/or steps B1-B4ofFIG. 4). In general, a work function layer (TiN)102is applied over substrate104, dielectric stacks106A-B, and spacers108A-B. A high resistivity gate metal layer110(e.g., W) is then applied (e.g., via CVD) over work function layer102. Similar toFIGS. 3and/or4, gate metal layer110may then be polished, and one or more etchings steps may be performed on gate metal layer110and work function layer102. The etchings(s) will result in work function layer102and gate metal layer110residing in short trenches112A-B. However, as shown, long trench114will have multiple, alternating layers of work function layer102A-B and gate metal layer110A-B as shown.

Referring now toFIG. 6, a graph150of etch rates versus temperature is shown. Specifically, graph150shows etch rates at various temperatures for TiN152A, Ti152B, and W152C. As shown, W etches at the highest rate at a temperature of approximately 50° (C.), which makes it highly useable in the processes described herein.

In various embodiments, design tools can be provided and configured to create the data sets used to pattern the semiconductor layers as described herein. For example data sets can be created to generate photomasks used during lithography operations to pattern the layers for structures as described herein. Such design tools can include a collection of one or more modules and can also include hardware, software, or a combination thereof. Thus, for example, a tool can be a collection of one or more software modules, hardware modules, software/hardware modules or any combination or permutation thereof. As another example, a tool can be a computing device or other appliance on which software runs or in which hardware is implemented. As used herein, a module might be implemented utilizing any form of hardware, software, or a combination thereof. For example, one or more processors, controllers, application-specific integrated circuits (ASIC), programmable logic arrays (PLA)s, logical components, software routines, or other mechanisms might be implemented to make up a module. In implementation, the various modules described herein might be implemented as discrete modules or the functions and features described can be shared in part or in total among one or more modules. In other words, as would be apparent to one of ordinary skill in the art after reading this description, the various features and functionality described herein may be implemented in any given application and can be implemented in one or more separate or shared modules in various combinations and permutations. Even though various features or elements of functionality may be individually described or claimed as separate modules, one of ordinary skill in the art will understand that these features and functionality can be shared among one or more common software and hardware elements, and such description shall not require or imply that separate hardware or software components are used to implement such features or functionality.

While the invention has been particularly shown and described in conjunction with exemplary embodiments, it will be appreciated that variations and modifications will occur to those skilled in the art. For example, although the illustrative embodiments are described herein as a series of acts or events, it will be appreciated that the present invention is not limited by the illustrated ordering of such acts or events unless specifically stated. Some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein, in accordance with the invention. In addition, not all illustrated steps may be required to implement a methodology in accordance with the present invention. Furthermore, the methods according to the present invention may be implemented in association with the formation and/or processing of structures illustrated and described herein as well as in association with other structures not illustrated. Therefore, it is to be understood that the appended claims are intended to cover all such modifications and changes that fall within the true spirit of the invention.