Shared address counters for multiple modes of operation in a memory device

As described above, certain modes of operation, such as the Fast Zero mode and the ECS mode, may facilitate sequential access to individual cells of a memory array. To facilitate this functionality, a command controller may be provided, including one or more individual controllers to control the address sequencing when a particular mode entry command (e.g., Fast Zero or ECS) is received. In order to generate internal addresses to be accessed sequentially, one or more counters may also be provided. Advantageously, the counters may be shared such that they can be used in any mode of operation that may require address sequencing of all or large portions of the memory array, such as the Fast Zero mode or the ECS mode.

BACKGROUND

Embodiments described herein relate generally to the field of memory devices. More specifically, the current embodiments include one or more systems, devices, and methods for utilizing shared address counters for multiple modes of operation.

DESCRIPTION OF RELATED ART

Various modes of operation in memory devices may require access to large sections or all of the memory array on the memory device. For instance, in certain instances, such as testing, the memory device may be set to a mode such that each memory cell of the memory array may be individually accessed. The accessing of each memory cell in certain modes of operation may be an iterative process such that each of the memory cells in the memory array is sequentially accessed. In order to facilitate such functionality, it may be desirable to provide fast and efficient methods and structures for allowing sequential access to each memory cell in a sequential manner. Further, such sequential access should be provided without necessitating the usage of extra hardware components which may increase cost of the memory device and increase the size of the memory device. Accordingly, embodiments described herein may be directed to one or more of the problems set forth above.

DETAILED DESCRIPTION

As is described in detail below, memory devices may employ modes of operation that facilitate sequential access to all memory cells or large blocks of memory cells in a memory array. For instance, in double data rate type five synchronous dynamic random access memory (DDR5 SDRAM), certain modes of operation, such as the Fast Zero mode and the Error, Check and Scrub (ECS) mode, provide that each cell of the memory array is sequentially accessed. In order to sequentially access each memory cell, one or more commands may be received by the memory device. Controllers in the memory device may be used to generate internal memory addresses such that each cell can be individually accessed. One or more counters may be used to sequence through internal addresses to access each memory cell of the array. Because counters may increase the cost and/or size of the memory device, present embodiments share the same counters in utilizing each of the Fast Zero mode and the ECS mode, to minimize the additional hardware used to generate the address sequencing to access the entire memory array.

Referring now toFIG. 1, a simplified block diagram of a computer system10is illustrated. The computer system10includes a controller12and a memory device14. The controller12may include processing circuitry, such as one or more processors16(e.g., one or more microprocessors), that may execute software programs to provide various signals to the memory device14over one or more bi-directional communication buses18to facilitate the transmission and receipt of data to be written to or read from the memory device14. Moreover, the processor(s)16may include multiple microprocessors, one or more “general-purpose” microprocessors, one or more special-purpose microprocessors, and/or one or more application specific integrated circuits (ASICS), or some combination thereof. For example, the processor(s)16may include one or more reduced instruction set (RISC) processors. The controller12may be coupled to one or more memories20that may store information such as control logic and/or software, look up tables, configuration data, etc. In some embodiments, the processor(s)16and/or the memory20may be external to the controller12. The memory20may include a tangible, non-transitory, machine-readable-medium, such as a volatile memory (e.g., a random access memory (RAM)) and/or a nonvolatile memory (e.g., a read-only memory (ROM), flash memory, a hard drive, or any other suitable optical, magnetic, or solid-state storage medium, or a combination thereof). The memory20may store a variety of information and may be used for various purposes. For example, the memory20may store machine-readable and/or processor-executable instructions (e.g., firmware or software) for the processor(s)16to execute, such as instructions for providing various signals and commands to the memory device14to facilitate the transmission and receipt of data to be written to or read from the memory device14.

The memory device14includes a memory array22of individual memory cells. As described further below, the memory array22may include one or more memory banks that may be grouped or partitioned in a variety of ways to provide access to the cells of the memory array22, as described below. The controller12may communicate with the memory device14through one or more command and input/output (I/O) interfaces24. In general, the command and input/output interfaces24provide access to various components of the memory device14by external devices, such as the controller12.

The memory device14may include a command decoder26. The command decoder26may receive command signals from the command and input/output (I/O) interfaces24and may decode the command signals to provide various internal commands. For instance, the command decoder26may decode commands, such as read commands, write commands, mode-register set commands, activate commands, etc., and provide access to specified regions of the memory array22. As described above, certain modes of operation, such as the Fast Zero mode and the ECS mode, may facilitate sequential access to individual cells of the memory array22. To facilitate this functionality, the command decoder26includes a command controller28that includes one or more individual controllers to control the address sequencing when a particular mode entry command (e.g., Fast Zero or ECS) is received. Further, in order to generate internal addresses to be accessed sequentially, one or more counters30may also be provided. Advantageously, the counters30may be shared such that they can be used in any mode of operation that may require address sequencing of all or large portions of the memory array22, such as the Fast Zero mode or the ECS mode. The use and implementation of the command controller28and the counters30will be described in greater detail below with regard toFIGS. 3-5. It should be noted that while the command controller28and counters30are illustrated as being part of the command decoder26, alternatively, these elements may be provided elsewhere on the memory device14.

FIG. 2is a simplified block diagram illustrating certain additional features of the memory device14ofFIG. 1. Specifically, the block diagram ofFIG. 2is a functional block diagram illustrating certain additional features and related functionality of the memory device14. In accordance with one embodiment, the memory device14may be a double data rate type five synchronous dynamic random access memory (DDR5 SDRAM) device. Various features of DDR5 SDRAM allow for reduced power consumption, more bandwidth and more storage capacity compared to prior generations of DDR SDRAM.

The memory device14, may include a memory array logically and functionally grouped into a number of memory banks32. The memory banks32may be DDR5 SDRAM memory banks, for instance. The memory banks32may be provided on one or more chips (e.g., SDRAM chips) that are arranged on dual inline memory modules (DIMMS). Each DIMM may include a number of SDRAM memory chips (e.g., ×8 or ×16 memory chips), as will be appreciated. Each SDRAM memory chip may include one or more memory banks32. The memory device14represents a portion of a single memory chip (e.g., SDRAM chip) having a number of memory banks32. For DDR5, the memory banks32may be further arranged to form bank groups. For instance, for an 8 gigabit (Gb) DDR5 SDRAM, the memory chip may include 16 memory banks32, arranged into 8 bank groups, each bank group including 2 memory banks. For a 16 Gb DDR5 SDRAM, the memory chip may include 32 memory banks32, arranged into 8 bank groups, each bank group including 4 memory banks, for instance. Various other configurations, organization and sizes of the memory banks32on the memory device14may be utilized depending on the application and design of the overall system.

As previously described, the memory device14may include one or more command and input/output (I/O) interfaces. For instance, the memory device14may include a command interface34and an input/output (I/O) interface36. The command interface34is configured to provide a number of signals (e.g., signals38) from an external device (not shown), such as a processor or controller. The processor or controller may provide various signals38over one or more bi-directional data buses (e.g., data bus18) to and from the memory device14to facilitate the transmission and receipt of data to be written to or read from the memory device14.

As will be appreciated, the command interface34may include a number of circuits, such as a clock input circuit40and a command address input circuit42, for instance, to ensure proper handling of the signals38. The command interface34may receive one or more clock signals from an external device. Generally, double data rate (DDR) memory utilizes a differential pair of system clock signals, referred to herein as the true clock signal (Clk_t/) and the complementary clock signal (Clk_c). The positive clock edge for DDR refers to the point where the rising true clock signal Clk_t/crosses the falling complementary clock signal Clk_c, while the negative clock edge indicates that transition of the falling true clock signal Clk_t and the rising of the complementary clock signal Clk_c. Commands (e.g., read command, write command, etc.) are typically entered on the positive edges of the clock signal and data is transmitted or received on both the positive and negative clock edges.

The clock input circuit40receives the true clock signal (Clk_t/) and the complementary clock signal (Clk_c) and generates an internal clock signal CLK. The internal clock signal CLK is supplied to an internal clock generator44, such as a delay locked loop (DLL) circuit. The internal clock generator44generates a phase controlled internal clock signal LCLK based on the received internal clock signal CLK. The phase controlled internal clock signal LCLK is supplied to the I/O interface36, for instance, and is used as a timing signal for determining an output timing of read data.

The internal clock signal CLK may also be provided to various other components within the memory device14and may be used to generate various additional internal clock signals. For instance, the internal clock signal CLK may be provided to a command decoder26. The command decoder26may receive command signals from the command bus46and may decode the command signals to provide various internal commands. For instance, the command decoder26may provide command signals to the internal clock generator44over the bus48to coordinate generation of the phase controlled internal clock signal LCLK. The phase controlled internal clock signal LCLK may be used to clock data through the I/O interface36, for instance.

Further, the command decoder26may decode commands, such as read commands, write commands, activate commands, mode-register set commands, such as Fast Zero Entry and ECS commands, etc., and provide access to a particular memory bank32corresponding to the command, via the bus path50. As will be appreciated, the memory device14may include various other decoders, such as row decoders and column decoders, to facilitate access to the memory banks32. In one embodiment, each memory bank32includes a bank control block54which provides the necessary decoding (e.g., row decoder and column decoder), as well as other features, such as timing control and data control, to facilitate the execution of commands to and from the memory banks32.

As previously described with regard toFIG. 1and described further below with regard toFIGS. 3-5, the command decoder26may include one or more command controllers28to facilitate certain functions, such as implementation of the Fast Zero Entry mode and ECS mode of operation. In addition, the command decoder26may include one or more counters30that may be utilized under control of the command controller(s)28to generate internal addresses for sequential access of cells of the individual storage locations within each memory bank32, as described in greater detail below. Advantageously, by utilizing the same set of counters30for each of the various modes of operation that employ sequential accessing schemes, such as Fast Zero and ECS modes, rather than employing individual counters for each independent mode, the inclusion of additional hardware components (e.g., counters) can be avoided.

The memory device14executes operations, such as read commands and write commands, based on the command/address signals received from an external device, such as a processor. In one embodiment, the command/address bus may be a 14-bit bus to accommodate the command/address signals (CA<13:0>). The command/address signals are clocked to the command interface34using the clock signals (Clk_t/ and Clk_c). The command interface34may include a command address input circuit42which is configured to receive and transmit the commands to provide access to the memory banks32, through the command decoder26, for instance. In addition, the command interface34may receive a chip select signal (CS_n). The CS_n signal enables the memory device14to process commands on the incoming CA<13:0> bus. Access to specific banks32within the memory device14is encoded on the CA<13:0> bus with the commands.

In addition, the command interface34may be configured to receive a number of other command signals. For instance, a command/address on die termination (CA_ODT) signal may be provided to facilitate proper impedance matching within the memory device14. A reset command (RESET_n) may be used to reset the command interface34, status registers, state machines and the like, during power-up for instance. The command interface34may also receive a command/address invert (CAI) signal which may be provided to invert the state of command/address signals CA<13:0> on the command/address bus, for instance, depending on the command/address routing for the particular memory device14. A mirror (MIR) signal may also be provided to facilitate a mirror function. The MIR signal may be used to multiplex signals so that they can be swapped for enabling certain routing of signals to the memory device14, based on the configuration of multiple memory devices in a particular application. Various signals to facilitate testing of the memory device14, such as the test enable (TEN) signal, may be provided, as well. For instance, the TEN signal may be used to place the memory device14into a test mode for connectivity testing.

The command interface34may also be used to provide an alert signal (ALERT_n) to the system processor or controller for certain errors that may be detected. For instance, an alert signal (ALERT_n) may be transmitted from the memory device14if a cyclic redundancy check (CRC) error is detected. Other alert signals may also be generated. Further, the bus and pin for transmitting the alert signal (ALERT_n) from the memory device14may be used as an input pin during certain operations, such as the connectivity test mode executed using the TEN signal, as described above.

Data may be sent to and from the memory device14, utilizing the command and clocking signals discussed above, by transmitting and receiving data signals56through the I/O interface36. More specifically, the data may be sent to or retrieved from the memory banks32over the data path52, which includes a plurality of bi-directional data buses. Data I/O signals, generally referred to as DQ signals, are generally transmitted and received in one or more bi-directional data busses. For certain memory devices, such as a DDR5 SDRAM memory device, the I/O signals may be divided into upper and lower bytes. For instance, for a x16 memory device, the I/O signals may be divided into upper and lower IO signals (e.g., DQ<15:8> and DQ<7:0>) corresponding to upper and lower bytes of the data signals, for instance.

To allow for higher data rates within the memory device14, certain memory devices, such as DDR memory devices may utilize data strobe signals, generally referred to as DQS signals. The DQS signals are driven by the external processor or controller sending the data (e.g., for a write command) or by the memory device14(e.g., for a read command). For read commands, the DQS signals are effectively additional data output (DQ) signals with a predetermined pattern. For write commands, the DQS signals are used as clock signals to capture the corresponding input data. As with the clock signals (Clk_t/ and Clk_c), the data strobe (DQS) signals may be provided as a differential pair of data strobe signals (DQS_t/ and DQS_c) to provide differential pair signaling during reads and writes. For certain memory devices, such as a DDR5 SDRAM memory device, the differential pairs of DQS signals may be divided into upper and lower data strobe signals (e.g., UDQS_t/ and UDQS_c; LDQS_t/ and LDQS_c) corresponding to upper and lower bytes of data sent to and from the memory device14, for instance.

An impedance (ZQ) calibration signal may also be provided to the memory device14through the IO interface36. The ZQ calibration signal may be provided to a reference pin and used to tune output drivers and ODT values by adjusting pull-up and pull-down resistors of the memory device14across changes in process, voltage and temperature (PVT) values. Because PVT characteristics may impact the ZQ resistor values, the ZQ calibration signal may be provided to the ZQ reference pin to be used to adjust the resistance to calibrate the input impedance to known values. As will be appreciated, a precision resistor is generally coupled between the ZQ pin on the memory device14and GND/VSS external to the memory device14. This resistor acts as a reference for adjusting internal ODT and drive strength of the I/O pins.

In addition, a loopback signal (LOOPBACK) may be provided to the memory device14through the I/O interface36. The loopback signal may be used during a test or debugging phase to set the memory device14into a mode wherein signals are looped back through the memory device14through the same pin. For instance, the loopback signal may be used to set the memory device14to test the data output (DQ) of the memory device14. Loopback may include both a data and a strobe or possibly just a data pin. This is generally intended to be used to monitor the data captured by the memory device14at the I/O interface36.

As will be appreciated, various other components such as power supply circuits (for receiving external VDD and VSS signals), mode registers (to define various modes of programmable operations and configurations), read/write amplifiers (to amplify signals during read/write operations), temperature sensors (for sensing temperatures of the memory device14), etc., may also be incorporated into the memory system10. Accordingly, it should be understood that the block diagram ofFIG. 2is only provided to highlight certain functional features of the memory device14to aid in the subsequent detailed description.

Referring now toFIG. 3, a portion of the command decoder26is illustrated. As previously described, in certain modes of operation, each of the individual memory cells of the memory array22may be sequentially accessed. For instance, certain modes of operation, such as the Fast Zero mode and the ECS mode, may facilitate sequential access to individual cells of the memory array22and coordinate the generation of internal memory addresses by the counter30. To facilitate this functionality, the command decoder26includes a command controller28that includes one or more individual controllers60and62to control the address sequencing when a particular mode entry command (e.g., Fast Zero Entry command or ECS Command) is received. In the illustrated embodiment, the command controller28includes a state control fast zero mode controller62configured to receive a Fast Zero Entry command. The Fast Zero Entry command may be asserted by one of the processors16in the external controller12as part of the device power-up and initialization sequence, for instance. The fast zero mode controller62is configured to write logical 0s to each of the memory cells of the memory array22. As will be appreciated, while the fast zero mode of operation is utilized to write logical 0s to each of the memory locations, a similar mode register command could also be used to write other known values to each of the memory locations (e.g., all logical 1s, or a specified and known pattern). When the Fast Zero Entry command is received by the fast zero mode controller62, the fast zero mode controller62will cycle through the entire memory array22, sequentially writing a zero to each memory cell. To sequentially write to each memory cell, one or more counters30may be employed to generate internal memory addresses by sequentially incrementing the counters30. In accordance with one embodiment, the counters30may include a bank group counter64, a bank address counter66, a row address counter68and a column address counter70. The usage of the counters30and execution of the Fast Zero Mode will be described in greater detail below with regard toFIG. 4.

In accordance with the present embodiments, a state control ECS controller60may also be provided to facilitate receipt and control of an ECS command. The ECS command may be utilized to systematically search for errors throughout the memory array22and correct the errors, if possible. As with the fast zero mode controller62, the ECS controller60facilitates the generation of internal memory addresses using the counters30, in order to sequentially access each individual memory cell of the memory array. As will be described in greater detail below with regard toFIG. 5, the ECS controller60may direct the testing of each memory cell for an error, correction of the error if possible, and logging of the error for later reporting.

Advantageously, each of the Fast Zero mode and the ECS mode utilize the same set of counters30to generate the internal memory addresses that facilitate sequential access to each memory cell, for the particular mode of operation. By utilizing the same shared counters30for multiple modes of operation that provide for the generation of internal memory addresses to sequentially access each cell of the memory array22, hardware components and valuable real estate on the memory device may be conserved.

In the present embodiment, four counters are provided in order to facilitate the various groupings of cells for sequential access. Specifically, a bank group counter64is provided to switch from one bank group to another during sequential accessing of the memory array22. In one embodiment, the memory array22may include four bank groups and the bank group counter64is a 2-bit counter. A bank address counter66is also provided to switch from one bank to another during sequential accessing of the memory array22. In one embodiment, the memory array22may include two or four banks per one bank group and the bank address counter66is a 1-bit or 2-bit counter. A row address counter68is also provided to switch from one row to another during sequential accessing of the memory array22. In one embodiment, the memory array22may include 32,768 rows and the row address counter68is a 16-bit counter. Finally, in the illustrated embodiment, a column address counter70is also provided to switch from one column to another during sequential accessing of the memory array22. In one embodiment, the memory array22may include 128 columns and the column address counter70is a 7-bit counter.

While the presently described embodiments include counters30that are shared when the memory device14is in a Fast Zero Mode of operation or an ECS mode of operation, the counters30may be shared for other modes of operation, as well. For instance, if other test or setup modes employ sequential accessing of the entire memory array22, or large portions of the memory array (e.g., an entire memory bank or bank group), the counters30can also be shared for these additional modes of operation, as well. Further, in certain embodiments of the memory device14, it may be that not all of the illustrated counters in the counter block30are utilized. For instance, certain memory devices14may only employ one bank group. In such a device, the bank group counter64may not be utilized or may be omitted entirely from the memory device14. Further, in certain embodiment of memory devices, additional counters30may be employed if other groupings of memory cells are provided.

Turning now toFIG. 4, a state diagram80illustrating an example of an implementation of a Fast Zero Mode sequence is provided. As previously described, the Fast Zero Mode may be entered during an initialization or power-up of the memory device14. Before the Fast Zero Entry command is received by the fast zero mode controller62, the memory device14may be in an Idle State82. Next, the fast zero mode controller62receives the Fast Zero Entry command. Upon receipt of the Fast Zero Entry command, the fast zero mode controller62issues an activate command to the memory array22, as indicated by the Active State84. In accordance with one embodiment, the activate command may select or turn on one or more rows of each of the banks of the memory array22responsive to the row address counter68. Because the Fast Zero Mode is intended to sequentially write a logical 0 to each cell of each of the banks of the memory array22, multiple rows per each bank may be activated at once. In one embodiment, four rows per each bank may be activated at a time.

Once the selected row(s) is activated, a write command may be issued by the fast zero mode controller62to write a logical 0 to the first memory cell(s) in the selected row(s) of each bank responsive to the column address counter70, as indicated by the Write State86. After the first memory cell(s) in the selected row(s) is written, the fast zero mode controller62increments the column address counter70to generate the next sequential memory address (next column address) in the activate row(s), as indicated by the Update Column State88. The Write State86and Update Column State88are then repeated for each column of the activated row(s) until the end of the activated row(s) is reached. Once the end of the row(s) of each bank is reached, a pre-charge (PRE) command may be sent to the active row(s) by the fast zero mode controller62, in order to deactivate or precharge the row(s), as indicated by the Pre State90.

Once the selected row(s) is deactivated or precharged, the row address counter68may be incremented such that a new internal row address is generated to access the next row or set of rows (e.g., set of four rows) of each bank, as indicated by the Update State92, because writing logic 0 into a memory cell has not reached yet the end memory cell of each bank. Next, the process returns to the Activate State84to activate the next row(s) to be written. As may be appreciated, because every memory cell of each bank is to be written to (e.g., a logical 0) during the Fast Zero Mode of operation and the internal counters30are being controlled to generate the internal addresses to step through the memory cells in an ordered manner, a new activate command need not be generated during the Fast Zero Mode of operation. That is, once the initial activate command is sent, the fast zero mode controller62may repeat the steps indicated in the Activate State84, Write State86, Update Column State88, Pre State90and Update State92without having to generate another activate command. Thus, the Activate State84may not necessarily refer to the assertion of an activate command once the initial activate command is sent.

In the embodiment illustrated by the state diagram80, the process is repeated until a logical 0 is written into each cell of all rows of each of the banks of the memory array22. Thus, the illustrated state diagram80indicates a process whereby only the row address counter68and column address counter70are utilized. That is, each bank may be activated and written to in parallel and thus, neither bank group counter nor the bank address counter66need be incremented. In alternative embodiments, each bank may be written to sequentially, such that the process includes incrementing of the bank group counter64and the bank address counter66, once each column of each row of the bank is written to. Further, in the illustrated embodiment, the memory array may only include a single bank group and therefor, the bank group counter64may not be employed. However, those skilled in the art will appreciate that for memory arrays having multiple bank groups, the bank group counter64may be similarly employed for generation of the internal memory addresses to sequentially access the memory cells in additional banks, as will be described below with regard to the ECS Mode of operation.

Turning now toFIG. 5, a state diagram100illustrating an example of an implementation of a ECS Mode sequence is provided. The ECS Mode may be entered periodically. In one embodiment, the ECS Mode may be entered after a Fast Zero Mode of operation has been asserted to write logical 0s to each memory cell. Further, the ECS Mode may be implemented periodically, depending on how often an error, check and scrub scrub of the memory array22is useful for a particular application. For instance, in various embodiments, the ECS Mode may be implemented once each day, once each week, once each month or once each year, for example.

Before the ECS command is received by the ECS controller60, the memory device14may be in an Idle State102. Next, the ECS controller60receives the ECS command. Upon receipt of the ECS command, the ECS controller60issues an activate command to the memory array22, as indicated by the Active State104. In accordance with one embodiment, the activate command may select or turn on one row in a first bank in a first bank group of the memory array22responsive to the bank group counter64, the bank address counter66and the row address counter68. Once the selected row is activated, a read-modify-write (RMW) command may be issued by the ECS controller60responsive to the column address counter70, as indicated by the Write State106. As appreciated, the RMW command provides a process of error detection and correction. When data is read from a memory cell of the memory array22designated by counters64-70, an error correction code (ECC) is computed and compared with the read data value. If a match is detected, the data in the memory cell is correct. If there is no match, that data value is corrected (if possible) and the memory cell is re-written with the correct data value (if possible). As will be appreciated, certain hard errors may not be correctable (e.g., if the memory cell is damaged). Those skilled in the art will appreciate the usage of the RMW command and the error detection and correction capabilities provided by implementing such.

After the RMW action is performed on the first memory cell in the selected row, the ECS controller60updates an ECC register to increment an error counter, if an ECC error is detected, as indicated by the ECC Register State116. The ECC register captures and holds the information from the ECC error. A Sample State108is provided to ensure that there is sufficient wait time to capture the ECC error in the ECC register before the next memory cell in the memory array22is tested. In one embodiment, the wait time may be approximately 10 ns, for instance. Once the wait time has expired, a pre-charge (PRE) command may be sent to the active row by the ECS controller60, in order to deactivate the row and precharge the bank including a memory cell to be tested for a next RMW action, as indicated by the Pre State110.

Once the selected row is deactivated, the relevant counter(s)30is updated, as indicated by the Update State112. Specifically, the column address counter70is incremented with each cycle of an ECS command. The memory device14is then transitioned back to the Idle State102to await the next ECS command from the controller12to test the next memory cell. While in the Idle State102, the controller12is free to continue other processing. This is repeated until the end of the row is reached, at which time the row address counter68is incremented and the column address counter70is reset. This is repeated until the last column of the last row of the memory bank is reached, at which time, the bank address counter66is incremented and each of the column address counter70and the row address counter68is reset. This is repeated until the last column of the last row of the last memory bank in a group is reached, at which time, the bank group counter64is incremented and each of the column address counter70, the row address counter68and the bank address counter66is reset. Finally, once the entire memory device14has been tested the results of the ECS testing can be stored in a user-readable mode register, as indicated by the Store Result State114. As will be appreciated, the mode register may be configured by a user to send an alert once an unacceptable number of errors has been detected and stored after ECS mode testing. For instance, an error threshold of 1K errors, 15K errors, 50K errors, 100K errors, etc. may be selected based on the particular application and the number of acceptable errors related thereto.

As described above, certain modes of operation, such as the Fast Zero mode and the ECS mode, may facilitate sequential access to individual cells of the memory array22. To facilitate this functionality, a command controller28may be provided, including one or more individual controllers to control the address sequencing when a particular mode entry command (e.g., Fast Zero or ECS) is received. In order to generate internal addresses to be accessed sequentially, one or more counters30may also be provided. Advantageously, the counters30may be shared such that they can be used in any mode of operation that may require address sequencing of all or large portions of the memory array22, such as the Fast Zero mode or the ECS mode.

While the current techniques may be susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. However, it should be understood that the current techniques are not intended to be limited to the particular forms disclosed. Rather, instead the present embodiments are intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present techniques as defined by the following appended claims.