METHODS AND SYSTEMS FOR VERIFYING INTEGRATED CIRCUITS

A system for verifying an integrated circuit includes a tracing module configured to: trace a specified path based on the specified path on which a timing analysis will be performed among a plurality of signal transfer paths within the integrated circuit and a netlist of the integrated circuit at a transistor level, generate a list of nets listing names of nets in the specified path based on the netlist and information on the specified path, declare design constraints for the specified path based on the list of the nets, and generate parasitic data for the net based on the list of the nets. The system further includes an analysis module configured to perform a timing analysis for the specified path based on the design constraints and the parasitic data.

This application claims priority to Korean Patent Application No. 10-2023-0045410, filed Apr. 6, 2023, and Korean Patent Application No. 10-2023-0085940, filed Jul. 3, 2023, the entire contents of which are hereby incorporated herein by reference.

BACKGROUND

The present disclosure relates to methods and systems for verifying integrated circuits.

An integrated circuit memory device such as a dynamic random access memory (DRAM), an application specific integrated circuit (ASIC), or the like, goes through various verification processes before being manufactured using fabrication processes. Moreover, a method for finding a timing error(s) within an integrated circuit may include performing a dynamic timing analysis (DTA) and/or a static timing analysis (STA).

A DRAM is typically verified using the dynamic timing analysis (DTA); nonetheless, it is impossible to simulate all cases that may occur within the circuit using an input vector(s). In addition, because a block-level static timing analysis (STA) is typically not possible due to a structure of the DRAM designed at a transistor level and because the entire circuit has to be analyzed at one time, there is typically a problem because the static timing analysis (STA) has a relatively long runtime and it is often difficult to create design constraints required for the static timing analysis (STA) due to the complexity of the circuit, so that a turn-around-time (TAT) becomes longer.

SUMMARY

Embodiments are to provide a method and a system for verifying an integrated circuit, by performing a static timing analysis (STA) only for a specified path of the integrated circuit.

Further embodiments are to provide a method and a system for verifying an integrated circuit that reduce a verification time for timing sign-off.

A system for verifying an integrated circuit according to an embodiment of the present disclosure includes: a tracing module configured to: trace a specified path based on the specified path on which a timing analysis will be performed among a plurality of signal transfer paths within the integrated circuit and a netlist of the integrated circuit at a transistor level, generate a list of nets listing names of nets in the specified path based on the netlist and information on the specified path, declare design constraints for the specified path based on the list of the nets, and generate parasitic data for the net based on the list of the nets. An analysis module is also provided, which is configured to perform a timing analysis for the specified path based on the design constraints and the parasitic data.

The information on the specified path may include information on at least one signal start point and at least one signal end point of the specified path, information on a path to be excluded from tracing among a plurality of signal transfer paths between the at least one signal start point and the at least one signal end point, and information on at least one memory element that the specified path passes through. In addition, the specified path may include a data path connected to a signal start point among the at least one signal start point that outputs a data signal, and a clock path connected to a signal start point among the at least one signal start point that outputs a clock signal. The tracing may include extracting a plurality of paths between the at least one signal start point and the at least one signal end point, and excluding a path to be excluded from the tracing among the extracted plurality of paths. Advantageously, in some embodiments, the tracing may be performed in a reverse direction of a signal transfer direction of the plurality of signal transfer paths. The plurality of paths may be distinguished by the memory element. The memory element may include a first pin that receives the clock signal, and the clock path may include the net connected to the first pin. The design constraints may be declared for the clock path among the specified paths. The parasitic data may further include parasitic data for a net that forms a coupling capacitance with the net, and a net that is logically adjacent to the net. The memory element may include a latch.

According to a further embodiment, a method for verifying an integrated circuit according to an embodiment of the present disclosure may include: receiving a netlist of a transistor-level integrated circuit, receiving information on a specified path on which a timing analysis will be performed among a plurality of signal transfer paths within the integrated circuit, tracing the specified path and generating a list of nets listing names of nets in the specified path based on the netlist and information on the specified path, declaring design constraints for the specified path based on the list of the nets, and generating parasitic data for the net in the specified path based on the list of the nets. The information on the specified path may include a name of a net connected to a plurality of signal start points and a plurality of signal end points in the specified path, a name of a net in a path to be excluded from tracing among a plurality of signal transfer paths between the plurality of signal start points and the plurality of signal end points, and a name of a net connected to a memory element through which the specified path passes. The tracing of the specified path may include: extracting a plurality of path from the plurality of signal end points to the plurality of signal start points, and excluding a path to be excluded from the tracing among the plurality of paths. The plurality of paths may be distinguished by the memory element. The declaring of the design constraints may include extracting a clock path from the plurality of paths. The memory element may include a first pin that receives a clock signal, and the clock path may be a path connected to the first pin. The clock path may be a path connected to a signal start point among the plurality of signal start points that outputs the clock signal. The extracting of the clock path from the plurality of paths may include: extracting at least one net connected to the plurality of signal start points from the list of the nets, extracting the signal start point among the plurality of signal start points that outputs the clock signal, and extracting a path including a net connected to the signal start point outputting the clock signal among the at least one net. The generating of the parasitic data may include: receiving the parasitic data from layout data of the integrated circuit, and extracting the parasitic data of the net in the list of the nets from the parasitic data of the integrated circuit.

A device for verifying an integrated circuit according to an embodiment of the present disclosure includes: a path tracer configured to trace a specified path on which a timing analysis will be performed among a plurality of signal transfer paths within the integrated circuit at a transistor level and generate a list of nets listing names of nets in the specified path, a design constraints generator configured to declare design constraints for the specified path based on the list of the nets, and a file generator configured to generate parasitic data for a net in the list of the nets based on the list of the nets.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Hereinafter, an embodiment of the present disclosure will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same constituent elements on the drawings, and duplicate descriptions for the same constituent elements are omitted.

Moreover, in order to clearly explain the present disclosure in the drawings, parts irrelevant to the description are omitted, and similar reference numerals are attached to similar parts throughout the specification. In the flowchart described with reference to the drawings, the order of the operations may be changed, several operations may be merged, certain operations may be divided, and specific operations may be omitted.

A timing analysis of an integrated circuit is essential to ensure that the integrated circuit operates and performs as expected when the integrated circuit is manufactured on silicon. A static timing analysis (STA) of the integrated circuit is an analysis method that considers all timing paths existing in the circuit to find a path that may exhibit an unstable operation. In other words, the static timing analysis (STA) analyzes a timing between signals input/output to/from a designed semiconductor memory or logic to test whether the designed integrated circuit may normally operate without a timing problem(s).

The static timing analysis (STA) is performed by a static timing analysis (STA) tool that analyzes a timing between input and output signals based on delay information and connection relationship information for a cell (e.g., a transistor, a gate-level cell, a unit logic (AND, OR, or the like) level cell, a memory element (e.g., a latch, a flip-flop, or the like)), which is included in the integrated circuit and design constraints of a clock path. A representative tool currently used for the static timing analysis (STA) of an integrated circuit designed at a transistor level is NanoTime, which is a product developed by Synopsys Inc.

FIG.1is a view illustrating a signal transfer path for describing the static timing analysis (STA). Referring toFIG.1, an integrated circuit100may include plurality of signal input points101and102and a signal output point103. A clock signal may be transmitted from the first signal input point (CLK)102among the signal input points101and102to each of latches111and121. A data signal may be transferred from the second signal input point (A)101to the signal output point (Z)103. Specifically, when the clock signal is input to each of the latches (L1)111and (L2)121through a first clock path140and a second clock path150, each of the latches111and121may be activated, and the data signal may be transferred to the latch111through a first data path110, and then transferred to the latch121through a second data path120, and then may be transferred to the signal output point103through a third data path130. In this case, the static timing analysis (STA) may check whether a given design may operate at a specific clock signal frequency without an error that occurs when the signal of each data path110,120, or130arrives too early or too late than the signal of each clock path140or150.

In other words, the static timing analysis (STA) may break a design down into a timing path(s) to check timing errors for all timing paths. However, unlike an application specific integrated circuit (ASIC) that is designed as a gate-level cell, a dynamic random access memory (DRAM) is designed at a transistor level so that complexity of the circuit further increases. Therefore, when the static timing analysis (STA) for all timing paths is performed on a DRAM, a runtime is long and a clock path is complex so that it is difficult to create design constraints.

Embodiments described in the present disclosure extract a list of nets included in a specified path to be analyzed in a memory semiconductor design, which is designed at a transistor level and extracts a clock path from the extracted list of nets to create design constraints. Thus, the present disclosure is intended to provide a method of performing a static timing analysis (STA) for the specified path. In an embodiment, the specified path to be analyzed may be a path involved in a read operation of a memory semiconductor or a path involved in a write operation of the memory semiconductor, but the present disclosure is not limited thereto.

FIG.2is an implementation flow of the static timing analysis (STA) according to an embodiment. First, a netlist that describes a connection relationship of cells of an integrated circuit may be extracted from a transistor level design210. The transistor level design may refer to a memory semiconductor design such as a dynamic random access memory (DRAM). In order to perform the static timing analysis (STA) of a specified path to be analyzed in a memory semiconductor design designed at a transistor level, a path tracer230may extract a list of nets in the specified path. In order to extract the list of nets in the specified path, the path tracer230may further receive path information231for the specified path in addition to the netlist. The path information231may include information on a start point and an end point of the path, a latch within the path, or the like

The path tracer230may extract a list of nets listing names of nets in the specified path from the received information. The list of nets in the specified path may be input to a design constraints generator240and a file generator260.

The design constraints generator240may generate a design constraints file required to perform the static timing analysis (STA) based on the list of nets received from the path tracer230. Since the design constraints for performing the static timing analysis (STA) are declared only for the clock path, the design constraints generator240may extract the clock path from the specified path and may declare the designs constraint for the extracted clock path.

The file generator260may further receive parasitic data from a chip layout250in addition to the list of nets received from the path tracer230. The chip layout250may refer to layout data generated by placing and routing cells and nets included in the integrated circuit. The parasitic data may refer to resistor (R) information, capacitor (C) information, and the like of each net included in the integrated circuit. Based on the list of nets received from the path tracer230, the file generator260may extract parasitic data for a net in a specified path on which to perform the static timing analysis (STA) among the parasitic data.

A static timing analyzer270may perform the static timing analysis (STA) by receiving the design constraints file and a parasitic data file for the specified path as inputs. If a timing error is found during the timing analysis, the static timing analyzer270may generate an engineering change order (ECO) list for correcting the error. The chip layout250may be modified based on the ECO list, and then when all timing errors are resolved, timing sign-off for the integrated circuit is completed.

Here, a series of operations220for extracting the list of nets included in the specified path and generating the design constraints and the parasitic data from the list of nets may perform the static timing analysis only for the specified path, and instructions for performing each operation of the series of operations may be stored in one program. In an embodiment, the devices230,240, and260performing the series of operations220for extracting the list of nets included in the specified path and generating the design constraints and the parasitic data from the list of nets and the timing analyzer270may be referred to as a device for verifying the integrated circuit.

FIGS.3to13describe a method for performing the static timing analysis (STA) according to an embodiment. In particular,FIG.3is a flowchart for performing the static timing analysis (STA) according to an embodiment. Referring toFIG.3, in step S311, the path tracer230ofFIG.2receives a full-chip netlist of a transistor-level integrated circuit design. In step S312, the path tracer230receives information on the specified path. Here, the specified path may be a path for performing the static timing analysis (STA).

The step S312will be described with reference toFIGS.4and5. In particular,FIG.4is a view showing a signal transfer path of an integrated circuit according to an embodiment, andFIG.5is a view showing an information file of a specified path received by a path tracer according to an embodiment. Referring toFIG.4, the integrated circuit400may include a plurality of signal start points (S1, S2, S3, and S4)401and402and a plurality of signal end points (E1and E2)403. Each of the signal start points (S1, S2, and S3)401may transfer a data signal, whereas the signal start point402may transfer a clock signal, which operates to synchronize the signal transfer path(s). A plurality of paths P1to P12may exist between the plurality of signal start points401and402and the plurality of signal end points403. In an embodiment, paths starting from the signal start points (S1, S2, and S3)401may be data paths, and a path starting from the signal start point (S4)402may be a clock path(s).

The static timing analysis (STA) may be performed by breaking a design down into a timing path. Since the latch transfers a data signal based on a clock signal, the timing path may be broken down at each latch. In an embodiment, the timing path may include a first path P1, P2, P3, and P4from the plurality of signal start points401and402to the latches, a second path P5, P6, P7, and P8between the latches, and a third path P9, P10, P11, and P12from the latches to the plurality of signal end points E1and E2. Each timing path may include various logics, but may not include a flip-flop, a latch, or the like. As described herein, the timing path is broken down into segments at each latch, but the present disclosure is not limited thereto. For example, in alternative embodiments, the timing path may be broken down into segments at a flip-flop, a register, or the like.

Referring to an information file500of the specified path ofFIG.5, in an embodiment, information of the specified path received by the path tracer230may include information510on the signal end point and information520on the signal start point. Since path tracing is performed in a reverse direction relative to the direction in which the data signal and/or the clock signal are transferred, the path tracer230may receive information on the signal end point and the signal start point to determine a tracing start point (the signal end point) and a tracing end point (the signal start point).

In an embodiment, the information on the specified path received by the path tracer230may include information530on a net to be excluded from the path tracing. The path tracer230may not perform path tracing for a path after a net (within the path) is excluded from the path tracing during path tracing from the tracing start point to the tracing end point. In this case, information on the net may be input as a specified pattern of a name of the net.

In an embodiment, the information on the specified path received by the path tracer230may include information540on latches in the specified path. Specifically, the path tracer230may receive information on the latch through which a signal passes during the path tracing from the tracing start point to the tracing end point. In an embodiment, the information on the latch may include information on a net connected to the latch. During the path tracing, the path tracer230may perform path tracing of the data signal and the clock signal of the latch through which the signal passes.

In another embodiment, the information on the specified path received by the path tracer230may include information550on the latch in which the clock signal is always on among the latches in the specified path. Specifically, the path tracer230may receive information on the latch in which the clock signal is always on among the latches through which the signal passes during the path tracing from the tracing start point to the tracing end point. In an embodiment, the information on the latch in which the clock signal is always on may include information on a net connected to the latch in which the clock signal is always on. The latch in which the clock signal is always on may be referred to as a bypass latch. The path tracer230may not perform path tracing of the clock signal of the bypass latch during the path tracing. The information received by the path tracer230is not limited thereto, and may further receive information on the specified path required for the path tracing.

Referring again toFIG.3, in step S320, the path tracer230traces a path by receiving information on the full-chip netlist and the specified path, and in step S330, the path tracer230generates (or creates) the list of nets included in the specified path. The steps S320and S330will be described more fully with reference toFIGS.6to9.

FIG.6is a view showing a path within the integrated circuit according to an embodiment. Specifically, the path within the integrated circuit represents all paths from the tracing start points E1and E2to the tracing end points S1, S2, S3, and S4to be traced by the path tracer230. Referring toFIG.6, based on the information510on the signal end point and the information520on the signal start point ofFIG.5, the path tracer230may perform path tracing from the signal end point (that is, the tracing start points E1and E2) to the signal start point (that is, the tracing end points S1, S2, S3, and S4). In an embodiment, the path may be broken down into the latch. For example, the path may include the paths P9, P10, P11, and P12from the tracing start points E1and E2, the paths P5, P6, P7, and P8between the latches, and the paths P1, P2, P3, and P4from the latches to the tracing end points S1, S2, S3, and S4.

FIG.7is a view showing a path excluded from the tracing according to an embodiment. Referring toFIG.7, the path tracer230may determine the path to be excluded from the path tracing based on: (i) the information530on the net to be excluded from the path tracing, (ii) the information540on the latches in the specified path for performing the timing analysis, and (iii) the bypass latch information550of FIG.5.

For example, if the net (for example, the net whose name includes “rst”) to be excluded from the path tracing is encountered, the path tracing to the path P10may not be performed during the path tracing from the tracing start points E1and E2. In addition, if the net (for example, the net whose value is fixed to 0 or 1 according to a mode setting) to be excluded from the path tracing is encountered, the path tracing to the path P11may not be performed during the path tracing from the tracing start points E1and E2. For example, if the latches L1and L5other than the latches L2, L4, and L6(see540ofFIG.5) or the bypass latch L3(see550ofFIG.5) in the specified path are encountered, the path tracing to the paths P9and P7may not be performed during the path tracing from the tracing start points E1and E2.

FIG.8is a view showing the specified path traced by the path tracer according to an embodiment. Referring toFIG.8, the path tracer230may perform path tracing only on specified paths P1, P2, P3, P4, P5, P6, P8, and P12among the paths P1to P12from the tracing start points E1and E2to the tracing end points S1, S2, S3, and S4. In an embodiment, the path tracer230may generate a list of only nets in the specified paths P1, P2, P3, P4, P5, P6, P8, and P12among the paths P1to P12from the tracing start points E1and E2to the tracing end points S1, S2, S3, and S4.

FIG.9is a view showing a list file of a net generated by the path tracer according to an embodiment. Specifically,FIG.9shows the list file900of the net that lists names of nets in the specified path and is generated by the path tracer230based on the information on the full-chip netlist and the specified path.

In an embodiment, the list file900of the net may include information of a net910connected to the latch L4ofFIG.8, a net920connected to a logic disposed between the latch L4and the latch L6, a net930connected to the latch L6, a net940connected to a logic disposed between the latch L6and the signal start point S4, and a net950connected to the signal start point S4, but the present disclosure is not limited thereto.

Referring again toFIG.3, in step S340, the design constraints generator240ofFIG.2receives the list file of the net in the specified path from the path tracer230, and generates a design constraints file for the clock path of the specified path.

The step S340will be described with reference toFIGS.10to12, whereFIG.10is a flowchart showing a method for generating the design constraints file according to an embodiment, andFIG.11is a view illustrating design constraints according to an embodiment. However, the design constraints generated here are required when the static timing analysis (STA) is performed using NanoTime, by Synopsys Inc., but the present disclosure is not limited thereto, and it should be noted that performing the static timing analysis (STA) with another tool may require different design constraints.

In an embodiment, the design constraints generator240receives the list of nets in the specified path traced from the signal tracer230(S341), and determines whether the path including the net is the clock path (S342). Specifically, if a net included in a timing path within the specified path is connected to a clock pin of the latch, the design constraints generator240may determine that the timing path including the net is the clock path. In addition, if a first net in the specified path is connected to the signal start point S4that outputs the clock signal, the design constraints generator240may determine that the path including the net is the clock path. For example, the design constraints generator240may extract the first net in the specified path from the list of the nets, may extract the signal start point S4that outputs the clock signal among the plurality of signal start points S1to S4, and may extract a path including a net connected to the signal start point S4. In an embodiment, the design constraints generator240may extract the clock path in the specified path, and may declare the design constraints for the clock path (S343). In an embodiment, the design constraints generator240does not declare the design constraints for a path (that is, the data path) other than the clock path (S344).

The design constraints, constraint1to constraint4ofFIG.10, will be described with reference toFIG.11. In an embodiment, the design constraints generator240may declare the design constraints (constraint1) for the net connected to the signal start point that outputs the clock signal among the nets within the clock path. Here, the signal start point that outputs the clock signal may be a clock source. Referring toFIG.11, the design constraints generator240may declare the design constraints indicating that the net connected to the signal start point s4that outputs the clock signal among the nets within the clock path1110is the net that generates the clock signal (1124). In an embodiment, if the clock signal passes through a first latch, the clock signal after the first latch in a signal transfer process may be a clock signal regenerated from the first latch. Therefore, if the clock path passes through the latch, the design constraints generator240may declare the design constraints (constraint2) for indicating that the clock signal is regenerated in the latch. Referring toFIG.11, if the clock path1110passes the latch L6in the signal transfer process, the design constraints generator240may declare the design constraints indicating that the clock signal is regenerated in the latch L6. Additionally, the design constraints generator240may declare the design constraints for indicating that the clock signal of the latch L6is transferred from the clock source S4(1122). If the clock path1110passes through the latch L4in the signal transfer process, the design constraints generator240may declare the design constraints for indicating that the clock signal is regenerated in the latch L4. Additionally, the design constraints generator240may declare the design constraints for indicating that the clock signal of the latch L4is transferred from the latch L6before the latch L4(1121).

In an embodiment, when the clock path is a reconvergent path, the design constraints generator240may declare the design constraints (constraint3) for analyzing all nets included in the reconvergent path together. Referring toFIG.11, if some logic1111included in the clock path1110includes a path that reconverges after the clock path is divided into two sections, the design constraints generator240may declare the design constraints for analyzing all nets included in the reconvergent path together (1123).

In an embodiment, if some of the clock paths are paths excluded from the analysis, the design constraints generator240may declare the design constraints (constraints4) that prevents the timing analysis from being performed on the path. The design constraints declared by the design constraints generator240are not limited thereto, and more design constraints may be declared.

FIG.12is a view showing the design constraints file generated by the design constraints generator240according to an embodiment. Specifically,FIG.12shows the file1200declaring the design constraints for the clock path based on the list file of the net in the specified path received by the design constraints generator240from the path tracer230. As described inFIG.11, various design constraints on the clock path1110may be declared in the file1200.

Referring again toFIG.3, in step S350, the file generator260ofFIG.2generates the parasitic data of the net in the specified path. This step S350will be described with reference toFIG.13, which is a flowchart showing a method for generating the parasitic data according to an embodiment.

In an embodiment, the file generator260may receive the list of nets in the specified path generated from the path tracer230(S351). Additionally, the file generator260may receive the parasitic data from the layout data (S352). The parasitic data may refer to the resistor (R) information, the capacitor (C) information, and the like of the net within the integrated circuit.

In an embodiment, the file generator260may extract the parasitic data of the net in the specified path from the parasitic data received from the layout data (S353). In this case, the extracted information may include not only the parasitic data of the net in the specified path but also parasitic data of a net that forms a coupling capacitance with the net in the specified path. In addition, the extracted information may include parasitic data of a net (for example, a plurality of nets output from one logic or a plurality of nets input to one logic) logically adjacent to the net in the specified path, but the present disclosure is not limited thereto. In an embodiment, the file generator260may generate a parasitic data file of the net in the specified path based on the extracted parasitic data (S350).

In step S360ofFIG.3, the static timing analyzer270ofFIG.2receives a design constraints file and the parasitic data file for the net in the specified path, and performs the static timing analysis (STA) based on the received design constraints file and parasitic data file.

FIG.14is data representing results of performing the path tracer, the design constraints generator, and the file generator according to an embodiment. Specifically, the specified path to be analyzed in the integrated circuit is separated using the path tracer230, the design constraints is declared using the design constraints generator240, and the parasitic data file1400that is the data representing the results is generated using the file generator260. Each item ofFIG.14is as follows.

In an embodiment, the total number of nets in the full-chip netlist of the integrated circuit for data analysis ofFIG.14is125,321,221. Referring to Case 1, the specified path to be analyzed may have a total of 23 signal start points1410and a total of 454 signal end points1430, and a signal between the signal start point and the signal end point may pass through 1,453 latches1420. The number of paths1440traced by the path tracer between the signal start point and the signal end point is 27,213, and a ratio1450of nets within the traced path to the number of entire nets within the full-chip netlist is 0.06%. The design constraints generator240declares107design constraints1460for the nets within the traced path, and a runtime1470of the path tracer and the design constraints generator is 238 s. Additionally, a ratio1480of the number of transistors within the parasitic data file generated by the file generator260to the number of transistors of a full-chip is 3.1%, and a runtime1490of the file generator is 369 s. That is, the number of nets for the timing analysis is significantly reduced compared with the entire nets within the full-chip netlist.

Referring to Cases 2 to 8, a ratio1450of nets in the specified path for the timing analysis to the entire nets within the full-chip netlist may be less than 1%. In other words, because a block-level static timing analysis is not possible due to a structure of the DRAM and an entire circuit has to be analyzed at one time, the static timing analysis may have a long runtime. However, if the static timing analysis is performed by extracting only the specified path within the integrated circuit, the runtime of the static timing analysis may be advantageously reduced. Therefore, there is an advantage in which a turn-around-time (TAT) for the static timing analysis (STA) may be reduced.

FIG.15is a block diagram showing a computing system1500for designing and verifying the integrated circuit according to an embodiment of the present disclosure. Referring toFIG.15, the computing system1500for designing and verifying the integrated circuit may include a processor1510, a memory1530, an input/output device1550, a storage device1570, and a bus1590. The computing system1500may perform a verification operation of the integrated circuit ofFIGS.2to13. The computing system1500may be provided as a dedicated device for designing and verifying the integrated circuit of a semiconductor device, but may be a computer for driving various simulation tools or design tools.

The processor1510may be configured to execute instructions that perform at least one of various operations for designing and verifying the integrated circuit. The processor1510may communicate with the memory1530, the input/output device1550, and the storage device1570through the bus1590. The processor1510may execute a design operation and a verification operation of the integrated circuit by driving a tracing module1531and a static timing analysis (STA) module1532loaded in the memory1530.

The memory1530may store the tracing module1531and the static timing analysis (STA) module1532. Additionally, the memory1530may further store a composition module and a layout module. The tracing module1531and the STA module1532may be loaded from the storage device1570to the memory1530. The memory1530may be a volatile memory such as an SRAM or a DRAM, or a non-volatile memory such as a PRAM, an MRAM, an ReRAM, an FRAM, a NOR flash memory, or the like.

For example, the tracing module1531may be a program that includes a plurality of instructions for performing path tracing and file creation according to the operations220ofFIG.2and the step ofFIG.3. For example, the tracing module1531may be a program that includes the plurality of instructions for tracing the specified path to be analyzed from a transistor-level netlist according toFIGS.2to13, extracting a list of nets in the specified path, and generating the design constraints and the parasitic data file for the specified path based on the extracted list of nets. For example, the STA module1533may be a program that includes a plurality of instructions for receiving the design constraints and the parasitic data file generated according toFIGS.2to13to perform the static timing analysis (STA) for the specified path.

The input/output device1550may control an input and an output of a user from user interface devices. For example, the input/output device1550may include an input device such as a keyboard, a mouse, a touchpad, or the like to receive input data defining the integrated circuit. For example, the input/output device1550may include an output device such as a display, a speaker, or the like to display a placement result, a routing result, or a timing analysis result. The storage device1570may store various data related to the tracing module1531and the STA module1532. The storage device1570may include a memory card (an MMC, an eMMC, an SD, a MicroSD, or the like), a solid-state drive (SSD), a hard disk drive (HDD), or the like.