Method of making an electrode contact structure and structure therefor

In one embodiment, a method for forming a semiconductor device having a shield electrode includes forming first and second shield electrode contact portions within a contact trench. The first shield electrode contact portion can be formed recessed within the contact trench and includes a flat portion. The second shield electrode contact portion can be formed within the contact trench and makes contact to the first shield electrode contact portion along the flat portion.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is related to U.S. patent application No. 13/471,105, an application entitled “METHOD OF MAKING AN INSULATED GATE SEMICONDUCTOR DEVICE HAVING A SHIELD ELECTRODE STRUCTURE” having a common assignee and a common inventor, and filed concurrently on May 14, 2012.

BACKGROUND OF THE INVENTION

This document relates generally to semiconductor devices, and more specifically to methods of forming insulated gate devices and structures.

Metal oxide field effect semiconductor transistor (MOSFET) devices have been used in many power switching applications, such as dc-dc converters. In a typical MOSFET, a gate electrode provides turn-on and turn-off control with the application of an appropriate gate voltage. By way of example, in an n-type enhancement mode MOSFET, turn-on occurs when a conductive n-type inversion layer (i.e., channel region) is formed in a p-type body region in response to the application of a positive gate voltage, which exceeds an inherent threshold voltage. The inversion layer connects n-type source regions to n-type drain regions, and allows for majority carrier conduction between these regions.

There is a class of MOSFET devices in which the gate electrode is formed in a trench that extends downward from a major surface of a semiconductor material, such as silicon. Current flow in this class of devices is primarily in a vertical direction through the device, and, as a result, device cells can be more densely packed. All else being equal, the more densely packed device cells can increase the current carrying capability and can reduce on-resistance of the device.

Achieving reduced specific on-resistance (ohm-area) performance is one important goal for MOSFET device designers. A reduced specific on-resistance can determine product cost and gross margins or profitability for a MOSFET design. For example, a low specific on-resistance allows for a smaller MOSFET die or chip, which in turn leads to lower costs in semiconductor materials and package structures. However, challenges continue to exist in manufacturing higher density MOSFET devices that achieve the desired performance including reduced specific on-resistance. Such challenges include providing reliable die size or pitch reductions, reducing manufacturing costs, simplifying process steps, and improving yields.

Accordingly, it is desirable to have a method and structure that reduces cell size, reduces manufacturing costs, simplifies processing steps, improve yields, or combinations thereof. Additionally, it is beneficial for the method and structure to maintain or improve electrical performance compared to related structures.

For simplicity and clarity of illustration, elements in the figures are not necessarily drawn to scale, and the same reference numbers in different figures denote generally the same elements. Additionally, descriptions and details of well-known steps and elements may be omitted for simplicity of the description. As used herein current-carrying electrode means an element of a device that carries current through the device, such as a source or a drain of an MOS transistor, an emitter or a collector of a bipolar transistor, or a cathode or anode of a diode, and a control electrode means an element of the device that controls current through the device, such as a gate of a MOS transistor or a base of a bipolar transistor. Although the devices are explained herein as certain N-channel devices, a person of ordinary skill in the art understands that P-channel devices and complementary devices are also possible in accordance with the present description. For clarity of the drawings, doped regions of device structures are illustrated as having generally straight-line edges and precise angular corners; however, those skilled in the art understand that due to the diffusion and activation of dopants, the edges of doped regions are generally not straight lines and the corners are not precise angles.

Furthermore, the term “major surface” when used in conjunction with a semiconductor region or substrate means the surface of the semiconductor region or substrate that forms an interface with another material, such as a dielectric, an insulator, a conductor, or a polycrystalline semiconductor. The major surface can have a topography that changes in the x, y and z directions.

In addition, structures of the present description can embody either a cellular base design (in which the body regions are a plurality of distinct and separate cellular or stripe regions) or a single base design (in which the body region is a single region formed in an elongated pattern, typically in a serpentine pattern or a central portion with connected appendages). However, one embodiment of the present description will be described as a cellular base design throughout the description for ease of understanding. It should be understood that the present disclosure encompasses both a cellular base design and a single base design.

DETAILED DESCRIPTION OF THE DRAWINGS

FIG. 1illustrates a partial cross-sectional view of a semiconductor device10or cell10at an early stage of fabrication in accordance with a first embodiment. Device10includes a region of semiconductor material, semiconductor substrate, or semiconductor region11, which can be, for example, an n-type silicon substrate12having a resistivity ranging from about 0.001 ohm-cm to about 0.005 ohm-cm. By way of example, substrate12can be doped with phosphorous, arsenic, or antimony. In the embodiment illustrated, substrate12provides a drain region, drain contact, or a first current carrying contact for device10. In this embodiment, device10can include an active area102and a contact area103where contact can be made, for example, to shield electrode structures described hereinafter. Also, in this embodiment, device10can be configured as a vertical power MOSFET structure, but this description applies as well to insulated gate bipolar transistors (IGBT), MOS-gated thyristors, and other related or equivalent structures as known by one of ordinary skill in the relevant art.

A semiconductor layer, drift region, or extended drain region14can be formed in, on, or overlying substrate12. In one embodiment, semiconductor layer14can be formed using semiconductor epitaxial growth techniques. Alternatively, semiconductor layer14can be formed using semiconductor doping and diffusion techniques. In an embodiment suitable for a 50 volt device, semiconductor layer14can be n-type with a dopant concentration of about 1.0×1016atoms/cm3to about 1.0×1017atoms/cm3and can have a thickness from about 3 microns to about 5 microns. The dopant concentration and thickness of semiconductor layer14can be increased or decreased depending on the desired drain-to-source breakdown voltage (BVDSS) rating of device10. In one embodiment, semiconductor layer14can have a graded dopant profile. In an alternate embodiment, the conductivity type of substrate12can be opposite to the conductivity type of semiconductor layer14to form, for example, an IGBT embodiment.

A masking layer47can be formed overlying a major surface18of region of semiconductor material11. In one embodiment, region of semiconductor material11also includes major surface19, which is opposite to major surface18. In one embodiment, masking layer47can comprise a dielectric film or a film resistant to the etch chemistries used to form trenches described hereinafter. In one embodiment, masking layer47can include more than one layer including, for example, a dielectric layer471of 0.030 microns of thermal oxide, a dielectric layer472of about 0.2 microns of silicon nitride, and a dielectric layer473of about 0.1 microns of deposited oxide. In accordance with one embodiment, dielectric layer472can be configured to protect major surface18from encroachment effects in subsequent process steps that occur, for example, after trench structures are formed. This encroachment effect is a problem with related devices when thermal oxides are formed along upper surfaces of trench structures and in proximity to exposed portions of semiconductor layer14along major surface18. The encroachment problem can cause an uneven dielectric layer along major surface18, which can impact the dopant profiles of subsequently formed doped regions.

Openings58and59can then be formed in masking layer47. In one embodiment, photoresist and etch processes can be used to form openings58and59. In one embodiment, openings58can have a width16of about 0.2 microns to about 0.25 microns, and opening59can have a width17of about 0.4 microns to about 0.5 microns. In one embodiment, an initial spacing181between openings58can be about 0.55 microns to about 0.65 microns.

After openings58and59are formed, segments of semiconductor layer14can be removed to form trenches22and27extending from major surface18. By way of example, trenches22and27can be etched using plasma etching techniques with a fluorocarbon chemistry (for example, SF6/O2). In one embodiment, trenches22and27can extend partially into semiconductor layer14leaving a portion of semiconductor layer between lower portions of trenches22and27and substrate12. In one embodiment, trenches22and27can extend through semiconductor layer14and into substrate12. In one embodiment, a sloped sidewall etch can be used with a slope of about 88 degrees to 89.5 degrees being one example. By way of example when using a SF6/O2chemistry, the sloped sidewalls can be achieved by increasing the flow of O2, which increases the sidewall Si—F—O passivant. When a sloped etch is used, trenches22can be separated by a distance182of about 0.6 microns to about 0.70 microns near the lower surfaces of trenches22as generally noted inFIG. 1. In one embodiment, trenches22and27can have a depth of about 1.5 microns to about 2.5 microns. In accordance with the present embodiment, trenches22can be configured as gate electrode and shield electrode trenches for the active devices of device10formed within active area102, and trench27can be configured as a contact trench where external contact can be made to the shield electrodes within contact area103. In one embodiment, contact area103can be located in a peripheral portion of device10. In another embodiment, contact area103can be located in a centralized portion of device10. In a further embodiment, a plurality of contact areas103can be used. For example, one can be located in a peripheral portion of device10, and another can be located in a centralized portion of device10.

FIG. 2illustrates a partial cross-sectional view of device10after additional processing. In an optional step, a sacrificial layer (not shown) is formed adjoining surfaces of trenches22and27. By way of example, a thermal silicon oxide layer can be formed. Subsequently, the sacrificial layer and dielectric layer473can be removed using, for example, an etch process. A layer261of material can then be formed along surfaces of trenches22and27. In one embodiment, layer261can be a dielectric or insulative material. By way of example, layer261can be about a 0.03 micron wet or thermal oxide layer. Portions of semiconductor layer14can be consumed during the formation of the thermal oxide, which reduces spacing181approximately by the thickness of the sacrificial layer (if used) and of layer261designated as reduced spacing or first reduction1810. In one embodiment, first reduction1810can be about 0.5 to about 0.6 microns.

FIG. 3illustrates a partial cross-sectional view of device10after further processing. A conformal layer262can be formed along layer261and sidewall portions of dielectric layer472, and overlying dielectric layer472. In one embodiment, conformal layer262can be a dielectric or insulative material. In one embodiment, conformal layer262can be a deposited oxide. By way of example, conformal layer262can have a thickness from about 0.05 microns to about 0.1 microns. In an alternate embodiment, conformal layer262can be formed by depositing a polysilicon layer and fully oxidizing it to convert it to a thermal oxide. In one embodiment, layers261and/or262are configured as a shield electrode dielectric layer or structure259, which separate, insulate, or isolate the shield electrode (for example, element21illustrated inFIG. 17) from semiconductor layer14and substrate12(if trenches22adjoin substrate12).

In one embodiment, a layer of material can be formed overlying major surface18and within trenches22and27. In one embodiment, the layer of material can be a crystalline semiconductor material, a conductive material, or combinations thereof. In one embodiment, the layer of material can be doped polysilicon. In one embodiment, the polysilicon can be doped with an n-type dopant, such as phosphorous or arsenic. In a subsequent step, the layer of material can be planarized to form intermediate structures1021and1141in trenches22and27respectively. In one embodiment, chemical mechanical polishing techniques can be used for the planarization step. When the layer of material includes crystalline semiconductor material, the layer of material can be heat treated before or after planarization to, for example, active and/or diffuse any dopant material present in the crystalline semiconductor material.

FIG. 4illustrates a partial cross-sectional view of device10after more processing. For example, intermediate structures1021and1141can be further recessed within trenches22and27to form shield electrodes21and a shield electrode contact portion141. As an example, a dry etch with a fluorine or chlorine based chemistry can be used for the recess step. In one embodiment, an etch step, such as a wet etch step can be used to remove conformal layer262overlying dielectric layer472and along sidewall portions of dielectric layer472. The wet etch step can be used to further remove conformal layer262and layer261from upper sidewall portions or sidewall portions221of trenches22, and from upper sidewall portions or sidewall portions271of trench27as illustrated inFIG. 5. In one embodiment, a buffered hydrofluoric (HF) acid can be used. The etch step can also expose portions210of shield electrodes21and portions1410of shield electrode contact portion141as illustrated, for example, inFIG. 5.

FIG. 6illustrates a partial cross-sectional view of device10after additional processing. In one embodiment, a dielectric layer266can be formed along sidewall portions221and271and along exposed portions210and1410. In one embodiment, dielectric layer266can be a thin sacrificial or thermal oxide layer, or another dielectric or insulative layer. In one embodiment, dielectric layer266can have a thickness of about 0.005 microns to about 0.01 microns. Subsequently, an etch step can be used to remove additional portions of shield electrodes21and shield electrode contact portion141as illustrated, for example, inFIG. 7. In one embodiment, portions of dielectric layer266that overlie shield electrodes21and shield electrode contact portion141can be removed with an initial break-through etch or removal step. By way of example, a fluorine based chemistry can be used for the break-through etch step, and a fluorine or chlorine based chemistry can be used for the recess etch step.

FIG. 8illustrates a partial cross-sectional view of device10after further processing. In one embodiment, a removal step can be used to remove dielectric layer266and portions of layers261and262. Subsequently, in accordance with the present embodiment, a dielectric layer is formed along sidewall portions221and227of trenches22and27. In one embodiment, the dielectric layer can also be formed overlying portions of layers261and262, shield electrode21, and/or shield electrode contact141. In accordance with the present embodiment, the dielectric layer forms gate layers or gate dielectric layers26along upper sidewall surfaces221of trenches22. Gate layers26can be oxides, nitrides, tantalum pentoxide, titanium dioxide, barium strontium titanate, high k dielectric materials, combinations thereof, or other related or equivalent materials as known by one of ordinary skill in the art. In one embodiment, gate layers26can be silicon oxide and can have a thickness from about 0.01 microns to about 0.06 microns. Portions of semiconductor layer14can be further consumed in the formation of gate layers26, which reduces spacing181approximately by the thickness of gate layers26. This reduction in spacing181is designated as reduced spacing or second reduction1811. In one embodiment, second reduction1811can be about 0.045 to about 0.055 microns.

With the presence of layers261and262along the lower sidewall portions of trenches22, lower portions260of gate layers26in trenches22can be thinner than the upper portions of gate layers26. This thinning effect is believed to be caused at least in part by stresses present in the various and different layers of material in proximity to where the thinning effect occurs. The gate dielectric layer thinning effect can lead to lower yields and/or impaired device performance.

FIG. 9illustrates a partial cross-sectional view of device10after additional processing. In a subsequent step, a layer of material is formed along gate layers26and overlying major surface18. In one embodiment, the layer of material can be a material that is different than gate layers26. In one embodiment, the layer of material can be an oxidation-resistant material. The layer of material can then be anisotropically etched to form spacer layers55along sidewall portions of gate layers26while leaving other portions of gate layers26exposed above shield electrodes21and shield electrode contact portion141. In one embodiment, spacer layers55can be a nitride material, such as a deposited silicon nitride. In one embodiment, spacer layers55can have a thickness from about 0.015 microns to about 0.02 microns. In one embodiment, lower portions of spacer layers55adjoin lower portions260of gate layers26as illustrated, for example, inFIG. 9.

FIG. 10illustrates a partial cross-sectional view of device10in accordance with an alternative embodiment. In an alternative processing step, a layer of crystalline semiconductor material can be formed along gate layers26and overlying major surface18before the layer of material used to form spacer layers55is formed. The layer of material used to form spacer layers55can then be formed along the layer of crystalline semiconductor material. Both layers can then be anisotropically etched to form spacer layers55and56as illustrated, for example, inFIG. 10. Alternatively, the layer of crystalline semiconductor layer can be anisotropically etched before layers55are formed. In one embodiment, spacer layers56can comprise about 0.03 microns of polysilicon, and can be doped or undoped. In another embodiment, spacer layers56can comprise 0.03 microns of amorphous silicon, and can be doped or undoped.

FIG. 11illustrates a partial cross-sectional view of device10based on theFIG. 9embodiment after additional processing. In accordance with the present embodiment, layers127can be formed adjacent shield electrodes21and shield electrode contact portion141. In one embodiment, layers127can comprise a dielectric or insulative material, and are configured, for example, as interpoly dielectric layers or inter-electrode dielectric layers. In one embodiment, layers127can comprise a silicon oxide formed using wet or thermal oxidation techniques. In one embodiment, layers127can have a thickness from about 0.1 microns to about 0.3 microns. In accordance with the present embodiment, spacers55(and optionally56) are configured to provide a localized oxidation effect that compensates for the thinning of gate layers26along lower portions260. In one embodiment, layers127increase the thickness of the gate layers26in proximity to where gate layers26and shield dielectric structure259meet or adjoin.

In related devices where the gate dielectric layers are formed after the interpoly dielectric layer is formed, the gate thinning effect is not appropriately addressed, which can cause lower yields and/or impaired device performance. In the present embodiment, the dielectric layer used to form gate layer26is formed before interpoly dielectric layer127is formed, and in accordance with the present embodiment, the impact of the gate layer thinning effect is reduced with the localized oxidation process thereby improving, for example, performance and yields. Additionally, the thinning effect can be addressed while the interpoly dielectric is formed without added processing costs. Moreover, because gate layers26are formed before the formation of layers127and not later stripped and reformed as in related devices, the integrity of the interface between semiconductor layer14and gate layers26can be maintained, for example, by reducing exposure of the interface to contamination and/or damage.

FIG. 12illustrates a partial cross-sectional view of device10after further processing. In subsequent steps, spacers55(and56if present) can be removed. In one embodiment, dielectric layer472can also be removed. In an optional step, an oxidation process can be used to increase or add to the thickness of gate layers26. Subsequently, a conductive or crystalline semiconductor layer281can be formed overlying major surface18and within trenches22and27. In one embodiment, layer281can comprise doped polysilicon. In one embodiment, the polysilicon can be doped with an n-type dopant, such as phosphorous or arsenic. Subsequently, a masking layer (not shown) can be formed overlying major surface18and a removal step can be used to remove portions of layer281from within trench27. The masking layer can then be removed.

In accordance with the present embodiment, a layer of material can be formed overlying major surface18and along upper portions or portions of trench27. In one embodiment, the layer of material can be a dielectric or insulative material. In one embodiment, the layer of material can comprise a deposited oxide, and can have a thickness from about 0.08 microns to about 0.12 microns. The layer of material can then be anisotropically etched to form spacer layers68within trench27. The anisotropic etch step can also remove portions of layer127to form an opening1270in layer127in trench27to expose a portion of shield contact portion141. In accordance with the present embodiment, shield contact portion141is configured to provide a flat or horizontal portion1410for making subsequent contact to another shield electrode portion142(illustrated inFIG. 14). In one embodiment, flat portion1410can be generally oriented parallel to major surface19of substrate12. In one embodiment, flat portion1410can be generally oriented perpendicular to sidewall portions271of trench27. Flat portion1410is further illustrated inFIG. 13, which is a 90 degree rotation of contact area103of device10. In one embodiment, flat portion1410terminates in a recessed configuration within trench27in contact area103. Flat portion1410is an improvement over related devices where the shield contact structure curves upwards to major surface18as single or continuous structure. In related devices, the formation of the curved portion of the shield contact structure was found to cause yield issues.FIG. 13further illustrates a gate electrode contact portion282, which can also be formed in contact area103and is configured for providing external electrical connection to gate electrodes28within active portion102of device10. In one embodiment, gate electrode contact portion282can be formed as part of layer281.

FIG. 14illustrates a partial cross-sectional view of device10after further processing. A layer of material can be formed overlying major surface18and within trench27. In one embodiment, the layer of material can comprise crystalline semiconductor material, a conductive material, or combinations thereof. In one embodiment, the layer of material can comprise doped polysilicon. In one embodiment, the polysilicon can be doped with an n-type dopant, such as phosphorous or arsenic. Subsequently, the layer of material can be planarized using dielectric layer471as a stop layer. In one embodiment, chemical mechanical planarization can be used for the planarization step. The planarization step can be used to form shield contact portion142, which in accordance with the present embodiment contacts shield contact portion141along flat portion1410. In addition, the planarization step can form gate electrodes28within trenches22as illustrated, for example, inFIG. 14.

Subsequently, a masking layer (not shown) can be formed overlying contact area103, and body, base, or doped regions31can be formed extending from major surface18adjacent to trenches22. Body regions31can have a conductivity type that is opposite to the conductivity type of semiconductor layer14. In one embodiment, body regions31can have p-type conductivity, and can be formed using, for example, a boron dopant source. Body regions31have a dopant concentration suitable for forming inversion layers that operate as conduction channels or channel regions45(illustrated, for example, inFIG. 17) of device10. Body regions31can extend from major surface18to a depth, for example, from about 0.5 microns to about 2.0 microns. It is understood that body regions31can be formed at an earlier stage of fabrication, for example, before trenches22are formed. Body regions31can be formed using doping techniques, such as ion implantation and anneal techniques.

FIG. 15illustrates a partial cross-sectional view of device10after additional processing. In a subsequent step, a masking layer131can be formed overlying portions of major surface18. In one embodiment, source regions, current conducting regions, or current carrying regions33can be formed within, in, or overlying body regions31, and can extend from major surface18to a depth, for example, from about 0.1 microns to about 0.5 microns. In one embodiment, source regions33can have n-type conductivity, and can be formed using, for example, a phosphorous or arsenic dopant source. In one embodiment, an ion implant doping process can be used to form source regions33within body regions31. Masking layer131can then be removed, and the implanted dopant can be annealed.

Gate electrodes28and shield electrode contact portion142can be recessed below major surface18as illustrated inFIG. 16. In one embodiment, about 0.15 microns to about 0.25 microns of material can be removed as a result of the recessing step. In an optional step, enhancement or conductive regions89can be formed within upper surfaces of gate electrodes28and/or shield electrode contact portion142. In one embodiment, conductive regions89can be self-aligned silicide structures. In one embodiment, conductive regions89can be a cobalt silicide. A layer of material477can then formed overlying major surface18, gate electrode28, and shield electrode contact portion142. In one embodiment, layer of material477can be a dielectric or insulative material. In one embodiment, layer of material477can be a nitride layer, such as a deposited silicon nitride layer, and can have thickness of about 0.05 microns.

In one embodiment, a layer or layers41can be formed overlying major surface18. In one embodiment, layers41comprise dielectric or insulative layers, and can be configured as an inter-layer dielectric (ILD) structure. In one embodiment, layers41can be silicon oxides, such as doped or undoped deposited silicon oxides. In one embodiment, layers41can include at least one layer of deposited silicon oxide doped with phosphorous or boron and phosphorous, and at least one layer of undoped oxide. In one embodiment, layers41can have a thickness from about 0.4 microns to about 1.0 microns. In one embodiment, layers41can be planarized to provide a more uniform surface topography, which improves manufacturability.

Subsequently, a masking layer (not shown) can be formed overlying device10, and openings, vias, or contact trenches422can be formed for making contact to source regions33, body regions31, and shield contact portion142as illustrated, for example, inFIG. 17. In one embodiment, the masking layer can be removed, and a recess etch can be used to remove portions of source regions33and portions of shield contact portion142. The recess etch step can expose portions of body regions31below source regions33. A p-type body contact, enhancement region, or contact region36can then be formed in body regions31, which can be configured to provide a lower contact resistance to body regions31. Ion implantation (for example, using boron) and anneal techniques can be used to form contact regions36.

Conductive regions43can then be formed in contact trenches422and configured to provide for electrical contact to source regions33, body regions31through contact regions36, and shield electrode contact portion142. In one embodiment, conductive regions43can be conductive plugs or plug structures. In one embodiment, conductive regions43can include a conductive barrier structure or liner and a conductive fill material. In one embodiment, the barrier structure can include a metal/metal-nitride configuration, such as titanium/titanium-nitride or other related or equivalent materials as known by one of ordinary skill in the art. In another embodiment, the barrier structure can further include a metal-silicide structure. In one embodiment, the conductive fill material includes tungsten. In one embodiment, conductive regions43can be planarized to provide a more uniform surface topography.

A conductive layer44can be formed overlying major surface18, and a conductive layer46can be formed overlying major surface19. Conductive layers44and46typically are configured to provide electrical connection between the individual device components of device10and a next level of assembly. In one embodiment, conductive layer44can be titanium/titanium-nitride/aluminum-copper or other related or equivalent materials as known by one of ordinary skill in the art, and is configured as a source electrode or terminal. In one embodiment, conductive layer46can be a solderable metal structure, such as titanium-nickel-silver, chromium-nickel-gold, or other related or equivalent materials as known by one of ordinary skill in the art, and is configured as a drain electrode or terminal. In one embodiment, a further passivation layer (not shown) can be formed overlying conductive layer44. In one embodiment, all or a portion of shield electrodes21can be connected to conductive layer44so that shield electrodes21are configured to be at the same potential as source regions33when device10is in use. In another embodiment, shield electrodes21can be configured to be independently biased or coupled in part to gate electrodes28.

In one embodiment, the operation of device10can proceed as follows. Assume that source electrode (or input terminal)44and shield electrodes21are operating at a potential VSof zero volts, gate electrodes28would receive a control voltage VGof 4.5 volts, which is greater than the conduction threshold of device10, and drain electrode (or output terminal)46would operate at a drain potential VDof less than 2.0 volts. The values of VGand VSwould cause body regions31to invert adjacent gate electrodes28to form channels45, which would electrically connect source regions33to semiconductor layer14. A device current IDSwould flow from drain electrode46and would be routed through semiconductor layer14, channels45, and source regions33to source electrode44. In one embodiment, IDSis on the order of 10.0 amperes. To switch device10to the off state, a control voltage VGthat is less than the conduction threshold of device10would be applied to gate electrodes28(e.g., VG<1.0 volts). Such a control voltage would remove channels45and IDSwould no longer flow through device10. In accordance with the present embodiment, gate layers26are formed before interpoly dielectric layers127. The method subsequently used to form interpoly dielectric layers127reduces the gate layer thinning effect, which improves yields and device performance. Also, by using a multi-portioned shield contact structure (for example, elements141and142) and a flat portion (for example, element1410), an improved shield electrode contact structure is formed for providing electrical contact to shield electrodes21, which improves yields and performance.

The foregoing method and structure provides several advantages over related devices. For example, the method and structure can facilitate a die shrink to about 0.8 microns or less, which can improve performance parameters, such as specific on-resistance. Also, the method and structure facilitates higher yield and improved shield electrode contact integrity compared to related devices.

From all of the foregoing, one skilled in the art can determine that according to one embodiment, a method for forming an electrode contact structure comprises the steps of providing a region of semiconductor material (for example, element11) having a major surface (for example, element18). The method includes forming a contact trench (for example, element27) extending from the major surface into the region of semiconductor material and forming a first dielectric layer (for example, element261,262) along surfaces of the contact trench. The method includes forming a first electrode contact portion (for example, element141) adjacent the first dielectric layer, wherein the first electrode contact portion is recessed below the first major surface. The method includes forming a second dielectric layer (for example, element127) overlying the first electrode contact portion. The method includes forming spacers (for example, element68) along upper sidewall surfaces (for example, element271) of the contact trench. The method includes forming an opening (for example, element1270) in the second dielectric layer aligned to the spacers. The method includes forming a second electrode contact portion (for example, element142) within the contact trench adjacent the spacers and contacting the first electrode contact portion within the contact trench.

Those skilled in the art will also appreciate that according to another embodiment, the method can further include the steps of forming a first conductive layer within the contact trench, and removing portions of the first conductive layer while leaving another portion of the first conductive layer (for example, element141) within a lower portion of the contact trench, wherein the removing step forms the first electrode contact portion with a horizontal portion (for example, element1410), and wherein the step of forming the second electrode contact portion includes forming the second contact portion so that the second contact portion makes contact to the first electrode contact portion along the horizontal portion.

Those skilled in the art will also appreciate that according to another embodiment, the method can further include the steps of forming a third dielectric layer (for example, element26) along upper surfaces (for example, element271) of the contact trench and overlying the first electrode contact portion, and forming oxidation-resistant spacers (for example, element55) along the third dielectric layer, wherein the step of forming the second dielectric layer comprises forming the second dielectric layer using localized oxidation.

Those skilled in the art will also appreciate that according to another embodiment, the method can further include the steps of forming an inter-layer dielectric (for example, element41) overlying the major surface, forming an opening (for example, element422) in the interlayer dielectric aligned to the second electrode contact portion, and forming a conductive plug (for example, element43) in the opening and contacting the second electrode contact portion.

Those skilled in the art will also appreciate that according to still another embodiment a method for forming a semiconductor device comprises the steps of providing a region of semiconductor material (for example, element11) having first and second opposing major surfaces (for example, elements18,19). The method includes forming a contact trench (for example, element27) extending from the first major surface into the region of semiconductor material. The method includes forming a first dielectric layer (for example, element261,262) along surfaces of the contact trench. The method includes forming a first shield electrode contact portion (for example, element141) adjacent the first dielectric layer, wherein the first electrode contact portion is recessed below the first major surface and includes a flat portion (for example, element1410) parallel to the second major surface. The method includes forming a second dielectric layer (for example, element127) overlying the first electrode contact portion. The method includes forming an opening (for example, element1270) in the second dielectric layer. The method includes forming a second shield electrode contact portion (for example, element142) within the contact trench contacting the first electrode contact portion within the contact trench and along the flat portion.

Those skilled in the art will also appreciate that according to another embodiment, the method can further comprise the steps of forming a third dielectric layer (for example, element26) along upper surfaces of the contact trench and overlying the first electrode contact portion, and forming oxidation-resistant spacers (for example, element55) along the third dielectric layer, wherein the step of forming the second dielectric layer comprises forming the second dielectric layer using localized oxidation.

Those skilled in the art will also appreciate that according to another embodiment, the method can further include the steps of recessing the second electrode contact portion within the contact trench below the first major surface, forming a conductive region (for example, element89) in an upper portion of the second electrode contact portion, forming an inter-layer dielectric (for example, element41) overlying the major surface, forming an opening (for example, element422) in the interlayer dielectric aligned to the second electrode contact portion, and forming a conductive plug (for example, element43) in the opening and contacting the second electrode contact portion.

Those skilled in the art will also appreciate that according to yet another embodiment, a method of forming a semiconductor device having a shield electrode comprises the steps of providing a region of semiconductor material (for example, element11) having first and second opposing major surfaces (for example, element18,19). The method includes forming a contact trench (for example, element27) extending from the first major surface into the region of semiconductor material. The method includes forming a first dielectric layer (for example, element261,262) along surfaces of the contact trench. The method includes forming a first shield electrode contact portion (for example, element141) adjacent the first dielectric layer, wherein the first electrode contact portion is recessed below the first major surface and includes a portion (for example, element1410) parallel to the second major surface. The method includes forming oxidation-resistant spacers (for example, element55) along upper sidewall surfaces of the contact trench. The method includes forming a second dielectric layer (for example, element127) overlying the first electrode contact portion using localized oxidation. The method includes forming an opening (for example, element1270) in the second dielectric layer. The method includes forming a second shield electrode contact portion (for example, element142) within the contact trench contacting the first electrode contact portion within the contact trench and along the portion parallel to the second major surface.

Those skilled in the art will also appreciate that according to another embodiment, the method can further comprise the step of forming dielectric spacers (for example, element68) along the upper sidewall surfaces of the contact trench before the step of forming the opening in the second dielectric layer, wherein the step of forming the opening includes forming the opening self-aligned to the spacers, and wherein the step of forming the second electrode contact portion includes forming the second electrode contact portion adjacent the dielectric spacers.

Those skilled in the art will also appreciate that according to another embodiment, the method can further comprise the step of forming a third dielectric layer (for example, element26) along the upper sidewall surfaces of the contact trench before the step of forming the oxidation-resistant spacers.

Those skilled in the art will also appreciate that according to yet a further embodiment, an electrode contact structure comprises a region of semiconductor material (for example, element11) having first and second opposing major surfaces (for example, elements18,19), wherein the region of semiconductor material includes an active area (for example,102) and a contact area (for example, element103). The structure includes a contact trench (for example, element27) extending from the first major surface into the region of semiconductor material. The structure includes a first dielectric layer (for example, element261,262) formed along surfaces of the contact trench, and a first shield electrode contact portion (for example, element141) formed adjacent the first dielectric layer, wherein the first electrode contact portion is recessed below the first major surface and includes a flat portion (for example, element1410) parallel to the second major surface. The structure includes a second dielectric layer (for example, element127) formed overlying a part of the first electrode contact portion, and a second shield electrode contact portion (for example, element142) formed in the contact trench and contacting the first electrode contact portion along the flat portion.

Those skilled in the art will also appreciate that according to a still further embodiment, a shield electrode contact structure comprises a contact trench (for example, element27) formed in a region of semiconductor material (for example, element11) having first and second opposing major surfaces (for example, elements18,19). The structure includes a first conductive contact portion (for example, element141) formed in a lower portion of the contact trench and having a recessed surface (for example, element1410) that is parallel to the second major surface, wherein the first conductive contact portion is insulated (for example, element259) from the region of semiconductor material, and wherein the first conductive contact portion is further coupled to at least one shield electrode structure in an active portion of the region of semiconductor material. The structure includes a second conductive contact portion (for example, element142) formed in the contact trench and contacting the first conductive contact portion along the recessed surface.

In view of all the above, it is evident that a novel method and structure disclosed. Included, among other features, is a shield electrode contact structure formed in more than one portions, where a first portion is formed recessed within a contact trench and formed with a flat portion. A second portion is formed overlying the first portion and makes contact to the first portion along the flat portion. The method improves yields and devices performance by reducing manufacturing problems associated with related contact structures that use continuous conductive layers that curve upwards towards the major surface of the device.

While the subject matter of the invention is described with specific preferred embodiments and example embodiments, the foregoing drawings and descriptions thereof depict only typical embodiments of the subject matter, and are not therefore to be considered limiting of its scope. It is evident that many alternatives and variations will be apparent to those skilled in the art. For example, the subject matter has been described for a particular n-channel MOSFET structure, although the method and structure is directly applicable to other MOS transistors, as wells as bipolar, BiCMOS, metal semiconductor FETs (MESFETs), HFETs, thyristors bi-directional transistors, and other transistor structures.

As the claims hereinafter reflect, inventive aspects may lie in less than all features of a single foregoing disclosed embodiment. Thus, the hereinafter expressed claims are hereby expressly incorporated into this Detailed Description of the Drawings, with each claim standing on its own as a separate embodiment of the invention. Furthermore, while some embodiments described herein include some but not other features included in other embodiments, combinations of features of different embodiments are meant to be within the scope of the invention, and form different embodiments, as would be understood by those skilled in the art.