Display driving circuit and operating method of the same

A display driving circuit according to an example embodiment of the inventive concept is disclosed. A display driving circuit may include an interface configured to receive a synchronization packet and image data from the outside; a memory configured to receive the image data from the interface in the command mode; a synchronization controller configured to receive the synchronization packet and generate a flag control signal and an internal synchronization signal; a flag generator configured to generate a first flag signal and a second flag signal; and an image controller configured to receive the image data from the memory in the command mode, receive the image data from the interface in the video mode, wherein the synchronization controller is configured to calculate a delay time between a generation time of the first flag signal and a reception time of the synchronization packet, and is configured to adjust a generation time of the second flag signal.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based on and claims priority under 35 U. S. C. § 119 to Korean Patent Application No. 10-2020-0170744, filed on Dec. 8, 2020, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety.

BACKGROUND

At least one technical idea of the inventive concepts relates to a display driving circuit, and in particular, to a display driving circuit for driving a display panel so that an image is displayed on the display panel, and a method of operating the same.

A display device includes a display panel displaying an image and a display driving circuit driving the display panel. The display driving circuit may drive the display panel by receiving image data from a processor and applying an image signal corresponding to the received image data to the data line of the display panel. The display device may be implemented in various forms such as a liquid crystal display (LCD), a light emitting diode (LED) display, an organic LED (OLED) display, and an active matrix OLED (AMOLED) display.

The display device may operate in various operation modes through the control of a host, and seamless switching of the operation mode may be required to switch the operation mode.

SUMMARY

At least one problem to be solved by at least one technical idea of the inventive concepts is to provide a display driving circuit that operates in a command mode and a video mode, which are a plurality of operation modes.

A display driving circuit operating in a video mode and a command mode, according to example embodiments of the inventive concepts for solving the technical problem, the display driving circuit may include an interface configured to receive a synchronization packet and image data from the outside; a memory configured to receive the image data from the interface in the command mode; a synchronization controller configured to receive the synchronization packet from the interface and generate a flag control signal and an internal synchronization signal; a flag generator configured to generate a first flag signal and a second flag signal in response to the flag control signal; and an image controller configured to receive the image data from the memory in the command mode, receive the image data from the interface in the video mode, and drive a display panel based on the image data, wherein the synchronization controller is configured to calculate a delay time between a generation time of the first flag signal and a reception time of the synchronization packet, and is configured to adjust a generation time of the second flag signal based on the delay time.

A method of operating a display driving circuit operating in a video mode and a command mode according to example embodiments of the inventive concepts for solving the technical problem, the method may include receiving, from a host, a command for changing from the command mode to the video mode; generating a first flag signal to transmit the generated first flag signal to the host; receiving a synchronization packet depending on the first flag signal; and adjusting a generation time of a second flag signal and switching a mode to the video mode, based on a delay time between a generation time of the first flag signal and a reception time of the synchronization packet depending on the first flag signal.

A method of operating a display driving circuit according to example embodiments of the inventive concepts for solving the technical problem, the method may include generating a first flag signal and transmitting the generated first flag signal to a host; receiving a synchronization packet depending on the first flag signal and image data; storing the image data in a memory based on a result of comparing a delay time between a generation time of the first flag signal and a reception time of the synchronization packet depending on the first flag signal with a reference time; and adjusting a generation time of a second flag signal by changing the reference time based on the delay time.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

Hereinafter, various example embodiments of the inventive concepts will be described in connection with the accompanying drawings.

FIG.1is a block diagram illustrating a display system according to example embodiments of the inventive concepts.

A display system10according to example embodiments of the inventive concepts may be mounted on, or otherwise interface with, an electronic device having an image display function. For example, electronic devices may include smartphones, tablet personal computers (PCs), portable multimedia players (PMPs), cameras, wearable devices, internet of thing devices, and televisions, digital video disk (DVD) players, refrigerators, air conditioners, air purifiers, set-top boxes, robots, drones, various medical devices, navigation devices, global positioning system (GPS) receivers, advanced drivers assistance system (ADAS), vehicle devices, furniture, or various measuring devices.

Referring toFIG.1, the display system10may include a host200, a display driving circuit110(or a display driving integrated circuit), and/or a display panel120. In example embodiments, the display driving circuit110and the display panel120may be implemented as one module, and the module may be referred to as a display device100. For example, the display driving circuit110may be mounted on a circuit film such as a tape carrier package (TCP), a chip on film (COF), or a flexible print circuit (FPC), and may be attached to the display panel120in a tape automatic bonding (TAB) manner or be mounted on a non-display area of the display panel120in a chip on glass (COG) or chip on plastic (COP) manner.

The host200may overall control the display system10. The host200may generate image data IDT to be displayed on the display panel120, and may transmit the image data IDT, a synchronization packet SYNC_PAC, and a command (e.g., mode change command CMD) to the display driving circuit110. InFIG.1, the image data IDT, the synchronization packet SYNC_PAC, and the command CMD are shown as separate signals, but may be transmitted to the display driving circuit110in a single packet, and may be separated from each other in an interface111of the display driving circuit110.

The host200may be an application processor. However, the present inventive concepts are not limited thereto, and the host200may be implemented as various types of processors such as a central processing unit (CPU), a microprocessor, a multimedia processor, and a graphic processor. In example embodiments, the host200may be implemented as an integrated circuit (IC), and may be implemented as a mobile application processor (AP) or a system on chip (SoC).

The host200may include a display processor210and an interface220. The display processor210may control the operation of the display device100. The display processor210may transmit image data IDT to be displayed on the display device100, the synchronization packet SYNC_PAC for timing control, and the command CMD for changing an operation mode of the display device100to the display device100through the interface220.

The display driving circuit110may display an image on the display panel120by converting the image data IDT received from the host200into image signals for driving the display panel120, and supplying the image signals to the display panel120.

The display driving circuit110may operate in a plurality of operation modes. The operation modes may include a command mode receiving only image data IDT from the host200and a video mode for receiving image data IDT and the synchronization packet SYNC_PAC for timing control from the host200together. For example, the display device100may display a still image in the command mode and a moving image in the video mode. The display driving circuit110may switch the operation mode in response to the command CMD received from the host200. In order to seamlessly switch the operation mode from the command mode to the video mode, the display driving circuit110may operate in a switching mode between a section operating in the command mode and a section operating in the video mode. The operation of the display driving circuit110in the switching mode will be described in detail in the following drawings.

The display driving circuit110may include the interface111, a memory112, a synchronization controller113, a display controller114, a driver115, and/or a flag generator116. The display driving circuit110may receive the image data IDT, the synchronization packet SYNC_PAC, and the command CMD from the host200through the interface111. In example embodiments, the interface220of the host200and the interface111of the display driving circuit110may be a mobile industry processor interface (MIPI).

The memory112may store the image data IDT received through the interface111in the command mode and may transmit the image data IDT to the display controller114. In example embodiments, the memory112may be a graphic RAM (GRAM). On the other hand, in the video mode, the image data IDT received through the interface111is not stored in the memory112and may be transmitted to the display controller114.

The synchronization controller113may receive the synchronization packet SYNC_PAC through the interface111. The synchronization controller113may receive the synchronization packet SYNC_PAC through the interface111in the video mode, and generate internal synchronization signals VSYNC and HSYNC based on the synchronization packet SYNC_PAC. The synchronization controller113may output an internal vertical synchronization signal VSYNC having the same period as the period of the vertical synchronization packet of the synchronization packet SYNC_PAC, and may output an internal horizontal synchronization signal HSYNC having the same period as the period of the horizontal synchronization packet of the synchronization packet SYNC_PAC.

On the other hand, the synchronization controller113may directly generate the internal synchronization signals VSYNC and HSYNC without receiving the synchronization packet SYNC_PAC in the command mode. The internal synchronization signals VSYNC and HSYNC may include the internal vertical synchronization signal VSYNC and the internal horizontal synchronization signal HSYNC.

The synchronization controller113may transmit a flag control signal FCS to the flag generator116. The synchronization controller113may generate the flag control signal FCS to synchronize the synchronization packet SYNC_PAC and the internal synchronization signals VSYNC and HSYNC with each other in the switching mode for switching from the command mode to the video mode.

The display controller114may generate control signals for controlling the driver115by receiving image data IDT and the internal synchronization signals VSYNC and HSYNC. The driver115may provide voltages to gate lines and data lines of the display panel120in response to the control signals. The operation of the display controller114and the driver115will be described in detail later with reference toFIG.2.

The flag generator116may generate a flag signal (TE, or a tearing effect control signal) in response to the flag control signal FCS, and may transmit the flag signal TE to the host200. For example, a rising edge of the flag signal TE may be regarded as a generation time of the flag signal TE.

The host200may receive the flag signal TE and control a generation time or transmission time of the synchronization packet SYNC_PAC based on the flag signal TE. Accordingly, a generation time of the internal synchronization signals VSYNC and HSYNC, that is, a start time of each period of the internal synchronization signals VSYNC and HSYNC for synchronization, may vary depending on the flag signal TE. For example, the generation time of the internal vertical synchronization signal VSYNC may be determined depending on the generation time of the flag signal TE.

The generation time of the flag signal TE may be controlled based on a preset reference time TR. For example, the reference time TR may be preset by the host200. The time from the time when the flag signal TE is generated to the time when the synchronization packet SYNC_PAC is predicted to be received by the display driving circuit110may be set as the reference time TR, and thus, the display driving circuit110may be set so that the flag signal TE is generated prior to the generation time of the internal synchronization signals VSYNC and HSYNC by the reference time TR.

In example embodiments, in the switching mode for switching from the command mode to the video mode, the synchronization controller113may adjust the reference time TR based on the generation time of the first flag signal, the reception time of the synchronization packet SYNC_PAC, and the generation time of the internal synchronization signals VSYNC and HSYNC. For example, the synchronization controller113may calculate a delay time between the generation time of the first flag signal and the reception time of the synchronization packet SYNC_PAC, and may change the reference time TR based on a result of comparing the delay time with the reference time TR. The synchronization controller113may adjust the generation time of the second flag signal to be transmitted following the first flag signal by adjusting the reference time TR, and may generate the flag control signal FCS based on the generation time of the adjusted second flag signal. The display driving circuit110may synchronize the synchronization packet SYNC_PAC and the internal synchronization signals VSYNC and HSYNC with each other by generating a flag control signal FCS for adjusting the generation time of the flag signal TE, and seamless conversion from the command mode to the video mode may be performed.

The display panel120is a display unit on which an image is actually displayed, and may be one of a thin film transistor-liquid crystal display (TFT-LCD), an organic light emitting diode (OLED) display, a field emission display, a plasma display panel (PDP), and the like, which are a display device that displays a two-dimensional image by receiving electrically transmitted image signals. The display panel120may be implemented as another type of flat panel display or a flexible display panel.

FIG.2is a block diagram illustrating a partial configuration of a display device according to example embodiments of the inventive concepts, and may correspond to the display controller114, the driver115, and the display panel120ofFIG.1.

Referring toFIGS.1and2, the driver115may include a scan driver115_1and a data driver115_2. However, the display driving circuit110may not include the scan driver115_1, and the scan driver115_1may be included in the display device100in a separate configuration from the display driving circuit110.

The display panel120includes a plurality of pixels PXs arranged in a matrix form, and may display an image for each frame. The display panel120may include scan lines SL1to SLn arranged in a row direction, data lines DL1to DLm arranged in a column direction, and the pixels PXs formed at intersections of the scan lines SL1to SLn and the data lines DL1to DLm.

The scan driver115_1may sequentially select the scan lines SL1to SLn by sequentially supplying a scan-on signal to the scan lines SL1to SLn in response to a scan control signal CTRL1provided from the display controller114. Based on the scan-on signal output from the scan driver115_1, the scan lines SL1to SLn are sequentially selected, and a gray voltage corresponding to the pixels PX is applied to the pixels PXs connected to the selected scan line through the data lines DL1to DLm, so that a display operation may be performed. During a period in which the scan-on signal is not supplied to the scan lines SL1to SLn, a scan-off signal (e.g., a scan voltage with a logic high level) may be supplied to the scan lines SL1to SLn.

In response to a data control signal CTRL2, the data driver115_2converts data DATA corresponding to the image data IDT into image signals, which are analog signals, and provide the image signals to the data lines DL1to DLm. The data driver115_2may include a plurality of channel amplifiers, and each of the plurality of channel amplifiers may provide image signals to at least one data line corresponding to each of the amplifiers.

The display controller114may control the overall operation of the display panel120. The display controller114may be implemented in hardware, software, or a combination of hardware and software, and for example, the display controller114may be implemented as digital logic circuits and registers that perform various functions below.

The display controller114may receive the image data IDT, an internal horizontal synchronization signal HSYNC, and an internal vertical synchronization signal VSYNC, and may generate a control signal (e.g., the scan control signal CTRL1and the data control signal CTRL2) for controlling the data driver115_2and the scan driver115_1based on the received signals. In addition, the display controller114may convert the format of the image data IDT received from the outside of the display driving circuit110to conform to the interface specification with the data driver115_2, and may transmit the converted data DATA to the data driver115_2.

FIGS.3and4are flowcharts illustrating a method of operating a display driving circuit according to example embodiments of the inventive concepts.FIG.3is a flowchart illustrating an operation of a display driving circuit in a switching mode prepared to change from a command mode to a video mode.FIG.4is an example of operation S50ofFIG.3, and operation S50may include operations S51to S57.

Referring toFIGS.1and3, the display driving circuit110may receive a command CMD for changing from the command mode to the video mode in operation S10. In response to the command CMD, the display driving circuit110may operate in the switching mode.

The display driving circuit110may generate and transmit the first flag signal to the host200in operation S20. When the host200receives the first flag signal, the host200may transmit the synchronization packet SYNC_PAC to the display driving circuit110. The display driving circuit110may receive the synchronization packet SYNC_PAC from the host200in operation S30.

The display driving circuit110may calculate a delay time between the generation time (or transmission time) of the first flag signal and the reception time of the synchronization packet SYNC_PAC in operation S40. For example, the display driving circuit110may calculate a difference time between the reception time of the synchronization packet SYNC_PAC and the generation time of the internal vertical synchronization signal VSYNC, and may calculate a delay time by calculating a difference value between the reference time TR and the difference time.

In operation S50, the display driving circuit110may adjust the generation time (or transmission time) of the second flag signal transmitted following the first flag signal based on the delay time, and switch the mode to the video mode. For example, when the delay time coincides with the reference time TR, it may be seen that the vertical synchronization packet included in the synchronization packet SYNC_PAC transmitted from the host200and the internal vertical synchronization signal VSYNC are synchronized with each other. Accordingly, the display driving circuit110may generate the second flag signal based on the reference time TR, and the mode may be seamlessly switched from the command mode to the video mode.

Referring toFIGS.1and4, in operation S51, the display driving circuit110may determine whether a delay time between the generation time of the first flag signal and the reception time of the synchronization packet coincides with the reference time TR. In the present specification, the term “coincidence” may mean that the difference between the two values is within a set error range, and an error range corresponding to a reference of the coincidence may be preset in the control logic of the display driving circuit110.

When the delay time between the generation time of the first flag signal and the reception time of the synchronization packet coincides with the reference time TR, the display driving circuit110may switch the mode to the video mode in operation S53. Following the first flag signal, a second flag signal may be generated based on a reference time TR.

As the mode is switched to the video mode, the display driving circuit110may generate the internal synchronization signals VSYNC and HSYNC based on the synchronization packet SYNC_PAC corresponding to the first flag signal, and the image data IDT received after transmitting the first flag signal may be transmitted to the display controller114without being stored in the memory112.

When the delay time between the generation time of the first flag signal and the reception time of the synchronization packet is different from the reference time TR, the display driving circuit110may store the image data IDT in the memory112in operation S55. In the present specification, the term “difference” may mean that the difference between the two values is outside a set error range.

In operation S57, the display driving circuit110may adjust the generation time of the second flag signal by adjusting the reference time TR based on the delay time and may switch the mode to the video mode. The flag signal TE may include the first flag signal and the second flag signal generated after the first flag signal.

For example, in operation S57, the display driving circuit110may change the reference time TR to coincide with the delay time, and adjust the generation time of the second flag signal depending on the changed reference time TR. The display driving circuit110may generate the internal synchronization signals VSYNC and HSYNC based on the synchronization packet SYNC_PAC corresponding to the second flag signal in the video mode, and the image data IDT received after transmitting the second flag signal may be transmitted to the display controller114without being stored in the memory112.

FIGS.5to7are timing diagrams for describing an operation of a display driving circuit according to example embodiments of the inventive concepts.FIGS.5to7are timing diagrams for explaining an operation of a display driving circuit in a switching mode preparing to change a mode from a command mode to a video mode. In the description ofFIGS.6and7, descriptions previously given with reference toFIG.5will be omitted.

Referring toFIGS.1and5, the display driving circuit110may receive a packet PAC from the host200, and the packet PAC may include a command CMD, image data IDT1and IDT2, a vertical synchronization packet VS, and a horizontal synchronization packet HS. In some example embodiments, the packet PAC may be a set of bits.

The first image data IDT1received in the command mode may be stored in the memory112, and an image may be displayed on the display panel120based on the first data DATA1corresponding to the first image data IDT1with a time difference from the time when the first image data IDT1is received.

When the command CMD for mode switching is received in the command mode, the display driving circuit110may operate in the switching mode from the time T0, the flag signal TE transmitted in the command mode is masked, and an image may be displayed on the display panel120depending on the first data DATA1until new image data is received.

The display driving circuit110may transmit the first flag signal TE1to the host200based on the reference time TR, and the host200may transmit the vertical synchronization packet VS by receiving the first flag signal TEL In some example embodiments, the first reception time TP1of the vertical synchronization packet VS based on the first flag signal TE1may be a time delayed by a delay time TD from the first generation time TT1of the first flag signal TEL The first generation time TT1of the first flag signal TE1may correspond to a rising edge of the first flag signal TEL

The reference time TR may be a reference time for determining a first generation time TT1at which the first flag signal TE1is first generated before generating the internal vertical synchronization signal VSYNC. Depending on the preset reference time TR, the display driving circuit110may generate the first flag signal TE1and then generate the internal vertical synchronization signal VSYNC after the reference time TR has elapsed.

The generation time TV1of the internal vertical synchronization signal VSYNC illustrated and described in the following timing diagrams includingFIG.5may mean the start time of one period of the internal vertical synchronization signal VSYNC. A frame may start at the start time of one period of the internal vertical synchronization signal VSYNC, and a section from the start time of one period of the internal vertical synchronization signal VSYNC to the start of the next period may mean one frame.

FIG.5illustrates an example in which the delay time TD coincides with the preset reference time TR. Referring toFIG.5, as the delay time TD coincides with the preset reference time TR, the first reception time TP1of the vertical synchronization packet VS received after the display driving circuit110transmits the first flag signal TE1may coincide with the generation time TV1generating the internal vertical synchronization signal VSYNC. Accordingly, the display driving circuit110may switch to the video mode after transmitting the first flag signal TE1, and the second image data IDT2received after transmitting the first flag signal TE1is not stored in the memory112and may be directly converted into second data DATA2.

The display driving circuit110may generate the second flag signal TE2based on the reference time TR in the video mode and transmit the second flag signal TE2to the host200. The host200may receive the second flag signal TE2and transmit the vertical synchronization packet VS.

Referring toFIGS.1and6, the display driving circuit110may receive a packet PAC from the host200, and the packet PAC may include a command CMD, image data IDT1, IDT2′, and IDT3, the vertical synchronization packet VS, and the horizontal synchronization packet HS.

The display driving circuit110may transmit a first flag signal TE1′ to the host200in the switching mode, and the host200receives the first flag signal TE1′ and transmits the vertical synchronization packet VS. In some example embodiments, a first reception time TP1′ of the vertical synchronization packet VS based on the first flag signal TE1′ may be a time delayed by a delay time TD′ from the first generation time TT1′ of the first flag signal TE1′.

With reference toFIG.6, an example in which the delay time TD′ is different from a preset first reference time TR1is described. In detail, an example in which the delay time TD′ is shorter than the first reference time TR1is described. The display driving circuit110may calculate a delay time TD′ by calculating a difference value between the first reference time TR1and a difference time TC′. In some example embodiments, the difference time TC′ may be a time between the first reception time TP1′ of the vertical synchronization packet VS based on the first flag signal TE1′ and the generation time TV1′ of generating the internal vertical synchronization signal VSYNC.

Because the first reception time TP1′ of the vertical synchronization packet VS based on the first flag signal TE1′ does not coincide with the generation time TV1′ of generating the internal vertical synchronization signal VSYNC, the display driving circuit110may continue to operate in the switching mode without switching to the video mode, and the second image data IDT2‘ received after transmitting the first flag signal TE1’ may be stored in the memory112and then converted into second data DATA2′ when a predetermined or alternatively, desired time elapses.

The display driving circuit110may newly set a second reference time TR2to coincide with the delay time TD′. For example, the second reference time TR2may be calculated by subtracting the difference time TC′ from the first reference time TR1.

The display driving circuit110may adjust the second generation time TT2of the second flag signal TE2′ based on the second reference time TR2. The display driving circuit110may transmit the second flag signal TE2′ to the host200at the adjusted second generation time TT2, and the host200may transmit the vertical synchronization packet VS by receiving the second flag signal TE2′. In some example embodiments, the second reception time TP2of the vertical synchronization packet VS based on the second flag signal TE2′ may be delayed by the delay time TD′ from the second generation time TT2of the second flag signal TE2′.

As the delay time TD′ coincides with the second reference time TR2, the second reception time TP2of the vertical synchronization packet VS received after the display driving circuit110transmits the second flag signal TE2′ may coincide with the generation time TV2at which the internal vertical synchronization signal VSYNC is generated. Accordingly, the display driving circuit110may switch to the video mode after transmitting the second flag signal TE2′, and the third image data IDT3received after transmitting the second flag signal TE2′ is not stored in the memory112and may be directly converted into third data DATA3.

However, unlikeFIG.6, when the delay time TD′ of the vertical synchronization packet VS based on the second flag signal TE2′ is different from the second reference time TR2, the display driving circuit110may not operate in the video mode. In order to generate a third flag signal for a next frame, a third reference time may be adjusted again based on the delay time TD′.

Referring toFIGS.1and7, the display driving circuit110may receive a packet PAC from the host200, and the packet PAC may include a command CMD, image data IDT1, IDT2″, and IDT3″, a vertical synchronization packet VS, and a horizontal synchronization packet HS.

The display driving circuit110may transmit a first flag signal TE1″ to the host200in the switching mode, and the host200may transmit a vertical synchronization packet VS by receiving the first flag signal TE1″. In some example embodiments, the first reception time TP1″ of the vertical synchronization packet VS based on the first flag signal TE1“may be delayed by a delay time TD” from the first generation time TT1″ of the first flag signal TE1″.

With reference toFIG.7, an example in which the delay time TD″ is different from a preset first reference time TR1″ is described, and in detail, the delay time TD “is greater than the first reference time TR1”. The display driving circuit110may calculate the delay time TD “by adding the difference time TC” to the first reference time TR1″. In some example embodiments, the difference time TC″ may be a time between the first reception time TP1″ of the vertical synchronization packet VS based on the first flag signal TE″ and a time TVE at which the first reference time TR1″ has elapsed after generating the first flag signal TE″.

Because the first reception time TP1″ of the vertical synchronization packet VS based on the first flag signal TE1″ does not coincide with the generation time TV1″ of generating the internal vertical synchronization signal VSYNC, the display driving circuit110may continue to operate in the switching mode without switching to the video mode, and the second image data IDT2″ received after transmitting the first flag signal TE1“may be stored in the memory112and then converted into second data DATA2” when a predetermined or alternatively, desired time elapses.

The display driving circuit110may be set to generate an internal vertical synchronization signal VSYNC after the first flag signal TE1″ is generated and then the first reference time TR1″ elapses. When the first delay time TD1″ is longer than the first reference time TR″, that is, when the vertical synchronization packet VS is not received even if the first reference time TR1″ elapses after generating the first flag signal TE1the display driving circuit110may increase the corresponding frame by the extended time ET. By generating the internal vertical synchronization signal VSYNC after the extended time ET from the time TVE at which the first reference time TR1″ has elapsed after generating the first flag signal TE1″, the section of a frame in which an image based on the first data DATA1″ is displayed on the display panel120may be increased. That is, the display driving circuit110may delay the generation time TV1″ of the internal vertical synchronization signal VSYNC corresponding to the first flag signal TE1″ later than the time TVE at which the first reference time TR1″ has elapsed after generating the first flag signal TE1″. In example embodiments, the display driving circuit110may increase the section of the frame in a luminance adjustment unit, and for example, the extension time ET may be a multiple of the luminance adjustment unit.

The display driving circuit110may newly set the second reference time TR2“to coincide with the delay time TD”. For example, the second reference time TR2“may be calculated by adding the difference time TC” to the first reference time TR1″.

The display driving circuit110may adjust the second generation time TT2″ of the second flag signal TE2″ based on the second reference time TR2″. The display driving circuit110may transmit a second flag signal TE2″ to the host200at the adjusted second generation time TT2″, and the host200may receive the second flag signal TE2″ and transmit the vertical synchronization packet VS. In some example embodiments, the second reception time TP2″ of the vertical synchronization packet VS based on the second flag signal TE2″ may be delayed by the delay time TD″ from the second generation time TT2″ of the second flag signal TE2″.

As the delay time TD″ coincides with the second reference time TR2″, the second reception time TP2of the vertical synchronization packet VS received after the display driving circuit110transmits the second flag signal TE2″ may coincide with the generation time TV2″ at which the internal vertical synchronization signal VSYNC is generated. Accordingly, the display driving circuit110may switch to the video mode after transmitting the second flag signal TE2″, and the third image data IDT3″ received after transmitting the second flag signal TE2″ is not stored in the memory112and may be directly converted into third data DATA3″.

However, unlikeFIG.7, when the delay time TD″ of the vertical synchronization packet VS based on the second flag signal TE2″ is different from the second reference time TR2″, the display driving circuit110may not operate in the video mode. In order to generate a third flag signal for a next frame, a third reference time may be adjusted again based on the delay time TD″.

FIGS.8A to8Care block diagrams illustrating a synchronization controller of a display driving circuit according to example embodiments of the inventive concepts.FIG.8Amay be a diagram for explaining an operation of a synchronization controller in a command mode,FIG.8Bmay be a diagram for explaining an operation of a synchronization controller in a switching mode, andFIG.8Cmay be a diagram for explaining an operation of the synchronization controller in a video mode. Alternatively,FIG.8Bmay be a diagram for explaining an operation of a synchronization controller in a video memory mode of a video mode to be described with reference toFIGS.10and11, andFIG.8Cmay be a diagram for explaining an operation of a synchronization controller in a normal video mode of a video mode to be described with reference toFIGS.10and11.

Referring toFIGS.1and8A, the synchronization controller113may include a synchronization packet detector113_1, a synchronization signal generator113_2, a delay calculator113_3, and/or an internal synchronization controller113_4. Each of the synchronization packet detector113_1, the synchronization signal generator113_2, the delay calculator113_3, and the internal synchronization controller113_4may be implemented in hardware or software.

In the command mode, the internal synchronization controller113_4may control the synchronization signal generator113_2, and the synchronization signal generator113_2may generate an internal vertical synchronization signal VSYNC and an internal horizontal synchronization signal HSYNC under the control of the internal synchronization controller113_4. Under the control of the internal synchronization controller113_4, the synchronization signal generator113_2may adjust the generation time and output time of the internal vertical synchronization signal VSYNC and the internal horizontal synchronization signal HSYNC. That is, in the command mode, the synchronization controller113may directly determine a timing and a generation period at which the internal vertical synchronization signal VSYNC and the internal horizontal synchronization signal HSYNC are generated.

Referring toFIGS.1and8B, in the switching mode, the synchronization packet detector113_1may detect the synchronization packet SYNC_PAC and transmit the detected synchronization packet SYNC_PAC to the delay calculator113_3. The delay calculator113_3may calculate a delay time TD.

The delay calculator113_3may acquire the difference time between the reception time of the vertical synchronization packet of the synchronization packet SYNC_PAC and the generation time of generating the internal vertical synchronization signal VSYNC, and may calculate a delay time TD using the difference time and the reference time TR. Accordingly, a new reference time may be set, and based on the newly changed reference time, the delay calculator113_3may transmit the flag control signal FCS to the flag generator116.

In the switching mode, the synchronization controller113may directly determine a timing and a generation period at which the internal vertical synchronization signal VSYNC and the internal horizontal synchronization signal HSYNC are generated.

Referring toFIGS.1and8C, when the reference time coincides with the calculated delay time, the display driving circuit110may operate in a video mode. In the video mode, the synchronization packet detector113_1may detect the synchronization packet SYNC_PAC and transmit the detected synchronization packet SYNC_PAC to the synchronization signal generator113_2, and the synchronization signal generator113_2may generate an internal vertical synchronization signal VSYNC and an internal horizontal synchronization signal HSYNC based on the vertical synchronization packet and the horizontal synchronization packet included in the synchronization packet SYNC_PAC. For example, the synchronization signal generator113_2may generate the internal vertical synchronization signal VSYNC based on the vertical synchronization packet included in the synchronization packet SYNC_PAC, and generate the internal horizontal synchronization signal HSYNC based on the horizontal synchronization packet included in the synchronization packet SYNC_PAC.

That is, in the video mode, the synchronization controller113does not directly determine the timing and generation period at which the internal vertical synchronization signal VSYNC and the internal horizontal synchronization signal HSYNC are generated, but may determine the timing and generation period based on the received synchronization packet SYNC_PAC.

FIG.9are flowcharts illustrating a method of operating a display driving circuit according to example embodiments of the inventive concepts.FIG.9is a flowchart illustrating an operation of a display driving circuit in a video mode. That is, the display driving circuit may perform operations S100to S700in the video mode, and the video mode may include the normal video mode and the video memory mode.

Referring toFIGS.1and9, in operation S100, the display driving circuit110may calculate a delay time between the generation time of the flag signal TE and the reception time of the synchronization packet SYNC_PAC in the video mode. For example, the display driving circuit110may obtain a difference time between the reception time of the synchronization packet SYNC_PAC and the generation time of the internal vertical synchronization signal VSYNC, and may calculate a delay time using the reference time TR and the difference time. In the following operations, the image data IDT may be stored in the memory based on the result of comparing the delay time with the reference time TR, and the generation time of the second flag signal may be adjusted by changing the reference time TR based on the delay time.

The display driving circuit110may determine whether the delay time coincides with the reference time TR in operation S200. When the delay time coincides with the reference time TR, the display driving circuit110may operate in the normal video mode in operation S300. As described inFIG.8C, in the normal video mode, the synchronization controller113does not directly determine the timing and generation period at which the internal vertical synchronization signal VSYNC and the internal horizontal synchronization signal HSYNC are generated, but may determine the timing and generation period based on the received synchronization packet SYNC_PAC. Image data IDT received from the host200in the normal video mode may not be stored in the memory112and may be provided to the display controller114through the interface111. Even after operation S300operating in the normal video mode, operations S100to S700may be performed again.

The display driving circuit110may determine whether the delay time is less than the reference time TR in operation S400. When the delay time is less than the reference time TR, the display driving circuit110may perform operations S600and S700, and when the delay time is greater than the reference time TR, the display driving circuit110may perform operations S500to S700. At least some of operations S500to S700may be performed in parallel with each other.

The display driving circuit110may increase the section of the corresponding frame at the time when the synchronization packet SYNC_PAC is received in operation S500. When the synchronization packet SYNC_PAC is received later than the expected time (time elapsed by the reference time TR from the generation time of the flag signal TE), it becomes difficult to generate the internal synchronization signals VSYNC and HSYNC based on the synchronization packet SYNC_PAC, so the display driving circuit110may increase a section of a corresponding frame without generating the internal vertical synchronization signal VSYNC to start a new frame. In some example embodiments, the display driving circuit110may increase the section of the frame in a luminance adjustment unit, and the frame section that increases depending on the delay time may be adjusted. For example, as the delay time increases, the increasing frame period may increase. Because the display driving circuit110according to the inventive concepts adjusts the length of the frame section in the luminance adjustment unit, a change in luminance of an image displayed on the display panel120may be reduced or prevented despite an increase in the frame section.

The display driving circuit110may store the image data IDT received from the host200in the memory112in operation S600. When the synchronization packet SYNC_PAC from the host200is received by the display driving circuit110at a time different from the expected time (e.g., the time elapsed by the reference time TR from the generation time of the flag signal TE), by temporarily storing the image data IDT in the memory112even while the video mode is being performed, the display driving circuit110may operate in the memory video mode. The display driving circuit110may temporarily store the image data IDT in the memory112and then provide signals to the display panel120so that an image is displayed on the display panel120based on the image data IDT.

The display driving circuit110may adjust the generation time of the next flag signal TE to be transmitted following the flag signal TE by changing the reference time TR based on the delay time in operation S700. For example, the display driving circuit110may change the reference time TR to coincide with the delay time, and accordingly adjust the generation time of the next flag signal TE. After operation S700is performed, operations S100to S700may be performed again.

The display driving circuit110according to the inventive concepts may operate in the normal video mode or the video memory mode based on the reception time of the synchronization packet SYNC_PAC received from the outside even while operating in the video mode. When the reception time of the synchronization packet SYNC_PAC received from the outside is different from the expected time, the image data IDT may be temporarily stored in the memory112, so that the display driving circuit110may operate similarly to that in the command mode. In the video memory mode, by changing the generation time of the next flag signal TE and the reference time TR, the display driving circuit110may adjust the synchronization packet SYNC_PAC to be received from the host200at an expected time in the next frame. Accordingly, in displaying different images on the display panel120in the video mode, the display driving circuit110enables smooth image conversion.

FIGS.10and11are timing diagrams for describing an operation of a display driving circuit according to example embodiments of the inventive concepts.FIGS.10and11are timing diagrams for explaining an operation of a display driving circuit in a video mode. In the description ofFIG.11, descriptions previously given with reference toFIG.5will be omitted.

Referring toFIGS.1and10, the display driving circuit110may receive the packet PAC from the host200and may transmit the flag signal TE to the host200. The packet PAC may include a command CMD, image data IDT1A, IDT2A, and IDT3A, a vertical synchronization packet VS, and a horizontal synchronization packet HS. First image data IDT1A, second image data IDT2A, and third image data IDT3A may be sequentially received from the host200to the display driving circuit110.

When the delay time coincides with a preset reference time, the display driving circuit110may operate in the normal video mode. Accordingly, the first image data IDT1A received from the host200is not stored in the memory112, but is directly converted to first data DATA1A, and an image based on the first data DATA1A may be displayed on the display panel120.

The display driving circuit110may transmit a first flag signal TE1A to the host200based on a first reference time TRV1, and the host200may receive the first flag signal TE1A and transmit the vertical synchronization packet VS. In some example embodiments, a first reception time TPV1of the vertical synchronization packet VS based on the first flag signal TE1A may be delayed by a first delay time TDV1from a first generation time TTV1of the first flag signal TE1A.

Depending on the preset first reference time TRV1, the display driving circuit110may generate the first flag signal TE1A and then generate the internal vertical synchronization signal V SYNC after the first reference time TRV1has elapsed.

InFIG.10, an example in which a first delay time TDV1is shorter than a preset first reference time TRV1is described. The display driving circuit110may calculate a first delay time TDV1by calculating a difference value between the first reference time TRV1and a difference time TCV. In some example embodiments, the difference time TCV may be a time between the first reception time TPV1of the vertical synchronization packet VS based on the first flag signal TE1A and a generation time TVV1of generating the internal vertical synchronization signal VSYNC.

Because the first reception time TPV1of the vertical synchronization packet VS based on the first flag signal TE1A does not coincide with the generation time TVV1at which the internal vertical synchronization signal VSYNC is generated, the display driving circuit110may operate in the video memory mode, and the second image data IDT2A received after transmitting the first flag signal TE1A may be stored in the memory112and then be converted into second data DATA2A when a predetermined or alternatively, desired time elapses.

The display driving circuit110may newly set a second reference time TRV2based on the first delay time TDV1. For example, the second reference time TRV2may be set to coincide with the first delay time TDV1, and may be calculated by subtracting the difference time TCV from the first reference time TRV1.

The display driving circuit110may adjust a second generation time TTV2of the second flag signal TE2A based on the second reference time TRV2. The display driving circuit110may transmit the second flag signal TE2A to the host200at the adjusted second generation time TTV2, and the host200may transmit the vertical synchronization packet VS by receiving the second flag signal TE2A. In some example embodiments, the second reception time TPV2of the vertical synchronization packet VS based on the second flag signal TE2A may be delayed by a second delay time TDV2from the second generation time TTV2of the second flag signal TE2A.

The second delay time TDV2may coincide with the second reference time TRV2. As the second delay time TDV2coincides with the second reference time TRV2, a second reception time TPV2of the vertical synchronization packet VS received after the display driving circuit110transmits the second flag signal TE2A may coincide with a generation time TVV2at which the internal vertical synchronization signal VSYNC is generated. Accordingly, the display driving circuit110may operate in a normal video mode after transmitting the second flag signal TE2A, and the third image data IDT3A received after transmitting the second flag signal TE2A is not stored in the memory112and may be directly converted into third data DATA3A. However, unlike inFIG.10, when the second delay time TDV2is different from the second reference time TRV2, the display driving circuit110may operate in the video memory mode, and the third image data IDT3A may be temporarily stored in the memory112.

Referring toFIGS.1and11, the display driving circuit110may receive a packet PAC from the host200and may transmit a flag signal TE to the host200. The packet PAC may include a command CMD, image data IDT1B, IDT2B, and IDT3B, a vertical synchronization packet VS, and a horizontal synchronization packet HS. First image data IDT1B, second image data IDT2B, and third image data IDT3B may be sequentially received from the host200to the display driving circuit110.

When the delay time coincides with a preset reference time, the display driving circuit110may operate in a normal video mode. Accordingly, the first image data IDT1B received from the host200is not stored in the memory112, but is directly converted to the first data DATA1B, and an image based on the first data DATA1B may be displayed on the display panel120.

The display driving circuit110may transmit a first flag signal TE1B to the host200based on a first reference time TRV1B, and the host200may receive the first flag signal TE1B and then transmit the vertical synchronization packet VS. In some example embodiments, a first reception time TPV1B of the vertical synchronization packet VS based on the first flag signal TE1B may be delayed by the first delay time TDV1B from a first generation time TTV1B of the first flag signal TE1B.

The display driving circuit110may be set to generate an internal vertical synchronization signal VSYNC, after the first flag signal TE1B is generated and then the first reference time TRV1B has elapsed. However, because the display driving circuit110generates an internal vertical synchronization signal VSYNC using the vertical synchronization packet VS received from the host200in the video mode, when the first delay time TDV1B is longer than the first reference time TRV1B, it may be difficult to generate the internal vertical synchronization signal VSYNC using the vertical synchronization packet VS. Therefore, when the vertical synchronization packet VS is not received even after the first reference time TRV1B elapses after generating the first flag signal TE1B, the display driving circuit110may increase the frame by the extended time ETB. That is, by generating the internal vertical synchronization signal VSYNC after the extended time ETB from a time TVEB at which the first reference time TRV1B has elapsed after generating the first flag signal TE1B, the display driving circuit110may increase a section of a frame in which an image based on the first data DATA1B is displayed on the display panel120and may delay the generation time TVV1B of the internal vertical synchronization signal VSYNC corresponding to the first flag signal TE1B later than the time TVEB when the first reference time TRV1elapses after generating the first flag signal TE1B.

InFIG.11, an example in which the first delay time TDV1B is longer than the preset first reference time TRV1B is described. The display driving circuit110may calculate the first delay time TDV1B by adding the first reference time TRV1B to the difference time TCVB. In some example embodiments, the difference time TCVB may be a time between the first reception time TPV1B of the vertical synchronization packet VS based on the first flag signal TE1B and the time TVEB at which the first reference time TRV1B has elapsed after generating the first flag signal TE1B.

Because the first reception time TPV1B of the vertical synchronization packet VS based on the first flag signal TE1B does not coincide with a generation time TVV1B at which the internal vertical synchronization signal VSYNC is generated, the display driving circuit110may operate in the video memory mode, and the second image data IDT2B received after transmitting the first flag signal TE1B may be stored in the memory112and then be converted into second data DATA2B when a predetermined or alternatively, desired time elapses.

The display driving circuit110may newly set the second reference time TRV2B based on the first delay time TDV1B. For example, the second reference time TRV2B may be set to coincide with the first delay time TDV1B, and may be calculated by adding the difference time TCVB to the first reference time TRV1B.

The display driving circuit110may adjust a second generation time TTV2B of the second flag signal TE2B based on the second reference time TRV2B. The display driving circuit110may transmit the second flag signal TE2B to the host200at the adjusted second generation time TTV2B, and the host200may transmit the vertical synchronization packet VS by receiving the second flag signal TE2B. In some example embodiments, the second reception time TPV2B of the vertical synchronization packet VS based on the second flag signal TE2B may be delayed by a second delay time TDV2B from the second generation time TTV2B of the second flag signal TE2B.

The second delay time TDV2B may coincide with the second reference time TRV2B. As the second delay time TDV2B coincides with the second reference time TRV2B, the second reception time TPV2B of the vertical synchronization packet VS received after the display driving circuit110transmits the second flag signal TE2B may coincide with the generation time TVV2B at which the internal vertical synchronization signal VSYNC is generated. Accordingly, the display driving circuit110may operate in a normal video mode after transmitting the second flag signal TE2B, and the third image data IDT3B received after transmitting the second flag signal TE2B is not stored in the memory112and may be directly converted into third data DATA3B. However, unlike inFIG.11, when the second delay time TDV2B is different from the second reference time TRV2B, the display driving circuit110may operate in the video memory mode, and the third image data IDT3B may be temporarily stored in the memory112.

FIG.12is a diagram illustrating an internal vertical synchronization signal and an internal horizontal synchronization signal generated by a display driving circuit according to example embodiments of the inventive concepts.

Referring toFIG.12, the display panel120may be operated by an internal vertical synchronization signal VSYNC having a vertical period VP and an internal horizontal synchronization signal HSYNC having a horizontal period HP. The vertical period VP may include a first vertical porch period VBP, a vertical active period VACT, and a second vertical porch period VFP, and the first vertical porch period VBP may include a vertical speed action VSA, which is a vertical response period. In example embodiments, the first vertical porch period VBP may be a vertical back porch period, and the second vertical porch period VFP may be a vertical front porch period. The vertical period VP may correspond to one frame period.

The horizontal period HP may include a first horizontal porch period HBP, a horizontal active period HACT, and a second horizontal porch period HFP, and the first horizontal porch period HBP may include a horizontal speed action HSA, which is a horizontal response period. In example embodiments, the first horizontal porch period HBP may be a horizontal back porch period, and the second horizontal porch period HFP may be a horizontal front porch period.

Scanning for a plurality of scan lines (for example, SL1to SLn inFIG.2) included in the display panel120and data input for pixels connected to the scanned scan lines are performed during vertical and horizontal active periods VACT and HACT. That is, the plurality of scan lines SL1to SLn may be sequentially scanned during the vertical active period VACT, and data input to a pixel connected to the scanned scan line may be performed during the horizontal active period HACT.

The operation of increasing the frame period described with reference toFIGS.7,9and11may mean increasing the second vertical porch period VFP included in the vertical period VP of the internal vertical synchronization signal VSYNC.

FIG.13Ais a block diagram illustrating a partial configuration of a display device according to example embodiments of the inventive concepts, and may correspond to the driver115and the display panel120ofFIG.1.FIG.13Bis a timing diagram illustrating an operation of a display driving circuit according to example embodiments of the inventive concepts. InFIG.13A, the OLED panel is described as an example of the display panel120ofFIG.1, and redundant descriptions of the same reference numerals as inFIG.2will be omitted.

Referring toFIGS.13A and13B, a display panel120aincludes a plurality of data lines DL1to DLm, a plurality of scan lines SL1to SLn, a plurality of emission control lines EL1to ELn, and a plurality of pixels PX′ between the lines. Each of the plurality of pixels PX′ may be connected to a corresponding scan line, a data line, and an emission control line.

A light emission control driver115_3may be connected to the plurality of emission control lines EL1to ELn, and may control an emission time of the pixels PX′ by sequentially applying the emission control signals ECS to the pixels PX′. Each of the pixels PX′ may include a corresponding OLED, and may include a transistor that supplies a driving current corresponding to an image signal to the OLED or blocks the driving current supplied to the OLED. The emission control signal ECS provided through each of the plurality of emission control lines EL1to ELn may turn on/off the transistor that provides the driving current to the OLED, thereby controlling the emission time of the OLED.

The luminance value of each of the pixels PX′ may vary depending on the duty ratio of the emission control signal ECS. As the duty ratio (e.g., the length of the on period ONT of the emission control signal ECS compared to the period ECST of the emission control signal ECS) of the emission control signal ECS increases, the emission time of the pixels PX′ may increase, and the luminance of the pixels PX′ may increase. In this way, the light emission control driver115_3may adjust the luminance of the display panel120aby adjusting the pulse width modulation (PWM) of the light emission control signal ECS under the control of the display controller114.

One frame period corresponding to the period of the internal vertical synchronization signal VSYNC may increase or decrease in units of the period ECST of the emission control signal ECS. Accordingly, the operation of increasing the period of the frame described with reference toFIGS.7,9, and11may be performed in units of the period ECST of the emission control signal ECS. In some example embodiments, the unit of the period ECST of the emission control signal ECS may be a luminance adjustment unit of the pixels PX′.

When the internal vertical synchronization signal VSYNC is received later than the expected time, the display driving circuit according to the inventive concepts may increase the corresponding frame (That is, the first vertical period VP1of the internal vertical synchronization signal VSYNC) by the extension time ET and ETB. In some example embodiments, the extension times ET and ETB may be a multiple of the period ECST of the emission control signal ECS, that is, a multiple of the luminance adjustment unit. Accordingly, even if the frame period is increased, the luminance of the display panel120amay be maintained, and as the operation mode is changed, flicker that appears to change the luminance of the display panel120amay be reduced or prevented.

One or more of the elements disclosed above may include or be implemented in one or more processing circuitries such as hardware including logic circuits; a hardware/software combination such as a processor executing software; or a combination thereof. For example, the processing circuitries more specifically may include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a System-on-Chip (SoC), a programmable logic unit, a microprocessor, application-specific integrated circuit (ASIC), etc.