Method and system of generating a layout including a fuse layout pattern

A method of generating a layout usable for fabricating an integrated circuit is disclosed. The method includes generating a block layout layer usable in conjunction with a first conductive layout layer. The first conductive layout layer includes a fuse layout pattern, and the block layout layer includes a block layout pattern overlapping a portion of a fuse line portion of the fuse layout pattern. A second conductive layout layer is generated to replace the first conductive layout layer. The generating the second conductive layout layer includes performing an optical proximity correction (OPC) process on the first conductive layout layer except the portion of the fuse line portion of the fuse layout pattern corresponding to the block layout pattern.

BACKGROUND

The present disclosure relates generally to the field of semiconductor circuits, and more particularly, to integrated circuits having fuses and systems thereof.

In the semiconductor industry, fuse elements have been widely utilized in integrated circuits for a variety of purposes, such as improving manufacturing yield or customizing a generic integrated circuit. For example, fuse elements can be used to replace defective circuits on a chip with redundant circuits on the same chip, and thus manufacturing yields can be significantly increased. Replacing defective circuits is especially useful for improving manufacturing yield of the memory chips since memory chips consist of a lot of identical memory cells and cell groups. In another example, selectively blowing fuses within an integrated circuit can be utilized to customize a generic integrated circuit design to a variety of custom uses.

DETAILED DESCRIPTION

In general, there are many ways to disconnect fuses: disconnection carried out by the action of a laser beam (referred to as a laser fuse); or disconnection carried out by electrical destruction resulting from the production of heat (referred to as an electrical fuse, or E-fuse).

Laser programmable redundancy using laser fuses has been widely used in large-scale memory devices. However, laser repair rates in various structures such as in lower level metal layers are low and the process is complex. For example, an extra mask is needed to form an opening for laser fusing and the process has to be precisely controlled. If a laser fuse is disposed in a lower level layer deep in a chip, the opening will be deeper. The thickness of dielectric of interconnection has to be controlled precisely, which increases the complexity significantly and decreases the repairable rate.

For electrical fusing, a polysilicon strip is formed and patterned. The polysilicon strip is formed by a process forming polysilicon gates. When the complementary metal-oxide-semiconductor (CMOS) technology has advanced from the polysilicon gates to metal gates, an extra process forming the polysilicon strip is added. The extra polysilicon process increases the manufacturing costs. It is also found that a fuse programming ratio, i.e., a final resistance after fusing (Rfusing) to an initial resistance (Rinitial), is about 50 or less. Such fuse programming ratio may result in an undesired failure fusing rate or repair rate.

FIG. 1is a schematic drawing illustrating an exemplary fuse of an integrated circuit and a plurality of dummy patterns adjacent thereto. InFIG. 1, an integrated circuit100includes a fuse100aover a substrate (not shown). The integrated circuit can include a memory circuit, an analog circuit, a digital circuit, a mixed-mode circuit, processor, other integrated circuits, and/or combinations thereof. At least a part of the circuit in the integrated circuit100is coupled with the fuse100a. The substrate is made of semiconductor materials, such as silicon or germanium in crystal, polycrystalline, or an amorphous structure; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP; any other suitable material; or combinations thereof. In one embodiment, the alloy semiconductor substrate may have a gradient SiGe feature in which the Si and Ge composition change from one ratio at one location to another ratio at another location of the gradient SiGe feature. In another embodiment, the alloy SiGe is formed over a silicon substrate. In another embodiment, a SiGe substrate is strained. Furthermore, the semiconductor substrate may be a semiconductor on insulator, such as a silicon on insulator (SOI), or a thin film transistor (TFT). In some examples, the semiconductor substrate may include a doped epi layer or a buried layer. In other examples, the compound semiconductor substrate has a multilayer structure, or the substrate may include a multilayer compound semiconductor structure.

Referring toFIG. 1, the fuse100aincludes a first end101, a second end103, and a central portion105between the first end101and the second end103. The first end101and the second end103of the fuse100aare coupled with at least one integrated circuit. If a current flowing through the fuse100ais high enough, the central portion105of the fuse100amelts, which results in the disconnection of the integrated circuit coupled thereto. In embodiments, the fuse100ahas the same material as a metal gate of a field effect transistor (FET), e.g., copper, tungsten, titanium, tantulum, titanium nitride, tantalum nitride, nickel silicide, cobalt silicide; other proper conductive materials; and combinations thereof, a material as same as a metallic layer of interconnection, e.g., copper, aluminum oxide, aluminum, aluminum nitride, titanium, titanium nitride (TiN), tantalum, tantalum nitride, other suitable material, and/or combinations thereof, and/or other suitable metallic material. In at least one other embodiment, the fuse100ais formed by a process forming a metal gate or a metal interconnection layer, and no extra step of forming an extra polysilicon strip for fusing being necessary.

In one of the embodiments, the integrated circuit100includes a first dummy patterns110aand110badjacent to each side of the central portion105of the fuse100a. The patterns of the fuse100aand first dummy patterns110a,110bcan be transferred from patterns of at least one mask layer by a photolithographic process. In some embodiments, the fuse100ais a single line. If the width of the central portion105of the fuse100ais reduced according to technology scaling without a neighboring dummy pattern, the photolithographic process may distort the pattern of the central portion105of the fuse100a, resulting in unexpected variation in critical dimension of the central portion105of the fuse100a. Dummy patterns of the mask layer corresponding to the first dummy patterns110aand110bare configured to eliminate or reduce the change in critical dimension of the central portion105of the fuse100aresulting from the photolithographic process or logic operation applied through optical proximate correction (OPC). By adding dummy patterns corresponding to the first dummy patterns110aand110bon the mask layer, the lithographic process can better form the pattern of the central portion105of the fuse100aon the substrate at the predetermined dimension.

In some of the embodiments, the first dummy pattern110aand110bhave lines111,113and117,119, respectively. The first dummy pattern110ahas a space115abetween the lines111and113; and the first dummy pattern110bhas a space115bbetween the lines117and119. In some embodiments, the spaces115aand115bare adjacent to the central portion105of the fuse100a. In other embodiments, the spaces115aand115bare adjacent to the center (not labeled) of the central portion105. If a current flow melts the fuse100aand the melted fuse material migrates to the lines111and/or113, the space115ais capable of isolating the line111from the line113, keeping the path of the current flow open. The integrated circuit coupled with the fuse100acan thus be programmed and/or operate. It is noted that the number and location of the spaces115aand115bshown inFIG. 1are mere examples. One of skill in the art is able to change the number and/or modify the location to achieve a desired fuse element.

Referring toFIG. 1, in one of the embodiments, the integrated circuit100includes at least one second dummy pattern such as second dummy patterns120aand120b. The second dummy patterns120aand120bare disposed adjacent to the first dummy patterns110aand110b, respectively. As noted, the photolithographic process transferring the pattern of the fuse100afrom the mask layer to the substrate may distort the central portion105of the fuse100a. Dummy patterns on the mask layer corresponding to the second dummy patterns120aand120breduce the distortion as well as ensure local pattern density.

In at least one of the embodiments, the second dummy patterns120aand120bhave lines121,123and127,129, respectively. The second dummy pattern120ahas a space125abetween the lines121and123; and the second dummy pattern120bhas a space125bbetween the lines127and129. The spaces125aand125bare adjacent to the spaces115aand115bof the first dummy patterns110aand110b, respectively. If a current flow melts the fuse100aand the melted fuse material migrates to the lines111and/or113and further to the lines121and/or123, the space125ais capable of isolating the line121from the line123, maintaining an open current flow path. The integrated circuit coupled with the fuse100acan thus be programmed and operate. It is noted that the number and location of the spaces125aand125bshown inFIG. 1are mere examples. One of skill in the art is able to change the number and/or modify the location to achieve a desired fuse element.

Referring again toFIG. 1, in yet another embodiment, the integrated circuit100includes at least one third dummy pattern such as third dummy patterns130aand130b. The third dummy patterns130aand130breduce the distortion to the central portion105of the fuse100aresulting from the photolithographic process as well as ensure local pattern density. In embodiments, the third dummy patterns130aand130binclude a plurality of lines131-133and136-138, respectively. The dummy patterns130aand130bcontinuously extend over the substrate. In other embodiments, the dummy patterns130aand130binclude at least one space described above in conjunction with dummy patterns110aand110b.

It is noted that the positions of the spaces115a,115b,125a, and125bcan be modified as long as the spaces115a,115b,125a, and125bcan desirably break the current flow through the migrating fuse material. It is also noted that the patterns and numbers of the dummy patterns110a-110b,120a-120b,130a-130b, and lines111,113,117,119,121,123,127,129,131-133, and136-138are mere examples. The scope of the invention is not limited thereto. One of skill in the art is able to modify them to achieve a desired fuse pattern.

Referring again toFIG. 1, in one embodiment, the fuse100aincludes portions107and109between the first end101and the central portion105and between the second103and the central portion105, respectively. As noted, the photolithographic process may distort the pattern of the central portion105. The photolithographic process may also distort the pattern of joints between the first end101and the central portion105and between the second end103and the central portion105. A pattern on the mask layer corresponding to the portion107is configured to eliminate or reduce the distortion at the joint of the first end101and the central portion105. In some embodiments, the pattern on the mask layer corresponding to the portion107has a reduced width from the first end101to the central portion105. The pattern on the mask layer corresponding to the portion107can be referred to as an optical proximate correction (OPC) technique. It is noted that the pattern of the portion107shown inFIG. 1is merely illustrative. By transferring the pattern on the mask layer to the substrate, the final pattern of the portion107may be shown as the reference numeral207shown inFIG. 2.FIG. 2is a drawing illustrating a simulation pattern corresponding to the fuse pattern ofFIG. 1. Items ofFIG. 2that are the same or similar items inFIG. 1are indicated by the corresponding reference numerals, which are reference numerals ofFIG. 1increased by 100. As shown, the final pattern of the portion207can have a width “w” gradually reducing from the first end (not shown inFIG. 2) to the central portion205.

FIG. 3is a drawing illustrating another fuse of an integrated circuit and exemplary dummy patterns adjacent thereto. Items ofFIG. 3that are the same or similar items inFIG. 1are indicated by corresponding reference numerals, which are reference numerals ofFIG. 1increased by 200. In one of the embodiments, the first dummy pattern310aincludes “L” shape dummy patterns311and313. Each of the L-shape dummy patterns, e.g., the dummy pattern311, has a corner, e.g., corner311a, facing the portion307between the first end301and the central portion305. Dummy patterns on the mask layer corresponding to the L-shape dummy pattern307eliminate or reduce distortions to the central portion305and/or the portion307of the fuse300aresulting from the photolithographic process. It is noted that the shape of the dummy patterns310aand310bis merely an example. One of skill in the art is able to modify the shape of the dummy pattern to achieve a desired fuse pattern.

FIGS. 4A-4Hare schematic drawings showing various exemplary patterns of potions between fuse ends and central portions usable in the embodiments depicted inFIGS. 1 and 3. Items ofFIGS. 4A-4Hthat are the same or similar items inFIG. 1are indicated by the corresponding reference numerals, which are reference numerals ofFIG. 1increased by 300 plus an alphabet changing from “a” to “h” for each drawing, respectively. It is noted that the patterns of the portions407a-407hshown inFIGS. 4A-4Hare mere examples and may be similar to those on mask layers. The final patterns of the portions407a-407hon substrates may be similar to the portion207shown inFIG. 2and/or changed according to the patterns on the mask layer. It is noted that the patterns of the portions407a-407hbetween the fuse ends and the central portions are merely examples. One of skill in the art can modify the patterns to achieve a desired final pattern.

FIGS. 5A-5Fare schematic drawings showing various exemplary patterns of the central portion of the fuse usable in conjunction with the embodiments depicted inFIGS. 1 and 3. Items ofFIGS. 5A-5Fthat are the same or similar items inFIG. 1are indicated by corresponding reference numerals, which are reference numerals ofFIG. 1increased by 400 plus an alphabet changing from “a” to “f” for each drawing, respectively. In embodiments depicted inFIGS. 5A-5E, the central portions505a-505ehave portions545a-545ebetween portions540a-540e, respectively. The widths of the portions545a-545eare smaller than the width of one of the portions540a-540e, respectively. The portions545a-545eare configured to melt if a high current flows through the central portions505a-505e. InFIG. 5F, the central portion505fhas portion545fbetween portions540f, wherein the width of the portion545fis larger than that of each of the portions540f. In one embodiment, the portions540fare configured to melt if a high current flows through the central portions505f. It is noted that the patterns of the central portions505a-505fare merely examples. One of skill in the art can modify the patterns to achieve a desired central portion of the fuse.

FIG. 6is a drawing showing a relationship between resistance (Ω) and cumulative distribution (%) of exemplary fuses. As shown, a ratio of a final resistance (Rfusing) after fusing to an initial resistance (Rinitial) can be about 10,000 or more. That is, the fuses described above in conjunction withFIGS. 1, 3, 4A-4H, and 5A-5Fcan be desirably blown if a high current flows through the fuse, and thus the integrated circuit coupled with the fuse is protected.

FIG. 7is a schematic drawing showing a portion of an integrated circuit. InFIG. 7, in accordance with one of the embodiments, an integrated circuit700includes a fuse700a, a metal-oxide-semiconductor field effect transistor (MOSFET)710, and a sensing circuit720. The fuse700ais represented by a resistor symbol in the schematic diagram. The fuse700acan be similar to the fuse100aor300adescribed above in conjunction withFIG. 1orFIG. 3, respectively. A first terminal of the fuse700ais coupled with a supply voltage, e.g., Vcc, and a second terminal is coupled with a drain terminal of the MOSFET710, e.g., n-channel MOSFET. A source terminal of the MOSFET710is coupled with Vssor ground. In one of the embodiments, the MOSFET710is a driver device operable to supply a programming current and voltage drop across the fuse700a. A control signal (not shown) is supplied to a gate terminal710aof the MOSFET710that is operable to turn the MOSFET710ON or OFF. The sensing circuit720is coupled with the drain terminal of the MOSFET710. The sensing circuit720is capable of sensing whether the fuse700ais programmed. As noted, the resistance differential of the fuse700abetween its unprogrammed state and its programmed state is large. In one embodiment, the sensing circuit720senses if the fuse700ais programmed by, for example, sensing a current flowing through the drain terminal of the MOSFET710or a voltage at the drain terminal of the MOSFET700.

Although an n-channel MOSFET has been shown in this example, a p-channel MOSFET or another suitable driver device may be used. In embodiments, the driver device is simple in structure and can be formed by desired processing steps.

In operation, in accordance with one of the embodiments, if the fuse700ais in the unprogrammed state, it exhibits a low resistance. The output voltage level at the drain terminal of the MOSFET710is substantially near the supply voltage level. To program the fuse700a, a control signal (not shown) is supplied to the gate terminal710aof the MOSFET710that can turn on the MOSFET710. A voltage drop of substantially Vcc is applied across the fuse700aand a current flows through the fuse700a. The central portion of the fuse700ais forced to bear the current flow and thus melts or is blown. A discontinuity is formed in the fuse700a. The fuse700abecomes an open circuit or its resistance becomes very high. In one embodiment, the sensing circuit720detects a voltage level approximating Vcc if the fuse700ais in an unprogrammed state, and a floating or very low voltage level if the fuse700ais in a programmed state.

In embodiments, the fuse700ahas a desired programming condition. For example, a desired programming potential and/or current can desirably convert the fuse700afrom an unprogrammed state with a low resistance to a programmed state with a high resistance.

FIG. 8is schematic drawing showing a system including an exemplary integrated circuit. InFIG. 8, a system800can include a processor810coupled with the integrated circuit700. The processor810is capable of accessing the integrated circuit700. In embodiments, the processor810can be a processing unit, central processing unit, digital signal processor, or other processor.

In some embodiments, the processor810and the integrated circuit700are formed within a system that is physically and electrically coupled with a printed wiring board or printed circuit board (PCB) to form an electronic assembly. In another embodiment, the electronic assembly is part of an electronic system such as computers, wireless communication devices, computer-related peripherals, entertainment devices, or the like.

In some embodiments, the system800including the integrated circuit700provides an entire system in one IC, so-called system on a chip (SOC) or system on integrated circuit (SOIC) devices. These SOC devices provide, for example, all of the circuitry needed to implement a cell phone, personal data assistant (PDA), digital VCR, digital camcorder, digital camera, MP3 player, or the like in a single integrated circuit.

FIG. 9is a flow chart of a method900of generating a layout in accordance with some embodiments.FIGS. 10A-10Care schematic drawings of a portion of a layout1000corresponding to region A inFIG. 1at various processing stage in accordance with some embodiments. Method900will be illustrated in conjunction with the examples depicted inFIGS. 10A-10C. It is understood that additional operations may be performed before, during, and/or after the method900depicted inFIG. 9, and that some other processes may only be briefly described herein.

As depicted inFIGS. 9 and 10A, the method900begins with operation910, where a layout1000usable for fabricating an integrated circuit having a fuse component as described in conjunction withFIGS. 1-8is generated.

The layout1000includes a first conductive layout layer including a fuse layout pattern1010and a plurality of dummy layout patterns1040. Fuse layout pattern1010includes a first end portion1012, a second end portion1014, a fuse line portion1020between the first end portion1012and the second end portion1014, a first step-wise portion1016connecting the first end portion1012and the fuse line portion1020, and a second step-wise portion1018connecting the second end portion1014and the fuse line portion1020. In some embodiments, first end portion1012corresponds to first end101inFIG. 1; second end portion1014corresponds to second end103; fuse line portion1020corresponds to central portion105; first step-wise portion1016corresponds to portion107; and second step-wise portion1018corresponds to portion109.

Fuse line portion1020includes a first line portion1022, a second line portion1024, and an intermediate portion1026between the first line portion1022and the second line portion1024. In some embodiments, the first line portion1022has a width the same as that of the second line portion1024, and the intermediate portion1026has a width less than that of the first and second line portion1022and1024. In some embodiments, intermediate portion1026has a shape corresponding to the shapes depicted inFIGS. 5A-5F.

The plurality of dummy layout patterns1040includes a first dummy layout pattern1042and a second dummy layout pattern1044adjacent to a first side of the central portion1020, and a third dummy layout pattern1046and a fourth dummy layout pattern1048adjacent to a second side of the central portion1040. Also, first dummy layout pattern1042and third dummy layout pattern extend alongside the first line portion1022, and second dummy layout pattern1044and fourth dummy layout pattern1048extend alongside the second line portion1044. First dummy layout pattern1042and second dummy layout pattern1044are separated by a gap; and third dummy layout pattern1046and fourth dummy layout pattern1048are separated by a gap. As such, the first, second, third, and fourth dummy layout patterns1042-1048are free from extending alongside the intermediate portion1026.

In some embodiments, first dummy layout pattern1042corresponds to dummy pattern111or311; second dummy layout pattern1044corresponds to dummy pattern113or313; third dummy layout pattern1046corresponds to dummy pattern117or317; and fourth dummy layout pattern1048corresponds to dummy pattern119or319. Detail description thereof is thus omitted.

As depicted inFIGS. 9 and 10B, the method900proceeds to operation920, where a block layout layer usable in conjunction with conductive layout layer1010is generated. The block layout layer includes one or more block layout patterns, such as block layout pattern1052. Block layout pattern1052overlaps a portion1026aof intermediate portion1026without overlapping portions1026bof intermediate portion1026. In some embodiments, block layout pattern1052overlaps the entirety of intermediate portion1026. Block layout pattern1052is within a region of the layout1000that abuts, without overlaps, the first, second, third, and fourth dummy layout patterns1042-1048. Therefore, the first, second, third, and fourth dummy layout patterns1042-1048are free from overlapping the block layout pattern1052.

In some embodiments, the one or more layout patterns define blocking regions where a subsequent optical proximity correction (OPC) process is omitted. In some embodiments, the OPC process is performed by a processor of a computer, such as processor1112(FIG. 11) executing a set of instructions (e.g.,1114a), and the block layout pattern152has a size equal to or greater than a minimum size permissible by the set of instructions for OPC.

As depicted inFIGS. 9 and 10C, the method900proceeds to operation930, where the subsequent OPC process is performed on the first conductive layout layer except the one or more regions corresponding to the one or more block layout patterns, and a second conductive layout layer is generated accordingly. In some embodiments, the OPC process is performed to adjust a line width of the first, second, third, or fourth dummy layout patterns1042-1048. In some embodiments, the OPC process is performed to adjust the shape or dimension of fuse layout pattern1010and the plurality of dummy layout patterns1040except the blocked regions based on the block layout layer. The second conductive layout layer includes modified layout patterns including portions1012′,1014′,1016′,1018′,1022′,1024′,1042′,1044′,1046′, and1048′ variously correspond to portions1012,1014,1016,1018,1022,1024,1042,1044,1046, and1048. Moreover, portions1022′,1024′ also includes OPC-processed portions corresponding to portions1026b. However, because portion1026ais with the block region defined by block layout pattern1052, the second conductive layout layer includes the portion1026aas provided in the first conductive layout layer.

As depicted inFIG. 9, the method900proceeds to operation940, where the second conductive layout layer replaces the first conductive layout layer in layout1000.

FIG. 11is a functional block diagram of an integrated circuit designing system1100in accordance with one or more embodiments. Integrated circuit designing system1100includes a first computer system1110, a second computer system1120, a networked storage device1130, and a network1140connecting the first computer system1110, the second computer system1120, and the networked storage device1130. In some embodiments, one or more of the second computer system1120, the storage device1130, and the network1140are omitted.

The first computer system1110includes a hardware processor1112communicatively coupled with a non-transitory, computer readable storage medium1114encoded with, i.e., storing, a set of instructions1114a, a layout1114b, or any intermediate data1114cfor executing the set of instructions1114a. The processing unit1112is electrically and communicatively coupled with the computer readable storage medium1114. The processing unit1112is configured to execute the set of instructions1114aencoded in the computer readable storage medium1114in order to cause the computer1110to be usable as a layout checking tool for performing a method as described in conjunction withFIG. 9.

In some embodiments, the set of instructions1114a, the layout1114b, or the intermediate data1114care stored in a non-transitory storage medium other than storage medium1114. In some embodiments, some or all of the set of instructions1114a, the layout1114b, or the intermediate data1114care stored in a non-transitory storage medium in networked storage device1130or second computer system1120. In such case, some or all of the set of instructions1114a, the layout1114b, or the intermediate data1114cstored outside computer1110is accessible by the processing unit1112through the network1140.

In some embodiments, the processor1112is a central processing unit (CPU), a multi-processor, a distributed processing system, an application specific integrated circuit (ASIC), and/or a suitable processing unit.

The computer system1110includes, in at least some embodiments, an input/output interface1116and a display unit1117. The input/output interface1116is coupled to the processor1112and allows the circuit designer to manipulate the first computer system1110. In at least some embodiments, the display unit1117displays the status of executing the set of instructions1114aand, in at least some embodiments, provides a Graphical User Interface (GUI). In at least some embodiments, the display unit1117displays the status of executing the set of instructions1114ain a real time manner. In at least some embodiments, the input/output interface1116and the display1117allow an operator to operate the computer system1110in an interactive manner.

In at least some embodiments, the computer system1100also includes a network interface1118coupled to the processor1112. The network interface1118allows the computer system1110to communicate with the network1140, to which one or more other computer systems are connected. The network interface includes wireless network interfaces such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or wired network interface such as ETHERNET, USB, or IEEE-1394.

In accordance with one embodiment, a method of generating a layout usable for fabricating an integrated circuit is disclosed. The method includes generating a block layout layer usable in conjunction with a first conductive layout layer. The first conductive layout layer includes a fuse layout pattern, and the block layout layer includes a block layout pattern overlapping a portion of a fuse line portion of the fuse layout pattern. A second conductive layout layer is generated to replace the first conductive layout layer. The generating the second conductive layout layer includes performing an optical proximity correction (OPC) process on the first conductive layout layer except the portion of the fuse line portion of the fuse layout pattern corresponding to the block layout pattern.

In accordance with another embodiment, a method of generating a layout usable for fabricating an integrated circuit is disclosed. The method includes generating a block layout layer usable in conjunction with a first conductive layout layer. The first conductive layout layer includes a fuse layout pattern, a first dummy layout pattern, a second dummy layout pattern, a third dummy layout pattern, and a fourth dummy layout pattern. The fuse layout pattern includes a first end portion, a second end portion, and a central portion between the first end portion and the second end portion. The first dummy layout pattern is adjacent to a first side of the central portion of the fuse layout pattern. The second dummy layout pattern is adjacent to the first side of the central portion of the fuse layout pattern, and the first dummy layout pattern and the second dummy layout pattern are separated by a first gap. The third dummy layout pattern is adjacent to a second side of the central portion of the fuse layout pattern. The fourth dummy layout pattern is adjacent to the second side of the central portion of the fuse layout pattern, and the third dummy layout pattern and the fourth dummy layout pattern are separated by a second gap. The block layout layer includes one or more block layout patterns, and one of the one or more block layout patterns overlaps a portion of the central portion of the fuse layout pattern and within a region of the layout. The region abuts, without overlaps, the first, second, third, and fourth dummy layout patterns. The method also includes generating a second conductive layout layer to replace the first conductive layout layer. The generating the second conductive layout layer includes performing an optical proximity correction (OPC) process on the first conductive layout layer except one or more regions corresponding to the one or more block layout patterns.

In accordance with another embodiment, an integrated circuit designing system includes a non-transitory storage medium encoded with a set of instructions and a hardware processor communicatively coupled with the non-transitory storage medium. The processor is configured to execute the set of instruction to generate a block layout layer usable in conjunction with a first conductive layout layer and to perform an optical proximity correction (OPC) process. The first conductive layout layer includes a fuse layout pattern, and the block layout layer includes a block layout pattern overlapping a portion of a fuse line portion of the fuse layout pattern. The OPC process is performed on the first conductive layout layer except the portion of the fuse line portion of the fuse layout pattern corresponding to the block layout pattern, thereby generating a second conductive layout layer to replace the first conductive layout layer.