Termination structure of DMOS device and method of forming the same

Embodiments of the invention provide a termination structure of DMOS device and a method of forming the same. In forming the termination structure, a silicon substrate with an epitaxial layer formed thereon is provided. A body region defined by doping the epitaxial layer is then selectively etched to form a plurality of DMOS trenches therein. Thereafter, a gate oxide layer is formed over exposed surfaces in the body region and a termination oxide layer is formed to encircle the body region. Afterward, a polysilicon layer is deposited over all the exposed surfaces, and then selectively etched to form a plurality of poly gates in the DMOS trenches and a polysilicon plate having an extending portion toward the body region over the termination oxide layer. By using the termination polysilicon layer as an implantation mask, sources are formed in the body region. Afterward, an isolation layer and a source metal contact layer are deposited over the structure, in which the isolation layer is utilized to protect the polysilicon gates, and also the source metal contact layer is utilized to ground both the body region and the polysilicon plate.

This application claims priority from R.O.C. patent application No. 092105250, filed Mar. 11, 2003, the entire disclosure of which is incorporated herein by reference.

BACKGROUND OF THE INVENTION

This invention relates to a termination structure, and more particularly relates to a termination structure for a DMOS device as well as a method for forming the same.

A diffused metal-oxide-semiconductor (DMOS) transistor is an important power transistor device and is widely used in power suppliers and power control devices for high-voltage systems. Among many published power transistor structures, a trenched power transistor is a noble design and some reports indicate that it has better performance than a planar power transistor in efficiency and pattern density.

A typical fabrication method for forming a trenched DMOS is shown inFIG. 1AthroughFIG. 1F. InFIG. 1A, an N-type epi layer10is formed on an N+-type silicon substrate1, and then a thermal oxidation process is performed to form a termination oxide layer20over a location of a termination structure. The termination oxide layer20is utilized as a mask for a P-type doping to form a P-type active area12. InFIG. 1B, the P-type active area12is etched to form a plurality of DMOS trenches13extending through the P-type body12down to the N-type epi layer10. Afterward, an oxidation process is performed to form a gate oxide layer21over the active area12and also to grow the termination oxide layer20to become a field oxide layer22. InFIG. 1C, a polysilicon layer is formed by a chemical vapor deposition (CVD) process and then etched to remove polysilicon on the surface of the epi layer10around the DMOS trenches13. A polysilicon gate30then is formed in each DMOS trench. InFIG. 1D, a lithographic process is performed to define locations of source regions40. Using a photoresist layer40PR on the source regions40, N-type dopants are implanted into the active area12to form N+-type source regions40surrounding the DMOS trenches13. InFIG. 1E, an isolation layer50is formed by a CVD process. An etch is performed to form a plurality of body contact windows51over the N+-type source regions40. Moreover, P-type dopants are implanted into the body contact windows to form doped regions41surrounding the source regions. InFIG. 1F, a source metal contact layer60is deposited over the isolation layer50. The source metal contact layer60connects with the active area12through the body contact windows51. The source metal contact layer60has contact windows to expose the isolation layer50. In addition, a drain metal contact layer61covers the backside of the N-type silicon substrate1. With a voltage applied on the polysilicon gate, it can show whether the source regions of the DMOS trenches are conductive to the drain regions.

A trenched power transistor performs better than a planar power transistor. However, the structure of a trenched power transistor is more complex than that of a planar power transistor. Therefore, reducing the number of lithographic process steps is one way of improving the manufacturing process.

For the abovementioned lithographic process, the process improvement focuses on canceling the lithographic steps for the source region implantation and polysilicon layer deposition. As shown inFIG. 2, N-type dopants are directly implanted without a mask (not shown) which is used for forming a source region photoresist40PR and defining the scope of implantation of a source region40as a source region mask. The silicon substrate1is masked by the field oxide layer22and the polysilicon gates30, so that a small gap is formed having the horizontal width w (marked as A) between the N-type doped area40aand the N-type epi layer10on the P-type active area12. Punch-through occurs easily in the location A on the P-type active area12and leads to breakdown of the transistor.

To avoid the effects of electrostatic discharge on power transistors, an ESD (Electrostatic Discharge) protective circuit14is usually utilized in the IC design. A typical ESD14is shown inFIG. 3. It is noted that, to form a polysilicon layer32, a mask is needed to define the location of the ESD polysilicon layer32. As a consequence, the lithographic process related to the polysilicon layer deposition cannot be neglected usually.

In addition, because the power transistor device is usually utilized under a higher electric voltage, a termination structure should be added thereto for avoiding early breakdown and current leakage. In the art, various structures such as a local oxidation of silicon (LOCOS), a field plate, a guard ring or the like can be utilized as the termination structure. In particular, the LOCOS structure is well known for its simple fabrication process.

In the typical trenched DMOS device as shown inFIG. 1B, the field oxide layer22is utilized as the main body of the termination structure. However, due to the process characteristics of the field oxide layer22, the electric field crowding around the active area12is improved with limitation. The better result can be reached by combining some other termination structures such as a field plate, for example.

Referring toFIG. 4A, a typical field plate16is shown. The field plate is a conductive layer over the oxide layer, and is typically made of polysilicon or metal. When the field plate16is applied with a negative bias, positive charges are formed under the field plate16thereof so as to extend the boundary of the depletion region of P-N junction from15to15′. On the other hand, when the field plate16is biased positively, to the boundary will move from15to15″. InFIG. 4B, a planar P-N junction is shown, connected with an electric plate16and having a boundary15of the depletion region of the planar P-N junction. The electric field crowding effect near the junction surface161can be improved by applying a negative bias on the field plate16.

BRIEF SUMMARY OF THE INVENTION

The present invention discloses a termination structure to not only meet the requirement of the reduction of the source region mask, but also provide the advantages of the abovementioned field oxide and electric plate.

Embodiments of the present invention provide a DMOS device with a termination structure and a method for forming the same. First, an epi layer doped with first conductive dopants is formed on an N+ silicon substrate highly doped with the first conductive dopants. Then, a termination oxide layer is formed over the surface of the epi layer to be a mask of an active area of the DMOS device by lithographic and etching technologies. With the mask, second conductive dopants are implanted to define the active area. Then, a plurality of DMOS trenches extending from the bottom of the active area is formed in the active area by an etching process. Thereafter, a thermal oxidation process is performed to form a gate oxide layer over the active area. Meanwhile, the termination oxide layer grows to become a field oxide layer.

A polysilicon layer is deposited by a CVD process. A plurality of poly gates and a polysilicon layer of a termination structure, located on the field oxide layer and extending to the top of adjacent DMOS trenches. With the polysilicon layer of the termination structure and the field oxide layer as a mask, the first conductive dopants are implanted directly to form first conductive doped regions. An isolation layer is formed. Lithographic and anisotropic etching processes are performed to form a plurality of contact windows of the active area over the first conductive doped regions and a first contact window on the polysilicon plate. Thereafter, using the isolation layer as a mask, second conductive dopants are implanted to form a plurality of first conductive source regions and a plurality of the second conductive highly-doped contact regions surrounding the source regions. Finally, a metal layer is deposited. A portion of the metal layer over the termination area is removed to form a metal contact layer for the source regions with lithographic and etching processes. The metal contact layer for the source regions is connected with the active area through the contact windows of the active area and connected with the polysilicon layer of the termination structure through the first contact window.

The polysilicon layer of the termination structure and the polysilicon gates are formed in the same etching process. The polysilicon layer of the termination structure can be used as a mask for the implantation of the first conductive dopants. Therefore, comparing to the prior art, the lithographic process for defining the source regions of the DMOS devices can then be eliminated in the present embodiment.

In addition, as the DMOS device made by the present embodiment is operated, capacitance is created between the polysilicon layer of the termination structure and the active area under that layer. It results in the extension of the depletion region of the P-N junction at the surface of the active area. It not only increases the horizontal distance between the first conductive source region of the DMOS device and the surface of the P-N junction, but also releases the electric field crowding beneath the field oxide layer to prevent from early-happening electric breakdown.

DETAILED DESCRIPTION OF THE INVENTION

Embodiments of the invention disclosed herein are directed to a termination structure of DMOS device and a method for forming the same. In the following description, numerous details are set forth in order to provide a clear understanding of the present invention. It will be appreciated by one skilled in the art that variations of these specific details are possible while still achieving the results of the present invention. In some cases, well-known components are not described in detail in order not to unnecessarily obscure the present invention.

The fabrication processes of a trenched DMOS and a termination structure thereof in accordance with the present embodiment are shown in a schematic sequence ofFIG. 5AthroughFIG. 5F.

As shown inFIG. 5A, an N-type epi layer10is formed on an N+-type silicon substrate1. Afterward, an oxide layer is formed over the top surface of the N-type epi layer10. A lithographic process is used to define an active area12and a termination area11surrounding the active area12. An etching step is performed to remove the oxide layer over the top surface of the active area12. Then, a termination oxide layer20is formed over the termination area11. Thereafter, a thermal oxidation process is performed to form a sacrificial oxide layer over all surfaces. The termination oxide layer20is used as a mask for an implantation process of P+-type dopants to form the active area12.

Afterward, as shown inFIG. 5B, a plurality of DMOS trenches13is formed by etching the active area12. The bottom of a plurality of the DMOS trenches13is below the substrate of the active area12. Then, the sacrificial oxide layer is removed by a blanket etching. A high temperature oxidation process is performed to form a gate oxide layer21over all surfaces of the active area12, while a field oxide layer22is grown from the termination oxide layer20.

InFIG. 5C, a polysilicon layer is deposited, and lithographic and etching steps are used to remove a part of the polysilicon layer over the surface of the epi layer10and the field oxide layer22to form polysilicon gates30in the DMOS trenches13and a termination structure polysilicon layer31with an extending portion over the field oxide layer22extending to the active area at a certain distance. Then, by using the termination structure polysilicon layer31and the field oxide layer22as a mask, an implantation process is performed to form a N+-type region40bbetween adjacent DMOS trenches.

InFIG. 5D, an isolation layer50is formed. Then, by using lithographic and two-step anisotropic etching processes where the first-step etching is to remove the isolation layer50and the gate oxide layer21, a plurality of contact windows51of the active area are formed over the N+-type region40band a first contact window52over the termination structure polysilicon layer31. The second-step etching is shown inFIG. 5E. By using the isolation layer50as a mask, the exposed portions of the N+-type region40band the termination structure polysilicon layer31are etched and then removed. Then, an implantation process of P+-type dopants is performed directly to have sidewalls of the contact windows51of the active area adjoining to the sources40and also have the bottom adjoining to the P+-type regions41.

Finally, a metal layer is deposited. Then, by using lithographic and etching processes to remove parts of the metal layer over the termination region11, a metal contact layer60for the source regions is formed, which connects the N+-type source regions40and P+-type regions41through the contact windows51of the active area and also connects the first contact window52through the polysilicon layer31of the termination structure.

Subsequently, a chemical mechanical polishing (CMP) process is carried out to remove excess deposited layer on the backside of the silicon substrate1, so that the backside is exposed. Then, a metal contact layer61of a drain region is deposited on the backside of the silicon substrate1.

In some preferred embodiments, the isolation layer50may be silicate glass, and the metal contact layer60of the source regions may include a stack of Ti, TiN, and AlSiCu layers from down to up in sequence.

FIG. 1D,FIG. 2, andFIG. 5Care compared. As shown inFIG. 1D, a source region40is formed by a lithographic process. The distance between the source region40and the boundary of the active area12should remain a certain horizontal distance so as to avoid the punch through effect on the active area, happening between the source regions40and the N-type epi layer10. However, if the source-region mask of the process in accord withFIG. 1Dis eliminated as indicated by the location A shown inFIG. 2, the horizontal width w of the P-type active area12between the N+-type region40aand the N-type epi layer10is too narrow, so that the P-type active area is easily punched through and it leads to electrical breakdown. Referring toFIG. 5C, by changing the pattern on the mask used for defining the polysilicon layer in accord with the present embodiment, a polysilicon layer31of the termination structure is formed during the etching process to form the polysilicon gates30. The polysilicon layer31of the termination structure covers the termination oxide layer20and extends to the field oxide region12for a certain distance. Then, use the polysilicon layer31of the termination structure and the field oxide layer22as a mask to process the N-type implantation. Therefore, the horizontal width w of the P-type active area12between the N+-type region40aand the N-type epi layer10increases to w′ (w′>w). Thus, the problems of punch through effect and electrical breakdown shown inFIG. 2can be avoided.

For a general power IC design, an ESD circuit14is included for protection. Therefore, the abovementioned mask for forming the polysilicon layer is necessary. Thus, the present embodiment is configured to change the pattern of the abovementioned mask to form the polysilicon layer31of the termination structure, so the source region mask used inFIG. 1Dis saved. One lithographic process is omitted.

In addition, a sandwiched MOS structure of the termination structure polysilicon layer31, the field oxide layer22, and the epi layer10can function as an electric field plate. Referring toFIG. 6, a driving voltage applied to the termination structure of the present embodiment is illustrated. The metal contact layer60of source region is connected to the ground so that N+-type source region40and the termination structure polysilicon layer31are also connected to the ground. Meanwhile, the metal contact layer61of the drain region on the backside of the silicon substrate1is applied with a forward bias. Thus, the similar capacitance effect occurs between the termination structure polysilicon layer31and the underlying region of the epi layer10. That is, negative charges gather in the bottom surface of the polysilicon layer31, and positive charges gather in the corresponding top surface of the epi layer10. It results in the15-to-15′ extension of the depletion region of the P-N junction between the field active area12and the termination region11. Thus, the horizontal distance between the N+-type region40band the boundary of the active area12increases, so as to avoid electric breakdown.

FIG. 7shows a computer simulation result of equivalent electric field lines in the termination structure in accordance with the present embodiment. By adding the polysilicon layer31over the field oxide layer22, the dense electric gradient region extends to the outside of the active region12and the equivalent electric field lines near cylinder-like P-N junction of the edge of the active area12become flat. Therefore, the density of electric field decreases to avoid early-happening electric breakdown.

Another embodiment is shown inFIG. 8, which is based on the structure illustrated inFIG. 5D. InFIG. 5Dshowing some step, the anisotropic etching process is used to remove portions of the isolation layer50and the gate oxide layer21. Thus, the contact windows51of the active area and the first contact window52are formed. The termination structure polysilicon layer31and the N+-type region40bare used as an etching stop layer. Afterward, an implantation process of P+-type dopants is performed. The amount of P+-type ions implanted is large enough to change the electric property of the exposed N+-type region40bto be P-type. Thus, the P+-type region41and the adjacent N+-type source region40are formed. The bottom of the P+-type region41underlies that of N+-type source region40.

The above-described arrangements of apparatus and methods are merely illustrative of applications of the principles of this invention and many other embodiments and modifications may be made without departing from the spirit and scope of the invention as defined in the claims. For example, the shapes and sizes of the components that form the camera supporting device may be changed. The scope of the invention should, therefore, be determined not with reference to the above description, but instead should be determined with reference to the appended claims along with their full scope of equivalents.