Domain crossing circuit of a semiconductor memory apparatus

The domain crossing circuit of a semiconductor memory apparatus for improving a timing margin includes a sampler that provides a sampling internal signal generated by delaying an internal input signal by a predetermined time in response to a clock and an edge information signal that defines an output timing of the sampling internal signal and an output stage that allows the sampling internal signal to be synchronized with the clock in response to the edge information signal to be output as a final output signal.

CROSS-REFERENCES TO RELATED PATENT APPLICATION

The present application claims priority under 35 U.S.C 119(a) to Korean Application No. 10-2008-0126447, filed on Dec. 12, 2008, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety as set forth in full.

BACKGROUND

Embodiments described herein relate generally to a semiconductor memory apparatus, and more particularly, to a domain crossing circuit of a semiconductor memory apparatus.

A synchronous semiconductor memory apparatus is a semiconductor apparatus that performs an operation in synchronization with a clock. At this time, command signals and data must be synchronized with an external clock in order to properly operate in internal circuits, and internal signals synchronized with internal clock signals must be synchronized with the external clock. This is referred to as a region switchover between an internal clock region and an external clock region, and is commonly referred to as a domain crossing.

For example, a domain crossing circuit allows the command signals or data, etc. to be synchronized with the internal clock generated using a delay-locked loop (DLL) in order to provide synchronized signal to the clock required in the internal circuit unit. However, according to physical positions of control pins (RAS, CAS, WE, CS, etc.) used with command signals, a difference may exist between the time when command signals are applied from an external system and the time when signals are actually received by the control pins. Therefore, when the signals applied to the control pins, etc. are delayed by a predetermined time to be synchronized with the internal clock, in consideration of such physical positions, it is difficult to synchronize nonsynchronization signals in a high-frequency clock accurately. As such, a timing margin of the signals may be insufficient.

SUMMARY

A domain crossing circuit of a semiconductor memory apparatus for improving a timing margin is disclosed herein.

In one aspect, a domain crossing circuit includes a sampler that provides a sampling internal signal generated by delaying an internal input signal by a predetermined time in response to a clock and an edge information signal that defines an output timing of the sampling internal signal; and an output stage that allows the sampling internal signal to be synchronized with the clock in response to the edge information signal to be output as a final output signal.

In another aspect, a domain crossing circuit includes a sampler that provides a sampling internal signal generated by allowing an internal input signal that is a nonsynchronous signal to be synchronized with a clock and an edge information signal that becomes an output reference of the sampling internal signal; and a final output signal synchronized with the clock by delaying the sampling internal signal at a different delay time according to levels of the edge information signal, wherein the sampling internal signal is selectively synchronized with a rising edge or a falling edge of the clock and the final output signal is synchronized with the rising edge of the clock.

These and other features, aspects, and embodiments are described below in the section “Detailed Description.”

DETAILED DESCRIPTION

Hereinafter, a semiconductor integrated circuit according to an embodiment of the present invention will be described with reference to the accompanying drawings.

According to an embodiment of the present invention, a domain crossing circuit capable of accurately synchronizing an internal input signal for a high frequency clock is provided. Furthermore, even when a set up margin between an internal input signal and a clock is insufficient, according to an embodiment of the present invention, the domain crossing circuit controls the internal input signals to be output at a constant timing by being synchronized with an edge of the clock. Thereby, according to an embodiment of the present invention, a domain crossing circuit suitable for reliable operation of a high-speed circuit is realized.

FIG. 1is a schematic block diagram of a domain crossing circuit10according to an embodiment of the present invention. Referring toFIG. 1, the domain crossing circuit10is configured to include a delay line100, a sampler200, and an output stage300.

The delay line100delays an external input signal IN1by a predetermined time, in consideration of a transfer time from an external pin (not shown) to an internal circuit unit (not shown), so as to provide an internal input signal IN2. The delay line100may be implemented using various methods. For example, a plurality of inverter chains coupled in series, a NAND gate logic, etc., may be used to realize the delay line100. The delay line100is constituted by a nonsynchronization delay device so that there may be a difference between time when the internal input signal IN2is output from the external input signal IN1and a predetermined delay time. The external input signal IN1may be input data, however it is to be understood that the present invention is not limited in this regard, and the external input signal may also be, for example, a command signal, etc.

According to an embodiment, the sampler200provides the internal input signal IN2as a sampling internal signal smp_out in synchronization with a clock CLK. Further, the sampler200provides an edge information signal position for determining whether the sampling internal signal smp_out is output in response to a rising edge of the clock CLK or is output in response to a falling edge of the clock CLK. That is, the sampler200provides the sampling internal signal smp_out by synchronizing the internal input signal IN2, which is a nonsynchronous signal, with one of the rising edge and the falling edge of the clock CLK.

More specifically, the sampler200samples the internal input signal IN2using one of the rising edge and the falling edge of the clock CLK, and primarily synchronizes the internal input signal IN2with the clock CLK using the sampled information. At this time, the sampling internal signal smp_out may be output based on the rising edge or the falling edge of the clock CLK based on when the internal signal IN2is delayed. Therefore, in an embodiment of the present invention, edge information of the clock at the time when the sampling internal signal smp_out is output is also required in a subsequent operation, thereby providing the edge information signal position.

The output stage300synchronizes the sampling internal signal smp_out with a desired edge of the clock CLK in response to the edge information signal position to provide the sampling internal signal smp_out as a final output signal OUT. According to an embodiment of the present invention, the output stage300synchronizes the sampling internal signal smp_out, primarily synchronized with the clock CLK, with the rising edge of the clock CLK.

In this case, the edge of the clock CLK that becomes the reference of output according to the feature of the circuit units may use the rising edge or the falling edge, however the final output signal OUT is provided based on the rising edge of the clock CLK, as will be described in detail below.

FIG. 2is a block diagram of shown an embodiment of the sampler200shown inFIG. 1.FIGS. 3 and 4are circuit diagrams showing embodiments of the trigger signal generation block220and the combination block240shown inFIG. 2, respectively.

Referring toFIGS. 2 to 4, the sampler200is configured to include a trigger signal generation block220, a combination block240, and a clock edge information block260.

The trigger signal generation block220generates first to fourth trigger signals HHEAD, LTAIL, LHEAD, and HTAIL in response to the internal input signal IN2and the clock CLK.

The trigger signal generation block220is configured to include first to fourth latch units222,224,226, and228.

The first latch unit222latches the internal input signal IN2on the rising edge of the clock CLK so as to provide the internal input signal as the first trigger signal HHEAD. The first latch unit222samples a logic level of the internal input signal IN2based on the rising edge of the clock CLK and delays the internal input signal IN2by a predetermined time to output the first trigger signal HHEAD. In other words, the first latch unit222may be a delay element that responds to the rising edge of the clock CLK.

The second latch unit224latches the first trigger signal HHEAD on the falling edge of the clock CLK so as to provide the first trigger signal HHEAD as the second trigger signal LTAIL. The second latch unit224delays the internal input signal IN2by a predetermined time so as to output the internal signal IN2in a next falling edge of the clock CLK. It will be assumed that a predetermined delay time, for example, a delay time satisfied by 1UI (Unit Interval; ½tCK), is set between the first latch unit222and the second latch unit224.

The third latch unit226latches the internal input signal IN2on the falling edge of the clock CLK so as to provide the internal input signal IN2as the third trigger signal LHEAD. The third latch unit226samples a logic level of the internal input signal IN2based on the falling edge of the clock CLK. The third latch unit226may be considered as a delay element that delays the internal input signal IN2by a predetermined time in response to the falling edge of the clock CLK.

The fourth latch unit228latches the third trigger signal LHEAD on the rising edge of the clock CLK so as to provide the third trigger signal LHEAD as the fourth trigger signal HTAIL. The fourth latch unit228delays the third trigger signal LHEAD by a predetermined time in response to the rising edge of the clock CLK so as to provide the fourth trigger signal HTAIL. In the same manner, it will be assumed that a predetermined delay time, for example, a delay time satisfied by 1UI (½tCK), is set between the third latch unit226and the fourth latch unit228.

Both the first and third latch units222and226sample the internal input signal IN2, but the first and third latch units222and226sample the internal input signal IN2using different edges of the clock CLK, i.e., the rising edge and the falling edge of the clock signal CLK. Further, the second and fourth latch units224and228latch the output of the first and third latch units222and226respectively to delay the outputs of the respective latch units by a half cycle (½tCK) of the clock CLK. If the cycle of the clock CLK is constant and the delay time between the latch units is also constant, the following equation can be exemplified.
(Falling time of clockCLK−rising time of clockCLK)within the same clockCLKcycle=delay time between latch units coupled in series=½tCK[Equation 1]

Therefore, when explained based on only the clock CLK, regardless of the internal input signal IN2, the second latch224and the third latch unit226respond to the same timing (i.e., the same falling edge) of the clock CLK. Therefore, if the clock CLK is constant, the transition time of the second trigger signal LTAIL and the third trigger signal LHEAD will correspond to each other, and furthermore if the internal input signal IN2is received in order to satisfy the set-up time, the second trigger signal LTAIL and the third trigger signal LHEAD that are latched from the same falling edge of the clock CLK will have the same level. It can be appreciated that if the clock CLK has a constant cycle, but the second trigger signal LTAIL and the third trigger signal LHEAD have different levels, the set-up time of the internal input signal IN2is not satisfied.

The combination block240provides the sampling internal signal smp_out continuously, the output timing of the sampling internal signal smp_out is adjusted in response to the first to fourth trigger signals HHEAD, LTAIL, LHEAD, and HTAIL. According to an embodiment of the present invention, even when a set-up margin of the internal input signal IN2is insufficient, the combination block240always provides the sampling internal signal smp_out having a delay time within ½tCK from a time point when the internal input signal IN2is applied using the first to fourth trigger signals HHEAD, LTAIL, LHEAD, and HTAIL.

As shown inFIG. 4, the combination block240is configured to include first to third NAND gates ND1to ND3.

The first NAND gate ND1logically NAND combines the first and fourth trigger signals HHEAD and HTAIL to provide a first reference edge signal INLOW.

The second NAND gate ND2logically NAND combines the second and third trigger signals LTAIL and LHEAD to provide a second reference edge signal INHIGH.

The third NAND gate ND3logically NAND combines the first and second edge signals INLOW and INHIGH to provide the sampling internal signal smp_out.

The first and fourth trigger signals HHEAD and HTAIL include ‘sampling information’ sampled from the first rising edge and the second rising edge within 1tCK, and the second and third trigger signals LTAIL and LHED include ‘sampling information’ sampled from the falling edge shared within 1tCK as described above. The information described above is information that is sampled for controlling the timing margin with the clock CLK at the time point when the internal input signal IN2is applied. The detailed description thereof will be described in more detail with reference to a timing diagram.

FIGS. 5 and 6are timing diagrams showing the relation of output signals of the trigger signal generation block220and the combination block240shown inFIG. 2.

FIG. 5shows a case where a set-up margin between the internal input signal IN2and the clock CLK is satisfied, andFIG. 6shows a case where set-up margin between the internal input signal IN2and the clock CLK is insufficient.

First, referring toFIG. 5, when a set-up time ‘ts’ between the internal input signal IN2and the clock CLK is satisfied, the first trigger signal HHEAD is sampled at a first rising edge of the clock CLK and delayed by a predetermined time to be output. After a delay time tdff between predetermined latch units elapses in response to the first trigger signal HHEAD, the second trigger signal LTAIL is output. The level of the internal input signal IN2is sampled at the first falling edge of the clock CLK to be provided as the third trigger signal LHEAD. After a delay time tdff between predetermined latch units elapses, the fourth trigger signal HTAIL is also output. The first reference edge signal INLOW (i.e., the NAND combined first and fourth trigger signals HHEAD and HTAIL) is output, and the second reference edge signal INHIGH (the NAND combined second and third trigger signals LHEAD and LTAIL) is also output. Here, it can be appreciated that the second reference edge signal INHIGH precedes the first reference edge signal INLOW. Therefore, the sampling internal signal smp_out is output in response to the preceding signal, that is, the second reference edge signal INHIGH.

That is, when the set-up margin between the internal input signal IN2and the clock CLK is satisfied, the output timings of the second and third trigger signals LTAIL and LHEAD correspond to each other. Therefore, the sampling internal signal smp_out is output in response to the second reference edge signal INHIGH. It can be appreciated that the timing when the sampling internal signal smp_out is output is within one cycle 1tCK of the clock CLK from the time where the internal input signal IN2is input.

Referring toFIG. 6, a case where a set-up time between the internal input signal IN2and the clock CLK is insufficient is illustrated. At the first rising edge t0of the clock CLK the internal input signal IN2is sampled having a low level, and at the second rising edge t2of the clock CLK the internal input signal IN2is sampled having a high level, thereby outputting the first trigger signal HHEAD. After a delay time tdff between predetermined latch units elapses in response to the first trigger signal HHEAD, the second trigger signal LTAIL is output. The level of the internal input signal IN2sampled at the first falling edge of the clock CLK is latched on the next falling edge and is output, thereby being output as the third trigger signal LHEAD. After a delay time tdff between predetermined latch units elapses in response to the third trigger signal LHEAD, the fourth trigger signal HTAIL is output. The first reference edge signal INLOW (i.e., the NAND combined first and fourth trigger signals HHEAD and HTAIL) is output, and in the same manner, the second reference edge signal INHIGH (i.e., the NAND combined second and third trigger signals LHEAD and LTAIL) is output. Here, it can be appreciated that the first reference edge signal INLOW precedes the second reference edge signal INHIGH. Therefore, the sampling internal signal smp_out is output in response to the preceding signal, that is, the first reference edge signal INLOW.

When the set-up margin between the internal input signal IN2and the clock CLK is insufficient as shown inFIG. 6, while the output timings of the second and third trigger signals LHEAD and LTAIL do not correspond to each other, it is shown that the output timings of the first and fourth trigger signals HHEAD and HTAIL do correspond to each other. Therefore, the sampling internal signal smp_out may be output based on the first reference edge signal INLOW generated in response to the first and fourth trigger signals HHEAD and HTAIL. It can be appreciated that the sampling internal signal smp_out is output within one cycle 1tCK of the clock CLK after the internal input signal IN2is input.

Assuming that the timings between when the sampling internal signal smp_out is output and the time point when the internal input signal IN2is input, as described above, are a first output time tout1and a second output time tout2inFIGS. 5 and 6, respectively. As shown inFIGS. 5 and 6, the first output time tout1and the second output time tout2are substantially the same. Therefore, the sampling internal signals smp_out synchronized with one of the rising edge and the falling edge of the clock CLK is provided within 1tCK from the time point when the internal input signal IN2, which is a nonsynchronous signal, is input.

FIG. 7is a conceptual circuit diagram showing a clock edge information block260shown inFIG. 2.

Referring toFIG. 7, the clock edge information block260outputs an edge information signal ‘position’ in response to the clock CLK and the sampling internal signal smp_out. That is, the clock edge information block260provides information for determining whether the timing that the sampling internal signal smp_out is output in response to is the rising edge or the falling edge of the clock CLK.

According to an embodiment of the present invention the clock edge information block260may include a latch unit F/F operating in the rising edge of the block260. Therefore, it can be appreciated that when the signal of the clock CLK latched in the rising edge of the sampling internal signal smp_out is at a low level, (i.e., the edge information signal position is at a low level) the sampling internal signal smp_out is synchronized with the falling edge of the clock CLK. Similarly, it can be appreciated that when the signal of the clock CLK latched in the rising edge of the sampling internal signal smp_out has a high level (i.e., the edge information signal position is at a high level) the sampling internal signal smp_out is synchronized with the rising edge of the clock CLK. As described above, the clock edge information block260provides edge information of the clock CLK in synchronization with the sampling internal signal smp_out as a level signal.

Referring toFIG. 8, the output stage300is configured to include first to fourth latch units310to340coupled in series.

The first latch unit310receives the sampling internal signal smp_out and operates in response to the falling edge of the clock CLK. The second latch unit320receives the output signal from the first latch unit310and operates in response to the rising edge of the clock CLK. The third latch unit330receives the output signal from the second latch unit320and operates in response to the falling edge of the clock CLK. The fourth latch unit340receives the output signal from one of the third latch unit330and the first latch unit310and operates in response to the rising edge of the clock CLK.

When the edge information signal position is at a low level, a first switch is activated such that the sampling internal signal smp_out is passed through the first to fourth latch units310to340. However, when the edge information signal position has a high level, a second switch is activated such that the sampling internal signal smp_out is passed through only the first and fourth latch units310and340. Here, although the first and second switches sw1and sw2are described for convenience of explanation, the present invention is not limited herein, for example a transmission gate may be used in the realization of the output stage300. Therefore, according to an embodiment of the present invention, the circuit unit can be implemented so that the number of latch units driven depends on the level of the edge information signal position. That is, the number of latch units driven is selectively varied depending on the level of the edge information signal position.

If a delay time between the first and second latch units310and320is Δt1, a delay time between the second and third latch units320and330is Δt2, and a delay time between the third and fourth latch units330and340is Δt3, the delay time between latch units is set as constant ½tCK, as will be described below.

A final output signal OUT, to be used in the internal circuit, can avoid colliding with the operation or the timing spec of other internal circuit units only when the final output signal OUT is output in synchronization with the rising edge of the clock CLK.

Therefore, when the sampling internal signal smp_out is synchronized with the rising edge of the clock CLK, the output stage300selects a portion of the latch units so that the final output signal OUT is output in response to the rising edge of the clock CLK within a predetermined time, that is, within a time of 1tCK, so as to be synchronized with the rising edge of the clock CLK in response to the high-level edge information signal position.

Similarly, when the sampling internal signal smp_out is output in response to the falling edge of the clock CLK, it all of the latch units in the output stage300are utilized so as to additionally delay a predetermined time. Therefore, according to the present invention, even when the sampling internal signal smp_out is output in response to the falling edge of the clock CLK, the final output signal OUT can be output in response to the rising edge of the clock CLK.

Therefore, when the edge information signal position is at a low level, the sampling internal signal smp_out is received and passed through all of the first to fourth latch units310to340, thereby providing the final output signal OUT. Similarly, when the edge information signal position is at a high level, the sampling internal signal smp_out is received and passed through partial latch units, that is for example, the first and fourth latch units310and340, thereby providing the final output signal OUT.

FIGS. 9 and 10are timing diagrams shown for illustrating the operation of the clock CLK, the sampling internal signal smp_out, and the final output signal OUT.

Referring toFIGS. 8 to 10, the synchronization of the final output signal OUT with the rising edge of the clock CLK using the edge information signal position is described below.

First,FIG. 9shows a case where the sampling internal signal smp_out is output in response to the falling edge of the clock CLK while the edge information signal position is at a low level. Therefore, for the sampling internal signal smp_out to be synchronized with the rising edge of the clock CLK, the total delay time includes the time of 1tCK and additionally the time of ½tCK, such that the sampling internal signal smp_out passes through all of the first to fourth latch units310to340. In other words, in a case where the sampling internal signal smp_out is output in response to a falling edge of the clock CLK, the output of the sampling internal signal smp_out is delayed by the difference ½tCK between the falling edge and the rising edge of the clock CLK and is output to be synchronized with the rising edge of the clock CLK in addition to a stabilized predetermined time (time of one clock cycle 1tCK) from the application of the sampling internal signal smp_out to the final output, thereby making it possible to provide the final output signal OUT.

FIG. 10shows a case where the sampling internal signal smp_out is output in response to the rising edge of the clock CLK while the edge information signal position has a high level. Therefore, for the sampling internal signal smp_out to be synchronized with the rising edge of the clock CLK, the sampling internal signal smp_out passes through the first and fourth latch units310and340, since the sampling internal signal smp_out can be synchronized with the rising edge of the clock CLK when the sampling internal signal smp_out is output within one stable clock cycle 1tCK from a time when the sampling internal signal smp_out is applied. Thereby, the final output signal OUT can be provided in response to the rising edge of the clock CLK.

This is only an example to synchronously adjust the delay time to be responded to the rising edge of the clock CLK in response to the sampling internal signal smp_out. It is to be understood that it is also possible to configure the sampling internal signal smp_out output in response to the falling edge of the clock CLK depending on the constitution of the internal circuit or the property of the signal.

As described above, the domain crossing circuit according to an embodiment of the present invention samples and uses the transition information of the clock CLK, making it possible to synchronize a nonsynchronous signal with the clock and to synchronize the nonsynchronous signal again with the desired edge of the clock using the clock edge information at the synchronized time point.