Semiconductor device

A semiconductor device includes a semiconductor substrate having a drift layer, a base layer, a collector layer and a cathode layer. The semiconductor substrate includes a cell region and an outer peripheral region surrounding the cell region. The cell region includes an IGBT region and a diode region. The semiconductor substrate further includes a damage region arranged in the diode region and a part of the outer peripheral region adjacent to a boundary between the outer peripheral region and the diode region. A length, in a longitudinal direction of the diode region, of the part of the outer peripheral region, in which the damage region is arranged, is equal to or more than twice of a thickness of the semiconductor substrate. As a result, recovery characteristic is improved in a portion of the diode region adjacent to the boundary between the outer peripheral region and the diode region.

CROSS REFERENCE TO RELATED APPLICATION

This application is based on Japanese Patent Application No. 2015-184084 filed on Sep. 17, 2015, the disclosure of which is incorporated herein by reference.

TECHNICAL FIELD

The present disclosure relates to a semiconductor device having an IGBT region, in which an insulated gate bipolar transistor (IGBT) is arranged, and a diode region, in which a freewheeling diode (FWD) is arranged.

BACKGROUND

For a switching element employed in an inverter or the like, it is conventionally proposed a semiconductor device having an IGBT region, in which an IGBT element is arranged, and a diode region, in which a diode element is arranged (for example, see JP 2008492737 A).

Specifically, in the semiconductor device, a base layer is arranged at a surface layer portion of a semiconductor substrate providing an N−type drift layer. A trench gate structure is arranged to pass through the base layer. On a rear surface of the semiconductor substrate, a P type collector layer and an N type cathode layer are arranged. An N type emitter region is arranged at a portion of the base layer located above the collector layer.

On a front surface of the semiconductor substrate, an upper electrode, which is electrically connected to the base layer and the emitter region, is arranged. On the rear surface of the semiconductor substrate, a lower electrode, which is electrically connected to the collector layer and the cathode layer, is arranged.

That is, the IGBT region corresponds to a region in which the collector layer is arranged on the rear surface of the semiconductor substrate, and the diode region corresponds to a region in which the cathode layer is arranged on the rear surface of the semiconductor substrate. In other words, in the above semiconductor device, a boundary between the collector layer and the cathode layer corresponds to a boundary between the IGBT region and the diode region.

The IGBT region and the diode region are repeated alternately in one direction along a plane of the semiconductor substrate. The IGBT region and the diode region extend along a longitudinal direction perpendicular to the one direction in which the IGBT region and the diode region are repeated.

At a surface layer portion of the diode region of the semiconductor substrate, a damage region is arranged. The damage region is formed by irradiating He-ray to an entire surface of the semiconductor substrate.

In the above semiconductor device, a hole of the drift layer (i.e., an excess carrier) is recombined with an electron and eliminated in the damage region during the recovery time of the diode element. Therefore, the excess carrier, which causes a reverse current flowing to the diode element during the recovery time, is reduced, and the reverse current is decreased. Accordingly, a recovery characteristic of the diode element is improved.

SUMMARY

In the above semiconductor device, however, a hole that flows from the IGBT region (i.e., IGBT element) to the diode region (i.e., diode element) during the recovery time is not blocked. There is a possibility that the recovery characteristic is decreased especially at each end of the diode region in the longitudinal direction.

That is, when the IGBT region and the diode region are defined as a cell region, there is a possibility that the recovery characteristic is decreased at a boundary region between the cell region and an outer peripheral region surrounding the cell region.

In the present disclosure, the phrase “recovery characteristic is decreased” means that the recovery current is increased, that recovery loss is increased, and that recovery resistance is decreased.

It is an object of the present disclosure to provide a semiconductor device capable of improving a recovery characteristic at a boundary region between a diode region and an outer peripheral region.

According to an aspect of the present disclosure, a semiconductor device includes a semiconductor substrate having a drift layer, a base layer, a collector layer and a cathode layer. The drift layer has a first conductivity type. The base layer has a second conductivity type and is arranged on the drift layer. The collector layer has the second conductivity type. The cathode layer has the first conductivity type. The collector layer and the cathode layer are arranged opposite to the base layer with respect to the drift layer.

The semiconductor substrate includes a cell region and an outer peripheral region surrounding the cell region. The cell region includes an IGBT region operating as an IGBT element, and a diode region operating as a diode element. The IGBT region and the diode region are alternately repeated in the cell region.

The collector layer is arranged in the IGBT region and the cathode layer is arranged in the diode region. A boundary between the IGBT region and the diode region is defined by a boundary between the collector layer and the cathode layer. The collector layer is arranged in the outer peripheral region and is in contact with the cathode layer A boundary between the outer peripheral region and the diode region of the cell region is defined by the boundary between the collector layer and the cathode layer.

The semiconductor substrate further includes a damage region arranged in a surface layer portion of the semiconductor substrate. The damage region is arranged in the diode region and a part of the outer peripheral region adjacent to the boundary between the outer peripheral region and the diode region.

When a direction in which the diode region and the IGBT region are repeated is defined as an arrangement direction, and a direction perpendicular to the arrangement direction is defined as a longitudinal direction of the diode region, a length, in the longitudinal direction of the diode region, of the part of the outer peripheral region, in which the damage region is arranged, is equal to or more than twice of a thickness of the semiconductor substrate.

As described above, the damage region is arranged in the part of the outer peripheral region adjacent to the boundary between the outer peripheral region and the diode region, and the length, in the longitudinal direction of the diode region, of the part of the outer peripheral region, in which the damage region is arranged, is equal to or more than twice of the thickness of the semiconductor substrate.

As a result, a hole is restricted from being inserted from the outer peripheral region to the diode region, and a recovery characteristic is improved in a portion of the diode region adjacent to the boundary between the outer peripheral region and the diode region.

DETAILED DESCRIPTION

Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In the embodiments, same or equivalent parts will be designated with the same symbols.

A first embodiment of the present disclosure will be described. For example, a semiconductor device of the present embodiment is employed as a power switching element of a power source circuit such as an inverter, a direct current (DC)/DC converter and the like.

As shown inFIG. 1, the semiconductor device includes a cell region1and an outer peripheral region2surrounding the cell region1.

As shown inFIG. 1andFIG. 2, the cell region1includes IGBT regions1aand diode regions1b.An IGBT element is arranged in the IGBT region1aand a diode element is arranged in the diode region1b.

Specifically, the IGBT region1aand the diode region1bare arranged in an N−type semiconductor substrate10. The N−type semiconductor substrate10provides a drift layer11. Each of the IGBT regions1aand the diode regions1bextends along an extension direction of a first surface10aof the semiconductor substrate10. The extension direction corresponds to a vertical direction of the paper surface ofFIG. 1. The extension direction will be also referred to as a longitudinal direction of the IGBT region1aand the diode region1b.

The IGBT regions is and the diode regions1bare arranged alternately in a direction perpendicular to the extension direction. The direction, in which the IGBT regions is and the diode regions1bare arranged, will be also referred to as an arrangement direction of the IGBT regions1aand the diode regions1b.

A P type base layer12is arranged on the drift layer11. Namely, the P type base layer12is arranged adjacent to the first surface10aof the semiconductor substrate10. The P type base layer12has an impurity concentration of around 1.0×1017cm3. Plural trenches13are arranged to pass through the base layer12and reach the drift layer11. The trenches13separate the base layer12into plural portions.

In the present embodiment, the trenches13extend along a planar direction along the first surface10aof the semiconductor substrate10. The planar direction corresponds to a front-back direction of the paper surface ofFIG. 2. The trenches13are arranged to have equal intervals with each other. The first surface10aof the semiconductor substrate10is a surface of the base layer12opposite to the drift layer11.

The base layer12functions as a channel region in the IGBT region1a.In the base layer12as the channel region (i.e., the base layer12in the IGBT region1a), N+type emitter regions14and P+type body regions15are arranged. Each of the body regions15is sandwiched between the emitter regions14.

The emitter region14has impurity concentration higher than the drift layer11. The emitter region14ends within the base layer12, and is in contact with a side surface of the trench13. The body region15has impurity concentration higher than the base layer12. Similarly to the emitter region14, the body region15ends within the base layer12.

For details, the emitter region14is arranged between the trenches13. The emitter region14has a bar shape extending along a longitudinal direction of the trench13and is in contact with the side surface of the trench13. The emitter region14ends shallower than an end of the trench13. Namely, the emitter region14is shorter than the trench13in the longitudinal direction of the trench13. The body region15has a bar shape extending along the longitudinal direction of the trench13(i.e., extending along the emitter region14) and is sandwiched between two emitter regions14. In the present embodiment, the body region15is deeper than the emitter region14with respect to the first surface10aof the semiconductor substrate10.

In each of the trenches13, a gate insulation film16and a gate electrode17are implanted. The gate insulation film16covers an inner wall surface of the trench13. The gate electrode17is made of polysilicon and the like, and is arranged on the gate insulation film16. As described above, a trench gate structure is provided.

On the base layer12(i.e., on the first surface10aof the semiconductor substrate10), an interlayer insulation film18is arranged. The interlayer insulation film18is made of, for example, boron phosphorous silicon glass (BPSG). The interlayer insulation film18has contact holes18aand contact holes18b.The contact hole18aexposes a part of the emitter region14and the body region15in the IGBT region1a.The contact hole18bexposes the base layer12in the diode region1b.

On the interlayer insulation film18, an upper electrode19is arranged. The upper electrode19is electrically connected to the emitter region14and the body region15through the contact holes18ain the IGBT region1a.The upper electrode19is electrically connected to the base layer12through the contact holes18bin the diode region1b.That is, the upper electrode19functions as an emitter electrode in the IGBT region, and functions as an anode electrode in the diode region1b.

An N type field stop layer20, which is referred to as a FS layer, is arranged opposite to the base layer12with respect to the drift layer11. Namely, the FS layer20is arranged adjacent to a second surface10bof the semiconductor substrate10. The FS layer is not always required. The FS layer is arranged to improve performance such as resistance and steady loss by restricting a depletion layer from spreading, and to control the amount of holes inserted from the second surface10bof the semiconductor substrate10.

In the IGBT region1a,a P type collector layer21is arranged opposite to the drift layer11with respect to the FS layer20. In the diode region1b,an N type cathode layer22is arranged opposite to the drift layer11with respect to the FS layer20. That is, the IGBT region1aand the diode region1bare divided according to whether a layer arranged adjacent to the second surface10bof the semiconductor substrate10is the collector layer21or the cathode layer22. In other words, a boundary between the IGBT region1aand the diode region1bis defined by a boundary between the collector layer21and the cathode layer22.

In the present embodiment, the second surface10bof the semiconductor substrate10is provided by the collector layer21and the cathode layer22. In the present embodiment, the collector layer21is arranged opposite to the base layer12, which has the emitter region14and the body region15, with respect to the FS layer20. The cathode layer22is arranged opposite to the base layer12, which does not have the emitter region14and the body region15, with respect to the FS layer20. That is, in the present embodiment, the boundary between the IGBT region1aand the diode region1bis defined by a boundary between the base layer12, which has the emitter region14and the body region15, and the base layer12, which does not have the emitter region14and the body region15.

As described above, the base layer12is arranged adjacent to the first surface10aof the semiconductor substrate10, and the collector layer21and the cathode layer22are arranged adjacent to the second surface10bof the semiconductor substrate10. That is, the semiconductor substrate10includes the collector layer21, the cathode layer22, the FS layer20, the drift layer11and the base layer12laminated in orders.

A lower electrode23is arranged on the collector layer21and the cathode layer22(i.e., on the second surface10bof the semiconductor substrate10). The lower electrode23functions as the collector electrode in the IGBT region1a,and functions as the cathode electrode in the diode region1b.

As a result, a PN junction diode, including the base layer12as an anode and including the drift layer11, the FS layer20and the cathode layer22as a cathode, is provided in the diode region1b.

A damage region24is arranged adjacent to the first surface10aof the semiconductor substrate10. In other words, the damage region24is arranged at a surface layer portion of the semiconductor substrate10. The damage region24is arranged in a surface layer portion of the drift layer11. Specifically, the damage region24is arranged in the diode region1b.The damage region24protrudes from the diode region1btoward the outer peripheral region2in the longitudinal direction of the diode region1b.

That is, the damage region24is arranged in the diode region1band a part of the outer peripheral region2adjacent to the boundary between the diode region1band the outer peripheral region2.

As a result, a hole (i.e., an excess hole) of the drift layer11in the outer peripheral region2is recombined with an electron and eliminated at the damage region24, arranged in the outer peripheral region2. Therefore, the hole is restricted from being inserted from the outer peripheral region2into the diode region1b.

A relationship between the damage region24, arranged in the outer peripheral region2, and a thickness of the semiconductor substrate10will be described. Hereinafter, a thickness of the semiconductor substrate10is represented as “d”, a width of the damage region24arranged in the outer peripheral region2is represented as “W1”. A ratio of the width of the damage region24, arranged in the outer peripheral region2, to the thickness of the semiconductor substrate10is defined as a first thickness ratio (W1/d).

The width W1of the damage region21arranged in the outer peripheral region2is a length in the longitudinal direction of the diode region1b,which is one of the directions along the plane of the first surface10aof the semiconductor substrate10. For example, the width W1is the length along the vertical direction of the paper surface ofFIG. 1. In other words, the width W1is the length in a direction perpendicular to the arrangement direction of the IGBT regions is and the diode regions1b.

As shown inFIG. 4, rated current value steeply decreases when the first thickness ratio (W1/d) exceeds 0, and almost does not change when the first thickness ratio (W1/d) exceeds 2. In other words, at a point where the first thickness ratio (W1/d) is equal to 2, a tangent line L1and a tangent line L2crosses. The tangent line L1corresponds to a portion in which the rated current value steeply decreases. The tangent line L2corresponds to a portion in which the rated current value almost does not change. Accordingly, the damage region24is arranged so that the first thickness ratio (W1/d) is equal to or more than 2.

InFIG. 4, when the damage region24is arranged only in the diode region1b,the first thickness ratio (W1/d) is equal to 0. When the damage region24is not arranged in the portion of the diode region1badjacent to the outer peripheral region2, the first thickness ratio (W1/d) is less than 0.

The structure of the cell region1of the present embodiment is described hereinabove. Next, the structure of the outer peripheral region2surrounding the cell region1will be described.

As shown inFIG. 3, in the outer peripheral region2, plural P type guard rings25are arranged adjacent to the first surface10aof the semiconductor substrate10. The guard rings25have a multiple ring structure. Each of the guard rings25has impurity concentration higher than the base layer12. For example, the guard ring25has impurity concentration around 1.0×1018cm−3. In the present embodiment, one of the guard rings25that is arranged closest to the cell region1is arranged to be in contact with the base layer12of the diode region1b.

An oxide film26is arranged on the guard rings25. The oxide film26has openings26aat portions corresponding to the guard rings25. Outer peripheral electrodes27are arranged on the oxide film26. The outer peripheral electrodes27are electrically connected to the guard rings25through the openings26aof the oxide film26. A passivation film28is arranged to cover the outer peripheral electrodes27, and the outer peripheral electrodes27are protected by the passivation film28.

The P type collector layer21is arranged opposite to the drift layer11with respect to the FS layer20in the second surface10bside of the semiconductor substrate10. That is, the diode region1band the outer peripheral region2are divided according to whether a layer arranged adjacent to the second surface10bof the semiconductor substrate10is the collector layer21or the cathode layer22. In other words, the boundary between the diode region1band the outer peripheral region2is defined by the boundary between the collector layer21and the cathode layer22.

In the present embodiment, the collector layer21is arranged opposite to the guard rings25with respect to the FS layer20. The cathode layer22is arranged opposite to the base layer12with respect to the FS layer20. That is, in the present embodiment, the boundary between the diode region1band the outer peripheral region2is defined by the boundary between the guard rings25and the base layer12.

As described above, the semiconductor device of the present embodiment is provided. In the present embodiment, N type, N−type and N+type correspond to a first conductivity type, and P type and P+type correspond to a second conductivity type.

Next, a method for producing the above semiconductor device will be described. As shown inFIG. 5, an N−type wafer100having plural chip formation regions101is prepared.

The base layer12, which is shown inFIG. 1, is formed in a surface100aof the wafer100by thermal diffusion. Thereafter, the trench gate structure, the emitter regions14and the body regions15are formed in each of the chip formation regions101. The interlayer insulation film18is formed on the base layer12, and the contact holes18aand18bare formed in the interlayer insulation film18. The upper electrode19is formed on the interlayer insulation film18. The upper electrode19is electrically connected to the emitter regions14and the body regions15through the contact holes18a,and electrically connected to the base layer12through the contact holes18b.

The FS layer20is formed in another surface100bof the wafer100. The collector layer21and the cathode layer22are formed opposite to the drift layer11with respect to the FS layer20.

Next, as shown inFIG. 6andFIG. 7, a mask110is prepared and disposed on the surface100bof the wafer100. The mask110has openings110aat potions opposing to the diode regions1b(i.e., cathode layer22) and the portions of the outer peripheral region2adjacent to the boundary between the outer peripheral region2and the diode region1b(i.e., a part of the collector layer21). The damage region24is formed by irradiating He-ray from the surface100bof the wafer100.FIG. 6is an enlarged diagram illustrating the situation in which the mask110is disposed at a region A ofFIG. 5.

The lower electrode23is formed on the surface100bof the wafer100. Thereafter, the wafer100is divided into chip units to produce the above semiconductor device. The outer peripheral region2, including the guard rings25and the outer peripheral electrodes27, is formed in the above method, or is formed in another exclusive process.

As described above, in the present embodiment, the damage region24, having the first thickness ratio (W1/d) equal to or higher than 2, is arranged in the portion of the outer peripheral region2adjacent to the boundary between the outer peripheral region2and the diode region1b.The hole1arestricted from being inserted from the outer peripheral region2to the diode region1b.As a result, the recovery characteristic is improved in the portion of the diode region1badjacent to the boundary between the outer peripheral region2and the diode region1b.

A second embodiment of the present disclosure will be described. In the second embodiment, a layout of the damage region24is different from the first embodiment. Since the other part of the second embodiment is similar to the first embodiment, only the part different from the first embodiment will be described.

As shown inFIG. 8andFIG. 9, in the present embodiment, the damage region24protrudes from the diode region1btoward the IGBT region1a.As a result, a hole (i.e., an excess hole) of the drift layer11in the IGBT region1ais recombined with an electron and eliminated at the damage region24, arranged in the IGBT region1a.Therefore, the hole is restricted from being inserted from the IGBT region1ainto the diode region1b.

A relationship between the damage region24, arranged in the IGBT region1a,and the thickness of the semiconductor substrate10will be described. Hereinafter, the thickness of the semiconductor substrate10is represented as “d”, a width of the damage region24arranged in the IGBT region1ais represented as “W2”. A ratio of the width of the damage region24, arranged in the IGBT region1a,to the thickness of the semiconductor substrate10is defined as a second thickness ratio (W2/d).

The width W2of the damage region24, arranged in the IGBT region1a,is a length in the arrangement direction of the IGBT regions1aand the diode regions1b,which is one of the directions along the plane of the first surface10aof the semiconductor substrate10. For example, the width W2is the length along the horizontal direction of the paper surface ofFIG. 9.

As shown inFIG. 10, rated current value steeply decreases when the second thickness ratio (W2/d) exceeds 0, and almost does not change when the second thickness ratio (W2/d) exceeds 1. In other words, at a point where the second thickness ratio (W2/d) is equal to 1, a tangent line L3and a tangent line L4cross. The tangent line L3corresponds to a portion in which the rated current value steeply changes. The tangent line L4corresponds to a portion in which the rated current value almost does not change. Accordingly, the damage region24is arranged so that the second thickness ratio (W2/d) is equal to or more than 1.

The rated current ratio of the present embodiment, which is described inFIG. 10, corresponds to a recovery current for a current flowing when the IGBT element (i.e., the semiconductor device) is turned on. When the rated current ratio decreases, the recovery current also decreases. A design current ratio of the present embodiment, which is described inFIG. 10, corresponds to a ratio of a test current (i.e., an on-current applied to the IGBT element) to an allowable current (i.e., design current) of the IGBT element. InFIG. 10, when the damage region24is arranged only in the diode region1b,the second thickness ratio (W2/d) is equal to 0. When the damage region24is not arranged in the portion of the diode region1badjacent to the IGBT region1a,the second thickness ratio (W2/d) is less than 0.

When the damage region24is arranged in the IGBT region1a,a hole is recombined with an electron and eliminated at the damage region24even in the regular operation of the IGBT element, and the on-voltage increases. As shown inFIG. 11, on-voltage increases as a ratio of the width of the damage region24to the width of the IGBT region1aincreases. That is, on-voltage decreases as a ratio of a width a part of the IGBT region1a,in which the damage region24is not arranged, to the width of the IGBT region1aincreases. In other words, on-voltage decreases as a ratio of width difference between the IGBT region1aand the damage region24to the width of the IGBT region1aincreases.

Accordingly, the damage region24is arranged at the portion of the IGBT region1aadjacent to the boundary between the IGBT region1aand the diode region1b,so that the second thickness ratio is equal to or more than 1. The damage region24is not arranged out of the portion of the IGBT region1aadjacent to the boundary between the IGBT region1aand the diode region1b.

For example, the IGBT region1apreferably has a portion, in which the damage region24is not arranged, (i.e., a no-damage-region-arranged portion) having a width equal to or more than half of the width of the IGBT region1a.In other words, a width of a portion of the IGBT region1a,in which the damage region24is not arranged, is preferably equal to or more than half of the width of entire IGBT region1a.

The width of the IGBT region1ais a length in the arrangement direction of the IGBT regions1aand the diode regions1b,which is one of the directions along the plane of the first surface10aof the semiconductor substrate10. For example, the width of the IGBT region1ais the length along the horizontal direction of the paper surface ofFIG. 8.

Even when the damage region24is arranged in the IGBT region1aas described above, the switching loss does not change as shown inFIG. 12. The steady current described inFIG. 12is a current flowing when the IGBT element (i.e., the semiconductor device) is turned on.

As described above, in the second embodiment, the damage region24is arranged at the portion on the IGBT region1aadjacent to the boundary between the IGBT region1aand the diode region1b,so that the second thickness ratio is equal to or more than 1. The IGBT region1aincludes the portion in which the damage region24is not arranged.

The on-voltage is restricted from decreasing, and the holes are restricted from being inserted from the IGBT region1ato the diode region1b.In addition to restricting the on-voltage from decreasing, the recovery characteristic is improved in the portion of the diode region1badjacent to the boundary between the IGBT region1aand the diode region1b.That is, in addition to restricting the on-voltage from decreasing, the recovery current and the recovery loss is reduced and the recovery resistance is improved.

A method for producing the above semiconductor device is similar to the first embodiment. A mask110shown inFIG. 13is prepared when the He-ray is irradiated as shown inFIG. 7. Specifically, the mask110has openings110aat portions opposing to the portions of the outer peripheral region2adjacent to the boundary between the outer peripheral region2and the diode region1b(i.e., a part of the collector layer21). As such, the semiconductor device according to the second embodiment is produced.FIG. 13is an enlarged diagram illustrating the situation in which the mask110is disposed at a region A ofFIG. 5.

A third embodiment of the present disclosure will be described. In the third embodiment, a layout of the damage region24is different from the second embodiment. Since the other part of the third embodiment is similar to the second embodiment, only the part different from the second embodiment will be described.

As shown inFIG. 14, the damage region24is arranged in the portion of the IGBT region1aadjacent to the boundary between the diode region1band the IGBT region1a.The damage region24in the IGBT region1aincludes an end portion adjacent to an end of the diode region1bin the longitudinal direction of the diode region1b.The damage region24in the IGBT region1aincludes a center portion adjacent to a center of the diode region1bin the longitudinal direction of the diode region1b.A width of the end portion of the damage region24is greater than a width of the center portion of the damage region24. Specifically, the width of the end portion of the damage region24in the IGBT region1ais W1, and the width of the center portion of the damage region24in the IGBT region1ais W2. The width W1is a length along the horizontal direction of the paper surface ofFIG. 14. The width W2is a length along the horizontal direction of the paper surface ofFIG. 14.

As a result, a hole is restricted from being inserted from the outer peripheral region2to the diode region1bthrough the IGBT region1a,and the recovery characteristic of the diode region1bis further improved.

A method for producing the above semiconductor device is similar to the first embodiment. A mask110is prepared when the He-ray is irradiated as shown inFIG. 7, and the mask110having the openings110asize of which are larger in each end of the diode region1bthan the center of the diode region1b.

In the first embodiment, the first conductivity type corresponds to P type and the second conductivity type corresponds to N type. However, the first conductivity type may correspond to N type and the second conductivity type may correspond to P type.

In the above embodiments, the portion of the base layer12arranged in the IGBT region1a(i.e., the channel region) may have different impurity concentration from the portion of the base layer12arranged in the diode region1b(i.e., the anode).

In the above embodiments, another damage layer different from the damage region24may be arranged adjacent to the second surface10bof the semiconductor substrate10. The damage layer arranged in the IGBT region1arecombines and quenches the excess carriers of the drift layer11in the IGBT region1a.Therefore, excellent trade-off characteristic between the switching loss and the steady loss is achieved in the IGBT element. The damage layer arranged in the diode region1brecombines and quenches the excess carriers of the drift layer11in the diode region1b.Therefore, excellent trade-off characteristic between the switching loss and the steady loss is achieved in the diode element.

In the above embodiments, IGBT element may be a planar type instead of the trench gate type.

In the above embodiments, as shown inFIG. 15A, the IGBT region1amay have repetition units, in which the emitter region14and the body region15are omitted, repeatedly mirror-inverted. In such a case, among the base layer12, which is divided by the trenches13, the portion having the emitter region14functions as the channel region12a,and the portion not having the emitter region14functions as the float region12b.

As shown inFIG. 15B, the IGBT region1amay have repetition units, in which an N type hole stopper layer (HS layer)29is arranged to divide the float region12bin the depth direction, repeatedly mirror-inverted. In such a case, the HS layer29restricts the holes in the drift layer11from flowing into the upper electrode19through the float region12b.

As shown inFIG. 15C, the IGBT region1amay have repetition units, in which the HS layer29is arranged and a carrier storage layer (CS layer)30is arranged between the channel region12aand the drift layer11, repeatedly mirror-inverted. In such a case, the CS layer30restricts the holes in the drift layer11from flowing into the upper electrode19through the channel region12a.

Although not especially illustrated, inFIG. 15C, the HS layer29may be omitted in the IGBT region1a.

In the second and the third embodiments, the boundary between the IGBT region1aand the diode region1bcorresponds to the boundary between the base layer12, which has the emitter region14and the body region15, and the base layer12, which does not have the emitter region14and the body region15.

However, the IGBT region1aand the diode region1bare divided according to whether the layer arranged adjacent to the second surface10bof the semiconductor substrate10is the collector layer21or the cathode layer22. Therefore, as shown inFIG. 16, the boundary between the IGBT region1aand the diode region1bmay be located between the adjacent base layers12both of which do not have the emitter region14and the body region15.

That is, the base layer12, which does not have the emitter region14and the body region15, may be arranged in the IGBT region1aadjacent to the diode region1b.In such a semiconductor device, when the damage region24, having the second thickness ratio (W2/d) equal to or more than 1, is arranged in the IGBT region1a,the recovery characteristic of the diode region1bis improved.

In the first to third embodiments, as shown inFIG. 17, the diode region1band the outer peripheral region2may be arranged to divide the base layer12. That is, the base layer12may be arranged in the outer peripheral region2adjacent to the diode region1b.In such a semiconductor device, when the damage region24, having the first thickness ratio (W1/d) equal to or more than 2, is arranged in the outer peripheral region2, the recovery characteristic of the diode region1bis improved.

In the first to third embodiments, the damage region24, arranged in the outer peripheral region2, may be extended to ends of the semiconductor substrate10along the extension direction of the diode region1b.In such a case, as shown inFIG. 18, a mask110, which has stripe shaped openings110aand shielding portions (masking portions), is employed, and a shaping process of the mask110is simplified.

In the first and the second embodiments, the mask110, which has the openings110aat portions opposing to the damage region24, may include plural masks having the stripe shaped openings110aand the shielding portions.

In the third embodiment, as shown inFIG. 19, the portions of the damage region24, arranged at both ends of the diode region1bin the extension direction of the diode region1b,may have other shape such as circular shape. For example, the damage region24have circular shape in which the first thickness ratio (W1/d) of the center of the damage region24arranged in the outer peripheral region2is equal to or more than 2.

In the above embodiments, when the damage region24arranged at both ends of the diode region1bhas square shape or circular shape, the damage region24arranged at center portion of the diode region1bdoes not have to protrude toward the IBGT region1a.

While only the selected exemplary embodiment and examples have been chosen to illustrate the present disclosure, it will be apparent to those skilled in the art from this disclosure that various changes and modifications can be made therein without departing from the scope of the disclosure as defined in the appended claims. Furthermore, the foregoing description of the exemplary embodiment and examples according to the present disclosure is provided for illustration only, and not for the purpose of limiting the disclosure as defined by the appended claims and their equivalents.