THIN FILM RESISTOR MISMATCH IMPROVEMENT USING A SELF-ALIGNED DOUBLE PATTERN (SADP) TECHNIQUE

A passive circuit component includes an edge having a low line edge roughness (LER). A method for manufacturing the passive circuit component includes a self-aligned double patterning (SADP) etch process using a tri-layer process flow. The tri-layer process flow includes use of an underlayer, hard mask, and photoresist. The passive circuit component made by this method achieves improved mismatch between like components due to the low LER.

BACKGROUND

Thin film resistor mismatch is defined as the difference in the value of a resistor parameter (e.g., resistance) among generally identically designed resistors. Reducing thin film resistor mismatch is difficult due to, inter alia, line edge roughness (LER) often associated with the pattern transfer process (e.g., photoresist patterning and the etch process). LER is defined as a deviation of a feature edge from a smooth, ideal sidewall surface. With higher LER, an increased mismatch occurs between one resistor and its neighboring resistor because the edges are less smooth than for resistors having lower LER, resulting in variability in the width of the resistor along those edges. Moreover, for a given LER, narrower resistors are more affected by the variable width. It is desirable to have those edges as smooth as possible so that resistor-to-resistor matching is improved. Therefore, LER should be as small as possible to improve thin film resistor matching.

SUMMARY

One example provides a method of forming an integrated circuit that includes receiving semiconductor substrate with a material layer thereover. A hard mask is formed over an underlayer located over the material layer. The hard mask is patterned, therefrom forming a hard mask line. Spacers are formed on sidewalls of the hard mask line, and the hard mask line between the spacers is removed, thereby forming a spacer line pattern. A block mask pattern is formed over the spacers and the underlayer, and the block mask pattern is transferred to the underlayer, thereby forming an exposed portion of the material layer. The exposed portion of the material layer is removed, and the spacer line pattern is transferred to the material layer, thereby forming a patterned material layer.

In another example, a method of forming an integrated circuit includes forming a sacrificial layer pattern over a conductive layer located over a substrate. Dielectric spacers are formed on sidewalls of the sacrificial layer pattern and the sacrificial layer is removed between the dielectric spacers, thereby forming a spacer pattern. The spacer pattern is transferred to the conductive layer thereby forming a conductive pattern.

The same reference number is used in the drawings for the same or similar (either by function and/or structure) features.

DETAILED DESCRIPTION

This description provides examples of the fabrication of a resistor to reduce LER.

The resistor may be a thin-film or non-thin-film resistor. Although the embodiments described pertain to resistors, the manufacturing techniques of this description can be applied to the fabrication of other types of passive components such as capacitors or inductors. Such alternatives are considered to be within the spirit and scope of the present description, and may utilize the advantages of the configurations and embodiments described herein.

For thin film resistors, reducing mismatch between resistors is desirable in many applications. Reducing LER helps to reduce the mismatch between thin film resistors on the same die and between the corresponding resistors on different dies of the same integrated circuit design. LER is associated with both the photoresist patterning and the etch process. Specifically, with standard lithography and etch techniques which include patterning a photoresist directly on a substrate, because of the chemically amplified resist that is used, rougher edges of the resistors are exhibited which create a pseudo-oscillatory pattern along that entire edge. The smaller the feature that is patterned, the worse the LER becomes. With higher LER, a mismatch occurs between one resistor and its neighboring resistor because the edges are not precisely smooth resulting in variability in the width of the resistor along those edges, resulting in imprecise resistor values. A goal is to have the edges as smooth as reasonably possible for a given application thereby improving the resistor-to-resistor match. For at least these reasons, it is desired to reduce the LER as much as possible.

An aspect of this disclosure reduces LER for thin film resistors by using, inter alia, a tri-layer fabrication approach which includes spin coating an underlayer above a substrate, then spin coating a silicon-containing hard mask above the underlayer, and then using a photoresist to transfer a pattern through the hard mask and the underlayer to the substrate. With this technique, the deposition process drives/controls the pattern transfer. In addition, the minimum pitch of the process can be cut in half (e.g., 100 nm pitch becomes 50 nm) and more resistors can be fit per unit area (e.g., 100 nm pitch doubles to 50 nm and therefore doubles number of resistors per unit area). Compared to conventional fabrication techniques, the process described herein results in substantially lower mismatch and permits smaller high precision resistors to be fabricated, e.g., having widths as low as 25 nm in the example above.

FIG.1shows a plot100of standard deviation of relative resistance (along the y-axis, in ppm) as a function of the inverse of the square of the cross-sectional area (1/√{square root over (area)}, along x-axis, in μm−1) for a population of two illustrative adjacent resistors, such as exemplified by resistors shown inFIG.2B. In theFIG.1plot100, the curve10is a best fit to the data which depicts a measure of mismatch between two identically drawn resistors. Curve10shows that the standard deviation of relative resistance difference increases as the inverse of the square of the area of the resistor increases. In other words, as resistors become smaller, the standard deviation of relative resistance increases, and resistor mismatch increases. It is desirable that curve10have a small slope, ideally zero slope, so that the standard deviation for small resistors is smaller. Since LER may be generally similar regardless of line width, the LER for a particular resistor population on a device is expected to have a greater effect on the standard deviation for resistors having a smaller line width than resistors having a larger line width. Thus, decreasing the LER would be expected to reduce the slope of the best fit line to the standard deviation data, indicating less sensitivity to LER across the range of resistor line widths in the sample population. While the reduction of LER may be particularly beneficial for reducing variation between nominally matched resistors formed in close proximity in a semiconductor device, reduced LER is also expected to be beneficial for reducing departure of non-adjacent resistors (e.g., those positioned on opposite sides of the same chip) from nominal design values, the reduction expected from lower LER achieved via the tri-layer (SADP) approach described herein.

FIG.2Ais a perspective view of one resistor line portion in accordance with an example. Resistance (R) is inversely proportional to the cross-sectional area (A) of a material in accordance with the formula: R=ρL/A (where R is the resistance of the material, ρ is the resistivity of the material, L is the length of the material, and A is the cross-sectional area of the material).FIG.2Aillustrates this relationship (and the corresponding dimensions via a perspective view) for resistor TFR1shown inFIG.2B. With reference toFIG.2B, making edge15of resistor TFR1and edge16of resistor TFR2as smooth as possible (i.e., by achieving a lower LER), improves mismatch. A higher degree of LER along the edges of the resistors results in worse mismatch because the variation in the corresponding cross-sectional areas A along the length of the resistors is higher, and may be different for the resistor TFR1than for the resistor TFR2. With worse mismatch, the potential difference in resistances between resistors TFR1and TFR2becomes larger. Such variation may result in deviations of circuit functionality from the ideal (design) case and may limit the accuracy and/or precision of the circuit functionality.

Examples described herein provide innovative manufacturing techniques that results are expected to result in lower LER of conductive lines, such as those used in TFRs or other components, thereby resulting in a lower mismatch characteristic. While such examples may be expected to provide a reduction of line-edge roughness and improved matching of nominally identical devices, no particular result is a requirement of the present invention unless explicitly recited in a particular claim.

FIG.3is a flowchart illustrating a method300, e.g. a self-aligned double pattern (SADP) method, for manufacturing passive circuit components such as TFRs as exemplified by the resistors TFR1and TFR2shown inFIG.2B, in accordance with various examples.FIGS.4A-41are cross-sectional views of an example process at various stages of manufacturing, consistent with the steps of the method300shown inFIG.3.FIGS.5A-5Fare plan views of an example process consistent withFIGS.4A-41. Methods consistent withFIGS.3,4A-41and5A-5Fare expected to reduce etch-induced line width variation resulting in reduced LER, or smoother and more uniform resistor sides.

Method300includes forming an underlayer on a substrate (block302).FIG.4Ashows a corresponding example including forming an underlayer32above a conductive or resistive material layer30. The material layer30is formed over a semiconductor substrate20, possibly with intervening layers including, e.g. a dielectric isolation layer. Forming the underlayer may be performed via, for example, spin coating of a cross-linking polymer. The material layer30may comprise any suitable material, for example and without limitation, NimCrnor a composite of SixCyCrzand alloys thereof, wherein m, n, x, y and z may depend on specific needs and applications. More specific examples include nichrome (NiCr), silicon-chromium (SiCr), and silicon-silicon carbide-chromium (SiCCr). In some examples the material layer30is formed by physical vapor deposition (PVD) using a composite target that includes appropriate elemental concentrations to result in the desired layer composition.

Method300also includes forming a hard mask above the underlayer (block304).FIG.4Aalso shows a corresponding example including forming a hard mask34above the underlayer32. In this step, a silicon-containing polymer may be spin-coated onto the underlayer32. The silicon-containing polymer may include, for example, poly(dimethylsilioxane), and may be used according to manufacturer's specifications. In some examples the hard mask34may be photo-definable, while in other example the hard mask34may be patterned using an additional photo-definable layer.

Method300shows an example in which the hard mask34is patterned using a photoresist layer (block306) to form a hard mask line.FIG.4Ashows a corresponding example including patterning a photoresist layer36above the hard mask34. The photoresist36may be a photo-definable carbon-based polymer, such as a photoresist or BARC (bottom anti-reflective coating). In some examples, the photoresist36and the hard mask34have a different etch rate in a plasma-based etch process such that the etch selectively etches the photoresist36.

Method300further includes illuminating the photoresist layer36using a mask (block308).FIG.4Afurther shows a corresponding example including forming a mask38above the photoresist36to selectively expose the photoresist36to UV light. Such a process may be implemented on a stepper or scanner. Not shown, the exposed photoresist36is developed, or partially removed by a solvent, to remove exposed photoresist36if the photoresist is a positive resist, or to remove unexposed photoresist36if the photoresist36is a negative resist.

Method300further includes transferring the photoresist pattern into the hard mask using the patterned photoresist (block310). Not shown, an etch process such an CF4/O2plasma may be used to remove portions of the hard mask layer34unprotected by the photoresist36pattern. Such a plasma may preferable selectively remove the exposed hard mask34, preserving the patterned photoresist36pattern for the duration of the process. Alternatively, in some examples the photoresist36may be omitted and the hard mask34may be directly patterned using the mask38and light exposure.FIGS.4B and5Afurther show a corresponding example including patterned hard mask34a(e.g., the hard mask line, sacrificial layer pattern, or sacrificial hard mask layer pattern) after either method.

Method300further includes depositing a dielectric layer, e.g. a silicon oxide layer, on exposed surfaces of the hard mask and the underlayer (block312).FIG.4Cshows a corresponding example including a deposited dielectric layer such as silicon oxide layer40(shown also inFIG.5B) on exposed surfaces of the patterned hard mask34aand the underlayer32. In this step, the depositing may be performed via, for example, atomic layer vacuum depositing. This process may result in a uniform and conformal layer of silicon oxide on the patterned hard mask34a.

Method300further includes removing the silicon oxide on horizontal surfaces, such as above the patterned hard mask and a portion of the oxide above the underlayer, to form sidewall spacers (block314).FIGS.4D and5Cshow a corresponding example after partial removal (e.g., anisotropically) of the silicon oxide layer40, leaving sidewall dielectric (or oxide) spacers40aformed on sidewalls of the patterned hard mask34a, including hard mask lines. In this step, removal of the silicon oxide may be performed via, for example, isotropic-type reactive-ion etching (RIE). In this example, the material layer30is formed over a dielectric layer25which may be referred to as an isolation layer. The dielectric layer25is formed over semiconductor substrate20, and may be or include, for example, shallow trench isolation (STI) or local oxidation of silicon (LOCOS).

Method300further includes removing the patterned hard mask between the spacers (block316) to form a spacer pattern or spacer line pattern.FIGS.4E and5Dshow a corresponding example after the patterned hard mask34ahas been removed between the spacers40a. In this step, the removing of the patterned hard mask between the spacers may be performed via, for example, another RIE process.

Method300further includes forming a block mask having a block mask pattern above and between at least two adjacent spacers, and which is above a portion of the underlayer32(block318).FIGS.4F and5Eshow a corresponding example including a block mask50above and between at least two adjacent spacers40a, and which is above a portion of the underlayer32. In this step, the block mask may be formed (not shown) by spin-coating a photoresist layer and patterning the photoresist layer with a suitable mask using photolithography.

Method300further includes removing part of the underlayer32in regions unprotected by the block mask formed above (block320).FIG.4Gshows a corresponding example after removing part of the underlayer32and any overlying spacers40a, in regions unprotected by a block mask50. In this step, the removing may be performed via, for example, reactive ion etching or other wet or dry etch. Portions of the resistive material layer30outside of the block mask50perimeter may also be removed, exposing the dielectric layer25. As shown inFIG.5E, the block mask50protects one or more portions of the spacers40aand the underlayer32, while leaving exposed other portions of the spacers40aand the underlayer32. The protected portion of the spacers40amay define a pattern related to a passive component, e.g. a serpentine resistor. The exposed portions of the spacers40aare those that are removed to result in the desired pattern of the passive component. Thus definition of the spacers40ain the pattern of the passive device may use two masking levels, including patterning the hard mask34aand the block mask50.

Method300further includes removing the block mask50, portions of the underlayer32unprotected by the spacers40a, and portions of the material layer30unprotected by the spacers40a(block322).FIG.4Hshows a corresponding example including after removing the block mask50and that portion of the underlayer32and material layer30unprotected by the spacers40a, resulting in resistive lines30a. In this step, the removing of the block mask50, underlayer32, and material layer30may be performed via, for example, one or more bath processes appropriate to the material used. A combined stack of a resistive line30a, a remaining portion32aof the underlayer32, and a spacer40ais illustrative of the SADP technique, in which the remaining portion32ais defined by two patterning levels. An etch process that implements the SADP technique may be referred to as an “SADP etch”.

Method300further includes removing the spacers40aand portions32aof the underlayer32below the spacers40a(block324) to form the device or passive circuit component.FIG.4Ishows a corresponding example after removing the two adjacent spacers40aand remaining portions32aof the underlayer32below the adjacent spacers40a. In this step, the removing of the spacers40aand underlayer32may be performed via, for example, wet and/or dry etching. As also shown inFIG.5F, the resultant example patterned material layer30(or conductive pattern) forms resistive lines30a(from which the devices or passive circuit components are formed) thereby remain on the dielectric layer25.FIG.4Iis a view of a cross-sectional area of two resistive lines (see, for example,FIG.2B), with the length (long axis, or current-carrying direction) of the resistors extending into the page. The resistive lines30amay be portions of a serpentine resistor or other resistor pattern, and are expected to have low LER due to forming the silicon oxide layer40with precisely-controlled atomic layer vacuum depositing. As mentioned above, the patterning and etch processes involved in the SADP process reduce etch-induced line width variation and etch selectivity requirements in order to achieve reduced LER, resulting in smoother and more uniform resistor-to-resistor side edges.

Example implementations consistent with the disclosure are expected to provide conductive or resistive lines having an LER significantly less than such lines in baseline devices. In a non-limiting example, the LER is expected to be about 1.5 nm for the resistive lines30a. Furthermore, the SADP technique may provide conductive or resistive lines having a width on the order of 10 nm, e.g. about 12.5 nm. Such features produced at such dimensions may provide, e.g. reduced resistor size for a same resistance as a similar resistor with larger line width. But such small line widths may have excessive LER when formed by other than an SADP process.

FIG.6shows an integrated circuit600including a completed TFR615and a transistor610connected by vias and a metal interconnect650. The TFR615is within the scope of previously described examples (see, for example, resistor30a) and is on or over a dielectric isolation layer605(see, for example, dielectric layer25previously described) which could be STI as shown, or could be LOCOS. The dielectric isolation layer605is on or over semiconductor substrate601(see, for example, semiconductor substrate20previously described) which may be p-type or n-type. The semiconductor substrate601in some examples is a doped well region over a bulk substrate such as a semiconductor wafer or singulated die.

The transistor610is also on or over the semiconductor substrate601. The example transistor610is a MOS transistor, while other examples may provide a bipolar transistor. The transistor610includes a source region620and a drain region625, which are p-type or n-type, but are opposite of the conductivity type of the semiconductor substrate301. The transistor610also includes a gate electrode630(e.g., polysilicon) and a gate dielectric (not shown). The metal interconnect650may be a line or trace (e.g., aluminum (Al) or copper (Cu)) and electrically connects the TFR615to the transistor610by metal contacts645(e.g., tungsten (W)) within a pre-metal dielectric (PMD)635which, for example, includes silicon oxide. The metal interconnect650is may be positioned within an intra-metal dielectric (IMD)640which, for example, includes silicon oxide.

Unless otherwise stated, “about,” “approximately,” or “substantially” preceding a value means +/−10 percent of the stated value. Modifications are possible in the described examples, and other examples are possible within the scope of the claims.