Semiconductor device with a solder creep-up prevention zone

The present invention provides a semiconductor device which includes a U-shaped metal package base, and a semiconductor chip having at least surface electrodes and being mounted on the inner bottom portion of the U-shaped metal package base, wherein the metal package base has, in a portion thereof ranging from the opened side end portion of the inner side wall to the semiconductor chip, a creep-up preventive zone preventing solder entering from the opened side end portion from creeping up. The device makes it possible to solve problems which have been apprehended for conventional semiconductor devices configured as mounting a semiconductor chip on a small semiconductor package, in that reduction in distance between external terminal portions of the metal package and the semiconductor chip results in contact of a solder for mounting with the semiconductor chip to thereby adversely affect the electrical properties and reliability thereof, and in that resin filling or partial plating for avoiding intrusion of the solder raises the cost.

This application is based on Japanese patent application No. 2004-016772 the content of which is incorporated hereinto by reference.

DISCLOSURE OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device, and in particular to a semiconductor device having a package structure having a size close to chip size, and an excellent heat radiation property.

2. Related Art

Recent demands on higher integration of electronic circuits having semiconductor devices incorporated therein raise another demand on down-sizing of packages of the individual semiconductor devices. Chip-size package (CSP) has been proposed as a semiconductor device successfully reduced in the package size.

U.S. Patent Publication No. 2001/0048116 discloses an exemplary case.FIG. 6shows a plan view of the semiconductor device disclosed in the U.S. Patent Publication No. 2001/0048116, andFIG. 7shows a vertical sectional view of the device. As shown in these drawings, the conventional semiconductor device is configured by mounting a semiconductor chip30in a recessed portion of a dish-formed metal plate100, wherein the dish-formed metal plate100is formed by processing a metal plate having a size slightly larger than that of the semiconductor chip. The semiconductor chip30is exemplified by a MOS transistor chip, and has a drain electrode formed on the back surface thereof. The drain electrode is directly fixed onto a bottom surface101of the recessed portion using a resin102, and the semiconductor chip30is molded by filling the resin102also in the recessed portion therearound. The semiconductor chip30has also a gate electrode37and a source electrode40formed on the surface thereof, so as to be aligned nearly in the same plane with the upper surface of the peripheral portion of the metal plate100. A plurality of areas on the upper surface of the peripheral portion of the metal plate100are configured as drain connection electrodes105. By mounting thus-configured semiconductor device onto a mounting substrate, not shown, in a face-down manner, the drain connection electrodes105are connected with pad portions for the drain connection electrodes, provided on the mounting substrate, and at the same time, the gate electrode37and the source electrode40are respectively connected to the individual pad portions provided therefor.

The semiconductor device was, however, found to have a latent problem as described below, from investigations by the present inventor. The surface of the semiconductor chip30and the upper surface of the peripheral portion of the metal plate100in the conventional semiconductor device are aligned nearly in the same plane, so that, in a process of attaching the semiconductor device onto a mounting substrate using a solder, the solder fed in a large amount to the drain connection electrodes105may run out from the drain connection electrodes105and creep up on the inner wall of the metal plate100, and may flow to reach the boundary with an adhesive resin103, and may produce a solder puddle inside the metal plate100. In order to prevent the solder from contacting with the end portion of the semiconductor chip30, it is necessary to ensure a reasonable width for the adhesive resin103. The side face of the semiconductor chip30and the side wall of the metal plate100are therefore spaced by a relatively large gap, so as to avoid contact of the crept solder with the end portion or side face portion of the semiconductor chip30, so that two-dimensional outer dimension of the metal plate100is set considerably larger than two-dimensional dimension of the semiconductor chip30. The side face of the semiconductor chip30and the side wall of the metal plate100are spaced typically by 0.5 mm or around, and the side space of the semiconductor chip is filled with the conductive resin102, and thereon the adhesive resin103is filled.

The conventional semiconductor device has a large distance between the external terminal portions of the metal plate and the semiconductor chip as described in the above, so that the size of the semiconductor device as a whole becomes larger than expected from the semiconductor chip. Shrinkage of the distance may sometimes result in contact of the solder, used for bonding in the mounting process, with the semiconductor chip, and this adversely affects the electrical characteristics and reliability. For the case where the resin filling or partial plating for the purpose of preventing the solder intrusion is not provided, the solder creeps up to a large degree and this varies amount of solder contributable to the connection, so that reliability in the connection may be less reliable, and nonconformities may occur in the environment of use. The filling of the resin into the side space of the semiconductor chip demands additional costs for the resin material and operations for the injection and curing, and this makes the device expensive. The operations become more difficult in terms of constant-volume supply of the resin and positional alignment for the injection as the space becomes smaller, and are inappropriate for small-sized devices. The partial plating additionally demands a mask and a photolithographic system allowing the selective plating, and this makes the device expensive, and cannot downsize the device because a redundant design is essential from a viewpoint of accuracy.

It is therefore an object of the present invention to provide a semiconductor device in a form of small semiconductor package in which a semiconductor chip is not molded by a resin, which is inexpensive, allows further down-sizing, and ensures a high reliability in the mounting, without partially plating the semiconductor package.

SUMMARY OF THE INVENTION

According to the present invention, there is provided a semiconductor device which comprises a U-shaped metal package base, and a semiconductor chip having at least surface electrodes and being mounted on the inner bottom portion of the U-shaped metal package base, wherein the metal package base has, in a portion thereof ranging from the opened side end portion of the inner side wall to the semiconductor chip, a creep-up preventive zone preventing solder entering from the opened side end portion from creeping up.

In other words, the present invention provides a semiconductor device which comprises a U-shaped metal package base, and a semiconductor chip having at least surface electrodes and being mounted on the inner bottom portion of the U-shaped metal package base, wherein a level of the end position of the U-shaped metal package base is set higher than the surface level of the semiconductor chip, and the metal package base has, in a portion thereof ranging from the surface position to the end position, a creep-up preventive zone preventing solder from creeping up.

The metal package base, herein, preferably has a groove carved thereon at the position of the creep-up preventive zone. The groove may be provided in the direction in parallel with the surface of the semiconductor chip.

It is also allowable that the groove is provided in the direction normal to the surface of the semiconductor chip, so as to reach the opened side end portion.

It is also allowable that the metal package base has an insulating resin zone provided thereon at the position of the creep-up preventive zone. It is still also allowable that the metal package base has a plated film formed thereon, but has no plated film at the position of the creep-up preventive zone.

The semiconductor chip preferably has, as being formed on the surface electrode, solder bumps or solder balls having an almost equal height with that of the opened side end portion.

As has been described in the above, by providing the external terminal portions as the electrodes at the opened side end portion of the metal package base processed into a U-shape, and by providing the solder creep-up preventive zone, the present invention can successfully prevent the solder from creeping from the external terminal portions up to the semiconductor chip side, and from entering the side space of the semiconductor chip, and this allows a design in which the distance between the inner wall surface of the metal package base and the side face of the semiconductor chip is set to as close as 0.10 mm or below. The solder for mounting is prevented from contacting with the side faces or surface edge portions of the semiconductor chip, and this is successful in preventing nonconformities in the electrical characteristics, and nonconformities caused by mechanical force. It is also made possible to suppress variation in spreading of the solder, so that solder geometry at the connected portions can be stabilized, and this is further successful in stabilizing reliability of the connection, and making nonconformities after the mounting less likely to occur.

DETAILED DESCRIPTION OF THE INVENTION

The following paragraphs will describe the embodiments of the present invention referring to the attached drawings.FIG. 1shows a structure of a semiconductor device according to a first embodiment of the present invention, and is a perspective view of a semiconductor device having a semiconductor chip mounted on a small-sized semiconductor package, without being molded on the outer periphery thereof with a resin.

A U-shaped metal package base1is composed of copper, copper alloy or the like, and has external terminal portions6as electrodes at the end position of the opened side end portions of the U-shaped metal package base1. The first embodiment shows four electrodes, wherein a single electrode is also allowable. On the bottom portion inside the U-shaped metal package base1, a semiconductor chip2is fixed using a conductive paste3, for example.

This way of fixation of the semiconductor chip2on the bottom portion inside the U-shaped metal package base1makes it possible to ensure a desirable electrical connection between the semiconductor chip2and metal package base1. It is, therefore, also allowable to form a plated layer4, such as an Ag plated layer, on the inner surface, and to form the plated layer4further on the entire surface of the external terminal portions6including the outer surface thereof, to thereby ensure a necessary level of soldering property.

On the surface of the semiconductor chip2, there are formed surface electrodes5for soldering respectively having a solder bump, or solder balls as the surface electrodes5. By aligning the end portions (14) of the external terminal portions6and the top surface of the solder bumps as the surface electrodes5nearly in the same plane, or locating them within a height difference of 50 μm or less, it is made possible to collectively solder these electrodes in the process of mounting the semiconductor device onto the mounting substrate, and to connect electrodes on the back surface of the semiconductor chip2to the external through the external terminal portions6, and to connect the surface electrodes5of the semiconductor chip2to the external through the solder bumps.

In the portion ranging from the opened side end portion of the inner side wall of the metal package base1to the semiconductor chip2, there is provided a creep-up preventive zone preventing solder entering from the opened side end portion from creeping up.

That is, inFIG. 1, the external terminal portions6located at the end position of the U-shaped metal package base are configured as having the level higher than that of the surface of the semiconductor chip2, and as having, on the inner side wall of the of the U-shaped metal package base1, the creep-up preventive zone between the surface position of the semiconductor chip2and the end position of the external terminal portions6, wherein the solder creep-up preventive zone is configured by providing a groove, or by covering with a resin. In the first embodiment, horizontal grooves7are formed as the solder creep-up preventive zone, in parallel with the surface of the semiconductor chip2, wherein the grooves7are formed at a level almost equivalent to the surface level of the fixed semiconductor chip2, or at a position more closer to the external terminal portions6.

FIG. 2Ashows an enlarged sectional view including a portion of the groove7. The surface of the metal package base1is covered with the plated layer4, but it is also allowable to remove the plated layer4from the portion of the groove7. Metal package base1will be plated after being shaped by pressing, etching or the like, wherein scratching made on the surface of the plated layer4results in removal of the plated layer4and makes the plated surface discontinuous, and the groove7will consequently be formed.

FIG. 3Ais a sectional view of the semiconductor device of the first embodiment mounted on a mounting substrate10, showing an exemplary case using a solder for mounting. When the substrate copper foil pattern11provided on the mounting substrate10and the external terminal portions6are connected using a solder9, the solder9melts under heating, and the molten solder creeps up from the end portions14of the external terminal portions6towards the direction of mounting of the semiconductor chip2. The groove7functions as a discontinuous portion capable of blocking the spreading of the solder9if the plated layer4is preliminarily removed therefrom, and can limit the creep-up of the solder9on this side of the groove7. This successfully prevents the solder9for mounting from entering the side space of the semiconductor chip2as shown inFIG. 3A. It is therefore made possible to avoid any electrical nonconformities caused by the solder9contacting with the side faces or surface edge portions of the semiconductor chip2, and any nonconformities ascribable to mechanical force. This consequently makes it possible to design the distance between the metal package base1and the side face of the semiconductor chip2shorter than that in the conventional case, or to make them closer with a distance typically as short as of 0.10 mm or less, and more specifically, the distance can be reduced to as short as 0.05 mm. It is also successful in suppressing variation in the spreading of the solder9, and this makes it possible to stabilize geometry of the solder9at the connection portion, to consequently stabilize reliability of the connection, and to make any nonconformities after the mounting less likely to occur.

FIG. 2Bshows a second embodiment, in which a groove12is formed by pressing, etching or the like, at the time when the metal package base1is shaped, and the plated layer4is then formed by plating on the inner wall of the groove, wherein the groove has a width and a depth larger than those in the first embodiment. The groove12is formed, similarly to as described in the first embodiment, on the inner surface of the external connection portions6in the horizontal direction in parallel with the surface of the semiconductor chip2(that is, in the direction normal to the sheet ofFIG. 2B), wherein the lower edge of the groove12is formed so as to be aligned at an almost equal level of height with the surface level of the semiconductor chip, or so as to be more closer to the external terminal portions6.FIG. 3Bis a partial sectional view of the semiconductor devices mounted on the mounting substrates according to the second embodiment. In this configuration, the solder9may flow into the groove12, but is limited from flowing out from the groove12by ensuring a sufficiently large capacity of the groove12as compared with volume of the solder9. The groove12can, therefore, function as a discontinuous portion preventing the spreading of the solder9as shown inFIG. 3B, and can limit thereat the creep-up of the solder9.

FIG. 2Cshows a third embodiment, in which an insulating resin zone8is formed as a discontinuous portion blocking the spreading of the solder9. The insulating resin zone8is formed on the inner surface of the external terminal portions6in horizontal direction in parallel with the surface of the semiconductor chip2(that is, the direction normal to the sheet ofFIG. 2C), so that any portion of the insulating resin zone8reaches a level almost equivalent to the surface level of the semiconductor chip2. The insulating resin zone8can be formed by transferring or coating an ink mainly containing a heat-resistant resin such as epoxy resin, followed by and curing through drying, heating or UV irradiation. In this configuration, the solder9is successfully limited from flowing out from the insulating resin zone8, and similarly to as described in the first embodiment, the insulating resin zone8functions as the discontinuous portion capable of blocking the spreading of the solder9, and can limit the creep-up of the solder9at the portion of the insulating resin zone8. It is also allowable to combine the insulating resin zone8with the groove similarly to as described in the above, so as to suppress blurring of the insulating resin zone8(or, intrusion of the solder around the semiconductor chip2).

FIG. 4shows a fourth embodiment, in which a vertical groove13is formed on the inner surface of each of the external terminal portions6, wherein the groove13is formed so as to rise up from a level almost equivalent to the surface level of the semiconductor chip2to reach the end portion14in the direction normal to the surface of the semiconductor chip2.FIG. 5is a sectional view of a mounted state of the semiconductor device of the fourth embodiment. In this configuration, the solder9may flow into the groove13, but can be limited from flowing out therefrom by ensuring a capacity of the groove13sufficiently larger than the volume of the solder9. The groove13can therefore function as the discontinuous portion capable of blocking the spreading of the solder9, and can limit the creep-up of the solder9at the portion of the groove13.

The above-described embodiments have described the exemplary cases where the present invention was applied MOSFET, but the present invention can similarly be applied also to semiconductor devices having, incorporated therein, any other semiconductor chips such as bipolar transistor, diode and IC.

It is apparent that the present invention is not limited to the above embodiments, that may be modified and changed without departing from the scope and spirit of the invention.