Semiconductor device with higher breakdown voltage and electronic apparatus

A semiconductor device including a first conductivity-type layer into which first conductivity-type impurities are introduced, a second conductivity-type layer into which second conductivity-type impurities are introduced, the second conductivity-type impurities being different in polarity from the first conductivity-type impurities, and an intermediate layer that is sandwiched between the first conductivity-type layer and the second conductivity-type layer, and does not include the first conductivity-type impurities or the second conductivity-type impurities, or includes the first conductivity-type impurities or the second conductivity-type impurities at a concentration lower than a concentration of the first conductivity-type impurities in the first conductivity-type layer or the second conductivity-type impurities in the second conductivity-type layer, the first conductivity-type layer, the intermediate layer, and the second conductivity-type layer being stacked in a thickness direction of a semiconductor substrate inside the semiconductor substrate.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a U.S. National Phase of International Patent Application No. PCT/JP2018/026529 filed on Jul. 13, 2018, which claims priority benefit of Japanese Patent Application No. JP 2017-165619 filed in the Japan Patent Office on Aug. 30, 2017. Each of the above-referenced applications is hereby incorporated herein by reference in its entirety.

TECHNICAL FIELD

The present disclosure relates to a semiconductor device and an electronic apparatus.

BACKGROUND ART

In recent years, in semiconductor devices to be used in the IoT (Internet of Things) field and the automotive field, voltages of power supplies have become higher. Therefore, in such semiconductor devices, it is desired to withstand a higher surge voltage for a withstand voltage element that is provided in an input/output section (called also an I/O section) or the like to protect an internal circuit.

For example, as a typical withstand voltage element, a PN-junction diode in which a P-type semiconductor and an N-type semiconductor are joined is known. However, the PN-junction diode has a low breakdown voltage, which causes a difficulty in application to the withstand voltage element that is desired to have high withstand voltage performance as described above.

Here, as the withstand voltage element having high withstand voltage performance, for example, as disclosed in the following PTL 1, a diode having a PIN (P-Intrinsic-N) structure is proposed. In the PIN structure, a P-type semiconductor and an N-type semiconductor are joined with a low-dose intermediate layer interposed therebetween. In the diode having the PIN structure, a depletion layer is formed between the low-dose intermediate layer and each of the P-type semiconductor and the N-type semiconductor; therefore, an electric field between the P-type semiconductor and the N-type semiconductor is relaxed by the formed depletion layer. This allows the diode having the PIN structure to achieve a higher breakdown voltage than the PN-junction diode, which makes it possible to apply the diode having the PIN structure to the withstand voltage element having higher withstand voltage performance.

CITATION LIST

Patent Literature

SUMMARY OF THE INVENTION

Problems to be Solved by the Invention

However, in the withstand voltage element disclosed in PTL 1, the PIN structure is formed in an in-plane direction of a semiconductor substrate, which causes an occupancy area of the withstand voltage element to become large. Accordingly, the withstand voltage element is not suitable for microfabrication of a semiconductor device. In particular, in a case where the withstand voltage element is provided for each input/output section, the withstand voltage element having a large occupancy area places a constraint on reduction in chip size of a semiconductor device.

Further, to make a breakdown voltage higher in the diode having the PIN structure, it is necessary to further increase a width of the depletion layer that is formed between the P-type semiconductor and the N-type semiconductor. Accordingly, the withstand voltage element that is desired to have higher withstand voltage performance has a larger occupancy area, which has raised a possibility of an increase in size of a semiconductor device.

Accordingly, a semiconductor device has been desired that is allowed to withstand a higher voltage while having a more efficient occupancy area.

Means for Solving the Problems

According to the present disclosure, there is provided a semiconductor device including: a first conductivity-type layer into which first conductivity-type impurities are introduced; a second conductivity-type layer into which second conductivity-type impurities are introduced, the second conductivity-type impurities being different in polarity from the first conductivity-type impurities; and an intermediate layer that is sandwiched between the first conductivity-type layer and the second conductivity-type layer, and does not include the first conductivity-type impurities or the second conductivity-type impurities, or includes the first conductivity-type impurities or the second conductivity-type impurities at a concentration lower than a concentration of the first conductivity-type impurities in the first conductivity-type layer or the second conductivity-type impurities in the second conductivity-type layer, the first conductivity-type layer, the intermediate layer, and the second conductivity-type layer being stacked in a thickness direction of a semiconductor substrate inside the semiconductor substrate.

Further, according to the present disclosure, there is provided an electronic apparatus provided with a semiconductor device that is provided inside a semiconductor substrate, the semiconductor device including: a first conductivity-type layer into which first conductivity-type impurities are introduced; a second conductivity-type layer into which second conductivity-type impurities are introduced, the second conductivity-type impurities being different in polarity from the first conductivity-type impurities; and an intermediate layer that is sandwiched between the first conductivity-type layer and the second conductivity-type layer, and does not include the first conductivity-type impurities or the second conductivity-type impurities, or includes the first conductivity-type impurities or the second conductivity-type impurities at a concentration lower than a concentration of the first conductivity-type impurities in the first conductivity-type layer or the second conductivity-type impurities in the second conductivity-type layer, the first conductivity-type layer, the intermediate layer, and the second conductivity-type layer being stacked in a thickness direction of a semiconductor substrate inside the semiconductor substrate.

According to the present disclosure, it is possible to form a PIN structure that includes, in a stacking direction, the first conductivity-type layer including the first conductivity-type impurities, the intermediate layer that does not include conductivity-type impurities or includes the conductivity-type impurities at a low concentration, and the second conductivity-type layer including the second conductivity-type impurities.

Effects of the Invention

As described above, according to the present disclosure, it is possible to provide a semiconductor device that is allowed to withstand a higher voltage while having a more efficient occupancy area.

It is to be noted that the above-described effects are not necessarily limitative. Any of the effects indicated in this description or other effects that may be understood from this description may be exerted in addition to the above-described effects or in place of the above-described effects.

MODES FOR CARRYING OUT THE INVENTION

Hereinafter, preferred embodiments of the present disclosure will be described in detail with reference to the attached drawings. It is to be noted that, in the present specification and drawings, component parts having substantially the same functional configurations are denoted with the same reference numerals, and description thereof is not repeated.

It is to be noted that description is given in the following order.

1. Configuration of Semiconductor Device

2. Application Examples of Semiconductor Device

2.1. Application Examples to Single-Layer Semiconductor Device

2.2. Application Examples to Multi-Layer Semiconductor Device

3. Method of Manufacturing Semiconductor Device

3.1. First Manufacturing Method

3.2. Second Manufacturing Method

3.3. Third Manufacturing Method

4. Electronic Apparatus

1. CONFIGURATION OF SEMICONDUCTOR DEVICE

First, a configuration of a semiconductor device according to an embodiment of the present disclosure is described with reference toFIG. 1.FIG. 1is a perspective view for describing a configuration of a semiconductor device100according to the present embodiment.

As illustrated inFIG. 1, the semiconductor device100includes a first conductivity-type layer111, an intermediate layer113, and a second conductivity-type layer115. Further, a circumferential side surface of the semiconductor device100may be covered with a separating layer120for electrical insulation purpose.

The first conductivity-type layer111includes a semiconductor material into which first conductivity-type impurities are introduced. Specifically, the first conductivity-type layer111may include silicon (Si) into which an n-type impurities such as phosphorus (P) or arsenic (As) are introduced. For example, the first conductivity-type layer111may be formed as a silicon layer into which the n-type impurities are introduced at a concentration within a range of 1.0×1016pieces/cm3to 1.0×1019pieces/cm3using an ion implantation method or the like.

The second conductivity-type layer115includes a semiconductor material into which second conductivity-type impurities are introduced. Specifically, the second conductivity-type layer115may include silicon (Si) into which p-type impurities such as boron (B) or aluminum (Al) are introduced. For example, the second conductivity-type layer115may be formed as a silicon layer into which the p-type impurities are introduced at a concentration within a range of 1.0×1016pieces/cm3to 1.0×1019pieces/cm3using the ion implantation method or the like.

In the semiconductor device100according to the present embodiment, the first conductivity-type impurities and the second conductivity-type impurities represent conductivity-type impurities that are different in polarity from each other. Therefore, as exemplified in the above, in a case where the first conductivity-type impurities are n-type impurities, the second conductivity-type impurities are p-type impurities. On the contrary, in a case where the first conductivity-type impurities are p-type impurities, the second conductivity-type impurities are n-type impurities.

The intermediate layer113is provided to be sandwiched in a stacking direction between the first conductivity-type layer111and the second conductivity-type layer115. The intermediate layer113includes a semiconductor material that does not include conductivity-type impurities, or a semiconductor material that includes conductivity-type impurities at a concentration lower than a concentration of conductivity-type impurities in the first conductivity-type layer111or the second conductivity-type layer115.

Specifically, the intermediate layer113may be a silicon layer that does not include the p-type impurities or the n-type impurities, or a silicon layer that includes the p-type impurities or the n-type impurities at a concentration lower than a concentration of the p-type impurities in the first conductivity-type layer111or n-type impurities in the second conductivity-type layer115. For example, the intermediate layer113may be formed as a silicon layer into which the n-type impurities are introduced at a concentration within a range of 1.0×1014pieces/cm3to 1.0×1015pieces/cm3using the ion implantation method or the like. It is to be noted that the intermediate layer113is a layer characterized by a lower doping concentration of the p-type impurities or the n-type impurities as compared with the first conductivity-type layer111and the second conductivity-type layer115, and it is not specifically limitative whether or not the intermediate layer113includes the p-type impurities or the n-type impurities.

Each of the first conductivity-type layer111, the intermediate layer113, and the second conductivity-type layer115as described above includes a semiconductor material, and these layers are different in any one or more of presence or absence, a type, and a concentration of the conductivity-type impurities included in the semiconductor material. Therefore, the first conductivity-type layer111, the intermediate layer113, and the second conductivity-type layer115may include the same semiconductor material. For example, each of the first conductivity-type layer111, the intermediate layer113, and the second conductivity-type layer115may include silicon.

However, it goes without saying that the first conductivity-type layer111, the intermediate layer113, and the second conductivity-type layer115may include a semiconductor material other than silicon. For example, the first conductivity-type layer111, the intermediate layer113, and the second conductivity-type layer115may include another elemental semiconductor such as germanium (Ge), or a compound semiconductor such as gallium arsenide (GaAs), gallium nitride (GaN), or silicon carbide (SiC).

The separating layer120is provided using an insulating material to surround a side surface of a stacking body of the first conductivity-type layer111, the intermediate layer113, and the second conductivity-type layer115. For example, the separating layer120may be provided using the insulating material such as silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiON). The separating layer120allows a leakage current from the semiconductor device100to be suppressed by forming an electrically insulating layer on the side surface of the stacking body of the first conductivity-type layer111, the intermediate layer113, and the second conductivity-type layer115.

In the stacking body including the first conductivity-type layer111, the intermediate layer113, and the second conductivity-type layer115, an upper surface of the second conductivity-type layer115and a lower surface of the first conductivity-type layer111that are opposed to each other in a stacking direction are not covered with the separating layer120, and are exposed. The exposed upper surface of the second conductivity-type layer115and the exposed lower surface of the first conductivity-type layer111function as terminals of the semiconductor device100, and it is possible to electrically couple these terminals to a variety of wiring lines through a via and the like, for example. The exposed upper surface of the second conductivity-type layer115and the exposed lower surface of the first conductivity-type layer111may be doped with high-concentration conductivity-type impurities to reduce contact resistance between the semiconductor device100and the via.

With such configurations, in the semiconductor device100according to the present embodiment, a PIN structure is formed in which a p-type semiconductor and an n-type semiconductor (that is, the first conductivity-type layer111and the second conductivity-type layer115) are joined in the stacking direction with a semiconductor layer (that is, the intermediate layer113) doped at a low concentration or undoped interposed therebetween. In the PIN structure, a depletion layer with an extremely low carrier concentration is formed from the first conductivity-type layer111and the second conductivity-type layer115toward the intermediate layer113. In the semiconductor device100according to the present embodiment, the depletion layer allows for a rise in a breakdown voltage, which makes it possible to ensure high withstand voltage performance.

For example, in a PIN-structure diode, to achieve high withstand voltage performance (for example, more than 20 V) that exceeds withstand voltage performance of a PN-junction diode (for example, about 10 V), it is necessary for the intermediate layer113to have a thickness exceeding several μm. In the semiconductor device100according to the present embodiment, forming the PIN structure in the stacking direction allows for reduction in a planar area occupied by the semiconductor device100, as compared with a case where the PIN structure is formed in a planar direction.

It is to be noted that, in the semiconductor device100, on a surface of the first conductivity-type layer111or the second conductivity-type layer115that is opposed to a surface thereof on which the intermediate layer113is provided, a layer including conductivity-type impurities having different polarity may be provided. Specifically, on a surface of the first conductivity-type layer111that is opposed to a surface thereof on which the intermediate layer113is provided, a layer including the second conductivity-type impurities may be provided. Alternatively, on a surface of the second conductivity-type layer115that is opposed to a surface thereof on which the intermediate layer113is provided, a layer including the first conductivity-type impurities may be provided. In such a case, the semiconductor device100has an NPIN (N-P-Intrinsic-N) structure or a PINP (P-Intrinsic-N-P) structure obtained by replacing a PN-junction of a bipolar transistor having an NPN structure or a PNP structure with a PIN-junction. Such a structure also allows the semiconductor device100to function as a high withstand voltage element.

Next, a more specific configuration of the semiconductor device100according to the present embodiment is described with reference toFIG. 2.FIG. 2is a top view and a cross-sectional view for describing the configuration of the semiconductor device100according to the present embodiment. It is to be noted that, in directly facingFIG. 2, a diagram on the upside is the top view of the semiconductor device100, and a diagram on the downside is the cross-sectional view of the semiconductor device100.

As illustrated inFIG. 2, for example, the semiconductor device100may be provided inside a semiconductor substrate130, and may be electrically insulated from the semiconductor substrate130by the separating layer120.

The semiconductor substrate130is a substrate that includes a semiconductor material. For example, the semiconductor substrate130may be a silicon substrate. In a case where the semiconductor substrate130is a readily processible silicon substrate, it is possible to form the semiconductor device100inside the semiconductor substrate130more easily. However, the semiconductor substrate130may be a substrate that includes another elemental semiconductor such as germanium (Ge), or a substrate that includes a compound semiconductor such as gallium arsenide (GaAs), gallium nitride (GaN), or silicon carbide (SiC).

Further, the semiconductor substrate130may be reduced in thickness by CMP (Chemical Mechanical Polishing) or the like. It is possible to provide the semiconductor device100according to the present embodiment penetrating through the semiconductor substrate130. Therefore, to achieve withstand voltage performance of the semiconductor device100as desired characteristics, the semiconductor substrate130may be reduced in thickness within a range of several μm to several dozen μm to ensure that a thickness of the intermediate layer113falls within a range of several μm to several dozen μm, and may be reduced in thickness within a range of about 2 μm to about 20 μm, for example. A typical semiconductor substrate130available commercially to form a semiconductor device is about several hundred μm in thickness, and thus reduction in thickness down to the above-described range of the semiconductor substrate130makes it possible to more easily form the semiconductor device100that includes the desired characteristics.

As described above, the semiconductor device100is provided to penetrate through the semiconductor substrate130in a stacking structure of the first conductivity-type layer111, the intermediate layer113, and the second conductivity-type layer115. Specifically, it is possible to form the semiconductor device100by introducing predetermined conductivity-type impurities (either the first conductivity-type impurities or the second conductivity-type impurities) into regions in a thickness direction of the semiconductor substrate130that correspond to the first conductivity-type layer111and the second conductivity-type layer115. In other words, in the semiconductor substrate130, a region into which the first conductivity-type impurities are introduced becomes the first conductivity-type layer111, and a region into which the second conductivity-type impurities are introduced becomes the second conductivity-type layer115. Further, a region sandwiched between the above-described first conductivity-type layer111and second conductivity-type layer115in the thickness direction of the semiconductor substrate130becomes the intermediate layer113.

The semiconductor device100is provided to penetrate through the semiconductor substrate130, which makes it possible to expose the first conductivity-type layer111and the second conductivity-type layer115respectively on both respective main surfaces opposed to each other of the semiconductor substrate130. This allows the semiconductor device100to use the exposed first conductivity-type layer111and exposed second conductivity-type layer115as terminals of a PIN-structure diode, which makes it possible to easily form electrical coupling of the semiconductor device100to a variety of wiring lines.

However, the first conductivity-type layer111and the second conductivity-type layer115may not be exposed on both the main surfaces opposed to each other of the semiconductor substrate130from a point of time when such layers are formed. For example, after the first conductivity-type layer111and the second conductivity-type layer115are formed inside the semiconductor substrate130, the first conductivity-type layer111and the second conductivity-type layer115may be exposed on both the main surfaces opposed to each other of the semiconductor substrate130by reducing the semiconductor substrate130in thickness at a subsequent stage.

The separating layer120is provided to penetrate through the semiconductor substrate130and surround a side surface of the semiconductor device100that is provided as the stacking body of the first conductivity-type layer111, the intermediate layer113, and the second conductivity-type layer115. Specifically, it is possible to form the separating layer120by removing the semiconductor substrate130around the semiconductor device100by etching or the like, and thereafter filling a removed region with an insulating material. For example, the separating layer120may be formed by filling an opening of the semiconductor substrate130with the insulating material such as silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiON). In other words, the separating layer120may be formed by a method similar to a so-called STI (Shallow Trench Isolation) method.

Here, the separating layer120may be formed by filling an opening that is formed by etching from the one main surface of the semiconductor substrate130with the insulating material, or may be formed by filling each of openings that are formed by etching from both the main surfaces opposed to each other of the semiconductor substrate130with the insulating material.

It is possible to determine an etching direction at the time of formation of the separating layer120depending on, for example, how a cross-sectional shape of the separating layer120in a thickness direction of the semiconductor substrate130is tapered. Specifically, in a case where the tapered direction of the cross-sectional shape of the separating layer120is the same, it is possible to determine that the separating layer120is formed by etching only from the one main surface of the semiconductor substrate130. In contrast, in a case where the tapered direction of the cross-sectional shape of the separating layer120is reversed halfway, it is possible to determine that the separating layer120is formed by etching each from both the main surfaces opposed to each other of the semiconductor substrate130. In the separating layer120illustrated inFIG. 2, the tapered direction of the cross-sectional shape of the separating layer120is fixed; therefore, it is possible to determine that this separating layer120is formed by etching only from the one main surface of the semiconductor substrate130on the side where the first conductivity-type layer111is provided.

According to the semiconductor device100that has such a configuration, it is possible to provide the PIN structure in the thickness direction of the semiconductor substrate130, which allows for reduction in the planar area occupied by the semiconductor device100, as compared with a case where the PIN structure is provided in an in-plane direction of the semiconductor substrate130. Further, the semiconductor device100is provided to penetrate through the semiconductor substrate130, which makes it possible to easily form electrical coupling to a variety of wiring lines.

2. APPLICATION EXAMPLES OF SEMICONDUCTOR DEVICE

Subsequently, application examples of the semiconductor device100according to the present embodiment are described with reference toFIGS. 3A, 3B, 3C, 4A, 4B, and 4C. Each ofFIGS. 3A, 3B, andFIG. 3Cis a are cross-sectional views of an example in which the semiconductor device100according to the present embodiment is applied to a single-layer semiconductor device. Each ofFIGS. 4A, 4B, and 4Cis a are cross-sectional views of an example in which the semiconductor device100according to the present embodiment is applied to a multi-layer semiconductor device.

(2.1. Application Examples to Single-Layer Semiconductor Device)

First, application examples of the semiconductor device100according to the present embodiment to a single-layer semiconductor device are described with reference to Each ofFIGS. 3A, 3B, and 3C.

As illustrated inFIG. 3A, a single-layer semiconductor device11includes one semiconductor substrate130, and one multi-layer wiring layer140that is formed on the semiconductor substrate130.

The semiconductor substrate130is a silicon substrate that is reduced in thickness within a range of, for example, several μm to several dozen μm (for example, 2 μm to 20 μm). On the semiconductor substrate130, for example, a PIN diode100(that is, the above-described semiconductor device100), a field-effect transistor145, and the like are provided to be isolated by the separating layer120and an element separating layer121.

As described above, the PIN diode100is configured by stacking the first conductivity-type layer111, the intermediate layer113, and the second conductivity-type layer115in the thickness direction of the semiconductor substrate130, and functions as a withstand voltage element. The field-effect transistor145is, for example, a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), and executes signal processing and the like in the single-layer semiconductor device11.

It is to be noted that the field-effect transistor145is an example of an active element and a passive element that are provided on the semiconductor substrate130, and an element provided on the semiconductor substrate130is not limited to the field-effect transistor145. Further, a plurality of other active elements and a plurality of other passive elements may be provided on the semiconductor substrate130.

Each of the separating layer120and the element separating layer121includes, for example, an insulating material such as silicon oxide, and electrically isolates the PIN diode100and the field-effect transistor145from each other to prevent the PIN diode100and the field-effect transistor145from being electrically conducted through the semiconductor substrate130. It is to be noted that, in order to electrically isolate the PIN diode100, the separating layer120is provided to penetrate through the semiconductor substrate130. In contrast, the element separating layer121may not be provided to penetrate through the semiconductor substrate130, and may be provided to a predetermined depth allowing for electrical isolation of the field-effect transistor145.

The multi-layer wiring layer140is provided on the semiconductor substrate130by stacking a plurality of interlayer insulating films143including an insulating material, for example. In addition, for example, a wiring layer142that transmits signals from the PIN diode100, the field-effect transistor145, and the like is provided inside the multi-layer wiring layer140. The wiring layer142is electrically coupled to the PIN diode100, the field-effect transistor145, or the like that are provided on the semiconductor substrate130through a via141provided in a lowermost layer. It is possible for the wiring layer142to take signals from the PIN diode100, the field-effect transistor145, and the like through the via141.

The interlayer insulating film143may include a heretofore known insulating material such as SiO2or SiN, for example. As an alternative, the interlayer insulating film143may include a single kind of insulating material, or may include a plurality of kinds of insulating materials. The wiring layer142may include, for example, a metallic material, such as copper (Cu) or aluminum (Al), that has relatively low resistance to allow for signal transmission at higher speed. The via141may include, for example, a metallic material, such as tungsten (W), that has high opening filling property at the time of forming a film.

The PIN diode100(that is, the above-described semiconductor device100) is applicable as a withstand voltage element to such a single-layer semiconductor device11. The PIN diode100is usable as a withstand voltage protection element that protects an internal circuit against a surge voltage from an external circuit by coupling, to a bump and the like, the first conductivity-type layer111that is exposed on a rear surface of the semiconductor substrate130(that is, a surface opposed to a surface on which the multi-layer wiring layer140is provided).

Next, another example of the single-layer semiconductor device is described with reference toFIG. 3B.

As illustrated inFIG. 3B, a single-layer semiconductor device12includes one semiconductor substrate130, and one multi-layer wiring layer140that is formed on the semiconductor substrate130. On the semiconductor substrate130, for example, a PIN diode100A, the field-effect transistor145, and the like are provided to be isolated by a separating layer120A and the element separating layer121. The PIN diode100A is configured by stacking a first conductivity-type layer111A, an intermediate layer113A, and a second conductivity-type layer115A in the thickness direction of the semiconductor substrate130.

It is to be noted that, in configurations, other than cross-sectional shapes, of the PIN diode100A and the separating layer120A, respective configurations of the single-layer semiconductor device12illustrated inFIG. 3Bare substantially similar to respective configurations of the single-layer semiconductor device11illustrated inFIG. 3A. Therefore, description of these configurations is not repeated here.

The single-layer semiconductor device12illustrated inFIG. 3Bis different in only the cross-sectional shapes of the PIN diode100A and the separating layer120A as compared with the single-layer semiconductor device11illustrated inFIG. 3A. Specifically, in the single-layer semiconductor device12illustrated inFIG. 3B, the cross-sectional shapes of the PIN diode100A and the separating layer120A are hexagonal shapes in which a tapered direction is reversed halfway. In contrast, in the single-layer semiconductor device11illustrated inFIG. 3A, the cross-sectional shapes of the PIN diode100and the separating layer120are trapezoidal shapes that are tapered in one direction.

Such a difference in the cross-sectional shape of the separating layer120A is possibly made by a difference in a process of forming the separating layer120A. Specifically, in a case where an opening with a high aspect ratio is formed by etching, the thus-formed opening has a reverse-tapered shape in which a bottom portion is smaller in area than a top portion on the opening side.

The separating layer120A of the single-layer semiconductor device12illustrated inFIG. 3Bis formed by filling each of openings provided by etching from both the main surfaces opposed to each other of the semiconductor substrate130with the insulating material, thereby having a hexagonal shape in which a tapered direction is reversed halfway. In contrast, the separating layer120of the single-layer semiconductor device11illustrated inFIG. 3Ais formed by filling an opening provided by etching from the one main surface of the semiconductor substrate130with the insulating material, thereby having a trapezoidal shape that is tapered in one direction.

In the single-layer semiconductor device12illustrated inFIG. 3B, a portion of the separating layer120A is formed simultaneously with the element separating layer121from a surface side of the semiconductor substrate130on which the field-effect transistor145is formed, and thereafter a remaining portion of the separating layer120A is formed from a surface opposed to the surface, on which the element separating layer121is formed, of the semiconductor substrate130. This makes it possible to form the separating layer120A that penetrates through the semiconductor substrate130in the single-layer semiconductor device12illustrated inFIG. 3B.

In the single-layer semiconductor device12illustrated inFIG. 3B, an opening with a high aspect ratio that penetrates through the semiconductor substrate130may not be formed at the time of formation of the separating layer120A, which makes it possible to reduce the level of difficulty in etching at the time of formation of the separating layer120A.

Further, still another example of the single-layer semiconductor device is described with reference toFIG. 3C.

As illustrated inFIG. 3C, a single-layer semiconductor device13includes one semiconductor substrate130A, and one multi-layer wiring layer140that is formed on the semiconductor substrate130A. On the semiconductor substrate130A, for example, the PIN diode100, a field-effect transistor (unillustrated), and the like are provided to be isolated by the separating layer120and the element separating layer121. The PIN diode100is configured by stacking the first conductivity-type layer111, the intermediate layer113, and the second conductivity-type layer115in the thickness direction of the semiconductor substrate130.

Here, in the single-layer semiconductor device13illustrated inFIG. 3C, the semiconductor substrate130A is not reduced in thickness, and has a thickness of about several hundred μm. Therefore, in a case where the PIN diode100is formed to penetrate through the semiconductor substrate130A, an entire height of the PIN diode100is about several hundred μm, which makes it difficult to achieve the PIN diode100having desired characteristics.

Hence, in the single-layer semiconductor device13illustrated inFIG. 3C, the PIN diode100is first formed with a height having the desired characteristics. Thereafter, an opening131is provided that exposes the PIN diode100from a surface opposed to a surface, on which the multi-layer wiring layer140is provided, of the semiconductor substrate130A, which allows for electrical coupling to the PIN diode100.

In the single-layer semiconductor device13illustrated inFIG. 3C, the semiconductor substrate130is not reduced in thickness, and has a thickness of about several hundred μm, which makes it possible to enhance mechanical strength of the single-layer semiconductor device13.

It is to be noted that, in the configuration, other than the thickness, of the semiconductor substrate130A, respective configurations of the single-layer semiconductor device13illustrated inFIG. 3Care substantially similar to respective configurations of the single-layer semiconductor device11illustrated inFIG. 3A. Therefore, description of these configurations is not repeated here.

(2.2. Application Examples to Multi-Layer Semiconductor Device)

Next, application examples of the semiconductor device100according to the present embodiment to a multi-layer semiconductor device are described with reference to Each ofFIGS. 4A, 4B, and 4C.

As illustrated inFIG. 4A, a multi-layer semiconductor device21includes a substrate including a semiconductor substrate130and a multi-layer wiring layer140that is formed on the semiconductor substrate130, and a substrate including a semiconductor substrate230and a multi-layer wiring layer240that is formed on the semiconductor substrate130. In other words, the multi-layer semiconductor device21is a semiconductor device including two semiconductor substrates bonded to each other, and may be, for example, a back-illuminated solid-state imaging device.

In the multi-layer semiconductor device21, the substrate including the semiconductor substrate130and the multi-layer wiring layer140that is formed on the semiconductor substrate130, and the substrate including the semiconductor substrate230and the multi-layer wiring layer240that is formed on the semiconductor substrate230are bonded to each other to cause the multi-layer wiring layers140and240to be opposed to each other (that is, in face to face) with an insulating layer151interposed therebetween. However, it goes without saying that, in the multi-layer semiconductor device21, the substrates may be bonded to each other to cause the semiconductor substrate130and the multi-layer wiring layer240to be opposed to each other, or to cause the multi-layer wiring layer140and the semiconductor substrate230to be opposed to each other (that is, in face to back).

The semiconductor substrate130is, for example, a silicon substrate that is reduced in thickness within a range of several μm to several dozen μm (for example, 2 μm to 20 μm). On the semiconductor substrate130, for example, the PIN diode100(that is, the above-described semiconductor device100), the field-effect transistor145, and the like are provided to be isolated by the separating layer120and the element separating layer121.

As described above, the PIN diode100is configured by stacking a first conductivity-type layer, an intermediate layer, and a second conductivity-type layer in the thickness direction of the semiconductor substrate130, and functions as a withstand voltage element. The field-effect transistor145is, for example, a MOSFET, and executes signal processing and the like in the multi-layer semiconductor device21.

It is to be noted that the field-effect transistor145is an example of an active element and a passive element provided on the semiconductor substrate130, and an element provided on the semiconductor substrate130is not limited to the field-effect transistor145. Further, a plurality of other active elements and a plurality of other passive elements may be provided on the semiconductor substrate130.

Each of the separating layer120and the element separating layer121includes, for example, an insulating material such as silicon oxide, and electrically isolates the PIN diode100, the field-effect transistor145, and the like that are formed on the semiconductor substrate130from one another. It is to be noted that, in order to electrically isolate the PIN diode100, the separating layer120is provided to penetrate through the semiconductor substrate130. In contrast, the element separating layer121may not be provided to penetrate through the semiconductor substrate130.

The multi-layer wiring layer140is provided on the semiconductor substrate130by stacking the plurality of interlayer insulating films143including an insulating material, for example. In addition, for example, the wiring layer142that transmits signals from the PIN diode100, the field-effect transistor145, and the like is provided inside the multi-layer wiring layer140. The wiring layer142is electrically coupled to the PIN diode100, the field-effect transistor145, and the like that are provided on the semiconductor substrate130through the via141provided in a lowermost layer. It is possible for the wiring layer142to take signals from the PIN diode100, the field-effect transistor145, and the like through the via141.

A twin contact551is provided on a surface opposed to a surface, on which the multi-layer wiring layer140is provided, of the semiconductor substrate130to take a signal from the PIN diode100. Specifically, the twin contact551is formed by filling an opening for exposing either the first conductivity-type layer or the second conductivity-type layer of the PIN diode100, and an opening for exposing the wiring layer142with a metallic material such as copper (Cu), or the like, and coupling both the openings filled with the metallic material to each other.

The interlayer insulating film143may include a heretofore known insulating material such as SiO2or SiN, for example. As an alternative, the interlayer insulating film143may include a single kind of insulating material, or may include a plurality of kinds of insulating materials. The wiring layer142may include, for example, a metallic material, such as copper (Cu) or aluminum (Al), that has relatively low resistance. This allows the wiring layer142to transmit signals at higher speed. The via141may include, for example, a metallic material, such as tungsten (W), that has high opening filling property at the time of forming a film.

The semiconductor substrate230is, for example, a silicon substrate. The semiconductor substrate230may be reduced in thickness, or may not be reduced in thickness. On the semiconductor substrate230, for example, a field-effect transistor245and the like are provided to be isolated by an element separating layer221. The field-effect transistor245is, for example, a MOSFET, and executes signal processing and the like in the multi-layer semiconductor device21.

It is to be noted that the field-effect transistor245is an example of an active element and a passive element that are provided on the semiconductor substrate230, and an element provided on the semiconductor substrate230is not limited to the field-effect transistor245. Further, a plurality of other active elements and a plurality of other passive elements may be provided on the semiconductor substrate230.

The element separating layer221includes, for example, an insulating material such as oxide silicon, and electrically isolates the field-effect transistor245and the like that are formed on the semiconductor substrate230from each other.

The multi-layer wiring layer240is provided on the semiconductor substrate230by stacking a plurality of interlayer insulating films243including an insulating material, for example. In addition, for example, a wiring layer242that transmits signals from the field-effect transistor245and the like is provided inside the multi-layer wiring layer240. The wiring layer242is electrically coupled to the field-effect transistor245and the like that are provided on the semiconductor substrate230through a via241provided in a lowermost layer. It is possible for the wiring layer242to take signals from the field-effect transistor245and the like through the via241.

An interlayer insulating film243may include a heretofore known insulating material such as SiOxor SiNx, for example. As an alternative, the interlayer insulating film243may include a single kind of insulating material, or may include a plurality of kinds of insulating materials. The wiring layer242may include, for example, a metallic material, such as copper (Cu) or aluminum (Al), that has relatively low resistance to allow for signal transmission at higher speed. The via241may include, for example, a metallic material such as tungsten (W) that had high opening filling property at the time of forming a film.

The insulating layer151includes, for example, a heretofore known insulating material such as SiOxor SiNx, and is provided between the multi-layer wiring layer140and the multi-layer wiring layer240. The insulating layer151electrically insulates the wiring layer142inside the multi-layer wiring layer140and the wiring layer242inside the multi-layer wiring layer240from each other.

It is to be noted that use of heretofore known methods makes it possible to form electrical coupling between the wiring layer142inside the multi-layer wiring layer140and the wiring layer242inside the multi-layer wiring layer240. For example, it is possible to form electrical coupling between the wiring layer142inside the multi-layer wiring layer140and the wiring layer242inside the multi-layer wiring layer240by, for example, a contact via that is provided to penetrate through the insulating layer151, a twin contact via that forms electrical coupling by filling a plurality of through-holes with an electrically conductive material, an electrode junction structure that forms electrical coupling by joining electrodes exposed on a bonding surface, and the like.

A pad533is a metallic layer that is exposed by an opening531, and functions as an input/output section (an I/O section) of the multi-layer semiconductor device21. Coupling of wire bonding or the like to the pad533makes it possible to form electrical coupling between the multi-layer semiconductor device21and an external circuit. The pad533may include, for example, a metallic material, such as aluminum (Al), that facilitates electrical coupling by wire bonding or the like.

An insulating layer510is provided on a surface side opposed to a surface, on which the multi-layer wiring layer140is provided, of the semiconductor substrate130, and functions as a protective layer that protects an internal circuit and the like of the multi-layer semiconductor device21. The insulating layer510may include a transparent insulating material such as SiOx, SiNx, Al2O3, or TiO2, for example.

Microlenses520are provided in a case where the multi-layer semiconductor device21is a solid-state imaging device, and enhances sensitivity of the solid-state imaging device by collecting light from an imaging object. Further, in a case where the multi-layer semiconductor device21is the solid-state imaging device, a color filter having any color of red, green, or blue may be provided on each of the microlenses520to allow for color imaging.

The PIN diode100(that is, the above-described semiconductor device100) is applicable as a withstand voltage element to such a multi-layer semiconductor device21having a two-layer structure. In the multi-layer semiconductor device21, a multi-layer wiring layer or a semiconductor substrate is provided on each of the main surfaces opposed to each other of the semiconductor substrate130on which the PIN diode100is provided, which makes it possible to form electrical coupling to the PIN diode100more easily. Accordingly, the PIN diode100is usable as a withstand voltage protection element that protects an internal circuit against a surge voltage arising in the multi-layer semiconductor device21.

It is to be noted that, in the multi-layer semiconductor device21illustrated inFIG. 4A, an example in which the PIN diode100is provided inside the semiconductor substrate130is given; however, it goes without saying that the PIN diode100may be provided inside the semiconductor substrate230.

Next, another example of the multi-layer semiconductor device is described with reference toFIG. 4B.

As illustrated inFIG. 4B, a multi-layer semiconductor device31includes a substrate including the semiconductor substrate130and the multi-layer wiring layer140that is formed on the semiconductor substrate130, a substrate including the semiconductor substrate230and the multi-layer wiring layer240that is formed on the semiconductor substrate230, and a substrate including a semiconductor substrate330and a multi-layer wiring layer340that is formed on the semiconductor substrate330. In other words, the multi-layer semiconductor device31is a semiconductor device including three semiconductor substrates bonded together, and may be, for example, a back-illuminated solid-state imaging device.

In the multi-layer semiconductor device31, the substrate including the semiconductor substrate130and the multi-layer wiring layer140that is formed on the semiconductor substrate130, and the substrate including the semiconductor substrate230and the multi-layer wiring layer240that is formed on the semiconductor substrate230are bonded to each other to cause the multi-layer wiring layers140and240to be opposed to each other with the insulating layer151interposed therebetween. Meanwhile, the substrate including the semiconductor substrate130and the multi-layer wiring layer140that is formed on the semiconductor substrate130, and the substrate including the semiconductor substrate330and the multi-layer wiring layer340that is formed on the semiconductor substrate330are bonded to each other to cause the semiconductor substrate130and the multi-layer wiring layer340to be opposed to each other with an insulating layer152interposed therebetween.

In the multi-layer semiconductor device31illustrated inFIG. 4B, it is possible to electrically couple the PIN diode100to a field-effect transistor345and the like that are provided in the multi-layer wiring layer340by an electrode junction structure552. In the multi-layer semiconductor device31illustrated inFIG. 4B, configurations identical in name and reference numeral to the configurations described in the multi-layer semiconductor device21illustrated inFIG. 4Aare substantially as described in the multi-layer semiconductor device21illustrated inFIG. 4A; therefore, description thereof is not repeated here.

The semiconductor substrate330is, for example, a silicon substrate that is reduced in thickness within a range of several μm to several dozen μm (for example, 2 μm to 20 μm). On the semiconductor substrate330, for example, the field-effect transistor345and the like are provided. The field-effect transistor345is, for example, a MOSFET, and executes signal processing and the like in the multi-layer semiconductor device31.

It is to be noted that the field-effect transistor345is an example of an active element and a passive element provided on the semiconductor substrate330, and an element provided on the semiconductor substrate330is not limited to the field-effect transistor345. Further, a plurality of other active elements and a plurality of other passive elements may be provided on the semiconductor substrate330.

The multi-layer wiring layer340is provided on the semiconductor substrate330by stacking a plurality of interlayer insulating films including a heretofore known insulating material such as SiOxor SiNx, for example. In addition, for example, a wiring layer (not illustrated) that transmits signals from the field-effect transistor345and the like may be provided inside the multi-layer wiring layer340. The wiring layer is electrically coupled to the field-effect transistor345and the like that are provided on the semiconductor substrate330through a via (not illustrated) provided in a lowermost layer. It is to be noted that the wiring layer and the via may include, for example a metallic material, such as copper (Cu), aluminum (Al), or (W), that has relatively low resistance.

The insulating layer152includes, for example, a heretofore known insulating material such as SiOxor SiNx, and is provided between the multi-layer wiring layer340and the semiconductor substrate130. The insulating layer152electrically insulates the multi-layer wiring layer340and the semiconductor substrate130from each other.

The electrode junction structure552is an electrical coupling structure that is formed by joining electrodes exposed on a bonding surface of the insulating layer152and the multi-layer wiring layer340. Specifically, the electrode junction structure552is formed by bringing an electrode including copper (Cu) formed in the insulating layer152and an electrode including copper (Cu) formed in the multi-layer wiring layer340into contact with each other and joining both the electrodes by heat treatment.

The PIN diode100is applicable as a withstand voltage element also to such a multi-layer semiconductor device31having a three-layer structure. Further, a structure that forms electrical coupling between the multi-layer wiring layer340and the PIN diode100or the multi-layer wiring layer140is not limited to the above-described electrode junction structure552, and it is also possible to use various structures such as a contact via or a twin contact via.

In the multi-layer semiconductor device31illustrated inFIG. 4B, an example in which the PIN diode100is provided inside the semiconductor substrate130is given; however, it goes without saying that the PIN diode100may be provided inside the semiconductor substrate230or the semiconductor substrate330.

Next, still another example of the multi-layer semiconductor device is described with reference toFIG. 4C.

As illustrated inFIG. 4C, a multi-layer semiconductor device32includes a substrate including the semiconductor substrate130and the multi-layer wiring layer140that is formed on the semiconductor substrate130, a substrate including the semiconductor substrate230and the multi-layer wiring layer240that is formed on the semiconductor substrate230, and a substrate including the semiconductor substrate330and the multi-layer wiring layer340that is formed on the semiconductor substrate330. In other words, the multi-layer semiconductor device32is a semiconductor device including three semiconductor substrates bonded together, and may be, for example, a back-illuminated solid-state imaging device.

In the multi-layer semiconductor device32, the substrate including the semiconductor substrate130and the multi-layer wiring layer140that is formed on the semiconductor substrate130, and the substrate including the semiconductor substrate230and the multi-layer wiring layer240that is formed on the semiconductor substrate230are bonded to each other to cause the multi-layer wiring layers140and240to be opposed to each other with the insulating layer151interposed therebetween. Meanwhile, the substrate including the semiconductor substrate130and the multi-layer wiring layer140that is formed on the semiconductor substrate130, and the substrate including the semiconductor substrate330and the multi-layer wiring layer340that is formed on the semiconductor substrate330are bonded to each other to cause the semiconductor substrate130and the multi-layer wiring layer340to be opposed to each other with the insulating layer152interposed therebetween.

In the multi-layer semiconductor device32illustrated inFIG. 4C, it is possible to electrically couple the PIN diode100to the field-effect transistor345that is provided in the multi-layer wiring layer340and the wiring layer142that is provided in the multi-layer wiring layer140through twin contacts551A and551B. In the multi-layer semiconductor device32illustrated inFIG. 4C, configurations identical in names and reference numerals to the configurations described in the multi-layer semiconductor devices21and31illustrated inFIGS. 4A and 4Bare substantially as described in the multi-layer semiconductor devices21and31illustrated inFIGS. 4A and 4B; therefore, description thereof is not repeated here.

The twin contacts551A and551B are provided on a surface opposed to a surface, on which the multi-layer wiring layer140is provided, of the semiconductor substrate130to take a signal from the PIN diode100. Specifically, the twin contact551A is formed by filling an opening for exposing either the first conductivity-type layer or the second conductivity-type layer of the PIN diode100, and an opening for exposing the wiring layer142with a metallic material such as copper (Cu), or the like, and coupling both the openings filled with the metallic material to each other. Further, the twin contact551B is formed by filling an opening for exposing the twin contact551A and an opening for exposing a terminal of the field-effect transistor345with a metallic material such as copper (Cu), or the like, and coupling both the openings filled with the metallic material to each other.

The PIN diode100is applicable as a withstand voltage element also to such a multi-layer semiconductor device32having a three-layer structure.

3. METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

A first method of manufacturing the multi-layer semiconductor device21is described with reference toFIGS. 5A, 5B, 5C, 5D, and 5E. Each ofFIGS. 5A, 5B, 5C, 5D, and 5Eis a are longitudinal cross-sectional views for schematically describing each process of the first method of manufacturing the multi-layer semiconductor device21.

First, as illustrated inFIG. 5A, the separating layer120and the element separating layer121are formed in predetermined regions of the semiconductor substrate130. Specifically, openings are formed by etching predetermined regions of one main surface of the semiconductor substrate130that includes silicon or the like. Thereafter, the separating layer120and the element separating layer121are formed by filling the openings formed by etching with an insulating material, and perform planarization. It is to be noted that the separating layer120is formed to a region having a depth equal to or greater than a depth of a region in which the element separating layer121is formed.

Next, as illustrated inFIG. 5B, the second conductivity-type layer115and the field-effect transistor145are formed in predetermined regions of the semiconductor substrate130, and thereafter the interlayer insulating film143is formed on the semiconductor substrate130. Specifically, the second conductivity-type layer115is formed by ion-implanting the second conductivity-type impurities in a region surrounded by the separating layer120of the semiconductor substrate130and performing heat treatment. Further, the field-effect transistor145is formed by a heretofore known method in a region surrounded by the element separating layer121of the semiconductor substrate130. Thereafter, the interlayer insulating film143is formed using silicon oxide or the like on the one main surface of the semiconductor substrate130on which the second conductivity-type layer115and the field-effect transistor145are formed. It is to be noted that the heat treatment at the time of formation of the second conductivity-type layer115may be performed simultaneously with heat treatment for other configurations.

Subsequently, as illustrated inFIG. 5C, the multi-layer wiring layer140is formed on the semiconductor substrate130. Specifically, the multi-layer wiring layer140is formed on the semiconductor substrate130by repeating film formation of the interlayer insulating film143, formation of the wiring layer142, and formation of the via141penetrating through the interlayer insulating film143. For constituent materials of the interlayer insulating film143, the wiring layer142, and the via141, the above-described materials are usable.

Next, as illustrated inFIG. 5D, the semiconductor substrate130on which the multi-layer wiring layer140is formed in the above-described process, and the semiconductor substrate230on which the multi-layer wiring layer240is formed in a similar process are bonded to each other with the insulating layer151interposed therebetween. Specifically, the semiconductor substrate130on which the multi-layer wiring layer140is formed, and the semiconductor substrate230on which the multi-layer wiring layer240is formed are bonded to each other to cause the multi-layer wiring layers140and240to be opposed to each other. At this time, the wiring layer142inside the multi-layer wiring layer140and the wiring layer242inside the multi-layer wiring layer240are electrically insulated from each other by providing the insulating layer151on a bonding surface of the multi-layer wiring layers140and240. It is possible to form electrical coupling (not illustrated) between the wiring layer142inside the multi-layer wiring layer140and the wiring layer242inside the multi-layer wiring layer240by using a heretofore known method separately.

Thereafter, as illustrated inFIG. 5E, the semiconductor substrate130is reduced in thickness by polishing the semiconductor substrate130until the separating layer120is exposed. Specifically, the semiconductor substrate130is reduced in thickness within a range of several μm to several dozen μm (for example, 2 μm to 20 μm) by polishing a surface opposed to a surface, on which the multi-layer wiring layer140is provided, of the semiconductor substrate130until the separating layer120is exposed with use of CMP or the like.

Next, as illustrated inFIG. 5F, the first conductivity-type layer111is formed in a predetermined region of the semiconductor substrate130. Specifically, the first conductivity-type layer111is formed by ion-implanting the first conductivity-type impurities in a region surrounded by the separating layer120of the semiconductor substrate130and performing heat treatment. The first conductivity-type layer111is formed in a region having a depth that comes in no contact with the second conductivity-type layer115, and a region between the first conductivity-type layer111and the second conductivity-type layer115becomes the intermediate layer113. This makes it possible to form the semiconductor device100including the first conductivity-type layer111, the intermediate layer113, and the second conductivity-type layer115that are stacked, and the multi-layer semiconductor device including the semiconductor device100.

A second method of manufacturing the multi-layer semiconductor device21is described with reference toFIGS. 6A, 6B, 6C, 6D, and 6E. Each ofFIGS. 6A, 6B, 6C, 6D, and 6Eare longitudinal cross-sectional views for describing each process of the second method of manufacturing the multi-layer semiconductor device21.

First, as illustrated inFIG. 6A, the separating layer120and the element separating layer121are formed in predetermined regions of the semiconductor substrate130. Specifically, openings are formed by etching predetermined regions of one main surface of the semiconductor substrate130that includes silicon or the like. Thereafter, the separating layer120and the element separating layer121are formed by filling the openings formed by etching with an insulating material and performing planarization. It is to be noted that the separating layer120is formed to a region having a depth equal to or greater than a depth of a region in which the element separating layer121is formed.

Next, as illustrated inFIG. 6B, the first conductivity-type layer111, the second conductivity-type layer115, and the field-effect transistor145are formed in predetermined regions of the semiconductor substrate130, and thereafter the interlayer insulating film143is formed on the semiconductor substrate130. Specifically, the first conductivity-type layer111and the second conductivity-type layer115are formed by ion-implanting the first conductivity-type impurities and the second conductivity-type impurities respectively in a region surrounded by the separating layer120of the semiconductor substrate130and performing heat treatment. Depths at which the first conductivity-type layer111and the second conductivity-type layer115are formed are controllable by energy of the first conductivity-type impurities and the second conductivity-type impurities at the time of ion implantation. Therefore, control of a condition of the ion implantation makes it possible to form a stacking structure of the first conductivity-type layer111, the intermediate layer113, and the second conductivity-type layer115. Further, the field-effect transistor145is formed by a heretofore known method in a region surrounded by the element separating layer121of the semiconductor substrate130. Thereafter, the interlayer insulating film143is formed using silicon oxide or the like on the one main surface of the semiconductor substrate130on which the second conductivity-type layer115and the field-effect transistor145are formed.

Subsequently, as illustrated inFIG. 6C, the multi-layer wiring layer140is formed on the semiconductor substrate130. Specifically, the multi-layer wiring layer140is formed on the semiconductor substrate130by repeating film formation of the interlayer insulating film143, formation of the wiring layer142, and formation of the via141penetrating through the interlayer insulating film143. For constituent materials of the interlayer insulating film143, the wiring layer142, and the via141, the above-described materials are usable.

Next, as illustrated inFIG. 6D, the semiconductor substrate130on which the multi-layer wiring layer140is formed in the above-described process, and the semiconductor substrate230on which the multi-layer wiring layer240is formed in a similar process are bonded to each other with the insulating layer151interposed therebetween. Specifically, the semiconductor substrate130on which the multi-layer wiring layer140is formed, and the semiconductor substrate230on which the multi-layer wiring layer240is formed are bonded to each other to cause the multi-layer wiring layers140and240to be opposed to each other. At this time, the wiring layer142inside the multi-layer wiring layer140and the wiring layer242inside the multi-layer wiring layer240are electrically insulated from each other by providing the insulating layer151on a bonding surface of the multi-layer wiring layers140and240. It is possible to form electrical coupling (not illustrated) between the wiring layer142inside the multi-layer wiring layer140and the wiring layer242inside the multi-layer wiring layer240by using a heretofore known method separately.

Thereafter, as illustrated inFIG. 6E, the semiconductor substrate130is reduced in thickness by polishing the semiconductor substrate130until the first conductivity-type layer111is exposed. Specifically, the semiconductor substrate130is reduced in thickness within a range of several μm to several dozen μm (for example, 2 μm to 20 μm) by polishing a surface opposed to a surface, on which the multi-layer wiring layer140is provided, of the semiconductor substrate130until the first conductivity-type layer111is exposed with use of CMP or the like. This makes it possible to form the semiconductor device100including the first conductivity-type layer111, the intermediate layer113, and the second conductivity-type layer115that are stacked, and the multi-layer semiconductor device including the semiconductor device100.

A third method of manufacturing the multi-layer semiconductor device21is described with reference toFIGS. 7A, 7B, 7C, 7D, and 7E. Each ofFIGS. 7A, 7B, 7C, 7D, and 7Eare longitudinal cross-sectional views for describing each process of the third method of manufacturing the multi-layer semiconductor device21.

First, as illustrated inFIG. 7A, the separating layer120of which a portion of which serves as a diffusion layer123, and the element separating layer121are formed in predetermined regions of the semiconductor substrate130. Specifically, openings are formed by etching predetermined regions of one main surface of the semiconductor substrate130that includes silicon or the like. In the opening in which the separating layer120is to be formed, the diffusion layer123is first formed by filling a portion of the opening with a material that is prepared by adding the first conductivity-type impurities to an inorganic insulating substance, and thereafter the separating layer120is formed by filling a remaining portion of the opening with an insulating material and performing planarization. Meanwhile, in the opening in which the element separating layer121is to be formed, the element separating layer121is formed by filling the opening with the insulating material and performing planarization.

Next, as illustrated inFIG. 7B, the first conductivity-type layer111and the second conductivity-type layer115are formed in a predetermined region of the semiconductor substrate130by introducing the second conductivity-type impurities and thereafter performing heat treatment. Thereafter, the field-effect transistor145is formed in a predetermined region of the semiconductor substrate130, and then the interlayer insulating film143is formed on the semiconductor substrate130. Specifically, the second conductivity-type impurities are introduced into a region surrounded by the separating layer120of the semiconductor substrate130, and thereafter heat treatment is performed to activate the introduced second conductivity-type impurities, thereby forming the second conductivity-type layer115. Further, the heat treatment causes solid-state diffusion of the first conductivity-type impurities included in the diffusion layer123, thereby forming the first conductivity-type layer111. This makes it possible to form a stacking structure of the first conductivity-type layer111, the intermediate layer113, and the second conductivity-type layer115. Further, the field-effect transistor145is formed by a heretofore known method in a region surrounded by the element separating layer121of the semiconductor substrate130. Thereafter, the interlayer insulating film143is formed using silicon oxide or the like on the one main surface of the semiconductor substrate130on which the second conductivity-type layer115and the field-effect transistor145are formed.

Subsequently, as illustrated inFIG. 7C, the multi-layer wiring layer140is formed on the semiconductor substrate130. Specifically, the multi-layer wiring layer140is formed on the semiconductor substrate130by repeating film formation of the interlayer insulating film143, formation of the wiring layer142, and formation of the via141penetrating through the interlayer insulating film143. For constituent materials of the interlayer insulating film143, the wiring layer142, and the via141, the above-described materials are usable.

Next, as illustrated inFIG. 7D, the semiconductor substrate130on which the multi-layer wiring layer140is formed in the above-described process, and the semiconductor substrate230on which the multi-layer wiring layer240is formed in a similar process are bonded to each other with the insulating layer151interposed therebetween. Specifically, the semiconductor substrate130on which the multi-layer wiring layer140is formed, and the semiconductor substrate230on which the multi-layer wiring layer240is formed are bonded to each other to cause the multi-layer wiring layers140and240to be opposed to each other. At this time, the wiring layer142inside the multi-layer wiring layer140and the wiring layer242inside the multi-layer wiring layer240are electrically insulated from each other by providing the insulating layer151on a bonding surface of the multi-layer wiring layers140and240. It is possible to form electrical coupling (not illustrated) between the wiring layer142inside the multi-layer wiring layer140and the wiring layer242inside the multi-layer wiring layer240by using a heretofore known method separately.

Thereafter, as illustrated inFIG. 7E, the semiconductor substrate130is reduced in thickness by polishing the semiconductor substrate130until the separating layer120is exposed. Specifically, the semiconductor substrate130is reduced in thickness within a range of several μm to several dozen μm (for example, 2 μm to 20 μm) by polishing a surface opposed to a surface, on which the multi-layer wiring layer140is provided, of the semiconductor substrate130until the separating layer120is exposed with use of CMP or the like. This makes it possible to form the semiconductor device100including the first conductivity-type layer111, the intermediate layer113, and the second conductivity-type layer115that are stacked, and the multi-layer semiconductor device that includes the semiconductor device100.

4. ELECTRONIC APPARATUS

Next, description is given of an electronic apparatus according to an embodiment of the present disclosure. The electronic apparatus according to the embodiment of the present disclosure is any of a variety of electronic apparatuses in which circuits including the above-described semiconductor device100are mounted. Examples of the electronic apparatus according to the present embodiment are described with reference toFIGS. 8A, 8B, and 8C. Each ofFIGS. 8A, 8B, and 8Cis an are external views of an example of the electronic apparatus according to the present embodiment.

For example, the electronic apparatus according to the present embodiment may be an electronic apparatus such as a smartphone. Specifically, as illustrated inFIG. 8A, a smartphone900includes a display section901that displays various types of information, and an operating section903including a button or the like for receiving an input from a user. Here, the semiconductor device100according to the embodiment of the present disclosure may be provided in a control circuit that controls various operations of the smartphone900.

For example, the electronic apparatus according to the present embodiment may be an electronic apparatus such as a digital camera. Specifically, as illustrated inFIGS. 8B and 8C, a digital camera910includes a main body section (a camera body)911, an interchangeable lens unit913, a grip915to be gripped by the user at the time of photographing, a monitor section917that displays various types of information, and an EVF (Electronic View Finder)919that displays a through image viewed by the user at the time of photographing. It is to be noted thatFIG. 8Bis an external view of the digital camera910as seen from the front side (i.e., a subject side), andFIG. 8Cis an external view of the digital camera910as seen from the back side (i.e., a photographer side). Here, the semiconductor device100according to the embodiment of the present disclosure may be provided in a control circuit that controls various operations of the digital camera910.

It is to be noted that the electronic apparatus according to the present embodiment is not limited to the above-described examples. The electronic apparatus according to the present embodiment may be any of electronic apparatuses in every field. As examples of such electronic apparatuses, it is possible to exemplify a glass-shaped wearable device, an HMD (Head-Mounted Display), a television apparatus, an electronic book, a PDA (Personal Digital Assistant), a notebook personal computer, a video camera, a gaming console, or the like.

In particular, the semiconductor device100according to the embodiment of the present disclosure functions as a withstand voltage element that withstands a higher voltage. Therefore, the semiconductor device100according to the embodiment of the present disclosure is more suitably usable in electronic apparatuses in an in-vehicle mounting field or an IoT field in which a higher-voltage power supply is used in an internal circuit.

As described above, according to the semiconductor device100of the embodiment of the present disclosure, it is possible to form the PIN structure that includes the first conductivity-type layer111, the intermediate layer113, and the second conductivity-type layer115in the stacking direction. This allows the semiconductor device100according to the present embodiment to further reduce an occupancy area in a planar direction, as compared with a case where the PIN structure is formed in the planar direction. Therefore, the semiconductor device100according to the present embodiment makes it possible to provide a withstand voltage element that withstands a higher voltage while having a more efficient occupancy area.

A preferred embodiment(s) of the present disclosure has/have been described above in detail with reference to the accompanying drawings, but the technical scope of the present disclosure is not limited to such an embodiment(s). It is apparent that a person having ordinary skill in the art of the present disclosure may arrive at various alterations and modifications within the scope of the technical idea described in the appended claims, and it is understood that such alterations and modifications naturally fall within the technical scope of the present disclosure.

For example, in the above-described embodiment, an example in which the semiconductor device100according to the present embodiment is applied to a solid-state imaging device is described, but the present technology is not limited to such an example. The semiconductor device100according to the present embodiment may be applied to a logic circuit, a memory device, various sensors, and the like.

Furthermore, the effects described herein are merely illustrative and exemplary, and not limitative. That is, the technology according to the present disclosure may exert other effects that are apparent to those skilled in the art from the description herein, in addition to the above-described effects or in place of the above-described effects.

It is to be noted that the following configurations also fall within the technical scope of the present disclosure.

A semiconductor device including:

a first conductivity-type layer into which first conductivity-type impurities are introduced;

a second conductivity-type layer into which second conductivity-type impurities are introduced, the second conductivity-type impurities being different in polarity from the first conductivity-type impurities; and

an intermediate layer that is sandwiched between the first conductivity-type layer and the second conductivity-type layer, and does not include the first conductivity-type impurities or the second conductivity-type impurities, or includes the first conductivity-type impurities or the second conductivity-type impurities at a concentration lower than a concentration of the first conductivity-type impurities in the first conductivity-type layer or the second conductivity-type impurities in the second conductivity-type layer,

the first conductivity-type layer, the intermediate layer, and the second conductivity-type layer being stacked in a thickness direction of a semiconductor substrate inside the semiconductor substrate.

The semiconductor device according to (1), further including a separating layer that is provided between each of the first conductivity-type layer, the intermediate layer, and the second conductivity-type layer and the semiconductor substrate, and isolates the first conductivity-type layer, the intermediate layer, and the second conductivity-type layer from the semiconductor substrate.

The semiconductor device according to (2), in which a cross-sectional shape of the separating layer in the thickness direction of the semiconductor substrate is tapered.

The semiconductor device according to any one of (1) to (3), in which a stacking body of the first conductivity-type layer, the intermediate layer, and the second conductivity-type layer is provided to penetrate through the semiconductor substrate in the thickness direction.

The semiconductor device according to (4), in which the first conductivity-type layer and the second conductivity-type layer are exposed on both respective main surfaces opposed to each other of the semiconductor substrate.

The semiconductor device according to (4), in which at least one of the first conductivity-type layer or the second conductivity-type layer is exposed by an opening provided in the semiconductor substrate.

The semiconductor device according to any one of (1) to (6), in which the intermediate layer includes the first conductivity-type impurities or the second conductivity-type impurities at a concentration lower than the concentration of the first conductivity-type impurities in the first conductivity-type layer or the second conductivity-type impurities in the second conductivity-type layer.

The semiconductor device according to any one of (1) to (7), in which the first conductivity-type layer or the second conductivity-type layer is electrically coupled to a via provided in a multi-layer wiring layer that is formed on one of main surfaces of the semiconductor substrate.

An electronic apparatus provided with a semiconductor device that is provided inside a semiconductor substrate, the semiconductor device including:

a first conductivity-type layer into which first conductivity-type impurities are introduced;

a second conductivity-type layer into which second conductivity-type impurities are introduced, the second conductivity-type impurities being different in polarity from the first conductivity-type impurities; and

an intermediate layer that is sandwiched between the first conductivity-type layer and the second conductivity-type layer, and does not include the first conductivity-type impurities or the second conductivity-type impurities, or includes the first conductivity-type impurities or the second conductivity-type impurities at a concentration lower than a concentration of the first conductivity-type impurities in the first conductivity-type layer or the second conductivity-type impurities in the second conductivity-type layer,

the first conductivity-type layer, the intermediate layer, and the second conductivity-type layer being stacked in a thickness direction of a semiconductor substrate inside the semiconductor substrate.

REFERENCE NUMERAL LIST