Integrated trench capacitor with top plate having reduced voids

A method for forming trench capacitors includes forming a silicon nitride layer over a first region of a semiconductor surface doped a first type and over a second region doped a second type. A patterned photoresist layer is directly formed on the silicon nitride layer. An etch forms a plurality of deep trenches (DTs) within the first region. A liner oxide is formed that lines the DTs. The silicon nitride layer is etched forming an opening through the silicon nitride layer that is at least as large in area as the area of an opening in the semiconductor surface of the DT below the silicon nitride layer. The liner oxide is removed, a dielectric layer(s) on a surface of the DTs is formed, a top plate material layer is deposited to fill the DTs, and the top plate material layer is removed beyond the DT to form a top plate.

CROSS-REFERENCE TO COPENDING APPLICATIONS

This application has subject matter related to copending application Ser. No. 15/264,147 entitled “INTEGRATED TRENCH CAPACITOR” that was filed on Sep. 13, 2016.

FIELD

Disclosed embodiments relate generally to the field of integrated circuit (IC) design and processing, more specifically to integrated trench capacitors.

BACKGROUND

There are a number of challenges when attempting to integrate capacitors into the flow for an IC. Conventionally, integrated capacitors are built on the surface of the semiconductor chip, using the Metal-1 or Metal-2 layer for the bottom plate and a TiN layer for the top plate. These capacitors have a capacitive density of approximately 1.5 μF/μm2and can attain a highest operating voltage of approximately 8 V. More recently, trench capacitors generally having doped polysilicon top plates have been formed in deep trenches within the substrate or an epitaxial layer on the substrate.

SUMMARY

Disclosed embodiments recognize due to silicon undercutting during the deep trench (DT) silicon etch used to form integrated trench capacitors, the resulting silicon nitride opening at the top of the DT is smaller in area as compared to the area of the silicon opening below it. Due to this silicon undercut, after the top gate material (e.g., polysilicon) deposition for filling the DT and forming the top plate of the trench capacitor there are resulting voids/seams formed at and near the surface of the top plate material within the nitride opening or near the nitride opening. These voids/seams in the top plate material become exposed after the top plate etch, such as using chemical mechanical polishing (CMP), and remain with the integrated trench capacitor in the final integrated circuit (IC).

Problems with voids/seams in the top plate include increased contact resistance. Another problem is the trapping of slurry particles after CMP generally used for defining the top plate, or after a top plate etch such as a plasma etch. Yet another problem in some IC designs is there is a needed electrical contact to the top plate of the trench capacitor that can be rendered an open circuit by the presence of surface voids/seams. For example, for IC designs only allowing one contact in the center of the top plate for the integrated trench capacitors in an array of such capacitors, if the size of void at the surface is larger than the contact size, one will not be able to connect to the top plate resulting in an open circuit. As a result, due to missing the capacitance contribution for one or more integrated trench capacitors in an array of such trench capacitors hooked up in parallel, the capacitance density will be reduced and capacitance variation will be higher due to the randomness of void-induced open circuits.

Disclosed embodiments solve the top plate material layer void problem in DTs for integrated trench capacitors by adding processing including a silicon nitride etch back that renders the area of silicon nitride opening ≥ the area of the silicon opening underneath. Disclosed processing has been found to result in essentially eliminating voids in the top plate of the DT for contact landing. Reduced or eliminated voids in the surface of the top plate is particularly important for integrated high density trench capacitors which have a minimum silicon area to fit a single contact in the center of the top plate needed for the top plate connection to each trench capacitor in the trench capacitor array.

DETAILED DESCRIPTION

Also, the terms “coupled to” or “couples with” (and the like) as used herein without further qualification are intended to describe either an indirect or direct electrical connection. Thus, if a first device “couples” to a second device, that connection can be through a direct electrical connection where there are only parasitics in the pathway, or through an indirect electrical connection via intervening items including other devices and connections. For indirect coupling, the intervening item generally does not modify the information of a signal but may adjust its current level, voltage level, and/or power level.

FIG. 1is a flow chart that shows steps in an example method100for forming integrated trench capacitors with reduced top plate surface voids for an IC formed in and on a semiconductor surface, according to an example embodiment. Step101comprises forming a silicon nitride layer over a first region of the semiconductor surface that has a doping of a first type and over a second region having a doping of a second (opposite) type. As used herein, “silicon nitride” includes stoichiometric silicon nitride (Si3N4) or near stoichiometric silicon nitride, as well as silicon oxynitride (SiON) or a silicon-rich silicon nitride layer.

FIG. 2Aillustrates a portion of an in-process IC on which at least one disclosed integrated trench capacitor will be created after silicon nitride deposition. At this point, a lightly an epitaxial layer (epi layer)204such as a P-type epi layer can be been grown on a substrate202such as a P+ substrate. A buried layer (BL)206can be an N-type BL (NBL) that can be formed during the growth of the epi layer204. A buried layer205of the other dopant type relative to BL206, such as a P-type BL is also shown provided. The substrate202and epi layer204can both comprise silicon, and can also comprise other materials.

Additionally, a deep well region208is formed, i.e., patterned, deposited and driven in, to be created, such as an N-type deep well (DEEPN) in the case BL206is an NBL. In one embodiment, the DEEPN is doped in a range of 1×1015/cm3to 2×1016/cm3and the BL206embodies as an NBL is doped in a range 1×1015/cm3to 4×1015/cm3. In at least one embodiment, deep well region208and BL206are used in other regions of the IC to create isolation regions, so that formation of these regions is already part of a flow that does not necessarily include a disclosed integrated capacitor. In effect, Applicants are getting a “free” mask in that regions that are to be used for one plate of the trench capacitor, herein referred to as the bottom plate, can be included in existing masks, so that a new mask is not necessary to create this region. In other embodiments that do not already contain these steps, an additional mask may be used. In at least one embodiment, this point is the beginning of the modular process that can be inserted into an existing flow. On the surface of the epi layer204is shown a silicon nitride layer210on a silicon oxide layer209.

Step102comprises forming a patterned photoresist layer directly on the silicon nitride layer210. This is in contrast to a conventional oxide hard mask used on top of the silicon nitride layer210. The photoresist layer (see photoresist layer211inFIG. 2Bdescribed below) is created and patterned so that the DTs can be formed. For purposes of illustration, four DTs will be described but more generally one or more likely many more than 4 DTs will be simultaneously formed. A photoresist layer211overlies the silicon nitride layer210, which protects the surface of the IC.

Step103comprises etching to form a plurality DTs (see DTs212inFIG. 2Bdescribed below) within the first region. The DT silicon etch is typically a reactive ion etch (RIE) such as plasma RIE, or a combination of RIE and non-reactive dry or wet etching.FIG. 2Bis a cross sectional depiction showing an in-process integrated trench capacitor after the DTs212are formed with the pattered photoresist layer211over the silicon nitride layer210lateral to the DTs using anisotropic etching. As noted above, this etching arrangement is in contrast to a conventional oxide hard mask that is used on top of the silicon nitride layer210. A silicon undercut is shown in the DTs212(see the inset) which are etched through the silicon nitride layer210, silicon oxide layer209and into the deep well208/BL206. It will be understood that although photoresist layer211is shown as remaining intact after etching, much of the photoresist layer211may by removed by the DT etch process.

In at least one embodiment, such as using a circular trench layout, the width of the trenches is approximately 0.9 μm to 1.2 μm and the trenches are spaced apart approximately 0.5 μm to 1.0 μm. For an isolated trench capacitor, the depth of the trenches is determined by the depth of the isolation tank. The trench depth for the DTs can, of course, be deeper or shallower as required by a given application and to fit within the parameters of the process into which the trench capacitor is being integrated, e.g., the thickness of the epitaxial layer and the drive conditions for the deep well. In one embodiment for an isolated trench capacitor, RIE is used at least in part and the trench depth can be in the range of 5 μm to 9 μm. For a non-isolated capacitor the depth can be 20 μm deeper. In other embodiments, the depth of the trench can remain the same, while the thickness of capacitor's dielectric layer between its respective plates is varied to change the voltage rating of the trench capacitor.

Due to conventional undercut during the DT Si etch, the silicon nitride opening at top of the trench is recognized to be smaller in area compared to the Si opening below it. Once the top plate material completely fills at the nitride opening (seeFIG. 2Fdescribed below), some voids/seams are formed in the surface of the top plate material. These voids/seams become exposed when the silicon nitride layer is removed from the wafer surface. (seeFIG. 2Hdescribed below). The photoresist layer211is then removed and the wafer cleaned.

Step104comprises forming a liner oxide213that lines the DTs.FIG. 2Cis a cross sectional depiction showing an in-process integrated trench capacitor after forming the liner oxide inside the DTs. The liner oxide213in some embodiments can be 100 Å to 200 Å thick formed on the sidewalls of DTs212using a dry oxidation process or a deposition process.

Step105comprises wet etching the silicon nitride layer210. Heated phosphoric acid (H3PO4) can be used for silicon nitride etch selectivity relative to surrounding materials. A buffered oxide etch (BOE) dip can be first used to remove a thin oxynitride layer that may be on the silicon nitride layer210. After the wet etching an opening through the silicon nitride layer210is at least as large in area as the area of an opening in the DT212below the silicon nitride layer to make the size of the silicon nitride opening ≥ the size of the silicon opening below.

FIG. 2Dis a cross sectional depiction showing an in-process integrated trench capacitor after wet nitride pull back etch. As shown in the inset, after the nitride pull-back etch the area of the silicon nitride210opening is larger in area as compared to the area of the silicon opening below in the DTs212.

Step106comprises removing the liner oxide layer213. The liner oxide213is removed because it is generally phosphorous (or other dopant) contaminated.FIG. 2Eis a cross sectional depiction showing an in-process integrated trench capacitor after the removing the liner oxide layer213. The liner oxide layer213strip process can comprise an etch designed to remove the nominal liner oxide thickness with about a 200% over etch. Step107comprises forming at least one dielectric layer on a surface of the DTs.FIG. 2Fis a cross sectional depiction showing an in-process integrated trench capacitor after forming dielectric layers which can comprise in one embodiment a silicon oxynitride layer216on a silicon nitride layer215on a silicon oxide layer214on sidewall surfaces of the DTs212.

Step108comprises depositing a top plate material layer to fill the DTs.FIG. 2Gis a cross sectional depiction showing an in-process integrated trench capacitor after depositing the top plate material layer218to fill the DTs. The top plate material can generally be any electrically conductive layer, such as doped polysilicon either provided in-situ doped or extrinsically doped by ion implantation. Alternatively, the top plate material can comprise an electrically conductive transition metal compound such as electrically conductive transition metal nitrides including TiN and TaN (e.g., by magnetron sputtering). WSi, WN and WSi are also possible top plate materials. The top plate material layer218may also comprise two or more different layers. Step109comprises removing the top plate material layer218beyond the DT to form the top plate218a.FIG. 2His a cross sectional depiction showing an in-process integrated trench capacitor after removing the top plate material layer218beyond the DT (e.g., using CMP) and then removing the silicon nitride layer210.

Although not shown, the method can include another mask level to form dielectric isolation (LOCOS or STI) around the perimeter of each DT. For example, in the case of STI, photoresist can be formed on the wafer surface and patterned to expose areas where the STI trenches are to be etched. STI trenches are then etched into the wafer surface, after which the photoresist layer used to define the STI trenches can be removed. A typical STI trench depth is approximately 250 nm to 375 nm. A liner oxide (not specifically shown) can be grown or deposited on the exposed surfaces of the STI trench and the trench is overfilled with a high density plasma (HDP) oxide using chemical vapor deposition (CVD). Finally, the HDP oxide can be planarized using CMP to form the STI (see STI318inFIG. 3described below).

At a later point in the processing, source/drain regions are formed on the IC. The trench capacitor can receive these implants to finalize the doping for the trench capacitor. Another photoresist layer can be formed on the wafer and patterned with an N-type source/drain pattern and the wafer implanted with an N-type dopant such as phosphorus to form N+ regions. After this pattern is removed, another photoresist layer is deposited on the wafer and patterned with a P-type source/drain pattern and the wafer is implanted with a P-type dopant such as boron to form a P+ Regions. Once this photoresist layer is removed, the source/drain implants are annealed. Contact regions for both the bottom plate and the top plate are also formed. These steps complete formation of the trench capacitor. It will be understood that other processing can continue on the IC to form other components desired on the chip.

FIG. 3is a cross sectional depiction showing an IC350including essentially complete integrated trench capacitors300with reduced top plate surface voids that can be integrated into existing process flows, according to an example embodiment. Block345represents functional circuitry, which is integrated circuitry generally including a plurality of transistors, as well as resistors and capacitors all configured together to provide a circuit function that realizes and carries out a desired functionality of the IC350. For example, that of a digital IC (e.g., digital signal processor) or analog IC (e.g., amplifier or power converter), such as a BiMOS IC. The capability of functional circuitry provided by IC350may vary, for example ranging from a simple device to a complex device. The specific functionality provided by block345is not of importance to disclosed embodiments.

The trench capacitors300are shown created in an epi layer204that is grown on a substrate202, which in at least one embodiment is doped with a P-type dopant (e.g., boron). As noted above, the substrate202and epi layer204can both comprise silicon, and can also comprise other materials.

The bottom plate307of the trench capacitors300includes the BL206, and deep well208and generally also a source/drain in the deep well208, which in at least one embodiment receives N+ doping (e.g., phosphorus). In at least one embodiment, an implant of N+ doping and thermal drive is used to form heavily-doped deep well208. By doping the deep well208with an opposite type doping from that of the substrate202, the trench capacitors300are junction isolated from the substrate202by this pn junction. Given this junction isolation, the trench capacitors300may have a high voltage on either electrode/plate. In at least one embodiment the substrate202and the deep well208have the same type of doping, such that the trench capacitors300are not junction isolated from the substrate202. In this embodiment, the bottom plate of the trench capacitors300will be grounded and only the top plate will be able to be coupled to high voltage.

DTs are formed on the bottom plate307and are then lined with at least one dielectric layer shown as314(e.g., silicon oxide),315(e.g., silicon nitride) and316(e.g., silicon oxynitride). A top plate layer218, such as comprising polysilicon can be deposited over the dielectric layer(s) using in situ doping to fill and overfill the DT's and then be planarized, e.g., by CMP. In at least one embodiment, the top plate layer218comprises polysilicon that receives P+ doping, such as boron from in-situ doping at level of 1×1018to 5×1019cm−3.

The point at which the dielectric layers314-316intersect the upper surface of epi layer204/bottom plate307is recognized to be fragile and subject to damage during later processing. In order to protect these fragile areas to limit leakage, STI or LOCOS regions can be formed at the surface of the IC overlying the sidewalls of the previously-filled DTs. The capacitor300is shown including STI regions318formed at the surface of the IC overlying the sidewalls of the previously-filled DTs.

When transistors on the IC350receive source/drain (S/D) implants, both the bottom plate307and top plate218acan also receive appropriate types of S/D implants. Filled vias326(e.g., filled with W) through a pre-metal dielectric (PMD)320contact the bottom plate307and filled vias328(e.g., filled with W) through the PMD320contact the top plate218aas part of the metallization layers. A metal 1 connection over the PMD320to the top plate218aby the filled vias328is shown as335and a metal 1 connection over the PMD320to the bottom plate307by the filled vias326is shown as340.

In at least one embodiment, the formation of the trench capacitors300is modular and can be inserted into existing processes without disrupting other portion of the process flow for the IC350. In at least one embodiment, the formation of the bottom plate307occurs during the creation of isolation regions in other portions of the IC. In at least one embodiment, STI or LOCOS regions are formed in conjunction with the formation of STIs or LOCOS regions on other regions of the IC. In at least one embodiment, the modular flow that is exclusively for the trench capacitor includes a single mask to pattern for the deep trench etch, formation of the deep trenches, formation of a dielectric on the surface of the deep trenches, and filling the deep trenches with a top plate material (e.g., doped polysilicon) to form the top plate218a.

Applicants have disclosed a trench capacitor that can be integrated into existing semiconductor processor flows. Disclosed embodiments can be implemented in technologies that use a BL and deep well combination for isolation. The trench capacitor density may be as much as ten times higher than a known TiN capacitor, e.g., 15 μF/μm2and adds only a single mask to the process. At least some disclosed embodiments can support 12 V and even 20 V applications.

Regarding inventive distinctions, conventional solutions to mitigate voiding in the surface of the top plate materials such as polysilicon use an etch back after top plate metal fill and then redeposit top metal to try to eliminate the voids/seams. This requires these solutions in the case of polysilicon to include a second polysilicon deposition process, and a resulting polysilicon interface can be seen such as by a scanning electron microscope (SEM) inspection that is not present for disclosed top plate218ain disclosed trench capacitors because of a single top plate deposition process enabled by disclosed processing including a nitride pull back etch step. Another distinction is the low percentage of voids at a surface of the top plate218a, which is voids with a size larger than 0.1 μm being less than or equal to (≤1%), such as (≤0.1%). This enables reliable contact to be made to the top plate of disclosed trench capacitors when the area allotted in the IC design is sufficient to only provide a single contact for connection to the top plate. Other advantages for disclosed embodiments include relative simplicity and low implementation cost.

Disclosed embodiments can be used to form semiconductor die that may be discrete devices or part of integrated circuits integrated into a variety of assembly flows to form a variety of different devices and related products. The semiconductor die may include various elements therein and/or layers thereon, including barrier layers, dielectric layers, device structures, active elements and passive elements including source regions, drain regions, bit lines, bases, emitters, collectors, conductive lines, conductive vias, etc. Moreover, the semiconductor die can be formed from a variety of processes including bipolar, Insulated Gate Bipolar Transistor (IGBT), CMOS, BiCMOS and MEMS.

Those skilled in the art to which this disclosure relates will appreciate that many other embodiments and variations of embodiments are possible within the scope of the claimed invention, and further additions, deletions, substitutions and modifications may be made to the described embodiments without departing from the scope of this disclosure.