Quantization step size adjusting circuit using edge detections

A quantization step size adjusting circuit using edge detection techniques for adjusting quantization step sizes in sampling an image signal to provide a digital signal by controlling an image compression ratio in dependence upon a pixel density representation (levels of sophistication) of an image. The quantization step size adjusting circuit comprises a coordinate converter for providing the image signal representative of a luminance signal and color difference signals, an edge detector for detecting edge values representative of peripheral pixels of a plurality of addresses of the image signal designated by control signals, a block formatting circuit for formatting the image signal into a plurality of image blocks having a predetermined size of pixels, and a circuit for controlling quantization step sizes of the image signal in dependence upon a determination edge values representative of peripheral pixels of a plurality of addresses of the image signal designated by the control signals and a determination of a selected scale factor in accordance with the pixel density representation of the image.

FIELD OF THE INVENTION 
The present invention relates to a quanitzation step size adjusting circuit 
for use in an image compression method recommended by JPEG(the joint group 
of CCITT and ISO), and more particularly, to a quantization step size 
adjusting circuit in which an image is divided into a plurality of blocks 
and quantizing step size is varied in accordance with the image variations 
of the respective blocks to improve the S/N ratio. 
BACKGROUND OF THE INVENTION 
Generally, as shown in FIG. 1, the image compression method recommended by 
JPEG is carrried out after performing a discrete cosine transformation 
(DCT) conversion in order to carry out data compression within a digital 
image recording and reproducing device. Here, a quantizing step size is 
determined by a certain scaling factor S of a quantizing matrix which 
consists of 8.times.8 blocks, and in which the human optical 
characteristics are taken into account. Even if the quantizing step size 
is decided based on the certain scaling factor S, a sophisticated image 
can not be reproduced accurately and even a simple image requires a large 
amount of memories in its processing. 
SUMMARY OF THE INVENTION 
The present invention is intended to overcome the above described 
disadvantages of the prior art. 
Therefore, it is an object of the present invention to provide a 
quantization step size adjusting circuit using edge detections, in which a 
picture is divided into a plurality of blocks in such a manner that a 
sophisticated image is accorded with a large scaling factor S so as to 
minimize the quantizing step size and to decrease a data compression ratio 
and a simple image is accorded with a small scaling factor S' so as to 
enlarge the quantizing step size and to increase the data compression 
ratio to improve the a signal-to-noise (S/N) ratio. 
It is another object of the present invention to provide a quantization 
step size adjusting circuit using edge detections, in which the picture is 
divided into a plurality of blocks and the quantizing step size is varied 
corresponding to each block based on a level of sophistication of an image 
or the pixel density representation of the image in order to simplify the 
circuit. 
In order to achieve the above described objects, the present invention 
resides in a quantization step size adjusting circuit using edge 
detections. The quantization step size adjusting circuit comprises a 
control part 10 for controlling the whole system, a coordinate converting 
part 20 for storing luminance signals and chrominance signals separately 
in response to input R(Red), B(Blue), and G(Green) video signals, and edge 
detecting part 30 for extracting contour data for one frame by detecting 
an edge value according to an address of the control art in response to 
the input luminance signals and the chrominance signals from the 
coordinate converting part, a frame memory 40 for storing the extracted 
contour data of the edge detecting part based on the address value of the 
control part, a block formatting part 50 for summing up the contour data 
for each block after dividing the contour data for one frame of the frame 
memory into a predetermined number of sub-blocks, and a scaling factor 
generating part 60 for generating scaling factors according to the 
sophistication of the image in response to the input summed-up edge value 
for each block from the block formatting part 50.

DETAIL DESCRIPTION OF THE PREFERRED EMBODIMENT 
FIGS. 2A and 2B illustrate a block diagram of the quantization step size 
adjusting circuit using edge detections according to the present 
invention. As shown in FIGS. 2A and 2B, the quantization step size 
adjusting circuit comprises a control part 10 for controlling the system, 
a coordinate converting part 20 for separately storing luminance signals Y 
and chrominance signals C corresponding to input R,G,B video signals, an 
edge detecting part 30 for extracting contour data for one frame by 
detecting the edge values according to the address of the control part 10, 
in response to the input luminance signals Y and chrominance signals C 
from the coordinate converting section 20, a frame memory 40 for storing 
the contour data extracted from the edge detecting part 30 according to 
the address of the control part 10, a block formatting part 50 for 
outputting a summed-up output for each block after dividing the contour 
data for one frame of the frame memory 40 into a predetermined number of 
sub-blocks, and a scaling factor generating part 60 for generating scaling 
factors according to the block image status in response to the summed-up 
edge values for the respective blocks of the block formatting part 50. 
The edge detecting part 30 includes a latching part 31 for latching the 
values of peripheral pixels where the edge values are detected according 
to the address of the control part 10, a multiplier 32 for multiplying the 
latched peripheral pixel values of the latching part 31 double, a 
separator 33 for summing up the double-multiplied pixel values of the 
multiplier 32 by separating them into a negative number portion and a 
positive number portion, and a subtracter 34 for detecting the edge values 
by summing up the positive number portion and the negative number portion 
of the separator 33. 
The block formatting section 50 includes an adder 51 for summing up a 
predetermined number of edge value for the respective sub-blocks in 
response to the input edge value for one frame of the frame memory 40, and 
a latch 52 for carrying out a latching upon summing up the predetermined 
of edge values by the adder 51. 
The scaling factor generating part 60 includes a first scaling factor 
generator for deciding the range of a first scaling factor by comparing 
the output signals of the latch 52 with a first reference value, a second 
scaling factor generator for deciding the range of a second scaling factor 
by logically combining the first scaling factor range-over signals of the 
first scaling factor generator after comparing the output signals of the 
latch 52 with a second reference value, a third scaling factor generator 
for deciding the range of a third scaling factor by logically combining 
the second scaling factor range-over signals of the second scaling factor 
generator after comparing the output signals of the latch 52 with a third 
reference value, a fourth scaling factor generator for deciding the range 
of a fourth scaling factor by logically combining the third scaling factor 
range-over signals of the third scaling factor generator, and an encoder 
64 for encoding the scaling factor range deciding signals provided from 
the first to fourth scaling factor generator. 
The circuit of the present invention as above will now be described as to 
its operation and effects. 
First, the coordinate converting part 20 converts the input of R,G,B video 
signals into luminance signals Y and chrominance signals C, and stores 
into the frame memory. The present invention can be carried out using the 
luminance signals Y or the color signals C which are separately stored in 
the frame memory of the coordinate converting part 20, and the method 
using the chrominance signals C is similar to the conventional one and 
therefore, only the method using the luminance signals Y will be described 
below. 
The frame memory of the coordinate converting part 20 shown in FIG. 3A 
generates addresses X,Y from (1,1) to (510,510) except for the peripheral 
portions, where the peripheral addresses (X-1,Y-1) (X,Y-1) (X-1,Y) (X+1,Y) 
(X,Y+1) (X+1,Y+1) are generated for the respective addresses X,Y to read 
data, as shown in FIG. 3B. 
The data read by the coordinate converting part 20 is applied to the latch 
31 to be latched by clock signals of the control part 10. The latched 
output of the latch 31 is applied to the multiplier 32 from which the data 
is doubled. The output signals of the multiplier 32 are supplied to the 
separator 33 and separated into a negative number portion and positive 
number portion to be summed up together. 
The summed-up output of the separator 33 is applied to the subtracter 24 in 
which the positive number portion and the negative number portion are 
subtracted in order to detect the edge values. Under this condition, 
maskings in the directions of the X and Y axes are used in order to detect 
the edge values and the following table 1 shows examples of the summations 
of the maskings in the directions of X and Y axes. 
TABLE 1 
______________________________________ 
-1 -2 -1 -1 0 1 -2 -2 0 
0 0 0 -2 0 2 -2 0 2 
1 2 1 -1 0 1 0 2 2 
______________________________________ 
Therefore, the edge values of the addresses X,Y are as shown in table 2 
below; 
EQU 2{(X+1,Y)+(X,Y+1)+(X+1,Y+1)}-2{(X-1,Y-1)+(X,Y-1)+(X-1,Y)} 
TABLE 2 
______________________________________ 
(X-1,Y-1) (X,Y-1) (X+1,Y+1) 2 -2 0 
(X-1,Y) (X,Y) (X+1,Y) -2 0 2 
(X-1,Y+1) (X,Y+1) (X+1,Y+1) 0 2 2 
______________________________________ 
When the addresses X,Y excluding the peripheral portions are increased from 
(1,1) to (510,510) according to the control signals of the control part 10 
and the edge values for the respective addresses X,Y, which are detected 
by the subtracter 34 are stored into the frame memory 40. The edge values 
which are stored in the frame memory 40 are divided into 8.times.8 block 
units according to the control signals of the control part 10, and 64 
addresses are generated for each block. Therefore, when 64 edge values are 
summed up by the adder 51, they are cleared and the next block is latched 
by the latch 52. 
The latched output of the latch 52 is applied to an input terminal A of a 
first comparator 61, and the values of the latched output are compared 
with a first reference value which is input through an input terminal B of 
the comparator G1. If the latched output value of the latch 52 is smaller 
than the first reference value, a first scaling factor is determined and 
is input into a first input terminal of the encoder 64. 
On the other hand, if the latched output of the latch 52 is equal to or 
larger than the first reference value, the output value of the latch 52 is 
input into an input terminal C of a second comparator 62, and compared 
with a second reference value which is input through an input terminal D 
of the second comparator G2. 
If the latched output of the latch 52 is smaller than the second reference 
value, the output value of the first comparator 61 is input through an OR 
gate OR1 to an AND gate AND 1 and is logically combined with the output 
value of the second comparator 62. If the combined value is decided as a 
second scaling factor, then it is supplied to an input terminal 1 of the 
encoder 64. 
On the other hand, if the latched output of the latch 52 is equal to or 
larger than the second reference value, the output of the latch 52 is 
input into an input terminal E of a third comparator 63 and compared with 
a third reference value. If it is smaller than the third reference value, 
the output value of the second comparator 62 is input through an OR gate 
OR2 to an AND gate AND2, and is logically combined together with the data 
to be decided as a third scaling factor to supply to an input terminal 2 
of the encoder 64. 
On the other hand, if the output of the latch 52 is equal to or larger than 
the third reference value, the output of the third comparator 63 is input 
into an OR gate OR3 to be logically combined and decided as a fourth 
scaling factor for supplying to an input terminal 3 of the encoder 64. 
Accordingly, the encoder 64 encodes the scaling factors which are output in 
accordance with the sophistication of an image. 
As described above, the quantization step size adjusting circuit using edge 
detections according to the present invention includes a control part for 
controlling the system, a coordinate converting part for separately 
storing luminance signals and chrominance signals in response to the input 
R,G,B video signals, an edge detecting part for extracting contour data 
for one frame by detecting the edge values in according to the address of 
the control part in response to the input luminance signals and 
chrominance signals of the coordinate converting part, a frame memory for 
storing the contour data of the edge detecting part according to the 
address values of the control part, a block formatting part for summing up 
the edge values for each block after dividing the contour data for one 
frame of the frame memory into a predetermined number of sub-blocks, and a 
scaling factor generating part for generating scaling factors according to 
the level of sophistication of the block images in response to the input 
summed-up edge values for each block from the block image formatting part. 
Thus, in case of the block having sophisticated image signals, the 
quantizing step size is reduced so as to reduce the data compression ratio 
and in case of the block is representative of a simple image, the 
quantizing step size is enlarged so as to increase the data compression 
ratio for improving the S/N ratio.