Low power dual voltage mode receiver

A dual-voltage receiver, comprising a voltage detector. A high voltage Schmitt trigger coupled to the voltage detector. A low voltage Schmitt trigger coupled to the voltage detector. A combined level shifter coupled to the high voltage Schmitt trigger and the low voltage Schmitt trigger, wherein the high voltage Schmitt trigger is on and the low voltage Schmitt trigger is off when the voltage detector outputs a high voltage detect signal.

TECHNICAL FIELD

The present disclosure relates to a dual voltage mode receiver, and more particuarly to a dual voltage mode receiver for input/output applications.

BACKGROUND OF THE INVENTION

Some input/output interfaces require operation at multiple voltages. For example, an I2S interface can operate at either 3.3 V or 1.8 V, and Intel's HD-Audio specification allows for operation at 3.3 V and 1.5 V. Such interfaces must be tolerant of the higher voltages, which makes them difficult to operate at the lower voltage. In a CMOS design, this is because high-voltage transistors (suited for 3.3 V operation) have a large voltage threshold. When used with low voltage, the transistors are operated with very little overdrive, reducing their current drive, which reduces the speed of the circuit.

SUMMARY OF THE INVENTION

A dual-voltage receiver, comprising a voltage detector is provided. The dual-voltage receiver includes a high voltage Schmitt trigger and a low voltage Schmitt trigger, each connected to the voltage detector. A combined level shifter is connected to the high voltage Schmitt trigger and the low voltage Schmitt trigger, wherein the high voltage Schmitt trigger is on and the low voltage Schmitt trigger is off when the voltage detector outputs a high voltage detect signal.

DETAILED DESCRIPTION OF THE INVENTION

Some IO interfaces have operational requirements at multiple voltages. For example, an I2S interface can operate at either 3.3 V or 1.8 V, and Intel's HD-Audio specification allows for operation at 3.3 V and 1.5 V. Because of these voltage requirements, such interfaces must be tolerant of the higher voltages, which makes them difficult to operate at the lower voltage. In a CMOS design, this difficulty is encountered because high-voltage transistors (suited for 3.3 V operation) have a large voltage threshold. When used with low voltage, the transistors are operated with very little overdrive, reducing their current drive and the speed of the circuit.

Intel's HD audio specification, High Definition Audio Specification Revision 1.0a, dated Jun. 17, 2010, and which is hereby incorporated by reference for all purposes as set forth herein in its entirety, is particularly challenging due to the large difference of voltage, and the timing requirements imposed by the specification, as input receivers delays must be kept at a minimum.

The present disclosure is based on a comparator design. One disadvantage with a comparator-based design is its high power consumption. Because a comparator is a constant-biased circuit, it has a high quiescent current consumption, even when the data does not change state. The amount of power consumed is related to the speed of the circuit—the circuit must be biased to meet the timing requirements of the HD audio specification. The present disclosure uses circuits that are common to input receivers, such as a CMOS inverting Schmidt trigger, to solve the problem of high current consumption. By using different types of transistors, the receiver is split in two: one circuit that uses high voltage transistors for 3.3V operation, and one circuit that uses low voltage transistors for 1.5V operation. The output of each is then level shifted to the chip's core voltage and combined using an AND gate. As the optimum transistor type is used for each voltage mode, the performance of the receiver is also optimized for each voltage mode. This optimization allows for a design that is smaller, and has lower dynamic power consumption for a given performance.

To avoid voltage tolerance issues during 3.3 V operation in the low-voltage circuit, switches are used to disable the low-voltage circuit. Switches disconnect both the input signal and the supply voltage of the low-voltage circuit such that it is never exposed to any voltage above the transistors' limits. A voltage detector circuit is used to generate the controls of the switches. The switches use high-voltage transistors.

Notably, the present disclosure has no quiescent current consumption, is smaller in area and has higher performance at lower dynamic current consumption.

As used herein, “hardware” can include a combination of discrete components, an integrated circuit, an application-specific integrated circuit, a field programmable gate array, or other suitable hardware. As used herein, “software” can include one or more objects, agents, threads, lines of code, subroutines, separate software applications, two or more lines of code or other suitable software structures operating in two or more software applications or on two or more processors, or other suitable software structures. In one exemplary embodiment, software can include one or more lines of code or other suitable software structures operating in a general purpose software application, such as an operating system, and one or more lines of code or other suitable software structures operating in a specific purpose software application. As used herein, the term “couple” and its cognate terms, such as “couples” and “coupled,” can include a physical connection (such as a copper conductor), a virtual connection (such as through randomly assigned memory locations of a data memory device), a logical connection (such as through logical gates of a semiconducting device), other suitable connections, or a suitable combination of such connections.

FIG. 1is a diagram of a system100for a low-power dual voltage-mode receiver for digital input/output in accordance with an exemplary embodiment of the present disclosure. System100includes ESD protection102at the input, and voltage detector130having an output VDETthat is used to detect the voltage mode of operation (e.g. high or low). Depending on the detected mode, the configuration switches114,116,118,120,122,124,126and128select high voltage devices106or low voltage devices104for the amplifier and level shifters. In addition, the level shifter108and AND gate112are combined, as described in greater detail herein.

In operation, when the input voltage is a high voltage signal, such that the voltage detector signal VDETis high, switches116,120,124and126are closed and switches114,118and128are opened, so that low voltage devices104are isolated from the input voltage and to allow high voltage devices106to process the input signal. When the input voltage is a low voltage signal, such that the voltage detector signal VDETis low, switches116,120,124and126are open and switches114,118and128are closed, so that high voltage devices106are isolated from the input voltage and to allow low voltage devices104to process the input signal.

FIGS. 2A through 2Care circuit diagrams of a system200for a low-power dual voltage-mode receiver for digital input/output in accordance with an exemplary embodiment of the present disclosure. As shown inFIG. 2A, a series of devices are provided for protection against electrostatic discharge (ESD), which incorporates human body model (HEM) clamping plus charge device model (CDM) protection. The transistors include high voltage (H) devices having a thicker oxide layer, and low voltage devices (L) having a normal oxide layer.

In addition,FIG. 2Aincludes a low-voltage Schmitt trigger circuit followed by a low voltage inverter inFIG. 2B. The input is coupled to a resistor2and two series connected clamping diodes4and6. The source of a first NMOS high voltage transistor5is coupled to resistor2, and the gate of high voltage transistor5is coupled to an inverted voltage detector signal. The drain of a first NMOS low voltage transistor10is coupled to the drain of transistor5and the source is coupled to voltage common, with a resistor-connected gate to common through resistor8. A second high voltage NMOS transistor12is also coupled between the drain of transistor5and ground, and the gate of transistor12is coupled to the voltage detector signal. The drain of transistor5is also coupled to low voltage transistors forming a low voltage hysteresis inverter.

A third high voltage transistor18has a gate coupled to the inverted voltage detect signal and is coupled from the second series-connected clamping diode6to the drain of an NMOS high voltage transistor14, which has a gate coupled to the voltage detect signal. The source of transistor18is coupled to the gate of NMOS high voltage transistor16, which has a drain and source coupled to ground. The low voltage hysteresis inverter is formed by two series connected low voltage PMOS transistors20and22that are coupled in series to two series connected low voltage NMOS transistors24and26. The gates of the four series-connected low-voltage transistors are coupled to the drain of transistor5. The source of low voltage PMOS transistor30is coupled to the junction of transistors20and and the drain of transistor30is coupled to ground, the source of a low voltage NMOS transistor28is coupled to the junction of the first and second low voltage NMOS transistors24and26, and the drain is coupled to the source of transistor18. The gates of transistors28and30are coupled to the junction between the first and second series connected PMOS transistors20and22and the first and second series connected NMOS transistors24and26.

InFIG. 2B, two series-connected low voltage transistors (PMOS32and NMOS34) are coupled between the source of transistor18and ground, with gates connected to the junction between the first and second series connected PMOS transistors20and22and the first and second series connected NMOS transistors24and26. Two additional series-connected low voltage transistors (PMOS40and NMOS38) are coupled to the drain of PMOS low voltage transistor42and voltage common, with gates connected to the junction between the first and second series connected PMOS transistors20and22and the first and second series connected NMOS transistors24and26. The source of a low voltage PMOS transistor44is coupled to the source of transistor42, and the drain of transistor44is coupled to the source of low voltage PMOS transistor46. The drain of transistor46is coupled to the source of low voltage NMOS transistor48. The drains of transistors46and48are coupled to the gate of transistor42. The gate of transistor44is coupled to the drains of transistor38and40.

In addition, the drain of a high voltage NMOS transistor50is coupled the drain of transistor48, and the source of transistor50is coupled to voltage common. The gate of transistor50is coupled to a voltage detect signal.

A combined level shifter with an AND gate is formed by a low voltage PMOS transistor54, with a gate coupled to the gates of transistors38and40. The drain of transistor54is coupled to the drain of a high voltage PMOS transistor56, which has a source coupled to the source of transistor54. The drain of low voltage NMOS transistor58is coupled to the drain of transistor56, and the gate of transistor58is coupled to the gate of transistor54. The source of transistor58is coupled to the drains of high voltage NMOS transistors52and60, and the sources of transistors52and60are coupled to voltage common. The gate of transistor52is coupled to an inverted voltage detect signal, and the gate of transistor60is coupled to the gate of transistor56.

The drain of transistor62is coupled to the drain of low voltage NMOS transistor64. The gates of transistors62and64are coupled to the drains of transistors54,56and58.

FIG. 2Cincludes a high-voltage Schmitt trigger circuit, andFIG. 2Bincludes combined level shifter circuits and AND gate that can be used for low voltage or high voltage level shifting, depending upon the input state. The high voltage (HV) and low voltage (LV) devices can be distinguished based on oxide coating thickness, where the HV devices have thicker oxide coatings that the LV devices.

FIG. 2Cincludes three series-connected high voltage PMOS transistors66,68and70coupled in series to two series-connected high voltage NMOS transistors72and74. The gates of transistors68,70,72and74are coupled to resistor2, and the gate of transistor66is coupled to the inverted voltage detect signal. The source of high voltage PMOS transistor78is coupled to the junction of transistors68and70and the drain of transistor78is coupled to voltage common. The source of high voltage NMOS transistor76is coupled to the junction of transistors72and74and the drain of transistor76is coupled to the source of transistor66, which is net Vdd or VIO. The gates of transistors76and78are coupled to the junction of transistors70and72.

The drain of high voltage NMOS transistor80is coupled to the junction of transistors70and72, and the source of transistor80is coupled to voltage common. The gate of transistor80is coupled to an inverted voltage detect signal. The gates of high voltage PMOS transistor84and high voltage NMOS transistor82are coupled to the junction of transistors70and72, and the drain of transistor84is coupled to the drain of transistor82.