STRESS AND WARPAGE MODULATING STRUCTURE FOR MULTI-STACKED WAFER AND DIE LEVEL BONDING PACKAGES

A stress modulating device including a semiconductor substrate, a first insulating layer formed over a first side of the semiconductor substrate, a second insulating layer formed over the first insulating layer, a third insulating layer formed over a second side of the semiconductor substrate, a fourth insulating layer formed over the third insulating layer, and a fifth insulating layer formed over the fourth insulating layer for incorporation in multi-stack package assemblies for reducing stress, strain, and/or warpage on the active elements within the package assembly.

BACKGROUND

Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment. Semiconductor devices are fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material over a substrate, and patterning the various material layers using lithography to form circuit components and elements thereon. As the semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, improved performance, and lower costs, challenges from both fabrication and design issues have resulted in the development of a number of three-dimensional designs including, for example, Metal-Oxide-Silicon Field Effect Transistors (MOS-FET), Field Effect Transistors (FET), Fin Field Effect Transistor (FinFET), Gate-All-Around (GAA) devices (nanowires/nanosheets), GAA devices configured as Complementary Field Effect Transistor (CFET) devices, and Multi-Bridge Channel Field Effect Transistor (MBCFET) devices (nanosheets).

Integrated circuit (IC) manufacturing processes are divided into front-end-of-line (FEOL) processing and back-end-of-line (BEOL) processing, in some instances. FEOL processes generally encompass those processes related to fabricating functional elements, such as transistors and resistors, in or on a semiconductor substrate. For example, FEOL processes typically include forming isolation features, gate electrodes and dielectrics, and source and drain features (also referred to as source/drain or S/D features). BEOL processes generally encompass those processes related to fabricating a multilayer interconnect (MLI) features that interconnects the functional IC elements and structures fabricated during FEOL processing to provide connection to and enable operation of the resulting IC devices.

Stress analysis and control at both chip and package levels is becoming more of a consideration as dimensions continue to shrink and the use of chip-on-chip and chip-on-wafer assemblies increases. The reduction of stress and warpage between and across semiconductor components will tend to improve performance and the reliability of the resulting semiconductor devices. The chips, packages, and/or boards in stacked packages are each a potential source of structural and thermal stress that tend to increase along with the level of integration and complexity. Process and/or structural modifications that reduce and/or compensate for some of the mechanical and thermal stresses resulting from the selection and configuration of the material layers, bonding structures, semiconductor devices, complex assemblies, and/or the operation of such devices are helpful in reducing defects, improving performance, and/or increasing the lifetime of the resulting devices.

DETAILED DESCRIPTION

FIGS.1A-Care cross-sectional views of a stress and warpage modulating structure (SWM structure) during a manufacturing process, according to some embodiments. InFIG.1Aa semiconductor substrate102is prepared and a frontside pad oxide layer10f0and a backside pad oxide layer104b0are formed on opposing sides of the semiconductor substrate. The pad oxide layers will typically be formed using a process selected from atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition CVD, plasma enhanced chemical vapor deposition (PECVD), thermal oxidation, self-aligned monolayer (SAM) deposition and/or one or more other suitable method(s) and, in some embodiments, will comprise suitable materials in addition to or other than silicon dioxide. In some embodiments the frontside pad oxide layer104f0and a backside pad oxide layer104b0have a thickness of about 40 Å although layers having other thicknesses are used in some embodiments. In some embodiments, the pad oxide layers are formed using a thermal oxidation process to obtain an oxide layer having a thickness of 10-200 Å. Oxide layers of less than 10 Å tend to have reduced dielectric performance and/or undesirable variations in the thickness across the wafer. Oxide layers of greater than 200 Å tend to increase processing time without a corresponding improvement in the performance of the resulting layer and/or cause issues during downstream processing.

A frontside silicon nitride layer106f0and a backside silicon nitride layer106b0are then formed on the corresponding frontside pad oxide layer104f0and a backside pad oxide layer104b0. In some embodiments the silicon nitride layers have a thickness of about 380 Å although layers having other thicknesses are used in some embodiments. The silicon nitride layers will typically be formed using a process selected from atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition CVD, plasma enhanced chemical vapor deposition (PECVD), thermal oxidation, self-aligned monolayer (SAM) deposition and/or one or more other suitable method(s) and, in some embodiments, will comprise suitable materials in addition to or other than silicon nitride. The semiconductor substrate102, in combination with the frontside pad oxide layer104f0, the backside pad oxide layer104b0, the frontside silicon nitride layer106f0, and the backside silicon nitride layer106b0comprise a zero layer structure100A. In some embodiments, the silicon nitride layers are formed using a thermal nitridation process to obtain a silicon nitride layer having a thickness of 100-2000 Å. In some embodiments, the relative thicknesses of the pad oxide and silicon nitride layers are selected to provide an oxide:nitride thickness ratio of 1:9 to 1:10. Nitride layers of less than 100 Å tend to have reduced dielectric performance and/or undesirable variations in the thickness across the wafer. Nitride layers of greater than 2000 Å tend to increase processing time without a corresponding improvement in the performance of the resulting layer and/or cause issues during downstream processing. Relative thicknesses of the pad oxide and silicon nitride layers resulting in a oxide:nitride thickness ratio greater than 1:9 or less than 1:10 tend to have reduced dielectric and/or mechanical performance when compared with those combinations having relative thicknesses within the range of 1:9 and 1:10.

InFIG.1B, the zero layer structure100A is modified by the addition of a first frontside extra oxide layer104f1and a first frontside silicon nitride layer106f1. In some embodiments, a first frontside extra oxide layer104f1has a thickness of about 100 Å although layers having other thicknesses are used in some embodiments. The zero layer structure is further modified by the addition of a first backside silicon nitride layer106b1that is formed over the backside silicon nitride layer106b0without an intervening oxide layer with an interface109and provide a double nitride layer106b0+106b1on the backside of the first layer structure100B. In some embodiments, the first frontside silicon nitride layer106f1and the first backside silicon nitride layer106b1have a thickness of about 380 Å although one or both of the first silicon nitride layers having other thicknesses are used in some embodiments. In some embodiments, the zero layer structure100A is rotated to a predetermined offset angle120that is Θ degrees offset from the orientation used during formation of the underlying layer(s). In some embodiments, the offset angle is between 0° and 90°. In some embodiments, successive depositions are conducted at offset angles of 15°, 30°, 45°, 60°, 75°, or 90°. In some embodiments, the specific equipment utilized for rotating the substrate to create the predetermined Θ degree offset angle will have inherent mechanical interference positions that define forbidden angles of rotation for the specific equipment. Using the machine-specific information, the range of acceptable values for the predetermined Θ degree offset angle for processes utilizing such machines will be adjusted accordingly to exclude the forbidden angles. In some embodiments, a narrow range of values on either side of the forbidden angles will also be excluded to ensure proper operation of the machine.

InFIG.1C, the first layer structure100B is modified by removing the first frontside extra oxide layer104f1and a first frontside silicon nitride layer106f1to form a SWM structure100C. In some embodiments, the pad oxide and silicon nitride layers are removed using a dry-etch or plasma etch process. In some embodiments, plasma etching (PE) or reactive ion etching (RIE) of a substrate material(s) is/are performed using halogen-containing reactive gasses excited by an electromagnetic field to dissociate into ions. Reactive or etchant gases include, for example, CF4, SF6, NF3, Cl2, CCl2F2, SiCl4, BCl2, or combinations thereof, although other semiconductor-material etchant gases are also envisioned within the scope of the present disclosure. In some embodiments, at least one of the substrate materials is wholly or partially removed using a wet etch in which a liquid chemical etch solution including one or more etchants such as citric acid (C6H8O7), hydrogen peroxide (H2O2), nitric acid (HNO3), sulfuric acid (H2SO4), hydrochloric acid (HCl), acetic acid (CH3CO2H), hydrofluoric acid (HF), buffered hydrofluoric acid (BHF), phosphoric acid (H3PO4), ammonium fluoride (NH4F) potassium hydroxide (KOH), ethylenediamine pyrocatechol (EDP), TMAH (tetramethylammonium hydroxide), or a combination thereof is used to remove the target material(s).

FIG.1Dis a flowchart of a portion of a manufacturing process100D for the production of SWM structures according to some embodiments of the structures ofFIGS.1A-Cincluding operation S102during which the semiconductor substrate is prepared for pad oxide deposition, operation S104during which the zero layer pad oxide layers are formed on both the frontside (FS) and backside (BS) surfaces of the semiconductor substrate102and operation S106during which the zero layer silicon nitride layers are formed on both the FS and BS surfaces of the semiconductor substrate102to complete the zero layer structure100A. The zero layer structure100A is then further modified in operation S108during which the first layer extra oxide is formed on the FS of the zero layer structure100A, followed by an optional operation S110during which the zero layer structure100A is rotated to an offset angle of Θ°, e.g., 45°, and operation S112during which the first layer silicon nitride is deposited on the FS and BS of the zero layer structure100A to complete first layer structure100B. In operation S114the first layer of silicon nitride and the first layer of extra oxide are removed from the FS of the first layer structure100B to complete an embodiment of a SWM structure100C. The SWM structure100C can then be utilized in multi-stacked die/wafer and wafer/wafer comprising systems of integrated chips (SOIC) and chip on wafer on substrate (CoWoS) packaging configurations.

FIGS.2A-Care cross-sectional views of a stress and warpage modulating structure (SWM structure) during a manufacturing process, according to some embodiments. InFIG.2Aa semiconductor substrate102is prepared and a frontside pad oxide layer104f0and a backside pad oxide layer104b0are formed on opposing sides of the semiconductor substrate. The pad oxide layers will typically be formed using one or more of the processes discussed above in connection withFIG.1Aand, in some embodiments, will comprise suitable materials in addition to or other than silicon dioxide. In some embodiments the frontside pad oxide layer104f0and a backside pad oxide layer104b0have a thickness of about 40 Å although pad oxide layers having other thicknesses are used in some embodiments.

A frontside silicon nitride layer106f0and a backside silicon nitride layer106b0are then formed on the corresponding frontside pad oxide layer104f0and a backside pad oxide layer104b0. In some embodiments the silicon nitride layers have a thickness of about 380 Å although layers having other thicknesses are used in some embodiments. The silicon nitride layers will typically be formed using a process using one or more of the processes discussed above in connection withFIG.1Aand, in some embodiments, will comprise suitable materials in addition to or other than silicon nitride. The semiconductor substrate102, in combination with the frontside pad oxide layer104f0, the backside pad oxide layer104b0, the frontside silicon nitride layer106f0, and the backside silicon nitride layer106b0comprise a zero layer structure200A.

InFIG.2Bthe zero layer structure200A is modified by the addition of a first frontside extra oxide layer104f1and a first frontside silicon nitride layer106f1. In some embodiments a first frontside extra oxide layer104f1has a thickness of about 100 Å although layers having other thicknesses are used in some embodiments. The zero layer structure is further modified by the addition of a first backside silicon nitride layer106b1that is formed over the backside silicon nitride layer106b0without an intervening oxide layer with an interface109and provide a double nitride layer106b0+106b1on the backside of the first layer structure100B. In some embodiments the first frontside silicon nitride layer106f1and the first backside silicon nitride layer106b1have a thickness of about 200-2000 Å, e.g., 800 Å, although one or both of the first silicon nitride layers having other thicknesses are used in some embodiments. In some embodiments the zero layer structure200A is rotated to a predetermined offset angle120that is Θ degrees offset from the orientation used during formation of the underlying layer(s). In some embodiments the offset angle is between 0° and 90°. In some embodiments, successive depositions are conducted at offset angles of 15°, 30°, 45°, 60°, 75°, or 90°.

InFIG.2Cthe first layer structure200B is modified by removing the first frontside extra oxide layer104f1and a first frontside silicon nitride layer106f1to form a SWM structure200C. In some embodiments, the extra oxide and silicon nitride layers are removed using a dry-etch, plasma etch, and/or wet etch processes as detailed above with reference toFIG.1C.

FIG.2Dis a flowchart of a portion of a manufacturing process200D for the production of SWM structures according to some embodiments of the structures ofFIGS.2A-Cincluding operation S202during which the semiconductor substrate is prepared for pad oxide deposition, operation S204during which the zero layer pad oxide layers are formed on both the frontside (FS) and backside (BS) surfaces of the semiconductor substrate102and operation S206during which the zero layer silicon nitride layers are formed on both the FS and BS surfaces of the semiconductor substrate102to complete the zero layer structure200A. The zero layer structure200A is then further modified in operation S208during which the first layer extra oxide is formed on the FS of the zero layer structure200A, followed by an optional operation S210during which the zero layer structure200A is rotated to an offset angle of Θ°, e.g., 45°, and operation S212during which the thicker first layer silicon nitride is deposited on the FS and BS of the zero layer structure200A to complete first layer structure200B. In operation S214, the first layer silicon nitride and the first layer extra oxide are removed from the FS of the first layer structure200B are removed to complete an embodiment of a SWM structure200C. The SWM structure200C can then be utilized in multi-stacked die/wafer and wafer/wafer comprising systems of integrated chips (SOIC) and chip on wafer on substrate (CoWoS) packaging configurations.

FIGS.3A-Dare cross-sectional views of a stress and warpage modulating structure (SWM structure) during a manufacturing process, according to some embodiments. InFIG.3Aa semiconductor substrate102is prepared and a frontside pad oxide layer104f0and a backside pad oxide layer104b0are formed on opposing sides of the semiconductor substrate. The pad oxide layers will typically be formed using one or more of the processes discussed above in connection withFIG.1Aand, in some embodiments, will comprise suitable materials in addition to or other than silicon dioxide. In some embodiments the frontside pad oxide layer104f0and a backside pad oxide layer104b0have a thickness of about 40 Å although pad oxide layers having other thicknesses are used in some embodiments.

A frontside silicon nitride layer106f0and a backside silicon nitride layer106b0are then formed on the corresponding frontside pad oxide layer104f0and a backside pad oxide layer104b0. In some embodiments the silicon nitride layers have a thickness of about 380 Å although layers having other thicknesses are used in some embodiments. The silicon nitride layers will typically be formed using a process using one or more of the processes discussed above in connection withFIG.1Aand, in some embodiments, will comprise suitable materials in addition to or other than silicon nitride. The semiconductor substrate102, in combination with the frontside pad oxide layer104f0, the backside pad oxide layer104b0, the frontside silicon nitride layer106f0, and the backside silicon nitride layer106b0comprise a zero layer structure300A.

InFIG.3B, the zero layer structure300A is modified by the addition of a first frontside extra oxide layer104f1and a first frontside silicon nitride layer106f1. In some embodiments the first frontside extra oxide layer104f1has a thickness of about 20-200 Å although layers having other thicknesses are used in some embodiments. The zero layer structure is further modified by the addition of a first backside extra oxide layer104b1and a first backside silicon nitride layer106b1that is formed over the backside silicon nitride layer106b0on the backside of the first layer structure300B. In some embodiments, the first backside extra oxide layer104b1has a thickness of about 20-200 Å although layers having other thicknesses are used in some embodiments. In some embodiments, the first frontside silicon nitride layer106f1and first backside silicon nitride layer106b1have a thickness of about 200-2000 Å, e.g., 800 Å, although one or both of the first silicon nitride layers having other thicknesses are used in some embodiments. In some embodiments the zero layer structure300A is rotated to a predetermined offset angle120that is Θ degrees offset from the orientation used during formation of the underlying layer(s). In some embodiments the offset angle is between 0° and 90°. In some embodiments, successive depositions are conducted at offset angles of 15°, 30°, 45°, 60°, 75°, or 90°.

InFIG.3C, the first layer structure300B is modified by removing the first frontside extra oxide layer104f1and a first frontside silicon nitride layer106f1to form an intermediate SWM structure300C. In some embodiments, the extra oxide and silicon nitride layers are removed using a dry-etch, plasma etch, and/or wet etch processes as detailed above with reference toFIG.1C.

InFIG.3D, the intermediate SWM structure300C is modified by the repeated formation of additional N−1 frontside extra oxide layers104fN−1, backside extra oxide layers104bN−1, frontside silicon nitride layers106fN−1, and backside silicon nitride layers106bN−1as detailed above with reference toFIG.3B. The additional depositions are then followed by removing each of the additional N−1 frontside extra oxide layers104fN−1and frontside silicon nitride layers106fN−1to form SWM structure300D in which the backside of the SWM structure300D includes N layers of alternating layers of backside extra oxide layers104bNand backside silicon nitride layers106bN. In some embodiments, the extra oxide and silicon nitride layers are removed using a dry-etch, plasma etch, and/or wet etch processes as detailed above with reference toFIG.1C.

FIG.3Eis a flowchart of a portion of a manufacturing process300E for the production of SWM structures according to some embodiments of the structures ofFIGS.3A-Dincluding operation S302during which the semiconductor substrate is prepared for pad oxide deposition, operation S304during which the zero layer pad oxide layers are formed on both the frontside (FS) and backside (BS) surfaces of the semiconductor substrate102and operation S306during which the zero layer silicon nitride layers are formed on both the FS and BS surfaces of the semiconductor substrate102to complete the zero layer structure300A. The zero layer structure300A is then passed into optional operation S308during which the zero layer structure300A is rotated to an offset angle of Θ°, e.g., 45°, and operation S310during which the first layer extra oxide is formed on the FS of the zero layer structure300A, and operation S312during which the thicker first layer silicon nitride is deposited on the FS and BS of the zero layer structure200A to complete first layer structure200B. In operation S214the first layer silicon nitride and the first layer extra oxide are removed from the FS of the first layer structure200B are removed to complete an embodiment of a SWM structure200C. The SWM structure200C can then be utilized in multi-stacked die/wafer and wafer/wafer comprising systems of integrated chips (SOIC) and chip on wafer on substrate (CoWoS) packaging configurations.

FIGS.4A-Dare cross-sectional views of a stress and warpage modulating structure (SWM structure) during a manufacturing process, according to some embodiments. InFIG.4A, a semiconductor substrate102is prepared and a frontside pad oxide layer104f0and a backside pad oxide layer104b0are formed on opposing sides of the semiconductor substrate. The pad oxide layers will typically be formed using one or more of the processes discussed above in connection withFIG.1Aand, in some embodiments, will comprise suitable materials in addition to or other than silicon dioxide. In some embodiments the frontside pad oxide layer104f0and a backside pad oxide layer104b0have a thickness of about 40 Å although pad oxide layers having other thicknesses are used in some embodiments.

A frontside silicon nitride layer106f0and a backside silicon nitride layer106b0are then formed on the corresponding frontside pad oxide layer104f0and a backside pad oxide layer104b0. In some embodiments the silicon nitride layers have a thickness of about 380 Å although layers having other thicknesses are used in some embodiments. The silicon nitride layers will typically be formed using a process using one or more of the processes discussed above in connection withFIG.1Aand, in some embodiments, will comprise suitable materials in addition to or other than silicon nitride. The semiconductor substrate102, in combination with the frontside pad oxide layer104f0, the backside pad oxide layer104b0, the frontside silicon nitride layer106f0, and the backside silicon nitride layer106b0comprise a zero layer structure400A.

InFIG.4B, the zero layer structure400A is modified by the implanting oxygen into the backside silicon nitride layer106b0to obtain a SiON composition (alternatively SiN:OX) forming a backside SiN:OX layer112b0in place of the initially formed backside silicon nitride layer106b0to form an intermediate SWM structure400B. In some embodiments the backside SiN:OX layer112b0will have a thickness similar to that of the initially deposited of about 380 Å although layers having other thicknesses are used in some embodiments.

InFIG.4C, the intermediate SWM structure400B is then modified by the addition of a first frontside extra oxide layer104f1and a first frontside silicon nitride layer106f1to form a first layer structure400C. In some embodiments the first frontside extra oxide layer104f1has a thickness of about 20-200 Å, e.g., 40 Å, although layers having other thicknesses are used in some embodiments. The intermediate SWM structure400B is further modified by the addition of a first backside silicon nitride layer106b1that is formed over the backside SiN:OX layer112b0on the backside of the intermediate SWM structure400B. In some embodiments the first frontside silicon nitride layer106f1and first backside silicon nitride layer106b1have a thickness of about 200-2000 Å, e.g., 800 Å, although one or both of the first silicon nitride layers having other thicknesses are used in some embodiments. In some embodiments the intermediate SWM structure400B is rotated to a predetermined offset angle that is Θ degrees offset from the orientation used during formation of the underlying layer(s) between the formation of successive layers. In some embodiments the offset angle is between 0° and 90°. In some embodiments, successive depositions are conducted at offset angles of 15°, 30°, 45°, 60°, 75°, or 90°.

InFIG.4D, the first layer structure400C is modified by removing the first frontside extra oxide layer104f1and a first frontside silicon nitride layer106f1to form a SWM structure400D. In some embodiments, the extra oxide and silicon nitride layers are removed using a dry-etch, plasma etch, and/or wet etch processes as detailed above with reference toFIG.1C.

FIG.4Eis a flowchart of a portion of a manufacturing process400E for the production of SWM structures according to some embodiments of the structures ofFIGS.4A-Dincluding operation S402during which the semiconductor substrate is prepared for pad oxide deposition, operation S404during which the zero layer pad oxide layers are formed on both the frontside (FS) and backside (BS) surfaces of the semiconductor substrate102and operation S406during which the zero layer silicon nitride layers are formed on both the FS and BS surfaces of the semiconductor substrate102to complete the zero layer structure400A. In operation S408, the BS silicon nitride layer of the zero layer structure400A is implanted with oxygen to convert the initially deposited silicon nitride into a SiN:OX material. In operation S410the first layer extra oxide is formed on the FS of the intermediate SWM structure400B and then passed into optional operation S412during which the intermediate SWM structure400B is rotated to an offset angle of Θ°, e.g., 45°, and operation S414during which the first silicon nitride layers are formed on the FS and BS of the intermediate SWM structure400B. In operation S416the first layer silicon nitride and the first layer extra oxide are removed from the FS of the first layer structure400C to complete an embodiment of a SWM structure400D. The SWM structure400D is then ready to be used as a structural component in multi-stacked die/wafer and wafer/wafer comprising, e.g., systems of integrated chips (SOIC) and chip on wafer on substrate (CoWoS) packaging configurations.

FIGS.5A-Eare cross-sectional views of a stress and warpage modulating structure (SWM structure) during a manufacturing process, according to some embodiments. InFIG.5Aa semiconductor substrate102is prepared and a frontside pad oxide layer104f0and a backside pad oxide layer104b0are formed on opposing sides of the semiconductor substrate. The pad oxide layers will typically be formed using one or more of the processes discussed above in connection withFIG.1Aand, in some embodiments, will comprise suitable materials in addition to or other than silicon dioxide. In some embodiments the frontside pad oxide layer104f0and a backside pad oxide layer104b0have a thickness of about 40 Å although pad oxide layers having other thicknesses are used in some embodiments.

A frontside silicon nitride layer106f0and a backside silicon nitride layer106b0are then formed on the corresponding frontside pad oxide layer104f0and a backside pad oxide layer104b0. In some embodiments the silicon nitride layers have a thickness of about 380 Å although layers having other thicknesses are used in some embodiments. The silicon nitride layers will typically be formed using a process using one or more of the processes discussed above in connection withFIG.1Aand, in some embodiments, will comprise suitable materials in addition to or other than silicon nitride. The semiconductor substrate102, in combination with the frontside pad oxide layer104f0, the backside pad oxide layer104b0, the frontside silicon nitride layer106f0, and the backside silicon nitride layer106b0comprise a zero layer structure500A.

InFIG.5B, the zero layer structure500A is modified by the implanting oxygen into the backside silicon nitride layer106b0to obtain a SiON composition (alternatively SiN:OX) forming a backside SiN:OX layer112b0in place of the initially formed backside silicon nitride layer106b0to form a modified zero layer structure500B. In some embodiments the backside SiN:OX layer112b0will have a thickness similar to that of the initially deposited of about 380 Å although layers having other thicknesses are used in some embodiments.

InFIG.5C, the modified zero layer structure500B is then modified by the addition of a first frontside extra oxide layer104f1, a first backside extra oxide layer104b1, and a first frontside silicon nitride layer106f1to form a first layer structure500C. In some embodiments the first frontside extra oxide layer104f1has a thickness of about 20-200 Å, e.g., 40 Å, although layers having other thicknesses are used in some embodiments. The intermediate SWM structure500B is further modified by the addition of a first backside silicon nitride layer106b1that is formed over the first backside extra oxide layer104b1on the backside of the intermediate SWM structure500B to obtain the first layer structure500C. In some embodiments the first frontside silicon nitride layer106f1and first backside silicon nitride layer106b1have a thickness of about 200-2000 Å, e.g., 800 Å, although one or both of the first silicon nitride layers having other thicknesses are used in some embodiments. In some embodiments the intermediate SWM structure500B is rotated to a predetermined offset angle that is Θ degrees offset from the orientation used during formation of the underlying layer(s) between the formation of successive layers. In some embodiments the offset angle is between 0° and 90°. In some embodiments, successive depositions are conducted at offset angles of 15°, 30°, 45°, 60°, 75°, or 90°.

InFIG.5D, the first layer structure500C is modified by removing the first frontside extra oxide layer104f1and a first frontside silicon nitride layer106f1to form an intermediate SWM structure500D. In some embodiments, the extra oxide and silicon nitride layers are removed using a dry-etch, plasma etch, and/or wet etch processes as detailed above with reference toFIG.1C.

InFIG.5E, the intermediate SWM structure500D is further modified by the repeated formation of additional N−1 frontside extra oxide layers104fN−1, backside extra oxide layers104bN−1, frontside silicon nitride layers106fN−1, and backside silicon nitride layers106bN−1as detailed above with reference toFIG.5D. The additional depositions are then followed by removing each of the additional N−1 frontside extra oxide layers104fN−1and frontside silicon nitride layers106fN−1to form SWM structure500E in which the backside of the SWM structure500E includes N layers of alternating layers of backside extra oxide layers104bNand backside silicon nitride layers106bN. In some embodiments, the thicknesses of the alternating layers of backside extra oxide layers104bNand backside silicon nitride layers106bNare constant while in other embodiments one or both of the alternating layers of backside extra oxide layers104bNand backside silicon nitride layers106bNhave varied thicknesses, e.g., increasing thickness of the backside silicon nitride layers from the first backside silicon nitride layer106b1to106bNthe first backside silicon nitride layer. In some embodiments, the extra oxide and silicon nitride layers are removed using a dry-etch, plasma etch, and/or wet etch processes as detailed above with reference toFIG.5D.

FIG.5Fis a flowchart of a portion of a manufacturing process500F for the production of SWM structures according to some embodiments of the structures ofFIGS.5A-Eincluding operation S502during which the semiconductor substrate is prepared for pad oxide deposition, operation S504during which the zero layer pad oxide layers are formed on both the frontside (FS) and backside (BS) surfaces of the semiconductor substrate102and operation S506during which the zero layer silicon nitride layers are formed on both the FS and BS surfaces of the semiconductor substrate102to complete the zero layer structure500A. In operation S508the BS silicon nitride layer of the zero layer structure500A is implanted with oxygen to convert the initially deposited silicon nitride into a SiN:OX material and form the modified zero layer structure500B. In optional operation S510the modified zero layer structure500B is rotated to an offset angle of Θ°, e.g., 45°, after which first layer extra oxide is formed on the FS of the intermediate SWM structure500B in operation S512. In operation S514the first silicon nitride layers are formed on the FS and BS of the modified zero layer structure500B to form a first layer structure500C. In operation S516the first layer silicon nitride and the first layer extra oxide are removed from the FS of the first layer structure500C to form an intermediate SWM structure500D. The intermediate SWM structure500D is then further modified with the repeated application of operations S512-S516(and optionally, operation S510) to form a series of alternating layers of silicon oxide and silicon nitride on the backside of the intermediate SWM structure500D. After a predetermined number (N−1) additional alternating layers are formed the SWM structure500E is complete and can be utilized in multi-stacked die/wafer and wafer/wafer packaging assemblies comprising, e.g., systems of integrated chips (SOIC) and chip on wafer on substrate (CoWoS) packaging configurations.

The performance of the SWM structures within a multi-stacked die/wafer and wafer/wafer packaging assembly is a function of the configuration of the particular SWM structure including, for example, the thickness of the semiconductor substrate, the thickness and number of the silicon dioxide layers remaining on the frontside and backside of the semiconductor substrate, the thickness and number of the silicon nitride layers remaining on the frontside and backside of the semiconductor substrate. Other factors will include the manner of construction of the layers present, the angular offsets used between adjacent deposition layers, the presence of one or more modified deposition layers, e.g., SiN:OX layers, and the method and materials used to attach the SWM structure to a structure within the multi-stacked die/wafer or wafer/wafer packaging assembly. When properly utilized some embodiments of the SWM structures will improve the uniformity of the deposited layers and avoid stress cracking that provide channels to underlying layers and compromise etch processes.

FIGS.6A-Hare cross-sectional views of a multi-stack wafer/die level package during a manufacturing process that incorporates a SWM structure according to some embodiments.FIG.6Ais a cross-sectional view of a first semiconductor device202A after the addition of an interposer and formation of through silicon vias204(TSV).FIG.6Bis a cross-sectional view reflecting the results of a subsequent operation during which μ-bump structures, e.g., copper bumps206A have been formed on the frontside of the first semiconductor device202A.FIG.6Cis a cross-sectional view of an assembly including a second semiconductor device202B comprising one or more semiconductor die208and a corresponding plurality of copper bumps206B that has been inverted and mounted, frontside-to-frontside onto the first semiconductor device202A using, in some embodiments, frontside die-to-wafer (D2W) bonding processes. In some embodiments, an underfill material210is used for filing spaces between the components or elements that are configured as the second semiconductor device202B as shown inFIG.6C.

In some embodiments, the assembly comprising the first semiconductor device202A and the second semiconductor device202B are inverted and a carrier202C is mounted on the backside of the second semiconductor device as shown inFIG.6E. As shown inFIG.6F, a portion of the backside of the first semiconductor device202A is removed to thin the assembly and expose a lower surface (relative to the first semiconductor device) of the TSVs. In some embodiments as shown inFIGS.6F and6Ga backside portion of the semiconductor dies208is removed and replaced with, e.g., a silicon oxide layer214A or a combination of silicon oxide and silicon nitride214B. As shown inFIG.6H, in some embodiments a stress and warpage modulating (SWM) structure216is then mounted on the backside of the first semiconductor device202A for reducing the detrimental effects associated with stress, strain, and warpage on the performance and/or lifetime of the resulting multi-stack package.

FIGS.7A-Dare cross-sectional views of embodiments of multi-stack wafer/die level packages incorporating a SWM structure. Embodiments of multi-stack wafer/die level packages according toFIG.7Aare configured to incorporate a SWM structure216by mounting the SWM structure on a backside carrier202C. Embodiments of multi-stack wafer/die level packages according toFIG.7Aare configured to incorporate a SWM structure216by mounting the SWM structure on a backside carrier202C. Embodiments of multi-stack wafer/wafer level packages according toFIG.7Bare configured to incorporate a SWM structure216by mounting the SWM structure216on a backside surface of a first wafer218A. Embodiments of multi-stack wafer/wafer level packages according toFIG.7Care configured to incorporate a SWM structure216by mounting the SWM structure216on a backside surface of a first semiconductor device202A opposite an included carrier. Embodiments of multi-stack wafer/wafer level packages according toFIG.7Dare configured to incorporate a SWM structure216by mounting a first SWM structure216A on a backside surface of a first semiconductor device202A opposite an included carrier and a second SWM structure216B on a carrier202C.

FIGS.8A-Hare cross-sectional views of a multi-stack wafer/die level package during a manufacturing process that incorporates a SWM structure according to some embodiments.FIG.8Ais a cross-sectional view of a first semiconductor device202A after the addition of an interposer and formation of through silicon vias204(TSV).FIG.8Bis a cross-sectional view reflecting the results of a subsequent operation during which μ-bump structures, e.g., copper bumps206A have been formed on the frontside of the first semiconductor device202A.FIG.8Cis a cross-sectional view of an assembly including a second semiconductor device202B comprising one or more semiconductor die208and a corresponding plurality of copper bumps206B that has been inverted and mounted, frontside-to-frontside onto the first semiconductor device202A using, in some embodiments, frontside die-to-wafer (D2W) bonding processes. In some embodiments, an underfill material210is used for filing spaces between the components or elements including the semiconductor die208that are configured as the second semiconductor device202B as shown inFIG.8D.

In some embodiments, the assembly comprising the first semiconductor device202A and the second semiconductor device202B are inverted and a carrier202C is mounted on the backside of the second semiconductor device as shown inFIG.8E. As shown inFIG.8F, a portion of the backside of the first semiconductor device202A is removed to thin the assembly and expose a lower surface (relative to the first semiconductor device) of the TSVs. In some embodiments as shown inFIG.8Fa backside portion of the semiconductor dies208is removed and replaced with, e.g., a silicon oxide layer214A or a combination of silicon oxide and silicon nitride214B (not shown) that provides a local SWM structure. As shown inFIG.8G, in some embodiments a passivation layer215is added to the backside of the first semiconductor device202A and then patterned and etched so that contact bumps217can be formed on the TSVs214. As shown inFIG.8H, in some embodiments the carrier202C is removed and the composite package counted on a dicing frame222. a stress and warpage modulating (SWM) structure216is then mounted on the backside of the first semiconductor device202A for reducing the detrimental effects associated with stress, strain, and warpage on the performance and/or lifetime of the resulting multi-stack package.

FIG.9is a cross-sectional view of a multi-stack wafer/die system of integrated chips (SOIC) package during a manufacturing process that incorporates a SWM structure according to some embodiments. The composite multi-stack package ofFIG.9includes a first semiconductor device202A, a multilayer interconnection structure202M including a sequence of metal patterns separated by interlayer dielectric layers (not shown) and vias219added to the first semiconductor device during backend of line (BEOF) processing, a second semiconductor device202B, a carrier202C, and a SWM structure216mounted on a backside of the carrier that will reduce the mechanical and thermal stress experienced by the active components and improve the performance and/or lifetime of the multi-stack assembly. In some embodiments a via219extending through the carrier202C and the second semiconductor device202B provides an electrical connection between frontside and backside circuits.

FIG.10is a block diagram of an electronic process control (EPC) system1000, in accordance with some embodiments. Methods used for generating cell layout diagrams corresponding to some embodiments of the FET device structures detailed above, particularly with respect to the addition and placement of the electrical contacts, thermal contacts, active metal patterns, dummy metal patterns, and other heat dissipating structures may be implemented, for example, using EPC system1000, in accordance with some embodiments of such systems.

In some embodiments, EPC system1000is a general purpose computing device including a hardware processor1002and a non-transitory, computer-readable, storage medium1004. Computer-readable storage medium1004, amongst other things, is encoded with, i.e., stores, computer program code (or instructions)1006, i.e., a set of executable instructions. Execution of computer program code1006by hardware processor1002represents (at least in part) an EPC tool which implements a portion or all of, e.g., the methods described herein in accordance with one or more (hereinafter, the noted processes and/or methods).

Hardware processor1002is electrically coupled to computer-readable storage medium1004via a bus1018. Hardware processor1002is also electrically coupled to an I/O interface1012by bus1018. A network interface1014is also electrically connected to hardware processor1002via bus1018. Network interface1014is connected to a network1016, so that hardware processor1002and computer-readable storage medium1004are capable of connecting to external elements via network1016. Hardware processor1002is configured to execute computer program code1006encoded in computer-readable storage medium1004in order to cause the EPC system1000to be usable for performing a portion or all of the noted processes and/or methods. In one or more embodiments, hardware processor1002is a central processing unit (CPU), a multi-processor, a distributed processing system, an application specific integrated circuit (ASIC), and/or a suitable processing unit.

In one or more embodiments, computer-readable storage medium1004stores computer program code1006configured to cause the EPC system1000(where such execution represents (at least in part) the EPC tool) to be usable for performing a portion or all of the noted processes and/or methods. In one or more embodiments, computer-readable storage medium1004also stores information which facilitates performing a portion or all of the noted processes and/or methods. In one or more embodiments, computer-readable storage medium1004stores process control data1008including, in some embodiments, control algorithms, process variables and constants, target ranges, set points, programming control data, and code for enabling statistical process control (SPC) and/or model predictive control (MPC) based control of the various processes.

EPC system1000includes I/O interface1012. I/O interface1012is coupled to external circuitry. In one or more embodiments, I/O interface1012includes a keyboard, keypad, mouse, trackball, trackpad, touchscreen, and/or cursor direction keys for communicating information and commands to hardware processor1002.

EPC system1000also includes network interface1014coupled to hardware processor1002. Network interface1014allows EPC system1000to communicate with network1016, to which one or more other computer systems are connected. Network interface1014includes wireless network interfaces such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or wired network interfaces such as ETHERNET, USB, or IEEE-1364. In one or more embodiments, a portion or all of noted processes and/or methods, is implemented in two or more EPC systems1000.

EPC system1000is configured to send information to and receive information from fabrication tools1020that include one or more of ion implant tools, etching tools, deposition tools, coating tools, rinsing tools, cleaning tools, chemical-mechanical planarizing (CMP) tools, testing tools, inspection tools, transport system tools, and thermal processing tools that will perform a predetermined series of manufacturing operations to produce the desired integrated circuit devices. The information includes one or more of operational data, parametric data, test data, and functional data used for controlling, monitoring, and/or evaluating the execution, progress, and/or completion of the specific manufacturing process. The process tool information is stored in and/or retrieved from computer-readable storage medium1004.

EPC system1000is configured to receive information through I/O interface1012. The information received through I/O interface1012includes one or more of instructions, data, programming data, design rules that specify, e.g., layer thicknesses, spacing distances, structure and layer resistivity, and feature sizes, process performance histories, target ranges, set points, and/or other parameters for processing by hardware processor1002. The information is transferred to hardware processor1002via bus1018. EPC system1000is configured to receive information related to a user interface (UI) through I/O interface1012. The information is stored in computer-readable medium1004as user interface (UI)1010.

In some embodiments, a portion or all of the noted processes and/or methods is implemented as a standalone software application for execution by a processor. In some embodiments, a portion or all of the noted processes and/or methods is implemented as a software application that is a part of an additional software application. In some embodiments, a portion or all of the noted processes and/or methods is implemented as a plug-in to a software application. In some embodiments, at least one of the noted processes and/or methods is implemented as a software application that is a portion of an EPC tool. In some embodiments, a portion or all of the noted processes and/or methods is implemented as a software application that is used by EPC system1000.

InFIG.11, IC manufacturing system1100includes entities, such as a design house1120, a mask house1130, and an IC manufacturer/fabricator (“fab”)1150, that interact with one another in the design, development, and manufacturing cycles and/or services related to manufacturing an IC device1160. Once the manufacturing process has been completed to form a plurality of IC devices on a wafer, the wafer is optionally sent to backend or back end of line (BEOL)1180for, depending on the device, programming, electrical testing, and packaging in order to obtain the final IC device products. The entities in manufacturing system1100are connected by a communications network. In some embodiments, the communications network is a single network. In some embodiments, the communications network is a variety of different networks, such as an intranet and the Internet.

The communications network includes wired and/or wireless communication channels. Each entity interacts with one or more of the other entities and provides services to and/or receives services from one or more of the other entities. In some embodiments, two or more of design house1120, mask house1130, and IC Fab1150is owned by a single larger company. In some embodiments, two or more of design house1120, mask house1130, and IC Fab1150coexist in a common facility and use common resources.

Design house (or design team)1120generates an IC design layout diagram1122. IC design layout diagram1122includes various geometrical patterns designed for an IC device1160. The geometrical patterns correspond to patterns of metal, oxide, or semiconductor layers that make up the various components of IC device1160to be fabricated. The various layers combine to form various IC features.

For example, a portion of IC design layout diagram1122includes various IC features, such as an active region, gate electrode, source and drain, metal lines or vias of an intermetal interconnection, and openings for bonding pads, to be formed in a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate. Design house1120implements a proper design procedure to form IC design layout diagram1122. The design procedure includes one or more of logic design, physical design or place and route. IC design layout diagram1122is presented in one or more data files having information of the geometrical patterns. For example, IC design layout diagram1122, in some operations, will be expressed in a GDSII file format or DFII file format.

Whereas the pattern of a modified IC design layout diagram is adjusted by an appropriate method in order to, for example, reduce parasitic capacitance of the integrated circuit as compared to an unmodified IC design layout diagram, the modified IC design layout diagram reflects the results of changing positions of conductive line in the layout diagram, and, in some embodiments, inserting to the IC design layout diagram, features associated with capacitive isolation structures to further reduce parasitic capacitance, as compared to IC structures having the modified IC design layout diagram without features for forming capacitive isolation structures located therein.

Mask house1130includes mask data preparation1132and mask fabrication1144. Mask house1130uses IC design layout diagram1122to manufacture one or more masks1145to be used for fabricating the various layers of IC device1160according to IC design layout diagram1122. Mask house1130performs mask data preparation1132, where IC design layout diagram1122is translated into a representative data file (“RDF”). Mask data preparation1132provides the RDF to mask fabrication1144. Mask fabrication1144includes a mask writer. A mask writer converts the RDF to an image on a substrate, such as a mask (reticle)1145or a semiconductor wafer1153. The IC design layout diagram1122is manipulated by mask data preparation1132to comply with particular characteristics of the mask writer and/or requirements of IC Fab1150. InFIG.11, mask data preparation1132and mask fabrication1144are illustrated as separate elements. In some embodiments, mask data preparation1132and mask fabrication1144are collectively referred to as mask data preparation.

In some embodiments, mask data preparation1132includes a mask rule checker (MRC) that checks the IC design layout diagram1122that has undergone processes in OPC with a set of mask creation rules which contain certain geometric and/or connectivity restrictions to ensure sufficient margins, to account for variability in semiconductor manufacturing processes, and the like. In some embodiments, the MRC modifies the IC design layout diagram1122to compensate for limitations during mask fabrication1144, which may undo part of the modifications performed by OPC in order to meet mask creation rules.

It should be understood that the above description of mask data preparation1132has been simplified for the purposes of clarity. In some embodiments, mask data preparation1132includes additional features such as a logic operation (LOP) to modify the IC design layout diagram1122according to manufacturing rules. Additionally, the processes applied to IC design layout diagram1122during mask data preparation1132may be executed in a variety of different orders.

After mask data preparation1132and during mask fabrication1144, a mask1145or a group of masks1145are fabricated based on the modified IC design layout diagram1122. In some embodiments, mask fabrication1144includes performing one or more lithographic exposures based on IC design layout diagram1122. In some embodiments, an electron-beam (e-beam) or a mechanism of multiple e-beams is used to form a pattern on a mask (photomask or reticle)1145based on the modified IC design layout diagram1122. Mask1145will be formed using a process selected from various available technologies. In some embodiments, mask1145is formed using binary technology. In some embodiments, a mask pattern includes opaque regions and transparent regions. A radiation beam, such as an ultraviolet (UV) beam, used to expose the image sensitive material layer (e.g., photoresist) which has been coated on a wafer, is blocked by the opaque region and transmits through the transparent regions. In one example, a binary mask version of mask1145includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chromium) coated in the opaque regions of the binary mask.

In another example, mask1145is formed using a phase shift technology. In a phase shift mask (PSM) version of mask1145, various features in the pattern formed on the phase shift mask are configured to have proper phase difference to enhance the resolution and imaging quality. In various examples, the phase shift mask will be attenuated PSM or alternating PSM. The mask(s) generated by mask fabrication1144is used in a variety of processes. For example, such a mask(s) is/are used in an ion implantation process to form various doped regions in semiconductor wafer1153, in an etching process to form various etching regions in semiconductor wafer1153, and/or in other suitable processes.

Wafer fabrication1152includes forming a patterned layer of mask material formed on a semiconductor substrate is made of a mask material that includes one or more layers of photoresist, polyimide, silicon oxide, silicon nitride (e.g., Si3N4, SiON, SiC, SiOC), or combinations thereof. In some embodiments, masks1145include a single layer of mask material. In some embodiments, a mask1145includes multiple layers of mask materials.

In some embodiments IC Fab1155includes wafer fabrication1157. IC Fab1155is an IC fabrication business that includes one or more manufacturing facilities for the fabrication of a variety of different IC products. In some embodiments, IC Fab1155is a manufacturing facility provide the back end fabrication for the interconnection and packaging of the IC products (back-end-of-line (BEOL) fabrication) to add one or more metallization layers to wafer1159, and a third manufacturing facility (not shown) may provide other services for the foundry business such as packaging and labelling.

In some embodiments, the mask material is patterned by exposure to an illumination source. In some embodiments, the illumination source is an electron beam source. In some embodiments, the illumination source is a lamp that emits light. In some embodiments, the light is ultraviolet light. In some embodiments, the light is visible light. In some embodiments, the light is infrared light. In some embodiments, the illumination source emits a combination of different (UV, visible, and/or infrared) light.

In some embodiments, etching processes include presenting the exposed structures in the functional area(s) to an oxygen-containing atmosphere to oxidize an outer portion of the exposed structures, followed by a chemical trimming process such as plasma-etching or liquid chemical etching, as described above, to remove the oxidized material and leave behind a modified structure. In some embodiments, oxidation followed by chemical trimming is performed to provide greater dimensional selectivity to the exposed material and to reduce a likelihood of accidental material removal during a manufacturing process. In some embodiments, the exposed structures may include the fin structures of Fin Field Effect Transistors (FinFET) with the fins being embedded in a dielectric support medium covering the sides of the fins. In some embodiments, the exposed portions of the fins of the functional area are top surfaces and sides of the fins that are above a top surface of the dielectric support medium, where the top surface of the dielectric support medium has been recessed to a level below the top surface of the fins, but still covering a lower portion of the sides of the fins.

Subsequent to mask patterning operations, areas not covered by the mask are etched to modify a dimension of one or more structures within the exposed area(s). In some embodiments, the etching is performed using plasma etching, reactive ion etching (RIE), or a liquid chemical etch solution, according to some embodiments. The chemistry of the liquid chemical etch solution includes one or more of etchants such as citric acid (C6H8O7), hydrogen peroxide (H2O2), nitric acid (HNO3), sulfuric acid (H2SO4), hydrochloric acid (HCl), acetic acid (CH3CO2H), hydrofluoric acid (HF), buffered hydrofluoric acid (BHF), phosphoric acid (H3PO4), ammonium fluoride (NH4F) potassium hydroxide (KOH), ethylenediamine pyrocatechol (EDP), TMAH (tetramethylammonium hydroxide), or a combination thereof.

In some embodiments, the etching process is a dry-etch or plasma etch process. Plasma etching of a substrate material is performed using halogen-containing reactive gasses excited by an electromagnetic field to dissociate into ions. Reactive or etchant gases include, for example, CF4, SF6, NF3, Cl2, CCl2F2, SiCl4, BCl2, or a combination thereof, although other semiconductor-material etchant gases are also envisioned within the scope of the present disclosure. Ions are accelerated to strike exposed material by alternating electromagnetic fields or by fixed bias according to methods of plasma etching that are known in the art.

In some embodiments, molecular level processing technologies that share the self-limiting surface reaction characteristics utilized in ALD including, for example, Molecular Layer Deposition (MLD) and Self-Assembled Monolayers (SAM). MLD utilizes successive precursor-surface reactions in which a precursor is introduced into a reaction zone above the wafer surface. The precursor adsorbs to the wafer surface where it is confined by physisorption. The precursor then undergoes a quick chemisorption reaction with a number of active surface sites, leading to the self-limiting formation of molecular attachments in specific assemblies or regularly recurring structures. These MLD structures will be formed successfully using lower process temperatures than some traditional deposition techniques.

SAM is a deposition technique that involves the spontaneous adherence of organized organic structures on a wafer surface. This adherence involves adsorption of the organic structures from the vapor or liquid phase utilizing relatively weak interactions with the wafer surface. Initially, the structures are adsorbed on the surface by physisorption through, for instance, van der Waals forces or polar interactions. The self-assembled monolayers will then become confined to the surface by a chemisorption process. In some embodiments, the ability of SAM to grow layers as thin as a single molecule through chemisorption-driven interactions with the wafer surface(s) will be particularly useful in forming thin films including, for example, “near-zero-thickness” activation or barrier layers. SAM will also be particularly useful in area-selective deposition (ASD) (or area-specific deposition) using molecules that exhibit preferential reactions with specific segments of the underlying wafer surface in order to facilitate or obstruct subsequent material growth in the targeted areas. In some embodiments, SAM is used to form a foundation or blueprint region for subsequent area-selective ALD (AS-ALD) or area-selective CVD (AS-CVD).

The ALD, MLD, and SAM processes represent viable options for manufacturing thin layers (in some embodiments, the manufactured layers are only few atoms thick) that exhibit sufficient uniformity, conformality, and/or purity for the intended IC device application. By delivering the constituents of the material systems being manufactured both individually and sequentially into the processing environment, these processes and the precise control of the resulting surface chemical reactions allow for excellent control of processing parameters and the target composition and performance of the resulting film(s).

FIG.12is a schematic diagram of various processing departments defined within a Fab/Front End/Foundry for manufacturing IC devices according to some embodiments. The processing departments utilized in both front end of line (FEOL) and back end of line (BEOL) IC device manufacturing typically include a wafer transport operation1202for moving the wafers between the various processing departments. In some embodiments, the wafer transport operation will be integrated with an electronic process control (EPC) system according toFIG.5and utilized for providing process control operations, ensuring that the wafers being both processed in a timely manner and sequentially delivered to the appropriate processing departments as determined by the process flow. In some embodiments, the EPC system will also provide control and/or quality assurance and parametric data for the proper operation of the defined processing equipment. Interconnected by the wafer transport operation1202will be the various processing departments providing, for example, photolithographic operations1204, etch operations1206, ion implant operations1208, clean-up/strip operations1210, chemical mechanical polishing (CMP) operations1212, epitaxial growth operations1214, deposition operations1216, thermal treatments1218, and, in some embodiments, wafer assembly1220during which two or more substrates are joined to form a final device substrate structure.

In some embodiments a stress modulating device includes a semiconductor substrate, a first insulating layer formed over a first side of the semiconductor substrate, a second insulating layer formed over the first insulating layer, a third insulating layer formed over a second side of the semiconductor substrate, a fourth insulating layer formed over the third insulating layer, and a fifth insulating layer formed over the fourth insulating layer.

Some embodiments of stress modulating devices also include one or more additional elements selected from a group including a first insulating layer and a third insulating layer having a first composition with a second insulating layer and a fourth insulating layer having a second composition that is distinct from the first composition, a fifth insulating layer having the second composition; first and third insulating layers including silicon dioxide and second, fourth, and fifth insulating layers including silicon nitride; a fourth insulating layer formed from a composition corresponding to SixOyNzin which 1≤x≤3, 0<y≤2, and 0<z≤4, a series of N−1 alternating layers of the first and second compositions; and/or a series of N−1 alternating layers of silicon dioxide and silicon nitride formed over the fifth insulating layer.

In some embodiments of methods of manufacturing stress modulating devices includes preparing a semiconductor substrate, forming first and second insulating layers over a first side of the semiconductor substrate, forming a second insulating layer over the first insulating layer, forming a third, fourth, and fifth insulating layer over a second side of the semiconductor substrate.

Some embodiments of methods of manufacturing stress modulating devices also include one or more additional elements selected from a group including the operations of forming the first insulating layer by depositing a film including silicon dioxide, forming the second insulating layer by depositing a film including silicon nitride, forming the third insulating layer by depositing a film including silicon dioxide, forming the fourth insulating layer by depositing a film including silicon nitride, and forming the fifth insulating layer by depositing a film including silicon nitride; depositing a silicon dioxide film between the fourth insulating layer and the fifth insulating layer; modifying the fourth insulating layer with oxygen to form a SiON composition before forming the fifth insulating layer; rotating the semiconductor substrate by Θ° after forming the third insulating layer and before forming the fourth insulating layer; rotating the semiconductor substrate by Θ° comprises rotating the semiconductor substrate by 45°; and/or depositing a series of N−1 alternating layers of a first layer comprising silicon dioxide and a second layer comprising silicon nitride over the fifth insulating layer; forming a series of N−1 alternating layers of silicon dioxide and silicon nitride formed over the first side of the semiconductor substrate, forming a series of N−1 alternating layers of silicon dioxide and silicon nitride formed over the second side of the semiconductor substrate, and removing each of the series of N−1 alternating layers of silicon dioxide and silicon nitride formed over the first side of the semiconductor substrate before depositing an addition one of the series of N−1 alternating layers of silicon dioxide and silicon nitride.

Some embodiments of multi-layer semiconductor package assemblies include a first semiconductor device, a second semiconductor device mounted on the first semiconductor device for establishing electrical connections between the first and second semiconductor devices with the first semiconductor device and the second semiconductor device having an initial stress load, and a first stress modulating device that reduces the initial stress load with the first stress modulating device including a semiconductor substrate, a first insulating layer on a first side of the semiconductor substrate, a second insulating layer on the first insulating layer, a third insulating layer on a second side of the semiconductor substrate, a fourth insulating layer on the third insulating layer, and a fifth insulating layer on the fourth insulating layer.

Some embodiments of multi-layer semiconductor package assemblies also include one or more additional elements or configurations selected from a group including a carrier mounted on the second semiconductor device, wherein the first stress modulating device is mounted on the carrier and reduces the initial stress load; the first stress modulating device is mounted on the first semiconductor device; a second stress modulating device mounted on the first semiconductor device, wherein the combination of the first stress modulating device and the second stress modulating device further reduces the initial stress load; and/or the first and second semiconductor devices are independently selected from semiconductor wafers and semiconductor dies.