Thin film transistor structure, array substrate and method for manufacturing a thin film transistor structure

The disclosure relates to a thin film transistor structure, an array substrate, and a method for manufacturing a thin film transistor structure. The thin-film transistor structure includes a base substrate, a thin film transistor on the base substrate. Wherein the thin film transistor includes an active layer and a source/drain electrode on a side, facing towards the base substrate, of the active layer. Wherein the source/drain electrode has a protrusion protruding from an edge portion of the active layer in a direction parallel to a surface of the base substrate.

CROSS REFERENCE TO RELATED APPLICATIONS

This patent application claims the benefit and priority of Chinese Patent Application No. 201810959883.7 filed on Aug. 22, 2018, the disclosure of which is incorporated by reference herein in its entirety as part of the present application.

BACKGROUND

The disclosure relates to a technical field of display. More specifically, the disclosure relates to a method for manufacturing a thin film transistor structure, an array substrate, and a method for manufacturing a thin film transistor structure.

Thin film transistors may include gate electrode, source/drain electrode, active layer, gate insulation layer, and so on. Thin film transistors are widely used in various display devices, such as liquid crystal displays, organic light-emitting diode displays, and so on.

BRIEF DESCRIPTION

Embodiments of the present disclosure provide a thin film transistor structure, an array substrate, and a method of manufacturing a thin film transistor structure.

An object of an embodiment of the disclosure is to provide a thin film transistor structure. The thin film transistor structure includes a base substrate, a thin film transistor on the base substrate, wherein the thin film transistor includes an active layer and a source/drain electrode on a side, facing towards the base substrate, of the active layer, and wherein the source/drain electrode has a protrusion protruding from an edge portion of the active layer in a direction parallel to a surface of the base substrate.

In an embodiment, the thin film transistor structure further includes an intermediate layer between the active layer and the base substrate. The intermediate layer has a groove on a side, facing towards the active layer, of the intermediate layer. Wherein the source/drain electrode is located in the groove. Wherein the top surface of the source/drain electrode is flush with a top surface of the active layer contacting the intermediate layer.

In an embodiment, a depth of the groove is in a range from 4000 angstroms to 6000 angstroms.

In an embodiment, the thin film transistor structure further includes an insulating layer on the thin-film transistor including an opening that exposes the protrusion and the edge portion.

In an embodiment, the thin film transistor structure further includes a conductive portion in the opening, wherein the conductive portion is in contact with the protrusion and the edge portion.

In an embodiment, the thin film transistor further includes a gate electrode on a side, away from the base substrate, of the active layer and a gate insulating layer between the gate electrode and the active layer.

In an embodiment, the intermediate layer includes a buffer layer.

In an embodiment, the intermediate layer includes an insulating layer, and the thin film transistor further includes a gate electrode located on a side, facing towards the base substrate, of the intermediate layer.

In an embodiment, the source/drain electrode includes a first source/drain electrode and a second source/drain electrode, wherein the conductive portion includes a first conductive portion connected to the first source/drain electrode and a second conductive portion connected to the second source/drain electrode, and wherein the first conductive portion functions as an anode of an OLED light-emitting device.

Another purpose of some embodiments of the disclosure is to provide an array substrate. The array substrate includes a thin film transistor structure as described above.

Another purpose of some embodiments of the disclosure is to provide a method for manufacturing a thin film transistor structure. The method for manufacturing a thin film transistor structure includes forming an intermediate layer on a base substrate, forming a groove on a side, away from the base substrate, of the intermediate layer, forming a source/drain electrode of the thin film transistor in the groove, and forming an active layer of the thin film transistor on the intermediate layer. Wherein the source/drain electrode has a protrusion protruding from an edge portion of the active layer in a direction parallel to a surface of the base substrate.

In an embodiment, a top surface of the source/drain electrode is formed to be flush with a top surface of the intermediate layer contacting the active layer.

In an embodiment, the method further includes forming an insulating layer on the active layer and the intermediate layer, forming an opening in the insulation layer to expose the edge portion of the active layer and the protrusion of the source/drain electrode, and forming a conductive portion, covering the edge portion of the active layer and the protrusion, in the opening.

In an embodiment, the method further includes, after forming the active layer and prior to forming the insulating layer, forming a gate insulation layer on the active layer, and forming a gate electrode on the gate insulation layer.

In an embodiment, the method further includes, prior to forming the intermediate layer, forming a gate electrode on the base substrate, and wherein the intermediate layer comprises an insulating layer.

DETAILED DESCRIPTION

In order to make the technical solutions and advantages of the embodiments of the present disclosure more comprehensible, the technical solutions of the embodiments of the present disclosure are clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part but not all of the embodiments of the present disclosure. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative efforts shall further fall within the protection scope of the present disclosure.

As used herein and in the appended claims, the singular form of a word includes the plural, and vice versa, unless the context clearly dictates otherwise. Thus, the references “a”, “an”, and “the” are generally inclusive of the plurals of the respective terms. Similarly, the words “comprise”, “comprises”, and “comprising” are to be interpreted inclusively rather than exclusively. For purposes of the description, hereinafter, the terms “upper”, “lower”, “right”, “left”, “vertical”, “horizontal”, “top”, “bottom”, and derivatives thereof shall relate to the disclosure, as it is oriented in the drawing figures. The terms “overlying”, “atop”, “positioned on” or “positioned atop” means that a first element, such as a first structure, is present on a second element, such as a second structure, wherein intervening elements, such as an interface structure, e.g. interface layer, may be present between the first element and the second element. The term “contact” means that a first element, such as a first structure, and a second element, such as a second structure, are connected with or without any intermediary elements at the interface of the two elements.

FIG. 1is a schematic view of a thin film transistor structure according to some embodiments of the present disclosure. As shown inFIG. 1, the thin film transistor structure according to embodiments of the present disclosure includes a base substrate1, a thin film transistor located on the base substrate1. The thin film transistor2includes an active layer3and a source/drain electrode4located on a side of the active layer3facing the base substrate1. By such a source/drain electrode4below the active layer3, the source/drain contact resistance can be reduced by potentially increasing the contact area between other conductive structures and the source/drain region. There also is a possibility of eliminating the segment difference (that is, the height difference) of the subsequent layer caused by the relative thicker source/drain electrode.

As shown inFIG. 1, the source/drain electrode4may further have a protrusion41protruding from an edge portion E of the active layer3in a direction parallel to a surface of the base substrate1. With such a setting, when a hole for a conductive structure connected to the source/drain region is subsequently formed, the hole can be aligned not only with the source and drain region of the active layer, but further with the protrusion. Thus, the alignment difficulty between the hole and the source/drain region can be reduced. In addition, the conductive structure (for example, the conductive portion7inFIG. 4) and the source/drain electrode cover the active layer from both sides of the active layer, thus increasing the contact area with the source/drain region of the active layer and reducing the contact resistance of the source/drain contact.

FIG. 2is a schematic view of a thin film transistor structure according to some embodiments of the present disclosure. As shown inFIG. 2, the thin film transistor structure according to embodiments of the present disclosure may further include an intermediate layer5between the active layer3and the base substrate1. The intermediate layer5has a groove51on a side thereof facing the active layer3. The source/drain electrode4is located in the groove51. A top surface S41of the source/drain electrode4is flush with a top surface S51of the intermediate layer5contacting the active layer3. The “top surface” here refers to a surface away from the base substrate1, and “flush with” refers to the surfaces are on the same plane. Due to that the top surface S41of the source/drain electrode4is flush with the top surface S51of the intermediate layer5contacting the active layer3, the segment difference of the layer formed on the source/drain electrode4can be eliminated.

In an embodiment, the depth of the groove51may be about 4000-6000 angstroms. The source/drain electrode4may include a metal, for example, copper or aluminum. The active layer3may include an oxide semiconductor.

FIG. 3is a schematic view of a thin film transistor structure according to some embodiments of the present disclosure. As shown inFIG. 3, the thin film transistor structure according to some embodiments of the present disclosure may further include an insulating layer6located on the thin film transistor. The insulation layer has an opening61. The opening61exposes the protrusion41of the source/drain electrode4and the edge portion E of the active layer3.

FIG. 4is a schematic view of a thin film transistor structure according to some embodiments of the present disclosure. As shown inFIG. 4, the thin film transistor structure according to some embodiments of the present disclosure may further include a conductive portion7located in the opening61. The conductive portion7is in contact with the protrusion41of the source/drain electrode4and the edge portion E of the active layer3.

The source/drain electrode4may include a first source/drain electrode41and a second source/drain electrode42. The conductive portion may include a first conductive portion71connected to the first source/drain electrode41and a second conductive portion72connected to the second source/drain electrode42. The first conductive portion71may be used as an electrode (for example, an anode) of the luminous structure10(e.g., OLED light-emitting device) thereon.

FIG. 5is a schematic view of a thin film transistor structure according to some embodiments of the present disclosure. As shown inFIG. 5, the thin film transistor structure according to some embodiments of the disclosure may further include a gate electrode8located on a side of the active layer3away from the base substrate1and a gate insulation layer9located between the gate electrode8and the active layer3. It is understandable that in this case, the thin film transistor is a top gate structure. The intermediate layer5may include a buffer layer. The material of the buffer layer may include at least one of the following: silica, organosilicon, and materials that can be used as black matrix.

FIG. 6is a schematic view of a thin film transistor structure according to some embodiments of the present disclosure. As shown inFIG. 6, the thin film transistor structure according to some embodiments of the present disclosure further includes a gate electrode8located on a side of the intermediate layer5facing the base substrate1. In this case, the intermediate layer5includes an insulating layer.

The embodiments of the disclosure further provide an array substrate.

FIG. 7is a schematic view of an array substrate according to some embodiments of the present disclosure. As shown inFIG. 7the array substrate2000according to some embodiments of the present disclosure may include a thin film transistor structure1000as described above. The thin film transistor structure1000may include an array substrate as shown inFIG. 1-FIG. 6.

The embodiments of the disclosure further provide a method for manufacturing of a thin film transistor structure.

FIG. 8is a schematic view of a method for manufacturing of a thin film transistor structure according to some embodiments of the present disclosure. As shown inFIG. 8, the method for manufacturing of a thin film transistor structure according to some embodiments of the present disclosure includes:

S1, forming an intermediate layer5on a base substrate1;

S3, forming a groove51on a side, away from the base substrate1, of the intermediate layer5;

S5, forming a source/drain electrode4of the thin film transistor in the groove51; and

S7, forming an active layer3of the thin film transistor on the intermediate layer5, wherein the source/drain electrode4has a protrusion41protruding from an edge portion E of the active layer3in a direction parallel to a surface of the base substrate1.

The method for manufacturing a thin film transistor structure according to embodiments of the disclosure can facilitate the conductive connection to the source/drain electrode and reduce the source/drain contact resistance, as well as reduce the alignment difficulty between the subsequently formed hole and the source/drain region.

The top surface of the source/drain electrode4can be formed as flush with the top surface of the intermediate layer5contacting the active layer3. Because the top surface S41of the source/drain electrode4is flush with the top surface S51of the intermediate layer5contacting the active layer3, the segment difference of the layers formed on the source/drain electrode4can be eliminated.

FIG. 9is a schematic view of a method for manufacturing of a thin film transistor structure according to some embodiments of the present disclosure. As shown inFIG. 9, the method can further include:

S9, forming an insulating layer6on the active layer3and the intermediate layer5;

S11, forming an opening61in the insulation layer6to expose the edge portion E of the active layer3and the protrusion41of the source/drain electrode4; and

S13, forming a conductive portion7, covering the edge portion E of the active layer3and the protrusion41, in the opening61.

FIG. 10Ais a schematic view of a method for manufacturing a thin film transistor structure according to some embodiments of the present disclosure. As shown inFIG. 10A, the method further includes after forming the active layer3and prior to forming the insulating layer6:

S15, forming a gate insulation layer9on the active layer3; and

S17, forming a gate electrode8on the gate insulation layer9.

In particular, the insulating layer may be deposited on the active layer3(for example, an oxide semiconductor layer), and then the gate electrode layer (for example, a metal layer) may be deposited on the insulating layer. The gate electrode layer is etched by mask (for example, wet method) to form the gate electrode. The mask can continue to be used to etch the insulation layer (for example, dry method) to form the gate insulation layer. Wet etch has side etch while dry etch does not. Therefore, although being etched using the same mask, the width of the formed gate electrode8is different from that of the gate insulation layer9. Thus, the gate insulation layer9has a protrusion part91protruding from an edge part E′ of the gate electrode8in a direction parallel to a surface of the base substrate1. After dry etch, conductive treatment (for example, plasma treatment) may be performed on the active layer to conduct the region of the non-channel region of the active layer. It should be understood that, depending on the specific process adopted, the gate insulation layer may not have the protrusion part91.

FIG. 10Bis a schematic view of a method for manufacturing a thin film transistor structure according to some embodiments of the present disclosure. As shown inFIG. 10B, the method further includes, prior to forming the intermediate layer5:

S19, forming a gate electrode8on the base substrate1, and wherein the intermediate layer comprises an insulating layer.