Polysilicon thin film transistor with a self-aligned LDD structure

A polysilicon thin film transistor (poly-Si TFT) with a self-aligned lightly doped drain (LDD) structure has a transparent insulating substrate; a buffering layer formed on the transparent insulating substrate; a polysilicon layer formed on the buffering layer and having a channel region, an LDD structure surrounding the channel region, and a source/drain region surrounding the LDD structure; a gate insulating layer formed on the polysilicon layer; a gate layer formed on the gate insulating layer and positioned over the channel region; an insulating spacer formed on the sidewall of the gate layer and positioned over the LDD structure; and a sub-gate layer formed on the insulating spacer.

Similar reference characters denote corresponding features consistently throughout the attached drawings. 
 DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIGS. 2A to 2 G are cross-sectional diagrams showing a method of forming an LDD structure on a poly-Si TFT according to the present invention. As shown in FIG. 2A, a transparent insulating substrate 30 comprises a buffering layer 31 of silicon oxide, a polysilicon layer 32 formed on the buffering layer 31 , a gate insulating layer 34 formed on the polysilicon layer 32 , and a gate layer 36 patterned on the gate insulating layer 34 . It is noted that the gate layer 36 may be formed to have a trapezoid profile or a rectangular profile. Hereinafter, the method of forming the LDD structure is used in P-MOS poly-Si TFTs applications. As shown in FIG. 2 B, using the gate layer 36 as a mask, a light ion implantation process, employing P ions or As ions with a concentration of 1×10 13 ˜1×10 14 cm −2 , is performed to form a N − doped region 38 on the exposed polysilicon layer 32 . Then, as shown in FIG. 2 C, an insulating layer 40 and a barrier layer 42 are sequentially deposited on the exposed surface of the substrate 10 . The insulating layer 40 may be silicon oxide or silicon nitride, and the barrier layer 42 may be silicon nitride, amorphous silicon or metallic materials. Next, as shown in FIG. 2 D, using dry etching to remove part of the barrier layer 42 , the barrier layer 42 remains over part of the insulating layer 40 that surrounds the gate layer 36 . Next, s shown in FIG. 2 E, using wet etching with the barrier layer 42 as a mask, the insulating layer 40 on the gate insulating layer 34 and the top of the gate layer 36 is removed. Thus, the insulating layer 40 remaining on the sidewall of the gate layer 36 serves as a insulating spacer 46 , and the barrier layer 42 remaining over the insulating spacer 46 serves as a bump 44 . Then, as shown in FIG. 2 F, using the gate layer 36 , the insulating spacer 46 and the bump 44 as a mask, a heavy ion implantation process, employing P ions or As ions with a concentration of 1×10 15 ˜1×10 16 cm −2 , is performed to form a N &plus; doped region 48 on the exposed area of the N − doped region 38 . The remaining part of the N − doped region 38 serves as a self-aligned LDD structure, the N &plus; doped region 48 serves as a source/drain region, and the undoped region of the polysilicon layer 32 serves as a channel. Besides, if the barrier layer 42 is of amorphous silicon or polysilicon, the heavy ion implantation process can form the bump 44 into a semiconductor gate layer. Finally, depending on the requirements of process control and product performance, the bump 44 can be removed or left. When the bump 44 is removed, a poly-Si TFT with the LDD structure is completed as shown in FIG. 2G . When the bump 44 is of conductive materials, such as metallic materials or doped polysilicon, the bump 44 can be left over the insulating spacer 46 (shown in FIG. 2F ) to serve as a sub-gate layer. The sub-gate layer covers the self-aligned LDD structure to provide a metal shielding effect, thus the vertical electric field between the gate layer 36 and drain in decreased. This can be used in a high frequency operating circuit application. Compared with the method of forming an LDD structure in the prior art, the present invention employs the barrier layer 42 to pattern the self-aligned LDD structure without an extra photo mask, thus an error of alignment caused by the limitation of the exposure technique is avoided. In addition, irrespective of whether the gate layer 36 is formed to be rectangular or trapezoidal, the problems caused by formation of the trapezoidal profile are solved. Furthermore, the bump 44 provides a metal shielding effect, thereby the poly-Si TFT with the aligned LDD structure can be used in a high frequency operating circuit application. It is to be understood that the present invention is not limited to the embodiments described above, but encompasses any and all embodiments within the scope of the following claims.