Semiconductor die with heat and electrical pipes

Thermal hot spots in the substrate of a semiconductor die, and the required surface area of the semiconductor die, are substantially reduced by forming thermal or thermal and electrical pipes in the substrate that extend from a bottom surface of the substrate to a point near the top surface of the substrate.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to semiconductor dice and, more particularly, to a semiconductor die with heat and electrical pipes.

2. Description of the Related Art

Conventional semiconductor die have many advantages, but also suffer from a number of problem areas. One problem area is the removal of heat from the substrate of the die. The high current circuits of current-generation integrated circuits can generate significant amounts of heat in the substrate which, if not removed, can damage or erroneously bias adjacent circuits.

Another problem area is the surface area penalty that is paid to provide electrical contacts to the different regions of the substrate. For example, current-generation semiconductor die commonly have a large number of wells to support a large number of electrically-isolated CMOS circuits.

To place voltages on the wells, each well must be electrically contacted, and can be electrically contacted multiple times. Each electrical contact, in turn, consumes a region on the surface of the substrate (where the minimum size of the region is defined by the design rules of the fabrication process). Thus, a large number of well contacts consume a large amount of the surface area of the die.

FIG. 1shows a cross-sectional diagram that illustrates a prior-art semiconductor die100. As shown inFIG. 1, semiconductor die100includes a conventional semiconductor substrate110that has a top surface110A, a bottom surface110B, and a thickness T1of approximately 500–750×10−6m (500–750 microns or approximately 20–30 mils).

Further, die100includes a p− region112and a number of shallow trench isolation (STI) regions that are located in substrate110. In addition, die100includes a p− well114and an n− well116that are located in substrate110to contact p− region112. P− well114has a heavier dopant concentration than p− region112of substrate110.

As further shown inFIG. 1, semiconductor die100includes a p+ substrate contact region120that is located in substrate110to contact p− region112, a p+ well contact122that is located in substrate110to contact p− well114, and an n+ well contact124that is located in substrate110to contact n− well116.

Semiconductor die100additionally includes an NMOS transistor126and a PMOS transistor128. NMOS transistor126has spaced-apart n+ source and drain regions130and132that are located in p− well114, and a channel region134of p− well114that is located between source and drain regions130and132. NMOS transistor126also has a gate oxide layer136that is formed on p− well114over channel region134, and a gate138that is formed on gate oxide layer136over channel region134.

PMOS transistor128has spaced-apart p+ source and drain regions140and142that are located in n− well116, and a channel region144of n− well116that is located between source and drain regions140and142. PMOS transistor128also has a gate oxide layer146that is formed on n− well116over channel region144, and a gate148that is formed on gate oxide layer146over channel region144.

As additionally shown inFIG. 1, die100includes a first dielectric layer150that is formed on top surface110A of substrate110over p+regions120,122,140, and142, n+ regions124,130, and132, and gates138and148. Die100further includes a large number of contacts152that are formed through first dielectric layer150to make electrical connections with p+ regions120,122,140, and142, n+ regions124,130, and132, and gates138and148.

Semiconductor die100also includes a large number of metal-1 regions156, such as traces and lines, that are formed on first dielectric layer150to make electrical connections with the contacts152, and a second dielectric layer160that is formed on first dielectric layer150and the metal-1 regions156.

Die100further includes a large number of vias162that are formed through second dielectric layer160to make electrical connections with the metal-1 regions156, a large number of metal-2 regions164, such as traces and lines, that are formed on second dielectric layer160to make electrical connections with the vias162, and a top dielectric layer170that is formed on second dielectric layer160and the metal-2 regions164.

In operation, significant amounts of heat can be generated in the channel regions134and144when transistors126and128are high current transistors, such as driver transistors. Further, as shown inFIG. 1, p+ regions120and122and n+region124, along with the adjacent STI regions, consume a significant amount of the area of top surface110A providing electrical connections to p− region112of substrate110, p− well114, and n− well116, respectively.

As a result, there is a need for a semiconductor die that reduces the build up of heat in the high-current regions of the die. In addition, there is a need for a semiconductor die that reduces the amount of surface area that is consumed by the substrate and well contacts.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 2shows a cross-sectional view that illustrates a semiconductor die200in accordance with the present invention. Semiconductor die200is similar to semiconductor die100and, as a result, utilizes the same reference numerals to designate the structures which are common to both die.

As shown inFIG. 2, semiconductor die200differs from semiconductor die100in that semiconductor die200includes a number of thermally-conductive heat pipes210that are located in substrate110to extend from bottom surface110B of substrate110up to near top surface110A of substrate110, where near is defined to be within 5×10−6m (five microns) of top surface110A of substrate110, without touching top surface110A of substrate110.

Heat pipes210can include a metal region212, such as metal silicide or other metallic materials and combinations, and an electrically isolating material214, such as oxide, that completely surrounds metal region212in substrate110. As a result, heat pipes210can thermally transfer heat faster than substrate110transfers heat.

In addition, as further shown inFIG. 2, semiconductor die200can also include a thermally-conductive interconnect216, such as a solder ball, that allows a thermally-conductive path to be formed between die200and a carrier substrate or a printed circuit board when the bottom surface of die200is electrically connected to the carrier substrate or printed circuit board using through-the-wafer metal plugs. Further, die200is significantly thinner than die100, having an etchable thickness T2, which is defined to be approximately 12–100×10−6m (12–100 microns or approximately 0.5–4 mils).

One of the advantages of the present invention is that the thermal hot spots in substrate110can be easily accessed from the backside of die200. Unlike top surface110A of substrate110, which is dotted with p+ and n+ active regions and gate structures that significantly limit access to the thermal hot spots in substrate110, the bottom surface of substrate110is free from any region or structure which would impede access to a hot spot.

As a result, heat pipes can be easily added to any substrate region which is excessively hot. Further, multiple heat pipes can be clustered together to increase the heat flow from the area. For example, three heat pipes210could be formed near channel region134, while only one heat pipe210is formed near channel region144when channel region134is substantially hotter than channel region144.

FIG. 3shows a cross-sectional view that illustrates a semiconductor die300in accordance with the present invention. Semiconductor die300is similar to semiconductor die200and, as a result, utilizes the same reference numerals to designate the structures which are common to both die.

As shown inFIG. 3, semiconductor die300differs from semiconductor die200in that semiconductor die300includes heat/electrical pipes310in lieu of heat pipes210. As further shown in FIG.3, each heat/electrical pipe310can include a metal region312, such as metal silicide or other metallic materials and combinations, and an electrically isolating material314, such as oxide, that only partially surrounds metal region312.

Metal region312, which can have a pillar shape, has a side wall312A and an end or top wall312B. Isolating material314, in turn, contacts side wall312A, isolating side wall312A from substrate110. Isolating material314, however, does not contact top wall312B. As a result, top wall312B contacts substrate110.

In addition, semiconductor die300can include a number of contact regions320that corresponds with the heat/electrical pipes310. Each contact region320lies between and contacts the top wall312B and substrate110of a heat/electrical pipe310. Each contact region320has the same conductivity type, but a greater dopant concentration, than the adjoining region of substrate110.

In operation, since the top walls312B of the heat/electrical pipes310contact substrate110either directly or via contact regions320, the heat/electrical pipes310can be used to both set the voltages on the wells and provide a thermally conductive path. As shown inFIG. 3, heat/electrical pipe310A can be used to both set the voltage on p− well114and provide a thermally conductive path, while heat/electrical pipe310B can be used to both set the voltage on n− well116and provide a thermally conductive path.

As a result, one of the advantages of the present invention is that, in addition to providing a thermal path to substantially reduce thermal hot spots in substrate110, the present invention also eliminates the need for p+ well contact122, n+ well contact124, and the adjoining STI regions required by semiconductor die100.

Heat/electrical pipes330are identical to heat/electrical pipes310except that heat/electrical pipes330are shorter to set the voltage on p− region112of substrate110.

Thus as above, each heat/electrical-pipe330can include a metal region332, such as metal silicide or other metallic materials and combinations, and an electrically isolating material334, such as oxide, that only partially surrounds metal region332. Metal region332, which can have a pillar shape, has a side wall332A and an end or top wall332B. Isolating material334, in turn, contacts side wall332A, isolating side wall332A from substrate110. Isolating material334, however, does not contact top wall332B. As a result, top wall332B contacts p− region112of substrate110.

In addition, semiconductor die300can include a number of contact regions340that corresponds with the heat/electrical pipes330. Each contact region340lies between and contacts the top wall332B and substrate110of a heat/electrical pipe330. Each contact region340has the same conductivity type, but a greater dopant concentration than, the adjoining region of substrate110.

As a result, one of the advantages of the present invention is that, in addition to providing a thermal path to substantially reduce thermal hot spots in substrate110, the present invention also eliminates the need for p+ substrate contact120and the adjoining STI region required by semiconductor die100. Thus, since the present invention eliminates the need for p+ substrate contact120, p+ well contact122, n+ well contact124, and the adjoining STI regions, the present invention reduces the amount of area of top surface110A that is consumed by the substrate and well contacts.

FIGS. 4A–4Fshow a series of cross-sectional views that illustrate a method of forming a die in accordance with the present invention. As shown inFIG. 4A, the method begins with a semiconductor die400that has been conventionally formed, except that the substrate and well contacts have been eliminated.

Semiconductor die400includes a semiconductor substrate410that has a top surface410A, a bottom surface410B, and a thickness T3of approximately 500–750×10−6m (500–750 microns or approximately 20–30 mils). Further, die400includes a p− region412and a number of shallow trench isolation (STI) regions that are located in substrate410. In addition, die400includes a p− well414and an n− well416that are located in substrate410to contact p− region412. P−well414has a heavier dopant concentration than p− region412of substrate410.

As further shown inFIG. 4A, semiconductor die400includes an NMOS transistor420and a PMOS transistor422. NMOS transistor420has spaced-apart n+ source and drain regions430and432that are formed in p− well414, and a channel region434of p− well414that is located between source and drain regions430and432. NMOS transistor420also has a gate oxide layer436that is formed on p− well414over channel region434, and a gate438that is formed on gate oxide layer436over channel region434.

PMOS transistor422has spaced-apart p+ source and drain regions440and442that are formed in n− well416, and a channel region444of n− well416that is located between source and drain regions440and442. PMOS transistor422also has a gate oxide layer446that is formed on n− well414over channel region444, and a gate448that is formed on gate oxide layer446over channel region444.

As additionally shown inFIG. 4A, die400includes a first dielectric layer450that is formed on top surface410A of substrate410over n+ regions430and432, p+ regions440and442, and gates438and448. Die400further includes a large number of contacts452that are formed through first dielectric layer450to make electrical connections with n+ regions430and432, p+ regions440and442, and gates438and448.

Semiconductor die400also includes a large number of metal-1 regions456, such as traces and lines, that are formed on first dielectric layer450to make electrical connections with the contacts452, and a second dielectric layer460that is formed on first dielectric layer450and the metal-1 regions456.

Die400further includes a large number of vias462that are formed through second dielectric layer460to make electrical connections with the metal-1 regions456, a large number of metal-2 regions464, such as traces and lines, that are formed on second dielectric layer460to make electrical connections with the vias462, and a top dielectric layer470that is formed on second dielectric layer460and the metal-2 regions464.

As shown inFIG. 4B, the method begins by back grinding bottom surface410B of semiconductor die400until substrate410has an etchable thickness T4that lies in the range of approximately 12–100×10−6m (12–100 microns or approximately 0.5–4 mils). An etchable thickness of silicon is a thickness that can be anisotropically etched through in a relatively short period of time.

For example, an etchable thickness of silicon of 25×10−6m (25 microns or 1 mil) can be anisotropically etched through in a reactive ion etcher in a relatively short period of time, e.g., 30 minutes. By contrast, approximately eight hours are required to etch through silicon that is 500×10−6m (500 microns or 20 mils) thick.

Following this, a mask480, such as a hard mask, is formed and patterned on bottom surface410A of substrate410. Once mask480has been formed and patterned, the exposed regions of substrate410are etched until a number of openings482are formed in substrate410. After the openings482have been formed, the exposed regions of substrate410are oxidized to form insulation layers484that line the openings482.

Following this, a metallic material486is deposited on mask480and in openings482to fill up openings482. As shown inFIG. 4C, once openings482have been filled, the overlying regions of metallic material486and mask480are removed, such as by back grinding, to form a die488that has a number of metal regions490that are isolated from substrate410by the insulation layers484. Die488, in turn, is similar to die200.

Optionally, as shown inFIG. 4D, after insulation layer484has been formed, a mask500is formed and patterned on mask480to expose the openings482that are formed over the n− wells416. Following this, the exposed regions of substrate410at the bottom of openings482are implanted with an n− type dopant, and activated with a low temperature drive in, to form n+ contact regions502at the ends of the openings482. Next, the openings482are anisotropically etched with, for example, a reactive ion etcher to remove the portion of insulation layer484that contacts the n+ contact regions502.

With reference toFIG. 4E, mask500is then removed, and the process is repeated to form p+ contact regions504the ends of the openings482that are formed over p− well414. After this, a metallic material506is deposited on mask480and in openings482to fill up openings482.

As shown inFIG. 4F, once openings482have been filled, the overlying regions of metallic material506and mask480are removed, such as by back grinding, to form a die508that has a number of metal regions510that are isolated from substrate410by the insulation layers484. Die508, in turn, is similar to die300.

It should be understood that the above descriptions are examples of the present invention, and that various alternatives of the invention described herein may be employed in practicing the invention. Thus, it is intended that the following claims define the scope of the invention and that structures and methods within the scope of these claims and their equivalents be covered thereby.