Bistable resistance value acquisition device, manufacturing method thereof, metal oxide thin film, and manufacturing method thereof

A ferroelectric layer (104) is sandwiched between a lower electrode layer (103) and an upper electrode (105). When a predetermined voltage (DC or pulse) is applied between the lower electrode layer (103) and the upper electrode (105) to change the resistance value of the ferroelectric layer (104) to switch a stable high resistance mode and low resistance mode, a memory operation is obtained. A read can easily be done by reading a current value when a predetermined voltage is applied to the upper electrode (105).

TECHNICAL FIELD

The present invention relates to a bistable resistance value acquisition device and manufacturing method thereof and a metal oxide thin film and manufacturing method thereof.

BACKGROUND ART

Research and development aimed at a wider multimedia information society, and more particularly, realization of a ubiquitous service are flourishing. Especially, a device (to be referred to as a memory hereinafter) which is mounted in a network equipment or information terminal to record information is an important key device. The memory mounted in a ubiquitous terminal is required to implement a high-speed operation, long-term holding, environmental resistance, and low power consumption. In addition, a function of inhibiting any erase of stored information even in a power-off state, i.e., nonvolatility is indispensable.

Conventionally, semiconductor devices are widely used as memories. One of the widely used memories is a DRAM (Dynamic Random Access Memory). The unit storage element (to be referred to as a memory cell hereinafter) of a DRAM includes one storage capacitor and one MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor). A voltage corresponding to the state of charges stored in the storage capacity of a selected memory cell is extracted from a bit line as “on” or “off” of an electrical digital signal, thereby reading out stored data (S. M. Sze, “Physics of Semiconductor Devices”, John Wiley and Sons, Inc., 1981, and Fujio Masuoka, “Applied Physics”, Vol. 73, No. 9, p. 1166, 2004).

In the power-off state, however, the DRAM cannot maintain the state of the storage capacitor, and the stored information is erased. In other words, the DRAM is a volatile memory device. Additionally, since the DRAM requires a refresh operation to rewrite data, as is well known, the operation speed is low.

As a nonvolatile memory having the function of inhibiting volatilization of data even in the power-off state, a ROM (Read Only Memory) is well known. However, this memory cannot erase or change recorded data. As a rewritable nonvolatile memory, a flash memory using an EEPROM (Electrically Erasable Programmable Read Only Memory) has been developed (Japanese Patent Laid-Open No. 8-031960, and Fujio Masuoka, “Applied Physics”, Vol. 73, No. 9, p. 1166, 2004). The flash memory is used in various fields as a practical nonvolatile memory.

In a memory cell of a typical flash memory, the gate electrode portion of the MOSFET has a stacked gate structure including a plurality of layers with a control gate electrode and floating gate electrode. The flash memory enables data recording by using a phenomenon that the threshold value of the MOSFET changes depending on the amount of charges stored in the floating gate.

The data write of the flash memory is done on the basis of a phenomenon that hot carriers generated by applying a high voltage to the drain region move over the energy barrier of the gate insulating film. When charges (generally, electrons) are injected from the semiconductor substrate to the floating gate by applying a high field to the gate insulating film and supplying an F-N (Fowler-Nordheim) tunnel current, data is written. The data is erased by removing charges from the floating gate by applying a high field in a reverse direction to the gate insulating film.

The flash memory requires no refresh operation, unlike the DRAM. However, since the F-N tunnel phenomenon is used, the time necessary for the data write and erase is much longer as compared to the DRAM. In addition, when the data write/erase is repeated, the gate insulating film degrades. Hence, the number of times of writes is limited to some extent.

As a new nonvolatile memory different from the above-described flash memory, a ferroelectric memory (to be referred to as an FeRAM (Ferroelectric RAM) hereinafter) using polarization of a ferroelectric or a ferromagnetic memory (to be referred to as an MRAM (Magnetoresist RAM) hereinafter) using the magnetoresistance of a ferromagnetic has received a great deal of attention and been studied extensively. The FeRAM is already put into practical use and therefore expected to replace not only a portable memory but also a logic DRAM if various problems can be solved.

Examples of the ferromagnetic are an oxide ferroelectric (also called a ferroelectric ceramic), a polymer ferroelectric represented by polyvinylidene fluoride (PVDF), and a fluoride ferroelectric such as BaMgF4. In the oxide ferroelectric and fluoride ferroelectric, polarization reverses due to a slight displacement of atoms which are causing the polarization. On the other hand, in the polymer ferroelectric, polarization reverses as individual molecular chains rotate, whose elementary process is a change in conformation (bonding form) of molecular chains which are bonded long by covalent bond.

Polymer ferroelectrics represented by polyvinylidene fluoride (PVDF) also includes P(VDF/TrFF), i.e., a copolymer of vinylidene fluoride (PDV) and ethylene trifluoride and is prepared by polymerization of a polymer. For further information about ferroelectrics, see “Development and Application of Ferroelectric Materials” edited by Tadashi Shiosaki, CMC Co. Ltd.

Of the above-described ferroelectric materials, the oxide ferroelectrics are mainly used for an FeRAM. Of the oxide ferroelectrics, ferroelectrics having a perovskite structure (to be referred to as perovskite ferroelectrics hereinafter) and, more particularly, lead-based ferroelectrics represented by Pb(Zr,Ti)O3(PZT) are widely used. However, use of lead-containing substances and lead oxides is restricted by the Industrial Safety and Health Law because of concerns about influence on the ecological system and an increase in environmental load. They are therefore being restricted in Europe and U.S.A. from the viewpoint of ecology and pollution control.

Non-lead (lead-free) ferroelectric materials equivalent to the performance of lead-based ferroelectrics have received a great deal of attention on a worldwide basis under the recent necessity for reducing the environmental load. Especially, lead-free perovskite ferroelectrics and bismuth layer-structured ferroelectrics (BLSF) are thought to be most promising. In fact, polarization amounts in these materials are smaller than in the lead-based ferroelectrics, and many unsolved problems still remain in both film formation and process.

FeRAMs that are expected to replace flash memories are mainly classified into stacked memories and FET memories. Stacked FeRAMs are also called 1-transistor/1-capacitor FeRAMs which are categorized in accordance with the structure into FeRAMs with a stacked capacitor as shown inFIG. 127, FeRAMs with a planar capacitor, and FeRAMs with a solid capacitor. The stacked FeRAMs include 1-transistor/1-capacitor FeRAMs and 2-transistor/2-capacitor FeRAMs formed by stacking two 1-transistor/1-capacitor FeRAMs to stabilize the operation.

The stacked FeRAM shown inFIG. 127comprises, on a semiconductor substrate12701, a MOS transistor including a source12702, a drain12703, and a gate electrode12705provided on a gate insulating film12704. A capacitor including a lower electrode12711, a dielectric layer12712made of a ferroelectric, and an upper electrode12713is connected to the source12702of the MOS transistor. In the example shown inFIG. 127, the capacitor is connected to the source12702by a source electrode12706. A drain electrode12707is connected to the drain12703. An ammeter is connected to the drain electrode12707.

This structure has a function of extracting “on” or “off” data by detecting the direction of polarization of the dielectric layer12712made of a ferroelectric as a current flowing between the source and drain (channel12721). The structure has nonvolatility because the polarization of the ferroelectric can be held even without voltage application. In this structure, however, since data is destroyed in the data read, the data must be rewritten, and the speed is therefore low. Additionally, since the area occupied by one element is large, the structure is unsuitable for increasing integration.

In addition to the above-described stacked FeRAMs, FET FeRAMs are expected as FeRAMs of next generation. FET FeRAMs are also called 1-transistor FeRAMs which are categorized in accordance with the structure into MFS (Metal-Ferroelectric-Semiconductor) FeRAMs in which ferroelectric films are arranged in place of the gate electrode of a MOSFET and the gate insulating film in the channel region, MFMIS (Metal-Ferroelectric-Metal-Insulator-Semiconductor) FeRAMs in which a ferroelectric film is arranged on the gate electrode of a MOSFET, and MFIS (Metal-Ferroelectric-Insulator-Semiconductor) FeRAMs as shown inFIG. 128in which a ferroelectric film is arranged between the gate electrode of a MOSFET and the gate insulating film (Koichiro Inomata, Shuichi Tahara, & Yoshihiro Arimoto, “MRAM Technology—from Fundamentals to LSI Applications”, SIPEC).

In the MFIS shown inFIG. 128, a source12802and drain12803are provided on a semiconductor substrate12801. A dielectric layer12805made of a ferroelectric is provided on a gate insulating film12804arranged between the source and drain. A gate electrode12806is provided on the dielectric layer12805. A source voltage is applied to the source12802through a source electrode12807. An ammeter is connected to the drain12803through a drain electrode12808.

In this FeRAM, polarization of a ferroelectric is applied to the operation of a MOSFET. The FeRAM has a function of creating, by the polarization state, a state wherein a channel12821is formed in the semiconductor surface immediately under the gate insulating film12804and a state wherein no channel is formed, reading the current value between the source and drain, and extracting the state as “on” or “off” of an electrical digital signal.

In the FET FeRAM, nondestructive read is possible owing to the operation principle because the polarization amount of the ferroelectric does not change even when data is read out. Hence, a high-speed operation is expected. Since the occupation area can be reduced as compared to the 1-transistor/1-capacitor FeRAM, the FET FeRAM is advantageous in increasing integration. Actually, of the 1-transistor FeRAMs, the MFIS FeRAM (FIG. 128) has the gate insulating film between the ferroelectric film and the semiconductor, and for this reason, a polarization reducing field to cancel the polarization amount of the ferroelectric is generated.

To implement the above-described structure, a high-quality high-K dielectric film having a polarization characteristic and orientation is formed on an insulating film generally made of an amorphous material. It is however difficult to form a ferroelectric with a high orientation on an insulating film by using an existing film formation method to be described later. For this reason, in the MFIS FeRAM manufactured by the conventional technique, polarization cannot hold because of the polarization reducing field, and data cannot be held for a long time. If the quality of the insulating film formed on the semiconductor is poor, the polarization amount of the ferroelectric further decreases due to a leakage current generated by the electric field. For these reasons, the data holding period (data life) of the operation of the current MFIS FeRAM serving as a memory remains about 10 days. It is far from commercialization.

In the MFMIS FeRAM, a ferroelectric can be formed on a crystal metal electrode (generally Pt or SrRuO2). Hence, a high-quality film can be formed because the ferroelectric need not be formed on an insulating film, unlike the MFIS FeRAM structure. However, no method to stably form a ferroelectric on a metal has been proposed yet. Since the decrease in polarization by the polarization reducing field generated by the insulating film on the semiconductor poses a problem even in this case, long-term data holding cannot be implemented.

In the MFS FeRAM, since no insulating film is necessary on the semiconductor, the decrease in polarization by the polarization reducing field can be avoided in principle. However, since a ferroelectric film formation method such as a sol-gel process or MOCVD requires a high film formation temperature, the surface of the semiconductor such as Si is oxidized or deteriorated, resulting in an oxide film or many defects on the interface. If an oxide film (interface oxide film) is consequently formed in the interface between the semiconductor and ferroelectric, a polarization reducing field is generated, like the MFIS FeRAM.

If no interface oxide film but a number of defect levels are formed on the interface, the influence of stored charges becomes large, and no accurate memory operation is performed. If the formed ferroelectric film has a poor quality, the leakage current flows in the film, and the polarization characteristic cannot be held for a long time, as is pointed out in many reports.

In the above-described FeRAMs, formation of an oxide ferroelectric on a substrate is important. Various formation apparatuses and various thin film formation methods have been tested until now. Examples are CSD (Chemical Solution Deposition) including a sol-gel process and MOD (Metal-Organic Deposition), MOCVD (Metal-Organic Chemical Vapor Deposition) or MOVPE, PLD (Pulse Laser Deposition), LSMCD (Liquid Source Misted Chemical Deposition), EPD (Electro-Phoretic Deposition), RF-sputtering (also called RF sputtering or magnetron sputtering), and ECR sputtering (Electron Cyclotron Resonance sputtering).

The mainstream of these film formation methods is the CSD called a sol-gel process or MOD. In the CSD, a film is formed by dissolving the matrix of a ferroelectric in an organic solvent and repeatedly applying and sintering the resultant solution on a substrate. As a characteristic feature, a ferroelectric film with a relatively large area can be formed by a simple method. As is reported from many institutions, the CSD can form a ferroelectric film having an arbitrary composition by controlling the composition of the solution to be applied.

There are however problems that it may be impossible to form a film because of poor wettability of the substrate to which the solution is applied and that the solvent used to prepare the solution may remain in the formed film so no high film quality can be obtained. Additionally, in the CSD, the sintering temperature must be higher than the Curie temperature of the ferroelectric film. If the temperature or atmosphere cannot be controlled well, no high-quality film is obtained at all.

Ferroelectric film formation by methods except the CDS have also been tested. For example, the PLD has attracted attention, in which a ferroelectric film having high quality can be formed by sputtering a target of a ferroelectric material with a strong laser source such as an excimer laser. In this method, however, the area of the laser irradiated portion in the target plane is very small, and the material sputtered and supplied from the small irradiated plane has a large distribution. For this reason, in the PLD, a large in-plane distribution is formed in the thickness or quality of the ferroelectric formed on the substrate. There is also a serious problem in reproducibility because the properties change even under the same formation conditions.

However, these properties are suitable for specifically examining conditions. A combinatorial method has received attention as a method of examining the film formation properties by using the above-described properties. However, from the industrial viewpoint, a method capable of forming a large-area film with good reproducibility is essential. It is difficult to industrially use the current PLD.

In addition to the above-described various film formation methods, a sputtering method (to be also simply referred to as sputtering) has received a great deal of attention as a ferroelectric film formation method. Sputtering is a promising film formation apparatus/method because neither dangerous gas nor toxic gas need be used, and a deposited film can have a relatively good surface roughness (surface morphology). In sputtering, a reactive sputtering apparatus/method is considered as a promising apparatus/method for obtaining a ferroelectric film with a stoichiometric composition, in which any oxygen or nitrogen defect is prevented by supplying oxygen gas or nitrogen gas.

In the conventionally used RF sputtering method (conventional sputtering), a compound (sintered body) target is used to deposit an oxide ferroelectric. In the conventional sputtering, however, when an oxide ferroelectric is formed by using argon as an inert gas and oxygen as a reactive gas, oxygen in the ferroelectric film formed on the substrate is not sufficiently captured so no ferroelectric with high quality can be obtained.

For this reason, after the ferroelectric is deposited, the quality of the ferroelectric film formed on the substrate must be improved by executing a heat treatment called annealing in oxygen by using a furnace. In the conventional sputtering, hence, a process called annealing is added, and the manufacturing process becomes complex. In the annealing process, since control is done to obtain a predetermined quality, the conditions such as the temperature must be controlled strictly. Furthermore, annealing may be impossible depending on the material of the formed film.

An example of the method of improving the quality of a sputter film is ECR (Electron Cyclotron Resonance) sputtering. In this method, plasma is produced by ECR. The substrate is irradiated with a plasma flow generated by using the divergent magnetic field of the plasma. Simultaneously, a high frequency or negative DC voltage is applied between the target and ground. Ions in the plasma flow generated by ECR are introduced and made to collide against the target to execute sputtering, thereby depositing a film on the substrate.

In the conventional sputtering, no stable plasma can be obtained without a gas pressure of about 0.1 Pa or more. In the ECR sputtering, stable plasma is obtained at a pressure on the order of 0.01 Pa. In the ECR sputtering, since particles generated by ECR by using a high frequency or high negative DC voltage are caused to strike the target to execute sputtering, sputtering can be done at a low pressure.

In the ECR sputtering, the substrate is irradiated with the ECR plasma flow and sputtered particles. Ions in the ECR plasma flow have an energy of 10 to several ten eV by the divergent magnetic field. In addition, since the plasma is produced and transported at such a low pressure that a gas behaves as a molecular flow, the ion current density of the ions that arrive at the substrate can also be ensured high. Hence, the ions in the ECR plasma give an energy to the material particles which are sputtered and come onto the substrate and also promote the bonding reaction between the material particles and oxygen. Hence, the quality of the deposited film is improved.

As a characteristic feature of ECR sputtering, a high-quality film can be formed at a low substrate temperature. For further information about how to deposit a high-quality thin film by ECR sputtering, see, e.g., Japanese Patent Nos. 2814416 and 2779997 and Amazawa et al., “J. Vac. Sci. Technol.”, B 17, No. 5, 2222 (1999). The ECR sputtering is suitable for forming a very thin film such as a gate insulating film while controlling the thickness well because of the relatively stable film deposition rate. The surface morphology of the film deposited by ECR sputtering is flat on the order of atomic scale. Hence, the ECR sputtering can be regarded as a promising method not only for forming a gate insulating film with high permittivity but also for forming a ferroelectric film necessary for the above-described FeRAM or a metal electrode film.

Predecessors tried to select conditions to form a film made of a ferroelectric material by regarding the ECR sputtering as similar to the conventional sputtering. Hence, even when a ferroelectric film is formed by using the ECR sputtering, no satisfactory ferroelectricity applicable to the FeRAM cannot be obtained so far.

Under the above-described circumstances surrounding the memories, a technique has been proposed (Japanese Patent Laid-Open No. 7-263646), in which the resistance value of a ferroelectric layer12902directly formed on a semiconductor substrate12901is changed, thereby implementing the memory function, as shown inFIG. 129, instead of implementing a memory by changing the state of a semiconductor (forming a channel) by the polarization amount of a ferroelectric. The resistance value of the ferroelectric layer12902is controlled by applying a voltage between electrodes12903and12904.

DISCLOSURE OF INVENTION

Problems to be Solved by the Invention

The structure proposed in patent reference 6 shown inFIG. 129has a ferroelectric layer on the semiconductor, like the structure immediately under the gate electrode of the above-described MFS FeRAM. Hence, in the element shown inFIG. 129, it is difficult to form a high-quality ferroelectric layer on the semiconductor, like the largest challenge in the manufacturing process of the MFS FeRAM. In addition, a semiconductor oxide is formed between the semiconductor and the ferroelectric layer. It is conceivable that a polarization reducing field or a number of defects will greatly influence the properties and make it impossible to hold data for a long time. In fact, the element shown inFIG. 129can achieve a holding period of only about 2 min. That is, a data rewrite must be done in about 1 min.

The current-voltage hysteresis observed in the element shown inFIG. 129is supposed to occur because defects generated in the interface between the semiconductor substrate12901and the ferroelectric layer12902capture (trap) electrons or holes. In patent reference 6, a material with a small number of carriers related to electrical conduction is preferable, and the semiconductor substrate12901is suitable. However, since the carrier trap phenomenon of interface defects is used, an increase in the number of traps to capture carriers generates a leakage current and shortens the data holding period accordingly. When the ferroelectric layer12902is formed on the semiconductor substrate12901without any interface to reduce the leakage current, no carrier capture occurs, and the memory effect is lost. Because of this contradiction, the element shown inFIG. 129is unsuitable for long-term data holding in principle.

The present invention has been made to solve the above-described problems, and has as its object to provide an element capable of obtaining a stable operation by using a metal oxide and, e.g., forming a memory device capable of holding data more stably.

Means of Solution to the Problems

A bistable resistance value acquisition device according to the present invention comprises at least a first metal oxide layer which is made of a metal oxide containing at least two metals, is formed on a substrate, and has a predetermined thickness, a first electrode which is formed on one surface of the first metal oxide layer, and a second electrode which is formed on the other surface of the first metal oxide layer.

In the bistable resistance value acquisition device, a third electrode spaced apart from the second electrode may be provided on the other surface of the first metal oxide layer. In this case, a 3-terminal element can be constructed by a gate electrode formed from the first electrode, a source electrode formed from the second electrode, and a drain electrode formed from the third electrode.

The bistable resistance value acquisition device may further comprise at least a second metal oxide layer which is made of the metal oxide, is formed on the substrate, and has a predetermined thickness, and a fourth electrode which is provided on the second metal oxide layer, wherein the first electrode, the first metal oxide layer, the second metal oxide layer, and the fourth electrode may be connected in series in an order named.

The bistable resistance value acquisition device may further comprise an insulating layer which is formed in contact with at least one of one surface and the other surface of the first metal oxide layer. The bistable resistance value acquisition device may further comprise an insulating layer which is formed in contact with at least one of one surface and the other surface of the second metal oxide layer. The bistable resistance value acquisition device may further comprise at least an amorphous layer in an amorphous state which is formed on the substrate, a plurality of elements each of which includes the first electrode made of a conductive material in a crystalline state and formed on the amorphous layer, the first metal oxide layer formed on the first electrode, and the second electrode formed on the first metal oxide layer, and an isolation layer which is made of the metal oxide and formed on the amorphous layer between the elements, wherein the plurality of elements may be isolated by the isolation layer. In this case, the first metal oxide layer and the isolation layer may be formed integrally.

In the bistable resistance value acquisition device, a resistance value of the metal oxide changes depending on an electrical signal supplied between the first electrode and the second electrode. For example, the metal oxide changes to a first state having a first resistance value upon application of a voltage having not less than a first voltage value and a second state having a second resistance value different from the first resistance value upon application of a voltage having not more than a second voltage value with a polarity different from the first voltage value. Alternatively, the metal oxide changes to a first state having a first resistance value upon application of a voltage more than a first voltage value and a second state having a second resistance value larger than the first resistance value upon application of a voltage more than a second voltage value in a range not more than the first voltage.

In the bistable resistance value acquisition device, the metal oxide comprises at least a base layer made of at least a first metal and oxygen, and a plurality of fine particles made of the first metal, a second metal, and oxygen and dispersed in the base layer. At this time, the base layer need only be made of the first metal, the second metal, and oxygen in which a content of the second metal is smaller in comparison with a stoichiometric composition. The base layer may contain the first metal, the second metal, and a column crystal of oxygen. The metal oxide may comprise a metal oxide monolayer in at least one of a column-crystal state and an amorphous state, which is arranged in contact with the base layer and made of at least the first metal and oxygen. In the metal oxide monolayer, a content of the second metal is smaller in comparison with a stoichiometric composition of the first metal, the second metal, and oxygen. The metal oxide monolayer does not contain the fine particles. The first metal is titanium, the second metal is bismuth, and the base layer need only be in amorphous state and be formed from a layer containing titanium in an excessive amount relative to a stoichiometric composition. In the bistable resistance value acquisition device, the metal oxide may be a ferroelectric.

In the bistable resistance value acquisition device, the first electrode need only be made of at least one of ruthenium and platinum and have at least one of a single-layer structure made of a single material and a layered structure made of a plurality of materials. The substrate may be made of a conductive material. The first electrode may be identical to the substrate.

A bistable resistance value acquisition device manufacturing method according to the present invention is a method of manufacturing a bistable resistance value acquisition device including at least a first metal oxide layer which is made of a metal oxide containing at least two metals, is formed on a substrate, and has a predetermined thickness, a first electrode which is formed on one surface of the first metal oxide layer, and a second electrode which is formed on the other surface of the first metal oxide layer, which comprises the first step of producing a first plasma made of an inert gas and oxygen gas which are supplied at a predetermined composition ratio, applying a negative bias to a target made of at least a first metal and a second metal and causing particles generated from the first plasma to collide against the target to cause a sputtering phenomenon, and depositing a material of the target, thereby forming the first metal oxide layer made of a metal oxide containing the first metal, the second metal, and oxygen, wherein the first plasma is an electron cyclotron resonance plasma which is produced by electron cyclotron resonance and receives kinetic energy from a divergent magnetic field, and the substrate is heated to a predetermined temperature.

The bistable resistance value acquisition device manufacturing method further comprises the second step of irradiating a surface of a layer made of the metal oxide with a second plasma made of an inert gas and a reactive gas which are supplied at a predetermined composition ratio, wherein the second plasma need only be an electron cyclotron resonance plasma which is produced by electron cyclotron resonance and receives kinetic energy from a divergent magnetic field. The reactive gas need only be oxygen gas. In the first step, the substrate is preferably heated to a temperature not more than a Curie temperature of the metal oxide. A voltage to control ion energy generated by the plasma may be applied to the substrate. The first metal only need be titanium, and the second metal only need be bismuth. The target need only be made of at least the first metal, the second metal, and oxygen.

A metal oxide thin film according to the present invention comprises at least a base layer which is made of at least a first metal and oxygen, and a plurality of microcrystalline grains (e.g., microcrystalline grains having a stoichiometric composition) which are made of the first metal, a second metal, and oxygen and dispersed in the base layer.

A metal oxide thin film forming method according to the present invention comprises the step of producing a first plasma made of an inert gas and oxygen gas which are supplied at a predetermined composition ratio, applying a negative bias to a target made of at least a first metal and a second metal and causing particles generated from the first plasma to collide against the target to cause a sputtering phenomenon, and depositing a material of the target on a substrate, thereby forming, on the substrate, a metal oxide thin film including at least a base layer which is made of at least the first metal and oxygen, and a plurality of fine particles which are made of the first metal, a second metal, and oxygen and dispersed in the base layer, wherein the first plasma is an electron cyclotron resonance plasma which is produced by electron cyclotron resonance and receives kinetic energy from a divergent magnetic field, and the substrate is heated to a predetermined temperature. The first metal is titanium, and the second metal is bismuth.

EFFECT OF THE INVENTION

As described above, according to the present invention, an element is formed by preparing a first electrode on one surface of a first metal oxide layer made of a metal oxide containing at least two metals and having a predetermined thickness, and a second electrode on the other surface. Hence, an element capable of obtaining a stable operation by using a metal oxide can be provided so that, e.g., a memory device capable of holding data more stably can be formed.

BEST MODE FOR CARRYING OUT THE INVENTION

An embodiment of the present invention will be described below with reference to the accompanying drawings.FIG. 1Ais a schematic sectional view showing a structure example of a bistable resistance value acquisition device according to an embodiment of the present invention.FIG. 1Bis a partial sectional view. Application to a ferroelectric element which uses a metal oxide layer (ferroelectric layer104) exhibiting ferroelectric properties will be described below. The element shown inFIG. 1Acomprises, on a substrate101made of, e.g., single-crystal silicon, an insulating layer102, a lower electrode layer103, the ferroelectric layer104containing, e.g., Bi and Ti and having a thickness of about 30 to 200 nm, and an upper electrode105.

The substrate101can be made of any one of a semiconductor, insulator, and conductive material such as a metal. When the substrate101is made of an insulating material, the insulating layer102can be omitted. When the substrate101is made of a conductive material, the insulating layer102and lower electrode layer103can be omitted. In this case, the substrate101made of the conductive material serves as a lower electrode.

The lower electrode layer103and upper electrode105need only be made of a transition metal including noble metals such as platinum (Pt), ruthenium (Ru), gold (Au), and silver (Ag). The lower electrode layer103and upper electrode105may be made of a compound such as a nitride, oxide, or fluoride of a transition metal, such as titanium nitride (TiN), hafnium nitride (HfN), strontium ruthenate (SrRuO2), zinc oxide (ZnO), indium tin oxide (ITO), or lanthanum fluoride (LaF3), or a composite film formed by stacking them.

The ferroelectric layer104is made of an oxide ferroelectric. The ferroelectric layer104need only be made of, e.g., a material having a perovskite structure, a material having a pseudo-ilmenite structure, a material having a tungsten-bronze structure, a material having a bismuth layer-structure, or a material having a pyrochlore structure. Examples are BaTiO3, Pb(Zr,Ti)O3, (Pb,La)(Zr,Ti)O3, LiNbO3, LiTaO3, PbNb3O6, PbNaNb5O15, Cd2Nb2O7, Pb2Nb2O7, Bi4Ti3O12, (Bi,La)4Ti3O12, and SrBi2Ta2O9.

The ferroelectric layer104is made of a material such as an oxide, nitride, or fluoride which contains at least two metals and generally exhibits ferroelectric properties. A state wherein no ferroelectric properties are exhibited depending on the film thickness condition is also included. A “ferroelectric” to be described below also indicates a metal compound which contains at least two metals and generally exhibits ferroelectric properties.

A detailed example of the ferroelectric element shown inFIGS. 1A and 1Bwill be described. For example, the lower electrode layer103is a ruthenium film having a thickness of 10 nm. The ferroelectric layer104is a Bi4Ti3O12film having a thickness of 40 nm. The upper electrode105is made of gold. The structures of the substrate101and insulating layer102are not limited to those described above, and any other material can also be selected appropriately if it has no effect on the electrical characteristics.

The ferroelectric layer104will be described next in more detail. As shown in the enlarged view ofFIG. 1B, the ferroelectric layer104is formed by dispersing a plurality of microcrystalline grains142of Bi4Ti3O12crystal with a grain size of about 3 to 15 nm in a base layer141, i.e., a layer containing titanium in an excessive amount relative to the stoichiometric composition of Bi4Ti3O12. This is confirmed by observation using a transmission electron microscope. The base layer141may be TiOxwith a bismuth content of almost 0. In other words, the base layer141is made of a metal oxide which contains two metals and in which the content of one metal is smaller in comparison with the stoichiometric composition.FIG. 1Bis a sectional view schematically showing the approximate state of the ferroelectric layer104.

According to the ferroelectric element using the ferroelectric layer104, a functional element that holds two states can be implemented, as will be described later. The characteristics of the ferroelectric element shown inFIGS. 1A and 1Bwill be described. The characteristics were investigated by applying a voltage between the lower electrode layer103and the upper electrode105. When a voltage from a power supply was applied between the lower electrode layer103and the upper electrode105, and a current flowing when the voltage was applied was measured by an ammeter, a result shown inFIG. 2was obtained. Referring toFIG. 2, the ordinate represents the current density obtained by dividing the current value by the area.

FIG. 2and the operation principle of the ferroelectric element shown inFIGS. 1A and 1Bwill be described below. The voltage values and current values to be described here are mere examples measured in an actual element. Hence, the phenomenon is not limited to the following numerical values. Other numerical values can also be measured depending on the material and thickness of each film actually used in the element and other conditions.

FIG. 2shows the hysteresis characteristics of the values of currents which flow in the ferroelectric layer104when the voltage applied to the upper electrode105is increased from 0 in the positive direction, returned to 0, decreased in the negative direction, and finally returned to 0 again. When the voltage applied to the upper electrode105is gradually increased from 0 V in the positive direction, the positive current flowing in the ferroelectric layer104is relatively small (about 0.014 A/cm2at 0.1 V).

When the voltage exceeds 0.5 V, the positive current value starts abruptly increasing. After the voltage is increased up to about 1 V, the positive voltage is decreased. Even when the voltage decreases from 1 V to about 0.7 V, the positive current value further increases. When the voltage is lower than about 0.7 V, the current value also starts decreasing. At this time, the positive current readily flows as compared to the previous state. The current value is about 1.3 A/cm2at 0.1 V (100 times the previous current value). When the applied voltage is returned to 0, the current value also becomes 0.

Next, a negative voltage is applied to the upper electrode105. In this state, when the negative voltage is low, a relatively large negative current flows according to the previous hysteresis. When the applied negative voltage is changed up to about −0.5 V, the negative current suddenly starts decreasing. Even when the applied negative voltage is changed up to about −1 V, the negative current value continuously decreases. Finally, the applied negative voltage is decreased from −1 V to 0 V, the negative current value further decreases together and returns to 0. In this case, the negative current hardly flows and about −0.035 A/cm2at −0.1 V.

The above-described hysteresis of the current flowing in the ferroelectric layer104can be regarded as being generated because the resistance value of the ferroelectric layer104changes depending on the voltage applied to the upper electrode105. When a positive voltage VW1with a predetermined magnitude or more is applied, the ferroelectric layer104changes to a “low resistance state” (data “1”) wherein the current easily flows. When a negative voltage VW0with a predetermined magnitude is applied, the ferroelectric layer104changes to a “high resistance state” (data “0”) wherein the current hardly flows.

The ferroelectric layer104has the two stable states, i.e., low resistance state and high resistance state. Each state remains unless the above-described positive or negative voltage with a predetermined magnitude or more is applied. The value of VW1is about +1 V. The value of VW0is about −1 V. The resistance ratio of the high resistance state to the low resistance state is about 10 to 100. When the above-described phenomenon that the resistance of the ferroelectric layer104is switched by the voltage is used, a nonvolatile functional element capable of a nondestructive read operation can be implemented by the ferroelectric element shown inFIGS. 1A and 1B.

When a DC voltage is used, the memory operation of the ferroelectric element shown inFIG. 1Ais executed in the following way. First, a positive voltage with the magnitude VW1or more is applied to change the ferroelectric layer104to the low resistance state. This sequence corresponds to writing data “1” in the memory. The data “1” can be read out by measuring a current value JR1at a read voltage VR. It is important to select, as VR, such a small value to obtain a sufficient resistance ratio and not to cause state transition (about 0.1 V in the above example). Hence, the read can be done many times without destroying the low resistance state, i.e., data “1”.

On the other hand, when a negative voltage with the magnitude VW0or more is applied, the ferroelectric layer104changes to the high resistance state so that data “0” can be written. This state can be read out by measuring a current value JR0at the read voltage VR(JR1/JR0≈10 to 100). When the electrodes are not energized, the ferroelectric layer104has nonvolatility to hold each state. Except in the write and read, no voltage need be applied. This element can also be used as a switching element to control the current.

FIG. 3shows the data holding characteristic of the ferroelectric element shown inFIG. 1A. For example, the positive voltage VW1is applied to the upper electrode105to change the ferroelectric layer to the low resistance state (data “1”) shown inFIG. 2. Then, the read voltage VRis applied, and the current value JR1is measured. Next, the negative voltage VW0is applied to the upper electrode105to change the ferroelectric layer to the high resistance state to write data “0”. After that, the read voltage VRis applied to the upper electrode105for every predetermined time, and the current value JR0is measured. The ON/OFF ratio of the ferroelectric element can be represented by the value JR1/JR0.FIG. 3plots the value JR1/JR0along the ordinate and shows a time-rate change in value JR1/JR0obtained by the above-described measurement.

The calculated ON/OFF ratio tends to gradually decrease over time but falls within a range where data discrimination is sufficiently possible. The ON/OFF ratio 1,000 min after, which is predicted from the extrapolated line (broken line) by the calculation result indicated by dots inFIG. 3, is about 21. Discrimination is possible even at this point. As is apparent, the ferroelectric element shown inFIG. 1Ahas a holding time of at least 1,000 min. In the above-described embodiment, a DC voltage is applied. However, the same effect can be obtained even by applying a pulse voltage having appropriate width and magnitude.

An example of a method of manufacturing the ferroelectric element shown inFIG. 1Awill be described next. A method of forming each thin film by using ECR plasma sputtering will be described below. However, the present invention is not limited to this, and any other film formation technique or method can be used, as a matter of course.

As shown inFIG. 4A, the p-type silicon substrate101having a plane orientation of (100) on the principal plane and a resistivity of 1 to 2 Ωcm is prepared. The surface of the substrate101is cleaned by a solution mixture of sulfuric acid and a hydrogen peroxide solution, pure water, and a hydrogen fluoride solution and dried. The insulating layer102is formed on the cleaned and dried substrate101. In forming the insulating layer102, the above-described ECR sputtering apparatus and pure silicon (Si) as a target are used. The insulating layer102in a metal mode by Si—O molecules is formed on the substrate101to a thickness to just cover its surface by ECR sputtering using argon (Ar) as a plasma gas and oxygen gas.

For example, Ar gas is supplied at a flow rate of 20 sccm into a plasma production chamber whose internal pressure is set on the order of 10−5Pa. The internal pressure is set to about 10−3to 10−2Pa. A microwave of 2.45 GHz (about 500 W) and a magnetic field of 0.0875 T are supplied to set the electron cyclotron resonance condition, thereby producing Ar plasma in the plasma production chamber. Note that sccm is the unit of flow rate and indicates that a fluid at 0° C. and 1 atmospheric pressure flows 1 cm3in 1 min. T (tesla) is the unit of magnetic flux density, and 1 T=10,000 gauss.

The plasma produced by the above-described method is output from the plasma production chamber to the process chamber side by the divergent magnetic field of the magnetic coil. In addition, a high-frequency power of 13.56 MHz (e.g., 500 W) is supplied from a high-frequency power supply to the silicon target placed at the outlet of the plasma production chamber. When Ar ions collide against the silicon target, a sputtering phenomenon occurs to sputter Si particles. The Si particles sputtered from the silicon target reach the surface of the substrate101together with the plasma output from the plasma production chamber and the oxygen gas which is supplied and activated by the plasma and are oxidized to silicon dioxide by the activated oxygen. With the above process, the insulating layer102made of silicon dioxide and having a thickness of, e.g., about 100 nm can be formed on the substrate101(FIG. 4A).

The insulating layer102ensures insulation to prevent a voltage from leaking to the substrate101and influencing desired electrical characteristics when a voltage is applied between the lower electrode layer103and upper electrode105to be formed later. For example, a silicon oxide film formed by oxidizing the surface of the silicon substrate by thermal oxidation may be used as the insulating layer102. The insulating layer102may be made of any other insulating material except silicon oxide if the insulating properties can be ensured. The thickness of the insulating layer102need not always be 100 nm and may be smaller or larger. In the above-described formation of the insulating layer102by ECR sputtering, the substrate101is not heated. However, the film may be formed while heating the substrate101.

After the insulating layer102is formed in the above-described manner, a ruthenium film is formed on the insulating layer102by similar ECR sputtering using pure ruthenium (Ru) as a target, thereby forming the lower electrode layer103, as shown inFIG. 4B. Formation of the Ru film will be described in detail. In an ECR sputtering apparatus using a Ru target, for example, the silicon substrate with the insulating layer formed on it is heated to 400° C. Ar gas as a rare gas is supplied into the plasma production chamber at a flow rate of, e.g., 7 sccm. In addition, Xe gas is supplied at a flow rate of, e.g., 5 sccm to set the internal pressure of the plasma production chamber on the order of, e.g., 10−2to 10−3Pa.

The magnetic field of the electron cyclotron resonance condition is given to the plasma production chamber. Then, a microwave of 2.45 GHz (about 500 W) is supplied into the plasma production chamber to produce ECR plasma of Ar and Xe in it. The produced ECR plasma is output from the plasma production chamber to the process chamber side by the divergent magnetic field of the magnetic coil. In addition, a high-frequency power of 13.56 MHz (e.g., 500 W) is supplied to the ruthenium target placed at the outlet of the plasma production chamber. The sputtering phenomenon occurs to sputter Ru particles from the ruthenium target. The Ru particles sputtered from the ruthenium target reach the surface of the insulating layer102on the substrate101and are deposited.

With the above process, the lower electrode layer103having a thickness of, e.g., about 10 nm can be formed on the insulating layer102(FIG. 4B). The lower electrode layer103enables voltage application to the ferroelectric layer104when a voltage is applied between the lower electrode layer103and the upper electrode105to be formed later. The lower electrode layer103may be made of any other material except ruthenium if the conductivity can be ensured. The lower electrode layer103may be made of, e.g., platinum. A platinum film formed on silicon dioxide readily peels off, as is known. To prevent this, a layered structure is formed by inserting a titanium layer, titanium nitride layer, or ruthenium layer under the platinum layer. The thickness of the lower electrode layer103need not always be 10 nm and may be smaller or larger.

As described above, in forming the Ru film by ECR sputtering, the substrate101is heated to 400° C. However, the substrate need not always be heated. However, if the substrate is not heated, the adhesion of ruthenium to silicon dioxide becomes low, and the film may peel off. To prevent peeling, the film is formed preferably while heating the substrate.

After the lower electrode layer103is formed in the above-described manner, the ferroelectric layer104is formed on the lower electrode layer103to a thickness to just cover its surface, as shown inFIG. 4C, by ECR sputtering using argon (Ar) as a plasma gas and oxygen gas and a target formed from an oxide sintered body (Bi—Ti—O) in which the ratio of Bi to Ti is 4:3.

Formation of the ferroelectric layer104will be described in detail. The substrate101is heated to 300° C. to 700° C. Ar gas as a rare gas is supplied into the plasma production chamber at a flow rate of, e.g., 20 sccm to set the pressure on the order of, e.g., 10−3to 10−2Pa. In this state, the magnetic field of the electron cyclotron resonance condition is given to the plasma production chamber. Then, a microwave of 2.45 GHz (about 500 W) is supplied into the plasma production chamber to produce ECR plasma in it.

The produced ECR plasma is output from the plasma production chamber to the process chamber side by the divergent magnetic field of the magnetic coil. In addition, a high-frequency power of 13.56 MHz (e.g., 500 W) is supplied to the sintered body target placed at the outlet of the plasma production chamber. When Ar particles collide against the sintered body target, the sputtering phenomenon occurs to sputter Bi particles and Ti particles.

The Bi particles and Ti particles sputtered from the sintered body target reach the surface of the heated lower electrode layer103together with the ECR plasma output from the plasma production chamber and the oxygen gas activated by the output ECR plasma and are oxidized by the activated oxygen. The oxygen (O2) gas serving as a reactive gas is supplied at a flow rate of, e.g., 1 sccm separately from the Ar gas, as will be described later. Although the sintered body target contains oxygen, any shortage of oxygen in the deposited film can be prevented by supplying oxygen. With the above-described film formation by ECR sputtering, the ferroelectric layer104having a thickness of, e.g., about 40 nm can be formed (FIG. 4C).

The film quality may be improved by irradiating the formed ferroelectric layer104with ECR plasma of an inert gas and a reactive gas. As the reactive gas, not oxygen gas but nitrogen gas, fluorine gas, or hydrogen gas can be used. The film quality improvement can also be applied to formation of the insulating layer102. The ferroelectric layer104may be formed at a low substrate temperature of 300° C. or less and then annealed (heat-treated) in an appropriate gas atmosphere such as oxygen atmosphere to greatly improve the properties of the film.

After the ferroelectric layer104is formed in the above-described way, the upper electrode105made of Au and having a predetermined area is formed on the ferroelectric layer104, as shown inFIG. 4D, thereby obtaining the element using a layer formed from a metal oxide thin film according to this embodiment. The upper electrode105can be formed by a well-known lift-off method and gold deposition by resistance heating vacuum deposition. The upper electrode105may be made of another metal material or conductive material such as Ru, Pt, or TiN. When Pt is used, the adhesion is poor, and the film may peel off. Hence, the upper electrode105must be formed as an electrode with a predetermined area by using a structure such as Ti—Pt—Au that hardly peels off and executing a patterning process such as photolithography or lift-off on that structure.

The above-described layer formation by ECR sputtering is done by using an ECR sputtering apparatus shown inFIG. 5. The ECR sputtering apparatus shown inFIG. 5will be described. The ECR sputtering apparatus comprises a process chamber501and a plasma production chamber502communicating with the process chamber501. The process chamber501communicates with a vacuum pumping apparatus (not shown). The vacuum pumping apparatus evacuates the process chamber501and plasma production chamber502. A substrate holder504to fix the substrate101as the film formation target is provided in the process chamber501. The substrate holder504can be tilted at a desired angle and rotated by a tilting/rotating mechanism (not shown). When the substrate holder504is tilted and rotated, the film in-plane uniformity and step coverage of a deposited material can be improved.

A ring-shaped target505surrounds the opening region of the process chamber501to which plasma is supplied from the plasma production chamber502. The target505is placed in a container505amade of an insulator. The inner surface of the target505is exposed to the interior of the process chamber501. A high-frequency power supply522is connected to the target505through a matching unit521so that a high frequency of, e.g., 13.56 MHz can be applied. If the target505is made of a conductive material, a negative DC voltage may be applied. The target505may have not the circular shape but a polygonal shape when viewed from the upper side.

The plasma production chamber502communicates with a vacuum waveguide506. The vacuum waveguide506is connected to a waveguide508through a quartz window507. A magnetic coil (magnetic field formation means)510is provided around the plasma production chamber502and at the upper portion of the plasma production chamber502. The microwave generation unit, waveguide508, quartz window507, and vacuum waveguide506form a microwave supply means. A mode converter may be provided midway in the waveguide508.

An operation example of the ECR sputtering apparatus shown inFIG. 5will be described. The process chamber501and plasma production chamber502are evacuated to 10−5to 10−4Pa. Argon gas as an inert gas is supplied from an inert gas supply unit511, and a reactive gas such as oxygen gas is supplied from a reactive gas supply unit512to set the internal pressure of the plasma production chamber502to about 10−3to 10−2Pa. In this state, a magnetic field of 0.0875 T is generated in the plasma production chamber502by the magnetic coil510. Then, a microwave of 2.45 GHz is supplied into the plasma production chamber502through the waveguide508and quartz window507to produce electron cyclotron resonance (ECR) plasma.

The ECR plasma forms a plasma flow in the direction of the substrate holder504by the divergent magnetic field from the magnetic coil510. Of the produced plasma, electrons are passed through the target505and attracted to the side of the substrate101by the divergent magnetic field formed by the magnetic coil510so that the surface of the substrate101is irradiated with the electrons. Simultaneously, positive ions in the ECR plasma are attracted to the side of the substrate101to neutralize negative charges by the electrons, i.e., weaken the electric field so that the formed layer is irradiated with the positive ions. During irradiation of the particles, some of the positive ions are bonded to the electrons to form neutral particles.

In the thin film formation apparatus shown inFIG. 5, the microwave supplied from the microwave generation unit (not shown) is temporarily branched by the waveguide508and connected to the vacuum waveguide506at the upper portion of the from the side of the plasma production chamber502through the quartz window507. With this structure, an adhesion of scattering particles from the target505to the quartz window507can be prevented, and the running time can largely be prolonged.

The properties of the Bi4Ti3O12film as the ferroelectric layer104formed by the ECR sputtering will be described next in more detail. The present inventors carefully and repeatedly observed Bi4Ti3O12film formation using ECR sputtering and found that the composition of the Bi4Ti3O12film to be formed can be controlled by the temperature and the flow rate of supplied oxygen. In this sputtering film formation, an oxide sintered body target (Bi4Ti3OX) whose composition ratio of bismuth and titanium is 4:3 is used.FIG. 6is a graph showing a change in deposition rate with respect to the flow rate of supplied oxygen when a Bi4Ti3O12film is formed by using ECR sputtering.FIG. 6shows a result when single-crystal silicon is used as the substrate, and the substrate temperature is set to 420° C.

As is apparent fromFIG. 6, there are a range corresponding to a low oxygen flow rate of 0 to 0.5 sccm, a range corresponding to an oxygen flow rate of 0.5 to 0.8 sccm, and a range corresponding to an oxygen flow rate of 0.8 sccm or more. For this characteristic, inductively coupled plasma (ICP) atomic emission spectrochemical analysis and section observation by a transmission electron microscope were executed to specifically examine formed films. As a result of examination, when the oxygen flow rate was as low as 0 to 0.5 sccm, a crystal film few Bi but mainly Ti—O was formed, although the Bi—Ti—O sintered target was used as the target205. This oxygen range will be defined as an oxygen range A.

When the oxygen flow rate was as low as 0.8 to 3 sccm, a film of microcrystal or column crystal with the stoichiometric composition of Bi4Ti3O12was formed. This oxygen range will be defined as an oxygen range C. When the oxygen flow rate was 3 sccm or more, a film with a large proportion of Bi was formed, and the composition deviated from the stoichiometric composition of Bi4Ti3O12. This oxygen range will be defined as an oxygen range D. When the oxygen flow rate was 0.5 to 0.8 sccm, a film with an intermediate characteristic between the oxygen range A and the oxygen range C was formed. This oxygen range will be defined as an oxygen range B.

It has not been known so far that the composition changes between the four ranges of the flow rate of supplied oxygen. This is a characteristic feature in forming a Bi4Ti3O12film by using a Bi—Ti—O sintered target by ECR sputtering. When film formation is controlled in consideration of these ranges, a film having a desired composition and quality can be obtained. It was also confirmed from another strict measurement result that the film formation condition to make an obtained film certainly exhibit ferroelectricity was the oxygen range C where the stoichiometric composition was realized.

The states of Bi4Ti3O12thin films formed under various oxygen flow rate conditions, i.e., α in the oxygen range A, β in the oxygen range B, and γ in the oxygen range C shown inFIG. 6will be described next with reference toFIGS. 7A to 7d.FIGS. 7A to 7dshow results obtained by observing the sections of the formed thin films with a transmission electron microscope.FIGS. 7A to 7Dare microphotographs, andFIGS. 7ato7dare schematic views showing the respective states. Under the condition α corresponding to an oxygen flow rate of 0, the entire film is formed from a column crystal, as shown inFIGS. 7A and 7a. When the composition of the elements of the thin film formed under the condition α is analyzed by EDS (Energy Dispersive X-ray Spectroscopy), this film is made of titanium oxide and contains no bismuth.

Under the condition β corresponding to an oxygen flow rate of 0.5 sccm, the formed thin film includes two layers, i.e., a metal oxide monolayer144containing titanium in an excessive amount relative to the stoichiometric composition of Bi4Ti3O12and the base layer141containing titanium in an excessive amount relative to the stoichiometric composition of Bi4Ti3O12, as shown inFIGS. 7B and 7b. The plurality of microcrystalline grains142of Bi4Ti3O12crystal with a grain size of about 3 to 15 nm are dispersed in the base layer141. The base layer141is amorphous.

Under the condition γ corresponding to an oxygen flow rate of 1 sccm, the microcrystalline grains142are dispersed in the base layer141, as shown inFIGS. 7C and 7c. Both the base layer141and the metal oxide monolayer144rarely contain bismuth. The microphotograph shown inFIG. 7Cindicates the same state as inFIG. 1B. The above-described states are obtained when the temperature in film formation is 420° C.FIGS. 7D and 7dshow an observation result of a film formed when the oxygen flow rate is 1 sccm but the temperature condition in film formation is different, as will be described later.

The properties of the Bi4Ti3O12film formed by ECR sputtering also depend on the film formation temperature.FIG. 8shows changes in deposition rate and refractive index with respect to the substrate temperature.FIG. 8shows changes in deposition rate and refractive index for the oxygen flow rates corresponding to the oxygen range A, oxygen range C and oxygen range D shown inFIG. 6. As shown inFIG. 8, both the deposition rate and refractive index change with respect to the temperature.

The refractive index behaves similarly in all the oxygen range A, oxygen range C, and oxygen range D. More specifically, in a low temperature range up to about 250° C., the refractive index is as small as about 2, and the characteristic of an amorphous state is indicated. In an intermediate temperature range from 300° C. to 600° C., the refractive index is about 2.6, i.e., close to a bulk reported in papers. It is apparent that crystallization of Bi4Ti3O12progresses. For further information about these numerical values, see, e.g., Yamaguchi et al., “Jpn. J. Appl. Phys.”, No. 37, p. 5166 (1988).

In a temperature range more than about 600° C., however, the refractive index is high, and the surface morphology (surface roughness) is large. It seems that the crystallinity changes. The temperature is lower than the Curie temperature (675° C.) of Bi4Ti3O12. However, if ECR plasma irradiation on the substrate surface during film formation supplies an energy to increase the substrate temperature and cause deterioration of crystallinity such as oxygen defects, the above-described result has no contradiction. As for the dependence of deposition rate on the temperature, the oxygen ranges exhibit a behavior with same tendency. More specifically, up to about 200° C., the deposition rate increases together with the temperature. However, in the range from about 200° C. to 300° C., the deposition rate abruptly decreases.

When the temperature reaches about 300° C., the deposition rate is constant up to 600° C. The deposition rate was about 1.5 nm/min in the oxygen range A, about 3 nm/min in the oxygen range C, and about 2.5 nm/min in the oxygen range D. From the above-described result, the temperature suitable for forming a Bi4Ti3O12crystal film falls in the range where the refractive index is close to the bulk, and the deposition rate is constant, i.e., 300° C. to 600° C.

The state of the ferroelectric layer104changes depending on the above-described temperature condition in film formation. When the film formation temperature is set as high as 450° C. under the oxygen flow rate condition to obtain the state shown inFIG. 7C, the microcrystalline grains142with a size of about 3 to 15 nm are observed in a plurality of column crystal portions143of Bi4Ti3O12column crystal with a size (grain size) of about 20 to 40 nm, as shown inFIGS. 7D and 7d. In this state, the column crystal portion143corresponds to the base layer141shown inFIGS. 7C and 7c. In all the films shown inFIG. 7, a peak of a (117) axis of Bi4Ti3O12is measured by XRD (X-Ray Diffraction). In the above-described observation by a transmission electron microscope, it was confirmed by electron diffraction of the microcrystalline grains142that they have the (117) plane of Bi4Ti3O12.

Generally, a material which exhibits ferroelectricity cannot maintain the crystallinity at the Curie temperature or more so no ferroelectricity appears. For example, the Curie temperature of a ferroelectric material such as Bi4Ti3O12containing Bi, Ti, and oxygen is about 675° C. For this reason, at a temperature of about 600° C. or more, the energy given from ECR plasma is also added, and oxygen defects are readily generated. Hence, the crystallinity deteriorates, and the ferroelectricity hardly appears.

It was found by X-ray diffusion analysis that the Bi4Ti3O12film formed at the oxygen flow rate C in the above-described temperature range (450° C.) is a (117)-oriented film. The Bi4Ti3O12film formed under these conditions has a thickness of about 100 nm, a sufficient breakdown voltage exceeding 2 MV/cm is obtained. As described above, when a Bi4Ti3O12film is formed in the range shown inFIG. 6or8by ECR sputtering, the composition and properties of the film can be controlled.

In the ferroelectric layer104, the state shown inFIG. 9is also observed. The ferroelectric layer104shown inFIG. 9has a layered structure including the metal oxide monolayer144containing titanium in an excessive amount relative to the stoichiometric composition of Bi4Ti3O12and the base layer141in which the plurality of microcrystalline grains142are dispersed. The state shown inFIG. 9is also confirmed by observation with a transmission electron microscope, like the states shown inFIGS. 1B and 7. The above-described states of the ferroelectric layer104change depending on the state of the underlayer on which the ferroelectric layer104is to be formed, the film formation temperature, and the oxygen flow rate in film formation. For example, when a film is formed on an underlayer made of a metal material at an oxygen flow rate corresponding to β shown inFIG. 8, the state shown inFIG. 7Bor9is obtained.

As described above, in the film formation condition range where microcrystalline grains are observed, the base layer has an amorphous state or contains a column crystal. In either case, the state of microcrystalline grains is the same, and the observed microcrystalline grains have a size of about 3 to 15 nm. The ferroelectric layer104in which microcrystalline grains are observed has two stable states, i.e., low resistance state and high resistance state. In a thin film with the state shown inFIGS. 7A and 7a, the two states are considerably poor.

According to the metal oxide thin film having the states shown inFIGS. 1B,7B to7d, and9, a ferroelectric element having a function of holding the state can be implemented, as described with reference toFIG. 2. When a film is formed by the above-described ECR sputtering, this characteristic is obtained by a film formed in the oxygen range B or C inFIG. 6. As for the film formation temperature condition shown inFIG. 8, a thin film having the above above-described characteristic can be formed in a temperature range where the deposition rate decreases and stabilizes, and the refractive index increases and stabilizes at about 2.6.

An oxide containing a binary metal, i.e., bismuth and titanium has been exemplified above. The characteristic to hold two states can be obtained by any other metal oxide thin film containing at least two metals and oxygen. The characteristic described with reference toFIG. 2can appear when a plurality of microcrystalline grains with a stoichiometric composition are dispersed in a layer which contains at least two metals and oxygen and in which the content of one metal is smaller in comparison with the stoichiometric composition.

For example, even a metal oxide thin film made of BaTiO3, Pb(Zr,Ti)O3, (Pb,La)(Zr,Ti)O3, LiNbO3, LiTaO3, PbNb3O6, PbNaNb5O15, Cd2Nb2O7, Pb2Nb2O7, (Bi,La)4Ti3O12, or SrBi2Ta2O9can obtain the same function and effect as in the above-described embodiment if a plurality of microcrystalline grains with a stoichiometric composition are dispersed in a layer in which the content of one metal is smaller in comparison with the stoichiometric composition. In addition, for an oxide containing a binary metal such as bismuth and titanium, when (La,Bi)TiO or (Sr,Bi)TiO is formed by doping lanthanum (La) or strontium (strontium) in the metal oxide thin film, the state of each resistance value can variably be controlled.

In the above-described example, each of the insulating layer on the silicon substrate, the lower electrode layer on the insulating layer, and the ferroelectric layer on the lower electrode layer is formed by ECR sputtering. However, the method of forming each layer is not limited to ECR sputtering. For example, the insulating layer to be formed on the silicon substrate may be formed by thermal oxidation or CVD (Chemical Vapor Deposition) or a conventional sputtering method.

The lower electrode layer may be formed by any other film formation method such as EB deposition, CVD, MBE, IBD, or hot deposition. The ferroelectric layer can also be formed by the above-described MOD, conventional sputtering method, or PLD. However, when ECR sputtering is used, flat and excellent insulating film, metal film, and ferroelectric film can easily be obtained.

The layers may be formed by a continuous process without unloading the structure into the atmospheric by using an apparatus which connects, through vacuum transfer chambers, the process chambers to realize ECR sputtering to form the respective layers. With this arrangement, the substrate to be processed can be transported in vacuum and is therefore prevented from being influenced by disturbance such as water adhesion. Hence, the film quality and interface properties can be improved.

Arraying elements and storing a plurality of data simultaneously in a memory is called “integration”. The degree of integrating elements is called a degree of integration. The structure shown inFIG. 1Ais very simple and can greatly increase the degree of integration as compared to a conventional memory cell. For DRAMs, SRAMs, or flash memories based on MOSFETs which must ensure gate, source, and drain regions, limitation on integration has been pointed out recently. However, the element shown inFIG. 1Auses the simple structure and can therefore increase the degree of integration without being affected by the current limitation on integration.

The basic idea of the present invention is sandwiching the ferroelectric layer104by two electrodes, as shown inFIG. 1A. With this structure, when a predetermined voltage (DC or pulse) is applied between the two electrodes to change the resistance value of the ferroelectric layer and switch the stable high resistance state and low resistance state, a memory function can be implemented consequently.

For example, as shown inFIG. 10A, an insulating substrate101amay be used, and stacked lower electrode layers103aand103bmay be used. As shown inFIG. 10B, the insulating substrate101amay be used, and a contact electrode103cmay be provided on the lower electrode layer103. As shown inFIG. 10C, the insulating substrate101amay be used, and stacked upper electrodes105aand105bmay be used. As shown inFIG. 10D, the stacked lower electrode layers103aand103band the stacked upper electrodes105aand105bmay be used.

As shown inFIG. 11A, an insulating substrate1101made of glass or quartz may be used. With this structure, the present invention can be applied to, e.g. a glass substrate easy to process. In this case, as shown inFIG. 11B, a through hole may be formed in the substrate1101to form a plug, and an electrical contact may be formed on the lower surface of the substrate1101(the side opposite to the surface where the lower electrode layer103is formed). Since the ferroelectric layer104which has a refractive index of about 2.6 measured at a wavelength of 632.8 nm is optically transparent, the structures shown inFIGS. 11A and 11Bcan be applied to a display. When the ferroelectric layer104is formed so thick in the range of 10 to 200 nm that an interference color is generated, the visual effect of a colored state can be obtained.

As shown inFIG. 11C, a conductive substrate1111made of, e.g., a metal may be used. As shown inFIG. 11D, a lower electrode1102contacting the substrate1111may be formed, and a ferroelectric layer1103and upper electrode1104may be provided on it. In the structure shown inFIG. 11D, a predetermined electrical signal can be applied between the substrate1111and the upper electrode1104.

As shown inFIG. 11E, a ferroelectric layer1112and upper electrode1113may be provided on a metal plate1121. In this structure, the metal plate1121serves as a lower electrode layer. With the structure shown inFIG. 11Ein which the constituent elements are formed on the metal plate1121with high thermal conductivity, a higher cooling effect can be obtained, and a stable element operation can be expected.

As the ferroelectric layer104,1103, or1112becomes thick, the current flows more hardly, and the resistance increases. When a memory is implemented by using a change in resistance value, the resistance value of in each of the low resistance state and high resistance state is important. For example, when the ferroelectric layer104,1103, or1112becomes thick, the resistance value in the low resistance state increases. Since it is difficult to ensure a high S/N ratio, the state of the memory is hard to determine. On the other hand, when the ferroelectric layer104,1103, or1112becomes thin, and the leakage current is dominant, memory information can hardly be held, and the resistance value in the high resistance state decreases. It is therefore difficult to ensure a high S/N ratio.

Hence, the ferroelectric layer104,1103, or1112preferably has an optimum thickness. For example, when the problem of leakage current is taken into consideration, the ferroelectric layer104,1103, or1112need only have a thickness of at least 10 nm. When the resistance value in the low resistance state is taken into consideration, the ferroelectric layer104,1103, or1112is preferably thinner than 300 nm. In experiments conducted by the present inventors, a memory operation was confirmed when the thickness of the ferroelectric layer104,1103, or1112was 30 to 200 nm.

In the above description, one ferroelectric element has been exemplified. However, a plurality of ferroelectric elements may be arrayed and integrated, as will be described later. For example, as shown inFIG. 12A, a common lower electrode layer602and ferroelectric layer603are formed on an insulating substrate601. A plurality of upper electrodes604spaced apart from each other by a predetermined distance are formed on the ferroelectric layer603. That is, a plurality of ferroelectric elements are arrayed in correspondence with the plurality of upper electrodes604. When the distance between the elements corresponding to the upper electrodes604is set in consideration of, e.g., the conductivity, a stable operation can be expected.

As shown inFIG. 12B, the common lower electrode layer602may be formed on the insulating substrate601, and a plurality of elements each including a ferroelectric layer613and upper electrode614may be arrayed on the lower electrode layer602. For example, when a metal oxide thin film is formed and processed by using a method such as RIE, ICP etching, or ECR etching, the individual ferroelectric layers613can be formed. When the elements are separated in this way, the distance between them can further be shortened, and the degree of integration can be made higher.

As shown inFIG. 12C, the side surface of the ferroelectric layer613of each element may be covered with an insulating sidewall615. As shown inFIG. 12D, the plurality of ferroelectric layers613may be formed in correspondence with the elements, and an insulating layer625may be formed to fill spaces on the sides of the plurality of ferroelectric layers613that are spaced apart from each other. When the portions between the plurality of ferroelectric layers613formed separately in correspondence with the elements are covered with an insulator, the leakage current between the elements can be reduced, and their stability can be increased.

As shown inFIG. 13, a plurality of elements according to the embodiment of the present invention are arrayed. More specifically, n elements are arrayed in the X direction, and m elements are arrayed in the Y direction. X-direction buses are connected to the lower electrode layers, and Y-direction buses are connected to the upper electrodes. A processor unit having a selection signal switching function is connected to each of the X- and Y-direction buses. With this structure, a memory capable of accessing each element at random can be implemented.

For example, as shown in the perspective view ofFIG. 14, elements each including a lower electrode801, ferroelectric layer802, and upper electrode803are arrayed. A Y-direction bus812is commonly connected to the lower electrodes801of each column, and an X-direction bus811is commonly connected to the lower electrodes803of each row. When a predetermined voltage is applied to the X-direction bus811and Y-direction bus812which cross in a selected element, as described above, data can be written or read out. In this structure, the memory cell can be formed by only the ferroelectric element with the above-described structure without using any memory cell select transistor. Hence, the degree of integration can be increased.

The change in resistance value of the ferroelectric layer104can also be controlled by a current. The value of a current which flows when a predetermined voltage is applied to the ferroelectric layer104to flow a predetermined current, and then, a voltage of +0.5 V is applied is observed. As shown inFIG. 15, a current value observed after a current of 1×10−5A is supplied to the ferroelectric layer104is almost 0 A. A current value observed after a current up to 1×10−4A is supplied to the ferroelectric layer104is about 0.02 A or less.

To the contrary, a current value observed after a current of 1×10−4A or more is supplied to the ferroelectric layer104abruptly changes to 0.7 A. As is apparent from this, the resistance of the ferroelectric layer104also changes depending on the current flowing to it. That is, two resistance values representing a high resistance state and low resistance state are present. Hence, the ferroelectric element shown inFIG. 1,10,11, or12can be driven by both a voltage and a current.

The resistance change in the ferroelectric layer104can also be controlled by a pulse voltage. For example, the value of a current which flows when a DC voltage of +0.3 V is applied to the above-described element in the early stage is measured, as shown inFIG. 16. A voltage or current is applied between the lower electrode layer103and the upper electrode105. Next, the value of a current which flows when a pulse voltage of −4 V having a width of 10 μs is applied between the upper electrode105and the lower electrode layer103once, and then a DC voltage of +0.3 V is applied is measured. The value of a current which flows when a pulse voltage of +5 V having a width of 10 μs is applied between the upper electrode105and the lower electrode layer103four times, and then a DC voltage of +0.3 V is applied is measured.

The value of a current which flows when a pulse voltage of −4 V having a width of 10 μs is applied between the upper electrode105and the lower electrode layer103once, and then a DC voltage of +0.3 V is applied is measured. Then, the value of a current which flows when a pulse voltage of +5 V having a width of 10 μs is applied between the upper electrode105and the lower electrode layer103four times, and a DC voltage of +0.3 V is applied is measured. These measurements are repeated a predetermined number of times. After that, the value of a current which flows when a pulse voltage of −4 V having a width of 1 μs is applied between the upper electrode105and the lower electrode layer10310 times, and then a DC voltage of +0.3 V is applied is measured. The value of a current which flows when a pulse voltage of +5 V having a width of 1 μs is applied between the upper electrode105and the lower electrode layer103100 times, and then a DC voltage of +0.3 V is applied is measured. Finally, the value of a current which flows when a pulse voltage of −3 V having a width of 100 μs is applied between the upper electrode105and the lower electrode layer103100 times, and then a DC voltage of +0.3 V is applied is measured.

The current value measured after the above-described pulse voltage application changes as shown inFIG. 17. As shown inFIG. 17, in the initial state, a high resistance state representing a current value of 10−5A or less is obtained. When a pulse voltage of −4 V having a width of 10 μs is applied once, the state changes to a low resistance state representing a current value of 10−5A or more. In addition, when a pulse voltage of +5 V having a width of 10 μs is applied four times in this state, the high resistance state representing a current value of 10−5A or less is obtained. This indicates that the resistance value of the ferroelectric layer104changes when a positive voltage pulse or negative voltage pulse is applied. Hence, for example, when a positive voltage pulse or negative voltage pulse is applied, a memory operation can be executed so that the memory state of the element changes from an “on” state to an “off” state or from an “off” state to an “on” state.

The voltage and time of the voltage pulse capable of changing the resistance state of the ferroelectric layer104can be changed in accordance with the situation. For example, when a voltage pulse of +5 V having a width of 10 as is applied four times to set the high resistance state, and a short pulse of −4 V having a width of 1 μs is applied 10 times, the state can be changed to the low resistance state. When a short pulse of +5 V having a width of 1 μs is applied 100 times in this state, the state can be changed to the high resistance state. When a low voltage pulse of −3 V having a width of 100 μs is applied 100 times in this state, the state can be changed to the low resistance state.

According to the ferroelectric element shown inFIG. 1, a multilevel memory operation is also possible. For example, in the current-voltage characteristic when a DC voltage is applied between the upper electrode105and the lower electrode layer103, when the positive-side applied voltage is changed, the low resistance state changes to a different low resistance state, as shown inFIG. 18. InFIG. 18, the current value at the read voltage shown inFIG. 18changes between the low resistance state after a voltage up to 0.5 V is applied, the low resistance state after a voltage up to 1.0 V is applied, and the low resistance state after a voltage up to 1.5 V is applied. A memory which can have three states (three values) “0”, “1”, and “2” in correspondence with the current values at the read voltage in the respective states can be implemented.

According to the element shown inFIG. 1, a multilevel memory can be implemented by the difference in pulse voltage value. As shown inFIG. 19, every time a predetermined pulse voltage with a predetermined pulse width is applied a predetermined number of times, the current value is read out at a read voltage of −0.2 V at a point indicated by a triangle. Then, as shown inFIG. 20, three states (three values) “0”, “1”, and “2” are obtained. In this example, the memory is reset by the state “2”.

Other metal materials usable for each electrode of the element shown inFIG. 1will be described next. A case wherein the lower electrode layer103which the ferroelectric layer104contacts in the ferroelectric element shown inFIG. 1is made of platinum will be described first. In this case, the lower electrode layer103is a multilayered film formed by stacking ruthenium and platinum in this order from the side of the insulating layer102. The lower electrode layer103may be a multilayered film formed by stacking titanium and platinum in this order from the side of the insulating layer102. When a ruthenium or titanium layer is provided on the side of the insulating layer102, the adhesion to the insulating layer102increases.

The ferroelectric element in which the ferroelectric layer104is formed in contact with the lower electrode layer103made of platinum has a current-voltage characteristic shown inFIG. 21.FIG. 21shows the hysteresis characteristics of the values of currents which flow in the ferroelectric layer104when the voltage applied to the upper electrode105is increased from 0 in the positive direction, returned to 0, decreased in the negative direction, and finally returned to 0 again. When the voltage applied to the upper electrode105is gradually increased from 0 V in the positive direction, the positive current flowing in the ferroelectric layer104is relatively small (high resistance state).

When the voltage exceeds 1 V, the positive current value starts abruptly increasing. After the voltage is increased up to about 1.6 V, the positive voltage is decreased to a voltage value of about 0.5 or less. Then, the current value starts decreasing (low resistance state). At this time, the positive current readily flows as compared to the above-described high resistance state. The current value is about 50 μA at 0.2 V. When the applied voltage is returned to 0, the current value also becomes 0.

Next, a negative voltage is applied to the upper electrode105. In this state, when the negative voltage is low, a relatively large negative current flows according to the previous hysteresis. When the applied negative voltage is changed up to about −0.3 V, the negative current suddenly starts decreasing. When the applied negative voltage is changed up to about −0.4 V, the negative current value continuously decreases and returns to 0. After that, even when the voltage applied to the upper electrode105is changed up to about −0.1 V and then to 0 V, the current rarely flows.

As described above, even when the lower electrode layer103made of platinum is used, the ferroelectric layer104has the two stable states, i.e., low resistance state and high resistance state. Each state remains unless the above-described positive or negative voltage with a predetermined magnitude or more is applied. Hence, even when the lower electrode layer103of the ferroelectric element shown inFIG. 1is made of platinum, a nonvolatile functional element capable of a nondestructive read operation can be implemented by the ferroelectric element shown inFIG. 1.

A case wherein the lower electrode layer103which the ferroelectric layer104contacts in the ferroelectric element shown inFIG. 1is made of titanium nitride will be described next. In this case, the lower electrode layer103is formed from a titanium nitride monolayer film. The ferroelectric element in which the ferroelectric layer104is formed in contact with the lower electrode layer103made of titanium nitride has a current-voltage characteristic shown inFIG. 22.

When the lower electrode layer103is made of titanium nitride, and the positive voltage applied to the upper electrode105is swept from 0 V to VW0, the high resistance state is held, as indicated by filled circles inFIG. 22. When the positive voltage applied to the upper electrode105is increased to VW1higher than VW0, the state changes to the low resistance state indicated by open circles inFIG. 22. When the voltage VW0is applied to the upper electrode105, the state changes to the high resistance state.

As described above, even when the lower electrode layer103made of titanium nitride is used, the ferroelectric layer104has the two stable states, i.e., low resistance state and high resistance state. Each state remains unless the above-described positive or negative voltage with a predetermined magnitude or more is applied. Hence, even when the lower electrode layer103of the ferroelectric element shown inFIG. 1is made of titanium nitride, a nonvolatile functional element capable of a nondestructive read operation can be implemented by the ferroelectric element shown inFIG. 1.

A case wherein the lower electrode layer103formed on the insulating substrate1101made of quartz in the ferroelectric element shown inFIG. 11is made of ruthenium, and the upper electrode105is made of titanium nitride will be described. When the upper electrode105made of titanium nitride is formed on the ferroelectric layer104, a current-voltage characteristic shown inFIG. 23is obtained, which exhibits the same tendency as inFIG. 21. Hence, even when the upper electrode105is made of titanium nitride, the ferroelectric layer104has the two stable states, i.e., low resistance state and high resistance state. Each state remains unless the above-described positive or negative voltage with a predetermined magnitude or more is applied.

Hence, even when the upper electrode105of the ferroelectric element shown inFIG. 11Ais made of titanium nitride, a nonvolatile functional element capable of a nondestructive read operation can be implemented by the ferroelectric element shown inFIG. 11A. Even in the ferroelectric element with the above-described structure, each state is held for a long time, as is apparent fromFIG. 24.

Generally, a Bi4Ti3O12crystal is a bismuth layer-structured ferroelectric having a pseudo-perovskite structure. When the film thickness is decreased to 40 nm or less, no clear ferroelectricity is observed because a large leakage current flows, as is known. Even in the ferroelectric layer (metal oxide thin film) of this embodiment, which is made of Bi4Ti3O12and has the structure shown inFIG. 1B, when the film thickness is 40 nm or less, a large current flows (measured value), and no clear ferroelectricity is observed. To the contrary, when the thickness of the metal oxide thin film exceeds 40 nm, the flowing current (measured value) becomes small in a state immediately after film formation, and ferroelectricity is slightly observed.

When the leakage current (measured value) is so small that ferroelectricity is observed, the metal oxide thin film of the ferroelectric layer104shown inFIG. 1exhibits a current-voltage characteristic shown inFIG. 25A. The state shown inFIG. 25Awill be described. When a positive DC voltage is applied in the initial state wherein the voltage is 0 V at 0 A, a positive current starts flowing. The value of the flowing current moderately increases first. When a voltage of +4 V or more is applied, the current value becomes large. A current of +2.5 nA flows at +5.3 V.

The applied voltage is sequentially decreased from this state. Unlike the current-voltage characteristic from the initial value, the characteristic shows a tendency not to flow the current. This is because since the voltage is swept and decreased, the amount of charges stored between capacitors decreases over time, and this decrease appears as a negative displacement current. Hence, the leakage current measured here equals a value obtained by adding the above-described displacement current to the leakage current actually flowing in the film. For example, when the voltage is decreased up to +4 V, a current of only about +0.1 nA flows, unlike when the voltage is increased (+1 nA). When the applied voltage is decreased to 0 V, a current of −0.5 nA flows.

When a negative voltage is applied further, for example, a negative current of about −2.3 nA flows at −4 V, and a negative current of about −2.8 nA flows at −5.3 V. When the negative voltage is swept in the positive direction to make it closer to 0, a displacement current opposite to the previous case flows. Since the above-described positive displacement current is observed as a leakage current in addition to the leakage current actually flowing through the film, a current-voltage characteristic different from that observed when the voltage is swept in the negative direction is obtained. For example, a current of only about −0.5 nA flows at −4 V. Even when the applied voltage is set to 0 V, a positive current of +1 nA flows.

As described above, when the leakage current is small, the behavior of the displacement current is dominant. For this reason, a change in current-voltage characteristic caused by the difference in voltage sweep direction (increase or decrease in voltage) is conspicuously observed. However, such a phenomenon occurs because the time-rate change in charge amount between capacitors appears as a positive or negative displacement current which changes depending on the sweep direction. Hence, the phenomenon disappears when the voltage sweep is slowed down. For example, when the current-voltage characteristic is measured at different sweep rates in the same element as described above, the characteristic changes, as shown inFIG. 25B. As is apparent fromFIG. 25B, when the sweep rate is low, the current-voltage characteristic largely changes due to the difference in sweep direction. When quasi-static sweep is executed by further decreasing the sweep rate, the same current-voltage characteristic is obtained independently of the sweep direction, and only the characteristic of the leakage current actually flowing in the film is observed.

The phenomenon similar to the hysteresis of the current-voltage characteristic shown inFIG. 25Ais observed only because the positive or negative displacement current which changes depending on voltage sweep is superimposed on the leakage current actually flowing in the film. This phenomenon occurs independently of the change in resistance of the element (the change in value of the leakage current actually flowing in the film) and can be observed in dielectric capacitors including general ferroelectrics. Such a change in current-voltage characteristic cannot be used as a memory operation in principle, as a matter of course.

As is generally known, an insulating film or ferroelectric film with a high breakdown voltage causes dielectric breakdown upon application of a high voltage more than 5 V. For example, a case wherein a high voltage is applied to a ferroelectric thin film made of a ferroelectric with a high breakdown voltage and having a thickness of, e.g., 200 nm or more will be described below. As shown inFIG. 26, even when the applied voltage is increased up to +15 V, only a very small current of about 10−9A flows. However, when a higher voltage is applied, the current abruptly flows to cause dielectric breakdown (breakdown) so that the thin film itself is damaged. From then, a large current always flows in the thin film that has caused dielectric breakdown so no state with two or more resistance values can be obtained.

Contrary to the above-described characteristic of ferroelectrics, the “metal oxide thin film (ferroelectric layer104) formed by dispersing the plurality of microcrystalline grains of Bi4Ti3O12with a grain size of about 3 to 15 nm in the base layer containing titanium in an excessive amount relative to the stoichiometric composition of Bi4Ti3O12” as shown inFIGS. 1B,7and9exhibits a current-voltage characteristic shown inFIG. 27when the thickness is about 40 nm. In the initial stage after the ferroelectric layer104is formed by ECR sputtering, and the element shown inFIG. 4Dis formed, as described with reference toFIGS. 4A to 4Dand5, the element exhibits a high breakdown voltage so that only a very small current of about 10−9A flows even when a voltage up to 14 V is applied.

When a voltage more than 15 V is applied, the current abruptly flows, like the characteristic shown inFIG. 26. When a negative voltage is applied to the ferroelectric layer104after the high voltage is applied to readily flow the current, a current of about −10−2A flows. However, if the applied negative voltage is about −2 V, a high resistance state without flowing a current is abruptly set. When a positive voltage is applied from this state, a current-voltage characteristic in a positive high resistance state is obtained. The current value abruptly increases at about +2.5 V to set a positive high resistance state. This is the same as the characteristic shown inFIG. 21.

As described above, when a high voltage of about +15 V is applied to the ferroelectric layer104with a thickness of about 40 nm or more in the film formation initial state with a high breakdown voltage, a characteristic current-voltage characteristic as shown inFIG. 2is obtained. The initial process for changing the film formation initial state to a state to exhibit a resistance change characteristic will be referred to as an EO (Electrical Orientation) process. When the metal oxide thin film according to this embodiment, which is formed thick and ensures a high breakdown voltage, undergoes the EO process, the above-described characteristic is obtained, and a ferroelectric element can be implemented.

In the above-described EO process, a voltage more than 10 V is applied to the element. For this reason, when elements shown inFIG. 1are formed in integration with semiconductor elements and subjected to the EO process, the semiconductor elements may be broken. To suppress this, the EO process may be done by using ECR plasma. In, e.g., an ECR plasma apparatus, a plasma flow can be generated by a divergent magnetic field, and a substrate to be processed can be irradiated with the plasma flow with an energy of 20 to 30 eV. In a section perpendicular to the plasma flow divergent direction, the plasma flow has an energy distribution from the center to the periphery because the distribution of the magnetic field is reflected.

This energy distribution can be controlled between several eV and several ten eV by the degree of divergence of the divergent magnetic field so that a potential difference from several V to several ten V can be generated between the center and the periphery. Hence, when one end of the interconnection connected to the lower electrode layer103of the element shown inFIG. 1is exposed to the peripheral portion of the plasma flow, and the upper electrode105is exposed to the central portion of the plasma flow, a voltage necessary for the EO process can be applied between the two electrodes by the potential difference generated from the distribution in the plasma flow. For example, when the element is irradiated with a plasma mainly containing Ar, the EO process can be done in a short time of 1 sec to several ten sec.

When a plasma is used as described above, a plurality of elements can be subjected to the EO process, as shown inFIG. 28.FIG. 28shows a state wherein a device on which a plurality of elements are integrated by the plurality of upper electrodes604on the common ferroelectric layer603shown inFIG. 12Ais irradiated with an ECR plasma flow to execute the EO process. When the potential difference generated from the distribution of the ECR plasma flow is controlled to a value exceeding the potential difference necessary for the EO process of the plurality of elements, the plurality of elements integrated on the device can undergo the EO process.

The voltage value to switch (change) the resistance value of the ferroelectric layer104can be controlled by changing the voltage application time, as shown inFIG. 29.FIG. 29is an explanatory view showing a change in resistance value of the element when a voltage of +1 V is applied to the element which moderately changes to the low resistance state at +1.6 V. Referring toFIG. 29, the abscissa represents the voltage application time, and the ordinate represents the resistance value of the element. When a normal operation voltage of 1.6 V is applied, the element can be changed to the low resistance state in a short time tL1(about 150 ms). Even when a voltage of 1 V slightly lower than the normal operation voltage is applied, the element can be changed to the low resistance state by prolonging the application time to tL2(about 3.7 sec). As described above, when operation voltage is changed by controlling the voltage application time, the element can be driven as a memory.

A multilevel operation can be implemented in the following way. A multilevel memory (ternary) operation will be described below with reference toFIG. 30.FIG. 30shows a time-rate change in resistance value of the element when a predetermined voltage (e.g., 1.2 V) is applied between the upper electrode and the lower electrode layer. For example, when the time of continuously applying a predetermined voltage between the upper electrode and the lower electrode layer is changed, two low resistance states can be obtained. As shown inFIG. 30, when a voltage is applied for t1sec (e.g., 250 ms) from the high resistance state, the state can be changed to a low resistance state 1 (data “1”). When the voltage is applied for a longer time t2, the state can be changed to a low resistance state 2 (data “2”). The state can be changed to the high resistance state (data “0”) at about −1.2 V to reset the element. A ternary memory can be implemented by changing the voltage application time from the reset state to t1and t2.

Another embodiment of the present invention will be described below with reference to the accompanying drawings.FIG. 31is a sectional view schematically showing a structure example of a bistable resistance value acquisition device according to another embodiment of the present invention. Application to a ferroelectric element which uses a metal oxide layer (ferroelectric layer3104) exhibiting ferroelectric properties will be described below. The element shown inFIG. 31comprises, on a substrate3101made of, e.g., single-crystal silicon, an insulating layer3102, a lower electrode layer3103, the ferroelectric layer3104, an insulating layer3105, and an upper electrode3106. The substrate3101can be made of any one of a semiconductor, insulator, and conductive material such as a metal. When the substrate3101is made of an insulating material, the insulating layer3102can be omitted. When the substrate3101is made of a conductive material, the insulating layer3102and lower electrode layer3103can be omitted. In this case, the substrate3101made of the conductive material serves as a lower electrode.

The lower electrode layer3103and upper electrode3106need only be made of a transition metal including noble metals such as platinum (Pt), ruthenium (Ru), gold (Au), and silver (Ag). The lower electrode layer3103and upper electrode3106may be made of a compound such as a nitride, oxide, or fluoride of a transition metal, such as titanium nitride (TiN), hafnium nitride (HfN), strontium ruthenate (SrRuO2), zinc oxide (ZnO), indium tin oxide (ITO), or lanthanum fluoride (LaF3), or a composite film formed by stacking them.

The insulating layer3105need only be made of silicon dioxide, silicon oxynitride, alumina, an oxide such as LiNbO3containing a light metal such as lithium, beryllium, magnesium, or calcium, or a fluoride such as LiCaAlF6, LiSrAlF6, LiYF4, LiLuF4, or KMgF3. Alternatively, the insulating layer3105need only be made of an oxide or nitride of a transition metal such as scandium, titanium, strontium, yttrium, zirconium, hafnium, tantalum, or lanthanum series, a silicate (ternary compound of a metal, silicon, and oxygen) containing the above-described elements, an aluminate (ternary compound of a metal, aluminum, and oxygen) containing these elements, or an oxide or nitride containing at least two of the above elements.

The ferroelectric layer3104is made of, e.g., an oxide ferroelectric, like the above-described ferroelectric layer104. The ferroelectric layer3104is made of a material such as an oxide, nitride, or fluoride which contains at least two metals and generally exhibits ferroelectric properties. A state wherein no ferroelectric properties are exhibited depending on the film thickness condition is also included, as described above.

A detailed example of the ferroelectric element shown inFIG. 31will be described. For example, the lower electrode layer3103is a ruthenium film having a thickness of 10 nm. The ferroelectric layer3104is a Bi4Ti3O12film having a thickness of 40 nm. The insulating layer3105is a multilayered film made of tantalum pentoxide and silicon dioxide and having a thickness of 5 nm. The upper electrode3106is made of gold. The upper electrode3106may have a multilayered structure formed by stacking a titanium layer, titanium nitride layer, and gold layer in this order sequentially from the side of the insulating layer3105. When the contact surface to the insulating layer3105is formed from a titanium layer, the adhesion can be increased. As described above, the structures of the substrate3101and insulating layer3102are not limited to those described above, and any other material can also be selected appropriately if it has no effect on the electrical characteristics.

A detailed method of forming the above-described insulating layer3102, lower electrode layer3103, ferroelectric layer3104, insulating layer3105, and upper electrode3106will be described later. They can be formed by sputtering a metal target or sintered target in ECR plasma made of argon gas, oxygen gas, or nitrogen gas by using an ECR sputtering apparatus shown inFIG. 5, as inFIG. 1A.

An example of a method of manufacturing the ferroelectric element shown inFIG. 31will be described next with reference toFIGS. 32A to 32E. As shown inFIG. 32A, the p-type silicon substrate3101having a plane orientation of (100) on the principal plane and a resistivity of 1 to 2 Ωcm is prepared. The surface of the substrate3101is cleaned by a solution mixture of sulfuric acid and a hydrogen peroxide solution, pure water, and a hydrogen fluoride solution and dried.

The insulating layer3102is formed on the cleaned and dried substrate3101. In forming the insulating layer3102, the ECR sputtering apparatus shown inFIG. 5is used. The substrate3101is fixed on a substrate holder504in a process chamber501. Pure silicon (Si) is used as a target505. The insulating layer3102in a metal mode by Si—O molecules is formed on the substrate3101to a thickness to just cover its surface by ECR sputtering using argon (Ar) as a plasma gas and oxygen gas.

In ECR sputtering shown inFIG. 5, a plasma production chamber502is evacuated to a high vacuum state on the order of 10−5Pa. For example, Ar gas as a rare gas is supplied at a flow rate of about 20 sccm from an inert gas supply unit511into the plasma production chamber502to set the internal pressure of the plasma production chamber502on the order of, e.g., 10−2to 10−3Pa. A coil current of, e.g., 28 A is supplied to a magnetic coil510to give the magnetic field of the electron cyclotron resonance condition to the plasma production chamber502. The magnetic flux density in the plasma production chamber502is set to, e.g., about 87.5 mT (tesla).

A microwave of, e.g., 2.45 GHz (e.g., 500 W) is supplied from a microwave generation unit (not shown) into the plasma production chamber502through a waveguide508, quartz window507, and vacuum waveguide506. With this supply of the microwave, Ar plasma is produced in the plasma production chamber502. Note that sccm is the unit of flow rate and indicates that a fluid at 0° C. and 1 atmospheric pressure flows 1 cm3in 1 min.

The plasma produced by the above-described method is output from the plasma production chamber502to the side of the process chamber501by the divergent magnetic field of the magnetic coil510. In addition, a high-frequency power (e.g., 13.56 MHz or 500 W) is supplied from a high-frequency power supply522to the target505placed at the outlet of the plasma production chamber502. When Ar particles collide against the target505, a sputtering phenomenon occurs to sputter Si particles from the target505.

After this state is obtained, a shutter (not shown) between the process chamber501and the substrate3101is opened. The Si particles sputtered from the target505reach the surface of the substrate3101together with the plasma output from the plasma production chamber502and the oxygen gas which is supplied from a reactive gas supply unit512and activated by the plasma and are oxidized to silicon dioxide by the activated oxygen.

With the above process, the insulating layer3102made of silicon dioxide and having a thickness of, e.g., about 100 nm can be formed on the substrate3101(FIG. 32A). When the insulating layer is formed to a predetermined thickness, the above-described shutter is closed not to make the sputtered material reach the substrate3101, thereby stopping film formation. After that, plasma irradiation is stopped by, e.g., stopping supplying the microwave power. Supply of the gases is stopped. When the substrate temperature decreases to a predetermined value, and the internal pressure of the process chamber501is increased to the atmospheric pressure, the substrate3101which has undergone film formation is unloaded from the process chamber501.

The insulating layer3102ensures insulation to prevent a voltage from leaking to the substrate3101and influencing desired electrical characteristics when a voltage is applied between the lower electrode layer3103and upper electrode3106to be formed later. For example, a silicon oxide film formed by oxidizing the surface of the silicon substrate by thermal oxidation may be used as the insulating layer3102. The insulating layer3102may be made of any other insulating material except silicon oxide if the insulating properties can be ensured. The thickness of the insulating layer3102need not always be 100 nm and may be smaller or larger. In the above-described formation of the insulating layer3102by ECR sputtering, the substrate3101is not heated. However, the film may be formed while heating the substrate3101.

After the insulating layer3102is formed in the above-described manner, the substrate3101is unloaded from the apparatus to the atmosphere. The substrate3101is fixed on the substrate holder504of the same ECR sputtering apparatus as inFIG. 5in which pure ruthenium (Ru) is used as the target505. ECR sputtering using argon (Ar) as a plasma gas and xenon (Xe) is executed to form an Ru film on the insulating layer3102to a thickness to just cover its surface, thereby forming the lower electrode layer3103, as shown inFIG. 32B.

Formation of the Ru film will be described in detail. In the ECR sputtering apparatus shown inFIG. 5, the substrate3101is heated to, e.g., about 400° C. Next, Ar gas as a rare gas is supplied at a flow rate of, e.g., 7 sccm from the inert gas supply unit511into the plasma production chamber502, and Xe gas is supplied at a flow rate of, e.g., 5 sccm to set the internal pressure of the plasma production chamber502on the order of, e.g., 10−2to 10−3Pa. A coil current of, e.g., 26 A is supplied to the magnetic coil510to give the magnetic field of the electron cyclotron resonance condition to the plasma production chamber502.

A microwave of, e.g., 2.45 GHz (e.g., 500 W) is supplied from the microwave generation unit (not shown) into the plasma production chamber502through the waveguide508, quartz window507, and vacuum waveguide506. With this supply of the microwave, a plasma of Ar and Xe is produced in the plasma production chamber502. The produced plasma is output from the plasma production chamber502to the side of the process chamber501by the divergent magnetic field of the magnetic coil510. In addition, a high-frequency power (e.g., 500 W) is supplied from the high-frequency electrode supply unit to the target505placed at the outlet of the plasma production chamber502. When Ar particles collide against the target505, a sputtering phenomenon occurs to sputter Ru particles from the target505. The Ru particles sputtered from the target505reach the surface of the insulating layer3102on the substrate3101and are deposited.

With the above process, the lower electrode layer3103having a thickness of, e.g., about 10 nm can be formed on the insulating layer3102(FIG. 32B). The lower electrode layer3103enables voltage application to the ferroelectric layer3104and insulating layer3105when a voltage is applied between the lower electrode layer3103and the upper electrode3106to be formed later. The lower electrode layer3103may be made of any other material except ruthenium if the conductivity can be ensured. The thickness of the lower electrode layer3103need not always be 10 nm and may be smaller or larger.

As described above, in forming the Ru film by ECR sputtering, the substrate3101is heated to 400° C. However, the substrate need not always be heated. However, if the substrate is not heated, the adhesion of ruthenium to silicon dioxide becomes low, and the film may peel off. To prevent peeling, the film is formed preferably while heating the substrate. After Ru is deposited to a desired thickness in the above-described way, an end process is executed by stopping film formation by, e.g., closing the shutter and stopping plasma irradiation by stopping supply of the microwave power. Then, the substrate3101can be unloaded.

After the lower electrode layer3103is formed in the above-described manner, the substrate3101is unloaded from the apparatus to the atmosphere. The substrate3101is fixed on the substrate holder504of the same ECR sputtering apparatus as inFIG. 5in which a sintered body (Bi—Ti—O) with an Bi—Ti ratio of 4:3 is used as the target505. ECR sputtering using argon (Ar) as a plasma gas and oxygen gas is executed to form the ferroelectric layer3104on the lower electrode layer3103to a thickness to just cover its surface, as shown inFIG. 32C.

Formation of the ferroelectric layer3104will be described in detail. In the ECR sputtering apparatus shown inFIG. 5in which the target505made of Bi—Ti—O is used, the substrate3101is heated to, e.g., 300° C. to 700° C. Next, Ar gas as a rare gas is supplied at a flow rate of, e.g., 20 sccm from the inert gas supply unit511into the plasma production chamber502, and O2gas serving as a reactive gas is supplied at a flow rate of, e.g., 1 sccm to set the pressure on the order of, e.g., 10−2to 10−3Pa. A coil current of, e.g., 27 A is supplied to the magnetic coil510to give the magnetic field of the electron cyclotron resonance condition to the plasma production chamber502.

A microwave of, e.g., 2.45 GHz (e.g., 500 W) is supplied from the microwave generation unit (not shown) into the plasma production chamber502through the waveguide508, quartz window507, and vacuum waveguide506. With this supply of the microwave, an Ar plasma is produced in the plasma production chamber502. The produced ECR plasma is output from the plasma production chamber502to the side of the process chamber501by the divergent magnetic field of the magnetic coil510. In addition, a high-frequency power (e.g., 500 W) is supplied from the high-frequency electrode supply unit to the target505placed at the outlet of the plasma production chamber502. When Ar particles collide against the target505, a sputtering phenomenon occurs to sputter Bi particles and Ti particles from the target505.

The Bi particles and Ti particles sputtered from the target505reach the surface of the lower electrode layer3103together with the plasma output from the plasma production chamber502and the oxygen gas which is supplied from the reactive gas supply unit512and activated by the plasma and are oxidized by the activated oxygen. Although the target505is a sintered body and contains oxygen, any shortage of oxygen in the film can be prevented by supplying oxygen.

With the above-described film formation by ECR sputtering, the ferroelectric layer3104having a thickness of, e.g., about 40 nm can be formed (FIG. 32C). After that, the same end process as described above is executed to make it possible to unload the substrate. The film quality may be improved by irradiating the formed ferroelectric layer3104with ECR plasma of an inert gas and a reactive gas. As the reactive gas, not oxygen gas but nitrogen gas, fluorine gas, or hydrogen gas can be used. The film quality improvement can also be applied to formation of the insulating layer3102or formation of the insulating layer3105to be described later.

After the ferroelectric layer3104is formed in the above-described manner, the substrate3101is unloaded from the apparatus to the atmosphere. The substrate3101is fixed on the substrate holder504of the same ECR sputtering apparatus as inFIG. 5in which pure tantalum (Ta) is used as the target505. The insulating layer3105is formed on the ferroelectric layer3104to a thickness to just cover its surface, as shown inFIG. 32D, by ECR sputtering using argon (Ar) as a plasma gas and oxygen gas. A metal mode film by Ta—O molecules is formed as the insulating layer3105, as will be described below.

Formation of a metal mode film by Ta—O molecules will be described in detail. In the ECR sputtering apparatus shown inFIG. 5in which the target505made of tantalum is used, Ar gas as a rare gas is supplied at a flow rate of, e.g., 25 sccm from the inert gas supply unit511into the plasma production chamber502to set the internal pressure of the plasma production chamber502on the order of, e.g., 10−3Pa. A coil current of, e.g., 28 A is supplied to the magnetic coil510to give the magnetic field of the electron cyclotron resonance condition to the plasma production chamber502.

A microwave of, e.g., 2.45 GHz (e.g., 500 W) is supplied from the microwave generation unit (not shown) into the plasma production chamber502through the waveguide508, quartz window507, and vacuum waveguide506. With this supply of the microwave, Ar plasma is produced in the plasma production chamber502. The produced plasma is output from the plasma production chamber502to the side of the process chamber501by the divergent magnetic field of the magnetic coil510. In addition, a high-frequency power (e.g., 500 W) is supplied from the high-frequency electrode supply unit to the target505placed at the outlet of the plasma production chamber502.

When Ar particles collide against the target505, a sputtering phenomenon occurs to sputter Ta particles from the target505. The Ta particles sputtered from the target505reach the surface of the ferroelectric layer3104on the substrate3101together with the plasma output from the plasma production chamber502and the oxygen gas which is supplied from the reactive gas supply unit512and activated by the plasma and are oxidized to tantalum pentoxide by the activated oxygen.

With the above process, a tantalum pentoxide film is formed on the ferroelectric layer3104. Subsequently, a silicon dioxide film is formed on the tantalum pentoxide film by ECR sputtering using the target505made of pure silicon, like silicon dioxide deposition described with reference toFIG. 32A. The above-described formation of a tantalum pentoxide film and silicon dioxide film is repeated to form a multilayered film including the tantalum pentoxide films and silicon dioxide films to, e.g., about 5 nm, thereby obtaining the insulating layer3105(FIG. 32D).

The insulating layer3105including the tantalum pentoxide films and silicon dioxide films is used to control the voltage to be applied to the ferroelectric film upon voltage application to the ferroelectric layer3104. The insulating layer3105may have any other structure except the multilayered structure of tantalum pentoxide films and silicon dioxide films if it can control the voltage applied to the ferroelectric layer3104. The insulating layer3105may be a single layer. The thickness is not limited to 5 nm, either. In the above-described ECR sputtering, the substrate3101is not heated but may be heated.

When the upper electrode3106made of Au and having a predetermined area is formed on the insulating layer3105, as shown inFIG. 32E, an element using a layer formed from a ferroelectric can be obtained. The upper electrode3106can be formed by a well-known lift-off method and gold deposition by resistance heating vacuum deposition. The upper electrode3106may be made of another metal material or conductive material such as Ru, Pt, or TiN. When Pt is used, the adhesion is poor, and the film may peel off. Hence, the upper electrode3106must be formed as an electrode with a predetermined area by executing film formation by heating or using a structure such as Ti—Pt—Au that hardly peels off and executing a patterning process such as photolithography or lift-off on that structure.

As described above, when a high-quality Bi4Ti3O12film formed by, e.g., ECR sputtering is thinned to about 50 nm or less, the ferroelectricity tends to be small. In addition, when the Bi4Ti3O12film is made so thick as to flow a certain leakage current, a unique hysteresis appears in the measured current-voltage characteristic. Based on these findings, when these phenomena are notably used, an element to hold two states can be implemented by the element shown inFIG. 31, like the element shown inFIG. 1A.

The characteristics of the ferroelectric element shown inFIG. 31will be described next. The characteristics were investigated by applying a voltage between the lower electrode layer3103and the upper electrode3106. When a voltage from a power supply was applied between the lower electrode layer3103and the upper electrode3106, and a current flowing when the voltage was applied was measured by an ammeter, a result shown inFIG. 33was obtained. The memory operation principle of the present invention will be described below with reference toFIG. 33. The voltage values and current values to be described here are mere examples measured in an actual element. Hence, the phenomenon is not limited to the following numerical values. Other numerical values can also be measured depending on the material and thickness of each film actually used in the element and other conditions.

When a negative voltage is applied to the upper electrode3106, the flowing current is very small up to −0.8 V, as indicated by (1) inFIG. 33. However, as indicated by (2), when the voltage exceeds −0.8 V, a negative current flows abruptly. Actually, a current larger than −15 μA also flows. However, since flowing of a larger current is inhibited to protect the measurement device, the current is not measured. In the range from 0 V to −0.8 V indicated by (1), a high resistance state is held (maintained) by inhibiting flowing of a large current as indicated by (2).

When a negative voltage is applied again to the upper electrode3106, a locus to flow a negative current of −10 μA or more is obtained at −0.5 V, as indicated by (3). When the negative voltage is further applied to the upper electrode3106, a current of −10 μA or more flows at about −0.5 V, as indicated by (3). When a positive voltage is applied to the upper electrode3106, a positive current flows up to about +0.2 V, as indicated by (4). The current increases to 3 μA at maximum. When the absolute value of the voltage is decreased, the current traces a locus indicated by (4).

When the positive voltage is applied up to 0.2 V, the current traces the locus indicated by (4). After that, as indicated by (5), the value of the flowing current decreases, and no positive current flows. When the positive voltage is further applied to the upper electrode3106, a locus to rarely flow a current is obtained, as indicated by (6). Even when the absolute value of the voltage is decreased then, the current rarely flows, as indicated by (6). When a negative voltage is applied to the upper electrode3106, the current rarely flows up to about 0 to −0.8 V, as indicated by (1). Hence, the high resistance state wherein no current flows as in (1) is maintained unless a voltage of −0.8 V or more is applied to the upper electrode3106to prevent any sudden current flow as in (2). The state (1) will be referred to as a “negative high resistance mode”.

For example, as indicated by (2), when a voltage of −0.8 V or more is applied to abruptly flow a current, a low resistance state in which the current readily flows is obtained, as indicated by (3). This state is also maintained while a negative voltage is applied to the upper electrode3106. The state (3) will be referred to as a “negative low resistance mode”.

However, when a positive voltage is applied to the upper electrode3106, a low resistance state in which the current flows in a positive voltage range from 0 to 0.2 V is obtained, as indicated by (4). This state is also maintained while a positive voltage in the range of 0 to 0.2 V is applied. The state (4) will be referred to as a “positive low resistance mode”.

When a positive voltage of 0.2 V or more is applied, no current flows, and the state changes to a high resistance state, as indicated by (5). In this state, the state wherein the current value has a high resistance is maintained while a positive voltage in the range of 0 to 2 V is applied, as indicated by (6). The state (6) will be referred to as a “positive high resistance mode”.

As described above, the element using a ferroelectric layer shown inFIG. 31apparently has four stable modes: “positive high resistance mode”, “positive low resistance mode”, “negative high resistance mode”, and “negative low resistance mode”. More specifically, the “positive high resistance mode” and “negative high resistance mode” are “high resistance modes” which exhibit the same high resistance state. The “positive low resistance mode” and “negative low resistance mode” are “low resistance modes” which exhibit the same low resistance state. That is, two modes are present. In the state of the “high resistance mode”, the “high resistance mode” is maintained in the voltage range of −0.8 V to +0.8 V. When a voltage of −0.8 V or more is applied to change the state to the “low resistance mode”, the “low resistance mode” is maintained in the voltage range of −0.5 V to +2.0 V. Switching between the two, “high resistance mode” and “low resistance mode” occurs. This also applied to the negative resistance modes, i.e., “negative high resistance mode” and “negative low resistance mode”.

As for the actual current value in each “negative mode” when a voltage of −0.5 V is applied, the current value in the “negative high resistance mode” is −5×10−8A, and that in the “negative low resistance mode” is −1×10−5A. The ratio is as high as 200 times. This facilitates each mode identification. The present inventors estimate that the above-described phenomenon occurs when the resistance value of the ferroelectric film dramatically changes depending on the direction and magnitude of the applied voltage.

Since the insulating layer3105is provided between the ferroelectric layer3104and the upper electrode3106, carriers can be controlled by the band structure of the insulating layer3105. More specifically, for example, tantalum pentoxide has a band gap of about 4.5 eV. The energy difference viewed from the Fermi level is about 1.2 eV in the conduction band and 2.3 eV in the valence band. That is, the barrier is higher on the valence band side. Hence, the barrier effect is high for holes in the valence band but low for electrons in the conduction band. For further information, see Wilk et al., “J. Appl. Phys.”, No. 87, p. 484 (2000).

From the above-described characteristic, when, e.g., a tantalum pentoxide film is used as the insulating layer between the electrode and the ferroelectric layer, a phenomenon that electrons readily flow but holes hardly flow can be expected. Actually, as shown inFIG. 33, the value of the flowing current largely changes between a case wherein a positive voltage is applied to the upper electrode3106and a case wherein a negative voltage is applied. In discriminating a memory, this has a large effect to increase the signal-to-noise ratio (S/N ratio) and facilitate data discrimination. This is the effect of use of the insulating layer3105.

It was found that when the above-described “low resistance mode” and “high resistance mode” shown inFIG. 33are applied as a memory operation, the element shown inFIG. 31can be used as a nonvolatile nondestructive memory. More specifically, initialization of the element and data erase, i.e., the write of data “off” is done by changing the mode from the “low resistance mode” to the “high resistance mode” by applying a negative voltage of the upper electrode3106, as indicated by (4) or (5) inFIG. 33.

The write of data “on” is done by abruptly flowing a current by applying a negative voltage of −0.8 V or more to the upper electrode3106, as indicated by (2) inFIG. 33. With this operation, the mode is changed from the “high resistance mode” to the “low resistance mode”, and data “on” is written. As described above, when a voltage is applied to the upper electrode3106to set the “high resistance mode” or “low resistance mode”, “off” or “on” data (state) can be written.

The read of data written in the above-described way can easily be done by reading a current value when an appropriate voltage of −0.8 V to +0.8 V is applied to the upper electrode3106. For example, when the mode state of the element shown inFIG. 31is “off”, i.e., “high resistance mode”, it can be determined because a current hardly flows when an appropriate voltage of −0.8 V to +0.8 V is applied, as indicated by (1) inFIG. 33.

When the mode state of the element shown inFIG. 31is “on”, i.e., “low resistance mode”, it can be determined because a current abruptly flows when an appropriate voltage of −0.5 V to +0.2 V is applied, as indicated by (2) inFIG. 33. Since the difference in current value between the “negative high resistance mode” and the “negative low resistance mode”, i.e., “off” and “on” is 200 times or more, “off” and “on” can easily be determined. Even in the positive voltage range, “off” and “on” can be determined in the voltage range of 0 to +0.2 V.

The above-described read operation of the memory can easily be done only by checking whether the element shown inFIG. 31is in the “high resistance mode” or “low resistance mode”. In other words, while the element shown inFIG. 31can hold the two modes, data is held. Even when a positive voltage is applied to the electrode to check the mode, the held mode does not change, and data is not destroyed. Hence, according to the ferroelectric element shown inFIG. 31, nondestructive read is possible. The element shown inFIG. 31functions as a nonvolatile memory element since the resistance value of the ferroelectric layer3105changes depending on the voltage applied between the lower electrode layer3103and the upper electrode3106. This element can also be used as a switching element to control the current.

The voltage to operate the element shown inFIG. 31is maximized in the write to set the “negative low resistance mode”. However, the voltage is about −0.8 V, and the power consumption is very low, as shown inFIG. 33. The low power consumption is very advantageous for devices. Devices using a memory, e.g., not only mobile communication devices, digital general-purpose devices, digital image sensing devices, notebook personal computers, and PDAs (Personal Digital Appliances) but also all computers, personal computers, workstations, office computers, mainframes, communication units, and multifunction apparatuses can reduce the power consumption.

FIG. 34shows the data holding time of the element shown inFIG. 31. After a positive voltage is applied to the upper electrode3106to set the “positive high resistance state” shown inFIG. 33, i.e., “high resistance mode”, a voltage of −0.8 V or more is applied to the upper electrode3106to set the “negative low resistance state” (“low resistance mode”), i.e., data “on” written state. A voltage of −0.3 V is applied to the upper electrode3106every predetermined time, and the value of a current flowing upon voltage application is measured.FIG. 34shows the observation result.

The measured current is maximized about 10 min after and then moderately decreases up to 1,000 min. However, since the current value at this time is 86% of the maximum value, the data can be discriminated without any problem. As is predicted from the extrapolated line of 10,000,000 min corresponding to 10 years shown inFIG. 34, the current value after 10 years corresponding to 66% (⅔) of the maximum value, and the data can discriminated. As is apparent from the above description, the memory using the element shown inFIG. 31has a data holding period of 10 years.

In the above-described example of the present invention, each of the insulating layer on the silicon substrate, the lower electrode layer on the insulating layer, and the ferroelectric layer on the lower electrode layer is formed by ECR sputtering. However, the method of forming each layer is not limited to ECR sputtering. For example, the insulating layer to be formed on the silicon substrate may be formed by thermal oxidation or CVD (Chemical Vapor Deposition) or a conventional sputtering method.

The lower electrode layer may be formed by any other film formation method such as EB deposition, CVD, MBE, or IBD. The ferroelectric layer can also be formed by the above-described MOD, conventional sputtering method, or PLD. However, when ECR sputtering is used, flat and excellent insulating film, metal film, and ferroelectric film can easily be obtained.

In the above-described embodiment, after each layer is formed, the substrate is temporarily unloaded into the atmosphere. However, the layers may be formed by a continuous process without unloading the structure into the atmospheric by using an apparatus which connects, through vacuum transfer chambers, the process chambers to realize ECR sputtering to form the respective layers. With this arrangement, the substrate to be processed can be transported in vacuum and is therefore prevented from being influenced by disturbance such as water adhesion. Hence, the film quality and interface properties can be improved.

As shown in Japanese Patent Laid-Open No. 2003-77911, after each layer is formed, the surface of the formed layer may be irradiated with ECR plasma to improve the properties. After each layer is formed, the formed layer may be annealed (heat-treated) in an appropriate gas atmosphere such as hydrogen atmosphere to greatly improve the properties of each layer.

Arraying elements and storing a plurality of data simultaneously in a memory is called “integration”. The degree of integrating elements is called a degree of integration. The structure shown inFIG. 31is very simple and can greatly increase the degree of integration as compared to a conventional memory cell. For DRAMs, SRAMs, or flash memories based on MOSFETs which must ensure gate, source, and drain regions, limitation on integration has been pointed out recently. However, the element shown inFIG. 31uses the simple structure and can therefore increase the degree of integration without being affected by the current limitation on integration.

In the above-described embodiment, a DC voltage is applied. However, even when a pulse voltage having an appropriate width and magnitude is applied, the same effect as described above can be obtained. The basic idea of the present invention is arranging an insulating layer in contact with the ferroelectric layer and sandwiching these layers by two electrodes, as shown inFIG. 31. With this structure, when a predetermined voltage (DC or pulse) is applied between the two electrodes to change the resistance value of the ferroelectric layer and switch the stable high resistance mode and low resistance mode, a memory function can be implemented consequently.

For example, as shown inFIG. 35A, an insulating substrate3101amay be used, and stacked lower electrode layers3103aand3103bmay be used. As shown inFIG. 35B, the insulating substrate3101amay be used, and a contact electrode3103cmay be provided on the lower electrode layer3103. As shown inFIG. 35C, the insulating substrate3101amay be used, and stacked upper electrodes3106aand3106bmay be used. As shown inFIG. 35D, the stacked lower electrode layers3103aand3103band the stacked upper electrodes3106aand3106bmay be used.

As shown inFIG. 36A, an insulating substrate3601made of glass or quartz may be used. In this case, as shown inFIG. 37, a through hole may be formed in the substrate3601to form a plug, and an electrical contact may be formed on the lower surface of the substrate3601(the side opposite to the surface where the lower electrode layer3103is formed). With this structure, the present invention can be applied to, e.g. a glass substrate easy to process. When an optically transparent substrate is used, the structure can be applied to a display.

As shown inFIG. 38A, a conductive substrate3801made of, e.g., a metal may be used. As shown inFIG. 38B, a lower electrode layer3802contacting the substrate3801may be formed, and a ferroelectric layer3803, insulating layer3804, and upper electrode3805may be provided on it. In the structure shown inFIG. 38B, a predetermined electrical signal can be applied between the substrate3801and the upper electrode3805.

As shown inFIG. 38C, a ferroelectric layer3902, insulating layer1203, and upper electrode3904may be provided on a metal plate3901. In this structure, the metal plate3901serves as a lower electrode layer. With the structure shown inFIG. 38Cin which the constituent elements are formed on the metal plate3901with high thermal conductivity, a higher cooling effect can be obtained, and a stable element operation can be expected.

As the ferroelectric layer becomes thick, the current flows more hardly, and the resistance increases. When a memory is implemented by using a change in resistance value, the resistance value of in each of the ON state and OFF state is important. For example, when the ferroelectric layer becomes thick, the resistance value in the ON state increases. Since it is difficult to ensure a high S/N ratio, the state of the memory is hard to determine. On the other hand, when the ferroelectric layer becomes thin, and the leakage current is dominant, memory information can hardly be held, and the resistance value in the OFF state increases. It is therefore difficult to ensure a high S/N ratio.

Hence, the ferroelectric layer preferably has an optimum thickness. For example, when the problem of leakage current is taken into consideration, the ferroelectric layer need only have a thickness of at least 10 nm. When the resistance value in the ON state is taken into consideration, the ferroelectric layer is preferably thinner than 200 nm. In experiments conducted by the present inventors, a memory operation was confirmed when the thickness of the ferroelectric layer was 30 to 100 nm. The most satisfactory state was obtained when the thickness of the ferroelectric layer was 50 nm.

A more preferable thickness is present even in the insulating layer on the ferroelectric layer. The thickness will be described by using an example in which an Al2O3film, SiO2film, and Ta2O3film are formed on silicon substrates by ECR sputtering using an Al target, Si target, and Ta target. Each film is formed to a predetermined thickness. An upper electrode made of Al is formed on each film. A current-voltage characteristic is measured by applying a voltage between the silicon substrate and the upper electrode. The current density observed in each thin film at −1 V is observed.FIG. 39shows the result of the current densities.

As shown inFIG. 39, the current density changes depending on the material of the insulating layer. The smaller the thickness becomes, the more the leakage current flows to increase the current density. On the other hand, when the thickness increases, the current density decreases. This indicates that if the thickness of too small, the characteristic of an insulating layer cannot be obtained. If the thickness is large, the voltage applied to the ferroelectric film is small so it is difficult to ensure a high S/N ratio, and the memory state is hard to determine. Hence, the insulating layer preferably has an optimum thickness in combination with the ferroelectric layer.

For example, when the problem of leakage current is taken into consideration, and an Al2O3film or SiO2film is used, the thickness is preferably about 1 to 3 nm. A Ta2O3film need only have a thickness of at least 3 nm. When the problem of magnitude of the resistance value is taken into consideration, the insulating layer is preferably thicker than 20 nm. In experiments conducted by the present inventors, the above-described memory operation was confirmed when an insulating layer made of SiO2and Ta2O3had a thickness of 3 to 5 nm.

In the above description, one ferroelectric element has been exemplified. However, a plurality of ferroelectric elements may be arrayed and integrated, as will be described later. For example, as shown inFIG. 40A, a common lower electrode layer4002, ferroelectric layer4003, and insulating layer4004are formed on an insulating substrate4001. A plurality of upper electrodes4005spaced apart from each other by a predetermined distance are formed on the insulating layer4004. That is, a plurality of ferroelectric elements are arrayed in correspondence with the plurality of upper electrodes4005.

A ferroelectric or insulating film has a much lower conductivity than a conductor such as a metal and can therefore be used commonly. In this case, since the working process can be omitted, the productivity can be increased, resulting in large advantage from the industrial viewpoint. When the distance between the ferroelectric elements corresponding to the plurality of upper electrodes4005is set in consideration of, e.g., the conductivity, a stable operation can be expected.

As shown inFIG. 40B, the common lower electrode layer4002may be formed on the insulating substrate4001, and a plurality of elements each including a ferroelectric layer4013, insulating layer4014, and upper electrode4015may be arrayed on the lower electrode layer4002. For example, when a ferroelectric film is formed and processed by using a method such as RIE, ICP etching, or ECR etching, the individual ferroelectric layers4013can be formed. When the elements are separated in this way, the distance between them can further be shortened, and the degree of integration can be made higher.

As shown inFIG. 40C, the side surfaces of the ferroelectric layer4013and insulating layer4014of each element may be covered with an insulating sidewall4016. As shown inFIG. 40D, an insulating layer4024common to the elements may be formed to cover the side surface of the ferroelectric layer4013. In this case, the insulating layer4014shown inFIG. 40Bis formed by part of the insulating layer4024.

As shown inFIG. 40(e), the plurality of ferroelectric layers4013may be formed in correspondence with the elements, the common insulating layer4014may be formed, and an insulating layer4026may be formed to fill spaces on the sides of the plurality of ferroelectric layers4013that are spaced apart from each other. When the portions between the plurality of ferroelectric layers4013formed separately in correspondence with the elements are covered with an insulator, the leakage current between the ferroelectric elements can be reduced, and their stability can be increased.

Even in the element shown inFIG. 31, as shown inFIG. 13, a plurality of elements are arrayed. More specifically, n elements are arrayed in the X direction, and m elements are arrayed in the Y direction. X-direction buses are connected to the lower electrode layers, and Y-direction buses are connected to the upper electrodes. A processor unit having a selection signal switching function is connected to each of the X- and Y-direction buses. With this structure, a memory capable of accessing each element at random can be implemented.

The change in resistance value of the ferroelectric layer3104can also be controlled by a current. A predetermined voltage is applied to the ferroelectric layer3104to flow a predetermined current. Immediately after that, a predetermined voltage (e.g., −0.8 V) is applied between the upper electrode3106and the lower electrode layer3103. The current value then changes as shown inFIG. 41. The ordinate inFIG. 41represents the current measured when a current detection voltage is applied between the electrodes.

For example, after a current from 1×10−9A (inclusive) to 1×10−6A (exclusive) is supplied between the electrodes, the current value is small, and a high resistance state is obtained. After a current of 1×10−6A or more is supplied between the electrodes, the value of the flowing current becomes large (e.g., 10 μA), and the state changes to a low resistance state. As is apparent from this, the resistance of the ferroelectric layer3104also changes depending on the current flowing to it. That is, two resistance values representing a high resistance state and low resistance state are present. Hence, the element shown inFIG. 31can be driven by both a voltage and a current.

The resistance change in the ferroelectric layer3104can also be controlled by a pulse voltage. For example, as shown inFIG. 42, a negative pulse voltage (e.g., −4 V and 10 μs) is applied once between the upper electrode3106and the lower electrode layer3103of the element shown inFIG. 31whose ferroelectric layer3104is in the high resistance state in the initial state. Then, the state changes to the low resistance state. After that, when a positive pulse voltage (e.g., +5 V and 10 μs) is applied between the electrodes a plurality of number of times (e.g., four times), the state changes to the high resistance state.

The above-described pulse voltage application is repeated. The current measured after each pulse voltage application changes as shown inFIG. 43. As shown inFIG. 43, the high resistance state is set in the initial state. After a negative pulse voltage is applied, the state changes to the low resistance state. When a positive pulse voltage is applied in this state a plurality of number of times, the state changes to the high resistance state. The resistance value of the ferroelectric layer3104changes when a positive voltage pulse or negative voltage pulse is applied. Hence, for example, when a positive voltage pulse or negative voltage pulse is applied, a memory operation can be executed so that the memory state of the element changes from an “on” state to an “off” state or from an “off” state to an “on” state.

The voltage and time of the voltage pulse capable of changing the resistance state of the ferroelectric layer3104can be changed in accordance with the situation. For example, when a voltage pulse of +5 V having a width of 10 μs is applied four times to set the high resistance state, and a short pulse of −4 V having a width of 1 μs is applied 10 times, the state can be changed to the low resistance state. When a short pulse of +5 V having a width of 1 μs is applied 100 times in this state, the state can be changed to the high resistance state. When a low voltage pulse of −3 V having a width of 100 μs is applied 100 times in this state, the state can be changed to the low resistance state.

A case wherein the element shown inFIG. 31is used as a switching element to control a current will be described next. In an element shown inFIG. 44A, the current flowing between the upper electrode3106and the lower electrode layer3103is set in an OFF state when the ferroelectric layer3104is in the high resistance state or in an ON state when the ferroelectric layer3104is in the low resistance state, as shown inFIG. 44B. For example, as shown in the sequence ofFIG. 45, when a negative pulse and positive pulse are alternately applied between the upper electrode3106and the lower electrode layer3103, the ON state and OFF state of the current flowing between the upper electrode3106and the lower electrode layer3103can alternately be switched.

According to the element shown inFIG. 31which uses the ferroelectric layer3104of this embodiment, the current-voltage characteristic when a DC voltage is applied between the lower electrode layer3103and the upper electrode3106is changed to different low resistance states by changing the positive-side applied voltage, as shown inFIG. 46. These correspond to the current values at the read voltage in the respective states. Hence, a memory with three states (three values) can be implemented. For example, when the read voltage is about 0.5 V, a ternary memory can be implemented. Before change to each state, a voltage of −2 V is applied to the lower electrode layer3103to return the state to the high resistance state (reset).

Even in the element shown inFIG. 31, when a high voltage of about +15 V is applied, a characteristic current-voltage characteristic as shown inFIG. 33is obtained, as in the element shown inFIG. 1. Even in the element shown inFIG. 31, with the EO (Electrical Orientation) process, the above-described characteristic is obtained, and a memory element can be implemented.

In the above-described EO process, a voltage more than 10 V is applied to the element. For this reason, when a plurality of elements are formed in integration with semiconductor elements as shown inFIG. 40and subjected to the EO process, the semiconductor elements may be broken. Even in this case, to suppress destruction of the semiconductor elements, the EO process may be done by using ECR plasma, as described above. For example, when one end of the interconnection connected to the lower electrode layer4002of the element shown inFIG. 15is exposed to the peripheral portion of the plasma flow, and the upper electrode4005is exposed to the central portion of the plasma flow, a voltage necessary for the EO process can be applied between the two electrodes by the potential difference generated from the distribution in the plasma flow. For example, when the element is irradiated with a plasma mainly containing Ar, the EO process can be done in a short time of 1 sec to several ten sec.

Still another embodiment of the present invention will be described below with reference to the accompanying drawings.FIG. 47is a sectional view schematically showing a structure example of a bistable resistance value acquisition device according to another embodiment of the present invention. A ferroelectric element including a ferroelectric layer4705made of a metal oxide exhibiting ferroelectric properties will be described below. The element shown inFIG. 47comprises, on a substrate4701made of, e.g., single-crystal silicon, an insulating layer4702, a lower electrode layer4703, an insulating layer4704, the ferroelectric layer4705, and an upper electrode4706. The substrate4701can be made of any one of a semiconductor, insulator, and conductive material such as a metal. When the substrate4701is made of an insulating material, the insulating layer4702can be omitted. When the substrate4701is made of a conductive material, the insulating layer4702and lower electrode layer4703can be omitted. In this case, the substrate4701made of the conductive material serves as a lower electrode.

The lower electrode layer4703and upper electrode4706need only be made of a transition metal including noble metals such as platinum (Pt), ruthenium (Ru), gold (Au), and silver (Ag). The lower electrode layer4703and upper electrode4706may be made of a compound such as a nitride, oxide, or fluoride of a transition metal, such as titanium nitride (TiN), hafnium nitride (HfN), strontium ruthenate (SrRuO2), zinc oxide (ZnO), indium tin oxide (ITO), or lanthanum fluoride (LaF3), or a composite film formed by stacking them.

The insulating layer4704need only be made of silicon dioxide, silicon oxynitride, alumina, an oxide such as LiNbO3containing a light metal such as lithium, beryllium, magnesium, or calcium, or a fluoride such as LiCaAlF6, LiSrAlF6, LiYF4, LiLuF4, or KMgF3. Alternatively, the insulating layer4704need only be made of an oxide or nitride of a transition metal such as scandium, titanium, strontium, yttrium, zirconium, hafnium, tantalum, or lanthanum series, a silicate (ternary compound of a metal, silicon, and oxygen) containing the above-described elements, an aluminate (ternary compound of a metal, aluminum, and oxygen) containing these elements, or an oxide or nitride containing at least two of the above elements.

The ferroelectric layer4705is the same as the above-described ferroelectric layer104and ferroelectric layer3104. The ferroelectric layer4705is made of a material such as a metal oxide which contains at least two metals and generally exhibits ferroelectric properties. A state wherein no ferroelectric properties are exhibited depending on the film thickness condition is also included, as described above.

A detailed example of the element shown inFIG. 47will be described. For example, the lower electrode layer4703is a ruthenium film having a thickness of 10 nm. The insulating layer4704is a multilayered film made of tantalum pentoxide and silicon dioxide and having a thickness of about 5 nm. The ferroelectric layer4705is a Bi4Ti3O12film having a thickness of 40 nm. The upper electrode4706is made of gold. As described above, the structures of the substrate4701and insulating layer4702are not limited to those described above, and any other material can also be selected appropriately if it has no effect on the electrical characteristics.

A detailed method of forming the above-described insulating layer4702, lower electrode layer4703, insulating layer4704, ferroelectric layer4705, and upper electrode4706will be described later. They can be formed by sputtering a metal target or sintered target in ECR plasma made of argon gas, oxygen gas, or nitrogen gas by using an ECR sputtering apparatus shown inFIG. 5.

An example of a method of manufacturing the element shown inFIG. 47will be described next with reference toFIG. 48. As shown inFIG. 48A, the p-type silicon substrate4701having a plane orientation of (100) on the principal plane and a resistivity of 1 to 2 Ωcm is prepared. The surface of the substrate4701is cleaned by a solution mixture of sulfuric acid and a hydrogen peroxide solution, pure water, and a hydrogen fluoride solution and dried.

The insulating layer4702is formed on the cleaned and dried substrate4701. In forming the insulating layer4702, the above-described ECR sputtering apparatus is used. The substrate4701is fixed on a substrate holder504in a process chamber501. Pure silicon (Si) is used as a target505. The insulating layer4702in a metal mode by Si—O molecules is formed on the substrate4701to a thickness to just cover its surface by ECR sputtering using argon (Ar) as a plasma gas and oxygen gas.

In ECR sputtering shown inFIG. 5, a plasma production chamber502is evacuated to a high vacuum state on the order of 10−5Pa. For example, Ar gas as a rare gas is supplied at a flow rate of about 20 sccm from an inert gas supply unit511into the plasma production chamber502to set the internal pressure of the plasma production chamber502to on the order of, e.g., 10−2to 10−3Pa. A coil current of, e.g., 28 A is supplied to a magnetic coil510to give the magnetic field of the electron cyclotron resonance condition to the plasma production chamber502. The magnetic flux density in the plasma production chamber502is set to, e.g., about 87.5 mT (tesla).

A microwave of, e.g., 2.45 GHz (e.g., 500 W) is supplied from a microwave generation unit (not shown) into the plasma production chamber502through a waveguide508, quartz window507, and vacuum waveguide506. With this supply of the microwave, Ar plasma is produced in the plasma production chamber502. Note that sccm is the unit of flow rate and indicates that a fluid at 0° C. and 1 atmospheric pressure flows 1 cm3in 1 min.

The plasma produced by the above-described method is output from the plasma production chamber502to the side of the process chamber501by the divergent magnetic field of the magnetic coil510. In addition, a high-frequency power (e.g., 500 W) is supplied from a high-frequency power supply522to the target505placed at the outlet of the plasma production chamber502. When Ar particles collide against the target505, a sputtering phenomenon occurs to sputter Si particles from the target505.

After this state is obtained, a shutter (not shown) between the process chamber501and the substrate4701is opened. The Si particles sputtered from the target505reach the surface of the substrate4701together with the plasma output from the plasma production chamber502and the oxygen gas which is supplied from a reactive gas supply unit512and activated by the plasma and are oxidized to silicon dioxide by the activated oxygen.

With the above process, the insulating layer4702made of silicon dioxide and having a thickness of, e.g., about 100 nm can be formed on the substrate4701(FIG. 48A). When the insulating layer is formed to a predetermined thickness, the above-described shutter is closed not to make the sputtered material reach the substrate4701, thereby stopping film formation. After that, plasma irradiation is stopped by, e.g., stopping supplying the microwave power. Supply of the gases is stopped. When the substrate temperature decreases to a predetermined value, and the internal pressure of the process chamber501is increased to the atmospheric pressure, the substrate4701which has undergone film formation is unloaded from the process chamber501.

The insulating layer4702ensures insulation to prevent a voltage from leaking to the substrate4701and influencing desired electrical characteristics when a voltage is applied between the lower electrode layer4703and upper electrode4706to be formed later. For example, a silicon oxide film formed by oxidizing the surface of the silicon substrate by thermal oxidation may be used as the insulating layer4702. The insulating layer4702may be made of any other insulating material except silicon oxide if the insulating properties can be ensured. The thickness of the insulating layer4702need not always be 100 nm and may be smaller or larger. In the above-described formation of the insulating layer4702by ECR sputtering, the substrate4701is not heated. However, the film may be formed while heating the substrate4701.

After the insulating layer4702is formed in the above-described manner, the substrate4701is unloaded from the apparatus to the atmosphere. The substrate4701is fixed on the substrate holder504of the same ECR sputtering apparatus as inFIG. 5in which pure ruthenium (Ru) is used as the target505. ECR sputtering using argon (Ar) as a plasma gas and xenon (Xe) is executed to form an Ru film on the insulating layer4702to a thickness to just cover its surface, thereby forming the lower electrode layer4703, as shown inFIG. 48B.

Formation of the Ru film will be described in detail. In the ECR sputtering apparatus shown inFIG. 5, the substrate4701is heated to, e.g., about 400° C. Next, Ar gas as a rare gas is supplied at a flow rate of, e.g., 7 sccm from the inert gas supply unit511into the plasma production chamber502, and Xe gas is supplied at a flow rate of, e.g., 5 sccm to set the internal pressure of the plasma production chamber502to on the order of, e.g., 10−2to 10−3Pa. A coil current of, e.g., 26 A is supplied to the magnetic coil510to give the magnetic field of the electron cyclotron resonance condition to the plasma production chamber502.

A microwave of, e.g., 2.45 GHz (e.g., 500 W) is supplied from the microwave generation unit (not shown) into the plasma production chamber502through the waveguide508, quartz window507, and vacuum waveguide506. With this supply of the microwave, a plasma of Ar and Xe is produced in the plasma production chamber502. The produced plasma is output from the plasma production chamber502to the side of the process chamber501by the divergent magnetic field of the magnetic coil510. In addition, a high-frequency power (e.g., 500 W) is supplied from the high-frequency electrode supply unit to the target505placed at the outlet of the plasma production chamber502. When Ar particles collide against the target505, a sputtering phenomenon occurs to sputter Ru particles from the target505. The Ru particles sputtered from the target505reach the surface of the insulating layer4702on the substrate4701and are deposited.

With the above process, the lower electrode layer4703having a thickness of, e.g., about 10 nm can be formed on the insulating layer4702(FIG. 48B). The lower electrode layer4703enables voltage application to the ferroelectric layer4705and insulating layer4704when a voltage is applied between the lower electrode layer4703and the upper electrode4706to be formed later. The lower electrode layer4703may be made of any other material except ruthenium if the conductivity can be ensured. The thickness of the lower electrode layer4703need not always be 10 nm and may be smaller or larger.

As described above, in forming the Ru film by ECR sputtering, the substrate4701is heated to 400° C. However, the substrate need not always be heated. However, if the substrate is not heated, the adhesion of ruthenium to silicon dioxide becomes low, and the film may peel off. To prevent peeling, the film is formed preferably while heating the substrate. After Ru is deposited to a desired thickness in the above-described way, an end process is executed by stopping film formation by, e.g., closing the shutter and stopping plasma irradiation by stopping supply of the microwave power. Then, the substrate4701can be unloaded.

After the lower electrode layer4703is formed in the above-described manner, the substrate4701is unloaded from the apparatus to the atmosphere. The substrate4701is fixed on the substrate holder504of the same ECR sputtering apparatus as inFIG. 5in which pure tantalum (Ta) is used as the target505. The insulating layer4704is formed on the lower electrode layer4703to a thickness to just cover its surface, as shown inFIG. 48C, by ECR sputtering using argon (Ar) as a plasma gas and oxygen gas. A metal mode film by Ta—O molecules is formed as the insulating layer4704, as will be described below.

Formation of a metal mode film by Ta—O molecules will be described in detail. In the ECR sputtering apparatus shown inFIG. 5in which the target505made of tantalum is used, Ar gas as a rare gas is supplied at a flow rate of, e.g., 25 sccm from the inert gas supply unit511into the plasma production chamber502to set the internal pressure of the plasma production chamber502on the order of, e.g., 10−2to 10−3Pa. A coil current of, e.g., 27 A is supplied to the magnetic coil510to give the magnetic field of the electron cyclotron resonance condition to the plasma production chamber502.

A microwave of, e.g., 2.45 GHz (e.g., 500 W) is supplied from the microwave generation unit (not shown) into the plasma production chamber502through the waveguide508, quartz window507, and vacuum waveguide506. With this supply of the microwave, Ar plasma is produced in the plasma production chamber502. The produced plasma is output from the plasma production chamber502to the side of the process chamber501by the divergent magnetic field of the magnetic coil510. In addition, a high-frequency power (e.g., 500 W) is supplied from the high-frequency electrode supply unit to the target505placed at the outlet of the plasma production chamber502. When Ar particles collide against the target505, a sputtering phenomenon occurs to sputter Ta particles from the target505.

The Ta particles sputtered from the target505reach the surface of the lower electrode layer4703on the substrate4701together with the plasma output from the plasma production chamber502and the oxygen gas which is supplied from the reactive gas supply unit512and activated by the plasma and are oxidized to tantalum pentoxide by the activated oxygen.

With the above process, a tantalum pentoxide film is formed on the lower electrode layer4703. Subsequently, a silicon dioxide film is formed on the tantalum pentoxide film by ECR sputtering using the target505made of pure silicon, like silicon dioxide deposition described with reference toFIG. 48A. The above-described formation of a tantalum pentoxide film and silicon dioxide film is repeated to form a multilayered film including the tantalum pentoxide films and silicon dioxide films to, e.g., about 5 nm, thereby obtaining the insulating layer4704(FIG. 48D).

The insulating layer4704including the tantalum pentoxide films and silicon dioxide films is used to control the voltage to be applied to the ferroelectric film upon voltage application to the ferroelectric layer4705. The insulating layer4704may have any other structure except the multilayered structure of tantalum pentoxide films and silicon dioxide films if it can control the voltage applied to the ferroelectric layer4705. The insulating layer4704may be a single layer. The thickness is not limited to 5 nm, either. In the above-described ECR sputtering, the substrate4701is not heated but may be heated.

After the insulating layer4704is formed in the above-described manner, the substrate4701is unloaded from the apparatus to the atmosphere. The substrate4701is fixed on the substrate holder504of the same ECR sputtering apparatus as inFIG. 5in which a sintered body (Bi—Ti—O) with an Bi—Ti ratio of 4:3 is used as the target505. ECR sputtering using argon (Ar) as a plasma gas and oxygen gas is executed to form the ferroelectric layer4705on the insulating layer4704to a thickness to just cover its surface, as shown inFIG. 48D.

Formation of the ferroelectric layer4705will be described in detail. In the ECR sputtering apparatus shown inFIG. 5in which the target505made of Bi—Ti—O is used, the substrate4701is heated to, e.g., 300° C. to 700° C. Next, Ar gas as a rare gas is supplied at a flow rate of, e.g., 20 sccm from the inert gas supply unit511into the plasma production chamber502to set the pressure to on the order of, e.g., 10−2to 10−3Pa. A coil current of, e.g., 27 A is supplied to the magnetic coil510to give the magnetic field of the electron cyclotron resonance condition to the plasma production chamber502.

A microwave of, e.g., 2.45 GHz (e.g., 500 W) is supplied from the microwave generation unit (not shown) into the plasma production chamber502through the waveguide508, quartz window507, and vacuum waveguide506. With this supply of the microwave, a plasma is produced in the plasma production chamber502. The produced plasma is output from the plasma production chamber502to the side of the process chamber501by the divergent magnetic field of the magnetic coil510. In addition, a high-frequency power (e.g., 500 W) is supplied from the high-frequency electrode supply unit to the target505placed at the outlet of the plasma production chamber502. When Ar particles collide against the target505, a sputtering phenomenon occurs to sputter Bi particles and Ti particles from the target505.

The Bi particles and Ti particles sputtered from the target505reach the surface of the insulating layer4704together with the plasma output from the plasma production chamber502and the oxygen gas which is supplied from the reactive gas supply unit512and activated by the plasma and are oxidized by the activated oxygen. The oxygen (O2) gas need only be supplied from the matching unit521at a flow rate of, e.g., about 1 sccm. Although the target505is a sintered body and contains oxygen, any shortage of oxygen in the film can be prevented by supplying oxygen.

With the above-described film formation by ECR sputtering, the ferroelectric layer4705having a thickness of, e.g., about 40 nm can be formed (FIG. 48D). After that, the same end process as described above is executed to make it possible to unload the substrate. The film quality may be improved by irradiating the formed ferroelectric layer4705with ECR plasma of an inert gas and a reactive gas. As the reactive gas, not oxygen gas but nitrogen gas, fluorine gas, or hydrogen gas can be used. The film quality improvement can also be applied to formation of the insulating layer4702or insulating layer4704.

When the upper electrode4706made of Au and having a predetermined area is formed on the ferroelectric layer4705, as shown inFIG. 48E, an element using a layer formed from a ferroelectric can be obtained. The upper electrode4706can be formed by a well-known lift-off method and gold deposition by resistance heating vacuum deposition. The upper electrode4706may be made of another metal material or conductive material such as Ru, Pt, or TiN. When Pt is used, the adhesion is poor, and the film may peel off. Hence, the upper electrode4706must be formed as an electrode with a predetermined area by executing film formation by heating or using a structure such as Ti—Pt—Au that hardly peels off and executing a patterning process such as photolithography or lift-off on that structure.

According to this embodiment, the insulating layer4704is formed, and in this state, the ferroelectric layer4705is formed on it. As a result, in forming the ferroelectric layer4705by the above-described ECR sputtering, the ferroelectric film can be formed without degrading the morphology of the surface of the underlying metal film or the surface of the ferroelectric film. For example, if the underlying layer is made of a metal material which is readily oxidized, the surface of the underlying layer may be partially oxidized in the above-described formation of the ferroelectric layer4705, resulting in degradation in morphology. However, according to this embodiment, the ferroelectric layer4705can be formed while keeping the good surface morphology of the underlying layer. Hence, the ferroelectric layer4705with higher quality can be obtained.

The characteristics of the element shown inFIG. 47will be described next. The characteristics were investigated by applying a voltage between the lower electrode layer4703and the upper electrode4706. When a voltage from a power supply was applied between the lower electrode layer4703and the upper electrode4706, and a current flowing when the voltage was applied was measured by an ammeter, a result shown inFIG. 49was obtained. InFIG. 49, the ordinate represents the current density obtained by dividing the current value by the area.FIG. 49and the memory operation principle of the present invention will be described below. The voltage values and current values to be described here are mere examples measured in an actual element. Hence, the phenomenon is not limited to the following numerical values. Other numerical values can also be measured depending on the material and thickness of each film actually used in the element and other conditions.

When a positive voltage is applied to the upper electrode4706, the flowing current is very small in the range of 0 to 1.0 V, as indicated by (1) inFIG. 49. However, as indicated by (2), when the voltage exceeds 1.1 V, a positive current flows abruptly. Actually, a current larger than 0.1 A/cm2also flows. However, since flowing of a larger current is inhibited to protect the measurement device, the current is not measured. In the range of 0 to 1.0 V indicated by (1), a high resistance state is held (maintained) by inhibiting flowing of a large current as indicated by (2).

When a positive voltage is applied again to the upper electrode4706, a locus to flow a positive current of 0.1 A/cm2or more is obtained at about 0.8 V, as indicated by (3). When the positive voltage is further applied to the upper electrode4706, a current of 0.1 A/cm2or more flows at about 0.8 V, as indicated by (3).

When a negative voltage is applied to the upper electrode4706, a negative current flows up to about −0.2 V, as indicated by (4). The current increases to −1.5×10−2A/cm2at maximum. When the absolute value of the voltage is decreased, the current traces a locus indicated by (4).

When the negative voltage is applied up to −0.2 V, the current traces the locus indicated by (4). After that, as indicated by (5), the value of the flowing current decreases, and no negative current flows. When the negative voltage is further applied to the upper electrode4706, a locus to rarely flow a current is obtained, as indicated by (6). Even when the absolute value of the voltage is decreased then, the current rarely flows, as indicated by (6). When a positive voltage is applied to the upper electrode4706, the current rarely flows up to 0 to 1.0 V, as indicated by (1).

Hence, the high resistance state wherein no current flows as in (1) is maintained unless a voltage of 1.1 V or more is applied to the upper electrode4706to prevent any sudden current flow as in (2). The state (1) will be referred to as a “positive high resistance mode”.

For example, as indicated by (2), when a voltage of 1.1 V or more is applied to abruptly flow a current, a low resistance state in which the current readily flows is obtained, as indicated by (3). This state is also maintained while a positive voltage is applied to the upper electrode4706. The state (3) will be referred to as a “positive low resistance mode”.

However, when a negative voltage is applied to the upper electrode4706, a low resistance state in which a small current flows in the early stage in a negative voltage range from 0 to −0.2 V is obtained, as indicated by (4). This state is also maintained while a negative voltage in the range of 0 to −0.2 V is applied. The state (4) will be referred to as a “negative low resistance mode”.

When a negative voltage of −0.2 V or more is applied, no current flows, and the state changes to a high resistance state, as indicated by (5). In this state, the state wherein the current value has a high resistance is maintained while a negative voltage in the range of 0 to −1.0 V is applied, as indicated by (6). The state (6) will be referred to as a “negative high resistance mode”.

As described above, the element using a ferroelectric layer shown inFIG. 47apparently has four stable modes: “positive high resistance mode”, “positive low resistance mode”, “negative high resistance mode”, and “negative low resistance mode”. More specifically, the “positive high resistance mode” and “negative high resistance mode” are “high resistance modes” which exhibit the same high resistance state. The “positive low resistance mode” and “negative low resistance mode” are “low resistance modes” which exhibit the same low resistance state. That is, two modes are present. In the state of the “high resistance mode”, the “high resistance mode” is maintained in the voltage range of −1.5 V to +1.0 V. When a voltage of +1.0 V or more is applied to change the state to the “low resistance mode”, the “low resistance mode” is maintained in the voltage range of −0.2 V to +0.8 V. Switching between the two, “high resistance mode” and “low resistance mode” occurs. This also applied to the negative resistance modes, i.e., “negative high resistance mode” and “negative low resistance mode”.

As for the actual current value in each “positive mode” when a voltage of 0.5 V is applied, the current value in the “positive high resistance mode” is 1.0×10−5A/cm2, and that in the “positive low resistance mode” is 5×10−2A/cm2. The ratio is as high as 5,000 times. This facilitates each mode identification. The present inventors estimate that the above-described phenomenon occurs when the resistance value of the ferroelectric film dramatically changes depending on the direction and magnitude of the applied voltage.

Since the insulating layer4704is provided between the ferroelectric layer4705and the upper electrode4706, carriers can be controlled by the band structure of the insulating layer4704. More specifically, for example, tantalum pentoxide has a band gap of about 4.5 eV. The energy difference viewed from the Fermi level is about 1.2 eV in the conduction band and 2.3 eV in the valence band. That is, the barrier is higher on the valence band side. Hence, the barrier effect is high for holes in the valence band but low for electrons in the conduction band. For further information, see Wilk et al., “J. Appl. Phys.”, No. 87, p. 484 (2000).

From the above-described characteristic, when, e.g., a tantalum pentoxide film is used as the insulating layer between the electrode and the ferroelectric layer, a phenomenon that electrons readily flow but holes hardly flow can be expected. Actually, as shown inFIG. 49, the value of the flowing current largely changes between a case wherein a positive voltage is applied to the upper electrode4706and a case wherein a negative voltage is applied. In discriminating a memory, this has a large effect to increase the signal-to-noise ratio (S/N ratio) and facilitate data discrimination. This is the effect of use of the insulating layer4704.

It was found that when the above-described “low resistance mode” and “high resistance mode” shown inFIG. 49are applied as a memory operation, the element shown inFIG. 47can be used as a nonvolatile nondestructive memory. More specifically, initialization of the element and data erase, i.e., the write of data “off” is done by changing the mode from the “low resistance mode” to the “high resistance mode” by applying a negative voltage of the upper electrode4706, as indicated by (4) or (5) inFIG. 49.

The write of data “on” is done by abruptly flowing a current by applying a positive voltage of 1.1 V or more to the upper electrode4706, as indicated by (2) inFIG. 49. With this operation, the mode is changed from the “high resistance mode” to the “low resistance mode”, and data “on” is written. As described above, when a voltage is applied to the upper electrode4706to set the “high resistance mode” or “low resistance mode”, “off” or “on” data (state) can be written.

The read of data written in the above-described way can easily be done by reading a current value when an appropriate voltage of 0 to 1.0 V is applied to the upper electrode4706. For example, when the mode state of the element shown inFIG. 47is “off”, i.e., “high resistance mode”, it can be determined because a current hardly flows when an appropriate voltage of 0 to 1.0 V is applied, as indicated by (1) inFIG. 49.

When the mode state of the element shown inFIG. 47is “on”, i.e., “low resistance mode”, it can be determined because a current abruptly flows when an appropriate voltage of 0 to 0.8 V is applied, as indicated by (2) inFIG. 49. Since the difference in current value between the “positive high resistance mode” and the “positive low resistance mode”, i.e., “off” and “on” is 5,000 times or more, “off” and “on” can easily be determined. Even in the negative voltage range, “off” and “on” can be determined in the voltage range of 0 to −0.2 V.

The above-described read operation of the memory can easily be done only by checking whether the element shown inFIG. 47is in the “high resistance mode” or “low resistance mode”. In other words, while the element shown inFIG. 47can hold the two modes, data is held. Even when a positive voltage is applied to the electrode to check the mode, the held mode does not change, and data is not destroyed. Hence, according to the element shown inFIG. 47, nondestructive read is possible. The element shown inFIG. 47functions as a nonvolatile memory element since the resistance value of the ferroelectric layer4705changes depending on the voltage applied between the lower electrode layer4703and the upper electrode4706. This element can also be used as a switching element to control the current.

The voltage to operate the element shown inFIG. 47is maximized in the write to set the “positive low resistance mode”. However, the voltage is about 1.1 V, and the power consumption is very low, as shown inFIG. 49. The low power consumption is very advantageous for devices. Devices using a memory, e.g., not only mobile communication devices, digital general-purpose devices, digital image sensing devices, notebook personal computers, and PDAs (Personal Digital Appliances) but also all computers, personal computers, workstations, office computers, mainframes, communication units, and multifunction apparatuses can reduce the power consumption. The memory using the element shown inFIG. 47also has a holding period of 10 years, like the above-described element.

In the above-described example of the present invention, each of the insulating layer on the silicon substrate, the lower electrode layer on the insulating layer, the insulating layer on the lower electrode layer, and the ferroelectric layer on the insulating layer is formed by ECR sputtering. However, the method of forming each layer is not limited to ECR sputtering. For example, the insulating layer to be formed on the silicon substrate may be formed by thermal oxidation or CVD (Chemical Vapor Deposition) or a conventional sputtering method.

The lower electrode layer may be formed by any other film formation method such as EB deposition, CVD, MBE, or IBD. The insulating layer on the lower electrode layer may be formed by ALD, MOCVD, or conventional sputtering. The ferroelectric layer can also be formed by the above-described MOD, conventional sputtering method, PLD, or MOCVD. However, when ECR sputtering is used, flat and excellent insulating film, metal film, and ferroelectric film can easily be obtained.

In the above-described embodiment, after each layer is formed, the substrate is temporarily unloaded into the atmosphere. However, the layers may be formed by a continuous process without unloading the structure into the atmospheric by using an apparatus which connects, through vacuum transfer chambers, the process chambers to realize ECR sputtering to form the respective layers. With this arrangement, the substrate to be processed can be transported in vacuum and is therefore prevented from being influenced by disturbance such as water adhesion. Hence, the film quality and interface properties can be improved.

As shown in patent reference 7, after each layer is formed, the surface of the formed layer may be irradiated with ECR plasma to improve the properties. After each layer is formed, the formed layer may be annealed (heat-treated) in an appropriate gas atmosphere such as hydrogen atmosphere to greatly improve the properties of each layer.

Arraying elements and storing a plurality of data simultaneously in a memory is called “integration”. The degree of integrating elements is called a degree of integration. The structure shown inFIG. 47is very simple and can greatly increase the degree of integration as compared to a conventional memory cell. For DRAMs, SRAMs, or flash memories based on MOSFETs which must ensure gate, source, and drain regions, limitation on integration has been pointed out recently. However, the element shown inFIG. 47uses the simple structure and can therefore increase the degree of integration without being affected by the current limitation on integration.

In the above-described embodiment, a DC voltage is applied. However, even when a pulse voltage having an appropriate width and magnitude is applied, the same effect as described above can be obtained. The basic idea of the present invention is arranging a ferroelectric layer in contact with an insulating layer and sandwiching these layers by two electrodes, as shown inFIG. 47. With this structure, when a predetermined voltage (DC or pulse) is applied between the two electrodes to change the resistance value of the ferroelectric layer and switch the stable high resistance mode and low resistance mode, a memory function can be implemented consequently.

For example, as shown inFIG. 50A, an insulating substrate4701amay be used, and stacked lower electrode layers4703aand4703bmay be used. As shown inFIG. 50B, the insulating substrate4701amay be used, and a contact electrode4703cmay be provided on the lower electrode layer4703. As shown inFIG. 50C, the insulating substrate4701amay be used, and stacked upper electrodes4706aand4706bmay be used. As shown inFIG. 50D, the stacked lower electrode layers4703aand4703band the stacked upper electrodes4706aand4706bmay be used.

As shown inFIG. 51, an insulating substrate5101made of glass or quartz may be used. In this case, as shown inFIG. 52, a through hole may be formed in the substrate5101to form a plug, and an electrical contact may be formed on the lower surface of the substrate5101(the side opposite to the surface where the lower electrode layer4703is formed). With this structure, the present invention can be applied to, e.g. a glass substrate easy to process. Since the ferroelectric layer4705which has a refractive index of about 2.6 measured at a wavelength of 632.8 nm is optically transparent, the structure shown inFIG. 51can be applied to a display. When the ferroelectric layer4705is formed so thick in the range of 10 to 200 nm that an interference color is generated, the visual effect of a colored state can be obtained.

As shown inFIG. 53A, a conductive substrate5201made of, e.g., a metal may be used. As shown inFIG. 53B, a lower electrode layer5202contacting the substrate5201may be formed, and an insulating layer5203, ferroelectric layer5204, and upper electrode5205may be provided on it. In the structure shown inFIG. 53B, a predetermined electrical signal can be applied between the substrate5201and the upper electrode5205.

As shown inFIG. 53C, an insulating layer5302, ferroelectric layer5303, and upper electrode5304may be provided on a metal plate5301. In this structure, the metal plate5301serves as a lower electrode layer. With the structure shown inFIG. 53Cin which the constituent elements are formed on the metal plate5301with high thermal conductivity, a higher cooling effect can be obtained, and a stable element operation can be expected.

As the ferroelectric layer becomes thick, the current flows more hardly, and the resistance increases. When a memory is implemented by using a change in resistance value, the resistance value of in each of the ON state and OFF state is important. For example, when the ferroelectric layer becomes thick, the resistance value in the ON state increases. Since it is difficult to ensure a high S/N ratio, the state of the memory is hard to determine. On the other hand, when the ferroelectric layer becomes thin, and the leakage current is dominant, memory information can hardly be held, and the resistance value in the OFF state increases. It is therefore difficult to ensure a high S/N ratio.

Hence, the ferroelectric layer preferably has an optimum thickness. For example, when the problem of leakage current is taken into consideration, the ferroelectric layer need only have a thickness of at least 10 nm. When the resistance value in the ON state is taken into consideration, the ferroelectric layer is preferably thinner than 200 nm. In experiments conducted by the present inventors, a memory operation was confirmed when the thickness of the ferroelectric layer was 30 to 100 nm. The most satisfactory state was obtained when the thickness of the ferroelectric layer was 50 nm.

A more preferable thickness is present even in the insulating layer on the lower electrode layer. The thickness will be described by using an example in which an Al2O3film, SiO2film, and Ta2O3film are formed on silicon substrates by ECR sputtering using an Al target, Si target, and Ta target. Each film is formed to a predetermined thickness. An upper electrode made of Al is formed on each film. A current-voltage characteristic is measured by applying a voltage between the silicon substrate and the upper electrode. The current density observed in each thin film at −1 V is observed. The result of the current densities is the same as inFIG. 39.

As shown inFIG. 39, the current density changes depending on the material of the insulating layer. The smaller the thickness becomes, the more the leakage current flows to increase the current density. On the other hand, when the thickness increases, the current density decreases. This indicates that if the thickness of too small, the characteristic of an insulating layer cannot be obtained. If the thickness is large, the voltage applied to the ferroelectric film is small so it is difficult to ensure a high S/N ratio, and the memory state is hard to determine. Hence, the insulating layer preferably has an optimum thickness in combination with the ferroelectric layer.

For example, when the problem of leakage current is taken into consideration, and an Al2O3film or SiO2film is used, the thickness is preferably about 1 to 3 nm. A Ta2O3film need only have a thickness of at least 3 nm. When the problem of magnitude of the resistance value is taken into consideration, the insulating layer is preferably thicker than 20 nm. In experiments conducted by the present inventors, the above-described memory operation was confirmed when an insulating layer made of SiO2and Ta2O3had a thickness of 3 to 5 nm.

In the above description, one element has been exemplified. However, a plurality of elements may be arrayed and integrated, as will be described later. For example, as shown inFIG. 54A, a common lower electrode layer5402, insulating layer5403, and ferroelectric layer5404are formed on an insulating substrate5401. A plurality of upper electrodes5405spaced apart from each other by a predetermined distance are formed on the ferroelectric layer5404. That is, a plurality of ferroelectric elements are arrayed in correspondence with the plurality of upper electrodes5405.

A ferroelectric or insulating film has a much lower conductivity than a conductor such as a metal and can therefore be used commonly. In this case, since the working process can be omitted, the productivity can be increased, resulting in large advantage from the industrial viewpoint. When the distance between the ferroelectric elements corresponding to the plurality of upper electrodes5405is set in consideration of, e.g., the conductivity, a stable operation can be expected.

As shown inFIG. 54B, the common lower electrode layer5402may be formed on the insulating substrate5401, and a plurality of elements each including an insulating layer5413, ferroelectric layer5414, and upper electrode5415may be arrayed on the lower electrode layer5402. For example, when a ferroelectric film is formed and processed by using a method such as RIE, ICP etching, or ECR etching, the individual ferroelectric layers5414can be formed. When the elements are separated in this way, the distance between them can further be shortened, and the degree of integration can be made higher.

As shown inFIG. 54C, the common lower electrode layer5402and insulating layer5403may be formed on the insulating substrate5401, and a plurality of elements each including the ferroelectric layer5414and upper electrode5415may be arrayed on the insulating layer5403. As shown inFIG. 54D, the side surfaces of the insulating layer5413and ferroelectric layer5414of each element may be covered with an insulating sidewall5416. As shown inFIG. 54E, the common lower electrode layer5402and insulating layer5403may be formed on the insulating substrate5401, a plurality of elements each including the ferroelectric layer5414and upper electrode5415may be arrayed on the insulating layer5403, and the side surface of the ferroelectric layer5414of each element may be covered with an insulating sidewall5417.

As shown inFIG. 55, the common lower electrode layer5402may be formed on the insulating substrate5401, a plurality of elements each including the insulating layer5413, ferroelectric layer5414, and upper electrode5415may be arrayed on the lower electrode layer5402, and an insulating layer5426may be formed to fill spaces on the sides of the plurality of ferroelectric layers5414that are spaced apart from each other. When the portions between the plurality of ferroelectric layers5414formed separately in correspondence with the elements are covered with an insulator, the leakage current between the elements can be reduced, and their stability can be increased.

As shown inFIG. 13, a plurality of elements according to the embodiment of the present invention are arrayed. More specifically, n elements are arrayed in the X direction, and m elements are arrayed in the Y direction. X-direction buses are connected to the lower electrode layers, and Y-direction buses are connected to the upper electrodes. A processor unit having a selection signal switching function is connected to each of the X- and Y-direction buses. With this structure, a memory capable of accessing each element at random can be implemented.

The change in resistance value of the ferroelectric layer4705can also be controlled by a current. A predetermined voltage is applied to the ferroelectric layer4705in the “high resistance mode” to flow a predetermined current. Immediately after that, a predetermined voltage (e.g., +0.5 V) is applied between the upper electrode4706and the lower electrode layer4703. The current value then changes as shown inFIG. 41.

For example, after a current from 1×10−5A (inclusive) to 1×10−4A (exclusive) is supplied between the electrodes, the current value is small, and a high resistance state is obtained. After a current of 1×10−4A or more is supplied between the electrodes, the value of the flowing current becomes large (e.g., 0.7 mA), and the state changes to a low resistance state. As is apparent from this, the resistance of the ferroelectric layer4705also changes depending on the current flowing to it. That is, two resistance values representing a high resistance state and low resistance state are present. Hence, the element shown inFIG. 1can be driven by both a voltage and a current.

Even in the element shown inFIG. 47, the resistance change in the ferroelectric layer4705can be controlled by a pulse voltage, as in the above-described element. The element can also be used as a switching element to control a current. Even the element shown inFIG. 47can implement a ternary memory, like the above-described element.

Forming the insulating layer4705from a ferroelectric layer containing tantalum pentoxide and silicon dioxide and having a thickness of 5 nm will be described next. A case wherein the insulating layer4704has a three-layered structure formed by stacking a tantalum pentoxide film, silicon dioxide film, and tantalum pentoxide film in this order will be described below. In early experiments, the present inventors formed a metal oxide layer serving as the ferroelectric layer4705on a cleaned silicon substrate. As a result of specific examination of the experiment result, formation of an interface layer between the silicon substrate and the metal oxide layer was observed.

The observation result will be described. The substrate temperature was set to 420° C., and a metal oxide layer containing bismuth and titanium was formed on a silicon substrate. When the state of a section was observed by a transmission electron microscope, the state schematically shown inFIG. 56was observed. As shown inFIG. 56, the ferroelectric layer4705is formed on the substrate4701made of silicon via an interface layer which includes a silicon oxide layer4721and an oxide layer4722made of an oxide containing Bi, Ti, and Si.

When the ferroelectric layer4705is thus formed on the silicon substrate, the above-described two kinds of oxide layers are formed in the interface between them. Even when the ferroelectric layer4705is formed on an intentionally formed silicon oxide layer, an oxide layer containing Bi, Ti, and Si is also observed in the interface. Of the layers formed in the interface, the silicon oxide layer4721is estimated to have a relative dielectric constant as small as 3.8. When a voltage is applied to the ferroelectric layer4705, the voltage may be applied mostly to the silicon oxide layer4721, and no voltage may be distributed to the ferroelectric layer4705. The oxide layer4722poses a problem when interface controllability is required. Hence, when the ferroelectric layer4705is to be formed, a more desirable state can be obtained by suppressing reaction with silicon and preventing formation of silicon oxide with a small relative dielectric constant.

A case wherein the ferroelectric layer4705is formed directly on an underlying metal layer made of, e.g., ruthenium will be examined. As is well known, ruthenium forms an oxide. Hence, when a ferroelectric layer is formed on a metal layer made of ruthenium, the surface of the metal layer is expected to be oxidized to degrade the morphology.

For example, a silicon dioxide layer was formed on a silicon substrate by thermal oxidation. A ruthenium electrode layer having a thickness of about 20 nm was formed on it by the above-described ECR sputtering. The substrate temperature was set to 450° C., and a metal oxide layer containing bismuth and titanium was formed on the ruthenium layer. When the state of a section was observed by a transmission electron microscope, the state shown inFIG. 57was observed.FIG. 58schematically shows the state of the electron micrograph ofFIG. 57.

As shown inFIG. 58, the lower electrode layer4703made of ruthenium is formed on a silicon dioxide layer4702a. The ferroelectric layer4705is formed on the lower electrode layer4703via an interface layer4723made of an oxide containing Bi, Ti, and Ru. The interface layer4723is confirmed by EDS (Energy Dispersive X-ray Spectroscopy) to be an oxide containing Ru, Ti, and Bi. The surface of the ferroelectric layer4705has a morphology of 10 to 20 nm due to the influence of the interface layer4723. As is apparent from this, a more desirable state can be obtained when the ferroelectric layer4705is not directly formed on the metal layer.

From the above experiment and observation results, the present inventors directed attention to an insulating layer having a multilayered structure formed by sandwiching a silicon dioxide layer between tantalum pentoxide layers. When the tantalum pentoxide layers contact the lower electrode layer4703and ferroelectric layer4705, oxidation in the interface of the lower electrode layer4703can be prevented. In addition, formation of an interface layer due to reaction in the interface to the ferroelectric layer4705can be suppressed. When a silicon dioxide layer is formed, insulating properties can be ensured. Hence, any other material capable of preventing formation of an interface layer in the interface between the lower electrode layer4703and the ferroelectric layer4705can be used in place of tantalum pentoxide. The silicon dioxide layer need not always be formed. Only a tantalum pentoxide layer suffices depending on the state of necessary insulating properties.

The characteristic of the element using the insulating layer (insulating layer4702) formed from a tantalum pentoxide layer will be described next. A silicon dioxide layer is formed on a silicon substrate by thermal oxidation. A ruthenium electrode layer having a thickness of about 20 nm is formed on the silicon dioxide layer by the above-described ECR sputtering. A tantalum pentoxide layer, silicon dioxide layer, and tantalum pentoxide layer are stacked in this order on the formed ruthenium electrode layer to form an insulating layer having a thickness of about 5 nm. These layers are formed by the ECR sputtering described with reference toFIG. 48C.

The state of a section of the insulating layer formed on the above-described ruthenium electrode layer was observed by a transmission electron microscope. The tantalum pentoxide layer, silicon dioxide layer, and tantalum pentoxide layer in an amorphous state were observed as a very thin film having a thickness of 5 nm on the ruthenium electrode layer in a crystalline state. No interface layers were observed on the interfaces between the layers, and it was confirmed that the layers were formed very flat.

An investigation result of the electrical characteristics of the insulating layer of the above-described layered structure will be described next. The electrical characteristics were investigated by preparing four samples A, B, C, and D. In the sample A, an insulating layer having a thickness of about 3 nm and including a tantalum pentoxide layer, silicon dioxide layer, and tantalum pentoxide layer stacked in this order is formed on a cleaned p-type silicon substrate. In the sample B, an insulating layer having a thickness of about 3 nm and including a silicon dioxide layer, tantalum pentoxide layer, and silicon dioxide layer stacked in this order is formed on a cleaned p-type silicon substrate. In the sample C, a silicon dioxide insulating layer having a thickness of about 3 nm is formed on a cleaned p-type silicon substrate. In the sample D, a tantalum pentoxide insulating layer having a thickness of about 3 nm is formed on a cleaned p-type silicon substrate.

In each sample, an upper electrode made of aluminum is formed on the insulating layer. A predetermined voltage is applied between the silicon substrate and the upper electrode, thereby measuring the current density. When a negative voltage is applied to the upper electrode to set the silicon substrate in a storage state of the semiconductor, the voltage is applied to only the insulating layer.

FIG. 59shows the measurement result obtained by using the above-described samples. As indicated by c inFIG. 59, the silicon dioxide insulating layer has high insulating properties. To the contrary, as indicated by d, the tantalum pentoxide insulating layer has low insulating properties and a high current density at a very low applied voltage. The samples a and b have intermediate characteristics between the samples c and d. As is apparent from this result, the insulating layer having a multilayered structure formed by sandwiching a silicon dioxide layer between tantalum pentoxide layers can obtain higher insulating properties as compared to the insulating layer including a single tantalum pentoxide layer.

An observation result of an element having the same structure as inFIG. 47, i.e., an element using an insulating layer having a multilayered structure including a silicon dioxide layer sandwiched between tantalum pentoxide layers will be described next. Formation of the element used for observation will briefly be described. A silicon dioxide layer is formed on a silicon substrate by thermal oxidation. A ruthenium electrode layer having a thickness of about 20 nm is formed on the silicon dioxide layer by the above-described ECR sputtering. An insulating layer having a thickness of about 5 nm is formed on the ruthenium electrode layer by stacking a tantalum pentoxide layer, silicon dioxide layer, and tantalum pentoxide layer in this order, as described above. A metal oxide layer having a thickness of about 40 nm and containing bismuth and titanium is formed on the insulating layer at a substrate temperature of 420° C. and an oxygen flow rate of 1 sccm.

FIG. 60shows a result obtained by observing a section of the element formed in the above-described way by using a transmission electron microscope.FIG. 61schematically shows this state. As a result of observation, the insulating layer4704including a tantalum pentoxide layer4724, silicon dioxide layer4725, and tantalum pentoxide layer4726stacked in this order was formed on the lower electrode layer4703. The ferroelectric layer4705was formed on the insulating layer4704. No interface layers were observed on the interfaces between the layers. The interfaces between the layers were flat on the order of nm. As described above, when an insulating layer including a silicon dioxide layer sandwiched between tantalum pentoxide layers is used in forming the element shown inFIG. 47, formation of an interface layer by predicted reaction after oxidation is suppressed, and the surface morphology of the ferroelectric layer is improved.

Still another embodiment of the present invention will be described below with reference to the accompanying drawings.FIG. 62is a sectional view schematically showing a structure example of a bistable resistance value acquisition device according to another embodiment of the present invention. An element (functional element) using a metal oxide layer will be described below. The element shown inFIG. 62comprises, on a substrate6201made of, e.g., single-crystal silicon, an insulating layer6202, a lower electrode layer6203, an insulating layer (first insulating layer)6204, a metal oxide layer6205, an insulating layer (second insulating layer)6206, and an upper electrode6207. The substrate6201can be made of any one of a semiconductor, insulator, and conductive material such as a metal. When the substrate6201is made of a conductive material, the insulating layer6202can be omitted. In this case, the substrate6201made of the conductive material serves as a lower electrode layer.

The lower electrode layer6203and upper electrode6207need only be made of a transition metal including noble metals such as platinum (Pt), ruthenium (Ru), gold (Au), and silver (Ag). The lower electrode layer6203and upper electrode6207may be made of a compound such as a nitride, oxide, or fluoride of a transition metal, such as titanium nitride (TiN), hafnium nitride (HfN), strontium ruthenate (SrRuO2), zinc oxide (ZnO), indium tin oxide (ITO), or lanthanum fluoride (LaF3), or a composite film formed by stacking them.

The insulating layer6204and insulating layer6202need only be made of silicon dioxide, silicon oxynitride, alumina, an oxide such as LiNbO3containing a light metal such as lithium, beryllium, magnesium, or calcium, or a fluoride such as LiCaAlF6, LiSrAlF6, LiYF4, LiLuF4, or KMgF3. Alternatively, the insulating layer6204and insulating layer6202need only be made of an oxide or nitride of a transition metal such as scandium, titanium, strontium, yttrium, zirconium, hafnium, tantalum, or lanthanum series, a silicate (ternary compound of a metal, silicon, and oxygen) containing the above-described elements, an aluminate (ternary compound of a metal, aluminum, and oxygen) containing these elements, or an oxide or nitride containing at least two of the above elements.

The metal oxide layer6205is the same as the ferroelectric layer104shown inFIG. 1and is made of a metal oxide containing at least two metals. For example, the metal oxide layer6205is formed by dispersing a plurality of microcrystalline grains or fine particles of Bi4Ti3O12crystal with a grain size of about 3 to 15 nm in a base layer, i.e., a layer containing titanium in an excessive amount relative to the stoichiometric composition of Bi4Ti3O12. The base layer may be TiOxwith a bismuth content of almost 0. In other words, the base layer is made of a metal oxide which contains two metals and in which the content of one metal is smaller in comparison with the stoichiometric composition. The metal oxide layer6205need only be made of, e.g., a material having a perovskite structure, a material having a pseudo-ilmenite structure, a material having a tungsten-bronze structure, a material having a bismuth layer-structure, or a material having a pyrochlore structure.

More specifically, Bi4Ti3O12, La2Ti2O7, BaTiO3, PbTiO3, Pb(Zr1−xTix)O3, (Pb1−yLay)(Zr1−xTix)O3, LiNbO3, LiTaO3, KNbO3, YMnO3, PbNb3O6, Ba2NaNb5O15, (Ba1−xSrx)2NaNb5O15, Ba2Na1−xBix/3Nb5O15, or a metal oxide (e.g., a ferroelectric) having a bismuth layer structure represented by (Bi2O2)2+(Am−1BmO3m+1)2−wherein A indicates at least one of monovalent, divalent, and trivalent ions and a combination thereof, B indicates at least one of tetravalent, pentavalent, and sexivalent ions and a combination thereof, O indicates oxygen, Bi indicates bismuth, and m indicates 1 to 5.

The metal oxide layer6205may be made of a material represented by Ln1−xAexTrO3or LnAe1−xTrxO3wherein Ln indicates at least one rare-earth metal element selected from the lanthanum series, Ae indicates at least one material selected from light metals of group II (Be, Mg, and Ca, Sr, Ba, and Ra of alkaline earth metals), Tr indicates at least one material selected from heavy metals (transition metals) of group III, group IV, group V, group VI, group VII, group VIII, group I, and group II, and O indicates oxygen. Note that x is a number effective in the solubility limit range.

The metal oxide layer6205is made of a metal oxide containing at least two metals and often exhibits ferroelectric properties. In some cases, however, no ferroelectric properties are exhibited depending on the film thickness condition.

A detailed example of the functional element shown inFIG. 62will be described. For example, the lower electrode layer6203is a ruthenium film having a thickness of 10 nm. The insulating layer6204is a multilayered film made of tantalum pentoxide and silicon dioxide and having a thickness of about 5 nm. The metal oxide layer6205is a Bi4Ti3O12film having a thickness of 40 nm. The insulating layer6206is a tantalum pentoxide layer having a thickness of 3 nm. The upper electrode6207is made of gold. As described above, the structures of the substrate6201and insulating layer6202are not limited to those described above, and any other material can also be selected appropriately if it has no effect on the electrical characteristics.

A detailed method of forming the above-described insulating layer6202, lower electrode layer6203, insulating layer6204, metal oxide layer6205, insulating layer6206, and upper electrode6207will be described later. They can be formed by sputtering a metal target or sintered target in ECR plasma made of argon gas, oxygen gas, or nitrogen gas by using an ECR sputtering apparatus shown inFIG. 5.

An example of a method of manufacturing the functional element shown inFIG. 62will be described next with reference toFIG. 63. As shown inFIG. 63A, the p-type silicon substrate6201having a plane orientation of (100) on the principal plane and a resistivity of 1 to 2 Ωcm is prepared. The surface of the substrate6201is cleaned by a solution mixture of sulfuric acid and a hydrogen peroxide solution, pure water, and a hydrogen fluoride solution and dried.

The insulating layer6202is formed on the cleaned and dried substrate6201. In forming the insulating layer6202, the above-described ECR sputtering apparatus is used. The substrate6201is fixed on a substrate holder504in a process chamber501. Pure silicon (Si) is used as a target505. The insulating layer6202in a metal mode by Si—O molecules is formed on the substrate6201to a thickness to just cover its surface by ECR sputtering using argon (Ar) as a plasma gas and oxygen gas.

In ECR sputtering shown inFIG. 5, a plasma production chamber502is evacuated to a high vacuum state on the order of 10−5to 10−4Pa. For example, Ar gas as a rare gas is supplied at a flow rate of about 20 sccm from an inert gas supply unit511into the plasma production chamber502to set the internal pressure of the plasma production chamber502on the order of, e.g., 10−3- to 10−2Pa. Note that sccm is the unit of flow rate and indicates that a fluid at 0° C. and 1 atmospheric pressure flows 1 cm3in 1 min.

A coil current of, e.g., 28 A is supplied to a magnetic coil510to give the magnetic field of the electron cyclotron resonance condition to the plasma production chamber502. The magnetic flux density in the plasma production chamber502is set to, e.g., about 87.5 mT (tesla).

A microwave of, e.g., 2.45 GHz (e.g., 500 W) is supplied from a microwave generation unit (not shown) into the plasma production chamber502through a waveguide508, quartz window507, and vacuum waveguide506. With this supply of the microwave, Ar plasma is produced in the plasma production chamber502.

The plasma produced by the above-described method is output from the plasma production chamber502to the side of the process chamber501by the divergent magnetic field of the magnetic coil510. In addition, a high-frequency power (e.g., 500 W) is supplied from a high-frequency power supply522to the target505placed at the outlet of the plasma production chamber502. When Ar particles collide against the target505, a sputtering phenomenon occurs to sputter Si particles from the target505.

After this state is obtained, a shutter (not shown) between the process chamber501and the substrate6201is opened. The Si particles sputtered from the target505reach the surface of the substrate6201together with the plasma output from the plasma production chamber502and the oxygen gas which is supplied from a reactive gas supply unit512and activated by the plasma and are oxidized to silicon dioxide by the activated oxygen.

With the above process, the insulating layer6202made of silicon dioxide and having a thickness of, e.g., about 100 nm can be formed on the substrate6201(FIG. 63A). When the insulating layer is formed to a predetermined thickness, the above-described shutter is closed not to make the sputtered material reach the substrate6201, thereby stopping film formation. After that, plasma irradiation is stopped by, e.g., stopping supplying the microwave power. Supply of the gases is stopped. When the substrate temperature decreases to a predetermined value, and the internal pressure of the process chamber501is increased to the atmospheric pressure, the substrate6201which has undergone film formation is unloaded from the process chamber501.

The insulating layer6202ensures insulation to prevent a voltage from leaking to the substrate6201and influencing desired electrical characteristics when a voltage is applied between the lower electrode layer6203and upper electrode6207to be formed later. For example, a silicon oxide film formed by oxidizing the surface of the silicon substrate by thermal oxidation may be used as the insulating layer6202. The insulating layer6202may be made of any other insulating material except silicon oxide if the insulating properties can be ensured. The thickness of the insulating layer6202need not always be 100 nm and may be smaller or larger. In the above-described formation of the insulating layer6202by ECR sputtering, the substrate6201is not heated. However, the film may be formed while heating the substrate6201. Alternatively, the surface of the substrate6201made of silicon may be oxidized by thermal oxidation to form the insulating layer6202made of silicon oxide.

After the insulating layer6202is formed in the above-described manner, the substrate6201is unloaded from the apparatus to the atmosphere. The substrate6201is fixed on the substrate holder504of the same ECR sputtering apparatus as inFIG. 5in which pure ruthenium (Ru) is used as the target505. ECR sputtering using argon (Ar) as a plasma gas and xenon (Xe) is executed to form an Ru film on the insulating layer6202to a thickness to just cover its surface, thereby forming the lower electrode layer6203, as shown inFIG. 63B.

Formation of the Ru film will be described in detail. In the ECR sputtering apparatus shown inFIG. 5, the substrate6201is heated to, e.g., about 400° C. Next, Ar gas as a rare gas is supplied at a flow rate of, e.g., 7 sccm from the inert gas supply unit511into the plasma production chamber502, and Xe gas is supplied at a flow rate of, e.g., 5 sccm to set the internal pressure of the plasma production chamber502to on the order of, e.g., 10−3to 10−2Pa. A coil current of, e.g., 26 A is supplied to the magnetic coil510to give the magnetic field of the electron cyclotron resonance condition to the plasma production chamber502.

A microwave of, e.g., 2.45 GHz (e.g., 500 W) is supplied from the microwave generation unit (not shown) into the plasma production chamber502through the waveguide508, quartz window507, and vacuum waveguide. With this supply of the microwave, a plasma of Ar and Xe is produced in the plasma production chamber502. The produced plasma is output from the plasma production chamber502to the side of the process chamber501by the divergent magnetic field of the magnetic coil510. In addition, a high-frequency power (e.g., 500 W) is supplied from the high-frequency electrode supply unit to the target505placed at the outlet of the plasma production chamber502. When Ar particles collide against the target505, a sputtering phenomenon occurs to sputter Ru particles from the target505. The Ru particles sputtered from the target505reach the surface of the insulating layer6202on the substrate6201and are deposited.

With the above process, the lower electrode layer6203having a thickness of, e.g., about 10 nm can be formed on the insulating layer6202(FIG. 63B). The lower electrode layer6203enables voltage application to the metal oxide layer6205and insulating layer6204when a voltage is applied between the lower electrode layer6203and the upper electrode6207to be formed later. The lower electrode layer6203may be made of any other material except ruthenium if the conductivity can be ensured. The thickness of the lower electrode layer6203need not always be 10 nm and may be smaller or larger.

As described above, in forming the Ru film by ECR sputtering, the substrate6201is heated to 400° C. However, the substrate need not always be heated. However, if the substrate is not heated, the adhesion of ruthenium to silicon dioxide becomes low, and the film may peel off. To prevent peeling, the film is formed preferably while heating the substrate. After Ru is deposited to a desired thickness in the above-described way, an end process is executed by stopping film formation by, e.g., closing the shutter and stopping plasma irradiation by stopping supply of the microwave power. Then, the substrate6201can be unloaded.

After the lower electrode layer6203is formed in the above-described manner, the substrate6201is unloaded from the apparatus to the atmosphere. The substrate6201is fixed on the substrate holder504of the same ECR sputtering apparatus as inFIG. 5in which pure tantalum (Ta) is used as the target505. The insulating layer6204is formed on the lower electrode layer6203to a thickness to just cover its surface, as shown inFIG. 63C, by ECR sputtering using argon (Ar) as a plasma gas and oxygen gas. A metal mode film by Ta—O molecules is formed as the insulating layer6204, as will be described below.

Formation of a metal mode film by Ta—O molecules will be described in detail. In the ECR sputtering apparatus shown inFIG. 5in which the target505made of tantalum is used, the plasma production chamber502is evacuated a high vacuum state on the order of 10−5to 10−4Pa. Then, Ar gas as a rare gas is supplied at a flow rate of, e.g., 25 sccm from the inert gas supply unit511into the plasma production chamber502to set the internal pressure of the plasma production chamber502on the order of, e.g., 10−3to 10−2Pa. A coil current of, e.g., 27 A is supplied to the magnetic coil510to give the magnetic field of the electron cyclotron resonance condition to the plasma production chamber502.

A microwave of, e.g., 2.45 GHz (e.g., 500 W) is supplied from the microwave generation unit (not shown) into the plasma production chamber502through the waveguide508, quartz window507, and vacuum waveguide506. With this supply of the microwave, Ar plasma is produced in the plasma production chamber502. The produced plasma is output from the plasma production chamber502to the side of the process chamber501by the divergent magnetic field of the magnetic coil510. In addition, a high-frequency power (e.g., 500 W) is supplied from the high-frequency electrode supply unit to the target505placed at the outlet of the plasma production chamber502. When Ar particles collide against the target505, a sputtering phenomenon occurs to sputter Ta particles from the target505.

The Ta particles sputtered from the target505reach the surface of the lower electrode layer6203on the substrate6201together with the plasma output from the plasma production chamber502and the oxygen gas which is supplied from the reactive gas supply unit512and activated by the plasma and are oxidized to tantalum pentoxide by the activated oxygen.

With the above process, a tantalum pentoxide film is formed on the lower electrode layer6203. Subsequently, a silicon dioxide film is formed on the tantalum pentoxide film by ECR sputtering using the target505made of pure silicon, like silicon dioxide deposition described with reference toFIG. 63A. The above-described formation of a tantalum pentoxide film and silicon dioxide film is repeated to form a multilayered film including the tantalum pentoxide films and silicon dioxide films to, e.g., about 5 nm, thereby obtaining the insulating layer6204(FIG. 63D).

The insulating layer6204including the tantalum pentoxide films and silicon dioxide films is used to control the voltage to be applied to the metal oxide layer6205upon voltage application to the metal oxide layer6205. The insulating layer6204may have any other structure except the multilayered structure of tantalum pentoxide films and silicon dioxide films if it can control the voltage applied to the metal oxide layer6205. The insulating layer6204may be a single layer. The thickness is not limited to 5 nm, either. In the above-described ECR sputtering, the substrate6201is not heated but may be heated.

After the insulating layer6204is formed in the above-described manner, the substrate6201is unloaded from the apparatus to the atmosphere. The substrate6201is fixed on the substrate holder504of the same ECR sputtering apparatus as inFIG. 5in which a sintered body (Bi—Ti—O) with an Bi—Ti ratio of 4:3 is used as the target505. ECR sputtering using argon (Ar) as a plasma gas and oxygen gas is executed to form the metal oxide layer6205on the insulating layer6204to a thickness to just cover its surface, as shown inFIG. 63D.

Formation of the metal oxide layer6205will be described in detail. In the ECR sputtering apparatus shown inFIG. 5in which the target505made of Bi—Ti—O is used, the process chamber501and plasma production chamber502are evacuated to set the internal pressure to 10−5to 10−4Pa. Then, the substrate6201is heated to, e.g., 300° C. to 700° C. Next, Ar gas as a rare gas is supplied at a flow rate of, e.g., 20 sccm from the inert gas supply unit511into the plasma production chamber502to set the pressure to on the order of, e.g., 10−3to 10−2Pa. A coil current of, e.g., 27 A is supplied to the magnetic coil510to give the magnetic field of the electron cyclotron resonance condition to the plasma production chamber502.

A microwave of, e.g., 2.45 GHz (e.g., 500 W) is supplied from the microwave generation unit (not shown) into the plasma production chamber502through the waveguide508, quartz window507, and vacuum waveguide506. With this supply of the microwave, a plasma is produced in the plasma production chamber502. The produced plasma is output from the plasma production chamber502to the side of the process chamber501by the divergent magnetic field of the magnetic coil510. In addition, a high-frequency power (e.g., 500 W) is supplied from the high-frequency electrode supply unit to the target505placed at the outlet of the plasma production chamber502. When Ar particles collide against the target505, a sputtering phenomenon occurs to sputter Bi particles and Ti particles from the target505.

The Bi particles and Ti particles sputtered from the target505reach the surface of the insulating layer6204together with the plasma output from the plasma production chamber502and the oxygen gas which is supplied from the reactive gas supply unit512and activated by the plasma and are oxidized by the activated oxygen. The oxygen (O2) gas need only be supplied from the matching unit521at a flow rate of, e.g., about 1 sccm. Although the target505is a sintered body and contains oxygen, any shortage of oxygen in the film can be prevented by supplying oxygen.

With the above-described film formation by ECR sputtering, the metal oxide layer6205having a thickness of, e.g., about 40 nm can be formed (FIG. 63D). After that, the same end process as described above is executed to make it possible to unload the substrate.

After the metal oxide layer6205is formed in the above-described manner, the substrate6201is unloaded from the apparatus to the atmosphere. The substrate6201is fixed on the substrate holder504of the same ECR sputtering apparatus as inFIG. 5in which pure tantalum (Ta) is used as the target505. A tantalum pentoxide film is formed on the metal oxide layer6205a thickness to just cover its surface, as shown inFIG. 63(e), by ECR sputtering using argon as a plasma gas and oxygen gas as a reactive gas, thereby forming the insulating layer6206. The tantalum pentoxide film is a metal mode film by Ta—O molecules, as will be described below.

Formation of a metal mode film by Ta—O molecules will be described in detail. In the ECR sputtering apparatus shown inFIG. 5in which the target505made of tantalum is used, the plasma production chamber502is evacuated a high vacuum state on the order of 10−5to 10−4Pa. Then, Ar gas is supplied at a flow rate of, e.g., 25 sccm from the inert gas supply unit511into the plasma production chamber502to set the internal pressure of the plasma production chamber502on the order of, e.g., 10−3to 10−2Pa. A coil current of, e.g., 27 A is supplied to the magnetic coil510to give the magnetic field of the electron cyclotron resonance condition to the plasma production chamber502.

A microwave of, e.g., 2.45 GHz (e.g., 500 W) is supplied from the microwave generation unit (not shown) into the plasma production chamber502through the waveguide508, quartz window507, and vacuum waveguide506. With this supply of the microwave, Ar plasma is produced in the plasma production chamber502. The produced plasma is output from the plasma production chamber502to the side of the process chamber501by the divergent magnetic field of the magnetic coil510. In addition, a high-frequency power (e.g., 500 W) is supplied from the high-frequency electrode supply unit to the target505placed at the outlet of the plasma production chamber502. When Ar particles collide against the target505, a sputtering phenomenon occurs to sputter Ta particles from the target505.

The Ta particles sputtered from the target505reach the surface of the lower electrode layer6203on the substrate6201together with the plasma output from the plasma production chamber502and the oxygen gas which is supplied from the reactive gas supply unit512and activated by the plasma and are oxidized to tantalum pentoxide by the activated oxygen.

With the above process, a tantalum pentoxide film having a thickness of about 3 nm is formed on the metal oxide layer6205so that the insulating layer6206is formed, as shown inFIG. 63(e). The insulating layer6206made of tantalum pentoxide is used to control the voltage to be applied to the metal oxide layer6205upon voltage application to the metal oxide layer6205. The insulating layer6206may be made of any other material except tantalum pentoxide if it can control the voltage applied to the metal oxide layer6205. The insulating layer6206may be a single layer. The thickness is not limited to 3 nm, either.

In the above-described ECR sputtering, the substrate6201is not heated but may be heated. The properties may be improved by irradiating the surface of the formed insulating layer6206with ECR plasma of an inert gas and a reactive gas. As the reactive gas, oxygen gas, nitrogen gas, fluorine gas, or hydrogen gas can be used. The film quality improvement can also be applied to the insulating layer6204or metal oxide layer6205.

When the upper electrode6207made of Au and having a predetermined area is formed on the insulating layer6206, as shown inFIG. 63(f), an element using a metal oxide layer containing at least two metals can be obtained. The upper electrode6207can be formed by a well-known lift-off method and gold deposition by resistance heating vacuum deposition. The upper electrode6207may be made of another metal material or conductive material such as Ru, Pt, or TiN. When Pt is used, the adhesion is poor, and the film may peel off. Hence, the upper electrode6207must be formed as an electrode with a predetermined area by executing film formation by heating or using a structure such as Ti—Pt—Au that hardly peels off and executing a patterning process such as photolithography or lift-off on that structure.

According to this embodiment, the insulating layer6204is formed, and in this state, the metal oxide layer6205is formed on it. As a result, in forming the metal oxide layer6205by the above-described ECR sputtering, the morphology of the surface of the underlying metal film or the surface of the metal oxide layer6205does not degrades. For example, if the underlying layer is made of a metal material which is readily oxidized, the surface of the underlying layer may be partially oxidized in the above-described formation of the metal oxide layer6205, resulting in degradation in morphology. However, according to this embodiment, the metal oxide layer6205can be formed while keeping the good surface morphology of the underlying layer. Hence, the metal oxide layer6205with higher quality can be obtained.

The characteristics of the functional element shown inFIG. 62will be described next. The characteristics were investigated by applying a voltage between the lower electrode layer6203and the upper electrode6207. When a voltage from a power supply was applied between the lower electrode layer6203and the upper electrode6207, and a current flowing when the voltage was applied was measured by an ammeter, a result shown inFIG. 64was obtained. InFIG. 64, the ordinate indicates the absolute value of a current value as a logarithm. For this reason, a current value is indicated as a positive current value independently of whether the applied voltage is positive or negative. Actually, when a positive voltage is applied, a positive current value is observed. When a negative voltage is applied, a negative current value is observed.FIG. 64and the memory operation principle of the present invention will be described below. The voltage values and current values to be described here are mere examples measured in an actual element. Hence, the phenomenon is not limited to the following numerical values. Other numerical values can also be measured depending on the material and thickness of each film actually used in the element and other conditions.

When a positive voltage is applied to the upper electrode6207, the flowing current is very small in the range of 0 to 1.6 V, as indicated by (1) inFIG. 64. However, as indicated by (2), when the voltage exceeds 1.6 V, a positive current flows abruptly. Actually, a current larger than 5×10−3A/cm2also flows. However, since flowing of a larger current is inhibited to protect the measurement device, the current is not measured. When a voltage of 0 to 1.6 V is applied to inhibit abrupt current flow as indicated by (2), a state wherein the resistance is high, as indicated by (1), is maintained.

When a positive voltage is applied again to the upper electrode6207, a locus to flow a positive current of 1×10−3A/cm2or more is obtained at about 0.5 V, as indicated by (3). When the positive voltage is further applied to the upper electrode6207, a current of 1×10−3A/cm2or more flows at about 0.5 V, as indicated by (3). When a voltage of 0 to 0.5 V is applied, a state wherein the resistance is low, as indicated by (3), is maintained.

When a negative voltage is applied to the upper electrode6207, a negative current flows up to about −0.5 V, as indicated by (4). The current increases to −1.5×10−3A/cm2at maximum. When a voltage of 0 to −0.5 V is applied, a state wherein the resistance is low is maintained, as indicated by (4).

When a negative voltage is applied from −0.5 V to −1.6 V, the current value decreases, and no negative current flows, as indicated by (5). Even when the absolute value of the voltage from −1.6 V to 0 V is decreased then, the current rarely flows, as indicated by (6). When a negative voltage is applied to the upper electrode6207, a locus to rarely flow a current is obtained, as indicated by (6).

When a positive voltage is applied to the upper electrode6207, a locus to rarely flow a current t up 0 to 1.6 V is obtained, as indicated by (1) When a voltage of 1.6 V or more is applied, a state representing a low resistance indicated by (3) is obtained.

Hence, the high resistance state wherein no current flows as in (1) is maintained unless a voltage of 1.6 V or more is applied to the upper electrode6207to prevent any sudden current flow as in (2). The state (1) will be referred to as a “positive high resistance mode”.

For example, as indicated by (2), when a voltage of 1.6 V or more is applied to abruptly flow a current, a low resistance state in which the current readily flows is obtained, as indicated by (3). This state is also maintained while a positive voltage is applied to the upper electrode6207. The state (3) will be referred to as a “positive low resistance mode”.

However, when a negative voltage is applied to the upper electrode6207, a low resistance state in which a small current flows in the early stage in a negative voltage range from 0 to −0.5 V is obtained, as indicated by (4). This state is also maintained while a negative voltage in the range of 0 to −0.5 V is applied. The state (4) will be referred to as a “negative low resistance mode”.

When a negative voltage exceeding −0.5 V is applied, no current flows, and the state changes to a high resistance state, as indicated by (5). In this state, the state wherein the current value has a high resistance is maintained while a negative voltage in the range of 0 to −1.6 V is applied, as indicated by (6). The state (6) will be referred to as a “negative high resistance mode”.

As described above, the element using a metal oxide layer shown inFIG. 62apparently has four stable modes: “positive high resistance mode”, “positive low resistance mode”, “negative high resistance mode”, and “negative low resistance mode”. More specifically, the “positive high resistance mode” and “negative high resistance mode” are “high resistance modes” which exhibit the same high resistance state. The “positive low resistance mode” and “negative low resistance mode” are “low resistance modes” which exhibit the same low resistance state. That is, two modes are present. In the state of the “high resistance mode”, the “high resistance mode” is maintained in the voltage range of −1.6 V to +1.6 V. When a voltage of +1.6 V or more is applied to change the state to the “low resistance mode”, the “low resistance mode” is maintained in the voltage range of −0.5 V to +0.5 V. Switching between the two, “high resistance mode” and “low resistance mode” occurs. This also applied to the negative resistance modes, i.e., “negative high resistance mode” and “negative low resistance mode”.

As for the actual current value in each “positive mode” when a voltage of 0.5 V is applied, the current value in the “positive high resistance mode” is 5.0×10−6A/cm2, and that in the “positive low resistance mode” is 5×10−3A/cm2. The ratio is as high as 1,000 times. This facilitates each mode identification. The present inventors estimate that the above-described phenomenon occurs when the resistance value of the metal oxide layer6205dramatically changes depending on the direction and magnitude of the applied voltage. This also applies to the “negative low resistance mode”.

Since the insulating layer6204is provided between the metal oxide layer6205and the upper electrode6207, carriers can be controlled by the band structure of the insulating layer6204. More specifically, for example, tantalum pentoxide has a band gap of about 4.5 eV. The energy difference viewed from the Fermi level is about 1.2 eV in the conduction band and 2.3 eV in the valence band. That is, the barrier is higher on the valence band side. Hence, the barrier effect is high for holes in the valence band but low for electrons in the conduction band. For further information, see Wilk et al., “J. Appl. Phys.”, No. 87, p. 484 (2000).

It was found that when the above-described “low resistance mode” and “high resistance mode” shown inFIG. 64are applied as a memory operation, the element shown inFIG. 62can be used as a nonvolatile nondestructive memory. More specifically, initialization of the element and data erase, i.e., the write of data “off” is done by changing the mode from the “low resistance mode” to the “high resistance mode” by applying a negative voltage of the upper electrode6207, as indicated by (4) or (5) inFIG. 64.

The write of data “on” is done by abruptly flowing a current by applying a positive voltage of 1.6 V or more to the upper electrode6207, as indicated by (2) inFIG. 64. With this operation, the mode is changed from the “high resistance mode” to the “low resistance mode”, and data “on” is written. As described above, when a voltage is applied to the upper electrode6207to set the “high resistance mode” or “low resistance mode”, “off” or “on” data (state) can be written.

The read of data written in the above-described way can easily be done by reading a current value when an appropriate voltage of 0 to 1.6 V is applied to the upper electrode6207. For example, when the mode state of the element shown inFIG. 62is “off”, i.e., “high resistance mode”, it can be determined because a current hardly flows when an appropriate voltage of 0.5 to 1.6 V is applied, as indicated by (1) inFIG. 64.

When the mode state of the element shown inFIG. 62is “on”, i.e., “low resistance mode”, it can be determined because a current abruptly flows when an appropriate voltage of 1 to 0.6 V is applied, as indicated by (2) inFIG. 64. Since the difference in current value between the “high resistance mode” and the “low resistance mode”, i.e., “off” and “on” is 1,000 times or more, “off” and “on” can easily be determined. Even in the negative voltage range, “off” and “on” can be determined in the voltage range of 0 to −1.6 V.

The above-described read operation of the memory can easily be done only by checking whether the element shown inFIG. 62is in the “high resistance mode” or “low resistance mode”. In other words, while the element shown inFIG. 62can hold the two modes, data is held. Even when a positive voltage is applied to the electrode to check the mode, the held mode does not change, and data is not destroyed. Hence, according to the functional element shown inFIG. 62, nondestructive read is possible. The element shown inFIG. 62functions as a nonvolatile memory element since the resistance value of the metal oxide layer6205changes depending on the voltage applied between the lower electrode layer6203and the upper electrode6207. This element can also be used as a switching element to control the current.

The voltage to operate the element shown inFIG. 62is maximized in the write to set the “positive low resistance mode”. However, the voltage is about 1.6 V at most, and the power consumption is very low, as shown inFIG. 64. The low power consumption is very advantageous for devices. Devices using a memory, e.g., not only mobile communication devices, digital general-purpose devices, digital image sensing devices, notebook personal computers, and PDAs (Personal Digital Appliances) but also all computers, personal computers, workstations, office computers, mainframes, communication units, and multifunction apparatuses can reduce the power consumption. The memory using the element shown inFIG. 62also has a holding period of 10 years.

In the above-described example of the present invention, each of the insulating layer on the silicon substrate, the lower electrode layer on the insulating layer, the insulating layer on the lower electrode layer, the metal oxide layer on the insulating layer, and the insulating layer on the metal oxide layer is formed by ECR sputtering. However, the method of forming each layer is not limited to ECR sputtering. For example, the insulating layer to be formed on the silicon substrate may be formed by thermal oxidation or CVD (Chemical Vapor Deposition) or a conventional sputtering method.

The lower electrode layer may be formed by any other film formation method such as EB deposition, CVD, MBE, or IBD. The insulating layer on the lower electrode layer may be formed by ALD, MOCVD, or conventional sputtering. The metal oxide layer can also be formed by the above-described MOD, conventional sputtering method, PLD, or MOCVD. However, when ECR sputtering is used, flat and excellent insulating film, metal film, and metal oxide film of, e.g., a ferroelectric can easily be obtained.

In the above-described embodiment, after each layer is formed, the substrate is temporarily unloaded into the atmosphere. However, the layers may be formed by a continuous process without unloading the structure into the atmospheric by using an apparatus which connects, through vacuum transfer chambers, the process chambers to realize ECR sputtering to form the respective layers. With this arrangement, the substrate to be processed can be transported in vacuum and is therefore prevented from being influenced by disturbance such as water adhesion. Hence, the film quality and interface properties can be improved.

As shown in Japanese Patent Laid-Open No. 2003-77911, after each layer is formed, the surface of the formed layer may be irradiated with ECR plasma to improve the properties. After each layer is formed, the formed layer may be annealed (heat-treated) in an appropriate gas atmosphere such as hydrogen atmosphere to greatly improve the properties of each layer.

Arraying elements and storing a plurality of data simultaneously in a memory is called “integration”. The degree of integrating elements is called a degree of integration. The structure shown inFIG. 62is very simple and can greatly increase the degree of integration as compared to a conventional memory cell. For DRAMs, SRAMs, or flash memories based on MOSFETs which must ensure gate, source, and drain regions, limitation on integration has been pointed out recently. However, the element shown inFIG. 62uses the simple structure and can therefore increase the degree of integration without being affected by the current limitation on integration.

In the above-described embodiment, a DC voltage is applied. However, even when a pulse voltage having an appropriate width and magnitude is applied, the same effect as described above can be obtained. The basic idea of the present invention is arranging a metal oxide layer in contact with an insulating layer and sandwiching these layers by two electrodes, as shown inFIG. 62. With this structure, when a predetermined voltage (DC or pulse) is applied between the two electrodes to change the resistance value of the metal oxide layer and switch the stable high resistance mode and low resistance mode, a memory function can be implemented consequently.

For example, as shown inFIG. 65A, an insulating substrate6201amay be used, and stacked lower electrode layers6203aand6203bmay be used. As shown inFIG. 65B, the insulating substrate6201amay be used, and a contact electrode6203cmay be provided on the lower electrode layer6203. As shown inFIG. 65C, the insulating substrate6201amay be used, and stacked upper electrodes6207aand6207bmay be used. As shown inFIG. 65D, the stacked lower electrode layers6203aand6203band the stacked upper electrodes6207aand6207bmay be used.

As shown inFIG. 66A, an insulating substrate6601made of glass or quartz may be used. In this case, as shown inFIG. 66B, a through hole may be formed in the substrate6601to form a plug, and an electrical contact may be formed on the lower surface of the substrate6601(the side opposite to the surface where the lower electrode layer6203is formed). With this structure, the present invention can be applied to, e.g. a glass substrate easy to process. Since the metal oxide layer6205which has a refractive index of about 2.6 measured at a wavelength of 632.8 nm is optically transparent, the structure shown inFIG. 66Aor66B can be applied to a display. When the metal oxide layer6205is formed so thick in the range of 10 to 200 nm that an interference color is generated, the visual effect of a colored state can be obtained.

As shown inFIG. 67A, a conductive substrate6701made of, e.g., a metal may be used. As shown inFIG. 67B, a lower electrode layer6702contacting the substrate6701may be formed, and an insulating layer6703, metal oxide layer6704, insulating layer6705, and upper electrode6706may be provided on it. In the structure shown inFIG. 67B, a predetermined electrical signal can be applied between the substrate6701and the upper electrode6706.

As shown inFIG. 68, an insulating layer6802, metal oxide layer6803, insulating layer6804, and upper electrode6805may be provided on a metal plate6801. In this structure, the metal plate6801serves as a lower electrode layer. With the structure shown inFIG. 68in which the constituent elements are formed on the metal plate6801with high thermal conductivity, a higher cooling effect can be obtained, and a stable element operation can be expected.

As the metal oxide layer becomes thick, the current flows more hardly, and the resistance increases. When a memory is implemented by using a change in resistance value, the resistance value of in each of the ON state and OFF state is important. For example, when the metal oxide layer becomes thick, the resistance value in the ON state increases. Since it is difficult to ensure a high S/N ratio, the state of the memory is hard to determine. On the other hand, when the metal oxide layer becomes thin, and the leakage current is dominant, memory information can hardly be held, and the resistance value in the OFF state increases. It is therefore difficult to ensure a high S/N ratio.

Hence, the metal oxide layer preferably has an optimum thickness. For example, when the problem of leakage current is taken into consideration, the metal oxide layer need only have a thickness of at least 10 nm. When the resistance value in the ON state is taken into consideration, the metal oxide layer is preferably thinner than 200 nm. In experiments conducted by the present inventors, a memory operation was confirmed when the thickness of the metal oxide layer was 30 to 100 nm. The most satisfactory state was obtained when the thickness of the metal oxide layer was 50 nm.

A more preferable thickness is present even in the insulating layer on the lower electrode layer. More specifically, in forming the insulating layer by ECR sputtering, the smaller the thickness becomes, the more the leakage current flows to increase the current density. On the other hand, when the thickness increases, the current density decreases. This indicates that if the thickness of too small, the characteristic of an insulating layer cannot be obtained. If the thickness is large, the voltage applied to the metal oxide layer is small so it is difficult to ensure a high S/N ratio, and the memory state is hard to determine. As described above, the insulating layer preferably has an optimum thickness in combination with the metal oxide layer.

For example, when the problem of leakage current is taken into consideration, and an SiO2film is used, the thickness is preferably about 1 to 3 nm. A Ta2O3film need only have a thickness of 3 to 5 nm. When the problem of magnitude of the resistance value is taken into consideration, the insulating layer is preferably thicker than 20 nm. In experiments conducted by the present inventors, the above-described memory operation was confirmed when an insulating layer made of SiO2and Ta2O3had a thickness of 3 to 5 nm.

In the above description, one functional element has been exemplified. However, a plurality of functional elements may be arrayed and integrated, as will be described later. For example, as shown inFIG. 69A, a common lower electrode layer6902, insulating layer6903, metal oxide layer6904, and insulating layer6905are formed on an insulating substrate6901. A plurality of upper electrodes6906spaced apart from each other by a predetermined distance are formed on the insulating layer6905. That is, a plurality of functional elements are arrayed in correspondence with the plurality of upper electrodes6906.

The metal oxide layer6205or insulating layer6903or6905has a much lower conductivity than a conductor such as a metal and can therefore be used commonly. In this case, since the working process can be omitted, the productivity can be increased, resulting in large advantage from the industrial viewpoint. When the distance between the functional elements corresponding to the plurality of upper electrodes6906is set in consideration of, e.g., the conductivity, a stable operation can be expected.

As shown inFIG. 69B, the common lower electrode layer6902may be formed on the insulating substrate6901, and a plurality of elements each including an insulating layer6913, metal oxide layer6914, insulating layer6915, and upper electrode6916may be arrayed on the lower electrode layer6902. For example, when a metal oxide film is formed and processed by using a method such as RIE, ICP etching, or ECR etching, the individual metal oxide layers6914can be formed. When the elements are separated in this way, the distance between them can further be shortened, and the degree of integration can be made higher.

As shown inFIG. 69C, the common lower electrode layer6902and insulating layer6903may be formed on the insulating substrate6901, and a plurality of elements each including the metal oxide layer6914, insulating layer6915, and upper electrode6916may be arrayed on the insulating layer6903. As shown inFIG. 69D, the side surfaces of the insulating layer6913, metal oxide layer6914, and insulating layer6915of each element may be covered with an insulating sidewall6917. As shown inFIG. 69(e), the common lower electrode layer6902and insulating layer6903may be formed on the insulating substrate6901, a plurality of elements each including the metal oxide layer6914, insulating layer6915, and upper electrode6916may be arrayed on the insulating layer6903, and the side surface of the metal oxide layer6914of each element may be covered with an insulating sidewall6918.

As shown inFIG. 70, the common lower electrode layer6902may be formed on the insulating substrate6901, a plurality of elements each including the insulating layer6913, metal oxide layer6914, insulating layer6915, and upper electrode6916may be arrayed on the lower electrode layer6902, and an insulating layer6926may be formed to fill spaces on the sides of the plurality of metal oxide layers6914that are spaced apart from each other. When the portions between the plurality of metal oxide layers6914formed separately in correspondence with the elements are covered with an insulator, the leakage current between the functional elements can be reduced, and their stability can be increased.

A plurality of functional elements are arrayed and, more specifically, n elements are arrayed in the X direction, and m elements are arrayed in the Y direction. X-direction buses are connected to the lower electrode layers, and Y-direction buses are connected to the upper electrodes. A processor unit having a selection signal switching function is connected to each of the X- and Y-direction buses. With this structure, a memory capable of accessing each element at random can be implemented.

The change in resistance value of the metal oxide layer6205can also be controlled by a current, like the above-described element. The resistance change in the metal oxide layer6205can be controlled by a pulse voltage. The element can also be used as a switching element.

According to the element shown inFIG. 62which uses the metal oxide layer6205of this embodiment, the current-voltage characteristic when a DC voltage is applied between the lower electrode layer6203and the upper electrode6207is changed to different low resistance states by changing the positive-side applied voltage, as shown inFIG. 71. These correspond to the current values at the read voltage in the respective states. Hence, a memory with three states (three values) indicated by a square, circle, and triangle can be implemented. For example, when the read voltage is about 0.5 V, a ternary memory can be implemented. Before change to each state, a voltage of −2 V is applied to the lower electrode layer6203to return the state to the high resistance state (reset).

A case wherein the ferroelectric layer104of the element shown inFIG. 1is formed at room temperature (about 20° C. to 24° C.) will be described next. The lower electrode layer103is made of Pt—Ti. In a thus formed element, when a voltage from a power supply was applied between the lower electrode layer103and the upper electrode105, and a current flowing upon voltage application was measured by an ammeter, a result shown inFIG. 72was obtained. When the applied voltage is raised from 0 V, a positive high resistance mode is obtained first, as indicated by (1) inFIG. 72. When the applied voltage exceeds 1.6 V, an abrupt current flow is measured, as indicated by (2). Voltage application is temporarily stopped. When a positive voltage is then applied again, a positive low resistance mode is obtained, as indicated by (3).

When a negative voltage is applied to the upper electrode105in the positive low resistance mode indicated by (3), a negative low resistance mode indicated by (4) is obtained. A negative voltage is applied to the upper electrode105. When the applied voltage exceeds −0.8 V, a transition state indicated by (5) is obtained, and the resistance value abruptly increases. After this state, a negative high resistance mode indicated by (6) is obtained. The states (1) to (6) are repeatedly observed.

When the ferroelectric layer104formed at a low temperature by the same ECR sputtering as described above is observed by a transmission electron microscope, it is confirmed that the entire film is in an amorphous state, as shown in the observation result inFIG. 73. It is also confirmed that a plurality of fine particles having a grain size of about 3 to 10 nm are dispersed in the entire film. However, a portion with a size of about 10 nm can also be regarded as an aggregate of a plurality of finer particles. It is also confirmed that the content of bismuth of the fine particles is larger than titanium or oxygen. This state is a characteristic feature of a metal oxide thin film formed by ECR sputtering and is supposed to be created because migration of atoms in the film surface is promoted as the thin film in the film formation process is irradiated with ECR plasma.

A case wherein the ferroelectric layer104of the element shown inFIG. 1is formed at about 150° C. will be described next. The lower electrode layer103is made of Pt—Ti. The substrate101is made of plastic. In a thus formed element, when a voltage from a power supply was applied between the lower electrode layer103and the upper electrode105(a negative voltage is applied to the upper electrode105), and a current flowing upon voltage application was measured by an ammeter, a result shown inFIG. 74was obtained. First, a negative high resistance mode is obtained, as indicated by (1) inFIG. 74. When the applied voltage exceeds −2 V, an abrupt current flow is measured, as indicated by (2). Voltage application is temporarily stopped. When a positive voltage is then applied, a negative low resistance mode is obtained, as indicated by (3).

When a positive voltage is applied to the upper electrode105in the negative low resistance mode indicated by (3), a positive low resistance mode indicated by (4) is obtained. A positive voltage is applied to the upper electrode105. When the applied voltage exceeds 0.8 V, a transition state indicated by (5) is obtained, and the resistance value abruptly increases. After this state, a positive high resistance mode indicated by (6) is obtained. The states (1) to (6) are repeatedly observed. In the above-described conditions, the ferroelectric layer104is almost transparent. When a transparent material is used for the substrate, and the electrodes are formed as transparent electrodes made of, e.g., ITO, an optically transparent element can be formed.

A case wherein the ferroelectric layer3104of the element shown inFIG. 31is formed at about 450° C. will be described next. The lower electrode layer3103is made of Ru. In a thus formed element, when a voltage from a power supply was applied between the lower electrode layer3103and the upper electrode3106(a negative voltage is applied to the upper electrode3106), and a current flowing upon voltage application was measured by an ammeter, a result shown inFIG. 75was obtained. A negative high resistance mode is obtained first, as indicated by (1) inFIG. 75. When the applied voltage exceeds −3 V, an abrupt current flow is measured, as indicated by (2). When a positive voltage is then applied, a negative low resistance mode is obtained, as indicated by (3).

When a positive voltage is applied to the upper electrode3106in the negative low resistance mode indicated by (3), a positive low resistance mode indicated by (4) is obtained. A positive voltage is applied to the upper electrode3106. When the applied voltage exceeds 9 V, a transition state indicated by (5) is obtained, and the resistance value abruptly increases. After this state, a positive high resistance mode indicated by (6) is obtained. The states (1) to (6) are repeatedly observed.

The data holding characteristic of the element which exhibits the characteristic shown inFIG. 74described above will be described below. As shown inFIG. 76, first, when a positive voltage is applied to the upper electrode3106first in the high resistance mode, a current value of about 10−6A is measured. In this state, when a negative voltage more than −4 V is applied to the upper electrode3106, a low resistance mode is set in which a current of about 2×10−3A flows. According to the above-described element, this low resistance mode has a stability more than 10 years, as is apparent from the extrapolated line inFIG. 76.

A case wherein the ferroelectric layer104of the element shown inFIG. 1is formed at about 430° C. will be described next. The lower electrode layer103is made of Ru. The upper electrode105has an upper layer made of titanium and a lower layer made of platinum. In a thus formed element, when a voltage from a power supply was applied between the lower electrode layer103and the upper electrode105, and a current flowing upon voltage application was measured by an ammeter, a result shown inFIG. 77was obtained. When the applied voltage is raised from 0 V, a positive high resistance mode is obtained first, as indicated by (1) inFIG. 77. When the applied voltage exceeds 2.5 V, an abrupt current flow is measured, as indicated by (2). Voltage application is temporarily stopped. When a positive voltage is then applied again, a positive low resistance mode is obtained, as indicated by (3).

When a negative voltage is applied to the upper electrode105in the positive low resistance mode indicated by (3), a negative low resistance mode indicated by (4) is obtained. A negative voltage is applied to the upper electrode105. When the applied voltage exceeds −1.8 V, a transition state indicated by (5) is obtained, and the resistance value abruptly increases. After this state, a negative high resistance mode indicated by (6) is obtained. The states (1) to (6) are repeatedly observed.

Holding two states in a metal oxide layer such as the above-described ferroelectric layer104or ferroelectric layer3104will be examined next. In a metal oxide layer in which the state shown inFIGS. 7C,7c, and73is observed, since conductive paths7802schematically indicated by solid lines are formed between a plurality of dispersed fine particles7801, as shown inFIG. 78, the low resistance mode is supposed to occur. The conductive path7802is supposed to be formed by quantum tunneling between the nanosized fine particles7801, hopping of holes or electrons, or oxygen defects. In many cases, a plurality of conductive paths7802are formed although only one conductive path7802may also be formed. When a certain number of conductive paths7802are formed, the resistance value between the electrodes to which a voltage is applied decreases, and the low resistance mode shown inFIG. 79is obtained.

As shown inFIG. 80, when the polarity of the applied voltage is changed, some or all conductive paths7802disappear, and the resistance value between the electrodes abruptly increases. As shown inFIG. 81, the low resistance mode changes to the high resistance mode. When a voltage to just flow a current between the electrodes is applied in this high resistance mode, the plurality of conductive paths7802are formed again, as shown inFIG. 82. Hence, a current abruptly flows, and the mode changes to the low resistance mode, as shown inFIG. 83.

In the above-described example, switching between the high resistance state and the low resistance state is done by applying voltages with different polarities. However, the present invention is not limited to this. Switching between the high resistance state and the low resistance state can also be done by applying different voltages with the same polarity, as will be described below. In the following case, the metal oxide layer is formed at 450° C. For example, as shown inFIG. 84, when a voltage more than −3.5 V is applied to the upper electrode in a negative low resistance state indicated by (1), an abrupt current flow is generated, as indicated by (2). When a negative voltage is then applied again, a negative low resistance state indicated by (3) is obtained and maintained.

When a negative voltage more than −1 V is applied in the negative low resistance state, transition occurs, and the state changes to a negative high resistance state indicated by (5). At a voltage of −3.5 V or less, this state is maintained. When a voltage more than −3.5 V is applied, an abrupt current flow indicated by (6) occurs, and the state changes to a negative low resistance state. If the direction of the applied voltage (the electrode to which the voltage is applied) is changed, the same state as described above can be obtained except that the above-described voltages have positive values.

Pulse driving can also be executed by applying voltages with the same polarity. When the state of the element is confirmed at an observation voltage of −0.1 V, the element is in a high resistance state with a current of about 10−8A, as shown inFIG. 85. Even when the measurement is executed four times at the observation voltage of −0.1 V, the high resistance state is maintained. In this state, a pulse voltage of −5.0 V having a width of 500 μsec is applied once, as indicated by hollow arrows, and measurement is done at the observation voltage of −0.1 V. A current of about 10−4A is measured. That is, a low resistance mode is set. Even when the measurement is executed four times at the observation voltage of −0.1 V, the low resistance state is maintained. In this state, a pulse voltage of 3.0 V having a width of 1 μsec is applied 10 times, as indicated by solid arrows, and measurement is done at the observation voltage of −0.1 V. A current of about 10−9A is measured. That is, a high resistance mode is set. When appropriate pulse voltages are applied in a similar way, the high and low resistance states are repeatedly observed.

Still another embodiment of the present invention will be described below with reference to the accompanying drawings.FIGS. 86A and 86Bare schematic sectional views schematically showing a structure example of a 3-terminal element according to an embodiment of the present invention. The 3-terminal element shown inFIGS. 86A and 86Bcomprises, on a substrate8601made of, e.g., single-crystal silicon, an insulating layer8602, a gate electrode8603, a metal oxide layer8604containing Bi, Ti, and O and having a thickness of about 10 to 200 nm, a source electrode8605, and a drain electrode8606. In the 3-terminal element having the above-described structure, a state wherein a potential is applied as shown inFIG. 86Awill be defined as a write state, and a state wherein a potential is applied as shown inFIG. 86Bwill be defined as a read state.

The substrate8601can be made of any one of a semiconductor, insulator, and conductive material such as a metal. When the substrate8601is made of an insulating material, the insulating layer8602can be omitted. When the substrate8601is made of a conductive material, the insulating layer8602and gate electrode8603can be omitted. In this case, the substrate8601made of the conductive material serves as a gate electrode. The gate electrode8603, source electrode8605, and drain electrode8606need only be made of a transition metal including noble metals such as platinum (Pt), ruthenium (Ru), gold (Au), and silver (Ag). The electrodes may be made of a compound such as a nitride, oxide, or fluoride of a transition metal, such as titanium nitride (TiN), hafnium nitride (HfN), strontium ruthenate (SrRuO2), zinc oxide (ZnO), indium tin oxide (ITO), or lanthanum fluoride (LaF3), or a composite film formed by stacking them.

A detailed example of the structure of the 3-terminal element shown inFIGS. 86A and 86Bwill be described. For example, the gate electrode8603is a ruthenium film having a thickness of 10 nm. The metal oxide layer8604is made of a metal oxide containing Bi and Ti and having a thickness of 40 nm. The source electrode8605and drain electrode8606are made of gold. The metal oxide layer8604have the same properties as those of the above-described ferroelectric layer104, ferroelectric layer3104, ferroelectric layer4705, and metal oxide layer6205, including the state of the layer, the electrical characteristics, and the viewpoint of electrical orientation. The interval between the source electrode8605and the drain electrode8606is, e.g., 1 mm. As described above, the structures of the substrate8601and insulating layer8602are not limited to those described above, and any other material can also be selected appropriately if it has no effect on the electrical characteristics.

The metal oxide layer8604included in the 3-terminal element according to the present invention will be described next in more detail. Like the above-described ferroelectric layer104or metal oxide layer6205, the metal oxide layer8604is formed by dispersing a plurality of microcrystalline grains or fine particles of Bi4Ti3O12crystal with a grain size of about 3 to 15 nm in a base layer, i.e., a layer containing titanium in an excessive amount relative to the stoichiometric composition of Bi4Ti3O12. The base layer may be TiOxwith a bismuth content of almost 0. In other words, the base layer is made of a metal oxide which contains two metals and in which the content of one metal is smaller in comparison with the stoichiometric composition.

According to the 3-terminal element using the metal oxide layer8604, two states (ON and OFF) can be held, as will be described below. The characteristics of the 3-terminal element shown inFIGS. 86A and 86Bwill be described. The characteristics were investigated by applying a voltage between the gate electrode8603and the source electrode8605and drain electrode8606. When a voltage from a power supply was applied between the gate electrode8603and the source electrode8605and drain electrode8606, and a current flowing from the gate electrode8603to the source electrode8605and drain electrode8606was measured by an ammeter, a result shown inFIG. 86Cwas obtained. Referring toFIG. 86C, the ordinate represents the value of a current whose positive direction is set to the direction from the gate electrode8603to the source electrode8605and drain electrode8606.

FIG. 86Cand the operation principle of the 3-terminal element of the present invention will be described below. The voltage values and current values to be described here are mere examples measured in an actual element. Hence, the phenomenon is not limited to the following numerical values. Other numerical values can also be measured depending on the material and thickness of each film actually used in the element and other conditions.

FIG. 86Cshows the hysteresis characteristics of the values of currents which flow in the metal oxide layer8604when the voltage (gate voltage) applied to the gate electrode8603is decreased from 0 in the negative direction, returned to 0, increased in the positive direction, and finally returned to 0 again. When the gate voltage applied to the gate electrode8603is gradually decreased from 0 V in the negative direction, the negative current flowing in the metal oxide layer8604is relatively small (about −0.12 mA at −0.1 V).

When the voltage exceeds −0.4 V, the negative current value starts increasing. After the voltage is decreased up to about −1 V, the negative voltage is decreased. The negative current value decreases while keeping the state wherein a negative current having a larger absolute value than before flows. At this time, the current value is about −0.63 mA at −0.1 V. The resistance value is lower by about five times than the previous state, and the current readily flows. When the applied gate voltage is returned to 0, the current value also becomes 0.

Next, a positive gate voltage is applied to the gate electrode8603. In this state, when the positive gate voltage is low, a relatively large positive current flows according to the previous hysteresis (about 0.63 mA at 0.1 V). When the positive gate voltage is applied up to about 0.7 V, the positive current suddenly decreases. Finally, the applied positive gate voltage is decreased from +1 V to 0 V, the positive current value also decreases while keeping the hardly current flowing state and returns to 0. At this time, the positive current is about 0.12 mA at 0.1 V.

The above-described hysteresis of the current flowing in the metal oxide layer8604can be regarded as being generated because the resistance value of the metal oxide layer8604changes depending on the gate voltage applied to the gate electrode8603. When a negative gate voltage VW1with a predetermined magnitude or more is applied, the metal oxide layer8604changes to a “low resistance state” (ON state) wherein the current easily flows. When a positive gate voltage VW0with a predetermined magnitude is applied, the metal oxide layer8604changes to a “high resistance state” (OFF state) wherein the current hardly flows.

The metal oxide layer8604has the two stable states, i.e., low resistance state and high resistance state. The ON or OFF state remains unless the above-described positive or negative gate voltage with a predetermined magnitude or more is applied. The value of VW0described above is about +1 V. The value of VW1is about −1 V. The resistance ratio of the high resistance state to the low resistance state is about 10 to 100. When the above-described phenomenon that the resistance of the metal oxide layer8604is switched by the gate voltage is used, a nonvolatile functional element capable of a nondestructive read operation can be implemented by the 3-terminal element shown inFIGS. 86A and 86B.

A case wherein the 3-terminal element shown inFIGS. 86A and 86Bis operated by using a DC voltage will be described next. First, a negative gate voltage equal to or higher than the low resistance transition voltage VW1is applied to change the metal oxide layer8604to the low resistance state. An ON state wherein a current readily flows between the source and drain is obtained. The ON state can be read out by measuring a current value JR1between the source and drain at a read voltage VR. It is important to select, as the read voltage VR, such a small value to obtain a sufficient resistance ratio and not to cause state transition (about 0.1 V in the above example). Hence, the read can be done many times without destroying the low resistance state, i.e., ON state.

On the other hand, when a positive gate voltage equal to or higher than the high resistance transition voltage VW0is applied, the metal oxide layer8604changes to the high resistance state, i.e., OFF state wherein a current hardly flows between the source and drain. The OFF state can also be read out by measuring a current value JR0between the source and drain at the read voltage VR(JR1/JR0≈10 to 100). When the electrodes are not energized, the metal oxide layer8604has nonvolatility to hold each state. Except in the write and read, no voltage need be applied. This element can also be used as a switching element to control the current.

A change in current (source-drain current) which flows between the source electrode8605and the drain electrode8606when different voltages are applied by the gate electrode8603will be described. As shown inFIG. 87, after a gate voltage of +1 V is applied to set the OFF state, the source-drain current rarely flows when the read voltage applied between the source and drain falls within the range of 0 to 0.15 V. On the other hand, when a gate voltage of −1 V is applied to set the ON state, and the read voltage applied between the source and drain is raised from 0 V to 0.15 V, the source-drain current flows in a larger amount almost in proportion to the increase in read voltage. In the ON state, a source-drain current of about 0.5 mA is measured at 0.15 V. As described above, according to the 3-terminal element shown inFIGS. 86A and 86B, the source-drain current can be controlled by the gate voltage.

When a positive or negative gate voltage is applied only once, the state changes to a corresponding ON or OFF state, and the state is maintained, as shown inFIG. 88.FIG. 88shows a change in current flowing between the source and drain when a voltage of +1 V or −1 V is applied to the gate electrode8603, and a read voltage of 0.15 V is then applied between the source electrode8605and the drain electrode8606.

A case wherein the source electrode8605is set open, and in this state, a gate voltage is applied to set the ON or OFF state will be described. In this case, the gate voltage is applied between the gate electrode8603and the drain electrode8606. The state is read out by applying a read voltage up to 0.2 V between the source electrode8605and the drain electrode8606and, in this state, measuring a current flowing between the source and drain.

As shown inFIG. 89, a gate voltage of +1 V is applied to set the OFF state. After that, the read voltage applied between the source and drain is increased from 0 V to 0.2 V. Then, a current to some extent flows between the source and drain. At a read voltage of 0.2 V, a current of about 0.1 mA flows between the source and drain. To the contrary, a gate voltage of −1 V is applied to set the ON state. After that, the read voltage applied between the source and drain is increased from 0 V to 0.2 V. Then, a larger source-drain current flows almost in proportion to the increase in read voltage. In the ON state, a source-drain current of about 0.4 mA is measured at a read voltage of 0.2 V. Hence, even when the source electrode8605is set open, and the gate voltage is applied in this state, the 3-terminal element shown inFIGS. 86A and 86Bcan perform the ON/OFF operation.

However, in the case wherein the source electrode8605is set open, and in this state, a gate voltage is applied to set the OFF state, when the read voltage is increased, a current to some extent flows between the source and drain, as described above. When the source electrode8605is set open, and the gate voltage is applied in this state, the applied voltage selectively acts depending on the region under the drain electrode8606. The above-described result is supposed to be observed for this reason. As can be seen from this result, the source-drain current is supposed to flow through a path formed from the source electrode8605, the metal oxide layer8604in the region under the source electrode8605, the gate electrode8603, the metal oxide layer8604in the region under the drain electrode8606, and the drain electrode8606.

As for the holding characteristic of the ON and OFF states in the 3-terminal element shown inFIGS. 86A and 86B, a holding time of at least 1,000 min is ensured, like the above-described element shown inFIG. 1. In the above description, the applied gate voltage is a DC voltage. However, the same effect can be obtained even by applying a pulse voltage having appropriate width and magnitude.

An example of a method of manufacturing the 3-terminal element shown inFIGS. 86A and 86Bwill be described next. A method of forming each thin film by using ECR plasma sputtering will be described below. However, the present invention is not limited to this, and any other film formation technique or method can be used, as a matter of course.

As shown inFIG. 90A, the p-type silicon substrate8601having a plane orientation of (100) on the principal plane and a resistivity of 1 to 2 Ωcm is prepared. The surface of the substrate8601is cleaned by a solution mixture of sulfuric acid and a hydrogen peroxide solution, pure water, and a hydrogen fluoride solution and dried. The insulating layer8602is formed on the cleaned and dried substrate8601. In forming the insulating layer8602, e.g., an ECR sputtering apparatus and pure silicon (Si) as a target are used. The insulating layer8602in a metal mode by Si—O molecules is formed on the silicon substrate8601to a thickness to just cover its surface by ECR sputtering using argon (Ar) as a plasma gas and oxygen gas.

For example, Ar gas is supplied at a flow rate of 20 sccm into a plasma production chamber whose internal pressure is set on the order of 10−5Pa. The internal pressure is set to about 10−3to 10−2Pa. A magnetic field of 0.0875 T and a microwave of 2.45 GHz (about 500 W) are supplied to set the electron cyclotron resonance condition, thereby producing Ar plasma in the plasma production chamber. Note that sccm is the unit of flow rate and indicates that a fluid at 0° C. and 1 atmospheric pressure flows 1 cm3in 1 min. T (tesla) is the unit of magnetic flux density, and 1 T=10,000 gauss.

The plasma produced by the above-described method is output from the plasma production chamber to the process chamber side by the divergent magnetic field of the magnetic coil. In addition, a high-frequency power of 13.56 MHz (e.g., 500 W) is supplied from a high-frequency power supply to the silicon target placed at the outlet of the plasma production chamber. When Ar ions collide against the silicon target, a sputtering phenomenon occurs to sputter Si particles. The Si particles sputtered from the silicon target reach the surface of the silicon substrate8601together with the plasma output from the plasma production chamber and the oxygen gas which is supplied and activated by the plasma and are oxidized to silicon dioxide by the activated oxygen. With the above process, the insulating layer8602made of silicon dioxide and having a thickness of, e.g., about 100 nm can be formed on the substrate8601(FIG. 90A).

The insulating layer8602ensures insulation to prevent a voltage from leaking to the substrate8601and influencing desired electrical characteristics when a voltage is applied between the electrodes to be formed later. For example, a silicon oxide film formed by oxidizing the surface of the silicon substrate by thermal oxidation may be used as the insulating layer8602. The insulating layer8602may be made of any other insulating material except silicon oxide if the insulating properties can be ensured. The thickness of the insulating layer8602need not always be 100 nm and may be smaller or larger. In the above-described formation of the insulating layer8602by ECR sputtering, the substrate8601is not heated. However, the film may be formed while heating the substrate8601.

After the insulating layer8602is formed in the above-described manner, a ruthenium film is formed on the insulating layer8602by similar ECR sputtering using pure ruthenium (Ru) as a target, thereby forming the gate electrode8603, as shown inFIG. 90B. Formation of the Ru film will be described in detail. In an ECR sputtering apparatus using a Ru target, for example, the silicon substrate with the insulating layer formed on it is heated to 400° C. Ar gas as a rare gas is supplied into the plasma production chamber at a flow rate of, e.g., 7 sccm. In addition, Xe gas is supplied at a flow rate of, e.g., 5 sccm to set the internal pressure of the plasma production chamber to on the order of, e.g., 10−2to 10−3Pa.

The magnetic field of the electron cyclotron resonance condition is given to the plasma production chamber. Then, a microwave of 2.45 GHz (about 500 W) is supplied into the plasma production chamber to produce ECR plasma of Ar and Xe in it. The produced ECR plasma is output from the plasma production chamber to the process chamber side by the divergent magnetic field of the magnetic coil. In addition, a high-frequency power of 13.56 MHz (e.g., 500 W) is supplied to the ruthenium target placed at the outlet of the plasma production chamber. The sputtering phenomenon occurs to sputter Ru particles from the ruthenium target. The Ru particles sputtered from the ruthenium target reach the surface of the insulating layer8602on the substrate8601and are deposited.

With the above process, the gate electrode8603having a thickness of, e.g., about 10 nm can be formed on the insulating layer8602(FIG. 90B). The gate electrode8603enables voltage application to the metal oxide layer8604when a voltage is applied between the source electrode8605and drain electrode8606to be formed later. The gate electrode8603may be made of any other material except ruthenium if the conductivity can be ensured. The gate electrode8603may be made of, e.g., platinum. A platinum film formed on silicon dioxide readily peels off, as is known. To prevent this, a layered structure is formed by inserting a titanium layer, titanium nitride layer, or ruthenium layer under the platinum layer. The thickness of the gate electrode8603need not always be 10 nm and may be smaller or larger.

As described above, in forming the Ru film by ECR sputtering, the substrate8601is heated to 400° C. However, the substrate need not always be heated. However, if the substrate is not heated, the adhesion of ruthenium to silicon dioxide becomes low, and the film may peel off. To prevent peeling, the film is formed preferably while heating the substrate.

After the gate electrode8603is formed in the above-described manner, the metal oxide layer8604is formed on the gate electrode8603to a thickness to just cover its surface, as shown inFIG. 90C, by ECR sputtering using argon (Ar) as a plasma gas and oxygen gas and a target formed from an oxide sintered body (Bi—Ti—O) in which the ratio of Bi to Ti is 4:3.

Formation of the metal oxide layer8604will be described in detail. The substrate8601is heated to 300° C. to 700° C. Ar gas as a rare gas is supplied into the plasma production chamber at a flow rate of, e.g., 20 sccm to set the pressure on the order of, e.g., 10−3to 10−2Pa. In this state, the magnetic field of the electron cyclotron resonance condition is given to the plasma production chamber. Then, a microwave of 2.45 GHz (about 500 W) is supplied into the plasma production chamber to produce ECR plasma in it.

The produced ECR plasma is output from the plasma production chamber to the process chamber side by the divergent magnetic field of the magnetic coil. In addition, a high-frequency power of 13.56 MHz (e.g., 500 W) is supplied to the sintered body target placed at the outlet of the plasma production chamber. When Ar particles collide against the sintered body target, the sputtering phenomenon occurs to sputter Bi particles and Ti particles.

The Bi particles and Ti particles sputtered from the sintered body target reach the surface of the heated gate electrode8603together with the ECR plasma output from the plasma production chamber and the oxygen gas activated by the output ECR plasma and are oxidized by the activated oxygen. The oxygen (O2) gas serving as a reactive gas is supplied at a flow rate of, e.g., 1 sccm separately from the Ar gas, as will be described later. Although the sintered body target contains oxygen, any shortage of oxygen in the deposited film can be prevented by supplying oxygen. With the above-described film formation by ECR sputtering, the metal oxide layer8604having a thickness of, e.g., about 40 nm can be formed (FIG. 90C).

The film quality may be improved by irradiating the formed metal oxide layer8604with ECR plasma of an inert gas and a reactive gas. As the reactive gas, not oxygen gas but nitrogen gas, fluorine gas, or hydrogen gas can be used. The film quality improvement can also be applied to formation of the insulating layer8602. The metal oxide layer8604may be formed at a low substrate temperature of 300° C. or less and then annealed (heat-treated) in an appropriate gas atmosphere such as oxygen atmosphere to greatly improve the properties of the film.

After the metal oxide layer8604is formed in the above-described way, the source electrode8605and drain electrode8606each made of Au and having a predetermined area are formed on the metal oxide layer8604, as shown inFIG. 90D, thereby obtaining the 3-terminal element shown inFIGS. 86A and 86B. The source electrode8605and drain electrode8606can be formed by a well-known lift-off method and gold deposition by resistance heating vacuum deposition. The source electrode8605and drain electrode8606may be made of another metal material or conductive material such as Ru, Pt, or TiN. When Pt is used, the adhesion is poor, and the film may peel off. Hence, each electrode must be formed as an electrode with a predetermined area by using a structure such as Ti—Pt—Au that hardly peels off and executing a patterning process such as photolithography or lift-off on that structure.

The above-described layer formation by ECR sputtering is done by using an ECR sputtering apparatus shown inFIG. 89.

The 3-terminal element according to this embodiment is not limited to the structure example shown inFIGS. 86A and 86B. For example, as shown inFIG. 91, a source electrode8615and drain electrode8616may be formed on the insulating layer8602and covered with the metal oxide layer8604, and a gate electrode8613may be formed on the metal oxide layer8604. As shown inFIGS. 92A and 92B, an insulating substrate8601amay be used, as a matter of course. In this case, the insulating layer8602can be omitted. Alternatively, the structure including the metal oxide layer8604, source electrode8605, and drain electrode8606shown inFIGS. 86A and 86Bmay be arranged on a conductive substrate. In this case, the substrate also serves as a gate electrode.

In the above-described example, the single-crystal silicon substrate8601is used. However, an insulating substrate made of glass or quartz may be used. With this structure, the present invention can be applied to, e.g. a glass substrate easy to process. The metal oxide layer8604which has a refractive index of about 2.6 measured at a wavelength of 632.8 nm is optically transparent. For this reason, when a transparent substrate is used, the 3-terminal element of this embodiment can be applied to a display. When the metal oxide layer8604is formed so thick in the range of 10 to 200 nm that an interference color is generated, the visual effect of a colored state can be obtained.

As the metal oxide layer becomes thick, the current flows more hardly, and the resistance increases. When a 3-terminal element is implemented by using a change in resistance value, the resistance value of in each of the low resistance state and high resistance state is important. For example, when the metal oxide layer becomes thick, the resistance value in the low resistance state increases. Since it is difficult to ensure a high S/N ratio, the ON or OFF state is hard to determine. On the other hand, when the metal oxide layer becomes thin, and the leakage current is dominant, the ON or OFF state can hardly be held, and the resistance value in the high resistance state decreases. It is therefore difficult to ensure a high S/N ratio.

Hence, the metal oxide layer preferably has an optimum thickness. For example, when the problem of leakage current is taken into consideration, the metal oxide layer need only have a thickness of at least 10 nm. When the resistance value in the low resistance state is taken into consideration, the metal oxide layer is preferably thinner than 300 nm. In experiments conducted by the present inventors, the operation of the 3-terminal element was confirmed when the thickness of the metal oxide layer was 30 to 200 nm.

In the above description, one metal oxide element has been exemplified. However, a plurality of 3-terminal elements may be arrayed and integrated in a cross-point pattern, as will be described later. In the example shown in the sectional view ofFIG. 93Aand the plan view ofFIG. 93B, word lines9303serving as gate electrodes are arranged on an insulating layer9302on a substrate9301. Island-shaped metal oxide layers9304arrayed at a predetermined interval are arranged on the word lines9303. A plurality of source electrodes9305and drain electrodes9306are arrayed on each metal oxide layer9304. In addition, plate lines9315are commonly connected to the source electrodes9305arrayed in a direction perpendicular to the word lines9303. Bit lines9316are commonly connected to the arrayed drain electrodes9306. As described above, the 3-terminal elements according to this embodiment can be integrated. InFIGS. 93A and 93B, the metal oxide layers9304are spaced apart from each other to reduce interference between the plate lines or bit lines. However, the present invention is not limited to this. An integrated metal oxide layer may be formed.

According to the 3-terminal element shown inFIGS. 86A and 86B, a multilevel operation is also possible. For example, in the current-voltage characteristic of the metal oxide layer8604when a DC gate voltage is applied to the gate electrode8603, when the applied gate voltage is changed, the low resistance state changes to a different low resistance state, as shown inFIG. 94. InFIG. 94, the current value at the read voltage shown inFIG. 94changes between the low resistance state after a voltage up to −0.5 V is applied, the low resistance state after a voltage up to −1.0 V is applied, and the low resistance state after a voltage up to −1.5 V is applied. These states can be read out by applying a read voltage between the source and drain and measuring a current flowing between the source and drain. Three states (three values) “0”, “1”, and “2” can be implemented in correspondence with the source-drain currents obtained by a predetermined read voltage.

According to the element shown inFIGS. 86A and 86B, a multilevel state can be implemented by the difference in pulse voltage value. As shown inFIG. 95, every time a predetermined pulse voltage with a predetermined pulse width is applied a predetermined number of times, the current value between the source and drain is read out at a read voltage of 0.2 V at a point indicated by a triangle. Then, as shown inFIG. 96, three states (three values) “0”, “1”, and “2” are obtained. In this example, the memory is reset by the state “2”.

Still another embodiment of the present invention will be described below with reference to the accompanying drawings.FIGS. 97A and 97Bare schematic sectional views schematically showing a structure example of a 3-terminal element according to another embodiment of the present invention. The 3-terminal element shown inFIGS. 97A and 97Bcomprises, on a substrate9701made of, e.g., single-crystal silicon, an insulating layer9702, a gate electrode9703, a metal oxide layer9704containing Bi, Ti, and O and having a thickness of about 30 to 200 nm, a source electrode9706, a drain electrode9707. In addition, an insulating layer9705is provided between the gate electrode9703and the metal oxide layer9704. In the 3-terminal element having the above-described structure, a state wherein a potential is applied as shown inFIG. 97Awill be defined as a write state, and a state wherein a potential is applied as shown inFIG. 97Bwill be defined as a read state.

The substrate9701can be made of any one of a semiconductor, insulator, and conductive material such as a metal. When the substrate9701is made of an insulating material, the insulating layer9702can be omitted. When the substrate9701is made of a conductive material, the insulating layer9702and gate electrode9703can be omitted. In this case, the substrate9701made of the conductive material serves as a gate electrode. The gate electrode9703, source electrode9706, and drain electrode9707need only be made of a transition metal including noble metals such as platinum (Pt), ruthenium (Ru), gold (Au), silver (Ag), and titanium (Ti). The electrodes may be made of a compound such as a nitride, oxide, or fluoride of a transition metal, such as titanium nitride (TiN), hafnium nitride (HfN), strontium ruthenate (SrRuO2), zinc oxide (ZnO), indium tin oxide (ITO), or lanthanum fluoride (LaF3), or a composite film formed by stacking them.

The insulating layer9705need only be made of silicon dioxide, silicon oxynitride, alumina, an oxide such as LiNbO3containing a light metal such as lithium, beryllium, magnesium, or calcium, or a fluoride such as LiCaAlF6, LiSrAlF6, LiYF4, LiLuF4, or KMgF3. Alternatively, the insulating layer9705need only be made of an oxide or nitride of a transition metal such as scandium, titanium, strontium, yttrium, zirconium, hafnium, tantalum, or lanthanum series, a silicate (ternary compound of a metal, silicon, and oxygen) containing the above-described elements, an aluminate (ternary compound of a metal, aluminum, and oxygen) containing these elements, or an oxide or nitride containing at least two of the above elements.

Like the above-described ferroelectric layer104and the like, the metal oxide layer9704is formed by dispersing a plurality of microcrystalline grains and fine particles including a Bi4Ti3O12crystal and a part excessively containing bismuth and having a grain size of about 3 to 15 nm in a base layer, i.e., a layer containing titanium in an excessive amount relative to the stoichiometric composition of Bi4Ti3O12. This is confirmed by observation using a transmission electron microscope. The base layer may be TiOxwith a bismuth content of almost 0. In other words, the base layer is made of a metal oxide which contains two metals and in which the content of one metal is smaller in comparison with the stoichiometric composition.

A detailed example of the 3-terminal element shown inFIGS. 97A and 97Bwill be described. For example, the gate electrode9703is a ruthenium film having a thickness of 10 nm. The metal oxide layer9704is made of a metal oxide with the above-described composition and has a thickness of 40 nm. The insulating layer9705is a multilayered film made of tantalum pentoxide and silicon dioxide and having a thickness of 5 nm. The source electrode9706and drain electrode9707are made of gold. The source electrode9706and drain electrode9707may have a multilayered structure formed by stacking a titanium layer, titanium nitride layer, and gold layer in this order sequentially from the side of the metal oxide layer9704. When the contact surface to the metal oxide layer9704is formed from a titanium layer, the adhesion can be increased. The interval between the source electrode9706and the drain electrode9707is, e.g., 1 mm. As described above, the structures of the substrate9701and insulating layer9702are not limited to those described above, and any other material can also be selected appropriately if it has no effect on the electrical characteristics.

A detailed method of forming the above-described insulating layer9702, gate electrode9703, insulating layer9705, metal oxide layer9704, source electrode9706, and drain electrode9707will be described later. They can be formed by sputtering a metal target or sintered target in ECR plasma made of argon gas, oxygen gas, or nitrogen gas by using an ECR sputtering apparatus shown inFIG. 5.

An example of a method of manufacturing the 3-terminal element shown inFIGS. 97A and 97Bwill be described next with reference toFIG. 98. As shown inFIG. 98A, the p-type silicon substrate9701having a plane orientation of (100) on the principal plane and a resistivity of 1 to 2 Ωcm is prepared. The surface of the substrate9701is cleaned by a solution mixture of sulfuric acid and a hydrogen peroxide solution, pure water, and a hydrogen fluoride solution and dried. The insulating layer9702is formed on the cleaned and dried substrate9701. In forming the insulating layer9702, the above-described ECR sputtering apparatus and pure silicon (Si) as a target are used. The insulating layer9702in a metal mode by Si—O molecules is formed on the silicon substrate9701to a thickness to just cover its surface by ECR sputtering using argon (Ar) as a plasma gas and oxygen gas.

For example, Ar gas is supplied at a flow rate of 20 sccm into a plasma production chamber whose internal pressure is set on the order of 10−5Pa. The internal pressure is set to about 10−3to 10−2Pa. A magnetic field of 0.0875 T and a microwave of 2.45 GHz (about 500 W) are supplied to set the electron cyclotron resonance condition, thereby producing Ar plasma in the plasma production chamber. Note that sccm is the unit of flow rate and indicates that a fluid at 0° C. and 1 atmospheric pressure flows 1 cm3in 1 min.

The plasma produced by the above-described method is output from the plasma production chamber to the process chamber side by the divergent magnetic field of the magnetic coil. In addition, a high-frequency power of 13.56 MHz (e.g., 500 W) is supplied from a high-frequency power supply to the silicon target placed at the outlet of the plasma production chamber. When Ar ions collide against the silicon target, a sputtering phenomenon occurs to sputter Si particles. The Si particles sputtered from the silicon target reach the surface of the silicon substrate9701together with the plasma output from the plasma production chamber and the oxygen gas which is supplied and activated by the plasma and are oxidized to silicon dioxide by the activated oxygen. With the above process, the insulating layer9702made of silicon dioxide and having a thickness of, e.g., about 100 nm can be formed on the substrate9701(FIG. 98A).

The insulating layer9702ensures insulation to prevent a voltage from leaking to the substrate9701and influencing desired electrical characteristics when a voltage is applied between the electrodes to be formed later. For example, a silicon oxide film formed by oxidizing the surface of the silicon substrate by thermal oxidation may be used as the insulating layer9702. The insulating layer9702may be made of any other insulating material except silicon oxide if the insulating properties can be ensured. The thickness of the insulating layer9702need not always be 100 nm and may be smaller or larger. In the above-described formation of the insulating layer9702by ECR sputtering, the substrate9701is not heated. However, the film may be formed while heating the substrate9701.

After the insulating layer9702is formed in the above-described manner, a ruthenium film is formed on the insulating layer9702by similar ECR sputtering using pure ruthenium (Ru) as a target, thereby forming the gate electrode9703, as shown inFIG. 98B. Formation of the Ru film will be described in detail. In an ECR sputtering apparatus using a Ru target, for example, the silicon substrate with the insulating layer formed on it is heated to 400° C. Ar gas as a rare gas is supplied into the plasma production chamber at a flow rate of, e.g., 7 sccm. In addition, Xe gas is supplied at a flow rate of, e.g., 5 sccm to set the internal pressure of the plasma production chamber to on the order of, e.g., 10−2to 10−3Pa.

The magnetic field of the electron cyclotron resonance condition is given to the plasma production chamber. Then, a microwave of 2.45 GHz (about 500 W) is supplied into the plasma production chamber to produce ECR plasma of Ar and Xe in it. The produced ECR plasma is output from the plasma production chamber to the process chamber side by the divergent magnetic field of the magnetic coil. In addition, a high-frequency power of 13.56 MHz (e.g., 500 W) is supplied to the ruthenium target placed at the outlet of the plasma production chamber. The sputtering phenomenon occurs to sputter Ru particles from the ruthenium target. The Ru particles sputtered from the ruthenium target reach the surface of the insulating layer9702on the substrate9701and are deposited.

With the above process, the gate electrode9703having a thickness of, e.g., about 10 nm can be formed on the insulating layer9702(FIG. 98B). The gate electrode9703enables voltage application to the metal oxide layer9704when a voltage is applied between the gate electrode9703and the source electrode9706and drain electrode9707to be formed later. The gate electrode9703may be made of any other material except ruthenium if the conductivity can be ensured. The gate electrode9703may be made of, e.g., platinum. A platinum film formed on silicon dioxide readily peels off, as is known. To prevent this, a layered structure is formed by inserting a titanium layer, titanium nitride layer, or ruthenium layer under the platinum layer. The thickness of the gate electrode9703need not always be 10 nm and may be smaller or larger.

As described above, in forming the Ru film by ECR sputtering, the substrate9701is heated to 400° C. However, the substrate need not always be heated. However, if the substrate is not heated, the adhesion of ruthenium to silicon dioxide becomes low, and the film may peel off. To prevent peeling, the film is formed preferably while heating the substrate.

After the gate electrode9703is formed in the above-described manner, the substrate9701is unloaded from the apparatus to the atmosphere. The substrate9701is fixed on the substrate holder of the same ECR sputtering apparatus as inFIG. 5in which pure tantalum (Ta) is used as the target. The insulating layer9705is formed on the gate electrode9703to a thickness to just cover its surface, as shown inFIG. 98C, by ECR sputtering using argon (Ar) as a plasma gas and oxygen gas. A metal mode film by Ta—O molecules is formed as the insulating layer9705, as will be described below.

Formation of a metal mode film by Ta—O molecules will be described in detail. In the ECR sputtering apparatus shown inFIG. 5in which the target made of tantalum is used, Ar gas as a rare gas is supplied at a flow rate of, e.g., 25 sccm from the inert gas supply unit into the plasma production chamber to set its internal pressure on the order of, e.g., 10−3Pa. A coil current of, e.g., 28 A is supplied to the magnetic coil to give the magnetic field of the electron cyclotron resonance condition to the plasma production chamber.

A microwave of, e.g., 2.45 GHz (e.g., 500 W) is supplied from the microwave generation unit (not shown) into the plasma production chamber through the waveguide, quartz window, and vacuum waveguide. With this supply of the microwave, Ar plasma is produced in the plasma production chamber. The produced plasma is output from the plasma production chamber to the side of the process chamber by the divergent magnetic field of the magnetic coil. In addition, a high-frequency power (e.g., 500 W) is supplied from the high-frequency electrode supply unit to the target placed at the outlet of the plasma production chamber.

When Ar particles collide against the target, a sputtering phenomenon occurs to sputter Ta particles from the target. The Ta particles sputtered from the target reach the surface of the gate electrode9703on the substrate9701together with the plasma output from the plasma production chamber and the oxygen gas which is supplied from the reactive gas supply unit and activated by the plasma and are oxidized to tantalum pentoxide by the activated oxygen.

With the above process, a tantalum pentoxide film is formed on the gate electrode9703. Subsequently, a silicon dioxide film is formed on the tantalum pentoxide film by ECR sputtering using the target made of pure silicon, like silicon dioxide deposition described with reference toFIG. 98A. The above-described formation of a tantalum pentoxide film and silicon dioxide film is repeated to form a multilayered film including the tantalum pentoxide films and silicon dioxide films to, e.g., about 5 nm, thereby obtaining the insulating layer9705(FIG. 98C).

The insulating layer9705including the tantalum pentoxide films and silicon dioxide films is used to control the voltage to be applied to the ferroelectric film upon voltage application to the metal oxide layer9704. The insulating layer9705may have any other structure except the multilayered structure of tantalum pentoxide films and silicon dioxide films if it can control the voltage applied to the metal oxide layer9704. The insulating layer9705may be a single layer. The thickness is not limited to 5 nm, either. In the above-described ECR sputtering, the substrate9701is not heated but may be heated.

After the insulating layer9705is formed in the above-described manner, the metal oxide layer9704is formed on the insulating layer9705to a thickness to just cover its surface, as shown inFIG. 98D, by ECR sputtering using argon (Ar) as a plasma gas and oxygen gas and a target formed from an oxide sintered body (Bi—Ti—O) in which the ratio of Bi to Ti is 4:3.

Formation of the metal oxide layer9704will be described in detail. The substrate9701is heated to 300° C. to 700° C. Ar gas as a rare gas is supplied into the plasma production chamber at a flow rate of, e.g., 20 sccm to set the pressure on the order of, e.g., 10−3to 10−2Pa. In this state, the magnetic field of the electron cyclotron resonance condition is given to the plasma production chamber. Then, a microwave of 2.45 GHz (about 500 W) is supplied into the plasma production chamber to produce ECR plasma in it.

The produced ECR plasma is output from the plasma production chamber to the process chamber side by the divergent magnetic field of the magnetic coil. In addition, a high-frequency power of 13.56 MHz (e.g., 500 W) is supplied to the sintered body target placed at the outlet of the plasma production chamber. When Ar particles collide against the sintered body target, the sputtering phenomenon occurs to sputter Bi particles and Ti particles.

The Bi particles and Ti particles sputtered from the sintered body target reach the surface of the heated insulating layer9705together with the ECR plasma output from the plasma production chamber and the oxygen gas activated by the output ECR plasma and are oxidized by the activated oxygen. The oxygen (O2) gas serving as a reactive gas is supplied at a flow rate of, e.g., 1 sccm separately from the Ar gas, as will be described later. Although the sintered body target contains oxygen, any shortage of oxygen in the deposited film can be prevented by supplying oxygen. With the above-described film formation by ECR sputtering, the metal oxide layer9704having a thickness of, e.g., about 40 nm can be formed (FIG. 98D).

The film quality may be improved by irradiating the formed metal oxide layer9704with ECR plasma of an inert gas and a reactive gas. As the reactive gas, not oxygen gas but nitrogen gas, fluorine gas, or hydrogen gas can be used. The film quality improvement can also be applied to formation of the insulating layer9702. The metal oxide layer9704may be formed at a low substrate temperature of 300° C. or less and then annealed (heat-treated) in an appropriate gas atmosphere such as oxygen atmosphere to greatly improve the properties of the film.

The source electrode9706and drain electrode9707each made of Au and having a predetermined area are formed on the metal oxide layer9704, as shown inFIG. 98E, thereby obtaining the 3-terminal element shown inFIGS. 97A and 97B. The source electrode9706and drain electrode9707can be formed by a well-known lift-off method and gold deposition by resistance heating vacuum deposition. The source electrode9706and drain electrode9707may be made of another metal material or conductive material such as Ru, Pt, or TiN. When Pt is used, the adhesion is poor, and the film may peel off. Hence, each electrode must be formed as an electrode with a predetermined area by using a structure such as Ti—Pt—Au that hardly peels off and executing a patterning process such as photolithography or lift-off on that structure.

The characteristics of the 3-terminal element shown inFIGS. 97A and 97Bwill be described next. The characteristics were investigated by applying a voltage between the gate electrode9703and the drain electrode9707(source electrode9706). When a voltage from a power supply was applied between the gate electrode9703and the drain electrode9707, and a current flowing when the voltage was applied was measured by an ammeter, a result shown inFIG. 33was obtained. As described above, inFIG. 33, the ordinate represents the current density obtained by dividing the current value by the area.FIG. 33and the memory operation principle of the present invention will be described below. The voltage values and current values to be described here are mere examples measured in an actual element. Hence, the phenomenon is not limited to the following numerical values. Other numerical values can also be measured depending on the material and thickness of each film actually used in the element and other conditions.

When a negative voltage is applied to the gate electrode9703, the flowing current is very small up to −0.8 V, as indicated by (1) inFIG. 33. However, as indicated by (2), when the voltage exceeds −0.8 V, a negative current flows abruptly. Actually, a current larger than −15 μA also flows. However, since flowing of a larger current is inhibited to protect the measurement device, the current is not measured. In the range from 0 V to −0.8 V indicated by (1), a high resistance state is held (maintained) by inhibiting flowing of a large current as indicated by (2).

When a negative voltage is applied again to the gate electrode9703, a locus to flow a negative current of −10 μA or more is obtained at −0.5 V, as indicated by (3). When the negative voltage is further applied to the gate electrode9703, a current of −10 μA or more flows at about −0.5 V, as indicated by (3). When a positive voltage is applied to the gate electrode9703, a positive current flows up to about 0.2 V, as indicated by (4). The current increases to 3 μA at maximum. When the absolute value of the voltage is decreased, the current traces a locus indicated by (4).

When the positive voltage is applied up to 0.2 V again, the current traces the locus indicated by (4). After that, as indicated by (5), the value of the flowing current decreases, and no positive current flows. When the positive voltage is further applied to the gate electrode9703, a locus to rarely flow a current is obtained, as indicated by (6). Even when the absolute value of the voltage is decreased then, the current rarely flows, as indicated by (6). When a negative voltage is applied to the gate electrode9703, the current rarely flows up to about 0 to −0.8 V, as indicated by (1). Hence, the high resistance state wherein no current flows as in (1) is maintained unless a voltage of −0.8 V or more is applied to the gate electrode9703to prevent any sudden current flow as in (2). The state (1) will be referred to as a “negative high resistance mode”.

For example, as indicated by (2), when a voltage of −0.8 V or more is applied to the gate electrode9703to abruptly flow a current, a low resistance state in which the current readily flows is obtained, as indicated by (3). This state is also maintained while a negative voltage is applied to the gate electrode9703. The state (3) will be referred to as a “negative low resistance mode”.

However, when a positive voltage is applied to the gate electrode9703, a low resistance state in which the current flows in a positive voltage range from 0 to 0.2 V is obtained, as indicated by (4). This state is also maintained while a positive voltage in the range of 0 to 0.2 V is applied to the gate electrode9703. The state (4) will be referred to as a “positive low resistance mode”.

When a positive voltage of 0.2 V or more is applied to the gate electrode9703, no current flows, and the state changes to a high resistance state, as indicated by (5). In this state, the state wherein the current value has a high resistance is maintained while a positive voltage in the range of 0 to 2 V is applied to the gate electrode9703, as indicated by (6). The state (6) will be referred to as a “positive high resistance mode”.

As described above, the element using the metal oxide layer9704apparently has four stable modes: “positive high resistance mode”, “positive low resistance mode”, “negative high resistance mode”, and “negative low resistance mode”. More specifically, the “positive high resistance mode” and “negative high resistance mode” are “high resistance modes” which exhibit the same high resistance state. The “positive low resistance mode” and “negative low resistance mode” are “low resistance modes” which exhibit the same low resistance state. That is, two modes are present. In the state of the “high resistance mode”, the “high resistance mode” is maintained in the voltage range of −0.8 V to +0.8 V. When a voltage of −0.8 V or more is applied to change the state to the “low resistance mode”, the “low resistance mode” is maintained in the voltage range of −0.5 V to +2.0 V. Switching between the two, “high resistance mode” and “low resistance mode” occurs. This also applied to the negative resistance modes, i.e., “negative high resistance mode” and “negative low resistance mode”.

As for the actual current value in each “negative mode” when a voltage of −0.5 V is applied, the current value in the “negative high resistance mode” is −5×10−8A, and that in the “negative low resistance mode” is −1×10−5A. The ratio is as high as 200 times. This facilitates each mode identification. The present inventors estimate that the above-described phenomenon occurs when the resistance value of the metal oxide layer9704dramatically changes depending on the direction and magnitude of the applied voltage.

Since the insulating layer9705is provided between the metal oxide layer9704and the gate electrode9703, carriers can be controlled by the band structure of the insulating layer9705. More specifically, for example, tantalum pentoxide has a band gap of about 4.5 eV. The energy difference viewed from the Fermi level is about 1.2 eV in the conduction band and 2.3 eV in the valence band. That is, the barrier is higher on the valence band side. Hence, the barrier effect is high for holes in the valence band but low for electrons in the conduction band. For further information, see Wilk et al., “J. Appl. Phys.”, No. 87, p. 484 (2000).

From the above-described characteristic, when, e.g., a tantalum pentoxide film is used as the insulating layer between the electrode and the metal oxide layer, a phenomenon that electrons readily flow but holes hardly flow can be expected. Actually, as shown inFIG. 33, the value of the flowing current largely changes between a case wherein a positive voltage is applied from the drain electrode9707to the gate electrode9703and a case wherein a negative voltage is applied. In discriminating the state of the metal oxide layer9704, this has a large effect to increase the signal-to-noise ratio (S/N ratio) and facilitate data discrimination. This is the effect of use of the insulating layer9705.

It was found that when the above-described “low resistance mode” and “high resistance mode” shown inFIG. 33are applied as a memory operation, the element shown inFIGS. 97A and 97Bcan be used as a nonvolatile nondestructive 3-terminal element. More specifically, the OFF state wherein the current between the source and drain hardly flows is set by applying a positive voltage to the gate electrode9703and a negative voltage to the drain electrode9707to change the mode from the “low resistance mode” to the “high resistance mode”, as indicated by (4) or (5) inFIG. 33.

The shift to the ON state wherein the current between the source and drain readily flows is done by applying a negative voltage to the gate electrode9703and a positive voltage of 1.1 V or more to the drain electrode9707to abruptly flow the current, as indicated by (2) inFIG. 33. With this operation, the mode is changed from the “high resistance mode” to the “low resistance mode”, and the ON state is obtained. As described above, when a voltage is applied to the gate electrode9703(drain electrode9707) to set the “high resistance mode” or “low resistance mode”, switching between the OFF state and the ON state can be done.

The ON/OFF state between the source and drain controlled in the above-described way can easily be recognized by reading a current value when an appropriate voltage of 0 to 1.0 V is applied between the source and drain. For example, when the mode state of the 3-terminal element shown inFIGS. 97A and 97Bis “off”, i.e., “high resistance mode”, it can be determined because a current hardly flows when an appropriate voltage of 0 to 1.0 V is applied, as indicated by (1) inFIG. 33.

When the mode state of the element shown inFIGS. 97A and 97Bis “on”, i.e., “low resistance mode”, it can be determined because a current abruptly flows between the source and drain when an appropriate voltage of 0 to 0.8 V is applied, as indicated by (2) inFIG. 33. Since the difference in current value between the “positive high resistance mode” and the “positive low resistance mode”, i.e., “off” and “on” is 5,000 times or more, “off” and “on” can easily be determined. Even in the negative voltage range, “off” and “on” can be determined in the voltage range of 0 to −0.2 V.

The above-described ON/OFF state of the 3-terminal element can easily be identified only by checking whether the element shown inFIGS. 97A and 97Bis in the “high resistance mode” or “low resistance mode”. In other words, while the 3-terminal element shown inFIGS. 97A and 97Bcan hold the two modes, data is held. Even when a voltage is applied to the electrode to check the mode, the held mode does not change, and data is not destroyed. Hence, according to the 3-terminal element element shown inFIGS. 97A and 97B, a nondestructive operation is possible. The 3-terminal element shown inFIGS. 97A and 97Bfunctions as a 3-terminal element element to control ON/OFF between the source and drain since the resistance value of the metal oxide layer9704changes depending on the voltage applied between the gate electrode9703and the drain electrode9707(or source electrode9706). This element can also be used as an element to control the current.

Even when the source electrode9706is set open, the ON state and OFF state can be controlled by applying a gate voltage. In the case wherein the source electrode9706is set open, when the read voltage is increased, a current to some extent flows between the source and drain even when a gate voltage is applied to set the OFF state. When the source electrode9706is set open, and the gate voltage is applied in this state, the applied voltage selectively acts depending on the region under the drain electrode9707. As described above, a certain source-drain current is supposed to flow when the read voltage is high. Hence, the source-drain current is supposed to flow through a path formed from the source electrode9706, the metal oxide layer9704in the region under the source electrode9706, the gate electrode9703, the metal oxide layer9704in the region under the drain electrode9707, and the drain electrode9707.

The voltage to operate the 3-terminal element shown inFIGS. 97A and 97Bis maximized when a gate voltage to set the “positive low resistance mode” is applied. However, the voltage is about 1.1 V, and the power consumption is very low, as shown inFIG. 33. The low power consumption is very advantageous for devices. Devices using a 3-terminal element, e.g., not only mobile communication devices, digital general-purpose devices, digital image sensing devices, notebook personal computers, and PDAs (Personal Digital Appliances) but also all computers, personal computers, workstations, office computers, mainframes, communication units, and multifunction apparatuses can reduce the power consumption.

FIG. 34shows the time of holding the ON or OFF state in the 3-terminal element shown inFIGS. 97A and 97B. After a negative voltage is applied from the drain electrode9707to the gate electrode9703to set the “negative high resistance state” shown inFIG. 33, i.e., “high resistance mode”, a voltage of 1.1 V or more is applied from the drain electrode9707to the gate electrode9703to set the “positive low resistance state” (“low resistance mode”), i.e., ON state. A voltage of +0.5 V is applied from the drain electrode9707to the gate electrode9703every predetermined time, and the value of a current flowing between the source and drain after voltage application is measured.FIG. 34shows the observation result.

The measured current is maximized about 10 min after and then moderately decreases up to 1,000 min. However, since the current value at this time is 97% of the maximum value, the data can be discriminated without any problem. As is predicted from the extrapolated line of 10,000,000 min corresponding to 10 years shown inFIG. 34, the current value after 10 years corresponding to 66% (⅔) of the maximum value, and the data can discriminated. As is apparent from the above description, the 3-terminal element shown inFIGS. 97A and 97Bcan hold the ON or OFF state for 10 years.

In the above-described example of the present invention, each of the insulating layer on the silicon substrate, the gate electrode layer on the insulating layer, and the metal oxide layer on the gate electrode is formed by ECR sputtering. However, the method of forming each layer is not limited to ECR sputtering. For example, the insulating layer to be formed on the silicon substrate may be formed by thermal oxidation or CVD (Chemical Vapor Deposition) or a conventional sputtering method.

The gate electrode layer may be formed by any other film formation method such as EB deposition, CVD, MBE, or IBD. The metal oxide layer can also be formed by the above-described MOD, conventional sputtering method, PLD, or MOCVD. However, when ECR sputtering is used, flat and excellent insulating film, metal film, and metal oxide film can easily be obtained.

In the above-described embodiment, after each layer is formed, the substrate is temporarily unloaded into the atmosphere. However, the layers may be formed by a continuous process without unloading the structure into the atmospheric by using an apparatus which connects, through vacuum transfer chambers, the process chambers to realize ECR sputtering to form the respective layers. With this arrangement, the substrate to be processed can be transported in vacuum and is therefore prevented from being influenced by disturbance such as water adhesion. Hence, the film quality and interface properties can be improved.

As shown in patent reference 7, after each layer is formed, the surface of the formed layer may be irradiated with ECR plasma to improve the properties. After each layer is formed, the formed layer may be annealed (heat-treated) in an appropriate gas atmosphere such as hydrogen atmosphere to greatly improve the properties of each layer.

The basic idea of the present invention is arranging an insulating layer in contact with a metal oxide layer and sandwiching these layers by the gate electrode and the source and drain electrodes, as shown inFIGS. 97A and 97B. With this structure, when a predetermined voltage (DC or pulse) is applied to the gate electrode to change the resistance value of the metal oxide layer and switch the stable high resistance mode and low resistance mode, an operation as a 3-terminal element can be implemented consequently.

For example, as shown inFIG. 99, a source electrode9716and drain electrode9717may be formed on the insulating layer9702and covered with the metal oxide layer9704, and a gate electrode9713may be formed on the metal oxide layer9704via an insulating layer9715. As shown inFIGS. 100A and 100B, an insulating substrate9701amay be used. In this case, the insulating layer9702shown inFIGS. 97A and 97Bcan be omitted. Alternatively, the structure including the insulating layer9705, metal oxide layer9704, source electrode9706, and drain electrode9707shown inFIGS. 97A and 97Bmay be arranged on a conductive substrate. In this case, the substrate also serves as a gate electrode. When a metal substrate with high thermal conductivity is used as the conductive substrate, a higher cooling effect can be obtained, and a stable element operation can be expected.

An insulating substrate made of glass or quartz may be used. With this structure, the present invention can be applied to, e.g. a glass substrate easy to process. The metal oxide layer9704which has a refractive index of about 2.6 measured at a wavelength of 632.8 nm is optically transparent. For this reason, when a transparent substrate is used, the 3-terminal element of this embodiment can be applied to a display. When the metal oxide layer9704is formed so thick in the range of 10 to 200 nm that an interference color is generated, the visual effect of a colored state can be obtained.

Another form of the 3-terminal element of the present invention will be described next. In the above description, one ferroelectric element has been exemplified. However, as has been described with reference toFIGS. 93A and 93B, a plurality of 3-terminal elements may be arrayed and integrated in a cross-point pattern.

The change in resistance value of the metal oxide layer9704can also be controlled by a current, as described above. A predetermined voltage is applied to the metal oxide layer9704to flow a predetermined current. Immediately after that, a predetermined voltage (e.g., +0.5 V) is applied between the drain electrode9707and the gate electrode9703. The current value changes then.

For example, after a current from 1×10−9A (inclusive) to 1×10−6A (exclusive) is supplied between the electrodes, the current value is small, and a high resistance state is obtained. After a current of 1×10−6A or more is supplied between the electrodes, the value of the flowing current becomes large (e.g., 0.7 mA), and the state changes to a low resistance state. As is apparent from this, the resistance of the metal oxide layer9704also changes depending on the current flowing to it. That is, two resistance values representing a high resistance state and low resistance state are present. Hence, the 3-terminal element shown inFIGS. 97A and 97Bcan be ON/OFF-controlled by both a voltage and a current.

As described above, the resistance change in the metal oxide layer9704can also be controlled by a pulse voltage. For example, as shown inFIG. 42, a negative pulse voltage (e.g., −4 V and 10 μs) is applied once between the gate electrode9703(positive electrode side) and the drain electrode9707(negative electrode side) of the element shown inFIGS. 97A and 97Bwhose metal oxide layer9704is in the high resistance state in the initial state. Then, the state changes to the low resistance state. After that, when a positive pulse voltage (e.g., +5 V and 10 μs) is applied between the electrodes a plurality of number of times (e.g., four times), the state changes to the high resistance state.

The above-described pulse voltage application is repeated. The current measured after each pulse voltage application changes as shown inFIG. 43. As shown inFIG. 43, the high resistance state is set in the initial state. After a negative pulse voltage is applied, the state changes to the low resistance state. When a positive pulse voltage is applied in this state a plurality of number of times, the state changes to the high resistance state. The resistance value of the metal oxide layer9704changes when a positive voltage pulse or negative voltage pulse is applied. Hence, for example, when a positive voltage pulse or negative voltage pulse is applied, the 3-terminal element shown inFIGS. 97A and 97Bcan also be changed from an “on” state to an “off” state or from an “off” state to an “on” state.

The voltage and time of the voltage pulse capable of changing the resistance state of the metal oxide layer9704can be changed in accordance with the situation. For example, when a voltage pulse of +5 V having a width of 10 μs is applied four times to set the high resistance state, and a short pulse of −4 V having a width of 1 μs is applied 10 times, the state can be changed to the low resistance state. When a short pulse of +5 V having a width of 1 μs is applied 100 times in this state, the state can be changed to the high resistance state. When a low voltage pulse of −3 V having a width of 100 μs is applied 100 times in this state, the state can be changed to the low resistance state.

A case wherein the 3-terminal element shown inFIGS. 97A and 97Bis controlled by pulse voltage application will be described next. For example, as shown in the sequence ofFIG. 101, when a negative pulse and positive pulse are alternately applied to the gate electrode9703, the resistance mode between the source electrode9706and the gate electrode9703and that between the drain electrode9707and the gate electrode9703change. In correspondence with this, the ON state and OFF state of the current flowing between the source electrode9706and the drain electrode9707can alternately be switched.

Even in the 3-terminal element shown inFIGS. 97A and 97Busing the metal oxide layer9704of this embodiment, the current-voltage characteristic when a DC voltage is applied between the gate electrode9703and the drain electrode9707(source electrode9706) is changed to different low resistance states by changing the positive-side applied voltage, as shown inFIG. 46. In correspondence with these states, three states (three values) can be implemented in the value of the current flowing between the source and drain. For example, when the read voltage is about 0.5 V, ternary states can be implemented in the value of the current flowing between the source and drain. Before change to each state, a voltage of −2 V is applied to the gate electrode9703to return the state to the high resistance state (reset).

Still another embodiment of the present invention will be described below with reference to the accompanying drawings.FIGS. 102A and 102Bare schematic sectional views schematically showing a structure example of a 3-terminal element according to still another embodiment of the present invention. The 3-terminal element shown inFIGS. 102A and 102Bcomprises, on a substrate10201made of, e.g., single-crystal silicon, an insulating layer10202, a gate electrode10203, a metal oxide layer10204containing Bi, Ti, and O and having a thickness of about 30 to 200 nm, an insulating layer10205, a source electrode10206, and a drain electrode10207. In the 3-terminal element having the above-described structure, a state wherein a potential is applied as shown inFIG. 102Awill be defined as a write state, and a state wherein a potential is applied as shown inFIG. 102Bwill be defined as a read state.

The substrate10201can be made of any one of a semiconductor, insulator, and conductive material such as a metal. When the substrate10201is made of an insulating material, the insulating layer10202can be omitted. When the substrate10201is made of a conductive material, the insulating layer10202and gate electrode10203can be omitted. In this case, the substrate10201made of the conductive material serves as a gate electrode. The gate electrode10203, source electrode10206, and drain electrode10207need only be made of a transition metal including noble metals such as platinum (Pt), ruthenium (Ru), gold (Au), silver (Ag), and titanium (Ti). The electrodes may be made of a compound such as a nitride, oxide, or fluoride of a transition metal, such as titanium nitride (TiN), hafnium nitride (HfN), strontium ruthenate (SrRuO2), zinc oxide (ZnO), indium tin oxide (ITO), or lanthanum fluoride (LaF3), or a composite film formed by stacking them.

The insulating layer10205need only be made of silicon dioxide, silicon oxynitride, alumina, an oxide such as LiNbO3containing a light metal such as lithium, beryllium, magnesium, or calcium, or a fluoride such as LiCaAlF6, LiSrAlF6, LiYF4, LiLuF4, or KMgF3. Alternatively, the insulating layer10205need only be made of an oxide or nitride of a transition metal such as scandium, titanium, strontium, yttrium, zirconium, hafnium, tantalum, or lanthanum series, a silicate (ternary compound of a metal, silicon, and oxygen) containing the above-described elements, an aluminate (ternary compound of a metal, aluminum, and oxygen) containing these elements, or an oxide or nitride containing at least two of the above elements.

Like the above-described ferroelectric layer104and the like, the metal oxide layer10204is formed by dispersing a plurality of microcrystalline grains of Bi4Ti3O12crystal having a grain size of about 3 to 15 nm in a base layer, i.e., a layer containing titanium in an excessive amount relative to the stoichiometric composition of Bi4Ti3O12. This is confirmed by observation using a transmission electron microscope. The base layer may be TiOxwith a bismuth content of almost 0. In other words, the base layer is made of a metal oxide which contains two metals and in which the content of one metal is smaller in comparison with the stoichiometric composition.

A detailed example of the 3-terminal element shown inFIGS. 102A and 102Bwill be described. For example, the gate electrode10203is a ruthenium film having a thickness of 10 nm. The metal oxide layer10204is made of a metal oxide with the above-described composition and has a thickness of 40 nm. The insulating layer10205is a multilayered film made of tantalum pentoxide and silicon dioxide and having a thickness of 5 nm. The source electrode10206and drain electrode10207are made of gold. The source electrode10206and drain electrode10207may have a multilayered structure formed by stacking a titanium layer, titanium nitride layer, and gold layer in this order sequentially from the side of the insulating layer10205. When the contact surface to the insulating layer10205is formed from a titanium layer, the adhesion can be increased. The interval between the source electrode10206and the drain electrode10207is, e.g., 1 mm. As described above, the structures of the substrate10201and insulating layer10202are not limited to those described above, and any other material can also be selected appropriately if it has no effect on the electrical characteristics.

A detailed method of forming the above-described insulating layer10202, gate electrode10203, metal oxide layer10204, insulating layer10205, source electrode10206, and drain electrode10207will be described later. They can be formed by sputtering a metal target or sintered target in ECR plasma made of argon gas, oxygen gas, or nitrogen gas by using an ECR sputtering apparatus shown inFIG. 5.

An example of a method of manufacturing the 3-terminal element shown inFIGS. 102A and 102Bwill be described next with reference toFIG. 103. As shown inFIG. 103A, the p-type silicon substrate10201having a plane orientation of (100) on the principal plane and a resistivity of 1 to 2 Ωcm is prepared. The surface of the substrate10201is cleaned by a solution mixture of sulfuric acid and a hydrogen peroxide solution, pure water, and a hydrogen fluoride solution and dried. The insulating layer10202is formed on the cleaned and dried substrate10201. In forming the insulating layer10202, the above-described ECR sputtering apparatus and pure silicon (Si) as a target are used. The insulating layer10202in a metal mode by Si—O molecules is formed on the silicon substrate10201to a thickness to just cover its surface by ECR sputtering using argon (Ar) as a plasma gas and oxygen gas.

For example, Ar gas is supplied at a flow rate of 20 sccm into a plasma production chamber whose internal pressure is set on the order of 10−5Pa. The internal pressure is set to about 10−3to 10−2Pa. A magnetic field of 0.0875 T and a microwave of 2.45 GHz (about 500 W) are supplied to set the electron cyclotron resonance condition, thereby producing Ar plasma in the plasma production chamber. Note that sccm is the unit of flow rate and indicates that a fluid at 0° C. and 1 atmospheric pressure flows 1 cm3in 1 min.

The plasma produced by the above-described method is output from the plasma production chamber to the process chamber side by the divergent magnetic field of the magnetic coil. In addition, a high-frequency power of 13.56 MHz (e.g., 500 W) is supplied from a high-frequency power supply to the silicon target placed at the outlet of the plasma production chamber. When Ar ions collide against the silicon target, a sputtering phenomenon occurs to sputter Si particles. The Si particles sputtered from the silicon target reach the surface of the silicon substrate10201together with the plasma output from the plasma production chamber and the oxygen gas which is supplied and activated by the plasma and are oxidized to silicon dioxide by the activated oxygen. With the above process, the insulating layer10202made of silicon dioxide and having a thickness of, e.g., about 100 nm can be formed on the substrate10201(FIG. 103A).

The insulating layer10202ensures insulation to prevent a voltage from leaking to the substrate10201and influencing desired electrical characteristics when a voltage is applied between the electrodes to be formed later. For example, a silicon oxide film formed by oxidizing the surface of the silicon substrate by thermal oxidation may be used as the insulating layer10202. The insulating layer10202may be made of any other insulating material except silicon oxide if the insulating properties can be ensured. The thickness of the insulating layer10202need not always be 100 nm and may be smaller or larger. In the above-described formation of the insulating layer10202by ECR sputtering, the substrate10201is not heated. However, the film may be formed while heating the substrate10201.

After the insulating layer10202is formed in the above-described manner, a ruthenium film is formed on the insulating layer10202by similar ECR sputtering using pure ruthenium (Ru) as a target, thereby forming the gate electrode10203, as shown inFIG. 103B. Formation of the Ru film will be described in detail. In an ECR sputtering apparatus using a Ru target, for example, the silicon substrate with the insulating layer formed on it is heated to 400° C. Ar gas as a rare gas is supplied into the plasma production chamber at a flow rate of, e.g., 7 sccm. In addition, Xe gas is supplied at a flow rate of, e.g., 5 sccm to set the internal pressure of the plasma production chamber to on the order of, e.g., 10−2to 10−3Pa.

The magnetic field of the electron cyclotron resonance condition is given to the plasma production chamber. Then, a microwave of 2.45 GHz (about 500 W) is supplied into the plasma production chamber to produce ECR plasma of Ar and Xe in it. The produced ECR plasma is output from the plasma production chamber to the process chamber side by the divergent magnetic field of the magnetic coil. In addition, a high-frequency power of 13.56 MHz (e.g., 500 W) is supplied to the ruthenium target placed at the outlet of the plasma production chamber. The sputtering phenomenon occurs to sputter Ru particles from the ruthenium target. The Ru particles sputtered from the ruthenium target reach the surface of the insulating layer10202on the substrate10201and are deposited.

With the above process, the gate electrode10203having a thickness of, e.g., about 10 nm can be formed on the insulating layer10202(FIG. 103B). The gate electrode10203enables voltage application to the metal oxide layer10204when a voltage is applied between the source electrode10206and drain electrode10207to be formed later. The gate electrode10203may be made of any other material except ruthenium if the conductivity can be ensured. The gate electrode10203may be made of, e.g., platinum. A platinum film formed on silicon dioxide readily peels off, as is known. To prevent this, a layered structure is formed by inserting a titanium layer, titanium nitride layer, or ruthenium layer under the platinum layer. The thickness of the gate electrode10203need not always be 10 nm and may be smaller or larger.

As described above, in forming the Ru film by ECR sputtering, the substrate10201is heated to 400° C. However, the substrate need not always be heated. However, if the substrate is not heated, the adhesion of ruthenium to silicon dioxide becomes low, and the film may peel off. To prevent peeling, the film is formed preferably while heating the substrate.

After the gate electrode10203is formed in the above-described manner, the metal oxide layer10204is formed on the gate electrode10203to a thickness to just cover its surface, as shown inFIG. 103C, by ECR sputtering using argon (Ar) as a plasma gas and oxygen gas and a target formed from an oxide sintered body (Bi—Ti—O) in which the ratio of Bi to Ti is 4:3.

Formation of the metal oxide layer10204will be described in detail. The substrate10201is heated to 300° C. to 700° C. Ar gas as a rare gas is supplied into the plasma production chamber at a flow rate of, e.g., 20 sccm to set the pressure on the order of, e.g., 10−3to 10−2Pa. In this state, the magnetic field of the electron cyclotron resonance condition is given to the plasma production chamber. Then, a microwave of 2.45 GHz (about 500 W) is supplied into the plasma production chamber to produce ECR plasma in it.

The produced ECR plasma is output from the plasma production chamber to the process chamber side by the divergent magnetic field of the magnetic coil. In addition, a high-frequency power of 13.56 MHz (e.g., 500 W) is supplied to the sintered body target placed at the outlet of the plasma production chamber. When Ar particles collide against the sintered body target, the sputtering phenomenon occurs to sputter Bi particles and Ti particles.

The Bi particles and Ti particles sputtered from the sintered body target reach the surface of the heated gate electrode10203together with the ECR plasma output from the plasma production chamber and the oxygen gas activated by the output ECR plasma and are oxidized by the activated oxygen. The oxygen (O2) gas serving as a reactive gas is supplied at a flow rate of, e.g., 1 sccm separately from the Ar gas, as will be described later. Although the sintered body target contains oxygen, any shortage of oxygen in the deposited film can be prevented by supplying oxygen. With the above-described film formation by ECR sputtering, the metal oxide layer10204having a thickness of, e.g., about 40 nm can be formed (FIG. 103C).

The film quality may be improved by irradiating the formed metal oxide layer10204with ECR plasma of an inert gas and a reactive gas. As the reactive gas, not oxygen gas but nitrogen gas, fluorine gas, or hydrogen gas can be used. The film quality improvement can also be applied to formation of the insulating layer10202. The metal oxide layer10204may be formed at a low substrate temperature of 300° C. or less and then annealed (heat-treated) in an appropriate gas atmosphere such as oxygen atmosphere to greatly improve the properties of the film.

After the metal oxide layer10204is formed in the above-described manner, the substrate10201is unloaded from the apparatus to the atmosphere. The substrate10201is fixed on the substrate holder of the same ECR sputtering apparatus as inFIG. 5in which pure tantalum (Ta) is used as the target. The insulating layer10205is formed on the metal oxide layer10204to a thickness to just cover its surface, as shown inFIG. 103D, by ECR sputtering using argon (Ar) as a plasma gas and oxygen gas. A metal mode film by Ta—O molecules is formed as the insulating layer10205, as will be described below.

Formation of a metal mode film by Ta—O molecules will be described in detail. In the ECR sputtering apparatus shown inFIG. 5in which the target made of tantalum is used, Ar gas as a rare gas is supplied at a flow rate of, e.g., 25 sccm from the inert gas supply unit into the plasma production chamber to set its internal pressure on the order of, e.g., 10−3Pa. A coil current of, e.g., 28 A is supplied to the magnetic coil to give the magnetic field of the electron cyclotron resonance condition to the plasma production chamber.

A microwave of, e.g., 2.45 GHz (e.g., 500 W) is supplied from the microwave generation unit (not shown) into the plasma production chamber through the waveguide, quartz window, and vacuum waveguide. With this supply of the microwave, Ar plasma is produced in the plasma production chamber. The produced plasma is output from the plasma production chamber to the side of the process chamber by the divergent magnetic field of the magnetic coil. In addition, a high-frequency power (e.g., 500 W) is supplied from the high-frequency electrode supply unit to the target placed at the outlet of the plasma production chamber.

When Ar particles collide against the target, a sputtering phenomenon occurs to sputter Ta particles from the target. The Ta particles sputtered from the target reach the surface of the metal oxide layer10204on the substrate10201together with the plasma output from the plasma production chamber and the oxygen gas which is supplied from the reactive gas supply unit and activated by the plasma and are oxidized to tantalum pentoxide by the activated oxygen.

With the above process, a tantalum pentoxide film is formed on the metal oxide layer10204. Subsequently, a silicon dioxide film is formed on the tantalum pentoxide film by ECR sputtering using the target made of pure silicon, like silicon dioxide deposition described with reference toFIG. 103A. The above-described formation of a tantalum pentoxide film and silicon dioxide film is repeated to form a multilayered film including the tantalum pentoxide films and silicon dioxide films to, e.g., about 5 nm, thereby obtaining the insulating layer10205(FIG. 103D).

The insulating layer10205including the tantalum pentoxide films and silicon dioxide films is used to control the voltage to be applied to the ferroelectric film upon voltage application to the metal oxide layer10204. The insulating layer10205may have any other structure except the multilayered structure of tantalum pentoxide films and silicon dioxide films if it can control the voltage applied to the metal oxide layer10204. The insulating layer10205may be a single layer. The thickness is not limited to 5 nm, either. In the above-described ECR sputtering, the substrate10201is not heated but may be heated.

The source electrode10206and drain electrode10207each made of Au and having a predetermined area are formed on the insulating layer10205, as shown inFIG. 103E, thereby obtaining the 3-terminal element shown inFIGS. 102A and 102B. The source electrode10206and drain electrode10207can be formed by a well-known lift-off method and gold deposition by resistance heating vacuum deposition. The source electrode10206and drain electrode10207may be made of another metal material or conductive material such as Ru, Pt, or TiN. When Pt is used, the adhesion is poor, and the film may peel off. Hence, each electrode must be formed as an electrode with a predetermined area by using a structure such as Ti—Pt—Au that hardly peels off and executing a patterning process such as photolithography or lift-off on that structure.

The characteristics of the element using the metal oxide layer10204will be described next. The characteristics were investigated by applying a voltage between the gate electrode10203and the drain electrode10207. When a voltage from a power supply was applied between the gate electrode10203and the drain electrode10207, and a current flowing when the voltage was applied was measured by an ammeter, a result shown inFIG. 49was obtained.FIG. 49and the operation principle of the element according to the present invention will be described below. The voltage values and current values to be described here are mere examples measured in an actual element. Hence, the phenomenon is not limited to the following numerical values. Other numerical values can also be measured depending on the material and thickness of each film actually used in the element and other conditions.

When a positive voltage is applied to the gate electrode10203, the flowing current is very small in the range of 0 to 1.0 V, as indicated by (1) inFIG. 49. However, as indicated by (2), when the voltage exceeds 1.1 V, a positive current flows abruptly. Actually, a current larger than 0.1 A/cm2also flows. However, since flowing of a larger current is inhibited to protect the measurement device, the current is not measured. In the range of 0 to 1.0 V indicated by (1), a high resistance state is held (maintained) by inhibiting flowing of a large current as indicated by (2).

When a positive voltage is applied again to the gate electrode10203, a locus to flow a positive current of 0.1 A/cm2or more is obtained at about 0.8 V, as indicated by (3). When the positive voltage is further applied to the gate electrode10203, a current of 0.1 A/cm2or more flows at about 0.8 V, as indicated by (3).

When a negative voltage is applied to the gate electrode10203, a negative current flows up to about −0.2 V, as indicated by (4). The current increases to −1.5×10−2A/cm2at maximum. When the absolute value of the voltage is decreased, the current traces a locus indicated by (4).

When the negative voltage is applied up to −0.2 V, the current-traces the locus indicated by (4). After that, as indicated by (5), the value of the flowing current decreases, and no negative current flows. When the negative voltage is further applied to the gate electrode10203, a locus to rarely flow a current is obtained, as indicated by (6). Even when the absolute value of the voltage is decreased then, the current rarely flows, as indicated by (6). When a positive voltage is applied to the gate electrode10203, the current rarely flows up to 0 to 1.0 V, as indicated by (1).

Hence, the high resistance state wherein no current flows as in (1) is maintained unless a voltage of 1.1 V or more is applied to the gate electrode10203to prevent any sudden current flow as in (2). The state (1) will be referred to as a “positive high resistance mode”.

For example, as indicated by (2), when a voltage of 1.1 V or more is applied to abruptly flow a current, a low resistance state in which the current readily flows is obtained, as indicated by (3). This state is also maintained while a positive voltage is applied to the gate electrode10203. The state (3) will be referred to as a “positive low resistance mode”.

However, when a negative voltage is applied to the gate electrode10203, a low resistance state in which a small current flows in the early stage in a negative voltage range from 0 to −0.2 V is obtained, as indicated by (4). This state is also maintained while a negative voltage in the range of 0 to −0.2 V is applied. The state (4) will be referred to as a “negative low resistance mode”.

When a negative voltage of −0.2 V or more is applied, no current flows, and the state changes to a high resistance state, as indicated by (5). In this state, the state wherein the current value has a high resistance is maintained while a negative voltage in the range of 0 to −1.0 V is applied, as indicated by (6). The state (6) will be referred to as a “negative high resistance mode”.

As described above, the metal oxide layer10204apparently has four stable modes: “positive high resistance mode”, “positive low resistance mode”, “negative high resistance mode”, and “negative low resistance mode”. More specifically, the “positive high resistance mode” and “negative high resistance mode” are “high resistance modes” which exhibit the same high resistance state. The “positive low resistance mode” and “negative low resistance mode” are “low resistance modes” which exhibit the same low resistance state. That is, two modes are present. In the state of the “high resistance mode”, the “high resistance mode” is maintained in the voltage range of −1.5 V to +1.0 V. When a voltage of +1.0 V or more is applied to change the state to the “low resistance mode”, the “low resistance mode” is maintained in the voltage range of −0.2 V to +0.8 V. Switching between the two, “high resistance mode” and “low resistance mode” occurs. This also applied to the negative resistance modes, i.e., “negative high resistance mode” and “negative low resistance mode”.

As for the actual current value in each “positive mode” when a voltage of 0.5 V is applied, the current value in the “positive high resistance mode” is 1.0×10−5A/cm2, and that in the “positive low resistance mode” is 5×10−2A/cm2. The ratio is as high as 5,000 times. This facilitates each mode identification. The present inventors estimate that the above-described phenomenon occurs when the resistance value of the metal oxide layer10204dramatically changes depending on the direction and magnitude of the applied voltage.

Since the insulating layer10205is provided between the metal oxide layer10204and the drain electrode10207(source electrode10206), carriers can be controlled by the band structure of the insulating layer10205. More specifically, for example, tantalum pentoxide has a band gap of about 4.5 eV. The energy difference viewed from the Fermi level is about 1.2 eV in the conduction band and 2.3 eV in the valence band. That is, the barrier is higher on the valence band side. Hence, the barrier effect is high for holes in the valence band but low for electrons in the conduction band. For further information, see Wilk et al., “J. Appl. Phys.”, No. 87, p. 484 (2000).

From the above-described characteristic, when, e.g., a tantalum pentoxide film is used as the insulating layer between the electrode and the metal oxide layer10204, a phenomenon that electrons readily flow but holes hardly flow can be expected. Actually, as shown inFIG. 49, the value of the flowing current largely changes between a case wherein a positive voltage is applied to the drain electrode10207and a case wherein a negative voltage is applied. In discriminating the state of the metal oxide layer10204, this has a large effect to increase the signal-to-noise ratio (S/N ratio) and facilitate state discrimination. This is the effect of use of the insulating layer10205.

It was found that when the above-described “low resistance mode” and “high resistance mode” shown inFIG. 49are applied, the element shown inFIGS. 102Aand102B can be used as a nonvolatile 3-terminal element capable of a nondestructive read. More specifically, the OFF state wherein the current between the source and drain hardly flows is set by applying a negative voltage to the gate electrode10203and a positive voltage to the drain electrode10207to change the mode from the “low resistance mode” to the “high resistance mode”, as indicated by (4) or (5) inFIG. 49.

The ON state wherein the current between the source and drain readily flows is set by applying a positive voltage to the gate electrode10203and a negative voltage of −0.8 V or more to the drain electrode10207to abruptly flow the current, as indicated by (2) inFIG. 49. With this operation, the mode is changed from the “high resistance mode” to the “low resistance mode”, and the ON state is obtained. As described above, when a voltage is applied to the gate electrode10203(drain electrode10207) to set the “high resistance mode” or “low resistance mode”, switching between the OFF state and the ON state can be done.

The ON/OFF state between the source and drain controlled in the above-described way can easily be recognized by reading a current value when an appropriate voltage of −0.8 to +0.8 V is applied between the source and drain. For example, when the mode state of the element shown inFIGS. 102A and 102Bis “off”, i.e., “high resistance mode”, it can be determined because a current hardly flows when an appropriate voltage of −0.8 to +0.8 V is applied, as indicated by (1) inFIG. 49.

When the mode state of the element shown inFIGS. 102A and 102Bis “on”, i.e., “low resistance mode”, it can be determined because a current abruptly flows when an appropriate voltage of −0.5 to +0.2 V is applied, as indicated by (2) inFIG. 49. Since the difference in current value between the “negative high resistance mode” and the “negative low resistance mode”, i.e., “off” and “on” is 200 times or more, “off” and “on” can easily be determined. Even in the positive voltage range, “off” and “on” can be determined in the voltage range of 0 to +0.2 V.

The above-described ON/OFF state can easily be identified only by checking whether the element shown inFIGS. 102A and 102Bis in the “high resistance mode” or “low resistance mode”. Even when a positive voltage is applied to the electrode to check the mode, the held mode does not change. Hence, according to the 3-terminal element shown inFIGS. 102A and 102B, a nondestructive read operation is possible. The element shown inFIGS. 102A and 102Bfunctions as a 3-terminal element to control ON/OFF between the source and drain since the resistance value of the metal oxide layer10204changes depending on the voltage applied between the gate electrode10203and the drain electrode10207(or source electrode10206). This element can also be used as an element to control the current.

Even when the source electrode10206is set open, the ON state and OFF state can be controlled by applying a gate voltage. In the case wherein the source electrode10206is set open, when the read voltage is increased, a current to some extent flows between the source and drain even when a gate voltage is applied to set the OFF state. When the source electrode10206is set open, and the gate voltage is applied in this state, the applied voltage selectively acts depending on the region under the drain electrode10207. As described above, a certain source-drain current is supposed to flow when the read voltage is high. Hence, the source-drain current is supposed to flow through a path formed from the source electrode10206, the metal oxide layer10204in the region under the source electrode10206, the gate electrode10203, the metal oxide layer10204in the region under the drain electrode10207, and the drain electrode10207.

The voltage to operate the element shown inFIGS. 102A and 102Bis maximized in the “negative low resistance mode”. However, the voltage is about −0.8 V, and the power consumption is very low, as shown inFIG. 49. The low power consumption is very advantageous for devices. Devices using a 3-terminal element, e.g., not only mobile communication devices, digital general-purpose devices, digital image sensing devices, notebook personal computers, and PDAs (Personal Digital Appliances) but also all computers, personal computers, workstations, office computers, mainframes, communication units, and multifunction apparatuses can reduce the power consumption.

Like the above-described elements, the 3-terminal element shown inFIGS. 102A and 102Bcan also hold the ON or OFF state for 10 years.

In the above-described example of the present invention, each of the insulating layer on the silicon substrate, the gate electrode layer on the insulating layer, and the metal oxide layer on the gate electrode is formed by ECR sputtering. However, the method of forming each layer is not limited to ECR sputtering. For example, the insulating layer to be formed on the silicon substrate may be formed by thermal oxidation or CVD (Chemical Vapor Deposition) or a conventional sputtering method.

The gate electrode layer may be formed by any other film formation method such as EB deposition, CVD, MBE, or IBD. The metal oxide layer can also be formed by the above-described MOD, conventional sputtering method, PLD, or MOCVD. However, when ECR sputtering is used, flat and excellent insulating film, metal film, and metal oxide film can easily be obtained.

In the above-described embodiment, after each layer is formed, the substrate is temporarily unloaded into the atmosphere. However, the layers may be formed by a continuous process without unloading the structure into the atmospheric by using an apparatus which connects, through vacuum transfer chambers, the process chambers to realize ECR sputtering to form the respective layers. With this arrangement, the substrate to be processed can be transported in vacuum and is therefore prevented from being influenced by disturbance such as water adhesion. Hence, the film quality and interface properties can be improved.

As shown in patent reference 7, after each layer is formed, the surface of the formed layer may be irradiated with ECR plasma to improve the properties. After each layer is formed, the formed layer may be annealed (heat-treated) in an appropriate gas atmosphere such as hydrogen atmosphere to greatly improve the properties of each layer.

The basic idea of the present invention is arranging an insulating layer in contact with a metal oxide layer and sandwiching these layers by the gate electrode and the source and drain electrodes, as shown inFIGS. 102A and 102B. With this structure, when a predetermined voltage (DC or pulse) is applied to the gate electrode to change the resistance value of the metal oxide layer and switch the stable high resistance mode and low resistance mode, an operation as a 3-terminal element can be implemented consequently.

For example, as shown inFIG. 104, a source electrode10216and drain electrode10217may be formed on the insulating layer10202and covered with the metal oxide layer10204on an insulating layer10215, and a gate electrode10213may be formed on the metal oxide layer10204. As shown inFIGS. 105A and 105B, an insulating substrate10201amay be used. In this case, the insulating layer10202shown inFIGS. 102A and 102Bcan be omitted. Alternatively, the structure including the metal oxide layer10204, insulating layer10205, source electrode10206, and drain electrode10207shown inFIGS. 102A and 102Bmay be arranged on a conductive substrate. In this case, the substrate also serves as a gate electrode. When a metal substrate with high thermal conductivity is used as the conductive substrate, a higher cooling effect can be obtained, and a stable element operation can be expected.

An insulating substrate made of glass or quartz may be used. With this structure, the present invention can be applied to, e.g. a glass substrate easy to process. The metal oxide layer10204which has a refractive index of about 2.6 measured at a wavelength of 632.8 nm is optically transparent. For this reason, when a transparent substrate is used, the 3-terminal element of this embodiment can be applied to a display. When the metal oxide layer10204is formed so thick in the range of 10 to 200 nm that an interference color is generated, the visual effect of a colored state can be obtained.

In the above description, one ferroelectric element has been exemplified. However, as has been described with reference toFIG. 93, a plurality of 3-terminal elements may be arrayed and integrated in a cross-point pattern. The change in resistance value of the metal oxide layer10204of the 3-terminal element shown inFIGS. 102A and 102Bcan also be controlled by a current, like the above-described 3-terminal elements. The resistance change in the metal oxide layer10204can also be controlled by a pulse voltage. Even the 3-terminal element shown inFIGS. 102A and 102Bcan implement three states (three values) in the value of the current flowing between the source and drain.

Still another embodiment of the present invention will be described below with reference to the accompanying drawings.FIGS. 106A and 106Bare schematic sectional views schematically showing a structure example of a 3-terminal element according to still another embodiment of the present invention. The 3-terminal element shown inFIG. 106comprises, on a substrate10601made of, e.g., single-crystal silicon, an insulating layer10602, a gate electrode10603, a metal oxide layer10604containing Bi, Ti, and O and having a thickness of about 30 to 200 nm, a source electrode10607, and a drain electrode10608. In addition, an insulating layer (first insulating layer)10605is provided between the gate electrode10603and the metal oxide layer10604. An insulating layer (second insulating layer)10606is provided between the metal oxide layer10604and the source electrode10607and drain electrode10608. In the 3-terminal element having the above-described structure, a state wherein a potential is applied as shown inFIG. 106Awill be defined as a write state, and a state wherein a potential is applied as shown inFIG. 106Bwill be defined as a read state.

The substrate10601can be made of any one of a semiconductor, insulator, and conductive material such as a metal. When the substrate10601is made of an insulating material, the insulating layer10602can be omitted. When the substrate10601is made of a conductive material, the insulating layer10602and gate electrode10603can be omitted. In this case, the substrate10601made of the conductive material serves as a gate electrode. The gate electrode10603, source electrode10607, and drain electrode10608need only be made of a transition metal including noble metals such as platinum (Pt), ruthenium (Ru), gold (Au), silver (Ag), and titanium (Ti). The electrodes may be made of a compound such as a nitride, oxide, or fluoride of a transition metal, such as titanium nitride (TiN), hafnium nitride (HfN), strontium ruthenate (SrRuO2), zinc oxide (ZnO), indium tin oxide (ITO), or lanthanum fluoride (LaF3), or a composite film formed by stacking them.

The insulating layers10605and10606need only be made of silicon dioxide, silicon oxynitride, alumina, an oxide such as LiNbO3containing a light metal such as lithium, beryllium, magnesium, or calcium, or a fluoride such as LiCaAlF6, LiSrAlF6, LiYF4, LiLuF4, or KMgF3. Alternatively, the insulating layers10605and10606need only be made of an oxide or nitride of a transition metal such as scandium, titanium, strontium, yttrium, zirconium, hafnium, tantalum, or lanthanum series, a silicate (ternary compound of a metal, silicon, and oxygen) containing the above-described elements, an aluminate (ternary compound of a metal, aluminum, and oxygen) containing these elements, or an oxide or nitride containing at least two of the above elements.

The metal oxide layer10604is the same as the above-described ferroelectric layer10604, ferroelectric layer310604, ferroelectric layer4705, ferroelectric layer6205, metal oxide layer8604, metal oxide layer9704, and metal oxide layer10204.

A detailed example of the 3-terminal element shown inFIG. 106will be described. For example, the gate electrode10603is a ruthenium film having a thickness of 10 nm. The metal oxide layer10604is made of a metal oxide with the above-described composition and has a thickness of 40 nm. Each of the insulating layers10605and106is a multilayered film made of tantalum pentoxide and silicon dioxide and having a thickness of 5 nm. The source electrode10607and drain electrode10608are made of gold. The source electrode10607and drain electrode10608may have a multilayered structure formed by stacking a titanium layer, titanium nitride layer, and gold layer in this order sequentially from the side of the metal oxide layer10604. When the contact surface to the metal oxide layer10604is formed from a titanium layer, the adhesion can be increased. The interval between the source electrode10607and the drain electrode10608is, e.g., 1 mm. As described above, the structures of the substrate10601and insulating layer10602are not limited to those described above, and any other material can also be selected appropriately if it has no effect on the electrical characteristics.

A detailed method of forming the above-described insulating layer10602, gate electrode10603, insulating layer10605, metal oxide layer10604, insulating layer10606, source electrode10607, and drain electrode10608will be described later. They can be formed by sputtering a metal target or sintered target in ECR plasma made of argon gas, oxygen gas, or nitrogen gas by using an ECR sputtering apparatus shown inFIG. 5.

An example of a method of manufacturing the 3-terminal element shown inFIG. 106will be described next with reference toFIGS. 107A to 107F. As shown inFIG. 107A, the p-type silicon substrate10601having a plane orientation of (100) on the principal plane and a resistivity of 1 to 2 Ωcm is prepared. The surface of the substrate10601is cleaned by a solution mixture of sulfuric acid and a hydrogen peroxide solution, pure water, and a hydrogen fluoride solution and dried. The insulating layer10602is formed on the cleaned and dried substrate10601. In forming the insulating layer10602, the above-described ECR sputtering apparatus and pure silicon (Si) as a target are used. The insulating layer10602in a metal mode by Si—O molecules is formed on the silicon substrate10601to a thickness to just cover its surface by ECR sputtering using argon (Ar) as a plasma gas and oxygen gas.

For example, Ar gas is supplied at a flow rate of 20 sccm into a plasma production chamber whose internal pressure is set on the order of 10−5Pa. The internal pressure is set to about 10−3to 10−2Pa. A magnetic field of 0.0875 T and a microwave of 2.45 GHz (about 500 W) are supplied to set the electron cyclotron resonance condition, thereby producing Ar plasma in the plasma production chamber. Note that sccm is the unit of flow rate and indicates that a fluid at 0° C. and 1 atmospheric pressure flows 1 cm3in 1 min.

The plasma produced by the above-described method is output from the plasma production chamber to the process chamber side by the divergent magnetic field of the magnetic coil. In addition, a high-frequency power of 13.56 MHz (e.g., 500 W) is supplied from a high-frequency power supply to the silicon target placed at the outlet of the plasma production chamber. When Ar ions collide against the silicon target, a sputtering phenomenon occurs to sputter Si particles. The Si particles sputtered from the silicon target reach the surface of the silicon substrate10601together with the plasma output from the plasma production chamber and the oxygen gas which is supplied and activated by the plasma and are oxidized to silicon dioxide by the activated oxygen. With the above process, the insulating layer10602made of silicon dioxide and having a thickness of, e.g., about 100 nm can be formed on the substrate10601(FIG. 107A).

The insulating layer10602ensures insulation to prevent a voltage from leaking to the substrate10601and influencing desired electrical characteristics when a voltage is applied between the electrodes to be formed later. For example, a silicon oxide film formed by oxidizing the surface of the silicon substrate by thermal oxidation may be used as the insulating layer10602. The insulating layer10602may be made of any other insulating material except silicon oxide if the insulating properties can be ensured. The thickness of the insulating layer10602need not always be 100 nm and may be smaller or larger. In the above-described formation of the insulating layer10602by ECR sputtering, the substrate10601is not heated. However, the film may be formed while heating the substrate10601.

After the insulating layer10602is formed in the above-described manner, a ruthenium film is formed on the insulating layer10602by similar ECR sputtering using pure ruthenium (Ru) as a target, thereby forming the gate electrode10603, as shown inFIG. 107B. Formation of the Ru film will be described in detail. In an ECR sputtering apparatus using a Ru target, for example, the silicon substrate with the insulating layer formed on it is heated to 400° C. Ar gas as a rare gas is supplied into the plasma production chamber at a flow rate of, e.g., 7 sccm. In addition, Xe gas is supplied at a flow rate of, e.g., 5 sccm to set the internal pressure of the plasma production chamber to on the order of, e.g., 10−2to 10−3Pa.

The magnetic field of the electron cyclotron resonance condition is given to the plasma production chamber. Then, a microwave of 2.45 GHz (about 500 W) is supplied into the plasma production chamber to produce ECR plasma of Ar and Xe in it. The produced ECR plasma is output from the plasma production chamber to the process chamber side by the divergent magnetic field of the magnetic coil. In addition, a high-frequency power of 13.56 MHz (e.g., 500 W) is supplied to the ruthenium target placed at the outlet of the plasma production chamber. The sputtering phenomenon occurs to sputter Ru particles from the ruthenium target. The Ru particles sputtered from the ruthenium target reach the surface of the insulating layer10602on the substrate10601and are deposited.

With the above process, the gate electrode10603having a thickness of, e.g., about 10 nm can be formed on the insulating layer10602(FIG. 107B). The gate electrode10603enables voltage application to the metal oxide layer10604when a voltage is applied between the source electrode10607and drain electrode10608to be formed later. The gate electrode10603may be made of any other material except ruthenium if the conductivity can be ensured. The gate electrode10603may be made of, e.g., platinum. A platinum film formed on silicon dioxide readily peels off, as is known. To prevent this, a layered structure is formed by inserting a titanium layer, titanium nitride layer, or ruthenium layer under the platinum layer. The thickness of the gate electrode10603need not always be 10 nm and may be smaller or larger.

As described above, in forming the Ru film by ECR sputtering, the substrate10601is heated to 400° C. However, the substrate need not always be heated. However, if the substrate is not heated, the adhesion of ruthenium to silicon dioxide becomes low, and the film may peel off. To prevent peeling, the film is formed preferably while heating the substrate.

After the gate electrode10603is formed in the above-described manner, the substrate10601is unloaded from the apparatus to the atmosphere. The substrate10601is fixed on the substrate holder of the same ECR sputtering apparatus as inFIG. 5in which pure tantalum (Ta) is used as the target. The insulating layer10605is formed on the gate electrode10603to a thickness to just cover its surface, as shown inFIG. 107C, by ECR sputtering using argon (Ar) as a plasma gas and oxygen gas. A metal mode film by Ta—O molecules is formed as the insulating layer10605, as will be described below.

Formation of a metal mode film by Ta—O molecules will be described in detail. In the ECR sputtering apparatus shown inFIG. 5in which the target made of tantalum is used, Ar gas as a rare gas is supplied at a flow rate of, e.g., 25 sccm from the inert gas supply unit into the plasma production chamber to set its internal pressure on the order of, e.g., 10−3Pa. A coil current of, e.g., 28 A is supplied to the magnetic coil to give the magnetic field of the electron cyclotron resonance condition to the plasma production chamber.

A microwave of, e.g., 2.45 GHz (e.g., 500 W) is supplied from the microwave generation unit (not shown) into the plasma production chamber through the waveguide, quartz window, and vacuum waveguide. With this supply of the microwave, Ar plasma is produced in the plasma production chamber. The produced plasma is output from the plasma production chamber to the side of the process chamber by the divergent magnetic field of the magnetic coil. In addition, a high-frequency power (e.g., 500 W) is supplied from the high-frequency electrode supply unit to the target placed at the outlet of the plasma production chamber.

When Ar particles collide against the target, a sputtering phenomenon occurs to sputter Ta particles from the target. The Ta particles sputtered from the target reach the surface of the gate electrode10603on the substrate10601together with the plasma output from the plasma production chamber and the oxygen gas which is supplied from the reactive gas supply unit and activated by the plasma and are oxidized to tantalum pentoxide by the activated oxygen.

With the above process, a tantalum pentoxide film is formed on the gate electrode10603. Subsequently, a silicon dioxide film is formed on the tantalum pentoxide film by ECR sputtering using the target made of pure silicon, like silicon dioxide deposition described with reference toFIG. 107A. The above-described formation of a tantalum pentoxide film and silicon dioxide film is repeated to form a multilayered film including the tantalum pentoxide films and silicon dioxide films to, e.g., about 5 nm, thereby obtaining the insulating layer10605(FIG. 107C).

The insulating layer10605including the tantalum pentoxide films and silicon dioxide films is used to control the voltage to be applied to the ferroelectric film upon voltage application to the metal oxide layer10604. The insulating layer10605may have any other structure except the multilayered structure of tantalum pentoxide films and silicon dioxide films if it can control the voltage applied to the metal oxide layer10604. The insulating layer10605may be a single layer. The thickness is not limited to 5 nm, either. In the above-described ECR sputtering, the substrate10601is not heated but may be heated.

After the insulating layer10605is formed in the above-described manner, the metal oxide layer10604is formed on the insulating layer10605to a thickness to just cover its surface, as shown inFIG. 107D, by ECR sputtering using argon (Ar) as a plasma gas and oxygen gas and a target formed from an oxide sintered body (Bi—Ti—O) in which the ratio of Bi to Ti is 4:3.

Formation of the metal oxide layer10604will be described in detail. The substrate10601is heated to 300° C. to 700° C. Ar gas as a rare gas is supplied into the plasma production chamber at a flow rate of, e.g., 20 sccm to set the pressure on the order of, e.g., 10−3to 10−2Pa. In this state, the magnetic field of the electron cyclotron resonance condition is given to the plasma production chamber. Then, a microwave of 2.45 GHz (about 500 W) is supplied into the plasma production chamber to produce ECR plasma in it.

The produced ECR plasma is output from the plasma production chamber to the process chamber side by the divergent magnetic field of the magnetic coil. In addition, a high-frequency power of 13.56 MHz (e.g., 500 W) is supplied to the sintered body target placed at the outlet of the plasma production chamber. When Ar particles collide against the sintered body target, the sputtering phenomenon occurs to sputter Bi particles and Ti particles.

The Bi particles and Ti particles sputtered from the sintered body target reach the surface of the heated insulating layer10605together with the ECR plasma output from the plasma production chamber and the oxygen gas activated by the output ECR plasma and are oxidized by the activated oxygen. The oxygen (O2) gas serving as a reactive gas is supplied at a flow rate of, e.g., 1 sccm separately from the Ar gas, as will be described later. Although the sintered body target contains oxygen, any shortage of oxygen in the deposited film can be prevented by supplying oxygen. With the above-described film-formation by ECR sputtering, the metal oxide layer10604having a thickness of, e.g., about 40 nm can be formed (FIG. 107D).

The film quality may be improved by irradiating the formed metal oxide layer10604with ECR plasma of an inert gas and a reactive gas. As the reactive gas, not oxygen gas but nitrogen gas, fluorine gas, or hydrogen gas can be used. The film quality improvement can also be applied to formation of the insulating layer10602. The metal oxide layer10604may be formed at a low substrate temperature of 300° C. or less and then annealed (heat-treated) in an appropriate gas atmosphere such as oxygen atmosphere to greatly improve the properties of the film.

After the metal oxide layer10604is formed in the above-described manner, the insulating layer10606is formed on the metal oxide layer10604to a thickness to just cover its surface, as shown inFIG. 107E, as in the above-described formation of the insulating layer10605.

The source electrode10607and drain electrode10608each made of Au and having a predetermined area are formed on the insulating layer10606, as shown inFIG. 107F, thereby obtaining the 3-terminal element shown inFIG. 106. The source electrode10607and drain electrode10608can be formed by a well-known lift-off method and gold deposition by resistance heating vacuum deposition. The source electrode10607and drain electrode10608may be made of another metal material or conductive material such as Ru, Pt, or TiN. When Pt is used, the adhesion is poor, and the film may peel off. Hence, each electrode must be formed as an electrode with a predetermined area by using a structure such as Ti—Pt—Au that hardly peels off and executing a patterning process such as photolithography or lift-off on that structure.

The characteristics of the 3-terminal element shown inFIG. 106will be described next. The characteristics were investigated by applying a voltage between the gate electrode10603and the drain electrode10608(source electrode10607). When a voltage from a power supply was applied between the gate electrode10603and the drain electrode10608, and a current flowing when the voltage was applied was measured by an ammeter, a result shown inFIG. 64was obtained. InFIG. 64, the ordinate represents the current density obtained by dividing the current value by the area.FIG. 64and the memory operation principle of the present invention will be described below. The voltage values and current values to be described here are mere examples measured in an actual element. Hence, the phenomenon is not limited to the following numerical values. Other numerical values can also be measured depending on the material and thickness of each film actually used in the element and other conditions.

When a positive voltage is applied to the drain electrode10608, the flowing current is very small in the range of 0 to 1.6 V, as indicated by (1) inFIG. 64. However, as indicated by (2), when the voltage exceeds 1.6 V, a positive current flows abruptly. Actually, a current larger than 5×10−3A/cm2also flows. However, since flowing of a larger current is inhibited to protect the measurement device, the current is not measured. When a voltage of 0 to 1.6 V is applied to inhibit abrupt current flow as indicated by (2), a state wherein the resistance is high, as indicated by (1), is maintained.

When a positive voltage is applied again to the drain electrode10608, a locus to flow a positive current of 1×10−3A/cm2or more is obtained at about 0.5 V, as indicated by (3). When the positive voltage is further applied to the drain electrode10608, a current of 1×10−3A/cm2or more flows at about 0.5 V, as indicated by (3). When a voltage of 0 to 0.5 V is applied, a state wherein the resistance is low, as indicated by (3), is maintained.

When a negative voltage is applied to the drain electrode10608, a negative current flows up to about −0.5 V, as indicated by (4). The current increases to −1.5×10−3A/cm2at maximum. When a voltage of 0 to −0.5 V is applied, a state wherein the resistance is low is maintained, as indicated by (4).

When a negative voltage is applied from −0.5 V to −1.6 V, the current value decreases, and no negative current flows, as indicated by (5). Even when the absolute value of the voltage from −1.6 V to 0 V is decreased then, the current rarely flows, as indicated by (6). When a negative voltage is applied to the drain electrode10608, a locus to rarely flow a current is obtained, as indicated by (6).

When a positive voltage is applied to the drain electrode10608, a locus to rarely flow a current t up 0 to 1.6 V is obtained, as indicated by (1) When a voltage of 1.6 V or more is applied, a state representing a low resistance indicated by (3) is obtained.

Hence, the high resistance state wherein no current flows as in (1) is maintained unless a voltage of 1.6 V or more is applied to the drain electrode10608to prevent any sudden current flow as in (2). The state (1) will be referred to as a “positive high resistance mode”.

For example, as indicated by (2), when a voltage of 1.6 V or more is applied to abruptly flow a current, a low resistance state in which the current readily flows is obtained, as indicated by (3). This state is also maintained while a positive voltage is applied to the drain electrode10608. The state (3) will be referred to as a “positive low resistance mode”.

However, when a negative voltage is applied to the drain electrode10608, a low resistance state in which a small current flows in the early stage in a negative voltage range from 0 to −0.5 V is obtained, as indicated by (4). This state is also maintained while a negative voltage in the range of 0 to −0.5 V is applied. The state (4) will be referred to as a “negative low resistance mode”.

When a negative voltage exceeding −0.5 V is applied, no current flows, and the state changes to a high resistance state, as indicated by (5). In this state, the state wherein the current value has a high resistance is maintained while a negative voltage in the range of 0 to −1.6 V is applied, as indicated by (6). The state (6) will be referred to as a “negative high resistance mode”.

As described above, the metal oxide layer10604apparently has four stable modes: “positive high resistance mode”, “positive low resistance mode”, “negative high resistance mode”, and “negative low resistance mode”. More specifically, the “positive high resistance mode” and “negative high resistance mode” are “high resistance modes” which exhibit the same high resistance state. The “positive low resistance mode” and “negative low resistance mode” are “low resistance modes” which exhibit the same low resistance state. That is, two modes are present. In the state of the “high resistance mode”, the “high resistance mode” is maintained in the voltage range of −1.6 V to +1.6 V. When a voltage of +1.6 V or more is applied to change the state to the “low resistance mode”, the “low resistance mode” is maintained in the voltage range of −0.5 V to +0.5 V. Switching between the two, “high resistance mode” and “low resistance mode” occurs. This also applied to the negative resistance modes, i.e., “negative high resistance mode” and “negative low resistance mode”.

As for the actual current value in each “positive mode” when a voltage of 0.5 V is applied, the current value in the “positive high resistance mode” is 5.0×10−6A/cm2, and that in the “positive low resistance mode” is 5×10−3A/cm2. The ratio is as high as 1,000 times. This facilitates each mode identification. The present inventors estimate that the above-described phenomenon occurs when the resistance value of the metal oxide layer6205dramatically changes depending on the direction and magnitude of the applied voltage. This also applies to the “negative low resistance mode”.

Since the insulating layer10605is provided between the metal oxide layer10604and the gate electrode10603, and the insulating layer10606is provided between the metal oxide layer10604and the drain electrode10608(source electrode10607), carriers can be controlled by the band structures of the insulating layers10605and10606. More specifically, for example, tantalum pentoxide has a band gap of about 4.5 eV. The energy difference viewed from the Fermi level is about 1.2 eV in the conduction band and 2.3 eV in the valence band. That is, the barrier is higher on the valence band side. Hence, the barrier effect is high for holes in the valence band but low for electrons in the conduction band. For further information, see Wilk et al., “J. Appl. Phys.”, No. 87, p. 484 (2000).

From the above-described characteristic, when, e.g., a tantalum pentoxide film is used as the insulating layer between the electrode and the metal oxide layer, a phenomenon that electrons readily flow but holes hardly flow can be expected. Actually, as shown inFIG. 64, the value of the flowing current largely changes between a case wherein a positive voltage is applied from the drain electrode10608to the gate electrode10603and a case wherein a negative voltage is applied. In discriminating the state of the metal oxide layer10604, this has a large effect to increase the signal-to-noise ratio (S/N ratio) and facilitate state discrimination. This is the effect of use of the insulating layers10605and10606.

It was found that when the above-described “low resistance mode” and “high resistance mode” shown inFIG. 64are applied, the element shown inFIG. 106can be used as a nonvolatile nondestructive 3-terminal element. More specifically, the OFF state wherein the current between the source and drain hardly flows is set by applying a positive voltage to the gate electrode10603and a negative voltage to the drain electrode10608to change the mode from the “low resistance mode” to the “high resistance mode”, as indicated by (4) or (5) inFIG. 64.

The ON state wherein the current between the source and drain readily flows is set by applying a negative voltage to the gate electrode10603and a positive voltage of 1.6 V or more to the drain electrode10608to abruptly flow the current, as indicated by (2) inFIG. 64. With this operation, the mode is changed from the “high resistance mode” to the “low resistance mode”, and the ON state is obtained. As described above, when a voltage is applied to the gate electrode10603(drain electrode10608) to set the “high resistance mode” or “low resistance mode”, switching between the OFF state and the ON state can be done.

The ON/OFF state between the source and drain controlled in the above-described way can easily be recognized by reading a current value when an appropriate voltage of 0 to 1.6 V is applied between the source and drain. For example, when the mode state of the 3-terminal element shown inFIG. 106is “off”, i.e., “high resistance mode”, it can be determined because a current hardly flows when an appropriate voltage of 0.5 to 1.6 V is applied, as indicated by (1) inFIG. 64.

When the mode state of the element shown inFIG. 106is “on”, i.e., “low resistance mode”, it can be determined because a current abruptly flows between the source and drain when an appropriate voltage of 1 to 0.6 V is applied, as indicated by (2) inFIG. 64. Since the difference in current value between the “positive high resistance mode” and the “positive low resistance mode”, i.e., “off” and “on” is 1,000 times or more, “off” and “on” can easily be determined. Even in the negative voltage range, “off” and “on” can be determined in the voltage range of 0 to −2.6 V.

The above-described ON/OFF state of the 3-terminal element can easily be identified only by checking whether the element shown inFIG. 106is in the “high resistance mode” or “low resistance mode”. In other words, while the 3-terminal element shown inFIG. 106can hold the two modes, data is held. Even when a voltage is applied to the electrode to check the mode, the held mode does not change, and data is not destroyed. Hence, according to the 3-terminal element element shown inFIG. 106, a nondestructive operation is possible. The 3-terminal element shown inFIG. 106functions as a 3-terminal element element to control ON/OFF between the source and drain since the resistance value of the metal oxide layer10604changes depending on the voltage applied between the gate electrode10603and the drain electrode10608(or source electrode10607). This element can also be used as an element to control the current.

Even when the source electrode10607is set open, the ON state and OFF state can be controlled by applying a gate voltage. In the case wherein the source electrode10607is set open, when the read voltage is increased, a current to some extent flows between the source and drain even when a gate voltage is applied to set the OFF state. When the source electrode10607is set open, and the gate voltage is applied in this state, the applied voltage selectively acts depending on the region under the drain electrode10608. As described above, a certain source-drain current is supposed to flow when the read voltage is high. Hence, the source-drain current is supposed to flow through a path formed from the source electrode10607, the metal oxide layer10604in the region under the source electrode10607, the gate electrode10603, the metal oxide layer10604in the region under the drain electrode10608, and the drain electrode10608.

The voltage to operate the 3-terminal element shown inFIG. 106is maximized when a gate voltage to set the “positive low resistance mode” is applied. However, the voltage is about 1.6 V at most, and the power consumption is very low, as shown inFIG. 64. The low power consumption is very advantageous for devices. Devices using a 3-terminal element, e.g., not only mobile communication devices, digital general-purpose devices, digital image sensing devices, notebook personal computers, and PDAs (Personal Digital Appliances) but also all computers, personal computers, workstations, office computers, mainframes, communication units, and multifunction apparatuses can reduce the power consumption. The 3-terminal element shown inFIG. 106can also hold the ON or OFF state for 10 years.

The basic idea of the 3-terminal element shown inFIG. 106is arranging an insulating layer in contact with a metal oxide layer and sandwiching these layers by the gate electrode and the source and drain electrodes. With this structure, when a predetermined voltage (DC or pulse) is applied to the gate electrode to change the resistance value of the metal oxide layer and switch the stable high resistance mode and low resistance mode, an operation as a 3-terminal element can be implemented consequently.

For example, as shown inFIG. 108, a source electrode10617and drain electrode10618may be formed on the insulating layer10602and covered with the metal oxide layer10604on an insulating layer10616, and a gate electrode10613may be formed on the metal oxide layer10604via an insulating layer10615. As shown inFIGS. 109A and 109B, an insulating substrate10601amay be used. In this case, the insulating layer10602shown inFIG. 106can be omitted. Alternatively, the structure including the insulating layer10605, metal oxide layer10604, insulating layer10606, source electrode10607, and drain electrode10608shown inFIG. 106may be arranged on a conductive substrate. In this case, the substrate also serves as a gate electrode. When a metal substrate with high thermal conductivity is used as the conductive substrate, a higher cooling effect can be obtained, and a stable element operation can be expected.

An insulating substrate made of glass or quartz may be used. With this structure, the present invention can be applied to, e.g. a glass substrate easy to process. The metal oxide layer10604which has a refractive index of about 2.6 measured at a wavelength of 632.8 nm is optically transparent. For this reason, when a transparent substrate is used, the 3-terminal element of this embodiment can be applied to a display. When the metal oxide layer10604is formed so thick in the range of 10 to 200 nm that an interference color is generated, the visual effect of a colored state can be obtained.

Even in the 3-terminal element shown inFIG. 106, a plurality of 3-terminal elements may be arrayed and integrated in a cross-point pattern. The change in resistance value of the metal oxide layer10604can also be controlled by a current. The resistance change in the metal oxide layer10604can also be controlled by a pulse voltage. Even the 3-terminal element shown inFIG. 106can implement three states (three values) in the value of the current flowing between the source and drain.

Still another embodiment of the present invention will be described below with reference to the accompanying drawings.FIG. 110is a schematic sectional view showing a structure example of a memory element according to an embodiment of the present invention. The memory element shown inFIG. 110comprises, on a substrate11001made of, e.g., single-crystal silicon, an insulating layer11002, a gate electrode11003, a switching layer11004made of a metal oxide containing Bi, Ti, and O and having a thickness of about 30 to 200 nm, a bit electrode11005, a memory layer11006made of a metal oxide containing Bi, Ti, and O and having a thickness of about 30 to 200 nm, and a word electrode11007. In this memory element, the ground electrode11003, switching layer11004, memory layer11006, and word electrode11007are connected in series in this order, and the bit electrode11005is provided on the switching layer11004.FIG. 110shows one memory cell portion connected to each of the intersections between a plurality of bit lines and a plurality of word lines arrayed in, e.g., a matrix.

The substrate11001can be made of any one of a semiconductor, insulator, and conductive material such as a metal. When the substrate11001is made of an insulating material, the insulating layer11002can be omitted. When the substrate11001is made of a conductive material, the insulating layer11002and ground electrode11003can be omitted. In this case, the substrate11001made of the conductive material serves as a ground electrode. The ground electrode11003, bit electrode11005, and word electrode11007need only be made of a transition metal including noble metals such as platinum (Pt), ruthenium (Ru), gold (Au), silver (Ag), and titanium (Ti). The electrodes may be made of a compound such as a nitride, oxide, or fluoride of a transition metal, such as titanium nitride (TiN), hafnium nitride (HfN), strontium ruthenate (SrRuO2), zinc oxide (ZnO), indium tin oxide (ITO), or lanthanum fluoride (LaF3), or a composite film formed by stacking them.

A detailed example of the memory element shown inFIG. 110will be described. For example, the ground electrode11003is a ruthenium film having a thickness of 10 nm. The bit electrode11005is a layered film obtained by forming a ruthenium film having a thickness of 10 nm on a titanium (Ti) film having a thickness of about 20 nm. Each of the switching layer11004and memory layer11006is made of a metal oxide containing Bi and Ti and having a thickness of 40 nm. The word electrode11007is made of Au.

The switching layer11004and memory layer11006are the same as the above-described ferroelectric layer10604, ferroelectric layer310604, ferroelectric layer4705, ferroelectric layer6205, metal oxide layer8604, metal oxide layer9704, metal oxide layer10204, and metal oxide layer10604.

According to the memory element using the metal oxide layer (memory layer11006), two states (ON and OFF) can be held, as will be described below. The characteristics of the metal oxide layer having the above-described structure were investigated by applying a voltage between the bit electrode11005and the word electrode11007. When a voltage from a power supply was applied between the bit electrode11005and the word electrode11007, and a current flowing from the bit electrode11005to the word electrode11007was measured by an ammeter, the same result as inFIG. 33was obtained. Referring toFIG. 33, the ordinate represents the value of a current whose positive direction is set to the direction from the bit electrode11005to the word electrode11007.

FIG. 33and the operation principle of the memory element of the present invention will be described below. The voltage values and current values to be described here are mere examples measured in an actual element. Hence, the phenomenon is not limited to the following numerical values. Other numerical values can also be measured depending on the material and thickness of each film actually used in the element and other conditions.

FIG. 33shows the hysteresis characteristics of the values of currents which flow in the memory layer11006when the voltage applied to the bit electrode11005is decreased from 0 in the negative direction, returned to 0, increased in the positive direction, and finally returned to 0 again. When the voltage applied to the bit electrode11005is gradually decreased from 0 V in the negative direction, the negative current flowing in the memory layer11006is relatively small (about −0.12 mA at −0.1 V).

When the voltage exceeds −0.4 V, the negative current value starts increasing. After the voltage is decreased up to about −1 V, the negative voltage is decreased. The negative current value decreases while keeping the state wherein a negative current having a larger absolute value than before flows. At this time, the current value is about −0.63 mA at −0.1 V. The resistance value is lower by about five times than the previous state, and the current readily flows. When the applied voltage is returned to 0, the current value also becomes 0.

Next, a positive voltage is applied to the bit electrode11005. In this state, when the applied positive voltage is low, a relatively large positive current flows according to the previous hysteresis (about 0.63 mA at 0.1 V). When the positive voltage is applied up to about 0.7 V, the positive current suddenly decreases. Finally, the applied positive voltage is decreased from −1 V to 0 V, the positive current value also decreases while keeping the hardly current flowing state and returns to 0. At this time, the positive current is about 0.12 mA at 0.1 V.

The above-described hysteresis of the current flowing in the memory layer11006can be regarded as being generated because the resistance value of the memory layer11006changes depending on the voltage applied to the memory layer11006. A case wherein a voltage is applied to the word electrode11007will be examined. When a positive voltage VW1with a predetermined magnitude or more is applied, the memory layer11006changes to a “low resistance mode” (ON state) wherein the current easily flows. When a negative voltage VW0with a predetermined magnitude is applied, the memory layer11006changes to a “high resistance mode” (OFF state) wherein the current hardly flows.

The memory layer11006has the two stable states, i.e., low resistance mode and high resistance mode. The ON or OFF state remains unless the above-described positive or negative voltage with a predetermined magnitude or more is applied. The value of VW0described above is about −1 V. The value of VW1is about +1 V. The resistance ratio of the high resistance mode to the low resistance mode is about 10 to 100. When the above-described phenomenon that the resistance of the switching layer11004and memory layer11006is switched (changed) by the voltage is used, a nonvolatile functional element capable of a nondestructive read operation can be implemented by the memory element shown inFIG. 110.

A case wherein the above-described two states are controlled by using a DC voltage will be described next. First, a positive voltage equal to or higher than the low resistance transition voltage VW1is applied to the word electrode11007to change the memory layer11006to the low resistance mode. An ON state wherein a current readily flows is obtained. The ON state can be read out by measuring a current value JR1between the electrodes at a read voltage VR. It is important to select, as the read voltage VR, such a small value to obtain a sufficient resistance ratio and not to cause state transition (about 0.1 V in the above example). Hence, the read can be done many times without destroying the low resistance mode, i.e., ON state.

On the other hand, when a negative voltage equal to or higher than the high resistance transition voltage VW0is applied to the word electrode11007, the memory layer11006changes to the high resistance mode, i.e., OFF state wherein a current hardly flows between the electrodes. The OFF state can also be read out by measuring a current value JR0between the electrodes at the read voltage VR(JR1/JR0≅10 to 100). When the electrodes are not energized, the memory layer11006has nonvolatility to hold each state. Except in the write and read, no voltage need be applied.

The above-described characteristics with two states can also apply to the switching layer11004. The operation of the memory element shown inFIG. 110, which has the switching layer11004and memory layer11006, will be described below. The read operation will be described first. In the initial state, the switching layers11004of all memory cells are set in the high resistance state. In this state, the word electrode11007(word line) is opened, and an electrical signal to change the switching layer11004of a corresponding memory cell to the low resistance mode is applied to the bit electrode11005(corresponding bit line) to turn on the switching layer11004serving as a switch. Next, the bit electrode11005(bit line) is opened, and a read voltage is applied to the word electrode11007(word line). When the resistance value of the memory layer11006is measured in this state, the data is read out. Finally, the word electrode11007(word line) is opened, and an electrical signal to change the switching layer11004to the high resistance mode is applied to the bit electrode11005to turn off the switching layer11004serving as a switch.

The write operation will be described next. An electrical signal to change the memory layer11006to the high resistance mode or low resistance mode is applied to the word line and bit line corresponding to a memory cell as a write target. The signal applied to the bit line side at this time corresponds to a voltage not to change the resistance state of the switching layer11004. With this operation, the memory layer11006of the memory cell (memory element) as a write target is changed to the desired high resistance mode or low resistance mode, thereby writing data.

The above-described read and write operations are executed in accordance with, e.g., the flow shown inFIG. 111. First, the word electrode11007is opened, and the low resistance transition voltage VW1is applied to the bit electrode11005to change the switching layer11004of the memory element to the “ON” state, i.e., readable state. Next, when the bit electrode is opened, and the read voltage VRis applied to the word electrode11007, the state of the memory layer11006can be read out. After that, the word electrode11007is opened, and the high resistance transition voltage VW0is applied to the bit electrode11005to change the switching layer11004of the memory element to the “OFF” state, i.e., unreadable state.

After that, when a write word signal having a voltage about ½ the low resistance transition voltage VW1is applied to the word electrode11007, and a write bit signal having a voltage about ½ the low resistance transition voltage VW1and a polarity opposite to the above-described signal is applied to the bit electrode11005, a “write state” of “1” is obtained. When a signal is applied to the word electrode11007and bit electrode11005, as described above, a voltage equal to the low resistance transition voltage VW1is applied to the memory layer11006. The memory layer11006is set in the low resistance mode. Hence, “1” is written in this “write state”. To the contrary, when a write word signal having a voltage about ½ the high resistance transition voltage VW0is applied to the word electrode11007, and a write bit signal having a voltage about ½ the high resistance transition voltage VW0and a polarity opposite to the above-described signal is applied to the bit electrode11005, the memory layer11006is set in a “write state” of “0”. In either “write state”, since only a voltage about ½ each transition voltage is applied to the switching layer11004, the resistance state does not change.

As described above, according to the memory element shown inFIG. 110, the “ON” state and “OFF” state of the memory cell are switched by using the switching layer11004. When the switching layer11004is set in the “OFF” state independently of the resistance state of the memory layer11006, the leakage current (interference current) from an unselected memory cell can be suppressed. According to the element shown inFIG. 110, the above-described switching between “ON” and “OFF” is done by the switching layer11004made of a metal oxide, like the memory layer11006. Since no element made of another material such as a MOS transistor using a semiconductor such as silicon need be used, materials applicable to the substrate11001are not limited.

In the above-described embodiment, the applied gate voltage is a DC voltage. However, the same effect can be obtained even by applying a pulse voltage having appropriate width and magnitude. As for the ON or OFF state holding time of the memory element shown inFIG. 110, the element has a holding time of at least 1,000 min, like the above-described elements.

An example of a method of manufacturing the memory element shown inFIG. 110will be described next. A method of forming each thin film by using ECR plasma sputtering will be described below. However, the present invention is not limited to this, and any other film formation technique or method can be used, as a matter of course.

As shown inFIG. 112A, the p-type silicon substrate11001having a plane orientation of (100) on the principal plane and a resistivity of 1 to 2 Ωcm is prepared. The surface of the substrate11001is cleaned by a solution mixture of sulfuric acid and a hydrogen peroxide solution, pure water, and a hydrogen fluoride solution and dried. The insulating layer11002is formed on the cleaned and dried substrate11001. In forming the insulating layer11002, e.g., an ECR sputtering apparatus and pure silicon (Si) as a target are used. The insulating layer11002in a metal mode by Si—O molecules is formed on the silicon substrate11001to a thickness to just cover its surface by ECR sputtering using argon (Ar) as a plasma gas and oxygen gas.

For example, Ar gas is supplied at a flow rate of 20 sccm into a plasma production chamber whose internal pressure is set on the order of 10−5Pa. The internal pressure is set to about 10−3to 10−2Pa. A magnetic field of 0.0875 T and a microwave of 2.45 GHz (about 500 W) are supplied to set the electron cyclotron resonance condition, thereby producing Ar plasma in the plasma production chamber. Note that sccm is the unit of flow rate and indicates that a fluid at 0° C. and 1 atmospheric pressure flows 1 cm3in 1 min. T (tesla) is the unit of magnetic flux density, and 1 T=10,000 gauss.

The plasma produced by the above-described method is output from the plasma production chamber to the process chamber side by the divergent magnetic field of the magnetic coil. In addition, a high-frequency power of 13.56 MHz (e.g., 500 W) is supplied from a high-frequency power supply to the silicon target placed at the outlet of the plasma production chamber. When Ar ions collide against the silicon target, a sputtering phenomenon occurs to sputter Si particles. The Si particles sputtered from the silicon target reach the surface of the silicon substrate11001together with the plasma output from the plasma production chamber and the oxygen gas which is supplied and activated by the plasma and are oxidized to silicon dioxide by the activated oxygen. With the above process, the insulating layer11002made of silicon dioxide and having a thickness of, e.g., about 100 nm can be formed on the substrate11001(FIG. 112A).

The insulating layer11002ensures insulation to prevent a voltage from leaking to the substrate11001and influencing desired electrical characteristics when a voltage is applied between the electrodes to be formed later. For example, a silicon oxide film formed by oxidizing the surface of the silicon substrate by thermal oxidation may be used as the insulating layer11002. The insulating layer11002may be made of any other insulating material except silicon oxide if the insulating properties can be ensured. The thickness of the insulating layer11002need not always be 100 nm and may be smaller or larger. In the above-described formation of the insulating layer11002by ECR sputtering, the substrate11001is not heated. However, the film may be formed while heating the substrate11001.

After the insulating layer11002is formed in the above-described manner, a ruthenium film is formed on the insulating layer11002by similar ECR sputtering using pure ruthenium (Ru) as a target, thereby forming the ground electrode11003, as shown inFIG. 112B. Formation of the Ru film will be described in detail. In an ECR sputtering apparatus using a Ru target, for example, the silicon substrate with the insulating layer formed on it is heated to 400° C. Ar gas as a rare gas is supplied into the plasma production chamber at a flow rate of, e.g., 7 sccm. In addition, Xe gas is supplied at a flow rate of, e.g., 5 sccm to set the internal pressure of the plasma production chamber to on the order of, e.g., 10−2to 10−3Pa.

The magnetic field of the electron cyclotron resonance condition is given to the plasma production chamber. Then, a microwave of 2.45 GHz (about 500 W) is supplied into the plasma production chamber to produce ECR plasma of Ar and Xe in it. The produced ECR plasma is output from the plasma production chamber to the process chamber side by the divergent magnetic field of the magnetic coil. In addition, a high-frequency power of 13.56 MHz (e.g., 500 W) is supplied to the ruthenium target placed at the outlet of the plasma production chamber. The sputtering phenomenon occurs to sputter Ru particles from the ruthenium target. The Ru particles sputtered from the ruthenium target reach the surface of the insulating layer11002on the substrate11001and are deposited.

With the above process, the ground electrode11003having a thickness of, e.g., about 10 nm can be formed on the insulating layer11002(FIG. 112B). The ground electrode11003enables voltage application to the switching layer11004when a voltage is applied to the bit electrode11005to be formed later. The ground electrode11003may be made of any other material except ruthenium if the conductivity can be ensured. The ground electrode11003may be made of, e.g., platinum. A platinum film formed on silicon dioxide readily peels off, as is known. To prevent this, a layered structure is formed by inserting a titanium layer, titanium nitride layer, or ruthenium layer under the platinum layer. The thickness of the ground electrode11003need not always be 10 nm and may be smaller or larger.

As described above, in forming the Ru film by ECR sputtering, the substrate11001is heated to 400° C. However, the substrate need not always be heated. However, if the substrate is not heated, the adhesion of ruthenium to silicon dioxide becomes low, and the film may peel off. To prevent peeling, the film is formed preferably while heating the substrate.

After the ground electrode11003is formed in the above-described manner, the switching layer11004is formed on the ground electrode11003to a thickness to just cover its surface, as shown inFIG. 112C, by ECR sputtering using argon (Ar) as a plasma gas and oxygen gas and a target formed from an oxide sintered body (Bi—Ti—O) in which the ratio of Bi to Ti is 4:3.

Formation of the switching layer11004will be described in detail. The substrate11001is heated to 300° C. to 700° C. Ar gas as a rare gas is supplied into the plasma production chamber at a flow rate of, e.g., 20 sccm to set the pressure on the order of, e.g., 10−3to 10−2Pa. In this state, the magnetic field of the electron cyclotron resonance condition is given to the plasma production chamber. Then, a microwave of 2.45 GHz (about 500 W) is supplied into the plasma production chamber to produce ECR plasma in it.

The produced ECR plasma is output from the plasma production chamber to the process chamber side by the divergent magnetic field of the magnetic coil. In addition, a high-frequency power of 13.56 MHz (e.g., 500 W) is supplied to the sintered body target placed at the outlet of the plasma production chamber. When Ar particles collide against the sintered body target, the sputtering phenomenon occurs to sputter Bi particles and Ti particles.

The Bi particles and Ti particles sputtered from the sintered body target reach the surface of the heated ground electrode11003together with the ECR plasma output from the plasma production chamber and the oxygen gas activated by the output ECR plasma and are oxidized by the activated oxygen. The oxygen (O2) gas serving as a reactive gas is supplied at a flow rate of, e.g., 1 sccm separately from the Ar gas, as will be described later. Although the sintered body target contains oxygen, any shortage of oxygen in the deposited film can be prevented by supplying oxygen. With the above-described film formation by ECR sputtering, the switching layer11004having a thickness of, e.g., about 40 nm can be formed (FIG. 112C).

The film quality may be improved by irradiating the formed switching layer11004with ECR plasma of an inert gas and a reactive gas. As the reactive gas, not oxygen gas but nitrogen gas, fluorine gas, or hydrogen gas can be used. The film quality improvement can also be applied to formation of the insulating layer11002. The switching layer11004may be formed at a low substrate temperature of 300° C. or less and then annealed (heat-treated) in an appropriate gas atmosphere such as oxygen atmosphere to greatly improve the properties of the film.

After the switching layer11004is formed in the above-described manner, a Ti film having a thickness of about 20 nm is formed by ECR sputtering. Next, a ruthenium film having a thickness of about 10 nm is formed again by the same ECR sputtering as described above using pure ruthenium (Ru) as a target, thereby forming the bit electrode11005having a layered structure on the switching layer11004, as shown inFIG. 112D. Formation of the ruthenium film is the same as the above-described formation of the ground electrode11003. Next, the memory layer11006is formed on the bit electrode11005to a thickness to just cover its surface, as shown inFIG. 112E, by ECR sputtering using argon (Ar) as a plasma gas and oxygen gas and a target formed from an oxide sintered body (Bi—Ti—O) in which the ratio of Bi to Ti is 4:3. Formation of the memory layer11006is the same as the above-described formation of the switching layer11004.

After the memory layer11006is formed in the above-described way, the word electrode11007made of Au is formed on the memory layer11006, thereby obtaining the memory element shown inFIG. 110. The word electrode11007can be formed by gold deposition by resistance heating vacuum deposition. The word electrode11007may be made of another metal material or conductive material such as Ru, Pt, or TiN. When Pt is used, the adhesion is poor, and the film may peel off. Hence, a structure such as Ti—Pt—Au that hardly peels off needs to be employed. The switching layer11004, bit electrode11005, memory layer11006, and word electrode11007are formed into a memory cell structure by forming a layered structure thereof and patterning it by well-known photolithography and etching.

The above-described layer formation by ECR sputtering is done by using an ECR sputtering apparatus shown inFIG. 112.

The memory element according to this embodiment is not limited to the structure example shown inFIG. 110. For example, as shown inFIG. 113A, a switching layer and memory layer11016may be arrayed in the in-plane direction of the substrate11001in one memory cell. In the memory element shown inFIG. 113A, a ground electrode11013and a connection electrode11015bspaced apart from it are arranged on the insulating layer11002. The switching layer11014is formed across the ground electrode11013and connection electrode11015b. The memory layer11016is formed in contact with the connection electrode11015b. A bit electrode11015ais formed on the switching layer11014. A word electrode11017is formed on the memory layer11016.

As described above, the connection electrode11015bconnected to the surface of the switching layer11014in the first direction is newly provided. The connection electrode11015bis connected to the first-direction surface of the memory layer11016. The ground electrode11013is connected to the first-direction surface of the switching layer11014while being isolated from the connection electrode11015b. The bit electrode11015ais connected to the surface of the switching layer11014in the second direction different from the first direction. The word electrode11017is connected to the second-direction surface of the memory layer11016. Even in this structure, the ground electrode11013, switching layer11014, memory layer11016, and word electrode11017are connected in series in this order, like the element shown inFIG. 110. Hence, the components may be reversed in the vertical direction on the substrate11001on the drawing surface ofFIG. 113A.

An operation example of the memory element shown inFIG. 113Awill be described. In the read, the switching layer11014is set in a high resistance “OFF” state. In this initial state, the connection electrode11015bis grounded, and a low resistance transition voltage (e.g., pulse voltage) is applied to the bit electrode11015aof a corresponding memory cell to turn on the switching layer11014. Next, the connection electrode11015band bit electrode11015a(corresponding bit line) are opened. A read voltage is applied to the word electrode11017(corresponding word line). When the resistance value of the memory layer11016is measured, data is read out. Finally, the connection electrode11015bis grounded, and an electrical signal (e.g., pulse voltage) to change the switching layer11014to the high resistance mode is applied to the bit electrode11015ato turn off the switching layer11014serving as a switch.

In the write operation of the memory element shown inFIG. 113A, the connection electrode11015bis grounded, and a write voltage is applied to a word line corresponding to the memory cell as a write target. For example, to set a “write state” of “1”, the low resistance transition voltage is applied to the word electrode11017. To set a “write state” of “0”, the high resistance transition voltage is applied to the word electrode11017.

The memory element of the present invention may have the structure shown inFIG. 113B. In the memory element shown inFIG. 113B, a bit electrode11025ais arranged on the insulating layer11002. A switching layer11024is formed on the bit electrode11025a. A ground electrode11023and a connection electrode11025bspaced part from it are arranged on the switching layer11024. A memory layer11026is formed on the connection electrode11025b. A word electrode11027is formed on the memory layer11026.

As described above, the connection electrode11025bconnected to the surface of the switching layer11024in the first direction is newly provided. The connection electrode11025bis connected to the surface of the memory layer11026in the second direction different from the first direction. The ground electrode11023is connected to the first-direction surface of the switching layer11024. The bit electrode11025ais connected to the second-direction surface of the switching layer11024. The word electrode11027is connected to the first-direction surface of the memory layer11026. Even in this structure, the ground electrode11023, switching layer11024, memory layer11026, and word electrode11027are connected in series in this order, like the element shown inFIG. 110. Hence, the components may be reversed in the vertical direction on the substrate11001on the drawing surface ofFIG. 113B.

The memory element of the present invention may have an insulating layer between the electrode and the metal oxide layer, as shown inFIG. 114. The memory element shown inFIG. 114Acomprises an insulating layer11008between the bit electrode11005and the memory layer11006. The memory element shown inFIG. 114Bcomprises an insulating layer11009between the ground electrode11003and the switching layer11004. The memory element shown inFIG. 114Ccomprises both the insulating layers11008and11009.

In applying a voltage from the insulating layer11008or11009to memory layer11006or switching layer11004, the voltage applied to each layer can be controlled. When an insulating layer is formed, and the switching layer11004or memory layer11006is formed on it, the switching layer11004or memory layer11006can be formed without degrading the morphology of the surface of the underlying metal film or the surface of the metal oxide layer in the above-described formation by ECR sputtering. For example, if the underlying layer is made of a metal material which is readily oxidized, the surface of the underlying layer may be partially oxidized in formation of the switching layer11004, resulting in degradation in morphology. However, when an insulating layer is inserted, the switching layer11004can be formed while keeping the good surface morphology of the underlying layer. Hence, the switching layer11004with higher quality can be obtained.

As shown inFIG. 115, an insulating layer11018, insulating layer11019, insulating layer11028, and insulating layer11029may be provided. The memory element shown inFIG. 115Acomprises the insulating layer11018between the connection electrode11015band the memory layer11016. The memory element shown inFIG. 115Bcomprises the insulating layer11019between the switching layer11014and the bit electrode11015a. The memory element shown inFIG. 115Ccomprises the insulating layer11018between the connection electrode11015band the memory layer11016and the insulating layer11019between the switching layer11014and the bit electrode11015a. The memory element shown inFIG. 115Dcomprises the insulating layer11028between the switching layer11024and the connection electrode11025b. The memory element shown inFIG. 115Ecomprises the insulating layer11029between the bit electrode11025aand the switching layer11024. The memory element shown inFIG. 115Fcomprises the insulating layer11028between the switching layer11024and the connection electrode11025band the insulating layer11029between the bit electrode11025aand the switching layer11024.

FIGS. 114 and 115show examples of a form including an insulating layer, and the present invention is not limited to those. The above-described insulating layer need only be provided in contact with the switching layer and memory layer. The insulating layer may be provided in contact with either the surface of one of the switching layer and memory layer or the surfaces of both the switching layer and memory layer. The insulating layer need only be provided between the metal oxide layer of the switching layer or memory layer and one of electrodes connected to it.

As the metal oxide layer of the switching layer11004or memory layer11006becomes thick, the current flows more hardly, and the resistance increases. When memory element is implemented by using a change in resistance value, the resistance value of in each of the low resistance mode and high resistance mode is important. For example, when the metal oxide layer becomes thick, the resistance value in the low resistance mode increases. Since it is difficult to ensure a high S/N ratio, the ON or OFF state is hard to determine. On the other hand, when the metal oxide layer becomes thin, and the leakage current is dominant, the ON or OFF state can hardly be held, and the resistance value in the high resistance mode decreases. It is therefore difficult to ensure a high S/N ratio.

Hence, the metal oxide layer preferably has an optimum thickness. For example, when the problem of leakage current is taken into consideration, the metal oxide layer need only have a thickness of at least 10 nm. When the resistance value in the low resistance mode is taken into consideration, the metal oxide layer is preferably thinner than 300 nm. In experiments conducted by the present inventors, the operation of the memory element was confirmed when the thickness of the metal oxide layer was 30 to 200 nm.

According to the memory element shown inFIG. 110, a multilevel operation is also possible. For example, in the current-voltage characteristic of the memory layer11006when a voltage is applied between the bit electrode11005(and the word electrode11007), when the applied voltage is changed, the low resistance mode changes to a different low resistance state, as shown inFIG. 116. InFIG. 116, the current value at the read voltage shown inFIG. 116changes between the low resistance mode after a voltage up to −0.5 V is applied, the low resistance mode after a voltage up to −1.0 V is applied, and the low resistance mode after a voltage up to −1.5 V is applied. These states can be read out by applying a read voltage between the electrodes and measuring a current flowing between the electrodes. Three states (three values) “0”, “1”, and “2” can be implemented in correspondence with the inter-electrode currents obtained by a predetermined read voltage.

According to the element shown inFIG. 110, a multilevel state can be implemented by the difference in pulse voltage value. As shown inFIG. 117, every time a predetermined pulse voltage with a predetermined pulse width is applied a predetermined number of times, the current value between the electrodes is read out at a read voltage of 0.2 V at a point indicated by a triangle. Then, as shown inFIG. 118, three states (three values) “0”, “1”, and “2” are obtained. In this example, the memory is reset by the state “2”.

For example, when the insulating layer11008is provided between the bit electrode11005and the memory layer11006, as shown inFIG. 114A, the current-voltage characteristic of the memory layer11006is changed as shown inFIG. 46by changing the voltage applied to the word electrode11007. In this case, for example, when the read voltage is about 0.5 V, ternary states can be implemented.

In many cases, a plurality of elements using a thin film made of a metal oxide as described above are monolithically integrated on a single substrate. When a plurality of elements are integrated in this way, adjacent elements are isolated, as shown in, e.g.,FIG. 12D. The element isolation structure is formed in the following way. As shown inFIG. 119A, an insulating layer1602is formed on a substrate1601. A metal film1623is formed on the insulating layer1602. As shown inFIG. 119B, a ferroelectric thin film1614is formed on the metal film1623. As shown inFIG. 119C, a metal film1615is formed on the ferroelectric thin film1614.

As shown inFIG. 119D, a plurality of mask patterns1620are formed on the metal film1615. The metal film1615and ferroelectric thin film1614are selectively removed by etching using the mask pattern1620as a mask to form a plurality of elements each including a ferroelectric layer1604and upper electrode1606on a lower electrode layer1613, as shown inFIG. 119E. After that, the mask patterns1620are removed. An insulating material is deposited between the elements to form element isolation insulating layers1605between the elements, as shown inFIG. 119F.

As described above, in the conventional element isolation, a thin film serving as a ferroelectric layer is formed, a plurality of element portions are formed by processing the thin film, and insulating layers for element isolation are formed between the elements. Conventionally, to obtain an element isolation structure, a number of thin film formation steps and thin film processing steps are required, resulting in an increase in number of steps. Especially, in the processing step, photolithography and etching are used in general. For this reason, one pattern must be formed using a number of steps.

Unlike the above-described situation, when elements are isolated in a manner to be described below, the element isolation structure can be formed without requiring many steps.

Element isolation will be described below with reference to the accompanying drawings.FIG. 120is a schematic sectional view showing a structure example of the element isolation structure according to the embodiment of the present invention. As shown inFIG. 120, in the element isolation structure shown inFIG. 120, an insulating layer102is provided on a substrate101, and a plurality of elements each including a lower electrode103formed on the insulating layer102, a ferroelectric layer104having a thickness of about 30 to 200 nm, and an upper electrode136are isolated by an isolation layer135. The ferroelectric layer104is formed on the lower electrode103made of a crystalline material. The isolation layer135is formed on the insulating layer102made of an amorphous material.

The ferroelectric layer104and isolation layer135are made of, e.g., Bi, Ti, and O and contain a plurality of microcrystalline grains of Bi4Ti3O12crystal having a stoichiometric composition and a grain size of about 3 to 15 nm. The ferroelectric layer104also contains column crystal with the stoichiometric composition of Bi4Ti3O12in addition to the microcrystalline grains. The isolation layer135having the above-described structure has a higher electrical resistance than the ferroelectric layer104so that the dielectric isolation for a breakdown voltage is large. On the other hand, the ferroelectric layer104has two stable states, i.e., low resistance state and high resistance state, as will be described later. An element using the ferroelectric layer104is a functional element to hold two states.

An example of a method of manufacturing the element isolation structure shown inFIG. 120will be described next. As shown inFIG. 121A, the p-type silicon substrate101having a plane orientation of (100) on the principal plane and a resistivity of 1 to 2 Ωcm is prepared. The surface of the substrate101is cleaned by a solution mixture of sulfuric acid and a hydrogen peroxide solution, pure water, and a hydrogen fluoride solution and dried. The insulating layer102is formed on the cleaned and dried substrate101. In forming the insulating layer102, e.g., an ECR sputtering apparatus and pure silicon (Si) as a target are used. ECR sputtering is executed by using argon (Ar) as a plasma gas and oxygen gas. The insulating layer102in a metal mode by Si—O molecules is formed on the silicon substrate101to a thickness to just cover its surface by ECR sputtering.

For example, Ar gas is supplied at a flow rate of 20 sccm into a plasma production chamber whose internal pressure is set on the order of 10−5Pa. The internal pressure is set to about 10−3to 10−2Pa. A magnetic field of 0.0875 T and a microwave of 2.45 GHz (about 500 W) are supplied to set the electron cyclotron resonance condition, thereby producing Ar plasma in the plasma production chamber. Note that sccm is the unit of flow rate and indicates that a fluid at 0° C. and 1 atmospheric pressure flows 1 cm3in 1 min. T (tesla) is the unit of magnetic flux density, and 1 T=10,000 gauss.

The plasma produced by the above-described method is output from the plasma production chamber to the process chamber side by the divergent magnetic field of the magnetic coil. In addition, a high-frequency power of 13.56 MHz (e.g., 500 W) is supplied from a high-frequency power supply to the silicon target placed at the outlet of the plasma production chamber. When Ar ions collide against the silicon target, a sputtering phenomenon occurs to sputter Si particles. The Si particles sputtered from the silicon target reach the surface of the silicon substrate101together with the plasma output from the plasma production chamber and the oxygen gas which is supplied and activated by the plasma and are oxidized to silicon dioxide by the activated oxygen. With the above process, the insulating layer102made of silicon dioxide and having a thickness of, e.g., about 100 nm can be formed on the substrate101.

The insulating layer102ensures insulation to prevent a voltage from leaking to the substrate101and influencing desired electrical characteristics when a voltage is applied between the electrodes to be formed later. For example, a silicon oxide film formed by oxidizing the surface of the silicon substrate by thermal oxidation may be used as the insulating layer102. The insulating layer102may be made of any other insulating material except silicon oxide if the insulating properties can be ensured. The thickness of the insulating layer102need not always be 100 nm and may be smaller or larger. In the above-described formation of the insulating layer102by ECR sputtering, the substrate101is not heated. However, the film may be formed while heating the substrate101.

After the insulating layer102is formed in the above-described manner, a ruthenium film is formed on the insulating layer102by similar ECR sputtering using pure ruthenium (Ru) as a target. Formation of the Ru film will be described in detail. In an ECR sputtering apparatus using a Ru target, for example, the silicon substrate with the insulating layer formed on it is heated to 400° C. Ar gas as a rare gas is supplied into the plasma production chamber at a flow rate of, e.g., 7 sccm. In addition, Xe gas is supplied at a flow rate of, e.g., 5 sccm to set the internal pressure of the plasma production chamber to on the order of, e.g., 10−2to 10−3Pa.

The magnetic field of the electron cyclotron resonance condition is given to the plasma production chamber. Then, a microwave of 2.45 GHz (about 500 W) is supplied into the plasma production chamber to produce ECR plasma of Ar and Xe in it. The produced ECR plasma is output from the plasma production chamber to the process chamber side by the divergent magnetic field of the magnetic coil. In addition, a high-frequency power of 13.56 MHz (e.g., 500 W) is supplied to the ruthenium target placed at the outlet of the plasma production chamber. The sputtering phenomenon occurs to sputter Ru particles from the ruthenium target. The Ru particles sputtered from the ruthenium target reach the surface of the insulating layer102on the substrate101and are deposited.

With the above process, a metal film made of Ru and having a thickness of, e.g., about 10 nm can be formed on the insulating layer102. When the metal film is patterned by known lithography and etching, the plurality of lower electrodes103arranged while spaced apart from each other are formed, as shown inFIG. 121A. When ruthenium is irradiated with oxygen plasma, ozone, or oxygen radicals, a ruthenium oxide (e.g., RuO2or RuO4) having a high vapor pressure is formed, as is known. When ruthenium is oxidized by irradiation through a mask by using the above nature, selective etching can be done.

The dry etching using oxygen plasma, ozone, or oxygen radicals is an isotropic etching process so that so-called undercuts may be produced in the sectional shape after etching. To avoid this, the ruthenium film may be irradiated with plasma of a gas prepared by adding argon to oxygen. When anisotropy is imparted to etching in this way, a pattern without undercut can be formed.

The lower electrode103enables voltage application to the ferroelectric layer104when a voltage is applied between the lower electrode103and the upper electrode136to be formed later. The lower electrode103may be made of any other material except ruthenium if the conductivity can be ensured. The lower electrode103may be made of, e.g., platinum. A platinum film formed on silicon dioxide readily peels off, as is known. To prevent this, a layered structure is formed by inserting a titanium layer, titanium nitride layer, or ruthenium layer under the platinum layer. Platinum cannot be etched by oxygen plasma, unlike ruthenium. Patterning for electrode formation can be done by using a known lift-off method. The thickness of the lower electrode103need not always be 10 nm and may be smaller or larger.

As described above, in forming the Ru film by ECR sputtering, the substrate101is heated to 400° C. However, the substrate need not always be heated. However, if the substrate is not heated, the adhesion of ruthenium to silicon dioxide becomes low, and the film may peel off. To prevent peeling, the film is formed preferably while heating the substrate.

After the lower electrode103is formed in the above-described manner, the ferroelectric layer104is formed on the lower electrode103, and the isolation layer135is formed on the insulating layer102, as shown inFIG. 121B, by ECR sputtering using argon (Ar) as a plasma gas and oxygen gas and a target formed from an oxide sintered body (Bi—Ti—O) in which the ratio of Bi to Ti is 4:3. Formation of the ferroelectric layer104and isolation layer135will be described. The substrate101is heated to 400° C. to 450° C. Ar gas as a rare gas is supplied into the plasma production chamber at a flow rate of, e.g., 20 sccm to set the pressure on the order of, e.g., 10−3to 10−2Pa. In this state, the magnetic field of the electron cyclotron resonance condition is given to the plasma production chamber. Then, a microwave of 2.45 GHz (about 500 W) is supplied into the plasma production chamber to produce ECR plasma in it.

The produced ECR plasma is output from the plasma production chamber to the process chamber side by the divergent magnetic field of the magnetic coil. In addition, a high-frequency power of 13.56 MHz (e.g., 500 W) is supplied to the sintered body target placed at the outlet of the plasma production chamber. When Ar particles collide against the sintered body target, the sputtering phenomenon occurs to sputter Bi particles and Ti particles. The Bi particles and Ti particles sputtered from the sintered body target reach the surfaces of the heated insulating layer102and lower electrode103together with the ECR plasma output from the plasma production chamber and the oxygen gas activated by the output ECR plasma and are oxidized by the activated oxygen.

The oxygen (O2) gas serving as a reactive gas is supplied at a flow rate of, e.g., 1 sccm separately from the Ar gas, as will be described later. Although the sintered body target contains oxygen, any shortage of oxygen in the deposited film can be prevented by supplying oxygen. With the above-described film formation by ECR sputtering, the ferroelectric layer104and isolation layer135each having a thickness of, e.g., about 40 can be formed (FIG. 121B). The isolation layer135formed on the insulating layer102in an amorphous state contains a plurality of microcrystalline grains of Bi4Ti3O12crystal having a stoichiometric composition and a grain size of about 3 to 15 nm. The ferroelectric layer104formed on the lower electrode103in a crystalline state also contains column crystal with the stoichiometric composition of Bi4Ti3O12in addition to the microcrystalline grains.

As shown inFIG. 121C, a metal film146made of, e.g., Au is formed on the ferroelectric layer104and isolation layer135. As shown inFIG. 121D, resist patterns150are formed on portions as prospective elements by well-known lithography. The metal film146is patterned by dry etching using the resist patterns150as a mask to form the upper electrodes136on the ferroelectric layers104, as shown inFIG. 121E. When the resist patterns150are removed then, the element isolation structure shown inFIG. 120is obtained. The upper electrode136may be made of another metal material or conductive material such as Ru, Pt, or TiN. When Pt is used, the adhesion is poor, and the film may peel off. Hence, the upper electrode136must be formed as an electrode by forming a structure such as Ti—Pt—Au that hardly peels off and executing a patterning process by photolithography on that structure.

The above-described layer formation by ECR sputtering is done by using an ECR sputtering apparatus shown inFIG. 5.

In the film formation condition range wherein microcrystalline grains are observed, as shown in FIGS.7B and7B′, the base layer is amorphous, or column crystal is observed in it. In either case, the state of the microcrystalline grains does not change. The size of the observed microcrystalline grains is about 3 to 15 nm. In the film formation range wherein the microcrystalline grains are observed, different dependences are exhibited depending on the underlayer condition and temperature condition of the layer to be formed, as shown inFIG. 122. Temperatures to generate states “amorphous”, “microcrystalline grains are dispersed”, “dispersed microcrystalline grains and column crystal are mixed”, and “column-crystal or single-crystal ferroelectric” change between film formation on an amorphous material such as oxide silicon and film formation on a crystal material such as ruthenium.

As shown inFIG. 122, on an amorphous material, an “amorphous” state is obtained under a film formation condition up to 350° C. “Microcrystalline grains are dispersed” under a film formation condition from 350° C. to 500° C. “Dispersed microcrystalline grains and column crystal are mixed” under a film formation condition from 500° C. to 540° C. A “column-crystal or single-crystal ferroelectric” is obtained under a film formation condition of 540° C. or more. On the other hand, on a crystal material, an “amorphous” state is obtained under a film formation condition up to 300° C. “Microcrystalline grains are dispersed” under a film formation condition from 300° C. to 450° C. “Dispersed microcrystalline grains and column crystal are mixed” under a film formation condition from 450° C. to 530° C. A “column-crystal or single-crystal ferroelectric” is obtained under a film formation condition of 530° C. or more.

Hence, when the film formation condition is set to 450° C. to 500° C. in a temperature range T shown inFIG. 122, a film in which “microcrystalline grains are dispersed” is formed on an amorphous material, and a film in which “dispersed microcrystalline grains and column crystal are mixed” is formed on a crystal material.

The film in which “microcrystalline grains are dispersed” and the film in which “dispersed microcrystalline grains and column crystal are mixed” will be described next. A sample element A is prepared by forming a film in which “microcrystalline grains are dispersed” (thickness: about 50 nm) on a lower electrode made of ruthenium at a temperature lower than 450° C. and forming an upper electrode made of gold on the film. A sample element B is prepared by forming a film in which “dispersed microcrystalline grains and column crystal are mixed” (thickness: about 50 nm) on a lower electrode made of ruthenium at a temperature of 450° C. to 500° C. and forming an upper electrode made of gold on the film.

FIG. 123shows a result obtained when a voltage was applied to the upper electrode and lower electrode in each of the above-described sample elements A and B, and the state of a current flowing between the upper electrode and the lower electrode was measured. As shown inFIG. 123, in the sample element A, even when a voltage of about 10 V is applied, no large current flows. To the contrary, in the sample element B, when a voltage of about 2 V is applied, a large current flows. That is, the dielectric isolation for a breakdown voltage is larger in the film in which “microcrystalline grains are dispersed” than the film in which “dispersed microcrystalline grains and column crystal are mixed”.

After the EO process of applying a high voltage in the film formation initial state is executed to flow a current as shown inFIG. 123, these films exhibit a current-voltage characteristic (resistance change characteristic) to repeat the high resistance state and low resistance state in accordance with the applied voltage, as will be described later.

When the film in which “microcrystalline grains are dispersed” and film in which “dispersed microcrystalline grains and column crystal are mixed” undergo the EO process, they exhibit the resistance change characteristic shown inFIG. 124. As shown inFIG. 123, although the film in which “microcrystalline grains are dispersed” requires voltage application of 10 V or more for the EO process, the EO process of the film in which “dispersed microcrystalline grains and column crystal are mixed” can be executed by voltage application of about 2 V. Although the film in which “dispersed microcrystalline grains and column crystal are mixed” can be EO-processed by applying a voltage of about 2 V to obtain the resistance change characteristic, the film in which “microcrystalline grains are dispersed” is not EO-processed by the same voltage application and exhibits no resistance change characteristic.

When the film in which “dispersed microcrystalline grains and column crystal are mixed” is used as the ferroelectric layer104, and the film in which “microcrystalline grains are dispersed” is used as the isolation layer135, an element isolation structure can be obtained in which a plurality of elements using the ferroelectric layer104with the resistance change characteristic are isolated by the isolation layers135having a high resistance. As described above, by changing the underlayer condition, the ferroelectric layer104and isolation layer135can be formed simultaneously under the same sputtering film formation condition in the same temperature range T.

The above-described resistance change characteristics will be described next. The characteristics were investigated by applying a voltage between the lower electrode103and the upper electrode136. When a voltage from a power supply was applied between the lower electrode103and the upper electrode136after the above-described EO process, and a current flowing when the voltage was applied was measured by an ammeter, a result shown inFIG. 124was obtained. Referring toFIG. 124, the ordinate represents the current density obtained by dividing the current value by the area.FIG. 124and the operation principle of each element isolated by the element isolation structure shown inFIG. 120will be described below. The voltage values and current values to be described here are mere examples measured in an actual element. Hence, the phenomenon is not limited to the following numerical values. Other numerical values can also be measured depending on the material and thickness of each film actually used in the element and other conditions.

FIG. 124shows the hysteresis characteristics of the values of currents which flow in the ferroelectric layer104when the voltage applied to the upper electrode136is increased from 0 in the positive direction, returned to 0, decreased in the negative direction, and finally returned to 0 again. When the voltage applied to the upper electrode136is gradually increased from 0 V in the positive direction, the positive current flowing in the ferroelectric layer104is relatively small (about 0.4 μA at 0.1 V).

When the voltage exceeds 0.5 V, the positive current value starts abruptly increasing. After the voltage is increased up to about 1 V, the positive voltage is decreased. Even when the voltage decreases from 1 V to about 0.7 V, the positive current value further increases. When the voltage is lower than about 0.7 V, the current value also starts decreasing. At this time, the positive current readily flows as compared to the previous state. The current value is about 4 μA at 0.1 V (10 times the previous current value). When the applied voltage is returned to 0, the current value also becomes 0.

Next, a negative voltage is applied to the upper electrode136. In this state, when the negative voltage is low, a relatively large negative current flows according to the previous hysteresis. When the applied negative voltage is changed up to about −0.5 V, the negative current suddenly starts decreasing. Even when the applied negative voltage is changed up to about −1 V, the negative current value continuously decreases. Finally, the applied negative voltage is decreased from −1 V to 0 V, the negative current value further decreases together and returns to 0. In this case, the negative current hardly flows and about −0.5 μA at −0.1 V.

The above-described hysteresis of the current flowing in the ferroelectric layer104can be regarded as being generated because the resistance value of the ferroelectric layer104changes depending on the voltage applied to the upper electrode136, as described above. When a positive voltage VW1with a predetermined magnitude or more is applied, the ferroelectric layer104changes to a “low resistance state” (data “1”) wherein the current easily flows. When a negative voltage VW0with a predetermined magnitude is applied, the ferroelectric layer104changes to a “high resistance state” (data “0”) wherein the current hardly flows.

The ferroelectric layer104in the element isolation structure also has the two stable states, i.e., low resistance state and high resistance state. Each state remains unless the above-described positive or negative voltage with a predetermined magnitude or more is applied. The value of VW1is about +1 V. The value of VW0is about −1 V. The resistance ratio of the high resistance state to the low resistance state is about 10 to 100. When the above-described phenomenon that the resistance of the ferroelectric layer104is switched by the voltage is used, a nonvolatile functional element capable of a nondestructive read operation can be implemented even in the element isolation structure, like the above-described functional elements.

Another element isolation structure according to an embodiment of the present invention will be described next.FIG. 125is a schematic sectional view showing another structure example of the element isolation structure according to the embodiment of the present invention. In the element isolation structure shown inFIG. 125, an insulating layer102is provided on a substrate101made of, e.g., single-crystal silicon, and a plurality of elements each including a common electrode layer113formed on the insulating layer102, a lower electrode103, a ferroelectric layer104having a thickness of about 30 to 200 nm, and an upper electrode136are isolated by an isolation layer135.

The ferroelectric layer104and isolation layer135are made of, e.g., Bi, Ti, and O and contain a plurality of microcrystalline grains of Bi4Ti3O12crystal having a stoichiometric composition and a grain size of about 3 to 15 nm. The ferroelectric layer104also contains column crystal with the stoichiometric composition of Bi4Ti3O12in addition to the microcrystalline grains. The isolation layer135having the above-described structure has a higher electrical resistance than the ferroelectric layer104so that the dielectric isolation for a breakdown voltage is large. On the other hand, the ferroelectric layer104has two stable states, i.e., low resistance state and high resistance state, as will be described later. An element using the ferroelectric layer104is a functional element to hold two states. This is the same as in the structure shown inFIG. 120.

The element isolation structure shown inFIG. 125is different from the element isolation structure shown inFIG. 120in that the lower electrodes103are connected by the common electrode layer113. In the element isolation structure shown inFIG. 125, the common electrode layer113is made of a conductive material in an amorphous state. The common electrode layer113is made of, e.g., titanium nitride, zinc oxide, or ITO (Indium Tin Oxide) in an amorphous state. Hence, even in the element isolation structure shown inFIG. 125, the isolation layer135is formed on an amorphous layer.

An example of a method of manufacturing the element isolation structure shown inFIG. 125will be described next. As shown inFIG. 126A, the p-type silicon substrate101having a plane orientation of (100) on the principal plane and a resistivity of 1 to 2 Ωcm is prepared. The surface of the substrate101is cleaned by a solution mixture of sulfuric acid and a hydrogen peroxide solution, pure water, and a hydrogen fluoride solution and dried. The insulating layer102is formed on the cleaned and dried substrate101. A common electrode layer143made of, e.g., titanium nitride is formed on the insulating layer102. A metal film made of, e.g., Ru and having a thickness of about 10 nm is formed on the common electrode layer143. When the metal film is patterned by known lithography and etching, the plurality of lower electrodes103spaced apart from each other are formed, as shown inFIG. 126A.

After the lower electrode103is formed in the above-described manner, the ferroelectric layer104is formed on the lower electrode103, and the isolation layer135is formed on the common electrode layer143, as shown inFIG. 126B, by ECR sputtering using argon (Ar) as a plasma gas and oxygen gas and a target formed from an oxide sintered body (Bi—Ti—O) in which the ratio of Bi to Ti is 4:3. Formation of the ferroelectric layer104and isolation layer135will be described. The substrate101is heated to 400° C. to 450° C. Ar gas as a rare gas is supplied into the plasma production chamber at a flow rate of, e.g., 20 sccm to set the pressure on the order of, e.g., 10−3to 10−2Pa. In this state, the magnetic field of the electron cyclotron resonance condition is given to the plasma production chamber. Then, a microwave of 2.45 GHz (about 500 W) is supplied into the plasma production chamber to produce ECR plasma in it.

The produced ECR plasma is output from the plasma production chamber to the process chamber side by the divergent magnetic field of the magnetic coil. In addition, a high-frequency power of 13.56 MHz (e.g., 500 W) is supplied to the sintered body target placed at the outlet of the plasma production chamber. When Ar particles collide against the sintered body target, the sputtering phenomenon occurs to sputter Bi particles and Ti particles. The Bi particles and Ti particles sputtered from the sintered body target reach the surfaces of the heated common electrode layer143and lower electrode103together with the ECR plasma output from the plasma production chamber and the oxygen gas activated by the output ECR plasma and are oxidized by the activated oxygen.

The oxygen (O2) gas serving as a reactive gas is supplied at a flow rate of, e.g., 1 scam separately from the Ar gas, as will be described later. Although the sintered body target contains oxygen, any shortage of oxygen in the deposited film can be prevented by supplying oxygen. With the above-described film formation by ECR sputtering, the ferroelectric layer104and isolation layer135each having a thickness of, e.g., about 40 nm can be formed (FIG. 126B). The isolation layer135formed on the common electrode layer143in an amorphous state contains a plurality of microcrystalline grains of Bi4Ti3O12crystal having a stoichiometric composition and a grain size of about 3 to 15 nm. The ferroelectric layer104formed on the lower electrode103in a crystalline state also contains column crystal with the stoichiometric composition of Bi4Ti3O12in addition to the microcrystalline grains.

As shown inFIG. 126C, a metal film146made of, e.g., Au is formed on the ferroelectric layer104and isolation layer135. As shown inFIG. 126D, resist patterns150are formed on portions as prospective elements by well-known lithography. The metal film146is patterned by dry etching using the resist patterns150as a mask to form the upper electrodes136on the ferroelectric layers104, as shown inFIG. 126E. When the resist patterns150are removed then, the element isolation structure shown inFIG. 125is obtained.

The substrate101can be made of any one of a semiconductor, insulator, and conductive material such as a metal. When the substrate101is made of an insulating material, the insulating layer102can be omitted. The lower electrode103and upper electrode136need only be made of a transition metal including noble metals such as gold (Au) and silver (Ag). The above-described electrodes may be made of a compound such as a nitride, oxide, or fluoride of a transition metal, such as titanium nitride (TiN), hafnium nitride (HfN), strontium ruthenate (SrRuO2), zinc oxide (ZnO), indium tin oxide (ITO), or lanthanum fluoride (LaF3) in a crystalline state, or a composite film formed by stacking them. The common electrode layer143may be made of a compound such as a nitride, oxide, or fluoride of a transition metal, such as hafnium nitride (HfN), strontium ruthenate (SrRuO2), or lanthanum fluoride (LaF3) in an amorphous state, or a composite film formed by stacking them.

FIGS. 120 and 125show three element portions. A plurality of elements may be arrayed and integrated two-dimensionally. For example, when island-shaped metal oxide layers are arrayed on a substrate at a predetermined interval and connected by an electrode, the degree of integration can easily be increased.