Data loading circuit and semiconductor memory device comprising same

A data loading circuit comprises a non-volatile memory configured to store non-volatile data and output a serial data signal based on the stored non-volatile data in response to a power-up operation, a deserializer configured to receive the serial data signal and output multiple data bits at intervals of a unit period based on the received serial data signal, a load controller configured to generate multiple loading selection signals that are sequentially activated one-by-one at each interval of the unit period, and a loading memory unit configured to sequentially store the data bits at each interval of the unit period in response to the loading selection signals.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority under 35 USC §119 to Korean Patent Application No. 10-2012-0115140 filed on Oct. 17, 2012, the subject matter of which is hereby incorporated by reference.

BACKGROUND OF THE INVENTION

The inventive concept relates generally to semiconductor devices. Certain embodiments relate to a data loading circuit for a non-volatile memory device and a semiconductor memory device comprising the data loading circuit.

An electronic device may incorporate a non-volatile memory to store data when the device is powered off. In such a device, the data may be moved from the non-volatile memory to a volatile memory during a power-up operation to allow rapid access during operation of the device.

The volatile memory may be a main memory, or it may be some other type of memory. For example, where the data comprises fail addresses for repairing failed memory cells, the volatile memory may be a repair control circuit disposed near a memory cell array.

The repair control circuit typically comprises a shift register in which the fail addresses are loaded. In general, the shift register requires a master latch and a slave latch for storing one data bit and thus the shift register occupies a relatively large area. As the quantity of data to be loaded increases, the required area of the shift register tends to increase accordingly. As a result, the design margin of the electronic device may decrease as well.

SUMMARY OF THE INVENTION

In one embodiment of the inventive concept, a data loading circuit comprises a non-volatile memory configured to store non-volatile data and output a serial data signal based on the stored non-volatile data in response to a power-up operation, a deserializer configured to receive the serial data signal and output multiple data bits at intervals of a unit period based on the received serial data signal, a load controller configured to generate multiple loading selection signals that are sequentially activated one-by-one at each interval of the unit period, and a loading memory unit configured to sequentially store the data bits at each interval of the unit period in response to the loading selection signals.

In another embodiment of the inventive concept, a semiconductor memory device comprises a memory cell array comprising normal memory cells coupled to normal selection lines and redundancy memory cells coupled to redundancy selection lines, a decoder configured to select one of the normal selection lines based on an address of a read operation or a write operation, a non-volatile memory configured to store fail addresses indicating locations of fail memory cells among the normal memory cells, and further configured to output a serial data signal based on the stored fail addresses in response to a power-up operation, a load controller configured to generate multiple loading selection signals that are sequentially activated one-by-one at intervals of a unit period, and a repair control circuit configured to store the fail addresses sequentially based on the serial data signal and the loading selection signals, and further configured to select one of the redundancy selection lines with disabling the decoder when the address is identical to one of the stored fail addresses.

In yet another embodiment of the inventive concept, a method of operating a semiconductor device comprising a non-volatile memory and a data loading circuit comprises detecting a power-up operation of the semiconductor device, in response to the power-up operation, outputting, by the non-volatile memory, a serial data signal based on stored non-volatile data, deserializing the serial data signal and outputting multiple data bits at intervals of a unit period based on the received serial data signal, generating multiple loading selection signals that are sequentially activated one-by-one at each interval of the unit period, and sequentially storing the data bits at each interval of the unit period in a loading memory unit in response to the loading selection signals.

These and other embodiments of the inventive concept can potentially improve the efficiency of operations for loading data from a non-volatile memory to a volatile memory in response to a power-up operation of a semiconductor device.

DETAILED DESCRIPTION

Embodiments of the inventive concept are described below with reference to the accompanying drawings. These embodiments are presented as teaching examples and should not be construed to limit the scope of the inventive concept.

In the description that follows, the terms first, second, third, etc. may be used to describe various features, but these features should not be limited by these terms. Rather, these terms are used to distinguish between different features. Thus, a first feature discussed below could be termed a second feature and vice versa without materially changing the relevant teachings. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

Where a feature is referred to as being “connected” or “coupled” to another feature, it can be directly connected or coupled to the other feature or intervening features may be present. In contrast, where a feature is referred to as being “directly connected” or “directly coupled” to another feature, there are no intervening features present. Other words used to describe the relationship between features should be interpreted in a like fashion (e.g., “between” versus “directly between,” “adjacent” versus “directly adjacent,” etc.).

The terminology used herein is for the purpose of describing example embodiments only and is not intended to limit the inventive concept. The singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. Terms such as “comprises” and/or “comprising,” where used in this description, indicate the presence of stated features but do not preclude the presence or addition of other features.

FIG. 1is a block diagram illustrating a data loading circuit10according to an embodiment of the inventive concept.

Referring toFIG. 1, data loading circuit10comprises a non-volatile memory (NVM)100, a deserializer200, a load controller300, and a loading memory unit400.

Non-volatile memory100stores data in non-volatile fashion (“non-volatile data”) and outputs a serial signal SER based on the stored non-volatile data in response to a power-up operation. The non-volatile memory may be any type of structure capable of retaining stored data when disconnected from power. For example, non-volatile memory100may comprise a fuse array, a flash memory, a phase-change random access memory (PRAM), a ferroelectric random access memory (FRAM), a resistance random access memory (RRAM), a magneto-resistive random access memory (MRAM), etc.

The non-volatile data stored in non-volatile memory100may be provided to deserializer200in the form of data bits in serial signal SER when power is provided to a device and/or a system comprising data loading circuit10. An indication of a power-up operation may be provided, for instance, by a power-up signal PWU that is activated when a power supply voltage reaches a predetermined level.

Load controller300generates a control signal TCON for controlling and synchronizing operations of non-volatile memory100and deserializer200. Control signal TCON comprises a transfer clock signal TCK and/or a mask signal MSK, which are further described with reference toFIGS. 2 through 8. Where power-up signal PWU is activated, load controller300launches a loading process for the non-volatile data using the control signal. Load controller300may be distinct from a processor such as a central processing unit CPU of the device comprising load controller300. Load controller300typically comprises a logic circuit dedicated to controlling the loading process of the non-volatile data in response to the power-up operation. Load controller300may be disabled after the loading process is completed.

Deserializer200receives serial signal SER from non-volatile memory100and provides multiple data bits at intervals of a unit period based on the received serial signal SER. Deserializer200is configured to store M data bits provided through serial signal SER. For example, deserializer200may be implemented with a shift register as illustrated inFIG. 2.

Load controller300generates multiple loading selection signals LDS1through LDSN that are sequentially activated at the intervals of the unit period, and loading selection signals LDS1through LDSN are provided to loading memory unit400. In addition, as described above, load controller300may further generate control signal TCON for controlling and synchronizing operations of non-volatile memory100and deserializer200. As will be described with reference toFIGS. 5,7and8, transfer clock signal TCK may be in control signal TCON.

Loading memory unit400sequentially stores first through M-th data bits Q1through QM, which are provided at intervals of the unit period, in response to loading selection signals LDS1through LDSN.

Loading memory unit400comprises first through N-th loading units LDU1through LDUN. Loading units LDU1through LDUN receive first through N-th loading selection signals LDS1through LDSN, respectively, so that loading units LDU1through LDUN are enabled sequentially one-by-one at the intervals in response to loading selection signals LDS1through LDSN. For example, first loading selection signal LDS1may be activated during a first unit period, and first loading unit LDU1may be enabled to store first through M-th data bits Q1through QM in the first unit period. Second loading selection signal LDS2may be activated during a second unit period and second loading unit LDU2may be enabled to store first through M-th data bits Q1through QM in the second unit period.

As such, loading selection signals LDS1through LDSN may be sequentially activated one-by-one at intervals of the unit period, and the N*M data bits may be sequentially stored in loading units LDU1through LDUN for N times the unit period.

FIG. 2is a diagram illustrating an example of a deserializer and a loading memory unit in the data loading circuit ofFIG. 1.

Referring toFIG. 2, the deserializer comprises a shift register circuit200a. Shift register circuit200acomprises M flip-flops FF1through FFM or M registers that are cascade-coupled, where M is an integer greater than or equal to two, and the M data bits Q1through QM are provided through output nodes of the M flip-flops FF1through FFM. Here, the terms “cascade-coupled” or “cascaded” indicate that an output of a previous flip-flop is coupled to an input of a next flip-flop and thus flip-flops FF1through FFN form a single chain. Each of the M flip-flops FF1through FFM may comprise a master latch ML and a slave latch SL.

Shift register circuit200aperforms a shifting operation to store the M data bits provided in serial signal SER in response to transfer clock signal TCK. For example, the shifting operation of shift register circuit200aand the outputting operation of non-volatile memory100inFIG. 1may be synchronized with each other based on transfer clock signal TCK.

Loading memory unit400acomprises N*M one-bit storage elements S11through SNM for storing the N*M data bits that are provided in serial signal SER for N times the unit period. As described above, one-bit storage elements S11through SNM may be grouped into the N loading units LDU1through LDUN. First loading unit LDU1comprises M one-bit storage elements S11through S1M of the first row, second loading unit LDU2comprises M one-bit storage elements S21through S2M of the second row, and in this way N-th loading unit LDUN comprises M one-bit storage elements SN1through SNM of the N-th row.

The output nodes of flip-flops FF1through FFM in shift register circuit200aare commonly coupled to loading units LDU1through LDUN. Where first loading selection signal LDS1is activated, one-bit storage elements S11through S1M in first loading unit LDU1are enabled to store data bits Q1through QM of the first unit period. Where second loading selection signal LDS2is activated, one-bit storage elements S21through S2M in second loading unit LDU2are enabled to store data bits Q1through QM of the second unit period. In this way, one-bit storage elements SN1through SNM in N-th loading unit LDUN are enabled, where N-th loading selection signal LDSN is activated, to store data bits Q1through QM of the N-th unit period. As such, shift register circuit200areceives and stores the M data bits periodically, and loading memory unit400astores the N*M data bits sequentially in response to the N loading selection signals LDS1through LDSN that are sequentially activated.

FIG. 3is a circuit diagram illustrating an example one-bit storage unit of the deserializer inFIG. 2, andFIG. 4is a circuit diagram illustrating an example one-bit storage unit of the loading memory unit inFIG. 2.

Referring toFIG. 3, a one-bit storage element, i.e., a flip-flop FFj or a register in shift register circuit200ainFIG. 2, comprises a master latch ML and a slave latch SL. Master latch ML comprises two inverters INV1and INV2that are coupled between two nodes N1and N2with inputs and outputs crossed, and slave latch SL comprises two inverters INV3and INV4that are coupled between two nodes N3and N4with inputs and outputs crossed.

Master latch ML latches data bit Qk transferred from a previous flip-flop through a first switch SW1which is turned-on in response to an inverted transfer clock signal TCKb, and slave latch SL latches the data bit output from master latch ML through a second switch SW2which is turned-on in response to a transfer clock signal TCK. In alternative embodiments, first switch SW1may be turned-on in response to transfer clock signal TCK, and second switch SW2may be turned-on in response to the inverted transfer clock signal TCKb.

Using the cascade-coupled M flip-flops as illustrated inFIG. 3, one-bit shifting may be performed per the cyclic period of transfer clock signal TCK, and M-bit shifting may be performed for the M cyclic periods. The cyclic period of transfer clock signal TCK may correspond to the above-mentioned unit period and thus shift register circuit200amay store the M data bits Q1through QM that are provided in serial signal SER for N times the unit period.

Referring toFIG. 4, a one-bit storage element Sij in loading memory unit400of shift register circuit200ainFIG. 2comprises a latch. The latch comprises two inverters INV5and INV6that are coupled between two nodes N5and N6with inputs and outputs crossed. The latch latches data bit Qj transferred through a switch SW, which is turned-on in response to corresponding loading selection signal LDSi. Data bit Qj is transferred from the output node of the corresponding flip-flop FFj in shift register circuit200a.

As illustrated inFIGS. 3 and 4, one-bit storage element FFj in shift register circuit200aoccupies about twice as much area as one-bit storage element Sij in loading memory unit400a.FIG. 4illustrates a non-limiting example of the one-bit storage element Sij having the smaller area. One-bit storage element Sij in loading memory unit400acan be implemented with various storage structures other than the latch.

In a less effective approach, all of the data bits of the non-volatile data are loaded in the shift register circuit. Where the N*M data bits are loaded, the N*M flip-flops, each comprising the master and slave latches, have to be in the shift register circuit. The master latches are required to prevent errors of the shifting operation and the slave latches function as the substantial storage to store the data bits. Where all of the data bits are loaded in the shift register circuit after the last one-bit shifting is performed, the master latches need not operate and occupy areas unnecessarily. Thus the master devices act as a size penalty in a device performing the loading process according to the less effective approach, a significant penalty for a high-density device, especially one having insufficient design margin.

Compared to the less effective approach, data loading circuit10reduces the number of storage elements in shift register circuit200ahaving a relatively large area, and it stores the data bits in loading memory unit400ahaving a relatively smaller area. As described above, to load the N*M data bits, data loading circuit10stores the N*M data bits by performing, N times repeatedly, the shifting operation for temporarily storing the M data bits using the M flip-flops, and the loading operation for storing the M data bits in the loading memory.

As a result, the data loading circuit may be implemented with a reduced area, and such down-sizing effect may be increased as the number of data bits of the non-volatile data to be loaded is increased.

FIG. 5is a timing diagram illustrating operations of a data loading circuit according to an embodiment of the inventive concept.

Referring toFIG. 5, the above-mentioned unit period may comprise a shifting period TSi and a loading period TLi (i=1, 2, . . . , or N). Transfer clock signal TCK is activated during shifting period TSi and deactivated during loading period TLi. Loading selection signals LDS1through LDSN are activated sequentially one-by-one during loading periods TL1through TLN.

Referring toFIGS. 2 and 5, shift register circuit200aperforms the shifting operation to store the M data bits TDi in synchronization with transfer clock signal TCK during shifting period TSi. Loading memory unit400areceives and stores the M data bits TDi from shift register circuit200aduring loading period TLi.

First data TD1of M bits is temporarily stored in shift register circuit200ain response to transfer clock signal TCK during first shifting period TS1, and first loading selection signal LDS1is activated to store first data TD1in first loading unit LDU1during the first loading period TL1. Second data TD2of M bits is temporarily stored in shift register circuit200ain response to transfer clock signal TCK during the second shifting period TS2, and second loading selection signal LDS2is activated to store second data TD2in second loading unit LDU2during second loading period TL2. In this way, N-th data TDN of M bits is temporarily stored in shift register circuit200ain response to transfer clock signal TCK during N-th shifting period TSN, and N-th loading selection signal LDSN is activated to store the N-th data TDN in N-th loading unit LDUN during N-th loading period TLN.

As a result, the N*M data bits in first through N-th data TD1through TDN are stored in loading memory unit400aby repeating N times the shifting operation and the loading operation with respect to the M data bits.

FIG. 6is a diagram illustrating an example of non-volatile memory100in the data loading circuit ofFIG. 1.

Non-volatile cell array110comprises multiple memory cells of various types. For example, the memory cell may comprise a fuse cell, a flash memory cell, a PRAM cell, an FRAM cell, an RRAM cell, an MRAM cell, etc. In some embodiments, non-volatile cell array110may be a fuse array comprising multiple fuse cells having relatively simple programming or writing means. The fuse cell may be an electric fuse cell that is programmed by cutting a conduction path of a metal-oxide semiconductor (MOS) transistor, or an anti-fuse cell that is programmed by forming a conduction path in a MOS capacitor with a breakdown therein.

Serializer130serializes non-volatile data from non-volatile cell array110to produce serial signal SER. Serializer130performs an output operation of serial signal SER in synchronization with transfer clock signal TCK. Transfer clock signal TCK is provided in common to serializer130and the above-described shift register circuit200a. The shifting operation of shift register circuit200aand the output operation of non-volatile memory100are synchronized based on transfer clock signal TCK.

FIGS. 7 and 8are diagrams for describing an example of generating a transfer clock signal used in a data loading circuit according to an embodiment of the inventive concept.

Referring toFIGS. 7 and 8, transfer clock signal TCK is generated using a logic gate GT to perform a logical operation on a clock signal CLK and a mask signal MSK. For example, logic gate GT may be an AND gate performing an AND logic operation. In this case, transfer clock signal TCK is activated while the mask signal is in a logic “high” level and deactivated while the mask signal is in a logic “low” level. In other words, transfer clock signal TCK may be activated during the above-described shifting period TSi and deactivated during the above-described loading period TLi. Each of shifting period TSi and loading period TLi may be determined by the cycle number of transfer clock signal TCK. For example, where shift register circuit200acomprises the M flip-flops and one-bit shifting is performed per cycle of transfer clock signal TCK, shifting period TSi may correspond to the M cyclic periods of transfer clock signal TCK. Loading period TLi may be determined properly considering the data transfer from shift register circuit200ato loading memory unit400a.

In some embodiments, load controller300inFIG. 1comprises logic gate GT as illustrated inFIG. 7to generate transfer clock signal TCK, and transfer clock signal TCK may be provided in common to serializer130in non-volatile memory100and the deserializer such as a shift register circuit200a. In this case, the shifting operation of shift register circuit200aand the output operation of non-volatile memory100may be performed in synchronization based on transfer clock signal TCK from load controller300.

In some other embodiments, each of non-volatile memory100and shift register circuit200amay comprise logic gate GT as illustrated inFIG. 7. Load controller300inFIG. 1may provide, as one of control signal TCON, mask signal MSK commonly to non-volatile memory100and shift register circuit200a, each of non-volatile memory100and shift register circuit200amay generate the respective transfer control signal TCK. In this case, the shifting operation of shift register circuit200aand the output operation of non-volatile memory100may be synchronized based on mask signal MSK from load controller300.

FIG. 9is a block diagram illustrating a semiconductor memory device50according to an embodiment of the inventive concept.

Referring toFIG. 9, semiconductor memory device50comprises a memory cell array520and540, a decoder (DEC)600, non-volatile memory100, load controller300and a repair control circuit (RECON)700. InFIG. 9, components unrelated with descriptions of the loading process of the non-volatile data are omitted.

Memory cell array520and540comprises is divided into normal memory cell array520and redundancy memory cell array540. Normal cell array520comprises multiple normal memory cells NCs coupled to normal selection lines NS1through NSP, and redundancy memory cell array540comprises multiple redundancy memory cells RCs coupled to redundancy selection lines RS1through RSK.

Decoder600selects one of normal selection lines NS1through NSP based on an address ADD for a read operation or a write operation. By selecting the normal selection line, the read operation or the write operation may be performed with respect to the normal memory cells coupled to the selected one of normal selection lines NS1through NSP.

Non-volatile memory100stores fail addresses indicating locations of fail memory cells among the normal memory cells NCs, and outputs a serial signal SER based on the stored fail addresses when semiconductor memory device50is powered-up. The fail addresses may be obtained and stored in non-volatile memory100through test processes of semiconductor memory device50. Load controller300generates multiple loading selection signals LDS that are sequentially activated one-by-one at an interval of a unit period. The configurations and operations of non-volatile memory100and load controller300may be the same as described with reference toFIGS. 1 through 8, and the repeated description may be omitted.

Repair control circuit700stores or loads the fail addresses sequentially based on serial signal SER and loading selection signals LDS. Repair control circuit700controls a repair operation for replacing an access to the normal memory cells NCs with an access to the redundancy memory cells RCs when input address ADD is identical to one of the stored fail addresses. Repair control circuit700selects one of redundancy selection lines RS1through RSK with disabling decoder600by activating a disable signal NDIS, when input address ADD is identical to one of the stored fail addresses.

In some embodiments, normal selection lines NS1through NSP and redundancy selection lines RS1through RSK are wordlines. In such embodiments, repair control circuit700may perform the repair operation wordline by wordline. Where each wordline stores multiple pages, repair control circuit700may perform the repair operation page by page. In some other embodiments, normal selection lines NS1through NSP and redundancy selection lines RS1through RSK are bitlines. In such embodiments, repair control circuit700performs repair operations bitline by bitline.

FIG. 10is a block diagram illustrating an example of repair control circuit700in semiconductor memory device50ofFIG. 9.

Referring toFIG. 10, repair control circuit700comprises deserializer200, loading memory unit400, and a comparator (COM)710.

Deserializer200receives serial signal SER and provides multiple data bits at the intervals of the unit period based on the received serial signal SER. As described above, the deserializer may comprise M flip-flops that are cascade-coupled as illustrated inFIG. 2, and the M flip-flops form the shift register circuit SRC to provide the M data bits through output nodes of the M flip-flops.

Loading memory unit400may sequentially store the data bits at the interval of the unit period in response to loading selection signals LDS1through LDS40.FIG. 10illustrates four fail addresses FADD1through FADD4loaded based on the four loading selection signals LDS1through LDS4for convenience of illustration and description, but the number of the loading selection signals may be changed according to the total data bits to be loaded.

As described above, loading memory unit400may have a storage capacity for the M*N data bits that are provided from deserializer200for N times the unit period. Depending on the number of the flip-flops in the shift register circuit SRC, only a portion of the data bits corresponding to the one fail address be loaded in loading memory unit400whenever the one loading selection signal is activated, or the data bits corresponding to the two or more fail addresses may be loaded simultaneously in loading memory unit400whenever the one loading selection signal is activated.

Comparator710compares input address ADD with the stored fail addresses FADD1through FADD4. Based on the comparison, comparator710generates disable signal NDIS for disabling decoder600inFIG. 9and redundancy enable signal REN for selecting one of redundancy selection lines RS1through RSK.

FIG. 11is a block diagram illustrating a semiconductor memory device60according to another embodiment of the inventive concept. Semiconductor memory device60has certain features in common with semiconductor memory device50ofFIG. 9, and a repeated description of those features will be omitted to avoid redundancy.

Comparing semiconductor memory device60ofFIG. 11with semiconductor memory device50ofFIG. 9, normal memory cell array520ofFIG. 9is divided into multiple normal blocks521and522. AlthoughFIG. 11illustrates a first normal block (NBL1)521and a second normal block (NBL2)522for convenience of illustration, normal cell array520may be divided into three or more normal blocks.

According to the division of normal memory cell array520in first normal block521and second normal block522, redundancy memory cell array540is divided into a first redundancy block (RBL1)541and a second redundancy block (RBL2)542, decoder600is divided into a first sub decoder (SDEC1)601and a second sub decoder (SDEC2)602, repair control circuit700is divided into a first sub repair control circuit (RECON1)701and a second sub repair control circuit (RECON2)702. AlthoughFIG. 11illustrates a layout in which the redundancy block is disposed at a bottom portion of the corresponding normal block, the redundancy block may be disposed in various alternative locations. For example, the redundancy block may be disposed at an upper portion of the corresponding normal block, or it may be distributed between the bottom and upper portions of the corresponding normal block.

As such, repair control circuit700inFIG. 9may be divided into sub repair control circuits701and702that are disposed spatially apart from each other as illustrated inFIG. 11, and the M flip-flops and the loading memory unit may be distributed in sub repair control circuits701and702.

The transfer path of the data bits in serial signal SER is represented by a dashed line inFIG. 11. As described with reference toFIG. 12, the flip-flops in first sub repair control circuit701and the flip-flops in second sub repair control circuit702may be cascade-coupled in their entirety to form a single shift register circuit.

FIG. 12is a block diagram illustrating an example of a repair control circuit in semiconductor memory device60ofFIG. 11.

Referring toFIG. 12, first sub repair control circuit701comprises a first shift register circuit (SRC1)201, a first loading memory (401) and a first comparator (COM1)711, and second sub repair control circuit702comprises a second shift register circuit (SRC2)202, a second loading memory (402) and a second comparator (COM2)712.

As illustrated inFIG. 12, the output of first shift register circuit201is coupled to the input of second shift register circuit202. In this case, first shift register circuit201and second shift register circuit202form a single coupled shift register circuit201and202for performing a shifting operation in their entirety.

Coupled shift register circuit201and202provide multiple data bits at the interval of the unit period based on the received serial signal SER. As described above, coupled shift register circuit201and202may comprise the M flip-flops and the M data bits may be provided through the output nodes of the M flip-flops at the interval of the unit period.

Loading memories401and402distributed in the first and second sub repair control circuits701and702may sequentially store the M data bits at the interval of the unit period in response to loading selection signals LDS1through LDSN. AlthoughFIG. 12illustrates eight fail addresses FADD1through FADD8loaded based on four loading selection signals LDS1through LDS4for convenience of illustration and description, the number of the loading selection signals may be changed according to the total data bits to be loaded. As described above, loading memories401and402may have a storage capacity for the M*N data bits that are provided from coupled shift register circuit201and202for N times the unit period.

First comparator711compares input address ADD with fail addresses FADD2, FADD4, FADD6and FADD8stored in first loading memory unit401. Based on the comparison, first comparator711generates the first disable signal NDIS1for disabling first sub decoder601inFIG. 11and the first redundancy enable signal REN1for selecting one of the redundancy selection lines RSs coupled to first redundancy block541inFIG. 11. Second comparator712compares input address ADD with fail addresses FADD1, FADD3, FADD5and FADD7stored in second loading memory unit402. Based on the comparison, second comparator712generates the second disable signal NDIS2for disabling second sub decoder602inFIG. 11and the second redundancy enable signal REN2for selecting one of the redundancy selection lines RSs coupled to second redundancy block542inFIG. 11.

FIG. 13is a timing diagram illustrating an operation of the repair control circuit ofFIG. 12.

Referring toFIG. 13, a unit period comprises a shifting period TSi and a loading period TLi (i=1, 2, 3 or 4). Transfer clock signal TCK is activated during shifting period TSi and deactivated during loading period TLi. Loading selection signals LDS1through LDS4are activated sequentially one-by-one during loading periods TL1through TL4.

Referring toFIGS. 11,12and13, coupled shift register circuit201and202performs the shifting operation to store the M data bits TDi in synchronization with transfer clock signal TCK during shifting period TSi and loading memories401and402receive and store the M data bits TDi from coupled shift register circuit201and202during loading period TLi.

First fail address FADD1and second fail address FADD2of the M data bits in total are stored respectively in the first and second shift register circuits201and202in response to transfer clock signal TCK during first shifting period TS1, and then first loading selection signal LDS1is activated to store the first fail address FADD1and the second fail address FADD2in first and second loading memories401and402during first loading period TL1.

Third fail address FADD3and fourth fail address FADD4of the M data bits in total are stored respectively in first and second shift register circuits201and202in response to transfer clock signal TCK during second shifting period TS2, and then second loading selection signal LDS2is activated to store third fail address FADD3and fourth fail address FADD4in first and second loading memories401and402during second loading period TL2.

Fifth fail address FADD5and sixth fail address FADD6of the M data bits in total are stored respectively in first and second shift register circuits201and202in response to transfer clock signal TCK during third shifting period TS3, and then third loading selection signal LDS3is activated to store fifth fail address FADD5and sixth fail address FADD6in first and second loading memories401and402during third loading period TL3.

Seventh fail address FADD7and eighth fail address FADD8of the M data bits in total are stored respectively in first and second shift register circuits201and202in response to transfer clock signal TCK during fourth shifting period TS4, and then fourth loading selection signal LDS4is activated to store seventh fail address FADD7and eighth fail address FADD8in first and second loading memories401and402during fourth loading period TL4.

As such, the N*M data bits in the fail addresses are stored in loading memories401and402by repeating N times the shifting operation and the loading operation with respect to the M data bits.

FIG. 14is a block diagram illustrating a computing system2000comprising a semiconductor memory device according to an embodiment of the inventive concept.

Referring toFIG. 14, computing system2000comprises a processor1010, a memory device1020, a storage device1030, a display device1040, a power supply1050and an image sensor1060. Although not illustrated inFIG. 14, computing system2000may further comprise ports that communicate with a video card, a sound card, a memory card, a USB device, other electronic devices, etc.

Processor1010performs various calculations or tasks. According to some embodiments, processor1010may be a microprocessor or a CPU. Processor1010may communicate with memory device1020, storage device1030, and display device1040via an address bus, a control bus, and/or a data bus. In some embodiments, processor1010may be coupled to an extended bus, such as a peripheral component interconnection (PCI) bus. Memory device1020stores data for operating computing system2000. Memory device1020may comprise, for instance, a dynamic random access memory (DRAM) device, a mobile DRAM device, a static random access memory (SRAM) device, a PRAM device, an FRAM device, an RRAM device, and/or an MRAM device. Memory device1020comprises the data loading circuit according to example embodiments as described with reference toFIGS. 1 through 13.

Storage device1030may comprise a solid state drive (SSD), a hard disk drive (HDD), a CD-ROM, etc. Computing system2000may further comprise an input device such as a touchscreen, a keyboard, a keypad, a mouse, etc., and an output device such as a printer, a display device, etc. power supply1050supplies operation voltages for computing system2000.

Image sensor1060may communicate with processor1010via the buses or other communication links. Image sensor1060can be integrated with processor1010in one chip, or image sensor1060and processor1010may be implemented as separate chips.

At least a portion of computing system2000may be packaged in various forms, such as package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carrier (PLCC), plastic dual in-line package (PDIP), die in waffle pack, die in wafer form, chip on board (COB), ceramic dual in-line package (CERDIP), plastic metric quad flat pack (MQFP), thin quad flat pack (TQFP), small outline IC (SOIC), shrink small outline package (SSOP), thin small outline package (TSOP), system in package (SIP), multi chip package (MCP), wafer-level fabricated package (WFP), or wafer-level processed stack package (WSP). Computing system2000may be a computing system using a data loading circuit, e.g., a digital camera, a mobile phone, a smart phone, a portable multimedia player (PMP), a personal digital assistant (PDA), a computer, etc.

FIG. 15is a block diagram illustrating an interface for computing system1100ofFIG. 14.

Referring toFIG. 15, computing system1100may comprise a data processing device that uses or supports a mobile industry processor interface (MIPI) interface. Computing system1100may comprise an application processor1110, an image sensor1140, a display device1150, etc. display device1150may comprise the source driver according to certain embodiments as described with reference toFIGS. 10 and 11. A CSI host1112of application processor1110may perform a serial communication with a CSI device1141of image sensor1140via a camera serial interface (CSI). In some embodiments, CSI host1112may comprise a deserializer (DES), and CSI device1141may comprise a serializer (SER). A DSI host1111of application processor1110may perform a serial communication with a DSI device1151of display device1150via a display serial interface (DSI).

In some embodiments, DSI host1111comprises a serializer, and DSI device1151comprises a deserializer. Computing system1100may further comprise a radio frequency (RF) chip1160performing communication with application processor1110. A physical layer (PHY)1113of computing system1100and a physical layer (PHY)1161of RF chip1160may perform data communications based on a MIPI DigRF. Application processor1110may further comprise a DigRF MASTER1114that controls the data communications of PHY1161.

Computing system1100may further comprise a global positioning system (GPS)1120, a storage1170, a MIC1180, a DRAM device1185, and a speaker1190. In addition, computing system1100may perform communications using an ultra wideband (UWB)1120, a wireless local area network (WLAN)1220, a worldwide interoperability for microwave access (WIMAX)1130, etc. Other structures and interfaces of electric device1000may also be used.

The data loading circuit according to example embodiments of the inventive concept may be applied in various devices and systems requiring the loading process of the non-volatile data. Particularly the data loading circuit may be applied usefully in a high-density memory device and a system comprising the high-density memory device requiring the loading process of a large amount of the non-volatile data.

The foregoing is illustrative of embodiments and is not to be construed as limiting thereof. Although a few embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the embodiments without materially departing from the scope of the inventive concept. Accordingly, all such modifications are intended to be included within the scope of the inventive concept as defined in the claims.