Wrap around gate field effect transistor (WAGFET)

A field effect transistor (FET) including a substrate, a plurality of semiconductor epitaxial layers deposited on the substrate, and a heavily doped gate layer deposited on the semiconductor layers. The FET also includes a plurality of castellation structures formed on the heavily doped gate layer and being spaced apart from each other, where each castellation structure includes at least one channel layer. A gate metal is deposited on the castellation structures and between the castellation structures to be in direct electrical contact with the heavily doped gate layer. A voltage potential applied to the gate metal structure modulates the at least one channel layer in each castellation structure from an upper, lower and side direction.

BACKGROUND

Field

This invention relates generally to a wrap around gate field effect transistor (WAGFET) and, more particularly, to a WAGFET that includes a plurality of three-dimensional castellation structures each having one or more channels layers deposited on a heavily doped layer, where gate metal is deposited on the castellation structures and between the castellation structures to be in direct electrical contact with the heavily doped gate layer so as to modulate the channel layer from all directions.

Discussion

Field-effect transistors (FET) are well known in the transistor art, and come in a variety of well known types, such a HEMT, MOSFET, MISFET, FinFET, etc., and can be integrated as horizontal devices or vertical devices. A typical FET will include various semiconductor layers, such as silicon, gallium arsenide (GaAs), indium gallium arsenide (InGaAs), gallium nitride (GaN), indium phosphide (InP), etc. Sometimes the semiconductor layers are doped with various impurities, such as boron, to increase the population of carriers in the layer, where the higher the doping level of the layer the greater the conductivity of the particular semiconductor material. An FET will also include a source terminal, a drain terminal and a gate terminal, where one or more of the semiconductor layers is designated a channel layer and is in a electrical contact with the source and drain terminals. An electrical potential provided to the source terminal allows electrical carriers, either N-type or P-type, to flow through the channel layer to the drain terminal. An electric signal applied to the gate terminal creates an electrical field that modulates the carriers in the channel layer, where a small change in the gate voltage can cause a large variation in the population of carriers in the channel layer to change the current flow from the source terminal to the drain terminal.

It is known in the art to provide an FET that includes spaced apart castellation structures including one or more channel layers all deposited on a common base structure. In these types of castellated FETs, a common gate metal is deposited on the base structure so that it encloses all of the castellation structures, particularly tops of the castellation structures and sides of the castellation structures. In this type of configuration, the electric field generated by the gate terminal to modulate the channel layer or layers is applied to not only the top of the channel layer, but also to the sides of the channel layer, which improves the amplification of the current flow.

DETAILED DESCRIPTION OF THE EMBODIMENTS

The following discussion of the embodiments of the invention is directed to a WAGFET including a plurality of castellation structures and a heavily doped gate layer, where gate metal is deposited on the castellation structures and between the castellation structures to be in direct electrical contact with the heavily doped gate layer so as to modulate the channel layer from all directions, where the discussion is merely exemplary in nature, and is in no way intended to limit the invention or its applications or uses.

FIG. 1is an isometric view of a WAGFET10that provides modulation of one or more channel layers as will be described in detail below. The WAGFET10includes a substrate12that is made of any suitable material, for example, SiC, Sapphire, GaN, AlN, Si, GaAs, etc. In this non-limiting example, the substrate12is a GaAs substrate. A number of semiconductor layers are then grown on the substrate12as epitaxial layers to a desired layer thickness for the particular FET design. For example, in this non-limiting embodiment, a buffer layer14is grown on the substrate12and an InGaAs barrier layer16is grown on the buffer layer14. A heavily doped gate layer18is grown on the barrier layer16, and is a pseudo-conductive layer that provides a modulation signal to a channel layer, as will be described in detail below. The gate layer18can be any suitable semiconductor material, such as GaAs in this non-limiting example, having any suitable thickness, and being doped with any suitable impurity or dopant that provides a high number of N-type or P-type carriers. Suitable and well known patterning and metal deposition steps are employed to deposit a source terminal24, a drain terminal26and a gate terminal28on the gate layer18, where the gate terminal28includes a top portion30and side portions32for reasons that will become apparent from the discussion below. The gate terminal28is not in electrical contact with the source terminal24and the drain terminal26. Furthermore, regions of the gate layer18and the barrier layer16beneath the source terminal24and the drain terminal26are removed so that the source and drain terminals24and26are deposited on the undoped buffer layer14and isolated from the gate layer18.

FIG. 2is an isometric view of the WAGFET10with the gate terminal28removed showing a plurality of gate castellation structures36.FIG. 3is a cut-away cross-sectional view of the WAGFET10through line3-3ofFIG. 1. In this embodiment, the WAGFET10includes two of the castellation structures36. However, as would be well understood by those skilled in the art, such a castellated FET of the type described herein would include many of the castellation structures36forming a castellated gate. Each castellation structure36includes two channel layers, namely, an upper channel layer38and a lower channel layer40, separated by a semiconductor spacer layer42, where the channel layers38and40may be quantum well structures, for example, alternating layers of GaAs and AlAs. Although the castellation structures36include the two channel layers38and40, this is by way of a non-limiting example in that the castellated structures36may only employ a single channel layer, or more than two channel layers. Further, a second semiconductor spacer layer44is provided between the lower channel layer40and the gate layer18. A semiconductor cap layer46is grown on the upper channel layer38and insulates the upper channel layer38from the gate terminal28. The spacer layers42and44and the cap layer46can be made of any suitable semiconductor material and have any suitable thickness for the purposes described herein. The side portion32of the gate terminal28encloses sides of the castellation structures36and is not in electrical contact with the channel layers38and40.

As is apparent, in this configuration, the gate terminal28is formed on top of each of the castellation structures36and around the sides of each of the castellation structures36so that a voltage potential from the gate terminal28is provided to sides and the top of the channel layers38and40. Further, the gate terminal28is in electrical contact with the gate layer18so that the gate layer18is at the same potential as the terminal28, which causes a current flow therethrough that generates an electric field applied to a bottom of the channel layers38and40. The field effect from the upper, lateral and lower surfaces of the castellation structures36provides a more uniform channel flow in each of the channel layers36and40in each of the castellation structures36. In other words, applying a modulation signal to all sides of the channel layers38and40, provides a more uniform modulation of the electric field, which allows the WAGFET10to operate with higher linearity to amplify signals with different strengths. The modulating signals from the gate terminal28and the heavily doped gate layer18operate to populate the channel layers38and40in a uniform manner so that the performance of the channel layers38and40is improved. In this manner, the gate layer18can be grown on the base layers in the same manner as the castellation structures36, where the gate terminal28is then deposited on top of the castellation structures36, and where the gate layer18will ultimately act as a suitable conductor.