Semiconductor structure patterning

Methods, apparatuses, and systems related to removing a hard mask are described. An example method includes patterning a silicon hard mask on a semiconductor structure having a first silicate material on a working surface. The method further includes forming a first nitride material on the first silicate material. The method further includes forming a second silicate material on the first nitride material. The method further includes forming a second nitride material on the second silicate material. The method further includes an opening through the semiconductor structure using the patterned hard mask to form a pillar support. The method further includes forming a silicon liner material on the semiconductor structure. The method further includes removing the silicon liner material using a wet etch process.

TECHNICAL FIELD

The present disclosure relates generally to semiconductor devices and methods, and more particularly to pattern a semiconductor structure.

BACKGROUND

Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory, including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), static random access memory (SRAM), synchronous dynamic random access memory (SDRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), resistive random access memory (ReRAM), and flash memory, among others. Some types of memory devices may be non-volatile memory (e.g., ReRAM) and may be used for a wide range of electronic applications in need of high memory densities, high reliability, and low power consumption. Volatile memory cells (e.g., DRAM cells) require power to retain their stored data state (e.g., via a refresh process), as opposed to non-volatile memory cells (e.g., flash memory cells), which retain their stored state in the absence of power. However, various volatile memory cells, such as DRAM cells may be operated (e.g., programmed, read, erased, etc.) faster than various non-volatile memory cells, such as flash memory cells.

DETAILED DESCRIPTION

Various types of semiconductor structures on memory devices (e.g., those that include volatile or non-volatile memory cells) may include rectilinear trenches and/or round, square, oblong, etc., cavities that may be formed into semiconductor material to create openings thereon for subsequent semiconductor processing steps. Various materials may be deposited using chemical vapor deposition (CVD), plasma deposition, etc. and patterned using photolithographic techniques, doped and etched using vapor, wet and/or dry etch processes to form semiconductor structures on a working surface. Such openings may contain, or be associated with, various materials that contribute to data access, storage, and/or processing, or to various support structures, on the memory device. As an example, capacitor material may be deposited into these openings to provide the data access, storage, and/or processing.

In order to increase the capacitance of a cell of the memory device, a surface area of a semiconductor working surface formed into a column can be increased by increasing the height of the capacitor material column within the openings. However, as capacitor columns increase in height with pillars having higher aspect ratios, it may increase the thickness of the hard mask material. Subsequent dry etches to straighten the capacitor column and etch away the silicon hard mask material and a silicon liner material within the semiconductor structure may result in a loss of semiconductor support structure pillar materials particularly the nitride lattice.

In order to mitigate this issue, a method for patterning a semiconductor structure is described further below. As an example, a wet etch may be used to remove the silicon. A portion of the hard mask may be left remaining after an initial dry etch. A wet etch may subsequently be performed to remove the hard mask material and a liner material within the semiconductor support structure pillar. During the wet etch, the remaining hard mask material may serve as protection for the semiconductor support structure pillar. Using a wet etch may protect the liner material recess within the semiconductor support structure pillar. Positioning the hard mask material above the semiconductor support structure pillar (e.g. the nitride lattice) during the wet etch may protect the loss of the nitride lattice material.

The present disclosure includes methods, apparatuses, and systems related to patterning a semiconductor structure, resulting in reduced liner loss and reduced semiconductor support structure pillar loss. For example, in a previous approach, a dry etch may remove a portion of the semiconductor support structure pillar. As such, some additional material may be added as a buffer to account for potential semiconductor support structure pillar loss in the etch process.

In one example, accurate nitride material may be formed within the semiconductor support structure pillar without accounting for or providing for potential loss. An example of a method described herein includes patterning a silicon hard mask on a semiconductor structure having a first silicate material on a working surface. The method further includes forming a first nitride material on the first silicate material. The method further includes forming a second silicate material on the first nitride material. The method further includes forming a second nitride material on the second silicate material. The method further includes forming a sacrificial material on the second nitride material. The method further includes an opening through the semiconductor structure using the patterned hard mask to form a semiconductor support structure pillar. The method further includes forming a silicon liner material on the semiconductor structure. The method further includes removing the silicon liner material.

In the following detailed description of the present disclosure, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration how one or more examples of the disclosure may be practiced. These examples are described in sufficient detail to enable those of ordinary skill in the art to practice the examples of this disclosure, and it is to be understood that other examples may be utilized and that process, electrical, and/or structural changes may be made without departing from the scope of the present disclosure. As used herein, “a number of” something can refer to one or more such things. For example, a number of capacitors can refer to at least one capacitor.

The figures herein follow a numbering convention in which the first digit or digits correspond to the figure number of the drawing and the remaining digits identify an element or component in the drawing. Similar elements or components between different figures may be identified by the use of similar digits. For example, reference numeral108may reference element “08” inFIG. 1, and a similar element may be referenced as208inFIG. 2. In some instances, a plurality of similar, but functionally and/or structurally distinguishable, elements or components in the same figure or in different figures may be referenced sequentially with the same element number (e.g.,124-1,124-2,124-3,124-4inFIG. 1).

FIG. 1illustrates a cross-sectional view190of a portion of a semiconductor structure of a memory device in association with a semiconductor fabrication sequence for patterning a semiconductor structure in accordance with a number of examples of the present disclosure. The example semiconductor support structure can include a plurality of pillars109-1,109-2, . . . ,109-N (hereinafter referred to collectively as plurality of pillars109). Each of the plurality of pillars109may include a first silicate material103, shown to have been formed over an underlying working surface101. The working surface101may be formed from various undoped or doped materials on which memory device materials may be fabricated. Examples of a relatively inert undoped working surface101may include monocrystalline silicon (monosilicon), polycrystalline silicon (polysilicon), and amorphous silicon, among other possibilities.

The first silicate material103may, in a number of examples, have been formed from borophosphosilicate glass (BPSG). The BPSG may include a silicon compound doped with various concentrations and/or ratios of a boron compound and a phosphorus compound. The silicon compound may be silicon dioxide (SiO2), which may be formed by oxidation of silane (SiH4), among other possibilities. The boron compound may be diboron trioxide (B2O3), which may be formed by oxidation of diborane (B2H6), among other possibilities. The phosphorus compound may be diphosphorus pentoxide (P2O5), which may be formed by oxidation of phosphine (PH3), among other possibilities. The silicon, boron, and phosphorus compounds of the BPSG may include various isotopes of silicon, boron, and phosphorus, as determined to be appropriate for functionality, and/or formation of the first silicate material103, as described herein.

The first silicate material103may be originally formed (e.g., deposited) over a surface of the underlying working surface101. For example, the first silicate material103may be formed without an opening formed therein from an upper surface of the first silicate material103to the surface of the underlying working surface101. The first silicate material103may, in a number of examples, be deposited to a thickness in a range of approximately 200 nanometers (nm) to approximately 600 nm above the surface of the underlying working surface101. However, embodiments of the present disclosure are not limited to this example.

A first nitride material105may be formed over a surface of the first silicate material103opposite from the underlying working surface101. The first nitride material105may be formed (e.g., deposited) over an upper surface of the first silicate material103. The first nitride material105may be formed from a nitride material selected for dielectric properties. For example, one or more dielectric nitrides may be selected from silicon nitride (SiNX, Si3N4), aluminum nitride (AlN), gallium nitride (GN), tantalum nitride (TaN, Ta2N), titanium nitride (TiN, Ti2N), titanium silicon nitride (TiSiN), and tungsten nitride (WN, W2N, WN2), among other possibilities, for formation of the first nitride material105. The first nitride material105may, in a number of examples, be deposited to a thickness in a range of approximately 5 nm to approximately 60 nm above the surface of the first silicate material103. However, embodiments of the present disclosure are not limited to this example.

A second silicate material106is shown to have been formed over a surface of the first nitride material105opposite from the first silicate material103. The second silicate material106may, in a number of examples, be formed from tetraethyl orthosilicate (Si(OC2H5)4), which is also referred to as TEOS. TEOS may be formed as an ethyl ester of orthosilicic acid (Si(OH)4), among other possibilities. The second silicate material106may, in a number of examples, be deposited to a thickness in a range of approximately 250 nm to 450 nm above the surface of the first nitride material105. However, embodiments of the present disclosure are not limited to this example.

A second nitride material108is shown to have been formed over a surface of the second silicate material106opposite from the first nitride material105. The second nitride material108may be formed (e.g., deposited) over an upper surface of the second silicate material106.

Similar to the first nitride material105, the second nitride material108may be formed from a nitride material selected for dielectric properties. For example, the second nitride material108may be formed from the same material as the first nitride material105. The second nitride material108may, in a number of examples, be deposited to a thickness in a range of from approximately 20 nm to approximately 100 nm above the surface of the second silicate material106.

A hard mask material110is shown to have been formed over a surface of the second nitride material108opposite from the second silicate material106. The hard mask material110may, in a number of examples, be formed from a silicon material and may be referred to as a silicon hard mask material110. The hard mask material110may, in a number of examples, be formed from a polycrystalline silicon (polysilicon), among other possibilities. The hard mask material110may, in a number of examples, be deposited to a thickness in a range of approximately 50 nm to 400 nm above the surface of the second nitride material108. However, embodiments of the present disclosure are not limited to this example. The hard mask material110may be patterned and etched, e.g., using a reactive ion etch (RIE) process to form the plurality of pillars109.

An electrode material114, e.g., a bottom electrode, may be formed (e.g., deposited) on the sidewalls of the plurality of pillars109and on the surface of the working surface101. The electrode material114may be formed (e.g., deposited) from the working surface101to a height122of the openings132at the upper surface of the plurality of pillars109through a conformal deposition process such as chemical vapor deposition (CVD). The electrode material114may be formed (e.g., deposited) on upper surfaces of the plurality of pillars109. For example, the inner and upper surfaces of the plurality of pillars109may be covered by the electrode material114.

The electrode material114may be formed from a nitride compound material selected for conductive properties. For example, one or more conductive nitrides may be selected from silicon nitride (SiNX, Si3N4), aluminum nitride (AlN), gallium nitride (GN), tantalum nitride (TaN, Ta2N), titanium nitride (TiN, Ti2N), and tungsten nitride (WN, W2N, WN2), among other possibilities. The electrode material114may be formed to various widths (e.g., thicknesses)124-6as suited to a particular design rule for the formation of an operable capacitor for a semiconductor device.

In at least one example, the width or diameter respective openings132-1,132-2(hereinafter referred to collectively as openings132) between plurality of pillars109-1and109-2may be within a range of approximately 200-600 Angstroms (or 20 to 60 nm) and the height of the openings132may be within a range of approximately 8,000-15,000 Angstroms (800-1,500 nm) and may result in an aspect ratio (AR) of the height to width being in a range of approximately 25:1 to approximately 50:1. For clarity in the example fabrication sequence, the figures show a first opening132-1and a second opening132-2but examples are not limited to two openings and may include various numbers of openings.

As the height122of the plurality of pillars109-1to109-N increases, the thickness of the hard mask material110may increase as well. Subsequent dry etches to straighten the capacitor column and etch away the hard mask material110and subsequently a liner material may result in a loss of pillar materials particularly the second nitride material108. The plurality of pillars109may be formed using a pattern of materials. The plurality of pillars109may be formed using a pattern of materials. The plurality of pillars109may, in a number of examples, be formed by patterning (e.g., depositing) a first silicate material103, a first nitride material105, a second silicate material106, a second nitride material108, the hard mask material110, and the electrode material114. A support structure formed as such may enable a stack of the first and the second silicate materials103,106to be maintained in a more static configuration relative to each other and the underlying working surface101than provided by the first and the second silicate materials103,106themselves.

An etch process (e.g., a first wet etch process or dry etch process) may be utilized to etch into (e.g., through) the hard mask material110, the second nitride material108, the second silicate material106, the first nitride material105, and/or the first silicate material103to form the opening within the previously listed materials (as is illustrated already as opening132-1between the plurality of pillars109-1and109-2). Performance of the etch process may allow for a formation of an opening (within which a column of silicon liner material can be deposited) that extends from the upper surface of the hard mask material110to the surface of the working surface101.

The resultant openings132may have a height122in a range of from approximately 8,000 Angstroms (or 800 nm) to approximately 15,000 Angstroms (or 1,500 nm). Each of the materials may contribute a particular height to the overall height122of the structure. As is illustrated inFIG. 1, the first silicate material103can have a height124-1, the first nitride material105can have a height124-2, the second silicate material106can have a height124-3, the second nitride material108can have a height124-4, the hard mask material110can have a height124-5, and the electrode material114can have a height/thickness124-6that, when added together, results in the overall height122.

In some examples, the height124-1of the first silicate material103can be one of approximately 2000 Angstroms, approximately 2400 Angstroms, approximately 3600 Angstroms, approximately 4000 Angstroms, approximately 4200 Angstroms, approximately 4500 Angstroms, approximately 4900 Angstroms, approximately 5300 Angstroms, approximately 5700 Angstroms, and/or within a range from approximately 2000 Angstroms to approximately 6000 Angstroms. In some examples, the height124-2of the first nitride material105can be one of approximately 50 Angstroms, approximately 100 Angstroms, approximately 400 Angstroms, approximately 550 Angstroms, and/or within a range from approximately 50 to approximately 600 Angstroms. In some examples, the height124-3of the second silicate material108can be one of approximately 2500 Angstroms, approximately 3500 Angstroms, approximately 4200 Angstroms, and/or within a range from approximately 2500 to 4500 Angstroms. In some examples, the height124-4of the second nitride material108can be one of approximately 200 Angstroms, approximately 750 Angstroms, approximately 970 Angstroms, and/or within a range from approximately 200 to approximately 1000 Angstroms. However, embodiments of the present disclosure are not limited to this example.

FIG. 2illustrate cross-sectional views291of a portion of a semiconductor structure of a memory device in association with a semiconductor fabrication sequence for patterning a semiconductor structure in accordance with a number of examples of the present disclosure.FIG. 2illustrates the example semiconductor structure at the particular stage following completion of the example fabrication sequence described in connection withFIG. 1.

The cross-sectional view291may include the same or similar elements as the example cross-sectional view190as referenced inFIG. 1. For example, the working surface201is analogous or similar to working surface101. First silicate material203is analogous or similar to first silicate material103, first nitride material205is analogous or similar to first nitride material105, second silicate material206is analogous or similar to second silicate material106, second nitride material208is analogous or similar to second nitride material108, and electrode material214is analogous or similar to electrode material114.

As illustrated inFIG. 2, the hard mask material (110as illustrated inFIG. 1) has been removed from the portion of the example memory device shown inFIG. 1. As the height222of the plurality of pillars209increases, the thickness of the hard mask material may increase. Subsequent dry etches may be used to straighten the capacitor column and etch away the electrode material214and the hard mask material. The hard mask material may be removed by (via application of) dry etch.

The dry etch may be a mixture of a selective solvent may be selected from water (H2O), methanol (CH3OH), ethanol (C2H5OH), isomers of propanol (C3H7OH) such as n-propanol and isopropanol, n-butanol (C4H9OH), among other possible alcohols, and sulfuric acid (H2SO4), Hydrofluoric acid (HF), Phosphoric Acid (H3PO4), Hydrochloric Acid (HCl), Ammonium Hydroxide (NH4OH), and combinations thereof, among other possibilities. The dry etch may be used to etch away the hard mask material on top of the second nitride material208. The dry etch may be used to etch away the entirety of the hard mask material. For example, the dry etch may remove approximately 50 nm to 400 nm of the hard mask material above the surface of the second nitride material208. The removal of the hard mask material leaves the second nitride material208exposed at the top of the plurality of the pillars209.

FIG. 3Aillustrates a cross-sectional view392of a portion of semiconductor structure of a memory device in association with a semiconductor fabrication sequence for patterning a semiconductor structure in accordance with a number of examples of the present disclosure.FIG. 3illustrates the example semiconductor structure at a particular stage following completion of the example fabrication sequence described in connection withFIG. 2.

The cross-sectional view392can include the same or similar elements as the example cross-sectional views190and291as referenced inFIGS. 1 and 2, respectively. For example, the working surface301is analogous or similar to working surface101and201ofFIGS. 1 and 2, respectively. The first silicate material303is analogous or similar to first silicate material103and203ofFIGS. 1 and 2, respectively. The first nitride material305is analogous or similar to first nitride material105and205ofFIGS. 1 and 2, respectively. The second silicate material306is analogous or similar to second silicate material106and206ofFIGS. 1 and 2, respectively. The second nitride material308is analogous or similar to second nitride material108and208ofFIGS. 1 and 2, respectively. The electrode material314is analogous or similar to electrode material114and214ofFIGS. 1 and 2, respectively.

In one example, a liner material316may be deposited within the openings332to create more stability within the semiconductor structure. The liner material316may fill the openings332such that it is be deposited on the upper surfaces of the plurality of pillars309. The liner material316may fill the openings332from the surface of the working surface to a height322of the openings332at the upper surface of the plurality of pillars309. The liner material316may, in a number of examples, be formed from a silicon material and may be referred to as a silicon liner material316. The liner material316may, in a number of examples, be formed from monocrystalline silicon (monosilicon), polycrystalline silicon (polysilicon), and amorphous silicon, among other possibilities.

Following the etching of the hard mask material (110, as illustrated inFIG. 1), the liner material316may be deposited on the exposed second nitride material308. The liner material316may, in a number of examples, be deposited to a thickness in a range of approximately 50 nm to 500 nm above the surface of the second nitride material108. The resultant structure may have a height322in a range of from approximately 8,000 Angstroms (or 800 nm) to approximately 15,000 Angstroms (or 1,500 nm). Each of the materials may contribute a particular height to the overall height322of the structure. As is illustrated inFIG. 3, the first silicate material303can have a height324-1, the first nitride material305can have a height324-2, the second silicate material306can have a height324-3, the second nitride material308can have a height324-4, and the liner material316can have a height324-8that, when added together, results in the overall height322.

FIG. 3Billustrates a cross-sectional view382of a portion of semiconductor structure of a memory device in association with a semiconductor fabrication sequence for patterning a semiconductor structure in accordance with a number of examples of the present disclosure.FIG. 3illustrates the example semiconductor structure at a particular stage following completion of the example fabrication sequence described in connection withFIG. 3A.

The cross-sectional view382can include the same or similar elements as the example cross-sectional views190,291, and392as referenced inFIGS. 1, 2, and 3A, respectively. For example, the working surface301is analogous or similar to working surface101and201ofFIGS. 1 and 2, respectively. The first silicate material303is analogous or similar to first silicate material103and203ofFIGS. 1 and 2, respectively. The first nitride material305is analogous or similar to first nitride material105and205ofFIGS. 1 and 2, respectively. The second silicate material306is analogous or similar to second silicate material106and206ofFIGS. 1 and 2, respectively. The second nitride material308is analogous or similar to second nitride material108and208ofFIGS. 1 and 2, respectively. The electrode material314is analogous or similar to electrode material114and214ofFIGS. 1 and 2, respectively. The liner material316is analogous or similar to liner material316ofFIG. 3A.

As illustrated inFIG. 3B, the top of the liner material316has been removed from the portion of the example semiconductor structure shown inFIG. 3A. The top of the liner material316may be removed by (via application of) wet etch. The removal of the top of the liner material316leaves the second nitride material308exposed at the top of the plurality of the pillars309.

The wet etch may be a solvent formed from ammonium, and combinations thereof, among other possibilities. The wet etch may be used to etch away the top of the liner material316. The liner material316may be deposited within the openings332to create more stability within the semiconductor structure. After the wet etch to remove the top of the liner material316, the liner material316may fill the openings332from the surface of the working surface to a height near the surface of the second nitride material308.

An etch of the top of the liner material616may cause a recess of the liner material316to a depth (D)313between the walls of the electrode614. The liner material316may recess below the second nitride material308to a less extent using the wet etch process, described herein, as it is removed. This result can be advantageous as a recess may cause less stability to the pillars309in subsequent processing steps and allow for shorts, or other defects, within a resulting semiconductor structure. Advantageously, in some example embodiments according to particular design rules and/or aspect ratios (A/R) of greater than 25:1, using a wet etch may cause the liner material316to recess by a range of 2 nm to 20 nm. As such, using a wet etch may lessen the liner material316recess by a range of 10% to 20% over using a dry etch process.

FIG. 4illustrates a cross-sectional view493of a portion of semiconductor structure of a memory device in association with a semiconductor fabrication sequence for patterning a semiconductor structure in accordance with a number of examples of the present disclosure.FIG. 4illustrates the example semiconductor structure following completion of the example fabrication sequence described in connection withFIG. 1.

The cross-sectional view493can include the same or similar elements as the example cross-sectional views190,291,392, and382as referenced inFIGS. 1, 2, 3A, and 3Brespectively. For example, the working surface401is analogous or similar to working surface101,201, and301ofFIGS. 1, 2, 3A, and 3Brespectively. The first silicate material403is analogous or similar to first silicate material103,203, and303ofFIGS. 1, 2, 3A, and 3Brespectively. The first nitride material405is analogous or similar to first nitride material105,205, and305ofFIGS. 1, 2, 3A, and 3Brespectively. The second silicate material406is analogous or similar to first silicate material106,206, and306ofFIGS. 1, 2, 3A, and 3Brespectively. The second nitride material408is analogous or similar to second nitride material108,208, and308ofFIGS. 1, 2, 3A, and 3Brespectively. The electrode material414is analogous or similar to electrode material114,214, and314ofFIGS. 1, 2, 3A, and 3Brespectively. The hard mask material410is analogous or similar to hard mask material110ofFIG. 1.

As illustrated inFIG. 4, a portion of the hard mask material410has been removed from the portion of the example memory device shown inFIG. 1using a controlled dry etch. As the height422of the plurality of pillars409increases, the thickness of the hard mask material410may increase. Subsequent dry etches may be used to straighten the capacitor column and etch away the hard mask material410. As such, the hard mask material410may be removed by (via application of) dry etch.

The dry etch may be a mixture of a selective solvent may be selected from water (H2O), methanol (CH3OH), ethanol (C2H5OH), isomers of propanol (C3H7OH) such as n-propanol and isopropanol, n-butanol (C4H9OH), among other possible alcohols, and sulfuric acid (H2SO4), Hydrofluoric acid (HF), Phosphoric Acid (H3PO4), Hydrochloric Acid (HCl), Ammonium Hydroxide (NH4OH), and combinations thereof, among other possibilities.

In this example embodiment, the controlled dry etch may be used to etch away a portion of the hard mask material, but leave a remaining portion of the hard mask material410as a buffer. In some embodiments, the dry etch may be used to etch away approximately 60% of the hard mask material (110as illustrated inFIG. 1) above the second nitride material408. In one example, up to approximately 40% of an original thickness of the hard mask material410may be remaining after the controlled dry etch removal process in order to protect the second nitride material408from removal in subsequent processing steps. In this example, the height (124-5inFIG. 1) of hard mask material410may be reduced to the height424-7.

In previous approaches, the second nitride material408may be a thicker height than described in connection with the present application because of the inclusion of a sacrificial portion of the second nitride material408. Also, in previous approaches, a dry etch is used to etch away a liner material (316as illustrated inFIG. 3). And, as a result, the sacrificial portion of the second nitride would be used because the dry etch will attack and remove a portion of the second nitride material408.

It is possible that as a wet etch is used in the present description and in the description ofFIGS. 1-3B, the wet etch, too, may remove a portion of a liner material filled in the openings432-1and432-2and that the wet etch without the remaining hard mask material410serving as a buffer the wet may also etch away a portion of the second nitride material208shown inFIG. 2.

However, in the present example embodiment, having the remaining hard mask material410as protection for the second nitride material408means a thinner nitride material may be used. During the wet etch process, the wet etch may remove the remaining hard mask material410and not, or to a lesser degree, the second nitride material408. As such, according to this example embodiment, a sacrificial portion may no longer be needed for the second nitride material408because the second nitride material408is protected by the remaining hard mask material410. In some embodiments, a thinner second nitride material408may produce a capacitance gain between 0.1 to 2%, or 0.1 to 0.5 femto Farads (fF) in capacitance in certain design rules. For example, more of a second silicate material406may be deposited to a greater height for taller pillars409within an acceptable stability and an overall greater height to a storage node structure may be realized. With more height, a resultant surface area for a capacitor structure may be increased allowing for a greater storage capacitance value. This is described further next in connection withFIGS. 5 and 6to the present embodiment.

FIG. 5illustrates a cross-sectional view594of a portion of semiconductor structure of a memory device in association with a semiconductor fabrication sequence for patterning a semiconductor structure in accordance with a number of examples of the present disclosure.FIG. 5illustrates the example semiconductor structure following completion of the example fabrication sequence described in connection withFIG. 4.

The cross-sectional view594can include the same or similar elements as the example cross-sectional views190,291,392,382, and493as referenced inFIGS. 1, 2, 3A, 3B, and 4respectively. For example, the working surface501is analogous or similar to working surface101,201,301, and401ofFIGS. 1, 2, 3, and 4respectively. The first silicate material503is analogous or similar to first silicate material103,203,303, and403ofFIGS. 1, 2, 3, and 4respectively. The first nitride material505is analogous or similar to first nitride material105,205,305, and405ofFIGS. 1, 2, 3, and 4respectively. The second silicate material506is analogous or similar to first silicate material106,206,306, and406ofFIGS. 1, 2, 3, and 4, respectively. The second nitride material508is analogous or similar to second nitride material108,208,308, and408ofFIGS. 1, 2, 3, and 4respectively. The electrode material514is analogous or similar to electrode material114,214,314and414ofFIGS. 1, 2, 3, and 4, respectively. The hard mask material510is analogous or similar to hard mask material110and410ofFIGS. 1 and 4respectively.

In one example, a liner material516may be deposited within the openings532to create more stability within the semiconductor structure. The liner material516may fill the openings532such that it is be deposited on the upper surfaces of the plurality of pillars509. The liner material516may fill the openings532from the surface of the working surface501to a height522of the openings532at the upper surface of the plurality of pillars509.

Following the etching away of a portion of the hard mask material510, the liner material516may be deposited on the remaining portion of the hard mask material510, opposite the second nitride material508. The liner material516may, in a number of examples, be deposited to a thickness in a range of approximately 50 nm to 500 nm above the surface of the remaining portion of the hard mask material510.

The resultant semiconductor structure may have a height522in a range of from approximately 8,000 Angstroms (or 800 nm) to approximately 15,000 Angstroms (or 1,500 nm). Each of the materials may contribute a particular height to the overall height522of the structure. As is illustrated inFIG. 5, the first silicate material503can have a height524-1, the first nitride material505can have a height524-2, the second silicate material506can have a height524-3, the second nitride material508can have a height524-4, the remaining portion of the hard mask material510can have a height524-7, and the liner material516can have a height524-8that, when added together, results in the overall height522.

FIG. 6illustrates a cross-sectional view695of a portion of semiconductor structure of a memory device in association with a semiconductor fabrication sequence for patterning a semiconductor structure in accordance with a number of examples of the present disclosure.FIG. 6illustrates the example semiconductor structure at the particular stage following completion of the example fabrication sequence described in connection withFIG. 5.

The cross-sectional view695can include the same or similar elements as the example cross-sectional views190,291,392,382,493, and594as referenced inFIGS. 1, 2, 3A, 3B, 4, and 5respectively. For example, the working surface601is analogous or similar to working surface101,201,301,401, and501ofFIGS. 1, 2, 3, 4, and 5respectively. The first silicate material603is analogous or similar to first silicate material103and203ofFIGS. 1 and 2respectively. The first nitride material605is analogous or similar to first nitride material105,205,305,405, and505ofFIGS. 1, 2, 3, 4, and 5respectively. The second silicate material606is analogous or similar to second silicate material106,206,306,406, and506ofFIGS. 1, 2, 3, 4, and 5respectively. The second nitride material608is analogous or similar to second nitride material108,208,308,408, and508ofFIGS. 1, 2, 3, 4, and 5respectively. The electrode material614is analogous or similar to electrode material114,214,314,414, and514ofFIGS. 1, 2, 3, 4, and 5respectively.

As illustrated inFIG. 6, the remaining portion of the hard mask material and the top of the liner material616have been removed from the portion of the example semiconductor structure shown inFIG. 5. The remaining portion of the hard mask material and the top of the liner material616may be removed by (via application of) wet etch. The removal of the remaining portion of the hard mask material leaves the second nitride material608exposed at the top of the plurality of the pillars609and maintains an intended height (H)622to walls of the electrodes614, e.g., bottom electrodes.

The wet etch may be a solvent formed from ammonium, and combinations thereof, among other possibilities. The wet etch may be used to etch away the top of the liner material616and the hard mask material. The second nitride material608may be protected from the wet etch by the hard mask material. The liner material616may be deposited within the openings632to create more stability within the semiconductor structure. After the wet etch to remove the top of the liner material616, the liner material616may fill the openings632from the surface of the working surface to a height near the surface of the second nitride material608.

An etch of the top of the liner material616and the hard mask material may cause a recess of the liner material616to a depth (D)613between the walls of the electrode614. The liner material616may recess below the second nitride material608to a less extent using the wet etch process, described herein, and/or due to the buffer of the remaining hard mask material (510fromFIG. 5) as it is removed. This result can be advantageous as a recess may cause less stability to the pillars609in subsequent processing steps and allow for shorts, or other defects, within a resulting semiconductor structure. Advantageously, in some example embodiments according to particular design rules and/or aspect ratios (A/R) of greater than 25:1, using a wet etch may cause the liner material616to recess by a range of 2 nm to 20 nm. As such, using a wet etch may lessen the liner material616recess by a range of 10% to 20% over using a dry etch process and/or not maintaining the buffer of the remaining hard mask material (510inFIG. 5).

FIG. 7illustrates a cross-sectional view730of a portion of an example semiconductor structure of a memory device in association with a semiconductor fabrication sequence for patterning a semiconductor structure in accordance with a number of examples of the present disclosure.FIG. 7illustrates the example semiconductor structure following completion of the example fabrication sequence described in connection withFIG. 6.

Using the techniques and method embodiments described herein has allowed maintaining a height (H)722to achieve greater surface area to the storage node structure, e.g., capacitor cell, permitting an increase in the capacitance of the one (1) to five (5) percent (1-5%) according to a particular design rule. As shown, the dielectric material723has been formed (e.g., deposited) on an outer surface of the electrode material714. The dielectric material723may, in a number of examples, be formed from a surface of the working surface701to cover the outer surface, including an upper surface, of the electrode material714. A capacitor may be subsequently formed, at least in part, by formation (e.g., deposition) of a top electrode material747on an outer surface of the dielectric material723.

As is illustrated inFIG. 7, a height722of the semiconductor support structure can include a height724-2and724-4of the first nitride material705and the second nitride material708along with heights724-1, and724-3of the removed first silicate material, and the second silicate material.

A height722of the capacitor may be higher than the height of the original opening (H622) due to the maintained height of the second nitride material708and resultantly the electrode material714, the added height of the dielectric material723, and the top electrode material747, being formed over the electrode material714. The dielectric material723and the top electrode material547may be formed from various respective dielectric materials, conductive materials, and resistive materials and to various width (e.g., thickness) usable in association with formation of an operable silicon fill material721for a semiconductor device.

The support structure is formed from the first nitride material705and the second nitride material708, in addition to the underlying working surface701. The support structure may provide support to the silicon fill material721after the removal of the first and second silicate materials has left voids in the semiconductor structure and even after such voids may have been at least partially filled by a buffer material. The support structure formed from the first and second nitride materials705,708is shown for ease of illustration in what can be a 3D-cross sectional view to be supporting behind the silicon fill material721and the right side of the electrode material714. However, the support structure formed from the first and second nitride materials705,708also may be on the opposite sides, or may be attached at four position or even surround, the silicon fill material721. In a number of examples, the dielectric material723and/or the top electrode material747may surround the electrode material714except at defined positions where the first and second nitride materials705,708of the support structures are attached to the electrode material714.

Formation of the capacitors and a capacitor support structure as just described may enable each of the capacitors to be maintained in a static configuration (e.g., relative to each other and the underlying material). For example, the capacitor support structure may reduce (e.g., prevent) a possibility of a capacitor bending and/or twisting during fabrication or use. By including a sacrificial storage node, as described herein, the width for openings732may be widened, increasing the space for the capacitor to be filled. The capacitor may be filled into the openings732, leaving space for another capacitor material to be filled without the two capacitor materials touching. For example, the widening of the openings732.

Formation of the capacitors and capacitor support structure as just described may be utilized in fabrication of a memory device that includes at least one memory cell. Such a memory cell may include at least one such capacitor, as a data storage element, that is supported by the capacitor support structure. The memory cell also may include at least one access device (e.g., transistor) (not shown) that is, or may be, coupled to the at least one capacitor.

FIG. 8is a functional block diagram of a system860for implementation of an example semiconductor fabrication process in accordance with a number of embodiments of the present disclosure. The system860can include a processing apparatus861. The processing apparatus861can be configured to enable patterning a semiconductor structure.

The processing apparatus861can include a semiconductor processing chamber862to enclose components configured to pattern a semiconductor structure. The chamber862can further enclose a carrier863to hold a batch of semiconductor wafers864(e.g., the working surface101). The processing apparatus861can include and/or be associated with tools including, for example, a pump865unit and a purge866unit configured to introduce and remove reactants. In one example, the reactants may include precursors/reducing agents. The processing apparatus861can further include a temperature control867unit configured to maintain the chamber862at appropriate temperatures as described herein.

The system860can further include a controller868. The controller868can include, or be associated with, circuitry and/or programming for implementation of, for instance, depositing a storage node material. Adjustment of such deposition and purging operations by the controller868can control the thickness of the materials described herein (the first silicate material, the first nitride material, the first silicate material, and the second nitride material).

The controller868can, in a number of embodiments, be configured to use hardware as control circuitry. Such control circuitry may, for example, be an application specific integrated circuit (ASIC) with logic to control fabrication steps, via associated deposition and purge processes, for patterning a semiconductor structure.

FIG. 9is a functional block diagram of a computing system980including at least an example of semiconductor structure of a memory system944in accordance with one or more examples of the present disclosure. Memory system944may be, for example, a solid-state drive (SSD).

In the example illustrated inFIG. 9, memory system944includes a memory interface946, a number of memory devices940-1, . . . ,940-N, and a controller948selectably coupled to the memory interface946and memory devices940-1, . . . ,940-N. Memory interface946may be used to communicate information between memory system944and another device, such as a host942. Host942may include a processor (not shown). As used herein, “a processor” may be a number of processors, such as a parallel processing system, a number of coprocessors, etc. Example hosts may include, or be implemented in, laptop computers, personal computers, digital cameras, digital recording devices and playback devices, mobile telephones, PDAs, memory card readers, interface hubs, and the like. Such a host may be associated with fabrication operations performed on semiconductor devices and/or SSDs using, for example, a processing.

In a number of examples, host942may be associated with (e.g., include or be coupled to) a host interface943. The host interface943may enable input of scaled preferences (e.g., in numerically and/or structurally defined gradients) to define, for example, critical dimensions (CDs) of a final structure or intermediary structures of a memory device (e.g., as shown at940) and/or an array of memory cells (e.g., as shown at954) formed thereon to be implemented by the processing apparatus. The scaled preferences may be provided to the host interface943via input of a number of preferences stored by the host942, input of preferences from another storage system (not shown), and/or input of preferences by a user (e.g., a human operator).

Memory interface946may be in the form of a standardized physical interface. For example, when memory system944is used for information (e.g., data) storage in computing system980, memory interface946may be a serial advanced technology attachment (SATA) interface, a peripheral component interconnect express (PCIe) interface, or a universal serial bus (USB) interface, among other physical connectors and/or interfaces. In general, however, memory interface may provide an interface for passing control, address, information, scaled preferences, and/or other signals between the controller948of memory system944and a host942(e.g., via host interface943).

Controller948may include, for example, firmware and/or control circuitry (e.g., hardware). Controller948may be operably coupled to and/or included on the same physical device (e.g., a die) as one or more of the memory devices940-1, . . . ,940-N. For example, controller948may be, or may include, an ASIC as hardware operably coupled to circuitry (e.g., a printed circuit board) including memory interface946and memory devices940-1, . . . ,940-N. Alternatively, controller948may be included on a separate physical device that is communicatively coupled to the physical device (e.g., the die) that includes one or more of the memory devices940-1, . . . ,940-N.

Controller948may communicate with memory devices940-1, . . . ,940-N to direct operations to sense (e.g., read), program (e.g., write), and/or erase information, among other functions and/or operations for management of memory cells. Controller948may have circuitry that may include a number of integrated circuits and/or discrete components. In a number of examples, the circuitry in controller948may include control circuitry for controlling access across memory devices940-1, . . . ,940-N and/or circuitry for providing a translation layer between host942and memory system944.

Memory devices940-1, . . . ,940-N may include, for example, a number of memory arrays954(e.g., arrays of volatile and/or non-volatile memory cells). For instance, memory devices940-1, . . . ,940-N may include arrays of memory cells, such as a portion of an example memory device990structured to form structures formed according to embodiments described inFIGS. 1-7, described in connection withFIG. 9. As will be appreciated, the memory cells in the memory arrays954of memory devices940-1, . . . ,940-N may be in a RAM architecture (e.g., DRAM, SRAM, SDRAM, FeRAM, MRAM, ReRAM, etc.), a flash architecture (e.g., NAND, NOR, etc.), a three-dimensional (3D) RAM and/or flash memory cell architecture, or some other memory array architecture including pillars and adjacent trenches.

Memory devices940may be formed on the same die. A memory device (e.g., memory device940-1) may include one or more arrays954of memory cells formed on the die. A memory device may include sense circuitry955and control circuitry956associated with one or more arrays954formed on the die, or portions thereof. The sense circuitry955may be utilized to determine (sense) a particular data value (e.g., 0 or 1) that is stored at a particular memory cell in a row of an array954. The control circuitry956may be utilized to direct the sense circuitry955to sense particular data values, in addition to directing storage, erasure, etc., of data values in response to a command from host942and/or host interface943. The command may be sent directly to the control circuitry956via the memory interface946or to the control circuitry956via the controller948.

The example illustrated inFIG. 9may include additional circuitry that is not illustrated so as not to obscure examples of the present disclosure. For example, memory devices940may include address circuitry to latch address signals provided over I/O connectors through I/O circuitry. Address signals may be received and decoded by a row decoder and a column decoder to access a memory array954. It will be appreciated that the number of address input connectors may depend on the density and/or architecture of memory devices940and/or memory arrays954.

FIG. 10illustrates a cross-sectional view of transistors in accordance with a number of embodiments of the present disclosure.FIG. 10illustrates a gate1021-1, . . . ,1021-N (individually or collectively referred to as gate1021) during a fabrication process. The gate1021can also be referred to as a gate electrode. The gate1021may be a gate to a recessed access device, e.g., a buried recessed access device (BRAD). In the example shown, the gate1021may include a first portion1026including a metal, e.g., titanium nitride (TiN), and a second portion1036including a doped polysilicon to form a hybrid metal gate (HMG)1021. The gate1021may be separated from a channel1035, separating a first source/drain region1076-1and1076-2(collectively referred to as first source/drain region1076) and a second source/drain region1072-1and1072-2(collectively referred to as second source/drain region1072) by a gate dielectric1037. In the example ofFIG. 1, two neighboring access devices1021and1023are shown sharing a second source/drain region1072at a junction.

In the example ofFIG. 10, a storage node1031may be coupled to the second source/drain region1072. An insulation material1040(e.g., a dielectric material) can be formed on the spacer material1026and the gate mask material1038, and in contact with the metallic material1034. In at least one embodiment, a first portion1028of the metallic material1034can be formed in contact with the spacer material1026, the source/drain regions1072and1076, and the junction. The insulation material1040can be formed on the spacer material1026and the gate mask material1038, and in contact with the metallic material1034.

It is to be understood that the terminology used herein is for the purpose of describing particular examples only and is not intended to be limiting. As used herein, the singular forms “a”, “an”, and “the” include singular and plural referents, unless the context clearly dictates otherwise, as do “a number of”, “at least one”, and “one or more” (e.g., a number of memory arrays may refer to one or more memory arrays), whereas a “plurality of” is intended to refer to more than one of such things. Furthermore, the words “can” and “may” are used throughout this application in a permissive sense (i.e., having the potential to, being able to), not in a mandatory sense (i.e., must). The term “include,” and derivations thereof, means “including, but not limited to”. The terms “coupled” and “coupling” mean to be directly or indirectly connected physically and, unless stated otherwise, can include a wireless connection for access to and/or for movement (transmission) of instructions (e.g., control signals, address signals, etc.) and data, as appropriate to the context.

While example examples including various combinations and configurations of semiconductor materials, underlying materials, structural materials, dielectric materials, capacitor materials, working surface materials, silicate materials, nitride materials, buffer materials, etch chemistries, etch processes, solvents, memory devices, memory cells, sidewalls of openings and/or trenches, among other materials and/or components related to patterning a semiconductor structure have been illustrated and described herein, examples of the present disclosure are not limited to those combinations explicitly recited herein. Other combinations and configurations of the semiconductor materials, underlying materials, structural materials, dielectric materials, capacitor materials, substrate materials, silicate materials, nitride materials, buffer materials, etch chemistries, etch processes, solvents, memory devices, memory cells, sidewalls of openings and/or trenches related to patterning a semiconductor structure than those disclosed herein are expressly included within the scope of this disclosure.

In the foregoing Detailed Description, some features are grouped together in an example for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the disclosed examples of the present disclosure have to use more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a disclosed example. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate example.