Apparatus and associated method for making a virtual ground array structure that uses inversion bit lines

A virtual ground array structure uses inversion bit lines in order to eliminate the need for implanted bit lines. As a result, the cell size can be reduced, which can provide greater densities and smaller packaging.

BACKGROUND

1. Field of the Invention

The embodiments described herein are directed to virtual ground array memory structures, and more particularly to a virtual ground array structure that uses inversion bit lines in place of the conventional implanted bit lines.

2. Background of the Invention

It is well known to use virtual ground array designs in order to reduce the cell size for non-volatile memory products, such as flash memory products. While virtual ground structures have allowed reduction in the overall cell size in a virtual ground array, the achievable cell size reductions are still limited. As new applications call for ever smaller packaging and increased densities, further reductions in cell size are highly desirable.

One limitation in cell size reduction for conventional virtual ground structures, for example, is the need for implanted bit lines. The inclusion of the implanted bit lines requires a certain area for each cell. If the need for the implanted bit lines is eliminated, then the cell size can be reduced; however, conventional virtual ground array structures require the implanted bit lines.

SUMMARY

A virtual ground array structure uses inversion bit lines in order to eliminate the need for implanted bit lines. As a result, the cell size can be reduced, which can provide greater densities and smaller packaging.

In another aspect, a method for fabricating a virtual ground array structure that uses inversion bit lines is disclosed.

These and other features, aspects, and embodiments of the invention are described below in the section entitled “Detailed Description.”

DETAILED DESCRIPTION

In the embodiments described below reduced cell sizes in a virtual ground array can be achieved by eliminating implanted bit lines. In place of the implanted bit lines, the structures described herein use inversion bit lines to conduct the drain and source voltages required for operation. The elimination of implanted bit lines reduces the area required for each cell and allows a reduced cell size.

FIG. 1Ais a diagram illustrating a top view of a virtual ground array structure100configured in accordance with one embodiment. Structure100is formed on a substrate102. In the example ofFIG. 1A, substrate102is a P-type substrate; however, it will be understood that in other embodiments substrate102can be an N-type substrate. N+ implanted diffusion regions112and114are then formed in substrate102. Diffusion regions112and114can act as source and drain regions for a particular cell as will be explained below. Polysilicon bit lines104and106are then formed on substrate102as illustrated. Polysilicon word lines110and108are then formed over and perpendicular to bit lines104and106. In the example ofFIG. 1A, bit lines104and106are formed in the Y direction, while word lines110and108are formed in the X direction.

Various contacts are then formed that contact diffusion regions112and114, bit lines104and106, and word lines108and110. Thus, contact116is formed so as to contact implantation region112, contact126is formed so as to contact implantation region114, contact118is formed so as to contact bit line106, contact120is formed so as to contact word line108, contact122is formed so as to contact word line110, and contact124is formed so as to contact bit line104. These contacts can be used to supply the appropriate voltages to the appropriate portions of the cell.

FIG. 1Bis a diagram illustrating a cross section of structure100along line AA′. As can be seen in the cross section, word line108is formed over a polysilicon layer202. Word line108can be said to be formed from a third poly layer, while polysilicon layer202can be referred to as a first poly layer. Bit lines104and106can then be formed from a second poly layer. The third poly and the first poly layers can be connected so as to form a gate structure between bit lines104and106. A gate dielectric layer can then be formed under the gate structure.

In the example ofFIG. 1, the gate dielectric layer below the gate structure includes an Oxide-Nitride-Oxide (ONO) layer formed from oxide layer204, nitride layer206, and oxide layer208. Oxide layers204and208can, e.g., be silicon dioxide (SiO2) layers, while nitride layer206can be a Silicon Nitride (SiN) layer.

In the example ofFIG. 1, dielectric layer208also extends below polysilicon bit lines104and106. Thus, in the example ofFIG. 1, there is a single dielectric layer208below polysilicon bit lines104and106and above inversion bit lines210and212. In other embodiments, however, the dielectric layer below polysilicon bit line104and106can comprise an Oxide-Nitride (ON) structure. In still other embodiments, the dielectric layer below polysilicon bit lines104and106can comprise an ONO structure. Depending on the fabrication process used, the dielectric layer below polysilicon bit lines104and106can also comprise a residual oxide layer left after an ON etching process, or re-grown oxide layer formed after an ONO etching process.

As can be seen, structure100does not comprise implanted bit lines below with polysilicon bit lines104and106. Instead, when the appropriate voltages are applied to bit lines104and106, inversion bit lines210and212will be formed. Inversion bit lines210and212can then be used to conduct the source and drain voltages as required.

FIG. 2Ais diagram illustrating a top view of a virtual ground array structure200that is similar to structure100, except that structure200only includes a single word line108.FIG. 2Bis a diagram illustrating a cross section along the line BB′ of structure200.

As withFIG. 1A, it can be seen that word line108can be formed from a third poly layer. The third poly layer can be formed on top of another polysilicon layer202, which can be referred to as the first poly layer. The first and third poly layers can form a gate structure. The gate structure can also comprise a gate dielectric. The gate dielectric can be an ONO structure, e.g., formed from layers204,206, and208.

Bit lines104and106can then be formed from another polysilicon layer, which can be referred to as the second poly layer. Dielectric layer208can extend under bit lines104and106. Alternatively, an ON or ONO dielectric structure can be included in the regions under bit lines104and106.

The various layers and associated contacts can be fabricated so as to form cells, such as cell220. Cell220can be used to illustrate the application of various voltages during operation of a device comprising structure200. It will be understood that similar operation principles will apply for a two word line (or more) structure, such as that illustrated inFIG. 1.

Inversion bit lines210and212can be formed by applying sufficient voltage to bit lines104and106respectively. For example,FIG. 3is a diagram illustrating a cross section of structure100along the line CC′. As illustrated, inversion bit line210can be formed by applying a sufficient voltage, e.g., approximately +10 volts, to bit line104via contact124. Similarly,FIG. 4is a diagram illustrating a cross section of structure100across the line DD′. As can be seen, inversion bit line212can be formed by applying a sufficient voltage, e.g., approximately +10 volts, to bit line106via contact118.

Once inversion bit lines210and/or212are formed, cell220can be programmed, erased, or read, by applying the appropriate voltages to word line120, source region114, and drain region112. Applying the appropriate voltage to word line120will create a channel region between source and drain regions114and112respectively. Applying the appropriate voltages to drain region112and source region114, via contacts116and126respectively, can then create the lateral field necessary to cause carriers to migrate into the channel region and flow between drain region112and source region114. Device operating methods and conditions are described in detail with respect toFIGS. 7-12.

FIG. 5is a diagram illustrating a virtual ground array structure500configured in accordance with one embodiment. Like structure100, structure500uses inversion bit lines in order to reduce the cell size and therefore the overall size of array500. As can be seen, array500comprises a substrate502with implanted drain/source regions518,520,522, and524. Bit lines510,512,514, and516are then formed over substrate502in a Y direction. Word line504,506, and508are then formed perpendicular to bit lines510,512,514, and516as illustrated.

By applying the appropriate voltage to bit line510,512,514, and/or516, inversion bit lines can be formed within the upper layer of substrate502under bit lines510,512,514and/or516. Application of the appropriate voltages to word line504,506, and/or508, can then allow access to the appropriate cell in array500. The word line voltage will create a channel between source and drain regions for the cell, the inversion bit lines will conduct the appropriate drain and source voltages for programming, erasing, and reading.

FIGS. 7-12are diagrams illustrating example methods for operating array500in accordance with certain embodiments.FIG. 7is a diagram illustrating an example process for programming a first bit702of a selected cell700within array500. In the example ofFIG. 7, bit702can be programmed via Channel Hot Electron (CHE) programming techniques. In order to program bit702via CHE programming, a positive voltage must first be applied to bit lines510and512to create inversion bit lines in substrate502under bit lines510and512. In the example ofFIG. 7, a positive voltage of approximately +10 volts is applied to bit lines510and512. A positive voltage must also be applied to word line506in order to create a channel under the gate region of cell700. In the example ofFIG. 7, a positive voltage of approximately +10 volts is applied to word line506. A high voltage must be applied to diffusion region522, while a low voltage is applied to diffusion region518. In the example ofFIG. 7, a high voltage of approximately +5 volts is applied to diffusion region522, while a low voltage of 0 volts is applied to diffusion region518.

It will be understood, that the voltages illustrated inFIG. 7are by way of example only and that the actual voltages used will depend on the requirements of a specific implementation. For example, a voltage in the range of +5-+10 volts can be applied to bit lines104and106.

The voltages applied to diffusion regions518and522generate a large lateral electric field that causes electrons to flow into a channel created under word line506. The positive voltage applied to word line506then causes those electrons to inject into the gate structure of cell700. During the programming operation, bit lines514and516can be left floating as can diffusion regions520and524. Word lines504and508can be tied to 0 volts.

FIG. 8is a diagram illustrating CHE programming of a second bit704of selected cell700. As with the programming of bit702, a positive voltage is applied to each of bit lines510and512in order to create inversion bit lines in the upper layers of substrate502under bit lines510and512. Again, these inversion bit lines are used to conduct the source and drain voltages needed to program bit704. A positive voltage is then applied to word line506in order to activate the channel under the gate structure of selected cell700. Additionally, diffusion region518is tied to a high voltage while diffusion region522is tied to a low voltage to generate the lateral electric field needed to cause electrons to enter the channel of cell700. The high voltage on word line506will then cause some of these electrons to inject into the gate structure, thus programming bit704.

In the example ofFIG. 8, positive voltages of approximately +10 volts are applied to bit lines510and512, as well as word line506. A high voltage of approximately +5 volts is applied to diffusion region518, while a low voltage of approximately 0 volts is applied to diffusion region522. It will be understood, however, that the voltages illustrated with respect to the example ofFIG. 8are by way of example only and that the actual voltages will depend on the requirements of a specific implementation.

FIGS. 9 and 10are diagrams illustrating example processes for erasing bits for cells in array500. In the examples ofFIGS. 9 and 10, Band To Band Hot Hole (BTBHH) tunneling is used to erase multiple bits at a time.

For example, inFIG. 9the bits adjacent to bit lines510and514can be erased in one process via BTBHH tunneling. First, a positive voltage is applied to each of bit lines510,512,514, and516to produce inversion bit lines in the upper layers of substrate502under bit lines510,512,514, and516. Again, the inversion bit lines are used to conduct the source and drain voltages needed to perform the BTBHH erasing. Positive voltages are then applied to diffusion regions518and520to produce minority carriers in the upper regions of diffusion region518and520. A large negative voltage is then applied to bit lines504,506, and508in order to cause those minority carriers to tunnel into the gate structures of the selected cells, where they will compensate for any electrons trapped in the gate structure e.g., via CHE programming as described in relation toFIGS. 7 and 9. Diffusion regions522and524can be tied to 0 volts.

In the example ofFIG. 9, each of bits902,904,906,908,910,912,914,916,918,920,922, and924can be erased during one erase operation. It will be understood, however, that more or less bits can be erased by applying the appropriate voltages to the appropriate word and bit lines, while isolating other cells by tying the word and bit lines associated with those cells to 0 volts or letting them float as appropriate.

In the example ofFIG. 9, a positive voltage of approximately +10 volts is applied to bit lines510,512,514, and516. A large negative voltage of approximately −10 volts is applied to bit lines504,506, and508. A positive voltage of approximately +5 volts is applied to diffusion regions518and520. It will be understood, however, that the voltages illustrated with respect toFIG. 9are by way of example only and that the actual voltages used will depend on the requirements of a specific implementation.

FIG. 10is a diagram illustrating BTBHH erasing of the bits adjacent to bit lines512and516. Accordingly, a positive voltage is again applied to bit lines510,512,514, and516to produce the inversion bit lines in the upper layers of substrate502. Positive voltages are then applied to diffusion regions522and524in order to produce the minority carriers needed for the BTBHH operation. A large negative voltage is applied to word lines504,506, and508in order to attract minority carriers into the gate structures of the selected cells to erase bits926,928,930,932,934,936,938,940,942,944,946, and948at the same time. Diffusion regions518and520can be tied to 0 volts.

In the example ofFIG. 10, a positive voltage of approximately +10 volts can be applied to bit lines510,512,514, and516. Negative voltages of approximately −10 volts can be applied to word lines504,506, and508. Positive voltages of approximately +5 volts can be applied to diffusion regions522and524. It will be understood, however, that the voltages illustrated with respect toFIG. 10are by way of example only and that the actual voltages used will depend on the requirements of a specific implementation.

FIG. 11is a diagram illustrating an example process for reading a first bit1102of a selected cell1100in array500. In order to read bit1102, a positive voltage is applied to bit lines510and512in order to create inversion bit lines in the upper layer substrate502under bit lines510and512. A positive voltage is applied to word line506and to diffusion region522. Diffusion region518can be tied to 0 volts. Word lines504and508can also be tied to 0 volts, while bit lines514and516as well as diffusion regions520and524are allowed to float.

In the example ofFIG. 11, a positive voltage of approximately +10 volts is applied to bit lines510and512, while a positive voltage of approximately +5 volts is applied to word line506. A positive voltage of approximately +1.6 volts is applied to diffusion region522. It will be understood, however, that the voltages illustrated with respect toFIG. 11are by way of example only and that the actual voltages used will depend on the requirements of a specific implementation.

FIG. 12is a diagram illustrating an example process for reading a second bit1104of selected cell1100. Thus, a positive voltage can be applied to bit lines510and512to create the inversion bit lines in the upper layers of substrate502. A positive voltage can then be applied to word line506and to diffusion region518, while diffusion region522is tied to 0 volts. Word lines504and508can be tied to 0 volts, while bit lines514and516as well as diffusion regions520and524are allowed to float.

In the example ofFIG. 12, a positive voltage of approximately +10 volts is applied to bit lines510and512, while a positive voltage of approximately +5 volts is applied to word line506. A positive voltage of approximately +1.6 volts can be applied to diffusion region518. It will be understood, however, that the voltages illustrated in respect ofFIG. 12are by way of example only and that the actual voltages used will depend on the requirements of a specific implementation.

FIGS. 6A through 6Hare diagrams illustrating an example process for fabricating a virtual ground structure that uses inversion bit line such as structure100inFIG. 1. As illustrated inFIG. 6A, the fabrication of the virtual ground array structure begins with formation of a substrate602. In the example ofFIG. 6A, substrate602is a P type substrate; however, it will be apparent that substrate602can, depending on the embodiment, also be and an N-type substrate.

As illustrated inFIG. 6B, implantation regions604and606can then be formed in substrate602. In this example, implantation regions602and604are N+ implantation regions; however, it will be apparent that in embodiments where substrate602is an N-type substrate, implantation regions602and604will be P+ implantation regions.

Implantation regions602and604can be formed by forming a photoresist layer over substrate602. The photoresist layer can define region602and604. Implantation region602and604can then be formed and the photoresist layer can be removed.

It will understood, that implantation regions604and606are formed by accelerating ions at high energy onto substrate602, where they will be driven into substrate602and become embedded in the areas left unprotected by the photoresist layer. In certain embodiments, an annealing step can be used to heal any damage that result from the ion implantation.

As illustrated inFIG. 6C, after implantation of region604and606, a dielectric structure608can be formed over substrate602. For example, dielectric structure608can comprise an ONO structure formed from oxide layer612, SiN layer614, and oxide layer616. Layers612,614, and616can be formed, for example, using Chemical Vapor Deposition (CVD). In other embodiments, dielectric structure608can comprise an ON structure or an oxide layer. In still other embodiments, a dielectric structure608can be formed after the etching step described in relation toFIG. 6D. For example, a dielectric structure608can comprise an oxide layer re-grown after etching of ONO layers612,614, and616. In another embodiment, the dielectric structure can comprise a residual oxide layer formed after etching of an ON layer formed over substrate602.

A polysilicon layer610can then be deposited over structure608. Again, polysilicon layer610can be deposited using CVD.

InFIG. 6D, a photoresist612can be formed over N-type polysilicon layer610as illustrated. Photoresist layer612can be used to define layer610and608. Once photoresist layer612is formed, layer608and610can then be etched accordingly. After layer608and610are etched, photoresist layer612can be removed. The etching chemical and/or process used should be such that the etching stops at layer oxide layer616.

As illustrated inFIG. 6E, the trenches formed in the etching step described above can then be lined with oxide spacers613. Polysilicon layer614can then be formed in the trenches as illustrated inFIG. 6F. Polysilicon layer614can form the bit lines for the array.

As illustrated inFIG. 6G, a dielectric layer such as oxide layer616can then be formed over polysilicon layer614. For example, in one embodiment, oxide layer616can be formed using High Density Plasma techniques (HDP). Formation of the HDP oxide can then be followed by a planarization step. For example, an etch back process or chemical-mechanic-polish can be used to planarize the upper layers of the structure illustrated inFIG. 6G.

A polysilicon layer618can then be deposited over the planarized structure as illustrated inFIG. 6H. A photoresist layer (not shown) can then be formed in order to define layer618. Layer618can then be etched accordingly to form word lines, such as word line620illustrated inFIG. 61.

FIG. 6Iis a diagram illustrating the top view of an example structure fabricated using the process steps illustrated inFIGS. 6A-6H.

While certain embodiments of the inventions have been described above, it will be understood that the embodiments described are by way of example only. Accordingly, the inventions should not be limited based on the described embodiments. Rather, the scope of the inventions described herein should only be limited in light of the claims that follow when taken in conjunction with the above description and accompanying drawings.