256 Meg dynamic random access memory

A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to data lines. A datapath is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks. A plurality of voltage supplies provide the voltages needed in the array and in the peripheral circuits. The power supplies are organized to match their power output to the power demand and to maintain a desired ratio of power production capability and decoupling capacitance. A powerup sequence circuit is provided to control the powerup of the chip. Redundant rows and columns are provided as is the circuitry necessary to logically replace defective rows and columns with operational rows and columns. Circuitry is also provided on chip to support various types of test modes.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention is directed to integrated circuit memory design and, more particularly, to dynamic random access memory (DRAM) designs.

2. Description of the Background

Random access memories (RAMs) are used in a large number of electronic devices from computers to toys. Perhaps the most demanding applications for such devices are computer applications in which high density memory devices are required to operate at high speeds and low power. To meet the needs of varying applications, two basic types of RAM have been developed. The dynamic random access memory (DRAM) is, in its simplest form, a capacitor in combination with a transistor which acts as a switch. The combination is connected across a digitline and a predetermined voltage with a wordline used to control the state of the transistor. The digitline is used to write information to the capacitor or read information from the capacitor when the signal on the wordline renders the transistor conductive.

In contrast, a static random access memory (SRAM) is comprised of a more complicated circuit which may include a latch. The SRAM architecture also uses digitlines for carrying information to and reading information from each individual memory cell and wordlines to carry control signals.

There are a number of design tradeoffs between DRAM and SRAM devices. Dynamic devices must be periodically refreshed or the data stored will be lost. SRAM devices tend to have faster access times than similarly sized DRAM devices. SRAM devices tend to be more expensive than DRAM devices because the simplicity of the DRAM architecture allows for a much higher density memory to be constructed. For those reasons, SRAM devices tend to be used as cache memory whereas DRAM devices tend to be used to provide the bulk of the memory requirements. As a result, there is tremendous pressure on producers of DRAM devices to produce higher density devices in a cost effective manner.

A DRAM chip is a sophisticated device which may be thought of as being comprised of two portions: the array, which is comprised of a plurality of individual memory cells for storing data, and the peripheral devices, which are all of the circuits needed to read information into and out of the array and support the other functions of the chip. The peripheral devices may be further divided into data path elements, address path elements, and all other circuits such as voltage regulators, voltage pumps, redundancy circuits, test logic, etc.

A. The Array

Turning first to the array, the topology of a modern DRAM array1is illustrated in FIG.1. The array1is comprised of a plurality of cells2with each cell constructed in a similar manner. Each cell is comprised of a rectangular active area, which inFIG. 1is a N+ active area. A dotted box3illustrates where one transistor/capacitor pair is fabricated while a dotted box4illustrates where a second transistor/capacitor pair is fabricated. A wordline WL1runs through dotted box3, and at least a portion of where that wordline overlays the N+ active area is where the gate of the transistor is formed. To the left of the wordline WL1in dotted box3, one terminal of the transistor is connected to a storage node5which forms the capacitor. The other terminal of the capacitor is connected to a cell plate. To the right of the wordline WL1, the other terminal of the transistor is connected to a digitline D2at a digitline contact6. The transistor/capacitor pair in dotted box4is a mirror image of the transistor/capacitor pair in dotted box3. The transistor within dotted box4is connected to its own wordline WL2while sharing the digitline contact6with the transistor in the dotted box3.

The wordlines WL1and WL2may be constructed of polysilicon while the digitline may be constructed of polysilicon or metal. The capacitors may be formed with an oxide-nitride-oxide-dielectric between two polysilicon layers. In some processes, the wordline polysilicon is silicided to reduce the resistance which permits longer wordline segments without impacting speed.

The digitline pitch, which is the width of the digitline plus the space between digitlines, dictates the active area pitch and the capacitor pitch. Process engineers adjust the active area width and the resulting field oxide width to maximize transistor drive and minimize transistor-to-transistor leakage. In a similar manner, the wordline pitch dictates the space available for the digitline contact, transistor length, active area length, field poly width, and capacitor length. Each of those features is closely balanced by process engineers to maximize capacitance and yield and to minimize leakage.

B. The Data Path Elements

The data path is divided into the data read path and the data write path. The first element of the data read path, and the last element of the data write path, is the sense amplifier. The sense amplifier is actually a collection of circuits that pitch up to the digitlines of a DRAM array. That is, the physical layout of each circuit within the sense amplifier is constrained by the digitline pitch. For example, the sense amplifiers for a specific digitline pair are generally laid out within the space of four digitlines. One sense amplifier for every four digitlines is commonly referred to as quarter pitch or four pitch.

The circuits typically comprising the sense amplifier include isolation transistors, circuits for digitline equilibration and bias, one or more N-sense amplifiers, one or more P-sense amplifiers, and I/O transistors for connecting the digitlines to the I/O signal lines. Each of those circuits will be discussed.

Isolation transistors provide two functions. First, if the sense amplifiers are positioned between and connected to two arrays, they electrically isolate one of the two arrays. Second, the isolation transistors provide resistance between the sense amplifier and the highly capacitive digitlines, thereby stabilizing the sense amplifier and speeding up the sensing operation. The isolation transistors are responsive to a signal produced by an isolation driver. The isolation driver drives the isolation signal to the supply potential and then drives the signal to a pumped potential which is equal to the value of the charge on the digit lines plus the threshold voltage of the isolation transistors.

The purpose of the equilibration and bias circuits is to ensure that the digitlines are at the proper voltages to enable a read operation to be performed. The N-sense amplifiers and P-sense amplifiers work together to detect the signal voltage appearing on the digitlines in a read operation and to locally drive the digitlines in a write operation. Finally, the I/O transistors allow data to be transferred between digitlines and I/O signal lines.

After data is read from an mbit and latched by the sense amplifier, it propagates through the I/O transistors onto the I/O signal lines and into a DC sense amplifier. The I/O lines are equilibrated and biased to a voltage approaching the peripheral voltage Vcc. The DC sense amplifier is sometimes referred to as the data amplifier or read amplifier. The DC sense amplifier is a high speed, high gain, differential amplifier for amplifying very small read signals appearing on the I/O lines into full CMOS data signals input to an output data buffer. In most designs, the array sense amplifiers have very limited drive capability and are unable to drive the I/O lines quickly. Because the DC sense amplifier has a very high gain, it amplifies even the slightest separation in the I/O lines into full CMOS levels.

The read data path proceeds from the DC sense amplifier to the output buffers either directly or through data read multiplexers (muxes). Data read muxes are commonly used to accommodate multiple part configurations with a single design. For an ×16 part, each output buffer has access to only one data read line pair. For an ×8 part, the eight output buffers each have two pairs of data lines available thereby doubling the quantity of mbits accessible by each output. Similarly, for a ×4 part, the four output buffers have four pairs of datalines available, again doubling the quantity of mbits available for each output.

The final element in the read data path is the output buffer circuit. The output buffer circuit consists of an output latch and an output driver circuit. The output driver circuit typically uses a plurality of transistors to drive an output pad to a predetermined voltage, Vccx or ground, typically indicating a logic level 1 or logic level 0, respectively.

A typical DRAM data path is bidirectional, allowing data to be both read from and written to the array. Some circuits, however, are truly bidirectional, operating the same regardless of the direction of the data. An example of such bidirectional circuits is the sense amplifiers. Most of the circuits, however, are unidirectional, operating on data in only a read operation or a write operation. The DC sense amplifiers, data read muxes, and output buffer circuits are examples of unidirectional circuits. Therefore, to support data flow in both directions, unidirectional circuits must be provided in complementary pairs, one for reading and one for writing. The complementary circuits provided in the data write path are the data input buffers, data write muxes, and write driver circuits.

The data input buffers consist of both nMOS and pMOS transistors, basically forming a pair of cascaded inverters. Data write muxes, like data read muxes, are often used to extend the versatility of a design. While some DRAM designs connect the input buffer directly to the write driver circuits, most architectures place a block of data write muxes between the input buffers and the write drivers. The muxes allow a given DRAM design to support multiple configurations, such as ×4, ×8, and ×16 parts. For ×16 operation, each input buffer is muxed to only one set of data write lines. For ×8 operation, each input buffer is muxed to two sets of data write lines, doubling the quantity of mbits available to each input buffer. For ×4 operation, each input buffer is muxed to four sets of data writelines, again doubling the number of mbits available to the remaining four operable input buffers. As the quantity of input buffers is reduced, the amount of column address space is increased for the remaining buffers.

A given write driver is generally connected to only one set of I/O lines, unless multiple sets of I/O lines are fed by a single write driver via additional muxes. The write driver uses a tri-state output stage to connect to the I/O lines. Tri-state outputs are necessary because the I/O lines are used for both read and write operations. The write driver remains in a high impedance state unless the signal labeled “write” is high, indicating a write operation. The drive transistors are sized large enough to insure a quick, efficient, write operation.

The remaining element of the data write path is, as mentioned, the bidirectional sense amplifier which is connected directly to the array.

C. The Address Path Elements

Up to this point we have been discussing data paths. The movement of data into or out of a particular location within the array is performed under the control of address information. We next turn to a discussion of the address path elements.

Since the 4 Kb generation of DRAMs, DRAMs have used multiplexed addresses. Multiplexing in DRAMs is possible because DRAM operation is sequential. That is, column operations follow row operations. Thus, the column address is not needed until the sense amplifiers for an identified row have latched, and that does not occur until sometime after the wordline has fired. DRAMs operate at higher current levels with multiplexed addressing, because an entire page (row address) is opened with each row access. That disadvantage is overcome by the lower packaging costs associated with multiplexed addresses. Additionally, because of the presence of the column address strobe signal (CAS*), column operation is independent of row operation, enabling a page to remain open for multiple, high-speed, column accesses. That page mode type of operation improves system performance because column access time is much shorter than row access time. Page mode operation appears in more advanced forms, such as extended data out (EDO) and burst EDO (BEDO), providing even better system performance through a reduction in effective column access time.

The address path for a DRAM can be broken into two parts: the row address path and the column address path. The design of each path is dictated by a unique set of requirements. The address path, unlike the data path, is unidirectional. That is, address information flows only into the DRAM. The address path must achieve a high level of performance with minimal power and die area, just like every other aspect of DRAM design. Both paths are designed to minimize propagation delay and maximize DRAM performance.

The row address path encompasses all of the circuits from the address input pad to the wordline driver. Those circuits generally include the row address input buffers, CAS before RAS counter (CBR counter), predecode logic, array buffers, redundancy logic (treated separately hereinbelow), row decoders, and phase drivers.

The row address buffer consists of a standard input buffer and the additional circuits necessary to implement functions required for the row address path. The CBR counter consists of a single inverter and a pair of inverter latches coupled to a pair of complementary muxes to form a one bit counter. All of the CBR counters from each row address buffer are cascaded together to form a CBR ripple counter. By cycling through all possible row address combinations in a minimum of clock pulses, the CBR ripple counter provides a simple means of internally generating refresh addresses.

There are many types of predecode logic used for the row address path. Predecoded address lines may be formed by logically combining (AND) addresses as shown in Table 1.

TABLE 1Predecoded address truth tablePR01RA<0>RA<1>(n)PR01<0>PR01<1>PR01<2>PR01<3>0001000101010001200101130001
The remaining addresses are identically coded except for RA<12>, which is essentially a “don't care”. Advantages to predecoded addresses include lower power due to fewer signals making transitions during address changes and higher efficiency because of the reduced number of transistors necessary to decode addresses. Predecoding is especially beneficial in redundancy circuits. Predecoded addresses are used throughout most DRAM designs today.

Array buffers drive the predecoded address signals into the row decoders. In general, the buffers are no more than cascaded inverters, but in some cases they may include static logic gates or level translators, depending upon the row decoder requirements.

Row decoders must pitch up to the mbit arrays. There are a variety of implementations, but however implemented, the row decoder essentially consists of two elements: a wordline driver and an address decoder tree. With respect to the wordline driver, there are three basic configurations: the NOR driver, the inverter (CMOS) driver, and the bootstrap driver. Just about any type of logic may be used for the address decoder tree. Static logic, dynamic logic such as precharge and evaluate logic, pass gate logic, or some combination thereof may be provided to decode the predecoded address signals. Additionally, the drivers and associated decode trees can be configured either as local row decodes for each array section or as global row decodes that drive a multitude of array sections.

The wordline driver in the row decoder causes the wordline to fire in response to a signal called PHASE. Essentially, the PHASE signal is the final address term to arrive at the wordline driver. Its timing is carefully determined by the control logic. PHASE cannot fire until the row addresses are set up in the decode tree. Normally, the timing of PHASE also includes enough time for the row redundancy circuits to evaluate the current address. The phase driver can be composed of standard static logic gates.

The column address path consists of the input buffers, address transition detection (ATD) circuits, predecode logic, redundancy logic (discussed below), and column decoders. The column address input buffers are similar in construction and operation to the row address input buffers. The ATD circuit detects any transition that occurs on an address pin to which the circuit is dedicated. ATD output signals from all of the column addresses are routed to an equilibration driver circuit. The equilibration driver circuit generates a set of equilibration signals for the DRAM. The first of these signals is Equilibrate I/O (EQIO) which is used in the arrays to force equilibration of the I/O lines. The second signal generated by the equilibration driver is called Equilibrate Sense Amps (EQSA). That signal is generated from address transitions occurring on all of the column addresses, including the least significant address.

The column addresses are fed into predecode logic which is very similar to the row address predecode logic. The address signals emanating from the predecode logic are buffered and distributed throughout the die to feed the column decoders.

The column decoders represent the final elements that must pitch up to the array mbits. Unlike row decoder implementation, though, column decoder implementation is simple and straightforward. Static logic gates may be used for both the decode tree elements and the driver output. Static logic is used primarily because of the nature of column addressing. Unlike row addressing, which occurs once per RAS* cycle with a modest precharge period until the next cycle, column addressing can occur multiple times per RAS* cycle. Each column is held open until a subsequent column appears. In a typical implementation, the address tree consists of combinations of NAND or NOR gates. The column decoder output driver is a simple CMOS inverter.

The row and column addressing scheme impacts the refresh rate for the DRAM. Normally, when refresh rates change for a DRAM, a higher order address is treated as a “don't care” address, thereby decreasing the row address space, but increasing the column address space. For example, a 16 Mb DRAM bonded as a 4 Mb ×4 part could be configured in several refresh rates: 1K, 2K, and 4K. Table 1 below shows how row and column addressing is related to those refresh rates for the 16 Mb example. In this example, the 2K refresh rate would be more popular because it has an equal number of row and column addresses, sometimes referred to as square addressing.

TABLE 2Refresh rate versus row and column addressesRefreshRowColumnRateRowsColumnsAddressesAddresses4K4096102412102K2048204811111K102440961012

D. Other Circuits

Additional circuits are provided to enable various other features. For example, circuits to enable test modes are typically included in DRAM designs to extend test capabilities, speed component testing, or subject a part to conditions that are not seen during normal operation. Two examples are address compression and data compression which are two special test modes usually supported by the design of the data path. Compression test modes yield shorter test times by allowing data from multiple array locations to be tested and compressed on-chip, thereby reducing the effective memory size. The costs of any additional circuitry to implement test modes must be balanced against cost benefits derived from reductions in test time. It is also important that operation in test mode achieve 100% correlation to operation of non-test mode. Correlation is often difficult to achieve, however, because additional circuitry must be activated during compression, modifying the noise and power characteristics on the die.

Additional circuitry is added to the DRAM to provide redundancy. Redundancy has been used in DRAM designs since the 256 Kb generation to improve yield. Redundancy involves the creation of spare rows and columns which can be used as a substitute for normal rows and columns, respectively, which are found to be defective. Additional circuitry is provided to control the physical encoding which enables the substitution of a usable device for a defective device. The importance of redundancy has continued to increase as memory density and size have increased.

The concept of row redundancy involves replacing bad wordlines with good wordlines. The row to be repaired is not physically replaced, but rather it is logically replaced. In essence, whenever a row address is strobed into a DRAM by RAS*, the address is compared to the addresses of known bad rows. If the address comparison produces a match, then a replacement wordline is fired in place of the normal (bad) wordline. The replacement wordline can reside anywhere on the DRAM. Its location is not restricted to the array that contains the normal wordline, although architectural considerations may restrict its range. In general, the redundancy is considered local if the redundant wordline and normal wordline must always be on the same subarray.

Column redundancy is a second type of repair available in most DRAM designs. Recall that column accesses can occur multiple times per RAS* cycle. Each column is held open until a subsequent column appears. Because of that, circuits that are very different from those seen in the row redundancy are used to implement column redundancy.

The DRAM circuit also carries a number of circuits for providing the various voltages used throughout the circuit.

3. Design Considerations

U.S. patent application Ser. No. 08/460,234, entitled Single Deposition Layer Metal Dynamic Random Access Memory, filed 17 Aug. 1995 and assigned to the same assignee as the present invention is directed to a 16 Meg DRAM. U.S. patent application Ser. No. 08/420,943, entitled Dynamic Random Access Memory, filed 4 Jun. 1995 and assigned to the same assignee as the present invention is directed to a 64 Meg DRAM. As will be seen from a comparison of the two aforementioned patent applications, it is not a simple matter to quadruple the size of a DRAM. Quadrupling the size of a 64 Meg DRAM to a 256 Meg DRAM poses a substantial number of problems for the design engineer. For example, to standardize the part so that 256 Meg DRAMs from different manufacturers can be interchanged, a standard pin configuration has been established. The location of the pins places constraints on the design engineer with respect to where circuits may be laid out on the die. Thus, the entire layout of the chip must be reengineered so as to minimize wire runs, eliminate hot spots, simplify the architecture, etc.

Another problem faced by the design engineer in designing a 256 Meg DRAM is the design of the array itself. Using prior art array architectures does not provide sufficient space for all of the components which must pitch up to the array.

Another problem involves the design of the data path. The data path between the cells and the output pads must be as short as possible so as to minimize line lengths to speed up part operation while at the same time present a design which can be manufactured using existing processes and machines.

Another problem faced by the design engineer involves the issue of redundancy. A 256 Meg DRAM requires the fabrication of millions of individual devices, and millions of contacts and vias to enable those devices to be interconnected. With such a large number of components and interconnections, even a very small failure rate results in a certain number of defects per die. Accordingly, it is necessary to design redundancy schemes to compensate for such failures. However, without practical experience in manufacturing the part and learning what failures are likely to occur, it is difficult to predict the type and amount of redundancy which must be provided.

Another problem involves latch-up in the isolation driver circuit when the pumped potential is driven to ground. Latch-up occurs when parasitic components give rise to the establishment of low-resistance paths between the supply potential and ground. A large amount of current flows along the low-resistance paths and device failure may result.

Designing the on-chip test capability also presents problems. Test modes, as opposed to normal operating modest are used to test memory integrated circuits. Because of the limited number of pins available and the large number of components which must be tested, without some type of test compression architecture, the time which each DRAM would have to spend in a test fixture would be so long as to be commercially unreasonable. It is known to use test modes to reduce the amount of time required to test the memory integrated circuit, as well as to ensure that the memory integrated circuit meets or exceeds performance requirements. Putting a memory integrated circuit into a test mode is described in U.S. Pat. No. 5,155,704, entitled “Memory Integrated Circuit Test mode Switching” to Walther et al. However, because the test mode operates internal to the memory, it is difficult to determine whether the memory integrated circuit successfully completed one or more test modes. Therefore, a need exists for providing a solution to verify successful or unsuccessful execution of a test mode. Furthermore, it would be desirable that such a solution have minimal impact with respect to additional circuitry. Certain test modes, such as the all row high test mode, must be rethought with respect to a part as large as a 256 Meg chip because the current required for such a test would destroy power transistors servicing the array.

Providing power for a chip as large as a 256 Meg DRAM also presents its own set of unique problems. Refresh rates may cause the power needed to vary greatly. Providing voltage pumps and generators of sufficient size to provide the necessary power may result in noise and other undesirable side effects when maximum power is not required. Additionally, reconfiguring the DRAM to achieve a usable part in the event of component failure may result in voltage pumps and generators ill sized for the smaller part.

Even something as basic as powering up the device must be rethought in the context of such a large and complicated device as a 256 Meg DRAM. Prior art timing circuits use an RC circuit to wait a predetermined period of time and then blindly bring up the various voltage pumps and generators. Such systems do not receive feedback and, therefore, are not responsive to problems during power up. Also, to work reliably, such systems are conservative in the event some voltage pumps or generators operated more slowly than others. As a result, in most cases, the power up sequence was more time consuming than it needed to be. In a device as complicated as a 256 Meg DRAM, it is necessary to ensure that the device powers up in a manner that permits the device to be properly operated in a minimum amount of time.

All of the foregoing problems are superimposed upon the problems which every memory design engineer faces such as satisfying the parameters set for the memory, e.g., access time, power consumption, etc., while at the same time laying out each and every one of millions of components and interconnections in a manner so as to maximize yield and minimize defects. Thus, the need exists for a 256 Meg DRAM which overcomes the foregoing problems.

SUMMARY OF THE INVENTION

The present invention is directed to a 256 Meg DRAM, although those of ordinary skill in the art will recognize that the circuits and architecture disclosed herein may be used in memory devices of other sizes or even other types of circuits.

The present invention is directed to a memory device comprised of a triple polysilicon, double metal main array of 256 Meg. The main array is divided into four array quadrants each of 64 Meg. Each of the array quadrants is broken up into two 32 Meg array blocks. Thus, there are eight 32 Meg array blocks in total. Each of the 32 Meg array blocks consists of 128 256 k bit subarrays. Thus, there are 1,024 256 k bit subarrays in total. Each 32 Meg array block features sense amp strips with single p-sense amps and boosted wordline voltage Vccp isolation transistors. Local row decode drivers are used for wordline driving and to provide “streets” for dataline routing to the circuits outside of the array. The I/O lines which route through the sense amps extend across two subarray blocks. That permits a 50% reduction in the number of data muxes required in the gap cells. The data muxes are carefully programmed to support the firing of two rows per 32 Meg block without data contention on the data lines. Additionally, the architecture of the present invention routes the redundant wordline enable signal though the sense amp in metal two to ensure quick deselect of the normal row. The normal phase lines are rematched to appropriate redundant wordline drivers for efficient reuse of signals.

Also, the data paths for reading information into and writing information out of the array have been designed to minimize the length of the data path and increase overall operational speed. In particular, the output buffers in the read data path include a self-timed path to ensure that the holding transistor connected between the boosted voltage Vccp and a boot capacitor is turned off before the boot capacitor is unbooted. That modification ensures that charge is not removed from the Vccp source when turning off a logic “1” level.

The power busing scheme of the present invention is based upon central distribution of voltages from the pads area. On-chip voltage supplies are distributed throughout the center pads area for generation of both peripheral power and array power. The array voltage is generated in the center of the design for distribution to the arrays from a central web. Bias and boosted voltages are generated on either side of the regulator producing the array voltage for distribution throughout the tier logic. The web surrounds each 32 Meg array block for efficient, low-resistant distribution. The 32 Meg arrays feature fully gridded power distribution for better IR and electromigration performance.

Redundancy schemes have been built into the design of the present invention to enable global as well as local repair.

The present invention includes a method and apparatus for providing contemporaneously generated (status) information or programmed information. In particular, address information may be used as a test key. A detect circuit, in electrical communication with decoding circuits, receives an enable signal which activates the detection of a non-standard or access voltage. By non-standard or access voltage it is meant that a voltage outside of the logic level range (e.g., transistor-transistor logic) is used for test logic. The decoding circuit uses the address information as a vector to access a selected type or types of information. With such a vector, a bank, having information stored therein, may be selected from a plurality of banks, and a bit or bits within the selected bank may be accessed. Depending on the test mode selected, either programmed information or status information will be accessed. The decoding circuits and the detect circuit are in electrical communication with a select circuit for selecting between test mode operation and standard memory operation (e.g., a memory read operation).

The power and voltage requirements of a 256 Meg DRAM prevent entering the all row high test in the manner used in other, smaller DRAMs. To reduce the current requirements, in the present invention only subsets of the rows are brought high at a time. The timing of those subsets of rows is handled by cycling CAS. The CAS before RAS (CBR) counter, or another counter, may be used to determine which subset of rows is brought high on each CAS cycle. Various test compression features are also designed into the architecture.

The present invention also includes a powerup sequence circuit to ensure that a powerup sequence occurs in the right order. Inputs to the sequence circuit are the current levels of the voltage pumps, the voltage generator, the voltage regulator, and other circuitry important to correctly powerup the part. The logic to control the sequence circuit may be constructed using analog circuitry and level detectors to ensure a predictable response at low voltages. The circuitry may also handle power glitches both during and after initial powerup.

The 32 Meg array blocks comprising the main array can each be shut down if the quantity of failures or the extent of the failures exceed the array block's repair capability. That shutdown is both logical and physical. The physical shutdown includes removing power such as the peripheral voltage Vcc, the digitline bias voltage DVC2, and the wordline bias voltage Vccp. The switches which disconnect power from the block must, in some designs, be placed ahead of the decoupling capacitors for that block. Therefore, the total amount of decoupling capacitance available on the die is reduced with each array block that is disabled. Because the voltage regulator's stability can in large part be dependant upon the amount of decoupling capacitance available, it is important that as 32 Meg array blocks are disabled, a corresponding voltage regulator section be similarly disabled. The voltage regulator of the present invention has a total of twelve power amplifiers. For eight of the twelve, one of the eight is associated with one of the eight array blocks. The four remaining power amplifiers are associated with decoupling capacitors not effected by the array switches. Furthermore, because the total load current is reduced with each 32 Meg array block that is disconnected, the need for the additional power amplifiers is also reduced.

The present invention also incorporates address remapping to ensure contiguous address space for the partial die. That design realizes a partial array by reducing the address space rather than eliminating DQs.

The present invention also includes a unique on-chip voltage regulator. The power amplifiers of the voltage regulator have a closed loop gain of 1.5. Each amplifier has a boost circuit which increases the amplifier's slew rate by increasing the differential pair bias current. The design includes additional amplifiers that are specialized to operate when the pumps fire and a very low Icc standby amplifier. The design allows for multiple refresh operations by enabling additional amplifiers as needed.

The present invention also includes a tri-region voltage reference which utilizes a current related to the externally supplied voltage Vccx in conjunction with an adjustable (trimmable) pseudo diode stack to generate a stable low voltage reference.

The present invention also includes a unique design of a Vccp voltage pump which is configurable for various refresh options. The 256 Meg chip requires 6.5 mA of Iccp current in the 8 k refresh mode and over 12.8 mA in the 4 k refresh mode. That much variation in load current is best managed by bringing more pump sections into operation for the 4 k refresh mode. Accordingly, the design of the Vccp voltage pump of the present invention uses three pump circuits for 8 k and six pump circuits for 4 k refresh mode. The use of six pump circuits for the 8 k mode is unacceptable from a noise standpoint and actually produces excessive Vccp ripple when the pumps are so lightly loaded.

The present invention also includes a unique DVC2cellplate/digitline bias generator with an output status sensor. The powerup sequence circuit previously described requires that each power supply be monitored as to its status when powering up. The DVC2generator constructed according to the teachings of the present invention allows its status to be determined through the use of both voltage and current sensing. The voltage sensing is a window detector which determines if the output voltage is one Vt above ground Vss and one Vt below the array voltage Vcca. The current sensing is based upon measuring changes in the output current as a function of time. If the output current reaches a stable steady state level, the current sensor indicates a steady state condition. Additionally, a DC current monitor is present which determines if the steady state current exceeds a preset threshold. The output of the DC current monitor can either be used in the powerup sequence or to identify row to column or cellplate to digitline shorts in the arrays. Following completion of the powerup sequence, the sensor output status is disabled.

The present invention also includes devices to support partial array power down of the isolation driver circuit. The devices ensure that no current paths are produced when the voltage Vccp, which is used to control the isolation transistors, is driven to ground and, thus, latch-up is avoided. Also, the devices ensure that all components in the isolation driver that are connected to the voltage Vccp are disabled when the driver is disabled.

The architecture and circuits of the present invention represent a substantial advance over the art. For example, the array architecture represents an improvement for several reasons. One, the data is routed directly to the peripheral circuits which shortens the data path and speeds part operation. Second, doubling the I/O line length simplifies gap cell layout and provides the framework for 4 k operation, i.e., two rows of the 32 Meg block. Third, sending the Red signal through the sense amps provides for faster operation, and when combined with PHASE signal remapping, a more efficient design is achieved.

The improved output buffer used in the data path of the present invention lowers Iccp current when the buffer turns off a logic “1” level.

The unique power busing layout of the present invention efficiently uses die size. Central distribution of array power is well suited to the 256 Meg DRAM design. Alternatives in which regulators are spread around the die require that the external voltage Vccx be routed extensively around the die. That results in inefficiencies and requires a larger die.

Other advantages that flow from the architecture and circuits of the present invention include the following. The generation of status information allows us to confirm that the port is still in the desired test mode at the end of a test mode cycle and allows us to check every possible test mode. Combining this with fuse ID information reduces the area penalty. During the all row high test mode, the timing of the rows can be controlled better using the CAS cycle. Also, the number of row subsets that can be brought high can be greater than four. The powerup sequence circuit provides for more foolproof operation of the DRAM. The powerup sequence circuit also handles power glitches both during powerup and during normal operation. The disabling of 32 Meg array blocks together with their corresponding voltage regulator section, while maintaining a proper ratio of output stages to decoupling capacitance, ensures voltage regulator stability despite changes in part configuration stemming from partial array implementation. The on-chip voltage regulator provides low standby current, improved operating characteristics over the entire operating range, and better flexibility. The adjustable, tri-region voltage reference produces a voltage in a manner that ensures that the output amplifiers (which have gain) will operate linearly over the entire voltage range. Furthermore, moving the gain to the output amplifiers improves common mode range and overall voltage characteristics. Also, the use of pMOS diodes creates the desired burn-in characteristics. The variable capacity voltage pump circuit, in which capacity is brought on line only when needed, keeps operating current to the level needed depending upon the refresh mode, and also lowers noise level in the 8 k refresh mode. The cellplate/digitline bias generator allows the determination of the DVC2status in support of the powerup sequence circuit. Those advantages and benefits of the present invention, and others, will become apparent from the Description of the Preferred Embodiments hereinbelow.

MICROFICHE APPENDIX

Reference is hereby made to an appendix which contains eleven microfiche having a total of sixty-six frames. The appendix contains 44 drawings which illustrate substantially the same information as is shown inFIGS. 1-113, but in a more connected format.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

For convenience, this Description of the Preferred Embodiments is divided into the following sections:I. IntroductionII. 256 Meg DRAM ArchitectureIII. Array ArchitectureIV. Data and Test PathsV. Product Configuration and Exemplary Design SpecificationsVI. Bus ArchitectureVII. Voltage SuppliesVIII. Center LogicIX. Global Sense Amp DriversX. Right and Left LogicXI. Miscellaneous FiguresXII. Conclusion
I. Introduction

In the following description, various aspects of the disclosed memory device are depicted in different figures, and often the same component is depicted in different ways and/or different levels of detail in different figures for the purposes of describing various aspects of the present invention. It is to be understood, however, that any component depicted in more than one figure retains the same reference numeral in each.

Regarding the nomenclature to be used herein, throughout this specification and in the figures, “CA<x>” and “RA<y>” are to be understood as representing bit x of a given column address and bit y of a given row address, respectively. References to DLa<0>, DLb<0>, DLc<0>, and DLd<0> will be understood to represent the least significant bit of an n bit byte coming from four distinct memory locations.

It is to be understood that the various signal line designations are used consistently in the figures, such that the same signal line designation (e.g., “Vcc”, “CAS,” etc . . . ) appearing in two or more figures is to be interpreted as indicating a connection between the lines that they designate in those figures, in accordance with conventional practice relating to schematic, wiring, and/or block diagrams. Finally, a signal having an asterisk indicates that that signal is the logical complement of the signal having the same designation but without the asterisk, e.g., CMAT* is the logical complement of the column match signal CMAT.

There are a number of voltages used through the DRAM of the present invention. The production of those voltages is described in detail in Section VII—Supply Voltages. However, the voltages appear throughout the figures and in some instances are discussed in conjunction with the operation of specific circuits prior to Section VII. Therefore, to minimize confusion, the various voltages will now be introduced and defined.

Vccx—externally supplied voltage

Vccq—power for the data output pad drivers

Vccp—boosted version of Vcc used for biasing the wordlines (produced by the Vccp pump400shown inFIG. 39)

Vssq—ground for the data output pad drivers

DVC2—one half of Vcc used for biasing the digitlines (produced by the DVC2generators500-507shown inFIG. 41)

AVC2—one half of Vcc used as the cellplate voltage (has the same value as DVC2)

The prefix “map” before a voltage or signal indicates that the voltage or signal is switched, i.e., it can be turned on or off.

Certain of the components and/or signals identified in the description of the preferred embodiment are known in the industry by other names. For example, the conductors in the array which are referred to in the Description of the Preferred Embodiments as digitlines are sometimes referred to in the industry as bitlines. The term “column” actually refers to two conductors which comprise the column. Another example is the conductor which is referred to herein as a rowline. That conductor is also known in the industry as a wordline. Those of ordinary skill in the art will recognize that the terminology used herein is used for purposes of explaining exemplary embodiments of the present invention and not for limiting the same. Terms used in this document are intended to include the other names by which signals or parts are commonly known in the industry.

FIG. 2is a high level block diagram illustrating a 256 Meg DRAM10constructed according to the teachings of present invention. Although the following description is specific to this presently preferred embodiment of the invention, it is to be understood that the architecture and circuits of the present invention may be advantageously applied to semiconductor memories of different sizes, both larger and smaller in capacity. Additionally, certain circuits disclosed herein, such as the powerup sequence circuit, voltage pumps, etc. may find uses in circuits other than memory devices.

InFIG. 2, the chip10is comprised of a main memory12. Main memory12is comprised of four equally sized array quadrants numbered consecutively, beginning with array quadrant14in the upper right hand corner, array quadrant15in the bottom right hand corner, array quadrant16in the bottom left hand corner, and array quadrant17in the upper left hand corner. Between array quadrant14and array quadrant15is situated right logic19. Between the array quadrant16and the array quadrant17is situated left logic21. Between the right logic19and the left logic21is situated center logic23. The center logic23is discussed in greater detail hereinbelow in Section VIII. The right and left logic19and21, respectively, are described in greater detail hereinbelow in Section X.

The array quadrant14is illustrated in greater detail inFIGS. 3A-3E. Each of the other array quadrants15,16,17, is identical in construction and operation to the array quadrant14. Therefore, only the array quadrant14will be described in detail.

It is seen fromFIG. 3Athat the left 32 Meg array25can be physically disconnected from the various voltage supplies that supply voltage to the array25by controlling the condition of switches48. The switches48control the application of the switched array voltage (mapVcca), the switched, boosted, array voltage (mapVccp), (the switch48associated with mapVccp is not shown in the figure), the switched digitline bias voltage (mapDVC2), and the switched, cellplate bias voltage (mapAVC2). The 32 Meg array25also includes one or more decoupling capacitors44. The purpose of the decoupling capacitors is to provide a capacitive load for the voltage supplies as will be described hereinbelow in greater detail in Section VII. For now, it is sufficient to note the that the decoupling capacitor44is located on the opposite side of the switch from the voltage supplies. The right 32 Meg array27, and all the other 32 Meg arrays31,33,38,40,45, and47are similarly provided with decoupling capacitors44and switched versions of the array voltage, boosted array voltage, digitline bias voltage, and cellplate bias voltage.

III. Array Architecture

FIG. 4is a block diagram of the 32 Meg array block25which illustrates an 8×16 array of individual arrays50, each 256 k, which make up the 32 Meg array block25. Between each row of individual arrays50are positioned sense amplifiers52. Between each column of individual arrays50are positioned row decoders54. In the gaps, multiplexers55are positioned. The portion of the figure shaded inFIG. 4is illustrated in greater detail in FIG.5.

InFIG. 5, one of the individual arrays50is illustrated. The individual array50is serviced by a left row decoder56and a right row decoder58. The individual array50is also serviced by a “top” N-P sense amplifier60and a “bottom” N-P sense amplifier62. A top sense amp driver64and a bottom sense amp driver66are also provided.

Between the individual array50and the N-P sense amp60are a plurality of digit lines, two of which68,68′ and,69,69′ are shown. As is known in the art, the digitlines extend through the array50and into the sense amp60. The digitlines are a pair of lines with one of the lines carrying a signal and the other line carrying the complement of the signal. It is the function of the N-P sense amp60to sense a difference between the two lines. The sense amplifier60also services the 256 k array located above the array50, which is not shown inFIG. 5, via a plurality of digitlines, two of which,70,70′ and77,71′, are shown. The upper N-P sense amp60places the signals sensed on the various digitlines onto I/O lines72,72′,74,74′. (Like the digitlines, the I/O lines designated with a prime carry the complement of the signal carried by the I/O line bearing the same reference number but without the prime designation.) The I/O lines run through multiplexers76,78(also referred to as muxes). The mux76takes the data on the I/O lines72,72′,74,74′ and places the data on datalines. Datalines79,79′,80,80′,81,81′,82,82′ are responsive to mux76. (The same designation scheme used for the I/O lines applies to the datalines, e.g., dataline79′ carries the complement of the signal carried on dataline79.)

In a similar fashion, N-P sense amp62senses signals on the digitlines represented generally by reference numbers86,87and places signals on I/O lines represented generally by reference No.88which are then input to multiplexers90and92. The multiplexer90, like the multiplexer76, places signals on the datalines79,79′,80,80′,81,81′,82,82′.

The 256 k individual array50illustrated in the block diagram ofFIG. 5is illustrated in detail in FIG.6A. The individual array50is comprised of a plurality of individual cells which may be as described hereinabove in conjunction with FIG.1. The individual array50may include a twist, represented generally by reference number84, as is well known in the art. Twisting improves the signal-to-noise characteristics. There are a variety of twisting schemes used in the industry, e.g., single standard, triple standard, complex, etc., any of which may be used for the twist84illustrated in FIG.6A. (The reader seeking more detail regarding the construction of the array50is directed toFIG. 97which is a topological view of the array50, and the description associated therewith, andFIG. 98, which is a view of a cell, and the description associated therewith.)

FIG. 6Billustrates the row decoder56illustrated in FIG.5. The purpose of the row decoder56is to fire one of the wordlines within individual array50which is identified in address information received by the chip10. The use of local row decoders enables sending the full address and eliminates a metal layer. Those of ordinary skill in the art will understand the operation of the row decoder56from an examination of FIG.6B. However, it is important to note that the RED (redundant) line runs through the sense amp60in metal2, and is input to an lph driver circuit96and a redundant wordline driver circuit97in row decoder56for the purpose of turning off the normal wordline and turning on the redundant wordline.

FIG. 6Cillustrates the sense amplifier60shown inFIG. 5in detail. The purpose of the sense amplifier60is to sense the difference between, for example, digitline68,68′ to determine if the storage element whose wordline is fired and that is connected to digitline68,68′ has a logic “1” or a logic “0” stored therein. In the design illustrated inFIG. 6C, the sense amps are located inside isolation transistors83. It is necessary to gate the isolation transistors83with a sufficiently high voltage to enable the isolation transistors83to conduct a full Vcc to enable a write of a full “one” into the device. It is, thus, necessary to gate the transistors83high enough to pass the voltage Vcc and not the voltage Vcc-Vth. Therefore, the boosted voltage Vccp is used to gate the isolation transistors83. The operation of the sense amplifier60will be understood by those of ordinary skill in the art from an examination of FIG.6C.

FIG. 6Dillustrates the array multiplexer78and the sense amp driver64shown inFIG. 5in detail. As previously mentioned, the purpose of the multiplexer78is to determine which signals available on the array's I/O lines are to be placed on the array's datalines. That may be accomplished by programming the switches in the area generally designated63. Such “softswitching” allows for different types of mapping without requiring hardware changes. The sense amp driver64provides known control signals, e.g.. ACT, ISO, LEQ, etc., to N-P sense amplifier60. From the schematic illustrated inFIG. 6D, the construction and operation of the array multiplexer78and sense amp driver64will be understood.

IV. Data and Test Paths

The data read path begins, of course, in an individual storage element within one of the 256 k arrays. The data in that element is sensed by an N-P sense amplifier, such as sense amplifier60in FIG.6C. Through proper operation of the I/O switches85within N-P sense amplifier60, that data is then placed on I/O lines72,72′,74,74′. Once on the I/O lines, the data's “journey” to the output pads of the chip10begins.

Turning now toFIG. 7, the 32 Meg array25shown inFIG. 4is illustrated. InFIG. 7, the 8×16 array of 256 k individual arrays50is again illustrated. The lines running vertically inFIG. 7between the columns of arrays50are data lines. Recall fromFIG. 5that the row decoders are also positioned between the columns of individual arrays50. InFIG. 6B, the detail is illustrated as to how the datalines route through the row decoders. In that manner, the row decoders are used for wordline driving as is known in the art, and to provide “streets” for dataline routing to the peripheral circuits.

Returning toFIG. 7, the lines running horizontally between rows of individual arrays50are the I/O lines. The I/O lines must route through the sense amplifiers, as shown inFIG. 6C, because the sense amplifiers are also located in the space between the rows of arrays50. Recall that it is the function of the multiplexers as described hereinabove in conjunction withFIG. 5to take signals from the I/O lines and place them on the datalines. The positioning of the multiplexers within the array25is illustrated in FIG.7. InFIG. 7, nodes94indicate the positioning of a multiplexer of the type shown inFIG. 6Dat an intersection of the I/O lines with the datalines. As will be appreciated from an examination ofFIG. 7, the I/O lines, which route through the sense amplifiers, extend across two arrays50before being input to a multiplexer. That architecture permits a 50% reduction in the number of data muxes required in the gap cells. The data muxes are carefully programmed to support the firing of only two rows, separated by a predetermined number of arrays, per 32 Meg block without data contention on the datalines. For example, rows may be fired in arrays0and8,1and9, etc. Both fire and repairs are done on the same associated groups. Additionally, as previously mentioned, the architecture of the present invention routes the redundant wordline enable signal (shown inFIG. 6B) through the sense amp strip in metal2to ensure quick deselection of the normal row. Finally, normal phase lines are remapped, as shown inFIG. 61, to appropriate redundant wordline drivers for efficient reuse of signals.

The architecture illustrated inFIG. 7is, of course, repeated in the other 32 Meg array blocks27,31,33,38,40,45,47. Use of the architecture illustrated inFIG. 7allows the data to be routed directly to the peripheral circuits which shortens the data path and speeds part operation. Second, doubling the I/O line length by appropriately positioning the multiplexers simplifies the gap cell layout and provides a convenient framework for 4 k operation, i.e., two rows per 32 Meg block. Third, sending the RED signal through the sense amp is faster when combined with the phase signal remapping discussed above.

After the data has been transferred from the I/O lines to the data lines, that data is next input to an array I/O block100as shown in FIG.8. The array I/O block100services the array quadrant14illustrated in FIG.2. In a similar fashion, an array I/O block102services array quadrant15; an array I/O block104services array quadrant16; an array I/O block services array quadrant17. Thus, each of the array I/O blocks100,102,104,106serves as the interface between the 32 Meg array blocks in each of the quadrants and the remainder of the data path illustrated in FIG.8.

InFIG. 8, after the array I/O blocks, the next element in the data read path is a data read mux108. The data read mux108determines the data to be input to an output data buffer110in response to control signals produced by a data read mux control circuit112. The output data buffer110outputs the data to a data pad driver114in response to a data out control circuit116. The data pad driver114drives a data pad to either Vccq or Vssq to represent a logic level “1” or a logic level “0”, respectively, on the output pad.

With respect to the write data path, that data path includes a data in buffer118under the control of a data in buffer control circuit120. Data in the data in buffer118is input to a data write mux122which is under the control of a data write mux control circuit124. From the data write mux122, the input data is input to the array I/O blocks100,102,104,106and ultimately written into array quadrants14,15,16,17, respectively, according to address information received by chip10.

The data test path is comprised of a data test block126and a data path test block128connected between the array I/O blocks100,102,104,106and the data read mux108.

Completing the description of the block diagram ofFIG. 8, a data read bus bias circuit130, a DC sense amp control circuit132, and a data test DC enable circuit134are also provided. The circuits130,132, and134provide control and other signals to the various blocks illustrated in FIG.8. Each of the blocks illustrated inFIG. 8will now be described in more detail.

One of the array blocks100is illustrated in block diagram form in FIG.9and as a wiring schematic inFIGS. 10A-10D. The I/O block100is comprised of a plurality of data select blocks136. An electrical schematic of one type of data select block136that may be used is illustrated in FIG.11. InFIG. 11, the EQIO line is fired when the columns are to be charged or for a write recovery. When the two transistors137and138are conductive, the voltage on the lines LIOA and LIOA* are clamped to one Vth below Vcc.

Returning toFIG. 9, the I/O block100is also comprised of a plurality of data blocks140and data test comp circuits141. The data test comp circuits141are described hereinbelow in conjunction withFIG. 25. Atype of data block140that may be used is shown in detail in the electrical schematics ofFIGS. 12A and 12B. The data blocks140may contain, for example, a write driver142illustrated inFIG. 12A, and a DC sense amp143illustrated in FIG.12B. The write driver142is part of the write data path while the DC sense amp143is part of the data read path.

The write driver142, as the name implies, writes data into specific memory locations. The write driver142is connected to only one set of I/O lines, although multiple sets of I/O lines may be fed by a single write driver circuit via muxes. The write driver142uses a tri-state output stage to connect to the I/O lines. Tri-state outputs are necessary because the I/O lines are used for both read and write operations. The write driver142remains in a high impedance state unless the signal labeled WRITE is high, indicating a write operation. As shown inFIG. 12A, the write driver142is controlled by specific column addresses, the WRITE signal, and Data Write (DW) Signal.

The write driver142also receives topinv and topinv*. The purpose of the topo signals is to ensure that a logical one is written when a logical one is input to the part. The topo decoder circuit, which produces the topo signals, knows what m-bits are connected to the digit and digit* lines. The topo decoder circuit is illustrated in FIG.95. Each array I/O block gets four topo signals.

The drive transistors are sized large enough to ensure a quick, efficient, write operation, which is important because the array sense amplifiers usually remain on during a write cycle. The signals placed on the IOA, IOA* lines inFIG. 12Aare the signals (LIOA, LIOA*) input to the data select block136as illustrated in the upper left hand corner of FIG.11.

The DC sense amplifier143illustrated inFIG. 12Bis sometimes referred to as a data amplifier or read amplifier. Such an amplifier is an important component even though it may take a variety of configurations. The purpose of the DC sense amp143is to provide a high speed, high gain, differential amplifier for amplifying very small read signals appearing on the I/O lines into full CMOS data signals used in the data read mux108. In most designs, the I/O lines connected to the sense amplifiers are very capacitive. The array sense amplifiers have very limited drive capability and are unable to drive those lines quickly. Because the DC sense amp has a very high gain, it amplifies even the slightest separation of the I/O lines into full CMOS levels, essentially gaining back any delay associated with the I/O lines. The illustrated sense amp is capable of outputting full rail-to-rail signals with input signals as small as 15 mV.

As illustrated inFIG. 12B, the DC sense amp143consists of four differential pair amplifiers and self biasing CMOS stages144,144′,145,145′. The differential pairs are configured as two sets of balanced amplifiers. The amplifiers are built with an nMOS differential pair using pMOS active loads and nMOS current mirrors. Because the nMOS transistors have higher mobility providing for smaller transistors and lower parasitic loads, nMOS amplifiers usually provide faster operation than pMOS amplifiers. Furthermore, Vth matching is usually better for nMOS transistors providing for a more balanced design. The first set of amplifiers is fed with the signals from the I/O lines from the array (IOA*, IOA) while the second set of amplifiers is fed with output signals from the first pair labeled DAX, DAX*. Bias levels into each stage are carefully controlled to provide optimum performance.

The outputs from the second stage, labeled DAY, feed into self biasing CMOS inverter stages147,147′ which provide for fast operation. The final output stage is capable of tri-state operation to allow multiple sets of DC sense amps to drive a given set of data read lines (DR <n> and DR* <n>). The entire DC sense amplifier143is equilibrated prior to operation, including the self-biasing CMOS inverter stages147,147′, by the signals labeled EQSA, EQSA*, and EQSA2. Equilibration is necessary to ensure that the DC sense amplifier143is electrically balanced and properly biased before the input signals are applied. The DC sense amplifier143is enabled whenever the enable sense amp signal ENSA* is brought low, turning on the output stage and the current mirror bias circuit148(seen in FIG.12A), which is connected to the differential amplifiers via the signal labeled CM.

InFIG. 12B, the production of the signals DRT and DRT* is shown in the left-hand portion of the figure. The signals DRT and DRT* are used for data compression testing and cause the normal data path to be bypassed.

The data block140requires a number of control signals to ensure proper operation. Those signals are generated by the DC sense amp control circuit132illustrated in FIG.8. The details of the DC sense amp control circuit132are shown in the electrical schematics ofFIGS. 13A and 13B. InFIGS. 13A and 13B, a number of signals are received which, through the proper combination of logic gates as shown in the figure, are combined to produce the necessary control signals for the data block140. It is seen inFIG. 13Athat the DC sense amp control circuit132includes a mux decode A circuit150and a mux decode B circuit151. Electrical schematics of one type of such circuits which may be utilized are provided inFIGS. 14 and 15, respectively. Mux decode A circuit150and mux decode B circuit151use row addresses to determine which datalines from the array will be used for read/write access in each array block. Thus, the mux decode A circuit150and the mux decode B circuit151produce signals for controlling the muxes found within the array IO blocks100,102,104, and106.

The purpose of the data blocks140when in the read mode is to place data coming from the data select blocks136from the data lines coming out of the array onto the lines which feed into the data read mux108of FIG.8. The data read mux108is illustrated in detail inFIGS. 16A,16B, and16C. The purpose of the data read muxes is to provide more part flexibility by enabling data output buffer110to be responsive to more data. For example, for ×16 operation, each output buffer110has access to only one data read (DR) line pair. For ×8 operation, the eight output buffers110each have two pairs of data read lines available, doubling the quantity of mbits accessible by each output buffer. Similarly, for ×4 operation, the four output buffers have four pairs of data read lines available, again doubling the quantity of mbits available for each output. For those configurations with multiple pairs available, address lines control which data read line pair is connected to a data buffer.

The data read mux108receives control signals from data read mux control circuit112, an electrical schematic of one type being illustrated in FIG.17. The purpose of the data read mux control circuit112is to produce control signals to enable data read mux108to operate so as to select the appropriate data signals for output to data buffer110. Note inFIG. 17the change in signal notation from DR for the input signals to LDQ for the output signals of the Mux108.

An electrical schematic of data buffer110is provided in FIG.18. The control signals used to control the operation of the data output buffer110are generated by the data output control circuit116, an electrical schematic of which is illustrated in FIG.19. The data output control circuit116is one type which may be employed; other types of control circuits may be used.

Returning toFIG. 18, the data output buffer110is comprised of a latch circuit160for receiving data which is to be output. The latch circuit160frees the DC sense amp143and other circuits upstream to get subsequent data for output. The input to the latch is connected to the LQD, LQD* signals coming from the data read mux108. Latch circuits160appear in a variety of forms, each serving the needs of a specific application or architecture. The data path may, of course, contain additional latches in support of special modes of operation, such as burst mode.

A logic circuit162is responsive to the latch160for controlling the condition, conductive or nonconductive, of a plurality of drive transistors in a drive transistor section164. By proper operation of the drive transistors in drive transistor section164, a pullup terminal167can be pulled up to the voltage Vcc and a pulldown terminal183can be pulled down to ground. The signals PUP and PDN available at terminals167and183, respectively, are used to control the data pad driver114shown in FIG.20. If both the PUP terminal and the PDN terminal are pulled low, a tri-state or high impedance condition results.

To ensure sufficient voltage is available at the gate of the output drive transistor responsible for pulling the PUP terminal up, a boot capacitor168is used. To charge the boot capacitor168and also to avoid the effects of inherent leakage, the capacitor168is held at its booted up or fully charged level by a holding transistor170. The holding transistor is connected to the boosted voltage Vccp, which is greater than the voltage Vcc, and which may be developed by a voltage pump of the type described hereinbelow. Upon a change of state, the boot capacitor168is unbooted. In prior art circuits, because of transient effects, the holding transistor170was prone to continue to conduct and draw power from the voltage pump although the boot capacitor was unbooted, or in the process of being unbooted. That condition is undesirable, and this aspect of the present invention addresses and solves that problem by providing a self-timed path172. The self-timed path ensures the boot capacitor168is not unbooted until the holding transistor170is completely off.

The self-timed circuit path172is connected between the gate of transistor170and the low side of the boot capacitor168. The path172is comprised of an inverter174having its input terminal connected to the gate of the transistor170and having its output terminal connected to one of the input terminals of a NAND gate176. In that manner, the gate potential of the holding transistor170is continually monitored and fed into the NAND gate176. An output terminal of the NAND gate176is connected to the low side of the boot capacitor168. The path172is referred to as being self-timed because it operates directly in response to the condition of the transistor170rather than relying upon some arbitrary time delay.

A second input terminal of the NAND gate176is connected to an output terminal of an inverter178. The inverter178is part of the logic circuit162and is in the path between the latch160and the gate terminal of a PUP transistor166. The inverter178directly controls the state of PUP transistor166and, therefore, the state of the terminal167. The PUP transistor166may be a pMOS transistor with the voltage of the boot capacitor being used to ensure that the voltage output is sufficient to drive the transistor in the data pad driver114. When the holding transistor170is on, a logic “1” is input to the inverter174causing a logic “0” to appear at the first input terminal of the NAND gate176. With a logic “0” at the first input terminal, the signal available at the output terminal is high and the signal available at the second input terminal does not matter.

When the signal available at an output terminal of the inverter178goes high thereby shutting off PUP transistor166, a logic “1” is input to the second input terminal of NAND gate176. That logic “1” also propagates through the circuitry illustrated in the upper portion of FIG.18and becomes a logic “0” which turns off transistor170. The logic “0” which turns off transistor170is input to inverter174such that a logic “1” is input to the first input terminal of NAND gate176. With the input signals at both input terminals now high, the signal available at the output terminal of the NAND gate176goes low allowing the capacitor168to unboot.

A string of transistors190,192,194,196, and198act as a buffer clamp circuit for limiting the maximum voltage on boot capacitor168. A transistor199is connected to the peripheral voltage Vcc for precharging the boot capacitor168prior to the operation of holding transistor170and the application of the boosted voltage Vccp. An optional feature illustrated inFIG. 18is that the pullup terminal167may be additionally regulated through a switch180so that a PUP pulldown transistor182is subject to self-timing according to the state of the signal at the bottom of the boot capacitor168.

The terminal167, a terminal181, and the terminal183are electrically connected to the data pad driver114, an electrical schematic of which is illustrated in FIG.20. The data pad driver114drives a data output/data input pad DQn. The data output/data input pad DQn represents the end of the data output path.

A data read bus bias circuit130is illustrated in detail in FIG.21. The purpose of the data read bus bias circuit130is to keep the DR lines from floating when not in use. When the EQSA* signal disables the sense amps, the circuit130monitors that condition and holds the DR lines at a predetermined voltage.

The data write path begins at an input/output pad and continues with the data in buffer118which is under control of the data in buffer enable control circuit120which are both illustrated in FIG.22. The buffer118is comprised primarily of a latch as shown in the figure. For a DRAM that is 8 bits wide (×8), there will be eight input buffers, each driving into one or more write drivers through a signal labeled DW <n> (Data Write where n corresponds to the specific data bit0-15). The data in buffer enable control circuit120produces control signals according to the type of part.

In the present invention, the data write mux122, illustrated inFIG. 23, is provided. While some DRAM designs connect the input buffer directly to the write driver circuits, a block of data write muxes between the input buffers and the write drivers allows the DRAM design to support multiple configurations such as ×4, ×8, and ×16. As shown inFIG. 23, the muxes are programmed according to the bond option control signals labeled OPT×4, OPT×8, and OPT×16. For ×16 operation, each input buffer110is muxed to only one set of DW lines. For ×8 operation, each input buffer is muxed to two sets of DW lines, essentially doubling the quantity of mbits available to each input buffer. For ×4 operation, each input buffer is muxed to four sets of DW lines, again doubling the number of mbits available to the remaining four operable input buffers. Essentially, as the quantity of input buffers is reduced, the amount of column address space is increased for the remaining buffers.

The data write mux122is under the control of the data write mux control circuit124which is illustrated in detail in FIG.24. InFIGS. 23 and 24, note the change in notation between the signals input to the data write mux122(DIN) and the signals output from data write mux122(DW).

From the data write mux122, the data to be written is input to the write driver142within data block140, described hereinabove in conjunction withFIG. 12A, where the DW signal is input in the upper left hand corner of FIG.12A. The write driver142places the data to be written on the I/O lines which allow the signals to work their way back into the array through the sense amplifiers.

Now that the data read and data write paths have been described, our attention will now turn to compression issues. Address compression and data compression are two special test modes supported by the test path design. DRAM designs include test paths to extend test capabilities, speed component testing, or subject a part to conditions that are not seen during normal operation. Compression test modes yield shorter test times by allowing data from multiple array locations to be tested and compressed on chip, thereby reducing the effective memory size by a factor of 128 or more in some cases. Address compression usually on the order of 4× to 32×, is accomplished by internally treating certain address bits as “don't care” addresses. The data from all of the don't care address locations, which correspond to specific DQ pins, are compared together with special match circuits. Match circuits are usually realized with NAND and NOR logic gates. The match circuits determine if the data from each address location is the same, reporting the result on the respective DQ pin as a match or a fail. The data path must be designed to support the desired level of data compression. That may necessitate more DC sense amp circuits, logic, and other pathways than those necessary for normal operation.

The second form of test compression is data compression, i.e., combining data upstream of the output drivers. Data compression usually reduces the number of DQ pins to four, which reduces the number of tester pins required for each part and increases through-put by allowing additional parts to be tested in parallel. Therefore ×16 parts accommodate 4× data compression and ×8 parts accommodate 2× data compression. The cost of any additional circuitry to implement address and data compression must be balanced against cost benefits derived from test time reduction. It is also important that operation in test mode achieve 100% correlation to operation in non-test mode. Correlation is often difficult to achieve, however, because additional circuitry must be activated during compression, which modifies the noise and power characteristics on the die.

In the description ofFIGS. 25,26,27,28, and29, we address primarily the issue of data compression. The issue of address compression is additionally dealt with hereinbelow.

InFIG. 25, one of the data test comparison circuits141found in the array I/O block100is illustrated. The circuit141receives a test signal from a data test DC enable circuit134also seen in FIG.8. The purpose of the data test comparison circuit141is to provide a first level of comparison.

The signals output by the various array I/O blocks100,102,104,106are input to the data test block b126illustrated in the center of FIG.26. The purpose of the data test block b126is to provide some additional compression and to reduce the number of tracks which must be provided. The output of the data test block b126is input to the data path test block128, which is illustrated in detail in FIG.27. As seen inFIG. 27, the data test block128is constructed of two types of circuits, a data test DC21circuit186and a data test BLK circuit188. One type of data test DC21circuit186is shown in detail inFIG. 28, which facilitates data and address compression, while one type of data test BLK circuit188is illustrated in detail inFIG. 29, which facilitates address compression. Each of the circuits186,188performs compression and comparison of the various input signals so as to produce at the output of the data path test block128a data read signal (DR, DR*) suitable for input to the data read mux108. Through the combination of the foregoing circuits which comprise the test data path, data compression and the benefits flowing therefrom as discussed above are achieved.

V. Product Configuration and Exemplary Design Specifications

The memory chip10of the present invention may be configured to provide parts of varying size.FIG. 30illustrates the mapping of the address bits to the 256 Meg array so as to provide ×16, ×8, and ×4 operation. Illustrated inFIG. 30is the mapping for each of the 32 Meg array blocks25,27,31,33,38,40,45,47for various types of operation. For example, for ×16 operation, the array block45is divided into four sections for storage of DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, and DQ7. If the chip10were configured for ×8 operation, the same array block45would be mapped to provide storage for only DQ0, DQ1, DQ2, and DQ3. If the chip10were configured for ×4 operation, the array block45would be mapped so as to provide storage for only DQ0and DQ1. The other array blocks are similarly mapped as shown in FIG.30.

The different part configurations are primarily a function of the various muxes provided in the read and write data paths as described hereinabove. Part configurations may be selected through bond options, which are “read” by the various logic circuits. The bond options for the present preferred embodiment are illustrated in Table 3 below. There are only two bond option pads. The logic circuits produce control signals for controlling the muxes and other components based on the selected part configuration.

For each configuration, the amount of array sections available to an input buffer must change. By using data write muxes as described hereinabove to drive as few or as many write driver circuits as required, design flexibility is easily accommodated. The pin configurations corresponding to operation as a ×16, ×8, and ×4 part are illustrated inFIGS. 31A,31B, and31C.

Regardless of the product configuration, all data is stored and retrieved from the main array12. The part is designed so that all data in the 256 Meg main array12can be located by bit column addresses and bit row addresses, the number of which is dependent on part size or type.

FIG. 32Aillustrates one column address mapping scheme for the 256 Meg main array12. Column address CA_9<0:1> selects between the bottom 64 Meg quadrants15and16and the top 64 Meg quadrants14and17. Selecting between 32 Meg array blocks within any 128 Meg quadrant is accomplished with a column address which is a function of part type and refresh rate (e.g. 32 Meg uses <0:1> in the figure). Within any 32 Meg array block, the array is divided into eight blocks of four Meg each, and the blocks are organized into four pairs. For example, column addresses CA1011<0:3> select one of the four pair, and column address CA_7<0:1> selects between the four Meg blocks making up the pair. Columns within each four Meg block are accessed with an eight bit address. Those eight bits are represented by column addresses CA_6<0:1>, CA45<0:3>, CA23<0:3>, CA01<0:3>, and CA_8<0:1>. Column address CA_6<0:1> represents the most significant bit in the address, and column address CA_8<0:1> represents the least significant bit in the address.

FIG. 32Billustrates the row address mapping for a single 64 Meg quadrant. Because row addresses are identical for each 64 Meg quadrant, row addressing will be described only with respect to a single 64 Meg quadrant. Each 64 Meg quadrant is divided into two 32 Meg array blocks, and row address RA_13<0:1> selects between the two 32 Meg array blocks. Each 32 Meg array block is divided into sixteen blocks of two Meg each, and those sixteen blocks are organized into four groups of four. Row addresses RA11<0:1> and 16 Meg select <0:1> together select one of the four groups. 16 Meg select <0:1> is a function of part type and refresh rate as shown in the table in the Figure. Within each group, row addresses RA910<0:3> select one of the two Meg blocks. Rows within each two Meg block are accessed with a nine bit row address. Those nine bits are represented by row addresses RA_0<0:1>, RA12<0:3>, RA34<0:3>, RA56<0:3>, and RA78<0:3>. Row addresses RA78<0:3> represent the most significant bits in the address, and row address RA_0<0:1> represents the least significant bit in the address.

Exemplary design specifications for the present preferred embodiment are as follows:

TABLE 5Features3.3 volt supply internally regulated to 2.5 voltsLaser fuses and antifuse cell Redundancy32 rows/32 Meg and 16 cols/16 Meg Laser Fuse Redundancy8 rows/32 Meg and 4 cols/16 Meg Anti-FuseLead Over Chip Bonding (LOC)Separate power and ground pins for output buffersFuse ID (laser and antifuse)

The power bussing scheme implemented in the present invention is based upon central distribution of voltages from a central area200illustrated inFIGS. 33A through 33Cand33D and E. The central area200is where the pads are physically located on the chip10. As seen inFIGS. 33D and E, a Vcc regulator220is centrally located within the pads area200. As will be discussed hereinbelow in conjunction withFIG. 35, the Vcc regulator220produces the array voltage Vcca and the peripheral voltage Vcc. A Vbb pump280, discussed in detail hereinbelow in conjunction withFIG. 37, is located in the right portion of the pads area200as seen inFIG. 33E. AVccp pump, which is described hereinbelow in conjunction withFIG. 39, is comprised of Vcc pump control401, a first plurality of pump circuits402, and a second plurality of pump circuits403. The Vccp pump produces a boosted version of Vcc referred to as Vccp which is used for biasing the wordlines. Finally, a plurality of DVC2generators500,501,502,503,504,505,506, and507are distributed throughout the central pads area200. One of the DVC2generators500is described in detail hereinbelow in conjunction with FIG.41. The DVC2generators500-507produce a voltage which is one-half of the peripheral voltage Vcc which is used for biasing the digitlines and the cell plate.

As seen inFIGS. 33A,33B, and33C, the web202is constructed so as to emanate from the central pads area200to surround each of the 32 Meg array blocks40and47illustrated inFIG. 33A, each of the array blocks27,33,38, and45illustrated inFIG. 33B, and each of the array blocks25and31illustrated in FIG.33C. For example, focusing upon the array block40inFIG. 33A, it is seen that the web202is comprised of a first plurality of conductors surrounding the array block10and carrying the following voltages: mapAVC2, mapDVC2, mapVccp, Vss, Vbb, and Vcca. The voltages AVC2, DVC2, and Vccp may be switched as shown inFIGS. 3A and 3Csuch that those voltages are no longer delivered to the array in the event the array is shut down. The web202, comprised of conductors carrying the foregoing voltages, surrounds each of the 32 Meg array blocks for efficient low resistance distribution.

Extending vertically into each 32 Meg array block at, for example, nine locations, are conductors carrying the following voltages: mapVccp, Vcca, and Vss. Extending horizontally through the 32 Meg array block at, for example, seventeen locations are conductors carrying the following voltages: mapAVC2, Vss, Vcca, mapDVC2, and Vbb. Thus, not only are each of the array blocks ringed, the power bussing layout features fully gridded power distribution through a second plurality of conductors for better IR and electromigration performance.

FIGS. 34A,34B, and34C illustrate the 71 pads and certain of the conductors connected to those pads. It is understood that the subject matter illustrated inFIGS. 34A,34B, and34C is located in the central pads area200ofFIGS. 33A through Cand33D and E. As seen inFIGS. 34A,34B, and34C, the pads designated Vccq, which are pads1,5,11, and15are connected to a Vccq conductor204. Conductor204runs parallel to the central portion of the web202as best seen inFIG. 33Abut is not part of the web202. The conductor204carries the power needed for the output buffers.

Pads17,32, and53, which are designated Vccx, are connected to a Vccx conductor206. Conductor206runs parallel to the central portion of the web202as best seen inFIG. 33Bbut is not part of the web. Pads59,65, and69, which are designated Vccq, are connected to a Vccq conductor208. Conductor208runs parallel to the central portion of the web202as best seen inFIG. 33Cbut is not part of the web202. Above, and parallel to the conductors204,206, and208, are conductors210,211, and212for carrying the voltages Vcc, Vcca, and Vcc, respectively. The conductors210,211,212are part of the first plurality of conductors forming the web202.

A conductor214, which provides a ground for the output buffers, is provided for connection to the pads designated Vssq which are pads2,6,12, and16as shown in FIG.34A. Conductor214runs parallel to the central portion of the web202as best seen inFIG. 33Abut is not part of the web. Another Vssq conductor216is provided for connection to the pads56,60,66, and70. Conductor216runs parallel to the central portion of the web202as best seen inFIG. 33Cbut is not part of the web202. Finally, a conductor218is provided for connection to pads marked Vss, which are pads18,33, and54. The Vss conductor218also extends below and beyond the conductors214and216as illustrated inFIGS. 34A,34B, and34C. Conductor218is part of the first plurality of conductors forming the web202. Through that method of distribution, voltages impressed upon the pads are efficiently distributed to the voltage supplies distributed throughout the central pads area200and the external voltage and ground are made available for the data output pad drivers.

VII. Voltage Supplies

The chip10of the present invention produces from the externally supplied voltage Vccx all of the various voltages that are used throughout the chip10. The voltage regulator220(FIG. 35) may be used to produce the array voltage Vcca and the peripheral voltage Vcc. The voltage pump280(FIG. 37) may be used to produce a back bias voltage Vbb for the die. The voltage pump400(FIG. 39) may be used to produce a boosted voltage Vccp needed for, inter alia, driving the word lines. The DVC2generators500-507(FIG. 41) may be used to produce a bias voltage DVC2for biasing the digitlines and a voltage AVC2(which is equal to DVC2)for the cellplate. The voltage regulator, Vbb pump, Vccp pump, and DVC2generators, which may be collectively referred to as a power supply, will each be described in detail.

FIG. 35is a block diagram illustrating the voltage regulator220which may be used to produce the peripheral voltage Vcc and array voltage Vcca from the externally supplied voltage Vccx. As seen fromFIG. 33E, the voltage regulator220is located in the center of the pads area200in what is referred to hereinbelow as the center logic (See Section VIII).

The process used to fabricate the chip10determines such properties as gate oxide thickness, field device characteristics, and diffused junction properties. Each of those properties in turn effects breakdown voltages and leakage parameters which limit the maximum operating voltage which a part produced by a particular process can reliably tolerate. For example, a 16 Meg DRAM built on a 0.35 μm CMOS process with 120 angstrom gate oxide can operate reliably with an internal supply voltage not exceeding 3.6 volts. If that DRAM had to operate in a 5 volt system, an internal voltage regulator would be needed to convert the external 5 volt supply to an internal 3.3 volt supply. For the same DRAM operating in a 3.3 volt system, an internal voltage regulator would not be required. Although the actual operating voltage is determined by process considerations and reliability studies, the internal supply voltage is generally proportional to the minimum feature size. The following table summarizes that relationship.

The circuit220is comprised of three major sections, an amplifier portion222, a tri-region voltage reference circuit224, which produces a reference voltage input to the amplifier portion222, and a control circuit226which produces control signals input to the amplifier portion222. Each will now be described in detail.

InFIG. 36A, the tri-region voltage reference circuit224is illustrated in detail. The tri-region voltage reference circuit224is comprised of a current source228. A current I1flowing through a resistor244generates a voltage which is equal to the gate to source voltage of a transistor230. The drain to source voltage of another transistor231is equal to the gate to source voltage plus Vth. The current flowing through the transistor231is constrained by a current mirror comprised of transistors245,246,247, and248to be equal to the current I1. In that manner, the current source228provides a current I1to a circuit node232. Current is drained from the circuit node232by a trimmable, or programmable, “pseudo”  diode stack234. The pseudo diode stack234is a plurality of transistors connected in series with their gate terminals connected to a common potential. The pseudo diode stack234is essentially a long channel FET which can be programmed or trimmed to provide the desired impedance.

Connected across each of the transistors in the pseudo diode stack234is a switching or trimming transistor from a stack236of such transistors. The gates of each of the switching transistors in the stack236are connected to a reference potential through a closed fuse or other type of device which may be either opened or closed. Assuming fuses are used, half of the gates may be connected to a potential which renders the switching transistor conductive, thereby removing the associated transistor from the stack234while the gates of the remaining transistors may be connected through fuses to a potential which renders the switching transistor nonconductive, thereby leaving the associated transistor in the stack234. In that manner, fuses may be blown to either turn on or turn off a switching transistor to thereby decrease or increase, respectively, the impedance of the trimmable diode stack234. In that manner, a reference signal (voltage) available at the circuit node232can be precisely controlled. Such trimming is required due to process variations during fabrication.

The current source228together with the pseudo diode stack234and switching transistors236form an active voltage reference circuit which produces the reference signal available at the circuit node232that is responsive to the external voltage Vccx applied to the circuit224. Those components are considered to form an active voltage reference circuit as contrasted with a resistor/trimmable pseudo diode stack combination found in the prior art which passively produces a signal at node232. A bootstrap circuit255is also provided to “kickstart” the current source228.

The reference signal available at circuit node232is input to a unity gain amplifier238. The output of the unity gain amplifier238is available at an output terminal240at which a regulated reference voltage Vref is available. Use of an active voltage reference circuit for producing the reference signal at circuit node232produces the desired relationship between Vref and Vccx which is not available with prior art circuits at the voltage range. Additionally, by making amplifier238a unity gain amplifier, common mode range and overall voltage characteristics are improved.

The tri-region voltage reference circuit includes a pullup stage242for pulling up the reference voltage available at output terminal240so that the reference voltage substantially tracks the external voltage when the external voltage exceeds a predetermined value. The pullup stage242is comprised of a plurality of diodes formed by pMOS transistors connected between the external voltage Vccx and the output terminal240. When the voltage Vccx exceeds the voltage at the terminal240by the number of diode drops in the series connected diodes comprising the pullup stage242, the pMOS diodes will be turned on clamping the voltage available at the output terminal240to Vccx minus the voltage drop across the diode stack.

The voltage available at the output terminal240is input to the amplifier portion222of the voltage regulator220where it is amplified to produce both the array voltage Vcca and peripheral voltage Vcc as will be described hereinbelow in conjunction with a description of amplifier portion222.

The relationship between the peripheral voltage Vcc and the externally supplied voltage Vccx is illustrated in FIG.36B. The tri-region voltage reference circuit224is responsible for those portions of the curve occurring in region2, corresponding to the “operating range” of the externally supplied voltage Vccx, and region3, corresponding to the “burn-in range” of the externally supplied voltage Vccx. The output of the tri-region voltage reference circuit224is not used to generate the peripheral voltage Vcc during region1. Region1is implemented by shorting the bus carrying the external voltage Vccx and the bus carrying the peripheral voltage Vcc together though pMOS output transistors found in the power stage of each power amplifier as will be described hereinbelow. The first region occurs during a powerup or powerdown cycle in which the externally supplied voltage Vccx is below a first predetermined value. In the first region, the peripheral voltage Vcc is set equal to the externally supplied voltage Vccx to provide the maximum operating voltage allowable in the part. A maximum voltage is desirable in region1to extend the DRAM's operating range and to ensure data retention during low-voltage conditions.

After the first predetermined value for the externally supplied voltage Vccx has been reached, the buses carrying the voltages Vccx and Vcc are no longer shorted together. After the first predetermined value for the externally supplied voltage Vccx is reached, the normal operating range, region2, illustrated inFIG. 36Bis entered. In region2, the peripheral voltage Vcc flattens out and establishes a relatively constant supply voltage to the peripheral devices of the chip10. Certain manufacturers strive to make region2absolutely flat, thereby eliminating any dependance on the externally supplied voltage Vccx. A moderate amount of slope in region2is advantageous for characterizing performance. It is important in the manufacturing environment that each DRAM meet the advertized specifications with some margin for error. A simple way to ensure such margins is to exceed the operating range by a fixed amount during component testing. The voltage slope depicted inFIG. 36Ballows that margin testing to occur by establishing a moderate degree of dependance between the externally supplied voltage Vccx and the peripheral voltage Vcc.

The third region illustrated inFIG. 36Bis used for component burn-in, and is entered whenever the externally supplied voltage Vccx exceeds a second predetermined value. That second predetermined value is set by the number of diodes in the diode stack comprising pullup stage242. During burn-in, both temperature and voltage are elevated above the normal operating range to stress the DRAM and weed out infant failures. Again, if there were no relationship between the external voltage Vccx and the peripheral voltage Vcc, the internal voltage could not be elevated.

The characteristic of the peripheral voltage Vcc may be summarized as follows: the slope of the peripheral voltage Vcc is substantially the same as the slope of the external voltage Vccx in region1(up to the first predetermined value); the slope of the peripheral voltage Vcc is substantially less than the slope of the external voltage Vccx in region2(between the first predetermined value and the second predetermined value); and the slope of the peripheral voltage Vcc is greater than the slope of the external voltage Vccx in region3(above the second predetermined value) because the signal available at output terminal240, which substantially tracks the external voltage Vccx, is multiplied in an amplifier having a gain greater than one.

The next section of the voltage regulator220is the control circuit226. The control circuit226is comprised of a logic circuit1250illustrated inFIG. 36C, a Vccx 2 v circuit252and a Vccx detect circuit253illustrated inFIG. 36D, and a second logic circuit258illustrated in FIG.36E. Turning first toFIG. 36C, the logic circuit1250receives a number of input signals: SEL32M<0:7>, LLOW, EQ*, RL*,8KREF, ACT, DISABLEA, DISABLEA*, and PWRUP. The logic circuit1250may be comprised primarily of static CMOS logic gates and level translators. The logic gates are referenced to the peripheral voltage Vcc. The level translators are necessary to drive the power stages, which are referenced to the external voltage Vccx. A series of delay elements tune the control circuit226relative to P-sense activation (ACT) and RAS* (RL*) timing. The purpose of the logic circuit1250is: (i) to produce, from the aforementioned input signals, clamp signals (for both N and P type transistors) for shorting, in the power amplifiers, a voltage bus carrying the external voltage Vccx with a voltage bus supplying the peripheral voltage Vcc, (ii) to produce an enable signal (for both N and P type transistors) for enabling the power amplifiers, and (iii) to produce a boost signal (for both N and P type transistors) for changing the slew rate of the amplifiers. The particular combination of logic gates illustrated inFIG. 36Cillustrates but one method of manipulating the aforementioned input signals to produce the previously listed output signals. The uses for the output signals will be described hereinbelow in conjunction with the amplifier portion222. Other methods for producing control signals are known. See, for example, U.S. Pat. No. 5,373,227 entitled Control Circuit Responsive To Its Supply Voltage Level and issued Dec. 13, 1994.

FIG. 36Dillustrates the Vccx 2 v circuit252and the Vccx detect circuit253. The circuit252receives the DISABLEA and DISABLEA* signals and produces two reference signals, VSW and VTH. The circuit253receives those signals and acts as a comparator to determine if the first predetermined value for Vccx (seeFIG. 36B) has been reached. Circuit253may be implemented as a CMOS comparator. The circuit253produces the signals PWRUP and PWRUP*. The PWRUP and PWRUP* signals are input to a number of circuits, such as the logic circuit1250and the amplifiers within the amplifier portion222as will be described hereinbelow.

FIG. 36Eillustrates the second logic circuit258which is the last element of the control circuit226. The second logic circuit258produces the PUMPBOOST signal and the DISABLEA and DISABLEA* signals used in other parts of the control circuit226from the following input signals: PWRDUP*, VccpON, VbbON, DISABLEA*, DISREG, and SV0. The PUMPBOOST signal will be described in conjunction with the amplifier portion222whereas the other two signals output from the second logic circuit258are, as mentioned, used both within the control circuit226and in the amplifier portion222.

Returning toFIG. 35, it is seen that the amplifier portion222is comprised of a plurality of power amps260,261a plurality of boost amps262, and a standby amp264which are selectively operated to achieve better characteristics than those obtainable with a single amplifier. The power amps260have greater than unity gain (e.g., 1.5×) which reduces the requirements of the reference voltage, Vref, and smooth transitions such as between the powerup range and the operating range shown in FIG.36B. Further, the power amps260may be controlled in groups (e.g., two groups of three each and a third group of twelve) rather than all on or all off at a time. Such controlled operation permits the number of operational power amps260to be reduced when power demand is low. Such controlled operation also enables additional amps to be activated, as needed, to achieve multiple refresh operations, e.g., firing two or more rows of the array at the same time. As explained further hereinbelow, the groups of power amplifiers have additional flexibility due to the ability to control individual power amps in a group.

A further novel characteristic of the amplifier portion222is to include one or more boost amplifiers262that are specialized in that they operate only when voltage pumps fire.

A further component of the amplifier portion222is the standby amplifier264. The standby amplifier264allows for a further reduction in current consumption when the other amplifiers are not operating. Prior voltage regulators for DRAMs included a standby amplifier but not one in combination with the power amplifiers260and boost amplifiers262. In the present invention, the standby amplifier264does not need to be designed to provide a regulated supply for voltage pumps, which is accomplished by the boost amplifiers262, such that the standby amplifier264may truly function as a standby amplifier.

The power amplifiers260, boost amplifiers262, and standby amplifier264are similar in general structure but the power amps operate at a moderate bias current level (e.g., approximately 1 ma, or about half of that required in the prior art) during memory array operations, such as reading and writing. The boost amplifiers262are designed for a low bias such as about 300 μa, and may also have a lower slew rate than the power amps because the boost amps operate only during operation of the voltage pumps which are described hereinbelow. The standby amplifier operates continuously at a very low bias of about 20 μa. Through the use of multiple power amplifiers260, boost amplifiers262, and the standby amplifier244, minimization of operating current for each of the various operating conditions experienced by the DRAM is achieved.

Six of the amplifiers in the amplifier portion222may be connected in parallel between the output of the tri-region voltage circuit224and the bus266which carries the peripheral voltage Vcc and twelve of the amplifiers in the amplifier portion222may be connected in parallel between the output of the tri-region voltage circuit224and the bus267which carries the array voltage Vcca. The power buses266and267are isolated except for a twenty ohm resistor269that bridges the two buses together. Isolating the buses is important because it keeps high current spikes that occur in the array from effecting the peripheral circuits. Failure to isolate buses266and267can result in speed degradation for the DRAM because large current spikes in the array may cause voltage cratoring and a corresponding slowdown in logic transitions. With isolation, the peripheral voltage Vcc is almost immune to array noise.

An electrical schematic illustrating one type of power amplifier260is illustrated in FIG.36F. To improve the slew rate, the power amplifier260features a boost circuit270that raises the bias current of a differential amplifier272to improve the slew rate during expected periods of large current spikes. Large spikes are normally associated with P-sense amp activation.

To reduce active current consumption, the boost circuit270is disabled a short time after P-sense amp activation by the signal labeled pump BOOST. The power stages are enabled by the signal ENS* only when RAS* is low and the part is active. When RAS* is high, all of the power amplifiers260are disabled.

The signal labeled CLAMP* ensures that the pMOS output transistor274is off whenever the amplifier is disabled to prevent unwanted charging of the Vcc bus. When forced to ground, however, the signal labeled VPWRUP shorts the Vccx and Vcc buses together through a pMOS output transistor274. The need for that function was described earlier in conjunction with the description of region1of FIG.36B. Basically, the bus carrying Vccx and the bus carrying Vcc are shorted together whenever the DRAM is operating in the powerup range of FIG.36B. The signals CLAMP* and VPWRUP are mutually exclusive to prevent a short circuit between the external voltage Vccx and ground.

The ENS signal is supplied to the gate of a transistor switch276whose conduction path is coupled at one end to the gate of one of the transistors of the differential amplifier272through a resistor R1while the other end of the conduction path is tied to ground. A second resistor R2is connected between the gate of the aforementioned transistor and the Vcc bus. The ratio of the resistors R1and R2determines the closed loop gain of the circuit. As previously mentioned, the power amplifiers260have somewhat higher than unity gain.

An example of a boost amplifier262is illustrated in FIG.36G. The boost amplifier262is very similar in construction and operation to the power amplifier in that it has an output pMOS transistor capable of shorting together the buses carrying Vccx and Vcc. The boost amplifiers262also have a greater than unity gain as a result of the ratio between resistors R1and R2. One difference between the boost amps262and the power amps260is that that boost amps262are responsive to the PUMPBOOST signal so that the boost amps262are operational whenever the voltage pumps are operational. Another difference is that the boost amplifiers262are designed to operate with a smaller bias current.

The standby amplifier264is illustrated in FIG.36H. The standby amplifier264is included to sustain the peripheral voltage Vcc whenever the DRAM is inactive, as determined by RAS*. The standby amplifier264is similar in design to the other amplifiers in that it is built around a differential pair, but is specifically designed for a very low operating current and a correspondingly low slew rate. Accordingly, the standby amplifier264cannot sustain any type of active load.

FIG. 36Iillustrates the details of one of the power amplifiers261in the group of twelve power amplifiers277illustrated in FIG.35. The power amplifiers261are of the same design as the boost amplifiers262described hereinabove and illustrated in detail in FIG.36G. The power amplifiers261, however, receive different control signals than the boost amplifiers262. For example, the power amplifiers261are responsive to the CLAMPF* signal in a manner similar to the power amplifiers260. Furthermore, the power amplifiers261are responsive to the VPWRUP and BOOSTF signals in a manner similar to the power amplifiers260. The functions of the CLAMPF*, VPWRUP, and BOOSTF signals are described hereinabove with respect to the power amplifiers260and FIG.36F.

The numbers of respective power amps260,261and boost amps262are matters of design choice according to the overall requirements of the DRAM. For example, a greater bandwidth is achieved by larger numbers of power amplifiers, which can be made relatively smaller if a larger number are to be provided.

A further factor affecting the choice of the number of power amplifiers has to do with the construction of the memory array. As described hereinabove, the memory array of the present invention is constructed of eight 32 Meg array blocks. Each block can be shut down if the quantity of failures or the extent of the failures exceeds the array's repair capability. That shutdown is both logical and physical. The physical shutdown includes removing power such as the voltages Vcc, DVC2, AVC2, and Vccp. It is often the case that the switches which disconnect power from the array block must be placed ahead of some of the decoupling capacitors44(seen inFIG. 3A) for that block. The decoupling capacitors44are provided to help maintain the voltage regulator's220stability. Reasons dictating the location of the decoupling capacitors44include the desire to have some decoupling capacitance proximate the array block because of possible current spikes in the array block and die geometry constraints. In the general case, the decoupling capacitance can be provided on both sides of the switch controlling an array block. When the total amount of decoupling capacitance available on the die is reduced with each array block that is disabled, there could be an adverse effect on voltage stability. Therefore, according to a further feature of the present invention, each array block has a corresponding power amplifier that is associated therewith and which is disabled whenever the array block is disabled. Disabling of a power amplifier260is accomplished by properly controlling the state of the ENS* signal produced by the eight pwr Amp Drive circuits seen in FIG.36C. That compensates for the reduction in decoupling capacitance and maintains the desired voltage stability by removing power amplifiers proportionately to the removal of decoupling capacitance.

More specifically, in the preferred embodiment, the power amps260are configured with a certain load capacitance and compensation network such that their slew rate and voltage stability are considered optimum when there is about 0.25 nanofarads of decoupling capacitance in the array block per power amplifier. In the disclosed embodiment, a group of twelve power amplifiers (277in FIG.35), includes eight that are respectively associated with each one of the eight array blocks and four additional amplifiers that are not affected by the array switches. When a switch is opened that disables an array block and its associates decoupling capacitors, a signal is input to the control circuit226to disable the corresponding power amplifier to maintain the correct, optimal, relationship. In additional to maintaining voltage stability, that reduces unneeded current consumption. In general, more decoupling capacitance is better for voltage stability and lower ripple but is worse for amplifier slew rate and hence an optimum is sought to be maintained.

The next elements which comprise the voltage supplies provided on the chip10are the voltage pumps, which include the voltage pump280(FIG. 37) which may be used to produce the Voltage Vbb used to back bias the die, and the voltage pump400(FIG. 39) which may be used to produce the Voltage Vccp which is a boosted voltage for the wordline drivers. Voltage pumps are commonly used to create voltages that are more positive or more negative than available supply voltages. The Vbb pump is typically built from pMOS transistors while the Vcc pump is built primarily from nMOS transistors. The exclusive use of nMOS transistors or pMOS transistors in each pump is required to prevent latchup from occurring and prevent current injection into the mbit arrays. The use of pMOS transistors is required in the Vbb pump because various active nodes will swing negative with respect to the substrate voltage, Vbb. Any n-diffusion regions connected to those active nodes would forward bias and cause latchup and injection. Similar conditions mandate the use of nMOS transistors in the Vccp pump.

Turning toFIG. 37, the Vbb pump280is illustrated in block diagram form. As seen fromFIG. 33E, the Vbb pump is located in the right portion of the pads area200in what is referred to hereinbelow as the right logic (See Section X). The pump is constructed of two pump circuits282,283. An electrical schematic of one of the pump circuits is illustrated in FIG.38A. The pump circuit283is the same as the circuit282and is therefore not illustrated.

InFIG. 38A, it is seen that the pump circuit282is responsive to an oscillator signal OSC input at an input terminal thereof. The circuit282is comprised of an upper pump portion285and a lower pump portion286which work in tandem to produce the output Voltage Vbb. Assume that the value of the oscillator signal OSC is such that the output of an inverter290available at a node292is high. A voltage available at a node293is clamped to ground by a pMOS transistor294. The nodes292and293are separated by a capacitor296. As the oscillator signal changes state such that the voltage available at the node292begins to decrease, the transistor294will be turned off and a pMOS transistor298will become conductive so that the charge on the capacitor296is made available to the bus carrying the voltage Vbb. The lower pump portion286operates in substantially the same manner but is constructed so that its output transistor298′ is conductive when the transistor298of upper pump portion285is nonconductive, and vice versa.

Returning toFIG. 37, the input to the pump circuits282and283which controls their operation is the signal OSC which is generated by a Vbb oscillator circuit300. An electrical schematic of one type of oscillator is illustrated in FIG.38B. The oscillator circuit300used in the voltage pump may be a CMOS ring oscillator of the type illustrated inFIG. 38B. Aunique feature of the oscillator circuit300is the capability for multi-frequency operation permitted by the inclusion of mux circuits302which are connected to various different tap points within the oscillator ring. The muxes, which are controlled by a signal labeled VBBOK*, enable higher frequency operation by reducing the number of inverter stages304comprising the ring oscillator. Typically, the oscillator circuit300is operated at a higher frequency when the DRAM is in a power-up state, because the higher frequency of operation will assist the Vbb pump to produce the required back bias voltage. The oscillator is enabled and disabled through a signal labeled OSCEN* which is produced by a Vbb regulator select circuit306as shown in FIG.37. The oscillator may also include the concepts disclosed in U.S. Pat. No. 5,519,360 entitled Ring Oscillator Enable Circuit With Immediate Shutdown, issued May 21, 1996, so that it can be immediately shut down thereby reducing the amount of noise.

The Vbb regulator select circuit306is illustrated in detail in FIG.38C. The circuit306receives the following input signals: DIFFVBBON, REG2VBBON, PWRDUP, DISVBB, and GNDVBB. The logic illustrated inFIG. 38Ccombines those signals to provide a signal labeled VBBREG* which is the same as the signal OSCEN* input to the oscillator300. An inverted version of that signal is also available as signal VBBON. Two other signals are generated by the circuit306, the signals labeled DIFFREGEN* and REG2EN*, which are used to select which of the two regulator circuits308and320will be enabled.

Returning toFIG. 37, a Vbb differential regulator2circuit308is provided.FIG. 38Dillustrates an electrical schematic of the circuit308. The circuit308, if enabled by the Vbb Regulator Select Circuit306, basically controls the operation of the Vbb pump circuits282,283albeit indirectly. The circuit308has a first portion310which produces the signal DIFFVBBON, that is input to the Vbb regulator select circuit306, which produces the signal for running the oscillator300, which drives the pump circuits282,283. The signal DIFFVBBON goes high whenever the back bias voltage Vbb is more positive than minus 1 volt.

A second portion312of the circuit308produces the signal VBBOK* which is directly input to the oscillator300. The signal VBBOK* speeds up the oscillator. The first circuit portion310and the second circuit portion312are the same circuit, and both operate as differential amplifiers. Basically, regardless of the specific circuit design, the Vbb differential regulator2circuit308should be constructed using low-biased current sources and pMOS diodes to translate the pump voltage Vbb to a normal voltage level. The reader seeking additional information concerning the Vbb differential regulator2circuit308is directed to U.S. patent application Ser. No. 08/668,347 entitled Differential Voltage Regulator, filed Jun. 26, 1996, and assigned to the same assignee as the present invention (Micron No. 96-172).

Returning toFIG. 37, the last element of the Vbb pump is the Vbb Reg2circuit320. An electrical schematic of the Vbb Reg2circuit320is illustrated in FIG.38E. The circuit320produces the REG2VBBON signal input to the Vbb regulator select circuit306. The input portion of the circuit320normalizes the input voltage. That normalized voltage level is then fed into a modified inverter stage having an adjustable trip point. The trip point may be modified with feedback to provide hysteresis for the circuit. Minimum and maximum operating voltages for the Vbb pump280are controlled by the first inverter stage trip point, the hysteresis, and the PMOS diode voltages.

Two regulator2circuits (308and320) are provided for enabling the selection of one of two control signals produced by circuits implementing different control philosophies. The Vbb differential regulator2circuit308produces a control signal from a differential amplifier stage. In contrast, the Vbb Reg2circuit320compares a normalized voltage to fixed trip points. Selection of one of the Vbb differential Reg2circuit308and Vbb Reg2circuit320may be made through a mask option. Depending upon the mask option selected, the Vbb regulator circuit306produces one of the two signals DIFFREGEN* or REG2EN* for activating either the Vbb differential regulator2circuit308or the Vbb regulator2circuit320, respectively. The activated regulator circuit then produces its control signal which is input to the Vbb regulator select circuit306for production of the signal OSCEN* for driving the Vbb oscillator circuit300.

The other voltage pump used in the circuit10is the Vccp pump400illustrated in FIG.39. The Vccp pump400produces a boosted voltage Vccp for, inter alia, the wordline drivers. The demand for the voltage Vccp varies considerably in different refresh modes. For example, a 256 Meg DRAM requires approximately 6.5 milliamps of current from the Vccp pump400when operating in an 8K refresh mode. In contrast, the same DRAM requires over 12.8 milliamps of current when operating in a 4K refresh mode. Unfortunately, a Vccp pump that can provide adequate current in 4K refresh mode is not suitable for use in an 8K refresh mode because it will generate an unacceptable level of noise and excessive Vccp ripple with the relatively light load applied in 8K refresh mode.

The Vccp pump400of the present invention is comprised of multiple pump circuits, six (410,411,412,413,414,415) being illustrated in the embodiment shown in FIG.39. All six pump circuits410-415are used to generate Vccp voltage during 4K refresh mode. However, if all six pump circuits are operated during 8K refresh mode, an unacceptable level of noise and excessive Vccp ripple will be generated because there will be an insufficient load on the pumps410-415. As a result, only a portion of the pump circuits410-415are used during 8K refresh mode.

The pump circuits410-415are divided into two groups, a primary group422comprising pump circuits410-412, and a secondary group423comprising pump circuits413-415. The primary group422of pump circuits410-412is always enabled by having their enable terminals tied to the peripheral voltage Vcc. The secondary group423of pump circuits413-415, however, are only enabled during 4K refresh mode by having their enable terminals tied to a 4K signal. The 4K signal is produced in the center logic as described herein below in conjunction with FIG.59J.

In addition to the six pump circuits410-415, the Vccp pump400includes the control portion401. As seen fromFIGS. 33D and E, the control portion401is found in the center logic (See Section VIII) while the pump circuits410-415are found in both the right and the left logic (See Section X).

All of the pump circuits410-415are driven by an OSC signal generated by an oscillator424. The OSC signal acts as an additional enable signal because it is required for the pump circuits410-415to operate. The oscillator424may be controlled by either of two regulators, a Vccp Reg.3circuit426or a differential regulator circuit428. The regulators426,428regulate Vccp by turning the pump circuits410-415on and off as needed to maintain Vccp at a desired level. The regulators426,428control the pump circuits410-415indirectly by controlling the oscillator424. Because only one of the regulators426,428may control the oscillator424, and thereby control the pump circuits410-415, a selection between the two regulators426,428is made by a regulator select circuit430. The selection may be made, for example, by opening or closing connections within the regulator select circuit430. Once a selection is made, the regulator select circuit430provides an enable signal to one of the regulators426,428. The regulator select circuit430then enables the oscillator424in response to signals received back from the enabled regulator426or428.FIG. 40Aillustrates the details of one type of regulator select circuit430.

The Vccp pump400also includes a burnin circuit434. The burnin circuit434generates a signal BURNIN used by various components, including the pump circuits410-415, to put components in a special “burnin mode” during component burnin tests. One type of burnin circuit434is illustrated in detail in FIG.40B.

The Vccp pump400further includes a pullup circuit438. The pullup circuit438connects the bus carrying Vccp to the bus carrying Vcc whenever Vccp falls at least one Vth below Vcc. One type of pullup circuit438is illustrated in detail in FIG.40C.

The Vccp pump400also includes four clamp circuits442, one of which is seen in FIG.40D. The clamp circuits442are usually enabled but can be disabled in a Test mode. Vccp is normally higher than Vcc, usually by a little more than one Vth. However, if Vccp becomes too high, e.g., more than about three Vths above Vcc, it will be clamped to Vcc to bring it back within acceptable limits. If Vccp becomes too low, e.g., more than about one Vth below Vcc, it will be clamped so as not to fall more than one Vth below Vcc by the clamp circuits442. Thus, the clamp circuits442bracket Vccp to keep it no greater than three Vths above Vcc and no less than one Vth below Vcc.

FIG. 40Eillustrates the details of one of the pump circuits410. The pump circuits410-415are two-phase pump circuits, meaning that one portion of the pump circuit pumps current when the OSC signal is high and another portion pumps current when the OSC signal is low. The pump circuits410-415are very similar in construction and operation to the pump circuits282,283of the Vbb pump, except that nMOS transistors are used. The pump circuits410-415include a first latch450and a second latch452which pump current through capacitors456,456′ and drive logic circuits462,462′. The logic circuit462provides a voltage to a gate of a transistor464. Transistor464conducts current to the Vccp bus when the OSC signal is low and transistor464′ conducts current to the Vccp bus when the OSC signal is high. The pump circuit410includes a Vccplim2circuit474and a Vccplim3circuit476which can be used during burnin mode to limit voltages on internal nodes of the pump. The details of one type of Vccplim2circuit474and the details of one type of Vccplim3circuit476are illustrated inFIGS. 40F and 40G, respectively.

FIG. 40Hillustrates the details of the oscillator424. The oscillator424is a ring-type oscillator similar to the oscillator300illustrated in FIG.38B. The oscillator424has a variable a frequency so that, for example, the pump circuits410-415may be operated at a higher frequency during powerup to more quickly bring the Vccp bus to its operating voltage. The oscillator424includes a series of inverters478which loops back on itself to form a ring. The time required for a signal to propagate through the inverters478determines the period of the signal OSC. Multiple frequency operation is implemented by the inclusion of several multiplexers479which receive signals from various tap points in the chain of inverters478. The multiplexers are controlled by a signal VPWRUP* and produce a higher frequency OSC signal by reducing the number of inverters478in the ring.

FIG. 40Iillustrates the details of one type of Reg Vccp3circuit426shown in FIG.39. The circuit426may use several series connected pMOS and nMOS diodes to “normalize” the voltage Vccp to the level of Vcc. In other words, several Vths are subtracted from Vccp by the diodes. The normalized voltage is used by transistors480,481,482, and483for generating an enable signal REG2VCCPON for the oscillator424. If the normalized voltage is too high, a low value of the enable signal is generated, and if the normalized voltage is too low, a high value of the enable signal is generated.

FIG. 40Jillustrates the details of the differential regulator circuit428shown in FIG.39. The differential regulator circuit428generates an enable signal DIFFVCCPON by comparing Vccp with a reference voltage in a differential amplifier486. When Vccp is below the reference voltage, a high value of the enable signal is generated to enable the oscillator424. When Vcc is above the reference voltage, a low value of the enable signal is generated to disable the oscillator424. A similar differential regulator circuit is disclosed in U.S. patent application Ser. No. 08/521,563 entitled Improved Voltage Regular Circuit, filed Aug. 30, 1995, and assigned to the same assignee as the present invention (Micron No. 94-088).

The last of the voltage supplies on the chip10are the DVC2generators one of which, generator500, is illustrated in FIG.41.FIG. 41is a block diagram of one of the DVC2generators500located in the right and left logic (See Section X). The DVC2generator500produces a voltage of one half of Vcc, known as DVC2, for biasing the memory capacitor cellplates. A related voltage, AVC2, which has the same value as DVC2, is used for biasing the digitlines between array accesses. The DVC2generator500includes a voltage generator510for producing the voltage DVC2and an enable1circuit512for enabling and disabling the voltage generator510. A stability sensor514receives the output from the voltage generator510and produces an output signal indicative of whether the voltage DVC2is stable.

The stability sensor514includes an enable2circuit515which generates enable signals for the stability sensor514. The stability sensor514includes a voltage detection circuit516for producing a signal indicative of whether the voltage level of the voltage DVC2is within a first predetermined range. A pullup current monitor518produces a signal indicative of whether a pullup current is stable. A pulldown current monitor520produces a signal indicative of whether a pulldown current is stable. An overcurrent monitor522produces a signal indicative of whether the pullup current is above a predetermined value, suggesting short circuits within the array.

An output logic circuit524receives the output signals from the voltage detection circuit516, the pullup current monitor518, and the pulldown current monitor520, and produces an output signal indicative of whether the voltage DVC2is stable. The output of the overcurrent monitor522is not input to the output logic524because overcurrent is not a measure of the stability of the voltage DVC2. Instead, the overcurrent output signal may be used during testing of the DRAM to diagnose defective array blocks. Furthermore, the output of the overcurrent monitor522may be latched at the end of powerup and used by the DRAM for self-diagnosis to determine whether an excessive current situation exists and whether a partial array shutdown is required.

Although the stability sensor514will be described as being used with the voltage generator510producing the voltage DVC2, the stability sensor514may be used with any power source, either on an integrated circuit or constructed of discrete components. Furthermore, the stability sensor514will be described as including the voltage detection circuit516, the pullup current monitor518, the overcurrent monitor522, and the pulldown current monitor520. Any of those components, however, may be used individually or in other combinations to provide an indication of the stability of a voltage generator.

FIG. 42Aillustrates the details of the voltage generator510shown in FIG.41. The voltage generator510is enabled by a signal DVC2EN* received from a powerup sequence circuit described below in Section XI, and signals ENABLE and ENABLE* received from the enable1circuit512. The voltage generator510generates the voltage DVC2which is available at a node530by varying the conductivity of transistors532and534connecting node530to Vcc and to ground, respectively. Current flowing from Vcc through transistor532to node530is “pullup” current because it raises the voltage at node530. Current flowing from node530through transistor534to ground is “pulldown” current because it lowers the voltage of node530. Pullup current and pulldown current are controlled by controlling the gate voltage, and thereby the conductivity, of transistors532and534, respectively. Feedback is provided from node530to the gates of a series of pMOS transistors536and the gates of a series of nMOS transistors538. The transistors536control the resistance of the path from the voltage Vcc to the gate of transistor532. Two nMOS transistors540and542control the resistance of the path away from the gate of transistor532. The nMOS transistors538control the resistance of the path from the gate of transistor534to ground. A pMOS transistor548controls the resistance of the path of the gate of transistor534to Vcc. A series of capacitors550and552connect the gate of transistor532to Vcc and to ground, respectively, thereby smoothing transitions in the gate voltage. Likewise, capacitors554and556connect the gate of transistor534to Vcc and to ground, respectively.

In operation, the voltage DVC2is held steady under varying loads by controlling transistors532and534in response to feedback signals. If DVC2is too high, pMOS transistors536begin to turn off thereby lowering the gate voltage of transistor532and decreasing the pullup current. At the same time, nMOS transistors538begin to turn on thereby decreasing the gate voltage and resistance of transistor534and increasing the pulldown current. The combination of decreased pullup current and increased pulldown current decreases the value of the DVC2voltage. Conversely, if DVC2is too low, transistors536begin to turn on thereby increasing the gate voltage of transistor532and increasing the pullup current. In addition, transistors538begin to turn off thereby increasing the gate voltage of transistor534and decreasing the pulldown current. The combination of increased pullup current and decreased pulldown current raises the voltage of DVC2. Related circuitry is disclosed in U.S. Pat. No. 5,212,440 entitled Quick Response CMOS Voltage Reference Circuit issued May 18, 1993.

FIG. 42Billustrates the details of one type of enable1circuit512shown in FIG.41. The enable1circuit512generates the signals ENABLE and ENABLE* for enabling the voltage generator510.

FIG. 42Cillustrates the details of one type of enable2circuit515shown in FIG.41. The enable2circuit515generates signals SENSEON, SENSEONB, SENSEON*, and SENSEONB*. Those signals are used to enable the voltage detection circuit516, the pullup current monitor518, the overcurrent monitor522, and the pulldown current monitor520.

FIG. 42Dillustrates the details of one type of voltage detection circuit516shown in FIG.41. The voltage detection circuit516is enabled by signals SENSEON and SENSEON*. The voltage detection circuit516receives the voltage DVC2from the voltage generator510and produces signals VOLTOK1and VOLTOK2indicative of whether the voltage DVC2is within a predetermined range of voltages. The predetermined range is defined by ground plus the turn-on voltage of an nMOS transistor560, and Vcc minus the turn-on voltage of a pMOS transistor562. The range may be adjusted by adjusting the turn-on voltages of the transistors560and562. The voltage DVC2is connected to the gate of the nMOS transistor560and the gate of the pMOS transistor562, and only when the voltage DVC2is within the predetermined range are both of the transistors560and562turned on and both of the signals VOLTOK1and VOLTOK2at a high logic value. If the voltage DVC2is too high, transistor560will be turned on but transistor562will be turned off, so that signal VOLTOK1will be high but signal VOLTOK2will be low. Likewise, if the voltage DVC2is too low, transistor560will be turned off but transistor562will be turned on, so that signal VOLTOK1will be low and signal VOLTOK2will be high.

More particularly, a resistor564allows current to trickle from Vcc to the input terminal of an inverter566. When transistor560is turned off, the current coming through resistor564creates a high logic state at the input terminal of the inverter566. When transistor560is turned on, current flows through transistor560and the input terminal of the inverter566is pulled to a low logic state. Likewise, a resistor568allows current to drain from the input terminal of an inverter570, resulting in a low logic state. When transistor562is turned off, the low logic state is undisturbed at the input terminal of inverter570. When transistor562is turned on, however, current flows through transistor562and into the input terminal of the inverter570, and a high logic state exists at the input terminal of inverter570.

FIG. 42Eillustrates the details of one type of pullup current monitor518shown in FIG.41. The pullup current monitor518is enabled by signals SENSEONB, SENSEONB*, and ENABLE*, is responsive to the PULLUP current and the voltage DVC2, and produces signals PULLUPOK1and PULLUPOK2indicative of whether the pullup current is stable. The pullup current monitor518includes several current sources in the form of transistors582,583,584, and585. The current sources582-585are responsive to the PULLUP current such that each transistor sources a current indicative of the present pullup current in the voltage generator510. The pullup current monitor518also includes several current sinks in the form of transistors588,589, and590. The current sink588sinks a current indicative of the present pullup current. The current sinks589-590each sink a current indicative of a past pullup current. A time delay between the past pullup current and the present pullup current is defined by an RC time constant created by a resistor594and a capacitor596. The charge on the capacitor596is indicative of the past pullup current and changes when current flows into or out of the capacitor596through the resistor594. Current flows into capacitor596when the source current from transistor582is greater than the sink current flowing through transistor588. Conversely, current flows out of capacitor596when the source current from transistor582is less than the sink current through transistor588. A delay in the charging and the discharging of the capacitor596is caused by the RC time constant and can be adjusted to obtain a desired delay between the current sinks589-590and the current sources582-585. Transistors589-590have gates connected to capacitor596such that they each sink a current indicative of the past pullup current.

As seen inFIG. 42E, transistor582is connected in series with transistor588, transistor583is connected in series with transistor589, and transistor585is connected in series with transistor590. In operation, transistor588acts to control the current input to the capacitor596. When the source current exceeds the sink current, transistor582is generating more current than transistor588is sinking. As a result, the additional source current flows through resistor594and charges capacitor596. If the source current is less than the sink current, then transistor588is sinking more current than transistor582is sourcing and the additional sink current flows from the capacitor596through the resistor594and through transistor588, thereby decreasing the charge on capacitor596.

A resistor600, current source583, and current sink589form a positive differential current circuit for determining whether the present pullup current is greater than the past pullup current. When the source current through transistor583is greater than the sink current through transistor589, the additional source current flows through resistor600to ground. That current creates a positive voltage across resistor600, raising the voltage at an input terminal of an inverter602. When the voltage at the input terminal of the inverter602becomes a high logic value, the inverter602will change the output signal PULLUPOK1to a low logic value indicating an increase in the pullup current. When the source current is less than or equal to the sink current, the voltage across resistor600is zero or negative, and does not affect the signal PULLUPOK1.

Similarly, a resistor606, current source585, and current sink590form a negative current differential circuit for determining whether the present pullup current is less than the past pullup current. When the sink current through transistor590is greater than the source current through transistor585, the additional sink current flows from Vcc through resistor606and into transistor590. As a result, a voltage at an input terminal of an inverter608is lowered. When the voltage at the input terminal of the inverter608becomes a low logic value, the signal PULLUPOK2will change to a low logic value as a result of the series connection of inverter608with an inverter609thereby indicating that the pullup current has decreased. However, when the sink current through transistor590is equal to or less than the source current through transistor585, additional current builds up at the input terminal of inverter608, causing the voltage at the input terminal of inventor608to remain at a high logic value, thereby maintaining a high logic value for the PULLUPOK2signal.

The pullup current monitor518also includes the overcurrent monitor522. The overcurrent monitor522includes current source584and generates a signal DVC2HIC indicative of whether the pullup current is excessive. The source current from transistor584flows into a resistor514. Resister514converts the current into a voltage that is monitored by an inverter616. As long as the source current is not too high, the input terminal of inverter616remains at a low logic state. If, however, the source current becomes excessive, the input terminal of inverter616changes to a high logic state and causes signal DVC2HIC to assume a high logic state, as a result of the series connection of the inverter616with an inverter617, indicating an overcurrent situation. The amount of current required to trigger the overcurrent monitor is defined by the input voltage at which the inverter616changes states divided by the resistance of resistor514.

The pulldown current monitor520illustrated inFIG. 42Ffunctions in an analogous manner to the pullup current monitor518. The pulldown current monitor520includes current sinking transistor620-622for sinking a current indicative of the present pulldown current in the voltage generator510. The pulldown current monitor520also includes current sourcing transistor626-628. Transistor626generates a source current indicative of the present pulldown current and transistors627and628generate a source current indicative of a past pulldown current. The time difference between the present pulldown current and the past pulldown current is defined by an RC time constant formed from a resistor630and a capacitor632. Pulldown current monitor520also includes a resistor636forming part of a positive differential current circuit for producing signal PULLDOWNOK1and a resistor638forming part of a negative differential current circuit for producing signal PULLDOWNOK2. The pulldown current monitor520, however, does not include a circuit analogous to the overcurrent monitor522.

FIG. 42Gillustrates the details of the output logic524shown in FIG.41. The output logic524is enabled by signal ENABLE and receives signals VOLTOK1and VOLTOK2from the voltage detection circuit516, PULLUPOK1and PULLUPOK2from the pullup current monitor518, and PULLDOWNOK1and PULLDOWNOK2from the pulldown current monitor520. If the output logic524is enabled, and if all the input signals indicate that the voltage generator510is stable, the output logic524will generate a signal DVC2OK*, indicating that the DVC2voltage is stable. That, completes the description of the voltage supplies.

VIII. Center Logic

The center logic23illustrated inFIG. 2is illustrated in block diagram from in FIG.43. The center logic is responsible for performing a number of functions including processing of the row address strobe signals in a RAS chain circuit650, processing of column address strobe signals in control logic651, row address predecoding in row address block652, and column address predecoding in block654. The center logic23also contains test mode logic656, option logic658, a “spares” circuit660, and a misc. signal input circuit662. The control portion401of the Vccp pump400(seeFIG. 39) and the voltage regulator220(seeFIG. 35) are located in the center logic. Completing the description of the center logic23illustrated inFIG. 43, a power up sequence circuit1348of the type illustrated inFIG. 100is also provided. Each of the blocks650,651,652,654,656,658,660and662illustrated inFIG. 43will now be described. The voltage regulator220and the control portion401of the Vccp pump400have already been described hereinabove in Section VII; the power up sequence circuit1348is described hereinbelow in Section XI.

The RAS chain circuit650is illustrated in block diagram form in FIG.44. The purpose of the RAS chain circuit650is to provide read and write control signals for the circuit10. Beginning in the upper left hand corner ofFIG. 44, a RAS D generator665is provided. The purpose of the generator665is to simulate the time needed for the address buffers to set up. A signal RASD is produced by the generator665in response to that simulation. An electrical schematic of one type of RAS D generator665is illustrated in FIG.45A.

The next circuit in the RAS chain circuit650is the enable phase circuit670. The purpose of the circuit670is to generate phase signals ENPH, ENPH* used for timing purposes. An electric schematic of one type of circuit670is illustrated in FIG.45B.

An ra enable circuit675is provided to generate row address latch signals RAL and row address enable signals RAEN*. Those signals are input to an equilibration circuit700and an isolation circuit705, the purpose of which will be described hereinbelow. An electric schematic illustrating one type of circuit675is illustrated in FIG.45C.

The RAS chain circuit650includes a WL tracking circuit680the purpose of which is to approximate how long it takes a wordline to fire. An electrical schematic of one type of tracking circuit680is illustrated in FIG.45D. The tracking circuit illustrated inFIG. 45Dis comprised of a first portion681which estimates the time needed for the row encoders to power up, a second portion682which estimates the time required for the array to power up (shown schematically in the enlargement), and a third portion683which provides additional delay before the signal WLTON is produced. The signal WLTON is used for wordline tracking.

A sense amps enable circuit685is provided which produces signals ENSA, ENSA* for firing the N-sense amplifiers and signals EPSA, EPSA* for firing the P-sense amplifiers. An electrical schematic of one type of sense amps enable circuit685is illustrated in FIG.45E.

A RAS lockout circuit690is provided for generating a signal RASLK* which is used elsewhere in the logic for lockout purposes. An electric schematic of one type of RAS lockout circuit690is illustrated in FIG.45F.

An enable column circuit695is provided to produce the signals ECOL, ECOL* which are used to enable the column address circuitry. An electrical schematic of one type of enable column circuit695is illustrated in FIG.45G.

An equilibration circuit700and isolation circuit705each receive the signals RAEN*, RAEND which are used to produce the EQ* signal and ISO* signal, respectively. The EQ* signal is used to control the equilibration process while the ISO* signal controls the isolation of the array. An electrical schematic of one type of circuit which may be used for the equilibration circuit700is illustrated inFIG. 45Hwhile an electrical schematic of one type of circuit which may be used for the isolation circuit705is illustrated in FIG.45I.

A read/write control circuit710is provided for producing the signals CAL* and RWL. The purpose of the circuit710is to latch the column address buffers when the correct combination of CAS*, RAS*, and WE* are provided at the input thereto. An electrical schematic of one type of circuit which may be used for the read/write control circuit710is illustrated in FIG.45J.

A write time out circuit715is provided to control the write function. That control is implemented through the production of a signal WRTLOCK* which is input to the read/write control circuit710for control purposes. An electrical schematic of one type of write time out circuit715is illustrated in FIG.45K.

A plurality of data in latches720and725are provided for latching data. An electrical schematic of one type of latch circuit which may be used for data in latch720is illustrated inFIG. 45Lwhile an electrical schematic of one type of latch circuit which may be used for the data in latch725is illustrated in FIG.45M. The latch circuits720and725may, in fact, be identical with only the signals input thereto changing.

A stop equilibration circuit730is provided to generate a signal STOPEQ* for the purposes of ending the equilibration process. An electrical schematic of one type of stop equilibration circuit730which may be used is illustrated in FIG.45N.

Completing the description of the RAS chain circuit650, a CAS L RAS H circuit735and a RAS-RASB circuit740are provided to monitor the status of the CAS and RAS signals for producing output signals used elsewhere in the logic, and ultimately for controlling the amount of power generated by the voltage regulators. An electrical schematic of one type of CAS L RAS H circuit735is illustrated inFIG. 450while an electrical schematic of one type of RAS-RAS B circuit740is illustrated in FIG.45P.

The control logic651illustrated inFIG. 43is illustrated in block diagram form in FIG.46. The control logic651includes a RAS buffer745. The RAS buffer is produces two output signals PROW* which is for powering up the row address buffer and a signal RAS* which starts the RAS chain circuit650. An electrical schematic of one type of RAS buffer which may be used for the buffer745is illustrated in FIG.47A.

A fuse pulse generator750is provided which is responsive to the powered up signal, produced by the powerup sequence circuit described hereinbelow, and the RAS* signal. The fuse pulse generator750produces a number of pulses which effectively prompt the circuit10to determine the status of various bond options and fuses. An electrical schematic of one type of fuse pulse generator750is illustrated in FIG.47B.

An output enable buffer755is responsive to a number of input signals for producing an output enable OE signal. An electrical schematic of one type of output enable buffer which may be used for the output enable buffer755is illustrated in FIG.47C.

The next two circuits, a CAS buffer760and a dual CAS buffer765, are responsive to various input signals related to the CAS signal to produce output signals input to a QED logic circuit775. In an x16part, CAS H refers to the eight most significant bits of the data while CAS L refers to the eight least significant bits of the data. An electrical schematic illustrating one type of CAS buffer which may be used for the CAS buffer760is illustrated inFIG. 47Dwhile47E is an electrical schematic of one type of dual CAS buffer which may be used for the dual CAS buffer765.

A write enable buffer770produces a write enable signal WE* and a signal PWE* which are input to the QED logic circuit775. An electrical schematic of one type of circuit which may be used for the write enable buffer770is illustrated in FIG.47F.

The QED logic circuit775is responsive to a number of input signals illustrated in both FIG.46and FIG.47G. The QED logic circuit775is responsible for producing the control signals QEDL, responsible for the low byte, and QEDH, responsible for the high byte. The control signals QEDL and QEDH are ultimately responsible for controlling the transfer of data. The electrical schematic illustrated inFIG. 47Gillustrates one type of QED logic circuit which may be used for the QED logic circuit775.

A data out latch780is provided to hold the data until the CAS signal goes low and new data is latched. An electrical schematic for one type of data latch which may be used as the data out latch780is illustrated in FIG.47H.

A row fuse precharge circuit785produces signals which are input to row fuse blocks, discussed hereinbelow, for initiating the process of determining if there is a match between a row address and a redundant row address. An electrical schematic of one type of circuit which may be used for the row fuse precharge circuit785is illustrated in FIG.47I.

A CBR circuit790is provided for determining when there is an occurrence of CAS before RAS. An electrical schematic of one type of circuit suitable for the CBR circuit790is illustrated in FIG.47J.

A pcol circuit800is provided which is responsive to the input signals RAS*, WCBR, CBR, and RAEN* for producing the signals PCOL WCBR*, PCOL*, and PCOL. An electrical schematic of one type of circuit which may be used for the p col circuit800is illustrated in FIG.47K. The signal PCOL WCBR* is input to the column predecode enable circuits to enable the column predecoders.

Finally, write enable circuits805and810are provided which are substantially identical in construction and operation. An electrical schematic of one type of write enable circuit which may be used for the circuit805is illustrated inFIG. 47Lwhile an example of a write enable circuit which may be used for the circuit810is illustrated in FIG.47M.

The row address block652ofFIG. 43is illustrated in block diagram form inFIGS. 48A and B. InFIGS. 48A and Ba number of row address buffers820through833are illustrated. Each of the row address buffers820through833is responsive to a different bit of the row address information. The row address buffers are also responsive to a row address enable circuit835while the first row address buffer820is responsive to a clock837. The row address block652also includes a row address predecoder840comprised of a 2 inv driver842, an all row P decode row driver844, and a plurality of NANDP decoders846through850. The row address block652also includes a 4k8k log circuit852and an 8k16k log circuit854.

An electrical schematic of the row address buffer820as well as the row address enable circuit835and clock837is illustrated in FIG.49A.FIGS. 49B and 49Cillustrate the wiring between the row address buffers820through833. The electrical schematics illustrated in FIG.49A and the wiring diagrams illustrated inFIGS. 49B and Care one implementation of the required functionality.

Turning toFIG. 50A, an example of a 2 inv driver842is illustrated. Also illustrated is an example of one type of an all row P decode row address driver844and an exemplary circuit for the NAND P decoders846. The inputs and outputs for the NAND P decoders847,848, and849are illustrated in FIG.50B. It is to be understood that the NAND P decoders847,848, and849illustrated inFIG. 50Bmay take the form of the NAND P decoder846illustrated in FIG.50A. Finally, the NAND P decoder850and the log circuits852and854are illustrated in detail in FIG.50C.

FIGS. 51A and 51Billustrate in block diagram form the column address block654illustrated in FIG.43. The column address block654is comprised of a plurality of column address buffers860through872which are each responsive to a bit of the column address information. The column address buffers860through868are also responsive to a pcol address1circuit874. The column address buffer869is responsive to a pcol address circuit876. Similarly, the column address buffers870,871,872are each responsive to a pcol address10, address11, and address12circuits878,880, and882, respectively.

The column address block654also includes a column predecode portion884which includes a column P decoder enable circuit886and a plurality of encode P decoders888through893. The decoder893is also responsive to a mux895.

Completing the description of the column address block654illustrated inFIG. 51B, two select circuits, a 16 meg select circuit897and a 32 meg select circuit898are provided to produce control signals which dictate the functions of the various addresses. An equilibration driver900is responsive to a plurality of ATD 4AND circuits902,903, and904.

FIGS. 52A,52B, and52C illustrate the column address buffers860through872with the column address buffer860and the column address buffer872being illustrated as electrical schematics. Also illustrated as electrical schematics are the pcol address1circuit874and the pcol address9circuit876. The address circuits878,880, and882are illustrated as electrical schematics in FIG.52D. The reader should understand that the electrical schematics and wiring configuration illustrated inFIGS. 52A through 52Dillustrate but one example for implementing and interconnecting the column address buffers.

The predecoder portion884of the column address block654is illustrated as an electrical schematic and wiring diagram in FIG.53. One of the encode P decoders888is illustrated as an electrical schematic as are the column P decoder enable circuit886and the mux895. The reader should understand that the electrical schematic and wiring configuration illustrated inFIG. 53is but one implementation for the predecoder portion884.

An electrical schematic which may be used to implement the 16 meg select circuit897is illustrated in FIG.54A. An electrical schematic which may be used to implement the 32 meg select circuit898is illustrated in FIG.54B. The select circuits897and898determine the significance of the address information.

Finally, the equilibration driver900and associated circuits902,903,904are illustrated as an electrical schematic in FIG.55. The equilibration driver900produces the signals which are used to equilibrate the sense amps and IO lines. The reader should understand that the electrical schematic illustrated inFIG. 55is but one way to implement the equilibration driver900.

The test mode logic656illustrated inFIG. 43is illustrated as a block diagram in FIG.56. InFIG. 56, the test mode logic656is comprised of the following circuits:

a test mode reset circuit910shown in detail inFIG. 57A;a test mode enable latch912shown in detail inFIG. 57B;a test option logic circuit914shown in detail inFIG. 57C;a supervolt circuit916shown in detail inFIG. 57D;a test mode decode circuit918shown in detail inFIG. 57E;a plurality of SV test mode decode2circuits920and a plurality of associated output buses921shown in detail inFIG. 57F;an optprog driver circuit922shown in detail inFIG. 57F;a red test circuit923shown in detail inFIG. 57G;a Vccp clamp shift circuit924shown in detail inFIG. 57H;a DVC2up/down circuit925shown in detail inFIG. 57I;a DVC2OFF circuit926shown in detail inFIG. 57J;a pass Vcc circuit927shown in detail inFIG. 57K;a TTLSV circuit928shown in detail inFIG. 57L; anda disred circuit929shown in detail in FIG.57M.

An electrical schematic of one type of test mode reset circuit which may be used for the reset circuit910is illustrated in FIG.57A. If a test mode is to be reset, test mode reset circuit910provides the SVTMRESET signal to the SV test mode decode2circuits920of FIG.57F and the TMRESET signal to the test mode decode circuit918of FIG.57E.

An example of a test mode enable latch912is illustrated in FIG.57B. In the present preferred embodiment of the invention, addresses have been divided into two categories: for the low set of addresses, signal SVTMLATCHL is used while the signal SVTMLATCHH is used for the high set of addresses. The signals SVTMLATCHL and SVTMLATCHH are mutually exclusive. The signal TMLATCH is supplied to the test mode decode circuit918of FIG.57E and the SV test mode decode2circuits920of FIG.57F.

An example of the test option logic914is illustrated as an electrical schematic in FIG.57C. The logic illustrated inFIG. 57Cis but one example of how the test mode logic914ofFIG. 56may be implemented.

One example of an electrical schematic for implementing the supervolt circuit916is illustrated in FIG.57D. The purpose of the supervolt circuit916is to prevent a power-up when the chip is in a supervoltage mode.

An electrical schematic illustrating one example of a test mode decode circuit918is illustrated in FIG.57E. Test mode decode circuit918is employed to decode certain column address bits to activate a supervolt test mode enable signal (SVTMEN*) when a signal (TMLATCH), indicating that the supervoltage mode is to be looked for, is latched. By latching a test or detect mode with latches906,907, if the address signal is correct or a match, then initiation of a test mode begins with the SVTMEN* signal being activated. Latch906latches a supervoltage enable test mode at a RAS active (low) time. Latch907latches the supervoltage enable test mode after RAS goes inactive (high) and the WLTON 1 signal is inactive. That allows other test mode(s) to be looked at or entered provided signal NCSV (FIG. 57D) goes to a supervoltage level. Test mode decode circuit918provides the signal SVTMEN* to the supervolt circuit916(FIG. 57D) and test mode enable latch912(FIG.57B). Supervolt circuit916, in response to the signal SVTMEN*, activates the supervolt signal SV when the signal NCSV is in the supervolt mode. The signal SV is provided to the test mode reset circuit910of FIG.57A and the test mode enable circuit latch912. To prevent inadvertent access, two cycles are needed to enter a test mode to test mode decode circuit918(FIG.57E). In one embodiment, a first WCBR cycle is used to initiate a ready state; a second WCBR cycle is used to actually enter a test mode state. That makes it more difficult to inadvertently enable supervoltage and enter a test mode state. If the test mode enable latch912is active, either the signal SVTMLATCHH or the signal SVTMLATCHL (FIG. 57B) will be active for activating certain of the supervolt test mode decode2circuits920of FIG.57F.

The SV test mode decode2circuits920, of which there are eight, are illustrated in detail inFIG. 57Ftogether with the respective output buses921. The reader should realize that the electrical schematic illustrated in the bottom portion ofFIG. 57Fmay be used to implement the other SV test mode decode2circuits as well as the fact that other combinations of logic gates may be used to implement that functionality. Also shown inFIG. 57Fis the optprog driver circuit922which produces the signal OPTPROG* which is input to the option logic658.

The SV test mode decode2circuits920receive column address fuse identification signals (CAFID), column address test mode bit signals, test mode latch signals (SVTMLATCH), and fuse identification select signals (FIDBSEL), in addition to the TMSLAVE signal, TMSLAVE* signal, and supervolt test mode reset signal (SVTMRESET). The number of column address test mode bit signals depend on array size, number of test modes, number of fuse identifications, multiplexing, and the like. Each of the SV test mode decode2circuits920provides test mode signals TM, TM*, as well as fuse identification signals FIDDATA, FIDDATA*. While the signals FIDDATA indicate fuse ID, it should be understood that technology other than fuses, such as latches, flash cells, ROM cells, antifuses, RAM cells, mask programmed cells, or the like, may be used.

With continuing reference toFIG. 57F, SV test mode decode2circuit920receives column address bits via inputs A0and A1. Such bits may be multiplexed. Bits received by a NOR gate1262are for identifying a selected test mode. The column address fuse ID signal (CAFID) is supplied to a NAND gate1263along with the fuse ID select signal (FIDBSEL). The signal FIDBSEL is for selecting a fuse bank while the signal CAFID is for selecting a bit of a selected bank.

A signal available at an output terminal of the NAND gate1263is input directly to an inverting tri-state buffer1264and is input to the buffer1264through an inverter1265. When the output of the NAND gate1263is inactive, output buffer1264is tri-stated. When the output of the NAND gate1265is active, data signals FIDDATA, FIDDATA* are active such that information is output. The TMSLAVE and TMSLAVE* signals are for setting a latch1266formed by a pair of multiplexers. The signal TMLATCH is for setting a latch1267formed by another pair of multiplexers. As the column address bit information is processed, a test mode can be latched by the latch1267via signal TMLATCH. The latched test mode status of latch1267is provided to latch1266resulting in the output of the signal SEL32MTM after RAS and WLTON go inactive. A discussion of a timing diagram for test mode entry is set forth hereinbelow in conjunction with FIG.103.

An electrical schematic illustrating one implementation of the redundant test circuit923is illustrated in FIG.57G. The circuit923produces redundant row and redundant column signals as illustrated.

The Vccp clamp shift circuit924is illustrated in FIG. H. The circuit924is used to shift the voltage level of the input signal. Other types of clamp shift circuits may be implemented.

FIG. 57Iillustrates an example of a DVC2up/down circuit925. The circuit925produces the signals DVC2up* and DVC2down which are input to the DVC2up circuit1069and the DVC2down circuit1070, respectively, both of which are illustrated in FIG.72B.

In FIG,57J an example of a DVC2OFF Circuit926is illustrated. The circuit926produces the signal DVC2OFF which is input to the enable1circuit512illustrated in FIG.42B.

FIG. 57Killustrates the Pass Vcc circuit927. Other ways of implementing the functionality provided by the circuit927may be implemented.

FIG. 57Lillustrates an implementation for the TTLSV circuit928. The primary function of the circuit928is to delay the signal TTLSVPAD.

Lastly, a disred circuit929is illustrated in FIG.57M. The circuit929may be implemented by a Nor gate as shown in the figure.

The next element ofFIG. 43to be described is the option logic658which is illustrated as a block diagram inFIGS. 58A and 58B. InFIG. 58A, a plurality of both fuse 2 circuits930through940are responsive to a number of external signals. The both fuse2circuits932through940are responsive to an SGND circuit941while the both fuse 2 circuits930,931are responsive to a second SGND circuit942.

An ecol delay circuit944provides input to an anti-fuse cancel enable circuit945.

InFIG. 58B, a first CGND circuit946is responsive to an OPTPROG signal and a CGND Probe signal. Additional CGND circuits947-951are responsive to an XA<10> signal; CGND circuit #947is responsive to the OPTPROG signal, and CGND circuit948-951are responsive to an ANTIFUSE signal.

Returning toFIG. 58A, an anti-fuse program enable circuit956produces a signal input to a plurality of passgate circuits952through955. A PRG CAN decode circuit957is responsive to the passgate952, a PRG CAN decode circuit958is responsive to the passgate circuit953, and FAL circuits959and960are responsive to both the passgate952and the passgate954.

Bond option circuits965,966produce input signals which are input to a bond option logic circuit967.

Two laser fuse option circuits970and971are also provided. In addition to the laser fuse option circuits970,971, a bank of laser fuse option2circuits978through982(SeeFIG. 58B) are provided. The laser fuse option2circuits978through982are responsive to a reg pretest circuit983.

Completing the description ofFIG. 58A, the option logic658also includes a 4K logic circuit985, a fuse ID circuit986, a DVC2E circuit987, a DVC2GEN circuit988, and a 128 Meg circuit989.

An electrical schematic of one type of circuit which may be used as the both fuse2circuits930through940is illustrated in FIG.59A. The external signals which are on a bus which interconnects all of the both fuse2circuits931through940is illustrated inFIG. 59Bas is the 120 Meg circuit989.

FIG. 59Cillustrates an electrical schematic of one type of SGND circuit941.

One embodiment of the ecol delay circuit944and the antifuse cancel enable circuit945is illustrated in detail in FIG.59D. The circuits944and945cooperate to produce the LATMAT signal.

FIG. 59Eillustrates an electrical schematic of the CGND circuit951, which may be used to implement the other CGND circuits947-951, as well as the interconnection of the CGND circuits946-951.

FIG. 59Eillustrates one implementation for the passgates952-955, anti-fuse program enable circuit956, PRG decode circuits957,958, and FAL circuits959,960. The reader should understand that the details illustrated inFIG. 59Fare but one method of implementing the functionality of that circuitry.

An electrical schematic for implementing the bond option circuits965,966is illustrated inFIG. 59Gas is the bond option logic circuit967. The purpose of the bond option circuits965,966and the bond option logic967is to determine the bond option selected and to produce logic signals instructing the part if it is an ×4, ×8 or ×16 part.

The laser fuse option circuits970,971are illustrated in FIG.59H.FIG. 59Hillustrates one type of circuit implementation for the option. Other types of fuse option circuits may be provided.

FIG. 59Iillustrates one of the laser fuse opt2circuits978as well as the interconnections between the reg pretest circuit983and the laser fuse opt2circuits978-982. The circuitry used to implement the laser fuse opt2circuit978may be used to implement the circuits979-982.

FIG. 59Jis an example of how the 4k logic circuit985may be implemented. The 4k logic circuit produces signals which are ultimately used by the voltage supplies of the chip to determine the amount of power which must be produced. For example, recall that the 4k signal is input to the pump circuits413-415comprising the secondary group423to control the operation of those pump circuits (see FIG.39).

The construction of the fuse ID circuit986is illustrated inFIGS. 59K and 59L. The fuse ID circuit may be comprised of eight multibit banks. The banks may be used to store unique information about the part such as part number, position on the die, etc.

Finally,FIGS. 59M and 59Nillustrate the details of one implementation of the DVC2E circuit987and the DVC2GEN circuit988, respectively.

Completing the description of the block diagram illustrated inFIG. 43, the spare circuit660is shown in detail in FIG.590and the miscellaneous signal input circuit662is illustrated in detail in FIG.59P. The spare circuit660illustrates various additional components which may be fabricated to provide spares for repair purposes. The miscellaneous signal input circuit662illustrates a plurality of pads at which signals may be input or available.

IX. Global Sense Amp Drivers

The global sense amp driver29illustrated inFIG. 3Cis illustrated in block diagram form in FIG.60. As seen inFIG. 3C, a substantial number of signals generated by the right logic19are input, vertically as shown inFIG. 3C, into global sense amp driver29. It is the function of global sense amp driver29to reorient those signals 90° and in some cases decode or produce signals therefrom for input to the circuits in the horizontal space existing between the rows of individual 256K arrays50making up left 32 Meg array block25and right 32 Meg array block27. The global sense amp drivers35,42, and49are identical in construction and operation to the global sense amp driver29such that only one will be described.

As shown in the block diagram ofFIG. 60, the global sense amp driver29is comprised of alternating row gap drivers990, of which there are seventeen, and sense amp driver blocks992, of which there are sixteen in this embodiment. The row gap drivers990determine which of the sixteen strips is enabled. An example of one type of sense amp driver block992which may be used in connection with the present invention is illustrated in FIG.61. An electrical schematic of one type of row gap driver990which may be used in connection with the present invention is illustrated in FIG.62. Those of ordinary skill in the art will recognize that many types of row gap drivers990and sense amp driver blocks992may be provided.

Sense amp driver block992includes an isolation driver994which receives an enable signal and a select signal to produce the ISO* signal used to drive the isolation transistors83shown in FIG.6C. The condition of the isolation driver994is controlled by the state of the enable signal.

The isolation driver994is illustrated in detail in FIG.63. The isolation driver994includes a control circuit995which is responsive to an internal signal1004generated by a detector circuit998. The control circuit995is also responsive to the enable signal ENISO and the select signal SEL32M. The control circuit995includes an enable circuit996, which ensures that all devices connected to the pumped potential are disabled when the isolation driver994is disabled. The detector circuit998monitors a first driver circuit999, which circuit includes a transistor1003, and generates the internal signal1004to deactivate the first driver circuit999when an output node1000is driven to the supply voltage. The detector circuit998includes a pull-down transistor1001to prevent latch-up. A second driver circuit1002is responsive to the internal signal1004produced by the detector circuit998to couple the output node1000to the pumped potential. In that manner, latch up within the isolation driver994is prevented when the isolation driver is disabled.

X. Right and Left Logic

FIGS. 64A,64B,65A, and65B are high level block diagrams illustrating the right and left logic19and21, respectively, of the present invention. The right logic19and left logic21are each associated with two 64 Meg array quadrants. As illustrated above inFIG. 2, the right logic19is associated with array quadrants14and15and the left logic21is associated with array quadrants16and17. The right and left logic19and21are very similar to each other in both construction and operation. The right logic19is comprised of a left side and a right side, illustrated inFIGS. 64A and 64B, respectively. The sides are not identical because, as described below, some functions are performed for both sides by a single circuit.

As illustrated inFIG. 64A, the left side of the right logic19includes a 128 Meg driver block A1010and a 128 Meg driver block B1012, each of which drive signals used by many circuits in the right logic19. The architecture of the present invention allows for a clock-tree distribution of control signals, with some signals being redriven several times. The 128 Meg driver block A1010receives and drives predecoded row address signals RAnm<0:3>, ODD and EVEN signals, and control signals, such as ISO* and EQ*, for the sense amp elements. The 128 Meg driver block A1010is illustrated in detail in FIG.66.

FIG. 67is a block diagram of the 128 Meg driver block B1012, which includes a row address driver1014for driving additional predecoded row address signals RA910<0:3> and RA1112<0:3>, and column address delay circuits1016for delaying predecoded column address signals CAnm<0:3>. The column address signals are delayed to allow time to determine if a redundant column should be fixed. Details of the row address driver1014and column address delay circuits1016are illustrated inFIGS. 68A and 68B, respectively.

Referring back toFIG. 64A, the right logic19includes a number of decoupling elements1017. A decoupling element1017, illustrated in detail inFIG. 69, may be embodied as two decoupling capacitors44together with an associated transistor1019. The decoupling elements1017are distributed around the right logic19to stabilize voltage levels and to prevent localized voltage fluctuations. Generally, the concentration of decoupling elements1017in a given region of the right logic19is proportional to the power consumption in that region. If too few decoupling elements1017are present, power levels will fluctuate as components turn on and off, and power levels will vary from one location to another.

The right logic19also includes four global column decoders1020-1023, one for each 32 Meg array block associated with the right logic19. The 32 Meg array blocks are discussed in detail hereinabove in Section II. Closely associated with each global column decoder1020-1023is a column address driver block1026-1029, and an odd/even driver1032-1035, respectively. Associated with the column decoders1020,1021are a column address driver block21038and a column redundancy block1042; associated with the column decoders1022,1023are a column address driver block21039and a column redundancy block1043.

The odd/even drivers1032-1035drive signals ODD and EVEN to circuits in the global column decoders1020-1023. One of the odd/even drivers1032is illustrated in detail in FIG.70. Signal SEL32M<n> enables the odd/even drivers1020-1023and is indicative of whether the 32 Meg array block associated with the odd/even drivers1020-1023is enabled.

Each column address driver block1026-1029determines whether the 32 Meg array block associated with it is enabled. If the 32 Meg array block is enabled, an enable signal is provided to the column address driver block21038,1039and column address signals are provided to the global column decoders1020,1021or1022,1023, respectively. If the 32 Meg array block is not enabled, the column address driver block1026-1029discontinues the column address signals. The column address driver blocks1026-1029are discussed in more detail below in conjunction with FIG.74.

Each side of the right logic19includes only one column address driver block2. Column address driver block21038is responsive to enable signals from the column address driver blocks1026,1027, and column address driver block21039is responsive to enable signals from the column address driver blocks1028,1029. Only one enable signal is required to enable each column address driver block21038,1039. Once enabled, they provide column address data to the column redundancy blocks1042,1043, respectively. The column address driver block21038and1039are discussed in more detail below in conjunction with FIG.76.

Only two column redundancy blocks1042,1043are present in the entire right logic19, one in the left side and one in the right side. Each of the column redundancy blocks1042,1043is associated with two 32 Meg array blocks and two global column decoders1020,1021and1022,1023, respectively. The column redundancy blocks1042,1043receive column address signals from the column address driver block21038,1039, respectively, and determine whether the columns being accessed have been replaced with redundant columns. Information regarding redundant columns is provided to the appropriate global column decoder1020,1021in the case of column redundancy block1042, and the appropriate global column decoder1022,1023in the case of column redundancy block1043. The column redundancy blocks1042,1043are discussed in more detail below in conjunction with FIG.78.

The global column decoders1020-1023receive information regarding redundant columns, column address signals, and row address signals, and provide address signals to the 32 Meg array blocks. The global column decoders1020-1023are discussed in more detail below in conjunction with FIG.82.

The right logic19also includes four row redundancy blocks1046-1049, one for each 32 Meg array block. The row redundancy blocks1046-1049, in a manner analogous to the column redundancy blocks1042-1043, determine whether a row address has been logically replaced with a redundant row and produce output signals indicative thereof. The output signals from the row redundancy blocks1046-1049are driven by row redundancy buffers1052-1055, respectively, and are also provided, via topo decoders1058-1061, respectively, to the datapath1064. The datapath1064is discussed in more detail hereinabove in Section IV.

The right logic19includes certain of the Vccp pump circuits403, the Vbb pump280, and four DVC2generators504,505,506, and507, one for each 32 Meg array. The Vccp pump circuits are described in conjunction withFIG. 39, the Vbb pump280is described in conjunction withFIG. 37, and the DVC2generators are described in conjunction withFIG. 41, hereinabove.

The right logic19also includes array V switches1080-1083and associated array V drivers1086-1089, respectively.FIG. 71Aillustrates one of the array V drivers1086-1089. The array V drivers1086-1089are comprised primarily of two level translators1094and1095and two inverters1096and1097. The array V drivers1086-1089translate signals to levels high enough to drive the array V switches1080-1083, respectively. The array V drivers1086-1089each drive one of the signals SEL32M*<2:5> to a corresponding array V switch1080-1083, respectively. Each of the array V drivers1086-1089also produces one of the signals ENDVC2<2:5> and provides it to an associated array V switch1080-1083, respectively. Signals SEL32M*<2:5> are indicative of whether each of the four 32 Meg array blocks associated with the right logic19is enabled. Each one of the signals ENDVC2L<2:5> is indicative of whether an associated one of the DVC2generators504,505,506, and507is enabled. Each of the array V switches1080-1083, one of which is shown in detail inFIG. 71B, receives one of the signals SEL32M*<n>, and produces one of the signals Vccp<n>. Similar functionality can be used to switch the voltage Vcca.

FIG. 72Aillustrates the details of the DVC2switch1066shown in FIG.64B. The DVC2switch1067may be implemented in the same manner as the switch1066. The DVC2switches1066,1067receive signals AVC2<2:5> and DVC2<2:5>, respectively. Because both DVC2switches1066,1067are identical in construction but receive different signals,FIG. 72Auses signal DVC2I<0:3> to represent signal AVC2<2:5> in the case of DVC2switch1066. In the case of DVC2switch1067, signal DVC2<2:5> is used. The DVC2switches1066,1067are responsive to signals SEL32<n> and DVC2OFF, and can connect signals DVC2I<n> to DVC2PROBE. DVC2PROBE is connected to a probe pad and can be measured with a probe, for example, during testing of the DRAM. DVC2PRIBE is connected to ground when not in a test mode.

FIG. 72Billustrates the details of the DVC2up circuit1069and DVC2down circuit1070illustrated in FIG.64B. The circuits1069and1070regulate the voltage level of the voltage DVC2received by the DVC2switch1066in response to signals DVC2up and DVC2down, respectively. When the voltage DVC2is too high, the signal DVC2down turns on the transistor in circuit1070which tends to pull the voltage DVC2to ground. Conversely, when the voltage DVC2is too low, the signal DVC2up turns on the transistor in circuit1069which tends to pull the voltage DVC2up toward the voltage Vccx.

The right logic19includes a DVC2NOR circuit1092, illustrated in detail in FIG.73. The DVC2NOR circuit1092logically combines signals DVC2OK*<n> generated by the four DVC2generators504,505,506, and507. Logic gate1073produces a signal indicative of all of the DVC2generators being good while logic gate1072produces a signal if any of the DVC2generators is good. Switches1074are set to conduct the desired DVC2OK signal to an output terminal of circuit1092.

Some of the components identified above will now be described in more detail. Unless stated otherwise, the following description is made with respect to the left side of the right logic19, which is illustrated in FIG.64A. In particular, the description is made with respect to the components located in the bottom portion ofFIG. 64A, associated with the 32 Meg array block31on the left side of quadrant15, as illustrated in FIG.2. As with the electrical schematics and wiring diagrams previously shown, the following electrical schematics and wiring diagrams are being provided for exemplary purposes and not for limiting the claims to any particular preferred embodiment.

FIG. 74is a block diagram of the column address driver block1027illustrated in FIG.64A. The column address driver block1027includes an enable circuit1110, a delay circuit1112, and five column address drivers1114. The enable circuit1110determines whether the 32 Meg array block31is enabled and generates signals32MEGEN and32MEGEN*. Signal32MEGEN is output to enable the column address driver block2,1038and signal32MEGEN* is provided to the delay circuit1112and eventually enables the column address drivers1114. The delay is needed to determine if a redundant column should be fired. Once the column address drivers1114are enabled, they drive the column address signals CAnm*<0:3> for use by the global column decoder1021.

FIG. 75Aillustrates the enable circuit1110for producing signals32MEGEN* and32MEGEN.FIG. 75Billustrates the delay circuit1112as a series of inverters which delay the propagation of the signal32MEGEN*. The delay is increased by capacitors connected to an output terminal and an input terminal of two series connected inverters. The delay circuit1112produces a signal EN* for enabling the column address drivers1114. The purpose of the delay circuit1112is to prevent the column address drivers1114from being enabled before the column redundancy can evaluate a new column address.

FIG. 75Cillustrates one of the column address drivers1114. Each column address driver1114receives column address signals CAnm*<0:3>, is enabled by signal EN*, and produces output signals LCAnm*<0:3> input to the global column decoder1021.

FIG. 76illustrates a block diagram of the column address driver block21038which services the entire left side of the right logic19. The column address driver block21038drives column address signals CAnm<0:3> to the column redundancy block1042. The column address driver block21038includes a NOR gate1120and five column address drivers1122. The NOR gate1120receives signals32MEGENa and32MEGENb from column address driver blocks1026and1027, respectively, and produces an enable signal EN* for the column address drivers1122. If either of signals32MEGENa and32MEGENb is a logic high, the NOR gate1120will enable the column address drivers1122.

FIG. 77illustrates one of the column address drivers1122. Each column address driver1122receives column address signals CAnm*<0:3>, is enabled by signal EN* from the NOR gate1120, and produces output signals LCAnm*<0:3> input to the column redundancy block1042.

FIG. 78is a block diagram of the column redundancy block1042. The column redundancy block1042services both the top and bottom portions of the left side of the right logic19and is comprised of two sets of eight identical column banks1130. The first set1132of eight column banks1130serves global column decoder1020and the second set1134of eight column banks1130serves global column decoder1021. The purpose of the column redundancy block1042is to determine whether a column address matches a redundant column address. Such matching will occur whenever a column has been logically replaced with a redundant column.

FIG. 79is a block diagram of one of the column banks1130shown in FIG.78. The column bank1130includes four column fuse blocks1136-1139. All of the column fuse blocks1136-1139may be programmed by opening fuses with a precision laser, and one of the column fuse blocks1136may also be programmed electrically. The column fuse blocks1136-1139receive column address signals and produce column match signals CMAT*<0:3> which are indicative of a match between a column address and a redundant column. The CMAT* <0:3> signals cancel column select signals CSEL produced by the global column decoder1021, and enable redundant column select signals RCSEL.

FIG. 80Ais a block diagram of the column fuse block1136shown in FIG.79. The column fuse block1136contains four column fuse circuits1144, each of which receives column address signals CAnm*<0:3> and produces a column address match signal CAM* indicative of whether the column address signals match a portion of a redundant column address. An enable circuit1146produces an enable signal EN indicative of whether the column fuse block1136is enabled. The output signals CAM* and the enable signal EN* are combined in output circuit1148to produce a column match signal CMAT*, indicative of whether there is a match between a column address and a redundant column. Details of the output circuit1148are illustrated in FIG.80B.

FIG. 80Cillustrates the details of one of the columns fuse circuits1144shown in FIG.80A. The column fuse circuit1144contains two fuses which may be opened to represent two bits of a redundant column address. Associated with each fuse is a latch, comprising two inverters in a feedback loop. Once enabled by column fuse power signals CFP and CFP* generated by the enable circuit1146, the latches read the fuses and latch the data. The latches are generally enabled on powerup and during RAS cycles. The data in the latches is predecoded into true and complement signals and provided, along with the column address signals CAnm*<0:3>, to comparator logic for producing signal CAM*.

FIG. 80Dillustrates details of the enable circuit1046shown in FIG.80A. The enable circuit1046contains two fuses, one for enabling the fuse block1136, and one for subsequently disabling the fuse block1136in the event the fuse block1136itself becomes defective. The enable circuit1046feeds the column fuse power signals CFP and CFP* for the column fuse circuits1144and a feedback signal EFDIS<n> indicative of whether the fuse block1136is disabled.

Referring back toFIG. 79, column electric fuse circuits1150and a column electric fuse block enable circuit1152provide signals to the electrically programmable column fuse block1136. A fuse block select circuit1154receives the column address signals CAnm*<0:3> and produces a fuse block select signal FBSEL* indicative of whether the fuse blocks1136-1139are enabled. A CMATCH circuit1156receives the signals CMAT*<0:3> from the column fuse blocks1136-1139and produces signals CELEM and CMATCH* indicative of whether there is a match between a column address and a redundant column. Details of the column electric fuse circuits1150, column electric fuse block enable circuit1152, fuse block select circuit1154, and CMATCH circuit1156are illustrated inFIGS. 81A,81B,81C, and81D, respectively.

FIG. 82is a block diagram of the global column decoder1021shown in FIG.64A. The global column decoder1021includes four groups of column drivers, with each group having two column decode CMAT drivers1160,1161and one column decode CA01driver1164. Each group of column CMAT drivers1160,1161and column decode CA01driver1164provides signals to a pair of global column decode sections1170,1171. The global column decoder1021also includes nine row driver blocks1166. Each row driver block1166drives row address data to produce row address signals nLRA12<0:3>, nLRA34<0:3>, and nLRA56<0:3> for use by the 32 Meg array block31.FIG. 83Aillustrates the details of one of the row driver blocks1166.

Each pair of column decode CMAT drivers1160,1161are enabled by one of signals CA1011*<0:3> and collectively drive eight of the CMAT*<0:3> signals. Each of the column decode CA01drivers1164is enabled by two of the signals CELEM<0:7> and each drives the signals CA01*<0:3>.FIGS. 83B and 83Cillustrate the details of one of the column decode CMAT drivers1160and one of the column decode CA01driver1164, respectively.

Each of the global column decode sections1170,1171are enabled by signals LCA01<0:3> and further predecode a group of column address signals to produce132column select signals CSEL for use by the 32 Meg block array31. A total of 1056 column select signals CSEL<0:1055> are generated by all of the global column decode sections.

FIG. 83Dis a block diagram of one of the global column decode sections1170. The global column decode section1170is comprised of a plurality of column select drivers1174and R column select drivers1176.

FIGS. 84A and 84Billustrate one of the column select drivers1174and R column select drivers1176, respectively, found in the global column decode sections1170,1171.

FIG. 85is a block diagram of the row redundancy block1047illustrated in FIG.64A. The row redundancy block1047includes eight identical row banks1180for comparing a portion of a row address RAnm<0:3> to a portion of a redundant row address and for producing row match signals RMAT indicative of a match. Redundant logic1182logically combines the RMAT signals and produces output signals indicative of whether the row address RAnm<0:3> has been replaced with a redundant row. The redundant logic1182is shown in detail in FIG.86.

InFIG. 86, the redundant logic1182receives the row match signals RMAT <n>. A node1183is charged to a high level. If any of the RMAT signals goes high, the node1183is discharged which is captured in a latch. If the signal ROWRED <n> stays low, then there is no redundancy match. Under those circumstances, the normal row is used. If the signal ROWRED <n> goes high, then one of the redundancy rows is to be used and the particular signal which goes high identifies the phase to be fired.

The redundant logic1182also receives the fuse address latch signal FAL which is combined with other signals to produce the RMATCH* signal, which is used for programming. The redundant logic1182also receives all of the ROWRED signals and combines them to produce a signal RELEM* which indicates that there is a match somewhere in the redundant logic. That signal is used to create the redundant (RED) signal.

FIG. 87is a block diagram of one of the row banks1180illustrated in FIG.85. The row bank1180includes one row electrical block1186which may be programmed either electrically or with a precision laser, and three row fuse blocks1187-1189which may be programmed only with a precision laser. The row electrical block1186and row fuse blocks1187-1189receive row address signals RAnm<0:3> and produce output signals RMAT<0:3> indicative of whether a row address matches a redundant row. Rsect logic1192receives the signals RMAT<0:3> and produces a signal RSECT<n> indicating which array section has a redundant match. The details of the rsect logic1192are illustrated in FIG.88.

FIG. 89is a block diagram of the row electric block1186illustrated in FIG.87. The row electric block1186includes six electric banks1200-1205which receive row address signals and produce signals RED* indicative of whether there is a match between a row address and a redundant row. The addresses of redundant rows are represented electrically by signals EFnm<0:3>. A redundancy enable circuit1208is programmable with fuses to enable and disable the row electric block1186, and to produce a signal PR to enable the electric banks1200-1205and an electric bank21210. A select circuit1212and the electric bank21210receive row address signals and produce signals G252and RED*, respectively, indicative of whether the row electric block1186is enabled. Like the electric banks1200-1205, the electric bank21210compares row address data, represented by signals EVEN and ODD, to electrical signals EFeo<0:1>. An output circuit1214receives signals RED* from the electric banks1200-1205and signals G252and RED* from the select circuit1212and the electric bank21210, and produces row match signal RMAT indicative of whether there is a match between a row address and a redundant row. Details of one of the electric banks1200, the redundancy enable circuit1208, the select circuit1212, the electric bank21210, and the output circuit1214, are illustrated inFIGS. 90A,90B,90C,90D, and90E, respectively.

FIG. 91is a block diagram of one of the row fuse blocks1187illustrated in FIG.87. The row fuse block1187includes fuse banks1220-1225, a fuse bank21228, a redundancy enable circuit1230, a select circuit1232, and an output circuit1234. The components of the row fuse block1187are identical to the row electric fuse block1186, except that redundant rows are represented by fuses in the fuse banks1220-1225and fuse bank21228of the row fuse block1187, rather than with electrical signals EFnm<0:3> and EFeo<0:1> in the row electric banks1200-1205and row electric bank21210of the row electric block1186. Details of one of the fuse banks1220, the redundancy enable circuit1230, the select circuit1232, fuse bank21228, and the output circuit1234are illustrated inFIGS. 92A-92E, respectively.

Referring back toFIG. 87, row electric pairs1240-1245and a row electric fuse1248provide signals EFnm<0:3> representing a redundant row address to the row electrical block1186. The row electric pairs1240-1245and row electric fuse1248are enabled by fuse block select signal FBSEL* produced by input logic1250, shown in more detail in FIG.93A. The row electrical block1186is enabled by signal EFEN, produced by row electric fuse block enable circuit1252illustrated in detail in FIG.93B.

FIG. 93Cillustrates the row electric fuse1248shown in FIG.87. The row electric fuse1248includes an antifuse that can be shorted electrically by applying a high voltage at signal CGND. The data stored in the antifuse is output as predecoded signals EFB*<0> and EFB<1>.

FIG. 93Dillustrates one of the row electric pairs1240shown in FIG.87. The row electric pairs1240-1245each store two bits of data, a most significant bit and a least significant bit, and include two independent and identical circuits, one for the most significant bit and one for the least significant bit. Each of the circuits store its bit of data with an antifuse that can be shorted by applying a high voltage at signals CGND. The row electric pairs1240-1245also include a predecode circuit for producing predecoded signals EFnm<0:3>.

Referring briefly back toFIG. 64A, the output of the row redundancy block1047is driven by the row redundancy buffer1053, illustrated in detail in FIG.94. The output of the row redundancy buffer1053is also input to the topo decoder1059, illustrated in FIG.95. The topo decoder1059produces signals TOPINVODD, TOPINVODD*, TOPINVEVEN, and TOPINVEVEN* which are input to the datapath1064.

The left logic21, illustrated inFIGS. 65A and 65B, is nearly identical to the right logic19. Generally, components in the left logic21use the same reference numbers, followed by a prime symbol “′”, as functionally-identical components in the right logic19. Exceptions to the numbering scheme are made for the Vccp pump circuits402and the DVC2generators500,501,502, and503, which were introduced and are described in more detail in Section VII.

The left logic21differs from the right logic19in that the left logic21does not include a Vbb pump280. Furthermore, the left logic21does include a data fuse id1260, which is not present in the right logic19. The data fuse id1260drives fuse id data through the datapath1064′ to one or more data pads.FIG. 96illustrates the details of the data fuse id1260. The data used in the data fuse id circuit1260comes from the center logic.

XI. Miscellaneous Figures

FIG. 97illustrates the data topology of one of the 256K arrays50shown inFIG. 4which is constructed in accordance with the teachings of the present invention. The array50is constructed from a plurality of individual memory cells1312, all of which are constructed in a similar manner.

FIG. 98illustrates the details of one of the memory cells1312. Each memory cell1312includes first and second transistor/capacitor pairs1314,1315. Each of the transistor/capacitor pairs1314,1315include a storage node1318,1319, respectively. A contact1320, shared by the two transistor/capacitor pairs1314,1315, connects the transistor/capacitor pairs1314,1315to the wordlines WL<n>.

Referring back toFIG. 97, the memory array50has wordlines WL<n> running horizontally and digitlines DIGa<n>, DIGa*<n>, DIGb<n>, and DIGb*<n> running vertically. The wordlines WL<n> overlay active areas of the transistor/capacitor pairs1314,1315and determine whether transistors in the transistor/capacitor pairs1314,1315are in a conductive or a non-conductive state. The wordline signals originate from row decoders located to the left and right of the memory array10. The memory array10has512live wordlines WL<0:511>, two redundant wordlines RWL<0:1> located on the bottom of the memory array50, and two redundant wordlines RWL<2:3> located on the top of the memory array50. The redundant wordlines may be logically substituted in place of defective wordlines. The digitlines are organized in pairs, with each pair representing a true and a complement value for the same bit of data in the array50. The digitlines carry data into or away from the digital contact1320, and connect the digital contact1320to sense amps located on the top and bottom of the memory array50. There are 512 digitline pairs in the memory array, with an additional 32 redundant digitline pairs.

The wordlines are preferably constructed of polysilicon while the digitlines are preferably constructed of either polysilicon or metal. Most preferably, the wordlines are constructed of polysilicon that is silicided to reduce resistance and heat to thereby permit longer wordline segments without reducing speed. The storage nodes1318may be constructed with an oxide-nitride-oxide dielectric between two polysilicon layers.

FIG. 99is a state diagram1330illustrating the operation of a powerup sequence circuit1348(shown inFIG. 100) which may be used to control the powering up of the various voltage supplies and associated components of the chip10. The state diagram1330includes a reset state1332, a Vbb pump powerup state1334, a DVC2generator powerup state1336, a Vccp pump powerup state1338, a RAS powerup state1340, and a finish powerup sequence state1342. The Vbb pumps, the DVC2generators, and the Vccp pumps are discussed hereinabove in Section VII.

When power is first applied to the chip10, the powerup sequence circuit1348begins in the reset state1332. The purpose of the reset state1332is to wait for the externally supplied voltage Vccx to reach a third predetermined value preferably below the first predetermined value shown inFIG. 36B, before allowing the powerup sequence to begin. Once Vccx exceeds that third predetermined value, the sequence circuit1348proceeds to the Vbb powerup state1334. If Vccx ever falls below the third predetermined value, the sequence circuit1348will return to the reset state1332.

The purpose of the Vbb powerup state1334is to wait for the back bias voltage Vbb, provided by Vbb pumps280, to reach a predetermined value, preferably −1 volt or less, before proceeding with powering up additional voltage supplies. The Vbb pumps280are automatically activated when Vccx begins to rise, and they are usually still running when the sequence circuit1348reaches the Vbb powerup state1334. When the voltage Vbb has reached its predetermined state, the Vbb pumps280turn off and the sequence circuit1348leaves the Vbb powerup state1334and proceeds to the DVC2powerup state1336.

The purpose of the DVC2powerup state1336is to wait for the voltage DVC2to reach a predetermined state before proceeding with powering up additional voltage supplies. That may mean waiting for all the DVC2generators to reach a steady state or just one depending upon how the switches74are set in the DVC2NOR circuit1092shown in FIG.73. When the voltage DVC2has reached a predetermined state, and assuming that the voltages Vccx and Vbb are each in their desired respective predetermined states, the sequence circuit1348proceeds from the DVC2powerup state1336to the Vccp powerup state1338.

The purpose of the Vccp powerup state1338is to wait for the voltage Vccp to reach a predetermined state, preferably above approximately Vcc plus 1.5 volts. Before voltage Vccp can reach its predetermined state, however, voltage Vcc must be in its predetermined state. Vcc usually does not delay the Vccp powerup state because, as mentioned above, Vcc is powered up during the reset state1332. Once the voltage Vccp has reached its predetermined state, and assuming that the voltages Vccx, Vbb, and DVC2are each in their desired respective predetermined states, the sequence circuit1348proceeds from the Vccp powerup state1338to the RAS powerup state1340.

The purpose of the RAS powerup state1340is to provide power to the RAS buffers745(shown in FIG.46). The sequence circuit1348then proceeds to a finish powerup sequence state1342where it remains until Vccx falls below the third predetermined value. At that time, the sequence circuit1348returns to the reset state1332and waits for Vccx to return to the third predetermined value.

FIG. 100is a block diagram of one example of a powerup sequence circuit1348constructed to implement the functionality of the state diagram1330illustrated inFIG. 99. Avoltage detector1350receives the externally supplied voltage Vccx and generates an output signal UNDERVOLT* indicative of whether Vccx is above the third predetermined value, preferably approximately two volts.FIG. 101Ais an electrical schematic illustrating one example of a voltage detector1350which may be used. The voltage detector1350includes a pair of parallel-connected resistors, one of which is optioned out, in series with series-connected pMOS transistors to form a first voltage limiting circuit1352responsive to Vccx. The first voltage limiting circuit1352produces a first threshold signal VTH1seen inFIG. 101Bat a junction between the resistors and the pMOS transistors. The first threshold signal VTH1is used to gate a transistor of a first signal generating circuit1354which produces a signal VSW when Vccx is above a fourth predetermined value, preferably approximately 2.0 volts.

The voltage detector1350also includes a second voltage limiting circuit1356and a second signal generating circuit1358which are constructed and function in an analogous manner to the first voltage limiting circuit1352and the first signal generating circuit1354, respectively. The second voltage limiting circuit1356is constructed of series-connected nMOS transistors and a resistors, one of which is optioned out. The circuit1356is responsive to Vccx and produces a second threshold signal VTH2seen in FIG.101C. The second signal generating circuit1358is constructed of an nMOS transistor and a pair of parallel-connected resistors, is responsive to Vccx and VTH2, and produces a second signal VSW2indicative of whether Vccx is above the fourth predetermined value.

The signals VSW and VSW2from the first and second signal generating circuits1354,1358, respectively, are logically combined in a logic circuit1360to produce the UNDERVOLT* signal indicative of whether both first and second signal generating circuits1354,1358indicate that Vccx is above the fourth predetermined value.

The voltage detector1350contains two pair of substantially identical circuits to compensate for fabrication variances that may cause either nMOS devices or pMOS devices to operate in a different manner than anticipated. Such variances, if they occur, will likely cause one of the voltage limiting circuits1352,1356or one of the signal generating circuits1354,1358to trigger sooner than expected, thereby prematurely indicating that Vccx is above the fourth predetermined value. If that happens, the sequence circuit1348may begin to operate before Vccx can reliably support operation of the circuits, potentially resulting in errors. However, because the logic circuit1360requires that both signal generating circuits1354,1358indicate Vccx is above the fourth predetermined value before UNDERVOLT* is produced in a high logic state, an error by any one of the circuits1352,1354,1356,1358will not adversely affect the performance of the voltage detector1350. It is, of course, possible that a fabrication variance will cause one of the circuits1352,1354,1356,1358to trigger too late, delaying one of the signals VSW or VSW2. That type of variance, however, is more easily corrected and, in any event, will not result in the sequence circuit1348operating without sufficient voltage. Other types of logic circuits1360may be used to effect different results, e.g., production of the UNDERVOLT* signal when only one of the signals VSW and VSW2is available.

FIG. 101Dis an electrical schematic illustrating one example of the reset circuit1362which may be used. The reset logic1362receives the UNDERVOLT* signal and generates a signal CLEAR* indicative of whether UNDERVOLT* is stable. In the preferred embodiment, the reset circuit1362determines that Vccx is stable if it is above two volts for at least a predetermined period of time, approximately 100 nanoseconds. The reset circuit1362includes a number of series-connected delay circuits1363responsive to the signal UNDERVOLT*. The number of delay circuits1363, and the propagation delay associated with each one, largely determines the predetermined period of time that Vccx must be above two volts before the reset circuit1362determines that Vccx is stable. The reset circuit1362also includes a reset logic gate, comprised of an inverter responsive to the signal UNDERVOLT* for producing a reset signal RST to reset the delay circuits1363. When the UNDERVOLT* signal goes to a low logic state, indicating that Vccx is less than the first predetermined value, the reset logic gate generates a high logic state signal that discharges a capacitor in the delay circuits1363as shown in FIG.101E. By discharging the capacitor, the delay is always the same. If a power “glitch” is relied upon to discharge the capacitor, the glitch might not be long enough to completely discharge the capacitor. Under such cases, the delay time would become unpredictable.

The reset logic1362also includes a logic circuit comprising a NAND gate and an inverter that are responsive to both the UNDERVOLT* signal and to an output signal from the last delay circuit1363. If both the UNDERVOLT* signal and the output signal from the last delay circuit1363are in a high logic state, then the logic circuit will generate a CLEAR* signal in a high logic state, indicating that Vccx is stable. If, however, the UNDERVOLT* signal goes to a low logic state at any time, the delay circuits1363will be reset and the logic circuit will generate the CLEAR* signal in a low logic state, indicating that Vccx is not stable. The CLEAR* signal will remain in a low logic state until the UNDERVOLT* signal remains in a high logic state long enough for a signal to propagate through the delay circuits1363and through the logic circuit. The reset logic1362is used in the preferred embodiment to prevent the sequence circuit1348from proceeding beyond the reset sequence state1332(shown inFIG. 99) before Vccx is both above the desired predetermined value and stable. The reset logic1362, however, is not required for the sequence circuit to implement the functionality of the state diagram1330illustrated in FIG.99.

A state machine circuit1364shown inFIG. 100receives the CLEAR* signal from the reset logic1362, and also receives other signals indicative of the state of Vbb, DVC2, and Vccp. The state machine circuit1364performs the functions illustrated in the state diagram shown inFIG. 99, as will be described in more detail below.

An alternative to the powerup sequence circuit1348is RC timing circuits1368,1369. RC timing circuits1368,1369generate powerup signals based only on the passage of time since the application of the externally supplied voltage Vccx, and they do not receive feedback signals. The RC timing circuits1368,1369are provided as an alternative to the sequence circuit1348, but they are not required for the sequence circuit1348to operate. FIG.101F andFIG. 101Gare electrical schematics illustrating one embodiment of the RC timing circuits1368,1369, respectively.

Output logic1372receives output signals from both the state machine circuit1364and the RC timing circuits1368,1369. The output logic uses only one set of output signals, either from the state machine circuit1364or from the RC timing circuits1368,1369. A STATEMACH* signal received by the output logic1372determines which set of output signals are used by the output logic1372.FIG. 101Hillustrates an electrical schematic of one embodiment of the output logic1372comprising a number of multiplexers controlled by the STATEMACH* signal.

Bond option1374allows for a selection between the use of the state machine circuit1364or the use of the RC timing circuits1368,1369. That selection is made, for example, by opening or not opening a fuse within the bond option1374so as to generate the STATEMACH* signal for use by the output logic1372.FIG. 101Iillustrates an electrical schematic of one embodiment of the bond option1374.

FIG. 101Jis an electrical schematic of one embodiment of the state machine circuit1364shown inFIG. 100. ANOR gate1379receives the VBBON and VBBOK* signals and generates a VBBOK2signal, which is provided along with a CLEAR* signal to a spare circuit1388. The spare circuit1388is provided to allow for modifications of the DRAM in the event an additional powerup state is desired at a later time. If the CLEAR* signal is in a high logic state, the VBBOK2signal is passed through the spare circuit1388and provided to a DVC2enable circuit1380. If the CLEAR* signal is in a low logic state, the spare circuit1388generates a low logic signal for the DVC2enable circuit1380, indicating that Vccx is not stable. The DVC2enable circuit1380also receives the CLEAR* signal, and generates a DVC2EN* signal to enable the DVC2generators500when the above-described conditions are met. Signals DVC2OKR and DVC2OKL are indicative of whether DVC2is determined to be within a predetermined range in the right and left logic19,21, respectively. A NAND gate1377, whose output is coupled to an inverter1378, logically combines the DVC2OKR and DVC2OKL signals to produce the DVC2OK signal indicative of whether DVC2is determined to be within a predetermined range in both the right and left logic19,21.

A Vccp enable circuit1382receives the CLEAR*, VBBOK2, and DVC2OK signals and generates the VCCPEN* signal to enable the Vccp pumps400when the above-described conditions are met. An inverter1383converts the VCCPON signal into its complement, VCCPON*. A power RAS circuit1384receives the CLEAR*, VBBOK2, DVC2OK, and VCCPON* signals and generates the PWRRAS* signal to enable the RAS buffers745when the above-described conditions are met. A RAS feedback circuit1366receives a PWRRAS* signal and generates a RASUP signal indicative of whether the RAS buffers have been enabled.

A powered up circuit1386receives the CLEAR*, VBBOK2, DVC2OK, VCCPON*, and RASUP signals and generates the PWRDUP and PWRDUP* signals to indicate that the chip10has reached a powered up state when the above-described conditions are met. Each of the circuits1380,1382,1384,1386,1388are comprised of a NAND gate receiving various signals and a latch that is reset by the CLEAR* signal when Vccx is determined to be unstable.

FIGS. 102A-102Kare simulations of timing diagrams illustrating the signals associated with the powerup sequence circuit1348.FIG. 102Aillustrates Vccx as it ramps steadily upward as more external power is applied.

FIG. 102Billustrates the UNDERVOLT* signal, which changes state from a low to a high logic state to indicate when the voltage Vccx has reached or exceeded the first predetermined value.

FIG. 102Cillustrates the CLEAR* signal, which is responsive to the UNDERVOLT* signal and changes state from a low to a high logic state after the UNDERVOLT* signal has been in a high logic state for a predetermined period of time, preferably approximately 100 nanoseconds. The CLEAR* signal indicates that the externally supplied voltage Vccx is believed to be stable.

FIG. 102Dillustrates the VBBOK2signal. The VBBOK2signal falls from a high to a low logic state at a point in time indicated by reference number1390when the voltage Vbb reaches a predetermined state and the Vbb pumps280turn off.

FIG. 102Eillustrates the DVC2EN* signal, which is output from the sequence circuit1348to enable the DVC2generators500. As can be seen by comparingFIGS. 102D and 102E, the DVC2generators500are not enabled until the signal VBBOK2goes to a low logic state.

FIG. 102Fillustrates the DVC2OKR signal, which is indicative of whether the voltage DVC2is stable in the right logic. An analogous signal indicative of the whether the voltage DVC2is stable in the left logic, DVC2OKL, is provided to the sequence circuit1348illustrated inFIG. 100but is not shown in the timing diagram because, under normal circumstances, both DVCOKR and DVC2OKL react very similarly. The signal DVC2OKR does not indicate a stable state for the voltage DVC2until a time indicated by reference number1391.

FIG. 102Gillustrates the VCCPEN* signal, which is output from the sequence circuit1348to enable the Vccp pumps400. The signal VCCPEN* will not enable the Vccp pumps400until point1392, when the CLEAR* signal is high, the VBBOK2signal is low, and the DVC2OKR signal is high.

FIG. 102Hillustrates the VCCPON signal, which is indicative of whether the Vccp pumps400are on after the pumps have been enabled. Prior to that time, its state is irrelevant.

FIG. 102Iillustrates the PWRRAS* signal, which is output from the sequence circuit1348to provide power to the RAS buffers745. The PWRRAS* signal does not provide power to the RAS buffers745until a point in time indicated by reference number1393, when the CLEAR* signal is high, the VBBOK2signal is low, the DVC2OKR signal is high, and the VCCPON signal is low.

FIG. 102Jillustrates the RASUP signal, which is indicative of whether the RAS buffers745are receiving power.

FIG. 102Killustrates the PWRDUP* signal, which is output from the sequence circuit1348to indicate that the chip10has completed its powerup sequence. The PWRDUP* signal does not indicate completion of powerup until a point in time indicated by reference number1394, when the CLEAR* signal is high, the VBBOK2signal is low, the DVC2OKR signal is high, the VCCPON signal is low, and the RASUP signal is high.

If, at any time during the powerup sequence, the external voltage Vccx falls below the first predetermined value, the signal CLEAR* will go low and reset the sequence circuit1348, including the output signals DVC2EN*, VCCPEN*, PWRRAS, and PWRDUP*.

Referring toFIG. 103, a test mode entry timing diagram is illustrated. Supervoltage WCBR test modes require a vectored WCBR to load the supervoltage enable test key. That is followed by a second SVWCBR, to load the desired test key, but with the supervoltage applied to the N/C (no connect) pin. Testkeys may be entered on CA0-7, and the test mode will remain valid until the supervoltage is removed or the clear test mode key is asserted. Once the supervoltage enable test mode has been loaded into the DRAM, subsequent SVWCBRs will load in additional test modes. For example, if mode2(discussed below) is to be combined with mode4(discussed below), then 1 WCBR and 2 SVWCBRs are performed. The first WCBR will enable the supervoltage circuit and the next two SVWCBRs load in key2and key4(see FIG.103). To exit all selected test modes, including the supervoltage enable test mode, enter either the clear test mode key during a SVWCBR or drop the supervoltage on the N/C pin. All of the tests which can be performed on the DRAM are entered using this supervoltage test mode.

As shown inFIG. 103, two CAS before RAS cycles1270,1271are used. Cycles1270,1271correspond to edges1272,1273,1274and edges1275,1276,1277, of the write enable (WE*) signal, CAS* signal, and RAS* signal, respectively. During cycles1270,1271the address signal may provide address information for putting the chip10in a ready state and a test mode state, respectively. At time1280, which is after time1281when RAS* goes inactive, if the WLTON1signal goes inactive low, then a test mode operation may be entered provided the access voltage signal is at a supervoltage level.

According to the present preferred embodiment of the invention, the test modes which can be entered are as follows:

0. CLEAR—This testkey will disable all test modes previously entered by WCBR cycles, including the supervoltage enable.

1. DCSACOMP—This test mode provides 2× address compression without writing adjacent bits or crossing redundancy regions by compressing CA<12> on a ×8 4K part, CA<11> on a ×16 4K part, or RA<12> on any 8K part. This address compression combines the data from upper and lower 16 Meg array sections within a 32 Meg array. This test mode can be combined with other test modes.

2. CA9COMP—This test mode provides 2× address compression without writing adjacent bits but does cross redundancy regions by compressing CA<9>. This address compression combines the data from upper and lower 64 Meg quadrants. This test mode can be combined with other test modes.

3.32MEGCOMP—This test mode provides 2× address compression without writing adjacent bits but does cross redundancy regions by compressing CA<11> for a ×8 part (CA<10> for a ×16 8K part, CA<12> for ×4 8K part or RA<13> for any 16K part). This address compression combines the data from left and right 32 Megs within 64 Meg quadrants. This test mode can be combined with other test modes.

4. REDROW—This test mode allows independent testing of the row redundant elements. The addresses at RAS and CAS during subsequent cycles select the bits to be accessed. From the row pretest, if one of the hard-coded addresses used to select a redundant row is entered, the subsequent column addresses will be from this redundant row. The 32 redundant row banks per octant are hard-coded using row addresses RA0-6. For the standard 8K refresh, all 32 MEG octants will fire a redundant row. For the 8K-×4 part, CA9and CA12determine which octant is connected to the DQs. If both REDROW and REDCOL are selected, the row address selects one of the redundant row elements, while the column address selects either a normal or redundant column. This allows testing of crossing redundant bits. This test mode can be combined with DCSACOMP, CA9COMP,32MEGCOMP or CA10COMP test modes. Also see the descrition of “redundancy pretest” herein below.5. REDCOL—This test mode allows independent testing of column redundant elements. The column redundant elements use hard-coded addresses to enable them. While performing column pretest, the column address is fully decoded which permits testing redundant columns or any normal columns that don't match the hard-coded addresses. Since the 64 redundant column locations are fully decoded it requires all column addresses to select them. The redundant element crossing bits are tested if both REDROW and REDCOL are loaded. This test mode can be combined with DCSACOMP, CA9COMP,32MEGCOMP or CA10COMP test modes.

6. ALLROW—The RAS cycle following the selection of this test mode will latch all bits on the “seed” wordline selected by the row address. On each of the next 2 WE signal edges another ¼ of the rows within a 2 Meg section of each octant will be brought high. On the 3rd WE transition another quarter of the rows will be brought high and the DVC2generator will be disabled. The 4th WE transition will bring the last quarter of the rows high and will force DVC2high. After the 4th WE transition WE will control the voltage of DVC2. If WE is high then DVC2will be pulled to internal Vcc through a p-channel device; if WE is low DVC2will be pulled to GND. See FIG.104. Once RAS is brought low, the data stored in the memory cells will be corrupted since EQ will fire before all wordlines are low. When combining with other test modes, this must be the last WCBR entered. The ALLROW high test mode is described in greater detail hereinbelow in conjunction withFIGS. 104,108, and109.

7. HALFROW—Similar to the ALLROW test mode, HALFROW will Allow A0to control whether EVEN or ODD rows are brought high. All other functions of HALFROW are the same as ALLROW.

8. DISLOCK—This test mode disables the RAS and Write lockout circuit so that full characterization can be done.

9. DISRED—This test mode disables all row and column redundant elements.

10. FLOATDVC2—This test mode disables the AVC2and DVC2generators allowing the voltage on the cellplate and digitlines to be externally driven.

11. FLOATVBB—This test mode will disable the VBB pump and float the substrate.

12. GNDVBB—This test mode will disable the Vbb pump and ground the substrate.

13. FUSEID—This test mode allows access to 64 bits of laser and antifuse FuseID, 32 bits of data representing currently active test modes, and 24 bits representing the status of various chip options. All bits will be accessible through DQ<0>. These bits are accessed using row address <1:4> to select 1 of 16 banks and column address <0:7> to select 1 of 8 bits in each bank. Table 8 below lists the various FuseID banks. Currently the first 7 banks of FuseID are laser with bank7as the only antifuse bank.

FIG. 105illustrates the timing for reading out FUSEID information. After the RAS* signal goes low at time1284, a bank address1285is latched. Later, the CAS* signal goes low. Each CAS* cycle, while the RAS* signal is held low, is used for accessing bits. In the embodiment illustratively shown inFIG. 105, eight bits (B0to B7) per bank are accessed per read cycle1286. The WE* signal is held inactive high. Bits B0, B1, B2, . . . B7are latched for access prior to each CAS* cycle. In other words, transition times1287,1288,1289,1290of the address signal respectively lead transition times1291,1292,1293,1294of the CAS* signal. Each of bits B0through B7may then be provided to the data path and output.

Table 9 provides additional details of certain exemplary values which may be represented by banks0-7. A blown laser fuse in the fuse ID banks fires the DQ<1> output pin high. This is the case for banks <0:6> of fuse ID. In bank7antifuses are used and therefore a “blown” fuse will drive the DQ<1> output pin low. Note that the generic bits will contain both 8 antifuses and 2 laser fuses. Fuse ID data register fields will then be scrambled using standardized fuse ID bit #'s as follows:

TABLE 9FUSEID Specification# ofFuse ID bit #'sMaximumFusesLSB to MSBRangeUsed RangeEXPLANATION23#0-#220 to 83886070 to 53999997 digit fuse ID lot number “WWFSSSS” consisting of workweek WW (01-53), FAB digit F (1-9), and 4 digit waferscribe number SSSS, (0000-9999). Will match the lot numberon the traveler for non-bonus lots. For bonus lots, and off-linedatabase will have to map wafer scribe numbers to the travelerlot number.6#23-#280 to 631-50Wafer number12#29-#420 to 40950 to ??Ordinal die position register that is a function of X and Y probecoordinates i.e. diepos = F(X, Y). Preferred function is tocode for a rectangular region covering the wafer leading to afunction of the form diepos = (Y + A) * (# of rows) + X + Bwhere A and B are constants to account for the placement of theorigin. A generous amount has been assigned here to allowdistinction between 6 and 8 inch wafer positions for whichmutually exclusive die position ranges would be used. Thiswould be handled by 2 different sets of values for the A and Bconstants. In the event that 4095 combos are insufficient(unlikely to be the case on any future DRAM or SRAM design),additional bits can be taken from the generic designator registerbelow.8 antifuse#43-#500 to 2550 to 255Generic designator register for miscellaneous uses. Will be2 laserprogrammed and read as a single register. Possible values willbe defined as needed over the life of the design. Will be treatedas “used” from the beginning with a default value of 0 eventhough all possible values are initially undefined. (Thisinformation will include the fast/slow option code fuse.)Product engineers should be responsible for coordinating theusage of these bits.2#51-#520 to 30 to 3Will be encoded by the function fid_year = year % 4 where“%” is the modulus or remainder function. For 1994, thefid_year value would be 2. Avoids non-unique fuse ID's incase lot number and work week rollover.7#53-#590 to 1270 to 127Design Revision register. Should be able to open these fuseswith both metal mask and laser. “Hard coding” by the metalmask is the preferred method. Laser programming is used as abackup. Will be reprogrammed whenever the metal mask istaped out. In some rare cases, a metal mask may be taped outjust to reprogram this register given there are significant enoughchanges on other layers to require careful backend sortingbetween mask sets.4#60-#630 to 150 to 15Parity error detection bits. This helps determine whether afailing condition on a reject affected a correct fuse ID read. Asa bonus, it also serves as a fuse blow process monitor. (Theerror detection will apply to the entire die id word.)

See modes24-31for the numbering of the arrays which correspond to the DVC2status and 32 Meg Select Bits. The FUSEID is programmed using the OPTPROG test mode, which is mode23below.

14. VCCPCLAMP—This test mode disconnects the clamp between Vcc and Vccp allowing the characterization of the Vccp pump. See FIG. 574. This allows the Vccp level to be elevated at low Vcc stressing silicon pits between memory cells.

15. FASTTM—This test mode speeds up the EQ, ISO, Row Address latch, and P and N Sense Amp enable timing paths.

16. ANTIFUSE—This test mode is used to test and program the row and column redundancy antifuse elements.

17. CA10COMP—This test mode provides 2× address compression on ×4 and ×8 parts or 2× data compression on ×16 parts without writing adjacent bits but does cross redundancy regions. On a ×4 or ×8 part CA<10> is compressed. This combines left and right 16 Megs within a 32 Meg octant. On a ×16 part this is DQ compression. This test mode can be combined with other test modes.

18. FUSESTRESS—This test mode applies Vcc across all antifuses. The DVC2E line is pulled to Vccp and the antifuses are all read, which stresses the antifuses with Vcc. The antifuses will be stressed as long as this test mode is selected and RAS is low.

19. PASSVCC—This test mode passes the internal periphery Vcc onto DQ1.

20. REGOFFTM—This test mode will disable the regulator and short external Vccx and internal Vcc.

21. NOTOPO—This test mode will disable the topo scrambler circuit.

22. REGPRETM—This test mode uses RA<5:9> to pretest the trim values on the voltage regulator. The addresses map to the fuses as shown in Table 10 below. A HIGH address value represents a blown fuse. Note that at least one address needs to be high throughout the RAS low time of this test mode. A timing diagram illustrating the timing of the REGPRETM test mode is set forth in FIG.106.

TABLE 10Address to fuse map for REGPRETM Test ModeRAFUSE5REF12*6REF24*7REF48*8REF100A*9REF100B*

23. OPTPROG—This test mode enables the antifuse options and antifuse FUSEID bits to be programmed. A <10> is used as the CGND signal which sets the programming voltage and either DQ<3> or OE is used as both the chip select and to set the program duration on the antifuse. OE can be used in situations where the DQ's may be OR'ed together from multiple parts and DQ<3> can be used in situations where OE is grounded. A timing diagram illustrating the timing of the OPTPROG test mode is set forth in FIG.107.

All laser/antifuse options can be read out through the FUSEID test mode on banks13and14.FAST—Removes delay in the raend_enph and wl_tracking circuits.128MEG —Forces the part to be accessed as a 128 Meg density part. This option must be combined with 4 of the SEL32MOPT<0:7> option.8KOPT*—Puts the part in 4K refresh mode if combined with 128 MEG option, otherwise the part will be in 16K refresh.SEL32MOPT<0:7>—Blowing the fuse on these options disables the corresponding 32 Meg array.

The following laser options are available in the present preferred embodiment:DISREG—Disables the regulator by clamping Vccx to Vcc through a large p-channel.DISANTIFUSE—Disables the backend redundancy antifuses. Antifuse FID bits are still available.REF12*—LSB of voltage regulator trim.REF24*—regulator trim.REF48*—regulator trim.REF100A*—regulator trim.REF100B*—MSB of voltage regulator trim.

Referring now to the ALLROW high test mode, as noted that test mode is used to rapidly reproduce data for testing a memory array. In the preferred embodiment, the test mode operates on 2 Meg “array slices”1400taken from a 32 Meg array block31, as illustrated in FIG.108. Each array slice1400includes eight adjacent 256k arrays50in the 32 Meg array block31. The 32 Meg array block31is discussed in more detail hereinabove in Section III.

FIG. 109illustrates the details of a 256k array50making up a portion of the array slice1400, and also shows sense amps60,62located above and below the 256k array50and row decoders56,58located on the left and right of the 256k array50, respectively. The 256k array50, the sense amps60,62, and the row decoders56,58are described in more detail hereinabove in Section III. A “seed row”1402, consisting of a number of storage nodes or storage elements5including both true and complement data, extends across the 256k array50and across the array slice1400(as shown in FIG.108), and is programmed with a pattern of data that is used to test the array. Patterns of data used to test for defects in memory arrays are well known in the art of semiconductor fabrication and they will not be discussed herein. The writing of data into the 256k array is a relatively slow process because in most memory devices no more than one or two bits of data can be written in the array slice1400during each write cycle. Once the seed row1402is written, however, the present invention allows the data stored in the seed row1402to be quickly duplicated into the remaining rows within the array slice1400. More specifically, by “firing” the appropriate wordline, the data stored in the seed row1402is placed on the digitlines68,68′,69,69′ in the 256k array50. Once the data is on the digitlines68,68′,69,69′, the data is latched by the sense amps60,62. Thereafter, the latched data may be stored in any row of storage nodes5in the 256k array50by firing the appropriate wordline to connect the row of storage nodes to the digitlines68,68′,69,69′.

In the preferred embodiment, the seed row1402is written in a conventional manner. In addition, the seed row1402is always the same row within the 256k array50so that the test mode knows where to find the data. After the seed row1400is written, the test mode is entered by any one of many means known in the art. Once in the test mode, signals take on special meanings to accomplish the testing. Cycling the RAS* signal will cause all storage nodes5in the seed row1402to be connected to the digitlines68,68′,69,69′, so that the sense amps60,62latch the data. After the data is latched, cycling the CAS signal will cause additional rows of storage nodes5to be connected to the digitlines68,68′,69,69′ and, thereby, to have the data on the digitlines68,68′,69,69′ written thereto. Preferably, multiple rows are accessed with each CAS cycle so that the array50is written more quickly. In the preferred embodiment, each CAS cycle causes approximately 25% of the rows in the array slice1400to be programmed with the data on the digitlines68,68′,69,69′. As a result, only four CAS cycles are required to program an entire array slice1400from a single seed row1402. The choice of duplicating the array slice1400in 25% increments is based on considerations such as power supply capacity. Greater or smaller increments may, of course, be used. For example, in some applications the entire array slice1400may be programmed in a single CAS cycle. Furthermore, external signals other than CAS and RAS* may be used to control the test mode.

In the present invention, the row and column address signals required to select the array slice1400are provided externally. In contrast, the row address signals required to select rows within the array slice1400are provided internally by the test mode. The test mode selects 25% of the array slice1400by generating a high logic state signal for each predecoded row address signal RA_0<0:1>, RA34<0:3>, RA56<0:3>, and RA78<0:3>, in combination with generating a high logic state signal for only one of the four predecoded row address signals RA12<0:3>. The one row address signal RA12<n> that is a high logic state will determine which 25% of the array slice1400is selected. The row address mapping and column address mapping schemes for the present invention are discussed in more detail hereinabove in Section V. Row address data signals RA12<0:3> are provided by a CAS before RAS CBR ripple counter formed from cascading one bit CBR counters located in the row address buffers. In normal operation, the CBR ripple counter is used to provide internally-generated refresh address signals, but in the all row high test mode it is used to automatically generate row address signals RA12<0:3> for each CAS cycle. During each CAS cycle, the CBR ripple counter generates new row address signals RA12<0:3>. For example, during the first CAS cycle, the CBR ripple counter will generate a high logic state signal for row address signal RA12<0> only, thereby selecting 25% of the array slice1400. During the second CAS cycle, the CBR ripple counter will, generate a high logic state signal for row address signal RA12<1> only, thereby selecting a different 25% of the array slice1400. Likewise, during third and fourth CAS cycles the CBR counter will generate high logic state signals for only row address signals RA12<2> and RA12<3>, respectively. After four CAS cycles, the CBR counter will have selected the entire array slice1400.

Referring back toFIG. 104,FIG. 104illustrates timing diagrams of the RAS*, CAS, and WE signals used to practice the present invention. As shown, RAS* goes to a low logic state at a time indicated by reference number1410to fire the seed row1402so that the seed row data is latched by the sense amps60,62. A delay period1412following the RAS* cycle allows the sense amps60,62to reach a stable state. At a time indicated by reference number1414, WE goes to a low logic state and 25% of the rows in the array slice1400, represented by row address; signal RA12<0>, are written with the data latched by the sense amps60,62. On the rising edge1416of the WE signal, another 25% of the rows in the array slice, represented by row address signal RA12<1>, is written. At trailing edge1418of the WE signal, another 25% of the rows in the array slice, represented by row address signal RA12<2>, is written. DVC2is also disabled. At rising edge1420, the final 25% of the rows in the array slice, represented by row address signal RA12<3>, is written. On the following trailing edge, DVC2is set low. After the array slice1400has been written, the data can be read and analyzed to identify defects in the DRAM. Testing may also proceed to other array slices1400within the DRAM so that, with multiple iterations, the entire DRAM may be tested for defects.

One advantage of the all row high test mode is that it allows data to be quickly reproduced in a memory array. Another advantage is that the rate at which data is reproduced can be controlled by controlling the RAS*, CAS, and WE signals. As a result, the test mode can be used to study how quickly and in what manner a memory device will react during testing to better understand the DRAM10and to optimize the testing process.

In addition to operating in a plurality of test modes, in the present preferred embodiment, redundancy pretesting can be performed. There are two possible ways to use the redundancy pretest. At Probe there is the REDPRE probe pad. This pad is latched at RAS and CAS time to function as another address. If REDPRE is high at RAS time then the accompanying address will function as a redundancy pretest address. The same is true at CAS time. If the REDPRE pad is low at RAS time the address pins function in their normal manner. The same is true again at CAS time. That allows Probe to enter a redundancy pretest address at Row time and follow that with a normal column address. Also, a normal Row address can be followed by a redundant pretest column address. Once the part is packaged the REDPRE pad is no longer available and the REDROW and REDCOL test modes must be used.

The row redundancy pretest addresses are described in tables 11, 12 and 13. There are 32 elements in each 32 Meg octant organized into 8 banks of 4 elements. Element3in each bank is laser or antifuse programmable. Two physical rows are replaced in a 32 Meg array by each element. To exercise both physical rows attached to any particular element both states of the 16MEG* signal must be used. Table 11 illustrates how 16MEG is controlled by the various part types. Redundant rows can be pretested even if some of the redundancy has been enabled or if all redundancy has been disabled.

TABLE 12Row Element Address Within a BankRA0RA12Element000111022133 laser/elect

Tables 14 to 19 below show the pretest addressing for the redundant column elements and their corresponding DQ. Each octant contains 32 column elements grouped into 8 banks of 4 elements. Element3is both laser or antifuse programmable. Table 14 shows how CA9, 32MEG are used to decode the octants. Addresses CA11, CA10and CA7are used to decode the various banks and CA1and CA0are used to decode 1 of 4 elements within each bank. Address CA8selects between I/O pairs and must be tested in both states. Because the column pretest addresses feed through the laser fuses, the pretest may not work if any redundant elements have been enabled. Redundant column elements cannot be pretested if redundancy has been disabled.

TABLE 16Column Element Address Within a BankCA01Element00112233 Laser/Elect

TABLE 17Column Pretest Bank Addresses (X4)CA1011CA7Bank000011102113204215306317

FIG. 110illustrates the chip10of the present invention and provides some exemplary dimensions of one embodiment. In the illustrated embodiment, total die space is approximately 574.5 k mils2with approximately 323.5 k mils2devoted to the active array. Thus, the active array occupies over half the total die space.

FIG. 111illustrates an example of the connection of the bonding pads of the present invention to a lead frame1422. As can be seen inFIG. 111, there are tie bars1424connecting several lead fingers1425to the lead frame1422, thereby supporting the lead fingers1425so they do not move during a molding process. There are also combination tie bars and bus bars1426. The combination tie bar and bus bar1426supports lead fingers1425during the molding process and, after the tie bars are cut in a trim and form process, the bus bar remains to serve as a power bus or a ground bus. The chip10of the present invention may be encapsulated in a package during a molding process, so that the package has an encapsulating body and electrically conductive interconnect pins, or leads, extending outwardly from the body. After the molding process, the trim and form process separates the lead frame from the leads and separates the leads from each other.

FIG. 112illustrates a substrate carrying a plurality of chips10, each constructed according to the teachings of the present invention. The size of the substrate, or wafer, is determined by the size of the fabrication equipment. A six inch wafer size is typical.

FIG. 113is a block diagram illustrating the DRAM10of the present invention used in a microprocessor-based system1430. The DRAM10is under the control of a microprocessor1432which may be programmed to carry out particular functions as is known in the art. The microprocessor-based system1430may be used, for example, in a personal computer, computer workstations, and consumer electronics products.

While the present invention has been described in conjunction with preferred embodiments thereof, many modifications and variations will be apparent to those of ordinary skill in the art. For example, the number of individual arrays and their organization into array blocks, and the organization of the array blocks into quadrants may be varied. Rotation of an array by ninety degrees causes the rows to become columns and the columns to become rows. Therefore, descriptors such as “between adjacent columns” should be understood as including “between adjacent rows” in such a rotated device. Additionally, the position of the peripheral devices may be interchanged such that devices in the “columns” are in the “rows” and vice versa. The amount and location of the decoupling capacitors may be varied. More or less redundancy may be provided, and various combinations of laser and electrical types of fuses may be provided for logically replacing defective rows/columns with operational rows/columns. Other types of test modes may be supported. The number and location of the voltage supplies may be varied and numerous other types of circuits and logic may be supplied to provide the described functionality.

Other modifications and variations include varying the orientation of the array with respect to the periphery. The sequence of powering up the power supplies may be varied. Various signals may be combined with switched gates to effect different or additional functionality. Address space and DQ plans can be allocated differently. The distribution of address and control signals, predecoded versus nonpredecoded, results in various structural differences which are apparent to those of ordinary skill in the art. Decisions such as the number of metal layers also leads to distinctive circuit implementation. For example, the use of only two metal layers mandates the use of local row decoders. Different overall dimensions may be employed, as well as different bonding schemes between the chip and the lead frame.

Other decisions such as the size of the overall chip, density, memory size, and process limitations, will lead to many modifications and variations of the present invention too numerous to enumerate. The foregoing description and the following claims are intended to cover all such modifications and variations.