Current steering digital to analog converter with decoder free quad switching

Disclosed herein is a digital to analog converter including a first dynamic latch receiving a data signal and an inverse of the data signal. The first dynamic latch is clocked by a clock signal and configured to generate first and second quad switching control signals as a function of the data signal and the inverse of the data signal. A second dynamic latch receives the data signal and the inverse of the data signal, is clocked by an inverse of the clock signal, and is configured to generate third and fourth quad switching control signals as a function of the data signal and the inverse of the data signal. A quad switching bit cell is configured to generate an analog representation of the data signal as a function of the first, second, third, and fourth quad switching signals.

TECHNICAL FIELD

The present disclosure relates to a high-speed digital to analog converter, and more specifically, to a current steering digital to analog converter utilizing decoder free quad switching.

BACKGROUND

High-speed and high-accuracy digital to analog converts (DACs) are important building blocks for many signal processing and telecommunication systems. A DAC is a device that converts a digital signal into an analog signal. Due to the ever increasing digital processing power and speed of modern chips, the need for DACs with higher sampling speeds is on the rise. For example, 3D high-definition televisions (HDTVs) use DACs with 200 Megasamples per second (MSPS) while telecommunication transmitters use DACs with over a few GSPS. In addition to the high sampling speed, many of these applications also require very high linearity and high Spurious-Free Dynamic Range (SFDR) in the output analog signal.

Generally DACs use multiple switches to steer current to one or multiple outputs. The switches are operated by digital signals generated by a chain of digital signal processing. As the switches are turned on or off by the digital signals, jitter in the digital signals to the switches may degrade linearity performance and add spurious noises at the analog output. With high-speed DACs, the situation is especially critical since jitter at the digital signals tends to cause a more pronounced effect as the frequency increases.

Another important factor in high-speed DACs is data dependent switching of switches. Data dependent switching can be caused partly due to the asymmetry in the beginning transition and ending transition of an “on” pulse (e.g., “1” pulse) and an “off” pulse (e.g., “0” pulse). Generally, the transition time for turning on the pulse and turning off the pulse are asymmetric. Due to such differences in transition time, data streams including combinations of “on” pulses and “off” pulses generate noise in the analog output of the DACs that is dependent on digital signals provided to the DACs. This results in formation of switching power from the power supply. This switching power, when interacting with package parasitic like bonding or routing inductances, can generate harmonics of the desired signal from power supply to outputs and can further degrade the SFDR and SNR of the DAC.

Further development in the area of DACs is therefore needed to address these issues.

SUMMARY

Disclosed herein is a digital to analog converter including a first differential latch with reset input, receiving a data signal and an inverse of the data signal and with complementary outputs when not in reset state. Reset state will have same value of both outputs. One example for this kind of latch is the dynamic latch. However, there are many other derivatives of the latch which can be used to same functionality. For simplicity any future description will use Strong ARM dynamic latch as an example. The first dynamic latch is clocked by a clock signal and configured to generate first and second quad switching control signals as a function of the data signal and the inverse of the data signal. A second dynamic latch receives the data signal and the inverse of the data signal, is clocked by an inverse of the clock signal, and is configured to generate third and fourth quad switching control signals as a function of the data signal and the inverse of the data signal. A quad switching bit cell is configured to generate an analog representation of the data signal as a function of the first, second, third, and fourth quad switching signals.

The quad switching bit cell may include a tail node, and first and second output nodes. A first p-channel transistor may have a source coupled to the tail node, a drain coupled to the first output node, and a gate biased by the second quad switching control signal. A second p-channel transistor may have a source coupled to the tail node, a drain coupled to the second output node, and a gate biased by the third quad switching control signal. A third p-channel transistor may have a source coupled to the tail node, a drain coupled to the first output node, and a gate biased by the fourth quad switching control signal. A fourth p-channel transistor may have a source coupled to the tail node, a drain coupled to the second output node, and a gate biased by the first quad switching control signal.

The first dynamic latch may be in a reset phase when the clock signal is deasserted. The first and second quad switching control signals may be asserted when the clock signal is deasserted, thereby resetting the first and fourth p-channel transistors when the first dynamic latch is in the reset phase. The second dynamic latch may be in a reset phase when the inverse of the clock signal is deasserted, and the third and fourth quad switching control signals may be asserted when the inverse of the clock signal is deasserted, thereby resetting the second and third p-channel transistors when the second dynamic latch is in the reset phase.

The first dynamic latch may include a first p-channel transistor having a source coupled to a supply node, a drain coupled to a first node, and a gate biased by the clock signal. A second p-channel transistor may have a source coupled to the supply node, a drain coupled to the first node, and a gate biased by a second node. A third p-channel transistor may have a source coupled to the supply node, a drain coupled to the second node, and a gate biased by the first node. A fourth p-channel transistor may have a source coupled to the supply node, a drain coupled to the second node, and a gate biased by the clock signal. A first n-channel transistor may have a drain coupled to the first node, a source coupled to a third node, and a gate biased by the second node. A second n-channel transistor may have a drain coupled to the second node, a source coupled to a fourth node, and a gate biased by the first node. A third n-channel transistor may have a drain coupled to the third node, a source coupled to a fifth node, and a gate biased by the data signal. A fourth n-channel transistor may have a drain coupled to the fourth node, a source coupled to the fifth node, and a gate biased by the inverse of the data signal. A fifth n-channel transistor may have a drain coupled to the fifth node, a source coupled to ground, and a gate based by the clock signal.

The first and second quad switching control signals may be respectively generated at the first and second nodes. The third and fourth quad switching control signals may be respectively generated at the third and fourth nodes.

The second dynamic latch may include a first p-channel transistor having a source coupled to a supply node, a drain coupled to a first node, and a gate biased by the inverse of the clock signal. A second p-channel transistor may have a source coupled to the supply node, a drain coupled to the first node, and a gate biased by a second node. A third p-channel transistor may have a source coupled to the supply node, a drain coupled to the second node, and a gate biased by the first node. A fourth p-channel transistor may have a source coupled to the supply node, a drain coupled to the second node, and a gate biased by the inverse of the clock signal. A first n-channel transistor may have a drain coupled to the first node, a source coupled to a third node, and a gate biased by the second node. A second n-channel transistor may have a drain coupled to the second node, a source coupled to a fourth node, and a gate biased by the first node. A third n-channel transistor may have a drain coupled to the third node, a source coupled to a fifth node, and a gate biased by the data signal. A fourth n-channel transistor may have a drain coupled to the fourth node, a source coupled to the fifth node, and a gate biased by the inverse of the data signal. A fifth n-channel transistor may have a drain coupled to the fifth node, a source coupled to ground, and a gate based by the inverse of the clock signal.

A current source may be coupled to the tail node.

DETAILED DESCRIPTION

Reference will now be made in detail to several embodiments, examples of which are illustrated in the accompanying figures. It is noted that wherever practicable, similar or like reference numbers may be used in the figures and may indicate similar or like functionality. The figures depict embodiments for purposes of illustration only.

Embodiments relate to an analog to digital converter (DAC) utilizing a quad switching scheme turning on or off of switches for steering current to a differential output. The control signals for the quad switching scheme are generated by resettable differential latches. Details will now be given with initial reference toFIG. 1. The DAC100includes a current source102coupled to a tail node90. A PMOS transistor MP1has its source coupled to the tail node90, its drain coupled to a first output node101, and its gate biased by a control signal N1received from a first dynamic latch104. A PMOS transistor MP2has its source coupled to the tail node90, its drain coupled to a second output node103, and its gate biased by a control signal P2received from a second dynamic latch106. A PMOS transistor MP3has its source coupled to the tail node90, its drain coupled to the first output node101, and its gate biased by a control signal N2from the dynamic latch106. A PMOS transistor MP4has its source coupled to the tail node90, its drain coupled to the second output node103, and its gate biased by a control signal P1from the dynamic latch104. A load108is coupled to the first output node101and second output node103. The PMOS transistors MP1-MP4, among things, serve to isolate the load108from the current source102.

Referring additionally toFIG. 2, the first dynamic latch104includes a PMOS transistor MP5having its source coupled to a supply node Vdd, its drain coupled to node80, and its gate biased by a clock signal ϕ. A PMOS transistor MP6has its source coupled to the supply node Vdd, a drain coupled to node80, and its gate biased by the voltage at node81. A PMOS transistor MP7has its source coupled to the supply node Vdd, its drain coupled to node81, and its gate biased by the voltage at node80. A PMOS transistor MP8has its source coupled to supply node Vdd, its drain coupled to node81, and its gate biased by the clock signal ϕ.

A NMOS transistor MN1has its drain coupled to node80, its source coupled to node82, and its gate coupled to be biased by the voltage at node81. A NMOS transistor MN2has its drain coupled to node81, its source coupled to node83, and its gate coupled to be biased by the voltage at node80. A NMOS transistor MN3has its drain coupled to node82, its source coupled to node84, and its gate biased by a data signal D. Data signal D is represents a single bit of a multi-bit digital signal received from a digital modulator or OFDM generator that is to be converted to an analog signal representation. Other DACs100of the same design of the DAC100are used to convert the other bits of the data signal D to analog representations.

An NMOS transistor MN4has its drain coupled to node83, its source coupled to node84, and its gate biased by a logical inverse D of the data signal D. An NMOS transistor MN5has its drain coupled to node84, its source coupled to ground, and its gate biased by the clock signal ϕ.

PMOS transistors MP5and MP8operate as precharge transistors. PMOS transistors MP6and MP7form a PMOS latch, while NMOS transistors MN1and MN2form a NMOS latch that serves to prevent static current. NMOS transistors MN3and MN4provide clock data inputs to the dynamic latch104. The dynamic latch104generates the P1signal at node80and the N1signal at node81.

Referring additionally toFIG. 3, the second dynamic latch106includes a PMOS transistor MP9having its source coupled to a supply node Vdd, its drain coupled to node85, and its gate biased by a logical inverse ϕ of the clock signal ϕ. A PMOS transistor MP10has its source coupled to the supply node Vdd, a drain coupled to node85, and its gate biased by the voltage at node85. A PMOS transistor MP11has its source coupled to the supply node Vdd, its drain coupled to node85, and its gate biased by the voltage at node85. A PMOS transistor MP12has its source coupled to supply node Vdd, its drain coupled to node86, and its gate biased by the logical inverse ϕ of the clock signal ϕ.

An NMOS transistor MN6has its drain coupled to node85, its source coupled to node87, and its gate coupled to be biased by the voltage at node86. A NMOS transistor MN7has its drain coupled to node86, its source coupled to node88, and its gate coupled to be biased by the voltage at node85. A NMOS transistor MN8has its drain coupled to node87, its source coupled to node89, and its gate biased by a data signal D. A NOS transistor MN9has its drain coupled to node88, its source coupled to node89, and its gate biased by a logical inverse D of the data signal D. A NMOS transistor MN10has its drain coupled to node89, its source coupled to ground, and its gate biased by the logical inverse ϕ of the clock signal ϕ.

PMOS transistors MP9and MP12operate as precharge transistors. PMOS transistors MP10and MP11form a PMOS latch, while NMOS transistors MN6and MN7form a NMOS latch that serves to prevent static current. NMOS transistors MN8and MN9provide clock data inputs to the dynamic latch106. The dynamic latch106generates the P2signal at node80and the N2signal at node81.

It should be understood thatFIGS. 1-3are for one bit (represented by D) of a multi-bit digital signal, and that there will be an equal number of these structures as there are bits in a digital signal to be converterd.

The dynamic latches104and106may be Strong ARM latched. Details of strong ARM latches can be found in Razavi, “The StrongARM Latch”, IEEE Solid-State Circuits Magazine, Spring 2015, which is incorporated by reference herein in its entirety.

Details of operation of the DAC100will now be given with additional reference toFIGS. 4-5. The dynamic latch104operates in four phases, namely reset, sampling, regeneration, and output. The reset phase begins when the clock signal ϕ is deasserted. In the reset phase, PMOS transistors MP5and MP8turn on, causing the voltage at nodes80and81to increase to a precharge voltage, outputting signals P1and N1as high, as shown inFIG. 4. This turns off PMOS transistors MP6and MP7, and turns on NMOS transistors MN1and MN2, causing the voltage at nodes82and83to increase. NMOS transistor MN5is turned off when the clock signal ϕ is deasserted. Depending on the value of the data signal D and its inverse D, either NMOS MN3or MN4will turn on and charge up node84because NMOS transistor MN5is turned off when the clock signal ϕ is deasserted.

The sampling phase begins when the clock signal ϕ is asserted and continues until one of the PMOS transistors MP6and MP7turn on. When the clock signal ϕ goes high, NMOS transistor MN5turns on, discharging node84. Depending on the value of the data signal D and its inverse D, one of NMOS transistors MN3and MN4will be on, discharging node82or83. NMOS transistors MN1and MN2will, at the entry into the sampling phase, be on from the reset phase, and will discharge node80or81, depending on which of the NMOS transistors MN3and MN4is on. This will ultimately turn on one of the PMOS transistors MP6or MP7.

The regeneration phase begins when one of the PMOS transistors MP6and MP7turns on, charging node80or81. The output phase begins when the node80or81being charged is charged to Vdd, and the control signals P1and N1are then stable and have a valid output, as shown inFIG. 4.

Operation of the dynamic latch106proceeds in the same way as dynamic latch104, except for the fact that it is clocked by the inverse ϕ of the clock signal ϕ instead of the clock signal ϕ.

The reset phase of the dynamic latch106begins when the inverse clock signal ϕ switches low. In the reset phase, PMOS transistors MP9and MP12turn on, causing the voltage at nodes85and86to increase, outputting signals P2and N2as high. This turns off PMOS transistors MP10and MP11, and turns on NMOS transistors MN6and MN7, causing the voltage at nodes87and88to increase. NMOS transistor MN10is turned off when the inverse clock signal ϕ is deasserted. Depending on the value of the data signal D and its inverse D, either NMOS MN8or MN9will turn on and charge up node89because NMOS transistor MN10is turned off when the clock signal ϕ is deasserted.

The sampling phase begins when the clock signal ϕ is asserted and continues until one of the PMOS transistors MP10and MP11turns on. When the clock signal ϕ goes high, NMOS transistor MN10turns on, discharging node89. Depending on the value of the data signal D and its inverse D, one of NMOS transistors MN8and MN9will be on, discharging node87or88. NMOS transistors MN6and MN7will, at the entry into the sampling phase, be on from the reset phase, and will discharge node85or86, depending on which of the NMOS transistors MN8and MN9is on. This will ultimately turn on one of the PMOS transistors MP10or MP11.

The regeneration phase begins when one of the PMOS transistors MP10and MP11turns on, charging node85or86. The output phase begins when the node85or86being charged is charged to Vdd, and the control signals P2and N2are then stable ready to be read.

Referring now to the timing diagram ofFIG. 4, as an example, at time T1, the clock ϕ is high, and the data signal D is high. Thus, the dynamic latch104generates P1as high and N1as low, and the dynamic latch104generates P2and N2as high. Consequently, as explained, only the transistor MP1is on while the other transistors MP2-MP4are off. At time T2, the clock ϕ is low, and the data signal D is still high. It should be noted that the frequency of the data signal D matches that of the clock ϕ. Then, the dynamic latch104is in its reset phase and generates P1and N1as high, and the dynamic latch106generates P2as high and N2as low, turning MP3on, while transistors MP1-MP2and MP4are off. Next, at time T3, the clock ϕ is high again, and the data signal D is low. Thus, the dynamic latch104generates P1as low and N1as high, while dynamic latch106generates P2and N2as high, turning transistor MP1on, while transistors MP2-MP4are off.

Thus, from the description of the operation of the first and second dynamic latches104and106above, it should be apparent that in a clock cycle, the control signals P1, N1, P2, N2control the transistors MP1, MP2, MP3, and MP4such that one of the four is turned on whereas other three are turned off. In a subsequent clock cycle, a different transistor MP1, MP2, MP3, or MP4is turned on while the transistor MP1, MP2, MP3, or MP4activated in a previous cycle is turned off. The transistor MP1, MP2, MP3, or MP4to be turned on in a next cycle is one of two transistors MP1, MP2, MP3, or MP4adjacent to the transistor MP1, MP2, MP3, or MP4that was turned on in a previous cycle. Even if the current source102should remain connected to the same output node101or103during two adjacent clock cycles, the activated transistor MP1, MP2, MP3, or MP4is shifted between the two clock cycles.

The logic of the DAC100can be summed up as thus. Current In will equal current I when P1=P2=1 and either N1or N2=0. Current Ip will equal current I when N1=N2=1 and either P1or P2=0. Other operating states do not occur.

Further details of such a quad switching scheme can be found in Sungkyung Park et al., “A Digital-to-Analog Converter Based on Differential-Quad Switching,” IEEE Journal of Solid-State Circuits, vol. 38, No. 10 (October 2002), which is incorporated by reference herein in its entirety.

Through the use of the quad switching coupled with the use of the dynamic latches104and106instead of decoders, as well as the fact that the reset phase of the dynamic latches104and106overlaps with reset of the transistors MP1-MP4, data dependent noise is reduced or removed. Moreover, the complete symmetry of the design of the DAC100helps ensure that only clock frequency dependent ripples appear on the power supply. This is particularly advantageous because switching performance in a DAC100is crucial to the linearity of the performance of the DAC100itself. Imperfections in the data signal such as jitter, amplitude noise, and poor pulse width control can degrade DAC performance. By imparting the data signal with the clean characteristics of a clock, and doing so as physically close to the switching circuitry as possible with the least amount of circuitry involved, these deficiencies are greatly reduced.

Upon reading this disclosure, those of ordinary skill in the art will appreciate still additional alternative structural and functional designs through the disclosed principles of the embodiments. Thus, while particular embodiments and applications have been illustrated and described, it is to be understood that the embodiments are not limited to the precise construction and components disclosed herein and that various modifications, changes and variations which will be apparent to those skilled in the art may be made in the arrangement, operation and details of the method and apparatus disclosed herein without departing from the spirit and scope as defined in the appended claims.