Memory device

A memory device is configured as single chip to achieve routing control, bandwidth control, traffic monitoring, buffering, and access control of network functions. The memory device includes a search unit that includes a first memory unit and performs a search operation by searching, from the first memory unit, a piece of data corresponding to an input search key, a statistical information processing unit that includes a second memory unit that stores statistical information including the input search key, with which the piece of data has been successfully searched by the search unit, and an address of the piece of data in the first memory unit, and an arithmetic operation unit that updates the statistical information when the search unit successfully searches the pieces of data corresponding to the input search key.

TECHNICAL FIELD

The present invention relates to a memory device.

BACKGROUND ART

In the related art, personal computers (hereinafter appropriately abbreviated as “PCs”) and servers are IT devices which are manufactured and sold by limited manufacturers. Since components such as processors and memories which are used in devices have been recently generalized, the PCs or the servers have changed into IT devices which can be assembled by anyone. In PCs or servers in General, application software such as an OS is commodified, and such PCs or servers employ an open platform for which anyone can be a developer or a technical proposer. Like systems including the PCs or servers in the present day, a system of which casings are different but configurations of internal specifications are visualized are referred to as “White Box” or the like.

Network devices such as routers or switches (for example, see Patent Documents 1 to 3) were in a special IT device market which are dominated by only limited manufacturers, but as a new term “network functions virtualization (NFV)” emerges in recent years, the recent trend of the network devices are similar to the recent trend of the PCs or servers described above. For example, low cost type enterprise-grade models have gradually employed an open platform which can be manufactured by anyone by commodification of processors or memories.

DISCLOSURE OF THE INVENTION

Problems to be Solved by the Invention

However, on the occasion of commodification of NFV or networks, it is desired to extend network functions such as extending routing control including search. In this case, as illustrated inFIG. 15, this requires multiple expensive components consuming high power, such as special memories.

FIG. 15is a block diagram illustrating a configuration example of an information processing system according to related art for implementing network functions. For example, the information processing system according to the related art illustrated inFIG. 15is mounted on a board which is incorporated into a server or a PC. The information processing system according to the related art includes a network processor12, a CPU13, a plurality of (four in the example illustrated inFIG. 15) communication devices14ato14d, a TCAM501, an SRAM502, and a DRAM503. When the function of the network processor12is extended, various memories are required for the information processing system according to the related art. For example, the TCAM501is used to implement routing control and traffic monitoring, the SRAM502is used to implement routing control, bandwidth control, and traffic monitoring, and the DRAM503that can have a large capacity is used as a buffer. The TCAM501, the SRAM502, and the DRAM503are components with high prices and high power consumption.

The invention is made in consideration of the above-mentioned circumstances and an object thereof is to easily realize extension of network functions with low cost and low power consumption on the occasion of NFV or commodification of networks.

Means for Solving the Problems

A memory device according to an aspect of the invention is a memory device that is configured as single chip, in which the memory device allows at least routing control, bandwidth control, traffic monitoring, buffering, and access control of network functions to function.

Here, the memory device may include: a search unit that includes a first memory unit and performs a search operation of referring to an input search key for data stored in the first memory unit; a statistical information processing unit that correlates an address of the first memory unit with a search key which is hit by the search unit and includes a second memory unit that stores statistical information of the address; and an arithmetic operation unit that updates the statistical information whenever the search unit hits.

The search unit may have a function of changing a bit width of a search key.

The search unit may have a function of outputting a determination signal indicating whether writing of information has succeeded or failed.

The search unit may selectively perform the access control using a white list method and the access control using a black list method.

The memory device may be provided to be connected to each individual device in an information processing system including individual devices constituting a network and a network controller controlling the individual devices, and the memory device may have: a function of monitoring traffic of one connected individual device of the individual devices, acquiring data, and transmitting the acquired data to the network controller; and a function of receiving control information and controlling one connected individual device of the individual devices on the basis of the control information when data of the individual devices is analyzed and the control information for the individual devices is generated and transmitted by the network controller.

The memory device may further include: a memory unit; a network function unit that implements the network functions; and a selector unit that switches between a first route including the memory unit and the network function unit and a second route including the memory unit.

The selector unit may be implemented using at least one of a metal mask and an address key.

The network function unit may include a comparator group for a test mode of the memory unit.

Effects of the Invention

According to the invention, it is possible to easily realize extension of a network function with low cost and low power consumption on the occasion of NFV or commodification of networks.

PREFERRED MODE FOR CARRYING OUT THE INVENTION

FIG. 1is a block diagram illustrating a configuration example of an information processing system according to an embodiment of the invention. For example, the information processing system illustrated inFIG. 1is mounted on a board which is incorporated into a server or a PC. The information processing system includes a Poco Watcher11which is an example of an electronic device to which the invention is applied, a network processor12, a CPU13, and a plurality of (four in the example illustrated inFIG. 1) communication devices14ato14d.

When the function of the network processor12is extended, various memories were necessary in the related art as described above. For example, in the example of the related art illustrated inFIG. 15, the TCAM501is used to implement routing control and traffic monitoring, the SRAM502is used to implement routing control, bandwidth control, and traffic monitoring, and the DRAM503having a capacity capable of increasing is used as a buffer. On the other hand, in the information processing system according to this embodiment, since the Poco Watcher11is configured as a single chip allowing DRAM processes, it is possible to cope with a buffer with a large capacity. Accordingly, as illustrated inFIG. 1, it is possible to extend the function of the network processor12using only a configuration in which the Poco Watcher11is connected to the network processor12.

The configuration of the information processing system is not particularly limited to the configuration illustrated inFIG. 1, as long as it is a configuration in which the network processor12and the Poco Watcher11can communicate with each other.

FIGS. 2A and 2Bare block diagrams illustrating a configuration example of the information processing system according to the embodiment of the invention which is different from the example illustrated inFIG. 1. The information processing system in the example illustrated inFIG. 2Ais different from the example illustrated inFIG. 1, in that the communication devices14ato14dare connected to the Poco Watcher11. The information processing system in the example illustrated inFIG. 2Bis different from the example illustrated inFIG. 1, in that a communication device14ewhich is connected to a router which is not illustrated is connected to the Poco Watcher11. The configurations illustrated inFIGS. 2A and 2Bare only examples, and for example, although not illustrated, two Poco Watchers11may be provided and the Poco Watchers11may be respectively simultaneously inserted between the communication device14eand the network processor12and between the network processor12and the communication devices14ato14d.

FIG. 3is a functional block diagram illustrating implementation of network functions of functions of the Poco Watcher11. As illustrated inFIG. 3, the Poco Watcher11allows a routing control unit31, a bandwidth control unit32, a traffic monitoring unit33, a buffer unit34, an access control unit35, and a main control unit36to function.

The routing control unit31implements a function equivalent to the routing control which was implemented by the TCAM and the HS SRAM in the related art. The bandwidth control unit32implements a function equivalent to the bandwidth control which was implemented by the HS SRAM and the LLDRAM in the related art. The traffic monitoring unit33implements a function equivalent to the traffic monitoring which was implemented by the TCAM, the HS SRAM counter, and the ALU in the related art. The buffer unit34implements the buffering by a function equivalent to the DRAM in the related art. The access control unit35implements a function equivalent to the access control which has been implemented in the related art. The main control unit36controls the entire Poco Watcher11including the routing control unit31to the access control unit35.

FIG. 4is a functional block diagram illustrating implementation of a mining function of the functions of the Poco Watcher11. As illustrated inFIG. 4, the Poco Watcher11allows a clustering unit37, a ranking unit38, and a mining unit39to function in addition the main control unit36.

The clustering unit37implements a function equivalent to clustering control which has been implemented in the related art. The ranking unit38implements a function equivalent to ranking control which has been implemented in the related art. The mining unit39implements a function equivalent to mining which has been implemented in the related art.

FIG. 5illustrates an example of a hardware configuration which operates when the routing control unit31or the traffic monitoring unit33illustrated inFIG. 3or the clustering unit37or the ranking unit38illustrated inFIG. 4functions in the hardware configuration of the Poco Watcher11.FIG. 6illustrates an example of a hardware configuration which operates when the routing control unit31or the traffic monitoring unit33illustrated inFIG. 3or the clustering unit37or the ranking unit38illustrated inFIG. 4functions in the hardware configuration of the Poco Watcher11which is different from the example illustrated inFIG. 5. In order to clearly distinguish the example illustrated inFIG. 5and the example illustrated inFIG. 6, the Poco Watcher11in the example illustrated inFIG. 5is particularly referred to as a “Poco Watcher11a” and the Poco Watcher11in the example illustrated inFIG. 6is particularly referred to as a “Poco Watcher11b”.

The Poco Watcher11ain the example illustrated inFIG. 5includes a search unit51a, a statistical information processing unit52a, and an arithmetic operation unit53a.

The search unit51ais a so-called search engine and includes a hash generator61, a memory unit62, and a comparator63. Here, search refers to an operation of referring to a desired search key (a data string to be searched for) for data stored in a storage device such as a memory (the memory unit62in the example illustrated inFIG. 5). A case in which a search key has been found in the memory unit62is defined as a hit (a search hit), and a case in which a search key has not been found is defined as a miss (a search miss). After the search has hit, an action (or a rule) is output from the memory unit62. Specifically, for example, it is assumed that PortB (in which a destination is the communication device14b) is defined as an action when a search key 55_23_75_A4_53_10_89_bd is stored in the memory unit62and a hit occurs. In this way, when the search key 55_23_75_A4_53_10_89_bd is input to the search unit51a, the search key is searched for from the memory unit62to be hit and PortB is output as an action.

When various applications causing the routing control unit31or the traffic monitoring unit33illustrated inFIG. 3or the clustering unit37or the ranking unit38illustrated inFIG. 4to function are executed, this search operation is necessary. The search operation (command) cannot be performed with a hardware configuration using a normal memory in the related art (a configuration including only the memory unit62illustrated inFIG. 5). Accordingly, in the related art, when a network IP address is searched for, or the like, a special memory called TCAM501(FIG. 15) is used to perform a search operation. The TCAM501performs a search operation by providing an address comparator to a memory cell side and performing a process of comparing data stored in the memory cell with the search key for all memory cells. The search using the TCAM501has a problem in that power consumption is very great to simultaneously access all the memory cells in parallel.

Therefore, in this embodiment, the search unit51athat can perform a search operation is provided in a single chip called Poco Watcher11so as to perform a search operation without providing a special memory such as the TCAM501.

Here, the memory unit62in the search unit51ahas the same hardware configuration as a normal memory. That is, the memory unit62includes a memory cell array621, a decoder622, and a sense amplifier & selector623. The decoder622decodes encoded data (an input address). Here, the decoder622develops a signal of a binary number. For example, a value of N bits is developed into 2N by the decoder622. Then, the decoder622selects a position of the memory cell array621on the basis of the developed value, and data is written to the selected position or data is read from the selected position. The sense amplifier & selector623includes a sense amplifier that amplifies data read from the memory cell array621and a selector that selects data read from the memory cell array621in accordance with an address signal. In this way, all operations (commands) which can be performed by the memory unit62itself are writing and reading and the memory unit has no search function (command). Accordingly, like the Poco Watcher11in this embodiment, when a search operation is implemented using a normal memory (the memory unit62), an input search key needs to be handled as an address. Action data can be acquired from the memory by using an address of the memory as a search key, defining data of the memory as actions, and inputting search data as an address. However, according to this method, when a bit width which is used as a search key is long, there is a problem in that a memory capacity becomes enormous. For example, in the case of a search key with a length of 64 bits, the total capacity of the memory is 2{circumflex over ( )}64 (≈16×10{circumflex over ( )}18), which is much larger than a memory capacity which can be implemented in the semiconductor technology on the occasion of filing the present application.

Therefore, the search unit51aof this embodiment further includes the hash generator61in addition to the memory unit62. The hash generator61reduces a bit length of an input search key using a hash function. For example, the hash generator61compresses an input of a search key with a length of 64 bits to an output with a width of 16 bits. In this way, the search unit51aof this embodiment reduces a bit length which can be searched using the hash generator61therein and enables a search operation in consideration of a limit or restriction of a mounting capacity of the memory unit62.

Since the search key is compressed, there is a problem in that the address cannot be distinguished from another address. In order to solve this problem, the search unit51aof this embodiment further includes the comparator63in addition to the hash generator61and the memory unit62. At the time of reading from the memory cell array621via the sense amplifier & selector623, the comparator63reads a stored search key in addition to an action result, compares the read search key with the input search key, and finally determines hit/miss. Patent Document 3 can be referred to for further details of the search unit51a.

Here, in the Poco Watcher11illustrated inFIG. 5, the statistical information processing unit52aand the arithmetic operation unit53aare further provided in addition to the search unit51a. This is because, when the Poco Watcher is configured using only the search unit51a, there is a problem in that flexibility is insufficient for a search table that changes according to the application. For example, when IP addresses in network devices such as routers are listed in a search table, a capacity for storing data of about several millions of entries is required for IPv4. In the case of IPv6, since a search key has 64 bits but there are a large number of entries, a large search table is necessary. In recent information centric network (ICN) or content centric network/data centric network (CCN/DCN), a search key with a long bit length is required for controlling a route using a character string. In this way, there is a problem in that a single device such as the search unit51acannot cope with various applications for causing the routing control unit31or the traffic monitoring unit33illustrated inFIG. 3or the clustering unit37or the ranking unit38illustrated inFIG. 4to function or a waste occurs. In order to solve this problem, the Poco Watcher11illustrated inFIG. 5is further provided with the statistical information processing unit52aand the arithmetic operation unit53ain addition to the search unit51a.

For example, forwarding of a router or the like among applications of a search engine will be considered. The forwarding is implemented by the routing control by the routing control unit31illustrated inFIG. 3. The forwarding requires a process of determining a port number to which a packet is output from a destination address or the like which is described in the header of the packet. Here, it is assumed that a method of uniquely determining an output port number when a destination is determined is employed. For example, a table in which a relationship between a destination address and the like and an output port is described is used to determine a port number. In this case, when the same destination or the same output port is selected many times, congestion of traffic occurs. Since bypass of traffic is not possible in the method of unique determination, the forwarding employs a method of accumulating an amount of data of each flow and determining an output port in consideration of the amount of data thereof. According to this method, when a specific flow is hit many times, the output port is biased and congestion of traffic occurs. Accordingly, a process of counting the number of times of hit of each flow or an amount of traffic flowing is necessary to avoid such congestion. That is, a process of accumulating statistical information and constructing an efficient network is necessary.

In order to realize this process using a single chip, the Poco Watcher11illustrated inFIG. 5is further provided with the statistical information processing unit52aand the arithmetic operation unit53ain addition to the search unit51a.

The statistical information processing unit52aincludes a memory unit71to accumulate statistical information required for the above-mentioned process. The memory unit71has the same hardware configuration as a normal memory. That is, the memory unit71includes a memory cell array711, a decoder712, and a sense amplifier & selector713. In this way, the memory unit71that is used to accumulate the statistical information is not a special memory cell but is a normal memory cell and thus the configuration illustrated inFIG. 5can be implemented using a single chip such as the Poco Watcher11. In order to accumulate the statistical information, the memory unit71accumulates information corresponding to flows which are hit by the search unit51a(the search engine). That is, the memory unit71correlates an address with each hit search key and accumulates the statistic information in the addresses.

The arithmetic operation unit53areceives a hit/miss determination result from the comparator63, reads a unique address corresponding to a search key of a hit when the hit/miss determination result indicates the hit, accesses the memory unit71on the basis of the read address, and reads statistical information. The adder81of the arithmetic operation unit53updates the read statistical information by adding data thereto and rewrites the updated statistical information to the same address of the memory unit71. In this way, the adder81is a device that adds data to the read data. Addition of the adder81is performed only when the search unit51ahas hit. The adder81adds plus 1 when the statistical information is the number of packets, and adds a packet size described in the header of the packet to the read data when the statistical information is the packet size. Here, it is necessary to compare the data read from the memory unit71with the search key for the hit/miss determination. Accordingly, the operation of the adder81is controlled by a hit signal of the comparator63of the search unit51a.

The statistical information is accumulated in the memory unit71through this series of operations.

Similarly to the Poco Watcher11ain the example illustrated inFIG. 5, the Poco Watcher11bin the example illustrated inFIG. 6includes a search unit51b, a statistical information processing unit52b, and an arithmetic operation unit53b. In the example illustrated inFIG. 6, the memory unit62of the search unit51band the memory unit91of the statistical information processing unit52bare integrally formed. Accordingly, by writing data for statistic information to the same row as an action of the memory cell array621for search in the memory cell array911for statistical information, functions (for example, the above-mentioned routing control) equivalent to those in the example illustrated inFIG. 5can be implemented. As specific operations, the hash generator61inputs data (a search key) such as a destination input from the outside to a hash function to reduce the number of bits. The reduced data is used as an address of the memory (the memory unit62and the memory unit91). When an action as a search result is input to data in the memory, a search operation can be implemented. When an action is read from the memory cell array621on the search unit51bside, statistical data described in the same row in the memory cell array911on the statistical information processing unit52bside is read. When the search result indicates a hit, the arithmetic operation unit53updates the read statistical information and rewrites the updated statistical information to the same row in the memory cell array911on the statistical information processing unit52bside. On the other hand, when statistical information is read, a search key is input and statistical information stored in the address corresponding to the search key in the statistical information accumulated in the memory cell array911is read.

FIG. 7illustrates an enlarged view of the memory cell array911, the sense amplifier & selector912, and the arithmetic operation unit53bin the Poco Watcher11bin the example illustrated inFIG. 6. As illustrated inFIG. 7, each memory cell (a memory cell constituted by a word line and two bit lines) configuring the memory cell array911is connected to two sense amplifiers, a selector, and an adder81. Accordingly, although not illustrated in the drawing, the adder81may be inserted into the memory unit91. In this case, the time after being read and until being written can be reduced.

FIG. 8is a schematic diagram illustrating a router function in which the functions of the routing control unit31and the buffer unit34illustrated inFIG. 3are combined. As described above, the routing control unit31can be implemented by the configuration of the example illustrated inFIG. 5or the example illustrated inFIG. 6in the Poco Watcher11. Input data (such as a packet) for setting a route in the routing control unit31is input to an input buffer341N of the buffer unit34. On the other hand, data (such as a packet) of which a route has been set by the routing control unit31is input to an output buffer34OUT (one of four output buffers34OUT in the example illustrated inFIG. 8) connected to the output port to which one route has been set among a plurality of output ports (output ports #1 to #4 in the example illustrated inFIG. 8). Here, the output buffers34OUT employ a configuration of a queue such that data with higher priority can be output earlier as illustrated inFIG. 8. That is, by dividing the output buffers34OUT into FIFOs corresponding to the number of queues, FIFO queues input in the order of priorities can be controlled. The FIFO can be constituted by a standard memory.

As described above, in the Poco Watcher11, the search engine (the search unit51aillustrated inFIG. 5or the search unit51billustrated inFIG. 6) is configured to include a standard memory (the memory unit62illustrated inFIG. 5 or 6), and the memory (the memory unit71illustrated inFIG. 5or the memory unit91illustrated inFIG. 6) that stores the statistical information is also configured to include a standard memory. Accordingly, the network functions required for a data plane of a router or a network switch, that is, routing control, bandwidth control, traffic monitoring, buffering, and access control can be implemented by the one-chip Poco Watcher11(seeFIG. 3).

Specifically, the routing control can be mainly implemented by the configuration (such as the search engine) illustrated inFIG. 5 or 6as described above. That is, in the routing control, a destination address of an input packet is input to the search units51aand51b, and a packet is output to a specific output buffer34OUT (seeFIG. 8) in response to an action output from the search units51aand51b.

The bandwidth control can be implemented by the FIFO queue of the output buffer34OUT illustrated inFIG. 8as described above. That is, an amount of data which is output is limited by the FIFO provided in the output buffer34OUT. When an amount of data input from the input buffer341N is larger than an amount of data output, data is accumulated in the FIFO of the output buffer34OUT.

The traffic monitoring can be implemented by analyzing statistical information stored in the memory unit71illustrated inFIG. 5or the memory unit91illustrated inFIG. 6. That is, the traffic monitoring is performed by reading data stored in the memory unit71of the statistical information processing unit52aor the memory unit91of the statistical information processing unit52band checking data values thereof. For example, whether an amount of specific data is large, whether an amount of specific data has increased rapidly, or the like is checked from the read data. An entity of the checking operation is, for example, the CPU13illustrated inFIG. 1.

The buffer can be implemented by the FIFO or the like as described above (seeFIG. 8). That is, the buffer temporarily stores data until a route of an input packet is determined. Similarly to the bandwidth control, data is accumulated in the FIFO until being output.

The access control (filtering) can be implemented by a search engine. Details of the access control will be described later with reference toFIG. 10.

The above description is summarized as follows. The information processing system according to this embodiment can easily realize extension of the network functions by only connecting the Poco Watcher11configured as a single chip to the network processor12.

Specifically, in the related art, a packet input from the outside is input from a predetermined communication device (for example, the communication device14ainFIG. 14), a destination thereof is determined by the network processor12serving as a switch chip, and the packet is output to another communication device (for example, the communication device14binFIG. 14) or the same communication device (for example, the communication device14ainFIG. 14). In order to extend the network functions such as routing control, bandwidth control, access control, traffic monitoring, and buffering, a special memory (the TCAM501or the SRAM502) was required in addition to the DRAM503inFIG. 14.

On the other hand, in the information processing system according to this embodiment, it is possible to easily realize extension of the network functions by only connecting the Poco Watcher11to the network processor12. In the Poco Watcher11, the network functions such as routing control, bandwidth control, access control, traffic monitoring, and buffering are implemented by a single chip.

For example, when the information processing system has the configuration example illustrated inFIG. 2A, the Poco Watcher11is interposed between the communication device14aand the network processor12. In this case, the constituent part in the example illustrated inFIG. 5or the example illustrated inFIG. 6in the Poco Watcher11accumulates statistical information of a packet and outputs the statistical information in response to a request from the CPU13. The CPU13determines whether a flow is biased on the basis of the statistical information. This determination result is fed back to the network processor12serving as a switch chip. The network processor12controls selection of a port from which the packet is output on the basis of the feedback information. In this way, the routing control is implemented by the Poco Watcher11. In this case, the Poco Watcher11can also be used as a buffer that temporarily stores a packet input from the outside. The Poco Watcher11can also be used as a buffer at the time of outputting a packet. In this way, the bandwidth control of limiting an amount of data to be output is implemented by the Poco Watcher11.

For example, when the information processing system has the configuration example illustrated inFIG. 1, the Poco Watcher11is disposed on the network processor12side and thus can complement the performance of the network processor12. Accordingly, extension of a buffer size, extension of statistical information, extension of routing control, and the like can be realized as extension of the network functions of the network processor12. Here, the extension of statistical information means that, for example, a function of storing only statistical information for each input port is extended to a function of storing statistical information for each flow. By this extension of statistical information, the number of types of statistical information increases and thus fine control is possible.

For example, the information processing system may have the configuration example illustrated inFIG. 2Bfor applications of monitoring only packets input from a WAN which is an external network which is not illustrated or which are output to the WAN side.

While an embodiment of the invention has been described above, the invention is not limited to the embodiment, and modification, improvements, and the like within a range in which the object of the invention can be achieved are included in the invention.

For example, the search engine is used for various applications. Specifically, the search engine can be applied for pattern authentication such as face authentication. When the search engine is applied in this way, a bit width of an input search key depends on the applications. Accordingly, by employing a method of increasing a bit width of a search key, it is possible to cope with all applications, which may seem to be advantageous. However, this method has a problem in that the time for inputting a search key is elongated and system performance deteriorates as a result. A memory capacity for comparison with the search key is necessary inside a device and extra resources are consumed. A problem that the number of entries decreases for the same memory capacity also occurs.

The search engine in the above-mentioned embodiment, that is, the search unit51ain the example illustrated inFIG. 5or the search unit51bin the example illustrated inFIG. 6, has difficulty in solving such problems. Therefore, in order to solve these problems, a search engine capable of switching the configuration thereof using a mode register can be employed. Accordingly, the number of entries becomes a half and the number of bits of a search key doubles. By switching the configuration depending on applications, it is possible to provide configurations which are suitable for various types of applications using a single device (the Poco Watcher11).

That is, a search engine that can switch between the configurations is illustrated inFIG. 9. That is,FIG. 9illustrates an example of a hardware configuration of the search engine in the Poco Watcher11which is different from the examples illustrated inFIGS. 5 and 6.

As illustrated inFIG. 9, a search unit51cincludes an address conversion circuit100, a main search unit92A, a main search unit92B, and a selection circuit93. Here, the main search unit92A and the main search unit92B basically have the same functions and configurations as the search unit51ain the example illustrated inFIG. 5and thus detailed description thereof will not be repeated.

In the example illustrated inFIG. 9, a search engine is divided into two parts of the main search unit92A and the main search unit92B. A mode set (a signal of a mode register) is input to the address conversion circuit100and the selection circuit93. That is, an input address is switched by the mode set in the address conversion circuit100, and a search result is switched by the mode set in the selection circuit93.

For example, in the example illustrated inFIG. 9, when the number of entries doubles, the address conversion circuit100inputs the same search key to the two divided search engines, that is, the main search unit92A and the main search unit92B. Among actions output from the main search unit92A and the main search unit92B, an action result in which a hit signal is activated is selected and output as a search result by the selection circuit93. When miss signals are output from the main search unit92A and the main search unit92B, the selection circuit93outputs a miss.

For example, the example illustrated inFIG. 9, when the bit width of a search key doubles, the address conversion circuit100divides the input search key into first half bits and second half bits, inputs the first half bits to the main search unit92A, and inputs the second half bits to the main search unit92B. When hit signals are activated from the main search unit92A and the main search unit92B, the selection circuit93outputs an action result to be a hit. When a miss signal is output from at least one of the main search unit92A and the main search unit92B, the selection circuit93outputs a miss.

In the example illustrated inFIG. 9, the search engine is divided into two parts, but the number of divided parts of the search engine is not limited thereto and may be, for example, four. When the search engine is divided into four parts, the number of entries can be switched to one time, double, and quadruple.

Now, the access control (filtering) using a search engine will be described. The filtering is roughly classified into a black list method and a white list method. The black list method is a method of outputting information other than information of search keys including existing bit strings described in a black list. The white list method is a method of outputting information of search keys described in a white list. In the black list method, it is assumed that bit strings in which higher three bits of a search key of four bits are “000” are described in a black list. In this case, both search results in which the search keys are “0001” and “0000” should be excluded. In this case, “0001” and “0000” may be input as a search key to the search engine two times and search results may be individually output, but both search results of “0001” and “0000” can be output by providing a mask function to the search key and only inputting “000*” of which the lower 1 bit has been masked as a search key one time. In this way, when the black list method is employed, it is possible to reduce a process time or a process load of the search engine by providing a mask function to the search key.

There is also an application of outputting a high-ranked candidate. For example, there is an application of searching for a way to an art gallery and outputting a plurality of candidates as search results. Even when a plurality of candidates are output as search results, a mask function can be input to the search key.

FIG. 10illustrates an example of the hardware configuration of the search engine in the Poco Watcher11which is different from the examples illustrated inFIGS. 5, 6, and 9. As illustrated inFIG. 10, a search unit51dincludes a main search unit101A, a main search unit101B, and a selection circuit102. Here, the main search unit101A and the main search unit101B basically have the same functions and configurations as the search unit51ain the example illustrated inFIG. 5and thus detailed description thereof will not be repeated. When a search key is masked, the number of bits of an input search key decreases. However, since it is necessary to construct a configuration capable of outputting a plurality of actions as a search result, the configuration illustrated inFIG. 10is employed. Here, when a mask signal is activated, the selection circuit102outputs a result from the search engine corresponding to a search table corresponding to the mask.

As described above with reference toFIG. 9 or 10, it is possible to provide a device (the Poco Watcher11) which is suitable for various applications by dividing an internal search engine, changing an input search key, and changing determination as a search result.

In this way, the method of changing specifications by switching the functions of a search engine using a mode set or the like is suitable as the method of coping with various applications, but the invention is not limited to the method. For example, a method of using a plurality of LSIs (Poco Watchers11) on which a single search engine is mounted may be employed as another method.

FIG. 11illustrates a configuration example of an information processing system according to an embodiment of the invention, where the information processing system employs two search engines. In the example illustrated inFIG. 11, search engines111A and111B are connected to a search engine controller110of a network processor12. By employing this configuration, the capacity of a search table, that is, the number of entries, can double. At the time of search, search keys are simultaneously input to the two search engines111A and111B. The search engine controller110confirms the search results output from the two search engines111A and111B and uses one of the two search engines111A and111B which has hit. It is possible to enlarge a search table through this operation.

When a search table with a large capacity is constructed, different tables are written to the search engine111A and the search engine111B. Accordingly, a situation in which both the search engines111A and111B hit simultaneously does not occur at all. When a large-capacity table is constructed, writing of a table is first performed on the first search engine111A, as illustrated inFIG. 12. When this writing has succeeded, writing of a table is not performed on the second search engine111B. On the other hand, when writing of a table to the first search engine111A fails, writing of a table to the second search engine111B is performed.

Extension of a search table using a plurality of search engines (two search engines111A and111B in the example illustrated inFIGS. 11 and 12) can be implemented by outputting a determination result of whether writing has been completed and “succeeded” or “failed” from the search engines (two search engines111A and111B in the example illustrated inFIGS. 11 and 12).

The search engine controller110may determine whether writing has succeeded. However, since the same functions as the search engines111A and111B are provided in the search engine controller110, resources become insufficient in many cases. The resources are wasted, which cannot be said to be a good method. Conversely, a search table can be simply extended by using a writing completion signal. An example in which a search table is extended to double has been described above, but the invention is not limited thereto. When the number of search engines (LSIs) increases, it is possible to easily realize extension of the capacity of the search table in proportion thereto.

In the above-mentioned embodiment, the Poco Watcher11is mounted on a board in a server or a PC (one casing) along with a CPU or a network controller, but the mounting example is not particularly limited thereto. For example, as illustrated inFIGS. 13A and 13BorFIG. 14, a configuration in which the Poco Watcher11is configured as one device (one casing) and is connected to another device (one casing) may be employed.FIGS. 13A and 13Bare block diagrams illustrating a configuration example of the information processing system according to the embodiment of the invention which is different from the example illustrated inFIG. 1orFIGS. 2A and 2B. In the information processing system in the example illustrated inFIG. 13A, the Poco Watcher11is connected between an L2 switch203connected to a router202and a plurality of PCs204ato204d. A network controller201is connected to the router202, the L2 switch203, and the Poco Watcher11. In the information processing system in the example illustrated inFIG. 13B, the Poco Watcher11is connected between a router202and two L2 switches203A and203B. The network controller201is connected to the router202and the Poco Watcher11. A plurality of PCs204ato204care connected to the L2 switch203A. A plurality of other PCs204dto204fare connected to the L2 switch203B.

FIG. 14is a block diagram illustrating a configuration example of the information processing system according to the embodiment of the invention which is different from the example illustrated inFIG. 1,FIGS. 2A and 2B, orFIGS. 13A and 13B. In the information processing system in the example illustrated inFIG. 14, a router301, enterprise-grade routers302-1and302-2, and consumer-grade routers303-1to303-3are present as devices constituting a network N. A network controller401in the example illustrated inFIG. 14is a device that looks down on information on the network N as a whole. That is, the information processing system in the example illustrated inFIG. 14implements a software defined network (SDN). In order to implement the SDN, the network controller401needs to acquire states of the individual devices constituting the network N and to control the individual devices on the basis of the acquired information. Accordingly, in the related art, since a configuration in which the network controller401and the devices of the network N communicate directly with each other was employed which is not illustrated, it is very difficult to implement the SDN for the following reasons. The first reason is that the individual devices are provided by different makers. Furthermore, some devices support the SDN and some devices do not support the SDN. The second reason is that routers are further simplified, for example, by network function-virtualization (NFV) FV according to a future technical trend. Therefore, in the information processing system in the example illustrated inFIG. 14, Poco Watchers11-1to11-5are connected to the individual devices of the network N and the network controller401communicates with the Poco Watchers11-1to11-5(hereinafter collectively referred to as “Poco Watcher11”). The Poco Watcher11performs traffic monitoring (collection of data) and performs a variety of control. That is, the Poco Watcher11transmits traffic data to the network controller401and receives control data from the network controller401. In this way, the Poco Watcher11has a function of monitoring traffic of the connected individual device of the individual devices, acquiring data, and transmitting the acquired data to the network controller401and a function of receiving control information and controlling the connected individual device of the individual devices on the basis of the control information when data of the individual devices is analyzed and the control information for the individual devices is generated and transmitted by the network controller401.

In other words, the memory device according to the invention can have the following configurations and can be embodied in various embodiments including the above-mentioned embodiment. That is, the memory device according to the invention may be a memory device (for example, the Poco Watcher11illustrated inFIG. 1orFIGS. 2A and 2B) that is configured as single chip, in which the memory device allows at least routing control, bandwidth control, traffic monitoring, buffering, and access control of network functions to function (for example, the memory device has the functional configuration illustrated inFIG. 3). By employing the memory device having this configuration, it is possible to easily realize extension of a network function with low cost and low power consumption on the occasion of NFV or commodification of networks.

Here, the memory device may include: a search unit (for example, the search unit51aor51billustrated inFIG. 5 or 6) that includes a first memory unit (for example, the memory unit62illustrated inFIG. 5 or 6) and performs a search operation of referring to an input search key for data stored in the first memory unit; a statistical information processing unit (for example, the statistical information processing unit52aor52billustrated inFIG. 5 or 6) that correlates an address of the first memory unit with a search key which is hit by the search unit and includes a second memory unit (for example, the memory unit71illustrated inFIG. 5or the memory unit91illustrated inFIG. 6) that stores statistical information of the address; and an arithmetic operation unit (for example, the arithmetic operation unit53aor53billustrated inFIG. 5 or 6) that updates the statistical information whenever the search unit hits.

The search unit (for example, the search unit51cillustrated inFIG. 9) may have a function of changing a bit width of a search key.

The search unit (for example, the search engines111A and111B illustrated inFIG. 11) may have a function of outputting a determination signal indicating whether writing of information has succeeded or failed.

The search unit (for example, the search unit51dillustrated inFIG. 10) may selectively perform the access control using a white list method and the access control using a black list method.

The memory device may be provided to be connected to each individual device in an information processing system including individual devices (for example, the router301, the enterprise-Grade routers302-1and302-2, and the consumer-grade routers303-1to303-3which constitute the network N inFIG. 14) constituting a network and a network controller (for example, the network controller401illustrated inFIG. 14) controlling the individual devices, and the memory device (for example, the Poco Watchers11-1to11-5illustrated inFIG. 14) may have: a function of monitoring traffic of one connected individual device of the individual devices, acquiring data, and transmitting the acquired data to the network controller; and a function of receiving control information and controlling one connected individual device of the individual devices on the basis of the control information when data of the individual devices is analyzed and the control information for the individual devices is generated and transmitted by the network controller.

The Poco Watcher11can be embodied as a DDR DRAM dedicated for a network as described above, but may be embodied by selectively adding network functions to a general-purpose DDR DRAM as illustrated inFIG. 16. Here, a general-purpose DRAM refers to a DRAM which is standardized in the JEDEC.

A Poco Watcher11cillustrated inFIG. 16is formed in a DDR DRAM and has a configuration which is selectively usable for a network and for a general-purpose PC. A hash generator61is provided outside the DDR DRAM, and a memory unit62or91and a network function unit601such as a comparator68and an adder81are formed in the DDR DRAM. Here, the network function unit601has the functional configuration illustrated inFIG. 3. A selector602is provided in the DDR DRAM. That is, when the selector602is switched to an upper route inFIG. 16, that is, a route passing through the memory unit62or91and the network function unit601such as the comparator68and the adder81, the Poco Watcher functions as a DDR DRAM for a network. On the other hand, when the selector602is switched to a lower route inFIG. 16, that is, a route from the memory unit62or91directly to the selector602, the Poco Watcher functions as a general-purpose DDR DRAM. The selector602can be suitably mounted using at least one of a metal mask and an address key.

FIG. 17is a diagram illustrating a connection state of the Poco Watcher11c(which functions as a DDR DRAM for a network) illustrated inFIG. 16. As illustrated inFIG. 17, the Poco Watcher11c(which functions as a DDR DRAM for a network) can be connected to a controller701as an IP of an FPGA or an ASIC. Accordingly, it is possible to implement a function capable of performing parallel comparison like a TCAM. Here, as illustrated in a lower-right part ofFIG. 17, a general-purpose DRAM is originally provided with a comparator group812for use in a test mode in addition to a memory unit811. The comparator group812without any change can be used for the network function unit601illustrated inFIG. 16.

FIGS. 18A and 18Bare diagrams illustrating comparison of the configuration example of the information processing system including the Poco Watcher11c(which functions as a DDR DRAM for a network) illustrated inFIG. 16with the configuration example of the information processing system according to the related art for implementing the network function.

FIG. 18Aillustrates a configuration example of the information processing system according to the related art for implementing the network functions. As described above with reference toFIG. 15, in the information processing system according to the related art for implementing the network functions, the network functions are implemented by connecting a plurality of TCAMs, RLDRAMs, and QDR/DDR SRAMs to an NP, an ASIC, an FPGA, or the like. A plurality of TCAMs, RLDRAMs, and QDR/DDR SRAMs are components with high prices and high power consumption. Since it is predicted that prices of the components will not decrease due to a small market scale (no economies of scale), it is predicted that the components will have high prices. There is also a demerit that interfaces from an NP, an ASIC, an FPGA, or the like to the components are particularly necessary.

FIG. 18Billustrates a configuration example of the information processing system including the Poco Watcher11c(which functions as a DDR DRAM for a network) illustrated inFIG. 16to which the invention is applied. All the network functions (FIG. 3) are incorporated into the Poco Watcher11c. The Poco Watcher11cis formed on a general-purpose DDT2(3, 4) DRAM. That is, the selector602(FIG. 16) is implemented using at least one of a metal mask (a wired layer) and an address key (a mode register), and the DDT2 DRAM can be switched into either for a general-purpose PC or for a network. Here, since the comparator group812is provided in the DDT2 DRAM for use in a test mode in advance (FIG. 17), it is not necessary to provide a new element by using the comparator group for the network function unit601. Accordingly, it is possible to decrease a memory price for a network and to implement an information processing system with low prices and low power consumption due to a price premium of a general-purpose DDR. Since the network functions are integrated on the Poco Watcher11c, an interface between the Poco Watcher11cand the controller701of an IP of an NP, an ASIC, an FPGA, or the like has only to be provided as illustrated inFIGS. 18A and 18B. That is, the interfaces can be unified.

EXPLANATION OF REFERENCE NUMERALS