Method of forming miniaturized polycrystalline silicon gate electrodes using selective oxidation

Ultra narrow and thin polycrystalline silicon gate electrodes are formed by patterning a polysilicon gate precursor, reducing its width and height by selectively oxidizing its upper and side surfaces, and then removing the oxidized surfaces. Embodiments include patterning the polysilicon gate precursor with an oxide layer thereunder, ion implanting to form deep source/drain regions, forming a nitride layer on the substrate surface on each side of the polysilicon gate precursor, thermally oxidizing the upper and side surfaces of the polysilicon gate precursor thereby consuming silicon, and then removing the oxidized upper and side surfaces leaving a polysilicon gate electrode with a reduced width and a reduced height. Subsequent processing includes forming shallow source/drain extensions, forming dielectric sidewall spacers on the polysilicon gate electrode and then forming metal silicide layers on the upper surface of the polysilicon gate electrode and over the source/drain regions.

TECHNICAL FIELD

The present invention relates to the fabrication of miniaturized semiconductor devices comprising transistors with a gate electrode having a significantly reduced height and width. The present invention is particularly applicable to ultra large scale integrated circuit systems having features in the deep sub-micron regime.

BACKGROUND ART

As the drive for faster miniaturized semiconductor devices proceeds apace, it becomes increasingly more difficult to fabricate device features without engendering disadvantages. It is particularly challenging to form gate electrodes having a reduced height and a reduced width, such as a height less than 1,000 Å and a width less than 500 Å, without creating various issues. For example, it is extremely difficult to pattern a gate electrode having a width less than 500 Å by conventional photolithographic techniques with any degree of precision and reproducibility. Moreover, as the gate width decreases, the aspect ratio of the gate electrode disadvantageously increases. However, the gate electrode must be sufficient high to prevent impurity ion penetration therethrough into the underlying gate dielectric layer with an attendant decrease in reliability, as during ion implantation to form deep source/drain regions. Moreover, a high gate height contributes to fringing capacitance between the gate electrode and associated source/drain regions.

Accordingly, a need exists for methodology enabling the fabrication of semiconductor devices comprising transistors having a gate electrode with a reduced width and also a reduced height. There exists a particular need for methodology enabling the fabrication of semiconductor devices comprising transistors with a gate electrode having a width less than 500 Å and a height less than 1,000 Å.

DISCLOSURE OF THE INVENTION

An advantage of the present invention is a method of manufacturing a semiconductor device comprising a transistor having a miniaturized gate electrode with reduced fringing capacitance.

Another advantage of the present invention is a method of fabricating a semiconductor device comprising a transistor having an accurately dimensioned gate electrode with a height less than 1,000 Å and a width less than 500 Å, without adversely impacting gate dielectric integrity and transistor reliability while preserving the advantageous device performance associated with deep source/drain implants required for good contacts.

Another advantage of the present invention is a method of fabricating a semiconductor device comprising transistors having a gate electrode width less than 500 Å and a height less than 1,000 Å with significantly less demanding photolithographic capabilities which would otherwise be required for such small gates.

According to the present invention, the foregoing and other advantages are achieved in part by a method of manufacturing a semiconductor device, the method comprising: forming a polysilicon gate electrode precursor having first side surfaces at a first width and a first upper surface at a first height, over a main surface of the semiconductor substrate with a gate insulating layer therebetween; selectively oxidizing the first side surfaces and first upper surface of the polysilicon gate electrode precursor to form oxidized layers thereon; and removing the oxidized layers from the polysilicon gate electrode precursor to form a polysilicon gate electrode having second side surfaces at a second width less than the first width and a second upper surface at a second height less than the first height.

Embodiments of the present invention comprise ion implanting impurities, using the polysilicon gate electrode precursor as a mask, to form deep source/drain regions; forming nitride layers on the main surface of the semiconductor substrate over the deep source/drain layers on opposite sides of the polysilicon gate electrode precursor; selectively oxidizing the first side surfaces and first upper surface of the polysilicon gate electrode precursor to form the oxidized layers thereon, removing the oxidized layers from the polysilicon gate electrode precursor to form the polysilicon gate electrode, removing the nitride layers, and ion implanting impurities, using the polysilicon gate electrode as a mask, to form source/drain extensions. Embodiments of the present invention further include forming dielectric sidewall spacers on the second side surfaces of the polysilicon gate electrode and forming metal silicide layers on the second upper surface of the polysilicon gate electrode and on the main surface of the semiconductor substrate over the deep source/drain regions. Embodiments of the present invention enable formation of polysilicon gate electrodes having a height less than 1,000 Å, such as 300 Å to 900 Å, and a width less than 500 Å, such as 150 Å to 400 Å.

DESCRIPTION OF THE INVENTION

The present invention addresses and solves problems attendant upon fabricating miniaturized semiconductor devices, particularly transistors having a miniaturized gate electrode, such as a gate electrode with a height less than 1,000 Å and a width less than 500 Å. Conventional photolithographic techniques are limited in their ability resolution capabilities and, hence, cannot be used to pattern gate electrodes with a width less than 500 Å with the requisite precision and reproducibility. Reduction of the gate width disadvantageously increases the aspect ratio of the gate electrode. However, the gate electrode must be sufficiently high to prevent implanted impurities from penetrating therethough into the underlying gate oxide layer with attendant degradation thereof, as during ion implantation to form deep source/drain regions.

The present invention addresses and solves such problems by forming a gate electrode precursor having a first width fully within the resolution capability of conventional photolithographic techniques and at a first height sufficient to prevent impurity ion penetration therethrough into the underlying gate dielectric layer. In accordance with the present invention, the side surfaces and upper surface of the originally formed gate electrode precursor are selectively oxidized, thereby consuming silicon from the side surfaces and upper surface of the gate electrode precursor. Subsequently, the oxidized layers are removed from the side surfaces and upper surface of the gate electrode precursor leaving the finally dimensioned gate electrode having a reduced height and reduced width.

An embodiment of the present invention is schematically illustrated inFIGS. 1 through 8, adverting toFIG. 1, an oxide layer11is formed over a main surface of the semiconductor substrate10. A polycrystalline silicon layer is deposited and patterned in a conventional manner employing conventional photolithographic techniques to yield a polysilicon gate precursor12having a width fully within the resolution capabilities of conventional photolithographic techniques. For example, the polysilicon gate precursor12may have a height (H1) greater than 1,000 Å, such as 1,000 Å to 1,500 Å, and a width (W1) greater than 500 Å, e.g., 500 Å to 800 Å. During patterning, the gate oxide layer11may optionally remain on the main surface of the semiconductor substrate10on opposite sides thereof of gate electrode precursor12or may be removed during gate electrode precursor patterning.

Adverting toFIG. 2, ion implantation is then conducted, using gate precursor12having the height H1greater than 1,000 Å, followed by rapid thermal annealing to form deep source/drain regions20. The height H1of gate electrode precursor12is sufficient to prevent impurity ions from penetrating therethrough into gate oxide layer11.

Adverting toFIG. 3, a protective dielectric layer30is then formed on the main surface of semiconductor substrate10overlying deep source/drain regions20on opposite sides of polysilicon gate precursor12. Layer30can comprise silicon nitride deposited by chemical vapor deposition at a thickness of 50 Å to 300 Å.

Subsequently, as shown inFIG. 4, oxidation is implemented, as by heating in an oxidizing atmosphere to oxidize the side surfaces of polysilicon gate electrode precursor12forming oxidized surfaces40thereon, as at a thickness of 100 Å to 700 Å. The selectively oxidized surfaces40consume silicon from the polysilicon gate etched precursor12thereby reducing its lateral and vertical dimensions.

As shown inFIG. 5, the oxidized surfaces40are removed, as are nitride layers30and the extension of the gate oxide layer11. The resulting intermediate structure, as shown inFIG. 5, comprises gate electrode50having a reduced height H2less than 1,000 Å, such as 300 Å to 1,000 Å, and a reduced width W2less than 500 Å, such as 100 Å to 500 Å. Removal of the oxidized layers40and11can be implemented in a conventional manner using selective etchants, such as a buffered hydrofluoric acid solution. Removal of the nitride layer30can be implemented in a conventional manner, as with boiling phosphoric acid.

Subsequently, as shown ifFIG. 6, ion implantation is conducted, using miniaturized gate electrode50as a mask, to form shallow source/drain extension60. A silicon oxide or nitride liner70, as shown inFIG. 7, may be formed on the side surfaces of the gate electrode50and on a portion of the upper surface of semiconductor substrate10, as by chemical vapor deposition, or silicon oxide may be grown, as at a thickness of 20 Å to 200 Å. Silicon nitride/oxide sidewall spacers71are then formed, as by chemical vapor deposition at a thickness of 850 Å to 900 Å, on silicon oxide/nitride liner70. The silicon oxide/nitride liner70on top of polysilicon is etched off when the silicon nitride/oxide spacer71is etched. Subsequently, as illustrated inFIG. 8, the silicidation is conducted in a conventional manner, as by depositing a layer of metal, such as nickel, cobalt or tungsten, and then heating to react the deposited metal with the underlying silicon to form metal silicide layers80on the upper surface of gate electrode50and on the main surface of the semiconductor substrate10over deep source/drain regions20, resulting in the device illustrated inFIG. 8.

The present invention provides efficient methodology enabling the fabrication of miniaturized gate electrodes without pushing the limitations of conventional photolithographic techniques and without adversely impacting gate dielectric integrity. Advantageously, methodology in accordance with the present invention enables a reduction in not only the gate width but also the gate height, thereby avoiding disadvantages attendant upon a high aspect ratio. As the deep source/drain regions are prior to reducing the height of the gate electrode, gate oxide integrity issues are avoided, and device performance associated with deeper implants for good contacts is retained. The reduction in gate height also advantageously reduces fringing capacitance between the gate electrode and associated source/drain regions.

The present invention enjoys industrial applicability in manufacturing any of various types of semiconductor devices. The present invention is particularly applicable in manufacturing semiconductor devices with high operating speeds having design features in the deep sub-micron regime.

In the preceding detailed description, the present invention is described with reference to specifically exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the present invention, as set forth in claims. The specification and drawings are, accordingly, to be regarded as illustrative and not as restrictive. It is understood that the present invention is capable of using various other combinations, and environments and is capable of changes or modifications within the scope of the inventive concept as expressed herein.