Systems and methods for current management for digital logic devices

Systems and methods for Current Management of Digital Logic Devices is provided. In one embodiment, a method of current management for a digital logic circuit is provided. The method comprises drawing power to drive a digital logic integrated circuit; performing one or more switching operations with the digital logic integrated circuit; learning at least one bypass current setpoint based on a voltage powering the digital logic integrated circuit while performing the one or more switching operations.

CROSS REFERENCES

This application is also related to the following co-pending United States patent applications filed on even data herewith, which are hereby incorporated herein by reference:

U.S. patent application Ser. No. 11/340,245 entitled “Systems and Methods for Current Management for Digital Logic Devices”) and which is referred to here as the '949 application; and

U.S. patent application Ser. No. 11/340,287 entitled “Testing Control Methods for Use in Current Management Systems for Digital Logic Devices”) and which is referred to here as the '090 application.

TECHNICAL FIELD

The present invention generally relates to digital logic circuits and more specifically to current management for digital logic devices.

BACKGROUND

In the current state of the art, digital logic power-supply decoupling is achieved using decoupling capacitors. A digital logic device, due to its discrete nature, switches logic states between on and off. This digital switching causes transient currents to be generated, which must be supplied by the power distribution system. Typically, decoupling capacitors in proximity to the digital logic are used to supply the transient current. However, parasitic inductances are always present between the digital logic and the decoupling capacitor. These inductances react to changes in digital logic device current demand by producing voltages that impede the ability of decoupling capacitors to supply transient current to the digital logic. In simulations, it is apparent that this parasitic inductance is the prime limitation to the success of the decoupling capacitor in achieving its function—that of ensuring the power-supply voltage at the digital logic remains fixed at all times. Little has changed in the past 40 years, except incremental means of reducing the parasitic inductance between digital-logic integrated circuits and decoupling capacitors.

For the reasons stated above and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the specification, there is a need in the art for improved systems and methods for current management for digital logic devices.

SUMMARY

The Embodiments of the present invention provide methods and systems for current management and will be understood by reading and studying the following specification.

In one embodiment, a current management system for a digital logic circuit is provided. The system comprises a controllable current sink connected in parallel with a digital logic integrated circuit and adapted to draw a bypass current based on a control signal; and a current controller responsive to the digital logic integrated circuit and adapted to vary the bypass current in response to a priori information about an impending current need of the digital logic integrated circuit, the current controller adapted to output the control signal to the controllable current sink; and wherein the current controller is further adapted to adjust the bypass current to prevent a voltage across the digital logic integrated circuit from dropping below a reference voltage.

In another embodiment, a method of current management for a digital logic circuit is provided. The method comprises drawing power to drive a digital logic integrated circuit; performing one or more switching operations with the digital logic integrated circuit; and learning at least one bypass current setpoint based on a voltage powering the digital logic integrated circuit while performing the one or more switching operations.

In yet another embodiment, a current management system for a digital logic integrated circuit is provided. The system comprises means for controlling a bypass current, the means for controlling adapted to control the bypass current based on a priori information about an impending current need of a digital logic integrated circuit, wherein the bypass current is controlled to reduce discontinuities in a current supplied to the digital logic integrated circuit; means for drawing the bypass current, the means for drawing the bypass current connected electrically in parallel with the digital logic integrated circuit and responsive to the means for controlling; and means for limiting the bypass current to prevent a voltage powering the digital logic integrated circuit from dropping below a reference voltage, the means for limiting responsive to the means for controlling.

In accordance with common practice, the various described features are not drawn to scale but are drawn to emphasize features relevant to the present invention. Reference characters denote like elements throughout figures and text.

DETAILED DESCRIPTION

Embodiments of the present invention provide methods and systems for current management for digital logic devices. Embodiments of the present invention comprise systems and methods of reducing current demand variations on digital logic power supplies caused by digital logic switching, and thereby reduce impediments caused by parasitic inductance. Because the voltage developed across a parasitic inductance is equal to L times the change in current with respect to time, and the parasitic inductance is generally minimized, but never zero, embodiments of the present invention use: 1) a priori information about the impending current needs, and 2) current management circuitry to operate in parallel with the digital logic circuitry. The a priori information is used to ramp up or down the power supply current in advance of a digital-logic switching event to reduce di/dt, and thus reduce the transient parasitic voltage drop in the power supply system that would normally result.

FIG. 1is a block diagram illustrating a system100for managing current, of one embodiment of the present invention. System100comprises a digital logic integrated circuit110coupled to receive power (Vps) from a digital logic power supply120. In one embodiment, digital logic integrated circuit110is a small-scale integrated circuit (SSI) comprising gates that perform simple functions such as, but not limited to, AND, NAND, OR, NOR and INVERTER. In alternate embodiments, digital logic integrated circuit110comprises a high performance processor, such as, but not limited to, a microprocessor, and a digital signal processor. System100further comprises a current management system105. In one embodiment, current management system105includes a controllable current sink140and a current controller150. Controllable current sink140is coupled in parallel with power connections111and112of digital logic integrated circuit110as shown. Controllable current sink140is further coupled to receive a control signal from a current controller150, which in one embodiment is coupled to digital logic integrated circuit110.

In operation, when digital logic integrated circuit110performs a logic switching operation, the change in current demand (i3) of digital logic integrated circuit110is approximated by a step response, as illustrated generally byFIG. 3Bat320. In the absence of current management system105, parasitic inductances130between digital logic integrated circuit110and power supply120respond to such an abrupt change in current by generating a voltage response (VL=Ldi1/dt) as illustrated byFIG. 3Fat360. The generation of VLin between power supply120and digital logic integrated circuit110causes fluctuations in the voltage (VDLIC) available to power digital logic integrated circuit110.

Current management system105mitigates and limits the voltage VLgenerated by parasitic inductances130. In one embodiment, as described in detail by the '949 application herein incorporated by reference, prior to the digital logic integrated circuit110switching operation, controllable current sink140of current management system105ramps a bypass current (i2) up to an expected switching value Iswitch(shown inFIG. 3Cat332). Then, after the digital logic integrated circuit110switching operation, controllable current sink140ramps bypass current i2from Iswitchback to a steady state level (shown inFIG. 3Cat334). The resulting current (i1=i2+i3) from power supply120, shown generally inFIG. 3Dat340, comprises a first ramp342, a plateau344and a second ramp346. As would be appreciated by one skilled in the art upon reading this invention, the absence of abrupt current discontinuities in i1results in the generation of a transient parasitic voltage VL(shown inFIG. 3Eat350) that is significantly reduced compared to the spiking transient parasitic voltage VL(shown inFIG. 3Fat360) that would be produced by i3alone. Thus, the voltage (VDLIC) available to power digital logic integrated circuit110is consistently maintained within specification limits throughout the switching operation.

In one embodiment, controllable current sink140determines when to ramp up and ramp down bypass current i2via a control signal provided by current controller150. Current controller150outputs a control signal that is based on a priori information about the impending current needs of digital logic integrated circuit110. The a priori information can be obtained in a number of ways as described in the '949 application herein incorporated by reference.

In one embodiment of the present invention, in order to determine a maximum current for bypass current i2, system100observes the voltage drop in VDLICthat occurs during switching operations by digital logic integrated circuit110. In one embodiment, system100further comprises a voltage monitor (U1)160. In one embodiment, voltage monitor160comprises a comparator device having a non-inverting input connected to power terminal111of digital logic integrated circuit110, and an inverting input connected to a reference voltage VR. In one embodiment, the value of VRis based on a minimum voltage rating (Vmin required) for digital logic integrated circuit110, below which operation of digital logic integrated circuit110is not guaranteed. For many applications, a typical value for VRis 4.5 VDC. In an alternate embodiment, voltage monitor (U1)160comprises an analog to digital converter that converts a voltage measured at power terminal111to a digital signal. Note that, when using a comparator device for voltage monitor160, VRneed not be fixed, but in an alternate embodiment, VRis set to differing voltages to provide more detailed information. Similarly, in one embodiment, when voltage monitor160comprises an analog to digital converter, a high-speed analog-to-digital converter is utilized in lieu of a comparator circuit. In both cases, the detailed information captured and stored as discussed below is utilized to minimize the change in VDLICduring digital logic integrated circuit110operation.

In one embodiment, optimum operation of current management system105is obtained by ramping i2to a current level that allows VDLICto drop to exactly Vmin required(i.e., digital logic integrated circuit110's minimum required operating voltage). This optimized approach (illustrated byFIGS. 3G to 3J) consumes less power (i.e., the integral of I2*VDLICover time) than when controlling bypass current i2based strictly on reducing transient parasitic voltage VL. In one embodiment, when current controller150ramps bypass current i2in response to a priori information of a logic switching operation by digital logic integrated circuit110, bypass current i2is limited to maintain VDLICat or above Vmin required. In one embodiment, to reduce power consumption, the present invention adjusts one of the peak value of bypass current i2, the ramp rate of bypass current i2, and a transition time (e.g., starting at time t1and finishing at time t2as shown by example inFIG. 3G) for ramping bypass current i2, while allowing VDLICto drop all the way to Vmin required.

FIG. 3G(generally at370) illustrates an optimized bypass current i2(shown at371) controlled by current controller150to have a reduced peak current and slope when compared to a non-optimized bypass current i2(illustrated at372). The resulting current (i1=i2+i3) from power supply120shown generally inFIG. 3Hat380, comprises a first ramp382, a plateau384and a second ramp386. The transient parasitic voltage VLresulting from power supply120current transients is illustrated generally byFIG. 3Iat390and the corresponding optimized transient response of VDLICbyFIG. 3Jat395. Reducing the peak voltage of bypass current i2and allowing VDLICto drop to exactly Vmin requiredby controlling the ramp rate of bypass current i2, as digital logic integrated circuit110initiates a logic switching operation, thus reduces the total power that must be supplied by power supply120compared to non-optimized current management approaches. Note that for clarity of explanation inFIGS. 3A to 3J, all increasing and decreasing current ramps for bypass current i2are shown linearly increasing or linearly decreasing, with abrupt turn-on and turn-off at the beginning and end of the current ramps. Also, shown for clarity, i3is shown as a simplified pulse inFIG. 3B. However, one skilled in the art upon reading this specification would appreciate that i3will typically not be an ideal current pulse, and bypass current i2will typically be realized by gradual and generally non-linear increasing and decreasing current ramps, such that the sum of i2+i3yields a low di1/dt. Gradual and generally non-linear adjustments of bypass current i2reduce voltage change in VDLICduring digital logic operation.

The intended sequence of operation of system100includes two phases: a test phase, and a normal operation phase. During the first, or “test” phase, a test routine is executed to capture event data (i.e., event and timing data from digital logic integrated circuit110and VDLICdata from voltage monitor160) and generate time duration and bypass current i2data which is stored in data table168of memory165.

FIG. 1Bprovides a block diagram illustrating the flow of information within system100of one embodiment of the present invention. A test control method190(such as the test routines describe in the '090 Application herein incorporated by reference) collects VDLICinformation from voltage monitor160. In one embodiment, the VDLICinformation includes samples of the voltage, VDLICpowering digital logic integrated circuit110. In one embodiment, the VDLICinformation represents the difference between VDLICand reference voltage VR. Test control method190further collects event timing information from digital logic integrated circuit110. The timing information provides information as to when a logic event is executed by digital logic integrated circuit110. By pairing timing information received from digital logic integrated circuit110and VDLICinformation from voltage monitor160, test control method190can correlate the VDLICinformation associated with logic events. Test control method190provides event data obtained to one or both of current controller150and memory165to enable current controller150to control controllable current sink140and establish the desired bypass current i2characteristics during the test phase discussed below. As described below, event data includes information such as the identity of logic events, VDLICinformation associated with logic events, and bypass current i2characteristics associated with logic events. Then in one embodiment during the normal operation phase, when test control method190is no longer present, digital logic integrated circuit110provides one or both of logic event and timing information to enable current controller150to control controllable current sink140and establish the desired bypass current i2characteristics by accessing the event data stored in memory165during the test phase. Additional details regarding the test routine executed by digital logic integrated circuit110are described below and in the '090 Application herein incorporated by reference. In one embodiment, this test data is stored to correlate an event identifier, ramp duration time (e.g. t1, t2), and peak bypass current i2. In one embodiment, feedback from voltage monitor160is applied to reduce power consumption by minimizing i2peak current and/or i2transition time by allowing VDLICto drop exactly (within practical limits) to Vmin required, the DLIC's minimum guaranteed operating voltage.

During the second, or “normal operation” phase, one or more of event, time and VDLICdata obtained from the test phase and stored in data table168is used for input to the current controller150, which in turn, controls controllable current sink140producing the appropriate bypass current i2immediately preceding and following the execution of a digital logic operation event. Since, during the test phase, data stored in data table168produced an optimized VDLIC, digital logic integrated circuit110will operate with voltage meeting or exceeding Vmin requiredwith minimal power consumption. Note the inclusion of voltage monitor160in system100is not necessary while operating in the normal operation phase, but could be used for monitoring purposes. For example, in one embodiment, if while in the normal operation phase, VDLICdropped bellow Vmin requiredthen digital logic integrated circuit110one or both of sets an alarm flag and executes the test phase test routine.

In one embodiment, where the voltage drop in VDLICacross digital logic integrated circuit110is fairly consistent over time for a wide range of possible switching operations, current controller150is initially calibrated during the test phase to establish a single bypass current setpoint based on the received output of voltage monitor160. In one embodiment, the bypass current setpoint specifies one or more characteristics of bypass current i2including one or more of the peak current for bypass current i2, the ramp rate for bringing bypass current i2to the peak current level, and the transition time for bringing bypass current i2to the peak current level. In one embodiment, during the test phase, digital logic integrated circuit110performs one or more switching operations while the test data output of voltage monitor160is stored in data table168. In one embodiment, based on the test data output of voltage monitor160during the one or more switching operations, current controller150determines bypass current i2characteristics that will produce a VDLICat or above VR, for all of the one or more switching operations and established the bypass current setpoint based on those bypass current i2characteristics. In one embodiment, the bypass current setpoint is stored by current management system105in a memory165. In one embodiment, after calibrating current controller150with the bypass current setpoint, current controller150shifts to the normal operation phase. In the normal operation phase, current controller150ramps bypass current i2from steady state to the bypass current setpoint as described above, in response to the a priori information. After the switching operation is completed, current controller150ramps bypass current i2from ramping the bypass current from expected switching value Iswitchback to a steady state value (as shown inFIG. 3Gat373). Because while in normal operation phase, current management system105controls bypass current i2based on the bypass current setpoint rather than dynamic measurements of VDLIC, feedback from voltage monitor160is not required.

In other embodiments, the voltage drop in VDLICacross digital logic integrated circuit110will vary, increasing with the complexity of the synchronous logic path required for digital logic integrated circuit10to execute one or more logic functions. A more complex synchronous logic path within digital logic integrated circuit110generally requires more bypass current setpoints, some of which may draw a relatively larger current i3than a less complex synchronous logic path. Accordingly, in one embodiment, current controller150is calibrated to establish an associated bypass current setpoint for each of the one or more logic functions performed by digital logic integrated circuit110.

In one embodiment, when in the test phase, changes in VDLICare observed by voltage monitor160and stored as test data in data table160while digital logic integrated circuit110executes the one or more logic functions. For each of the one or more logic functions, current controller150determines bypass current i2characteristics such that VDLICis maintained at or above VR, and sets an associated bypass current setpoint based on those bypass current i2characteristics. In one embodiment, the associated bypass current setpoint specifies one or more characteristics of bypass current i2including one or more of the peak current for bypass current i2, the ramp rate for bringing bypass current i2to the peak current level, and the transition time for bringing bypass current i2to the peak current level. In one embodiment, to obtain optimum operation of current management system105, current controller150determines associated bypass current setpoint that allows VDLICto drop to exactly VRfor each of the one or more logic functions, as described with respect toFIGS. 3G to 3Jabove.

In one embodiment current management system105stores the bypass current setpoint values acquired during test phase testing in data table168. Data table168is configured to correlate an associated bypass current setpoint with each of the one or more logic functions executed by digital logic integrated circuit110. In one embodiment, bypass current setpoints for the one or more logic functions executed by digital logic integrated circuit110are acquired by performing one or more test methods for acquiring test data as described in the '090 Application herein incorporated by reference.

In one embodiment, after calibration is complete, current management system105shifts from the test phase to the normal operation phase. In the normal operation phase, current controller150ramps bypass current i2based on a bypass current setpoint as described above, in response to a prior information about the impending current needs of digital logic integrated circuit110. In one embodiment, current controller150receives a priori information that identifies which of the one or more logic functions will be executed by digital logic integrated circuit110, and based on the a priori information, selects an associated bypass current setpoint based on the one or more bypass current setpoints in data table168. The a priori information can be obtained in a number of ways as described in the '949 Application herein incorporated by reference. In one embodiment, digital logic integrated circuit110communicates to current controller150the a priori information that identifies which of the one or more logic functions will be executed by digital logic integrated circuit110. After the switching operation is completed, current controller150ramps bypass current i2from ramping the bypass current from expected switching value Iswitchback to a steady state value (as shown inFIG. 3Gat373).

One such means for obtaining a priori information identifying which of the one or more logic functions will be executed by digital logic integrated circuit110is illustrated byFIG. 2.FIG. 2illustrates a system200for communicating a priori switching information between a current controller250and a digital logic integrated circuit210of one embodiment of the present invention. In one embodiment, current controller250comprise an increasing ramp generator260adapted to output a control signal to a controllable current sink220to ramp bypass current i2from a steady state value (e.g. zero amps) to a bypass current setpoint. In one embodiment, current controller250also comprises a decreasing ramp generator265adapted to output a control signal to the controllable current sink220that ramps bypass current i2from the bypass current setpoint back to the steady state value (e.g. zero amps).

In one embodiment, the digital logic integrated circuit210comprises an input buffer stage212, a logic function stage214, and a power driver stage216as described in the '949 Application herein incorporated by reference. During operation of digital logic integrated circuit210, data from digital logic input signals are stored within input buffer stage212. The data is then transferred to logic function stage214, where one or more operations (e.g., NAND, NOR) are performed based on the function of digital logic integrated circuit210. When logic function stage214is ready to output data, the data is transferred to the power driver stage216for output. The contribution of each of input buffer stage212, logic function stage214, and power driver stage216to the total current draw i3of digital logic integrated circuit210is illustrated byFIG. 3Aat310by i3in, i3logic, and i3out, respectively. In one embodiment, upon receiving digital logic input data at time t1, input buffer stage212enables increasing ramp generator260to ramp bypass current i2to the bypass current setpoint via signal223. Logic function stage214then disables (via signal221) the output of increasing ramp generator260at time t2, which is when i3steps to Iswitchto support the switching operations of digital logic integrated circuit210. Signal222from power driver stage216then enables decreasing ramp generator260at time t3, which is when i3steps from Iswitchback to its steady state value. At time t3, decreasing ramp generator260begins to ramp bypass current i2back to steady state starting from the bypass current setpoint. In one embodiment, a timer266is also enabled at time t3by power driver stage216. At time t4, an output signal from timer266disables the output of decreasing ramp generator265. In one embodiment, the sum of the outputs from increasing ramp generator260and decreasing ramp generator comprise the control signal provided to controllable current sink220from current controller250.

In one embodiment, current controller250is configured to ramp bypass current i2to (and from) a selected peak current level based on a single bypass current setpoint stored in memory265. In an alternate embodiment, current controller250is configured to ramp bypass current i2to, and from, one of a plurality of bypass current setpoints stored in data table268, based on the logic operation to be performed by logic function stage214. In one embodiment, logic function stage214(via signal221) identifies to current controller250the logic operation to be performed by logic function stage214and current controller250correlates the logic operation with an associated bypass current setpoint stored in memory265. In one embodiment, logic function stage214identifies to current controller250the pending operation and current controller250determines the associated bypass current setpoint by correlating the identified pending operation with test data stored in data table268. The output of increasing ramp generator260is then disabled once bypass current i2reaches the associated bypass current setpoint. In one embodiment, data for data table268, correlating the one or more operations performed by digital logic integrated circuit210with one or more corresponding bypass current setpoints, is acquired as described in the '090 Application herein incorporated by reference. In one embodiment, one or both of increasing ramp generator260and decreasing ramp generator265vary their ramp rate based on the value of the bypass current setpoint. For example, in one embodiment, increasing ramp generator260ramps bypass current i2at a relatively faster rate for larger bypass current setpoints than for smaller bypass current setpoints, to ensure that the bypass current i2reaches the selected peak current level when digital logic integrated circuit210's current demand i3increases to switching value Iswitch(i.e., at time t2as shown inFIG. 3Cat332). Note that for clarity of explanation inFIGS. 3A to 3J, all increasing and decreasing current ramps for bypass current i2are shown linearly increasing or linearly decreasing, with abrupt turn-on and turn-off at the beginning and end of the current ramps. (A non-linear representation of one potential resulting current i1is shown generally at383). Also, shown for clarity, i3is shown as a simplified pulse inFIG. 3A. However, one skilled in the art upon reading this specification would appreciate that i3will typically not be an ideal current pulse, and bypass current i2will typically be realized by gradual and generally non-linear increasing and decreasing current ramps, such that the sum of i2+i3yields a low di1/dt. Gradual and generally non-linear adjustments of bypass current i2reduce voltage change in VDLICduring digital logic operation.

FIG. 4is a flow chart illustrating a method of current management for a digital logic circuit. In one embodiment,FIG. 4illustrates a method for operation of a current management in a test phase as described above. In one embodiment, the method may be used for calibrating a current management system for a digital logic circuit as described in the '949 Application herein incorporated by reference. The method begins at410and comprises drawing power to drive a digital logic integrated circuit. The method further comprises determining a priori information about an impending current need of the digital logic integrated circuit at420. In one embodiment, the a priori information is received from a signal from the digital logic integrated circuit. In one embodiment, the a priori information includes information about which of one or more logic functions will be executed by the digital logic integrated circuit.

In one embodiment, at430, the method also comprises observing a voltage, VDLIC, across the digital logic integrated circuit. In one embodiment, VDLIis compared to a reference voltage VR. In one embodiment, the reference voltage VRrepresents Vmin required, a minimum VDLICvoltage rating for the digital logic integrated circuit, below which operation of the digital logic integrated circuit cannot be guaranteed. For many applications, a typical value for VRis 4.5 VDC.

The method continues at440with controlling a bypass current in parallel with the digital logic integrated circuit based on the a priori information, wherein the bypass current is controlled to reduce discontinuities in the current supplied by a power supply. The method adjusts the bypass current at450to prevent the voltage of the digital logic integrated circuit from dropping below the reference voltage. In one embodiment, adjusting the bypass current includes controlling one or more of the peak current for bypass current i2, the ramp rate for bringing bypass current i2to the peak current level, and the transition time for bringing bypass current i2to the peak current level.

As discussed above, the voltage drop in VDLICacross the digital logic integrated circuit is a function of both the current i3drawn by the digital logic integrated circuit when performing logic switching operations and the bypass current. By adjusting the bypass current to maintain VDLICgreater than or equal to Vmin required, fluctuations in VDLICdue to parasitic inductances are reduced without allowing VDLICto drop to a level that could cause the digital logic integrated circuit to malfunction. In one embodiment, the method optionally comprises executing one or more logic functions within the digital logic integrated circuit and determining a bypass current setpoint based on the difference between the voltage of the digital logic integrated circuit and the reference voltage. In one embodiment, the bypass current setpoint is stored in a memory. In one embodiment, the bypass current setpoint is determined as described in the '090 Application herein incorporated by reference.

In one embodiment, the degree of voltage drop in VDLICvaries, increasing with the complexity of the synchronous logic path required for the digital logic integrated circuit to execute one or more logic functions, and the resulting i3current required to perform associated logic switching operations. Accordingly, in one embodiment, the method optionally comprises executing one or more logic functions with the digital logic integrated circuit and determining an associated bypass current setpoint for each of the one or more logic functions. In one embodiment, each bypass current setpoint is based on the difference between the voltage of the digital logic integrated circuit and a reference voltage while executing the associated logic function of the one or more logic functions. The associated bypass current setpoints and logic function can then be correlated within a data table for later access. In this way, the current controller essentially learns a bypass current setpoint specifying characteristics including one or more of a peak current, a ramp rate, and a transition time for each of the logic functions. In one embodiment, the data table is stored in memory. In one embodiment, the associated bypass current setpoints are determined as described in the '090 Application herein incorporated by reference.

In one embodiment,FIG. 5illustrates a method for operation of a current management in a normal operation phase as described above. In one embodiment, when one or more bypass current setpoints are established using the method ofFIG. 4, current management for the digital logic circuit is achieved by the method illustrated inFIG. 5. The method starts at510with drawing power to drive a digital logic integrated circuit. The method continues at520with determining a priori information about an impending current need of the digital logic integrated circuit. In one embodiment, the a priori information is received from a signal from the digital logic integrated circuit. In one embodiment, the a priori information includes information about which of one or more logic functions will be executed by the digital logic integrated circuit. The method continues at530with controlling a bypass current in parallel with the digital logic integrated circuit based on the a priori information and at540with adjusting the bypass current to prevent the voltage of the digital logic integrated circuit from dropping below Vmin required. In one embodiment, the bypass current is controlled to reduce discontinuities in the current supplied by a power supply. In one embodiment, controlling a bypass current further comprises ramping the bypass current based on a bypass current setpoint established during calibration, and when the impending current need of the digital logic integrated circuit is completed, ramping the bypass current from Iswitchback to a steady state value. In one embodiment, the bypass current setpoint is established by referring to a data table to look up the logic function identified by the a priori information, and correlate the logic function with an associated bypass current setpoint. In one embodiment, the associated bypass current setpoint specifies one or more characteristics of the bypass current including one or more of the peak current for bypass current, the ramp rate for bringing bypass current to the peak current level, and the transition time for bringing bypass current to the peak current level.

Several means are available to implement the controllable current sink, current controller, and digital logic integrated circuit discussed above. These means include, but are not limited to, digital computer systems, programmable controllers, or field programmable gate arrays. Therefore other embodiments of the present invention are program instructions resident on computer readable media which when implemented by such processors, enable the processors to implement embodiments of the present invention. Computer readable media include any form of computer memory, including but not limited to punch cards, magnetic disk or tape, any optical data storage system, flash read only memory (ROM), non-volatile ROM, programmable ROM (PROM), erasable-programmable ROM (E-PROM), random access memory (RAM), or any other form of permanent, semi-permanent, or temporary memory storage system or device. Program instructions include, but are not limited to computer-executable instructions executed by computer system processors and hardware description languages such as Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL).