Example low-delay complementary metal-oxide semiconductor (CMOS) to emitter-coupled logic (ECL) converters, methods and apparatus are disclosed. A disclosed example apparatus includes a reference level generator circuit to generate first and second reference signals and a bias signal based on a CMOS supply voltage, a source follower circuit to convert a CMOS input signal to a single-ended ECL signal based on the first and second reference signals, and an ECL buffer circuit to convert the single-ended ECL signal to a differential ECL output signal based on the bias signal and an ECL supply voltage.

FIELD OF THE DISCLOSURE

This disclosure relates generally to signal converters, and, more particularly, to low-delay complementary metal-oxide semiconductor (CMOS) to emitter-coupled logic (ECL) converters, methods and apparatus.

BACKGROUND

In some applications and/or circuits (e.g., requiring high-speed logic) it is necessary and/or desirable to convert a rail-to-rail signal, such as that generated by complementary metal-oxide semiconductor (CMOS) logic, to a differential signal compatible with emitter-coupled logic (ECL) logic. An example ECL differential signal uses a −1.75 volt (V) signal with respect to ground on a positive signal component and a −0.9 V signal with respect to ground on a negative signal component to represent a logic value of “0”; and the −0.9 V signal on the positive signal component and the −1.75 V signal on the negative signal component to represent a logic value of “1.”

DETAILED DESCRIPTION

Example low-delay complementary metal-oxide semiconductor (CMOS) to emitter-coupled logic (ECL) converters, methods and apparatus are disclosed. A disclosed example apparatus includes a reference level generator circuit to generate first and second reference signals and a bias signal based on a CMOS supply voltage, a source follower circuit to convert a CMOS input signal to a single-ended ECL signal based on the first and second reference signals, and an ECL buffer circuit to convert the single-ended ECL signal to a differential ECL output signal based on the bias signal and an ECL supply voltage.

A disclosed example converter to convert a CMOS input signal to a differential ECL output signal includes a reference level generator circuit, a source follower and an ECL buffer. In one example, the reference level generator circuit includes first and second transistors connected in series between a first CMOS supply voltage and a second CMOS supply voltage. In such an arrangement, the gate input signals to the first and second transistors are used as a bias signal having a first value substantially mid-way between the first and second CMOS supply voltages. The example also includes first and second components connected in series between the first and second transistors. The bias signal is created at a first node where the first and second components are connected. The first component creates a first reference signal having a second value that is a first voltage above the bias signal and the second component creates a second reference signal having a third value that is a second voltage below the bias signal. In some examples, the source follower circuit includes third and fourth transistors connected in series between the first and second reference signals in a source follower topology to create a single-ended ECL signal at a second node where the third and fourth transistors are connected, the third and fourth transistors using as their gate input signals the CMOS input signal. The ECL buffer circuit thereby generates a differential ECL output signal based on the single-ended ECL signal and the bias signal.

A disclosed example method includes generating a bias signal and first and second reference signals based on a CMOS supply voltage, converting a CMOS input signal to a single-ended ECL signal based on the first and second reference signals, and buffering the single-ended ECL compatible signal to form a differential ECL signal based on the bias signal and an ECL supply voltage.

FIG. 1is a schematic diagram of an example conventional CMOS to ECL converter100. The example CMOS to ECL converter100ofFIG. 1converts a CMOS input signal105to a differential ECL output signal110via a CMOS inverter115, and contains a delay stage120to equalize the delay in the two paths to a current mode logic (CML) buffer125. The CML buffer125ofFIG. 1uses MOS input transistors since its inputs are CMOS levels and, thus, not compatible with a bipolar transistor based ECL buffer.

FIG. 2is a schematic diagram of an example low-delay CMOS to ECL converter200. The example CMOS to ECL converter200ofFIG. 2converts a CMOS input signal205to a differential ECL output signal210. By eliminating the example CMOS inverter115and the example delay stage120ofFIG. 1and replacing the MOS based CML buffer125with a bipolar based ECL buffer260, the example CMOS to ECL converter200ofFIG. 2substantially reduces the delay introduced by the conversion process. For instance, the example CMOS to ECL converter circuits disclosed herein only introduce an average delay of 40 pico seconds (ps) across temperature and semiconductor process variations, as compared to a typical delay of 400 ps introduced by the conventional CMOS to ECL converters (e.g., the example CMOS to ECL converter100ofFIG. 1).

The example CMOS input signal205ofFIG. 2is a rail-to-rail signal taking on the value of a first CMOS supply voltage (CMOS VDD)215or a second CMOS supply voltage (CMOS VSS)220(e.g., a ground signal). The CMOS input signal205may also take on values falling between the CMOS supply voltage215and the CMOS ground signal220when transitioning between values, for example, as occurs on a rising and/or falling edge of the CMOS input signal205. The example differential ECL output signal210ofFIG. 2comprises a positive signal component212and a negative signal component213, the voltage differential thus between (e.g., the value of the positive signal component212minus the value of the negative signal component213) represents digital logic bits.

To provide voltage supplies and/or references, the example CMOS to ECL converter200ofFIG. 2includes the example CMOS supply voltage215, the example CMOS ground220, a first ECL supply voltage (ECC VDD)225and a second ECL supply signal (ECC VSS)230. An example set of supply voltages comprises a CMOS VDD215of 3 V, a CMOS VSS220of 0 V, an ECL VDD225of 3 V and an ECL VSS230of 0 V. As described below in connection withFIG. 3, the ECL supply voltages225and230ofFIG. 2also determine, at least partially, the signal levels that may occur on the positive and negative signal components212and213. The example CMOS supply signals215and220and the example ECL supply signals225and230can be implemented by any number and/or type(s) of past, present and/or future voltage supply and/or ground signal source(s), device(s) and/or circuit(s).

To generate a bias signal235and a pair of reference signals240and241, the example CMOS to ECL converter200ofFIG. 2includes a reference level generator245. The example reference level generator245ofFIG. 2receives the CMOS supply signal215and the CMOS ground signal220, and generates the bias signal235to be substantially mid-way between the CMOS supply signal215and the CMOS ground signal220. The example reference level generator245generates the reference signal240such that its voltage is substantially a diode drop voltage (e.g., 0.7 volts (V)) above the bias signal235, and the reference signal241such that its voltage is substantially a diode drop voltage below the bias signal235. For example, for a CMOS supply voltage215of 3V, the bias signal235would have a voltage of approximately 1.5V, the reference signal240would have approximately a voltage of 2.2V, and the reference signal241would have a voltage of approximately 0.8V. An example manner of implementing the example reference level generator245ofFIG. 2is described below in connection withFIG. 3.

To convert the CMOS input signal205to a single-ended ECL signal250, the example CMOS to ECL converter200ofFIG. 2includes a source follower255. The example source follower255ofFIG. 2causes the single-ended ECL signal250to follow the CMOS input signal205, but be bounded and/or limited by the example reference signals240and241. That is the singled-ended ECL signal250represents an ECL compatible version of the CMOS input signal250with respect to the bias signal235. For example, for a CMOS logical “1” and CMOS supply voltage215of 3V, the output250of the source follower255would be 2.2 V. Conversely, the voltage of the output250for a logical “0” would be 0.9 V. An example manner of implementing the example source follower255ofFIG. 2is described below in connection withFIG. 3.

To buffer the single-ended ECL signal250, the example CMOS to ECL converter200ofFIG. 2includes an ECL buffer260. The example ECL buffer260ofFIG. 2transforms the single-ended ECL signal250into the differential ECL output signal210based on the bias signal235and the ECL supply voltage225. The example differential ECL output signal210ofFIG. 2follows the single-ended ECL signal250, but the desired range for the values of the positive and negative signals212and213are determined by the ECL buffer260based on the ECL supply voltage225and a set of resistors (e.g., the example resistors R18, R19and R20ofFIG. 3). An example manner of implementing the example ECL buffer260ofFIG. 2is described below in connection withFIG. 3.

FIG. 3illustrates an example manner of implementing the example reference level generator245, the example source follower255, the example ECL buffer260and/or, more generally, the example CMOS to ECL converter200ofFIG. 2. To generate the example bias signal235, which is substantially mid-way between the CMOS supply215and the CMOS ground220, the example reference level generator245ofFIG. 3includes junction field-effect transistors (JFETs) MN1and MP2. The CMOS supply215is connected to the drain of MP2. To generate the reference signals240and241, the example reference level generator245ofFIG. 3includes bipolar junction transistors (BJTs) Q1and Q2. The example transistors MP2, Q2, Q1and MN1are connected in series in a voltage divider topology to generate the bias signal235, as illustrated inFIG. 3. The example bias signal235ofFIG. 3is generated at the point305where the collector of example transistor Q1is electrically coupled to the emitter of example transistor Q2, and this node305is connected to the gate input of both of the transistors MP2and MN1. The example transistors Q1and Q2ofFIG. 3have their bases coupled to their collectors and, thus, are each configured in a diode topology. Accordingly, the example reference signal240is substantially a diode drop voltage (e.g., 0.7V) above the bias signal235, and the example reference signal241is substantially a diode drop voltage below the bias signal235. Any number and/or type(s) of components could be used instead of, or in addition to, the example transistors Q1and Q2to create the example diode drop voltages ofFIG. 3. For example, either or both of the transistors Q1and Q2could be replaced by diodes. The example bias signal235is substantially at the midpoint of the CMOS supplies215and220. However, the bias signal235may alternatively be adjusted to be somewhat higher or lower as benefits the operation of the example converter200in a particular application, to account for process variability, temperature variation and/or absolute supply voltage levels.

To form the single-ended ECL signal250, the example source follower255ofFIG. 3includes MOS field-effect transistors (MOSFETs) MN0and MP0. The example transistors MN0and MP0ofFIG. 3are connected in series between the reference signals240and241in a source follower topology. The gates of transistors MN0and MP0are coupled together at a node310to form an input for the CMOS input signal205. The example single-ended ECL signal250ofFIG. 3is generated at a node315where the source of example transistor MN0is electrically coupled to the source of example transistor MP0. When the CMOS input signal205has a logical high value (e.g., 3V), the example transistor MN0ofFIG. 3is turned on and the example transistor MP0ofFIG. 3is turned off such that the single-ended ECL signal250takes on the value of the reference signal240(e.g., 2.2V). Likewise, when the CMOS input signal205has a logical low value (e.g., 0V), the transistor MN0is turned off and the transistor MP0is turned on such that the single-ended ECL signal250takes on the value of the reference signal241(e.g., 0.8V). In this fashion, the example source follower255ofFIG. 3forms a single-ended ECL signal250that follows the CMOS input signal205, is centered around the bias signal235, and is bounded and/or limited by the reference signals240and241.

To buffer the single-ended ECL signal250, the example ECL buffer260ofFIG. 2includes BJT transistors Q3and Q4, and resistors R18, R19and R20. The example transistors Q3and Q4ofFIG. 3are connected in a differential switch topology such that one, but not both, of the example transistors Q3and Q4is turned on at a given time. For example, when the single-ended ECL signal250is sufficiently greater than the bias signal235(e.g., by 200 millivolts (mV)), the transistor Q3is turned on and the transistor Q4is turned off.

The example resistors R18, R19and R20ofFIG. 3determine the allowable range of voltages for the positive and negative ECL signals212and213. The example resistors R18, R19and R20are arranged in a voltage divider topology. In the illustrated example ofFIG. 3, the resistance of the resistor R20is selected to determine the largest voltage that the signals212and213can have. The example resistors R18and R19ofFIG. 3are selected to have the same resistance, and the resistance is selected to determine the difference between the largest voltage and the smallest voltage that the signals212and213can have. For example, when the example transistor Q3ofFIG. 3is turned on, current flows through the left branch of the ECL buffer260and the voltage drop across the resistor R20determines the voltage of the positive signal212and the voltage drop across the series combination of resistors R20and R18determines the voltage of the negative signal213. Likewise, when the example transistor Q4is turned on, current flows through the right branch of the ECL buffer260and the voltage drop across the resistor R20determines the voltage of the negative signal213and the voltage drop across the series combination of resistors R20and R19determines the voltage of the positive signal212.

To control the amount of current that flows through the ECL buffer260, the example circuit ofFIG. 3includes any type of current source CS. The example current source CS and the resistors R18, R19and R20determine the voltage values taken by the positive and negative signals212and213. For example, if the current source CS provides 200 micro Amps (uA) of current, the resistance of R20is 2.5 thousand ohms (kΩ), and the resistances of R18and R19are 2.7 kΩ, then the largest voltage for the positive and negative signals212and213is 250 mV below the ECL supply voltage225, and the smallest voltage for the signals212and213is 520 mV below the ECL supply voltage225.

FIG. 4is a schematic illustration of an example circuit400that implements and/or includes the example reference signal generator245, the example source follower255, the example ECL buffer260and/or, more generally, the example CMOS to ECL converter200ofFIGS. 2and/or3. Portions of the example circuit400ofFIG. 4are identical to those discussed above in connection withFIG. 3and, thus, the descriptions of those portions are not repeated here. Instead, identical elements are illustrated with identical reference numerals inFIGS. 3 and 4, and the interested reader is referred back to the descriptions presented above in connection withFIG. 3for a complete description of those like-numbered elements.

To enable and/or disable the example circuit400ofFIG. 4, the example circuit400includes an enable input signal405and transistors MP1, MN2and MN3. When the example enable input signal405is a logical “1”, the transistors MP1, MN2and MN3are in an “on” state that enables the transistors MP2, MN1, Q1and Q2to behave as described above in connection withFIG. 3. However, when the enable signal405is a logical “0”, the transistors MP2, MN1, Q1and Q2are biased into an “off” state and, thus, the operation of the example circuit400is effectively disabled.

To control a bias of the example ECL buffer260, the example circuit400ofFIG. 4includes a bias input signal410. The example bias input signal410ofFIG. 4controls the amount of current generated by the example current source CS, and the voltage drops that occur across the resistors R18, R19and R20. Thus, the voltage values taken by the positive and negative signal components212and213may be adjusted by controlling the value of the bias input signal410. For example, a bias input signal410equal to the Vbe of Q17plus 100 mV, yields voltage values of (ECLVDD—0.25 V) and (ECLVDD—0.52 V) for the signal components212and213. A bias input signal equal to the Vbe of Q17plus 50 mV, yields voltage values of (ECLVDD—0.125 V) and (ECLVDD—0.26 V) for the signal components212and213.

The example current source CS ofFIG. 4is configured in a simple bipolar current mirror topology and operates as follows. A bias voltage is present on the base of Q17, such that, for example, the current into the collector of Q17is 100 uA. This current passes through the diode connected p-channel MOSFET (PMOS) MP4forming a simple MOS current mirror with MP3. The current out of the drain of MP3has the same magnitude as that in the drain of MP4. The current from the drain of MP3is fed into a diode connected NPN transistor, which forms a simple current mirror with another NPN, which provides the current of 100 uA into the ECL buffer260. Alternatively, the current of 100 uA into the ECL buffer260may be generated in any other way, depending on the specific needs of the application. For example, the current could be provided by a resistor connected to ECLVSS.

While example manners of implementing a low-delay CMOS to ECL converter are illustrated inFIGS. 2,3and4, a reference signal generator, a source follower and/or an ECL buffer may be implemented using any number and/or type(s) of alternative and/or additional logic, devices, components, circuits, modules, interfaces, etc. Further, the logic, devices, components, circuits, modules, elements, interfaces, etc. illustrated inFIGS. 2,3and/or4may be combined, divided, re-arranged, omitted, eliminated and/or implemented in any other way. For example reference signal generator245, the example source follower255, the example ECL buffer260may be implemented together within a single integrated circuit (IC) and/or with multiple ICs. Moreover, a CMOS to ECL converter may include additional logic, devices, components, circuits, interfaces and/or modules instead of, or in addition to those illustrated inFIGS. 2,3and/or4.