Semiconductor device protection circuits for protecting a semiconductor device during processing thereof, and associated methods, devices, and systems

Memory devices are disclosed. A memory device may include a source (SRC) plate configured to couple to a number of memory cells. The memory device may also include a resistor coupled between the source plate and a node. Further, the memory device may include at least one transistor coupled between the source plate and the ground voltage, wherein a gate of the at least one transistor is coupled to the node. The transistor may be configured to couple the SRC plate to the ground voltage during a processing stage. The transistor may further be configured to isolate the SRC plate from the ground voltage during an operation stage. Methods and electronic systems are also disclosed.

TECHNICAL FIELD

Embodiments of the disclosure relate generally to protection circuits. More specifically, various embodiments relate to protection circuits configured to protect a semiconductor device during processing thereof, and to related methods, devices, and systems.

BACKGROUND

Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic systems. There are many different types of memory including, for example, random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), resistive random access memory (RRAM), double data rate memory (DDR), low power double data rate memory (LPDDR), phase change memory (PCM), and Flash memory. Memory devices typically include many memory cells that are capable of holding a charge that is representative of a bit of data. Typically, these memory cells are arranged in a memory array. Data may be written to or retrieved from a memory cell by selectively activating the memory cell via an associated word line driver.

As will be appreciated by a person having ordinary skill in the art, during processing of a semiconductor device (e.g., a memory device, such as a 2D or 3D NAND device), a source (SRC) plate (e.g., formed via one or more conductive materials, such as polysilicon, silicide, or a combination thereof) of the semiconductor device may be biased to high voltages (e.g., during an etching process). More specifically, for example, during one or more “offending” processing steps (e.g., etching of a deep contact to or near the SRC plate), the SRC plate may be undesirably biased to high voltages (e.g., around 25-35 volts or more). As will also be appreciated, conventional controlling circuitry (e.g., SRC controlling circuitry, such as high voltage discharge circuitry) may not exhibit a sufficiently low breakdown voltage to prevent the SRC plate from reaching such high voltages during processing. The presence of a high voltage on the SRC plate may cause high electric fields between nearby features (e.g., grounded features created from the same polysilicon level as the SRC plate). In other words, because through-array contacts may be effectively grounded during an etching process, and the SRC plate may float to a high voltage, the lateral dielectric between the SRC plate and a landing pad (i.e., for a through-array contact) may be overly stressed. This stress may result in either diminished probe yield or reliability failures due to breakdown of the weakened dielectric between the SRC plate and the nearby polysilicon features (e.g., during erase operations when the SRC plate is biased to a high voltage).

DETAILED DESCRIPTION

Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programing different states of a memory device. For example, binary devices have two states, often denoted by a logic “1” or a logic “0.” In other systems, more than two states may be stored. To access the stored information, the electronic device may read, or sense, the stored information in the memory device. To store information, the electronic device may write, or program, the state in the memory device.

Various types of memory devices exist, including random access memory (RAM), read only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, and others. Memory devices may be volatile or non-volatile. A non-volatile memory device (e.g., flash memory) can store data for extended periods of time even in the absence of an external power source. A volatile memory device (e.g., DRAM) may lose its stored state over time unless it is periodically refreshed by an external power source. A binary memory device may, for example, include a charged or discharged capacitor.

Memory provides data storage for electronic systems. Flash memory is one of various memory types and has numerous uses in modern computers and devices. A typical flash memory device may include a memory array that has a large number of charge storage devices (e.g., memory cells, e.g., non-volatile memory cells) arranged in rows and columns. In a NAND architecture type of flash memory, storage devices arranged in a column are coupled in series, and a first storage device of the column is coupled to a bit line. In “two-dimensional NAND” (which may also be referred to herein as “2D NAND”), the storage devices are arranged in row and column fashion along a horizontal surface. In “three-dimensional NAND” (which may also be referred to herein as “3D NAND”), a type of vertical memory, not only are the storage devices arranged in row and column fashion in a horizontal array, but tiers of the horizontal arrays are stacked over one another to provide a “three-dimensional array” of the storage devices.

In 3D NAND, access lines, which may also be known as “word lines,” may each operably connect the storage devices corresponding to a respective tier of the three-dimensional array. In 2D NAND, access lines may operably connect storage devices corresponding to a row or column of the two-dimensional array. In either 2D or 3D NAND, string drivers may be in operational communication with the access lines. That is, the string drivers may drive the access line (e.g., word line) voltages to write to or read from the charge storage devices of the arrays. Each charge storage device may be electrically programmed by charging a floating gate of the device, and the charging is controlled, at least in part, by operation of the string driver. As another example, a charge storage device may be programmed via a trapping layer (e.g., one or more nitride layers).

As will be appreciated by a person having ordinary skill in the art, during processing of a semiconductor device (e.g., a memory device, such as a 2D or 3D NAND device), a source (SRC) plate (e.g., formed via one or more conductive materials, such as polysilicon, silicide, or a combination thereof) of the semiconductor device may be biased to high voltages (e.g., during an etching process). More specifically, for example, during one or more “offending” processing steps (e.g., etching of a deep contact to or near the SRC plate), the SRC plate may be undesirably biased to high voltages (e.g., around 25-35 volts or more). As will also be appreciated, conventional controlling circuitry (e.g., SRC controlling circuitry, such as high voltage discharge circuitry) may not exhibit a sufficiently low breakdown voltage to prevent the SRC plate from reaching such high voltages during processing. The presence of a high voltage on the SRC plate may cause high electric fields between nearby features (e.g., grounded features created from the same polysilicon level as the SRC plate). In other words, because through-array contacts may be effectively grounded during an etching process, and the SRC plate may float to a high voltage, the lateral dielectric between the SRC plate and a landing pad (i.e., for a through-array contact) may be overly stressed. This stress may result in either diminished probe yield or reliability failures due to breakdown of the weakened dielectric between the SRC plate and the nearby polysilicon features (e.g., during erase operations when the SRC plate is biased to a high voltage).

As described more fully below, various embodiments described herein may be related to protecting various portions of a semiconductor device during processing thereof, and not interfering with operation of the semiconductor device (i.e., after completion of semiconductor processing). More specifically, various embodiments relate to a protection circuit (i.e., of a semiconductor device) configured to protect (e.g., during processing of the semiconductor device) a dielectric positioned proximate (e.g., between) an SRC plate and neighboring landing pads, with minimal die-size impact. Further, according to various embodiments, the protection circuit may be configured to reduce parasitic leakage sufficiently (i.e., during die operation) such that the protection circuit does not substantially interfere with operation of the semiconductor device. As will be appreciated by a person having ordinary skill in the art, various embodiments disclosed herein may decrease yield fallout and/or reliability issues compared to conventional devices, systems, and methods.

More specifically, as described more fully below, various embodiments of the present disclosure include a protection device (also referred to herein as a “protection circuit”) configured to couple a source (SRC) plate to a ground voltage during a processing stage, and isolate the SRC plate from the ground voltage during an operation stage. Yet more specifically, according to various embodiments, a device (e.g., a semiconductor memory device) may include a SRC plate configured to couple to a number of memory cells. The device may also include a protection circuit. The protection circuit may include at least one transistor coupled between the SRC plate and a ground voltage, wherein a gate of the at least one transistor is coupled to a node. The protection circuit may further include a resistive element (e.g., including one or more resistors) coupled between the SRC plate and the node. Further, the at least one transistor may be configured to couple the SRC plate to the ground voltage during a processing stage (e.g., during at least one etching operation, at least one chemical mechanical planarization (CMP) operation, at least one implantation operation, at least one ashing operation, another processing operation, or any combination thereof). Also, the at least one transistor may be configured to isolate the SRC plate from the ground voltage during an operation stage (i.e., during operation of the semiconductor device).

Although various embodiments are described herein with reference to memory devices, the present disclosure is not so limited, and the embodiments may be generally applicable to microelectronic devices that may or may not include semiconductor devices and/or memory devices. Embodiments of the present disclosure will now be explained with reference to the accompanying drawings.

FIG. 1includes a block diagram of an example memory device100, according to various embodiments of the present disclosure. Memory device100, which is and may be referred to herein as a memory device, may include, for example, a DRAM (dynamic random access memory), a SRAM (static random access memory), a SDRAM (synchronous dynamic random access memory), a DDR SDRAM (double data rate DRAM, such as a DDR4 SDRAM and the like), or a SGRAM (synchronous graphics random access memory). Memory device100, which may be integrated on a semiconductor chip, may include a memory cell array102.

For example, memory device100, and more specifically, for example, memory cell array102, may include one or more protections circuits, as described herein. More specifically, for example, the memory device100may include a SRC plate coupled to a number of memory cells of memory cell array. Further, the SRC plate may be coupled to one or more protection circuits.

In the embodiment ofFIG. 1, memory cell array102is shown as including eight memory banks BANK0-7. More or fewer banks may be included in memory cell array102of other embodiments. Each memory bank includes a number of access lines (word lines WL), a number of data lines (bit lines BL) and/BL, and a number of memory cells MC arranged at intersections of the number of word lines WL and the number of bit lines BL and/BL. The selection of a word line WL may be performed by a row decoder104and the selection of the bit lines BL and/BL may be performed by a column decoder106. In the embodiment ofFIG. 1, row decoder104may include a respective row decoder for each memory bank BANK0-7, and column decoder106may include a respective column decoder for each memory bank BANK0-7.

Bit lines BL and/BL are coupled to a respective sense amplifier SAMP. Read data from bit line BL or/BL may be amplified by sense amplifier SAMP, and transferred to read/write amplifiers107over complementary local data lines (LIOT/B), transfer gate (TG), and complementary main data lines (MIOT/B). Conversely, write data outputted from read/write amplifiers107may be transferred to sense amplifier SAMP over complementary main data lines MIOT/B, transfer gate TG, and complementary local data lines LIOT/B, and written in memory cell MC coupled to bit line BL or/BL.

Memory device100may be generally configured to be receive various inputs (e.g., from an external controller) via various terminals, such as address terminals110, command terminals112, clock terminals114, data terminals116, and data mask terminals118. Memory device100may include additional terminals such as power supply terminals120and122.

During a contemplated operation, one or more command signals COM, received via command terminals112, may be conveyed to a command decoder150via a command input circuit152. Command decoder150may include a circuit configured to generate various internal commands via decoding one or more command signals COM. Examples of the internal commands include an active command ACT and a read/write signal R/W.

Further, one or more address signals ADD, received via address terminals110, may be conveyed to an address decoder130via an address input circuit132. Address decoder130may be configured to supply a row address XADD to row decoder104and a column address YADD to column decoder106. Although command input circuit152and address input circuit132are illustrated as separate circuits, in some embodiments, address signals and command signals may be received via a common circuit.

Active command ACT may include a pulse signal that is activated in response to a command signal COM indicating row access (e.g., an active command). In response to active signal ACT, row decoder104of a specified bank address may be activated. As a result, the word line WL specified by row address XADD may be selected and activated.

Read/write signal R/W may include a pulse signal that is activated in response to a command signal COM indicating column access (e.g., a read command or a write command). In response to read/write signal R/W, column decoder106may be activated, and the bit line BL specified by column address YADD may be selected.

In response to active command ACT, a read signal, a row address XADD, and a column address YADD, data may be read from memory cell MC specified by row address XADD and column address YADD. The read data may be output via a sense amplifier SAMP, a transfer gate TG, read/write amplifier107, an input/output circuit162, and data terminal116. Further, in response to active command ACT, a write signal, a row address XADD, and a column address YADD, write data may be supplied to memory cell array102via data terminal116, input/output circuit162, read/write amplifier107, transfer gate TG, and sense amplifier SAMP. The write data may be written to memory cell MC specified by row address XADD and column address YADD.

Clock signals CK and/CK may be received via clock terminals114. A clock input circuit170may generate internal clock signals ICLK based on clock signals CK and ICK. Internal clock signals ICLK may be conveyed to various components of memory device100, such as command decoder150and an internal clock generator172. Internal clock generator172may generate internal clock signals LCLK, which may be conveyed to input/output circuit162(e.g., for controlling the operation timing of input/output circuit162). Further, data mask terminals118may receive one or more data mask signals DM. When data mask signal DM is activated, overwrite of corresponding data may be prohibited.

According to one or more embodiments, memory cell array102may include a 3D NAND array including an array of memory cells (e.g., flash memory cells) arranged such that the memory cells are coupled in logical rows to access lines (also referred to herein as “word lines”). The access lines are coupled to, and in some cases are at least partially formed by, the control gates (CGs) of the memory cells. A string of memory cells of the array are coupled together in series between a SRC plate and a data line, which is conventionally referred to as a bit line.

FIG. 2is a top view of a portion of a 3D memory device200. As shown inFIG. 2, 3D memory device200(e.g., a 3D NAND array structure) includes a source (SRC) plate202, source slots204, and bit lines (BL)206. Source (SRC) plate202may be routed to a source terminal (e.g., a common source line or “CSL”) of memory device200via conductive source contacts208. For example, memory device200may be part of memory device100ofFIG. 1.

According to various embodiments of the present disclosure, a semiconductor device (e.g., including memory device100ofFIG. 1and/or memory device200ofFIG. 2) may include a protection circuit configured such that a SRC plate of the semiconductor device may be grounded during a first stage (e.g., during one or more semiconductor processing steps). More specifically, for example, the protection circuit may include one or more transistors (e.g., a NMOS field effect transistor (FET) or a series of NMOS FETS (e.g., in a cascode arrangement)) coupled between the SRC plate and a ground voltage. According to various embodiments, gates of the one or more transistors may be coupled to the SRC plate through a resistor. During one or more processing steps (e.g., one or more etching steps) the gates of the one or more transistors may be biased to the SRC voltage (i.e., through the resistor), such that the one or more transistors may operate as a forward-biased diode-connected transistor (e.g., MOSFET) and prevent the SRC plate from biasing to a high voltage.

Further, during another stage (e.g., after completion of the one or more processing steps and during operation of the semiconductor device), the protection circuit may operate as an open (e.g., highly resistive) circuit. More specifically, after completion of the one or more processing steps and during operation of the semiconductor device, the gates of the one or more transistors may be grounded (e.g., in metal) (i.e., to isolate the SRC plate from the ground voltage to prevent the one or more transistors from interfering with SRC biasing during device operation). According to some embodiments, the one or more transistors may have a sufficiently high breakdown voltage (i.e., so that the one or more transistors may not break down during device operation).

FIG. 3depicts an example circuit300, according to various embodiments of the present disclosure. Circuit300, which may be part of a semiconductor device (e.g., including memory device200ofFIG. 2and/or memory device100ofFIG. 1), includes a source (SRC) plate (also referred to herein as a “source line” or simply a “source”)302. Circuit300further includes a resistive element304(e.g., including one or more resistors) coupled between SRC plate302and a node N1. Node N1is further coupled to a deferred electrical connection component (e.g., a metal fuse)306, which is also coupled to a reference voltage (e.g., a ground voltage GRND). Deferred electrical connection component306, which may, in some embodiments, include an antifuse, may be configured to isolate node N1from ground voltage GRND during a first stage (e.g., during one or more processing steps), and couple node N1to ground voltage GRND during a second stage (e.g., during operation of an associated semiconductor device). For example only, deferred electrical connection component306may be a laser fuse, an electrical fuse, or any other suitable fuse.

Circuit300further includes a transistor M coupled between SRC plate302and ground voltage GRND. More specifically, for example, a first terminal (e.g., a gate) of transistor M is coupled to node N1, a second terminal (e.g., a source) of transistor M is coupled to ground voltage GRND, and third terminal (e.g., a drain) of transistor M is coupled to SRC plate302.

Although circuit300is depicted as including a single transistor, the present disclosure is not so limited, and circuit300may include more than one transistor (e.g., a NMOS field (e.g., a series of NMOS FETS (e.g., in a cascode arrangement)) coupled between SRC plate302and ground voltage GRND. In these embodiments, the gates of the more than one transistor may be coupled to a common node (e.g., node N1).

For example, during a first stage (e.g., during one or more processing steps to form at least a portion of semiconductor device), transistor M may be in a conductive state, and thus SRC plate302is coupled to ground voltage GRND. More specifically, during the first stage, transistor M may function as a forward-biased diode to couple SRC plate302to ground voltage GRND and prevent biasing of SRC plate302to a high voltage (e.g., around 25-35 volts or more). Further, during a second stage (e.g., during operation of the semiconductor device), node N1is grounded, and thus transistor M may be in a non-conductive state and SRC plate302is isolated from ground voltage GRND. More specifically, during the second stage, transistor M may function as an open circuit.

During device operation (i.e., operation of a semiconductor device including circuit300), current leakage through resistive element304and between SRC plate302and ground voltage GRND may exist. Thus, according to various embodiments, a value of resistive element304may be of sufficient value such that any current leakage does not interfere with device operation. More specifically, for example, a resistance value of resistive element304may be sufficiently high such that current leakage does not load a charge pump during high voltage biasing of SRC plate302. For example only, assuming a leakage current of 1 μA and a SRC bias voltage of 25 volts, a resistance value of resistive element304may be approximately 25 mega ohms (i.e., R=V/I=25V/10−6A=25 mega ohms).

FIG. 4depicts another example circuit400, according to various embodiments of the present disclosure. Like circuit300ofFIG. 3, circuit400, which may be part of a semiconductor device, includes SRC plate (also referred to herein as a “source line” or simply a “source”)402. Circuit400further includes a resistive element (e.g., including one or more resistors)404coupled between SRC plate402and a node N2. Node N2is further coupled to a deferred electrical connection component (e.g., a metal fuse)406, which is also coupled to a reference voltage (e.g., ground voltage GRND). Similar to deferred electrical connection component306, deferred electrical connection component406may include an antifuse configured to isolate node N2from ground voltage GRND during a first stage (e.g., during one or more processing steps), and couple node N2to ground voltage GRND during a second stage (e.g., during operation of an associate semiconductor device). For example only, deferred electrical connection component406may be a laser fuse, an electrical fuse, or any other suitable fuse.

Further, like circuit300, circuit400includes transistor M coupled between SRC plate402and ground voltage GRND. More specifically, for example, a first terminal (e.g., a gate) of transistor M is coupled to node N2, a second terminal (e.g., a source) of transistor M is coupled to ground voltage GRND, and third terminal (e.g., a drain) of transistor M is coupled to SRC plate402.

Although circuit400is depicted as including a single transistor, the present disclosure is not so limited, and circuit400may include more than one transistor (e.g., a NMOS field (e.g., a series of NMOS FETS (e.g., in a cascode arrangement))) coupled between SRC plate402and ground voltage GRND. In these embodiments, the gates of the more than one transistor may be coupled to a common node (e.g., node N2).

According to various embodiments, resistive element404may include a depletion resistor. More specifically, for example, resistive element404may include an N-depletion resistor. For example, a depletion resistor may be formed via a narrow N-active area including an N-implant, which may be formed via one or more implants (e.g., of one or more semiconductor device levels). For example, resistive element404may include a narrow (e.g., 0.1-0.25 um wide)N-diffusion active area, which, in some embodiments, may deplete (e.g., fully deplete) at a voltage (e.g., in the range of substantially 5-10 volts).

Further, for example, circuit400may include a field plate (e.g., a metal field plate)420coupled to a gate of transistor M. In some embodiments, field plate420, which may be positioned adjacent (e.g., over) resistive element404to assist with depletion, may be grounded during, and possibly prior to, a first stage (e.g., during, and possibly prior to, one or more processing steps (e.g., etching steps, planarization steps, implantation steps, ashing steps, other processing steps, or any combination thereof)). Alternatively, in other embodiments, field plate420may be floating during the first stage, and subsequently grounded during a second stage (e.g., during device operation).

In some embodiments wherein field plate420is coupled to the gate of transistor M (i.e., as depicted inFIG. 4), field plate420may provide feedback to improve (e.g., increase) the voltage supplied to the gate of transistor M during the first stage (i.e., one or more processing steps). After processing, and during the second stage (e.g., during device operation), field plate420and the gate of transistor M may be grounded.

Alternatively, in other embodiments, field plate420may be coupled an antenna (e.g., a number of contacts) (e.g., if an etching process associated with the antenna is an offending processing step) to bias high during the first stage (e.g., during an etching process associated with the antenna) to enable a sufficiently high voltage to be applied to the gate of transistor M. Field plate420, along with the gate of transistor M, may be grounded during, and possibly prior to, the second stage.

In at least the embodiments ofFIG. 4, resistive element404may be configured to: 1) pass a voltage to the gate of transistor M to turn transistor M ON during processing; and 2) deplete (i.e., to be highly resistive) during device operation (e.g., when a voltage is applied to SRC plate402). As will be appreciated, field plate420may amplify this effect (i.e., decrease resistance during processing and increase resistance during device operation). For example, resistive element404may be configured to fully deplete (e.g., fully deplete) at some voltage in the range of substantially 5-10 volts (“Vpass”). At applied voltages higher than voltage Vpass, resistive element404may become highly resistive. For example, during processing of one or more offending steps (e.g., charge-inducing steps), resistive element404may pass voltage Vpass to the gate of transistor M, and transistor M may conduct sufficiently (e.g., when a gate voltage of transistor M1(Vg)=Vpass) to allow current to flow from SRC plate402to ground (i.e., to ground voltage GRND). Further, for example, during device operation, (e.g., when SRC plate402is at high applied voltages), resistive element404may deplete and become highly resistive, thus reducing the parasitic SRC to ground current.

FIG. 5includes a simplified illustration of a semiconductor device500, in accordance with various embodiments of the present disclosure. Semiconductor device500includes an SRC plate502, a resistor (e.g., a diffusion resistor or a serpentine metal resistor)504, and a deferred electrical connection component506. Further, semiconductor device500includes a grounded node508(e.g., a landing pad for a through-array contact), and a dielectric510positioned between SRC plate502and grounded node508. Moreover, semiconductor device500includes a transistor518having a gate520.

According to various embodiments, during one or more semiconductor processing steps (e.g., etching steps to generate one or more contacts (e.g., node508), planarization steps, implantation steps, ashing steps, and/or other processing steps), SRC plate502may be charged, and transistor518may conduct responsive to a charge received from SRC plate502via resistor504. In some embodiments, for some etching processes, resistor504may be coupled to SRC plate502via a below-array level (e.g., a below-array metal (e.g., Tungsten) layer).

Thus, during the one or more processing steps, SRC plate502may be coupled to ground GRND via transistor518(e.g., to prevent biasing of SRC plate502to a high voltage (e.g., around 25-35 volts or higher)). Accordingly, an electric field between SRC plate502and dielectric510may be decreased (i.e., compared to conventional systems, device, and methods). As a result, stress applied to dielectric510may be decreased, which may increase reliability and/or probe yield of semiconductor device500.

Further, upon completion of the one or more semiconductor processing steps (i.e., during and possibly prior to operation of semiconductor device500), a node N3, which is coupled to gate520of transistor518, may be coupled to ground GRND via deferred electrical connection component506. More specifically, for example, gate520of transistor518may be coupled to one or more above-array metal layers (e.g., metal layer522). Thus, during device operation, SRC plate502may be isolated from ground GRND via transistor518. Although, during device operation, some parasitic leakage may occur through resistor504to node N3, the parasitic leakage may be sufficiently limited due to the resistance value of resistor504.

A contemplated operation, according to various embodiments of the present disclosure, will now be described with reference toFIGS. 3 and 4. Initially, a protection circuit300/400of a semiconductor device (e.g., semiconductor device500ofFIG. 5) may be formed (i.e., prior to at least some semiconductor processing steps). More specifically, protection circuit300/400may be formed prior to one or more offending (e.g., charge-inducing) processing steps. For example, resistive element304/404may be formed via one or more implants of one or more semiconductor layers.

Further, during at least some processing steps (e.g., one or more offending processing steps), SRC plate302/402may charge up, transistor M may turn ON (i.e., conduct), and SRC plate302/402may be coupled to ground voltage GRND. As a result, biasing of SRC plate302/402to a high voltage may be prevented. For example, the RC of resistive element304/404and the gate of transistor M be sufficiently low such that the gate voltage Vg does not significantly lag a voltage of SRC plate302/402.

Upon completion of the one or more processing steps, and prior to device operation, the gate of transistor M1may be grounded (e.g., hard-grounded) (e.g., to a back-end above-array metal). For example, the gate of transistor M1may be grounded via deferred electrical connection component306/406. Accordingly, during device operation, with the gate of transistor M grounded (e.g., hard-grounded), transistor M will not conduct (e.g., above sub-threshold leakage levels), and any parasitic leakage through resistive element304/404to ground may be limited due to a high resistance of resistive element304/404. In an embodiment wherein resistive element404comprises an N-depletion resistor, the resistance of resistive element404may be relatively high due to the depletion (e.g., full depletion) of resistive element404. Further, adding field plate420to resistive element404may further increase the resistance during device operation, and increase Vpass/Vg during processing.

FIG. 6is a flowchart of an example method600of utilizing a protection circuit, in accordance with various embodiments of the disclosure. Method600may be arranged in accordance with at least one embodiment described in the present disclosure. At least a portion of method600may be performed, in some embodiments, by a device or system, such as memory device100ofFIG. 1, memory device200ofFIG. 2, circuit300ofFIG. 3, circuit400ofFIG. 4, semiconductor device500ofFIG. 5, a memory system700ofFIG. 7, and/or an electronic system800ofFIG. 8, or another device or system. Although illustrated as discrete blocks, various blocks may be divided into additional blocks, combined into fewer blocks, or eliminated, depending on the desired implementation.

Method600may begin at block602, wherein a source plate of a semiconductor device may be coupled to a ground voltage, and method600may proceed to block604. For example, the source plate may be coupled to the ground voltage while, and possibly prior to, performing one or more semiconductor processing steps (e.g., etching processes). As an example, with reference toFIG. 3, SRC plate302may be coupled to ground voltage GRND. More specifically, during one or more offending processing steps (e.g., etching steps), SRC plate302may be charged, and, as a result, a charge may be applied to a gate of transistor M, thus causing transistor M to conduct and couple SRC plate302to ground voltage GRND.

At block604, the source plate may be isolated from the ground voltage. For example, the source plate may be isolated from the ground voltage during, and possibly prior to, operation of the semiconductor device. As an example, with reference toFIG. 3, SRC plate302may isolated from ground voltage GRND. More specifically, during, and possibly prior to operation of the semiconductor device, a gate of transistor M may be coupled to ground (e.g., ground voltage GRND). Thus, during operation of the semiconductor device, transistor M may not conduct, and therefore SRC plate302may be isolated from ground voltage GRND. Accordingly, the protection circuit may not substantially interfere with operation of the semiconductor device.

Modifications, additions, or omissions may be made to method600without departing from the scope of the present disclosure. For example, the operations of method600may be implemented in differing order. Furthermore, the outlined operations and actions are only provided as examples, and some of the operations and actions may be optional, combined into fewer operations and actions, or expanded into additional operations and actions without detracting from the essence of the disclosed embodiment. For example, a method may include one or more acts wherein a resistive element (e.g., one or more resistors) is formed between the SRC plate and a gate of a transistor, which is coupled between the SRC plate and the ground voltage. Further, for example, a method may include one or more acts wherein the gate of the transistor is coupled to ground. More specifically, for example, the gate of the transistor may be hard-grounded (e.g., via a metal fuse).

A memory system is also disclosed. According to various embodiments, the memory system may include a controller and a number of memory devices. Each memory device may include one or more memory cell arrays, which may include a number of memory cells.

FIG. 7is a simplified block diagram of a memory system700implemented according to one or more embodiments described herein. Memory system700, which may include, for example, a semiconductor device, includes a number of memory devices702and a controller704. For example, at least one memory device702may include one or more devices and/or protection circuits, as described herein. Controller704may be operatively coupled with memory devices702so as to convey command and/or address signals (e.g., command signals COM and/or address signals ADD ofFIG. 1) to memory devices702.

An electronic system is also disclosed. According to various embodiments, the electronic system may include a memory device including a number of memory dies, each memory die having an array of memory cells. Each memory cell may include an access transistor and a storage element operably coupled with the access transistor.

FIG. 8is a simplified block diagram of an electronic system800implemented according to one or more embodiments described herein. Electronic system800includes at least one input device802, which may include, for example, a keyboard, a mouse, or a touch screen. Electronic system800further includes at least one output device804, such as a monitor, a touch screen, or a speaker. Input device802and output device804are not necessarily separable from one another. Electronic system800further includes a storage device806. Input device802, output device804, and storage device806may be coupled to a processor808. Electronic system800further includes a memory system810coupled to processor808. Memory system810may include memory system700ofFIG. 7. Electronic system800may include, for example, a computing, processing, industrial, or consumer product. For example, without limitation, electronic system800may include a personal computer or computer hardware component, a server or other networking hardware component, a database engine, an intrusion prevention system, a handheld device, a tablet computer, an electronic notebook, a camera, a phone, a music player, a wireless device, a display, a chip set, a game, a vehicle, or other known systems.

Various embodiments of the present disclosure may include a device. The device may include a source (SRC) plate configured to couple to a number of memory cells of a memory device. The device may further include a resistor having a first end coupled to the SRC plate. Also, the device may include at least one transistor coupled between the SRC plate and a ground voltage, a gate of the at least one transistor coupled to a second end of the resistor.

According to another embodiment of the present disclosure, a method may include coupling a source plate of a semiconductor device to a ground voltage during one or more semiconductor processing steps. The method may also include isolating the source plate from the ground voltage during operation of the semiconductor device.

Additional embodiments of the present disclosure include an electronic system. The electronic system may include at least one input device, at least one output device, and at least one processor device operably coupled to the input device and the output device. The electronic system may also include at least one memory device operably coupled to the at least one processor device. The at least one memory device may include a source plate coupled to an array of memory cells. The at least one memory device may also include a protection circuit including at least one transistor coupled between the source plate and a ground voltage. A gate of the transistor is coupled to the ground voltage such that the transistor isolates the source plate from the ground voltage. The protection circuit further includes a resistor coupled between the source plate and the gate of the transistor.

As used herein, the term “device” or “memory device” may include a device with memory, but is not limited to a device with only memory. For example, a device or a memory device may include memory, a processor, and/or other components or functions. For example, a device or memory device may include a system on a chip (SOC).

As used herein, the term “semiconductor” should be broadly construed, unless otherwise specified, to include microelectronic and MEMS devices that may or may not employ semiconductor functions for operation (e.g., magnetic memory, optical devices, etc.).

Additionally, the use of the terms “first,” “second,” “third,” etc., are not necessarily used herein to connote a specific order or number of elements. Generally, the terms “first,” “second,” “third,” etc., are used to distinguish between different elements as generic identifiers. Absence a showing that the terms “first,” “second,” “third,” etc., connote a specific order, these terms should not be understood to connote a specific order. Furthermore, absence a showing that the terms “first,” “second,” “third,” etc., connote a specific number of elements, these terms should not be understood to connote a specific number of elements.

The embodiments of the disclosure described above and illustrated in the accompanying drawings do not limit the scope of the disclosure, which is encompassed by the scope of the appended claims and their legal equivalents. Any equivalent embodiments are within the scope of this disclosure. Indeed, various modifications of the disclosure, in addition to those shown and described herein, such as alternative useful combinations of the elements described, will become apparent to those skilled in the art from the description. Such modifications and embodiments also fall within the scope of the appended claims and equivalents.