Patterning method

A patterning method is disclosed. A hard mask layer, a lower pattern transfer layer, an upper pattern transfer layer are formed on a target layer. A first SARP process is performed to pattern the upper pattern transfer layer into an upper pattern mask. A second SARP process is performed to pattern the lower pattern transfer layer into a lower pattern mask. The upper pattern mask and the lower pattern mask define hole patterns. The hole patterns is filled with a dielectric layer. The dielectric layer and the upper pattern mask are etched back until the lower pattern mask is exposed. The lower pattern mask is removed, thereby forming island patterns. Using the island patterns as an etching hard mask, the hard mask layer is patterned into hard mask patterns. Using the hard mask patterns as an etching hard mask, the target layer is patterned into target patterns.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to the field of integrated circuit manufacturing. More particularly, the present invention relates to a patterning method for forming integrated circuit features on a wafer with improved manufacturability.

2. Description of the Prior Art

Integrated circuit (IC) dimensions are desired to be constantly scaled down with advancement of technology. Integrated circuit features are traditionally patterned via photolithographic processes. However, the current photolithography technology is reaching its limit of resolution.

As the degree of integration of semiconductor devices increases, it may be difficult to form ultrafine patterns using photolithography processes that exceed the limit of resolution. There is always a need in this industry to provide a resolution enhancement method for optical lithography with improved manufacturability

SUMMARY OF THE INVENTION

It is one object of the invention to provide a patterning method for forming integrated circuit features on a wafer with improved manufacturability.

According to one aspect of the invention, a patterning method is disclosed. A substrate having thereon a target layer is provided. A hard mask layer is formed on the target layer. A lower pattern transfer layer is formed on the hard mask layer. An upper pattern transfer layer is formed on the lower pattern transfer layer. A first self-aligned reverse patterning (SARP) process is performed to pattern the upper pattern transfer layer into an upper pattern mask on the lower pattern transfer layer. A second self-aligned reverse patterning (SARP) process is performed to pattern the lower pattern transfer layer into a lower pattern mask. The upper pattern mask and the lower pattern mask together define an array of hole patterns. The array of hole patterns is filled with an organic dielectric layer. The organic dielectric layer and the upper pattern mask are etched back until the lower pattern mask is exposed. The lower pattern mask is removed, leaving remnants of the organic dielectric layer on the hard mask layer to form island patterns. Using the island patterns as an etching hard mask, the hard mask layer is patterned into hard mask patterns. Using the hard mask patterns as an etching hard mask, the target layer is patterned into target patterns.

DETAILED DESCRIPTION

The present invention has been particularly shown and described with respect to certain embodiments and specific features thereof. The embodiments set forth herein below are to be taken as illustrative rather than limiting. It should be readily apparent to those of ordinary skill in the art that various changes and modifications in form and detail may be made without departing from the spirit and scope of the invention.

Before the further description of the preferred embodiment, the specific terms used throughout the text will be described below.

The term “etch” is used herein to describe the process of patterning a material layer so that at least a portion of the material layer after etching is retained. For example, it is to be understood that the method of etching silicon involves patterning a mask layer (e.g., photoresist or hard mask) over silicon and then removing silicon from the area that is not protected by the mask layer. Thus, during the etching process, the silicon protected by the area of the mask will remain.

In another example, however, the term “etch” may also refer to a method that does not use a mask, but leaves at least a portion of the material layer after the etch process is complete. The above description is used to distinguish between “etching” and “removal”. When “etching” a material layer, at least a portion of the material layer is retained after the end of the treatment. In contrast, when the material layer is “removed”, substantially all the material layer is removed in the process. However, in some embodiments, “removal” is considered to be a broad term and may include etching.

The terms “forming”, “depositing” or the term “disposing” are used hereinafter to describe the behavior of applying a layer of material to the substrate. Such terms are intended to describe any possible layer forming techniques including, but not limited to, thermal growth, sputtering, evaporation, chemical vapor deposition, epitaxial growth, electroplating, and the like.

According to various embodiments, for example, deposition may be carried out in any suitable known manner. For example, deposition may include any growth, plating, or transfer of material onto the substrate. Some known techniques include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), atomic layer deposition (ALD), and plasma enhanced CVD (PECVD).

The term “substrate” described in the text is commonly referred to as a silicon substrate. However, the substrate may also be any semiconductor material, such as germanium, gallium arsenide, indium phosphide and the like. In other embodiments, the substrate may be non-conductive, such as glass or sapphire wafers.

The present invention pertains to a patterning method for forming semiconductor features such as dense lines, spaces, vias, or pads on a substrate or wafer. In an exemplary embodiment, as will be described in more detail below, a patterning method for forming dense storage node (SN) pads in the cell array region of a dynamic random access memory (DRAM) device is disclosed.

Please refer toFIG. 1AtoFIG. 13AandFIG. 1BtoFIG. 13B.FIG. 1AtoFIG. 13Aare schematic top-view diagrams showing an exemplary patterning method for forming semiconductor features on a substrate according to one embodiment of the invention.FIG. 1BtoFIG. 13Bare schematic, cross-sectional diagrams taken along line I-I′ inFIG. 1AtoFIG. 13A, respectively.

First, as shown inFIG. 1AandFIG. 1B, a substrate10is provided. For example, the substrate10may comprise a silicon substrate, but is not limited thereto. For the sake of simplicity, only a portion of a cell array region101and a portion of a peripheral region102are illustrated. Memory cells such as DRAM cells are to be formed within the cell array region101.

According to one embodiment, the substrate10may comprise an inter-layer dielectric layer110and contact elements112and114in the inter-layer dielectric layer110. The contact elements112are disposed in the cell array region101and function as storage node contacts. The contact elements114are disposed in the peripheral region102and may be electrically coupled to terminals (e.g., source terminals, drain terminals, or gate electrodes) of transistors.

According to one embodiment, the inter-layer dielectric layer110may comprise a dielectric material such as silicon oxide or silicon nitride, but is not limited thereto. According to one embodiment, the contact elements112and114may comprise metal such as tungsten.

According to one embodiment, a target layer120to be patterned into dense storage node pads in the cell array region101is provided on the inter-layer dielectric layer110. The target layer120may comprise metal such as tungsten. The target layer120is in direct contact with the contact elements112and114. The target layer120is in direct contact with the inter-layer dielectric layer110. According to one embodiment, the target layer120may be deposited on a top surface of the inter-layer dielectric layer110in a blanket manner.

According to one embodiment, a hard mask layer130is disposed on the target layer120. For example, the hard mask layer130may comprise silicon nitride. According to one embodiment, an advanced patterning film140may be disposed on the hard mask layer130. According to one embodiment, the advanced patterning film140may comprise amorphous carbon layer.

An anti-reflection layer150may be disposed on the advanced patterning film140. According to one embodiment, the anti-reflection layer150may comprise silicon oxy-nitride (SiON).

According to one embodiment, a lower pattern transfer layer160is disposed on the anti-reflection layer150. An upper pattern transfer layer170is disposed on the lower pattern transfer layer160. For example, the lower pattern transfer layer160may comprise polysilicon, and the upper pattern transfer layer170may comprise silicon nitride.

Subsequently, as shown inFIG. 2A,FIG. 2B,FIG. 3A, andFIG. 3B, a first self-aligned reverse patterning (SARP) process (or referred to as “reverse self-aligned double patterning”; “reverse SADP”) is performed to pattern the upper pattern transfer layer170into an upper pattern mask170aon the lower pattern transfer layer160.

For example, as can be seen inFIG. 2AandFIG. 2B, a first structure layer L1is formed. The first structure layer L1includes an organic dielectric layer180coated onto the upper pattern transfer layer170. A bottom anti-reflection coating (BARC) layer190such as a silicon-containing spin-on material may be coated on the organic dielectric layer180. A photoresist layer200is formed on the BARC layer190.

Thereafter, straight-line shaped photoresist patterns200a, which extend along the reference y-axis and have a pitch P1, may be formed on the BARC layer190only within the cell array region101.

After the first SARP process, as can be seen inFIG. 3A, the upper pattern mask170acomprises straight-line shaped patterns, which extend along the reference y-axis and have a pitch P2. According to one embodiment, the pitch P2is smaller than the pitch P1. For example, the pitch P2is one-half of the pitch P1. It is noteworthy that the upper pattern mask170ais only formed within the cell array region101. The upper pattern transfer layer170within the peripheral region102is not patterned at this stage.

FIG. 14toFIG. 19illustrate the first SARP process in more detail. For the sake of simplicity, throughFIG. 14toFIG. 19, the substrate and layers under the lower pattern transfer layer160are omitted. As shown inFIG. 14, as previously described inFIG. 2B, an organic dielectric layer180is coated onto the upper pattern transfer layer170. A bottom anti-reflection coating layer190is then formed on the organic dielectric layer180. Thereafter, straight-line shaped photoresist patterns200a, which extend along the reference y-axis direction at pitch P1, are formed on the BARC layer190. The bottom anti-reflection coating layer190and the organic dielectric layer180are collectively referred to as a first structure layer.

The straight-line shaped photoresist patterns200aare formed by performing a lithographic process including, but not limited to, photoresist coating, baking, exposure, and development.

Subsequently, as shown inFIG. 15, using the straight-line shaped photoresist patterns200aas a hard mask, an anisotropic etching process is performed to etch the first structure layer, to thereby pattern the first structure layer into first straight line-shaped structure patterns280.

Aligning with the straight-line shaped photoresist patterns200a, the first straight line-shaped structure patterns280also extend along the reference y-axis direction and have the pitch P1.

As shown inFIG. 16, first spacers290are formed on sidewalls of the first straight line-shaped structure patterns280, respectively. For example, the first spacers290may comprise silicon oxide, but is not limited thereto. To form the first spacers290, a spacer material layer such as a silicon oxide layer is conformally deposited onto the first straight line-shaped structure patterns280inFIG. 15, and an anisotropic dry etching process is performed to etch the spacer material layer.

As shown inFIG. 17, the remnants of the first straight line-shaped structure patterns280are removed, leaving the first spacers290intact. The remnants of the first straight line-shaped structure patterns280may be removed by using oxygen plasma ashing process, but is not limited thereto. The first spacers290are also straight line-shaped and have a reduced pitch P2.

As shown inFIG. 18, using the first spacers290as an etching hard mask, an anisotropic dry etching process is performed to etch the upper pattern transfer layer170with the pitch P2. At this point, the upper pattern transfer layer170is patterned into the upper pattern mask170a.

As shown inFIG. 19, after the formation of the upper pattern mask170a, the remaining first spacers300are removed.

As shown in as shown inFIG. 4A,FIG. 4B,FIG. 5A, andFIG. 5B, a second self-aligned reverse patterning (SARP) process is performed to pattern the lower pattern transfer layer160into a lower pattern mask160a. As shown inFIG. 5AandFIG. 5B, the upper pattern mask170aand the lower pattern mask160atogether define an array of hole patterns161.

The second SARP process is similar with the steps as set forth throughFIG. 14toFIG. 19. For example, a second structure layer L2is formed on the upper pattern mask170aand on the exposed top surface of the lower pattern transfer layer160. Likewise, the second structure layer L2may comprise an organic dielectric layer380on the upper pattern mask170a, a bottom anti-reflection coating layer390on the organic dielectric layer380, and a photoresist layer400on the bottom anti-reflection coating layer390.

Thereafter, straight-line shaped photoresist patterns400a, which extend along the reference a direction at pitch P1may be formed on the BARC layer190only within the cell array region101. According to one embodiment, the reference a direction is not perpendicular to the reference y-axis.

Subsequently, as shown inFIG. 20, a lithographic process and an etching process are performed to pattern the second structure layer L2into second straight line-shaped structure patterns480extending along the reference a direction. Subsequently, similar with the steps set forth inFIG. 16, second spacers are formed on sidewalls of the second straight line-shaped structure patterns480, respectively. Subsequently, similar with the steps set forth inFIG. 17, the second straight line-shaped structure patterns480are removed. Then, similar withFIG. 18, using the second spacers and the upper pattern mask170aas an etching hard mask, the exposed lower pattern transfer layer160is etched, thereby forming the lower pattern mask160a. The second spacers are then removed, similar withFIG. 19.

FIG. 21is a perspective view showing a mask stack structure in the second SARP process. For the sake of simplicity, the substrate and the layers under the anti-reflection layer150are omitted. As shown inFIG. 21, a mask stack structure consisting of the lower pattern mask160aand the upper pattern mask170ais formed. The upper pattern mask170acomprises straight line-shaped patterns extending along the reference y-axis direction, and the lower pattern mask160ais a lattice pattern. As can be seen inFIG. 5B, at this point, each of the hole patterns161may have a rhombus shape when viewed from above.

FIG. 6toFIG. 9illustrate the steps for forming patterns in the peripheral region102. As shown inFIGS. 6A and 6B, a third structure layer L3is formed on the mask stack structure formed in the second SARP process as shown inFIG. 5AandFIG. 5B. Likewise, the third structure layer L3may comprise an organic dielectric layer480on the upper pattern mask170ain the cell array region101and on the upper pattern transfer layer170in the peripheral region102, a bottom anti-reflection coating layer490on the organic dielectric layer480, and a photoresist layer500on the bottom anti-reflection coating layer490.

By performing a lithographic process, a photoresist pattern500ais formed within the peripheral region102. The photoresist pattern500aincludes openings501that define a first feature pattern in the peripheral region102.

As shown inFIGS. 7A and 7B, using the photoresist pattern500aas an etching hard mask, a anisotropic dry etching process is performed to etch the anti-reflection coating layer490, the organic dielectric layer480, and the upper pattern transfer layer170in the peripheral region102, thereby forming a first peripheral mask pattern170b.

As shown inFIGS. 8A and 8B, a fourth structure layer L4is formed on the mask stack structure formed in the second SARP process as shown inFIG. 5AandFIG. 5B, and on the first peripheral mask pattern170bin the peripheral region102. Likewise, the fourth structure layer L4may comprise an organic dielectric layer580on the upper pattern mask170ain the cell array region101and on the first peripheral mask pattern170bin the peripheral region102, a bottom anti-reflection coating layer590on the organic dielectric layer580, and a photoresist layer600on the bottom anti-reflection coating layer590.

By performing a lithographic process, a photoresist pattern600ais formed within the peripheral region102. The photoresist pattern600aincludes openings601that define a second feature pattern in the peripheral region102. The second feature pattern may be disposed in proximity to the first feature pattern defined in the first peripheral mask pattern170bwhen viewed from above.

As shown inFIGS. 9A and 9B, using the photoresist pattern600aas an etching hard mask, an anisotropic dry etching process is performed to etch the anti-reflection coating layer590, the organic dielectric layer580, and the upper pattern transfer layer170in the peripheral region102, thereby forming a second peripheral mask pattern170cin the peripheral region102. The second peripheral mask pattern170cis then transferred to the underlying lower pattern transfer layer160in the peripheral region102, to thereby form a third peripheral mask pattern160bin the peripheral region102. Thereafter, the remaining fourth structure layer L4is removed to reveal the mask stack structure in the cell array region101.

FIG. 10toFIG. 13illustrate the steps for transferring the array of hole patterns161in the cell array region and the third peripheral mask pattern160binto the target layer120by using a reverse tone patterning method.

As shown inFIG. 10AandFIG. 10B, the array of hole patterns161in the cell array region101and the openings defined by the third peripheral mask pattern160bin the peripheral region102are filled with an organic dielectric layer. The organic dielectric layer680, the upper pattern mask170a, and the second peripheral mask pattern170care etched back until the lower pattern mask160ain the cell array region101and the third peripheral mask pattern160bare exposed.

Next, as shown inFIG. 11AandFIG. 11B, the lower pattern mask160aand the third peripheral mask pattern160bare removed, leaving remnants of the organic dielectric layer180on the hard mask layer150to form island patterns680aand680b.

As shown inFIG. 12AandFIG. 12B, using the island patterns680aand680bas an etching hard mask, an anisotropic dry etching process is performed to pattern the hard mask layer130into hard mask patterns130aand130b. During the anisotropic dry etching process, the advanced patterning film140is also etched into patterns140aand140bdirectly on the hard mask patterns130aand130b, respectively.

As shown inFIGS. 13A and 13B, using the hard mask patterns130aand130bas an etching hard mask, an anisotropic dry etching process is performed to pattern the target layer120into target patterns120ain the cell array region101and target patterns120bin the peripheral region102. The remaining hard mask patterns130aand130bmay be removed. According to one embodiment, the target patterns120ain the cell array region101may function as storage node pads. The target patterns120aand120bare formed directly on the inter-layer dielectric layer110, and the target patterns120aand120bmay be electrically coupled to the contact elements112and114, respectively.

According to another embodiment of the invention, the remaining hard mask patterns130aand130bmay be kept in the semiconductor structure.FIG. 22toFIG. 24illustrate an exemplary method for forming storage node openings on the storage node pads in the cell array region. As shown inFIG. 22, after the patterning of the storage node pads or target patterns120ain the cell array region101, the remaining hard mask patterns130aare not removed.

As shown inFIG. 23, subsequently, an etch stop layer710such as SiCN is conformally deposited on the target patterns120aand the remaining hard mask patterns130a. A dielectric layer712such as SiN is then deposited on the etch stop layer710, and a cap dielectric layer714is deposited on the dielectric layer712.

As shown inFIG. 24, a lithographic process and a dry etching process are performed to etch the cap dielectric layer714, the dielectric layer712, the etch stop layer710, and the remaining hard mask patterns130adirectly on the target patterns120ain the cell array region101, thereby forming storage node openings800.

It is advantageous to keep the remaining hard mask patterns130adirectly on the target patterns120ain the cell array region101, because this improves the punch through window when forming the storage node openings800and also improves the storage node bottom stress stability.

FIG. 25toFIG. 29illustrate various shapes of the storage node pads in the cell array region101according to embodiments of the invention. As shown inFIG. 25, when viewed from the above, the storage node pads or target patterns120ain the cell array region101may have hexagonal-packed pattern, and each of the storage node pads or target patterns120amay have a rhombus shape.

As shown inFIG. 26, when viewed from the above, the storage node pads or target patterns120ain the cell array region101may have hexagonal-packed pattern, and each of the storage node pads or target patterns120amay have a circular shape.

As shown inFIG. 27, when viewed from the above, the storage node pads or target patterns120ain the cell array region101may have hexagonal-packed pattern, and each of the storage node pads or target patterns120amay have an oval shape or ellipse shape.

As shown inFIG. 28, when viewed from the above, the storage node pads or target patterns120ain the cell array region101may have hexagonal-packed pattern, and each of the storage node pads or target patterns120amay have a square shape.

As shown inFIG. 28, when viewed from the above, the storage node pads or target patterns120ain the cell array region101may have hexagonal-packed pattern, and each of the storage node pads or target patterns120amay have a square shape with four rounded corners.