Sensitivity and static timing analysis for integrated circuit designs using a multi-CCC current source model

In one embodiment of the invention, a multi-CCC current source model is disclosed to perform statistical timing analysis of an integrated circuit design. The multi-CCC current source model includes a voltage waveform transfer function, a voltage dependent current source, and an output capacitor. The voltage waveform transfer function receives an input voltage waveform and transforms it into an intermediate voltage waveform. The voltage dependent current source generates an output current in response to the intermediate voltage waveform. The output capacitor is coupled in parallel to the voltage dependent current source to generate an output voltage waveform for computation of a timing delay.

FIELD

The embodiments of the invention relate generally to integrated circuit design software tools, such as static timing analysis software tools and signal integrity analysis software tools for designing integrated circuits.

BACKGROUND

Electronic computer aided design (ECAD) software tools for static timing analysis (STA) may be used to estimate timing delays in an electronic circuit such as that found in an integrated circuit. However as process technology improves so that smaller transistor channels of 65 nano-meters (nm) and 45 nm become available, there is an increased need for even more accurate timing analysis. Additionally with the smaller geometries there may be a number of unknown effects to electronic signal propagation that may be considered, which may not have been as severe with more relaxed process technology nodes.

BRIEF SUMMARY

The embodiments of the invention are summarized by the claims that follow below.

DETAILED DESCRIPTION

In the following detailed description of the embodiments of the invention, numerous specific details are set forth in order to provide a thorough understanding. However, it will be obvious to one skilled in the art that the embodiments of the invention may be practiced without these specific details. In other instances well known methods, procedures, components, and circuits have not been described in detail so as not to unnecessarily obscure aspects of the embodiments of the invention.

Introduction

FIG. 1Aillustrates an exemplary integrated circuit design flow100employing embodiments of the invention. Digital performance analysis software tools, such as Static Timing Analysis (STA) software tools and Signal Integrity (SI) Analysis software tools101, are used to estimate the performance of an integrated circuit chip. As shown inFIG. 1A, these software tools may internally employ different levels of abstraction, a graph level abstraction, a net level abstraction, and a shape level abstraction.

At the graph level of abstraction, the highest level, the software tool works with the entire circuit design as a design graph. The graph level abstraction propagates quantities or metrics of interest from the inputs of the circuit design to the outputs of the circuit design. For example, an STA tool may propagate arrival times throughout the circuit design.

At the net level of abstraction, the STA software tool calculates quantities of interest for each of the nets in the design. While doing an SI analysis, an SI analysis software tool may calculate the crosstalk glitch induced on a specific net.

At the shape level of abstraction, the software tools work with information from the actual chip layout. The information may include device sizes and interconnect parasitics, for example, such as can be obtained from a parasitic extractor.

In some embodiments of the invention, an electrical calculation engine component or delay calculator102is provided for the net level abstraction layer of electrical analysis software tools.

Referring now toFIG. 1B, a block diagram of a multi-CCC gate delay calculator (EOS)102is illustrated. The multi-CCC gate delay calculator (EOS)102may also be referred to herein as an electrical calculator. The delay calculator102receives characterization data104and a netlist106to generate timing delays108(e.g., max timing delay, min timing delay) including process sensitivities. The characterization data104may be part of a cell library of logic cells.

The delay calculator102includes an application programming interface (API)110, an interconnect reducer & analysis engine112, a gate simulation engine114, and a multi-CCC current source model116coupled together as shown.

The interconnect reducer & analysis engine112receives the netlist106including a defined interconnect of standard cells to reduce it down to a simplified model for use with the gate simulation engine114. The interconnect reduction and analysis engine112reduces the extracted parasitic network down to a simplified load model. Typically, the extracted parasitic network corresponding to an output net can be very large. Since only the inputs and outputs of the net need to be monitored, the interconnect network may be reduced to create a smaller, electrically equivalent representation speeding up delay calculations while preserving the input-to-output electrical behavior of the net.

The multi-CCC current source model116, described in further detail below, receives the characterization data104and models single-CCC and multi-CCC standard cells in response to the type of standard cell in the netlist that is being analyzed in a given stage of a delay path. The multi-CCC current source model116describes the electrical behavior of a standard cell in an abstract fashion in order to speed electrical calculations, such as delay calculations and noise delay calculations, and sensitivity calculations. The parameters of the gate model are usually derived by a library characterization process, such as described below.

The gate simulation engine114calculates the output waveform at the output of a given gate in response to the input stimulus as well as the multi-CCC current source model116and its parameters. A simplified load model may be used to model the effect of the interconnect loading on the gate. A noise model may also be used to model noise from aggressors in the standard cell.

The parameters for each standard cell to fashion its corresponding gate model are typically stored in a standard cell library. The IC netlist design data is stored in some form in the host tool. One or more application programming interfaces (API)110interact with the library and the design data to read information there-from. Another one or more APIs110may be used by graph level engines, operating at the graph level on the netlist to determine delays along data paths for example, to call the delay calculator110and obtain the timing results of the calculations at each gate along a graphed path.

A current source model for a multi-CCC structure described below may be used for both delay and SI calculations. Thus, a single characterization process may yield a gate model for both delay and SI calculations.

FIG. 1Cillustrates a block diagram of a portion of an exemplary netlist including a plurality of delay paths DP1-DPi from D flip-flops/latches/registers121A-121B multiplexed into a D flip-flop/latch/register121C by a multiplexer122. The delay calculator102may be used to compute the timing delays through the delay paths between the D flip-flops/latches/registers121A-121B and the D flip-flop/latch/register121C.

The delay paths DP1-DPi may have various stages of single-CCC and multi-CCC standard cells. A first delay path DP1includes a single stage Stage1. A second delay path DP2includes two stages, Stage1and Stage2. A third delay path DP3includes M stages, Stage1through StageM. An ithdelay path Dpi includes N stages, Stage1through StageN.

FIG. 1Dillustrates an exemplary pair of stages of standard cells, Stage(i) and Stage(i+1). The stage(i) may be modeled by a driver130driving a coupled RC interconnect network132and an load impedance Zr136. One or more neighbor nets133-135may induce noise through the coupled RC interconnect network132. A voltage source Vi representing a rising or falling transition is connected at the input of driver130. In response to the input voltage Vi, the coupled RC interconnect network132, and the load impedance Zr136; the driver130generates an output voltage Vo at the one or more outputs of the stage(i). However, the description herein describes a model with a single output that may be readily duplicated for a standard cell with a plurality of outputs.

Referring now toFIG. 2A, a schematic diagram of an exemplary standard cell in a netlist is illustrated. This is the view seen by the electrical delay calculator working at a gate or net level abstraction layer. The standard cell includes a driver130, the RC interconnect network132connected to the output of the driver consisting of one or more resistors210-211and one or more capacitors221-224, the extracted parasitics136associated with the output net Vo201(seeFIG. 1D) coupled together as shown. One or more receivers138are coupled to the output net Vo201and may add to the extracted parasitics136. An aggressor driver233may generate an aggressor signal250coupled into the interconnect network132. An aggressor receiver238may also influence the generation of the aggressor signal250, adding additional parasitic load to the network132.

FIG. 2Billustrates waveform diagrams200,250, and201A-201B respectively of the Vin signal200, the aggressor signal250, and the victim or Vo output signal201. The objective of the electrical delay calculator102is to calculate the waveforms at the output net Vo which is input to each of the receivers138of the net, and return quantities of interest about the waveform to the graph level abstraction layer. In this case, the delay calculator102applies the input signal Vin200as a stimulus when simulating the responses at the receiver inputs. For static timing analysis (STA), the quantity of interest is the timing delay from the input Vin200into the driving gate130and the output net Vo201that is coupled to the input of the receiver138in the next stage. For noise or signal integrity analysis, the quantity of interest may be the amount of crosstalk delay generated on the output net Vo201by the aggressor driver233.

Without any aggressor driver233or when node250is quiet, the delay calculator102may generate a relatively smooth output waveform201A on the Vo output signal201that has a timing delay TD0not affected by coupling noise (or crosstalk). When aggressor driver233and node250are switching, the delay calculator102may generate a noisy output waveform201B on the Vo output signal201that has a timing delay TDN which is affected by coupling noise that may be greater than the timing delay TD0without coupling noise. That is, the switching of the aggressor driver233may cause additional delay in the signal generated by the stage on the output net Vo201.

Models and Characterization

The multi-CCC current source model used in the delay calculator, may also be referred to herein as a ViVo II model. The multi-CCC current source model is capable of accurately supporting standard cells with both single-channel connected components (single-CCC) and multi-channel connected components (multi-CCC). Channel-connected components (CCCs) are found within standard circuit cells (or simply standard cells) of a standard cell library.

A single channel connected component (single-CCC) includes transistors connected to each other by their drain and/or source terminals between paths from the positive power supply VDD to the negative power supply VSS or ground. The boundary of a CCC is at a gate terminal or an input or output terminal of the standard cell.

Standard cells with multi-channel connected components (multi-CCCs) include a plurality of single-CCCs coupled in series together at gate terminals between inputs and outputs of the standard cell.

FIG. 3Aillustrates an exemplary single-CCC standard cell300A. The standard cell300A is a NOR logic gate with sources/drains of transistors301-304coupled together between the positive power supply VDD and the negative power supply VSS. Standard cells for an inverter and NAND gate are also single-CCC standard cells. There are no other CCCs between the inputs IN1, IN2and the output OUT.

FIG. 3Billustrates an exemplary multi-CCC standard cell300B. The multi-CCC standard cell300B includes a first single-CCC310A and a second single-CCC310B coupled in series together between the input IN and the output OUT of the standard cell300B. The single-CCC310A includes transistors311-313. The sources/drains of transistors311-313are coupled together between the positive power supply VDD and the negative power supply VSS. A source or drain of transistor313couples to the gate terminals of transistors314and315at the boundaries of the first and second single-CCCs310A-310B. The single-CCC310B includes transistors314-315. The sources/drains of transistors314-315are coupled together between the positive power supply VDD and the negative power supply VSS.

FIG. 3Cillustrates another exemplary multi-CCC standard cell300C. The multi-CCC standard cell300C is an AND gate and includes a first single-CCC (NAND gate)320A and a second single-CCC (inverter)320B coupled in series together between the inputs IN1, IN2and the output OUT of the standard cell300C. The single-CCC320A includes transistors321-324. The sources/drains of transistors321-324are coupled together between the positive power supply VDD and the negative power supply VSS. The single-CCC320B includes transistors325-326. The sources/drains of transistors325-326are coupled together between the positive power supply VDD and the negative power supply VSS. Other exemplary multi-CC standard cells include a non-inverting buffer formed by a pair of inverters coupled in series together, an OR gate formed by a NOR gate coupled in series to an inverter, an exclusive-NOR (XNOR) gate formed by a pair of parallel NOR gates coupled in series to an additional NOR gate, and an exclusive-OR (XOR) gate formed by a pair of parallel NAND gates coupled in series to an additional NAND gate.

The ViVo II multi-CCC current source model (i) treats standard cells (with either single-CCCs or multi-CCS) as black boxes during characterization; (ii) compacts the model, which is independent of output load and much less dependent on the number of input slews to use during characterization; and (iii) encapsulates internal waveform distortion and internal delay in multi-CCC standard cells efficiently.

FIG. 4Aillustrates an abstracted view of a multi-CCC standard cell, such as an XOR gate400. The exemplary XOR gate400may be modeled by a voltage transform function401to transform the input voltage Vi(t) into an intermediate voltage Vc(t); and a last stage or driver stage402to generate an output voltage Vo(t) and an output current Io(t) in response to the intermediate voltage Vc(t). The voltage transform function401may also be referred to herein as a delay transfer function may represent one or more internal stages of a multi-CCC standard cell.

The goal of ViVo II multi-CCC current source model is to characterize the gate's driving capability and to provide a simple abstraction which captures the output current waveform in the presence of multiple internal stages. The current through a single CCC can be described accurately based on a two dimensional DC current function F(Vi(t),Vo(t)). For a multi-CCC cell the current Io(t) waveform at the output of the standard cell400is dictated by the instantaneous input voltage at the last CCC402, which we denote as Vc(t). Thus, the current through a multi-CCC standard cell is a function of the instantaneous input voltage at the last CCC402which can be denoted by I=F(Vc(t),Vo(t)). In order to find Vc(t) from Vi(t), a waveform transfer function401can be used to map the input voltage transition to an intermediate voltage transition.

A multi-CCC current source model therefore may consist of two major components: (i) the dc current function modeling drawn current as a function of instantaneous input and output voltages and their time derivatives of the last CCC of the cell, and (ii) a waveform transfer function defining the waveform at the input of the last CCC as a function of the waveform at the cell's input.

A one straightforward way to construct these two parts is to perform a series of spice simulations where the node which is the input of the cell's lass CCC is directly probed or stimulated, respectively. However, while this approach is feasible, an understanding of the internal topology of the cell's circuit and a partition of the circuit into one or more CCCs must be performed. Instead, the embodiments of the invention treat a standard cell as a black box without having to understand the internal topology of a circuit and partition it into CCCs. Thus, the construction of the two components of the model is done through fitting the results of a series of spice simulations where excitation and probing points are only the standard cell's interface (e.g., input/output) pins.

ViVo II Multi-CCC Current Source Model

FIG. 4Billustrates the ViVo II multi-CCC current source model410. The multi-CCC current source model410includes two parts as explained in the previous section.

The first part is an internal waveform transformation function401which transforms the input voltage Vi(t) into the intermediate voltage Vc(t) by Equation 1 as follows:
Vc(t)=Γ(Vt(t))  (1)

Note that the intermediate voltage Vc(t) models a delay and distortion of the input signal transition as it propagates through a standard cell's circuit up until the input to the last CCC. Fitting techniques may be used to map the input signal to the intermediate voltage signal Vc(t).

The second part is a voltage dependent current source which characterizes the driving CCC402. It consists of a voltage dependent current source I=F(Vc,V0)412, which gives the driving current for any Vcand V0value and their derivatives:

In Equation 2, Fdcis a DC component of the current source defining the current value based on the values Vcand V0. The second and third terms in Equation 2 model the dynamic current due to Miller effect from input to the output of the last CCC of the cell and output pin capacitance of the cell. The coefficients of the two latter terms are nonlinear Miller and output pin capacitances which in general depend upon voltages Vc, Vo. However, since the contribution of the last dynamic term in Eq. (2) is usually small, characterizing the Cgfor the initial input voltage Vi (t=0) suffices to provide sufficiently accurate results.

FIG. 5illustrates the application of Γ(V(t)) which converts an input voltage waveform Vi(t) of slew σ into an intermediate voltage waveform Vc(t) in accordance with one embodiment of the invention. In one embodiment of the invention, the transformation function Γ which is used to generate the intermediate voltage Vc(t) in voltage transformation equation (Eq. 1) is as follows:

In Equation 3, Fσ(ν) is a normalized time transfer function (time versus time) with time normalization being defined by

v=t-τστσ.
As show by the input voltage Vi(t) versus time chart ofFIG. 5, τiand Tiare respectively the starting time and the duration of the input voltage Vi(t) transition from high to low. Alternatively, τiand Timay be the starting time and the duration of the input voltage Vi(t) transition from low to high, respectively.

As shown by the intermediate voltage Vc(t) versus time chart ofFIG. 5, τσis the starting time of the transition in the intermediate voltage Vc(t) and Tσis the transition period of the intermediate voltage Vc(t).

The function Fσ(ν) captures the non-linear waveform shape change from Vi(t) to Vc(t). Fσ(ν), Tσand τσare all functions of the slew rate σ (change in voltage over time) of the input voltage Vi(t) and are stored in tables indexed by σ.FIG. 11illustrates an exemplary table of values for Tσand τσas a function of a reference slew rate σref, a fast slew rate σfast, and a slow slew rate σslowof the input voltage Vi(t).FIG. 12illustrates an exemplary table of values for Fσ(ν) as a function of a reference slew rate σref, a fast slew rate σfast, and a slow slew rate σslowover the normalized time ν which varies from 0 to 1.

In its application, the multi-CCC current source model captures the slew rate σ from the voltage input waveform Vi(t), which is then used to look up the corresponding values for Tσ, τσand Fσ(V) from look up tables, such as the tables illustrated inFIG. 11andFIG. 12, respectively. The model then applies the voltage transformation equation (Eq. 3) to map the voltage points on Vi(t) to Vc(t) to convert an input waveform Vi(t) of slew rate σ to the intermediate voltage waveform Vc(t) in one embodiment of the invention. In another embodiment of the invention, a lookup table is used to convert the waveform Vi(t) of slew rate σ to the intermediate voltage waveform Vc(t).

With the intermediate voltage waveform Vc(t), the output current waveform may be computed by using the intermediate voltage waveform Vc(t) as the dependent input of the current source model I0(Vc,V0). The model may use a table to store I0(Vc,V0), such as illustrated byFIG. 13, which is indexed by both Vcand V0. To compute output current at time tn given a particular Vcand V0at time tn−1, the model may first find the nearest voltages in the table and then perform a two-dimensional interpolation to approximate the actual output current at Vcand V0. The model may also look up Cggiven V0from another table, such as illustrated inFIG. 14. With the values of I0and Cgcomputed at time tn, we can compute the value of V0and move on to the next time point tn+1, at which we look up I0and Cgagain using Vcand V0at time tn. This process repeats until the whole output waveform is computed.

ViVo II Model Characterization

The ViVo II multi-CCC model for gates is characterized from a blackbox view of a standard circuit cell. To characterize a ViVo II multi-CCC model, the voltage and current waveforms at inputs and outputs of the standard cell are observed. Characterization starts at block1600and jumps to block1602.

At block1602, the output current I0is characterized for the driving stage of the multi-CCC current source model. The flow chart ofFIG. 17illustrates the characterization of the output current of the multi-CCC standard cell in greater detail.

Referring now toFIG. 17, at block1702, the output voltage V0is fixed to a known voltage, such as zero volts.

To characterize the driving stage I0(Vc,V0), transient simulations with a SPICE transistor circuit simulator, such as Spectre software by Cadence Design Systems, Inc. are used to switch the input to the standard cell with its output voltage V0being fixed.

At block1704, while holding the output voltage V0fixed, a spice transistor simulation is run on the multi-CCC standard cell.

At block1706, one input of the multi-CCC standard cell is switched using an input signal with an initial reference slew rate.

At block1708, the output current waveform is measured and the results are tabulated such as inFIG. 13.

At block1710, a determination is made as to whether or not the output voltage was set to the power supply voltage Vdd. If so, the process ends at block99. If not, the process goes to block1714.

At block1714, the output voltage is incremented to a new value and the process returns to block1704, to determine the output current for the new fixed value of output voltage Vo.

In the case of standard cells with only one CCC, performing a DC-analysis by sweeping Viand V0is sufficient to find I0(Vc,V0). However for a multi-CCC standard cell, I0(Vc, V0) a DC-analysis may not be used since the input voltage Vidoes not equal the intermediate voltage Vc.

FIG. 6Ashows three output current waveforms I0refwhich are obtained by applying an input ramp voltage Vi(t) with a reference slew rate σrefwith different settings of fixed output voltage V0. These curves are stored in the current table I0(Vc,V0) ofFIG. 13for current look-up.FIG. 6Afurther shows an output current waveform I0slowwhich is obtained by applying the input ramp voltage Vi(t) with a slow slew rate σslow.

At block1604, the voltage transform function Γ(V(t)) of the multi-CCC standard cell is characterized. The flow chart ofFIG. 18illustrates the characterization of the voltage transform function Γ(V(t)) of the multi-CCC standard cell in greater detail. Characterizing the functional Γ in Equation 1 requires extra simulations using different input slews than a reference slew rate σref.

At block1802ofFIG. 18, the input signal slew rate is set to a first slew rate that is different form the reference slew rate. For example, the input slew rate may be changed to a slow slew rate σslow.

At block1804, the output voltage V0of the multi-CCC current source model is fixed to ⅓ of Vdd for a rising output and ⅔ of Vdd for a falling output.

At block1806, with the output voltage fixed, SPICE transistor circuit simulations are run with the multi-CCC current source model.

At block1808, one input of the multi-CCC standard cell is switched using the input signal with the differing slew rate than the reference slew rate.

At block1810, the output current I0slowis measured and results may be tabulated.FIG. 6Aillustrates an I0slow(Vc,V0=x·Vdd) waveform which is obtained by changing in rate to σslow, where x is a fraction of ⅓ for rising output and ⅔ for falling output.

At block1812, the output current waveform is compared with the input signal waveform to determine the extra delay time in the transition periods to extract τslowand Tslowparameters, for example.

From I0slow(Vc,V0=x·Vdd) waveform curve we observe that the output current waveform incurs an extra delay of τslow−τrefand its transition period stretches from Trefto Tslowcompared to the original reference current waveform I0ref(Vc,V0=x·Vdd). Tslowand τsloware stored, in the table ofFIG. 11for example, for the input slew σslowas part of the parameter for characterizing the functional Γ. Moreover, we can capture the non-linear shape difference between I0ref(Vc,V0=x·Vdd) and I0slow(Vc,V0=x·Vdd) by normalizing the time-axis

At block1814, the output I0slow(Vc,V0=x·Vdd) waveform curve is normalized using τslowand Tslowparameters. The reference waveform curve I0ref(Vc,V0=x·Vdd) is normalized using its τREFand TREFparameters. The normalized output waveform curve and the normalized reference curve are aligned together and equal-current time points are recorded for each output current for their respective slew rates, such as illustrated byFIG. 15. The equi-current normalized time information further simplifies the computations and reduces the amount of information that need be stored to model a multi-CCC standard cell. The equi-current normalized time information is used to further transform the output waveform, be it an output current waveform I0or an output voltage waveform V0.

Referring now back toFIG. 18at block1816, a determination is made if all desired slew rates differing from the reference slew rated have been simulated. If so, the process goes to block99and ends. If not, the process goes to block1820.

At block1820, the input signal slew rate is set to the next slew rate differing from the reference slew rate. The process then returns to block1804where the characterization process is repeated.

FIG. 6Billustrates normalized current curves from which parameters to characterize Fσ(ν) may be extracted. This process may be repeated for a fast input slew σfastto more accurately characterize Γ.

The current table ofFIG. 13is characterized for at least one input voltage slew rate, a reference slew rate σ0or σref. In another embodiment of the invention, it is characterized for two slew rates, a fast slew rate σ1or σfast, and a slow slew rate σ2or σslow. In another embodiment of the invention, it is characterized for at least three slew rates, the reference slew rate σ0or σref, the fast slew rate σ1or σfast, and the slow slew rate σ2or σslow. The more characterization data, the better the interpolation accuracy with respect to input slew.

To adapt the characterized output currents to input voltage signals with different slew rates, the values in the current table are adjusted. With a multi-CCC standard cell, there are first and second order adjustments to be made. With a single-CCC standard cell, a first order adjustment for a different slew rate may only be made.

Referring now toFIG. 5B, a first-order-only-transformation (applying Γ to the first order) of the voltage input waveform Vi into an output current waveform Io is illustrated. A reference voltage input waveform510was previously used to generate the tabulated output current waveform515. A voltage input waveform512with a new slew rate (indicated by the slope) and a delayed start (indicated by the offset from time zero) is coupled into the single-CCC standard cell. The new voltage input waveform512results in a new output current waveform517. The output current waveform518is the result of a SPICE transistor circuit simulation for comparison with the output current waveform517of the multi-CCC model.

A first order output adjustment to the output current waveform is due to the change input slew rate illustrated by the slope of waveform511and the delayed start of the input illustrated by the time offset between waveforms511and512. The change in slope of the input waveform (illustrated by the difference between waveforms511and510) results in a change in slope in the output waveform as illustrated by the difference between output waveforms515and516. The delayed start in the input waveform (illustrated by the difference between waveforms512and511) results in a delayed start in the output waveform as illustrated by the difference between output waveforms517and516. The change in slope is established by a stretch parameter T. The change in start time is established by a shift parameter τ.

A second order output adjustment to the output current waveform is the result of the extra gate stages in a multi-CCC standard cell. The new voltage input waveform is coupled into a different gate than that of the last driving stage of a multi-CCC standard cell. The second order adjustment to the output current waveform is illustrated by the difference between output waveforms518and517. The second order output adjustment is modeled by a time transformation function Γ that is responsive to the new input slew rate. If the standard cell is a simple single-CCC standard cell, the time transformation function is u=ν, where ν is the normalized time with respect to the current table and u is the normalized simulation time. That is, there is no second order output adjustment to be made to a simple standard cell with a single-CCC. The first order output adjustment may be made to a simple standard cell with a single CCC.

Referring now toFIG. 5C, the characterization of a time transformation function Γ is now described. A voltage input waveforms Viand its respective output current I0over time are plotted in the left chart. Output current waveforms Io normalized for time are plotted in the right chart.

From the plots of voltage input waveforms Vi with different slew rates and their respective output current Io, the shift parameters τ and the stretch parameters T are first measured. The shift parameters τ and the stretch parameters T for each voltage input waveform and its respective slew rate may be tabulated, such as illustrated inFIG. 11.

The output current waveforms Io are aligned and normalized for time over U from zero to one, such as illustrated in the right chart ofFIG. 5C. Three output current waveforms Io530A-530C are illustrated in the right chart ofFIG. 5Cwith slew rates σ1, σ0, and σ2, respectively. A plurality of equi-current points Iiare selected and their normalized times U for all of the output current waveforms Io530A-530C with their respective slew rates are recorded into a table, such as the table illustrated inFIG. 15.

For example, consider the equi-current point Iiillustrated in the right chart ofFIG. 5Cthat intersects the waveforms530A-530C at points531A-531C, respectively. At point531A on waveform530A, the normalized time is Zi. At point531C on waveform530C, the normalized time is Yi. At point531B on waveform530B, the normalized time is Xi. These normalized time points are tabulated inFIG. 15.

As another example, consider the equi-current point Ii+1illustrated in the right chart ofFIG. 5Cthat intersects the waveforms530A-530C at points532A-532C, respectively. At point532A on waveform530A, the normalized time is Zi+1. At point532C on waveform530C, the normalized time is Yi+1. At point532B on waveform530B, the normalized time is Xi+1. These normalized time points are also tabulated inFIG. 15. Additional equi-current points are selected and their respective normalized times for each waveform and slew rate are tabulated.

The greater the number of equi-current points selected the better the accuracy of the model. Additionally the greater the number of output currents characterized for different input slew rates, the better the accuracy of the model.

Referring now toFIG. 5D, the equi-current values of the output current waveform with their respective slew rates can be inverted and normalized with respect to time in order to form time transformation curves551,552illustrated inFIG. 5D. That is,FIG. 5Dillustrates time versus time plots plotted fromFIG. 5C. Time transformation waveforms551,552with respective slew rates of σ1and σ2are illustrated inFIG. 5D.

With curves551and552, a new intermediate voltage waveform530with respect to a new slew rate σnewmay be readily interpolated by applying the second order adjustment. The interpolation is to construct an intermediate waveform for a multi-CCC standard cell to assist in output current look-up during simulation. The curves551and552ofFIG. 5Dmay be stored in a table, such as illustrated inFIG. 15, as piece-wise linear time versus time curves.

The characterized time transformation curves ofFIG. 5Dfor the slew rates σ1and σ2may be saved and used as part of the multi-CCC current source model. After determining a new slew rate of an input voltage waveform to a multi-CCC standard cell, the characterized time transformation curves551-552ofFIG. 5Dfor the slew rates σ1and σ2, respectively, may be utilized to interpolate a new time transformation curve550associated with the new slew rate σnewof the input voltage waveform.

At a normalized time of u1inFIG. 5D, curves551and552have normalized equi-current values of Y1and Z1, respectively. The new transformation curve550has an interpolated value of W1at a normalized time of X1. Equivalent ratios may be set up to interpolate all values of W along the curve530as follows:

for all values of normalized time u and each respective value of y and z. The equation may be solved for the value w along the curve530as follows:

Referring now to the left graph illustrated inFIG. 9, the input voltage waveform is then normalized by shifting the starting time point to zero at the origin and scaling the time axis so that the normalized input waveform V1900goes from the normalized time of zero to one.

Using the new time transformation curve550, new time points are generated from the new input voltage waveform900to begin its transformation into the intermediate voltage waveform Vc″901as illustrated by the right graph inFIG. 9.

The equation may be solved for the new shift parameter value τnewas follows:

The equation may be solved for the new stretch parameter value Tnewas follows:

Referring now toFIG. 10, the intermediate voltage waveform Vc″901is further transformed by the stretch parameter value Tnewby stretching it into the intermediate voltage waveform Vc′1001. The intermediate voltage waveform Vc′1001is finally transformed by the shift parameter value τnewby shifting it into the final intermediate voltage waveform Vc1002.

At block1606, the parasitic capacitance of the standard cell for the multi-CCC current source model is characterized. The flow chart ofFIG. 19illustrates the characterization of the parasitics of the standard cell in greater detail.

At block1902, all the inputs of the multi-CCC standard cell are set to a constant logic level input voltage. At block1904, a voltage source is coupled to the output of the multi-CCC standard cell. With the input voltage Vi being held constant, the intermediate voltage level Vc is also held constant.

At block1906, while holding the inputs to the multi-CCC standard cell fixed, a SPICE transistor circuit simulation is run of the transistors in the given multi-CCC standard cell.

At block1908, to characterize Cg(V0), the voltage source at output applies a voltage ramp with a slew rate σ0at the output of the multi-CCC standard cell.

At block1910, the current (Imeas) going through the voltage source at the output of the multi-CCC standard cell which asserts the voltage ramp is measured.

At block1912, the expected initial output current I0(V0(t=0),V0) may be looked up from a current table, such as the table illustrated inFIG. 13, given that we set the output voltage V0and we estimated the intermediate voltage Vc(t=0) at time zero.

At block1914, given the foregoing information, Cg(V0) can be computed by using Eq. 10 as follows:

where Imeasis the measured current and I0(V0(t=0),V0) is the initial output current that may be looked up from a current table.

At block1608inFIG. 16, the miller capacitance of the multi-CCC current source model may also be characterized.

Referring now toFIG. 20andFIG. 4C, a method of characterizing the miller capacitance (Cmilleror Cm) of the multi-CCC current source model is now described.

At block2002, all the inputs422but one input421of the multi-CCC standard cell420are set to a constant logic level input voltage. They may be set to a constant high logic level by coupling to the positive power supply voltage VDD or a constant low logic level by being coupled to ground VSS.

At block2004, a fixed voltage source Vfixedis coupled to the output of the multi-CCC standard cell420. The fixed voltage source Vfixedmay be fixed to a constant positive power supply voltage level (VDD) in one embodiment of the invention or a constant zero volts in another embodiment of the invention.

At block2006, while holding the output voltage of the multi-CCC standard cell fixed to the fixed voltage source Vfixed, a SPICE transistor circuit simulation is run of the transistors in the given multi-CCC standard cell.

At block2008, to characterize the miller capacitance Cm, a voltage source applies a voltage ramp with a fast slew rate σfastat the input421to the multi-CCC standard cell420. The slew rate of the voltage ramp should be as fast as possible for best results.

At block2010, the output current (Iout) going through the fixed voltage source is measured and plotted over time in response to the voltage ramp at the input421of the multi-CCC standard cell.

At block2012, the miller current Imilleror Imis determined and a time delay S in the change of the output current is also determined from the plotted output current. The time delay S is used as the change in the time period for the voltage decay over the miller capacitor.

Referring now toFIGS. 22A-22C, plots of exemplary waveforms for the input voltage ramp Vi, intermediate voltage Vc, and the output current Ioutare illustrated in the case that the fixed voltage source is set to the positive power supply voltage VDD.FIGS. 23A-23Cillustrate plots of exemplary waveforms for the input voltage ramp Vi, intermediate voltage Vc, and the output current Ioutin the case that the fixed voltage source is set to the zero volts.

In either case, the miller current is a current that results because the miller capacitor resists an instantaneous change in voltage. The miller current flows from the input to the driver stage of the multi-CCC current source model through the miller capacitor to the output node Vo. The miller current is the instantaneous change in current illustrated inFIGS. 22C and 23Cas a result in the initial change in the intermediate voltage Vc inFIGS. 22B and 23B. The driver stage of multi-CCC current source model has yet to turn on and provide a current. Thus, the measured output current is the miller current prior to the driver stage turning on and driving a current into the output node.

The current through a capacitor is known to be proportional to the product of the capacitance and a time derivative of the voltage. The latter can be approximated by a change in voltage divided by a change in time:

Rearranging Eq. 11 to solve for the miller capacitance we get:

At block2014, the change in voltage over time in the miller capacitor is estimated using the time delay S. That is, dV/dt is congruent to the positive power supply voltage VDD divided by the time delay S or VDD/S.

At block2016, the miller capacitance is calculated using Eq. 12 and the measured miller current Im through the miller capacitor Cm and the change in voltage over time VDD/S across the miller capacitance. After the miller capacitance is determined for the given multi-CCC standard cell, it is stored with the other parameters of the multi-CCC current source model.

After the miller capacitance is determined, the characterization of the miller capacitance ends at block2099.

Generally, the multi-CCC current source model is efficient in the runtime that is required to characterize the model, as well as the amount of data storage need to preserve its parameters. The multi-CCC current source model can achieve sufficient accuracy by keeping seven V0values and twenty time samples of

Ioref⁡(Vc⁡(t),Vo)
for each V0in the I0(Vc,V0) table ofFIG. 13. Cg(V0) may require only seven V0values in its table ofFIG. 14. It is also sufficient to store values of Tσ,τσand F0(ν) for three different input slew rates, a reference input slew σref, a slow input slew σslow, and a fast input slew σfastthat may be stored in tables, such as tables illustrated inFIGS. 11 and 12. Characterizing these parameters may take about ten transistor circuit simulations using a transistor circuit simulator, such as Cadence Design Systems, Inc.'s Spectre transistor circuit simulator, compared to about eighty transistor circuit simulations that may be required for other gate models.

Delay Calculation for Application Specific Ic Design

The embodiments of the invention may be used with or in a static timing analyzer for analyzing the timing of an integrated circuit.

Referring now toFIG. 21andFIGS. 1C-1D, a timing analysis of the circuit netlist ofFIG. 1Dmay be made starting at block2100inFIG. 21which jumps to block2102.

At block2102, a register-transfer-level netlist is analyzed to partition a circuit into stages. The stages are further levelized to perform static timing analysis. Each stage may include one or more standard cells and associated interconnect.

At block2104in each stage, one or more standard cells are modeled using a multi-CCC current source model. If a standard cell is a single-CCC standard cell, the multi-CCC current source model may still be used with the voltage transform function having a unity value of one such that the intermediate voltage is the input voltage.

At block2106in each stage, the coupled RC interconnect network may be generated from a parasitic extraction after a circuit is laid out or the parasitics may be generated in response to the netlist after logic synthesis and possibly a floor plan of the functional blocks of the circuit, if available. The parasitics of the coupled RC interconnect network in each stage are modeled using a reduced order model (ROM).

At block2108, a determination is made as to whether or not the system is in a concurrent calculation mode. A concurrent calculation mode includes a noise or signal integrity analysis as part of the multi-CCC current source model. If not, the process goes to block2110. If so, the process goes to block2112.

At block2110, the delay in each stage is computed using the modeled current of the multi-CCC current source model and the modeled parasitics of the reduced order model (ROM). The process then goes to block2120.

At block2112for each stage, assuming concurrent calculation mode, the response on the output of each stage due to each noise aggressor transition is computed and tabulated. The process may then go to block2114.

At block2114for each stage, the combined response on the output of each stage in response to all noise aggressor transitions may be computed and tabulated.

Next at block2116, for each stage, the delays and the sensitivities to all noise aggressors and process variations are computed via simulation using the multi-CCC current source model and the reduced-order model (ROM) for the associated RC interconnect. The receiving gates in each stage are modeled using constant capacitors. The process then goes to block2120.

At block2120, the calculated delays of each stage are used by a static timing analysis tool to determine the critical delay paths. The process goes to block2199and ends.

Stage Delay Calculation Under Process Variations

The multi-CCC current source model may be used to perform timing delay calculations on a stage of a circuit in the presence of process variations. Process variations can effect the interconnect as well as the transistors used in the logic cells of a standard cell library. For example, a metallization process is used to manufacture the interconnect within an integrated circuit. During the metallization process, the sheet resistance may vary in the metal as well as the width and thickness of metal lines due to process variations and change the impedance.

Referring now toFIG. 24, a circuit stage2400is illustrated including a driver2401connected to a plurality of receivers2402A-2402N through an interconnecting net2403. The stage2400is modeled by a circuit consisting of the net's parasitics and its driver2401and receivers2402A-2402N. For the sake of simplicity, a net is assumed to have a single driver as shown. However, the methods may be adopted with modification for the general case of multiple driving stages.

For calculation of STA delays at the driver output X12420and receiver inputs Y1-YN2422A-2422N, the transition at the driver input is required. Correspondently, the delay calculator computes voltage responses at the so-called probing points Yd, Y1-YN (2420,2422A-2422N in FIG.24)—nodes which are connected to output of the driving gate and inputs of receiving gates, respectively.

For calculation of the responses at the probing points Yd,Y1-YN2400,2422A-2422N, a state-space formulation is used. A vector of voltages V (v1, . . . , vN+1) is formed at nodes of the RC network in the stage2400. The vector V of voltages may be formed so that v1denotes vd—a voltage on the output node from the driver2401as shown inFIG. 24, and v2, . . . , vN+1denote respectively voltages at input nodes of the receiving gates—Vr1, . . . , VrN.

To enable an efficient and accurate delay calculation the nonlinear parts of the stage are approximated using appropriate models. The driver2401is modeled with the multi-CCC current source model described previously. The driver2401includes a voltage controlled current source2412and a capacitance Cg2414.

Calculation of responses at the stage's probing points is performed after responses are computed at the previous stages and parameters of input transitions, such as slews and delays, are determined at the inputs of the stage being analyzed.

During calculation of responses, it is assumed that voltage at one of the inputs of the driving gate is transitioning (either rising or falling) and this causes some transition at the nodes of the driven interconnect. We can assume that for each input pin of the driving gate, direction of transition at the input and output pins and logical values at other input pin, there exists a unique current source model describing current at the output pin as a function of voltage transitions at the switching input and output pins: I=Idrv(vin(t),vout(t)). However, since transition at the inputs of the driving gate are known at the time of delay calculation at the stage, the driver current source can be represented as a function of time and voltage at the output node of the driving gate: I=Idrv(t,vout(t)).

For a given switching input pin, directions of transitions at the input and the output of the driving gate and logical values at the other inputs, the current drawn by the driver is thus a known function of time t and voltage v1and may be designated as Idrv(t,v1).

Each of the receivers or receiving gates2402A-240@N may be modeled using a constant input capacitor Cin2416extracted from a standard cell library for the respective type of cell or gate.

Kirchhoff's current law (KCL) equations regarding the principle of conservation of electric charge, may be applied to describe the stage2400as follows:

In the left-hand side of Eq. 13, C is a capacitance matrix,

G is a conductance matrix, and v is the voltage vector. The vector y={v1,v2, . . . , vM+1} denotes voltages at the probing points which include output of the driver and inputs to the receiving gates of the M receivers2402A-2402N as shown inFIG. 24.

In the right-hand side of Eq. 13,14, the matrices B and L are respectively input and output position matrices, and Idrvis the current drawn by the driver current source.

The input capacitors modeling the receiver gates2402A-240@N may be added into the capacitance matrix C.

The set of equations (13,14) is sufficient to calculate responses at the probing points, which may be achieved via simulation of the circuit using numerical integration of the governing equations (13,14). Note that the current source model for the driver is different for different input switching pins, input and output direction transition and values at side (other) inputs. That is, for each such configuration of the driver, a separate simulation is required.

Since RC interconnect may include hundreds or even thousands of resistors and capacitors, it is usually expensive to integrate Eqs. (13,14) with highly sparse matrices G,C. In order to make simulation more efficient a model-order reduction (MOR) may be performed to generate a load model (a reduced order model ROM) of the RC interconnect. Model-order reduction is generally described in U.S. Patent Application Publication No. 2006/0095236A for U.S. patent application Ser. No. 10/932,406 filed on Sep. 2, 2004 by Joel R. Phillips and incorporated herein by reference. The model-order reduction results in much more compact state-space equations with very little loss of accuracy. The reduction produces a reduced-order model (ROM) for the interconnect parasitics, which also includes receiver pin capacitors. After the reduced-order model (ROM) for the interconnect parasitics is generated, the state-space equations can be formulated in this conventional form:

Note that matrix C in Eq. (16) is unrelated to the capacitance matrix used in Eq. (13). The vector x is the state vector, which usually has much smaller dimension that original vector of node voltages. Vector y is the vector of probing points as before, and u in the right-hand side of Eq. (15) is the driver current Idrv. The input to the ROM, which is the node where driver is connected to, and the outputs, which are nodes where receiving gates are connected to, are often referred to as port and taps, respectively. Matrices E,A are of much smaller size than before reduction.

Generally, both linear and nonlinear elements of a circuit are functions of process parameters. Let a vector λ={λn} with n=1, . . . , P denote a vector of interconnect and cell process parameters. It is assumed that the capacitance and the conductance matrices of the original state-space system C(λ), G(λ) and driver current source Idrv(t, v, λ) are known functions of process parameters. Likewise, the state-space matrices of the reduced system A,E are also functions of process parameters. Moreover, the capacitance matrix C(λ), the conductance matrix G(λ), the driver current source Idrv(t, v, λ), of the original stage-space system and the state-space matrices A,E of the reduced state-space system can also be modeled so that the effects of variation of temperature and variation in power supply voltage Vdd can be accounted for.

For a fixed vector of process parameters λ the port and tap responses can be determined by solving both of the equations (5,6). This may be done for instance using trapezoidal integration method. Since excitation u is a nonlinear function of the port voltage, Newton-Raphson iterations are used at each time step. This means that the responses and correspondent delays are implicitly functions of process parameters.

The delay calculation problem of the stage2400may be formulated as a problem of finding the port and tap responses y and the correspondent delays and slews as functions of vector λ. Some delay characteristics are of particular interest in the presence of process variations. The timing delay of the stage (the “stage delay”) is of interest at a particular point of the subspace of process parameters, referred to as a process parameter vector (PPV). The maximum (and minimum) values of the stage delay within a certain range (subspace) of process parameters may be of interest. Moreover, the sensitivity of the stage delay with respect to process parameters at a particular process parameter vector may be of interest.

In the presence of large variations in process parameters, one approach to model the stage delay is to choose a representative set of process parameter vectors, often referred to as set of process corners, and perform a delay calculation at each process corner. The selection of the corners is usually done in such a way as to cover the feasible space of process variations and ensure that the maximum and/or minimum timing delays are reached at least one of the chosen corners. However with a large number of process parameters, the number of corners to ensure a conservative analysis may be too high for the process corner approach of analyzing timing delays to be practical.

However, all or several of the process parameters may vary within a relatively small range. In this case, an efficient technique to model the timing delay with process variations is as a linear function of the process parameters. This approach is based on a sensitivity analysis. The sensitivity of delay is defined as a derivative of the timing delay with respect to a varying parameter. Since the behavior of timing delay in a sufficiently small vicinity of a chosen process parameter vector is linear with respect to the process parameters, knowing the delay and its sensitivities at a process parameter vector provides a good model for the delay in the vicinity of the process parameter vector.

Calculation of Delay, Slew and their Sensitivities to Process Variations

An algorithm for the calculation of the stage delay and delay sensitivity at a given process parameter vector is now described with reference toFIG. 24.

A state-space system for the voltage responses at the output port2420of the driver2401and receiver inputs2422A-2422N of the receivers2402A-2402N in the presence of process variations may be written as

Since both matrices and excitation vector depend on process parameter vector λ, the solution must depend on λ as well.

In order to find sensitivity of the stage delay with respect to process parameters at a given process parameter vector, the state-space system as well as responses are expanded in Taylor series around some nominal value of the process parameter vector λ=λnom.

Assuming that small variations of process parameters around their nominal values cause the variation of responses to be also small, the circuit responses in the vicinity of the nominal vector of process parameters can be sought in the form of a Taylor series with respect to the deviation of the process parameter vector from its nominal value: σ=λ−λnom:

In equations 19-22, the zero-order terms A(0), E(0), u(0), x(0), correspond to nominal matrices excitation and states which are taken at λ=λnom. In this approach which uses Z-formulation, the matrices B and C do not depend on process parameters and therefore do not need to be expanded. The first-order terms are summations of a product of the deviation δnof process parameter λnfrom its nominal value and the sensitivity (or partial derivative) of the correspondent function with respect to this process parameter, e.g.

At zero order we have the following problem:

Before formulating the first-order problem allowing sensitivity calculations, notice that since u=Idrv(t,v1(λ),λ) depends on process parameters via two latter arguments, the sensitivity with respect to (w.r.t.) λnis

In Equation 25, g(t) is the small-signal admittance of the current at the nominal voltage response:

The two components in the first-order correction of driver current are due, respectively, to variation of the gate driving strength itself, and due to change in driver output response.

At the first order we obtain a set of linear problems, one for each process parameter as follows:

In equation 27, y1,n(1), is first element of vector yn(1), which is the sensitivity of driver output response w.r.t. parameter λnand it can be expressed via xn(1)using Eq. (28).

Equations 27,28 are linear with respect to sensitivity values. All quantities in the right-hand side of equations 27,28 are known since they depend on the nominal response which is found from equations 23,24. The sensitivities can be calculated from equations 27,28 using different numerical methods for solving a set of linear ordinary differential equations. For instance, a trapezoidal numerical integration method can be used to calculate the sensitivities using equations 27,28.

In another embodiment of the invention, the total delay under nominal conditions may initially be computed. The non-linear circuit equations for the stage including current source model for the driver Idrvand ROM for interconnect may be formulated in their parameterized form with respect to the process parameter vectors. The port and tap responses as well as the equations and the driver current equations may be expanded around the nominal values of process parameter. The sensitivities of the responses and hence delays to process variations may be determined from a set of linear equations (27,28) obtained by the application of a perturbation method to original equations (17,18).

Results

Digital electrical analysis engines are usually compared against a SPICE-like transistor level circuit simulator, such as Cadence Design Systems, Inc. Spectre transistor level circuit simulator product. A number of tests have been performed to validate the accuracy of the multi-CCC current source model. A comparison was made on a stage by stage basis. The basic structure of all netlists is a three-stage gate chain. The test-suite has thousands of combinations of input slews, drivers, interconnect topologies, lengths and sizes. To validate nominal delay, noise coupling capacitors of the interconnect, if any, are coupled to ground. Each of the cells in the standard cell library, such as a commercial 90 nm technology cell library, is completely characterized for the multi-CCC current source model beforehand. The library models for the electrical simulation engine may also be fine tuned to achieve greater accuracy.

Referring now toFIG. 7, voltage waveform results of a static timing analysis using the digital delay calculator with a multi-CCC current source model and transistor level simulations generated by Cadence Design System, Inc.'s Spectre transistor level simulator are plotted for comparison.

The test case used to generate the plots ofFIG. 7was three stages of AND gates coupled in series together with an interconnect network with a maximum span of 200 microns (μm). An AND gate is a multi-CCC standard cell with its driver stage being an inverter. The ramp input voltage waveform V1(t)701coupled to the input of the multi-CCC standard cell in the first stage had a slew rate of 100 pico-seconds (ps). The other curves plotted inFIG. 7are pairs of curves both generated at the following stages: input voltage Vi(t)702at stage2, input voltage Vi(t)703at stage3, and output voltage Vout(t)704at the output port of stage3. The calculated results from the static timing analysis using the digital delay calculator and the simulated results of the transistor level simulator are substantially similar such that the pairs of curves are indistinguishable from each other at each stage.

Referring now toFIG. 8, a plot of timing delays calculated with the delay calculator (EOS) versus those simulated with a spice transistor level simulator, such as Spectre simulator by Cadence Design Systems, Inc., is illustrated. A forty-five degree line illustrating a perfect match is also drawn to see how well the static timing results match that of the transistor level simulated results. As shown inFIG. 8, the timing delay determined using delay calculator (EOS) with a multi-CCC current source model substantially matches the timing delay simulated by the Spectre transistor level simulator in most cases.

While the output results of the static timing analysis may be substantially similar, there may be other cases where a lesser level of accuracy may be acceptable. Depending on the usage scenario, different applications may need different levels of accuracy. For example, during cell placement, we may want to perform delay calculations using lookup models without considering any signal integrity issue. However during sign-off of a integrated circuit design for manufacture, it may be desirable to calculate the timing delays with noise effects using the fully extracted parasitics. For some critical paths, the most accurate delay calculations may be desirable with results substantially similar to that achieved using a SPICE transistor level simulation. The software infrastructure of static timing analyzer EOS with the multi-CCC current source model can support such different usage scenarios.

Conclusion

When implemented in software, the elements of the embodiments of the invention are essentially the code segments to perform the necessary tasks. The program or code segments can be stored in a processor readable medium or transmitted by a computer data signal embodied in a carrier wave over a transmission medium or communication link. The “processor readable medium” may include any medium that can store or transfer information. Examples of the processor readable medium include an electronic circuit, a semiconductor memory device, a read only memory (ROM), a flash memory, an erasable programmable read only memory (EPROM), a floppy diskette, a CD-ROM, an optical disk, and a magnetic disk. The program or code segments may be downloaded via computer networks such as the Internet, Intranet, etc.

The embodiments of the invention are thus described. While embodiments of the invention have been particularly described, they should not be construed as limited by such embodiments. For example, the delay calculator's primary use is as a common timing computing engine to perform static timing analysis. However, its software infrastructure allows it to be portable and used with different design databases, timing library environments, and ECAD design tools. Instead, the embodiments of the invention should be construed according to the claims that follow below.