Three-dimensional integrated circuit integration

Wiring structures, methods for providing a wiring structure, and methods for distributing currents with a wiring structure from one or more through-substrate vias to multiple bumps. A first current is directed from a first through-substrate via of a first electrical resistance through a first connection line to a first bump and directing a second current from the first through-substrate via through a second connection line of a second electrical resistance to a second bump. The first connection line has a first length relative to a first position of the first bump and a first cross-sectional area, the second connection line has a second length relative to a first position of the second bump and a second cross-sectional area, the second length is different from the first length, and the second cross-sectional area is different from the first cross-sectional area.

BACKGROUND

The invention generally relates to semiconductor manufacturing and, more particularly, to wiring structures, methods for providing a wiring structure, and methods for distributing currents with a wiring structure from one or more through-substrate vias to multiple bumps.

Stacked chips may be used to increase the function that can be provided by a single package. The constituent chips of the chip stack are arranged in a compact three-dimensional stack characterized by multiple levels. The functionality of a chip stack requires functionality of each individual chip. The stacked arrangement of the three-dimensional integration conserves space and shortens signal transmission distances for inter-chip communications, which may improve both efficiency and performance of the chip stack. During manufacture, each chip is processed independently to form integrated circuits. The different chips are subsequently stacked in a three-dimensional arrangement and bonded so that the chips are vertically arranged with permanent attachment to each other.

Signals and power must be transmitted to all silicon chips in the chip stack. One approach is to provide a conductor that penetrates from one side of a chip or interposer to the opposite side of the chip or interposer. Such conductors are often called through-substrate vias (TSVs). One way of stacking the chips is by using solder bumps between the chips, which are used in conjunction with the TSVs to distribute power and signals.

Improved wiring structures, methods for providing a wiring structure, and methods for distributing currents with a wiring structure from one or more through-substrate vias to multiple bumps are needed.

SUMMARY

In an embodiment of the invention, a method includes directing a first current from a first through-substrate via through a first connection line to a first bump and directing a second current from the first through-substrate via through a second connection line to a second bump. The first connection line has a first length relative to a first position of the first bump and a first cross-sectional area, the second connection line has a second length relative to a first position of the second bump and a second cross-sectional area, the second length is different from the first length, and the second cross-sectional area is different from the first cross-sectional area.

In an embodiment of the invention, a structure comprising a first bump, a second bump, a first through-substrate via, and wiring including a first connection line coupling the first through-substrate via with the first bump and a second connection line coupling the first through-substrate via with the second bump. The first connection line has a first length relative to a first position of the first bump and a first cross-sectional area. The second connection line has a second length relative to a second position of the second bump and a second cross-sectional area different from the first cross-sectional area.

In an embodiment of the invention, a method is provided for providing a wiring structure coupled with a through-substrate via. The method includes receiving, at a processor, a first current and a first length for a first connection line coupling the through-substrate via with a first bump, and receiving, at the processor, a second current and a second length for a second connection line coupling the through-substrate via with a second bump. The processor determines a first cross-sectional area for the first connection line based upon the first current and the first length such that the first connection line has a first electrical resistance. The processor determines a second cross-sectional area for the second connection line based upon the second current and the second length such that the second connection line has a second electrical resistance.

DETAILED DESCRIPTION

With reference toFIG. 1and in accordance with an embodiment of the invention, an assembly10includes a chip12, an interposer14, and a laminate substrate16that are united to form the assembly10. The chip12may comprise a single chip, as in the representative embodiment, or a chip stack comprising a plurality of chips arranged in a stack. The chip12may include an FEOL side12aon which integrated circuits have fabricated with a front-end-of-line (FEOL) process, such as a complementary metal-oxide-semiconductor (CMOS) process. In one embodiment, the chip12may be a custom logic or processor chip, and the interposer14may function to spread the electrical connections to a wider pitch than for the chip12and/or reroute electrical connections. The interposer14may also provide interconnections between devices or provide ancillary functions such as providing capacitance or inductance.

The chip12may include a substrate17used to form integrated circuits and an interconnect structure18fabricated with middle-end-of-line and back-end-of-line processes. The interconnect structure18is configured to communicate signals to and from the integrated circuits of the chip12and to also provide power and ground connections for the integrated circuits of the chip12. On FEOL side12a, the interconnect structure18of the chip12may include one or more dielectric layers20, metallization22in the one or more dielectric layers20, and bond pads24that are coupled with the metallization22. The bond pads24are accessible at the FEOL side12aof chip12for establishing electrical connections with the interposer14.

The interposer14may include a substrate26that is comprised of a semiconductor material (e.g., silicon) or, alternatively, that is comprised of a different type of material, such as glass or sapphire. If the substrate26is comprised of semiconductor material, then integrated circuits may be fabricated using the substrate26.

The interposer14further includes conductive features in the form of through-substrate vias (TSVs)28that extend through the entire thickness of the thickness, t, of the substrate26. The TSVs28may be fabricated by deep reactive ion etching or laser drilling a deep via into the substrate26, electrically insulating the deep via with a dielectric material, lining the via with a conductive liner that is a diffusion barrier and/or adhesion promoter, and filling the via with a conductor such as a metal (e.g., copper). After the vias are filled, the substrate26may be thinned from its back side by grinding and/or a wet or dry etch to reduce its original thickness and thereby expose the opposite end of each TSV28at the depth of the vias. The thinning defines a grind side14bof the interposer14. The interposer14may be functionalized with passive and active circuit elements on a FEOL side14a, which is separated by the thickness, t, of the substrate26from the grind side14b. The TSVs28provide continuous conductive paths between the FEOL side14aand the grind side14bfor signals, power, and/or ground.

The FEOL side14aof the interposer14may comprise an interconnect structure30fabricated with middle-end-of-line and back-end-of-line processes. The FEOL side14aof the interposer14may face the laminate substrate16. On FEOL side14a, the interposer14may include bond pads36and wiring50that are coupled with the TSVs28. The interposer14also includes bond pads38on its grind side14b, which are coupled by the TSVs28with the bond pads36on its FEOL side14a. The bond pads38are also coupled by the solder bumps40, which may be reflowed C4 (Controlled Collapse Chip Connections) solder balls or other types of solder balls or bumps, with the bond pads24at the FEOL side12aof chip12. The chip12and interposer14are joined in a face-to-face fashion by the solder bumps40with the solder bumps40located between the chip12and interposer14.

The grind side14bof the interposer14may face the FEOL side12aof the chip12. The laminate substrate16may include metallization42that defines a power plane that is used to supply power to the chip12via the interposer14. Solder bumps44, which may be reflowed C4 solder balls or other types of solder balls or bumps, couple the bond pads36at the FEOL side14aof interposer14with the metallization42. The laminate substrate16may be coupled by reflowed solder bumps46with a printed circuit board, which may provide the physical structure for mounting and supporting the assembly10, as well as providing electrical interconnections with other electronic components populating the printed circuit board and coupled with the printed circuit board. Specifically, the assembly10may be integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any end product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.

In the representative embodiment, the FEOL side14aof the interposer14faces the laminate substrate16and the grind side14bof the interposer14faces the FEOL side12aof the chip12. Alternatively, the interposer14may be oriented such that its grind side14bfaces the laminate substrate16and its FEOL side14afaces the FEOL side12aof the chip12. The specific orientation of the interposer14may depend on the build approach that is used to form the assembly10.

With reference toFIG. 2and continued reference toFIG. 1, the wiring50of the interposer14may comprise a redistribution layer on its grind side14a. The wiring50may be coupled with one or more TSVs28and thereby distribute power, ground, or signals from one or more TSVs28to multiple solder bumps40. In particular, the wiring50may be used to distribute current from the one or more TSVs28, when powered, to multiple solder bumps40. The solder bumps40and wiring50are arranged in a configuration that may enable an increased number of solder bumps40to feed current to the TSV28or to receive current from the TSV28by configuring the widths of the connection lines to ensure that the current flowing to/from each solder bump40from the TSV28is equal.

The wiring50on the grind side14bof the interposer14includes the bond pads38, a section52overlying one of the TSVs28, a plurality of connection lines54, and a plurality of connection lines56. Each of the connection lines54,56originates at the section52and terminates at its opposite end at one of the bond pads38. In the representative embodiment, only a single TSV28is associated with the section52of wiring50. One of the solder bumps40is associated with each of the bond pads38, and the bond pads38and solder bumps40are linearly arranged in a row58adjacent to the TSV28.

The bond pads38and solder bumps40are located adjacent to the TSV28, and the connection lines54,56extend toward the TSV28and section52. The connection lines54,56thereby couple the TSV28, which is located at the shared origin at the opposite end of the connection lines54,56, with the bond pads38and solder bumps40. In this manner, the wiring50promotes the sharing of the TSV28and the distribution of its current among the different bond pads38and solder bumps40.

The wiring50may be formed from a layer of a conductor, which is deposited, masked, and etched to define the connection lines54,56and section52. To that end, the layer of conductor may be deposited and a mask layer may be applied to its top surface. The conductor constituting the connection lines54,56is characterized by an electrical resistivity (i.e., ρ) that may be measured in ohm-meters (Ω·m). In an embodiment, the conductor may be a metal having an electrical resistivity of less that 10−7Ω·m. In another embodiment, the conductor may be copper characterized by an electrical resistivity of 1.72×10−8Ωm. The mask layer may comprise, for example, a photoresist that is applied with a spin coating process, pre-baked, exposed to a radiation projected through a photomask, baked after exposure, and developed with a chemical developer to define a pattern with lines of photoresist covering the intended positions of the connection lines54,56. An etching process may be used to define the connection lines54,56from the conductor layer. The etching process may comprise a wet chemical etch or a dry etch, and may rely on a given etch chemistry. After the connection lines54,56are defined, the mask layer may be removed by oxygen plasma ashing or wet chemical stripping, and a conventional cleaning process may be applied to remove any contaminants.

The respective lengths of the connection lines54,56may be adjusted relative to the locations of multiple solder bumps40adjacent to the TSV28so that the TSV28can be coupled with these adjacent solder bumps40. In the representative embodiment, the connection lines54are longer than connection lines56. Specifically, the connection lines54have a length, l1, between its opposite ends that is greater than a length, l2, of the connection lines56. The ends and lengths of each of the connection lines54,56may extend from the intersection with the respective bond pad38(and associated solder bump40) to the intersection with the section52of wiring50. The section52is shared by the connection lines54,56and may contribute the same amount of electrical resistance to each of the connection lines54,56. Similarly, each of the connection lines54,56includes a bond pad38, which may also contribute the same amount of electrical resistance to each of the connection lines54,56.

In the representative embodiment, the connection lines54,56are linear. In an alternative embodiment, one or both of the different types of the connection lines54,56may alternatively include a plurality of joined segments that collectively define the respective lengths and that are piecewise joined together in a linked chain with angled intersections between the different segments. In an alternative embodiment, the layout of the connection lines54,56may be influenced by the position of the TSV28relative to the row58of solder bumps40such that the individual connection lines54and/or the individual connection lines56may have different lengths.

The cross-sectional area of the connection lines54may systematically differ from the cross-sectional area of the connection lines56. In one embodiment, the width, w1, of the connection lines54may differ from the width, w2, of the connection lines56. The selection of the respective cross-sectional areas or widths is utilized as a factor to systematically control the resistance of the connection lines54,56.

The cross-sectional area of each of the connection lines54,56in a plane normal to the respective longitudinal axis is given by the product of the width and thickness. In an embodiment, the connection lines54,56may have uniform thicknesses, and the cross-sectional area of the respective connection lines54,56may not vary along their respective lengths so that the cross-sectional area is constant along the length. In another embodiment, the connection lines54,56may have uniform thicknesses, and the widths of the respective connection lines54,56may not vary along their respective lengths so that the width is constant along the length. Each of the connection lines54,56may then constitute a conductor of uniform cross-sectional area along its length for which the electrical resistance can be determined from the product of the electrical resistivity and a ratio of the respective length to the respective cross-sectional area. However, the connection lines54and/or the connection lines56may include lengthwise variations in the cross-sectional area and/or width in which the segments of different cross-sectional area and/or width are taken into consideration by the determination of electrical resistance.

In an embodiment, the respective cross-sectional areas of the connection lines54,56may be selected such that the electrical resistance of each of the connection lines54is equal to the electrical resistance of each of the connection lines56. To that end and in an embodiment, the width, w1, of the connection lines54may be selected to be greater than the width, w2, of the connection lines56in order to compensate for the longer length, l1, of the connection lines54relative to the length, l2, of the connection lines56when determining the electrical resistance. The connection lines54of longer length and greater width are coupled with bond pads38and solder bumps40that are more distant from the TSV28than those coupled with the connection lines56of shorter length and lesser width. Due to the inverse dependence of electrical resistance on cross-sectional area and on width for a uniform thickness, the reduced width of the connection lines56relative to connection lines54permits the electrical resistances to be equalized among the connection lines54,56.

According to Ohm's law and when powered by virtue of the equal electrical resistances, the current flowing through connection lines54from the TSV28to their terminating bond pads38and associated solder bumps40may be the same as the current flowing through connection lines56from the TSV28to their terminating bond pads38and associated solder bumps40so that the current is evenly distributed. The balancing of the currents delivered to the different solder bumps40assumes that the load on the respective solder bumps40is uniform. If the loads are different, then the currents may differ and/or the different loads may be taken into account when determining the line widths.

The current-carrying capacity of the TSV28may be greater than the individual current-carrying capacity of each solder bump40. The wiring50may increase the ability to distribute power from the TSV28to multiple nearby solder bumps40so that the full current-carrying capacity of the TSV28can be realized and the current-carrying capacity of the TSV28is less constrained by the lower current-carrying capacity of the solder bumps40. The wiring50may also relax size constraints on the number of solder bumps40that can be nearest neighbors of the TSV28. The adjustments to the cross-sectional areas of the connection lines54,56can be used to ensure that solder bumps40closer to the TSV28do not draw higher current than the solder bumps further from the TSV. The adjustments to the cross-sectional areas of the connection lines54,56can be adapted to reflect different numbers of solder bumps40of different sizes and/or current-carrying capacity.

Alternatively, the selected cross-sectional areas of the connection lines54,56may be used to meter the current supplied to the bond pads38and solder bumps40so that the supplied currents are unequal. For example, the cross-sectional area and/or width, w1, of the connection lines54may be selected to be greater than the cross-sectional area and/or width, w2, of the connection lines56, but may be selected to under-compensate for the greater length, l1, of the connection lines54relative to the shorter length, l2, of the connection lines56in the determination of the electrical resistance. In this instance, the connection lines54may have a higher electrical resistance than the connection lines56. Under Ohm's law and when powered, a smaller current may flow from the TSV28to the bond pads38and solder bumps40fed by the connection lines54than those solder bumps40fed by the connection lines56. In this embodiment characterized by different electrical resistances, the cross-sectional area of the connection lines54may be selected to be less than the cross-sectional area of the connection lines56and/or the cross-sectional area of connection lines may be selected such that the electrical resistance of connection lines54is less than connection lines56.

In an alternative embodiment, the chip12may be connected with an adjacent chip to form a chip stack and may include through-substrate vias (TSVs) similar to TSVs28. The adjacent chip may be similar to the chip12or different from chip12in terms of function. For example, the adjacent chip may be a memory chip if chip12is a custom processor chip. Such stacked chip arrangements may exhibit improved performance, bandwidth, and/or functionality compared with non-stacked-arrangements. For example, a stacked chip arrangement improve electrical performance due to the short interconnects and high number of TSV interconnections between stacked chips. As another example, a stacked chip arrangement may permit the heterogeneous integration of logic, memory, graphics, power and sensor ICs that cannot otherwise be integrated into a single chip. Chip12and/or the adjacent chip to chip12may include wiring similar to the wiring50that is used with width adjustments in the connection lines to adjust the current supplied to from the TSVs to the solder bumps connecting the chip12with the adjacent chip in the chip stack. In an alternative embodiment, wiring similar to wiring50may be used to adjust the current supplied from the laminate substrate16to the bond pads36and solder bumps44on the FEOL side14aof the interposer14with the metallization42.

With reference toFIG. 3in which like reference numerals refer to like features inFIG. 2and in accordance with an alternative embodiment of the invention, the wiring50may further include additional connection lines64analogous to connection lines54and additional connection lines66analogous to connection lines56each terminating at one end with one of the bond pads38on the grind side14bof the interposer14. The bond pads38and the solder bumps40associated with the bond pads38are linearly arranged in a row62. The TSV28is positioned between row58and row62such that the TSV28feeds current to the bond pads38and the solder bumps40in each of the rows58,62. The addition of the connection lines64,66to connection lines54,56promotes connections with multiple parallel rows58,62of bond pads38and solder bumps40.

The respective cross-sectional areas of the connection lines64,66may be selected as discussed above with respect to connection lines54,56and in coordination with the selection of the respective widths of the connection lines54,56. In one embodiment, the lengths and widths of the connection lines64,66may be the same as the lengths l1, l2and widths w1, w2of the connection lines54,56. Alternatively, the lengths and/or widths of the connection lines64,66may differ from the lengths l1, l2and/or widths w1, w2of the connection lines54,56so long as the respective widths are selected to adjust the electrical resistance as discussed above with respect to connection lines54,56.

With reference toFIG. 4in which like reference numerals refer to like features inFIG. 3and in accordance with an alternative embodiment of the invention, the wiring50may further include additional connection lines76analogous to connection lines56each terminating at one end with one of the bond pads38on the grind side14bof the interposer14. The bond pads38and the solder bumps40associated with the bond pads38coupled with the connection lines76are disposed between the rows58,62so that the TSV28is surrounded by the bond pads38and solder bumps40. The cross-sectional areas of the connection lines76may be selected as discussed above with respect to connection lines54,56,64,66. The wiring50may include a section72that is positioned between the TSV28and the bond pads38and solder bumps40, and that is larger than section52(FIG. 2). The section72of wiring50may improve the uniformity of the current distribution.

With reference toFIG. 5in which like reference numerals refer to like features inFIGS. 2-4and in accordance with an alternative embodiment of the invention, wiring80that is similar to the wiring50may be configured to couple the bond pads38and solder bumps40with multiple TSVs28that are themselves coupled with a section82that is similar to section72. The enlarged section82may promote the coupling of the multiple TSV's with the wiring80by increasing the surface area available for such coupling. The wiring80includes connection lines83,84,85,86each terminating at one end with one of the bond pads38on the grind side14bof the interposer14. Each of the connection lines83,84,85,86is coupled by one of the bond pads38with a respective solder bump40.

Connection lines83have a width, w3, and length, l3, and are each constituted by a linear segment. Connection lines84have a width, w4, and length, l4, and are each constituted by a linear segment. Connection lines85include a segment of width, w5, and a segment87of width, w7, that collectively provide the length, l5Connection lines86include a segment86of width, w6, a segment88of width, w8, and the segment87that collectively provide the length, l6. The connection lines85,86exhibits a change in direction along their respective length. The cross-sectional area of the connection lines83,84,85,86and the cross-sectional area of the segments87,88may be selected in the same manner as the widths of connection lines54,56to compute electrical resistances that provide a desired power distribution. The section82, which is shared by the connection lines83,84,85,86, may contribute the same electrical resistance to each of the connection lines83,84,85,86as an offset.

The connection lines83,84,85,86may be arranged and include dimensions that permit the bond pads38to match the arrangement for a row of solder bumps40. Additional connection lines similar to connection lines83,84,85,86can be added to the wiring80. In an alternative embodiment, the wiring80may be used to couple the TSVs28with another row of solder bumps40arranged in a row that is parallel and spaced apart from the row of solder bumps40coupled with connection lines83,84,85,86. The additional connection lines would be arranged and include dimensions to add another set of bond pads38to match the locations of solder bumps40in the added row. The TSVs28can then be coupled by the expanded set of connection lines with multiple parallel rows of solder bumps40.

Referring now toFIG. 6, a schematic of an exemplary computer system112is shown. The computer system112may include one or more processors or processing units116, a system memory128, and a bus118that couples various system components including system memory128to each processing unit116. Bus118represents one or more of any of several types of bus structures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, and a processor or local bus using any of a variety of bus architectures. By way of example, and not limitation, such architectures include Industry Standard Architecture (ISA) bus, Micro Channel Architecture (MCA) bus, Enhanced ISA (EISA) bus, Video Electronics Standards Association (VESA) local bus, and Peripheral Component Interconnect (PCI) bus.

Computer system112typically includes a variety of computer system readable media. Such media may be any available media that is accessible by computer system112, and it includes both volatile and non-volatile media, removable and non-removable media.

Program/utility140, having a set (at least one) of program modules142, may be stored in system memory128by way of example, and not limitation, as well as an operating system, one or more application programs, other program modules, and program data. Each of the operating system, one or more application programs, other program modules, and program data or some combination thereof, may include an implementation of a networking environment. Program modules142generally carry out the functions and/or methodologies of embodiments of the invention as described herein.

Computer system112may also communicate with one or more external devices114such as a keyboard, a pointing device, a display124, etc.; one or more devices that enable a user to interact with computer system112; and/or any devices (e.g., network card, modem, etc.) that enable computer system112to communicate with one or more other computing devices. Such communication can occur via Input/Output (I/O) interfaces122. Still yet, computer system112can communicate with one or more networks such as a local area network (LAN), a general wide area network (WAN), and/or a public network (e.g., the Internet) via network adapter120. As depicted, network adapter120communicates with the other components of computer system112via bus118. It should be understood that although not shown, other hardware and/or software components could be used in conjunction with computer system112. Examples, include, but are not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data archival storage systems, etc.

FIG. 7provides a flowchart200that illustrates a sequence of operations that may be performed by the computer system112to design wiring consistent with the embodiments of the invention.

In block210, input parameters characterizing a layout for the wiring are received at the computer system112. For example, the computer system112may receive a set of input parameters characterizing the wiring, such as the length and arrangement of each of the connection lines, a thickness and electrical resistivity of the constituent material of the connection lines, one or more TSVs that are to be coupled with the connection lines, the position of each TSV relative to the connection lines, the positions of solder bumps and bond pads relative to each TSV, etc. The length and arrangement of the connection lines may be influenced by the positions of the solder bumps and bond pads, especially if these positions are predetermined (e.g., in a row). In this regard, the positions of the solder bumps and bond pads may provide a constraint on the layout that is determined for the wiring. In one embodiment, all connection lines are linear current paths relative to an origin at the one or more TSVs. In another embodiment, the positions of the solder bumps and bond pads may result in one or more of the connection lines including multiple segments that are connected to provide a current path.

The system may also receive, as an input parameter, a current that is to be supplied from the one or more TSV's by the connection lines to each of the solder bumps. In an embodiment, the currents supplied to each of the solder bumps may be equal so that the current distribution by the connection lines is balanced. In an alternative embodiment, the currents supplied to each of the solder bumps may be unequal so that the current distribution by the connection lines is metered to the different solder bumps and unbalanced.

In block220, based upon the input parameters, the computer system112may compute a cross-sectional area for each of the multiple connection lines that determines respective electrical resistances and results in the desired distribution of currents. As discussed above, the currents to the solder bumps may be either equal or unequal.

In one embodiment, the computer system112may compute a width for each of the connection lines of uniform thickness and the computation of the respective widths by the computer system112may provide the connection lines with the same electrical resistance calculated per Ohm's Law. As a result, during operation, the current flowing from the one or more powered TSVs to each of the bumps may be equal so that the power distribution is balanced. In an alternative embodiment, the computer system112may compute a cross-sectional area for each of the connection lines and the computation of the respective cross-sectional areas by the computer system112may provide the connection lines with different electrical resistances. As a result, during operation, the current from the one or more powered TSVs to each of the bumps may be differ so that a lesser current is supplied to some bumps and a greater current is supplied to other bumps.

The determination of the cross-sectional area may be couched in terms of electrical conductivity, which has a reciprocal relationship with electrical resistivity. The determination of the electrical resistance may constrain the conductors of the wiring to have a uniform cross-sectional area and/or uniform width along their respective lengths. However, the cross-sectional area and/or width may be piecewise varied along the length of a given connection line such that the result of the computation is a cross-sectional area and/or width for each segment in a set of segments that collectively comprise the connection line. In this instance, a set of correlated lengths and cross-sectional areas/widths may be determined for a given connection line, and associated with the different segments constituting the connection line.

The cross-sectional areas and/or widths of the different connection lines may be determined based on electrical resistance under an assumption that the load on the respective solder bumps is uniform such that the voltage drops used as a factor in the Ohm's Law calculation are equal. However, if the loads are different, then the cross-sectional area and/or width determinations may consider this variable factor.

An integrated circuit layout that includes a layout for wiring comprising the connection lines may be received at a fabrication facility. The layout for the connection lines may include parameters such as the lengths, cross-sectional areas, and/or the widths of the connection lines. The connection lines of the integrated circuit may be fabricated, as discussed herein, consistent with the parameters of the integrated circuit layout.

It will be understood that when an element is described as being “connected” or “coupled” to or with another element, it can be directly connected or coupled to the other element or, instead, one or more intervening elements may be present. In contrast, when an element is described as being “directly connected” or “directly coupled” to or with another element, there are no intervening elements present. When an element is described as being “indirectly connected” or “indirectly coupled” to or with another element, there is at least one intervening element present.