Semiconductor package and manufacturing method thereof

A semiconductor package and a manufacturing method thereof are provided with the following steps, attaching a rear surface of a semiconductor die on a first redistribution structure by a die attach material, wherein the semiconductor die is pressed so that the die attach material is extruded laterally out and climbs upwardly to cover a sidewall of the semiconductor die, and after attaching, the die attach material comprises an extruded region surrounding the semiconductor die, a first shortest distance from a midpoint of an bottom edge of semiconductor die to a midpoint of an bottom edge of extruded region in a width direction is greater than a second shortest distance between an endpoint of the bottom edge of semiconductor die to an endpoint of the bottom edge of extruded region; and forming an insulating encapsulant on the first redistribution structure to encapsulate the semiconductor die and the die attach material.

BACKGROUND

Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. As the demand for shrinking electronic devices has grown, a need for smaller and more creative packaging techniques of semiconductor dies has emerged. Thus, packages such as wafer level packaging (WLP) have begun to be developed, in which integrated circuits (ICs) are placed on a carrier having connectors for making connection to the ICs and other electrical components. In an attempt to further increase circuit density, three-dimensional (3D) ICs have also been developed, in which multiple ICs are bonded together electrical connections are formed between the dies and contact pads on a substrate. These relatively new types of packaging for semiconductors face manufacturing challenges such as poor adhesion between the IC and carriers, sidewall chipping, warpage, die shifting, and other reliability issues.

DETAILED DESCRIPTION

In addition, terms, such as “first,” “second,” “third,” and the like, may be used herein for ease of description to describe similar or different element(s) or feature(s) as illustrated in the figures, and may be used interchangeably depending on the order of the presence or the contexts of the description.

FIG. 1AtoFIG. 1Kare schematic cross-sectional views of various stages of manufacturing a semiconductor package in accordance with some exemplary embodiments of the disclosure.FIG. 2is a schematic enlarged top view illustrating a part of the structure depicted inFIG. 1C, whereFIG. 2shows the enlarged cross-sectional view of the dotted box A indicated inFIG. 1C.FIG. 3is a schematic enlarged top view illustrating a part of the structure depicted inFIG. 1D, whereFIG. 3shows the enlarged top view of the dotted box B indicated inFIG. 1D.FIG. 4is a schematic enlarged cross-sectional view illustrating a part of the structure depicted inFIG. 1D, whereFIG. 4shows the enlarged cross-sectional view of the dot-dashed box C indicated inFIG. 1D.

Referring toFIG. 1A, a temporary carrier50is provided. In some embodiments, the temporary carrier50may include any suitable material that could provide structural support during processing. For example, the temporary carrier50includes metal (e.g., steel), glass, ceramic, silicon (e.g., bulk silicon), combinations thereof, multi-layers thereof, or the like. In some embodiments, a release layer52may be formed on the temporary carrier50. The material of the release layer52may be any material suitable for bonding and de-bonding the temporary carrier50from the structure formed thereon. For example, the release layer52includes a layer of light-to-heat-conversion (LTHC) release coating and a layer of associated adhesive (such as a ultra-violet curable adhesive or a heat curable adhesive layer), or the like.

Referring toFIG. 1BandFIG. 1C, a first redistribution structure100is formed on the temporary carrier50and a conductive connector200may be formed on the first redistribution structure100. The first redistribution structure100may include a first dielectric layer110and a first patterned conductive layer120stacked alternately. In some embodiments, one or more layers of dielectric materials may be represented collectively as the first dielectric layer110, and conductive features (e.g. conductive lines, conductive pads, and/or conductive vias) are collectively represented as the first patterned conductive layer120. The first redistribution structure100may be referred to as a backside redistribution structure given its placement in the structure.

For example, the first dielectric layer110may be formed of any suitable material, such as polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), or other material that is electrically insulating. According to some embodiments, the first dielectric layer110may be formed using any suitable method, such as a spin-on coating process, a deposition process, and the like.

In some embodiments, to facilitate the formation of the first patterned conductive layer120, a seed layer (not shown) may be first formed on the first dielectric layer110using a deposition process, or other suitable method. For example, the seed layer is a conductive layer, which may be a single layer or a composite layer including several sub-layers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer over the titanium layer and may be formed using a deposition process, or other suitable process. Then, a mask material may be formed and patterned on the seed layer to form a mask pattern (not shown) using a spin coating process, an etching process, or other suitable processes. The mask pattern may include a plurality of openings exposing the underlying seed layer. For example, the material of the mask pattern may include a positive photoresist or a negative phot-resist, but not limited thereto. Next, a conductive material including copper, copper alloy, aluminum, aluminum alloy, or combinations thereof, may be formed in the openings of the mask pattern and on the exposed portions of the seed layer using, for example, a sputtering process, a plating process, or other suitable process. Subsequently, the mask pattern and portions of the seed layer on which the conductive material is not formed may be removed. For example, the mask pattern may be removed using stripping process, or other acceptable removing process. After removing the mask pattern, the exposed portions of the seed layer are removed using, such as wet or dry etching process, or other acceptable removing process. The remaining portions of the seed layer and conductive material form the first patterned conductive layer120as shown inFIG. 1B.

In some embodiments, the first redistribution structure100includes more than one of the first dielectric layer110stacked on the first patterned conductive layer120. For example, a layer of the dielectric material may be formed over the first patterned conductive layer120. Then, a portion of the dielectric material may be removed to form the first dielectric layer110using, for example, lithography and etching process, or other suitable methods. In other words, the first dielectric layer110may include a plurality of openings exposing portions of the first patterned conductive layer120for further electrical connection. In some embodiments, the abovementioned steps may be performed multiple times to obtain a multi-layered redistribution structure as required by the circuit design. That is, the numbers of the first dielectric layer110and the first patterned conductive layer120can be selected based on demand and are not limited in the disclosure. In other embodiments, the first patterned conductive layer120may be formed before forming the first dielectric layer110. It should be noted that the forming sequence of the first dielectric layer110and the first patterned conductive layer120depends on the design requirement and construe no limitation in the disclosure.

Continued onFIG. 1C, in some embodiments, a conductive material may be formed in the openings of the first dielectric layer110to connect the first patterned conductive layer120and further protrude on the first dielectric layer110, thereby forming the conductive connectors200. The material of the conductive connector200may be the same or similar with that of the first patterned conductive layer120. According to some embodiments, the conductive connectors200may be formed by photolithography, plating, photoresist stripping processes, or any other suitable method. For example, the conductive connectors200may be formed by forming a mask pattern having openings (not shown), where the mask pattern covers a portion of the first redistribution structure100and exposes another portion of the first patterned conductive layer120with the openings; forming a metallic material to fill the openings so as to form the conductive connector200by electroplating or deposition; and then removing the mask pattern. In certain embodiments, the conductive connectors200are through integrated fan-out (InFO) vias.

In some embodiments, the first redistribution structure100includes a die attach region DR and a peripheral region PR connected to the die attach region DR. The conductive connectors200may be formed in the peripheral region PR of the first redistribution structure100. The first patterned conductive layer120may be formed in the peripheral region PR and/or die attach region DR. In some embodiments, at least a portion of the first patterned conductive layer120are formed in the die attach region DR.

The first redistribution structure100may have a first surface100afacing towards the temporary carrier50and a second surface100bopposite to the first surface100a. Referring toFIG. 1CandFIG. 2, the second surface100bof the first redistribution structure100may be uneven and roughed due to material characteristics and the formation of the first patterned conductive layer120. In some embodiments, the first redistribution structure100may be referred to as a patterned structure. For example, the top surface of the top layer of the first dielectric layer110may include concave areas110acorresponding to the space of the underlying first patterned conductive layer120, such that the concave areas110amay cause the second surface100bto be uneven. That is, the concave areas110amay be formed between adjacent patterns. In some embodiments, at least a portion of the first patterned conductive layer120is formed in the die attach region DR so that the concave areas110aare introduced in the die attach region DR, thereby causing the second surface100bin the die attach region DR uneven. As surface roughness is known that provides a measure of the unevenness of the surface height. For example, the average surface roughness of the second surface100bmay be in the range of about 0.1 um to about 1 um. In some embodiments, the surface roughness in the die attach region DR may range from about 1 um to about 15 um due to the underlying patterned conductive layers. It should be appreciated that the illustration of the concave areas110ais schematic and is not in scale.

Referring toFIG. 1D, a semiconductor die300is provided and disposed on the first redistribution structure100using, for example, a pick and place technique, or other suitable method. In some embodiments, the semiconductor die300is manufactured through a front end of line (FEOL) process, but is not limited thereto. In some embodiments, the semiconductor die300includes a semiconductor substrate310, a plurality of connecting pads320, a plurality of connecting pillars330and a protection layer340. In one embodiment, the semiconductor substrate310may be a silicon substrate including active components (e.g., diodes, transistors or the like) and passive components (e.g., resistors, capacitors, inductors or the like) formed therein. In one embodiment, the connecting pads320may be made of aluminum or alloys thereof, or the like. In some embodiments, the semiconductor die300may include an interconnection structure (not shown) disposed between the semiconductor substrate310and the connecting pads320, where the connecting pads320physically contact the interconnection structure.

In some embodiments, the connecting pillars330are respectively disposed on and electrically connected to the connecting pads320, where the connecting pillars330physically contact the connecting pads320. In one embodiment, the connecting pillars330may include copper pillars, copper alloy pillars, or other suitable metal pillars. In some embodiments, the connecting pillars330may include lead-based materials or lead-free materials with or without additional impurity formed on the top, but is not limited thereto. In some embodiments, the protection layer340covers the connecting pads320, and the connecting pillars330. That is, the protection layer340prevents any possible damage(s) occurring on the surfaces of the connecting pillar330during the transfer of the semiconductor die300. In one embodiment, the protection layer340may be made of a polybenzoxazole (PBO) layer, a polyimide (PI) layer, or suitable polymers or inorganic materials. In some embodiments, the protection layer340may further act as a passivation layer for providing better planarization and evenness. The numbers of the connecting pads320and the connecting pillars330can be selected based on demand and are not limited in the disclosure. It should be appreciated that the illustration of the semiconductor die300and other components throughout all figures is schematic and is not in scale.

For example, the semiconductor die300may include digital die, analog die or mixed signal die, such as application-specific integrated circuit (ASIC) die, logic die, sensor die, but is not limited thereto. Note that, as shown inFIG. 1D, only one semiconductor die300is presented for illustrative purposes; however, it should be noted that the number of the semiconductor die can be one or more than one, the disclosure is not limited thereto. In certain embodiments, additional semiconductor die(s) may be provided, and the additional semiconductor die(s) and the semiconductor die300may be the same type or different types.

The semiconductor die300includes a rear surface300r, a sidewall300sconnected to the rear surface300r, and a bottom edge300e(illustrated inFIG. 2) is between the rear surface300rand the sidewall300s. Continued onFIG. 1D, a rear surface300rof the semiconductor die300is attached to the first redistribution structure100through a die attach material400. In some embodiments, the die attach material400may function as an adhesive mechanism to adhere the semiconductor die300to the first redistribution structure100. For example, the die attach material400may be attached to the rear surface300rof the semiconductor die300before placing the semiconductor die300on the first redistribution structure100. In some embodiments, before placing the semiconductor die300on the first redistribution structure100, the die attach material400on the rear surface300rof the semiconductor die300may include a thickness ranging about 10 um to about 40 um. The die attach material400may have a similar dimension and/or shape to the semiconductor die300. Alternatively, the die attach material400may include other dimensions and shapes. In some embodiments, the die attach material400include a polymer, thermoplastic material (e.g. epoxy resin, phenol resin, etc.), or the like that functions as an adhesive. For example, the die attach material400may be a die attached film (DAF), an adhesive bonding film (ABF), or the like. Other suitable adhesive materials compatible with semiconductor processing environments may be utilized. The die attach material400may be a single film or a multi-layered film, but is not limited thereto. In some embodiments, the die attach material400may include pressure sensitive material and/or radiation sensitive material. For example, the die attach material400may become semi-liquid when subjecting a pressure and/or a heat, and may become sticky to function as an adhesive at elevated pressures and/or temperatures.

For example, during attaching the semiconductor die300, the semiconductor die300is pressed so that the die attach material400is extruded laterally out of the rear surface300rof the semiconductor die300and climbs upwardly to cover a sidewall300sof the semiconductor die300. In some embodiments, a process of applying a temperature to the die attach material400in the range of about 80° C. to about 200° C. is performed while the semiconductor die300is placed on the first redistribution structure100for a duration ranging from about 1 second to about 3 seconds. In some embodiments, the heating operation may be followed after the semiconductor die placement. During the heating operation, the die attach material400may be softened. For example, the die attach material400may be exposed to UV radiation and/or heating to elevated temperatures so as to soften and/or activate the adhesive properties of the die attach material400. In some embodiments, the time taken for applying the temperature (e.g., from about 140° C. to about 200° C.) may range from 1 second to 3 seconds approximately. In some embodiments, during attaching the semiconductor die300, a process of applying a pressure to the die attach material400in the range of about 0.5 MPA to about 3 MPA is performed for the duration ranging from 1 second to 3 seconds approximately. In some embodiments, a force exerted on the semiconductor die300is increased in order to enhance the adhesion between the semiconductor die300and the first redistribution structure100. The elevated pressures and the elevated temperatures can be applied to the die attach material400during the same process or applying separately, the disclosure is not limited thereto.

When the die attach material400is returned to normal temperature and pressure, the die attach material400may return to a solid state and the semiconductor die300can be securely adhered and positioned in the die attach region DR of the first redistribution structure100. In some embodiments, after attaching, the die attach material400may follow the contour of the surface topography of the second surface100bof the first redistribution structure100. For example, the processed die attach material400may fill the concave areas110aon the second surface100bof the first redistribution structure100. The presence of voids may create weak spots on reliability test and cause the semiconductor die loosely attached. After processing to the die attach material400, the voids in the die attach material400may be substantially eliminated, thereby improving the reliability and adhesion between the semiconductor die300and the first redistribution structure100. In some embodiments, after processing to the die attach material400, the interfacial adhesion between the die attach material400and the second surface100bof the first redistribution structure100may be improved by approximately 10% to 50%.

Referring toFIG. 1D,FIG. 3andFIG. 4, in some embodiments, after attaching the semiconductor die300, the die attach material400includes an extruded region ER surrounding the semiconductor die300. For example, the extruded region ER of the die attach material400may be the portion of the die attach material400which is not covered by the rear surface300rof the semiconductor die300. In some embodiments, a first shortest distance D1from a midpoint of an bottom edge300eof the rear surface300rof the semiconductor die300to a midpoint of an bottom edge400eof the extruded region ER of the die attach material400in a width direction of the semiconductor die300is greater than a second shortest distance D2between an endpoint of the bottom edge300eof the rear surface300rof the semiconductor die300to an endpoint of the bottom edge400eof the extruded region ER of the die attach material400. In some embodiments, as the top plan view shown inFIG. 3, the boundary line of the die attach material400may intersect with the boundary line of the semiconductor die300. For example, the boundary line of the die attach material400may intersect with the boundary line of at the vertices of the semiconductor die300or the edges close to the vertices of the semiconductor die300. In other words, a small amount of the die attach material400is extruded out at the corners of the semiconductor die300such that the corner edge of the semiconductor die300may be slightly covered or may not be covered by the die attach material400.

In some embodiments, a width W of the extruded region ER of the die attach material400decreases from the midpoint of the bottom edge400eof the extruded region ER to the endpoint of the bottom edge400eof the extruded region ER. In some embodiments, the width W of the extruded region ER may gradually decrease from the midpoint of the bottom edge400eof the extruded region ER towards the both endpoints of the bottom edge400eof the extruded region ER. The width W (e.g., extruded amount of the die attach material400) can be controlled by, for example, selecting suitable constituents and/or thickness of the die attach material400, adjusting the processing conditions (e.g., pressure, temperature and duration), and the like. In some embodiments, the width W of the extruded region ER of the die attach material400may range from about 5 um to about 200 um. In some embodiments, as shown inFIG. 4, after attaching the semiconductor die300, a covered distance D3of the sidewall300sof the semiconductor die300covered by the extruded region ER of the die attach material400may range from about 5 um to about 200 um.

Referring toFIG. 1E, an insulating encapsulant500is formed on the first redistribution structure100to encapsulate the semiconductor die100and the die attach material400. For example, the insulating encapsulant500may be formed by an over-molding process followed by a planarizing process. For example, the formation of the insulating encapsulant500may include forming an insulating material (not shown) by over-molding to encapsulate the conductive connectors200, the semiconductor die300and the die attach material400, and then planarizing insulating material, the conductive connectors200, and the semiconductor die300until the top surfaces of the connecting pillars330and the protection layer340of the semiconductor die300and the top surfaces200aof the conductive connectors200being exposed by the planarized insulating material to form the insulating encapsulant500.

That is, after the planarizing process, the protection layer340of the semiconductor die300is partially removed to expose the connecting pillars330of the semiconductor die300, and the insulating material is partially removed to expose the top surfaces200aof the conductive connectors200, and the top surfaces of the connecting pillars330and the protection layer340. In other words, as shown inFIG. 1E, the top surfaces200aof the conductive connectors200, the connecting pillars330and the protection layer340are exposed by the top surface500aof the insulating encapsulant500. The top surfaces of the connecting pillars330and the protection layer340may be referred to as an active surface300aof the semiconductor die300. In certain embodiments, after the planarization, the top surface500aof the insulating encapsulant500, the top surfaces200aof the conductive connectors200, and the active surface300aof the semiconductor die300become substantially levelled with and coplanar to each other.

In other embodiments, the conductive connectors200may be formed after forming the insulating material. For example, after forming the first redistribution structure100, then the semiconductor die300may be disposed and attached on the first redistribution structure100. Next, the insulating material is formed on the first redistribution structure100to encapsulate the semiconductor die300and the die attach material400. Subsequently, a drilling process (e.g., a laser drilling, a mechanical drilling, or other suitable process) may be performed on the insulating material to form holes in the insulating material. Next, the conductive material may be filled in the holes of the insulating material. In some embodiments, the insulating material and the conductive material may be planarized such that the insulating encapsulant500and the conductive connectors200are formed. In some embodiments, the conductive connectors200may be referred to as through insulating vias (TIVs).

In some embodiments, after forming the insulating encapsulant500, an inclined interface S is formed between the insulating encapsulant500and the die attach material400. The inclined interface S may be coplanar with the surface of the extruded region ER. As the cross-sectional view depicted inFIG. 1E, the inclined interface S may be nonlinear. For example, the inclined interface S may be a convex-upward surface relative to the first redistribution structure100in the cross section. In some embodiments, the curve which the inclined interface S intersects with the cross-section plane may be substantially concave down toward the first redistribution structure100as depicted inFIG. 1E. In other embodiments, the inclined interface S may be linear, but is not limited thereto. Due to the presence of the extruded region ER of the die attach material400, the maximum stress on the first redistribution structure100may shift from the semiconductor die300side to the insulating encapsulant500side, thereby protecting the semiconductor die300from being subjecting to excessive compressive stress (e.g., caused by CTE mismatch).

Referring toFIG. 1F, a second redistribution structure600is formed on the insulating encapsulant500. For example, the second redistribution structure600may include a second dielectric layer610and a second patterned conductive layer620sequentially formed on the insulating encapsulant500, where the second patterned conductive layer620is connected to the conductive connectors200and the connecting pillars330of the semiconductor die300. In some embodiments, the second patterned conductive layer620is electrically connected to the first redistribution structure100through the conductive connectors200.

In some embodiments, the second dielectric layer620is formed by forming a dielectric material (not shown) on the active surface300aof the semiconductor die300, the top surfaces200aof the conductive connectors200and the top surface500aof the insulating encapsulant500, and patterning the dielectric material to form a plurality of openings (not marked) exposing the top surfaces200aof the conductive connectors200and portions of the active surface300aof the semiconductor die300(e.g., the top surfaces of the connecting pillars330). Then, the second patterned conductive layer620is formed by forming a conductive material (not shown) on the second dielectric layer610, where the conductive material filling into the openings formed in the second dielectric layer610to physically contact the top surfaces200aof the conductive connectors200and the top surface of the connecting pillars330of the semiconductor die300. Subsequently, patterning the conductive material to form the second patterned conductive layer620. It should be noted that the forming sequence of the second dielectric layer610and the second patterned conductive layer620depends on the design requirement and construe no limitation in the disclosure. Due to the configuration of the second dielectric layer610and the second patterned conductive layer620, a routing function is provided to the package structure such that of the second redistribution structure600is referred as a front side redistribution structure. In certain embodiments, as the underlying insulating encapsulant500provides better planarization and evenness, the later-formed second redistribution structure600can be formed with uniform line-widths or even profiles, resulting in improved line/wiring reliability.

The formation of the second redistribution structure600includes sequentially forming one or more second dielectric layers610and one or more layers of second patterned conductive layers620in alternation. In certain embodiments, the second patterned conductive layers620are sandwiched between the second dielectric layers610, where the top surface of the topmost layer of the second patterned conductive layers620is exposed by a topmost layer of the second dielectric layers610, and a bottom surface of the lowest layer of the second patterned conductive layers620is exposed by the lowest layer of the second dielectric layers610. In one embodiment, the top surface of the topmost layer of the second patterned conductive layers620exposed by a topmost layer of the second dielectric layers610may be connected to a later-formed component(s), and the bottom surface of the lowest layer of the second patterned conductive layers620exposed by the lowest layer of the second dielectric layers610is connected to an underlying component (e.g. the semiconductor die300and the conductive connectors200).

The material and the forming process of the second redistribution structure600may be similar with that of the first redistribution structure100, and the detailed descriptions are omitted for simplification. In some embodiments, as shown inFIG. 3, the second redistribution structure600includes more than one dielectric layers610and multiple second patterned conductive layers620stacked alternately; however, the disclosure is not limited thereto. The numbers of the second dielectric layer610and the second patterned conductive layer620is not limited in this disclosure.

In some other embodiments, a plurality of pads (not marked) may be formed on some of the top surface of the topmost layer of the second patterned conductive layer620for electrically connecting with the later-formed components. For example, the above-mentioned pads include under-ball metallurgy (UBM) patterns for ball mount and/or connection pads for mounting of electronic components. In one embodiment, the material of the pads may include copper, nickel, titanium, tungsten, or alloys thereof or the like, and may be formed by an electroplating process. The shape and number of the pads is not limited in this disclosure.

Referring toFIG. 1G, an electronic component700may be optionally disposed on the second redistribution structure600to generate the desired functional requirements. In some embodiments, the electronic component700includes a surface mount component, integrated passive component (e.g., resistors, capacitors, or the like), or the like.

Referring toFIG. 1H, a conductive terminal800may be formed on the second redistribution structure600for external electrical connection. In some embodiments, the conductive terminals800may be disposed on the second patterned conductive layer620of the second redistribution structure600by a ball placement process, a plating process, or other suitable processes. For example, the conductive terminals800include solder balls, ball grid array (BGA) balls, or other terminals, but is not limited thereto. Other possible forms and shapes of the conductive terminals800may be utilized according to the design requirement. In some embodiments, a soldering process and a reflow process may be optionally performed for enhancement of the adhesion between the conductive terminals800and the second redistribution structure600.

Referring toFIG. 1I, a plurality of conductive joints70is formed on the first redistribution structure100opposite to the insulating encapsulant500. In some embodiments, after forming the electronic component700and the conductive terminals800, the temporary carrier50and the release layer52are removed to expose the first surface100aof the first redistribution structure100. For example, the temporary carrier50is detached from the first redistribution structure100through a de-bonding process. In some embodiments, the external energy such as UV laser, visible light or heat, may be applied to the release layer52so that the first redistribution structure100and the temporary carrier50can be separated. Subsequently, the structure may be flipped (turned upside down) and placed on a holder60for subsequent processes formed on the first surface100aof the first redistribution structure100as shown inFIG. 1I.

After removing the temporary carrier50and the release layer52, forming a plurality of openings (not marked) on the first surface100aof the first redistribution structure100. For example, the first dielectric layer110is patterned to form openings exposing at least a portion of the first patterned conductive layer120using, for example, an etching process, a laser drilling process, or other suitable process. Next, the conductive joints70may be formed or dispensed in the openings of the first dielectric layer110. In some embodiments, the conductive joints70are made of solder materials (e.g., solder paste or the like). In some embodiments, the conductive joints may be referred to as solder joints.

Referring toFIG. 1JandFIG. 1K, a semiconductor device900is provided and may be disposed on the first redistribution structure100opposite to the insulating encapsulant500. In some embodiments, through the first redistribution structure100, the conductive connectors200and the second redistribution structure600, the semiconductor device900is electrically connected to the semiconductor die300.

In some embodiments, the semiconductor device900may be bonded to the first redistribution structure100with the conductive joints70therebetween through flip chip bonding technology and/or surface mount technology. The disclosure is not limited thereto. For example, the semiconductor device900may include digital chips, analog chips or mixed signal chips, such as application-specific integrated circuit (ASIC) chips, sensor chips, wireless and radio frequency (RF) chips, MEMS chips, CIS chips, pre-assembled packages, memory chips, logic chips or voltage regulator chips. The disclosure is not limited thereto. For example, the semiconductor device900may include terminals910. The terminals910may be disposed and/or positioned on the conductive joints70. In some embodiments, a subsequent bonding process may be performed to bond the conductive joints70and terminals910of the semiconductor device900. For example, a reflow process may be performed such that a portion of the terminals910and/or the conductive joints70may melt during the reflow process and form at least portions of the solder regions between the terminals910and the first redistribution structure100. Other suitable methods may be utilized to attach the semiconductor device900onto the first redistribution structure100. The disclosure is not limited thereto.

Continued onFIG. 1K, an underfill material80may be formed between the semiconductor device900and the first surface100aof the first redistribution structure100using, for example, a dispensing process, or other suitable method. In some embodiments, the underfill material80at least fills the gaps between the conductive joints80and between the first redistribution structure100, the semiconductor device900to provide structural support and protection to the terminals910of the semiconductor device900. In some embodiments, the underfill material80may be a molding compound including polymer material (e.g., epoxy, resin, and the like) either with or without fillers (e.g., silica filler, glass filler, and the like), adhesion promoters, combinations thereof, and the like.

After forming the underfill material80, the conductive terminals800may be released from the holder60to form a semiconductor package10. For example, a dicing process is performed to form a plurality of the semiconductor packages10into individual and separated semiconductor packages10. In one embodiment, the dicing process is wafer dicing process including mechanical blade sawing, laser cutting, or other suitable method. In some embodiments, the semiconductor package10is placed in the tray and ready to package out. Up to here, the manufacture of the semiconductor package10is completed.

According to some embodiments, a manufacturing method of a semiconductor package is provided with the following steps: attaching a rear surface of a semiconductor die on a first redistribution structure by a die attach material, where during attaching the semiconductor die, the semiconductor die is pressed so that the die attach material is extruded laterally out of the rear surface of the semiconductor die and climbs upwardly to cover a sidewall of the semiconductor die, and after attaching the semiconductor die, the die attach material comprises an extruded region surrounding the semiconductor die, a first shortest distance from a midpoint of an bottom edge of the rear surface of the semiconductor die to a midpoint of an bottom edge of the extruded region of the die attach material in a width direction of the semiconductor die is greater than a second shortest distance between an endpoint of the bottom edge of the rear surface of the semiconductor die to an endpoint of the bottom edge of the extruded region of the die attach material; and forming an insulating encapsulant on the first redistribution structure to encapsulate the semiconductor die and the die attach material.

According to some embodiments, a manufacturing method of a semiconductor package is provided with the following steps: providing a semiconductor die with a die attach material; placing the semiconductor die on a patterned structure, where the die attach material is between the semiconductor die and the patterned structure and in contact with a roughed surface of the patterned structure, and a surface roughness of the roughed surface ranges from about 1 um to about 15 um; subjecting the die attach material to a pressure and a temperature; and forming an insulating encapsulant on the patterned structure to encapsulate the semiconductor die and the die attach material.

According to some embodiments, a semiconductor package includes a first redistribution structure, a semiconductor die, a die attach material and an insulating encapsulant. The semiconductor die is disposed on the first redistribution structure and includes a rear surface, a sidewall connected to the rear surface and a bottom edge between the rear surface and the sidewall. The die attach material is disposed between the first redistribution structure and the semiconductor die and includes an extruded region, where a first shortest distance from a midpoint of the bottom edge of the semiconductor die to a midpoint of an bottom edge of the extruded region of the die attach material in a width direction of the semiconductor die is greater than a second shortest distance between an endpoint of the bottom edge of the semiconductor die to an endpoint of the bottom edge of the extruded region of the die attach material. The insulating encapsulant is disposed on the first redistribution structure and encapsulates the semiconductor die and the die attach material, where an inclined interface is between the insulating encapsulant and the extruded region of the die attach material.