Quadrature decoder filtering circuitry for motor control

The disclosed quadrature decoder filtering circuitry for motor control uses one quadrature signal to correct an error in the other quadrature signal, thus allowing a noisy signal due to large dust particles or scratches to be recovered. In some implementations, a system processing for quadrature signals comprises a first circuitry triggered by edges of a first quadrature signal to detect inactivity of a second quadrature signal during consecutive edges of the first quadrature signal. A second circuitry is operable to count the number of consecutive edges of the first quadrature signal during inactivity of the second quadrature signal. A third circuitry is operable to combine transitions of the first quadrature signal with the second quadrature signal during a period of time determined by the count value of the second circuitry.

TECHNICAL FIELD

This subject matter is generally related to electronics, and more particularly to a quadrature decoder filtering circuitry for motor control.

BACKGROUND

A speed/rotation sensor of an electrical motor typically comprises an optical or magnetic disk mounted on the shaft of the motor. An optical disk contains a series of light reflective or magnetic bars that allows electrical pulses to be generated. Noise introduced by dust and scratches located on an optical disk of a speed sensor of a motor may create inaccurate processing by downstream circuitries, including but not limited to false direction detection that may lead to inaccuracy in system positioning and/or additional delay in positioning.

Small dust particles can produce small spurious pulses in the electrical pulses, which can be easily filtered using conventional filtering circuitry. Large dust particles and scratches, however, may produce spurious pulses having larger duration, which are more difficult to suppress using conventional filtering circuitry designed to filter small spurious pulses.

SUMMARY

The disclosed quadrature decoder filtering circuitry for motor control uses one quadrature signal to correct an error in the other quadrature signal, thus allowing a noisy signal to be recovered. In some implementations, a system processing for quadrature signals comprises a first circuitry triggered by edges of a first quadrature signal to detect inactivity of a second quadrature signal during consecutive edges of the first quadrature signal. A second circuitry is operable to count the number of consecutive edges of the first quadrature signal during inactivity of the second quadrature signal. A third circuitry is operable to combine transitions of the first quadrature signal with the second quadrature signal during a period of time determined by the count value of the second circuitry.

DETAILED DESCRIPTION

FIG. 1is a block diagram of an example microcontroller with a quadrature decoder (QDEC) and a pulse width modulator (PWM) module connected as a peripheral of a microprocessor core located in the microcontroller. In this example configuration the QDEC is included in a microcontroller. The QDEC, however, can be used in any type of integrated circuit (IC) device.

To control a motor (e.g., speed, position), a control application generates signals to create the rotation of the motor and receives and processes signals generated by a rotary sensor module mounted on the shaft of the motor. This rotary sensor produces electrical signals that enable the motor control logic circuitry to be aware of the rotation, speed and direction of the motor. This feedback circuitry allows operation of the motor in a closed loop system for accurate speed and positioning of the motor.

The feedback circuitry processing these signals is often a standard microcontroller. The microcontroller can include a peripheral module (e.g., a PWM module) to generate the signals used to operate rotation of the motor. The signals from the microcontroller can be amplified (e.g., voltage, current) by means of power transistors (e.g., MOSFET power transistors) or any other power transistors, prior to driving the coils of the motors. The signals generating the rotation are well known in the art and will not be discussed further in this document.

The feedback signals from the rotary sensor are usually not directly processed by the microprocessor module of the microcontroller but rather are processed by a peripheral module (e.g., a QDEC), which performs filtering and analysis. This method is generally the only way to process these signals in a real time manner without requiring too much power (e.g., very high clock frequency) for the microprocessor core. Increasing power by adding additional circuitry would make the bill of materials of the control application too expensive for volume production.

Referring toFIG. 1, the microcontroller100comprises a microprocessor101capable of accessing peripheral circuitries like PWM module105and “TIMER+QDEC” Quadrature Decoder106. Data exchanges are performed by means of the system bus120, which comprises (not shown) a read data bus carrying data from peripherals to microprocessor101, a write data bus carrying data from microprocessor101to peripherals, an address bus and control signals to indicate transfer direction on system bus120. Since the address bus of the system bus120is shared by all peripherals there is a need to decode the value carried on this bus to select one peripheral at a time. A circuitry102acts as an address decoder by receiving the address bus (part of system bus120) and provides select signals121,122,123,124. Peripheral circuits103,104,105,106read these select signals to take into account values carried on system bus120.

On-chip memories103store the application software to be processed by microprocessor101. The microcontroller100is powered by means of a different set of terminals140. Terminals140comprise a series of physical access terminals (PADs) to power the microcontroller100, some for providing VDD, some for providing GND. A user application runs software, which may be loaded within on-chip memories103during the startup of the microcontroller (boot section). The software located within on-chip memory103is fetched by microprocessor101by means of system bus120. The on-chip memory103is selected (e.g., signal123is active) as soon as the address value of the address bus matches the address range allocated for the on-chip memory. The address decoder102is designed accordingly, the address range being hard-wired in the address decoder. As a response, the memory provides the corresponding data onto system bus120which is read by microprocessor101and processed accordingly.

The software may also be aware of the availability of a data through the interrupt signal125. When set, this signal triggers interrupt module104. Then the interrupt controller104signals the event directly to a dedicated pin of the microprocessor101. A central interrupt module allows any number of interrupts to be handled by a single input pin on the microprocessor101. When the microprocessor101is triggered by the interrupt signal, its internal state machine interrupts the processing of the current task and performs a read access on the interrupt controller104by means of system bus120to get the source (peripheral) of interrupt.

The microcontroller100supervises the control of an electrical motor150. To get feedback information, a rotary sensor160is mounted on shaft161. To create the rotation, the PWM module105generates a set of signals132. The rotation is detected by rotary sensor160, which creates electrical signals133and134according to the speed of the motor. The amplification of signals132in order to match the voltage requirements of the motor, and amplification of signals133,134to adapt the microcontroller100voltage levels and the power supply circuitries of rotary sensor are well known and therefore not described in this document.

Several types of rotary sensors exist but they basically provide the same type of electrical signals. If only one signal is provided there is no way to determine the rotation direction. Some sensors provide two electrical signals aligned in quadrature. This quadrature alignment, after processing (decoding) provides the direction of rotation.

FIGS. 2 and 3illustrate output waveforms200,201of a rotary sensor aligned in quadrature. In this example, the output waveform200corresponds to the waveform of signal133ofFIG. 1and the output waveform201corresponds to the waveform of signal134ofFIG. 1. Quadrature alignment allows easy detection of the direction of rotation using simple circuitry. Depending on the value sampled by the rising edge of signal133(waveform200) on signal134(waveform201) the rotation is determined. The rising edge of waveform200may capture either a logical “0” or “1” on signal201. A direction change event can also be declared as soon as two consecutive edges on one of the quadrature signals occurs without any change on the other quadrature signal.

The waveforms200,201shown inFIG. 3can be easily determined when one knows how the sensor generating the waveforms200,201is built. An optical disk is often mounted on the shaft of a motor. The optical disk contains a series of reflective bars. A Light Emitting Diode (LED) generates a light beam which bounces on the disk or not and is detected by a receiving diode circuitry (e.g., an amplifier, filter, level shifter) to provide the waveform200. In a quadrature sensor interface, at least two series of reflective bars are printed in quadrature and two LED emitters/receivers are mounted to provide the quadrature waveforms200,201. The same result can be obtained by a series of holes within the disk, so that the light source is transmitted to the receiver or not, thus creating the same waveforms200,201as reflective bars method.

The more bars on a disk, the more accuracy the sensor provides for rotation at lower speed. The speed can be calculated by differentiating the accumulated number of received pulses. A time base is generated, providing sampling points. For each sampling point, the counter is first stored in a register and then cleared; otherwise, the pulses are counted. The register contains an image of the speed of rotation. In practice, however, the optical disk may not be as clean. Dust particles and scratches may be located on the disk. Therefore, the output signal from the rotary sensor may be corrupted due to dust particles and scratches, which can cause spurious pulses in the signal generated by the rotary sensor. These spurious signals can be misread by downstream circuitry as, for example, a direction change in rotation of the motor shaft.

FIG. 4illustrates spurious pulses in sensor output waveforms200,201due to light reflective and light absorbing dust. Depending on the nature of the dust, the light can be absorbed or reflected, resulting in a glitch in the waveforms200,201that can be positive or negative.

FIG. 5is a schematic diagram of a circuit that overcomes spurious pulses resulting from dust or scratches located on an optical disk. Referring to the left-hand portion of the circuit, the PHA input signal is generated by the rotary sensor and is first sampled on the system clock (“Clock”) signal of filtering synchronous logic. Because the PHA signal is asynchronous, a proper synchronization circuit can be a dual stage flip-flop (DFF). But for simplicity only one DFF500is described in the circuitry shown. The signal520(“PHA”) is therefore synchronous of “Clock.”

DFF501samples the signal520and both DFF500and DFF501outputs are compared by means of XNOR gate502. The output522of XNOR gate502is high (logical “1”) when there is no difference between the outputs520and521. The output522drives a series of AND gates505, where one input of each AND gate of the series is connected to output522. As soon as output522is cleared, i.e., there is an edge on input PHA, the outputs of the series of AND gates505are cleared. Therefore, one “Clock” cycle later, the signal524“Count” has cleared its current value. When PHA input is stable, two “clock” cycles after output522is high (logical “0”), the series of AND gates505acts as transparent cells because 1 AND X results in X (X representing logical 1 or 0).

Signal524feeds incrementor503, comparator504and a series of 2 to 1 multiplexers507. The incrementor503provides on its output the input value +1. The current value524is compared with a maximum value “max” which can be driven by a configuration register accessible from a software user interface. This value modifies the filtering feature of the circuitry. For simplicity, we will assume a constant value of 4. Just after being cleared, the value524is lower than 4, as a consequence the signal523is cleared and multiplexers507copy, respectively, on their outputs, their inputs driven by the output of incrementor503, so 1 is loaded on outputs of “Count signal524. And so on up to 4. When524reaches 4, the output of the comparator504is set and multiplexers507copy, respectively, on their outputs, their inputs driven by signal524, the “count” value is held.

The output of comparator504is also driving two-input AND gate509. The second input is driven by output522. If the “count” value is 4 and “PHA” input is stable, true when output522is set, the output of AND gate509is high. When high, the 2 to 1 multiplexer508copies signal521on its output, therefore DFF510loads an image of the input value “PHA” on signal525; otherwise, DFF510and multiplexer508re-circulates the data525. Both cells (multiplexer509and DFF510) constitute a sample and hold function. As a consequence, if “PHA” is not stable for more than 4 clock cycles, “PHA” is not copied on output525. The filter circuitry described inFIG. 5delays the output by 4 clock cycles compared to the input PHA.

FIG. 6illustrates the waveforms of the circuitry ofFIG. 5. The circuitry shown inFIG. 5can be found on many existing integrated circuits because it prevents false detection of direction changes in rotation. A spurious pulse locally looks like a direction change (refer toFIG. 4). If this circuitry is efficiently filtering spurious pulses introduced by dusts located on the disk, the circuitry cannot efficiently filter the noise introduced by large dust particles or scratches because a scratch may cover several reflective bars. If the filtering capability (e.g., the “max” value of the circuitry ofFIG. 5) is increased, then correct pulses from the reflective bars may be filtered, resulting in no rotation detection. So another technique and circuitry is needed for large dust particles and scratches. Such circuitry can be located downstream compared to the previously described filtering circuitry shown inFIG. 5.

FIG. 7shows a change in rotation followed by a quadrature signal error due to dust that masks a reflective bar. Even if there is a condition of change at the time the quadrature error occurs (e.g., two edges of one signal while the other remains at the same logical value), one can see that there is no change in the quadrature signals alignment just before and just after the dust masking (e.g., the rising edge of signal200samples a logical ‘1’ on201just before the dust masking but also just after). Thus declaring a rotation change when the quadrature error occurs may lead to unpredictable behavior of the logic downstream. Of course this situation can be also found without any dust or scratch, if the motor is started in one direction then stopped, direction reverted for one reflective bar, then reverted again and so on. But it is unlikely to occur for a normal mode of operation, especially when the motor is powered in one direction for several rounds or several seconds (e.g., hundreds or thousands of rounds).

The method and circuitry described below in reference toFIGS. 8 and 9detects errors in a quadrature signal, and corrects missing pulses in the quadrature signal. The method is based on consecutive edges counting on one quadrature signal while the other quadrature signal is constant. The determination of direction change or a missing pulse will depend on events of the constant signal and count value (odd, even). The correction of missing pulses will also depend on count value. To calculate speed and position, the edges of signals200and201are counted.

FIG. 8is schematic diagram of example quadrature decoder filter circuitry for detecting errors in a quadrature signal, and for correcting missing pulses in the quadrature signal. The circuitry ofFIG. 8can be connected downstream to the filtering circuitry described inFIG. 5or coupled directly to rotary sensor outputs. For simplicity,FIG. 8shows the circuitry coupled directly to rotary sensor outputs (PHA, PHB).FIG. 8describes circuitry to detect and correct a missing pulse on PHB using an edge of PHA. The same circuit can be used for detecting and correcting a missing pulse on PHA using an edge of PHB. Part of the logic can be shared between these two circuitries. In practice the circuitry shown inFIG. 8can be duplicated to process the input signal PHA in the same manner as input signal PHB is processed, as described below.

Referring now toFIG. 8with reference to the waveforms ofFIG. 9, because the signals PHA and PHB are asynchronous to the synchronous logic system clock (“clock”), the signals PHA and PHB are first sampled using, respectively, DFF600and DFF606. To detect the rising or falling edges in a synchronous way, the outputs of DFF600and DFF606are sampled again using respectively DFF601and DFF607. When the input PHA switches from 0 to 1 or 1 to 0, the output value of DFF600differs from output value of DFF601for one clock cycle. This difference is detected by means of XOR gate602generating a logical “1” on signal652each time a difference occurs between DFF600and DFF601. The same structure is located on PHB path, with XOR gate608generating a logical “1” on signal657, so that a difference exists between the output of DFF606and the output of DFF607. A difference is detected as soon as a rising edge or a falling edge occurs on PHA or PHB. Therefore, cells601and602act as an edge detector for input PHA and cells607and608act as an edge detector for input PHB.

Let's now assume there is a direction change in rotation and two consecutive edges of PHA occurs without any change on PHB. The edge detection of PHA, signal652, drives the select input of 2 to 1 multiplexer603so that when there is an edge detected on PHA (signal652is high), the multiplexer603selects the input driven by signal655. Signal655is an image of PHB input. When there is no more edge on PHA, two clock cycles later the signal652is cleared and multiplexor603selects the input driven by the output of DFF604. Therefore, DFF604stores the value of PHB when an edge occurs on PHA. So for any PHA edge, the value of PHB during the previous PHA edge is available by reading DFF604output. A matching circuit, for example, XNOR gate605receives output of DFF604and signal655(image of PHB) and drives a 1 on signal653when both inputs are equal. This is the case when two consecutive edges of PHA samples the same value on PHB, so when a possible direction change occurred. Signal653also drives two-input AND gate618. The other input is driven by signal652, which corresponds to the detection of any PHA edge. The output of the AND gate is set when there are two consecutive edges of PHA sampling the same value on PHB. This result drives a series of multiplexers615which select the output of incrementor614when output of AND gate618is high. When the AND gate618output is 0, the set of multiplexers615copy the other input driven by the output of DFF617, thus re-circulating the data (hold function), if the set of AND gate616acts as transparent (e.g., the output of two-input NAND gate613is high). The incrementor614is driven by the output of the series of DFF617. Therefore if DFF617is carrying 0, incrementor output will be 1, and this value will be loaded by DFF617because NAND gate613is driven by the output of bit wise OR gate612. The bit wise OR gate612receives all outputs of the set of DFF617and makes an OR between all these bits resulting in logical “1” on its output when signal658differs from 0. When 0, the NAND gate613drives a 1 on its output. Therefore, the set of AND gate is transparent and signal658is incremented. So cells614to617form a counter that counts the number of times two consecutive edges on PHA samples the same data on PHB.

The direction change detection logic (not shown) does not declare a change direction at this time (when signal658changes from 0 to 1). When signal658is 1, if an edge occurs on PHB, the signal657is set and bitwise OR gate612is 1 because signal658differs from 0 (the LSB of signal658is set); therefore NAND gate613output is 0. This value clears the outputs of AND gates616, therefore clearing the DFF617output and signal658. The direction change detection logic (not shown) can declare a direction change by using the output of NAND613(e.g., signal658equals 1 and output of NAND613is 1).

Let's now assume, there is a scratch or big dust on PHB reflective bars of the optical disk on signal654. There are missing pulses on signal657due to this noise. Therefore, the counter made of cells614to617counts up to the next edge of PHB as described in reference to the previous figures. When the counter increments from 1 to 2 (refer to waveforms onFIG. 9), there is an edge on PHA but at this time the output of comparator619is 0 because signal658is still 1 (just switching to 2). Comparator619drives a 1 on its output when the value of signal658is strictly greater than 1. When signal658is 2 and edge occurs again on PHA, then there is a quadrature error and direction change is not the root cause; therefore there is a missing pulse and no edge can be detected without correction. When signal658is 2 and an edge occurs on PHA, signal652is set, therefore two-input AND gate620drives a 1 on input of DFF621and also two-input OR gate622. The output of OR gate622is high. Therefore, a 1 is propagated to output659through two-input OR gate623. If synchronous counter logic is placed downstream signal659, it will increment by one whereas PHB input has no edge. Correction is active but since a complete pulse was lost, 2 edges are missing. The edge on PHA results on a 1-clock cycle pulse on signal652. This is sampled by DFF621and its output is high the next clock cycle and for 1 clock cycle. The DFF621driving the output of OR gate622, there is a 1 on this output for one more clock cycle, therefore propagating to output signal659. Then for each missing pulse on PHB, any pulse on PHA creates a two-clock cycle pulse duration on signal659. Therefore, if downstream logic is a synchronous counter it will increment by two, which corrects the missing edge of PHB.

Depending on the counter value one can also determine if the direction change occurred at the time missing edges are detected. If the counter value658is odd and there is an edge detected on signal654(e.g., signal657equals 1) then we have also a direction change. If the counter value is even, then only missing edges are detected and also corrected.