Data storage device and flash memory control method

A flash memory control technology with power recovery capability, by which command sequence information is generated for write data that is requested to be written into a flash memory. A random access memory is allocated for temporary storage of the write data and the command sequence information. The write data is uploaded from the random access memory onto a run-time write block between physical blocks of the flash memory with the command sequence information corresponding thereto. During a power recovery process of a data storage device that is equipped with the flash memory, the run-time write block is checked and, according to the command sequence information that has been uploaded onto the run-time write block, the write data in the run-time write block and later in a command sequence than lost data is abandoned.

CROSS REFERENCE TO RELATED APPLICATIONS

This Application claims priority of Taiwan Patent Application No. 104102053, filed on Jan. 22, 2015, the entirety of which is incorporated by reference herein.

BACKGROUND OF THE INVENTION

Field of the Invention

The present invention relates to data storage devices with flash memory and flash memory control methods.

Description of the Related Art

Flash memory, a data storage medium, is common in today's data storage devices. A NAND flash is one common type of flash memory.

For example, flash memory is typically used in memory cards, USB flash devices, solid-state drives, and so on. In another application with multi-chip package technology, a NAND flash chip and a controller chip are combined in one package as an embedded multi-media card (e.g. eMMC).

The storage space of a flash memory generally provides a plurality of physical blocks, and each physical block includes a plurality of physical pages. To release storage space for reuse, an erase operation has to be performed on a block-by-block basis, to release space one block at a time. When updating data, the new data is written into a spare space rather than being overwritten onto old data, and the old data has to be invalidated. Thus, the storage space management of flash memory is more complex than other storage mediums. A controller designed especially for flash memory is therefore called for.

BRIEF SUMMARY OF THE INVENTION

A flash memory control technology with power recovery capability is shown.

A data storage device in accordance with an exemplary embodiment of the disclosure comprises a flash memory and a control unit. The flash memory provides a storage space that is divided into a plurality of physical blocks with each physical block comprising a plurality of physical pages. The control unit comprises a microcontroller and a random access memory. The microcontroller is configured to generate command sequence information for write data and further allocate the random access memory for temporary storage of the write data and the command sequence information. The microcontroller is further configured to upload the write data from the random access memory onto a run-time write block between the physical blocks of the flash memory with the command sequence information. The microcontroller is further configured to check the run-time write block during a power recovery process of the data storage device. Based on the command sequence information that has been uploaded onto the run-time write block, the write data in the run-time write block and later in a command sequence than lost data is abandoned. In this manner, after the power recovery process for the power failure events, the valid data in the run-time write block complies with the command sequence. When considering the operational efficiency and therefore not following the command sequence to upload the write data onto the run-time write block, the valid data in the run-time write block still complies with the command sequence after the power recovery process.

A flash memory control method in accordance with an exemplary embodiment of the disclosure comprises the following steps: generating command sequence information for write data that is requested to be written into a flash memory, and allocating a random access memory for temporary storage of the write data and the command sequence information; uploading the write data onto a run-time write block between physical blocks of the flash memory with the command sequence information corresponding thereto, each physical block comprising a plurality of physical pages; and checking the run-time write block during a power recovery process of a data storage device that is equipped with the flash memory, to abandon the write data in the run-time write block and later than lost data in a command sequence in accordance with the command sequence information that has been uploaded onto the run-time write block.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1depicts a storage space provided by a flash memory100, which is divided into a plurality of physical blocks BLK1, BLK2. . . BLKi . . . Each physical block comprises a plurality of physical pages.

FIG. 2depicts a data storage device200in accordance with an exemplary embodiment of the disclosure, which comprises a flash memory202and a control unit204. The control unit204is coupled between a host206and the flash memory202to operate the flash memory202in accordance with the commands issued from the host206.

The storage space of the flash memory202is allocated to provide ISP (in-system-program) blocks210, spare blocks212, a run-time write block CB and a data pool214. The ISP blocks210store in-system programs (ISPs). The run-time write block CB is allocated from the spare blocks212for reception of write data issued from the host206. When the collection of write data is finished, the run-time write block CB is pushed into the data pool214and another physical block between the spare blocks212is allocated to play the role of the reception block of the write data.

The control unit204includes a microcontroller220, a random access memory222(e.g. an SRAM) and a read-only memory224. The read-only memory224stores read-only codes (e.g. ROM code). The microcontroller220operates by executing the ROM code stored in the read-only memory224or/and by executing the ISPs stored in the ISP blocks210of the flash memory202.

The microcontroller220is configured to generate command sequence information for write data, and further allocates the random access memory222for temporary storage of the write data and the command sequence information. The microcontroller220is further configured to upload the write data from the random access memory222onto the run-time write block CB of the flash memory202with the command sequence information. The microcontroller220is further configured to check the run-time write block CB during a power recovery process of the data storage device200. Based on the command sequence information that has been uploaded onto the run-time write block CB, the write data in the run-time write block and later in a command sequence than lost data is abandoned.

In this paragraph, the exemplary embodiment ofFIG. 2is discussed in detail. The host206issues write commands that contain write data Data1, Data2, Data3, Data4and Data5. Based on the order of the write commands, the microcontroller220generates command sequence information S1, S2, S3, S4and S5for the write data Data1, Data2, Data3, Data4and Data5, to show that the write data Data1is requested earlier than the write data Data2, the write data Data2is requested earlier than the write data Data3, the write data Data3is requested earlier than the write data Data4, and the write data Data4is requested earlier than the write data Data5. The microcontroller220is further configured to upload the write data Data1. . . Data5from the random access memory222onto the run-time write block CB of the flash memory202with the command sequence information S1. . . S5. Note that the run-time write block CB is updated for the best performance of the flash memory202. It means that the data uploaded onto the run-time write block CB may be inconsistent with the order of the write commands. InFIG. 2, considering the operational efficiency of the flash memory202, the write data Data4and Data5and the command sequence information S4and S5corresponding thereto are uploaded onto the run-time write block CB earlier than the write data Data2and Data3and the command sequence information S2and S3. However, inFIG. 2, a sudden power-off event SPO occurs before uploading the write data Data2and Data3and the command sequence information S2and S3onto the run-time write block CB. During the power recovery process (e.g., a sudden power off recovery process, a.k.a. SPOR process) of the data storage device200, the microcontroller220is configured to check the run-time write block CB. Based on the command sequence information S1, S4and S5contained in the run-time write block CB, the microcontroller220abandons the write data Data4and Data5in the run-time write block CB because the write data Data4and Data5is later than the lost data Data2and Data3in the command sequence (e.g. the host206requests the write data Data4and Data5later than the lost data Data2and Data3). In an exemplary embodiment, the physical pages storing the write data Data4and Data5and the command sequence information S4and S5in the run-time write block CB are regarded as containing invalid data. In this manner, the run-time write block CB with the remaining valid data Data1is consistent with the command sequence. The microcontroller220may be further configured to build logical-to-physical address mapping information for the run-time write block CB. In summary, the run-time write block CB after the power recovery process is consistent with the command sequence even though the write data was not uploaded onto the run-time write block CB according to the command sequence.

FIG. 3is a flowchart depicting a write process of a flash memory202in accordance with an exemplary embodiment of the disclosure, which is discussed with respect toFIG. 2. In step S302, write data issued from the host206is received by the data storage device200. The first received write data is Data1. In step S304, the command sequence information for the write data that is requested to be written into the flash memory202is generated. Thus, command sequence information S1is generated for the write data Data1. In step S306, the write data and the command sequence information are stored into the random access memory222for temporary storage. Thus, the write data Data1and the command sequence information S1are stored into the random access memory222for temporary storage. In step S308, it is determined whether to perform the update of the flash memory202. In the exemplary embodiment shown inFIG. 2, the update of the flash memory202is not performed and steps S302to S308are repeated until the write data Data5and the command sequence information S5are stored into the random access memory222. When it is determined in step S308that it is time to update the flash memory202, step S310is performed to upload the write data Data1. . . Data5and the command sequence information S1. . . S5from the random access memory222onto the run-time write block CB of the flash memory202. After the update of the flash memory202(step S310) is finished, the flow returns to step302for new write data.

Referring toFIG. 2, considering the operational efficiency of the flash memory202, the write data Data4and Data5and the command sequence information S4and S5are uploaded onto the run-time write block CB earlier than the write data Data2and Data3and the command sequence information S2and S3. A sudden power-off event SPO unexpectedly occurs when the write data Data4and Data5and the command sequence information S4and S5have been uploaded onto the run-time write block CB but the write data Data2and Data3and the command sequence information S2and S3have not been uploaded onto the run-time write block CB. The sudden power-off event SPO interrupts step S310. In the power recovery process, a procedure is required to cope with the interrupted step S310.

FIG. 4is a flowchart depicting a power recovery process in accordance with an exemplary embodiment of the disclosure, which is discussed with respect toFIG. 2. In step S402, the run-time write block CB is checked and the command sequence information S1, S4and S5stored therein is obtained. In step S404, it is determined, based on the command sequence information S1, S4and S5, whether any write data has been lost in the update of the flash memory202(e.g., because of the interrupted step S310). The command sequence information S1, S4and S5obtained from the run-time write block CB implies the loss of the write data Data2and Data3, and step S406is performed to abandon the write data Data4and Data5later than the lost data Data2and Data3in the command sequence. After the write data Data4and Data5in the run-time write block CB is abandoned, step S408is performed to build the logical-to-physical mapping information about the run-time write block CB. In the exemplary embodiment ofFIG. 2, the logical-to-physical address mapping information between the write data Data1and the run-time write block CB is established while logical-to-physical address mapping between the write data Data4and Data5and the run-time write block CB is ignored. Conversely, when it is determined in step S404that none of the write data is lost, step S406is bypassed and step S408is performed to build the logical-to-physical address mapping information about the run-time write block CB.

In some exemplary embodiments, each physical page for write data is further allocated for storage of the command sequence information. Referring to the exemplary embodiment ofFIG. 2, the write data Data1and the command sequence information S1are stored in the same physical page, the write data Data4and the command sequence information S4are stored in the same physical page, and the write data Data5and the command sequence information S5are stored in the same physical page.

In some exemplary embodiments, the command sequence information is stored in a plurality of digital bits. During the power recovery process of the data storage device200, a logical operation is performed on the command sequence information contained in the run-time write block CB to identify the write data later in the command sequence than the lost data.

FIG. 5shows an exemplary embodiment of the disclosure and is discussed with respect toFIG. 2. For the write data, 8 bits of each physical page is allocated for the storage of the command sequence information. The lower bit ‘1’ represents the earlier command. The command sequence information S1generated for the write data Data1is represented by “000000001”. The command sequence information S2generated for the write data Data2is represented by “000000010”. The command sequence information S3generated for the write data Data3is represented by “000000100”. The command sequence information S4generated for the write data Data4is represented by “000001000”. The command sequence information S5generated for the write data Data5is represented by “000010000”. As shown, a sudden power-off event SPO occurs during the update of the run-time write block CB. During the power recovery process, the command sequence information “000000001”, “000001000” and “000001000” are obtained from the run-time write block CB in step S402. In step S404, a logical OR calculation is performed on the digital bits “000000001”, “000001000” and “000001000” and the calculation result is “00011001”. The lower bits with logic ‘0’ value show that the write data Data2and Data3are lost data. In step S406, the write data Data4and Data5later than the lost data Data2and Data3in the command sequence is abandoned. The run-time write block CB with the remaining valid data Data1, therefore, is consistent with the command sequence. According to the disclosure, the valid data contained in the run-time write block CB after the power recovery process always complies with the command sequence even though the write data is not uploaded onto the run-time write block CB in the command sequence when considering the operational efficiency.

The invention further involves flash memory control methods, which are not limited to any specific controller architecture. Furthermore, any technique using the aforementioned concept to control a flash memory is within the scope of the invention.