Semiconductor memory device having duty cycle correction circuit and interpolation circuit interpolating clock signal in the semiconductor memory device

A semiconductor memory device having a duty cycle correction circuit and an interpolating circuit interpolating a clock signal in the semiconductor memory device are disclosed. The semiconductor memory device comprises a duty cycle correction circuit, which receives an external clock, corrects the duty cycle of the external clock, and outputs the corrected duty cycle. The duty cycle correction circuit comprises a first delay locked loop that receives the external clock, inverts the external clock, synchronizes the external clock with the inverted external clock, and outputs the synchronized clock; a second delay locked loop that receives the inverted external clock, synchronizes the inverted external clock with the external clock and outputs the synchronized clock; an inverting circuit that inverts the output signal of the first delay locked loop; an interpolation circuit that interpolates the output signal of the inverting circuit with the output signal of the second delay locked loop, and outputs the interpolated signal; and a control circuit that controls the interpolation circuit in response to the clock frequency information of the external clock.

BACKGROUND OF THE INVENTION

This application claims priority to Korean Patent Application No. 2002-53327 filed on Sep. 4, 2002, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

1. Field of the Invention

The present invention relates to a synchronous semiconductor memory device, and more particularly, to a semiconductor memory device having a duty cycle correction circuit correcting the duty cycle of an external clock signal and an interpolation circuit interpolating the clock signal in the semiconductor memory device.

2. Description of the Related Art

The duty cycle of a clock signal is a numerical value representing the ratio of a pulse width with respect to a pulse period of the clock signal. In digital clock applications, it is very important for the duty cycle of a clock signal to be precisely controlled. In synchronous semiconductor memory devices that output data by synchronizing with a clock, when the duty cycle of a clock signal is not precisely controlled distortion of the data can occur. Thus, it is very important to precisely control the duty cycle.

In general, a clock signal with a duty cycle of 50% is mainly used in digital clock applications such as a semiconductor integrated circuit. A duty cycle of 50% means that the high-level and low-level portions of the clock signal are of identical duration. When a clock signal whose duty cycle is not at 50% is input to a duty cycle correction circuit, the duty-cycle correction circuit converts the clock signal whose duty cycle is not at 50% into a clock signal with a duty cycle of 50%.

FIG. 1shows a duty cycle correction circuit1000correcting the duty cycle of an external clock. The duty cycle correction circuit1000shown inFIG. 1includes a delay locked loop110, an interpolation circuit120, and an inverting circuit130.

The delay locked loop110receives an external clock CLK_IN and an output signal of the inverting circuit130, delays the external clock CLK_IN for a predetermined time, and outputs the delayed clock signal. The inverting circuit130inverts the output signal of the delay locked loop110, and outputs the inverted output signal. The interpolation circuit120receives the external clock CLK_IN and the output signal CLK_B of the inverting circuit130, interpolates these signals, and outputs a duty cycle-corrected clock signal CLK_OUT.

FIG. 2shows internal details of the interpolation circuit120from FIG.1. The interpolation circuit120shown inFIG. 2includes a plurality of inverting circuits210,220, and230. The first and second inverting circuits210and220are connected to a common output node N1. The output node N1is an input to the third inverting circuit230. The first inverting circuit210includes a PMOS transistor MP21and a NMOS transistor MN22, and the second inverting circuit220includes a PMOS transistor MP23and a NMOS transistor MN24. The third inverting circuit230receives a signal from the output node N1, and inverts the signal of the output node N1at a predetermined point in time.

If the clock frequency of the external clock CLK_IN changes, the point in time when the third inverting circuit230inverts changes.FIGS. 3A and 3Bshow the relationships between an input signal and an output signal of an inverting circuit according to the clock frequency of an external clock. InFIG. 3A, the external clock CLK_IN has a low frequency, and inFIG. 3B, the external clock CLK_IN has a high frequency. As shown inFIG. 3A, when the external clock CLK_IN has a low frequency, the slope of the signal at the output node N1is large. Thus, the point in time when the external clock CLK_IN is inverted changes from a to b to c, and the output signal at the output node N1changes greatly.

As shown inFIG. 3B, when the external clock CLK_IN has a high frequency, the slope of the signal at the output node N1is small. Thus, the point in time when the external clock CLK_IN is inverted changes from a to b to c, and the output signal at the output node N1does not change greatly. However, when the external clock CLK_IN has a high frequency, since a drop in the speed of the clock signal is slow, the clock signal is not completely swung from a low voltage to a high voltage.

SUMMARY OF THE INVENTION

The present invention provides an interpolation circuit for interpolating a clock signal according to clock frequency information of an external clock.

The present invention also provides a duty cycle correction circuit having an interpolation circuit, and a semiconductor memory device having a duty cycle correction circuit.

According to a first aspect of the present invention, there is provided a semiconductor memory device operating in synchronization with an external clock, comprising a frequency detecting unit that receives the external clock, detects clock frequency information of the external clock, and outputs the detected clock frequency information; and a duty cycle correction circuit that corrects the duty cycle of the external clock in response to the clock frequency information.

Preferably, the duty cycle correction circuit comprises a first delay locked loop that receives the external clock, inverts the external clock, synchronizes the external clock with the inverted external clock, and outputs the synchronized clock; a second delay locked loop that receives the inverted external clock, synchronizes the inverted external clock with the external clock, and outputs the synchronized clock; and an interpolation circuit that interpolates a signal inverting the output signal of the first delay locked loop with the output signal of the second delay locked loop and outputs the interpolated signal. The interpolation circuit comprises a first inverting circuit that receives the signal inverting the output signal of the first delay locked loop, inverts the received signal, and outputs the inverted signal; a second inverting circuit that inverts the output signal of the second delay locked loop and outputs the inverted signal, the output end of the first inverting circuit and the output end of the second inverting circuit connected with each other; a third inverting circuit that receives and inverts the output signal of the first inverting circuit and the output signal of the second inverting circuit, and outputs the inverted signals; and a plurality of capacitors having predetermined capacitances, which are connected between a ground power supply and respective input ends of the first, second, and third inverting circuits. Here, the capacitances of the plurality of capacitors are controlled by the clock frequency of the external clock.

According to a second aspect of the present invention, there is provided a semiconductor memory device operating in synchronization with an external clock, comprising a duty cycle correction circuit that receives the external clock, corrects the duty cycle of the external clock, and outputs the corrected duty cycle. The duty cycle correction circuit comprises a first delay locked loop that receives the external clock, inverts the external clock, synchronizes the external clock with the inverted external clock, and outputs the synchronized clock; a second delay locked loop that receives the inverted external clock, synchronizes the inverted external clock with the external clock and outputs the synchronized clock; an inverting circuit that inverts the output signal of the first delay locked loop; an interpolation circuit that interpolates the output signal of the inverting circuit with the output signal of the second delay locked loop and outputs the interpolated signal; and a control circuit that controls the interpolation circuit in response to the clock frequency information of the external clock. Here, the interpolation circuit is controlled in response to an output signal of the control circuit.

According to a third aspect of the present invention, there is provided a semiconductor memory device operating in synchronization with an external clock, comprising a first delay locked loop that receives the external clock, inverts the external clock, synchronizes the external clock with the inverted external clock, and outputs the synchronized clock; a second delay locked loop that receives the inverted external clock, synchronizes the inverted external clock with the external clock, and outputs the synchronized clock; and an interpolation circuit that interpolates a signal inverting the output signal of the first delay locked loop with the output signal of the second delay locked loop and outputs the interpolated signal. Here, the interpolation circuit is controlled by CAS (column address strobe) latency.

Preferably, the interpolation circuit comprises a first inverting circuit that receives and inverts the signal inverting the output signal of the first delay locked loop, and outputs the inverted signal; a second inverting circuit that inverts the output signal of the second delay locked loop and outputs the inverted signal, the output end of the first inverting circuit and the output end of the second inverting circuit connected with each other; a third inverting circuit that receives the output signal of the first inverting circuit and the output signal of the second inverting circuit, inverts these signals, and outputs the inverted signals; and a plurality of capacitors having predetermined capacitances, connected between a ground power supply and respective input ends of the first, second, and third inverting circuits. Here, the capacitances of the plurality of capacitors are controlled by the CAS latency.

According to a fourth aspect of the present invention, there is provided an interpolation circuit, included in a semiconductor memory device, which interpolates two clock signals whose clock frequencies identify with each other and whose phases are different from each other. The interpolation circuit comprises a first inverting circuit that receives a first clock signal, inverts the first clock signal, and outputs the inverted first clock signal; a second inverting circuit that receives a second clock signal, inverts the second clock signal, and outputs the inverted second clock signal, the output end of the first inverting circuit and the output end of the second inverting circuit connected with each other; a third inverting circuit that receives and inverts the output of the first inverting circuit and the output of the second inverting circuit and outputs the inverted signal; and first, second, and third capacitors having predetermined capacitances, connected between a ground power supply and respective input ends of the first, second, and third inverting circuits. Here, the capacitances of the first, second, and third capacitors are controlled according to the clock frequency.

Preferably, when the clock frequency of the external clock is high, the capacitances of the first, second, and third capacitors are small, and when the clock frequency of the external clock is low, the capacitances of the first, second, and third of capacitors are large.

Preferably, the capacitances of the first, second, and third of capacitors are controlled by CAS latency of the semiconductor memory device. When the CAS latency is high, the capacitances of the first, second, and third capacitors are small, when the CAS latency is low, the capacitances of the first, second, and third of capacitors are large.

DETAILED DESCRIPTION OF THE INVENTION

The present invention will now be described more fully with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. The same reference numerals in different drawings represent the same element.

FIG. 4is a schematic block diagram of a semiconductor memory device4000having a duty cycle correction circuit according to an embodiment of the present invention. The semiconductor memory device4000includes a frequency detecting unit410and a duty cycle correction circuit420.

The frequency detecting unit410receives an external clock CLK_IN, detects clock frequency information of the external clock CLK_IN, and outputs the detected clock frequency information to the duty cycle correction circuit420. The duty cycle correction circuit420corrects the duty cycle of the external clock CLK_IN in response to the clock frequency information and outputs a corrected clock signal CLK_OUT.

The clock frequency information of the external clock CLK_IN is detected in order to correct the duty cycle of the external clock CLK_IN. At this time, in a case where the clock frequency is high, the duty cycle is corrected corresponding to the external clock having the high frequency. In a case where the clock frequency is low, the duty cycle is corrected corresponding to the external clock having the low frequency. Thus, a semiconductor memory device4000in which the duty cycle is precisely corrected can be provided.

FIG. 5shows a semiconductor memory device5000having a duty cycle correction circuit5100according to an embodiment of the present invention in detail.FIG. 6is a timing diagram showing waveforms in respective locations of the duty cycle correction circuit5100shown in FIG.5. The semiconductor memory device5000includes the duty cycle correction circuit5100and a frequency detecting unit5200.

The duty cycle correction circuit5100includes a first delay locked loop500, a second delay locked loop510, and an interpolation circuit520. The duty cycle correction circuit5100may further include a second inverter530for inverting an output signal of the first delay locked loop500. Also, the duty cycle correction circuit5100may include a delaying circuit540for delaying the output signal of the first delay locked loop500for a predetermined time.

The first delay locked loop500includes a first variable delay line501, a first phase detector502, and an input buffer503. The second delay locked loop510includes a second variable delay line511, a second phase detector512, and a first inverter513inverting an external clock CLK_IN.

The input buffer503receives and buffers the external clock CLK_IN and outputs the buffered clock to the first variable delay line501and the second phase detector512. The first variable delay line501delays the output signal of the input buffer503for a predetermined time in response to an output signal of the first phase detector502and outputs a delayed output signal A. The first inverter513receives the external clock CLK_IN, inverts the external clock CLK_IN, and outputs an inverted external clock CLK_INB.

The first phase detector502outputs a signal for controlling the first variable delay line501in response to the inverted external clock CLK_INB and the output signal of the first variable delay line501. The second variable delay line511delays the inverted external clock CLK_INB for a predetermined time in response to an output signal of the second phase detector512and outputs the delayed external clock CLK_INB. The second phase detector512outputs a signal for controlling the second variable delay line511in response to the output signal of the input buffer503and the output signal of the second variable delay line511.

The second inverter530receives and inverts an output signal A of the first variable delay line501and outputs an inverted signal AB. The interpolation circuit520includes first, second and third inverting circuits521,522, and523. The output end of the first inverting circuit521and the output end of the second inverting circuit522are connected with each other. The common output end of the first and second inverting circuits521and522is an input end of the third inverting circuit523. A plurality of capacitors524,525, and526having predetermined capacitances are connected between respective input ends and respective ground power supplies of the first, second and third inverting circuits521,522, and523, respectively. Capacitances of the respective capacitors524,525, and526are controlled by an output signal of the frequency detecting unit5200.

The interpolation circuit520receives and interpolates the inverted signal AB and the output signal B of the second variable delay line511and outputs a interpolated signal C. Here, an output end of the second inverter530is connected to an input end of the first inverting circuit521, and an output end of the second variable delay line511is connected to an input end of the second inverting circuit522.

The delaying circuit540receives the output signal A of the first variable delay line501, delays the output signal A for a predetermined time, and outputs a delayed signal d(A). The delaying circuit540delays the output signal of the first delay locked loop500by the sum of a delay amount of the interpolation circuit520and a delay amount of the second inverter530, in order to synchronize the two output signals d(A) and C of the duty cycle correction circuit5100. In a case where the delay amount of the interpolation circuit520is great, another delaying circuit may be added to the delaying circuit540to compensate for the great delay amount.

Operations of the semiconductor memory device5000and the interpolation circuit520according to the present invention now will be explained with reference toFIGS. 5 and 6. If the first delay locked loop500receives an external clock CLK_IN whose duty-cycle is not at 50%, the first delay locked loop500outputs the output signal A, and the second delay locked loop510receives the inverted external clock CLK_INB and outputs the output signal B.

Here, the first delay locked loop500outputs the output signal A obtained by synchronizing the external clock CLK_IN with the inverted external clock CLK_INB. The second delay locked loop510outputs the output signal B obtained by synchronizing the inverted external clock CLK_INB with the external clock CLK_IN.

The second inverter530inverts the output signal A of the first delay locked loop500, and the interpolation circuit520interpolates the inverted output signal AB of the output signal A and the output signal B of the second delay locked loop510, and outputs the output signal C. Supposing that the interpolation circuit520and the second inverter530do not have the delays, the duty cycle corrected clocks, as shown inFIG. 6, are the output signal A and the output signal C. That is, the duty cycles of the signal A has a constant value and the signal C also has another constant value.

The frequency detecting unit5200receives the external clock CLK_IN and detects and outputs clock frequency information of the external clock CLK_IN. The output signal of the frequency detecting unit5200adjusts the capacitances of the first, second, and third capacitors524,525, and526of the interpolation circuit520.

When the external clock CLK_IN has a high frequency, the capacitances of the capacitors524,525, and526are small in order to reduce the delay of the interpolation circuit520. When the external clock CLK_IN has a low frequency, the capacitances of capacitors524,525, and526are large in order increase the delay of the interpolation circuit520.

As described above, the semiconductor memory device in which the duty cycle is precisely corrected can be provided by adjusting the capacitance and the delay amount of the interpolation circuit520in response to the clock frequency information of the external clock.

FIG. 7shows the structure of the frequency detecting unit5200shown in FIG.5. The frequency detecting unit5200includes a frequency detecting circuit710, an analog-to-digital converter (ADC)720, and a register730.

The frequency detecting circuit710receives the external clock CLK_IN and detects the clock frequency of the external clock CLK_IN. The ADC720receives an output signal of the frequency detecting circuit710, converts the output signal into a digital signal, and outputs the digital signal. The register730receives the output signal of the ADC720and stores the output signal of the ADC720.

The digital signal stored in the register730controls the capacitances of the plurality of capacitors524,525, and526of the interpolation circuit520ofFIG. 5so that the interpolation circuit520can operate precisely.

FIG. 8is a table showing the relationship between CAS (column address strobe) latency and the clock frequency of a semiconductor memory device. As shown inFIG. 8, if the CAS latency increases, the operation frequency of an external clock is high. The CAS latency indirectly indicates operation frequency information of the external clock. Thus, the duty cycle correction circuit and the interpolation circuit, which are controlled by the CAS latency, can be embodied without using the frequency detecting unit.

FIG. 9shows a semiconductor memory device, which is controlled by CAS latency and has a duty cycle correction circuit, according to an embodiment of the present invention. The semiconductor memory device9000ofFIG. 9includes a first delay locked loop900, a second delay locked loop910, and an interpolation circuit920. Preferably, the semiconductor memory device9000further includes a second inverter930inverting an output signal A of the first delay locked loop900, and a delaying circuit940delaying the output signal A of the first delay locked loop900for a predetermined time.

The first delay locked loop900includes a first variable delay line901, a first phase detector902, and an input buffer903. The second delay locked loop910includes a second variable delay line911, a second phase detector912, and a first inverter913inverting an external clock CLK_IN. The first delay locked loop900receives the external clock CLK_IN, synchronizes the external clock CLK_IN with the inverted external clock CLK_INB, and outputs the synchronized external clock. The second delay locked loop910receives the inverted external clock CLK_INB, synchronizes the inverted external clock CLK_INB with the external clock CLK_IN, and outputs the synchronized external clock.

The input buffer903receives and buffers the external clock CLK_IN and outputs a buffered clock to the first variable delay line901and the second phase detector912. The first variable delay line901delays the output signal of the input buffer903for a time in response to the output signal of the first phase detector902and outputs the delayed output signal of the input buffer903. The first inverter913receives the external clock CLK_IN, inverts the external clock CLK_IN, and outputs an inverted external clock CLK_INB.

The first phase detector902outputs a signal for controlling the first variable delay line901in response to the inverted external clock CLK_INB and the output signal of the first variable delay line901. The second variable delay line911delays the inverted external clock CLK_INB for a predetermined time in response to an output signal of the second phase detector912and a delayed inverted external clock at B. The second phase detector912outputs a signal for controlling the second variable delay line911in response to the output signal of the input buffer903and the output signal of the second variable delay line911.

The second inverter930receives and inverts an output signal A of the first variable delay line901and outputs an inverted signal AB. The interpolation circuit920includes first, second, and third inverting circuits921,922, and923. The output end of the first inverting circuit921and the output end of the second inverting circuit922are connected with each other. The common output end of the first and second inverting circuits921and922is an input end of the third inverting circuit923. Capacitors924,925, and926having predetermined capacitances are connected between respective input ends of the first, second and third inverting circuits921,922, and923and a ground power supply. Capacitances of the respective capacitors924,925, and926are controlled by CAS latency of the semiconductor memory device9000.

The delaying circuit940receives the output signal A of the first variable delay line901, delays the output signal A for a predetermined time, and outputs a delayed signal d(A). The delaying circuit940delays the output signal of the first delay locked loop900by the sum of the delay amount of the interpolation circuit920and the delay amount of the second inverter930, in order to synchronize the two output signals d(A) and C of a duty cycle correction circuit. In a case where the delay amount of the interpolation circuit920is great, another delaying circuit may be added to the delaying circuit940to compensate for the great delay amount.

The interpolation circuit920of the semiconductor memory device9000responds to the value of the CAS latency corresponding to the clock frequency of the external clock CLK_IN and adjusts the capacitances of the capacitors924,925, and926of the interpolation circuit920. For a case where the CAS latency is large, the capacitances of the capacitors924,925, and926are small in order to reduce the delay amount of the interpolation circuit920. When the CAS latency is small, the capacitances of the capacitors924,925, and926are high in order to increase the delay amount of the interpolation circuit920.

The semiconductor memory device9000precisely interpolates the external clock and precisely corrects the duty cycle by adjusting the capacitance or the delay amount of the interpolation circuit920in response to the CAS latency.

As described above, semiconductor memory device embodiments according to the present invention can precisely correct the duty cycle according to the clock frequency of the external clock or the CAS latency of the semiconductor memory device by responding to the clock frequency information of the external clock or the CAS latency and adjusting the capacitance or the delay amount of the interpolation circuit.

Further, the interpolation circuit according to the present invention can correctly correct the clock signal according to the clock frequency of the external clock or the CAS latency of the semiconductor memory device by responding to the clock frequency information of the external clock or the CAS latency and adjusting the capacitance or the delay amount of the interpolation circuit.