Method of forming a semiconductor structure comprising a field effect transistor having a stressed channel region

A method of forming a semiconductor structure comprises providing a semiconductor substrate comprising a first transistor element and a second transistor element. The first transistor element comprises at least one first amorphous region and the second transistor element comprises at least one second amorphous region. A stress-creating layer is formed over the first transistor element. The stress-creating layer does not cover the second transistor element. A first annealing process is performed. The first annealing process is adapted to re-crystallize the first amorphous region and the second amorphous region. After the first annealing process, a second annealing process is performed. The stress-creating layer remains on the semiconductor substrate during the second annealing process.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present disclosure generally relates to the formation of integrated circuits, and, more particularly, to the formation of semiconductor structures comprising field effect transistors having stressed channel regions.

2. Description of the Related Art

Integrated circuits comprise a large number of individual circuit elements, e.g., transistors, capacitors and resistors. These elements are connected internally to form complex circuits, such as memory devices, logic devices and microprocessors. The performance of integrated circuits can be improved by increasing the number of functional elements per circuit in order to increase their functionality and/or by increasing the speed of operation of the circuit elements. A reduction of feature sizes allows the formation of a greater number of circuit elements on the same area, hence allowing an extension of the functionality of the circuit, and also reduces signal propagation delays, thus making an increase of the speed of operation of circuit elements possible.

Field effect transistors are used as switching elements in integrated circuits. They provide a means to control a current flowing through a channel region located between a source region and a drain region. The source region and the drain region are highly doped. In N-type transistors, the source and drain regions are doped with an N-type dopant. Conversely, in P-type transistors, the source and drain regions are doped with a P-type dopant. The doping of the channel region is inverse to the doping of the source region and the drain region. The conductivity of the channel region is controlled by a gate voltage applied to a gate electrode formed above the channel region and separated therefrom by a thin insulating layer. Depending on the gate voltage, the channel region may be switched between a conductive “on” state and a substantially non-conductive “off” state.

When reducing the size of field effect transistors, it is important to maintain a high conductivity of the channel region in the “on” state. The conductivity of the channel region in the “on” state depends on the dopant concentration in the channel region, the mobility of the charge carriers, the extension of the channel region in the width direction of the transistor and on the distance between the source region and the drain region, which is commonly denoted as “channel length.” While a reduction of the width of the channel region leads to a decrease of the channel conductivity, a reduction of the channel length enhances the channel conductivity. An increase of the charge carrier mobility leads to an increase of the channel conductivity.

As feature sizes are reduced, the extension of the channel region in the width direction is also reduced. A reduction of the channel length entails a plurality of issues associated therewith. First, advanced techniques of photolithography and etching have to be provided in order to reliably and reproducibly create transistors having short channel lengths. Moreover, highly sophisticated dopant profiles, in the vertical direction as well as in the lateral direction, are required in the source region and in the drain region in order to provide a low sheet resistivity and a low contact resistivity in combination with a desired channel controllability.

In view of the problems associated with a further reduction of the channel length, it has been proposed to also enhance the performance of field effect transistors by increasing the charge carrier mobility in the channel region. In principle, at least two approaches may be used to increase the charge carrier mobility.

First, the dopant concentration in the channel region may be reduced. Thus, the probability of scattering events of charge carriers in the channel region is reduced, which leads to an increase of the conductivity of the channel region. Reducing the dopant concentration in the channel region, however, significantly affects the threshold voltage of the transistor device. This makes the reduction of dopant concentration a less attractive approach.

Second, the lattice structure in the channel region may be modified by creating tensile or compressive stress. This leads to a modified mobility of electrons and holes, respectively. Depending on the magnitude of the stress, a compressive stress may significantly increase the mobility of holes in a silicon layer. The mobility of electrons may be increased by providing a silicon layer having a tensile stress.

A method of forming a field effect transistor wherein the channel region is formed in stressed silicon will be described in the following with reference toFIGS. 1a-1b.FIG. 1ashows a schematic cross-sectional view of a semiconductor structure100in a first stage of a manufacturing process according to the state of the art.

The semiconductor structure100comprises a substrate101. The substrate101comprises a first transistor element102and a second transistor element103. The first transistor element102comprises an active region105formed in the substrate101. A gate electrode110is formed over a channel region123in the substrate101and separated therefrom by a gate insulation layer121. The gate electrode110is flanked by inner sidewall spacers109,111and outer sidewall spacers108,112. In the substrate101, a source region107and a drain region113are formed adjacent the gate electrode101.

Similarly, the second transistor element103comprises an active region106, a gate electrode117, a gate insulation layer122, inner sidewall spacers116,118, outer sidewall spacers115,119, a source region114, a drain region120and a channel region124. A trench isolation structure104provides electrical insulation between the first transistor element102and the second transistor element103. Additionally, the trench isolation structure104may provide electrical insulation between the transistor elements102,103and other electrical elements in the semiconductor structure100.

The first transistor element102and the second transistor element103, as well as the trench isolation structure104, may be formed by means of well-known methods of photo-lithography, etching, deposition, ion implantation and oxidation. In particular, the active regions105,106, the source regions107,114and the drain regions113,120may be formed by implanting ions of dopant materials into the semiconductor structure100.

In some examples of methods of forming a semiconductor structure according to the state of the art, the first transistor element102can be an N-type transistor and the second transistor element103can be a P-type transistor. In such methods, the active region105may comprise a P-type dopant and the active region106may comprise an N-type dopant. The source region107and the drain region113comprise an N-type dopant. The source region114and the drain region120comprise a P-type dopant. In ion implantation processes, one of the field effect transistor elements102,103may be covered with a mask which may, for example, comprise a photoresist, while the other of the field effect transistor elements102,103is irradiated with ions. Thus, an undesirable introduction of dopants which are not in line with the type of the transistor elements102,103may be avoided.

In the formation of the source regions107,114and the drain regions113,120, a plurality of implantation processes may be performed for each of the transistor elements102,103. First, ion implantation processes may be formed before the formation of the inner sidewall spacers109,111,116,118and the outer sidewall spacers108,112,115,119. Thereafter, the inner sidewall spacers109,111,116,118can be formed by means of known methods comprising an isotropic deposition of a material layer and an anisotropic etching process.

After the formation of the inner sidewall spacers109,111,116,118, second ion implantation processes can be performed. In the second ion implantation processes, the inner sidewall spacers109,111,116,118absorb ions impinging in the vicinity of the gate electrodes110,117. Hence, in the second ion implantation process, substantially no dopants are introduced in the vicinity of the gate electrodes110,117. Thus, dopants may be selectively introduced into portions of the source regions107,114and the drain regions113,120having a distance from the gate electrodes110,117which is greater than a thickness of the inner sidewall spacers109,111,116,118.

Thereafter, the outer sidewall spacers108,112,115,119are formed and third ion implantation processes are performed. In the third ion implantation processes, both the inner sidewall spacers109,111,116,118and the outer sidewall spacers108,112,115,119absorb ions impinging on the semiconductor structure100. Thus, dopants may be selectively introduced into portions of the source regions107,114and the drain regions113,120having a distance from the gate electrodes110,117which is greater than a sum of the thickness of the inner sidewall spacers109,111,116,118and a thickness of the outer sidewall spacers108,112,115,119.

Hence, dopant profiles in the source regions107,113and the drain regions114,120may be controlled by varying a thickness of the inner sidewall spacers109,111,116,118, a thickness of the outer sidewall spacers108,112,115,119and ion doses applied in the first, second and third ion implantation processes. Thus, highly sophisticated dopant profiles may be created in the first transistor element102and the second transistor element103.

In the ion implantation processes performed in the formation of the source regions107,114and the drain regions113,120, atoms of the substrate101may be pushed away from their sites in the crystal lattice of the material of the substrate101. In modern methods of manufacturing a semiconductor structure, ion doses applied in the formation of the source regions107,114and the drain regions113,120may be sufficient to destroy the crystalline order of the material of the substrate101, such that an amorphous material is obtained in the source regions107,114and the drain regions113,120.

FIG. 1bshows a schematic cross-sectional view of the semiconductor structure100in a later stage of the manufacturing process according to the state of the art. A liner layer125and a stress-creating layer126are formed over the first transistor element102and the second transistor element103. The stress-creating layer126may comprise a relatively hard material such as silicon nitride and the liner layer125may comprise silicon dioxide. In the formation of the liner layer125and the stress-creating layer126, methods of deposition well known to persons skilled in the art, such as chemical vapor deposition and/or plasma enhanced chemical vapor deposition, may be employed.

A portion of the stress-creating layer126covering the second transistor element103may be removed. To this end, a mask comprising a photoresist covering the first transistor element102may be formed. Thereafter, an etching process adapted to selectively remove the material of the stress-creating layer126can be performed. An etchant used in the etching process may be adapted such that the liner layer125is substantially not affected by the etching process. Thus, the etching process may be stopped as soon as the stress-creating layer126is removed. Portions of the stress-creating layer126over the first transistor element102are protected from being etched by the mask and remain on the surface of the semiconductor structure100. After the etching process, the mask can be removed by means of a known resist strip process.

An annealing process is performed. In the annealing process, the semiconductor structure100is exposed to an elevated temperature for a predetermined time. In the annealing process, amorphous material in the source regions107,114and the drain regions113,120re-crystallizes. In the re-crystallization process, atoms in the source regions107,114and the drain regions113,120adapt to the crystalline order of portions of the substrate101below the source regions107,114and the drain regions113,120. Thus, a crystalline material may be obtained in the source regions107,114and the drain regions113,120.

Amorphous semiconductor materials may have a lower density than crystalline semiconductor material. In particular, a density of amorphous silicon is lower than a density of crystalline silicon. Therefore, the material of the source regions107,114and the drain regions113,120tends to reduce its volume in the re-crystallization process.

In the first transistor element102, the stress-creating layer126, which, as detailed above, may comprise a relatively hard material such as silicon nitride, may prevent a reduction of the volume of the material in the source region107and the drain region113, since the material of the source region107and the drain region113adheres to the stress-creating layer126, and the hardness of the stress-creating layer126may prevent a deformation of the stress-creating layer126.

Therefore, the atoms in the source region107and the drain region113may arrange at a distance which is greater than the bulk lattice constant of the material of the substrate101. Thus, an intrinsic tensile stress can be created in the source region107, the drain region113and in a channel region121of the first transistor element102.

In the second transistor element103, the volume of the material of the source region114and the drain region120may change during the annealing process. Hence, the source region114, the drain regions120, as well as a channel region122of the second transistor element103, may be substantially unstressed.

The annealing process may also be employed in order to activate the dopant materials in the source regions107,114and the drain regions113,120such that they may act as electron donors or acceptors.

After the annealing process, the stress-creating layer126and the liner layer125may be removed by means of an etching process. The intrinsic stress in the source region107, the drain region113and the channel region123of the first transistor element102, however, may be maintained after the removal of the stress-creating layer126. This phenomenon is known to persons skilled in the art as “stress memorization.”

A problem of the above method of forming a semiconductor structure is that, in the annealing process, dopant materials in the source regions107,114and the drain regions113,120may diffuse. Hence, sophisticated dopant profiles created by means of the first to third ion implantation process may be blurred.

SUMMARY OF THE INVENTION

According to one illustrative embodiment disclosed herein, a method of forming a semiconductor structure comprises providing a semiconductor substrate comprising a first transistor element and a second transistor element. The first transistor element comprises at least one first amorphous region and the second transistor element comprises at least one second amorphous region. A stress-creating layer is formed over the first transistor element. The stress-creating layer does not cover the second transistor element. A first annealing process is performed. The first annealing process is adapted to re-crystallize the first amorphous region and the second amorphous region. After the first annealing process, a second annealing process is performed. The stress-creating layer remains on the semiconductor substrate during the second annealing process.

According to another illustrative embodiment disclosed herein, a method of forming a semiconductor structure comprises providing a semiconductor substrate comprising a first transistor element and a second transistor element. A stress-creating layer is formed over the first transistor element. The stress-creating layer does not cover the second transistor element. An annealing process is performed. The annealing process comprises irradiating the semiconductor substrate with laser radiation. The stress-creating layer remains on the semiconductor substrate during the annealing process.

DETAILED DESCRIPTION OF THE INVENTION

In some embodiments, a stress-creating layer is formed over a first transistor element provided in a semiconductor substrate. A second transistor element provided in the semiconductor substrate is not covered by the layer of the material. A first and a second annealing process are performed, wherein the layer of the material remains on the semiconductor substrate during both annealing processes.

While the first annealing process can be adapted to induce a solid phase epitaxial re-growth of amorphous regions in the first and the second transistor element, the second annealing process can be adapted to activate dopant materials in the transistor element. In some embodiments, the second annealing process can comprise irradiating the semiconductor substrate with laser radiation. Thus, portions of the semiconductor substrate in the vicinity of a substrate thereof may be exposed to relatively high temperatures for a relatively short time. Hence, dopants may be activated, while the short duration of the second annealing process may substantially prevent or at least reduce a diffusion of dopant atoms. The presence of the layer of the material on the semiconductor substrate during the second annealing process reduces a relaxation of an intrinsic stress in a channel region of the first transistor element during the second annealing process.

FIG. 2ashows a schematic cross-sectional view of a semiconductor structure200in a first stage of a manufacturing process according to an illustrative embodiment disclosed herein. The semiconductor structure200comprises a substrate201. The substrate201may comprise a semiconductor material, for example, silicon. While, in some embodiments of the present invention, the substrate201can be a bulk silicon substrate, in other embodiments, the substrate201can be a silicon-on-insulator (SOI) substrate.

In and on the substrate201, a first transistor element202and a second transistor element203are formed. A trench isolation structure204electrically isolates the first transistor element202and the second transistor element203from each other and from other circuit elements in the semiconductor structure200.

The first transistor element202comprises an active region205and a gate electrode210. A gate insulation layer221separates the gate electrode210from a channel region223located in the substrate201below the gate electrode210. The gate electrode210is flanked by inner sidewall spacers209,211and outer sidewall spacers208,212. In the substrate201, a source region207and a drain region213are formed adjacent the gate electrode210.

Similar to the first transistor element202, the second transistor element203comprises an active region206, a gate electrode217, a gate insulation layer222, a channel region224, inner sidewall spacers216,218, outer sidewall spacers215,219, a source region214and a drain region220.

The first transistor element202and the second transistor element203can be formed by means of known methods of photolithography, etching, deposition, oxidation and ion implantation. In particular, advanced known methods of ion implantation may be employed in order to provide highly sophisticated dopant profiles in the source regions207,214and the drain regions213,220, similar to those employed in the method of manufacturing a semiconductor structure according to the state of the art described above with reference toFIGS. 1a-1b. In some embodiments, the first transistor element202can be an N-type transistor and the second transistor element203can be a P-type transistor. In other embodiments, the first transistor element202can be a P-type transistor and the second transistor element203can be an N-type transistor.

The first transistor element202may further comprise a source-side amorphous region230and a drain-side amorphous region231. Similarly, the second transistor element203may comprise a source-side amorphous region232and a drain-side amorphous region233. In some embodiments, the amorphous regions230,231,232,233may be formed prior to the formation of the source regions207,214and the drain regions213,220.

To this end, the substrate201can be irradiated with an ion beam (not shown). The ion beam comprises ions of a non-doping element which do not contribute to the number of charge carriers in the substrate201material when they are incorporated into its crystal lattice. The non-doping element can be a noble gas, such as argon (Ar), xenon (Xe) or krypton (Kr). Typical implant energies and doses for the above-identified non-doping elements are in the range of approximately 30-600 keV and approximately 5×1014-1017ions/cm2.

In other embodiments, the non-doping element can be an element of the fourth group of the periodic table of elements, e.g., silicon (Si) or germanium (Ge), which are iso-electronic to a silicon substrate. The ions push atoms in the substrate201away from their sites in the crystal lattice. Ion energy and ion flux of the ion beam and the time of exposure of the substrate201to the ion beam are adapted such that the long range order, and mostly the short range order, of the crystal lattice is lost and the material becomes amorphous.

In other embodiments, the amorphous regions230,231,232,233may be formed during the formation of the source regions207,214and the drain regions213,220. In such embodiments, implant energies and doses applied in the formation of the source regions207,214and the drain regions213,220may be adapted such that the long range order, and mostly the short range order, of the material of the substrate201in the source regions207,214and the drain regions213,220is lost and amorphous material is obtained.

Amorphous materials may have a lower density than crystalline materials. For example, amorphous silicon may have a lower density than crystalline silicon. Hence, a volume of the portions of the semiconductor substrate201in which the amorphous regions230,231,232,233are formed may increase during the amorphization process.

A liner layer225and a stress-creating layer226are formed over the substrate201. In some embodiments, the liner layer225may comprise silicon dioxide and the stress-creating layer226may comprise silicon nitride. In other embodiments, the liner layer225may comprise silicon nitride and the stress-creating layer226may comprise silicon dioxide. In still further embodiments, at least one of the liner layer225and the stress-creating layer226may comprise silicon oxynitride. While, in some embodiments, the stress-creating layer226may be substantially unstressed, in other embodiments, the stress-creating layer226may comprise a tensile or compressive intrinsic stress.

Both the liner layer225and the stress-creating layer226can be formed by means of plasma enhanced chemical vapor deposition. As persons skilled in the art know, in plasma enhanced chemical vapor deposition, the semiconductor structure200is provided in a reactor vessel. A reactant gas is supplied to the reactor vessel. The reactant gas comprises chemical compounds which may react chemically with each other. In the chemical reaction, the material to be deposited is created. A radio-frequency alternating voltage and, optionally, a DC or low-frequency AC bias voltage, may be applied between a first electrode provided in the reactor vessel and the semiconductor structure200or a second electrode located in the vicinity of the semiconductor structure200. The radio-frequency alternating voltage and the bias voltage create a glow discharge in the reactant gas. In the glow discharge, reactive species, such as ions, atoms or radicals, are generated from the reactant gas. Thus, relatively high reaction rates may be obtained at moderate temperatures, which may help reduce the thermal budget of the semiconductor structure200.

Properties of the stress-creating layer226, in particular an intrinsic stress thereof, may be controlled by varying parameters of the plasma enhanced chemical vapor deposition process, such as temperature and pressure of the reactant gas, as well as power and frequency of the radio-frequency alternating voltage and the bias voltage. Parameter values which allow obtaining a stress-creating layer226having substantially no intrinsic stress or a stress-creating layer having a tensile or compressive intrinsic stress are known to persons skilled in the art or may be determined by means of routine experimentation.

A portion of the stress-creating layer226over the second transistor element203is removed. To this end, a mask (not shown) comprising a photoresist may be formed over the first transistor element202by means of well-known methods of photolithography. Thereafter, an etching process, for example a dry etching process, may be performed. An etchant used in the etching process may be adapted to etch the material of the stress-creating layer226, leaving the material of the liner layer225substantially intact. Hence, the liner layer225may act as an etch stop layer, protecting the second transistor element203from being affected by the etchant. The mask may be removed after the etching process. After the etching process, the stress-creating layer226covers the first transistor element202, but not the second transistor element203.

A first annealing process may be performed. The first annealing process may be adapted to induce a re-crystallization of the material in the amorphous regions230,231,232,233. In some embodiments, the first annealing process may be a rapid thermal annealing process. In rapid thermal annealing, the semiconductor structure200is exposed to an elevated temperature for a relatively short time. In some embodiments, the rapid thermal annealing process may have a duration of about 30 seconds or less. In some embodiments, the rapid thermal annealing process may have a duration of about 1 second or less. As persons skilled in the art know, rapid thermal annealing processes wherein the semiconductor structure200is exposed to the elevated temperature for less than about 1 second are sometimes denoted as “spike annealing.” Rapid thermal annealing may be performed by irradiating the semiconductor structure200with electromagnetic radiation which may, for example, comprise light generated by means of one or more lamps.

In other embodiments, the first annealing process may comprise introducing the semiconductor structure200into an oven heated to an elevated temperature. A temperature to which the semiconductor structure200is heated in the annealing process can be adapted such that a re-crystallization of the material of the amorphous regions230,231,232,233occurs. The temperature applied in the first annealing process may be adapted to induce solid phase epitaxial re-growth of the material in the amorphous regions230,231,232,233, wherein the material of the amorphous regions230,231,232,233passes into the crystalline state without there being an intermediary liquid phase. In embodiments wherein the substrate201comprises silicon, the first annealing process may be performed at a temperature of about 500° C. or more.

The re-crystallization of the material in the amorphous regions230,231,232,233may occur at temperatures which are lower than a temperature required in order to activate dopants introduced into the source regions207,214, and the drain regions213,220. For example, in embodiments wherein the substrate201comprises silicon, a full activation of dopants may occur at temperatures of about 800-1000° C. or more, while solid phase epitaxial re-growth may occur at temperatures of about 500° C. or more. In some embodiments, the first annealing process may be performed at a temperature less than about 800° C., at a temperature less than about 700° C. or at a temperature less than about 600° C. More specifically, the first annealing process may be performed at a temperature in a range from about 500-800° C., at a temperature in a range from about 500-700° C. or at a temperature in a range from about 500-600° C. Advantageously, performing the first annealing process at a relatively low temperature may help reduce a diffusion of dopant atoms in the source regions207,214and in the drain regions213,220. Hence, dopant profiles created in the source regions207,214and in the drain regions213,220by means of ion implantation may be substantially maintained.

In other embodiments, the first annealing process may be performed at a temperature at which an activation of dopants in the source regions207,214and in the drain regions213,220may occur.

In the fist annealing process, a density of the material in the amorphous regions230,231232,233may increase. In the second transistor element203, the material in the amorphous regions232,233may, without restraint, substantially shrink in the re-crystallization process. Hence, the material in the amorphous regions232,233may remain substantially unstressed.

In the first transistor element202, the presence of the stress-creating layer226may have an influence on the shrinkage of the material in the amorphous region230,231. In particular, similar to the method of forming a semiconductor structure described above with reference toFIGS. 1a-1b, the stress-creating layer226may prevent or reduce a reduction of the volume of the material in the amorphous regions230,231, since the material of the amorphous regions230,231adheres to the stress-creating layer226, and a stiffness of the stress-creating layer226may prevent or reduce a deformation of the stress-creating layer226.

Hence, atoms of the material of the substrate201may arrange at a distance which is greater than the lattice constant of the material of the substrate201in a bulk crystal. Thus, an intrinsic tensile stress may be created in the source region207and the drain region213. The intrinsic tensile stress of the source region207and the drain region213may have an influence on portions of the substrate201in the vicinity of the source region207and the drain region213, in particular on the channel region223. Thus, a tensile stress may be created in the channel region223. The tensile stress may be employed to increase the mobility of electrons in the channel region223. This can help to improve the performance of the first transistor element202, in particular in embodiments wherein the first transistor element202is an N-type transistor.

The intrinsic stress created in the source region207and the drain region213, as well as the stress created in the channel region223of the first transistor element202, may be influenced by an intrinsic stress of the stress-creating layer226. As detailed above, an intrinsic tensile or compressive stress of the stress-creating layer226may be controlled by varying parameters of a deposition process employed in the formation of the stress-creating layer226. While a tensile stress of the stress-creating layer226may enhance the tensile stress created in the source region207, the drain region213and the channel region223, a compressive stress of the stress-creating layer226can reduce the tensile stress created in the source region207, the drain region213and the channel region223or may even lead to a formation of a compressive stress in these regions. A compressive stress in the channel region223may enhance the mobility of holes. This may help to improve the performance of the first transistor element202, in particular in embodiments wherein the first transistor element202comprises a P-type transistor.

FIG. 2bshows a schematic cross-sectional view of the semiconductor structure200in a later stage of the manufacturing process. After the first annealing process, a second annealing process is performed. The stress-creating layer226may remain on the substrate201during the second annealing process. The second annealing process may comprise irradiating the semiconductor structure200with laser radiation, as indicated by arrows227inFIG. 2b.

In some embodiments, an absorption layer228may be formed over the semiconductor structure200before the second annealing process. A material of the absorption layer228and a wavelength of the laser radiation227are adapted such that the laser radiation227is strongly absorbed in the absorption layer228. In some embodiments, the absorption layer228may comprise silicon. As persons skilled in the art know, silicon has a relatively high absorption coefficient for light having wavelengths in the ultraviolet range. In other embodiments, the absorption layer228may comprise carbon, for example in the form of diamond-like carbon having a relatively high absorption coefficient for light having wave-lengths in the visual or ultraviolet range. Other materials may be employed as well.

The laser radiation227may be substantially absorbed in the absorption layer228. Thus, the absorption layer228is heated to a relatively high temperature. The heat of the absorption layer228is then transmitted to the substrate201, in particular to the source regions207,214and the drain regions213,220, by heat conduction through the stress-creating layer226and the liner layer225. Silicon nitride has a relatively high heat conductance. Hence, in embodiments wherein the stress-creating layer226comprises silicon nitride, heat generated in portions of the absorption layer228over the first transistor element202may be efficiently transferred to the source region207and the drain region213. Hence, potential non-uniformities of the heating of the semiconductor structure200which might be caused by the presence of the stress-creating layer226may be substantially avoided or at least reduced.

In other embodiments, the absorption layer228may be omitted. In such embodiments, properties of the stress-creating layer226and the wavelength of the laser radiation227may be adapted such that a relatively large fraction of the laser radiation227is transmitted through the stress-creating layer226. The transmission of the laser radiation227through the stress-creating layer226may be influenced both by an absorption of the laser radiation227in the stress-creating layer226and by a reflection of the laser radiation227by the stress-creating layer226.

The absorption of the laser radiation227in the stress-creating layer226may be controlled by an adaptation of the wavelength of the laser radiation and the material composition of the stress-creating layer226. For example, the stress-creating layer226, when comprising silicon dioxide and/or silicon oxynitride, may have a low absorption coefficient for radiation in the visual and near ultraviolet wavelength range.

The reflection of light by the stress-creating layer226can be controlled by adapting a thickness of the stress-creating layer226such that a predetermined phase difference is introduced between laser radiation227reflected at a surface of the stress-creating layer226and laser radiation227reflected at an interface between the stress-creating layer226and the liner layer225. Thus, an interference occurs between the laser radiation227reflected at the surface of the stress-creating layer226and the laser radiation227reflected at the interface between the stress-creating layer226and the liner layer225. In some embodiments, the thickness of the stress-creating layer226can be adapted such that destructive interference is obtained. Thus, a reflection of the laser radiation227may be significantly reduced.

A reflection of the laser radiation may also occur at a portion of the liner layer225exposed over the second transistor element203. In some embodiments, the thickness of the stress-creating layer226may be adapted such that a reflectivity of the stress-creating layer226formed over the first transistor element202is substantially equal to a reflectivity of the portion of the liner layer225formed over the second transistor element203. Hence, an amount of energy introduced by the laser radiation227into the first transistor element202may be made substantially equal to an amount of energy introduced into the second transistor element203.

An intensity of the laser radiation227provided in the second annealing process may be adapted such that portions of the substrate201at the surface thereof, in particular the source regions207,214and the drain regions213,220, are heated to a predetermined temperature. In some embodiments, the second annealing process may be adapted such that a temperature sufficient for the activation of dopants in the source regions207,214and in the drain regions213,220is obtained. For example, the second annealing process can be adapted such that a temperature greater than about 800° C., in particular a temperature greater than about 1000° C., is obtained. A duration of the second annealing process may be adapted such that a diffusion of dopants in the source regions207,214and the drain regions213,220may be substantially avoided. For example, the duration may be less than approximately 1 ms.

In other embodiments, the second annealing process may comprise a rapid thermal annealing instead of the irradiation of the semiconductor structure200with the laser radiation227or in addition to the irradiation of the semiconductor structure200with the laser radiation227.

Due to the presence of the stress-creating layer226on the first transistor element202, a relaxation of the intrinsic stress created in the source region207, the drain region213and the channel region223during the first annealing process may be substantially avoided. In some embodiments, the intrinsic stress in the source region207, the drain region213and the channel region223may even be enhanced in the second annealing process, since the second annealing process may lead to a healing of lattice defects in the source region207and the drain region213. Since the presence of lattice defects may lead to a reduction of the intrinsic stress, the healing of such lattice defects may increase the intrinsic stress.

After the second annealing process, the absorption layer228, the stress-creating layer226and the liner layer225may be removed. To this end, etching processes well known to persons skilled in the art may be employed. For example, known wet etch processes may be used. The intrinsic stress created in the source region207, the drain region213and the channel region223may be maintained at least partially after the removal of the stress-creating layer226.

Thereafter, silicide regions which may, for example, comprise a cobalt silicide and/or a nickel silicide may be formed in the source regions207,214and the drain regions213,220. As persons skilled in the art know, to this end, a refractory metal such as cobalt and/or nickel may be deposited over the semiconductor structure200. Thereafter, a third annealing process may be performed in order to initiate a chemical reaction between the refractory metal and the silicon in the source regions207,214and the drain regions213,220. The third annealing process may be performed at a temperature of less than about 800° C. This may help to avoid a relaxation of the intrinsic stress in the source region207, the drain region213and the channel region223of the first transistor element202during the third annealing process.

The subject matter disclosed herein is not restricted to embodiments wherein a first and a second annealing process are performed. In other embodiments, the first annealing process may be omitted. In such embodiments, a single annealing process which comprises irradiating the semiconductor structure200with laser radiation, similar to the second annealing process described above with reference toFIG. 2b, may be performed. This annealing process may be adapted to both induce a re-crystallization of the material in the amorphous regions230,231and to activate dopants in the source regions207,214and in the drain regions213,220.