Method of manufacturing semiconductor device

In one embodiment, a method of manufacturing a semiconductor device includes forming a structure in which first to N-th insulating layers and first to N-th metal layers are alternately provided on a substrate where N is an integer of two or more. The method further includes processing the first insulating layer. The method further includes forming a first film on a side face of the first insulating layer, the first film containing a first reaction product generated by processing the first insulating layer. The method further includes processing the first metal layer under the first insulating layer, and the second insulating layer under the first metal layer by using the first film as a mask.

FIELD

Embodiments described herein relate to a method of manufacturing a semiconductor device.

BACKGROUND

When a three-dimensional memory is manufactured, a contact region having a stair shape is formed by forming a structure in which insulating layers and metal layers are alternately provided on a substrate and processing these layers by alternately executing lithography and dry etching. In this case, it is necessary to repeatedly move the substrate between an exposure apparatus for the lithography and a dry etching apparatus for the dry etching. Therefore, many worker-hours are required to form the contact region, which increases manufacturing cost of the three-dimensional memory. Such a problem may occur in manufacturing a semiconductor device other than the three-dimensional memory by executing the lithography and the dry etching.

DETAILED DESCRIPTION

In one embodiment, a method of manufacturing a semiconductor device includes forming a structure in which first to N-th insulating layers and first to N-th metal layers are alternately provided on a substrate where N is an integer of two or more. The method further includes processing the first insulating layer. The method further includes forming a first film on a side face of the first insulating layer, the first film containing a first reaction product generated by processing the first insulating layer. The method further includes processing the first metal layer under the first insulating layer, and the second insulating layer under the first metal layer by using the first film as a mask.

First Embodiment

FIGS. 1A to 6Bare sectional views illustrating a method of manufacturing a semiconductor device of a first embodiment. In the method of the present embodiment, a contact region of a three-dimensional memory is formed on a substrate1.

First, a ground layer2and an insulator3are formed on the substrate1(FIG. 1A). Next, a structure in which metal layers4ato4dand insulating layers5ato5dare alternately stacked is formed on the insulator3(FIG. 1A). This structure may be formed by alternately forming the metal layers4ato4dand the insulating layers5ato5don the insulator3, or may be formed by alternately forming sacrificial layers and the insulating layers5ato5don the insulator3and replacing these sacrificial layers with the metal layers4ato4d. A resist layer6is then formed on the structure (FIG. 1A). A hard mask layer may be used in place of the resist layer6.

An example of the substrate1includes a semiconductor substrate such as a silicon substrate.FIG. 1Aillustrates an X direction and a Y direction that are parallel to a surface of the substrate1and are perpendicular to each other, and a Z direction perpendicular to the surface of the substrate1. In the present specification, +Z direction is treated as an up direction, and −Z direction is treated as a down direction. The −Z direction of the present embodiment may be matched with a gravity direction, or may not be matched with the gravity direction.

Examples of the ground layer2include a gate insulator, a gate electrode, a contact plug, an interconnect layer and an inter layer dielectric. An example of the insulator3includes an inter layer dielectric. In the present embodiment, illustration of the substrate1, the ground layer2and the insulator3is omitted in the drawings afterFIGS. 1A and 1B.

An example of each of the metal layers4ato4dincludes an elemental metal layer such as a tungsten (W) layer, an aluminum (Al) layer or a copper (Cu) layer. An example of each of the insulating layers5ato5dincludes a silicon-containing insulator such as a silicon nitride film (SiN) or a silicon oxide film (SiO2). In the present embodiment, the metal layers4ato4dare W layers, and the insulating layers5ato5dare SiN layers.

Hereinafter, the metal layers4ato4dare respectively called first to fourth metal layers4ato4d, and the insulating layers5ato5dare respectively called first to fourth insulating layers5ato5d. The first to fourth metal layers4ato4dare examples of first to N-th metal layers, and the first to fourth insulating layers5ato5dare examples of first to N-th insulating layers, where N is an integer of two or more. N may be a value other than four.

Next, the resist layer6is processed by lithography and etching (FIG. 1B). As a result, the resist layer6is patterned in a predetermined shape.

Next, the first insulating layer5ais processed by using the resist layer6as a mask (FIG. 2A). The first insulating layer5aof the present embodiment is processed by dry etching using a first gas. An example of this dry etching is reactive ion etching (RIE).

The first gas contains carbon, and further contains fluorine and/or hydrogen. Examples of the first gas include a CH2F2gas, a CHF3gas, a C4F6gas and a C4F8gas where C represents carbon, F represents fluorine and H represents hydrogen. Composition ratios of fluorine in these gases are respectively ⅖, ⅗, 6/10 and 8/12, which are smaller than a composition ratio of fluorine in a CF4gas (i.e., 8/10). Such a first gas has an advantage that it can selectively etch the first insulating layer5aselected from the first insulating layer5aand the first metal layer4a. By using such a first gas, the first insulating layer5acan be etched such that a selection ratio of the first insulating layer5ato the first metal layer4ais five or more (preferably, ten or more).

The first insulating layer5ais etched by a chemical reaction of a substance that forms the first insulating layer5a(i.e., SiN) and the first gas. In this case, carbon is generated as a reaction product of the chemical reaction, and a carbon film7ais formed to contain this carbon (FIG. 2B). This reaction product is an example of a first reaction product, and the carbon film7ais an example of a first film. The carbon film7ais formed on a side face of the first insulating layer5a, and a side face and an upper face of the resist layer6. In the present embodiment, adhesion of the carbon film7ato an upper face of the first metal layer4acan be suppressed by decreasing effective power between electrodes of a RIE apparatus. The thickness of the carbon film7acan be controlled by adjusting etching time of the first insulating layer5a.

Next, the first metal layer4aunder the first insulating layer5ais processed by using the carbon film7aas a mask (FIG. 3A). The first metal layer4aof the present embodiment is processed by dry etching using a second gas that is different from the first gas. An example of this dry etching is RIE.

The second gas contains carbon, and further contains fluorine and/or hydrogen. An example of the second gas includes a CF4gas. Therefore, in the present embodiment, the composition ratio of fluorine in the first gas is smaller than the composition ratio of fluorine in the second gas. By using the CF4gas as the second gas in the present embodiment, the second gas can selectively etch the first metal layer4aselected from the first metal layer4aand the second insulating layer5b.

More specifically, the first metal layer4aof the present embodiment is processed by using the second gas and an oxygen gas. Therefore, carbon generated from the CF4gas reacts with this oxygen, and is changed into carbon dioxide.

Next, the second insulating layer5bunder the first metal layer4ais processed by using the carbon film7aas a mask (FIG. 3A). The second insulating layer5bof the present embodiment is processed by RIE using the first gas, similarly to the first insulating layer5a. The second insulating layer5bis an example of a second insulating layer, and is an example of a K-th insulator (K is an integer from 2 to N−1) in a case of K=2. Examples of the first gas include a CH2F2gas, a CHF3gas, a C4F6gas and a C4F8gas.

The second insulating layer5bis etched by a chemical reaction of a substance that forms the second insulating layer5b(i.e., SiN) and the first gas. In this case, carbon is generated as a reaction product of the chemical reaction, and a carbon film7bis formed to contain this carbon (FIG. 3B). This reaction product is an example of a K-th reaction product (K=2), and the carbon film7bis an example of a K-th film (K=2). The carbon film7bis formed on a side face of the second insulating layer5b, a side face of the first metal layer4a, and a side face and an upper face of the carbon film7a. In the present embodiment, adhesion of the carbon film7bto an upper face of the second metal layer4bcan be suppressed by decreasing the effective power between the electrodes of the RIE apparatus. The thickness of the carbon film7bcan be controlled by adjusting etching time of the second insulating layer5b.

Next, the second metal layer4bunder the second insulating layer5bis processed by using the carbon film7bas a mask (FIG. 4A). The second metal layer4bof the present embodiment is processed by RIE using the second gas, similarly to the first metal layer4a. The second metal layer4bis an example of a K-th metal film in the case of K=2. An example of the second gas includes a CF4gas.

More specifically, the second metal layer4bof the present embodiment is processed by using the second gas and an oxygen gas. Therefore, carbon generated from the CF4gas reacts with this oxygen, and is changed into carbon dioxide.

Thereafter, processing of the third and fourth insulating layers5cand5dand the third metal layer4cis executed similarly to the processing of the second insulating layer5band the second metal layer4b. The third insulating layer5cis processed with the first gas by using the carbon film7bas a mask (FIG. 4A), and thereby a carbon film7cis formed (FIG. 4B). The third metal layer4cis processed with the second gas by using the carbon film7cas a mask (FIG. 5A). The fourth insulating layer5dis processed with the first gas by using the carbon film7cas a mask (FIG. 5A), and thereby a carbon film7dis formed (FIG. 5B). The carbon films7ato7dare then removed (FIG. 6A).

In this way, the contact region having a stair shape is formed of the first to fourth insulating layers5ato5dand the first to fourth metal layers4ato4d(FIG. 6A). InFIG. 6A, upper faces of the first to fourth metal layers4ato4dare respectively exposed from the first to fourth insulating layers5ato5d.

Next, an inter layer dielectric8is formed on the contact region (FIG. 6A). Contact holes reaching the upper faces of the first to fourth metal layers4ato4dare then formed in the inter layer dielectric8, and a plug material is embedded in the contact holes. As a result, first to fourth contact plugs9ato9dare respectively formed on the upper faces of the first to fourth metal layers4ato4d(FIG. 6B).

Thereafter, various interconnect layers and inter layer dielectrics are formed on the substrate1. In this way, the semiconductor device of the present embodiment is manufactured.

FIG. 7is a sectional view illustrating an example of a structure of the semiconductor device of the first embodiment.

FIG. 7illustrates a first insulator11, a charge storage layer12, a second insulator13and a channel semiconductor layer14that form the three-dimensional memory. Examples of the first insulator11, the charge storage layer12, the second insulator13and the channel semiconductor layer14are a silicon oxide film, a silicon nitride film, a silicon oxide film, and a polysilicon layer, respectively. The charge storage layer12has a function to store signal charges of the three-dimensional memory. Shapes of the first insulator11, the charge storage layer12and the second insulator13inFIG. 7are circular pipe shapes extending in the Z direction. A shape of the channel semiconductor layer14inFIG. 7is a circular cylinder shape extending in the Z direction. The first to fourth metal layers4ato4dand the first to fourth insulating layers5ato5dface the channel semiconductor layer14through the first insulator11, the charge storage layer12and the second insulator13.

FIG. 8is a sectional view illustrating another example of the structure of the semiconductor device of the first embodiment.

FIG. 8further illustrates a third insulator15that forms the three-dimensional memory. An example of the third insulator15is a silicon oxide film. The shapes of the first insulator11, the charge storage layer12, the second insulator13and the channel semiconductor layer14inFIG. 8are circular pipe shapes extending in the Z direction. A shape of the third insulator15inFIG. 8is a circular cylinder shape extending in the Z direction and is surrounded by the channel semiconductor layer14.

The stair shape of the present embodiment can be applied to a semiconductor device other than the three-dimensional memory. An example of such a semiconductor device is a resistive random access memory (ReRAM).

FIG. 9is a diagram for describing an advantage of the method of manufacturing the semiconductor device of the first embodiment.

FIG. 9illustrates an exposure apparatus21and a dry etching apparatus22used in the method of the present embodiment. The exposure apparatus21is used in lithography of the resist layer6in the process ofFIG. 1B. The dry etching apparatus22is used in the processing from the first to fourth insulating layers5ato5dand the first to third metal layers4ato4cin the processes ofFIGS. 2A to 5B. In this case, the carbon films7ato7dare also formed in the dry etching apparatus22.

In general, when the contact region having the stair shape is formed, the substrate1is repeatedly moved between the exposure apparatus21and the dry etching apparatus22. Therefore, many worker-hours are required to form the contact region, which increases manufacturing cost of the three-dimensional memory.

Meanwhile, the processes ofFIGS. 2A to 5Bin the present embodiment can be executed in the same dry etching apparatus22, and therefore the substrate1is not moved from the dry etching apparatus22to the exposure apparatus21during the processes. Therefore, the present embodiment makes it possible to easily form the contact region with a few worker-hours and to decrease the manufacturing cost of the three-dimensional memory. Furthermore, the present embodiment makes it possible, by using the carbon films7ato7dformed in processing the first to fourth insulating layers5ato5das masks, to decrease the worker-hours for forming the masks.

FIG. 10is a sectional view illustrating details of the structure of the semiconductor device of the first embodiment.

FIG. 10illustrates the contact region ofFIG. 5Ain detail. The reference signs S1to S7indicate side faces of the first to fourth insulating layers5ato5dand the first to third metal layers4ato4c. In the processes ofFIGS. 2A to 5Bof the present embodiment, the first to fourth insulating layers5ato5dand the first to third metal layers4ato4care processed such that these side faces S1to S7have tapered shapes. However, angles of inclination of these side faces S1to S7to the Z direction are slight angles in many cases.

As described above, the present embodiment forms the carbon films7ato7dcontaining the reaction product generated by processing the insulating layers5ato5d, on the side faces of the insulating layers5ato5d, and processes the metal layers4ato4cand the insulating layers5bto5dby using the carbon films7ato7das the masks. Therefore, the present embodiment makes it possible to easily form the contact region having the stair shape.

Second Embodiment

FIGS. 11A to 11Dare sectional views illustrating a method of manufacturing a semiconductor device of a second embodiment.

First, a ground layer2, an insulator3, a metal layer4, an insulating layer5and a resist layer6are formed on a substrate1, similarly to the process ofFIG. 1A(FIG. 11A). Examples of the metal layer4are similar to those of the metal layers4ato4dof the first embodiment. Examples of the insulating layer5are similar to those of the insulating layers5ato5dof the first embodiment.

Next, the resist layer6is processed similarly to the process ofFIG. 1B, and the insulating layer5is processed similarly to the process ofFIG. 2A(FIG. 11A). As a result, a carbon film7is formed on a side face of the insulating layer5and a side face and an upper face of the resist layer6, similarly to the carbon film7aofFIG. 2B(FIG. 11A). The metal layer4, the insulating layer5and the carbon film7are examples of a first layer, a second layer and a first film, respectively.

Next, the carbon film7is removed from the upper face of the resist layer6(FIG. 11B). The resist layer6and the insulating layer5are then removed (FIG. 11C). In this way, a sidewall pattern of the carbon film7is formed on the metal layer4.

Next, the metal layer4is processed by using the carbon film7as a mask (FIG. 11D). For example, the metal layer4is processed by RIE using a second gas.

As described above, the present embodiment can process the carbon film7into the sidewall pattern, and can process the metal layer4by using the sidewall pattern as a mask. The sidewall pattern of the present embodiment may be used for processing the first layer made of only the metal layer4, or may be used for processing the first layer including the metal layer4and another layer.

Third Embodiment

FIGS. 12A and 12Bare sectional views illustrating a method of manufacturing a semiconductor device of a third embodiment.

First, a ground layer2, an insulator3, a metal layer4, an insulating layer5and a resist layer6are formed on a substrate1, similarly to the process ofFIG. 1A(FIG. 12A). Examples of the metal layer4are similar to those of the metal layers4ato4dof the first embodiment. Examples of the insulating layer5are similar to those of the insulating layers5ato5dof the first embodiment. In the present embodiment, the thickness of the metal layer4is set thicker than the thickness of the insulating layer5.

Next, the resist layer6is processed similarly to the process ofFIG. 1B, and the insulating layer5is processed similarly to the process ofFIG. 2A(FIG. 12A). As a result, a carbon film7is formed on a side face of the insulating layer5, and a side face and an upper face of the resist layer6, similarly to the carbon film7aofFIG. 2B(FIG. 12A). The metal layer4, the insulating layer5and the carbon film7are examples of a first layer, a second layer and a first film, respectively.

Next, the metal layer4is processed by using the carbon film7as a mask (FIG. 12B). For example, the metal layer4is processed by RIE using a second gas. In this case, since the metal layer4of the present embodiment is thick, the carbon film7is removed during the RIE, so that the resist layer6is exposed. Therefore, the metal layer4is processed by using the carbon film7and the resist layer6as a mask.

In the present embodiment, when the insulating layer5is processed by the processing ofFIG. 12A, carbon is generated as a reaction product. This carbon does not only form the carbon film7, but also enters the resist layer6. As a result, strength of the resist layer6is improved. Therefore, the present embodiment makes it possible to form a deep hole H in the metal layer4by using the resist layer6as a mask (FIG. 12B).

As described above, the present embodiment can process the thick metal layer4by using the resist layer6as a mask. The resist layer6of the present embodiment may be used for processing the first layer made of only the metal layer4, or may be used for processing the first layer including the metal layer4and another layer.