Assembly of thin die coreless package

In one embodiment, a method comprises coupling a coreless substrate panel to a pressure cover plate of a carrier, applying flux to the coreless substrate panel, placing at least one die on the coreless substrate panel, reflowing solder onto the coreless substrate panel, defluxing the coreless substrate panel, underfilling the coreless substrate panel, and attaching at least one heat spreader to the coreless substrate panel.

BACKGROUND

The subject matter described herein relates to the assembly of thin die coreless packages.

Electronic components, including integrated circuits, may be assembled into component packages by physically and electrically coupling them to a substrate. Thin dies exhibit performance advantages in some circumstances. Hence, techniques for the assembly of thin die packages find utility.

DETAILED DESCRIPTION

Described herein are techniques for assembly of thin die coreless packages for integrated circuits. In the following description, numerous specific details are set forth to provide a thorough understanding of various embodiments. However, it will be understood by those skilled in the art that the various embodiments may be practiced without the specific details. In other instances, well-known methods, procedures, components, and circuits have not been illustrated or described in detail so as not to obscure the particular embodiments.

One embodiment of techniques for assembly of thin die coreless packages for integrated circuits will be described with reference toFIG. 1andFIGS. 2A-2D.FIG. 1is a flowchart illustrating operations in an embodiment of a method for assembly of thin die coreless integrated circuit (IC packages).FIG. 2Ais a schematic illustration of an embodiment of a thin die coreless IC package.FIGS. 2B-2Dare schematic illustrations of an embodiment of a thin die coreless IC package during an assembly process.

Referring first toFIG. 2A, in some embodiments a thin die coreless (TDCL) package architecture may comprise a thin die210, a coreless substrate215, a heat spreader, and a thermal interface material (TIM). In some embodiments, a coreless substrate may be obtained in panel form. Extra space may be provided between adjacent substrates. A substrate carrier230is provided. In some embodiments the substrate carrier230may be designed and fabricated. In the embodiment depicted inFIG. 2B, the substrate carrier230has a flat base and a pressure cover plate240. The cover plate240includes a grid which will be pressed against the space between adjacent substrates to flatten the coreless substrates.

Referring toFIG. 1, at operation105a coreless substrate215is coupled to a pressure cover plate240of a substrate carrier230. In some embodiments, the coreless substrate215may be in panel form. In some embodiments, the coreless substrate215provides a space between two or more adjacent substrates. In some embodiments, the carrier230comprises a flat base and a pressure cover plate, and the pressure cover plate240comprises a fine grid, which is pressed against space between adjacent substrates.

At operation110flux is applied to the coreless substrate panel215. At operation115at least one die (210) is placed on the coreless substrate panel215(FIG. 2C). At operation120solder is reflowed onto the coreless substrate panel215(FIG. 2C). At operation125the coreless substrate panel215is defluxed (FIG. 2C). At operation130the coreless substrate panel215is underfilled.

At operation135at least one heat spreader250is attached to the coreless substrate panel (FIG. 2D). In some embodiments, attaching at least one heat spreader250to the coreless substrate panel215may include attaching one or more pressure clips255to apply bonding pressure to the heat spreader250. The assembled chip packages may then be separated.

Another embodiment of techniques for assembly of thin die coreless packages for integrated circuits will be described with reference toFIG. 3andFIGS. 4A-4E.FIG. 3is a flowchart illustrating operations in an embodiment of a method for assembly of thin die coreless IC packages.FIG. 4Ais a schematic illustration of an embodiment of a template for use in a thin die coreless IC package.FIGS. 4B-4Eare schematic illustrations of an embodiment of a thin die coreless IC package during an assembly process.

Referring toFIG. 3, at operation310a template is formed. In some embodiments a template405may be fabricated with one or more shallow cavities for holding the dies410. The dimensions and location of the cavities may be controlled with high precision. The template may comprise silicon. At operation315a die is positioned in at least one cavity of the template405. In some embodiments all dies are positioned in the cavities of the template405.

At operation320the die(s) are transferred to a die carrier420. In some embodiments transferring the die(s) to a die carrier comprises coating the die carrier with a layer of a high temperature silicone-based tacky material and contacting the die carrier to the template (FIG. 4B). At operation325the die carrier420is positioned adjacent a substrate panel having printed flux thereon (FIG. 4B). The substrate panel may be positioned with a carrier430(FIG. 4C). In some embodiments carrier430comprises a flat base and a pressure cover plate, which may comprise a grid which is pressed against space between adjacent substrates.

At operation345at least one heat spreader450is attached to the coreless substrate panel (FIG. 4E). In some embodiments, attaching at least one heat spreader450to the coreless substrate panel415may include attaching one or more pressure clips455to apply bonding pressure to the heat spreader450. The assembled chip packages may then be separated.

In the description and claims, the terms coupled and connected, along with their derivatives, may be used. In particular embodiments, connected may be used to indicate that two or more elements are in direct physical or electrical contact with each other. Coupled may mean that two or more elements are in direct physical or electrical contact. However, coupled may also mean that two or more elements may not be in direct contact with each other, but yet may still cooperate or interact with each other.

Reference in the specification to “one embodiment” “some embodiments” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least an implementation. The appearances of the phrase “in one embodiment” in various places in the specification may or may not be all referring to the same embodiment.