Adaptive communication methods and apparatus

Possible deficiencies of a communication link are detected and automatically counteracted, at least to some degree. The deficiencies addressed can include phase shift and attenuation compensation. The counter-action can include adjustment of pre-emphasis given a signal applied to the communication link and/or adjustment of equalization given a signal received from the communication link.

BACKGROUND OF THE INVENTION

This invention relates to communication between devices in a system, and more particularly to methods and apparatus for automatically adjusting transmission and/or reception of signals to compensate for deficiencies in the communication link being used.

Circuitry via which it is desired to send a signal may have various deficiencies that adversely affect transmission of the signal. For example, the communication link may somewhat attenuate (weaken) the signal and/or the communication link may introduce a phase shift into the signal. The magnitudes of these various deficiencies (e.g., attenuation and/or phase shift) may depend on the frequency(ies) of the signal being transmitted. These deficiencies can make it more difficult or even impossible to reliably receive a signal that has been transmitted, especially at certain frequencies or in certain frequency ranges.

Pre-emphasis and equalization are known techniques for attempting to compensate for deficiencies in a communication link. Pre-emphasis is used at the transmitter and involves giving the signal transmitted some extra energy for a certain amount of time after each change in level of the signal. Equalization is used at the receiver and involves initially responding more strongly to each change in level of the received signal. Each communication link is, however, potentially different. Also, some components (e.g., programmable logic devices or PLDs) are manufactured to be general-purpose devices to at least some degree, so that it may not be known by the manufacturer what use will be made of those devices (e.g., what communication links and frequencies they will be used with). It can accordingly be difficult or impossible to build into communication devices the appropriate amount of pre-emphasis and/or equalization.

SUMMARY OF THE INVENTION

In accordance with this invention, methods and apparatus are provided for testing a communication link for one or more types of possible deficiencies and automatically adjusting circuitry associated with the communication link to at least partly counteract detected deficiency. The communication link typically extends between first and second circuits. In accordance with the invention, the communication link is swept with a test signal having time-varying frequency. A possible deficiency of the communication link in transmitting the test signal is monitored, for example, by dividing the frequency of the test signal before and after application to the communication link and comparing phases of signals resulting from such frequency division in order to detect phase shift possibly introduced by the communication link. A circuit component of the communication link is controlled, at least in part, on the basis of this comparison of phases to at least partly counteract any such phase-shift deficiency of the communication link. For example, pre-emphasis given to signals applied to the communication link may be adjusted, and/or equalization given to signals received from the communication link may be adjusted. A second communication link between the first and second circuits may be used to convey some of results of the frequency division between those circuits to facilitate the phase comparison mentioned above. Also to facilitate and/or improve the phase comparison, the amplitude at the output of the test signal may be monitored and kept constant by the use of adjusting circuitry (e.g., an automatic gain control circuit employing feedback).

If desired in addition to the above-mentioned phase comparison, control of the communication link may be based to some degree on determining attenuation (amplitude loss) of the test signal after passage of that signal through the communication link.

DETAILED DESCRIPTION

Although the invention is applicable in other contexts, the invention will be fully understood from the following description, which for the most part assumes that the communication being discussed is between two integrated circuit devices. Also for the most part, these two devices are assumed to be programmable logic devices or PLDs, and one device is generally assumed to be the transmitter while the other device is generally assumed to be the receiver. It will be understood, however, that PLDs are only one example of devices that can be equipped with the invention, and that any transmitter or receiver may be both a transmitter and a receiver. Still another assumption that is generally made herein is that the communication is differential signalling. This is not a requirement, however, and the invention is equally applicable to non-differential, single-ended communication. Examples of PLDs that can be augmented to include the present invention are shown in Lee et al. U.S. patent application Ser. No. 10/093,785, filed Mar. 6, 2002; Venkata et al. U.S. patent application Ser. No. 10/195,229, filed Jul. 11, 2002; Venkata et al. U.S. patent application Ser. No. 10/317,262, filed Dec. 10, 2002; Lui et al. U.S. patent application Ser. No. 10/454,626, filed Jun. 3, 2003; Venkata et al. U.S. patent application Ser. No. 10/317,264, filed Dec. 10, 2002; and Venkata et al. U.S. patent application Ser. No. 10/349,541, filed Jan. 21, 2003.

In the illustrative system10shown inFIG. 1, integrated circuit device20is intended as a transmitter of signal information via differential communication link60to receiver integrated circuit device70. This is what may be termed the “normal” operating mode of system10, which occurs after a preliminary “training” mode of the system that will be the subject of most of the discussion herein. One possible configuration is for a high-speed link60to exist next to a low-speed link98, and so the term “training” is used to describe only the sequence of applied test signals, monitoring, and subsequent application of correction measures such as changing pre-emphasis and/or equalization. Device20may be a programmable logic device (PLD) having circuitry that produces or at least passes on a signal22(differential or non-differential) to be output via output driver24. Output driver24produces corresponding complementary output signals that are respectively applied to the two conductors62aand62bof communication link60. At the other end of that link, device70(which may be, for example, another programmable logic device (PLD)) the received signals are applied (across optional resistor72) to differential input driver or buffer74. Buffer74typically produces a corresponding (differential or non-differential) output signal76for use by other circuitry on device70or at least for passing on to still other circuitry or devices.

Because the normal communication circuitry just described may have transmission characteristics (e.g., signal attenuation and phase shift characteristics) that are at least to some extent unpredictable, the circuitry and methods of this invention are provided to initially test the characteristics of link60and to automatically adapt at least some of its components (if necessary) to counteract deficiencies in the performance of the link. For example, various undesirable amounts of attenuation and/or phase shift caused by link60may be counteracted by adjusting output driver24to cause that output driver to give the signal being transmitted various amounts, durations, shapes, etc., of pre-emphasis (i.e., extra energy (voltage and/or current amplitude) after each transition in the signal being transmitted). Alternatively or in addition, various undesirable amounts of attenuation and/or phase shift caused by link60may be counteracted by adjusting input driver or buffer74to cause that component to give the received signal various amounts, durations, shapes, etc., of equalization (i.e., extra energy or amplitude) after each transition in the received signal. An example of pre-emphasis and equalization circuitry that can be operated in different ways to give different amounts of pre-emphasis and/or equalization is shown in Baig et al. U.S. patent application Ser. No. 10/702,195, filed Nov. 4, 2003. Leads26are provided for controlling the operation (pre-emphasis) of output driver24. Leads78are provided for controlling the operation (equalization) of input driver or buffer74.

In accordance with this invention, prior to normal operation of link60, output driver24is preferably turned off (tri-stated) by a signal on control lead28. Variable oscillator30is then controlled via lead(s)32to begin to output differential signals34that progress through a predetermined desired range of frequencies that bracket (i.e., extend above and below) the frequency(ies) at which link60will operate during subsequent normal operation of system10. Typically also, oscillator30is controlled to progressively step through each of several discretely different frequencies that are spaced from one another across the desired range. Oscillator30operates at each of these frequencies for a period of time long enough to gather the desired data regarding the performance of link60at that frequency. Control32for oscillator30may come from microprocessor or other control circuitry100, which is shown inFIG. 1as though it is a separate element, but which can be part of device20and/or device70or included in system10in any other desired way. Block100represents the componentry that controls the test or training mode of system10in accordance with this invention; and that at the conclusion of testing, trains (i.e., controls or programs) components24and/or component74to operate during subsequent normal operation of the system to counteract deficiencies of link60that have been detected during testing.

Oscillator30preferably outputs differential sinusoidal signals having the frequency desired at any give time during the test sequence. Although sinusoidal oscillator outputs are thus preferred, periodic signals having other shapes may be used instead if desired.

The output signals of oscillator30are preferably applied to variable gain control circuitry36. Circuitry38detects the amplitude of the output signals that are applied to leads62aand62band provides a control signal39(feedback) for controlling the gain of circuitry36so that the amplitude (power) of the signals applied to leads62aand62bremains constant for all of the various frequencies used during test mode.

The output signals of variable gain control circuitry36are respectively applied to operational amplifiers40aand40b. Each operational amplifier supplies the gate control signal for an associated MOSFET42aor42b. MOSFET42ais an NMOS transistor. MOSFET42bis a PMOS transistor. The source terminal signal of NMOS transistor42ais fed back to the second input of operational amplifier40a, and also connected to lead62ain cooperation with current source circuitry44a. The source terminal signal of PMOS transistor42bis fed back to the second input of operational amplifier40b, and also connected to lead62bin cooperation current source circuitry44b.

The net effect of the circuitry that includes elements36,38,40,42and44is to apply to leads62aand62bdifferential signals having substantially contant amplitude and the successive different frequencies at which oscillator30is operated as test mode operation of the circuitry proceeds.

At receiver device70, during test mode, any attenuation of the signal received via communication link60is preferably monitored by elements80and82. For example, element80may be peak detector circuitry (like above-described element38in transmitter device20), and element82may be analog-to-digital or quantizer circuitry. One possible way to measure attenuation is to first operate link60at low frequency (where little or no attenuation is expected) and save the output83of circuitry82as a baseline. This baseline value can then be compared to subsequent values of output83as communication link60is operated at higher frequencies in order to accumulate data indicative of attenuation as a function of frequency. (Determination of such a low-frequency base line attenuation in order to effectively subtract it from attenuation values measured at higher frequencies may be referred to as de-embedding.) Circuitry100can store and manipulate outputs83in this manner to accumulate the described attenuation vs. frequency information. In addition to accumulating attenuation data, circuitry100may use that data as test mode proceeds to adjust the output of device20to counteract the attenuation that has been detected. For example, an output from circuitry100(based at least in part on data83from receiver70) may supplement or replace the output39of circuitry38as a control for variable gain circuitry36. In this way transmitter output power can be increased or decreased to more nearly flatten the response as the sweep frequency (from oscillator30) is increased. If the system is operated in this way, a record (maintained in circuitry100) of the amounts by which gain circuitry36was adjusted at each different frequency during test mode can be the attenuation-vs.-frequency information for the system.

Also at receiver70, during test mode, the signal received via communication link60is applied to input driver or buffer74, which is then preferably operated with any equalization capability that it has turned off (i.e., a flat frequency response is desired so that no phase shifting is taking place and is mistaken as a link impediment if no further de-embedding of the link and associated circuitry is performed). Note that any small phase shift at low frequencies may be negligible, but propagation delays attributable to the associated circuitry such as74may not be. Accordingly, de-embedding (the process of measuring the phase at low frequency and then subtracting those results from all further measurements at higher frequencies) eliminates this variable, should it be significant. This type of phase shift de-embedding can be similar to the above-described attenuation de-embedding, and it can be performed in the same general way and by the same means as described above for attenuation de-embedding. Either or both of attenuation and phase shift de-embedding can be performed as desired.

Although the received test signal is preferably sinusoidal or relatively sinusoidal as described earlier in connection with the discussion of oscillator30, input driver or buffer74is typically designed to receive and output digital (two-level) signals, which the normal mode signals will be in most cases. Accordingly, input buffer74tends to convert a received sinusoidal test mode signal to an output signal76that is more like a square-wave, i.e., with fairly abrupt changes in level associated with axis crossings in the received signal. Output signal76has the same frequency as the ultimate source test signal (produced by oscillator30), but its phase may have shifted relative to oscillator30as a result of passing through communication link60(now also including receiver buffer74).

The test mode output signal of input driver or buffer74is applied to frequency divider circuit90, which divides the frequency of the received test mode signal by a factor N. The output signal of divider92is one of the inputs to multiplexer92, which during test mode is controlled to apply the divider output signal (rather than a normal mode output signal94) to output driver96. Output driver96applies the signal it receives to differential communication link98for passage back to device20.

At device20the test mode signal received via link98is applied (across optional resistor50) to input buffer52. Input buffer52converts the differential signal it receives to a single-ended signal and applies that signal to one input of phase comparison circuit54. The other input to phase comparison circuit54is an output signal of oscillator30that has been divided in frequency by frequency divider circuit56. In particular, this output of oscillator30has the same frequency and phase as the test mode signal(s) oscillator30concurrently applies to variable gain circuit36as described earlier. In addition, the factor N that divider circuit56employs is the same factor N concurrently employed by divider circuit90.

Any phase shift experienced by the test mode signal in traveling through communication link60is preserved by the operation of divider circuit90. Among its effects, divider90extends the allowable phase range by 360° times the divider ratio. An example follows: If the phase shift encountered on the high-speed link is 362°, then this phase shift appears as 181° after a divide-by-two takes place on the low-speed link. This is because the divide-by-two signal has twice the period now, but the absolute phase shift in time (e.g., in picoseconds) remains the same before and after the divider.

Divider circuit90reduces the frequency of the received, possibly phase-shifted, test mode frequency for transmission back to device20via communication link98. The frequency reduction effected by divider90is preferably great enough so that the signal transmitted back to device20does not experience any significant further phase shift in propagating through communication link98and its associated circuit elements92,96and52. The test mode output signal of input buffer52therefore contains the same phase shift information as the concurrent test mode output signal of input buffer74. All phase shifts and attenuation are recorded at very low test frequencies and subsequently subtracted from higher test frequency phase and attenuation information. This is in essence a de-embedding step (also mentioned earlier) that eliminates most of the effects associated with in-line circuitry in series with the link under test (e.g., if the equalizer74and transmitter96in receiver70still introduce a phase shift at low frequencies (which may result from propagation delay of circuit elements only), that can be nulled out as just described).

The output signal of divider circuit56similarly contains phase information for the concurrent, source, test mode output of oscillator30. Phase comparison circuit54compares the phases of the two signals it receives and produces an output signal58indicative of any difference in those phases. Accordingly, the output signal58of phase comparator54indicates the phase shift, if any, experienced by the test mode signal in propagating through communication link60. As oscillator30progressively operates at different frequencies throughout the test mode frequency range, output signal58progressively indicates the communication link60phase shift for reach of the frequencies tested. Circuit100typically stores or otherwise accumulates this phase shift vs. frequency information58as test mode operations proceed. A low-frequency, baseline phase shift value may be subtracted from higher-frequency phase shift values in the accumulated phase shift vs. frequency information. This is the de-embedding process mentioned above.

Although the foregoing may imply use of a constant value of N in both of frequency dividers56and90, N can be changed as test mode proceeds. For example, at relatively low test frequencies, N may be relatively low if it is not necessary to greatly reduce the frequency in communication link98to avoid additional phase shift in that link. At higher test frequencies, N may be increased to keep the frequency in communication link98relatively low to continue to avoid additional phase shift in that link. Of course, any change in N is preferably made simultaneously in both of circuits56and90.

After all desired test mode frequencies have been employed and the attenuation (83) and phase shift (58) response of communication link60has been recorded or otherwise captured (e.g., by circuitry100), that information may be analyzed (again, typically by circuitry100) to determine how to adjust one or more of the circuit elements serving communication link60to counteract the deficiencies (e.g., attenuation and/or phase shift) of that link to thereby improve the performance of the link during subsequent normal operation of the circuitry. For example, circuitry100may determine, based on the test mode information that has been accumulated (and possibly also other information such as the frequency(ies) at which communication link60will be operated during normal operation mode), that a certain amount, duration, and/or shape of pre-emphasis should be made part of the operation of output driver24. In order to accomplish that, circuitry100may apply control signals26to driver24appropriate to configure driver24to subsequently operate (i.e., in normal operation mode) with such pre-emphasis. Alternatively or in addition, circuitry may determine that a certain amount, duration, and/or shape of equalization should be made part of the operation of input buffer74. To accomplish that, circuitry100may apply control signals78to buffer74appropriate to configure buffer74to subsequently operate (i.e., in normal operation mode) with such pre-emphasis.

Any of several techniques may be used to analyze the information (58and83) that is gathered during test mode to adapt the circuitry as described above for better performance during subsequent normal operation. For example, a look-up table of responses appropriate to various types and amounts of communication link deficiencies detected during test mode may be used. As another example, an algorithm may be performed using the test mode information (58and83) to determine the appropriate response to that particular test mode experience.

Signals26and/or78may control components24and/or74in any way appropriate to the construction of those components. For example, if component24includes multi-tap pre-emphasis circuitry, signals26may control or program component24to turn on certain of those taps while turning off others of those taps. As another example, signals26may control or program component24to select a clock speed for use in the pre-emphasis circuitry of component24to lengthen or shorten the duration of the pre-emphasis (or various parts of the pre-emphasis) given to a normal mode signal handled by component24. These examples are equally applicable to controlling the equalization effected by input buffer74.

At the conclusion of test mode operation, and after any appropriate adjustments have been made to the circuitry (e.g., via leads26and78) as described above, the test mode components of the circuitry can be disabled and any normal mode components that are not already enabled can be enabled. For example, such test mode components as elements30,36,40,42,44,58,80,82,90,54, and56can be disabled. Previously tri-stated normal mode output driver24can be enabled, and multiplexer92can be switched from (1) connecting divider90to driver96to (2) switching normal mode signal lead94to driver96. Communication link60can thereafter be used to transmit signal22from device20to device70lead76. The normal mode performance of communication link60will be improved by any adjustments that have been made (via leads26and/or78) to components24and/or74. (Note that link98can be used for normal mode communication in the opposite direction (i.e., from device70lead94to device20lead53).)

AlthoughFIG. 1shows only one communication link60equipped for test mode testing and possible adjustment prior to normal mode operation, it will be understood that any number of such links can be thus equipped, and that those links can be variously adapted to convey signals either from device20to device70(as in the case of link60) or in the opposite direction from device70to device20. For example, a link like link60can be used, if desired, to transmit the phase information. This would mean substitution of the more complex type of transmitter shown in circuit20for transmitter96. Similarly, the receiver52in circuitry20may be replaced by the type of receiver shown in circuitry70.

FIG. 2illustrates a programmable logic device (PLD)200of this invention in a data processing system202. For example, PLD200can be or include either circuit20or circuit70inFIG. 1, and the remainingFIG. 1circuitry can be included in any other device or devices inFIG. 2that PLD200communicates with. Processor204inFIG. 2can perform the functions of element100inFIG. 1, although other ways of performing those functions are also possible as mentioned earlier. Data processing system202may include one or more of the following components: a processor204; memory206; I/O circuitry208; and peripheral devices210. These components are coupled together by a system bus220and are populated on a circuit board230(e.g., a printed circuit board), which is contained in an end-user system240.

System202can be used in any of a wide variety of applications, such as computer networking, data networking, instrumentation, video processing, digital signal processing, or any other application where the advantage of using programmable or reprogrammable logic is desirable. Programmable logic device200can be used to perform a variety of different logic functions. For example, programmable logic device200can be configured as a processor or controller that works in cooperation with processor204. Programmable logic device200may also be used as an arbiter for arbitrating access to a shared resource in system202. In yet another example, programmable logic device200can be configured as an interface between processor204and one of the other components in system202. It should be noted that system202is only exemplary, and that the true scope and spirit of the invention should be indicated by the following claims.

It will be understood that the embodiments shown and described herein are only illustrative, and that various modifications can be made by those skilled in the art without departing from the scope and spirit of the invention. For example, circuitry100can take any of many different forms. Circuitry100can be wholly separate from devices20and70, or it can partly or wholly part of either or both of devices20and70. If either or both devices20and70are PLDs, circuitry100can be wholly or partly implemented in the programmable logic circuitry of those devices, or in so-called hard or soft IP (intellectual property) of those devices. As another example of modifications within the scope of the invention, phase comparison circuitry58could be moved from device20to device70, and the direction of communication link98could be reversed so that the phase comparison is performed in device70rather than in device20as shown inFIG. 1.