Methods for etching silicon using hydrogen radicals in a hot wire chemical vapor deposition chamber

Methods for etching silicon using hydrogen radicals in a hot wire chemical vapor deposition process are provided herein. In some embodiments, a method of processing a substrate having a crystalline silicon layer atop the substrate and a patterned masking layer atop the crystalline silicon layer exposing portions of the crystalline silicon layer; the method may include (a) exposing the substrate to a plasma formed from an inert gas wherein ions from the plasma amorphize a first part of the exposed portions of the crystalline silicon layer; and (b) exposing the substrate to hydrogen radicals generated from a process gas comprising a hydrogen-containing gas in a hot wire chemical vapor deposition (HWCVD) process chamber to etch the amorphized first part of the exposed portion of the crystalline silicon layer.

FIELD

Embodiments of the present disclosure generally relate to methods for etching silicon material on substrates in a hot wire chemical vapor deposition (HWCVD) process.

BACKGROUND

The inventors have observed that typical silicon etch processes performed on three dimensional devices, such as a fin field effect transistor (FinFET) can result in damage to the fin, for example, due to physical damage from high energy ions, chemical damage due to corrosive gases, and inadequate selectivity to silicon oxide layer that protects the fin. In addition, the inventors noted that typical silicon etch processes often change the fin shape due to micro-loading, for example, causing tapered profiles between fins and/or erosion of fins. Lastly, the inventors have observed that post etch residue can lead to loss of fins altogether and/or the formation of irregular and poor quality epitaxial layers.

Therefore, the inventors have provided improved methods for etching silicon films.

SUMMARY

Methods for etching silicon using hydrogen radicals in a hot wire chemical vapor deposition process are provided herein. In some embodiments, a method of processing a substrate having a crystalline silicon layer atop the substrate and a patterned masking layer atop the crystalline silicon layer exposing portions of the crystalline silicon layer includes (a) exposing the substrate to a plasma formed from an inert gas wherein ions from the plasma amorphize a first part of the exposed portions of the crystalline silicon layer; and (b) exposing the substrate to hydrogen radicals generated from a process gas comprising a hydrogen-containing gas in a hot wire chemical vapor deposition (HWCVD) process chamber to etch the amorphized first part of the exposed portion of the crystalline silicon layer.

In some embodiments, a method of processing a substrate having a crystalline silicon layer atop the substrate and a patterned masking layer atop the crystalline silicon layer exposing portions of the crystalline silicon layer includes: (a) exposing the substrate to a plasma formed from an inert gas wherein ions from the plasma amorphize a first part of the exposed portions of the crystalline silicon layer, wherein the substrate is exposed to the plasma for a first period of time from about 1 seconds to about 360 seconds, and wherein a temperature of the substrate during exposure to the plasma is about 15 degrees Celsius to about 25 degrees Celsius, and a process pressure during exposure to the plasma is about 5 to about 100 mTorr; (b) exposing the substrate to hydrogen radicals generated from a process gas comprising a hydrogen-containing gas in a hot wire chemical vapor deposition (HWCVD) process chamber to etch the amorphized first part of the exposed portion of the crystalline silicon layer, wherein the substrate is exposed to hydrogen radicals for a second period of time substantially equal to the first period of time, wherein the amorphized first part of the exposed portion of the crystalline silicon layer has a thickness of about 0.5 nm to about 10 nm, and wherein a temperature of one or more filaments within the HWCVD process chamber during exposure to the hydrogen radicals is about 1200 to about 1700 degrees Celsius; and (c) repeating (a)-(b) to etch the crystalline silicon layer to a desired depth.

In some embodiments, the disclosure may be embodied in a computer readable medium having instructions stored thereon that, when executed, cause a method to be performed in a process chamber, the method includes any of the embodiments disclosed herein.

DETAILED DESCRIPTION

Embodiments of the present disclosure provide hot wire chemical vapor deposition (HWCVD) processing techniques useful for etching silicon films. In one exemplary application, embodiments of the present disclosure may advantageously be used to etch fin structures in fin field effect transistors (FinFET) while providing one or more of the following benefits: a reduction in fin damage, high selectivity to oxide and nitride, and residue-free etching for subsequent EPI growth. Embodiments of the present disclosure may be used to advantage for other silicon etch applications including but not limited to poly-silicon gate etch and silicon trench etch.

FIG. 1depicts a flow chart for a method100of processing a substrate200.FIGS. 2A-2Cdepict illustrative cross-sectional views of a substrate200during different stages of the processing sequence ofFIG. 1in accordance with some embodiments of the present disclosure.

The method begins at102by exposing the substrate200to a plasma formed from an inert gas.102may be performed in any suitable process chamber where an inert gas plasma can be formed. Example of suitable process chambers include, but are not limited to, an ENDURA® PVD processing chamber, an ADVANTEDGE™ line of etch reactors (such as the AdvantEdge G3 or the AdvantEdge G5), a MESA™ chamber, an ENABLER® or PRODUCER® etch chamber, or other commercially available chambers from Applied Materials, Inc., of Santa Clara, Calif. In some embodiments, the process chamber is a part of a multi-chamber processing system (e.g., a cluster tool) described below with respect toFIG. 4.

The inert gas may be one or more of argon, helium, or the like. In some embodiments, the inert gas is provided at a flow rate of about 10 sccm to about 50 sccm. In some embodiments, the inert gas is ignited to form a plasma using an RF power of about 200 watts to about 700 watts at a frequency of about 100 kHz to about 162 MHz, such as about 13.56 MHz. In some embodiments, the RF power may be pulsed at about 200 watts to about 700 watts at a duty cycle of about 20% to about 90%.

The substrate200may be any suitable substrate, such as a doped or un-doped silicon substrate, a III-V compound substrate, a silicon germanium (SiGe) substrate, an epi-substrate, a silicon-on-insulator (SOI) substrate, a display substrate such as a liquid crystal display (LCD), a plasma display, an electro luminescence (EL) lamp display, a light emitting diode (LED) substrate, a solar cell array, solar panel, or the like. In some embodiments, the substrate200may be a semiconductor wafer. In some embodiments, the substrate200includes one or more partially or fully fabricated semiconductor devices, for example, such as a FinFET, a fully depleted SOI device, or the like.

As depicted inFIG. 2A, the substrate200comprises a crystalline silicon layer202and a mask layer204disposed above the crystalline silicon layer202. The crystalline silicon layer202may be formed by any process suitable for forming a crystalline silicon layer202. In some embodiments, the crystalline silicon layer202is a silicon oxide (SiOx) layer formed atop the substrate200. The silicon oxide (SiOx) layer may be deposited via any process suitable to deposit the silicon oxide (SiOx) layer having desired characteristics (e.g., crystallinity, composition, uniformity, or the like). For example, in some embodiments, the silicon oxide (SiOx) layer is deposited via chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or the like. In some embodiments, the silicon oxide (SiOx) layer may be formed by first depositing a silicon (Si) containing layer via one of the aforementioned deposition processes, followed by a subsequent oxidation process. The silicon oxide (SiOx) layer may be deposited to any thickness suitable for fabrication of a desired semiconductor device.

The mask layer204is deposited and patterned to expose portions206of the crystalline silicon layer202. The patterned mask layer204may define one or more features to be etched into the substrate200. In addition, the patterned mask layer204may define separate regions of varying feature density (e.g., regions of high feature density and regions of low feature density). The patterned mask layer204may be any suitable mask layer such as a hard mask or photoresist layer. For example, in embodiments where the patterned mask layer204is a hard mask, the patterned mask layer204may comprise silicon nitride (Si3N4), silicon oxide (SiO2), titanium oxide (TiO), TiN (titanium nitride), aluminum oxide (Al2O3) or the like. Alternatively, or in combination, in some embodiments, the mask layer may comprise an amorphous carbon, such as Advanced Patterning Film (APF), available from Applied Materials, Inc., located in Santa Clara, Calif., or a tri-layer resist (e.g., a photoresist layer, a Si-rich anti-reflective coating (ARC) layer, and a carbon-rich ARC, or bottom ARC (BARC) layer), a spin-on hardmask (SOH), or the like. The patterned mask layer204may be formed by any process suitable to form a patterned mask layer204. For example, in some embodiments, the patterned mask layer204may be formed via a patterned etch process. In some embodiments, for example where the patterned mask layer204will be utilized to define advanced or very small node devices (e.g., about 40 nm or smaller nodes, such as Flash memory devices), the patterned mask layer204may be formed via a spacer mask patterning technique, such as a self-aligned double patterning process (SADP).

In some embodiments, as depicted inFIG. 2A, ions208from the plasma strike the exposed portions206of the crystalline silicon layer202resulting in the amorphization of a first part210of the exposed portions206. In some embodiments, the amorphized first part210has a thickness of about 0.5 to about 10 nm. In some embodiments, the substrate200is exposed to the ions208for a first period of time from about 1 seconds to about 360 seconds. In some embodiments, during exposure to the ions208, the substrate200is maintained at a temperature of about 15 degrees Celsius to about 25 degrees Celsius. In some embodiments, during exposure of the substrate200to the ions208, the process chamber is at a pressure of about 5 mTorr to about 100 mTorr.

Next at104, and as depicted inFIG. 2B, the substrate200is exposed to hydrogen radicals212generated from a process gas within a hot wire chemical vapor deposition (HWCVD) chamber, for example the HWCVD chamber depicted inFIG. 3. In some embodiments, the HWCVD chamber is a part of the multi-chamber processing system described below with respect toFIG. 4. The process gas comprises a hydrogen-containing gas for example hydrogen (H2), or dinitrogen tetrahydride (N2H4), or ammonia (NH3), or a hydrocarbon (e.g.: methylene, ethylene, or the like) or the like. In some embodiments, the flow rate of the process gas is about 400 to about 800 sccm. In some embodiments, the process gas further comprises an inert gas such as argon, helium or the like. The hydrogen radicals212etch the amorphized first part210of the crystalline silicon layer202. In some embodiments, the substrate200is exposed to the hydrogen radicals212for a second period of time substantially equal to the first period of time. In some embodiments, the temperature of one or more filaments within the HWCVD process chamber during exposure to hydrogen radicals212is about 1200 to about 1700 degrees Celsius. In some embodiments, the pressure within the process chamber during 104 is about 5 to about 500 mTorr. Next at106,102-104are repeated to etch the crystalline silicon layer202to a desired depth. Upon completion of etching the crystalline silicon layer202to a desired depth the substrate200may continue being processed, as desired, to complete the formation of structures and/or devices thereupon.

FIG. 3depicts a schematic side view of an HWCVD process chamber300(e.g. process chamber300) suitable for use in accordance with embodiments of the present disclosure. The process chamber300generally comprises a chamber body302having an internal processing volume304. A plurality of filaments, or wires310, are disposed within the chamber body302(e.g., within the internal processing volume304). The plurality of wires310may also be a single wire routed back and forth across the internal processing volume304. The plurality of wires310comprise a HWCVD source. The wires310are typically made of tungsten, although tantalum or iridium may also be used. Each wire310is clamped in place by support structures (not shown) to keep the wire taught when heated to high temperature, and to provide electrical contact to the wire. A power supply312is coupled to the wire310to provide current to heat the wire310. A substrate330may be positioned under the HWCVD source (e.g., the wires310), for example, on a substrate support328. The substrate support328may be stationary for static deposition, or may move (as shown by arrow305) for dynamic deposition as the substrate330passes under the HWCVD source.

The chamber body302further includes one or more gas inlets (one gas inlet332shown) to provide one or more process gases and one or more outlets (two outlets334shown) to a vacuum pump to maintain a suitable operating pressure within the process chamber300and to remove excess process gases and/or process byproducts. The gas inlet332may feed into a shower head333(as shown), or other suitable gas distribution element, to distribute the gas uniformly, or as desired, over the wires310.

In some embodiments, one or more shields320may be provided to minimize unwanted deposition on interior surfaces of the chamber body302. Alternatively or in combination, one or more chamber liners322can be used to make cleaning easier. The use of shields, and liners, may preclude or reduce the use of undesirable cleaning gases, such as the greenhouse gas NF3. The shields320and chamber liners322generally protect the interior surfaces of the chamber body from undesirably collecting deposited materials due to the process gases flowing in the chamber. The shields320and chamber liners322may be removable, replaceable, and/or cleanable. The shields320and chamber liners322may be configured to cover every area of the chamber body that could become coated, including but not limited to, around the wires310and on all walls of the coating compartment. Typically, the shields320and chamber liners322may be fabricated from aluminum (Al) and may have a roughened surface to enhance adhesion of deposited materials (to prevent flaking off of deposited material). The shields320and chamber liners322may be mounted in the desired areas of the process chamber, such as around the HWCVD sources, in any suitable manner. In some embodiments, the source, shields, and liners may be removed for maintenance and cleaning by opening an upper portion of the deposition chamber. For example, in some embodiments, the a lid, or ceiling, of the deposition chamber may be coupled to the body of the deposition chamber along a flange338that supports the lid and provides a surface to secure the lid to the body of the deposition chamber.

A controller306may be coupled to various components of the process chamber300to control the operation thereof. Although schematically shown coupled to the process chamber300, the controller may be operably connected to any component that may be controlled by the controller, such as the power supply312, a gas supply (not shown) coupled to the inlet332, a vacuum pump and or throttle valve (not shown) coupled to the outlet334, the substrate support328, and the like, in order to control the HWCVD deposition process in accordance with the methods disclosed herein. The controller306generally comprises a central processing unit (CPU)308, a memory313, and support circuits311for the CPU308. The controller306may control the process chamber300directly, or via other computers or controllers (not shown) associated with particular support system components. The controller306may be one of any form of general-purpose computer processor that can be used in an industrial setting for controlling various chambers and sub-processors. The memory, or computer-readable medium,313of the CPU308may be one or more of readily available memory such as random access memory (RAM), read only memory (ROM), floppy disk, hard disk, flash, or any other form of digital storage, local or remote. The support circuits311are coupled to the CPU308for supporting the processor in a conventional manner. These circuits include cache, power supplies, clock circuits, input/output circuitry and subsystems, and the like. Inventive methods as described herein may be stored in the memory313as software routine314that may be executed or invoked to turn the controller into a specific purpose controller to control the operation of the process chamber300in the manner described herein. The software routine may also be stored and/or executed by a second CPU (not shown) that is remotely located from the hardware being controlled by the CPU308.

FIG. 4is a schematic top-view diagram of an exemplary multi-chamber processing system400(e.g. process system400) in accordance with some embodiments of the present disclosure. Examples of suitable multi-chamber processing systems include the ENDURA®, CENTURA®, and PRODUCER® processing systems, commercially available from Applied Materials, Inc.

The process system400generally includes a first transfer chamber402and a second transfer chamber404. The first and second transfer chambers402,404may be vacuum chambers and may be separated by one or more intermediate load lock chambers406,408coupling the second transfer chamber404to the first transfer chamber402. The first and second transfer chambers402,404are capable of transferring substrates to and receiving substrates from one or more process chambers coupled to the first or second transfer chambers402,404. At least one of the process chambers (e.g., a first process chamber) may be a HWCVD process chamber as described above and as depicted inFIG. 3.

The process system400may further include load lock chambers410,412to transfer substrates into and out from the process system400. For example, the load lock chambers410,412may be coupled to the second transfer chamber404as depicted inFIG. 4. The load lock chambers410,412are vacuum chambers that can be selectively “pumped down” to a vacuum pressure at or near that in the transfer chamber, or brought to a pressure at or near the ambient room pressure to facilitate entry and egress of substrates into and out of to the process system400.

A plurality of process chambers may be coupled to the second transfer chamber404. For example, as shown inFIG. 4, process chambers414,416,418, and420are shown coupled to the second transfer chamber404(although greater or fewer process chambers may be provided). Each process chamber414,416,418, and420may be configured to perform particular substrate processing operations such as, but not limited to, cyclical layer deposition including atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etch, pre-clean, de-gas, anneal, orientation, or other substrate processes.

The second transfer chamber404may include a second robot405to transfer substrates, for example substrate200discussed above, between the load lock chambers410,412, and one or more process chambers414,416, the one or more intermediate load lock chambers406,408, and other chambers418,420. Similarly, the first transfer chamber402may include a first robot403to transfer substrates (e.g., substrate200) between process chambers coupled to the first transfer chamber402and the one or more intermediate load lock chambers406,408.

A plurality of process chambers may be coupled to the first transfer chamber402. For example, as shown inFIG. 4, process chambers422,424,426, and428are shown coupled to the first transfer chamber402(although greater or fewer process chambers may be provided). Similar to process chambers414,416,418, and420, the process chambers422,424,426, and428can be configured to perform particular substrate processing operations, such as, but not limited to, cyclical layer deposition including atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etch, pre-clean, de-gas, anneal, orientation, or the like.

The one or more intermediate load lock chambers406,408may be used to maintain ultrahigh vacuum conditions while allowing substrates to be transferred within the process system400. The one or more intermediate load lock chambers406,408may allow for independent and/or isolated ambient control between the first and second transfer chambers402,404. For example, the one or more intermediate load lock chambers406,408may allow for the first and second transfer chambers402,404to have one or more independently controlled chamber parameters. For example, the one or more independently controlled chamber parameters may include one or more of transfer chamber pressure, purge gas flow through the transfer chamber, transfer chamber moisture level, or residual gas level within the respective transfer chamber.

In some embodiments, the one or more intermediate load lock chambers406,408may include a gas source442coupled to the one or more intermediate load lock chambers406,408to expose the substrate to a gas when the substrate is placed within the one or more intermediate load lock chambers406,408. For example, gas source may provide a passivation gas or the like as the substrate passes through the one or more intermediate load lock chambers406,408between processes. Examples of suitable gases include hydrogen sulfide (H2S), ammonium sulfide (NH4S), hydrogen (H2), or the like. Further, the one or more intermediate load lock chambers406,408may be used as cooling or heating chambers or the like. Alternatively, any of the process chambers couple to the first or second transfer chambers402,404may be utilized as a cooling chamber.

A controller450may be coupled to the process system400to control the operation of the process system400and/or the individual components of the process system400. The controller450may be one of any form of general-purpose computer processor that can be used in an industrial setting for controlling various chambers and sub-processors. The memory, or computer-readable medium,454of the CPU452may be one or more of readily available memory such as random access memory (RAM), read only memory (ROM), floppy disk, hard disk, or any other form of digital storage, local or remote. The support circuits456are coupled to the CPU452for supporting the processor in a conventional manner. These circuits include cache, power supplies, clock circuits, input/output circuitry and subsystems, and the like.