Digital feedforward sigma-delta modulator in analog-to-digital converter and modulation method thereof

A digital feedforward sigma-delta modulator in an analog-to-digital converter and its modulation method are disclosed. The modulator changes a feedforward path from an analog domain to a digital domain and processes it. The modulator integrates an analog input by using a plurality of integrators, weights them, quantizes them by using a plurality of quantizers in a digital domain to output digital signals, and then adds up the thusly outputted digital signals by using a digital adder. In case of a continuous time digital feedforward sigma-delta modulator (SDM), a digital signal outputted from the digital adder is weighted and then immediately inputted to the digital adder in the digital domain so as to be subtracted, allowing for digital feedforwarding. Because the feedforward signal is processed in the digital domain, the area occupied by an analog circuit and power consumption can be reduced. Also, because signals are added up in the digital domain, a digital output signal can be immediately used when an excess loop delay needs to be corrected. Thus, because there is no need to convert the digital output signal into an analog signal by using a DAC, the DAC can be omitted.

BACKGROUND OF THE INVENTION

(a) Field of the Invention

The present invention relates to a sigma-delta modulator (SDM) used in an analog-to-digital converter (ADC) and, more particularly, to a digital feedforward SDM having a feedforward path and a modulation method thereof.

(b) Description of the Related Art

A digital feedforward signal-delta modulator (SDM) used in an analog-to-digital converter (ADC) and other applications is well known in this field. Because such an SDM is easily implemented by using a CMOS process without requiring precise components, it is commonly used especially in an analog-to-digital converter (ADC) or the like.

FIG. 1is a schematic block diagram showing the structure of the related art discrete time feedforward SDM.

As shown inFIG. 1, in the related art discrete time feedforward SDM, the an analog input signal and analog outputs from integrators10-1,10-2, . . . ,10-nare multiplied by coefficients b0, b1, b2, . . . , bnby multipliers20-0,20-1,20-2, . . . ,20-n, which are then inputted to an analog adder30. The analog adder30adds up the analog signals inputted from the multipliers20-0,20-1,20-2, . . . ,20-nand outputs an analog added signal. The analog added signal outputted from the analog adder30is quantized by a quantizer40, so as to be outputted as a digital output signal. The digital output signal outputted from the quantizer40is converted into an analog signal by a digital-to-analog converter (DAC)50so as to be fed back, to which a coefficient a1is applied by a multiplier60so as to be outputted as an analog signal. The analog input signal is subtracted by the analog signal fed back from the multiplier60by a subtractor70, which is then inputted to the integrator10-1.

With reference toFIG. 1, in the related art discrete time feedforward SDM, the part from the quantizer40to the DAC50is a digital domain, while the other part, namely, from the analog input signal to the analog adder30and from the multiplier60to the subtractor70is an analog domain.

Thus, the related art discrete time feedforward SDM requires an analog adding circuit such as the analog adder30in order to add up the analog signals, and in general, a high speed signal processing is required in the analog adding circuit.

FIG. 2is a schematic block diagram showing the structure of the related art continuous time feedforward SDM.

As shown inFIG. 2, the related art continuous time feedforward SDM has a very similar structure to that of the discrete time feedforward SDM illustrated inFIG. 1. Thus, the same reference numerals will be used for the same elements as those illustrated inFIG. 1.

The continuous time feedforward SDM illustrated inFIG. 2additionally includes elements80and90for correcting an excess loop delay besides the elements10-1,10-2, . . . ,10-n,20-0,20-1,20-2, . . . ,20-n,30,40,50,60, and70of the related art discrete time feedforward SDM illustrated inFIG. 1. Namely, a digital output signal outputted from the quantizer40is converted into an analog signal by a DAC80, to which a coefficient a2is multiplied by the multiplier90so as to be outputted as an analog signal, and the analog signal is outputted to the analog adder30so as to be applied as a subtraction value. Namely, the analog adder30illustrated inFIG. 1adds up only the analog signals outputted from the multipliers20-0,20-1,20-2, . . . ,20-n, while the analog adder30illustrated inFIG. 2adds up all the analog signals outputted from the multipliers20-0,20-1,20-2, . . . ,20-n, subtracts an analog signal, which has been converted from a digital output signal outputted from the quantizer40, weighted, and fed back, from the added analog signal and then outputs the resultant signal to the quantizer.

With reference toFIG. 2, the part from the quantizer40to the DACs50and80is a digital domain, and the other part, namely, from the analog input signal to the analog adder30, from the multiplier60to the subtractor70, and from the multiplier90to the analog adder30, is an analog domain.

Thus, the related art continuous time feedforward SDM also requires an analog adding circuit such as the analog adder30in order to add up the analog signals, and in general, a high speed signal processing is required in such an analog adding circuit. Also, it is noted that, the related art continuous time feedforward SDM additionally uses the DAC80for converting the digital output signal to the analog signal in order to correct the excess loop delay.

SUMMARY OF THE INVENTION

The present invention has been made in an effort to provide a digital feedforward sigma-delta modulator (SDM) and its modulation method having advantages of improving activity in circuit designing according to a process by reducing the area of an analog circuit and power consumption.

An exemplary embodiment of the present invention provides a digital feedforward SDM for performing digital feedforward sigma-delta modulation on an analog input signal and outputting a corresponding digital output signal, including: a plurality of integrators connected in series, receiving an analog signal, integrating the received analog signal and outputting a corresponding analog signal, respectively; a plurality of multipliers weighting the analog signals outputted from the plurality of integrators and outputting the weighted analog signals, respectively; a plurality of quantizers performing quantization on the analog signals outputted from the plurality of multipliers and outputting a digital signal, respectively; and a digital adder adding up the digital signals outputted from the plurality of quantizers and outputting a corresponding digital output signal.

Another embodiment of the present invention provides, a digital feedforward SDM for performing digital feedforward sigma-delta modulation on an analog input signal and outputting a corresponding digital output signal, including: a plurality of integrators connected in series, receiving an analog signal, integrating the received analog signal and outputting a corresponding analog signal, respectively; a plurality of multipliers weighting the analog signals outputted from the plurality of integrators and outputting a weighted analog signal, respectively; a plurality of quantizers performing quantization on the analog signals outputted from the plurality of multipliers and outputting a digital signal, respectively; a digital adder adding up the digital signals outputted from the plurality of quantizers, subtracting a signal inputted as a feedback signal from the result of the adding up the digital signals, and outputting a corresponding digital output signal; and a second multiplier weighting the digital signal outputted from the digital adder and outputting the weighted digital signal to the digital adder.

Yet another embodiment of the present invention provides a digital feedforward sigma-delta modulation method for performing digital feedforward sigma-delta modulation on an analog input signal and outputting a corresponding digital output signal, including: inputting an analog input signal to a plurality of integrators connected in series; weighting the analog input signal and analog signals outputted from the plurality of integrators, and outputting corresponding analog signals; quantizing the weighted analog signals and outputting corresponding digital signals; and adding up all the digital signals and outputting a corresponding digital output signal.

Still another embodiment of the present invention provides a digital feedforward sigma-delta modulation method for performing digital feedforward sigma-delta modulation on an analog input signal and outputting a corresponding digital output signal, including: inputting an analog input signal to a plurality of integrators connected in series; weighting the analog input signal and an analog signal outputted from each of the plurality of integrators, and outputting corresponding analog signals; quantizing the weighted analog signals and outputting corresponding digital signals; and adding up all the digital signals and outputting a corresponding digital output signal, and in this case, a signal, fed back after it is obtained by weighting the digital output signal, is applied as a subtraction value when the digital signals are all added up.

According to an exemplary embodiment of the present invention, because the feedforward signal is processed in a digital domain, the area occupied by the analog circuit and power consumption can be reduced.

Also, because signals are added up in the digital domain, a digital output signal can be immediately used when an excess loop delay needs to be corrected. Thus, because there is no need to convert the digital output signal into an analog signal by using a DAC, the DAC can be omitted.

In addition, because the most signal processing can be performed in the digital domain, not in an analog domain, a process development can be achieved, advantageously reducing area and power consumption, and the activity in circuit designing according to the process can be also improved.

DETAILED DESCRIPTION OF THE EMBODIMENTS

When a part ‘includes’ an element, it means that it may include a different element, rather than excluding the different element, unless otherwise specified. Terms such as ‘part’ or ‘unit’, ‘module’ used in the specification refers to a unit for processing at least one function or operation, which may be implemented by hardware, software, or a combination of hardware or software.

FIG. 3is a schematic block diagram showing the structure of a discrete time feedforward SDM according to an exemplary embodiment of the present invention.

The subtractor100subtracts an analog signal outputted from a multiplier160from an analog input signal, and outputs a resultant signal to the integrator110-1.

The integrators110-1,110-2, . . . ,110-nare connected in series. Each integrator receives an output from its front stage, integrates the received signal, and outputs the integrated signal to its rear stage. The first integrator110-1of the integrators110-1,110-2, . . . ,110-nconnected in series receives the analog signal outputted from the subtractor100. The analog signal outputted from the integrator110-npositioned at the end of the integrators connected in series is inputted to the multiplier120-n.

An input to the multiplier120-0is an analog input signal.

The quantizers130-0,130-1,130-2, . . . ,130-nperform quantization on the respective analog signals to which the coefficients b0, b1, b2, . . . , bnhave been multiplied by the multipliers120-0,120-1,120-2, . . . ,120-n, and output corresponding digital signals to the digital adder140.

The digital adder140adds up all the digital signals outputted from the quantizers130-0,130-1,130-2, . . . ,130-n, and output a corresponding digital output signal.

The DAC150converts the digital output signal outputted from the digital adder140into a corresponding analog signal so as to be fed back to the subtractor100, and outputs the converted analog signal.

The multiplier160multiplies a coefficient a1to the analog signal outputted from the DAC150, and feeds the corresponding analog signal to the subtractor100.

With reference toFIG. 3, roughly, the part from the quantizers130-0,130-1,130-2, . . . ,130-nto the digital adder140and to the DAC150is a digital domain, and the other part, namely, from the analog input signal to the multipliers120-0,120-1,120-2, . . . ,120-nand to the multiplier160, is an analog domain.

Compared with the related art feedforward SDM described above with reference toFIG. 1, in the digital feedforward SDM according to an exemplary embodiment of the present invention described with reference toFIG. 3, the digital adder140, as a circuit for adding up the signals, belongs to the digital domain.

The operation of the digital feedforward SDM according to an exemplary embodiment of the present invention will now be described.

After a signal fed back from the multiplier160is subtracted by the subtractor100from the analog input signal, the resultant signal is inputted as an input signal to the first integrator110-1among the integrators110-1,110-2, . . . ,110-3connected in series. Also, the analog input signal is inputted to the multiplier120-0.

In this manner, the analog signals outputted from the multipliers120-0,120-1,120-2, . . . ,120-nof the analog domain are transferred to the digital domain and inputted to the quantizers130-0,130-1,130-2, . . . ,130-n.

The respective analog signals are then quantized by the quantizers130-0,130-1,130-2,130-n, and outputted as digital signals to the digital adder140.

And then, the digital signals inputted to the digital adder140are all added up and outputted as a corresponding digital output signal. That is, the digital adder140only adds up the digital signals on the digital domain.

Thereafter, the digital output signal outputted from the digital adder140is converted into a corresponding analog signal by the DAC150so as to be fed back to the analog domain, weighted by the coefficient a1in the multiplier160, and then fed back to the subtractor100.

As described above, the digital feedforward SDM according to an exemplary embodiment of the present invention digitalizes the feedforward path, allowing for shifting the signal processing part, which is performed in the analog domain in the related art, to the digital domain, and accordingly, only the digital adding circuit is used on the digital domain without using a high speed analog adding circuit, thus reducing the area otherwise occupied by the analog circuit or its power consumption.

FIG. 4is a schematic block diagram showing the structure of a continuous time feedforward SDM according to an exemplary embodiment of the present invention. The continuous time digital feedforward SDM illustrated inFIG. 4has a similar configuration to that of the discrete time digital feedforward SDM illustrated inFIG. 3, so the same reference numerals are used for the same elements as those illustrated inFIG. 3.

As shown inFIG. 4, the continuous time digital feedforward SDM according to an exemplary embodiment of the present invention includes a subtractor100, integrators110-1,110-2, . . . ,110-n, multipliers120-0,120-1,120-2, . . . ,120-n,160, quantizers130-0,130-1,130-2, . . . ,130-n, a digital adder200, and a digital-to-analog converter (DAC)150.

The continuous time digital feedforward SDM illustrated inFIG. 4has a similar configuration to that of the discrete time digital feedforward SDM illustrated inFIG. 3, so, here, only the different parts from those of the discrete time digital feedforward SDM illustrated inFIG. 3will be described.

In the continuous time digital feedforward SDM, an excessive loop delay needs to be corrected, so a multiplier210is added to the discrete time digital feedforward SDM illustrated inFIG. 3and the digital adder200applies a digital signal outputted from the multiplier210for a subtraction.

Namely, the multiplier210multiplies a digital output signal outputted from the digital adder200by a coefficient a2, and outputs the resultant signal to the digital adder200. Here, because the digital adder200exists in the digital domain, a signal fed forward to the digital adder200does not need to be converted into an analog signal.

In addition, the digital adder200adds up all the digital signals outputted from the quantizers130-0,130-1,130-2, . . . ,130-n, and additionally subtracts the digital signal outputted from the multiplier210, and outputs a corresponding digital output signal.

Compared with the related art feedforward SDM described above with reference toFIG. 2, in the digital feedforward SDM according to an exemplary embodiment of the present invention described with reference toFIG. 4, the digital adder200, as a circuit for adding up the signals, belongs to the digital domain. In addition, in the related art feedforward SDM described above with reference toFIG. 2, the DAC is used to correct the excessive loop delay, but in the digital feedforward SDM according to the exemplary embodiment illustrated inFIG. 4, because the digital adder200is positioned in the digital domain, only the coefficient a2can be simply multiplied to the digital output signal outputted from the digital adder200through the multiplier210, which is then inputted as a digital signal to the digital adder200, in order to correct the excessive loop delay, so there is no need to use a DAC.

The operation of the continuous time digital feedforward SDM according to an exemplary embodiment of the present invention illustrated inFIG. 4is very similar to the discrete time digital feedforward SDM illustrated inFIG. 3. That is, the digital output signal outputted from the digital adder200is weighted by the coefficient a2in the multiplier210, which is then feedforward to the digital adder200, and when all the digital signals outputted from the quantizers130-0,130-1,130-2, . . . ,130-nare added up by the digital adder200, the digital signal outputted from the multiplier210is applied to the digital adder210such that it is subtracted from all the digital signals outputted from the quantizers130-0,130-1,130-2, . . . ,130-n, and as a result, an excessive loop delay with respect to the digital output signal can be corrected.

As described above, the continuous time digital feedforward SDM according to an exemplary embodiment of the present invention digitalizes the feedforward path, allowing for shifting the signal processing part, which is performed in the analog domain in the related art, to the digital domain, and accordingly, only the digital adding circuit is used on the digital domain without using a high speed analog adding circuit, thus reducing the area otherwise occupied by the analog circuit or its power consumption.

Also, because the digital adder200used for correcting the excessive loop delay is positioned in the digital domain, not in the analog domain, the digital output signal can be simply weighted by the coefficient a2in the multiplier210, without being converted into an analog signal, and then immediately applied to the digital adder200, removing the necessity of the use of a DAC. Accordingly, the area otherwise occupied by an analog circuit and its power consumption can be further reduced.

Meanwhile, the digital feedforward SDMs according to the exemplary embodiments of the present invention described with reference toFIGS. 3 and 4are illustrated to use many quantizers130-0,130-1,130-2, . . . ,130-n, but actually, in consideration of a low swing range of the outputs of the integrators110-1,110-2, . . . ,110-n, the advantage of the feedforward structure, a significantly small number of quantizers, not as much as the actually required resolution, is required. For example, when a 4-bit quantizer is desired to be implemented, the related art feedforward SDMs illustrated inFIGS. 1 and 2generally use fifteen comparators for one quantizer, and the digital feedforward SDMs according to the exemplary embodiments of the present invention illustrated inFIGS. 3 and 4may also use fifteen comparators or smaller for each quantizer, so the total number of comparators is similar.

Meanwhile, in the above description, the discrete time digital feedforward SDM and the continuous time digital feedforward SDM are separately configured as shown inFIGS. 3 and 4. In this respect, however, in the continuous time digital feedforward SDM, the coefficient a2of the multiplier210may be set to be 0 to cut off the connection of the signal fed forward to the discrete digital adder200, whereby the continuous time digital feedforward SDM can operate like the discrete time digital feedforward SDM. In this case, because the continuous time digital feedforward SDM according to the present exemplary embodiment feeds forward the digital output signal to the digital adder200without using a DAC, even when the coefficient of the multiplier210is set to be 0 so as to be implemented as a discrete time digital feedforward SDM, only the multiplier210is not in use, so a smaller number of components are used compared with the related art.