Packaged circuit system structure

A packaged circuit system structure with circuit elements embedded into a bulk material. At least one of the embedded circuit elements forms a dual coupling that includes an electrical connection to a signal ground potential on one side of the structure and an electrical connection to a conductive layer on the other side of the structure. The conductive layer extends over at least one embedded circuit element that does not form a dual coupling, and thereby provides an effective EMI shielding for it.

FIELD OF THE DISCLOSURE

The present disclosure relates to circuit systems, and particularly to packaged circuit systems that include two or more circuit elements. The present disclosure further concerns a method for manufacturing a packaged circuit system that includes two or more circuit elements.

BACKGROUND OF THE DISCLOSURE

Electromagnetic (EM) field is defined as a property of space caused by the motion of an electric charge (Encyclopedia Britannica). A stationary charge generates an electric field in the surrounding space, and when the charge is moving, a magnetic field is also produced. An electric field can be produced also by a changing magnetic field. The mutual interaction of electric and magnetic fields produces an electromagnetic field.

Both man-made and natural sources of EM fields in the space tend to disturb operation of electrical devices. For example, sensors used in automotive systems are exposed to various changing fields, and need to be effectively shielded to avoid electromagnetic interference (EMI). Normally the devices are isolated by blocking EM fields with barriers made of conductive or magnetic materials. For example, a conventional microelectromechanical system (MEMS) device typically includes a MEMS die and an integrated circuit (IC) die, and the required shielding has been achieved by having a layer of metal on each side of the assembled MEMS and IC dies. In pre-molded plastic packages, shielding is often achieved by having a lead frame (die pad) on one side of the assembly and a grounded lid on the other side of the assembly. Over-molded plastic packages mainly use a so-called inverted die-pad, where the shield is provided by the die-pad on one side, and by a metallization on the printed wiring board (PWB) on the other side.

In recent years, also many leadless package technologies have been developed to streamline manufacturing processes and to reduce the size of the packages. However, the established leadless package technologies do not yet provide appropriate solutions for EMI shielding in challenging conditions, which are typical in automotive applications.

BRIEF DESCRIPTION OF THE DISCLOSURE

An object of the present disclosure is to introduce a packaged circuit system structure, in which effective EMI shielding for embedded circuit elements is provided in a simple manner.

The objects of the disclosure are achieved by a packaged circuit system structure and a manufacturing method, which are characterized by what is stated in the independent claims. The preferred embodiments of the disclosure are disclosed in the dependent claims.

In the solution, a side normally exposed to external EM fields is at least partially covered with a conductive layer, and one of the embedded circuit elements is arranged to form a dual coupling through an embedding bulk material, and thereby couple the conductive layer and a signal ground potential. The conductive layer in the signal ground potential thus provides an effective EMI shielding to circuit elements covered by it. The improved EMI shielding can be implemented with simple structural elements in an easily manufactured manner.

DETAILED DESCRIPTION OF THE DISCLOSURE

In the following, features of the invention will be described with a simple example of a device architecture with which various embodiments of the invention may be implemented. Only elements relevant for illustrating the embodiments are described in detail. Various components of integrated devices, which are generally known to a person skilled in the art, may not be specifically described herein.

The schematic ofFIG. 1illustrates a typical state of the art packaged circuit system structure. The structure includes one or more circuit element (dies) of possibly different origin (different wafers, designs, technologies).FIG. 1shows an exemplary fan-out wafer level packaging (FO-WLP) device, an integrated device100that can be formed by embedding circuit elements into a bulk material. The circuit elements may include one or more IC dies101, one or more other elements104and one or more conductive via—forming parts105, embedded in a low cost plastic material106. The other elements104may include, for example, MEMS dies or passive components, like optical elements, or any other electrical components or subassemblies.

The IC die101typically includes a substrate part103and a surface part102with circuit features and contact pads of the IC die. The surface part102of the IC die101and contact surfaces of the other embedded elements104are oriented similarly to be on, or aligned to one surface of the integrated device100. This one surface may be covered by a combination of insulator and conductor layers that form a re-distribution layer (RDL)107. The RDL is configured to provide selectively connections to elements that are in contact with conductive parts of the RDL. External connection elements, like solder bumps108are typically fabricated on top of the RDL, into positions that also enable contact with the conductive parts of the RDL. The RDL thus provides selectively connections between circuit elements of the element layer and the external connection elements108of the integrated device100. The back sides of the dies may either be embedded in the plastic (as the other element104and the IC die101) or may extend to alignment with the back surface of the integrated device (as the conductive via-forming part105). As fan-out wafer level packaging (FO-WLP) devices are diced from a larger entity, their vertical sides are of the low cost plastic material106, and therefore do not include any functional structures, like conducting leads.

FIG. 2shows the integrated FO-WLP device100ofFIG. 1in a soldering assembly to a printed wiring board (PWB)206. The effect of varying external electric fields to the integrated device is illustrated by an AC voltage source215. Capacitive coupling of the virtual voltage source215to each of the embedded dies104,101is illustrated by capacitances213and214, respectively. The substrate part103of the IC die101is usually connected to a potential that represents ground potential to signals of the integrated device. InFIG. 2, the surface part102of the IC die101is shown to include a contact pad212that is in electrical contact with the substrate part103. This contact pad212is aligned with a contact area and wiring211, which is part of the RDL107. The contact area and wiring211is connected to a signal ground250or equivalent potential on the PWB206. The redistribution layer RDL107thus provides an electrical connection to the signal ground potential250.

In this configuration, the substrate103of the IC die101forms a natural EMI shield for the circuit part102of the IC die. However, the other circuit elements104, like the MEMS dies, passive devices, and/or electrical subassemblies do not have such a natural shield. The bulk volume of the embedded dies may be connected to a relatively high impedance216(for example, via the RDL107of the integrated device100, the circuit part103of the IC die101, the solder bumps209and the PWB206, or via the RDL107of the integrated device100, the solder bumps208, PWB206and external impedances connected to the PWB). In such a case, a fraction of the voltage of the voltage source215appears between a circuit element and the signal ground. The magnitude of said voltage fraction depends on a voltage division by the capacitance213and the impedance216. This voltage fraction may sometimes be high enough to detrimentally affect the operation of the integrated device due to EMI.

FIG. 3illustrates an embodiment of a packaged circuit system structure that provides an improved EMI shielding to the embedded circuit elements and helps to avoid the described EMI effect. The packaged circuit system structure is hereinafter referred to as the integrated device300. The effect of varying external electric fields to the integrated device is again illustrated by a voltage source315. Capacitive coupling of the virtual voltage source315to each of the embedded dies304,301is further illustrated by capacitances313and317, respectively. The integrated device300includes a circuit layer320in which circuit elements301,304are embedded into a bulk material322. The integrated device300includes also external connection elements308,309, and a redistribution layer310configured to provide selectively connections between the circuit elements301,304of the element layer and the external connection elements308,309, as described above. Let us denote that the packaged circuit system structure has a first side324that includes the external connection elements308,309. The integrated device300includes also a conductive layer316, which is on a second side of integrated device. The second side is the side opposite to the first side of the integrated device. The conductive layer316at least partially covers the surface of the second side. In the example ofFIG. 3, the conductive layer covers the whole surface of the second side. In case of FO-WLP devices, the sides of the integrated device300between the first side324and the second side are of the bulk material322. In other words, the outer surface of the integrated device300between the first surface and the second surface does not include conductive parts to create a conductive path between the conductive layer and the redistribution layer.

At least one of the embedded circuit elements is now arranged to form a dual coupling through the bulk material. The dual coupling is formed of an electrical connection to a signal ground potential350, and an electrical connection to the conductive layer316of the integrated device300. In the exemplary embodiment ofFIG. 3, an IC die301is arranged to extend from the redistribution layer310of the integrated device300to the conductive layer316on the second side of the integrated device300. The IC die301includes a substrate part303and a surface part302. The substrate part303of the IC die is aligned to a surface of the circuit layer320, which surface is oriented towards the second side, and is thus exposed to and in contact with the conductive layer316. The surface part302of the IC die is aligned to form part of a surface of the circuit layer320, which surface is oriented towards the first side324. The IC die is thus exposed to and in contact with one or more conductive parts of the redistribution layer310. The conductive part of the redistribution layer310includes a contact area and wiring311to the signal ground potential350. The surface part302of the IC die301is again shown to include a contact pad312that is in electrical contact with the substrate part303of the IC die. As described withFIG. 2, this contact pad312is aligned with the contact area and wiring311of the redistribution layer307and is thereby connected to a signal ground350or equivalent potential on a printed wiring board306. Due to the low impedance contact between the conductive layer316and the substrate part303, the voltage of the conductive layer316is thus negligible and the conductive layer316remains practically at the signal ground potential.

The conductive layer316extends over the embedded circuit element it is in contact with for the dual coupling, here over the IC die301. In addition, the conductive layer316extends also over at least one embedded circuit element that does not form the dual coupling, here a MEMS die304. The expression extend over in this context means that the conductive layer316forms a conductive layer between the embedded circuit element and the external EM fields. InFIG. 3, the layers316,320,310of the integrated device300extend in a horizontal direction and the conductive layer316extends horizontally over the MEMS die304and thereby effectively shields it from the influence of the voltage source315, i.e. from the external EM fields and thus renders the capacitance313from the effective voltage source315to the MEMS die304close to zero, depending on the degree of extension of the coverage of the layer316over the die304

The conductive layer316layer may be of any conductive material. Advantageously, the conductive layer is a metal layer, formed of one metal material, or of multiple sub-layers of metal materials. An example of an advantageous sub-layered configuration includes a double layer structure that includes a layer of titanium (Ti) or titanium-tungsten (Ti/W) in combination with a layer of copper (Cu) or aluminum (Al). This conductive layer316is in immediate contact with the substrate part303. The electrical connection in the dual coupling may be an ohmic contact between the metal material of the conductive layer316and the silicon material of the substrate part303. Also a Schottky-barrier type contact between the metal material of the conductive layer316and the silicon material of the substrate part303may be applied. The Schottky-barrier type contact is adequate for the purpose since the interface capacitance of the Schottky-barrier will be many orders of magnitude higher than the capacitance317from the voltage source315to the conductive layer316and will present a low impedance contact at a high frequency.

Let us denote that a vertical dimension of the embedded circuit element that forms the dual coupling is the dimension perpendicular to the first surface and the second surface. At least part of the vertical dimension of the embedded circuit element301that forms the dual coupling is not of conductive material. The term conductive material refers herein to materials, the resistivity of which is in the order of 10−8to 10−7Ohmm. In case of circuit elements that include a substrate part and a surface part, the part of the vertical dimension of the embedded circuit element includes the substrate part. In case of a circuit element with uniform structure, like a semiconductor via, the part of the vertical dimension of the embedded circuit element includes the whole vertical extent of the via. The requirement relates to properties of the connection path from the conductive layer316to the signal ground350, as will be discussed in more detail withFIGS. 7 and 8.FIG. 4illustrates a further embodiment of a packaged circuit system structure, hereinafter referred to as the integrated device400. The elements ofFIG. 4by far correspond to the elements of theFIG. 3, so more detailed description on them may be referred from description ofFIG. 3. The integrated device400includes a circuit layer420in which circuit elements401,404are embedded into a bulk material. The integrated device400includes also external connection elements408,409, and a redistribution layer410configured to provide selectively connections between the circuit elements401,404of the element layer and the external connection elements408,409, as described above. A first side424if the integrated device includes external connection elements408,409. A conductive layer416is on a second side, opposite to the first side of the integrated device.

The integrated device400includes an IC die401and a MEMS die404. The IC die includes a substrate part403and a surface part402and forms a dual coupling, as described with the IC die ofFIG. 3. The MEMS die includes a device layer419and a substrate part418. In this embodiment, also the substrate part418of the MEMS die is aligned to form a surface of the circuit layer420and is thus exposed to and in contact with the conductive layer416. This will force the substrate part418of the MEMS die to the same near ground potential as the conductive layer416. This is allowed and even advantageous whenever the MEMS device has a layered structure in which a device layer419is on the front surface of the MEMS die, i.e. in the first side of the integrated device, and the device layer419is electrically isolated from the substrate part418. A MEMS device fabricated on a silicon on insulator (SOI) wafer has this kind of a structure by default. The conductive layer416and the substrate part403provide an effective EMI shielding to the device layer.

FIG. 5illustrates a further embodiment of a packaged circuit system structure, hereinafter referred to as the integrated device500. The elements ofFIG. 5by far correspond to the elements of theFIG. 3, so more detailed description on them may be referred from description ofFIG. 3. The integrated device500includes a circuit layer520in which circuit elements501,504are embedded in a bulk material. The integrated device500includes also external connection elements508,509, and a redistribution layer510configured to provide selectively connections between the circuit elements501,504of the element layer and the external connection elements508,509, as described above. A first side524if the integrated device includes external connection elements508,509. A conductive layer516is on a second side, opposite to the first side524of the integrated device.

The integrated device500includes an IC die501and a MEMS die504. The integrated device500includes also a via of semiconductor material forming part505, hereinafter referred to as a conductive via505. In this embodiment, the via505forms the dual coupling by means of an electrical connection to a signal ground potential, and an electrical connection to the conductive layer of the integrated device500. In the embodiment ofFIG. 5, the via505is arranged to extend from the redistribution layer510to the conductive layer516of the integrated device500. One end of the via505is aligned to form a surface of the circuit layer520and is thus exposed to and in contact with the conductive layer516. The other end of the via505is aligned to an opposite surface of the circuit layer520and is thus exposed to and in contact with the redistribution layer510that includes a contact area and wiring511to the signal ground potential. The conductive layer516extends horizontally over the IC die501and the MEMS die504and provides effective EMI shielding for them.

The flow chart ofFIG. 6illustrates stages of a method for manufacturing the packaged circuit system structure shown inFIGS. 3 to 5. The process may start by fabricating (stage600) a circuit layer wafer that includes one or more circuit elements of possibly different origin (different wafers, designs, technologies), embedded into a bulk material.

For example, fan-out wafer level packaging (FO-WLP) process, well known to a person skilled in the art may be applied. The bulk material may be thinned (stage602) from one surface of the circuit layer wafer such that at least one of the embedded circuit elements is exposed. A redistribution layer that includes an electrical connection to a signal ground potential is fabricated (stage604) on a surface of the circuit layer that is not thinned, and external connection elements are fabricated (stage606) on the redistribution layer. The redistribution layer thus provides selectively connections between circuit elements of the element layer and the external connection elements. A conductive layer is fabricated (stage608) on the thinned surface. The exposed embedded circuit element thus forms a dual coupling that includes an electrical connection to the signal ground potential, and an electrical connection to the conductive layer. The conductive layer is made to extend over at least one embedded circuit element that does not form a dual coupling.

FIGS. 3, 4 and 5show embodiments where the conductive layer is added on top of a FO-WLP packaged device and this shielding conductive layer is connected to the signal ground potential of a printed wiring board via one of the embedded structures within the device, via the redistribution layer on the first surface of the device, and via external connection elements, like solder spheres.

A common understanding is that the resistance of the connection between the conductive layer and the ground plane on the printed wiring board should be made as small as possible. This is true up to a certain frequency, but it has now been detected that there exists a frequency range where the contrary is true: the lower the resistance the poorer is the shielding effect.

It can be seen fromFIGS. 3, 4 and 5that the conductive layer and any ground potential plane on the printed wiring board form a capacitor, with parts of the FOWLP-device being located within the capacitor. Accordingly, in the connection path from the conductive layer to the ground potential plane there is, in addition to resistance, also an inductive component, produced especially by any narrow and long wiring section.FIG. 7shows a scheme of a circuit hereby formed, and the associated capacitive coupling of EMI.

The circuit of theFIG. 7can be analyzed, and the disturbing voltage UEMIsolved:

Where CPis the coupling capacitance from an external disturbing source, UEXTis the voltage of the external source, R is the resistance of the connection path, L is the inductance of the connection path, CPis the package capacitance and ω is the angular frequency of the disturbing voltage. In microelectromechanical devices, typical exemplary values for package capacitance and inductance of the connection path would be in the order of CP=0.4 pF and L=10 nH.FIG. 8shows the absolute value of the ratio (UEMICP)/(UEXTCC) plotted as a function of frequency for different values of R. This ratio is not the total attenuation but just the relative value with respect to very high frequencies, where the capacitive voltage division dominates.

The curves ofFIG. 8show, that at small values of R, like R=5, there is a marked resonance at about 2.5 GHz. in practice, such resonance is very detrimental since this band is commonly used by many communication systems like WiFi. At higher values of the resistance R, e.g. in the range from 50 to 150 ohms, this resonance becomes negligible, but then at the expense of higher signal levels at lower frequencies. But overall, the higher resistances produce much more acceptable results. The exact optimum values vary based on dimensions of the package, and no generally valid resistance values can be defined. The optimum value for the resistance of the connection path may vary between 20 ohms and 1 kohm.

The shielding arrangement shown inFIGS. 3, 4 and 5offer a novel way to include the resistance R in the conductive path. Since the substrate part303/403of the IC die inFIG. 3/4has most often high resistivity and the substrate contact has a limited size the resulting resistance can be easily brought to the desired range. If the resistance is dominated by the spreading resistance of one contact of finite size it will be

Where ρ is the resistivity of silicon and d is the diameter of the contact point. If ρ=5 ohmcm and d=100 μm then RSPRD=250 ohm, which is a very usable value for preventing the resonance ofFIG. 8. This same principle can be applied to the conductive via505ofFIG. 5. The conductive via may be made of semiconductor material, for example of silicon with resistivity and contact size selected to produce the desired resistance value according to equation 2.

It is apparent to a person skilled in the art that the order of some stages of the process may be varied, depending on the applied technologies. The intermediate step of thinning the surface of the circuit layer wafer provides an easy way to expose one or more of the embedded circuit elements to be connected to the ground potential from the side of their substrate part.

As technology advances, the basic idea of the invention can be implemented in various ways. The invention and its embodiments are therefore not restricted to the above examples, but they may vary within the scope of the claims.