Array substrate assembly, method of manufacturing array substrate assembly, display panel and display apparatus

The present disclosure relates to an array substrate assembly, a method of manufacturing the array substrate assembly, a display panel and a display apparatus. An array substrate assembly includes: a substrate; a first conducting wire on the substrate; a first insulating layer on the first conducting wire; a second conducting wire on the first insulating layer, wherein orthogonal projections of the first conducting wire and the second conducting wire on the substrate at least partly overlap, and at least one of the first conducting wire and the second conducting wire is constituted by a plurality of conducting segments arranged discontinuously; and a connection part configured to electrically connect adjacent ones of the conducting segments of the first conducting wire or the second conducting wire.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a Section 371 National Stage Application of International Application No. PCT/CN2017/093690, filed on 20 Jul. 2017, entitled “ARRAY SUBSTRATE ASSEMBLY, METHOD OF MANUFACTURING ARRAY SUBSTRATE ASSEMBLY, DISPLAY PANEL AND DISPLAY APPARATUS”, which has not yet published, which claims priority to Chinese Application No. 201610876795.1, filed on 30 Sep. 2016, incorporated herein by reference in their entirety.

BACKGROUND

1. Technical Field

At least one embodiment of the present disclosure relates to an array substrate assembly, a method of manufacturing the array substrate assembly, a display panel and a display apparatus.

2. Description of the Related Art

In a structure of an array substrate assembly, whether in a display region or in a peripheral region such as a test region (shorting bar), orthogonal projections of wirings, such as a gate layer wiring and a source and drain layer wiring, on a substrate at least partly overlap. Although an insulating layer is formed between these wirings, the longer wirings tend to cause an accumulation of static electricity, which will give rise to an electrostatic discharge (ESD) in an area where the orthogonal projections of wirings on the substrate overlap in a sequent process.

SUMMARY

In accordance with an aspect of the present disclosure, there is provided an array substrate assembly, comprising: a substrate; a first conducting wire on the substrate; a first insulating layer on the first conducting wire; a second conducting wire on the first insulating layer, wherein orthogonal projections of the first conducting wire and the second conducting wire on the substrate at least partly overlap, and at least one of the first conducting wire and the second conducting wire is constituted by a plurality of conducting segments arranged discontinuously; and a connection part configured to electrically connect adjacent ones of the conducting segments of the first conducting wire or the second conducting wire.

In embodiments of the present disclosure, the first conducting wire comprises a first conducting segment and a second conducting segment which are arranged discontinuously, and the second conducting wire is continuous.

In embodiments of the present disclosure, the array substrate assembly further comprises a second insulating layer formed on the second conducting wire and an exposed surface of the first insulating layer.

In embodiments of the present disclosure, the array substrate assembly further comprises a first via hole and a second via hole which pass through the first insulating layer and the second insulating layer, the connection part electrically connect the first conducting segment and the second conducting segment of the first conducting wire through the first via hole and the second via hole.

In embodiments of the present disclosure, the array substrate assembly further comprises: a third conducting wire on the second insulating layer; a third via hole passing through the second insulating layer and exposing the second conducting wire, wherein an orthogonal projection of the third via hole on the substrate is located within an area where the orthogonal projections of the first conducting wire and the second conducting wire on the substrate overlap; a fourth via hole passing through the first insulating layer and the second insulating layer and exposing the first conducting segment of the first conducting wire, an orthogonal projection of the first conducting segment on the substrate and the orthogonal projection of the second conducting wire on the substrate overlapping, wherein: the third conducting wire is electrically connected to the second conducting wire and the first conducting wire through the third via hole and the fourth via hole, respectively.

In embodiments of the present disclosure, the first conducting wire is located in the same layer as a gate line of the array substrate assembly, and the second conducting wire is located in the same layer as a data line of the array substrate assembly.

In embodiments of the present disclosure, the first conducting wire, the second conducting wire, the third conducting wire, and the connection part are located in a peripheral region of the array substrate assembly.

In embodiments of the present disclosure, the first conducting wire is formed of chromium, a chromium alloy material, a molybdenum tantalum alloy, aluminum, or an aluminum alloy material, the second conducting wire is formed of chromium, aluminum, or an aluminum alloy material, the third conducting wire is formed of indium tin oxide, the connection part is formed of indium tin oxide, the first insulating layer is formed of silicon oxide, silicon nitride, or aluminum oxide, the second insulating layer is formed of silicon nitride.

In accordance with another aspect of the present disclosure, there is provided a method of manufacturing an array substrate assembly, comprising: forming a first conducting wire on a substrate; forming a first insulating layer on the first conducting wire; forming a second conducting wire on the first insulating layer, wherein orthogonal projections of the first conducting wire and the second conducting wire on the substrate at least partly overlap, and at least one of the first conducting wire and the second conducting wire is constituted by a plurality of conducting segments arranged discontinuously; and forming a connection part configured to electrically connect adjacent ones of the conducting segments of the first conducting wire or the second conducting wire.

In embodiments of the present disclosure, the first conducting wire is formed into a first conducting segment and a second conducting segment which are arranged discontinuously, and the second conducting wire is formed to be continuous.

In embodiments of the present disclosure, the method further comprises: forming a second insulating layer on the second conducting wire and an exposed surface of the first insulating layer.

In embodiments of the present disclosure, the forming the connection part comprises: forming a first via hole and a second via hole which pass through the first insulating layer and the second insulating layer, wherein the first via hole and the second via hole expose the first conducting segment and the second conducting segment of the first conducting wire, respectively; forming a conducting layer on a surface of the second insulating layer and in the first via hole and the second via hole; and patterning the conducting layer to form the connection part which electrically connects the first conducting segment and the second conducting segment through the first via hole and the second via hole.

In embodiments of the present disclosure, the method further comprises: forming a third via hole and a fourth via hole prior to the forming the conducting layer, wherein the third via hole passes through the second insulating layer and exposes the second conducting wire, and an orthogonal projection of the third via hole on the substrate is located within an area where the orthogonal projections of the first conducting wire and the second conducting wire on the substrate overlap, the fourth via hole passes through the first insulating layer and the second insulating layer and exposes the first conducting segment of the first conducting wire, and an orthogonal projection of the first conducting segment on the substrate and the orthogonal projection of the second conducting wire on the substrate overlap, wherein the conducting layer is further formed in the third via hole and the fourth via hole, and the patterning the conducting layer further comprises forming a third conducting wire which electrically connects the second conducting wire and the first conducting wire through the third via hole and the fourth via hole.

In embodiments of the present disclosure, the first conducting wire and a gate line of the array substrate assembly are formed in the same layer, and the second conducting wire and a data line of the array substrate assembly are formed in the same layer.

In embodiments of the present disclosure, the first conducting wire, the second conducting wire, the third conducting wire, and the connection part are formed in a peripheral region of the array substrate assembly.

In embodiments of the present disclosure, the first conducting wire is formed of chromium, a chromium alloy material, a molybdenum tantalum alloy, aluminum, or an aluminum alloy material, the second conducting wire is formed of chromium, aluminum, or an aluminum alloy material, the third conducting wire is formed of indium tin oxide, the connection part is formed of indium tin oxide, the first insulating layer is formed of silicon oxide, silicon nitride, or aluminum oxide, the second insulating layer is formed of silicon nitride.

In accordance with a further aspect of the present disclosure, there is provided a display panel comprising: the array substrate assembly according to the embodiments of the present disclosure.

In accordance with a still another aspect of the present disclosure, there is provided a display apparatus comprising the display panel according to the embodiments of the present disclosure.

DETAILED DESCRIPTION OF THE EMBODIMENTS

In order that objects, technical solutions and advantages of embodiments of the present disclosure become more apparent, the embodiments of the present disclosure will be described in detail with reference to the accompanying drawings as below. Apparently, the described embodiments are only some of the embodiments of the present disclosure rather than all of the embodiments of the present disclosure.

Wording for describing feature(s), advantage(s) or the like throughout the present description does not imply that all of the feature(s) and advantage(s) that can be achieved by the present disclosure should be or are within any single embodiment of the present disclosure. On the contrary, it is to be understood that the wording relating to the feature(s) and advantage(s) means that specific feature(s), advantage(s), or characteristic(s) described in combination with the embodiment is/are included in at least one embodiment of the present disclosure. Therefore, discussion and similar wording for the features and advantages throughout the present description may refer to the same embodiment, but do not necessarily refer to the same embodiment. In addition, feature(s), advantage(s) and characteristic(s) of the present disclosure to be described may be combined in any appropriate manner in one or more embodiments. It would be appreciated by those skilled in the art that the present disclosure may be practiced without one or more specific feature(s) or advantage(s) of a particular embodiment. In other examples, additional feature(s) and advantage(s) may be achieved in some embodiments, and do not necessarily appear in all of the embodiments of the present disclosure.

In the description of the present disclosure, it is to be noted that orientations or positional relationships indicated by terms such as “upper”, “lower”, “top”, and “bottom” are based on orientations or positional relationships shown in the accompanying drawings, are merely used to facilitate the description of the present disclosure and simplification of the description, but do not indicate or imply that a device or an element of which an orientation or positional relationship is indicated must have the particular orientation and must be configured and operated in the particular orientation. Therefore, the orientations or positional relationships should not be construed to limit the present disclosure.

Furthermore, in the description of the present disclosure, “plurality of” means two or more unless otherwise described.

Embodiments of the present disclosure provide an array substrate assembly, comprising: a substrate; a first conducting wire on the substrate; a first insulating layer on the first conducting wire; a second conducting wire on the first insulating layer, wherein orthogonal projections of the first conducting wire and the second conducting wire on the substrate at least partly overlap, and at least one of the first conducting wire and the second conducting wire is constituted by a plurality of conducting segments arranged discontinuously; and a connection part configured to electrically connect adjacent ones of the conducting segments of the first conducting wire or the second conducting wire. In order to facilitate understanding of the embodiments of the present disclosure, specific examples of the array substrate assembly are illustrated as below.

The array substrate assembly and the method of manufacturing the array substrate assembly according to at least one of the embodiments of the present disclosure can avoid, an accumulation of static electricity which is caused due to the long first or second conducting wire in the case where orthogonal projections of the first conducting wire and the second conducting wire on the substrate at least partly overlap and the insulating layer is formed between the first conducting wire and the second conducting wire, and an electrostatic discharge which occurs when accumulated static electricity is conducted to a position where the orthogonal projections of the first conducting wire and the second conducting wire on the substrate overlap.

FIG. 1shows a schematic partial plan view of an example of an array substrate assembly according to an embodiment of the present disclosure.

As shown inFIG. 1, the array substrate assembly comprises a first conducting wire200, a second conducting wire400, and a connection part710. Orthogonal projections of the first conducting wire200and the second conducting wire400in a vertical direction partly overlap. The first conducting wire200comprises a first conducting segment201and a second conducting segment202which are arranged discontinuously, and the connection part710electrically connect the first conducting segment201and the second conducting segment202.

FIG. 2shows a schematic partial sectional view of the example of the array substrate assembly according to the embodiment of the present disclosure. Specifically,FIG. 2shows a schematic partial sectional view taken along a longitudinal direction of the first conducting wire200inFIG. 1.

As shown inFIG. 2, the array substrate assembly further comprises a substrate100and a first insulating layer300. The first conducting wire200is located on the substrate100, the first insulating layer300is located on the first conducting wire200, and the second conducting wire400is located on the first insulating layer300. The orthogonal projections of the first conducting wire200and the second conducting wire400on the substrate100partly overlap.

As shown inFIG. 1, the first conducting wire200comprises a first conducting segment201and a second conducting segment202which are arranged discontinuously, and the second conducting wire400is continuous. For the sake of brevity,FIG. 1andFIG. 2show only two conducting segments of the first conducting wire200which are arranged discontinuously, but the present disclosure is not limited to this and the first conducting wire200may also comprise more than two conducting segments arranged discontinuously.

In this way, the first conducting wire is constituted by a plurality of conducting segments arranged discontinuously. In other words, the first conducting wire is not continuous, thereby avoiding an accumulation of static electricity which is caused due to a long conducting wire, and an electrostatic discharge which occurs when accumulated static electricity is conducted to an area where the orthogonal projections of the first conducting wire and the second conducting wire on the substrate overlap, during manufacturing of for example a passivation insulating layer.

As shown inFIG. 2, the array substrate assembly further comprises a second insulating layer500formed on the second conducting wire400and an exposed surface of the first insulating layer300. The exposed surface of the first insulating layer300refers to a surface of the first insulating layer300which is not covered by the second conducting wire400.

As shown inFIG. 1, the connection part710electrically connect the first conducting segment201and the second conducting segment202of the first conducting wire200through the first via hole610and the second via hole620.

More specifically, as shown inFIG. 1andFIG. 2, the array substrate assembly further comprises a first via hole610and a second via hole620which pass through the first insulating layer300and the second insulating layer500. The connection part710electrically connect the first conducting segment201and the second conducting segment202of the first conducting wire200through the first via hole610and the second via hole620. The first via hole610and the second via hole620expose the first conducting segment201and the second conducting segment202of the first conducting wire200, respectively.

The schematic partial plan view of the array substrate assembly shown inFIG. 1may be for example a schematic plan view of, for example, a test region (shorting bar) of the array substrate assembly. In detection of the array substrate assembly, quality of the array substrate assembly is detected by loading test signals to the test region.

As shown inFIG. 1, the array substrate assembly further comprises a third conducting wire720, a third via hole630and a fourth via hole640. The third conducting wire720electrically connects the second conducting wire400and the first conducting wire200through the third via hole630and the fourth via hole640.

More specifically, as shown inFIG. 2, the third conducting wire720electrically connect the second conducting wire400and the first conducting wire200through the third via hole630passing through the second insulating layer500and the fourth via hole640passing through the first insulating layer300and the second insulating layer500.

In particular, as shown inFIG. 1andFIG. 2, an orthogonal projection of the third via hole630on the substrate is located within an area where the orthogonal projections of the first conducting wire200and the second conducting wire400on the substrate100overlap and the third via hole630exposes the second conducting wire400; and the fourth via hole640exposes the first conducting segment201of the first conducting wire200, and an orthogonal projection of the first conducting segment201on the substrate100and the orthogonal projection of the second conducting wire400on the substrate100overlap.

The schematic partial plan view of the array substrate assembly shown inFIG. 1is a schematic plan view of, for example, a test region (shorting bar) of the array substrate assembly, but does not show a circuit in for example a display region of the array substrate assembly. However, it would be appreciated by those skilled in the art that the first conducting wire200may be located in the same layer as a gate line of the array substrate assembly, and the second conducting wire400may be located in the same layer as a data line of the array substrate assembly.

A circuit in the array substrate assembly, for example in the test region of the array substrate assembly, is generally disposed in a peripheral region of the array substrate assembly. Therefore, it would be appreciated by those skilled in the art that the first conducting wire200, the second conducting wire400, the third conducting wire720and the connection part710may be located in the peripheral region of the array substrate assembly.

In the present embodiment, the first conducting wire200may be formed of chromium, chromium alloy material, molybdenum tantalum alloy, aluminum, or aluminum alloy material.

In the present embodiment, the second conducting wire400may be formed of chromium, aluminum, or aluminum alloy material.

In the present embodiment, the third conducting wire720may be formed of indium tin oxide.

In the present embodiment, the connection part710may be formed of indium tin oxide.

In the present embodiment, the first insulating layer300may be formed of silicon oxide, silicon nitride, or aluminum oxide.

In the present embodiment, the second insulating layer500may be formed of silicon nitride.

Embodiments of the present disclosure also provide a method of manufacturing an array substrate assembly, and the method comprises: forming a first conducting wire on a substrate; forming a first insulating layer on the first conducting wire; forming a second conducting wire on the first insulating layer, wherein orthogonal projections of the first conducting wire and the second conducting wire on the substrate at least partly overlap, and at least one of the first conducting wire and the second conducting wire is constituted by a plurality of conducting segments arranged discontinuously; and forming a connection part configured to electrically connect adjacent ones of the conducting segments of the first conducting wire or the second conducting wire. In order to facilitate understanding of the embodiments of the present disclosure, specific examples of the method of manufacturing the array substrate assembly are illustrated as below.

FIG. 3shows a flow diagram of an example of a method of manufacturing an array substrate assembly according to an embodiment of the present disclosure.

As shown inFIG. 3, in a step S10, a first conducting wire is formed on a substrate.

FIG. 4Ashows a schematic view of a first conducting wire formed in the example of the method of manufacturing the array substrate assembly according to the embodiment of the present disclosure.

As shown inFIG. 4A, the first conducting wire200is formed on the substrate100. The first conducting wire200is formed into a first conducting segment201and a second conducting segment202which are arranged discontinuously. For example, the first conducting wire200constituted by the plurality of conducting segments arranged discontinuously may be formed by forming a conducting layer on the substrate100and patterning the conducting layer. It would be appreciated by those skilled in the art that the patterning refers to a process technology which includes steps such as a photoresist coating, an exposing, a developing, an etching, a photoresist stripping, and the like.

For the sake of brevity,FIG. 4Ashows only two conducting segments of the first conducting wire200which are arranged discontinuously, but the present disclosure is not limited to this and the first conducting wire200may also comprise more than two conducting segments arranged discontinuously.

In this way, the first conducting wire is constituted by a plurality of conducting segments arranged discontinuously. In other words, the first conducting wire is not continuous, thereby avoiding an accumulation of static electricity which is caused due to a long conducting wire, and an electrostatic discharge which occurs when accumulated static electricity is conducted to an area where the orthogonal projections of the first conducting wire and the second conducting wire on the substrate overlap, during manufacturing of for example a passivation insulating layer.

As shown inFIG. 3, in a step S20, a first insulating layer is formed on the first conducting wire.

FIG. 4Bshows a schematic view of a first insulating layer formed in the example of the method of manufacturing the array substrate assembly according to the embodiment of the present disclosure.

As shown inFIG. 4B, the first insulating layer300is formed on the first conducting wire200, on the substrate100on which the step S10has been performed. The first insulating layer300insulates the first conducting segment and the second conducting segment from each other.

As shown inFIG. 3, in a step S30, a second conducting wire is formed on the first insulating layer. Orthogonal projections of the first conducting wire and the second conducting wire on the substrate partly overlap.

FIG. 4Cshows a schematic view of a second conducting wire formed in the example of the method of manufacturing the array substrate assembly according to the embodiment of the present disclosure.

As shown inFIG. 4C, the second conducting wire400is formed on the first insulating layer300, on the substrate100on which the step S20has been performed. The orthogonal projections of the first conducting wire200and the second conducting wire400on the substrate partly overlap. For example, the second conducting wire400may be formed by forming a conducting layer on the first insulating layer300and patterning the conducting layer. For example, the second conducting wire400may be formed to be continuous.

As shown inFIG. 3, in a step S40, a second insulating layer is formed on the second conducting wire and an exposed surface of the first insulating layer. The exposed surface of the first insulating layer refers to a surface of the first insulating layer which is not covered by the second conducting wire.

FIG. 4Dshows a schematic view of a second insulating layer formed in the example of the method of manufacturing the array substrate assembly according to the embodiment of the present disclosure.

As shown inFIG. 4D, the second insulating layer500is formed on the second conducting wire400and the exposed surface of the first insulating layer300, on the substrate100on which the step S30has been performed. The exposed surface of the first insulating layer300refers to a surface of the first insulating layer300which is not covered by the second conducting wire400.

As shown inFIG. 3, in a step S50, a first via hole and a second via hole which pass through the first insulating layer and the second insulating layer are formed to expose the first conducting segment and the second conducting segment of the first conducting wire, respectively.

If the first conducting wire and the second conducting wire belong to the circuit in the array substrate assembly, for example in the test region of the array substrate assembly, a third via hole passing through the second insulating layer and a fourth via hole passing through the first insulating layer and the second insulating layer may also be formed. An orthogonal projection of the third via hole on the substrate is located within an area where the orthogonal projections of the first conducting wire and the second conducting wire on the substrate overlap; and the third via hole exposes the second conducting wire, the fourth via hole exposes the first conducting segment of the first conducting wire, and an orthogonal projection of the first conducting segment on the substrate and the orthogonal projection of the second conducting wire on the substrate overlap.

FIG. 4Eshows a schematic view of a via hole formed in the example of the method of manufacturing the array substrate assembly according to the embodiment of the present disclosure.

For example, as shown inFIG. 4E, the first via hole610and the second via hole620which pass through the first insulating layer300and the second insulating layer500, the third via hole630passing through the second insulating layer500, and the fourth via hole640passing through the first insulating layer300and the second insulating layer500are formed, on the substrate100on which the step S40has been performed. The first via hole610and the second via hole620expose the first conducting segment and the second conducting segment of the first conducting wire200; an orthogonal projection of the third via hole630on the substrate is located within an area where the orthogonal projections of the first conducting wire200and the second conducting wire400on the substrate100overlap, and the third via hole630exposes the second conducting wire400; and the fourth via hole640exposes the first conducting segment of the first conducting wire200, and the orthogonal projections of the first conducting segment and the second conducting wire400on the substrate100overlap. For example, the via holes may be formed in the insulating layers by patterning.

As shown inFIG. 3, in a step S60, a conducting layer is formed on a surface of the second insulating layer and in the first via hole and the second via hole.

If the first conducting wire and the second conducting wire belong to the circuit in the array substrate assembly, for example in the test region of the array substrate assembly, the conducting layer may further be formed in the third via hole and the fourth via hole.

FIG. 4Fshows a schematic view of a conducting layer formed in the example of the method of manufacturing the array substrate assembly according to the embodiment of the present disclosure.

For example, as shown inFIG. 4F, the conducting layer700is formed on the surface of the second insulating layer500and in the first via hole610and the second via hole620, on the substrate100on which the step S50has been performed. The conducting layer700may be further formed in the third via hole630and the fourth via hole640.

As shown inFIG. 3, in a step S70, the conducting layer is patterned to form the connection part which electrically connects the first conducting segment and the second conducting segment through the first via hole and the second via hole.

If the first conducting wire and the second conducting wire belong to the circuit in the array substrate assembly, for example in the test region of the array substrate assembly, the patterning the conducting layer further comprises forming a third conducting wire which electrically connects the second conducting wire and the first conducting wire through the third via hole and the fourth via hole.

FIG. 4Gshows a schematic view of the conducting layer patterned in the example of the method of manufacturing the array substrate assembly according to the embodiment of the present disclosure.

For example, as shown inFIG. 4G, on the substrate100on which the step S60has been performed, the connection part710which electrically connects the first conducting segment and the second conducting segment through the first via hole610and the second via hole620is formed by patterning the conducting layer700shown inFIG. 4F, and the third conducting wire720which electrically connects the second conducting wire400and the first conducting wire200through the third via hole630and the fourth via hole640is further formed by patterning the conducting layer700shown inFIG. 4F.

For the case where the first conducting wire and the second conducting wire belong to the circuit in the array substrate assembly, for example in the test region of the array substrate assembly, it would be appreciated by those skilled in the art that the first conducting wire200and a gate line of the array substrate assembly may be formed in the same layer, and the second conducting wire500and a data line of the array substrate assembly may be formed in the same layer.

A circuit in the array substrate assembly, for example in the test region of the array substrate assembly is generally disposed in a peripheral region of the array substrate assembly. Therefore, it would be appreciated by those skilled in the art that the first conducting wire200, the second conducting wire400, the third conducting wire720and the connection part710may be formed in the peripheral region of the array substrate assembly.

In the present embodiment, the first conducting wire200may be formed of chromium, chromium alloy material, molybdenum tantalum alloy, aluminum, or aluminum alloy material.

In the present embodiment, the second conducting wire400may be formed of chromium, aluminum, or aluminum alloy material.

In the present embodiment, the third conducting wire720may be formed of indium tin oxide.

In the present embodiment, the connection part710may be formed of indium tin oxide.

In the present embodiment, the first insulating layer300may be formed of silicon oxide, silicon nitride, or aluminum oxide.

In the present embodiment, the second insulating layer500may be formed of silicon nitride.

In a manufacturing process of the array substrate assembly, in addition to the above steps, other necessary process steps are involved. Specific implementation of the other process steps would be known by those skilled in the art according to prior art and thus will be no longer described for the sake of brevity.

Embodiments of the present disclosure also provide a display panel2000which comprises the array substrate assembly1000according to the embodiments of the present disclosure, as shown inFIG. 5.

Embodiments of the present disclosure further provide a display apparatus3000which comprises the display panel2000according to the embodiments of the present disclosure, as shown inFIG. 5. The display apparatus may comprise any products or parts having display function such as a liquid crystal panel, an electronic paper, an OLED (organic light-emitting device) panel, a mobile phone, a tablet computer, a TV, a display, a notebook computer, a digital frame, and navigator.

While the exemplary embodiments of the present disclosure have been described with reference to the drawings, they are only illustrative and schematic description for explaining a concept of the present disclosure, rather than a limitation on aspects of the present disclosure. It should be appreciated by those skilled in the art that various modifications and changes may be made in the embodiments without departing from the spirit and principles of the present disclosure, and all of these modifications and changes fall within the protection scope of the present disclosure.