Apparatus and methods for lock detection for semi-digital and fully-digital clock data recovery

One embodiment relates to a lock detection circuit. The lock detection circuit includes at least a dither detection circuit and a lock filter. The dither detection circuit maintains a bi-directional count based on early and late signals from a sampler circuit and asserts a non-lock signal if the bi-directional count reaches either a positive non-lock assertion threshold or a negative non-lock assertion threshold. The lock filter increments a lock filter count for each sample and outputs a lock-initiated signal when the lock filter count reaches a pre-set maximum value. The maximum value of the lock filter count is greater than the non-lock assertion thresholds. Other embodiments and features are also disclosed.

BACKGROUND

1. Technical Field

The present invention relates generally to data communications.

2. Description of the Background Art

High-speed data links are used to communicate data between devices in a system. Serial interface protocols have been developed at increasingly fast data rates for such high-speed links. Examples of industry-standard protocols for serial interfaces include PCI Express® (Peripheral Component Interconnect Express), XAUI (X Attachment Unit Interface), sRIO (serial Rapid IO), and others.

Market demands for transceiver data rates for high-speed data links continue to increase. In recent years, the demanded increase in transceiver data rates has exceeded gains based on process improvements alone. As such, improvements in transceiver design are also needed to provide the desired increases in speed.

SUMMARY

One embodiment relates to a lock detection circuit. The lock detection circuit includes at least a dither detection circuit and a lock filter. The dither detection circuit maintains a bi-directional count based on early and late signals from a sampler circuit and asserts a non-lock signal if the bi-directional count reaches either a positive non-lock assertion threshold or a negative non-lock assertion threshold. The lock filter increments a lock filter count for each sample and outputs a lock-initiated signal when the lock filter count reaches a pre-set maximum value. The maximum value of the lock filter count is greater than the non-lock assertion thresholds.

Another embodiment relates to a method for detecting a lock state of a semi-digital or digital clock data recovery circuit. A bi-directional count is maintained based on early and late signals from a sampler circuit, and a non-lock signal is asserted if the bi-directional count reaches either a positive non-lock assertion threshold or a negative non-lock assertion threshold. In addition, a lock filter count is incremented for each sample, and a lock-initiated signal is output when the lock filter count reaches a pre-set maximum value.

Other embodiments and features are also disclosed.

DETAILED DESCRIPTION

Clock data recovery (CDR) circuits may be categorized as analog CDR circuits, semi-digital CDR circuits, and fully-digital CDR circuits. Analog CDR circuits are typically based on phase-locked loop (PLL) circuits. Semi-digital CDR circuits are interpolator based. Fully-digital CDR circuits typically utilize a digitally controlled oscillator.

Conventional lock detection circuitry for an analog CDR circuit measures the frequency offset difference between the reference clock and recovered clock to detect when the CDR circuit has achieved a lock state. However, when this method is used for a semi-digital CDR circuit, such as an interpolator-based CDR circuit, it cannot function properly because the input reference clock and the recovered clock come from the same source. Similarly, the method mentioned above is not useful for lock detection for a fully-digital CDR circuit.

The present disclosure provides innovative technique for lock detection for semi-digital and fully-digital clock and data recovery (CDR) circuits. As observed by the applicant, the “early” and “late” outputs from an interpolator-based CDR's sampler will toggle interchangeably when the CDR is in a lock state. The present disclosure utilizes this behavior to determine the state of the CDR. The presently-disclosed lock detection technique may be implemented using a dither detection circuit and a lock filter, where the lock filter may be an n-bit binary counter.

The technique disclosed herein has various benefits and advantages. First, it solves a need to detect a lock state in semi-digital (interpolator-based) CDR circuits. Second, the technique may be used to detect a lock state in both semi-digital and fully-digital CDR circuits. Third, the technique requires a small area for its circuitry and consumes a small amount of power.

FIG. 1depicts a clock and data recovery (CDR) circuit100that includes a lock detection circuit110in accordance with an embodiment of the invention. As shown, the CDR circuit100is interpolator based and includes a circuit loop that is formed by a sampler (phase detector) circuit102, a digital filter circuit104, a phase interpolator (PI) control circuit106, and a phase interpolator circuit108.

The sampler circuit102may be configured to receive an incoming serial data signal (DataIn) that may be at a data rate of X gigabits per second. The sampler circuit102may be configured to sample the input data signal to determine the position of a sampling clock with respect to the input data signal. The sampling clock may be generated by the phase interpolator circuit108. As shown inFIG. 1, the sampling clock may include four clock signals, shown as clk0, clk90, clk180, and clk270, which have a phase difference of 90 degrees (π/2 radians) between them.

If the sampling clock is leading the input data signal, then an early signal may be asserted (set to high) by the sampler circuit102; and, if the sampling clock is lagging the input data signal, then a late signal may be asserted (set to high) by the sampler circuit102. The early and late signals together may be referred to as the feedback signal.

The feedback signal is provided to the digital filter circuit104. Typically, the digital filter may be an N-bit binary counter. The digital filter circuit104may be arranged to compensate for the latency of the CDR loop and to reduce loop dithering. The digital filter circuit104may generate a filtered version of the feedback signal (i.e. a filtered feedback signal). The filtered feedback signal may include a down signal which is the filtered version of the early signal and an up signal which is the filtered version of the late signal. The digital filter circuit104may be programmable to a plurality of filter settings.

The filtered feedback signal may be received by the PI controller106. The PI controller106may be arranged to generate an interpolator control signal based on the filtered feedback signal. The interpolator control signal may control the phase interpolator108to shift the phase of the sampling clock up or down or to maintain (i.e. not shift) the current phase of the sampling clock.

If the sampling clock is consistently early (leading) with respect to the input data signal, then the PI controller106will receive a down signal and will control the phase interpolator108to shift down the phase of the sampling clock. On the other hand, if the sampling clock is consistently late (lagging) with respect to the input data signal, then the PI controller106will receive an up signal and will control the phase interpolator108to shift up the phase of the sampling clock.

The phase interpolator circuit108may be arranged to receive a reference clock and generate the sampling clock. The reference clock may be received from a phase locked loop (PLL) or a delay locked loop (DLL) circuit. As shown inFIG. 1, the reference clock may include four clock signals, shown as clk0i, clk90i, clk180i, and clk270i, which have a phase difference of 90 degrees (π/2 radians) between them. The phase interpolator circuit108may generate the clock signals of the sampling clock (the recovered clock) by interpolation of the clock signals of the reference clock.

In accordance with an embodiment of the invention, the CDR circuit100further includes a lock detection circuit110. The lock detection circuit110is arranged to generate a lock signal which indicates when the CDR circuit100is in a lock state. As shown, the lock detection circuit110may receive the early and late signals from the sampler102.

FIG. 2depicts a lock detection circuit110in accordance with an embodiment of the invention. As shown, the lock detection circuit110may include a dither detection circuit202, a lock filter204, and a D flip-flop (DFF)206.

The dither detection circuit202receives the early and late signals from the sampler102. The output of the dither detection circuit202is a non-lock signal that may be asserted to the reset ports of the lock filter204and the DFF206. One embodiment of the dither detection circuit202is described below in relation toFIG. 3.

The lock filter204may be implemented, for example, as an n-bit binary counter. The output of the lock filter204is a lock-initiated signal that may be asserted to the clock port of the DFF206. The data input port of the DFF206may be connected to a supply voltage (VCC), and the data output port of the DFF206may generate the lock signal. The lock signal indicates when the CDR circuit100is in its lock state.

Functionally, the dither detection circuit202monitors the early and late signals from the sampler102to determine if they are toggling interchangeably (one after the other), or approximately interchangeably, such that a bi-directional count is within a range around the zero count. If the sampler's output is determined to be not toggling interchangeably by the bi-directional count reaching positive or negative non-lock thresholds, then the dither detection circuit202will assert the non-lock signal so as to reset the DFF206(such that the lock is de-asserted) and also reset the count (LFC) of the lock filter204.

The lock filter204ensures that the sampler's output has been toggling interchangeably for some number of cycles, n, before the lock signal is asserted. The lock-initiated signal will be asserted by the lock filter204once the LFC reaches n. The lock-initiated signal will not be asserted if the lock filter204is reset before the LFC reaches n.

The lock signal will be asserted by the DFF206once it is triggered by the lock-initiated signal from the lock filter204. The lock signal will be de-asserted by the DFF206upon receiving the non-lock signal from the dither detection circuit202.

FIG. 3depicts a dither detection circuit202in accordance with an embodiment of the invention. As shown, the dither detection circuit202may include a bi-directional counter310, a polarity detection circuit365, and polarity select logic380.

A five-bit implementation of a bi-directional counter310is depicted inFIG. 3and described herein. Other implementations of the bi-directional counter310are also possible. The bi-directional counter310need not necessarily use five bits and may instead use a larger or smaller number of bits than five. The count of the bi-directional counter310may be referred to as the bi-directional count (BDC) to distinguish it from the lock filter count (LFC).

The bi-directional counter310receives the late and early signals into exclusive OR (XOR) gate312. The output of XOR gate312is provided to the data input port of T flip-flop (TFF)320. The Q output of TFF320may be used as the bit0output of the bi-directional counter310. The Q output of TFF320is also provided to a first input of AND gate324, and the Qbar output of TFF320is provided to a first input of AND gate322. In addition, the early signal is inverted by inverter314, and the late signal and inverted early signal are provided to the inputs of AND gate316. The output of AND gate316is inverted by inverter318. The output of AND gate316is provided to a second input of AND gate322, and the inverted output of AND gate316is provided to a second input of AND gate324. The outputs of AND gates322and324are provided to the inputs of OR gate326.

The output of XOR gate312is also provided to a first input of AND gate328, and the output of OR gate326is provided to a second input of AND gate328. The output of AND gate328is provided to the data input of TFF330. The Q output of TFF330may be used as the bit1output of the bi-directional counter310. The Q output of TFF330is also provided to a first input of AND gate334, and the Qbar output of TFF330is provided to a first input of AND gate332. In addition, the output of AND gate322is provided to a second input of AND gate332, and the output of AND gate324is provided to a second input of AND gate334. The outputs of AND gates332and334are provided to the inputs of OR gate336.

The output of XOR gate312is also provided to a first input of AND gate338, and the output of OR gate336is provided to a second input of AND gate338. The output of AND gate338is provided to the data input of TFF340. The Q output of TFF340may be used as the bit2output of the bi-directional counter310. The Q output of TFF340is also provided to a first input of AND gate344, and the Qbar output of TFF340is provided to a first input of AND gate342. In addition, the output of AND gate332is provided to a second input of AND gate342, and the output of AND gate334is provided to a second input of AND gate344. The outputs of AND gates342and344are provided to the inputs of OR gate346.

The output of XOR gate312is also provided to a first input of AND gate348, and the output of OR gate346is provided to a second input of AND gate348. The output of AND gate348is provided to the data input of TFF350. The Q output of TFF350may be used as the bit3output of the bi-directional counter310. The Q output of TFF350is also provided to a first input of AND gate354, and the Qbar output of TFF350is provided to a first input of AND gate352. In addition, the output of AND gate342is provided to a second input of AND gate352, and the output of AND gate344is provided to a second input of AND gate354. The outputs of AND gates352and354are provided to the inputs of OR gate356.

The output of XOR gate312is also provided to a first input of AND gate358, and the output of OR gate356is provided to a second input of AND gate358. The output of AND gate358is provided to the data input port of TFF360. The Q output of TFF360may be used as the bit4output of the bi-directional counter310.

A clock signal CLK may be provided to the clock ports of the five T flip-flops (TFF320, TFF330, TFF340, TFF350and TFF360). As mentioned above, the five bi-directional counter bits (bit0, bit1, bit2, bit3and bit4) are provided by the Q outputs of the five T flip-flops. The five bi-directional counter bits may be provided to inputs of the polarity detection circuit365. One embodiment of the polarity detection circuit365is described below in relation toFIG. 4.

In addition, the higher counter bits may be provided to the polarity select logic380. In the example shown inFIG. 3, the higher counter bits include bit2, bit3and bit4. In particular, as shown inFIG. 3, the Q outputs of TFFs340,350and360may be provided to the first inputs of AND gates381,384, and387, respectively. In addition, the Qbar outputs of TFF340,350and360may be inverted by inverters372,373, and374, respectively, and the inverted Qbar outputs are provided to the first inputs of AND gates382,385, and388.

The outputs of AND gates381and382are provided to the inputs of OR gate383. The outputs of AND gates384and385are provided to the inputs of the OR gate386. The outputs of AND gate387and388are provided to the inputs of the OR gate389. The outputs of OR gates383,386, and389are provided to a selector395which is controlled by configurable bits (which may be memory such as, for example, RAM).

The output of the selector395is the non-lock signal which is provided to the lock filter204and the DFF206. A connection397also routes the non-lock signal to the reset port of the polarity detection circuit365and to the clear (CLR) ports of the TFFs (320,330,340,350and360).

Consider a first case where the selector395is configured to select the signal output from OR gate383which is related to bit2. OR gate383outputs a logical zero unless either (i) the positive polarity (pos) signal is asserted and bit2is logical one, or (ii) the negative polarity (neg) signal is asserted and bit2is logical zero. The first instance happens when the BDC reaches 00111 or +7 in decimal, and the second instance happens when BDC reaches 11000 in binary or −7 in decimal. Hence, if the selector395is configured to select the input related to bit2, then the non-lock signal is asserted when BDC reaches +/−7. At that point, the asserted non-lock signal is routed397back to trigger a reset of the bi-directional counter310and the polarity detection circuit365. This causes the de-assertion of the non-lock signal, until the BDC again reaches +/−7.

Consider a second case where the selector395is configured to select the signal output from OR gate386which is related to bit3. OR gate386outputs a logical zero unless either (i) the positive polarity (pos) signal is asserted and bit3is logical one, or (ii) the negative polarity (neg) signal is asserted and bit3is logical zero. The first instance happens when the BDC reaches 01011 or +11 in decimal, and the second instance happens when BDC reaches 10100 in binary or −11 in decimal. Hence, if the selector395is configured to select the input related to bit3, then the non-lock signal is asserted when BDC reaches +/−11. At that point, the asserted non-lock signal is routed397back to trigger a reset of the bi-directional counter310and the polarity detection circuit365. This causes the de-assertion of the non-lock signal, until the BDC again reaches +/−11.

Consider a third case where the selector395is configured to select the signal output from OR gate389which is related to bit4. OR gate389outputs a logical zero unless either (i) the positive polarity (pos) signal is asserted and bit4is logical one, or (ii) the negative polarity (neg) signal is asserted and bit4is logical zero. The first instance happens when the BDC reaches 10011 or +19 in decimal, and the second instance happens when BDC reaches 01100 in binary or −19 in decimal. Hence, if the selector395is configured to select the input related to bit4, then the non-lock signal is asserted when BDC reaches +/−19. At that point, the asserted non-lock signal is routed397back to trigger a reset of the bi-directional counter310and the polarity detection circuit365. This causes the de-assertion of the non-lock signal, until the BDC again reaches +/−19.

FIG. 4depicts a polarity detection circuit365in accordance with an embodiment of the invention. The polarity detection circuit365includes two D flip-flops (DFFs)402and412and two OR gates404and414. The data output of the first DFF402provides a negative polarity signal (neg) indicative of a negative polarity count, and the data output of the second DFF404provides a positive polarity signal (pos) indicative of a positive polarity count.

The clock port of DFF402receives a negative assertion (neg assert) signal from first multiple-bit AND logic. In this example, the first multiple-bit AND logic performs the logical AND of five bits: bit4; bit3; bit2; inverted bit1; and inverted bit0. Hence, the neg assert signal is zero unless the BDC is 11100 in binary, which is equivalent to −3 in decimal. When the BDC reaches 11100, then the output Q of DFF402goes from logical zero to logical one. This is because the data input for DFF402is tied to the supply voltage VCC.

Similarly, the clock port of DFF412receives a positive assertion (pos assert) signal from second multiple-bit AND logic. In this example, the second multiple-bit AND logic performs the logical AND of five bits: inverted bit4; inverted bit3; inverted bit2; bit1; and bit0. Hence, the pos assert signal is zero unless the BDC is 00011 in binary, which is equivalent to +3 in decimal. When the BDC reaches 00011, then the output Q of DFF412goes from logical zero to logical one. This is because the data input for DFF412is tied to the supply voltage VCC.

OR gate404receives both a negative de-assertion (neg de-assert) signal from third multiple-bit AND logic and a reset signal (comprising the non-lock signal). The output of OR gate404is provided to the clear port of DFF402. In this example, the third multiple-bit AND logic performs the logical AND of five bits: bit4; bit3; bit2; bit1; and inverted bit0. Hence, the neg de-assert signal is zero unless the BDC is 11110 in binary, which is equivalent to −1 in decimal. When the BDC reaches 11110, then the output Q of DFF402is cleared to logical zero. The output Q of DFF402may also be cleared to logical zero if the reset signal is received.

Similarly, OR gate414receives both a positive de-assertion (pos de-assert) signal from fourth multiple-bit AND logic and a reset signal (comprising the non-lock signal). The output of OR gate414is provided to the clear port of DFF412. In this example, the fourth multiple-bit AND logic performs the logical AND of five bits: inverted bit4; inverted bit3; inverted bit2; inverted bit1; and bit0. Hence, the pos de-assert signal is zero unless the BDC is 00001 in binary, which is equivalent to +1 in decimal. When the BDC reaches 00001, then the output Q of DFF412is cleared to logical zero. The output Q of DFF412may also be cleared to logical zero if the reset signal is received.

FIG. 5is a flow chart of a method500for generating a lock signal in accordance with an embodiment of the invention. The method500may be implemented by the circuitry described above in relation toFIGS. 2-4.

In a first step502, the bi-directional counter (BDC) and the filter counter (LFC) may be each reset to zero. In a second step504, the sampler102samples the input data on every ½ unit interval (UI) to determine if the input data is early or late (or neither early nor late) with respect to the sampling clock.

If an early signal is asserted by the sampler102, then BDC and LFC are both incremented by one, as shown in step506. On the other hand, if a late signal is asserted by the sampler102, then BDC is decremented by one and LFC is incremented by one, as shown in step508.

If no signal is asserted by the sampler102(indicating that the input data is neither early nor late), then BDC is kept at the same count while LFC is incremented by one, as shown in step510. Thereafter, the method500moves on to step516which is described further below.

After either step506or step508, a determination is made, per step512, as to whether or not the non-lock signal is asserted. If the non-lock signal is asserted, then, per step514, the lock signal may be de-asserted, and LFC may be reset to zero. Thereafter, the method500may loop back to step504so as to obtain and process the next sample.

On the other hand, if the non-lock signal is not asserted, then, per step516, a determination is made as to whether LFC is equal to a predetermined maximum count. As mentioned above, step516may also be reached via step510. The maximum value of the LFC should be greater than the non-lock assertion thresholds.

If LFC is determined to equal to the maximum count in step516, then, per step518, the lock signal may be asserted, and LFC may be reset to zero. Thereafter, the method500may loop back to step504so as to obtain and process the next sample. On the other hand, if LFC is determined to not equal to the maximum count in step516, then the method500may loop back to step504so as to obtain and process the next sample.

FIG. 6shows example timing diagrams in relation to an embodiment of the invention. The diagrams depict select signals in a computational simulation of the lock detection circuitry disclosed herein.

The first (top) diagram depicts delay602versus time t, where delay602is the time between the rising (or falling) edge of the sampling clock and the rising (or falling) edge of the input data. In this example, the ideal sampling point is at 160 pico seconds (ps) which is reached at or around t=240 nano seconds (ns). Sometime after the ideal sampling point is reached, the CDR may be determined to be in a lock state.

The second diagram depicts the early signal604which may be asserted by the sampler102in accordance with an embodiment of the invention. Meanwhile, the third diagram depicts the late signal606which may be asserted by the sampler102in accordance with an embodiment of the invention. As seen, in this example, the early and late signals begin to toggle interchangeably at or around t=240 ns.

The fourth diagram depicts the reset signal608which may be asserted by the dither detection circuit202. As shown, reset pulses are asserted to reset the lock filter to prevent the lock signal from being asserted when the CDR is not in a lock state. The reset pulses are not asserted when the CDR is in a lock state. As shown, in this example, the last reset pulse is asserted at or around t=240 ns.

The fifth diagram depicts the lock signal which is asserted by the lock detection circuit110when the CDR is determined to be in a lock state. As shown, in this example, the lock signal is asserted at or around t=280 ns.

FIG. 7is a high-level diagram of a communication link including a receiver within which the lock detection technique disclosed herein may be applied in accordance with an embodiment of the invention. As shown inFIG. 7, a communication link is generally composed of a transmitter (TX)720, a receiver (RX)740, and a communication channel (CH)730that is located in between the transmitter and the receiver.

The TX720may include a parallel-in-serial-out (PISO) circuit722. The PISO (serializer) circuit722may be configured to receive parallel data signals and convert it to a serial data signal. For example, the transmitter720may be part of an integrated circuit, and the parallel data signals may be provided by a communication protocol module in the integrated circuit.

The serial data signal may be adjusted by a transmitter equalizer (TX EQ) circuit724. In one embodiment, the TX EQ circuit724may implement a finite impulse response (FIR) equalization that pre-distorts the transmitted signal to compensate for signal distortion in the channel730. Clock generator (CLK) circuit721may utilize a phase locked loop (PLL) circuit to provide a clock signal to the PISO722and TX EQ724circuits. The output from the TX EQ724circuit may be provided to a driver circuit726. The driver circuit726may be configured to transmit the serial data signal over the channel730.

The channel730communicates the serial data signal from the transmitter720to the receiver740. The channel730may use multiple lanes to communicate the serial data signal.

The receiver740may be configured to receive the transmitted serial data signal from the multiple-lane channel into buffer circuitry742. The buffer circuitry742may output the received serial data signal to receiver equalization (RX EQ) circuit744and to the clock and data recovery (CDR) circuit745. In accordance with an embodiment of the invention, the CDR circuit745may use a lock detection circuit circuit, as disclosed herein, to indicate a lock state of the CDR circuit745.

The RX EQ circuit744may be configured to perform one or more equalizations to compensate for high-frequency signal loss in the channel. The RX EQ circuit744may output an “equalized” serial data signal to a data input of a latch circuit746.

The sampling clock may be provided from the CDR circuit745to clock inputs of the RX EQ circuit744and to a latch circuit746. The latch circuit746may be configured to receive the equalized serial data signal from the RX EQ circuit744at its data input and to receive the sampling clock from the CDR circuit745at its clock input. The latch circuit746outputs the regenerated serial data signal to a serial-in-parallel-out (SIPO) circuit748.

The SIPO (serializer) circuit748is configured to receive a serial data signal and convert it to parallel data signals. The parallel data signals may be provided to other circuitry of the receiving device. For example, the receiving device may be an integrated circuit, and the parallel data signals may be provided to a communication protocol module in the integrated circuit.

FIG. 8is a simplified partial block diagram of a field programmable gate array (FPGA)10including transceiver circuits within which the lock detection technique disclosed herein may be applied in accordance with an embodiment of the invention. It should be understood that embodiments of the present invention can be used in numerous types of integrated circuits such as field programmable gate arrays (FPGAs), programmable logic devices (PLDs), complex programmable logic devices (CPLDs), programmable logic arrays (PLAs), digital signal processors (DSPs) and application specific integrated circuits (ASICs).

FPGA10includes within its “core” a two-dimensional array of programmable logic array blocks (or LABs)12that are interconnected by a network of column and row interconnect conductors of varying length and speed. LABs12include multiple (e.g., ten) logic elements (or LEs). A LE is a programmable logic block that provides for efficient implementation of user defined logic functions. An FPGA has numerous logic elements that can be configured to implement various combinatorial and sequential functions. The logic elements have access to a programmable interconnect structure. The programmable interconnect structure can be programmed to interconnect the logic elements in almost any desired configuration.

FPGA10may also include a distributed memory structure including random access memory (RAM) blocks of varying sizes provided throughout the array. The RAM blocks include, for example, blocks14, blocks16, and block18. These memory blocks can also include shift registers and FIFO buffers.

FPGA10may further include digital signal processing (DSP) blocks20that can implement, for example, multipliers with add or subtract features. Input/output elements (IOEs)22located, in this example, around the periphery of the chip support numerous single-ended and differential input/output standards. Each IOE22is coupled to an external terminal (i.e., a pin) of FPGA10. A transceiver (TX/RX) channel array may be arranged as shown, for example, with each TX/RX channel circuit30being coupled to several LABs. A TX/RX channel circuit30may include, among other circuitry, the receiver circuitry described herein.

It is to be understood that FPGA10is described herein for illustrative purposes only and that the present invention can be implemented in many different types of PLDs, FPGAs, and ASICs.

The present invention can also be implemented in a system that has a FPGA as one of several components.FIG. 9is a block diagram of an exemplary digital system within which the lock detection technique disclosed herein may be utilized in accordance with an embodiment of the invention.

System50may be a programmed digital computer system, digital signal processing system, specialized digital switching network, or other processing system. Moreover, such systems can be designed for a wide variety of applications such as telecommunications systems, automotive systems, control systems, consumer electronics, personal computers, Internet communications and networking, and others. Further, system50may be provided on a single board, on multiple boards, or within multiple enclosures.

System50includes a processing unit52, a memory unit54, and an input/output (I/O) unit56interconnected together by one or more buses. According to this exemplary embodiment, FPGA58is embedded in processing unit52. FPGA58can serve many different purposes within the system50. FPGA58can, for example, be a logical building block of processing unit52, supporting its internal and external operations. FPGA58is programmed to implement the logical functions necessary to carry on its particular role in system operation. FPGA58can be specially coupled to memory54through connection60and to I/O unit56through connection62.

Processing unit52may direct data to an appropriate system component for processing or storage, execute a program stored in memory54, receive and transmit data via I/O unit56, or other similar function. Processing unit52may be a central processing unit (CPU), microprocessor, floating point coprocessor, graphics coprocessor, hardware controller, microcontroller, field programmable gate array programmed for use as a controller, network controller, or any type of processor or controller. Furthermore, in many embodiments, there is often no need for a CPU.

For example, instead of a CPU, one or more FPGAs58may control the logical operations of the system. As another example, FPGA58acts as a reconfigurable processor that may be reprogrammed as needed to handle a particular computing task. Alternately, FPGA58may itself include an embedded microprocessor. Memory unit54may be a random access memory (RAM), read only memory (ROM), fixed or flexible disk media, flash memory, tape, or any other storage means, or any combination of these storage means.

In the above description, numerous specific details are given to provide a thorough understanding of embodiments of the invention. However, the above description of illustrated embodiments of the invention is not intended to be exhaustive or to limit the invention to the precise forms disclosed. One skilled in the relevant art will recognize that the invention can be practiced without one or more of the specific details, or with other methods, components, etc.

In other instances, well-known structures or operations are not shown or described in detail to avoid obscuring aspects of the invention. While specific embodiments of, and examples for, the invention are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize. These modifications may be made to the invention in light of the above detailed description.