Test apparatus and test module

A test apparatus is provided. The test apparatus includes: a signal provision section that provides a test signal to a device under test; an input section that inputs the output signal outputted from the device under test in response to the test signal as a signal-under-test; a periodic pulse generating section that generates a periodic pulse having a pulse width corresponding to one cycle of the signal-under-test; a converting section that outputs a voltage corresponding to the width of periodic pulse; an AD converter that converts a voltage to a digital voltage value; a pulse width calculating section that calculates a digital pulse width indicative of the width of the periodic pulse based on the digital voltage value; and an adjusting section that adjusts a conversion parameter that converts between the digital voltage value and the digital pulse width.

BACKGROUND

1. Field of the Invention

The present invention relates to a test apparatus and a test module. Particularly, the present invention relates to a test apparatus that tests a device under test such as a semiconductor circuit and a test module that is provided in the test apparatus.

2. Related Art

There is an apparatus that measures a plurality of device under tests at a time as a test apparatus that tests a device under test such as a semiconductor circuit. For example, the apparatus measures an output signal outputted from each device under test in parallel by a plurality of channels. For example, a level comparator that compares the level of the output signal with a reference value and an operation circuit are packaged for each channel of a testing board such as a mother board, so that the output signal for each device under test can be measured.

However, various circuits such as a circuit that generates a test signal and provides the same to the device under test, and a circuit that generates a clock signal and provides the same to the device under test are provided on the testing board. Therefore, the packaging density and the space on the testing board are limited, so that it is difficult to package a testing circuit for each channel.

Additionally, when the testing circuit is packaged for each channel, it is different to ensure the accuracy of measurement for each channel because the components are different between each measuring circuit.

Thus, the advantage of the present invention is to provide a test apparatus and a test module which are capable of solving the problem accompanying the conventional art. The above and other advantages can be achieved by combining the features recited in independent claims. Then, dependent claims define further effective specific example of the present invention.

SUMMARY

In order to solve the above described problems, a first aspect of the present invention provides a test apparatus that tests a device under test. The test apparatus includes: a signal provision section that provides a test signal to a device under test; an input section that inputs the output signal outputted from the device under test in response to the test signal as a signal-under-test; a periodic pulse generating section that generates a periodic pulse having a pulse width corresponding to one cycle of the signal-under-test; a converting section that outputs a voltage corresponding to the width of periodic pulse; an AD converter that converts a voltage to a digital voltage value; a pulse width calculating section that calculates a digital pulse width indicative of the width of the periodic pulse based on the digital voltage value; and an adjusting section that adjusts a conversion parameter that converts between the digital voltage value and the digital pulse width.

A second aspect of the present invention provides a test module provided in a test head of a test apparatus that tests a device under test. The test module includes: an input section that inputs an output signal outputted from a device under test through a mother board placed on a test head as a signal-under-test; a periodic pulse generating section that generates a periodic pulse having a pulse width corresponding to one cycle of the signal-under-test; a converting section that outputs a voltage corresponding to the width of periodic pulse; an AD converter that converts a voltage to a digital voltage value; a pulse width calculating section that calculates a digital pulse width indicative of the width of the periodic pulse based on the digital voltage value; and an adjusting section that adjusts a conversion parameter that converts between the digital voltage value and the digital pulse width.

Here, all necessary features of the present invention are not listed in the summary of the invention. The sub-combinations of the features may become the invention.

DESCRIPTION OF EXEMPLARY EMBODIMENTS

The invention will now be described based on preferred embodiments, which do not intend to limit the scope of the invention, but exemplify the invention. All of the features and the combinations thereof described in the embodiments are not necessarily essential to the invention.

FIG. 1shows an example of configuration of a test apparatus100according to an embodiment of the present invention. The test apparatus100having a mother board110, a test head120and a mainframe130that tests a device under test200such as a semiconductor circuit. The device under test200is placed on the mother board110. The mother board110has a plurality of device side terminals which are electrically connected to each input/output pin of the device under test. The mother board110has a plurality of tester side terminals which are electrically connected to the test head120.

The mother board110is placed on the test head120. A plurality of test modules140are also placed on the test head120. Each of the test modules140is electrically connected to the tester side terminal of the mother board110and transmits/receives signals to/from the device under test200. For example, the test module140that provides a test signal to the device under test200through the mother board, and the test module140that receives the output signal from the device under test200through the mother board may be placed on the test head120. By measuring an output signal for the predetermined test signal provided to the device under test200, the device under test200can be tested.

The mainframe130is connected to the test head120by such as an optical cable and a coaxial cable. The mainframe130may output a control signal that controls each of the test modules140. Additionally, the mainframe130may receive a result obtained by measuring the output signal of the device under test.

FIG. 2shows an example of configuration of a circuit provided on a test head120. Here, the motherboard110and the mainframe130are omitted inFIG. 2.

The test head120includes a signal provision section10, a measurement circuit12and an operation section122. The signal provision section10generates a test signal to test the device under test200and provides the same to the device under test200. For example, the signal provision section10may provide a test pattern signal having a predetermined logic pattern signal and a source power.

A measurement circuit12measures the output signal from the device under test200. The measurement circuit12has a plurality of measurement channels. For example, the measurement circuit12may have a plurality of measurement channels each of which measures the output signal from the device under test200. Additionally, the measurement circuit12may have a plurality of measurement channels each of which measures the output signals from the device under test and also may have a plurality of measurement channels each of which measures the output signals from a plurality of output pins of the device under test. There may be a plurality of signal provision sections10corresponding to the plurality of measurement channels.

Each of the signal provision section10and the measurement circuit12may be provided in the different test modules120as shown inFIG. 1, or may be provided in the same test module140. Additionally, the measurement circuit12may have the test module140for each of the plurality of measurement channels. The signal provision section10may provide in the test module140in the corresponding to the measurement channel.

The measurement circuit12has a circuit for each channel20, a data processing section80and an adjusting clock generating section90. The circuit for each channel20is provided for each of the measurement channels. That is, the circuit for each channel20is provided for each of the output signals to be measured. The circuit for each channels20may be provided for each of the plurality of test modules140corresponding to the plurality of measurement channels.

Each of the plurality of circuit for each channels20has a data processing section80and an adjusting clock generating section90, respectively. That is, each of the data processing section80and the adjusting clock generating section90is provided as a common circuit for a plurality of measurement signals to be measured. Each of the data processing section80and the adjusting clock generating section90may be provided for each of the circuit for each channels20. Additionally, when the plurality of circuit for each channels20are divided into a plurality of groups, each of the data processing section80and the adjusting clock generating section90may be provided for each group.

Each of the circuit for each channels20has an input section26, a periodic pulse generating section40, a converting section50and an AD converter22. The input section26receives output signals outputted from the corresponding device under test200or the output pins of the corresponding device under test200. The input section26inputs the received output signal to the circuit for each channel20as a signal-under-test. For example, the input section26may compare the level of the output signal at the timing of the provided clock signal with a predetermined reference value, and input the comparison result as the signal-under-test. For example, the input section26may input the comparison result as the signal-under-test, which indicates H logic when the level of the output signal at the timing of the clock signal is higher than the reference value and L logic when the level of the output signal at the timing of the clock signal is lower than the reference value.

The periodic pulse generating section40generates a periodic clock having a pulse width corresponding to one period of the signal-under-test in response to a sample clock which designates the timing at which the signal-under-test is sampled. An example of operation of the periodic pulse generating section40will be described later with reference toFIG. 4. That is, the periodic pulse generating section40outputs each period in a cycle of the signal-under-test designated by the sample clock, respectively as the amount of time indicated by the pulse width.

The converting section50outputs a voltage corresponding to the width of the periodic pulse. For example, the converting section50may output the voltage based on the result obtained by integrating the periodic pulse. That is, the converting section50converts the amount of time indicated by the pulse width of the periodic clock outputted by the periodic pulse generating section40to an analog voltage. The voltage is corresponded to the value for each period in the cycle of the signal-under-test designated by the sample clock, respectively.

The AD converter22converts the analog signal outputted by the converting section50to a digital voltage value. That is, the AD converter22outputs the digital voltage value corresponding to the value for each period in the cycle of the signal-under-test designated by the sample clock, respectively. The AD converter22may convert the analog voltage at the timing of the provided sample clock to a digital voltage value, and output the same.

As described above, the period in a predetermined cycle of the signal-under-test in each measurement channel can be measured. Thereby a periodic jitter of the signal-under-test can be obtained.

The data processing section80receives the digital voltage value outputted by each of the circuit for each channels20and performs a processing dependent on the digital voltage value. For example, the data processing section80may be a FPGA (Field Programmable Gate Array). In this case, the data processing section may perform a predetermined processing set in the FPGA.

The data processing section80according to the present embodiment includes a pulse width calculating section82, an adjusting section86and a sample clock generating section84. The operation of each of the pulse width calculating section82, the adjusting section86and the sample clock generating section84may be previously set in the FPGA. The sample clock generating section84generates a sample clock having a predetermined period and provides the same to the periodic pulse generating section40and the AD converting section22.

The pulse width calculating section82calculates a digital pulse width indicative of the width of the corresponding periodic pulse based on the digital voltage value outputted from each of the circuit for each channels20.

That is, the converting section50converts the value on the to axis to the value on the voltage axis and inputs the same to the AD converter22in order to detect the value for a period of a predetermined cycle of the signal-under-test by the AD converter22. Then, the pulse width calculating section82converts the digital value on the voltage axis outputted by the AD converter22to the digital value (digital voltage value) on the time axis.

The adjusting section86adjusts the conversion parameter used to convert from the digital value on the voltage axis (digital voltage value) to the digital value of the time axis (digital pulse value) by the pulse width calculating section82. For example, the adjusting section86may individually adjust the conversion parameter for each of the circuit for each channels20. By above-described processing, the characteristic difference among the measurement channels can be compensated to accurately measure the periodic jitter of the signal-under-test. The adjusting section86may previously measure the characteristic for each measurement channel and adjust the conversion parameter based on the measurement result.

When the characteristic of the measurement channel is previously measured, the adjusting clock generating section90sequentially provides a plurality of adjusting clocks of which periods are different from each other to the input section26of the circuit for, each channels20to be measured. In this case, the input section26inputs the plurality of adjusting clocks instead of the output signal of the device under test200as the signal-under-tests. The adjusting clock generating section90may be provided in the FPGA on which the data processing section80is provided.

the adjusting section86sets the conversion parameter to the plurality of adjusting clock in the pulse width calculating section82such that if the adjusting clocks are inputted to the input section26, the digital voltage value measured by the AD converter22is converted to the digital pulse width corresponding to one period of the adjusting clock in the pulse width calculating section82.

The adjusting clock generating section90may notify the adjusting section of the value of one period for each adjusting clock. Additionally, controlling the value of one period for the adjusting clock to be generated by the adjusting clock generating section90, the adjusting section86may calculate the value of one period for each adjusting clock based on the control signal provided to the adjusting clock generating section90. An example of operation of the adjusting section86will be described later with reference toFIG. 6.

By the above-described processing, the difference for each measurement channel is compensated, so that each signal-under-test can be accurately measured. Additionally, since one data processing section80can provided for each of the plurality of measurement channels, the measurement variation in the data processing section80can be reduced. Additionally, the FPGA provided in the test apparatus10is used as the data processing section80, so that a circuit layout on the substrate can be facilitated and the substrate design also can be facilitated.

The operation section122may calculate the maximum value and the minimum value of the digital pulse width calculated by the pulse width calculating section82. Additionally, the operation section122may further calculate the average value of the digital pulse width calculated by the pulse width calculating section82.

By performing the above-described processing, the periodic variation of the device-under-signal can be easily evaluated by such as the mainframe130and an external electronic calculator. For example, the mainframe130may calculate the peak to peak value of the periodic jitter of the signal-under-test based on the difference between the maximum value and the minimum value of the digital pulse width calculated by the operation section122. Additionally, the mainframe130may calculate the standard deviation of the periodic jitter of the signal-under-test based on the average value calculated by the operation section122.

FIG. 3shows an example of detailed configuration of a circuit for each channel20. The circuit for each channel20according to the present embodiment further includes a switching sections24-1and24-2in addition to the components shown inFIG. 2. The circuit for each channel20according to the present embodiment receives the differential signal as the output signal. In this case, the input section26has a positive side terminal that receives the differential signal at the positive side and a negative side terminal that receives the differential signal at the negative side.

The switching section24-1is provided in front step of the positive side terminal in the input section26. That is, the positive side terminal in the input section26receives the differential signal of the positive side which is outputted by the device under test200through the switching section24-1.

The switching section24-2is provided in front step of the negative side terminal in the input section26. That is, the negative side terminal in the input section26receives the differential signal of the negative side outputted from the device under test200through the switching section24-2.

Additionally, each of the switching sections24selects either of the output signal from the device under test200and the adjusting clock outputted by the adjusting clock generating section90, and inputs the same to the input section26. For example, when the adjusting section86measures the characteristic of the circuit for each channel20, each of the switching sections24selects the adjusting clock and inputs the same to the input section26. Additionally, when the adjusting section86measures the output signal from the device under test200, each of the switching section24selects the output signal and inputs the same to the input section26.

The input section26has condensers28, switches30, diodes32, diodes34, a comparison circuit36and an output circuit38. The condensers28, the switches30, diodes32and diodes34are provided for each of the positive side terminal and the negative side terminal.

The condenser28filters the de component of the signal provided from the switching section24. The signal filtered through the condensers28is inputted to the comparison circuit36. Additionally, the transmission path between the condensers28and the comparison circuit36is divided into transmission paths having a predetermined impedance and connected to ground. The switch30switches the impedances of the divided transmission paths. Thereby the impedances in the transmission paths from the condensers20to the comparison circuit can be matched with each other.

The diodes32and the diodes34limit the voltage value of the signal transmitted through the transmission path from the condensers28to the comparison circuit36. For example, the diodes32are provided between the transmission path and a predetermined high level wiring (+V) to prevent the level of the signal transmitted through the transmission path from being higher than the predetermined value. Meanwhile, the diodes34are provided between the transmission path and a predetermined low level wiring (−V2) to prevent the level of the signal transmitted through the transmission path from being lower than the predetermined value. Thereby the absolute value of the level of the signal transmitted through the transmission path can be limited, so that the comparison circuit can be prevented from being damaged.

The comparison circuit36compares the level of the inputted signal with the predetermined reference level (VTH) and outputs the comparison results. The output circuit may be a LVPECL (Low Voltage Positive Emitter Coupled Logic) circuit. The output circuit38provides the signal outputted by the comparison circuit36to the periodic pulse generating section40. The signals outputted by the comparison circuit36and the output circuit38may be differential signals.

The periodic pulse generating section40includes a plurality of flip flops which are cascade-connected. The periodic pulse generating section40according to the present embodiment includes a first flip flop42, a second flip flop44, a third flip flop46and an output circuit48.

The first flip flop42receives a predetermined logic value as a data input, loads the data input according to the sample clock provided from the sample clock generating section84and outputs the same. The first flip flop42according to the present embodiment receives a fixed ‘H’ logic signal as the data input. Additionally, the output of the first flip flop42is reset in response to the output signal of the third flip flop46. In the present embodiment, when the output signal of the third flip flop46is transferred to ‘H’ logic, the output of the first flip flop42is reset.

The second flip flop44receives the output signal of the first flip flop42as a data input, loads the data input in response to the signal-under-test outputted by the input section26and outputs the same. In the present embodiment, the input section26inputs the differential signal of the signal-under-test to a differential clock terminal of the second flip flop44. The output of the second flip flop44is reset in response to the output signal of the third flip flop.

The third flip flop46receives the output signal of the second flip flop44as a data input, loads the data input in response to the signal-under-test outputted by the input section26and outputs the same as a periodic pulse. In the present embodiment, the input section26inputs the differential signal of the signal-under-test to the differential clock terminal of the second flip flop44. Here, the signal-under-tests inputted to the differential clock terminals of the second flip flop44and the third flip flop46may have the same phase.

The output circuit48receives the periodic pulse outputted by the third flip flop46and outputs the same to the converting section50. The output circuit48may includes the function and the configuration the same as those of the output circuit38in the input section26.

Additionally, the output circuit48provides the periodic pulse outputted by the third flip flop46to reset terminals of the first flip flop42and the second flip flop44. It is preferred that the transmission path from the output circuit48to the reset terminals of the first flip flop42and the second flip flop44of which wire length is short as possible. For example, it is preferred that the amount of delay for the transmission path is sufficiently shorter than one period of the signal-under-test. An example of operation of the periodic pulse generating section40will be described later with reference toFIG. 4.

The converting section50includes a source side current source52, a source side transistor54, a sink side current source58, a condenser60, a switch62, a condenser64, a diode66, a diode68and an amplifier70.

The source side transistor54and the sink side transistor56of which gate terminals receive the periodic pulses outputted by the periodic pulse generating section40. Here, the polarity of the source side transistor is reversed to that of the sink side transistor56. For example, one is a N-channel transistor and the other is a N-channel transistor. Thereby when the source side transistor is in on-state, the sink side transistor56is in off-state. Alternatively, the source side transistor54is in off-state, the sink side transistor56is in on-state.

The source side current source52is provided between a predetermined positive electric potential and a drain terminal of the source side transistor54. When the source side transistor54is in on-state, the source side current source52charges the condenser60and the condenser64with a predetermined source current. The sink side current source58is provided between a predetermined negative electric potential and a source terminal of the sink side transistor. When the sink side transistor56is in on-state, the sink side current source58discharges the condenser60and the condenser64with a predetermined sink current. Thereby the voltages of the condenser60and the condenser64are in the level according to the width of the periodic pulse.

The switch62switches whether the condenser60is connected to ground. That is, the switch62is in off-state, so that the voltage of the condenser60can be held. Thereby the AD converter22can easily detect the voltage of the condenser60.

The diode66and the diode68limit the voltage level inputted to the amplifier70. The amplifier70amplifies the voltages of the condenser60and the condenser64at a predetermined amplification factor and inputs the same to the AD converter22.

FIG. 4shows an example of operation of a periodic pulse generating section40and a converting section50. As described above, “H” logic is inputted to the data input of the first flip flop42. Therefore, the output of the first flip flop42is transferred from the “L” logic to “H” logic in response to the leading edge of the provided sample clock shown as a inFIG. 2.

The second flip flop44loads the output of the first flip flop42in response to the leading edge of the signal-under-test and outputs the same. Therefore, the output of the second flip flop44is transferred from “L” logic to “H” logic in response to the leading edge of the signal-under-test immediately after the output of the first flip flop42is transferred to “H” logic shown as b inFIG. 4.

The third flip flop46loads the output of the second flip flop44in response to the leading edge of the signal-under-test and outputs the same. Therefore, the output of the third flip flop46is transferred from “L” logic to “H” logic in response to the leading edge of the signal-under-test immediately after the output of the second flip flop44is transferred to “H” logic shown as c-FIG. 4.

Then, when the output of the third flip flop46indicates “H” logic, the outputs of the first flip flop42and the second flip flop44are reset Therefore, the outputs of the first flip flop42and the second flip flop44are transferred to “L” logic after a predetermined propagation delay since the output of the third flip flop46indicates “H” logic shown as d and e inFIG. 4.

Then, the output of the third flip flop46is transferred to the “L” logic in response to the leading edge of the signal-under-test immediately after the output of the second flip flop is transferred to “L” logic shown as f inFIG. 4. Thereby the periodic pulse generating section40detects the period for a cycle of the signal-under-test designated by the sample clock.

The converting section50integrates the periodic pulse outputted by the third flip flop46. The output level V1of the converting section50corresponds to a length T1of a predetermined cycle of the signal-under-test. Then, the switch62is turned off, so that the output of the converting section50is held to V1. The AD converter22converts the output level V1to a digital value at the timing of the sample clock. For example, the AD converter22may detect the output level of the converter50in response to the leading edge of the sample clock. After detecting the output level of the converting section50, the AD converter22controls the switch62to turn on to discharge the condenser60. Additionally, AD converter22controls the switch62to turn off in response to the trailing edge of the output of the third flip flop46.

The sample block generating section84may generate a sample clock having the pulse width larger than three periods of the signal-under-test, for example. Additionally, the sample clock generating section84may designate any number of cycles of the signal-under-test. In this case, the sample clock generating section84generates a sample clock having the designated number of pulses. Here, each pulse generated by the sample clock generating section84may be arranged at even intervals, or may be arranged at uneven intervals. It is preferred that the interval between each pulse of the sample clock is larger than a time for which the output of the converting section50returns to the initial value since the output is changed in response to the output of the third flip flop46.

FIG. 5shows an example of configuration of an adjusting clock generating section90. Here, the measurement circuit12further includes a divider88and a divider98in addition to the components shown inFIG. 2.

The divider88receives a predetermined clock signal, divides the same at a predetermined division ratio and outputs the same. For example, the divider88may receive a system clock of the test apparatus100. The test apparatus100may further include a clock generating device which generates a clock signal provided to the divider88.

The adjusting clock generating section90receives a divided clock outputted by the divider88. The adjusting clock generating section90includes a variable clock generating section92, a clock driver94and a clock driver96.

The variable clock generating section92generates a clock signal having any frequency based on the divided clock outputted by the divider88. For example, the variable clock generating section92may generate a clock signal having any frequency by using a PLL circuit, a fractional PLL circuit and a frequency multiplying circuit.

The clock driver94provides a clock signal outputted by the variable clock generating section92as an adjusting clock signal to the switching section24. When there are n circuit for each channels24, the clock driver94provides the adjusting clock signals to n switching sections24.

The clock driver92provides the clock signal generated by the variable clock generating section92to the sample clock generating section84. The divider98further divides the divided clock signal outputted by the divider88and provides the same to the sample clock generating section84.

The sample clock generating section84generates a sample clock based on either of the clock signal received from the divider98or the clock signal received from the clock driver96. The sample clock generating section84may provide the same sample clock to the first flip flop42and the AD converter22. When there are n circuit for each channels20, the sample clock generating section84provides the sample clocks to n first flip flops42and n AD converters22.

Thereby the adjusting clock signal and the sample clock can be generated at a desired period.

FIG. 6shows an example of operation of an adjusting section86. Firstly, the adjusting section86causes the adjusting clock generating section90to output an adjusting clock signal having a known frequency. For example, the adjusting section86causes the adjusting clock generating section90to sequentially output adjusting clock signals having frequency T1, T2, T3and T4, respectively. It is preferred that the adjusting clock signal of which jitter is sufficiently reduced.

Next, the adjusting section86detects a digital voltage value outputted by the AD converter22for each of the adjusting clock signals. In the present embodiment, the AD converter22outputs digital voltage values V1, V2, V3and V4for the adjusting clock signals each of which frequency is T1, T2, T3and T4.

The adjusting section86associates each of the digital voltage value V1, V2, V3and V4with each digital value of which frequency is T1, T2, T3and T4, respectively. The digital value is a value for the digital pulse width to be calculated for each of the digital voltage values.

The adjusting section86may create a table in which the digital voltage values are associated with the digital pulses width as described above. The adjusting section86may convert the digital voltage value outputted for the signal-under-test to the digital pulse width with reference to the table.

Additionally, the correspondence between each of the actually measured digital voltage values (V1, V2, V3and V4) and the digital pulse width may be calculated by linear-interpolating as shown inFIG. 6. For example, the adjusting section86may calculate a linear equation to convert the digital voltage value to the digital pulse width for each interval (T1-T2, T2-T3, T3-T4) obtained by dividing the period of the adjusting clock. The linear equation can be easily calculated based on the digital voltage value and the digital pulse width at both ends of each interval.

The adjusting section86may calculate coefficients and constants of the linear expression and store therein the same. Additionally, the adjusting section86may calculate coefficients and constants of corresponding linear expression every interval obtained by dividing the period of the adjusting clock and store therein the same. The pulse width calculating section82converts the digital voltage value to the digital pulse value by using the linear expression calculated by the adjusting section86.

As evidenced by the above description, the measurement difference for each channel can be compensated according to one embodiment of the present invention. Additionally, a substrate on which various circuits are provided can be easily designed by using the FPFGA as the data processing section80.

While the present invention has been described with the embodiment, the technical scope of the invention not limited to the above described embodiment. It is apparent to persons skilled in the art that various alternations and improvements can be added to the above-described embodiment. It is apparent from the scope of the claims that the embodiment added such alternation or improvements can be included in the technical scope of the invention.