Solid-state imaging device, method of driving solid-state imaging device, and image processing device

An image processing device comprising: first A/D converters that receive output signals of respective columns of a plurality of pixels arranged in a matrix form, convert the output signals into first digital signals, and output the first digital signals; a second A/D converter that receives a correction signal, converts the correction signal into a second digital signal, and outputs the second digital signal; a first correction calculation unit that produces a first correction formula; a second correction calculation unit that produces a second correction formula based on the second digital signal; a determination unit that compares a coefficient of the second correction formula and a coefficient of a second correction formula produced before the second correction formula, and determines whether or not to produce the first correction formula based on the comparison result; and a signal output unit that outputs an update signal when it is determined to produce the first correction formula.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a solid-state imaging device, a method of driving a solid-state imaging device, and an image processing device.

Priority is claimed on Japanese Patent Application No. 2010-024408, filed Feb. 5, 2010, the content of which is incorporated herein by reference.

2. Description of the Related Art

All patents, patent applications, patent publications, scientific articles, and the like, which will hereinafter be cited or identified in the present application, will hereby be incorporated by reference in their entirety in order to describe more fully the state of the art to which the present invention pertains.

Recent imaging devices such as digital cameras, camcorders, and endoscopes include solid-state imaging devices such as charge coupled device (CCD) image sensors or complementary metal oxide semiconductor (CMOS) image sensors. Demands for reduction in size and power consumption of imaging devices are continuously increasing.

There is a solid-state imaging device including a plurality of time analog-to-digital converter type analog/digital (A/D) converters (TADs). A TAD outputs a frequency pulse according to a pixel signal, and a counter counts the pulse, thereby performing A/D conversion on the pixel signal. The pixel signal corresponds to voltage output from a pixel. An area in which pixels are arranged in a two-dimensional matrix is referred to as a pixel block. Japanese Patent Laid-Open No. 2006-287879 discloses a solid-state imaging device having a TAD in which the TAD is disposed in a pixel block to perform A/D conversion on a pixel signal with a high signal-to-noise (S/N) ratio.

A TAD has a nonlinear input/output (I/O) characteristic. Thus, an output value needs to be corrected to make the I/O characteristic linear.

Japanese Unexamined Patent Application, First Publication No. 2004-274157 discloses a method of correcting an output value of a TAD. Correlated double sampling (CDS) is performed on a pixel signal. It is determined whether the resultant voltage belongs to a high voltage region or a low voltage region constituting a voltage region. Using a correction formula corresponding to the corresponding region, an output value of the TAD is corrected.

SUMMARY

A solid-state imaging device may include: a plurality of pixels that are arranged in a matrix form and output output signals; a plurality of first A/D converters that receive the output signals of respective columns of the plurality of pixels, convert the output signals into first digital signals, and output the first digital signals; a second A/D converter that receives a correction signal, converts the correction signal into a second digital signal, and outputs the second digital signal; a first correction calculation unit that produces a first correction formula for correcting linearity of the first digital signals; a second correction calculation unit that produces a second correction formula for correcting linearity of the second digital signal based on the second digital signal; a determination unit that compares a coefficient of the second correction formula produced by the second correction calculation unit and a coefficient of a second correction formula produced before the second correction formula, and determines whether or not to produce the first correction formula based on the comparison result; and a signal output unit that outputs an update signal for causing the first correction calculation unit to produce the first correction formula to the first correction calculation unit when it is determined to produce the first correction formula.

The correction signal may be a constant voltage for reference.

The correction signal may be an output signal of the pixel masked to block incident light.

The first correction calculation unit may correct a coefficient of the first correction formula based on a rate of change of the coefficient of the second correction formula.

The plurality of first A/D converters may receive the correction signal, convert the correction signal into digital signals, and output the digital signals as third digital signals. The first correction calculation unit may produce the first correction formula based on the third digital signals.

A method of driving a solid-state imaging device may include: receiving output signals of respective columns of a plurality of pixels arranged in a matrix form, converting the output signals into first digital signals, and outputting the first digital signals; receiving a correction signal, converting the correction signal into a second digital signal, and outputting the second digital signal; producing a first correction formula for correcting linearity of the first digital signals; producing a second correction formula for correcting linearity of the second digital signal based on the second digital signal; determining whether or not to produce the first correction formula based on a result of comparison between a coefficient of the second correction formula and a coefficient of a second correction formula produced before the second correction formula; and outputting an update signal for causing a first correction calculation unit to produce the first correction formula to the first correction calculation unit, when it is determined to produce the first correction formula.

The correction signal may be a constant voltage for reference.

The correction signal may be an output signal of the pixel masked to block incident light.

A coefficient of the first correction formula may be corrected based on a rate of change of the coefficient of the second correction formula.

The method of driving a solid-state imaging device may further include: receiving the correction signal; converting the correction signal into digital signals; and outputting the digital signals as third digital signals. The first correction formula may be produced based on the third digital signals.

An image processing device may include: a plurality of first A/D converters, each of which receives output signals of respective columns of a plurality of pixels, the plurality of pixels being arranged in a matrix form, each of the plurality of first A/D converters converting the output signals into first digital signals, each of the plurality of first A/D converters outputting the first digital signals; a second A/D converter that receives a correction signal, converts the correction signal into a second digital signal, and outputs the second digital signal; a first correction calculation unit that produces a first correction formula for correcting linearity of the first digital signals; a second correction calculation unit that produces a second correction formula for correcting linearity of the second digital signal based on the second digital signal; a determination unit that compares a coefficient of the second correction formula produced by the second correction calculation unit and a coefficient of a second correction formula produced before the second correction formula, and determines whether or not to produce the first correction formula based on the comparison result; and a signal output unit that outputs an update signal for causing the first correction calculation unit to produce the first correction formula to the first correction calculation unit when it is determined to produce the first correction formula.

The correction signal may be a constant voltage for reference.

The correction signal may be an output signal of the pixel masked to block incident light.

The first correction calculation unit may correct a coefficient of the first correction formula based on a rate of change of the coefficient of the second correction formula.

The plurality of first A/D converters may receive the correction signal, convert the correction signal into digital signals, and output the digital signals as third digital signals. The first correction calculation unit may produce the first correction formula based on the third digital signals.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

First Preferred Embodiment

A first preferred embodiment of the present invention will be described below.FIG. 1is a block diagram showing a schematic constitution of a solid-state imaging device according to this embodiment. The solid-state imaging device includes a pixel unit1, an analog signal processing unit3, switch units4, a correction voltage generation unit5, a vertical driving unit6, a horizontal driving unit7, a control unit8, a correction unit9, first analog/digital (A/D) converters10, and second A/D converters20. The pixel unit1includes a plurality of pixels2arranged in a matrix form. The first A/D converters10have pulse delay circuits11. The second A/D converters20have the pulse delay circuits11.

The pixels2output optical signals according to the amount of incident light. The analog signal processing unit3calculates a difference between a reset-time signal and an incident-light-dependent optical signal output from each of the pixels2, thereby generating a pixel signal whose reset-time noise is suppressed. The analog signal processing unit3outputs the generated pixel signal as an input signal Vin. The switch units4switch signals input to the first A/D converters10and the second A/D converters20. The correction voltage generation unit5has a first voltage circuit51generating a voltage Vref3, a second voltage circuit52generating a voltage Vref2, and a third voltage circuit53generating a voltage Vref1. The voltages Vref1, Vref2and Vref3become references for producing a correction formula. The correction voltage generation unit5outputs the voltages Vref1, Vref2and Vref3by turns. The voltage Vref1is the lowest, the voltage Vref2is the second lowest, and the voltage Vref3is the highest (Vref1<Vref2<Vref3).

The vertical driving unit6selects the pixels2outputting signals from among the pixels2arranged in the matrix form according to rows. The horizontal driving unit7controls the first A/D converters10and the second A/D converters20to output output digital signals ΦD in sequence. The control unit8controls each unit that the solid-state imaging device has. The correction unit9corrects the output digital signals ΦD output by the first A/D converters10and the second A/D converters20. The first A/D converters10and the second A/D converters20are time analog-to-digital converter type A/D converters (TADs). The first A/D converters10and the second A/D converters20receive analog signals, convert the analog signals into digital signals, and output the digital signals.

The correction unit9has a first correction calculation unit110, a second correction calculation unit210, a determination unit220, and an update signal output unit230. The first correction calculation unit110produces a first correction formula for correcting linearity of outputs of the first A/D converters10. The second correction calculation unit210produces a second correction formula for correcting linearity of outputs of the second A/D converters20. The determination unit220determines whether or not there is a change in the second correction formula. The update signal output unit230outputs an update signal for causing the first correction calculation unit110to produce the first correction formula.

Next, a constitution of the first A/D converters10and the second A/D converters20will be described. The first A/D converters10have the same constitution as the second A/D converters20.FIG. 2is a block diagram showing a schematic constitution of the first A/D converters10and the second A/D converters20according to this embodiment. The first A/D converters10and the second A/D converters20include the pulse delay circuit11and a circuit for detecting the number of stages through which a pulse has passed. The circuit for detecting the number of stages through which a pulse has passed has a counter12, a latch circuit13, a latch and encoder circuit14, and a signal processing circuit15.

The pulse delay circuit11includes one delay element AND1and a plurality of delay elements DU1connected in a ring shape. The input signal Vin is supplied to each delay element. The input signal Vin is a pixel signal output by the analog signal processing unit3or a correction voltage output by the correction voltage generation unit5. The delay element delays an input pulse ΦPL for a delay time according to a signal level of the input signal Vin using the input signal Vin as a power supply voltage. The pulse delay circuit11generates a pulse signal ΦCK having a frequency according to delay times of the delay elements.

The counter12counts the pulse signal ΦCK generated by the pulse delay circuit11, that is, the number of rounds of the input pulse ΦPL. The counter12outputs the count result as a digital signal ΦD1. The latch circuit13latches the digital signal ΦD1output by the counter12and outputs the latched digital signal as a digital signal ΦD2. The latch and encoder circuit14receives outputs of the delay element in the pulse delay circuit11. The number of delay element stages through which the input pulse ΦPL has passed corresponds to position information about the pulse signal ΦCK. The latch and encoder circuit14detects the position information about the pulse signal ΦCK and outputs the detection result as a digital signal ΦD3.

The signal processing circuit15receives the digital signal ΦD2from the latch circuit13and the digital signal ΦD3from the latch and encoder circuit14. The signal processing circuit15processes the digital signals ΦD2and ΦD3, and generates a digital signal ΦD4according to the signal level of the input signal Vin, that is, the pixel signal output by the analog signal processing unit3. The digital signal ΦD4is an output digital signal ΦD (Vin) A/D-converted by the first A/D converters10and the second A/D converters20.

Next, a sequence in which the first correction calculation unit110produces a first correction formula according to this embodiment will be described. Digital signals ΦD output by the first A/D converters10are corrected using first correction formulae. Before the solid-state imaging device takes an image (e.g., immediately after a start), the first correction calculation unit110performs the following process to produce and store first correction formulae corresponding to the first A/D converters10.

At first, the control unit8controls the switch units4so that a correction voltage output by the correction voltage generation unit5is input to the first A/D converters10. Then, the correction voltage output by the correction voltage generation unit5is input to the first A/D converters10.

Subsequently, the control unit8controls the correction voltage generation unit5to output the correction voltage Vref1. The first A/D converters10output output digital signals ΦD (Vref1) according to the input correction voltage Vref1to the first correction calculation unit110. Subsequently, the control unit8controls the correction voltage generation unit5to output the correction voltage Vref2. The first A/D converters10output output digital signals ΦD (Vref2) according to the input correction voltage Vref2to the first correction calculation unit110. Subsequently, the control unit8controls the correction voltage generation unit5to output the correction voltage Vref3. The first A/D converters10output output digital signals ΦD (Vref3) according to the input correction voltage Vref3to the first correction calculation unit110. In this way, the output digital signals ΦD (Vref1), ΦD (Vref2) and ΦD (Vref3) of the first A/D converters10are input to the first correction calculation unit110.

Subsequently, the first correction calculation unit110produces first correction formulae of the first A/D converters10based on the output digital signals ΦD (Vref1), ΦD (Vref2) and ΦD (Vref3). Any correction formulae whereby outputs of the first A/D converters10can be corrected can be used as the first correction formulae of the first A/D converters10produced by the first correction calculation unit110.

For example, a case in which Formula1is used as the first correction formulae of the first A/D converters10will be described. Based on the output digital signals ΦD (Vref1), ΦD (Vref2) and ΦD (Vref3), the first correction calculation unit110calculates a slope and intercept of Formula1, which are correction coefficients, or MIN, MAX and C of Formula1, thereby producing the first correction formula. In Formula1, X denotes an output digital signal ΦD (Vin) input from the A/D converters10. MIN denotes the output digital signal ΦD (Vref1), and MAX denotes the output digital signal ΦD (Vref3). C denotes the output digital signal ΦD (Vref2). A correction value H is a digital signal ΦD (H) obtained by correcting the output digital signal ΦD (Vin) output by the first A/D converters10based on the first correction formula.

Next, a sequence in which the second correction calculation unit210produces a second correction formula according to this embodiment will be described. Output digital signals ΦD output by the second A/D converters20are corrected using second correction formulae. Before the solid-state imaging device takes an image (e.g., immediately after a start), the second correction calculation unit210performs the following process to produce and store second correction formulae of the second A/D converters20. When the solid-state imaging device outputs an image signal to the outside, the second correction calculation unit210performs the following process to produce the second correction formulae of the second A/D converters20.

At first, the control unit8controls the switch units4so that a correction voltage output by the correction voltage generation unit5is input to the second A/D converters20. Then, the correction voltage output by the correction voltage generation unit5is input to the second A/D converters20.

Subsequently, the control unit8controls the correction voltage generation unit5to output the correction voltage Vref1. The second A/D converters20output output digital signals ΦD (Vref1) according to the input correction voltage Vref1to the second correction calculation unit210. Subsequently, the control unit8controls the correction voltage generation unit5to output the correction voltage Vref2. The second A/D converters20output output digital signals ΦD (Vref2) according to the input correction voltage Vref2to the second correction calculation unit210. Subsequently, the control unit8controls the correction voltage generation unit5to output the correction voltage Vref3. The second A/D converters20output output digital signals ΦD (Vref3) according to the input correction voltage Vref3to the second correction calculation unit210. In this way, the output digital signals ΦD (Vref1), ΦD (Vref2) and ΦD (Vref3) of the second A/D converters20are input to the second correction calculation unit210.

Subsequently, the second correction calculation unit210produces second correction formulae based on the output digital signals ΦD (Vref1), ΦD (Vref2) and ΦD (Vref3) in the same way as the first correction calculation unit110produces first correction formulae.

Next, a sequence in which light is incident on the pixel unit1of the solid-state imaging device and signals generated by the pixels2are converted into digital signals according to this embodiment will be described. At first, the vertical driving unit6sets a pixel selection signal ΦSL to a “high” level. Then, the pixels2of a first row of the pixel unit1are selected, and signals of the pixels2of the selected first row are output to the analog signal processing unit3. Each of the selected pixels2outputs two signals, that is, a reset-time signal output when a photoelectric conversion device in the pixel2is reset and an incident-light-dependent optical signal according to the amount of incident light. The analog signal processing unit3calculates a difference between the reset-time signal and the incident-light-dependent optical signal output by each of the pixels2. In this way, a pixel signal whose reset-time noise is suppressed is generated. The generated pixel signal is output as the input signal Vin to the corresponding one of the first A/D converters10prepared for columns of the pixels2. At this time, the control unit8controls the switch units4and the correction voltage generation unit5to input the correction voltage Vref1generated by the correction voltage generation unit5to the second A/D converters20.

Subsequently, the control unit8sets the input pulse ΦPL output to the first A/D converters10and the second A/D converters20to a “high” level. Then, the pulse delay circuit11in each of the first A/D converters10and the second A/D converters20delays the input pulse ΦPL for a delay according to a difference between a signal level of the input signal Vin input from the analog signal processing unit3or the correction voltage generator5or the correction voltage Vref1and ground voltage GND. The pulse delay circuit11generates the pulse signal ΦCK having a frequency according to delays of the delay elements. The counter12counts the pulse signal ΦCK output by the pulse delay circuit11.

After a predetermined time period, the latch and encoder circuit14detects position information about the pulse signal ΦCK in the pulse delay circuit11. At the same time, the latch circuit13latches the count result of the counter12. After this, the control unit8sets the input pulse ΦPL to a “low” level. Then, delay of the input pulse ΦPL in the pulse delay circuit11is stopped, and generation of the pulse signal ΦCK is finished.

Subsequently, the signal processing circuit15processes the digital signal ΦD2output by the latch circuit13and the digital signal ΦD3output by the latch and encoder circuit14. Also, the signal processing circuit15outputs the digital signal ΦD4according to a signal level of the input signal Vin input from the analog signal processing unit3or the correction voltage generation unit5, or the correction voltage Vref1as the output digital signal ΦD (Vin) or ΦD (Vref1). In other words, the first A/D converters10output output digital signals ΦD (Vin) according to pixel signals of the pixels2, and the second A/D converters20output the output digital signals ΦD (Vref1) according to the correction voltage Vref1of the correction voltage generation unit5.

Subsequently, the horizontal driving unit7sets readout control signals ΦH to a “high” level in sequence. Then, the output digital signals ΦD (Vin) output by the first A/D converters10are input to the first correction calculation unit110of the correction unit9in sequence. Also, the output digital signals ΦD (Vref1) output by the second A/D converters20are input to the second correction calculation unit210of the correction unit9in sequence.

The first correction calculation unit110corrects the output digital signals ΦD (Vin) according to a first correction formula. The first correction calculation unit110outputs the digital signals ΦD (H) obtained after correction to the outside as image signals of the pixels2in the first row of the solid-state imaging device. The second correction calculation unit210temporarily stores the output digital signals ΦD (Vref1) according to the correction voltage Vref1.

Subsequently, the vertical driving unit6sets the pixel selection signal ΦSL to a “low” level. Then, the readout of the pixels2in the first row is finished.

The solid-state imaging device repeatedly performs the above-described sequence. The solid-state imaging device converts electric potentials generated by the pixels2of a second row to the last row into digital signals and outputs the digital signals to the outside as image signals of the pixels2of the second row to the last row. In this way, the solid-state imaging device can output image signals of all the pixels2to the outside.

As mentioned above, the electric potentials generated by the pixels2of the second row are converted into digital signals and output to the outside as image signals of the pixels2of the second row. At this time, the control unit8controls the switch units4and the correction voltage generation unit5to input the correction voltage Vref2generated by the correction voltage generation unit5to the second A/D converters20. The second A/D converters20output the output digital signals ΦD (Vref2) according to the correction voltage Vref2of the correction voltage generation unit5. The second correction calculation unit210temporarily stores the output digital signals ΦD (Vref2) according to the correction voltage Vref2.

As mentioned above, the electric potentials generated by the pixels2of the third row are converted into digital signals and output to the outside as image signals of the pixels2of the third row. At this time, the control unit8controls the switch units4and the correction voltage generation unit5to input the correction voltage Vref3generated by the correction voltage generation unit5to the second A/D converters20. The second A/D converters20output the output digital signals ΦD (Vref3) according to the correction voltage Vref3of the correction voltage generation unit5. The second correction calculation unit210temporarily stores the output digital signals ΦD (Vref3) according to the correction voltage Vref3.

As mentioned above, the electric potentials generated by the pixels2of the fourth row to the last row are converted into digital signals and output to the outside as image signals of the pixels2of the fourth row to the last row. At this time, the correction voltage generation unit5and the second A/D converters20do not perform the same process as mentioned above. At this time, the second correction calculation unit210produces second correction formulae of the second A/D converters20based on the output digital signals ΦD (Vref1), ΦD (Vref2) and ΦD (Vref3). Then, the second correction calculation unit210can newly produce second correction formulae of the second A/D converters20every time the solid-state imaging device takes an image. After producing the second correction formulae, the second correction calculation unit210removes the temporarily stored output digital signals ΦD (Vref1), ΦD (Vref2) and ΦD (Vref3).

Next, a sequence of newly producing a first correction formula will be described.FIG. 3is a flowchart illustrating a sequence of newly producing a first correction formula according to this embodiment.

The solid-state imaging device takes an image. At this time, the second correction calculation unit210produces correction formulae of the second A/D converters20. Then, the process proceeds to step S102.

The determination unit220calculates a rate of change between a correction coefficient of a second correction formula of each of the second A/D converters20stored by the second correction calculation unit210and a correction coefficient of a second correction formula of the second A/D converters20produced in step S101. Then, the process proceeds to step S103.

The determination unit220compares the rate of change calculated in step S102and a predetermined reference value. Then, the process proceeds to step S104. However, when the solid-state imaging device has a plurality of second A/D converters20, a rate of change of a correction coefficient of a second correction formula of any one of the second A/D converters20may be compared with the predetermined reference value. Alternatively, the average rate of change of correction coefficients of second correction formulae of the plurality of second A/D converters20may be compared with the predetermined reference value.

The determination unit220determines whether or not the rate of change calculated in step S102is the predetermined reference value or more based on the comparison result of step S103. When it is determined that the rate of change calculated in step S102is the predetermined reference value or more, the process proceeds to step S106. On the other hand, when it is determined that the rate of change calculated in step S102is less than the predetermined reference value, the process proceeds to step S105.

The determination unit220determines not to newly produce a first correction formula. The second correction calculation unit210discards the second correction formulae produced in step S101. Then, the process proceeds back to step S101.

The determination unit220determines to newly produce a first correction formula. Then, the process proceeds to step S107.

Since the determination unit220has determined to newly produce a first correction formula, the update signal output unit230outputs a signal for newly producing a first correction formula to the first correction calculation unit110. Then, the process proceeds to step S108.

Since the signal for newly producing a first correction formula has been input from the update signal output unit230, the first correction calculation unit110newly produces a first correction formula. Thereafter, the first correction calculation unit110corrects output digital signals ΦD (Vin) using the newly produced first correction formula. The second correction calculation unit210discards a stored second correction formula and stores the second correction formulae produced in step S101. Then, the process proceeds back to step S101. Here, any method can be used for the first correction calculation unit110to newly produce a first correction formula.

For example, in step S102, the first correction calculation unit110may newly produce a first correction formula using the rate of change of the correction coefficient of the second correction formula calculated by the determination unit220. When temperature of the solid-state imaging device varies and thus the correction coefficient of the first correction formula and the correction coefficient of the second correction formula vary, the correction coefficient of the first correction formula can be considered to have the same rate of change as the second correction formula. The first correction calculation unit110corrects the correction coefficient of the first correction formula so that the rate of change of the correction coefficient of the first correction formula becomes the same as that of the correction coefficient of the second correction formula. For example, when the correction coefficient of the second correction formula becomes 1.2 times the original correction coefficient, the first correction calculation unit110multiplies the correction coefficient of the first correction formula by 1.2. In this way, the first correction calculation unit110can newly produce a first correction formula using the rate of change of the correction coefficient of the second correction formula.

When the solid-state imaging device has the plurality of second A/D converters20, the determination unit220may calculate the average rate of change of correction coefficients of second correction formulae of the plurality of second A/D converters20. The first correction calculation unit110may correct the correction coefficient of the first correction formula using the average rate of change. In this way, the first correction calculation unit110can newly produce a first correction formula using the average rate of change of the correction coefficients of the second correction formulae.

When the solid-state imaging device has two second A/D converters20and, as shown inFIG. 1, the two second A/D converters20are disposed to be spaced apart from each other with the first A/D converters10interposed between them, an average rate of change of correction coefficients of second correction formulae of the two second A/D converters20may not be simply used, but distance from the two second A/D converters20may be taken into consideration to produce a first correction formula. To be specific, the determination unit220calculates a rate of change of a correction coefficient according to the distance from the two second A/D converters20.

The first correction calculation unit110corrects the correction coefficient of the first correction formula using the rate of change of a correction coefficient according to the distance from the two second A/D converters20. In this way, the first correction calculation unit110can newly produce a first correction formula using the rate of change of a correction coefficient according to the distance from the two second A/D converters20.

For example, a rate of change of a correction coefficient of a second correction formula of the left second A/D converter20is ΔAL20, and a rate of change of a correction coefficient of a second correction formula of the right second A/D converter20is ΔAL20. Between the left second A/D converter20and the right second A/D converter20, n first A/D converters10are installed at regular intervals. Correction coefficients of first correction formulae of the first A/D converters10are A10_1, A10_2, A10_3, . . . , and A10_n in order from left to right.

In consideration of the distance from the two second A/D converters20, rates of change of the correction coefficients of the first correction formulae of the first A/D converters10become ΔAL20, {ΔAL20×(n−1)+ΔAR20×1}/n, {ΔAL20×(n−2)+ΔAR20×2}/n, . . . , and ΔAR20in order from left to right.

Thus, a correction coefficient of a corrected first correction formula of the leftmost first A/D converter10becomes A10_1×ΔAL20. A correction coefficient of a corrected first correction formula of the first A/D converter10that is the second from the left becomes A10_2×{ΔAL20×(n−1)+ΔAR20×1}/n. A correction coefficient of a corrected first correction formula of the first A/D converter10that is the third from the left becomes A10_3×{ΔAL20×(n−2)+ΔAR20×2}/n. Also, a correction coefficient of a corrected first correction formula of the rightmost first A/D converter10that is the n-th from the left becomes A10_n×ΔAR20.

In this way, the correction coefficient of the first correction formula is corrected using the rate of change of the correction coefficient according to the distance from the two second A/D converters20, so that even if there is a temperature difference between the left second A/D converter20and the right second A/D converter20, a first correction formula can be newly produced according to the temperature difference.

A first correction formula may be produced in the same way as a first correction formula produced before the solid-state imaging device takes an image. This method has greater throughput than a method of correcting a correction coefficient of a first correction formula using a rate of change of a correction coefficient of a second correction formula. Since a correction coefficient of a previously produced first correction formula is not corrected but the first correction calculation unit110produces a first correction formula using a reference voltage, accuracy of the first correction formula improves.

As described above, in this embodiment, first correction formulae of the plurality of first A/D converters10are not repeatedly produced, but second correction formulae of the second A/D converters20having a smaller number than the first A/D converters10are repeatedly produced. Also, when correction coefficients of the second correction formulae vary at a predetermined rate of change or more, first correction formulae of the first A/D converters10are newly produced. In this way, it is possible to reduce the number of correction formulae repeatedly produced in the solid-state imaging device. Thus, the production throughput of the first correction formulae of the first A/D converters10can be reduced.

In this embodiment, the first correction calculation unit110can also produce first correction formulae of the first A/D converters10based on correction coefficients of second correction formulae of the second A/D converters20. In this case, correction coefficients of previously produced first correction formulae are corrected to produce the first correction formulae. Thus, this method has lower throughput than a method of producing first correction formulae using a reference voltage. In other words, correction throughput of the first correction formulae can be reduced.

Second Preferred Embodiment

A second preferred embodiment of the present invention will be described below with reference to a drawing. A solid-state imaging device of this embodiment is different from that of the first preferred embodiment in that a pixel unit1has optical black (OB) pixels, and a correction voltage generation unit5has a first voltage circuit51generating a voltage Vref3and a second voltage circuit52generating a voltage Vref2.

FIG. 4is a block diagram showing a schematic constitution of the solid-state imaging device according to this embodiment. In an example shown in the drawing, the solid-state imaging device includes the pixel unit1, an analog signal processing unit3, switch units4, the correction voltage generation unit5, a vertical driving unit6, a horizontal driving unit7, a control unit8, a correction unit9, first A/D converters10, and second A/D converters20. The pixel unit1includes a plurality of pixels2and light-shielded OB pixels201arranged in a matrix form.

The correction unit9has a first correction calculation unit110, a second correction calculation unit210, a determination unit220, and an update signal output unit230. The first correction calculation unit110produces a first correction formula for correcting linearity of the first A/D converters10. The second correction calculation unit210produces a second correction formula for correcting linearity of the second A/D converters20. The determination unit220determines whether or not there is a change in the second correction formula. The update signal output unit230outputs an update signal to the first correction calculation unit110. The units of the solid-state imaging device are the same as those of the solid-state imaging device of the first preferred embodiment except for the pixel unit1. Constitutions of the first A/D converters10and the second A/D converters20are the same as those of the first preferred embodiment, that is, the same as shown inFIG. 2. The OB pixels201are masked to block incident light.

Next, a sequence in which the first correction calculation unit110produces a first correction formula according to this embodiment will be described. Digital signals ΦD output by the first A/D converters10are corrected using a first correction formula. Before the solid-state imaging device takes an image (e.g., immediately after a start), the first correction calculation unit110performs the following process to produce and store first correction formulae corresponding to the first A/D converters10.

At first, the control unit8controls the switch units4so that an input signal Vin output by the analog signal processing unit3is input to each of the first A/D converters10. Subsequently, the control unit8controls the vertical driving unit6to input signals of the OB pixels201in a fifth row of the pixel unit1to the analog signal processing unit3. The analog signal processing unit3generates pixel signals whose noise has been suppressed. The analog signal processing unit3outputs the generated pixel signals as input signals Vin(ob) to the first A/D converters10prepared according to columns of the pixels and the OB pixels201. The first A/D converters10output output digital signals ΦD (Vin(ob)) according to the input signals Vin(ob) of the OB pixels201to the first correction calculation unit110.

Subsequently, the control unit8controls the switch units4so that a correction voltage output by the correction voltage generation unit5is input to the first A/D converters10. Thus, a correction voltage output by the correction voltage generation unit5is input to the first A/D converters10. Subsequently, the control unit8controls the correction voltage generation unit5to output the correction voltage Vref2. The first A/D converters10output output digital signals ΦD (Vref2) according to the input correction voltage Vref2to the first correction calculation unit110. Subsequently, the control unit8controls the correction voltage generation unit5to output the correction voltage Vref3. The first A/D converters10output output digital signals ΦD (Vref3) according to the input correction voltage Vref3to the first correction calculation unit110. In this way, the output digital signals ΦD (Vin(ob)), ΦD (Vref2) and ΦD (Vref3) of the first A/D converters10are input to the first correction calculation unit110. Here, the input signals Vin(ob) have the lowest voltage, the correction voltage Vref2is the second lowest, and the correction voltage Vref3is the highest (Vin(ob)<Vref2<Vref3).

Subsequently, the first correction calculation unit110produces correction formulae of the first A/D converters10based on the output digital signals ΦD (Vin(ob)), ΦD (Vref2) and ΦD (Vref3). Any correction formulae whereby outputs of the first A/D converters10can be corrected can be used as the correction formulae of the first A/D converters10produced by the first correction calculation unit110. For example, the correction formulae are produced in the same way as described in the first preferred embodiment.

Next, a sequence in which the second correction calculation unit210produces a second correction formula according to this embodiment will be described. Output digital signals ΦD output by the second A/D converters20are corrected using second correction formulae. Before the solid-state imaging device takes an image (e.g., immediately after a start), the second correction calculation unit210performs the following process to produce and store second correction formulae of the second A/D converters20. When the solid-state imaging device outputs an image signal to the outside, the second correction calculation unit210also performs the following process to produce second correction formulae of the second A/D converters20.

At first, the control unit8controls the switch units4so that the input signal Vin output by the analog signal processing unit3is input to the first A/D converters10. Subsequently, the control unit8controls the vertical driving unit6to input a signal of one OB pixel201per row among OB pixels201disposed in a first column and a fifth row of the pixel unit1to the analog signal processing unit3. The analog signal processing unit3generates pixel signals whose noise has been suppressed. The generated pixel signals are output to the second A/D converters20as the input signals Vin(ob). The second A/D converters20output output digital signals ΦD (Vin(ob)) according to the input signals Vin(ob) of the OB pixels201to the second correction calculation unit210.

Subsequently, the control unit8controls the switch units4so that a correction voltage output by the correction voltage generation unit5is input to the second A/D converters20. Thus, a correction voltage output by the correction voltage generation unit5is input to the second A/D converters20. Subsequently, the control unit8controls the correction voltage generation unit5to output the correction voltage Vref2. The second A/D converters20output output digital signals ΦD (Vref2) according to the input correction voltage Vref2to the second correction calculation unit210. Subsequently, the control unit8controls the correction voltage generation unit5to output the correction voltage Vref3. The second A/D converters20output output digital signals ΦD (Vref3) according to the input correction voltage Vref3to the second correction calculation unit210. In this way, the output digital signals ΦD (Vin(ob)), ΦD (Vref2) and ΦD (Vref3) of the second A/D converters20are input to the second correction calculation unit210.

Subsequently, the second correction calculation unit210produces second correction formulae in the same way as the first correction calculation unit110based on the output digital signals ΦD (Vin(ob)), ΦD (Vref2) and ΦD (Vref3).

As described above, in this embodiment, the first A/D converters10and the second A/D converters20output the output digital signals ΦD (Vin(ob)) according to the input signals Vin(ob) resulting from pixel signals of the OB pixels201, the output digital signals ΦD (Vref2) according to the correction voltage Vref2output by the correction voltage generation unit5, and the output digital signals ΦD (Vref3) according to the correction voltage Vref3output by the correction voltage generation unit5. The first correction calculation unit110produces first correction formulae based on the output digital signals ΦD (Vin(ob)), ΦD (Vref2) and ΦD (Vref3) output by the first A/D converters10. The second correction calculation unit210produces second correction formulae based on the output digital signals ΦD (Vin(ob)), ΦD (Vref2) and ΦD (Vref3) output by the second A/D converters20.

In other words, unlike the first preferred embodiment, signals output by the OB pixels201are used instead of the correction voltage Vref1to produce first correction formulae and second correction formulae in this embodiment. Thus, the correction voltage generation unit5only has the first voltage circuit51generating the voltage Vref3and the second voltage circuit52generating the voltage Vref2, and the circuit size can be reduced.

As used herein, the following directional terms “forward, rearward, above, downward, right, left, vertical, horizontal, below, and transverse” as well as any other similar directional terms refer to those directions of an apparatus equipped with the present invention. Accordingly, these terms, as utilized to describe the present invention should be interpreted relative to an apparatus equipped with the present invention.

The term “configured” is used to describe a component, section or part of a device includes hardware and/or software that is constructed and/or programmed to carry out the desired function.

The terms of degree such as “substantially,” “about,” “nearly”, and “approximately” as used herein mean a reasonable amount of deviation of the modified term such that the end result is not significantly changed. For example, these terms can be construed as including a deviation of at least ±5 percents of the modified term if this deviation would not negate the meaning of the word it modifies.

The term “unit” is used to describe a component, section or part of a hardware and/or software that is constructed and/or programmed to carry out the desired function. Typical examples of the hardware may include, but are not limited to, a device and a circuit.