Counter circuit

A counter circuit includes a first Johnson counter circuit and a second Johnson counter circuit coupled in cascade. Each Johnson counter circuit includes a clock input, a data input, a first clock data output, a second clock data output and a feedback from the second clock data input to first data input. The clock input of the first Johnson counter circuit is configured to receive an input clock signal. The clock input of the second Johnson counter circuit is connected to the second clock data output of the first Johnson counter circuit. A ripple counter circuit has a clock input and additional clock data outputs. The clock input of the ripple counter circuit is connected to the second clock data output of the preceding Johnson counter circuit.

TECHNICAL FIELD

The present disclosure generally relates to electronic circuits and, more particularly, to counter circuits.

BACKGROUND

Reference is now made toFIG. 1showing a block diagram of an n-bit Johnson counter circuit10. The counter circuit10includes n flip-flops12(l)-12(n) arranged in cascade with the output of one flip flop12coupled to the data input of a next flip flop. The output of the last flip-flop12(n) is fed back to the data input of the first flip-flop12(l) with a signal inversion. The clock inputs (>) of each of the included flip-flops12are coupled to receive a common clock signal (CLK). The output bits Q1-Qn of the counter circuit10are taken at the corresponding outputs of the included flip-flops12. In an embodiment, the flip-flops12comprise D-type flip-flops as well known to those skilled in the art. Each D-type flip-flop12includes a data input D and a pair of complementary data outputs Q and QB. The Q output of one flip-flop is coupled to the data input D of the succeeding flip flop, and the QB output of the last flip-flop is coupled to the data input D of the first flip-flop (thus implementing the data inversion, which could instead be implemented using a logic inverter connected to the Q output). The counter circuit10functions as divider of the clock signal CLK to produce n output clock signals Q1-Qn, with each output clock signal having a frequency equal to the clock signal frequency divided by 2n and being phase shifted relative to each other by the period of the clock signal. See,FIG. 1Afor output waveforms for an n=4 Johnson counter.

Reference is now made toFIG. 2showing a block diagram of an m-bit ripple counter circuit20. The counter circuit20includes m flip-flops22(l)-22(m) arranged in cascade with the data output of one flip flop12coupled to the clock input (>) of a next flip flop. More specifically, the output of a previous flip-flop22is coupled to the clock input of a succeeding flip-flop. A complementary data output of each flip-flop22is coupled to the data input D of that same flip-flop. The first flip-flop22is coupled to receive an input clock signal CLK at its clock input. The output bits Q1-Qm of the counter circuit20are taken at the corresponding data outputs of the included flip-flops22. In an embodiment, the flip-flops22comprise D-type flip-flops as well known to those skilled in the art. Each D-type flip-flop22includes a data input D and a pair of complementary data outputs Q and QB. The Q output of one flip-flop is coupled to the clock input of the succeeding flip flop, and the QB output of each flip-flop is coupled to the data input D of that same flip-flop (alternatively, an inverter circuit may be coupled to the Q output to provide the inverted feedback to the data input). The counter circuit20functions as divider of the clock signal CLK to produce n output clock signals Q1-Qn, with each output clock signal having a frequency equal to one half of the signal received at its clock input. See,FIG. 2Afor output waveforms for m=4.

There is a need for an improved counter circuit operable at a reduced power consumption.

SUMMARY

In an embodiment, a counter circuit comprises: a first Johnson counter circuit having a first clock input and a first plurality of clock data outputs; a second Johnson counter circuit having a second clock input and a second plurality of clock data outputs; wherein the first clock input is configured to receive an input clock signal; and wherein the second clock input is connected to one of the first plurality of clock data outputs.

A ripple counter circuit having a third clock input and a third plurality of clock data outputs may be included in the counter circuit, with the third clock input connected to one of the second plurality of clock data outputs.

In an embodiment, a counter circuit comprises: a first Johnson counter circuit having a first clock input, a first data input, a first clock data output, a second clock data output and a feedback from the second clock data input to first data input; a second Johnson counter circuit having a second clock input, a second data input, a third clock data output, a fourth clock data output and a feedback from the fourth clock data input to second data input; wherein the first clock input is configured to receive an input clock signal; and wherein the second clock input is directly connected to the second clock data output.

A ripple counter circuit having a third clock input and a plurality of additional clock data output may be included in the counter circuit, with the third clock input connected to the fourth clock data output.

DETAILED DESCRIPTION

The same elements have been designated with the same reference numerals in the different drawings. In particular, the structural and/or functional elements common to the different embodiments may be designated with the same reference numerals and may have identical structural, dimensional, and material properties. For clarity, only those steps and elements which are useful to the understanding of the described embodiments have been shown and will be detailed. In particular, the circuits powered by the power converter have not been detailed, the described embodiments being compatible with usual applications. In the following description, when reference is made to terms “about”, “approximately”, or “in the order of”, this means to within 10%, preferably to within 5%.

Reference is now made toFIG. 3showing a block diagram for an embodiment of a counter circuit30. The counter circuit30comprises a plurality of Johnson counter circuits32(1)-32(p) coupled in cascade. A first one of the Johnson counter circuits32(1) includes a clock input (>) configured to receive an input clock signal CLK. A data output of each Johnson counter circuit32(for example, output Q2) is coupled to the clock input of a succeeding Johnson counter circuit32.

Each Johnson counter circuit32is preferably a 2-bit Johnson counter circuit as shown inFIG. 3A. The Johnson counter circuit32includes two flip-flops42(1)-42(2) arranged in cascade with the data output of the first flip flop42(1) coupled to the data input of the second flip flop42(2). The data output of the second flip-flop42(2) is fed back to the data input of the first flip-flop42(1) with a signal inversion. The clock inputs (>) of each of the included flip-flops42are coupled to receive a common clock signal. The output bits O1-O2of the counter circuit32are taken at the corresponding data outputs of the included flip-flops42. In an embodiment, the flip-flops42comprise D-type flip-flops as well known to those skilled in the art. Each D-type flip-flop12includes a data input D and a pair of complementary data outputs Q and QB. The Q output of the first flip-flop42(1) is coupled to the data input D of the second flip flop42(2), and the QB output of the second flip-flop42(2) is coupled to the data input D of the first flip-flop42(1) (alternatively implemented using an inverter circuit coupled to the Q output to provide the data inversion in feedback). The circuit32functions as divider of the received clock signal to produce two output clock signals Q1-Q2, with each output clock signal having a frequency equal to the clock signal frequency divided by 4 and being phase shifted relative to each other by the period of the clock signal.

The counter circuit30produces, from the p Q1outputs and p Q2outputs of the included counter circuits32,2poutput clocks O1-O2p.FIG. 3Bshows the output waveforms for the first four outputs O1-O4. The counter circuit30presents advantages over a corresponding m-bit ripple counter (like that shown inFIG. 2) wherein m=2p. The four least significant bits (LSBs) of the ripple counter consume more than 90% of the overall power of the counter circuitry. In the counter circuit30, the 4 LSBs of the counter circuit are implemented by two 2-bit Johnson counters32in cascade. The Johnson counter implements four D flip-flop commutations per counting cycle while a correspondingly sized ripple counter implements six D flip-flop commutations per counting cycle. The 2-bit Johnson counter thus has a theoretical 33% power savings compared to the ripple counter. Use of the Johnson counter in at least the positions of the LSBs which undergo the most logic state changes significantly reduces power consumption. Power savings of 14-16% or more for counters have been measured by simulation with the counter circuit30in comparison to a correspondingly sized ripple counter like that ofFIG. 2.

Reference is now made toFIG. 4showing a block diagram for an embodiment of a counter circuit40. The counter circuit40comprises a plurality of Johnson counter circuits32(1)-32(j) coupled in cascade with each other (in an example, j=2) and with a k-bit ripple counter46. In this embodiment, the Johnson counter circuits32provide the LSBs outputs Ol-O2jand the ripple counter46provides the most significant bits (MSBs) outputs O2j+1-O2j+k.

A first one of the Johnson counter circuits32(l) includes a clock input (>) configured to receive an input clock signal CLK. A data output of each Johnson counter circuit32is coupled to the clock input of a succeeding Johnson counter circuit32. A data output of the last Johnson counter circuit32(j) is coupled to the clock input of the k-bit ripple counter46.

Each Johnson counter circuit32is preferably a 2-bit Johnson counter circuit as shown inFIG. 3A. The Johnson counter circuit32includes two flip-flops42(1)-42(2) arranged in cascade with the data output of the first flip flop42(1) coupled to the data input of the second flip flop42(2). The data output of the second flip-flop42(2) is fed back to the data input of the first flip-flop42(1) with a signal inversion. The clock inputs (>) of each of the included flip-flops42are coupled to receive a common clock signal. The output bits Q1-Q2of the counter circuit32are taken at the corresponding data outputs of the included flip-flops42. In an embodiment, the flip-flops42comprise D-type flip-flops as well known to those skilled in the art. Each D-type flip-flop12includes a data input D and a pair of complementary data outputs Q and QB. The Q output of the first flip-flop42(1) is coupled to the data input D of the second flip flop42(2), and the QB output of the second flip-flop42(2) is coupled to the data input D of the first flip-flop42(1) (alternatively, an inverter circuit could be connected to the Q output to provide the signal inversion in feedback). The counter circuit32functions as divider of the received clock signal to produce two output clock signals Q1-Q2, with each output clock signal having a frequency equal to the clock signal frequency divided by 4 and being phase shifted relative to each other by the period of the clock signal.

The k-bit ripple counter46may have a circuit configuration as shown inFIG. 2(where m=k).

Simulation of the counter40reveals an approximately 30% reduction in power consumption when compared to a conventional ripple counter of equal number of bits (like that ofFIG. 2). This reduction in power consumption is attributed to the use of the Johnson counter circuits32for the LSBs. A further reduction in power may be accomplished through efficient layout of the circuit components (for example, by implementation of measures for compactness such as with a minimization of source/drain diffusion area for the transistors). This further reduction may be on the order of an additional 30%.

Various embodiments have been described. Various alterations, modifications, and improvements will readily occur to those skilled in the art. Further, the practical implementation of the embodiments which have been described is within the abilities of those skilled in the art based on the functional indications given hereabove.