BMC-hosted real-time clock and non-volatile RAM replacement

A baseboard management controller (BMC) hosts a real-time clock and non-volatile RAM replacement that does not require a battery power supply. The BMC includes an I/O mapped interface responsive to I/O accesses to an address range associated with storage locations of a real-time clock circuit and storage locations holding configuration information. The BMC receives power when a processor coupled to the BMC is not powered. The I/O address range may include 70h and 71h. A network interface may communicate information between a network external to the BMC and the real-time clock and/or the storage locations holding the configuration information. The network external to the BMC may communicate clock synchronization and/or configuration information to the BMC.

CROSS-REFERENCE TO RELATED APPLICATION(S)

BACKGROUND

1. Field of the Invention

This invention relates to computing systems and more particularly to the real-time clock and configuration parameters utilized by computers.

2. Description of the Related Art

In prior art systems, the real-time clock was a battery-powered circuit providing date and time information independently from power supplied to the central processing unit (CPU) and other system components. When the computer is turned off, the real-time clock continues to update the time and date. In prior art systems, the real-time clock stores the time and date in a circuit on the motherboard of the computer called the CMOS RAM. The CMOS RAM also stores information relating to system configuration. The CMOS RAM is supplied with battery power to maintain configuration data even when the computer is powered off. During the boot process, the Basic Input/Output System (BIOS) utilizes information from the CMOS RAM, reads the time and date from the CMOS RAM, and sets an internal system clock used by software based on the time/date information.

Prior art implementations include the real-time clock and the CMOS RAM in a single device. Referring toFIG. 1, a prior art computer system100includes a CPU102, connected to an I/O interface104that connects to integrated circuit106. Device106includes a real-time clock108, and CMOS RAM110. CMOS RAM110includes storage locations112and114for date, time, and configuration data storage. A typical CMOS RAM implementation includes at least 64 bytes and may operate for several years with a single battery.

The bytes of the CMOS RAM can be addressed individually. Typically, the first 14 bytes of the CMOS RAM are reserved for time and date information and the control and status registers for the real-time clock. The remainder of the CMOS RAM stores hardware-specific information including processor clock speed, size of the BIOS ROM, data bus size, etc. The typical CMOS RAM includes four status registers that are used for monitoring and programming the operating mode of the real-time clock and the CMOS RAM chip. The real-time clock may be accelerated, slowed down, initialized, or adjusted for daylight savings time. In addition, various interrupts can be enabled. The CMOS RAM also stores information regarding the shutdown status of the computer and the indicators for memory and power failures. CMOS RAM110has typically been accessed in two ways: limited access via a BIOS interrupt1Ah, and complete access via the address and data register accessible via input/output instructions at ports70hand71h.

BIOS interrupt1Ah provides access to date and time features of the real-time clock. Although CMOS RAM110includes additional data storage locations that are not part of the function of these date and time features, the additional data storage locations are not accessible via the BIOS interrupt handler for interrupt1Ah. Instead, data stored in these additional data storage locations, e.g., configuration data, are accessed via the ports70hand71h. Port70haccesses the address register of the CMOS RAM110and port71haccesses the data register of the CMOS RAM110. CPU102may access CMOS RAM110via the I/O interface104, by accessing I/O ports numbered70hand71h. CPU102supplies an address to port70hand retrieves the corresponding byte of data from port71h.

Device106is powered by battery116. Although device106requires little power as compared to other memory circuits, it may need replacement after several years. Depending on the implementation, battery replacement may require merely opening the device package and replacing the battery, replacing the entire chip, or even replacing the motherboard. Replacement may be expensive and data may be lost in the process. Therefore, it would be desirable to replace device106with an implementation that does not require a battery power supply.

SUMMARY

Accordingly, the invention provides a BMC-hosted real-time clock and non-volatile RAM replacement that does not require a battery power supply.

In one embodiment of the invention, the BMC includes an I/O mapped interface responsive to I/O accesses to an address range associated with storage locations of a real-time clock circuit and storage locations holding configuration information. The BMC receives power when a processor coupled to the BMC is not powered. In one embodiment of the invention, the I/O address range includes70hand71h.

In one embodiment of the invention, a network interface communicates information between a network external to the BMC and the real-time clock and/or the storage locations holding the configuration information. The network external to the BMC communicates clock synchronization and/or configuration information to the BMC.

DESCRIPTION OF THE PREFERRED EMBODIMENT(S)

Servers are computing systems that give multiple clients access to the same data or resources. A group of networked servers that reside in a single location are known as server farms. Processes are distributed among these servers to improve performance and reliability of processes running on the individual servers. Software tracks the processing demand from individual machines, prioritizing tasks, and scheduling and rescheduling these tasks.

The Intelligent Platform Management Interface (IPMI) architecture specification defines a common interface to the hardware that monitors server physical health characteristics including temperature, voltage, fans, power supplies, and chassis intrusion. For a detailed description of the IPMI architecture, see Intel Corp., Hewlett-Packard Corp., NEC Corp., & Dell Computer Corp.,Intelligent Platform Management Interface Specification v1.5, (Feb. 20, 2002), which is incorporated herein by reference.

IPMI also includes automatic alerting, automatic system shutdown and restart, remote restart and power control capabilities, and asset tracking. The standard describes an interface for remote management of servers and systems. Managers can determine the health of systems whether the servers are running normally or the servers are in a non-operational state. A characteristic of an IPMI-compliant system is that inventory, monitoring, logging, and recovery control functions are available independent from the main processors, BIOS, and the operating system.

One of the main elements of an IPMI-compliant system is the baseboard management controller (BMC).FIG. 2illustrates BMC200configured according to an embodiment consistent with the present invention. The BMC is a central management controller that monitors system parameters, logs events, provides recovery control, manages the interface between system management software and platform management hardware, and provides a gateway between system management software and the Intelligent Chassis Management Bus (ICMB) and the Intelligent Platform Management Bus (IPMB) in an IPMI-compliant system. The BMC operates autonomously from the main processors, BIOS, and operating system, and functions even when the system is in a powered-down state. This may be accomplished by providing a power plane that allows power to be supplied independently of power supplied to other system components, including the CPU(s). Note that any sensors that are to be monitored by the BMC while system power is down (e.g., chassis temperature sensors) also supplied by this “always on” power plane. The BMC is a trusted component that is connected to a central monitoring facility by a local area network (LAN) connection. The BMC enables remote monitoring and control of the operational state of the system. The BMC functionality may be implemented with a combination of hardware and firmware.

Because the BMC functions when the system is powered down, the functions of the RTC and the CMOS RAM may be incorporated into the BMC and the battery may be eliminated.

FIG. 2illustrates an exemplary BMC200embodying an embodiment of the present invention. The BMC200includes a70h/71hfront end204, a real-time clock206, and storage210, which may be implemented as SRAM. In one embodiment,70h/71hfront end204is implemented by firmware running on the BMC200. The70h/71hfront end204emulates the port functionality of an address register70hand a data register71hinteracting with storage. An example of the behavior emulated by the70h/71hfront end is illustrated by the following assembly code instructions:;Read contents of location30hof the CMOS RAM:mov al,30h; Set up the CMOS RAM addressout70h, al; Write the address to70hin al,71h; Read contents of CMOS RAM location30hinto al register;Write55hto location30hof the CMOS RAM:mov al,30h; Set up the CMOS RAM addressout70h, al; Write the address to port70hmov al,55h; Set up data to be writtenout71h, al; Write the data55hto address CMOS RAM location30h;Location30hof the CMOS RAM now contains data55h.
The address being accessed is written to port70h. Data is read or written from port71hin response to a read or write access, respectively.

In one embodiment, real-time clock206is implemented via a background firmware process that increments a counter at a predefined rate. The real-time clock206stores the counter value in memory via storage interface208. Storage interface208reads and writes real-time clock data and configuration data to storage210. In one embodiment, storage interface208is a firmware process that copies the configuration information and/or information related to the real-time clock from memory210to non-volatile memory212. That way, in the event of a failure in the power being supplied to the BMC, the information will not be lost. Serial EEPROM212is available to BMC200for non-volatile storage. Alternative embodiments may include SRAM external to the BMC, non-volatile memory internal to the BMC, or a combination thereof. In one embodiment, non-volatile storage may be provided by a remote computer that communicates with BMC200via LAN218. Thus, the cost of an individual system including BMC200may be reduced by relocating nonvolatile storage for storing the contents of the CMOS RAM to a remote computer. In one embodiment, BMC200emulates some or all functions of the real-time clock in firmware, thus reducing the system cost by eliminating hardware. In one embodiment, network interface202can receive real-time clock synchronization data and/or configuration information from a remote computer. In one embodiment, storage interface208receives those data and updates appropriate locations of memory210corresponding to the real-time clock. Alternatively, network interface202may communicate real-time clock data directly to real-time clock206. In addition, network interface202communicates real-time clock synchronization data and configuration information from the storage interface208to facilitate system monitoring by a remote computer.

FIG. 3illustrates a server computing system incorporating an embodiment of the present invention. Server300is connected to a remote computer310by LAN218. Within server300, baseboard management controller200communicates with CPU302via port interface304. Memory buffer308is connected to the baseboard management controller200via bus316. Baseboard management controller200receives configuration data or real-time clock synchronization data from remote computer310. Baseboard management controller200receives power from power supply312even when CPU302is powered off.

In one embodiment, if the server power fails and thus the power supplied to BMC200fails, system time may be lost. However, remote computer310can detect when the BMC power plane is restored and remote computer310programs BMC200with the correct time, without CPU302detecting the time loss. In addition, individual time drift on server300can be eliminated by receiving a time update from remote computer310.

FIG. 4illustrates multiple servers404–412including the present invention. Servers404–412are connected to remote computer402. Remote computer402can monitor the real-time clocks and configuration information on all of the servers on the network. In addition, remote computer402can download identical real-time clock synchronization information and/or configuration information to all or a subset of servers404–412. That allows efficient updates in a multiple server environment.

The description of the invention set forth herein is illustrative, and is not intended to limit the scope of the invention as set forth in the following claims. For example, while the invention has been described in an embodiment in which the70h/71hfront end, storage interface, and real-time clock are implemented in firmware, one of skill in the art will appreciate that the teachings herein can be utilized with hardware implementations of these blocks. Variations and modifications of the embodiments disclosed herein, may be made based on the description set forth herein, without departing from the scope and spirit of the invention as set forth in the following claims.