Method and system for filter calibration using fractional-N frequency synthesized signals

A method and system for filter calibration using fractional-N frequency synthesized signals are presented. The method may include generating an Local Oscillator (LO) signal by a Phase Locked Loop (PLL) circuit within a chip. A reference signal may be generated based on the generated LO signal and a synthesizer control signal. A frequency response for a filter circuit integrated within the chip may be calibrated by adjusting parameters associated with the filter circuit based on the generated LO signal. The system may include a single-chip multi-band RF receiver that enables generation of a LO signal by a PLL circuit within the single-chip, and enables calibration of a frequency response for a filter circuit integrated within the chip. A reference signal may be generated based on the generated LO signal and a synthesizer control signal. The frequency response may be calibrated by adjusting the filter based on the generated reference signal.

FIELD OF THE INVENTION

Certain embodiments of the invention relate to on-chip RF tuners. More specifically, certain embodiments of the invention relate to a method and system for filter calibration using fractional-N frequency synthesized signals.

BACKGROUND OF THE INVENTION

Broadcasting and telecommunications have historically occupied separate fields. In the past, broadcasting was largely an “over-the-air” medium while wired media carried telecommunications. That distinction may no longer apply as both broadcasting and telecommunications may be delivered over either wired or wireless media. Present development may adapt broadcasting to mobility services. One limitation has been that broadcasting may often require high bit rate data transmission at rates higher than could be supported by existing mobile communications networks. However, with emerging developments in wireless communications technology, even this obstacle may be overcome.

Terrestrial television and radio broadcast networks have made use of high power transmitters covering broad service areas, which enable one-way distribution of content to user equipment such as televisions and radios. By contrast, wireless telecommunications networks have made use of low power transmitters, which have covered relatively small areas known as “cells”. Unlike broadcast networks, wireless networks may be adapted to provide two-way interactive services between users of user equipment such as telephones and computer equipment.

The introduction of cellular communications systems in the late 1970's and early 1980's represented a significant advance in mobile communications. The networks of this period may be commonly known as first generation, or “1G” systems. These systems were based upon analog, circuit-switching technology, the most prominent of these systems may have been the advanced mobile phone system (AMPS). Second generation, or “2G” systems, ushered improvements in performance over 1G systems and introduced digital technology to mobile communications. Exemplary 2G systems include the global system for mobile communications (GSM), digital AMPS (D-AMPS), and code division multiple access (CDMA). Many of these systems have been designed according to the paradigm of the traditional telephony architecture, often focused on circuit-switched services, voice traffic, and supported data transfer rates up to 14.4 kbits/s. Higher data rates were achieved through the deployment of “2.5G” networks, many of which were adapted to existing 2G network infrastructures. The 2.5G networks began the introduction of packet-switching technology in wireless networks. However, it is the evolution of third generation, or “3G” technology that may introduce fully packet-switched networks, which support high-speed data communications.

Standards for digital television terrestrial broadcasting (DTTB) have evolved around the world with different systems being adopted in different regions. The three leading DTTB systems are, the advanced standards technical committee (ATSC) system, the digital video broadcast terrestrial (DVB-T) system, and the integrated service digital broadcasting terrestrial (ISDB-T) system. The ATSC system has largely been adopted in North America, South America, Taiwan, and South Korea. This system adapts trellis coding and 8-level vestigial sideband (8-VSB) modulation. The DVB-T system has largely been adopted in Europe, the Middle East, Australia, as well as parts of Africa and parts of Asia. The DVB-T system adapts coded orthogonal frequency division multiplexing (COFDM). The OFDM spread spectrum technique may be utilized to distribute information over many carriers that are spaced apart at specified frequencies. The OFDM technique may also be referred to as multi-carrier or discrete multi-tone modulation. This technique may result in spectral efficiency and lower multi-path distortion, for example. The ISDB-T system has been adopted in Japan and adapts bandwidth segmented transmission orthogonal frequency division multiplexing (BST-OFDM). The various DTTB systems may differ in important aspects; some systems employ a 6 MHz channel separation, while others may employ 7 MHz or 8 MHz channel separations.

While 3G systems are evolving to provide integrated voice, multimedia, and data services to mobile user equipment, there may be compelling reasons for adapting DTTB systems for this purpose. One of the more notable reasons may be the high data rates that may be supported in DTTB systems. For example, DVB-T may support data rates of 15 Mbits/s in an 8 MHz channel in a wide area single frequency network (SFN). There are also significant challenges in deploying broadcast services to mobile user equipment. Because of form factor constraints, many handheld portable devices, for example, may require that Printed Circuit Board (PCB)area be minimized and that services consume minimum power to extend battery life to a level that may be acceptable to users. Another consideration is the Doppler Effect in moving user equipment, which may cause inter-symbol interference in received signals. Among the three major DTTB systems, ISDB-T was originally designed to support broadcast services to mobile user equipment. While DVB-T may not have been originally designed to support mobility broadcast services, a number of adaptations have been made to provide support for mobile broadcast capability. The adaptation of DVB-T to mobile broadcasting is commonly known as DVB handheld (DVB-H). The broadcasting frequencies for Europe are in UHF (bands IVIV) and in the US, the 1670-1675 MHz band that has been allocated for DVB-H operation. Additional spectrum is expected to be allocated in the L-band world-wide.

To meet requirements for mobile broadcasting the DVB-H specification supports time slicing to reduce power consumption at the user equipment, addition of a 4 k mode to enable network operators to make tradeoffs between the advantages of the 2 k mode and those of the 8 k mode, and an additional level of forward error correction on multi-protocol encapsulated data—forward error correction (MPE-FEC) to make DVB-H transmissions more robust to the challenges presented by mobile reception of signals and to potential limitations in antenna designs for handheld user equipment. DVB-H may also use the DVB-T modulation schemes, like Quadrature Phase Shift Keving (QPSK) and 16-quadrature amplitude modulation (16-QAM).

While several adaptations have been made to provide support for mobile broadcast capabilities in DVB-T, concerns regarding device size, cost, and/or power requirements still remain significant constraints for the implementation of handheld portable devices enabled for digital video broadcasting operations. For example, typical DVB-T tuners or receivers in mobile terminals may employ super-heterodyne architectures with one or two intermediate frequency (IF) stages and direct sampling of the passband signal for digital quadrature down-conversion. Moreover, external tracking and Sound Acoustic Wave (SAW) filters may generally be utilized for channel selection and image rejection. Such approaches may result in increased power consumption and high external component count, which may limit their application in handheld portable devices. As a result, the success of mobile broadcast capability of DVB-T may depend in part on the ability to develop TV tuners that have smaller form factor, are produced at lower cost, and consume less power during operation. Furthermore, process and temperature variations within conventional tuners or receivers in mobile terminals result in deviation in the characteristics of many sub-circuits of the transceiver. A very important case is the deviation of the frequency response of analog filters used within the tuners or receivers. Such deviation of the frequency response results in deterioration of channel selection capabilities of the tuners or receivers.

As mobile terminals support a wider range of content from voice to data to video, they may be required to receive a correspondingly wider range of frequencies. Consequently, filtering circuitry may be required to filter signals for correspondingly wider ranges of frequencies.

FIG. 1is diagram for a conventional filter calibration scheme utilizing a matched oscillator. This is an indirect filter calibration techniques, meaning that filter bandwidth is calibrated through the calibration of a circuit other than the filter itself (the oscillator). Referring toFIG. 1, there is shown a filter202, an oscillator204, a crystal oscillator206, a frequency divider block208, an exclusive-or (XOR) block210, and a control block212.

The oscillator204may comprise suitable logic, circuitry, and/or code that may enable generation of a clock signal. The oscillator204may comprise resistive (R) and capacitive (C) components. The R and C components may be variable or fixed. When the frequency associated with the clock signal is based on the values for the R and C components, the oscillator204may comprise an RC oscillator circuit.

The oscillator204may comprise active components, for example operational amplifier (op-amp) and C components. The op-amp component may comprise one or more electrical devices characterized by one or more transconductance (Gm) values. The C component may comprise one or more electrical devices characterized by one or more fixed or variable capacitive values. When the frequency associated with the clock signal is based on the values for the op-amp and C components, the oscillator204may comprise a GmC oscillator circuit.

The frequency divider block208may comprise suitable logic, circuitry, and/or code that may enable generation of an output signal based on an input signal, wherein the input signal is characterized by a frequency that is a multiple of the corresponding frequency of the output signal. The value of each corresponding frequency may be determined by the frequency divider block208.

The XOR block210may comprise suitable logic, circuitry, and/or code that may enable generation of an output signal in which the value of the output signal is based on a comparison of respective values associated with two input signals. The XOR block210may output a LOW value when the respective values of the two input signals are approximately equal. The XOR block210may output a HIGH value when the respective values of the two input signals are not approximately equal.

The control block212may comprise suitable logic, circuitry, and/or code that may enable generating a control signal, fControl, based on an input signal. The control signal may comprise an analog signal, such as a value for a voltage or a current for example, based on the input signal. The control signal may comprise a digital representation comprising one or more bits for example, based on the input signal. The control block212may receive an input signal from an external circuit. The control block212may generate the control signal based on the input signal. The control signal may be communicated to control at least a portion of the circuitry from which the input signal was received.

In operation, the crystal oscillator206may enable generation of a crystal (xtal) timing signal. The crystal timing signal may be characterized by a crystal frequency, fxtal. The frequency divider208may receive the crystal timing signal as an input signal. The frequency divider208may utilize a frequency division factor, fD, to generate a reference timing signal characterized by a reference frequency, fRef, and a reference phase φRef. The value of the reference frequency may be about equal to the ratio of the value of the reference frequency and the value of the frequency division factor, fRef/fD.

The oscillator204may enable generation of an oscillator timing signal characterized by an oscillator frequency, fOsc, and an oscillator phase φOsc. For an oscillator204comprising an RC oscillator, the oscillator frequency may be referred to as an RC oscillator frequency, fOsc(RC). The corresponding oscillator phase may be referred to as an RC oscillator phase, φOsc(RC). The value of the RC oscillator frequency and/or phase may be based on values for the R and C components. The values for the R and/or C components may be determined based on the control signal fControl.

The XOR block210may concurrently compare a value for the reference timing signal and a corresponding value for the oscillator timing signal at various time instants. Based on the comparison, the XOR block210may generate a difference signal. The difference signal may be nonzero when there are differences between the frequencies fRefand fOsc(RC), at a given time instant. The difference signal may be nonzero when there are differences between the phases φRefand φOsc(RC), at a given time instant.

The control block212may receive the difference signal and generate the control signal, fControl, based on the value of the difference signal. The control block212may communicate the control signal, comprising feedback information, to the oscillator204. The feedback information may cause the oscillator204to adjust the R and/or C values. As a result of the adjustment, the corresponding frequency and/or phase values, fOsc(RC)/φOsc(RC) may be adjusted.

For an oscillator204comprising an GmC oscillator, the oscillator frequency may be referred to as an GmC oscillator frequency, fOsc(GmC). The corresponding oscillator phase may be referred to as an GmC oscillator phase, φOsc(GmC). The value of the GmC oscillator frequency and/or phase may be based on values for the op-amp and C components. The values for the op-amp and/or C components may be determined based on the control signal fControl.

The difference signal generated by the XOR block210may be nonzero when there are differences between the frequencies fRefand fOsc(GmC), at a given time instant. The difference signal may be nonzero when there are differences between the phases φRefand φOsc(GmC), at a given time instant.

The control block212may receive the difference signal and generate the control signal, fControl, based on the value of the difference signal. The control block212may communicate the control signal, comprising feedback information, to the oscillator204. The feedback information may cause the oscillator204to adjust the Gmand/or C values. As a result of the adjustment, the corresponding frequency and/or phase values, fOsc(GmC)/φOsc(GmC), may be adjusted.

The oscillator204may utilize shared or common components with the filter202. For example, for an oscillator204that comprises R and C components, the filter202may comprise equivalent R and C components. When the value for the f−3 dBfilter cut-off frequency is based on the values of the R and C components, the filter202may comprise an RC filter circuit. For an oscillator204that comprises op-amp components and C components, the filter202may comprise equivalent op-amp and C components. When the value for the f—3 dBfilter cut-off frequency is based on the values of the op-amp and C components, the filter202may comprise a GmC filter circuit.

For a filter202comprising an RC filter circuit, the control signal, fControl, generated by the control block212may cause the filter202to adjust the R and/or C values for the equivalent R and/or C components. As a result of the adjustment, the corresponding value for the f−3 dBfilter cut-off frequency may be adjusted. For a filter202comprising a GmC filter circuit, the control signal, fControl, generated by the control block212may cause the filter202to adjust the Gmand/or C values for the equivalent op-amp and/or C components. As a result of the adjustment, the corresponding value for the f−3 dBfilter cut-off frequency may be adjusted.

The oscillator204may be utilized to calibrate the filter202since the control signal, fControl, is generated based on the oscillator frequency fOsc, and/or oscillator phase φOsc. The control signal may cause the filter202to compute a value for the f−3 dBfilter cut-off frequency. A disadvantage in this method is that the accuracy of the calibration may be limited based on the extent to which the values for the R and C components in the oscillator204are equal to corresponding values for the equivalent R and C components in the filter202, for a given value of the control signal fControl. The accuracy of the calibration may also be limited based on the range of values for frequency, fRef, and/or phase, φRef, which may be generated by the frequency divider block208.

BRIEF SUMMARY OF THE INVENTION

A system and/or method is provided for filter calibration using fractional-N frequency synthesized signals, substantially as shown in and/or described in connection with at least one of the figures, as set forth more completely in the claims.

DETAILED DESCRIPTION OF THE INVENTION

Certain aspects of the invention provide a method and system for filter calibration using fractional-N frequency synthesized signals. Aspects of the method may comprise generating a LO signal by a PLL circuit within a chip. A reference signal may be generated based on the generated LO signal and a synthesizer control signal. The method may further comprise calibrating a frequency response for a filter circuit integrated within the chip by adjusting parameters associated with the filter circuit based on the generated reference signal. Aspects of the system may include a single-chip multi-band RF receiver that enables generation of a LO signal by a PLL circuit within the single-chip. A reference signal may be generated based on the generated LO signal and a synthesizer control signal. The single-chip multi-band RF receiver may enable calibration of a frequency response for a filter circuit integrated within the chip. The frequency response may be calibrated by adjusting the filter based on the generated reference signal.

Various embodiments of the invention may comprise a scheme for calibrating a filter in a communication receiver without requiring additional circuitry. In such embodiments, a Σ-Δ fractional-N synthesizer may be utilized for synthesizing RF signals. The Σ-Δ fractional-N synthesizer may enable the generation of a wide range of reference signal frequencies. In addition, the Σ-Δ fractional-N synthesizer may enable more accurate generation of a specified filter cutoff frequency f−3 dBthan may be the case with many conventional filter calibration schemes. Various embodiments of the invention may utilize a digital frequency synthesizer to enable even greater accuracy in the generation of a specific frequency f−3 dB.

FIG. 2Ais a block diagram illustrating an exemplary mobile terminal, in accordance with an embodiment of the invention. Referring toFIG. 2A, there is shown a mobile terminal120that may comprise an RF receiver123a,an RF transmitter123b,a digital baseband processor129, a processor125, and a memory127. A receive antenna121amay be communicatively coupled to the RF receiver123a.A transmit antenna121bmay be communicatively coupled to the RF transmitter123b.The mobile terminal120may be operated in a system, such as the cellular network and/or digital video broadcast network described inFIG. 2A, for example.

The RF receiver123amay comprise suitable logic, circuitry, and/or code that may enable processing of received RF signals. The RF receiver123amay enable receiving RF signals in a plurality of frequency bands. For example, the RF receiver123amay enable receiving DVB-H transmission signals via the VHF band, from about 174 MHz to about 240 MHz, the UHF band, from about 470 MHz to about 890 MHz, the 1670-1675 MHz band, and/or the L-band, from about 1400 MHz to about 1700 MHz, for example. Moreover, the RF receiver123amay enable receiving signals in cellular frequency bands, for example. Each frequency band supported by the RF receiver123amay have a corresponding front-end circuit for handling low noise amplification and down conversion operations, for example. In this regard, the RF receiver123amay be referred to as a multi-band receiver when it supports more than one frequency band. In another embodiment of the invention, the mobile terminal120may comprise more than one RF receiver123a,wherein each of the RF receivers123amay be a single-band or a multi-band receiver.

The RF receiver123amay quadrature down convert the received RF signal to a baseband frequency signal that comprises an in-phase (I) component and a quadrature (Q) component. The RF receiver123amay perform direct down conversion of the received RF signal to a baseband frequency signal, for example. In some instances, the RF receiver123amay enable analog-to-digital conversion of the baseband signal components before transferring the components to the digital baseband processor129. In other instances, the RF receiver123amay transfer the baseband signal components in analog form.

The digital baseband processor129may comprise suitable logic, circuitry, and/or code that may enable processing and/or handling of baseband frequency signals. In this regard, the digital baseband processor129may process or handle signals received from the RF receiver123aand/or signals to be transferred to the RF transmitter123b,when the RF transmitter123bis present, for transmission to the network. The digital baseband processor129may also provide control and/or feedback information to the RF receiver123aand to the RF transmitter123bbased on information from the processed signals. The digital baseband processor129may communicate information and/or data from the processed signals to the processor125and/or to the memory127. Moreover, the digital baseband processor129may receive information from the processor125and/or to the memory127, which may be processed and transferred to the RF transmitter123bfor transmission to the network.

The RF transmitter123bmay comprise suitable logic, circuitry, and/or code that may enable processing of RF signals for transmission. The RF transmitter123bmay enable transmission of RF signals in a plurality of frequency bands. Moreover, the RF transmitter123bmay enable transmitting signals in cellular frequency bands, for example. Each frequency band supported by the RF transmitter123bmay have a corresponding front-end circuit for handling amplification and up conversion operations, for example. In this regard, the RF transmitter123bmay be referred to as a multi-band transmitter when it supports more than one frequency band. In another embodiment of the invention, the mobile terminal120may comprise more than one RF transmitter123b,wherein each of the RF transmitters123bmay be a single-band or a multi-band transmitter.

The RF transmitter123bmay quadrature up convert the baseband frequency signal comprising I/Q components to an RF signal. The RF transmitter123bmay perform direct up conversion of the baseband frequency signal to a baseband frequency signal, for example. In some instances, the RF transmitter123bmay enable digital-to-analog conversion of the baseband signal components received from the digital baseband processor129before up conversion. In other instances, the RF transmitter123bmay receive baseband signal components in analog form.

The processor125may comprise suitable logic, circuitry, and/or code that may enable control and/or data processing operations for the mobile terminal120. The processor125may be utilized to control at least a portion of the RF receiver123a,the RF transmitter123b,the digital baseband processor129, and/or the memory127. In this regard, the processor125may generate at least one signal for controlling operations within the mobile terminal120. The processor125may also enable executing of applications that may be utilized by the mobile terminal120. For example, the processor125may execute applications that may enable displaying and/or interacting with content received via DVB-H transmission signals in the mobile terminal120.

The memory127may comprise suitable logic, circuitry, and/or code that may enable storage of data and/or other information utilized by the mobile terminal120. For example, the memory127may be utilized for storing processed data generated by the digital baseband processor129and/or the processor125. The memory127may also be utilized to store information, such as configuration information, that may be utilized to control the operation of at least one block in the mobile terminal120. For example, the memory127may comprise information necessary to configure the RF receiver123ato enable receiving DVB-H transmission in the appropriate frequency band.

FIG. 2Bis a block diagram illustrating exemplary communication between a multi-band RF receiver and a digital baseband processor in a mobile terminal, in accordance with an embodiment of the invention. Referring toFIG. 2B, there is shown a multi-band RF receiver130, an analog-to-digital converter (ADC)134, and a digital baseband processor132. The multi-band RF receiver130may comprise a UHF front-end131a,an L-band front-end131b,a VHF front-end131c,a baseband block133a,a received signal strength indicator (RSSI) block133b,and a synthesizer133c.The multi-band RF receiver130, the analog-to-digital converter (ADC)134, and/or the digital baseband processor132may be part of a mobile terminal, such as the mobile terminal120inFIG. 2A, for example.

The multi-band RF receiver130may comprise suitable logic, circuitry, and/or code that may enable handling of VHF, UHF and L-band signals. The multi-band RF receiver130may be enabled via an enable signal, such as the signal RxEN139a,for example. In this regard, enabling the multi-band RF receiver130via the signal RxEN139aby a 1:10 ON/OFF ratio may allow time slicing in DVB-H while reducing power consumption. At least a portion of the circuitry within the multi-band RF receiver130may be controlled via the control interface139b.The control interface139bmay receive information from, for example, a processor, such as the processor125inFIG. 2A, or from the digital baseband processor132. The control interface139bmay comprise more than one bit. For example, when implemented as a 2-bit interface, the control interface139amay be an inter-integrated circuit (I2C) interface.

The VHF front-end131cmay comprise suitable logic, circuitry, and/or code that may enable low noise amplification and direct down conversion of VHF signals. In this regard, the VHF front-end131cmay utilize an integrated low noise amplifier (LNA) and mixers, such as passive mixers, for example. The VHF front-end131cmay communicate the resulting baseband frequency signals to the baseband block133afor further processing.

The UHF front-end131amay comprise suitable logic, circuitry, and/or code that may enable low noise amplification and direct down conversion of UHF signals. In this regard, the UHF front-end131amay utilize an integrated low noise amplifier (LNA) and mixers, such as passive mixers, for example. The UHF front-end131amay communicate the resulting baseband frequency signals to the baseband block133afor further processing.

The L-band front-end131bmay comprise suitable logic, circuitry, and/or code that may enable low noise amplification and direct down conversion of L-band signals. In this regard, the L-band front-end131bmay utilize an integrated LNA and mixers, such as passive mixers, for example. The L-band front-end131bmay communicate the resulting baseband frequency signals to the baseband block133afor further processing. The multi-band RF receiver130may enable one of the VHF front-end131c,the UHF front-end131aand the L-band front-end131bbased on current communication conditions.

The synthesizer133cmay comprise suitable logic, circuitry, and/or code that may enable generating the appropriate local oscillator (LO) signal for performing direct down conversion in either the VHF front-end131c,the UHF front-end131aor the L-band front-end131b.Since the synthesizer133cmay enable fractional division of a source frequency when generating the LO signal, a large range of crystal oscillators may be utilized as a frequency source for the synthesizer133c.This approach may enable the use of an existing crystal oscillator in a mobile terminal PCB, thus reducing the number of external components necessary to support the operations of the multi-band RF receiver130, for example. The synthesizer133cmay generate a common LO signal for the VHF front-end131c,the UHF front-end131aand for the L-band front-end131b.In this regard, the VHF front-end131c,the UHF front-end131aand the L-band front-end131bmay enable dividing the LO signal in order to generate the appropriate signal to perform down conversion from the VHF band, from the UHF band and from the L-band respectively. In some instances, the synthesizer133cmay have at least one integrated voltage controlled oscillator (VCO) for generating the LO signal. In other instances, the VCO may be implemented outside the synthesizer133c.

The baseband block133amay comprise suitable logic, circuitry, and/or code that may enable processing of I/Q components generated from the direct down conversion operations in the VHF front-end131c,the UHF front-end131aand the L-band front-end131b.The baseband block133amay enable amplification and/or filtering of the I/Q components in analog form. The baseband block133amay communicate the processed I component, that is, signal135a,and the processed Q component, that is, signal135c,to the ADC134for digital conversion.

The RSSI block133bmay comprise suitable logic, circuitry, and/or code that may enable measuring the strength, that is, the RSSI value, of a received RF signal, whether VHF, UHF or L-band signal. The RSSI measurement may be performed, for example, after the received RF signal is amplified in either the VHF front-end131c,the UHF front-end131aor the L-band front-end131b.The RSSI block133bmay communicate the analog RSSI measurement that is, signal135e,to the ADC134for digital conversion.

The ADC134may comprise suitable logic, circuitry, and/or code that may enable digital conversion of signals135a,135c,and/or135eto signals135b,135d,and/or135frespectively. In some instances, the ADC134may be integrated into the multi-band RF receiver130or into the digital baseband processor132.

The digital baseband processor132may comprise suitable logic, circuitry, and/or code that may enable processing and/or handling of baseband frequency signals. In this regard, the digital baseband processor132may be the same or substantially similar to the digital baseband processor129described inFIG. 2A. The digital baseband processor132may enable generating at least one signal, such as the signals AGC_BB137aand AGC_RF137b,for adjusting the operations of the multi-band RF receiver130. For example, the signal AGC_BB137amay be utilized to adjust the gain provided by the baseband block133aon the baseband frequency signals generated from either the VHF front-end131c,the UHF front-end131aor the L-band front-end131b.In another example, the signal AGC_RF137bmay be utilized to adjust the gain provided by an integrated LNA in either the VHF front-end131c,the UHF front-end131aor the L-band front-end131b.In another example, the digital baseband processor132may generate at least one control signal or control information communicated to the multi-band RF receiver130via the control interface139bfor adjusting operations within the multi-band RF receiver130.

FIG. 2Cis a block diagram illustrating an exemplary single-chip multi-band RF receiver with an integrated LNA in each front-end, in accordance with an embodiment of the invention. Referring toFIG. 2C, there is shown a single-chip multi-band RF receiver140athat may comprise a VHF front-end148c,a UHF front-end148a,an L-band front-end148b,a baseband block164, a digital frequency synthesizer188, a logarithmic amplifier (logarithmic amplifier)172, a Σ-Δ fractional-N synthesizer174, a VCO block176, a digital interface160, an ADC162, an oscillator180, and a buffer182.

The single-chip multi-band RF receiver140amay be fabricated using any of a plurality of semiconductor manufacturing processes, for example, complimentary metal-oxide-semiconductor (CMOS) processes, bipolar CMOS (BiCMOS), or Silicon Germanium (SiGe). The single-chip multi-band RF receiver140amay be implemented using differential structures to minimize noise effects and/or substrate coupling, for example. The single-chip multi-band RF receiver140amay utilize low drop out (LDO) voltage regulators to regulate and clean up on-chip voltage supplies. In this regard, the LDO voltage regulators may be utilized to transform external voltage sources to the appropriate on-chip voltages.

When the single-chip multi-band RF receiver140ais implemented utilizing a CMOS process, some design considerations may include achieving low noise figure (NF) values, wide-band operation, high signal-to-noise ration (SNR), performing DC offset removal, achieving high input second-order and third-order intercept points (IIP2 and IIP3), and/or reducing I/Q mismatch, for example.

The single-chip multi-band RF receiver140amay receive UHF signals via a first antenna142a,a UHF filter144a,and a first balum146a.The UHF filter144aenables band pass filtering, wherein the band pass may be about 470 to about 702 MHz for cellular signals, for example, or about 470 to about 862 MHz, for other types of received signals, for example. The balum146aenables balancing the filtered signals before being communicated to the UHF front-end148a.

The single-chip multi-band RF receiver140amay receive L-band signals via a second antenna142b,an L-band filter144b,and a second balum146b.The L-band filter144benables band pass filtering, wherein the band pass may be about 1670 to about 1675 MHz for signals in US systems, for example, or about 1450 to about 1490 MHz, for signals in European systems, for example. The balum146benables balancing the filtered signals before being communicated to the L-band front-end148a.In some instances, antennas142aand142bmay be implemented utilizing a single antenna communicatively coupled to the single-chip multi-band RF receiver140athat may support receiving radio signals operating in the UHF IV/V and/or L-band, for example.

The single-chip multi-band RF receiver140amay receive VHF signals via a third antenna142c,a VHF filter144c,and a third balum146c.The VHF filter144cenables band pass filtering, wherein the band pass may be about 174 to about 240 MHz, for example. The balum146cenables balancing the filtered signals before being communicated to the VHF front-end148c.

The UHF front-end148amay comprise a variable low noise amplifier (LNA)150a,a mixer152a,a mixer154a,and a LO signal divider156. The variable LNA150amay comprise suitable logic and/or circuitry that may enable amplification of the UHF signals received. Matching between the output of the balum146aand the input of the variable LNA150amay be achieved by utilizing off-chip series inductors, for example. The variable LNA150amay implement continuous gain control by current steering that may be controlled by a replica scheme within the variable LNA150a.The gain of the variable LNA150amay be adjusted via the signal AGC_RF137b,for example.

The mixers152aand154amay comprise suitable logic and/or circuitry that may enable generating in-phase (I) and quadrature (Q) components of the baseband frequency signal based on direct down conversion of the amplified received UHF signal with the quadrature signals186I and186Q generated by the divider block156. The mixers152aand154amay be passive mixers in order to achieve high linearity and/or low flicker noise, for example. The LO signal divider156may comprise suitable logic, circuitry, and/or code that may enable dividing of the LO signal186by a factor of 2 (:/2) or a factor of 3 (:/3) and at the same time provide quadrature outputs186I and186Q, wherein186I and186Q have 90 degrees separation between them. The factor of 3 division may be used when the received UHF signal band is about 470 to about 600 MHz, for example. The factor of 2 division may be used when the received UHF signal band is about 600 to about 900 MHz, for example. The I/Q components generated by the mixers152aand154amay be communicated to the baseband block164.

The L-band front-end148bmay comprise a variable LNA150b, a mixer152b6, a mixer154b, and a LO signal generator158. The variable LNA150bmay comprise suitable logic and/or circuitry that may enable amplification of the L-band signals received. Matching between the output of the balum146band the input of the variable LNA150bmay be achieved by utilizing off-chip series inductors, for example. The variable LNA150bmay implement continuous gain control by current steering that may be controlled by a replica scheme within the variable LNA150b. The gain of the variable LNA150bmay be adjusted via the signal AGC_RF137b, for example.

The mixers152band154bmay comprise suitable logic and/or circuitry that may enable generating I/Q components of the baseband frequency signal based on the direct down conversion of the amplified received L-band signal with the LO signals158I and158Q generated by the LO generator block158. The mixers152band154bmay be passive mixers in order to achieve high linearity and/or low flicker noise, for example. The LO signal generator158may comprise suitable logic, circuitry, and/or code that may enable generation of quadrature LO signals158I and158Q, that is, signals with 90 degree phase split between them, from the LO signal186. The I/Q components generated by the mixers152band154bmay be communicated to the baseband block164.

The VHF front-end148cmay comprise a variable low noise amplifier (LNA)150c,a mixer152c,a mixer154c,and a LO signal divider157. The variable LNA150cmay comprise suitable logic and/or circuitry that may enable amplification of the VHF signals received. Matching between the output of the balum146cand the input of the variable LNA150cmay be achieved by utilizing off-chip series inductors, for example. The variable LNA150cmay implement continuous gain control by current steering that may be controlled by a replica scheme within the variable LNA150c.The gain of the variable LNA150cmay be adjusted via the signal AGC_RF137b,for example.

The mixers152cand154cmay comprise suitable logic and/or circuitry that may enable generating in-phase (I) and quadrature (Q) components of the baseband frequency signal based on direct down conversion of the amplified received VHF signal with the quadrature signals187I and187Q generated by the divider block157. The mixers152cand154cmay be passive mixers in order to achieve high linearity and/or low flicker noise, for example. The LO signal divider157may comprise suitable logic, circuitry, and/or code that may enable dividing of the LO signal186by a factor of 6 (:/6) or a factor of 8 (:/8) and at the same time provide quadrature outputs187I and187Q, wherein187I and187Q have 90 degrees separation between them. The I/Q components generated by the mixers152cand154cmay be communicated to the baseband block164.

The digital frequency synthesizer188may comprise suitable logic, circuitry, and/or code that may enable generation of a reference signal based on a clock timing signal, and on a control input signal. In various embodiments of the invention, the digital frequency synthesizer188may implement a look up table (LUT) function wherein a given clock timing signal and control input signal combination may correspond to a frequency, phase, and/or magnitude for a generated reference signal. Data utilized for the LUT function may be stored and/or retrieved from the memory127(FIG. 2A), for example. In other embodiments of the invention, the digital frequency synthesizer188may comprise an over-sampling digital to analog conversion (DAC) function in which the digital frequency synthesizer188performs digital sampling of the clock timing signal. A rate of digital sampling may be determined based on the control input signal.

The logarithmic amplifier172may comprise suitable logic, circuitry, and/or code that may enable generation of a wideband, received signal strength indicator (RSSI) signal, such as the signal135e,based on the output of the variable LNA150a.The RSSI signal indicates the total amount of signal power that is present at the output of the LNA, for example. The RSSI signal may be utilized by, for example, the digital baseband processor132inFIG. 2C, to adjust the gain of the variable LNA150ain the presence of RF interference to achieve NF and/or linearity performance that meets blocking and/or intermodulation specifications, for example. In this regard, interference may refer to blocker signals, for example. Blocker signals may be unwanted signals in frequency channels outside the wanted or desired channel that may disturb the reception of the wanted signals. This effect may be a result of blockers generating large signals within the receiver path. These large signals may introduce harmonics, intermodulation products, and/or unwanted mixing products that crosstalk with the wanted signals. In another embodiment of the invention, the logarithmic amplifier172may enable generating a wideband, RSSI signal, such as the signal135e,based on the output of the variable LNA150b.In this instance, the RSSI signal may be utilized by to adjust the gain of the variable LNA150b.

The baseband block164may comprise an in-phase component processing path and a quadrature component processing path. The in-phase processing path may comprise at least one programmable gain amplifier (PGA)166a,a baseband filter168a,and at least one PGA170a.The quadrature component processing path may comprise at least one PGA166b,a baseband filter168b,and at least one PGA170b.The PGAs166a,166b,170a,and170bmay comprise suitable logic, circuitry, and/or code that may enable amplification of the down converted components of the baseband frequency signal generated by the RF front-end. The gain of the PGAs166a,166b,170a,and170bmay be digitally programmable. In addition, at the output of the PGAs166aand166b,a programmable pole may be utilized to reduce linearity requirements for the baseband filters168aand168brespectively. Since the static and time-varying DC offset may saturate the operation of the single-chip multi-band RF receiver140a,the PGAs166a,166b,170a,and170bmay utilize DC servo loops to address DC offset issues. The gain of the PGAs166a,166b,170a,and/or170bmay be controlled via the AGC_BB signal137a,for example. In this regard, the ADC162may be utilized to provide digital control of the PGAs166a,166b,170a,and/or170bwhen the AGC_BB signal137ais an analog signal.

The baseband filters168aand168bmay comprise suitable logic, circuitry, and/or code that may enable channel selection, for example. Channel selection may be performed by filters, such as an Nthorder lowpass Chebyschev filter implemented by opamp-RC active integrators in a leapfrog configuration, for example. For the correct tuning of the characteristics of the filters, an on-chip auto-calibration loop may be activated upon power-up. The auto-calibration loop may set up the cut-off frequency, f−3 dBto the correct vale required to meet the requirements of the communications standard for which the receiver is designed. For example, in DVB-T/DVB-H, the value f−3 dBof the filter cut-off frequency may be set to a value from 2 to 5 MHz thus supporting the different channel bandwidths of 5-8 MHz specified by DVB-T/DVB-H standards. During auto-calibration, a tone at the appropriate f−3 dBmay be generated by the digital frequency synthesizer188and may be applied at the input of the baseband filters168aand168bfor comparison with the filter output of a root-mean-squared (RMS) detector. A digitally controlled loop may be utilized to adjust the baseband filter bandwidth until the output of the baseband filter and the RMS detector are the same.

The Σ-Δ fractional-N synthesizer174may comprise suitable logic, circuitry, and/or code that may enable LO generation that may be independent of the reference crystal frequency, such as the crystal178, for example. In this regard, the synthesizer174may generate a signal, such as the signal190, for example, to control the operation of the VCO block176and therefore the generation of the LO signal186. Since the synthesizer174may enable fractional synthesis, the single-chip multi band RF receiver140amay utilize the same crystal utilized by other operations in the mobile terminal while maintaining fine tuning capability. The synthesizer174may receive a reference frequency signal from the crystal178via an oscillator180, for example. The output of the oscillator180may also be buffered by the buffer182to generate a clock signal184, for example.

The VCO block176may comprise suitable logic, circuitry, and/or code that may enable generating the LO signal186utilized by the VHF front-end148c,the UHF front-end148aand the L-band front-end148bfor direct down conversion of the received RF signals. The VCO block176may comprise at least one VCO, wherein each VCO may have cross-coupled NMOS and PMOS devices and metal-oxide-semiconductor (MOS) varactors in an accumulation mode for tuning. In this regard, a switched varactor bank may be utilized for providing coarse tuning. The VCO block176may provide a range of about 1.2 to about 1.8 GHz when implemented utilizing two VCOs, for example. When more than one VCO is utilized in implementing the VCO block176, selecting the proper VCO for generating the LO signal186may be based on the type of RF signal being received by the single-chip multi band RF receiver140a.

The digital interface160may comprise suitable logic, circuitry, and/or code that may enable controlling circuitry within the single-chip multi band RF receiver140a.The digital interface160may comprise a plurality of registers for storing control and/or operational information for use by the single-chip multi-band RF receiver140a.The digital interface160may enable receiving the signal RxEN139athat may be utilized to perform 1:10 ON/OFF ratio time slicing in DVB-H while reducing power consumption. Moreover, the digital interface160may enable receiving the control interface139bfrom, for example, a processor, such as the processor125inFIG. 2A, or from the digital baseband processor132inFIG. 2C. The control interface139bmay comprise more than one bit. The control interface139bmay be utilized to control the synthesis operations of the synthesizer174and/or the filtering operations of the baseband filters168aand168b.The control interface139bmay also be utilized to adjust the bias of circuits within the single-chip multi-band RF receiver140a,such as those of the variable LNAs150aand150b,the PGAs166a,166b,170a,and170b,and/or the baseband filters168aand168b,for example.

FIG. 2Dis a diagram for an exemplary direct filter calibration scheme utilizing filtering, which may be utilized in connection with an embodiment of the invention. Referring toFIG. 2D, there is shown a crystal oscillator206, a frequency divider block208, a filtering block222, a filter block224, and a control block226. The crystal oscillator block206may substantially comprise the functions of the crystal178, and the oscillator180(FIG. 2C). The frequency divider block208may be substantially as described inFIG. 1. The control block226may be substantially as described for the control block212inFIG. 1. The filter block224may substantially comprise the functions of the baseband filter168a.When the value for the f−3 dBfilter cut-off frequency is based on the values of R and C components, the filter224may comprise an opamp-RC filter circuit. For the opamp-RC filter circuit, the f−3 dBfilter cut-off frequency may be referred to as a f−3 dB(RC) filter cut-off frequency. When the value for the f−3 dBfilter cut-off frequency is based on the values of transconductors and C components, the filter224may comprise a GmC filter circuit. For the RC filter circuit, the f−3 dBfilter cut-off frequency may be referred to as a f−3 dB(GmC) filter cut-off frequency.

The filtering block222may comprise suitable logic, circuitry, and/or code that may enable generation of an output signal by removing harmonic frequency components from a received input signal. The function of the filtering block222may be practiced by implementations comprising a low pass filter, a high pass filter, and/or a band pass filter.

In operation, the crystal oscillator206may enable generation of a crystal (xtal) timing signal. The crystal timing signal may be characterized by a crystal frequency, fXtal. The frequency divider208may receive the crystal timing signal as an input signal. The frequency divider208may utilize a frequency division factor, fD, to generate a reference timing signal characterized by a reference frequency, fRef. The value of the reference frequency may be approximately equal to the ratio of the value of the reference frequency and the value of the frequency division factor, fRef/fD.

The filtering block222may enable generation of a filtered reference timing signal based on the reference timing signal. The filtered reference timing signal may also be characterized by the reference frequency. The filtering block222may generate the filtered reference timing signal may attenuating frequency components in the reference timing signal, which are characterized by harmonic frequencies of the reference frequency.

For a filter block224comprising an opamp-RC filter circuit, the control signal, fControl, generated by the control block226may cause the filter block224to adjust the R and/or C values for the R and/or C components. As a result of the adjustment, the corresponding value for the f−3 dB(RC) filter cut-off frequency may be adjusted. The filter block224may generate a filter calibration signal by filtering the filtered reference timing signal. The filter block224may perform the filtering function by attenuating certain frequency components in the filtered reference timing signal based on the f−3 dB(RC) filter cut-off frequency. The filtering function performed by the filter block224may modify an amplitude parameter and/or phase parameter, which characterizes at least a portion of the frequency components contained within the filtered reference timing signal.

For a filter block224comprising an GmC filter circuit, the control signal, fControl, generated by the control block226may cause the filter block224to adjust the Gmand/or C values for the transconductor and/or C components. As a result of the adjustment, the corresponding value for the f−3 dB(GmC) filter cut-off frequency may be adjusted. The filter block224may generate a filter calibration signal by filtering the filtered reference timing signal. The filter block224may perform the filtering function by attenuating frequency components in the filtered reference timing signal based on the f−3 dB(GmC) filter cut-off frequency. The filtering function performed by the filter block224may modify an amplitude parameter and/or phase parameter, which characterizes at least a portion of the frequency components contained within the filtered reference timing signal.

The control block226may compare values of the amplitude parameters and/or phase parameters, which characterize the corresponding frequency components in the filter calibration signal received from the filter block224. The values of the amplitude parameters and/or phase parameters may be compared with expected values for the amplitude and/or phase parameters for the corresponding frequency components. The control block may generate a control signal, fControl, based on the comparison.

The component value mismatch problem may be avoided in comparison to the system illustrated inFIG. 1since the control signal, fControl, is generated based on the filter calibration signal generated by the filter block224. This calibration method is direct as opposed to the indirect method inFIG. 1. As with the system illustrated inFIG. 1, a disadvantage in this method is that that the accuracy of the calibration may also be limited based on the range of values for frequency, fRef, and/or phase, φRef, which may be generated by the frequency divider block208. In addition, embodiments of the system illustrated inFIG. 2Dmay require additional circuitry to implement the filtering block222.

FIG. 3Ais a block diagram of an exemplary analog baseband processing system supporting auto-calibration, in accordance with an embodiment of the invention. Referring toFIG. 3A, the baseband processing block300amay comprise a plurality of programmable gain amplifiers (PGAs)304a,308a,310a,and314a,and baseband filters306aand312a.

For example, the baseband processing block300amay comprise an in-phase (I) component processing path comprising PGAs304aand308a,and a baseband filter306a.The in-phase component processing path of the baseband processing block300amay process an input in-phase (I) signal316ato generate an output in-phase signal318a.The input in-phase signal316amay comprise a down converted component of a baseband frequency signal generated by an RF front end, for example. The baseband processing block300amay also comprise a quadrature component (Q) processing path comprising PGAs310aand314a,and a baseband filter312a.The quadrature component processing path of the baseband processing block300amay process an input quadrature (Q) signal320ato generate an output quadrature signal322a.The input quadrature signal320amay comprise a down converted component of a baseband frequency signal generated by an RF front end, for example.

The PGAs304a,308a,310a,and314amay comprise suitable logic, circuitry, and/or code that may enable amplification of the down converted components of the baseband frequency signals316aand320a.The PGAs304a,308a,310a,and314amay be digitally programmable. For example, at the output of the PGAs304aand310a,a programmable pole may be utilized to reduce linearity requirements for the baseband filters306aand312a,respectively. Furthermore, the PGAs304a,308a,310a,and314amay utilize DC servo loops to address DC offset issues. The baseband filters306aand312amay comprise suitable logic, circuitry, gain and/or code that may enable channel selection, for example. Channel selection may be performed by a filter bank, such as an Nth order Chebyschev filter implemented by active integrators, for example.

FIG. 3Bis a schematic diagram of an exemplary opamp-RC baseband filter that may be used in accordance with an embodiment of the invention. Referring toFIG. 3B, the baseband filter300bmay comprise a sixth order Chebyschev filter, for example. The Chebyschev filter300bmay comprise a plurality of operational amplifiers (opamps) a1, . . . , a6, a plurality of variable capacitors c1, . . . , c6, and a plurality of resistors r1, . . . , r14. In one embodiment of the invention, the opamp-RC integrators a1-c1-r1and a6-c6-r8may be arranged in a leapfrog formation. Each of the capacitors c1, . . . , c6may be implemented as a binary weighted array of capacitors that may be controlled by 6 bits, for example.

In operation, the cut-off frequency f−3 dBof the Chebyschev filter300bmay be changed during channel selection. For example, the cut-off frequency f−3 dBof the Chebyschev filter300bmay be set to a value from 2 MHz, for example, thereby supporting channel bandwidth of about 5 MHz to about 8 MHz, which is specified by the DVB-T standard. Even though the baseband filter300bcomprises a sixth order Chebyschev filter, the present invention may not be so limited and an Nth order low-pass filter (LPF) may be utilized instead.

Even though the baseband filter300bis described as a Chebyschev filter, the present invention may not be so limited. Other types of filters may also be utilized, such as Butterworth, Elliptic etc., for example. Furthermore, even though operational amplifier RC integrators are utilized within the filter300b,the present invention may not be so limited and other integrator implementations may also be utilized, such as a Gm-C integrator. Additionally, topologies other than the leapfrog formation may be utilized, such as cascaded biquads.

FIG. 3Cis a block diagram of an exemplary baseband processing system using opamp-RC filters and an auto-calibration loop, in accordance with an embodiment of the invention. Referring toFIG. 3C, the baseband processing block300cmay comprise a plurality of programmable gain amplifiers (PGAs)302c,304c,318c,and320c,and baseband filters310cand312c.In addition, the baseband processing block may comprise an auto-calibration loop circuitry. The auto-calibration loop circuitry may comprise switches306c,314c,308c,and316c,a digital frequency synthesizer188, a Σ-Δ fractional-N synthesizer174, a crystal178, an oscillator180, an amplifier324c,root-means-square (rms) blocks326cand328c,a comparator330c,and control logic block334c.The digital frequency synthesizer188, Σ-Δ fractional-N synthesizer174, crystal178, and oscillator180may be substantially as described inFIG. 2C.

Even though rms blocks are used within the baseband processing block300c,the present invention may not be so limited and peak detectors may be used instead of the rms blocks.

The functionality of the PGAs302c,318c,304c,and320cmay be similar to the functionality of the PGAs304a,308a,310a,and314ainFIG. 3A, respectively. Similarly, the functionality of the baseband filters310cand312cmay be the same as the functionality of the baseband filters306aand312ainFIG. 3A, respectively. For example, the baseband filters310cand312cmay each comprise a sixth order Chebyschev filters, such as the Chebyschev filter311cor the Chebyschev filter300binFIG. 3B.

During an exemplary auto-calibration of the quadrature-phase signal path, the switch308cmay communicatively couple the output from the digital frequency synthesizer188to the input for the baseband filter312c.The switch316cmay communicatively couple the output from the baseband filter312cto the input for the rms block326c.The digital frequency synthesizer188may generate a reference frequency signal f−3 dB. The reference frequency signal may then be applied at the input of the baseband filter312cand the amplifier324c.The amplifier324cmay attenuate the reference frequency signal by 3 dB, for example. The attenuated frequency signal may then be communicated to the rms block328c.After the baseband filter312cfilters the reference frequency signal communicated from the digital frequency synthesizer188, the filtered reference frequency signal may be communicated to the rms block326c.A corresponding exemplary auto-calibration may be performed for the in-phase signal path.

Even though the digital frequency synthesizer188generates a reference frequency signal f−3 dBthat corresponds to the frequency where the filter attenuates by 3 dB the present invention may not be so limited. In this regard, digital frequency synthesizer188may generate a reference frequency signal f−x dBthat corresponds to the frequency of a main signal attenuated from the filter by x dB in accordance with the expected frequency response of the baseband filters310cand312c.In such instances, the amplifier324cmay correspondingly attenuate the signal generated by the digital frequency synthesizer188.

While the digital frequency synthesizer188may receive an input signal from the Σ-Δ fractional-N synthesizer174in the exemplary system ofFIG. 3C, various embodiments of the invention may not be so limited. In various embodiments of the invention, the digital frequency synthesizer188may receive an LO signal from the phase locked loop (PLL) present in a communication receiver. In one aspect of the invention, a scheme for calibrating a filter in a communication receiver without requiring additional circuitry may be provided. In various embodiments of the invention, the Σ-Δ fractional-N synthesizer174may be utilized to enable the generation of a wide range of reference signal frequencies. In addition, the Σ-Δ fractional-N synthesizer174may enable more accurate generation of a specified frequency f−3 dBthan may be the case with many conventional filter calibration schemes. In another embodiment of the invention, a digital frequency synthesizer188may provide even greater accuracy in the generation of a specific frequency f−3 dB.

The rms blocks326cand328cmay perform an averaging function, for example, on the filtered reference frequency signal and the attenuated reference frequency signal, respectively. The averaged filtered reference frequency signal and the attenuated reference frequency signal may be compared by the comparator330c.A comparator output signal may be communicated from the comparator330cto the control logic block334c.The control logic block334cmay comprise suitable circuitry, logic, and/or code and may enable generation of a filter control signal336cand/or synthesizer control signal338c.The control logic block334cmay use a clock signal332cduring control signal generation. In one exemplary embodiment of the invention, if a sixth order Chebyschev filter is used within the baseband processing block300c,the filter control signal336cmay comprise a 6-bit signal. In this regard, six bits may be used to program or adjust the capacitance of each variable capacitor c1, . . . , c6in the filter311c.

The filter control signal336cmay be communicated to each of the baseband filters310c,312c.The baseband filters310cand312cmay adjust capacitance of the variable capacitors within the filters and, thereby, change the cut-off frequency that determines filter bandwidth. The cut-off frequency and filter bandwidth of the filters310cand312cmay be adjusted until attenuation of the reference frequency signal by the filter312cequals 3 dB, for example. The synthesizer control signal338cmay be communicated to the digital frequency synthesizer from the control logic block334c.The synthesizer control signal338cmay be utilized by the digital frequency synthesizer188to generate a reference frequency signal based on a received LO signal.

Even though an auto-calibration loop is described with respect to the quadrature signal path of the baseband processing block300c,the same auto-calibration loop circuitry, such as the digital frequency synthesizer188, amplifier324c,rms blocks326cand328c,comparator330cand control logic block334c,may be used with regard to the in-phase signal path of the baseband processing block300c.

In one embodiment of the invention, for DVB-T applications, for example, an on-chip auto-calibration loop may be activated within the baseband processing block300cupon power-up. The auto-calibration loop may adjust the cut-off frequency f−3 dBof the filter response of baseband filters310cand312cto a value from about 2 MHz to about 5 MHz, for example. In this regard, the baseband processing block300cmay support a plurality of channel bandwidths of 4-10 MHz, such as bandwidths specified by the DVB-T standard. A similar principle may apply to a plurality of channel bandwidths required by a specific communication standard. The auto-calibration loop may be utilized to enable adjustment of the filter cut-off frequency to a selected value as required, given that proper component value ranges have been provided in the design of the system. For example, the filter cut-off frequency may be adjusted to 210 kHz as required by the ISDB-T standard.

FIG. 4is a flow diagram illustrating exemplary steps in a filter calibration scheme using fractional-N frequency synthesized signals, in accordance with an embodiment of the invention. Referring toFIG. 4, in step402a reference frequency at which to characterize a baseband filter312cmay be determined. The reference frequency may correspond to an expected f−3 dBcutoff frequency for the baseband filter312c.In step404, a local oscillator (LO) signal and synthesizer control signal338cmay be generated. In various embodiments of the invention, the LO signal may be generated by a Σ-Δ fractional-N synthesizer174, and the synthesizer control signal338cmay be generated by the control logic block334c.

In step406, a reference signal may be generated. The reference signal may be characterized by the reference frequency, f−3 dB. In various embodiments of the invention, the reference signal may be generated by the digital frequency synthesizer188. The digital frequency synthesizer188may generate the reference signal based on the LO signal and the synthesizer control signal338c.

In step408, a filtered version of the reference frequency signal and an attenuated version of the reference frequency signal may be generated. In various embodiments of the invention, the filtered version of the reference frequency signal may be generated by applying the filtering characteristics of the baseband filter312cto the reference frequency signal, while the attenuated version of the reference frequency signal may be generated based on the reference frequency signal by the amplifier324c.

In step410, the filtered version of the reference frequency signal and the attenuated version of the reference frequency signal may be compared by the comparator330c.The comparison may be based on an amplitude and/or phase of the filtered version of the reference frequency signal versus the corresponding amplitude and/or phase of the attenuated version of the reference frequency signal. Prior to comparing, the respective signals may be averaged.

In step412, a filter control signal336cmay be generated and/or modified based on the comparison from step410. In various embodiments of the invention, the filter control signal may be generated and/or modified by the control logic block334c.

In step414, a resistance, transconductance, and/or capacitance value may be modified for a baseband filter312cbased on the filter control signal336cgenerated and/or modified in step412. In various embodiments of the invention that comprise an RC filter, a resistance and/or capacitance value may be modified based on the filter control signal336c.In various embodiments of the invention that comprise a GmC filter, a transconductance and/or capacitance value may be modified based on the filter control signal336c.

Aspects of a system for filter calibration using fractional-N synthesized signals may include a single-chip multi-band RF receiver140athat enables generation of a LO signal by a PLL circuit within the single-chip, and enables calibration of a frequency response for a filter circuit integrated within the chip. The frequency response may include a filter cut-off frequency and/or a filter phase shift. The filter cut-off frequency may represent a frequency beyond which the filter circuit may attenuate signal amplitudes by at least 3 dB, for example. The filter phase shift may represent a phase shift induced in signals that are processed by the filter circuit. A reference signal may be generated based on the generated LO signal and a synthesizer control signal. The frequency response may be calibrated by adjusting the filter circuit based on the generated reference signal. For an RC filter, exemplary parameters may comprise resistance values and/or capacitance values. For a GmC filter, exemplary parameters may comprise transconductance values and/or capacitance values. In various embodiments of the invention, the function of the PLL may be implemented by a Σ-Δ fractional-N synthesizer174. The function of the filter circuit may be implemented by a baseband filter312c.

The single-chip multi-band RF receiver140amay enable generation of a reference signal based on the generated LO signal and on a synthesizer control signal. The reference signal may be generated by the digital frequency synthesizer188. The synthesizer control signal may be generated by a control logic block334c.The single-chip multi-band RF receiver140amay also enable generation of an attenuated reference signal by attenuating the reference signal. The reference signal may be attenuated by the amplifier324c.The single-chip multi-band RF receiver140amay enable generation of a filtered reference signal based on filtering of the reference signal by the filter circuit. The single-chip multi-band RF receiver140amay enable comparison of the attenuated reference signal and the filtered reference signal. The comparison may be performed by the comparator330c.

The single-chip multi-band RF receiver140amay also enable computation of averages for the attenuated reference signal and for the filtered reference signal, prior to performing the comparison. Each average may be computed by an rms block326c.The single-chip multi-band RF receiver140amay enable generation of one or more filter control signals based on the comparison. The control logic block334cmay enable generation of the filter control signals336c.

The single-chip multi-band RF receiver140amay enable adjustment of a resistance value, and/or a capacitance value, for the filter circuit integrated within the single chip based on the generated one or more control signals. The single-chip multi-band RF receiver140amay enable modification of a cut-off frequency for the filter circuit integrated within the chip based on the adjusting of the resistance value, and/or the capacitance value.

The single-chip multi-band RF receiver140amay enable adjustment of a transconductance value, and/or a capacitance value, for the filter circuit integrated within the chip based on the generated one or more control signals. The single-chip multi-band RF receiver140amay enable modification of a cut-off frequency for the filter circuit integrated within the chip based on the adjusting of the transconductance value, and/or the capacitance value.

The filter circuit integrated within the single-chip multi-band RF receiver140amay comprise a low-pass filter. An exemplary low pass filter may comprise a Chebychev filter.

Accordingly, aspects of the invention may be realized in hardware, software, firmware and/or a combination thereof. The invention may be realized in a centralized fashion in at least one computer system or in a distributed fashion where different elements are spread across several interconnected computer systems. Any kind of computer system or other apparatus adapted for carrying out the methods described herein is suited. A typical combination of hardware, software and firmware may be a general-purpose computer system with a computer program that, when being loaded and executed, controls the computer system such that it carries out the methods described herein.