Fast fourier transform (FFT) addressing apparatus and method

Apparatus for generating memory addresses for accessing and storing data in an FFT (Fast Fourier Transform) computation is provided. The FFT computation is typically performed by computing a plurality of FFT butterflies belonging to a plurality of ranks. The apparatus includes a butterfly counter for determining the current FFT butterfly being computed. The butterfly counter produces a plurality of butterfly carries. A rank counter for determining the rank of said current FFT butterfly being computed produces a rank number. Coupled to the rank and butterfly counters is incremental curcuitry, which generates an incremental number in response to the rank number and the butterfly carries. An adder circuitry coupled to the incremental circuitry adds the incremental number and a plurality of memory addresses to produce the FFT data memory addresses.

TECHNICAL FIELD OF THE INVENTION 
This invention relates generally to the field of FFT computing circuits, 
and more particularly to FFT memory addressing apparatus and method for 
performing the same. 
BACKGROUND OF THE INVENTION 
The Fast Fourier Transform (FFT) is the generic name for a class of 
computationally efficient algorithms that implement the Discrete Fourier 
Transform (DFT) and are widely used in the field of digital signal 
processing. With the advent of integrated circuits (IC), near real time 
digital signal processing has become possible. However, circuit designers 
are still striving for faster and better FFT IC devices. 
In a typical computing system, the most time consuming operation is usually 
associated with memory. This is evident in the many schemes which have 
been developed to boost memory access time to increase the overall speed 
of computing systems. 
The FFT algorithm is especially memory access and storage intensive. For 
example, in order to compute a radix-4 DIF FFT butterfly, four pieces of 
data and three twiddle coefficients are read from memory and four 
resultant data are written back into memory. In an N-point radix-4 
decimation-in-frequency (DIF) FFT, there are a total of 2Nlog.sub.4 N 
pieces of data and intermediate data to be accessed and stored and a total 
of (3N/4)log.sub.4 N twiddle coefficients to be accessed. In other words, 
to compute a 64-point radix-4 DIF FFT, 192 data memory reads and 192 data 
memory writes and 144 memory reads for the twiddle coefficients must be 
performed. Accordingly, it is desirable to provide adequate memory 
arrangement to accommodate all the data and coefficients. 
In computing the FFT butterflies going from one rank to the next, the 
output data of the butterfly computations of the former become the input 
data of the latter, where the order and grouping of the data vary from one 
rank to the next. It is therefore necessary to ensure that correct data is 
accessed from memory for each butterfly computation. 
To further increase speed, a fully parallel implementation of an FFT 
circuit may be desirable. In such a parallel FFT circuit, it is preferable 
that the four pieces of data and the three twiddle coefficients are 
available substantially simultaneously for each butterfly computation. 
It is apparent from the foregoing that memory access for an FFT circuit is 
not trivial. Not only a large number of data are accessed from memory, but 
a large number of resultant data are also stored back into memory for use 
in future computations. For each butterfly computation, the data and 
twiddle coefficient must also be obtained substantially simultaneously. 
Furthermore, for each memory access and storage operation, the address 
must be correctly computed and referenced. 
It is therefore desirable to increase the speed of FFT memory access for 
the purpose of obtaining and storing FFT computational data and twiddle 
coefficients. It is further desirable to devise a scheme to access and 
store the data and twiddle coefficients systematically so that correct 
data and twiddle coefficients are obtained in a timely fashion for each 
butterfly computation. In particular, a need has arisen for FFT memory 
addressing apparatus and method that provides for the above-mentioned 
desirable features. 
SUMMARY OF THE INVENTION 
In accordance with the present invention, FFT memory addressing apparatus 
and method are provided which substantially eliminate or reduce 
disadvantages and problems associated with prior addressing schemes. 
In one aspect of the present invention, there is provided apparatus for 
generating memory addresses for accessing and storing data in an FFT 
computation. The FFT computation is performed by computing a plurality of 
FFT butterflies belonging to a plurality of ranks. The apparatus includes 
a butterfly counter for determining the current FFT butterfly being 
computed. The butterfly counter produces a plurality of butterfly carries. 
A rank counter for determining the rank of said current FFT butterfly 
being computed is also included, and a rank number is produced therefrom. 
Coupled to the rank and butterfly counters is incremental circuitry, which 
generates an incremental number in response to the rank number and the 
butterfly carries. An adder circuitry coupled to the incremental circuitry 
adds the incremental number and a plurality of memory addresses to produce 
the FFT data memory addresses. 
In another aspect of the present invention, a method for accelerating the 
memory access and storage speed in an FFT computation is provided. The FFT 
computation is performed in ranks of FFT butterflies, the method includes 
the steps of producing initial memory addresses, counting the number of 
the current butterfly to be computed and producing a plurality of 
butterfly carry values. Further, the rank of the current butterfly is 
determined to produce a rank number. An incremental number is produced 
subsequently in response to the butterfly carry values and the rank 
number, and the incremental number is added to the initial memory 
addresses to produce addresses for the current butterfly. 
In yet another aspect of the current invention, there is provided apparatus 
for generating addresses for accessing three twiddle coefficients for 
computing a plurality of radix-4 FFT butterflies. The apparatus includes 
butterfly counting circuitry for determining the current FFT butterfly 
being computed and producing a butterfly count A rank counting circuitry 
determines the rank of the current FFT butterfly being computed and 
produces a rank number. Further included is a shift controller coupled to 
the rank counting circuitry, which controls a shifter that receives the 
butterfly count, shifts the butterfly count a plurality of places to the 
left and produces a shifted butterfly count. In addition, circuitry 
coupled to the shifter adds two zeros as the most significant bits to the 
shifted butterfly count and produces a first twiddle coefficient address. 
The second twiddle coefficient address is generated by circuitry coupled 
to the shifter for adding two zeros as the most significant bit and least 
significant bit to the shifted butterfly count. An adder circuitry coupled 
to the shifter and the second address producing circuitry adds the shifted 
butterfly count and the second address to produce a third twiddle 
coefficient address. 
An important technical advantage of the present invention provides for the 
capability of storing FFT data in R separate banks of memory, and the 
ability for reading R correct FFT data from the R banks of memory, where R 
is the radix number. 
Another important technical advantage of the present invention provides for 
memory addressing apparatus and method which allows for accessing all the 
data required for an FFT butterfly computation simultaneously, and for 
accessing the twiddle coefficients for the butterfly substantially 
simultaneously. 
Yet another important technical advantage of the present invention provides 
for generating read addresses for accessing FFT butterfly input data in a 
rank simultaneously, and manipulating the read addresses to produce the 
write addresses for storing the output data from the computation of the 
same FFT butterfly, so that the output data are stored in different memory 
banks to allow simultaneous access thereof for FFT butterfly computations 
of the next rank.

DETAILED DESCRIPTION OF THE INVENTION 
The FFT Compiler 
FIG. 1 provides an overview of the inputs and outputs of a preferred 
embodiment of an FFT compiler 10 constructed in accordance with the 
teachings of the present invention. FFT compiler 10 is capable of 
receiving a set of design requirements 12 specified by a user. The set of 
design requirements 12 may include specifications on problem size, word 
size, accuracy, throughput, and special pre- and post-processing 
operations. Based on design requirements 12, FFT compiler 10 selects from 
among a number of architecture styles 1, 2, . . . , k 14-18 one which 
optimizes the resultant FFT device. The architecture styles offer space 
and time tradeoffs, which are dependent on user-specified design 
requirements 12. Additionally, sequential, parallel and pipelined 
architecture styles are among architecture styles 14-18. Note that 
although architecture styles 1, 2, . . . , k 14-18 are shown explicitly 
outside the physical boundaries of FFT compiler 10, the architecture 
styles are in fact knowledge resident within FFT compiler 10. 
Once an architecture style is selected, FFT compiler 10 generates an FFT 
circuit realization of the selected architecture style. The FFT circuit is 
generated by first generating large functional blocks of the circuit such 
as control circuits; memory blocks; clock signal generation circuits, 
drivers and distribution networks; memory addressing logic; and glue logic 
as known in the art. These large functional blocks are in turn implemented 
by generating smaller functional or logic blocks, such as adders, 
subtractors, multipliers, multiplexers, registers, latches and any 
combinatorial special function cells. 
The FFT circuit realization is then implemented by using instances made 
from functional blocks stored in a macrocell library 20. Examples of the 
functional blocks or macrocells include adders, multipliers, registers, 
multiplexers, logic gates and the like. FFT compiler 10 subsequently 
generates a semiconductor device specification 22, or more commonly a net 
list, from which an implementation in silicon may be fabricated as known 
in the art. Semiconductor device specification 22 includes functional 
block specifications, interconnection between functional blocks, and 
layout of the functional blocks and interconnections. 
Radix-4 Decimation-In-Frequency FFT 
A more efficient method of computing the Discrete Fourier Transform (DFT) 
is the radix-4 decimation-infrequency (DIF) FFT where an N-point FFT is 
reduced to the computation of four N/4-point FFTs. Referring to FIG. 2, a 
radix-4 DIF FFT flow diagram, more commonly known as a butterfly, is 
shown. The computation in the radix-4 DIF FFT butterfly may be represented 
in the following equations: 
##EQU1## 
where W.sub.n =e.sup.-j2.pi./N, and W.sub.N is commonly known as the 
twiddle factor or twiddle coefficient. Note that each radix-4 DIF 
butterfly requires four complex data inputs and only three twiddle 
coefficients for its evaluation (W.sub.N.sup.0 is, by definition, 1), and 
produces four complex data outputs. The radix-4 DIF butterfly computation 
may also be partitioned into a scaling and sum section and a complex 
multiplication section. 
Accordingly, an N-point DFT may be evaluated as a collection of 4-point 
butterflies, where N is a power of four. FIG. 3 shows a simpler graphical 
representation of 10 the radix-4 DIF FFT butterfly, which explicitly shows 
the four inputs x(n), x(n+N/4), x(n+N/2) and x(n+3N/4) and the four 
outputs y(n), y(n+N/4), y(n+N/2) and y(n+3N/4). 
A graphical representation of a 64-point, radix-4 DIF FFT is shown in FIG. 
4. Several characteristics of radix-4 DIF FFT are worth noting here. In an 
N-point, radix-4 FFT algorithm, the frequency decimation process passes 
through a total of M ranks, where N=4.sup.M with N/4 4-point butterflies 
per rank. The total number of butterflies in an N-point radix-4 DIF FFT is 
(N/4)log.sub.4 N. Therefore, in the example shown in FIG. 4, there are 
three ranks of 16 butterflies per rank with a total of 48 butterflies for 
N=64. 
Note that the four data inputs for each butterfly and the four data outputs 
from each butterfly exhibit certain regularity in the positions from which 
they originate and terminate. For example, the first butterfly of rank one 
has four inputs from positions 0, 16, 32 and 48. The numerical spacing 
between the positions is 16. The first butterfly of rank two has four 
inputs from positions 0, 4, 8, 12, where the spacing is 4. For the 
butterflies in rank three, the spacing of the inputs becomes one. 
Therefore, it seems that there exists an incremental spacing of base four. 
Further note that the N input data samples of the input signal x(n) is in 
normal ascending order, while the order of the N resultant frequency 
output samples seems scrambled. In fact, the output samples are in 
digit-reversed order in the quaternary system. For example, the data at 
location 30 (corresponding to number 132 in the quaternary system) 
exchanges positions with the data at location 45 (corresponding to 
quaternary number 231, digit-reversal of 132). For additional information 
on the FFT algorithm, please refer to textbooks on the topic of digital 
signal processing, such as Digital Signal Processing by Alan V. Oppenheim 
and Ronald W. Schafer. 
Pipelined FFT Architecture 
Referring to FIG. 5, a block diagram of a pipelined FFT architecture 24 for 
computing radix-4 DIF FFT is shown. Architecture style 24 is a pipelined 
architecture in which one butterfly computation is computed in one 
pipeline cycle. Input data are received and stored in a memory such as a 
RAM (random access memory) 26. A controller 28 supplies control signals on 
lines 30 which are coupled to an address generator 32. Address generator 
32 is coupled to RAM 26 and supplies read and write addresses thereto on 
bus 34. 
From RAM 26 four data are accessed and supplied to a pipelined data path 36 
on lines 38. Pipelined data path 36 is capable of computing a radix-4 DIF 
butterfly, the computation consisting of 16 additions/subtractions and 
three complex multiplications. The complex multiplication procedure 
requires three complex twiddle coefficients, which are stored in 
preferably at least two coefficient ROMs (read-only memories) 40 and 
output to pipelined data path on lines 42. In order to read the twiddle 
coefficients substantially simultaneously, two ROMs are used for storage 
purpose thereof. If space allows, three ROMs may be used so that all three 
coefficients are accessed and available simultaneously. The addresses for 
reading the correct twiddle coefficients from coefficient ROMs 40 are 
generated in a coefficient address generator 44 and supplied to 
coefficient ROMs 40 on lines 46. Coefficient address generator 44 receives 
control signals from controller 28 on lines 48. The output of pipelined 
data path 36 is coupled to RAM 26 by lines 50, so that the output 
generated from each butterfly computation may be stored in RAM 26. 
Referring to FIG. 6 for the timing of pipelined FFT architecture 24, two 
time periods, t.sub.sys1 and t.sub.sys2, consisting of two system clock 
periods are shown. During t.sub.sys1, four input data are accessed from 
RAM 26 and placed at the input of pipelined data path 36. Concurrently, 
during t.sub.sys1, the first two twiddle coefficients are read from ROMs 
40 and also supplied to pipelined data path 36. 
In the next period of the system clock, t.sub.sys2, the third coefficient 
is read from ROMs 40 and also supplied to pipelined data path 36. During 
the same time period, t.sub.sys2, the outputs become available at the 
output of pipelined data path 36 and are stored in RAM 26. It follows that 
a pipeline delay is two periods of the system clock, or (t.sub.sys1 
+t.sub.sys2), which will be referred to as one pipeline cycle. 
The details of architecture style 24 are shown in FIG. 7, where like 
elements are referred to by like numerals in FIG. 6. Input data has a path 
70 into a permutation network 72. Permutation network 72 is coupled to the 
input of a pipeline register 74, the output of which is coupled to four 
banks of RAM 26: RAM0, RAM1, RAM2 and RAM3, 76-82, respectively. Address 
generator 32 is coupled to each bank of RAM 76-82 via lines 34. Address 
generator 32 is controlled by controller 28 and coupled thereto via lines 
30. The output of RAM0, . . . RAM3 76-82 are coupled to the input of a 
pipeline register 84, the output of which is coupled to the input of 
another permutation network 86. The output of permutation network 86 is 
coupled to the input of a scaling circuit 88, the output of which is 
coupled to the input of pipelined data path 36. The operation of both 
permutation network 86 and scaling circuit 88 are controlled by controller 
28, the control signals being transported on lines 90 and 92, 
respectively. 
Pipelined data path 36 includes a pipeline register 94. From pipeline 
register 94, the data are supplied to a bank of eight adders/subtractors 
96. The output of adders/subtractors 96 is coupled to the input of yet 
another pipeline register 98. Subsequently, the output of pipeline 
register 98 is coupled to another eight adders/subtractors 100, and the 
output of adders/subtractors 100 is coupled to a pipeline register 102. 
Coefficient address generator 44, coupled to controller 28 via lines 48, 
generates addresses on lines 46 for accessing coefficient ROMs 40. The 
output of coefficient ROMs 40 is coupled to pipeline register 102 via 
lines 42. Three of the four outputs of pipeline register 102 are coupled 
to a first stage of twelve multipliers 104, followed by a pipeline 
register 106 and a second stage of twelve multipliers 108. The output of 
multipliers 108 is coupled to a pipeline register 110, followed by six 
adders/subtractors 112 and another pipeline register 114. Note that a data 
path 116 supplies one of the four outputs from pipeline register 102 to 
subsequent pipeline registers 102, 106, 110 and 114 without passing 
through multipliers 104 and 108 and adders/subtractors 112. The output of 
pipeline register 114 is coupled to a sign-bit detection circuit 118 via 
lines 50, the output of which is coupled to the input of permutation 
network 72 via lines 120. 
The operations of pipelined FFT architecture 24 will become more apparent 
from the discussion below on the major components thereof. 
Address Generator 
The address generator 32 must ensure that the correct data is presented to 
pipelined data path 36 at the beginning of each pipeline cycle, and that 
the output data from pipelined data path 36 is stored in RAM 26 at the end 
of each pipeline cycle. As discussed above, each radix-4 DIF butterfly 
computation requires four complex data 
inputs RAM 26 has four banks RAM0 to RAM3 76-82 so that the four data 
required for each butterfly computation can be extracted concurrently from 
RAM banks 76-82. During the same pipeline cycle, the output data from 
pipelined data path 36 must be stored in the correct bank of RAM 26 to be 
ready for subsequent computations, even though the data are shuffled when 
going from rank to rank during the computations. 
Referring to FIG. 8, a block diagram of address generator 32 constructed in 
accordance with the present invention is shown. A reset circuit 130 
receives timing and control signals from controller 28 on lines 30. Reset 
circuit 130 is coupled to a butterfly counter 132, whose carry values are 
output on lines 133 and provided to an increment circuit 134. The carry 
values on line 133 consist of the carry value into the least significant 
bit of butterfly counter 132 and the second carry value, the fourth carry 
value, etc. In other words, only every other carry value from the binary 
counter elements is output onto lines 133, since radix-4 DIF FFT is being 
implemented. If radix-2 FFT is being implemented, every carry value is 
needed. Similarly, if radix-8 FFT is being implemented, only every third 
carry value is required to generate the address incremental values. 
Butterfly counter 132 is constructed from a plurality of cascaded binary 
counter elements (not shown), each receiving a carry signal from its less 
significant counter element. The construction of such counters are known 
in the art of digital logic circuits, the details of which need not be 
discussed herein. 
A rank counter 135 is coupled to reset circuit 130 and is further coupled 
to increment circuit 134 composed of circuits of varying incremental 
values which increase by base four. These circuits compute the incremental 
address values for each carry line coming from butterfly counter 132. For 
N=1024 and radix-4, increment circuit 134 includes a one's increment 
circuit 136, a four's increment circuit 138, a 16's increment circuit 140 
and a 64's increment circuit 142. The output of increment circuits 136-142 
are summed and connected to a common bus 144, which is coupled to one 
input of four modulo 4 adders 146-152. The output of modulo 4 adders 
146-152 are connected to respective address registers 154-160. The output 
162-168 from each of address registers 154-160 is fed back to the other 
input of respective modulo 4 adders 146-152. The address register outputs 
162-168 are further coupled to RAM banks 76-82 of RAM 26, respectively. 
In operation, butterfly counter 132 and rank counter 135 keep track of 
which butterfly of which rank is currently being computed, so that the RAM 
read and write addresses may be derived therefrom. Both counters 132 and 
135 are reset or initialized by reset circuit 130, which receives 
instructions from controller 28 on line 30. The count from rank counter 
135 is supplied to increment circuits 136-142. In addition, the carry 
values from butterfly counter 132 are supplied to increment circuits 
136-142. The embodiment shown in FIG. 8 is for a 1024-point radix-4 DIF 
FFT, where the increment circuits implement one's, four's, 16's and 64's 
increments. 
Address registers 154-160 are initialized with the addresses of the four 
data for the first butterfly in each rank. Depending on the rank, the 
initial addresses may vary. In the preferred embodiment of the present 
invention, the initial read and write addresses in base four for each 
branch of a butterfly in a rank are shown in TABLE 1. Note that the last 
base 4 digit corresponds to the RAM number used for the read/write 
operation. 
TABLE 1 
______________________________________ 
RANK 1 00000.sub.4 
11111.sub.4 22222.sub.4 
33333.sub.4 
RANK 2 00000.sub.4 
01111.sub.4 02222.sub.4 
03333.sub.4 
RANK 3 00000.sub.4 
00111.sub.4 00222.sub.4 
00333.sub.4 
RANK 4 00000.sub.4 
00011.sub.4 00022.sub.4 
00033.sub.4 
RANK 5 00000.sub.4 
00001.sub.4 00002.sub.4 
00003.sub.4 
______________________________________ 
For subsequent butterfly computations, certain of the incremental amounts 
generated in increment circuit 134 in response to the carry values from 
butterfly counter 132 are summed and supplied to each modulo 4 adder 
146-152. For example, if the least significant carry value into butterfly 
counter 132 is one, the second carry value and the third least significant 
carry value in butterfly counter 132 are zero and one, respectively, then 
the incremental amounts in 1's and 16's increment circuit 136 and 140 are 
summed. Shown in TABLES 2 and 3 are the read and write incremental values 
for ranks 1-5 for a 1,024-point FFT. Modulo 4 adders 146-152 adds the 
addresses in address registers 154-160 and the incremental values as 
supplied by increment circuit 134. The incremented addresses are output 
onto lines 162-168 and supplied to RAM banks 76-82, according to the last 
base 4 digit of the address. 
TABLE 2 
______________________________________ 
READ 1's 4's 16's 64's 
______________________________________ 
RANK 1 00001 00011 00111 01111 
RANK 2 00001 00011 00111 [11111] 
RANK 3 00001 00011 [01111] 
10000 
RANK 4 00001 [00111] 01000 10000 
RANK 5 [00011] 00100 01000 10000 
______________________________________ 
TABLE 3 
______________________________________ 
WRITE 1's 4's 16's 64's 
______________________________________ 
RANK 1 00001 00011 00111 01111 
RANK 2 00001 00011 00111 [10000] 
RANK 3 00001 00011 [01000] 
10000 
RANK 4 00001 [00100] 01000 10000 
RANK 5 [00010] 00100 01000 10000 
______________________________________ 
The logic behind the generation of the data read and write address 
increments shown in TABLES 2 and 3 may be summarized in the form of a 
flowchart beginning in block 170 as shown in FIGS. 9 and 10. An index c to 
an array CARRY is initialized to zero in block 171. The values indexed by 
c in the CARRY array represent the carry values in butterfly counter 132 
of address generator 32. In block 172 the value in the CARRY array at 
location c, or CARRY[c], is compared to one. If the value at CARRY[c]is 
equal to one, then a loop count d is initialized to zero in block 173. If 
the comparison in block 172 is false, then execution skips forward, and no 
increments are generated in the corresponding increment circuit 136-142. 
Following block 173, a statement: 
EQU INCR[2*d+1,2*d]=INCR [2*d+1,2*d]+INCR4(d,c,rank) 
is executed in block 174. INCR is an array which contains incremental 
values for each address digit. Since each digit represents two binary bits 
of address, INCR[1,0] to INCR[9,8] represents digits 0 to 4. INCR4 is a 
subroutine which determines the increment for each address digit for a 
certain rank. The statement in block 174 calls the INCR4() subroutine 
while passing three arguments: d, c, and rank to it. 
Referring to FIG. 10, subroutine INCR4 begins in block 175. In block 176, a 
variable INC is initialized to zero. Subsequently in block 177, the rank 
value passed to the INCR4 subroutine is subtracted from the total number 
of ranks, NO-RANK, and the result is set equal to a variable name 
DIAGONAL.sub.-- TEST If value [(c+1)&lt;DIAGONAL.sub.-- TEST] OR [RW.sub.-- 
FLAG AND ((c+1)=DIAGONAL.sub.-- TEST)] is true in block 178, then d is 
compared with c in block 179. The RW-FLAG is one for read and zero for 
write which accounts for the difference between read address increments 
and write address increments in TABLES 2 and 3. In block 179, it is 
determined whether d is less than or equal to c. If the comparison is 
positive in block 179, then the variable INC is set to equal one in block 
180 and execution proceeds to block 181. If the conditions in either block 
178 or block 179 are false, then execution skips to block 181, where the 
value (c+1) is compared to DIAGONAL.sub. -- TEST. If (c+1) is greater than 
or equal to DIAGONAL.sub.-- TEST, then the value of d is compared with 
(c+1) in block 182. If d is equal to (c+1), then the variable INC is set 
to equal to one in block 183, else execution returns in block 184. 
Similarly, if the comparisons in either block 181 or 182 are false, then 
execution skips to RETURN block 184. 
Upon returning from the INCR4 subroutine, the value of INC is summed with 
INCR[2*d+1,2*d] in block 174. Subsequently, the value of d is incremented 
by one in block 185, and in block 186 it is checked to determine whether d 
is equal to the total number of ranks, NO-RANK, minus one. If not, 
execution returns to block 174, if so, execution proceeds to block 187, 
where the value c is incremented by one. In block 188, it is determined 
whether c is equal to NO-RANK minus two, if so, execution ends in block 
189, else execution loops back to block 172. 
The logic in the flowcharts in FIGS. 9 and 10 generates the incremental 
values shown in tabular format in TABLES 2 and 3. In order to understand 
that logic, several items are worth noting in TABLES 2 and 3. TABLE 2 
shows the read address increments for ranks 1 through 5. Note that the 
entries on the diagonal have been bracketed. Note further that the read 
increment entries above the bracketed entries on the diagonal are nothing 
but successive left-shifted bits, as one goes from one's increment to 64's 
increment, with the bits shifted in being ones. For example, for rank 1, 
the entries are successively, 00001, 00011, 00111, and 01111. On the 
diagonal, however, the entries become the left-shifted version of the 
entries above each respective diagonal entry, again with the bit shifted 
in being ones. For example, for rank 3, the diagonal entry is 01111, which 
is 00111 shifted left one bit, with a one shifted in. Below the diagonal, 
the entries are equal to the entry above the diagonal entry plus one. For 
example, for rank 4, the entry 01000 is the entry 00111 above the diagonal 
entry 01111 plus one. 
The pattern changes slightly for write address increments. Referring to 
TABLE 3, the entries above the diagonal are also successively left-shifted 
as one goes from one's increment to 64's increment in each rank. The 
diagonal entries, however, are now the same as the below the diagonal 
entries which are equal to the entry above the diagonal entries plus one. 
For example, for rank 3, the diagonal entry 01000 is the entry above the 
diagonal entry, 00111, plus one. The entries below the diagonal entries 
are equal to the diagonal entries for each incremental value For example, 
for 16's increment, entries for ranks 3-5 are all 01000. 
With the above-described patterns in mind, the logic behind FIGS. 9 and 10 
should be obvious. The subroutine INCR4 tests for whether the current 
increment desired falls on the diagonal by determining DIAGONAL.sub.-- 
TEST in block 177. It also determines whether read or write address 
increments are currently being computed by testing a flag RW.sub.-- FLAG. 
Furthermore, depending on the values of c and d, the variable INC is set 
to equal one, or left to equal zero. The initial addresses for both read 
and write are the same, as shown in TABLE 1. To further illustrate the 
address generator and method, shown in TABLES 4 and 5 are read and write 
addresses, respectively, for the second and third butterflies in ranks 
1-5. 
TABLE 4 
______________________________________ 
(rank, butterfly) 
READ (1,2) (2,2) (3,2) (4,2) (5,2) 
______________________________________ 
ADDR.sub.1 
00001 00001 00001 00001 00011 
ADDR.sub.2 
11112 01112 00112 00012 00012 
ADDR.sub.3 
22223 02223 00223 00023 00013 
ADDR.sub.4 
33330 03330 00330 00030 00010 
______________________________________ 
(1,3) (2,3) (3,3) (4,3) (5,3) 
______________________________________ 
ADDR.sub.1 
00002 00002 00002 00002 00022 
ADDR.sub.2 
11113 01113 00113 00013 00023 
ADDR.sub.3 
22220 02220 00220 00020 00020 
ADDR.sub.4 
33331 03331 00331 00031 00021 
______________________________________ 
TABLE 5 
______________________________________ 
(rank, butterfly) 
WRITE (1,2) (2,2) (3,2) (4,2) (5,2) 
______________________________________ 
ADDR.sub.1 
00001 00001 00001 00001 00010 
ADDR.sub.2 
11112 01112 00112 00012 00011 
ADDR.sub.3 
22223 02223 00223 00023 00012 
ADDR.sub.4 
33330 033330 00330 00030 00013 
______________________________________ 
(1,3) (2,3) (3,3) (4,3) (5,3) 
______________________________________ 
ADDR.sub.1 
00002 00002 00002 00002 00020 
ADDR.sub.2 
11113 01113 00113 00013 00021 
ADDR.sub.3 
22220 02220 00220 00020 00022 
ADDR.sub.4 
33331 03331 00331 00031 00023 
______________________________________ 
Permutation Networks 
Referring to FIG. 11, permutation networks 72 and 86 are positioned at the 
input and output sides of RAM banks 76-82 of RAM 26. Permutation network 
72 is constructed with a plurality of four-to-one multiplexers 190-193 
coupled to the output of sign-bit detection circuit 118 via a bus 194. 
Multiplexers 190-193 receive control signals WS from the lowest base 4 
digit of the write addresses. The output of multiplexers 190-193 are 
coupled to the inputs of RAM banks 76-82, respectively. The outputs of RAM 
banks 76-82 are coupled to a second permutation network 86 constructed in 
like manner as permutation network 72 via a bus 195. Permutation network 
86 consists of four-to-one multiplexers 196-199, which receive control 
signals RS from the lowest base 4 digit of the read addresses. The outputs 
of multiplexers 196-199 are coupled to scaling circuit 88. 
It is important to note that each multiplexer block 190-193 and 196-199 
shown in FIG. 11 is representative of a plurality of multiplexers which 
are required to multiplex all bits of data. For example, in the preferred 
embodiment where data are 32 bits (16 bits real and 16 bits imaginary), 
each multiplexer 190-193 and 196-199 is actually 32 four-to-one 
multiplexers. 
In operation, during the first half of a pipeline cycle, one data is read 
from each RAM bank 76-82 in accordance with the data address generator and 
method as described above. The two least significant bits of each 
generated read address for each RAM bank 76-82 are used to control 
multiplexers 196-199, respectively, as the RS signals. Therefore, in 
actuality, the RS signals consist of eight individual signals, two for 
each multiplexer 196-199. Multiplexers 196-199 then multiplex one of the 
four data present at the input to the output, and are received by scaling 
circuit 88. 
Permutation network 72 operates much in the same fashion as permutation 
network 86. During the second half of a pipeline cycle, four data are 
present on bus 194 from sign-bit detection circuit 118. Multiplexers 
190-193 are under the control of signals WS consisting of the two least 
significant bits of each write address, which multiplex one of the four 
data present at the input to the output. The data are then received by RAM 
banks 76-82. 
Sign-Bit Detection Circuit and Scaling Circuit 
As discussed previously in conjunction with FIG. 4, in an N-point, radix-4 
FFT algorithm, the frequency decimation process passes through a total of 
M ranks (N=4.sup.M), where the output data from one rank become the input 
data of the next. 
In FFT pipeline architecture 24, as the four butterfly output data leave 
the last pipeline register 114 in the pipeline data path 36, their widths 
have essentially doubled from the multiplication process. Each time the 
DIF process passes through yet another rank, the data size doubles. To 
prevent data overflowing the capacity of the hardware, the less 
significant bits in butterfly output data are truncated or right shifted 
to fit the prescribed width of RAM 26. Conditional scaling is then applied 
at the beginning of the next rank to improve the dynamic range of 
subsequent butterfly computations. This conditional scaling is realized by 
the cooperation of sign-bit detection circuit 118 and scaling circuit 88. 
Sign-bit detection circuit 118 determines the largest truncated output data 
in a rank before the data are saved in RAM 26. This determination entails 
detecting the number of duplicated sign bits in the largest data value in 
the rank, which yields the number of bits the data may be scaled or left 
shifted to improve the dynamic range of the data. In other words, sign-bit 
detection circuit 118 determines the number of bits all the output data 
from a rank are to be scaled up, and all the output data from the same 
rank are scaled up by the same number of bits. 
When the computations begin for the next rank, the output data of the 
previous rank, which were stored in RAM 26, become the input data and are 
passed to scaling circuit 88. Scaling circuit 88 left shifts the data by 
the number of bits determined by sign-bit detection circuit 118, and these 
scaled data are then passed to pipelined data path 36. 
Coefficient Address Generator 
In each radix-4 butterfly computation, in addition to the four complex 
data, three complex twiddle coefficients are also required to produce the 
output data. The twiddle coefficients for angles between 0 and 45 degrees 
are calculated with known DSP techniques and are stored in coefficient 
ROMs 40. The memory in coefficient ROMs 40 is duplicated to form two 
copies of the twiddle coefficients. 
Referring to FIG. 12, a block diagram of coefficient address generator 44 
is shown. The output of a butterfly counter 200 is coupled to the input of 
a shifter 202. Shifter 202 may be implemented with a shift register or a 
series of muliplexers connected to perform the shift function. Shifter 202 
is also arranged to receive a number of zeros as input on lines 204. 
Shifter 202 is coupled to a shift control 206, which controls its shift 
function. Shift control 206 is coupled to a rank counter 208 for receiving 
input therefrom. Note that butterfly counter 200 and rank counter 208 
perform identical functions as butterfly counter 132 and rank counter 135 
of FIG. 8. Therefore, only one butterfly counter and one rank counter may 
be implemented in controller 28 and their outputs routed to both address 
generator 32 and coefficient address generator 44. 
The output of shifter 202 is subsequently manipulated to form coefficient 
addresses ADDR.sub.1, ADDR.sub.2 and ADDR.sub.3. For the formation of 
ADDR.sub.1 on address lines 208, two zeros are added to form the uppermost 
two bits. Address lines 208 are coupled to coefficient ROMs 40. For 
forming ADDR.sub.2 on lines 210, one zero is added to form the uppermost 
bit and another zero is added to form the lowermost bit. ADDR.sub.2 is 
then fed into the input of a multiplexer (MUX) 212. ADDR.sub.3 is formed 
by adding ADDR.sub.1 and ADDR.sub.2 in an adder 214, its input connected 
to lines 208 and 210. The output of adder 214 is coupled to the other 
input of multiplexer 212. Multiplexer 212 is coupled to a MUX control 216, 
and the output thereof is supplied on address lines 218 coupled to 
coefficient ROMs 40. 
The coefficient addresses generated by coefficient address generator 44 for 
each butterfly computation may be expressed in equation form as: 
EQU ADDR.sub.1 =[4.sup.r-1 (b mod N/4.sup.r)] mod N, 
EQU ADDR.sub.2 =[2 * 4.sup.r-1 (b mod N/4.sup.r )] mod N, 
and 
EQU ADDR.sub.3 =[3 * 4.sup.r-1 (b mod N/4.sup.r )] mod N, 
where 
N is the number of points, 
b is the butterfly count, 
r is the rank count, and 
n=log.sub.2 N. 
From the foregoing equations, it may be seen that ADDR.sub.2 is twice that 
of ADDR.sub.1 and ADDR.sub.3 is three times that of ADDR.sub.1. In other 
words, ADDR.sub.2 added to ADDR.sub.1 yields ADDR.sub.3. This is performed 
by adder 214. In operation, the butterfly count from counter 200 in (n-2) 
bits is received by shifter 202, forming the upper (n-2) bits therein. 
2(r-1) bits of zeros are also received by shifter 202 on lines 204, which 
form the lower 2(r-1) bits in shifter 202. Shift control 206 computes 
2(r-1) and instructs shifter 202 to shift left by this amount. In effect, 
the left shift by 2(r-1) bits multiplies the number in shifter by 
4.sup.r-1. The output of shifter 202 consists of the lower (n-2) bits, 
which in effect yields [4.sup.r-1 (b mod N/4.sup.r)]. The subsequent 
addition of two bits with value zero yields addresses of n bits. 
Referring back to FIG. 6 for the timing of coefficient access, it may be 
seen that three coefficient accesses are required within one pipeline 
cycle. This is accomplished by accessing the first and second coefficients 
for butterfly first and second branches in the first half of the pipeline 
cycle, and then accessing the third coefficient in the second half of the 
same pipeline cycle. Multiplexer 212 is thus controlled by MUX control 216 
to provide the multiplexing of ADDR.sub.2 and ADDR.sub.3, so that 
ADDR.sub.2 is available in the first half of the pipeline cycle and 
ADDR.sub.3 is available in the second half of the cycle. cl Adders and 
Subtractors 
Referring to FIG. 13, a portion of the radix-4 DIF FFT butterfly diagram is 
shown. Prior to multiplying to the complex twiddle coefficients, the four 
complex data D0-D3 are added and/or subtracted to form output data 00-03 
as shown. Values 1, -1, j and -j shown on those branches indicate 
multipliers. Since each complex data D0-D3 has a real part D0r-D3r and an 
imaginary part D0i-D3i, the total number of additions and subtractions to 
compute 00-03 is 16. 
In order to compute the 16 additions and subtractions for each butterfly in 
a time efficient manner, 16 adders or subtractors are required as shown in 
FIG. 14. Therefore, FFT architecture includes a first bank of eight 
adders/subtractors 96 and a second bank of eight adders/subtractors 100 to 
perform the first computation portion of a radix-4 butterfly. 
Interleaved Complex Multiplier 
In the second computation portion of a radix-4 butterfly, the output data 
00-03 from adders/subtractors 96 and 100 are multiplied with complex 
twiddle coefficients. Recall that since W.sub.N.sup.0 is, by definition, 
equal to one, only three complex multiplications are actually performed. 
Each 5 complex multiplication may be represented as: 
EQU M+jN=(A+jB) * (X+jY), 
or equivalently, as the following two equations: 
EQU M=A * X-B * Y, and 
EQU N=A * Y+B * X, 
where M is the real part of the complex product, and N is the imaginary 
part of the complex product. It is evident from the foregoing that one 
complex multiplication function consisting of multiplying two complex 
numbers is, in effect, four separate multiplications, one addition and one 
subtraction. Therefore, the three twiddle coefficient multiplizations are 
equivalent to a total of twelve multiplications, three additions and three 
subtractions. Therefore, the most time efficient implementation uses 
twelve multipliers, three adders and three subtractors. 
FIG. 15 shows an eight-bit multiplier, multiplying A7-A0 and B7-B0 and 
producing a product shown as P15-P0. In the preferred embodiment of the 
present invention, multipliers of the Booth recoding type as shown in FIG. 
15 are used. Since the Booth recoding algorithm is well known in the art 
of logic circuit design, the details of the algorithm will not be 
discussed herein. However, references such as Digital CMOS Circuit Design 
by Marco Annaratone may be consulted for details. 
In a Booth recoding multiplier, there are four basic building blocks: R, 
M1, M2, FA. Recoders, R, 240-246 receive inputs B(2J-1), B(2J) and B(2J+1) 
and produce a sign bit S on lines 248-254. M1 blocks 256-162 generate a 
"one" at the output lines 264-270 depending on the state of the select 
lines 272-278. An M2 block, such as block 280, is basically a multiplexer 
(MUX) which produces at the output 282 one of the inputs 284 and 286, 
depending on the select input 248. Lastly, an FA, or full adder, such as 
block 282, adds two numbers present at its input 290, produces a sum on 
line 292 and generates a carry signal on line 294. A ripple carry adder 
296 is used to sum all the 30 partial products to form the final product 
P15-P0. Note that for eight-bit multiplicand and multiplier, there are 
four stages 298-304 in the multiplier circuit. 
From the foregoing, it is evident that even though the Booth recoding 
algorithm decreases the number of steps required in the multiplication 
function, the resultant multiplier circuit and interconnections are still 
somewhat cumbersome. For the purpose of illustration, four such 
multipliers, each with four stages 298a-d to 304a-d, Booth recoders 240a-d 
to 246a-d, and a ripple carry adder (R.C.A.) 296a-d for performing one 
complex multiplication may be arranged as shown in FIG. 16. In addition, a 
subtractor 308 and an adder 310 further receive (A * X), (A * Y), (B * X) 
and (B * Y) to compute the real part M and imaginary part N. Such 
placement presents serious routing problems not only between the input 
quantities A, B, X and Y and the various stages of the multipliers, but 
also from each multiplier to subtractor 308 and adder 310. As discussed 
above, twelve multipliers are required to achieve the most time efficient 
implementation of the radix-4 FFT computation. As a result, the total 
layout area of the multipliers may cause the overall size of the FFT 
architecture to exceed the area available on a typical integrated circuit 
device. 
In the preferred embodiment of the present invention, an interleaved 
complex multiplier implementing the Booth recoding algorithm greatly 
reduces the total layout area of the multipliers 104 and 108 (FIG. 7). 
Referring to FIG. 17, a block diagram of an interleaved complex multiplier 
306 is shown. Interleaved complex multiplier 306, when compared with the 
complex multiplier layout shown in FIG. 16, (A * X) stages 298a-304a with 
their respective recoders 240a-246a are interleaved with (A * Y) stages 
298c-304c and their respective recoders 240c-246c. Similarly, (B * X) 
stages 298b-304b with their respective recoders 240b-246b are interleaved 
with (B * Y) stages 298d-304d, but share recoders 240a-246a and 240c-246c 
of (A * X) and (A * Y) stages 298a-304a and 298c-304c. Additionally, 
ripple carry adders 296a and 296c are stacked and aligned with (A * X) and 
(A * Y) stages 298a-304a and 298c-304c, and ripple carry adders 296b and 
296d are stacked and aligned with (B * X) and (B * Y) stages 298b-304b and 
298d-304d. When arranged in the manner shown in FIG. 17, not only is the 
routing length between the input quantities A, B, X, Y and the multiplier 
stages reduced, but the area occupied by the multiplier is also reduced 
since the layout is much more compact and only half as much recoding logic 
is required. In addition, the output from each multiplier becomes 
available near the input of subtractor 308 and adder 310, so that routing 
therebetween is minimal. 
It follows that three such interleaved complex multipliers 306 are used to 
implement the twelve multiplications of the three twiddle coefficient 
multipliers 104 and 108 and adders/subtractors 112 (FIG. 7). More 
specifically, the first stage of multipliers 104 includes interleaved 
partial product generating stages 240a-d, 242a-d, 244a-d and 246a-d of 
three interleaved complex multipliers, and the second stages of 
multipliers 108 include ripple carry adders 296a-d of the three 
interleaved complex multipliers. Six adders/subtractors 112 include one 
adder and one subtractor for each complex multiplier 310 and 308 to sum 
the real and imaginary parts of each output. 
Note that variations of the Booth recoding multipliers exist and one 
skilled in the art will appreciate that the invention is not necessarily 
limited to the Booth recoding multiplier shown in FIG. 15. 
Although the present invention has been described in detail, it should be 
understood that various changes, substitutions and alterations can be made 
thereto without departing from the spirit and scope of the invention as 
defined by the appended claims.