Machine learning for a multi-memory system

A multi-memory apparatus that uses machine learning is described. The apparatus may include an interface controller, a non-volatile memory, and a volatile memory. The interface controller may cause the apparatus to receive a first command from a host device. The interface controller may cause the apparatus to communicate the first command to a machine learning engine and to circuitry configured to store and manage commands for the non-volatile memory and the volatile memory. The interface controller may further cause the apparatus to communicate a second command generated by the machine learning engine to the circuitry. The second command may be based on information determined by the machine learning engine during a training mode.

FIELD OF TECHNOLOGY

The following relates generally to one or more systems for memory and more specifically to machine learning for a multi-memory system.

BACKGROUND

Various types of memory devices and memory cells exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self-selecting memory, chalcogenide memory technologies, and others. Memory cells may be volatile or non-volatile. Non-volatile memory, e.g., FeRAM, may maintain their stored logic state for extended periods of time even in the absence of an external power source. Volatile memory devices, e.g., DRAM, may lose their stored state if disconnected from an external power source.

DETAILED DESCRIPTION

A device, such as an electronic device, may include a non-volatile memory (e.g., a primary memory for storing information among other operations) and a volatile memory (e.g., a secondary memory) that may operate as a cache for the non-volatile memory. Such a configuration may allow the device to benefit from advantages of the non-volatile memory (e.g., non-volatility and persistent storage, high storage capacity, low power consumption) while maintaining compatibility with a host device through the volatile memory, among other aspects. To support this type of configuration, a device may include an interface controller that interfaces with a host device on behalf of the volatile memory and the non-volatile memory. The interface controller may receive many (e.g., millions, billions) of commands from the host device and may manage memory operations of the non-volatile memory and the volatile memory according to the commands. However, due to the quantity of commands, the interface controller may be unable to recognize various operational patterns associated with the commands, and thus may be unable to perform predictive operations that improve device performance (e.g., reduce latency, reduce power) or may otherwise perform the quantity of commands in a less efficient way than is desirable.

According to the techniques described herein, a device may include an engine (e.g., hardware, software, a combination of both) that employs machine learning to learn patterns associated with incoming commands (e.g., memory commands) from a host device and generate internal commands (e.g., internal memory commands) based on (e.g., in response to determining) those patterns. In some examples, the machine learning engine may be or employ an artificial intelligence (AI) neural network, a transformer neural network, a Long Short Term Memory (LSTM) neural network, a gated recurrent unit (GRU) neural network, or other type of learning network, or some combination thereof. Rather than attempting to recognize patterns on an address basis alone, which may occur in other different techniques and may be impracticable for high volumes of command traffic, the machine learning engine may group commands into clusters based on (e.g., in response to determining) one or more shared characteristics so that patterns are easier to detect. In this way the machine learning engine may efficiently recognize patterns associated with incoming commands and in doing so may learn information that allows the device to perform predictive operations that improve device performance, among other benefits.

Features of the disclosure are initially described in the context of a system and a memory subsystem as described with reference toFIGS.1and2. Features of the disclosure are described in the context of a device, as described with reference toFIG.3, and a process flow, as described with reference toFIG.4. These and other features of the disclosure are further illustrated by and described with reference to an apparatus diagram and flowcharts that relate to machine learning for a multi-memory system as described with reference toFIGS.5and6.

FIG.1illustrates an example of a system100that supports machine learning in accordance with examples as disclosed herein. The system100may be included in an electronic device such a computer or phone. The system100may include a host device105and a memory subsystem110. The host device105may be a processor or system-on-a-chip (SoC) that interfaces with the interface controller115as well as other components of the electronic device that includes the system100. The memory subsystem110may store and provide access to electronic information (e.g., digital information, data) for the host device105. The memory subsystem110may include an interface controller115, a volatile memory120, and a non-volatile memory125. In some examples, the interface controller115, the volatile memory120, and the non-volatile memory125may be included in a same physical package such as a package130. However, the interface controller115, the volatile memory120, and the non-volatile memory125may be disposed on different, respective dies (e.g., silicon dies).

The devices in the system100may be coupled by various conductive lines (e.g., traces, printed circuit board (PCB) routing, redistribution layer (RDL) routing) that may enable the communication of information (e.g., commands, addresses, data) between the devices. The conductive lines may make up channels, data buses, command buses, address buses, and the like.

The memory subsystem110may be configured to provide the benefits of the non-volatile memory125while maintaining compatibility with a host device105that supports protocols for a different type of memory, such as the volatile memory120, among other examples. For example, the non-volatile memory125may provide benefits (e.g., relative to the volatile memory120) such as non-volatility, higher capacity, or lower power consumption. But the host device105may be incompatible or inefficiently configured with various aspects of the non-volatile memory125. For instance, the host device105may support voltages, access latencies, protocols, page sizes, etc. that are incompatible with the non-volatile memory125. To compensate for the incompatibility between the host device105and the non-volatile memory125, the memory subsystem110may be configured with the volatile memory120, which may be compatible with the host device105and serve as a cache for the non-volatile memory125. Thus, the host device105may use protocols supported by the volatile memory120while benefitting from the advantages of the non-volatile memory125.

In some examples, the system100may be included in, or coupled with, a computing device, electronic device, mobile computing device, or wireless device. The device may be a portable electronic device. For example, the device may be a computer, a laptop computer, a tablet computer, a smartphone, a cellular phone, a wearable device, an internet-connected device, or the like. In some examples, the device may be configured for bi-directional wireless communication via a base station or access point. In some examples, the device associated with the system100may be capable of machine-type communication (MTC), machine-to-machine (M2M) communication, or device-to-device (D2D) communication. In some examples, the device associated with the system100may be referred to as a user equipment (UE), station (STA), mobile terminal, or the like.

The host device105may be configured to interface with the memory subsystem110using a first protocol (e.g., low-power double data rate (LPDDR)) supported by the interface controller115. Thus, the host device105may, in some examples, interface with the interface controller115directly and the non-volatile memory125and the volatile memory120indirectly. In alternative examples, the host device105may interface directly with the non-volatile memory125and the volatile memory120. The host device105may also interface with other components of the electronic device that includes the system100. The host device105may be or include an SoC, a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or it may be a combination of these types of components. In some examples, the host device105may be referred to as a host.

The interface controller115may be configured to interface with the volatile memory120and the non-volatile memory125on behalf of the host device105(e.g., based on or in response to one or more commands or requests issued by the host device105). For instance, the interface controller115may facilitate the retrieval and storage of data in the volatile memory120and the non-volatile memory125on behalf of the host device105. Thus, the interface controller115may facilitate data transfer between various subcomponents, such as between at least some of the host device105, the volatile memory120, or the non-volatile memory125. The interface controller115may interface with the host device105and the volatile memory120using the first protocol and may interface with the non-volatile memory125using a second protocol supported by the non-volatile memory125.

The non-volatile memory125may be configured to store digital information (e.g., data) for the electronic device that includes the system100. Accordingly, the non-volatile memory125may include an array or arrays of memory cells and a local memory controller configured to operate the array(s) of memory cells. In some examples, the memory cells may be or include FeRAM cells (e.g., the non-volatile memory125may be FeRAM). The non-volatile memory125may be configured to interface with the interface controller115using the second protocol that is different than the first protocol used between the interface controller115and the host device105. In some examples, the non-volatile memory125may have a longer latency for access operations than the volatile memory120. For example, retrieving data from the non-volatile memory125may take longer than retrieving data from the volatile memory120. Similarly, writing data to the non-volatile memory125may take longer than writing data to the volatile memory120. In some examples, the non-volatile memory125may have a smaller page size than the volatile memory120, as described herein.

The volatile memory120may be configured to operate as a cache for one or more components, such as the non-volatile memory125. For example, the volatile memory120may store information (e.g., data) for the electronic device that includes the system100. Accordingly, the volatile memory120may include an array or arrays of memory cells and a local memory controller configured to operate the array(s) of memory cells. In some examples, the memory cells may be or include DRAM cells (e.g., the volatile memory may be DRAM). The non-volatile memory125may be configured to interface with the interface controller115using the first protocol that is used between the interface controller115and the host device105.

In some examples, the volatile memory120may have a shorter latency for access operations than the non-volatile memory125. For example, retrieving data from the volatile memory120may take less time than retrieving data from the non-volatile memory125. Similarly, writing data to the volatile memory120may take less time than writing data to the non-volatile memory125. In some examples, the volatile memory120may have a larger page size than the non-volatile memory125. For instance, the page size of volatile memory120may be 2 kilobytes (2 kB) and the page size of non-volatile memory125may be 64 bytes (64B) or 128 bytes (128B).

Although the non-volatile memory125may be a higher-density memory than the volatile memory120, accessing the non-volatile memory125may take longer than accessing the volatile memory120(e.g., due to different architectures and protocols, among other reasons). Accordingly, operating the volatile memory120as a cache may reduce latency in the system100. As an example, an access request for data from the host device105may be satisfied relatively quickly by retrieving the data from the volatile memory120rather than from the non-volatile memory125. To facilitate operation of the volatile memory120as a cache, the interface controller115may include multiple buffers135. The buffers135may be disposed on the same die as the interface controller115and may be configured to temporarily store data for transfer between the volatile memory120, the non-volatile memory125, or the host device105(or any combination thereof) during one or more access operations (e.g., storage and retrieval operations).

An access operation may also be referred to as an access process or access procedure and may involve one or more sub-operations that are performed by one or more of the components of the memory subsystem110. Examples of access operations may include storage operations in which data provided by the host device105is stored (e.g., written to) in the volatile memory120or the non-volatile memory125(or both), and retrieval operations in which data requested by the host device105is obtained (e.g., read) from the volatile memory120or the non-volatile memory125and is returned to the host device105.

To store data in the memory subsystem110, the host device105may initiate a storage operation (or “storage process”) by transmitting a storage command (also referred to as a storage request, a write command, or a write request) to the interface controller115. The storage command may target a set of non-volatile memory cells in the non-volatile memory125. In some examples, a set of memory cells may also be referred to as a portion of memory. The host device105may also provide the data to be written to the set of non-volatile memory cells to the interface controller115. The interface controller115may temporarily store the data in the buffer135-a. After storing the data in the buffer135-a, the interface controller115may transfer the data from the buffer135-ato the volatile memory120or the non-volatile memory125or both. In write-through mode, the interface controller115may transfer the data to both the volatile memory120and the non-volatile memory125. In write-back mode, the interface controller115may simply transfer the data to the volatile memory120(with the data being transferred to the non-volatile memory125during a later eviction process).

In either mode, the interface controller115may identify an appropriate set of one or more volatile memory cells in the volatile memory120for storing the data associated with the storage command. To do so, the interface controller115may implement set-associative mapping in which each set of one or more non-volatile memory cells in the non-volatile memory125may be mapped to multiple sets (e.g., rows) of volatile memory cells in the volatile memory120. For instance, the interface controller115may implement n-way associative mapping which allows data from a set of non-volatile memory cells to be stored in one of n sets of volatile memory cells in the volatile memory120. Thus, the interface controller115may manage the volatile memory120as a cache for the non-volatile memory125by referencing the n sets of volatile memory cells associated with a targeted set of non-volatile memory cells. As used herein, a “set” of objects may refer to one or more of the objects unless otherwise described or noted. Although described with reference to set-associative mapping, the interface controller115may manage the volatile memory120as a cache by implementing one or more other types of mapping such as direct mapping or associative mapping, among other examples.

After determining which n sets of volatile memory cells are associated with the targeted set of non-volatile memory cells, the interface controller115may store the data in one or more of the n sets of volatile memory cells. This way, a subsequent (e.g., following) retrieval command from the host device105for the data can be efficiently satisfied by retrieving the data from the lower-latency volatile memory120instead of retrieving the data from the higher-latency non-volatile memory125. The interface controller115may determine which of the n sets of the volatile memory120store the data based on or in response to one or more parameters associated with the data stored in the n sets of the volatile memory120, such as the validity, age, or modification status of the data. Thus, a storage command by the host device105may be wholly (e.g., in write-back mode) or partially (e.g., in write-through mode) satisfied by storing the data in the volatile memory120. To track the data stored in the volatile memory120, the interface controller115may store for one or more sets of volatile memory cells (e.g., for each set of volatile memory cells) a tag address that indicates the non-volatile memory cells with data stored in a given set of volatile memory cells.

To retrieve data from the memory subsystem110, the host device105may initiate a retrieval operation (also referred to as a retrieval process) by transmitting a retrieval command (also referred to as a retrieval request, a read command, or a read request) to the interface controller115. The retrieval command may target a set of one or more non-volatile memory cells in the non-volatile memory125. Upon receiving the retrieval command, the interface controller115may check for the requested data in the volatile memory120. For instance, the interface controller115may check for the requested data in the n sets of volatile memory cells associated with the targeted set of non-volatile memory cells. If one of the n sets of volatile memory cells stores the requested data (e.g., stores data for the targeted set of non-volatile memory cells), the interface controller115may transfer the data from the volatile memory120to the buffer135-a(e.g., in response to determining whether or that one of the n sets of volatile memory cells stores the requested data, as described inFIGS.4and5) so that it can be transmitted to the host device105.

In general, the term “hit” may be used to refer to the scenario where the volatile memory120stores data targeted by the host device105. If the n sets of one or more volatile memory cells do not store the requested data (e.g., the n sets of volatile memory cells store data for a set of non-volatile memory cells other than the targeted set of non-volatile memory cells), the interface controller115may transfer the requested data from the non-volatile memory125to the buffer135-a(e.g., in response to determining whether or that the n sets of volatile memory cells do not store the requested data, as described with reference toFIGS.4and5) so that it can be transmitted to the host device105. In general, the term “miss” may be used to refer to the scenario where the volatile memory120does not store data targeted by the host device105.

In a miss scenario, after transferring the requested data to the buffer135-a, the interface controller115may transfer the requested data from the buffer135-ato the volatile memory120so that subsequent read requests for the data can be satisfied by the volatile memory120instead of the non-volatile memory125. For example, the interface controller115may store the data in one of the n sets of volatile memory cells associated with the targeted set of non-volatile memory cells. But then sets of volatile memory cells may already be storing data for other sets of non-volatile memory cells. So, to preserve this other data, the interface controller115may transfer the other data to the buffer135-bso that it can be transferred to the non-volatile memory125for storage. Such a process may be referred to as “eviction” and the data transferred from the volatile memory120to the buffer135-bmay be referred to as “victim” data.

In some cases, the interface controller115may transfer a subset of the victim data from the buffer135-bto the non-volatile memory125. For example, the interface controller115may transfer one or more subsets of victim data that have changed since the data was initially stored in the non-volatile memory125. Data that is inconsistent between the volatile memory120and the non-volatile memory125(e.g., due to an update in one memory and not the other) may be referred to in some cases as “modified” or “dirty” data. In some examples (e.g., if interface controller operates in one mode such as a write-back mode), dirty data may be data that is present in the volatile memory120but not present in the non-volatile memory125.

So, the interface controller115may perform an eviction procedure to save data from the volatile memory120to the non-volatile memory125if the volatile memory120is full (e.g., to make space for new data in the volatile memory120). In some examples, the interface controller115may perform a “fill” procedure in which data from the non-volatile memory125is saved to the volatile memory120. The interface controller115may perform a fill procedure in the event of a miss (e.g., to populate the volatile memory120with relevant data). For example, in the event of a read miss, which occurs if a read command from the host device105targets data stored in the non-volatile memory125instead of the volatile memory120, the interface controller115may retrieve (from the non-volatile memory125) the data requested by the read command and, in addition to returning the data to the host device, store the data in the volatile memory120(e.g., so that the data can be retrieved quickly in the future).

Thus, the memory subsystem110may satisfy (or “fulfill”) requests (e.g., read commands, write commands) from the host device105using either the volatile memory120or the non-volatile memory125, depending on the hit or miss status of the request. For example, in the event of a read miss, the read command from the host device105may be satisfied by the non-volatile memory125, which means that the data returned from the host device105may originate from the non-volatile memory125. And in the event of a read hit, the read command from the host device105may be satisfied by the volatile memory120, which means that the data returned from the host device105may originate from the volatile memory120. In some examples, the ratio of hits to misses (“hit-to-miss ratio”) may be relatively high (e.g., the hit percentage (or “hit rate”) may be around 85% whereas the miss percentage (or “miss rate”) may be around 15%).

In some examples, the interface controller115may use machine learning to preemptively manage the volatile memory120and the non-volatile memory125, among other components and devices. For example, the interface controller115may be trained during a first mode, such as a training mode, to recognize various patterns (e.g., patterns for operating the memory subsystem110) associated with commands received during the first mode. If operated in a second mode, such as a field mode (e.g., a mode in which the interface controller115operates on user data), the interface controller115may use the information learned during the first mode to predictively perform memory operations based on or in response to commands received from the host device105(e.g., the interface controller115may perform one or more memory operations before instructed or caused to do so by the host device105).

The system100may include any quantity of non-transitory computer readable media that support quality-of-service information as described herein. For example, the host device105, the interface controller115, the volatile memory120, or the non-volatile memory125may include or otherwise may access one or more non-transitory computer readable media storing instructions (e.g., firmware) for performing the functions ascribed herein to the host device105, the interface controller115, the volatile memory120, or the non-volatile memory125. For example, such instructions, if executed by the host device105(e.g., by a host device controller), by the interface controller115, by the volatile memory120(e.g., by a local controller), or by the non-volatile memory125(e.g., by a local controller), may cause the host device105, the interface controller115, the volatile memory120, or the non-volatile memory125to perform associated functions as described herein.

FIG.2illustrates an example of a memory subsystem200that supports machine learning in accordance with examples as disclosed herein. The memory subsystem200may be an example of the memory subsystem110described with reference toFIG.1. Accordingly, the memory subsystem200may interact with a host device as described with reference toFIG.1. The memory subsystem200may include an interface controller202, a volatile memory204, and a non-volatile memory206, which may be examples of the interface controller115, the volatile memory120, and the non-volatile memory125, respectively, as described with reference toFIG.1. Thus, the interface controller202may interface with the volatile memory204and the non-volatile memory206on behalf of the host device as described with reference toFIG.1. For example, the interface controller202may operate the volatile memory204as a cache for the non-volatile memory206. Operating the volatile memory204as the cache may allow subsystem to provide the benefits of the non-volatile memory206(e.g., non-volatile, high-density storage) while maintaining compatibility with a host device that supports a different protocol than the non-volatile memory206.

InFIG.2, dashed lines between components represent the flow of data or communication paths for data and solid lines between components represent the flow of commands or communication paths for commands. In some cases, the memory subsystem200is one of multiple similar or identical subsystems that may be included in an electronic device. Each subsystem may be referred to as a slice and may be associated with a respective channel of a host device in some examples.

The non-volatile memory206may be configured to operate as a main memory (e.g., memory for long-term data storage) for a host device. In some cases, the non-volatile memory206may include one or more arrays of FeRAM cells. Each FeRAM cell may include a selection component and a ferroelectric capacitor and may be accessed by applying appropriate voltages to one or more access lines such as word lines, plates lines, and digit lines. In some examples, a subset of FeRAM cells coupled with to an activated word line may be sensed, for example concurrently or simultaneously, without having to sense all FeRAM cells coupled with the activated word line. Accordingly, a page size for an FeRAM array may be different than (e.g., smaller than) a DRAM page size. In the context of a memory device, a page may refer to the memory cells in a row (e.g., a group of the memory cells that have a common row address) and a page size may refer to the quantity of memory cells or column addresses in a row, or the quantity of column addresses accessed during an access operation. Alternatively, a page size may refer to a size of data handled by various interfaces or the amount of data a row is capable of storing. In some cases, different memory device types may have different page sizes. For example, a DRAM page size (e.g., 2 kB) may be a superset of a non-volatile memory (e.g., FeRAM) page size (e.g., 64B).

A smaller page size of an FeRAM array may provide various efficiency benefits, as an individual FeRAM cell may need more power to read or write than an individual DRAM cell. For example, a smaller page size for an FeRAM array may facilitate effective energy usage because a smaller quantity of FeRAM cells may be activated if an associated change in information is minor. In some examples, the page size for an array of FeRAM cells may vary, for example dynamically (e.g., during operation of the array of FeRAM cells) depending on the nature of data and command utilizing FeRAM operation.

Although an individual FeRAM cell may need more power to read or write than an individual DRAM cell, an FeRAM cell may maintain a stored logic state for an extended period of time in the absence of an external power source, as the ferroelectric material in the FeRAM cell may maintain a non-zero electric polarization in the absence of an electric field. Therefore, including an FeRAM array in the non-volatile memory206may provide power and efficiency benefits relative to volatile memory cells (e.g., DRAM cells in the volatile memory204), as it may reduce or eliminate constraints to perform refresh operations.

The volatile memory204may be configured to operate as a cache for the non-volatile memory206. In some cases, the volatile memory204may include one or more arrays of DRAM cells. Each DRAM cell may include a capacitor that includes a dielectric material to store a charge representative of the programmable state. The memory cells of the volatile memory204may be logically grouped or arranged into one or more memory banks (as referred to herein as “banks”). For example, volatile memory204may include sixteen banks. The memory cells of a bank may be arranged in a grid or an array of intersecting columns and rows and each memory cell may be accessed or refreshed by applying appropriate voltages to the digit line (e.g., column line) and word line (e.g., row line) for that memory cell. The rows of a bank may be referred to pages, and the page size may refer to the quantity of columns or memory cells in a row (and thus, the amount of data a row is capable of storing). As noted, the page size of the volatile memory204may be different than (e.g., larger than) the page size of the non-volatile memory206.

The interface controller202may include various circuits for interfacing (e.g., communicating) with other devices, such as a host device, the volatile memory204, and the non-volatile memory206. For example, the interface controller202may include a data (DA) bus interface208, a command and address (C/A) bus interface210, a data bus interface212, a C/A bus interface214, a data bus interface216, and a C/A bus interface264. The data bus interfaces may support the communication of information using one or more communication protocols. For example, the data bus interface208, the C/A bus interface210, the data bus interface216, and the C/A bus interface264may support information that is communicated using a first protocol (e.g., LPDDR signaling), whereas the data bus interface212and the C/A bus interface214may support information communicated using a second protocol. Thus, the various bus interfaces coupled with the interface controller202may support different amounts of data or data rates.

The data bus interface208may be coupled with the data bus260, the transactional bus222, and the buffer circuitry224. The data bus interface208may be configured to transmit and receive data over the data bus260and control information (e.g., acknowledgements/negative acknowledgements) or metadata over the transactional bus222. The data bus interface208may also be configured to transfer data between the data bus260and the buffer circuitry224. The data bus260and the transactional bus222may be coupled with the interface controller202and the host device such that a conductive path is established between the interface controller202and the host device. In some examples, the pins of the transactional bus222may be referred to as data mask inversion (DMI) pins. Although shown with one data bus260and one transactional bus222, there may be any quantity of data buses260and any quantity of transactional buses222coupled with one or more data bus interfaces208.

The C/A bus interface210may be coupled with the C/A bus226and the decoder228. The C/A bus interface210may be configured to transmit and receive commands and addresses over the C/A bus226. The commands and addresses received over the C/A bus226may be associated with data received or transmitted over the data bus260. The C/A bus interface210may also be configured to transmit commands and addresses to the decoder228so that the decoder228can decode the commands and relay the decoded commands and associated addresses to the command circuitry230.

The data bus interface212may be coupled with the data bus232and the memory interface circuitry234. The data bus interface212may be configured to transmit and receive data over the data bus232, which may be coupled with the non-volatile memory206. The data bus interface212may also be configured to transfer data between the data bus232and the memory interface circuitry234. The C/A bus interface214may be coupled with the C/A bus236and the memory interface circuitry234. The C/A bus interface214may be configured to receive commands and addresses from the memory interface circuitry234and relay the commands and the addresses to the non-volatile memory206(e.g., to a local controller of the non-volatile memory206) over the C/A bus236. The commands and the addresses transmitted over the C/A bus236may be associated with data received or transmitted over the data bus232. The data bus232and the C/A bus236may be coupled with the interface controller202and the non-volatile memory206such that conductive paths are established between the interface controller202and the non-volatile memory206.

The data bus interface216may be coupled with the data buses238(e.g., data bus238-a, data bus238-b) and the memory interface circuitry240. The data bus interface216may be configured to transmit and receive data over the data buses238, which may be coupled with the volatile memory204. The data bus interface216may also be configured to transfer data between the data buses238and the memory interface circuitry240. The C/A bus interface264may be coupled with the C/A bus242and the memory interface circuitry240. The C/A bus interface264may be configured to receive commands and addresses from the memory interface circuitry240and relay the commands and the addresses to the volatile memory204(e.g., to a local controller of the volatile memory204) over the C/A bus242. The commands and addresses transmitted over the C/A bus242may be associated with data received or transmitted over the data buses238. The data bus238and the C/A bus242may be coupled with the interface controller202and the volatile memory204such that conductive paths are established between the interface controller202and the volatile memory204.

In addition to buses and bus interfaces for communicating with coupled devices, the interface controller202may include circuitry for operating the non-volatile memory206as a main memory and the volatile memory204as a cache. For example, the interface controller202may include command circuitry230, buffer circuitry224, cache management circuitry244, one or more engines246, and one or more schedulers248.

The command circuitry230may be coupled with the buffer circuitry224, the decoder228, the cache management circuitry244, and the schedulers248, among other components. The command circuitry230may be configured to receive command and address information from the decoder228and store the command and address information in the queue250. The command circuitry230may include logic262that processes command information (e.g., from a host device) and storage information from other components (e.g., the cache management circuitry244, the buffer circuitry224) and uses that information to generate one or more commands for the schedulers248. The command circuitry230may also be configured to transfer address information (e.g., address bits) to the cache management circuitry244. In some examples, the logic262may be a circuit configured to operate as a finite state machine (FSM).

The buffer circuitry224may be coupled with the data bus interface208, the command circuitry230, the memory interface circuitry234, and the memory interface circuitry234. The buffer circuitry224may include a set of one or more buffer circuits for at least some banks, if not each bank, of the volatile memory204. The buffer circuitry224may also include components (e.g., a memory controller) for accessing the buffer circuits. In one example, the volatile memory204may include sixteen banks and the buffer circuitry224may include sixteen sets of buffer circuits. Each set of the buffer circuits may be configured to store data from or for (or both) a respective bank of the volatile memory204. As an example, the buffer circuit set for bank 0 (BK0) may be configured to store data from or for (or both) the first bank of the volatile memory204and the buffer circuit for bank 15 (BK15) may be configured to store data from or for (or both) the sixteenth bank of the volatile memory204.

Each set of buffer circuits in the buffer circuitry224may include a pair of buffers. The pair of buffers may include one buffer (e.g., an open page data (OPD) buffer) configured to store data targeted by an access command (e.g., a write command or read command) from the host device and another buffer (e.g., a victim page data (VPD) buffer) configured to store data for an eviction process that results from the access command. For example, the buffer circuit set for BK0 may include the buffer218and the buffer220, which may be examples of buffer135-aand135-b, respectively. The buffer218may be configured to store BK0 data that is targeted by an access command from the host device. And the buffer220may be configured to store data that is transferred from BK0 as part of an eviction process triggered by the access command. Each buffer in a buffer circuit set may be configured with a size (e.g., storage capacity) that corresponds to a page size of the volatile memory204. For example, if the page size of the volatile memory204is 2 kB, the size of each buffer may be 2 kB. Thus, the size of the buffer may be equivalent to the page size of the volatile memory204in some examples.

The cache management circuitry244may be coupled with the command circuitry230, the engines246, and the schedulers248, among other components. The cache management circuitry244may include a cache management circuit set for one or more banks (e.g., each bank) of volatile memory. As an example, the cache management circuitry244may include sixteen cache management circuit sets for BK0 through BK15. Each cache management circuit set may include two memory arrays that may be configured to store storage information for the volatile memory204. As an example, the cache management circuit set for BK0 may include a memory array252(e.g., a Cache DRAM (CDRAM) Tag Array (CDT-TA)) and a memory array254(e.g., a CDRAM Valid (CDT-V) array), which may be configured to store storage information for BK0. The memory arrays may also be referred to as arrays or buffers in some examples. In some cases, the memory arrays may be or include volatile memory cells, such as static RAM (SRAM) cells.

Storage information (or “metadata”) may include content information, validity information, or dirty information (or any combination thereof) associated with the volatile memory204, among other examples. Content information (which may also be referred to as tag information or address information) may indicate which data is stored in a set of volatile memory cells. For example, the content information (e.g., a tag address) for a row of the volatile memory204may indicate which set of one or more non-volatile memory cells currently has data stored in the row. As noted, validity information may indicate whether the data stored in a set of volatile memory cells is actual data (e.g., data having an intended order or form) or placeholder data (e.g., data being random or dummy, not having an intended or important order). And dirty information may indicate whether the data stored in a set of one or more volatile memory cells of the volatile memory204is different than corresponding data stored in a set of one or more non-volatile memory cells of the non-volatile memory206. For example, dirty information may indicate whether data stored in a set of volatile memory cells has been updated relative to data stored in the non-volatile memory206.

The memory array252may include memory cells that store storage information (e.g., tag information, validity information, dirty information) for an associated bank (e.g., BK0) of the volatile memory204. The storage information may be stored on a per-row basis (e.g., there may be respective storage information for each row of the associated non-volatile memory bank). The interface controller202may check for requested data in the volatile memory204by referencing the storage information in the memory array252. For instance, the interface controller202may receive, from a host device, a retrieval command for data in a set of non-volatile memory cells in the non-volatile memory206. The interface controller202may use a set of one or more address bits (e.g., a set of row address bits) targeted by the access request to reference the storage information in the memory array252. For instance, using set-associative mapping, the interface controller202may reference the content information in the memory array252to determine which set of volatile memory cells, if any, stores the requested data.

In addition to storing content information for volatile memory cells, the memory array252may also store validity information that indicates whether the data in a set of volatile memory cells is actual data (also referred to as valid data) or random data (also referred to as invalid data). For example, the volatile memory cells in the volatile memory204may initially store random data and continue to do so until the volatile memory cells are written with data from a host device or the non-volatile memory206. To track which data is valid, the memory array252may be configured to set a bit for each set (e.g., row) of volatile memory cells if actual data is stored in that set of volatile memory cells. This bit may be referred to a validity bit or a validity flag. As with the content information, the validity information stored in the memory array252may be stored on a per-row basis. Thus, each validity bit may indicate the validity of data stored in an associated row in some examples.

In some examples, the memory array252may store dirty information that indicates whether a set (e.g., row) of volatile memory cells stores any dirty data. Like the validity information, the dirty information stored in the memory array252may be stored on a per-row basis.

The memory array254may be similar to the memory array252and may also include memory cells that store storage information for a bank (e.g., BK0) of the volatile memory204that is associated with the memory array252. For example, the memory array254may store validity information and dirty information for a bank of the volatile memory204. However, the storage information stored in the memory array254may be stored on a sub-block basis as opposed to a per-row basis. For example, the validity information stored in the memory cells of the memory array254may indicate the validity of data for subsets of volatile memory cells in a row of the volatile memory204.

As an example, the validity information in the memory array254may indicate the validity of each subset (e.g., 32B or 64B) of data stored in row of BK0 of the volatile memory204. Similarly, the dirty information stored in the memory cells of the memory array254may indicate which subsets of volatile memory cells in a row of the volatile memory204store dirty data. For instance, the dirty information in the memory array254may indicate the dirty status of each subset (e.g., 32B or 64B) of data stored in row of BK0 of the volatile memory204. Storing storage information (e.g., tag information, validity information) on a per-row basis in the memory array252may allow the interface controller202to determine whether there is a hit or whether there is a miss for data in the volatile memory204. Storing storage information (e.g., validity information, dirty information) on a sub-block basis in the memory array254may allow the interface controller202to determine which one or more subsets of data to return to the host device (e.g., during a retrieval process) and which one or more subsets of data to preserve in the non-volatile memory206(e.g., during an eviction process).

Each cache management circuit set may also include a respective pair of registers coupled with the command circuitry230, the engines246, the memory interface circuitry234, the memory interface circuitry240, and the memory arrays for that cache management circuit set, among other components. For example, a cache management circuit set may include a first register (e.g., a register256which may be an open page tag (OPT) register) configured to receive storage information (e.g., one or more bits of tag information, validity information, or dirty information, other information, or any combination) from the memory array252or the scheduler248-bor both. The cache management circuitry set may also include a second register (e.g., a register258which may be a victim page tag (VPT) register) configured to receive storage information (e.g., validity information or dirty information or both) from the memory array254and the scheduler248-aor both. The information in the register256and the register258may be transferred to the command circuitry230and the engines246to enable decision-making by these components. For example, the command circuitry230may issue commands for reading the non-volatile memory206or the volatile memory204based on or in response to storage information in the register256, or the register258, or both.

The engine246-amay be coupled with the register256, the register258, and the schedulers248. The engine246-amay be configured to receive storage information from various components and issue commands to the schedulers248based on or in response to the storage information. For example, if the interface controller202is in a first mode such as a write-through mode, the engine246-amay issue commands to the scheduler248-band in response the scheduler248-bto initiate or facilitate the transfer of data from the buffer218to both the volatile memory204and the non-volatile memory206. Alternatively, if the interface controller202is in a second mode such as a write-back mode, the engine246-amay issue commands to the scheduler248-band in response the scheduler248-bmay initiate or facilitate the transfer of data from the buffer218to the volatile memory204. In the event of a write-back operation, the data stored in the volatile memory204may eventually be transferred to the non-volatile memory206during a subsequent (e.g., following) eviction process.

The engine246-bmay be coupled with the register258and the scheduler248-a. The engine246-bmay be configured to receive storage information from the register258and issue commands to the scheduler248-abased on or in response to the storage information. For instance, the engine246-bmay issue commands to the scheduler248-ato initiate or facilitate transfer of dirty data from the buffer220to the non-volatile memory206(e.g., as part of an eviction process). If the buffer220holds a set of data transferred from the volatile memory204(e.g., victim data), the engine246-bmay indicate which one or more subsets (e.g., which 64B) of the set of data in the buffer220should be transferred to the non-volatile memory206.

The scheduler248-amay be coupled with various components of the interface controller202and may facilitate accessing the non-volatile memory206by issuing commands to the memory interface circuitry234. The commands issued by the scheduler248-amay be based on or in response to commands from the command circuitry230, the engine246-a, the engine246-b, or a combination of these components. Similarly, the scheduler248-bmay be coupled with various components of the interface controller202and may facilitate accessing the volatile memory204by issuing commands to the memory interface circuitry240. The commands issued by the scheduler248-bmay be based on or in response to commands from the command circuitry230or the engine246-a, or both.

The memory interface circuitry234may communicate with the non-volatile memory206via one or more of the data bus interface212and the C/A bus interface214. For example, the memory interface circuitry234may prompt the C/A bus interface214to relay commands issued by the memory interface circuitry234over the C/A bus236to a local controller in the non-volatile memory206. And the memory interface circuitry234may transmit to, or receive data from, the non-volatile memory206over the data bus232. In some examples, the commands issued by the memory interface circuitry234may be supported by the non-volatile memory206but not the volatile memory204(e.g., the commands issued by the memory interface circuitry234may be different than the commands issued by the memory interface circuitry240).

The memory interface circuitry240may communicate with the volatile memory204via one or more of the data bus interface216and the C/A bus interface264. For example, the memory interface circuitry240may prompt the C/A bus interface264to relay commands issued by the memory interface circuitry240over the C/A bus242to a local controller of the volatile memory204. And the memory interface circuitry240may transmit to, or receive data from, the volatile memory204over one or more data buses238. In some examples, the commands issued by the memory interface circuitry240may be supported by the volatile memory204but not the non-volatile memory206(e.g., the commands issued by the memory interface circuitry240may be different than the commands issued by the memory interface circuitry234).

Together, the components of the interface controller202may operate the non-volatile memory206as a main memory and the volatile memory204as a cache. Such operation may be prompted by one or more access commands (e.g., read/retrieval commands/requests and write/storage commands/requests) received from a host device.

In some examples, the interface controller202may receive a storage command from the host device. The storage command may be received over the C/A bus226and transferred to the command circuitry230via one or more of the C/A bus interface210and the decoder228. The storage command may include or be accompanied by address bits that target a memory address of the non-volatile memory206. The data to be stored may be received over the data bus260and transferred to the buffer218via the data bus interface208. In a write-through mode, the interface controller202may transfer the data to both the non-volatile memory206and the volatile memory204. In a write-back mode, in some example, the interface controller202may transfer the data to only the volatile memory204.

In either mode, the interface controller202may first check to see if the volatile memory204has space in memory cells available to store the data. To do so, the command circuitry230may reference the memory array252(e.g., using a set of the memory address bits) to determine whether one or more of the n sets (e.g., row) of volatile memory cells associated with the memory address are empty (e.g., store random or invalid data) or whether one or more of then sets (e.g., row) of volatile memory cells associated with the memory address are full (e.g., store valid data). For example, the command circuitry230may determine whether one or more of the n sets (e.g., rows) of volatile memory cells is available (or is unavailable) based on or in response to determining tag information and validity information stored in the memory array252. In some cases, a set of volatile memory cells in the volatile memory204may be referred to as a line, cache line, or row.

If one of then associated sets of volatile memory cells is available for storing information, the interface controller202may transfer the data from the buffer218to the volatile memory204for storage in that set of volatile memory cells. But if no associated sets of volatile memory cells are empty, the interface controller202may initiate an eviction process to make room for the data in the volatile memory204. The eviction process may involve transferring the victim data from one of then associated sets of volatile memory cells to the buffer220. The dirty information for the victim data may be transferred from the memory array254to the register258for identification of dirty subsets of the victim data. After the victim data is stored in the buffer220, the new data can be transferred from the buffer218to the volatile memory204and the victim data can be transferred from the buffer220to the non-volatile memory206. In some cases, dirty subsets of the old data may be transferred to the non-volatile memory206and clean subsets (e.g., unmodified subsets) may be discarded. The dirty subsets may be identified by the engine246-bbased on or in response to dirty information transferred from the memory array254to the register258during the eviction process.

In another example, the interface controller202may receive a command, such as a retrieval command, from the host device. The retrieval command may be received over the C/A bus226and transferred to the command circuitry230via one or more of the C/A bus interface210and the decoder228. The retrieval command may include address bits that target a memory address of the non-volatile memory206. Before attempting to access the targeted memory address of the non-volatile memory206, the interface controller202may check to see if the volatile memory204stores the data. To do so, the command circuitry230may reference the memory array252(e.g., using a set of the memory address bits) to determine whether one or more of the n sets (e.g., rows) of volatile memory cells associated with the memory address stores the requested data (e.g., whether one or more of the n sets of volatile memory cells associated with the memory address stores the requested data or alternatively do not store the requested data). If the requested data is stored in the volatile memory204, the interface controller202may transfer the requested data to the buffer218for transmission to the host device over the data bus260.

If the requested data is not stored in the volatile memory204(e.g., the requested data may be stored in the non-volatile memory206or another location), the interface controller202may retrieve the data from the non-volatile memory206and transfer the data to the buffer218for transmission to the host device over the data bus260. Additionally, the interface controller202may transfer the requested data from the buffer218to the volatile memory204so that the data can be accessed with a lower latency during a subsequent retrieval operation. Before transferring the requested data, however, the interface controller202may first determine whether one or more of the n associated sets of volatile memory cells is available to store the requested data (e.g., whether one or more of the n associated sets of volatile memory cells is empty or is full). The interface controller202may determine the availability of the n associated sets of volatile memory cells by communicating with the related cache management circuit set. If an associated set of volatile memory cells is available, the interface controller202may transfer the data in the buffer218to the volatile memory204without performing an eviction process. Otherwise, the interface controller202may transfer the data from the buffer218to the volatile memory204after performing an eviction process.

The memory subsystem200may be implemented in one or more configurations, including one-chip versions and multi-chip versions. A multi-chip version may include one or more constituents of the memory subsystem200, including the interface controller202, the volatile memory204, and the non-volatile memory206(among other constituents or combinations of constituents), on a chip that is separate from a chip that includes one or more other constituents of the memory subsystem200. For example, in one multi-chip version, respective separate chips may include each of the interface controller202, the volatile memory204, and the non-volatile memory206. In contrast, a one-chip version may include the interface controller202, the volatile memory204, and the non-volatile memory206on a single chip.

In some examples, the interface controller202may include a machine learning engine that generates commands for the memory subsystem200based on or in response to commands from the host device and information determined from machine learning. The machine learning engine may communicate the generated commands to the command circuitry230, which may store and manage the commands in the same manner as commands received from the host device. The machine learning engine may be centralized with respect to the volatile memory204and the non-volatile memory206, meaning that the machine learning engine may use machine learning to detect patterns (e.g., operational patterns) associated with commands for the volatile memory204as well as patterns associated with commands for the non-volatile memory206. In some examples, the machine learning engine may use different neural networks, algorithms, learning mechanisms, or models for the volatile memory204and the non-volatile memory206. By pre-emptively (e.g., anticipatorily, predictively) generating commands based on or in response to machine learning, the interface controller202may improve (e.g., reduce latency, reduce power consumption) the performance of the memory subsystem200.

FIG.3illustrates an example of a system300that supports machine learning in accordance with examples as disclosed herein. The system300may include a host device305and a memory subsystem310and may be an example of a system100as described with reference toFIG.1. The memory subsystem310may include an interface controller315, a volatile memory320, and a non-volatile memory325, which may be coupled with one another via one or more transmission lines, buses, or both. The interface controller315may be an example of an interface controller202and may include a decoder330, a machine learning (ML) engine335, transaction command queue (TCQ) circuitry340, and a mode controller345. The interface controller315may use machine learning to improve performance of the memory subsystem310.

The decoder330may be configured to receive commands from the host device305(e.g., over the C/A bus350) and decode the received commands. The decoder330may also be configured to communicate decoded commands to the ML engine335and to the TCQ circuitry340, each of which may be coupled with the decoder330. In some examples, the decoder330may be configured to communicate a decoded command to the ML engine335and the TCQ circuitry in parallel (e.g., the decoder330may concurrently communicate the command to the ML engine335and the TCQ circuitry340).

The TCQ circuitry340may be an example of the command circuitry230and may be configured to store commands for the memory subsystem310and manage communication of the commands to appropriate components of the memory subsystem310. Put another way, the TCQ circuitry340may be configured to temporarily buffer commands and distribute (e.g., transfer, send) the commands to other components of the memory subsystem310, such as schedulers for the volatile memory320and the non-volatile memory325(e.g., schedulers similar to the scheduler248-aand the scheduler248-b). The TCQ circuitry340may include an array355(which may also be referred to as a buffer, a queue, or a storage structure) and logic360. The array355may store commands received from the decoder330(and commands received from the ML engine335) as well as control information corresponding to the commands, such as address information (e.g., bank information, row information, column information) and QoS information. The logic360may be configured to determine hits and misses for the commands, among other information, so that the TCQ circuitry340can communicate the commands and other control information from the array355to the appropriate scheduler.

The ML engine335may be capable of machine learning and generating commands based on (e.g., in accordance with or in response to) information determined as part of machine learning. Accordingly, the ML engine335may support a first mode, such as a training mode, in which the ML engine performs machine learning and a second mode, such as a field mode, in which the ML engine uses information from the training mode to generate commands. In some examples, the ML engine335may support continuous learning, which means that the ML engine may be configured to use information during operating in the field mode over a duration (e.g., information based on commands associated with user data) to generate predictive commands. The ML engine335may be or include software, hardware, or combination thereof, that is configured for performing machine learning.

In the training mode, the ML engine335may receive sequences of commands that allow the ML engine to detect various patterns (e.g., operational patterns of the memory subsystem310) associated with the command sequences. The ML engine335may use the patterns and information learned during the training mode to build one or more models that the ML engine335can use during the field mode to process commands. Rather than detecting patterns on the basis of memory address alone, which may inefficient, impracticable, or otherwise disadvantageous for high volumes of commands, the ML engine335may group (e.g., logically) received commands based on (e.g., conditioned on or in response to determining) one or more shared characteristics, then detect patterns based on (e.g., by referring to) the grouped commands. For example, the ML engine335may create address clusters based on (e.g., according to or in response to determining) the characteristics and find pattern information within or based on the address clusters (as opposed to detecting pattern information based on all addresses). Shared characteristics may also be referred to as memory reference characteristics.

In some examples, the ML engine335may group commands based on (e.g., conditioned on or in response to determining) a read bandwidth associated with the commands. A read bandwidth may refer to an amount of data read from the volatile memory320, the non-volatile memory325, or both, during a predetermined amount of time. In some examples, the ML engine335may group commands based on (e.g., conditioned on or in response to determining) a write bandwidth associated with the commands. A write bandwidth may refer to an amount of data written to the volatile memory320, the non-volatile memory325, or both, during a predetermined amount of time.

In some examples, the ML engine335may group commands based on (e.g., conditioned on or in response to determining) a read distance associated with the commands. A read distance may refer to the amount of time in between consecutive read operations for a set of data or a memory address. In some examples, the ML engine335may group commands based on (e.g., conditioned on or in response to determining) a write distance associated with the commands. A write distance may refer to the amount of time in between consecutive write operations for a set of data or a memory address.

In some examples, the ML engine may group commands based on (e.g., conditioned on or in response to determining) a read turnaround timing associated with the commands. A read turnaround timing may refer to an amount of time in between changing the direction of a data bus (e.g., a bi-directional data bus) from a write direction (in which data is communicated from the interface controller315) to a read direction (in which data is communicated to the interface controller315). In some examples, the ML engine may group commands based on (e.g., conditioned on or in response to determining) a write turnaround timing associated with the commands. A write turnaround timing may refer to an amount of time in between changing the direction of a data bus (e.g., a bi-directional data bus) from a read direction to a write direction.

In some examples, the ML engine may group commands based on (e.g., conditioned on or in response to determining) a reuse distance associated with the commands. A reuse distance may refer to an amount of time in between the use and re-use of the same data location (e.g., memory address). In some examples, the ML engine may group commands based on (e.g., conditioned on or in response to determining) an eviction distance or eviction frequency associated with the commands. An eviction distance may refer to an amount of time a set of data is stored in the volatile memory320(e.g., at a particular address) before undergoing an eviction procedure. Alternatively, the eviction distance may refer to an amount of time in between evictions of a memory address of the volatile memory320. An eviction frequency may refer to a quantity of times a set of data or a memory address undergoes an eviction procedure within a predetermined amount of time. In some examples, the eviction distance or the eviction frequency may be based on (e.g., correspond to or in response to determining) the set and/or way associated with one or more commands. In some examples, the ML engine335may predict address and victim pages based on or in response to determining address patterns. In some examples, the ML engine335may group commands based on a page open and close timing associated with the commands. A page open and close timing may refer to the amount of time an opened page remains open (e.g., the amount of time between opening a page and closing the page).

Although described with reference to various characteristics, the ML engine335may group commands based on other characteristics not described herein.

In the field mode, the ML engine335may use information learned during the training mode (or learned earlier during the field mode or a combination thereof) to generate various commands for the memory subsystem310. For instance, the ML engine335may use information and/or one or more models from the training mode to determine that one or more commands from the host device305are associated with a particular operation. Accordingly, the ML engine335may generate one or more commands for the TCQ circuitry340to predictively facilitate or effectuate the operation (e.g., before implicitly or explicitly prompted to do so by one or more additional commands from the host device305). Thus, the ML engine335may determine that one or more commands are associated with a particular operation or procedure using cluster-based pattern information. In some examples, the ML engine335may group commands in the field mode based on or in response to determining one or more shared characteristics and use the grouped commands (or “clusters”) to predict one or more operations of the memory subsystem310.

In some examples, the ML engine335may determine that one or more commands from the host device305are associated with a given operation, such as a pre-fetch operation, in which data is retrieved from the volatile memory320or the non-volatile memory325before the host device305requests the data. Accordingly, the ML engine335may generate one or more commands associated with (e.g., for effectuating) the pre-fetch operation and may communicate the one or more commands to the TCQ circuitry340for processing (e.g., storage and distribution). In some examples, the ML engine335may determine that one or more commands from the host device305are associated with an eviction operation in which data from the volatile memory320is stored in the non-volatile memory325. Accordingly, the ML engine335may generate one or more commands associated with (e.g., for effectuating) the eviction operation and may communicate the one or more commands to the TCQ circuitry340for processing.

In some examples, the ML engine335may determine that one or more commands from the host device305are associated with opening (e.g., activating) or closing (e.g., deactivating) a page in the non-volatile memory325or the volatile memory320. Accordingly, the ML engine335may generate one or more commands associated with (e.g., for effectuating) the page open or page close operation and may communicate the one or more commands to the TCQ circuitry340for processing.

In some examples, the ML engine335may determine that one or more commands from the host device305are associated with a cache hit or cache miss. Accordingly, the ML engine335may generate one or more commands associated with (e.g., for effectuating) operations associated with the cache hit or cache miss and may communicate the one or more commands to the TCQ circuitry340for processing. In some examples, the ML engine335may determine that one or more commands from the host device305are associated with a write-back operation or a write-through operation. Accordingly, the ML engine335may generate one or more commands associated with (e.g., for effectuating) the write-back or write-through procedure and may communicate the one or more commands to the TCQ circuitry340for processing.

In some examples, the ML engine335may determine that one or more commands from the host device305are associated with a power mode for the volatile memory320or the non-volatile memory325. For example, the ML engine335may determine that the one or more commands from the host device305are associated with a low power mode for the volatile memory320, the non-volatile memory325, or both. Accordingly, the ML engine335may generate a power mode command that indicates the low power mode and communicate the power mode command to the mode controller345. The mode controller345may be made up of or include a first mode controller configured to control the power mode of the non-volatile memory325and a second mode controller configured to control the power mode of the volatile memory320. Thus, the ML engine335may use machine learning to predict power mode transitions, which may allow the memory subsystem310to conserve power.

Although described with reference to various operations herein, the ML engine335may generate commands for other types of operations not explicitly detailed herein.

Thus, by leveraging machine learning, the interface controller315may generate commands in anticipation of expected operations, which may reduce system latency and power consumption.

FIG.4illustrates an example of a process flow400that supports machine learning for a multi-memory system in accordance with examples as disclosed herein. Process flow400may be implemented by a memory subsystem110or an interface controller115as described with reference toFIG.1, a memory subsystem200or an interface controller202as described with reference toFIG.2, or a memory subsystem310or an interface controller315as described with reference toFIG.3. However, other types of devices or components may implement process flow400. The process flow400may illustrate the operations of a device that uses machine learning to generate commands.

For ease of reference, the process flow400is described with reference to a device. For example, aspects of the process flow400may be implemented by a device that includes a volatile memory and a non-volatile memory. Additionally or alternatively, aspects of the process flow400may be implemented as instructions stored in memory (e.g., firmware stored in the volatile memory120or the non-volatile memory125or both). For example, the instructions, if executed by a controller, may cause the controller to perform the operations of the process flow400.

At405, machine learning may be performed. For example, the ML engine335may perform machine learning in a first mode, such as a training mode. In the training mode, the ML engine335may receive sequences of commands from the host device305and detect operational patterns associated with the commands by grouping the commands based on (e.g., conditioned on, in accordance with) one or more shared characteristics. The sequences of commands may be for training the ML engine335and may be unassociated with user data. In some examples, the ML engine335may build one or more models or algorithms based on (e.g., in response to) the training. At410, a field mode may be entered. For example, the ML engine335may enter the field mode. During the field mode, commands associated with user data may be received from the host device305and the ML engine335may process the commands based on (e.g., in response to) machine learning information determined during the training mode.

At415, a first command may be received. For example, the decoder330may receive the first command (potentially among/with other commands) from the host device305. At420, the first command (potentially among/with other commands) may be communicated to the TCQ circuitry340and the ML engine335. For example, the decoder330may communicate the first command to the TCQ circuitry340and the ML engine335. In some examples, the first command may be communicated to the TCQ circuitry340and the ML engine335in parallel (e.g., at the same time, concurrently, at partially overlapping times). In some examples, the decoder330may decode the first command before communicating the first command to the TCQ circuitry340and the ML engine335.

At425, a second command may be generated. For example, the ML engine335may generate the second command based on (e.g., in response to) the first command (and potentially other commands) and information learned during the training mode (e.g., based on one or more models or algorithms built during the training mode). The second command may be associated with one or more memory operations (e.g., a page operation, an eviction operation, a pre-fetch operation). At430, the second command may be communicated to the TCQ circuitry340. For example, the ML engine335may communicate the second command to the TCQ circuitry340. At435, a power mode command may be generated. For example, the ML engine335may generate the power command based on or in response to the first command (and potentially other commands) and information learned during the training mode. The power mode command may be for the volatile memory320, the non-volatile memory325, or both.

At440, the second command may be communicated. For example, the ML engine335may communicate the second command to the TCQ circuitry340. The TCQ circuitry340may distribute the second command to an appropriate component of the interface controller315. At445, the power mode command may be communicated. For example, the ML engine335may communicate the power mode command to the mode controller345. If the power mode command is for the volatile memory320, the ML engine335may communicate the power mode command to a mode controller for the volatile memory320. If the power mode is for the non-volatile memory325, the ML engine335may communicate the power mode command to a mode controller for the non-volatile memory325. Based on or in response to the power mode command, the mode controller345may cause the volatile memory320, the non-volatile memory325, or both, to enter the power mode indicated by the third command.

Alternative examples of the foregoing may be implemented, where some operations partially overlap, are performed in a different order than described, are performed in parallel, or are not performed at all. In some cases, operations may include additional features not mentioned herein, or further operations may be added. Additionally, certain operations may be performed multiple times or certain combinations of operations may repeat or cycle.

FIG.5shows a block diagram500of a memory device520that supports machine learning for a multi-memory system in accordance with examples as disclosed herein. The memory device520may be an example of aspects of a memory device as described with reference toFIGS.1through4. The memory device520, or various components thereof, may be an example of means for performing various aspects of machine learning for a multi-memory system as described herein. For example, the memory device520may include a decoder525, an ML engine530, TCQ circuitry535, or any combination thereof. Each of these components may communicate, directly or indirectly, with one another (e.g., via one or more buses).

The decoder525may be or include logic or circuitry capable of performing the functions described herein. In some examples, the decoder525may be an example of the decoder228as described with reference toFIG.2or the decoder330as described with reference toFIG.3. The ML engine530may be or include logic, circuitry, a controller, a processor, or other components capable of performing the functions described herein. In some examples, the ML engine530may be an example of the ML engine335as described with reference toFIG.3. The TCQ circuitry535may be or include buffers, logic, circuitry, a processor, a controller, or other components capable of performing the functions described herein. In some examples, the TCQ circuitry535may be an example of the command circuitry230as described with reference toFIG.2or the TCQ circuitry340described with reference toFIG.3.

The decoder525may be configured as or otherwise support a means for receiving, at an interface controller, a first command from a host device, the interface controller coupled with a non-volatile memory and a volatile memory. In some examples, the decoder525may be configured as or otherwise support a means for communicating the first command to a machine learning engine and to circuitry configured to store and manage commands for the non-volatile memory and the volatile memory. The ML engine530may be configured as or otherwise support a means for communicating a second command generated by the machine learning engine to the circuitry, the second command based at least in part on information determined by the machine learning engine during a training mode. In some examples, the machine learning engine includes an LSTM neural network, a GRU neural network, a transformer neural network, or a combination thereof.

In some examples, the ML engine530may be configured as or otherwise support a means for grouping, by the machine learning engine according to one or more shared characteristics, commands received from the host device during the training mode. In some examples, the ML engine530may be configured as or otherwise support a means for detecting, by the machine learning engine, one or more patterns associated with the commands based at least in part on grouping the commands, where the information determined by the machine learning engine is based at least in part on the one or more patterns.

In some examples, the one or more patterns include one or more patterns for operating the interface controller, the non-volatile memory, the volatile memory, or a combination thereof. In some examples, the one or more shared characteristics includes a read bandwidth, a write bandwidth, a read distance, a write distance, a page open and close timing, a read turnaround timing, a write turnaround timing, a reuse distance, an eviction frequency, or a combination thereof.

In some examples, the ML engine530may be configured as or otherwise support a means for determining, by the machine learning engine, a prefetch operation based at least in part on the first command and the information determined during the training mode, where the second command is associated with the prefetch operation and the prefetch operation includes retrieving data from the volatile memory or the non-volatile memory before the data is requested by the host device.

In some examples, the ML engine530may be configured as or otherwise support a means for determining, by the machine learning engine, an eviction operation based at least in part on the first command and the information determined during the training mode, where the second command is associated with the eviction operation and the eviction operation includes storing data from the volatile memory in the non-volatile memory.

In some examples, the ML engine530may be configured as or otherwise support a means for determining, by the machine learning engine, a page open operation or a page close operation based at least in part on the first command and the information determined during the training mode, where the second command is associated with the page open operation or the page close operation.

In some examples, the ML engine530may be configured as or otherwise support a means for determining, by the machine learning engine, a power mode for the non-volatile memory or the volatile memory based at least in part on the first command and the information determined during the training mode. In some examples, the ML engine530may be configured as or otherwise support a means for communicating, by the machine learning engine, a third command associated with the power mode to logic that is configured to control the power mode of the volatile memory, the power mode of the non-volatile memory, or both.

In some examples, the interface controller includes a command decoder configured to concurrently communicate the first command to the machine learning engine and the circuitry. In some examples, the TCQ circuitry535may be configured as or otherwise support a means for storing the second command received from the machine learning engine. In some examples, the TCQ circuitry535may be configured as or otherwise support a means for communicating the second command to a scheduling component for the non-volatile memory or the volatile memory.

In some examples, the first command is received during a field mode in which the apparatus operates on user data. In some examples, first sequences of commands for training the machine learning engine are received during the training mode and second sequences of commands associated with user data are received during the field mode. In some examples, the second command is generated based at least in part on information determined by the machine learning engine during the field mode.

FIG.6shows a flowchart illustrating a method600that supports machine learning for a multi-memory system in accordance with examples as disclosed herein. The operations of method600may be implemented by a memory device or its components as described herein. For example, the operations of method600may be performed by a memory device as described with reference toFIGS.1through5. In some examples, a memory device may execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally or alternatively, the memory device may perform aspects of the described functions using special-purpose hardware.

At605, the method may include receiving, at an interface controller, a first command from a host device, the interface controller coupled with a non-volatile memory and a volatile memory. The operations of605may be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of605may be performed by a decoder525as described with reference toFIG.5.

At610, the method may include communicating the first command to a machine learning engine and to circuitry configured to store and manage commands for the non-volatile memory and the volatile memory. The operations of610may be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of610may be performed by a decoder525as described with reference toFIG.5.

At615, the method may include communicating a second command generated by the machine learning engine to the circuitry, the second command based at least in part on information determined by the machine learning engine during a training mode. The operations of615may be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of615may be performed by an ML engine530as described with reference toFIG.5.

In some examples, an apparatus as described herein may perform a method or methods, such as the method600. The apparatus may include, features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for receiving, at an interface controller, a first command from a host device, the interface controller coupled with a non-volatile memory and a volatile memory, communicating the first command to a machine learning engine and to circuitry configured to store and manage commands for the non-volatile memory and the volatile memory, and communicating a second command generated by the machine learning engine to the circuitry, the second command based at least in part on information determined by the machine learning engine during a training mode.

In some examples of the method600and the apparatus described herein, the machine learning engine includes an LSTM neural network, a GRU neural network, a transformer neural network, or a combination thereof. Some examples of the method600and the apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for grouping, by the machine learning engine according to one or more shared characteristics, commands received from the host device during the training mode and detecting, by the machine learning engine, one or more patterns associated with the commands based at least in part on grouping the commands, where the information determined by the machine learning engine may be based at least in part on the one or more patterns.

In some examples of the method600and the apparatus described herein, the one or more patterns include one or more patterns for operating the interface controller, the non-volatile memory, the volatile memory, or a combination thereof. In some examples of the method600and the apparatus described herein, the one or more shared characteristics includes a read bandwidth, a write bandwidth, a read distance, a write distance, a page open and close timing, a read turnaround timing, a write turnaround timing, a reuse distance, an eviction frequency, or a combination thereof.

Some examples of the method600and the apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for determining, by the machine learning engine, a prefetch operation based at least in part on the first command and the information determined during the training mode, where the second command may be associated with the prefetch operation and the prefetch operation includes retrieving data from the volatile memory or the non-volatile memory before the data may be requested by the host device.

Some examples of the method600and the apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for determining, by the machine learning engine, an eviction operation based at least in part on the first command and the information determined during the training mode, where the second command may be associated with the eviction operation and the eviction operation includes storing data from the volatile memory in the non-volatile memory.

Some examples of the method600and the apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for determining, by the machine learning engine, a page open operation or a page close operation based at least in part on the first command and the information determined during the training mode, where the second command may be associated with the page open operation or the page close operation.

Some examples of the method600and the apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for determining, by the machine learning engine, a power mode for the non-volatile memory or the volatile memory based at least in part on the first command and the information determined during the training mode and communicating, by the machine learning engine, a third command associated with the power mode to logic that may be configured to control the power mode of the volatile memory, the power mode of the non-volatile memory, or both.

In some examples of the method600and the apparatus described herein, the interface controller includes a command decoder configured to concurrently communicate the first command to the machine learning engine and the circuitry. Some examples of the method600and the apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for storing the second command received from the machine learning engine and communicating the second command to a scheduling component for the non-volatile memory or the volatile memory.

In some examples of the method600and the apparatus described herein, the first command may be received during a field mode in which the apparatus operates on user data. In some examples of the method600and the apparatus described herein, first sequences of commands for training the machine learning engine may be received during the training mode and second sequences of commands associated with user data may be received during the field mode.

In some examples of the method600and the apparatus described herein, the second command may be generated based at least in part on information determined by the machine learning engine during the field mode. It should be noted that the methods described herein describe possible implementations, and that the operations and the steps may be rearranged or otherwise modified and that other implementations are possible. Further, portions from two or more of the methods may be combined.

An apparatus is described. The apparatus may include a non-volatile memory, a volatile memory configured to operate as a cache for the non-volatile memory, and an interface controller coupled with the non-volatile memory and the volatile memory, the interface controller configured to cause the apparatus to receive a first command from a host device, communicate the first command to a machine learning engine and to circuitry configured to store and manage commands for the non-volatile memory and the volatile memory, and communicate a second command generated by the machine learning engine to the circuitry, the second command based at least in part on information determined by the machine learning engine during a training mode.

In some examples of the apparatus, the machine learning engine includes an LSTM neural network, a GRU neural network, a transformer neural network, or a combination thereof. In some examples of the apparatus, the machine learning engine may be configured to group, according to one or more shared characteristics, commands received from the host device during the training mode and detect one or more patterns associated with the commands based at least in part on grouping the commands, where the information determined by the machine learning engine may be based at least in part on the one or more patterns.

In some examples of the apparatus, the one or more patterns include one or more patterns for operating the apparatus. In some examples of the apparatus, the one or more shared characteristics includes a read bandwidth, a write bandwidth, a read distance, a write distance, a page open and close timing, a read turnaround timing, a write turnaround timing, a reuse distance, an eviction frequency, or a combination thereof.

In some examples, the apparatus may include determine a prefetch operation based at least in part on the first command and the information determined during the training mode, where the second command may be associated with the prefetch operation and the prefetch operation includes retrieving data from the volatile memory or the non-volatile memory before the data may be requested by the host device.

In some examples, the apparatus may include determine an eviction operation based at least in part on the first command and the information determined during the training mode, where the second command may be associated with the eviction operation and the eviction operation includes storing data from the volatile memory in the non-volatile memory.

In some examples, the apparatus may include determine a page open operation or a page close operation based at least in part on the first command and the information determined during the training mode, where the second command may be associated with the page open operation or the page close operation.

In some examples, the apparatus may include determine a power mode for the non-volatile memory or the volatile memory based at least in part on the first command and the information determined during the training mode and communicate a third command associated with the power mode to logic that may be configured to control the power mode of the volatile memory, the power mode of the non-volatile memory, or both.

In some examples of the apparatus, the interface controller includes a command decoder configured to concurrently communicate the first command to the machine learning engine and the circuitry. In some examples, the apparatus may include store the second command received from the machine learning engine and communicate the second command to a scheduling component for the non-volatile memory or the volatile memory.

In some examples of the apparatus, the first command may be received during a field mode in which the apparatus operates on user data. In some examples of the apparatus, the first sequences of commands for training the machine learning engine may be received during the training mode and second sequences of commands associated with user data may be received during the field mode. In some examples of the apparatus, the second command may be generated based at least in part on information determined by the machine learning engine during the field mode.

Another apparatus is described. The apparatus may include a non-volatile memory, a volatile memory configured to operate as a cache for the non-volatile memory, and an interface controller coupled with the non-volatile memory and the volatile memory, the interface controller including circuitry configured to store and manage commands for the non-volatile memory and the volatile memory, a command decoder configured to receive a first command from a host device and communicate the first command to the circuitry and to a machine learning engine, and the machine learning engine configured to generate a second command based at least in part on information determined by the machine learning engine during a training mode and configured to communicate the second command to the circuitry.

In some examples of the apparatus, the machine learning engine may be configured to group, according to one or more shared characteristics, commands received from the host device during the training mode and detect one or more patterns associated with the commands based at least in part on grouping the commands, where the information determined by the machine learning engine may be based at least in part on the one or more patterns.

In some examples, the apparatus may include determine a prefetch operation based at least in part on the first command and the information determined during the training mode, where the second command may be associated with the prefetch operation and the prefetch operation includes retrieving data from the volatile memory or the non-volatile memory before the data may be requested by the host device.

In some examples, the apparatus may include determine an eviction operation based at least in part on the first command and the information determined during the training mode, where the second command may be associated with the eviction operation and the eviction operation includes storing data from the volatile memory in the non-volatile memory. In some examples, the apparatus may include determine a page open operation or a page close operation based at least in part on the first command and the information determined during the training mode, where the second command may be associated with the page open operation or the page close operation.

In some examples, the apparatus may include determine a power mode for the non-volatile memory or the volatile memory based at least in part on the first command and the information determined during the training mode and communicate a third command associated with the power mode to logic configured to control the power mode of the volatile memory, the power mode of the non-volatile memory, or both.

Another apparatus is described. The apparatus may include circuitry configured to store and manage commands for a non-volatile memory and a volatile memory operated as a cache for the non-volatile memory, a command decoder configured to receive a first command from a host device and communicate the first command to the circuitry and to a machine learning engine, and the machine learning engine configured to generate a second command based at least in part on information determined by the machine learning engine during a training mode and configured to communicate the second command to the circuitry.

In some examples of the apparatus, the machine learning engine may be configured to group, according to one or more shared characteristics, commands received from the host device during the training mode and detect one or more patterns associated with the commands based at least in part on grouping the commands, where the information determined by the machine learning engine may be based at least in part on the one or more patterns. In some examples, the apparatus may include determine a memory operation based at least in part on the first command and the information determined during the training mode, where the second command may be associated with the memory operation.

A protocol may define one or more communication procedures and one or more communication parameters supported for use by a device or component. For example, a protocol may define various operations, a timing and a frequency for those operations, a meaning of various commands or signals or both, one or more addressing scheme(s) for one or more memories, a type of communication for which pins are reserved, a size of data handled at various components such as interfaces, a data rate supported by various components such as interfaces, or a bandwidth supported by various components such as interfaces, among other parameters and metrics, or any combination thereof. Use of a shared protocol may enable interaction between devices because each device may operate in a manner expected, recognized, and understood by another device. For example, two devices that support the same protocol may interact according to the policies, procedures, and parameters defined by the protocol, whereas two devices that support different protocols may be incompatible.

To illustrate, two devices that support different protocols may be incompatible because the protocols define different addressing schemes (e.g., different quantities of address bits). As another illustration, two devices that support different protocols may be incompatible because the protocols define different transfer procedures for responding to a single command (e.g., the burst length or quantity of bytes permitted in response to the command may differ). Merely translating a command to an action should not be construed as use of two different protocols. Rather, two protocols may be considered different if corresponding procedures or parameters defined by the protocols vary. For example, a device may be said to support two different protocols if the device supports different addressing schemes, or different transfer procedures for responding to a command.

As used herein, the term “substantially” means that the modified characteristic (e.g., a verb or adjective modified by the term substantially) need not be absolute but is close enough to achieve the advantages of the characteristic. As used herein, the term “concurrently” means that the described actions or phenomena occur during durations that at least partially overlap in time, that can occur at substantially the same time or be offset in time.