High-performance static programmable logic array

A high-performance programmable logic array (PLA) includes an AND plane that is initialized when a reset signal is activated and that evaluates a plurality of input signals when the reset signal is inactivated; and or OR plane that receives output signals of the AND plane, that is disabled when one of the output signals is activated, and that evaluates the rest of the output signals of the AND plane to output a final result signal when the one of the output signals of the AND plane is inactivated. The PLA uses a reset signal as a driving signal, instead of a clock signal. Accordingly, it is possible to realize a PLA with both low power consumption and high operation speed.

CROSS-REFERENCE TO RELATED PATENT APPLICATION

This application claims the benefit of Korean Patent Application No. 10-2006-0016684, filed on Feb. 21, 2006, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

BACKGROUND OF THE INVENTION

1. Technical Field

The present disclosure relates to a programmable logic array (PLA), and more particularly, to a high-performance static PLA.

2. Discussion of the Related Art

A programmable logic array (PLA) is generally used in an instruction decoder block of a processor or a control block of a finite state machine (FSM), which is typically complex, in order to increase an operation speed or reduce a chip area. The PLA generally includes an AND plane and an OR plane, which are connected to each other in series.

The PLA is classified into two types: a dynamic PLA and a static PLA. An example of the dynamic PLA is disclosed in U.S. Pat. No. 4,894,564, and an example of the static PLA is disclosed in U.S. Pat. No. 4,728,827. In general, while the dynamic PLA has a high operation speed, it has a high power consumption and a large amount of noise because the dynamic PLA is operated in synchronization with a clock signal having a short duration. In contrast, the static PLA has a low power consumption, but also has a low operation speed.

SUMMARY OF THE INVENTION

Accordingly, exemplary embodiments of the present invention provide a high-performance static programmable logic array (PLA) having a high operation speed and a low power consumption.

According to an exemplary embodiment of the present invention, there is provided a programmable logic array including an AND plane that is initialized when a reset signal is activated and that evaluates a plurality of input signals when the reset signal is inactivated; and an OR plane that receives a plurality of output signals of the AND plane, that is disabled when one of the output signals of the AND plane is activated, and that evaluates the rest of the output signals of the AND plane to output a final result signal when one of the output signals of the AND plane is inactivated.

The AND plane may include a plurality of product term lines that are selected by selection input signals, that are disabled when the reset signal is activated, and that evaluate the plurality of input signals to output the output signals when the reset signal is inactivated.

Each of the product term lines may include an AND plane evaluating circuit and a plurality of pull-down transistors. The AND plane evaluating circuit can receive a result signal obtained by a logic operation between each of the selection input signals and the reset signal, can initialize an output signal of an output line when the result signal is in a first logic state, and can evaluate states of the input signals when the result signal is in a second logic state. The plurality of pull-down transistors can be connected in parallel to the output line of the AND plane evaluating circuit and can be controlled by the input signals, respectively.

The OR plane can include an OR plane evaluating circuit, a plurality of pull-down transistors, and an inverter. The OR plane evaluating circuit can receive the one of the output signals of the AND plane, can disable a signal of an output port of the OR plane evaluating circuit when the one of the output signals of the AND plane is inactivated, and can evaluate the states of the other output signals when the one of the output signals is inactivated. The plurality of pull-down transistors can be connected to the output port of the OR plane evaluating circuit in parallel and can be controlled by the other output signals of the AND plane, respectively. The inverter can invert the signal of the output port of the OR plane evaluating circuit to output the final result signal.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

The attached drawings illustrating exemplary embodiments of the present invention are referred to in order to gain a sufficient understanding of the present invention, the merits thereof, and the objectives accomplished by the implementation of the present invention.

Hereinafter, the present invention will be described in detail by explaining exemplary embodiments of the invention with reference to the attached drawings. Like reference numerals in the drawings denote like elements.FIG. 1is a block diagram of a high-performance static programmable logic array (PLA) according to an exemplary embodiment of the present invention.

Referring toFIG. 1, the PLA according to the exemplary embodiment of the present invention includes an AND plane11and an OR plane13.

The PLA according to the exemplary embodiment of the present invention uses a reset signal RESET instead of a clock signal. The AND plane11is initialized when the reset signal RESET is activated (logic high), and evaluates a plurality of input signals AIto APwhen the reset signal RESET is inactivated (logic low). The activation of the reset signal RESET indicates a reset state and the inactivation of the reset signal RESET indicates a reset release state.

The OR plane13receives output signals F1to Fnof the AND plane11, is disabled when an output signal F1is activated (logic high), and evaluates the other output signals F2to Fnto output a final result signal OUT when the output signal F1is inactivated (logic low).

The AND plane11includes a plurality of product term lines111to11n.The product term lines111to11nare selected by selection input signals Akto Am, respectively. The product term lines111to11nare disabled when the reset signal RESET is activated and input signals AIto APare evaluated to output the output signals F1to Fnwhen the reset signal RESET is inactivated.

More specifically, each of the product term lines111to11nincludes an AND plane evaluating circuit120and a plurality of pull-down transistors N11to N1n. The AND plane evaluating circuit120receives a result signal NRESET obtained by a NOR operation between each of the selection input signals Akto Amand the reset signal RESET through each of NOR gates NR1to NRn.

The AND plane evaluating circuit120initializes the output signal F1based on a logic low state of the result signal NRESET, that is, when the reset signal RESET is activated to a logic high level, and evaluates a state of each of the input signals AIto APin a logic high state of the result signal NRESET, that is, when the reset signal RESET is inactivated to a logic low level. The detailed configuration and operation of the AND plane evaluating circuit120will be described below with respect toFIGS. 2 and 4.

The pull-down transistors N11to N1nare connected to an output line of the AND plane evaluating circuit120in parallel and controlled by the input signals AIto AP, respectively. The pull-down transistors N11to N1nset the output line of the AND plane evaluating circuit120to a logic low level in response to the input signals AIto AP, respectively.

The OR plane13includes an OR plane evaluating circuit130, a plurality of pull-down transistors N31to N3n,and an inverter131. The OR plane evaluating circuit130receives the output signal F1of the AND plane11, disables a signal of an output port XO when the output signal F1is activated (logic high) and evaluates the states of the output signals F2to Fnwhen the output signal F1is inactivated (logic low). The detailed configuration of the OR plane evaluating circuit130will be described below with reference toFIG. 3.

The pull-down transistors N31to N3nare connected to the output port of the OR plane evaluating circuit130in parallel and controlled by the output signals F2to Fn, respectively. The pull-down transistors N31to N3nset the output port of the OR plane evaluating circuit130to a logic low level in response to the output signals F2to Fn, respectively.

The inverter131inverts the signal of the output port XO of the OR plane evaluating circuit130and outputs the final result signal OUT.

FIG. 2illustrates a detailed circuit diagram of the AND plane evaluating circuit120shown inFIG. 1, according to an exemplary embodiment of the present invention.

Referring toFIG. 2, the AND plane evaluating circuit120includes a first inverter IV1, a second inverter IV2, a NAND gate NA1, and MOS transistors P1, P2, P3, M1, and M2.

In the exemplary embodiment of the present invention, MOS transistors P1, P2, and P3are PMOS transistors and MOS transistors M1and M2are NMOS transistors.

The first inverter IV1inverts the result signal NRESET obtained by the NOR operation between each of the selection input signals Akto Amand the reset signal RESET. The NAND gate NA1performs a NAND operation between the result signal NRESET and a signal at an internal node W2, and the second inverter IV2inverts an output signal EVAL1of the NAND gate NA1.

The PMOS transistor P1is connected between a first power supply voltage, that is, a power supply voltage VDD, and an output line Fi, and is controlled by the output signal EVAL1of the NAND gate NA1. The NMOS transistor M2is connected between a second power supply source voltage, that is, a ground voltage VSS, and the output line Fi and is controlled by an output signal PG1of the first inverter IV1. The NMOS transistor M1is connected between the internal node W2and the output line Fi and is controlled by an output signal T1of the second inverter IV2.

The PMOS transistor P3is connected between the power supply voltage VDD and the internal node W2and is controlled by the output signal T1of the second inverter IV2. The PMOS transistor P2is connected between the power supply voltage VSS and the internal node W2and is controlled by the result signal NRESET.

FIG. 3illustrates a detailed circuit diagram of the OR plane evaluating circuit130shown inFIG. 1, according to an exemplary embodiment of the present invention.

Referring toFIG. 3, the OR plane evaluating circuit130includes a first inverter IV11, a second inverter IV21, a NAND gate NA11, MOS transistors P11, P21, and P31, and MOS transistors M11and M21.

In the exemplary embodiment of the present invention, MOS transistors P11, P21, and P31are PMOS transistors and MOS transistors M11and M21are NMOS transistors. The inverter IV11receives and inverts the output signal Fi of the AND plane evaluating circuit120. The NAND gate NA11performs a NAND operation between an output signal of the inverter IV11and a signal of an internal node W21, and the inverter IV21inverts an output signal EVAL11of the NAND gate NA11.

The PMOS transistor P11is connected between the first power supply source voltage, that is, the power supply voltage VDD, and the output port XO and is controlled by the output signal EVAL11of the NAND gate NA11. The NMOS transistor M21is connected between the second power supply source voltage, that is, the ground voltage VSS, and the output port XO and is controlled by the output signal Fi of the AND plane evaluating circuit120. The NMOS transistor M11is connected between the internal node W21and the output port XO, and controlled by an output signal T11of the inverter IV21.

The PMOS transistor P31is connected between the power supply voltage VDD and the internal node W21and is controlled by the output signal T11of the inverter IV21. The PMOS transistor P2is connected between the power supply voltage VSS and the internal node W21and is controlled by the output signal Fi of the AND plane evaluating circuit120.

FIG. 4illustrates an operation timing diagram of the AND plane evaluating circuit120shown inFIG. 2.

First, when the reset signal RESET is activated to the logic high level (at this time, it is assumed that the selection input signal Akshown inFIG. 1is at a logic low level), the result signal NRESET, which is obtained by the NOR operation between the selection input signal Akand the reset signal RESET, is in the logic low level. Accordingly, the output signal EVAL1of the NAND gate NA1is in the logic high level and, thus, the PMOS transistor P1is turned off.

The output signal T1of the inverter IV2is at the logic low level, the PMOS transistor P3is turned on, and the internal node W2is pre-charged to the logic high level. At this time, the NMOS transistor M1is turned off by the signal T1at the logic low level. Since the output signal PG1of the inverter IV1is at the logic high level, the NMOS transistor M2is turned on, and thus, the output line Fi is set to the logic low level.

When the reset signal RESET is inactivated to the logic low level (at this time, it is assumed that the selection input signal Akshown inFIG. 1is at a logic low level), the result signal NRESET, which is obtained by the NOR operation between the selection input signal Akand the reset signal RESET, is at the logic high level. At this time, since the internal node W2is pre-charged to the logic high level, the output signal EVAL1of the NAND gate NA1is at the logic low level and thus, the PMOS transistor P1is turned on. As a result, the output line Fi is at the logic high level.

At this time, the PMOS transistor P2is turned off. Since the output signal T1of the inverter IV2is at the logic high level and the output signal PG1of the inverter IV1is at the logic low level, the PMOS transistor P3and the NMOS transistor M2are turned off and the NMOS transistor M1is turned on.

At this state, when at least one of the input signals A1to Ap(seeFIG. 1) is applied to the pull-down transistors N11to N1nconnected to the output line Fi of the AND plane evaluating circuit120and is at the logic high level, the output line Fi is set to the logic low level. Accordingly, the NMOS transistor M1is turned on and the internal node W2is at the logic low level. As a result, the output signal EVAL1of the NAND gate NA1is at the logic high level again.

When all the input signals AIto APare applied to the pull-down transistors N11to N1nand are at the logic low level, all the pull-down transistors N11to N1nare turned off and the output line Fi is maintained constant at the logic high level.

As described above, the AND plane evaluating circuit120initializes the output line Fi and sets the output line Fi to the logic low level based on the logic low state of the result signal NRESET, that is, when the reset signal RESET is activated to the logic high level, and evaluates the states of the input signals AIto APin the logic high state of the result signal NRESET, that is, when the reset signal RESET is inactivated to the logic low level.

FIG. 5illustrates an operation timing diagram of the OR plane evaluating circuit130ofFIG. 3. A signal Fi shown inFIG. 5denotes one of the signals F2to Fn(seeFIG. 1) applied to the pull-down transistors N31to N3nconnected to the output port XO of the OR plane evaluating circuit130. The operation of the OR plane evaluating circuit130is substantially the same as that of the AND plane evaluating circuit120and, thus, a detailed description of the operation of the OR plane evaluating circuit130will be omitted.

As described above, the PLA according to exemplary embodiments of the present invention uses the reset signal RESET as a driving signal, instead of a clock signal having a low period or a high frequency. Accordingly, it is possible to realize a PLA with both low power consumption and high-speed operation. In addition, when the reset signal RESET is activated (reset state), the PLA according to exemplary embodiments of the present invention is held in a disabled state (initialized state) and, thus, the power consumption of the PLA due to current leakage is minimal. When the reset signal RESET is inactivated (reset release state), the PLA according to the present invention is operated depending on the selection of the input signals Akto Am.

As described above, according to the PLA provided by an exemplary embodiment of the present invention, it is possible to realize a PLA with both low power consumption and high operation speed.